35 #ifndef __ALT_SOCAL_I2C_H__
36 #define __ALT_SOCAL_I2C_H__
137 #define ALT_I2C_IC_CON_MASTER_MODE_E_DISABLED 0x0
143 #define ALT_I2C_IC_CON_MASTER_MODE_E_ENABLED 0x1
146 #define ALT_I2C_IC_CON_MASTER_MODE_LSB 0
148 #define ALT_I2C_IC_CON_MASTER_MODE_MSB 0
150 #define ALT_I2C_IC_CON_MASTER_MODE_WIDTH 1
152 #define ALT_I2C_IC_CON_MASTER_MODE_SET_MSK 0x00000001
154 #define ALT_I2C_IC_CON_MASTER_MODE_CLR_MSK 0xfffffffe
156 #define ALT_I2C_IC_CON_MASTER_MODE_RESET 0x1
158 #define ALT_I2C_IC_CON_MASTER_MODE_GET(value) (((value) & 0x00000001) >> 0)
160 #define ALT_I2C_IC_CON_MASTER_MODE_SET(value) (((value) << 0) & 0x00000001)
205 #define ALT_I2C_IC_CON_SPEED_E_STANDARD 0x1
211 #define ALT_I2C_IC_CON_SPEED_E_FAST 0x2
217 #define ALT_I2C_IC_CON_SPEED_E_HIGH 0x3
220 #define ALT_I2C_IC_CON_SPEED_LSB 1
222 #define ALT_I2C_IC_CON_SPEED_MSB 2
224 #define ALT_I2C_IC_CON_SPEED_WIDTH 2
226 #define ALT_I2C_IC_CON_SPEED_SET_MSK 0x00000006
228 #define ALT_I2C_IC_CON_SPEED_CLR_MSK 0xfffffff9
230 #define ALT_I2C_IC_CON_SPEED_RESET 0x2
232 #define ALT_I2C_IC_CON_SPEED_GET(value) (((value) & 0x00000006) >> 1)
234 #define ALT_I2C_IC_CON_SPEED_SET(value) (((value) << 1) & 0x00000006)
272 #define ALT_I2C_IC_CON_IC_10BITADDR_SLAVE_E_ADDR_7BITS 0x0
278 #define ALT_I2C_IC_CON_IC_10BITADDR_SLAVE_E_ADDR_10BITS 0x1
281 #define ALT_I2C_IC_CON_IC_10BITADDR_SLAVE_LSB 3
283 #define ALT_I2C_IC_CON_IC_10BITADDR_SLAVE_MSB 3
285 #define ALT_I2C_IC_CON_IC_10BITADDR_SLAVE_WIDTH 1
287 #define ALT_I2C_IC_CON_IC_10BITADDR_SLAVE_SET_MSK 0x00000008
289 #define ALT_I2C_IC_CON_IC_10BITADDR_SLAVE_CLR_MSK 0xfffffff7
291 #define ALT_I2C_IC_CON_IC_10BITADDR_SLAVE_RESET 0x1
293 #define ALT_I2C_IC_CON_IC_10BITADDR_SLAVE_GET(value) (((value) & 0x00000008) >> 3)
295 #define ALT_I2C_IC_CON_IC_10BITADDR_SLAVE_SET(value) (((value) << 3) & 0x00000008)
345 #define ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_E_ADDR_7BITS 0x0
351 #define ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_E_ADDR_10BITS 0x1
354 #define ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_LSB 4
356 #define ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_MSB 4
358 #define ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_WIDTH 1
360 #define ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_SET_MSK 0x00000010
362 #define ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_CLR_MSK 0xffffffef
364 #define ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_RESET 0x1
366 #define ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_GET(value) (((value) & 0x00000010) >> 4)
368 #define ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_SET(value) (((value) << 4) & 0x00000010)
428 #define ALT_I2C_IC_CON_IC_RESTART_EN_E_DISABLED 0x0
434 #define ALT_I2C_IC_CON_IC_RESTART_EN_E_ENABLED 0x1
437 #define ALT_I2C_IC_CON_IC_RESTART_EN_LSB 5
439 #define ALT_I2C_IC_CON_IC_RESTART_EN_MSB 5
441 #define ALT_I2C_IC_CON_IC_RESTART_EN_WIDTH 1
443 #define ALT_I2C_IC_CON_IC_RESTART_EN_SET_MSK 0x00000020
445 #define ALT_I2C_IC_CON_IC_RESTART_EN_CLR_MSK 0xffffffdf
447 #define ALT_I2C_IC_CON_IC_RESTART_EN_RESET 0x1
449 #define ALT_I2C_IC_CON_IC_RESTART_EN_GET(value) (((value) & 0x00000020) >> 5)
451 #define ALT_I2C_IC_CON_IC_RESTART_EN_SET(value) (((value) << 5) & 0x00000020)
501 #define ALT_I2C_IC_CON_IC_SLAVE_DISABLE_E_SLAVE_ENABLED 0x0
507 #define ALT_I2C_IC_CON_IC_SLAVE_DISABLE_E_SLAVE_DISABLED 0x1
510 #define ALT_I2C_IC_CON_IC_SLAVE_DISABLE_LSB 6
512 #define ALT_I2C_IC_CON_IC_SLAVE_DISABLE_MSB 6
514 #define ALT_I2C_IC_CON_IC_SLAVE_DISABLE_WIDTH 1
516 #define ALT_I2C_IC_CON_IC_SLAVE_DISABLE_SET_MSK 0x00000040
518 #define ALT_I2C_IC_CON_IC_SLAVE_DISABLE_CLR_MSK 0xffffffbf
520 #define ALT_I2C_IC_CON_IC_SLAVE_DISABLE_RESET 0x1
522 #define ALT_I2C_IC_CON_IC_SLAVE_DISABLE_GET(value) (((value) & 0x00000040) >> 6)
524 #define ALT_I2C_IC_CON_IC_SLAVE_DISABLE_SET(value) (((value) << 6) & 0x00000040)
565 #define ALT_I2C_IC_CON_STOP_DET_IFADDRESSED_E_DISABLED 0x0
571 #define ALT_I2C_IC_CON_STOP_DET_IFADDRESSED_E_ENABLED 0x1
574 #define ALT_I2C_IC_CON_STOP_DET_IFADDRESSED_LSB 7
576 #define ALT_I2C_IC_CON_STOP_DET_IFADDRESSED_MSB 7
578 #define ALT_I2C_IC_CON_STOP_DET_IFADDRESSED_WIDTH 1
580 #define ALT_I2C_IC_CON_STOP_DET_IFADDRESSED_SET_MSK 0x00000080
582 #define ALT_I2C_IC_CON_STOP_DET_IFADDRESSED_CLR_MSK 0xffffff7f
584 #define ALT_I2C_IC_CON_STOP_DET_IFADDRESSED_RESET 0x0
586 #define ALT_I2C_IC_CON_STOP_DET_IFADDRESSED_GET(value) (((value) & 0x00000080) >> 7)
588 #define ALT_I2C_IC_CON_STOP_DET_IFADDRESSED_SET(value) (((value) << 7) & 0x00000080)
614 #define ALT_I2C_IC_CON_TX_EMPTY_CTRL_E_DISABLED 0x0
620 #define ALT_I2C_IC_CON_TX_EMPTY_CTRL_E_ENABLED 0x1
623 #define ALT_I2C_IC_CON_TX_EMPTY_CTRL_LSB 8
625 #define ALT_I2C_IC_CON_TX_EMPTY_CTRL_MSB 8
627 #define ALT_I2C_IC_CON_TX_EMPTY_CTRL_WIDTH 1
629 #define ALT_I2C_IC_CON_TX_EMPTY_CTRL_SET_MSK 0x00000100
631 #define ALT_I2C_IC_CON_TX_EMPTY_CTRL_CLR_MSK 0xfffffeff
633 #define ALT_I2C_IC_CON_TX_EMPTY_CTRL_RESET 0x0
635 #define ALT_I2C_IC_CON_TX_EMPTY_CTRL_GET(value) (((value) & 0x00000100) >> 8)
637 #define ALT_I2C_IC_CON_TX_EMPTY_CTRL_SET(value) (((value) << 8) & 0x00000100)
675 #define ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_E_DISABLED 0x0
681 #define ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_E_ENABLED 0x1
684 #define ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_LSB 9
686 #define ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_MSB 9
688 #define ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_WIDTH 1
690 #define ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_SET_MSK 0x00000200
692 #define ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_CLR_MSK 0xfffffdff
694 #define ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_RESET 0x0
696 #define ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_GET(value) (((value) & 0x00000200) >> 9)
698 #define ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_SET(value) (((value) << 9) & 0x00000200)
732 #define ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_E_DISABLED 0x0
738 #define ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_E_ENABLED 0x1
741 #define ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_LSB 10
743 #define ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_MSB 10
745 #define ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_WIDTH 1
747 #define ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_SET_MSK 0x00000400
749 #define ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_CLR_MSK 0xfffffbff
751 #define ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_RESET 0x0
753 #define ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_GET(value) (((value) & 0x00000400) >> 10)
755 #define ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_SET(value) (((value) << 10) & 0x00000400)
766 #define ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL_LSB 11
768 #define ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL_MSB 11
770 #define ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL_WIDTH 1
772 #define ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL_SET_MSK 0x00000800
774 #define ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL_CLR_MSK 0xfffff7ff
776 #define ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL_RESET 0x0
778 #define ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL_GET(value) (((value) & 0x00000800) >> 11)
780 #define ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL_SET(value) (((value) << 11) & 0x00000800)
791 #define ALT_I2C_IC_CON_RSVD_IC_CON_1_LSB 12
793 #define ALT_I2C_IC_CON_RSVD_IC_CON_1_MSB 15
795 #define ALT_I2C_IC_CON_RSVD_IC_CON_1_WIDTH 4
797 #define ALT_I2C_IC_CON_RSVD_IC_CON_1_SET_MSK 0x0000f000
799 #define ALT_I2C_IC_CON_RSVD_IC_CON_1_CLR_MSK 0xffff0fff
801 #define ALT_I2C_IC_CON_RSVD_IC_CON_1_RESET 0x0
803 #define ALT_I2C_IC_CON_RSVD_IC_CON_1_GET(value) (((value) & 0x0000f000) >> 12)
805 #define ALT_I2C_IC_CON_RSVD_IC_CON_1_SET(value) (((value) << 12) & 0x0000f000)
816 #define ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL_LSB 16
818 #define ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL_MSB 16
820 #define ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL_WIDTH 1
822 #define ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL_SET_MSK 0x00010000
824 #define ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL_CLR_MSK 0xfffeffff
826 #define ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL_RESET 0x0
828 #define ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL_GET(value) (((value) & 0x00010000) >> 16)
830 #define ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL_SET(value) (((value) << 16) & 0x00010000)
841 #define ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN_LSB 17
843 #define ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN_MSB 17
845 #define ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN_WIDTH 1
847 #define ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN_SET_MSK 0x00020000
849 #define ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN_CLR_MSK 0xfffdffff
851 #define ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN_RESET 0x0
853 #define ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN_GET(value) (((value) & 0x00020000) >> 17)
855 #define ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN_SET(value) (((value) << 17) & 0x00020000)
866 #define ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN_LSB 18
868 #define ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN_MSB 18
870 #define ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN_WIDTH 1
872 #define ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN_SET_MSK 0x00040000
874 #define ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN_CLR_MSK 0xfffbffff
876 #define ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN_RESET 0x0
878 #define ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN_GET(value) (((value) & 0x00040000) >> 18)
880 #define ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN_SET(value) (((value) << 18) & 0x00040000)
891 #define ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN_LSB 19
893 #define ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN_MSB 19
895 #define ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN_WIDTH 1
897 #define ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN_SET_MSK 0x00080000
899 #define ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN_CLR_MSK 0xfff7ffff
901 #define ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN_RESET 0x0
903 #define ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN_GET(value) (((value) & 0x00080000) >> 19)
905 #define ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN_SET(value) (((value) << 19) & 0x00080000)
916 #define ALT_I2C_IC_CON_RSVD_IC_CON_2_LSB 20
918 #define ALT_I2C_IC_CON_RSVD_IC_CON_2_MSB 31
920 #define ALT_I2C_IC_CON_RSVD_IC_CON_2_WIDTH 12
922 #define ALT_I2C_IC_CON_RSVD_IC_CON_2_SET_MSK 0xfff00000
924 #define ALT_I2C_IC_CON_RSVD_IC_CON_2_CLR_MSK 0x000fffff
926 #define ALT_I2C_IC_CON_RSVD_IC_CON_2_RESET 0x0
928 #define ALT_I2C_IC_CON_RSVD_IC_CON_2_GET(value) (((value) & 0xfff00000) >> 20)
930 #define ALT_I2C_IC_CON_RSVD_IC_CON_2_SET(value) (((value) << 20) & 0xfff00000)
944 struct ALT_I2C_IC_CON_s
946 volatile uint32_t MASTER_MODE : 1;
947 volatile uint32_t SPEED : 2;
948 volatile uint32_t IC_10BITADDR_SLAVE : 1;
949 const volatile uint32_t IC_10BITADDR_MASTER_rd_only : 1;
950 volatile uint32_t IC_RESTART_EN : 1;
951 volatile uint32_t IC_SLAVE_DISABLE : 1;
952 volatile uint32_t STOP_DET_IFADDRESSED : 1;
953 volatile uint32_t TX_EMPTY_CTRL : 1;
954 const volatile uint32_t RX_FIFO_FULL_HLD_CTRL : 1;
955 const volatile uint32_t STOP_DET_IF_MASTER_ACTIVE : 1;
956 const volatile uint32_t RSVD_BUS_CLEAR_FEATURE_CTRL : 1;
957 const volatile uint32_t RSVD_IC_CON_1 : 4;
958 const volatile uint32_t RSVD_OPTIONAL_SAR_CTRL : 1;
959 const volatile uint32_t RSVD_SMBUS_SLAVE_QUICK_EN : 1;
960 const volatile uint32_t RSVD_SMBUS_ARP_EN : 1;
961 const volatile uint32_t RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN : 1;
962 const volatile uint32_t RSVD_IC_CON_2 : 12;
966 typedef struct ALT_I2C_IC_CON_s ALT_I2C_IC_CON_t;
970 #define ALT_I2C_IC_CON_RESET 0x0000007d
972 #define ALT_I2C_IC_CON_OFST 0x0
974 #define ALT_I2C_IC_CON_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CON_OFST))
1064 #define ALT_I2C_IC_TAR_IC_TAR_LSB 0
1066 #define ALT_I2C_IC_TAR_IC_TAR_MSB 9
1068 #define ALT_I2C_IC_TAR_IC_TAR_WIDTH 10
1070 #define ALT_I2C_IC_TAR_IC_TAR_SET_MSK 0x000003ff
1072 #define ALT_I2C_IC_TAR_IC_TAR_CLR_MSK 0xfffffc00
1074 #define ALT_I2C_IC_TAR_IC_TAR_RESET 0x55
1076 #define ALT_I2C_IC_TAR_IC_TAR_GET(value) (((value) & 0x000003ff) >> 0)
1078 #define ALT_I2C_IC_TAR_IC_TAR_SET(value) (((value) << 0) & 0x000003ff)
1119 #define ALT_I2C_IC_TAR_GC_OR_START_E_GENERAL_CALL 0x0
1125 #define ALT_I2C_IC_TAR_GC_OR_START_E_START_BYTE 0x1
1128 #define ALT_I2C_IC_TAR_GC_OR_START_LSB 10
1130 #define ALT_I2C_IC_TAR_GC_OR_START_MSB 10
1132 #define ALT_I2C_IC_TAR_GC_OR_START_WIDTH 1
1134 #define ALT_I2C_IC_TAR_GC_OR_START_SET_MSK 0x00000400
1136 #define ALT_I2C_IC_TAR_GC_OR_START_CLR_MSK 0xfffffbff
1138 #define ALT_I2C_IC_TAR_GC_OR_START_RESET 0x0
1140 #define ALT_I2C_IC_TAR_GC_OR_START_GET(value) (((value) & 0x00000400) >> 10)
1142 #define ALT_I2C_IC_TAR_GC_OR_START_SET(value) (((value) << 10) & 0x00000400)
1176 #define ALT_I2C_IC_TAR_SPECIAL_E_DISABLED 0x0
1182 #define ALT_I2C_IC_TAR_SPECIAL_E_ENABLED 0x1
1185 #define ALT_I2C_IC_TAR_SPECIAL_LSB 11
1187 #define ALT_I2C_IC_TAR_SPECIAL_MSB 11
1189 #define ALT_I2C_IC_TAR_SPECIAL_WIDTH 1
1191 #define ALT_I2C_IC_TAR_SPECIAL_SET_MSK 0x00000800
1193 #define ALT_I2C_IC_TAR_SPECIAL_CLR_MSK 0xfffff7ff
1195 #define ALT_I2C_IC_TAR_SPECIAL_RESET 0x0
1197 #define ALT_I2C_IC_TAR_SPECIAL_GET(value) (((value) & 0x00000800) >> 11)
1199 #define ALT_I2C_IC_TAR_SPECIAL_SET(value) (((value) << 11) & 0x00000800)
1237 #define ALT_I2C_IC_TAR_IC_10BITADDR_MASTER_E_ADDR_7BITS 0x0
1243 #define ALT_I2C_IC_TAR_IC_10BITADDR_MASTER_E_ADDR_10BITS 0x1
1246 #define ALT_I2C_IC_TAR_IC_10BITADDR_MASTER_LSB 12
1248 #define ALT_I2C_IC_TAR_IC_10BITADDR_MASTER_MSB 12
1250 #define ALT_I2C_IC_TAR_IC_10BITADDR_MASTER_WIDTH 1
1252 #define ALT_I2C_IC_TAR_IC_10BITADDR_MASTER_SET_MSK 0x00001000
1254 #define ALT_I2C_IC_TAR_IC_10BITADDR_MASTER_CLR_MSK 0xffffefff
1256 #define ALT_I2C_IC_TAR_IC_10BITADDR_MASTER_RESET 0x1
1258 #define ALT_I2C_IC_TAR_IC_10BITADDR_MASTER_GET(value) (((value) & 0x00001000) >> 12)
1260 #define ALT_I2C_IC_TAR_IC_10BITADDR_MASTER_SET(value) (((value) << 12) & 0x00001000)
1271 #define ALT_I2C_IC_TAR_RSVD_DEVICE_ID_LSB 13
1273 #define ALT_I2C_IC_TAR_RSVD_DEVICE_ID_MSB 13
1275 #define ALT_I2C_IC_TAR_RSVD_DEVICE_ID_WIDTH 1
1277 #define ALT_I2C_IC_TAR_RSVD_DEVICE_ID_SET_MSK 0x00002000
1279 #define ALT_I2C_IC_TAR_RSVD_DEVICE_ID_CLR_MSK 0xffffdfff
1281 #define ALT_I2C_IC_TAR_RSVD_DEVICE_ID_RESET 0x0
1283 #define ALT_I2C_IC_TAR_RSVD_DEVICE_ID_GET(value) (((value) & 0x00002000) >> 13)
1285 #define ALT_I2C_IC_TAR_RSVD_DEVICE_ID_SET(value) (((value) << 13) & 0x00002000)
1296 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_1_LSB 14
1298 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_1_MSB 15
1300 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_1_WIDTH 2
1302 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_1_SET_MSK 0x0000c000
1304 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_1_CLR_MSK 0xffff3fff
1306 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_1_RESET 0x0
1308 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_1_GET(value) (((value) & 0x0000c000) >> 14)
1310 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_1_SET(value) (((value) << 14) & 0x0000c000)
1321 #define ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD_LSB 16
1323 #define ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD_MSB 16
1325 #define ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD_WIDTH 1
1327 #define ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD_SET_MSK 0x00010000
1329 #define ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD_CLR_MSK 0xfffeffff
1331 #define ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD_RESET 0x0
1333 #define ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD_GET(value) (((value) & 0x00010000) >> 16)
1335 #define ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD_SET(value) (((value) << 16) & 0x00010000)
1346 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_2_LSB 17
1348 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_2_MSB 31
1350 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_2_WIDTH 15
1352 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_2_SET_MSK 0xfffe0000
1354 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_2_CLR_MSK 0x0001ffff
1356 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_2_RESET 0x0
1358 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_2_GET(value) (((value) & 0xfffe0000) >> 17)
1360 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_2_SET(value) (((value) << 17) & 0xfffe0000)
1362 #ifndef __ASSEMBLY__
1374 struct ALT_I2C_IC_TAR_s
1376 volatile uint32_t IC_TAR : 10;
1377 volatile uint32_t GC_OR_START : 1;
1378 volatile uint32_t SPECIAL : 1;
1379 volatile uint32_t IC_10BITADDR_MASTER : 1;
1380 const volatile uint32_t RSVD_DEVICE_ID : 1;
1381 const volatile uint32_t RSVD_IC_TAR_1 : 2;
1382 const volatile uint32_t RSVD_SMBUS_QUICK_CMD : 1;
1383 const volatile uint32_t RSVD_IC_TAR_2 : 15;
1387 typedef struct ALT_I2C_IC_TAR_s ALT_I2C_IC_TAR_t;
1391 #define ALT_I2C_IC_TAR_RESET 0x00001055
1393 #define ALT_I2C_IC_TAR_OFST 0x4
1395 #define ALT_I2C_IC_TAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_TAR_OFST))
1447 #define ALT_I2C_IC_SAR_IC_SAR_LSB 0
1449 #define ALT_I2C_IC_SAR_IC_SAR_MSB 9
1451 #define ALT_I2C_IC_SAR_IC_SAR_WIDTH 10
1453 #define ALT_I2C_IC_SAR_IC_SAR_SET_MSK 0x000003ff
1455 #define ALT_I2C_IC_SAR_IC_SAR_CLR_MSK 0xfffffc00
1457 #define ALT_I2C_IC_SAR_IC_SAR_RESET 0x55
1459 #define ALT_I2C_IC_SAR_IC_SAR_GET(value) (((value) & 0x000003ff) >> 0)
1461 #define ALT_I2C_IC_SAR_IC_SAR_SET(value) (((value) << 0) & 0x000003ff)
1472 #define ALT_I2C_IC_SAR_RSVD_IC_SAR_LSB 10
1474 #define ALT_I2C_IC_SAR_RSVD_IC_SAR_MSB 31
1476 #define ALT_I2C_IC_SAR_RSVD_IC_SAR_WIDTH 22
1478 #define ALT_I2C_IC_SAR_RSVD_IC_SAR_SET_MSK 0xfffffc00
1480 #define ALT_I2C_IC_SAR_RSVD_IC_SAR_CLR_MSK 0x000003ff
1482 #define ALT_I2C_IC_SAR_RSVD_IC_SAR_RESET 0x0
1484 #define ALT_I2C_IC_SAR_RSVD_IC_SAR_GET(value) (((value) & 0xfffffc00) >> 10)
1486 #define ALT_I2C_IC_SAR_RSVD_IC_SAR_SET(value) (((value) << 10) & 0xfffffc00)
1488 #ifndef __ASSEMBLY__
1500 struct ALT_I2C_IC_SAR_s
1502 volatile uint32_t IC_SAR : 10;
1503 const volatile uint32_t RSVD_IC_SAR : 22;
1507 typedef struct ALT_I2C_IC_SAR_s ALT_I2C_IC_SAR_t;
1511 #define ALT_I2C_IC_SAR_RESET 0x00000055
1513 #define ALT_I2C_IC_SAR_OFST 0x8
1515 #define ALT_I2C_IC_SAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_SAR_OFST))
1587 #define ALT_I2C_IC_DATA_CMD_DAT_LSB 0
1589 #define ALT_I2C_IC_DATA_CMD_DAT_MSB 7
1591 #define ALT_I2C_IC_DATA_CMD_DAT_WIDTH 8
1593 #define ALT_I2C_IC_DATA_CMD_DAT_SET_MSK 0x000000ff
1595 #define ALT_I2C_IC_DATA_CMD_DAT_CLR_MSK 0xffffff00
1597 #define ALT_I2C_IC_DATA_CMD_DAT_RESET 0x0
1599 #define ALT_I2C_IC_DATA_CMD_DAT_GET(value) (((value) & 0x000000ff) >> 0)
1601 #define ALT_I2C_IC_DATA_CMD_DAT_SET(value) (((value) << 0) & 0x000000ff)
1670 #define ALT_I2C_IC_DATA_CMD_CMD_E_WRITE 0x0
1676 #define ALT_I2C_IC_DATA_CMD_CMD_E_READ 0x1
1679 #define ALT_I2C_IC_DATA_CMD_CMD_LSB 8
1681 #define ALT_I2C_IC_DATA_CMD_CMD_MSB 8
1683 #define ALT_I2C_IC_DATA_CMD_CMD_WIDTH 1
1685 #define ALT_I2C_IC_DATA_CMD_CMD_SET_MSK 0x00000100
1687 #define ALT_I2C_IC_DATA_CMD_CMD_CLR_MSK 0xfffffeff
1689 #define ALT_I2C_IC_DATA_CMD_CMD_RESET 0x0
1691 #define ALT_I2C_IC_DATA_CMD_CMD_GET(value) (((value) & 0x00000100) >> 8)
1693 #define ALT_I2C_IC_DATA_CMD_CMD_SET(value) (((value) << 8) & 0x00000100)
1737 #define ALT_I2C_IC_DATA_CMD_STOP_E_DISABLE 0x0
1743 #define ALT_I2C_IC_DATA_CMD_STOP_E_ENABLE 0x1
1746 #define ALT_I2C_IC_DATA_CMD_STOP_LSB 9
1748 #define ALT_I2C_IC_DATA_CMD_STOP_MSB 9
1750 #define ALT_I2C_IC_DATA_CMD_STOP_WIDTH 1
1752 #define ALT_I2C_IC_DATA_CMD_STOP_SET_MSK 0x00000200
1754 #define ALT_I2C_IC_DATA_CMD_STOP_CLR_MSK 0xfffffdff
1756 #define ALT_I2C_IC_DATA_CMD_STOP_RESET 0x0
1758 #define ALT_I2C_IC_DATA_CMD_STOP_GET(value) (((value) & 0x00000200) >> 9)
1760 #define ALT_I2C_IC_DATA_CMD_STOP_SET(value) (((value) << 9) & 0x00000200)
1801 #define ALT_I2C_IC_DATA_CMD_RESTART_E_DISABLE 0x0
1807 #define ALT_I2C_IC_DATA_CMD_RESTART_E_ENABLE 0x1
1810 #define ALT_I2C_IC_DATA_CMD_RESTART_LSB 10
1812 #define ALT_I2C_IC_DATA_CMD_RESTART_MSB 10
1814 #define ALT_I2C_IC_DATA_CMD_RESTART_WIDTH 1
1816 #define ALT_I2C_IC_DATA_CMD_RESTART_SET_MSK 0x00000400
1818 #define ALT_I2C_IC_DATA_CMD_RESTART_CLR_MSK 0xfffffbff
1820 #define ALT_I2C_IC_DATA_CMD_RESTART_RESET 0x0
1822 #define ALT_I2C_IC_DATA_CMD_RESTART_GET(value) (((value) & 0x00000400) >> 10)
1824 #define ALT_I2C_IC_DATA_CMD_RESTART_SET(value) (((value) << 10) & 0x00000400)
1872 #define ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE_E_INACTIVE 0x0
1878 #define ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE_E_ACTIVE 0x1
1881 #define ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE_LSB 11
1883 #define ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE_MSB 11
1885 #define ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE_WIDTH 1
1887 #define ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE_SET_MSK 0x00000800
1889 #define ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE_CLR_MSK 0xfffff7ff
1891 #define ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE_RESET 0x0
1893 #define ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE_GET(value) (((value) & 0x00000800) >> 11)
1895 #define ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE_SET(value) (((value) << 11) & 0x00000800)
1906 #define ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD_LSB 12
1908 #define ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD_MSB 31
1910 #define ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD_WIDTH 20
1912 #define ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD_SET_MSK 0xfffff000
1914 #define ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD_CLR_MSK 0x00000fff
1916 #define ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD_RESET 0x0
1918 #define ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD_GET(value) (((value) & 0xfffff000) >> 12)
1920 #define ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD_SET(value) (((value) << 12) & 0xfffff000)
1922 #ifndef __ASSEMBLY__
1934 struct ALT_I2C_IC_DATA_CMD_s
1936 volatile uint32_t DAT : 8;
1937 volatile uint32_t CMD : 1;
1938 volatile uint32_t STOP : 1;
1939 volatile uint32_t RESTART : 1;
1940 const volatile uint32_t FIRST_DATA_BYTE : 1;
1941 const volatile uint32_t RSVD_IC_DATA_CMD : 20;
1945 typedef struct ALT_I2C_IC_DATA_CMD_s ALT_I2C_IC_DATA_CMD_t;
1949 #define ALT_I2C_IC_DATA_CMD_RESET 0x00000000
1951 #define ALT_I2C_IC_DATA_CMD_OFST 0x10
1953 #define ALT_I2C_IC_DATA_CMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_DATA_CMD_OFST))
2017 #define ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB 0
2019 #define ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB 15
2021 #define ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_WIDTH 16
2023 #define ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET_MSK 0x0000ffff
2025 #define ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_CLR_MSK 0xffff0000
2027 #define ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET 0x1f4
2029 #define ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0)
2031 #define ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff)
2042 #define ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT_LSB 16
2044 #define ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT_MSB 31
2046 #define ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT_WIDTH 16
2048 #define ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT_SET_MSK 0xffff0000
2050 #define ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT_CLR_MSK 0x0000ffff
2052 #define ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT_RESET 0x0
2054 #define ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT_GET(value) (((value) & 0xffff0000) >> 16)
2056 #define ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT_SET(value) (((value) << 16) & 0xffff0000)
2058 #ifndef __ASSEMBLY__
2070 struct ALT_I2C_IC_SS_SCL_HCNT_s
2072 volatile uint32_t IC_SS_SCL_HCNT : 16;
2073 const volatile uint32_t RSVD_IC_SS_SCL_HIGH_COUNT : 16;
2077 typedef struct ALT_I2C_IC_SS_SCL_HCNT_s ALT_I2C_IC_SS_SCL_HCNT_t;
2081 #define ALT_I2C_IC_SS_SCL_HCNT_RESET 0x000001f4
2083 #define ALT_I2C_IC_SS_SCL_HCNT_OFST 0x14
2085 #define ALT_I2C_IC_SS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_SS_SCL_HCNT_OFST))
2143 #define ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB 0
2145 #define ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB 15
2147 #define ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_WIDTH 16
2149 #define ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET_MSK 0x0000ffff
2151 #define ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_CLR_MSK 0xffff0000
2153 #define ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET 0x24c
2155 #define ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0)
2157 #define ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff)
2168 #define ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT_LSB 16
2170 #define ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT_MSB 31
2172 #define ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT_WIDTH 16
2174 #define ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT_SET_MSK 0xffff0000
2176 #define ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT_CLR_MSK 0x0000ffff
2178 #define ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT_RESET 0x0
2180 #define ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT_GET(value) (((value) & 0xffff0000) >> 16)
2182 #define ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT_SET(value) (((value) << 16) & 0xffff0000)
2184 #ifndef __ASSEMBLY__
2196 struct ALT_I2C_IC_SS_SCL_LCNT_s
2198 volatile uint32_t IC_SS_SCL_LCNT : 16;
2199 const volatile uint32_t RSVD_IC_SS_SCL_LOW_COUNT : 16;
2203 typedef struct ALT_I2C_IC_SS_SCL_LCNT_s ALT_I2C_IC_SS_SCL_LCNT_t;
2207 #define ALT_I2C_IC_SS_SCL_LCNT_RESET 0x0000024c
2209 #define ALT_I2C_IC_SS_SCL_LCNT_OFST 0x18
2211 #define ALT_I2C_IC_SS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_SS_SCL_LCNT_OFST))
2274 #define ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB 0
2276 #define ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB 15
2278 #define ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_WIDTH 16
2280 #define ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET_MSK 0x0000ffff
2282 #define ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_CLR_MSK 0xffff0000
2284 #define ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET 0x4b
2286 #define ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0)
2288 #define ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff)
2299 #define ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT_LSB 16
2301 #define ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT_MSB 31
2303 #define ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT_WIDTH 16
2305 #define ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT_SET_MSK 0xffff0000
2307 #define ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT_CLR_MSK 0x0000ffff
2309 #define ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT_RESET 0x0
2311 #define ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT_GET(value) (((value) & 0xffff0000) >> 16)
2313 #define ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT_SET(value) (((value) << 16) & 0xffff0000)
2315 #ifndef __ASSEMBLY__
2327 struct ALT_I2C_IC_FS_SCL_HCNT_s
2329 volatile uint32_t IC_FS_SCL_HCNT : 16;
2330 const volatile uint32_t RSVD_IC_FS_SCL_HCNT : 16;
2334 typedef struct ALT_I2C_IC_FS_SCL_HCNT_s ALT_I2C_IC_FS_SCL_HCNT_t;
2338 #define ALT_I2C_IC_FS_SCL_HCNT_RESET 0x0000004b
2340 #define ALT_I2C_IC_FS_SCL_HCNT_OFST 0x1c
2342 #define ALT_I2C_IC_FS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_FS_SCL_HCNT_OFST))
2408 #define ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB 0
2410 #define ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB 15
2412 #define ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_WIDTH 16
2414 #define ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET_MSK 0x0000ffff
2416 #define ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_CLR_MSK 0xffff0000
2418 #define ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET 0xa3
2420 #define ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0)
2422 #define ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff)
2433 #define ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT_LSB 16
2435 #define ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT_MSB 31
2437 #define ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT_WIDTH 16
2439 #define ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT_SET_MSK 0xffff0000
2441 #define ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT_CLR_MSK 0x0000ffff
2443 #define ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT_RESET 0x0
2445 #define ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT_GET(value) (((value) & 0xffff0000) >> 16)
2447 #define ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT_SET(value) (((value) << 16) & 0xffff0000)
2449 #ifndef __ASSEMBLY__
2461 struct ALT_I2C_IC_FS_SCL_LCNT_s
2463 volatile uint32_t IC_FS_SCL_LCNT : 16;
2464 const volatile uint32_t RSVD_IC_FS_SCL_LCNT : 16;
2468 typedef struct ALT_I2C_IC_FS_SCL_LCNT_s ALT_I2C_IC_FS_SCL_LCNT_t;
2472 #define ALT_I2C_IC_FS_SCL_LCNT_RESET 0x000000a3
2474 #define ALT_I2C_IC_FS_SCL_LCNT_OFST 0x20
2476 #define ALT_I2C_IC_FS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_FS_SCL_LCNT_OFST))
2547 #define ALT_I2C_IC_INTR_STAT_R_RX_UNDER_E_INACTIVE 0x0
2553 #define ALT_I2C_IC_INTR_STAT_R_RX_UNDER_E_ACTIVE 0x1
2556 #define ALT_I2C_IC_INTR_STAT_R_RX_UNDER_LSB 0
2558 #define ALT_I2C_IC_INTR_STAT_R_RX_UNDER_MSB 0
2560 #define ALT_I2C_IC_INTR_STAT_R_RX_UNDER_WIDTH 1
2562 #define ALT_I2C_IC_INTR_STAT_R_RX_UNDER_SET_MSK 0x00000001
2564 #define ALT_I2C_IC_INTR_STAT_R_RX_UNDER_CLR_MSK 0xfffffffe
2566 #define ALT_I2C_IC_INTR_STAT_R_RX_UNDER_RESET 0x0
2568 #define ALT_I2C_IC_INTR_STAT_R_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
2570 #define ALT_I2C_IC_INTR_STAT_R_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
2611 #define ALT_I2C_IC_INTR_STAT_R_RX_OVER_E_INACTIVE 0x0
2617 #define ALT_I2C_IC_INTR_STAT_R_RX_OVER_E_ACTIVE 0x1
2620 #define ALT_I2C_IC_INTR_STAT_R_RX_OVER_LSB 1
2622 #define ALT_I2C_IC_INTR_STAT_R_RX_OVER_MSB 1
2624 #define ALT_I2C_IC_INTR_STAT_R_RX_OVER_WIDTH 1
2626 #define ALT_I2C_IC_INTR_STAT_R_RX_OVER_SET_MSK 0x00000002
2628 #define ALT_I2C_IC_INTR_STAT_R_RX_OVER_CLR_MSK 0xfffffffd
2630 #define ALT_I2C_IC_INTR_STAT_R_RX_OVER_RESET 0x0
2632 #define ALT_I2C_IC_INTR_STAT_R_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
2634 #define ALT_I2C_IC_INTR_STAT_R_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
2668 #define ALT_I2C_IC_INTR_STAT_R_RX_FULL_E_INACTIVE 0x0
2674 #define ALT_I2C_IC_INTR_STAT_R_RX_FULL_E_ACTIVE 0x1
2677 #define ALT_I2C_IC_INTR_STAT_R_RX_FULL_LSB 2
2679 #define ALT_I2C_IC_INTR_STAT_R_RX_FULL_MSB 2
2681 #define ALT_I2C_IC_INTR_STAT_R_RX_FULL_WIDTH 1
2683 #define ALT_I2C_IC_INTR_STAT_R_RX_FULL_SET_MSK 0x00000004
2685 #define ALT_I2C_IC_INTR_STAT_R_RX_FULL_CLR_MSK 0xfffffffb
2687 #define ALT_I2C_IC_INTR_STAT_R_RX_FULL_RESET 0x0
2689 #define ALT_I2C_IC_INTR_STAT_R_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
2691 #define ALT_I2C_IC_INTR_STAT_R_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
2723 #define ALT_I2C_IC_INTR_STAT_R_TX_OVER_E_INACTIVE 0x0
2729 #define ALT_I2C_IC_INTR_STAT_R_TX_OVER_E_ACTIVE 0x1
2732 #define ALT_I2C_IC_INTR_STAT_R_TX_OVER_LSB 3
2734 #define ALT_I2C_IC_INTR_STAT_R_TX_OVER_MSB 3
2736 #define ALT_I2C_IC_INTR_STAT_R_TX_OVER_WIDTH 1
2738 #define ALT_I2C_IC_INTR_STAT_R_TX_OVER_SET_MSK 0x00000008
2740 #define ALT_I2C_IC_INTR_STAT_R_TX_OVER_CLR_MSK 0xfffffff7
2742 #define ALT_I2C_IC_INTR_STAT_R_TX_OVER_RESET 0x0
2744 #define ALT_I2C_IC_INTR_STAT_R_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
2746 #define ALT_I2C_IC_INTR_STAT_R_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
2796 #define ALT_I2C_IC_INTR_STAT_R_TX_EMPTY_E_INACTIVE 0x0
2802 #define ALT_I2C_IC_INTR_STAT_R_TX_EMPTY_E_ACTIVE 0x1
2805 #define ALT_I2C_IC_INTR_STAT_R_TX_EMPTY_LSB 4
2807 #define ALT_I2C_IC_INTR_STAT_R_TX_EMPTY_MSB 4
2809 #define ALT_I2C_IC_INTR_STAT_R_TX_EMPTY_WIDTH 1
2811 #define ALT_I2C_IC_INTR_STAT_R_TX_EMPTY_SET_MSK 0x00000010
2813 #define ALT_I2C_IC_INTR_STAT_R_TX_EMPTY_CLR_MSK 0xffffffef
2815 #define ALT_I2C_IC_INTR_STAT_R_TX_EMPTY_RESET 0x0
2817 #define ALT_I2C_IC_INTR_STAT_R_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
2819 #define ALT_I2C_IC_INTR_STAT_R_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
2858 #define ALT_I2C_IC_INTR_STAT_R_RD_REQ_E_INACTIVE 0x0
2864 #define ALT_I2C_IC_INTR_STAT_R_RD_REQ_E_ACTIVE 0x1
2867 #define ALT_I2C_IC_INTR_STAT_R_RD_REQ_LSB 5
2869 #define ALT_I2C_IC_INTR_STAT_R_RD_REQ_MSB 5
2871 #define ALT_I2C_IC_INTR_STAT_R_RD_REQ_WIDTH 1
2873 #define ALT_I2C_IC_INTR_STAT_R_RD_REQ_SET_MSK 0x00000020
2875 #define ALT_I2C_IC_INTR_STAT_R_RD_REQ_CLR_MSK 0xffffffdf
2877 #define ALT_I2C_IC_INTR_STAT_R_RD_REQ_RESET 0x0
2879 #define ALT_I2C_IC_INTR_STAT_R_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
2881 #define ALT_I2C_IC_INTR_STAT_R_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
2925 #define ALT_I2C_IC_INTR_STAT_R_TX_ABRT_E_INACTIVE 0x0
2931 #define ALT_I2C_IC_INTR_STAT_R_TX_ABRT_E_ACTIVE 0x1
2934 #define ALT_I2C_IC_INTR_STAT_R_TX_ABRT_LSB 6
2936 #define ALT_I2C_IC_INTR_STAT_R_TX_ABRT_MSB 6
2938 #define ALT_I2C_IC_INTR_STAT_R_TX_ABRT_WIDTH 1
2940 #define ALT_I2C_IC_INTR_STAT_R_TX_ABRT_SET_MSK 0x00000040
2942 #define ALT_I2C_IC_INTR_STAT_R_TX_ABRT_CLR_MSK 0xffffffbf
2944 #define ALT_I2C_IC_INTR_STAT_R_TX_ABRT_RESET 0x0
2946 #define ALT_I2C_IC_INTR_STAT_R_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
2948 #define ALT_I2C_IC_INTR_STAT_R_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
2980 #define ALT_I2C_IC_INTR_STAT_R_RX_DONE_E_INACTIVE 0x0
2986 #define ALT_I2C_IC_INTR_STAT_R_RX_DONE_E_ACTIVE 0x1
2989 #define ALT_I2C_IC_INTR_STAT_R_RX_DONE_LSB 7
2991 #define ALT_I2C_IC_INTR_STAT_R_RX_DONE_MSB 7
2993 #define ALT_I2C_IC_INTR_STAT_R_RX_DONE_WIDTH 1
2995 #define ALT_I2C_IC_INTR_STAT_R_RX_DONE_SET_MSK 0x00000080
2997 #define ALT_I2C_IC_INTR_STAT_R_RX_DONE_CLR_MSK 0xffffff7f
2999 #define ALT_I2C_IC_INTR_STAT_R_RX_DONE_RESET 0x0
3001 #define ALT_I2C_IC_INTR_STAT_R_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
3003 #define ALT_I2C_IC_INTR_STAT_R_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
3044 #define ALT_I2C_IC_INTR_STAT_R_ACTIVITY_E_INACTIVE 0x0
3050 #define ALT_I2C_IC_INTR_STAT_R_ACTIVITY_E_ACTIVE 0x1
3053 #define ALT_I2C_IC_INTR_STAT_R_ACTIVITY_LSB 8
3055 #define ALT_I2C_IC_INTR_STAT_R_ACTIVITY_MSB 8
3057 #define ALT_I2C_IC_INTR_STAT_R_ACTIVITY_WIDTH 1
3059 #define ALT_I2C_IC_INTR_STAT_R_ACTIVITY_SET_MSK 0x00000100
3061 #define ALT_I2C_IC_INTR_STAT_R_ACTIVITY_CLR_MSK 0xfffffeff
3063 #define ALT_I2C_IC_INTR_STAT_R_ACTIVITY_RESET 0x0
3065 #define ALT_I2C_IC_INTR_STAT_R_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
3067 #define ALT_I2C_IC_INTR_STAT_R_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
3120 #define ALT_I2C_IC_INTR_STAT_R_STOP_DET_E_INACTIVE 0x0
3126 #define ALT_I2C_IC_INTR_STAT_R_STOP_DET_E_ACTIVE 0x1
3129 #define ALT_I2C_IC_INTR_STAT_R_STOP_DET_LSB 9
3131 #define ALT_I2C_IC_INTR_STAT_R_STOP_DET_MSB 9
3133 #define ALT_I2C_IC_INTR_STAT_R_STOP_DET_WIDTH 1
3135 #define ALT_I2C_IC_INTR_STAT_R_STOP_DET_SET_MSK 0x00000200
3137 #define ALT_I2C_IC_INTR_STAT_R_STOP_DET_CLR_MSK 0xfffffdff
3139 #define ALT_I2C_IC_INTR_STAT_R_STOP_DET_RESET 0x0
3141 #define ALT_I2C_IC_INTR_STAT_R_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
3143 #define ALT_I2C_IC_INTR_STAT_R_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
3171 #define ALT_I2C_IC_INTR_STAT_R_START_DET_E_INACTIVE 0x0
3177 #define ALT_I2C_IC_INTR_STAT_R_START_DET_E_ACTIVE 0x1
3180 #define ALT_I2C_IC_INTR_STAT_R_START_DET_LSB 10
3182 #define ALT_I2C_IC_INTR_STAT_R_START_DET_MSB 10
3184 #define ALT_I2C_IC_INTR_STAT_R_START_DET_WIDTH 1
3186 #define ALT_I2C_IC_INTR_STAT_R_START_DET_SET_MSK 0x00000400
3188 #define ALT_I2C_IC_INTR_STAT_R_START_DET_CLR_MSK 0xfffffbff
3190 #define ALT_I2C_IC_INTR_STAT_R_START_DET_RESET 0x0
3192 #define ALT_I2C_IC_INTR_STAT_R_START_DET_GET(value) (((value) & 0x00000400) >> 10)
3194 #define ALT_I2C_IC_INTR_STAT_R_START_DET_SET(value) (((value) << 10) & 0x00000400)
3224 #define ALT_I2C_IC_INTR_STAT_R_GEN_CALL_E_INACTIVE 0x0
3230 #define ALT_I2C_IC_INTR_STAT_R_GEN_CALL_E_ACTIVE 0x1
3233 #define ALT_I2C_IC_INTR_STAT_R_GEN_CALL_LSB 11
3235 #define ALT_I2C_IC_INTR_STAT_R_GEN_CALL_MSB 11
3237 #define ALT_I2C_IC_INTR_STAT_R_GEN_CALL_WIDTH 1
3239 #define ALT_I2C_IC_INTR_STAT_R_GEN_CALL_SET_MSK 0x00000800
3241 #define ALT_I2C_IC_INTR_STAT_R_GEN_CALL_CLR_MSK 0xfffff7ff
3243 #define ALT_I2C_IC_INTR_STAT_R_GEN_CALL_RESET 0x0
3245 #define ALT_I2C_IC_INTR_STAT_R_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
3247 #define ALT_I2C_IC_INTR_STAT_R_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
3274 #define ALT_I2C_IC_INTR_STAT_R_RESTART_DET_E_INACTIVE 0x0
3280 #define ALT_I2C_IC_INTR_STAT_R_RESTART_DET_E_ACTIVE 0x1
3283 #define ALT_I2C_IC_INTR_STAT_R_RESTART_DET_LSB 12
3285 #define ALT_I2C_IC_INTR_STAT_R_RESTART_DET_MSB 12
3287 #define ALT_I2C_IC_INTR_STAT_R_RESTART_DET_WIDTH 1
3289 #define ALT_I2C_IC_INTR_STAT_R_RESTART_DET_SET_MSK 0x00001000
3291 #define ALT_I2C_IC_INTR_STAT_R_RESTART_DET_CLR_MSK 0xffffefff
3293 #define ALT_I2C_IC_INTR_STAT_R_RESTART_DET_RESET 0x0
3295 #define ALT_I2C_IC_INTR_STAT_R_RESTART_DET_GET(value) (((value) & 0x00001000) >> 12)
3297 #define ALT_I2C_IC_INTR_STAT_R_RESTART_DET_SET(value) (((value) << 12) & 0x00001000)
3323 #define ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_E_INACTIVE 0x0
3329 #define ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_E_ACTIVE 0x1
3332 #define ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_LSB 13
3334 #define ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_MSB 13
3336 #define ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_WIDTH 1
3338 #define ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_SET_MSK 0x00002000
3340 #define ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_CLR_MSK 0xffffdfff
3342 #define ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_RESET 0x0
3344 #define ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_GET(value) (((value) & 0x00002000) >> 13)
3346 #define ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_SET(value) (((value) << 13) & 0x00002000)
3374 #define ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW_E_INACTIVE 0x0
3380 #define ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW_E_ACTIVE 0x1
3383 #define ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW_LSB 14
3385 #define ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW_MSB 14
3387 #define ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW_WIDTH 1
3389 #define ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW_SET_MSK 0x00004000
3391 #define ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW_CLR_MSK 0xffffbfff
3393 #define ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW_RESET 0x0
3395 #define ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW_GET(value) (((value) & 0x00004000) >> 14)
3397 #define ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW_SET(value) (((value) << 14) & 0x00004000)
3408 #define ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT_LSB 15
3410 #define ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT_MSB 31
3412 #define ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT_WIDTH 17
3414 #define ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT_SET_MSK 0xffff8000
3416 #define ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT_CLR_MSK 0x00007fff
3418 #define ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT_RESET 0x0
3420 #define ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT_GET(value) (((value) & 0xffff8000) >> 15)
3422 #define ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT_SET(value) (((value) << 15) & 0xffff8000)
3424 #ifndef __ASSEMBLY__
3436 struct ALT_I2C_IC_INTR_STAT_s
3438 const volatile uint32_t R_RX_UNDER : 1;
3439 const volatile uint32_t R_RX_OVER : 1;
3440 const volatile uint32_t R_RX_FULL : 1;
3441 const volatile uint32_t R_TX_OVER : 1;
3442 const volatile uint32_t R_TX_EMPTY : 1;
3443 const volatile uint32_t R_RD_REQ : 1;
3444 const volatile uint32_t R_TX_ABRT : 1;
3445 const volatile uint32_t R_RX_DONE : 1;
3446 const volatile uint32_t R_ACTIVITY : 1;
3447 const volatile uint32_t R_STOP_DET : 1;
3448 const volatile uint32_t R_START_DET : 1;
3449 const volatile uint32_t R_GEN_CALL : 1;
3450 const volatile uint32_t R_RESTART_DET : 1;
3451 const volatile uint32_t R_MASTER_ON_HOLD : 1;
3452 const volatile uint32_t RSVD_R_SCL_STUCK_AT_LOW : 1;
3453 const volatile uint32_t RSVD_IC_INTR_STAT : 17;
3457 typedef struct ALT_I2C_IC_INTR_STAT_s ALT_I2C_IC_INTR_STAT_t;
3461 #define ALT_I2C_IC_INTR_STAT_RESET 0x00000000
3463 #define ALT_I2C_IC_INTR_STAT_OFST 0x2c
3465 #define ALT_I2C_IC_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_INTR_STAT_OFST))
3535 #define ALT_I2C_IC_INTR_MASK_M_RX_UNDER_E_ENABLED 0x0
3541 #define ALT_I2C_IC_INTR_MASK_M_RX_UNDER_E_DISABLED 0x1
3544 #define ALT_I2C_IC_INTR_MASK_M_RX_UNDER_LSB 0
3546 #define ALT_I2C_IC_INTR_MASK_M_RX_UNDER_MSB 0
3548 #define ALT_I2C_IC_INTR_MASK_M_RX_UNDER_WIDTH 1
3550 #define ALT_I2C_IC_INTR_MASK_M_RX_UNDER_SET_MSK 0x00000001
3552 #define ALT_I2C_IC_INTR_MASK_M_RX_UNDER_CLR_MSK 0xfffffffe
3554 #define ALT_I2C_IC_INTR_MASK_M_RX_UNDER_RESET 0x1
3556 #define ALT_I2C_IC_INTR_MASK_M_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
3558 #define ALT_I2C_IC_INTR_MASK_M_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
3582 #define ALT_I2C_IC_INTR_MASK_M_RX_OVER_E_ENABLED 0x0
3588 #define ALT_I2C_IC_INTR_MASK_M_RX_OVER_E_DISABLED 0x1
3591 #define ALT_I2C_IC_INTR_MASK_M_RX_OVER_LSB 1
3593 #define ALT_I2C_IC_INTR_MASK_M_RX_OVER_MSB 1
3595 #define ALT_I2C_IC_INTR_MASK_M_RX_OVER_WIDTH 1
3597 #define ALT_I2C_IC_INTR_MASK_M_RX_OVER_SET_MSK 0x00000002
3599 #define ALT_I2C_IC_INTR_MASK_M_RX_OVER_CLR_MSK 0xfffffffd
3601 #define ALT_I2C_IC_INTR_MASK_M_RX_OVER_RESET 0x1
3603 #define ALT_I2C_IC_INTR_MASK_M_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
3605 #define ALT_I2C_IC_INTR_MASK_M_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
3629 #define ALT_I2C_IC_INTR_MASK_M_RX_FULL_E_ENABLED 0x0
3635 #define ALT_I2C_IC_INTR_MASK_M_RX_FULL_E_DISABLED 0x1
3638 #define ALT_I2C_IC_INTR_MASK_M_RX_FULL_LSB 2
3640 #define ALT_I2C_IC_INTR_MASK_M_RX_FULL_MSB 2
3642 #define ALT_I2C_IC_INTR_MASK_M_RX_FULL_WIDTH 1
3644 #define ALT_I2C_IC_INTR_MASK_M_RX_FULL_SET_MSK 0x00000004
3646 #define ALT_I2C_IC_INTR_MASK_M_RX_FULL_CLR_MSK 0xfffffffb
3648 #define ALT_I2C_IC_INTR_MASK_M_RX_FULL_RESET 0x1
3650 #define ALT_I2C_IC_INTR_MASK_M_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
3652 #define ALT_I2C_IC_INTR_MASK_M_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
3676 #define ALT_I2C_IC_INTR_MASK_M_TX_OVER_E_ENABLED 0x0
3682 #define ALT_I2C_IC_INTR_MASK_M_TX_OVER_E_DISABLED 0x1
3685 #define ALT_I2C_IC_INTR_MASK_M_TX_OVER_LSB 3
3687 #define ALT_I2C_IC_INTR_MASK_M_TX_OVER_MSB 3
3689 #define ALT_I2C_IC_INTR_MASK_M_TX_OVER_WIDTH 1
3691 #define ALT_I2C_IC_INTR_MASK_M_TX_OVER_SET_MSK 0x00000008
3693 #define ALT_I2C_IC_INTR_MASK_M_TX_OVER_CLR_MSK 0xfffffff7
3695 #define ALT_I2C_IC_INTR_MASK_M_TX_OVER_RESET 0x1
3697 #define ALT_I2C_IC_INTR_MASK_M_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
3699 #define ALT_I2C_IC_INTR_MASK_M_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
3723 #define ALT_I2C_IC_INTR_MASK_M_TX_EMPTY_E_ENABLED 0x0
3729 #define ALT_I2C_IC_INTR_MASK_M_TX_EMPTY_E_DISABLED 0x1
3732 #define ALT_I2C_IC_INTR_MASK_M_TX_EMPTY_LSB 4
3734 #define ALT_I2C_IC_INTR_MASK_M_TX_EMPTY_MSB 4
3736 #define ALT_I2C_IC_INTR_MASK_M_TX_EMPTY_WIDTH 1
3738 #define ALT_I2C_IC_INTR_MASK_M_TX_EMPTY_SET_MSK 0x00000010
3740 #define ALT_I2C_IC_INTR_MASK_M_TX_EMPTY_CLR_MSK 0xffffffef
3742 #define ALT_I2C_IC_INTR_MASK_M_TX_EMPTY_RESET 0x1
3744 #define ALT_I2C_IC_INTR_MASK_M_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
3746 #define ALT_I2C_IC_INTR_MASK_M_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
3772 #define ALT_I2C_IC_INTR_MASK_M_RD_REQ_E_ENABLED 0x0
3778 #define ALT_I2C_IC_INTR_MASK_M_RD_REQ_E_DISABLED 0x1
3781 #define ALT_I2C_IC_INTR_MASK_M_RD_REQ_LSB 5
3783 #define ALT_I2C_IC_INTR_MASK_M_RD_REQ_MSB 5
3785 #define ALT_I2C_IC_INTR_MASK_M_RD_REQ_WIDTH 1
3787 #define ALT_I2C_IC_INTR_MASK_M_RD_REQ_SET_MSK 0x00000020
3789 #define ALT_I2C_IC_INTR_MASK_M_RD_REQ_CLR_MSK 0xffffffdf
3791 #define ALT_I2C_IC_INTR_MASK_M_RD_REQ_RESET 0x1
3793 #define ALT_I2C_IC_INTR_MASK_M_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
3795 #define ALT_I2C_IC_INTR_MASK_M_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
3819 #define ALT_I2C_IC_INTR_MASK_M_TX_ABRT_E_ENABLED 0x0
3825 #define ALT_I2C_IC_INTR_MASK_M_TX_ABRT_E_DISABLED 0x1
3828 #define ALT_I2C_IC_INTR_MASK_M_TX_ABRT_LSB 6
3830 #define ALT_I2C_IC_INTR_MASK_M_TX_ABRT_MSB 6
3832 #define ALT_I2C_IC_INTR_MASK_M_TX_ABRT_WIDTH 1
3834 #define ALT_I2C_IC_INTR_MASK_M_TX_ABRT_SET_MSK 0x00000040
3836 #define ALT_I2C_IC_INTR_MASK_M_TX_ABRT_CLR_MSK 0xffffffbf
3838 #define ALT_I2C_IC_INTR_MASK_M_TX_ABRT_RESET 0x1
3840 #define ALT_I2C_IC_INTR_MASK_M_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
3842 #define ALT_I2C_IC_INTR_MASK_M_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
3868 #define ALT_I2C_IC_INTR_MASK_M_RX_DONE_E_ENABLED 0x0
3874 #define ALT_I2C_IC_INTR_MASK_M_RX_DONE_E_DISABLED 0x1
3877 #define ALT_I2C_IC_INTR_MASK_M_RX_DONE_LSB 7
3879 #define ALT_I2C_IC_INTR_MASK_M_RX_DONE_MSB 7
3881 #define ALT_I2C_IC_INTR_MASK_M_RX_DONE_WIDTH 1
3883 #define ALT_I2C_IC_INTR_MASK_M_RX_DONE_SET_MSK 0x00000080
3885 #define ALT_I2C_IC_INTR_MASK_M_RX_DONE_CLR_MSK 0xffffff7f
3887 #define ALT_I2C_IC_INTR_MASK_M_RX_DONE_RESET 0x1
3889 #define ALT_I2C_IC_INTR_MASK_M_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
3891 #define ALT_I2C_IC_INTR_MASK_M_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
3915 #define ALT_I2C_IC_INTR_MASK_M_ACTIVITY_E_ENABLED 0x0
3921 #define ALT_I2C_IC_INTR_MASK_M_ACTIVITY_E_DISABLED 0x1
3924 #define ALT_I2C_IC_INTR_MASK_M_ACTIVITY_LSB 8
3926 #define ALT_I2C_IC_INTR_MASK_M_ACTIVITY_MSB 8
3928 #define ALT_I2C_IC_INTR_MASK_M_ACTIVITY_WIDTH 1
3930 #define ALT_I2C_IC_INTR_MASK_M_ACTIVITY_SET_MSK 0x00000100
3932 #define ALT_I2C_IC_INTR_MASK_M_ACTIVITY_CLR_MSK 0xfffffeff
3934 #define ALT_I2C_IC_INTR_MASK_M_ACTIVITY_RESET 0x0
3936 #define ALT_I2C_IC_INTR_MASK_M_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
3938 #define ALT_I2C_IC_INTR_MASK_M_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
3962 #define ALT_I2C_IC_INTR_MASK_M_STOP_DET_E_ENABLED 0x0
3968 #define ALT_I2C_IC_INTR_MASK_M_STOP_DET_E_DISABLED 0x1
3971 #define ALT_I2C_IC_INTR_MASK_M_STOP_DET_LSB 9
3973 #define ALT_I2C_IC_INTR_MASK_M_STOP_DET_MSB 9
3975 #define ALT_I2C_IC_INTR_MASK_M_STOP_DET_WIDTH 1
3977 #define ALT_I2C_IC_INTR_MASK_M_STOP_DET_SET_MSK 0x00000200
3979 #define ALT_I2C_IC_INTR_MASK_M_STOP_DET_CLR_MSK 0xfffffdff
3981 #define ALT_I2C_IC_INTR_MASK_M_STOP_DET_RESET 0x0
3983 #define ALT_I2C_IC_INTR_MASK_M_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
3985 #define ALT_I2C_IC_INTR_MASK_M_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
4009 #define ALT_I2C_IC_INTR_MASK_M_START_DET_E_ENABLED 0x0
4015 #define ALT_I2C_IC_INTR_MASK_M_START_DET_E_DISABLED 0x1
4018 #define ALT_I2C_IC_INTR_MASK_M_START_DET_LSB 10
4020 #define ALT_I2C_IC_INTR_MASK_M_START_DET_MSB 10
4022 #define ALT_I2C_IC_INTR_MASK_M_START_DET_WIDTH 1
4024 #define ALT_I2C_IC_INTR_MASK_M_START_DET_SET_MSK 0x00000400
4026 #define ALT_I2C_IC_INTR_MASK_M_START_DET_CLR_MSK 0xfffffbff
4028 #define ALT_I2C_IC_INTR_MASK_M_START_DET_RESET 0x0
4030 #define ALT_I2C_IC_INTR_MASK_M_START_DET_GET(value) (((value) & 0x00000400) >> 10)
4032 #define ALT_I2C_IC_INTR_MASK_M_START_DET_SET(value) (((value) << 10) & 0x00000400)
4056 #define ALT_I2C_IC_INTR_MASK_M_GEN_CALL_E_ENABLED 0x0
4062 #define ALT_I2C_IC_INTR_MASK_M_GEN_CALL_E_DISABLED 0x1
4065 #define ALT_I2C_IC_INTR_MASK_M_GEN_CALL_LSB 11
4067 #define ALT_I2C_IC_INTR_MASK_M_GEN_CALL_MSB 11
4069 #define ALT_I2C_IC_INTR_MASK_M_GEN_CALL_WIDTH 1
4071 #define ALT_I2C_IC_INTR_MASK_M_GEN_CALL_SET_MSK 0x00000800
4073 #define ALT_I2C_IC_INTR_MASK_M_GEN_CALL_CLR_MSK 0xfffff7ff
4075 #define ALT_I2C_IC_INTR_MASK_M_GEN_CALL_RESET 0x1
4077 #define ALT_I2C_IC_INTR_MASK_M_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
4079 #define ALT_I2C_IC_INTR_MASK_M_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
4103 #define ALT_I2C_IC_INTR_MASK_M_RESTART_DET_E_ENABLED 0x0
4109 #define ALT_I2C_IC_INTR_MASK_M_RESTART_DET_E_DISABLED 0x1
4112 #define ALT_I2C_IC_INTR_MASK_M_RESTART_DET_LSB 12
4114 #define ALT_I2C_IC_INTR_MASK_M_RESTART_DET_MSB 12
4116 #define ALT_I2C_IC_INTR_MASK_M_RESTART_DET_WIDTH 1
4118 #define ALT_I2C_IC_INTR_MASK_M_RESTART_DET_SET_MSK 0x00001000
4120 #define ALT_I2C_IC_INTR_MASK_M_RESTART_DET_CLR_MSK 0xffffefff
4122 #define ALT_I2C_IC_INTR_MASK_M_RESTART_DET_RESET 0x0
4124 #define ALT_I2C_IC_INTR_MASK_M_RESTART_DET_GET(value) (((value) & 0x00001000) >> 12)
4126 #define ALT_I2C_IC_INTR_MASK_M_RESTART_DET_SET(value) (((value) << 12) & 0x00001000)
4150 #define ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_E_ENABLED 0x0
4156 #define ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_E_DISABLED 0x1
4159 #define ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_LSB 13
4161 #define ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_MSB 13
4163 #define ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_WIDTH 1
4165 #define ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_SET_MSK 0x00002000
4167 #define ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_CLR_MSK 0xffffdfff
4169 #define ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_RESET 0x0
4171 #define ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_GET(value) (((value) & 0x00002000) >> 13)
4173 #define ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_SET(value) (((value) << 13) & 0x00002000)
4184 #define ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW_LSB 14
4186 #define ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW_MSB 14
4188 #define ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW_WIDTH 1
4190 #define ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW_SET_MSK 0x00004000
4192 #define ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW_CLR_MSK 0xffffbfff
4194 #define ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW_RESET 0x0
4196 #define ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW_GET(value) (((value) & 0x00004000) >> 14)
4198 #define ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW_SET(value) (((value) << 14) & 0x00004000)
4209 #define ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT_LSB 15
4211 #define ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT_MSB 31
4213 #define ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT_WIDTH 17
4215 #define ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT_SET_MSK 0xffff8000
4217 #define ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT_CLR_MSK 0x00007fff
4219 #define ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT_RESET 0x0
4221 #define ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT_GET(value) (((value) & 0xffff8000) >> 15)
4223 #define ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT_SET(value) (((value) << 15) & 0xffff8000)
4225 #ifndef __ASSEMBLY__
4237 struct ALT_I2C_IC_INTR_MASK_s
4239 volatile uint32_t M_RX_UNDER : 1;
4240 volatile uint32_t M_RX_OVER : 1;
4241 volatile uint32_t M_RX_FULL : 1;
4242 volatile uint32_t M_TX_OVER : 1;
4243 volatile uint32_t M_TX_EMPTY : 1;
4244 volatile uint32_t M_RD_REQ : 1;
4245 volatile uint32_t M_TX_ABRT : 1;
4246 volatile uint32_t M_RX_DONE : 1;
4247 volatile uint32_t M_ACTIVITY : 1;
4248 volatile uint32_t M_STOP_DET : 1;
4249 volatile uint32_t M_START_DET : 1;
4250 volatile uint32_t M_GEN_CALL : 1;
4251 volatile uint32_t M_RESTART_DET : 1;
4252 volatile uint32_t M_MASTER_ON_HOLD : 1;
4253 const volatile uint32_t RSVD_M_SCL_STUCK_AT_LOW : 1;
4254 const volatile uint32_t RSVD_IC_INTR_STAT : 17;
4258 typedef struct ALT_I2C_IC_INTR_MASK_s ALT_I2C_IC_INTR_MASK_t;
4262 #define ALT_I2C_IC_INTR_MASK_RESET 0x000008ff
4264 #define ALT_I2C_IC_INTR_MASK_OFST 0x30
4266 #define ALT_I2C_IC_INTR_MASK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_INTR_MASK_OFST))
4333 #define ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER_E_INACTIVE 0x0
4339 #define ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER_E_ACTIVE 0x1
4342 #define ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER_LSB 0
4344 #define ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER_MSB 0
4346 #define ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER_WIDTH 1
4348 #define ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER_SET_MSK 0x00000001
4350 #define ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER_CLR_MSK 0xfffffffe
4352 #define ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER_RESET 0x0
4354 #define ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
4356 #define ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
4395 #define ALT_I2C_IC_RAW_INTR_STAT_RX_OVER_E_INACTIVE 0x0
4401 #define ALT_I2C_IC_RAW_INTR_STAT_RX_OVER_E_ACTIVE 0x1
4404 #define ALT_I2C_IC_RAW_INTR_STAT_RX_OVER_LSB 1
4406 #define ALT_I2C_IC_RAW_INTR_STAT_RX_OVER_MSB 1
4408 #define ALT_I2C_IC_RAW_INTR_STAT_RX_OVER_WIDTH 1
4410 #define ALT_I2C_IC_RAW_INTR_STAT_RX_OVER_SET_MSK 0x00000002
4412 #define ALT_I2C_IC_RAW_INTR_STAT_RX_OVER_CLR_MSK 0xfffffffd
4414 #define ALT_I2C_IC_RAW_INTR_STAT_RX_OVER_RESET 0x0
4416 #define ALT_I2C_IC_RAW_INTR_STAT_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
4418 #define ALT_I2C_IC_RAW_INTR_STAT_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
4452 #define ALT_I2C_IC_RAW_INTR_STAT_RX_FULL_E_INACTIVE 0x0
4458 #define ALT_I2C_IC_RAW_INTR_STAT_RX_FULL_E_ACTIVE 0x1
4461 #define ALT_I2C_IC_RAW_INTR_STAT_RX_FULL_LSB 2
4463 #define ALT_I2C_IC_RAW_INTR_STAT_RX_FULL_MSB 2
4465 #define ALT_I2C_IC_RAW_INTR_STAT_RX_FULL_WIDTH 1
4467 #define ALT_I2C_IC_RAW_INTR_STAT_RX_FULL_SET_MSK 0x00000004
4469 #define ALT_I2C_IC_RAW_INTR_STAT_RX_FULL_CLR_MSK 0xfffffffb
4471 #define ALT_I2C_IC_RAW_INTR_STAT_RX_FULL_RESET 0x0
4473 #define ALT_I2C_IC_RAW_INTR_STAT_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
4475 #define ALT_I2C_IC_RAW_INTR_STAT_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
4507 #define ALT_I2C_IC_RAW_INTR_STAT_TX_OVER_E_INACTIVE 0x0
4513 #define ALT_I2C_IC_RAW_INTR_STAT_TX_OVER_E_ACTIVE 0x1
4516 #define ALT_I2C_IC_RAW_INTR_STAT_TX_OVER_LSB 3
4518 #define ALT_I2C_IC_RAW_INTR_STAT_TX_OVER_MSB 3
4520 #define ALT_I2C_IC_RAW_INTR_STAT_TX_OVER_WIDTH 1
4522 #define ALT_I2C_IC_RAW_INTR_STAT_TX_OVER_SET_MSK 0x00000008
4524 #define ALT_I2C_IC_RAW_INTR_STAT_TX_OVER_CLR_MSK 0xfffffff7
4526 #define ALT_I2C_IC_RAW_INTR_STAT_TX_OVER_RESET 0x0
4528 #define ALT_I2C_IC_RAW_INTR_STAT_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
4530 #define ALT_I2C_IC_RAW_INTR_STAT_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
4582 #define ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY_E_INACTIVE 0x0
4588 #define ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY_E_ACTIVE 0x1
4591 #define ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY_LSB 4
4593 #define ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY_MSB 4
4595 #define ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY_WIDTH 1
4597 #define ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY_SET_MSK 0x00000010
4599 #define ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY_CLR_MSK 0xffffffef
4601 #define ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY_RESET 0x0
4603 #define ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
4605 #define ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
4644 #define ALT_I2C_IC_RAW_INTR_STAT_RD_REQ_E_INACTIVE 0x0
4650 #define ALT_I2C_IC_RAW_INTR_STAT_RD_REQ_E_ACTIVE 0x1
4653 #define ALT_I2C_IC_RAW_INTR_STAT_RD_REQ_LSB 5
4655 #define ALT_I2C_IC_RAW_INTR_STAT_RD_REQ_MSB 5
4657 #define ALT_I2C_IC_RAW_INTR_STAT_RD_REQ_WIDTH 1
4659 #define ALT_I2C_IC_RAW_INTR_STAT_RD_REQ_SET_MSK 0x00000020
4661 #define ALT_I2C_IC_RAW_INTR_STAT_RD_REQ_CLR_MSK 0xffffffdf
4663 #define ALT_I2C_IC_RAW_INTR_STAT_RD_REQ_RESET 0x0
4665 #define ALT_I2C_IC_RAW_INTR_STAT_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
4667 #define ALT_I2C_IC_RAW_INTR_STAT_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
4716 #define ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT_E_INACTIVE 0x0
4722 #define ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT_E_ACTIVE 0x1
4725 #define ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT_LSB 6
4727 #define ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT_MSB 6
4729 #define ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT_WIDTH 1
4731 #define ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT_SET_MSK 0x00000040
4733 #define ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT_CLR_MSK 0xffffffbf
4735 #define ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT_RESET 0x0
4737 #define ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
4739 #define ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
4771 #define ALT_I2C_IC_RAW_INTR_STAT_RX_DONE_E_INACTIVE 0x0
4777 #define ALT_I2C_IC_RAW_INTR_STAT_RX_DONE_E_ACTIVE 0x1
4780 #define ALT_I2C_IC_RAW_INTR_STAT_RX_DONE_LSB 7
4782 #define ALT_I2C_IC_RAW_INTR_STAT_RX_DONE_MSB 7
4784 #define ALT_I2C_IC_RAW_INTR_STAT_RX_DONE_WIDTH 1
4786 #define ALT_I2C_IC_RAW_INTR_STAT_RX_DONE_SET_MSK 0x00000080
4788 #define ALT_I2C_IC_RAW_INTR_STAT_RX_DONE_CLR_MSK 0xffffff7f
4790 #define ALT_I2C_IC_RAW_INTR_STAT_RX_DONE_RESET 0x0
4792 #define ALT_I2C_IC_RAW_INTR_STAT_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
4794 #define ALT_I2C_IC_RAW_INTR_STAT_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
4835 #define ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY_E_INACTIVE 0x0
4841 #define ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY_E_ACTIVE 0x1
4844 #define ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY_LSB 8
4846 #define ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY_MSB 8
4848 #define ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY_WIDTH 1
4850 #define ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY_SET_MSK 0x00000100
4852 #define ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY_CLR_MSK 0xfffffeff
4854 #define ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY_RESET 0x0
4856 #define ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
4858 #define ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
4912 #define ALT_I2C_IC_RAW_INTR_STAT_STOP_DET_E_INACTIVE 0x0
4918 #define ALT_I2C_IC_RAW_INTR_STAT_STOP_DET_E_ACTIVE 0x1
4921 #define ALT_I2C_IC_RAW_INTR_STAT_STOP_DET_LSB 9
4923 #define ALT_I2C_IC_RAW_INTR_STAT_STOP_DET_MSB 9
4925 #define ALT_I2C_IC_RAW_INTR_STAT_STOP_DET_WIDTH 1
4927 #define ALT_I2C_IC_RAW_INTR_STAT_STOP_DET_SET_MSK 0x00000200
4929 #define ALT_I2C_IC_RAW_INTR_STAT_STOP_DET_CLR_MSK 0xfffffdff
4931 #define ALT_I2C_IC_RAW_INTR_STAT_STOP_DET_RESET 0x0
4933 #define ALT_I2C_IC_RAW_INTR_STAT_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
4935 #define ALT_I2C_IC_RAW_INTR_STAT_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
4963 #define ALT_I2C_IC_RAW_INTR_STAT_START_DET_E_INACTIVE 0x0
4969 #define ALT_I2C_IC_RAW_INTR_STAT_START_DET_E_ACTIVE 0x1
4972 #define ALT_I2C_IC_RAW_INTR_STAT_START_DET_LSB 10
4974 #define ALT_I2C_IC_RAW_INTR_STAT_START_DET_MSB 10
4976 #define ALT_I2C_IC_RAW_INTR_STAT_START_DET_WIDTH 1
4978 #define ALT_I2C_IC_RAW_INTR_STAT_START_DET_SET_MSK 0x00000400
4980 #define ALT_I2C_IC_RAW_INTR_STAT_START_DET_CLR_MSK 0xfffffbff
4982 #define ALT_I2C_IC_RAW_INTR_STAT_START_DET_RESET 0x0
4984 #define ALT_I2C_IC_RAW_INTR_STAT_START_DET_GET(value) (((value) & 0x00000400) >> 10)
4986 #define ALT_I2C_IC_RAW_INTR_STAT_START_DET_SET(value) (((value) << 10) & 0x00000400)
5016 #define ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL_E_INACTIVE 0x0
5022 #define ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL_E_ACTIVE 0x1
5025 #define ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL_LSB 11
5027 #define ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL_MSB 11
5029 #define ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL_WIDTH 1
5031 #define ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL_SET_MSK 0x00000800
5033 #define ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL_CLR_MSK 0xfffff7ff
5035 #define ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL_RESET 0x0
5037 #define ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
5039 #define ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
5075 #define ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET_E_INACTIVE 0x0
5081 #define ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET_E_ACTIVE 0x1
5084 #define ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET_LSB 12
5086 #define ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET_MSB 12
5088 #define ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET_WIDTH 1
5090 #define ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET_SET_MSK 0x00001000
5092 #define ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET_CLR_MSK 0xffffefff
5094 #define ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET_RESET 0x0
5096 #define ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET_GET(value) (((value) & 0x00001000) >> 12)
5098 #define ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET_SET(value) (((value) << 12) & 0x00001000)
5124 #define ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_E_INACTIVE 0x0
5130 #define ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_E_ACTIVE 0x1
5133 #define ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_LSB 13
5135 #define ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_MSB 13
5137 #define ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_WIDTH 1
5139 #define ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_SET_MSK 0x00002000
5141 #define ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_CLR_MSK 0xffffdfff
5143 #define ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_RESET 0x0
5145 #define ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_GET(value) (((value) & 0x00002000) >> 13)
5147 #define ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_SET(value) (((value) << 13) & 0x00002000)
5158 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW_LSB 14
5160 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW_MSB 14
5162 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW_WIDTH 1
5164 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW_SET_MSK 0x00004000
5166 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW_CLR_MSK 0xffffbfff
5168 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW_RESET 0x0
5170 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW_GET(value) (((value) & 0x00004000) >> 14)
5172 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW_SET(value) (((value) << 14) & 0x00004000)
5183 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT_LSB 15
5185 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT_MSB 31
5187 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT_WIDTH 17
5189 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT_SET_MSK 0xffff8000
5191 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT_CLR_MSK 0x00007fff
5193 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT_RESET 0x0
5195 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT_GET(value) (((value) & 0xffff8000) >> 15)
5197 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT_SET(value) (((value) << 15) & 0xffff8000)
5199 #ifndef __ASSEMBLY__
5211 struct ALT_I2C_IC_RAW_INTR_STAT_s
5213 const volatile uint32_t RX_UNDER : 1;
5214 const volatile uint32_t RX_OVER : 1;
5215 const volatile uint32_t RX_FULL : 1;
5216 const volatile uint32_t TX_OVER : 1;
5217 const volatile uint32_t TX_EMPTY : 1;
5218 const volatile uint32_t RD_REQ : 1;
5219 const volatile uint32_t TX_ABRT : 1;
5220 const volatile uint32_t RX_DONE : 1;
5221 const volatile uint32_t RAW_INTR_ACTIVITY : 1;
5222 const volatile uint32_t STOP_DET : 1;
5223 const volatile uint32_t START_DET : 1;
5224 const volatile uint32_t GEN_CALL : 1;
5225 const volatile uint32_t RESTART_DET : 1;
5226 const volatile uint32_t MASTER_ON_HOLD : 1;
5227 const volatile uint32_t RSVD_SCL_STUCK_AT_LOW : 1;
5228 const volatile uint32_t RSVD_IC_RAW_INTR_STAT : 17;
5232 typedef struct ALT_I2C_IC_RAW_INTR_STAT_s ALT_I2C_IC_RAW_INTR_STAT_t;
5236 #define ALT_I2C_IC_RAW_INTR_STAT_RESET 0x00000000
5238 #define ALT_I2C_IC_RAW_INTR_STAT_OFST 0x34
5240 #define ALT_I2C_IC_RAW_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_RAW_INTR_STAT_OFST))
5288 #define ALT_I2C_IC_RX_TL_RX_TL_LSB 0
5290 #define ALT_I2C_IC_RX_TL_RX_TL_MSB 7
5292 #define ALT_I2C_IC_RX_TL_RX_TL_WIDTH 8
5294 #define ALT_I2C_IC_RX_TL_RX_TL_SET_MSK 0x000000ff
5296 #define ALT_I2C_IC_RX_TL_RX_TL_CLR_MSK 0xffffff00
5298 #define ALT_I2C_IC_RX_TL_RX_TL_RESET 0x0
5300 #define ALT_I2C_IC_RX_TL_RX_TL_GET(value) (((value) & 0x000000ff) >> 0)
5302 #define ALT_I2C_IC_RX_TL_RX_TL_SET(value) (((value) << 0) & 0x000000ff)
5313 #define ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL_LSB 8
5315 #define ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL_MSB 31
5317 #define ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL_WIDTH 24
5319 #define ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL_SET_MSK 0xffffff00
5321 #define ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL_CLR_MSK 0x000000ff
5323 #define ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL_RESET 0x0
5325 #define ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL_GET(value) (((value) & 0xffffff00) >> 8)
5327 #define ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL_SET(value) (((value) << 8) & 0xffffff00)
5329 #ifndef __ASSEMBLY__
5341 struct ALT_I2C_IC_RX_TL_s
5343 volatile uint32_t RX_TL : 8;
5344 const volatile uint32_t RSVD_IC_RX_TL : 24;
5348 typedef struct ALT_I2C_IC_RX_TL_s ALT_I2C_IC_RX_TL_t;
5352 #define ALT_I2C_IC_RX_TL_RESET 0x00000000
5354 #define ALT_I2C_IC_RX_TL_OFST 0x38
5356 #define ALT_I2C_IC_RX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_RX_TL_OFST))
5404 #define ALT_I2C_IC_TX_TL_TX_TL_LSB 0
5406 #define ALT_I2C_IC_TX_TL_TX_TL_MSB 7
5408 #define ALT_I2C_IC_TX_TL_TX_TL_WIDTH 8
5410 #define ALT_I2C_IC_TX_TL_TX_TL_SET_MSK 0x000000ff
5412 #define ALT_I2C_IC_TX_TL_TX_TL_CLR_MSK 0xffffff00
5414 #define ALT_I2C_IC_TX_TL_TX_TL_RESET 0x0
5416 #define ALT_I2C_IC_TX_TL_TX_TL_GET(value) (((value) & 0x000000ff) >> 0)
5418 #define ALT_I2C_IC_TX_TL_TX_TL_SET(value) (((value) << 0) & 0x000000ff)
5429 #define ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL_LSB 8
5431 #define ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL_MSB 31
5433 #define ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL_WIDTH 24
5435 #define ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL_SET_MSK 0xffffff00
5437 #define ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL_CLR_MSK 0x000000ff
5439 #define ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL_RESET 0x0
5441 #define ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL_GET(value) (((value) & 0xffffff00) >> 8)
5443 #define ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL_SET(value) (((value) << 8) & 0xffffff00)
5445 #ifndef __ASSEMBLY__
5457 struct ALT_I2C_IC_TX_TL_s
5459 volatile uint32_t TX_TL : 8;
5460 const volatile uint32_t RSVD_IC_TX_TL : 24;
5464 typedef struct ALT_I2C_IC_TX_TL_s ALT_I2C_IC_TX_TL_t;
5468 #define ALT_I2C_IC_TX_TL_RESET 0x00000000
5470 #define ALT_I2C_IC_TX_TL_OFST 0x3c
5472 #define ALT_I2C_IC_TX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_TX_TL_OFST))
5512 #define ALT_I2C_IC_CLR_INTR_CLR_INTR_LSB 0
5514 #define ALT_I2C_IC_CLR_INTR_CLR_INTR_MSB 0
5516 #define ALT_I2C_IC_CLR_INTR_CLR_INTR_WIDTH 1
5518 #define ALT_I2C_IC_CLR_INTR_CLR_INTR_SET_MSK 0x00000001
5520 #define ALT_I2C_IC_CLR_INTR_CLR_INTR_CLR_MSK 0xfffffffe
5522 #define ALT_I2C_IC_CLR_INTR_CLR_INTR_RESET 0x0
5524 #define ALT_I2C_IC_CLR_INTR_CLR_INTR_GET(value) (((value) & 0x00000001) >> 0)
5526 #define ALT_I2C_IC_CLR_INTR_CLR_INTR_SET(value) (((value) << 0) & 0x00000001)
5537 #define ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR_LSB 1
5539 #define ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR_MSB 31
5541 #define ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR_WIDTH 31
5543 #define ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR_SET_MSK 0xfffffffe
5545 #define ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR_CLR_MSK 0x00000001
5547 #define ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR_RESET 0x0
5549 #define ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR_GET(value) (((value) & 0xfffffffe) >> 1)
5551 #define ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR_SET(value) (((value) << 1) & 0xfffffffe)
5553 #ifndef __ASSEMBLY__
5565 struct ALT_I2C_IC_CLR_INTR_s
5567 const volatile uint32_t CLR_INTR : 1;
5568 const volatile uint32_t RSVD_IC_CLR_INTR : 31;
5572 typedef struct ALT_I2C_IC_CLR_INTR_s ALT_I2C_IC_CLR_INTR_t;
5576 #define ALT_I2C_IC_CLR_INTR_RESET 0x00000000
5578 #define ALT_I2C_IC_CLR_INTR_OFST 0x40
5580 #define ALT_I2C_IC_CLR_INTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_INTR_OFST))
5614 #define ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_LSB 0
5616 #define ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_MSB 0
5618 #define ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_WIDTH 1
5620 #define ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_SET_MSK 0x00000001
5622 #define ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_CLR_MSK 0xfffffffe
5624 #define ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_RESET 0x0
5626 #define ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
5628 #define ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
5639 #define ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER_LSB 1
5641 #define ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER_MSB 31
5643 #define ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER_WIDTH 31
5645 #define ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER_SET_MSK 0xfffffffe
5647 #define ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER_CLR_MSK 0x00000001
5649 #define ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER_RESET 0x0
5651 #define ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER_GET(value) (((value) & 0xfffffffe) >> 1)
5653 #define ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER_SET(value) (((value) << 1) & 0xfffffffe)
5655 #ifndef __ASSEMBLY__
5667 struct ALT_I2C_IC_CLR_RX_UNDER_s
5669 const volatile uint32_t CLR_RX_UNDER : 1;
5670 const volatile uint32_t RSVD_IC_CLR_RX_UNDER : 31;
5674 typedef struct ALT_I2C_IC_CLR_RX_UNDER_s ALT_I2C_IC_CLR_RX_UNDER_t;
5678 #define ALT_I2C_IC_CLR_RX_UNDER_RESET 0x00000000
5680 #define ALT_I2C_IC_CLR_RX_UNDER_OFST 0x44
5682 #define ALT_I2C_IC_CLR_RX_UNDER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_RX_UNDER_OFST))
5716 #define ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER_LSB 0
5718 #define ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER_MSB 0
5720 #define ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER_WIDTH 1
5722 #define ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER_SET_MSK 0x00000001
5724 #define ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER_CLR_MSK 0xfffffffe
5726 #define ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER_RESET 0x0
5728 #define ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER_GET(value) (((value) & 0x00000001) >> 0)
5730 #define ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER_SET(value) (((value) << 0) & 0x00000001)
5741 #define ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER_LSB 1
5743 #define ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER_MSB 31
5745 #define ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER_WIDTH 31
5747 #define ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER_SET_MSK 0xfffffffe
5749 #define ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER_CLR_MSK 0x00000001
5751 #define ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER_RESET 0x0
5753 #define ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER_GET(value) (((value) & 0xfffffffe) >> 1)
5755 #define ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER_SET(value) (((value) << 1) & 0xfffffffe)
5757 #ifndef __ASSEMBLY__
5769 struct ALT_I2C_IC_CLR_RX_OVER_s
5771 const volatile uint32_t CLR_RX_OVER : 1;
5772 const volatile uint32_t RSVD_IC_CLR_RX_OVER : 31;
5776 typedef struct ALT_I2C_IC_CLR_RX_OVER_s ALT_I2C_IC_CLR_RX_OVER_t;
5780 #define ALT_I2C_IC_CLR_RX_OVER_RESET 0x00000000
5782 #define ALT_I2C_IC_CLR_RX_OVER_OFST 0x48
5784 #define ALT_I2C_IC_CLR_RX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_RX_OVER_OFST))
5818 #define ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER_LSB 0
5820 #define ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER_MSB 0
5822 #define ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER_WIDTH 1
5824 #define ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER_SET_MSK 0x00000001
5826 #define ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER_CLR_MSK 0xfffffffe
5828 #define ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER_RESET 0x0
5830 #define ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER_GET(value) (((value) & 0x00000001) >> 0)
5832 #define ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER_SET(value) (((value) << 0) & 0x00000001)
5843 #define ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER_LSB 1
5845 #define ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER_MSB 31
5847 #define ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER_WIDTH 31
5849 #define ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER_SET_MSK 0xfffffffe
5851 #define ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER_CLR_MSK 0x00000001
5853 #define ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER_RESET 0x0
5855 #define ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER_GET(value) (((value) & 0xfffffffe) >> 1)
5857 #define ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER_SET(value) (((value) << 1) & 0xfffffffe)
5859 #ifndef __ASSEMBLY__
5871 struct ALT_I2C_IC_CLR_TX_OVER_s
5873 const volatile uint32_t CLR_TX_OVER : 1;
5874 const volatile uint32_t RSVD_IC_CLR_TX_OVER : 31;
5878 typedef struct ALT_I2C_IC_CLR_TX_OVER_s ALT_I2C_IC_CLR_TX_OVER_t;
5882 #define ALT_I2C_IC_CLR_TX_OVER_RESET 0x00000000
5884 #define ALT_I2C_IC_CLR_TX_OVER_OFST 0x4c
5886 #define ALT_I2C_IC_CLR_TX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_TX_OVER_OFST))
5922 #define ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ_LSB 0
5924 #define ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ_MSB 0
5926 #define ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ_WIDTH 1
5928 #define ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ_SET_MSK 0x00000001
5930 #define ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ_CLR_MSK 0xfffffffe
5932 #define ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ_RESET 0x0
5934 #define ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ_GET(value) (((value) & 0x00000001) >> 0)
5936 #define ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ_SET(value) (((value) << 0) & 0x00000001)
5947 #define ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ_LSB 1
5949 #define ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ_MSB 31
5951 #define ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ_WIDTH 31
5953 #define ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ_SET_MSK 0xfffffffe
5955 #define ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ_CLR_MSK 0x00000001
5957 #define ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ_RESET 0x0
5959 #define ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ_GET(value) (((value) & 0xfffffffe) >> 1)
5961 #define ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ_SET(value) (((value) << 1) & 0xfffffffe)
5963 #ifndef __ASSEMBLY__
5975 struct ALT_I2C_IC_CLR_RD_REQ_s
5977 const volatile uint32_t CLR_RD_REQ : 1;
5978 const volatile uint32_t RSVD_IC_CLR_RD_REQ : 31;
5982 typedef struct ALT_I2C_IC_CLR_RD_REQ_s ALT_I2C_IC_CLR_RD_REQ_t;
5986 #define ALT_I2C_IC_CLR_RD_REQ_RESET 0x00000000
5988 #define ALT_I2C_IC_CLR_RD_REQ_OFST 0x50
5990 #define ALT_I2C_IC_CLR_RD_REQ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_RD_REQ_OFST))
6034 #define ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_LSB 0
6036 #define ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_MSB 0
6038 #define ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_WIDTH 1
6040 #define ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_SET_MSK 0x00000001
6042 #define ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_CLR_MSK 0xfffffffe
6044 #define ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_RESET 0x0
6046 #define ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_GET(value) (((value) & 0x00000001) >> 0)
6048 #define ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_SET(value) (((value) << 0) & 0x00000001)
6059 #define ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT_LSB 1
6061 #define ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT_MSB 31
6063 #define ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT_WIDTH 31
6065 #define ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT_SET_MSK 0xfffffffe
6067 #define ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT_CLR_MSK 0x00000001
6069 #define ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT_RESET 0x0
6071 #define ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT_GET(value) (((value) & 0xfffffffe) >> 1)
6073 #define ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT_SET(value) (((value) << 1) & 0xfffffffe)
6075 #ifndef __ASSEMBLY__
6087 struct ALT_I2C_IC_CLR_TX_ABRT_s
6089 const volatile uint32_t CLR_TX_ABRT : 1;
6090 const volatile uint32_t RSVD_IC_CLR_TX_ABRT : 31;
6094 typedef struct ALT_I2C_IC_CLR_TX_ABRT_s ALT_I2C_IC_CLR_TX_ABRT_t;
6098 #define ALT_I2C_IC_CLR_TX_ABRT_RESET 0x00000000
6100 #define ALT_I2C_IC_CLR_TX_ABRT_OFST 0x54
6102 #define ALT_I2C_IC_CLR_TX_ABRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_TX_ABRT_OFST))
6138 #define ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE_LSB 0
6140 #define ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE_MSB 0
6142 #define ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE_WIDTH 1
6144 #define ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE_SET_MSK 0x00000001
6146 #define ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE_CLR_MSK 0xfffffffe
6148 #define ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE_RESET 0x0
6150 #define ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE_GET(value) (((value) & 0x00000001) >> 0)
6152 #define ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE_SET(value) (((value) << 0) & 0x00000001)
6163 #define ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE_LSB 1
6165 #define ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE_MSB 31
6167 #define ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE_WIDTH 31
6169 #define ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE_SET_MSK 0xfffffffe
6171 #define ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE_CLR_MSK 0x00000001
6173 #define ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE_RESET 0x0
6175 #define ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE_GET(value) (((value) & 0xfffffffe) >> 1)
6177 #define ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE_SET(value) (((value) << 1) & 0xfffffffe)
6179 #ifndef __ASSEMBLY__
6191 struct ALT_I2C_IC_CLR_RX_DONE_s
6193 const volatile uint32_t CLR_RX_DONE : 1;
6194 const volatile uint32_t RSVD_IC_CLR_RX_DONE : 31;
6198 typedef struct ALT_I2C_IC_CLR_RX_DONE_s ALT_I2C_IC_CLR_RX_DONE_t;
6202 #define ALT_I2C_IC_CLR_RX_DONE_RESET 0x00000000
6204 #define ALT_I2C_IC_CLR_RX_DONE_OFST 0x58
6206 #define ALT_I2C_IC_CLR_RX_DONE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_RX_DONE_OFST))
6252 #define ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_LSB 0
6254 #define ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_MSB 0
6256 #define ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_WIDTH 1
6258 #define ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_SET_MSK 0x00000001
6260 #define ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_CLR_MSK 0xfffffffe
6262 #define ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_RESET 0x0
6264 #define ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0)
6266 #define ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_SET(value) (((value) << 0) & 0x00000001)
6277 #define ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY_LSB 1
6279 #define ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY_MSB 31
6281 #define ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY_WIDTH 31
6283 #define ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY_SET_MSK 0xfffffffe
6285 #define ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY_CLR_MSK 0x00000001
6287 #define ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY_RESET 0x0
6289 #define ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY_GET(value) (((value) & 0xfffffffe) >> 1)
6291 #define ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY_SET(value) (((value) << 1) & 0xfffffffe)
6293 #ifndef __ASSEMBLY__
6305 struct ALT_I2C_IC_CLR_ACTIVITY_s
6307 const volatile uint32_t CLR_ACTIVITY : 1;
6308 const volatile uint32_t RSVD_IC_CLR_ACTIVITY : 31;
6312 typedef struct ALT_I2C_IC_CLR_ACTIVITY_s ALT_I2C_IC_CLR_ACTIVITY_t;
6316 #define ALT_I2C_IC_CLR_ACTIVITY_RESET 0x00000000
6318 #define ALT_I2C_IC_CLR_ACTIVITY_OFST 0x5c
6320 #define ALT_I2C_IC_CLR_ACTIVITY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_ACTIVITY_OFST))
6354 #define ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET_LSB 0
6356 #define ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET_MSB 0
6358 #define ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET_WIDTH 1
6360 #define ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET_SET_MSK 0x00000001
6362 #define ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET_CLR_MSK 0xfffffffe
6364 #define ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET_RESET 0x0
6366 #define ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET_GET(value) (((value) & 0x00000001) >> 0)
6368 #define ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET_SET(value) (((value) << 0) & 0x00000001)
6379 #define ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET_LSB 1
6381 #define ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET_MSB 31
6383 #define ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET_WIDTH 31
6385 #define ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET_SET_MSK 0xfffffffe
6387 #define ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET_CLR_MSK 0x00000001
6389 #define ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET_RESET 0x0
6391 #define ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET_GET(value) (((value) & 0xfffffffe) >> 1)
6393 #define ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET_SET(value) (((value) << 1) & 0xfffffffe)
6395 #ifndef __ASSEMBLY__
6407 struct ALT_I2C_IC_CLR_STOP_DET_s
6409 const volatile uint32_t CLR_STOP_DET : 1;
6410 const volatile uint32_t RSVD_IC_CLR_STOP_DET : 31;
6414 typedef struct ALT_I2C_IC_CLR_STOP_DET_s ALT_I2C_IC_CLR_STOP_DET_t;
6418 #define ALT_I2C_IC_CLR_STOP_DET_RESET 0x00000000
6420 #define ALT_I2C_IC_CLR_STOP_DET_OFST 0x60
6422 #define ALT_I2C_IC_CLR_STOP_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_STOP_DET_OFST))
6456 #define ALT_I2C_IC_CLR_START_DET_CLR_START_DET_LSB 0
6458 #define ALT_I2C_IC_CLR_START_DET_CLR_START_DET_MSB 0
6460 #define ALT_I2C_IC_CLR_START_DET_CLR_START_DET_WIDTH 1
6462 #define ALT_I2C_IC_CLR_START_DET_CLR_START_DET_SET_MSK 0x00000001
6464 #define ALT_I2C_IC_CLR_START_DET_CLR_START_DET_CLR_MSK 0xfffffffe
6466 #define ALT_I2C_IC_CLR_START_DET_CLR_START_DET_RESET 0x0
6468 #define ALT_I2C_IC_CLR_START_DET_CLR_START_DET_GET(value) (((value) & 0x00000001) >> 0)
6470 #define ALT_I2C_IC_CLR_START_DET_CLR_START_DET_SET(value) (((value) << 0) & 0x00000001)
6481 #define ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET_LSB 1
6483 #define ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET_MSB 31
6485 #define ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET_WIDTH 31
6487 #define ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET_SET_MSK 0xfffffffe
6489 #define ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET_CLR_MSK 0x00000001
6491 #define ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET_RESET 0x0
6493 #define ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET_GET(value) (((value) & 0xfffffffe) >> 1)
6495 #define ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET_SET(value) (((value) << 1) & 0xfffffffe)
6497 #ifndef __ASSEMBLY__
6509 struct ALT_I2C_IC_CLR_START_DET_s
6511 const volatile uint32_t CLR_START_DET : 1;
6512 const volatile uint32_t RSVD_IC_CLR_START_DET : 31;
6516 typedef struct ALT_I2C_IC_CLR_START_DET_s ALT_I2C_IC_CLR_START_DET_t;
6520 #define ALT_I2C_IC_CLR_START_DET_RESET 0x00000000
6522 #define ALT_I2C_IC_CLR_START_DET_OFST 0x64
6524 #define ALT_I2C_IC_CLR_START_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_START_DET_OFST))
6558 #define ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_LSB 0
6560 #define ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_MSB 0
6562 #define ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_WIDTH 1
6564 #define ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_SET_MSK 0x00000001
6566 #define ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_CLR_MSK 0xfffffffe
6568 #define ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_RESET 0x0
6570 #define ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0)
6572 #define ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_SET(value) (((value) << 0) & 0x00000001)
6583 #define ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL_LSB 1
6585 #define ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL_MSB 31
6587 #define ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL_WIDTH 31
6589 #define ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL_SET_MSK 0xfffffffe
6591 #define ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL_CLR_MSK 0x00000001
6593 #define ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL_RESET 0x0
6595 #define ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL_GET(value) (((value) & 0xfffffffe) >> 1)
6597 #define ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL_SET(value) (((value) << 1) & 0xfffffffe)
6599 #ifndef __ASSEMBLY__
6611 struct ALT_I2C_IC_CLR_GEN_CALL_s
6613 const volatile uint32_t CLR_GEN_CALL : 1;
6614 const volatile uint32_t RSVD_IC_CLR_GEN_CALL : 31;
6618 typedef struct ALT_I2C_IC_CLR_GEN_CALL_s ALT_I2C_IC_CLR_GEN_CALL_t;
6622 #define ALT_I2C_IC_CLR_GEN_CALL_RESET 0x00000000
6624 #define ALT_I2C_IC_CLR_GEN_CALL_OFST 0x68
6626 #define ALT_I2C_IC_CLR_GEN_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_GEN_CALL_OFST))
6716 #define ALT_I2C_IC_ENABLE_ENABLE_E_DISABLED 0x0
6722 #define ALT_I2C_IC_ENABLE_ENABLE_E_ENABLED 0x1
6725 #define ALT_I2C_IC_ENABLE_ENABLE_LSB 0
6727 #define ALT_I2C_IC_ENABLE_ENABLE_MSB 0
6729 #define ALT_I2C_IC_ENABLE_ENABLE_WIDTH 1
6731 #define ALT_I2C_IC_ENABLE_ENABLE_SET_MSK 0x00000001
6733 #define ALT_I2C_IC_ENABLE_ENABLE_CLR_MSK 0xfffffffe
6735 #define ALT_I2C_IC_ENABLE_ENABLE_RESET 0x0
6737 #define ALT_I2C_IC_ENABLE_ENABLE_GET(value) (((value) & 0x00000001) >> 0)
6739 #define ALT_I2C_IC_ENABLE_ENABLE_SET(value) (((value) << 0) & 0x00000001)
6784 #define ALT_I2C_IC_ENABLE_ABORT_E_DISABLE 0x0
6790 #define ALT_I2C_IC_ENABLE_ABORT_E_ENABLED 0x1
6793 #define ALT_I2C_IC_ENABLE_ABORT_LSB 1
6795 #define ALT_I2C_IC_ENABLE_ABORT_MSB 1
6797 #define ALT_I2C_IC_ENABLE_ABORT_WIDTH 1
6799 #define ALT_I2C_IC_ENABLE_ABORT_SET_MSK 0x00000002
6801 #define ALT_I2C_IC_ENABLE_ABORT_CLR_MSK 0xfffffffd
6803 #define ALT_I2C_IC_ENABLE_ABORT_RESET 0x0
6805 #define ALT_I2C_IC_ENABLE_ABORT_GET(value) (((value) & 0x00000002) >> 1)
6807 #define ALT_I2C_IC_ENABLE_ABORT_SET(value) (((value) << 1) & 0x00000002)
6848 #define ALT_I2C_IC_ENABLE_TX_CMD_BLOCK_E_NOT_BLOCKED 0x0
6854 #define ALT_I2C_IC_ENABLE_TX_CMD_BLOCK_E_BLOCKED 0x1
6857 #define ALT_I2C_IC_ENABLE_TX_CMD_BLOCK_LSB 2
6859 #define ALT_I2C_IC_ENABLE_TX_CMD_BLOCK_MSB 2
6861 #define ALT_I2C_IC_ENABLE_TX_CMD_BLOCK_WIDTH 1
6863 #define ALT_I2C_IC_ENABLE_TX_CMD_BLOCK_SET_MSK 0x00000004
6865 #define ALT_I2C_IC_ENABLE_TX_CMD_BLOCK_CLR_MSK 0xfffffffb
6867 #define ALT_I2C_IC_ENABLE_TX_CMD_BLOCK_RESET 0x0
6869 #define ALT_I2C_IC_ENABLE_TX_CMD_BLOCK_GET(value) (((value) & 0x00000004) >> 2)
6871 #define ALT_I2C_IC_ENABLE_TX_CMD_BLOCK_SET(value) (((value) << 2) & 0x00000004)
6882 #define ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE_LSB 3
6884 #define ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE_MSB 3
6886 #define ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE_WIDTH 1
6888 #define ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE_SET_MSK 0x00000008
6890 #define ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE_CLR_MSK 0xfffffff7
6892 #define ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE_RESET 0x0
6894 #define ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE_GET(value) (((value) & 0x00000008) >> 3)
6896 #define ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE_SET(value) (((value) << 3) & 0x00000008)
6907 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1_LSB 4
6909 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1_MSB 15
6911 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1_WIDTH 12
6913 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1_SET_MSK 0x0000fff0
6915 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1_CLR_MSK 0xffff000f
6917 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1_RESET 0x0
6919 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1_GET(value) (((value) & 0x0000fff0) >> 4)
6921 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1_SET(value) (((value) << 4) & 0x0000fff0)
6932 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET_LSB 16
6934 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET_MSB 16
6936 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET_WIDTH 1
6938 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET_SET_MSK 0x00010000
6940 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET_CLR_MSK 0xfffeffff
6942 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET_RESET 0x0
6944 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET_GET(value) (((value) & 0x00010000) >> 16)
6946 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET_SET(value) (((value) << 16) & 0x00010000)
6957 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN_LSB 17
6959 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN_MSB 17
6961 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN_WIDTH 1
6963 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN_SET_MSK 0x00020000
6965 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN_CLR_MSK 0xfffdffff
6967 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN_RESET 0x0
6969 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN_GET(value) (((value) & 0x00020000) >> 17)
6971 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN_SET(value) (((value) << 17) & 0x00020000)
6982 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN_LSB 18
6984 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN_MSB 18
6986 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN_WIDTH 1
6988 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN_SET_MSK 0x00040000
6990 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN_CLR_MSK 0xfffbffff
6992 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN_RESET 0x0
6994 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN_GET(value) (((value) & 0x00040000) >> 18)
6996 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN_SET(value) (((value) << 18) & 0x00040000)
7007 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2_LSB 19
7009 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2_MSB 31
7011 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2_WIDTH 13
7013 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2_SET_MSK 0xfff80000
7015 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2_CLR_MSK 0x0007ffff
7017 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2_RESET 0x0
7019 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2_GET(value) (((value) & 0xfff80000) >> 19)
7021 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2_SET(value) (((value) << 19) & 0xfff80000)
7023 #ifndef __ASSEMBLY__
7035 struct ALT_I2C_IC_ENABLE_s
7037 volatile uint32_t ENABLE : 1;
7038 volatile uint32_t ABORT : 1;
7039 volatile uint32_t TX_CMD_BLOCK : 1;
7040 const volatile uint32_t RSVD_SDA_STUCK_RECOVERY_ENABLE : 1;
7041 const volatile uint32_t RSVD_IC_ENABLE_1 : 12;
7042 const volatile uint32_t RSVD_SMBUS_CLK_RESET : 1;
7043 const volatile uint32_t RSVD_SMBUS_SUSPEND_EN : 1;
7044 const volatile uint32_t RSVD_SMBUS_ALERT_EN : 1;
7045 const volatile uint32_t RSVD_IC_ENABLE_2 : 13;
7049 typedef struct ALT_I2C_IC_ENABLE_s ALT_I2C_IC_ENABLE_t;
7053 #define ALT_I2C_IC_ENABLE_RESET 0x00000000
7055 #define ALT_I2C_IC_ENABLE_OFST 0x6c
7057 #define ALT_I2C_IC_ENABLE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_ENABLE_OFST))
7139 #define ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY_E_INACTIVE 0x0
7145 #define ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY_E_ACTIVE 0x1
7148 #define ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY_LSB 0
7150 #define ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY_MSB 0
7152 #define ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY_WIDTH 1
7154 #define ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY_SET_MSK 0x00000001
7156 #define ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY_CLR_MSK 0xfffffffe
7158 #define ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY_RESET 0x0
7160 #define ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0)
7162 #define ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY_SET(value) (((value) << 0) & 0x00000001)
7194 #define ALT_I2C_IC_STATUS_TFNF_E_FULL 0x0
7200 #define ALT_I2C_IC_STATUS_TFNF_E_NOT_FULL 0x1
7203 #define ALT_I2C_IC_STATUS_TFNF_LSB 1
7205 #define ALT_I2C_IC_STATUS_TFNF_MSB 1
7207 #define ALT_I2C_IC_STATUS_TFNF_WIDTH 1
7209 #define ALT_I2C_IC_STATUS_TFNF_SET_MSK 0x00000002
7211 #define ALT_I2C_IC_STATUS_TFNF_CLR_MSK 0xfffffffd
7213 #define ALT_I2C_IC_STATUS_TFNF_RESET 0x1
7215 #define ALT_I2C_IC_STATUS_TFNF_GET(value) (((value) & 0x00000002) >> 1)
7217 #define ALT_I2C_IC_STATUS_TFNF_SET(value) (((value) << 1) & 0x00000002)
7251 #define ALT_I2C_IC_STATUS_TFE_E_NON_EMPTY 0x0
7257 #define ALT_I2C_IC_STATUS_TFE_E_EMPTY 0x1
7260 #define ALT_I2C_IC_STATUS_TFE_LSB 2
7262 #define ALT_I2C_IC_STATUS_TFE_MSB 2
7264 #define ALT_I2C_IC_STATUS_TFE_WIDTH 1
7266 #define ALT_I2C_IC_STATUS_TFE_SET_MSK 0x00000004
7268 #define ALT_I2C_IC_STATUS_TFE_CLR_MSK 0xfffffffb
7270 #define ALT_I2C_IC_STATUS_TFE_RESET 0x1
7272 #define ALT_I2C_IC_STATUS_TFE_GET(value) (((value) & 0x00000004) >> 2)
7274 #define ALT_I2C_IC_STATUS_TFE_SET(value) (((value) << 2) & 0x00000004)
7306 #define ALT_I2C_IC_STATUS_RFNE_E_EMPTY 0x0
7312 #define ALT_I2C_IC_STATUS_RFNE_E_NOT_EMPTY 0x1
7315 #define ALT_I2C_IC_STATUS_RFNE_LSB 3
7317 #define ALT_I2C_IC_STATUS_RFNE_MSB 3
7319 #define ALT_I2C_IC_STATUS_RFNE_WIDTH 1
7321 #define ALT_I2C_IC_STATUS_RFNE_SET_MSK 0x00000008
7323 #define ALT_I2C_IC_STATUS_RFNE_CLR_MSK 0xfffffff7
7325 #define ALT_I2C_IC_STATUS_RFNE_RESET 0x0
7327 #define ALT_I2C_IC_STATUS_RFNE_GET(value) (((value) & 0x00000008) >> 3)
7329 #define ALT_I2C_IC_STATUS_RFNE_SET(value) (((value) << 3) & 0x00000008)
7363 #define ALT_I2C_IC_STATUS_RFF_E_NOT_FULL 0x0
7369 #define ALT_I2C_IC_STATUS_RFF_E_FULL 0x1
7372 #define ALT_I2C_IC_STATUS_RFF_LSB 4
7374 #define ALT_I2C_IC_STATUS_RFF_MSB 4
7376 #define ALT_I2C_IC_STATUS_RFF_WIDTH 1
7378 #define ALT_I2C_IC_STATUS_RFF_SET_MSK 0x00000010
7380 #define ALT_I2C_IC_STATUS_RFF_CLR_MSK 0xffffffef
7382 #define ALT_I2C_IC_STATUS_RFF_RESET 0x0
7384 #define ALT_I2C_IC_STATUS_RFF_GET(value) (((value) & 0x00000010) >> 4)
7386 #define ALT_I2C_IC_STATUS_RFF_SET(value) (((value) << 4) & 0x00000010)
7428 #define ALT_I2C_IC_STATUS_MST_ACTIVITY_E_IDLE 0x0
7434 #define ALT_I2C_IC_STATUS_MST_ACTIVITY_E_ACTIVE 0x1
7437 #define ALT_I2C_IC_STATUS_MST_ACTIVITY_LSB 5
7439 #define ALT_I2C_IC_STATUS_MST_ACTIVITY_MSB 5
7441 #define ALT_I2C_IC_STATUS_MST_ACTIVITY_WIDTH 1
7443 #define ALT_I2C_IC_STATUS_MST_ACTIVITY_SET_MSK 0x00000020
7445 #define ALT_I2C_IC_STATUS_MST_ACTIVITY_CLR_MSK 0xffffffdf
7447 #define ALT_I2C_IC_STATUS_MST_ACTIVITY_RESET 0x0
7449 #define ALT_I2C_IC_STATUS_MST_ACTIVITY_GET(value) (((value) & 0x00000020) >> 5)
7451 #define ALT_I2C_IC_STATUS_MST_ACTIVITY_SET(value) (((value) << 5) & 0x00000020)
7487 #define ALT_I2C_IC_STATUS_SLV_ACTIVITY_E_IDLE 0x0
7493 #define ALT_I2C_IC_STATUS_SLV_ACTIVITY_E_ACTIVE 0x1
7496 #define ALT_I2C_IC_STATUS_SLV_ACTIVITY_LSB 6
7498 #define ALT_I2C_IC_STATUS_SLV_ACTIVITY_MSB 6
7500 #define ALT_I2C_IC_STATUS_SLV_ACTIVITY_WIDTH 1
7502 #define ALT_I2C_IC_STATUS_SLV_ACTIVITY_SET_MSK 0x00000040
7504 #define ALT_I2C_IC_STATUS_SLV_ACTIVITY_CLR_MSK 0xffffffbf
7506 #define ALT_I2C_IC_STATUS_SLV_ACTIVITY_RESET 0x0
7508 #define ALT_I2C_IC_STATUS_SLV_ACTIVITY_GET(value) (((value) & 0x00000040) >> 6)
7510 #define ALT_I2C_IC_STATUS_SLV_ACTIVITY_SET(value) (((value) << 6) & 0x00000040)
7521 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY_LSB 7
7523 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY_MSB 7
7525 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY_WIDTH 1
7527 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY_SET_MSK 0x00000080
7529 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY_CLR_MSK 0xffffff7f
7531 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY_RESET 0x0
7533 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY_GET(value) (((value) & 0x00000080) >> 7)
7535 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY_SET(value) (((value) << 7) & 0x00000080)
7546 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL_LSB 8
7548 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL_MSB 8
7550 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL_WIDTH 1
7552 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL_SET_MSK 0x00000100
7554 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL_CLR_MSK 0xfffffeff
7556 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL_RESET 0x0
7558 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL_GET(value) (((value) & 0x00000100) >> 8)
7560 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL_SET(value) (((value) << 8) & 0x00000100)
7571 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY_LSB 9
7573 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY_MSB 9
7575 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY_WIDTH 1
7577 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY_SET_MSK 0x00000200
7579 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY_CLR_MSK 0xfffffdff
7581 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY_RESET 0x0
7583 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY_GET(value) (((value) & 0x00000200) >> 9)
7585 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY_SET(value) (((value) << 9) & 0x00000200)
7596 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL_LSB 10
7598 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL_MSB 10
7600 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL_WIDTH 1
7602 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL_SET_MSK 0x00000400
7604 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL_CLR_MSK 0xfffffbff
7606 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL_RESET 0x0
7608 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL_GET(value) (((value) & 0x00000400) >> 10)
7610 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL_SET(value) (((value) << 10) & 0x00000400)
7621 #define ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED_LSB 11
7623 #define ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED_MSB 11
7625 #define ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED_WIDTH 1
7627 #define ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED_SET_MSK 0x00000800
7629 #define ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED_CLR_MSK 0xfffff7ff
7631 #define ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED_RESET 0x0
7633 #define ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED_GET(value) (((value) & 0x00000800) >> 11)
7635 #define ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED_SET(value) (((value) << 11) & 0x00000800)
7646 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1_LSB 12
7648 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1_MSB 15
7650 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1_WIDTH 4
7652 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1_SET_MSK 0x0000f000
7654 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1_CLR_MSK 0xffff0fff
7656 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1_RESET 0x0
7658 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1_GET(value) (((value) & 0x0000f000) >> 12)
7660 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1_SET(value) (((value) << 12) & 0x0000f000)
7671 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT_LSB 16
7673 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT_MSB 16
7675 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT_WIDTH 1
7677 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT_SET_MSK 0x00010000
7679 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT_CLR_MSK 0xfffeffff
7681 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT_RESET 0x0
7683 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT_GET(value) (((value) & 0x00010000) >> 16)
7685 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT_SET(value) (((value) << 16) & 0x00010000)
7696 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID_LSB 17
7698 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID_MSB 17
7700 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID_WIDTH 1
7702 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID_SET_MSK 0x00020000
7704 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID_CLR_MSK 0xfffdffff
7706 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID_RESET 0x0
7708 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID_GET(value) (((value) & 0x00020000) >> 17)
7710 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID_SET(value) (((value) << 17) & 0x00020000)
7721 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED_LSB 18
7723 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED_MSB 18
7725 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED_WIDTH 1
7727 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED_SET_MSK 0x00040000
7729 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED_CLR_MSK 0xfffbffff
7731 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED_RESET 0x0
7733 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED_GET(value) (((value) & 0x00040000) >> 18)
7735 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED_SET(value) (((value) << 18) & 0x00040000)
7746 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS_LSB 19
7748 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS_MSB 19
7750 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS_WIDTH 1
7752 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS_SET_MSK 0x00080000
7754 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS_CLR_MSK 0xfff7ffff
7756 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS_RESET 0x0
7758 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS_GET(value) (((value) & 0x00080000) >> 19)
7760 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS_SET(value) (((value) << 19) & 0x00080000)
7771 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS_LSB 20
7773 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS_MSB 20
7775 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS_WIDTH 1
7777 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS_SET_MSK 0x00100000
7779 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS_CLR_MSK 0xffefffff
7781 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS_RESET 0x0
7783 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS_GET(value) (((value) & 0x00100000) >> 20)
7785 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS_SET(value) (((value) << 20) & 0x00100000)
7796 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2_LSB 21
7798 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2_MSB 31
7800 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2_WIDTH 11
7802 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2_SET_MSK 0xffe00000
7804 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2_CLR_MSK 0x001fffff
7806 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2_RESET 0x0
7808 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2_GET(value) (((value) & 0xffe00000) >> 21)
7810 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2_SET(value) (((value) << 21) & 0xffe00000)
7812 #ifndef __ASSEMBLY__
7824 struct ALT_I2C_IC_STATUS_s
7826 const volatile uint32_t IC_STATUS_ACTIVITY : 1;
7827 const volatile uint32_t TFNF : 1;
7828 const volatile uint32_t TFE : 1;
7829 const volatile uint32_t RFNE : 1;
7830 const volatile uint32_t RFF : 1;
7831 const volatile uint32_t MST_ACTIVITY : 1;
7832 const volatile uint32_t SLV_ACTIVITY : 1;
7833 const volatile uint32_t RSVD_MST_HOLD_TX_FIFO_EMPTY : 1;
7834 const volatile uint32_t RSVD_MST_HOLD_RX_FIFO_FULL : 1;
7835 const volatile uint32_t RSVD_SLV_HOLD_TX_FIFO_EMPTY : 1;
7836 const volatile uint32_t RSVD_SLV_HOLD_RX_FIFO_FULL : 1;
7837 const volatile uint32_t RSVD_SDA_STUCK_NOT_RECOVERED : 1;
7838 const volatile uint32_t RSVD_IC_STATUS_1 : 4;
7839 const volatile uint32_t RSVD_SMBUS_QUICK_CMD_BIT : 1;
7840 const volatile uint32_t RSVD_SMBUS_SLAVE_ADDR_VALID : 1;
7841 const volatile uint32_t RSVD_SMBUS_SLAVE_ADDR_RESOLVED : 1;
7842 const volatile uint32_t RSVD_SMBUS_SUSPEND_STATUS : 1;
7843 const volatile uint32_t RSVD_SMBUS_ALERT_STATUS : 1;
7844 const volatile uint32_t RSVD_IC_STATUS_2 : 11;
7848 typedef struct ALT_I2C_IC_STATUS_s ALT_I2C_IC_STATUS_t;
7852 #define ALT_I2C_IC_STATUS_RESET 0x00000006
7854 #define ALT_I2C_IC_STATUS_OFST 0x70
7856 #define ALT_I2C_IC_STATUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_STATUS_OFST))
7912 #define ALT_I2C_IC_TXFLR_TXFLR_LSB 0
7914 #define ALT_I2C_IC_TXFLR_TXFLR_MSB 6
7916 #define ALT_I2C_IC_TXFLR_TXFLR_WIDTH 7
7918 #define ALT_I2C_IC_TXFLR_TXFLR_SET_MSK 0x0000007f
7920 #define ALT_I2C_IC_TXFLR_TXFLR_CLR_MSK 0xffffff80
7922 #define ALT_I2C_IC_TXFLR_TXFLR_RESET 0x0
7924 #define ALT_I2C_IC_TXFLR_TXFLR_GET(value) (((value) & 0x0000007f) >> 0)
7926 #define ALT_I2C_IC_TXFLR_TXFLR_SET(value) (((value) << 0) & 0x0000007f)
7937 #define ALT_I2C_IC_TXFLR_RSVD_TXFLR_LSB 7
7939 #define ALT_I2C_IC_TXFLR_RSVD_TXFLR_MSB 31
7941 #define ALT_I2C_IC_TXFLR_RSVD_TXFLR_WIDTH 25
7943 #define ALT_I2C_IC_TXFLR_RSVD_TXFLR_SET_MSK 0xffffff80
7945 #define ALT_I2C_IC_TXFLR_RSVD_TXFLR_CLR_MSK 0x0000007f
7947 #define ALT_I2C_IC_TXFLR_RSVD_TXFLR_RESET 0x0
7949 #define ALT_I2C_IC_TXFLR_RSVD_TXFLR_GET(value) (((value) & 0xffffff80) >> 7)
7951 #define ALT_I2C_IC_TXFLR_RSVD_TXFLR_SET(value) (((value) << 7) & 0xffffff80)
7953 #ifndef __ASSEMBLY__
7965 struct ALT_I2C_IC_TXFLR_s
7967 const volatile uint32_t TXFLR : 7;
7968 const volatile uint32_t RSVD_TXFLR : 25;
7972 typedef struct ALT_I2C_IC_TXFLR_s ALT_I2C_IC_TXFLR_t;
7976 #define ALT_I2C_IC_TXFLR_RESET 0x00000000
7978 #define ALT_I2C_IC_TXFLR_OFST 0x74
7980 #define ALT_I2C_IC_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_TXFLR_OFST))
8034 #define ALT_I2C_IC_RXFLR_RXFLR_LSB 0
8036 #define ALT_I2C_IC_RXFLR_RXFLR_MSB 6
8038 #define ALT_I2C_IC_RXFLR_RXFLR_WIDTH 7
8040 #define ALT_I2C_IC_RXFLR_RXFLR_SET_MSK 0x0000007f
8042 #define ALT_I2C_IC_RXFLR_RXFLR_CLR_MSK 0xffffff80
8044 #define ALT_I2C_IC_RXFLR_RXFLR_RESET 0x0
8046 #define ALT_I2C_IC_RXFLR_RXFLR_GET(value) (((value) & 0x0000007f) >> 0)
8048 #define ALT_I2C_IC_RXFLR_RXFLR_SET(value) (((value) << 0) & 0x0000007f)
8059 #define ALT_I2C_IC_RXFLR_RSVD_RXFLR_LSB 7
8061 #define ALT_I2C_IC_RXFLR_RSVD_RXFLR_MSB 31
8063 #define ALT_I2C_IC_RXFLR_RSVD_RXFLR_WIDTH 25
8065 #define ALT_I2C_IC_RXFLR_RSVD_RXFLR_SET_MSK 0xffffff80
8067 #define ALT_I2C_IC_RXFLR_RSVD_RXFLR_CLR_MSK 0x0000007f
8069 #define ALT_I2C_IC_RXFLR_RSVD_RXFLR_RESET 0x0
8071 #define ALT_I2C_IC_RXFLR_RSVD_RXFLR_GET(value) (((value) & 0xffffff80) >> 7)
8073 #define ALT_I2C_IC_RXFLR_RSVD_RXFLR_SET(value) (((value) << 7) & 0xffffff80)
8075 #ifndef __ASSEMBLY__
8087 struct ALT_I2C_IC_RXFLR_s
8089 const volatile uint32_t RXFLR : 7;
8090 const volatile uint32_t RSVD_RXFLR : 25;
8094 typedef struct ALT_I2C_IC_RXFLR_s ALT_I2C_IC_RXFLR_t;
8098 #define ALT_I2C_IC_RXFLR_RESET 0x00000000
8100 #define ALT_I2C_IC_RXFLR_OFST 0x78
8102 #define ALT_I2C_IC_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_RXFLR_OFST))
8153 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_LSB 0
8155 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_MSB 15
8157 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_WIDTH 16
8159 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_SET_MSK 0x0000ffff
8161 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_CLR_MSK 0xffff0000
8163 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_RESET 0x1
8165 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_GET(value) (((value) & 0x0000ffff) >> 0)
8167 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_SET(value) (((value) << 0) & 0x0000ffff)
8182 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_LSB 16
8184 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_MSB 23
8186 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_WIDTH 8
8188 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_SET_MSK 0x00ff0000
8190 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_CLR_MSK 0xff00ffff
8192 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_RESET 0x0
8194 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_GET(value) (((value) & 0x00ff0000) >> 16)
8196 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_SET(value) (((value) << 16) & 0x00ff0000)
8207 #define ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD_LSB 24
8209 #define ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD_MSB 31
8211 #define ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD_WIDTH 8
8213 #define ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD_SET_MSK 0xff000000
8215 #define ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD_CLR_MSK 0x00ffffff
8217 #define ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD_RESET 0x0
8219 #define ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD_GET(value) (((value) & 0xff000000) >> 24)
8221 #define ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD_SET(value) (((value) << 24) & 0xff000000)
8223 #ifndef __ASSEMBLY__
8235 struct ALT_I2C_IC_SDA_HOLD_s
8237 volatile uint32_t IC_SDA_TX_HOLD : 16;
8238 volatile uint32_t IC_SDA_RX_HOLD : 8;
8239 const volatile uint32_t RSVD_IC_SDA_HOLD : 8;
8243 typedef struct ALT_I2C_IC_SDA_HOLD_s ALT_I2C_IC_SDA_HOLD_t;
8247 #define ALT_I2C_IC_SDA_HOLD_RESET 0x00000001
8249 #define ALT_I2C_IC_SDA_HOLD_OFST 0x7c
8251 #define ALT_I2C_IC_SDA_HOLD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_SDA_HOLD_OFST))
8348 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_E_INACTIVE 0x0
8354 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_E_ACTIVE 0x1
8357 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_LSB 0
8359 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MSB 0
8361 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_WIDTH 1
8363 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_SET_MSK 0x00000001
8365 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_CLR_MSK 0xfffffffe
8367 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_RESET 0x0
8369 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_GET(value) (((value) & 0x00000001) >> 0)
8371 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_SET(value) (((value) << 0) & 0x00000001)
8405 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_E_INACTIVE 0x0
8411 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_E_ACTIVE 0x1
8414 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_LSB 1
8416 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MSB 1
8418 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_WIDTH 1
8420 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_SET_MSK 0x00000002
8422 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_CLR_MSK 0xfffffffd
8424 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_RESET 0x0
8426 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_GET(value) (((value) & 0x00000002) >> 1)
8428 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_SET(value) (((value) << 1) & 0x00000002)
8462 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_E_INACTIVE 0x0
8468 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_E_ACTIVE 0x1
8471 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_LSB 2
8473 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MSB 2
8475 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_WIDTH 1
8477 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_SET_MSK 0x00000004
8479 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_CLR_MSK 0xfffffffb
8481 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_RESET 0x0
8483 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_GET(value) (((value) & 0x00000004) >> 2)
8485 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_SET(value) (((value) << 2) & 0x00000004)
8524 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_E_ABRT_TXDATA_NOACK_VOID 0x0
8530 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_E_ABRT_TXDATA_NOACK_GENERATED 0x1
8533 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_LSB 3
8535 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MSB 3
8537 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_WIDTH 1
8539 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_SET_MSK 0x00000008
8541 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_CLR_MSK 0xfffffff7
8543 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET 0x0
8545 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_GET(value) (((value) & 0x00000008) >> 3)
8547 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_SET(value) (((value) << 3) & 0x00000008)
8580 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_E_ABRT_GCALL_NOACK_VOID 0x0
8586 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_E_ABRT_GCALL_NOACK_GENERATED 0x1
8589 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_LSB 4
8591 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MSB 4
8593 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_WIDTH 1
8595 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_SET_MSK 0x00000010
8597 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_CLR_MSK 0xffffffef
8599 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_RESET 0x0
8601 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_GET(value) (((value) & 0x00000010) >> 4)
8603 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_SET(value) (((value) << 4) & 0x00000010)
8640 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_E_ABRT_GCALL_READ_VOID 0x0
8646 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_E_ABRT_GCALL_READ_GENERATED 0x1
8649 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_LSB 5
8651 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MSB 5
8653 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_WIDTH 1
8655 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_SET_MSK 0x00000020
8657 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_CLR_MSK 0xffffffdf
8659 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_RESET 0x0
8661 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_GET(value) (((value) & 0x00000020) >> 5)
8663 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_SET(value) (((value) << 5) & 0x00000020)
8696 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_E_ABRT_HS_ACK_VOID 0x0
8702 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_E_ABRT_HS_ACK_GENERATED 0x1
8705 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_LSB 6
8707 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MSB 6
8709 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_WIDTH 1
8711 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_SET_MSK 0x00000040
8713 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_CLR_MSK 0xffffffbf
8715 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_RESET 0x0
8717 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_GET(value) (((value) & 0x00000040) >> 6)
8719 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_SET(value) (((value) << 6) & 0x00000040)
8750 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_E_ABRT_SBYTE_ACKDET_VOID 0x0
8756 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_E_ABRT_SBYTE_ACKDET_GENERATED 0x1
8759 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_LSB 7
8761 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MSB 7
8763 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_WIDTH 1
8765 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_SET_MSK 0x00000080
8767 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_CLR_MSK 0xffffff7f
8769 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_RESET 0x0
8771 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_GET(value) (((value) & 0x00000080) >> 7)
8773 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_SET(value) (((value) << 7) & 0x00000080)
8814 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_E_ABRT_HS_NORSTRT_VOID 0x0
8820 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_E_ABRT_HS_NORSTRT_GENERATED 0x1
8823 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_LSB 8
8825 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MSB 8
8827 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_WIDTH 1
8829 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_SET_MSK 0x00000100
8831 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_CLR_MSK 0xfffffeff
8833 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET 0x0
8835 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_GET(value) (((value) & 0x00000100) >> 8)
8837 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_SET(value) (((value) << 8) & 0x00000100)
8893 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_E_ABRT_SBYTE_NORSTRT_VOID 0x0
8899 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_E_ABRT_SBYTE_NORSTRT_GENERATED 0x1
8902 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_LSB 9
8904 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MSB 9
8906 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_WIDTH 1
8908 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_SET_MSK 0x00000200
8910 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_CLR_MSK 0xfffffdff
8912 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET 0x0
8914 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_GET(value) (((value) & 0x00000200) >> 9)
8916 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_SET(value) (((value) << 9) & 0x00000200)
8952 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_E_ABRT_10B_RD_VOID 0x0
8958 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_E_ABRT_10B_RD_GENERATED 0x1
8961 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_LSB 10
8963 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB 10
8965 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_WIDTH 1
8967 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_SET_MSK 0x00000400
8969 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_CLR_MSK 0xfffffbff
8971 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET 0x0
8973 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_GET(value) (((value) & 0x00000400) >> 10)
8975 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_SET(value) (((value) << 10) & 0x00000400)
9007 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_E_ABRT_MASTER_DIS_VOID 0x0
9013 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_E_ABRT_MASTER_DIS_GENERATED 0x1
9016 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_LSB 11
9018 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MSB 11
9020 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_WIDTH 1
9022 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_SET_MSK 0x00000800
9024 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_CLR_MSK 0xfffff7ff
9026 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET 0x0
9028 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_GET(value) (((value) & 0x00000800) >> 11)
9030 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_SET(value) (((value) << 11) & 0x00000800)
9067 #define ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST_E_ABRT_LOST_VOID 0x0
9073 #define ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST_E_ABRT_LOST_GENERATED 0x1
9076 #define ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST_LSB 12
9078 #define ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MSB 12
9080 #define ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST_WIDTH 1
9082 #define ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST_SET_MSK 0x00001000
9084 #define ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST_CLR_MSK 0xffffefff
9086 #define ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET 0x0
9088 #define ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST_GET(value) (((value) & 0x00001000) >> 12)
9090 #define ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST_SET(value) (((value) << 12) & 0x00001000)
9127 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_E_ABRT_SLVFLUSH_TXFIFO_VOID 0x0
9133 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_E_ABRT_SLVFLUSH_TXFIFO_GENERATED 0x1
9136 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_LSB 13
9138 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB 13
9140 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_WIDTH 1
9142 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_SET_MSK 0x00002000
9144 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_CLR_MSK 0xffffdfff
9146 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET 0x0
9148 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_GET(value) (((value) & 0x00002000) >> 13)
9150 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_SET(value) (((value) << 13) & 0x00002000)
9203 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_E_ABRT_SLV_ARBLOST_VOID 0x0
9209 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_E_ABRT_SLV_ARBLOST_GENERATED 0x1
9212 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_LSB 14
9214 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MSB 14
9216 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_WIDTH 1
9218 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_SET_MSK 0x00004000
9220 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_CLR_MSK 0xffffbfff
9222 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_RESET 0x0
9224 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_GET(value) (((value) & 0x00004000) >> 14)
9226 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_SET(value) (((value) << 14) & 0x00004000)
9264 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_E_ABRT_SLVRD_INTX_VOID 0x0
9270 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_E_ABRT_SLVRD_INTX_GENERATED 0x1
9273 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_LSB 15
9275 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MSB 15
9277 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_WIDTH 1
9279 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_SET_MSK 0x00008000
9281 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_CLR_MSK 0xffff7fff
9283 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET 0x0
9285 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_GET(value) (((value) & 0x00008000) >> 15)
9287 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_SET(value) (((value) << 15) & 0x00008000)
9316 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_E_ABRT_USER_ABRT_VOID 0x0
9322 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_E_ABRT_USER_ABRT_GENERATED 0x1
9325 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_LSB 16
9327 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_MSB 16
9329 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_WIDTH 1
9331 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_SET_MSK 0x00010000
9333 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_CLR_MSK 0xfffeffff
9335 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_RESET 0x0
9337 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_GET(value) (((value) & 0x00010000) >> 16)
9339 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_SET(value) (((value) << 16) & 0x00010000)
9348 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW_LSB 17
9350 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW_MSB 17
9352 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW_WIDTH 1
9354 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW_SET_MSK 0x00020000
9356 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW_CLR_MSK 0xfffdffff
9358 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW_RESET 0x0
9360 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW_GET(value) (((value) & 0x00020000) >> 17)
9362 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW_SET(value) (((value) << 17) & 0x00020000)
9373 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE_LSB 18
9375 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE_MSB 20
9377 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE_WIDTH 3
9379 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE_SET_MSK 0x001c0000
9381 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE_CLR_MSK 0xffe3ffff
9383 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE_RESET 0x0
9385 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE_GET(value) (((value) & 0x001c0000) >> 18)
9387 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE_SET(value) (((value) << 18) & 0x001c0000)
9398 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE_LSB 21
9400 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE_MSB 22
9402 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE_WIDTH 2
9404 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE_SET_MSK 0x00600000
9406 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE_CLR_MSK 0xff9fffff
9408 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE_RESET 0x0
9410 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE_GET(value) (((value) & 0x00600000) >> 21)
9412 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE_SET(value) (((value) << 21) & 0x00600000)
9431 #define ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_LSB 23
9433 #define ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_MSB 31
9435 #define ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_WIDTH 9
9437 #define ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_SET_MSK 0xff800000
9439 #define ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_CLR_MSK 0x007fffff
9441 #define ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_RESET 0x0
9443 #define ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_GET(value) (((value) & 0xff800000) >> 23)
9445 #define ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_SET(value) (((value) << 23) & 0xff800000)
9447 #ifndef __ASSEMBLY__
9459 struct ALT_I2C_IC_TX_ABRT_SOURCE_s
9461 const volatile uint32_t ABRT_7B_ADDR_NOACK : 1;
9462 const volatile uint32_t ABRT_10ADDR1_NOACK : 1;
9463 const volatile uint32_t ABRT_10ADDR2_NOACK : 1;
9464 const volatile uint32_t ABRT_TXDATA_NOACK : 1;
9465 const volatile uint32_t ABRT_GCALL_NOACK : 1;
9466 const volatile uint32_t ABRT_GCALL_READ : 1;
9467 const volatile uint32_t ABRT_HS_ACKDET : 1;
9468 const volatile uint32_t ABRT_SBYTE_ACKDET : 1;
9469 const volatile uint32_t ABRT_HS_NORSTRT : 1;
9470 const volatile uint32_t ABRT_SBYTE_NORSTRT : 1;
9471 const volatile uint32_t ABRT_10B_RD_NORSTRT : 1;
9472 const volatile uint32_t ABRT_MASTER_DIS : 1;
9473 const volatile uint32_t ARB_LOST : 1;
9474 const volatile uint32_t ABRT_SLVFLUSH_TXFIFO : 1;
9475 const volatile uint32_t ABRT_SLV_ARBLOST : 1;
9476 const volatile uint32_t ABRT_SLVRD_INTX : 1;
9477 const volatile uint32_t ABRT_USER_ABRT : 1;
9478 const volatile uint32_t RSVD_ABRT_SDA_STUCK_AT_LOW : 1;
9479 const volatile uint32_t RSVD_ABRT_DEVICE_WRITE : 3;
9480 const volatile uint32_t RSVD_IC_TX_ABRT_SOURCE : 2;
9481 const volatile uint32_t TX_FLUSH_CNT : 9;
9485 typedef struct ALT_I2C_IC_TX_ABRT_SOURCE_s ALT_I2C_IC_TX_ABRT_SOURCE_t;
9489 #define ALT_I2C_IC_TX_ABRT_SOURCE_RESET 0x00000000
9491 #define ALT_I2C_IC_TX_ABRT_SOURCE_OFST 0x80
9493 #define ALT_I2C_IC_TX_ABRT_SOURCE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_TX_ABRT_SOURCE_OFST))
9571 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK_E_DISABLED 0x0
9577 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK_E_ENABLED 0x1
9580 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK_LSB 0
9582 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK_MSB 0
9584 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK_WIDTH 1
9586 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK_SET_MSK 0x00000001
9588 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK_CLR_MSK 0xfffffffe
9590 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK_RESET 0x0
9592 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK_GET(value) (((value) & 0x00000001) >> 0)
9594 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK_SET(value) (((value) << 0) & 0x00000001)
9605 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY_LSB 1
9607 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY_MSB 31
9609 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY_WIDTH 31
9611 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY_SET_MSK 0xfffffffe
9613 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY_CLR_MSK 0x00000001
9615 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY_RESET 0x0
9617 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY_GET(value) (((value) & 0xfffffffe) >> 1)
9619 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY_SET(value) (((value) << 1) & 0xfffffffe)
9621 #ifndef __ASSEMBLY__
9633 struct ALT_I2C_IC_SLV_DATA_NACK_ONLY_s
9635 volatile uint32_t NACK : 1;
9636 const volatile uint32_t RSVD_IC_SLV_DATA_NACK_ONLY : 31;
9640 typedef struct ALT_I2C_IC_SLV_DATA_NACK_ONLY_s ALT_I2C_IC_SLV_DATA_NACK_ONLY_t;
9644 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_RESET 0x00000000
9646 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_OFST 0x84
9648 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_SLV_DATA_NACK_ONLY_OFST))
9716 #define ALT_I2C_IC_DMA_CR_RDMAE_E_DISABLED 0x0
9722 #define ALT_I2C_IC_DMA_CR_RDMAE_E_ENABLED 0x1
9725 #define ALT_I2C_IC_DMA_CR_RDMAE_LSB 0
9727 #define ALT_I2C_IC_DMA_CR_RDMAE_MSB 0
9729 #define ALT_I2C_IC_DMA_CR_RDMAE_WIDTH 1
9731 #define ALT_I2C_IC_DMA_CR_RDMAE_SET_MSK 0x00000001
9733 #define ALT_I2C_IC_DMA_CR_RDMAE_CLR_MSK 0xfffffffe
9735 #define ALT_I2C_IC_DMA_CR_RDMAE_RESET 0x0
9737 #define ALT_I2C_IC_DMA_CR_RDMAE_GET(value) (((value) & 0x00000001) >> 0)
9739 #define ALT_I2C_IC_DMA_CR_RDMAE_SET(value) (((value) << 0) & 0x00000001)
9771 #define ALT_I2C_IC_DMA_CR_TDMAE_E_DISABLED 0x0
9777 #define ALT_I2C_IC_DMA_CR_TDMAE_E_ENABLED 0x1
9780 #define ALT_I2C_IC_DMA_CR_TDMAE_LSB 1
9782 #define ALT_I2C_IC_DMA_CR_TDMAE_MSB 1
9784 #define ALT_I2C_IC_DMA_CR_TDMAE_WIDTH 1
9786 #define ALT_I2C_IC_DMA_CR_TDMAE_SET_MSK 0x00000002
9788 #define ALT_I2C_IC_DMA_CR_TDMAE_CLR_MSK 0xfffffffd
9790 #define ALT_I2C_IC_DMA_CR_TDMAE_RESET 0x0
9792 #define ALT_I2C_IC_DMA_CR_TDMAE_GET(value) (((value) & 0x00000002) >> 1)
9794 #define ALT_I2C_IC_DMA_CR_TDMAE_SET(value) (((value) << 1) & 0x00000002)
9805 #define ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31_LSB 2
9807 #define ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31_MSB 31
9809 #define ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31_WIDTH 30
9811 #define ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31_SET_MSK 0xfffffffc
9813 #define ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31_CLR_MSK 0x00000003
9815 #define ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31_RESET 0x0
9817 #define ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31_GET(value) (((value) & 0xfffffffc) >> 2)
9819 #define ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31_SET(value) (((value) << 2) & 0xfffffffc)
9821 #ifndef __ASSEMBLY__
9833 struct ALT_I2C_IC_DMA_CR_s
9835 volatile uint32_t RDMAE : 1;
9836 volatile uint32_t TDMAE : 1;
9837 const volatile uint32_t RSVD_IC_DMA_CR_2_31 : 30;
9841 typedef struct ALT_I2C_IC_DMA_CR_s ALT_I2C_IC_DMA_CR_t;
9845 #define ALT_I2C_IC_DMA_CR_RESET 0x00000000
9847 #define ALT_I2C_IC_DMA_CR_OFST 0x88
9849 #define ALT_I2C_IC_DMA_CR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_DMA_CR_OFST))
9905 #define ALT_I2C_IC_DMA_TDLR_DMATDL_LSB 0
9907 #define ALT_I2C_IC_DMA_TDLR_DMATDL_MSB 5
9909 #define ALT_I2C_IC_DMA_TDLR_DMATDL_WIDTH 6
9911 #define ALT_I2C_IC_DMA_TDLR_DMATDL_SET_MSK 0x0000003f
9913 #define ALT_I2C_IC_DMA_TDLR_DMATDL_CLR_MSK 0xffffffc0
9915 #define ALT_I2C_IC_DMA_TDLR_DMATDL_RESET 0x0
9917 #define ALT_I2C_IC_DMA_TDLR_DMATDL_GET(value) (((value) & 0x0000003f) >> 0)
9919 #define ALT_I2C_IC_DMA_TDLR_DMATDL_SET(value) (((value) << 0) & 0x0000003f)
9930 #define ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR_LSB 6
9932 #define ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR_MSB 31
9934 #define ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR_WIDTH 26
9936 #define ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR_SET_MSK 0xffffffc0
9938 #define ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR_CLR_MSK 0x0000003f
9940 #define ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR_RESET 0x0
9942 #define ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR_GET(value) (((value) & 0xffffffc0) >> 6)
9944 #define ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR_SET(value) (((value) << 6) & 0xffffffc0)
9946 #ifndef __ASSEMBLY__
9958 struct ALT_I2C_IC_DMA_TDLR_s
9960 volatile uint32_t DMATDL : 6;
9961 const volatile uint32_t RSVD_DMA_TDLR : 26;
9965 typedef struct ALT_I2C_IC_DMA_TDLR_s ALT_I2C_IC_DMA_TDLR_t;
9969 #define ALT_I2C_IC_DMA_TDLR_RESET 0x00000000
9971 #define ALT_I2C_IC_DMA_TDLR_OFST 0x8c
9973 #define ALT_I2C_IC_DMA_TDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_DMA_TDLR_OFST))
10031 #define ALT_I2C_IC_DMA_RDLR_DMARDL_LSB 0
10033 #define ALT_I2C_IC_DMA_RDLR_DMARDL_MSB 5
10035 #define ALT_I2C_IC_DMA_RDLR_DMARDL_WIDTH 6
10037 #define ALT_I2C_IC_DMA_RDLR_DMARDL_SET_MSK 0x0000003f
10039 #define ALT_I2C_IC_DMA_RDLR_DMARDL_CLR_MSK 0xffffffc0
10041 #define ALT_I2C_IC_DMA_RDLR_DMARDL_RESET 0x0
10043 #define ALT_I2C_IC_DMA_RDLR_DMARDL_GET(value) (((value) & 0x0000003f) >> 0)
10045 #define ALT_I2C_IC_DMA_RDLR_DMARDL_SET(value) (((value) << 0) & 0x0000003f)
10056 #define ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR_LSB 6
10058 #define ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR_MSB 31
10060 #define ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR_WIDTH 26
10062 #define ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR_SET_MSK 0xffffffc0
10064 #define ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR_CLR_MSK 0x0000003f
10066 #define ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR_RESET 0x0
10068 #define ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR_GET(value) (((value) & 0xffffffc0) >> 6)
10070 #define ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR_SET(value) (((value) << 6) & 0xffffffc0)
10072 #ifndef __ASSEMBLY__
10084 struct ALT_I2C_IC_DMA_RDLR_s
10086 volatile uint32_t DMARDL : 6;
10087 const volatile uint32_t RSVD_DMA_RDLR : 26;
10091 typedef struct ALT_I2C_IC_DMA_RDLR_s ALT_I2C_IC_DMA_RDLR_t;
10095 #define ALT_I2C_IC_DMA_RDLR_RESET 0x00000000
10097 #define ALT_I2C_IC_DMA_RDLR_OFST 0x90
10099 #define ALT_I2C_IC_DMA_RDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_DMA_RDLR_OFST))
10153 #define ALT_I2C_IC_SDA_SETUP_SDA_SETUP_LSB 0
10155 #define ALT_I2C_IC_SDA_SETUP_SDA_SETUP_MSB 7
10157 #define ALT_I2C_IC_SDA_SETUP_SDA_SETUP_WIDTH 8
10159 #define ALT_I2C_IC_SDA_SETUP_SDA_SETUP_SET_MSK 0x000000ff
10161 #define ALT_I2C_IC_SDA_SETUP_SDA_SETUP_CLR_MSK 0xffffff00
10163 #define ALT_I2C_IC_SDA_SETUP_SDA_SETUP_RESET 0x64
10165 #define ALT_I2C_IC_SDA_SETUP_SDA_SETUP_GET(value) (((value) & 0x000000ff) >> 0)
10167 #define ALT_I2C_IC_SDA_SETUP_SDA_SETUP_SET(value) (((value) << 0) & 0x000000ff)
10178 #define ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP_LSB 8
10180 #define ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP_MSB 31
10182 #define ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP_WIDTH 24
10184 #define ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP_SET_MSK 0xffffff00
10186 #define ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP_CLR_MSK 0x000000ff
10188 #define ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP_RESET 0x0
10190 #define ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP_GET(value) (((value) & 0xffffff00) >> 8)
10192 #define ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP_SET(value) (((value) << 8) & 0xffffff00)
10194 #ifndef __ASSEMBLY__
10206 struct ALT_I2C_IC_SDA_SETUP_s
10208 volatile uint32_t SDA_SETUP : 8;
10209 const volatile uint32_t RSVD_IC_SDA_SETUP : 24;
10213 typedef struct ALT_I2C_IC_SDA_SETUP_s ALT_I2C_IC_SDA_SETUP_t;
10217 #define ALT_I2C_IC_SDA_SETUP_RESET 0x00000064
10219 #define ALT_I2C_IC_SDA_SETUP_OFST 0x94
10221 #define ALT_I2C_IC_SDA_SETUP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_SDA_SETUP_OFST))
10284 #define ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_E_DISABLED 0x0
10290 #define ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ENABLED 0x1
10293 #define ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB 0
10295 #define ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB 0
10297 #define ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_WIDTH 1
10299 #define ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_SET_MSK 0x00000001
10301 #define ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_CLR_MSK 0xfffffffe
10303 #define ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET 0x1
10305 #define ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0)
10307 #define ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_SET(value) (((value) << 0) & 0x00000001)
10318 #define ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31_LSB 1
10320 #define ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31_MSB 31
10322 #define ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31_WIDTH 31
10324 #define ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31_SET_MSK 0xfffffffe
10326 #define ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31_CLR_MSK 0x00000001
10328 #define ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31_RESET 0x0
10330 #define ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31_GET(value) (((value) & 0xfffffffe) >> 1)
10332 #define ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31_SET(value) (((value) << 1) & 0xfffffffe)
10334 #ifndef __ASSEMBLY__
10346 struct ALT_I2C_IC_ACK_GENERAL_CALL_s
10348 volatile uint32_t ACK_GEN_CALL : 1;
10349 const volatile uint32_t RSVD_IC_ACK_GEN_1_31 : 31;
10353 typedef struct ALT_I2C_IC_ACK_GENERAL_CALL_s ALT_I2C_IC_ACK_GENERAL_CALL_t;
10357 #define ALT_I2C_IC_ACK_GENERAL_CALL_RESET 0x00000001
10359 #define ALT_I2C_IC_ACK_GENERAL_CALL_OFST 0x98
10361 #define ALT_I2C_IC_ACK_GENERAL_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_ACK_GENERAL_CALL_OFST))
10448 #define ALT_I2C_IC_ENABLE_STATUS_IC_EN_E_DISABLED 0x0
10454 #define ALT_I2C_IC_ENABLE_STATUS_IC_EN_E_ENABLED 0x1
10457 #define ALT_I2C_IC_ENABLE_STATUS_IC_EN_LSB 0
10459 #define ALT_I2C_IC_ENABLE_STATUS_IC_EN_MSB 0
10461 #define ALT_I2C_IC_ENABLE_STATUS_IC_EN_WIDTH 1
10463 #define ALT_I2C_IC_ENABLE_STATUS_IC_EN_SET_MSK 0x00000001
10465 #define ALT_I2C_IC_ENABLE_STATUS_IC_EN_CLR_MSK 0xfffffffe
10467 #define ALT_I2C_IC_ENABLE_STATUS_IC_EN_RESET 0x0
10469 #define ALT_I2C_IC_ENABLE_STATUS_IC_EN_GET(value) (((value) & 0x00000001) >> 0)
10471 #define ALT_I2C_IC_ENABLE_STATUS_IC_EN_SET(value) (((value) << 0) & 0x00000001)
10539 #define ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_E_INACTIVE 0x0
10545 #define ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_E_ACTIVE 0x1
10548 #define ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_LSB 1
10550 #define ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MSB 1
10552 #define ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_WIDTH 1
10554 #define ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_SET_MSK 0x00000002
10556 #define ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_CLR_MSK 0xfffffffd
10558 #define ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_RESET 0x0
10560 #define ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_GET(value) (((value) & 0x00000002) >> 1)
10562 #define ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_SET(value) (((value) << 1) & 0x00000002)
10616 #define ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_E_INACTIVE 0x0
10622 #define ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_E_ACTIVE 0x1
10625 #define ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_LSB 2
10627 #define ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MSB 2
10629 #define ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_WIDTH 1
10631 #define ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_SET_MSK 0x00000004
10633 #define ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_CLR_MSK 0xfffffffb
10635 #define ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_RESET 0x0
10637 #define ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_GET(value) (((value) & 0x00000004) >> 2)
10639 #define ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_SET(value) (((value) << 2) & 0x00000004)
10650 #define ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS_LSB 3
10652 #define ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS_MSB 31
10654 #define ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS_WIDTH 29
10656 #define ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS_SET_MSK 0xfffffff8
10658 #define ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS_CLR_MSK 0x00000007
10660 #define ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS_RESET 0x0
10662 #define ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS_GET(value) (((value) & 0xfffffff8) >> 3)
10664 #define ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS_SET(value) (((value) << 3) & 0xfffffff8)
10666 #ifndef __ASSEMBLY__
10678 struct ALT_I2C_IC_ENABLE_STATUS_s
10680 const volatile uint32_t IC_EN : 1;
10681 const volatile uint32_t SLV_DISABLED_WHILE_BUSY : 1;
10682 const volatile uint32_t SLV_RX_DATA_LOST : 1;
10683 const volatile uint32_t RSVD_IC_ENABLE_STATUS : 29;
10687 typedef struct ALT_I2C_IC_ENABLE_STATUS_s ALT_I2C_IC_ENABLE_STATUS_t;
10691 #define ALT_I2C_IC_ENABLE_STATUS_RESET 0x00000000
10693 #define ALT_I2C_IC_ENABLE_STATUS_OFST 0x9c
10695 #define ALT_I2C_IC_ENABLE_STATUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_ENABLE_STATUS_OFST))
10758 #define ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_LSB 0
10760 #define ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_MSB 7
10762 #define ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_WIDTH 8
10764 #define ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_SET_MSK 0x000000ff
10766 #define ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_CLR_MSK 0xffffff00
10768 #define ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_RESET 0x2
10770 #define ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_GET(value) (((value) & 0x000000ff) >> 0)
10772 #define ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_SET(value) (((value) << 0) & 0x000000ff)
10783 #define ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN_LSB 8
10785 #define ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN_MSB 31
10787 #define ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN_WIDTH 24
10789 #define ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN_SET_MSK 0xffffff00
10791 #define ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN_CLR_MSK 0x000000ff
10793 #define ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN_RESET 0x0
10795 #define ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN_GET(value) (((value) & 0xffffff00) >> 8)
10797 #define ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN_SET(value) (((value) << 8) & 0xffffff00)
10799 #ifndef __ASSEMBLY__
10811 struct ALT_I2C_IC_FS_SPKLEN_s
10813 volatile uint32_t IC_FS_SPKLEN : 8;
10814 const volatile uint32_t RSVD_IC_FS_SPKLEN : 24;
10818 typedef struct ALT_I2C_IC_FS_SPKLEN_s ALT_I2C_IC_FS_SPKLEN_t;
10822 #define ALT_I2C_IC_FS_SPKLEN_RESET 0x00000002
10824 #define ALT_I2C_IC_FS_SPKLEN_OFST 0xa0
10826 #define ALT_I2C_IC_FS_SPKLEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_FS_SPKLEN_OFST))
10860 #define ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_LSB 0
10862 #define ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_MSB 0
10864 #define ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_WIDTH 1
10866 #define ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_SET_MSK 0x00000001
10868 #define ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_CLR_MSK 0xfffffffe
10870 #define ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_RESET 0x0
10872 #define ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_GET(value) (((value) & 0x00000001) >> 0)
10874 #define ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_SET(value) (((value) << 0) & 0x00000001)
10885 #define ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET_LSB 1
10887 #define ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET_MSB 31
10889 #define ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET_WIDTH 31
10891 #define ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET_SET_MSK 0xfffffffe
10893 #define ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET_CLR_MSK 0x00000001
10895 #define ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET_RESET 0x0
10897 #define ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET_GET(value) (((value) & 0xfffffffe) >> 1)
10899 #define ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET_SET(value) (((value) << 1) & 0xfffffffe)
10901 #ifndef __ASSEMBLY__
10913 struct ALT_I2C_IC_CLR_RESTART_DET_s
10915 const volatile uint32_t CLR_RESTART_DET : 1;
10916 const volatile uint32_t RSVD_IC_CLR_RESTART_DET : 31;
10920 typedef struct ALT_I2C_IC_CLR_RESTART_DET_s ALT_I2C_IC_CLR_RESTART_DET_t;
10924 #define ALT_I2C_IC_CLR_RESTART_DET_RESET 0x00000000
10926 #define ALT_I2C_IC_CLR_RESTART_DET_OFST 0xa8
10928 #define ALT_I2C_IC_CLR_RESTART_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_RESTART_DET_OFST))
10997 #define ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_E_APB_08BITS 0x0
11003 #define ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_E_APB_16BITS 0x1
11009 #define ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_E_APB_32BITS 0x2
11012 #define ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_LSB 0
11014 #define ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_MSB 1
11016 #define ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_WIDTH 2
11018 #define ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_SET_MSK 0x00000003
11020 #define ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc
11022 #define ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_RESET 0x2
11024 #define ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0)
11026 #define ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003)
11063 #define ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_E_STANDARD 0x1
11069 #define ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_E_FAST 0x2
11075 #define ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_E_HIGH 0x3
11078 #define ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_LSB 2
11080 #define ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_MSB 3
11082 #define ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_WIDTH 2
11084 #define ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_SET_MSK 0x0000000c
11086 #define ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_CLR_MSK 0xfffffff3
11088 #define ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_RESET 0x2
11090 #define ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_GET(value) (((value) & 0x0000000c) >> 2)
11092 #define ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_SET(value) (((value) << 2) & 0x0000000c)
11124 #define ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_E_DISABLED 0x0
11130 #define ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_E_ENABLED 0x1
11133 #define ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_LSB 4
11135 #define ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_MSB 4
11137 #define ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_WIDTH 1
11139 #define ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_SET_MSK 0x00000010
11141 #define ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_CLR_MSK 0xffffffef
11143 #define ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_RESET 0x0
11145 #define ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_GET(value) (((value) & 0x00000010) >> 4)
11147 #define ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_SET(value) (((value) << 4) & 0x00000010)
11177 #define ALT_I2C_IC_COMP_PARAM_1_INTR_IO_E_INDIVIDUAL 0x0
11183 #define ALT_I2C_IC_COMP_PARAM_1_INTR_IO_E_COMBINED 0x1
11186 #define ALT_I2C_IC_COMP_PARAM_1_INTR_IO_LSB 5
11188 #define ALT_I2C_IC_COMP_PARAM_1_INTR_IO_MSB 5
11190 #define ALT_I2C_IC_COMP_PARAM_1_INTR_IO_WIDTH 1
11192 #define ALT_I2C_IC_COMP_PARAM_1_INTR_IO_SET_MSK 0x00000020
11194 #define ALT_I2C_IC_COMP_PARAM_1_INTR_IO_CLR_MSK 0xffffffdf
11196 #define ALT_I2C_IC_COMP_PARAM_1_INTR_IO_RESET 0x1
11198 #define ALT_I2C_IC_COMP_PARAM_1_INTR_IO_GET(value) (((value) & 0x00000020) >> 5)
11200 #define ALT_I2C_IC_COMP_PARAM_1_INTR_IO_SET(value) (((value) << 5) & 0x00000020)
11230 #define ALT_I2C_IC_COMP_PARAM_1_HAS_DMA_E_DISABLED 0x0
11236 #define ALT_I2C_IC_COMP_PARAM_1_HAS_DMA_E_ENABLED 0x1
11239 #define ALT_I2C_IC_COMP_PARAM_1_HAS_DMA_LSB 6
11241 #define ALT_I2C_IC_COMP_PARAM_1_HAS_DMA_MSB 6
11243 #define ALT_I2C_IC_COMP_PARAM_1_HAS_DMA_WIDTH 1
11245 #define ALT_I2C_IC_COMP_PARAM_1_HAS_DMA_SET_MSK 0x00000040
11247 #define ALT_I2C_IC_COMP_PARAM_1_HAS_DMA_CLR_MSK 0xffffffbf
11249 #define ALT_I2C_IC_COMP_PARAM_1_HAS_DMA_RESET 0x1
11251 #define ALT_I2C_IC_COMP_PARAM_1_HAS_DMA_GET(value) (((value) & 0x00000040) >> 6)
11253 #define ALT_I2C_IC_COMP_PARAM_1_HAS_DMA_SET(value) (((value) << 6) & 0x00000040)
11295 #define ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_E_DISBALED 0x0
11301 #define ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_E_ENABLED 0x1
11304 #define ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_LSB 7
11306 #define ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_MSB 7
11308 #define ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_WIDTH 1
11310 #define ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_SET_MSK 0x00000080
11312 #define ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_CLR_MSK 0xffffff7f
11314 #define ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_RESET 0x1
11316 #define ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_GET(value) (((value) & 0x00000080) >> 7)
11318 #define ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_SET(value) (((value) << 7) & 0x00000080)
11343 #define ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_LSB 8
11345 #define ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_MSB 15
11347 #define ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_WIDTH 8
11349 #define ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_SET_MSK 0x0000ff00
11351 #define ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_CLR_MSK 0xffff00ff
11353 #define ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_RESET 0x3f
11355 #define ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_GET(value) (((value) & 0x0000ff00) >> 8)
11357 #define ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_SET(value) (((value) << 8) & 0x0000ff00)
11382 #define ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_LSB 16
11384 #define ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_MSB 23
11386 #define ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_WIDTH 8
11388 #define ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_SET_MSK 0x00ff0000
11390 #define ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_CLR_MSK 0xff00ffff
11392 #define ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_RESET 0x3f
11394 #define ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_GET(value) (((value) & 0x00ff0000) >> 16)
11396 #define ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_SET(value) (((value) << 16) & 0x00ff0000)
11407 #define ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1_LSB 24
11409 #define ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1_MSB 31
11411 #define ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1_WIDTH 8
11413 #define ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1_SET_MSK 0xff000000
11415 #define ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1_CLR_MSK 0x00ffffff
11417 #define ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1_RESET 0x0
11419 #define ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1_GET(value) (((value) & 0xff000000) >> 24)
11421 #define ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1_SET(value) (((value) << 24) & 0xff000000)
11423 #ifndef __ASSEMBLY__
11435 struct ALT_I2C_IC_COMP_PARAM_1_s
11437 const volatile uint32_t APB_DATA_WIDTH : 2;
11438 const volatile uint32_t MAX_SPEED_MODE : 2;
11439 const volatile uint32_t HC_COUNT_VALUES : 1;
11440 const volatile uint32_t INTR_IO : 1;
11441 const volatile uint32_t HAS_DMA : 1;
11442 const volatile uint32_t ADD_ENCODED_PARAMS : 1;
11443 const volatile uint32_t RX_BUFFER_DEPTH : 8;
11444 const volatile uint32_t TX_BUFFER_DEPTH : 8;
11445 const volatile uint32_t RSVD_IC_COMP_PARAM_1 : 8;
11449 typedef struct ALT_I2C_IC_COMP_PARAM_1_s ALT_I2C_IC_COMP_PARAM_1_t;
11453 #define ALT_I2C_IC_COMP_PARAM_1_RESET 0x003f3fea
11455 #define ALT_I2C_IC_COMP_PARAM_1_OFST 0xf4
11457 #define ALT_I2C_IC_COMP_PARAM_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_COMP_PARAM_1_OFST))
11490 #define ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION_LSB 0
11492 #define ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION_MSB 31
11494 #define ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION_WIDTH 32
11496 #define ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION_SET_MSK 0xffffffff
11498 #define ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION_CLR_MSK 0x00000000
11500 #define ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION_RESET 0x3230302a
11502 #define ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION_GET(value) (((value) & 0xffffffff) >> 0)
11504 #define ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION_SET(value) (((value) << 0) & 0xffffffff)
11506 #ifndef __ASSEMBLY__
11518 struct ALT_I2C_IC_COMP_VERSION_s
11520 const volatile uint32_t IC_COMP_VERSION : 32;
11524 typedef struct ALT_I2C_IC_COMP_VERSION_s ALT_I2C_IC_COMP_VERSION_t;
11528 #define ALT_I2C_IC_COMP_VERSION_RESET 0x3230302a
11530 #define ALT_I2C_IC_COMP_VERSION_OFST 0xf8
11532 #define ALT_I2C_IC_COMP_VERSION_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_COMP_VERSION_OFST))
11569 #define ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE_LSB 0
11571 #define ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE_MSB 31
11573 #define ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE_WIDTH 32
11575 #define ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE_SET_MSK 0xffffffff
11577 #define ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE_CLR_MSK 0x00000000
11579 #define ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE_RESET 0x44570140
11581 #define ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE_GET(value) (((value) & 0xffffffff) >> 0)
11583 #define ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE_SET(value) (((value) << 0) & 0xffffffff)
11585 #ifndef __ASSEMBLY__
11597 struct ALT_I2C_IC_COMP_TYPE_s
11599 const volatile uint32_t IC_COMP_TYPE : 32;
11603 typedef struct ALT_I2C_IC_COMP_TYPE_s ALT_I2C_IC_COMP_TYPE_t;
11607 #define ALT_I2C_IC_COMP_TYPE_RESET 0x44570140
11609 #define ALT_I2C_IC_COMP_TYPE_OFST 0xfc
11611 #define ALT_I2C_IC_COMP_TYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_COMP_TYPE_OFST))
11613 #ifndef __ASSEMBLY__
11627 volatile ALT_I2C_IC_CON_t IC_CON;
11628 volatile ALT_I2C_IC_TAR_t IC_TAR;
11629 volatile ALT_I2C_IC_SAR_t IC_SAR;
11630 volatile uint32_t _pad_0xc_0xf;
11631 volatile ALT_I2C_IC_DATA_CMD_t IC_DATA_CMD;
11632 volatile ALT_I2C_IC_SS_SCL_HCNT_t IC_SS_SCL_HCNT;
11633 volatile ALT_I2C_IC_SS_SCL_LCNT_t IC_SS_SCL_LCNT;
11634 volatile ALT_I2C_IC_FS_SCL_HCNT_t IC_FS_SCL_HCNT;
11635 volatile ALT_I2C_IC_FS_SCL_LCNT_t IC_FS_SCL_LCNT;
11636 volatile uint32_t _pad_0x24_0x2b[2];
11637 volatile ALT_I2C_IC_INTR_STAT_t IC_INTR_STAT;
11638 volatile ALT_I2C_IC_INTR_MASK_t IC_INTR_MASK;
11639 volatile ALT_I2C_IC_RAW_INTR_STAT_t IC_RAW_INTR_STAT;
11640 volatile ALT_I2C_IC_RX_TL_t IC_RX_TL;
11641 volatile ALT_I2C_IC_TX_TL_t IC_TX_TL;
11642 volatile ALT_I2C_IC_CLR_INTR_t IC_CLR_INTR;
11643 volatile ALT_I2C_IC_CLR_RX_UNDER_t IC_CLR_RX_UNDER;
11644 volatile ALT_I2C_IC_CLR_RX_OVER_t IC_CLR_RX_OVER;
11645 volatile ALT_I2C_IC_CLR_TX_OVER_t IC_CLR_TX_OVER;
11646 volatile ALT_I2C_IC_CLR_RD_REQ_t IC_CLR_RD_REQ;
11647 volatile ALT_I2C_IC_CLR_TX_ABRT_t IC_CLR_TX_ABRT;
11648 volatile ALT_I2C_IC_CLR_RX_DONE_t IC_CLR_RX_DONE;
11649 volatile ALT_I2C_IC_CLR_ACTIVITY_t IC_CLR_ACTIVITY;
11650 volatile ALT_I2C_IC_CLR_STOP_DET_t IC_CLR_STOP_DET;
11651 volatile ALT_I2C_IC_CLR_START_DET_t IC_CLR_START_DET;
11652 volatile ALT_I2C_IC_CLR_GEN_CALL_t IC_CLR_GEN_CALL;
11653 volatile ALT_I2C_IC_ENABLE_t IC_ENABLE;
11654 volatile ALT_I2C_IC_STATUS_t IC_STATUS;
11655 volatile ALT_I2C_IC_TXFLR_t IC_TXFLR;
11656 volatile ALT_I2C_IC_RXFLR_t IC_RXFLR;
11657 volatile ALT_I2C_IC_SDA_HOLD_t IC_SDA_HOLD;
11658 volatile ALT_I2C_IC_TX_ABRT_SOURCE_t IC_TX_ABRT_SOURCE;
11659 volatile ALT_I2C_IC_SLV_DATA_NACK_ONLY_t IC_SLV_DATA_NACK_ONLY;
11660 volatile ALT_I2C_IC_DMA_CR_t IC_DMA_CR;
11661 volatile ALT_I2C_IC_DMA_TDLR_t IC_DMA_TDLR;
11662 volatile ALT_I2C_IC_DMA_RDLR_t IC_DMA_RDLR;
11663 volatile ALT_I2C_IC_SDA_SETUP_t IC_SDA_SETUP;
11664 volatile ALT_I2C_IC_ACK_GENERAL_CALL_t IC_ACK_GENERAL_CALL;
11665 volatile ALT_I2C_IC_ENABLE_STATUS_t IC_ENABLE_STATUS;
11666 volatile ALT_I2C_IC_FS_SPKLEN_t IC_FS_SPKLEN;
11667 volatile uint32_t _pad_0xa4_0xa7;
11668 volatile ALT_I2C_IC_CLR_RESTART_DET_t IC_CLR_RESTART_DET;
11669 volatile uint32_t _pad_0xac_0xf3[18];
11670 volatile ALT_I2C_IC_COMP_PARAM_1_t IC_COMP_PARAM_1;
11671 volatile ALT_I2C_IC_COMP_VERSION_t IC_COMP_VERSION;
11672 volatile ALT_I2C_IC_COMP_TYPE_t IC_COMP_TYPE;
11676 typedef struct ALT_I2C_s ALT_I2C_t;
11678 struct ALT_I2C_raw_s
11680 volatile uint32_t IC_CON;
11681 volatile uint32_t IC_TAR;
11682 volatile uint32_t IC_SAR;
11683 volatile uint32_t _pad_0xc_0xf;
11684 volatile uint32_t IC_DATA_CMD;
11685 volatile uint32_t IC_SS_SCL_HCNT;
11686 volatile uint32_t IC_SS_SCL_LCNT;
11687 volatile uint32_t IC_FS_SCL_HCNT;
11688 volatile uint32_t IC_FS_SCL_LCNT;
11689 volatile uint32_t _pad_0x24_0x2b[2];
11690 volatile uint32_t IC_INTR_STAT;
11691 volatile uint32_t IC_INTR_MASK;
11692 volatile uint32_t IC_RAW_INTR_STAT;
11693 volatile uint32_t IC_RX_TL;
11694 volatile uint32_t IC_TX_TL;
11695 volatile uint32_t IC_CLR_INTR;
11696 volatile uint32_t IC_CLR_RX_UNDER;
11697 volatile uint32_t IC_CLR_RX_OVER;
11698 volatile uint32_t IC_CLR_TX_OVER;
11699 volatile uint32_t IC_CLR_RD_REQ;
11700 volatile uint32_t IC_CLR_TX_ABRT;
11701 volatile uint32_t IC_CLR_RX_DONE;
11702 volatile uint32_t IC_CLR_ACTIVITY;
11703 volatile uint32_t IC_CLR_STOP_DET;
11704 volatile uint32_t IC_CLR_START_DET;
11705 volatile uint32_t IC_CLR_GEN_CALL;
11706 volatile uint32_t IC_ENABLE;
11707 volatile uint32_t IC_STATUS;
11708 volatile uint32_t IC_TXFLR;
11709 volatile uint32_t IC_RXFLR;
11710 volatile uint32_t IC_SDA_HOLD;
11711 volatile uint32_t IC_TX_ABRT_SOURCE;
11712 volatile uint32_t IC_SLV_DATA_NACK_ONLY;
11713 volatile uint32_t IC_DMA_CR;
11714 volatile uint32_t IC_DMA_TDLR;
11715 volatile uint32_t IC_DMA_RDLR;
11716 volatile uint32_t IC_SDA_SETUP;
11717 volatile uint32_t IC_ACK_GENERAL_CALL;
11718 volatile uint32_t IC_ENABLE_STATUS;
11719 volatile uint32_t IC_FS_SPKLEN;
11720 volatile uint32_t _pad_0xa4_0xa7;
11721 volatile uint32_t IC_CLR_RESTART_DET;
11722 volatile uint32_t _pad_0xac_0xf3[18];
11723 volatile uint32_t IC_COMP_PARAM_1;
11724 volatile uint32_t IC_COMP_VERSION;
11725 volatile uint32_t IC_COMP_TYPE;
11729 typedef struct ALT_I2C_raw_s ALT_I2C_raw_t;