35 #ifndef __ALT_SOCAL_ECC_OCRAM_ECC_H__
36 #define __ALT_SOCAL_ECC_OCRAM_ECC_H__
74 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_LSB 0
76 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_MSB 15
78 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_WIDTH 16
80 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_SET_MSK 0x0000ffff
82 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_CLR_MSK 0xffff0000
84 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_RESET 0x0
86 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_GET(value) (((value) & 0x0000ffff) >> 0)
88 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_SET(value) (((value) << 0) & 0x0000ffff)
101 struct ALT_ECC_OCRAM_ECC_IP_REV_ID_s
103 const uint32_t SIREV : 16;
108 typedef volatile struct ALT_ECC_OCRAM_ECC_IP_REV_ID_s ALT_ECC_OCRAM_ECC_IP_REV_ID_t;
112 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_RESET 0x00000000
114 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_OFST 0x0
143 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_LSB 0
145 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_MSB 0
147 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_WIDTH 1
149 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_SET_MSK 0x00000001
151 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_CLR_MSK 0xfffffffe
153 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_RESET 0x0
155 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
157 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
173 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_LSB 1
175 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_MSB 1
177 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_WIDTH 1
179 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_SET_MSK 0x00000002
181 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_CLR_MSK 0xfffffffd
183 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_RESET 0x1
185 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_GET(value) (((value) & 0x00000002) >> 1)
187 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_SET(value) (((value) << 1) & 0x00000002)
198 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_LSB 8
200 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_MSB 8
202 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_WIDTH 1
204 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_SET_MSK 0x00000100
206 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_CLR_MSK 0xfffffeff
208 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_RESET 0x0
210 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_GET(value) (((value) & 0x00000100) >> 8)
212 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_SET(value) (((value) << 8) & 0x00000100)
223 #define ALT_ECC_OCRAM_ECC_CTL_INITA_LSB 16
225 #define ALT_ECC_OCRAM_ECC_CTL_INITA_MSB 16
227 #define ALT_ECC_OCRAM_ECC_CTL_INITA_WIDTH 1
229 #define ALT_ECC_OCRAM_ECC_CTL_INITA_SET_MSK 0x00010000
231 #define ALT_ECC_OCRAM_ECC_CTL_INITA_CLR_MSK 0xfffeffff
233 #define ALT_ECC_OCRAM_ECC_CTL_INITA_RESET 0x0
235 #define ALT_ECC_OCRAM_ECC_CTL_INITA_GET(value) (((value) & 0x00010000) >> 16)
237 #define ALT_ECC_OCRAM_ECC_CTL_INITA_SET(value) (((value) << 16) & 0x00010000)
250 struct ALT_ECC_OCRAM_ECC_CTL_s
253 uint32_t ECC_SLVERR_DIS : 1;
255 uint32_t CNT_RSTA : 1;
262 typedef volatile struct ALT_ECC_OCRAM_ECC_CTL_s ALT_ECC_OCRAM_ECC_CTL_t;
266 #define ALT_ECC_OCRAM_ECC_CTL_RESET 0x00000002
268 #define ALT_ECC_OCRAM_ECC_CTL_OFST 0x8
293 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_LSB 0
295 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_MSB 0
297 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_WIDTH 1
299 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_SET_MSK 0x00000001
301 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_CLR_MSK 0xfffffffe
303 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_RESET 0x0
305 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_GET(value) (((value) & 0x00000001) >> 0)
307 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_SET(value) (((value) << 0) & 0x00000001)
320 struct ALT_ECC_OCRAM_ECC_INITSTAT_s
322 uint32_t INITCOMPLETEA : 1;
327 typedef volatile struct ALT_ECC_OCRAM_ECC_INITSTAT_s ALT_ECC_OCRAM_ECC_INITSTAT_t;
331 #define ALT_ECC_OCRAM_ECC_INITSTAT_RESET 0x00000000
333 #define ALT_ECC_OCRAM_ECC_INITSTAT_OFST 0xc
357 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_LSB 0
359 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_MSB 0
361 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_WIDTH 1
363 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_SET_MSK 0x00000001
365 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_CLR_MSK 0xfffffffe
367 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_RESET 0x0
369 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_GET(value) (((value) & 0x00000001) >> 0)
371 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_SET(value) (((value) << 0) & 0x00000001)
384 struct ALT_ECC_OCRAM_ECC_ERRINTEN_s
386 uint32_t SERRINTEN : 1;
391 typedef volatile struct ALT_ECC_OCRAM_ECC_ERRINTEN_s ALT_ECC_OCRAM_ECC_ERRINTEN_t;
395 #define ALT_ECC_OCRAM_ECC_ERRINTEN_RESET 0x00000000
397 #define ALT_ECC_OCRAM_ECC_ERRINTEN_OFST 0x10
421 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_LSB 0
423 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_MSB 0
425 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_WIDTH 1
427 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_SET_MSK 0x00000001
429 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_CLR_MSK 0xfffffffe
431 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_RESET 0x0
433 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_GET(value) (((value) & 0x00000001) >> 0)
435 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_SET(value) (((value) << 0) & 0x00000001)
448 struct ALT_ECC_OCRAM_ECC_ERRINTENS_s
450 uint32_t SERRINTS : 1;
455 typedef volatile struct ALT_ECC_OCRAM_ECC_ERRINTENS_s ALT_ECC_OCRAM_ECC_ERRINTENS_t;
459 #define ALT_ECC_OCRAM_ECC_ERRINTENS_RESET 0x00000000
461 #define ALT_ECC_OCRAM_ECC_ERRINTENS_OFST 0x14
492 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_LSB 0
494 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_MSB 0
496 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_WIDTH 1
498 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_SET_MSK 0x00000001
500 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_CLR_MSK 0xfffffffe
502 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_RESET 0x0
504 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_GET(value) (((value) & 0x00000001) >> 0)
506 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_SET(value) (((value) << 0) & 0x00000001)
519 struct ALT_ECC_OCRAM_ECC_ERRINTENR_s
521 uint32_t SERRINTR : 1;
526 typedef volatile struct ALT_ECC_OCRAM_ECC_ERRINTENR_s ALT_ECC_OCRAM_ECC_ERRINTENR_t;
530 #define ALT_ECC_OCRAM_ECC_ERRINTENR_RESET 0x00000000
532 #define ALT_ECC_OCRAM_ECC_ERRINTENR_OFST 0x18
560 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_LSB 0
562 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_MSB 0
564 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_WIDTH 1
566 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_SET_MSK 0x00000001
568 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_CLR_MSK 0xfffffffe
570 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_RESET 0x0
572 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_GET(value) (((value) & 0x00000001) >> 0)
574 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_SET(value) (((value) << 0) & 0x00000001)
585 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_LSB 8
587 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_MSB 8
589 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_WIDTH 1
591 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_SET_MSK 0x00000100
593 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_CLR_MSK 0xfffffeff
595 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_RESET 0x0
597 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_GET(value) (((value) & 0x00000100) >> 8)
599 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_SET(value) (((value) << 8) & 0x00000100)
610 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_LSB 16
612 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_MSB 16
614 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_WIDTH 1
616 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_SET_MSK 0x00010000
618 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_CLR_MSK 0xfffeffff
620 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_RESET 0x0
622 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_GET(value) (((value) & 0x00010000) >> 16)
624 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_SET(value) (((value) << 16) & 0x00010000)
637 struct ALT_ECC_OCRAM_ECC_INTMOD_s
639 uint32_t INTMODE : 1;
641 uint32_t INTONOVF : 1;
643 uint32_t INTONCMP : 1;
648 typedef volatile struct ALT_ECC_OCRAM_ECC_INTMOD_s ALT_ECC_OCRAM_ECC_INTMOD_t;
652 #define ALT_ECC_OCRAM_ECC_INTMOD_RESET 0x00000000
654 #define ALT_ECC_OCRAM_ECC_INTMOD_OFST 0x1c
682 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_LSB 0
684 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_MSB 0
686 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_WIDTH 1
688 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_SET_MSK 0x00000001
690 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_CLR_MSK 0xfffffffe
692 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_RESET 0x0
694 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_GET(value) (((value) & 0x00000001) >> 0)
696 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_SET(value) (((value) << 0) & 0x00000001)
707 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_LSB 8
709 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_MSB 8
711 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_WIDTH 1
713 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_SET_MSK 0x00000100
715 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_CLR_MSK 0xfffffeff
717 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_RESET 0x0
719 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_GET(value) (((value) & 0x00000100) >> 8)
721 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_SET(value) (((value) << 8) & 0x00000100)
734 struct ALT_ECC_OCRAM_ECC_INTSTAT_s
736 uint32_t SERRPENA : 1;
738 uint32_t DERRPENA : 1;
743 typedef volatile struct ALT_ECC_OCRAM_ECC_INTSTAT_s ALT_ECC_OCRAM_ECC_INTSTAT_t;
747 #define ALT_ECC_OCRAM_ECC_INTSTAT_RESET 0x00000000
749 #define ALT_ECC_OCRAM_ECC_INTSTAT_OFST 0x20
775 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_LSB 0
777 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_MSB 0
779 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_WIDTH 1
781 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_SET_MSK 0x00000001
783 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_CLR_MSK 0xfffffffe
785 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_RESET 0x0
787 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_GET(value) (((value) & 0x00000001) >> 0)
789 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_SET(value) (((value) << 0) & 0x00000001)
800 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_LSB 8
802 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_MSB 8
804 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_WIDTH 1
806 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_SET_MSK 0x00000100
808 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_CLR_MSK 0xfffffeff
810 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_RESET 0x0
812 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_GET(value) (((value) & 0x00000100) >> 8)
814 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_SET(value) (((value) << 8) & 0x00000100)
827 struct ALT_ECC_OCRAM_ECC_INTTEST_s
836 typedef volatile struct ALT_ECC_OCRAM_ECC_INTTEST_s ALT_ECC_OCRAM_ECC_INTTEST_t;
840 #define ALT_ECC_OCRAM_ECC_INTTEST_RESET 0x00000000
842 #define ALT_ECC_OCRAM_ECC_INTTEST_OFST 0x24
866 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_LSB 0
868 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_MSB 0
870 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_WIDTH 1
872 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_SET_MSK 0x00000001
874 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_CLR_MSK 0xfffffffe
876 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_RESET 0x0
878 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_GET(value) (((value) & 0x00000001) >> 0)
880 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_SET(value) (((value) << 0) & 0x00000001)
893 struct ALT_ECC_OCRAM_ECC_MODSTAT_s
895 uint32_t CMPFLGA : 1;
900 typedef volatile struct ALT_ECC_OCRAM_ECC_MODSTAT_s ALT_ECC_OCRAM_ECC_MODSTAT_t;
904 #define ALT_ECC_OCRAM_ECC_MODSTAT_RESET 0x00000000
906 #define ALT_ECC_OCRAM_ECC_MODSTAT_OFST 0x28
931 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_LSB 0
933 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_MSB 14
935 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_WIDTH 15
937 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_SET_MSK 0x00007fff
939 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_CLR_MSK 0xffff8000
941 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_RESET 0x0
943 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_GET(value) (((value) & 0x00007fff) >> 0)
945 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_SET(value) (((value) << 0) & 0x00007fff)
958 struct ALT_ECC_OCRAM_ECC_DERRADDRA_s
960 uint32_t Address : 15;
965 typedef volatile struct ALT_ECC_OCRAM_ECC_DERRADDRA_s ALT_ECC_OCRAM_ECC_DERRADDRA_t;
969 #define ALT_ECC_OCRAM_ECC_DERRADDRA_RESET 0x00000000
971 #define ALT_ECC_OCRAM_ECC_DERRADDRA_OFST 0x2c
996 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_LSB 0
998 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_MSB 14
1000 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_WIDTH 15
1002 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_SET_MSK 0x00007fff
1004 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_CLR_MSK 0xffff8000
1006 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_RESET 0x0
1008 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_GET(value) (((value) & 0x00007fff) >> 0)
1010 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_SET(value) (((value) << 0) & 0x00007fff)
1012 #ifndef __ASSEMBLY__
1023 struct ALT_ECC_OCRAM_ECC_SERRADDRA_s
1025 uint32_t Address : 15;
1030 typedef volatile struct ALT_ECC_OCRAM_ECC_SERRADDRA_s ALT_ECC_OCRAM_ECC_SERRADDRA_t;
1034 #define ALT_ECC_OCRAM_ECC_SERRADDRA_RESET 0x00000000
1036 #define ALT_ECC_OCRAM_ECC_SERRADDRA_OFST 0x30
1059 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_LSB 0
1061 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_MSB 31
1063 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_WIDTH 32
1065 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_SET_MSK 0xffffffff
1067 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_CLR_MSK 0x00000000
1069 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_RESET 0x0
1071 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_GET(value) (((value) & 0xffffffff) >> 0)
1073 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_SET(value) (((value) << 0) & 0xffffffff)
1075 #ifndef __ASSEMBLY__
1086 struct ALT_ECC_OCRAM_ECC_SERRCNTREG_s
1088 uint32_t SERRCNT : 32;
1092 typedef volatile struct ALT_ECC_OCRAM_ECC_SERRCNTREG_s ALT_ECC_OCRAM_ECC_SERRCNTREG_t;
1096 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_RESET 0x00000000
1098 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_OFST 0x3c
1123 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_LSB 0
1125 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_MSB 14
1127 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_WIDTH 15
1129 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_SET_MSK 0x00007fff
1131 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_CLR_MSK 0xffff8000
1133 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_RESET 0x0
1135 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_GET(value) (((value) & 0x00007fff) >> 0)
1137 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_SET(value) (((value) << 0) & 0x00007fff)
1139 #ifndef __ASSEMBLY__
1150 struct ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_s
1152 uint32_t ECC_AddrBUS : 15;
1157 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_s ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_t;
1161 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_RESET 0x00000000
1163 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_OFST 0x40
1186 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_LSB 0
1188 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_MSB 31
1190 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_WIDTH 32
1192 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1194 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1196 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_RESET 0x0
1198 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1200 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1202 #ifndef __ASSEMBLY__
1213 struct ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_s
1215 uint32_t ECC_RDataBUS : 32;
1219 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_s ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_t;
1223 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_RESET 0x00000000
1225 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_OFST 0x44
1248 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_LSB 0
1250 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_MSB 31
1252 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_WIDTH 32
1254 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1256 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1258 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_RESET 0x0
1260 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1262 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1264 #ifndef __ASSEMBLY__
1275 struct ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_s
1277 uint32_t ECC_RDataBUS : 32;
1281 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_s ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_t;
1285 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_RESET 0x00000000
1287 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_OFST 0x48
1310 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_LSB 0
1312 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_MSB 31
1314 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_WIDTH 32
1316 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1318 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1320 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_RESET 0x0
1322 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1324 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1326 #ifndef __ASSEMBLY__
1337 struct ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_s
1339 uint32_t ECC_RDataBUS : 32;
1343 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_s ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_t;
1347 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_RESET 0x00000000
1349 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_OFST 0x4c
1372 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_LSB 0
1374 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_MSB 31
1376 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_WIDTH 32
1378 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1380 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1382 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_RESET 0x0
1384 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1386 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1388 #ifndef __ASSEMBLY__
1399 struct ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_s
1401 uint32_t ECC_RDataBUS : 32;
1405 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_s ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_t;
1409 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_RESET 0x00000000
1411 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_OFST 0x50
1434 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_LSB 0
1436 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_MSB 31
1438 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_WIDTH 32
1440 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1442 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1444 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_RESET 0x0
1446 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1448 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1450 #ifndef __ASSEMBLY__
1461 struct ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_s
1463 uint32_t ECC_WDataBUS : 32;
1467 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_s ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_t;
1471 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_RESET 0x00000000
1473 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_OFST 0x54
1496 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_LSB 0
1498 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_MSB 31
1500 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_WIDTH 32
1502 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1504 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1506 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_RESET 0x0
1508 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1510 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1512 #ifndef __ASSEMBLY__
1523 struct ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_s
1525 uint32_t ECC_WDataBUS : 32;
1529 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_s ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_t;
1533 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_RESET 0x00000000
1535 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_OFST 0x58
1558 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_LSB 0
1560 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_MSB 31
1562 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_WIDTH 32
1564 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1566 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1568 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_RESET 0x0
1570 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1572 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1574 #ifndef __ASSEMBLY__
1585 struct ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_s
1587 uint32_t ECC_WDataBUS : 32;
1591 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_s ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_t;
1595 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_RESET 0x00000000
1597 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_OFST 0x5c
1620 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_LSB 0
1622 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_MSB 31
1624 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_WIDTH 32
1626 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1628 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1630 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_RESET 0x0
1632 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1634 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1636 #ifndef __ASSEMBLY__
1647 struct ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_s
1649 uint32_t ECC_WDataBUS : 32;
1653 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_s ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_t;
1657 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_RESET 0x00000000
1659 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_OFST 0x60
1690 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_LSB 0
1692 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_MSB 4
1694 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_WIDTH 5
1696 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET_MSK 0x0000001f
1698 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_CLR_MSK 0xffffffe0
1700 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_RESET 0x0
1702 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_GET(value) (((value) & 0x0000001f) >> 0)
1704 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET(value) (((value) << 0) & 0x0000001f)
1715 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_LSB 8
1717 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_MSB 12
1719 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_WIDTH 5
1721 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET_MSK 0x00001f00
1723 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_CLR_MSK 0xffffe0ff
1725 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_RESET 0x0
1727 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_GET(value) (((value) & 0x00001f00) >> 8)
1729 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET(value) (((value) << 8) & 0x00001f00)
1740 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_LSB 16
1742 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_MSB 20
1744 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_WIDTH 5
1746 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET_MSK 0x001f0000
1748 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_CLR_MSK 0xffe0ffff
1750 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_RESET 0x0
1752 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_GET(value) (((value) & 0x001f0000) >> 16)
1754 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET(value) (((value) << 16) & 0x001f0000)
1765 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_LSB 24
1767 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_MSB 28
1769 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_WIDTH 5
1771 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET_MSK 0x1f000000
1773 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_CLR_MSK 0xe0ffffff
1775 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_RESET 0x0
1777 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_GET(value) (((value) & 0x1f000000) >> 24)
1779 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET(value) (((value) << 24) & 0x1f000000)
1781 #ifndef __ASSEMBLY__
1792 struct ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_s
1794 uint32_t ECC_RDataecc0BUS : 5;
1796 uint32_t ECC_RDataecc1BUS : 5;
1798 uint32_t ECC_RDataecc2BUS : 5;
1800 uint32_t ECC_RDataecc3BUS : 5;
1805 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_s ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_t;
1809 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_RESET 0x00000000
1811 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_OFST 0x64
1842 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_LSB 0
1844 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_MSB 4
1846 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_WIDTH 5
1848 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET_MSK 0x0000001f
1850 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_CLR_MSK 0xffffffe0
1852 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_RESET 0x0
1854 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_GET(value) (((value) & 0x0000001f) >> 0)
1856 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET(value) (((value) << 0) & 0x0000001f)
1867 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_LSB 8
1869 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_MSB 12
1871 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_WIDTH 5
1873 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET_MSK 0x00001f00
1875 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_CLR_MSK 0xffffe0ff
1877 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_RESET 0x0
1879 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_GET(value) (((value) & 0x00001f00) >> 8)
1881 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET(value) (((value) << 8) & 0x00001f00)
1892 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_LSB 16
1894 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_MSB 20
1896 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_WIDTH 5
1898 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET_MSK 0x001f0000
1900 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_CLR_MSK 0xffe0ffff
1902 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_RESET 0x0
1904 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_GET(value) (((value) & 0x001f0000) >> 16)
1906 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET(value) (((value) << 16) & 0x001f0000)
1917 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_LSB 24
1919 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_MSB 28
1921 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_WIDTH 5
1923 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET_MSK 0x1f000000
1925 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_CLR_MSK 0xe0ffffff
1927 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_RESET 0x0
1929 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_GET(value) (((value) & 0x1f000000) >> 24)
1931 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET(value) (((value) << 24) & 0x1f000000)
1933 #ifndef __ASSEMBLY__
1944 struct ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_s
1946 uint32_t ECC_RDataecc4BUS : 5;
1948 uint32_t ECC_RDataecc5BUS : 5;
1950 uint32_t ECC_RDataecc6BUS : 5;
1952 uint32_t ECC_RDataecc7BUS : 5;
1957 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_s ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_t;
1961 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_RESET 0x00000000
1963 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_OFST 0x68
1994 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_LSB 0
1996 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_MSB 4
1998 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_WIDTH 5
2000 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET_MSK 0x0000001f
2002 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_CLR_MSK 0xffffffe0
2004 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_RESET 0x0
2006 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_GET(value) (((value) & 0x0000001f) >> 0)
2008 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET(value) (((value) << 0) & 0x0000001f)
2019 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_LSB 8
2021 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_MSB 12
2023 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_WIDTH 5
2025 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET_MSK 0x00001f00
2027 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_CLR_MSK 0xffffe0ff
2029 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_RESET 0x0
2031 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_GET(value) (((value) & 0x00001f00) >> 8)
2033 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET(value) (((value) << 8) & 0x00001f00)
2044 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_LSB 16
2046 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_MSB 20
2048 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_WIDTH 5
2050 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET_MSK 0x001f0000
2052 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_CLR_MSK 0xffe0ffff
2054 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_RESET 0x0
2056 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_GET(value) (((value) & 0x001f0000) >> 16)
2058 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET(value) (((value) << 16) & 0x001f0000)
2069 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_LSB 24
2071 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_MSB 28
2073 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_WIDTH 5
2075 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET_MSK 0x1f000000
2077 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_CLR_MSK 0xe0ffffff
2079 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_RESET 0x0
2081 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_GET(value) (((value) & 0x1f000000) >> 24)
2083 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET(value) (((value) << 24) & 0x1f000000)
2085 #ifndef __ASSEMBLY__
2096 struct ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_s
2098 uint32_t ECC_WDataecc0BUS : 5;
2100 uint32_t ECC_WDataecc1BUS : 5;
2102 uint32_t ECC_WDataecc2BUS : 5;
2104 uint32_t ECC_WDataecc3BUS : 5;
2109 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_s ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_t;
2113 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_RESET 0x00000000
2115 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_OFST 0x6c
2146 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_LSB 0
2148 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_MSB 4
2150 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_WIDTH 5
2152 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET_MSK 0x0000001f
2154 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_CLR_MSK 0xffffffe0
2156 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_RESET 0x0
2158 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_GET(value) (((value) & 0x0000001f) >> 0)
2160 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET(value) (((value) << 0) & 0x0000001f)
2171 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_LSB 8
2173 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_MSB 12
2175 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_WIDTH 5
2177 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET_MSK 0x00001f00
2179 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_CLR_MSK 0xffffe0ff
2181 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_RESET 0x0
2183 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_GET(value) (((value) & 0x00001f00) >> 8)
2185 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET(value) (((value) << 8) & 0x00001f00)
2196 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_LSB 16
2198 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_MSB 20
2200 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_WIDTH 5
2202 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET_MSK 0x001f0000
2204 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_CLR_MSK 0xffe0ffff
2206 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_RESET 0x0
2208 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_GET(value) (((value) & 0x001f0000) >> 16)
2210 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET(value) (((value) << 16) & 0x001f0000)
2221 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_LSB 24
2223 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_MSB 28
2225 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_WIDTH 5
2227 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET_MSK 0x1f000000
2229 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_CLR_MSK 0xe0ffffff
2231 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_RESET 0x0
2233 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_GET(value) (((value) & 0x1f000000) >> 24)
2235 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET(value) (((value) << 24) & 0x1f000000)
2237 #ifndef __ASSEMBLY__
2248 struct ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_s
2250 uint32_t ECC_WDataecc4BUS : 5;
2252 uint32_t ECC_WDataecc5BUS : 5;
2254 uint32_t ECC_WDataecc6BUS : 5;
2256 uint32_t ECC_WDataecc7BUS : 5;
2261 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_s ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_t;
2265 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_RESET 0x00000000
2267 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_OFST 0x70
2291 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_LSB 0
2293 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_MSB 7
2295 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_WIDTH 8
2297 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_SET_MSK 0x000000ff
2299 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_CLR_MSK 0xffffff00
2301 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_RESET 0x0
2303 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_GET(value) (((value) & 0x000000ff) >> 0)
2305 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_SET(value) (((value) << 0) & 0x000000ff)
2307 #ifndef __ASSEMBLY__
2318 struct ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_s
2325 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_s ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_t;
2329 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_RESET 0x00000000
2331 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_OFST 0x74
2363 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_LSB 0
2365 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_MSB 0
2367 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_WIDTH 1
2369 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_SET_MSK 0x00000001
2371 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_CLR_MSK 0xfffffffe
2373 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_RESET 0x0
2375 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_GET(value) (((value) & 0x00000001) >> 0)
2377 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_SET(value) (((value) << 0) & 0x00000001)
2388 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_LSB 1
2390 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_MSB 1
2392 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_WIDTH 1
2394 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_SET_MSK 0x00000002
2396 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_CLR_MSK 0xfffffffd
2398 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_RESET 0x0
2400 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_GET(value) (((value) & 0x00000002) >> 1)
2402 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_SET(value) (((value) << 1) & 0x00000002)
2413 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_LSB 8
2415 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_MSB 8
2417 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_WIDTH 1
2419 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_SET_MSK 0x00000100
2421 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_CLR_MSK 0xfffffeff
2423 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_RESET 0x0
2425 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_GET(value) (((value) & 0x00000100) >> 8)
2427 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_SET(value) (((value) << 8) & 0x00000100)
2429 #ifndef __ASSEMBLY__
2440 struct ALT_ECC_OCRAM_ECC_ECC_ACCCTL_s
2442 uint32_t DATAOVR : 1;
2443 uint32_t ECCOVR : 1;
2450 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_ACCCTL_s ALT_ECC_OCRAM_ECC_ECC_ACCCTL_t;
2454 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RESET 0x00000000
2456 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_OFST 0x78
2481 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_LSB 16
2483 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_MSB 16
2485 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_WIDTH 1
2487 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_SET_MSK 0x00010000
2489 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_CLR_MSK 0xfffeffff
2491 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_RESET 0x0
2493 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_GET(value) (((value) & 0x00010000) >> 16)
2495 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_SET(value) (((value) << 16) & 0x00010000)
2497 #ifndef __ASSEMBLY__
2508 struct ALT_ECC_OCRAM_ECC_ECC_STARTACC_s
2511 uint32_t ENBUSA : 1;
2516 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_STARTACC_s ALT_ECC_OCRAM_ECC_ECC_STARTACC_t;
2520 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_RESET 0x00000000
2522 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_OFST 0x7c
2546 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_LSB 0
2548 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_MSB 0
2550 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_WIDTH 1
2552 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_SET_MSK 0x00000001
2554 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_CLR_MSK 0xfffffffe
2556 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_RESET 0x0
2558 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_GET(value) (((value) & 0x00000001) >> 0)
2560 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_SET(value) (((value) << 0) & 0x00000001)
2562 #ifndef __ASSEMBLY__
2573 struct ALT_ECC_OCRAM_ECC_ECC_WDCTL_s
2575 uint32_t WDEN_RAM : 1;
2580 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_WDCTL_s ALT_ECC_OCRAM_ECC_ECC_WDCTL_t;
2584 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_RESET 0x00000000
2586 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_OFST 0x80
2615 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_LSB 0
2617 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_MSB 14
2619 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_WIDTH 15
2621 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_SET_MSK 0x00007fff
2623 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_CLR_MSK 0xffff8000
2625 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_RESET 0x0
2627 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_GET(value) (((value) & 0x00007fff) >> 0)
2629 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_SET(value) (((value) << 0) & 0x00007fff)
2641 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_LSB 31
2643 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_MSB 31
2645 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_WIDTH 1
2647 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_SET_MSK 0x80000000
2649 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_CLR_MSK 0x7fffffff
2651 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_RESET 0x0
2653 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_GET(value) (((value) & 0x80000000) >> 31)
2655 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_SET(value) (((value) << 31) & 0x80000000)
2657 #ifndef __ASSEMBLY__
2668 struct ALT_ECC_OCRAM_ECC_SERRLKUPA0_s
2670 const uint32_t Address : 15;
2676 typedef volatile struct ALT_ECC_OCRAM_ECC_SERRLKUPA0_s ALT_ECC_OCRAM_ECC_SERRLKUPA0_t;
2680 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_RESET 0x00000000
2682 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_OFST 0x90
2684 #ifndef __ASSEMBLY__
2695 struct ALT_ECC_OCRAM_ECC_s
2697 ALT_ECC_OCRAM_ECC_IP_REV_ID_t IP_REV_ID;
2698 volatile uint32_t _pad_0x4_0x7;
2699 ALT_ECC_OCRAM_ECC_CTL_t CTRL;
2700 ALT_ECC_OCRAM_ECC_INITSTAT_t INITSTAT;
2701 ALT_ECC_OCRAM_ECC_ERRINTEN_t ERRINTEN;
2702 ALT_ECC_OCRAM_ECC_ERRINTENS_t ERRINTENS;
2703 ALT_ECC_OCRAM_ECC_ERRINTENR_t ERRINTENR;
2704 ALT_ECC_OCRAM_ECC_INTMOD_t INTMODE;
2705 ALT_ECC_OCRAM_ECC_INTSTAT_t INTSTAT;
2706 ALT_ECC_OCRAM_ECC_INTTEST_t INTTEST;
2707 ALT_ECC_OCRAM_ECC_MODSTAT_t MODSTAT;
2708 ALT_ECC_OCRAM_ECC_DERRADDRA_t DERRADDRA;
2709 ALT_ECC_OCRAM_ECC_SERRADDRA_t SERRADDRA;
2710 volatile uint32_t _pad_0x34_0x3b[2];
2711 ALT_ECC_OCRAM_ECC_SERRCNTREG_t SERRCNTREG;
2712 ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_t ECC_Addrbus;
2713 ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_t ECC_RData0bus;
2714 ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_t ECC_RData1bus;
2715 ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_t ECC_RData2bus;
2716 ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_t ECC_RData3bus;
2717 ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_t ECC_WData0bus;
2718 ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_t ECC_WData1bus;
2719 ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_t ECC_WData2bus;
2720 ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_t ECC_WData3bus;
2721 ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_t ECC_RDataecc0bus;
2722 ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_t ECC_RDataecc1bus;
2723 ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_t ECC_WDataecc0bus;
2724 ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_t ECC_WDataecc1bus;
2725 ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_t ECC_dbytectrl;
2726 ALT_ECC_OCRAM_ECC_ECC_ACCCTL_t ECC_accctrl;
2727 ALT_ECC_OCRAM_ECC_ECC_STARTACC_t ECC_startacc;
2728 ALT_ECC_OCRAM_ECC_ECC_WDCTL_t ECC_wdctrl;
2729 volatile uint32_t _pad_0x84_0x8f[3];
2730 ALT_ECC_OCRAM_ECC_SERRLKUPA0_t SERRLKUPA0;
2731 volatile uint32_t _pad_0x94_0x400[219];
2735 typedef volatile struct ALT_ECC_OCRAM_ECC_s ALT_ECC_OCRAM_ECC_t;
2737 struct ALT_ECC_OCRAM_ECC_raw_s
2739 volatile uint32_t IP_REV_ID;
2740 uint32_t _pad_0x4_0x7;
2741 volatile uint32_t CTRL;
2742 volatile uint32_t INITSTAT;
2743 volatile uint32_t ERRINTEN;
2744 volatile uint32_t ERRINTENS;
2745 volatile uint32_t ERRINTENR;
2746 volatile uint32_t INTMODE;
2747 volatile uint32_t INTSTAT;
2748 volatile uint32_t INTTEST;
2749 volatile uint32_t MODSTAT;
2750 volatile uint32_t DERRADDRA;
2751 volatile uint32_t SERRADDRA;
2752 uint32_t _pad_0x34_0x3b[2];
2753 volatile uint32_t SERRCNTREG;
2754 volatile uint32_t ECC_Addrbus;
2755 volatile uint32_t ECC_RData0bus;
2756 volatile uint32_t ECC_RData1bus;
2757 volatile uint32_t ECC_RData2bus;
2758 volatile uint32_t ECC_RData3bus;
2759 volatile uint32_t ECC_WData0bus;
2760 volatile uint32_t ECC_WData1bus;
2761 volatile uint32_t ECC_WData2bus;
2762 volatile uint32_t ECC_WData3bus;
2763 volatile uint32_t ECC_RDataecc0bus;
2764 volatile uint32_t ECC_RDataecc1bus;
2765 volatile uint32_t ECC_WDataecc0bus;
2766 volatile uint32_t ECC_WDataecc1bus;
2767 volatile uint32_t ECC_dbytectrl;
2768 volatile uint32_t ECC_accctrl;
2769 volatile uint32_t ECC_startacc;
2770 volatile uint32_t ECC_wdctrl;
2771 uint32_t _pad_0x84_0x8f[3];
2772 volatile uint32_t SERRLKUPA0;
2773 uint32_t _pad_0x94_0x400[219];
2777 typedef volatile struct ALT_ECC_OCRAM_ECC_raw_s ALT_ECC_OCRAM_ECC_raw_t;