35 #ifndef __ALT_SOCAL_SOC_NOC_FW_MPFE_CSR_H__
36 #define __ALT_SOCAL_SOC_NOC_FW_MPFE_CSR_H__
81 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU_LSB 0
83 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU_MSB 0
85 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU_WIDTH 1
87 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU_SET_MSK 0x00000001
89 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU_CLR_MSK 0xfffffffe
91 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU_RESET 0x0
93 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU_GET(value) (((value) & 0x00000001) >> 0)
95 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU_SET(value) (((value) << 0) & 0x00000001)
108 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC_LSB 8
110 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC_MSB 8
112 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC_WIDTH 1
114 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC_SET_MSK 0x00000100
116 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC_CLR_MSK 0xfffffeff
118 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC_RESET 0x0
120 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC_GET(value) (((value) & 0x00000100) >> 8)
122 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC_SET(value) (((value) << 8) & 0x00000100)
135 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP_LSB 16
137 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP_MSB 16
139 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP_WIDTH 1
141 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP_SET_MSK 0x00010000
143 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP_CLR_MSK 0xfffeffff
145 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP_RESET 0x0
147 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP_GET(value) (((value) & 0x00010000) >> 16)
149 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP_SET(value) (((value) << 16) & 0x00010000)
163 struct ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_s
165 volatile uint32_t mpu : 1;
167 volatile uint32_t fpga2soc : 1;
169 volatile uint32_t axi_ap : 1;
174 typedef struct ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_s ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_t;
178 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_RESET 0x00000000
180 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_OFST 0x0
210 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU_LSB 0
212 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU_MSB 0
214 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU_WIDTH 1
216 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU_SET_MSK 0x00000001
218 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU_CLR_MSK 0xfffffffe
220 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU_RESET 0x0
222 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU_GET(value) (((value) & 0x00000001) >> 0)
224 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU_SET(value) (((value) << 0) & 0x00000001)
237 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC_LSB 8
239 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC_MSB 8
241 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC_WIDTH 1
243 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC_SET_MSK 0x00000100
245 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC_CLR_MSK 0xfffffeff
247 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC_RESET 0x0
249 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC_GET(value) (((value) & 0x00000100) >> 8)
251 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC_SET(value) (((value) << 8) & 0x00000100)
264 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP_LSB 16
266 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP_MSB 16
268 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP_WIDTH 1
270 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP_SET_MSK 0x00010000
272 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP_CLR_MSK 0xfffeffff
274 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP_RESET 0x0
276 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP_GET(value) (((value) & 0x00010000) >> 16)
278 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP_SET(value) (((value) << 16) & 0x00010000)
292 struct ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_s
294 volatile uint32_t mpu : 1;
296 volatile uint32_t fpga2soc : 1;
298 volatile uint32_t axi_ap : 1;
303 typedef struct ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_s ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_t;
307 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_RESET 0x00000000
309 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_OFST 0x4
339 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU_LSB 0
341 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU_MSB 0
343 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU_WIDTH 1
345 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU_SET_MSK 0x00000001
347 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU_CLR_MSK 0xfffffffe
349 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU_RESET 0x0
351 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU_GET(value) (((value) & 0x00000001) >> 0)
353 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU_SET(value) (((value) << 0) & 0x00000001)
366 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC_LSB 8
368 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC_MSB 8
370 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC_WIDTH 1
372 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC_SET_MSK 0x00000100
374 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC_CLR_MSK 0xfffffeff
376 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC_RESET 0x0
378 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC_GET(value) (((value) & 0x00000100) >> 8)
380 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC_SET(value) (((value) << 8) & 0x00000100)
393 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP_LSB 16
395 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP_MSB 16
397 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP_WIDTH 1
399 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP_SET_MSK 0x00010000
401 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP_CLR_MSK 0xfffeffff
403 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP_RESET 0x0
405 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP_GET(value) (((value) & 0x00010000) >> 16)
407 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP_SET(value) (((value) << 16) & 0x00010000)
421 struct ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_s
423 volatile uint32_t mpu : 1;
425 volatile uint32_t fpga2soc : 1;
427 volatile uint32_t axi_ap : 1;
432 typedef struct ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_s ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_t;
436 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_RESET 0x00000000
438 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_OFST 0x8
468 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU_LSB 0
470 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU_MSB 0
472 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU_WIDTH 1
474 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU_SET_MSK 0x00000001
476 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU_CLR_MSK 0xfffffffe
478 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU_RESET 0x0
480 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU_GET(value) (((value) & 0x00000001) >> 0)
482 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU_SET(value) (((value) << 0) & 0x00000001)
495 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC_LSB 8
497 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC_MSB 8
499 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC_WIDTH 1
501 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC_SET_MSK 0x00000100
503 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC_CLR_MSK 0xfffffeff
505 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC_RESET 0x0
507 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC_GET(value) (((value) & 0x00000100) >> 8)
509 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC_SET(value) (((value) << 8) & 0x00000100)
522 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP_LSB 16
524 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP_MSB 16
526 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP_WIDTH 1
528 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP_SET_MSK 0x00010000
530 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP_CLR_MSK 0xfffeffff
532 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP_RESET 0x0
534 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP_GET(value) (((value) & 0x00010000) >> 16)
536 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP_SET(value) (((value) << 16) & 0x00010000)
550 struct ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_s
552 volatile uint32_t mpu : 1;
554 volatile uint32_t fpga2soc : 1;
556 volatile uint32_t axi_ap : 1;
561 typedef struct ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_s ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_t;
565 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_RESET 0x00000000
567 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_OFST 0x10
597 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU_LSB 0
599 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU_MSB 0
601 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU_WIDTH 1
603 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU_SET_MSK 0x00000001
605 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU_CLR_MSK 0xfffffffe
607 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU_RESET 0x0
609 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU_GET(value) (((value) & 0x00000001) >> 0)
611 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU_SET(value) (((value) << 0) & 0x00000001)
624 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC_LSB 8
626 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC_MSB 8
628 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC_WIDTH 1
630 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC_SET_MSK 0x00000100
632 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC_CLR_MSK 0xfffffeff
634 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC_RESET 0x0
636 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC_GET(value) (((value) & 0x00000100) >> 8)
638 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC_SET(value) (((value) << 8) & 0x00000100)
651 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP_LSB 16
653 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP_MSB 16
655 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP_WIDTH 1
657 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP_SET_MSK 0x00010000
659 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP_CLR_MSK 0xfffeffff
661 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP_RESET 0x0
663 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP_GET(value) (((value) & 0x00010000) >> 16)
665 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP_SET(value) (((value) << 16) & 0x00010000)
679 struct ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_s
681 volatile uint32_t mpu : 1;
683 volatile uint32_t fpga2soc : 1;
685 volatile uint32_t axi_ap : 1;
690 typedef struct ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_s ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_t;
694 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_RESET 0x00000000
696 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_OFST 0x14
726 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU_LSB 0
728 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU_MSB 0
730 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU_WIDTH 1
732 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU_SET_MSK 0x00000001
734 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU_CLR_MSK 0xfffffffe
736 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU_RESET 0x0
738 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU_GET(value) (((value) & 0x00000001) >> 0)
740 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU_SET(value) (((value) << 0) & 0x00000001)
753 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC_LSB 8
755 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC_MSB 8
757 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC_WIDTH 1
759 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC_SET_MSK 0x00000100
761 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC_CLR_MSK 0xfffffeff
763 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC_RESET 0x0
765 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC_GET(value) (((value) & 0x00000100) >> 8)
767 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC_SET(value) (((value) << 8) & 0x00000100)
780 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP_LSB 16
782 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP_MSB 16
784 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP_WIDTH 1
786 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP_SET_MSK 0x00010000
788 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP_CLR_MSK 0xfffeffff
790 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP_RESET 0x0
792 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP_GET(value) (((value) & 0x00010000) >> 16)
794 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP_SET(value) (((value) << 16) & 0x00010000)
808 struct ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_s
810 volatile uint32_t mpu : 1;
812 volatile uint32_t fpga2soc : 1;
814 volatile uint32_t axi_ap : 1;
819 typedef struct ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_s ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_t;
823 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_RESET 0x00000000
825 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_OFST 0x18
839 struct ALT_SOC_NOC_FW_MPFE_CSR_s
841 volatile ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_t hmc_register;
842 volatile ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_t hmc_adaptor_register;
843 volatile ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_t noc_scheduler_csr;
844 volatile uint32_t _pad_0xc_0xf;
845 volatile ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_t noc_qos;
846 volatile ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_t noc_probes;
847 volatile ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_t fpga2sdram_sidebandmgr;
848 volatile uint32_t _pad_0x1c_0x100[57];
852 typedef struct ALT_SOC_NOC_FW_MPFE_CSR_s ALT_SOC_NOC_FW_MPFE_CSR_t;
854 struct ALT_SOC_NOC_FW_MPFE_CSR_raw_s
856 volatile uint32_t hmc_register;
857 volatile uint32_t hmc_adaptor_register;
858 volatile uint32_t noc_scheduler_csr;
859 volatile uint32_t _pad_0xc_0xf;
860 volatile uint32_t noc_qos;
861 volatile uint32_t noc_probes;
862 volatile uint32_t fpga2sdram_sidebandmgr;
863 volatile uint32_t _pad_0x1c_0x100[57];
867 typedef struct ALT_SOC_NOC_FW_MPFE_CSR_raw_s ALT_SOC_NOC_FW_MPFE_CSR_raw_t;