Hardware Libraries  20.1
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alt_i2c.h
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32 
33 /* Altera - ALT_I2C */
34 
35 #ifndef __ALTERA_ALT_I2C_H__
36 #define __ALTERA_ALT_I2C_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
43 /*
44  * Component : I2C Module - ALT_I2C
45  * I2C Module
46  *
47  * Registers in the I2C module
48  *
49  */
50 /*
51  * Register : Control Register - ic_con
52  *
53  * This register can be written only when the I2C is disabled, which corresponds to
54  * the Bit [0] of the Enable Register being set to 0. Writes at other times have no
55  * effect.
56  *
57  * Register Layout
58  *
59  * Bits | Access | Reset | Description
60  * :-------|:-------|:------|:---------------------
61  * [0] | RW | 0x1 | Master Enable
62  * [2:1] | RW | 0x2 | Master Speed Control
63  * [3] | RW | 0x1 | Slave Address Size
64  * [4] | RW | 0x1 | Master Address Size
65  * [5] | RW | 0x1 | Restart Enable
66  * [6] | RW | 0x1 | Slave Disable
67  * [31:7] | ??? | 0x0 | *UNDEFINED*
68  *
69  */
70 /*
71  * Field : Master Enable - master_mode
72  *
73  * This bit controls whether the i2c master is enabled.
74  *
75  * NOTE: Software should ensure that if this bit is written with '1', then bit 6
76  * should also be written with a '1'.
77  *
78  * Field Enumeration Values:
79  *
80  * Enum | Value | Description
81  * :--------------------------|:------|:----------------
82  * ALT_I2C_CON_MST_MOD_E_DIS | 0x0 | master disabled
83  * ALT_I2C_CON_MST_MOD_E_EN | 0x1 | master enabled
84  *
85  * Field Access Macros:
86  *
87  */
88 /*
89  * Enumerated value for register field ALT_I2C_CON_MST_MOD
90  *
91  * master disabled
92  */
93 #define ALT_I2C_CON_MST_MOD_E_DIS 0x0
94 /*
95  * Enumerated value for register field ALT_I2C_CON_MST_MOD
96  *
97  * master enabled
98  */
99 #define ALT_I2C_CON_MST_MOD_E_EN 0x1
100 
101 /* The Least Significant Bit (LSB) position of the ALT_I2C_CON_MST_MOD register field. */
102 #define ALT_I2C_CON_MST_MOD_LSB 0
103 /* The Most Significant Bit (MSB) position of the ALT_I2C_CON_MST_MOD register field. */
104 #define ALT_I2C_CON_MST_MOD_MSB 0
105 /* The width in bits of the ALT_I2C_CON_MST_MOD register field. */
106 #define ALT_I2C_CON_MST_MOD_WIDTH 1
107 /* The mask used to set the ALT_I2C_CON_MST_MOD register field value. */
108 #define ALT_I2C_CON_MST_MOD_SET_MSK 0x00000001
109 /* The mask used to clear the ALT_I2C_CON_MST_MOD register field value. */
110 #define ALT_I2C_CON_MST_MOD_CLR_MSK 0xfffffffe
111 /* The reset value of the ALT_I2C_CON_MST_MOD register field. */
112 #define ALT_I2C_CON_MST_MOD_RESET 0x1
113 /* Extracts the ALT_I2C_CON_MST_MOD field value from a register. */
114 #define ALT_I2C_CON_MST_MOD_GET(value) (((value) & 0x00000001) >> 0)
115 /* Produces a ALT_I2C_CON_MST_MOD register field value suitable for setting the register. */
116 #define ALT_I2C_CON_MST_MOD_SET(value) (((value) << 0) & 0x00000001)
117 
118 /*
119  * Field : Master Speed Control - speed
120  *
121  * These bits control at which speed the I2C operates, its setting is relevant only
122  * if one is operating the I2C in master mode. Hardware protects against illegal
123  * values being programmed by software. This field should be programmed only with
124  * standard or fast speed.
125  *
126  * Field Enumeration Values:
127  *
128  * Enum | Value | Description
129  * :-----------------------------|:------|:---------------------------
130  * ALT_I2C_CON_SPEED_E_STANDARD | 0x1 | standard mode (100 kbit/s)
131  * ALT_I2C_CON_SPEED_E_FAST | 0x2 | fast mode (400 kbit/s)
132  *
133  * Field Access Macros:
134  *
135  */
136 /*
137  * Enumerated value for register field ALT_I2C_CON_SPEED
138  *
139  * standard mode (100 kbit/s)
140  */
141 #define ALT_I2C_CON_SPEED_E_STANDARD 0x1
142 /*
143  * Enumerated value for register field ALT_I2C_CON_SPEED
144  *
145  * fast mode (400 kbit/s)
146  */
147 #define ALT_I2C_CON_SPEED_E_FAST 0x2
148 
149 /* The Least Significant Bit (LSB) position of the ALT_I2C_CON_SPEED register field. */
150 #define ALT_I2C_CON_SPEED_LSB 1
151 /* The Most Significant Bit (MSB) position of the ALT_I2C_CON_SPEED register field. */
152 #define ALT_I2C_CON_SPEED_MSB 2
153 /* The width in bits of the ALT_I2C_CON_SPEED register field. */
154 #define ALT_I2C_CON_SPEED_WIDTH 2
155 /* The mask used to set the ALT_I2C_CON_SPEED register field value. */
156 #define ALT_I2C_CON_SPEED_SET_MSK 0x00000006
157 /* The mask used to clear the ALT_I2C_CON_SPEED register field value. */
158 #define ALT_I2C_CON_SPEED_CLR_MSK 0xfffffff9
159 /* The reset value of the ALT_I2C_CON_SPEED register field. */
160 #define ALT_I2C_CON_SPEED_RESET 0x2
161 /* Extracts the ALT_I2C_CON_SPEED field value from a register. */
162 #define ALT_I2C_CON_SPEED_GET(value) (((value) & 0x00000006) >> 1)
163 /* Produces a ALT_I2C_CON_SPEED register field value suitable for setting the register. */
164 #define ALT_I2C_CON_SPEED_SET(value) (((value) << 1) & 0x00000006)
165 
166 /*
167  * Field : Slave Address Size - ic_10bitaddr_slave
168  *
169  * When acting as a slave, this bit controls whether the I2C responds to 7- or
170  * 10-bit addresses. In 7-bit addressing, only the lower 7 bits of the Slave
171  * Address Register are compared. The I2C responds will only respond to 10-bit
172  * addressing transfers that match the full 10 bits of the Slave Address register.
173  *
174  * Field Enumeration Values:
175  *
176  * Enum | Value | Description
177  * :--------------------------------------------|:------|:------------------
178  * ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT | 0x0 | 7-bit addressing
179  * ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT | 0x1 | 10-bit addressing
180  *
181  * Field Access Macros:
182  *
183  */
184 /*
185  * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_SLV
186  *
187  * 7-bit addressing
188  */
189 #define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT 0x0
190 /*
191  * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_SLV
192  *
193  * 10-bit addressing
194  */
195 #define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT 0x1
196 
197 /* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */
198 #define ALT_I2C_CON_IC_10BITADDR_SLV_LSB 3
199 /* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */
200 #define ALT_I2C_CON_IC_10BITADDR_SLV_MSB 3
201 /* The width in bits of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */
202 #define ALT_I2C_CON_IC_10BITADDR_SLV_WIDTH 1
203 /* The mask used to set the ALT_I2C_CON_IC_10BITADDR_SLV register field value. */
204 #define ALT_I2C_CON_IC_10BITADDR_SLV_SET_MSK 0x00000008
205 /* The mask used to clear the ALT_I2C_CON_IC_10BITADDR_SLV register field value. */
206 #define ALT_I2C_CON_IC_10BITADDR_SLV_CLR_MSK 0xfffffff7
207 /* The reset value of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */
208 #define ALT_I2C_CON_IC_10BITADDR_SLV_RESET 0x1
209 /* Extracts the ALT_I2C_CON_IC_10BITADDR_SLV field value from a register. */
210 #define ALT_I2C_CON_IC_10BITADDR_SLV_GET(value) (((value) & 0x00000008) >> 3)
211 /* Produces a ALT_I2C_CON_IC_10BITADDR_SLV register field value suitable for setting the register. */
212 #define ALT_I2C_CON_IC_10BITADDR_SLV_SET(value) (((value) << 3) & 0x00000008)
213 
214 /*
215  * Field : Master Address Size - ic_10bitaddr_master
216  *
217  * This bit controls whether the I2C starts its transfers in 7-or 10-bit addressing
218  * mode when acting as a master.
219  *
220  * Field Enumeration Values:
221  *
222  * Enum | Value | Description
223  * :--------------------------------------------|:------|:------------------
224  * ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT | 0x0 | 7-bit addressing
225  * ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT | 0x1 | 10-bit addressing
226  *
227  * Field Access Macros:
228  *
229  */
230 /*
231  * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_MST
232  *
233  * 7-bit addressing
234  */
235 #define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT 0x0
236 /*
237  * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_MST
238  *
239  * 10-bit addressing
240  */
241 #define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT 0x1
242 
243 /* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_10BITADDR_MST register field. */
244 #define ALT_I2C_CON_IC_10BITADDR_MST_LSB 4
245 /* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_10BITADDR_MST register field. */
246 #define ALT_I2C_CON_IC_10BITADDR_MST_MSB 4
247 /* The width in bits of the ALT_I2C_CON_IC_10BITADDR_MST register field. */
248 #define ALT_I2C_CON_IC_10BITADDR_MST_WIDTH 1
249 /* The mask used to set the ALT_I2C_CON_IC_10BITADDR_MST register field value. */
250 #define ALT_I2C_CON_IC_10BITADDR_MST_SET_MSK 0x00000010
251 /* The mask used to clear the ALT_I2C_CON_IC_10BITADDR_MST register field value. */
252 #define ALT_I2C_CON_IC_10BITADDR_MST_CLR_MSK 0xffffffef
253 /* The reset value of the ALT_I2C_CON_IC_10BITADDR_MST register field. */
254 #define ALT_I2C_CON_IC_10BITADDR_MST_RESET 0x1
255 /* Extracts the ALT_I2C_CON_IC_10BITADDR_MST field value from a register. */
256 #define ALT_I2C_CON_IC_10BITADDR_MST_GET(value) (((value) & 0x00000010) >> 4)
257 /* Produces a ALT_I2C_CON_IC_10BITADDR_MST register field value suitable for setting the register. */
258 #define ALT_I2C_CON_IC_10BITADDR_MST_SET(value) (((value) << 4) & 0x00000010)
259 
260 /*
261  * Field : Restart Enable - ic_restart_en
262  *
263  * Determines whether RESTART conditions may be sent when acting as a master. Some
264  * older slaves do not support handling RESTART conditions; however, RESTART
265  * conditions are used in several I2C operations. When RESTART is disabled, the
266  * master is prohibited from performing the following functions
267  *
268  * * Changing direction within a transfer (split),
269  *
270  * * Sending a START BYTE,
271  *
272  * * High-speed mode operation,
273  *
274  * * Combined format transfers in 7-bit addressing modes,
275  *
276  * * Read operation with a 10-bit address,
277  *
278  * * Sending multiple bytes per transfer,
279  *
280  * By replacing RESTART condition followed by a STOP and a subsequent START
281  * condition, split operations are broken down into multiple I2C transfers. If the
282  * above operations are performed, it will result in setting bit [6](tx_abort) of
283  * the Raw Interrupt Status Register.
284  *
285  * Field Enumeration Values:
286  *
287  * Enum | Value | Description
288  * :--------------------------------|:------|:-----------------------
289  * ALT_I2C_CON_IC_RESTART_EN_E_DIS | 0x0 | restart master disable
290  * ALT_I2C_CON_IC_RESTART_EN_E_EN | 0x1 | restart master enable
291  *
292  * Field Access Macros:
293  *
294  */
295 /*
296  * Enumerated value for register field ALT_I2C_CON_IC_RESTART_EN
297  *
298  * restart master disable
299  */
300 #define ALT_I2C_CON_IC_RESTART_EN_E_DIS 0x0
301 /*
302  * Enumerated value for register field ALT_I2C_CON_IC_RESTART_EN
303  *
304  * restart master enable
305  */
306 #define ALT_I2C_CON_IC_RESTART_EN_E_EN 0x1
307 
308 /* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_RESTART_EN register field. */
309 #define ALT_I2C_CON_IC_RESTART_EN_LSB 5
310 /* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_RESTART_EN register field. */
311 #define ALT_I2C_CON_IC_RESTART_EN_MSB 5
312 /* The width in bits of the ALT_I2C_CON_IC_RESTART_EN register field. */
313 #define ALT_I2C_CON_IC_RESTART_EN_WIDTH 1
314 /* The mask used to set the ALT_I2C_CON_IC_RESTART_EN register field value. */
315 #define ALT_I2C_CON_IC_RESTART_EN_SET_MSK 0x00000020
316 /* The mask used to clear the ALT_I2C_CON_IC_RESTART_EN register field value. */
317 #define ALT_I2C_CON_IC_RESTART_EN_CLR_MSK 0xffffffdf
318 /* The reset value of the ALT_I2C_CON_IC_RESTART_EN register field. */
319 #define ALT_I2C_CON_IC_RESTART_EN_RESET 0x1
320 /* Extracts the ALT_I2C_CON_IC_RESTART_EN field value from a register. */
321 #define ALT_I2C_CON_IC_RESTART_EN_GET(value) (((value) & 0x00000020) >> 5)
322 /* Produces a ALT_I2C_CON_IC_RESTART_EN register field value suitable for setting the register. */
323 #define ALT_I2C_CON_IC_RESTART_EN_SET(value) (((value) << 5) & 0x00000020)
324 
325 /*
326  * Field : Slave Disable - ic_slave_disable
327  *
328  * This bit controls whether I2C has its slave disabled. The slave will be
329  * disabled, after reset.
330  *
331  * NOTE: Software should ensure that if this bit is written with 0, then bit [0] of
332  * this register should also be written with a 0.
333  *
334  * Field Enumeration Values:
335  *
336  * Enum | Value | Description
337  * :-----------------------------|:------|:--------------
338  * ALT_I2C_CON_IC_SLV_DIS_E_DIS | 0x1 | slave disable
339  * ALT_I2C_CON_IC_SLV_DIS_E_EN | 0x0 | slave enable
340  *
341  * Field Access Macros:
342  *
343  */
344 /*
345  * Enumerated value for register field ALT_I2C_CON_IC_SLV_DIS
346  *
347  * slave disable
348  */
349 #define ALT_I2C_CON_IC_SLV_DIS_E_DIS 0x1
350 /*
351  * Enumerated value for register field ALT_I2C_CON_IC_SLV_DIS
352  *
353  * slave enable
354  */
355 #define ALT_I2C_CON_IC_SLV_DIS_E_EN 0x0
356 
357 /* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_SLV_DIS register field. */
358 #define ALT_I2C_CON_IC_SLV_DIS_LSB 6
359 /* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_SLV_DIS register field. */
360 #define ALT_I2C_CON_IC_SLV_DIS_MSB 6
361 /* The width in bits of the ALT_I2C_CON_IC_SLV_DIS register field. */
362 #define ALT_I2C_CON_IC_SLV_DIS_WIDTH 1
363 /* The mask used to set the ALT_I2C_CON_IC_SLV_DIS register field value. */
364 #define ALT_I2C_CON_IC_SLV_DIS_SET_MSK 0x00000040
365 /* The mask used to clear the ALT_I2C_CON_IC_SLV_DIS register field value. */
366 #define ALT_I2C_CON_IC_SLV_DIS_CLR_MSK 0xffffffbf
367 /* The reset value of the ALT_I2C_CON_IC_SLV_DIS register field. */
368 #define ALT_I2C_CON_IC_SLV_DIS_RESET 0x1
369 /* Extracts the ALT_I2C_CON_IC_SLV_DIS field value from a register. */
370 #define ALT_I2C_CON_IC_SLV_DIS_GET(value) (((value) & 0x00000040) >> 6)
371 /* Produces a ALT_I2C_CON_IC_SLV_DIS register field value suitable for setting the register. */
372 #define ALT_I2C_CON_IC_SLV_DIS_SET(value) (((value) << 6) & 0x00000040)
373 
374 #ifndef __ASSEMBLY__
375 /*
376  * WARNING: The C register and register group struct declarations are provided for
377  * convenience and illustrative purposes. They should, however, be used with
378  * caution as the C language standard provides no guarantees about the alignment or
379  * atomicity of device memory accesses. The recommended practice for writing
380  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
381  * alt_write_word() functions.
382  *
383  * The struct declaration for register ALT_I2C_CON.
384  */
385 struct ALT_I2C_CON_s
386 {
387  uint32_t master_mode : 1; /* Master Enable */
388  uint32_t speed : 2; /* Master Speed Control */
389  uint32_t ic_10bitaddr_slave : 1; /* Slave Address Size */
390  uint32_t ic_10bitaddr_master : 1; /* Master Address Size */
391  uint32_t ic_restart_en : 1; /* Restart Enable */
392  uint32_t ic_slave_disable : 1; /* Slave Disable */
393  uint32_t : 25; /* *UNDEFINED* */
394 };
395 
396 /* The typedef declaration for register ALT_I2C_CON. */
397 typedef volatile struct ALT_I2C_CON_s ALT_I2C_CON_t;
398 #endif /* __ASSEMBLY__ */
399 
400 /* The byte offset of the ALT_I2C_CON register from the beginning of the component. */
401 #define ALT_I2C_CON_OFST 0x0
402 /* The address of the ALT_I2C_CON register. */
403 #define ALT_I2C_CON_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CON_OFST))
404 
405 /*
406  * Register : Target Address Register - ic_tar
407  *
408  * This register can be written to only when the ic_enable register is set to 0.
409  * This register is 13 bits wide. All bits can be dynamically updated as long as
410  * any set of the following conditions are true,
411  *
412  * (Enable Register bit 0 is set to 0) or (Enable Register bit 0 is set to 1 AND
413  * (I2C is NOT engaged in any Master [tx, rx] operation [ic_status register
414  * mst_activity bit 5 is set to 0]) AND (I2C is enabled to operate in Master
415  * mode[ic_con bit[0] is set to one]) AND (there are NO entries in the TX FIFO
416  * Register [IC_STATUS bit [2] is set to 1])
417  *
418  * Register Layout
419  *
420  * Bits | Access | Reset | Description
421  * :--------|:-------|:------|:------------------------------
422  * [9:0] | RW | 0x55 | Master Target Address
423  * [10] | RW | 0x0 | General Call OR Start
424  * [11] | RW | 0x0 | Special
425  * [12] | RW | 0x1 | Master Addressing Bit Control
426  * [31:13] | ??? | 0x0 | *UNDEFINED*
427  *
428  */
429 /*
430  * Field : Master Target Address - ic_tar
431  *
432  * This is the target address for any master transaction. When transmitting a
433  * General Call, these bits are ignored. To generate a START BYTE, the CPU needs to
434  * write only once into these bits. If the ic_tar and ic_sar are the same, loopback
435  * exists but the FIFOs are shared between master and slave, so full loopback is
436  * not feasible. Only one direction loopback mode is supported (simplex), not
437  * duplex. A master cannot transmit to itself; it can transmit to only a slave.
438  *
439  * Field Access Macros:
440  *
441  */
442 /* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_IC_TAR register field. */
443 #define ALT_I2C_TAR_IC_TAR_LSB 0
444 /* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_IC_TAR register field. */
445 #define ALT_I2C_TAR_IC_TAR_MSB 9
446 /* The width in bits of the ALT_I2C_TAR_IC_TAR register field. */
447 #define ALT_I2C_TAR_IC_TAR_WIDTH 10
448 /* The mask used to set the ALT_I2C_TAR_IC_TAR register field value. */
449 #define ALT_I2C_TAR_IC_TAR_SET_MSK 0x000003ff
450 /* The mask used to clear the ALT_I2C_TAR_IC_TAR register field value. */
451 #define ALT_I2C_TAR_IC_TAR_CLR_MSK 0xfffffc00
452 /* The reset value of the ALT_I2C_TAR_IC_TAR register field. */
453 #define ALT_I2C_TAR_IC_TAR_RESET 0x55
454 /* Extracts the ALT_I2C_TAR_IC_TAR field value from a register. */
455 #define ALT_I2C_TAR_IC_TAR_GET(value) (((value) & 0x000003ff) >> 0)
456 /* Produces a ALT_I2C_TAR_IC_TAR register field value suitable for setting the register. */
457 #define ALT_I2C_TAR_IC_TAR_SET(value) (((value) << 0) & 0x000003ff)
458 
459 /*
460  * Field : General Call OR Start - gc_or_start
461  *
462  * If bit 11 (SPECIAL) of this Register is set to 1, then this bit indicates
463  * whether a General Call or START byte command is to be performed by the I2C or
464  * General Call Address after issuing a General Call, only writes may be performed.
465  * Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the Raw
466  * Interrupt_Status register. The I2C remains in General Call mode until the
467  * special bit value (bit 11) is cleared.
468  *
469  * Field Enumeration Values:
470  *
471  * Enum | Value | Description
472  * :------------------------------------|:------|:-------------
473  * ALT_I2C_TAR_GC_OR_START_E_GENCALL | 0x0 | General Call
474  * ALT_I2C_TAR_GC_OR_START_E_STARTBYTE | 0x1 | START Byte
475  *
476  * Field Access Macros:
477  *
478  */
479 /*
480  * Enumerated value for register field ALT_I2C_TAR_GC_OR_START
481  *
482  * General Call
483  */
484 #define ALT_I2C_TAR_GC_OR_START_E_GENCALL 0x0
485 /*
486  * Enumerated value for register field ALT_I2C_TAR_GC_OR_START
487  *
488  * START Byte
489  */
490 #define ALT_I2C_TAR_GC_OR_START_E_STARTBYTE 0x1
491 
492 /* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_GC_OR_START register field. */
493 #define ALT_I2C_TAR_GC_OR_START_LSB 10
494 /* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_GC_OR_START register field. */
495 #define ALT_I2C_TAR_GC_OR_START_MSB 10
496 /* The width in bits of the ALT_I2C_TAR_GC_OR_START register field. */
497 #define ALT_I2C_TAR_GC_OR_START_WIDTH 1
498 /* The mask used to set the ALT_I2C_TAR_GC_OR_START register field value. */
499 #define ALT_I2C_TAR_GC_OR_START_SET_MSK 0x00000400
500 /* The mask used to clear the ALT_I2C_TAR_GC_OR_START register field value. */
501 #define ALT_I2C_TAR_GC_OR_START_CLR_MSK 0xfffffbff
502 /* The reset value of the ALT_I2C_TAR_GC_OR_START register field. */
503 #define ALT_I2C_TAR_GC_OR_START_RESET 0x0
504 /* Extracts the ALT_I2C_TAR_GC_OR_START field value from a register. */
505 #define ALT_I2C_TAR_GC_OR_START_GET(value) (((value) & 0x00000400) >> 10)
506 /* Produces a ALT_I2C_TAR_GC_OR_START register field value suitable for setting the register. */
507 #define ALT_I2C_TAR_GC_OR_START_SET(value) (((value) << 10) & 0x00000400)
508 
509 /*
510  * Field : Special - special
511  *
512  * This bit indicates whether software performs a General Call or START BYTE
513  * command.
514  *
515  * Field Enumeration Values:
516  *
517  * Enum | Value | Description
518  * :--------------------------------|:------|:--------------------------------------------
519  * ALT_I2C_TAR_SPECIAL_E_GENCALL | 0x0 | Ignore bit 10 gc_or_start and use ic_tar
520  * : | | normally
521  * ALT_I2C_TAR_SPECIAL_E_STARTBYTE | 0x1 | Perform special I2C command as specified in
522  * : | | gc_or_start
523  *
524  * Field Access Macros:
525  *
526  */
527 /*
528  * Enumerated value for register field ALT_I2C_TAR_SPECIAL
529  *
530  * Ignore bit 10 gc_or_start and use ic_tar normally
531  */
532 #define ALT_I2C_TAR_SPECIAL_E_GENCALL 0x0
533 /*
534  * Enumerated value for register field ALT_I2C_TAR_SPECIAL
535  *
536  * Perform special I2C command as specified in gc_or_start
537  */
538 #define ALT_I2C_TAR_SPECIAL_E_STARTBYTE 0x1
539 
540 /* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_SPECIAL register field. */
541 #define ALT_I2C_TAR_SPECIAL_LSB 11
542 /* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_SPECIAL register field. */
543 #define ALT_I2C_TAR_SPECIAL_MSB 11
544 /* The width in bits of the ALT_I2C_TAR_SPECIAL register field. */
545 #define ALT_I2C_TAR_SPECIAL_WIDTH 1
546 /* The mask used to set the ALT_I2C_TAR_SPECIAL register field value. */
547 #define ALT_I2C_TAR_SPECIAL_SET_MSK 0x00000800
548 /* The mask used to clear the ALT_I2C_TAR_SPECIAL register field value. */
549 #define ALT_I2C_TAR_SPECIAL_CLR_MSK 0xfffff7ff
550 /* The reset value of the ALT_I2C_TAR_SPECIAL register field. */
551 #define ALT_I2C_TAR_SPECIAL_RESET 0x0
552 /* Extracts the ALT_I2C_TAR_SPECIAL field value from a register. */
553 #define ALT_I2C_TAR_SPECIAL_GET(value) (((value) & 0x00000800) >> 11)
554 /* Produces a ALT_I2C_TAR_SPECIAL register field value suitable for setting the register. */
555 #define ALT_I2C_TAR_SPECIAL_SET(value) (((value) << 11) & 0x00000800)
556 
557 /*
558  * Field : Master Addressing Bit Control - ic_10bitaddr_master
559  *
560  * This bit controls whether the i2c starts its transfers in 7-bit or 10-bit
561  * addressing mode when acting as a master.
562  *
563  * Field Enumeration Values:
564  *
565  * Enum | Value | Description
566  * :---------------------------------------|:------|:----------------------
567  * ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 | 0x0 | Master Address, 7bit
568  * ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 | 0x1 | Master Address, 10bit
569  *
570  * Field Access Macros:
571  *
572  */
573 /*
574  * Enumerated value for register field ALT_I2C_TAR_IC_10BITADDR_MST
575  *
576  * Master Address, 7bit
577  */
578 #define ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 0x0
579 /*
580  * Enumerated value for register field ALT_I2C_TAR_IC_10BITADDR_MST
581  *
582  * Master Address, 10bit
583  */
584 #define ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 0x1
585 
586 /* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */
587 #define ALT_I2C_TAR_IC_10BITADDR_MST_LSB 12
588 /* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */
589 #define ALT_I2C_TAR_IC_10BITADDR_MST_MSB 12
590 /* The width in bits of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */
591 #define ALT_I2C_TAR_IC_10BITADDR_MST_WIDTH 1
592 /* The mask used to set the ALT_I2C_TAR_IC_10BITADDR_MST register field value. */
593 #define ALT_I2C_TAR_IC_10BITADDR_MST_SET_MSK 0x00001000
594 /* The mask used to clear the ALT_I2C_TAR_IC_10BITADDR_MST register field value. */
595 #define ALT_I2C_TAR_IC_10BITADDR_MST_CLR_MSK 0xffffefff
596 /* The reset value of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */
597 #define ALT_I2C_TAR_IC_10BITADDR_MST_RESET 0x1
598 /* Extracts the ALT_I2C_TAR_IC_10BITADDR_MST field value from a register. */
599 #define ALT_I2C_TAR_IC_10BITADDR_MST_GET(value) (((value) & 0x00001000) >> 12)
600 /* Produces a ALT_I2C_TAR_IC_10BITADDR_MST register field value suitable for setting the register. */
601 #define ALT_I2C_TAR_IC_10BITADDR_MST_SET(value) (((value) << 12) & 0x00001000)
602 
603 #ifndef __ASSEMBLY__
604 /*
605  * WARNING: The C register and register group struct declarations are provided for
606  * convenience and illustrative purposes. They should, however, be used with
607  * caution as the C language standard provides no guarantees about the alignment or
608  * atomicity of device memory accesses. The recommended practice for writing
609  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
610  * alt_write_word() functions.
611  *
612  * The struct declaration for register ALT_I2C_TAR.
613  */
614 struct ALT_I2C_TAR_s
615 {
616  uint32_t ic_tar : 10; /* Master Target Address */
617  uint32_t gc_or_start : 1; /* General Call OR Start */
618  uint32_t special : 1; /* Special */
619  uint32_t ic_10bitaddr_master : 1; /* Master Addressing Bit Control */
620  uint32_t : 19; /* *UNDEFINED* */
621 };
622 
623 /* The typedef declaration for register ALT_I2C_TAR. */
624 typedef volatile struct ALT_I2C_TAR_s ALT_I2C_TAR_t;
625 #endif /* __ASSEMBLY__ */
626 
627 /* The byte offset of the ALT_I2C_TAR register from the beginning of the component. */
628 #define ALT_I2C_TAR_OFST 0x4
629 /* The address of the ALT_I2C_TAR register. */
630 #define ALT_I2C_TAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TAR_OFST))
631 
632 /*
633  * Register : Slave Address Register - ic_sar
634  *
635  * Holds Address of Slave
636  *
637  * Register Layout
638  *
639  * Bits | Access | Reset | Description
640  * :--------|:-------|:------|:--------------
641  * [9:0] | RW | 0x55 | Slave Address
642  * [31:10] | ??? | 0x0 | *UNDEFINED*
643  *
644  */
645 /*
646  * Field : Slave Address - ic_sar
647  *
648  * The Slave Address register holds the slave address when the I2C is operating as
649  * a slave. For 7-bit addressing, only Field Bits [6:0] of the Slave Address
650  * Register are used. This register can be written only when the I2C interface is
651  * disabled, which corresponds to field bit 0 of the Enable Register being set to
652  * 0. Writes at other times have no effect.
653  *
654  * Note, the default values cannot be any of the reserved address locations: that
655  * is,
656  *
657  * 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not
658  * guaranteed if you program the Slave Address Register or Target Address Register
659  * to a reserved value.
660  *
661  * Field Access Macros:
662  *
663  */
664 /* The Least Significant Bit (LSB) position of the ALT_I2C_SAR_IC_SAR register field. */
665 #define ALT_I2C_SAR_IC_SAR_LSB 0
666 /* The Most Significant Bit (MSB) position of the ALT_I2C_SAR_IC_SAR register field. */
667 #define ALT_I2C_SAR_IC_SAR_MSB 9
668 /* The width in bits of the ALT_I2C_SAR_IC_SAR register field. */
669 #define ALT_I2C_SAR_IC_SAR_WIDTH 10
670 /* The mask used to set the ALT_I2C_SAR_IC_SAR register field value. */
671 #define ALT_I2C_SAR_IC_SAR_SET_MSK 0x000003ff
672 /* The mask used to clear the ALT_I2C_SAR_IC_SAR register field value. */
673 #define ALT_I2C_SAR_IC_SAR_CLR_MSK 0xfffffc00
674 /* The reset value of the ALT_I2C_SAR_IC_SAR register field. */
675 #define ALT_I2C_SAR_IC_SAR_RESET 0x55
676 /* Extracts the ALT_I2C_SAR_IC_SAR field value from a register. */
677 #define ALT_I2C_SAR_IC_SAR_GET(value) (((value) & 0x000003ff) >> 0)
678 /* Produces a ALT_I2C_SAR_IC_SAR register field value suitable for setting the register. */
679 #define ALT_I2C_SAR_IC_SAR_SET(value) (((value) << 0) & 0x000003ff)
680 
681 #ifndef __ASSEMBLY__
682 /*
683  * WARNING: The C register and register group struct declarations are provided for
684  * convenience and illustrative purposes. They should, however, be used with
685  * caution as the C language standard provides no guarantees about the alignment or
686  * atomicity of device memory accesses. The recommended practice for writing
687  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
688  * alt_write_word() functions.
689  *
690  * The struct declaration for register ALT_I2C_SAR.
691  */
692 struct ALT_I2C_SAR_s
693 {
694  uint32_t ic_sar : 10; /* Slave Address */
695  uint32_t : 22; /* *UNDEFINED* */
696 };
697 
698 /* The typedef declaration for register ALT_I2C_SAR. */
699 typedef volatile struct ALT_I2C_SAR_s ALT_I2C_SAR_t;
700 #endif /* __ASSEMBLY__ */
701 
702 /* The byte offset of the ALT_I2C_SAR register from the beginning of the component. */
703 #define ALT_I2C_SAR_OFST 0x8
704 /* The address of the ALT_I2C_SAR register. */
705 #define ALT_I2C_SAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SAR_OFST))
706 
707 /*
708  * Register : Tx Rx Data and Command Register - ic_data_cmd
709  *
710  * This is the register the CPU writes to when filling the TX FIFO. Reading from
711  * this register returns bytes from RX FIFO.
712  *
713  * Register Layout
714  *
715  * Bits | Access | Reset | Description
716  * :--------|:-------|:------|:--------------------------
717  * [7:0] | RW | 0x0 | Tx Rx Data
718  * [8] | W | 0x0 | Master Read Write Control
719  * [9] | W | 0x0 | Generate Stop
720  * [10] | W | 0x0 | Generate Restart
721  * [31:11] | ??? | 0x0 | *UNDEFINED*
722  *
723  */
724 /*
725  * Field : Tx Rx Data - dat
726  *
727  * This Field contains the data to be transmitted or received on the I2C bus. If
728  * you are writing to these bits and want to perform a read, bits 7:0 (dat) are
729  * ignored by the I2C. However, when you read from this register, these bits return
730  * the value of data received on the I2C interface.
731  *
732  * Field Access Macros:
733  *
734  */
735 /* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_DAT register field. */
736 #define ALT_I2C_DATA_CMD_DAT_LSB 0
737 /* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_DAT register field. */
738 #define ALT_I2C_DATA_CMD_DAT_MSB 7
739 /* The width in bits of the ALT_I2C_DATA_CMD_DAT register field. */
740 #define ALT_I2C_DATA_CMD_DAT_WIDTH 8
741 /* The mask used to set the ALT_I2C_DATA_CMD_DAT register field value. */
742 #define ALT_I2C_DATA_CMD_DAT_SET_MSK 0x000000ff
743 /* The mask used to clear the ALT_I2C_DATA_CMD_DAT register field value. */
744 #define ALT_I2C_DATA_CMD_DAT_CLR_MSK 0xffffff00
745 /* The reset value of the ALT_I2C_DATA_CMD_DAT register field. */
746 #define ALT_I2C_DATA_CMD_DAT_RESET 0x0
747 /* Extracts the ALT_I2C_DATA_CMD_DAT field value from a register. */
748 #define ALT_I2C_DATA_CMD_DAT_GET(value) (((value) & 0x000000ff) >> 0)
749 /* Produces a ALT_I2C_DATA_CMD_DAT register field value suitable for setting the register. */
750 #define ALT_I2C_DATA_CMD_DAT_SET(value) (((value) << 0) & 0x000000ff)
751 
752 /*
753  * Field : Master Read Write Control - cmd
754  *
755  * This bit controls whether a read or a write is performed. This bit does not
756  * control the direction when the I2C acts as a slave. It controls only the
757  * direction when it acts as a master. When a command is entered in the TX FIFO,
758  * this bit distinguishes the write and read commands. In slave-receiver mode, this
759  * bit is a 'don't care' because writes to this register are not required. In
760  * slave-transmitter mode, a '0' indicates that the CPU data is to be transmitted.
761  * When programming this bit, you should remember the following: attempting to
762  * perform a read operation after a General Call command has been sent results in a
763  * tx_abrt interrupt (bit 6 of the Raw Intr Status Register), unless bit 11 special
764  * in the Target Address Register has been cleared. If a '1' is written to this bit
765  * after receiving a RD_REQ interrupt, then a tx_abrt interrupt occurs.
766  *
767  * NOTE: It is possible that while attempting a master I2C read transfer on I2C, a
768  * RD_REQ interrupt may have occurred simultaneously due to a remote I2C master
769  * addressing I2C. In this type of scenario, I2C ignores the Data Cmd write,
770  * generates a tx_abrt interrupt, and waits to service the RD_REQ interrupt.
771  *
772  * Field Enumeration Values:
773  *
774  * Enum | Value | Description
775  * :--------------------------|:------|:-------------
776  * ALT_I2C_DATA_CMD_CMD_E_RD | 0x1 | Master Read
777  * ALT_I2C_DATA_CMD_CMD_E_WR | 0x0 | Master Write
778  *
779  * Field Access Macros:
780  *
781  */
782 /*
783  * Enumerated value for register field ALT_I2C_DATA_CMD_CMD
784  *
785  * Master Read
786  */
787 #define ALT_I2C_DATA_CMD_CMD_E_RD 0x1
788 /*
789  * Enumerated value for register field ALT_I2C_DATA_CMD_CMD
790  *
791  * Master Write
792  */
793 #define ALT_I2C_DATA_CMD_CMD_E_WR 0x0
794 
795 /* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_CMD register field. */
796 #define ALT_I2C_DATA_CMD_CMD_LSB 8
797 /* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_CMD register field. */
798 #define ALT_I2C_DATA_CMD_CMD_MSB 8
799 /* The width in bits of the ALT_I2C_DATA_CMD_CMD register field. */
800 #define ALT_I2C_DATA_CMD_CMD_WIDTH 1
801 /* The mask used to set the ALT_I2C_DATA_CMD_CMD register field value. */
802 #define ALT_I2C_DATA_CMD_CMD_SET_MSK 0x00000100
803 /* The mask used to clear the ALT_I2C_DATA_CMD_CMD register field value. */
804 #define ALT_I2C_DATA_CMD_CMD_CLR_MSK 0xfffffeff
805 /* The reset value of the ALT_I2C_DATA_CMD_CMD register field. */
806 #define ALT_I2C_DATA_CMD_CMD_RESET 0x0
807 /* Extracts the ALT_I2C_DATA_CMD_CMD field value from a register. */
808 #define ALT_I2C_DATA_CMD_CMD_GET(value) (((value) & 0x00000100) >> 8)
809 /* Produces a ALT_I2C_DATA_CMD_CMD register field value suitable for setting the register. */
810 #define ALT_I2C_DATA_CMD_CMD_SET(value) (((value) << 8) & 0x00000100)
811 
812 /*
813  * Field : Generate Stop - stop
814  *
815  * This bit controls whether a STOP is issued after the byte is sent or received.
816  *
817  * 1 = STOP is issued after this byte, regardless of whether or not the Tx FIFO is
818  * empty. If the Tx FIFO is not empty, the master immediately tries to start a new
819  * transfer by issuing a START and arbitrating for the bus.
820  *
821  * 0 = STOP is not issued after this byte, regardless of whether or not the Tx FIFO
822  * is empty. If the Tx FIFO is not empty, the master continues the current transfer
823  * by sending/receiving data bytes according to the value of the CMD bit. If the Tx
824  * FIFO is empty, the master holds the SCL line low and stalls the bus until a new
825  * command is available in the Tx FIFO.
826  *
827  * Field Enumeration Values:
828  *
829  * Enum | Value | Description
830  * :--------------------------------|:------|:------------------
831  * ALT_I2C_DATA_CMD_STOP_E_STOP | 0x1 | Issue Stop
832  * ALT_I2C_DATA_CMD_STOP_E_NO_STOP | 0x0 | Do Not Issue Stop
833  *
834  * Field Access Macros:
835  *
836  */
837 /*
838  * Enumerated value for register field ALT_I2C_DATA_CMD_STOP
839  *
840  * Issue Stop
841  */
842 #define ALT_I2C_DATA_CMD_STOP_E_STOP 0x1
843 /*
844  * Enumerated value for register field ALT_I2C_DATA_CMD_STOP
845  *
846  * Do Not Issue Stop
847  */
848 #define ALT_I2C_DATA_CMD_STOP_E_NO_STOP 0x0
849 
850 /* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_STOP register field. */
851 #define ALT_I2C_DATA_CMD_STOP_LSB 9
852 /* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_STOP register field. */
853 #define ALT_I2C_DATA_CMD_STOP_MSB 9
854 /* The width in bits of the ALT_I2C_DATA_CMD_STOP register field. */
855 #define ALT_I2C_DATA_CMD_STOP_WIDTH 1
856 /* The mask used to set the ALT_I2C_DATA_CMD_STOP register field value. */
857 #define ALT_I2C_DATA_CMD_STOP_SET_MSK 0x00000200
858 /* The mask used to clear the ALT_I2C_DATA_CMD_STOP register field value. */
859 #define ALT_I2C_DATA_CMD_STOP_CLR_MSK 0xfffffdff
860 /* The reset value of the ALT_I2C_DATA_CMD_STOP register field. */
861 #define ALT_I2C_DATA_CMD_STOP_RESET 0x0
862 /* Extracts the ALT_I2C_DATA_CMD_STOP field value from a register. */
863 #define ALT_I2C_DATA_CMD_STOP_GET(value) (((value) & 0x00000200) >> 9)
864 /* Produces a ALT_I2C_DATA_CMD_STOP register field value suitable for setting the register. */
865 #define ALT_I2C_DATA_CMD_STOP_SET(value) (((value) << 9) & 0x00000200)
866 
867 /*
868  * Field : Generate Restart - restart
869  *
870  * This bit controls whether a RESTART is issued before the byte is sent or
871  * received.
872  *
873  * 1 = A RESTART is issued before the data is sent/received (according to the value
874  * of CMD), regardless of whether or not the transfer direction is changing from
875  * the previous command.
876  *
877  * 0 = A RESTART is issued only if the transfer direction is changing from the
878  * previous command.
879  *
880  * Field Enumeration Values:
881  *
882  * Enum | Value | Description
883  * :-------------------------------------------------|:------|:----------------------------------
884  * ALT_I2C_DATA_CMD_RESTART_E_RESTART | 0x1 | Issue Restart
885  * ALT_I2C_DATA_CMD_RESTART_E_RESTART_ON_DIR_CHANGE | 0x0 | Issue Restart On Direction Change
886  *
887  * Field Access Macros:
888  *
889  */
890 /*
891  * Enumerated value for register field ALT_I2C_DATA_CMD_RESTART
892  *
893  * Issue Restart
894  */
895 #define ALT_I2C_DATA_CMD_RESTART_E_RESTART 0x1
896 /*
897  * Enumerated value for register field ALT_I2C_DATA_CMD_RESTART
898  *
899  * Issue Restart On Direction Change
900  */
901 #define ALT_I2C_DATA_CMD_RESTART_E_RESTART_ON_DIR_CHANGE 0x0
902 
903 /* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_RESTART register field. */
904 #define ALT_I2C_DATA_CMD_RESTART_LSB 10
905 /* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_RESTART register field. */
906 #define ALT_I2C_DATA_CMD_RESTART_MSB 10
907 /* The width in bits of the ALT_I2C_DATA_CMD_RESTART register field. */
908 #define ALT_I2C_DATA_CMD_RESTART_WIDTH 1
909 /* The mask used to set the ALT_I2C_DATA_CMD_RESTART register field value. */
910 #define ALT_I2C_DATA_CMD_RESTART_SET_MSK 0x00000400
911 /* The mask used to clear the ALT_I2C_DATA_CMD_RESTART register field value. */
912 #define ALT_I2C_DATA_CMD_RESTART_CLR_MSK 0xfffffbff
913 /* The reset value of the ALT_I2C_DATA_CMD_RESTART register field. */
914 #define ALT_I2C_DATA_CMD_RESTART_RESET 0x0
915 /* Extracts the ALT_I2C_DATA_CMD_RESTART field value from a register. */
916 #define ALT_I2C_DATA_CMD_RESTART_GET(value) (((value) & 0x00000400) >> 10)
917 /* Produces a ALT_I2C_DATA_CMD_RESTART register field value suitable for setting the register. */
918 #define ALT_I2C_DATA_CMD_RESTART_SET(value) (((value) << 10) & 0x00000400)
919 
920 #ifndef __ASSEMBLY__
921 /*
922  * WARNING: The C register and register group struct declarations are provided for
923  * convenience and illustrative purposes. They should, however, be used with
924  * caution as the C language standard provides no guarantees about the alignment or
925  * atomicity of device memory accesses. The recommended practice for writing
926  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
927  * alt_write_word() functions.
928  *
929  * The struct declaration for register ALT_I2C_DATA_CMD.
930  */
931 struct ALT_I2C_DATA_CMD_s
932 {
933  uint32_t dat : 8; /* Tx Rx Data */
934  uint32_t cmd : 1; /* Master Read Write Control */
935  uint32_t stop : 1; /* Generate Stop */
936  uint32_t restart : 1; /* Generate Restart */
937  uint32_t : 21; /* *UNDEFINED* */
938 };
939 
940 /* The typedef declaration for register ALT_I2C_DATA_CMD. */
941 typedef volatile struct ALT_I2C_DATA_CMD_s ALT_I2C_DATA_CMD_t;
942 #endif /* __ASSEMBLY__ */
943 
944 /* The byte offset of the ALT_I2C_DATA_CMD register from the beginning of the component. */
945 #define ALT_I2C_DATA_CMD_OFST 0x10
946 /* The address of the ALT_I2C_DATA_CMD register. */
947 #define ALT_I2C_DATA_CMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DATA_CMD_OFST))
948 
949 /*
950  * Register : Std Spd Clock SCL HCNT Register - ic_ss_scl_hcnt
951  *
952  * This register sets the SCL clock high-period count for standard speed.
953  *
954  * Register Layout
955  *
956  * Bits | Access | Reset | Description
957  * :--------|:-------|:------|:------------------------
958  * [15:0] | RW | 0x190 | Std Spd SCL High Period
959  * [31:16] | ??? | 0x0 | *UNDEFINED*
960  *
961  */
962 /*
963  * Field : Std Spd SCL High Period - ic_ss_scl_hcnt
964  *
965  * This register must be set before any I2C bus transaction can take place to
966  * ensure proper I/O timing. This field sets the SCL clock high-period count for
967  * standard speed. This register can be written only when the I2C interface is
968  * disabled which corresponds to the Enable Register being set to 0. Writes at
969  * other times have no effect. The minimum valid value is 6; hardware prevents
970  * values less than this being written, and if attempted results in 6 being set. It
971  * is readable and writeable.
972  *
973  * NOTE: This register must not be programmed to a value higher than 65525, because
974  * I2C uses a 16-bit counter to flag an I2C bus idle condition when this counter
975  * reaches a value of IC_SS_SCL_HCNT + 10.
976  *
977  * Field Access Macros:
978  *
979  */
980 /* The Least Significant Bit (LSB) position of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */
981 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB 0
982 /* The Most Significant Bit (MSB) position of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */
983 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB 15
984 /* The width in bits of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */
985 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_WIDTH 16
986 /* The mask used to set the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value. */
987 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET_MSK 0x0000ffff
988 /* The mask used to clear the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value. */
989 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_CLR_MSK 0xffff0000
990 /* The reset value of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */
991 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET 0x190
992 /* Extracts the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT field value from a register. */
993 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0)
994 /* Produces a ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value suitable for setting the register. */
995 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff)
996 
997 #ifndef __ASSEMBLY__
998 /*
999  * WARNING: The C register and register group struct declarations are provided for
1000  * convenience and illustrative purposes. They should, however, be used with
1001  * caution as the C language standard provides no guarantees about the alignment or
1002  * atomicity of device memory accesses. The recommended practice for writing
1003  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1004  * alt_write_word() functions.
1005  *
1006  * The struct declaration for register ALT_I2C_SS_SCL_HCNT.
1007  */
1008 struct ALT_I2C_SS_SCL_HCNT_s
1009 {
1010  uint32_t ic_ss_scl_hcnt : 16; /* Std Spd SCL High Period */
1011  uint32_t : 16; /* *UNDEFINED* */
1012 };
1013 
1014 /* The typedef declaration for register ALT_I2C_SS_SCL_HCNT. */
1015 typedef volatile struct ALT_I2C_SS_SCL_HCNT_s ALT_I2C_SS_SCL_HCNT_t;
1016 #endif /* __ASSEMBLY__ */
1017 
1018 /* The byte offset of the ALT_I2C_SS_SCL_HCNT register from the beginning of the component. */
1019 #define ALT_I2C_SS_SCL_HCNT_OFST 0x14
1020 /* The address of the ALT_I2C_SS_SCL_HCNT register. */
1021 #define ALT_I2C_SS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_HCNT_OFST))
1022 
1023 /*
1024  * Register : Std Spd Clock SCL LCNT Register - ic_ss_scl_lcnt
1025  *
1026  * This register sets the SCL clock low-period count for standard speed
1027  *
1028  * Register Layout
1029  *
1030  * Bits | Access | Reset | Description
1031  * :--------|:-------|:------|:-----------------------
1032  * [15:0] | RW | 0x1d6 | Std Spd SCL Low Period
1033  * [31:16] | ??? | 0x0 | *UNDEFINED*
1034  *
1035  */
1036 /*
1037  * Field : Std Spd SCL Low Period - ic_ss_scl_lcnt
1038  *
1039  * This register must be set before any I2C bus transaction can take place to
1040  * ensure proper I/O timing. This field sets the SCL clock low period count for
1041  * standard speed. This register can be written only when the I2C interface is
1042  * disabled which corresponds to the Enable Register register being set to 0.
1043  * Writes at other times have no effect. The minimum valid value is 8; hardware
1044  * prevents values less than this from being written, and if attempted, results in
1045  * 8 being set.
1046  *
1047  * Field Access Macros:
1048  *
1049  */
1050 /* The Least Significant Bit (LSB) position of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */
1051 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB 0
1052 /* The Most Significant Bit (MSB) position of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */
1053 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB 15
1054 /* The width in bits of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */
1055 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_WIDTH 16
1056 /* The mask used to set the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value. */
1057 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET_MSK 0x0000ffff
1058 /* The mask used to clear the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value. */
1059 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_CLR_MSK 0xffff0000
1060 /* The reset value of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */
1061 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET 0x1d6
1062 /* Extracts the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT field value from a register. */
1063 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0)
1064 /* Produces a ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value suitable for setting the register. */
1065 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff)
1066 
1067 #ifndef __ASSEMBLY__
1068 /*
1069  * WARNING: The C register and register group struct declarations are provided for
1070  * convenience and illustrative purposes. They should, however, be used with
1071  * caution as the C language standard provides no guarantees about the alignment or
1072  * atomicity of device memory accesses. The recommended practice for writing
1073  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1074  * alt_write_word() functions.
1075  *
1076  * The struct declaration for register ALT_I2C_SS_SCL_LCNT.
1077  */
1078 struct ALT_I2C_SS_SCL_LCNT_s
1079 {
1080  uint32_t ic_ss_scl_lcnt : 16; /* Std Spd SCL Low Period */
1081  uint32_t : 16; /* *UNDEFINED* */
1082 };
1083 
1084 /* The typedef declaration for register ALT_I2C_SS_SCL_LCNT. */
1085 typedef volatile struct ALT_I2C_SS_SCL_LCNT_s ALT_I2C_SS_SCL_LCNT_t;
1086 #endif /* __ASSEMBLY__ */
1087 
1088 /* The byte offset of the ALT_I2C_SS_SCL_LCNT register from the beginning of the component. */
1089 #define ALT_I2C_SS_SCL_LCNT_OFST 0x18
1090 /* The address of the ALT_I2C_SS_SCL_LCNT register. */
1091 #define ALT_I2C_SS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_LCNT_OFST))
1092 
1093 /*
1094  * Register : Fast Spd Clock SCL HCNT Register - ic_fs_scl_hcnt
1095  *
1096  * This register sets the SCL clock high-period count for fast speed
1097  *
1098  * Register Layout
1099  *
1100  * Bits | Access | Reset | Description
1101  * :--------|:-------|:------|:-------------------------
1102  * [15:0] | RW | 0x3c | Fast Spd SCL High Period
1103  * [31:16] | ??? | 0x0 | *UNDEFINED*
1104  *
1105  */
1106 /*
1107  * Field : Fast Spd SCL High Period - ic_fs_scl_hcnt
1108  *
1109  * This register must be set before any I2C bus transaction can take place to
1110  * ensure proper I/O timing. This register sets the SCL clock high-period count for
1111  * fast speed. It is used in high-speed mode to send the Master Code and START BYTE
1112  * or General CALL. This register goes away and becomes read-only returning 0s if
1113  * in Standard Speed Mode. This register can be written only when the I2C interface
1114  * is disabled, which corresponds to the Enable Register being set to 0. Writes at
1115  * other times have no effect. The minimum valid value is 6; hardware prevents
1116  * values less than this from being written, and if attempted results in 6 being
1117  * set.
1118  *
1119  * Field Access Macros:
1120  *
1121  */
1122 /* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */
1123 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB 0
1124 /* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */
1125 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB 15
1126 /* The width in bits of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */
1127 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_WIDTH 16
1128 /* The mask used to set the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value. */
1129 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET_MSK 0x0000ffff
1130 /* The mask used to clear the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value. */
1131 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_CLR_MSK 0xffff0000
1132 /* The reset value of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */
1133 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET 0x3c
1134 /* Extracts the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT field value from a register. */
1135 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0)
1136 /* Produces a ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value suitable for setting the register. */
1137 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff)
1138 
1139 #ifndef __ASSEMBLY__
1140 /*
1141  * WARNING: The C register and register group struct declarations are provided for
1142  * convenience and illustrative purposes. They should, however, be used with
1143  * caution as the C language standard provides no guarantees about the alignment or
1144  * atomicity of device memory accesses. The recommended practice for writing
1145  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1146  * alt_write_word() functions.
1147  *
1148  * The struct declaration for register ALT_I2C_FS_SCL_HCNT.
1149  */
1150 struct ALT_I2C_FS_SCL_HCNT_s
1151 {
1152  uint32_t ic_fs_scl_hcnt : 16; /* Fast Spd SCL High Period */
1153  uint32_t : 16; /* *UNDEFINED* */
1154 };
1155 
1156 /* The typedef declaration for register ALT_I2C_FS_SCL_HCNT. */
1157 typedef volatile struct ALT_I2C_FS_SCL_HCNT_s ALT_I2C_FS_SCL_HCNT_t;
1158 #endif /* __ASSEMBLY__ */
1159 
1160 /* The byte offset of the ALT_I2C_FS_SCL_HCNT register from the beginning of the component. */
1161 #define ALT_I2C_FS_SCL_HCNT_OFST 0x1c
1162 /* The address of the ALT_I2C_FS_SCL_HCNT register. */
1163 #define ALT_I2C_FS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_HCNT_OFST))
1164 
1165 /*
1166  * Register : Fast Spd Clock SCL LCNT Register - ic_fs_scl_lcnt
1167  *
1168  * This register sets the SCL clock low period count
1169  *
1170  * Register Layout
1171  *
1172  * Bits | Access | Reset | Description
1173  * :--------|:-------|:------|:------------------------
1174  * [15:0] | RW | 0x82 | Fast Spd SCL Low Period
1175  * [31:16] | ??? | 0x0 | *UNDEFINED*
1176  *
1177  */
1178 /*
1179  * Field : Fast Spd SCL Low Period - ic_fs_scl_lcnt
1180  *
1181  * This register must be set before any I2C bus transaction can take place to
1182  * ensure proper I/O timing. This field sets the SCL clock low period count for
1183  * fast speed. It is used in high-speed mode to send the Master Code and START BYTE
1184  * or General CALL. This register can be written only when the I2C interface is
1185  * disabled, which corresponds to the Enable Register being set to 0. Writes at
1186  * other times have no effect.The minimum valid value is 8; hardware prevents
1187  * values less than this being written, and if attempted results in 8 being set.
1188  *
1189  * Field Access Macros:
1190  *
1191  */
1192 /* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */
1193 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB 0
1194 /* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */
1195 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB 15
1196 /* The width in bits of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */
1197 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_WIDTH 16
1198 /* The mask used to set the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value. */
1199 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET_MSK 0x0000ffff
1200 /* The mask used to clear the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value. */
1201 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_CLR_MSK 0xffff0000
1202 /* The reset value of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */
1203 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET 0x82
1204 /* Extracts the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT field value from a register. */
1205 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0)
1206 /* Produces a ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value suitable for setting the register. */
1207 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff)
1208 
1209 #ifndef __ASSEMBLY__
1210 /*
1211  * WARNING: The C register and register group struct declarations are provided for
1212  * convenience and illustrative purposes. They should, however, be used with
1213  * caution as the C language standard provides no guarantees about the alignment or
1214  * atomicity of device memory accesses. The recommended practice for writing
1215  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1216  * alt_write_word() functions.
1217  *
1218  * The struct declaration for register ALT_I2C_FS_SCL_LCNT.
1219  */
1220 struct ALT_I2C_FS_SCL_LCNT_s
1221 {
1222  uint32_t ic_fs_scl_lcnt : 16; /* Fast Spd SCL Low Period */
1223  uint32_t : 16; /* *UNDEFINED* */
1224 };
1225 
1226 /* The typedef declaration for register ALT_I2C_FS_SCL_LCNT. */
1227 typedef volatile struct ALT_I2C_FS_SCL_LCNT_s ALT_I2C_FS_SCL_LCNT_t;
1228 #endif /* __ASSEMBLY__ */
1229 
1230 /* The byte offset of the ALT_I2C_FS_SCL_LCNT register from the beginning of the component. */
1231 #define ALT_I2C_FS_SCL_LCNT_OFST 0x20
1232 /* The address of the ALT_I2C_FS_SCL_LCNT register. */
1233 #define ALT_I2C_FS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_LCNT_OFST))
1234 
1235 /*
1236  * Register : Interrupt Status Register - ic_intr_stat
1237  *
1238  * Each bit in this register has a corresponding mask bit in the Interrupt Mask
1239  * Register. These bits are cleared by reading the matching Interrupt Clear
1240  * Register. The unmasked raw versions of these bits are available in the Raw
1241  * Interrupt Status Register.
1242  *
1243  * Register Layout
1244  *
1245  * Bits | Access | Reset | Description
1246  * :--------|:-------|:------|:-------------------------
1247  * [0] | R | 0x0 | Receiver Under
1248  * [1] | R | 0x0 | Receiver Over
1249  * [2] | R | 0x0 | Receive Full
1250  * [3] | R | 0x0 | Interrupt Transmit Over
1251  * [4] | R | 0x0 | Interrupt Transmit Empty
1252  * [5] | R | 0x0 | Interrupt Read Request
1253  * [6] | R | 0x0 | Interrupt TX Abort
1254  * [7] | R | 0x0 | Interrupt RX Done
1255  * [8] | R | 0x0 | Interrupt R_activity
1256  * [9] | R | 0x0 | Interrupt Stop Detect
1257  * [10] | R | 0x0 | Interrupt Start Detect
1258  * [11] | R | 0x0 | Interrupt General Call
1259  * [31:12] | ??? | 0x0 | *UNDEFINED*
1260  *
1261  */
1262 /*
1263  * Field : Receiver Under - r_rx_under
1264  *
1265  * Set if the processor attempts to read the receive buffer when it is empty by
1266  * reading from the Tx Rx Data and Command Register. If the module is disabled,
1267  * Enable Register is set to 0, this bit keeps its level until the master or slave
1268  * state machines go into idle, then this interrupt is cleared.
1269  *
1270  * Field Access Macros:
1271  *
1272  */
1273 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */
1274 #define ALT_I2C_INTR_STAT_R_RX_UNDER_LSB 0
1275 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */
1276 #define ALT_I2C_INTR_STAT_R_RX_UNDER_MSB 0
1277 /* The width in bits of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */
1278 #define ALT_I2C_INTR_STAT_R_RX_UNDER_WIDTH 1
1279 /* The mask used to set the ALT_I2C_INTR_STAT_R_RX_UNDER register field value. */
1280 #define ALT_I2C_INTR_STAT_R_RX_UNDER_SET_MSK 0x00000001
1281 /* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_UNDER register field value. */
1282 #define ALT_I2C_INTR_STAT_R_RX_UNDER_CLR_MSK 0xfffffffe
1283 /* The reset value of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */
1284 #define ALT_I2C_INTR_STAT_R_RX_UNDER_RESET 0x0
1285 /* Extracts the ALT_I2C_INTR_STAT_R_RX_UNDER field value from a register. */
1286 #define ALT_I2C_INTR_STAT_R_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
1287 /* Produces a ALT_I2C_INTR_STAT_R_RX_UNDER register field value suitable for setting the register. */
1288 #define ALT_I2C_INTR_STAT_R_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
1289 
1290 /*
1291  * Field : Receiver Over - r_rx_over
1292  *
1293  * Set if the receive buffer is completely filled to 64 and an additional byte is
1294  * received from an external I2C device. The I2C acknowledges this, but any data
1295  * bytes received after the FIFO is full are lost. If the module is disabled,
1296  * Enable Register bit[0] is set to 0 this bit keeps its level until the master or
1297  * slave state machines go into idle, then this interrupt is cleared.
1298  *
1299  * Field Access Macros:
1300  *
1301  */
1302 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */
1303 #define ALT_I2C_INTR_STAT_R_RX_OVER_LSB 1
1304 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */
1305 #define ALT_I2C_INTR_STAT_R_RX_OVER_MSB 1
1306 /* The width in bits of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */
1307 #define ALT_I2C_INTR_STAT_R_RX_OVER_WIDTH 1
1308 /* The mask used to set the ALT_I2C_INTR_STAT_R_RX_OVER register field value. */
1309 #define ALT_I2C_INTR_STAT_R_RX_OVER_SET_MSK 0x00000002
1310 /* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_OVER register field value. */
1311 #define ALT_I2C_INTR_STAT_R_RX_OVER_CLR_MSK 0xfffffffd
1312 /* The reset value of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */
1313 #define ALT_I2C_INTR_STAT_R_RX_OVER_RESET 0x0
1314 /* Extracts the ALT_I2C_INTR_STAT_R_RX_OVER field value from a register. */
1315 #define ALT_I2C_INTR_STAT_R_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
1316 /* Produces a ALT_I2C_INTR_STAT_R_RX_OVER register field value suitable for setting the register. */
1317 #define ALT_I2C_INTR_STAT_R_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
1318 
1319 /*
1320  * Field : Receive Full - r_rx_full
1321  *
1322  * Set when the receive buffer reaches or goes above the Receive FIFO Threshold
1323  * Value(rx_tl). It is automatically cleared by hardware when buffer level goes
1324  * below the threshold. If the module is disabled, Bit [0] of the Enable Register
1325  * set to 0, the RX FIFO is flushed and held in reset; therefore the RX FIFO is not
1326  * full. So this bit is cleared once the Enable Register Bit 0 is programmed with a
1327  * 0, regardless of the activity that continues.
1328  *
1329  * Field Access Macros:
1330  *
1331  */
1332 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */
1333 #define ALT_I2C_INTR_STAT_R_RX_FULL_LSB 2
1334 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */
1335 #define ALT_I2C_INTR_STAT_R_RX_FULL_MSB 2
1336 /* The width in bits of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */
1337 #define ALT_I2C_INTR_STAT_R_RX_FULL_WIDTH 1
1338 /* The mask used to set the ALT_I2C_INTR_STAT_R_RX_FULL register field value. */
1339 #define ALT_I2C_INTR_STAT_R_RX_FULL_SET_MSK 0x00000004
1340 /* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_FULL register field value. */
1341 #define ALT_I2C_INTR_STAT_R_RX_FULL_CLR_MSK 0xfffffffb
1342 /* The reset value of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */
1343 #define ALT_I2C_INTR_STAT_R_RX_FULL_RESET 0x0
1344 /* Extracts the ALT_I2C_INTR_STAT_R_RX_FULL field value from a register. */
1345 #define ALT_I2C_INTR_STAT_R_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
1346 /* Produces a ALT_I2C_INTR_STAT_R_RX_FULL register field value suitable for setting the register. */
1347 #define ALT_I2C_INTR_STAT_R_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
1348 
1349 /*
1350  * Field : Interrupt Transmit Over - r_tx_over
1351  *
1352  * Set during transmit if the transmit buffer is filled to 64 and the processor
1353  * attempts to issue another I2C command by writing to the Data and Command
1354  * Register. When the module is disabled, this bit keeps its level until the master
1355  * or slave state machines goes into idle, then interrupt is cleared.
1356  *
1357  * Field Access Macros:
1358  *
1359  */
1360 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */
1361 #define ALT_I2C_INTR_STAT_R_TX_OVER_LSB 3
1362 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */
1363 #define ALT_I2C_INTR_STAT_R_TX_OVER_MSB 3
1364 /* The width in bits of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */
1365 #define ALT_I2C_INTR_STAT_R_TX_OVER_WIDTH 1
1366 /* The mask used to set the ALT_I2C_INTR_STAT_R_TX_OVER register field value. */
1367 #define ALT_I2C_INTR_STAT_R_TX_OVER_SET_MSK 0x00000008
1368 /* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_OVER register field value. */
1369 #define ALT_I2C_INTR_STAT_R_TX_OVER_CLR_MSK 0xfffffff7
1370 /* The reset value of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */
1371 #define ALT_I2C_INTR_STAT_R_TX_OVER_RESET 0x0
1372 /* Extracts the ALT_I2C_INTR_STAT_R_TX_OVER field value from a register. */
1373 #define ALT_I2C_INTR_STAT_R_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
1374 /* Produces a ALT_I2C_INTR_STAT_R_TX_OVER register field value suitable for setting the register. */
1375 #define ALT_I2C_INTR_STAT_R_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
1376 
1377 /*
1378  * Field : Interrupt Transmit Empty - r_tx_empty
1379  *
1380  * This bit is set to 1 when the transmit buffer is at or below the threshold value
1381  * set in the ic_tx_tl register. It is automatically cleared by hardware when the
1382  * buffer level goes above the threshold. When the ic_enable bit 0 is 0, the TX
1383  * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data
1384  * within it, so this bit is set to 1, provided there is activity in the master or
1385  * slave state machines. When there is no longer activity, this bit is set to 0.
1386  *
1387  * Field Access Macros:
1388  *
1389  */
1390 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */
1391 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_LSB 4
1392 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */
1393 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_MSB 4
1394 /* The width in bits of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */
1395 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_WIDTH 1
1396 /* The mask used to set the ALT_I2C_INTR_STAT_R_TX_EMPTY register field value. */
1397 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET_MSK 0x00000010
1398 /* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_EMPTY register field value. */
1399 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_CLR_MSK 0xffffffef
1400 /* The reset value of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */
1401 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_RESET 0x0
1402 /* Extracts the ALT_I2C_INTR_STAT_R_TX_EMPTY field value from a register. */
1403 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
1404 /* Produces a ALT_I2C_INTR_STAT_R_TX_EMPTY register field value suitable for setting the register. */
1405 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
1406 
1407 /*
1408  * Field : Interrupt Read Request - r_rd_req
1409  *
1410  * This bit is set to 1 when i2c is acting as a slave and another I2C master is
1411  * attempting to read data from I2C. The I2C holds the I2C bus in a wait state
1412  * (SCL=0) until this interrupt is serviced, which means that the slave has been
1413  * addressed by a remote master that is asking for data to be transferred. The
1414  * processor must respond to this interrupt and then write the requested data to
1415  * the IC_DATA_CMD register. This bit is set to 0 just after the processor reads
1416  * the ic_clr_rd_req register.
1417  *
1418  * Field Access Macros:
1419  *
1420  */
1421 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */
1422 #define ALT_I2C_INTR_STAT_R_RD_REQ_LSB 5
1423 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */
1424 #define ALT_I2C_INTR_STAT_R_RD_REQ_MSB 5
1425 /* The width in bits of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */
1426 #define ALT_I2C_INTR_STAT_R_RD_REQ_WIDTH 1
1427 /* The mask used to set the ALT_I2C_INTR_STAT_R_RD_REQ register field value. */
1428 #define ALT_I2C_INTR_STAT_R_RD_REQ_SET_MSK 0x00000020
1429 /* The mask used to clear the ALT_I2C_INTR_STAT_R_RD_REQ register field value. */
1430 #define ALT_I2C_INTR_STAT_R_RD_REQ_CLR_MSK 0xffffffdf
1431 /* The reset value of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */
1432 #define ALT_I2C_INTR_STAT_R_RD_REQ_RESET 0x0
1433 /* Extracts the ALT_I2C_INTR_STAT_R_RD_REQ field value from a register. */
1434 #define ALT_I2C_INTR_STAT_R_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
1435 /* Produces a ALT_I2C_INTR_STAT_R_RD_REQ register field value suitable for setting the register. */
1436 #define ALT_I2C_INTR_STAT_R_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
1437 
1438 /*
1439  * Field : Interrupt TX Abort - r_tx_abrt
1440  *
1441  * This bit indicates if I2C, as an I2C transmitter, is unable to complete the
1442  * intended actions on the contents of the transmit FIFO. This situation can occur
1443  * both as an I2C master or an I2C slave, and is referred to as a 'transmit
1444  * abort'.When this bit is set to 1, the ic_tx_abrt_source register indicates the
1445  * reason why the transmit abort takes places.
1446  *
1447  * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The
1448  * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read.
1449  * Once this read is performed, the TX FIFO is then ready to accept more data bytes
1450  * from the APB interface.
1451  *
1452  * Field Access Macros:
1453  *
1454  */
1455 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */
1456 #define ALT_I2C_INTR_STAT_R_TX_ABRT_LSB 6
1457 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */
1458 #define ALT_I2C_INTR_STAT_R_TX_ABRT_MSB 6
1459 /* The width in bits of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */
1460 #define ALT_I2C_INTR_STAT_R_TX_ABRT_WIDTH 1
1461 /* The mask used to set the ALT_I2C_INTR_STAT_R_TX_ABRT register field value. */
1462 #define ALT_I2C_INTR_STAT_R_TX_ABRT_SET_MSK 0x00000040
1463 /* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_ABRT register field value. */
1464 #define ALT_I2C_INTR_STAT_R_TX_ABRT_CLR_MSK 0xffffffbf
1465 /* The reset value of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */
1466 #define ALT_I2C_INTR_STAT_R_TX_ABRT_RESET 0x0
1467 /* Extracts the ALT_I2C_INTR_STAT_R_TX_ABRT field value from a register. */
1468 #define ALT_I2C_INTR_STAT_R_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
1469 /* Produces a ALT_I2C_INTR_STAT_R_TX_ABRT register field value suitable for setting the register. */
1470 #define ALT_I2C_INTR_STAT_R_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
1471 
1472 /*
1473  * Field : Interrupt RX Done - r_rx_done
1474  *
1475  * When the I2C is acting as a slave-transmitter, this bit is set to 1, if the
1476  * master does not acknowledge a transmitted byte. This occurs on the last byte of
1477  * the transmission, indicating that the transmission is done.
1478  *
1479  * Field Access Macros:
1480  *
1481  */
1482 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */
1483 #define ALT_I2C_INTR_STAT_R_RX_DONE_LSB 7
1484 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */
1485 #define ALT_I2C_INTR_STAT_R_RX_DONE_MSB 7
1486 /* The width in bits of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */
1487 #define ALT_I2C_INTR_STAT_R_RX_DONE_WIDTH 1
1488 /* The mask used to set the ALT_I2C_INTR_STAT_R_RX_DONE register field value. */
1489 #define ALT_I2C_INTR_STAT_R_RX_DONE_SET_MSK 0x00000080
1490 /* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_DONE register field value. */
1491 #define ALT_I2C_INTR_STAT_R_RX_DONE_CLR_MSK 0xffffff7f
1492 /* The reset value of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */
1493 #define ALT_I2C_INTR_STAT_R_RX_DONE_RESET 0x0
1494 /* Extracts the ALT_I2C_INTR_STAT_R_RX_DONE field value from a register. */
1495 #define ALT_I2C_INTR_STAT_R_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
1496 /* Produces a ALT_I2C_INTR_STAT_R_RX_DONE register field value suitable for setting the register. */
1497 #define ALT_I2C_INTR_STAT_R_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
1498 
1499 /*
1500  * Field : Interrupt R_activity - r_activity
1501  *
1502  * This bit captures I2C activity and stays set until it is cleared. There are four
1503  * ways to clear it:
1504  *
1505  * * Disabling the I2C
1506  *
1507  * * Reading the ic_clr_activity register
1508  *
1509  * * Reading the ic_clr_intr register
1510  *
1511  * * I2C reset
1512  *
1513  * Once this bit is set, it stays set unless one of the four methods is used to
1514  * clear it. Even if the I2C module is idle, this bit remains set until cleared,
1515  * indicating that there was activity on the bus.
1516  *
1517  * Field Access Macros:
1518  *
1519  */
1520 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */
1521 #define ALT_I2C_INTR_STAT_R_ACTIVITY_LSB 8
1522 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */
1523 #define ALT_I2C_INTR_STAT_R_ACTIVITY_MSB 8
1524 /* The width in bits of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */
1525 #define ALT_I2C_INTR_STAT_R_ACTIVITY_WIDTH 1
1526 /* The mask used to set the ALT_I2C_INTR_STAT_R_ACTIVITY register field value. */
1527 #define ALT_I2C_INTR_STAT_R_ACTIVITY_SET_MSK 0x00000100
1528 /* The mask used to clear the ALT_I2C_INTR_STAT_R_ACTIVITY register field value. */
1529 #define ALT_I2C_INTR_STAT_R_ACTIVITY_CLR_MSK 0xfffffeff
1530 /* The reset value of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */
1531 #define ALT_I2C_INTR_STAT_R_ACTIVITY_RESET 0x0
1532 /* Extracts the ALT_I2C_INTR_STAT_R_ACTIVITY field value from a register. */
1533 #define ALT_I2C_INTR_STAT_R_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
1534 /* Produces a ALT_I2C_INTR_STAT_R_ACTIVITY register field value suitable for setting the register. */
1535 #define ALT_I2C_INTR_STAT_R_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
1536 
1537 /*
1538  * Field : Interrupt Stop Detect - r_stop_det
1539  *
1540  * Indicates whether a STOP condition has occurred on the I2C interface regardless
1541  * of whether I2C is operating in slave or master mode.
1542  *
1543  * Field Access Macros:
1544  *
1545  */
1546 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */
1547 #define ALT_I2C_INTR_STAT_R_STOP_DET_LSB 9
1548 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */
1549 #define ALT_I2C_INTR_STAT_R_STOP_DET_MSB 9
1550 /* The width in bits of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */
1551 #define ALT_I2C_INTR_STAT_R_STOP_DET_WIDTH 1
1552 /* The mask used to set the ALT_I2C_INTR_STAT_R_STOP_DET register field value. */
1553 #define ALT_I2C_INTR_STAT_R_STOP_DET_SET_MSK 0x00000200
1554 /* The mask used to clear the ALT_I2C_INTR_STAT_R_STOP_DET register field value. */
1555 #define ALT_I2C_INTR_STAT_R_STOP_DET_CLR_MSK 0xfffffdff
1556 /* The reset value of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */
1557 #define ALT_I2C_INTR_STAT_R_STOP_DET_RESET 0x0
1558 /* Extracts the ALT_I2C_INTR_STAT_R_STOP_DET field value from a register. */
1559 #define ALT_I2C_INTR_STAT_R_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
1560 /* Produces a ALT_I2C_INTR_STAT_R_STOP_DET register field value suitable for setting the register. */
1561 #define ALT_I2C_INTR_STAT_R_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
1562 
1563 /*
1564  * Field : Interrupt Start Detect - r_start_det
1565  *
1566  * Indicates whether a START or RESTART condition has occurred on the I2C interface
1567  * regardless of whether I2C is operating in slave or master mode.
1568  *
1569  * Field Access Macros:
1570  *
1571  */
1572 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_START_DET register field. */
1573 #define ALT_I2C_INTR_STAT_R_START_DET_LSB 10
1574 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_START_DET register field. */
1575 #define ALT_I2C_INTR_STAT_R_START_DET_MSB 10
1576 /* The width in bits of the ALT_I2C_INTR_STAT_R_START_DET register field. */
1577 #define ALT_I2C_INTR_STAT_R_START_DET_WIDTH 1
1578 /* The mask used to set the ALT_I2C_INTR_STAT_R_START_DET register field value. */
1579 #define ALT_I2C_INTR_STAT_R_START_DET_SET_MSK 0x00000400
1580 /* The mask used to clear the ALT_I2C_INTR_STAT_R_START_DET register field value. */
1581 #define ALT_I2C_INTR_STAT_R_START_DET_CLR_MSK 0xfffffbff
1582 /* The reset value of the ALT_I2C_INTR_STAT_R_START_DET register field. */
1583 #define ALT_I2C_INTR_STAT_R_START_DET_RESET 0x0
1584 /* Extracts the ALT_I2C_INTR_STAT_R_START_DET field value from a register. */
1585 #define ALT_I2C_INTR_STAT_R_START_DET_GET(value) (((value) & 0x00000400) >> 10)
1586 /* Produces a ALT_I2C_INTR_STAT_R_START_DET register field value suitable for setting the register. */
1587 #define ALT_I2C_INTR_STAT_R_START_DET_SET(value) (((value) << 10) & 0x00000400)
1588 
1589 /*
1590  * Field : Interrupt General Call - r_gen_call
1591  *
1592  * Set only when a General Call address is received and it is acknowledged. It
1593  * stays set until it is cleared either by disabling I2C or when the CPU reads bit
1594  * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx
1595  * buffer.
1596  *
1597  * Field Access Macros:
1598  *
1599  */
1600 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */
1601 #define ALT_I2C_INTR_STAT_R_GEN_CALL_LSB 11
1602 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */
1603 #define ALT_I2C_INTR_STAT_R_GEN_CALL_MSB 11
1604 /* The width in bits of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */
1605 #define ALT_I2C_INTR_STAT_R_GEN_CALL_WIDTH 1
1606 /* The mask used to set the ALT_I2C_INTR_STAT_R_GEN_CALL register field value. */
1607 #define ALT_I2C_INTR_STAT_R_GEN_CALL_SET_MSK 0x00000800
1608 /* The mask used to clear the ALT_I2C_INTR_STAT_R_GEN_CALL register field value. */
1609 #define ALT_I2C_INTR_STAT_R_GEN_CALL_CLR_MSK 0xfffff7ff
1610 /* The reset value of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */
1611 #define ALT_I2C_INTR_STAT_R_GEN_CALL_RESET 0x0
1612 /* Extracts the ALT_I2C_INTR_STAT_R_GEN_CALL field value from a register. */
1613 #define ALT_I2C_INTR_STAT_R_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
1614 /* Produces a ALT_I2C_INTR_STAT_R_GEN_CALL register field value suitable for setting the register. */
1615 #define ALT_I2C_INTR_STAT_R_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
1616 
1617 #ifndef __ASSEMBLY__
1618 /*
1619  * WARNING: The C register and register group struct declarations are provided for
1620  * convenience and illustrative purposes. They should, however, be used with
1621  * caution as the C language standard provides no guarantees about the alignment or
1622  * atomicity of device memory accesses. The recommended practice for writing
1623  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1624  * alt_write_word() functions.
1625  *
1626  * The struct declaration for register ALT_I2C_INTR_STAT.
1627  */
1628 struct ALT_I2C_INTR_STAT_s
1629 {
1630  const uint32_t r_rx_under : 1; /* Receiver Under */
1631  const uint32_t r_rx_over : 1; /* Receiver Over */
1632  const uint32_t r_rx_full : 1; /* Receive Full */
1633  const uint32_t r_tx_over : 1; /* Interrupt Transmit Over */
1634  const uint32_t r_tx_empty : 1; /* Interrupt Transmit Empty */
1635  const uint32_t r_rd_req : 1; /* Interrupt Read Request */
1636  const uint32_t r_tx_abrt : 1; /* Interrupt TX Abort */
1637  const uint32_t r_rx_done : 1; /* Interrupt RX Done */
1638  const uint32_t r_activity : 1; /* Interrupt R_activity */
1639  const uint32_t r_stop_det : 1; /* Interrupt Stop Detect */
1640  const uint32_t r_start_det : 1; /* Interrupt Start Detect */
1641  const uint32_t r_gen_call : 1; /* Interrupt General Call */
1642  uint32_t : 20; /* *UNDEFINED* */
1643 };
1644 
1645 /* The typedef declaration for register ALT_I2C_INTR_STAT. */
1646 typedef volatile struct ALT_I2C_INTR_STAT_s ALT_I2C_INTR_STAT_t;
1647 #endif /* __ASSEMBLY__ */
1648 
1649 /* The byte offset of the ALT_I2C_INTR_STAT register from the beginning of the component. */
1650 #define ALT_I2C_INTR_STAT_OFST 0x2c
1651 /* The address of the ALT_I2C_INTR_STAT register. */
1652 #define ALT_I2C_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_STAT_OFST))
1653 
1654 /*
1655  * Register : Interrupt Mask Register - ic_intr_mask
1656  *
1657  * These bits mask their corresponding interrupt status bits.
1658  *
1659  * Register Layout
1660  *
1661  * Bits | Access | Reset | Description
1662  * :--------|:-------|:------|:----------------
1663  * [0] | RW | 0x1 | Mask RX Under
1664  * [1] | RW | 0x1 | RX Buffer Over
1665  * [2] | RW | 0x1 | RX Buffer Full
1666  * [3] | RW | 0x1 | TX Buffer Over
1667  * [4] | RW | 0x1 | TX Buffer Empty
1668  * [5] | RW | 0x1 | Read Request
1669  * [6] | RW | 0x1 | TX Abort
1670  * [7] | RW | 0x1 | RX Done
1671  * [8] | RW | 0x0 | Activity Bit
1672  * [9] | RW | 0x0 | Stop Detect
1673  * [10] | RW | 0x0 | Start Detect
1674  * [11] | RW | 0x1 | General Call
1675  * [31:12] | ??? | 0x0 | *UNDEFINED*
1676  *
1677  */
1678 /*
1679  * Field : Mask RX Under - m_rx_under
1680  *
1681  * Set if the processor attempts to read the receive buffer when it is empty by
1682  * reading from the ic_data_cmd register. If the module is disabled ic_enable[0]=0,
1683  * this bit keeps its level until the master or slave state machines go into idle,
1684  * and then this interrupt is cleared.
1685  *
1686  * Field Access Macros:
1687  *
1688  */
1689 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */
1690 #define ALT_I2C_INTR_MSK_M_RX_UNDER_LSB 0
1691 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */
1692 #define ALT_I2C_INTR_MSK_M_RX_UNDER_MSB 0
1693 /* The width in bits of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */
1694 #define ALT_I2C_INTR_MSK_M_RX_UNDER_WIDTH 1
1695 /* The mask used to set the ALT_I2C_INTR_MSK_M_RX_UNDER register field value. */
1696 #define ALT_I2C_INTR_MSK_M_RX_UNDER_SET_MSK 0x00000001
1697 /* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_UNDER register field value. */
1698 #define ALT_I2C_INTR_MSK_M_RX_UNDER_CLR_MSK 0xfffffffe
1699 /* The reset value of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */
1700 #define ALT_I2C_INTR_MSK_M_RX_UNDER_RESET 0x1
1701 /* Extracts the ALT_I2C_INTR_MSK_M_RX_UNDER field value from a register. */
1702 #define ALT_I2C_INTR_MSK_M_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
1703 /* Produces a ALT_I2C_INTR_MSK_M_RX_UNDER register field value suitable for setting the register. */
1704 #define ALT_I2C_INTR_MSK_M_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
1705 
1706 /*
1707  * Field : RX Buffer Over - m_rx_over
1708  *
1709  * Set if the receive buffer is completely filled to 64 and an additional byte is
1710  * received from an external I2C device. The I2C acknowledges this, but any data
1711  * bytes received after the FIFO is full are lost. If the module is disabled
1712  * ic_enable[0]=0, this bit keeps its level until the master or slave state
1713  * machines go into idle, then this interrupt is cleared.
1714  *
1715  * Field Access Macros:
1716  *
1717  */
1718 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */
1719 #define ALT_I2C_INTR_MSK_M_RX_OVER_LSB 1
1720 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */
1721 #define ALT_I2C_INTR_MSK_M_RX_OVER_MSB 1
1722 /* The width in bits of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */
1723 #define ALT_I2C_INTR_MSK_M_RX_OVER_WIDTH 1
1724 /* The mask used to set the ALT_I2C_INTR_MSK_M_RX_OVER register field value. */
1725 #define ALT_I2C_INTR_MSK_M_RX_OVER_SET_MSK 0x00000002
1726 /* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_OVER register field value. */
1727 #define ALT_I2C_INTR_MSK_M_RX_OVER_CLR_MSK 0xfffffffd
1728 /* The reset value of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */
1729 #define ALT_I2C_INTR_MSK_M_RX_OVER_RESET 0x1
1730 /* Extracts the ALT_I2C_INTR_MSK_M_RX_OVER field value from a register. */
1731 #define ALT_I2C_INTR_MSK_M_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
1732 /* Produces a ALT_I2C_INTR_MSK_M_RX_OVER register field value suitable for setting the register. */
1733 #define ALT_I2C_INTR_MSK_M_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
1734 
1735 /*
1736  * Field : RX Buffer Full - m_rx_full
1737  *
1738  * Set when the receive buffer reaches or goes above the RX_TL threshold in the
1739  * ic_rx_tl register. It is automatically cleared by hardware when buffer level
1740  * goes below the threshold. If the module is disabled ic_enable[0]=0, the RX FIFO
1741  * is flushed and held in reset; therefore the RX FIFO is not full. So this bit is
1742  * cleared once the ic_enable bit 0 is programmed with a 0, regardless of the
1743  * activity that continues.
1744  *
1745  * Field Access Macros:
1746  *
1747  */
1748 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */
1749 #define ALT_I2C_INTR_MSK_M_RX_FULL_LSB 2
1750 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */
1751 #define ALT_I2C_INTR_MSK_M_RX_FULL_MSB 2
1752 /* The width in bits of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */
1753 #define ALT_I2C_INTR_MSK_M_RX_FULL_WIDTH 1
1754 /* The mask used to set the ALT_I2C_INTR_MSK_M_RX_FULL register field value. */
1755 #define ALT_I2C_INTR_MSK_M_RX_FULL_SET_MSK 0x00000004
1756 /* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_FULL register field value. */
1757 #define ALT_I2C_INTR_MSK_M_RX_FULL_CLR_MSK 0xfffffffb
1758 /* The reset value of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */
1759 #define ALT_I2C_INTR_MSK_M_RX_FULL_RESET 0x1
1760 /* Extracts the ALT_I2C_INTR_MSK_M_RX_FULL field value from a register. */
1761 #define ALT_I2C_INTR_MSK_M_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
1762 /* Produces a ALT_I2C_INTR_MSK_M_RX_FULL register field value suitable for setting the register. */
1763 #define ALT_I2C_INTR_MSK_M_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
1764 
1765 /*
1766  * Field : TX Buffer Over - m_tx_over
1767  *
1768  * Set during transmit if the transmit buffer is filled to 64 and the processor
1769  * attempts to issue another I2C command by writing to the ic_data_cmd register.
1770  * When the module is disabled, this bit keeps its level until the master or slave
1771  * state machines go into idle, then this interrupt is cleared.
1772  *
1773  * Field Access Macros:
1774  *
1775  */
1776 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */
1777 #define ALT_I2C_INTR_MSK_M_TX_OVER_LSB 3
1778 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */
1779 #define ALT_I2C_INTR_MSK_M_TX_OVER_MSB 3
1780 /* The width in bits of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */
1781 #define ALT_I2C_INTR_MSK_M_TX_OVER_WIDTH 1
1782 /* The mask used to set the ALT_I2C_INTR_MSK_M_TX_OVER register field value. */
1783 #define ALT_I2C_INTR_MSK_M_TX_OVER_SET_MSK 0x00000008
1784 /* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_OVER register field value. */
1785 #define ALT_I2C_INTR_MSK_M_TX_OVER_CLR_MSK 0xfffffff7
1786 /* The reset value of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */
1787 #define ALT_I2C_INTR_MSK_M_TX_OVER_RESET 0x1
1788 /* Extracts the ALT_I2C_INTR_MSK_M_TX_OVER field value from a register. */
1789 #define ALT_I2C_INTR_MSK_M_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
1790 /* Produces a ALT_I2C_INTR_MSK_M_TX_OVER register field value suitable for setting the register. */
1791 #define ALT_I2C_INTR_MSK_M_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
1792 
1793 /*
1794  * Field : TX Buffer Empty - m_tx_empty
1795  *
1796  * This bit is set to 1 when the transmit buffer is at or below the threshold value
1797  * set in the ic_tx_tl register. It is automatically cleared by hardware when the
1798  * buffer level goes above the threshold. When the ic_enable bit 0 is 0, the TX
1799  * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data
1800  * within it, so this bit is set to 1, provided there is activity in the master or
1801  * slave state machines. When there is no longer activity, then this bit is set to
1802  * 0.
1803  *
1804  * Field Access Macros:
1805  *
1806  */
1807 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */
1808 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_LSB 4
1809 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */
1810 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_MSB 4
1811 /* The width in bits of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */
1812 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_WIDTH 1
1813 /* The mask used to set the ALT_I2C_INTR_MSK_M_TX_EMPTY register field value. */
1814 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET_MSK 0x00000010
1815 /* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_EMPTY register field value. */
1816 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_CLR_MSK 0xffffffef
1817 /* The reset value of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */
1818 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_RESET 0x1
1819 /* Extracts the ALT_I2C_INTR_MSK_M_TX_EMPTY field value from a register. */
1820 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
1821 /* Produces a ALT_I2C_INTR_MSK_M_TX_EMPTY register field value suitable for setting the register. */
1822 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
1823 
1824 /*
1825  * Field : Read Request - m_rd_req
1826  *
1827  * This bit is set to 1 when I2C is acting as a slave and another I2C master is
1828  * attempting to read data from I2C. The I2C holds the I2C bus in a wait state
1829  * (SCL=0) until this interrupt is serviced, which means that the slave has been
1830  * addressed by a remote master that is asking for data to be transferred. The
1831  * processor must respond to this interrupt and then write the requested data to
1832  * the ic_data_cmd register. This bit is set to 0 just after the processor reads
1833  * the ic_clr_rd_req register.
1834  *
1835  * Field Access Macros:
1836  *
1837  */
1838 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */
1839 #define ALT_I2C_INTR_MSK_M_RD_REQ_LSB 5
1840 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */
1841 #define ALT_I2C_INTR_MSK_M_RD_REQ_MSB 5
1842 /* The width in bits of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */
1843 #define ALT_I2C_INTR_MSK_M_RD_REQ_WIDTH 1
1844 /* The mask used to set the ALT_I2C_INTR_MSK_M_RD_REQ register field value. */
1845 #define ALT_I2C_INTR_MSK_M_RD_REQ_SET_MSK 0x00000020
1846 /* The mask used to clear the ALT_I2C_INTR_MSK_M_RD_REQ register field value. */
1847 #define ALT_I2C_INTR_MSK_M_RD_REQ_CLR_MSK 0xffffffdf
1848 /* The reset value of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */
1849 #define ALT_I2C_INTR_MSK_M_RD_REQ_RESET 0x1
1850 /* Extracts the ALT_I2C_INTR_MSK_M_RD_REQ field value from a register. */
1851 #define ALT_I2C_INTR_MSK_M_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
1852 /* Produces a ALT_I2C_INTR_MSK_M_RD_REQ register field value suitable for setting the register. */
1853 #define ALT_I2C_INTR_MSK_M_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
1854 
1855 /*
1856  * Field : TX Abort - m_tx_abrt
1857  *
1858  * This bit indicates if I2C, as an I2C transmitter, is unable to complete the
1859  * intended actions on the contents of the transmit FIFO. This situation can occur
1860  * both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'.
1861  * When this bit is set to 1, the ic_tx_abrt_source register indicates the reason
1862  * why the transmit abort takes places.
1863  *
1864  * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The
1865  * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read.
1866  * Once this read is performed, the TX FIFO is then ready to accept more data bytes
1867  * from the APB interface.
1868  *
1869  * Field Access Macros:
1870  *
1871  */
1872 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */
1873 #define ALT_I2C_INTR_MSK_M_TX_ABRT_LSB 6
1874 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */
1875 #define ALT_I2C_INTR_MSK_M_TX_ABRT_MSB 6
1876 /* The width in bits of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */
1877 #define ALT_I2C_INTR_MSK_M_TX_ABRT_WIDTH 1
1878 /* The mask used to set the ALT_I2C_INTR_MSK_M_TX_ABRT register field value. */
1879 #define ALT_I2C_INTR_MSK_M_TX_ABRT_SET_MSK 0x00000040
1880 /* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_ABRT register field value. */
1881 #define ALT_I2C_INTR_MSK_M_TX_ABRT_CLR_MSK 0xffffffbf
1882 /* The reset value of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */
1883 #define ALT_I2C_INTR_MSK_M_TX_ABRT_RESET 0x1
1884 /* Extracts the ALT_I2C_INTR_MSK_M_TX_ABRT field value from a register. */
1885 #define ALT_I2C_INTR_MSK_M_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
1886 /* Produces a ALT_I2C_INTR_MSK_M_TX_ABRT register field value suitable for setting the register. */
1887 #define ALT_I2C_INTR_MSK_M_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
1888 
1889 /*
1890  * Field : RX Done - m_rx_done
1891  *
1892  * When the I2C is acting as a slave-transmitter, this bit is set to 1, if the
1893  * master does not acknowledge a transmitted byte. This occurs on the last byte of
1894  * the transmission, indicating that the transmission is done.
1895  *
1896  * Field Access Macros:
1897  *
1898  */
1899 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */
1900 #define ALT_I2C_INTR_MSK_M_RX_DONE_LSB 7
1901 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */
1902 #define ALT_I2C_INTR_MSK_M_RX_DONE_MSB 7
1903 /* The width in bits of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */
1904 #define ALT_I2C_INTR_MSK_M_RX_DONE_WIDTH 1
1905 /* The mask used to set the ALT_I2C_INTR_MSK_M_RX_DONE register field value. */
1906 #define ALT_I2C_INTR_MSK_M_RX_DONE_SET_MSK 0x00000080
1907 /* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_DONE register field value. */
1908 #define ALT_I2C_INTR_MSK_M_RX_DONE_CLR_MSK 0xffffff7f
1909 /* The reset value of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */
1910 #define ALT_I2C_INTR_MSK_M_RX_DONE_RESET 0x1
1911 /* Extracts the ALT_I2C_INTR_MSK_M_RX_DONE field value from a register. */
1912 #define ALT_I2C_INTR_MSK_M_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
1913 /* Produces a ALT_I2C_INTR_MSK_M_RX_DONE register field value suitable for setting the register. */
1914 #define ALT_I2C_INTR_MSK_M_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
1915 
1916 /*
1917  * Field : Activity Bit - m_activity
1918  *
1919  * This bit captures i2c activity and stays set until it is cleared. There are four
1920  * ways to clear it:
1921  *
1922  * * Disabling the i2c
1923  *
1924  * * Reading the ic_clr_activity register
1925  *
1926  * * Reading the ic_clr_intr register
1927  *
1928  * * System reset
1929  *
1930  * Once this bit is set, it stays set unless one of the four methods is used to
1931  * clear it. Even if the I2C module is idle, this bit remains set until cleared,
1932  * indicating that there was activity on the bus.
1933  *
1934  * Field Access Macros:
1935  *
1936  */
1937 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */
1938 #define ALT_I2C_INTR_MSK_M_ACTIVITY_LSB 8
1939 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */
1940 #define ALT_I2C_INTR_MSK_M_ACTIVITY_MSB 8
1941 /* The width in bits of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */
1942 #define ALT_I2C_INTR_MSK_M_ACTIVITY_WIDTH 1
1943 /* The mask used to set the ALT_I2C_INTR_MSK_M_ACTIVITY register field value. */
1944 #define ALT_I2C_INTR_MSK_M_ACTIVITY_SET_MSK 0x00000100
1945 /* The mask used to clear the ALT_I2C_INTR_MSK_M_ACTIVITY register field value. */
1946 #define ALT_I2C_INTR_MSK_M_ACTIVITY_CLR_MSK 0xfffffeff
1947 /* The reset value of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */
1948 #define ALT_I2C_INTR_MSK_M_ACTIVITY_RESET 0x0
1949 /* Extracts the ALT_I2C_INTR_MSK_M_ACTIVITY field value from a register. */
1950 #define ALT_I2C_INTR_MSK_M_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
1951 /* Produces a ALT_I2C_INTR_MSK_M_ACTIVITY register field value suitable for setting the register. */
1952 #define ALT_I2C_INTR_MSK_M_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
1953 
1954 /*
1955  * Field : Stop Detect - m_stop_det
1956  *
1957  * Indicates whether a STOP condition has occurred on the I2C interface regardless
1958  * of whether i2c is operating in slave or master mode.
1959  *
1960  * Field Access Macros:
1961  *
1962  */
1963 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */
1964 #define ALT_I2C_INTR_MSK_M_STOP_DET_LSB 9
1965 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */
1966 #define ALT_I2C_INTR_MSK_M_STOP_DET_MSB 9
1967 /* The width in bits of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */
1968 #define ALT_I2C_INTR_MSK_M_STOP_DET_WIDTH 1
1969 /* The mask used to set the ALT_I2C_INTR_MSK_M_STOP_DET register field value. */
1970 #define ALT_I2C_INTR_MSK_M_STOP_DET_SET_MSK 0x00000200
1971 /* The mask used to clear the ALT_I2C_INTR_MSK_M_STOP_DET register field value. */
1972 #define ALT_I2C_INTR_MSK_M_STOP_DET_CLR_MSK 0xfffffdff
1973 /* The reset value of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */
1974 #define ALT_I2C_INTR_MSK_M_STOP_DET_RESET 0x0
1975 /* Extracts the ALT_I2C_INTR_MSK_M_STOP_DET field value from a register. */
1976 #define ALT_I2C_INTR_MSK_M_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
1977 /* Produces a ALT_I2C_INTR_MSK_M_STOP_DET register field value suitable for setting the register. */
1978 #define ALT_I2C_INTR_MSK_M_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
1979 
1980 /*
1981  * Field : Start Detect - m_start_det
1982  *
1983  * Indicates whether a START or RESTART condition has occurred on the I2C interface
1984  * regardless of whether I2C is operating in slave or master mode.
1985  *
1986  * Field Access Macros:
1987  *
1988  */
1989 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_START_DET register field. */
1990 #define ALT_I2C_INTR_MSK_M_START_DET_LSB 10
1991 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_START_DET register field. */
1992 #define ALT_I2C_INTR_MSK_M_START_DET_MSB 10
1993 /* The width in bits of the ALT_I2C_INTR_MSK_M_START_DET register field. */
1994 #define ALT_I2C_INTR_MSK_M_START_DET_WIDTH 1
1995 /* The mask used to set the ALT_I2C_INTR_MSK_M_START_DET register field value. */
1996 #define ALT_I2C_INTR_MSK_M_START_DET_SET_MSK 0x00000400
1997 /* The mask used to clear the ALT_I2C_INTR_MSK_M_START_DET register field value. */
1998 #define ALT_I2C_INTR_MSK_M_START_DET_CLR_MSK 0xfffffbff
1999 /* The reset value of the ALT_I2C_INTR_MSK_M_START_DET register field. */
2000 #define ALT_I2C_INTR_MSK_M_START_DET_RESET 0x0
2001 /* Extracts the ALT_I2C_INTR_MSK_M_START_DET field value from a register. */
2002 #define ALT_I2C_INTR_MSK_M_START_DET_GET(value) (((value) & 0x00000400) >> 10)
2003 /* Produces a ALT_I2C_INTR_MSK_M_START_DET register field value suitable for setting the register. */
2004 #define ALT_I2C_INTR_MSK_M_START_DET_SET(value) (((value) << 10) & 0x00000400)
2005 
2006 /*
2007  * Field : General Call - m_gen_call
2008  *
2009  * Set only when a General Call address is received and it is acknowledged. It
2010  * stays set until it is cleared either by disabling I2C or when the CPU reads bit
2011  * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx
2012  * buffer.
2013  *
2014  * Field Access Macros:
2015  *
2016  */
2017 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */
2018 #define ALT_I2C_INTR_MSK_M_GEN_CALL_LSB 11
2019 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */
2020 #define ALT_I2C_INTR_MSK_M_GEN_CALL_MSB 11
2021 /* The width in bits of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */
2022 #define ALT_I2C_INTR_MSK_M_GEN_CALL_WIDTH 1
2023 /* The mask used to set the ALT_I2C_INTR_MSK_M_GEN_CALL register field value. */
2024 #define ALT_I2C_INTR_MSK_M_GEN_CALL_SET_MSK 0x00000800
2025 /* The mask used to clear the ALT_I2C_INTR_MSK_M_GEN_CALL register field value. */
2026 #define ALT_I2C_INTR_MSK_M_GEN_CALL_CLR_MSK 0xfffff7ff
2027 /* The reset value of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */
2028 #define ALT_I2C_INTR_MSK_M_GEN_CALL_RESET 0x1
2029 /* Extracts the ALT_I2C_INTR_MSK_M_GEN_CALL field value from a register. */
2030 #define ALT_I2C_INTR_MSK_M_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
2031 /* Produces a ALT_I2C_INTR_MSK_M_GEN_CALL register field value suitable for setting the register. */
2032 #define ALT_I2C_INTR_MSK_M_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
2033 
2034 #ifndef __ASSEMBLY__
2035 /*
2036  * WARNING: The C register and register group struct declarations are provided for
2037  * convenience and illustrative purposes. They should, however, be used with
2038  * caution as the C language standard provides no guarantees about the alignment or
2039  * atomicity of device memory accesses. The recommended practice for writing
2040  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2041  * alt_write_word() functions.
2042  *
2043  * The struct declaration for register ALT_I2C_INTR_MSK.
2044  */
2045 struct ALT_I2C_INTR_MSK_s
2046 {
2047  uint32_t m_rx_under : 1; /* Mask RX Under */
2048  uint32_t m_rx_over : 1; /* RX Buffer Over */
2049  uint32_t m_rx_full : 1; /* RX Buffer Full */
2050  uint32_t m_tx_over : 1; /* TX Buffer Over */
2051  uint32_t m_tx_empty : 1; /* TX Buffer Empty */
2052  uint32_t m_rd_req : 1; /* Read Request */
2053  uint32_t m_tx_abrt : 1; /* TX Abort */
2054  uint32_t m_rx_done : 1; /* RX Done */
2055  uint32_t m_activity : 1; /* Activity Bit */
2056  uint32_t m_stop_det : 1; /* Stop Detect */
2057  uint32_t m_start_det : 1; /* Start Detect */
2058  uint32_t m_gen_call : 1; /* General Call */
2059  uint32_t : 20; /* *UNDEFINED* */
2060 };
2061 
2062 /* The typedef declaration for register ALT_I2C_INTR_MSK. */
2063 typedef volatile struct ALT_I2C_INTR_MSK_s ALT_I2C_INTR_MSK_t;
2064 #endif /* __ASSEMBLY__ */
2065 
2066 /* The byte offset of the ALT_I2C_INTR_MSK register from the beginning of the component. */
2067 #define ALT_I2C_INTR_MSK_OFST 0x30
2068 /* The address of the ALT_I2C_INTR_MSK register. */
2069 #define ALT_I2C_INTR_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_MSK_OFST))
2070 
2071 /*
2072  * Register : Raw Interrupt Status Register - ic_raw_intr_stat
2073  *
2074  * Unlike the ic_intr_stat register, these bits are not masked so they always show
2075  * the true status of the I2C.
2076  *
2077  * Register Layout
2078  *
2079  * Bits | Access | Reset | Description
2080  * :--------|:-------|:------|:---------------------------
2081  * [0] | R | 0x0 | I2C Raw Interrupt RX Under
2082  * [1] | R | 0x0 | Raw Interrupt RX Over
2083  * [2] | R | 0x0 | Raw Interrupt RX Full
2084  * [3] | R | 0x0 | Raw Interrupt TX Over
2085  * [4] | R | 0x0 | Raw Interrupt TX Empty
2086  * [5] | R | 0x0 | Raw Interrupt Read Request
2087  * [6] | R | 0x0 | Raw Interrupt TX Abort
2088  * [7] | R | 0x0 | Raw Interrupt RX Done
2089  * [8] | R | 0x0 | Raw Interrupt Activity
2090  * [9] | R | 0x0 | Raw Interrupt Stop Detect
2091  * [10] | R | 0x0 | Raw Interrupt Start Detect
2092  * [11] | R | 0x0 | Raw Interrupt General Call
2093  * [31:12] | ??? | 0x0 | *UNDEFINED*
2094  *
2095  */
2096 /*
2097  * Field : I2C Raw Interrupt RX Under - rx_under
2098  *
2099  * Set if the processor attempts to read the receive buffer when it is empty by
2100  * reading from the ic_data_cmd register. If the module is disabled ic_enable[0]=0,
2101  * this bit keeps its level until the master or slave state machines go into idle,
2102  * then this interrupt is cleared.
2103  *
2104  * Field Access Macros:
2105  *
2106  */
2107 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */
2108 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_LSB 0
2109 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */
2110 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_MSB 0
2111 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */
2112 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_WIDTH 1
2113 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value. */
2114 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET_MSK 0x00000001
2115 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value. */
2116 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_CLR_MSK 0xfffffffe
2117 /* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */
2118 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_RESET 0x0
2119 /* Extracts the ALT_I2C_RAW_INTR_STAT_RX_UNDER field value from a register. */
2120 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
2121 /* Produces a ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value suitable for setting the register. */
2122 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
2123 
2124 /*
2125  * Field : Raw Interrupt RX Over - rx_over
2126  *
2127  * Set if the receive buffer is completely filled to 64 and an additional byte is
2128  * received from an external I2C device. The I2C acknowledges this, but any data
2129  * bytes received after the FIFO is full are lost. If the module is disabled
2130  * ic_enable[0]=0), this bit keeps its level until the master or slave state
2131  * machines go into then, this interrupt is cleared.
2132  *
2133  * Field Access Macros:
2134  *
2135  */
2136 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */
2137 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_LSB 1
2138 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */
2139 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_MSB 1
2140 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */
2141 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_WIDTH 1
2142 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_OVER register field value. */
2143 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET_MSK 0x00000002
2144 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_OVER register field value. */
2145 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_CLR_MSK 0xfffffffd
2146 /* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */
2147 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_RESET 0x0
2148 /* Extracts the ALT_I2C_RAW_INTR_STAT_RX_OVER field value from a register. */
2149 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
2150 /* Produces a ALT_I2C_RAW_INTR_STAT_RX_OVER register field value suitable for setting the register. */
2151 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
2152 
2153 /*
2154  * Field : Raw Interrupt RX Full - rx_full
2155  *
2156  * Set when the receive buffer reaches or goes above the RX_TL threshold in the
2157  * ic_rx_tl register. It is automatically cleared by hardware when buffer level
2158  * goes below the threshold. If the module is disabled ic_enable[0]=0, the RX FIFO
2159  * is flushed and held in reset; therefore the RX FIFO is not full. So this bit is
2160  * cleared once the ic_enable bit 0 is programmed with a 0, regardless of the
2161  * activity that continues.
2162  *
2163  * Field Access Macros:
2164  *
2165  */
2166 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */
2167 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_LSB 2
2168 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */
2169 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_MSB 2
2170 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */
2171 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_WIDTH 1
2172 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_FULL register field value. */
2173 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET_MSK 0x00000004
2174 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_FULL register field value. */
2175 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_CLR_MSK 0xfffffffb
2176 /* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */
2177 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_RESET 0x0
2178 /* Extracts the ALT_I2C_RAW_INTR_STAT_RX_FULL field value from a register. */
2179 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
2180 /* Produces a ALT_I2C_RAW_INTR_STAT_RX_FULL register field value suitable for setting the register. */
2181 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
2182 
2183 /*
2184  * Field : Raw Interrupt TX Over - tx_over
2185  *
2186  * Set during transmit if the transmit buffer is filled to 64 and the processor
2187  * attempts to issue another I2C command by writing to the ic_data_cmd register.
2188  * When the module is disabled, this bit keeps its level until the master or slave
2189  * state machines go into idle, then this interrupt is cleared.
2190  *
2191  * Field Access Macros:
2192  *
2193  */
2194 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */
2195 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_LSB 3
2196 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */
2197 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_MSB 3
2198 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */
2199 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_WIDTH 1
2200 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_OVER register field value. */
2201 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET_MSK 0x00000008
2202 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_OVER register field value. */
2203 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_CLR_MSK 0xfffffff7
2204 /* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */
2205 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_RESET 0x0
2206 /* Extracts the ALT_I2C_RAW_INTR_STAT_TX_OVER field value from a register. */
2207 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
2208 /* Produces a ALT_I2C_RAW_INTR_STAT_TX_OVER register field value suitable for setting the register. */
2209 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
2210 
2211 /*
2212  * Field : Raw Interrupt TX Empty - tx_empty
2213  *
2214  * This bit is set to 1 when the transmit buffer is at or below the threshold value
2215  * set in the ic_tx_tl register. It is automatically cleared by hardware when the
2216  * buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX
2217  * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data
2218  * within it, so this bit is set to 1, provided there is activity in the master or
2219  * slave state machines. When there is no longer activity, then this bit is set to
2220  * 0.
2221  *
2222  * Field Access Macros:
2223  *
2224  */
2225 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */
2226 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_LSB 4
2227 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */
2228 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_MSB 4
2229 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */
2230 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_WIDTH 1
2231 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value. */
2232 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET_MSK 0x00000010
2233 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value. */
2234 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_CLR_MSK 0xffffffef
2235 /* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */
2236 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_RESET 0x0
2237 /* Extracts the ALT_I2C_RAW_INTR_STAT_TX_EMPTY field value from a register. */
2238 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
2239 /* Produces a ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value suitable for setting the register. */
2240 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
2241 
2242 /*
2243  * Field : Raw Interrupt Read Request - rd_req
2244  *
2245  * This bit is set to 1 when I2C is acting as a slave and another I2C master is
2246  * attempting to read data from I2C. The i2c holds the I2C bus in a wait state
2247  * (SCL=0) until this interrupt is serviced, which means that the slave has been
2248  * addressed by a remote master that is asking for data to be transferred. The
2249  * processor must respond to this interrupt and then write the requested data to
2250  * the ic_data_cmd register. This bit is set to 0 just after the processor reads
2251  * the ic_clr_rd_req register.
2252  *
2253  * Field Access Macros:
2254  *
2255  */
2256 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */
2257 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_LSB 5
2258 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */
2259 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_MSB 5
2260 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */
2261 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_WIDTH 1
2262 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_RD_REQ register field value. */
2263 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET_MSK 0x00000020
2264 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RD_REQ register field value. */
2265 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_CLR_MSK 0xffffffdf
2266 /* The reset value of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */
2267 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_RESET 0x0
2268 /* Extracts the ALT_I2C_RAW_INTR_STAT_RD_REQ field value from a register. */
2269 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
2270 /* Produces a ALT_I2C_RAW_INTR_STAT_RD_REQ register field value suitable for setting the register. */
2271 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
2272 
2273 /*
2274  * Field : Raw Interrupt TX Abort - tx_abrt
2275  *
2276  * This bit indicates if I2C, as an I2C transmitter, is unable to complete the
2277  * intended actions on the contents of the transmit FIFO. This situation can occur
2278  * both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'.
2279  * When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason
2280  * why the transmit abort takes places.
2281  *
2282  * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The
2283  * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read.
2284  * Once this read is performed, the TX FIFO is then ready to accept more data bytes
2285  * from the APB interface.
2286  *
2287  * Field Access Macros:
2288  *
2289  */
2290 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */
2291 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_LSB 6
2292 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */
2293 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_MSB 6
2294 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */
2295 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_WIDTH 1
2296 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value. */
2297 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET_MSK 0x00000040
2298 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value. */
2299 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_CLR_MSK 0xffffffbf
2300 /* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */
2301 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_RESET 0x0
2302 /* Extracts the ALT_I2C_RAW_INTR_STAT_TX_ABRT field value from a register. */
2303 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
2304 /* Produces a ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value suitable for setting the register. */
2305 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
2306 
2307 /*
2308  * Field : Raw Interrupt RX Done - rx_done
2309  *
2310  * When the I2C is acting as a slave-transmitter, this bit is set to 1 if the
2311  * master does not acknowledge a transmitted byte. This occurs on the last byte of
2312  * the transmission, indicating that the transmission is done.
2313  *
2314  * Field Access Macros:
2315  *
2316  */
2317 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */
2318 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_LSB 7
2319 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */
2320 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_MSB 7
2321 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */
2322 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_WIDTH 1
2323 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_DONE register field value. */
2324 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET_MSK 0x00000080
2325 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_DONE register field value. */
2326 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_CLR_MSK 0xffffff7f
2327 /* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */
2328 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_RESET 0x0
2329 /* Extracts the ALT_I2C_RAW_INTR_STAT_RX_DONE field value from a register. */
2330 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
2331 /* Produces a ALT_I2C_RAW_INTR_STAT_RX_DONE register field value suitable for setting the register. */
2332 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
2333 
2334 /*
2335  * Field : Raw Interrupt Activity - activity
2336  *
2337  * This bit captures i2c activity and stays set until it is cleared. There are four
2338  * ways to clear it:
2339  *
2340  * * Disabling the I2C
2341  *
2342  * * Reading the ic_clr_activity register
2343  *
2344  * * Reading the ic_clr_intr register
2345  *
2346  * * System reset
2347  *
2348  * Once this bit is set, it stays set unless one of the four methods is used to
2349  * clear it. Even if the i2c module is idle, this bit remains set until cleared,
2350  * indicating that there was activity on the bus.
2351  *
2352  * Field Access Macros:
2353  *
2354  */
2355 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */
2356 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_LSB 8
2357 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */
2358 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_MSB 8
2359 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */
2360 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_WIDTH 1
2361 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value. */
2362 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET_MSK 0x00000100
2363 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value. */
2364 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_CLR_MSK 0xfffffeff
2365 /* The reset value of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */
2366 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_RESET 0x0
2367 /* Extracts the ALT_I2C_RAW_INTR_STAT_ACTIVITY field value from a register. */
2368 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
2369 /* Produces a ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value suitable for setting the register. */
2370 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
2371 
2372 /*
2373  * Field : Raw Interrupt Stop Detect - stop_det
2374  *
2375  * Indicates whether a STOP condition has occurred on the I2C interface regardless
2376  * of whether I2C is operating in slave or master mode.
2377  *
2378  * Field Access Macros:
2379  *
2380  */
2381 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */
2382 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_LSB 9
2383 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */
2384 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_MSB 9
2385 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */
2386 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_WIDTH 1
2387 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_STOP_DET register field value. */
2388 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET_MSK 0x00000200
2389 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_STOP_DET register field value. */
2390 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_CLR_MSK 0xfffffdff
2391 /* The reset value of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */
2392 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_RESET 0x0
2393 /* Extracts the ALT_I2C_RAW_INTR_STAT_STOP_DET field value from a register. */
2394 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
2395 /* Produces a ALT_I2C_RAW_INTR_STAT_STOP_DET register field value suitable for setting the register. */
2396 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
2397 
2398 /*
2399  * Field : Raw Interrupt Start Detect - start_det
2400  *
2401  * Indicates whether a START or RESTART condition has occurred on the I2C interface
2402  * regardless of whether I2C is operating in slave or master mode.
2403  *
2404  * Field Access Macros:
2405  *
2406  */
2407 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */
2408 #define ALT_I2C_RAW_INTR_STAT_START_DET_LSB 10
2409 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */
2410 #define ALT_I2C_RAW_INTR_STAT_START_DET_MSB 10
2411 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */
2412 #define ALT_I2C_RAW_INTR_STAT_START_DET_WIDTH 1
2413 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_START_DET register field value. */
2414 #define ALT_I2C_RAW_INTR_STAT_START_DET_SET_MSK 0x00000400
2415 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_START_DET register field value. */
2416 #define ALT_I2C_RAW_INTR_STAT_START_DET_CLR_MSK 0xfffffbff
2417 /* The reset value of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */
2418 #define ALT_I2C_RAW_INTR_STAT_START_DET_RESET 0x0
2419 /* Extracts the ALT_I2C_RAW_INTR_STAT_START_DET field value from a register. */
2420 #define ALT_I2C_RAW_INTR_STAT_START_DET_GET(value) (((value) & 0x00000400) >> 10)
2421 /* Produces a ALT_I2C_RAW_INTR_STAT_START_DET register field value suitable for setting the register. */
2422 #define ALT_I2C_RAW_INTR_STAT_START_DET_SET(value) (((value) << 10) & 0x00000400)
2423 
2424 /*
2425  * Field : Raw Interrupt General Call - gen_call
2426  *
2427  * Set only when a General Call address is received and it is acknowledged. It
2428  * stays set until it is cleared either by disabling I2C or when the CPU reads bit
2429  * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx
2430  * buffer.
2431  *
2432  * Field Access Macros:
2433  *
2434  */
2435 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */
2436 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_LSB 11
2437 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */
2438 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_MSB 11
2439 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */
2440 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_WIDTH 1
2441 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value. */
2442 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET_MSK 0x00000800
2443 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value. */
2444 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_CLR_MSK 0xfffff7ff
2445 /* The reset value of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */
2446 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_RESET 0x0
2447 /* Extracts the ALT_I2C_RAW_INTR_STAT_GEN_CALL field value from a register. */
2448 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
2449 /* Produces a ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value suitable for setting the register. */
2450 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
2451 
2452 #ifndef __ASSEMBLY__
2453 /*
2454  * WARNING: The C register and register group struct declarations are provided for
2455  * convenience and illustrative purposes. They should, however, be used with
2456  * caution as the C language standard provides no guarantees about the alignment or
2457  * atomicity of device memory accesses. The recommended practice for writing
2458  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2459  * alt_write_word() functions.
2460  *
2461  * The struct declaration for register ALT_I2C_RAW_INTR_STAT.
2462  */
2463 struct ALT_I2C_RAW_INTR_STAT_s
2464 {
2465  const uint32_t rx_under : 1; /* I2C Raw Interrupt RX Under */
2466  const uint32_t rx_over : 1; /* Raw Interrupt RX Over */
2467  const uint32_t rx_full : 1; /* Raw Interrupt RX Full */
2468  const uint32_t tx_over : 1; /* Raw Interrupt TX Over */
2469  const uint32_t tx_empty : 1; /* Raw Interrupt TX Empty */
2470  const uint32_t rd_req : 1; /* Raw Interrupt Read Request */
2471  const uint32_t tx_abrt : 1; /* Raw Interrupt TX Abort */
2472  const uint32_t rx_done : 1; /* Raw Interrupt RX Done */
2473  const uint32_t activity : 1; /* Raw Interrupt Activity */
2474  const uint32_t stop_det : 1; /* Raw Interrupt Stop Detect */
2475  const uint32_t start_det : 1; /* Raw Interrupt Start Detect */
2476  const uint32_t gen_call : 1; /* Raw Interrupt General Call */
2477  uint32_t : 20; /* *UNDEFINED* */
2478 };
2479 
2480 /* The typedef declaration for register ALT_I2C_RAW_INTR_STAT. */
2481 typedef volatile struct ALT_I2C_RAW_INTR_STAT_s ALT_I2C_RAW_INTR_STAT_t;
2482 #endif /* __ASSEMBLY__ */
2483 
2484 /* The byte offset of the ALT_I2C_RAW_INTR_STAT register from the beginning of the component. */
2485 #define ALT_I2C_RAW_INTR_STAT_OFST 0x34
2486 /* The address of the ALT_I2C_RAW_INTR_STAT register. */
2487 #define ALT_I2C_RAW_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RAW_INTR_STAT_OFST))
2488 
2489 /*
2490  * Register : Receive FIFO Threshold Register - ic_rx_tl
2491  *
2492  * I2C Receive FIFO Threshold Register.
2493  *
2494  * Register Layout
2495  *
2496  * Bits | Access | Reset | Description
2497  * :-------|:-------|:------|:-----------------------------
2498  * [7:0] | RW | 0x0 | Receive FIFO Threshold Level
2499  * [31:8] | ??? | 0x0 | *UNDEFINED*
2500  *
2501  */
2502 /*
2503  * Field : Receive FIFO Threshold Level - rx_tl
2504  *
2505  * Controls the level of entries (or above) that triggers the RX_FULL interrupt
2506  * (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the
2507  * additional restriction that hardware does not allow this value to be set to a
2508  * value larger than the depth of the buffer. If an attempt is made to do that, the
2509  * actual value set will be the maximum depth of the buffer. A value of 0 sets the
2510  * threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.
2511  *
2512  * Field Access Macros:
2513  *
2514  */
2515 /* The Least Significant Bit (LSB) position of the ALT_I2C_RX_TL_RX_TL register field. */
2516 #define ALT_I2C_RX_TL_RX_TL_LSB 0
2517 /* The Most Significant Bit (MSB) position of the ALT_I2C_RX_TL_RX_TL register field. */
2518 #define ALT_I2C_RX_TL_RX_TL_MSB 7
2519 /* The width in bits of the ALT_I2C_RX_TL_RX_TL register field. */
2520 #define ALT_I2C_RX_TL_RX_TL_WIDTH 8
2521 /* The mask used to set the ALT_I2C_RX_TL_RX_TL register field value. */
2522 #define ALT_I2C_RX_TL_RX_TL_SET_MSK 0x000000ff
2523 /* The mask used to clear the ALT_I2C_RX_TL_RX_TL register field value. */
2524 #define ALT_I2C_RX_TL_RX_TL_CLR_MSK 0xffffff00
2525 /* The reset value of the ALT_I2C_RX_TL_RX_TL register field. */
2526 #define ALT_I2C_RX_TL_RX_TL_RESET 0x0
2527 /* Extracts the ALT_I2C_RX_TL_RX_TL field value from a register. */
2528 #define ALT_I2C_RX_TL_RX_TL_GET(value) (((value) & 0x000000ff) >> 0)
2529 /* Produces a ALT_I2C_RX_TL_RX_TL register field value suitable for setting the register. */
2530 #define ALT_I2C_RX_TL_RX_TL_SET(value) (((value) << 0) & 0x000000ff)
2531 
2532 #ifndef __ASSEMBLY__
2533 /*
2534  * WARNING: The C register and register group struct declarations are provided for
2535  * convenience and illustrative purposes. They should, however, be used with
2536  * caution as the C language standard provides no guarantees about the alignment or
2537  * atomicity of device memory accesses. The recommended practice for writing
2538  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2539  * alt_write_word() functions.
2540  *
2541  * The struct declaration for register ALT_I2C_RX_TL.
2542  */
2543 struct ALT_I2C_RX_TL_s
2544 {
2545  uint32_t rx_tl : 8; /* Receive FIFO Threshold Level */
2546  uint32_t : 24; /* *UNDEFINED* */
2547 };
2548 
2549 /* The typedef declaration for register ALT_I2C_RX_TL. */
2550 typedef volatile struct ALT_I2C_RX_TL_s ALT_I2C_RX_TL_t;
2551 #endif /* __ASSEMBLY__ */
2552 
2553 /* The byte offset of the ALT_I2C_RX_TL register from the beginning of the component. */
2554 #define ALT_I2C_RX_TL_OFST 0x38
2555 /* The address of the ALT_I2C_RX_TL register. */
2556 #define ALT_I2C_RX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RX_TL_OFST))
2557 
2558 /*
2559  * Register : Transmit FIFO Threshold Level Register - ic_tx_tl
2560  *
2561  * Sets FIFO depth for Interrupt.
2562  *
2563  * Register Layout
2564  *
2565  * Bits | Access | Reset | Description
2566  * :-------|:-------|:------|:------------------------------
2567  * [7:0] | RW | 0x0 | Transmit FIFO Threshold Level
2568  * [31:8] | ??? | 0x0 | *UNDEFINED*
2569  *
2570  */
2571 /*
2572  * Field : Transmit FIFO Threshold Level - tx_tl
2573  *
2574  * Controls the level of entries (or below) that trigger the TX_EMPTY interrupt
2575  * (bit 4 in ic_raw_intr_stat register). The valid range is 0-255, with the
2576  * additional restriction that it may not be set to value larger than the depth of
2577  * the buffer. If an attempt is made to do that, the actual value set will be the
2578  * maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and
2579  * a value of 255 sets the threshold for 255 entries.
2580  *
2581  * Field Access Macros:
2582  *
2583  */
2584 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_TL_TX_TL register field. */
2585 #define ALT_I2C_TX_TL_TX_TL_LSB 0
2586 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_TL_TX_TL register field. */
2587 #define ALT_I2C_TX_TL_TX_TL_MSB 7
2588 /* The width in bits of the ALT_I2C_TX_TL_TX_TL register field. */
2589 #define ALT_I2C_TX_TL_TX_TL_WIDTH 8
2590 /* The mask used to set the ALT_I2C_TX_TL_TX_TL register field value. */
2591 #define ALT_I2C_TX_TL_TX_TL_SET_MSK 0x000000ff
2592 /* The mask used to clear the ALT_I2C_TX_TL_TX_TL register field value. */
2593 #define ALT_I2C_TX_TL_TX_TL_CLR_MSK 0xffffff00
2594 /* The reset value of the ALT_I2C_TX_TL_TX_TL register field. */
2595 #define ALT_I2C_TX_TL_TX_TL_RESET 0x0
2596 /* Extracts the ALT_I2C_TX_TL_TX_TL field value from a register. */
2597 #define ALT_I2C_TX_TL_TX_TL_GET(value) (((value) & 0x000000ff) >> 0)
2598 /* Produces a ALT_I2C_TX_TL_TX_TL register field value suitable for setting the register. */
2599 #define ALT_I2C_TX_TL_TX_TL_SET(value) (((value) << 0) & 0x000000ff)
2600 
2601 #ifndef __ASSEMBLY__
2602 /*
2603  * WARNING: The C register and register group struct declarations are provided for
2604  * convenience and illustrative purposes. They should, however, be used with
2605  * caution as the C language standard provides no guarantees about the alignment or
2606  * atomicity of device memory accesses. The recommended practice for writing
2607  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2608  * alt_write_word() functions.
2609  *
2610  * The struct declaration for register ALT_I2C_TX_TL.
2611  */
2612 struct ALT_I2C_TX_TL_s
2613 {
2614  uint32_t tx_tl : 8; /* Transmit FIFO Threshold Level */
2615  uint32_t : 24; /* *UNDEFINED* */
2616 };
2617 
2618 /* The typedef declaration for register ALT_I2C_TX_TL. */
2619 typedef volatile struct ALT_I2C_TX_TL_s ALT_I2C_TX_TL_t;
2620 #endif /* __ASSEMBLY__ */
2621 
2622 /* The byte offset of the ALT_I2C_TX_TL register from the beginning of the component. */
2623 #define ALT_I2C_TX_TL_OFST 0x3c
2624 /* The address of the ALT_I2C_TX_TL register. */
2625 #define ALT_I2C_TX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_TL_OFST))
2626 
2627 /*
2628  * Register : Combined and Individual Interrupt Register - ic_clr_intr
2629  *
2630  * Controls Interrupts
2631  *
2632  * Register Layout
2633  *
2634  * Bits | Access | Reset | Description
2635  * :-------|:-------|:------|:---------------------------------------
2636  * [0] | R | 0x0 | Combined and Individual Interrupt Bits
2637  * [31:1] | ??? | 0x0 | *UNDEFINED*
2638  *
2639  */
2640 /*
2641  * Field : Combined and Individual Interrupt Bits - clr_intr
2642  *
2643  * Read this register to clear the combined interrupt, all individual interrupts,
2644  * and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable
2645  * interrupts but software clearable interrupts. Refer to Bit 9 of the
2646  * ic_tx_abrt_source register for an exception to clearing ic_tx_abrt_source.
2647  *
2648  * Field Access Macros:
2649  *
2650  */
2651 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_INTR_CLR_INTR register field. */
2652 #define ALT_I2C_CLR_INTR_CLR_INTR_LSB 0
2653 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_INTR_CLR_INTR register field. */
2654 #define ALT_I2C_CLR_INTR_CLR_INTR_MSB 0
2655 /* The width in bits of the ALT_I2C_CLR_INTR_CLR_INTR register field. */
2656 #define ALT_I2C_CLR_INTR_CLR_INTR_WIDTH 1
2657 /* The mask used to set the ALT_I2C_CLR_INTR_CLR_INTR register field value. */
2658 #define ALT_I2C_CLR_INTR_CLR_INTR_SET_MSK 0x00000001
2659 /* The mask used to clear the ALT_I2C_CLR_INTR_CLR_INTR register field value. */
2660 #define ALT_I2C_CLR_INTR_CLR_INTR_CLR_MSK 0xfffffffe
2661 /* The reset value of the ALT_I2C_CLR_INTR_CLR_INTR register field. */
2662 #define ALT_I2C_CLR_INTR_CLR_INTR_RESET 0x0
2663 /* Extracts the ALT_I2C_CLR_INTR_CLR_INTR field value from a register. */
2664 #define ALT_I2C_CLR_INTR_CLR_INTR_GET(value) (((value) & 0x00000001) >> 0)
2665 /* Produces a ALT_I2C_CLR_INTR_CLR_INTR register field value suitable for setting the register. */
2666 #define ALT_I2C_CLR_INTR_CLR_INTR_SET(value) (((value) << 0) & 0x00000001)
2667 
2668 #ifndef __ASSEMBLY__
2669 /*
2670  * WARNING: The C register and register group struct declarations are provided for
2671  * convenience and illustrative purposes. They should, however, be used with
2672  * caution as the C language standard provides no guarantees about the alignment or
2673  * atomicity of device memory accesses. The recommended practice for writing
2674  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2675  * alt_write_word() functions.
2676  *
2677  * The struct declaration for register ALT_I2C_CLR_INTR.
2678  */
2679 struct ALT_I2C_CLR_INTR_s
2680 {
2681  const uint32_t clr_intr : 1; /* Combined and Individual Interrupt Bits */
2682  uint32_t : 31; /* *UNDEFINED* */
2683 };
2684 
2685 /* The typedef declaration for register ALT_I2C_CLR_INTR. */
2686 typedef volatile struct ALT_I2C_CLR_INTR_s ALT_I2C_CLR_INTR_t;
2687 #endif /* __ASSEMBLY__ */
2688 
2689 /* The byte offset of the ALT_I2C_CLR_INTR register from the beginning of the component. */
2690 #define ALT_I2C_CLR_INTR_OFST 0x40
2691 /* The address of the ALT_I2C_CLR_INTR register. */
2692 #define ALT_I2C_CLR_INTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_INTR_OFST))
2693 
2694 /*
2695  * Register : Rx Under Interrupt Register - ic_clr_rx_under
2696  *
2697  * Rx Under Interrupt Bits.
2698  *
2699  * Register Layout
2700  *
2701  * Bits | Access | Reset | Description
2702  * :-------|:-------|:------|:-----------------------------
2703  * [0] | R | 0x0 | Clear Rx Under Interrupt Bit
2704  * [31:1] | ??? | 0x0 | *UNDEFINED*
2705  *
2706  */
2707 /*
2708  * Field : Clear Rx Under Interrupt Bit - clr_rx_under
2709  *
2710  * Read this register to clear the RX_UNDER interrupt bit 0 of the ic_raw_intr_stat
2711  * register.
2712  *
2713  * Field Access Macros:
2714  *
2715  */
2716 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */
2717 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_LSB 0
2718 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */
2719 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_MSB 0
2720 /* The width in bits of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */
2721 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_WIDTH 1
2722 /* The mask used to set the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value. */
2723 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET_MSK 0x00000001
2724 /* The mask used to clear the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value. */
2725 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_CLR_MSK 0xfffffffe
2726 /* The reset value of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */
2727 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_RESET 0x0
2728 /* Extracts the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER field value from a register. */
2729 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
2730 /* Produces a ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value suitable for setting the register. */
2731 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
2732 
2733 #ifndef __ASSEMBLY__
2734 /*
2735  * WARNING: The C register and register group struct declarations are provided for
2736  * convenience and illustrative purposes. They should, however, be used with
2737  * caution as the C language standard provides no guarantees about the alignment or
2738  * atomicity of device memory accesses. The recommended practice for writing
2739  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2740  * alt_write_word() functions.
2741  *
2742  * The struct declaration for register ALT_I2C_CLR_RX_UNDER.
2743  */
2744 struct ALT_I2C_CLR_RX_UNDER_s
2745 {
2746  const uint32_t clr_rx_under : 1; /* Clear Rx Under Interrupt Bit */
2747  uint32_t : 31; /* *UNDEFINED* */
2748 };
2749 
2750 /* The typedef declaration for register ALT_I2C_CLR_RX_UNDER. */
2751 typedef volatile struct ALT_I2C_CLR_RX_UNDER_s ALT_I2C_CLR_RX_UNDER_t;
2752 #endif /* __ASSEMBLY__ */
2753 
2754 /* The byte offset of the ALT_I2C_CLR_RX_UNDER register from the beginning of the component. */
2755 #define ALT_I2C_CLR_RX_UNDER_OFST 0x44
2756 /* The address of the ALT_I2C_CLR_RX_UNDER register. */
2757 #define ALT_I2C_CLR_RX_UNDER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_UNDER_OFST))
2758 
2759 /*
2760  * Register : RX Over Interrupt Register - ic_clr_rx_over
2761  *
2762  * Clears Rx over Interrupt Bit
2763  *
2764  * Register Layout
2765  *
2766  * Bits | Access | Reset | Description
2767  * :-------|:-------|:------|:----------------------
2768  * [0] | R | 0x0 | RX Over Interrupt Bit
2769  * [31:1] | ??? | 0x0 | *UNDEFINED*
2770  *
2771  */
2772 /*
2773  * Field : RX Over Interrupt Bit - clr_rx_over
2774  *
2775  * Read this register to clear the RX_OVER interrupt bit 1 of the ic_raw_intr_stat
2776  * register.
2777  *
2778  * Field Access Macros:
2779  *
2780  */
2781 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */
2782 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_LSB 0
2783 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */
2784 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_MSB 0
2785 /* The width in bits of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */
2786 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_WIDTH 1
2787 /* The mask used to set the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value. */
2788 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET_MSK 0x00000001
2789 /* The mask used to clear the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value. */
2790 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_CLR_MSK 0xfffffffe
2791 /* The reset value of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */
2792 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_RESET 0x0
2793 /* Extracts the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER field value from a register. */
2794 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_GET(value) (((value) & 0x00000001) >> 0)
2795 /* Produces a ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value suitable for setting the register. */
2796 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET(value) (((value) << 0) & 0x00000001)
2797 
2798 #ifndef __ASSEMBLY__
2799 /*
2800  * WARNING: The C register and register group struct declarations are provided for
2801  * convenience and illustrative purposes. They should, however, be used with
2802  * caution as the C language standard provides no guarantees about the alignment or
2803  * atomicity of device memory accesses. The recommended practice for writing
2804  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2805  * alt_write_word() functions.
2806  *
2807  * The struct declaration for register ALT_I2C_CLR_RX_OVER.
2808  */
2809 struct ALT_I2C_CLR_RX_OVER_s
2810 {
2811  const uint32_t clr_rx_over : 1; /* RX Over Interrupt Bit */
2812  uint32_t : 31; /* *UNDEFINED* */
2813 };
2814 
2815 /* The typedef declaration for register ALT_I2C_CLR_RX_OVER. */
2816 typedef volatile struct ALT_I2C_CLR_RX_OVER_s ALT_I2C_CLR_RX_OVER_t;
2817 #endif /* __ASSEMBLY__ */
2818 
2819 /* The byte offset of the ALT_I2C_CLR_RX_OVER register from the beginning of the component. */
2820 #define ALT_I2C_CLR_RX_OVER_OFST 0x48
2821 /* The address of the ALT_I2C_CLR_RX_OVER register. */
2822 #define ALT_I2C_CLR_RX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_OVER_OFST))
2823 
2824 /*
2825  * Register : TX Over Interrupt Register - ic_clr_tx_over
2826  *
2827  * Clears Over Interrupts
2828  *
2829  * Register Layout
2830  *
2831  * Bits | Access | Reset | Description
2832  * :-------|:-------|:------|:----------------------
2833  * [0] | R | 0x0 | TX Over Interrupt Bit
2834  * [31:1] | ??? | 0x0 | *UNDEFINED*
2835  *
2836  */
2837 /*
2838  * Field : TX Over Interrupt Bit - clr_tx_over
2839  *
2840  * Read this register to clear the TX_OVER interrupt (bit 3) of the
2841  * ic_raw_intr_stat register.
2842  *
2843  * Field Access Macros:
2844  *
2845  */
2846 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */
2847 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_LSB 0
2848 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */
2849 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_MSB 0
2850 /* The width in bits of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */
2851 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_WIDTH 1
2852 /* The mask used to set the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value. */
2853 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET_MSK 0x00000001
2854 /* The mask used to clear the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value. */
2855 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_CLR_MSK 0xfffffffe
2856 /* The reset value of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */
2857 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_RESET 0x0
2858 /* Extracts the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER field value from a register. */
2859 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_GET(value) (((value) & 0x00000001) >> 0)
2860 /* Produces a ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value suitable for setting the register. */
2861 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET(value) (((value) << 0) & 0x00000001)
2862 
2863 #ifndef __ASSEMBLY__
2864 /*
2865  * WARNING: The C register and register group struct declarations are provided for
2866  * convenience and illustrative purposes. They should, however, be used with
2867  * caution as the C language standard provides no guarantees about the alignment or
2868  * atomicity of device memory accesses. The recommended practice for writing
2869  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2870  * alt_write_word() functions.
2871  *
2872  * The struct declaration for register ALT_I2C_CLR_TX_OVER.
2873  */
2874 struct ALT_I2C_CLR_TX_OVER_s
2875 {
2876  const uint32_t clr_tx_over : 1; /* TX Over Interrupt Bit */
2877  uint32_t : 31; /* *UNDEFINED* */
2878 };
2879 
2880 /* The typedef declaration for register ALT_I2C_CLR_TX_OVER. */
2881 typedef volatile struct ALT_I2C_CLR_TX_OVER_s ALT_I2C_CLR_TX_OVER_t;
2882 #endif /* __ASSEMBLY__ */
2883 
2884 /* The byte offset of the ALT_I2C_CLR_TX_OVER register from the beginning of the component. */
2885 #define ALT_I2C_CLR_TX_OVER_OFST 0x4c
2886 /* The address of the ALT_I2C_CLR_TX_OVER register. */
2887 #define ALT_I2C_CLR_TX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_OVER_OFST))
2888 
2889 /*
2890  * Register : Interrupt Read Request Register - ic_clr_rd_req
2891  *
2892  * Clear RD_REQ Interrupt Register
2893  *
2894  * Register Layout
2895  *
2896  * Bits | Access | Reset | Description
2897  * :-------|:-------|:------|:------------------------------------
2898  * [0] | R | 0x0 | Interrupt Register Read Request Bit
2899  * [31:1] | ??? | 0x0 | *UNDEFINED*
2900  *
2901  */
2902 /*
2903  * Field : Interrupt Register Read Request Bit - clr_rd_req
2904  *
2905  * Read this register to clear the RD_REQ interrupt (bit 5) of the ic_raw_intr_stat
2906  * register.
2907  *
2908  * Field Access Macros:
2909  *
2910  */
2911 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */
2912 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_LSB 0
2913 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */
2914 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_MSB 0
2915 /* The width in bits of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */
2916 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_WIDTH 1
2917 /* The mask used to set the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value. */
2918 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET_MSK 0x00000001
2919 /* The mask used to clear the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value. */
2920 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_CLR_MSK 0xfffffffe
2921 /* The reset value of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */
2922 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_RESET 0x0
2923 /* Extracts the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ field value from a register. */
2924 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_GET(value) (((value) & 0x00000001) >> 0)
2925 /* Produces a ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value suitable for setting the register. */
2926 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET(value) (((value) << 0) & 0x00000001)
2927 
2928 #ifndef __ASSEMBLY__
2929 /*
2930  * WARNING: The C register and register group struct declarations are provided for
2931  * convenience and illustrative purposes. They should, however, be used with
2932  * caution as the C language standard provides no guarantees about the alignment or
2933  * atomicity of device memory accesses. The recommended practice for writing
2934  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2935  * alt_write_word() functions.
2936  *
2937  * The struct declaration for register ALT_I2C_CLR_RD_REQ.
2938  */
2939 struct ALT_I2C_CLR_RD_REQ_s
2940 {
2941  const uint32_t clr_rd_req : 1; /* Interrupt Register Read Request Bit */
2942  uint32_t : 31; /* *UNDEFINED* */
2943 };
2944 
2945 /* The typedef declaration for register ALT_I2C_CLR_RD_REQ. */
2946 typedef volatile struct ALT_I2C_CLR_RD_REQ_s ALT_I2C_CLR_RD_REQ_t;
2947 #endif /* __ASSEMBLY__ */
2948 
2949 /* The byte offset of the ALT_I2C_CLR_RD_REQ register from the beginning of the component. */
2950 #define ALT_I2C_CLR_RD_REQ_OFST 0x50
2951 /* The address of the ALT_I2C_CLR_RD_REQ register. */
2952 #define ALT_I2C_CLR_RD_REQ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RD_REQ_OFST))
2953 
2954 /*
2955  * Register : Tx Abort Interrupt Register - ic_clr_tx_abrt
2956  *
2957  * Clear TX_ABRT Interrupt
2958  *
2959  * Register Layout
2960  *
2961  * Bits | Access | Reset | Description
2962  * :-------|:-------|:------|:-----------------------
2963  * [0] | R | 0x0 | Tx Abort Interrupt Bit
2964  * [31:1] | ??? | 0x0 | *UNDEFINED*
2965  *
2966  */
2967 /*
2968  * Field : Tx Abort Interrupt Bit - clr_tx_abort
2969  *
2970  * Read this register to clear the TX_ABRT interrupt (bit 6) of the
2971  * ic_raw_intr_stat register, and the ic_tx_abrt_source register. This also
2972  * releases the TX FIFO from the flushed/reset state, allowing more writes to the
2973  * TX FIFO. Refer to Bit 9 of the ic_tx_abrt_source register for an exception to
2974  * clearing ic_tx_abrt_source.
2975  *
2976  * Field Access Macros:
2977  *
2978  */
2979 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */
2980 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_LSB 0
2981 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */
2982 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_MSB 0
2983 /* The width in bits of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */
2984 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_WIDTH 1
2985 /* The mask used to set the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value. */
2986 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET_MSK 0x00000001
2987 /* The mask used to clear the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value. */
2988 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_CLR_MSK 0xfffffffe
2989 /* The reset value of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */
2990 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_RESET 0x0
2991 /* Extracts the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT field value from a register. */
2992 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_GET(value) (((value) & 0x00000001) >> 0)
2993 /* Produces a ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value suitable for setting the register. */
2994 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET(value) (((value) << 0) & 0x00000001)
2995 
2996 #ifndef __ASSEMBLY__
2997 /*
2998  * WARNING: The C register and register group struct declarations are provided for
2999  * convenience and illustrative purposes. They should, however, be used with
3000  * caution as the C language standard provides no guarantees about the alignment or
3001  * atomicity of device memory accesses. The recommended practice for writing
3002  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3003  * alt_write_word() functions.
3004  *
3005  * The struct declaration for register ALT_I2C_CLR_TX_ABRT.
3006  */
3007 struct ALT_I2C_CLR_TX_ABRT_s
3008 {
3009  const uint32_t clr_tx_abort : 1; /* Tx Abort Interrupt Bit */
3010  uint32_t : 31; /* *UNDEFINED* */
3011 };
3012 
3013 /* The typedef declaration for register ALT_I2C_CLR_TX_ABRT. */
3014 typedef volatile struct ALT_I2C_CLR_TX_ABRT_s ALT_I2C_CLR_TX_ABRT_t;
3015 #endif /* __ASSEMBLY__ */
3016 
3017 /* The byte offset of the ALT_I2C_CLR_TX_ABRT register from the beginning of the component. */
3018 #define ALT_I2C_CLR_TX_ABRT_OFST 0x54
3019 /* The address of the ALT_I2C_CLR_TX_ABRT register. */
3020 #define ALT_I2C_CLR_TX_ABRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_ABRT_OFST))
3021 
3022 /*
3023  * Register : Rx Done Interrupt Register - ic_clr_rx_done
3024  *
3025  * Clear RX_DONE Interrupt Register
3026  *
3027  * Register Layout
3028  *
3029  * Bits | Access | Reset | Description
3030  * :-------|:-------|:------|:----------------------
3031  * [0] | R | 0x0 | RX_DONE Interrupt Bit
3032  * [31:1] | ??? | 0x0 | *UNDEFINED*
3033  *
3034  */
3035 /*
3036  * Field : RX_DONE Interrupt Bit - clr_rx_done
3037  *
3038  * Read this register to clear the RX_DONE interrupt (bit 7) of the
3039  * ic_raw_intr_stat register.
3040  *
3041  * Field Access Macros:
3042  *
3043  */
3044 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */
3045 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_LSB 0
3046 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */
3047 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_MSB 0
3048 /* The width in bits of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */
3049 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_WIDTH 1
3050 /* The mask used to set the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value. */
3051 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET_MSK 0x00000001
3052 /* The mask used to clear the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value. */
3053 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_CLR_MSK 0xfffffffe
3054 /* The reset value of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */
3055 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_RESET 0x0
3056 /* Extracts the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE field value from a register. */
3057 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_GET(value) (((value) & 0x00000001) >> 0)
3058 /* Produces a ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value suitable for setting the register. */
3059 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET(value) (((value) << 0) & 0x00000001)
3060 
3061 #ifndef __ASSEMBLY__
3062 /*
3063  * WARNING: The C register and register group struct declarations are provided for
3064  * convenience and illustrative purposes. They should, however, be used with
3065  * caution as the C language standard provides no guarantees about the alignment or
3066  * atomicity of device memory accesses. The recommended practice for writing
3067  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3068  * alt_write_word() functions.
3069  *
3070  * The struct declaration for register ALT_I2C_CLR_RX_DONE.
3071  */
3072 struct ALT_I2C_CLR_RX_DONE_s
3073 {
3074  const uint32_t clr_rx_done : 1; /* RX_DONE Interrupt Bit */
3075  uint32_t : 31; /* *UNDEFINED* */
3076 };
3077 
3078 /* The typedef declaration for register ALT_I2C_CLR_RX_DONE. */
3079 typedef volatile struct ALT_I2C_CLR_RX_DONE_s ALT_I2C_CLR_RX_DONE_t;
3080 #endif /* __ASSEMBLY__ */
3081 
3082 /* The byte offset of the ALT_I2C_CLR_RX_DONE register from the beginning of the component. */
3083 #define ALT_I2C_CLR_RX_DONE_OFST 0x58
3084 /* The address of the ALT_I2C_CLR_RX_DONE register. */
3085 #define ALT_I2C_CLR_RX_DONE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_DONE_OFST))
3086 
3087 /*
3088  * Register : Activity Interrupt Register - ic_clr_activity
3089  *
3090  * Clears ACTIVITY Interrupt
3091  *
3092  * Register Layout
3093  *
3094  * Bits | Access | Reset | Description
3095  * :-------|:-------|:------|:-----------------------
3096  * [0] | R | 0x0 | Activity Interrupt Bit
3097  * [31:1] | ??? | 0x0 | *UNDEFINED*
3098  *
3099  */
3100 /*
3101  * Field : Activity Interrupt Bit - clr_activity
3102  *
3103  * Reading this register clears the ACTIVITY interrupt if the I2C is not active
3104  * anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt
3105  * bit continues to be set. It is automatically cleared by hardware if the module
3106  * is disabled and if there is no further activity on the bus. The value read from
3107  * this register to get status of the ACTIVITY interrupt (bit 8) of the
3108  * ic_raw_intr_stat register.
3109  *
3110  * Field Access Macros:
3111  *
3112  */
3113 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */
3114 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_LSB 0
3115 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */
3116 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_MSB 0
3117 /* The width in bits of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */
3118 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_WIDTH 1
3119 /* The mask used to set the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value. */
3120 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET_MSK 0x00000001
3121 /* The mask used to clear the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value. */
3122 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_CLR_MSK 0xfffffffe
3123 /* The reset value of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */
3124 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_RESET 0x0
3125 /* Extracts the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY field value from a register. */
3126 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0)
3127 /* Produces a ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value suitable for setting the register. */
3128 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET(value) (((value) << 0) & 0x00000001)
3129 
3130 #ifndef __ASSEMBLY__
3131 /*
3132  * WARNING: The C register and register group struct declarations are provided for
3133  * convenience and illustrative purposes. They should, however, be used with
3134  * caution as the C language standard provides no guarantees about the alignment or
3135  * atomicity of device memory accesses. The recommended practice for writing
3136  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3137  * alt_write_word() functions.
3138  *
3139  * The struct declaration for register ALT_I2C_CLR_ACTIVITY.
3140  */
3141 struct ALT_I2C_CLR_ACTIVITY_s
3142 {
3143  const uint32_t clr_activity : 1; /* Activity Interrupt Bit */
3144  uint32_t : 31; /* *UNDEFINED* */
3145 };
3146 
3147 /* The typedef declaration for register ALT_I2C_CLR_ACTIVITY. */
3148 typedef volatile struct ALT_I2C_CLR_ACTIVITY_s ALT_I2C_CLR_ACTIVITY_t;
3149 #endif /* __ASSEMBLY__ */
3150 
3151 /* The byte offset of the ALT_I2C_CLR_ACTIVITY register from the beginning of the component. */
3152 #define ALT_I2C_CLR_ACTIVITY_OFST 0x5c
3153 /* The address of the ALT_I2C_CLR_ACTIVITY register. */
3154 #define ALT_I2C_CLR_ACTIVITY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_ACTIVITY_OFST))
3155 
3156 /*
3157  * Register : Stop Detect Interrupt Register - ic_clr_stop_det
3158  *
3159  * Clear Interrupts.
3160  *
3161  * Register Layout
3162  *
3163  * Bits | Access | Reset | Description
3164  * :-------|:-------|:------|:--------------------------
3165  * [0] | R | 0x0 | Stop Detect Interrupt Bit
3166  * [31:1] | ??? | 0x0 | *UNDEFINED*
3167  *
3168  */
3169 /*
3170  * Field : Stop Detect Interrupt Bit - clr_stop_det
3171  *
3172  * Read this register to clear the clr_stop_det interrupt (bit 9) of the
3173  * ic_raw_intr_stat register.
3174  *
3175  * Field Access Macros:
3176  *
3177  */
3178 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */
3179 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_LSB 0
3180 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */
3181 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_MSB 0
3182 /* The width in bits of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */
3183 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_WIDTH 1
3184 /* The mask used to set the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value. */
3185 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET_MSK 0x00000001
3186 /* The mask used to clear the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value. */
3187 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_CLR_MSK 0xfffffffe
3188 /* The reset value of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */
3189 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_RESET 0x0
3190 /* Extracts the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET field value from a register. */
3191 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_GET(value) (((value) & 0x00000001) >> 0)
3192 /* Produces a ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value suitable for setting the register. */
3193 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET(value) (((value) << 0) & 0x00000001)
3194 
3195 #ifndef __ASSEMBLY__
3196 /*
3197  * WARNING: The C register and register group struct declarations are provided for
3198  * convenience and illustrative purposes. They should, however, be used with
3199  * caution as the C language standard provides no guarantees about the alignment or
3200  * atomicity of device memory accesses. The recommended practice for writing
3201  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3202  * alt_write_word() functions.
3203  *
3204  * The struct declaration for register ALT_I2C_CLR_STOP_DET.
3205  */
3206 struct ALT_I2C_CLR_STOP_DET_s
3207 {
3208  const uint32_t clr_stop_det : 1; /* Stop Detect Interrupt Bit */
3209  uint32_t : 31; /* *UNDEFINED* */
3210 };
3211 
3212 /* The typedef declaration for register ALT_I2C_CLR_STOP_DET. */
3213 typedef volatile struct ALT_I2C_CLR_STOP_DET_s ALT_I2C_CLR_STOP_DET_t;
3214 #endif /* __ASSEMBLY__ */
3215 
3216 /* The byte offset of the ALT_I2C_CLR_STOP_DET register from the beginning of the component. */
3217 #define ALT_I2C_CLR_STOP_DET_OFST 0x60
3218 /* The address of the ALT_I2C_CLR_STOP_DET register. */
3219 #define ALT_I2C_CLR_STOP_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_STOP_DET_OFST))
3220 
3221 /*
3222  * Register : Start Detect Interrupt Register - ic_clr_start_det
3223  *
3224  * Clears START_DET Interrupt
3225  *
3226  * Register Layout
3227  *
3228  * Bits | Access | Reset | Description
3229  * :-------|:-------|:------|:---------------------------
3230  * [0] | R | 0x0 | Start Detect Interrupt Bit
3231  * [31:1] | ??? | 0x0 | *UNDEFINED*
3232  *
3233  */
3234 /*
3235  * Field : Start Detect Interrupt Bit - clr_start_det
3236  *
3237  * Read this register to clear the start_det interrupt (bit 10) of the
3238  * ic_raw_intr_stat register.
3239  *
3240  * Field Access Macros:
3241  *
3242  */
3243 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */
3244 #define ALT_I2C_CLR_START_DET_CLR_START_DET_LSB 0
3245 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */
3246 #define ALT_I2C_CLR_START_DET_CLR_START_DET_MSB 0
3247 /* The width in bits of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */
3248 #define ALT_I2C_CLR_START_DET_CLR_START_DET_WIDTH 1
3249 /* The mask used to set the ALT_I2C_CLR_START_DET_CLR_START_DET register field value. */
3250 #define ALT_I2C_CLR_START_DET_CLR_START_DET_SET_MSK 0x00000001
3251 /* The mask used to clear the ALT_I2C_CLR_START_DET_CLR_START_DET register field value. */
3252 #define ALT_I2C_CLR_START_DET_CLR_START_DET_CLR_MSK 0xfffffffe
3253 /* The reset value of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */
3254 #define ALT_I2C_CLR_START_DET_CLR_START_DET_RESET 0x0
3255 /* Extracts the ALT_I2C_CLR_START_DET_CLR_START_DET field value from a register. */
3256 #define ALT_I2C_CLR_START_DET_CLR_START_DET_GET(value) (((value) & 0x00000001) >> 0)
3257 /* Produces a ALT_I2C_CLR_START_DET_CLR_START_DET register field value suitable for setting the register. */
3258 #define ALT_I2C_CLR_START_DET_CLR_START_DET_SET(value) (((value) << 0) & 0x00000001)
3259 
3260 #ifndef __ASSEMBLY__
3261 /*
3262  * WARNING: The C register and register group struct declarations are provided for
3263  * convenience and illustrative purposes. They should, however, be used with
3264  * caution as the C language standard provides no guarantees about the alignment or
3265  * atomicity of device memory accesses. The recommended practice for writing
3266  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3267  * alt_write_word() functions.
3268  *
3269  * The struct declaration for register ALT_I2C_CLR_START_DET.
3270  */
3271 struct ALT_I2C_CLR_START_DET_s
3272 {
3273  const uint32_t clr_start_det : 1; /* Start Detect Interrupt Bit */
3274  uint32_t : 31; /* *UNDEFINED* */
3275 };
3276 
3277 /* The typedef declaration for register ALT_I2C_CLR_START_DET. */
3278 typedef volatile struct ALT_I2C_CLR_START_DET_s ALT_I2C_CLR_START_DET_t;
3279 #endif /* __ASSEMBLY__ */
3280 
3281 /* The byte offset of the ALT_I2C_CLR_START_DET register from the beginning of the component. */
3282 #define ALT_I2C_CLR_START_DET_OFST 0x64
3283 /* The address of the ALT_I2C_CLR_START_DET register. */
3284 #define ALT_I2C_CLR_START_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_START_DET_OFST))
3285 
3286 /*
3287  * Register : GEN CALL Interrupt Register - ic_clr_gen_call
3288  *
3289  * Clear GEN_CALL Interrupt Register
3290  *
3291  * Register Layout
3292  *
3293  * Bits | Access | Reset | Description
3294  * :-------|:-------|:------|:-----------------------
3295  * [0] | R | 0x0 | GEN CALL Interrupt Bit
3296  * [31:1] | ??? | 0x0 | *UNDEFINED*
3297  *
3298  */
3299 /*
3300  * Field : GEN CALL Interrupt Bit - clr_gen_call
3301  *
3302  * Read this register to clear the GEN_CALL interrupt (bit 11) of ic_raw_intr_stat
3303  * register.
3304  *
3305  * Field Access Macros:
3306  *
3307  */
3308 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */
3309 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_LSB 0
3310 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */
3311 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_MSB 0
3312 /* The width in bits of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */
3313 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_WIDTH 1
3314 /* The mask used to set the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value. */
3315 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET_MSK 0x00000001
3316 /* The mask used to clear the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value. */
3317 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_CLR_MSK 0xfffffffe
3318 /* The reset value of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */
3319 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_RESET 0x0
3320 /* Extracts the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL field value from a register. */
3321 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0)
3322 /* Produces a ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value suitable for setting the register. */
3323 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET(value) (((value) << 0) & 0x00000001)
3324 
3325 #ifndef __ASSEMBLY__
3326 /*
3327  * WARNING: The C register and register group struct declarations are provided for
3328  * convenience and illustrative purposes. They should, however, be used with
3329  * caution as the C language standard provides no guarantees about the alignment or
3330  * atomicity of device memory accesses. The recommended practice for writing
3331  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3332  * alt_write_word() functions.
3333  *
3334  * The struct declaration for register ALT_I2C_CLR_GEN_CALL.
3335  */
3336 struct ALT_I2C_CLR_GEN_CALL_s
3337 {
3338  const uint32_t clr_gen_call : 1; /* GEN CALL Interrupt Bit */
3339  uint32_t : 31; /* *UNDEFINED* */
3340 };
3341 
3342 /* The typedef declaration for register ALT_I2C_CLR_GEN_CALL. */
3343 typedef volatile struct ALT_I2C_CLR_GEN_CALL_s ALT_I2C_CLR_GEN_CALL_t;
3344 #endif /* __ASSEMBLY__ */
3345 
3346 /* The byte offset of the ALT_I2C_CLR_GEN_CALL register from the beginning of the component. */
3347 #define ALT_I2C_CLR_GEN_CALL_OFST 0x68
3348 /* The address of the ALT_I2C_CLR_GEN_CALL register. */
3349 #define ALT_I2C_CLR_GEN_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_GEN_CALL_OFST))
3350 
3351 /*
3352  * Register : Enable Register - ic_enable
3353  *
3354  * Enable and disable i2c operation
3355  *
3356  * Register Layout
3357  *
3358  * Bits | Access | Reset | Description
3359  * :-------|:-------|:------|:-------------
3360  * [0] | RW | 0x0 | Enable Bit
3361  * [1] | RW | 0x0 | TX abort Bit
3362  * [31:2] | ??? | 0x0 | *UNDEFINED*
3363  *
3364  */
3365 /*
3366  * Field : Enable Bit - enable
3367  *
3368  * Controls whether the I2C is enabled. Software can disable I2C while it is
3369  * active. However, it is important that care be taken to ensure that I2C is
3370  * disabled properly. When the I2C is disabled, the following occurs:
3371  *
3372  * The TX FIFO and RX FIFO get flushed. Status bits in the IC_INTR_STAT register
3373  * are still active until I2C goes into IDLE state. If the module is transmitting,
3374  * it stops as well as deletes the contents of the transmit buffer after the
3375  * current transfer is complete. If the module is receiving, the I2C stops the
3376  * current transfer at the end of the current byte and does not acknowledge the
3377  * transfer. The l4_sp_clk synchronizes pclk and ic_clk. The register
3378  * ic_enable_status is added to allow software to determine when the hardware has
3379  * completely shutdown in response to the IC_ENABLE register being set from 1 to 0.
3380  * Only one register is required to be monitored. Procedure for Disabling I2C
3381  *
3382  * 1. Define a timer interval (ti2c_poll) equal to the 10 times the signaling
3383  * period for the highest I2C transfer speed used in the system and supported by
3384  * I2C. For example, if the highest I2C transfer mode is 400 kb/s, then this
3385  * ti2c_poll is 25us.
3386  *
3387  * 2. Define a maximum time-out parameter, MAX_T_POLL_COUNT, such that if any
3388  * repeated polling operation exceeds this maximum value, an error is reported. 3.
3389  * Execute a blocking thread/process/function that prevents any further I2C master
3390  * transactions to be started by software, but allows any pending transfers to be
3391  * completed.
3392  *
3393  * 4. The variable POLL_COUNT is initialized to zero. 5. Set IC_ENABLE to 0.
3394  *
3395  * 6. Read the IC_ENABLE_STATUS register and test the IC_EN bit (bit 0). Increment
3396  * POLL_COUNT by one. If POLL_COUNT >= MAX_T_POLL_COUNT, exit with the relevant
3397  * error code.
3398  *
3399  * 7. If IC_ENABLE_STATUS[0] is 1, then sleep for ti2c_poll and proceed to the
3400  * previous step. Otherwise, exit with a relevant success code.
3401  *
3402  * Field Enumeration Values:
3403  *
3404  * Enum | Value | Description
3405  * :--------------------|:------|:-----------------------------------------------
3406  * ALT_I2C_EN_EN_E_DIS | 0x0 | Disables i2c. TX and RX FIFOs are held in an
3407  * : | | erased state
3408  * ALT_I2C_EN_EN_E_EN | 0x1 | Enables i2c. Software can disable i2c while it
3409  * : | | is active
3410  *
3411  * Field Access Macros:
3412  *
3413  */
3414 /*
3415  * Enumerated value for register field ALT_I2C_EN_EN
3416  *
3417  * Disables i2c. TX and RX FIFOs are held in an erased state
3418  */
3419 #define ALT_I2C_EN_EN_E_DIS 0x0
3420 /*
3421  * Enumerated value for register field ALT_I2C_EN_EN
3422  *
3423  * Enables i2c. Software can disable i2c while it is active
3424  */
3425 #define ALT_I2C_EN_EN_E_EN 0x1
3426 
3427 /* The Least Significant Bit (LSB) position of the ALT_I2C_EN_EN register field. */
3428 #define ALT_I2C_EN_EN_LSB 0
3429 /* The Most Significant Bit (MSB) position of the ALT_I2C_EN_EN register field. */
3430 #define ALT_I2C_EN_EN_MSB 0
3431 /* The width in bits of the ALT_I2C_EN_EN register field. */
3432 #define ALT_I2C_EN_EN_WIDTH 1
3433 /* The mask used to set the ALT_I2C_EN_EN register field value. */
3434 #define ALT_I2C_EN_EN_SET_MSK 0x00000001
3435 /* The mask used to clear the ALT_I2C_EN_EN register field value. */
3436 #define ALT_I2C_EN_EN_CLR_MSK 0xfffffffe
3437 /* The reset value of the ALT_I2C_EN_EN register field. */
3438 #define ALT_I2C_EN_EN_RESET 0x0
3439 /* Extracts the ALT_I2C_EN_EN field value from a register. */
3440 #define ALT_I2C_EN_EN_GET(value) (((value) & 0x00000001) >> 0)
3441 /* Produces a ALT_I2C_EN_EN register field value suitable for setting the register. */
3442 #define ALT_I2C_EN_EN_SET(value) (((value) << 0) & 0x00000001)
3443 
3444 /*
3445  * Field : TX abort Bit - txabort
3446  *
3447  * Write 1 does a TX abort. Self cleared on abort completion
3448  *
3449  * Field Access Macros:
3450  *
3451  */
3452 /* The Least Significant Bit (LSB) position of the ALT_I2C_EN_TXABT register field. */
3453 #define ALT_I2C_EN_TXABT_LSB 1
3454 /* The Most Significant Bit (MSB) position of the ALT_I2C_EN_TXABT register field. */
3455 #define ALT_I2C_EN_TXABT_MSB 1
3456 /* The width in bits of the ALT_I2C_EN_TXABT register field. */
3457 #define ALT_I2C_EN_TXABT_WIDTH 1
3458 /* The mask used to set the ALT_I2C_EN_TXABT register field value. */
3459 #define ALT_I2C_EN_TXABT_SET_MSK 0x00000002
3460 /* The mask used to clear the ALT_I2C_EN_TXABT register field value. */
3461 #define ALT_I2C_EN_TXABT_CLR_MSK 0xfffffffd
3462 /* The reset value of the ALT_I2C_EN_TXABT register field. */
3463 #define ALT_I2C_EN_TXABT_RESET 0x0
3464 /* Extracts the ALT_I2C_EN_TXABT field value from a register. */
3465 #define ALT_I2C_EN_TXABT_GET(value) (((value) & 0x00000002) >> 1)
3466 /* Produces a ALT_I2C_EN_TXABT register field value suitable for setting the register. */
3467 #define ALT_I2C_EN_TXABT_SET(value) (((value) << 1) & 0x00000002)
3468 
3469 #ifndef __ASSEMBLY__
3470 /*
3471  * WARNING: The C register and register group struct declarations are provided for
3472  * convenience and illustrative purposes. They should, however, be used with
3473  * caution as the C language standard provides no guarantees about the alignment or
3474  * atomicity of device memory accesses. The recommended practice for writing
3475  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3476  * alt_write_word() functions.
3477  *
3478  * The struct declaration for register ALT_I2C_EN.
3479  */
3480 struct ALT_I2C_EN_s
3481 {
3482  uint32_t enable : 1; /* Enable Bit */
3483  uint32_t txabort : 1; /* TX abort Bit */
3484  uint32_t : 30; /* *UNDEFINED* */
3485 };
3486 
3487 /* The typedef declaration for register ALT_I2C_EN. */
3488 typedef volatile struct ALT_I2C_EN_s ALT_I2C_EN_t;
3489 #endif /* __ASSEMBLY__ */
3490 
3491 /* The byte offset of the ALT_I2C_EN register from the beginning of the component. */
3492 #define ALT_I2C_EN_OFST 0x6c
3493 /* The address of the ALT_I2C_EN register. */
3494 #define ALT_I2C_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_OFST))
3495 
3496 /*
3497  * Register : Status Register - ic_status
3498  *
3499  * This is a read-only register used to indicate the current transfer status and
3500  * FIFO status. The status register may be read at any time. None of the bits in
3501  * this register request an interrupt.When the I2C is disabled by writing 0 in bit
3502  * 0 of the ic_enable register:
3503  *
3504  * * Bits 1 and 2 are set to 1
3505  *
3506  * * Bits 3 and 4 are set to 0
3507  *
3508  * When the master or slave state machines goes to idle
3509  *
3510  * * Bits 5 and 6 are set to 0
3511  *
3512  * Register Layout
3513  *
3514  * Bits | Access | Reset | Description
3515  * :-------|:-------|:------|:-------------------------------
3516  * [0] | R | 0x0 | Activity Status Bit
3517  * [1] | R | 0x1 | TX FIFO Not Full Bit
3518  * [2] | R | 0x1 | TX FIFO Empty Bit
3519  * [3] | R | 0x0 | RX FIFO Empty Bit
3520  * [4] | R | 0x0 | RX FIFO Full Bit
3521  * [5] | R | 0x0 | Master FSM Activity Status Bit
3522  * [6] | R | 0x0 | Slave FSM Activity Status Bit
3523  * [31:7] | ??? | 0x0 | *UNDEFINED*
3524  *
3525  */
3526 /*
3527  * Field : Activity Status Bit - activity
3528  *
3529  * I2C Activity.
3530  *
3531  * Field Access Macros:
3532  *
3533  */
3534 /* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_ACTIVITY register field. */
3535 #define ALT_I2C_STAT_ACTIVITY_LSB 0
3536 /* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_ACTIVITY register field. */
3537 #define ALT_I2C_STAT_ACTIVITY_MSB 0
3538 /* The width in bits of the ALT_I2C_STAT_ACTIVITY register field. */
3539 #define ALT_I2C_STAT_ACTIVITY_WIDTH 1
3540 /* The mask used to set the ALT_I2C_STAT_ACTIVITY register field value. */
3541 #define ALT_I2C_STAT_ACTIVITY_SET_MSK 0x00000001
3542 /* The mask used to clear the ALT_I2C_STAT_ACTIVITY register field value. */
3543 #define ALT_I2C_STAT_ACTIVITY_CLR_MSK 0xfffffffe
3544 /* The reset value of the ALT_I2C_STAT_ACTIVITY register field. */
3545 #define ALT_I2C_STAT_ACTIVITY_RESET 0x0
3546 /* Extracts the ALT_I2C_STAT_ACTIVITY field value from a register. */
3547 #define ALT_I2C_STAT_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0)
3548 /* Produces a ALT_I2C_STAT_ACTIVITY register field value suitable for setting the register. */
3549 #define ALT_I2C_STAT_ACTIVITY_SET(value) (((value) << 0) & 0x00000001)
3550 
3551 /*
3552  * Field : TX FIFO Not Full Bit - tfnf
3553  *
3554  * Transmit Fifo Full
3555  *
3556  * Field Enumeration Values:
3557  *
3558  * Enum | Value | Description
3559  * :----------------------------|:------|:--------------------------
3560  * ALT_I2C_STAT_TFNF_E_FULL | 0x0 | Transmit FIFO is full
3561  * ALT_I2C_STAT_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full
3562  *
3563  * Field Access Macros:
3564  *
3565  */
3566 /*
3567  * Enumerated value for register field ALT_I2C_STAT_TFNF
3568  *
3569  * Transmit FIFO is full
3570  */
3571 #define ALT_I2C_STAT_TFNF_E_FULL 0x0
3572 /*
3573  * Enumerated value for register field ALT_I2C_STAT_TFNF
3574  *
3575  * Transmit FIFO is not full
3576  */
3577 #define ALT_I2C_STAT_TFNF_E_NOTFULL 0x1
3578 
3579 /* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_TFNF register field. */
3580 #define ALT_I2C_STAT_TFNF_LSB 1
3581 /* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_TFNF register field. */
3582 #define ALT_I2C_STAT_TFNF_MSB 1
3583 /* The width in bits of the ALT_I2C_STAT_TFNF register field. */
3584 #define ALT_I2C_STAT_TFNF_WIDTH 1
3585 /* The mask used to set the ALT_I2C_STAT_TFNF register field value. */
3586 #define ALT_I2C_STAT_TFNF_SET_MSK 0x00000002
3587 /* The mask used to clear the ALT_I2C_STAT_TFNF register field value. */
3588 #define ALT_I2C_STAT_TFNF_CLR_MSK 0xfffffffd
3589 /* The reset value of the ALT_I2C_STAT_TFNF register field. */
3590 #define ALT_I2C_STAT_TFNF_RESET 0x1
3591 /* Extracts the ALT_I2C_STAT_TFNF field value from a register. */
3592 #define ALT_I2C_STAT_TFNF_GET(value) (((value) & 0x00000002) >> 1)
3593 /* Produces a ALT_I2C_STAT_TFNF register field value suitable for setting the register. */
3594 #define ALT_I2C_STAT_TFNF_SET(value) (((value) << 1) & 0x00000002)
3595 
3596 /*
3597  * Field : TX FIFO Empty Bit - tfe
3598  *
3599  * Transmit FIFO Empty.
3600  *
3601  * Field Enumeration Values:
3602  *
3603  * Enum | Value | Description
3604  * :----------------------------|:------|:---------------------------
3605  * ALT_I2C_STAT_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty
3606  * ALT_I2C_STAT_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty
3607  *
3608  * Field Access Macros:
3609  *
3610  */
3611 /*
3612  * Enumerated value for register field ALT_I2C_STAT_TFE
3613  *
3614  * Transmit FIFO is not empty
3615  */
3616 #define ALT_I2C_STAT_TFE_E_NOTEMPTY 0x0
3617 /*
3618  * Enumerated value for register field ALT_I2C_STAT_TFE
3619  *
3620  * Transmit FIFO is empty
3621  */
3622 #define ALT_I2C_STAT_TFE_E_EMPTY 0x1
3623 
3624 /* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_TFE register field. */
3625 #define ALT_I2C_STAT_TFE_LSB 2
3626 /* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_TFE register field. */
3627 #define ALT_I2C_STAT_TFE_MSB 2
3628 /* The width in bits of the ALT_I2C_STAT_TFE register field. */
3629 #define ALT_I2C_STAT_TFE_WIDTH 1
3630 /* The mask used to set the ALT_I2C_STAT_TFE register field value. */
3631 #define ALT_I2C_STAT_TFE_SET_MSK 0x00000004
3632 /* The mask used to clear the ALT_I2C_STAT_TFE register field value. */
3633 #define ALT_I2C_STAT_TFE_CLR_MSK 0xfffffffb
3634 /* The reset value of the ALT_I2C_STAT_TFE register field. */
3635 #define ALT_I2C_STAT_TFE_RESET 0x1
3636 /* Extracts the ALT_I2C_STAT_TFE field value from a register. */
3637 #define ALT_I2C_STAT_TFE_GET(value) (((value) & 0x00000004) >> 2)
3638 /* Produces a ALT_I2C_STAT_TFE register field value suitable for setting the register. */
3639 #define ALT_I2C_STAT_TFE_SET(value) (((value) << 2) & 0x00000004)
3640 
3641 /*
3642  * Field : RX FIFO Empty Bit - rfne
3643  *
3644  * Receive FIFO Not Empty.
3645  *
3646  * Field Enumeration Values:
3647  *
3648  * Enum | Value | Description
3649  * :-----------------------------|:------|:--------------------------
3650  * ALT_I2C_STAT_RFNE_E_EMPTY | 0x0 | Receive FIFO is empty
3651  * ALT_I2C_STAT_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty
3652  *
3653  * Field Access Macros:
3654  *
3655  */
3656 /*
3657  * Enumerated value for register field ALT_I2C_STAT_RFNE
3658  *
3659  * Receive FIFO is empty
3660  */
3661 #define ALT_I2C_STAT_RFNE_E_EMPTY 0x0
3662 /*
3663  * Enumerated value for register field ALT_I2C_STAT_RFNE
3664  *
3665  * Receive FIFO is not empty
3666  */
3667 #define ALT_I2C_STAT_RFNE_E_NOTEMPTY 0x1
3668 
3669 /* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_RFNE register field. */
3670 #define ALT_I2C_STAT_RFNE_LSB 3
3671 /* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_RFNE register field. */
3672 #define ALT_I2C_STAT_RFNE_MSB 3
3673 /* The width in bits of the ALT_I2C_STAT_RFNE register field. */
3674 #define ALT_I2C_STAT_RFNE_WIDTH 1
3675 /* The mask used to set the ALT_I2C_STAT_RFNE register field value. */
3676 #define ALT_I2C_STAT_RFNE_SET_MSK 0x00000008
3677 /* The mask used to clear the ALT_I2C_STAT_RFNE register field value. */
3678 #define ALT_I2C_STAT_RFNE_CLR_MSK 0xfffffff7
3679 /* The reset value of the ALT_I2C_STAT_RFNE register field. */
3680 #define ALT_I2C_STAT_RFNE_RESET 0x0
3681 /* Extracts the ALT_I2C_STAT_RFNE field value from a register. */
3682 #define ALT_I2C_STAT_RFNE_GET(value) (((value) & 0x00000008) >> 3)
3683 /* Produces a ALT_I2C_STAT_RFNE register field value suitable for setting the register. */
3684 #define ALT_I2C_STAT_RFNE_SET(value) (((value) << 3) & 0x00000008)
3685 
3686 /*
3687  * Field : RX FIFO Full Bit - rff
3688  *
3689  * Receive FIFO Completely Full.
3690  *
3691  * Field Enumeration Values:
3692  *
3693  * Enum | Value | Description
3694  * :---------------------------|:------|:-------------------------
3695  * ALT_I2C_STAT_RFF_E_NOTFULL | 0x0 | Receive FIFO is not full
3696  * ALT_I2C_STAT_RFF_E_FULL | 0x1 | Receive FIFO is full
3697  *
3698  * Field Access Macros:
3699  *
3700  */
3701 /*
3702  * Enumerated value for register field ALT_I2C_STAT_RFF
3703  *
3704  * Receive FIFO is not full
3705  */
3706 #define ALT_I2C_STAT_RFF_E_NOTFULL 0x0
3707 /*
3708  * Enumerated value for register field ALT_I2C_STAT_RFF
3709  *
3710  * Receive FIFO is full
3711  */
3712 #define ALT_I2C_STAT_RFF_E_FULL 0x1
3713 
3714 /* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_RFF register field. */
3715 #define ALT_I2C_STAT_RFF_LSB 4
3716 /* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_RFF register field. */
3717 #define ALT_I2C_STAT_RFF_MSB 4
3718 /* The width in bits of the ALT_I2C_STAT_RFF register field. */
3719 #define ALT_I2C_STAT_RFF_WIDTH 1
3720 /* The mask used to set the ALT_I2C_STAT_RFF register field value. */
3721 #define ALT_I2C_STAT_RFF_SET_MSK 0x00000010
3722 /* The mask used to clear the ALT_I2C_STAT_RFF register field value. */
3723 #define ALT_I2C_STAT_RFF_CLR_MSK 0xffffffef
3724 /* The reset value of the ALT_I2C_STAT_RFF register field. */
3725 #define ALT_I2C_STAT_RFF_RESET 0x0
3726 /* Extracts the ALT_I2C_STAT_RFF field value from a register. */
3727 #define ALT_I2C_STAT_RFF_GET(value) (((value) & 0x00000010) >> 4)
3728 /* Produces a ALT_I2C_STAT_RFF register field value suitable for setting the register. */
3729 #define ALT_I2C_STAT_RFF_SET(value) (((value) << 4) & 0x00000010)
3730 
3731 /*
3732  * Field : Master FSM Activity Status Bit - mst_activity
3733  *
3734  * When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is
3735  * set. Note:IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and
3736  * MST_ACTIVITY bits.
3737  *
3738  * Field Enumeration Values:
3739  *
3740  * Enum | Value | Description
3741  * :------------------------------------|:------|:------------------------------------------------
3742  * ALT_I2C_STAT_MST_ACTIVITY_E_IDLE | 0x0 | Master FSM is in IDLE state. Master part of i2c
3743  * : | | is not Active
3744  * ALT_I2C_STAT_MST_ACTIVITY_E_NOTIDLE | 0x1 | Master FSM is not in IDLE state. Master part of
3745  * : | | i2c is Active
3746  *
3747  * Field Access Macros:
3748  *
3749  */
3750 /*
3751  * Enumerated value for register field ALT_I2C_STAT_MST_ACTIVITY
3752  *
3753  * Master FSM is in IDLE state. Master part of i2c is not Active
3754  */
3755 #define ALT_I2C_STAT_MST_ACTIVITY_E_IDLE 0x0
3756 /*
3757  * Enumerated value for register field ALT_I2C_STAT_MST_ACTIVITY
3758  *
3759  * Master FSM is not in IDLE state. Master part of i2c is Active
3760  */
3761 #define ALT_I2C_STAT_MST_ACTIVITY_E_NOTIDLE 0x1
3762 
3763 /* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_MST_ACTIVITY register field. */
3764 #define ALT_I2C_STAT_MST_ACTIVITY_LSB 5
3765 /* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_MST_ACTIVITY register field. */
3766 #define ALT_I2C_STAT_MST_ACTIVITY_MSB 5
3767 /* The width in bits of the ALT_I2C_STAT_MST_ACTIVITY register field. */
3768 #define ALT_I2C_STAT_MST_ACTIVITY_WIDTH 1
3769 /* The mask used to set the ALT_I2C_STAT_MST_ACTIVITY register field value. */
3770 #define ALT_I2C_STAT_MST_ACTIVITY_SET_MSK 0x00000020
3771 /* The mask used to clear the ALT_I2C_STAT_MST_ACTIVITY register field value. */
3772 #define ALT_I2C_STAT_MST_ACTIVITY_CLR_MSK 0xffffffdf
3773 /* The reset value of the ALT_I2C_STAT_MST_ACTIVITY register field. */
3774 #define ALT_I2C_STAT_MST_ACTIVITY_RESET 0x0
3775 /* Extracts the ALT_I2C_STAT_MST_ACTIVITY field value from a register. */
3776 #define ALT_I2C_STAT_MST_ACTIVITY_GET(value) (((value) & 0x00000020) >> 5)
3777 /* Produces a ALT_I2C_STAT_MST_ACTIVITY register field value suitable for setting the register. */
3778 #define ALT_I2C_STAT_MST_ACTIVITY_SET(value) (((value) << 5) & 0x00000020)
3779 
3780 /*
3781  * Field : Slave FSM Activity Status Bit - slv_activity
3782  *
3783  * Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in
3784  * the IDLE state, this bit is set.
3785  *
3786  * Field Enumeration Values:
3787  *
3788  * Enum | Value | Description
3789  * :------------------------------------|:------|:-------------------------------------------------
3790  * ALT_I2C_STAT_SLV_ACTIVITY_E_IDLE | 0x0 | Slave FSM is in IDLE state so the Slave part of
3791  * : | | i2c is not Active
3792  * ALT_I2C_STAT_SLV_ACTIVITY_E_NOTIDLE | 0x1 | Slave FSM is not in IDLE state so the Slave part
3793  * : | | of i2c is Active
3794  *
3795  * Field Access Macros:
3796  *
3797  */
3798 /*
3799  * Enumerated value for register field ALT_I2C_STAT_SLV_ACTIVITY
3800  *
3801  * Slave FSM is in IDLE state so the Slave part of i2c is not Active
3802  */
3803 #define ALT_I2C_STAT_SLV_ACTIVITY_E_IDLE 0x0
3804 /*
3805  * Enumerated value for register field ALT_I2C_STAT_SLV_ACTIVITY
3806  *
3807  * Slave FSM is not in IDLE state so the Slave part of i2c is Active
3808  */
3809 #define ALT_I2C_STAT_SLV_ACTIVITY_E_NOTIDLE 0x1
3810 
3811 /* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_SLV_ACTIVITY register field. */
3812 #define ALT_I2C_STAT_SLV_ACTIVITY_LSB 6
3813 /* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_SLV_ACTIVITY register field. */
3814 #define ALT_I2C_STAT_SLV_ACTIVITY_MSB 6
3815 /* The width in bits of the ALT_I2C_STAT_SLV_ACTIVITY register field. */
3816 #define ALT_I2C_STAT_SLV_ACTIVITY_WIDTH 1
3817 /* The mask used to set the ALT_I2C_STAT_SLV_ACTIVITY register field value. */
3818 #define ALT_I2C_STAT_SLV_ACTIVITY_SET_MSK 0x00000040
3819 /* The mask used to clear the ALT_I2C_STAT_SLV_ACTIVITY register field value. */
3820 #define ALT_I2C_STAT_SLV_ACTIVITY_CLR_MSK 0xffffffbf
3821 /* The reset value of the ALT_I2C_STAT_SLV_ACTIVITY register field. */
3822 #define ALT_I2C_STAT_SLV_ACTIVITY_RESET 0x0
3823 /* Extracts the ALT_I2C_STAT_SLV_ACTIVITY field value from a register. */
3824 #define ALT_I2C_STAT_SLV_ACTIVITY_GET(value) (((value) & 0x00000040) >> 6)
3825 /* Produces a ALT_I2C_STAT_SLV_ACTIVITY register field value suitable for setting the register. */
3826 #define ALT_I2C_STAT_SLV_ACTIVITY_SET(value) (((value) << 6) & 0x00000040)
3827 
3828 #ifndef __ASSEMBLY__
3829 /*
3830  * WARNING: The C register and register group struct declarations are provided for
3831  * convenience and illustrative purposes. They should, however, be used with
3832  * caution as the C language standard provides no guarantees about the alignment or
3833  * atomicity of device memory accesses. The recommended practice for writing
3834  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3835  * alt_write_word() functions.
3836  *
3837  * The struct declaration for register ALT_I2C_STAT.
3838  */
3839 struct ALT_I2C_STAT_s
3840 {
3841  const uint32_t activity : 1; /* Activity Status Bit */
3842  const uint32_t tfnf : 1; /* TX FIFO Not Full Bit */
3843  const uint32_t tfe : 1; /* TX FIFO Empty Bit */
3844  const uint32_t rfne : 1; /* RX FIFO Empty Bit */
3845  const uint32_t rff : 1; /* RX FIFO Full Bit */
3846  const uint32_t mst_activity : 1; /* Master FSM Activity Status Bit */
3847  const uint32_t slv_activity : 1; /* Slave FSM Activity Status Bit */
3848  uint32_t : 25; /* *UNDEFINED* */
3849 };
3850 
3851 /* The typedef declaration for register ALT_I2C_STAT. */
3852 typedef volatile struct ALT_I2C_STAT_s ALT_I2C_STAT_t;
3853 #endif /* __ASSEMBLY__ */
3854 
3855 /* The byte offset of the ALT_I2C_STAT register from the beginning of the component. */
3856 #define ALT_I2C_STAT_OFST 0x70
3857 /* The address of the ALT_I2C_STAT register. */
3858 #define ALT_I2C_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_STAT_OFST))
3859 
3860 /*
3861  * Register : Transmit FIFO Level Register - ic_txflr
3862  *
3863  * This register contains the number of valid data entries in the transmit FIFO
3864  * buffer. It is cleared whenever:
3865  *
3866  * * The I2C is disabled
3867  *
3868  * * There is a transmit abort that is, TX_ABRT bit is set in the ic_raw_intr_stat
3869  * register. The slave bulk transmit mode is aborted The register increments
3870  * whenever data is placed into the transmit FIFO and decrements when data is
3871  * taken from the transmit FIFO.
3872  *
3873  * Register Layout
3874  *
3875  * Bits | Access | Reset | Description
3876  * :-------|:-------|:------|:------------------------
3877  * [6:0] | R | 0x0 | Transmit FIFO Level Bit
3878  * [31:7] | ??? | 0x0 | *UNDEFINED*
3879  *
3880  */
3881 /*
3882  * Field : Transmit FIFO Level Bit - txflr
3883  *
3884  * Transmit FIFO Level.Contains the number of valid data entries in the transmit
3885  * FIFO.
3886  *
3887  * Field Access Macros:
3888  *
3889  */
3890 /* The Least Significant Bit (LSB) position of the ALT_I2C_TXFLR_TXFLR register field. */
3891 #define ALT_I2C_TXFLR_TXFLR_LSB 0
3892 /* The Most Significant Bit (MSB) position of the ALT_I2C_TXFLR_TXFLR register field. */
3893 #define ALT_I2C_TXFLR_TXFLR_MSB 6
3894 /* The width in bits of the ALT_I2C_TXFLR_TXFLR register field. */
3895 #define ALT_I2C_TXFLR_TXFLR_WIDTH 7
3896 /* The mask used to set the ALT_I2C_TXFLR_TXFLR register field value. */
3897 #define ALT_I2C_TXFLR_TXFLR_SET_MSK 0x0000007f
3898 /* The mask used to clear the ALT_I2C_TXFLR_TXFLR register field value. */
3899 #define ALT_I2C_TXFLR_TXFLR_CLR_MSK 0xffffff80
3900 /* The reset value of the ALT_I2C_TXFLR_TXFLR register field. */
3901 #define ALT_I2C_TXFLR_TXFLR_RESET 0x0
3902 /* Extracts the ALT_I2C_TXFLR_TXFLR field value from a register. */
3903 #define ALT_I2C_TXFLR_TXFLR_GET(value) (((value) & 0x0000007f) >> 0)
3904 /* Produces a ALT_I2C_TXFLR_TXFLR register field value suitable for setting the register. */
3905 #define ALT_I2C_TXFLR_TXFLR_SET(value) (((value) << 0) & 0x0000007f)
3906 
3907 #ifndef __ASSEMBLY__
3908 /*
3909  * WARNING: The C register and register group struct declarations are provided for
3910  * convenience and illustrative purposes. They should, however, be used with
3911  * caution as the C language standard provides no guarantees about the alignment or
3912  * atomicity of device memory accesses. The recommended practice for writing
3913  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3914  * alt_write_word() functions.
3915  *
3916  * The struct declaration for register ALT_I2C_TXFLR.
3917  */
3918 struct ALT_I2C_TXFLR_s
3919 {
3920  const uint32_t txflr : 7; /* Transmit FIFO Level Bit */
3921  uint32_t : 25; /* *UNDEFINED* */
3922 };
3923 
3924 /* The typedef declaration for register ALT_I2C_TXFLR. */
3925 typedef volatile struct ALT_I2C_TXFLR_s ALT_I2C_TXFLR_t;
3926 #endif /* __ASSEMBLY__ */
3927 
3928 /* The byte offset of the ALT_I2C_TXFLR register from the beginning of the component. */
3929 #define ALT_I2C_TXFLR_OFST 0x74
3930 /* The address of the ALT_I2C_TXFLR register. */
3931 #define ALT_I2C_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TXFLR_OFST))
3932 
3933 /*
3934  * Register : Receive FIFO Level Register - ic_rxflr
3935  *
3936  * This register contains the number of valid data entries in the receive FIFO
3937  * buffer. It is cleared whenever:
3938  *
3939  * * The I2C is disabled
3940  *
3941  * * Whenever there is a transmit abort caused by any of the events tracked in
3942  * ic_tx_abrt_source The register increments whenever data is placed into the
3943  * receive FIFO and decrements when data is taken from the receive FIFO.
3944  *
3945  * Register Layout
3946  *
3947  * Bits | Access | Reset | Description
3948  * :-------|:-------|:------|:-----------------------
3949  * [6:0] | R | 0x0 | Receive FIFO Level Bit
3950  * [31:7] | ??? | 0x0 | *UNDEFINED*
3951  *
3952  */
3953 /*
3954  * Field : Receive FIFO Level Bit - rxflr
3955  *
3956  * Receive FIFO Level. Contains the number of valid data entries in the receive
3957  * FIFO.
3958  *
3959  * Field Access Macros:
3960  *
3961  */
3962 /* The Least Significant Bit (LSB) position of the ALT_I2C_RXFLR_RXFLR register field. */
3963 #define ALT_I2C_RXFLR_RXFLR_LSB 0
3964 /* The Most Significant Bit (MSB) position of the ALT_I2C_RXFLR_RXFLR register field. */
3965 #define ALT_I2C_RXFLR_RXFLR_MSB 6
3966 /* The width in bits of the ALT_I2C_RXFLR_RXFLR register field. */
3967 #define ALT_I2C_RXFLR_RXFLR_WIDTH 7
3968 /* The mask used to set the ALT_I2C_RXFLR_RXFLR register field value. */
3969 #define ALT_I2C_RXFLR_RXFLR_SET_MSK 0x0000007f
3970 /* The mask used to clear the ALT_I2C_RXFLR_RXFLR register field value. */
3971 #define ALT_I2C_RXFLR_RXFLR_CLR_MSK 0xffffff80
3972 /* The reset value of the ALT_I2C_RXFLR_RXFLR register field. */
3973 #define ALT_I2C_RXFLR_RXFLR_RESET 0x0
3974 /* Extracts the ALT_I2C_RXFLR_RXFLR field value from a register. */
3975 #define ALT_I2C_RXFLR_RXFLR_GET(value) (((value) & 0x0000007f) >> 0)
3976 /* Produces a ALT_I2C_RXFLR_RXFLR register field value suitable for setting the register. */
3977 #define ALT_I2C_RXFLR_RXFLR_SET(value) (((value) << 0) & 0x0000007f)
3978 
3979 #ifndef __ASSEMBLY__
3980 /*
3981  * WARNING: The C register and register group struct declarations are provided for
3982  * convenience and illustrative purposes. They should, however, be used with
3983  * caution as the C language standard provides no guarantees about the alignment or
3984  * atomicity of device memory accesses. The recommended practice for writing
3985  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3986  * alt_write_word() functions.
3987  *
3988  * The struct declaration for register ALT_I2C_RXFLR.
3989  */
3990 struct ALT_I2C_RXFLR_s
3991 {
3992  const uint32_t rxflr : 7; /* Receive FIFO Level Bit */
3993  uint32_t : 25; /* *UNDEFINED* */
3994 };
3995 
3996 /* The typedef declaration for register ALT_I2C_RXFLR. */
3997 typedef volatile struct ALT_I2C_RXFLR_s ALT_I2C_RXFLR_t;
3998 #endif /* __ASSEMBLY__ */
3999 
4000 /* The byte offset of the ALT_I2C_RXFLR register from the beginning of the component. */
4001 #define ALT_I2C_RXFLR_OFST 0x78
4002 /* The address of the ALT_I2C_RXFLR register. */
4003 #define ALT_I2C_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RXFLR_OFST))
4004 
4005 /*
4006  * Register : SDA Hold Register - ic_sda_hold
4007  *
4008  * This register controls the amount of time delay (in terms of number of l4_sp_clk
4009  * clock periods) introduced in the falling edge of SCL, relative to SDA changing,
4010  * when I2C services a read request in a slave-transmitter operation. The relevant
4011  * I2C requirement is thd:DAT as detailed in the I2C Bus Specification.
4012  *
4013  * Register Layout
4014  *
4015  * Bits | Access | Reset | Description
4016  * :--------|:-------|:------|:-------------
4017  * [15:0] | RW | 0x1 | SDA Hold Bit
4018  * [31:16] | ??? | 0x0 | *UNDEFINED*
4019  *
4020  */
4021 /*
4022  * Field : SDA Hold Bit - ic_sda_hold
4023  *
4024  * Program to a minimum 0f 300ns.
4025  *
4026  * Field Access Macros:
4027  *
4028  */
4029 /* The Least Significant Bit (LSB) position of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */
4030 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_LSB 0
4031 /* The Most Significant Bit (MSB) position of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */
4032 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_MSB 15
4033 /* The width in bits of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */
4034 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_WIDTH 16
4035 /* The mask used to set the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value. */
4036 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET_MSK 0x0000ffff
4037 /* The mask used to clear the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value. */
4038 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_CLR_MSK 0xffff0000
4039 /* The reset value of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */
4040 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_RESET 0x1
4041 /* Extracts the ALT_I2C_SDA_HOLD_IC_SDA_HOLD field value from a register. */
4042 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_GET(value) (((value) & 0x0000ffff) >> 0)
4043 /* Produces a ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value suitable for setting the register. */
4044 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET(value) (((value) << 0) & 0x0000ffff)
4045 
4046 #ifndef __ASSEMBLY__
4047 /*
4048  * WARNING: The C register and register group struct declarations are provided for
4049  * convenience and illustrative purposes. They should, however, be used with
4050  * caution as the C language standard provides no guarantees about the alignment or
4051  * atomicity of device memory accesses. The recommended practice for writing
4052  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4053  * alt_write_word() functions.
4054  *
4055  * The struct declaration for register ALT_I2C_SDA_HOLD.
4056  */
4057 struct ALT_I2C_SDA_HOLD_s
4058 {
4059  uint32_t ic_sda_hold : 16; /* SDA Hold Bit */
4060  uint32_t : 16; /* *UNDEFINED* */
4061 };
4062 
4063 /* The typedef declaration for register ALT_I2C_SDA_HOLD. */
4064 typedef volatile struct ALT_I2C_SDA_HOLD_s ALT_I2C_SDA_HOLD_t;
4065 #endif /* __ASSEMBLY__ */
4066 
4067 /* The byte offset of the ALT_I2C_SDA_HOLD register from the beginning of the component. */
4068 #define ALT_I2C_SDA_HOLD_OFST 0x7c
4069 /* The address of the ALT_I2C_SDA_HOLD register. */
4070 #define ALT_I2C_SDA_HOLD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_HOLD_OFST))
4071 
4072 /*
4073  * Register : Transmit Abort Source Register - ic_tx_abrt_source
4074  *
4075  * This register has 16 bits that indicate the source of the TX_ABRT bit. Except
4076  * for Bit 9, this register is cleared whenever the ic_clr_tx_abrt register or the
4077  * ic_clr_intr register is read. To clear Bit 9, the source of the
4078  * abrt_sbyte_norstrt must be fixed first; RESTART must be enabled (ic_con[5]=1),
4079  * the special bit must be cleared (ic_tar[11]), or the gc_or_start bit must be
4080  * cleared (ic_tar[10]). Once the source of the abrt_sbyte_norstrt is fixed, then
4081  * this bit can be cleared in the same manner as other bits in this register. If
4082  * the source of the abrt_sbyte_norstrt is not fixed before attempting to clear
4083  * this bit, Bit 9 clears for one cycle and is then re-asserted.
4084  *
4085  * Register Layout
4086  *
4087  * Bits | Access | Reset | Description
4088  * :--------|:-------|:------|:-----------------------------------
4089  * [0] | RW | 0x0 | Master Abort 7 Bit Address
4090  * [1] | RW | 0x0 | Master Abort 10 Bit Address Byte 1
4091  * [2] | RW | 0x0 | Master Abort 10 Bit Address Byte 2
4092  * [3] | RW | 0x0 | Master Abort TX Noack Bit
4093  * [4] | RW | 0x0 | Master Abort GC Noack Bit
4094  * [5] | RW | 0x0 | Master Abort GC Read Bit
4095  * [6] | RW | 0x0 | Master HS MC Ack
4096  * [7] | RW | 0x0 | Master Abort START Byte
4097  * [8] | RW | 0x0 | Master HS Restart Disabled
4098  * [9] | RW | 0x0 | Master Abort START No Restart
4099  * [10] | RW | 0x0 | Master Abort 10 Bit No Restart
4100  * [11] | RW | 0x0 | Master Oper Master Dis
4101  * [12] | RW | 0x0 | Master Abort Arbitration Lost
4102  * [13] | RW | 0x0 | Slave Abort Flush TXFIFO
4103  * [14] | RW | 0x0 | Slave Abort Arbitration Lost
4104  * [15] | RW | 0x0 | Slave Abort Read TX
4105  * [31:16] | ??? | 0x0 | *UNDEFINED*
4106  *
4107  */
4108 /*
4109  * Field : Master Abort 7 Bit Address - abrt_7b_addr_noack
4110  *
4111  * Master is in 7-bit addressing mode and the address sent was not acknowledged by
4112  * any slave. Role of i2c: Master-Transmitter or Master-Receiver
4113  *
4114  * Field Access Macros:
4115  *
4116  */
4117 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */
4118 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_LSB 0
4119 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */
4120 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_MSB 0
4121 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */
4122 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_WIDTH 1
4123 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value. */
4124 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET_MSK 0x00000001
4125 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value. */
4126 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_CLR_MSK 0xfffffffe
4127 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */
4128 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_RESET 0x0
4129 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK field value from a register. */
4130 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_GET(value) (((value) & 0x00000001) >> 0)
4131 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value suitable for setting the register. */
4132 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET(value) (((value) << 0) & 0x00000001)
4133 
4134 /*
4135  * Field : Master Abort 10 Bit Address Byte 1 - abrt_10addr1_noack
4136  *
4137  * Master is in 10-bit address mode and the first 10-bit address byte was not
4138  * acknowledged by any slave. Role of i2c: Master-Transmitter or Master-Receiver
4139  *
4140  * Field Access Macros:
4141  *
4142  */
4143 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */
4144 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_LSB 1
4145 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */
4146 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_MSB 1
4147 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */
4148 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_WIDTH 1
4149 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value. */
4150 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET_MSK 0x00000002
4151 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value. */
4152 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_CLR_MSK 0xfffffffd
4153 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */
4154 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_RESET 0x0
4155 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK field value from a register. */
4156 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_GET(value) (((value) & 0x00000002) >> 1)
4157 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value suitable for setting the register. */
4158 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET(value) (((value) << 1) & 0x00000002)
4159 
4160 /*
4161  * Field : Master Abort 10 Bit Address Byte 2 - abrt_10addr2_noack
4162  *
4163  * Master is in 10-bit address mode and the second address byte of the 10-bit
4164  * address was not acknowledged by any slave. Role of i2c: Master-Transmitter or
4165  * Master-Receiver
4166  *
4167  * Field Access Macros:
4168  *
4169  */
4170 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */
4171 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_LSB 2
4172 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */
4173 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_MSB 2
4174 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */
4175 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_WIDTH 1
4176 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value. */
4177 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET_MSK 0x00000004
4178 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value. */
4179 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_CLR_MSK 0xfffffffb
4180 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */
4181 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_RESET 0x0
4182 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK field value from a register. */
4183 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_GET(value) (((value) & 0x00000004) >> 2)
4184 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value suitable for setting the register. */
4185 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET(value) (((value) << 2) & 0x00000004)
4186 
4187 /*
4188  * Field : Master Abort TX Noack Bit - abrt_txdata_noack
4189  *
4190  * This is a master-mode only bit. Master has received an acknowledgement for the
4191  * address, but when it sent data byte(s) following the address, it did not receive
4192  * an acknowledge from the remote slave(s). Role of i2c: Master-Transmitter
4193  *
4194  * Field Access Macros:
4195  *
4196  */
4197 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */
4198 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_LSB 3
4199 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */
4200 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_MSB 3
4201 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */
4202 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_WIDTH 1
4203 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value. */
4204 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET_MSK 0x00000008
4205 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value. */
4206 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_CLR_MSK 0xfffffff7
4207 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */
4208 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_RESET 0x0
4209 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK field value from a register. */
4210 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_GET(value) (((value) & 0x00000008) >> 3)
4211 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value suitable for setting the register. */
4212 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET(value) (((value) << 3) & 0x00000008)
4213 
4214 /*
4215  * Field : Master Abort GC Noack Bit - abrt_gcall_noack
4216  *
4217  * i2c in master mode sent a General Call and no slave on the bus acknowledged the
4218  * General Call. Role of i2c: Master-Transmitter
4219  *
4220  * Field Access Macros:
4221  *
4222  */
4223 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */
4224 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_LSB 4
4225 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */
4226 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_MSB 4
4227 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */
4228 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_WIDTH 1
4229 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value. */
4230 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET_MSK 0x00000010
4231 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value. */
4232 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_CLR_MSK 0xffffffef
4233 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */
4234 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_RESET 0x0
4235 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK field value from a register. */
4236 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_GET(value) (((value) & 0x00000010) >> 4)
4237 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value suitable for setting the register. */
4238 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET(value) (((value) << 4) & 0x00000010)
4239 
4240 /*
4241  * Field : Master Abort GC Read Bit - abrt_gcall_read
4242  *
4243  * i2c in master mode sent a General Call but the user programmed the byte
4244  * following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to
4245  * 1). Role of i2c: Master-Transmitter
4246  *
4247  * Field Access Macros:
4248  *
4249  */
4250 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */
4251 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_LSB 5
4252 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */
4253 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_MSB 5
4254 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */
4255 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_WIDTH 1
4256 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value. */
4257 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET_MSK 0x00000020
4258 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value. */
4259 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_CLR_MSK 0xffffffdf
4260 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */
4261 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_RESET 0x0
4262 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD field value from a register. */
4263 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_GET(value) (((value) & 0x00000020) >> 5)
4264 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value suitable for setting the register. */
4265 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET(value) (((value) << 5) & 0x00000020)
4266 
4267 /*
4268  * Field : Master HS MC Ack - abrt_hs_ackdet
4269  *
4270  * Master is in High Speed mode and the High Speed Master code was acknowledged
4271  * (wrong behavior). Role of i2c: Master
4272  *
4273  * Field Access Macros:
4274  *
4275  */
4276 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */
4277 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_LSB 6
4278 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */
4279 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_MSB 6
4280 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */
4281 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_WIDTH 1
4282 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value. */
4283 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET_MSK 0x00000040
4284 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value. */
4285 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_CLR_MSK 0xffffffbf
4286 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */
4287 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_RESET 0x0
4288 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET field value from a register. */
4289 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_GET(value) (((value) & 0x00000040) >> 6)
4290 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value suitable for setting the register. */
4291 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET(value) (((value) << 6) & 0x00000040)
4292 
4293 /*
4294  * Field : Master Abort START Byte - abrt_sbyte_ackdet
4295  *
4296  * Master has sent a START Byte and the START Byte was acknowledged (wrong
4297  * behavior). Role of i2c: Master
4298  *
4299  * Field Access Macros:
4300  *
4301  */
4302 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */
4303 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_LSB 7
4304 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */
4305 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_MSB 7
4306 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */
4307 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_WIDTH 1
4308 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value. */
4309 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET_MSK 0x00000080
4310 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value. */
4311 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_CLR_MSK 0xffffff7f
4312 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */
4313 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_RESET 0x0
4314 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET field value from a register. */
4315 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_GET(value) (((value) & 0x00000080) >> 7)
4316 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value suitable for setting the register. */
4317 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET(value) (((value) << 7) & 0x00000080)
4318 
4319 /*
4320  * Field : Master HS Restart Disabled - abrt_hs_norstrt
4321  *
4322  * The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is
4323  * trying to use the master to transfer data in High Speed mode. Role of i2c:
4324  * Master-Transmitter or Master-Receiver
4325  *
4326  * Field Access Macros:
4327  *
4328  */
4329 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */
4330 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_LSB 8
4331 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */
4332 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_MSB 8
4333 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */
4334 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_WIDTH 1
4335 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value. */
4336 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET_MSK 0x00000100
4337 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value. */
4338 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_CLR_MSK 0xfffffeff
4339 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */
4340 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_RESET 0x0
4341 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT field value from a register. */
4342 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_GET(value) (((value) & 0x00000100) >> 8)
4343 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value suitable for setting the register. */
4344 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET(value) (((value) << 8) & 0x00000100)
4345 
4346 /*
4347  * Field : Master Abort START No Restart - abrt_sbyte_norstrt
4348  *
4349  * To clear Bit 9, the source of then abrt_sbyte_norstrt must be fixed first;
4350  * restart must be enabled (ic_con[5]=1), the SPECIAL bit must be cleared
4351  * (ic_tar[11]), or the GC_OR_START bit must be cleared (ic_tar[10]). Once the
4352  * source of the abrt_sbyte_norstrt is fixed, then this bit can be cleared in the
4353  * same manner as other bits in this register. If the source of the
4354  * abrt_sbyte_norstrt is not fixed before attempting to clear this bit, bit 9
4355  * clears for one cycle and then gets reasserted. 1: The restart is disabled
4356  * (IC_RESTART_EN bit (ic_con[5]) =0) and the user is trying to send a START Byte.
4357  * Role of I2C: Master
4358  *
4359  * Field Access Macros:
4360  *
4361  */
4362 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */
4363 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_LSB 9
4364 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */
4365 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_MSB 9
4366 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */
4367 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_WIDTH 1
4368 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value. */
4369 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET_MSK 0x00000200
4370 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value. */
4371 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_CLR_MSK 0xfffffdff
4372 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */
4373 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_RESET 0x0
4374 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT field value from a register. */
4375 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_GET(value) (((value) & 0x00000200) >> 9)
4376 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value suitable for setting the register. */
4377 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET(value) (((value) << 9) & 0x00000200)
4378 
4379 /*
4380  * Field : Master Abort 10 Bit No Restart - abrt_10b_rd_norstrt
4381  *
4382  * The restart is disabled (ic_restart_en bit (ic_con[5]) =0) and the master sends
4383  * a read command in 10-bit addressing mode. Role of I2C: Master-Receiver
4384  *
4385  * Field Access Macros:
4386  *
4387  */
4388 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */
4389 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_LSB 10
4390 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */
4391 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_MSB 10
4392 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */
4393 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_WIDTH 1
4394 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value. */
4395 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET_MSK 0x00000400
4396 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value. */
4397 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_CLR_MSK 0xfffffbff
4398 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */
4399 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_RESET 0x0
4400 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT field value from a register. */
4401 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_GET(value) (((value) & 0x00000400) >> 10)
4402 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value suitable for setting the register. */
4403 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET(value) (((value) << 10) & 0x00000400)
4404 
4405 /*
4406  * Field : Master Oper Master Dis - abrt_master_dis
4407  *
4408  * User tries to initiate a Master operation with the Master mode disabled. Role of
4409  * I2C: Master-Transmitter or Master-Receiver
4410  *
4411  * Field Access Macros:
4412  *
4413  */
4414 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */
4415 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_LSB 11
4416 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */
4417 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_MSB 11
4418 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */
4419 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_WIDTH 1
4420 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value. */
4421 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET_MSK 0x00000800
4422 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value. */
4423 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_CLR_MSK 0xfffff7ff
4424 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */
4425 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_RESET 0x0
4426 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS field value from a register. */
4427 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_GET(value) (((value) & 0x00000800) >> 11)
4428 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value suitable for setting the register. */
4429 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET(value) (((value) << 11) & 0x00000800)
4430 
4431 /*
4432  * Field : Master Abort Arbitration Lost - arb_lost
4433  *
4434  * Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the
4435  * slave transmitter has lost arbitration. Note: I2C can be both master and slave
4436  * at the same time. Role of i2c: Master-Transmitter or Slave-Transmitter
4437  *
4438  * Field Access Macros:
4439  *
4440  */
4441 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */
4442 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_LSB 12
4443 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */
4444 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_MSB 12
4445 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */
4446 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_WIDTH 1
4447 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value. */
4448 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET_MSK 0x00001000
4449 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value. */
4450 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_CLR_MSK 0xffffefff
4451 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */
4452 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_RESET 0x0
4453 /* Extracts the ALT_I2C_TX_ABRT_SRC_ARB_LOST field value from a register. */
4454 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_GET(value) (((value) & 0x00001000) >> 12)
4455 /* Produces a ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value suitable for setting the register. */
4456 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET(value) (((value) << 12) & 0x00001000)
4457 
4458 /*
4459  * Field : Slave Abort Flush TXFIFO - abrt_slvflush_txfifo
4460  *
4461  * Slave has received a read command and some data exists in the TX FIFO so the
4462  * slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Role of I2C:
4463  * Slave-Transmitter
4464  *
4465  * Field Access Macros:
4466  *
4467  */
4468 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */
4469 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_LSB 13
4470 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */
4471 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_MSB 13
4472 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */
4473 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_WIDTH 1
4474 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value. */
4475 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET_MSK 0x00002000
4476 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value. */
4477 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_CLR_MSK 0xffffdfff
4478 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */
4479 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_RESET 0x0
4480 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO field value from a register. */
4481 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_GET(value) (((value) & 0x00002000) >> 13)
4482 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value suitable for setting the register. */
4483 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET(value) (((value) << 13) & 0x00002000)
4484 
4485 /*
4486  * Field : Slave Abort Arbitration Lost - abrt_slv_arblost
4487  *
4488  * Slave lost the bus while transmitting data to a remote master.
4489  * IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never
4490  * 'owns' the bus, something could go wrong on the bus. This is a fail safe check.
4491  * For instance, during a data transmission at the low-to-high transition of SCL,
4492  * if what is on the data bus is not what is supposed to be transmitted, then i2c
4493  * no longer own the bus. Role of I2C: Slave-Transmitter
4494  *
4495  * Field Access Macros:
4496  *
4497  */
4498 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */
4499 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_LSB 14
4500 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */
4501 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_MSB 14
4502 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */
4503 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_WIDTH 1
4504 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value. */
4505 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET_MSK 0x00004000
4506 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value. */
4507 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_CLR_MSK 0xffffbfff
4508 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */
4509 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_RESET 0x0
4510 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST field value from a register. */
4511 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_GET(value) (((value) & 0x00004000) >> 14)
4512 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value suitable for setting the register. */
4513 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET(value) (((value) << 14) & 0x00004000)
4514 
4515 /*
4516  * Field : Slave Abort Read TX - abrt_slvrd_intx
4517  *
4518  * When the processor side responds to a slave mode request for data to be
4519  * transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD
4520  * register. Role of I2C: Slave-Transmitter
4521  *
4522  * Field Access Macros:
4523  *
4524  */
4525 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */
4526 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_LSB 15
4527 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */
4528 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_MSB 15
4529 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */
4530 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_WIDTH 1
4531 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value. */
4532 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET_MSK 0x00008000
4533 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value. */
4534 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_CLR_MSK 0xffff7fff
4535 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */
4536 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_RESET 0x0
4537 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX field value from a register. */
4538 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_GET(value) (((value) & 0x00008000) >> 15)
4539 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value suitable for setting the register. */
4540 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET(value) (((value) << 15) & 0x00008000)
4541 
4542 #ifndef __ASSEMBLY__
4543 /*
4544  * WARNING: The C register and register group struct declarations are provided for
4545  * convenience and illustrative purposes. They should, however, be used with
4546  * caution as the C language standard provides no guarantees about the alignment or
4547  * atomicity of device memory accesses. The recommended practice for writing
4548  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4549  * alt_write_word() functions.
4550  *
4551  * The struct declaration for register ALT_I2C_TX_ABRT_SRC.
4552  */
4553 struct ALT_I2C_TX_ABRT_SRC_s
4554 {
4555  uint32_t abrt_7b_addr_noack : 1; /* Master Abort 7 Bit Address */
4556  uint32_t abrt_10addr1_noack : 1; /* Master Abort 10 Bit Address Byte 1 */
4557  uint32_t abrt_10addr2_noack : 1; /* Master Abort 10 Bit Address Byte 2 */
4558  uint32_t abrt_txdata_noack : 1; /* Master Abort TX Noack Bit */
4559  uint32_t abrt_gcall_noack : 1; /* Master Abort GC Noack Bit */
4560  uint32_t abrt_gcall_read : 1; /* Master Abort GC Read Bit */
4561  uint32_t abrt_hs_ackdet : 1; /* Master HS MC Ack */
4562  uint32_t abrt_sbyte_ackdet : 1; /* Master Abort START Byte */
4563  uint32_t abrt_hs_norstrt : 1; /* Master HS Restart Disabled */
4564  uint32_t abrt_sbyte_norstrt : 1; /* Master Abort START No Restart */
4565  uint32_t abrt_10b_rd_norstrt : 1; /* Master Abort 10 Bit No Restart */
4566  uint32_t abrt_master_dis : 1; /* Master Oper Master Dis */
4567  uint32_t arb_lost : 1; /* Master Abort Arbitration Lost */
4568  uint32_t abrt_slvflush_txfifo : 1; /* Slave Abort Flush TXFIFO */
4569  uint32_t abrt_slv_arblost : 1; /* Slave Abort Arbitration Lost */
4570  uint32_t abrt_slvrd_intx : 1; /* Slave Abort Read TX */
4571  uint32_t : 16; /* *UNDEFINED* */
4572 };
4573 
4574 /* The typedef declaration for register ALT_I2C_TX_ABRT_SRC. */
4575 typedef volatile struct ALT_I2C_TX_ABRT_SRC_s ALT_I2C_TX_ABRT_SRC_t;
4576 #endif /* __ASSEMBLY__ */
4577 
4578 /* The byte offset of the ALT_I2C_TX_ABRT_SRC register from the beginning of the component. */
4579 #define ALT_I2C_TX_ABRT_SRC_OFST 0x80
4580 /* The address of the ALT_I2C_TX_ABRT_SRC register. */
4581 #define ALT_I2C_TX_ABRT_SRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_ABRT_SRC_OFST))
4582 
4583 /*
4584  * Register : Generate Slave Data NACK - ic_slv_data_nack_only
4585  *
4586  * The register is used to generate a NACK for the data part of a transfer when i2c
4587  * is acting as a slave-receiver.
4588  *
4589  * Register Layout
4590  *
4591  * Bits | Access | Reset | Description
4592  * :-------|:-------|:------|:------------------
4593  * [0] | RW | 0x0 | Generate Nack Bit
4594  * [31:1] | ??? | 0x0 | *UNDEFINED*
4595  *
4596  */
4597 /*
4598  * Field : Generate Nack Bit - nack
4599  *
4600  * This Bit control Nack generation
4601  *
4602  * Field Enumeration Values:
4603  *
4604  * Enum | Value | Description
4605  * :---------------------------------------------|:------|:--------------------------------------
4606  * ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_AFTERDBYTE | 0x1 | Generate NACK after data byte receive
4607  * ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_NORM | 0x0 | Generate NACK/ACK normally
4608  *
4609  * Field Access Macros:
4610  *
4611  */
4612 /*
4613  * Enumerated value for register field ALT_I2C_SLV_DATA_NACK_ONLY_NACK
4614  *
4615  * Generate NACK after data byte receive
4616  */
4617 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_AFTERDBYTE 0x1
4618 /*
4619  * Enumerated value for register field ALT_I2C_SLV_DATA_NACK_ONLY_NACK
4620  *
4621  * Generate NACK/ACK normally
4622  */
4623 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_NORM 0x0
4624 
4625 /* The Least Significant Bit (LSB) position of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */
4626 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_LSB 0
4627 /* The Most Significant Bit (MSB) position of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */
4628 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_MSB 0
4629 /* The width in bits of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */
4630 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_WIDTH 1
4631 /* The mask used to set the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value. */
4632 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET_MSK 0x00000001
4633 /* The mask used to clear the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value. */
4634 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_CLR_MSK 0xfffffffe
4635 /* The reset value of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */
4636 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_RESET 0x0
4637 /* Extracts the ALT_I2C_SLV_DATA_NACK_ONLY_NACK field value from a register. */
4638 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_GET(value) (((value) & 0x00000001) >> 0)
4639 /* Produces a ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value suitable for setting the register. */
4640 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET(value) (((value) << 0) & 0x00000001)
4641 
4642 #ifndef __ASSEMBLY__
4643 /*
4644  * WARNING: The C register and register group struct declarations are provided for
4645  * convenience and illustrative purposes. They should, however, be used with
4646  * caution as the C language standard provides no guarantees about the alignment or
4647  * atomicity of device memory accesses. The recommended practice for writing
4648  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4649  * alt_write_word() functions.
4650  *
4651  * The struct declaration for register ALT_I2C_SLV_DATA_NACK_ONLY.
4652  */
4653 struct ALT_I2C_SLV_DATA_NACK_ONLY_s
4654 {
4655  uint32_t nack : 1; /* Generate Nack Bit */
4656  uint32_t : 31; /* *UNDEFINED* */
4657 };
4658 
4659 /* The typedef declaration for register ALT_I2C_SLV_DATA_NACK_ONLY. */
4660 typedef volatile struct ALT_I2C_SLV_DATA_NACK_ONLY_s ALT_I2C_SLV_DATA_NACK_ONLY_t;
4661 #endif /* __ASSEMBLY__ */
4662 
4663 /* The byte offset of the ALT_I2C_SLV_DATA_NACK_ONLY register from the beginning of the component. */
4664 #define ALT_I2C_SLV_DATA_NACK_ONLY_OFST 0x84
4665 /* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register. */
4666 #define ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SLV_DATA_NACK_ONLY_OFST))
4667 
4668 /*
4669  * Register : DMA Control - ic_dma_cr
4670  *
4671  * The register is used to enable the DMA Controller interface operation. There is
4672  * a separate bit for transmit and receive. This can be programmed regardless of
4673  * the state of IC_ENABLE.
4674  *
4675  * Register Layout
4676  *
4677  * Bits | Access | Reset | Description
4678  * :-------|:-------|:------|:------------------------
4679  * [0] | RW | 0x0 | Receive DMA Enable Bit
4680  * [1] | RW | 0x0 | Transmit DMA Enable Bit
4681  * [31:2] | ??? | 0x0 | *UNDEFINED*
4682  *
4683  */
4684 /*
4685  * Field : Receive DMA Enable Bit - rdmae
4686  *
4687  * This bit enables/disables the receive FIFO DMA channel.
4688  *
4689  * Field Enumeration Values:
4690  *
4691  * Enum | Value | Description
4692  * :---------------------------|:------|:--------------------
4693  * ALT_I2C_DMA_CR_RDMAE_E_DIS | 0x0 | Receive DMA disable
4694  * ALT_I2C_DMA_CR_RDMAE_E_EN | 0x1 | Receive DMA enabled
4695  *
4696  * Field Access Macros:
4697  *
4698  */
4699 /*
4700  * Enumerated value for register field ALT_I2C_DMA_CR_RDMAE
4701  *
4702  * Receive DMA disable
4703  */
4704 #define ALT_I2C_DMA_CR_RDMAE_E_DIS 0x0
4705 /*
4706  * Enumerated value for register field ALT_I2C_DMA_CR_RDMAE
4707  *
4708  * Receive DMA enabled
4709  */
4710 #define ALT_I2C_DMA_CR_RDMAE_E_EN 0x1
4711 
4712 /* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_CR_RDMAE register field. */
4713 #define ALT_I2C_DMA_CR_RDMAE_LSB 0
4714 /* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_CR_RDMAE register field. */
4715 #define ALT_I2C_DMA_CR_RDMAE_MSB 0
4716 /* The width in bits of the ALT_I2C_DMA_CR_RDMAE register field. */
4717 #define ALT_I2C_DMA_CR_RDMAE_WIDTH 1
4718 /* The mask used to set the ALT_I2C_DMA_CR_RDMAE register field value. */
4719 #define ALT_I2C_DMA_CR_RDMAE_SET_MSK 0x00000001
4720 /* The mask used to clear the ALT_I2C_DMA_CR_RDMAE register field value. */
4721 #define ALT_I2C_DMA_CR_RDMAE_CLR_MSK 0xfffffffe
4722 /* The reset value of the ALT_I2C_DMA_CR_RDMAE register field. */
4723 #define ALT_I2C_DMA_CR_RDMAE_RESET 0x0
4724 /* Extracts the ALT_I2C_DMA_CR_RDMAE field value from a register. */
4725 #define ALT_I2C_DMA_CR_RDMAE_GET(value) (((value) & 0x00000001) >> 0)
4726 /* Produces a ALT_I2C_DMA_CR_RDMAE register field value suitable for setting the register. */
4727 #define ALT_I2C_DMA_CR_RDMAE_SET(value) (((value) << 0) & 0x00000001)
4728 
4729 /*
4730  * Field : Transmit DMA Enable Bit - tdmae
4731  *
4732  * This bit enables/disables the transmit FIFO DMA channel.
4733  *
4734  * Field Enumeration Values:
4735  *
4736  * Enum | Value | Description
4737  * :---------------------------|:------|:---------------------
4738  * ALT_I2C_DMA_CR_TDMAE_E_DIS | 0x0 | Transmit DMA disable
4739  * ALT_I2C_DMA_CR_TDMAE_E_EN | 0x1 | Transmit DMA enabled
4740  *
4741  * Field Access Macros:
4742  *
4743  */
4744 /*
4745  * Enumerated value for register field ALT_I2C_DMA_CR_TDMAE
4746  *
4747  * Transmit DMA disable
4748  */
4749 #define ALT_I2C_DMA_CR_TDMAE_E_DIS 0x0
4750 /*
4751  * Enumerated value for register field ALT_I2C_DMA_CR_TDMAE
4752  *
4753  * Transmit DMA enabled
4754  */
4755 #define ALT_I2C_DMA_CR_TDMAE_E_EN 0x1
4756 
4757 /* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_CR_TDMAE register field. */
4758 #define ALT_I2C_DMA_CR_TDMAE_LSB 1
4759 /* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_CR_TDMAE register field. */
4760 #define ALT_I2C_DMA_CR_TDMAE_MSB 1
4761 /* The width in bits of the ALT_I2C_DMA_CR_TDMAE register field. */
4762 #define ALT_I2C_DMA_CR_TDMAE_WIDTH 1
4763 /* The mask used to set the ALT_I2C_DMA_CR_TDMAE register field value. */
4764 #define ALT_I2C_DMA_CR_TDMAE_SET_MSK 0x00000002
4765 /* The mask used to clear the ALT_I2C_DMA_CR_TDMAE register field value. */
4766 #define ALT_I2C_DMA_CR_TDMAE_CLR_MSK 0xfffffffd
4767 /* The reset value of the ALT_I2C_DMA_CR_TDMAE register field. */
4768 #define ALT_I2C_DMA_CR_TDMAE_RESET 0x0
4769 /* Extracts the ALT_I2C_DMA_CR_TDMAE field value from a register. */
4770 #define ALT_I2C_DMA_CR_TDMAE_GET(value) (((value) & 0x00000002) >> 1)
4771 /* Produces a ALT_I2C_DMA_CR_TDMAE register field value suitable for setting the register. */
4772 #define ALT_I2C_DMA_CR_TDMAE_SET(value) (((value) << 1) & 0x00000002)
4773 
4774 #ifndef __ASSEMBLY__
4775 /*
4776  * WARNING: The C register and register group struct declarations are provided for
4777  * convenience and illustrative purposes. They should, however, be used with
4778  * caution as the C language standard provides no guarantees about the alignment or
4779  * atomicity of device memory accesses. The recommended practice for writing
4780  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4781  * alt_write_word() functions.
4782  *
4783  * The struct declaration for register ALT_I2C_DMA_CR.
4784  */
4785 struct ALT_I2C_DMA_CR_s
4786 {
4787  uint32_t rdmae : 1; /* Receive DMA Enable Bit */
4788  uint32_t tdmae : 1; /* Transmit DMA Enable Bit */
4789  uint32_t : 30; /* *UNDEFINED* */
4790 };
4791 
4792 /* The typedef declaration for register ALT_I2C_DMA_CR. */
4793 typedef volatile struct ALT_I2C_DMA_CR_s ALT_I2C_DMA_CR_t;
4794 #endif /* __ASSEMBLY__ */
4795 
4796 /* The byte offset of the ALT_I2C_DMA_CR register from the beginning of the component. */
4797 #define ALT_I2C_DMA_CR_OFST 0x88
4798 /* The address of the ALT_I2C_DMA_CR register. */
4799 #define ALT_I2C_DMA_CR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_CR_OFST))
4800 
4801 /*
4802  * Register : DMA Transmit Data Level - ic_dma_tdlr
4803  *
4804  * This register supports DMA Transmit Operation.
4805  *
4806  * Register Layout
4807  *
4808  * Bits | Access | Reset | Description
4809  * :-------|:-------|:------|:----------------------------
4810  * [5:0] | RW | 0x0 | DMA Transmit Data Level Bit
4811  * [31:6] | ??? | 0x0 | *UNDEFINED*
4812  *
4813  */
4814 /*
4815  * Field : DMA Transmit Data Level Bit - dmatdl
4816  *
4817  * This bit field controls the level at which a DMA request is made by the transmit
4818  * logic. It is equal to the watermark level; that is, the i2c_dma_tx_req signal is
4819  * generated when the number of valid data entries in the transmit FIFO is equal to
4820  * or below this field value, and TDMAE = 1.
4821  *
4822  * Field Access Macros:
4823  *
4824  */
4825 /* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_TDLR_DMATDL register field. */
4826 #define ALT_I2C_DMA_TDLR_DMATDL_LSB 0
4827 /* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_TDLR_DMATDL register field. */
4828 #define ALT_I2C_DMA_TDLR_DMATDL_MSB 5
4829 /* The width in bits of the ALT_I2C_DMA_TDLR_DMATDL register field. */
4830 #define ALT_I2C_DMA_TDLR_DMATDL_WIDTH 6
4831 /* The mask used to set the ALT_I2C_DMA_TDLR_DMATDL register field value. */
4832 #define ALT_I2C_DMA_TDLR_DMATDL_SET_MSK 0x0000003f
4833 /* The mask used to clear the ALT_I2C_DMA_TDLR_DMATDL register field value. */
4834 #define ALT_I2C_DMA_TDLR_DMATDL_CLR_MSK 0xffffffc0
4835 /* The reset value of the ALT_I2C_DMA_TDLR_DMATDL register field. */
4836 #define ALT_I2C_DMA_TDLR_DMATDL_RESET 0x0
4837 /* Extracts the ALT_I2C_DMA_TDLR_DMATDL field value from a register. */
4838 #define ALT_I2C_DMA_TDLR_DMATDL_GET(value) (((value) & 0x0000003f) >> 0)
4839 /* Produces a ALT_I2C_DMA_TDLR_DMATDL register field value suitable for setting the register. */
4840 #define ALT_I2C_DMA_TDLR_DMATDL_SET(value) (((value) << 0) & 0x0000003f)
4841 
4842 #ifndef __ASSEMBLY__
4843 /*
4844  * WARNING: The C register and register group struct declarations are provided for
4845  * convenience and illustrative purposes. They should, however, be used with
4846  * caution as the C language standard provides no guarantees about the alignment or
4847  * atomicity of device memory accesses. The recommended practice for writing
4848  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4849  * alt_write_word() functions.
4850  *
4851  * The struct declaration for register ALT_I2C_DMA_TDLR.
4852  */
4853 struct ALT_I2C_DMA_TDLR_s
4854 {
4855  uint32_t dmatdl : 6; /* DMA Transmit Data Level Bit */
4856  uint32_t : 26; /* *UNDEFINED* */
4857 };
4858 
4859 /* The typedef declaration for register ALT_I2C_DMA_TDLR. */
4860 typedef volatile struct ALT_I2C_DMA_TDLR_s ALT_I2C_DMA_TDLR_t;
4861 #endif /* __ASSEMBLY__ */
4862 
4863 /* The byte offset of the ALT_I2C_DMA_TDLR register from the beginning of the component. */
4864 #define ALT_I2C_DMA_TDLR_OFST 0x8c
4865 /* The address of the ALT_I2C_DMA_TDLR register. */
4866 #define ALT_I2C_DMA_TDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_TDLR_OFST))
4867 
4868 /*
4869  * Register : Receive Data Level - ic_dma_rdlr
4870  *
4871  * DMA Control Signals Interface.
4872  *
4873  * Register Layout
4874  *
4875  * Bits | Access | Reset | Description
4876  * :-------|:-------|:------|:------------------------
4877  * [5:0] | RW | 0x0 | Receive Data Level Bits
4878  * [31:6] | ??? | 0x0 | *UNDEFINED*
4879  *
4880  */
4881 /*
4882  * Field : Receive Data Level Bits - dmardl
4883  *
4884  * This bit field controls the level at which a DMA request is made by the receive
4885  * logic. The watermark level \= DMARDL+1; that is, dma_rx_req is generated when
4886  * the number of valid data entries in the receive FIFO is equal to or more than
4887  * this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then
4888  * dma_rx_req is asserted when or more data entries are present in the receive
4889  * FIFO.
4890  *
4891  * Field Access Macros:
4892  *
4893  */
4894 /* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_RDLR_DMARDL register field. */
4895 #define ALT_I2C_DMA_RDLR_DMARDL_LSB 0
4896 /* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_RDLR_DMARDL register field. */
4897 #define ALT_I2C_DMA_RDLR_DMARDL_MSB 5
4898 /* The width in bits of the ALT_I2C_DMA_RDLR_DMARDL register field. */
4899 #define ALT_I2C_DMA_RDLR_DMARDL_WIDTH 6
4900 /* The mask used to set the ALT_I2C_DMA_RDLR_DMARDL register field value. */
4901 #define ALT_I2C_DMA_RDLR_DMARDL_SET_MSK 0x0000003f
4902 /* The mask used to clear the ALT_I2C_DMA_RDLR_DMARDL register field value. */
4903 #define ALT_I2C_DMA_RDLR_DMARDL_CLR_MSK 0xffffffc0
4904 /* The reset value of the ALT_I2C_DMA_RDLR_DMARDL register field. */
4905 #define ALT_I2C_DMA_RDLR_DMARDL_RESET 0x0
4906 /* Extracts the ALT_I2C_DMA_RDLR_DMARDL field value from a register. */
4907 #define ALT_I2C_DMA_RDLR_DMARDL_GET(value) (((value) & 0x0000003f) >> 0)
4908 /* Produces a ALT_I2C_DMA_RDLR_DMARDL register field value suitable for setting the register. */
4909 #define ALT_I2C_DMA_RDLR_DMARDL_SET(value) (((value) << 0) & 0x0000003f)
4910 
4911 #ifndef __ASSEMBLY__
4912 /*
4913  * WARNING: The C register and register group struct declarations are provided for
4914  * convenience and illustrative purposes. They should, however, be used with
4915  * caution as the C language standard provides no guarantees about the alignment or
4916  * atomicity of device memory accesses. The recommended practice for writing
4917  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4918  * alt_write_word() functions.
4919  *
4920  * The struct declaration for register ALT_I2C_DMA_RDLR.
4921  */
4922 struct ALT_I2C_DMA_RDLR_s
4923 {
4924  uint32_t dmardl : 6; /* Receive Data Level Bits */
4925  uint32_t : 26; /* *UNDEFINED* */
4926 };
4927 
4928 /* The typedef declaration for register ALT_I2C_DMA_RDLR. */
4929 typedef volatile struct ALT_I2C_DMA_RDLR_s ALT_I2C_DMA_RDLR_t;
4930 #endif /* __ASSEMBLY__ */
4931 
4932 /* The byte offset of the ALT_I2C_DMA_RDLR register from the beginning of the component. */
4933 #define ALT_I2C_DMA_RDLR_OFST 0x90
4934 /* The address of the ALT_I2C_DMA_RDLR register. */
4935 #define ALT_I2C_DMA_RDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_RDLR_OFST))
4936 
4937 /*
4938  * Register : SDA Setup Register - ic_sda_setup
4939  *
4940  * This register controls the amount of time delay (in terms of number of l4_sp_clk
4941  * clock periods) introduced in the rising edge of SCL relative to SDA changing by
4942  * holding SCL low when I2C services a read request while operating as a slave-
4943  * transmitter. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the
4944  * I2C Bus Specification. This register must be programmed with a value equal to or
4945  * greater than 2.
4946  *
4947  * Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) *
4948  * (l4_sp_clk)], so if the user requires 10 l4_sp_clk periods of setup time, they
4949  * should program a value of 11. The IC_SDA_SETUP register is only used by the I2C
4950  * when operating as a slave transmitter.
4951  *
4952  * Register Layout
4953  *
4954  * Bits | Access | Reset | Description
4955  * :-------|:-------|:------|:----------------
4956  * [7:0] | RW | 0x64 | SDA Setup Value
4957  * [31:8] | ??? | 0x0 | *UNDEFINED*
4958  *
4959  */
4960 /*
4961  * Field : SDA Setup Value - sda_setup
4962  *
4963  * It is recommended that if the required delay is 1000ns, then for an l4_sp_clk
4964  * frequency of 10 MHz, ic_sda_setup should be programmed to a value of 11.
4965  *
4966  * Field Access Macros:
4967  *
4968  */
4969 /* The Least Significant Bit (LSB) position of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */
4970 #define ALT_I2C_SDA_SETUP_SDA_SETUP_LSB 0
4971 /* The Most Significant Bit (MSB) position of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */
4972 #define ALT_I2C_SDA_SETUP_SDA_SETUP_MSB 7
4973 /* The width in bits of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */
4974 #define ALT_I2C_SDA_SETUP_SDA_SETUP_WIDTH 8
4975 /* The mask used to set the ALT_I2C_SDA_SETUP_SDA_SETUP register field value. */
4976 #define ALT_I2C_SDA_SETUP_SDA_SETUP_SET_MSK 0x000000ff
4977 /* The mask used to clear the ALT_I2C_SDA_SETUP_SDA_SETUP register field value. */
4978 #define ALT_I2C_SDA_SETUP_SDA_SETUP_CLR_MSK 0xffffff00
4979 /* The reset value of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */
4980 #define ALT_I2C_SDA_SETUP_SDA_SETUP_RESET 0x64
4981 /* Extracts the ALT_I2C_SDA_SETUP_SDA_SETUP field value from a register. */
4982 #define ALT_I2C_SDA_SETUP_SDA_SETUP_GET(value) (((value) & 0x000000ff) >> 0)
4983 /* Produces a ALT_I2C_SDA_SETUP_SDA_SETUP register field value suitable for setting the register. */
4984 #define ALT_I2C_SDA_SETUP_SDA_SETUP_SET(value) (((value) << 0) & 0x000000ff)
4985 
4986 #ifndef __ASSEMBLY__
4987 /*
4988  * WARNING: The C register and register group struct declarations are provided for
4989  * convenience and illustrative purposes. They should, however, be used with
4990  * caution as the C language standard provides no guarantees about the alignment or
4991  * atomicity of device memory accesses. The recommended practice for writing
4992  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4993  * alt_write_word() functions.
4994  *
4995  * The struct declaration for register ALT_I2C_SDA_SETUP.
4996  */
4997 struct ALT_I2C_SDA_SETUP_s
4998 {
4999  uint32_t sda_setup : 8; /* SDA Setup Value */
5000  uint32_t : 24; /* *UNDEFINED* */
5001 };
5002 
5003 /* The typedef declaration for register ALT_I2C_SDA_SETUP. */
5004 typedef volatile struct ALT_I2C_SDA_SETUP_s ALT_I2C_SDA_SETUP_t;
5005 #endif /* __ASSEMBLY__ */
5006 
5007 /* The byte offset of the ALT_I2C_SDA_SETUP register from the beginning of the component. */
5008 #define ALT_I2C_SDA_SETUP_OFST 0x94
5009 /* The address of the ALT_I2C_SDA_SETUP register. */
5010 #define ALT_I2C_SDA_SETUP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_SETUP_OFST))
5011 
5012 /*
5013  * Register : ACK General Call - ic_ack_general_call
5014  *
5015  * The register controls whether i2c responds with a ACK or NACK when it receives
5016  * an I2C General Call address.
5017  *
5018  * Register Layout
5019  *
5020  * Bits | Access | Reset | Description
5021  * :-------|:-------|:------|:---------------------
5022  * [0] | RW | 0x1 | ACK General Call Bit
5023  * [31:1] | ??? | 0x0 | *UNDEFINED*
5024  *
5025  */
5026 /*
5027  * Field : ACK General Call Bit - ack_gen_call
5028  *
5029  * When an ACK is asserted, (by asserting i2c_out_data) when it receives a General
5030  * call. Otherwise, i2c responds with a NACK (by negating i2c_out_data).
5031  *
5032  * Field Enumeration Values:
5033  *
5034  * Enum | Value | Description
5035  * :---------------------------------------------|:------|:-------------------------
5036  * ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_NACK | 0x0 | I2C responds with a NACK
5037  * ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ACK | 0x1 | I2C responds with an ACK
5038  *
5039  * Field Access Macros:
5040  *
5041  */
5042 /*
5043  * Enumerated value for register field ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL
5044  *
5045  * I2C responds with a NACK
5046  */
5047 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_NACK 0x0
5048 /*
5049  * Enumerated value for register field ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL
5050  *
5051  * I2C responds with an ACK
5052  */
5053 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ACK 0x1
5054 
5055 /* The Least Significant Bit (LSB) position of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */
5056 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB 0
5057 /* The Most Significant Bit (MSB) position of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */
5058 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB 0
5059 /* The width in bits of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */
5060 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_WIDTH 1
5061 /* The mask used to set the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value. */
5062 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET_MSK 0x00000001
5063 /* The mask used to clear the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value. */
5064 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_CLR_MSK 0xfffffffe
5065 /* The reset value of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */
5066 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET 0x1
5067 /* Extracts the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL field value from a register. */
5068 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0)
5069 /* Produces a ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value suitable for setting the register. */
5070 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET(value) (((value) << 0) & 0x00000001)
5071 
5072 #ifndef __ASSEMBLY__
5073 /*
5074  * WARNING: The C register and register group struct declarations are provided for
5075  * convenience and illustrative purposes. They should, however, be used with
5076  * caution as the C language standard provides no guarantees about the alignment or
5077  * atomicity of device memory accesses. The recommended practice for writing
5078  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5079  * alt_write_word() functions.
5080  *
5081  * The struct declaration for register ALT_I2C_ACK_GENERAL_CALL.
5082  */
5083 struct ALT_I2C_ACK_GENERAL_CALL_s
5084 {
5085  uint32_t ack_gen_call : 1; /* ACK General Call Bit */
5086  uint32_t : 31; /* *UNDEFINED* */
5087 };
5088 
5089 /* The typedef declaration for register ALT_I2C_ACK_GENERAL_CALL. */
5090 typedef volatile struct ALT_I2C_ACK_GENERAL_CALL_s ALT_I2C_ACK_GENERAL_CALL_t;
5091 #endif /* __ASSEMBLY__ */
5092 
5093 /* The byte offset of the ALT_I2C_ACK_GENERAL_CALL register from the beginning of the component. */
5094 #define ALT_I2C_ACK_GENERAL_CALL_OFST 0x98
5095 /* The address of the ALT_I2C_ACK_GENERAL_CALL register. */
5096 #define ALT_I2C_ACK_GENERAL_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_ACK_GENERAL_CALL_OFST))
5097 
5098 /*
5099  * Register : Enable Status Register - ic_enable_status
5100  *
5101  * This register is used to report the i2c hardware status when the IC_ENABLE
5102  * register is set from 1 to 0; that is, when i2c is disabled. If IC_ENABLE has
5103  * been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE
5104  * has been set to 0, bits 2:1 are only valid as soon as bit 0 is read as '0'.
5105  *
5106  * Note: When ic_enable has been written with '0' a delay occurs for bit 0 to be
5107  * read as '0' because disabling the i2c depends on I2C bus activities.
5108  *
5109  * Register Layout
5110  *
5111  * Bits | Access | Reset | Description
5112  * :-------|:-------|:------|:------------------------------
5113  * [0] | R | 0x0 | Enable Status Bit
5114  * [1] | R | 0x0 | Slave Disabled While Busy Bit
5115  * [2] | R | 0x0 | Slave Received Data Lost Bit
5116  * [31:3] | ??? | 0x0 | *UNDEFINED*
5117  *
5118  */
5119 /*
5120  * Field : Enable Status Bit - ic_en
5121  *
5122  * This bit always reflects the value driven on the output port ic_en. Not used in
5123  * current application. When read as 1, i2c is deemed to be in an enabled state.
5124  * When read as 0, i2c is deemed completely inactive. NOTE: The CPU can safely read
5125  * this bit anytime. When this bit is read as 0, the CPU can safely read
5126  * slv_rx_data_lost (bit 2) and slv_disabled_while_busy (bit 1).
5127  *
5128  * Field Access Macros:
5129  *
5130  */
5131 /* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_IC_EN register field. */
5132 #define ALT_I2C_EN_STAT_IC_EN_LSB 0
5133 /* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_IC_EN register field. */
5134 #define ALT_I2C_EN_STAT_IC_EN_MSB 0
5135 /* The width in bits of the ALT_I2C_EN_STAT_IC_EN register field. */
5136 #define ALT_I2C_EN_STAT_IC_EN_WIDTH 1
5137 /* The mask used to set the ALT_I2C_EN_STAT_IC_EN register field value. */
5138 #define ALT_I2C_EN_STAT_IC_EN_SET_MSK 0x00000001
5139 /* The mask used to clear the ALT_I2C_EN_STAT_IC_EN register field value. */
5140 #define ALT_I2C_EN_STAT_IC_EN_CLR_MSK 0xfffffffe
5141 /* The reset value of the ALT_I2C_EN_STAT_IC_EN register field. */
5142 #define ALT_I2C_EN_STAT_IC_EN_RESET 0x0
5143 /* Extracts the ALT_I2C_EN_STAT_IC_EN field value from a register. */
5144 #define ALT_I2C_EN_STAT_IC_EN_GET(value) (((value) & 0x00000001) >> 0)
5145 /* Produces a ALT_I2C_EN_STAT_IC_EN register field value suitable for setting the register. */
5146 #define ALT_I2C_EN_STAT_IC_EN_SET(value) (((value) << 0) & 0x00000001)
5147 
5148 /*
5149  * Field : Slave Disabled While Busy Bit - slv_disabled_while_busy
5150  *
5151  * This bit indicates if a potential or active Slave operation has been aborted due
5152  * to the setting of the ic_enable register from 1 to 0. This bit is set when the
5153  * CPU writes a 0 to the ic_enable register while: (a) I2C is receiving the address
5154  * byte of the Slave-Transmitter operation from a remote master; OR, (b) address
5155  * and data bytes of the Slave-Receiver operation from a remote master. When read
5156  * as 1, I2C is deemed to have forced a NACK during any part of an I2C transfer,
5157  * irrespective of whether the I2C address matches the slave address set in i2c
5158  * (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0
5159  * but has not taken effect. NOTE: If the remote I2C master terminates the transfer
5160  * with a STOP condition before the i2c has a chance to NACK a transfer, and
5161  * IC_ENABLE has been set to 0, then this bit will also be set to 1. When read as
5162  * 0, i2c is deemed to have been disabled when there is master activity, or when
5163  * the I2C bus is idle. NOTE: The CPU can safely read this bit when IC_EN (bit 0)
5164  * is read as 0.
5165  *
5166  * Field Access Macros:
5167  *
5168  */
5169 /* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */
5170 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_LSB 1
5171 /* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */
5172 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_MSB 1
5173 /* The width in bits of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */
5174 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_WIDTH 1
5175 /* The mask used to set the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value. */
5176 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET_MSK 0x00000002
5177 /* The mask used to clear the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value. */
5178 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_CLR_MSK 0xfffffffd
5179 /* The reset value of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */
5180 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_RESET 0x0
5181 /* Extracts the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY field value from a register. */
5182 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_GET(value) (((value) & 0x00000002) >> 1)
5183 /* Produces a ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value suitable for setting the register. */
5184 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET(value) (((value) << 1) & 0x00000002)
5185 
5186 /*
5187  * Field : Slave Received Data Lost Bit - slv_rx_data_lost
5188  *
5189  * This bit indicates if a Slave-Receiver operation has been aborted with at least
5190  * one data byte received from an I2C transfer due to the setting of IC ENABLE from
5191  * 1 to 0. When read as 1, i2c is deemed to have been actively engaged in an
5192  * aborted I2C transfer (with matching address) and the data phase of the I2C
5193  * transfer has been entered, even though a data byte has been responded with a
5194  * NACK. NOTE: If the remote I2C master terminates the transfer with a STOP
5195  * condition before the i2c has a chance to NACK a transfer, and ic_enable has been
5196  * set to 0, then this bit is also set to 1. When read as 0, i2c is deemed to have
5197  * been disabled without being actively involved in the data phase of a Slave-
5198  * Receiver transfer. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is
5199  * read as 0.
5200  *
5201  * Field Access Macros:
5202  *
5203  */
5204 /* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */
5205 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_LSB 2
5206 /* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */
5207 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_MSB 2
5208 /* The width in bits of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */
5209 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_WIDTH 1
5210 /* The mask used to set the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value. */
5211 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET_MSK 0x00000004
5212 /* The mask used to clear the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value. */
5213 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_CLR_MSK 0xfffffffb
5214 /* The reset value of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */
5215 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_RESET 0x0
5216 /* Extracts the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST field value from a register. */
5217 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_GET(value) (((value) & 0x00000004) >> 2)
5218 /* Produces a ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value suitable for setting the register. */
5219 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET(value) (((value) << 2) & 0x00000004)
5220 
5221 #ifndef __ASSEMBLY__
5222 /*
5223  * WARNING: The C register and register group struct declarations are provided for
5224  * convenience and illustrative purposes. They should, however, be used with
5225  * caution as the C language standard provides no guarantees about the alignment or
5226  * atomicity of device memory accesses. The recommended practice for writing
5227  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5228  * alt_write_word() functions.
5229  *
5230  * The struct declaration for register ALT_I2C_EN_STAT.
5231  */
5232 struct ALT_I2C_EN_STAT_s
5233 {
5234  const uint32_t ic_en : 1; /* Enable Status Bit */
5235  const uint32_t slv_disabled_while_busy : 1; /* Slave Disabled While Busy Bit */
5236  const uint32_t slv_rx_data_lost : 1; /* Slave Received Data Lost Bit */
5237  uint32_t : 29; /* *UNDEFINED* */
5238 };
5239 
5240 /* The typedef declaration for register ALT_I2C_EN_STAT. */
5241 typedef volatile struct ALT_I2C_EN_STAT_s ALT_I2C_EN_STAT_t;
5242 #endif /* __ASSEMBLY__ */
5243 
5244 /* The byte offset of the ALT_I2C_EN_STAT register from the beginning of the component. */
5245 #define ALT_I2C_EN_STAT_OFST 0x9c
5246 /* The address of the ALT_I2C_EN_STAT register. */
5247 #define ALT_I2C_EN_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_STAT_OFST))
5248 
5249 /*
5250  * Register : SS and FS Spike Suppression Limit Register - ic_fs_spklen
5251  *
5252  * This register is used to store the duration, measured in ic_clk cycles, of the
5253  * longest spike that is filtered out by the spike suppression logic when the
5254  * component is operating in SS or FS modes.
5255  *
5256  * Register Layout
5257  *
5258  * Bits | Access | Reset | Description
5259  * :-------|:-------|:------|:---------------------------------
5260  * [7:0] | RW | 0x2 | Spike Suppression Limit Register
5261  * [31:8] | ??? | 0x0 | *UNDEFINED*
5262  *
5263  */
5264 /*
5265  * Field : Spike Suppression Limit Register - spklen
5266  *
5267  * This register must be set before any I2C bus transaction can take place to
5268  * ensure stable operation. This register sets the duration, measured in ic_clk
5269  * cycles, of the longest spike in the SCL or SDA lines that are filtered out by
5270  * the spike suppression logic. This register can be written only when the I2C
5271  * interface is disabled, which corresponds to the IC_ENABLE register being set to
5272  * 0. Writes at other times have no effect. The minimum valid value is 1; hardware
5273  * prevents values less than this being written, and if attempted results in 2
5274  * being set.
5275  *
5276  * Field Access Macros:
5277  *
5278  */
5279 /* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */
5280 #define ALT_I2C_FS_SPKLEN_SPKLEN_LSB 0
5281 /* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */
5282 #define ALT_I2C_FS_SPKLEN_SPKLEN_MSB 7
5283 /* The width in bits of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */
5284 #define ALT_I2C_FS_SPKLEN_SPKLEN_WIDTH 8
5285 /* The mask used to set the ALT_I2C_FS_SPKLEN_SPKLEN register field value. */
5286 #define ALT_I2C_FS_SPKLEN_SPKLEN_SET_MSK 0x000000ff
5287 /* The mask used to clear the ALT_I2C_FS_SPKLEN_SPKLEN register field value. */
5288 #define ALT_I2C_FS_SPKLEN_SPKLEN_CLR_MSK 0xffffff00
5289 /* The reset value of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */
5290 #define ALT_I2C_FS_SPKLEN_SPKLEN_RESET 0x2
5291 /* Extracts the ALT_I2C_FS_SPKLEN_SPKLEN field value from a register. */
5292 #define ALT_I2C_FS_SPKLEN_SPKLEN_GET(value) (((value) & 0x000000ff) >> 0)
5293 /* Produces a ALT_I2C_FS_SPKLEN_SPKLEN register field value suitable for setting the register. */
5294 #define ALT_I2C_FS_SPKLEN_SPKLEN_SET(value) (((value) << 0) & 0x000000ff)
5295 
5296 #ifndef __ASSEMBLY__
5297 /*
5298  * WARNING: The C register and register group struct declarations are provided for
5299  * convenience and illustrative purposes. They should, however, be used with
5300  * caution as the C language standard provides no guarantees about the alignment or
5301  * atomicity of device memory accesses. The recommended practice for writing
5302  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5303  * alt_write_word() functions.
5304  *
5305  * The struct declaration for register ALT_I2C_FS_SPKLEN.
5306  */
5307 struct ALT_I2C_FS_SPKLEN_s
5308 {
5309  uint32_t spklen : 8; /* Spike Suppression Limit Register */
5310  uint32_t : 24; /* *UNDEFINED* */
5311 };
5312 
5313 /* The typedef declaration for register ALT_I2C_FS_SPKLEN. */
5314 typedef volatile struct ALT_I2C_FS_SPKLEN_s ALT_I2C_FS_SPKLEN_t;
5315 #endif /* __ASSEMBLY__ */
5316 
5317 /* The byte offset of the ALT_I2C_FS_SPKLEN register from the beginning of the component. */
5318 #define ALT_I2C_FS_SPKLEN_OFST 0xa0
5319 /* The address of the ALT_I2C_FS_SPKLEN register. */
5320 #define ALT_I2C_FS_SPKLEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SPKLEN_OFST))
5321 
5322 /*
5323  * Register : Component Parameter Register 1 - ic_comp_param_1
5324  *
5325  * This is a constant read-only register that contains encoded information about
5326  * the component's parameter settings.
5327  *
5328  * Register Layout
5329  *
5330  * Bits | Access | Reset | Description
5331  * :--------|:-------|:------|:------------------------
5332  * [1:0] | R | 0x2 | APB Data Width Register
5333  * [3:2] | R | 0x2 | Max Speed Mode
5334  * [4] | R | 0x0 | CNT Registers Access
5335  * [5] | R | 0x1 | Intr IO
5336  * [6] | R | 0x1 | Has DMA
5337  * [7] | R | 0x1 | Add Encoded Params
5338  * [15:8] | R | 0x3f | Rx Buffer Depth
5339  * [23:16] | R | 0x3f | Tx Buffer Depth
5340  * [31:24] | ??? | 0x0 | *UNDEFINED*
5341  *
5342  */
5343 /*
5344  * Field : APB Data Width Register - apb_data_width
5345  *
5346  * Sets the APB Data Width.
5347  *
5348  * Field Enumeration Values:
5349  *
5350  * Enum | Value | Description
5351  * :--------------------------------------------------|:------|:--------------------------
5352  * ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS | 0x2 | APB Data Width is 32 Bits
5353  *
5354  * Field Access Macros:
5355  *
5356  */
5357 /*
5358  * Enumerated value for register field ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH
5359  *
5360  * APB Data Width is 32 Bits
5361  */
5362 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2
5363 
5364 /* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */
5365 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_LSB 0
5366 /* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */
5367 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_MSB 1
5368 /* The width in bits of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */
5369 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_WIDTH 2
5370 /* The mask used to set the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value. */
5371 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET_MSK 0x00000003
5372 /* The mask used to clear the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value. */
5373 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc
5374 /* The reset value of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */
5375 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_RESET 0x2
5376 /* Extracts the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH field value from a register. */
5377 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0)
5378 /* Produces a ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value suitable for setting the register. */
5379 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003)
5380 
5381 /*
5382  * Field : Max Speed Mode - max_speed_mode
5383  *
5384  * The value of this field determines the maximum i2c bus interface speed.
5385  *
5386  * Field Enumeration Values:
5387  *
5388  * Enum | Value | Description
5389  * :------------------------------------------|:------|:-----------------------
5390  * ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST | 0x2 | Fast Mode (400 kbit/s)
5391  *
5392  * Field Access Macros:
5393  *
5394  */
5395 /*
5396  * Enumerated value for register field ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD
5397  *
5398  * Fast Mode (400 kbit/s)
5399  */
5400 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST 0x2
5401 
5402 /* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */
5403 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_LSB 2
5404 /* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */
5405 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_MSB 3
5406 /* The width in bits of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */
5407 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_WIDTH 2
5408 /* The mask used to set the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value. */
5409 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET_MSK 0x0000000c
5410 /* The mask used to clear the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value. */
5411 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_CLR_MSK 0xfffffff3
5412 /* The reset value of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */
5413 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_RESET 0x2
5414 /* Extracts the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD field value from a register. */
5415 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_GET(value) (((value) & 0x0000000c) >> 2)
5416 /* Produces a ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value suitable for setting the register. */
5417 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET(value) (((value) << 2) & 0x0000000c)
5418 
5419 /*
5420  * Field : CNT Registers Access - hc_count_values
5421  *
5422  * This makes the *CNT registers readable and writable.
5423  *
5424  * Field Enumeration Values:
5425  *
5426  * Enum | Value | Description
5427  * :--------------------------------------------|:------|:--------------------------
5428  * ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR | 0x0 | *CNT registers read/write
5429  *
5430  * Field Access Macros:
5431  *
5432  */
5433 /*
5434  * Enumerated value for register field ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES
5435  *
5436  * * CNT registers read/write
5437  */
5438 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR 0x0
5439 
5440 /* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */
5441 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_LSB 4
5442 /* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */
5443 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_MSB 4
5444 /* The width in bits of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */
5445 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_WIDTH 1
5446 /* The mask used to set the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value. */
5447 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET_MSK 0x00000010
5448 /* The mask used to clear the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value. */
5449 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_CLR_MSK 0xffffffef
5450 /* The reset value of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */
5451 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_RESET 0x0
5452 /* Extracts the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES field value from a register. */
5453 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_GET(value) (((value) & 0x00000010) >> 4)
5454 /* Produces a ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value suitable for setting the register. */
5455 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET(value) (((value) << 4) & 0x00000010)
5456 
5457 /*
5458  * Field : Intr IO - intr_io
5459  *
5460  * All interrupt sources are combined in to a single output.
5461  *
5462  * Field Enumeration Values:
5463  *
5464  * Enum | Value | Description
5465  * :----------------------------------------|:------|:--------------------------
5466  * ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED | 0x1 | Combined Interrupt Output
5467  *
5468  * Field Access Macros:
5469  *
5470  */
5471 /*
5472  * Enumerated value for register field ALT_I2C_COMP_PARAM_1_INTR_IO
5473  *
5474  * Combined Interrupt Output
5475  */
5476 #define ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED 0x1
5477 
5478 /* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */
5479 #define ALT_I2C_COMP_PARAM_1_INTR_IO_LSB 5
5480 /* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */
5481 #define ALT_I2C_COMP_PARAM_1_INTR_IO_MSB 5
5482 /* The width in bits of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */
5483 #define ALT_I2C_COMP_PARAM_1_INTR_IO_WIDTH 1
5484 /* The mask used to set the ALT_I2C_COMP_PARAM_1_INTR_IO register field value. */
5485 #define ALT_I2C_COMP_PARAM_1_INTR_IO_SET_MSK 0x00000020
5486 /* The mask used to clear the ALT_I2C_COMP_PARAM_1_INTR_IO register field value. */
5487 #define ALT_I2C_COMP_PARAM_1_INTR_IO_CLR_MSK 0xffffffdf
5488 /* The reset value of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */
5489 #define ALT_I2C_COMP_PARAM_1_INTR_IO_RESET 0x1
5490 /* Extracts the ALT_I2C_COMP_PARAM_1_INTR_IO field value from a register. */
5491 #define ALT_I2C_COMP_PARAM_1_INTR_IO_GET(value) (((value) & 0x00000020) >> 5)
5492 /* Produces a ALT_I2C_COMP_PARAM_1_INTR_IO register field value suitable for setting the register. */
5493 #define ALT_I2C_COMP_PARAM_1_INTR_IO_SET(value) (((value) << 5) & 0x00000020)
5494 
5495 /*
5496  * Field : Has DMA - has_dma
5497  *
5498  * This configures the inclusion of DMA handshaking interface signals.
5499  *
5500  * Field Enumeration Values:
5501  *
5502  * Enum | Value | Description
5503  * :---------------------------------------|:------|:------------
5504  * ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT | 0x1 | Has DMA
5505  *
5506  * Field Access Macros:
5507  *
5508  */
5509 /*
5510  * Enumerated value for register field ALT_I2C_COMP_PARAM_1_HAS_DMA
5511  *
5512  * Has DMA
5513  */
5514 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT 0x1
5515 
5516 /* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */
5517 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_LSB 6
5518 /* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */
5519 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_MSB 6
5520 /* The width in bits of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */
5521 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_WIDTH 1
5522 /* The mask used to set the ALT_I2C_COMP_PARAM_1_HAS_DMA register field value. */
5523 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET_MSK 0x00000040
5524 /* The mask used to clear the ALT_I2C_COMP_PARAM_1_HAS_DMA register field value. */
5525 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_CLR_MSK 0xffffffbf
5526 /* The reset value of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */
5527 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_RESET 0x1
5528 /* Extracts the ALT_I2C_COMP_PARAM_1_HAS_DMA field value from a register. */
5529 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_GET(value) (((value) & 0x00000040) >> 6)
5530 /* Produces a ALT_I2C_COMP_PARAM_1_HAS_DMA register field value suitable for setting the register. */
5531 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET(value) (((value) << 6) & 0x00000040)
5532 
5533 /*
5534  * Field : Add Encoded Params - add_encoded_params
5535  *
5536  * By adding in the encoded parameters, this gives firmware an easy and quick way
5537  * of identifying the DesignWare component within an I/O memory map. Some critical
5538  * design-time options determine how a driver should interact with the peripheral.
5539  * There is a minimal area overhead by including these parameters. Allows a single
5540  * driver to be developed for each component which will be self-configurable.
5541  *
5542  * Field Enumeration Values:
5543  *
5544  * Enum | Value | Description
5545  * :---------------------------------------------------|:------|:-------------------
5546  * ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS | 0x1 | Add Encoded Params
5547  *
5548  * Field Access Macros:
5549  *
5550  */
5551 /*
5552  * Enumerated value for register field ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS
5553  *
5554  * Add Encoded Params
5555  */
5556 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1
5557 
5558 /* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */
5559 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_LSB 7
5560 /* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */
5561 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_MSB 7
5562 /* The width in bits of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */
5563 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_WIDTH 1
5564 /* The mask used to set the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value. */
5565 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET_MSK 0x00000080
5566 /* The mask used to clear the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value. */
5567 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_CLR_MSK 0xffffff7f
5568 /* The reset value of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */
5569 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_RESET 0x1
5570 /* Extracts the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS field value from a register. */
5571 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00000080) >> 7)
5572 /* Produces a ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value suitable for setting the register. */
5573 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET(value) (((value) << 7) & 0x00000080)
5574 
5575 /*
5576  * Field : Rx Buffer Depth - rx_buffer_depth
5577  *
5578  * Sets Rx FIFO Depth.
5579  *
5580  * Field Enumeration Values:
5581  *
5582  * Enum | Value | Description
5583  * :------------------------------------------------|:------|:-------------------------
5584  * ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES | 0x40 | Rx Fifo Depth 64 Entries
5585  *
5586  * Field Access Macros:
5587  *
5588  */
5589 /*
5590  * Enumerated value for register field ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH
5591  *
5592  * Rx Fifo Depth 64 Entries
5593  */
5594 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES 0x40
5595 
5596 /* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */
5597 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_LSB 8
5598 /* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */
5599 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_MSB 15
5600 /* The width in bits of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */
5601 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_WIDTH 8
5602 /* The mask used to set the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value. */
5603 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET_MSK 0x0000ff00
5604 /* The mask used to clear the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value. */
5605 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_CLR_MSK 0xffff00ff
5606 /* The reset value of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */
5607 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_RESET 0x3f
5608 /* Extracts the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH field value from a register. */
5609 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_GET(value) (((value) & 0x0000ff00) >> 8)
5610 /* Produces a ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value suitable for setting the register. */
5611 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET(value) (((value) << 8) & 0x0000ff00)
5612 
5613 /*
5614  * Field : Tx Buffer Depth - tx_buffer_depth
5615  *
5616  * Sets Tx FIFO Depth.
5617  *
5618  * Field Enumeration Values:
5619  *
5620  * Enum | Value | Description
5621  * :------------------------------------------------|:------|:---------------------------
5622  * ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES | 0x40 | Tx Buffer Depth 64 Entries
5623  *
5624  * Field Access Macros:
5625  *
5626  */
5627 /*
5628  * Enumerated value for register field ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH
5629  *
5630  * Tx Buffer Depth 64 Entries
5631  */
5632 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES 0x40
5633 
5634 /* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */
5635 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_LSB 16
5636 /* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */
5637 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_MSB 23
5638 /* The width in bits of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */
5639 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_WIDTH 8
5640 /* The mask used to set the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value. */
5641 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET_MSK 0x00ff0000
5642 /* The mask used to clear the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value. */
5643 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_CLR_MSK 0xff00ffff
5644 /* The reset value of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */
5645 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_RESET 0x3f
5646 /* Extracts the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH field value from a register. */
5647 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_GET(value) (((value) & 0x00ff0000) >> 16)
5648 /* Produces a ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value suitable for setting the register. */
5649 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET(value) (((value) << 16) & 0x00ff0000)
5650 
5651 #ifndef __ASSEMBLY__
5652 /*
5653  * WARNING: The C register and register group struct declarations are provided for
5654  * convenience and illustrative purposes. They should, however, be used with
5655  * caution as the C language standard provides no guarantees about the alignment or
5656  * atomicity of device memory accesses. The recommended practice for writing
5657  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5658  * alt_write_word() functions.
5659  *
5660  * The struct declaration for register ALT_I2C_COMP_PARAM_1.
5661  */
5662 struct ALT_I2C_COMP_PARAM_1_s
5663 {
5664  const uint32_t apb_data_width : 2; /* APB Data Width Register */
5665  const uint32_t max_speed_mode : 2; /* Max Speed Mode */
5666  const uint32_t hc_count_values : 1; /* CNT Registers Access */
5667  const uint32_t intr_io : 1; /* Intr IO */
5668  const uint32_t has_dma : 1; /* Has DMA */
5669  const uint32_t add_encoded_params : 1; /* Add Encoded Params */
5670  const uint32_t rx_buffer_depth : 8; /* Rx Buffer Depth */
5671  const uint32_t tx_buffer_depth : 8; /* Tx Buffer Depth */
5672  uint32_t : 8; /* *UNDEFINED* */
5673 };
5674 
5675 /* The typedef declaration for register ALT_I2C_COMP_PARAM_1. */
5676 typedef volatile struct ALT_I2C_COMP_PARAM_1_s ALT_I2C_COMP_PARAM_1_t;
5677 #endif /* __ASSEMBLY__ */
5678 
5679 /* The byte offset of the ALT_I2C_COMP_PARAM_1 register from the beginning of the component. */
5680 #define ALT_I2C_COMP_PARAM_1_OFST 0xf4
5681 /* The address of the ALT_I2C_COMP_PARAM_1 register. */
5682 #define ALT_I2C_COMP_PARAM_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_PARAM_1_OFST))
5683 
5684 /*
5685  * Register : Component Version Register - ic_comp_version
5686  *
5687  * Describes the version of the I2C
5688  *
5689  * Register Layout
5690  *
5691  * Bits | Access | Reset | Description
5692  * :-------|:-------|:-----------|:--------------------------
5693  * [31:0] | R | 0x3132302a | Component Parameter Value
5694  *
5695  */
5696 /*
5697  * Field : Component Parameter Value - ic_comp_version
5698  *
5699  * Specifies I2C release number (encoded as 4 ASCII characters)
5700  *
5701  * Field Enumeration Values:
5702  *
5703  * Enum | Value | Description
5704  * :-----------------------------------------|:-----------|:--------------
5705  * ALT_I2C_COMP_VER_IC_COMP_VER_E_VER_1_20A | 0x3132302a | Version 1.20a
5706  *
5707  * Field Access Macros:
5708  *
5709  */
5710 /*
5711  * Enumerated value for register field ALT_I2C_COMP_VER_IC_COMP_VER
5712  *
5713  * Version 1.20a
5714  */
5715 #define ALT_I2C_COMP_VER_IC_COMP_VER_E_VER_1_20A 0x3132302a
5716 
5717 /* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */
5718 #define ALT_I2C_COMP_VER_IC_COMP_VER_LSB 0
5719 /* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */
5720 #define ALT_I2C_COMP_VER_IC_COMP_VER_MSB 31
5721 /* The width in bits of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */
5722 #define ALT_I2C_COMP_VER_IC_COMP_VER_WIDTH 32
5723 /* The mask used to set the ALT_I2C_COMP_VER_IC_COMP_VER register field value. */
5724 #define ALT_I2C_COMP_VER_IC_COMP_VER_SET_MSK 0xffffffff
5725 /* The mask used to clear the ALT_I2C_COMP_VER_IC_COMP_VER register field value. */
5726 #define ALT_I2C_COMP_VER_IC_COMP_VER_CLR_MSK 0x00000000
5727 /* The reset value of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */
5728 #define ALT_I2C_COMP_VER_IC_COMP_VER_RESET 0x3132302a
5729 /* Extracts the ALT_I2C_COMP_VER_IC_COMP_VER field value from a register. */
5730 #define ALT_I2C_COMP_VER_IC_COMP_VER_GET(value) (((value) & 0xffffffff) >> 0)
5731 /* Produces a ALT_I2C_COMP_VER_IC_COMP_VER register field value suitable for setting the register. */
5732 #define ALT_I2C_COMP_VER_IC_COMP_VER_SET(value) (((value) << 0) & 0xffffffff)
5733 
5734 #ifndef __ASSEMBLY__
5735 /*
5736  * WARNING: The C register and register group struct declarations are provided for
5737  * convenience and illustrative purposes. They should, however, be used with
5738  * caution as the C language standard provides no guarantees about the alignment or
5739  * atomicity of device memory accesses. The recommended practice for writing
5740  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5741  * alt_write_word() functions.
5742  *
5743  * The struct declaration for register ALT_I2C_COMP_VER.
5744  */
5745 struct ALT_I2C_COMP_VER_s
5746 {
5747  const uint32_t ic_comp_version : 32; /* Component Parameter Value */
5748 };
5749 
5750 /* The typedef declaration for register ALT_I2C_COMP_VER. */
5751 typedef volatile struct ALT_I2C_COMP_VER_s ALT_I2C_COMP_VER_t;
5752 #endif /* __ASSEMBLY__ */
5753 
5754 /* The byte offset of the ALT_I2C_COMP_VER register from the beginning of the component. */
5755 #define ALT_I2C_COMP_VER_OFST 0xf8
5756 /* The address of the ALT_I2C_COMP_VER register. */
5757 #define ALT_I2C_COMP_VER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_VER_OFST))
5758 
5759 /*
5760  * Register : Component Type Register - ic_comp_type
5761  *
5762  * Describes a unique ASCII value
5763  *
5764  * Register Layout
5765  *
5766  * Bits | Access | Reset | Description
5767  * :-------|:-------|:-----------|:----------------------
5768  * [31:0] | R | 0x44570140 | Component Type Number
5769  *
5770  */
5771 /*
5772  * Field : Component Type Number - ic_comp_type
5773  *
5774  * Designware Component Type number = 0x44_57_01_40. This assigned unique hex value
5775  * is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit
5776  * unsigned number.
5777  *
5778  * Field Access Macros:
5779  *
5780  */
5781 /* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */
5782 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_LSB 0
5783 /* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */
5784 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_MSB 31
5785 /* The width in bits of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */
5786 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_WIDTH 32
5787 /* The mask used to set the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value. */
5788 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET_MSK 0xffffffff
5789 /* The mask used to clear the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value. */
5790 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_CLR_MSK 0x00000000
5791 /* The reset value of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */
5792 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_RESET 0x44570140
5793 /* Extracts the ALT_I2C_COMP_TYPE_IC_COMP_TYPE field value from a register. */
5794 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_GET(value) (((value) & 0xffffffff) >> 0)
5795 /* Produces a ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value suitable for setting the register. */
5796 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET(value) (((value) << 0) & 0xffffffff)
5797 
5798 #ifndef __ASSEMBLY__
5799 /*
5800  * WARNING: The C register and register group struct declarations are provided for
5801  * convenience and illustrative purposes. They should, however, be used with
5802  * caution as the C language standard provides no guarantees about the alignment or
5803  * atomicity of device memory accesses. The recommended practice for writing
5804  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5805  * alt_write_word() functions.
5806  *
5807  * The struct declaration for register ALT_I2C_COMP_TYPE.
5808  */
5809 struct ALT_I2C_COMP_TYPE_s
5810 {
5811  const uint32_t ic_comp_type : 32; /* Component Type Number */
5812 };
5813 
5814 /* The typedef declaration for register ALT_I2C_COMP_TYPE. */
5815 typedef volatile struct ALT_I2C_COMP_TYPE_s ALT_I2C_COMP_TYPE_t;
5816 #endif /* __ASSEMBLY__ */
5817 
5818 /* The byte offset of the ALT_I2C_COMP_TYPE register from the beginning of the component. */
5819 #define ALT_I2C_COMP_TYPE_OFST 0xfc
5820 /* The address of the ALT_I2C_COMP_TYPE register. */
5821 #define ALT_I2C_COMP_TYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_TYPE_OFST))
5822 
5823 #ifndef __ASSEMBLY__
5824 /*
5825  * WARNING: The C register and register group struct declarations are provided for
5826  * convenience and illustrative purposes. They should, however, be used with
5827  * caution as the C language standard provides no guarantees about the alignment or
5828  * atomicity of device memory accesses. The recommended practice for writing
5829  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5830  * alt_write_word() functions.
5831  *
5832  * The struct declaration for register group ALT_I2C.
5833  */
5834 struct ALT_I2C_s
5835 {
5836  ALT_I2C_CON_t ic_con; /* ALT_I2C_CON */
5837  ALT_I2C_TAR_t ic_tar; /* ALT_I2C_TAR */
5838  ALT_I2C_SAR_t ic_sar; /* ALT_I2C_SAR */
5839  volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
5840  ALT_I2C_DATA_CMD_t ic_data_cmd; /* ALT_I2C_DATA_CMD */
5841  ALT_I2C_SS_SCL_HCNT_t ic_ss_scl_hcnt; /* ALT_I2C_SS_SCL_HCNT */
5842  ALT_I2C_SS_SCL_LCNT_t ic_ss_scl_lcnt; /* ALT_I2C_SS_SCL_LCNT */
5843  ALT_I2C_FS_SCL_HCNT_t ic_fs_scl_hcnt; /* ALT_I2C_FS_SCL_HCNT */
5844  ALT_I2C_FS_SCL_LCNT_t ic_fs_scl_lcnt; /* ALT_I2C_FS_SCL_LCNT */
5845  volatile uint32_t _pad_0x24_0x2b[2]; /* *UNDEFINED* */
5846  ALT_I2C_INTR_STAT_t ic_intr_stat; /* ALT_I2C_INTR_STAT */
5847  ALT_I2C_INTR_MSK_t ic_intr_mask; /* ALT_I2C_INTR_MSK */
5848  ALT_I2C_RAW_INTR_STAT_t ic_raw_intr_stat; /* ALT_I2C_RAW_INTR_STAT */
5849  ALT_I2C_RX_TL_t ic_rx_tl; /* ALT_I2C_RX_TL */
5850  ALT_I2C_TX_TL_t ic_tx_tl; /* ALT_I2C_TX_TL */
5851  ALT_I2C_CLR_INTR_t ic_clr_intr; /* ALT_I2C_CLR_INTR */
5852  ALT_I2C_CLR_RX_UNDER_t ic_clr_rx_under; /* ALT_I2C_CLR_RX_UNDER */
5853  ALT_I2C_CLR_RX_OVER_t ic_clr_rx_over; /* ALT_I2C_CLR_RX_OVER */
5854  ALT_I2C_CLR_TX_OVER_t ic_clr_tx_over; /* ALT_I2C_CLR_TX_OVER */
5855  ALT_I2C_CLR_RD_REQ_t ic_clr_rd_req; /* ALT_I2C_CLR_RD_REQ */
5856  ALT_I2C_CLR_TX_ABRT_t ic_clr_tx_abrt; /* ALT_I2C_CLR_TX_ABRT */
5857  ALT_I2C_CLR_RX_DONE_t ic_clr_rx_done; /* ALT_I2C_CLR_RX_DONE */
5858  ALT_I2C_CLR_ACTIVITY_t ic_clr_activity; /* ALT_I2C_CLR_ACTIVITY */
5859  ALT_I2C_CLR_STOP_DET_t ic_clr_stop_det; /* ALT_I2C_CLR_STOP_DET */
5860  ALT_I2C_CLR_START_DET_t ic_clr_start_det; /* ALT_I2C_CLR_START_DET */
5861  ALT_I2C_CLR_GEN_CALL_t ic_clr_gen_call; /* ALT_I2C_CLR_GEN_CALL */
5862  ALT_I2C_EN_t ic_enable; /* ALT_I2C_EN */
5863  ALT_I2C_STAT_t ic_status; /* ALT_I2C_STAT */
5864  ALT_I2C_TXFLR_t ic_txflr; /* ALT_I2C_TXFLR */
5865  ALT_I2C_RXFLR_t ic_rxflr; /* ALT_I2C_RXFLR */
5866  ALT_I2C_SDA_HOLD_t ic_sda_hold; /* ALT_I2C_SDA_HOLD */
5867  ALT_I2C_TX_ABRT_SRC_t ic_tx_abrt_source; /* ALT_I2C_TX_ABRT_SRC */
5868  ALT_I2C_SLV_DATA_NACK_ONLY_t ic_slv_data_nack_only; /* ALT_I2C_SLV_DATA_NACK_ONLY */
5869  ALT_I2C_DMA_CR_t ic_dma_cr; /* ALT_I2C_DMA_CR */
5870  ALT_I2C_DMA_TDLR_t ic_dma_tdlr; /* ALT_I2C_DMA_TDLR */
5871  ALT_I2C_DMA_RDLR_t ic_dma_rdlr; /* ALT_I2C_DMA_RDLR */
5872  ALT_I2C_SDA_SETUP_t ic_sda_setup; /* ALT_I2C_SDA_SETUP */
5873  ALT_I2C_ACK_GENERAL_CALL_t ic_ack_general_call; /* ALT_I2C_ACK_GENERAL_CALL */
5874  ALT_I2C_EN_STAT_t ic_enable_status; /* ALT_I2C_EN_STAT */
5875  ALT_I2C_FS_SPKLEN_t ic_fs_spklen; /* ALT_I2C_FS_SPKLEN */
5876  volatile uint32_t _pad_0xa4_0xf3[20]; /* *UNDEFINED* */
5877  ALT_I2C_COMP_PARAM_1_t ic_comp_param_1; /* ALT_I2C_COMP_PARAM_1 */
5878  ALT_I2C_COMP_VER_t ic_comp_version; /* ALT_I2C_COMP_VER */
5879  ALT_I2C_COMP_TYPE_t ic_comp_type; /* ALT_I2C_COMP_TYPE */
5880 };
5881 
5882 /* The typedef declaration for register group ALT_I2C. */
5883 typedef volatile struct ALT_I2C_s ALT_I2C_t;
5884 /* The struct declaration for the raw register contents of register group ALT_I2C. */
5885 struct ALT_I2C_raw_s
5886 {
5887  volatile uint32_t ic_con; /* ALT_I2C_CON */
5888  volatile uint32_t ic_tar; /* ALT_I2C_TAR */
5889  volatile uint32_t ic_sar; /* ALT_I2C_SAR */
5890  uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
5891  volatile uint32_t ic_data_cmd; /* ALT_I2C_DATA_CMD */
5892  volatile uint32_t ic_ss_scl_hcnt; /* ALT_I2C_SS_SCL_HCNT */
5893  volatile uint32_t ic_ss_scl_lcnt; /* ALT_I2C_SS_SCL_LCNT */
5894  volatile uint32_t ic_fs_scl_hcnt; /* ALT_I2C_FS_SCL_HCNT */
5895  volatile uint32_t ic_fs_scl_lcnt; /* ALT_I2C_FS_SCL_LCNT */
5896  uint32_t _pad_0x24_0x2b[2]; /* *UNDEFINED* */
5897  volatile uint32_t ic_intr_stat; /* ALT_I2C_INTR_STAT */
5898  volatile uint32_t ic_intr_mask; /* ALT_I2C_INTR_MSK */
5899  volatile uint32_t ic_raw_intr_stat; /* ALT_I2C_RAW_INTR_STAT */
5900  volatile uint32_t ic_rx_tl; /* ALT_I2C_RX_TL */
5901  volatile uint32_t ic_tx_tl; /* ALT_I2C_TX_TL */
5902  volatile uint32_t ic_clr_intr; /* ALT_I2C_CLR_INTR */
5903  volatile uint32_t ic_clr_rx_under; /* ALT_I2C_CLR_RX_UNDER */
5904  volatile uint32_t ic_clr_rx_over; /* ALT_I2C_CLR_RX_OVER */
5905  volatile uint32_t ic_clr_tx_over; /* ALT_I2C_CLR_TX_OVER */
5906  volatile uint32_t ic_clr_rd_req; /* ALT_I2C_CLR_RD_REQ */
5907  volatile uint32_t ic_clr_tx_abrt; /* ALT_I2C_CLR_TX_ABRT */
5908  volatile uint32_t ic_clr_rx_done; /* ALT_I2C_CLR_RX_DONE */
5909  volatile uint32_t ic_clr_activity; /* ALT_I2C_CLR_ACTIVITY */
5910  volatile uint32_t ic_clr_stop_det; /* ALT_I2C_CLR_STOP_DET */
5911  volatile uint32_t ic_clr_start_det; /* ALT_I2C_CLR_START_DET */
5912  volatile uint32_t ic_clr_gen_call; /* ALT_I2C_CLR_GEN_CALL */
5913  volatile uint32_t ic_enable; /* ALT_I2C_EN */
5914  volatile uint32_t ic_status; /* ALT_I2C_STAT */
5915  volatile uint32_t ic_txflr; /* ALT_I2C_TXFLR */
5916  volatile uint32_t ic_rxflr; /* ALT_I2C_RXFLR */
5917  volatile uint32_t ic_sda_hold; /* ALT_I2C_SDA_HOLD */
5918  volatile uint32_t ic_tx_abrt_source; /* ALT_I2C_TX_ABRT_SRC */
5919  volatile uint32_t ic_slv_data_nack_only; /* ALT_I2C_SLV_DATA_NACK_ONLY */
5920  volatile uint32_t ic_dma_cr; /* ALT_I2C_DMA_CR */
5921  volatile uint32_t ic_dma_tdlr; /* ALT_I2C_DMA_TDLR */
5922  volatile uint32_t ic_dma_rdlr; /* ALT_I2C_DMA_RDLR */
5923  volatile uint32_t ic_sda_setup; /* ALT_I2C_SDA_SETUP */
5924  volatile uint32_t ic_ack_general_call; /* ALT_I2C_ACK_GENERAL_CALL */
5925  volatile uint32_t ic_enable_status; /* ALT_I2C_EN_STAT */
5926  volatile uint32_t ic_fs_spklen; /* ALT_I2C_FS_SPKLEN */
5927  uint32_t _pad_0xa4_0xf3[20]; /* *UNDEFINED* */
5928  volatile uint32_t ic_comp_param_1; /* ALT_I2C_COMP_PARAM_1 */
5929  volatile uint32_t ic_comp_version; /* ALT_I2C_COMP_VER */
5930  volatile uint32_t ic_comp_type; /* ALT_I2C_COMP_TYPE */
5931 };
5932 
5933 /* The typedef declaration for the raw register contents of register group ALT_I2C. */
5934 typedef volatile struct ALT_I2C_raw_s ALT_I2C_raw_t;
5935 #endif /* __ASSEMBLY__ */
5936 
5937 
5938 #ifdef __cplusplus
5939 }
5940 #endif /* __cplusplus */
5941 #endif /* __ALTERA_ALT_I2C_H__ */
5942