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alt_dma_program.h
1
/******************************************************************************
2
*
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* Copyright 2013,2017 Altera Corporation. All Rights Reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
32
33
/*
34
* $Id: //acds/main/embedded/ip/hps/armv8/hwlib/include/alt_dma_program.h#1 $
35
*/
36
37
#ifndef __ALT_DMA_PROGRAM_H__
38
#define __ALT_DMA_PROGRAM_H__
39
40
#include "hwlib.h"
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#include "alt_dma_common.h"
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43
#ifdef __cplusplus
44
extern
"C"
45
{
46
#endif
/* __cplusplus */
47
78
#define ALT_DMA_PROGRAM_CACHE_LINE_SIZE (32)
79
86
#define ALT_DMA_PROGRAM_CACHE_LINE_COUNT (16)
87
101
#ifndef ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE
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#define ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE (ALT_DMA_PROGRAM_CACHE_LINE_SIZE * ALT_DMA_PROGRAM_CACHE_LINE_COUNT)
103
#endif
104
110
typedef
struct
ALT_DMA_PROGRAM_s
111
{
112
uint32_t flag;
113
114
uint16_t buffer_start;
115
uint16_t code_size;
116
117
uint16_t loop0;
118
uint16_t loop1;
119
120
uint16_t sar;
121
uint16_t dar;
122
123
/*
124
* Add a little extra space so that regardless of where this structure
125
* sits in memory, a suitable start address can be aligned to the cache
126
* line stride while providing the requested buffer space.
127
*/
128
uint8_t program[
ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE
+
129
ALT_DMA_PROGRAM_CACHE_LINE_SIZE
];
130
}
131
ALT_DMA_PROGRAM_t
;
132
137
typedef
enum
ALT_DMA_PROGRAM_REG_e
138
{
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ALT_DMA_PROGRAM_REG_SAR
= 0x0,
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ALT_DMA_PROGRAM_REG_DAR
= 0x2,
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ALT_DMA_PROGRAM_REG_CCR
= 0x1
147
}
148
ALT_DMA_PROGRAM_REG_t
;
149
170
typedef
enum
ALT_DMA_PROGRAM_INST_MOD_e
171
{
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ALT_DMA_PROGRAM_INST_MOD_NONE
,
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ALT_DMA_PROGRAM_INST_MOD_SINGLE
,
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ALT_DMA_PROGRAM_INST_MOD_BURST
,
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196
ALT_DMA_PROGRAM_INST_MOD_PERIPH
197
}
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ALT_DMA_PROGRAM_INST_MOD_t
;
199
211
ALT_STATUS_CODE
alt_dma_program_init
(
ALT_DMA_PROGRAM_t
* pgm);
212
223
ALT_STATUS_CODE
alt_dma_program_uninit
(
ALT_DMA_PROGRAM_t
* pgm);
224
235
ALT_STATUS_CODE
alt_dma_program_clear
(
ALT_DMA_PROGRAM_t
* pgm);
236
249
ALT_STATUS_CODE
alt_dma_program_validate
(
const
ALT_DMA_PROGRAM_t
* pgm);
250
284
ALT_STATUS_CODE
alt_dma_program_progress_reg
(
ALT_DMA_PROGRAM_t
* pgm,
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ALT_DMA_PROGRAM_REG_t
reg,
286
uint32_t current, uint32_t * progress);
287
309
ALT_STATUS_CODE
alt_dma_program_update_reg
(
ALT_DMA_PROGRAM_t
* pgm,
310
ALT_DMA_PROGRAM_REG_t
reg, uint32_t val);
311
334
/* Assembler Syntax: DMAADDH <address_register>, <16-bit immediate> */
335
ALT_STATUS_CODE
alt_dma_program_DMAADDH
(
ALT_DMA_PROGRAM_t
* pgm,
336
ALT_DMA_PROGRAM_REG_t
addr_reg, uint16_t val);
337
357
/* Assembler Syntax: DMAADNH <address_register>, <16-bit immediate> */
358
ALT_STATUS_CODE
alt_dma_program_DMAADNH
(
ALT_DMA_PROGRAM_t
* pgm,
359
ALT_DMA_PROGRAM_REG_t
addr_reg, uint16_t val);
360
371
/* Assembler Syntax: DMAEND */
372
ALT_STATUS_CODE
alt_dma_program_DMAEND
(
ALT_DMA_PROGRAM_t
* pgm);
373
388
/* Assembler Syntax: DMAFLUSHP <peripheral> */
389
ALT_STATUS_CODE
alt_dma_program_DMAFLUSHP
(
ALT_DMA_PROGRAM_t
* pgm,
390
ALT_DMA_PERIPH_t periph);
391
412
/* Assembler Syntax: DMAGO <channel_number>, <32-bit_immediate> [, ns] */
413
ALT_STATUS_CODE
alt_dma_program_DMAGO
(
ALT_DMA_PROGRAM_t
* pgm,
414
ALT_DMA_CHANNEL_t
channel, uint32_t val,
415
ALT_DMA_SECURITY_t
sec);
416
427
/* Assembler Syntax: DMAKILL */
428
ALT_STATUS_CODE
alt_dma_program_DMAKILL
(
ALT_DMA_PROGRAM_t
* pgm);
429
446
/* Assembler Syntax: DMALD[S|B] */
447
ALT_STATUS_CODE
alt_dma_program_DMALD
(
ALT_DMA_PROGRAM_t
* pgm,
448
ALT_DMA_PROGRAM_INST_MOD_t
mod);
449
470
/* Assembler Syntax: DMALDP<S|B> <peripheral> */
471
ALT_STATUS_CODE
alt_dma_program_DMALDP
(
ALT_DMA_PROGRAM_t
* pgm,
472
ALT_DMA_PROGRAM_INST_MOD_t
mod, ALT_DMA_PERIPH_t periph);
473
489
/* Assembler Syntax: DMALP [<LC0>|<LC1>] <loop_iterations> */
490
ALT_STATUS_CODE
alt_dma_program_DMALP
(
ALT_DMA_PROGRAM_t
* pgm,
491
uint32_t iterations);
492
513
/* Assembler Syntax: DMALPEND[S|B] */
514
ALT_STATUS_CODE
alt_dma_program_DMALPEND
(
ALT_DMA_PROGRAM_t
* pgm,
515
ALT_DMA_PROGRAM_INST_MOD_t
mod);
516
528
/* Assembler Syntax: DMALPFE */
529
ALT_STATUS_CODE
alt_dma_program_DMALPFE
(
ALT_DMA_PROGRAM_t
* pgm);
530
550
/* Assembler Syntax: DMAMOV <destination_register>, <32-bit_immediate> */
551
ALT_STATUS_CODE
alt_dma_program_DMAMOV
(
ALT_DMA_PROGRAM_t
* pgm,
552
ALT_DMA_PROGRAM_REG_t
chan_reg, uint32_t val);
553
564
/* Assembler Syntax: DMANOP */
565
ALT_STATUS_CODE
alt_dma_program_DMANOP
(
ALT_DMA_PROGRAM_t
* pgm);
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577
/* Assembler Syntax: DMARMB */
578
ALT_STATUS_CODE
alt_dma_program_DMARMB
(
ALT_DMA_PROGRAM_t
* pgm);
579
594
/* Assembler Syntax: DMASEV <event_num> */
595
ALT_STATUS_CODE
alt_dma_program_DMASEV
(
ALT_DMA_PROGRAM_t
* pgm,
596
ALT_DMA_EVENT_t
evt);
597
613
/* Assembler Syntax: DMAST[S|B] */
614
ALT_STATUS_CODE
alt_dma_program_DMAST
(
ALT_DMA_PROGRAM_t
* pgm,
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ALT_DMA_PROGRAM_INST_MOD_t
mod);
616
637
/* Assembler Syntax: DMASTP<S|B> <peripheral> */
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ALT_STATUS_CODE
alt_dma_program_DMASTP
(
ALT_DMA_PROGRAM_t
* pgm,
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ALT_DMA_PROGRAM_INST_MOD_t
mod, ALT_DMA_PERIPH_t periph);
640
651
/* Assembler Syntax: DMASTZ */
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ALT_STATUS_CODE
alt_dma_program_DMASTZ
(
ALT_DMA_PROGRAM_t
* pgm);
653
673
/* Assembler Syntax: DMAWFE <event_num>[, invalid] */
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ALT_STATUS_CODE
alt_dma_program_DMAWFE
(
ALT_DMA_PROGRAM_t
* pgm,
675
ALT_DMA_EVENT_t
evt,
bool
invalid);
676
698
/* Assembler Syntax: DMAWFP <peripheral>, <single|burst|periph> */
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ALT_STATUS_CODE
alt_dma_program_DMAWFP
(
ALT_DMA_PROGRAM_t
* pgm,
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ALT_DMA_PERIPH_t periph,
ALT_DMA_PROGRAM_INST_MOD_t
mod);
701
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/* Assembler Syntax: DMAWMB */
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ALT_STATUS_CODE
alt_dma_program_DMAWMB
(
ALT_DMA_PROGRAM_t
* pgm);
714
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/*
762
* Source Address {Fixed,Incrementing}
763
*/
765
#define ALT_DMA_CCR_OPT_SAF (0 << 0)
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#define ALT_DMA_CCR_OPT_SAI (1 << 0)
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#define ALT_DMA_CCR_OPT_SA_DEFAULT ALT_DMA_CCR_OPT_SAI
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/*
772
* Source burst Size (in bits)
773
*/
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#define ALT_DMA_CCR_OPT_SS8 (0 << 1)
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#define ALT_DMA_CCR_OPT_SS16 (1 << 1)
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#define ALT_DMA_CCR_OPT_SS32 (2 << 1)
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#define ALT_DMA_CCR_OPT_SS64 (3 << 1)
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#define ALT_DMA_CCR_OPT_SS128 (4 << 1)
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#define ALT_DMA_CCR_OPT_SS_DEFAULT ALT_DMA_CCR_OPT_SS8
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/*
788
* Source burst Length (in transfer(s))
789
*/
791
#define ALT_DMA_CCR_OPT_SB1 (0x0 << 4)
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#define ALT_DMA_CCR_OPT_SB2 (0x1 << 4)
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#define ALT_DMA_CCR_OPT_SB3 (0x2 << 4)
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#define ALT_DMA_CCR_OPT_SB4 (0x3 << 4)
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#define ALT_DMA_CCR_OPT_SB5 (0x4 << 4)
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#define ALT_DMA_CCR_OPT_SB6 (0x5 << 4)
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803
#define ALT_DMA_CCR_OPT_SB7 (0x6 << 4)
804
805
#define ALT_DMA_CCR_OPT_SB8 (0x7 << 4)
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807
#define ALT_DMA_CCR_OPT_SB9 (0x8 << 4)
808
809
#define ALT_DMA_CCR_OPT_SB10 (0x9 << 4)
810
811
#define ALT_DMA_CCR_OPT_SB11 (0xa << 4)
812
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#define ALT_DMA_CCR_OPT_SB12 (0xb << 4)
814
815
#define ALT_DMA_CCR_OPT_SB13 (0xc << 4)
816
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#define ALT_DMA_CCR_OPT_SB14 (0xd << 4)
818
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#define ALT_DMA_CCR_OPT_SB15 (0xe << 4)
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#define ALT_DMA_CCR_OPT_SB16 (0xf << 4)
822
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#define ALT_DMA_CCR_OPT_SB_DEFAULT ALT_DMA_CCR_OPT_SB1
824
825
/*
826
* Source Protection
827
*/
829
#define ALT_DMA_CCR_OPT_SP(imm3) ((imm3) << 8)
830
831
#define ALT_DMA_CCR_OPT_SP_DEFAULT ALT_DMA_CCR_OPT_SP(0)
832
833
/*
834
* Source cache
835
*/
837
#define ALT_DMA_CCR_OPT_SC(imm4) ((imm4) << 11)
838
839
#define ALT_DMA_CCR_OPT_SC_DEFAULT ALT_DMA_CCR_OPT_SC(0)
840
841
/*
842
* Destination Address {Fixed,Incrementing}
843
*/
845
#define ALT_DMA_CCR_OPT_DAF (0 << 14)
846
847
#define ALT_DMA_CCR_OPT_DAI (1 << 14)
848
849
#define ALT_DMA_CCR_OPT_DA_DEFAULT ALT_DMA_CCR_OPT_DAI
850
851
/*
852
* Destination burst Size (in bits)
853
*/
855
#define ALT_DMA_CCR_OPT_DS8 (0 << 15)
856
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#define ALT_DMA_CCR_OPT_DS16 (1 << 15)
858
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#define ALT_DMA_CCR_OPT_DS32 (2 << 15)
860
861
#define ALT_DMA_CCR_OPT_DS64 (3 << 15)
862
863
#define ALT_DMA_CCR_OPT_DS128 (4 << 15)
864
865
#define ALT_DMA_CCR_OPT_DS_DEFAULT ALT_DMA_CCR_OPT_DS8
866
867
/*
868
* Destination Burst length (in transfer(s))
869
*/
871
#define ALT_DMA_CCR_OPT_DB1 (0x0 << 18)
872
873
#define ALT_DMA_CCR_OPT_DB2 (0x1 << 18)
874
875
#define ALT_DMA_CCR_OPT_DB3 (0x2 << 18)
876
877
#define ALT_DMA_CCR_OPT_DB4 (0x3 << 18)
878
879
#define ALT_DMA_CCR_OPT_DB5 (0x4 << 18)
880
881
#define ALT_DMA_CCR_OPT_DB6 (0x5 << 18)
882
883
#define ALT_DMA_CCR_OPT_DB7 (0x6 << 18)
884
885
#define ALT_DMA_CCR_OPT_DB8 (0x7 << 18)
886
887
#define ALT_DMA_CCR_OPT_DB9 (0x8 << 18)
888
889
#define ALT_DMA_CCR_OPT_DB10 (0x9 << 18)
890
891
#define ALT_DMA_CCR_OPT_DB11 (0xa << 18)
892
893
#define ALT_DMA_CCR_OPT_DB12 (0xb << 18)
894
895
#define ALT_DMA_CCR_OPT_DB13 (0xc << 18)
896
897
#define ALT_DMA_CCR_OPT_DB14 (0xd << 18)
898
899
#define ALT_DMA_CCR_OPT_DB15 (0xe << 18)
900
901
#define ALT_DMA_CCR_OPT_DB16 (0xf << 18)
902
903
#define ALT_DMA_CCR_OPT_DB_DEFAULT ALT_DMA_CCR_OPT_DB1
904
905
/*
906
* Destination Protection
907
*/
909
#define ALT_DMA_CCR_OPT_DP(imm3) ((imm3) << 22)
910
911
#define ALT_DMA_CCR_OPT_DP_DEFAULT ALT_DMA_CCR_OPT_DP(0)
912
913
/*
914
* Destination Cache
915
*/
917
#define ALT_DMA_CCR_OPT_DC(imm4) ((imm4) << 25)
918
919
#define ALT_DMA_CCR_OPT_DC_DEFAULT ALT_DMA_CCR_OPT_DC(0)
920
921
/*
922
* Endian Swap size (in bits)
923
*/
925
#define ALT_DMA_CCR_OPT_ES8 (0 << 28)
926
927
#define ALT_DMA_CCR_OPT_ES16 (1 << 28)
928
929
#define ALT_DMA_CCR_OPT_ES32 (2 << 28)
930
931
#define ALT_DMA_CCR_OPT_ES64 (3 << 28)
932
933
#define ALT_DMA_CCR_OPT_ES128 (4 << 28)
934
935
#define ALT_DMA_CCR_OPT_ES_DEFAULT ALT_DMA_CCR_OPT_ES8
936
938
#define ALT_DMA_CCR_OPT_DEFAULT \
939
(ALT_DMA_CCR_OPT_SB1 | ALT_DMA_CCR_OPT_SS8 | ALT_DMA_CCR_OPT_SAI | \
940
ALT_DMA_CCR_OPT_SP(0) | ALT_DMA_CCR_OPT_SC(0) | \
941
ALT_DMA_CCR_OPT_DB1 | ALT_DMA_CCR_OPT_DS8 | ALT_DMA_CCR_OPT_DAI | \
942
ALT_DMA_CCR_OPT_DP(0) | ALT_DMA_CCR_OPT_DC(0) | \
943
ALT_DMA_CCR_OPT_ES8)
944
953
#ifdef __cplusplus
954
}
955
#endif
/* __cplusplus */
956
957
#endif
/* __ALT_DMA_PROGRAM_H__ */
include
alt_dma_program.h
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