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alt_sdmmc.h
1 /******************************************************************************
2 *
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31 ******************************************************************************/
32 
33 /*
34  * $Id: //acds/main/embedded/ip/hps/armv8/hwlib/include/alt_sdmmc.h#1 $
35  */
36 
37 #ifndef __ALT_SDMMC_H__
38 #define __ALT_SDMMC_H__
39 
40 #include "hwlib.h"
41 
42 #ifdef __cplusplus
43 extern "C"
44 {
45 #endif /* __cplusplus */
46 
47 /******************************************************************************/
148 /******************************************************************************/
161 {
172 
177 typedef struct ALT_SDMMC_CARD_INFO_s
178 {
180  uint32_t rca;
181  uint32_t xfer_speed;
182  uint32_t max_r_blkln;
183  uint32_t max_w_blkln;
186  bool high_speed;
187  uint32_t scr_sd_spec;
188  uint32_t csd_ccc;
189  uint32_t blk_number_high;
190  uint32_t blk_number_low;
199  uint32_t scr_bus_widths;
201 
214 ALT_STATUS_CODE alt_sdmmc_init(void);
215 
223 ALT_STATUS_CODE alt_sdmmc_uninit(void);
224 
232 ALT_STATUS_CODE alt_sdmmc_reset(void);
233 
238 {
242 
248 {
252 
258 {
259  ALT_SDMMC_GO_IDLE_STATE = 0,
260  ALT_SDMMC_ALL_SEND_CID = 2,
261  ALT_SDMMC_SET_RELATIVE_ADDR = 3,
262  ALT_SDMMC_SET_DSR = 4,
263  ALT_SDMMC_SEND_OP_COND = 5,
264  ALT_SDMMC_SWITCH = 6,
265  ALT_SDMMC_SEL_DES_CARD = 7,
266  ALT_SDMMC_IF_COND = 8,
267  ALT_SDMMC_SEND_EXT_CSD = 8,
268  ALT_SDMMC_SEND_CSD = 9,
269  ALT_SDMMC_SEND_CID = 10,
270  ALT_SDMMC_READ_DAT_UNTIL_STOP = 11,
271  ALT_SDMMC_STOP_TRANSMISSION = 12,
272  ALT_SDMMC_SEND_STATUS = 13,
273  ALT_SDMMC_GO_INACTIVE_STATE = 15,
274  ALT_SDMMC_SET_BLOCKLEN = 16,
275  ALT_SDMMC_READ_SINGLE_BLOCK = 17,
276  ALT_SDMMC_READ_MULTIPLE_BLOCK = 18,
277  ALT_SDMMC_WRITE_DAT_UNTIL_STOP = 20,
278  ALT_SDMMC_WRITE_BLOCK = 24,
279  ALT_SDMMC_WRITE_MULTIPLE_BLOCK = 25,
280  ALT_SDMMC_PROGRAM_CID = 26,
281  ALT_SDMMC_PROGRAM_CSD = 27,
282  ALT_SDMMC_SET_WRITE_PROT = 28,
283  ALT_SDMMC_CLR_WRITE_PROT = 29,
284  ALT_SDMMC_SEND_WRITE_PROT = 30,
285  ALT_SDMMC_TAG_SECTOR_START = 32,
286  ALT_SDMMC_TAG_SECTOR_END = 33,
287  ALT_SDMMC_UNTAG_SECTOR = 34,
288  ALT_SDMMC_TAG_ERASE_GROUP_START = 35,
289  ALT_SDMMC_TAG_ERASE_GROUP_END = 36,
290  ALT_SDMMC_UNTAG_ERASE_GROUP = 37,
291  ALT_SDMMC_ERASE = 38,
292  ALT_SDMMC_FAST_IO = 39,
293  ALT_SDMMC_GO_IRQ_STATE = 40,
294  ALT_SDMMC_LOCK_UNLOCK = 42,
295  ALT_SDMMC_APP_CMD = 55,
296  ALT_SDMMC_GEN_CMD = 56,
297  ALT_SDMMC_READ_OCR = 58,
298  ALT_SDMMC_CRC_ON_OFF = 59,
299 
300  ALT_SDMMC_STANDART_CMD_ALL = 60,
301 
302  /* TBD - Commands specific for card type. */
303  ALT_SD_SET_BUS_WIDTH = 6,
304  ALT_SD_SD_STATUS = 13,
305  ALT_SD_SEND_OP_COND = 41,
306  ALT_SD_SEND_SCR = 51,
307 
308  /* TBD - Clock command or command index does not matter... */
309  ALT_SDMMC_CLK_INDEX = -1,
310 
311  ALT_SDMMC_CMD_ALL = ALT_SDMMC_STANDART_CMD_ALL + 1
313 
318 {
319  uint32_t cmd_index : 6;
321  uint32_t response_expect : 1;
323  uint32_t response_length_long : 1;
325  uint32_t check_response_crc : 1;
327  uint32_t data_expected : 1;
329  uint32_t write_active : 1;
334  uint32_t stream_mode_active : 1;
336  uint32_t send_auto_stop : 1;
338  uint32_t wait_prvdata_complete : 1;
342  uint32_t stop_abort_cmd : 1;
346  uint32_t send_initialization : 1;
350  uint32_t card_number : 5;
354  uint32_t update_clock_registers_only : 1;
358  uint32_t read_ceata_device : 1;
362  uint32_t ccs_expected : 1;
367  uint32_t enable_boot : 1;
371  uint32_t expect_boot_ack : 1;
377  uint32_t disable_boot : 1;
379  uint32_t boot_mode : 1;
385  uint32_t volt_switch : 1;
387  uint32_t use_hold_reg : 1;
389  uint32_t reserved : 1;
390  uint32_t start_bit : 1;
398 
421 ALT_STATUS_CODE alt_sdmmc_command_send(ALT_SDMMC_CMD_TYPE_t command_type,
422  ALT_SDMMC_CMD_INDEX_t command,
423  uint32_t command_arg,
424  uint32_t *response);
425 
430 typedef struct ALT_SDMMC_RESPONSE_s
431 {
432  uint32_t resp0;
433  uint32_t resp1;
434  uint32_t resp2;
435  uint32_t resp3;
437 
448 ALT_STATUS_CODE alt_sdmmc_read_long_response(ALT_SDMMC_RESPONSE_t *response);
449 
458 uint32_t alt_sdmmc_int_status_get(void);
459 
470 uint32_t alt_sdmmc_int_mask_get(void);
471 
487 ALT_STATUS_CODE alt_sdmmc_int_clear(const uint32_t mask);
488 
510 ALT_STATUS_CODE alt_sdmmc_int_disable(const uint32_t mask);
511 
533 ALT_STATUS_CODE alt_sdmmc_int_enable(const uint32_t mask);
534 
545 {
546  ALT_SDMMC_INT_STATUS_CD = (1UL << 0),
547  ALT_SDMMC_INT_STATUS_RE = (1UL << 1),
556  ALT_SDMMC_INT_STATUS_HTO = (1UL << 10),
558  ALT_SDMMC_INT_STATUS_HLE = (1UL << 12),
559  ALT_SDMMC_INT_STATUS_SBE = (1UL << 13),
560  ALT_SDMMC_INT_STATUS_ACD = (1UL << 14),
561  ALT_SDMMC_INT_STATUS_EBE = (1UL << 15),
566 
569 /******************************************************************************/
590 {
591  ALT_SDMMC_BUS_WIDTH_1 = 1,
592  ALT_SDMMC_BUS_WIDTH_4 = 4,
593  ALT_SDMMC_BUS_WIDTH_8 = 8
595 
600 typedef struct ALT_SDMMC_CARD_MISC_s
601 {
602  uint32_t response_timeout;
605  uint32_t data_timeout;
611  uint32_t block_size;
612  uint32_t debounce_count;
616 
628 ALT_STATUS_CODE alt_sdmmc_card_misc_get(ALT_SDMMC_CARD_MISC_t *card_misc_cfg);
629 
641 ALT_STATUS_CODE alt_sdmmc_card_misc_set(const ALT_SDMMC_CARD_MISC_t *card_misc_cfg);
642 
658 ALT_STATUS_CODE alt_sdmmc_card_bus_width_set(ALT_SDMMC_CARD_INFO_t *card_info, const ALT_SDMMC_BUS_WIDTH_t width);
659 
670 ALT_STATUS_CODE alt_sdmmc_card_block_size_set(const uint16_t block_size);
671 
686 ALT_STATUS_CODE alt_sdmmc_card_identify(ALT_SDMMC_CARD_INFO_t *card_info);
687 
698 uint32_t alt_sdmmc_card_clk_div_get(void);
699 
714 ALT_STATUS_CODE alt_sdmmc_card_clk_div_set(const uint32_t clk_div);
715 
722 uint32_t alt_sdmmc_card_speed_get(void);
723 
738 ALT_STATUS_CODE alt_sdmmc_card_speed_set(ALT_SDMMC_CARD_INFO_t *card_info, uint32_t xfer_speed);
739 
746 ALT_STATUS_CODE alt_sdmmc_card_clk_disable(void);
747 
761 ALT_STATUS_CODE alt_sdmmc_card_clk_enable(const uint32_t use_low_pwr_mode);
762 
770 ALT_STATUS_CODE alt_sdmmc_card_clk_is_enabled(void);
771 
779 ALT_STATUS_CODE alt_sdmmc_card_clk_low_power_is_enabled(void);
780 
787 ALT_STATUS_CODE alt_sdmmc_card_reset(void);
788 
795 ALT_STATUS_CODE alt_sdmmc_card_is_detected(void);
796 
803 ALT_STATUS_CODE alt_sdmmc_card_is_write_protected(void);
804 
811 ALT_STATUS_CODE alt_sdmmc_card_pwr_is_on(void);
812 
822 ALT_STATUS_CODE alt_sdmmc_card_pwr_on(void);
823 
832 ALT_STATUS_CODE alt_sdmmc_card_pwr_off(void);
833 
836 /******************************************************************************/
879 {
888  ALT_SDMMC_DMA_INT_STATUS_ALL = 0x337
890 
903 {
907  union DES0
908  {
910  struct
911  {
912  uint32_t : 1;
913  uint32_t dic : 1;
922  uint32_t ld : 1;
928  uint32_t fs : 1;
936  uint32_t ch : 1;
946  uint32_t er : 1;
957  uint32_t ces : 1;
971  uint32_t : 24;
972  uint32_t own : 1;
983  } fld;
986  uint32_t raw;
989  } des0;
995  union DES1
996  {
998  struct
999  {
1000  uint32_t bs1 : 13;
1017  uint32_t bs2 : 13;
1026  uint32_t : 6;
1028  } fld;
1031  uint32_t raw;
1034  } des1;
1038  union DES2
1039  {
1041  struct
1042  {
1043  uint32_t bap1 : 32;
1051  } fld;
1054  uint32_t raw;
1057  } des2;
1065  union DES3
1066  {
1068  struct
1069  {
1070  uint32_t bap2_or_next : 32;
1087  } fld;
1090  uint32_t raw;
1093  } des3;
1104 
1115 ALT_STATUS_CODE alt_sdmmc_dma_reset(void);
1116 
1127 ALT_STATUS_CODE alt_sdmmc_dma_disable(void);
1128 
1137 ALT_STATUS_CODE alt_sdmmc_is_dma_enabled(void);
1138 
1149 ALT_STATUS_CODE alt_sdmmc_dma_enable(void);
1150 
1156 {
1167 
1201 ALT_STATUS_CODE alt_sdmmc_dma_start(ALT_SDMMC_DMA_BUF_DESC_t *buf_desc_list,
1202  const uint32_t desc_skip_len,
1203  const ALT_SDMMC_DMA_PBL_t burst_len,
1204  const bool use_fixed_burst);
1205 
1216 ALT_STATUS_CODE alt_sdmmc_poll_demand_set(const uint32_t value);
1217 
1226 uint32_t alt_sdmmc_dma_int_status_get(void);
1227 
1239 uint32_t alt_sdmmc_dma_int_mask_get(void);
1240 
1257 ALT_STATUS_CODE alt_sdmmc_dma_int_clear(const uint32_t mask);
1258 
1280 ALT_STATUS_CODE alt_sdmmc_dma_int_disable(const uint32_t mask);
1281 
1303 ALT_STATUS_CODE alt_sdmmc_dma_int_enable(const uint32_t mask);
1304 
1307 /******************************************************************************/
1317 #define ALT_SDMMC_FIFO_NUM_ENTRIES 1024
1318 
1326 ALT_STATUS_CODE alt_sdmmc_fifo_reset(void);
1327 
1333 {
1342 
1362 ALT_STATUS_CODE alt_sdmmc_fifo_param_get(uint32_t *rx_wtrmk, uint32_t *tx_wtrmk,
1363  ALT_SDMMC_MULT_TRANS_t *mult_trans_size);
1364 
1383 ALT_STATUS_CODE alt_sdmmc_fifo_param_set(uint32_t rx_wtrmk, uint32_t tx_wtrmk, ALT_SDMMC_MULT_TRANS_t mult_trans_size);
1384 
1392 ALT_STATUS_CODE alt_sdmmc_fifo_is_rx_wtrmk_reached(void);
1393 
1401 ALT_STATUS_CODE alt_sdmmc_fifo_is_tx_wtrmk_reached(void);
1402 
1409 ALT_STATUS_CODE alt_sdmmc_fifo_is_empty(void);
1410 
1417 ALT_STATUS_CODE alt_sdmmc_fifo_is_full(void);
1418 
1424 uint32_t alt_sdmmc_fifo_count(void);
1425 
1444 ALT_STATUS_CODE alt_sdmmc_fifo_read(void *dest, const size_t size);
1445 
1467 ALT_STATUS_CODE alt_sdmmc_fifo_write(const void *src, const size_t size);
1468 
1471 /******************************************************************************/
1505 ALT_STATUS_CODE alt_sdmmc_read(ALT_SDMMC_CARD_INFO_t *card_info, void *dest, void *src, const size_t size);
1506 
1534 ALT_STATUS_CODE alt_sdmmc_write(ALT_SDMMC_CARD_INFO_t *card_info, void *dest, void *src, const size_t size);
1535 
1540 #ifdef __cplusplus
1541 }
1542 #endif /* __cplusplus */
1543 
1544 #endif /* __ALT_SDMMC_H__ */