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alt_spim.h
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32 
33 /* Altera - ALT_SPIM */
34 
35 #ifndef __ALTERA_ALT_SPIM_H__
36 #define __ALTERA_ALT_SPIM_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
43 /*
44  * Component : SPI Master Module - ALT_SPIM
45  * SPI Master Module
46  *
47  * Registers in the SPI Master module
48  *
49  */
50 /*
51  * Register : Control Register 0 - ctrlr0
52  *
53  * This register controls the serial data transfer. It is impossible to write to
54  * this register when the SPI Master is enabled. The SPI Master is enabled and
55  * disabled by writing to the SPIENR register.
56  *
57  * Register Layout
58  *
59  * Bits | Access | Reset | Description
60  * :--------|:-------|:------|:----------------------
61  * [3:0] | RW | 0x7 | Data Frame Size
62  * [5:4] | RW | 0x0 | Frame Format
63  * [6] | RW | 0x0 | Serial Clock Phase
64  * [7] | RW | 0x0 | Serial Clock Polarity
65  * [9:8] | RW | 0x0 | Transfer Mode
66  * [10] | ??? | 0x0 | *UNDEFINED*
67  * [11] | RW | 0x0 | Shift Register Loop
68  * [15:12] | RW | 0x0 | Control Frame Size
69  * [31:16] | ??? | 0x0 | *UNDEFINED*
70  *
71  */
72 /*
73  * Field : Data Frame Size - dfs
74  *
75  * Selects the data frame length. When the data frame size is programmed to be less
76  * than 16 bits, the receive data are automatically right-justified by the receive
77  * logic, with the upper bits of the receive FIFO zero-padded. You must right-
78  * justify transmit data before writing into the transmit FIFO. The transmit logic
79  * ignores the upper unused bits when transmitting the data.
80  *
81  * Field Enumeration Values:
82  *
83  * Enum | Value | Description
84  * :--------------------------------|:------|:----------------------------
85  * ALT_SPIM_CTLR0_DFS_E_WIDTH4BIT | 0x3 | 4-bit serial data transfer
86  * ALT_SPIM_CTLR0_DFS_E_WIDTH5BIT | 0x4 | 5-bit serial data transfer
87  * ALT_SPIM_CTLR0_DFS_E_WIDTH6BIT | 0x5 | 6-bit serial data transfer
88  * ALT_SPIM_CTLR0_DFS_E_WIDTH7BIT | 0x6 | 7-bit serial data transfer
89  * ALT_SPIM_CTLR0_DFS_E_WIDTH8BIT | 0x7 | 8-bit serial data transfer
90  * ALT_SPIM_CTLR0_DFS_E_WIDTH9BIT | 0x8 | 9-bit serial data transfer
91  * ALT_SPIM_CTLR0_DFS_E_WIDTH10BIT | 0x9 | 10-bit serial data transfer
92  *
93  * Field Access Macros:
94  *
95  */
96 /*
97  * Enumerated value for register field ALT_SPIM_CTLR0_DFS
98  *
99  * 4-bit serial data transfer
100  */
101 #define ALT_SPIM_CTLR0_DFS_E_WIDTH4BIT 0x3
102 /*
103  * Enumerated value for register field ALT_SPIM_CTLR0_DFS
104  *
105  * 5-bit serial data transfer
106  */
107 #define ALT_SPIM_CTLR0_DFS_E_WIDTH5BIT 0x4
108 /*
109  * Enumerated value for register field ALT_SPIM_CTLR0_DFS
110  *
111  * 6-bit serial data transfer
112  */
113 #define ALT_SPIM_CTLR0_DFS_E_WIDTH6BIT 0x5
114 /*
115  * Enumerated value for register field ALT_SPIM_CTLR0_DFS
116  *
117  * 7-bit serial data transfer
118  */
119 #define ALT_SPIM_CTLR0_DFS_E_WIDTH7BIT 0x6
120 /*
121  * Enumerated value for register field ALT_SPIM_CTLR0_DFS
122  *
123  * 8-bit serial data transfer
124  */
125 #define ALT_SPIM_CTLR0_DFS_E_WIDTH8BIT 0x7
126 /*
127  * Enumerated value for register field ALT_SPIM_CTLR0_DFS
128  *
129  * 9-bit serial data transfer
130  */
131 #define ALT_SPIM_CTLR0_DFS_E_WIDTH9BIT 0x8
132 /*
133  * Enumerated value for register field ALT_SPIM_CTLR0_DFS
134  *
135  * 10-bit serial data transfer
136  */
137 #define ALT_SPIM_CTLR0_DFS_E_WIDTH10BIT 0x9
138 
139 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR0_DFS register field. */
140 #define ALT_SPIM_CTLR0_DFS_LSB 0
141 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR0_DFS register field. */
142 #define ALT_SPIM_CTLR0_DFS_MSB 3
143 /* The width in bits of the ALT_SPIM_CTLR0_DFS register field. */
144 #define ALT_SPIM_CTLR0_DFS_WIDTH 4
145 /* The mask used to set the ALT_SPIM_CTLR0_DFS register field value. */
146 #define ALT_SPIM_CTLR0_DFS_SET_MSK 0x0000000f
147 /* The mask used to clear the ALT_SPIM_CTLR0_DFS register field value. */
148 #define ALT_SPIM_CTLR0_DFS_CLR_MSK 0xfffffff0
149 /* The reset value of the ALT_SPIM_CTLR0_DFS register field. */
150 #define ALT_SPIM_CTLR0_DFS_RESET 0x7
151 /* Extracts the ALT_SPIM_CTLR0_DFS field value from a register. */
152 #define ALT_SPIM_CTLR0_DFS_GET(value) (((value) & 0x0000000f) >> 0)
153 /* Produces a ALT_SPIM_CTLR0_DFS register field value suitable for setting the register. */
154 #define ALT_SPIM_CTLR0_DFS_SET(value) (((value) << 0) & 0x0000000f)
155 
156 /*
157  * Field : Frame Format - frf
158  *
159  * Selects which serial protocol transfers the data.
160  *
161  * Field Enumeration Values:
162  *
163  * Enum | Value | Description
164  * :----------------------------|:------|:------------------------
165  * ALT_SPIM_CTLR0_FRF_E_MOTSPI | 0x0 | Motorola SPI
166  * ALT_SPIM_CTLR0_FRF_E_TISSP | 0x1 | Texas Instruments SSP
167  * ALT_SPIM_CTLR0_FRF_E_NATMW | 0x2 | National Semi Microwire
168  *
169  * Field Access Macros:
170  *
171  */
172 /*
173  * Enumerated value for register field ALT_SPIM_CTLR0_FRF
174  *
175  * Motorola SPI
176  */
177 #define ALT_SPIM_CTLR0_FRF_E_MOTSPI 0x0
178 /*
179  * Enumerated value for register field ALT_SPIM_CTLR0_FRF
180  *
181  * Texas Instruments SSP
182  */
183 #define ALT_SPIM_CTLR0_FRF_E_TISSP 0x1
184 /*
185  * Enumerated value for register field ALT_SPIM_CTLR0_FRF
186  *
187  * National Semi Microwire
188  */
189 #define ALT_SPIM_CTLR0_FRF_E_NATMW 0x2
190 
191 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR0_FRF register field. */
192 #define ALT_SPIM_CTLR0_FRF_LSB 4
193 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR0_FRF register field. */
194 #define ALT_SPIM_CTLR0_FRF_MSB 5
195 /* The width in bits of the ALT_SPIM_CTLR0_FRF register field. */
196 #define ALT_SPIM_CTLR0_FRF_WIDTH 2
197 /* The mask used to set the ALT_SPIM_CTLR0_FRF register field value. */
198 #define ALT_SPIM_CTLR0_FRF_SET_MSK 0x00000030
199 /* The mask used to clear the ALT_SPIM_CTLR0_FRF register field value. */
200 #define ALT_SPIM_CTLR0_FRF_CLR_MSK 0xffffffcf
201 /* The reset value of the ALT_SPIM_CTLR0_FRF register field. */
202 #define ALT_SPIM_CTLR0_FRF_RESET 0x0
203 /* Extracts the ALT_SPIM_CTLR0_FRF field value from a register. */
204 #define ALT_SPIM_CTLR0_FRF_GET(value) (((value) & 0x00000030) >> 4)
205 /* Produces a ALT_SPIM_CTLR0_FRF register field value suitable for setting the register. */
206 #define ALT_SPIM_CTLR0_FRF_SET(value) (((value) << 4) & 0x00000030)
207 
208 /*
209  * Field : Serial Clock Phase - scph
210  *
211  * Valid when the frame format (FRF) is set to Motorola SPI. The serial clock phase
212  * selects the relationship of the serial clock with the slave select signal. When
213  * SCPH = 0, data are captured on the first edge of the serial clock. When SCPH =
214  * 1, the serial clock starts toggling one cycle after the slave select line is
215  * activated, and data are captured on the second edge of the serial clock.
216  *
217  * Field Enumeration Values:
218  *
219  * Enum | Value | Description
220  * :-------------------------------|:------|:-------------------------------------------------
221  * ALT_SPIM_CTLR0_SCPH_E_MIDBIT | 0x0 | Serial clock toggles in middle of first data bit
222  * ALT_SPIM_CTLR0_SCPH_E_STARTBIT | 0x1 | Serial clock toggles at start of first data bit
223  *
224  * Field Access Macros:
225  *
226  */
227 /*
228  * Enumerated value for register field ALT_SPIM_CTLR0_SCPH
229  *
230  * Serial clock toggles in middle of first data bit
231  */
232 #define ALT_SPIM_CTLR0_SCPH_E_MIDBIT 0x0
233 /*
234  * Enumerated value for register field ALT_SPIM_CTLR0_SCPH
235  *
236  * Serial clock toggles at start of first data bit
237  */
238 #define ALT_SPIM_CTLR0_SCPH_E_STARTBIT 0x1
239 
240 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR0_SCPH register field. */
241 #define ALT_SPIM_CTLR0_SCPH_LSB 6
242 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR0_SCPH register field. */
243 #define ALT_SPIM_CTLR0_SCPH_MSB 6
244 /* The width in bits of the ALT_SPIM_CTLR0_SCPH register field. */
245 #define ALT_SPIM_CTLR0_SCPH_WIDTH 1
246 /* The mask used to set the ALT_SPIM_CTLR0_SCPH register field value. */
247 #define ALT_SPIM_CTLR0_SCPH_SET_MSK 0x00000040
248 /* The mask used to clear the ALT_SPIM_CTLR0_SCPH register field value. */
249 #define ALT_SPIM_CTLR0_SCPH_CLR_MSK 0xffffffbf
250 /* The reset value of the ALT_SPIM_CTLR0_SCPH register field. */
251 #define ALT_SPIM_CTLR0_SCPH_RESET 0x0
252 /* Extracts the ALT_SPIM_CTLR0_SCPH field value from a register. */
253 #define ALT_SPIM_CTLR0_SCPH_GET(value) (((value) & 0x00000040) >> 6)
254 /* Produces a ALT_SPIM_CTLR0_SCPH register field value suitable for setting the register. */
255 #define ALT_SPIM_CTLR0_SCPH_SET(value) (((value) << 6) & 0x00000040)
256 
257 /*
258  * Field : Serial Clock Polarity - scpol
259  *
260  * Valid when the frame format (FRF) is set to Motorola SPI. Used to select the
261  * polarity of the inactive serial clock, which is held inactive when the SPI
262  * Master is not actively transferring data on the serial bus.
263  *
264  * Field Enumeration Values:
265  *
266  * Enum | Value | Description
267  * :---------------------------------|:------|:---------------------------------------
268  * ALT_SPIM_CTLR0_SCPOL_E_INACTLOW | 0x0 | Inactive state of serial clock is low
269  * ALT_SPIM_CTLR0_SCPOL_E_INACTHIGH | 0x1 | Inactive state of serial clock is high
270  *
271  * Field Access Macros:
272  *
273  */
274 /*
275  * Enumerated value for register field ALT_SPIM_CTLR0_SCPOL
276  *
277  * Inactive state of serial clock is low
278  */
279 #define ALT_SPIM_CTLR0_SCPOL_E_INACTLOW 0x0
280 /*
281  * Enumerated value for register field ALT_SPIM_CTLR0_SCPOL
282  *
283  * Inactive state of serial clock is high
284  */
285 #define ALT_SPIM_CTLR0_SCPOL_E_INACTHIGH 0x1
286 
287 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR0_SCPOL register field. */
288 #define ALT_SPIM_CTLR0_SCPOL_LSB 7
289 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR0_SCPOL register field. */
290 #define ALT_SPIM_CTLR0_SCPOL_MSB 7
291 /* The width in bits of the ALT_SPIM_CTLR0_SCPOL register field. */
292 #define ALT_SPIM_CTLR0_SCPOL_WIDTH 1
293 /* The mask used to set the ALT_SPIM_CTLR0_SCPOL register field value. */
294 #define ALT_SPIM_CTLR0_SCPOL_SET_MSK 0x00000080
295 /* The mask used to clear the ALT_SPIM_CTLR0_SCPOL register field value. */
296 #define ALT_SPIM_CTLR0_SCPOL_CLR_MSK 0xffffff7f
297 /* The reset value of the ALT_SPIM_CTLR0_SCPOL register field. */
298 #define ALT_SPIM_CTLR0_SCPOL_RESET 0x0
299 /* Extracts the ALT_SPIM_CTLR0_SCPOL field value from a register. */
300 #define ALT_SPIM_CTLR0_SCPOL_GET(value) (((value) & 0x00000080) >> 7)
301 /* Produces a ALT_SPIM_CTLR0_SCPOL register field value suitable for setting the register. */
302 #define ALT_SPIM_CTLR0_SCPOL_SET(value) (((value) << 7) & 0x00000080)
303 
304 /*
305  * Field : Transfer Mode - tmod
306  *
307  * Selects the mode of transfer for serial communication. This field does not
308  * affect the transfer duplicity. Only indicates whether the receive or transmit
309  * data are valid. In transmit-only mode, data received from the external device is
310  * not valid and is not stored in the receive FIFO memory. It is overwritten on the
311  * next transfer. In receive-only mode, transmitted data are not valid. After the
312  * first write to the transmit FIFO, the same word is retransmitted for the
313  * duration of the transfer. In transmit-and-receive mode, both transmit and
314  * receive data are valid. The transfer continues until the transmit FIFO is empty.
315  * Data received from the external device are stored into the receive FIFO memory,
316  * where it can be accessed by the host processor.
317  *
318  * Field Enumeration Values:
319  *
320  * Enum | Value | Description
321  * :-----------------------------|:------|:-----------------------
322  * ALT_SPIM_CTLR0_TMOD_E_TXRX | 0x0 | Transmit & and Receive
323  * ALT_SPIM_CTLR0_TMOD_E_TXONLY | 0x1 | Transmit Only
324  * ALT_SPIM_CTLR0_TMOD_E_RXONLY | 0x2 | Receive Only
325  * ALT_SPIM_CTLR0_TMOD_E_EERD | 0x3 | EEPROM Read
326  *
327  * Field Access Macros:
328  *
329  */
330 /*
331  * Enumerated value for register field ALT_SPIM_CTLR0_TMOD
332  *
333  * Transmit & and Receive
334  */
335 #define ALT_SPIM_CTLR0_TMOD_E_TXRX 0x0
336 /*
337  * Enumerated value for register field ALT_SPIM_CTLR0_TMOD
338  *
339  * Transmit Only
340  */
341 #define ALT_SPIM_CTLR0_TMOD_E_TXONLY 0x1
342 /*
343  * Enumerated value for register field ALT_SPIM_CTLR0_TMOD
344  *
345  * Receive Only
346  */
347 #define ALT_SPIM_CTLR0_TMOD_E_RXONLY 0x2
348 /*
349  * Enumerated value for register field ALT_SPIM_CTLR0_TMOD
350  *
351  * EEPROM Read
352  */
353 #define ALT_SPIM_CTLR0_TMOD_E_EERD 0x3
354 
355 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR0_TMOD register field. */
356 #define ALT_SPIM_CTLR0_TMOD_LSB 8
357 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR0_TMOD register field. */
358 #define ALT_SPIM_CTLR0_TMOD_MSB 9
359 /* The width in bits of the ALT_SPIM_CTLR0_TMOD register field. */
360 #define ALT_SPIM_CTLR0_TMOD_WIDTH 2
361 /* The mask used to set the ALT_SPIM_CTLR0_TMOD register field value. */
362 #define ALT_SPIM_CTLR0_TMOD_SET_MSK 0x00000300
363 /* The mask used to clear the ALT_SPIM_CTLR0_TMOD register field value. */
364 #define ALT_SPIM_CTLR0_TMOD_CLR_MSK 0xfffffcff
365 /* The reset value of the ALT_SPIM_CTLR0_TMOD register field. */
366 #define ALT_SPIM_CTLR0_TMOD_RESET 0x0
367 /* Extracts the ALT_SPIM_CTLR0_TMOD field value from a register. */
368 #define ALT_SPIM_CTLR0_TMOD_GET(value) (((value) & 0x00000300) >> 8)
369 /* Produces a ALT_SPIM_CTLR0_TMOD register field value suitable for setting the register. */
370 #define ALT_SPIM_CTLR0_TMOD_SET(value) (((value) << 8) & 0x00000300)
371 
372 /*
373  * Field : Shift Register Loop - srl
374  *
375  * Used for testing purposes only. When internally active, connects the transmit
376  * shift register output to the receive shift register input.
377  *
378  * Field Enumeration Values:
379  *
380  * Enum | Value | Description
381  * :-----------------------------|:------|:----------------------
382  * ALT_SPIM_CTLR0_SRL_E_NORMMOD | 0x0 | Normal Mode Operation
383  * ALT_SPIM_CTLR0_SRL_E_TESTMOD | 0x1 | Test Mode Operation
384  *
385  * Field Access Macros:
386  *
387  */
388 /*
389  * Enumerated value for register field ALT_SPIM_CTLR0_SRL
390  *
391  * Normal Mode Operation
392  */
393 #define ALT_SPIM_CTLR0_SRL_E_NORMMOD 0x0
394 /*
395  * Enumerated value for register field ALT_SPIM_CTLR0_SRL
396  *
397  * Test Mode Operation
398  */
399 #define ALT_SPIM_CTLR0_SRL_E_TESTMOD 0x1
400 
401 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR0_SRL register field. */
402 #define ALT_SPIM_CTLR0_SRL_LSB 11
403 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR0_SRL register field. */
404 #define ALT_SPIM_CTLR0_SRL_MSB 11
405 /* The width in bits of the ALT_SPIM_CTLR0_SRL register field. */
406 #define ALT_SPIM_CTLR0_SRL_WIDTH 1
407 /* The mask used to set the ALT_SPIM_CTLR0_SRL register field value. */
408 #define ALT_SPIM_CTLR0_SRL_SET_MSK 0x00000800
409 /* The mask used to clear the ALT_SPIM_CTLR0_SRL register field value. */
410 #define ALT_SPIM_CTLR0_SRL_CLR_MSK 0xfffff7ff
411 /* The reset value of the ALT_SPIM_CTLR0_SRL register field. */
412 #define ALT_SPIM_CTLR0_SRL_RESET 0x0
413 /* Extracts the ALT_SPIM_CTLR0_SRL field value from a register. */
414 #define ALT_SPIM_CTLR0_SRL_GET(value) (((value) & 0x00000800) >> 11)
415 /* Produces a ALT_SPIM_CTLR0_SRL register field value suitable for setting the register. */
416 #define ALT_SPIM_CTLR0_SRL_SET(value) (((value) << 11) & 0x00000800)
417 
418 /*
419  * Field : Control Frame Size - cfs
420  *
421  * Selects the length of the control word for the Microwire frame format. The
422  * length (in bits) is the value of this field plus 1.
423  *
424  * Field Access Macros:
425  *
426  */
427 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR0_CFS register field. */
428 #define ALT_SPIM_CTLR0_CFS_LSB 12
429 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR0_CFS register field. */
430 #define ALT_SPIM_CTLR0_CFS_MSB 15
431 /* The width in bits of the ALT_SPIM_CTLR0_CFS register field. */
432 #define ALT_SPIM_CTLR0_CFS_WIDTH 4
433 /* The mask used to set the ALT_SPIM_CTLR0_CFS register field value. */
434 #define ALT_SPIM_CTLR0_CFS_SET_MSK 0x0000f000
435 /* The mask used to clear the ALT_SPIM_CTLR0_CFS register field value. */
436 #define ALT_SPIM_CTLR0_CFS_CLR_MSK 0xffff0fff
437 /* The reset value of the ALT_SPIM_CTLR0_CFS register field. */
438 #define ALT_SPIM_CTLR0_CFS_RESET 0x0
439 /* Extracts the ALT_SPIM_CTLR0_CFS field value from a register. */
440 #define ALT_SPIM_CTLR0_CFS_GET(value) (((value) & 0x0000f000) >> 12)
441 /* Produces a ALT_SPIM_CTLR0_CFS register field value suitable for setting the register. */
442 #define ALT_SPIM_CTLR0_CFS_SET(value) (((value) << 12) & 0x0000f000)
443 
444 #ifndef __ASSEMBLY__
445 /*
446  * WARNING: The C register and register group struct declarations are provided for
447  * convenience and illustrative purposes. They should, however, be used with
448  * caution as the C language standard provides no guarantees about the alignment or
449  * atomicity of device memory accesses. The recommended practice for writing
450  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
451  * alt_write_word() functions.
452  *
453  * The struct declaration for register ALT_SPIM_CTLR0.
454  */
455 struct ALT_SPIM_CTLR0_s
456 {
457  uint32_t dfs : 4; /* Data Frame Size */
458  uint32_t frf : 2; /* Frame Format */
459  uint32_t scph : 1; /* Serial Clock Phase */
460  uint32_t scpol : 1; /* Serial Clock Polarity */
461  uint32_t tmod : 2; /* Transfer Mode */
462  uint32_t : 1; /* *UNDEFINED* */
463  uint32_t srl : 1; /* Shift Register Loop */
464  uint32_t cfs : 4; /* Control Frame Size */
465  uint32_t : 16; /* *UNDEFINED* */
466 };
467 
468 /* The typedef declaration for register ALT_SPIM_CTLR0. */
469 typedef volatile struct ALT_SPIM_CTLR0_s ALT_SPIM_CTLR0_t;
470 #endif /* __ASSEMBLY__ */
471 
472 /* The byte offset of the ALT_SPIM_CTLR0 register from the beginning of the component. */
473 #define ALT_SPIM_CTLR0_OFST 0x0
474 /* The address of the ALT_SPIM_CTLR0 register. */
475 #define ALT_SPIM_CTLR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_CTLR0_OFST))
476 
477 /*
478  * Register : Control Register 1 - ctrlr1
479  *
480  * Control register 1 controls the end of serial transfers when in receive-only
481  * mode. It is impossible to write to this register when the SPI Master is
482  * enabled.The SPI Master is enabled and disabled by writing to the SPIENR
483  * register.
484  *
485  * Register Layout
486  *
487  * Bits | Access | Reset | Description
488  * :--------|:-------|:------|:----------------------
489  * [15:0] | RW | 0x0 | Number of Data Frames
490  * [31:16] | ??? | 0x0 | *UNDEFINED*
491  *
492  */
493 /*
494  * Field : Number of Data Frames - ndf
495  *
496  * When TMOD = 10 or TMOD =11, this register field sets the number of data frames
497  * to be continuously received by the SPI Master. The SPI Master continues to
498  * receive serial data until the number of data frames received is equal to this
499  * register value plus 1, which enables you to receive up to 64 KB of data in a
500  * continuous transfer.
501  *
502  * Field Access Macros:
503  *
504  */
505 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR1_NDF register field. */
506 #define ALT_SPIM_CTLR1_NDF_LSB 0
507 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR1_NDF register field. */
508 #define ALT_SPIM_CTLR1_NDF_MSB 15
509 /* The width in bits of the ALT_SPIM_CTLR1_NDF register field. */
510 #define ALT_SPIM_CTLR1_NDF_WIDTH 16
511 /* The mask used to set the ALT_SPIM_CTLR1_NDF register field value. */
512 #define ALT_SPIM_CTLR1_NDF_SET_MSK 0x0000ffff
513 /* The mask used to clear the ALT_SPIM_CTLR1_NDF register field value. */
514 #define ALT_SPIM_CTLR1_NDF_CLR_MSK 0xffff0000
515 /* The reset value of the ALT_SPIM_CTLR1_NDF register field. */
516 #define ALT_SPIM_CTLR1_NDF_RESET 0x0
517 /* Extracts the ALT_SPIM_CTLR1_NDF field value from a register. */
518 #define ALT_SPIM_CTLR1_NDF_GET(value) (((value) & 0x0000ffff) >> 0)
519 /* Produces a ALT_SPIM_CTLR1_NDF register field value suitable for setting the register. */
520 #define ALT_SPIM_CTLR1_NDF_SET(value) (((value) << 0) & 0x0000ffff)
521 
522 #ifndef __ASSEMBLY__
523 /*
524  * WARNING: The C register and register group struct declarations are provided for
525  * convenience and illustrative purposes. They should, however, be used with
526  * caution as the C language standard provides no guarantees about the alignment or
527  * atomicity of device memory accesses. The recommended practice for writing
528  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
529  * alt_write_word() functions.
530  *
531  * The struct declaration for register ALT_SPIM_CTLR1.
532  */
533 struct ALT_SPIM_CTLR1_s
534 {
535  uint32_t ndf : 16; /* Number of Data Frames */
536  uint32_t : 16; /* *UNDEFINED* */
537 };
538 
539 /* The typedef declaration for register ALT_SPIM_CTLR1. */
540 typedef volatile struct ALT_SPIM_CTLR1_s ALT_SPIM_CTLR1_t;
541 #endif /* __ASSEMBLY__ */
542 
543 /* The byte offset of the ALT_SPIM_CTLR1 register from the beginning of the component. */
544 #define ALT_SPIM_CTLR1_OFST 0x4
545 /* The address of the ALT_SPIM_CTLR1 register. */
546 #define ALT_SPIM_CTLR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_CTLR1_OFST))
547 
548 /*
549  * Register : Enable Register - spienr
550  *
551  * Enables and Disables all SPI operations.
552  *
553  * Register Layout
554  *
555  * Bits | Access | Reset | Description
556  * :-------|:-------|:------|:------------
557  * [0] | RW | 0x0 | Enable
558  * [31:1] | ??? | 0x0 | *UNDEFINED*
559  *
560  */
561 /*
562  * Field : Enable - spi_en
563  *
564  * Enables and disables all SPI Master operations. When disabled, all serial
565  * transfers are halted immediately. Transmit and receive FIFO buffers are cleared
566  * when the device is disabled. It is impossible to program some of the SPI Master
567  * control registers when enabled.
568  *
569  * Field Enumeration Values:
570  *
571  * Enum | Value | Description
572  * :------------------------------|:------|:------------------------------------
573  * ALT_SPIM_SPIENR_SPI_EN_E_DISD | 0x0 | Disables serial transfer operations
574  * ALT_SPIM_SPIENR_SPI_EN_E_END | 0x1 | Enables serial transfer operations
575  *
576  * Field Access Macros:
577  *
578  */
579 /*
580  * Enumerated value for register field ALT_SPIM_SPIENR_SPI_EN
581  *
582  * Disables serial transfer operations
583  */
584 #define ALT_SPIM_SPIENR_SPI_EN_E_DISD 0x0
585 /*
586  * Enumerated value for register field ALT_SPIM_SPIENR_SPI_EN
587  *
588  * Enables serial transfer operations
589  */
590 #define ALT_SPIM_SPIENR_SPI_EN_E_END 0x1
591 
592 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SPIENR_SPI_EN register field. */
593 #define ALT_SPIM_SPIENR_SPI_EN_LSB 0
594 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SPIENR_SPI_EN register field. */
595 #define ALT_SPIM_SPIENR_SPI_EN_MSB 0
596 /* The width in bits of the ALT_SPIM_SPIENR_SPI_EN register field. */
597 #define ALT_SPIM_SPIENR_SPI_EN_WIDTH 1
598 /* The mask used to set the ALT_SPIM_SPIENR_SPI_EN register field value. */
599 #define ALT_SPIM_SPIENR_SPI_EN_SET_MSK 0x00000001
600 /* The mask used to clear the ALT_SPIM_SPIENR_SPI_EN register field value. */
601 #define ALT_SPIM_SPIENR_SPI_EN_CLR_MSK 0xfffffffe
602 /* The reset value of the ALT_SPIM_SPIENR_SPI_EN register field. */
603 #define ALT_SPIM_SPIENR_SPI_EN_RESET 0x0
604 /* Extracts the ALT_SPIM_SPIENR_SPI_EN field value from a register. */
605 #define ALT_SPIM_SPIENR_SPI_EN_GET(value) (((value) & 0x00000001) >> 0)
606 /* Produces a ALT_SPIM_SPIENR_SPI_EN register field value suitable for setting the register. */
607 #define ALT_SPIM_SPIENR_SPI_EN_SET(value) (((value) << 0) & 0x00000001)
608 
609 #ifndef __ASSEMBLY__
610 /*
611  * WARNING: The C register and register group struct declarations are provided for
612  * convenience and illustrative purposes. They should, however, be used with
613  * caution as the C language standard provides no guarantees about the alignment or
614  * atomicity of device memory accesses. The recommended practice for writing
615  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
616  * alt_write_word() functions.
617  *
618  * The struct declaration for register ALT_SPIM_SPIENR.
619  */
620 struct ALT_SPIM_SPIENR_s
621 {
622  uint32_t spi_en : 1; /* Enable */
623  uint32_t : 31; /* *UNDEFINED* */
624 };
625 
626 /* The typedef declaration for register ALT_SPIM_SPIENR. */
627 typedef volatile struct ALT_SPIM_SPIENR_s ALT_SPIM_SPIENR_t;
628 #endif /* __ASSEMBLY__ */
629 
630 /* The byte offset of the ALT_SPIM_SPIENR register from the beginning of the component. */
631 #define ALT_SPIM_SPIENR_OFST 0x8
632 /* The address of the ALT_SPIM_SPIENR register. */
633 #define ALT_SPIM_SPIENR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SPIENR_OFST))
634 
635 /*
636  * Register : Microwire Control Register - mwcr
637  *
638  * This register controls the direction of the data word for the half-duplex
639  * Microwire serial protocol. It is impossible to write to this register when the
640  * SPI Master is enabled. The SPI Master is enabled and disabled by writing to the
641  * SPIENR register.
642  *
643  * Register Layout
644  *
645  * Bits | Access | Reset | Description
646  * :-------|:-------|:------|:------------------------
647  * [0] | RW | 0x0 | Microwire Transfer Mode
648  * [1] | RW | 0x0 | Microwire Control
649  * [2] | RW | 0x0 | Microwire Handshaking
650  * [31:3] | ??? | 0x0 | *UNDEFINED*
651  *
652  */
653 /*
654  * Field : Microwire Transfer Mode - mwmod
655  *
656  * Defines whether the Microwire transfer is sequential or non-sequential. When
657  * sequential mode is used, only one control word is needed to transmit or receive
658  * a block of data words. When non-sequential mode is used, there must be a control
659  * word for each data word that is transmitted or received.
660  *
661  * Field Enumeration Values:
662  *
663  * Enum | Value | Description
664  * :-----------------------------|:------|:------------------------
665  * ALT_SPIM_MWCR_MWMOD_E_NONSEQ | 0x0 | non-sequential transfer
666  * ALT_SPIM_MWCR_MWMOD_E_SEQ | 0x1 | sequential transfer
667  *
668  * Field Access Macros:
669  *
670  */
671 /*
672  * Enumerated value for register field ALT_SPIM_MWCR_MWMOD
673  *
674  * non-sequential transfer
675  */
676 #define ALT_SPIM_MWCR_MWMOD_E_NONSEQ 0x0
677 /*
678  * Enumerated value for register field ALT_SPIM_MWCR_MWMOD
679  *
680  * sequential transfer
681  */
682 #define ALT_SPIM_MWCR_MWMOD_E_SEQ 0x1
683 
684 /* The Least Significant Bit (LSB) position of the ALT_SPIM_MWCR_MWMOD register field. */
685 #define ALT_SPIM_MWCR_MWMOD_LSB 0
686 /* The Most Significant Bit (MSB) position of the ALT_SPIM_MWCR_MWMOD register field. */
687 #define ALT_SPIM_MWCR_MWMOD_MSB 0
688 /* The width in bits of the ALT_SPIM_MWCR_MWMOD register field. */
689 #define ALT_SPIM_MWCR_MWMOD_WIDTH 1
690 /* The mask used to set the ALT_SPIM_MWCR_MWMOD register field value. */
691 #define ALT_SPIM_MWCR_MWMOD_SET_MSK 0x00000001
692 /* The mask used to clear the ALT_SPIM_MWCR_MWMOD register field value. */
693 #define ALT_SPIM_MWCR_MWMOD_CLR_MSK 0xfffffffe
694 /* The reset value of the ALT_SPIM_MWCR_MWMOD register field. */
695 #define ALT_SPIM_MWCR_MWMOD_RESET 0x0
696 /* Extracts the ALT_SPIM_MWCR_MWMOD field value from a register. */
697 #define ALT_SPIM_MWCR_MWMOD_GET(value) (((value) & 0x00000001) >> 0)
698 /* Produces a ALT_SPIM_MWCR_MWMOD register field value suitable for setting the register. */
699 #define ALT_SPIM_MWCR_MWMOD_SET(value) (((value) << 0) & 0x00000001)
700 
701 /*
702  * Field : Microwire Control - mdd
703  *
704  * Defines the direction of the data word when the Microwire serial protocol is
705  * used.
706  *
707  * Field Enumeration Values:
708  *
709  * Enum | Value | Description
710  * :--------------------------|:------|:--------------------------
711  * ALT_SPIM_MWCR_MDD_E_RXMOD | 0x0 | SPI Master receives data
712  * ALT_SPIM_MWCR_MDD_E_TXMOD | 0x1 | SPI Master transmits data
713  *
714  * Field Access Macros:
715  *
716  */
717 /*
718  * Enumerated value for register field ALT_SPIM_MWCR_MDD
719  *
720  * SPI Master receives data
721  */
722 #define ALT_SPIM_MWCR_MDD_E_RXMOD 0x0
723 /*
724  * Enumerated value for register field ALT_SPIM_MWCR_MDD
725  *
726  * SPI Master transmits data
727  */
728 #define ALT_SPIM_MWCR_MDD_E_TXMOD 0x1
729 
730 /* The Least Significant Bit (LSB) position of the ALT_SPIM_MWCR_MDD register field. */
731 #define ALT_SPIM_MWCR_MDD_LSB 1
732 /* The Most Significant Bit (MSB) position of the ALT_SPIM_MWCR_MDD register field. */
733 #define ALT_SPIM_MWCR_MDD_MSB 1
734 /* The width in bits of the ALT_SPIM_MWCR_MDD register field. */
735 #define ALT_SPIM_MWCR_MDD_WIDTH 1
736 /* The mask used to set the ALT_SPIM_MWCR_MDD register field value. */
737 #define ALT_SPIM_MWCR_MDD_SET_MSK 0x00000002
738 /* The mask used to clear the ALT_SPIM_MWCR_MDD register field value. */
739 #define ALT_SPIM_MWCR_MDD_CLR_MSK 0xfffffffd
740 /* The reset value of the ALT_SPIM_MWCR_MDD register field. */
741 #define ALT_SPIM_MWCR_MDD_RESET 0x0
742 /* Extracts the ALT_SPIM_MWCR_MDD field value from a register. */
743 #define ALT_SPIM_MWCR_MDD_GET(value) (((value) & 0x00000002) >> 1)
744 /* Produces a ALT_SPIM_MWCR_MDD register field value suitable for setting the register. */
745 #define ALT_SPIM_MWCR_MDD_SET(value) (((value) << 1) & 0x00000002)
746 
747 /*
748  * Field : Microwire Handshaking - mhs
749  *
750  * Used to enable and disable the busy/ready handshaking interface for the
751  * Microwire protocol. When enabled, the SPI Master checks for a ready status from
752  * the target slave, after the transfer of the last data/control bit, before
753  * clearing the BUSY status in the SR register.
754  *
755  * Field Enumeration Values:
756  *
757  * Enum | Value | Description
758  * :-------------------------|:------|:----------------------------------
759  * ALT_SPIM_MWCR_MHS_E_DISD | 0x0 | Handshaking interface is disabled
760  * ALT_SPIM_MWCR_MHS_E_END | 0x1 | Handshaking interface is enabled
761  *
762  * Field Access Macros:
763  *
764  */
765 /*
766  * Enumerated value for register field ALT_SPIM_MWCR_MHS
767  *
768  * Handshaking interface is disabled
769  */
770 #define ALT_SPIM_MWCR_MHS_E_DISD 0x0
771 /*
772  * Enumerated value for register field ALT_SPIM_MWCR_MHS
773  *
774  * Handshaking interface is enabled
775  */
776 #define ALT_SPIM_MWCR_MHS_E_END 0x1
777 
778 /* The Least Significant Bit (LSB) position of the ALT_SPIM_MWCR_MHS register field. */
779 #define ALT_SPIM_MWCR_MHS_LSB 2
780 /* The Most Significant Bit (MSB) position of the ALT_SPIM_MWCR_MHS register field. */
781 #define ALT_SPIM_MWCR_MHS_MSB 2
782 /* The width in bits of the ALT_SPIM_MWCR_MHS register field. */
783 #define ALT_SPIM_MWCR_MHS_WIDTH 1
784 /* The mask used to set the ALT_SPIM_MWCR_MHS register field value. */
785 #define ALT_SPIM_MWCR_MHS_SET_MSK 0x00000004
786 /* The mask used to clear the ALT_SPIM_MWCR_MHS register field value. */
787 #define ALT_SPIM_MWCR_MHS_CLR_MSK 0xfffffffb
788 /* The reset value of the ALT_SPIM_MWCR_MHS register field. */
789 #define ALT_SPIM_MWCR_MHS_RESET 0x0
790 /* Extracts the ALT_SPIM_MWCR_MHS field value from a register. */
791 #define ALT_SPIM_MWCR_MHS_GET(value) (((value) & 0x00000004) >> 2)
792 /* Produces a ALT_SPIM_MWCR_MHS register field value suitable for setting the register. */
793 #define ALT_SPIM_MWCR_MHS_SET(value) (((value) << 2) & 0x00000004)
794 
795 #ifndef __ASSEMBLY__
796 /*
797  * WARNING: The C register and register group struct declarations are provided for
798  * convenience and illustrative purposes. They should, however, be used with
799  * caution as the C language standard provides no guarantees about the alignment or
800  * atomicity of device memory accesses. The recommended practice for writing
801  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
802  * alt_write_word() functions.
803  *
804  * The struct declaration for register ALT_SPIM_MWCR.
805  */
806 struct ALT_SPIM_MWCR_s
807 {
808  uint32_t mwmod : 1; /* Microwire Transfer Mode */
809  uint32_t mdd : 1; /* Microwire Control */
810  uint32_t mhs : 1; /* Microwire Handshaking */
811  uint32_t : 29; /* *UNDEFINED* */
812 };
813 
814 /* The typedef declaration for register ALT_SPIM_MWCR. */
815 typedef volatile struct ALT_SPIM_MWCR_s ALT_SPIM_MWCR_t;
816 #endif /* __ASSEMBLY__ */
817 
818 /* The byte offset of the ALT_SPIM_MWCR register from the beginning of the component. */
819 #define ALT_SPIM_MWCR_OFST 0xc
820 /* The address of the ALT_SPIM_MWCR register. */
821 #define ALT_SPIM_MWCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_MWCR_OFST))
822 
823 /*
824  * Register : Slave Enable Register - ser
825  *
826  * The register enables the individual slave select output lines from the SPI
827  * Master. Up to 4 slave-select output pins are available on the SPI Master. You
828  * cannot write to this register when SPI Master is busy and when SPI_EN = 1.
829  *
830  * Register Layout
831  *
832  * Bits | Access | Reset | Description
833  * :-------|:-------|:------|:-------------------------
834  * [3:0] | RW | 0x0 | Slave Select Enable Flag
835  * [31:4] | ??? | 0x0 | *UNDEFINED*
836  *
837  */
838 /*
839  * Field : Slave Select Enable Flag - ser
840  *
841  * Each bit in this register corresponds to a slave select line (spim_ss_x_n] from
842  * the SPI Master. When a bit in this register is set (1), the corresponding slave
843  * select line from the master is activated when a serial transfer begins. It
844  * should be noted that setting or clearing bits in this register have no effect on
845  * the corresponding slave select outputs until a transfer is started. Before
846  * beginning a transfer, you should enable the bit in this register that
847  * corresponds to the slave device with which the master wants to communicate. When
848  * not operating in broadcast mode, only one bit in this field should be set.
849  *
850  * Field Enumeration Values:
851  *
852  * Enum | Value | Description
853  * :-------------------------------|:------|:---------------------
854  * ALT_SPIM_SER_SER_E_NOTSELECTED | 0x0 | Slave x Not Selected
855  * ALT_SPIM_SER_SER_E_SELECTED | 0x1 | Slave x Selected
856  *
857  * Field Access Macros:
858  *
859  */
860 /*
861  * Enumerated value for register field ALT_SPIM_SER_SER
862  *
863  * Slave x Not Selected
864  */
865 #define ALT_SPIM_SER_SER_E_NOTSELECTED 0x0
866 /*
867  * Enumerated value for register field ALT_SPIM_SER_SER
868  *
869  * Slave x Selected
870  */
871 #define ALT_SPIM_SER_SER_E_SELECTED 0x1
872 
873 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SER_SER register field. */
874 #define ALT_SPIM_SER_SER_LSB 0
875 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SER_SER register field. */
876 #define ALT_SPIM_SER_SER_MSB 3
877 /* The width in bits of the ALT_SPIM_SER_SER register field. */
878 #define ALT_SPIM_SER_SER_WIDTH 4
879 /* The mask used to set the ALT_SPIM_SER_SER register field value. */
880 #define ALT_SPIM_SER_SER_SET_MSK 0x0000000f
881 /* The mask used to clear the ALT_SPIM_SER_SER register field value. */
882 #define ALT_SPIM_SER_SER_CLR_MSK 0xfffffff0
883 /* The reset value of the ALT_SPIM_SER_SER register field. */
884 #define ALT_SPIM_SER_SER_RESET 0x0
885 /* Extracts the ALT_SPIM_SER_SER field value from a register. */
886 #define ALT_SPIM_SER_SER_GET(value) (((value) & 0x0000000f) >> 0)
887 /* Produces a ALT_SPIM_SER_SER register field value suitable for setting the register. */
888 #define ALT_SPIM_SER_SER_SET(value) (((value) << 0) & 0x0000000f)
889 
890 #ifndef __ASSEMBLY__
891 /*
892  * WARNING: The C register and register group struct declarations are provided for
893  * convenience and illustrative purposes. They should, however, be used with
894  * caution as the C language standard provides no guarantees about the alignment or
895  * atomicity of device memory accesses. The recommended practice for writing
896  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
897  * alt_write_word() functions.
898  *
899  * The struct declaration for register ALT_SPIM_SER.
900  */
901 struct ALT_SPIM_SER_s
902 {
903  uint32_t ser : 4; /* Slave Select Enable Flag */
904  uint32_t : 28; /* *UNDEFINED* */
905 };
906 
907 /* The typedef declaration for register ALT_SPIM_SER. */
908 typedef volatile struct ALT_SPIM_SER_s ALT_SPIM_SER_t;
909 #endif /* __ASSEMBLY__ */
910 
911 /* The byte offset of the ALT_SPIM_SER register from the beginning of the component. */
912 #define ALT_SPIM_SER_OFST 0x10
913 /* The address of the ALT_SPIM_SER register. */
914 #define ALT_SPIM_SER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SER_OFST))
915 
916 /*
917  * Register : Baud Rate Select Register - baudr
918  *
919  * This register derives the frequency of the serial clock that regulates the data
920  * transfer. The 16-bit field in this register defines the spi_m_clk divider value.
921  * It is impossible to write to this register when the SPI Master is enabled. The
922  * SPI Master is enabled and disabled by writing to the SPIENR register.
923  *
924  * Register Layout
925  *
926  * Bits | Access | Reset | Description
927  * :--------|:-------|:------|:------------------
928  * [15:0] | RW | 0x0 | SPI Clock Divider
929  * [31:16] | ??? | 0x0 | *UNDEFINED*
930  *
931  */
932 /*
933  * Field : SPI Clock Divider - sckdv
934  *
935  * The LSB for this field is always set to 0 and is unaffected by a write
936  * operation, which ensures an even value is held in this register. If the value is
937  * 0, the serial output clock (spim_sclk_out) is disabled. The frequency of the
938  * spim_sclk_out is derived from the following equation:
939  *
940  * Fspim_sclk_out = Fspi_m_clk/SCKDV
941  *
942  * where SCKDV is any even value between 2 and 65534. For example:
943  *
944  * for Fspi_m_clk = 3.6864MHz and SCKDV =2
945  *
946  * Fspim_sclk_out = 3.6864/2 = 1.8432MHz
947  *
948  * Field Access Macros:
949  *
950  */
951 /* The Least Significant Bit (LSB) position of the ALT_SPIM_BAUDR_SCKDV register field. */
952 #define ALT_SPIM_BAUDR_SCKDV_LSB 0
953 /* The Most Significant Bit (MSB) position of the ALT_SPIM_BAUDR_SCKDV register field. */
954 #define ALT_SPIM_BAUDR_SCKDV_MSB 15
955 /* The width in bits of the ALT_SPIM_BAUDR_SCKDV register field. */
956 #define ALT_SPIM_BAUDR_SCKDV_WIDTH 16
957 /* The mask used to set the ALT_SPIM_BAUDR_SCKDV register field value. */
958 #define ALT_SPIM_BAUDR_SCKDV_SET_MSK 0x0000ffff
959 /* The mask used to clear the ALT_SPIM_BAUDR_SCKDV register field value. */
960 #define ALT_SPIM_BAUDR_SCKDV_CLR_MSK 0xffff0000
961 /* The reset value of the ALT_SPIM_BAUDR_SCKDV register field. */
962 #define ALT_SPIM_BAUDR_SCKDV_RESET 0x0
963 /* Extracts the ALT_SPIM_BAUDR_SCKDV field value from a register. */
964 #define ALT_SPIM_BAUDR_SCKDV_GET(value) (((value) & 0x0000ffff) >> 0)
965 /* Produces a ALT_SPIM_BAUDR_SCKDV register field value suitable for setting the register. */
966 #define ALT_SPIM_BAUDR_SCKDV_SET(value) (((value) << 0) & 0x0000ffff)
967 
968 #ifndef __ASSEMBLY__
969 /*
970  * WARNING: The C register and register group struct declarations are provided for
971  * convenience and illustrative purposes. They should, however, be used with
972  * caution as the C language standard provides no guarantees about the alignment or
973  * atomicity of device memory accesses. The recommended practice for writing
974  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
975  * alt_write_word() functions.
976  *
977  * The struct declaration for register ALT_SPIM_BAUDR.
978  */
979 struct ALT_SPIM_BAUDR_s
980 {
981  uint32_t sckdv : 16; /* SPI Clock Divider */
982  uint32_t : 16; /* *UNDEFINED* */
983 };
984 
985 /* The typedef declaration for register ALT_SPIM_BAUDR. */
986 typedef volatile struct ALT_SPIM_BAUDR_s ALT_SPIM_BAUDR_t;
987 #endif /* __ASSEMBLY__ */
988 
989 /* The byte offset of the ALT_SPIM_BAUDR register from the beginning of the component. */
990 #define ALT_SPIM_BAUDR_OFST 0x14
991 /* The address of the ALT_SPIM_BAUDR register. */
992 #define ALT_SPIM_BAUDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_BAUDR_OFST))
993 
994 /*
995  * Register : Transmit FIFO Threshold Level Register - txftlr
996  *
997  * This register controls the threshold value for the transmit FIFO memory. It is
998  * impossible to write to this register when the SPI Master is enabled. The SPI
999  * Master is enabled and disabled by writing to the SPIENR register.
1000  *
1001  * Register Layout
1002  *
1003  * Bits | Access | Reset | Description
1004  * :-------|:-------|:------|:------------------------------
1005  * [7:0] | RW | 0x0 | Transmit FIFO Threshold Level
1006  * [31:8] | ??? | 0x0 | *UNDEFINED*
1007  *
1008  */
1009 /*
1010  * Field : Transmit FIFO Threshold Level - tft
1011  *
1012  * Controls the level of entries (or below) at which the transmit FIFO controller
1013  * triggers an interrupt. When the number of transmit FIFO entries is less than or
1014  * equal to this value, the transmit FIFO empty interrupt is triggered.
1015  *
1016  * Field Access Macros:
1017  *
1018  */
1019 /* The Least Significant Bit (LSB) position of the ALT_SPIM_TXFTLR_TFT register field. */
1020 #define ALT_SPIM_TXFTLR_TFT_LSB 0
1021 /* The Most Significant Bit (MSB) position of the ALT_SPIM_TXFTLR_TFT register field. */
1022 #define ALT_SPIM_TXFTLR_TFT_MSB 7
1023 /* The width in bits of the ALT_SPIM_TXFTLR_TFT register field. */
1024 #define ALT_SPIM_TXFTLR_TFT_WIDTH 8
1025 /* The mask used to set the ALT_SPIM_TXFTLR_TFT register field value. */
1026 #define ALT_SPIM_TXFTLR_TFT_SET_MSK 0x000000ff
1027 /* The mask used to clear the ALT_SPIM_TXFTLR_TFT register field value. */
1028 #define ALT_SPIM_TXFTLR_TFT_CLR_MSK 0xffffff00
1029 /* The reset value of the ALT_SPIM_TXFTLR_TFT register field. */
1030 #define ALT_SPIM_TXFTLR_TFT_RESET 0x0
1031 /* Extracts the ALT_SPIM_TXFTLR_TFT field value from a register. */
1032 #define ALT_SPIM_TXFTLR_TFT_GET(value) (((value) & 0x000000ff) >> 0)
1033 /* Produces a ALT_SPIM_TXFTLR_TFT register field value suitable for setting the register. */
1034 #define ALT_SPIM_TXFTLR_TFT_SET(value) (((value) << 0) & 0x000000ff)
1035 
1036 #ifndef __ASSEMBLY__
1037 /*
1038  * WARNING: The C register and register group struct declarations are provided for
1039  * convenience and illustrative purposes. They should, however, be used with
1040  * caution as the C language standard provides no guarantees about the alignment or
1041  * atomicity of device memory accesses. The recommended practice for writing
1042  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1043  * alt_write_word() functions.
1044  *
1045  * The struct declaration for register ALT_SPIM_TXFTLR.
1046  */
1047 struct ALT_SPIM_TXFTLR_s
1048 {
1049  uint32_t tft : 8; /* Transmit FIFO Threshold Level */
1050  uint32_t : 24; /* *UNDEFINED* */
1051 };
1052 
1053 /* The typedef declaration for register ALT_SPIM_TXFTLR. */
1054 typedef volatile struct ALT_SPIM_TXFTLR_s ALT_SPIM_TXFTLR_t;
1055 #endif /* __ASSEMBLY__ */
1056 
1057 /* The byte offset of the ALT_SPIM_TXFTLR register from the beginning of the component. */
1058 #define ALT_SPIM_TXFTLR_OFST 0x18
1059 /* The address of the ALT_SPIM_TXFTLR register. */
1060 #define ALT_SPIM_TXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_TXFTLR_OFST))
1061 
1062 /*
1063  * Register : Receive FIFO Threshold Level Register - rxftlr
1064  *
1065  * This register controls the threshold value for the receive FIFO memory. It is
1066  * impossible to write to this register when the SPI Master is enabled. The SPI
1067  * Master is enabled and disabled by writing to the SPIENR register.
1068  *
1069  * Register Layout
1070  *
1071  * Bits | Access | Reset | Description
1072  * :-------|:-------|:------|:-----------------------------
1073  * [7:0] | RW | 0x0 | Receive FIFO Threshold Level
1074  * [31:8] | ??? | 0x0 | *UNDEFINED*
1075  *
1076  */
1077 /*
1078  * Field : Receive FIFO Threshold Level - rft
1079  *
1080  * Controls the level of entries (or above) at which the receive FIFO controller
1081  * triggers an interrupt. When the number of receive FIFO entries is greater than
1082  * or equal to this value + 1, the receive FIFO full interrupt is triggered.
1083  *
1084  * Field Access Macros:
1085  *
1086  */
1087 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RXFTLR_RFT register field. */
1088 #define ALT_SPIM_RXFTLR_RFT_LSB 0
1089 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RXFTLR_RFT register field. */
1090 #define ALT_SPIM_RXFTLR_RFT_MSB 7
1091 /* The width in bits of the ALT_SPIM_RXFTLR_RFT register field. */
1092 #define ALT_SPIM_RXFTLR_RFT_WIDTH 8
1093 /* The mask used to set the ALT_SPIM_RXFTLR_RFT register field value. */
1094 #define ALT_SPIM_RXFTLR_RFT_SET_MSK 0x000000ff
1095 /* The mask used to clear the ALT_SPIM_RXFTLR_RFT register field value. */
1096 #define ALT_SPIM_RXFTLR_RFT_CLR_MSK 0xffffff00
1097 /* The reset value of the ALT_SPIM_RXFTLR_RFT register field. */
1098 #define ALT_SPIM_RXFTLR_RFT_RESET 0x0
1099 /* Extracts the ALT_SPIM_RXFTLR_RFT field value from a register. */
1100 #define ALT_SPIM_RXFTLR_RFT_GET(value) (((value) & 0x000000ff) >> 0)
1101 /* Produces a ALT_SPIM_RXFTLR_RFT register field value suitable for setting the register. */
1102 #define ALT_SPIM_RXFTLR_RFT_SET(value) (((value) << 0) & 0x000000ff)
1103 
1104 #ifndef __ASSEMBLY__
1105 /*
1106  * WARNING: The C register and register group struct declarations are provided for
1107  * convenience and illustrative purposes. They should, however, be used with
1108  * caution as the C language standard provides no guarantees about the alignment or
1109  * atomicity of device memory accesses. The recommended practice for writing
1110  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1111  * alt_write_word() functions.
1112  *
1113  * The struct declaration for register ALT_SPIM_RXFTLR.
1114  */
1115 struct ALT_SPIM_RXFTLR_s
1116 {
1117  uint32_t rft : 8; /* Receive FIFO Threshold Level */
1118  uint32_t : 24; /* *UNDEFINED* */
1119 };
1120 
1121 /* The typedef declaration for register ALT_SPIM_RXFTLR. */
1122 typedef volatile struct ALT_SPIM_RXFTLR_s ALT_SPIM_RXFTLR_t;
1123 #endif /* __ASSEMBLY__ */
1124 
1125 /* The byte offset of the ALT_SPIM_RXFTLR register from the beginning of the component. */
1126 #define ALT_SPIM_RXFTLR_OFST 0x1c
1127 /* The address of the ALT_SPIM_RXFTLR register. */
1128 #define ALT_SPIM_RXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXFTLR_OFST))
1129 
1130 /*
1131  * Register : Transmit FIFO Level Register - txflr
1132  *
1133  * This register contains the number of valid data entries in the transmit FIFO
1134  * memory. Ranges from 0 to 256.
1135  *
1136  * Register Layout
1137  *
1138  * Bits | Access | Reset | Description
1139  * :-------|:-------|:------|:--------------------
1140  * [8:0] | R | 0x0 | Transmit FIFO Level
1141  * [31:9] | ??? | 0x0 | *UNDEFINED*
1142  *
1143  */
1144 /*
1145  * Field : Transmit FIFO Level - txtfl
1146  *
1147  * Contains the number of valid data entries in the transmit FIFO.
1148  *
1149  * Field Access Macros:
1150  *
1151  */
1152 /* The Least Significant Bit (LSB) position of the ALT_SPIM_TXFLR_TXTFL register field. */
1153 #define ALT_SPIM_TXFLR_TXTFL_LSB 0
1154 /* The Most Significant Bit (MSB) position of the ALT_SPIM_TXFLR_TXTFL register field. */
1155 #define ALT_SPIM_TXFLR_TXTFL_MSB 8
1156 /* The width in bits of the ALT_SPIM_TXFLR_TXTFL register field. */
1157 #define ALT_SPIM_TXFLR_TXTFL_WIDTH 9
1158 /* The mask used to set the ALT_SPIM_TXFLR_TXTFL register field value. */
1159 #define ALT_SPIM_TXFLR_TXTFL_SET_MSK 0x000001ff
1160 /* The mask used to clear the ALT_SPIM_TXFLR_TXTFL register field value. */
1161 #define ALT_SPIM_TXFLR_TXTFL_CLR_MSK 0xfffffe00
1162 /* The reset value of the ALT_SPIM_TXFLR_TXTFL register field. */
1163 #define ALT_SPIM_TXFLR_TXTFL_RESET 0x0
1164 /* Extracts the ALT_SPIM_TXFLR_TXTFL field value from a register. */
1165 #define ALT_SPIM_TXFLR_TXTFL_GET(value) (((value) & 0x000001ff) >> 0)
1166 /* Produces a ALT_SPIM_TXFLR_TXTFL register field value suitable for setting the register. */
1167 #define ALT_SPIM_TXFLR_TXTFL_SET(value) (((value) << 0) & 0x000001ff)
1168 
1169 #ifndef __ASSEMBLY__
1170 /*
1171  * WARNING: The C register and register group struct declarations are provided for
1172  * convenience and illustrative purposes. They should, however, be used with
1173  * caution as the C language standard provides no guarantees about the alignment or
1174  * atomicity of device memory accesses. The recommended practice for writing
1175  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1176  * alt_write_word() functions.
1177  *
1178  * The struct declaration for register ALT_SPIM_TXFLR.
1179  */
1180 struct ALT_SPIM_TXFLR_s
1181 {
1182  const uint32_t txtfl : 9; /* Transmit FIFO Level */
1183  uint32_t : 23; /* *UNDEFINED* */
1184 };
1185 
1186 /* The typedef declaration for register ALT_SPIM_TXFLR. */
1187 typedef volatile struct ALT_SPIM_TXFLR_s ALT_SPIM_TXFLR_t;
1188 #endif /* __ASSEMBLY__ */
1189 
1190 /* The byte offset of the ALT_SPIM_TXFLR register from the beginning of the component. */
1191 #define ALT_SPIM_TXFLR_OFST 0x20
1192 /* The address of the ALT_SPIM_TXFLR register. */
1193 #define ALT_SPIM_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_TXFLR_OFST))
1194 
1195 /*
1196  * Register : Receive FIFO Level Register - rxflr
1197  *
1198  * This register contains the number of valid data entries in the receive FIFO
1199  * memory. This register can be read at any time. Ranges from 0 to 256.
1200  *
1201  * Register Layout
1202  *
1203  * Bits | Access | Reset | Description
1204  * :-------|:-------|:------|:-------------------
1205  * [8:0] | R | 0x0 | Receive FIFO Level
1206  * [31:9] | ??? | 0x0 | *UNDEFINED*
1207  *
1208  */
1209 /*
1210  * Field : Receive FIFO Level - rxtfl
1211  *
1212  * Contains the number of valid data entries in the receive FIFO.
1213  *
1214  * Field Access Macros:
1215  *
1216  */
1217 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RXFLR_RXTFL register field. */
1218 #define ALT_SPIM_RXFLR_RXTFL_LSB 0
1219 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RXFLR_RXTFL register field. */
1220 #define ALT_SPIM_RXFLR_RXTFL_MSB 8
1221 /* The width in bits of the ALT_SPIM_RXFLR_RXTFL register field. */
1222 #define ALT_SPIM_RXFLR_RXTFL_WIDTH 9
1223 /* The mask used to set the ALT_SPIM_RXFLR_RXTFL register field value. */
1224 #define ALT_SPIM_RXFLR_RXTFL_SET_MSK 0x000001ff
1225 /* The mask used to clear the ALT_SPIM_RXFLR_RXTFL register field value. */
1226 #define ALT_SPIM_RXFLR_RXTFL_CLR_MSK 0xfffffe00
1227 /* The reset value of the ALT_SPIM_RXFLR_RXTFL register field. */
1228 #define ALT_SPIM_RXFLR_RXTFL_RESET 0x0
1229 /* Extracts the ALT_SPIM_RXFLR_RXTFL field value from a register. */
1230 #define ALT_SPIM_RXFLR_RXTFL_GET(value) (((value) & 0x000001ff) >> 0)
1231 /* Produces a ALT_SPIM_RXFLR_RXTFL register field value suitable for setting the register. */
1232 #define ALT_SPIM_RXFLR_RXTFL_SET(value) (((value) << 0) & 0x000001ff)
1233 
1234 #ifndef __ASSEMBLY__
1235 /*
1236  * WARNING: The C register and register group struct declarations are provided for
1237  * convenience and illustrative purposes. They should, however, be used with
1238  * caution as the C language standard provides no guarantees about the alignment or
1239  * atomicity of device memory accesses. The recommended practice for writing
1240  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1241  * alt_write_word() functions.
1242  *
1243  * The struct declaration for register ALT_SPIM_RXFLR.
1244  */
1245 struct ALT_SPIM_RXFLR_s
1246 {
1247  const uint32_t rxtfl : 9; /* Receive FIFO Level */
1248  uint32_t : 23; /* *UNDEFINED* */
1249 };
1250 
1251 /* The typedef declaration for register ALT_SPIM_RXFLR. */
1252 typedef volatile struct ALT_SPIM_RXFLR_s ALT_SPIM_RXFLR_t;
1253 #endif /* __ASSEMBLY__ */
1254 
1255 /* The byte offset of the ALT_SPIM_RXFLR register from the beginning of the component. */
1256 #define ALT_SPIM_RXFLR_OFST 0x24
1257 /* The address of the ALT_SPIM_RXFLR register. */
1258 #define ALT_SPIM_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXFLR_OFST))
1259 
1260 /*
1261  * Register : Status Register - sr
1262  *
1263  * This register is used to indicate the current transfer status, FIFO status, and
1264  * any transmission/reception errors that may have occurred. The status register
1265  * may be read at any time. None of the bits in this register request an interrupt.
1266  *
1267  * Register Layout
1268  *
1269  * Bits | Access | Reset | Description
1270  * :-------|:-------|:------|:-----------------------
1271  * [0] | R | 0x0 | SPI Busy Flag
1272  * [1] | R | 0x1 | Transmit FIFO Not Full
1273  * [2] | R | 0x1 | Transmit FIFO Empty
1274  * [3] | R | 0x0 | Receive FIFO Not Empty
1275  * [4] | R | 0x0 | Receive FIFO Full
1276  * [31:5] | ??? | 0x0 | *UNDEFINED*
1277  *
1278  */
1279 /*
1280  * Field : SPI Busy Flag - busy
1281  *
1282  * Reports the staus of a serial transfer
1283  *
1284  * Field Enumeration Values:
1285  *
1286  * Enum | Value | Description
1287  * :-------------------------|:------|:------------------------------------------
1288  * ALT_SPIM_SR_BUSY_E_INACT | 0x0 | SPI Master is inactive (idle or disabled)
1289  * ALT_SPIM_SR_BUSY_E_ACT | 0x1 | SPI Master is actively transferring data
1290  *
1291  * Field Access Macros:
1292  *
1293  */
1294 /*
1295  * Enumerated value for register field ALT_SPIM_SR_BUSY
1296  *
1297  * SPI Master is inactive (idle or disabled)
1298  */
1299 #define ALT_SPIM_SR_BUSY_E_INACT 0x0
1300 /*
1301  * Enumerated value for register field ALT_SPIM_SR_BUSY
1302  *
1303  * SPI Master is actively transferring data
1304  */
1305 #define ALT_SPIM_SR_BUSY_E_ACT 0x1
1306 
1307 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_BUSY register field. */
1308 #define ALT_SPIM_SR_BUSY_LSB 0
1309 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_BUSY register field. */
1310 #define ALT_SPIM_SR_BUSY_MSB 0
1311 /* The width in bits of the ALT_SPIM_SR_BUSY register field. */
1312 #define ALT_SPIM_SR_BUSY_WIDTH 1
1313 /* The mask used to set the ALT_SPIM_SR_BUSY register field value. */
1314 #define ALT_SPIM_SR_BUSY_SET_MSK 0x00000001
1315 /* The mask used to clear the ALT_SPIM_SR_BUSY register field value. */
1316 #define ALT_SPIM_SR_BUSY_CLR_MSK 0xfffffffe
1317 /* The reset value of the ALT_SPIM_SR_BUSY register field. */
1318 #define ALT_SPIM_SR_BUSY_RESET 0x0
1319 /* Extracts the ALT_SPIM_SR_BUSY field value from a register. */
1320 #define ALT_SPIM_SR_BUSY_GET(value) (((value) & 0x00000001) >> 0)
1321 /* Produces a ALT_SPIM_SR_BUSY register field value suitable for setting the register. */
1322 #define ALT_SPIM_SR_BUSY_SET(value) (((value) << 0) & 0x00000001)
1323 
1324 /*
1325  * Field : Transmit FIFO Not Full - tfnf
1326  *
1327  * Reports transmit FIFO condition.
1328  *
1329  * Field Enumeration Values:
1330  *
1331  * Enum | Value | Description
1332  * :---------------------------|:------|:--------------------------
1333  * ALT_SPIM_SR_TFNF_E_FULL | 0x0 | Transmit FIFO is full
1334  * ALT_SPIM_SR_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full
1335  *
1336  * Field Access Macros:
1337  *
1338  */
1339 /*
1340  * Enumerated value for register field ALT_SPIM_SR_TFNF
1341  *
1342  * Transmit FIFO is full
1343  */
1344 #define ALT_SPIM_SR_TFNF_E_FULL 0x0
1345 /*
1346  * Enumerated value for register field ALT_SPIM_SR_TFNF
1347  *
1348  * Transmit FIFO is not full
1349  */
1350 #define ALT_SPIM_SR_TFNF_E_NOTFULL 0x1
1351 
1352 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_TFNF register field. */
1353 #define ALT_SPIM_SR_TFNF_LSB 1
1354 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_TFNF register field. */
1355 #define ALT_SPIM_SR_TFNF_MSB 1
1356 /* The width in bits of the ALT_SPIM_SR_TFNF register field. */
1357 #define ALT_SPIM_SR_TFNF_WIDTH 1
1358 /* The mask used to set the ALT_SPIM_SR_TFNF register field value. */
1359 #define ALT_SPIM_SR_TFNF_SET_MSK 0x00000002
1360 /* The mask used to clear the ALT_SPIM_SR_TFNF register field value. */
1361 #define ALT_SPIM_SR_TFNF_CLR_MSK 0xfffffffd
1362 /* The reset value of the ALT_SPIM_SR_TFNF register field. */
1363 #define ALT_SPIM_SR_TFNF_RESET 0x1
1364 /* Extracts the ALT_SPIM_SR_TFNF field value from a register. */
1365 #define ALT_SPIM_SR_TFNF_GET(value) (((value) & 0x00000002) >> 1)
1366 /* Produces a ALT_SPIM_SR_TFNF register field value suitable for setting the register. */
1367 #define ALT_SPIM_SR_TFNF_SET(value) (((value) << 1) & 0x00000002)
1368 
1369 /*
1370  * Field : Transmit FIFO Empty - tfe
1371  *
1372  * Reports transmit FIFO condition.
1373  *
1374  * Field Enumeration Values:
1375  *
1376  * Enum | Value | Description
1377  * :---------------------------|:------|:---------------------------
1378  * ALT_SPIM_SR_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty
1379  * ALT_SPIM_SR_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty
1380  *
1381  * Field Access Macros:
1382  *
1383  */
1384 /*
1385  * Enumerated value for register field ALT_SPIM_SR_TFE
1386  *
1387  * Transmit FIFO is empty
1388  */
1389 #define ALT_SPIM_SR_TFE_E_EMPTY 0x1
1390 /*
1391  * Enumerated value for register field ALT_SPIM_SR_TFE
1392  *
1393  * Transmit FIFO is not empty
1394  */
1395 #define ALT_SPIM_SR_TFE_E_NOTEMPTY 0x0
1396 
1397 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_TFE register field. */
1398 #define ALT_SPIM_SR_TFE_LSB 2
1399 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_TFE register field. */
1400 #define ALT_SPIM_SR_TFE_MSB 2
1401 /* The width in bits of the ALT_SPIM_SR_TFE register field. */
1402 #define ALT_SPIM_SR_TFE_WIDTH 1
1403 /* The mask used to set the ALT_SPIM_SR_TFE register field value. */
1404 #define ALT_SPIM_SR_TFE_SET_MSK 0x00000004
1405 /* The mask used to clear the ALT_SPIM_SR_TFE register field value. */
1406 #define ALT_SPIM_SR_TFE_CLR_MSK 0xfffffffb
1407 /* The reset value of the ALT_SPIM_SR_TFE register field. */
1408 #define ALT_SPIM_SR_TFE_RESET 0x1
1409 /* Extracts the ALT_SPIM_SR_TFE field value from a register. */
1410 #define ALT_SPIM_SR_TFE_GET(value) (((value) & 0x00000004) >> 2)
1411 /* Produces a ALT_SPIM_SR_TFE register field value suitable for setting the register. */
1412 #define ALT_SPIM_SR_TFE_SET(value) (((value) << 2) & 0x00000004)
1413 
1414 /*
1415  * Field : Receive FIFO Not Empty - rfne
1416  *
1417  * Reports receive FIFO condition.
1418  *
1419  * Field Enumeration Values:
1420  *
1421  * Enum | Value | Description
1422  * :----------------------------|:------|:--------------------------
1423  * ALT_SPIM_SR_RFNE_E_EMPTY | 0x0 | Receive FIFO is empty
1424  * ALT_SPIM_SR_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty
1425  *
1426  * Field Access Macros:
1427  *
1428  */
1429 /*
1430  * Enumerated value for register field ALT_SPIM_SR_RFNE
1431  *
1432  * Receive FIFO is empty
1433  */
1434 #define ALT_SPIM_SR_RFNE_E_EMPTY 0x0
1435 /*
1436  * Enumerated value for register field ALT_SPIM_SR_RFNE
1437  *
1438  * Receive FIFO is not empty
1439  */
1440 #define ALT_SPIM_SR_RFNE_E_NOTEMPTY 0x1
1441 
1442 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_RFNE register field. */
1443 #define ALT_SPIM_SR_RFNE_LSB 3
1444 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_RFNE register field. */
1445 #define ALT_SPIM_SR_RFNE_MSB 3
1446 /* The width in bits of the ALT_SPIM_SR_RFNE register field. */
1447 #define ALT_SPIM_SR_RFNE_WIDTH 1
1448 /* The mask used to set the ALT_SPIM_SR_RFNE register field value. */
1449 #define ALT_SPIM_SR_RFNE_SET_MSK 0x00000008
1450 /* The mask used to clear the ALT_SPIM_SR_RFNE register field value. */
1451 #define ALT_SPIM_SR_RFNE_CLR_MSK 0xfffffff7
1452 /* The reset value of the ALT_SPIM_SR_RFNE register field. */
1453 #define ALT_SPIM_SR_RFNE_RESET 0x0
1454 /* Extracts the ALT_SPIM_SR_RFNE field value from a register. */
1455 #define ALT_SPIM_SR_RFNE_GET(value) (((value) & 0x00000008) >> 3)
1456 /* Produces a ALT_SPIM_SR_RFNE register field value suitable for setting the register. */
1457 #define ALT_SPIM_SR_RFNE_SET(value) (((value) << 3) & 0x00000008)
1458 
1459 /*
1460  * Field : Receive FIFO Full - rff
1461  *
1462  * Reports receive FIFO condition.
1463  *
1464  * Field Enumeration Values:
1465  *
1466  * Enum | Value | Description
1467  * :--------------------------|:------|:-------------------------
1468  * ALT_SPIM_SR_RFF_E_NOTFULL | 0x0 | Receive FIFO is not full
1469  * ALT_SPIM_SR_RFF_E_FULL | 0x1 | Receive FIFO is full
1470  *
1471  * Field Access Macros:
1472  *
1473  */
1474 /*
1475  * Enumerated value for register field ALT_SPIM_SR_RFF
1476  *
1477  * Receive FIFO is not full
1478  */
1479 #define ALT_SPIM_SR_RFF_E_NOTFULL 0x0
1480 /*
1481  * Enumerated value for register field ALT_SPIM_SR_RFF
1482  *
1483  * Receive FIFO is full
1484  */
1485 #define ALT_SPIM_SR_RFF_E_FULL 0x1
1486 
1487 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_RFF register field. */
1488 #define ALT_SPIM_SR_RFF_LSB 4
1489 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_RFF register field. */
1490 #define ALT_SPIM_SR_RFF_MSB 4
1491 /* The width in bits of the ALT_SPIM_SR_RFF register field. */
1492 #define ALT_SPIM_SR_RFF_WIDTH 1
1493 /* The mask used to set the ALT_SPIM_SR_RFF register field value. */
1494 #define ALT_SPIM_SR_RFF_SET_MSK 0x00000010
1495 /* The mask used to clear the ALT_SPIM_SR_RFF register field value. */
1496 #define ALT_SPIM_SR_RFF_CLR_MSK 0xffffffef
1497 /* The reset value of the ALT_SPIM_SR_RFF register field. */
1498 #define ALT_SPIM_SR_RFF_RESET 0x0
1499 /* Extracts the ALT_SPIM_SR_RFF field value from a register. */
1500 #define ALT_SPIM_SR_RFF_GET(value) (((value) & 0x00000010) >> 4)
1501 /* Produces a ALT_SPIM_SR_RFF register field value suitable for setting the register. */
1502 #define ALT_SPIM_SR_RFF_SET(value) (((value) << 4) & 0x00000010)
1503 
1504 #ifndef __ASSEMBLY__
1505 /*
1506  * WARNING: The C register and register group struct declarations are provided for
1507  * convenience and illustrative purposes. They should, however, be used with
1508  * caution as the C language standard provides no guarantees about the alignment or
1509  * atomicity of device memory accesses. The recommended practice for writing
1510  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1511  * alt_write_word() functions.
1512  *
1513  * The struct declaration for register ALT_SPIM_SR.
1514  */
1515 struct ALT_SPIM_SR_s
1516 {
1517  const uint32_t busy : 1; /* SPI Busy Flag */
1518  const uint32_t tfnf : 1; /* Transmit FIFO Not Full */
1519  const uint32_t tfe : 1; /* Transmit FIFO Empty */
1520  const uint32_t rfne : 1; /* Receive FIFO Not Empty */
1521  const uint32_t rff : 1; /* Receive FIFO Full */
1522  uint32_t : 27; /* *UNDEFINED* */
1523 };
1524 
1525 /* The typedef declaration for register ALT_SPIM_SR. */
1526 typedef volatile struct ALT_SPIM_SR_s ALT_SPIM_SR_t;
1527 #endif /* __ASSEMBLY__ */
1528 
1529 /* The byte offset of the ALT_SPIM_SR register from the beginning of the component. */
1530 #define ALT_SPIM_SR_OFST 0x28
1531 /* The address of the ALT_SPIM_SR register. */
1532 #define ALT_SPIM_SR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SR_OFST))
1533 
1534 /*
1535  * Register : Interrupt Mask Register - imr
1536  *
1537  * This register masks or enables all interrupts generated by the SPI Master.
1538  *
1539  * Register Layout
1540  *
1541  * Bits | Access | Reset | Description
1542  * :-------|:-------|:------|:--------------------------------------
1543  * [0] | RW | 0x1 | Transmit FIFO Empty Interrupt Mask
1544  * [1] | RW | 0x1 | Transmit FIFO Overflow Interrupt Mask
1545  * [2] | RW | 0x1 | Receive FIFO Underflow Interrupt Mask
1546  * [3] | RW | 0x1 | Receive FIFO Overflow Interrupt Mask
1547  * [4] | RW | 0x1 | Receive FIFO Full Interrupt Mask
1548  * [31:5] | ??? | 0x1 | *UNDEFINED*
1549  *
1550  */
1551 /*
1552  * Field : Transmit FIFO Empty Interrupt Mask - txeim
1553  *
1554  * Empty mask.
1555  *
1556  * Field Enumeration Values:
1557  *
1558  * Enum | Value | Description
1559  * :---------------------------|:------|:--------------------------------------------
1560  * ALT_SPIM_IMR_TXEIM_E_MSKED | 0x0 | spi_txe_intr interrupt is masked (disabled)
1561  * ALT_SPIM_IMR_TXEIM_E_END | 0x1 | spi_txe_intr interrupt is enabled
1562  *
1563  * Field Access Macros:
1564  *
1565  */
1566 /*
1567  * Enumerated value for register field ALT_SPIM_IMR_TXEIM
1568  *
1569  * spi_txe_intr interrupt is masked (disabled)
1570  */
1571 #define ALT_SPIM_IMR_TXEIM_E_MSKED 0x0
1572 /*
1573  * Enumerated value for register field ALT_SPIM_IMR_TXEIM
1574  *
1575  * spi_txe_intr interrupt is enabled
1576  */
1577 #define ALT_SPIM_IMR_TXEIM_E_END 0x1
1578 
1579 /* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_TXEIM register field. */
1580 #define ALT_SPIM_IMR_TXEIM_LSB 0
1581 /* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_TXEIM register field. */
1582 #define ALT_SPIM_IMR_TXEIM_MSB 0
1583 /* The width in bits of the ALT_SPIM_IMR_TXEIM register field. */
1584 #define ALT_SPIM_IMR_TXEIM_WIDTH 1
1585 /* The mask used to set the ALT_SPIM_IMR_TXEIM register field value. */
1586 #define ALT_SPIM_IMR_TXEIM_SET_MSK 0x00000001
1587 /* The mask used to clear the ALT_SPIM_IMR_TXEIM register field value. */
1588 #define ALT_SPIM_IMR_TXEIM_CLR_MSK 0xfffffffe
1589 /* The reset value of the ALT_SPIM_IMR_TXEIM register field. */
1590 #define ALT_SPIM_IMR_TXEIM_RESET 0x1
1591 /* Extracts the ALT_SPIM_IMR_TXEIM field value from a register. */
1592 #define ALT_SPIM_IMR_TXEIM_GET(value) (((value) & 0x00000001) >> 0)
1593 /* Produces a ALT_SPIM_IMR_TXEIM register field value suitable for setting the register. */
1594 #define ALT_SPIM_IMR_TXEIM_SET(value) (((value) << 0) & 0x00000001)
1595 
1596 /*
1597  * Field : Transmit FIFO Overflow Interrupt Mask - txoim
1598  *
1599  * Overflow Mask
1600  *
1601  * Field Enumeration Values:
1602  *
1603  * Enum | Value | Description
1604  * :---------------------------|:------|:--------------------------------------------
1605  * ALT_SPIM_IMR_TXOIM_E_MSKED | 0x0 | spi_txo_intr interrupt is masked (disabled)
1606  * ALT_SPIM_IMR_TXOIM_E_END | 0x1 | spi_txo_intr interrupt is enabled
1607  *
1608  * Field Access Macros:
1609  *
1610  */
1611 /*
1612  * Enumerated value for register field ALT_SPIM_IMR_TXOIM
1613  *
1614  * spi_txo_intr interrupt is masked (disabled)
1615  */
1616 #define ALT_SPIM_IMR_TXOIM_E_MSKED 0x0
1617 /*
1618  * Enumerated value for register field ALT_SPIM_IMR_TXOIM
1619  *
1620  * spi_txo_intr interrupt is enabled
1621  */
1622 #define ALT_SPIM_IMR_TXOIM_E_END 0x1
1623 
1624 /* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_TXOIM register field. */
1625 #define ALT_SPIM_IMR_TXOIM_LSB 1
1626 /* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_TXOIM register field. */
1627 #define ALT_SPIM_IMR_TXOIM_MSB 1
1628 /* The width in bits of the ALT_SPIM_IMR_TXOIM register field. */
1629 #define ALT_SPIM_IMR_TXOIM_WIDTH 1
1630 /* The mask used to set the ALT_SPIM_IMR_TXOIM register field value. */
1631 #define ALT_SPIM_IMR_TXOIM_SET_MSK 0x00000002
1632 /* The mask used to clear the ALT_SPIM_IMR_TXOIM register field value. */
1633 #define ALT_SPIM_IMR_TXOIM_CLR_MSK 0xfffffffd
1634 /* The reset value of the ALT_SPIM_IMR_TXOIM register field. */
1635 #define ALT_SPIM_IMR_TXOIM_RESET 0x1
1636 /* Extracts the ALT_SPIM_IMR_TXOIM field value from a register. */
1637 #define ALT_SPIM_IMR_TXOIM_GET(value) (((value) & 0x00000002) >> 1)
1638 /* Produces a ALT_SPIM_IMR_TXOIM register field value suitable for setting the register. */
1639 #define ALT_SPIM_IMR_TXOIM_SET(value) (((value) << 1) & 0x00000002)
1640 
1641 /*
1642  * Field : Receive FIFO Underflow Interrupt Mask - rxuim
1643  *
1644  * Underflow Mask
1645  *
1646  * Field Enumeration Values:
1647  *
1648  * Enum | Value | Description
1649  * :---------------------------|:------|:--------------------------------------------
1650  * ALT_SPIM_IMR_RXUIM_E_MSKED | 0x0 | spi_rxu_intr interrupt is masked (disabled)
1651  * ALT_SPIM_IMR_RXUIM_E_END | 0x1 | spi_rxu_intr interrupt is enabled
1652  *
1653  * Field Access Macros:
1654  *
1655  */
1656 /*
1657  * Enumerated value for register field ALT_SPIM_IMR_RXUIM
1658  *
1659  * spi_rxu_intr interrupt is masked (disabled)
1660  */
1661 #define ALT_SPIM_IMR_RXUIM_E_MSKED 0x0
1662 /*
1663  * Enumerated value for register field ALT_SPIM_IMR_RXUIM
1664  *
1665  * spi_rxu_intr interrupt is enabled
1666  */
1667 #define ALT_SPIM_IMR_RXUIM_E_END 0x1
1668 
1669 /* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_RXUIM register field. */
1670 #define ALT_SPIM_IMR_RXUIM_LSB 2
1671 /* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_RXUIM register field. */
1672 #define ALT_SPIM_IMR_RXUIM_MSB 2
1673 /* The width in bits of the ALT_SPIM_IMR_RXUIM register field. */
1674 #define ALT_SPIM_IMR_RXUIM_WIDTH 1
1675 /* The mask used to set the ALT_SPIM_IMR_RXUIM register field value. */
1676 #define ALT_SPIM_IMR_RXUIM_SET_MSK 0x00000004
1677 /* The mask used to clear the ALT_SPIM_IMR_RXUIM register field value. */
1678 #define ALT_SPIM_IMR_RXUIM_CLR_MSK 0xfffffffb
1679 /* The reset value of the ALT_SPIM_IMR_RXUIM register field. */
1680 #define ALT_SPIM_IMR_RXUIM_RESET 0x1
1681 /* Extracts the ALT_SPIM_IMR_RXUIM field value from a register. */
1682 #define ALT_SPIM_IMR_RXUIM_GET(value) (((value) & 0x00000004) >> 2)
1683 /* Produces a ALT_SPIM_IMR_RXUIM register field value suitable for setting the register. */
1684 #define ALT_SPIM_IMR_RXUIM_SET(value) (((value) << 2) & 0x00000004)
1685 
1686 /*
1687  * Field : Receive FIFO Overflow Interrupt Mask - rxoim
1688  *
1689  * Overflow Mask.
1690  *
1691  * Field Enumeration Values:
1692  *
1693  * Enum | Value | Description
1694  * :---------------------------|:------|:--------------------------------------------
1695  * ALT_SPIM_IMR_RXOIM_E_MSKED | 0x0 | spi_rxo_intr interrupt is masked (disabled)
1696  * ALT_SPIM_IMR_RXOIM_E_END | 0x1 | spi_rxo_intr interrupt is enabled
1697  *
1698  * Field Access Macros:
1699  *
1700  */
1701 /*
1702  * Enumerated value for register field ALT_SPIM_IMR_RXOIM
1703  *
1704  * spi_rxo_intr interrupt is masked (disabled)
1705  */
1706 #define ALT_SPIM_IMR_RXOIM_E_MSKED 0x0
1707 /*
1708  * Enumerated value for register field ALT_SPIM_IMR_RXOIM
1709  *
1710  * spi_rxo_intr interrupt is enabled
1711  */
1712 #define ALT_SPIM_IMR_RXOIM_E_END 0x1
1713 
1714 /* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_RXOIM register field. */
1715 #define ALT_SPIM_IMR_RXOIM_LSB 3
1716 /* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_RXOIM register field. */
1717 #define ALT_SPIM_IMR_RXOIM_MSB 3
1718 /* The width in bits of the ALT_SPIM_IMR_RXOIM register field. */
1719 #define ALT_SPIM_IMR_RXOIM_WIDTH 1
1720 /* The mask used to set the ALT_SPIM_IMR_RXOIM register field value. */
1721 #define ALT_SPIM_IMR_RXOIM_SET_MSK 0x00000008
1722 /* The mask used to clear the ALT_SPIM_IMR_RXOIM register field value. */
1723 #define ALT_SPIM_IMR_RXOIM_CLR_MSK 0xfffffff7
1724 /* The reset value of the ALT_SPIM_IMR_RXOIM register field. */
1725 #define ALT_SPIM_IMR_RXOIM_RESET 0x1
1726 /* Extracts the ALT_SPIM_IMR_RXOIM field value from a register. */
1727 #define ALT_SPIM_IMR_RXOIM_GET(value) (((value) & 0x00000008) >> 3)
1728 /* Produces a ALT_SPIM_IMR_RXOIM register field value suitable for setting the register. */
1729 #define ALT_SPIM_IMR_RXOIM_SET(value) (((value) << 3) & 0x00000008)
1730 
1731 /*
1732  * Field : Receive FIFO Full Interrupt Mask - rxfim
1733  *
1734  * Full Mask
1735  *
1736  * Field Enumeration Values:
1737  *
1738  * Enum | Value | Description
1739  * :---------------------------|:------|:--------------------------------------------
1740  * ALT_SPIM_IMR_RXFIM_E_MSKED | 0x0 | spi_rxf_intr interrupt is masked (disabled)
1741  * ALT_SPIM_IMR_RXFIM_E_END | 0x1 | spi_rxf_intr interrupt is enabled
1742  *
1743  * Field Access Macros:
1744  *
1745  */
1746 /*
1747  * Enumerated value for register field ALT_SPIM_IMR_RXFIM
1748  *
1749  * spi_rxf_intr interrupt is masked (disabled)
1750  */
1751 #define ALT_SPIM_IMR_RXFIM_E_MSKED 0x0
1752 /*
1753  * Enumerated value for register field ALT_SPIM_IMR_RXFIM
1754  *
1755  * spi_rxf_intr interrupt is enabled
1756  */
1757 #define ALT_SPIM_IMR_RXFIM_E_END 0x1
1758 
1759 /* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_RXFIM register field. */
1760 #define ALT_SPIM_IMR_RXFIM_LSB 4
1761 /* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_RXFIM register field. */
1762 #define ALT_SPIM_IMR_RXFIM_MSB 4
1763 /* The width in bits of the ALT_SPIM_IMR_RXFIM register field. */
1764 #define ALT_SPIM_IMR_RXFIM_WIDTH 1
1765 /* The mask used to set the ALT_SPIM_IMR_RXFIM register field value. */
1766 #define ALT_SPIM_IMR_RXFIM_SET_MSK 0x00000010
1767 /* The mask used to clear the ALT_SPIM_IMR_RXFIM register field value. */
1768 #define ALT_SPIM_IMR_RXFIM_CLR_MSK 0xffffffef
1769 /* The reset value of the ALT_SPIM_IMR_RXFIM register field. */
1770 #define ALT_SPIM_IMR_RXFIM_RESET 0x1
1771 /* Extracts the ALT_SPIM_IMR_RXFIM field value from a register. */
1772 #define ALT_SPIM_IMR_RXFIM_GET(value) (((value) & 0x00000010) >> 4)
1773 /* Produces a ALT_SPIM_IMR_RXFIM register field value suitable for setting the register. */
1774 #define ALT_SPIM_IMR_RXFIM_SET(value) (((value) << 4) & 0x00000010)
1775 
1776 #ifndef __ASSEMBLY__
1777 /*
1778  * WARNING: The C register and register group struct declarations are provided for
1779  * convenience and illustrative purposes. They should, however, be used with
1780  * caution as the C language standard provides no guarantees about the alignment or
1781  * atomicity of device memory accesses. The recommended practice for writing
1782  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1783  * alt_write_word() functions.
1784  *
1785  * The struct declaration for register ALT_SPIM_IMR.
1786  */
1787 struct ALT_SPIM_IMR_s
1788 {
1789  uint32_t txeim : 1; /* Transmit FIFO Empty Interrupt Mask */
1790  uint32_t txoim : 1; /* Transmit FIFO Overflow Interrupt Mask */
1791  uint32_t rxuim : 1; /* Receive FIFO Underflow Interrupt Mask */
1792  uint32_t rxoim : 1; /* Receive FIFO Overflow Interrupt Mask */
1793  uint32_t rxfim : 1; /* Receive FIFO Full Interrupt Mask */
1794  uint32_t : 27; /* *UNDEFINED* */
1795 };
1796 
1797 /* The typedef declaration for register ALT_SPIM_IMR. */
1798 typedef volatile struct ALT_SPIM_IMR_s ALT_SPIM_IMR_t;
1799 #endif /* __ASSEMBLY__ */
1800 
1801 /* The byte offset of the ALT_SPIM_IMR register from the beginning of the component. */
1802 #define ALT_SPIM_IMR_OFST 0x2c
1803 /* The address of the ALT_SPIM_IMR register. */
1804 #define ALT_SPIM_IMR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_IMR_OFST))
1805 
1806 /*
1807  * Register : Interrupt Status Register - isr
1808  *
1809  * This register reports the status of the SPI Master interrupts after they have
1810  * been masked.
1811  *
1812  * Register Layout
1813  *
1814  * Bits | Access | Reset | Description
1815  * :-------|:-------|:------|:-----------------------------------------
1816  * [0] | R | 0x0 | Transmit FIFO Empty Interrupt Status
1817  * [1] | R | 0x0 | Transmit FIFO Overflow Interrupt Status
1818  * [2] | R | 0x0 | Receive FIFO Underflow Interrupt Status
1819  * [3] | R | 0x0 | Receive FIFO Overflow Interrupt Status
1820  * [4] | R | 0x0 | Receive FIFO Full Interrupt Status
1821  * [5] | R | 0x0 | Multi-Master Contention Interrupt Status
1822  * [31:6] | ??? | 0x0 | *UNDEFINED*
1823  *
1824  */
1825 /*
1826  * Field : Transmit FIFO Empty Interrupt Status - txeis
1827  *
1828  * Empty status.
1829  *
1830  * Field Enumeration Values:
1831  *
1832  * Enum | Value | Description
1833  * :---------------------------|:------|:-----------------------------------------------
1834  * ALT_SPIM_ISR_TXEIS_E_INACT | 0x0 | spi_txe_intr interrupt is not active after
1835  * : | | masking
1836  * ALT_SPIM_ISR_TXEIS_E_ACT | 0x1 | spi_txe_intr interrupt is active after masking
1837  *
1838  * Field Access Macros:
1839  *
1840  */
1841 /*
1842  * Enumerated value for register field ALT_SPIM_ISR_TXEIS
1843  *
1844  * spi_txe_intr interrupt is not active after masking
1845  */
1846 #define ALT_SPIM_ISR_TXEIS_E_INACT 0x0
1847 /*
1848  * Enumerated value for register field ALT_SPIM_ISR_TXEIS
1849  *
1850  * spi_txe_intr interrupt is active after masking
1851  */
1852 #define ALT_SPIM_ISR_TXEIS_E_ACT 0x1
1853 
1854 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_TXEIS register field. */
1855 #define ALT_SPIM_ISR_TXEIS_LSB 0
1856 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_TXEIS register field. */
1857 #define ALT_SPIM_ISR_TXEIS_MSB 0
1858 /* The width in bits of the ALT_SPIM_ISR_TXEIS register field. */
1859 #define ALT_SPIM_ISR_TXEIS_WIDTH 1
1860 /* The mask used to set the ALT_SPIM_ISR_TXEIS register field value. */
1861 #define ALT_SPIM_ISR_TXEIS_SET_MSK 0x00000001
1862 /* The mask used to clear the ALT_SPIM_ISR_TXEIS register field value. */
1863 #define ALT_SPIM_ISR_TXEIS_CLR_MSK 0xfffffffe
1864 /* The reset value of the ALT_SPIM_ISR_TXEIS register field. */
1865 #define ALT_SPIM_ISR_TXEIS_RESET 0x0
1866 /* Extracts the ALT_SPIM_ISR_TXEIS field value from a register. */
1867 #define ALT_SPIM_ISR_TXEIS_GET(value) (((value) & 0x00000001) >> 0)
1868 /* Produces a ALT_SPIM_ISR_TXEIS register field value suitable for setting the register. */
1869 #define ALT_SPIM_ISR_TXEIS_SET(value) (((value) << 0) & 0x00000001)
1870 
1871 /*
1872  * Field : Transmit FIFO Overflow Interrupt Status - txois
1873  *
1874  * Overflow Status.
1875  *
1876  * Field Enumeration Values:
1877  *
1878  * Enum | Value | Description
1879  * :---------------------------|:------|:-----------------------------------------------
1880  * ALT_SPIM_ISR_TXOIS_E_INACT | 0x0 | spi_txo_intr interrupt is not active after
1881  * : | | masking
1882  * ALT_SPIM_ISR_TXOIS_E_ACT | 0x1 | spi_txo_intr interrupt is active after masking
1883  *
1884  * Field Access Macros:
1885  *
1886  */
1887 /*
1888  * Enumerated value for register field ALT_SPIM_ISR_TXOIS
1889  *
1890  * spi_txo_intr interrupt is not active after masking
1891  */
1892 #define ALT_SPIM_ISR_TXOIS_E_INACT 0x0
1893 /*
1894  * Enumerated value for register field ALT_SPIM_ISR_TXOIS
1895  *
1896  * spi_txo_intr interrupt is active after masking
1897  */
1898 #define ALT_SPIM_ISR_TXOIS_E_ACT 0x1
1899 
1900 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_TXOIS register field. */
1901 #define ALT_SPIM_ISR_TXOIS_LSB 1
1902 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_TXOIS register field. */
1903 #define ALT_SPIM_ISR_TXOIS_MSB 1
1904 /* The width in bits of the ALT_SPIM_ISR_TXOIS register field. */
1905 #define ALT_SPIM_ISR_TXOIS_WIDTH 1
1906 /* The mask used to set the ALT_SPIM_ISR_TXOIS register field value. */
1907 #define ALT_SPIM_ISR_TXOIS_SET_MSK 0x00000002
1908 /* The mask used to clear the ALT_SPIM_ISR_TXOIS register field value. */
1909 #define ALT_SPIM_ISR_TXOIS_CLR_MSK 0xfffffffd
1910 /* The reset value of the ALT_SPIM_ISR_TXOIS register field. */
1911 #define ALT_SPIM_ISR_TXOIS_RESET 0x0
1912 /* Extracts the ALT_SPIM_ISR_TXOIS field value from a register. */
1913 #define ALT_SPIM_ISR_TXOIS_GET(value) (((value) & 0x00000002) >> 1)
1914 /* Produces a ALT_SPIM_ISR_TXOIS register field value suitable for setting the register. */
1915 #define ALT_SPIM_ISR_TXOIS_SET(value) (((value) << 1) & 0x00000002)
1916 
1917 /*
1918  * Field : Receive FIFO Underflow Interrupt Status - rxuis
1919  *
1920  * Underflow Status.
1921  *
1922  * Field Enumeration Values:
1923  *
1924  * Enum | Value | Description
1925  * :---------------------------|:------|:-----------------------------------------------
1926  * ALT_SPIM_ISR_RXUIS_E_INACT | 0x0 | spi_rxu_intr interrupt is not active after
1927  * : | | masking
1928  * ALT_SPIM_ISR_RXUIS_E_ACT | 0x1 | spi_rxu_intr interrupt is active after masking
1929  *
1930  * Field Access Macros:
1931  *
1932  */
1933 /*
1934  * Enumerated value for register field ALT_SPIM_ISR_RXUIS
1935  *
1936  * spi_rxu_intr interrupt is not active after masking
1937  */
1938 #define ALT_SPIM_ISR_RXUIS_E_INACT 0x0
1939 /*
1940  * Enumerated value for register field ALT_SPIM_ISR_RXUIS
1941  *
1942  * spi_rxu_intr interrupt is active after masking
1943  */
1944 #define ALT_SPIM_ISR_RXUIS_E_ACT 0x1
1945 
1946 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_RXUIS register field. */
1947 #define ALT_SPIM_ISR_RXUIS_LSB 2
1948 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_RXUIS register field. */
1949 #define ALT_SPIM_ISR_RXUIS_MSB 2
1950 /* The width in bits of the ALT_SPIM_ISR_RXUIS register field. */
1951 #define ALT_SPIM_ISR_RXUIS_WIDTH 1
1952 /* The mask used to set the ALT_SPIM_ISR_RXUIS register field value. */
1953 #define ALT_SPIM_ISR_RXUIS_SET_MSK 0x00000004
1954 /* The mask used to clear the ALT_SPIM_ISR_RXUIS register field value. */
1955 #define ALT_SPIM_ISR_RXUIS_CLR_MSK 0xfffffffb
1956 /* The reset value of the ALT_SPIM_ISR_RXUIS register field. */
1957 #define ALT_SPIM_ISR_RXUIS_RESET 0x0
1958 /* Extracts the ALT_SPIM_ISR_RXUIS field value from a register. */
1959 #define ALT_SPIM_ISR_RXUIS_GET(value) (((value) & 0x00000004) >> 2)
1960 /* Produces a ALT_SPIM_ISR_RXUIS register field value suitable for setting the register. */
1961 #define ALT_SPIM_ISR_RXUIS_SET(value) (((value) << 2) & 0x00000004)
1962 
1963 /*
1964  * Field : Receive FIFO Overflow Interrupt Status - rxois
1965  *
1966  * Overflow Status.
1967  *
1968  * Field Enumeration Values:
1969  *
1970  * Enum | Value | Description
1971  * :---------------------------|:------|:-----------------------------------------------
1972  * ALT_SPIM_ISR_RXOIS_E_INACT | 0x0 | spi_rxo_intr interrupt is not active after
1973  * : | | masking
1974  * ALT_SPIM_ISR_RXOIS_E_ACT | 0x1 | spi_rxo_intr interrupt is active after masking
1975  *
1976  * Field Access Macros:
1977  *
1978  */
1979 /*
1980  * Enumerated value for register field ALT_SPIM_ISR_RXOIS
1981  *
1982  * spi_rxo_intr interrupt is not active after masking
1983  */
1984 #define ALT_SPIM_ISR_RXOIS_E_INACT 0x0
1985 /*
1986  * Enumerated value for register field ALT_SPIM_ISR_RXOIS
1987  *
1988  * spi_rxo_intr interrupt is active after masking
1989  */
1990 #define ALT_SPIM_ISR_RXOIS_E_ACT 0x1
1991 
1992 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_RXOIS register field. */
1993 #define ALT_SPIM_ISR_RXOIS_LSB 3
1994 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_RXOIS register field. */
1995 #define ALT_SPIM_ISR_RXOIS_MSB 3
1996 /* The width in bits of the ALT_SPIM_ISR_RXOIS register field. */
1997 #define ALT_SPIM_ISR_RXOIS_WIDTH 1
1998 /* The mask used to set the ALT_SPIM_ISR_RXOIS register field value. */
1999 #define ALT_SPIM_ISR_RXOIS_SET_MSK 0x00000008
2000 /* The mask used to clear the ALT_SPIM_ISR_RXOIS register field value. */
2001 #define ALT_SPIM_ISR_RXOIS_CLR_MSK 0xfffffff7
2002 /* The reset value of the ALT_SPIM_ISR_RXOIS register field. */
2003 #define ALT_SPIM_ISR_RXOIS_RESET 0x0
2004 /* Extracts the ALT_SPIM_ISR_RXOIS field value from a register. */
2005 #define ALT_SPIM_ISR_RXOIS_GET(value) (((value) & 0x00000008) >> 3)
2006 /* Produces a ALT_SPIM_ISR_RXOIS register field value suitable for setting the register. */
2007 #define ALT_SPIM_ISR_RXOIS_SET(value) (((value) << 3) & 0x00000008)
2008 
2009 /*
2010  * Field : Receive FIFO Full Interrupt Status - rxfis
2011  *
2012  * Full Status.
2013  *
2014  * Field Enumeration Values:
2015  *
2016  * Enum | Value | Description
2017  * :---------------------------|:------|:---------------------------------------------
2018  * ALT_SPIM_ISR_RXFIS_E_INACT | 0x0 | spi_rxf_intr interrupt is not active after
2019  * : | | masking
2020  * ALT_SPIM_ISR_RXFIS_E_ACT | 0x1 | spi_rxf_intr interrupt is full after masking
2021  *
2022  * Field Access Macros:
2023  *
2024  */
2025 /*
2026  * Enumerated value for register field ALT_SPIM_ISR_RXFIS
2027  *
2028  * spi_rxf_intr interrupt is not active after masking
2029  */
2030 #define ALT_SPIM_ISR_RXFIS_E_INACT 0x0
2031 /*
2032  * Enumerated value for register field ALT_SPIM_ISR_RXFIS
2033  *
2034  * spi_rxf_intr interrupt is full after masking
2035  */
2036 #define ALT_SPIM_ISR_RXFIS_E_ACT 0x1
2037 
2038 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_RXFIS register field. */
2039 #define ALT_SPIM_ISR_RXFIS_LSB 4
2040 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_RXFIS register field. */
2041 #define ALT_SPIM_ISR_RXFIS_MSB 4
2042 /* The width in bits of the ALT_SPIM_ISR_RXFIS register field. */
2043 #define ALT_SPIM_ISR_RXFIS_WIDTH 1
2044 /* The mask used to set the ALT_SPIM_ISR_RXFIS register field value. */
2045 #define ALT_SPIM_ISR_RXFIS_SET_MSK 0x00000010
2046 /* The mask used to clear the ALT_SPIM_ISR_RXFIS register field value. */
2047 #define ALT_SPIM_ISR_RXFIS_CLR_MSK 0xffffffef
2048 /* The reset value of the ALT_SPIM_ISR_RXFIS register field. */
2049 #define ALT_SPIM_ISR_RXFIS_RESET 0x0
2050 /* Extracts the ALT_SPIM_ISR_RXFIS field value from a register. */
2051 #define ALT_SPIM_ISR_RXFIS_GET(value) (((value) & 0x00000010) >> 4)
2052 /* Produces a ALT_SPIM_ISR_RXFIS register field value suitable for setting the register. */
2053 #define ALT_SPIM_ISR_RXFIS_SET(value) (((value) << 4) & 0x00000010)
2054 
2055 /*
2056  * Field : Multi-Master Contention Interrupt Status - mstis
2057  *
2058  * Multi-master contention status.
2059  *
2060  * Field Enumeration Values:
2061  *
2062  * Enum | Value | Description
2063  * :---------------------------|:------|:--------------------------------------------
2064  * ALT_SPIM_ISR_MSTIS_E_INACT | 0x0 | 0 = ssi_mst_intr interrupt not active after
2065  * : | | masking
2066  * ALT_SPIM_ISR_MSTIS_E_ACT | 0x1 | 1 = ssi_mst_intr interrupt is active after
2067  * : | | masking
2068  *
2069  * Field Access Macros:
2070  *
2071  */
2072 /*
2073  * Enumerated value for register field ALT_SPIM_ISR_MSTIS
2074  *
2075  * 0 = ssi_mst_intr interrupt not active after masking
2076  */
2077 #define ALT_SPIM_ISR_MSTIS_E_INACT 0x0
2078 /*
2079  * Enumerated value for register field ALT_SPIM_ISR_MSTIS
2080  *
2081  * 1 = ssi_mst_intr interrupt is active after masking
2082  */
2083 #define ALT_SPIM_ISR_MSTIS_E_ACT 0x1
2084 
2085 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_MSTIS register field. */
2086 #define ALT_SPIM_ISR_MSTIS_LSB 5
2087 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_MSTIS register field. */
2088 #define ALT_SPIM_ISR_MSTIS_MSB 5
2089 /* The width in bits of the ALT_SPIM_ISR_MSTIS register field. */
2090 #define ALT_SPIM_ISR_MSTIS_WIDTH 1
2091 /* The mask used to set the ALT_SPIM_ISR_MSTIS register field value. */
2092 #define ALT_SPIM_ISR_MSTIS_SET_MSK 0x00000020
2093 /* The mask used to clear the ALT_SPIM_ISR_MSTIS register field value. */
2094 #define ALT_SPIM_ISR_MSTIS_CLR_MSK 0xffffffdf
2095 /* The reset value of the ALT_SPIM_ISR_MSTIS register field. */
2096 #define ALT_SPIM_ISR_MSTIS_RESET 0x0
2097 /* Extracts the ALT_SPIM_ISR_MSTIS field value from a register. */
2098 #define ALT_SPIM_ISR_MSTIS_GET(value) (((value) & 0x00000020) >> 5)
2099 /* Produces a ALT_SPIM_ISR_MSTIS register field value suitable for setting the register. */
2100 #define ALT_SPIM_ISR_MSTIS_SET(value) (((value) << 5) & 0x00000020)
2101 
2102 #ifndef __ASSEMBLY__
2103 /*
2104  * WARNING: The C register and register group struct declarations are provided for
2105  * convenience and illustrative purposes. They should, however, be used with
2106  * caution as the C language standard provides no guarantees about the alignment or
2107  * atomicity of device memory accesses. The recommended practice for writing
2108  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2109  * alt_write_word() functions.
2110  *
2111  * The struct declaration for register ALT_SPIM_ISR.
2112  */
2113 struct ALT_SPIM_ISR_s
2114 {
2115  const uint32_t txeis : 1; /* Transmit FIFO Empty Interrupt Status */
2116  const uint32_t txois : 1; /* Transmit FIFO Overflow Interrupt Status */
2117  const uint32_t rxuis : 1; /* Receive FIFO Underflow Interrupt Status */
2118  const uint32_t rxois : 1; /* Receive FIFO Overflow Interrupt Status */
2119  const uint32_t rxfis : 1; /* Receive FIFO Full Interrupt Status */
2120  const uint32_t mstis : 1; /* Multi-Master Contention Interrupt Status */
2121  uint32_t : 26; /* *UNDEFINED* */
2122 };
2123 
2124 /* The typedef declaration for register ALT_SPIM_ISR. */
2125 typedef volatile struct ALT_SPIM_ISR_s ALT_SPIM_ISR_t;
2126 #endif /* __ASSEMBLY__ */
2127 
2128 /* The byte offset of the ALT_SPIM_ISR register from the beginning of the component. */
2129 #define ALT_SPIM_ISR_OFST 0x30
2130 /* The address of the ALT_SPIM_ISR register. */
2131 #define ALT_SPIM_ISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_ISR_OFST))
2132 
2133 /*
2134  * Register : Raw Interrupt Status Register - risr
2135  *
2136  * This register reports the status of the SPI Master interrupts prior to masking.
2137  *
2138  * Register Layout
2139  *
2140  * Bits | Access | Reset | Description
2141  * :-------|:-------|:------|:--------------------------------------------
2142  * [0] | R | 0x0 | Transmit FIFO Empty Raw Interrupt Status
2143  * [1] | R | 0x0 | Transmit FIFO Overflow Raw Interrupt Status
2144  * [2] | R | 0x0 | Receive FIFO Underflow Raw Interrupt Status
2145  * [3] | R | 0x0 | Receive FIFO Overflow Raw Interrupt Status
2146  * [4] | R | 0x0 | Receive FIFO Full Raw Interrupt Status
2147  * [31:5] | ??? | 0x0 | *UNDEFINED*
2148  *
2149  */
2150 /*
2151  * Field : Transmit FIFO Empty Raw Interrupt Status - txeir
2152  *
2153  * The interrupt is active or inactive prior to masking.
2154  *
2155  * Field Enumeration Values:
2156  *
2157  * Enum | Value | Description
2158  * :----------------------------|:------|:-----------------------------------------------
2159  * ALT_SPIM_RISR_TXEIR_E_INACT | 0x0 | spi_txe_intr interrupt is not active prior to
2160  * : | | masking
2161  * ALT_SPIM_RISR_TXEIR_E_ACT | 0x1 | spi_txe_intr interrupt is active prior masking
2162  *
2163  * Field Access Macros:
2164  *
2165  */
2166 /*
2167  * Enumerated value for register field ALT_SPIM_RISR_TXEIR
2168  *
2169  * spi_txe_intr interrupt is not active prior to masking
2170  */
2171 #define ALT_SPIM_RISR_TXEIR_E_INACT 0x0
2172 /*
2173  * Enumerated value for register field ALT_SPIM_RISR_TXEIR
2174  *
2175  * spi_txe_intr interrupt is active prior masking
2176  */
2177 #define ALT_SPIM_RISR_TXEIR_E_ACT 0x1
2178 
2179 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_TXEIR register field. */
2180 #define ALT_SPIM_RISR_TXEIR_LSB 0
2181 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_TXEIR register field. */
2182 #define ALT_SPIM_RISR_TXEIR_MSB 0
2183 /* The width in bits of the ALT_SPIM_RISR_TXEIR register field. */
2184 #define ALT_SPIM_RISR_TXEIR_WIDTH 1
2185 /* The mask used to set the ALT_SPIM_RISR_TXEIR register field value. */
2186 #define ALT_SPIM_RISR_TXEIR_SET_MSK 0x00000001
2187 /* The mask used to clear the ALT_SPIM_RISR_TXEIR register field value. */
2188 #define ALT_SPIM_RISR_TXEIR_CLR_MSK 0xfffffffe
2189 /* The reset value of the ALT_SPIM_RISR_TXEIR register field. */
2190 #define ALT_SPIM_RISR_TXEIR_RESET 0x0
2191 /* Extracts the ALT_SPIM_RISR_TXEIR field value from a register. */
2192 #define ALT_SPIM_RISR_TXEIR_GET(value) (((value) & 0x00000001) >> 0)
2193 /* Produces a ALT_SPIM_RISR_TXEIR register field value suitable for setting the register. */
2194 #define ALT_SPIM_RISR_TXEIR_SET(value) (((value) << 0) & 0x00000001)
2195 
2196 /*
2197  * Field : Transmit FIFO Overflow Raw Interrupt Status - txoir
2198  *
2199  * The interrupt is active or inactive prior to masking.
2200  *
2201  * Field Enumeration Values:
2202  *
2203  * Enum | Value | Description
2204  * :----------------------------|:------|:-----------------------------------------------
2205  * ALT_SPIM_RISR_TXOIR_E_INACT | 0x0 | spi_txo_intr interrupt is not active prior to
2206  * : | | masking
2207  * ALT_SPIM_RISR_TXOIR_E_ACT | 0x1 | spi_txo_intr interrupt is active prior masking
2208  *
2209  * Field Access Macros:
2210  *
2211  */
2212 /*
2213  * Enumerated value for register field ALT_SPIM_RISR_TXOIR
2214  *
2215  * spi_txo_intr interrupt is not active prior to masking
2216  */
2217 #define ALT_SPIM_RISR_TXOIR_E_INACT 0x0
2218 /*
2219  * Enumerated value for register field ALT_SPIM_RISR_TXOIR
2220  *
2221  * spi_txo_intr interrupt is active prior masking
2222  */
2223 #define ALT_SPIM_RISR_TXOIR_E_ACT 0x1
2224 
2225 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_TXOIR register field. */
2226 #define ALT_SPIM_RISR_TXOIR_LSB 1
2227 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_TXOIR register field. */
2228 #define ALT_SPIM_RISR_TXOIR_MSB 1
2229 /* The width in bits of the ALT_SPIM_RISR_TXOIR register field. */
2230 #define ALT_SPIM_RISR_TXOIR_WIDTH 1
2231 /* The mask used to set the ALT_SPIM_RISR_TXOIR register field value. */
2232 #define ALT_SPIM_RISR_TXOIR_SET_MSK 0x00000002
2233 /* The mask used to clear the ALT_SPIM_RISR_TXOIR register field value. */
2234 #define ALT_SPIM_RISR_TXOIR_CLR_MSK 0xfffffffd
2235 /* The reset value of the ALT_SPIM_RISR_TXOIR register field. */
2236 #define ALT_SPIM_RISR_TXOIR_RESET 0x0
2237 /* Extracts the ALT_SPIM_RISR_TXOIR field value from a register. */
2238 #define ALT_SPIM_RISR_TXOIR_GET(value) (((value) & 0x00000002) >> 1)
2239 /* Produces a ALT_SPIM_RISR_TXOIR register field value suitable for setting the register. */
2240 #define ALT_SPIM_RISR_TXOIR_SET(value) (((value) << 1) & 0x00000002)
2241 
2242 /*
2243  * Field : Receive FIFO Underflow Raw Interrupt Status - rxuir
2244  *
2245  * The interrupt is active or inactive prior to masking.
2246  *
2247  * Field Enumeration Values:
2248  *
2249  * Enum | Value | Description
2250  * :----------------------------|:------|:----------------------------------------------
2251  * ALT_SPIM_RISR_RXUIR_E_INACT | 0x0 | spi_rxu_intr interrupt is not active prior to
2252  * : | | masking
2253  * ALT_SPIM_RISR_RXUIR_E_ACT | 0x1 | spi_rxu_intr interrupt is active prior to
2254  * : | | masking
2255  *
2256  * Field Access Macros:
2257  *
2258  */
2259 /*
2260  * Enumerated value for register field ALT_SPIM_RISR_RXUIR
2261  *
2262  * spi_rxu_intr interrupt is not active prior to masking
2263  */
2264 #define ALT_SPIM_RISR_RXUIR_E_INACT 0x0
2265 /*
2266  * Enumerated value for register field ALT_SPIM_RISR_RXUIR
2267  *
2268  * spi_rxu_intr interrupt is active prior to masking
2269  */
2270 #define ALT_SPIM_RISR_RXUIR_E_ACT 0x1
2271 
2272 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_RXUIR register field. */
2273 #define ALT_SPIM_RISR_RXUIR_LSB 2
2274 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_RXUIR register field. */
2275 #define ALT_SPIM_RISR_RXUIR_MSB 2
2276 /* The width in bits of the ALT_SPIM_RISR_RXUIR register field. */
2277 #define ALT_SPIM_RISR_RXUIR_WIDTH 1
2278 /* The mask used to set the ALT_SPIM_RISR_RXUIR register field value. */
2279 #define ALT_SPIM_RISR_RXUIR_SET_MSK 0x00000004
2280 /* The mask used to clear the ALT_SPIM_RISR_RXUIR register field value. */
2281 #define ALT_SPIM_RISR_RXUIR_CLR_MSK 0xfffffffb
2282 /* The reset value of the ALT_SPIM_RISR_RXUIR register field. */
2283 #define ALT_SPIM_RISR_RXUIR_RESET 0x0
2284 /* Extracts the ALT_SPIM_RISR_RXUIR field value from a register. */
2285 #define ALT_SPIM_RISR_RXUIR_GET(value) (((value) & 0x00000004) >> 2)
2286 /* Produces a ALT_SPIM_RISR_RXUIR register field value suitable for setting the register. */
2287 #define ALT_SPIM_RISR_RXUIR_SET(value) (((value) << 2) & 0x00000004)
2288 
2289 /*
2290  * Field : Receive FIFO Overflow Raw Interrupt Status - rxoir
2291  *
2292  * The interrupt is active or inactive prior to masking.
2293  *
2294  * Field Enumeration Values:
2295  *
2296  * Enum | Value | Description
2297  * :-------------------------------|:------|:-----------------------------------------------
2298  * ALT_SPIM_RISR_RXOIR_E_INACTOVE | 0x0 | spi_rxo_intr interrupt is not active prior to
2299  * : | | masking
2300  * ALT_SPIM_RISR_RXOIR_E_ACT | 0x1 | spi_rxo_intr interrupt is active prior masking
2301  *
2302  * Field Access Macros:
2303  *
2304  */
2305 /*
2306  * Enumerated value for register field ALT_SPIM_RISR_RXOIR
2307  *
2308  * spi_rxo_intr interrupt is not active prior to masking
2309  */
2310 #define ALT_SPIM_RISR_RXOIR_E_INACTOVE 0x0
2311 /*
2312  * Enumerated value for register field ALT_SPIM_RISR_RXOIR
2313  *
2314  * spi_rxo_intr interrupt is active prior masking
2315  */
2316 #define ALT_SPIM_RISR_RXOIR_E_ACT 0x1
2317 
2318 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_RXOIR register field. */
2319 #define ALT_SPIM_RISR_RXOIR_LSB 3
2320 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_RXOIR register field. */
2321 #define ALT_SPIM_RISR_RXOIR_MSB 3
2322 /* The width in bits of the ALT_SPIM_RISR_RXOIR register field. */
2323 #define ALT_SPIM_RISR_RXOIR_WIDTH 1
2324 /* The mask used to set the ALT_SPIM_RISR_RXOIR register field value. */
2325 #define ALT_SPIM_RISR_RXOIR_SET_MSK 0x00000008
2326 /* The mask used to clear the ALT_SPIM_RISR_RXOIR register field value. */
2327 #define ALT_SPIM_RISR_RXOIR_CLR_MSK 0xfffffff7
2328 /* The reset value of the ALT_SPIM_RISR_RXOIR register field. */
2329 #define ALT_SPIM_RISR_RXOIR_RESET 0x0
2330 /* Extracts the ALT_SPIM_RISR_RXOIR field value from a register. */
2331 #define ALT_SPIM_RISR_RXOIR_GET(value) (((value) & 0x00000008) >> 3)
2332 /* Produces a ALT_SPIM_RISR_RXOIR register field value suitable for setting the register. */
2333 #define ALT_SPIM_RISR_RXOIR_SET(value) (((value) << 3) & 0x00000008)
2334 
2335 /*
2336  * Field : Receive FIFO Full Raw Interrupt Status - rxfir
2337  *
2338  * The interrupt is active or inactive prior to masking.
2339  *
2340  * Field Enumeration Values:
2341  *
2342  * Enum | Value | Description
2343  * :----------------------------|:------|:----------------------------------------------
2344  * ALT_SPIM_RISR_RXFIR_E_INACT | 0x0 | spi_rxf_intr interrupt is not active prior to
2345  * : | | masking
2346  * ALT_SPIM_RISR_RXFIR_E_ACT | 0x1 | spi_rxf_intr interrupt is active prior to
2347  * : | | masking
2348  *
2349  * Field Access Macros:
2350  *
2351  */
2352 /*
2353  * Enumerated value for register field ALT_SPIM_RISR_RXFIR
2354  *
2355  * spi_rxf_intr interrupt is not active prior to masking
2356  */
2357 #define ALT_SPIM_RISR_RXFIR_E_INACT 0x0
2358 /*
2359  * Enumerated value for register field ALT_SPIM_RISR_RXFIR
2360  *
2361  * spi_rxf_intr interrupt is active prior to masking
2362  */
2363 #define ALT_SPIM_RISR_RXFIR_E_ACT 0x1
2364 
2365 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_RXFIR register field. */
2366 #define ALT_SPIM_RISR_RXFIR_LSB 4
2367 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_RXFIR register field. */
2368 #define ALT_SPIM_RISR_RXFIR_MSB 4
2369 /* The width in bits of the ALT_SPIM_RISR_RXFIR register field. */
2370 #define ALT_SPIM_RISR_RXFIR_WIDTH 1
2371 /* The mask used to set the ALT_SPIM_RISR_RXFIR register field value. */
2372 #define ALT_SPIM_RISR_RXFIR_SET_MSK 0x00000010
2373 /* The mask used to clear the ALT_SPIM_RISR_RXFIR register field value. */
2374 #define ALT_SPIM_RISR_RXFIR_CLR_MSK 0xffffffef
2375 /* The reset value of the ALT_SPIM_RISR_RXFIR register field. */
2376 #define ALT_SPIM_RISR_RXFIR_RESET 0x0
2377 /* Extracts the ALT_SPIM_RISR_RXFIR field value from a register. */
2378 #define ALT_SPIM_RISR_RXFIR_GET(value) (((value) & 0x00000010) >> 4)
2379 /* Produces a ALT_SPIM_RISR_RXFIR register field value suitable for setting the register. */
2380 #define ALT_SPIM_RISR_RXFIR_SET(value) (((value) << 4) & 0x00000010)
2381 
2382 #ifndef __ASSEMBLY__
2383 /*
2384  * WARNING: The C register and register group struct declarations are provided for
2385  * convenience and illustrative purposes. They should, however, be used with
2386  * caution as the C language standard provides no guarantees about the alignment or
2387  * atomicity of device memory accesses. The recommended practice for writing
2388  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2389  * alt_write_word() functions.
2390  *
2391  * The struct declaration for register ALT_SPIM_RISR.
2392  */
2393 struct ALT_SPIM_RISR_s
2394 {
2395  const uint32_t txeir : 1; /* Transmit FIFO Empty Raw Interrupt Status */
2396  const uint32_t txoir : 1; /* Transmit FIFO Overflow Raw Interrupt Status */
2397  const uint32_t rxuir : 1; /* Receive FIFO Underflow Raw Interrupt Status */
2398  const uint32_t rxoir : 1; /* Receive FIFO Overflow Raw Interrupt Status */
2399  const uint32_t rxfir : 1; /* Receive FIFO Full Raw Interrupt Status */
2400  uint32_t : 27; /* *UNDEFINED* */
2401 };
2402 
2403 /* The typedef declaration for register ALT_SPIM_RISR. */
2404 typedef volatile struct ALT_SPIM_RISR_s ALT_SPIM_RISR_t;
2405 #endif /* __ASSEMBLY__ */
2406 
2407 /* The byte offset of the ALT_SPIM_RISR register from the beginning of the component. */
2408 #define ALT_SPIM_RISR_OFST 0x34
2409 /* The address of the ALT_SPIM_RISR register. */
2410 #define ALT_SPIM_RISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RISR_OFST))
2411 
2412 /*
2413  * Register : Transmit FIFO Overflow Interrupt Clear Register - txoicr
2414  *
2415  * Transmit FIFO Overflow Interrupt Clear Register
2416  *
2417  * Register Layout
2418  *
2419  * Bits | Access | Reset | Description
2420  * :-------|:-------|:------|:---------------------------------------
2421  * [0] | R | 0x0 | Clear Transmit FIFO Overflow Interrupt
2422  * [31:1] | ??? | 0x0 | *UNDEFINED*
2423  *
2424  */
2425 /*
2426  * Field : Clear Transmit FIFO Overflow Interrupt - txoicr
2427  *
2428  * This register reflects the status of the interrupt. A read from this register
2429  * clears the spi_txo_intr interrupt; writing has no effect.
2430  *
2431  * Field Access Macros:
2432  *
2433  */
2434 /* The Least Significant Bit (LSB) position of the ALT_SPIM_TXOICR_TXOICR register field. */
2435 #define ALT_SPIM_TXOICR_TXOICR_LSB 0
2436 /* The Most Significant Bit (MSB) position of the ALT_SPIM_TXOICR_TXOICR register field. */
2437 #define ALT_SPIM_TXOICR_TXOICR_MSB 0
2438 /* The width in bits of the ALT_SPIM_TXOICR_TXOICR register field. */
2439 #define ALT_SPIM_TXOICR_TXOICR_WIDTH 1
2440 /* The mask used to set the ALT_SPIM_TXOICR_TXOICR register field value. */
2441 #define ALT_SPIM_TXOICR_TXOICR_SET_MSK 0x00000001
2442 /* The mask used to clear the ALT_SPIM_TXOICR_TXOICR register field value. */
2443 #define ALT_SPIM_TXOICR_TXOICR_CLR_MSK 0xfffffffe
2444 /* The reset value of the ALT_SPIM_TXOICR_TXOICR register field. */
2445 #define ALT_SPIM_TXOICR_TXOICR_RESET 0x0
2446 /* Extracts the ALT_SPIM_TXOICR_TXOICR field value from a register. */
2447 #define ALT_SPIM_TXOICR_TXOICR_GET(value) (((value) & 0x00000001) >> 0)
2448 /* Produces a ALT_SPIM_TXOICR_TXOICR register field value suitable for setting the register. */
2449 #define ALT_SPIM_TXOICR_TXOICR_SET(value) (((value) << 0) & 0x00000001)
2450 
2451 #ifndef __ASSEMBLY__
2452 /*
2453  * WARNING: The C register and register group struct declarations are provided for
2454  * convenience and illustrative purposes. They should, however, be used with
2455  * caution as the C language standard provides no guarantees about the alignment or
2456  * atomicity of device memory accesses. The recommended practice for writing
2457  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2458  * alt_write_word() functions.
2459  *
2460  * The struct declaration for register ALT_SPIM_TXOICR.
2461  */
2462 struct ALT_SPIM_TXOICR_s
2463 {
2464  const uint32_t txoicr : 1; /* Clear Transmit FIFO Overflow Interrupt */
2465  uint32_t : 31; /* *UNDEFINED* */
2466 };
2467 
2468 /* The typedef declaration for register ALT_SPIM_TXOICR. */
2469 typedef volatile struct ALT_SPIM_TXOICR_s ALT_SPIM_TXOICR_t;
2470 #endif /* __ASSEMBLY__ */
2471 
2472 /* The byte offset of the ALT_SPIM_TXOICR register from the beginning of the component. */
2473 #define ALT_SPIM_TXOICR_OFST 0x38
2474 /* The address of the ALT_SPIM_TXOICR register. */
2475 #define ALT_SPIM_TXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_TXOICR_OFST))
2476 
2477 /*
2478  * Register : Receive FIFO Overflow Interrupt Clear Register - rxoicr
2479  *
2480  * Receive FIFO Overflow Interrupt Clear Register
2481  *
2482  * Register Layout
2483  *
2484  * Bits | Access | Reset | Description
2485  * :-------|:-------|:------|:--------------------------------------
2486  * [0] | R | 0x0 | Clear Receive FIFO Overflow Interrupt
2487  * [31:1] | ??? | 0x0 | *UNDEFINED*
2488  *
2489  */
2490 /*
2491  * Field : Clear Receive FIFO Overflow Interrupt - rxoicr
2492  *
2493  * This register reflects the status of the interrupt. A read from this register
2494  * clears the spi_rxo_intr interrupt; writing has no effect.
2495  *
2496  * Field Access Macros:
2497  *
2498  */
2499 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RXOICR_RXOICR register field. */
2500 #define ALT_SPIM_RXOICR_RXOICR_LSB 0
2501 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RXOICR_RXOICR register field. */
2502 #define ALT_SPIM_RXOICR_RXOICR_MSB 0
2503 /* The width in bits of the ALT_SPIM_RXOICR_RXOICR register field. */
2504 #define ALT_SPIM_RXOICR_RXOICR_WIDTH 1
2505 /* The mask used to set the ALT_SPIM_RXOICR_RXOICR register field value. */
2506 #define ALT_SPIM_RXOICR_RXOICR_SET_MSK 0x00000001
2507 /* The mask used to clear the ALT_SPIM_RXOICR_RXOICR register field value. */
2508 #define ALT_SPIM_RXOICR_RXOICR_CLR_MSK 0xfffffffe
2509 /* The reset value of the ALT_SPIM_RXOICR_RXOICR register field. */
2510 #define ALT_SPIM_RXOICR_RXOICR_RESET 0x0
2511 /* Extracts the ALT_SPIM_RXOICR_RXOICR field value from a register. */
2512 #define ALT_SPIM_RXOICR_RXOICR_GET(value) (((value) & 0x00000001) >> 0)
2513 /* Produces a ALT_SPIM_RXOICR_RXOICR register field value suitable for setting the register. */
2514 #define ALT_SPIM_RXOICR_RXOICR_SET(value) (((value) << 0) & 0x00000001)
2515 
2516 #ifndef __ASSEMBLY__
2517 /*
2518  * WARNING: The C register and register group struct declarations are provided for
2519  * convenience and illustrative purposes. They should, however, be used with
2520  * caution as the C language standard provides no guarantees about the alignment or
2521  * atomicity of device memory accesses. The recommended practice for writing
2522  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2523  * alt_write_word() functions.
2524  *
2525  * The struct declaration for register ALT_SPIM_RXOICR.
2526  */
2527 struct ALT_SPIM_RXOICR_s
2528 {
2529  const uint32_t rxoicr : 1; /* Clear Receive FIFO Overflow Interrupt */
2530  uint32_t : 31; /* *UNDEFINED* */
2531 };
2532 
2533 /* The typedef declaration for register ALT_SPIM_RXOICR. */
2534 typedef volatile struct ALT_SPIM_RXOICR_s ALT_SPIM_RXOICR_t;
2535 #endif /* __ASSEMBLY__ */
2536 
2537 /* The byte offset of the ALT_SPIM_RXOICR register from the beginning of the component. */
2538 #define ALT_SPIM_RXOICR_OFST 0x3c
2539 /* The address of the ALT_SPIM_RXOICR register. */
2540 #define ALT_SPIM_RXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXOICR_OFST))
2541 
2542 /*
2543  * Register : Receive FIFO Underflow Interrupt Clear Register - rxuicr
2544  *
2545  * Receive FIFO Underflow Interrupt Clear Register
2546  *
2547  * Register Layout
2548  *
2549  * Bits | Access | Reset | Description
2550  * :-------|:-------|:------|:---------------------------------------
2551  * [0] | R | 0x0 | Clear Receive FIFO Underflow Interrupt
2552  * [31:1] | ??? | 0x0 | *UNDEFINED*
2553  *
2554  */
2555 /*
2556  * Field : Clear Receive FIFO Underflow Interrupt - rxuicr
2557  *
2558  * This register reflects the status of the interrupt. A read from this register
2559  * clears the spi_rxu_intr interrupt; writing has no effect.
2560  *
2561  * Field Access Macros:
2562  *
2563  */
2564 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RXUICR_RXUICR register field. */
2565 #define ALT_SPIM_RXUICR_RXUICR_LSB 0
2566 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RXUICR_RXUICR register field. */
2567 #define ALT_SPIM_RXUICR_RXUICR_MSB 0
2568 /* The width in bits of the ALT_SPIM_RXUICR_RXUICR register field. */
2569 #define ALT_SPIM_RXUICR_RXUICR_WIDTH 1
2570 /* The mask used to set the ALT_SPIM_RXUICR_RXUICR register field value. */
2571 #define ALT_SPIM_RXUICR_RXUICR_SET_MSK 0x00000001
2572 /* The mask used to clear the ALT_SPIM_RXUICR_RXUICR register field value. */
2573 #define ALT_SPIM_RXUICR_RXUICR_CLR_MSK 0xfffffffe
2574 /* The reset value of the ALT_SPIM_RXUICR_RXUICR register field. */
2575 #define ALT_SPIM_RXUICR_RXUICR_RESET 0x0
2576 /* Extracts the ALT_SPIM_RXUICR_RXUICR field value from a register. */
2577 #define ALT_SPIM_RXUICR_RXUICR_GET(value) (((value) & 0x00000001) >> 0)
2578 /* Produces a ALT_SPIM_RXUICR_RXUICR register field value suitable for setting the register. */
2579 #define ALT_SPIM_RXUICR_RXUICR_SET(value) (((value) << 0) & 0x00000001)
2580 
2581 #ifndef __ASSEMBLY__
2582 /*
2583  * WARNING: The C register and register group struct declarations are provided for
2584  * convenience and illustrative purposes. They should, however, be used with
2585  * caution as the C language standard provides no guarantees about the alignment or
2586  * atomicity of device memory accesses. The recommended practice for writing
2587  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2588  * alt_write_word() functions.
2589  *
2590  * The struct declaration for register ALT_SPIM_RXUICR.
2591  */
2592 struct ALT_SPIM_RXUICR_s
2593 {
2594  const uint32_t rxuicr : 1; /* Clear Receive FIFO Underflow Interrupt */
2595  uint32_t : 31; /* *UNDEFINED* */
2596 };
2597 
2598 /* The typedef declaration for register ALT_SPIM_RXUICR. */
2599 typedef volatile struct ALT_SPIM_RXUICR_s ALT_SPIM_RXUICR_t;
2600 #endif /* __ASSEMBLY__ */
2601 
2602 /* The byte offset of the ALT_SPIM_RXUICR register from the beginning of the component. */
2603 #define ALT_SPIM_RXUICR_OFST 0x40
2604 /* The address of the ALT_SPIM_RXUICR register. */
2605 #define ALT_SPIM_RXUICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXUICR_OFST))
2606 
2607 /*
2608  * Register : Interrupt Clear Register - icr
2609  *
2610  * Clear Interrupt
2611  *
2612  * Register Layout
2613  *
2614  * Bits | Access | Reset | Description
2615  * :-------|:-------|:------|:----------------
2616  * [0] | R | 0x0 | Clear Interrupt
2617  * [31:1] | ??? | 0x0 | *UNDEFINED*
2618  *
2619  */
2620 /*
2621  * Field : Clear Interrupt - icr
2622  *
2623  * This register is set if any of the interrupts are active. A read clears the
2624  * spi_txo_intr, spi_rxu_intr, spi_rxo_intr, and the spi_mst_intr interrupts.
2625  * Writing to this register has no effect.
2626  *
2627  * Field Access Macros:
2628  *
2629  */
2630 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ICR_ICR register field. */
2631 #define ALT_SPIM_ICR_ICR_LSB 0
2632 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ICR_ICR register field. */
2633 #define ALT_SPIM_ICR_ICR_MSB 0
2634 /* The width in bits of the ALT_SPIM_ICR_ICR register field. */
2635 #define ALT_SPIM_ICR_ICR_WIDTH 1
2636 /* The mask used to set the ALT_SPIM_ICR_ICR register field value. */
2637 #define ALT_SPIM_ICR_ICR_SET_MSK 0x00000001
2638 /* The mask used to clear the ALT_SPIM_ICR_ICR register field value. */
2639 #define ALT_SPIM_ICR_ICR_CLR_MSK 0xfffffffe
2640 /* The reset value of the ALT_SPIM_ICR_ICR register field. */
2641 #define ALT_SPIM_ICR_ICR_RESET 0x0
2642 /* Extracts the ALT_SPIM_ICR_ICR field value from a register. */
2643 #define ALT_SPIM_ICR_ICR_GET(value) (((value) & 0x00000001) >> 0)
2644 /* Produces a ALT_SPIM_ICR_ICR register field value suitable for setting the register. */
2645 #define ALT_SPIM_ICR_ICR_SET(value) (((value) << 0) & 0x00000001)
2646 
2647 #ifndef __ASSEMBLY__
2648 /*
2649  * WARNING: The C register and register group struct declarations are provided for
2650  * convenience and illustrative purposes. They should, however, be used with
2651  * caution as the C language standard provides no guarantees about the alignment or
2652  * atomicity of device memory accesses. The recommended practice for writing
2653  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2654  * alt_write_word() functions.
2655  *
2656  * The struct declaration for register ALT_SPIM_ICR.
2657  */
2658 struct ALT_SPIM_ICR_s
2659 {
2660  const uint32_t icr : 1; /* Clear Interrupt */
2661  uint32_t : 31; /* *UNDEFINED* */
2662 };
2663 
2664 /* The typedef declaration for register ALT_SPIM_ICR. */
2665 typedef volatile struct ALT_SPIM_ICR_s ALT_SPIM_ICR_t;
2666 #endif /* __ASSEMBLY__ */
2667 
2668 /* The byte offset of the ALT_SPIM_ICR register from the beginning of the component. */
2669 #define ALT_SPIM_ICR_OFST 0x48
2670 /* The address of the ALT_SPIM_ICR register. */
2671 #define ALT_SPIM_ICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_ICR_OFST))
2672 
2673 /*
2674  * Register : DMA Control Register - dmacr
2675  *
2676  * This register is used to enable the DMA Controller interface operation.
2677  *
2678  * Register Layout
2679  *
2680  * Bits | Access | Reset | Description
2681  * :-------|:-------|:------|:--------------------
2682  * [0] | RW | 0x0 | Receive DMA Enable
2683  * [1] | RW | 0x0 | Transmit DMA Enable
2684  * [31:2] | ??? | 0x0 | *UNDEFINED*
2685  *
2686  */
2687 /*
2688  * Field : Receive DMA Enable - rdmae
2689  *
2690  * This bit enables/disables the receive FIFO DMA channel.
2691  *
2692  * Field Enumeration Values:
2693  *
2694  * Enum | Value | Description
2695  * :----------------------------|:------|:---------------------
2696  * ALT_SPIM_DMACR_RDMAE_E_DISD | 0x0 | Receive DMA disabled
2697  * ALT_SPIM_DMACR_RDMAE_E_END | 0x1 | Receive DMA enabled
2698  *
2699  * Field Access Macros:
2700  *
2701  */
2702 /*
2703  * Enumerated value for register field ALT_SPIM_DMACR_RDMAE
2704  *
2705  * Receive DMA disabled
2706  */
2707 #define ALT_SPIM_DMACR_RDMAE_E_DISD 0x0
2708 /*
2709  * Enumerated value for register field ALT_SPIM_DMACR_RDMAE
2710  *
2711  * Receive DMA enabled
2712  */
2713 #define ALT_SPIM_DMACR_RDMAE_E_END 0x1
2714 
2715 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DMACR_RDMAE register field. */
2716 #define ALT_SPIM_DMACR_RDMAE_LSB 0
2717 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DMACR_RDMAE register field. */
2718 #define ALT_SPIM_DMACR_RDMAE_MSB 0
2719 /* The width in bits of the ALT_SPIM_DMACR_RDMAE register field. */
2720 #define ALT_SPIM_DMACR_RDMAE_WIDTH 1
2721 /* The mask used to set the ALT_SPIM_DMACR_RDMAE register field value. */
2722 #define ALT_SPIM_DMACR_RDMAE_SET_MSK 0x00000001
2723 /* The mask used to clear the ALT_SPIM_DMACR_RDMAE register field value. */
2724 #define ALT_SPIM_DMACR_RDMAE_CLR_MSK 0xfffffffe
2725 /* The reset value of the ALT_SPIM_DMACR_RDMAE register field. */
2726 #define ALT_SPIM_DMACR_RDMAE_RESET 0x0
2727 /* Extracts the ALT_SPIM_DMACR_RDMAE field value from a register. */
2728 #define ALT_SPIM_DMACR_RDMAE_GET(value) (((value) & 0x00000001) >> 0)
2729 /* Produces a ALT_SPIM_DMACR_RDMAE register field value suitable for setting the register. */
2730 #define ALT_SPIM_DMACR_RDMAE_SET(value) (((value) << 0) & 0x00000001)
2731 
2732 /*
2733  * Field : Transmit DMA Enable - tdmae
2734  *
2735  * This bit enables/disables the transmit FIFO DMA channel.
2736  *
2737  * Field Enumeration Values:
2738  *
2739  * Enum | Value | Description
2740  * :----------------------------|:------|:----------------------
2741  * ALT_SPIM_DMACR_TDMAE_E_DISD | 0x0 | Transmit DMA disabled
2742  * ALT_SPIM_DMACR_TDMAE_E_END | 0x1 | Transmit DMA enabled
2743  *
2744  * Field Access Macros:
2745  *
2746  */
2747 /*
2748  * Enumerated value for register field ALT_SPIM_DMACR_TDMAE
2749  *
2750  * Transmit DMA disabled
2751  */
2752 #define ALT_SPIM_DMACR_TDMAE_E_DISD 0x0
2753 /*
2754  * Enumerated value for register field ALT_SPIM_DMACR_TDMAE
2755  *
2756  * Transmit DMA enabled
2757  */
2758 #define ALT_SPIM_DMACR_TDMAE_E_END 0x1
2759 
2760 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DMACR_TDMAE register field. */
2761 #define ALT_SPIM_DMACR_TDMAE_LSB 1
2762 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DMACR_TDMAE register field. */
2763 #define ALT_SPIM_DMACR_TDMAE_MSB 1
2764 /* The width in bits of the ALT_SPIM_DMACR_TDMAE register field. */
2765 #define ALT_SPIM_DMACR_TDMAE_WIDTH 1
2766 /* The mask used to set the ALT_SPIM_DMACR_TDMAE register field value. */
2767 #define ALT_SPIM_DMACR_TDMAE_SET_MSK 0x00000002
2768 /* The mask used to clear the ALT_SPIM_DMACR_TDMAE register field value. */
2769 #define ALT_SPIM_DMACR_TDMAE_CLR_MSK 0xfffffffd
2770 /* The reset value of the ALT_SPIM_DMACR_TDMAE register field. */
2771 #define ALT_SPIM_DMACR_TDMAE_RESET 0x0
2772 /* Extracts the ALT_SPIM_DMACR_TDMAE field value from a register. */
2773 #define ALT_SPIM_DMACR_TDMAE_GET(value) (((value) & 0x00000002) >> 1)
2774 /* Produces a ALT_SPIM_DMACR_TDMAE register field value suitable for setting the register. */
2775 #define ALT_SPIM_DMACR_TDMAE_SET(value) (((value) << 1) & 0x00000002)
2776 
2777 #ifndef __ASSEMBLY__
2778 /*
2779  * WARNING: The C register and register group struct declarations are provided for
2780  * convenience and illustrative purposes. They should, however, be used with
2781  * caution as the C language standard provides no guarantees about the alignment or
2782  * atomicity of device memory accesses. The recommended practice for writing
2783  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2784  * alt_write_word() functions.
2785  *
2786  * The struct declaration for register ALT_SPIM_DMACR.
2787  */
2788 struct ALT_SPIM_DMACR_s
2789 {
2790  uint32_t rdmae : 1; /* Receive DMA Enable */
2791  uint32_t tdmae : 1; /* Transmit DMA Enable */
2792  uint32_t : 30; /* *UNDEFINED* */
2793 };
2794 
2795 /* The typedef declaration for register ALT_SPIM_DMACR. */
2796 typedef volatile struct ALT_SPIM_DMACR_s ALT_SPIM_DMACR_t;
2797 #endif /* __ASSEMBLY__ */
2798 
2799 /* The byte offset of the ALT_SPIM_DMACR register from the beginning of the component. */
2800 #define ALT_SPIM_DMACR_OFST 0x4c
2801 /* The address of the ALT_SPIM_DMACR register. */
2802 #define ALT_SPIM_DMACR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DMACR_OFST))
2803 
2804 /*
2805  * Register : DMA Transmit Data Level Register - dmatdlr
2806  *
2807  * Controls the FIFO Level for a DMA transmit request
2808  *
2809  * Register Layout
2810  *
2811  * Bits | Access | Reset | Description
2812  * :-------|:-------|:------|:--------------------
2813  * [7:0] | RW | 0x0 | Transmit Data Level
2814  * [31:8] | ??? | 0x0 | *UNDEFINED*
2815  *
2816  */
2817 /*
2818  * Field : Transmit Data Level - dmatdl
2819  *
2820  * This bit field controls the level at which a DMA request is made by the transmit
2821  * logic. It is equal to the watermark level; that is, the dma_tx_req signal is
2822  * generated when the number of valid data entries in the transmit FIFO is equal to
2823  * or below this field value, and TDMAE = 1.
2824  *
2825  * Field Access Macros:
2826  *
2827  */
2828 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DMATDLR_DMATDL register field. */
2829 #define ALT_SPIM_DMATDLR_DMATDL_LSB 0
2830 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DMATDLR_DMATDL register field. */
2831 #define ALT_SPIM_DMATDLR_DMATDL_MSB 7
2832 /* The width in bits of the ALT_SPIM_DMATDLR_DMATDL register field. */
2833 #define ALT_SPIM_DMATDLR_DMATDL_WIDTH 8
2834 /* The mask used to set the ALT_SPIM_DMATDLR_DMATDL register field value. */
2835 #define ALT_SPIM_DMATDLR_DMATDL_SET_MSK 0x000000ff
2836 /* The mask used to clear the ALT_SPIM_DMATDLR_DMATDL register field value. */
2837 #define ALT_SPIM_DMATDLR_DMATDL_CLR_MSK 0xffffff00
2838 /* The reset value of the ALT_SPIM_DMATDLR_DMATDL register field. */
2839 #define ALT_SPIM_DMATDLR_DMATDL_RESET 0x0
2840 /* Extracts the ALT_SPIM_DMATDLR_DMATDL field value from a register. */
2841 #define ALT_SPIM_DMATDLR_DMATDL_GET(value) (((value) & 0x000000ff) >> 0)
2842 /* Produces a ALT_SPIM_DMATDLR_DMATDL register field value suitable for setting the register. */
2843 #define ALT_SPIM_DMATDLR_DMATDL_SET(value) (((value) << 0) & 0x000000ff)
2844 
2845 #ifndef __ASSEMBLY__
2846 /*
2847  * WARNING: The C register and register group struct declarations are provided for
2848  * convenience and illustrative purposes. They should, however, be used with
2849  * caution as the C language standard provides no guarantees about the alignment or
2850  * atomicity of device memory accesses. The recommended practice for writing
2851  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2852  * alt_write_word() functions.
2853  *
2854  * The struct declaration for register ALT_SPIM_DMATDLR.
2855  */
2856 struct ALT_SPIM_DMATDLR_s
2857 {
2858  uint32_t dmatdl : 8; /* Transmit Data Level */
2859  uint32_t : 24; /* *UNDEFINED* */
2860 };
2861 
2862 /* The typedef declaration for register ALT_SPIM_DMATDLR. */
2863 typedef volatile struct ALT_SPIM_DMATDLR_s ALT_SPIM_DMATDLR_t;
2864 #endif /* __ASSEMBLY__ */
2865 
2866 /* The byte offset of the ALT_SPIM_DMATDLR register from the beginning of the component. */
2867 #define ALT_SPIM_DMATDLR_OFST 0x50
2868 /* The address of the ALT_SPIM_DMATDLR register. */
2869 #define ALT_SPIM_DMATDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DMATDLR_OFST))
2870 
2871 /*
2872  * Register : DMA Receive Data Level Register - dmardlr
2873  *
2874  * Controls the FIFO Level for a DMA receeive request
2875  *
2876  * Register Layout
2877  *
2878  * Bits | Access | Reset | Description
2879  * :-------|:-------|:------|:-------------------
2880  * [7:0] | RW | 0x0 | Receive Data Level
2881  * [31:8] | ??? | 0x0 | *UNDEFINED*
2882  *
2883  */
2884 /*
2885  * Field : Receive Data Level - dmardl
2886  *
2887  * This bit field controls the level at which a DMA request is made by the receive
2888  * logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the
2889  * number of valid data entries in the receive FIFO is equal to or above this field
2890  * value + 1, and RDMAE=1.
2891  *
2892  * Field Access Macros:
2893  *
2894  */
2895 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DMARDLR_DMARDL register field. */
2896 #define ALT_SPIM_DMARDLR_DMARDL_LSB 0
2897 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DMARDLR_DMARDL register field. */
2898 #define ALT_SPIM_DMARDLR_DMARDL_MSB 7
2899 /* The width in bits of the ALT_SPIM_DMARDLR_DMARDL register field. */
2900 #define ALT_SPIM_DMARDLR_DMARDL_WIDTH 8
2901 /* The mask used to set the ALT_SPIM_DMARDLR_DMARDL register field value. */
2902 #define ALT_SPIM_DMARDLR_DMARDL_SET_MSK 0x000000ff
2903 /* The mask used to clear the ALT_SPIM_DMARDLR_DMARDL register field value. */
2904 #define ALT_SPIM_DMARDLR_DMARDL_CLR_MSK 0xffffff00
2905 /* The reset value of the ALT_SPIM_DMARDLR_DMARDL register field. */
2906 #define ALT_SPIM_DMARDLR_DMARDL_RESET 0x0
2907 /* Extracts the ALT_SPIM_DMARDLR_DMARDL field value from a register. */
2908 #define ALT_SPIM_DMARDLR_DMARDL_GET(value) (((value) & 0x000000ff) >> 0)
2909 /* Produces a ALT_SPIM_DMARDLR_DMARDL register field value suitable for setting the register. */
2910 #define ALT_SPIM_DMARDLR_DMARDL_SET(value) (((value) << 0) & 0x000000ff)
2911 
2912 #ifndef __ASSEMBLY__
2913 /*
2914  * WARNING: The C register and register group struct declarations are provided for
2915  * convenience and illustrative purposes. They should, however, be used with
2916  * caution as the C language standard provides no guarantees about the alignment or
2917  * atomicity of device memory accesses. The recommended practice for writing
2918  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2919  * alt_write_word() functions.
2920  *
2921  * The struct declaration for register ALT_SPIM_DMARDLR.
2922  */
2923 struct ALT_SPIM_DMARDLR_s
2924 {
2925  uint32_t dmardl : 8; /* Receive Data Level */
2926  uint32_t : 24; /* *UNDEFINED* */
2927 };
2928 
2929 /* The typedef declaration for register ALT_SPIM_DMARDLR. */
2930 typedef volatile struct ALT_SPIM_DMARDLR_s ALT_SPIM_DMARDLR_t;
2931 #endif /* __ASSEMBLY__ */
2932 
2933 /* The byte offset of the ALT_SPIM_DMARDLR register from the beginning of the component. */
2934 #define ALT_SPIM_DMARDLR_OFST 0x54
2935 /* The address of the ALT_SPIM_DMARDLR register. */
2936 #define ALT_SPIM_DMARDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DMARDLR_OFST))
2937 
2938 /*
2939  * Register : Identification Register - idr
2940  *
2941  * This register contains the peripherals identification code, which is 0x05510000.
2942  *
2943  * Register Layout
2944  *
2945  * Bits | Access | Reset | Description
2946  * :-------|:-------|:----------|:------------------------
2947  * [31:0] | R | 0x5510000 | Identification Register
2948  *
2949  */
2950 /*
2951  * Field : Identification Register - idr
2952  *
2953  * This register contains the peripherals identification code
2954  *
2955  * Field Access Macros:
2956  *
2957  */
2958 /* The Least Significant Bit (LSB) position of the ALT_SPIM_IDR_IDR register field. */
2959 #define ALT_SPIM_IDR_IDR_LSB 0
2960 /* The Most Significant Bit (MSB) position of the ALT_SPIM_IDR_IDR register field. */
2961 #define ALT_SPIM_IDR_IDR_MSB 31
2962 /* The width in bits of the ALT_SPIM_IDR_IDR register field. */
2963 #define ALT_SPIM_IDR_IDR_WIDTH 32
2964 /* The mask used to set the ALT_SPIM_IDR_IDR register field value. */
2965 #define ALT_SPIM_IDR_IDR_SET_MSK 0xffffffff
2966 /* The mask used to clear the ALT_SPIM_IDR_IDR register field value. */
2967 #define ALT_SPIM_IDR_IDR_CLR_MSK 0x00000000
2968 /* The reset value of the ALT_SPIM_IDR_IDR register field. */
2969 #define ALT_SPIM_IDR_IDR_RESET 0x5510000
2970 /* Extracts the ALT_SPIM_IDR_IDR field value from a register. */
2971 #define ALT_SPIM_IDR_IDR_GET(value) (((value) & 0xffffffff) >> 0)
2972 /* Produces a ALT_SPIM_IDR_IDR register field value suitable for setting the register. */
2973 #define ALT_SPIM_IDR_IDR_SET(value) (((value) << 0) & 0xffffffff)
2974 
2975 #ifndef __ASSEMBLY__
2976 /*
2977  * WARNING: The C register and register group struct declarations are provided for
2978  * convenience and illustrative purposes. They should, however, be used with
2979  * caution as the C language standard provides no guarantees about the alignment or
2980  * atomicity of device memory accesses. The recommended practice for writing
2981  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2982  * alt_write_word() functions.
2983  *
2984  * The struct declaration for register ALT_SPIM_IDR.
2985  */
2986 struct ALT_SPIM_IDR_s
2987 {
2988  const uint32_t idr : 32; /* Identification Register */
2989 };
2990 
2991 /* The typedef declaration for register ALT_SPIM_IDR. */
2992 typedef volatile struct ALT_SPIM_IDR_s ALT_SPIM_IDR_t;
2993 #endif /* __ASSEMBLY__ */
2994 
2995 /* The byte offset of the ALT_SPIM_IDR register from the beginning of the component. */
2996 #define ALT_SPIM_IDR_OFST 0x58
2997 /* The address of the ALT_SPIM_IDR register. */
2998 #define ALT_SPIM_IDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_IDR_OFST))
2999 
3000 /*
3001  * Register : Component Version Register - spi_version_id
3002  *
3003  * Version ID Register value
3004  *
3005  * Register Layout
3006  *
3007  * Bits | Access | Reset | Description
3008  * :-------|:-------|:-----------|:----------------
3009  * [31:0] | RW | 0x3332302a | Version ID Code
3010  *
3011  */
3012 /*
3013  * Field : Version ID Code - spi_version_id
3014  *
3015  * Contains the hex representation of the Synopsys component version. Consists of
3016  * ASCII value for each number in the version.
3017  *
3018  * Field Access Macros:
3019  *
3020  */
3021 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SPI_VER_ID_SPI_VER_ID register field. */
3022 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_LSB 0
3023 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SPI_VER_ID_SPI_VER_ID register field. */
3024 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_MSB 31
3025 /* The width in bits of the ALT_SPIM_SPI_VER_ID_SPI_VER_ID register field. */
3026 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_WIDTH 32
3027 /* The mask used to set the ALT_SPIM_SPI_VER_ID_SPI_VER_ID register field value. */
3028 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_SET_MSK 0xffffffff
3029 /* The mask used to clear the ALT_SPIM_SPI_VER_ID_SPI_VER_ID register field value. */
3030 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_CLR_MSK 0x00000000
3031 /* The reset value of the ALT_SPIM_SPI_VER_ID_SPI_VER_ID register field. */
3032 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_RESET 0x3332302a
3033 /* Extracts the ALT_SPIM_SPI_VER_ID_SPI_VER_ID field value from a register. */
3034 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_GET(value) (((value) & 0xffffffff) >> 0)
3035 /* Produces a ALT_SPIM_SPI_VER_ID_SPI_VER_ID register field value suitable for setting the register. */
3036 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_SET(value) (((value) << 0) & 0xffffffff)
3037 
3038 #ifndef __ASSEMBLY__
3039 /*
3040  * WARNING: The C register and register group struct declarations are provided for
3041  * convenience and illustrative purposes. They should, however, be used with
3042  * caution as the C language standard provides no guarantees about the alignment or
3043  * atomicity of device memory accesses. The recommended practice for writing
3044  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3045  * alt_write_word() functions.
3046  *
3047  * The struct declaration for register ALT_SPIM_SPI_VER_ID.
3048  */
3049 struct ALT_SPIM_SPI_VER_ID_s
3050 {
3051  uint32_t spi_version_id : 32; /* Version ID Code */
3052 };
3053 
3054 /* The typedef declaration for register ALT_SPIM_SPI_VER_ID. */
3055 typedef volatile struct ALT_SPIM_SPI_VER_ID_s ALT_SPIM_SPI_VER_ID_t;
3056 #endif /* __ASSEMBLY__ */
3057 
3058 /* The byte offset of the ALT_SPIM_SPI_VER_ID register from the beginning of the component. */
3059 #define ALT_SPIM_SPI_VER_ID_OFST 0x5c
3060 /* The address of the ALT_SPIM_SPI_VER_ID register. */
3061 #define ALT_SPIM_SPI_VER_ID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SPI_VER_ID_OFST))
3062 
3063 /*
3064  * Register : Data Register - dr
3065  *
3066  * This register is a 16-bit read/write buffer for the transmit/receive FIFOs. When
3067  * the register is read, data in the receive FIFO buffer is accessed. When it is
3068  * written to, data are moved into the transmit FIFO buffer; a write can occur only
3069  * when SPI_EN = 1. FIFOs are reset when SPI_EN = 0.
3070  *
3071  * The data register occupies 36 32-bit locations in the address map (0x60 to
3072  * 0xec). These are all aliases for the same data register. This is done to support
3073  * burst accesses.
3074  *
3075  * Register Layout
3076  *
3077  * Bits | Access | Reset | Description
3078  * :--------|:-------|:------|:------------
3079  * [15:0] | RW | 0x0 | Data
3080  * [31:16] | ??? | 0x0 | *UNDEFINED*
3081  *
3082  */
3083 /*
3084  * Field : Data - dr
3085  *
3086  * When writing to this register, you must right-justify the data. Read data are
3087  * automatically right-justified.
3088  *
3089  * Read = Receive FIFO buffer
3090  *
3091  * Write = Transmit FIFO buffer
3092  *
3093  * Field Access Macros:
3094  *
3095  */
3096 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR_DR register field. */
3097 #define ALT_SPIM_DR_DR_LSB 0
3098 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR_DR register field. */
3099 #define ALT_SPIM_DR_DR_MSB 15
3100 /* The width in bits of the ALT_SPIM_DR_DR register field. */
3101 #define ALT_SPIM_DR_DR_WIDTH 16
3102 /* The mask used to set the ALT_SPIM_DR_DR register field value. */
3103 #define ALT_SPIM_DR_DR_SET_MSK 0x0000ffff
3104 /* The mask used to clear the ALT_SPIM_DR_DR register field value. */
3105 #define ALT_SPIM_DR_DR_CLR_MSK 0xffff0000
3106 /* The reset value of the ALT_SPIM_DR_DR register field. */
3107 #define ALT_SPIM_DR_DR_RESET 0x0
3108 /* Extracts the ALT_SPIM_DR_DR field value from a register. */
3109 #define ALT_SPIM_DR_DR_GET(value) (((value) & 0x0000ffff) >> 0)
3110 /* Produces a ALT_SPIM_DR_DR register field value suitable for setting the register. */
3111 #define ALT_SPIM_DR_DR_SET(value) (((value) << 0) & 0x0000ffff)
3112 
3113 #ifndef __ASSEMBLY__
3114 /*
3115  * WARNING: The C register and register group struct declarations are provided for
3116  * convenience and illustrative purposes. They should, however, be used with
3117  * caution as the C language standard provides no guarantees about the alignment or
3118  * atomicity of device memory accesses. The recommended practice for writing
3119  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3120  * alt_write_word() functions.
3121  *
3122  * The struct declaration for register ALT_SPIM_DR.
3123  */
3124 struct ALT_SPIM_DR_s
3125 {
3126  uint32_t dr : 16; /* Data */
3127  uint32_t : 16; /* *UNDEFINED* */
3128 };
3129 
3130 /* The typedef declaration for register ALT_SPIM_DR. */
3131 typedef volatile struct ALT_SPIM_DR_s ALT_SPIM_DR_t;
3132 #endif /* __ASSEMBLY__ */
3133 
3134 /* The byte offset of the ALT_SPIM_DR register from the beginning of the component. */
3135 #define ALT_SPIM_DR_OFST 0x60
3136 /* The address of the ALT_SPIM_DR register. */
3137 #define ALT_SPIM_DR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR_OFST))
3138 
3139 /*
3140  * Register : RX Sample Delay Register - rx_sample_dly
3141  *
3142  * This register controls the number of spi_m_clk cycles that are delayed (from the
3143  * default sample time) before the actual sample of the rxd input occurs. It is
3144  * impossible to write to this register when the SPI Master is enabled. The SPI
3145  * Master is enabled and disabled by writing to the SPIENR register.
3146  *
3147  * Register Layout
3148  *
3149  * Bits | Access | Reset | Description
3150  * :-------|:-------|:------|:--------------------------
3151  * [6:0] | RW | 0x0 | Receive Data Sample Delay
3152  * [31:7] | ??? | 0x0 | *UNDEFINED*
3153  *
3154  */
3155 /*
3156  * Field : Receive Data Sample Delay - rsd
3157  *
3158  * This register is used to delay the sample of the rxd input port. Each value
3159  * represents a single spi_m_clk delay on the sample of rxd.
3160  *
3161  * Note; If this register is programmed with a value that exceeds 64, a 0 delay
3162  * will be applied to the receive sample. The maximum delay is 64 spi_m_clk cycles.
3163  *
3164  * Field Access Macros:
3165  *
3166  */
3167 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RX_SMPL_DLY_RSD register field. */
3168 #define ALT_SPIM_RX_SMPL_DLY_RSD_LSB 0
3169 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RX_SMPL_DLY_RSD register field. */
3170 #define ALT_SPIM_RX_SMPL_DLY_RSD_MSB 6
3171 /* The width in bits of the ALT_SPIM_RX_SMPL_DLY_RSD register field. */
3172 #define ALT_SPIM_RX_SMPL_DLY_RSD_WIDTH 7
3173 /* The mask used to set the ALT_SPIM_RX_SMPL_DLY_RSD register field value. */
3174 #define ALT_SPIM_RX_SMPL_DLY_RSD_SET_MSK 0x0000007f
3175 /* The mask used to clear the ALT_SPIM_RX_SMPL_DLY_RSD register field value. */
3176 #define ALT_SPIM_RX_SMPL_DLY_RSD_CLR_MSK 0xffffff80
3177 /* The reset value of the ALT_SPIM_RX_SMPL_DLY_RSD register field. */
3178 #define ALT_SPIM_RX_SMPL_DLY_RSD_RESET 0x0
3179 /* Extracts the ALT_SPIM_RX_SMPL_DLY_RSD field value from a register. */
3180 #define ALT_SPIM_RX_SMPL_DLY_RSD_GET(value) (((value) & 0x0000007f) >> 0)
3181 /* Produces a ALT_SPIM_RX_SMPL_DLY_RSD register field value suitable for setting the register. */
3182 #define ALT_SPIM_RX_SMPL_DLY_RSD_SET(value) (((value) << 0) & 0x0000007f)
3183 
3184 #ifndef __ASSEMBLY__
3185 /*
3186  * WARNING: The C register and register group struct declarations are provided for
3187  * convenience and illustrative purposes. They should, however, be used with
3188  * caution as the C language standard provides no guarantees about the alignment or
3189  * atomicity of device memory accesses. The recommended practice for writing
3190  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3191  * alt_write_word() functions.
3192  *
3193  * The struct declaration for register ALT_SPIM_RX_SMPL_DLY.
3194  */
3195 struct ALT_SPIM_RX_SMPL_DLY_s
3196 {
3197  uint32_t rsd : 7; /* Receive Data Sample Delay */
3198  uint32_t : 25; /* *UNDEFINED* */
3199 };
3200 
3201 /* The typedef declaration for register ALT_SPIM_RX_SMPL_DLY. */
3202 typedef volatile struct ALT_SPIM_RX_SMPL_DLY_s ALT_SPIM_RX_SMPL_DLY_t;
3203 #endif /* __ASSEMBLY__ */
3204 
3205 /* The byte offset of the ALT_SPIM_RX_SMPL_DLY register from the beginning of the component. */
3206 #define ALT_SPIM_RX_SMPL_DLY_OFST 0xf0
3207 /* The address of the ALT_SPIM_RX_SMPL_DLY register. */
3208 #define ALT_SPIM_RX_SMPL_DLY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RX_SMPL_DLY_OFST))
3209 
3210 #ifndef __ASSEMBLY__
3211 /*
3212  * WARNING: The C register and register group struct declarations are provided for
3213  * convenience and illustrative purposes. They should, however, be used with
3214  * caution as the C language standard provides no guarantees about the alignment or
3215  * atomicity of device memory accesses. The recommended practice for writing
3216  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3217  * alt_write_word() functions.
3218  *
3219  * The struct declaration for register group ALT_SPIM.
3220  */
3221 struct ALT_SPIM_s
3222 {
3223  ALT_SPIM_CTLR0_t ctrlr0; /* ALT_SPIM_CTLR0 */
3224  ALT_SPIM_CTLR1_t ctrlr1; /* ALT_SPIM_CTLR1 */
3225  ALT_SPIM_SPIENR_t spienr; /* ALT_SPIM_SPIENR */
3226  ALT_SPIM_MWCR_t mwcr; /* ALT_SPIM_MWCR */
3227  ALT_SPIM_SER_t ser; /* ALT_SPIM_SER */
3228  ALT_SPIM_BAUDR_t baudr; /* ALT_SPIM_BAUDR */
3229  ALT_SPIM_TXFTLR_t txftlr; /* ALT_SPIM_TXFTLR */
3230  ALT_SPIM_RXFTLR_t rxftlr; /* ALT_SPIM_RXFTLR */
3231  ALT_SPIM_TXFLR_t txflr; /* ALT_SPIM_TXFLR */
3232  ALT_SPIM_RXFLR_t rxflr; /* ALT_SPIM_RXFLR */
3233  ALT_SPIM_SR_t sr; /* ALT_SPIM_SR */
3234  ALT_SPIM_IMR_t imr; /* ALT_SPIM_IMR */
3235  ALT_SPIM_ISR_t isr; /* ALT_SPIM_ISR */
3236  ALT_SPIM_RISR_t risr; /* ALT_SPIM_RISR */
3237  ALT_SPIM_TXOICR_t txoicr; /* ALT_SPIM_TXOICR */
3238  ALT_SPIM_RXOICR_t rxoicr; /* ALT_SPIM_RXOICR */
3239  ALT_SPIM_RXUICR_t rxuicr; /* ALT_SPIM_RXUICR */
3240  volatile uint32_t _pad_0x44_0x47; /* *UNDEFINED* */
3241  ALT_SPIM_ICR_t icr; /* ALT_SPIM_ICR */
3242  ALT_SPIM_DMACR_t dmacr; /* ALT_SPIM_DMACR */
3243  ALT_SPIM_DMATDLR_t dmatdlr; /* ALT_SPIM_DMATDLR */
3244  ALT_SPIM_DMARDLR_t dmardlr; /* ALT_SPIM_DMARDLR */
3245  ALT_SPIM_IDR_t idr; /* ALT_SPIM_IDR */
3246  ALT_SPIM_SPI_VER_ID_t spi_version_id; /* ALT_SPIM_SPI_VER_ID */
3247  ALT_SPIM_DR_t dr; /* ALT_SPIM_DR */
3248  volatile uint32_t _pad_0x64_0xef[35]; /* *UNDEFINED* */
3249  ALT_SPIM_RX_SMPL_DLY_t rx_sample_dly; /* ALT_SPIM_RX_SMPL_DLY */
3250  volatile uint32_t _pad_0xf4_0x100[3]; /* *UNDEFINED* */
3251 };
3252 
3253 /* The typedef declaration for register group ALT_SPIM. */
3254 typedef volatile struct ALT_SPIM_s ALT_SPIM_t;
3255 /* The struct declaration for the raw register contents of register group ALT_SPIM. */
3256 struct ALT_SPIM_raw_s
3257 {
3258  volatile uint32_t ctrlr0; /* ALT_SPIM_CTLR0 */
3259  volatile uint32_t ctrlr1; /* ALT_SPIM_CTLR1 */
3260  volatile uint32_t spienr; /* ALT_SPIM_SPIENR */
3261  volatile uint32_t mwcr; /* ALT_SPIM_MWCR */
3262  volatile uint32_t ser; /* ALT_SPIM_SER */
3263  volatile uint32_t baudr; /* ALT_SPIM_BAUDR */
3264  volatile uint32_t txftlr; /* ALT_SPIM_TXFTLR */
3265  volatile uint32_t rxftlr; /* ALT_SPIM_RXFTLR */
3266  volatile uint32_t txflr; /* ALT_SPIM_TXFLR */
3267  volatile uint32_t rxflr; /* ALT_SPIM_RXFLR */
3268  volatile uint32_t sr; /* ALT_SPIM_SR */
3269  volatile uint32_t imr; /* ALT_SPIM_IMR */
3270  volatile uint32_t isr; /* ALT_SPIM_ISR */
3271  volatile uint32_t risr; /* ALT_SPIM_RISR */
3272  volatile uint32_t txoicr; /* ALT_SPIM_TXOICR */
3273  volatile uint32_t rxoicr; /* ALT_SPIM_RXOICR */
3274  volatile uint32_t rxuicr; /* ALT_SPIM_RXUICR */
3275  uint32_t _pad_0x44_0x47; /* *UNDEFINED* */
3276  volatile uint32_t icr; /* ALT_SPIM_ICR */
3277  volatile uint32_t dmacr; /* ALT_SPIM_DMACR */
3278  volatile uint32_t dmatdlr; /* ALT_SPIM_DMATDLR */
3279  volatile uint32_t dmardlr; /* ALT_SPIM_DMARDLR */
3280  volatile uint32_t idr; /* ALT_SPIM_IDR */
3281  volatile uint32_t spi_version_id; /* ALT_SPIM_SPI_VER_ID */
3282  volatile uint32_t dr; /* ALT_SPIM_DR */
3283  uint32_t _pad_0x64_0xef[35]; /* *UNDEFINED* */
3284  volatile uint32_t rx_sample_dly; /* ALT_SPIM_RX_SMPL_DLY */
3285  uint32_t _pad_0xf4_0x100[3]; /* *UNDEFINED* */
3286 };
3287 
3288 /* The typedef declaration for the raw register contents of register group ALT_SPIM. */
3289 typedef volatile struct ALT_SPIM_raw_s ALT_SPIM_raw_t;
3290 #endif /* __ASSEMBLY__ */
3291 
3292 
3293 #ifdef __cplusplus
3294 }
3295 #endif /* __cplusplus */
3296 #endif /* __ALTERA_ALT_SPIM_H__ */
3297