35 #ifndef __ALT_SOCAL_NOC_FW_L4_SYS_SCR_H__
36 #define __ALT_SOCAL_NOC_FW_L4_SYS_SCR_H__
71 #define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_LSB 0
73 #define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_MSB 31
75 #define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_WIDTH 32
77 #define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_SET_MSK 0xffffffff
79 #define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_CLR_MSK 0x00000000
81 #define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_RESET 0x0
83 #define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
85 #define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_SET(value) (((value) << 0) & 0xffffffff)
98 struct ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_s
100 uint32_t Reserved : 32;
104 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_s ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_t;
108 #define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RESET 0x00000000
110 #define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_OFST 0x0
131 #define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_LSB 0
133 #define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_MSB 31
135 #define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_WIDTH 32
137 #define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_SET_MSK 0xffffffff
139 #define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_CLR_MSK 0x00000000
141 #define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_RESET 0x0
143 #define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
145 #define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_SET(value) (((value) << 0) & 0xffffffff)
158 struct ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_s
160 uint32_t Reserved : 32;
164 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_s ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_t;
168 #define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RESET 0x00000000
170 #define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_OFST 0x4
200 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_LSB 0
202 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_MSB 0
204 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_WIDTH 1
206 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_SET_MSK 0x00000001
208 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_CLR_MSK 0xfffffffe
210 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_RESET 0x0
212 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
214 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
227 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_LSB 16
229 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_MSB 16
231 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_WIDTH 1
233 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_SET_MSK 0x00010000
235 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_CLR_MSK 0xfffeffff
237 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_RESET 0x0
239 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
241 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
254 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_LSB 24
256 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_MSB 24
258 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_WIDTH 1
260 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_SET_MSK 0x01000000
262 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_CLR_MSK 0xfeffffff
264 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_RESET 0x0
266 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
268 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
281 struct ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_s
285 uint32_t fpga2soc : 1;
292 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_s ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_t;
296 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_RESET 0x00000000
298 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_OFST 0x8
328 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_LSB 0
330 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_MSB 0
332 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_WIDTH 1
334 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_SET_MSK 0x00000001
336 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_CLR_MSK 0xfffffffe
338 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_RESET 0x0
340 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
342 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
355 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_LSB 16
357 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_MSB 16
359 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_WIDTH 1
361 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_SET_MSK 0x00010000
363 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_CLR_MSK 0xfffeffff
365 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_RESET 0x0
367 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
369 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
382 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_LSB 24
384 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_MSB 24
386 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_WIDTH 1
388 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_SET_MSK 0x01000000
390 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_CLR_MSK 0xfeffffff
392 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_RESET 0x0
394 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
396 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
409 struct ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_s
413 uint32_t fpga2soc : 1;
420 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_t;
424 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_RESET 0x00000000
426 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_OFST 0xc
456 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_LSB 0
458 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_MSB 0
460 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_WIDTH 1
462 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_SET_MSK 0x00000001
464 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_CLR_MSK 0xfffffffe
466 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_RESET 0x0
468 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
470 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
483 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_LSB 16
485 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_MSB 16
487 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_WIDTH 1
489 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_SET_MSK 0x00010000
491 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_CLR_MSK 0xfffeffff
493 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_RESET 0x0
495 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
497 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
510 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_LSB 24
512 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_MSB 24
514 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_WIDTH 1
516 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_SET_MSK 0x01000000
518 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_CLR_MSK 0xfeffffff
520 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_RESET 0x0
522 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
524 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
537 struct ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_s
541 uint32_t fpga2soc : 1;
548 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_t;
552 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_RESET 0x00000000
554 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_OFST 0x10
584 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_LSB 0
586 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_MSB 0
588 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_WIDTH 1
590 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_SET_MSK 0x00000001
592 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_CLR_MSK 0xfffffffe
594 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_RESET 0x0
596 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
598 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
611 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_LSB 16
613 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_MSB 16
615 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_WIDTH 1
617 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_SET_MSK 0x00010000
619 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_CLR_MSK 0xfffeffff
621 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_RESET 0x0
623 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
625 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
638 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_LSB 24
640 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_MSB 24
642 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_WIDTH 1
644 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_SET_MSK 0x01000000
646 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_CLR_MSK 0xfeffffff
648 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_RESET 0x0
650 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
652 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
665 struct ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_s
669 uint32_t fpga2soc : 1;
676 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_t;
680 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_RESET 0x00000000
682 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_OFST 0x14
712 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_LSB 0
714 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_MSB 0
716 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_WIDTH 1
718 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_SET_MSK 0x00000001
720 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_CLR_MSK 0xfffffffe
722 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_RESET 0x0
724 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
726 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
739 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_LSB 16
741 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_MSB 16
743 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_WIDTH 1
745 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_SET_MSK 0x00010000
747 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_CLR_MSK 0xfffeffff
749 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_RESET 0x0
751 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
753 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
766 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_LSB 24
768 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_MSB 24
770 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_WIDTH 1
772 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_SET_MSK 0x01000000
774 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_CLR_MSK 0xfeffffff
776 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_RESET 0x0
778 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
780 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
793 struct ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_s
797 uint32_t fpga2soc : 1;
804 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_t;
808 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_RESET 0x00000000
810 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_OFST 0x18
840 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_LSB 0
842 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_MSB 0
844 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_WIDTH 1
846 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_SET_MSK 0x00000001
848 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_CLR_MSK 0xfffffffe
850 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_RESET 0x0
852 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
854 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
867 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_LSB 16
869 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_MSB 16
871 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_WIDTH 1
873 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_SET_MSK 0x00010000
875 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_CLR_MSK 0xfffeffff
877 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_RESET 0x0
879 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
881 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
894 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_LSB 24
896 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_MSB 24
898 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_WIDTH 1
900 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_SET_MSK 0x01000000
902 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_CLR_MSK 0xfeffffff
904 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_RESET 0x0
906 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
908 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
921 struct ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_s
925 uint32_t fpga2soc : 1;
932 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_t;
936 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_RESET 0x00000000
938 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_OFST 0x1c
968 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_LSB 0
970 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_MSB 0
972 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_WIDTH 1
974 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_SET_MSK 0x00000001
976 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_CLR_MSK 0xfffffffe
978 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_RESET 0x0
980 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
982 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
995 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_LSB 16
997 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_MSB 16
999 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_WIDTH 1
1001 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_SET_MSK 0x00010000
1003 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_CLR_MSK 0xfffeffff
1005 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_RESET 0x0
1007 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
1009 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
1022 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_LSB 24
1024 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_MSB 24
1026 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_WIDTH 1
1028 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_SET_MSK 0x01000000
1030 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_CLR_MSK 0xfeffffff
1032 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_RESET 0x0
1034 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1036 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1038 #ifndef __ASSEMBLY__
1049 struct ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_s
1051 uint32_t mpu_m0 : 1;
1053 uint32_t fpga2soc : 1;
1055 uint32_t ahb_ap : 1;
1060 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_t;
1064 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_RESET 0x00000000
1066 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_OFST 0x20
1087 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_LSB 0
1089 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_MSB 31
1091 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_WIDTH 32
1093 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_SET_MSK 0xffffffff
1095 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_CLR_MSK 0x00000000
1097 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_RESET 0x0
1099 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
1101 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_SET(value) (((value) << 0) & 0xffffffff)
1103 #ifndef __ASSEMBLY__
1114 struct ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_s
1116 uint32_t Reserved : 32;
1120 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_t;
1124 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RESET 0x00000000
1126 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_OFST 0x24
1147 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_LSB 0
1149 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_MSB 31
1151 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_WIDTH 32
1153 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_SET_MSK 0xffffffff
1155 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_CLR_MSK 0x00000000
1157 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_RESET 0x0
1159 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
1161 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_SET(value) (((value) << 0) & 0xffffffff)
1163 #ifndef __ASSEMBLY__
1174 struct ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_s
1176 uint32_t Reserved : 32;
1180 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_t;
1184 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RESET 0x00000000
1186 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_OFST 0x28
1216 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_LSB 0
1218 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_MSB 0
1220 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_WIDTH 1
1222 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_SET_MSK 0x00000001
1224 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_CLR_MSK 0xfffffffe
1226 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_RESET 0x0
1228 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1230 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1243 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_LSB 16
1245 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_MSB 16
1247 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_WIDTH 1
1249 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_SET_MSK 0x00010000
1251 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_CLR_MSK 0xfffeffff
1253 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_RESET 0x0
1255 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
1257 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
1270 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_LSB 24
1272 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_MSB 24
1274 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_WIDTH 1
1276 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_SET_MSK 0x01000000
1278 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_CLR_MSK 0xfeffffff
1280 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_RESET 0x0
1282 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1284 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1286 #ifndef __ASSEMBLY__
1297 struct ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_s
1299 uint32_t mpu_m0 : 1;
1301 uint32_t fpga2soc : 1;
1303 uint32_t ahb_ap : 1;
1308 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_s ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_t;
1312 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_RESET 0x00000000
1314 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_OFST 0x2c
1344 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_LSB 0
1346 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_MSB 0
1348 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_WIDTH 1
1350 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_SET_MSK 0x00000001
1352 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_CLR_MSK 0xfffffffe
1354 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_RESET 0x0
1356 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1358 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1371 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_LSB 16
1373 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_MSB 16
1375 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_WIDTH 1
1377 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_SET_MSK 0x00010000
1379 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_CLR_MSK 0xfffeffff
1381 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_RESET 0x0
1383 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
1385 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
1398 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_LSB 24
1400 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_MSB 24
1402 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_WIDTH 1
1404 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_SET_MSK 0x01000000
1406 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_CLR_MSK 0xfeffffff
1408 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_RESET 0x0
1410 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1412 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1414 #ifndef __ASSEMBLY__
1425 struct ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_s
1427 uint32_t mpu_m0 : 1;
1429 uint32_t fpga2soc : 1;
1431 uint32_t ahb_ap : 1;
1436 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_s ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_t;
1440 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_RESET 0x00000000
1442 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_OFST 0x30
1472 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_LSB 0
1474 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_MSB 0
1476 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_WIDTH 1
1478 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_SET_MSK 0x00000001
1480 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_CLR_MSK 0xfffffffe
1482 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_RESET 0x0
1484 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1486 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1499 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_LSB 16
1501 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_MSB 16
1503 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_WIDTH 1
1505 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_SET_MSK 0x00010000
1507 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_CLR_MSK 0xfffeffff
1509 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_RESET 0x0
1511 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
1513 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
1526 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_LSB 24
1528 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_MSB 24
1530 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_WIDTH 1
1532 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_SET_MSK 0x01000000
1534 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_CLR_MSK 0xfeffffff
1536 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_RESET 0x0
1538 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1540 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1542 #ifndef __ASSEMBLY__
1553 struct ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_s
1555 uint32_t mpu_m0 : 1;
1557 uint32_t fpga2soc : 1;
1559 uint32_t ahb_ap : 1;
1564 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_s ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_t;
1568 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_RESET 0x00000000
1570 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_OFST 0x34
1600 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_LSB 0
1602 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_MSB 0
1604 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_WIDTH 1
1606 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_SET_MSK 0x00000001
1608 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_CLR_MSK 0xfffffffe
1610 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_RESET 0x0
1612 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1614 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1627 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_LSB 16
1629 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_MSB 16
1631 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_WIDTH 1
1633 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_SET_MSK 0x00010000
1635 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_CLR_MSK 0xfffeffff
1637 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_RESET 0x0
1639 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
1641 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
1654 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_LSB 24
1656 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_MSB 24
1658 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_WIDTH 1
1660 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_SET_MSK 0x01000000
1662 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_CLR_MSK 0xfeffffff
1664 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_RESET 0x0
1666 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1668 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1670 #ifndef __ASSEMBLY__
1681 struct ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_s
1683 uint32_t mpu_m0 : 1;
1685 uint32_t fpga2soc : 1;
1687 uint32_t ahb_ap : 1;
1692 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_s ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_t;
1696 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_RESET 0x00000000
1698 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_OFST 0x38
1728 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_LSB 0
1730 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_MSB 0
1732 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_WIDTH 1
1734 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_SET_MSK 0x00000001
1736 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_CLR_MSK 0xfffffffe
1738 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_RESET 0x0
1740 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1742 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1755 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_LSB 16
1757 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_MSB 16
1759 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_WIDTH 1
1761 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_SET_MSK 0x00010000
1763 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_CLR_MSK 0xfffeffff
1765 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_RESET 0x0
1767 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
1769 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
1782 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_LSB 24
1784 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_MSB 24
1786 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_WIDTH 1
1788 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_SET_MSK 0x01000000
1790 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_CLR_MSK 0xfeffffff
1792 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_RESET 0x0
1794 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1796 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1798 #ifndef __ASSEMBLY__
1809 struct ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_s
1811 uint32_t mpu_m0 : 1;
1813 uint32_t fpga2soc : 1;
1815 uint32_t ahb_ap : 1;
1820 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_s ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_t;
1824 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_RESET 0x00000000
1826 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_OFST 0x3c
1856 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_LSB 0
1858 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_MSB 0
1860 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_WIDTH 1
1862 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_SET_MSK 0x00000001
1864 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_CLR_MSK 0xfffffffe
1866 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_RESET 0x0
1868 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1870 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1883 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_LSB 16
1885 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_MSB 16
1887 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_WIDTH 1
1889 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_SET_MSK 0x00010000
1891 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_CLR_MSK 0xfffeffff
1893 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_RESET 0x0
1895 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
1897 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
1910 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_LSB 24
1912 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_MSB 24
1914 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_WIDTH 1
1916 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_SET_MSK 0x01000000
1918 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_CLR_MSK 0xfeffffff
1920 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_RESET 0x0
1922 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1924 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1926 #ifndef __ASSEMBLY__
1937 struct ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_s
1939 uint32_t mpu_m0 : 1;
1941 uint32_t fpga2soc : 1;
1943 uint32_t ahb_ap : 1;
1948 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_s ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_t;
1952 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_RESET 0x00000000
1954 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_OFST 0x40
1984 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_LSB 0
1986 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_MSB 0
1988 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_WIDTH 1
1990 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_SET_MSK 0x00000001
1992 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_CLR_MSK 0xfffffffe
1994 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_RESET 0x0
1996 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1998 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2011 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_LSB 16
2013 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_MSB 16
2015 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_WIDTH 1
2017 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_SET_MSK 0x00010000
2019 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_CLR_MSK 0xfffeffff
2021 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_RESET 0x0
2023 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
2025 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
2038 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_LSB 24
2040 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_MSB 24
2042 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_WIDTH 1
2044 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_SET_MSK 0x01000000
2046 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_CLR_MSK 0xfeffffff
2048 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_RESET 0x0
2050 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2052 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2054 #ifndef __ASSEMBLY__
2065 struct ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_s
2067 uint32_t mpu_m0 : 1;
2069 uint32_t fpga2soc : 1;
2071 uint32_t ahb_ap : 1;
2076 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_s ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_t;
2080 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_RESET 0x00000000
2082 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_OFST 0x44
2112 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_LSB 0
2114 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_MSB 0
2116 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_WIDTH 1
2118 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_SET_MSK 0x00000001
2120 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_CLR_MSK 0xfffffffe
2122 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_RESET 0x0
2124 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2126 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2139 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_LSB 16
2141 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_MSB 16
2143 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_WIDTH 1
2145 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_SET_MSK 0x00010000
2147 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_CLR_MSK 0xfffeffff
2149 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_RESET 0x0
2151 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
2153 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
2166 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_LSB 24
2168 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_MSB 24
2170 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_WIDTH 1
2172 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_SET_MSK 0x01000000
2174 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_CLR_MSK 0xfeffffff
2176 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_RESET 0x0
2178 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2180 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2182 #ifndef __ASSEMBLY__
2193 struct ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_s
2195 uint32_t mpu_m0 : 1;
2197 uint32_t fpga2soc : 1;
2199 uint32_t ahb_ap : 1;
2204 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_s ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_t;
2208 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_RESET 0x00000000
2210 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_OFST 0x48
2242 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_LSB 0
2244 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_MSB 0
2246 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_WIDTH 1
2248 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_SET_MSK 0x00000001
2250 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_CLR_MSK 0xfffffffe
2252 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_RESET 0x0
2254 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2256 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2269 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_LSB 8
2271 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_MSB 8
2273 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_WIDTH 1
2275 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_SET_MSK 0x00000100
2277 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_CLR_MSK 0xfffffeff
2279 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_RESET 0x0
2281 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_GET(value) (((value) & 0x00000100) >> 8)
2283 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_SET(value) (((value) << 8) & 0x00000100)
2296 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_LSB 16
2298 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_MSB 16
2300 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_WIDTH 1
2302 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_SET_MSK 0x00010000
2304 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_CLR_MSK 0xfffeffff
2306 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_RESET 0x0
2308 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_GET(value) (((value) & 0x00010000) >> 16)
2310 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_SET(value) (((value) << 16) & 0x00010000)
2323 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_LSB 24
2325 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_MSB 24
2327 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_WIDTH 1
2329 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_SET_MSK 0x01000000
2331 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_CLR_MSK 0xfeffffff
2333 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_RESET 0x0
2335 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2337 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2339 #ifndef __ASSEMBLY__
2350 struct ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_s
2352 uint32_t mpu_m0 : 1;
2356 uint32_t fpga2soc : 1;
2358 uint32_t ahb_ap : 1;
2363 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_s ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_t;
2367 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_RESET 0x00000000
2369 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_OFST 0x4c
2399 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_LSB 0
2401 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_MSB 0
2403 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_WIDTH 1
2405 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_SET_MSK 0x00000001
2407 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_CLR_MSK 0xfffffffe
2409 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_RESET 0x0
2411 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2413 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2426 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_LSB 8
2428 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_MSB 8
2430 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_WIDTH 1
2432 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_SET_MSK 0x00000100
2434 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_CLR_MSK 0xfffffeff
2436 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_RESET 0x0
2438 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_GET(value) (((value) & 0x00000100) >> 8)
2440 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_SET(value) (((value) << 8) & 0x00000100)
2453 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_LSB 24
2455 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_MSB 24
2457 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_WIDTH 1
2459 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_SET_MSK 0x01000000
2461 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_CLR_MSK 0xfeffffff
2463 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_RESET 0x0
2465 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2467 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2469 #ifndef __ASSEMBLY__
2480 struct ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_s
2482 uint32_t mpu_m0 : 1;
2486 uint32_t ahb_ap : 1;
2491 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_s ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_t;
2495 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_RESET 0x00000000
2497 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_OFST 0x50
2529 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_LSB 0
2531 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_MSB 0
2533 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_WIDTH 1
2535 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_SET_MSK 0x00000001
2537 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_CLR_MSK 0xfffffffe
2539 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_RESET 0x0
2541 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2543 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2556 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_LSB 8
2558 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_MSB 8
2560 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_WIDTH 1
2562 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_SET_MSK 0x00000100
2564 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_CLR_MSK 0xfffffeff
2566 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_RESET 0x0
2568 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_GET(value) (((value) & 0x00000100) >> 8)
2570 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_SET(value) (((value) << 8) & 0x00000100)
2583 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_LSB 16
2585 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_MSB 16
2587 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_WIDTH 1
2589 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_SET_MSK 0x00010000
2591 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_CLR_MSK 0xfffeffff
2593 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_RESET 0x0
2595 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
2597 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
2610 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_LSB 24
2612 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_MSB 24
2614 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_WIDTH 1
2616 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_SET_MSK 0x01000000
2618 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_CLR_MSK 0xfeffffff
2620 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_RESET 0x0
2622 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2624 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2626 #ifndef __ASSEMBLY__
2637 struct ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_s
2639 uint32_t mpu_m0 : 1;
2643 uint32_t fpga2soc : 1;
2645 uint32_t ahb_ap : 1;
2650 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_s ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_t;
2654 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_RESET 0x00000000
2656 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_OFST 0x54
2688 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_LSB 0
2690 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_MSB 0
2692 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_WIDTH 1
2694 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_SET_MSK 0x00000001
2696 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_CLR_MSK 0xfffffffe
2698 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_RESET 0x0
2700 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2702 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2715 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_LSB 8
2717 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_MSB 8
2719 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_WIDTH 1
2721 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_SET_MSK 0x00000100
2723 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_CLR_MSK 0xfffffeff
2725 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_RESET 0x0
2727 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_GET(value) (((value) & 0x00000100) >> 8)
2729 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_SET(value) (((value) << 8) & 0x00000100)
2742 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_LSB 16
2744 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_MSB 16
2746 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_WIDTH 1
2748 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_SET_MSK 0x00010000
2750 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_CLR_MSK 0xfffeffff
2752 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_RESET 0x0
2754 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_GET(value) (((value) & 0x00010000) >> 16)
2756 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_SET(value) (((value) << 16) & 0x00010000)
2769 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_LSB 24
2771 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_MSB 24
2773 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_WIDTH 1
2775 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_SET_MSK 0x01000000
2777 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_CLR_MSK 0xfeffffff
2779 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_RESET 0x0
2781 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2783 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2785 #ifndef __ASSEMBLY__
2796 struct ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_s
2798 uint32_t mpu_m0 : 1;
2802 uint32_t fpga2soc : 1;
2804 uint32_t ahb_ap : 1;
2809 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_s ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_t;
2813 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_RESET 0x00000000
2815 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_OFST 0x58
2847 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_LSB 0
2849 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_MSB 0
2851 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_WIDTH 1
2853 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_SET_MSK 0x00000001
2855 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_CLR_MSK 0xfffffffe
2857 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_RESET 0x0
2859 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2861 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2874 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_LSB 8
2876 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_MSB 8
2878 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_WIDTH 1
2880 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_SET_MSK 0x00000100
2882 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_CLR_MSK 0xfffffeff
2884 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_RESET 0x0
2886 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_GET(value) (((value) & 0x00000100) >> 8)
2888 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_SET(value) (((value) << 8) & 0x00000100)
2901 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_LSB 16
2903 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_MSB 16
2905 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_WIDTH 1
2907 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_SET_MSK 0x00010000
2909 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_CLR_MSK 0xfffeffff
2911 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_RESET 0x0
2913 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_GET(value) (((value) & 0x00010000) >> 16)
2915 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_SET(value) (((value) << 16) & 0x00010000)
2928 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_LSB 24
2930 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_MSB 24
2932 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_WIDTH 1
2934 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_SET_MSK 0x01000000
2936 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_CLR_MSK 0xfeffffff
2938 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_RESET 0x0
2940 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2942 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2944 #ifndef __ASSEMBLY__
2955 struct ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_s
2957 uint32_t mpu_m0 : 1;
2961 uint32_t fpga2soc : 1;
2963 uint32_t ahb_ap : 1;
2968 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_s ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_t;
2972 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_RESET 0x00000000
2974 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_OFST 0x5c
3006 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_LSB 0
3008 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_MSB 0
3010 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_WIDTH 1
3012 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_SET_MSK 0x00000001
3014 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_CLR_MSK 0xfffffffe
3016 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_RESET 0x0
3018 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3020 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3033 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_LSB 8
3035 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_MSB 8
3037 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_WIDTH 1
3039 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_SET_MSK 0x00000100
3041 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_CLR_MSK 0xfffffeff
3043 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_RESET 0x0
3045 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_GET(value) (((value) & 0x00000100) >> 8)
3047 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_SET(value) (((value) << 8) & 0x00000100)
3060 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_LSB 16
3062 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_MSB 16
3064 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_WIDTH 1
3066 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_SET_MSK 0x00010000
3068 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_CLR_MSK 0xfffeffff
3070 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_RESET 0x0
3072 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_GET(value) (((value) & 0x00010000) >> 16)
3074 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_SET(value) (((value) << 16) & 0x00010000)
3087 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_LSB 24
3089 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_MSB 24
3091 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_WIDTH 1
3093 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_SET_MSK 0x01000000
3095 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_CLR_MSK 0xfeffffff
3097 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_RESET 0x0
3099 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3101 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3103 #ifndef __ASSEMBLY__
3114 struct ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_s
3116 uint32_t mpu_m0 : 1;
3120 uint32_t fpga2soc : 1;
3122 uint32_t ahb_ap : 1;
3127 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_s ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_t;
3131 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_RESET 0x00000000
3133 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_OFST 0x60
3165 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_LSB 0
3167 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_MSB 0
3169 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_WIDTH 1
3171 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_SET_MSK 0x00000001
3173 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_CLR_MSK 0xfffffffe
3175 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_RESET 0x0
3177 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3179 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3192 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_LSB 8
3194 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_MSB 8
3196 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_WIDTH 1
3198 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_SET_MSK 0x00000100
3200 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_CLR_MSK 0xfffffeff
3202 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_RESET 0x0
3204 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_GET(value) (((value) & 0x00000100) >> 8)
3206 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_SET(value) (((value) << 8) & 0x00000100)
3219 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_LSB 16
3221 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_MSB 16
3223 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_WIDTH 1
3225 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_SET_MSK 0x00010000
3227 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_CLR_MSK 0xfffeffff
3229 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_RESET 0x0
3231 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_GET(value) (((value) & 0x00010000) >> 16)
3233 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_SET(value) (((value) << 16) & 0x00010000)
3246 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_LSB 24
3248 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_MSB 24
3250 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_WIDTH 1
3252 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_SET_MSK 0x01000000
3254 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_CLR_MSK 0xfeffffff
3256 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_RESET 0x0
3258 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3260 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3262 #ifndef __ASSEMBLY__
3273 struct ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_s
3275 uint32_t mpu_m0 : 1;
3279 uint32_t fpga2soc : 1;
3281 uint32_t ahb_ap : 1;
3286 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_s ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_t;
3290 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_RESET 0x00000000
3292 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_OFST 0x64
3324 #define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_LSB 0
3326 #define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_MSB 0
3328 #define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_WIDTH 1
3330 #define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_SET_MSK 0x00000001
3332 #define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_CLR_MSK 0xfffffffe
3334 #define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_RESET 0x0
3336 #define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3338 #define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3351 #define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_LSB 8
3353 #define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_MSB 8
3355 #define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_WIDTH 1
3357 #define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_SET_MSK 0x00000100
3359 #define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_CLR_MSK 0xfffffeff
3361 #define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_RESET 0x0
3363 #define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_GET(value) (((value) & 0x00000100) >> 8)
3365 #define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_SET(value) (((value) << 8) & 0x00000100)
3378 #define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_LSB 16
3380 #define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_MSB 16
3382 #define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_WIDTH 1
3384 #define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_SET_MSK 0x00010000
3386 #define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_CLR_MSK 0xfffeffff
3388 #define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_RESET 0x0
3390 #define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_GET(value) (((value) & 0x00010000) >> 16)
3392 #define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_SET(value) (((value) << 16) & 0x00010000)
3405 #define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_LSB 24
3407 #define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_MSB 24
3409 #define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_WIDTH 1
3411 #define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_SET_MSK 0x01000000
3413 #define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_CLR_MSK 0xfeffffff
3415 #define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_RESET 0x0
3417 #define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3419 #define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3421 #ifndef __ASSEMBLY__
3432 struct ALT_NOC_FW_L4_SYS_SCR_WD0_s
3434 uint32_t mpu_m0 : 1;
3438 uint32_t fpga2soc : 1;
3440 uint32_t ahb_ap : 1;
3445 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_WD0_s ALT_NOC_FW_L4_SYS_SCR_WD0_t;
3449 #define ALT_NOC_FW_L4_SYS_SCR_WD0_RESET 0x00000000
3451 #define ALT_NOC_FW_L4_SYS_SCR_WD0_OFST 0x68
3483 #define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_LSB 0
3485 #define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_MSB 0
3487 #define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_WIDTH 1
3489 #define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_SET_MSK 0x00000001
3491 #define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_CLR_MSK 0xfffffffe
3493 #define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_RESET 0x0
3495 #define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3497 #define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3510 #define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_LSB 8
3512 #define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_MSB 8
3514 #define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_WIDTH 1
3516 #define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_SET_MSK 0x00000100
3518 #define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_CLR_MSK 0xfffffeff
3520 #define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_RESET 0x0
3522 #define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_GET(value) (((value) & 0x00000100) >> 8)
3524 #define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_SET(value) (((value) << 8) & 0x00000100)
3537 #define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_LSB 16
3539 #define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_MSB 16
3541 #define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_WIDTH 1
3543 #define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_SET_MSK 0x00010000
3545 #define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_CLR_MSK 0xfffeffff
3547 #define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_RESET 0x0
3549 #define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_GET(value) (((value) & 0x00010000) >> 16)
3551 #define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_SET(value) (((value) << 16) & 0x00010000)
3564 #define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_LSB 24
3566 #define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_MSB 24
3568 #define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_WIDTH 1
3570 #define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_SET_MSK 0x01000000
3572 #define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_CLR_MSK 0xfeffffff
3574 #define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_RESET 0x0
3576 #define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3578 #define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3580 #ifndef __ASSEMBLY__
3591 struct ALT_NOC_FW_L4_SYS_SCR_WD1_s
3593 uint32_t mpu_m0 : 1;
3597 uint32_t fpga2soc : 1;
3599 uint32_t ahb_ap : 1;
3604 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_WD1_s ALT_NOC_FW_L4_SYS_SCR_WD1_t;
3608 #define ALT_NOC_FW_L4_SYS_SCR_WD1_RESET 0x00000000
3610 #define ALT_NOC_FW_L4_SYS_SCR_WD1_OFST 0x6c
3643 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_LSB 0
3645 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_MSB 0
3647 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_WIDTH 1
3649 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_SET_MSK 0x00000001
3651 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_CLR_MSK 0xfffffffe
3653 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_RESET 0x0
3655 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3657 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3670 #define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_LSB 8
3672 #define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_MSB 8
3674 #define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_WIDTH 1
3676 #define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_SET_MSK 0x00000100
3678 #define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_CLR_MSK 0xfffffeff
3680 #define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_RESET 0x0
3682 #define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_GET(value) (((value) & 0x00000100) >> 8)
3684 #define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_SET(value) (((value) << 8) & 0x00000100)
3697 #define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_LSB 16
3699 #define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_MSB 16
3701 #define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_WIDTH 1
3703 #define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_SET_MSK 0x00010000
3705 #define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_CLR_MSK 0xfffeffff
3707 #define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_RESET 0x0
3709 #define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_GET(value) (((value) & 0x00010000) >> 16)
3711 #define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_SET(value) (((value) << 16) & 0x00010000)
3724 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_LSB 24
3726 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_MSB 24
3728 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_WIDTH 1
3730 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_SET_MSK 0x01000000
3732 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_CLR_MSK 0xfeffffff
3734 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_RESET 0x0
3736 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3738 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3751 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_LSB 25
3753 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_MSB 25
3755 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_WIDTH 1
3757 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_SET_MSK 0x02000000
3759 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_CLR_MSK 0xfdffffff
3761 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_RESET 0x0
3763 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_GET(value) (((value) & 0x02000000) >> 25)
3765 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_SET(value) (((value) << 25) & 0x02000000)
3767 #ifndef __ASSEMBLY__
3778 struct ALT_NOC_FW_L4_SYS_SCR_DAP_s
3780 uint32_t mpu_m0 : 1;
3784 uint32_t fpga2soc : 1;
3786 uint32_t ahb_ap : 1;
3792 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_DAP_s ALT_NOC_FW_L4_SYS_SCR_DAP_t;
3796 #define ALT_NOC_FW_L4_SYS_SCR_DAP_RESET 0x00000000
3798 #define ALT_NOC_FW_L4_SYS_SCR_DAP_OFST 0x70
3828 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_LSB 0
3830 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_MSB 0
3832 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_WIDTH 1
3834 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_SET_MSK 0x00000001
3836 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_CLR_MSK 0xfffffffe
3838 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_RESET 0x0
3840 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3842 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3855 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_LSB 8
3857 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_MSB 8
3859 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_WIDTH 1
3861 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_SET_MSK 0x00000100
3863 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_CLR_MSK 0xfffffeff
3865 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_RESET 0x0
3867 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_GET(value) (((value) & 0x00000100) >> 8)
3869 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_SET(value) (((value) << 8) & 0x00000100)
3882 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_LSB 24
3884 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_MSB 24
3886 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_WIDTH 1
3888 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_SET_MSK 0x01000000
3890 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_CLR_MSK 0xfeffffff
3892 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_RESET 0x0
3894 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3896 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3898 #ifndef __ASSEMBLY__
3909 struct ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_s
3911 uint32_t mpu_m0 : 1;
3915 uint32_t ahb_ap : 1;
3920 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_s ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_t;
3924 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_RESET 0x00000000
3926 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_OFST 0x74
3956 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_LSB 0
3958 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_MSB 0
3960 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_WIDTH 1
3962 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_SET_MSK 0x00000001
3964 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_CLR_MSK 0xfffffffe
3966 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_RESET 0x0
3968 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3970 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3983 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_LSB 8
3985 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_MSB 8
3987 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_WIDTH 1
3989 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_SET_MSK 0x00000100
3991 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_CLR_MSK 0xfffffeff
3993 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_RESET 0x0
3995 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_GET(value) (((value) & 0x00000100) >> 8)
3997 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_SET(value) (((value) << 8) & 0x00000100)
4010 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_LSB 24
4012 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_MSB 24
4014 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_WIDTH 1
4016 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_SET_MSK 0x01000000
4018 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_CLR_MSK 0xfeffffff
4020 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_RESET 0x0
4022 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4024 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4026 #ifndef __ASSEMBLY__
4037 struct ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_s
4039 uint32_t mpu_m0 : 1;
4043 uint32_t ahb_ap : 1;
4048 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_s ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_t;
4052 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_RESET 0x00000000
4054 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_OFST 0x78
4056 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_OFST))
4088 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_LSB 0
4090 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_MSB 0
4092 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_WIDTH 1
4094 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_SET_MSK 0x00000001
4096 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_CLR_MSK 0xfffffffe
4098 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_RESET 0x0
4100 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4102 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4115 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_LSB 8
4117 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_MSB 8
4119 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_WIDTH 1
4121 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_SET_MSK 0x00000100
4123 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_CLR_MSK 0xfffffeff
4125 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_RESET 0x0
4127 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_GET(value) (((value) & 0x00000100) >> 8)
4129 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_SET(value) (((value) << 8) & 0x00000100)
4142 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_LSB 16
4144 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_MSB 16
4146 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_WIDTH 1
4148 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_SET_MSK 0x00010000
4150 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_CLR_MSK 0xfffeffff
4152 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_RESET 0x0
4154 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
4156 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
4169 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_LSB 24
4171 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_MSB 24
4173 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_WIDTH 1
4175 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_SET_MSK 0x01000000
4177 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_CLR_MSK 0xfeffffff
4179 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_RESET 0x0
4181 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4183 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4185 #ifndef __ASSEMBLY__
4196 struct ALT_NOC_FW_L4_SYS_SCR_HMC_REG_s
4198 uint32_t mpu_m0 : 1;
4202 uint32_t fpga2soc : 1;
4204 uint32_t ahb_ap : 1;
4209 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_HMC_REG_s ALT_NOC_FW_L4_SYS_SCR_HMC_REG_t;
4213 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_RESET 0x00000000
4215 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_OFST 0x7c
4247 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_LSB 0
4249 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_MSB 0
4251 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_WIDTH 1
4253 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_SET_MSK 0x00000001
4255 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_CLR_MSK 0xfffffffe
4257 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_RESET 0x0
4259 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4261 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4274 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_LSB 8
4276 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_MSB 8
4278 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_WIDTH 1
4280 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_SET_MSK 0x00000100
4282 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_CLR_MSK 0xfffffeff
4284 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_RESET 0x0
4286 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_GET(value) (((value) & 0x00000100) >> 8)
4288 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_SET(value) (((value) << 8) & 0x00000100)
4301 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_LSB 16
4303 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_MSB 16
4305 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_WIDTH 1
4307 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_SET_MSK 0x00010000
4309 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_CLR_MSK 0xfffeffff
4311 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_RESET 0x0
4313 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
4315 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
4328 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_LSB 24
4330 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_MSB 24
4332 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_WIDTH 1
4334 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_SET_MSK 0x01000000
4336 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_CLR_MSK 0xfeffffff
4338 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_RESET 0x0
4340 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4342 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4344 #ifndef __ASSEMBLY__
4355 struct ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_s
4357 uint32_t mpu_m0 : 1;
4361 uint32_t fpga2soc : 1;
4363 uint32_t ahb_ap : 1;
4368 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_s ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_t;
4372 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_RESET 0x00000000
4374 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_OFST 0x80
4404 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_LSB 0
4406 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_MSB 0
4408 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_WIDTH 1
4410 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_SET_MSK 0x00000001
4412 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_CLR_MSK 0xfffffffe
4414 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_RESET 0x0
4416 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4418 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4431 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_LSB 16
4433 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_MSB 16
4435 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_WIDTH 1
4437 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_SET_MSK 0x00010000
4439 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_CLR_MSK 0xfffeffff
4441 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_RESET 0x0
4443 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
4445 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
4458 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_LSB 24
4460 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_MSB 24
4462 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_WIDTH 1
4464 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_SET_MSK 0x01000000
4466 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_CLR_MSK 0xfeffffff
4468 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_RESET 0x0
4470 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4472 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4474 #ifndef __ASSEMBLY__
4485 struct ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_s
4487 uint32_t mpu_m0 : 1;
4489 uint32_t fpga2soc : 1;
4491 uint32_t ahb_ap : 1;
4496 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_s ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_t;
4500 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_RESET 0x00000000
4502 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_OFST 0x84
4532 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_LSB 0
4534 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_MSB 0
4536 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_WIDTH 1
4538 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_SET_MSK 0x00000001
4540 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_CLR_MSK 0xfffffffe
4542 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_RESET 0x0
4544 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4546 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4559 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_LSB 16
4561 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_MSB 16
4563 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_WIDTH 1
4565 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_SET_MSK 0x00010000
4567 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_CLR_MSK 0xfffeffff
4569 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_RESET 0x0
4571 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
4573 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
4586 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_LSB 24
4588 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_MSB 24
4590 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_WIDTH 1
4592 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_SET_MSK 0x01000000
4594 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_CLR_MSK 0xfeffffff
4596 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_RESET 0x0
4598 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4600 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4602 #ifndef __ASSEMBLY__
4613 struct ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_s
4615 uint32_t mpu_m0 : 1;
4617 uint32_t fpga2soc : 1;
4619 uint32_t ahb_ap : 1;
4624 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_s ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_t;
4628 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_RESET 0x00000000
4630 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_OFST 0x88
4660 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_LSB 0
4662 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_MSB 0
4664 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_WIDTH 1
4666 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_SET_MSK 0x00000001
4668 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_CLR_MSK 0xfffffffe
4670 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_RESET 0x0
4672 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4674 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4687 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_LSB 16
4689 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_MSB 16
4691 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_WIDTH 1
4693 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_SET_MSK 0x00010000
4695 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_CLR_MSK 0xfffeffff
4697 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_RESET 0x0
4699 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_GET(value) (((value) & 0x00010000) >> 16)
4701 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_SET(value) (((value) << 16) & 0x00010000)
4714 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_LSB 24
4716 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_MSB 24
4718 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_WIDTH 1
4720 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_SET_MSK 0x01000000
4722 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_CLR_MSK 0xfeffffff
4724 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_RESET 0x0
4726 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4728 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4730 #ifndef __ASSEMBLY__
4741 struct ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_s
4743 uint32_t mpu_m0 : 1;
4745 uint32_t fpga2soc : 1;
4747 uint32_t ahb_ap : 1;
4752 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_s ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_t;
4756 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_RESET 0x00000000
4758 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_OFST 0x8c
4788 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_LSB 0
4790 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_MSB 0
4792 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_WIDTH 1
4794 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_SET_MSK 0x00000001
4796 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_CLR_MSK 0xfffffffe
4798 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_RESET 0x0
4800 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4802 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4815 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_LSB 16
4817 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_MSB 16
4819 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_WIDTH 1
4821 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_SET_MSK 0x00010000
4823 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_CLR_MSK 0xfffeffff
4825 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_RESET 0x0
4827 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_GET(value) (((value) & 0x00010000) >> 16)
4829 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_SET(value) (((value) << 16) & 0x00010000)
4842 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_LSB 24
4844 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_MSB 24
4846 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_WIDTH 1
4848 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_SET_MSK 0x01000000
4850 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_CLR_MSK 0xfeffffff
4852 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_RESET 0x0
4854 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4856 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4858 #ifndef __ASSEMBLY__
4869 struct ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_s
4871 uint32_t mpu_m0 : 1;
4873 uint32_t fpga2soc : 1;
4875 uint32_t ahb_ap : 1;
4880 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_s ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_t;
4884 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_RESET 0x00000000
4886 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_OFST 0x90
4916 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_LSB 0
4918 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_MSB 0
4920 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_WIDTH 1
4922 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_SET_MSK 0x00000001
4924 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_CLR_MSK 0xfffffffe
4926 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_RESET 0x0
4928 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4930 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4943 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_LSB 16
4945 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_MSB 16
4947 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_WIDTH 1
4949 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_SET_MSK 0x00010000
4951 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_CLR_MSK 0xfffeffff
4953 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_RESET 0x0
4955 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_GET(value) (((value) & 0x00010000) >> 16)
4957 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_SET(value) (((value) << 16) & 0x00010000)
4970 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_LSB 24
4972 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_MSB 24
4974 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_WIDTH 1
4976 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_SET_MSK 0x01000000
4978 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_CLR_MSK 0xfeffffff
4980 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_RESET 0x0
4982 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4984 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4986 #ifndef __ASSEMBLY__
4997 struct ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_s
4999 uint32_t mpu_m0 : 1;
5001 uint32_t fpga2soc : 1;
5003 uint32_t ahb_ap : 1;
5008 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_s ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_t;
5012 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_RESET 0x00000000
5014 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_OFST 0x94
5016 #ifndef __ASSEMBLY__
5027 struct ALT_NOC_FW_L4_SYS_SCR_s
5029 ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_t can0_ecc;
5030 ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_t can1_ecc;
5031 ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_t dma_ecc;
5032 ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_t emac0rx_ecc;
5033 ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_t emac0tx_ecc;
5034 ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_t emac1rx_ecc;
5035 ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_t emac1tx_ecc;
5036 ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_t emac2rx_ecc;
5037 ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_t emac2tx_ecc;
5038 ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_t emac3rx_ecc;
5039 ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_t emac3tx_ecc;
5040 ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_t nand_ecc;
5041 ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_t nand_read_ecc;
5042 ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_t nand_write_ecc;
5043 ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_t onchipram_ecc;
5044 ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_t qspi_ecc;
5045 ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_t sdmmc_ecc;
5046 ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_t usb0_ecc;
5047 ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_t usb1_ecc;
5048 ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_t clock_manager;
5049 ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_t fpga_manager_register;
5050 ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_t pin_mux_register;
5051 ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_t reset_manager;
5052 ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_t system_manager;
5053 ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_t osc0_timer;
5054 ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_t osc1_timer;
5055 ALT_NOC_FW_L4_SYS_SCR_WD0_t watchdog0;
5056 ALT_NOC_FW_L4_SYS_SCR_WD1_t watchdog1;
5057 ALT_NOC_FW_L4_SYS_SCR_DAP_t dap;
5058 ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_t fpga_manager_streaming;
5059 ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_t security_manager_streaming;
5060 ALT_NOC_FW_L4_SYS_SCR_HMC_REG_t hmc_register;
5061 ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_t hmc_adaptor_register;
5062 ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_t l3_interconnect_register;
5063 ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_t ddr_scheduler_register;
5064 ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_t l4_interconnect_firewall_csr;
5065 ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_t l4_interconnect_probes_csr;
5066 ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_t l4_qos_csr;
5067 volatile uint32_t _pad_0x98_0x100[26];
5071 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_s ALT_NOC_FW_L4_SYS_SCR_t;
5073 struct ALT_NOC_FW_L4_SYS_SCR_raw_s
5075 volatile uint32_t can0_ecc;
5076 volatile uint32_t can1_ecc;
5077 volatile uint32_t dma_ecc;
5078 volatile uint32_t emac0rx_ecc;
5079 volatile uint32_t emac0tx_ecc;
5080 volatile uint32_t emac1rx_ecc;
5081 volatile uint32_t emac1tx_ecc;
5082 volatile uint32_t emac2rx_ecc;
5083 volatile uint32_t emac2tx_ecc;
5084 volatile uint32_t emac3rx_ecc;
5085 volatile uint32_t emac3tx_ecc;
5086 volatile uint32_t nand_ecc;
5087 volatile uint32_t nand_read_ecc;
5088 volatile uint32_t nand_write_ecc;
5089 volatile uint32_t onchipram_ecc;
5090 volatile uint32_t qspi_ecc;
5091 volatile uint32_t sdmmc_ecc;
5092 volatile uint32_t usb0_ecc;
5093 volatile uint32_t usb1_ecc;
5094 volatile uint32_t clock_manager;
5095 volatile uint32_t fpga_manager_register;
5096 volatile uint32_t pin_mux_register;
5097 volatile uint32_t reset_manager;
5098 volatile uint32_t system_manager;
5099 volatile uint32_t osc0_timer;
5100 volatile uint32_t osc1_timer;
5101 volatile uint32_t watchdog0;
5102 volatile uint32_t watchdog1;
5103 volatile uint32_t dap;
5104 volatile uint32_t fpga_manager_streaming;
5105 volatile uint32_t security_manager_streaming;
5106 volatile uint32_t hmc_register;
5107 volatile uint32_t hmc_adaptor_register;
5108 volatile uint32_t l3_interconnect_register;
5109 volatile uint32_t ddr_scheduler_register;
5110 volatile uint32_t l4_interconnect_firewall_csr;
5111 volatile uint32_t l4_interconnect_probes_csr;
5112 volatile uint32_t l4_qos_csr;
5113 uint32_t _pad_0x98_0x100[26];
5117 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_raw_s ALT_NOC_FW_L4_SYS_SCR_raw_t;