Altera SoCAL  20.1
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
 All Groups
alt_tmr.h
1 /***********************************************************************************
2 * *
3 * Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
4 * *
5 * Redistribution and use in source and binary forms, with or without *
6 * modification, are permitted provided that the following conditions are met: *
7 * *
8 * 1. Redistributions of source code must retain the above copyright notice, *
9 * this list of conditions and the following disclaimer. *
10 * *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, *
12 * this list of conditions and the following disclaimer in the documentation *
13 * and/or other materials provided with the distribution. *
14 * *
15 * 3. Neither the name of the copyright holder nor the names of its contributors *
16 * may be used to endorse or promote products derived from this software without *
17 * specific prior written permission. *
18 * *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
29 * POSSIBILITY OF SUCH DAMAGE. *
30 * *
31 ***********************************************************************************/
32 
33 /* Altera - ALT_TMR */
34 
35 #ifndef __ALTERA_ALT_TMR_H__
36 #define __ALTERA_ALT_TMR_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
43 /*
44  * Component : Timer Module - ALT_TMR
45  * Timer Module
46  *
47  * Registers in the timer module. The timer IP core supports multiple timers but it
48  * is configured for just one timer. The term Timer1 refers to this one timer in
49  * the IP core and not the module instance.
50  *
51  */
52 /*
53  * Register : Timer1 Load Count Register - timer1loadcount
54  *
55  * Used to load counter value into Timer1
56  *
57  * Register Layout
58  *
59  * Bits | Access | Reset | Description
60  * :-------|:-------|:------|:----------------
61  * [31:0] | RW | 0x0 | Timer1LoadCount
62  *
63  */
64 /*
65  * Field : Timer1LoadCount - timer1loadcount
66  *
67  * Value to be loaded into Timer1. This is the value from which counting commences.
68  * Any value written to this register is loaded into the associated timer.
69  *
70  * Field Access Macros:
71  *
72  */
73 /* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field. */
74 #define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_LSB 0
75 /* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field. */
76 #define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_MSB 31
77 /* The width in bits of the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field. */
78 #define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_WIDTH 32
79 /* The mask used to set the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field value. */
80 #define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_SET_MSK 0xffffffff
81 /* The mask used to clear the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field value. */
82 #define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_CLR_MSK 0x00000000
83 /* The reset value of the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field. */
84 #define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_RESET 0x0
85 /* Extracts the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT field value from a register. */
86 #define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_GET(value) (((value) & 0xffffffff) >> 0)
87 /* Produces a ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field value suitable for setting the register. */
88 #define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_SET(value) (((value) << 0) & 0xffffffff)
89 
90 #ifndef __ASSEMBLY__
91 /*
92  * WARNING: The C register and register group struct declarations are provided for
93  * convenience and illustrative purposes. They should, however, be used with
94  * caution as the C language standard provides no guarantees about the alignment or
95  * atomicity of device memory accesses. The recommended practice for writing
96  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
97  * alt_write_word() functions.
98  *
99  * The struct declaration for register ALT_TMR_TMR1LDCOUNT.
100  */
101 struct ALT_TMR_TMR1LDCOUNT_s
102 {
103  uint32_t timer1loadcount : 32; /* Timer1LoadCount */
104 };
105 
106 /* The typedef declaration for register ALT_TMR_TMR1LDCOUNT. */
107 typedef volatile struct ALT_TMR_TMR1LDCOUNT_s ALT_TMR_TMR1LDCOUNT_t;
108 #endif /* __ASSEMBLY__ */
109 
110 /* The byte offset of the ALT_TMR_TMR1LDCOUNT register from the beginning of the component. */
111 #define ALT_TMR_TMR1LDCOUNT_OFST 0x0
112 /* The address of the ALT_TMR_TMR1LDCOUNT register. */
113 #define ALT_TMR_TMR1LDCOUNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMR1LDCOUNT_OFST))
114 
115 /*
116  * Register : Timer1 Current Value Register - timer1currentval
117  *
118  * Provides current value of Timer1
119  *
120  * Register Layout
121  *
122  * Bits | Access | Reset | Description
123  * :-------|:-------|:------|:---------------------
124  * [31:0] | R | 0x0 | Timer1 Current Value
125  *
126  */
127 /*
128  * Field : Timer1 Current Value - timer1currentval
129  *
130  * Current value of Timer1.
131  *
132  * Field Access Macros:
133  *
134  */
135 /* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field. */
136 #define ALT_TMR_TMR1CURVAL_TMR1CURVAL_LSB 0
137 /* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field. */
138 #define ALT_TMR_TMR1CURVAL_TMR1CURVAL_MSB 31
139 /* The width in bits of the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field. */
140 #define ALT_TMR_TMR1CURVAL_TMR1CURVAL_WIDTH 32
141 /* The mask used to set the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field value. */
142 #define ALT_TMR_TMR1CURVAL_TMR1CURVAL_SET_MSK 0xffffffff
143 /* The mask used to clear the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field value. */
144 #define ALT_TMR_TMR1CURVAL_TMR1CURVAL_CLR_MSK 0x00000000
145 /* The reset value of the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field. */
146 #define ALT_TMR_TMR1CURVAL_TMR1CURVAL_RESET 0x0
147 /* Extracts the ALT_TMR_TMR1CURVAL_TMR1CURVAL field value from a register. */
148 #define ALT_TMR_TMR1CURVAL_TMR1CURVAL_GET(value) (((value) & 0xffffffff) >> 0)
149 /* Produces a ALT_TMR_TMR1CURVAL_TMR1CURVAL register field value suitable for setting the register. */
150 #define ALT_TMR_TMR1CURVAL_TMR1CURVAL_SET(value) (((value) << 0) & 0xffffffff)
151 
152 #ifndef __ASSEMBLY__
153 /*
154  * WARNING: The C register and register group struct declarations are provided for
155  * convenience and illustrative purposes. They should, however, be used with
156  * caution as the C language standard provides no guarantees about the alignment or
157  * atomicity of device memory accesses. The recommended practice for writing
158  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
159  * alt_write_word() functions.
160  *
161  * The struct declaration for register ALT_TMR_TMR1CURVAL.
162  */
163 struct ALT_TMR_TMR1CURVAL_s
164 {
165  const uint32_t timer1currentval : 32; /* Timer1 Current Value */
166 };
167 
168 /* The typedef declaration for register ALT_TMR_TMR1CURVAL. */
169 typedef volatile struct ALT_TMR_TMR1CURVAL_s ALT_TMR_TMR1CURVAL_t;
170 #endif /* __ASSEMBLY__ */
171 
172 /* The byte offset of the ALT_TMR_TMR1CURVAL register from the beginning of the component. */
173 #define ALT_TMR_TMR1CURVAL_OFST 0x4
174 /* The address of the ALT_TMR_TMR1CURVAL register. */
175 #define ALT_TMR_TMR1CURVAL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMR1CURVAL_OFST))
176 
177 /*
178  * Register : Timer1 Control Register - timer1controlreg
179  *
180  * This register controls enabling, operating mode (free-running or user-defined-
181  * count), and interrupt mask of Timer1. You can program this register to enable or
182  * disable Timer1 and to control its mode of operation.
183  *
184  * Register Layout
185  *
186  * Bits | Access | Reset | Description
187  * :-------|:-------|:------|:----------------------
188  * [0] | RW | 0x0 | Timer1 Enable
189  * [1] | RW | 0x0 | Timer1 Mode
190  * [2] | RW | 0x0 | Timer1 Interrupt Mask
191  * [31:3] | ??? | 0x0 | *UNDEFINED*
192  *
193  */
194 /*
195  * Field : Timer1 Enable - timer1_enable
196  *
197  * Timer1 enable/disable bit.
198  *
199  * Field Enumeration Values:
200  *
201  * Enum | Value | Description
202  * :----------------------------------|:------|:----------------
203  * ALT_TMR_TMR1CTLREG_TMR1_EN_E_DISD | 0x0 | Timer1 Disabled
204  * ALT_TMR_TMR1CTLREG_TMR1_EN_E_END | 0x1 | Timer1 Enabled
205  *
206  * Field Access Macros:
207  *
208  */
209 /*
210  * Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_EN
211  *
212  * Timer1 Disabled
213  */
214 #define ALT_TMR_TMR1CTLREG_TMR1_EN_E_DISD 0x0
215 /*
216  * Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_EN
217  *
218  * Timer1 Enabled
219  */
220 #define ALT_TMR_TMR1CTLREG_TMR1_EN_E_END 0x1
221 
222 /* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1CTLREG_TMR1_EN register field. */
223 #define ALT_TMR_TMR1CTLREG_TMR1_EN_LSB 0
224 /* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1CTLREG_TMR1_EN register field. */
225 #define ALT_TMR_TMR1CTLREG_TMR1_EN_MSB 0
226 /* The width in bits of the ALT_TMR_TMR1CTLREG_TMR1_EN register field. */
227 #define ALT_TMR_TMR1CTLREG_TMR1_EN_WIDTH 1
228 /* The mask used to set the ALT_TMR_TMR1CTLREG_TMR1_EN register field value. */
229 #define ALT_TMR_TMR1CTLREG_TMR1_EN_SET_MSK 0x00000001
230 /* The mask used to clear the ALT_TMR_TMR1CTLREG_TMR1_EN register field value. */
231 #define ALT_TMR_TMR1CTLREG_TMR1_EN_CLR_MSK 0xfffffffe
232 /* The reset value of the ALT_TMR_TMR1CTLREG_TMR1_EN register field. */
233 #define ALT_TMR_TMR1CTLREG_TMR1_EN_RESET 0x0
234 /* Extracts the ALT_TMR_TMR1CTLREG_TMR1_EN field value from a register. */
235 #define ALT_TMR_TMR1CTLREG_TMR1_EN_GET(value) (((value) & 0x00000001) >> 0)
236 /* Produces a ALT_TMR_TMR1CTLREG_TMR1_EN register field value suitable for setting the register. */
237 #define ALT_TMR_TMR1CTLREG_TMR1_EN_SET(value) (((value) << 0) & 0x00000001)
238 
239 /*
240  * Field : Timer1 Mode - timer1_mode
241  *
242  * Sets operating mode.
243  *
244  * NOTE: You must set the timer1loadcount register to all ones before enabling the
245  * timer in free-running mode.
246  *
247  * Field Enumeration Values:
248  *
249  * Enum | Value | Description
250  * :--------------------------------------|:------|:------------------------
251  * ALT_TMR_TMR1CTLREG_TMR1_MOD_E_FREERUN | 0x0 | Free-running mode
252  * ALT_TMR_TMR1CTLREG_TMR1_MOD_E_USEDEF | 0x1 | User-defined count mode
253  *
254  * Field Access Macros:
255  *
256  */
257 /*
258  * Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_MOD
259  *
260  * Free-running mode
261  */
262 #define ALT_TMR_TMR1CTLREG_TMR1_MOD_E_FREERUN 0x0
263 /*
264  * Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_MOD
265  *
266  * User-defined count mode
267  */
268 #define ALT_TMR_TMR1CTLREG_TMR1_MOD_E_USEDEF 0x1
269 
270 /* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1CTLREG_TMR1_MOD register field. */
271 #define ALT_TMR_TMR1CTLREG_TMR1_MOD_LSB 1
272 /* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1CTLREG_TMR1_MOD register field. */
273 #define ALT_TMR_TMR1CTLREG_TMR1_MOD_MSB 1
274 /* The width in bits of the ALT_TMR_TMR1CTLREG_TMR1_MOD register field. */
275 #define ALT_TMR_TMR1CTLREG_TMR1_MOD_WIDTH 1
276 /* The mask used to set the ALT_TMR_TMR1CTLREG_TMR1_MOD register field value. */
277 #define ALT_TMR_TMR1CTLREG_TMR1_MOD_SET_MSK 0x00000002
278 /* The mask used to clear the ALT_TMR_TMR1CTLREG_TMR1_MOD register field value. */
279 #define ALT_TMR_TMR1CTLREG_TMR1_MOD_CLR_MSK 0xfffffffd
280 /* The reset value of the ALT_TMR_TMR1CTLREG_TMR1_MOD register field. */
281 #define ALT_TMR_TMR1CTLREG_TMR1_MOD_RESET 0x0
282 /* Extracts the ALT_TMR_TMR1CTLREG_TMR1_MOD field value from a register. */
283 #define ALT_TMR_TMR1CTLREG_TMR1_MOD_GET(value) (((value) & 0x00000002) >> 1)
284 /* Produces a ALT_TMR_TMR1CTLREG_TMR1_MOD register field value suitable for setting the register. */
285 #define ALT_TMR_TMR1CTLREG_TMR1_MOD_SET(value) (((value) << 1) & 0x00000002)
286 
287 /*
288  * Field : Timer1 Interrupt Mask - timer1_interrupt_mask
289  *
290  * Timer1 interrupt mask
291  *
292  * Field Enumeration Values:
293  *
294  * Enum | Value | Description
295  * :-------------------------------------------|:------|:-------------------------------
296  * ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_E_NOTMSKED | 0x0 | interrupt not masked (enabled)
297  * ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_E_MSKED | 0x1 | interrupt masked (disabled)
298  *
299  * Field Access Macros:
300  *
301  */
302 /*
303  * Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_INT_MSK
304  *
305  * interrupt not masked (enabled)
306  */
307 #define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_E_NOTMSKED 0x0
308 /*
309  * Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_INT_MSK
310  *
311  * interrupt masked (disabled)
312  */
313 #define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_E_MSKED 0x1
314 
315 /* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field. */
316 #define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_LSB 2
317 /* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field. */
318 #define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_MSB 2
319 /* The width in bits of the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field. */
320 #define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_WIDTH 1
321 /* The mask used to set the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field value. */
322 #define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_SET_MSK 0x00000004
323 /* The mask used to clear the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field value. */
324 #define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_CLR_MSK 0xfffffffb
325 /* The reset value of the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field. */
326 #define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_RESET 0x0
327 /* Extracts the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK field value from a register. */
328 #define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_GET(value) (((value) & 0x00000004) >> 2)
329 /* Produces a ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field value suitable for setting the register. */
330 #define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_SET(value) (((value) << 2) & 0x00000004)
331 
332 #ifndef __ASSEMBLY__
333 /*
334  * WARNING: The C register and register group struct declarations are provided for
335  * convenience and illustrative purposes. They should, however, be used with
336  * caution as the C language standard provides no guarantees about the alignment or
337  * atomicity of device memory accesses. The recommended practice for writing
338  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
339  * alt_write_word() functions.
340  *
341  * The struct declaration for register ALT_TMR_TMR1CTLREG.
342  */
343 struct ALT_TMR_TMR1CTLREG_s
344 {
345  uint32_t timer1_enable : 1; /* Timer1 Enable */
346  uint32_t timer1_mode : 1; /* Timer1 Mode */
347  uint32_t timer1_interrupt_mask : 1; /* Timer1 Interrupt Mask */
348  uint32_t : 29; /* *UNDEFINED* */
349 };
350 
351 /* The typedef declaration for register ALT_TMR_TMR1CTLREG. */
352 typedef volatile struct ALT_TMR_TMR1CTLREG_s ALT_TMR_TMR1CTLREG_t;
353 #endif /* __ASSEMBLY__ */
354 
355 /* The byte offset of the ALT_TMR_TMR1CTLREG register from the beginning of the component. */
356 #define ALT_TMR_TMR1CTLREG_OFST 0x8
357 /* The address of the ALT_TMR_TMR1CTLREG register. */
358 #define ALT_TMR_TMR1CTLREG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMR1CTLREG_OFST))
359 
360 /*
361  * Register : Timer1 End-of-Interrupt Register - timer1eoi
362  *
363  * Clears Timer1 interrupt when read.
364  *
365  * Register Layout
366  *
367  * Bits | Access | Reset | Description
368  * :-------|:-------|:------|:------------------------
369  * [0] | R | 0x0 | Timer1 End of Interrupt
370  * [31:1] | ??? | 0x0 | *UNDEFINED*
371  *
372  */
373 /*
374  * Field : Timer1 End of Interrupt - timer1eoi
375  *
376  * Reading from this register clears the interrupt from Timer1 and returns 0.
377  *
378  * Field Access Macros:
379  *
380  */
381 /* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1EOI_TMR1EOI register field. */
382 #define ALT_TMR_TMR1EOI_TMR1EOI_LSB 0
383 /* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1EOI_TMR1EOI register field. */
384 #define ALT_TMR_TMR1EOI_TMR1EOI_MSB 0
385 /* The width in bits of the ALT_TMR_TMR1EOI_TMR1EOI register field. */
386 #define ALT_TMR_TMR1EOI_TMR1EOI_WIDTH 1
387 /* The mask used to set the ALT_TMR_TMR1EOI_TMR1EOI register field value. */
388 #define ALT_TMR_TMR1EOI_TMR1EOI_SET_MSK 0x00000001
389 /* The mask used to clear the ALT_TMR_TMR1EOI_TMR1EOI register field value. */
390 #define ALT_TMR_TMR1EOI_TMR1EOI_CLR_MSK 0xfffffffe
391 /* The reset value of the ALT_TMR_TMR1EOI_TMR1EOI register field. */
392 #define ALT_TMR_TMR1EOI_TMR1EOI_RESET 0x0
393 /* Extracts the ALT_TMR_TMR1EOI_TMR1EOI field value from a register. */
394 #define ALT_TMR_TMR1EOI_TMR1EOI_GET(value) (((value) & 0x00000001) >> 0)
395 /* Produces a ALT_TMR_TMR1EOI_TMR1EOI register field value suitable for setting the register. */
396 #define ALT_TMR_TMR1EOI_TMR1EOI_SET(value) (((value) << 0) & 0x00000001)
397 
398 #ifndef __ASSEMBLY__
399 /*
400  * WARNING: The C register and register group struct declarations are provided for
401  * convenience and illustrative purposes. They should, however, be used with
402  * caution as the C language standard provides no guarantees about the alignment or
403  * atomicity of device memory accesses. The recommended practice for writing
404  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
405  * alt_write_word() functions.
406  *
407  * The struct declaration for register ALT_TMR_TMR1EOI.
408  */
409 struct ALT_TMR_TMR1EOI_s
410 {
411  const uint32_t timer1eoi : 1; /* Timer1 End of Interrupt */
412  uint32_t : 31; /* *UNDEFINED* */
413 };
414 
415 /* The typedef declaration for register ALT_TMR_TMR1EOI. */
416 typedef volatile struct ALT_TMR_TMR1EOI_s ALT_TMR_TMR1EOI_t;
417 #endif /* __ASSEMBLY__ */
418 
419 /* The byte offset of the ALT_TMR_TMR1EOI register from the beginning of the component. */
420 #define ALT_TMR_TMR1EOI_OFST 0xc
421 /* The address of the ALT_TMR_TMR1EOI register. */
422 #define ALT_TMR_TMR1EOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMR1EOI_OFST))
423 
424 /*
425  * Register : Timer1 Interrupt Status Register - timer1intstat
426  *
427  * Provides the interrupt status of Timer1 after masking.
428  *
429  * Register Layout
430  *
431  * Bits | Access | Reset | Description
432  * :-------|:-------|:------|:------------------------
433  * [0] | R | 0x0 | Timer1 Interrupt Status
434  * [31:1] | ??? | 0x0 | *UNDEFINED*
435  *
436  */
437 /*
438  * Field : Timer1 Interrupt Status - timer1intstat
439  *
440  * Provides the interrupt status for Timer1. The status reported is after the
441  * interrupt mask has been applied. Reading from this register does not clear any
442  * active interrupts.
443  *
444  * Field Enumeration Values:
445  *
446  * Enum | Value | Description
447  * :----------------------------------------|:------|:-------------------------------
448  * ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_E_INACT | 0x0 | Timer1 interrupt is not active
449  * ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_E_ACT | 0x1 | Timer1 interrupt is active
450  *
451  * Field Access Macros:
452  *
453  */
454 /*
455  * Enumerated value for register field ALT_TMR_TMR1INTSTAT_TMR1INTSTAT
456  *
457  * Timer1 interrupt is not active
458  */
459 #define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_E_INACT 0x0
460 /*
461  * Enumerated value for register field ALT_TMR_TMR1INTSTAT_TMR1INTSTAT
462  *
463  * Timer1 interrupt is active
464  */
465 #define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_E_ACT 0x1
466 
467 /* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field. */
468 #define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_LSB 0
469 /* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field. */
470 #define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_MSB 0
471 /* The width in bits of the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field. */
472 #define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_WIDTH 1
473 /* The mask used to set the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field value. */
474 #define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_SET_MSK 0x00000001
475 /* The mask used to clear the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field value. */
476 #define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_CLR_MSK 0xfffffffe
477 /* The reset value of the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field. */
478 #define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_RESET 0x0
479 /* Extracts the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT field value from a register. */
480 #define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_GET(value) (((value) & 0x00000001) >> 0)
481 /* Produces a ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field value suitable for setting the register. */
482 #define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_SET(value) (((value) << 0) & 0x00000001)
483 
484 #ifndef __ASSEMBLY__
485 /*
486  * WARNING: The C register and register group struct declarations are provided for
487  * convenience and illustrative purposes. They should, however, be used with
488  * caution as the C language standard provides no guarantees about the alignment or
489  * atomicity of device memory accesses. The recommended practice for writing
490  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
491  * alt_write_word() functions.
492  *
493  * The struct declaration for register ALT_TMR_TMR1INTSTAT.
494  */
495 struct ALT_TMR_TMR1INTSTAT_s
496 {
497  const uint32_t timer1intstat : 1; /* Timer1 Interrupt Status */
498  uint32_t : 31; /* *UNDEFINED* */
499 };
500 
501 /* The typedef declaration for register ALT_TMR_TMR1INTSTAT. */
502 typedef volatile struct ALT_TMR_TMR1INTSTAT_s ALT_TMR_TMR1INTSTAT_t;
503 #endif /* __ASSEMBLY__ */
504 
505 /* The byte offset of the ALT_TMR_TMR1INTSTAT register from the beginning of the component. */
506 #define ALT_TMR_TMR1INTSTAT_OFST 0x10
507 /* The address of the ALT_TMR_TMR1INTSTAT register. */
508 #define ALT_TMR_TMR1INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMR1INTSTAT_OFST))
509 
510 /*
511  * Register : Timers Interrupt Status Register - timersintstat
512  *
513  * Provides the interrupt status for all timers after masking. Because there is
514  * only Timer1 in this module instance, this status is the same as timer1intstat.
515  *
516  * Register Layout
517  *
518  * Bits | Access | Reset | Description
519  * :-------|:-------|:------|:------------------------
520  * [0] | R | 0x0 | Timers Interrupt Status
521  * [31:1] | ??? | 0x0 | *UNDEFINED*
522  *
523  */
524 /*
525  * Field : Timers Interrupt Status - timersintstat
526  *
527  * Provides the interrupt status for Timer1. Because there is only Timer1 in this
528  * module instance, this status is the same as timer1intstat. The status reported
529  * is after the interrupt mask has been applied. Reading from this register does
530  * not clear any active interrupts.
531  *
532  * Field Enumeration Values:
533  *
534  * Enum | Value | Description
535  * :----------------------------------------|:------|:-------------------------
536  * ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_E_INACT | 0x0 | timer_intr is not active
537  * ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_E_ACT | 0x1 | timer_intr is active
538  *
539  * Field Access Macros:
540  *
541  */
542 /*
543  * Enumerated value for register field ALT_TMR_TMRSINTSTAT_TMRSINTSTAT
544  *
545  * timer_intr is not active
546  */
547 #define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_E_INACT 0x0
548 /*
549  * Enumerated value for register field ALT_TMR_TMRSINTSTAT_TMRSINTSTAT
550  *
551  * timer_intr is active
552  */
553 #define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_E_ACT 0x1
554 
555 /* The Least Significant Bit (LSB) position of the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field. */
556 #define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_LSB 0
557 /* The Most Significant Bit (MSB) position of the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field. */
558 #define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_MSB 0
559 /* The width in bits of the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field. */
560 #define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_WIDTH 1
561 /* The mask used to set the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field value. */
562 #define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_SET_MSK 0x00000001
563 /* The mask used to clear the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field value. */
564 #define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_CLR_MSK 0xfffffffe
565 /* The reset value of the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field. */
566 #define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_RESET 0x0
567 /* Extracts the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT field value from a register. */
568 #define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_GET(value) (((value) & 0x00000001) >> 0)
569 /* Produces a ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field value suitable for setting the register. */
570 #define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_SET(value) (((value) << 0) & 0x00000001)
571 
572 #ifndef __ASSEMBLY__
573 /*
574  * WARNING: The C register and register group struct declarations are provided for
575  * convenience and illustrative purposes. They should, however, be used with
576  * caution as the C language standard provides no guarantees about the alignment or
577  * atomicity of device memory accesses. The recommended practice for writing
578  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
579  * alt_write_word() functions.
580  *
581  * The struct declaration for register ALT_TMR_TMRSINTSTAT.
582  */
583 struct ALT_TMR_TMRSINTSTAT_s
584 {
585  const uint32_t timersintstat : 1; /* Timers Interrupt Status */
586  uint32_t : 31; /* *UNDEFINED* */
587 };
588 
589 /* The typedef declaration for register ALT_TMR_TMRSINTSTAT. */
590 typedef volatile struct ALT_TMR_TMRSINTSTAT_s ALT_TMR_TMRSINTSTAT_t;
591 #endif /* __ASSEMBLY__ */
592 
593 /* The byte offset of the ALT_TMR_TMRSINTSTAT register from the beginning of the component. */
594 #define ALT_TMR_TMRSINTSTAT_OFST 0xa0
595 /* The address of the ALT_TMR_TMRSINTSTAT register. */
596 #define ALT_TMR_TMRSINTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMRSINTSTAT_OFST))
597 
598 /*
599  * Register : Timers End-of-Interrupt Register - timerseoi
600  *
601  * Clears Timer1 interrupt when read. Because there is only Timer1 in this module
602  * instance, reading this register has the same effect as reading timer1eoi.
603  *
604  * Register Layout
605  *
606  * Bits | Access | Reset | Description
607  * :-------|:-------|:------|:------------------------
608  * [0] | R | 0x0 | Timers End-of-Interrupt
609  * [31:1] | ??? | 0x0 | *UNDEFINED*
610  *
611  */
612 /*
613  * Field : Timers End-of-Interrupt - timerseoi
614  *
615  * Reading from this register clears the interrupt all timers and returns 0.
616  * Because there is only Timer1 in this module instance, reading this register has
617  * the same effect as reading timer1eoi.
618  *
619  * Field Access Macros:
620  *
621  */
622 /* The Least Significant Bit (LSB) position of the ALT_TMR_TMRSEOI_TMRSEOI register field. */
623 #define ALT_TMR_TMRSEOI_TMRSEOI_LSB 0
624 /* The Most Significant Bit (MSB) position of the ALT_TMR_TMRSEOI_TMRSEOI register field. */
625 #define ALT_TMR_TMRSEOI_TMRSEOI_MSB 0
626 /* The width in bits of the ALT_TMR_TMRSEOI_TMRSEOI register field. */
627 #define ALT_TMR_TMRSEOI_TMRSEOI_WIDTH 1
628 /* The mask used to set the ALT_TMR_TMRSEOI_TMRSEOI register field value. */
629 #define ALT_TMR_TMRSEOI_TMRSEOI_SET_MSK 0x00000001
630 /* The mask used to clear the ALT_TMR_TMRSEOI_TMRSEOI register field value. */
631 #define ALT_TMR_TMRSEOI_TMRSEOI_CLR_MSK 0xfffffffe
632 /* The reset value of the ALT_TMR_TMRSEOI_TMRSEOI register field. */
633 #define ALT_TMR_TMRSEOI_TMRSEOI_RESET 0x0
634 /* Extracts the ALT_TMR_TMRSEOI_TMRSEOI field value from a register. */
635 #define ALT_TMR_TMRSEOI_TMRSEOI_GET(value) (((value) & 0x00000001) >> 0)
636 /* Produces a ALT_TMR_TMRSEOI_TMRSEOI register field value suitable for setting the register. */
637 #define ALT_TMR_TMRSEOI_TMRSEOI_SET(value) (((value) << 0) & 0x00000001)
638 
639 #ifndef __ASSEMBLY__
640 /*
641  * WARNING: The C register and register group struct declarations are provided for
642  * convenience and illustrative purposes. They should, however, be used with
643  * caution as the C language standard provides no guarantees about the alignment or
644  * atomicity of device memory accesses. The recommended practice for writing
645  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
646  * alt_write_word() functions.
647  *
648  * The struct declaration for register ALT_TMR_TMRSEOI.
649  */
650 struct ALT_TMR_TMRSEOI_s
651 {
652  const uint32_t timerseoi : 1; /* Timers End-of-Interrupt */
653  uint32_t : 31; /* *UNDEFINED* */
654 };
655 
656 /* The typedef declaration for register ALT_TMR_TMRSEOI. */
657 typedef volatile struct ALT_TMR_TMRSEOI_s ALT_TMR_TMRSEOI_t;
658 #endif /* __ASSEMBLY__ */
659 
660 /* The byte offset of the ALT_TMR_TMRSEOI register from the beginning of the component. */
661 #define ALT_TMR_TMRSEOI_OFST 0xa4
662 /* The address of the ALT_TMR_TMRSEOI register. */
663 #define ALT_TMR_TMRSEOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMRSEOI_OFST))
664 
665 /*
666  * Register : Timers Raw Interrupt Status Register - timersrawintstat
667  *
668  * Provides the interrupt status for all timers before masking. Note that there is
669  * only Timer1 in this module instance.
670  *
671  * Register Layout
672  *
673  * Bits | Access | Reset | Description
674  * :-------|:-------|:------|:----------------------------
675  * [0] | R | 0x0 | Timers Raw Interrupt Status
676  * [31:1] | ??? | 0x0 | *UNDEFINED*
677  *
678  */
679 /*
680  * Field : Timers Raw Interrupt Status - timersrawintstat
681  *
682  * Provides the interrupt status for Timer1. Because there is only Timer1 in this
683  * module instance, this status is the same as timer1intstat. The status reported
684  * is before the interrupt mask has been applied. Reading from this register does
685  * not clear any active interrupts.
686  *
687  * Field Enumeration Values:
688  *
689  * Enum | Value | Description
690  * :----------------------------------------------|:------|:-------------------------------
691  * ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_E_INACT | 0x0 | Timer1 interrupt is not active
692  * ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_E_ACT | 0x1 | Timer1 interrupt is active
693  *
694  * Field Access Macros:
695  *
696  */
697 /*
698  * Enumerated value for register field ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT
699  *
700  * Timer1 interrupt is not active
701  */
702 #define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_E_INACT 0x0
703 /*
704  * Enumerated value for register field ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT
705  *
706  * Timer1 interrupt is active
707  */
708 #define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_E_ACT 0x1
709 
710 /* The Least Significant Bit (LSB) position of the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field. */
711 #define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_LSB 0
712 /* The Most Significant Bit (MSB) position of the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field. */
713 #define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_MSB 0
714 /* The width in bits of the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field. */
715 #define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_WIDTH 1
716 /* The mask used to set the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field value. */
717 #define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_SET_MSK 0x00000001
718 /* The mask used to clear the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field value. */
719 #define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_CLR_MSK 0xfffffffe
720 /* The reset value of the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field. */
721 #define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_RESET 0x0
722 /* Extracts the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT field value from a register. */
723 #define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_GET(value) (((value) & 0x00000001) >> 0)
724 /* Produces a ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field value suitable for setting the register. */
725 #define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_SET(value) (((value) << 0) & 0x00000001)
726 
727 #ifndef __ASSEMBLY__
728 /*
729  * WARNING: The C register and register group struct declarations are provided for
730  * convenience and illustrative purposes. They should, however, be used with
731  * caution as the C language standard provides no guarantees about the alignment or
732  * atomicity of device memory accesses. The recommended practice for writing
733  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
734  * alt_write_word() functions.
735  *
736  * The struct declaration for register ALT_TMR_TMRSRAWINTSTAT.
737  */
738 struct ALT_TMR_TMRSRAWINTSTAT_s
739 {
740  const uint32_t timersrawintstat : 1; /* Timers Raw Interrupt Status */
741  uint32_t : 31; /* *UNDEFINED* */
742 };
743 
744 /* The typedef declaration for register ALT_TMR_TMRSRAWINTSTAT. */
745 typedef volatile struct ALT_TMR_TMRSRAWINTSTAT_s ALT_TMR_TMRSRAWINTSTAT_t;
746 #endif /* __ASSEMBLY__ */
747 
748 /* The byte offset of the ALT_TMR_TMRSRAWINTSTAT register from the beginning of the component. */
749 #define ALT_TMR_TMRSRAWINTSTAT_OFST 0xa8
750 /* The address of the ALT_TMR_TMRSRAWINTSTAT register. */
751 #define ALT_TMR_TMRSRAWINTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMRSRAWINTSTAT_OFST))
752 
753 /*
754  * Register : Timers Component Version Register - timerscompversion
755  *
756  * Register Layout
757  *
758  * Bits | Access | Reset | Description
759  * :-------|:-------|:-----------|:-------------------------
760  * [31:0] | R | 0x3230352a | Timers Component Version
761  *
762  */
763 /*
764  * Field : Timers Component Version - timerscompversion
765  *
766  * Current revision number of the timers component.
767  *
768  * Field Access Macros:
769  *
770  */
771 /* The Least Significant Bit (LSB) position of the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field. */
772 #define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_LSB 0
773 /* The Most Significant Bit (MSB) position of the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field. */
774 #define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_MSB 31
775 /* The width in bits of the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field. */
776 #define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_WIDTH 32
777 /* The mask used to set the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field value. */
778 #define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_SET_MSK 0xffffffff
779 /* The mask used to clear the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field value. */
780 #define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_CLR_MSK 0x00000000
781 /* The reset value of the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field. */
782 #define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_RESET 0x3230352a
783 /* Extracts the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER field value from a register. */
784 #define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_GET(value) (((value) & 0xffffffff) >> 0)
785 /* Produces a ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field value suitable for setting the register. */
786 #define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_SET(value) (((value) << 0) & 0xffffffff)
787 
788 #ifndef __ASSEMBLY__
789 /*
790  * WARNING: The C register and register group struct declarations are provided for
791  * convenience and illustrative purposes. They should, however, be used with
792  * caution as the C language standard provides no guarantees about the alignment or
793  * atomicity of device memory accesses. The recommended practice for writing
794  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
795  * alt_write_word() functions.
796  *
797  * The struct declaration for register ALT_TMR_TMRSCOMPVER.
798  */
799 struct ALT_TMR_TMRSCOMPVER_s
800 {
801  const uint32_t timerscompversion : 32; /* Timers Component Version */
802 };
803 
804 /* The typedef declaration for register ALT_TMR_TMRSCOMPVER. */
805 typedef volatile struct ALT_TMR_TMRSCOMPVER_s ALT_TMR_TMRSCOMPVER_t;
806 #endif /* __ASSEMBLY__ */
807 
808 /* The byte offset of the ALT_TMR_TMRSCOMPVER register from the beginning of the component. */
809 #define ALT_TMR_TMRSCOMPVER_OFST 0xac
810 /* The address of the ALT_TMR_TMRSCOMPVER register. */
811 #define ALT_TMR_TMRSCOMPVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMRSCOMPVER_OFST))
812 
813 #ifndef __ASSEMBLY__
814 /*
815  * WARNING: The C register and register group struct declarations are provided for
816  * convenience and illustrative purposes. They should, however, be used with
817  * caution as the C language standard provides no guarantees about the alignment or
818  * atomicity of device memory accesses. The recommended practice for writing
819  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
820  * alt_write_word() functions.
821  *
822  * The struct declaration for register group ALT_TMR.
823  */
824 struct ALT_TMR_s
825 {
826  ALT_TMR_TMR1LDCOUNT_t timer1loadcount; /* ALT_TMR_TMR1LDCOUNT */
827  ALT_TMR_TMR1CURVAL_t timer1currentval; /* ALT_TMR_TMR1CURVAL */
828  ALT_TMR_TMR1CTLREG_t timer1controlreg; /* ALT_TMR_TMR1CTLREG */
829  ALT_TMR_TMR1EOI_t timer1eoi; /* ALT_TMR_TMR1EOI */
830  ALT_TMR_TMR1INTSTAT_t timer1intstat; /* ALT_TMR_TMR1INTSTAT */
831  volatile uint32_t _pad_0x14_0x9f[35]; /* *UNDEFINED* */
832  ALT_TMR_TMRSINTSTAT_t timersintstat; /* ALT_TMR_TMRSINTSTAT */
833  ALT_TMR_TMRSEOI_t timerseoi; /* ALT_TMR_TMRSEOI */
834  ALT_TMR_TMRSRAWINTSTAT_t timersrawintstat; /* ALT_TMR_TMRSRAWINTSTAT */
835  ALT_TMR_TMRSCOMPVER_t timerscompversion; /* ALT_TMR_TMRSCOMPVER */
836  volatile uint32_t _pad_0xb0_0x100[20]; /* *UNDEFINED* */
837 };
838 
839 /* The typedef declaration for register group ALT_TMR. */
840 typedef volatile struct ALT_TMR_s ALT_TMR_t;
841 /* The struct declaration for the raw register contents of register group ALT_TMR. */
842 struct ALT_TMR_raw_s
843 {
844  volatile uint32_t timer1loadcount; /* ALT_TMR_TMR1LDCOUNT */
845  volatile uint32_t timer1currentval; /* ALT_TMR_TMR1CURVAL */
846  volatile uint32_t timer1controlreg; /* ALT_TMR_TMR1CTLREG */
847  volatile uint32_t timer1eoi; /* ALT_TMR_TMR1EOI */
848  volatile uint32_t timer1intstat; /* ALT_TMR_TMR1INTSTAT */
849  uint32_t _pad_0x14_0x9f[35]; /* *UNDEFINED* */
850  volatile uint32_t timersintstat; /* ALT_TMR_TMRSINTSTAT */
851  volatile uint32_t timerseoi; /* ALT_TMR_TMRSEOI */
852  volatile uint32_t timersrawintstat; /* ALT_TMR_TMRSRAWINTSTAT */
853  volatile uint32_t timerscompversion; /* ALT_TMR_TMRSCOMPVER */
854  uint32_t _pad_0xb0_0x100[20]; /* *UNDEFINED* */
855 };
856 
857 /* The typedef declaration for the raw register contents of register group ALT_TMR. */
858 typedef volatile struct ALT_TMR_raw_s ALT_TMR_raw_t;
859 #endif /* __ASSEMBLY__ */
860 
861 
862 #ifdef __cplusplus
863 }
864 #endif /* __cplusplus */
865 #endif /* __ALTERA_ALT_TMR_H__ */
866