35 #ifndef __ALT_SOCAL_GIC_H__
36 #define __ALT_SOCAL_GIC_H__
77 #define ALT_GIC_DIST_GICD_CTLR_FLD_LSB 0
79 #define ALT_GIC_DIST_GICD_CTLR_FLD_MSB 31
81 #define ALT_GIC_DIST_GICD_CTLR_FLD_WIDTH 32
83 #define ALT_GIC_DIST_GICD_CTLR_FLD_SET_MSK 0xffffffff
85 #define ALT_GIC_DIST_GICD_CTLR_FLD_CLR_MSK 0x00000000
87 #define ALT_GIC_DIST_GICD_CTLR_FLD_RESET 0x0
89 #define ALT_GIC_DIST_GICD_CTLR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
91 #define ALT_GIC_DIST_GICD_CTLR_FLD_SET(value) (((value) << 0) & 0xffffffff)
105 struct ALT_GIC_DIST_GICD_CTLR_s
107 volatile uint32_t fld : 32;
111 typedef struct ALT_GIC_DIST_GICD_CTLR_s ALT_GIC_DIST_GICD_CTLR_t;
115 #define ALT_GIC_DIST_GICD_CTLR_RESET 0x00000000
117 #define ALT_GIC_DIST_GICD_CTLR_OFST 0x0
140 #define ALT_GIC_DIST_GICD_TYPER_FLD_LSB 0
142 #define ALT_GIC_DIST_GICD_TYPER_FLD_MSB 31
144 #define ALT_GIC_DIST_GICD_TYPER_FLD_WIDTH 32
146 #define ALT_GIC_DIST_GICD_TYPER_FLD_SET_MSK 0xffffffff
148 #define ALT_GIC_DIST_GICD_TYPER_FLD_CLR_MSK 0x00000000
150 #define ALT_GIC_DIST_GICD_TYPER_FLD_RESET 0x0
152 #define ALT_GIC_DIST_GICD_TYPER_FLD_GET(value) (((value) & 0xffffffff) >> 0)
154 #define ALT_GIC_DIST_GICD_TYPER_FLD_SET(value) (((value) << 0) & 0xffffffff)
168 struct ALT_GIC_DIST_GICD_TYPER_s
170 volatile uint32_t fld : 32;
174 typedef struct ALT_GIC_DIST_GICD_TYPER_s ALT_GIC_DIST_GICD_TYPER_t;
178 #define ALT_GIC_DIST_GICD_TYPER_RESET 0x00000000
180 #define ALT_GIC_DIST_GICD_TYPER_OFST 0x4
203 #define ALT_GIC_DIST_GICD_IIDR_FLD_LSB 0
205 #define ALT_GIC_DIST_GICD_IIDR_FLD_MSB 31
207 #define ALT_GIC_DIST_GICD_IIDR_FLD_WIDTH 32
209 #define ALT_GIC_DIST_GICD_IIDR_FLD_SET_MSK 0xffffffff
211 #define ALT_GIC_DIST_GICD_IIDR_FLD_CLR_MSK 0x00000000
213 #define ALT_GIC_DIST_GICD_IIDR_FLD_RESET 0x200143b
215 #define ALT_GIC_DIST_GICD_IIDR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
217 #define ALT_GIC_DIST_GICD_IIDR_FLD_SET(value) (((value) << 0) & 0xffffffff)
231 struct ALT_GIC_DIST_GICD_IIDR_s
233 volatile uint32_t fld : 32;
237 typedef struct ALT_GIC_DIST_GICD_IIDR_s ALT_GIC_DIST_GICD_IIDR_t;
241 #define ALT_GIC_DIST_GICD_IIDR_RESET 0x0200143b
243 #define ALT_GIC_DIST_GICD_IIDR_OFST 0x8
266 #define ALT_GIC_DIST_GICD_IGROUPR0_FLD_LSB 0
268 #define ALT_GIC_DIST_GICD_IGROUPR0_FLD_MSB 31
270 #define ALT_GIC_DIST_GICD_IGROUPR0_FLD_WIDTH 32
272 #define ALT_GIC_DIST_GICD_IGROUPR0_FLD_SET_MSK 0xffffffff
274 #define ALT_GIC_DIST_GICD_IGROUPR0_FLD_CLR_MSK 0x00000000
276 #define ALT_GIC_DIST_GICD_IGROUPR0_FLD_RESET 0x0
278 #define ALT_GIC_DIST_GICD_IGROUPR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
280 #define ALT_GIC_DIST_GICD_IGROUPR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
294 struct ALT_GIC_DIST_GICD_IGROUPR0_s
296 volatile uint32_t fld : 32;
300 typedef struct ALT_GIC_DIST_GICD_IGROUPR0_s ALT_GIC_DIST_GICD_IGROUPR0_t;
304 #define ALT_GIC_DIST_GICD_IGROUPR0_RESET 0x00000000
306 #define ALT_GIC_DIST_GICD_IGROUPR0_OFST 0x80
329 #define ALT_GIC_DIST_GICD_IGROUPR1_FLD_LSB 0
331 #define ALT_GIC_DIST_GICD_IGROUPR1_FLD_MSB 31
333 #define ALT_GIC_DIST_GICD_IGROUPR1_FLD_WIDTH 32
335 #define ALT_GIC_DIST_GICD_IGROUPR1_FLD_SET_MSK 0xffffffff
337 #define ALT_GIC_DIST_GICD_IGROUPR1_FLD_CLR_MSK 0x00000000
339 #define ALT_GIC_DIST_GICD_IGROUPR1_FLD_RESET 0x0
341 #define ALT_GIC_DIST_GICD_IGROUPR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
343 #define ALT_GIC_DIST_GICD_IGROUPR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
357 struct ALT_GIC_DIST_GICD_IGROUPR1_s
359 volatile uint32_t fld : 32;
363 typedef struct ALT_GIC_DIST_GICD_IGROUPR1_s ALT_GIC_DIST_GICD_IGROUPR1_t;
367 #define ALT_GIC_DIST_GICD_IGROUPR1_RESET 0x00000000
369 #define ALT_GIC_DIST_GICD_IGROUPR1_OFST 0x84
392 #define ALT_GIC_DIST_GICD_IGROUPR2_FLD_LSB 0
394 #define ALT_GIC_DIST_GICD_IGROUPR2_FLD_MSB 31
396 #define ALT_GIC_DIST_GICD_IGROUPR2_FLD_WIDTH 32
398 #define ALT_GIC_DIST_GICD_IGROUPR2_FLD_SET_MSK 0xffffffff
400 #define ALT_GIC_DIST_GICD_IGROUPR2_FLD_CLR_MSK 0x00000000
402 #define ALT_GIC_DIST_GICD_IGROUPR2_FLD_RESET 0x0
404 #define ALT_GIC_DIST_GICD_IGROUPR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
406 #define ALT_GIC_DIST_GICD_IGROUPR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
420 struct ALT_GIC_DIST_GICD_IGROUPR2_s
422 volatile uint32_t fld : 32;
426 typedef struct ALT_GIC_DIST_GICD_IGROUPR2_s ALT_GIC_DIST_GICD_IGROUPR2_t;
430 #define ALT_GIC_DIST_GICD_IGROUPR2_RESET 0x00000000
432 #define ALT_GIC_DIST_GICD_IGROUPR2_OFST 0x88
455 #define ALT_GIC_DIST_GICD_IGROUPR3_FLD_LSB 0
457 #define ALT_GIC_DIST_GICD_IGROUPR3_FLD_MSB 31
459 #define ALT_GIC_DIST_GICD_IGROUPR3_FLD_WIDTH 32
461 #define ALT_GIC_DIST_GICD_IGROUPR3_FLD_SET_MSK 0xffffffff
463 #define ALT_GIC_DIST_GICD_IGROUPR3_FLD_CLR_MSK 0x00000000
465 #define ALT_GIC_DIST_GICD_IGROUPR3_FLD_RESET 0x0
467 #define ALT_GIC_DIST_GICD_IGROUPR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
469 #define ALT_GIC_DIST_GICD_IGROUPR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
483 struct ALT_GIC_DIST_GICD_IGROUPR3_s
485 volatile uint32_t fld : 32;
489 typedef struct ALT_GIC_DIST_GICD_IGROUPR3_s ALT_GIC_DIST_GICD_IGROUPR3_t;
493 #define ALT_GIC_DIST_GICD_IGROUPR3_RESET 0x00000000
495 #define ALT_GIC_DIST_GICD_IGROUPR3_OFST 0x8c
518 #define ALT_GIC_DIST_GICD_IGROUPR4_FLD_LSB 0
520 #define ALT_GIC_DIST_GICD_IGROUPR4_FLD_MSB 31
522 #define ALT_GIC_DIST_GICD_IGROUPR4_FLD_WIDTH 32
524 #define ALT_GIC_DIST_GICD_IGROUPR4_FLD_SET_MSK 0xffffffff
526 #define ALT_GIC_DIST_GICD_IGROUPR4_FLD_CLR_MSK 0x00000000
528 #define ALT_GIC_DIST_GICD_IGROUPR4_FLD_RESET 0x0
530 #define ALT_GIC_DIST_GICD_IGROUPR4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
532 #define ALT_GIC_DIST_GICD_IGROUPR4_FLD_SET(value) (((value) << 0) & 0xffffffff)
546 struct ALT_GIC_DIST_GICD_IGROUPR4_s
548 volatile uint32_t fld : 32;
552 typedef struct ALT_GIC_DIST_GICD_IGROUPR4_s ALT_GIC_DIST_GICD_IGROUPR4_t;
556 #define ALT_GIC_DIST_GICD_IGROUPR4_RESET 0x00000000
558 #define ALT_GIC_DIST_GICD_IGROUPR4_OFST 0x90
581 #define ALT_GIC_DIST_GICD_IGROUPR5_FLD_LSB 0
583 #define ALT_GIC_DIST_GICD_IGROUPR5_FLD_MSB 31
585 #define ALT_GIC_DIST_GICD_IGROUPR5_FLD_WIDTH 32
587 #define ALT_GIC_DIST_GICD_IGROUPR5_FLD_SET_MSK 0xffffffff
589 #define ALT_GIC_DIST_GICD_IGROUPR5_FLD_CLR_MSK 0x00000000
591 #define ALT_GIC_DIST_GICD_IGROUPR5_FLD_RESET 0x0
593 #define ALT_GIC_DIST_GICD_IGROUPR5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
595 #define ALT_GIC_DIST_GICD_IGROUPR5_FLD_SET(value) (((value) << 0) & 0xffffffff)
609 struct ALT_GIC_DIST_GICD_IGROUPR5_s
611 volatile uint32_t fld : 32;
615 typedef struct ALT_GIC_DIST_GICD_IGROUPR5_s ALT_GIC_DIST_GICD_IGROUPR5_t;
619 #define ALT_GIC_DIST_GICD_IGROUPR5_RESET 0x00000000
621 #define ALT_GIC_DIST_GICD_IGROUPR5_OFST 0x94
644 #define ALT_GIC_DIST_GICD_IGROUPR6_FLD_LSB 0
646 #define ALT_GIC_DIST_GICD_IGROUPR6_FLD_MSB 31
648 #define ALT_GIC_DIST_GICD_IGROUPR6_FLD_WIDTH 32
650 #define ALT_GIC_DIST_GICD_IGROUPR6_FLD_SET_MSK 0xffffffff
652 #define ALT_GIC_DIST_GICD_IGROUPR6_FLD_CLR_MSK 0x00000000
654 #define ALT_GIC_DIST_GICD_IGROUPR6_FLD_RESET 0x0
656 #define ALT_GIC_DIST_GICD_IGROUPR6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
658 #define ALT_GIC_DIST_GICD_IGROUPR6_FLD_SET(value) (((value) << 0) & 0xffffffff)
672 struct ALT_GIC_DIST_GICD_IGROUPR6_s
674 volatile uint32_t fld : 32;
678 typedef struct ALT_GIC_DIST_GICD_IGROUPR6_s ALT_GIC_DIST_GICD_IGROUPR6_t;
682 #define ALT_GIC_DIST_GICD_IGROUPR6_RESET 0x00000000
684 #define ALT_GIC_DIST_GICD_IGROUPR6_OFST 0x98
707 #define ALT_GIC_DIST_GICD_IGROUPR7_FLD_LSB 0
709 #define ALT_GIC_DIST_GICD_IGROUPR7_FLD_MSB 31
711 #define ALT_GIC_DIST_GICD_IGROUPR7_FLD_WIDTH 32
713 #define ALT_GIC_DIST_GICD_IGROUPR7_FLD_SET_MSK 0xffffffff
715 #define ALT_GIC_DIST_GICD_IGROUPR7_FLD_CLR_MSK 0x00000000
717 #define ALT_GIC_DIST_GICD_IGROUPR7_FLD_RESET 0x0
719 #define ALT_GIC_DIST_GICD_IGROUPR7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
721 #define ALT_GIC_DIST_GICD_IGROUPR7_FLD_SET(value) (((value) << 0) & 0xffffffff)
735 struct ALT_GIC_DIST_GICD_IGROUPR7_s
737 volatile uint32_t fld : 32;
741 typedef struct ALT_GIC_DIST_GICD_IGROUPR7_s ALT_GIC_DIST_GICD_IGROUPR7_t;
745 #define ALT_GIC_DIST_GICD_IGROUPR7_RESET 0x00000000
747 #define ALT_GIC_DIST_GICD_IGROUPR7_OFST 0x9c
770 #define ALT_GIC_DIST_GICD_IGROUPR8_FLD_LSB 0
772 #define ALT_GIC_DIST_GICD_IGROUPR8_FLD_MSB 31
774 #define ALT_GIC_DIST_GICD_IGROUPR8_FLD_WIDTH 32
776 #define ALT_GIC_DIST_GICD_IGROUPR8_FLD_SET_MSK 0xffffffff
778 #define ALT_GIC_DIST_GICD_IGROUPR8_FLD_CLR_MSK 0x00000000
780 #define ALT_GIC_DIST_GICD_IGROUPR8_FLD_RESET 0x0
782 #define ALT_GIC_DIST_GICD_IGROUPR8_FLD_GET(value) (((value) & 0xffffffff) >> 0)
784 #define ALT_GIC_DIST_GICD_IGROUPR8_FLD_SET(value) (((value) << 0) & 0xffffffff)
798 struct ALT_GIC_DIST_GICD_IGROUPR8_s
800 volatile uint32_t fld : 32;
804 typedef struct ALT_GIC_DIST_GICD_IGROUPR8_s ALT_GIC_DIST_GICD_IGROUPR8_t;
808 #define ALT_GIC_DIST_GICD_IGROUPR8_RESET 0x00000000
810 #define ALT_GIC_DIST_GICD_IGROUPR8_OFST 0xa0
833 #define ALT_GIC_DIST_GICD_IGROUPR9_FLD_LSB 0
835 #define ALT_GIC_DIST_GICD_IGROUPR9_FLD_MSB 31
837 #define ALT_GIC_DIST_GICD_IGROUPR9_FLD_WIDTH 32
839 #define ALT_GIC_DIST_GICD_IGROUPR9_FLD_SET_MSK 0xffffffff
841 #define ALT_GIC_DIST_GICD_IGROUPR9_FLD_CLR_MSK 0x00000000
843 #define ALT_GIC_DIST_GICD_IGROUPR9_FLD_RESET 0x0
845 #define ALT_GIC_DIST_GICD_IGROUPR9_FLD_GET(value) (((value) & 0xffffffff) >> 0)
847 #define ALT_GIC_DIST_GICD_IGROUPR9_FLD_SET(value) (((value) << 0) & 0xffffffff)
861 struct ALT_GIC_DIST_GICD_IGROUPR9_s
863 volatile uint32_t fld : 32;
867 typedef struct ALT_GIC_DIST_GICD_IGROUPR9_s ALT_GIC_DIST_GICD_IGROUPR9_t;
871 #define ALT_GIC_DIST_GICD_IGROUPR9_RESET 0x00000000
873 #define ALT_GIC_DIST_GICD_IGROUPR9_OFST 0xa4
896 #define ALT_GIC_DIST_GICD_IGROUPR10_FLD_LSB 0
898 #define ALT_GIC_DIST_GICD_IGROUPR10_FLD_MSB 31
900 #define ALT_GIC_DIST_GICD_IGROUPR10_FLD_WIDTH 32
902 #define ALT_GIC_DIST_GICD_IGROUPR10_FLD_SET_MSK 0xffffffff
904 #define ALT_GIC_DIST_GICD_IGROUPR10_FLD_CLR_MSK 0x00000000
906 #define ALT_GIC_DIST_GICD_IGROUPR10_FLD_RESET 0x0
908 #define ALT_GIC_DIST_GICD_IGROUPR10_FLD_GET(value) (((value) & 0xffffffff) >> 0)
910 #define ALT_GIC_DIST_GICD_IGROUPR10_FLD_SET(value) (((value) << 0) & 0xffffffff)
924 struct ALT_GIC_DIST_GICD_IGROUPR10_s
926 volatile uint32_t fld : 32;
930 typedef struct ALT_GIC_DIST_GICD_IGROUPR10_s ALT_GIC_DIST_GICD_IGROUPR10_t;
934 #define ALT_GIC_DIST_GICD_IGROUPR10_RESET 0x00000000
936 #define ALT_GIC_DIST_GICD_IGROUPR10_OFST 0xa8
959 #define ALT_GIC_DIST_GICD_IGROUPR11_FLD_LSB 0
961 #define ALT_GIC_DIST_GICD_IGROUPR11_FLD_MSB 31
963 #define ALT_GIC_DIST_GICD_IGROUPR11_FLD_WIDTH 32
965 #define ALT_GIC_DIST_GICD_IGROUPR11_FLD_SET_MSK 0xffffffff
967 #define ALT_GIC_DIST_GICD_IGROUPR11_FLD_CLR_MSK 0x00000000
969 #define ALT_GIC_DIST_GICD_IGROUPR11_FLD_RESET 0x0
971 #define ALT_GIC_DIST_GICD_IGROUPR11_FLD_GET(value) (((value) & 0xffffffff) >> 0)
973 #define ALT_GIC_DIST_GICD_IGROUPR11_FLD_SET(value) (((value) << 0) & 0xffffffff)
987 struct ALT_GIC_DIST_GICD_IGROUPR11_s
989 volatile uint32_t fld : 32;
993 typedef struct ALT_GIC_DIST_GICD_IGROUPR11_s ALT_GIC_DIST_GICD_IGROUPR11_t;
997 #define ALT_GIC_DIST_GICD_IGROUPR11_RESET 0x00000000
999 #define ALT_GIC_DIST_GICD_IGROUPR11_OFST 0xac
1022 #define ALT_GIC_DIST_GICD_IGROUPR12_FLD_LSB 0
1024 #define ALT_GIC_DIST_GICD_IGROUPR12_FLD_MSB 31
1026 #define ALT_GIC_DIST_GICD_IGROUPR12_FLD_WIDTH 32
1028 #define ALT_GIC_DIST_GICD_IGROUPR12_FLD_SET_MSK 0xffffffff
1030 #define ALT_GIC_DIST_GICD_IGROUPR12_FLD_CLR_MSK 0x00000000
1032 #define ALT_GIC_DIST_GICD_IGROUPR12_FLD_RESET 0x0
1034 #define ALT_GIC_DIST_GICD_IGROUPR12_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1036 #define ALT_GIC_DIST_GICD_IGROUPR12_FLD_SET(value) (((value) << 0) & 0xffffffff)
1038 #ifndef __ASSEMBLY__
1050 struct ALT_GIC_DIST_GICD_IGROUPR12_s
1052 volatile uint32_t fld : 32;
1056 typedef struct ALT_GIC_DIST_GICD_IGROUPR12_s ALT_GIC_DIST_GICD_IGROUPR12_t;
1060 #define ALT_GIC_DIST_GICD_IGROUPR12_RESET 0x00000000
1062 #define ALT_GIC_DIST_GICD_IGROUPR12_OFST 0xb0
1085 #define ALT_GIC_DIST_GICD_IGROUPR13_FLD_LSB 0
1087 #define ALT_GIC_DIST_GICD_IGROUPR13_FLD_MSB 31
1089 #define ALT_GIC_DIST_GICD_IGROUPR13_FLD_WIDTH 32
1091 #define ALT_GIC_DIST_GICD_IGROUPR13_FLD_SET_MSK 0xffffffff
1093 #define ALT_GIC_DIST_GICD_IGROUPR13_FLD_CLR_MSK 0x00000000
1095 #define ALT_GIC_DIST_GICD_IGROUPR13_FLD_RESET 0x0
1097 #define ALT_GIC_DIST_GICD_IGROUPR13_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1099 #define ALT_GIC_DIST_GICD_IGROUPR13_FLD_SET(value) (((value) << 0) & 0xffffffff)
1101 #ifndef __ASSEMBLY__
1113 struct ALT_GIC_DIST_GICD_IGROUPR13_s
1115 volatile uint32_t fld : 32;
1119 typedef struct ALT_GIC_DIST_GICD_IGROUPR13_s ALT_GIC_DIST_GICD_IGROUPR13_t;
1123 #define ALT_GIC_DIST_GICD_IGROUPR13_RESET 0x00000000
1125 #define ALT_GIC_DIST_GICD_IGROUPR13_OFST 0xb4
1148 #define ALT_GIC_DIST_GICD_IGROUPR14_FLD_LSB 0
1150 #define ALT_GIC_DIST_GICD_IGROUPR14_FLD_MSB 31
1152 #define ALT_GIC_DIST_GICD_IGROUPR14_FLD_WIDTH 32
1154 #define ALT_GIC_DIST_GICD_IGROUPR14_FLD_SET_MSK 0xffffffff
1156 #define ALT_GIC_DIST_GICD_IGROUPR14_FLD_CLR_MSK 0x00000000
1158 #define ALT_GIC_DIST_GICD_IGROUPR14_FLD_RESET 0x0
1160 #define ALT_GIC_DIST_GICD_IGROUPR14_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1162 #define ALT_GIC_DIST_GICD_IGROUPR14_FLD_SET(value) (((value) << 0) & 0xffffffff)
1164 #ifndef __ASSEMBLY__
1176 struct ALT_GIC_DIST_GICD_IGROUPR14_s
1178 volatile uint32_t fld : 32;
1182 typedef struct ALT_GIC_DIST_GICD_IGROUPR14_s ALT_GIC_DIST_GICD_IGROUPR14_t;
1186 #define ALT_GIC_DIST_GICD_IGROUPR14_RESET 0x00000000
1188 #define ALT_GIC_DIST_GICD_IGROUPR14_OFST 0xb8
1211 #define ALT_GIC_DIST_GICD_IGROUPR15_FLD_LSB 0
1213 #define ALT_GIC_DIST_GICD_IGROUPR15_FLD_MSB 31
1215 #define ALT_GIC_DIST_GICD_IGROUPR15_FLD_WIDTH 32
1217 #define ALT_GIC_DIST_GICD_IGROUPR15_FLD_SET_MSK 0xffffffff
1219 #define ALT_GIC_DIST_GICD_IGROUPR15_FLD_CLR_MSK 0x00000000
1221 #define ALT_GIC_DIST_GICD_IGROUPR15_FLD_RESET 0x0
1223 #define ALT_GIC_DIST_GICD_IGROUPR15_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1225 #define ALT_GIC_DIST_GICD_IGROUPR15_FLD_SET(value) (((value) << 0) & 0xffffffff)
1227 #ifndef __ASSEMBLY__
1239 struct ALT_GIC_DIST_GICD_IGROUPR15_s
1241 volatile uint32_t fld : 32;
1245 typedef struct ALT_GIC_DIST_GICD_IGROUPR15_s ALT_GIC_DIST_GICD_IGROUPR15_t;
1249 #define ALT_GIC_DIST_GICD_IGROUPR15_RESET 0x00000000
1251 #define ALT_GIC_DIST_GICD_IGROUPR15_OFST 0xbc
1274 #define ALT_GIC_DIST_GICD_ISENABLER0_FLD_LSB 0
1276 #define ALT_GIC_DIST_GICD_ISENABLER0_FLD_MSB 31
1278 #define ALT_GIC_DIST_GICD_ISENABLER0_FLD_WIDTH 32
1280 #define ALT_GIC_DIST_GICD_ISENABLER0_FLD_SET_MSK 0xffffffff
1282 #define ALT_GIC_DIST_GICD_ISENABLER0_FLD_CLR_MSK 0x00000000
1284 #define ALT_GIC_DIST_GICD_ISENABLER0_FLD_RESET 0x0
1286 #define ALT_GIC_DIST_GICD_ISENABLER0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1288 #define ALT_GIC_DIST_GICD_ISENABLER0_FLD_SET(value) (((value) << 0) & 0xffffffff)
1290 #ifndef __ASSEMBLY__
1302 struct ALT_GIC_DIST_GICD_ISENABLER0_s
1304 volatile uint32_t fld : 32;
1308 typedef struct ALT_GIC_DIST_GICD_ISENABLER0_s ALT_GIC_DIST_GICD_ISENABLER0_t;
1312 #define ALT_GIC_DIST_GICD_ISENABLER0_RESET 0x0000ffff
1314 #define ALT_GIC_DIST_GICD_ISENABLER0_OFST 0x100
1337 #define ALT_GIC_DIST_GICD_ISENABLER1_FLD_LSB 0
1339 #define ALT_GIC_DIST_GICD_ISENABLER1_FLD_MSB 31
1341 #define ALT_GIC_DIST_GICD_ISENABLER1_FLD_WIDTH 32
1343 #define ALT_GIC_DIST_GICD_ISENABLER1_FLD_SET_MSK 0xffffffff
1345 #define ALT_GIC_DIST_GICD_ISENABLER1_FLD_CLR_MSK 0x00000000
1347 #define ALT_GIC_DIST_GICD_ISENABLER1_FLD_RESET 0x0
1349 #define ALT_GIC_DIST_GICD_ISENABLER1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1351 #define ALT_GIC_DIST_GICD_ISENABLER1_FLD_SET(value) (((value) << 0) & 0xffffffff)
1353 #ifndef __ASSEMBLY__
1365 struct ALT_GIC_DIST_GICD_ISENABLER1_s
1367 volatile uint32_t fld : 32;
1371 typedef struct ALT_GIC_DIST_GICD_ISENABLER1_s ALT_GIC_DIST_GICD_ISENABLER1_t;
1375 #define ALT_GIC_DIST_GICD_ISENABLER1_RESET 0x00000000
1377 #define ALT_GIC_DIST_GICD_ISENABLER1_OFST 0x104
1400 #define ALT_GIC_DIST_GICD_ISENABLER2_FLD_LSB 0
1402 #define ALT_GIC_DIST_GICD_ISENABLER2_FLD_MSB 31
1404 #define ALT_GIC_DIST_GICD_ISENABLER2_FLD_WIDTH 32
1406 #define ALT_GIC_DIST_GICD_ISENABLER2_FLD_SET_MSK 0xffffffff
1408 #define ALT_GIC_DIST_GICD_ISENABLER2_FLD_CLR_MSK 0x00000000
1410 #define ALT_GIC_DIST_GICD_ISENABLER2_FLD_RESET 0x0
1412 #define ALT_GIC_DIST_GICD_ISENABLER2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1414 #define ALT_GIC_DIST_GICD_ISENABLER2_FLD_SET(value) (((value) << 0) & 0xffffffff)
1416 #ifndef __ASSEMBLY__
1428 struct ALT_GIC_DIST_GICD_ISENABLER2_s
1430 volatile uint32_t fld : 32;
1434 typedef struct ALT_GIC_DIST_GICD_ISENABLER2_s ALT_GIC_DIST_GICD_ISENABLER2_t;
1438 #define ALT_GIC_DIST_GICD_ISENABLER2_RESET 0x00000000
1440 #define ALT_GIC_DIST_GICD_ISENABLER2_OFST 0x108
1463 #define ALT_GIC_DIST_GICD_ISENABLER3_FLD_LSB 0
1465 #define ALT_GIC_DIST_GICD_ISENABLER3_FLD_MSB 31
1467 #define ALT_GIC_DIST_GICD_ISENABLER3_FLD_WIDTH 32
1469 #define ALT_GIC_DIST_GICD_ISENABLER3_FLD_SET_MSK 0xffffffff
1471 #define ALT_GIC_DIST_GICD_ISENABLER3_FLD_CLR_MSK 0x00000000
1473 #define ALT_GIC_DIST_GICD_ISENABLER3_FLD_RESET 0x0
1475 #define ALT_GIC_DIST_GICD_ISENABLER3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1477 #define ALT_GIC_DIST_GICD_ISENABLER3_FLD_SET(value) (((value) << 0) & 0xffffffff)
1479 #ifndef __ASSEMBLY__
1491 struct ALT_GIC_DIST_GICD_ISENABLER3_s
1493 volatile uint32_t fld : 32;
1497 typedef struct ALT_GIC_DIST_GICD_ISENABLER3_s ALT_GIC_DIST_GICD_ISENABLER3_t;
1501 #define ALT_GIC_DIST_GICD_ISENABLER3_RESET 0x00000000
1503 #define ALT_GIC_DIST_GICD_ISENABLER3_OFST 0x10c
1526 #define ALT_GIC_DIST_GICD_ISENABLER4_FLD_LSB 0
1528 #define ALT_GIC_DIST_GICD_ISENABLER4_FLD_MSB 31
1530 #define ALT_GIC_DIST_GICD_ISENABLER4_FLD_WIDTH 32
1532 #define ALT_GIC_DIST_GICD_ISENABLER4_FLD_SET_MSK 0xffffffff
1534 #define ALT_GIC_DIST_GICD_ISENABLER4_FLD_CLR_MSK 0x00000000
1536 #define ALT_GIC_DIST_GICD_ISENABLER4_FLD_RESET 0x0
1538 #define ALT_GIC_DIST_GICD_ISENABLER4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1540 #define ALT_GIC_DIST_GICD_ISENABLER4_FLD_SET(value) (((value) << 0) & 0xffffffff)
1542 #ifndef __ASSEMBLY__
1554 struct ALT_GIC_DIST_GICD_ISENABLER4_s
1556 volatile uint32_t fld : 32;
1560 typedef struct ALT_GIC_DIST_GICD_ISENABLER4_s ALT_GIC_DIST_GICD_ISENABLER4_t;
1564 #define ALT_GIC_DIST_GICD_ISENABLER4_RESET 0x00000000
1566 #define ALT_GIC_DIST_GICD_ISENABLER4_OFST 0x110
1589 #define ALT_GIC_DIST_GICD_ISENABLER5_FLD_LSB 0
1591 #define ALT_GIC_DIST_GICD_ISENABLER5_FLD_MSB 31
1593 #define ALT_GIC_DIST_GICD_ISENABLER5_FLD_WIDTH 32
1595 #define ALT_GIC_DIST_GICD_ISENABLER5_FLD_SET_MSK 0xffffffff
1597 #define ALT_GIC_DIST_GICD_ISENABLER5_FLD_CLR_MSK 0x00000000
1599 #define ALT_GIC_DIST_GICD_ISENABLER5_FLD_RESET 0x0
1601 #define ALT_GIC_DIST_GICD_ISENABLER5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1603 #define ALT_GIC_DIST_GICD_ISENABLER5_FLD_SET(value) (((value) << 0) & 0xffffffff)
1605 #ifndef __ASSEMBLY__
1617 struct ALT_GIC_DIST_GICD_ISENABLER5_s
1619 volatile uint32_t fld : 32;
1623 typedef struct ALT_GIC_DIST_GICD_ISENABLER5_s ALT_GIC_DIST_GICD_ISENABLER5_t;
1627 #define ALT_GIC_DIST_GICD_ISENABLER5_RESET 0x00000000
1629 #define ALT_GIC_DIST_GICD_ISENABLER5_OFST 0x114
1652 #define ALT_GIC_DIST_GICD_ISENABLER6_FLD_LSB 0
1654 #define ALT_GIC_DIST_GICD_ISENABLER6_FLD_MSB 31
1656 #define ALT_GIC_DIST_GICD_ISENABLER6_FLD_WIDTH 32
1658 #define ALT_GIC_DIST_GICD_ISENABLER6_FLD_SET_MSK 0xffffffff
1660 #define ALT_GIC_DIST_GICD_ISENABLER6_FLD_CLR_MSK 0x00000000
1662 #define ALT_GIC_DIST_GICD_ISENABLER6_FLD_RESET 0x0
1664 #define ALT_GIC_DIST_GICD_ISENABLER6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1666 #define ALT_GIC_DIST_GICD_ISENABLER6_FLD_SET(value) (((value) << 0) & 0xffffffff)
1668 #ifndef __ASSEMBLY__
1680 struct ALT_GIC_DIST_GICD_ISENABLER6_s
1682 volatile uint32_t fld : 32;
1686 typedef struct ALT_GIC_DIST_GICD_ISENABLER6_s ALT_GIC_DIST_GICD_ISENABLER6_t;
1690 #define ALT_GIC_DIST_GICD_ISENABLER6_RESET 0x00000000
1692 #define ALT_GIC_DIST_GICD_ISENABLER6_OFST 0x118
1715 #define ALT_GIC_DIST_GICD_ISENABLER7_FLD_LSB 0
1717 #define ALT_GIC_DIST_GICD_ISENABLER7_FLD_MSB 31
1719 #define ALT_GIC_DIST_GICD_ISENABLER7_FLD_WIDTH 32
1721 #define ALT_GIC_DIST_GICD_ISENABLER7_FLD_SET_MSK 0xffffffff
1723 #define ALT_GIC_DIST_GICD_ISENABLER7_FLD_CLR_MSK 0x00000000
1725 #define ALT_GIC_DIST_GICD_ISENABLER7_FLD_RESET 0x0
1727 #define ALT_GIC_DIST_GICD_ISENABLER7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1729 #define ALT_GIC_DIST_GICD_ISENABLER7_FLD_SET(value) (((value) << 0) & 0xffffffff)
1731 #ifndef __ASSEMBLY__
1743 struct ALT_GIC_DIST_GICD_ISENABLER7_s
1745 volatile uint32_t fld : 32;
1749 typedef struct ALT_GIC_DIST_GICD_ISENABLER7_s ALT_GIC_DIST_GICD_ISENABLER7_t;
1753 #define ALT_GIC_DIST_GICD_ISENABLER7_RESET 0x00000000
1755 #define ALT_GIC_DIST_GICD_ISENABLER7_OFST 0x11c
1778 #define ALT_GIC_DIST_GICD_ISENABLER8_FLD_LSB 0
1780 #define ALT_GIC_DIST_GICD_ISENABLER8_FLD_MSB 31
1782 #define ALT_GIC_DIST_GICD_ISENABLER8_FLD_WIDTH 32
1784 #define ALT_GIC_DIST_GICD_ISENABLER8_FLD_SET_MSK 0xffffffff
1786 #define ALT_GIC_DIST_GICD_ISENABLER8_FLD_CLR_MSK 0x00000000
1788 #define ALT_GIC_DIST_GICD_ISENABLER8_FLD_RESET 0x0
1790 #define ALT_GIC_DIST_GICD_ISENABLER8_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1792 #define ALT_GIC_DIST_GICD_ISENABLER8_FLD_SET(value) (((value) << 0) & 0xffffffff)
1794 #ifndef __ASSEMBLY__
1806 struct ALT_GIC_DIST_GICD_ISENABLER8_s
1808 volatile uint32_t fld : 32;
1812 typedef struct ALT_GIC_DIST_GICD_ISENABLER8_s ALT_GIC_DIST_GICD_ISENABLER8_t;
1816 #define ALT_GIC_DIST_GICD_ISENABLER8_RESET 0x00000000
1818 #define ALT_GIC_DIST_GICD_ISENABLER8_OFST 0x120
1841 #define ALT_GIC_DIST_GICD_ISENABLER9_FLD_LSB 0
1843 #define ALT_GIC_DIST_GICD_ISENABLER9_FLD_MSB 31
1845 #define ALT_GIC_DIST_GICD_ISENABLER9_FLD_WIDTH 32
1847 #define ALT_GIC_DIST_GICD_ISENABLER9_FLD_SET_MSK 0xffffffff
1849 #define ALT_GIC_DIST_GICD_ISENABLER9_FLD_CLR_MSK 0x00000000
1851 #define ALT_GIC_DIST_GICD_ISENABLER9_FLD_RESET 0x0
1853 #define ALT_GIC_DIST_GICD_ISENABLER9_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1855 #define ALT_GIC_DIST_GICD_ISENABLER9_FLD_SET(value) (((value) << 0) & 0xffffffff)
1857 #ifndef __ASSEMBLY__
1869 struct ALT_GIC_DIST_GICD_ISENABLER9_s
1871 volatile uint32_t fld : 32;
1875 typedef struct ALT_GIC_DIST_GICD_ISENABLER9_s ALT_GIC_DIST_GICD_ISENABLER9_t;
1879 #define ALT_GIC_DIST_GICD_ISENABLER9_RESET 0x00000000
1881 #define ALT_GIC_DIST_GICD_ISENABLER9_OFST 0x124
1904 #define ALT_GIC_DIST_GICD_ISENABLER10_FLD_LSB 0
1906 #define ALT_GIC_DIST_GICD_ISENABLER10_FLD_MSB 31
1908 #define ALT_GIC_DIST_GICD_ISENABLER10_FLD_WIDTH 32
1910 #define ALT_GIC_DIST_GICD_ISENABLER10_FLD_SET_MSK 0xffffffff
1912 #define ALT_GIC_DIST_GICD_ISENABLER10_FLD_CLR_MSK 0x00000000
1914 #define ALT_GIC_DIST_GICD_ISENABLER10_FLD_RESET 0x0
1916 #define ALT_GIC_DIST_GICD_ISENABLER10_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1918 #define ALT_GIC_DIST_GICD_ISENABLER10_FLD_SET(value) (((value) << 0) & 0xffffffff)
1920 #ifndef __ASSEMBLY__
1932 struct ALT_GIC_DIST_GICD_ISENABLER10_s
1934 volatile uint32_t fld : 32;
1938 typedef struct ALT_GIC_DIST_GICD_ISENABLER10_s ALT_GIC_DIST_GICD_ISENABLER10_t;
1942 #define ALT_GIC_DIST_GICD_ISENABLER10_RESET 0x00000000
1944 #define ALT_GIC_DIST_GICD_ISENABLER10_OFST 0x128
1967 #define ALT_GIC_DIST_GICD_ISENABLER11_FLD_LSB 0
1969 #define ALT_GIC_DIST_GICD_ISENABLER11_FLD_MSB 31
1971 #define ALT_GIC_DIST_GICD_ISENABLER11_FLD_WIDTH 32
1973 #define ALT_GIC_DIST_GICD_ISENABLER11_FLD_SET_MSK 0xffffffff
1975 #define ALT_GIC_DIST_GICD_ISENABLER11_FLD_CLR_MSK 0x00000000
1977 #define ALT_GIC_DIST_GICD_ISENABLER11_FLD_RESET 0x0
1979 #define ALT_GIC_DIST_GICD_ISENABLER11_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1981 #define ALT_GIC_DIST_GICD_ISENABLER11_FLD_SET(value) (((value) << 0) & 0xffffffff)
1983 #ifndef __ASSEMBLY__
1995 struct ALT_GIC_DIST_GICD_ISENABLER11_s
1997 volatile uint32_t fld : 32;
2001 typedef struct ALT_GIC_DIST_GICD_ISENABLER11_s ALT_GIC_DIST_GICD_ISENABLER11_t;
2005 #define ALT_GIC_DIST_GICD_ISENABLER11_RESET 0x00000000
2007 #define ALT_GIC_DIST_GICD_ISENABLER11_OFST 0x12c
2030 #define ALT_GIC_DIST_GICD_ISENABLER12_FLD_LSB 0
2032 #define ALT_GIC_DIST_GICD_ISENABLER12_FLD_MSB 31
2034 #define ALT_GIC_DIST_GICD_ISENABLER12_FLD_WIDTH 32
2036 #define ALT_GIC_DIST_GICD_ISENABLER12_FLD_SET_MSK 0xffffffff
2038 #define ALT_GIC_DIST_GICD_ISENABLER12_FLD_CLR_MSK 0x00000000
2040 #define ALT_GIC_DIST_GICD_ISENABLER12_FLD_RESET 0x0
2042 #define ALT_GIC_DIST_GICD_ISENABLER12_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2044 #define ALT_GIC_DIST_GICD_ISENABLER12_FLD_SET(value) (((value) << 0) & 0xffffffff)
2046 #ifndef __ASSEMBLY__
2058 struct ALT_GIC_DIST_GICD_ISENABLER12_s
2060 volatile uint32_t fld : 32;
2064 typedef struct ALT_GIC_DIST_GICD_ISENABLER12_s ALT_GIC_DIST_GICD_ISENABLER12_t;
2068 #define ALT_GIC_DIST_GICD_ISENABLER12_RESET 0x00000000
2070 #define ALT_GIC_DIST_GICD_ISENABLER12_OFST 0x130
2093 #define ALT_GIC_DIST_GICD_ISENABLER13_FLD_LSB 0
2095 #define ALT_GIC_DIST_GICD_ISENABLER13_FLD_MSB 31
2097 #define ALT_GIC_DIST_GICD_ISENABLER13_FLD_WIDTH 32
2099 #define ALT_GIC_DIST_GICD_ISENABLER13_FLD_SET_MSK 0xffffffff
2101 #define ALT_GIC_DIST_GICD_ISENABLER13_FLD_CLR_MSK 0x00000000
2103 #define ALT_GIC_DIST_GICD_ISENABLER13_FLD_RESET 0x0
2105 #define ALT_GIC_DIST_GICD_ISENABLER13_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2107 #define ALT_GIC_DIST_GICD_ISENABLER13_FLD_SET(value) (((value) << 0) & 0xffffffff)
2109 #ifndef __ASSEMBLY__
2121 struct ALT_GIC_DIST_GICD_ISENABLER13_s
2123 volatile uint32_t fld : 32;
2127 typedef struct ALT_GIC_DIST_GICD_ISENABLER13_s ALT_GIC_DIST_GICD_ISENABLER13_t;
2131 #define ALT_GIC_DIST_GICD_ISENABLER13_RESET 0x00000000
2133 #define ALT_GIC_DIST_GICD_ISENABLER13_OFST 0x134
2156 #define ALT_GIC_DIST_GICD_ISENABLER14_FLD_LSB 0
2158 #define ALT_GIC_DIST_GICD_ISENABLER14_FLD_MSB 31
2160 #define ALT_GIC_DIST_GICD_ISENABLER14_FLD_WIDTH 32
2162 #define ALT_GIC_DIST_GICD_ISENABLER14_FLD_SET_MSK 0xffffffff
2164 #define ALT_GIC_DIST_GICD_ISENABLER14_FLD_CLR_MSK 0x00000000
2166 #define ALT_GIC_DIST_GICD_ISENABLER14_FLD_RESET 0x0
2168 #define ALT_GIC_DIST_GICD_ISENABLER14_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2170 #define ALT_GIC_DIST_GICD_ISENABLER14_FLD_SET(value) (((value) << 0) & 0xffffffff)
2172 #ifndef __ASSEMBLY__
2184 struct ALT_GIC_DIST_GICD_ISENABLER14_s
2186 volatile uint32_t fld : 32;
2190 typedef struct ALT_GIC_DIST_GICD_ISENABLER14_s ALT_GIC_DIST_GICD_ISENABLER14_t;
2194 #define ALT_GIC_DIST_GICD_ISENABLER14_RESET 0x00000000
2196 #define ALT_GIC_DIST_GICD_ISENABLER14_OFST 0x138
2219 #define ALT_GIC_DIST_GICD_ISENABLER15_FLD_LSB 0
2221 #define ALT_GIC_DIST_GICD_ISENABLER15_FLD_MSB 31
2223 #define ALT_GIC_DIST_GICD_ISENABLER15_FLD_WIDTH 32
2225 #define ALT_GIC_DIST_GICD_ISENABLER15_FLD_SET_MSK 0xffffffff
2227 #define ALT_GIC_DIST_GICD_ISENABLER15_FLD_CLR_MSK 0x00000000
2229 #define ALT_GIC_DIST_GICD_ISENABLER15_FLD_RESET 0x0
2231 #define ALT_GIC_DIST_GICD_ISENABLER15_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2233 #define ALT_GIC_DIST_GICD_ISENABLER15_FLD_SET(value) (((value) << 0) & 0xffffffff)
2235 #ifndef __ASSEMBLY__
2247 struct ALT_GIC_DIST_GICD_ISENABLER15_s
2249 volatile uint32_t fld : 32;
2253 typedef struct ALT_GIC_DIST_GICD_ISENABLER15_s ALT_GIC_DIST_GICD_ISENABLER15_t;
2257 #define ALT_GIC_DIST_GICD_ISENABLER15_RESET 0x00000000
2259 #define ALT_GIC_DIST_GICD_ISENABLER15_OFST 0x13c
2282 #define ALT_GIC_DIST_GICD_ICENABLER0_FLD_LSB 0
2284 #define ALT_GIC_DIST_GICD_ICENABLER0_FLD_MSB 31
2286 #define ALT_GIC_DIST_GICD_ICENABLER0_FLD_WIDTH 32
2288 #define ALT_GIC_DIST_GICD_ICENABLER0_FLD_SET_MSK 0xffffffff
2290 #define ALT_GIC_DIST_GICD_ICENABLER0_FLD_CLR_MSK 0x00000000
2292 #define ALT_GIC_DIST_GICD_ICENABLER0_FLD_RESET 0x0
2294 #define ALT_GIC_DIST_GICD_ICENABLER0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2296 #define ALT_GIC_DIST_GICD_ICENABLER0_FLD_SET(value) (((value) << 0) & 0xffffffff)
2298 #ifndef __ASSEMBLY__
2310 struct ALT_GIC_DIST_GICD_ICENABLER0_s
2312 volatile uint32_t fld : 32;
2316 typedef struct ALT_GIC_DIST_GICD_ICENABLER0_s ALT_GIC_DIST_GICD_ICENABLER0_t;
2320 #define ALT_GIC_DIST_GICD_ICENABLER0_RESET 0x0000ffff
2322 #define ALT_GIC_DIST_GICD_ICENABLER0_OFST 0x180
2345 #define ALT_GIC_DIST_GICD_ICENABLER1_FLD_LSB 0
2347 #define ALT_GIC_DIST_GICD_ICENABLER1_FLD_MSB 31
2349 #define ALT_GIC_DIST_GICD_ICENABLER1_FLD_WIDTH 32
2351 #define ALT_GIC_DIST_GICD_ICENABLER1_FLD_SET_MSK 0xffffffff
2353 #define ALT_GIC_DIST_GICD_ICENABLER1_FLD_CLR_MSK 0x00000000
2355 #define ALT_GIC_DIST_GICD_ICENABLER1_FLD_RESET 0x0
2357 #define ALT_GIC_DIST_GICD_ICENABLER1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2359 #define ALT_GIC_DIST_GICD_ICENABLER1_FLD_SET(value) (((value) << 0) & 0xffffffff)
2361 #ifndef __ASSEMBLY__
2373 struct ALT_GIC_DIST_GICD_ICENABLER1_s
2375 volatile uint32_t fld : 32;
2379 typedef struct ALT_GIC_DIST_GICD_ICENABLER1_s ALT_GIC_DIST_GICD_ICENABLER1_t;
2383 #define ALT_GIC_DIST_GICD_ICENABLER1_RESET 0x00000000
2385 #define ALT_GIC_DIST_GICD_ICENABLER1_OFST 0x184
2408 #define ALT_GIC_DIST_GICD_ICENABLER2_FLD_LSB 0
2410 #define ALT_GIC_DIST_GICD_ICENABLER2_FLD_MSB 31
2412 #define ALT_GIC_DIST_GICD_ICENABLER2_FLD_WIDTH 32
2414 #define ALT_GIC_DIST_GICD_ICENABLER2_FLD_SET_MSK 0xffffffff
2416 #define ALT_GIC_DIST_GICD_ICENABLER2_FLD_CLR_MSK 0x00000000
2418 #define ALT_GIC_DIST_GICD_ICENABLER2_FLD_RESET 0x0
2420 #define ALT_GIC_DIST_GICD_ICENABLER2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2422 #define ALT_GIC_DIST_GICD_ICENABLER2_FLD_SET(value) (((value) << 0) & 0xffffffff)
2424 #ifndef __ASSEMBLY__
2436 struct ALT_GIC_DIST_GICD_ICENABLER2_s
2438 volatile uint32_t fld : 32;
2442 typedef struct ALT_GIC_DIST_GICD_ICENABLER2_s ALT_GIC_DIST_GICD_ICENABLER2_t;
2446 #define ALT_GIC_DIST_GICD_ICENABLER2_RESET 0x00000000
2448 #define ALT_GIC_DIST_GICD_ICENABLER2_OFST 0x188
2471 #define ALT_GIC_DIST_GICD_ICENABLER3_FLD_LSB 0
2473 #define ALT_GIC_DIST_GICD_ICENABLER3_FLD_MSB 31
2475 #define ALT_GIC_DIST_GICD_ICENABLER3_FLD_WIDTH 32
2477 #define ALT_GIC_DIST_GICD_ICENABLER3_FLD_SET_MSK 0xffffffff
2479 #define ALT_GIC_DIST_GICD_ICENABLER3_FLD_CLR_MSK 0x00000000
2481 #define ALT_GIC_DIST_GICD_ICENABLER3_FLD_RESET 0x0
2483 #define ALT_GIC_DIST_GICD_ICENABLER3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2485 #define ALT_GIC_DIST_GICD_ICENABLER3_FLD_SET(value) (((value) << 0) & 0xffffffff)
2487 #ifndef __ASSEMBLY__
2499 struct ALT_GIC_DIST_GICD_ICENABLER3_s
2501 volatile uint32_t fld : 32;
2505 typedef struct ALT_GIC_DIST_GICD_ICENABLER3_s ALT_GIC_DIST_GICD_ICENABLER3_t;
2509 #define ALT_GIC_DIST_GICD_ICENABLER3_RESET 0x00000000
2511 #define ALT_GIC_DIST_GICD_ICENABLER3_OFST 0x18c
2534 #define ALT_GIC_DIST_GICD_ICENABLER4_FLD_LSB 0
2536 #define ALT_GIC_DIST_GICD_ICENABLER4_FLD_MSB 31
2538 #define ALT_GIC_DIST_GICD_ICENABLER4_FLD_WIDTH 32
2540 #define ALT_GIC_DIST_GICD_ICENABLER4_FLD_SET_MSK 0xffffffff
2542 #define ALT_GIC_DIST_GICD_ICENABLER4_FLD_CLR_MSK 0x00000000
2544 #define ALT_GIC_DIST_GICD_ICENABLER4_FLD_RESET 0x0
2546 #define ALT_GIC_DIST_GICD_ICENABLER4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2548 #define ALT_GIC_DIST_GICD_ICENABLER4_FLD_SET(value) (((value) << 0) & 0xffffffff)
2550 #ifndef __ASSEMBLY__
2562 struct ALT_GIC_DIST_GICD_ICENABLER4_s
2564 volatile uint32_t fld : 32;
2568 typedef struct ALT_GIC_DIST_GICD_ICENABLER4_s ALT_GIC_DIST_GICD_ICENABLER4_t;
2572 #define ALT_GIC_DIST_GICD_ICENABLER4_RESET 0x00000000
2574 #define ALT_GIC_DIST_GICD_ICENABLER4_OFST 0x190
2597 #define ALT_GIC_DIST_GICD_ICENABLER5_FLD_LSB 0
2599 #define ALT_GIC_DIST_GICD_ICENABLER5_FLD_MSB 31
2601 #define ALT_GIC_DIST_GICD_ICENABLER5_FLD_WIDTH 32
2603 #define ALT_GIC_DIST_GICD_ICENABLER5_FLD_SET_MSK 0xffffffff
2605 #define ALT_GIC_DIST_GICD_ICENABLER5_FLD_CLR_MSK 0x00000000
2607 #define ALT_GIC_DIST_GICD_ICENABLER5_FLD_RESET 0x0
2609 #define ALT_GIC_DIST_GICD_ICENABLER5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2611 #define ALT_GIC_DIST_GICD_ICENABLER5_FLD_SET(value) (((value) << 0) & 0xffffffff)
2613 #ifndef __ASSEMBLY__
2625 struct ALT_GIC_DIST_GICD_ICENABLER5_s
2627 volatile uint32_t fld : 32;
2631 typedef struct ALT_GIC_DIST_GICD_ICENABLER5_s ALT_GIC_DIST_GICD_ICENABLER5_t;
2635 #define ALT_GIC_DIST_GICD_ICENABLER5_RESET 0x00000000
2637 #define ALT_GIC_DIST_GICD_ICENABLER5_OFST 0x194
2660 #define ALT_GIC_DIST_GICD_ICENABLER6_FLD_LSB 0
2662 #define ALT_GIC_DIST_GICD_ICENABLER6_FLD_MSB 31
2664 #define ALT_GIC_DIST_GICD_ICENABLER6_FLD_WIDTH 32
2666 #define ALT_GIC_DIST_GICD_ICENABLER6_FLD_SET_MSK 0xffffffff
2668 #define ALT_GIC_DIST_GICD_ICENABLER6_FLD_CLR_MSK 0x00000000
2670 #define ALT_GIC_DIST_GICD_ICENABLER6_FLD_RESET 0x0
2672 #define ALT_GIC_DIST_GICD_ICENABLER6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2674 #define ALT_GIC_DIST_GICD_ICENABLER6_FLD_SET(value) (((value) << 0) & 0xffffffff)
2676 #ifndef __ASSEMBLY__
2688 struct ALT_GIC_DIST_GICD_ICENABLER6_s
2690 volatile uint32_t fld : 32;
2694 typedef struct ALT_GIC_DIST_GICD_ICENABLER6_s ALT_GIC_DIST_GICD_ICENABLER6_t;
2698 #define ALT_GIC_DIST_GICD_ICENABLER6_RESET 0x00000000
2700 #define ALT_GIC_DIST_GICD_ICENABLER6_OFST 0x198
2723 #define ALT_GIC_DIST_GICD_ICENABLER7_FLD_LSB 0
2725 #define ALT_GIC_DIST_GICD_ICENABLER7_FLD_MSB 31
2727 #define ALT_GIC_DIST_GICD_ICENABLER7_FLD_WIDTH 32
2729 #define ALT_GIC_DIST_GICD_ICENABLER7_FLD_SET_MSK 0xffffffff
2731 #define ALT_GIC_DIST_GICD_ICENABLER7_FLD_CLR_MSK 0x00000000
2733 #define ALT_GIC_DIST_GICD_ICENABLER7_FLD_RESET 0x0
2735 #define ALT_GIC_DIST_GICD_ICENABLER7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2737 #define ALT_GIC_DIST_GICD_ICENABLER7_FLD_SET(value) (((value) << 0) & 0xffffffff)
2739 #ifndef __ASSEMBLY__
2751 struct ALT_GIC_DIST_GICD_ICENABLER7_s
2753 volatile uint32_t fld : 32;
2757 typedef struct ALT_GIC_DIST_GICD_ICENABLER7_s ALT_GIC_DIST_GICD_ICENABLER7_t;
2761 #define ALT_GIC_DIST_GICD_ICENABLER7_RESET 0x00000000
2763 #define ALT_GIC_DIST_GICD_ICENABLER7_OFST 0x19c
2786 #define ALT_GIC_DIST_GICD_ICENABLER8_FLD_LSB 0
2788 #define ALT_GIC_DIST_GICD_ICENABLER8_FLD_MSB 31
2790 #define ALT_GIC_DIST_GICD_ICENABLER8_FLD_WIDTH 32
2792 #define ALT_GIC_DIST_GICD_ICENABLER8_FLD_SET_MSK 0xffffffff
2794 #define ALT_GIC_DIST_GICD_ICENABLER8_FLD_CLR_MSK 0x00000000
2796 #define ALT_GIC_DIST_GICD_ICENABLER8_FLD_RESET 0x0
2798 #define ALT_GIC_DIST_GICD_ICENABLER8_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2800 #define ALT_GIC_DIST_GICD_ICENABLER8_FLD_SET(value) (((value) << 0) & 0xffffffff)
2802 #ifndef __ASSEMBLY__
2814 struct ALT_GIC_DIST_GICD_ICENABLER8_s
2816 volatile uint32_t fld : 32;
2820 typedef struct ALT_GIC_DIST_GICD_ICENABLER8_s ALT_GIC_DIST_GICD_ICENABLER8_t;
2824 #define ALT_GIC_DIST_GICD_ICENABLER8_RESET 0x00000000
2826 #define ALT_GIC_DIST_GICD_ICENABLER8_OFST 0x1a0
2849 #define ALT_GIC_DIST_GICD_ICENABLER9_FLD_LSB 0
2851 #define ALT_GIC_DIST_GICD_ICENABLER9_FLD_MSB 31
2853 #define ALT_GIC_DIST_GICD_ICENABLER9_FLD_WIDTH 32
2855 #define ALT_GIC_DIST_GICD_ICENABLER9_FLD_SET_MSK 0xffffffff
2857 #define ALT_GIC_DIST_GICD_ICENABLER9_FLD_CLR_MSK 0x00000000
2859 #define ALT_GIC_DIST_GICD_ICENABLER9_FLD_RESET 0x0
2861 #define ALT_GIC_DIST_GICD_ICENABLER9_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2863 #define ALT_GIC_DIST_GICD_ICENABLER9_FLD_SET(value) (((value) << 0) & 0xffffffff)
2865 #ifndef __ASSEMBLY__
2877 struct ALT_GIC_DIST_GICD_ICENABLER9_s
2879 volatile uint32_t fld : 32;
2883 typedef struct ALT_GIC_DIST_GICD_ICENABLER9_s ALT_GIC_DIST_GICD_ICENABLER9_t;
2887 #define ALT_GIC_DIST_GICD_ICENABLER9_RESET 0x00000000
2889 #define ALT_GIC_DIST_GICD_ICENABLER9_OFST 0x1a4
2912 #define ALT_GIC_DIST_GICD_ICENABLER10_FLD_LSB 0
2914 #define ALT_GIC_DIST_GICD_ICENABLER10_FLD_MSB 31
2916 #define ALT_GIC_DIST_GICD_ICENABLER10_FLD_WIDTH 32
2918 #define ALT_GIC_DIST_GICD_ICENABLER10_FLD_SET_MSK 0xffffffff
2920 #define ALT_GIC_DIST_GICD_ICENABLER10_FLD_CLR_MSK 0x00000000
2922 #define ALT_GIC_DIST_GICD_ICENABLER10_FLD_RESET 0x0
2924 #define ALT_GIC_DIST_GICD_ICENABLER10_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2926 #define ALT_GIC_DIST_GICD_ICENABLER10_FLD_SET(value) (((value) << 0) & 0xffffffff)
2928 #ifndef __ASSEMBLY__
2940 struct ALT_GIC_DIST_GICD_ICENABLER10_s
2942 volatile uint32_t fld : 32;
2946 typedef struct ALT_GIC_DIST_GICD_ICENABLER10_s ALT_GIC_DIST_GICD_ICENABLER10_t;
2950 #define ALT_GIC_DIST_GICD_ICENABLER10_RESET 0x00000000
2952 #define ALT_GIC_DIST_GICD_ICENABLER10_OFST 0x1a8
2975 #define ALT_GIC_DIST_GICD_ICENABLER11_FLD_LSB 0
2977 #define ALT_GIC_DIST_GICD_ICENABLER11_FLD_MSB 31
2979 #define ALT_GIC_DIST_GICD_ICENABLER11_FLD_WIDTH 32
2981 #define ALT_GIC_DIST_GICD_ICENABLER11_FLD_SET_MSK 0xffffffff
2983 #define ALT_GIC_DIST_GICD_ICENABLER11_FLD_CLR_MSK 0x00000000
2985 #define ALT_GIC_DIST_GICD_ICENABLER11_FLD_RESET 0x0
2987 #define ALT_GIC_DIST_GICD_ICENABLER11_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2989 #define ALT_GIC_DIST_GICD_ICENABLER11_FLD_SET(value) (((value) << 0) & 0xffffffff)
2991 #ifndef __ASSEMBLY__
3003 struct ALT_GIC_DIST_GICD_ICENABLER11_s
3005 volatile uint32_t fld : 32;
3009 typedef struct ALT_GIC_DIST_GICD_ICENABLER11_s ALT_GIC_DIST_GICD_ICENABLER11_t;
3013 #define ALT_GIC_DIST_GICD_ICENABLER11_RESET 0x00000000
3015 #define ALT_GIC_DIST_GICD_ICENABLER11_OFST 0x1ac
3038 #define ALT_GIC_DIST_GICD_ICENABLER12_FLD_LSB 0
3040 #define ALT_GIC_DIST_GICD_ICENABLER12_FLD_MSB 31
3042 #define ALT_GIC_DIST_GICD_ICENABLER12_FLD_WIDTH 32
3044 #define ALT_GIC_DIST_GICD_ICENABLER12_FLD_SET_MSK 0xffffffff
3046 #define ALT_GIC_DIST_GICD_ICENABLER12_FLD_CLR_MSK 0x00000000
3048 #define ALT_GIC_DIST_GICD_ICENABLER12_FLD_RESET 0x0
3050 #define ALT_GIC_DIST_GICD_ICENABLER12_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3052 #define ALT_GIC_DIST_GICD_ICENABLER12_FLD_SET(value) (((value) << 0) & 0xffffffff)
3054 #ifndef __ASSEMBLY__
3066 struct ALT_GIC_DIST_GICD_ICENABLER12_s
3068 volatile uint32_t fld : 32;
3072 typedef struct ALT_GIC_DIST_GICD_ICENABLER12_s ALT_GIC_DIST_GICD_ICENABLER12_t;
3076 #define ALT_GIC_DIST_GICD_ICENABLER12_RESET 0x00000000
3078 #define ALT_GIC_DIST_GICD_ICENABLER12_OFST 0x1b0
3101 #define ALT_GIC_DIST_GICD_ICENABLER13_FLD_LSB 0
3103 #define ALT_GIC_DIST_GICD_ICENABLER13_FLD_MSB 31
3105 #define ALT_GIC_DIST_GICD_ICENABLER13_FLD_WIDTH 32
3107 #define ALT_GIC_DIST_GICD_ICENABLER13_FLD_SET_MSK 0xffffffff
3109 #define ALT_GIC_DIST_GICD_ICENABLER13_FLD_CLR_MSK 0x00000000
3111 #define ALT_GIC_DIST_GICD_ICENABLER13_FLD_RESET 0x0
3113 #define ALT_GIC_DIST_GICD_ICENABLER13_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3115 #define ALT_GIC_DIST_GICD_ICENABLER13_FLD_SET(value) (((value) << 0) & 0xffffffff)
3117 #ifndef __ASSEMBLY__
3129 struct ALT_GIC_DIST_GICD_ICENABLER13_s
3131 volatile uint32_t fld : 32;
3135 typedef struct ALT_GIC_DIST_GICD_ICENABLER13_s ALT_GIC_DIST_GICD_ICENABLER13_t;
3139 #define ALT_GIC_DIST_GICD_ICENABLER13_RESET 0x00000000
3141 #define ALT_GIC_DIST_GICD_ICENABLER13_OFST 0x1b4
3164 #define ALT_GIC_DIST_GICD_ICENABLER14_FLD_LSB 0
3166 #define ALT_GIC_DIST_GICD_ICENABLER14_FLD_MSB 31
3168 #define ALT_GIC_DIST_GICD_ICENABLER14_FLD_WIDTH 32
3170 #define ALT_GIC_DIST_GICD_ICENABLER14_FLD_SET_MSK 0xffffffff
3172 #define ALT_GIC_DIST_GICD_ICENABLER14_FLD_CLR_MSK 0x00000000
3174 #define ALT_GIC_DIST_GICD_ICENABLER14_FLD_RESET 0x0
3176 #define ALT_GIC_DIST_GICD_ICENABLER14_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3178 #define ALT_GIC_DIST_GICD_ICENABLER14_FLD_SET(value) (((value) << 0) & 0xffffffff)
3180 #ifndef __ASSEMBLY__
3192 struct ALT_GIC_DIST_GICD_ICENABLER14_s
3194 volatile uint32_t fld : 32;
3198 typedef struct ALT_GIC_DIST_GICD_ICENABLER14_s ALT_GIC_DIST_GICD_ICENABLER14_t;
3202 #define ALT_GIC_DIST_GICD_ICENABLER14_RESET 0x00000000
3204 #define ALT_GIC_DIST_GICD_ICENABLER14_OFST 0x1b8
3227 #define ALT_GIC_DIST_GICD_ICENABLER15_FLD_LSB 0
3229 #define ALT_GIC_DIST_GICD_ICENABLER15_FLD_MSB 31
3231 #define ALT_GIC_DIST_GICD_ICENABLER15_FLD_WIDTH 32
3233 #define ALT_GIC_DIST_GICD_ICENABLER15_FLD_SET_MSK 0xffffffff
3235 #define ALT_GIC_DIST_GICD_ICENABLER15_FLD_CLR_MSK 0x00000000
3237 #define ALT_GIC_DIST_GICD_ICENABLER15_FLD_RESET 0x0
3239 #define ALT_GIC_DIST_GICD_ICENABLER15_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3241 #define ALT_GIC_DIST_GICD_ICENABLER15_FLD_SET(value) (((value) << 0) & 0xffffffff)
3243 #ifndef __ASSEMBLY__
3255 struct ALT_GIC_DIST_GICD_ICENABLER15_s
3257 volatile uint32_t fld : 32;
3261 typedef struct ALT_GIC_DIST_GICD_ICENABLER15_s ALT_GIC_DIST_GICD_ICENABLER15_t;
3265 #define ALT_GIC_DIST_GICD_ICENABLER15_RESET 0x00000000
3267 #define ALT_GIC_DIST_GICD_ICENABLER15_OFST 0x1bc
3290 #define ALT_GIC_DIST_GICD_ISPENDR0_FLD_LSB 0
3292 #define ALT_GIC_DIST_GICD_ISPENDR0_FLD_MSB 31
3294 #define ALT_GIC_DIST_GICD_ISPENDR0_FLD_WIDTH 32
3296 #define ALT_GIC_DIST_GICD_ISPENDR0_FLD_SET_MSK 0xffffffff
3298 #define ALT_GIC_DIST_GICD_ISPENDR0_FLD_CLR_MSK 0x00000000
3300 #define ALT_GIC_DIST_GICD_ISPENDR0_FLD_RESET 0x0
3302 #define ALT_GIC_DIST_GICD_ISPENDR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3304 #define ALT_GIC_DIST_GICD_ISPENDR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
3306 #ifndef __ASSEMBLY__
3318 struct ALT_GIC_DIST_GICD_ISPENDR0_s
3320 volatile uint32_t fld : 32;
3324 typedef struct ALT_GIC_DIST_GICD_ISPENDR0_s ALT_GIC_DIST_GICD_ISPENDR0_t;
3328 #define ALT_GIC_DIST_GICD_ISPENDR0_RESET 0x00000000
3330 #define ALT_GIC_DIST_GICD_ISPENDR0_OFST 0x200
3353 #define ALT_GIC_DIST_GICD_ISPENDR1_FLD_LSB 0
3355 #define ALT_GIC_DIST_GICD_ISPENDR1_FLD_MSB 31
3357 #define ALT_GIC_DIST_GICD_ISPENDR1_FLD_WIDTH 32
3359 #define ALT_GIC_DIST_GICD_ISPENDR1_FLD_SET_MSK 0xffffffff
3361 #define ALT_GIC_DIST_GICD_ISPENDR1_FLD_CLR_MSK 0x00000000
3363 #define ALT_GIC_DIST_GICD_ISPENDR1_FLD_RESET 0x0
3365 #define ALT_GIC_DIST_GICD_ISPENDR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3367 #define ALT_GIC_DIST_GICD_ISPENDR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
3369 #ifndef __ASSEMBLY__
3381 struct ALT_GIC_DIST_GICD_ISPENDR1_s
3383 volatile uint32_t fld : 32;
3387 typedef struct ALT_GIC_DIST_GICD_ISPENDR1_s ALT_GIC_DIST_GICD_ISPENDR1_t;
3391 #define ALT_GIC_DIST_GICD_ISPENDR1_RESET 0x00000000
3393 #define ALT_GIC_DIST_GICD_ISPENDR1_OFST 0x204
3416 #define ALT_GIC_DIST_GICD_ISPENDR2_FLD_LSB 0
3418 #define ALT_GIC_DIST_GICD_ISPENDR2_FLD_MSB 31
3420 #define ALT_GIC_DIST_GICD_ISPENDR2_FLD_WIDTH 32
3422 #define ALT_GIC_DIST_GICD_ISPENDR2_FLD_SET_MSK 0xffffffff
3424 #define ALT_GIC_DIST_GICD_ISPENDR2_FLD_CLR_MSK 0x00000000
3426 #define ALT_GIC_DIST_GICD_ISPENDR2_FLD_RESET 0x0
3428 #define ALT_GIC_DIST_GICD_ISPENDR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3430 #define ALT_GIC_DIST_GICD_ISPENDR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
3432 #ifndef __ASSEMBLY__
3444 struct ALT_GIC_DIST_GICD_ISPENDR2_s
3446 volatile uint32_t fld : 32;
3450 typedef struct ALT_GIC_DIST_GICD_ISPENDR2_s ALT_GIC_DIST_GICD_ISPENDR2_t;
3454 #define ALT_GIC_DIST_GICD_ISPENDR2_RESET 0x00000000
3456 #define ALT_GIC_DIST_GICD_ISPENDR2_OFST 0x208
3479 #define ALT_GIC_DIST_GICD_ISPENDR3_FLD_LSB 0
3481 #define ALT_GIC_DIST_GICD_ISPENDR3_FLD_MSB 31
3483 #define ALT_GIC_DIST_GICD_ISPENDR3_FLD_WIDTH 32
3485 #define ALT_GIC_DIST_GICD_ISPENDR3_FLD_SET_MSK 0xffffffff
3487 #define ALT_GIC_DIST_GICD_ISPENDR3_FLD_CLR_MSK 0x00000000
3489 #define ALT_GIC_DIST_GICD_ISPENDR3_FLD_RESET 0x0
3491 #define ALT_GIC_DIST_GICD_ISPENDR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3493 #define ALT_GIC_DIST_GICD_ISPENDR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
3495 #ifndef __ASSEMBLY__
3507 struct ALT_GIC_DIST_GICD_ISPENDR3_s
3509 volatile uint32_t fld : 32;
3513 typedef struct ALT_GIC_DIST_GICD_ISPENDR3_s ALT_GIC_DIST_GICD_ISPENDR3_t;
3517 #define ALT_GIC_DIST_GICD_ISPENDR3_RESET 0x00000000
3519 #define ALT_GIC_DIST_GICD_ISPENDR3_OFST 0x20c
3542 #define ALT_GIC_DIST_GICD_ISPENDR4_FLD_LSB 0
3544 #define ALT_GIC_DIST_GICD_ISPENDR4_FLD_MSB 31
3546 #define ALT_GIC_DIST_GICD_ISPENDR4_FLD_WIDTH 32
3548 #define ALT_GIC_DIST_GICD_ISPENDR4_FLD_SET_MSK 0xffffffff
3550 #define ALT_GIC_DIST_GICD_ISPENDR4_FLD_CLR_MSK 0x00000000
3552 #define ALT_GIC_DIST_GICD_ISPENDR4_FLD_RESET 0x0
3554 #define ALT_GIC_DIST_GICD_ISPENDR4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3556 #define ALT_GIC_DIST_GICD_ISPENDR4_FLD_SET(value) (((value) << 0) & 0xffffffff)
3558 #ifndef __ASSEMBLY__
3570 struct ALT_GIC_DIST_GICD_ISPENDR4_s
3572 volatile uint32_t fld : 32;
3576 typedef struct ALT_GIC_DIST_GICD_ISPENDR4_s ALT_GIC_DIST_GICD_ISPENDR4_t;
3580 #define ALT_GIC_DIST_GICD_ISPENDR4_RESET 0x00000000
3582 #define ALT_GIC_DIST_GICD_ISPENDR4_OFST 0x210
3605 #define ALT_GIC_DIST_GICD_ISPENDR5_FLD_LSB 0
3607 #define ALT_GIC_DIST_GICD_ISPENDR5_FLD_MSB 31
3609 #define ALT_GIC_DIST_GICD_ISPENDR5_FLD_WIDTH 32
3611 #define ALT_GIC_DIST_GICD_ISPENDR5_FLD_SET_MSK 0xffffffff
3613 #define ALT_GIC_DIST_GICD_ISPENDR5_FLD_CLR_MSK 0x00000000
3615 #define ALT_GIC_DIST_GICD_ISPENDR5_FLD_RESET 0x0
3617 #define ALT_GIC_DIST_GICD_ISPENDR5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3619 #define ALT_GIC_DIST_GICD_ISPENDR5_FLD_SET(value) (((value) << 0) & 0xffffffff)
3621 #ifndef __ASSEMBLY__
3633 struct ALT_GIC_DIST_GICD_ISPENDR5_s
3635 volatile uint32_t fld : 32;
3639 typedef struct ALT_GIC_DIST_GICD_ISPENDR5_s ALT_GIC_DIST_GICD_ISPENDR5_t;
3643 #define ALT_GIC_DIST_GICD_ISPENDR5_RESET 0x00000000
3645 #define ALT_GIC_DIST_GICD_ISPENDR5_OFST 0x214
3668 #define ALT_GIC_DIST_GICD_ISPENDR6_FLD_LSB 0
3670 #define ALT_GIC_DIST_GICD_ISPENDR6_FLD_MSB 31
3672 #define ALT_GIC_DIST_GICD_ISPENDR6_FLD_WIDTH 32
3674 #define ALT_GIC_DIST_GICD_ISPENDR6_FLD_SET_MSK 0xffffffff
3676 #define ALT_GIC_DIST_GICD_ISPENDR6_FLD_CLR_MSK 0x00000000
3678 #define ALT_GIC_DIST_GICD_ISPENDR6_FLD_RESET 0x0
3680 #define ALT_GIC_DIST_GICD_ISPENDR6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3682 #define ALT_GIC_DIST_GICD_ISPENDR6_FLD_SET(value) (((value) << 0) & 0xffffffff)
3684 #ifndef __ASSEMBLY__
3696 struct ALT_GIC_DIST_GICD_ISPENDR6_s
3698 volatile uint32_t fld : 32;
3702 typedef struct ALT_GIC_DIST_GICD_ISPENDR6_s ALT_GIC_DIST_GICD_ISPENDR6_t;
3706 #define ALT_GIC_DIST_GICD_ISPENDR6_RESET 0x00000000
3708 #define ALT_GIC_DIST_GICD_ISPENDR6_OFST 0x218
3731 #define ALT_GIC_DIST_GICD_ISPENDR7_FLD_LSB 0
3733 #define ALT_GIC_DIST_GICD_ISPENDR7_FLD_MSB 31
3735 #define ALT_GIC_DIST_GICD_ISPENDR7_FLD_WIDTH 32
3737 #define ALT_GIC_DIST_GICD_ISPENDR7_FLD_SET_MSK 0xffffffff
3739 #define ALT_GIC_DIST_GICD_ISPENDR7_FLD_CLR_MSK 0x00000000
3741 #define ALT_GIC_DIST_GICD_ISPENDR7_FLD_RESET 0x0
3743 #define ALT_GIC_DIST_GICD_ISPENDR7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3745 #define ALT_GIC_DIST_GICD_ISPENDR7_FLD_SET(value) (((value) << 0) & 0xffffffff)
3747 #ifndef __ASSEMBLY__
3759 struct ALT_GIC_DIST_GICD_ISPENDR7_s
3761 volatile uint32_t fld : 32;
3765 typedef struct ALT_GIC_DIST_GICD_ISPENDR7_s ALT_GIC_DIST_GICD_ISPENDR7_t;
3769 #define ALT_GIC_DIST_GICD_ISPENDR7_RESET 0x00000000
3771 #define ALT_GIC_DIST_GICD_ISPENDR7_OFST 0x21c
3794 #define ALT_GIC_DIST_GICD_ISPENDR8_FLD_LSB 0
3796 #define ALT_GIC_DIST_GICD_ISPENDR8_FLD_MSB 31
3798 #define ALT_GIC_DIST_GICD_ISPENDR8_FLD_WIDTH 32
3800 #define ALT_GIC_DIST_GICD_ISPENDR8_FLD_SET_MSK 0xffffffff
3802 #define ALT_GIC_DIST_GICD_ISPENDR8_FLD_CLR_MSK 0x00000000
3804 #define ALT_GIC_DIST_GICD_ISPENDR8_FLD_RESET 0x0
3806 #define ALT_GIC_DIST_GICD_ISPENDR8_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3808 #define ALT_GIC_DIST_GICD_ISPENDR8_FLD_SET(value) (((value) << 0) & 0xffffffff)
3810 #ifndef __ASSEMBLY__
3822 struct ALT_GIC_DIST_GICD_ISPENDR8_s
3824 volatile uint32_t fld : 32;
3828 typedef struct ALT_GIC_DIST_GICD_ISPENDR8_s ALT_GIC_DIST_GICD_ISPENDR8_t;
3832 #define ALT_GIC_DIST_GICD_ISPENDR8_RESET 0x00000000
3834 #define ALT_GIC_DIST_GICD_ISPENDR8_OFST 0x220
3857 #define ALT_GIC_DIST_GICD_ISPENDR9_FLD_LSB 0
3859 #define ALT_GIC_DIST_GICD_ISPENDR9_FLD_MSB 31
3861 #define ALT_GIC_DIST_GICD_ISPENDR9_FLD_WIDTH 32
3863 #define ALT_GIC_DIST_GICD_ISPENDR9_FLD_SET_MSK 0xffffffff
3865 #define ALT_GIC_DIST_GICD_ISPENDR9_FLD_CLR_MSK 0x00000000
3867 #define ALT_GIC_DIST_GICD_ISPENDR9_FLD_RESET 0x0
3869 #define ALT_GIC_DIST_GICD_ISPENDR9_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3871 #define ALT_GIC_DIST_GICD_ISPENDR9_FLD_SET(value) (((value) << 0) & 0xffffffff)
3873 #ifndef __ASSEMBLY__
3885 struct ALT_GIC_DIST_GICD_ISPENDR9_s
3887 volatile uint32_t fld : 32;
3891 typedef struct ALT_GIC_DIST_GICD_ISPENDR9_s ALT_GIC_DIST_GICD_ISPENDR9_t;
3895 #define ALT_GIC_DIST_GICD_ISPENDR9_RESET 0x00000000
3897 #define ALT_GIC_DIST_GICD_ISPENDR9_OFST 0x224
3920 #define ALT_GIC_DIST_GICD_ISPENDR10_FLD_LSB 0
3922 #define ALT_GIC_DIST_GICD_ISPENDR10_FLD_MSB 31
3924 #define ALT_GIC_DIST_GICD_ISPENDR10_FLD_WIDTH 32
3926 #define ALT_GIC_DIST_GICD_ISPENDR10_FLD_SET_MSK 0xffffffff
3928 #define ALT_GIC_DIST_GICD_ISPENDR10_FLD_CLR_MSK 0x00000000
3930 #define ALT_GIC_DIST_GICD_ISPENDR10_FLD_RESET 0x0
3932 #define ALT_GIC_DIST_GICD_ISPENDR10_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3934 #define ALT_GIC_DIST_GICD_ISPENDR10_FLD_SET(value) (((value) << 0) & 0xffffffff)
3936 #ifndef __ASSEMBLY__
3948 struct ALT_GIC_DIST_GICD_ISPENDR10_s
3950 volatile uint32_t fld : 32;
3954 typedef struct ALT_GIC_DIST_GICD_ISPENDR10_s ALT_GIC_DIST_GICD_ISPENDR10_t;
3958 #define ALT_GIC_DIST_GICD_ISPENDR10_RESET 0x00000000
3960 #define ALT_GIC_DIST_GICD_ISPENDR10_OFST 0x228
3983 #define ALT_GIC_DIST_GICD_ISPENDR11_FLD_LSB 0
3985 #define ALT_GIC_DIST_GICD_ISPENDR11_FLD_MSB 31
3987 #define ALT_GIC_DIST_GICD_ISPENDR11_FLD_WIDTH 32
3989 #define ALT_GIC_DIST_GICD_ISPENDR11_FLD_SET_MSK 0xffffffff
3991 #define ALT_GIC_DIST_GICD_ISPENDR11_FLD_CLR_MSK 0x00000000
3993 #define ALT_GIC_DIST_GICD_ISPENDR11_FLD_RESET 0x0
3995 #define ALT_GIC_DIST_GICD_ISPENDR11_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3997 #define ALT_GIC_DIST_GICD_ISPENDR11_FLD_SET(value) (((value) << 0) & 0xffffffff)
3999 #ifndef __ASSEMBLY__
4011 struct ALT_GIC_DIST_GICD_ISPENDR11_s
4013 volatile uint32_t fld : 32;
4017 typedef struct ALT_GIC_DIST_GICD_ISPENDR11_s ALT_GIC_DIST_GICD_ISPENDR11_t;
4021 #define ALT_GIC_DIST_GICD_ISPENDR11_RESET 0x00000000
4023 #define ALT_GIC_DIST_GICD_ISPENDR11_OFST 0x22c
4046 #define ALT_GIC_DIST_GICD_ISPENDR12_FLD_LSB 0
4048 #define ALT_GIC_DIST_GICD_ISPENDR12_FLD_MSB 31
4050 #define ALT_GIC_DIST_GICD_ISPENDR12_FLD_WIDTH 32
4052 #define ALT_GIC_DIST_GICD_ISPENDR12_FLD_SET_MSK 0xffffffff
4054 #define ALT_GIC_DIST_GICD_ISPENDR12_FLD_CLR_MSK 0x00000000
4056 #define ALT_GIC_DIST_GICD_ISPENDR12_FLD_RESET 0x0
4058 #define ALT_GIC_DIST_GICD_ISPENDR12_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4060 #define ALT_GIC_DIST_GICD_ISPENDR12_FLD_SET(value) (((value) << 0) & 0xffffffff)
4062 #ifndef __ASSEMBLY__
4074 struct ALT_GIC_DIST_GICD_ISPENDR12_s
4076 volatile uint32_t fld : 32;
4080 typedef struct ALT_GIC_DIST_GICD_ISPENDR12_s ALT_GIC_DIST_GICD_ISPENDR12_t;
4084 #define ALT_GIC_DIST_GICD_ISPENDR12_RESET 0x00000000
4086 #define ALT_GIC_DIST_GICD_ISPENDR12_OFST 0x230
4109 #define ALT_GIC_DIST_GICD_ISPENDR13_FLD_LSB 0
4111 #define ALT_GIC_DIST_GICD_ISPENDR13_FLD_MSB 31
4113 #define ALT_GIC_DIST_GICD_ISPENDR13_FLD_WIDTH 32
4115 #define ALT_GIC_DIST_GICD_ISPENDR13_FLD_SET_MSK 0xffffffff
4117 #define ALT_GIC_DIST_GICD_ISPENDR13_FLD_CLR_MSK 0x00000000
4119 #define ALT_GIC_DIST_GICD_ISPENDR13_FLD_RESET 0x0
4121 #define ALT_GIC_DIST_GICD_ISPENDR13_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4123 #define ALT_GIC_DIST_GICD_ISPENDR13_FLD_SET(value) (((value) << 0) & 0xffffffff)
4125 #ifndef __ASSEMBLY__
4137 struct ALT_GIC_DIST_GICD_ISPENDR13_s
4139 volatile uint32_t fld : 32;
4143 typedef struct ALT_GIC_DIST_GICD_ISPENDR13_s ALT_GIC_DIST_GICD_ISPENDR13_t;
4147 #define ALT_GIC_DIST_GICD_ISPENDR13_RESET 0x00000000
4149 #define ALT_GIC_DIST_GICD_ISPENDR13_OFST 0x234
4172 #define ALT_GIC_DIST_GICD_ISPENDR14_FLD_LSB 0
4174 #define ALT_GIC_DIST_GICD_ISPENDR14_FLD_MSB 31
4176 #define ALT_GIC_DIST_GICD_ISPENDR14_FLD_WIDTH 32
4178 #define ALT_GIC_DIST_GICD_ISPENDR14_FLD_SET_MSK 0xffffffff
4180 #define ALT_GIC_DIST_GICD_ISPENDR14_FLD_CLR_MSK 0x00000000
4182 #define ALT_GIC_DIST_GICD_ISPENDR14_FLD_RESET 0x0
4184 #define ALT_GIC_DIST_GICD_ISPENDR14_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4186 #define ALT_GIC_DIST_GICD_ISPENDR14_FLD_SET(value) (((value) << 0) & 0xffffffff)
4188 #ifndef __ASSEMBLY__
4200 struct ALT_GIC_DIST_GICD_ISPENDR14_s
4202 volatile uint32_t fld : 32;
4206 typedef struct ALT_GIC_DIST_GICD_ISPENDR14_s ALT_GIC_DIST_GICD_ISPENDR14_t;
4210 #define ALT_GIC_DIST_GICD_ISPENDR14_RESET 0x00000000
4212 #define ALT_GIC_DIST_GICD_ISPENDR14_OFST 0x238
4235 #define ALT_GIC_DIST_GICD_ISPENDR15_FLD_LSB 0
4237 #define ALT_GIC_DIST_GICD_ISPENDR15_FLD_MSB 31
4239 #define ALT_GIC_DIST_GICD_ISPENDR15_FLD_WIDTH 32
4241 #define ALT_GIC_DIST_GICD_ISPENDR15_FLD_SET_MSK 0xffffffff
4243 #define ALT_GIC_DIST_GICD_ISPENDR15_FLD_CLR_MSK 0x00000000
4245 #define ALT_GIC_DIST_GICD_ISPENDR15_FLD_RESET 0x0
4247 #define ALT_GIC_DIST_GICD_ISPENDR15_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4249 #define ALT_GIC_DIST_GICD_ISPENDR15_FLD_SET(value) (((value) << 0) & 0xffffffff)
4251 #ifndef __ASSEMBLY__
4263 struct ALT_GIC_DIST_GICD_ISPENDR15_s
4265 volatile uint32_t fld : 32;
4269 typedef struct ALT_GIC_DIST_GICD_ISPENDR15_s ALT_GIC_DIST_GICD_ISPENDR15_t;
4273 #define ALT_GIC_DIST_GICD_ISPENDR15_RESET 0x00000000
4275 #define ALT_GIC_DIST_GICD_ISPENDR15_OFST 0x23c
4298 #define ALT_GIC_DIST_GICD_ICPENDR0_FLD_LSB 0
4300 #define ALT_GIC_DIST_GICD_ICPENDR0_FLD_MSB 31
4302 #define ALT_GIC_DIST_GICD_ICPENDR0_FLD_WIDTH 32
4304 #define ALT_GIC_DIST_GICD_ICPENDR0_FLD_SET_MSK 0xffffffff
4306 #define ALT_GIC_DIST_GICD_ICPENDR0_FLD_CLR_MSK 0x00000000
4308 #define ALT_GIC_DIST_GICD_ICPENDR0_FLD_RESET 0x0
4310 #define ALT_GIC_DIST_GICD_ICPENDR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4312 #define ALT_GIC_DIST_GICD_ICPENDR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
4314 #ifndef __ASSEMBLY__
4326 struct ALT_GIC_DIST_GICD_ICPENDR0_s
4328 volatile uint32_t fld : 32;
4332 typedef struct ALT_GIC_DIST_GICD_ICPENDR0_s ALT_GIC_DIST_GICD_ICPENDR0_t;
4336 #define ALT_GIC_DIST_GICD_ICPENDR0_RESET 0x00000000
4338 #define ALT_GIC_DIST_GICD_ICPENDR0_OFST 0x280
4361 #define ALT_GIC_DIST_GICD_ICPENDR1_FLD_LSB 0
4363 #define ALT_GIC_DIST_GICD_ICPENDR1_FLD_MSB 31
4365 #define ALT_GIC_DIST_GICD_ICPENDR1_FLD_WIDTH 32
4367 #define ALT_GIC_DIST_GICD_ICPENDR1_FLD_SET_MSK 0xffffffff
4369 #define ALT_GIC_DIST_GICD_ICPENDR1_FLD_CLR_MSK 0x00000000
4371 #define ALT_GIC_DIST_GICD_ICPENDR1_FLD_RESET 0x0
4373 #define ALT_GIC_DIST_GICD_ICPENDR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4375 #define ALT_GIC_DIST_GICD_ICPENDR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
4377 #ifndef __ASSEMBLY__
4389 struct ALT_GIC_DIST_GICD_ICPENDR1_s
4391 volatile uint32_t fld : 32;
4395 typedef struct ALT_GIC_DIST_GICD_ICPENDR1_s ALT_GIC_DIST_GICD_ICPENDR1_t;
4399 #define ALT_GIC_DIST_GICD_ICPENDR1_RESET 0x00000000
4401 #define ALT_GIC_DIST_GICD_ICPENDR1_OFST 0x284
4424 #define ALT_GIC_DIST_GICD_ICPENDR2_FLD_LSB 0
4426 #define ALT_GIC_DIST_GICD_ICPENDR2_FLD_MSB 31
4428 #define ALT_GIC_DIST_GICD_ICPENDR2_FLD_WIDTH 32
4430 #define ALT_GIC_DIST_GICD_ICPENDR2_FLD_SET_MSK 0xffffffff
4432 #define ALT_GIC_DIST_GICD_ICPENDR2_FLD_CLR_MSK 0x00000000
4434 #define ALT_GIC_DIST_GICD_ICPENDR2_FLD_RESET 0x0
4436 #define ALT_GIC_DIST_GICD_ICPENDR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4438 #define ALT_GIC_DIST_GICD_ICPENDR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
4440 #ifndef __ASSEMBLY__
4452 struct ALT_GIC_DIST_GICD_ICPENDR2_s
4454 volatile uint32_t fld : 32;
4458 typedef struct ALT_GIC_DIST_GICD_ICPENDR2_s ALT_GIC_DIST_GICD_ICPENDR2_t;
4462 #define ALT_GIC_DIST_GICD_ICPENDR2_RESET 0x00000000
4464 #define ALT_GIC_DIST_GICD_ICPENDR2_OFST 0x288
4487 #define ALT_GIC_DIST_GICD_ICPENDR3_FLD_LSB 0
4489 #define ALT_GIC_DIST_GICD_ICPENDR3_FLD_MSB 31
4491 #define ALT_GIC_DIST_GICD_ICPENDR3_FLD_WIDTH 32
4493 #define ALT_GIC_DIST_GICD_ICPENDR3_FLD_SET_MSK 0xffffffff
4495 #define ALT_GIC_DIST_GICD_ICPENDR3_FLD_CLR_MSK 0x00000000
4497 #define ALT_GIC_DIST_GICD_ICPENDR3_FLD_RESET 0x0
4499 #define ALT_GIC_DIST_GICD_ICPENDR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4501 #define ALT_GIC_DIST_GICD_ICPENDR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
4503 #ifndef __ASSEMBLY__
4515 struct ALT_GIC_DIST_GICD_ICPENDR3_s
4517 volatile uint32_t fld : 32;
4521 typedef struct ALT_GIC_DIST_GICD_ICPENDR3_s ALT_GIC_DIST_GICD_ICPENDR3_t;
4525 #define ALT_GIC_DIST_GICD_ICPENDR3_RESET 0x00000000
4527 #define ALT_GIC_DIST_GICD_ICPENDR3_OFST 0x28c
4550 #define ALT_GIC_DIST_GICD_ICPENDR4_FLD_LSB 0
4552 #define ALT_GIC_DIST_GICD_ICPENDR4_FLD_MSB 31
4554 #define ALT_GIC_DIST_GICD_ICPENDR4_FLD_WIDTH 32
4556 #define ALT_GIC_DIST_GICD_ICPENDR4_FLD_SET_MSK 0xffffffff
4558 #define ALT_GIC_DIST_GICD_ICPENDR4_FLD_CLR_MSK 0x00000000
4560 #define ALT_GIC_DIST_GICD_ICPENDR4_FLD_RESET 0x0
4562 #define ALT_GIC_DIST_GICD_ICPENDR4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4564 #define ALT_GIC_DIST_GICD_ICPENDR4_FLD_SET(value) (((value) << 0) & 0xffffffff)
4566 #ifndef __ASSEMBLY__
4578 struct ALT_GIC_DIST_GICD_ICPENDR4_s
4580 volatile uint32_t fld : 32;
4584 typedef struct ALT_GIC_DIST_GICD_ICPENDR4_s ALT_GIC_DIST_GICD_ICPENDR4_t;
4588 #define ALT_GIC_DIST_GICD_ICPENDR4_RESET 0x00000000
4590 #define ALT_GIC_DIST_GICD_ICPENDR4_OFST 0x290
4613 #define ALT_GIC_DIST_GICD_ICPENDR5_FLD_LSB 0
4615 #define ALT_GIC_DIST_GICD_ICPENDR5_FLD_MSB 31
4617 #define ALT_GIC_DIST_GICD_ICPENDR5_FLD_WIDTH 32
4619 #define ALT_GIC_DIST_GICD_ICPENDR5_FLD_SET_MSK 0xffffffff
4621 #define ALT_GIC_DIST_GICD_ICPENDR5_FLD_CLR_MSK 0x00000000
4623 #define ALT_GIC_DIST_GICD_ICPENDR5_FLD_RESET 0x0
4625 #define ALT_GIC_DIST_GICD_ICPENDR5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4627 #define ALT_GIC_DIST_GICD_ICPENDR5_FLD_SET(value) (((value) << 0) & 0xffffffff)
4629 #ifndef __ASSEMBLY__
4641 struct ALT_GIC_DIST_GICD_ICPENDR5_s
4643 volatile uint32_t fld : 32;
4647 typedef struct ALT_GIC_DIST_GICD_ICPENDR5_s ALT_GIC_DIST_GICD_ICPENDR5_t;
4651 #define ALT_GIC_DIST_GICD_ICPENDR5_RESET 0x00000000
4653 #define ALT_GIC_DIST_GICD_ICPENDR5_OFST 0x294
4676 #define ALT_GIC_DIST_GICD_ICPENDR6_FLD_LSB 0
4678 #define ALT_GIC_DIST_GICD_ICPENDR6_FLD_MSB 31
4680 #define ALT_GIC_DIST_GICD_ICPENDR6_FLD_WIDTH 32
4682 #define ALT_GIC_DIST_GICD_ICPENDR6_FLD_SET_MSK 0xffffffff
4684 #define ALT_GIC_DIST_GICD_ICPENDR6_FLD_CLR_MSK 0x00000000
4686 #define ALT_GIC_DIST_GICD_ICPENDR6_FLD_RESET 0x0
4688 #define ALT_GIC_DIST_GICD_ICPENDR6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4690 #define ALT_GIC_DIST_GICD_ICPENDR6_FLD_SET(value) (((value) << 0) & 0xffffffff)
4692 #ifndef __ASSEMBLY__
4704 struct ALT_GIC_DIST_GICD_ICPENDR6_s
4706 volatile uint32_t fld : 32;
4710 typedef struct ALT_GIC_DIST_GICD_ICPENDR6_s ALT_GIC_DIST_GICD_ICPENDR6_t;
4714 #define ALT_GIC_DIST_GICD_ICPENDR6_RESET 0x00000000
4716 #define ALT_GIC_DIST_GICD_ICPENDR6_OFST 0x298
4739 #define ALT_GIC_DIST_GICD_ICPENDR7_FLD_LSB 0
4741 #define ALT_GIC_DIST_GICD_ICPENDR7_FLD_MSB 31
4743 #define ALT_GIC_DIST_GICD_ICPENDR7_FLD_WIDTH 32
4745 #define ALT_GIC_DIST_GICD_ICPENDR7_FLD_SET_MSK 0xffffffff
4747 #define ALT_GIC_DIST_GICD_ICPENDR7_FLD_CLR_MSK 0x00000000
4749 #define ALT_GIC_DIST_GICD_ICPENDR7_FLD_RESET 0x0
4751 #define ALT_GIC_DIST_GICD_ICPENDR7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4753 #define ALT_GIC_DIST_GICD_ICPENDR7_FLD_SET(value) (((value) << 0) & 0xffffffff)
4755 #ifndef __ASSEMBLY__
4767 struct ALT_GIC_DIST_GICD_ICPENDR7_s
4769 volatile uint32_t fld : 32;
4773 typedef struct ALT_GIC_DIST_GICD_ICPENDR7_s ALT_GIC_DIST_GICD_ICPENDR7_t;
4777 #define ALT_GIC_DIST_GICD_ICPENDR7_RESET 0x00000000
4779 #define ALT_GIC_DIST_GICD_ICPENDR7_OFST 0x29c
4802 #define ALT_GIC_DIST_GICD_ICPENDR8_FLD_LSB 0
4804 #define ALT_GIC_DIST_GICD_ICPENDR8_FLD_MSB 31
4806 #define ALT_GIC_DIST_GICD_ICPENDR8_FLD_WIDTH 32
4808 #define ALT_GIC_DIST_GICD_ICPENDR8_FLD_SET_MSK 0xffffffff
4810 #define ALT_GIC_DIST_GICD_ICPENDR8_FLD_CLR_MSK 0x00000000
4812 #define ALT_GIC_DIST_GICD_ICPENDR8_FLD_RESET 0x0
4814 #define ALT_GIC_DIST_GICD_ICPENDR8_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4816 #define ALT_GIC_DIST_GICD_ICPENDR8_FLD_SET(value) (((value) << 0) & 0xffffffff)
4818 #ifndef __ASSEMBLY__
4830 struct ALT_GIC_DIST_GICD_ICPENDR8_s
4832 volatile uint32_t fld : 32;
4836 typedef struct ALT_GIC_DIST_GICD_ICPENDR8_s ALT_GIC_DIST_GICD_ICPENDR8_t;
4840 #define ALT_GIC_DIST_GICD_ICPENDR8_RESET 0x00000000
4842 #define ALT_GIC_DIST_GICD_ICPENDR8_OFST 0x2a0
4865 #define ALT_GIC_DIST_GICD_ICPENDR9_FLD_LSB 0
4867 #define ALT_GIC_DIST_GICD_ICPENDR9_FLD_MSB 31
4869 #define ALT_GIC_DIST_GICD_ICPENDR9_FLD_WIDTH 32
4871 #define ALT_GIC_DIST_GICD_ICPENDR9_FLD_SET_MSK 0xffffffff
4873 #define ALT_GIC_DIST_GICD_ICPENDR9_FLD_CLR_MSK 0x00000000
4875 #define ALT_GIC_DIST_GICD_ICPENDR9_FLD_RESET 0x0
4877 #define ALT_GIC_DIST_GICD_ICPENDR9_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4879 #define ALT_GIC_DIST_GICD_ICPENDR9_FLD_SET(value) (((value) << 0) & 0xffffffff)
4881 #ifndef __ASSEMBLY__
4893 struct ALT_GIC_DIST_GICD_ICPENDR9_s
4895 volatile uint32_t fld : 32;
4899 typedef struct ALT_GIC_DIST_GICD_ICPENDR9_s ALT_GIC_DIST_GICD_ICPENDR9_t;
4903 #define ALT_GIC_DIST_GICD_ICPENDR9_RESET 0x00000000
4905 #define ALT_GIC_DIST_GICD_ICPENDR9_OFST 0x2a4
4928 #define ALT_GIC_DIST_GICD_ICPENDR10_FLD_LSB 0
4930 #define ALT_GIC_DIST_GICD_ICPENDR10_FLD_MSB 31
4932 #define ALT_GIC_DIST_GICD_ICPENDR10_FLD_WIDTH 32
4934 #define ALT_GIC_DIST_GICD_ICPENDR10_FLD_SET_MSK 0xffffffff
4936 #define ALT_GIC_DIST_GICD_ICPENDR10_FLD_CLR_MSK 0x00000000
4938 #define ALT_GIC_DIST_GICD_ICPENDR10_FLD_RESET 0x0
4940 #define ALT_GIC_DIST_GICD_ICPENDR10_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4942 #define ALT_GIC_DIST_GICD_ICPENDR10_FLD_SET(value) (((value) << 0) & 0xffffffff)
4944 #ifndef __ASSEMBLY__
4956 struct ALT_GIC_DIST_GICD_ICPENDR10_s
4958 volatile uint32_t fld : 32;
4962 typedef struct ALT_GIC_DIST_GICD_ICPENDR10_s ALT_GIC_DIST_GICD_ICPENDR10_t;
4966 #define ALT_GIC_DIST_GICD_ICPENDR10_RESET 0x00000000
4968 #define ALT_GIC_DIST_GICD_ICPENDR10_OFST 0x2a8
4991 #define ALT_GIC_DIST_GICD_ICPENDR11_FLD_LSB 0
4993 #define ALT_GIC_DIST_GICD_ICPENDR11_FLD_MSB 31
4995 #define ALT_GIC_DIST_GICD_ICPENDR11_FLD_WIDTH 32
4997 #define ALT_GIC_DIST_GICD_ICPENDR11_FLD_SET_MSK 0xffffffff
4999 #define ALT_GIC_DIST_GICD_ICPENDR11_FLD_CLR_MSK 0x00000000
5001 #define ALT_GIC_DIST_GICD_ICPENDR11_FLD_RESET 0x0
5003 #define ALT_GIC_DIST_GICD_ICPENDR11_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5005 #define ALT_GIC_DIST_GICD_ICPENDR11_FLD_SET(value) (((value) << 0) & 0xffffffff)
5007 #ifndef __ASSEMBLY__
5019 struct ALT_GIC_DIST_GICD_ICPENDR11_s
5021 volatile uint32_t fld : 32;
5025 typedef struct ALT_GIC_DIST_GICD_ICPENDR11_s ALT_GIC_DIST_GICD_ICPENDR11_t;
5029 #define ALT_GIC_DIST_GICD_ICPENDR11_RESET 0x00000000
5031 #define ALT_GIC_DIST_GICD_ICPENDR11_OFST 0x2ac
5054 #define ALT_GIC_DIST_GICD_ICPENDR12_FLD_LSB 0
5056 #define ALT_GIC_DIST_GICD_ICPENDR12_FLD_MSB 31
5058 #define ALT_GIC_DIST_GICD_ICPENDR12_FLD_WIDTH 32
5060 #define ALT_GIC_DIST_GICD_ICPENDR12_FLD_SET_MSK 0xffffffff
5062 #define ALT_GIC_DIST_GICD_ICPENDR12_FLD_CLR_MSK 0x00000000
5064 #define ALT_GIC_DIST_GICD_ICPENDR12_FLD_RESET 0x0
5066 #define ALT_GIC_DIST_GICD_ICPENDR12_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5068 #define ALT_GIC_DIST_GICD_ICPENDR12_FLD_SET(value) (((value) << 0) & 0xffffffff)
5070 #ifndef __ASSEMBLY__
5082 struct ALT_GIC_DIST_GICD_ICPENDR12_s
5084 volatile uint32_t fld : 32;
5088 typedef struct ALT_GIC_DIST_GICD_ICPENDR12_s ALT_GIC_DIST_GICD_ICPENDR12_t;
5092 #define ALT_GIC_DIST_GICD_ICPENDR12_RESET 0x00000000
5094 #define ALT_GIC_DIST_GICD_ICPENDR12_OFST 0x2b0
5117 #define ALT_GIC_DIST_GICD_ICPENDR13_FLD_LSB 0
5119 #define ALT_GIC_DIST_GICD_ICPENDR13_FLD_MSB 31
5121 #define ALT_GIC_DIST_GICD_ICPENDR13_FLD_WIDTH 32
5123 #define ALT_GIC_DIST_GICD_ICPENDR13_FLD_SET_MSK 0xffffffff
5125 #define ALT_GIC_DIST_GICD_ICPENDR13_FLD_CLR_MSK 0x00000000
5127 #define ALT_GIC_DIST_GICD_ICPENDR13_FLD_RESET 0x0
5129 #define ALT_GIC_DIST_GICD_ICPENDR13_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5131 #define ALT_GIC_DIST_GICD_ICPENDR13_FLD_SET(value) (((value) << 0) & 0xffffffff)
5133 #ifndef __ASSEMBLY__
5145 struct ALT_GIC_DIST_GICD_ICPENDR13_s
5147 volatile uint32_t fld : 32;
5151 typedef struct ALT_GIC_DIST_GICD_ICPENDR13_s ALT_GIC_DIST_GICD_ICPENDR13_t;
5155 #define ALT_GIC_DIST_GICD_ICPENDR13_RESET 0x00000000
5157 #define ALT_GIC_DIST_GICD_ICPENDR13_OFST 0x2b4
5180 #define ALT_GIC_DIST_GICD_ICPENDR14_FLD_LSB 0
5182 #define ALT_GIC_DIST_GICD_ICPENDR14_FLD_MSB 31
5184 #define ALT_GIC_DIST_GICD_ICPENDR14_FLD_WIDTH 32
5186 #define ALT_GIC_DIST_GICD_ICPENDR14_FLD_SET_MSK 0xffffffff
5188 #define ALT_GIC_DIST_GICD_ICPENDR14_FLD_CLR_MSK 0x00000000
5190 #define ALT_GIC_DIST_GICD_ICPENDR14_FLD_RESET 0x0
5192 #define ALT_GIC_DIST_GICD_ICPENDR14_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5194 #define ALT_GIC_DIST_GICD_ICPENDR14_FLD_SET(value) (((value) << 0) & 0xffffffff)
5196 #ifndef __ASSEMBLY__
5208 struct ALT_GIC_DIST_GICD_ICPENDR14_s
5210 volatile uint32_t fld : 32;
5214 typedef struct ALT_GIC_DIST_GICD_ICPENDR14_s ALT_GIC_DIST_GICD_ICPENDR14_t;
5218 #define ALT_GIC_DIST_GICD_ICPENDR14_RESET 0x00000000
5220 #define ALT_GIC_DIST_GICD_ICPENDR14_OFST 0x2b8
5243 #define ALT_GIC_DIST_GICD_ICPENDR15_FLD_LSB 0
5245 #define ALT_GIC_DIST_GICD_ICPENDR15_FLD_MSB 31
5247 #define ALT_GIC_DIST_GICD_ICPENDR15_FLD_WIDTH 32
5249 #define ALT_GIC_DIST_GICD_ICPENDR15_FLD_SET_MSK 0xffffffff
5251 #define ALT_GIC_DIST_GICD_ICPENDR15_FLD_CLR_MSK 0x00000000
5253 #define ALT_GIC_DIST_GICD_ICPENDR15_FLD_RESET 0x0
5255 #define ALT_GIC_DIST_GICD_ICPENDR15_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5257 #define ALT_GIC_DIST_GICD_ICPENDR15_FLD_SET(value) (((value) << 0) & 0xffffffff)
5259 #ifndef __ASSEMBLY__
5271 struct ALT_GIC_DIST_GICD_ICPENDR15_s
5273 volatile uint32_t fld : 32;
5277 typedef struct ALT_GIC_DIST_GICD_ICPENDR15_s ALT_GIC_DIST_GICD_ICPENDR15_t;
5281 #define ALT_GIC_DIST_GICD_ICPENDR15_RESET 0x00000000
5283 #define ALT_GIC_DIST_GICD_ICPENDR15_OFST 0x2bc
5306 #define ALT_GIC_DIST_GICD_ISACTIVER0_FLD_LSB 0
5308 #define ALT_GIC_DIST_GICD_ISACTIVER0_FLD_MSB 31
5310 #define ALT_GIC_DIST_GICD_ISACTIVER0_FLD_WIDTH 32
5312 #define ALT_GIC_DIST_GICD_ISACTIVER0_FLD_SET_MSK 0xffffffff
5314 #define ALT_GIC_DIST_GICD_ISACTIVER0_FLD_CLR_MSK 0x00000000
5316 #define ALT_GIC_DIST_GICD_ISACTIVER0_FLD_RESET 0x0
5318 #define ALT_GIC_DIST_GICD_ISACTIVER0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5320 #define ALT_GIC_DIST_GICD_ISACTIVER0_FLD_SET(value) (((value) << 0) & 0xffffffff)
5322 #ifndef __ASSEMBLY__
5334 struct ALT_GIC_DIST_GICD_ISACTIVER0_s
5336 volatile uint32_t fld : 32;
5340 typedef struct ALT_GIC_DIST_GICD_ISACTIVER0_s ALT_GIC_DIST_GICD_ISACTIVER0_t;
5344 #define ALT_GIC_DIST_GICD_ISACTIVER0_RESET 0x00000000
5346 #define ALT_GIC_DIST_GICD_ISACTIVER0_OFST 0x300
5369 #define ALT_GIC_DIST_GICD_ISACTIVER1_FLD_LSB 0
5371 #define ALT_GIC_DIST_GICD_ISACTIVER1_FLD_MSB 31
5373 #define ALT_GIC_DIST_GICD_ISACTIVER1_FLD_WIDTH 32
5375 #define ALT_GIC_DIST_GICD_ISACTIVER1_FLD_SET_MSK 0xffffffff
5377 #define ALT_GIC_DIST_GICD_ISACTIVER1_FLD_CLR_MSK 0x00000000
5379 #define ALT_GIC_DIST_GICD_ISACTIVER1_FLD_RESET 0x0
5381 #define ALT_GIC_DIST_GICD_ISACTIVER1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5383 #define ALT_GIC_DIST_GICD_ISACTIVER1_FLD_SET(value) (((value) << 0) & 0xffffffff)
5385 #ifndef __ASSEMBLY__
5397 struct ALT_GIC_DIST_GICD_ISACTIVER1_s
5399 volatile uint32_t fld : 32;
5403 typedef struct ALT_GIC_DIST_GICD_ISACTIVER1_s ALT_GIC_DIST_GICD_ISACTIVER1_t;
5407 #define ALT_GIC_DIST_GICD_ISACTIVER1_RESET 0x00000000
5409 #define ALT_GIC_DIST_GICD_ISACTIVER1_OFST 0x304
5432 #define ALT_GIC_DIST_GICD_ISACTIVER2_FLD_LSB 0
5434 #define ALT_GIC_DIST_GICD_ISACTIVER2_FLD_MSB 31
5436 #define ALT_GIC_DIST_GICD_ISACTIVER2_FLD_WIDTH 32
5438 #define ALT_GIC_DIST_GICD_ISACTIVER2_FLD_SET_MSK 0xffffffff
5440 #define ALT_GIC_DIST_GICD_ISACTIVER2_FLD_CLR_MSK 0x00000000
5442 #define ALT_GIC_DIST_GICD_ISACTIVER2_FLD_RESET 0x0
5444 #define ALT_GIC_DIST_GICD_ISACTIVER2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5446 #define ALT_GIC_DIST_GICD_ISACTIVER2_FLD_SET(value) (((value) << 0) & 0xffffffff)
5448 #ifndef __ASSEMBLY__
5460 struct ALT_GIC_DIST_GICD_ISACTIVER2_s
5462 volatile uint32_t fld : 32;
5466 typedef struct ALT_GIC_DIST_GICD_ISACTIVER2_s ALT_GIC_DIST_GICD_ISACTIVER2_t;
5470 #define ALT_GIC_DIST_GICD_ISACTIVER2_RESET 0x00000000
5472 #define ALT_GIC_DIST_GICD_ISACTIVER2_OFST 0x308
5495 #define ALT_GIC_DIST_GICD_ISACTIVER3_FLD_LSB 0
5497 #define ALT_GIC_DIST_GICD_ISACTIVER3_FLD_MSB 31
5499 #define ALT_GIC_DIST_GICD_ISACTIVER3_FLD_WIDTH 32
5501 #define ALT_GIC_DIST_GICD_ISACTIVER3_FLD_SET_MSK 0xffffffff
5503 #define ALT_GIC_DIST_GICD_ISACTIVER3_FLD_CLR_MSK 0x00000000
5505 #define ALT_GIC_DIST_GICD_ISACTIVER3_FLD_RESET 0x0
5507 #define ALT_GIC_DIST_GICD_ISACTIVER3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5509 #define ALT_GIC_DIST_GICD_ISACTIVER3_FLD_SET(value) (((value) << 0) & 0xffffffff)
5511 #ifndef __ASSEMBLY__
5523 struct ALT_GIC_DIST_GICD_ISACTIVER3_s
5525 volatile uint32_t fld : 32;
5529 typedef struct ALT_GIC_DIST_GICD_ISACTIVER3_s ALT_GIC_DIST_GICD_ISACTIVER3_t;
5533 #define ALT_GIC_DIST_GICD_ISACTIVER3_RESET 0x00000000
5535 #define ALT_GIC_DIST_GICD_ISACTIVER3_OFST 0x30c
5558 #define ALT_GIC_DIST_GICD_ISACTIVER4_FLD_LSB 0
5560 #define ALT_GIC_DIST_GICD_ISACTIVER4_FLD_MSB 31
5562 #define ALT_GIC_DIST_GICD_ISACTIVER4_FLD_WIDTH 32
5564 #define ALT_GIC_DIST_GICD_ISACTIVER4_FLD_SET_MSK 0xffffffff
5566 #define ALT_GIC_DIST_GICD_ISACTIVER4_FLD_CLR_MSK 0x00000000
5568 #define ALT_GIC_DIST_GICD_ISACTIVER4_FLD_RESET 0x0
5570 #define ALT_GIC_DIST_GICD_ISACTIVER4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5572 #define ALT_GIC_DIST_GICD_ISACTIVER4_FLD_SET(value) (((value) << 0) & 0xffffffff)
5574 #ifndef __ASSEMBLY__
5586 struct ALT_GIC_DIST_GICD_ISACTIVER4_s
5588 volatile uint32_t fld : 32;
5592 typedef struct ALT_GIC_DIST_GICD_ISACTIVER4_s ALT_GIC_DIST_GICD_ISACTIVER4_t;
5596 #define ALT_GIC_DIST_GICD_ISACTIVER4_RESET 0x00000000
5598 #define ALT_GIC_DIST_GICD_ISACTIVER4_OFST 0x310
5621 #define ALT_GIC_DIST_GICD_ISACTIVER5_FLD_LSB 0
5623 #define ALT_GIC_DIST_GICD_ISACTIVER5_FLD_MSB 31
5625 #define ALT_GIC_DIST_GICD_ISACTIVER5_FLD_WIDTH 32
5627 #define ALT_GIC_DIST_GICD_ISACTIVER5_FLD_SET_MSK 0xffffffff
5629 #define ALT_GIC_DIST_GICD_ISACTIVER5_FLD_CLR_MSK 0x00000000
5631 #define ALT_GIC_DIST_GICD_ISACTIVER5_FLD_RESET 0x0
5633 #define ALT_GIC_DIST_GICD_ISACTIVER5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5635 #define ALT_GIC_DIST_GICD_ISACTIVER5_FLD_SET(value) (((value) << 0) & 0xffffffff)
5637 #ifndef __ASSEMBLY__
5649 struct ALT_GIC_DIST_GICD_ISACTIVER5_s
5651 volatile uint32_t fld : 32;
5655 typedef struct ALT_GIC_DIST_GICD_ISACTIVER5_s ALT_GIC_DIST_GICD_ISACTIVER5_t;
5659 #define ALT_GIC_DIST_GICD_ISACTIVER5_RESET 0x00000000
5661 #define ALT_GIC_DIST_GICD_ISACTIVER5_OFST 0x314
5684 #define ALT_GIC_DIST_GICD_ISACTIVER6_FLD_LSB 0
5686 #define ALT_GIC_DIST_GICD_ISACTIVER6_FLD_MSB 31
5688 #define ALT_GIC_DIST_GICD_ISACTIVER6_FLD_WIDTH 32
5690 #define ALT_GIC_DIST_GICD_ISACTIVER6_FLD_SET_MSK 0xffffffff
5692 #define ALT_GIC_DIST_GICD_ISACTIVER6_FLD_CLR_MSK 0x00000000
5694 #define ALT_GIC_DIST_GICD_ISACTIVER6_FLD_RESET 0x0
5696 #define ALT_GIC_DIST_GICD_ISACTIVER6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5698 #define ALT_GIC_DIST_GICD_ISACTIVER6_FLD_SET(value) (((value) << 0) & 0xffffffff)
5700 #ifndef __ASSEMBLY__
5712 struct ALT_GIC_DIST_GICD_ISACTIVER6_s
5714 volatile uint32_t fld : 32;
5718 typedef struct ALT_GIC_DIST_GICD_ISACTIVER6_s ALT_GIC_DIST_GICD_ISACTIVER6_t;
5722 #define ALT_GIC_DIST_GICD_ISACTIVER6_RESET 0x00000000
5724 #define ALT_GIC_DIST_GICD_ISACTIVER6_OFST 0x318
5747 #define ALT_GIC_DIST_GICD_ISACTIVER7_FLD_LSB 0
5749 #define ALT_GIC_DIST_GICD_ISACTIVER7_FLD_MSB 31
5751 #define ALT_GIC_DIST_GICD_ISACTIVER7_FLD_WIDTH 32
5753 #define ALT_GIC_DIST_GICD_ISACTIVER7_FLD_SET_MSK 0xffffffff
5755 #define ALT_GIC_DIST_GICD_ISACTIVER7_FLD_CLR_MSK 0x00000000
5757 #define ALT_GIC_DIST_GICD_ISACTIVER7_FLD_RESET 0x0
5759 #define ALT_GIC_DIST_GICD_ISACTIVER7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5761 #define ALT_GIC_DIST_GICD_ISACTIVER7_FLD_SET(value) (((value) << 0) & 0xffffffff)
5763 #ifndef __ASSEMBLY__
5775 struct ALT_GIC_DIST_GICD_ISACTIVER7_s
5777 volatile uint32_t fld : 32;
5781 typedef struct ALT_GIC_DIST_GICD_ISACTIVER7_s ALT_GIC_DIST_GICD_ISACTIVER7_t;
5785 #define ALT_GIC_DIST_GICD_ISACTIVER7_RESET 0x00000000
5787 #define ALT_GIC_DIST_GICD_ISACTIVER7_OFST 0x31c
5810 #define ALT_GIC_DIST_GICD_ISACTIVER8_FLD_LSB 0
5812 #define ALT_GIC_DIST_GICD_ISACTIVER8_FLD_MSB 31
5814 #define ALT_GIC_DIST_GICD_ISACTIVER8_FLD_WIDTH 32
5816 #define ALT_GIC_DIST_GICD_ISACTIVER8_FLD_SET_MSK 0xffffffff
5818 #define ALT_GIC_DIST_GICD_ISACTIVER8_FLD_CLR_MSK 0x00000000
5820 #define ALT_GIC_DIST_GICD_ISACTIVER8_FLD_RESET 0x0
5822 #define ALT_GIC_DIST_GICD_ISACTIVER8_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5824 #define ALT_GIC_DIST_GICD_ISACTIVER8_FLD_SET(value) (((value) << 0) & 0xffffffff)
5826 #ifndef __ASSEMBLY__
5838 struct ALT_GIC_DIST_GICD_ISACTIVER8_s
5840 volatile uint32_t fld : 32;
5844 typedef struct ALT_GIC_DIST_GICD_ISACTIVER8_s ALT_GIC_DIST_GICD_ISACTIVER8_t;
5848 #define ALT_GIC_DIST_GICD_ISACTIVER8_RESET 0x00000000
5850 #define ALT_GIC_DIST_GICD_ISACTIVER8_OFST 0x320
5873 #define ALT_GIC_DIST_GICD_ISACTIVER9_FLD_LSB 0
5875 #define ALT_GIC_DIST_GICD_ISACTIVER9_FLD_MSB 31
5877 #define ALT_GIC_DIST_GICD_ISACTIVER9_FLD_WIDTH 32
5879 #define ALT_GIC_DIST_GICD_ISACTIVER9_FLD_SET_MSK 0xffffffff
5881 #define ALT_GIC_DIST_GICD_ISACTIVER9_FLD_CLR_MSK 0x00000000
5883 #define ALT_GIC_DIST_GICD_ISACTIVER9_FLD_RESET 0x0
5885 #define ALT_GIC_DIST_GICD_ISACTIVER9_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5887 #define ALT_GIC_DIST_GICD_ISACTIVER9_FLD_SET(value) (((value) << 0) & 0xffffffff)
5889 #ifndef __ASSEMBLY__
5901 struct ALT_GIC_DIST_GICD_ISACTIVER9_s
5903 volatile uint32_t fld : 32;
5907 typedef struct ALT_GIC_DIST_GICD_ISACTIVER9_s ALT_GIC_DIST_GICD_ISACTIVER9_t;
5911 #define ALT_GIC_DIST_GICD_ISACTIVER9_RESET 0x00000000
5913 #define ALT_GIC_DIST_GICD_ISACTIVER9_OFST 0x324
5936 #define ALT_GIC_DIST_GICD_ISACTIVER10_FLD_LSB 0
5938 #define ALT_GIC_DIST_GICD_ISACTIVER10_FLD_MSB 31
5940 #define ALT_GIC_DIST_GICD_ISACTIVER10_FLD_WIDTH 32
5942 #define ALT_GIC_DIST_GICD_ISACTIVER10_FLD_SET_MSK 0xffffffff
5944 #define ALT_GIC_DIST_GICD_ISACTIVER10_FLD_CLR_MSK 0x00000000
5946 #define ALT_GIC_DIST_GICD_ISACTIVER10_FLD_RESET 0x0
5948 #define ALT_GIC_DIST_GICD_ISACTIVER10_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5950 #define ALT_GIC_DIST_GICD_ISACTIVER10_FLD_SET(value) (((value) << 0) & 0xffffffff)
5952 #ifndef __ASSEMBLY__
5964 struct ALT_GIC_DIST_GICD_ISACTIVER10_s
5966 volatile uint32_t fld : 32;
5970 typedef struct ALT_GIC_DIST_GICD_ISACTIVER10_s ALT_GIC_DIST_GICD_ISACTIVER10_t;
5974 #define ALT_GIC_DIST_GICD_ISACTIVER10_RESET 0x00000000
5976 #define ALT_GIC_DIST_GICD_ISACTIVER10_OFST 0x328
5999 #define ALT_GIC_DIST_GICD_ISACTIVER11_FLD_LSB 0
6001 #define ALT_GIC_DIST_GICD_ISACTIVER11_FLD_MSB 31
6003 #define ALT_GIC_DIST_GICD_ISACTIVER11_FLD_WIDTH 32
6005 #define ALT_GIC_DIST_GICD_ISACTIVER11_FLD_SET_MSK 0xffffffff
6007 #define ALT_GIC_DIST_GICD_ISACTIVER11_FLD_CLR_MSK 0x00000000
6009 #define ALT_GIC_DIST_GICD_ISACTIVER11_FLD_RESET 0x0
6011 #define ALT_GIC_DIST_GICD_ISACTIVER11_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6013 #define ALT_GIC_DIST_GICD_ISACTIVER11_FLD_SET(value) (((value) << 0) & 0xffffffff)
6015 #ifndef __ASSEMBLY__
6027 struct ALT_GIC_DIST_GICD_ISACTIVER11_s
6029 volatile uint32_t fld : 32;
6033 typedef struct ALT_GIC_DIST_GICD_ISACTIVER11_s ALT_GIC_DIST_GICD_ISACTIVER11_t;
6037 #define ALT_GIC_DIST_GICD_ISACTIVER11_RESET 0x00000000
6039 #define ALT_GIC_DIST_GICD_ISACTIVER11_OFST 0x32c
6062 #define ALT_GIC_DIST_GICD_ISACTIVER12_FLD_LSB 0
6064 #define ALT_GIC_DIST_GICD_ISACTIVER12_FLD_MSB 31
6066 #define ALT_GIC_DIST_GICD_ISACTIVER12_FLD_WIDTH 32
6068 #define ALT_GIC_DIST_GICD_ISACTIVER12_FLD_SET_MSK 0xffffffff
6070 #define ALT_GIC_DIST_GICD_ISACTIVER12_FLD_CLR_MSK 0x00000000
6072 #define ALT_GIC_DIST_GICD_ISACTIVER12_FLD_RESET 0x0
6074 #define ALT_GIC_DIST_GICD_ISACTIVER12_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6076 #define ALT_GIC_DIST_GICD_ISACTIVER12_FLD_SET(value) (((value) << 0) & 0xffffffff)
6078 #ifndef __ASSEMBLY__
6090 struct ALT_GIC_DIST_GICD_ISACTIVER12_s
6092 volatile uint32_t fld : 32;
6096 typedef struct ALT_GIC_DIST_GICD_ISACTIVER12_s ALT_GIC_DIST_GICD_ISACTIVER12_t;
6100 #define ALT_GIC_DIST_GICD_ISACTIVER12_RESET 0x00000000
6102 #define ALT_GIC_DIST_GICD_ISACTIVER12_OFST 0x330
6125 #define ALT_GIC_DIST_GICD_ISACTIVER13_FLD_LSB 0
6127 #define ALT_GIC_DIST_GICD_ISACTIVER13_FLD_MSB 31
6129 #define ALT_GIC_DIST_GICD_ISACTIVER13_FLD_WIDTH 32
6131 #define ALT_GIC_DIST_GICD_ISACTIVER13_FLD_SET_MSK 0xffffffff
6133 #define ALT_GIC_DIST_GICD_ISACTIVER13_FLD_CLR_MSK 0x00000000
6135 #define ALT_GIC_DIST_GICD_ISACTIVER13_FLD_RESET 0x0
6137 #define ALT_GIC_DIST_GICD_ISACTIVER13_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6139 #define ALT_GIC_DIST_GICD_ISACTIVER13_FLD_SET(value) (((value) << 0) & 0xffffffff)
6141 #ifndef __ASSEMBLY__
6153 struct ALT_GIC_DIST_GICD_ISACTIVER13_s
6155 volatile uint32_t fld : 32;
6159 typedef struct ALT_GIC_DIST_GICD_ISACTIVER13_s ALT_GIC_DIST_GICD_ISACTIVER13_t;
6163 #define ALT_GIC_DIST_GICD_ISACTIVER13_RESET 0x00000000
6165 #define ALT_GIC_DIST_GICD_ISACTIVER13_OFST 0x334
6188 #define ALT_GIC_DIST_GICD_ISACTIVER14_FLD_LSB 0
6190 #define ALT_GIC_DIST_GICD_ISACTIVER14_FLD_MSB 31
6192 #define ALT_GIC_DIST_GICD_ISACTIVER14_FLD_WIDTH 32
6194 #define ALT_GIC_DIST_GICD_ISACTIVER14_FLD_SET_MSK 0xffffffff
6196 #define ALT_GIC_DIST_GICD_ISACTIVER14_FLD_CLR_MSK 0x00000000
6198 #define ALT_GIC_DIST_GICD_ISACTIVER14_FLD_RESET 0x0
6200 #define ALT_GIC_DIST_GICD_ISACTIVER14_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6202 #define ALT_GIC_DIST_GICD_ISACTIVER14_FLD_SET(value) (((value) << 0) & 0xffffffff)
6204 #ifndef __ASSEMBLY__
6216 struct ALT_GIC_DIST_GICD_ISACTIVER14_s
6218 volatile uint32_t fld : 32;
6222 typedef struct ALT_GIC_DIST_GICD_ISACTIVER14_s ALT_GIC_DIST_GICD_ISACTIVER14_t;
6226 #define ALT_GIC_DIST_GICD_ISACTIVER14_RESET 0x00000000
6228 #define ALT_GIC_DIST_GICD_ISACTIVER14_OFST 0x338
6251 #define ALT_GIC_DIST_GICD_ISACTIVER15_FLD_LSB 0
6253 #define ALT_GIC_DIST_GICD_ISACTIVER15_FLD_MSB 31
6255 #define ALT_GIC_DIST_GICD_ISACTIVER15_FLD_WIDTH 32
6257 #define ALT_GIC_DIST_GICD_ISACTIVER15_FLD_SET_MSK 0xffffffff
6259 #define ALT_GIC_DIST_GICD_ISACTIVER15_FLD_CLR_MSK 0x00000000
6261 #define ALT_GIC_DIST_GICD_ISACTIVER15_FLD_RESET 0x0
6263 #define ALT_GIC_DIST_GICD_ISACTIVER15_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6265 #define ALT_GIC_DIST_GICD_ISACTIVER15_FLD_SET(value) (((value) << 0) & 0xffffffff)
6267 #ifndef __ASSEMBLY__
6279 struct ALT_GIC_DIST_GICD_ISACTIVER15_s
6281 volatile uint32_t fld : 32;
6285 typedef struct ALT_GIC_DIST_GICD_ISACTIVER15_s ALT_GIC_DIST_GICD_ISACTIVER15_t;
6289 #define ALT_GIC_DIST_GICD_ISACTIVER15_RESET 0x00000000
6291 #define ALT_GIC_DIST_GICD_ISACTIVER15_OFST 0x33c
6314 #define ALT_GIC_DIST_GICD_ICACTIVER0_FLD_LSB 0
6316 #define ALT_GIC_DIST_GICD_ICACTIVER0_FLD_MSB 31
6318 #define ALT_GIC_DIST_GICD_ICACTIVER0_FLD_WIDTH 32
6320 #define ALT_GIC_DIST_GICD_ICACTIVER0_FLD_SET_MSK 0xffffffff
6322 #define ALT_GIC_DIST_GICD_ICACTIVER0_FLD_CLR_MSK 0x00000000
6324 #define ALT_GIC_DIST_GICD_ICACTIVER0_FLD_RESET 0x0
6326 #define ALT_GIC_DIST_GICD_ICACTIVER0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6328 #define ALT_GIC_DIST_GICD_ICACTIVER0_FLD_SET(value) (((value) << 0) & 0xffffffff)
6330 #ifndef __ASSEMBLY__
6342 struct ALT_GIC_DIST_GICD_ICACTIVER0_s
6344 volatile uint32_t fld : 32;
6348 typedef struct ALT_GIC_DIST_GICD_ICACTIVER0_s ALT_GIC_DIST_GICD_ICACTIVER0_t;
6352 #define ALT_GIC_DIST_GICD_ICACTIVER0_RESET 0x00000000
6354 #define ALT_GIC_DIST_GICD_ICACTIVER0_OFST 0x380
6377 #define ALT_GIC_DIST_GICD_ICACTIVER1_FLD_LSB 0
6379 #define ALT_GIC_DIST_GICD_ICACTIVER1_FLD_MSB 31
6381 #define ALT_GIC_DIST_GICD_ICACTIVER1_FLD_WIDTH 32
6383 #define ALT_GIC_DIST_GICD_ICACTIVER1_FLD_SET_MSK 0xffffffff
6385 #define ALT_GIC_DIST_GICD_ICACTIVER1_FLD_CLR_MSK 0x00000000
6387 #define ALT_GIC_DIST_GICD_ICACTIVER1_FLD_RESET 0x0
6389 #define ALT_GIC_DIST_GICD_ICACTIVER1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6391 #define ALT_GIC_DIST_GICD_ICACTIVER1_FLD_SET(value) (((value) << 0) & 0xffffffff)
6393 #ifndef __ASSEMBLY__
6405 struct ALT_GIC_DIST_GICD_ICACTIVER1_s
6407 volatile uint32_t fld : 32;
6411 typedef struct ALT_GIC_DIST_GICD_ICACTIVER1_s ALT_GIC_DIST_GICD_ICACTIVER1_t;
6415 #define ALT_GIC_DIST_GICD_ICACTIVER1_RESET 0x00000000
6417 #define ALT_GIC_DIST_GICD_ICACTIVER1_OFST 0x384
6440 #define ALT_GIC_DIST_GICD_ICACTIVER2_FLD_LSB 0
6442 #define ALT_GIC_DIST_GICD_ICACTIVER2_FLD_MSB 31
6444 #define ALT_GIC_DIST_GICD_ICACTIVER2_FLD_WIDTH 32
6446 #define ALT_GIC_DIST_GICD_ICACTIVER2_FLD_SET_MSK 0xffffffff
6448 #define ALT_GIC_DIST_GICD_ICACTIVER2_FLD_CLR_MSK 0x00000000
6450 #define ALT_GIC_DIST_GICD_ICACTIVER2_FLD_RESET 0x0
6452 #define ALT_GIC_DIST_GICD_ICACTIVER2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6454 #define ALT_GIC_DIST_GICD_ICACTIVER2_FLD_SET(value) (((value) << 0) & 0xffffffff)
6456 #ifndef __ASSEMBLY__
6468 struct ALT_GIC_DIST_GICD_ICACTIVER2_s
6470 volatile uint32_t fld : 32;
6474 typedef struct ALT_GIC_DIST_GICD_ICACTIVER2_s ALT_GIC_DIST_GICD_ICACTIVER2_t;
6478 #define ALT_GIC_DIST_GICD_ICACTIVER2_RESET 0x00000000
6480 #define ALT_GIC_DIST_GICD_ICACTIVER2_OFST 0x388
6503 #define ALT_GIC_DIST_GICD_ICACTIVER3_FLD_LSB 0
6505 #define ALT_GIC_DIST_GICD_ICACTIVER3_FLD_MSB 31
6507 #define ALT_GIC_DIST_GICD_ICACTIVER3_FLD_WIDTH 32
6509 #define ALT_GIC_DIST_GICD_ICACTIVER3_FLD_SET_MSK 0xffffffff
6511 #define ALT_GIC_DIST_GICD_ICACTIVER3_FLD_CLR_MSK 0x00000000
6513 #define ALT_GIC_DIST_GICD_ICACTIVER3_FLD_RESET 0x0
6515 #define ALT_GIC_DIST_GICD_ICACTIVER3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6517 #define ALT_GIC_DIST_GICD_ICACTIVER3_FLD_SET(value) (((value) << 0) & 0xffffffff)
6519 #ifndef __ASSEMBLY__
6531 struct ALT_GIC_DIST_GICD_ICACTIVER3_s
6533 volatile uint32_t fld : 32;
6537 typedef struct ALT_GIC_DIST_GICD_ICACTIVER3_s ALT_GIC_DIST_GICD_ICACTIVER3_t;
6541 #define ALT_GIC_DIST_GICD_ICACTIVER3_RESET 0x00000000
6543 #define ALT_GIC_DIST_GICD_ICACTIVER3_OFST 0x38c
6566 #define ALT_GIC_DIST_GICD_ICACTIVER4_FLD_LSB 0
6568 #define ALT_GIC_DIST_GICD_ICACTIVER4_FLD_MSB 31
6570 #define ALT_GIC_DIST_GICD_ICACTIVER4_FLD_WIDTH 32
6572 #define ALT_GIC_DIST_GICD_ICACTIVER4_FLD_SET_MSK 0xffffffff
6574 #define ALT_GIC_DIST_GICD_ICACTIVER4_FLD_CLR_MSK 0x00000000
6576 #define ALT_GIC_DIST_GICD_ICACTIVER4_FLD_RESET 0x0
6578 #define ALT_GIC_DIST_GICD_ICACTIVER4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6580 #define ALT_GIC_DIST_GICD_ICACTIVER4_FLD_SET(value) (((value) << 0) & 0xffffffff)
6582 #ifndef __ASSEMBLY__
6594 struct ALT_GIC_DIST_GICD_ICACTIVER4_s
6596 volatile uint32_t fld : 32;
6600 typedef struct ALT_GIC_DIST_GICD_ICACTIVER4_s ALT_GIC_DIST_GICD_ICACTIVER4_t;
6604 #define ALT_GIC_DIST_GICD_ICACTIVER4_RESET 0x00000000
6606 #define ALT_GIC_DIST_GICD_ICACTIVER4_OFST 0x390
6629 #define ALT_GIC_DIST_GICD_ICACTIVER5_FLD_LSB 0
6631 #define ALT_GIC_DIST_GICD_ICACTIVER5_FLD_MSB 31
6633 #define ALT_GIC_DIST_GICD_ICACTIVER5_FLD_WIDTH 32
6635 #define ALT_GIC_DIST_GICD_ICACTIVER5_FLD_SET_MSK 0xffffffff
6637 #define ALT_GIC_DIST_GICD_ICACTIVER5_FLD_CLR_MSK 0x00000000
6639 #define ALT_GIC_DIST_GICD_ICACTIVER5_FLD_RESET 0x0
6641 #define ALT_GIC_DIST_GICD_ICACTIVER5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6643 #define ALT_GIC_DIST_GICD_ICACTIVER5_FLD_SET(value) (((value) << 0) & 0xffffffff)
6645 #ifndef __ASSEMBLY__
6657 struct ALT_GIC_DIST_GICD_ICACTIVER5_s
6659 volatile uint32_t fld : 32;
6663 typedef struct ALT_GIC_DIST_GICD_ICACTIVER5_s ALT_GIC_DIST_GICD_ICACTIVER5_t;
6667 #define ALT_GIC_DIST_GICD_ICACTIVER5_RESET 0x00000000
6669 #define ALT_GIC_DIST_GICD_ICACTIVER5_OFST 0x394
6692 #define ALT_GIC_DIST_GICD_ICACTIVER6_FLD_LSB 0
6694 #define ALT_GIC_DIST_GICD_ICACTIVER6_FLD_MSB 31
6696 #define ALT_GIC_DIST_GICD_ICACTIVER6_FLD_WIDTH 32
6698 #define ALT_GIC_DIST_GICD_ICACTIVER6_FLD_SET_MSK 0xffffffff
6700 #define ALT_GIC_DIST_GICD_ICACTIVER6_FLD_CLR_MSK 0x00000000
6702 #define ALT_GIC_DIST_GICD_ICACTIVER6_FLD_RESET 0x0
6704 #define ALT_GIC_DIST_GICD_ICACTIVER6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6706 #define ALT_GIC_DIST_GICD_ICACTIVER6_FLD_SET(value) (((value) << 0) & 0xffffffff)
6708 #ifndef __ASSEMBLY__
6720 struct ALT_GIC_DIST_GICD_ICACTIVER6_s
6722 volatile uint32_t fld : 32;
6726 typedef struct ALT_GIC_DIST_GICD_ICACTIVER6_s ALT_GIC_DIST_GICD_ICACTIVER6_t;
6730 #define ALT_GIC_DIST_GICD_ICACTIVER6_RESET 0x00000000
6732 #define ALT_GIC_DIST_GICD_ICACTIVER6_OFST 0x398
6755 #define ALT_GIC_DIST_GICD_ICACTIVER7_FLD_LSB 0
6757 #define ALT_GIC_DIST_GICD_ICACTIVER7_FLD_MSB 31
6759 #define ALT_GIC_DIST_GICD_ICACTIVER7_FLD_WIDTH 32
6761 #define ALT_GIC_DIST_GICD_ICACTIVER7_FLD_SET_MSK 0xffffffff
6763 #define ALT_GIC_DIST_GICD_ICACTIVER7_FLD_CLR_MSK 0x00000000
6765 #define ALT_GIC_DIST_GICD_ICACTIVER7_FLD_RESET 0x0
6767 #define ALT_GIC_DIST_GICD_ICACTIVER7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6769 #define ALT_GIC_DIST_GICD_ICACTIVER7_FLD_SET(value) (((value) << 0) & 0xffffffff)
6771 #ifndef __ASSEMBLY__
6783 struct ALT_GIC_DIST_GICD_ICACTIVER7_s
6785 volatile uint32_t fld : 32;
6789 typedef struct ALT_GIC_DIST_GICD_ICACTIVER7_s ALT_GIC_DIST_GICD_ICACTIVER7_t;
6793 #define ALT_GIC_DIST_GICD_ICACTIVER7_RESET 0x00000000
6795 #define ALT_GIC_DIST_GICD_ICACTIVER7_OFST 0x39c
6818 #define ALT_GIC_DIST_GICD_ICACTIVER8_FLD_LSB 0
6820 #define ALT_GIC_DIST_GICD_ICACTIVER8_FLD_MSB 31
6822 #define ALT_GIC_DIST_GICD_ICACTIVER8_FLD_WIDTH 32
6824 #define ALT_GIC_DIST_GICD_ICACTIVER8_FLD_SET_MSK 0xffffffff
6826 #define ALT_GIC_DIST_GICD_ICACTIVER8_FLD_CLR_MSK 0x00000000
6828 #define ALT_GIC_DIST_GICD_ICACTIVER8_FLD_RESET 0x0
6830 #define ALT_GIC_DIST_GICD_ICACTIVER8_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6832 #define ALT_GIC_DIST_GICD_ICACTIVER8_FLD_SET(value) (((value) << 0) & 0xffffffff)
6834 #ifndef __ASSEMBLY__
6846 struct ALT_GIC_DIST_GICD_ICACTIVER8_s
6848 volatile uint32_t fld : 32;
6852 typedef struct ALT_GIC_DIST_GICD_ICACTIVER8_s ALT_GIC_DIST_GICD_ICACTIVER8_t;
6856 #define ALT_GIC_DIST_GICD_ICACTIVER8_RESET 0x00000000
6858 #define ALT_GIC_DIST_GICD_ICACTIVER8_OFST 0x3a0
6881 #define ALT_GIC_DIST_GICD_ICACTIVER9_FLD_LSB 0
6883 #define ALT_GIC_DIST_GICD_ICACTIVER9_FLD_MSB 31
6885 #define ALT_GIC_DIST_GICD_ICACTIVER9_FLD_WIDTH 32
6887 #define ALT_GIC_DIST_GICD_ICACTIVER9_FLD_SET_MSK 0xffffffff
6889 #define ALT_GIC_DIST_GICD_ICACTIVER9_FLD_CLR_MSK 0x00000000
6891 #define ALT_GIC_DIST_GICD_ICACTIVER9_FLD_RESET 0x0
6893 #define ALT_GIC_DIST_GICD_ICACTIVER9_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6895 #define ALT_GIC_DIST_GICD_ICACTIVER9_FLD_SET(value) (((value) << 0) & 0xffffffff)
6897 #ifndef __ASSEMBLY__
6909 struct ALT_GIC_DIST_GICD_ICACTIVER9_s
6911 volatile uint32_t fld : 32;
6915 typedef struct ALT_GIC_DIST_GICD_ICACTIVER9_s ALT_GIC_DIST_GICD_ICACTIVER9_t;
6919 #define ALT_GIC_DIST_GICD_ICACTIVER9_RESET 0x00000000
6921 #define ALT_GIC_DIST_GICD_ICACTIVER9_OFST 0x3a4
6944 #define ALT_GIC_DIST_GICD_ICACTIVER10_FLD_LSB 0
6946 #define ALT_GIC_DIST_GICD_ICACTIVER10_FLD_MSB 31
6948 #define ALT_GIC_DIST_GICD_ICACTIVER10_FLD_WIDTH 32
6950 #define ALT_GIC_DIST_GICD_ICACTIVER10_FLD_SET_MSK 0xffffffff
6952 #define ALT_GIC_DIST_GICD_ICACTIVER10_FLD_CLR_MSK 0x00000000
6954 #define ALT_GIC_DIST_GICD_ICACTIVER10_FLD_RESET 0x0
6956 #define ALT_GIC_DIST_GICD_ICACTIVER10_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6958 #define ALT_GIC_DIST_GICD_ICACTIVER10_FLD_SET(value) (((value) << 0) & 0xffffffff)
6960 #ifndef __ASSEMBLY__
6972 struct ALT_GIC_DIST_GICD_ICACTIVER10_s
6974 volatile uint32_t fld : 32;
6978 typedef struct ALT_GIC_DIST_GICD_ICACTIVER10_s ALT_GIC_DIST_GICD_ICACTIVER10_t;
6982 #define ALT_GIC_DIST_GICD_ICACTIVER10_RESET 0x00000000
6984 #define ALT_GIC_DIST_GICD_ICACTIVER10_OFST 0x3a8
7007 #define ALT_GIC_DIST_GICD_ICACTIVER11_FLD_LSB 0
7009 #define ALT_GIC_DIST_GICD_ICACTIVER11_FLD_MSB 31
7011 #define ALT_GIC_DIST_GICD_ICACTIVER11_FLD_WIDTH 32
7013 #define ALT_GIC_DIST_GICD_ICACTIVER11_FLD_SET_MSK 0xffffffff
7015 #define ALT_GIC_DIST_GICD_ICACTIVER11_FLD_CLR_MSK 0x00000000
7017 #define ALT_GIC_DIST_GICD_ICACTIVER11_FLD_RESET 0x0
7019 #define ALT_GIC_DIST_GICD_ICACTIVER11_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7021 #define ALT_GIC_DIST_GICD_ICACTIVER11_FLD_SET(value) (((value) << 0) & 0xffffffff)
7023 #ifndef __ASSEMBLY__
7035 struct ALT_GIC_DIST_GICD_ICACTIVER11_s
7037 volatile uint32_t fld : 32;
7041 typedef struct ALT_GIC_DIST_GICD_ICACTIVER11_s ALT_GIC_DIST_GICD_ICACTIVER11_t;
7045 #define ALT_GIC_DIST_GICD_ICACTIVER11_RESET 0x00000000
7047 #define ALT_GIC_DIST_GICD_ICACTIVER11_OFST 0x3ac
7070 #define ALT_GIC_DIST_GICD_ICACTIVER12_FLD_LSB 0
7072 #define ALT_GIC_DIST_GICD_ICACTIVER12_FLD_MSB 31
7074 #define ALT_GIC_DIST_GICD_ICACTIVER12_FLD_WIDTH 32
7076 #define ALT_GIC_DIST_GICD_ICACTIVER12_FLD_SET_MSK 0xffffffff
7078 #define ALT_GIC_DIST_GICD_ICACTIVER12_FLD_CLR_MSK 0x00000000
7080 #define ALT_GIC_DIST_GICD_ICACTIVER12_FLD_RESET 0x0
7082 #define ALT_GIC_DIST_GICD_ICACTIVER12_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7084 #define ALT_GIC_DIST_GICD_ICACTIVER12_FLD_SET(value) (((value) << 0) & 0xffffffff)
7086 #ifndef __ASSEMBLY__
7098 struct ALT_GIC_DIST_GICD_ICACTIVER12_s
7100 volatile uint32_t fld : 32;
7104 typedef struct ALT_GIC_DIST_GICD_ICACTIVER12_s ALT_GIC_DIST_GICD_ICACTIVER12_t;
7108 #define ALT_GIC_DIST_GICD_ICACTIVER12_RESET 0x00000000
7110 #define ALT_GIC_DIST_GICD_ICACTIVER12_OFST 0x3b0
7133 #define ALT_GIC_DIST_GICD_ICACTIVER13_FLD_LSB 0
7135 #define ALT_GIC_DIST_GICD_ICACTIVER13_FLD_MSB 31
7137 #define ALT_GIC_DIST_GICD_ICACTIVER13_FLD_WIDTH 32
7139 #define ALT_GIC_DIST_GICD_ICACTIVER13_FLD_SET_MSK 0xffffffff
7141 #define ALT_GIC_DIST_GICD_ICACTIVER13_FLD_CLR_MSK 0x00000000
7143 #define ALT_GIC_DIST_GICD_ICACTIVER13_FLD_RESET 0x0
7145 #define ALT_GIC_DIST_GICD_ICACTIVER13_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7147 #define ALT_GIC_DIST_GICD_ICACTIVER13_FLD_SET(value) (((value) << 0) & 0xffffffff)
7149 #ifndef __ASSEMBLY__
7161 struct ALT_GIC_DIST_GICD_ICACTIVER13_s
7163 volatile uint32_t fld : 32;
7167 typedef struct ALT_GIC_DIST_GICD_ICACTIVER13_s ALT_GIC_DIST_GICD_ICACTIVER13_t;
7171 #define ALT_GIC_DIST_GICD_ICACTIVER13_RESET 0x00000000
7173 #define ALT_GIC_DIST_GICD_ICACTIVER13_OFST 0x3b4
7196 #define ALT_GIC_DIST_GICD_ICACTIVER14_FLD_LSB 0
7198 #define ALT_GIC_DIST_GICD_ICACTIVER14_FLD_MSB 31
7200 #define ALT_GIC_DIST_GICD_ICACTIVER14_FLD_WIDTH 32
7202 #define ALT_GIC_DIST_GICD_ICACTIVER14_FLD_SET_MSK 0xffffffff
7204 #define ALT_GIC_DIST_GICD_ICACTIVER14_FLD_CLR_MSK 0x00000000
7206 #define ALT_GIC_DIST_GICD_ICACTIVER14_FLD_RESET 0x0
7208 #define ALT_GIC_DIST_GICD_ICACTIVER14_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7210 #define ALT_GIC_DIST_GICD_ICACTIVER14_FLD_SET(value) (((value) << 0) & 0xffffffff)
7212 #ifndef __ASSEMBLY__
7224 struct ALT_GIC_DIST_GICD_ICACTIVER14_s
7226 volatile uint32_t fld : 32;
7230 typedef struct ALT_GIC_DIST_GICD_ICACTIVER14_s ALT_GIC_DIST_GICD_ICACTIVER14_t;
7234 #define ALT_GIC_DIST_GICD_ICACTIVER14_RESET 0x00000000
7236 #define ALT_GIC_DIST_GICD_ICACTIVER14_OFST 0x3b8
7259 #define ALT_GIC_DIST_GICD_ICACTIVER15_FLD_LSB 0
7261 #define ALT_GIC_DIST_GICD_ICACTIVER15_FLD_MSB 31
7263 #define ALT_GIC_DIST_GICD_ICACTIVER15_FLD_WIDTH 32
7265 #define ALT_GIC_DIST_GICD_ICACTIVER15_FLD_SET_MSK 0xffffffff
7267 #define ALT_GIC_DIST_GICD_ICACTIVER15_FLD_CLR_MSK 0x00000000
7269 #define ALT_GIC_DIST_GICD_ICACTIVER15_FLD_RESET 0x0
7271 #define ALT_GIC_DIST_GICD_ICACTIVER15_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7273 #define ALT_GIC_DIST_GICD_ICACTIVER15_FLD_SET(value) (((value) << 0) & 0xffffffff)
7275 #ifndef __ASSEMBLY__
7287 struct ALT_GIC_DIST_GICD_ICACTIVER15_s
7289 volatile uint32_t fld : 32;
7293 typedef struct ALT_GIC_DIST_GICD_ICACTIVER15_s ALT_GIC_DIST_GICD_ICACTIVER15_t;
7297 #define ALT_GIC_DIST_GICD_ICACTIVER15_RESET 0x00000000
7299 #define ALT_GIC_DIST_GICD_ICACTIVER15_OFST 0x3bc
7322 #define ALT_GIC_DIST_GICD_IPRIORITYR0_FLD_LSB 0
7324 #define ALT_GIC_DIST_GICD_IPRIORITYR0_FLD_MSB 31
7326 #define ALT_GIC_DIST_GICD_IPRIORITYR0_FLD_WIDTH 32
7328 #define ALT_GIC_DIST_GICD_IPRIORITYR0_FLD_SET_MSK 0xffffffff
7330 #define ALT_GIC_DIST_GICD_IPRIORITYR0_FLD_CLR_MSK 0x00000000
7332 #define ALT_GIC_DIST_GICD_IPRIORITYR0_FLD_RESET 0x0
7334 #define ALT_GIC_DIST_GICD_IPRIORITYR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7336 #define ALT_GIC_DIST_GICD_IPRIORITYR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
7338 #ifndef __ASSEMBLY__
7350 struct ALT_GIC_DIST_GICD_IPRIORITYR0_s
7352 volatile uint32_t fld : 32;
7356 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR0_s ALT_GIC_DIST_GICD_IPRIORITYR0_t;
7360 #define ALT_GIC_DIST_GICD_IPRIORITYR0_RESET 0x00000000
7362 #define ALT_GIC_DIST_GICD_IPRIORITYR0_OFST 0x400
7385 #define ALT_GIC_DIST_GICD_IPRIORITYR1_FLD_LSB 0
7387 #define ALT_GIC_DIST_GICD_IPRIORITYR1_FLD_MSB 31
7389 #define ALT_GIC_DIST_GICD_IPRIORITYR1_FLD_WIDTH 32
7391 #define ALT_GIC_DIST_GICD_IPRIORITYR1_FLD_SET_MSK 0xffffffff
7393 #define ALT_GIC_DIST_GICD_IPRIORITYR1_FLD_CLR_MSK 0x00000000
7395 #define ALT_GIC_DIST_GICD_IPRIORITYR1_FLD_RESET 0x0
7397 #define ALT_GIC_DIST_GICD_IPRIORITYR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7399 #define ALT_GIC_DIST_GICD_IPRIORITYR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
7401 #ifndef __ASSEMBLY__
7413 struct ALT_GIC_DIST_GICD_IPRIORITYR1_s
7415 volatile uint32_t fld : 32;
7419 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR1_s ALT_GIC_DIST_GICD_IPRIORITYR1_t;
7423 #define ALT_GIC_DIST_GICD_IPRIORITYR1_RESET 0x00000000
7425 #define ALT_GIC_DIST_GICD_IPRIORITYR1_OFST 0x404
7448 #define ALT_GIC_DIST_GICD_IPRIORITYR2_FLD_LSB 0
7450 #define ALT_GIC_DIST_GICD_IPRIORITYR2_FLD_MSB 31
7452 #define ALT_GIC_DIST_GICD_IPRIORITYR2_FLD_WIDTH 32
7454 #define ALT_GIC_DIST_GICD_IPRIORITYR2_FLD_SET_MSK 0xffffffff
7456 #define ALT_GIC_DIST_GICD_IPRIORITYR2_FLD_CLR_MSK 0x00000000
7458 #define ALT_GIC_DIST_GICD_IPRIORITYR2_FLD_RESET 0x0
7460 #define ALT_GIC_DIST_GICD_IPRIORITYR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7462 #define ALT_GIC_DIST_GICD_IPRIORITYR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
7464 #ifndef __ASSEMBLY__
7476 struct ALT_GIC_DIST_GICD_IPRIORITYR2_s
7478 volatile uint32_t fld : 32;
7482 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR2_s ALT_GIC_DIST_GICD_IPRIORITYR2_t;
7486 #define ALT_GIC_DIST_GICD_IPRIORITYR2_RESET 0x00000000
7488 #define ALT_GIC_DIST_GICD_IPRIORITYR2_OFST 0x408
7511 #define ALT_GIC_DIST_GICD_IPRIORITYR3_FLD_LSB 0
7513 #define ALT_GIC_DIST_GICD_IPRIORITYR3_FLD_MSB 31
7515 #define ALT_GIC_DIST_GICD_IPRIORITYR3_FLD_WIDTH 32
7517 #define ALT_GIC_DIST_GICD_IPRIORITYR3_FLD_SET_MSK 0xffffffff
7519 #define ALT_GIC_DIST_GICD_IPRIORITYR3_FLD_CLR_MSK 0x00000000
7521 #define ALT_GIC_DIST_GICD_IPRIORITYR3_FLD_RESET 0x0
7523 #define ALT_GIC_DIST_GICD_IPRIORITYR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7525 #define ALT_GIC_DIST_GICD_IPRIORITYR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
7527 #ifndef __ASSEMBLY__
7539 struct ALT_GIC_DIST_GICD_IPRIORITYR3_s
7541 volatile uint32_t fld : 32;
7545 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR3_s ALT_GIC_DIST_GICD_IPRIORITYR3_t;
7549 #define ALT_GIC_DIST_GICD_IPRIORITYR3_RESET 0x00000000
7551 #define ALT_GIC_DIST_GICD_IPRIORITYR3_OFST 0x40c
7574 #define ALT_GIC_DIST_GICD_IPRIORITYR4_FLD_LSB 0
7576 #define ALT_GIC_DIST_GICD_IPRIORITYR4_FLD_MSB 31
7578 #define ALT_GIC_DIST_GICD_IPRIORITYR4_FLD_WIDTH 32
7580 #define ALT_GIC_DIST_GICD_IPRIORITYR4_FLD_SET_MSK 0xffffffff
7582 #define ALT_GIC_DIST_GICD_IPRIORITYR4_FLD_CLR_MSK 0x00000000
7584 #define ALT_GIC_DIST_GICD_IPRIORITYR4_FLD_RESET 0x0
7586 #define ALT_GIC_DIST_GICD_IPRIORITYR4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7588 #define ALT_GIC_DIST_GICD_IPRIORITYR4_FLD_SET(value) (((value) << 0) & 0xffffffff)
7590 #ifndef __ASSEMBLY__
7602 struct ALT_GIC_DIST_GICD_IPRIORITYR4_s
7604 volatile uint32_t fld : 32;
7608 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR4_s ALT_GIC_DIST_GICD_IPRIORITYR4_t;
7612 #define ALT_GIC_DIST_GICD_IPRIORITYR4_RESET 0x00000000
7614 #define ALT_GIC_DIST_GICD_IPRIORITYR4_OFST 0x410
7637 #define ALT_GIC_DIST_GICD_IPRIORITYR5_FLD_LSB 0
7639 #define ALT_GIC_DIST_GICD_IPRIORITYR5_FLD_MSB 31
7641 #define ALT_GIC_DIST_GICD_IPRIORITYR5_FLD_WIDTH 32
7643 #define ALT_GIC_DIST_GICD_IPRIORITYR5_FLD_SET_MSK 0xffffffff
7645 #define ALT_GIC_DIST_GICD_IPRIORITYR5_FLD_CLR_MSK 0x00000000
7647 #define ALT_GIC_DIST_GICD_IPRIORITYR5_FLD_RESET 0x0
7649 #define ALT_GIC_DIST_GICD_IPRIORITYR5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7651 #define ALT_GIC_DIST_GICD_IPRIORITYR5_FLD_SET(value) (((value) << 0) & 0xffffffff)
7653 #ifndef __ASSEMBLY__
7665 struct ALT_GIC_DIST_GICD_IPRIORITYR5_s
7667 volatile uint32_t fld : 32;
7671 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR5_s ALT_GIC_DIST_GICD_IPRIORITYR5_t;
7675 #define ALT_GIC_DIST_GICD_IPRIORITYR5_RESET 0x00000000
7677 #define ALT_GIC_DIST_GICD_IPRIORITYR5_OFST 0x414
7700 #define ALT_GIC_DIST_GICD_IPRIORITYR6_FLD_LSB 0
7702 #define ALT_GIC_DIST_GICD_IPRIORITYR6_FLD_MSB 31
7704 #define ALT_GIC_DIST_GICD_IPRIORITYR6_FLD_WIDTH 32
7706 #define ALT_GIC_DIST_GICD_IPRIORITYR6_FLD_SET_MSK 0xffffffff
7708 #define ALT_GIC_DIST_GICD_IPRIORITYR6_FLD_CLR_MSK 0x00000000
7710 #define ALT_GIC_DIST_GICD_IPRIORITYR6_FLD_RESET 0x0
7712 #define ALT_GIC_DIST_GICD_IPRIORITYR6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7714 #define ALT_GIC_DIST_GICD_IPRIORITYR6_FLD_SET(value) (((value) << 0) & 0xffffffff)
7716 #ifndef __ASSEMBLY__
7728 struct ALT_GIC_DIST_GICD_IPRIORITYR6_s
7730 volatile uint32_t fld : 32;
7734 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR6_s ALT_GIC_DIST_GICD_IPRIORITYR6_t;
7738 #define ALT_GIC_DIST_GICD_IPRIORITYR6_RESET 0x00000000
7740 #define ALT_GIC_DIST_GICD_IPRIORITYR6_OFST 0x418
7763 #define ALT_GIC_DIST_GICD_IPRIORITYR7_FLD_LSB 0
7765 #define ALT_GIC_DIST_GICD_IPRIORITYR7_FLD_MSB 31
7767 #define ALT_GIC_DIST_GICD_IPRIORITYR7_FLD_WIDTH 32
7769 #define ALT_GIC_DIST_GICD_IPRIORITYR7_FLD_SET_MSK 0xffffffff
7771 #define ALT_GIC_DIST_GICD_IPRIORITYR7_FLD_CLR_MSK 0x00000000
7773 #define ALT_GIC_DIST_GICD_IPRIORITYR7_FLD_RESET 0x0
7775 #define ALT_GIC_DIST_GICD_IPRIORITYR7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7777 #define ALT_GIC_DIST_GICD_IPRIORITYR7_FLD_SET(value) (((value) << 0) & 0xffffffff)
7779 #ifndef __ASSEMBLY__
7791 struct ALT_GIC_DIST_GICD_IPRIORITYR7_s
7793 volatile uint32_t fld : 32;
7797 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR7_s ALT_GIC_DIST_GICD_IPRIORITYR7_t;
7801 #define ALT_GIC_DIST_GICD_IPRIORITYR7_RESET 0x00000000
7803 #define ALT_GIC_DIST_GICD_IPRIORITYR7_OFST 0x41c
7826 #define ALT_GIC_DIST_GICD_IPRIORITYR8_FLD_LSB 0
7828 #define ALT_GIC_DIST_GICD_IPRIORITYR8_FLD_MSB 31
7830 #define ALT_GIC_DIST_GICD_IPRIORITYR8_FLD_WIDTH 32
7832 #define ALT_GIC_DIST_GICD_IPRIORITYR8_FLD_SET_MSK 0xffffffff
7834 #define ALT_GIC_DIST_GICD_IPRIORITYR8_FLD_CLR_MSK 0x00000000
7836 #define ALT_GIC_DIST_GICD_IPRIORITYR8_FLD_RESET 0x0
7838 #define ALT_GIC_DIST_GICD_IPRIORITYR8_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7840 #define ALT_GIC_DIST_GICD_IPRIORITYR8_FLD_SET(value) (((value) << 0) & 0xffffffff)
7842 #ifndef __ASSEMBLY__
7854 struct ALT_GIC_DIST_GICD_IPRIORITYR8_s
7856 volatile uint32_t fld : 32;
7860 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR8_s ALT_GIC_DIST_GICD_IPRIORITYR8_t;
7864 #define ALT_GIC_DIST_GICD_IPRIORITYR8_RESET 0x00000000
7866 #define ALT_GIC_DIST_GICD_IPRIORITYR8_OFST 0x420
7889 #define ALT_GIC_DIST_GICD_IPRIORITYR9_FLD_LSB 0
7891 #define ALT_GIC_DIST_GICD_IPRIORITYR9_FLD_MSB 31
7893 #define ALT_GIC_DIST_GICD_IPRIORITYR9_FLD_WIDTH 32
7895 #define ALT_GIC_DIST_GICD_IPRIORITYR9_FLD_SET_MSK 0xffffffff
7897 #define ALT_GIC_DIST_GICD_IPRIORITYR9_FLD_CLR_MSK 0x00000000
7899 #define ALT_GIC_DIST_GICD_IPRIORITYR9_FLD_RESET 0x0
7901 #define ALT_GIC_DIST_GICD_IPRIORITYR9_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7903 #define ALT_GIC_DIST_GICD_IPRIORITYR9_FLD_SET(value) (((value) << 0) & 0xffffffff)
7905 #ifndef __ASSEMBLY__
7917 struct ALT_GIC_DIST_GICD_IPRIORITYR9_s
7919 volatile uint32_t fld : 32;
7923 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR9_s ALT_GIC_DIST_GICD_IPRIORITYR9_t;
7927 #define ALT_GIC_DIST_GICD_IPRIORITYR9_RESET 0x00000000
7929 #define ALT_GIC_DIST_GICD_IPRIORITYR9_OFST 0x424
7952 #define ALT_GIC_DIST_GICD_IPRIORITYR10_FLD_LSB 0
7954 #define ALT_GIC_DIST_GICD_IPRIORITYR10_FLD_MSB 31
7956 #define ALT_GIC_DIST_GICD_IPRIORITYR10_FLD_WIDTH 32
7958 #define ALT_GIC_DIST_GICD_IPRIORITYR10_FLD_SET_MSK 0xffffffff
7960 #define ALT_GIC_DIST_GICD_IPRIORITYR10_FLD_CLR_MSK 0x00000000
7962 #define ALT_GIC_DIST_GICD_IPRIORITYR10_FLD_RESET 0x0
7964 #define ALT_GIC_DIST_GICD_IPRIORITYR10_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7966 #define ALT_GIC_DIST_GICD_IPRIORITYR10_FLD_SET(value) (((value) << 0) & 0xffffffff)
7968 #ifndef __ASSEMBLY__
7980 struct ALT_GIC_DIST_GICD_IPRIORITYR10_s
7982 volatile uint32_t fld : 32;
7986 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR10_s ALT_GIC_DIST_GICD_IPRIORITYR10_t;
7990 #define ALT_GIC_DIST_GICD_IPRIORITYR10_RESET 0x00000000
7992 #define ALT_GIC_DIST_GICD_IPRIORITYR10_OFST 0x428
8015 #define ALT_GIC_DIST_GICD_IPRIORITYR11_FLD_LSB 0
8017 #define ALT_GIC_DIST_GICD_IPRIORITYR11_FLD_MSB 31
8019 #define ALT_GIC_DIST_GICD_IPRIORITYR11_FLD_WIDTH 32
8021 #define ALT_GIC_DIST_GICD_IPRIORITYR11_FLD_SET_MSK 0xffffffff
8023 #define ALT_GIC_DIST_GICD_IPRIORITYR11_FLD_CLR_MSK 0x00000000
8025 #define ALT_GIC_DIST_GICD_IPRIORITYR11_FLD_RESET 0x0
8027 #define ALT_GIC_DIST_GICD_IPRIORITYR11_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8029 #define ALT_GIC_DIST_GICD_IPRIORITYR11_FLD_SET(value) (((value) << 0) & 0xffffffff)
8031 #ifndef __ASSEMBLY__
8043 struct ALT_GIC_DIST_GICD_IPRIORITYR11_s
8045 volatile uint32_t fld : 32;
8049 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR11_s ALT_GIC_DIST_GICD_IPRIORITYR11_t;
8053 #define ALT_GIC_DIST_GICD_IPRIORITYR11_RESET 0x00000000
8055 #define ALT_GIC_DIST_GICD_IPRIORITYR11_OFST 0x42c
8078 #define ALT_GIC_DIST_GICD_IPRIORITYR12_FLD_LSB 0
8080 #define ALT_GIC_DIST_GICD_IPRIORITYR12_FLD_MSB 31
8082 #define ALT_GIC_DIST_GICD_IPRIORITYR12_FLD_WIDTH 32
8084 #define ALT_GIC_DIST_GICD_IPRIORITYR12_FLD_SET_MSK 0xffffffff
8086 #define ALT_GIC_DIST_GICD_IPRIORITYR12_FLD_CLR_MSK 0x00000000
8088 #define ALT_GIC_DIST_GICD_IPRIORITYR12_FLD_RESET 0x0
8090 #define ALT_GIC_DIST_GICD_IPRIORITYR12_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8092 #define ALT_GIC_DIST_GICD_IPRIORITYR12_FLD_SET(value) (((value) << 0) & 0xffffffff)
8094 #ifndef __ASSEMBLY__
8106 struct ALT_GIC_DIST_GICD_IPRIORITYR12_s
8108 volatile uint32_t fld : 32;
8112 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR12_s ALT_GIC_DIST_GICD_IPRIORITYR12_t;
8116 #define ALT_GIC_DIST_GICD_IPRIORITYR12_RESET 0x00000000
8118 #define ALT_GIC_DIST_GICD_IPRIORITYR12_OFST 0x430
8141 #define ALT_GIC_DIST_GICD_IPRIORITYR13_FLD_LSB 0
8143 #define ALT_GIC_DIST_GICD_IPRIORITYR13_FLD_MSB 31
8145 #define ALT_GIC_DIST_GICD_IPRIORITYR13_FLD_WIDTH 32
8147 #define ALT_GIC_DIST_GICD_IPRIORITYR13_FLD_SET_MSK 0xffffffff
8149 #define ALT_GIC_DIST_GICD_IPRIORITYR13_FLD_CLR_MSK 0x00000000
8151 #define ALT_GIC_DIST_GICD_IPRIORITYR13_FLD_RESET 0x0
8153 #define ALT_GIC_DIST_GICD_IPRIORITYR13_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8155 #define ALT_GIC_DIST_GICD_IPRIORITYR13_FLD_SET(value) (((value) << 0) & 0xffffffff)
8157 #ifndef __ASSEMBLY__
8169 struct ALT_GIC_DIST_GICD_IPRIORITYR13_s
8171 volatile uint32_t fld : 32;
8175 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR13_s ALT_GIC_DIST_GICD_IPRIORITYR13_t;
8179 #define ALT_GIC_DIST_GICD_IPRIORITYR13_RESET 0x00000000
8181 #define ALT_GIC_DIST_GICD_IPRIORITYR13_OFST 0x434
8204 #define ALT_GIC_DIST_GICD_IPRIORITYR14_FLD_LSB 0
8206 #define ALT_GIC_DIST_GICD_IPRIORITYR14_FLD_MSB 31
8208 #define ALT_GIC_DIST_GICD_IPRIORITYR14_FLD_WIDTH 32
8210 #define ALT_GIC_DIST_GICD_IPRIORITYR14_FLD_SET_MSK 0xffffffff
8212 #define ALT_GIC_DIST_GICD_IPRIORITYR14_FLD_CLR_MSK 0x00000000
8214 #define ALT_GIC_DIST_GICD_IPRIORITYR14_FLD_RESET 0x0
8216 #define ALT_GIC_DIST_GICD_IPRIORITYR14_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8218 #define ALT_GIC_DIST_GICD_IPRIORITYR14_FLD_SET(value) (((value) << 0) & 0xffffffff)
8220 #ifndef __ASSEMBLY__
8232 struct ALT_GIC_DIST_GICD_IPRIORITYR14_s
8234 volatile uint32_t fld : 32;
8238 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR14_s ALT_GIC_DIST_GICD_IPRIORITYR14_t;
8242 #define ALT_GIC_DIST_GICD_IPRIORITYR14_RESET 0x00000000
8244 #define ALT_GIC_DIST_GICD_IPRIORITYR14_OFST 0x438
8267 #define ALT_GIC_DIST_GICD_IPRIORITYR15_FLD_LSB 0
8269 #define ALT_GIC_DIST_GICD_IPRIORITYR15_FLD_MSB 31
8271 #define ALT_GIC_DIST_GICD_IPRIORITYR15_FLD_WIDTH 32
8273 #define ALT_GIC_DIST_GICD_IPRIORITYR15_FLD_SET_MSK 0xffffffff
8275 #define ALT_GIC_DIST_GICD_IPRIORITYR15_FLD_CLR_MSK 0x00000000
8277 #define ALT_GIC_DIST_GICD_IPRIORITYR15_FLD_RESET 0x0
8279 #define ALT_GIC_DIST_GICD_IPRIORITYR15_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8281 #define ALT_GIC_DIST_GICD_IPRIORITYR15_FLD_SET(value) (((value) << 0) & 0xffffffff)
8283 #ifndef __ASSEMBLY__
8295 struct ALT_GIC_DIST_GICD_IPRIORITYR15_s
8297 volatile uint32_t fld : 32;
8301 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR15_s ALT_GIC_DIST_GICD_IPRIORITYR15_t;
8305 #define ALT_GIC_DIST_GICD_IPRIORITYR15_RESET 0x00000000
8307 #define ALT_GIC_DIST_GICD_IPRIORITYR15_OFST 0x43c
8330 #define ALT_GIC_DIST_GICD_IPRIORITYR16_FLD_LSB 0
8332 #define ALT_GIC_DIST_GICD_IPRIORITYR16_FLD_MSB 31
8334 #define ALT_GIC_DIST_GICD_IPRIORITYR16_FLD_WIDTH 32
8336 #define ALT_GIC_DIST_GICD_IPRIORITYR16_FLD_SET_MSK 0xffffffff
8338 #define ALT_GIC_DIST_GICD_IPRIORITYR16_FLD_CLR_MSK 0x00000000
8340 #define ALT_GIC_DIST_GICD_IPRIORITYR16_FLD_RESET 0x0
8342 #define ALT_GIC_DIST_GICD_IPRIORITYR16_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8344 #define ALT_GIC_DIST_GICD_IPRIORITYR16_FLD_SET(value) (((value) << 0) & 0xffffffff)
8346 #ifndef __ASSEMBLY__
8358 struct ALT_GIC_DIST_GICD_IPRIORITYR16_s
8360 volatile uint32_t fld : 32;
8364 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR16_s ALT_GIC_DIST_GICD_IPRIORITYR16_t;
8368 #define ALT_GIC_DIST_GICD_IPRIORITYR16_RESET 0x00000000
8370 #define ALT_GIC_DIST_GICD_IPRIORITYR16_OFST 0x440
8393 #define ALT_GIC_DIST_GICD_IPRIORITYR17_FLD_LSB 0
8395 #define ALT_GIC_DIST_GICD_IPRIORITYR17_FLD_MSB 31
8397 #define ALT_GIC_DIST_GICD_IPRIORITYR17_FLD_WIDTH 32
8399 #define ALT_GIC_DIST_GICD_IPRIORITYR17_FLD_SET_MSK 0xffffffff
8401 #define ALT_GIC_DIST_GICD_IPRIORITYR17_FLD_CLR_MSK 0x00000000
8403 #define ALT_GIC_DIST_GICD_IPRIORITYR17_FLD_RESET 0x0
8405 #define ALT_GIC_DIST_GICD_IPRIORITYR17_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8407 #define ALT_GIC_DIST_GICD_IPRIORITYR17_FLD_SET(value) (((value) << 0) & 0xffffffff)
8409 #ifndef __ASSEMBLY__
8421 struct ALT_GIC_DIST_GICD_IPRIORITYR17_s
8423 volatile uint32_t fld : 32;
8427 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR17_s ALT_GIC_DIST_GICD_IPRIORITYR17_t;
8431 #define ALT_GIC_DIST_GICD_IPRIORITYR17_RESET 0x00000000
8433 #define ALT_GIC_DIST_GICD_IPRIORITYR17_OFST 0x444
8456 #define ALT_GIC_DIST_GICD_IPRIORITYR18_FLD_LSB 0
8458 #define ALT_GIC_DIST_GICD_IPRIORITYR18_FLD_MSB 31
8460 #define ALT_GIC_DIST_GICD_IPRIORITYR18_FLD_WIDTH 32
8462 #define ALT_GIC_DIST_GICD_IPRIORITYR18_FLD_SET_MSK 0xffffffff
8464 #define ALT_GIC_DIST_GICD_IPRIORITYR18_FLD_CLR_MSK 0x00000000
8466 #define ALT_GIC_DIST_GICD_IPRIORITYR18_FLD_RESET 0x0
8468 #define ALT_GIC_DIST_GICD_IPRIORITYR18_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8470 #define ALT_GIC_DIST_GICD_IPRIORITYR18_FLD_SET(value) (((value) << 0) & 0xffffffff)
8472 #ifndef __ASSEMBLY__
8484 struct ALT_GIC_DIST_GICD_IPRIORITYR18_s
8486 volatile uint32_t fld : 32;
8490 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR18_s ALT_GIC_DIST_GICD_IPRIORITYR18_t;
8494 #define ALT_GIC_DIST_GICD_IPRIORITYR18_RESET 0x00000000
8496 #define ALT_GIC_DIST_GICD_IPRIORITYR18_OFST 0x448
8519 #define ALT_GIC_DIST_GICD_IPRIORITYR19_FLD_LSB 0
8521 #define ALT_GIC_DIST_GICD_IPRIORITYR19_FLD_MSB 31
8523 #define ALT_GIC_DIST_GICD_IPRIORITYR19_FLD_WIDTH 32
8525 #define ALT_GIC_DIST_GICD_IPRIORITYR19_FLD_SET_MSK 0xffffffff
8527 #define ALT_GIC_DIST_GICD_IPRIORITYR19_FLD_CLR_MSK 0x00000000
8529 #define ALT_GIC_DIST_GICD_IPRIORITYR19_FLD_RESET 0x0
8531 #define ALT_GIC_DIST_GICD_IPRIORITYR19_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8533 #define ALT_GIC_DIST_GICD_IPRIORITYR19_FLD_SET(value) (((value) << 0) & 0xffffffff)
8535 #ifndef __ASSEMBLY__
8547 struct ALT_GIC_DIST_GICD_IPRIORITYR19_s
8549 volatile uint32_t fld : 32;
8553 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR19_s ALT_GIC_DIST_GICD_IPRIORITYR19_t;
8557 #define ALT_GIC_DIST_GICD_IPRIORITYR19_RESET 0x00000000
8559 #define ALT_GIC_DIST_GICD_IPRIORITYR19_OFST 0x44c
8582 #define ALT_GIC_DIST_GICD_IPRIORITYR20_FLD_LSB 0
8584 #define ALT_GIC_DIST_GICD_IPRIORITYR20_FLD_MSB 31
8586 #define ALT_GIC_DIST_GICD_IPRIORITYR20_FLD_WIDTH 32
8588 #define ALT_GIC_DIST_GICD_IPRIORITYR20_FLD_SET_MSK 0xffffffff
8590 #define ALT_GIC_DIST_GICD_IPRIORITYR20_FLD_CLR_MSK 0x00000000
8592 #define ALT_GIC_DIST_GICD_IPRIORITYR20_FLD_RESET 0x0
8594 #define ALT_GIC_DIST_GICD_IPRIORITYR20_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8596 #define ALT_GIC_DIST_GICD_IPRIORITYR20_FLD_SET(value) (((value) << 0) & 0xffffffff)
8598 #ifndef __ASSEMBLY__
8610 struct ALT_GIC_DIST_GICD_IPRIORITYR20_s
8612 volatile uint32_t fld : 32;
8616 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR20_s ALT_GIC_DIST_GICD_IPRIORITYR20_t;
8620 #define ALT_GIC_DIST_GICD_IPRIORITYR20_RESET 0x00000000
8622 #define ALT_GIC_DIST_GICD_IPRIORITYR20_OFST 0x450
8645 #define ALT_GIC_DIST_GICD_IPRIORITYR21_FLD_LSB 0
8647 #define ALT_GIC_DIST_GICD_IPRIORITYR21_FLD_MSB 31
8649 #define ALT_GIC_DIST_GICD_IPRIORITYR21_FLD_WIDTH 32
8651 #define ALT_GIC_DIST_GICD_IPRIORITYR21_FLD_SET_MSK 0xffffffff
8653 #define ALT_GIC_DIST_GICD_IPRIORITYR21_FLD_CLR_MSK 0x00000000
8655 #define ALT_GIC_DIST_GICD_IPRIORITYR21_FLD_RESET 0x0
8657 #define ALT_GIC_DIST_GICD_IPRIORITYR21_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8659 #define ALT_GIC_DIST_GICD_IPRIORITYR21_FLD_SET(value) (((value) << 0) & 0xffffffff)
8661 #ifndef __ASSEMBLY__
8673 struct ALT_GIC_DIST_GICD_IPRIORITYR21_s
8675 volatile uint32_t fld : 32;
8679 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR21_s ALT_GIC_DIST_GICD_IPRIORITYR21_t;
8683 #define ALT_GIC_DIST_GICD_IPRIORITYR21_RESET 0x00000000
8685 #define ALT_GIC_DIST_GICD_IPRIORITYR21_OFST 0x454
8708 #define ALT_GIC_DIST_GICD_IPRIORITYR22_FLD_LSB 0
8710 #define ALT_GIC_DIST_GICD_IPRIORITYR22_FLD_MSB 31
8712 #define ALT_GIC_DIST_GICD_IPRIORITYR22_FLD_WIDTH 32
8714 #define ALT_GIC_DIST_GICD_IPRIORITYR22_FLD_SET_MSK 0xffffffff
8716 #define ALT_GIC_DIST_GICD_IPRIORITYR22_FLD_CLR_MSK 0x00000000
8718 #define ALT_GIC_DIST_GICD_IPRIORITYR22_FLD_RESET 0x0
8720 #define ALT_GIC_DIST_GICD_IPRIORITYR22_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8722 #define ALT_GIC_DIST_GICD_IPRIORITYR22_FLD_SET(value) (((value) << 0) & 0xffffffff)
8724 #ifndef __ASSEMBLY__
8736 struct ALT_GIC_DIST_GICD_IPRIORITYR22_s
8738 volatile uint32_t fld : 32;
8742 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR22_s ALT_GIC_DIST_GICD_IPRIORITYR22_t;
8746 #define ALT_GIC_DIST_GICD_IPRIORITYR22_RESET 0x00000000
8748 #define ALT_GIC_DIST_GICD_IPRIORITYR22_OFST 0x458
8771 #define ALT_GIC_DIST_GICD_IPRIORITYR23_FLD_LSB 0
8773 #define ALT_GIC_DIST_GICD_IPRIORITYR23_FLD_MSB 31
8775 #define ALT_GIC_DIST_GICD_IPRIORITYR23_FLD_WIDTH 32
8777 #define ALT_GIC_DIST_GICD_IPRIORITYR23_FLD_SET_MSK 0xffffffff
8779 #define ALT_GIC_DIST_GICD_IPRIORITYR23_FLD_CLR_MSK 0x00000000
8781 #define ALT_GIC_DIST_GICD_IPRIORITYR23_FLD_RESET 0x0
8783 #define ALT_GIC_DIST_GICD_IPRIORITYR23_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8785 #define ALT_GIC_DIST_GICD_IPRIORITYR23_FLD_SET(value) (((value) << 0) & 0xffffffff)
8787 #ifndef __ASSEMBLY__
8799 struct ALT_GIC_DIST_GICD_IPRIORITYR23_s
8801 volatile uint32_t fld : 32;
8805 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR23_s ALT_GIC_DIST_GICD_IPRIORITYR23_t;
8809 #define ALT_GIC_DIST_GICD_IPRIORITYR23_RESET 0x00000000
8811 #define ALT_GIC_DIST_GICD_IPRIORITYR23_OFST 0x45c
8834 #define ALT_GIC_DIST_GICD_IPRIORITYR24_FLD_LSB 0
8836 #define ALT_GIC_DIST_GICD_IPRIORITYR24_FLD_MSB 31
8838 #define ALT_GIC_DIST_GICD_IPRIORITYR24_FLD_WIDTH 32
8840 #define ALT_GIC_DIST_GICD_IPRIORITYR24_FLD_SET_MSK 0xffffffff
8842 #define ALT_GIC_DIST_GICD_IPRIORITYR24_FLD_CLR_MSK 0x00000000
8844 #define ALT_GIC_DIST_GICD_IPRIORITYR24_FLD_RESET 0x0
8846 #define ALT_GIC_DIST_GICD_IPRIORITYR24_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8848 #define ALT_GIC_DIST_GICD_IPRIORITYR24_FLD_SET(value) (((value) << 0) & 0xffffffff)
8850 #ifndef __ASSEMBLY__
8862 struct ALT_GIC_DIST_GICD_IPRIORITYR24_s
8864 volatile uint32_t fld : 32;
8868 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR24_s ALT_GIC_DIST_GICD_IPRIORITYR24_t;
8872 #define ALT_GIC_DIST_GICD_IPRIORITYR24_RESET 0x00000000
8874 #define ALT_GIC_DIST_GICD_IPRIORITYR24_OFST 0x460
8897 #define ALT_GIC_DIST_GICD_IPRIORITYR25_FLD_LSB 0
8899 #define ALT_GIC_DIST_GICD_IPRIORITYR25_FLD_MSB 31
8901 #define ALT_GIC_DIST_GICD_IPRIORITYR25_FLD_WIDTH 32
8903 #define ALT_GIC_DIST_GICD_IPRIORITYR25_FLD_SET_MSK 0xffffffff
8905 #define ALT_GIC_DIST_GICD_IPRIORITYR25_FLD_CLR_MSK 0x00000000
8907 #define ALT_GIC_DIST_GICD_IPRIORITYR25_FLD_RESET 0x0
8909 #define ALT_GIC_DIST_GICD_IPRIORITYR25_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8911 #define ALT_GIC_DIST_GICD_IPRIORITYR25_FLD_SET(value) (((value) << 0) & 0xffffffff)
8913 #ifndef __ASSEMBLY__
8925 struct ALT_GIC_DIST_GICD_IPRIORITYR25_s
8927 volatile uint32_t fld : 32;
8931 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR25_s ALT_GIC_DIST_GICD_IPRIORITYR25_t;
8935 #define ALT_GIC_DIST_GICD_IPRIORITYR25_RESET 0x00000000
8937 #define ALT_GIC_DIST_GICD_IPRIORITYR25_OFST 0x464
8960 #define ALT_GIC_DIST_GICD_IPRIORITYR26_FLD_LSB 0
8962 #define ALT_GIC_DIST_GICD_IPRIORITYR26_FLD_MSB 31
8964 #define ALT_GIC_DIST_GICD_IPRIORITYR26_FLD_WIDTH 32
8966 #define ALT_GIC_DIST_GICD_IPRIORITYR26_FLD_SET_MSK 0xffffffff
8968 #define ALT_GIC_DIST_GICD_IPRIORITYR26_FLD_CLR_MSK 0x00000000
8970 #define ALT_GIC_DIST_GICD_IPRIORITYR26_FLD_RESET 0x0
8972 #define ALT_GIC_DIST_GICD_IPRIORITYR26_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8974 #define ALT_GIC_DIST_GICD_IPRIORITYR26_FLD_SET(value) (((value) << 0) & 0xffffffff)
8976 #ifndef __ASSEMBLY__
8988 struct ALT_GIC_DIST_GICD_IPRIORITYR26_s
8990 volatile uint32_t fld : 32;
8994 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR26_s ALT_GIC_DIST_GICD_IPRIORITYR26_t;
8998 #define ALT_GIC_DIST_GICD_IPRIORITYR26_RESET 0x00000000
9000 #define ALT_GIC_DIST_GICD_IPRIORITYR26_OFST 0x468
9023 #define ALT_GIC_DIST_GICD_IPRIORITYR27_FLD_LSB 0
9025 #define ALT_GIC_DIST_GICD_IPRIORITYR27_FLD_MSB 31
9027 #define ALT_GIC_DIST_GICD_IPRIORITYR27_FLD_WIDTH 32
9029 #define ALT_GIC_DIST_GICD_IPRIORITYR27_FLD_SET_MSK 0xffffffff
9031 #define ALT_GIC_DIST_GICD_IPRIORITYR27_FLD_CLR_MSK 0x00000000
9033 #define ALT_GIC_DIST_GICD_IPRIORITYR27_FLD_RESET 0x0
9035 #define ALT_GIC_DIST_GICD_IPRIORITYR27_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9037 #define ALT_GIC_DIST_GICD_IPRIORITYR27_FLD_SET(value) (((value) << 0) & 0xffffffff)
9039 #ifndef __ASSEMBLY__
9051 struct ALT_GIC_DIST_GICD_IPRIORITYR27_s
9053 volatile uint32_t fld : 32;
9057 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR27_s ALT_GIC_DIST_GICD_IPRIORITYR27_t;
9061 #define ALT_GIC_DIST_GICD_IPRIORITYR27_RESET 0x00000000
9063 #define ALT_GIC_DIST_GICD_IPRIORITYR27_OFST 0x46c
9086 #define ALT_GIC_DIST_GICD_IPRIORITYR28_FLD_LSB 0
9088 #define ALT_GIC_DIST_GICD_IPRIORITYR28_FLD_MSB 31
9090 #define ALT_GIC_DIST_GICD_IPRIORITYR28_FLD_WIDTH 32
9092 #define ALT_GIC_DIST_GICD_IPRIORITYR28_FLD_SET_MSK 0xffffffff
9094 #define ALT_GIC_DIST_GICD_IPRIORITYR28_FLD_CLR_MSK 0x00000000
9096 #define ALT_GIC_DIST_GICD_IPRIORITYR28_FLD_RESET 0x0
9098 #define ALT_GIC_DIST_GICD_IPRIORITYR28_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9100 #define ALT_GIC_DIST_GICD_IPRIORITYR28_FLD_SET(value) (((value) << 0) & 0xffffffff)
9102 #ifndef __ASSEMBLY__
9114 struct ALT_GIC_DIST_GICD_IPRIORITYR28_s
9116 volatile uint32_t fld : 32;
9120 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR28_s ALT_GIC_DIST_GICD_IPRIORITYR28_t;
9124 #define ALT_GIC_DIST_GICD_IPRIORITYR28_RESET 0x00000000
9126 #define ALT_GIC_DIST_GICD_IPRIORITYR28_OFST 0x470
9149 #define ALT_GIC_DIST_GICD_IPRIORITYR29_FLD_LSB 0
9151 #define ALT_GIC_DIST_GICD_IPRIORITYR29_FLD_MSB 31
9153 #define ALT_GIC_DIST_GICD_IPRIORITYR29_FLD_WIDTH 32
9155 #define ALT_GIC_DIST_GICD_IPRIORITYR29_FLD_SET_MSK 0xffffffff
9157 #define ALT_GIC_DIST_GICD_IPRIORITYR29_FLD_CLR_MSK 0x00000000
9159 #define ALT_GIC_DIST_GICD_IPRIORITYR29_FLD_RESET 0x0
9161 #define ALT_GIC_DIST_GICD_IPRIORITYR29_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9163 #define ALT_GIC_DIST_GICD_IPRIORITYR29_FLD_SET(value) (((value) << 0) & 0xffffffff)
9165 #ifndef __ASSEMBLY__
9177 struct ALT_GIC_DIST_GICD_IPRIORITYR29_s
9179 volatile uint32_t fld : 32;
9183 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR29_s ALT_GIC_DIST_GICD_IPRIORITYR29_t;
9187 #define ALT_GIC_DIST_GICD_IPRIORITYR29_RESET 0x00000000
9189 #define ALT_GIC_DIST_GICD_IPRIORITYR29_OFST 0x474
9212 #define ALT_GIC_DIST_GICD_IPRIORITYR30_FLD_LSB 0
9214 #define ALT_GIC_DIST_GICD_IPRIORITYR30_FLD_MSB 31
9216 #define ALT_GIC_DIST_GICD_IPRIORITYR30_FLD_WIDTH 32
9218 #define ALT_GIC_DIST_GICD_IPRIORITYR30_FLD_SET_MSK 0xffffffff
9220 #define ALT_GIC_DIST_GICD_IPRIORITYR30_FLD_CLR_MSK 0x00000000
9222 #define ALT_GIC_DIST_GICD_IPRIORITYR30_FLD_RESET 0x0
9224 #define ALT_GIC_DIST_GICD_IPRIORITYR30_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9226 #define ALT_GIC_DIST_GICD_IPRIORITYR30_FLD_SET(value) (((value) << 0) & 0xffffffff)
9228 #ifndef __ASSEMBLY__
9240 struct ALT_GIC_DIST_GICD_IPRIORITYR30_s
9242 volatile uint32_t fld : 32;
9246 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR30_s ALT_GIC_DIST_GICD_IPRIORITYR30_t;
9250 #define ALT_GIC_DIST_GICD_IPRIORITYR30_RESET 0x00000000
9252 #define ALT_GIC_DIST_GICD_IPRIORITYR30_OFST 0x478
9275 #define ALT_GIC_DIST_GICD_IPRIORITYR31_FLD_LSB 0
9277 #define ALT_GIC_DIST_GICD_IPRIORITYR31_FLD_MSB 31
9279 #define ALT_GIC_DIST_GICD_IPRIORITYR31_FLD_WIDTH 32
9281 #define ALT_GIC_DIST_GICD_IPRIORITYR31_FLD_SET_MSK 0xffffffff
9283 #define ALT_GIC_DIST_GICD_IPRIORITYR31_FLD_CLR_MSK 0x00000000
9285 #define ALT_GIC_DIST_GICD_IPRIORITYR31_FLD_RESET 0x0
9287 #define ALT_GIC_DIST_GICD_IPRIORITYR31_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9289 #define ALT_GIC_DIST_GICD_IPRIORITYR31_FLD_SET(value) (((value) << 0) & 0xffffffff)
9291 #ifndef __ASSEMBLY__
9303 struct ALT_GIC_DIST_GICD_IPRIORITYR31_s
9305 volatile uint32_t fld : 32;
9309 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR31_s ALT_GIC_DIST_GICD_IPRIORITYR31_t;
9313 #define ALT_GIC_DIST_GICD_IPRIORITYR31_RESET 0x00000000
9315 #define ALT_GIC_DIST_GICD_IPRIORITYR31_OFST 0x47c
9338 #define ALT_GIC_DIST_GICD_IPRIORITYR32_FLD_LSB 0
9340 #define ALT_GIC_DIST_GICD_IPRIORITYR32_FLD_MSB 31
9342 #define ALT_GIC_DIST_GICD_IPRIORITYR32_FLD_WIDTH 32
9344 #define ALT_GIC_DIST_GICD_IPRIORITYR32_FLD_SET_MSK 0xffffffff
9346 #define ALT_GIC_DIST_GICD_IPRIORITYR32_FLD_CLR_MSK 0x00000000
9348 #define ALT_GIC_DIST_GICD_IPRIORITYR32_FLD_RESET 0x0
9350 #define ALT_GIC_DIST_GICD_IPRIORITYR32_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9352 #define ALT_GIC_DIST_GICD_IPRIORITYR32_FLD_SET(value) (((value) << 0) & 0xffffffff)
9354 #ifndef __ASSEMBLY__
9366 struct ALT_GIC_DIST_GICD_IPRIORITYR32_s
9368 volatile uint32_t fld : 32;
9372 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR32_s ALT_GIC_DIST_GICD_IPRIORITYR32_t;
9376 #define ALT_GIC_DIST_GICD_IPRIORITYR32_RESET 0x00000000
9378 #define ALT_GIC_DIST_GICD_IPRIORITYR32_OFST 0x480
9401 #define ALT_GIC_DIST_GICD_IPRIORITYR33_FLD_LSB 0
9403 #define ALT_GIC_DIST_GICD_IPRIORITYR33_FLD_MSB 31
9405 #define ALT_GIC_DIST_GICD_IPRIORITYR33_FLD_WIDTH 32
9407 #define ALT_GIC_DIST_GICD_IPRIORITYR33_FLD_SET_MSK 0xffffffff
9409 #define ALT_GIC_DIST_GICD_IPRIORITYR33_FLD_CLR_MSK 0x00000000
9411 #define ALT_GIC_DIST_GICD_IPRIORITYR33_FLD_RESET 0x0
9413 #define ALT_GIC_DIST_GICD_IPRIORITYR33_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9415 #define ALT_GIC_DIST_GICD_IPRIORITYR33_FLD_SET(value) (((value) << 0) & 0xffffffff)
9417 #ifndef __ASSEMBLY__
9429 struct ALT_GIC_DIST_GICD_IPRIORITYR33_s
9431 volatile uint32_t fld : 32;
9435 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR33_s ALT_GIC_DIST_GICD_IPRIORITYR33_t;
9439 #define ALT_GIC_DIST_GICD_IPRIORITYR33_RESET 0x00000000
9441 #define ALT_GIC_DIST_GICD_IPRIORITYR33_OFST 0x484
9464 #define ALT_GIC_DIST_GICD_IPRIORITYR34_FLD_LSB 0
9466 #define ALT_GIC_DIST_GICD_IPRIORITYR34_FLD_MSB 31
9468 #define ALT_GIC_DIST_GICD_IPRIORITYR34_FLD_WIDTH 32
9470 #define ALT_GIC_DIST_GICD_IPRIORITYR34_FLD_SET_MSK 0xffffffff
9472 #define ALT_GIC_DIST_GICD_IPRIORITYR34_FLD_CLR_MSK 0x00000000
9474 #define ALT_GIC_DIST_GICD_IPRIORITYR34_FLD_RESET 0x0
9476 #define ALT_GIC_DIST_GICD_IPRIORITYR34_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9478 #define ALT_GIC_DIST_GICD_IPRIORITYR34_FLD_SET(value) (((value) << 0) & 0xffffffff)
9480 #ifndef __ASSEMBLY__
9492 struct ALT_GIC_DIST_GICD_IPRIORITYR34_s
9494 volatile uint32_t fld : 32;
9498 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR34_s ALT_GIC_DIST_GICD_IPRIORITYR34_t;
9502 #define ALT_GIC_DIST_GICD_IPRIORITYR34_RESET 0x00000000
9504 #define ALT_GIC_DIST_GICD_IPRIORITYR34_OFST 0x488
9527 #define ALT_GIC_DIST_GICD_IPRIORITYR35_FLD_LSB 0
9529 #define ALT_GIC_DIST_GICD_IPRIORITYR35_FLD_MSB 31
9531 #define ALT_GIC_DIST_GICD_IPRIORITYR35_FLD_WIDTH 32
9533 #define ALT_GIC_DIST_GICD_IPRIORITYR35_FLD_SET_MSK 0xffffffff
9535 #define ALT_GIC_DIST_GICD_IPRIORITYR35_FLD_CLR_MSK 0x00000000
9537 #define ALT_GIC_DIST_GICD_IPRIORITYR35_FLD_RESET 0x0
9539 #define ALT_GIC_DIST_GICD_IPRIORITYR35_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9541 #define ALT_GIC_DIST_GICD_IPRIORITYR35_FLD_SET(value) (((value) << 0) & 0xffffffff)
9543 #ifndef __ASSEMBLY__
9555 struct ALT_GIC_DIST_GICD_IPRIORITYR35_s
9557 volatile uint32_t fld : 32;
9561 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR35_s ALT_GIC_DIST_GICD_IPRIORITYR35_t;
9565 #define ALT_GIC_DIST_GICD_IPRIORITYR35_RESET 0x00000000
9567 #define ALT_GIC_DIST_GICD_IPRIORITYR35_OFST 0x48c
9590 #define ALT_GIC_DIST_GICD_IPRIORITYR36_FLD_LSB 0
9592 #define ALT_GIC_DIST_GICD_IPRIORITYR36_FLD_MSB 31
9594 #define ALT_GIC_DIST_GICD_IPRIORITYR36_FLD_WIDTH 32
9596 #define ALT_GIC_DIST_GICD_IPRIORITYR36_FLD_SET_MSK 0xffffffff
9598 #define ALT_GIC_DIST_GICD_IPRIORITYR36_FLD_CLR_MSK 0x00000000
9600 #define ALT_GIC_DIST_GICD_IPRIORITYR36_FLD_RESET 0x0
9602 #define ALT_GIC_DIST_GICD_IPRIORITYR36_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9604 #define ALT_GIC_DIST_GICD_IPRIORITYR36_FLD_SET(value) (((value) << 0) & 0xffffffff)
9606 #ifndef __ASSEMBLY__
9618 struct ALT_GIC_DIST_GICD_IPRIORITYR36_s
9620 volatile uint32_t fld : 32;
9624 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR36_s ALT_GIC_DIST_GICD_IPRIORITYR36_t;
9628 #define ALT_GIC_DIST_GICD_IPRIORITYR36_RESET 0x00000000
9630 #define ALT_GIC_DIST_GICD_IPRIORITYR36_OFST 0x490
9653 #define ALT_GIC_DIST_GICD_IPRIORITYR37_FLD_LSB 0
9655 #define ALT_GIC_DIST_GICD_IPRIORITYR37_FLD_MSB 31
9657 #define ALT_GIC_DIST_GICD_IPRIORITYR37_FLD_WIDTH 32
9659 #define ALT_GIC_DIST_GICD_IPRIORITYR37_FLD_SET_MSK 0xffffffff
9661 #define ALT_GIC_DIST_GICD_IPRIORITYR37_FLD_CLR_MSK 0x00000000
9663 #define ALT_GIC_DIST_GICD_IPRIORITYR37_FLD_RESET 0x0
9665 #define ALT_GIC_DIST_GICD_IPRIORITYR37_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9667 #define ALT_GIC_DIST_GICD_IPRIORITYR37_FLD_SET(value) (((value) << 0) & 0xffffffff)
9669 #ifndef __ASSEMBLY__
9681 struct ALT_GIC_DIST_GICD_IPRIORITYR37_s
9683 volatile uint32_t fld : 32;
9687 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR37_s ALT_GIC_DIST_GICD_IPRIORITYR37_t;
9691 #define ALT_GIC_DIST_GICD_IPRIORITYR37_RESET 0x00000000
9693 #define ALT_GIC_DIST_GICD_IPRIORITYR37_OFST 0x494
9716 #define ALT_GIC_DIST_GICD_IPRIORITYR38_FLD_LSB 0
9718 #define ALT_GIC_DIST_GICD_IPRIORITYR38_FLD_MSB 31
9720 #define ALT_GIC_DIST_GICD_IPRIORITYR38_FLD_WIDTH 32
9722 #define ALT_GIC_DIST_GICD_IPRIORITYR38_FLD_SET_MSK 0xffffffff
9724 #define ALT_GIC_DIST_GICD_IPRIORITYR38_FLD_CLR_MSK 0x00000000
9726 #define ALT_GIC_DIST_GICD_IPRIORITYR38_FLD_RESET 0x0
9728 #define ALT_GIC_DIST_GICD_IPRIORITYR38_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9730 #define ALT_GIC_DIST_GICD_IPRIORITYR38_FLD_SET(value) (((value) << 0) & 0xffffffff)
9732 #ifndef __ASSEMBLY__
9744 struct ALT_GIC_DIST_GICD_IPRIORITYR38_s
9746 volatile uint32_t fld : 32;
9750 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR38_s ALT_GIC_DIST_GICD_IPRIORITYR38_t;
9754 #define ALT_GIC_DIST_GICD_IPRIORITYR38_RESET 0x00000000
9756 #define ALT_GIC_DIST_GICD_IPRIORITYR38_OFST 0x498
9779 #define ALT_GIC_DIST_GICD_IPRIORITYR39_FLD_LSB 0
9781 #define ALT_GIC_DIST_GICD_IPRIORITYR39_FLD_MSB 31
9783 #define ALT_GIC_DIST_GICD_IPRIORITYR39_FLD_WIDTH 32
9785 #define ALT_GIC_DIST_GICD_IPRIORITYR39_FLD_SET_MSK 0xffffffff
9787 #define ALT_GIC_DIST_GICD_IPRIORITYR39_FLD_CLR_MSK 0x00000000
9789 #define ALT_GIC_DIST_GICD_IPRIORITYR39_FLD_RESET 0x0
9791 #define ALT_GIC_DIST_GICD_IPRIORITYR39_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9793 #define ALT_GIC_DIST_GICD_IPRIORITYR39_FLD_SET(value) (((value) << 0) & 0xffffffff)
9795 #ifndef __ASSEMBLY__
9807 struct ALT_GIC_DIST_GICD_IPRIORITYR39_s
9809 volatile uint32_t fld : 32;
9813 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR39_s ALT_GIC_DIST_GICD_IPRIORITYR39_t;
9817 #define ALT_GIC_DIST_GICD_IPRIORITYR39_RESET 0x00000000
9819 #define ALT_GIC_DIST_GICD_IPRIORITYR39_OFST 0x49c
9842 #define ALT_GIC_DIST_GICD_IPRIORITYR40_FLD_LSB 0
9844 #define ALT_GIC_DIST_GICD_IPRIORITYR40_FLD_MSB 31
9846 #define ALT_GIC_DIST_GICD_IPRIORITYR40_FLD_WIDTH 32
9848 #define ALT_GIC_DIST_GICD_IPRIORITYR40_FLD_SET_MSK 0xffffffff
9850 #define ALT_GIC_DIST_GICD_IPRIORITYR40_FLD_CLR_MSK 0x00000000
9852 #define ALT_GIC_DIST_GICD_IPRIORITYR40_FLD_RESET 0x0
9854 #define ALT_GIC_DIST_GICD_IPRIORITYR40_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9856 #define ALT_GIC_DIST_GICD_IPRIORITYR40_FLD_SET(value) (((value) << 0) & 0xffffffff)
9858 #ifndef __ASSEMBLY__
9870 struct ALT_GIC_DIST_GICD_IPRIORITYR40_s
9872 volatile uint32_t fld : 32;
9876 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR40_s ALT_GIC_DIST_GICD_IPRIORITYR40_t;
9880 #define ALT_GIC_DIST_GICD_IPRIORITYR40_RESET 0x00000000
9882 #define ALT_GIC_DIST_GICD_IPRIORITYR40_OFST 0x4a0
9905 #define ALT_GIC_DIST_GICD_IPRIORITYR41_FLD_LSB 0
9907 #define ALT_GIC_DIST_GICD_IPRIORITYR41_FLD_MSB 31
9909 #define ALT_GIC_DIST_GICD_IPRIORITYR41_FLD_WIDTH 32
9911 #define ALT_GIC_DIST_GICD_IPRIORITYR41_FLD_SET_MSK 0xffffffff
9913 #define ALT_GIC_DIST_GICD_IPRIORITYR41_FLD_CLR_MSK 0x00000000
9915 #define ALT_GIC_DIST_GICD_IPRIORITYR41_FLD_RESET 0x0
9917 #define ALT_GIC_DIST_GICD_IPRIORITYR41_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9919 #define ALT_GIC_DIST_GICD_IPRIORITYR41_FLD_SET(value) (((value) << 0) & 0xffffffff)
9921 #ifndef __ASSEMBLY__
9933 struct ALT_GIC_DIST_GICD_IPRIORITYR41_s
9935 volatile uint32_t fld : 32;
9939 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR41_s ALT_GIC_DIST_GICD_IPRIORITYR41_t;
9943 #define ALT_GIC_DIST_GICD_IPRIORITYR41_RESET 0x00000000
9945 #define ALT_GIC_DIST_GICD_IPRIORITYR41_OFST 0x4a4
9968 #define ALT_GIC_DIST_GICD_IPRIORITYR42_FLD_LSB 0
9970 #define ALT_GIC_DIST_GICD_IPRIORITYR42_FLD_MSB 31
9972 #define ALT_GIC_DIST_GICD_IPRIORITYR42_FLD_WIDTH 32
9974 #define ALT_GIC_DIST_GICD_IPRIORITYR42_FLD_SET_MSK 0xffffffff
9976 #define ALT_GIC_DIST_GICD_IPRIORITYR42_FLD_CLR_MSK 0x00000000
9978 #define ALT_GIC_DIST_GICD_IPRIORITYR42_FLD_RESET 0x0
9980 #define ALT_GIC_DIST_GICD_IPRIORITYR42_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9982 #define ALT_GIC_DIST_GICD_IPRIORITYR42_FLD_SET(value) (((value) << 0) & 0xffffffff)
9984 #ifndef __ASSEMBLY__
9996 struct ALT_GIC_DIST_GICD_IPRIORITYR42_s
9998 volatile uint32_t fld : 32;
10002 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR42_s ALT_GIC_DIST_GICD_IPRIORITYR42_t;
10006 #define ALT_GIC_DIST_GICD_IPRIORITYR42_RESET 0x00000000
10008 #define ALT_GIC_DIST_GICD_IPRIORITYR42_OFST 0x4a8
10031 #define ALT_GIC_DIST_GICD_IPRIORITYR43_FLD_LSB 0
10033 #define ALT_GIC_DIST_GICD_IPRIORITYR43_FLD_MSB 31
10035 #define ALT_GIC_DIST_GICD_IPRIORITYR43_FLD_WIDTH 32
10037 #define ALT_GIC_DIST_GICD_IPRIORITYR43_FLD_SET_MSK 0xffffffff
10039 #define ALT_GIC_DIST_GICD_IPRIORITYR43_FLD_CLR_MSK 0x00000000
10041 #define ALT_GIC_DIST_GICD_IPRIORITYR43_FLD_RESET 0x0
10043 #define ALT_GIC_DIST_GICD_IPRIORITYR43_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10045 #define ALT_GIC_DIST_GICD_IPRIORITYR43_FLD_SET(value) (((value) << 0) & 0xffffffff)
10047 #ifndef __ASSEMBLY__
10059 struct ALT_GIC_DIST_GICD_IPRIORITYR43_s
10061 volatile uint32_t fld : 32;
10065 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR43_s ALT_GIC_DIST_GICD_IPRIORITYR43_t;
10069 #define ALT_GIC_DIST_GICD_IPRIORITYR43_RESET 0x00000000
10071 #define ALT_GIC_DIST_GICD_IPRIORITYR43_OFST 0x4ac
10094 #define ALT_GIC_DIST_GICD_IPRIORITYR44_FLD_LSB 0
10096 #define ALT_GIC_DIST_GICD_IPRIORITYR44_FLD_MSB 31
10098 #define ALT_GIC_DIST_GICD_IPRIORITYR44_FLD_WIDTH 32
10100 #define ALT_GIC_DIST_GICD_IPRIORITYR44_FLD_SET_MSK 0xffffffff
10102 #define ALT_GIC_DIST_GICD_IPRIORITYR44_FLD_CLR_MSK 0x00000000
10104 #define ALT_GIC_DIST_GICD_IPRIORITYR44_FLD_RESET 0x0
10106 #define ALT_GIC_DIST_GICD_IPRIORITYR44_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10108 #define ALT_GIC_DIST_GICD_IPRIORITYR44_FLD_SET(value) (((value) << 0) & 0xffffffff)
10110 #ifndef __ASSEMBLY__
10122 struct ALT_GIC_DIST_GICD_IPRIORITYR44_s
10124 volatile uint32_t fld : 32;
10128 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR44_s ALT_GIC_DIST_GICD_IPRIORITYR44_t;
10132 #define ALT_GIC_DIST_GICD_IPRIORITYR44_RESET 0x00000000
10134 #define ALT_GIC_DIST_GICD_IPRIORITYR44_OFST 0x4b0
10157 #define ALT_GIC_DIST_GICD_IPRIORITYR45_FLD_LSB 0
10159 #define ALT_GIC_DIST_GICD_IPRIORITYR45_FLD_MSB 31
10161 #define ALT_GIC_DIST_GICD_IPRIORITYR45_FLD_WIDTH 32
10163 #define ALT_GIC_DIST_GICD_IPRIORITYR45_FLD_SET_MSK 0xffffffff
10165 #define ALT_GIC_DIST_GICD_IPRIORITYR45_FLD_CLR_MSK 0x00000000
10167 #define ALT_GIC_DIST_GICD_IPRIORITYR45_FLD_RESET 0x0
10169 #define ALT_GIC_DIST_GICD_IPRIORITYR45_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10171 #define ALT_GIC_DIST_GICD_IPRIORITYR45_FLD_SET(value) (((value) << 0) & 0xffffffff)
10173 #ifndef __ASSEMBLY__
10185 struct ALT_GIC_DIST_GICD_IPRIORITYR45_s
10187 volatile uint32_t fld : 32;
10191 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR45_s ALT_GIC_DIST_GICD_IPRIORITYR45_t;
10195 #define ALT_GIC_DIST_GICD_IPRIORITYR45_RESET 0x00000000
10197 #define ALT_GIC_DIST_GICD_IPRIORITYR45_OFST 0x4b4
10220 #define ALT_GIC_DIST_GICD_IPRIORITYR46_FLD_LSB 0
10222 #define ALT_GIC_DIST_GICD_IPRIORITYR46_FLD_MSB 31
10224 #define ALT_GIC_DIST_GICD_IPRIORITYR46_FLD_WIDTH 32
10226 #define ALT_GIC_DIST_GICD_IPRIORITYR46_FLD_SET_MSK 0xffffffff
10228 #define ALT_GIC_DIST_GICD_IPRIORITYR46_FLD_CLR_MSK 0x00000000
10230 #define ALT_GIC_DIST_GICD_IPRIORITYR46_FLD_RESET 0x0
10232 #define ALT_GIC_DIST_GICD_IPRIORITYR46_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10234 #define ALT_GIC_DIST_GICD_IPRIORITYR46_FLD_SET(value) (((value) << 0) & 0xffffffff)
10236 #ifndef __ASSEMBLY__
10248 struct ALT_GIC_DIST_GICD_IPRIORITYR46_s
10250 volatile uint32_t fld : 32;
10254 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR46_s ALT_GIC_DIST_GICD_IPRIORITYR46_t;
10258 #define ALT_GIC_DIST_GICD_IPRIORITYR46_RESET 0x00000000
10260 #define ALT_GIC_DIST_GICD_IPRIORITYR46_OFST 0x4b8
10283 #define ALT_GIC_DIST_GICD_IPRIORITYR47_FLD_LSB 0
10285 #define ALT_GIC_DIST_GICD_IPRIORITYR47_FLD_MSB 31
10287 #define ALT_GIC_DIST_GICD_IPRIORITYR47_FLD_WIDTH 32
10289 #define ALT_GIC_DIST_GICD_IPRIORITYR47_FLD_SET_MSK 0xffffffff
10291 #define ALT_GIC_DIST_GICD_IPRIORITYR47_FLD_CLR_MSK 0x00000000
10293 #define ALT_GIC_DIST_GICD_IPRIORITYR47_FLD_RESET 0x0
10295 #define ALT_GIC_DIST_GICD_IPRIORITYR47_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10297 #define ALT_GIC_DIST_GICD_IPRIORITYR47_FLD_SET(value) (((value) << 0) & 0xffffffff)
10299 #ifndef __ASSEMBLY__
10311 struct ALT_GIC_DIST_GICD_IPRIORITYR47_s
10313 volatile uint32_t fld : 32;
10317 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR47_s ALT_GIC_DIST_GICD_IPRIORITYR47_t;
10321 #define ALT_GIC_DIST_GICD_IPRIORITYR47_RESET 0x00000000
10323 #define ALT_GIC_DIST_GICD_IPRIORITYR47_OFST 0x4bc
10346 #define ALT_GIC_DIST_GICD_IPRIORITYR48_FLD_LSB 0
10348 #define ALT_GIC_DIST_GICD_IPRIORITYR48_FLD_MSB 31
10350 #define ALT_GIC_DIST_GICD_IPRIORITYR48_FLD_WIDTH 32
10352 #define ALT_GIC_DIST_GICD_IPRIORITYR48_FLD_SET_MSK 0xffffffff
10354 #define ALT_GIC_DIST_GICD_IPRIORITYR48_FLD_CLR_MSK 0x00000000
10356 #define ALT_GIC_DIST_GICD_IPRIORITYR48_FLD_RESET 0x0
10358 #define ALT_GIC_DIST_GICD_IPRIORITYR48_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10360 #define ALT_GIC_DIST_GICD_IPRIORITYR48_FLD_SET(value) (((value) << 0) & 0xffffffff)
10362 #ifndef __ASSEMBLY__
10374 struct ALT_GIC_DIST_GICD_IPRIORITYR48_s
10376 volatile uint32_t fld : 32;
10380 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR48_s ALT_GIC_DIST_GICD_IPRIORITYR48_t;
10384 #define ALT_GIC_DIST_GICD_IPRIORITYR48_RESET 0x00000000
10386 #define ALT_GIC_DIST_GICD_IPRIORITYR48_OFST 0x4c0
10409 #define ALT_GIC_DIST_GICD_IPRIORITYR49_FLD_LSB 0
10411 #define ALT_GIC_DIST_GICD_IPRIORITYR49_FLD_MSB 31
10413 #define ALT_GIC_DIST_GICD_IPRIORITYR49_FLD_WIDTH 32
10415 #define ALT_GIC_DIST_GICD_IPRIORITYR49_FLD_SET_MSK 0xffffffff
10417 #define ALT_GIC_DIST_GICD_IPRIORITYR49_FLD_CLR_MSK 0x00000000
10419 #define ALT_GIC_DIST_GICD_IPRIORITYR49_FLD_RESET 0x0
10421 #define ALT_GIC_DIST_GICD_IPRIORITYR49_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10423 #define ALT_GIC_DIST_GICD_IPRIORITYR49_FLD_SET(value) (((value) << 0) & 0xffffffff)
10425 #ifndef __ASSEMBLY__
10437 struct ALT_GIC_DIST_GICD_IPRIORITYR49_s
10439 volatile uint32_t fld : 32;
10443 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR49_s ALT_GIC_DIST_GICD_IPRIORITYR49_t;
10447 #define ALT_GIC_DIST_GICD_IPRIORITYR49_RESET 0x00000000
10449 #define ALT_GIC_DIST_GICD_IPRIORITYR49_OFST 0x4c4
10472 #define ALT_GIC_DIST_GICD_IPRIORITYR50_FLD_LSB 0
10474 #define ALT_GIC_DIST_GICD_IPRIORITYR50_FLD_MSB 31
10476 #define ALT_GIC_DIST_GICD_IPRIORITYR50_FLD_WIDTH 32
10478 #define ALT_GIC_DIST_GICD_IPRIORITYR50_FLD_SET_MSK 0xffffffff
10480 #define ALT_GIC_DIST_GICD_IPRIORITYR50_FLD_CLR_MSK 0x00000000
10482 #define ALT_GIC_DIST_GICD_IPRIORITYR50_FLD_RESET 0x0
10484 #define ALT_GIC_DIST_GICD_IPRIORITYR50_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10486 #define ALT_GIC_DIST_GICD_IPRIORITYR50_FLD_SET(value) (((value) << 0) & 0xffffffff)
10488 #ifndef __ASSEMBLY__
10500 struct ALT_GIC_DIST_GICD_IPRIORITYR50_s
10502 volatile uint32_t fld : 32;
10506 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR50_s ALT_GIC_DIST_GICD_IPRIORITYR50_t;
10510 #define ALT_GIC_DIST_GICD_IPRIORITYR50_RESET 0x00000000
10512 #define ALT_GIC_DIST_GICD_IPRIORITYR50_OFST 0x4c8
10535 #define ALT_GIC_DIST_GICD_IPRIORITYR51_FLD_LSB 0
10537 #define ALT_GIC_DIST_GICD_IPRIORITYR51_FLD_MSB 31
10539 #define ALT_GIC_DIST_GICD_IPRIORITYR51_FLD_WIDTH 32
10541 #define ALT_GIC_DIST_GICD_IPRIORITYR51_FLD_SET_MSK 0xffffffff
10543 #define ALT_GIC_DIST_GICD_IPRIORITYR51_FLD_CLR_MSK 0x00000000
10545 #define ALT_GIC_DIST_GICD_IPRIORITYR51_FLD_RESET 0x0
10547 #define ALT_GIC_DIST_GICD_IPRIORITYR51_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10549 #define ALT_GIC_DIST_GICD_IPRIORITYR51_FLD_SET(value) (((value) << 0) & 0xffffffff)
10551 #ifndef __ASSEMBLY__
10563 struct ALT_GIC_DIST_GICD_IPRIORITYR51_s
10565 volatile uint32_t fld : 32;
10569 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR51_s ALT_GIC_DIST_GICD_IPRIORITYR51_t;
10573 #define ALT_GIC_DIST_GICD_IPRIORITYR51_RESET 0x00000000
10575 #define ALT_GIC_DIST_GICD_IPRIORITYR51_OFST 0x4cc
10598 #define ALT_GIC_DIST_GICD_IPRIORITYR52_FLD_LSB 0
10600 #define ALT_GIC_DIST_GICD_IPRIORITYR52_FLD_MSB 31
10602 #define ALT_GIC_DIST_GICD_IPRIORITYR52_FLD_WIDTH 32
10604 #define ALT_GIC_DIST_GICD_IPRIORITYR52_FLD_SET_MSK 0xffffffff
10606 #define ALT_GIC_DIST_GICD_IPRIORITYR52_FLD_CLR_MSK 0x00000000
10608 #define ALT_GIC_DIST_GICD_IPRIORITYR52_FLD_RESET 0x0
10610 #define ALT_GIC_DIST_GICD_IPRIORITYR52_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10612 #define ALT_GIC_DIST_GICD_IPRIORITYR52_FLD_SET(value) (((value) << 0) & 0xffffffff)
10614 #ifndef __ASSEMBLY__
10626 struct ALT_GIC_DIST_GICD_IPRIORITYR52_s
10628 volatile uint32_t fld : 32;
10632 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR52_s ALT_GIC_DIST_GICD_IPRIORITYR52_t;
10636 #define ALT_GIC_DIST_GICD_IPRIORITYR52_RESET 0x00000000
10638 #define ALT_GIC_DIST_GICD_IPRIORITYR52_OFST 0x4d0
10661 #define ALT_GIC_DIST_GICD_IPRIORITYR53_FLD_LSB 0
10663 #define ALT_GIC_DIST_GICD_IPRIORITYR53_FLD_MSB 31
10665 #define ALT_GIC_DIST_GICD_IPRIORITYR53_FLD_WIDTH 32
10667 #define ALT_GIC_DIST_GICD_IPRIORITYR53_FLD_SET_MSK 0xffffffff
10669 #define ALT_GIC_DIST_GICD_IPRIORITYR53_FLD_CLR_MSK 0x00000000
10671 #define ALT_GIC_DIST_GICD_IPRIORITYR53_FLD_RESET 0x0
10673 #define ALT_GIC_DIST_GICD_IPRIORITYR53_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10675 #define ALT_GIC_DIST_GICD_IPRIORITYR53_FLD_SET(value) (((value) << 0) & 0xffffffff)
10677 #ifndef __ASSEMBLY__
10689 struct ALT_GIC_DIST_GICD_IPRIORITYR53_s
10691 volatile uint32_t fld : 32;
10695 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR53_s ALT_GIC_DIST_GICD_IPRIORITYR53_t;
10699 #define ALT_GIC_DIST_GICD_IPRIORITYR53_RESET 0x00000000
10701 #define ALT_GIC_DIST_GICD_IPRIORITYR53_OFST 0x4d4
10724 #define ALT_GIC_DIST_GICD_IPRIORITYR54_FLD_LSB 0
10726 #define ALT_GIC_DIST_GICD_IPRIORITYR54_FLD_MSB 31
10728 #define ALT_GIC_DIST_GICD_IPRIORITYR54_FLD_WIDTH 32
10730 #define ALT_GIC_DIST_GICD_IPRIORITYR54_FLD_SET_MSK 0xffffffff
10732 #define ALT_GIC_DIST_GICD_IPRIORITYR54_FLD_CLR_MSK 0x00000000
10734 #define ALT_GIC_DIST_GICD_IPRIORITYR54_FLD_RESET 0x0
10736 #define ALT_GIC_DIST_GICD_IPRIORITYR54_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10738 #define ALT_GIC_DIST_GICD_IPRIORITYR54_FLD_SET(value) (((value) << 0) & 0xffffffff)
10740 #ifndef __ASSEMBLY__
10752 struct ALT_GIC_DIST_GICD_IPRIORITYR54_s
10754 volatile uint32_t fld : 32;
10758 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR54_s ALT_GIC_DIST_GICD_IPRIORITYR54_t;
10762 #define ALT_GIC_DIST_GICD_IPRIORITYR54_RESET 0x00000000
10764 #define ALT_GIC_DIST_GICD_IPRIORITYR54_OFST 0x4d8
10787 #define ALT_GIC_DIST_GICD_IPRIORITYR55_FLD_LSB 0
10789 #define ALT_GIC_DIST_GICD_IPRIORITYR55_FLD_MSB 31
10791 #define ALT_GIC_DIST_GICD_IPRIORITYR55_FLD_WIDTH 32
10793 #define ALT_GIC_DIST_GICD_IPRIORITYR55_FLD_SET_MSK 0xffffffff
10795 #define ALT_GIC_DIST_GICD_IPRIORITYR55_FLD_CLR_MSK 0x00000000
10797 #define ALT_GIC_DIST_GICD_IPRIORITYR55_FLD_RESET 0x0
10799 #define ALT_GIC_DIST_GICD_IPRIORITYR55_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10801 #define ALT_GIC_DIST_GICD_IPRIORITYR55_FLD_SET(value) (((value) << 0) & 0xffffffff)
10803 #ifndef __ASSEMBLY__
10815 struct ALT_GIC_DIST_GICD_IPRIORITYR55_s
10817 volatile uint32_t fld : 32;
10821 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR55_s ALT_GIC_DIST_GICD_IPRIORITYR55_t;
10825 #define ALT_GIC_DIST_GICD_IPRIORITYR55_RESET 0x00000000
10827 #define ALT_GIC_DIST_GICD_IPRIORITYR55_OFST 0x4dc
10850 #define ALT_GIC_DIST_GICD_IPRIORITYR56_FLD_LSB 0
10852 #define ALT_GIC_DIST_GICD_IPRIORITYR56_FLD_MSB 31
10854 #define ALT_GIC_DIST_GICD_IPRIORITYR56_FLD_WIDTH 32
10856 #define ALT_GIC_DIST_GICD_IPRIORITYR56_FLD_SET_MSK 0xffffffff
10858 #define ALT_GIC_DIST_GICD_IPRIORITYR56_FLD_CLR_MSK 0x00000000
10860 #define ALT_GIC_DIST_GICD_IPRIORITYR56_FLD_RESET 0x0
10862 #define ALT_GIC_DIST_GICD_IPRIORITYR56_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10864 #define ALT_GIC_DIST_GICD_IPRIORITYR56_FLD_SET(value) (((value) << 0) & 0xffffffff)
10866 #ifndef __ASSEMBLY__
10878 struct ALT_GIC_DIST_GICD_IPRIORITYR56_s
10880 volatile uint32_t fld : 32;
10884 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR56_s ALT_GIC_DIST_GICD_IPRIORITYR56_t;
10888 #define ALT_GIC_DIST_GICD_IPRIORITYR56_RESET 0x00000000
10890 #define ALT_GIC_DIST_GICD_IPRIORITYR56_OFST 0x4e0
10913 #define ALT_GIC_DIST_GICD_IPRIORITYR57_FLD_LSB 0
10915 #define ALT_GIC_DIST_GICD_IPRIORITYR57_FLD_MSB 31
10917 #define ALT_GIC_DIST_GICD_IPRIORITYR57_FLD_WIDTH 32
10919 #define ALT_GIC_DIST_GICD_IPRIORITYR57_FLD_SET_MSK 0xffffffff
10921 #define ALT_GIC_DIST_GICD_IPRIORITYR57_FLD_CLR_MSK 0x00000000
10923 #define ALT_GIC_DIST_GICD_IPRIORITYR57_FLD_RESET 0x0
10925 #define ALT_GIC_DIST_GICD_IPRIORITYR57_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10927 #define ALT_GIC_DIST_GICD_IPRIORITYR57_FLD_SET(value) (((value) << 0) & 0xffffffff)
10929 #ifndef __ASSEMBLY__
10941 struct ALT_GIC_DIST_GICD_IPRIORITYR57_s
10943 volatile uint32_t fld : 32;
10947 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR57_s ALT_GIC_DIST_GICD_IPRIORITYR57_t;
10951 #define ALT_GIC_DIST_GICD_IPRIORITYR57_RESET 0x00000000
10953 #define ALT_GIC_DIST_GICD_IPRIORITYR57_OFST 0x4e4
10976 #define ALT_GIC_DIST_GICD_IPRIORITYR58_FLD_LSB 0
10978 #define ALT_GIC_DIST_GICD_IPRIORITYR58_FLD_MSB 31
10980 #define ALT_GIC_DIST_GICD_IPRIORITYR58_FLD_WIDTH 32
10982 #define ALT_GIC_DIST_GICD_IPRIORITYR58_FLD_SET_MSK 0xffffffff
10984 #define ALT_GIC_DIST_GICD_IPRIORITYR58_FLD_CLR_MSK 0x00000000
10986 #define ALT_GIC_DIST_GICD_IPRIORITYR58_FLD_RESET 0x0
10988 #define ALT_GIC_DIST_GICD_IPRIORITYR58_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10990 #define ALT_GIC_DIST_GICD_IPRIORITYR58_FLD_SET(value) (((value) << 0) & 0xffffffff)
10992 #ifndef __ASSEMBLY__
11004 struct ALT_GIC_DIST_GICD_IPRIORITYR58_s
11006 volatile uint32_t fld : 32;
11010 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR58_s ALT_GIC_DIST_GICD_IPRIORITYR58_t;
11014 #define ALT_GIC_DIST_GICD_IPRIORITYR58_RESET 0x00000000
11016 #define ALT_GIC_DIST_GICD_IPRIORITYR58_OFST 0x4e8
11039 #define ALT_GIC_DIST_GICD_IPRIORITYR59_FLD_LSB 0
11041 #define ALT_GIC_DIST_GICD_IPRIORITYR59_FLD_MSB 31
11043 #define ALT_GIC_DIST_GICD_IPRIORITYR59_FLD_WIDTH 32
11045 #define ALT_GIC_DIST_GICD_IPRIORITYR59_FLD_SET_MSK 0xffffffff
11047 #define ALT_GIC_DIST_GICD_IPRIORITYR59_FLD_CLR_MSK 0x00000000
11049 #define ALT_GIC_DIST_GICD_IPRIORITYR59_FLD_RESET 0x0
11051 #define ALT_GIC_DIST_GICD_IPRIORITYR59_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11053 #define ALT_GIC_DIST_GICD_IPRIORITYR59_FLD_SET(value) (((value) << 0) & 0xffffffff)
11055 #ifndef __ASSEMBLY__
11067 struct ALT_GIC_DIST_GICD_IPRIORITYR59_s
11069 volatile uint32_t fld : 32;
11073 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR59_s ALT_GIC_DIST_GICD_IPRIORITYR59_t;
11077 #define ALT_GIC_DIST_GICD_IPRIORITYR59_RESET 0x00000000
11079 #define ALT_GIC_DIST_GICD_IPRIORITYR59_OFST 0x4ec
11102 #define ALT_GIC_DIST_GICD_IPRIORITYR60_FLD_LSB 0
11104 #define ALT_GIC_DIST_GICD_IPRIORITYR60_FLD_MSB 31
11106 #define ALT_GIC_DIST_GICD_IPRIORITYR60_FLD_WIDTH 32
11108 #define ALT_GIC_DIST_GICD_IPRIORITYR60_FLD_SET_MSK 0xffffffff
11110 #define ALT_GIC_DIST_GICD_IPRIORITYR60_FLD_CLR_MSK 0x00000000
11112 #define ALT_GIC_DIST_GICD_IPRIORITYR60_FLD_RESET 0x0
11114 #define ALT_GIC_DIST_GICD_IPRIORITYR60_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11116 #define ALT_GIC_DIST_GICD_IPRIORITYR60_FLD_SET(value) (((value) << 0) & 0xffffffff)
11118 #ifndef __ASSEMBLY__
11130 struct ALT_GIC_DIST_GICD_IPRIORITYR60_s
11132 volatile uint32_t fld : 32;
11136 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR60_s ALT_GIC_DIST_GICD_IPRIORITYR60_t;
11140 #define ALT_GIC_DIST_GICD_IPRIORITYR60_RESET 0x00000000
11142 #define ALT_GIC_DIST_GICD_IPRIORITYR60_OFST 0x4f0
11165 #define ALT_GIC_DIST_GICD_IPRIORITYR61_FLD_LSB 0
11167 #define ALT_GIC_DIST_GICD_IPRIORITYR61_FLD_MSB 31
11169 #define ALT_GIC_DIST_GICD_IPRIORITYR61_FLD_WIDTH 32
11171 #define ALT_GIC_DIST_GICD_IPRIORITYR61_FLD_SET_MSK 0xffffffff
11173 #define ALT_GIC_DIST_GICD_IPRIORITYR61_FLD_CLR_MSK 0x00000000
11175 #define ALT_GIC_DIST_GICD_IPRIORITYR61_FLD_RESET 0x0
11177 #define ALT_GIC_DIST_GICD_IPRIORITYR61_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11179 #define ALT_GIC_DIST_GICD_IPRIORITYR61_FLD_SET(value) (((value) << 0) & 0xffffffff)
11181 #ifndef __ASSEMBLY__
11193 struct ALT_GIC_DIST_GICD_IPRIORITYR61_s
11195 volatile uint32_t fld : 32;
11199 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR61_s ALT_GIC_DIST_GICD_IPRIORITYR61_t;
11203 #define ALT_GIC_DIST_GICD_IPRIORITYR61_RESET 0x00000000
11205 #define ALT_GIC_DIST_GICD_IPRIORITYR61_OFST 0x4f4
11228 #define ALT_GIC_DIST_GICD_IPRIORITYR62_FLD_LSB 0
11230 #define ALT_GIC_DIST_GICD_IPRIORITYR62_FLD_MSB 31
11232 #define ALT_GIC_DIST_GICD_IPRIORITYR62_FLD_WIDTH 32
11234 #define ALT_GIC_DIST_GICD_IPRIORITYR62_FLD_SET_MSK 0xffffffff
11236 #define ALT_GIC_DIST_GICD_IPRIORITYR62_FLD_CLR_MSK 0x00000000
11238 #define ALT_GIC_DIST_GICD_IPRIORITYR62_FLD_RESET 0x0
11240 #define ALT_GIC_DIST_GICD_IPRIORITYR62_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11242 #define ALT_GIC_DIST_GICD_IPRIORITYR62_FLD_SET(value) (((value) << 0) & 0xffffffff)
11244 #ifndef __ASSEMBLY__
11256 struct ALT_GIC_DIST_GICD_IPRIORITYR62_s
11258 volatile uint32_t fld : 32;
11262 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR62_s ALT_GIC_DIST_GICD_IPRIORITYR62_t;
11266 #define ALT_GIC_DIST_GICD_IPRIORITYR62_RESET 0x00000000
11268 #define ALT_GIC_DIST_GICD_IPRIORITYR62_OFST 0x4f8
11291 #define ALT_GIC_DIST_GICD_IPRIORITYR63_FLD_LSB 0
11293 #define ALT_GIC_DIST_GICD_IPRIORITYR63_FLD_MSB 31
11295 #define ALT_GIC_DIST_GICD_IPRIORITYR63_FLD_WIDTH 32
11297 #define ALT_GIC_DIST_GICD_IPRIORITYR63_FLD_SET_MSK 0xffffffff
11299 #define ALT_GIC_DIST_GICD_IPRIORITYR63_FLD_CLR_MSK 0x00000000
11301 #define ALT_GIC_DIST_GICD_IPRIORITYR63_FLD_RESET 0x0
11303 #define ALT_GIC_DIST_GICD_IPRIORITYR63_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11305 #define ALT_GIC_DIST_GICD_IPRIORITYR63_FLD_SET(value) (((value) << 0) & 0xffffffff)
11307 #ifndef __ASSEMBLY__
11319 struct ALT_GIC_DIST_GICD_IPRIORITYR63_s
11321 volatile uint32_t fld : 32;
11325 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR63_s ALT_GIC_DIST_GICD_IPRIORITYR63_t;
11329 #define ALT_GIC_DIST_GICD_IPRIORITYR63_RESET 0x00000000
11331 #define ALT_GIC_DIST_GICD_IPRIORITYR63_OFST 0x4fc
11354 #define ALT_GIC_DIST_GICD_IPRIORITYR64_FLD_LSB 0
11356 #define ALT_GIC_DIST_GICD_IPRIORITYR64_FLD_MSB 31
11358 #define ALT_GIC_DIST_GICD_IPRIORITYR64_FLD_WIDTH 32
11360 #define ALT_GIC_DIST_GICD_IPRIORITYR64_FLD_SET_MSK 0xffffffff
11362 #define ALT_GIC_DIST_GICD_IPRIORITYR64_FLD_CLR_MSK 0x00000000
11364 #define ALT_GIC_DIST_GICD_IPRIORITYR64_FLD_RESET 0x0
11366 #define ALT_GIC_DIST_GICD_IPRIORITYR64_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11368 #define ALT_GIC_DIST_GICD_IPRIORITYR64_FLD_SET(value) (((value) << 0) & 0xffffffff)
11370 #ifndef __ASSEMBLY__
11382 struct ALT_GIC_DIST_GICD_IPRIORITYR64_s
11384 volatile uint32_t fld : 32;
11388 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR64_s ALT_GIC_DIST_GICD_IPRIORITYR64_t;
11392 #define ALT_GIC_DIST_GICD_IPRIORITYR64_RESET 0x00000000
11394 #define ALT_GIC_DIST_GICD_IPRIORITYR64_OFST 0x500
11417 #define ALT_GIC_DIST_GICD_IPRIORITYR65_FLD_LSB 0
11419 #define ALT_GIC_DIST_GICD_IPRIORITYR65_FLD_MSB 31
11421 #define ALT_GIC_DIST_GICD_IPRIORITYR65_FLD_WIDTH 32
11423 #define ALT_GIC_DIST_GICD_IPRIORITYR65_FLD_SET_MSK 0xffffffff
11425 #define ALT_GIC_DIST_GICD_IPRIORITYR65_FLD_CLR_MSK 0x00000000
11427 #define ALT_GIC_DIST_GICD_IPRIORITYR65_FLD_RESET 0x0
11429 #define ALT_GIC_DIST_GICD_IPRIORITYR65_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11431 #define ALT_GIC_DIST_GICD_IPRIORITYR65_FLD_SET(value) (((value) << 0) & 0xffffffff)
11433 #ifndef __ASSEMBLY__
11445 struct ALT_GIC_DIST_GICD_IPRIORITYR65_s
11447 volatile uint32_t fld : 32;
11451 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR65_s ALT_GIC_DIST_GICD_IPRIORITYR65_t;
11455 #define ALT_GIC_DIST_GICD_IPRIORITYR65_RESET 0x00000000
11457 #define ALT_GIC_DIST_GICD_IPRIORITYR65_OFST 0x504
11480 #define ALT_GIC_DIST_GICD_IPRIORITYR66_FLD_LSB 0
11482 #define ALT_GIC_DIST_GICD_IPRIORITYR66_FLD_MSB 31
11484 #define ALT_GIC_DIST_GICD_IPRIORITYR66_FLD_WIDTH 32
11486 #define ALT_GIC_DIST_GICD_IPRIORITYR66_FLD_SET_MSK 0xffffffff
11488 #define ALT_GIC_DIST_GICD_IPRIORITYR66_FLD_CLR_MSK 0x00000000
11490 #define ALT_GIC_DIST_GICD_IPRIORITYR66_FLD_RESET 0x0
11492 #define ALT_GIC_DIST_GICD_IPRIORITYR66_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11494 #define ALT_GIC_DIST_GICD_IPRIORITYR66_FLD_SET(value) (((value) << 0) & 0xffffffff)
11496 #ifndef __ASSEMBLY__
11508 struct ALT_GIC_DIST_GICD_IPRIORITYR66_s
11510 volatile uint32_t fld : 32;
11514 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR66_s ALT_GIC_DIST_GICD_IPRIORITYR66_t;
11518 #define ALT_GIC_DIST_GICD_IPRIORITYR66_RESET 0x00000000
11520 #define ALT_GIC_DIST_GICD_IPRIORITYR66_OFST 0x508
11543 #define ALT_GIC_DIST_GICD_IPRIORITYR67_FLD_LSB 0
11545 #define ALT_GIC_DIST_GICD_IPRIORITYR67_FLD_MSB 31
11547 #define ALT_GIC_DIST_GICD_IPRIORITYR67_FLD_WIDTH 32
11549 #define ALT_GIC_DIST_GICD_IPRIORITYR67_FLD_SET_MSK 0xffffffff
11551 #define ALT_GIC_DIST_GICD_IPRIORITYR67_FLD_CLR_MSK 0x00000000
11553 #define ALT_GIC_DIST_GICD_IPRIORITYR67_FLD_RESET 0x0
11555 #define ALT_GIC_DIST_GICD_IPRIORITYR67_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11557 #define ALT_GIC_DIST_GICD_IPRIORITYR67_FLD_SET(value) (((value) << 0) & 0xffffffff)
11559 #ifndef __ASSEMBLY__
11571 struct ALT_GIC_DIST_GICD_IPRIORITYR67_s
11573 volatile uint32_t fld : 32;
11577 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR67_s ALT_GIC_DIST_GICD_IPRIORITYR67_t;
11581 #define ALT_GIC_DIST_GICD_IPRIORITYR67_RESET 0x00000000
11583 #define ALT_GIC_DIST_GICD_IPRIORITYR67_OFST 0x50c
11606 #define ALT_GIC_DIST_GICD_IPRIORITYR68_FLD_LSB 0
11608 #define ALT_GIC_DIST_GICD_IPRIORITYR68_FLD_MSB 31
11610 #define ALT_GIC_DIST_GICD_IPRIORITYR68_FLD_WIDTH 32
11612 #define ALT_GIC_DIST_GICD_IPRIORITYR68_FLD_SET_MSK 0xffffffff
11614 #define ALT_GIC_DIST_GICD_IPRIORITYR68_FLD_CLR_MSK 0x00000000
11616 #define ALT_GIC_DIST_GICD_IPRIORITYR68_FLD_RESET 0x0
11618 #define ALT_GIC_DIST_GICD_IPRIORITYR68_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11620 #define ALT_GIC_DIST_GICD_IPRIORITYR68_FLD_SET(value) (((value) << 0) & 0xffffffff)
11622 #ifndef __ASSEMBLY__
11634 struct ALT_GIC_DIST_GICD_IPRIORITYR68_s
11636 volatile uint32_t fld : 32;
11640 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR68_s ALT_GIC_DIST_GICD_IPRIORITYR68_t;
11644 #define ALT_GIC_DIST_GICD_IPRIORITYR68_RESET 0x00000000
11646 #define ALT_GIC_DIST_GICD_IPRIORITYR68_OFST 0x510
11669 #define ALT_GIC_DIST_GICD_IPRIORITYR69_FLD_LSB 0
11671 #define ALT_GIC_DIST_GICD_IPRIORITYR69_FLD_MSB 31
11673 #define ALT_GIC_DIST_GICD_IPRIORITYR69_FLD_WIDTH 32
11675 #define ALT_GIC_DIST_GICD_IPRIORITYR69_FLD_SET_MSK 0xffffffff
11677 #define ALT_GIC_DIST_GICD_IPRIORITYR69_FLD_CLR_MSK 0x00000000
11679 #define ALT_GIC_DIST_GICD_IPRIORITYR69_FLD_RESET 0x0
11681 #define ALT_GIC_DIST_GICD_IPRIORITYR69_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11683 #define ALT_GIC_DIST_GICD_IPRIORITYR69_FLD_SET(value) (((value) << 0) & 0xffffffff)
11685 #ifndef __ASSEMBLY__
11697 struct ALT_GIC_DIST_GICD_IPRIORITYR69_s
11699 volatile uint32_t fld : 32;
11703 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR69_s ALT_GIC_DIST_GICD_IPRIORITYR69_t;
11707 #define ALT_GIC_DIST_GICD_IPRIORITYR69_RESET 0x00000000
11709 #define ALT_GIC_DIST_GICD_IPRIORITYR69_OFST 0x514
11732 #define ALT_GIC_DIST_GICD_IPRIORITYR70_FLD_LSB 0
11734 #define ALT_GIC_DIST_GICD_IPRIORITYR70_FLD_MSB 31
11736 #define ALT_GIC_DIST_GICD_IPRIORITYR70_FLD_WIDTH 32
11738 #define ALT_GIC_DIST_GICD_IPRIORITYR70_FLD_SET_MSK 0xffffffff
11740 #define ALT_GIC_DIST_GICD_IPRIORITYR70_FLD_CLR_MSK 0x00000000
11742 #define ALT_GIC_DIST_GICD_IPRIORITYR70_FLD_RESET 0x0
11744 #define ALT_GIC_DIST_GICD_IPRIORITYR70_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11746 #define ALT_GIC_DIST_GICD_IPRIORITYR70_FLD_SET(value) (((value) << 0) & 0xffffffff)
11748 #ifndef __ASSEMBLY__
11760 struct ALT_GIC_DIST_GICD_IPRIORITYR70_s
11762 volatile uint32_t fld : 32;
11766 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR70_s ALT_GIC_DIST_GICD_IPRIORITYR70_t;
11770 #define ALT_GIC_DIST_GICD_IPRIORITYR70_RESET 0x00000000
11772 #define ALT_GIC_DIST_GICD_IPRIORITYR70_OFST 0x518
11795 #define ALT_GIC_DIST_GICD_IPRIORITYR71_FLD_LSB 0
11797 #define ALT_GIC_DIST_GICD_IPRIORITYR71_FLD_MSB 31
11799 #define ALT_GIC_DIST_GICD_IPRIORITYR71_FLD_WIDTH 32
11801 #define ALT_GIC_DIST_GICD_IPRIORITYR71_FLD_SET_MSK 0xffffffff
11803 #define ALT_GIC_DIST_GICD_IPRIORITYR71_FLD_CLR_MSK 0x00000000
11805 #define ALT_GIC_DIST_GICD_IPRIORITYR71_FLD_RESET 0x0
11807 #define ALT_GIC_DIST_GICD_IPRIORITYR71_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11809 #define ALT_GIC_DIST_GICD_IPRIORITYR71_FLD_SET(value) (((value) << 0) & 0xffffffff)
11811 #ifndef __ASSEMBLY__
11823 struct ALT_GIC_DIST_GICD_IPRIORITYR71_s
11825 volatile uint32_t fld : 32;
11829 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR71_s ALT_GIC_DIST_GICD_IPRIORITYR71_t;
11833 #define ALT_GIC_DIST_GICD_IPRIORITYR71_RESET 0x00000000
11835 #define ALT_GIC_DIST_GICD_IPRIORITYR71_OFST 0x51c
11858 #define ALT_GIC_DIST_GICD_IPRIORITYR72_FLD_LSB 0
11860 #define ALT_GIC_DIST_GICD_IPRIORITYR72_FLD_MSB 31
11862 #define ALT_GIC_DIST_GICD_IPRIORITYR72_FLD_WIDTH 32
11864 #define ALT_GIC_DIST_GICD_IPRIORITYR72_FLD_SET_MSK 0xffffffff
11866 #define ALT_GIC_DIST_GICD_IPRIORITYR72_FLD_CLR_MSK 0x00000000
11868 #define ALT_GIC_DIST_GICD_IPRIORITYR72_FLD_RESET 0x0
11870 #define ALT_GIC_DIST_GICD_IPRIORITYR72_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11872 #define ALT_GIC_DIST_GICD_IPRIORITYR72_FLD_SET(value) (((value) << 0) & 0xffffffff)
11874 #ifndef __ASSEMBLY__
11886 struct ALT_GIC_DIST_GICD_IPRIORITYR72_s
11888 volatile uint32_t fld : 32;
11892 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR72_s ALT_GIC_DIST_GICD_IPRIORITYR72_t;
11896 #define ALT_GIC_DIST_GICD_IPRIORITYR72_RESET 0x00000000
11898 #define ALT_GIC_DIST_GICD_IPRIORITYR72_OFST 0x520
11921 #define ALT_GIC_DIST_GICD_IPRIORITYR73_FLD_LSB 0
11923 #define ALT_GIC_DIST_GICD_IPRIORITYR73_FLD_MSB 31
11925 #define ALT_GIC_DIST_GICD_IPRIORITYR73_FLD_WIDTH 32
11927 #define ALT_GIC_DIST_GICD_IPRIORITYR73_FLD_SET_MSK 0xffffffff
11929 #define ALT_GIC_DIST_GICD_IPRIORITYR73_FLD_CLR_MSK 0x00000000
11931 #define ALT_GIC_DIST_GICD_IPRIORITYR73_FLD_RESET 0x0
11933 #define ALT_GIC_DIST_GICD_IPRIORITYR73_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11935 #define ALT_GIC_DIST_GICD_IPRIORITYR73_FLD_SET(value) (((value) << 0) & 0xffffffff)
11937 #ifndef __ASSEMBLY__
11949 struct ALT_GIC_DIST_GICD_IPRIORITYR73_s
11951 volatile uint32_t fld : 32;
11955 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR73_s ALT_GIC_DIST_GICD_IPRIORITYR73_t;
11959 #define ALT_GIC_DIST_GICD_IPRIORITYR73_RESET 0x00000000
11961 #define ALT_GIC_DIST_GICD_IPRIORITYR73_OFST 0x524
11984 #define ALT_GIC_DIST_GICD_IPRIORITYR74_FLD_LSB 0
11986 #define ALT_GIC_DIST_GICD_IPRIORITYR74_FLD_MSB 31
11988 #define ALT_GIC_DIST_GICD_IPRIORITYR74_FLD_WIDTH 32
11990 #define ALT_GIC_DIST_GICD_IPRIORITYR74_FLD_SET_MSK 0xffffffff
11992 #define ALT_GIC_DIST_GICD_IPRIORITYR74_FLD_CLR_MSK 0x00000000
11994 #define ALT_GIC_DIST_GICD_IPRIORITYR74_FLD_RESET 0x0
11996 #define ALT_GIC_DIST_GICD_IPRIORITYR74_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11998 #define ALT_GIC_DIST_GICD_IPRIORITYR74_FLD_SET(value) (((value) << 0) & 0xffffffff)
12000 #ifndef __ASSEMBLY__
12012 struct ALT_GIC_DIST_GICD_IPRIORITYR74_s
12014 volatile uint32_t fld : 32;
12018 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR74_s ALT_GIC_DIST_GICD_IPRIORITYR74_t;
12022 #define ALT_GIC_DIST_GICD_IPRIORITYR74_RESET 0x00000000
12024 #define ALT_GIC_DIST_GICD_IPRIORITYR74_OFST 0x528
12047 #define ALT_GIC_DIST_GICD_IPRIORITYR75_FLD_LSB 0
12049 #define ALT_GIC_DIST_GICD_IPRIORITYR75_FLD_MSB 31
12051 #define ALT_GIC_DIST_GICD_IPRIORITYR75_FLD_WIDTH 32
12053 #define ALT_GIC_DIST_GICD_IPRIORITYR75_FLD_SET_MSK 0xffffffff
12055 #define ALT_GIC_DIST_GICD_IPRIORITYR75_FLD_CLR_MSK 0x00000000
12057 #define ALT_GIC_DIST_GICD_IPRIORITYR75_FLD_RESET 0x0
12059 #define ALT_GIC_DIST_GICD_IPRIORITYR75_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12061 #define ALT_GIC_DIST_GICD_IPRIORITYR75_FLD_SET(value) (((value) << 0) & 0xffffffff)
12063 #ifndef __ASSEMBLY__
12075 struct ALT_GIC_DIST_GICD_IPRIORITYR75_s
12077 volatile uint32_t fld : 32;
12081 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR75_s ALT_GIC_DIST_GICD_IPRIORITYR75_t;
12085 #define ALT_GIC_DIST_GICD_IPRIORITYR75_RESET 0x00000000
12087 #define ALT_GIC_DIST_GICD_IPRIORITYR75_OFST 0x52c
12110 #define ALT_GIC_DIST_GICD_IPRIORITYR76_FLD_LSB 0
12112 #define ALT_GIC_DIST_GICD_IPRIORITYR76_FLD_MSB 31
12114 #define ALT_GIC_DIST_GICD_IPRIORITYR76_FLD_WIDTH 32
12116 #define ALT_GIC_DIST_GICD_IPRIORITYR76_FLD_SET_MSK 0xffffffff
12118 #define ALT_GIC_DIST_GICD_IPRIORITYR76_FLD_CLR_MSK 0x00000000
12120 #define ALT_GIC_DIST_GICD_IPRIORITYR76_FLD_RESET 0x0
12122 #define ALT_GIC_DIST_GICD_IPRIORITYR76_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12124 #define ALT_GIC_DIST_GICD_IPRIORITYR76_FLD_SET(value) (((value) << 0) & 0xffffffff)
12126 #ifndef __ASSEMBLY__
12138 struct ALT_GIC_DIST_GICD_IPRIORITYR76_s
12140 volatile uint32_t fld : 32;
12144 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR76_s ALT_GIC_DIST_GICD_IPRIORITYR76_t;
12148 #define ALT_GIC_DIST_GICD_IPRIORITYR76_RESET 0x00000000
12150 #define ALT_GIC_DIST_GICD_IPRIORITYR76_OFST 0x530
12173 #define ALT_GIC_DIST_GICD_IPRIORITYR77_FLD_LSB 0
12175 #define ALT_GIC_DIST_GICD_IPRIORITYR77_FLD_MSB 31
12177 #define ALT_GIC_DIST_GICD_IPRIORITYR77_FLD_WIDTH 32
12179 #define ALT_GIC_DIST_GICD_IPRIORITYR77_FLD_SET_MSK 0xffffffff
12181 #define ALT_GIC_DIST_GICD_IPRIORITYR77_FLD_CLR_MSK 0x00000000
12183 #define ALT_GIC_DIST_GICD_IPRIORITYR77_FLD_RESET 0x0
12185 #define ALT_GIC_DIST_GICD_IPRIORITYR77_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12187 #define ALT_GIC_DIST_GICD_IPRIORITYR77_FLD_SET(value) (((value) << 0) & 0xffffffff)
12189 #ifndef __ASSEMBLY__
12201 struct ALT_GIC_DIST_GICD_IPRIORITYR77_s
12203 volatile uint32_t fld : 32;
12207 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR77_s ALT_GIC_DIST_GICD_IPRIORITYR77_t;
12211 #define ALT_GIC_DIST_GICD_IPRIORITYR77_RESET 0x00000000
12213 #define ALT_GIC_DIST_GICD_IPRIORITYR77_OFST 0x534
12236 #define ALT_GIC_DIST_GICD_IPRIORITYR78_FLD_LSB 0
12238 #define ALT_GIC_DIST_GICD_IPRIORITYR78_FLD_MSB 31
12240 #define ALT_GIC_DIST_GICD_IPRIORITYR78_FLD_WIDTH 32
12242 #define ALT_GIC_DIST_GICD_IPRIORITYR78_FLD_SET_MSK 0xffffffff
12244 #define ALT_GIC_DIST_GICD_IPRIORITYR78_FLD_CLR_MSK 0x00000000
12246 #define ALT_GIC_DIST_GICD_IPRIORITYR78_FLD_RESET 0x0
12248 #define ALT_GIC_DIST_GICD_IPRIORITYR78_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12250 #define ALT_GIC_DIST_GICD_IPRIORITYR78_FLD_SET(value) (((value) << 0) & 0xffffffff)
12252 #ifndef __ASSEMBLY__
12264 struct ALT_GIC_DIST_GICD_IPRIORITYR78_s
12266 volatile uint32_t fld : 32;
12270 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR78_s ALT_GIC_DIST_GICD_IPRIORITYR78_t;
12274 #define ALT_GIC_DIST_GICD_IPRIORITYR78_RESET 0x00000000
12276 #define ALT_GIC_DIST_GICD_IPRIORITYR78_OFST 0x538
12299 #define ALT_GIC_DIST_GICD_IPRIORITYR79_FLD_LSB 0
12301 #define ALT_GIC_DIST_GICD_IPRIORITYR79_FLD_MSB 31
12303 #define ALT_GIC_DIST_GICD_IPRIORITYR79_FLD_WIDTH 32
12305 #define ALT_GIC_DIST_GICD_IPRIORITYR79_FLD_SET_MSK 0xffffffff
12307 #define ALT_GIC_DIST_GICD_IPRIORITYR79_FLD_CLR_MSK 0x00000000
12309 #define ALT_GIC_DIST_GICD_IPRIORITYR79_FLD_RESET 0x0
12311 #define ALT_GIC_DIST_GICD_IPRIORITYR79_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12313 #define ALT_GIC_DIST_GICD_IPRIORITYR79_FLD_SET(value) (((value) << 0) & 0xffffffff)
12315 #ifndef __ASSEMBLY__
12327 struct ALT_GIC_DIST_GICD_IPRIORITYR79_s
12329 volatile uint32_t fld : 32;
12333 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR79_s ALT_GIC_DIST_GICD_IPRIORITYR79_t;
12337 #define ALT_GIC_DIST_GICD_IPRIORITYR79_RESET 0x00000000
12339 #define ALT_GIC_DIST_GICD_IPRIORITYR79_OFST 0x53c
12362 #define ALT_GIC_DIST_GICD_IPRIORITYR80_FLD_LSB 0
12364 #define ALT_GIC_DIST_GICD_IPRIORITYR80_FLD_MSB 31
12366 #define ALT_GIC_DIST_GICD_IPRIORITYR80_FLD_WIDTH 32
12368 #define ALT_GIC_DIST_GICD_IPRIORITYR80_FLD_SET_MSK 0xffffffff
12370 #define ALT_GIC_DIST_GICD_IPRIORITYR80_FLD_CLR_MSK 0x00000000
12372 #define ALT_GIC_DIST_GICD_IPRIORITYR80_FLD_RESET 0x0
12374 #define ALT_GIC_DIST_GICD_IPRIORITYR80_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12376 #define ALT_GIC_DIST_GICD_IPRIORITYR80_FLD_SET(value) (((value) << 0) & 0xffffffff)
12378 #ifndef __ASSEMBLY__
12390 struct ALT_GIC_DIST_GICD_IPRIORITYR80_s
12392 volatile uint32_t fld : 32;
12396 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR80_s ALT_GIC_DIST_GICD_IPRIORITYR80_t;
12400 #define ALT_GIC_DIST_GICD_IPRIORITYR80_RESET 0x00000000
12402 #define ALT_GIC_DIST_GICD_IPRIORITYR80_OFST 0x540
12425 #define ALT_GIC_DIST_GICD_IPRIORITYR81_FLD_LSB 0
12427 #define ALT_GIC_DIST_GICD_IPRIORITYR81_FLD_MSB 31
12429 #define ALT_GIC_DIST_GICD_IPRIORITYR81_FLD_WIDTH 32
12431 #define ALT_GIC_DIST_GICD_IPRIORITYR81_FLD_SET_MSK 0xffffffff
12433 #define ALT_GIC_DIST_GICD_IPRIORITYR81_FLD_CLR_MSK 0x00000000
12435 #define ALT_GIC_DIST_GICD_IPRIORITYR81_FLD_RESET 0x0
12437 #define ALT_GIC_DIST_GICD_IPRIORITYR81_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12439 #define ALT_GIC_DIST_GICD_IPRIORITYR81_FLD_SET(value) (((value) << 0) & 0xffffffff)
12441 #ifndef __ASSEMBLY__
12453 struct ALT_GIC_DIST_GICD_IPRIORITYR81_s
12455 volatile uint32_t fld : 32;
12459 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR81_s ALT_GIC_DIST_GICD_IPRIORITYR81_t;
12463 #define ALT_GIC_DIST_GICD_IPRIORITYR81_RESET 0x00000000
12465 #define ALT_GIC_DIST_GICD_IPRIORITYR81_OFST 0x544
12488 #define ALT_GIC_DIST_GICD_IPRIORITYR82_FLD_LSB 0
12490 #define ALT_GIC_DIST_GICD_IPRIORITYR82_FLD_MSB 31
12492 #define ALT_GIC_DIST_GICD_IPRIORITYR82_FLD_WIDTH 32
12494 #define ALT_GIC_DIST_GICD_IPRIORITYR82_FLD_SET_MSK 0xffffffff
12496 #define ALT_GIC_DIST_GICD_IPRIORITYR82_FLD_CLR_MSK 0x00000000
12498 #define ALT_GIC_DIST_GICD_IPRIORITYR82_FLD_RESET 0x0
12500 #define ALT_GIC_DIST_GICD_IPRIORITYR82_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12502 #define ALT_GIC_DIST_GICD_IPRIORITYR82_FLD_SET(value) (((value) << 0) & 0xffffffff)
12504 #ifndef __ASSEMBLY__
12516 struct ALT_GIC_DIST_GICD_IPRIORITYR82_s
12518 volatile uint32_t fld : 32;
12522 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR82_s ALT_GIC_DIST_GICD_IPRIORITYR82_t;
12526 #define ALT_GIC_DIST_GICD_IPRIORITYR82_RESET 0x00000000
12528 #define ALT_GIC_DIST_GICD_IPRIORITYR82_OFST 0x548
12551 #define ALT_GIC_DIST_GICD_IPRIORITYR83_FLD_LSB 0
12553 #define ALT_GIC_DIST_GICD_IPRIORITYR83_FLD_MSB 31
12555 #define ALT_GIC_DIST_GICD_IPRIORITYR83_FLD_WIDTH 32
12557 #define ALT_GIC_DIST_GICD_IPRIORITYR83_FLD_SET_MSK 0xffffffff
12559 #define ALT_GIC_DIST_GICD_IPRIORITYR83_FLD_CLR_MSK 0x00000000
12561 #define ALT_GIC_DIST_GICD_IPRIORITYR83_FLD_RESET 0x0
12563 #define ALT_GIC_DIST_GICD_IPRIORITYR83_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12565 #define ALT_GIC_DIST_GICD_IPRIORITYR83_FLD_SET(value) (((value) << 0) & 0xffffffff)
12567 #ifndef __ASSEMBLY__
12579 struct ALT_GIC_DIST_GICD_IPRIORITYR83_s
12581 volatile uint32_t fld : 32;
12585 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR83_s ALT_GIC_DIST_GICD_IPRIORITYR83_t;
12589 #define ALT_GIC_DIST_GICD_IPRIORITYR83_RESET 0x00000000
12591 #define ALT_GIC_DIST_GICD_IPRIORITYR83_OFST 0x54c
12614 #define ALT_GIC_DIST_GICD_IPRIORITYR84_FLD_LSB 0
12616 #define ALT_GIC_DIST_GICD_IPRIORITYR84_FLD_MSB 31
12618 #define ALT_GIC_DIST_GICD_IPRIORITYR84_FLD_WIDTH 32
12620 #define ALT_GIC_DIST_GICD_IPRIORITYR84_FLD_SET_MSK 0xffffffff
12622 #define ALT_GIC_DIST_GICD_IPRIORITYR84_FLD_CLR_MSK 0x00000000
12624 #define ALT_GIC_DIST_GICD_IPRIORITYR84_FLD_RESET 0x0
12626 #define ALT_GIC_DIST_GICD_IPRIORITYR84_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12628 #define ALT_GIC_DIST_GICD_IPRIORITYR84_FLD_SET(value) (((value) << 0) & 0xffffffff)
12630 #ifndef __ASSEMBLY__
12642 struct ALT_GIC_DIST_GICD_IPRIORITYR84_s
12644 volatile uint32_t fld : 32;
12648 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR84_s ALT_GIC_DIST_GICD_IPRIORITYR84_t;
12652 #define ALT_GIC_DIST_GICD_IPRIORITYR84_RESET 0x00000000
12654 #define ALT_GIC_DIST_GICD_IPRIORITYR84_OFST 0x550
12677 #define ALT_GIC_DIST_GICD_IPRIORITYR85_FLD_LSB 0
12679 #define ALT_GIC_DIST_GICD_IPRIORITYR85_FLD_MSB 31
12681 #define ALT_GIC_DIST_GICD_IPRIORITYR85_FLD_WIDTH 32
12683 #define ALT_GIC_DIST_GICD_IPRIORITYR85_FLD_SET_MSK 0xffffffff
12685 #define ALT_GIC_DIST_GICD_IPRIORITYR85_FLD_CLR_MSK 0x00000000
12687 #define ALT_GIC_DIST_GICD_IPRIORITYR85_FLD_RESET 0x0
12689 #define ALT_GIC_DIST_GICD_IPRIORITYR85_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12691 #define ALT_GIC_DIST_GICD_IPRIORITYR85_FLD_SET(value) (((value) << 0) & 0xffffffff)
12693 #ifndef __ASSEMBLY__
12705 struct ALT_GIC_DIST_GICD_IPRIORITYR85_s
12707 volatile uint32_t fld : 32;
12711 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR85_s ALT_GIC_DIST_GICD_IPRIORITYR85_t;
12715 #define ALT_GIC_DIST_GICD_IPRIORITYR85_RESET 0x00000000
12717 #define ALT_GIC_DIST_GICD_IPRIORITYR85_OFST 0x554
12740 #define ALT_GIC_DIST_GICD_IPRIORITYR86_FLD_LSB 0
12742 #define ALT_GIC_DIST_GICD_IPRIORITYR86_FLD_MSB 31
12744 #define ALT_GIC_DIST_GICD_IPRIORITYR86_FLD_WIDTH 32
12746 #define ALT_GIC_DIST_GICD_IPRIORITYR86_FLD_SET_MSK 0xffffffff
12748 #define ALT_GIC_DIST_GICD_IPRIORITYR86_FLD_CLR_MSK 0x00000000
12750 #define ALT_GIC_DIST_GICD_IPRIORITYR86_FLD_RESET 0x0
12752 #define ALT_GIC_DIST_GICD_IPRIORITYR86_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12754 #define ALT_GIC_DIST_GICD_IPRIORITYR86_FLD_SET(value) (((value) << 0) & 0xffffffff)
12756 #ifndef __ASSEMBLY__
12768 struct ALT_GIC_DIST_GICD_IPRIORITYR86_s
12770 volatile uint32_t fld : 32;
12774 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR86_s ALT_GIC_DIST_GICD_IPRIORITYR86_t;
12778 #define ALT_GIC_DIST_GICD_IPRIORITYR86_RESET 0x00000000
12780 #define ALT_GIC_DIST_GICD_IPRIORITYR86_OFST 0x558
12803 #define ALT_GIC_DIST_GICD_IPRIORITYR87_FLD_LSB 0
12805 #define ALT_GIC_DIST_GICD_IPRIORITYR87_FLD_MSB 31
12807 #define ALT_GIC_DIST_GICD_IPRIORITYR87_FLD_WIDTH 32
12809 #define ALT_GIC_DIST_GICD_IPRIORITYR87_FLD_SET_MSK 0xffffffff
12811 #define ALT_GIC_DIST_GICD_IPRIORITYR87_FLD_CLR_MSK 0x00000000
12813 #define ALT_GIC_DIST_GICD_IPRIORITYR87_FLD_RESET 0x0
12815 #define ALT_GIC_DIST_GICD_IPRIORITYR87_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12817 #define ALT_GIC_DIST_GICD_IPRIORITYR87_FLD_SET(value) (((value) << 0) & 0xffffffff)
12819 #ifndef __ASSEMBLY__
12831 struct ALT_GIC_DIST_GICD_IPRIORITYR87_s
12833 volatile uint32_t fld : 32;
12837 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR87_s ALT_GIC_DIST_GICD_IPRIORITYR87_t;
12841 #define ALT_GIC_DIST_GICD_IPRIORITYR87_RESET 0x00000000
12843 #define ALT_GIC_DIST_GICD_IPRIORITYR87_OFST 0x55c
12866 #define ALT_GIC_DIST_GICD_IPRIORITYR88_FLD_LSB 0
12868 #define ALT_GIC_DIST_GICD_IPRIORITYR88_FLD_MSB 31
12870 #define ALT_GIC_DIST_GICD_IPRIORITYR88_FLD_WIDTH 32
12872 #define ALT_GIC_DIST_GICD_IPRIORITYR88_FLD_SET_MSK 0xffffffff
12874 #define ALT_GIC_DIST_GICD_IPRIORITYR88_FLD_CLR_MSK 0x00000000
12876 #define ALT_GIC_DIST_GICD_IPRIORITYR88_FLD_RESET 0x0
12878 #define ALT_GIC_DIST_GICD_IPRIORITYR88_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12880 #define ALT_GIC_DIST_GICD_IPRIORITYR88_FLD_SET(value) (((value) << 0) & 0xffffffff)
12882 #ifndef __ASSEMBLY__
12894 struct ALT_GIC_DIST_GICD_IPRIORITYR88_s
12896 volatile uint32_t fld : 32;
12900 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR88_s ALT_GIC_DIST_GICD_IPRIORITYR88_t;
12904 #define ALT_GIC_DIST_GICD_IPRIORITYR88_RESET 0x00000000
12906 #define ALT_GIC_DIST_GICD_IPRIORITYR88_OFST 0x560
12929 #define ALT_GIC_DIST_GICD_IPRIORITYR89_FLD_LSB 0
12931 #define ALT_GIC_DIST_GICD_IPRIORITYR89_FLD_MSB 31
12933 #define ALT_GIC_DIST_GICD_IPRIORITYR89_FLD_WIDTH 32
12935 #define ALT_GIC_DIST_GICD_IPRIORITYR89_FLD_SET_MSK 0xffffffff
12937 #define ALT_GIC_DIST_GICD_IPRIORITYR89_FLD_CLR_MSK 0x00000000
12939 #define ALT_GIC_DIST_GICD_IPRIORITYR89_FLD_RESET 0x0
12941 #define ALT_GIC_DIST_GICD_IPRIORITYR89_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12943 #define ALT_GIC_DIST_GICD_IPRIORITYR89_FLD_SET(value) (((value) << 0) & 0xffffffff)
12945 #ifndef __ASSEMBLY__
12957 struct ALT_GIC_DIST_GICD_IPRIORITYR89_s
12959 volatile uint32_t fld : 32;
12963 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR89_s ALT_GIC_DIST_GICD_IPRIORITYR89_t;
12967 #define ALT_GIC_DIST_GICD_IPRIORITYR89_RESET 0x00000000
12969 #define ALT_GIC_DIST_GICD_IPRIORITYR89_OFST 0x564
12992 #define ALT_GIC_DIST_GICD_IPRIORITYR90_FLD_LSB 0
12994 #define ALT_GIC_DIST_GICD_IPRIORITYR90_FLD_MSB 31
12996 #define ALT_GIC_DIST_GICD_IPRIORITYR90_FLD_WIDTH 32
12998 #define ALT_GIC_DIST_GICD_IPRIORITYR90_FLD_SET_MSK 0xffffffff
13000 #define ALT_GIC_DIST_GICD_IPRIORITYR90_FLD_CLR_MSK 0x00000000
13002 #define ALT_GIC_DIST_GICD_IPRIORITYR90_FLD_RESET 0x0
13004 #define ALT_GIC_DIST_GICD_IPRIORITYR90_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13006 #define ALT_GIC_DIST_GICD_IPRIORITYR90_FLD_SET(value) (((value) << 0) & 0xffffffff)
13008 #ifndef __ASSEMBLY__
13020 struct ALT_GIC_DIST_GICD_IPRIORITYR90_s
13022 volatile uint32_t fld : 32;
13026 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR90_s ALT_GIC_DIST_GICD_IPRIORITYR90_t;
13030 #define ALT_GIC_DIST_GICD_IPRIORITYR90_RESET 0x00000000
13032 #define ALT_GIC_DIST_GICD_IPRIORITYR90_OFST 0x568
13055 #define ALT_GIC_DIST_GICD_IPRIORITYR91_FLD_LSB 0
13057 #define ALT_GIC_DIST_GICD_IPRIORITYR91_FLD_MSB 31
13059 #define ALT_GIC_DIST_GICD_IPRIORITYR91_FLD_WIDTH 32
13061 #define ALT_GIC_DIST_GICD_IPRIORITYR91_FLD_SET_MSK 0xffffffff
13063 #define ALT_GIC_DIST_GICD_IPRIORITYR91_FLD_CLR_MSK 0x00000000
13065 #define ALT_GIC_DIST_GICD_IPRIORITYR91_FLD_RESET 0x0
13067 #define ALT_GIC_DIST_GICD_IPRIORITYR91_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13069 #define ALT_GIC_DIST_GICD_IPRIORITYR91_FLD_SET(value) (((value) << 0) & 0xffffffff)
13071 #ifndef __ASSEMBLY__
13083 struct ALT_GIC_DIST_GICD_IPRIORITYR91_s
13085 volatile uint32_t fld : 32;
13089 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR91_s ALT_GIC_DIST_GICD_IPRIORITYR91_t;
13093 #define ALT_GIC_DIST_GICD_IPRIORITYR91_RESET 0x00000000
13095 #define ALT_GIC_DIST_GICD_IPRIORITYR91_OFST 0x56c
13118 #define ALT_GIC_DIST_GICD_IPRIORITYR92_FLD_LSB 0
13120 #define ALT_GIC_DIST_GICD_IPRIORITYR92_FLD_MSB 31
13122 #define ALT_GIC_DIST_GICD_IPRIORITYR92_FLD_WIDTH 32
13124 #define ALT_GIC_DIST_GICD_IPRIORITYR92_FLD_SET_MSK 0xffffffff
13126 #define ALT_GIC_DIST_GICD_IPRIORITYR92_FLD_CLR_MSK 0x00000000
13128 #define ALT_GIC_DIST_GICD_IPRIORITYR92_FLD_RESET 0x0
13130 #define ALT_GIC_DIST_GICD_IPRIORITYR92_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13132 #define ALT_GIC_DIST_GICD_IPRIORITYR92_FLD_SET(value) (((value) << 0) & 0xffffffff)
13134 #ifndef __ASSEMBLY__
13146 struct ALT_GIC_DIST_GICD_IPRIORITYR92_s
13148 volatile uint32_t fld : 32;
13152 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR92_s ALT_GIC_DIST_GICD_IPRIORITYR92_t;
13156 #define ALT_GIC_DIST_GICD_IPRIORITYR92_RESET 0x00000000
13158 #define ALT_GIC_DIST_GICD_IPRIORITYR92_OFST 0x570
13181 #define ALT_GIC_DIST_GICD_IPRIORITYR93_FLD_LSB 0
13183 #define ALT_GIC_DIST_GICD_IPRIORITYR93_FLD_MSB 31
13185 #define ALT_GIC_DIST_GICD_IPRIORITYR93_FLD_WIDTH 32
13187 #define ALT_GIC_DIST_GICD_IPRIORITYR93_FLD_SET_MSK 0xffffffff
13189 #define ALT_GIC_DIST_GICD_IPRIORITYR93_FLD_CLR_MSK 0x00000000
13191 #define ALT_GIC_DIST_GICD_IPRIORITYR93_FLD_RESET 0x0
13193 #define ALT_GIC_DIST_GICD_IPRIORITYR93_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13195 #define ALT_GIC_DIST_GICD_IPRIORITYR93_FLD_SET(value) (((value) << 0) & 0xffffffff)
13197 #ifndef __ASSEMBLY__
13209 struct ALT_GIC_DIST_GICD_IPRIORITYR93_s
13211 volatile uint32_t fld : 32;
13215 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR93_s ALT_GIC_DIST_GICD_IPRIORITYR93_t;
13219 #define ALT_GIC_DIST_GICD_IPRIORITYR93_RESET 0x00000000
13221 #define ALT_GIC_DIST_GICD_IPRIORITYR93_OFST 0x574
13244 #define ALT_GIC_DIST_GICD_IPRIORITYR94_FLD_LSB 0
13246 #define ALT_GIC_DIST_GICD_IPRIORITYR94_FLD_MSB 31
13248 #define ALT_GIC_DIST_GICD_IPRIORITYR94_FLD_WIDTH 32
13250 #define ALT_GIC_DIST_GICD_IPRIORITYR94_FLD_SET_MSK 0xffffffff
13252 #define ALT_GIC_DIST_GICD_IPRIORITYR94_FLD_CLR_MSK 0x00000000
13254 #define ALT_GIC_DIST_GICD_IPRIORITYR94_FLD_RESET 0x0
13256 #define ALT_GIC_DIST_GICD_IPRIORITYR94_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13258 #define ALT_GIC_DIST_GICD_IPRIORITYR94_FLD_SET(value) (((value) << 0) & 0xffffffff)
13260 #ifndef __ASSEMBLY__
13272 struct ALT_GIC_DIST_GICD_IPRIORITYR94_s
13274 volatile uint32_t fld : 32;
13278 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR94_s ALT_GIC_DIST_GICD_IPRIORITYR94_t;
13282 #define ALT_GIC_DIST_GICD_IPRIORITYR94_RESET 0x00000000
13284 #define ALT_GIC_DIST_GICD_IPRIORITYR94_OFST 0x578
13307 #define ALT_GIC_DIST_GICD_IPRIORITYR95_FLD_LSB 0
13309 #define ALT_GIC_DIST_GICD_IPRIORITYR95_FLD_MSB 31
13311 #define ALT_GIC_DIST_GICD_IPRIORITYR95_FLD_WIDTH 32
13313 #define ALT_GIC_DIST_GICD_IPRIORITYR95_FLD_SET_MSK 0xffffffff
13315 #define ALT_GIC_DIST_GICD_IPRIORITYR95_FLD_CLR_MSK 0x00000000
13317 #define ALT_GIC_DIST_GICD_IPRIORITYR95_FLD_RESET 0x0
13319 #define ALT_GIC_DIST_GICD_IPRIORITYR95_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13321 #define ALT_GIC_DIST_GICD_IPRIORITYR95_FLD_SET(value) (((value) << 0) & 0xffffffff)
13323 #ifndef __ASSEMBLY__
13335 struct ALT_GIC_DIST_GICD_IPRIORITYR95_s
13337 volatile uint32_t fld : 32;
13341 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR95_s ALT_GIC_DIST_GICD_IPRIORITYR95_t;
13345 #define ALT_GIC_DIST_GICD_IPRIORITYR95_RESET 0x00000000
13347 #define ALT_GIC_DIST_GICD_IPRIORITYR95_OFST 0x57c
13370 #define ALT_GIC_DIST_GICD_IPRIORITYR96_FLD_LSB 0
13372 #define ALT_GIC_DIST_GICD_IPRIORITYR96_FLD_MSB 31
13374 #define ALT_GIC_DIST_GICD_IPRIORITYR96_FLD_WIDTH 32
13376 #define ALT_GIC_DIST_GICD_IPRIORITYR96_FLD_SET_MSK 0xffffffff
13378 #define ALT_GIC_DIST_GICD_IPRIORITYR96_FLD_CLR_MSK 0x00000000
13380 #define ALT_GIC_DIST_GICD_IPRIORITYR96_FLD_RESET 0x0
13382 #define ALT_GIC_DIST_GICD_IPRIORITYR96_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13384 #define ALT_GIC_DIST_GICD_IPRIORITYR96_FLD_SET(value) (((value) << 0) & 0xffffffff)
13386 #ifndef __ASSEMBLY__
13398 struct ALT_GIC_DIST_GICD_IPRIORITYR96_s
13400 volatile uint32_t fld : 32;
13404 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR96_s ALT_GIC_DIST_GICD_IPRIORITYR96_t;
13408 #define ALT_GIC_DIST_GICD_IPRIORITYR96_RESET 0x00000000
13410 #define ALT_GIC_DIST_GICD_IPRIORITYR96_OFST 0x580
13433 #define ALT_GIC_DIST_GICD_IPRIORITYR97_FLD_LSB 0
13435 #define ALT_GIC_DIST_GICD_IPRIORITYR97_FLD_MSB 31
13437 #define ALT_GIC_DIST_GICD_IPRIORITYR97_FLD_WIDTH 32
13439 #define ALT_GIC_DIST_GICD_IPRIORITYR97_FLD_SET_MSK 0xffffffff
13441 #define ALT_GIC_DIST_GICD_IPRIORITYR97_FLD_CLR_MSK 0x00000000
13443 #define ALT_GIC_DIST_GICD_IPRIORITYR97_FLD_RESET 0x0
13445 #define ALT_GIC_DIST_GICD_IPRIORITYR97_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13447 #define ALT_GIC_DIST_GICD_IPRIORITYR97_FLD_SET(value) (((value) << 0) & 0xffffffff)
13449 #ifndef __ASSEMBLY__
13461 struct ALT_GIC_DIST_GICD_IPRIORITYR97_s
13463 volatile uint32_t fld : 32;
13467 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR97_s ALT_GIC_DIST_GICD_IPRIORITYR97_t;
13471 #define ALT_GIC_DIST_GICD_IPRIORITYR97_RESET 0x00000000
13473 #define ALT_GIC_DIST_GICD_IPRIORITYR97_OFST 0x584
13496 #define ALT_GIC_DIST_GICD_IPRIORITYR98_FLD_LSB 0
13498 #define ALT_GIC_DIST_GICD_IPRIORITYR98_FLD_MSB 31
13500 #define ALT_GIC_DIST_GICD_IPRIORITYR98_FLD_WIDTH 32
13502 #define ALT_GIC_DIST_GICD_IPRIORITYR98_FLD_SET_MSK 0xffffffff
13504 #define ALT_GIC_DIST_GICD_IPRIORITYR98_FLD_CLR_MSK 0x00000000
13506 #define ALT_GIC_DIST_GICD_IPRIORITYR98_FLD_RESET 0x0
13508 #define ALT_GIC_DIST_GICD_IPRIORITYR98_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13510 #define ALT_GIC_DIST_GICD_IPRIORITYR98_FLD_SET(value) (((value) << 0) & 0xffffffff)
13512 #ifndef __ASSEMBLY__
13524 struct ALT_GIC_DIST_GICD_IPRIORITYR98_s
13526 volatile uint32_t fld : 32;
13530 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR98_s ALT_GIC_DIST_GICD_IPRIORITYR98_t;
13534 #define ALT_GIC_DIST_GICD_IPRIORITYR98_RESET 0x00000000
13536 #define ALT_GIC_DIST_GICD_IPRIORITYR98_OFST 0x588
13559 #define ALT_GIC_DIST_GICD_IPRIORITYR99_FLD_LSB 0
13561 #define ALT_GIC_DIST_GICD_IPRIORITYR99_FLD_MSB 31
13563 #define ALT_GIC_DIST_GICD_IPRIORITYR99_FLD_WIDTH 32
13565 #define ALT_GIC_DIST_GICD_IPRIORITYR99_FLD_SET_MSK 0xffffffff
13567 #define ALT_GIC_DIST_GICD_IPRIORITYR99_FLD_CLR_MSK 0x00000000
13569 #define ALT_GIC_DIST_GICD_IPRIORITYR99_FLD_RESET 0x0
13571 #define ALT_GIC_DIST_GICD_IPRIORITYR99_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13573 #define ALT_GIC_DIST_GICD_IPRIORITYR99_FLD_SET(value) (((value) << 0) & 0xffffffff)
13575 #ifndef __ASSEMBLY__
13587 struct ALT_GIC_DIST_GICD_IPRIORITYR99_s
13589 volatile uint32_t fld : 32;
13593 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR99_s ALT_GIC_DIST_GICD_IPRIORITYR99_t;
13597 #define ALT_GIC_DIST_GICD_IPRIORITYR99_RESET 0x00000000
13599 #define ALT_GIC_DIST_GICD_IPRIORITYR99_OFST 0x58c
13622 #define ALT_GIC_DIST_GICD_IPRIORITYR100_FLD_LSB 0
13624 #define ALT_GIC_DIST_GICD_IPRIORITYR100_FLD_MSB 31
13626 #define ALT_GIC_DIST_GICD_IPRIORITYR100_FLD_WIDTH 32
13628 #define ALT_GIC_DIST_GICD_IPRIORITYR100_FLD_SET_MSK 0xffffffff
13630 #define ALT_GIC_DIST_GICD_IPRIORITYR100_FLD_CLR_MSK 0x00000000
13632 #define ALT_GIC_DIST_GICD_IPRIORITYR100_FLD_RESET 0x0
13634 #define ALT_GIC_DIST_GICD_IPRIORITYR100_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13636 #define ALT_GIC_DIST_GICD_IPRIORITYR100_FLD_SET(value) (((value) << 0) & 0xffffffff)
13638 #ifndef __ASSEMBLY__
13650 struct ALT_GIC_DIST_GICD_IPRIORITYR100_s
13652 volatile uint32_t fld : 32;
13656 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR100_s ALT_GIC_DIST_GICD_IPRIORITYR100_t;
13660 #define ALT_GIC_DIST_GICD_IPRIORITYR100_RESET 0x00000000
13662 #define ALT_GIC_DIST_GICD_IPRIORITYR100_OFST 0x590
13685 #define ALT_GIC_DIST_GICD_IPRIORITYR101_FLD_LSB 0
13687 #define ALT_GIC_DIST_GICD_IPRIORITYR101_FLD_MSB 31
13689 #define ALT_GIC_DIST_GICD_IPRIORITYR101_FLD_WIDTH 32
13691 #define ALT_GIC_DIST_GICD_IPRIORITYR101_FLD_SET_MSK 0xffffffff
13693 #define ALT_GIC_DIST_GICD_IPRIORITYR101_FLD_CLR_MSK 0x00000000
13695 #define ALT_GIC_DIST_GICD_IPRIORITYR101_FLD_RESET 0x0
13697 #define ALT_GIC_DIST_GICD_IPRIORITYR101_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13699 #define ALT_GIC_DIST_GICD_IPRIORITYR101_FLD_SET(value) (((value) << 0) & 0xffffffff)
13701 #ifndef __ASSEMBLY__
13713 struct ALT_GIC_DIST_GICD_IPRIORITYR101_s
13715 volatile uint32_t fld : 32;
13719 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR101_s ALT_GIC_DIST_GICD_IPRIORITYR101_t;
13723 #define ALT_GIC_DIST_GICD_IPRIORITYR101_RESET 0x00000000
13725 #define ALT_GIC_DIST_GICD_IPRIORITYR101_OFST 0x594
13748 #define ALT_GIC_DIST_GICD_IPRIORITYR102_FLD_LSB 0
13750 #define ALT_GIC_DIST_GICD_IPRIORITYR102_FLD_MSB 31
13752 #define ALT_GIC_DIST_GICD_IPRIORITYR102_FLD_WIDTH 32
13754 #define ALT_GIC_DIST_GICD_IPRIORITYR102_FLD_SET_MSK 0xffffffff
13756 #define ALT_GIC_DIST_GICD_IPRIORITYR102_FLD_CLR_MSK 0x00000000
13758 #define ALT_GIC_DIST_GICD_IPRIORITYR102_FLD_RESET 0x0
13760 #define ALT_GIC_DIST_GICD_IPRIORITYR102_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13762 #define ALT_GIC_DIST_GICD_IPRIORITYR102_FLD_SET(value) (((value) << 0) & 0xffffffff)
13764 #ifndef __ASSEMBLY__
13776 struct ALT_GIC_DIST_GICD_IPRIORITYR102_s
13778 volatile uint32_t fld : 32;
13782 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR102_s ALT_GIC_DIST_GICD_IPRIORITYR102_t;
13786 #define ALT_GIC_DIST_GICD_IPRIORITYR102_RESET 0x00000000
13788 #define ALT_GIC_DIST_GICD_IPRIORITYR102_OFST 0x598
13811 #define ALT_GIC_DIST_GICD_IPRIORITYR103_FLD_LSB 0
13813 #define ALT_GIC_DIST_GICD_IPRIORITYR103_FLD_MSB 31
13815 #define ALT_GIC_DIST_GICD_IPRIORITYR103_FLD_WIDTH 32
13817 #define ALT_GIC_DIST_GICD_IPRIORITYR103_FLD_SET_MSK 0xffffffff
13819 #define ALT_GIC_DIST_GICD_IPRIORITYR103_FLD_CLR_MSK 0x00000000
13821 #define ALT_GIC_DIST_GICD_IPRIORITYR103_FLD_RESET 0x0
13823 #define ALT_GIC_DIST_GICD_IPRIORITYR103_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13825 #define ALT_GIC_DIST_GICD_IPRIORITYR103_FLD_SET(value) (((value) << 0) & 0xffffffff)
13827 #ifndef __ASSEMBLY__
13839 struct ALT_GIC_DIST_GICD_IPRIORITYR103_s
13841 volatile uint32_t fld : 32;
13845 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR103_s ALT_GIC_DIST_GICD_IPRIORITYR103_t;
13849 #define ALT_GIC_DIST_GICD_IPRIORITYR103_RESET 0x00000000
13851 #define ALT_GIC_DIST_GICD_IPRIORITYR103_OFST 0x59c
13874 #define ALT_GIC_DIST_GICD_IPRIORITYR104_FLD_LSB 0
13876 #define ALT_GIC_DIST_GICD_IPRIORITYR104_FLD_MSB 31
13878 #define ALT_GIC_DIST_GICD_IPRIORITYR104_FLD_WIDTH 32
13880 #define ALT_GIC_DIST_GICD_IPRIORITYR104_FLD_SET_MSK 0xffffffff
13882 #define ALT_GIC_DIST_GICD_IPRIORITYR104_FLD_CLR_MSK 0x00000000
13884 #define ALT_GIC_DIST_GICD_IPRIORITYR104_FLD_RESET 0x0
13886 #define ALT_GIC_DIST_GICD_IPRIORITYR104_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13888 #define ALT_GIC_DIST_GICD_IPRIORITYR104_FLD_SET(value) (((value) << 0) & 0xffffffff)
13890 #ifndef __ASSEMBLY__
13902 struct ALT_GIC_DIST_GICD_IPRIORITYR104_s
13904 volatile uint32_t fld : 32;
13908 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR104_s ALT_GIC_DIST_GICD_IPRIORITYR104_t;
13912 #define ALT_GIC_DIST_GICD_IPRIORITYR104_RESET 0x00000000
13914 #define ALT_GIC_DIST_GICD_IPRIORITYR104_OFST 0x5a0
13937 #define ALT_GIC_DIST_GICD_IPRIORITYR105_FLD_LSB 0
13939 #define ALT_GIC_DIST_GICD_IPRIORITYR105_FLD_MSB 31
13941 #define ALT_GIC_DIST_GICD_IPRIORITYR105_FLD_WIDTH 32
13943 #define ALT_GIC_DIST_GICD_IPRIORITYR105_FLD_SET_MSK 0xffffffff
13945 #define ALT_GIC_DIST_GICD_IPRIORITYR105_FLD_CLR_MSK 0x00000000
13947 #define ALT_GIC_DIST_GICD_IPRIORITYR105_FLD_RESET 0x0
13949 #define ALT_GIC_DIST_GICD_IPRIORITYR105_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13951 #define ALT_GIC_DIST_GICD_IPRIORITYR105_FLD_SET(value) (((value) << 0) & 0xffffffff)
13953 #ifndef __ASSEMBLY__
13965 struct ALT_GIC_DIST_GICD_IPRIORITYR105_s
13967 volatile uint32_t fld : 32;
13971 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR105_s ALT_GIC_DIST_GICD_IPRIORITYR105_t;
13975 #define ALT_GIC_DIST_GICD_IPRIORITYR105_RESET 0x00000000
13977 #define ALT_GIC_DIST_GICD_IPRIORITYR105_OFST 0x5a4
14000 #define ALT_GIC_DIST_GICD_IPRIORITYR106_FLD_LSB 0
14002 #define ALT_GIC_DIST_GICD_IPRIORITYR106_FLD_MSB 31
14004 #define ALT_GIC_DIST_GICD_IPRIORITYR106_FLD_WIDTH 32
14006 #define ALT_GIC_DIST_GICD_IPRIORITYR106_FLD_SET_MSK 0xffffffff
14008 #define ALT_GIC_DIST_GICD_IPRIORITYR106_FLD_CLR_MSK 0x00000000
14010 #define ALT_GIC_DIST_GICD_IPRIORITYR106_FLD_RESET 0x0
14012 #define ALT_GIC_DIST_GICD_IPRIORITYR106_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14014 #define ALT_GIC_DIST_GICD_IPRIORITYR106_FLD_SET(value) (((value) << 0) & 0xffffffff)
14016 #ifndef __ASSEMBLY__
14028 struct ALT_GIC_DIST_GICD_IPRIORITYR106_s
14030 volatile uint32_t fld : 32;
14034 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR106_s ALT_GIC_DIST_GICD_IPRIORITYR106_t;
14038 #define ALT_GIC_DIST_GICD_IPRIORITYR106_RESET 0x00000000
14040 #define ALT_GIC_DIST_GICD_IPRIORITYR106_OFST 0x5a8
14063 #define ALT_GIC_DIST_GICD_IPRIORITYR107_FLD_LSB 0
14065 #define ALT_GIC_DIST_GICD_IPRIORITYR107_FLD_MSB 31
14067 #define ALT_GIC_DIST_GICD_IPRIORITYR107_FLD_WIDTH 32
14069 #define ALT_GIC_DIST_GICD_IPRIORITYR107_FLD_SET_MSK 0xffffffff
14071 #define ALT_GIC_DIST_GICD_IPRIORITYR107_FLD_CLR_MSK 0x00000000
14073 #define ALT_GIC_DIST_GICD_IPRIORITYR107_FLD_RESET 0x0
14075 #define ALT_GIC_DIST_GICD_IPRIORITYR107_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14077 #define ALT_GIC_DIST_GICD_IPRIORITYR107_FLD_SET(value) (((value) << 0) & 0xffffffff)
14079 #ifndef __ASSEMBLY__
14091 struct ALT_GIC_DIST_GICD_IPRIORITYR107_s
14093 volatile uint32_t fld : 32;
14097 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR107_s ALT_GIC_DIST_GICD_IPRIORITYR107_t;
14101 #define ALT_GIC_DIST_GICD_IPRIORITYR107_RESET 0x00000000
14103 #define ALT_GIC_DIST_GICD_IPRIORITYR107_OFST 0x5ac
14126 #define ALT_GIC_DIST_GICD_IPRIORITYR108_FLD_LSB 0
14128 #define ALT_GIC_DIST_GICD_IPRIORITYR108_FLD_MSB 31
14130 #define ALT_GIC_DIST_GICD_IPRIORITYR108_FLD_WIDTH 32
14132 #define ALT_GIC_DIST_GICD_IPRIORITYR108_FLD_SET_MSK 0xffffffff
14134 #define ALT_GIC_DIST_GICD_IPRIORITYR108_FLD_CLR_MSK 0x00000000
14136 #define ALT_GIC_DIST_GICD_IPRIORITYR108_FLD_RESET 0x0
14138 #define ALT_GIC_DIST_GICD_IPRIORITYR108_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14140 #define ALT_GIC_DIST_GICD_IPRIORITYR108_FLD_SET(value) (((value) << 0) & 0xffffffff)
14142 #ifndef __ASSEMBLY__
14154 struct ALT_GIC_DIST_GICD_IPRIORITYR108_s
14156 volatile uint32_t fld : 32;
14160 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR108_s ALT_GIC_DIST_GICD_IPRIORITYR108_t;
14164 #define ALT_GIC_DIST_GICD_IPRIORITYR108_RESET 0x00000000
14166 #define ALT_GIC_DIST_GICD_IPRIORITYR108_OFST 0x5b0
14189 #define ALT_GIC_DIST_GICD_IPRIORITYR109_FLD_LSB 0
14191 #define ALT_GIC_DIST_GICD_IPRIORITYR109_FLD_MSB 31
14193 #define ALT_GIC_DIST_GICD_IPRIORITYR109_FLD_WIDTH 32
14195 #define ALT_GIC_DIST_GICD_IPRIORITYR109_FLD_SET_MSK 0xffffffff
14197 #define ALT_GIC_DIST_GICD_IPRIORITYR109_FLD_CLR_MSK 0x00000000
14199 #define ALT_GIC_DIST_GICD_IPRIORITYR109_FLD_RESET 0x0
14201 #define ALT_GIC_DIST_GICD_IPRIORITYR109_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14203 #define ALT_GIC_DIST_GICD_IPRIORITYR109_FLD_SET(value) (((value) << 0) & 0xffffffff)
14205 #ifndef __ASSEMBLY__
14217 struct ALT_GIC_DIST_GICD_IPRIORITYR109_s
14219 volatile uint32_t fld : 32;
14223 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR109_s ALT_GIC_DIST_GICD_IPRIORITYR109_t;
14227 #define ALT_GIC_DIST_GICD_IPRIORITYR109_RESET 0x00000000
14229 #define ALT_GIC_DIST_GICD_IPRIORITYR109_OFST 0x5b4
14252 #define ALT_GIC_DIST_GICD_IPRIORITYR110_FLD_LSB 0
14254 #define ALT_GIC_DIST_GICD_IPRIORITYR110_FLD_MSB 31
14256 #define ALT_GIC_DIST_GICD_IPRIORITYR110_FLD_WIDTH 32
14258 #define ALT_GIC_DIST_GICD_IPRIORITYR110_FLD_SET_MSK 0xffffffff
14260 #define ALT_GIC_DIST_GICD_IPRIORITYR110_FLD_CLR_MSK 0x00000000
14262 #define ALT_GIC_DIST_GICD_IPRIORITYR110_FLD_RESET 0x0
14264 #define ALT_GIC_DIST_GICD_IPRIORITYR110_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14266 #define ALT_GIC_DIST_GICD_IPRIORITYR110_FLD_SET(value) (((value) << 0) & 0xffffffff)
14268 #ifndef __ASSEMBLY__
14280 struct ALT_GIC_DIST_GICD_IPRIORITYR110_s
14282 volatile uint32_t fld : 32;
14286 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR110_s ALT_GIC_DIST_GICD_IPRIORITYR110_t;
14290 #define ALT_GIC_DIST_GICD_IPRIORITYR110_RESET 0x00000000
14292 #define ALT_GIC_DIST_GICD_IPRIORITYR110_OFST 0x5b8
14315 #define ALT_GIC_DIST_GICD_IPRIORITYR111_FLD_LSB 0
14317 #define ALT_GIC_DIST_GICD_IPRIORITYR111_FLD_MSB 31
14319 #define ALT_GIC_DIST_GICD_IPRIORITYR111_FLD_WIDTH 32
14321 #define ALT_GIC_DIST_GICD_IPRIORITYR111_FLD_SET_MSK 0xffffffff
14323 #define ALT_GIC_DIST_GICD_IPRIORITYR111_FLD_CLR_MSK 0x00000000
14325 #define ALT_GIC_DIST_GICD_IPRIORITYR111_FLD_RESET 0x0
14327 #define ALT_GIC_DIST_GICD_IPRIORITYR111_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14329 #define ALT_GIC_DIST_GICD_IPRIORITYR111_FLD_SET(value) (((value) << 0) & 0xffffffff)
14331 #ifndef __ASSEMBLY__
14343 struct ALT_GIC_DIST_GICD_IPRIORITYR111_s
14345 volatile uint32_t fld : 32;
14349 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR111_s ALT_GIC_DIST_GICD_IPRIORITYR111_t;
14353 #define ALT_GIC_DIST_GICD_IPRIORITYR111_RESET 0x00000000
14355 #define ALT_GIC_DIST_GICD_IPRIORITYR111_OFST 0x5bc
14378 #define ALT_GIC_DIST_GICD_IPRIORITYR112_FLD_LSB 0
14380 #define ALT_GIC_DIST_GICD_IPRIORITYR112_FLD_MSB 31
14382 #define ALT_GIC_DIST_GICD_IPRIORITYR112_FLD_WIDTH 32
14384 #define ALT_GIC_DIST_GICD_IPRIORITYR112_FLD_SET_MSK 0xffffffff
14386 #define ALT_GIC_DIST_GICD_IPRIORITYR112_FLD_CLR_MSK 0x00000000
14388 #define ALT_GIC_DIST_GICD_IPRIORITYR112_FLD_RESET 0x0
14390 #define ALT_GIC_DIST_GICD_IPRIORITYR112_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14392 #define ALT_GIC_DIST_GICD_IPRIORITYR112_FLD_SET(value) (((value) << 0) & 0xffffffff)
14394 #ifndef __ASSEMBLY__
14406 struct ALT_GIC_DIST_GICD_IPRIORITYR112_s
14408 volatile uint32_t fld : 32;
14412 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR112_s ALT_GIC_DIST_GICD_IPRIORITYR112_t;
14416 #define ALT_GIC_DIST_GICD_IPRIORITYR112_RESET 0x00000000
14418 #define ALT_GIC_DIST_GICD_IPRIORITYR112_OFST 0x5c0
14441 #define ALT_GIC_DIST_GICD_IPRIORITYR113_FLD_LSB 0
14443 #define ALT_GIC_DIST_GICD_IPRIORITYR113_FLD_MSB 31
14445 #define ALT_GIC_DIST_GICD_IPRIORITYR113_FLD_WIDTH 32
14447 #define ALT_GIC_DIST_GICD_IPRIORITYR113_FLD_SET_MSK 0xffffffff
14449 #define ALT_GIC_DIST_GICD_IPRIORITYR113_FLD_CLR_MSK 0x00000000
14451 #define ALT_GIC_DIST_GICD_IPRIORITYR113_FLD_RESET 0x0
14453 #define ALT_GIC_DIST_GICD_IPRIORITYR113_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14455 #define ALT_GIC_DIST_GICD_IPRIORITYR113_FLD_SET(value) (((value) << 0) & 0xffffffff)
14457 #ifndef __ASSEMBLY__
14469 struct ALT_GIC_DIST_GICD_IPRIORITYR113_s
14471 volatile uint32_t fld : 32;
14475 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR113_s ALT_GIC_DIST_GICD_IPRIORITYR113_t;
14479 #define ALT_GIC_DIST_GICD_IPRIORITYR113_RESET 0x00000000
14481 #define ALT_GIC_DIST_GICD_IPRIORITYR113_OFST 0x5c4
14504 #define ALT_GIC_DIST_GICD_IPRIORITYR114_FLD_LSB 0
14506 #define ALT_GIC_DIST_GICD_IPRIORITYR114_FLD_MSB 31
14508 #define ALT_GIC_DIST_GICD_IPRIORITYR114_FLD_WIDTH 32
14510 #define ALT_GIC_DIST_GICD_IPRIORITYR114_FLD_SET_MSK 0xffffffff
14512 #define ALT_GIC_DIST_GICD_IPRIORITYR114_FLD_CLR_MSK 0x00000000
14514 #define ALT_GIC_DIST_GICD_IPRIORITYR114_FLD_RESET 0x0
14516 #define ALT_GIC_DIST_GICD_IPRIORITYR114_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14518 #define ALT_GIC_DIST_GICD_IPRIORITYR114_FLD_SET(value) (((value) << 0) & 0xffffffff)
14520 #ifndef __ASSEMBLY__
14532 struct ALT_GIC_DIST_GICD_IPRIORITYR114_s
14534 volatile uint32_t fld : 32;
14538 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR114_s ALT_GIC_DIST_GICD_IPRIORITYR114_t;
14542 #define ALT_GIC_DIST_GICD_IPRIORITYR114_RESET 0x00000000
14544 #define ALT_GIC_DIST_GICD_IPRIORITYR114_OFST 0x5c8
14567 #define ALT_GIC_DIST_GICD_IPRIORITYR115_FLD_LSB 0
14569 #define ALT_GIC_DIST_GICD_IPRIORITYR115_FLD_MSB 31
14571 #define ALT_GIC_DIST_GICD_IPRIORITYR115_FLD_WIDTH 32
14573 #define ALT_GIC_DIST_GICD_IPRIORITYR115_FLD_SET_MSK 0xffffffff
14575 #define ALT_GIC_DIST_GICD_IPRIORITYR115_FLD_CLR_MSK 0x00000000
14577 #define ALT_GIC_DIST_GICD_IPRIORITYR115_FLD_RESET 0x0
14579 #define ALT_GIC_DIST_GICD_IPRIORITYR115_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14581 #define ALT_GIC_DIST_GICD_IPRIORITYR115_FLD_SET(value) (((value) << 0) & 0xffffffff)
14583 #ifndef __ASSEMBLY__
14595 struct ALT_GIC_DIST_GICD_IPRIORITYR115_s
14597 volatile uint32_t fld : 32;
14601 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR115_s ALT_GIC_DIST_GICD_IPRIORITYR115_t;
14605 #define ALT_GIC_DIST_GICD_IPRIORITYR115_RESET 0x00000000
14607 #define ALT_GIC_DIST_GICD_IPRIORITYR115_OFST 0x5cc
14630 #define ALT_GIC_DIST_GICD_IPRIORITYR116_FLD_LSB 0
14632 #define ALT_GIC_DIST_GICD_IPRIORITYR116_FLD_MSB 31
14634 #define ALT_GIC_DIST_GICD_IPRIORITYR116_FLD_WIDTH 32
14636 #define ALT_GIC_DIST_GICD_IPRIORITYR116_FLD_SET_MSK 0xffffffff
14638 #define ALT_GIC_DIST_GICD_IPRIORITYR116_FLD_CLR_MSK 0x00000000
14640 #define ALT_GIC_DIST_GICD_IPRIORITYR116_FLD_RESET 0x0
14642 #define ALT_GIC_DIST_GICD_IPRIORITYR116_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14644 #define ALT_GIC_DIST_GICD_IPRIORITYR116_FLD_SET(value) (((value) << 0) & 0xffffffff)
14646 #ifndef __ASSEMBLY__
14658 struct ALT_GIC_DIST_GICD_IPRIORITYR116_s
14660 volatile uint32_t fld : 32;
14664 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR116_s ALT_GIC_DIST_GICD_IPRIORITYR116_t;
14668 #define ALT_GIC_DIST_GICD_IPRIORITYR116_RESET 0x00000000
14670 #define ALT_GIC_DIST_GICD_IPRIORITYR116_OFST 0x5d0
14693 #define ALT_GIC_DIST_GICD_IPRIORITYR117_FLD_LSB 0
14695 #define ALT_GIC_DIST_GICD_IPRIORITYR117_FLD_MSB 31
14697 #define ALT_GIC_DIST_GICD_IPRIORITYR117_FLD_WIDTH 32
14699 #define ALT_GIC_DIST_GICD_IPRIORITYR117_FLD_SET_MSK 0xffffffff
14701 #define ALT_GIC_DIST_GICD_IPRIORITYR117_FLD_CLR_MSK 0x00000000
14703 #define ALT_GIC_DIST_GICD_IPRIORITYR117_FLD_RESET 0x0
14705 #define ALT_GIC_DIST_GICD_IPRIORITYR117_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14707 #define ALT_GIC_DIST_GICD_IPRIORITYR117_FLD_SET(value) (((value) << 0) & 0xffffffff)
14709 #ifndef __ASSEMBLY__
14721 struct ALT_GIC_DIST_GICD_IPRIORITYR117_s
14723 volatile uint32_t fld : 32;
14727 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR117_s ALT_GIC_DIST_GICD_IPRIORITYR117_t;
14731 #define ALT_GIC_DIST_GICD_IPRIORITYR117_RESET 0x00000000
14733 #define ALT_GIC_DIST_GICD_IPRIORITYR117_OFST 0x5d4
14756 #define ALT_GIC_DIST_GICD_IPRIORITYR118_FLD_LSB 0
14758 #define ALT_GIC_DIST_GICD_IPRIORITYR118_FLD_MSB 31
14760 #define ALT_GIC_DIST_GICD_IPRIORITYR118_FLD_WIDTH 32
14762 #define ALT_GIC_DIST_GICD_IPRIORITYR118_FLD_SET_MSK 0xffffffff
14764 #define ALT_GIC_DIST_GICD_IPRIORITYR118_FLD_CLR_MSK 0x00000000
14766 #define ALT_GIC_DIST_GICD_IPRIORITYR118_FLD_RESET 0x0
14768 #define ALT_GIC_DIST_GICD_IPRIORITYR118_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14770 #define ALT_GIC_DIST_GICD_IPRIORITYR118_FLD_SET(value) (((value) << 0) & 0xffffffff)
14772 #ifndef __ASSEMBLY__
14784 struct ALT_GIC_DIST_GICD_IPRIORITYR118_s
14786 volatile uint32_t fld : 32;
14790 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR118_s ALT_GIC_DIST_GICD_IPRIORITYR118_t;
14794 #define ALT_GIC_DIST_GICD_IPRIORITYR118_RESET 0x00000000
14796 #define ALT_GIC_DIST_GICD_IPRIORITYR118_OFST 0x5d8
14819 #define ALT_GIC_DIST_GICD_IPRIORITYR119_FLD_LSB 0
14821 #define ALT_GIC_DIST_GICD_IPRIORITYR119_FLD_MSB 31
14823 #define ALT_GIC_DIST_GICD_IPRIORITYR119_FLD_WIDTH 32
14825 #define ALT_GIC_DIST_GICD_IPRIORITYR119_FLD_SET_MSK 0xffffffff
14827 #define ALT_GIC_DIST_GICD_IPRIORITYR119_FLD_CLR_MSK 0x00000000
14829 #define ALT_GIC_DIST_GICD_IPRIORITYR119_FLD_RESET 0x0
14831 #define ALT_GIC_DIST_GICD_IPRIORITYR119_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14833 #define ALT_GIC_DIST_GICD_IPRIORITYR119_FLD_SET(value) (((value) << 0) & 0xffffffff)
14835 #ifndef __ASSEMBLY__
14847 struct ALT_GIC_DIST_GICD_IPRIORITYR119_s
14849 volatile uint32_t fld : 32;
14853 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR119_s ALT_GIC_DIST_GICD_IPRIORITYR119_t;
14857 #define ALT_GIC_DIST_GICD_IPRIORITYR119_RESET 0x00000000
14859 #define ALT_GIC_DIST_GICD_IPRIORITYR119_OFST 0x5dc
14882 #define ALT_GIC_DIST_GICD_IPRIORITYR120_FLD_LSB 0
14884 #define ALT_GIC_DIST_GICD_IPRIORITYR120_FLD_MSB 31
14886 #define ALT_GIC_DIST_GICD_IPRIORITYR120_FLD_WIDTH 32
14888 #define ALT_GIC_DIST_GICD_IPRIORITYR120_FLD_SET_MSK 0xffffffff
14890 #define ALT_GIC_DIST_GICD_IPRIORITYR120_FLD_CLR_MSK 0x00000000
14892 #define ALT_GIC_DIST_GICD_IPRIORITYR120_FLD_RESET 0x0
14894 #define ALT_GIC_DIST_GICD_IPRIORITYR120_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14896 #define ALT_GIC_DIST_GICD_IPRIORITYR120_FLD_SET(value) (((value) << 0) & 0xffffffff)
14898 #ifndef __ASSEMBLY__
14910 struct ALT_GIC_DIST_GICD_IPRIORITYR120_s
14912 volatile uint32_t fld : 32;
14916 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR120_s ALT_GIC_DIST_GICD_IPRIORITYR120_t;
14920 #define ALT_GIC_DIST_GICD_IPRIORITYR120_RESET 0x00000000
14922 #define ALT_GIC_DIST_GICD_IPRIORITYR120_OFST 0x5e0
14945 #define ALT_GIC_DIST_GICD_IPRIORITYR121_FLD_LSB 0
14947 #define ALT_GIC_DIST_GICD_IPRIORITYR121_FLD_MSB 31
14949 #define ALT_GIC_DIST_GICD_IPRIORITYR121_FLD_WIDTH 32
14951 #define ALT_GIC_DIST_GICD_IPRIORITYR121_FLD_SET_MSK 0xffffffff
14953 #define ALT_GIC_DIST_GICD_IPRIORITYR121_FLD_CLR_MSK 0x00000000
14955 #define ALT_GIC_DIST_GICD_IPRIORITYR121_FLD_RESET 0x0
14957 #define ALT_GIC_DIST_GICD_IPRIORITYR121_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14959 #define ALT_GIC_DIST_GICD_IPRIORITYR121_FLD_SET(value) (((value) << 0) & 0xffffffff)
14961 #ifndef __ASSEMBLY__
14973 struct ALT_GIC_DIST_GICD_IPRIORITYR121_s
14975 volatile uint32_t fld : 32;
14979 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR121_s ALT_GIC_DIST_GICD_IPRIORITYR121_t;
14983 #define ALT_GIC_DIST_GICD_IPRIORITYR121_RESET 0x00000000
14985 #define ALT_GIC_DIST_GICD_IPRIORITYR121_OFST 0x5e4
15008 #define ALT_GIC_DIST_GICD_IPRIORITYR122_FLD_LSB 0
15010 #define ALT_GIC_DIST_GICD_IPRIORITYR122_FLD_MSB 31
15012 #define ALT_GIC_DIST_GICD_IPRIORITYR122_FLD_WIDTH 32
15014 #define ALT_GIC_DIST_GICD_IPRIORITYR122_FLD_SET_MSK 0xffffffff
15016 #define ALT_GIC_DIST_GICD_IPRIORITYR122_FLD_CLR_MSK 0x00000000
15018 #define ALT_GIC_DIST_GICD_IPRIORITYR122_FLD_RESET 0x0
15020 #define ALT_GIC_DIST_GICD_IPRIORITYR122_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15022 #define ALT_GIC_DIST_GICD_IPRIORITYR122_FLD_SET(value) (((value) << 0) & 0xffffffff)
15024 #ifndef __ASSEMBLY__
15036 struct ALT_GIC_DIST_GICD_IPRIORITYR122_s
15038 volatile uint32_t fld : 32;
15042 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR122_s ALT_GIC_DIST_GICD_IPRIORITYR122_t;
15046 #define ALT_GIC_DIST_GICD_IPRIORITYR122_RESET 0x00000000
15048 #define ALT_GIC_DIST_GICD_IPRIORITYR122_OFST 0x5e8
15071 #define ALT_GIC_DIST_GICD_IPRIORITYR123_FLD_LSB 0
15073 #define ALT_GIC_DIST_GICD_IPRIORITYR123_FLD_MSB 31
15075 #define ALT_GIC_DIST_GICD_IPRIORITYR123_FLD_WIDTH 32
15077 #define ALT_GIC_DIST_GICD_IPRIORITYR123_FLD_SET_MSK 0xffffffff
15079 #define ALT_GIC_DIST_GICD_IPRIORITYR123_FLD_CLR_MSK 0x00000000
15081 #define ALT_GIC_DIST_GICD_IPRIORITYR123_FLD_RESET 0x0
15083 #define ALT_GIC_DIST_GICD_IPRIORITYR123_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15085 #define ALT_GIC_DIST_GICD_IPRIORITYR123_FLD_SET(value) (((value) << 0) & 0xffffffff)
15087 #ifndef __ASSEMBLY__
15099 struct ALT_GIC_DIST_GICD_IPRIORITYR123_s
15101 volatile uint32_t fld : 32;
15105 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR123_s ALT_GIC_DIST_GICD_IPRIORITYR123_t;
15109 #define ALT_GIC_DIST_GICD_IPRIORITYR123_RESET 0x00000000
15111 #define ALT_GIC_DIST_GICD_IPRIORITYR123_OFST 0x5ec
15134 #define ALT_GIC_DIST_GICD_IPRIORITYR124_FLD_LSB 0
15136 #define ALT_GIC_DIST_GICD_IPRIORITYR124_FLD_MSB 31
15138 #define ALT_GIC_DIST_GICD_IPRIORITYR124_FLD_WIDTH 32
15140 #define ALT_GIC_DIST_GICD_IPRIORITYR124_FLD_SET_MSK 0xffffffff
15142 #define ALT_GIC_DIST_GICD_IPRIORITYR124_FLD_CLR_MSK 0x00000000
15144 #define ALT_GIC_DIST_GICD_IPRIORITYR124_FLD_RESET 0x0
15146 #define ALT_GIC_DIST_GICD_IPRIORITYR124_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15148 #define ALT_GIC_DIST_GICD_IPRIORITYR124_FLD_SET(value) (((value) << 0) & 0xffffffff)
15150 #ifndef __ASSEMBLY__
15162 struct ALT_GIC_DIST_GICD_IPRIORITYR124_s
15164 volatile uint32_t fld : 32;
15168 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR124_s ALT_GIC_DIST_GICD_IPRIORITYR124_t;
15172 #define ALT_GIC_DIST_GICD_IPRIORITYR124_RESET 0x00000000
15174 #define ALT_GIC_DIST_GICD_IPRIORITYR124_OFST 0x5f0
15197 #define ALT_GIC_DIST_GICD_IPRIORITYR125_FLD_LSB 0
15199 #define ALT_GIC_DIST_GICD_IPRIORITYR125_FLD_MSB 31
15201 #define ALT_GIC_DIST_GICD_IPRIORITYR125_FLD_WIDTH 32
15203 #define ALT_GIC_DIST_GICD_IPRIORITYR125_FLD_SET_MSK 0xffffffff
15205 #define ALT_GIC_DIST_GICD_IPRIORITYR125_FLD_CLR_MSK 0x00000000
15207 #define ALT_GIC_DIST_GICD_IPRIORITYR125_FLD_RESET 0x0
15209 #define ALT_GIC_DIST_GICD_IPRIORITYR125_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15211 #define ALT_GIC_DIST_GICD_IPRIORITYR125_FLD_SET(value) (((value) << 0) & 0xffffffff)
15213 #ifndef __ASSEMBLY__
15225 struct ALT_GIC_DIST_GICD_IPRIORITYR125_s
15227 volatile uint32_t fld : 32;
15231 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR125_s ALT_GIC_DIST_GICD_IPRIORITYR125_t;
15235 #define ALT_GIC_DIST_GICD_IPRIORITYR125_RESET 0x00000000
15237 #define ALT_GIC_DIST_GICD_IPRIORITYR125_OFST 0x5f4
15260 #define ALT_GIC_DIST_GICD_IPRIORITYR126_FLD_LSB 0
15262 #define ALT_GIC_DIST_GICD_IPRIORITYR126_FLD_MSB 31
15264 #define ALT_GIC_DIST_GICD_IPRIORITYR126_FLD_WIDTH 32
15266 #define ALT_GIC_DIST_GICD_IPRIORITYR126_FLD_SET_MSK 0xffffffff
15268 #define ALT_GIC_DIST_GICD_IPRIORITYR126_FLD_CLR_MSK 0x00000000
15270 #define ALT_GIC_DIST_GICD_IPRIORITYR126_FLD_RESET 0x0
15272 #define ALT_GIC_DIST_GICD_IPRIORITYR126_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15274 #define ALT_GIC_DIST_GICD_IPRIORITYR126_FLD_SET(value) (((value) << 0) & 0xffffffff)
15276 #ifndef __ASSEMBLY__
15288 struct ALT_GIC_DIST_GICD_IPRIORITYR126_s
15290 volatile uint32_t fld : 32;
15294 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR126_s ALT_GIC_DIST_GICD_IPRIORITYR126_t;
15298 #define ALT_GIC_DIST_GICD_IPRIORITYR126_RESET 0x00000000
15300 #define ALT_GIC_DIST_GICD_IPRIORITYR126_OFST 0x5f8
15323 #define ALT_GIC_DIST_GICD_IPRIORITYR127_FLD_LSB 0
15325 #define ALT_GIC_DIST_GICD_IPRIORITYR127_FLD_MSB 31
15327 #define ALT_GIC_DIST_GICD_IPRIORITYR127_FLD_WIDTH 32
15329 #define ALT_GIC_DIST_GICD_IPRIORITYR127_FLD_SET_MSK 0xffffffff
15331 #define ALT_GIC_DIST_GICD_IPRIORITYR127_FLD_CLR_MSK 0x00000000
15333 #define ALT_GIC_DIST_GICD_IPRIORITYR127_FLD_RESET 0x0
15335 #define ALT_GIC_DIST_GICD_IPRIORITYR127_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15337 #define ALT_GIC_DIST_GICD_IPRIORITYR127_FLD_SET(value) (((value) << 0) & 0xffffffff)
15339 #ifndef __ASSEMBLY__
15351 struct ALT_GIC_DIST_GICD_IPRIORITYR127_s
15353 volatile uint32_t fld : 32;
15357 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR127_s ALT_GIC_DIST_GICD_IPRIORITYR127_t;
15361 #define ALT_GIC_DIST_GICD_IPRIORITYR127_RESET 0x00000000
15363 #define ALT_GIC_DIST_GICD_IPRIORITYR127_OFST 0x5fc
15386 #define ALT_GIC_DIST_GICD_ITARGETSR0_FLD_LSB 0
15388 #define ALT_GIC_DIST_GICD_ITARGETSR0_FLD_MSB 31
15390 #define ALT_GIC_DIST_GICD_ITARGETSR0_FLD_WIDTH 32
15392 #define ALT_GIC_DIST_GICD_ITARGETSR0_FLD_SET_MSK 0xffffffff
15394 #define ALT_GIC_DIST_GICD_ITARGETSR0_FLD_CLR_MSK 0x00000000
15396 #define ALT_GIC_DIST_GICD_ITARGETSR0_FLD_RESET 0x0
15398 #define ALT_GIC_DIST_GICD_ITARGETSR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15400 #define ALT_GIC_DIST_GICD_ITARGETSR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
15402 #ifndef __ASSEMBLY__
15414 struct ALT_GIC_DIST_GICD_ITARGETSR0_s
15416 volatile uint32_t fld : 32;
15420 typedef struct ALT_GIC_DIST_GICD_ITARGETSR0_s ALT_GIC_DIST_GICD_ITARGETSR0_t;
15424 #define ALT_GIC_DIST_GICD_ITARGETSR0_RESET 0x00000000
15426 #define ALT_GIC_DIST_GICD_ITARGETSR0_OFST 0x800
15449 #define ALT_GIC_DIST_GICD_ITARGETSR1_FLD_LSB 0
15451 #define ALT_GIC_DIST_GICD_ITARGETSR1_FLD_MSB 31
15453 #define ALT_GIC_DIST_GICD_ITARGETSR1_FLD_WIDTH 32
15455 #define ALT_GIC_DIST_GICD_ITARGETSR1_FLD_SET_MSK 0xffffffff
15457 #define ALT_GIC_DIST_GICD_ITARGETSR1_FLD_CLR_MSK 0x00000000
15459 #define ALT_GIC_DIST_GICD_ITARGETSR1_FLD_RESET 0x0
15461 #define ALT_GIC_DIST_GICD_ITARGETSR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15463 #define ALT_GIC_DIST_GICD_ITARGETSR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
15465 #ifndef __ASSEMBLY__
15477 struct ALT_GIC_DIST_GICD_ITARGETSR1_s
15479 volatile uint32_t fld : 32;
15483 typedef struct ALT_GIC_DIST_GICD_ITARGETSR1_s ALT_GIC_DIST_GICD_ITARGETSR1_t;
15487 #define ALT_GIC_DIST_GICD_ITARGETSR1_RESET 0x00000000
15489 #define ALT_GIC_DIST_GICD_ITARGETSR1_OFST 0x804
15512 #define ALT_GIC_DIST_GICD_ITARGETSR2_FLD_LSB 0
15514 #define ALT_GIC_DIST_GICD_ITARGETSR2_FLD_MSB 31
15516 #define ALT_GIC_DIST_GICD_ITARGETSR2_FLD_WIDTH 32
15518 #define ALT_GIC_DIST_GICD_ITARGETSR2_FLD_SET_MSK 0xffffffff
15520 #define ALT_GIC_DIST_GICD_ITARGETSR2_FLD_CLR_MSK 0x00000000
15522 #define ALT_GIC_DIST_GICD_ITARGETSR2_FLD_RESET 0x0
15524 #define ALT_GIC_DIST_GICD_ITARGETSR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15526 #define ALT_GIC_DIST_GICD_ITARGETSR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
15528 #ifndef __ASSEMBLY__
15540 struct ALT_GIC_DIST_GICD_ITARGETSR2_s
15542 volatile uint32_t fld : 32;
15546 typedef struct ALT_GIC_DIST_GICD_ITARGETSR2_s ALT_GIC_DIST_GICD_ITARGETSR2_t;
15550 #define ALT_GIC_DIST_GICD_ITARGETSR2_RESET 0x00000000
15552 #define ALT_GIC_DIST_GICD_ITARGETSR2_OFST 0x808
15575 #define ALT_GIC_DIST_GICD_ITARGETSR3_FLD_LSB 0
15577 #define ALT_GIC_DIST_GICD_ITARGETSR3_FLD_MSB 31
15579 #define ALT_GIC_DIST_GICD_ITARGETSR3_FLD_WIDTH 32
15581 #define ALT_GIC_DIST_GICD_ITARGETSR3_FLD_SET_MSK 0xffffffff
15583 #define ALT_GIC_DIST_GICD_ITARGETSR3_FLD_CLR_MSK 0x00000000
15585 #define ALT_GIC_DIST_GICD_ITARGETSR3_FLD_RESET 0x0
15587 #define ALT_GIC_DIST_GICD_ITARGETSR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15589 #define ALT_GIC_DIST_GICD_ITARGETSR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
15591 #ifndef __ASSEMBLY__
15603 struct ALT_GIC_DIST_GICD_ITARGETSR3_s
15605 volatile uint32_t fld : 32;
15609 typedef struct ALT_GIC_DIST_GICD_ITARGETSR3_s ALT_GIC_DIST_GICD_ITARGETSR3_t;
15613 #define ALT_GIC_DIST_GICD_ITARGETSR3_RESET 0x00000000
15615 #define ALT_GIC_DIST_GICD_ITARGETSR3_OFST 0x80c
15638 #define ALT_GIC_DIST_GICD_ITARGETSR4_FLD_LSB 0
15640 #define ALT_GIC_DIST_GICD_ITARGETSR4_FLD_MSB 31
15642 #define ALT_GIC_DIST_GICD_ITARGETSR4_FLD_WIDTH 32
15644 #define ALT_GIC_DIST_GICD_ITARGETSR4_FLD_SET_MSK 0xffffffff
15646 #define ALT_GIC_DIST_GICD_ITARGETSR4_FLD_CLR_MSK 0x00000000
15648 #define ALT_GIC_DIST_GICD_ITARGETSR4_FLD_RESET 0x0
15650 #define ALT_GIC_DIST_GICD_ITARGETSR4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15652 #define ALT_GIC_DIST_GICD_ITARGETSR4_FLD_SET(value) (((value) << 0) & 0xffffffff)
15654 #ifndef __ASSEMBLY__
15666 struct ALT_GIC_DIST_GICD_ITARGETSR4_s
15668 volatile uint32_t fld : 32;
15672 typedef struct ALT_GIC_DIST_GICD_ITARGETSR4_s ALT_GIC_DIST_GICD_ITARGETSR4_t;
15676 #define ALT_GIC_DIST_GICD_ITARGETSR4_RESET 0x00000000
15678 #define ALT_GIC_DIST_GICD_ITARGETSR4_OFST 0x810
15701 #define ALT_GIC_DIST_GICD_ITARGETSR5_FLD_LSB 0
15703 #define ALT_GIC_DIST_GICD_ITARGETSR5_FLD_MSB 31
15705 #define ALT_GIC_DIST_GICD_ITARGETSR5_FLD_WIDTH 32
15707 #define ALT_GIC_DIST_GICD_ITARGETSR5_FLD_SET_MSK 0xffffffff
15709 #define ALT_GIC_DIST_GICD_ITARGETSR5_FLD_CLR_MSK 0x00000000
15711 #define ALT_GIC_DIST_GICD_ITARGETSR5_FLD_RESET 0x0
15713 #define ALT_GIC_DIST_GICD_ITARGETSR5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15715 #define ALT_GIC_DIST_GICD_ITARGETSR5_FLD_SET(value) (((value) << 0) & 0xffffffff)
15717 #ifndef __ASSEMBLY__
15729 struct ALT_GIC_DIST_GICD_ITARGETSR5_s
15731 volatile uint32_t fld : 32;
15735 typedef struct ALT_GIC_DIST_GICD_ITARGETSR5_s ALT_GIC_DIST_GICD_ITARGETSR5_t;
15739 #define ALT_GIC_DIST_GICD_ITARGETSR5_RESET 0x00000000
15741 #define ALT_GIC_DIST_GICD_ITARGETSR5_OFST 0x814
15764 #define ALT_GIC_DIST_GICD_ITARGETSR6_FLD_LSB 0
15766 #define ALT_GIC_DIST_GICD_ITARGETSR6_FLD_MSB 31
15768 #define ALT_GIC_DIST_GICD_ITARGETSR6_FLD_WIDTH 32
15770 #define ALT_GIC_DIST_GICD_ITARGETSR6_FLD_SET_MSK 0xffffffff
15772 #define ALT_GIC_DIST_GICD_ITARGETSR6_FLD_CLR_MSK 0x00000000
15774 #define ALT_GIC_DIST_GICD_ITARGETSR6_FLD_RESET 0x0
15776 #define ALT_GIC_DIST_GICD_ITARGETSR6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15778 #define ALT_GIC_DIST_GICD_ITARGETSR6_FLD_SET(value) (((value) << 0) & 0xffffffff)
15780 #ifndef __ASSEMBLY__
15792 struct ALT_GIC_DIST_GICD_ITARGETSR6_s
15794 volatile uint32_t fld : 32;
15798 typedef struct ALT_GIC_DIST_GICD_ITARGETSR6_s ALT_GIC_DIST_GICD_ITARGETSR6_t;
15802 #define ALT_GIC_DIST_GICD_ITARGETSR6_RESET 0x00000000
15804 #define ALT_GIC_DIST_GICD_ITARGETSR6_OFST 0x818
15827 #define ALT_GIC_DIST_GICD_ITARGETSR7_FLD_LSB 0
15829 #define ALT_GIC_DIST_GICD_ITARGETSR7_FLD_MSB 31
15831 #define ALT_GIC_DIST_GICD_ITARGETSR7_FLD_WIDTH 32
15833 #define ALT_GIC_DIST_GICD_ITARGETSR7_FLD_SET_MSK 0xffffffff
15835 #define ALT_GIC_DIST_GICD_ITARGETSR7_FLD_CLR_MSK 0x00000000
15837 #define ALT_GIC_DIST_GICD_ITARGETSR7_FLD_RESET 0x0
15839 #define ALT_GIC_DIST_GICD_ITARGETSR7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15841 #define ALT_GIC_DIST_GICD_ITARGETSR7_FLD_SET(value) (((value) << 0) & 0xffffffff)
15843 #ifndef __ASSEMBLY__
15855 struct ALT_GIC_DIST_GICD_ITARGETSR7_s
15857 volatile uint32_t fld : 32;
15861 typedef struct ALT_GIC_DIST_GICD_ITARGETSR7_s ALT_GIC_DIST_GICD_ITARGETSR7_t;
15865 #define ALT_GIC_DIST_GICD_ITARGETSR7_RESET 0x00000000
15867 #define ALT_GIC_DIST_GICD_ITARGETSR7_OFST 0x81c
15890 #define ALT_GIC_DIST_GICD_ITARGETSR8_FLD_LSB 0
15892 #define ALT_GIC_DIST_GICD_ITARGETSR8_FLD_MSB 31
15894 #define ALT_GIC_DIST_GICD_ITARGETSR8_FLD_WIDTH 32
15896 #define ALT_GIC_DIST_GICD_ITARGETSR8_FLD_SET_MSK 0xffffffff
15898 #define ALT_GIC_DIST_GICD_ITARGETSR8_FLD_CLR_MSK 0x00000000
15900 #define ALT_GIC_DIST_GICD_ITARGETSR8_FLD_RESET 0x0
15902 #define ALT_GIC_DIST_GICD_ITARGETSR8_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15904 #define ALT_GIC_DIST_GICD_ITARGETSR8_FLD_SET(value) (((value) << 0) & 0xffffffff)
15906 #ifndef __ASSEMBLY__
15918 struct ALT_GIC_DIST_GICD_ITARGETSR8_s
15920 volatile uint32_t fld : 32;
15924 typedef struct ALT_GIC_DIST_GICD_ITARGETSR8_s ALT_GIC_DIST_GICD_ITARGETSR8_t;
15928 #define ALT_GIC_DIST_GICD_ITARGETSR8_RESET 0x00000000
15930 #define ALT_GIC_DIST_GICD_ITARGETSR8_OFST 0x820
15953 #define ALT_GIC_DIST_GICD_ITARGETSR9_FLD_LSB 0
15955 #define ALT_GIC_DIST_GICD_ITARGETSR9_FLD_MSB 31
15957 #define ALT_GIC_DIST_GICD_ITARGETSR9_FLD_WIDTH 32
15959 #define ALT_GIC_DIST_GICD_ITARGETSR9_FLD_SET_MSK 0xffffffff
15961 #define ALT_GIC_DIST_GICD_ITARGETSR9_FLD_CLR_MSK 0x00000000
15963 #define ALT_GIC_DIST_GICD_ITARGETSR9_FLD_RESET 0x0
15965 #define ALT_GIC_DIST_GICD_ITARGETSR9_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15967 #define ALT_GIC_DIST_GICD_ITARGETSR9_FLD_SET(value) (((value) << 0) & 0xffffffff)
15969 #ifndef __ASSEMBLY__
15981 struct ALT_GIC_DIST_GICD_ITARGETSR9_s
15983 volatile uint32_t fld : 32;
15987 typedef struct ALT_GIC_DIST_GICD_ITARGETSR9_s ALT_GIC_DIST_GICD_ITARGETSR9_t;
15991 #define ALT_GIC_DIST_GICD_ITARGETSR9_RESET 0x00000000
15993 #define ALT_GIC_DIST_GICD_ITARGETSR9_OFST 0x824
16016 #define ALT_GIC_DIST_GICD_ITARGETSR10_FLD_LSB 0
16018 #define ALT_GIC_DIST_GICD_ITARGETSR10_FLD_MSB 31
16020 #define ALT_GIC_DIST_GICD_ITARGETSR10_FLD_WIDTH 32
16022 #define ALT_GIC_DIST_GICD_ITARGETSR10_FLD_SET_MSK 0xffffffff
16024 #define ALT_GIC_DIST_GICD_ITARGETSR10_FLD_CLR_MSK 0x00000000
16026 #define ALT_GIC_DIST_GICD_ITARGETSR10_FLD_RESET 0x0
16028 #define ALT_GIC_DIST_GICD_ITARGETSR10_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16030 #define ALT_GIC_DIST_GICD_ITARGETSR10_FLD_SET(value) (((value) << 0) & 0xffffffff)
16032 #ifndef __ASSEMBLY__
16044 struct ALT_GIC_DIST_GICD_ITARGETSR10_s
16046 volatile uint32_t fld : 32;
16050 typedef struct ALT_GIC_DIST_GICD_ITARGETSR10_s ALT_GIC_DIST_GICD_ITARGETSR10_t;
16054 #define ALT_GIC_DIST_GICD_ITARGETSR10_RESET 0x00000000
16056 #define ALT_GIC_DIST_GICD_ITARGETSR10_OFST 0x828
16079 #define ALT_GIC_DIST_GICD_ITARGETSR11_FLD_LSB 0
16081 #define ALT_GIC_DIST_GICD_ITARGETSR11_FLD_MSB 31
16083 #define ALT_GIC_DIST_GICD_ITARGETSR11_FLD_WIDTH 32
16085 #define ALT_GIC_DIST_GICD_ITARGETSR11_FLD_SET_MSK 0xffffffff
16087 #define ALT_GIC_DIST_GICD_ITARGETSR11_FLD_CLR_MSK 0x00000000
16089 #define ALT_GIC_DIST_GICD_ITARGETSR11_FLD_RESET 0x0
16091 #define ALT_GIC_DIST_GICD_ITARGETSR11_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16093 #define ALT_GIC_DIST_GICD_ITARGETSR11_FLD_SET(value) (((value) << 0) & 0xffffffff)
16095 #ifndef __ASSEMBLY__
16107 struct ALT_GIC_DIST_GICD_ITARGETSR11_s
16109 volatile uint32_t fld : 32;
16113 typedef struct ALT_GIC_DIST_GICD_ITARGETSR11_s ALT_GIC_DIST_GICD_ITARGETSR11_t;
16117 #define ALT_GIC_DIST_GICD_ITARGETSR11_RESET 0x00000000
16119 #define ALT_GIC_DIST_GICD_ITARGETSR11_OFST 0x82c
16142 #define ALT_GIC_DIST_GICD_ITARGETSR12_FLD_LSB 0
16144 #define ALT_GIC_DIST_GICD_ITARGETSR12_FLD_MSB 31
16146 #define ALT_GIC_DIST_GICD_ITARGETSR12_FLD_WIDTH 32
16148 #define ALT_GIC_DIST_GICD_ITARGETSR12_FLD_SET_MSK 0xffffffff
16150 #define ALT_GIC_DIST_GICD_ITARGETSR12_FLD_CLR_MSK 0x00000000
16152 #define ALT_GIC_DIST_GICD_ITARGETSR12_FLD_RESET 0x0
16154 #define ALT_GIC_DIST_GICD_ITARGETSR12_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16156 #define ALT_GIC_DIST_GICD_ITARGETSR12_FLD_SET(value) (((value) << 0) & 0xffffffff)
16158 #ifndef __ASSEMBLY__
16170 struct ALT_GIC_DIST_GICD_ITARGETSR12_s
16172 volatile uint32_t fld : 32;
16176 typedef struct ALT_GIC_DIST_GICD_ITARGETSR12_s ALT_GIC_DIST_GICD_ITARGETSR12_t;
16180 #define ALT_GIC_DIST_GICD_ITARGETSR12_RESET 0x00000000
16182 #define ALT_GIC_DIST_GICD_ITARGETSR12_OFST 0x830
16205 #define ALT_GIC_DIST_GICD_ITARGETSR13_FLD_LSB 0
16207 #define ALT_GIC_DIST_GICD_ITARGETSR13_FLD_MSB 31
16209 #define ALT_GIC_DIST_GICD_ITARGETSR13_FLD_WIDTH 32
16211 #define ALT_GIC_DIST_GICD_ITARGETSR13_FLD_SET_MSK 0xffffffff
16213 #define ALT_GIC_DIST_GICD_ITARGETSR13_FLD_CLR_MSK 0x00000000
16215 #define ALT_GIC_DIST_GICD_ITARGETSR13_FLD_RESET 0x0
16217 #define ALT_GIC_DIST_GICD_ITARGETSR13_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16219 #define ALT_GIC_DIST_GICD_ITARGETSR13_FLD_SET(value) (((value) << 0) & 0xffffffff)
16221 #ifndef __ASSEMBLY__
16233 struct ALT_GIC_DIST_GICD_ITARGETSR13_s
16235 volatile uint32_t fld : 32;
16239 typedef struct ALT_GIC_DIST_GICD_ITARGETSR13_s ALT_GIC_DIST_GICD_ITARGETSR13_t;
16243 #define ALT_GIC_DIST_GICD_ITARGETSR13_RESET 0x00000000
16245 #define ALT_GIC_DIST_GICD_ITARGETSR13_OFST 0x834
16268 #define ALT_GIC_DIST_GICD_ITARGETSR14_FLD_LSB 0
16270 #define ALT_GIC_DIST_GICD_ITARGETSR14_FLD_MSB 31
16272 #define ALT_GIC_DIST_GICD_ITARGETSR14_FLD_WIDTH 32
16274 #define ALT_GIC_DIST_GICD_ITARGETSR14_FLD_SET_MSK 0xffffffff
16276 #define ALT_GIC_DIST_GICD_ITARGETSR14_FLD_CLR_MSK 0x00000000
16278 #define ALT_GIC_DIST_GICD_ITARGETSR14_FLD_RESET 0x0
16280 #define ALT_GIC_DIST_GICD_ITARGETSR14_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16282 #define ALT_GIC_DIST_GICD_ITARGETSR14_FLD_SET(value) (((value) << 0) & 0xffffffff)
16284 #ifndef __ASSEMBLY__
16296 struct ALT_GIC_DIST_GICD_ITARGETSR14_s
16298 volatile uint32_t fld : 32;
16302 typedef struct ALT_GIC_DIST_GICD_ITARGETSR14_s ALT_GIC_DIST_GICD_ITARGETSR14_t;
16306 #define ALT_GIC_DIST_GICD_ITARGETSR14_RESET 0x00000000
16308 #define ALT_GIC_DIST_GICD_ITARGETSR14_OFST 0x838
16331 #define ALT_GIC_DIST_GICD_ITARGETSR15_FLD_LSB 0
16333 #define ALT_GIC_DIST_GICD_ITARGETSR15_FLD_MSB 31
16335 #define ALT_GIC_DIST_GICD_ITARGETSR15_FLD_WIDTH 32
16337 #define ALT_GIC_DIST_GICD_ITARGETSR15_FLD_SET_MSK 0xffffffff
16339 #define ALT_GIC_DIST_GICD_ITARGETSR15_FLD_CLR_MSK 0x00000000
16341 #define ALT_GIC_DIST_GICD_ITARGETSR15_FLD_RESET 0x0
16343 #define ALT_GIC_DIST_GICD_ITARGETSR15_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16345 #define ALT_GIC_DIST_GICD_ITARGETSR15_FLD_SET(value) (((value) << 0) & 0xffffffff)
16347 #ifndef __ASSEMBLY__
16359 struct ALT_GIC_DIST_GICD_ITARGETSR15_s
16361 volatile uint32_t fld : 32;
16365 typedef struct ALT_GIC_DIST_GICD_ITARGETSR15_s ALT_GIC_DIST_GICD_ITARGETSR15_t;
16369 #define ALT_GIC_DIST_GICD_ITARGETSR15_RESET 0x00000000
16371 #define ALT_GIC_DIST_GICD_ITARGETSR15_OFST 0x83c
16394 #define ALT_GIC_DIST_GICD_ITARGETSR16_FLD_LSB 0
16396 #define ALT_GIC_DIST_GICD_ITARGETSR16_FLD_MSB 31
16398 #define ALT_GIC_DIST_GICD_ITARGETSR16_FLD_WIDTH 32
16400 #define ALT_GIC_DIST_GICD_ITARGETSR16_FLD_SET_MSK 0xffffffff
16402 #define ALT_GIC_DIST_GICD_ITARGETSR16_FLD_CLR_MSK 0x00000000
16404 #define ALT_GIC_DIST_GICD_ITARGETSR16_FLD_RESET 0x0
16406 #define ALT_GIC_DIST_GICD_ITARGETSR16_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16408 #define ALT_GIC_DIST_GICD_ITARGETSR16_FLD_SET(value) (((value) << 0) & 0xffffffff)
16410 #ifndef __ASSEMBLY__
16422 struct ALT_GIC_DIST_GICD_ITARGETSR16_s
16424 volatile uint32_t fld : 32;
16428 typedef struct ALT_GIC_DIST_GICD_ITARGETSR16_s ALT_GIC_DIST_GICD_ITARGETSR16_t;
16432 #define ALT_GIC_DIST_GICD_ITARGETSR16_RESET 0x00000000
16434 #define ALT_GIC_DIST_GICD_ITARGETSR16_OFST 0x840
16457 #define ALT_GIC_DIST_GICD_ITARGETSR17_FLD_LSB 0
16459 #define ALT_GIC_DIST_GICD_ITARGETSR17_FLD_MSB 31
16461 #define ALT_GIC_DIST_GICD_ITARGETSR17_FLD_WIDTH 32
16463 #define ALT_GIC_DIST_GICD_ITARGETSR17_FLD_SET_MSK 0xffffffff
16465 #define ALT_GIC_DIST_GICD_ITARGETSR17_FLD_CLR_MSK 0x00000000
16467 #define ALT_GIC_DIST_GICD_ITARGETSR17_FLD_RESET 0x0
16469 #define ALT_GIC_DIST_GICD_ITARGETSR17_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16471 #define ALT_GIC_DIST_GICD_ITARGETSR17_FLD_SET(value) (((value) << 0) & 0xffffffff)
16473 #ifndef __ASSEMBLY__
16485 struct ALT_GIC_DIST_GICD_ITARGETSR17_s
16487 volatile uint32_t fld : 32;
16491 typedef struct ALT_GIC_DIST_GICD_ITARGETSR17_s ALT_GIC_DIST_GICD_ITARGETSR17_t;
16495 #define ALT_GIC_DIST_GICD_ITARGETSR17_RESET 0x00000000
16497 #define ALT_GIC_DIST_GICD_ITARGETSR17_OFST 0x844
16520 #define ALT_GIC_DIST_GICD_ITARGETSR18_FLD_LSB 0
16522 #define ALT_GIC_DIST_GICD_ITARGETSR18_FLD_MSB 31
16524 #define ALT_GIC_DIST_GICD_ITARGETSR18_FLD_WIDTH 32
16526 #define ALT_GIC_DIST_GICD_ITARGETSR18_FLD_SET_MSK 0xffffffff
16528 #define ALT_GIC_DIST_GICD_ITARGETSR18_FLD_CLR_MSK 0x00000000
16530 #define ALT_GIC_DIST_GICD_ITARGETSR18_FLD_RESET 0x0
16532 #define ALT_GIC_DIST_GICD_ITARGETSR18_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16534 #define ALT_GIC_DIST_GICD_ITARGETSR18_FLD_SET(value) (((value) << 0) & 0xffffffff)
16536 #ifndef __ASSEMBLY__
16548 struct ALT_GIC_DIST_GICD_ITARGETSR18_s
16550 volatile uint32_t fld : 32;
16554 typedef struct ALT_GIC_DIST_GICD_ITARGETSR18_s ALT_GIC_DIST_GICD_ITARGETSR18_t;
16558 #define ALT_GIC_DIST_GICD_ITARGETSR18_RESET 0x00000000
16560 #define ALT_GIC_DIST_GICD_ITARGETSR18_OFST 0x848
16583 #define ALT_GIC_DIST_GICD_ITARGETSR19_FLD_LSB 0
16585 #define ALT_GIC_DIST_GICD_ITARGETSR19_FLD_MSB 31
16587 #define ALT_GIC_DIST_GICD_ITARGETSR19_FLD_WIDTH 32
16589 #define ALT_GIC_DIST_GICD_ITARGETSR19_FLD_SET_MSK 0xffffffff
16591 #define ALT_GIC_DIST_GICD_ITARGETSR19_FLD_CLR_MSK 0x00000000
16593 #define ALT_GIC_DIST_GICD_ITARGETSR19_FLD_RESET 0x0
16595 #define ALT_GIC_DIST_GICD_ITARGETSR19_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16597 #define ALT_GIC_DIST_GICD_ITARGETSR19_FLD_SET(value) (((value) << 0) & 0xffffffff)
16599 #ifndef __ASSEMBLY__
16611 struct ALT_GIC_DIST_GICD_ITARGETSR19_s
16613 volatile uint32_t fld : 32;
16617 typedef struct ALT_GIC_DIST_GICD_ITARGETSR19_s ALT_GIC_DIST_GICD_ITARGETSR19_t;
16621 #define ALT_GIC_DIST_GICD_ITARGETSR19_RESET 0x00000000
16623 #define ALT_GIC_DIST_GICD_ITARGETSR19_OFST 0x84c
16646 #define ALT_GIC_DIST_GICD_ITARGETSR20_FLD_LSB 0
16648 #define ALT_GIC_DIST_GICD_ITARGETSR20_FLD_MSB 31
16650 #define ALT_GIC_DIST_GICD_ITARGETSR20_FLD_WIDTH 32
16652 #define ALT_GIC_DIST_GICD_ITARGETSR20_FLD_SET_MSK 0xffffffff
16654 #define ALT_GIC_DIST_GICD_ITARGETSR20_FLD_CLR_MSK 0x00000000
16656 #define ALT_GIC_DIST_GICD_ITARGETSR20_FLD_RESET 0x0
16658 #define ALT_GIC_DIST_GICD_ITARGETSR20_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16660 #define ALT_GIC_DIST_GICD_ITARGETSR20_FLD_SET(value) (((value) << 0) & 0xffffffff)
16662 #ifndef __ASSEMBLY__
16674 struct ALT_GIC_DIST_GICD_ITARGETSR20_s
16676 volatile uint32_t fld : 32;
16680 typedef struct ALT_GIC_DIST_GICD_ITARGETSR20_s ALT_GIC_DIST_GICD_ITARGETSR20_t;
16684 #define ALT_GIC_DIST_GICD_ITARGETSR20_RESET 0x00000000
16686 #define ALT_GIC_DIST_GICD_ITARGETSR20_OFST 0x850
16709 #define ALT_GIC_DIST_GICD_ITARGETSR21_FLD_LSB 0
16711 #define ALT_GIC_DIST_GICD_ITARGETSR21_FLD_MSB 31
16713 #define ALT_GIC_DIST_GICD_ITARGETSR21_FLD_WIDTH 32
16715 #define ALT_GIC_DIST_GICD_ITARGETSR21_FLD_SET_MSK 0xffffffff
16717 #define ALT_GIC_DIST_GICD_ITARGETSR21_FLD_CLR_MSK 0x00000000
16719 #define ALT_GIC_DIST_GICD_ITARGETSR21_FLD_RESET 0x0
16721 #define ALT_GIC_DIST_GICD_ITARGETSR21_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16723 #define ALT_GIC_DIST_GICD_ITARGETSR21_FLD_SET(value) (((value) << 0) & 0xffffffff)
16725 #ifndef __ASSEMBLY__
16737 struct ALT_GIC_DIST_GICD_ITARGETSR21_s
16739 volatile uint32_t fld : 32;
16743 typedef struct ALT_GIC_DIST_GICD_ITARGETSR21_s ALT_GIC_DIST_GICD_ITARGETSR21_t;
16747 #define ALT_GIC_DIST_GICD_ITARGETSR21_RESET 0x00000000
16749 #define ALT_GIC_DIST_GICD_ITARGETSR21_OFST 0x854
16772 #define ALT_GIC_DIST_GICD_ITARGETSR22_FLD_LSB 0
16774 #define ALT_GIC_DIST_GICD_ITARGETSR22_FLD_MSB 31
16776 #define ALT_GIC_DIST_GICD_ITARGETSR22_FLD_WIDTH 32
16778 #define ALT_GIC_DIST_GICD_ITARGETSR22_FLD_SET_MSK 0xffffffff
16780 #define ALT_GIC_DIST_GICD_ITARGETSR22_FLD_CLR_MSK 0x00000000
16782 #define ALT_GIC_DIST_GICD_ITARGETSR22_FLD_RESET 0x0
16784 #define ALT_GIC_DIST_GICD_ITARGETSR22_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16786 #define ALT_GIC_DIST_GICD_ITARGETSR22_FLD_SET(value) (((value) << 0) & 0xffffffff)
16788 #ifndef __ASSEMBLY__
16800 struct ALT_GIC_DIST_GICD_ITARGETSR22_s
16802 volatile uint32_t fld : 32;
16806 typedef struct ALT_GIC_DIST_GICD_ITARGETSR22_s ALT_GIC_DIST_GICD_ITARGETSR22_t;
16810 #define ALT_GIC_DIST_GICD_ITARGETSR22_RESET 0x00000000
16812 #define ALT_GIC_DIST_GICD_ITARGETSR22_OFST 0x858
16835 #define ALT_GIC_DIST_GICD_ITARGETSR23_FLD_LSB 0
16837 #define ALT_GIC_DIST_GICD_ITARGETSR23_FLD_MSB 31
16839 #define ALT_GIC_DIST_GICD_ITARGETSR23_FLD_WIDTH 32
16841 #define ALT_GIC_DIST_GICD_ITARGETSR23_FLD_SET_MSK 0xffffffff
16843 #define ALT_GIC_DIST_GICD_ITARGETSR23_FLD_CLR_MSK 0x00000000
16845 #define ALT_GIC_DIST_GICD_ITARGETSR23_FLD_RESET 0x0
16847 #define ALT_GIC_DIST_GICD_ITARGETSR23_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16849 #define ALT_GIC_DIST_GICD_ITARGETSR23_FLD_SET(value) (((value) << 0) & 0xffffffff)
16851 #ifndef __ASSEMBLY__
16863 struct ALT_GIC_DIST_GICD_ITARGETSR23_s
16865 volatile uint32_t fld : 32;
16869 typedef struct ALT_GIC_DIST_GICD_ITARGETSR23_s ALT_GIC_DIST_GICD_ITARGETSR23_t;
16873 #define ALT_GIC_DIST_GICD_ITARGETSR23_RESET 0x00000000
16875 #define ALT_GIC_DIST_GICD_ITARGETSR23_OFST 0x85c
16898 #define ALT_GIC_DIST_GICD_ITARGETSR24_FLD_LSB 0
16900 #define ALT_GIC_DIST_GICD_ITARGETSR24_FLD_MSB 31
16902 #define ALT_GIC_DIST_GICD_ITARGETSR24_FLD_WIDTH 32
16904 #define ALT_GIC_DIST_GICD_ITARGETSR24_FLD_SET_MSK 0xffffffff
16906 #define ALT_GIC_DIST_GICD_ITARGETSR24_FLD_CLR_MSK 0x00000000
16908 #define ALT_GIC_DIST_GICD_ITARGETSR24_FLD_RESET 0x0
16910 #define ALT_GIC_DIST_GICD_ITARGETSR24_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16912 #define ALT_GIC_DIST_GICD_ITARGETSR24_FLD_SET(value) (((value) << 0) & 0xffffffff)
16914 #ifndef __ASSEMBLY__
16926 struct ALT_GIC_DIST_GICD_ITARGETSR24_s
16928 volatile uint32_t fld : 32;
16932 typedef struct ALT_GIC_DIST_GICD_ITARGETSR24_s ALT_GIC_DIST_GICD_ITARGETSR24_t;
16936 #define ALT_GIC_DIST_GICD_ITARGETSR24_RESET 0x00000000
16938 #define ALT_GIC_DIST_GICD_ITARGETSR24_OFST 0x860
16961 #define ALT_GIC_DIST_GICD_ITARGETSR25_FLD_LSB 0
16963 #define ALT_GIC_DIST_GICD_ITARGETSR25_FLD_MSB 31
16965 #define ALT_GIC_DIST_GICD_ITARGETSR25_FLD_WIDTH 32
16967 #define ALT_GIC_DIST_GICD_ITARGETSR25_FLD_SET_MSK 0xffffffff
16969 #define ALT_GIC_DIST_GICD_ITARGETSR25_FLD_CLR_MSK 0x00000000
16971 #define ALT_GIC_DIST_GICD_ITARGETSR25_FLD_RESET 0x0
16973 #define ALT_GIC_DIST_GICD_ITARGETSR25_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16975 #define ALT_GIC_DIST_GICD_ITARGETSR25_FLD_SET(value) (((value) << 0) & 0xffffffff)
16977 #ifndef __ASSEMBLY__
16989 struct ALT_GIC_DIST_GICD_ITARGETSR25_s
16991 volatile uint32_t fld : 32;
16995 typedef struct ALT_GIC_DIST_GICD_ITARGETSR25_s ALT_GIC_DIST_GICD_ITARGETSR25_t;
16999 #define ALT_GIC_DIST_GICD_ITARGETSR25_RESET 0x00000000
17001 #define ALT_GIC_DIST_GICD_ITARGETSR25_OFST 0x864
17024 #define ALT_GIC_DIST_GICD_ITARGETSR26_FLD_LSB 0
17026 #define ALT_GIC_DIST_GICD_ITARGETSR26_FLD_MSB 31
17028 #define ALT_GIC_DIST_GICD_ITARGETSR26_FLD_WIDTH 32
17030 #define ALT_GIC_DIST_GICD_ITARGETSR26_FLD_SET_MSK 0xffffffff
17032 #define ALT_GIC_DIST_GICD_ITARGETSR26_FLD_CLR_MSK 0x00000000
17034 #define ALT_GIC_DIST_GICD_ITARGETSR26_FLD_RESET 0x0
17036 #define ALT_GIC_DIST_GICD_ITARGETSR26_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17038 #define ALT_GIC_DIST_GICD_ITARGETSR26_FLD_SET(value) (((value) << 0) & 0xffffffff)
17040 #ifndef __ASSEMBLY__
17052 struct ALT_GIC_DIST_GICD_ITARGETSR26_s
17054 volatile uint32_t fld : 32;
17058 typedef struct ALT_GIC_DIST_GICD_ITARGETSR26_s ALT_GIC_DIST_GICD_ITARGETSR26_t;
17062 #define ALT_GIC_DIST_GICD_ITARGETSR26_RESET 0x00000000
17064 #define ALT_GIC_DIST_GICD_ITARGETSR26_OFST 0x868
17087 #define ALT_GIC_DIST_GICD_ITARGETSR27_FLD_LSB 0
17089 #define ALT_GIC_DIST_GICD_ITARGETSR27_FLD_MSB 31
17091 #define ALT_GIC_DIST_GICD_ITARGETSR27_FLD_WIDTH 32
17093 #define ALT_GIC_DIST_GICD_ITARGETSR27_FLD_SET_MSK 0xffffffff
17095 #define ALT_GIC_DIST_GICD_ITARGETSR27_FLD_CLR_MSK 0x00000000
17097 #define ALT_GIC_DIST_GICD_ITARGETSR27_FLD_RESET 0x0
17099 #define ALT_GIC_DIST_GICD_ITARGETSR27_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17101 #define ALT_GIC_DIST_GICD_ITARGETSR27_FLD_SET(value) (((value) << 0) & 0xffffffff)
17103 #ifndef __ASSEMBLY__
17115 struct ALT_GIC_DIST_GICD_ITARGETSR27_s
17117 volatile uint32_t fld : 32;
17121 typedef struct ALT_GIC_DIST_GICD_ITARGETSR27_s ALT_GIC_DIST_GICD_ITARGETSR27_t;
17125 #define ALT_GIC_DIST_GICD_ITARGETSR27_RESET 0x00000000
17127 #define ALT_GIC_DIST_GICD_ITARGETSR27_OFST 0x86c
17150 #define ALT_GIC_DIST_GICD_ITARGETSR28_FLD_LSB 0
17152 #define ALT_GIC_DIST_GICD_ITARGETSR28_FLD_MSB 31
17154 #define ALT_GIC_DIST_GICD_ITARGETSR28_FLD_WIDTH 32
17156 #define ALT_GIC_DIST_GICD_ITARGETSR28_FLD_SET_MSK 0xffffffff
17158 #define ALT_GIC_DIST_GICD_ITARGETSR28_FLD_CLR_MSK 0x00000000
17160 #define ALT_GIC_DIST_GICD_ITARGETSR28_FLD_RESET 0x0
17162 #define ALT_GIC_DIST_GICD_ITARGETSR28_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17164 #define ALT_GIC_DIST_GICD_ITARGETSR28_FLD_SET(value) (((value) << 0) & 0xffffffff)
17166 #ifndef __ASSEMBLY__
17178 struct ALT_GIC_DIST_GICD_ITARGETSR28_s
17180 volatile uint32_t fld : 32;
17184 typedef struct ALT_GIC_DIST_GICD_ITARGETSR28_s ALT_GIC_DIST_GICD_ITARGETSR28_t;
17188 #define ALT_GIC_DIST_GICD_ITARGETSR28_RESET 0x00000000
17190 #define ALT_GIC_DIST_GICD_ITARGETSR28_OFST 0x870
17213 #define ALT_GIC_DIST_GICD_ITARGETSR29_FLD_LSB 0
17215 #define ALT_GIC_DIST_GICD_ITARGETSR29_FLD_MSB 31
17217 #define ALT_GIC_DIST_GICD_ITARGETSR29_FLD_WIDTH 32
17219 #define ALT_GIC_DIST_GICD_ITARGETSR29_FLD_SET_MSK 0xffffffff
17221 #define ALT_GIC_DIST_GICD_ITARGETSR29_FLD_CLR_MSK 0x00000000
17223 #define ALT_GIC_DIST_GICD_ITARGETSR29_FLD_RESET 0x0
17225 #define ALT_GIC_DIST_GICD_ITARGETSR29_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17227 #define ALT_GIC_DIST_GICD_ITARGETSR29_FLD_SET(value) (((value) << 0) & 0xffffffff)
17229 #ifndef __ASSEMBLY__
17241 struct ALT_GIC_DIST_GICD_ITARGETSR29_s
17243 volatile uint32_t fld : 32;
17247 typedef struct ALT_GIC_DIST_GICD_ITARGETSR29_s ALT_GIC_DIST_GICD_ITARGETSR29_t;
17251 #define ALT_GIC_DIST_GICD_ITARGETSR29_RESET 0x00000000
17253 #define ALT_GIC_DIST_GICD_ITARGETSR29_OFST 0x874
17276 #define ALT_GIC_DIST_GICD_ITARGETSR30_FLD_LSB 0
17278 #define ALT_GIC_DIST_GICD_ITARGETSR30_FLD_MSB 31
17280 #define ALT_GIC_DIST_GICD_ITARGETSR30_FLD_WIDTH 32
17282 #define ALT_GIC_DIST_GICD_ITARGETSR30_FLD_SET_MSK 0xffffffff
17284 #define ALT_GIC_DIST_GICD_ITARGETSR30_FLD_CLR_MSK 0x00000000
17286 #define ALT_GIC_DIST_GICD_ITARGETSR30_FLD_RESET 0x0
17288 #define ALT_GIC_DIST_GICD_ITARGETSR30_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17290 #define ALT_GIC_DIST_GICD_ITARGETSR30_FLD_SET(value) (((value) << 0) & 0xffffffff)
17292 #ifndef __ASSEMBLY__
17304 struct ALT_GIC_DIST_GICD_ITARGETSR30_s
17306 volatile uint32_t fld : 32;
17310 typedef struct ALT_GIC_DIST_GICD_ITARGETSR30_s ALT_GIC_DIST_GICD_ITARGETSR30_t;
17314 #define ALT_GIC_DIST_GICD_ITARGETSR30_RESET 0x00000000
17316 #define ALT_GIC_DIST_GICD_ITARGETSR30_OFST 0x878
17339 #define ALT_GIC_DIST_GICD_ITARGETSR31_FLD_LSB 0
17341 #define ALT_GIC_DIST_GICD_ITARGETSR31_FLD_MSB 31
17343 #define ALT_GIC_DIST_GICD_ITARGETSR31_FLD_WIDTH 32
17345 #define ALT_GIC_DIST_GICD_ITARGETSR31_FLD_SET_MSK 0xffffffff
17347 #define ALT_GIC_DIST_GICD_ITARGETSR31_FLD_CLR_MSK 0x00000000
17349 #define ALT_GIC_DIST_GICD_ITARGETSR31_FLD_RESET 0x0
17351 #define ALT_GIC_DIST_GICD_ITARGETSR31_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17353 #define ALT_GIC_DIST_GICD_ITARGETSR31_FLD_SET(value) (((value) << 0) & 0xffffffff)
17355 #ifndef __ASSEMBLY__
17367 struct ALT_GIC_DIST_GICD_ITARGETSR31_s
17369 volatile uint32_t fld : 32;
17373 typedef struct ALT_GIC_DIST_GICD_ITARGETSR31_s ALT_GIC_DIST_GICD_ITARGETSR31_t;
17377 #define ALT_GIC_DIST_GICD_ITARGETSR31_RESET 0x00000000
17379 #define ALT_GIC_DIST_GICD_ITARGETSR31_OFST 0x87c
17402 #define ALT_GIC_DIST_GICD_ITARGETSR32_FLD_LSB 0
17404 #define ALT_GIC_DIST_GICD_ITARGETSR32_FLD_MSB 31
17406 #define ALT_GIC_DIST_GICD_ITARGETSR32_FLD_WIDTH 32
17408 #define ALT_GIC_DIST_GICD_ITARGETSR32_FLD_SET_MSK 0xffffffff
17410 #define ALT_GIC_DIST_GICD_ITARGETSR32_FLD_CLR_MSK 0x00000000
17412 #define ALT_GIC_DIST_GICD_ITARGETSR32_FLD_RESET 0x0
17414 #define ALT_GIC_DIST_GICD_ITARGETSR32_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17416 #define ALT_GIC_DIST_GICD_ITARGETSR32_FLD_SET(value) (((value) << 0) & 0xffffffff)
17418 #ifndef __ASSEMBLY__
17430 struct ALT_GIC_DIST_GICD_ITARGETSR32_s
17432 volatile uint32_t fld : 32;
17436 typedef struct ALT_GIC_DIST_GICD_ITARGETSR32_s ALT_GIC_DIST_GICD_ITARGETSR32_t;
17440 #define ALT_GIC_DIST_GICD_ITARGETSR32_RESET 0x00000000
17442 #define ALT_GIC_DIST_GICD_ITARGETSR32_OFST 0x880
17465 #define ALT_GIC_DIST_GICD_ITARGETSR33_FLD_LSB 0
17467 #define ALT_GIC_DIST_GICD_ITARGETSR33_FLD_MSB 31
17469 #define ALT_GIC_DIST_GICD_ITARGETSR33_FLD_WIDTH 32
17471 #define ALT_GIC_DIST_GICD_ITARGETSR33_FLD_SET_MSK 0xffffffff
17473 #define ALT_GIC_DIST_GICD_ITARGETSR33_FLD_CLR_MSK 0x00000000
17475 #define ALT_GIC_DIST_GICD_ITARGETSR33_FLD_RESET 0x0
17477 #define ALT_GIC_DIST_GICD_ITARGETSR33_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17479 #define ALT_GIC_DIST_GICD_ITARGETSR33_FLD_SET(value) (((value) << 0) & 0xffffffff)
17481 #ifndef __ASSEMBLY__
17493 struct ALT_GIC_DIST_GICD_ITARGETSR33_s
17495 volatile uint32_t fld : 32;
17499 typedef struct ALT_GIC_DIST_GICD_ITARGETSR33_s ALT_GIC_DIST_GICD_ITARGETSR33_t;
17503 #define ALT_GIC_DIST_GICD_ITARGETSR33_RESET 0x00000000
17505 #define ALT_GIC_DIST_GICD_ITARGETSR33_OFST 0x884
17528 #define ALT_GIC_DIST_GICD_ITARGETSR34_FLD_LSB 0
17530 #define ALT_GIC_DIST_GICD_ITARGETSR34_FLD_MSB 31
17532 #define ALT_GIC_DIST_GICD_ITARGETSR34_FLD_WIDTH 32
17534 #define ALT_GIC_DIST_GICD_ITARGETSR34_FLD_SET_MSK 0xffffffff
17536 #define ALT_GIC_DIST_GICD_ITARGETSR34_FLD_CLR_MSK 0x00000000
17538 #define ALT_GIC_DIST_GICD_ITARGETSR34_FLD_RESET 0x0
17540 #define ALT_GIC_DIST_GICD_ITARGETSR34_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17542 #define ALT_GIC_DIST_GICD_ITARGETSR34_FLD_SET(value) (((value) << 0) & 0xffffffff)
17544 #ifndef __ASSEMBLY__
17556 struct ALT_GIC_DIST_GICD_ITARGETSR34_s
17558 volatile uint32_t fld : 32;
17562 typedef struct ALT_GIC_DIST_GICD_ITARGETSR34_s ALT_GIC_DIST_GICD_ITARGETSR34_t;
17566 #define ALT_GIC_DIST_GICD_ITARGETSR34_RESET 0x00000000
17568 #define ALT_GIC_DIST_GICD_ITARGETSR34_OFST 0x888
17591 #define ALT_GIC_DIST_GICD_ITARGETSR35_FLD_LSB 0
17593 #define ALT_GIC_DIST_GICD_ITARGETSR35_FLD_MSB 31
17595 #define ALT_GIC_DIST_GICD_ITARGETSR35_FLD_WIDTH 32
17597 #define ALT_GIC_DIST_GICD_ITARGETSR35_FLD_SET_MSK 0xffffffff
17599 #define ALT_GIC_DIST_GICD_ITARGETSR35_FLD_CLR_MSK 0x00000000
17601 #define ALT_GIC_DIST_GICD_ITARGETSR35_FLD_RESET 0x0
17603 #define ALT_GIC_DIST_GICD_ITARGETSR35_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17605 #define ALT_GIC_DIST_GICD_ITARGETSR35_FLD_SET(value) (((value) << 0) & 0xffffffff)
17607 #ifndef __ASSEMBLY__
17619 struct ALT_GIC_DIST_GICD_ITARGETSR35_s
17621 volatile uint32_t fld : 32;
17625 typedef struct ALT_GIC_DIST_GICD_ITARGETSR35_s ALT_GIC_DIST_GICD_ITARGETSR35_t;
17629 #define ALT_GIC_DIST_GICD_ITARGETSR35_RESET 0x00000000
17631 #define ALT_GIC_DIST_GICD_ITARGETSR35_OFST 0x88c
17654 #define ALT_GIC_DIST_GICD_ITARGETSR36_FLD_LSB 0
17656 #define ALT_GIC_DIST_GICD_ITARGETSR36_FLD_MSB 31
17658 #define ALT_GIC_DIST_GICD_ITARGETSR36_FLD_WIDTH 32
17660 #define ALT_GIC_DIST_GICD_ITARGETSR36_FLD_SET_MSK 0xffffffff
17662 #define ALT_GIC_DIST_GICD_ITARGETSR36_FLD_CLR_MSK 0x00000000
17664 #define ALT_GIC_DIST_GICD_ITARGETSR36_FLD_RESET 0x0
17666 #define ALT_GIC_DIST_GICD_ITARGETSR36_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17668 #define ALT_GIC_DIST_GICD_ITARGETSR36_FLD_SET(value) (((value) << 0) & 0xffffffff)
17670 #ifndef __ASSEMBLY__
17682 struct ALT_GIC_DIST_GICD_ITARGETSR36_s
17684 volatile uint32_t fld : 32;
17688 typedef struct ALT_GIC_DIST_GICD_ITARGETSR36_s ALT_GIC_DIST_GICD_ITARGETSR36_t;
17692 #define ALT_GIC_DIST_GICD_ITARGETSR36_RESET 0x00000000
17694 #define ALT_GIC_DIST_GICD_ITARGETSR36_OFST 0x890
17717 #define ALT_GIC_DIST_GICD_ITARGETSR37_FLD_LSB 0
17719 #define ALT_GIC_DIST_GICD_ITARGETSR37_FLD_MSB 31
17721 #define ALT_GIC_DIST_GICD_ITARGETSR37_FLD_WIDTH 32
17723 #define ALT_GIC_DIST_GICD_ITARGETSR37_FLD_SET_MSK 0xffffffff
17725 #define ALT_GIC_DIST_GICD_ITARGETSR37_FLD_CLR_MSK 0x00000000
17727 #define ALT_GIC_DIST_GICD_ITARGETSR37_FLD_RESET 0x0
17729 #define ALT_GIC_DIST_GICD_ITARGETSR37_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17731 #define ALT_GIC_DIST_GICD_ITARGETSR37_FLD_SET(value) (((value) << 0) & 0xffffffff)
17733 #ifndef __ASSEMBLY__
17745 struct ALT_GIC_DIST_GICD_ITARGETSR37_s
17747 volatile uint32_t fld : 32;
17751 typedef struct ALT_GIC_DIST_GICD_ITARGETSR37_s ALT_GIC_DIST_GICD_ITARGETSR37_t;
17755 #define ALT_GIC_DIST_GICD_ITARGETSR37_RESET 0x00000000
17757 #define ALT_GIC_DIST_GICD_ITARGETSR37_OFST 0x894
17780 #define ALT_GIC_DIST_GICD_ITARGETSR38_FLD_LSB 0
17782 #define ALT_GIC_DIST_GICD_ITARGETSR38_FLD_MSB 31
17784 #define ALT_GIC_DIST_GICD_ITARGETSR38_FLD_WIDTH 32
17786 #define ALT_GIC_DIST_GICD_ITARGETSR38_FLD_SET_MSK 0xffffffff
17788 #define ALT_GIC_DIST_GICD_ITARGETSR38_FLD_CLR_MSK 0x00000000
17790 #define ALT_GIC_DIST_GICD_ITARGETSR38_FLD_RESET 0x0
17792 #define ALT_GIC_DIST_GICD_ITARGETSR38_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17794 #define ALT_GIC_DIST_GICD_ITARGETSR38_FLD_SET(value) (((value) << 0) & 0xffffffff)
17796 #ifndef __ASSEMBLY__
17808 struct ALT_GIC_DIST_GICD_ITARGETSR38_s
17810 volatile uint32_t fld : 32;
17814 typedef struct ALT_GIC_DIST_GICD_ITARGETSR38_s ALT_GIC_DIST_GICD_ITARGETSR38_t;
17818 #define ALT_GIC_DIST_GICD_ITARGETSR38_RESET 0x00000000
17820 #define ALT_GIC_DIST_GICD_ITARGETSR38_OFST 0x898
17843 #define ALT_GIC_DIST_GICD_ITARGETSR39_FLD_LSB 0
17845 #define ALT_GIC_DIST_GICD_ITARGETSR39_FLD_MSB 31
17847 #define ALT_GIC_DIST_GICD_ITARGETSR39_FLD_WIDTH 32
17849 #define ALT_GIC_DIST_GICD_ITARGETSR39_FLD_SET_MSK 0xffffffff
17851 #define ALT_GIC_DIST_GICD_ITARGETSR39_FLD_CLR_MSK 0x00000000
17853 #define ALT_GIC_DIST_GICD_ITARGETSR39_FLD_RESET 0x0
17855 #define ALT_GIC_DIST_GICD_ITARGETSR39_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17857 #define ALT_GIC_DIST_GICD_ITARGETSR39_FLD_SET(value) (((value) << 0) & 0xffffffff)
17859 #ifndef __ASSEMBLY__
17871 struct ALT_GIC_DIST_GICD_ITARGETSR39_s
17873 volatile uint32_t fld : 32;
17877 typedef struct ALT_GIC_DIST_GICD_ITARGETSR39_s ALT_GIC_DIST_GICD_ITARGETSR39_t;
17881 #define ALT_GIC_DIST_GICD_ITARGETSR39_RESET 0x00000000
17883 #define ALT_GIC_DIST_GICD_ITARGETSR39_OFST 0x89c
17906 #define ALT_GIC_DIST_GICD_ITARGETSR40_FLD_LSB 0
17908 #define ALT_GIC_DIST_GICD_ITARGETSR40_FLD_MSB 31
17910 #define ALT_GIC_DIST_GICD_ITARGETSR40_FLD_WIDTH 32
17912 #define ALT_GIC_DIST_GICD_ITARGETSR40_FLD_SET_MSK 0xffffffff
17914 #define ALT_GIC_DIST_GICD_ITARGETSR40_FLD_CLR_MSK 0x00000000
17916 #define ALT_GIC_DIST_GICD_ITARGETSR40_FLD_RESET 0x0
17918 #define ALT_GIC_DIST_GICD_ITARGETSR40_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17920 #define ALT_GIC_DIST_GICD_ITARGETSR40_FLD_SET(value) (((value) << 0) & 0xffffffff)
17922 #ifndef __ASSEMBLY__
17934 struct ALT_GIC_DIST_GICD_ITARGETSR40_s
17936 volatile uint32_t fld : 32;
17940 typedef struct ALT_GIC_DIST_GICD_ITARGETSR40_s ALT_GIC_DIST_GICD_ITARGETSR40_t;
17944 #define ALT_GIC_DIST_GICD_ITARGETSR40_RESET 0x00000000
17946 #define ALT_GIC_DIST_GICD_ITARGETSR40_OFST 0x8a0
17969 #define ALT_GIC_DIST_GICD_ITARGETSR41_FLD_LSB 0
17971 #define ALT_GIC_DIST_GICD_ITARGETSR41_FLD_MSB 31
17973 #define ALT_GIC_DIST_GICD_ITARGETSR41_FLD_WIDTH 32
17975 #define ALT_GIC_DIST_GICD_ITARGETSR41_FLD_SET_MSK 0xffffffff
17977 #define ALT_GIC_DIST_GICD_ITARGETSR41_FLD_CLR_MSK 0x00000000
17979 #define ALT_GIC_DIST_GICD_ITARGETSR41_FLD_RESET 0x0
17981 #define ALT_GIC_DIST_GICD_ITARGETSR41_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17983 #define ALT_GIC_DIST_GICD_ITARGETSR41_FLD_SET(value) (((value) << 0) & 0xffffffff)
17985 #ifndef __ASSEMBLY__
17997 struct ALT_GIC_DIST_GICD_ITARGETSR41_s
17999 volatile uint32_t fld : 32;
18003 typedef struct ALT_GIC_DIST_GICD_ITARGETSR41_s ALT_GIC_DIST_GICD_ITARGETSR41_t;
18007 #define ALT_GIC_DIST_GICD_ITARGETSR41_RESET 0x00000000
18009 #define ALT_GIC_DIST_GICD_ITARGETSR41_OFST 0x8a4
18032 #define ALT_GIC_DIST_GICD_ITARGETSR42_FLD_LSB 0
18034 #define ALT_GIC_DIST_GICD_ITARGETSR42_FLD_MSB 31
18036 #define ALT_GIC_DIST_GICD_ITARGETSR42_FLD_WIDTH 32
18038 #define ALT_GIC_DIST_GICD_ITARGETSR42_FLD_SET_MSK 0xffffffff
18040 #define ALT_GIC_DIST_GICD_ITARGETSR42_FLD_CLR_MSK 0x00000000
18042 #define ALT_GIC_DIST_GICD_ITARGETSR42_FLD_RESET 0x0
18044 #define ALT_GIC_DIST_GICD_ITARGETSR42_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18046 #define ALT_GIC_DIST_GICD_ITARGETSR42_FLD_SET(value) (((value) << 0) & 0xffffffff)
18048 #ifndef __ASSEMBLY__
18060 struct ALT_GIC_DIST_GICD_ITARGETSR42_s
18062 volatile uint32_t fld : 32;
18066 typedef struct ALT_GIC_DIST_GICD_ITARGETSR42_s ALT_GIC_DIST_GICD_ITARGETSR42_t;
18070 #define ALT_GIC_DIST_GICD_ITARGETSR42_RESET 0x00000000
18072 #define ALT_GIC_DIST_GICD_ITARGETSR42_OFST 0x8a8
18095 #define ALT_GIC_DIST_GICD_ITARGETSR43_FLD_LSB 0
18097 #define ALT_GIC_DIST_GICD_ITARGETSR43_FLD_MSB 31
18099 #define ALT_GIC_DIST_GICD_ITARGETSR43_FLD_WIDTH 32
18101 #define ALT_GIC_DIST_GICD_ITARGETSR43_FLD_SET_MSK 0xffffffff
18103 #define ALT_GIC_DIST_GICD_ITARGETSR43_FLD_CLR_MSK 0x00000000
18105 #define ALT_GIC_DIST_GICD_ITARGETSR43_FLD_RESET 0x0
18107 #define ALT_GIC_DIST_GICD_ITARGETSR43_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18109 #define ALT_GIC_DIST_GICD_ITARGETSR43_FLD_SET(value) (((value) << 0) & 0xffffffff)
18111 #ifndef __ASSEMBLY__
18123 struct ALT_GIC_DIST_GICD_ITARGETSR43_s
18125 volatile uint32_t fld : 32;
18129 typedef struct ALT_GIC_DIST_GICD_ITARGETSR43_s ALT_GIC_DIST_GICD_ITARGETSR43_t;
18133 #define ALT_GIC_DIST_GICD_ITARGETSR43_RESET 0x00000000
18135 #define ALT_GIC_DIST_GICD_ITARGETSR43_OFST 0x8ac
18158 #define ALT_GIC_DIST_GICD_ITARGETSR44_FLD_LSB 0
18160 #define ALT_GIC_DIST_GICD_ITARGETSR44_FLD_MSB 31
18162 #define ALT_GIC_DIST_GICD_ITARGETSR44_FLD_WIDTH 32
18164 #define ALT_GIC_DIST_GICD_ITARGETSR44_FLD_SET_MSK 0xffffffff
18166 #define ALT_GIC_DIST_GICD_ITARGETSR44_FLD_CLR_MSK 0x00000000
18168 #define ALT_GIC_DIST_GICD_ITARGETSR44_FLD_RESET 0x0
18170 #define ALT_GIC_DIST_GICD_ITARGETSR44_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18172 #define ALT_GIC_DIST_GICD_ITARGETSR44_FLD_SET(value) (((value) << 0) & 0xffffffff)
18174 #ifndef __ASSEMBLY__
18186 struct ALT_GIC_DIST_GICD_ITARGETSR44_s
18188 volatile uint32_t fld : 32;
18192 typedef struct ALT_GIC_DIST_GICD_ITARGETSR44_s ALT_GIC_DIST_GICD_ITARGETSR44_t;
18196 #define ALT_GIC_DIST_GICD_ITARGETSR44_RESET 0x00000000
18198 #define ALT_GIC_DIST_GICD_ITARGETSR44_OFST 0x8b0
18221 #define ALT_GIC_DIST_GICD_ITARGETSR45_FLD_LSB 0
18223 #define ALT_GIC_DIST_GICD_ITARGETSR45_FLD_MSB 31
18225 #define ALT_GIC_DIST_GICD_ITARGETSR45_FLD_WIDTH 32
18227 #define ALT_GIC_DIST_GICD_ITARGETSR45_FLD_SET_MSK 0xffffffff
18229 #define ALT_GIC_DIST_GICD_ITARGETSR45_FLD_CLR_MSK 0x00000000
18231 #define ALT_GIC_DIST_GICD_ITARGETSR45_FLD_RESET 0x0
18233 #define ALT_GIC_DIST_GICD_ITARGETSR45_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18235 #define ALT_GIC_DIST_GICD_ITARGETSR45_FLD_SET(value) (((value) << 0) & 0xffffffff)
18237 #ifndef __ASSEMBLY__
18249 struct ALT_GIC_DIST_GICD_ITARGETSR45_s
18251 volatile uint32_t fld : 32;
18255 typedef struct ALT_GIC_DIST_GICD_ITARGETSR45_s ALT_GIC_DIST_GICD_ITARGETSR45_t;
18259 #define ALT_GIC_DIST_GICD_ITARGETSR45_RESET 0x00000000
18261 #define ALT_GIC_DIST_GICD_ITARGETSR45_OFST 0x8b4
18284 #define ALT_GIC_DIST_GICD_ITARGETSR46_FLD_LSB 0
18286 #define ALT_GIC_DIST_GICD_ITARGETSR46_FLD_MSB 31
18288 #define ALT_GIC_DIST_GICD_ITARGETSR46_FLD_WIDTH 32
18290 #define ALT_GIC_DIST_GICD_ITARGETSR46_FLD_SET_MSK 0xffffffff
18292 #define ALT_GIC_DIST_GICD_ITARGETSR46_FLD_CLR_MSK 0x00000000
18294 #define ALT_GIC_DIST_GICD_ITARGETSR46_FLD_RESET 0x0
18296 #define ALT_GIC_DIST_GICD_ITARGETSR46_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18298 #define ALT_GIC_DIST_GICD_ITARGETSR46_FLD_SET(value) (((value) << 0) & 0xffffffff)
18300 #ifndef __ASSEMBLY__
18312 struct ALT_GIC_DIST_GICD_ITARGETSR46_s
18314 volatile uint32_t fld : 32;
18318 typedef struct ALT_GIC_DIST_GICD_ITARGETSR46_s ALT_GIC_DIST_GICD_ITARGETSR46_t;
18322 #define ALT_GIC_DIST_GICD_ITARGETSR46_RESET 0x00000000
18324 #define ALT_GIC_DIST_GICD_ITARGETSR46_OFST 0x8b8
18347 #define ALT_GIC_DIST_GICD_ITARGETSR47_FLD_LSB 0
18349 #define ALT_GIC_DIST_GICD_ITARGETSR47_FLD_MSB 31
18351 #define ALT_GIC_DIST_GICD_ITARGETSR47_FLD_WIDTH 32
18353 #define ALT_GIC_DIST_GICD_ITARGETSR47_FLD_SET_MSK 0xffffffff
18355 #define ALT_GIC_DIST_GICD_ITARGETSR47_FLD_CLR_MSK 0x00000000
18357 #define ALT_GIC_DIST_GICD_ITARGETSR47_FLD_RESET 0x0
18359 #define ALT_GIC_DIST_GICD_ITARGETSR47_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18361 #define ALT_GIC_DIST_GICD_ITARGETSR47_FLD_SET(value) (((value) << 0) & 0xffffffff)
18363 #ifndef __ASSEMBLY__
18375 struct ALT_GIC_DIST_GICD_ITARGETSR47_s
18377 volatile uint32_t fld : 32;
18381 typedef struct ALT_GIC_DIST_GICD_ITARGETSR47_s ALT_GIC_DIST_GICD_ITARGETSR47_t;
18385 #define ALT_GIC_DIST_GICD_ITARGETSR47_RESET 0x00000000
18387 #define ALT_GIC_DIST_GICD_ITARGETSR47_OFST 0x8bc
18410 #define ALT_GIC_DIST_GICD_ITARGETSR48_FLD_LSB 0
18412 #define ALT_GIC_DIST_GICD_ITARGETSR48_FLD_MSB 31
18414 #define ALT_GIC_DIST_GICD_ITARGETSR48_FLD_WIDTH 32
18416 #define ALT_GIC_DIST_GICD_ITARGETSR48_FLD_SET_MSK 0xffffffff
18418 #define ALT_GIC_DIST_GICD_ITARGETSR48_FLD_CLR_MSK 0x00000000
18420 #define ALT_GIC_DIST_GICD_ITARGETSR48_FLD_RESET 0x0
18422 #define ALT_GIC_DIST_GICD_ITARGETSR48_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18424 #define ALT_GIC_DIST_GICD_ITARGETSR48_FLD_SET(value) (((value) << 0) & 0xffffffff)
18426 #ifndef __ASSEMBLY__
18438 struct ALT_GIC_DIST_GICD_ITARGETSR48_s
18440 volatile uint32_t fld : 32;
18444 typedef struct ALT_GIC_DIST_GICD_ITARGETSR48_s ALT_GIC_DIST_GICD_ITARGETSR48_t;
18448 #define ALT_GIC_DIST_GICD_ITARGETSR48_RESET 0x00000000
18450 #define ALT_GIC_DIST_GICD_ITARGETSR48_OFST 0x8c0
18473 #define ALT_GIC_DIST_GICD_ITARGETSR49_FLD_LSB 0
18475 #define ALT_GIC_DIST_GICD_ITARGETSR49_FLD_MSB 31
18477 #define ALT_GIC_DIST_GICD_ITARGETSR49_FLD_WIDTH 32
18479 #define ALT_GIC_DIST_GICD_ITARGETSR49_FLD_SET_MSK 0xffffffff
18481 #define ALT_GIC_DIST_GICD_ITARGETSR49_FLD_CLR_MSK 0x00000000
18483 #define ALT_GIC_DIST_GICD_ITARGETSR49_FLD_RESET 0x0
18485 #define ALT_GIC_DIST_GICD_ITARGETSR49_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18487 #define ALT_GIC_DIST_GICD_ITARGETSR49_FLD_SET(value) (((value) << 0) & 0xffffffff)
18489 #ifndef __ASSEMBLY__
18501 struct ALT_GIC_DIST_GICD_ITARGETSR49_s
18503 volatile uint32_t fld : 32;
18507 typedef struct ALT_GIC_DIST_GICD_ITARGETSR49_s ALT_GIC_DIST_GICD_ITARGETSR49_t;
18511 #define ALT_GIC_DIST_GICD_ITARGETSR49_RESET 0x00000000
18513 #define ALT_GIC_DIST_GICD_ITARGETSR49_OFST 0x8c4
18536 #define ALT_GIC_DIST_GICD_ITARGETSR50_FLD_LSB 0
18538 #define ALT_GIC_DIST_GICD_ITARGETSR50_FLD_MSB 31
18540 #define ALT_GIC_DIST_GICD_ITARGETSR50_FLD_WIDTH 32
18542 #define ALT_GIC_DIST_GICD_ITARGETSR50_FLD_SET_MSK 0xffffffff
18544 #define ALT_GIC_DIST_GICD_ITARGETSR50_FLD_CLR_MSK 0x00000000
18546 #define ALT_GIC_DIST_GICD_ITARGETSR50_FLD_RESET 0x0
18548 #define ALT_GIC_DIST_GICD_ITARGETSR50_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18550 #define ALT_GIC_DIST_GICD_ITARGETSR50_FLD_SET(value) (((value) << 0) & 0xffffffff)
18552 #ifndef __ASSEMBLY__
18564 struct ALT_GIC_DIST_GICD_ITARGETSR50_s
18566 volatile uint32_t fld : 32;
18570 typedef struct ALT_GIC_DIST_GICD_ITARGETSR50_s ALT_GIC_DIST_GICD_ITARGETSR50_t;
18574 #define ALT_GIC_DIST_GICD_ITARGETSR50_RESET 0x00000000
18576 #define ALT_GIC_DIST_GICD_ITARGETSR50_OFST 0x8c8
18599 #define ALT_GIC_DIST_GICD_ITARGETSR51_FLD_LSB 0
18601 #define ALT_GIC_DIST_GICD_ITARGETSR51_FLD_MSB 31
18603 #define ALT_GIC_DIST_GICD_ITARGETSR51_FLD_WIDTH 32
18605 #define ALT_GIC_DIST_GICD_ITARGETSR51_FLD_SET_MSK 0xffffffff
18607 #define ALT_GIC_DIST_GICD_ITARGETSR51_FLD_CLR_MSK 0x00000000
18609 #define ALT_GIC_DIST_GICD_ITARGETSR51_FLD_RESET 0x0
18611 #define ALT_GIC_DIST_GICD_ITARGETSR51_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18613 #define ALT_GIC_DIST_GICD_ITARGETSR51_FLD_SET(value) (((value) << 0) & 0xffffffff)
18615 #ifndef __ASSEMBLY__
18627 struct ALT_GIC_DIST_GICD_ITARGETSR51_s
18629 volatile uint32_t fld : 32;
18633 typedef struct ALT_GIC_DIST_GICD_ITARGETSR51_s ALT_GIC_DIST_GICD_ITARGETSR51_t;
18637 #define ALT_GIC_DIST_GICD_ITARGETSR51_RESET 0x00000000
18639 #define ALT_GIC_DIST_GICD_ITARGETSR51_OFST 0x8cc
18662 #define ALT_GIC_DIST_GICD_ITARGETSR52_FLD_LSB 0
18664 #define ALT_GIC_DIST_GICD_ITARGETSR52_FLD_MSB 31
18666 #define ALT_GIC_DIST_GICD_ITARGETSR52_FLD_WIDTH 32
18668 #define ALT_GIC_DIST_GICD_ITARGETSR52_FLD_SET_MSK 0xffffffff
18670 #define ALT_GIC_DIST_GICD_ITARGETSR52_FLD_CLR_MSK 0x00000000
18672 #define ALT_GIC_DIST_GICD_ITARGETSR52_FLD_RESET 0x0
18674 #define ALT_GIC_DIST_GICD_ITARGETSR52_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18676 #define ALT_GIC_DIST_GICD_ITARGETSR52_FLD_SET(value) (((value) << 0) & 0xffffffff)
18678 #ifndef __ASSEMBLY__
18690 struct ALT_GIC_DIST_GICD_ITARGETSR52_s
18692 volatile uint32_t fld : 32;
18696 typedef struct ALT_GIC_DIST_GICD_ITARGETSR52_s ALT_GIC_DIST_GICD_ITARGETSR52_t;
18700 #define ALT_GIC_DIST_GICD_ITARGETSR52_RESET 0x00000000
18702 #define ALT_GIC_DIST_GICD_ITARGETSR52_OFST 0x8d0
18725 #define ALT_GIC_DIST_GICD_ITARGETSR53_FLD_LSB 0
18727 #define ALT_GIC_DIST_GICD_ITARGETSR53_FLD_MSB 31
18729 #define ALT_GIC_DIST_GICD_ITARGETSR53_FLD_WIDTH 32
18731 #define ALT_GIC_DIST_GICD_ITARGETSR53_FLD_SET_MSK 0xffffffff
18733 #define ALT_GIC_DIST_GICD_ITARGETSR53_FLD_CLR_MSK 0x00000000
18735 #define ALT_GIC_DIST_GICD_ITARGETSR53_FLD_RESET 0x0
18737 #define ALT_GIC_DIST_GICD_ITARGETSR53_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18739 #define ALT_GIC_DIST_GICD_ITARGETSR53_FLD_SET(value) (((value) << 0) & 0xffffffff)
18741 #ifndef __ASSEMBLY__
18753 struct ALT_GIC_DIST_GICD_ITARGETSR53_s
18755 volatile uint32_t fld : 32;
18759 typedef struct ALT_GIC_DIST_GICD_ITARGETSR53_s ALT_GIC_DIST_GICD_ITARGETSR53_t;
18763 #define ALT_GIC_DIST_GICD_ITARGETSR53_RESET 0x00000000
18765 #define ALT_GIC_DIST_GICD_ITARGETSR53_OFST 0x8d4
18788 #define ALT_GIC_DIST_GICD_ITARGETSR54_FLD_LSB 0
18790 #define ALT_GIC_DIST_GICD_ITARGETSR54_FLD_MSB 31
18792 #define ALT_GIC_DIST_GICD_ITARGETSR54_FLD_WIDTH 32
18794 #define ALT_GIC_DIST_GICD_ITARGETSR54_FLD_SET_MSK 0xffffffff
18796 #define ALT_GIC_DIST_GICD_ITARGETSR54_FLD_CLR_MSK 0x00000000
18798 #define ALT_GIC_DIST_GICD_ITARGETSR54_FLD_RESET 0x0
18800 #define ALT_GIC_DIST_GICD_ITARGETSR54_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18802 #define ALT_GIC_DIST_GICD_ITARGETSR54_FLD_SET(value) (((value) << 0) & 0xffffffff)
18804 #ifndef __ASSEMBLY__
18816 struct ALT_GIC_DIST_GICD_ITARGETSR54_s
18818 volatile uint32_t fld : 32;
18822 typedef struct ALT_GIC_DIST_GICD_ITARGETSR54_s ALT_GIC_DIST_GICD_ITARGETSR54_t;
18826 #define ALT_GIC_DIST_GICD_ITARGETSR54_RESET 0x00000000
18828 #define ALT_GIC_DIST_GICD_ITARGETSR54_OFST 0x8d8
18851 #define ALT_GIC_DIST_GICD_ITARGETSR55_FLD_LSB 0
18853 #define ALT_GIC_DIST_GICD_ITARGETSR55_FLD_MSB 31
18855 #define ALT_GIC_DIST_GICD_ITARGETSR55_FLD_WIDTH 32
18857 #define ALT_GIC_DIST_GICD_ITARGETSR55_FLD_SET_MSK 0xffffffff
18859 #define ALT_GIC_DIST_GICD_ITARGETSR55_FLD_CLR_MSK 0x00000000
18861 #define ALT_GIC_DIST_GICD_ITARGETSR55_FLD_RESET 0x0
18863 #define ALT_GIC_DIST_GICD_ITARGETSR55_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18865 #define ALT_GIC_DIST_GICD_ITARGETSR55_FLD_SET(value) (((value) << 0) & 0xffffffff)
18867 #ifndef __ASSEMBLY__
18879 struct ALT_GIC_DIST_GICD_ITARGETSR55_s
18881 volatile uint32_t fld : 32;
18885 typedef struct ALT_GIC_DIST_GICD_ITARGETSR55_s ALT_GIC_DIST_GICD_ITARGETSR55_t;
18889 #define ALT_GIC_DIST_GICD_ITARGETSR55_RESET 0x00000000
18891 #define ALT_GIC_DIST_GICD_ITARGETSR55_OFST 0x8dc
18914 #define ALT_GIC_DIST_GICD_ITARGETSR56_FLD_LSB 0
18916 #define ALT_GIC_DIST_GICD_ITARGETSR56_FLD_MSB 31
18918 #define ALT_GIC_DIST_GICD_ITARGETSR56_FLD_WIDTH 32
18920 #define ALT_GIC_DIST_GICD_ITARGETSR56_FLD_SET_MSK 0xffffffff
18922 #define ALT_GIC_DIST_GICD_ITARGETSR56_FLD_CLR_MSK 0x00000000
18924 #define ALT_GIC_DIST_GICD_ITARGETSR56_FLD_RESET 0x0
18926 #define ALT_GIC_DIST_GICD_ITARGETSR56_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18928 #define ALT_GIC_DIST_GICD_ITARGETSR56_FLD_SET(value) (((value) << 0) & 0xffffffff)
18930 #ifndef __ASSEMBLY__
18942 struct ALT_GIC_DIST_GICD_ITARGETSR56_s
18944 volatile uint32_t fld : 32;
18948 typedef struct ALT_GIC_DIST_GICD_ITARGETSR56_s ALT_GIC_DIST_GICD_ITARGETSR56_t;
18952 #define ALT_GIC_DIST_GICD_ITARGETSR56_RESET 0x00000000
18954 #define ALT_GIC_DIST_GICD_ITARGETSR56_OFST 0x8e0
18977 #define ALT_GIC_DIST_GICD_ITARGETSR57_FLD_LSB 0
18979 #define ALT_GIC_DIST_GICD_ITARGETSR57_FLD_MSB 31
18981 #define ALT_GIC_DIST_GICD_ITARGETSR57_FLD_WIDTH 32
18983 #define ALT_GIC_DIST_GICD_ITARGETSR57_FLD_SET_MSK 0xffffffff
18985 #define ALT_GIC_DIST_GICD_ITARGETSR57_FLD_CLR_MSK 0x00000000
18987 #define ALT_GIC_DIST_GICD_ITARGETSR57_FLD_RESET 0x0
18989 #define ALT_GIC_DIST_GICD_ITARGETSR57_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18991 #define ALT_GIC_DIST_GICD_ITARGETSR57_FLD_SET(value) (((value) << 0) & 0xffffffff)
18993 #ifndef __ASSEMBLY__
19005 struct ALT_GIC_DIST_GICD_ITARGETSR57_s
19007 volatile uint32_t fld : 32;
19011 typedef struct ALT_GIC_DIST_GICD_ITARGETSR57_s ALT_GIC_DIST_GICD_ITARGETSR57_t;
19015 #define ALT_GIC_DIST_GICD_ITARGETSR57_RESET 0x00000000
19017 #define ALT_GIC_DIST_GICD_ITARGETSR57_OFST 0x8e4
19040 #define ALT_GIC_DIST_GICD_ITARGETSR58_FLD_LSB 0
19042 #define ALT_GIC_DIST_GICD_ITARGETSR58_FLD_MSB 31
19044 #define ALT_GIC_DIST_GICD_ITARGETSR58_FLD_WIDTH 32
19046 #define ALT_GIC_DIST_GICD_ITARGETSR58_FLD_SET_MSK 0xffffffff
19048 #define ALT_GIC_DIST_GICD_ITARGETSR58_FLD_CLR_MSK 0x00000000
19050 #define ALT_GIC_DIST_GICD_ITARGETSR58_FLD_RESET 0x0
19052 #define ALT_GIC_DIST_GICD_ITARGETSR58_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19054 #define ALT_GIC_DIST_GICD_ITARGETSR58_FLD_SET(value) (((value) << 0) & 0xffffffff)
19056 #ifndef __ASSEMBLY__
19068 struct ALT_GIC_DIST_GICD_ITARGETSR58_s
19070 volatile uint32_t fld : 32;
19074 typedef struct ALT_GIC_DIST_GICD_ITARGETSR58_s ALT_GIC_DIST_GICD_ITARGETSR58_t;
19078 #define ALT_GIC_DIST_GICD_ITARGETSR58_RESET 0x00000000
19080 #define ALT_GIC_DIST_GICD_ITARGETSR58_OFST 0x8e8
19103 #define ALT_GIC_DIST_GICD_ITARGETSR59_FLD_LSB 0
19105 #define ALT_GIC_DIST_GICD_ITARGETSR59_FLD_MSB 31
19107 #define ALT_GIC_DIST_GICD_ITARGETSR59_FLD_WIDTH 32
19109 #define ALT_GIC_DIST_GICD_ITARGETSR59_FLD_SET_MSK 0xffffffff
19111 #define ALT_GIC_DIST_GICD_ITARGETSR59_FLD_CLR_MSK 0x00000000
19113 #define ALT_GIC_DIST_GICD_ITARGETSR59_FLD_RESET 0x0
19115 #define ALT_GIC_DIST_GICD_ITARGETSR59_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19117 #define ALT_GIC_DIST_GICD_ITARGETSR59_FLD_SET(value) (((value) << 0) & 0xffffffff)
19119 #ifndef __ASSEMBLY__
19131 struct ALT_GIC_DIST_GICD_ITARGETSR59_s
19133 volatile uint32_t fld : 32;
19137 typedef struct ALT_GIC_DIST_GICD_ITARGETSR59_s ALT_GIC_DIST_GICD_ITARGETSR59_t;
19141 #define ALT_GIC_DIST_GICD_ITARGETSR59_RESET 0x00000000
19143 #define ALT_GIC_DIST_GICD_ITARGETSR59_OFST 0x8ec
19166 #define ALT_GIC_DIST_GICD_ITARGETSR60_FLD_LSB 0
19168 #define ALT_GIC_DIST_GICD_ITARGETSR60_FLD_MSB 31
19170 #define ALT_GIC_DIST_GICD_ITARGETSR60_FLD_WIDTH 32
19172 #define ALT_GIC_DIST_GICD_ITARGETSR60_FLD_SET_MSK 0xffffffff
19174 #define ALT_GIC_DIST_GICD_ITARGETSR60_FLD_CLR_MSK 0x00000000
19176 #define ALT_GIC_DIST_GICD_ITARGETSR60_FLD_RESET 0x0
19178 #define ALT_GIC_DIST_GICD_ITARGETSR60_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19180 #define ALT_GIC_DIST_GICD_ITARGETSR60_FLD_SET(value) (((value) << 0) & 0xffffffff)
19182 #ifndef __ASSEMBLY__
19194 struct ALT_GIC_DIST_GICD_ITARGETSR60_s
19196 volatile uint32_t fld : 32;
19200 typedef struct ALT_GIC_DIST_GICD_ITARGETSR60_s ALT_GIC_DIST_GICD_ITARGETSR60_t;
19204 #define ALT_GIC_DIST_GICD_ITARGETSR60_RESET 0x00000000
19206 #define ALT_GIC_DIST_GICD_ITARGETSR60_OFST 0x8f0
19229 #define ALT_GIC_DIST_GICD_ITARGETSR61_FLD_LSB 0
19231 #define ALT_GIC_DIST_GICD_ITARGETSR61_FLD_MSB 31
19233 #define ALT_GIC_DIST_GICD_ITARGETSR61_FLD_WIDTH 32
19235 #define ALT_GIC_DIST_GICD_ITARGETSR61_FLD_SET_MSK 0xffffffff
19237 #define ALT_GIC_DIST_GICD_ITARGETSR61_FLD_CLR_MSK 0x00000000
19239 #define ALT_GIC_DIST_GICD_ITARGETSR61_FLD_RESET 0x0
19241 #define ALT_GIC_DIST_GICD_ITARGETSR61_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19243 #define ALT_GIC_DIST_GICD_ITARGETSR61_FLD_SET(value) (((value) << 0) & 0xffffffff)
19245 #ifndef __ASSEMBLY__
19257 struct ALT_GIC_DIST_GICD_ITARGETSR61_s
19259 volatile uint32_t fld : 32;
19263 typedef struct ALT_GIC_DIST_GICD_ITARGETSR61_s ALT_GIC_DIST_GICD_ITARGETSR61_t;
19267 #define ALT_GIC_DIST_GICD_ITARGETSR61_RESET 0x00000000
19269 #define ALT_GIC_DIST_GICD_ITARGETSR61_OFST 0x8f4
19292 #define ALT_GIC_DIST_GICD_ITARGETSR62_FLD_LSB 0
19294 #define ALT_GIC_DIST_GICD_ITARGETSR62_FLD_MSB 31
19296 #define ALT_GIC_DIST_GICD_ITARGETSR62_FLD_WIDTH 32
19298 #define ALT_GIC_DIST_GICD_ITARGETSR62_FLD_SET_MSK 0xffffffff
19300 #define ALT_GIC_DIST_GICD_ITARGETSR62_FLD_CLR_MSK 0x00000000
19302 #define ALT_GIC_DIST_GICD_ITARGETSR62_FLD_RESET 0x0
19304 #define ALT_GIC_DIST_GICD_ITARGETSR62_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19306 #define ALT_GIC_DIST_GICD_ITARGETSR62_FLD_SET(value) (((value) << 0) & 0xffffffff)
19308 #ifndef __ASSEMBLY__
19320 struct ALT_GIC_DIST_GICD_ITARGETSR62_s
19322 volatile uint32_t fld : 32;
19326 typedef struct ALT_GIC_DIST_GICD_ITARGETSR62_s ALT_GIC_DIST_GICD_ITARGETSR62_t;
19330 #define ALT_GIC_DIST_GICD_ITARGETSR62_RESET 0x00000000
19332 #define ALT_GIC_DIST_GICD_ITARGETSR62_OFST 0x8f8
19355 #define ALT_GIC_DIST_GICD_ITARGETSR63_FLD_LSB 0
19357 #define ALT_GIC_DIST_GICD_ITARGETSR63_FLD_MSB 31
19359 #define ALT_GIC_DIST_GICD_ITARGETSR63_FLD_WIDTH 32
19361 #define ALT_GIC_DIST_GICD_ITARGETSR63_FLD_SET_MSK 0xffffffff
19363 #define ALT_GIC_DIST_GICD_ITARGETSR63_FLD_CLR_MSK 0x00000000
19365 #define ALT_GIC_DIST_GICD_ITARGETSR63_FLD_RESET 0x0
19367 #define ALT_GIC_DIST_GICD_ITARGETSR63_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19369 #define ALT_GIC_DIST_GICD_ITARGETSR63_FLD_SET(value) (((value) << 0) & 0xffffffff)
19371 #ifndef __ASSEMBLY__
19383 struct ALT_GIC_DIST_GICD_ITARGETSR63_s
19385 volatile uint32_t fld : 32;
19389 typedef struct ALT_GIC_DIST_GICD_ITARGETSR63_s ALT_GIC_DIST_GICD_ITARGETSR63_t;
19393 #define ALT_GIC_DIST_GICD_ITARGETSR63_RESET 0x00000000
19395 #define ALT_GIC_DIST_GICD_ITARGETSR63_OFST 0x8fc
19418 #define ALT_GIC_DIST_GICD_ITARGETSR64_FLD_LSB 0
19420 #define ALT_GIC_DIST_GICD_ITARGETSR64_FLD_MSB 31
19422 #define ALT_GIC_DIST_GICD_ITARGETSR64_FLD_WIDTH 32
19424 #define ALT_GIC_DIST_GICD_ITARGETSR64_FLD_SET_MSK 0xffffffff
19426 #define ALT_GIC_DIST_GICD_ITARGETSR64_FLD_CLR_MSK 0x00000000
19428 #define ALT_GIC_DIST_GICD_ITARGETSR64_FLD_RESET 0x0
19430 #define ALT_GIC_DIST_GICD_ITARGETSR64_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19432 #define ALT_GIC_DIST_GICD_ITARGETSR64_FLD_SET(value) (((value) << 0) & 0xffffffff)
19434 #ifndef __ASSEMBLY__
19446 struct ALT_GIC_DIST_GICD_ITARGETSR64_s
19448 volatile uint32_t fld : 32;
19452 typedef struct ALT_GIC_DIST_GICD_ITARGETSR64_s ALT_GIC_DIST_GICD_ITARGETSR64_t;
19456 #define ALT_GIC_DIST_GICD_ITARGETSR64_RESET 0x00000000
19458 #define ALT_GIC_DIST_GICD_ITARGETSR64_OFST 0x900
19481 #define ALT_GIC_DIST_GICD_ITARGETSR65_FLD_LSB 0
19483 #define ALT_GIC_DIST_GICD_ITARGETSR65_FLD_MSB 31
19485 #define ALT_GIC_DIST_GICD_ITARGETSR65_FLD_WIDTH 32
19487 #define ALT_GIC_DIST_GICD_ITARGETSR65_FLD_SET_MSK 0xffffffff
19489 #define ALT_GIC_DIST_GICD_ITARGETSR65_FLD_CLR_MSK 0x00000000
19491 #define ALT_GIC_DIST_GICD_ITARGETSR65_FLD_RESET 0x0
19493 #define ALT_GIC_DIST_GICD_ITARGETSR65_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19495 #define ALT_GIC_DIST_GICD_ITARGETSR65_FLD_SET(value) (((value) << 0) & 0xffffffff)
19497 #ifndef __ASSEMBLY__
19509 struct ALT_GIC_DIST_GICD_ITARGETSR65_s
19511 volatile uint32_t fld : 32;
19515 typedef struct ALT_GIC_DIST_GICD_ITARGETSR65_s ALT_GIC_DIST_GICD_ITARGETSR65_t;
19519 #define ALT_GIC_DIST_GICD_ITARGETSR65_RESET 0x00000000
19521 #define ALT_GIC_DIST_GICD_ITARGETSR65_OFST 0x904
19544 #define ALT_GIC_DIST_GICD_ITARGETSR66_FLD_LSB 0
19546 #define ALT_GIC_DIST_GICD_ITARGETSR66_FLD_MSB 31
19548 #define ALT_GIC_DIST_GICD_ITARGETSR66_FLD_WIDTH 32
19550 #define ALT_GIC_DIST_GICD_ITARGETSR66_FLD_SET_MSK 0xffffffff
19552 #define ALT_GIC_DIST_GICD_ITARGETSR66_FLD_CLR_MSK 0x00000000
19554 #define ALT_GIC_DIST_GICD_ITARGETSR66_FLD_RESET 0x0
19556 #define ALT_GIC_DIST_GICD_ITARGETSR66_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19558 #define ALT_GIC_DIST_GICD_ITARGETSR66_FLD_SET(value) (((value) << 0) & 0xffffffff)
19560 #ifndef __ASSEMBLY__
19572 struct ALT_GIC_DIST_GICD_ITARGETSR66_s
19574 volatile uint32_t fld : 32;
19578 typedef struct ALT_GIC_DIST_GICD_ITARGETSR66_s ALT_GIC_DIST_GICD_ITARGETSR66_t;
19582 #define ALT_GIC_DIST_GICD_ITARGETSR66_RESET 0x00000000
19584 #define ALT_GIC_DIST_GICD_ITARGETSR66_OFST 0x908
19607 #define ALT_GIC_DIST_GICD_ITARGETSR67_FLD_LSB 0
19609 #define ALT_GIC_DIST_GICD_ITARGETSR67_FLD_MSB 31
19611 #define ALT_GIC_DIST_GICD_ITARGETSR67_FLD_WIDTH 32
19613 #define ALT_GIC_DIST_GICD_ITARGETSR67_FLD_SET_MSK 0xffffffff
19615 #define ALT_GIC_DIST_GICD_ITARGETSR67_FLD_CLR_MSK 0x00000000
19617 #define ALT_GIC_DIST_GICD_ITARGETSR67_FLD_RESET 0x0
19619 #define ALT_GIC_DIST_GICD_ITARGETSR67_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19621 #define ALT_GIC_DIST_GICD_ITARGETSR67_FLD_SET(value) (((value) << 0) & 0xffffffff)
19623 #ifndef __ASSEMBLY__
19635 struct ALT_GIC_DIST_GICD_ITARGETSR67_s
19637 volatile uint32_t fld : 32;
19641 typedef struct ALT_GIC_DIST_GICD_ITARGETSR67_s ALT_GIC_DIST_GICD_ITARGETSR67_t;
19645 #define ALT_GIC_DIST_GICD_ITARGETSR67_RESET 0x00000000
19647 #define ALT_GIC_DIST_GICD_ITARGETSR67_OFST 0x90c
19670 #define ALT_GIC_DIST_GICD_ITARGETSR68_FLD_LSB 0
19672 #define ALT_GIC_DIST_GICD_ITARGETSR68_FLD_MSB 31
19674 #define ALT_GIC_DIST_GICD_ITARGETSR68_FLD_WIDTH 32
19676 #define ALT_GIC_DIST_GICD_ITARGETSR68_FLD_SET_MSK 0xffffffff
19678 #define ALT_GIC_DIST_GICD_ITARGETSR68_FLD_CLR_MSK 0x00000000
19680 #define ALT_GIC_DIST_GICD_ITARGETSR68_FLD_RESET 0x0
19682 #define ALT_GIC_DIST_GICD_ITARGETSR68_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19684 #define ALT_GIC_DIST_GICD_ITARGETSR68_FLD_SET(value) (((value) << 0) & 0xffffffff)
19686 #ifndef __ASSEMBLY__
19698 struct ALT_GIC_DIST_GICD_ITARGETSR68_s
19700 volatile uint32_t fld : 32;
19704 typedef struct ALT_GIC_DIST_GICD_ITARGETSR68_s ALT_GIC_DIST_GICD_ITARGETSR68_t;
19708 #define ALT_GIC_DIST_GICD_ITARGETSR68_RESET 0x00000000
19710 #define ALT_GIC_DIST_GICD_ITARGETSR68_OFST 0x910
19733 #define ALT_GIC_DIST_GICD_ITARGETSR69_FLD_LSB 0
19735 #define ALT_GIC_DIST_GICD_ITARGETSR69_FLD_MSB 31
19737 #define ALT_GIC_DIST_GICD_ITARGETSR69_FLD_WIDTH 32
19739 #define ALT_GIC_DIST_GICD_ITARGETSR69_FLD_SET_MSK 0xffffffff
19741 #define ALT_GIC_DIST_GICD_ITARGETSR69_FLD_CLR_MSK 0x00000000
19743 #define ALT_GIC_DIST_GICD_ITARGETSR69_FLD_RESET 0x0
19745 #define ALT_GIC_DIST_GICD_ITARGETSR69_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19747 #define ALT_GIC_DIST_GICD_ITARGETSR69_FLD_SET(value) (((value) << 0) & 0xffffffff)
19749 #ifndef __ASSEMBLY__
19761 struct ALT_GIC_DIST_GICD_ITARGETSR69_s
19763 volatile uint32_t fld : 32;
19767 typedef struct ALT_GIC_DIST_GICD_ITARGETSR69_s ALT_GIC_DIST_GICD_ITARGETSR69_t;
19771 #define ALT_GIC_DIST_GICD_ITARGETSR69_RESET 0x00000000
19773 #define ALT_GIC_DIST_GICD_ITARGETSR69_OFST 0x914
19796 #define ALT_GIC_DIST_GICD_ITARGETSR70_FLD_LSB 0
19798 #define ALT_GIC_DIST_GICD_ITARGETSR70_FLD_MSB 31
19800 #define ALT_GIC_DIST_GICD_ITARGETSR70_FLD_WIDTH 32
19802 #define ALT_GIC_DIST_GICD_ITARGETSR70_FLD_SET_MSK 0xffffffff
19804 #define ALT_GIC_DIST_GICD_ITARGETSR70_FLD_CLR_MSK 0x00000000
19806 #define ALT_GIC_DIST_GICD_ITARGETSR70_FLD_RESET 0x0
19808 #define ALT_GIC_DIST_GICD_ITARGETSR70_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19810 #define ALT_GIC_DIST_GICD_ITARGETSR70_FLD_SET(value) (((value) << 0) & 0xffffffff)
19812 #ifndef __ASSEMBLY__
19824 struct ALT_GIC_DIST_GICD_ITARGETSR70_s
19826 volatile uint32_t fld : 32;
19830 typedef struct ALT_GIC_DIST_GICD_ITARGETSR70_s ALT_GIC_DIST_GICD_ITARGETSR70_t;
19834 #define ALT_GIC_DIST_GICD_ITARGETSR70_RESET 0x00000000
19836 #define ALT_GIC_DIST_GICD_ITARGETSR70_OFST 0x918
19859 #define ALT_GIC_DIST_GICD_ITARGETSR71_FLD_LSB 0
19861 #define ALT_GIC_DIST_GICD_ITARGETSR71_FLD_MSB 31
19863 #define ALT_GIC_DIST_GICD_ITARGETSR71_FLD_WIDTH 32
19865 #define ALT_GIC_DIST_GICD_ITARGETSR71_FLD_SET_MSK 0xffffffff
19867 #define ALT_GIC_DIST_GICD_ITARGETSR71_FLD_CLR_MSK 0x00000000
19869 #define ALT_GIC_DIST_GICD_ITARGETSR71_FLD_RESET 0x0
19871 #define ALT_GIC_DIST_GICD_ITARGETSR71_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19873 #define ALT_GIC_DIST_GICD_ITARGETSR71_FLD_SET(value) (((value) << 0) & 0xffffffff)
19875 #ifndef __ASSEMBLY__
19887 struct ALT_GIC_DIST_GICD_ITARGETSR71_s
19889 volatile uint32_t fld : 32;
19893 typedef struct ALT_GIC_DIST_GICD_ITARGETSR71_s ALT_GIC_DIST_GICD_ITARGETSR71_t;
19897 #define ALT_GIC_DIST_GICD_ITARGETSR71_RESET 0x00000000
19899 #define ALT_GIC_DIST_GICD_ITARGETSR71_OFST 0x91c
19922 #define ALT_GIC_DIST_GICD_ITARGETSR72_FLD_LSB 0
19924 #define ALT_GIC_DIST_GICD_ITARGETSR72_FLD_MSB 31
19926 #define ALT_GIC_DIST_GICD_ITARGETSR72_FLD_WIDTH 32
19928 #define ALT_GIC_DIST_GICD_ITARGETSR72_FLD_SET_MSK 0xffffffff
19930 #define ALT_GIC_DIST_GICD_ITARGETSR72_FLD_CLR_MSK 0x00000000
19932 #define ALT_GIC_DIST_GICD_ITARGETSR72_FLD_RESET 0x0
19934 #define ALT_GIC_DIST_GICD_ITARGETSR72_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19936 #define ALT_GIC_DIST_GICD_ITARGETSR72_FLD_SET(value) (((value) << 0) & 0xffffffff)
19938 #ifndef __ASSEMBLY__
19950 struct ALT_GIC_DIST_GICD_ITARGETSR72_s
19952 volatile uint32_t fld : 32;
19956 typedef struct ALT_GIC_DIST_GICD_ITARGETSR72_s ALT_GIC_DIST_GICD_ITARGETSR72_t;
19960 #define ALT_GIC_DIST_GICD_ITARGETSR72_RESET 0x00000000
19962 #define ALT_GIC_DIST_GICD_ITARGETSR72_OFST 0x920
19985 #define ALT_GIC_DIST_GICD_ITARGETSR73_FLD_LSB 0
19987 #define ALT_GIC_DIST_GICD_ITARGETSR73_FLD_MSB 31
19989 #define ALT_GIC_DIST_GICD_ITARGETSR73_FLD_WIDTH 32
19991 #define ALT_GIC_DIST_GICD_ITARGETSR73_FLD_SET_MSK 0xffffffff
19993 #define ALT_GIC_DIST_GICD_ITARGETSR73_FLD_CLR_MSK 0x00000000
19995 #define ALT_GIC_DIST_GICD_ITARGETSR73_FLD_RESET 0x0
19997 #define ALT_GIC_DIST_GICD_ITARGETSR73_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19999 #define ALT_GIC_DIST_GICD_ITARGETSR73_FLD_SET(value) (((value) << 0) & 0xffffffff)
20001 #ifndef __ASSEMBLY__
20013 struct ALT_GIC_DIST_GICD_ITARGETSR73_s
20015 volatile uint32_t fld : 32;
20019 typedef struct ALT_GIC_DIST_GICD_ITARGETSR73_s ALT_GIC_DIST_GICD_ITARGETSR73_t;
20023 #define ALT_GIC_DIST_GICD_ITARGETSR73_RESET 0x00000000
20025 #define ALT_GIC_DIST_GICD_ITARGETSR73_OFST 0x924
20048 #define ALT_GIC_DIST_GICD_ITARGETSR74_FLD_LSB 0
20050 #define ALT_GIC_DIST_GICD_ITARGETSR74_FLD_MSB 31
20052 #define ALT_GIC_DIST_GICD_ITARGETSR74_FLD_WIDTH 32
20054 #define ALT_GIC_DIST_GICD_ITARGETSR74_FLD_SET_MSK 0xffffffff
20056 #define ALT_GIC_DIST_GICD_ITARGETSR74_FLD_CLR_MSK 0x00000000
20058 #define ALT_GIC_DIST_GICD_ITARGETSR74_FLD_RESET 0x0
20060 #define ALT_GIC_DIST_GICD_ITARGETSR74_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20062 #define ALT_GIC_DIST_GICD_ITARGETSR74_FLD_SET(value) (((value) << 0) & 0xffffffff)
20064 #ifndef __ASSEMBLY__
20076 struct ALT_GIC_DIST_GICD_ITARGETSR74_s
20078 volatile uint32_t fld : 32;
20082 typedef struct ALT_GIC_DIST_GICD_ITARGETSR74_s ALT_GIC_DIST_GICD_ITARGETSR74_t;
20086 #define ALT_GIC_DIST_GICD_ITARGETSR74_RESET 0x00000000
20088 #define ALT_GIC_DIST_GICD_ITARGETSR74_OFST 0x928
20111 #define ALT_GIC_DIST_GICD_ITARGETSR75_FLD_LSB 0
20113 #define ALT_GIC_DIST_GICD_ITARGETSR75_FLD_MSB 31
20115 #define ALT_GIC_DIST_GICD_ITARGETSR75_FLD_WIDTH 32
20117 #define ALT_GIC_DIST_GICD_ITARGETSR75_FLD_SET_MSK 0xffffffff
20119 #define ALT_GIC_DIST_GICD_ITARGETSR75_FLD_CLR_MSK 0x00000000
20121 #define ALT_GIC_DIST_GICD_ITARGETSR75_FLD_RESET 0x0
20123 #define ALT_GIC_DIST_GICD_ITARGETSR75_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20125 #define ALT_GIC_DIST_GICD_ITARGETSR75_FLD_SET(value) (((value) << 0) & 0xffffffff)
20127 #ifndef __ASSEMBLY__
20139 struct ALT_GIC_DIST_GICD_ITARGETSR75_s
20141 volatile uint32_t fld : 32;
20145 typedef struct ALT_GIC_DIST_GICD_ITARGETSR75_s ALT_GIC_DIST_GICD_ITARGETSR75_t;
20149 #define ALT_GIC_DIST_GICD_ITARGETSR75_RESET 0x00000000
20151 #define ALT_GIC_DIST_GICD_ITARGETSR75_OFST 0x92c
20174 #define ALT_GIC_DIST_GICD_ITARGETSR76_FLD_LSB 0
20176 #define ALT_GIC_DIST_GICD_ITARGETSR76_FLD_MSB 31
20178 #define ALT_GIC_DIST_GICD_ITARGETSR76_FLD_WIDTH 32
20180 #define ALT_GIC_DIST_GICD_ITARGETSR76_FLD_SET_MSK 0xffffffff
20182 #define ALT_GIC_DIST_GICD_ITARGETSR76_FLD_CLR_MSK 0x00000000
20184 #define ALT_GIC_DIST_GICD_ITARGETSR76_FLD_RESET 0x0
20186 #define ALT_GIC_DIST_GICD_ITARGETSR76_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20188 #define ALT_GIC_DIST_GICD_ITARGETSR76_FLD_SET(value) (((value) << 0) & 0xffffffff)
20190 #ifndef __ASSEMBLY__
20202 struct ALT_GIC_DIST_GICD_ITARGETSR76_s
20204 volatile uint32_t fld : 32;
20208 typedef struct ALT_GIC_DIST_GICD_ITARGETSR76_s ALT_GIC_DIST_GICD_ITARGETSR76_t;
20212 #define ALT_GIC_DIST_GICD_ITARGETSR76_RESET 0x00000000
20214 #define ALT_GIC_DIST_GICD_ITARGETSR76_OFST 0x930
20237 #define ALT_GIC_DIST_GICD_ITARGETSR77_FLD_LSB 0
20239 #define ALT_GIC_DIST_GICD_ITARGETSR77_FLD_MSB 31
20241 #define ALT_GIC_DIST_GICD_ITARGETSR77_FLD_WIDTH 32
20243 #define ALT_GIC_DIST_GICD_ITARGETSR77_FLD_SET_MSK 0xffffffff
20245 #define ALT_GIC_DIST_GICD_ITARGETSR77_FLD_CLR_MSK 0x00000000
20247 #define ALT_GIC_DIST_GICD_ITARGETSR77_FLD_RESET 0x0
20249 #define ALT_GIC_DIST_GICD_ITARGETSR77_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20251 #define ALT_GIC_DIST_GICD_ITARGETSR77_FLD_SET(value) (((value) << 0) & 0xffffffff)
20253 #ifndef __ASSEMBLY__
20265 struct ALT_GIC_DIST_GICD_ITARGETSR77_s
20267 volatile uint32_t fld : 32;
20271 typedef struct ALT_GIC_DIST_GICD_ITARGETSR77_s ALT_GIC_DIST_GICD_ITARGETSR77_t;
20275 #define ALT_GIC_DIST_GICD_ITARGETSR77_RESET 0x00000000
20277 #define ALT_GIC_DIST_GICD_ITARGETSR77_OFST 0x934
20300 #define ALT_GIC_DIST_GICD_ITARGETSR78_FLD_LSB 0
20302 #define ALT_GIC_DIST_GICD_ITARGETSR78_FLD_MSB 31
20304 #define ALT_GIC_DIST_GICD_ITARGETSR78_FLD_WIDTH 32
20306 #define ALT_GIC_DIST_GICD_ITARGETSR78_FLD_SET_MSK 0xffffffff
20308 #define ALT_GIC_DIST_GICD_ITARGETSR78_FLD_CLR_MSK 0x00000000
20310 #define ALT_GIC_DIST_GICD_ITARGETSR78_FLD_RESET 0x0
20312 #define ALT_GIC_DIST_GICD_ITARGETSR78_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20314 #define ALT_GIC_DIST_GICD_ITARGETSR78_FLD_SET(value) (((value) << 0) & 0xffffffff)
20316 #ifndef __ASSEMBLY__
20328 struct ALT_GIC_DIST_GICD_ITARGETSR78_s
20330 volatile uint32_t fld : 32;
20334 typedef struct ALT_GIC_DIST_GICD_ITARGETSR78_s ALT_GIC_DIST_GICD_ITARGETSR78_t;
20338 #define ALT_GIC_DIST_GICD_ITARGETSR78_RESET 0x00000000
20340 #define ALT_GIC_DIST_GICD_ITARGETSR78_OFST 0x938
20363 #define ALT_GIC_DIST_GICD_ITARGETSR79_FLD_LSB 0
20365 #define ALT_GIC_DIST_GICD_ITARGETSR79_FLD_MSB 31
20367 #define ALT_GIC_DIST_GICD_ITARGETSR79_FLD_WIDTH 32
20369 #define ALT_GIC_DIST_GICD_ITARGETSR79_FLD_SET_MSK 0xffffffff
20371 #define ALT_GIC_DIST_GICD_ITARGETSR79_FLD_CLR_MSK 0x00000000
20373 #define ALT_GIC_DIST_GICD_ITARGETSR79_FLD_RESET 0x0
20375 #define ALT_GIC_DIST_GICD_ITARGETSR79_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20377 #define ALT_GIC_DIST_GICD_ITARGETSR79_FLD_SET(value) (((value) << 0) & 0xffffffff)
20379 #ifndef __ASSEMBLY__
20391 struct ALT_GIC_DIST_GICD_ITARGETSR79_s
20393 volatile uint32_t fld : 32;
20397 typedef struct ALT_GIC_DIST_GICD_ITARGETSR79_s ALT_GIC_DIST_GICD_ITARGETSR79_t;
20401 #define ALT_GIC_DIST_GICD_ITARGETSR79_RESET 0x00000000
20403 #define ALT_GIC_DIST_GICD_ITARGETSR79_OFST 0x93c
20426 #define ALT_GIC_DIST_GICD_ITARGETSR80_FLD_LSB 0
20428 #define ALT_GIC_DIST_GICD_ITARGETSR80_FLD_MSB 31
20430 #define ALT_GIC_DIST_GICD_ITARGETSR80_FLD_WIDTH 32
20432 #define ALT_GIC_DIST_GICD_ITARGETSR80_FLD_SET_MSK 0xffffffff
20434 #define ALT_GIC_DIST_GICD_ITARGETSR80_FLD_CLR_MSK 0x00000000
20436 #define ALT_GIC_DIST_GICD_ITARGETSR80_FLD_RESET 0x0
20438 #define ALT_GIC_DIST_GICD_ITARGETSR80_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20440 #define ALT_GIC_DIST_GICD_ITARGETSR80_FLD_SET(value) (((value) << 0) & 0xffffffff)
20442 #ifndef __ASSEMBLY__
20454 struct ALT_GIC_DIST_GICD_ITARGETSR80_s
20456 volatile uint32_t fld : 32;
20460 typedef struct ALT_GIC_DIST_GICD_ITARGETSR80_s ALT_GIC_DIST_GICD_ITARGETSR80_t;
20464 #define ALT_GIC_DIST_GICD_ITARGETSR80_RESET 0x00000000
20466 #define ALT_GIC_DIST_GICD_ITARGETSR80_OFST 0x940
20489 #define ALT_GIC_DIST_GICD_ITARGETSR81_FLD_LSB 0
20491 #define ALT_GIC_DIST_GICD_ITARGETSR81_FLD_MSB 31
20493 #define ALT_GIC_DIST_GICD_ITARGETSR81_FLD_WIDTH 32
20495 #define ALT_GIC_DIST_GICD_ITARGETSR81_FLD_SET_MSK 0xffffffff
20497 #define ALT_GIC_DIST_GICD_ITARGETSR81_FLD_CLR_MSK 0x00000000
20499 #define ALT_GIC_DIST_GICD_ITARGETSR81_FLD_RESET 0x0
20501 #define ALT_GIC_DIST_GICD_ITARGETSR81_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20503 #define ALT_GIC_DIST_GICD_ITARGETSR81_FLD_SET(value) (((value) << 0) & 0xffffffff)
20505 #ifndef __ASSEMBLY__
20517 struct ALT_GIC_DIST_GICD_ITARGETSR81_s
20519 volatile uint32_t fld : 32;
20523 typedef struct ALT_GIC_DIST_GICD_ITARGETSR81_s ALT_GIC_DIST_GICD_ITARGETSR81_t;
20527 #define ALT_GIC_DIST_GICD_ITARGETSR81_RESET 0x00000000
20529 #define ALT_GIC_DIST_GICD_ITARGETSR81_OFST 0x944
20552 #define ALT_GIC_DIST_GICD_ITARGETSR82_FLD_LSB 0
20554 #define ALT_GIC_DIST_GICD_ITARGETSR82_FLD_MSB 31
20556 #define ALT_GIC_DIST_GICD_ITARGETSR82_FLD_WIDTH 32
20558 #define ALT_GIC_DIST_GICD_ITARGETSR82_FLD_SET_MSK 0xffffffff
20560 #define ALT_GIC_DIST_GICD_ITARGETSR82_FLD_CLR_MSK 0x00000000
20562 #define ALT_GIC_DIST_GICD_ITARGETSR82_FLD_RESET 0x0
20564 #define ALT_GIC_DIST_GICD_ITARGETSR82_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20566 #define ALT_GIC_DIST_GICD_ITARGETSR82_FLD_SET(value) (((value) << 0) & 0xffffffff)
20568 #ifndef __ASSEMBLY__
20580 struct ALT_GIC_DIST_GICD_ITARGETSR82_s
20582 volatile uint32_t fld : 32;
20586 typedef struct ALT_GIC_DIST_GICD_ITARGETSR82_s ALT_GIC_DIST_GICD_ITARGETSR82_t;
20590 #define ALT_GIC_DIST_GICD_ITARGETSR82_RESET 0x00000000
20592 #define ALT_GIC_DIST_GICD_ITARGETSR82_OFST 0x948
20615 #define ALT_GIC_DIST_GICD_ITARGETSR83_FLD_LSB 0
20617 #define ALT_GIC_DIST_GICD_ITARGETSR83_FLD_MSB 31
20619 #define ALT_GIC_DIST_GICD_ITARGETSR83_FLD_WIDTH 32
20621 #define ALT_GIC_DIST_GICD_ITARGETSR83_FLD_SET_MSK 0xffffffff
20623 #define ALT_GIC_DIST_GICD_ITARGETSR83_FLD_CLR_MSK 0x00000000
20625 #define ALT_GIC_DIST_GICD_ITARGETSR83_FLD_RESET 0x0
20627 #define ALT_GIC_DIST_GICD_ITARGETSR83_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20629 #define ALT_GIC_DIST_GICD_ITARGETSR83_FLD_SET(value) (((value) << 0) & 0xffffffff)
20631 #ifndef __ASSEMBLY__
20643 struct ALT_GIC_DIST_GICD_ITARGETSR83_s
20645 volatile uint32_t fld : 32;
20649 typedef struct ALT_GIC_DIST_GICD_ITARGETSR83_s ALT_GIC_DIST_GICD_ITARGETSR83_t;
20653 #define ALT_GIC_DIST_GICD_ITARGETSR83_RESET 0x00000000
20655 #define ALT_GIC_DIST_GICD_ITARGETSR83_OFST 0x94c
20678 #define ALT_GIC_DIST_GICD_ITARGETSR84_FLD_LSB 0
20680 #define ALT_GIC_DIST_GICD_ITARGETSR84_FLD_MSB 31
20682 #define ALT_GIC_DIST_GICD_ITARGETSR84_FLD_WIDTH 32
20684 #define ALT_GIC_DIST_GICD_ITARGETSR84_FLD_SET_MSK 0xffffffff
20686 #define ALT_GIC_DIST_GICD_ITARGETSR84_FLD_CLR_MSK 0x00000000
20688 #define ALT_GIC_DIST_GICD_ITARGETSR84_FLD_RESET 0x0
20690 #define ALT_GIC_DIST_GICD_ITARGETSR84_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20692 #define ALT_GIC_DIST_GICD_ITARGETSR84_FLD_SET(value) (((value) << 0) & 0xffffffff)
20694 #ifndef __ASSEMBLY__
20706 struct ALT_GIC_DIST_GICD_ITARGETSR84_s
20708 volatile uint32_t fld : 32;
20712 typedef struct ALT_GIC_DIST_GICD_ITARGETSR84_s ALT_GIC_DIST_GICD_ITARGETSR84_t;
20716 #define ALT_GIC_DIST_GICD_ITARGETSR84_RESET 0x00000000
20718 #define ALT_GIC_DIST_GICD_ITARGETSR84_OFST 0x950
20741 #define ALT_GIC_DIST_GICD_ITARGETSR85_FLD_LSB 0
20743 #define ALT_GIC_DIST_GICD_ITARGETSR85_FLD_MSB 31
20745 #define ALT_GIC_DIST_GICD_ITARGETSR85_FLD_WIDTH 32
20747 #define ALT_GIC_DIST_GICD_ITARGETSR85_FLD_SET_MSK 0xffffffff
20749 #define ALT_GIC_DIST_GICD_ITARGETSR85_FLD_CLR_MSK 0x00000000
20751 #define ALT_GIC_DIST_GICD_ITARGETSR85_FLD_RESET 0x0
20753 #define ALT_GIC_DIST_GICD_ITARGETSR85_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20755 #define ALT_GIC_DIST_GICD_ITARGETSR85_FLD_SET(value) (((value) << 0) & 0xffffffff)
20757 #ifndef __ASSEMBLY__
20769 struct ALT_GIC_DIST_GICD_ITARGETSR85_s
20771 volatile uint32_t fld : 32;
20775 typedef struct ALT_GIC_DIST_GICD_ITARGETSR85_s ALT_GIC_DIST_GICD_ITARGETSR85_t;
20779 #define ALT_GIC_DIST_GICD_ITARGETSR85_RESET 0x00000000
20781 #define ALT_GIC_DIST_GICD_ITARGETSR85_OFST 0x954
20804 #define ALT_GIC_DIST_GICD_ITARGETSR86_FLD_LSB 0
20806 #define ALT_GIC_DIST_GICD_ITARGETSR86_FLD_MSB 31
20808 #define ALT_GIC_DIST_GICD_ITARGETSR86_FLD_WIDTH 32
20810 #define ALT_GIC_DIST_GICD_ITARGETSR86_FLD_SET_MSK 0xffffffff
20812 #define ALT_GIC_DIST_GICD_ITARGETSR86_FLD_CLR_MSK 0x00000000
20814 #define ALT_GIC_DIST_GICD_ITARGETSR86_FLD_RESET 0x0
20816 #define ALT_GIC_DIST_GICD_ITARGETSR86_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20818 #define ALT_GIC_DIST_GICD_ITARGETSR86_FLD_SET(value) (((value) << 0) & 0xffffffff)
20820 #ifndef __ASSEMBLY__
20832 struct ALT_GIC_DIST_GICD_ITARGETSR86_s
20834 volatile uint32_t fld : 32;
20838 typedef struct ALT_GIC_DIST_GICD_ITARGETSR86_s ALT_GIC_DIST_GICD_ITARGETSR86_t;
20842 #define ALT_GIC_DIST_GICD_ITARGETSR86_RESET 0x00000000
20844 #define ALT_GIC_DIST_GICD_ITARGETSR86_OFST 0x958
20867 #define ALT_GIC_DIST_GICD_ITARGETSR87_FLD_LSB 0
20869 #define ALT_GIC_DIST_GICD_ITARGETSR87_FLD_MSB 31
20871 #define ALT_GIC_DIST_GICD_ITARGETSR87_FLD_WIDTH 32
20873 #define ALT_GIC_DIST_GICD_ITARGETSR87_FLD_SET_MSK 0xffffffff
20875 #define ALT_GIC_DIST_GICD_ITARGETSR87_FLD_CLR_MSK 0x00000000
20877 #define ALT_GIC_DIST_GICD_ITARGETSR87_FLD_RESET 0x0
20879 #define ALT_GIC_DIST_GICD_ITARGETSR87_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20881 #define ALT_GIC_DIST_GICD_ITARGETSR87_FLD_SET(value) (((value) << 0) & 0xffffffff)
20883 #ifndef __ASSEMBLY__
20895 struct ALT_GIC_DIST_GICD_ITARGETSR87_s
20897 volatile uint32_t fld : 32;
20901 typedef struct ALT_GIC_DIST_GICD_ITARGETSR87_s ALT_GIC_DIST_GICD_ITARGETSR87_t;
20905 #define ALT_GIC_DIST_GICD_ITARGETSR87_RESET 0x00000000
20907 #define ALT_GIC_DIST_GICD_ITARGETSR87_OFST 0x95c
20930 #define ALT_GIC_DIST_GICD_ITARGETSR88_FLD_LSB 0
20932 #define ALT_GIC_DIST_GICD_ITARGETSR88_FLD_MSB 31
20934 #define ALT_GIC_DIST_GICD_ITARGETSR88_FLD_WIDTH 32
20936 #define ALT_GIC_DIST_GICD_ITARGETSR88_FLD_SET_MSK 0xffffffff
20938 #define ALT_GIC_DIST_GICD_ITARGETSR88_FLD_CLR_MSK 0x00000000
20940 #define ALT_GIC_DIST_GICD_ITARGETSR88_FLD_RESET 0x0
20942 #define ALT_GIC_DIST_GICD_ITARGETSR88_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20944 #define ALT_GIC_DIST_GICD_ITARGETSR88_FLD_SET(value) (((value) << 0) & 0xffffffff)
20946 #ifndef __ASSEMBLY__
20958 struct ALT_GIC_DIST_GICD_ITARGETSR88_s
20960 volatile uint32_t fld : 32;
20964 typedef struct ALT_GIC_DIST_GICD_ITARGETSR88_s ALT_GIC_DIST_GICD_ITARGETSR88_t;
20968 #define ALT_GIC_DIST_GICD_ITARGETSR88_RESET 0x00000000
20970 #define ALT_GIC_DIST_GICD_ITARGETSR88_OFST 0x960
20993 #define ALT_GIC_DIST_GICD_ITARGETSR89_FLD_LSB 0
20995 #define ALT_GIC_DIST_GICD_ITARGETSR89_FLD_MSB 31
20997 #define ALT_GIC_DIST_GICD_ITARGETSR89_FLD_WIDTH 32
20999 #define ALT_GIC_DIST_GICD_ITARGETSR89_FLD_SET_MSK 0xffffffff
21001 #define ALT_GIC_DIST_GICD_ITARGETSR89_FLD_CLR_MSK 0x00000000
21003 #define ALT_GIC_DIST_GICD_ITARGETSR89_FLD_RESET 0x0
21005 #define ALT_GIC_DIST_GICD_ITARGETSR89_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21007 #define ALT_GIC_DIST_GICD_ITARGETSR89_FLD_SET(value) (((value) << 0) & 0xffffffff)
21009 #ifndef __ASSEMBLY__
21021 struct ALT_GIC_DIST_GICD_ITARGETSR89_s
21023 volatile uint32_t fld : 32;
21027 typedef struct ALT_GIC_DIST_GICD_ITARGETSR89_s ALT_GIC_DIST_GICD_ITARGETSR89_t;
21031 #define ALT_GIC_DIST_GICD_ITARGETSR89_RESET 0x00000000
21033 #define ALT_GIC_DIST_GICD_ITARGETSR89_OFST 0x964
21056 #define ALT_GIC_DIST_GICD_ITARGETSR90_FLD_LSB 0
21058 #define ALT_GIC_DIST_GICD_ITARGETSR90_FLD_MSB 31
21060 #define ALT_GIC_DIST_GICD_ITARGETSR90_FLD_WIDTH 32
21062 #define ALT_GIC_DIST_GICD_ITARGETSR90_FLD_SET_MSK 0xffffffff
21064 #define ALT_GIC_DIST_GICD_ITARGETSR90_FLD_CLR_MSK 0x00000000
21066 #define ALT_GIC_DIST_GICD_ITARGETSR90_FLD_RESET 0x0
21068 #define ALT_GIC_DIST_GICD_ITARGETSR90_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21070 #define ALT_GIC_DIST_GICD_ITARGETSR90_FLD_SET(value) (((value) << 0) & 0xffffffff)
21072 #ifndef __ASSEMBLY__
21084 struct ALT_GIC_DIST_GICD_ITARGETSR90_s
21086 volatile uint32_t fld : 32;
21090 typedef struct ALT_GIC_DIST_GICD_ITARGETSR90_s ALT_GIC_DIST_GICD_ITARGETSR90_t;
21094 #define ALT_GIC_DIST_GICD_ITARGETSR90_RESET 0x00000000
21096 #define ALT_GIC_DIST_GICD_ITARGETSR90_OFST 0x968
21119 #define ALT_GIC_DIST_GICD_ITARGETSR91_FLD_LSB 0
21121 #define ALT_GIC_DIST_GICD_ITARGETSR91_FLD_MSB 31
21123 #define ALT_GIC_DIST_GICD_ITARGETSR91_FLD_WIDTH 32
21125 #define ALT_GIC_DIST_GICD_ITARGETSR91_FLD_SET_MSK 0xffffffff
21127 #define ALT_GIC_DIST_GICD_ITARGETSR91_FLD_CLR_MSK 0x00000000
21129 #define ALT_GIC_DIST_GICD_ITARGETSR91_FLD_RESET 0x0
21131 #define ALT_GIC_DIST_GICD_ITARGETSR91_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21133 #define ALT_GIC_DIST_GICD_ITARGETSR91_FLD_SET(value) (((value) << 0) & 0xffffffff)
21135 #ifndef __ASSEMBLY__
21147 struct ALT_GIC_DIST_GICD_ITARGETSR91_s
21149 volatile uint32_t fld : 32;
21153 typedef struct ALT_GIC_DIST_GICD_ITARGETSR91_s ALT_GIC_DIST_GICD_ITARGETSR91_t;
21157 #define ALT_GIC_DIST_GICD_ITARGETSR91_RESET 0x00000000
21159 #define ALT_GIC_DIST_GICD_ITARGETSR91_OFST 0x96c
21182 #define ALT_GIC_DIST_GICD_ITARGETSR92_FLD_LSB 0
21184 #define ALT_GIC_DIST_GICD_ITARGETSR92_FLD_MSB 31
21186 #define ALT_GIC_DIST_GICD_ITARGETSR92_FLD_WIDTH 32
21188 #define ALT_GIC_DIST_GICD_ITARGETSR92_FLD_SET_MSK 0xffffffff
21190 #define ALT_GIC_DIST_GICD_ITARGETSR92_FLD_CLR_MSK 0x00000000
21192 #define ALT_GIC_DIST_GICD_ITARGETSR92_FLD_RESET 0x0
21194 #define ALT_GIC_DIST_GICD_ITARGETSR92_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21196 #define ALT_GIC_DIST_GICD_ITARGETSR92_FLD_SET(value) (((value) << 0) & 0xffffffff)
21198 #ifndef __ASSEMBLY__
21210 struct ALT_GIC_DIST_GICD_ITARGETSR92_s
21212 volatile uint32_t fld : 32;
21216 typedef struct ALT_GIC_DIST_GICD_ITARGETSR92_s ALT_GIC_DIST_GICD_ITARGETSR92_t;
21220 #define ALT_GIC_DIST_GICD_ITARGETSR92_RESET 0x00000000
21222 #define ALT_GIC_DIST_GICD_ITARGETSR92_OFST 0x970
21245 #define ALT_GIC_DIST_GICD_ITARGETSR93_FLD_LSB 0
21247 #define ALT_GIC_DIST_GICD_ITARGETSR93_FLD_MSB 31
21249 #define ALT_GIC_DIST_GICD_ITARGETSR93_FLD_WIDTH 32
21251 #define ALT_GIC_DIST_GICD_ITARGETSR93_FLD_SET_MSK 0xffffffff
21253 #define ALT_GIC_DIST_GICD_ITARGETSR93_FLD_CLR_MSK 0x00000000
21255 #define ALT_GIC_DIST_GICD_ITARGETSR93_FLD_RESET 0x0
21257 #define ALT_GIC_DIST_GICD_ITARGETSR93_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21259 #define ALT_GIC_DIST_GICD_ITARGETSR93_FLD_SET(value) (((value) << 0) & 0xffffffff)
21261 #ifndef __ASSEMBLY__
21273 struct ALT_GIC_DIST_GICD_ITARGETSR93_s
21275 volatile uint32_t fld : 32;
21279 typedef struct ALT_GIC_DIST_GICD_ITARGETSR93_s ALT_GIC_DIST_GICD_ITARGETSR93_t;
21283 #define ALT_GIC_DIST_GICD_ITARGETSR93_RESET 0x00000000
21285 #define ALT_GIC_DIST_GICD_ITARGETSR93_OFST 0x974
21308 #define ALT_GIC_DIST_GICD_ITARGETSR94_FLD_LSB 0
21310 #define ALT_GIC_DIST_GICD_ITARGETSR94_FLD_MSB 31
21312 #define ALT_GIC_DIST_GICD_ITARGETSR94_FLD_WIDTH 32
21314 #define ALT_GIC_DIST_GICD_ITARGETSR94_FLD_SET_MSK 0xffffffff
21316 #define ALT_GIC_DIST_GICD_ITARGETSR94_FLD_CLR_MSK 0x00000000
21318 #define ALT_GIC_DIST_GICD_ITARGETSR94_FLD_RESET 0x0
21320 #define ALT_GIC_DIST_GICD_ITARGETSR94_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21322 #define ALT_GIC_DIST_GICD_ITARGETSR94_FLD_SET(value) (((value) << 0) & 0xffffffff)
21324 #ifndef __ASSEMBLY__
21336 struct ALT_GIC_DIST_GICD_ITARGETSR94_s
21338 volatile uint32_t fld : 32;
21342 typedef struct ALT_GIC_DIST_GICD_ITARGETSR94_s ALT_GIC_DIST_GICD_ITARGETSR94_t;
21346 #define ALT_GIC_DIST_GICD_ITARGETSR94_RESET 0x00000000
21348 #define ALT_GIC_DIST_GICD_ITARGETSR94_OFST 0x978
21371 #define ALT_GIC_DIST_GICD_ITARGETSR95_FLD_LSB 0
21373 #define ALT_GIC_DIST_GICD_ITARGETSR95_FLD_MSB 31
21375 #define ALT_GIC_DIST_GICD_ITARGETSR95_FLD_WIDTH 32
21377 #define ALT_GIC_DIST_GICD_ITARGETSR95_FLD_SET_MSK 0xffffffff
21379 #define ALT_GIC_DIST_GICD_ITARGETSR95_FLD_CLR_MSK 0x00000000
21381 #define ALT_GIC_DIST_GICD_ITARGETSR95_FLD_RESET 0x0
21383 #define ALT_GIC_DIST_GICD_ITARGETSR95_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21385 #define ALT_GIC_DIST_GICD_ITARGETSR95_FLD_SET(value) (((value) << 0) & 0xffffffff)
21387 #ifndef __ASSEMBLY__
21399 struct ALT_GIC_DIST_GICD_ITARGETSR95_s
21401 volatile uint32_t fld : 32;
21405 typedef struct ALT_GIC_DIST_GICD_ITARGETSR95_s ALT_GIC_DIST_GICD_ITARGETSR95_t;
21409 #define ALT_GIC_DIST_GICD_ITARGETSR95_RESET 0x00000000
21411 #define ALT_GIC_DIST_GICD_ITARGETSR95_OFST 0x97c
21434 #define ALT_GIC_DIST_GICD_ITARGETSR96_FLD_LSB 0
21436 #define ALT_GIC_DIST_GICD_ITARGETSR96_FLD_MSB 31
21438 #define ALT_GIC_DIST_GICD_ITARGETSR96_FLD_WIDTH 32
21440 #define ALT_GIC_DIST_GICD_ITARGETSR96_FLD_SET_MSK 0xffffffff
21442 #define ALT_GIC_DIST_GICD_ITARGETSR96_FLD_CLR_MSK 0x00000000
21444 #define ALT_GIC_DIST_GICD_ITARGETSR96_FLD_RESET 0x0
21446 #define ALT_GIC_DIST_GICD_ITARGETSR96_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21448 #define ALT_GIC_DIST_GICD_ITARGETSR96_FLD_SET(value) (((value) << 0) & 0xffffffff)
21450 #ifndef __ASSEMBLY__
21462 struct ALT_GIC_DIST_GICD_ITARGETSR96_s
21464 volatile uint32_t fld : 32;
21468 typedef struct ALT_GIC_DIST_GICD_ITARGETSR96_s ALT_GIC_DIST_GICD_ITARGETSR96_t;
21472 #define ALT_GIC_DIST_GICD_ITARGETSR96_RESET 0x00000000
21474 #define ALT_GIC_DIST_GICD_ITARGETSR96_OFST 0x980
21497 #define ALT_GIC_DIST_GICD_ITARGETSR97_FLD_LSB 0
21499 #define ALT_GIC_DIST_GICD_ITARGETSR97_FLD_MSB 31
21501 #define ALT_GIC_DIST_GICD_ITARGETSR97_FLD_WIDTH 32
21503 #define ALT_GIC_DIST_GICD_ITARGETSR97_FLD_SET_MSK 0xffffffff
21505 #define ALT_GIC_DIST_GICD_ITARGETSR97_FLD_CLR_MSK 0x00000000
21507 #define ALT_GIC_DIST_GICD_ITARGETSR97_FLD_RESET 0x0
21509 #define ALT_GIC_DIST_GICD_ITARGETSR97_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21511 #define ALT_GIC_DIST_GICD_ITARGETSR97_FLD_SET(value) (((value) << 0) & 0xffffffff)
21513 #ifndef __ASSEMBLY__
21525 struct ALT_GIC_DIST_GICD_ITARGETSR97_s
21527 volatile uint32_t fld : 32;
21531 typedef struct ALT_GIC_DIST_GICD_ITARGETSR97_s ALT_GIC_DIST_GICD_ITARGETSR97_t;
21535 #define ALT_GIC_DIST_GICD_ITARGETSR97_RESET 0x00000000
21537 #define ALT_GIC_DIST_GICD_ITARGETSR97_OFST 0x984
21560 #define ALT_GIC_DIST_GICD_ITARGETSR98_FLD_LSB 0
21562 #define ALT_GIC_DIST_GICD_ITARGETSR98_FLD_MSB 31
21564 #define ALT_GIC_DIST_GICD_ITARGETSR98_FLD_WIDTH 32
21566 #define ALT_GIC_DIST_GICD_ITARGETSR98_FLD_SET_MSK 0xffffffff
21568 #define ALT_GIC_DIST_GICD_ITARGETSR98_FLD_CLR_MSK 0x00000000
21570 #define ALT_GIC_DIST_GICD_ITARGETSR98_FLD_RESET 0x0
21572 #define ALT_GIC_DIST_GICD_ITARGETSR98_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21574 #define ALT_GIC_DIST_GICD_ITARGETSR98_FLD_SET(value) (((value) << 0) & 0xffffffff)
21576 #ifndef __ASSEMBLY__
21588 struct ALT_GIC_DIST_GICD_ITARGETSR98_s
21590 volatile uint32_t fld : 32;
21594 typedef struct ALT_GIC_DIST_GICD_ITARGETSR98_s ALT_GIC_DIST_GICD_ITARGETSR98_t;
21598 #define ALT_GIC_DIST_GICD_ITARGETSR98_RESET 0x00000000
21600 #define ALT_GIC_DIST_GICD_ITARGETSR98_OFST 0x988
21623 #define ALT_GIC_DIST_GICD_ITARGETSR99_FLD_LSB 0
21625 #define ALT_GIC_DIST_GICD_ITARGETSR99_FLD_MSB 31
21627 #define ALT_GIC_DIST_GICD_ITARGETSR99_FLD_WIDTH 32
21629 #define ALT_GIC_DIST_GICD_ITARGETSR99_FLD_SET_MSK 0xffffffff
21631 #define ALT_GIC_DIST_GICD_ITARGETSR99_FLD_CLR_MSK 0x00000000
21633 #define ALT_GIC_DIST_GICD_ITARGETSR99_FLD_RESET 0x0
21635 #define ALT_GIC_DIST_GICD_ITARGETSR99_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21637 #define ALT_GIC_DIST_GICD_ITARGETSR99_FLD_SET(value) (((value) << 0) & 0xffffffff)
21639 #ifndef __ASSEMBLY__
21651 struct ALT_GIC_DIST_GICD_ITARGETSR99_s
21653 volatile uint32_t fld : 32;
21657 typedef struct ALT_GIC_DIST_GICD_ITARGETSR99_s ALT_GIC_DIST_GICD_ITARGETSR99_t;
21661 #define ALT_GIC_DIST_GICD_ITARGETSR99_RESET 0x00000000
21663 #define ALT_GIC_DIST_GICD_ITARGETSR99_OFST 0x98c
21686 #define ALT_GIC_DIST_GICD_ITARGETSR100_FLD_LSB 0
21688 #define ALT_GIC_DIST_GICD_ITARGETSR100_FLD_MSB 31
21690 #define ALT_GIC_DIST_GICD_ITARGETSR100_FLD_WIDTH 32
21692 #define ALT_GIC_DIST_GICD_ITARGETSR100_FLD_SET_MSK 0xffffffff
21694 #define ALT_GIC_DIST_GICD_ITARGETSR100_FLD_CLR_MSK 0x00000000
21696 #define ALT_GIC_DIST_GICD_ITARGETSR100_FLD_RESET 0x0
21698 #define ALT_GIC_DIST_GICD_ITARGETSR100_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21700 #define ALT_GIC_DIST_GICD_ITARGETSR100_FLD_SET(value) (((value) << 0) & 0xffffffff)
21702 #ifndef __ASSEMBLY__
21714 struct ALT_GIC_DIST_GICD_ITARGETSR100_s
21716 volatile uint32_t fld : 32;
21720 typedef struct ALT_GIC_DIST_GICD_ITARGETSR100_s ALT_GIC_DIST_GICD_ITARGETSR100_t;
21724 #define ALT_GIC_DIST_GICD_ITARGETSR100_RESET 0x00000000
21726 #define ALT_GIC_DIST_GICD_ITARGETSR100_OFST 0x990
21749 #define ALT_GIC_DIST_GICD_ITARGETSR101_FLD_LSB 0
21751 #define ALT_GIC_DIST_GICD_ITARGETSR101_FLD_MSB 31
21753 #define ALT_GIC_DIST_GICD_ITARGETSR101_FLD_WIDTH 32
21755 #define ALT_GIC_DIST_GICD_ITARGETSR101_FLD_SET_MSK 0xffffffff
21757 #define ALT_GIC_DIST_GICD_ITARGETSR101_FLD_CLR_MSK 0x00000000
21759 #define ALT_GIC_DIST_GICD_ITARGETSR101_FLD_RESET 0x0
21761 #define ALT_GIC_DIST_GICD_ITARGETSR101_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21763 #define ALT_GIC_DIST_GICD_ITARGETSR101_FLD_SET(value) (((value) << 0) & 0xffffffff)
21765 #ifndef __ASSEMBLY__
21777 struct ALT_GIC_DIST_GICD_ITARGETSR101_s
21779 volatile uint32_t fld : 32;
21783 typedef struct ALT_GIC_DIST_GICD_ITARGETSR101_s ALT_GIC_DIST_GICD_ITARGETSR101_t;
21787 #define ALT_GIC_DIST_GICD_ITARGETSR101_RESET 0x00000000
21789 #define ALT_GIC_DIST_GICD_ITARGETSR101_OFST 0x994
21812 #define ALT_GIC_DIST_GICD_ITARGETSR102_FLD_LSB 0
21814 #define ALT_GIC_DIST_GICD_ITARGETSR102_FLD_MSB 31
21816 #define ALT_GIC_DIST_GICD_ITARGETSR102_FLD_WIDTH 32
21818 #define ALT_GIC_DIST_GICD_ITARGETSR102_FLD_SET_MSK 0xffffffff
21820 #define ALT_GIC_DIST_GICD_ITARGETSR102_FLD_CLR_MSK 0x00000000
21822 #define ALT_GIC_DIST_GICD_ITARGETSR102_FLD_RESET 0x0
21824 #define ALT_GIC_DIST_GICD_ITARGETSR102_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21826 #define ALT_GIC_DIST_GICD_ITARGETSR102_FLD_SET(value) (((value) << 0) & 0xffffffff)
21828 #ifndef __ASSEMBLY__
21840 struct ALT_GIC_DIST_GICD_ITARGETSR102_s
21842 volatile uint32_t fld : 32;
21846 typedef struct ALT_GIC_DIST_GICD_ITARGETSR102_s ALT_GIC_DIST_GICD_ITARGETSR102_t;
21850 #define ALT_GIC_DIST_GICD_ITARGETSR102_RESET 0x00000000
21852 #define ALT_GIC_DIST_GICD_ITARGETSR102_OFST 0x998
21875 #define ALT_GIC_DIST_GICD_ITARGETSR103_FLD_LSB 0
21877 #define ALT_GIC_DIST_GICD_ITARGETSR103_FLD_MSB 31
21879 #define ALT_GIC_DIST_GICD_ITARGETSR103_FLD_WIDTH 32
21881 #define ALT_GIC_DIST_GICD_ITARGETSR103_FLD_SET_MSK 0xffffffff
21883 #define ALT_GIC_DIST_GICD_ITARGETSR103_FLD_CLR_MSK 0x00000000
21885 #define ALT_GIC_DIST_GICD_ITARGETSR103_FLD_RESET 0x0
21887 #define ALT_GIC_DIST_GICD_ITARGETSR103_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21889 #define ALT_GIC_DIST_GICD_ITARGETSR103_FLD_SET(value) (((value) << 0) & 0xffffffff)
21891 #ifndef __ASSEMBLY__
21903 struct ALT_GIC_DIST_GICD_ITARGETSR103_s
21905 volatile uint32_t fld : 32;
21909 typedef struct ALT_GIC_DIST_GICD_ITARGETSR103_s ALT_GIC_DIST_GICD_ITARGETSR103_t;
21913 #define ALT_GIC_DIST_GICD_ITARGETSR103_RESET 0x00000000
21915 #define ALT_GIC_DIST_GICD_ITARGETSR103_OFST 0x99c
21938 #define ALT_GIC_DIST_GICD_ITARGETSR104_FLD_LSB 0
21940 #define ALT_GIC_DIST_GICD_ITARGETSR104_FLD_MSB 31
21942 #define ALT_GIC_DIST_GICD_ITARGETSR104_FLD_WIDTH 32
21944 #define ALT_GIC_DIST_GICD_ITARGETSR104_FLD_SET_MSK 0xffffffff
21946 #define ALT_GIC_DIST_GICD_ITARGETSR104_FLD_CLR_MSK 0x00000000
21948 #define ALT_GIC_DIST_GICD_ITARGETSR104_FLD_RESET 0x0
21950 #define ALT_GIC_DIST_GICD_ITARGETSR104_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21952 #define ALT_GIC_DIST_GICD_ITARGETSR104_FLD_SET(value) (((value) << 0) & 0xffffffff)
21954 #ifndef __ASSEMBLY__
21966 struct ALT_GIC_DIST_GICD_ITARGETSR104_s
21968 volatile uint32_t fld : 32;
21972 typedef struct ALT_GIC_DIST_GICD_ITARGETSR104_s ALT_GIC_DIST_GICD_ITARGETSR104_t;
21976 #define ALT_GIC_DIST_GICD_ITARGETSR104_RESET 0x00000000
21978 #define ALT_GIC_DIST_GICD_ITARGETSR104_OFST 0x9a0
22001 #define ALT_GIC_DIST_GICD_ITARGETSR105_FLD_LSB 0
22003 #define ALT_GIC_DIST_GICD_ITARGETSR105_FLD_MSB 31
22005 #define ALT_GIC_DIST_GICD_ITARGETSR105_FLD_WIDTH 32
22007 #define ALT_GIC_DIST_GICD_ITARGETSR105_FLD_SET_MSK 0xffffffff
22009 #define ALT_GIC_DIST_GICD_ITARGETSR105_FLD_CLR_MSK 0x00000000
22011 #define ALT_GIC_DIST_GICD_ITARGETSR105_FLD_RESET 0x0
22013 #define ALT_GIC_DIST_GICD_ITARGETSR105_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22015 #define ALT_GIC_DIST_GICD_ITARGETSR105_FLD_SET(value) (((value) << 0) & 0xffffffff)
22017 #ifndef __ASSEMBLY__
22029 struct ALT_GIC_DIST_GICD_ITARGETSR105_s
22031 volatile uint32_t fld : 32;
22035 typedef struct ALT_GIC_DIST_GICD_ITARGETSR105_s ALT_GIC_DIST_GICD_ITARGETSR105_t;
22039 #define ALT_GIC_DIST_GICD_ITARGETSR105_RESET 0x00000000
22041 #define ALT_GIC_DIST_GICD_ITARGETSR105_OFST 0x9a4
22064 #define ALT_GIC_DIST_GICD_ITARGETSR106_FLD_LSB 0
22066 #define ALT_GIC_DIST_GICD_ITARGETSR106_FLD_MSB 31
22068 #define ALT_GIC_DIST_GICD_ITARGETSR106_FLD_WIDTH 32
22070 #define ALT_GIC_DIST_GICD_ITARGETSR106_FLD_SET_MSK 0xffffffff
22072 #define ALT_GIC_DIST_GICD_ITARGETSR106_FLD_CLR_MSK 0x00000000
22074 #define ALT_GIC_DIST_GICD_ITARGETSR106_FLD_RESET 0x0
22076 #define ALT_GIC_DIST_GICD_ITARGETSR106_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22078 #define ALT_GIC_DIST_GICD_ITARGETSR106_FLD_SET(value) (((value) << 0) & 0xffffffff)
22080 #ifndef __ASSEMBLY__
22092 struct ALT_GIC_DIST_GICD_ITARGETSR106_s
22094 volatile uint32_t fld : 32;
22098 typedef struct ALT_GIC_DIST_GICD_ITARGETSR106_s ALT_GIC_DIST_GICD_ITARGETSR106_t;
22102 #define ALT_GIC_DIST_GICD_ITARGETSR106_RESET 0x00000000
22104 #define ALT_GIC_DIST_GICD_ITARGETSR106_OFST 0x9a8
22127 #define ALT_GIC_DIST_GICD_ITARGETSR107_FLD_LSB 0
22129 #define ALT_GIC_DIST_GICD_ITARGETSR107_FLD_MSB 31
22131 #define ALT_GIC_DIST_GICD_ITARGETSR107_FLD_WIDTH 32
22133 #define ALT_GIC_DIST_GICD_ITARGETSR107_FLD_SET_MSK 0xffffffff
22135 #define ALT_GIC_DIST_GICD_ITARGETSR107_FLD_CLR_MSK 0x00000000
22137 #define ALT_GIC_DIST_GICD_ITARGETSR107_FLD_RESET 0x0
22139 #define ALT_GIC_DIST_GICD_ITARGETSR107_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22141 #define ALT_GIC_DIST_GICD_ITARGETSR107_FLD_SET(value) (((value) << 0) & 0xffffffff)
22143 #ifndef __ASSEMBLY__
22155 struct ALT_GIC_DIST_GICD_ITARGETSR107_s
22157 volatile uint32_t fld : 32;
22161 typedef struct ALT_GIC_DIST_GICD_ITARGETSR107_s ALT_GIC_DIST_GICD_ITARGETSR107_t;
22165 #define ALT_GIC_DIST_GICD_ITARGETSR107_RESET 0x00000000
22167 #define ALT_GIC_DIST_GICD_ITARGETSR107_OFST 0x9ac
22190 #define ALT_GIC_DIST_GICD_ITARGETSR108_FLD_LSB 0
22192 #define ALT_GIC_DIST_GICD_ITARGETSR108_FLD_MSB 31
22194 #define ALT_GIC_DIST_GICD_ITARGETSR108_FLD_WIDTH 32
22196 #define ALT_GIC_DIST_GICD_ITARGETSR108_FLD_SET_MSK 0xffffffff
22198 #define ALT_GIC_DIST_GICD_ITARGETSR108_FLD_CLR_MSK 0x00000000
22200 #define ALT_GIC_DIST_GICD_ITARGETSR108_FLD_RESET 0x0
22202 #define ALT_GIC_DIST_GICD_ITARGETSR108_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22204 #define ALT_GIC_DIST_GICD_ITARGETSR108_FLD_SET(value) (((value) << 0) & 0xffffffff)
22206 #ifndef __ASSEMBLY__
22218 struct ALT_GIC_DIST_GICD_ITARGETSR108_s
22220 volatile uint32_t fld : 32;
22224 typedef struct ALT_GIC_DIST_GICD_ITARGETSR108_s ALT_GIC_DIST_GICD_ITARGETSR108_t;
22228 #define ALT_GIC_DIST_GICD_ITARGETSR108_RESET 0x00000000
22230 #define ALT_GIC_DIST_GICD_ITARGETSR108_OFST 0x9b0
22253 #define ALT_GIC_DIST_GICD_ITARGETSR109_FLD_LSB 0
22255 #define ALT_GIC_DIST_GICD_ITARGETSR109_FLD_MSB 31
22257 #define ALT_GIC_DIST_GICD_ITARGETSR109_FLD_WIDTH 32
22259 #define ALT_GIC_DIST_GICD_ITARGETSR109_FLD_SET_MSK 0xffffffff
22261 #define ALT_GIC_DIST_GICD_ITARGETSR109_FLD_CLR_MSK 0x00000000
22263 #define ALT_GIC_DIST_GICD_ITARGETSR109_FLD_RESET 0x0
22265 #define ALT_GIC_DIST_GICD_ITARGETSR109_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22267 #define ALT_GIC_DIST_GICD_ITARGETSR109_FLD_SET(value) (((value) << 0) & 0xffffffff)
22269 #ifndef __ASSEMBLY__
22281 struct ALT_GIC_DIST_GICD_ITARGETSR109_s
22283 volatile uint32_t fld : 32;
22287 typedef struct ALT_GIC_DIST_GICD_ITARGETSR109_s ALT_GIC_DIST_GICD_ITARGETSR109_t;
22291 #define ALT_GIC_DIST_GICD_ITARGETSR109_RESET 0x00000000
22293 #define ALT_GIC_DIST_GICD_ITARGETSR109_OFST 0x9b4
22316 #define ALT_GIC_DIST_GICD_ITARGETSR110_FLD_LSB 0
22318 #define ALT_GIC_DIST_GICD_ITARGETSR110_FLD_MSB 31
22320 #define ALT_GIC_DIST_GICD_ITARGETSR110_FLD_WIDTH 32
22322 #define ALT_GIC_DIST_GICD_ITARGETSR110_FLD_SET_MSK 0xffffffff
22324 #define ALT_GIC_DIST_GICD_ITARGETSR110_FLD_CLR_MSK 0x00000000
22326 #define ALT_GIC_DIST_GICD_ITARGETSR110_FLD_RESET 0x0
22328 #define ALT_GIC_DIST_GICD_ITARGETSR110_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22330 #define ALT_GIC_DIST_GICD_ITARGETSR110_FLD_SET(value) (((value) << 0) & 0xffffffff)
22332 #ifndef __ASSEMBLY__
22344 struct ALT_GIC_DIST_GICD_ITARGETSR110_s
22346 volatile uint32_t fld : 32;
22350 typedef struct ALT_GIC_DIST_GICD_ITARGETSR110_s ALT_GIC_DIST_GICD_ITARGETSR110_t;
22354 #define ALT_GIC_DIST_GICD_ITARGETSR110_RESET 0x00000000
22356 #define ALT_GIC_DIST_GICD_ITARGETSR110_OFST 0x9b8
22379 #define ALT_GIC_DIST_GICD_ITARGETSR111_FLD_LSB 0
22381 #define ALT_GIC_DIST_GICD_ITARGETSR111_FLD_MSB 31
22383 #define ALT_GIC_DIST_GICD_ITARGETSR111_FLD_WIDTH 32
22385 #define ALT_GIC_DIST_GICD_ITARGETSR111_FLD_SET_MSK 0xffffffff
22387 #define ALT_GIC_DIST_GICD_ITARGETSR111_FLD_CLR_MSK 0x00000000
22389 #define ALT_GIC_DIST_GICD_ITARGETSR111_FLD_RESET 0x0
22391 #define ALT_GIC_DIST_GICD_ITARGETSR111_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22393 #define ALT_GIC_DIST_GICD_ITARGETSR111_FLD_SET(value) (((value) << 0) & 0xffffffff)
22395 #ifndef __ASSEMBLY__
22407 struct ALT_GIC_DIST_GICD_ITARGETSR111_s
22409 volatile uint32_t fld : 32;
22413 typedef struct ALT_GIC_DIST_GICD_ITARGETSR111_s ALT_GIC_DIST_GICD_ITARGETSR111_t;
22417 #define ALT_GIC_DIST_GICD_ITARGETSR111_RESET 0x00000000
22419 #define ALT_GIC_DIST_GICD_ITARGETSR111_OFST 0x9bc
22442 #define ALT_GIC_DIST_GICD_ITARGETSR112_FLD_LSB 0
22444 #define ALT_GIC_DIST_GICD_ITARGETSR112_FLD_MSB 31
22446 #define ALT_GIC_DIST_GICD_ITARGETSR112_FLD_WIDTH 32
22448 #define ALT_GIC_DIST_GICD_ITARGETSR112_FLD_SET_MSK 0xffffffff
22450 #define ALT_GIC_DIST_GICD_ITARGETSR112_FLD_CLR_MSK 0x00000000
22452 #define ALT_GIC_DIST_GICD_ITARGETSR112_FLD_RESET 0x0
22454 #define ALT_GIC_DIST_GICD_ITARGETSR112_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22456 #define ALT_GIC_DIST_GICD_ITARGETSR112_FLD_SET(value) (((value) << 0) & 0xffffffff)
22458 #ifndef __ASSEMBLY__
22470 struct ALT_GIC_DIST_GICD_ITARGETSR112_s
22472 volatile uint32_t fld : 32;
22476 typedef struct ALT_GIC_DIST_GICD_ITARGETSR112_s ALT_GIC_DIST_GICD_ITARGETSR112_t;
22480 #define ALT_GIC_DIST_GICD_ITARGETSR112_RESET 0x00000000
22482 #define ALT_GIC_DIST_GICD_ITARGETSR112_OFST 0x9c0
22505 #define ALT_GIC_DIST_GICD_ITARGETSR113_FLD_LSB 0
22507 #define ALT_GIC_DIST_GICD_ITARGETSR113_FLD_MSB 31
22509 #define ALT_GIC_DIST_GICD_ITARGETSR113_FLD_WIDTH 32
22511 #define ALT_GIC_DIST_GICD_ITARGETSR113_FLD_SET_MSK 0xffffffff
22513 #define ALT_GIC_DIST_GICD_ITARGETSR113_FLD_CLR_MSK 0x00000000
22515 #define ALT_GIC_DIST_GICD_ITARGETSR113_FLD_RESET 0x0
22517 #define ALT_GIC_DIST_GICD_ITARGETSR113_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22519 #define ALT_GIC_DIST_GICD_ITARGETSR113_FLD_SET(value) (((value) << 0) & 0xffffffff)
22521 #ifndef __ASSEMBLY__
22533 struct ALT_GIC_DIST_GICD_ITARGETSR113_s
22535 volatile uint32_t fld : 32;
22539 typedef struct ALT_GIC_DIST_GICD_ITARGETSR113_s ALT_GIC_DIST_GICD_ITARGETSR113_t;
22543 #define ALT_GIC_DIST_GICD_ITARGETSR113_RESET 0x00000000
22545 #define ALT_GIC_DIST_GICD_ITARGETSR113_OFST 0x9c4
22568 #define ALT_GIC_DIST_GICD_ITARGETSR114_FLD_LSB 0
22570 #define ALT_GIC_DIST_GICD_ITARGETSR114_FLD_MSB 31
22572 #define ALT_GIC_DIST_GICD_ITARGETSR114_FLD_WIDTH 32
22574 #define ALT_GIC_DIST_GICD_ITARGETSR114_FLD_SET_MSK 0xffffffff
22576 #define ALT_GIC_DIST_GICD_ITARGETSR114_FLD_CLR_MSK 0x00000000
22578 #define ALT_GIC_DIST_GICD_ITARGETSR114_FLD_RESET 0x0
22580 #define ALT_GIC_DIST_GICD_ITARGETSR114_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22582 #define ALT_GIC_DIST_GICD_ITARGETSR114_FLD_SET(value) (((value) << 0) & 0xffffffff)
22584 #ifndef __ASSEMBLY__
22596 struct ALT_GIC_DIST_GICD_ITARGETSR114_s
22598 volatile uint32_t fld : 32;
22602 typedef struct ALT_GIC_DIST_GICD_ITARGETSR114_s ALT_GIC_DIST_GICD_ITARGETSR114_t;
22606 #define ALT_GIC_DIST_GICD_ITARGETSR114_RESET 0x00000000
22608 #define ALT_GIC_DIST_GICD_ITARGETSR114_OFST 0x9c8
22631 #define ALT_GIC_DIST_GICD_ITARGETSR115_FLD_LSB 0
22633 #define ALT_GIC_DIST_GICD_ITARGETSR115_FLD_MSB 31
22635 #define ALT_GIC_DIST_GICD_ITARGETSR115_FLD_WIDTH 32
22637 #define ALT_GIC_DIST_GICD_ITARGETSR115_FLD_SET_MSK 0xffffffff
22639 #define ALT_GIC_DIST_GICD_ITARGETSR115_FLD_CLR_MSK 0x00000000
22641 #define ALT_GIC_DIST_GICD_ITARGETSR115_FLD_RESET 0x0
22643 #define ALT_GIC_DIST_GICD_ITARGETSR115_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22645 #define ALT_GIC_DIST_GICD_ITARGETSR115_FLD_SET(value) (((value) << 0) & 0xffffffff)
22647 #ifndef __ASSEMBLY__
22659 struct ALT_GIC_DIST_GICD_ITARGETSR115_s
22661 volatile uint32_t fld : 32;
22665 typedef struct ALT_GIC_DIST_GICD_ITARGETSR115_s ALT_GIC_DIST_GICD_ITARGETSR115_t;
22669 #define ALT_GIC_DIST_GICD_ITARGETSR115_RESET 0x00000000
22671 #define ALT_GIC_DIST_GICD_ITARGETSR115_OFST 0x9cc
22694 #define ALT_GIC_DIST_GICD_ITARGETSR116_FLD_LSB 0
22696 #define ALT_GIC_DIST_GICD_ITARGETSR116_FLD_MSB 31
22698 #define ALT_GIC_DIST_GICD_ITARGETSR116_FLD_WIDTH 32
22700 #define ALT_GIC_DIST_GICD_ITARGETSR116_FLD_SET_MSK 0xffffffff
22702 #define ALT_GIC_DIST_GICD_ITARGETSR116_FLD_CLR_MSK 0x00000000
22704 #define ALT_GIC_DIST_GICD_ITARGETSR116_FLD_RESET 0x0
22706 #define ALT_GIC_DIST_GICD_ITARGETSR116_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22708 #define ALT_GIC_DIST_GICD_ITARGETSR116_FLD_SET(value) (((value) << 0) & 0xffffffff)
22710 #ifndef __ASSEMBLY__
22722 struct ALT_GIC_DIST_GICD_ITARGETSR116_s
22724 volatile uint32_t fld : 32;
22728 typedef struct ALT_GIC_DIST_GICD_ITARGETSR116_s ALT_GIC_DIST_GICD_ITARGETSR116_t;
22732 #define ALT_GIC_DIST_GICD_ITARGETSR116_RESET 0x00000000
22734 #define ALT_GIC_DIST_GICD_ITARGETSR116_OFST 0x9d0
22757 #define ALT_GIC_DIST_GICD_ITARGETSR117_FLD_LSB 0
22759 #define ALT_GIC_DIST_GICD_ITARGETSR117_FLD_MSB 31
22761 #define ALT_GIC_DIST_GICD_ITARGETSR117_FLD_WIDTH 32
22763 #define ALT_GIC_DIST_GICD_ITARGETSR117_FLD_SET_MSK 0xffffffff
22765 #define ALT_GIC_DIST_GICD_ITARGETSR117_FLD_CLR_MSK 0x00000000
22767 #define ALT_GIC_DIST_GICD_ITARGETSR117_FLD_RESET 0x0
22769 #define ALT_GIC_DIST_GICD_ITARGETSR117_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22771 #define ALT_GIC_DIST_GICD_ITARGETSR117_FLD_SET(value) (((value) << 0) & 0xffffffff)
22773 #ifndef __ASSEMBLY__
22785 struct ALT_GIC_DIST_GICD_ITARGETSR117_s
22787 volatile uint32_t fld : 32;
22791 typedef struct ALT_GIC_DIST_GICD_ITARGETSR117_s ALT_GIC_DIST_GICD_ITARGETSR117_t;
22795 #define ALT_GIC_DIST_GICD_ITARGETSR117_RESET 0x00000000
22797 #define ALT_GIC_DIST_GICD_ITARGETSR117_OFST 0x9d4
22820 #define ALT_GIC_DIST_GICD_ITARGETSR118_FLD_LSB 0
22822 #define ALT_GIC_DIST_GICD_ITARGETSR118_FLD_MSB 31
22824 #define ALT_GIC_DIST_GICD_ITARGETSR118_FLD_WIDTH 32
22826 #define ALT_GIC_DIST_GICD_ITARGETSR118_FLD_SET_MSK 0xffffffff
22828 #define ALT_GIC_DIST_GICD_ITARGETSR118_FLD_CLR_MSK 0x00000000
22830 #define ALT_GIC_DIST_GICD_ITARGETSR118_FLD_RESET 0x0
22832 #define ALT_GIC_DIST_GICD_ITARGETSR118_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22834 #define ALT_GIC_DIST_GICD_ITARGETSR118_FLD_SET(value) (((value) << 0) & 0xffffffff)
22836 #ifndef __ASSEMBLY__
22848 struct ALT_GIC_DIST_GICD_ITARGETSR118_s
22850 volatile uint32_t fld : 32;
22854 typedef struct ALT_GIC_DIST_GICD_ITARGETSR118_s ALT_GIC_DIST_GICD_ITARGETSR118_t;
22858 #define ALT_GIC_DIST_GICD_ITARGETSR118_RESET 0x00000000
22860 #define ALT_GIC_DIST_GICD_ITARGETSR118_OFST 0x9d8
22883 #define ALT_GIC_DIST_GICD_ITARGETSR119_FLD_LSB 0
22885 #define ALT_GIC_DIST_GICD_ITARGETSR119_FLD_MSB 31
22887 #define ALT_GIC_DIST_GICD_ITARGETSR119_FLD_WIDTH 32
22889 #define ALT_GIC_DIST_GICD_ITARGETSR119_FLD_SET_MSK 0xffffffff
22891 #define ALT_GIC_DIST_GICD_ITARGETSR119_FLD_CLR_MSK 0x00000000
22893 #define ALT_GIC_DIST_GICD_ITARGETSR119_FLD_RESET 0x0
22895 #define ALT_GIC_DIST_GICD_ITARGETSR119_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22897 #define ALT_GIC_DIST_GICD_ITARGETSR119_FLD_SET(value) (((value) << 0) & 0xffffffff)
22899 #ifndef __ASSEMBLY__
22911 struct ALT_GIC_DIST_GICD_ITARGETSR119_s
22913 volatile uint32_t fld : 32;
22917 typedef struct ALT_GIC_DIST_GICD_ITARGETSR119_s ALT_GIC_DIST_GICD_ITARGETSR119_t;
22921 #define ALT_GIC_DIST_GICD_ITARGETSR119_RESET 0x00000000
22923 #define ALT_GIC_DIST_GICD_ITARGETSR119_OFST 0x9dc
22946 #define ALT_GIC_DIST_GICD_ITARGETSR120_FLD_LSB 0
22948 #define ALT_GIC_DIST_GICD_ITARGETSR120_FLD_MSB 31
22950 #define ALT_GIC_DIST_GICD_ITARGETSR120_FLD_WIDTH 32
22952 #define ALT_GIC_DIST_GICD_ITARGETSR120_FLD_SET_MSK 0xffffffff
22954 #define ALT_GIC_DIST_GICD_ITARGETSR120_FLD_CLR_MSK 0x00000000
22956 #define ALT_GIC_DIST_GICD_ITARGETSR120_FLD_RESET 0x0
22958 #define ALT_GIC_DIST_GICD_ITARGETSR120_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22960 #define ALT_GIC_DIST_GICD_ITARGETSR120_FLD_SET(value) (((value) << 0) & 0xffffffff)
22962 #ifndef __ASSEMBLY__
22974 struct ALT_GIC_DIST_GICD_ITARGETSR120_s
22976 volatile uint32_t fld : 32;
22980 typedef struct ALT_GIC_DIST_GICD_ITARGETSR120_s ALT_GIC_DIST_GICD_ITARGETSR120_t;
22984 #define ALT_GIC_DIST_GICD_ITARGETSR120_RESET 0x00000000
22986 #define ALT_GIC_DIST_GICD_ITARGETSR120_OFST 0x9e0
23009 #define ALT_GIC_DIST_GICD_ITARGETSR121_FLD_LSB 0
23011 #define ALT_GIC_DIST_GICD_ITARGETSR121_FLD_MSB 31
23013 #define ALT_GIC_DIST_GICD_ITARGETSR121_FLD_WIDTH 32
23015 #define ALT_GIC_DIST_GICD_ITARGETSR121_FLD_SET_MSK 0xffffffff
23017 #define ALT_GIC_DIST_GICD_ITARGETSR121_FLD_CLR_MSK 0x00000000
23019 #define ALT_GIC_DIST_GICD_ITARGETSR121_FLD_RESET 0x0
23021 #define ALT_GIC_DIST_GICD_ITARGETSR121_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23023 #define ALT_GIC_DIST_GICD_ITARGETSR121_FLD_SET(value) (((value) << 0) & 0xffffffff)
23025 #ifndef __ASSEMBLY__
23037 struct ALT_GIC_DIST_GICD_ITARGETSR121_s
23039 volatile uint32_t fld : 32;
23043 typedef struct ALT_GIC_DIST_GICD_ITARGETSR121_s ALT_GIC_DIST_GICD_ITARGETSR121_t;
23047 #define ALT_GIC_DIST_GICD_ITARGETSR121_RESET 0x00000000
23049 #define ALT_GIC_DIST_GICD_ITARGETSR121_OFST 0x9e4
23072 #define ALT_GIC_DIST_GICD_ITARGETSR122_FLD_LSB 0
23074 #define ALT_GIC_DIST_GICD_ITARGETSR122_FLD_MSB 31
23076 #define ALT_GIC_DIST_GICD_ITARGETSR122_FLD_WIDTH 32
23078 #define ALT_GIC_DIST_GICD_ITARGETSR122_FLD_SET_MSK 0xffffffff
23080 #define ALT_GIC_DIST_GICD_ITARGETSR122_FLD_CLR_MSK 0x00000000
23082 #define ALT_GIC_DIST_GICD_ITARGETSR122_FLD_RESET 0x0
23084 #define ALT_GIC_DIST_GICD_ITARGETSR122_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23086 #define ALT_GIC_DIST_GICD_ITARGETSR122_FLD_SET(value) (((value) << 0) & 0xffffffff)
23088 #ifndef __ASSEMBLY__
23100 struct ALT_GIC_DIST_GICD_ITARGETSR122_s
23102 volatile uint32_t fld : 32;
23106 typedef struct ALT_GIC_DIST_GICD_ITARGETSR122_s ALT_GIC_DIST_GICD_ITARGETSR122_t;
23110 #define ALT_GIC_DIST_GICD_ITARGETSR122_RESET 0x00000000
23112 #define ALT_GIC_DIST_GICD_ITARGETSR122_OFST 0x9e8
23135 #define ALT_GIC_DIST_GICD_ITARGETSR123_FLD_LSB 0
23137 #define ALT_GIC_DIST_GICD_ITARGETSR123_FLD_MSB 31
23139 #define ALT_GIC_DIST_GICD_ITARGETSR123_FLD_WIDTH 32
23141 #define ALT_GIC_DIST_GICD_ITARGETSR123_FLD_SET_MSK 0xffffffff
23143 #define ALT_GIC_DIST_GICD_ITARGETSR123_FLD_CLR_MSK 0x00000000
23145 #define ALT_GIC_DIST_GICD_ITARGETSR123_FLD_RESET 0x0
23147 #define ALT_GIC_DIST_GICD_ITARGETSR123_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23149 #define ALT_GIC_DIST_GICD_ITARGETSR123_FLD_SET(value) (((value) << 0) & 0xffffffff)
23151 #ifndef __ASSEMBLY__
23163 struct ALT_GIC_DIST_GICD_ITARGETSR123_s
23165 volatile uint32_t fld : 32;
23169 typedef struct ALT_GIC_DIST_GICD_ITARGETSR123_s ALT_GIC_DIST_GICD_ITARGETSR123_t;
23173 #define ALT_GIC_DIST_GICD_ITARGETSR123_RESET 0x00000000
23175 #define ALT_GIC_DIST_GICD_ITARGETSR123_OFST 0x9ec
23198 #define ALT_GIC_DIST_GICD_ITARGETSR124_FLD_LSB 0
23200 #define ALT_GIC_DIST_GICD_ITARGETSR124_FLD_MSB 31
23202 #define ALT_GIC_DIST_GICD_ITARGETSR124_FLD_WIDTH 32
23204 #define ALT_GIC_DIST_GICD_ITARGETSR124_FLD_SET_MSK 0xffffffff
23206 #define ALT_GIC_DIST_GICD_ITARGETSR124_FLD_CLR_MSK 0x00000000
23208 #define ALT_GIC_DIST_GICD_ITARGETSR124_FLD_RESET 0x0
23210 #define ALT_GIC_DIST_GICD_ITARGETSR124_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23212 #define ALT_GIC_DIST_GICD_ITARGETSR124_FLD_SET(value) (((value) << 0) & 0xffffffff)
23214 #ifndef __ASSEMBLY__
23226 struct ALT_GIC_DIST_GICD_ITARGETSR124_s
23228 volatile uint32_t fld : 32;
23232 typedef struct ALT_GIC_DIST_GICD_ITARGETSR124_s ALT_GIC_DIST_GICD_ITARGETSR124_t;
23236 #define ALT_GIC_DIST_GICD_ITARGETSR124_RESET 0x00000000
23238 #define ALT_GIC_DIST_GICD_ITARGETSR124_OFST 0x9f0
23261 #define ALT_GIC_DIST_GICD_ITARGETSR125_FLD_LSB 0
23263 #define ALT_GIC_DIST_GICD_ITARGETSR125_FLD_MSB 31
23265 #define ALT_GIC_DIST_GICD_ITARGETSR125_FLD_WIDTH 32
23267 #define ALT_GIC_DIST_GICD_ITARGETSR125_FLD_SET_MSK 0xffffffff
23269 #define ALT_GIC_DIST_GICD_ITARGETSR125_FLD_CLR_MSK 0x00000000
23271 #define ALT_GIC_DIST_GICD_ITARGETSR125_FLD_RESET 0x0
23273 #define ALT_GIC_DIST_GICD_ITARGETSR125_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23275 #define ALT_GIC_DIST_GICD_ITARGETSR125_FLD_SET(value) (((value) << 0) & 0xffffffff)
23277 #ifndef __ASSEMBLY__
23289 struct ALT_GIC_DIST_GICD_ITARGETSR125_s
23291 volatile uint32_t fld : 32;
23295 typedef struct ALT_GIC_DIST_GICD_ITARGETSR125_s ALT_GIC_DIST_GICD_ITARGETSR125_t;
23299 #define ALT_GIC_DIST_GICD_ITARGETSR125_RESET 0x00000000
23301 #define ALT_GIC_DIST_GICD_ITARGETSR125_OFST 0x9f4
23324 #define ALT_GIC_DIST_GICD_ITARGETSR126_FLD_LSB 0
23326 #define ALT_GIC_DIST_GICD_ITARGETSR126_FLD_MSB 31
23328 #define ALT_GIC_DIST_GICD_ITARGETSR126_FLD_WIDTH 32
23330 #define ALT_GIC_DIST_GICD_ITARGETSR126_FLD_SET_MSK 0xffffffff
23332 #define ALT_GIC_DIST_GICD_ITARGETSR126_FLD_CLR_MSK 0x00000000
23334 #define ALT_GIC_DIST_GICD_ITARGETSR126_FLD_RESET 0x0
23336 #define ALT_GIC_DIST_GICD_ITARGETSR126_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23338 #define ALT_GIC_DIST_GICD_ITARGETSR126_FLD_SET(value) (((value) << 0) & 0xffffffff)
23340 #ifndef __ASSEMBLY__
23352 struct ALT_GIC_DIST_GICD_ITARGETSR126_s
23354 volatile uint32_t fld : 32;
23358 typedef struct ALT_GIC_DIST_GICD_ITARGETSR126_s ALT_GIC_DIST_GICD_ITARGETSR126_t;
23362 #define ALT_GIC_DIST_GICD_ITARGETSR126_RESET 0x00000000
23364 #define ALT_GIC_DIST_GICD_ITARGETSR126_OFST 0x9f8
23387 #define ALT_GIC_DIST_GICD_ITARGETSR127_FLD_LSB 0
23389 #define ALT_GIC_DIST_GICD_ITARGETSR127_FLD_MSB 31
23391 #define ALT_GIC_DIST_GICD_ITARGETSR127_FLD_WIDTH 32
23393 #define ALT_GIC_DIST_GICD_ITARGETSR127_FLD_SET_MSK 0xffffffff
23395 #define ALT_GIC_DIST_GICD_ITARGETSR127_FLD_CLR_MSK 0x00000000
23397 #define ALT_GIC_DIST_GICD_ITARGETSR127_FLD_RESET 0x0
23399 #define ALT_GIC_DIST_GICD_ITARGETSR127_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23401 #define ALT_GIC_DIST_GICD_ITARGETSR127_FLD_SET(value) (((value) << 0) & 0xffffffff)
23403 #ifndef __ASSEMBLY__
23415 struct ALT_GIC_DIST_GICD_ITARGETSR127_s
23417 volatile uint32_t fld : 32;
23421 typedef struct ALT_GIC_DIST_GICD_ITARGETSR127_s ALT_GIC_DIST_GICD_ITARGETSR127_t;
23425 #define ALT_GIC_DIST_GICD_ITARGETSR127_RESET 0x00000000
23427 #define ALT_GIC_DIST_GICD_ITARGETSR127_OFST 0x9fc
23450 #define ALT_GIC_DIST_GICD_ICFGR0_FLD_LSB 0
23452 #define ALT_GIC_DIST_GICD_ICFGR0_FLD_MSB 31
23454 #define ALT_GIC_DIST_GICD_ICFGR0_FLD_WIDTH 32
23456 #define ALT_GIC_DIST_GICD_ICFGR0_FLD_SET_MSK 0xffffffff
23458 #define ALT_GIC_DIST_GICD_ICFGR0_FLD_CLR_MSK 0x00000000
23460 #define ALT_GIC_DIST_GICD_ICFGR0_FLD_RESET 0xaaaaaaaa
23462 #define ALT_GIC_DIST_GICD_ICFGR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23464 #define ALT_GIC_DIST_GICD_ICFGR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
23466 #ifndef __ASSEMBLY__
23478 struct ALT_GIC_DIST_GICD_ICFGR0_s
23480 volatile uint32_t fld : 32;
23484 typedef struct ALT_GIC_DIST_GICD_ICFGR0_s ALT_GIC_DIST_GICD_ICFGR0_t;
23488 #define ALT_GIC_DIST_GICD_ICFGR0_RESET 0xaaaaaaaa
23490 #define ALT_GIC_DIST_GICD_ICFGR0_OFST 0xc00
23513 #define ALT_GIC_DIST_GICD_ICFGR1_FLD_LSB 0
23515 #define ALT_GIC_DIST_GICD_ICFGR1_FLD_MSB 31
23517 #define ALT_GIC_DIST_GICD_ICFGR1_FLD_WIDTH 32
23519 #define ALT_GIC_DIST_GICD_ICFGR1_FLD_SET_MSK 0xffffffff
23521 #define ALT_GIC_DIST_GICD_ICFGR1_FLD_CLR_MSK 0x00000000
23523 #define ALT_GIC_DIST_GICD_ICFGR1_FLD_RESET 0x0
23525 #define ALT_GIC_DIST_GICD_ICFGR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23527 #define ALT_GIC_DIST_GICD_ICFGR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
23529 #ifndef __ASSEMBLY__
23541 struct ALT_GIC_DIST_GICD_ICFGR1_s
23543 volatile uint32_t fld : 32;
23547 typedef struct ALT_GIC_DIST_GICD_ICFGR1_s ALT_GIC_DIST_GICD_ICFGR1_t;
23551 #define ALT_GIC_DIST_GICD_ICFGR1_RESET 0x55540000
23553 #define ALT_GIC_DIST_GICD_ICFGR1_OFST 0xc04
23576 #define ALT_GIC_DIST_GICD_ICFGR2_FLD_LSB 0
23578 #define ALT_GIC_DIST_GICD_ICFGR2_FLD_MSB 31
23580 #define ALT_GIC_DIST_GICD_ICFGR2_FLD_WIDTH 32
23582 #define ALT_GIC_DIST_GICD_ICFGR2_FLD_SET_MSK 0xffffffff
23584 #define ALT_GIC_DIST_GICD_ICFGR2_FLD_CLR_MSK 0x00000000
23586 #define ALT_GIC_DIST_GICD_ICFGR2_FLD_RESET 0x55555555
23588 #define ALT_GIC_DIST_GICD_ICFGR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23590 #define ALT_GIC_DIST_GICD_ICFGR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
23592 #ifndef __ASSEMBLY__
23604 struct ALT_GIC_DIST_GICD_ICFGR2_s
23606 volatile uint32_t fld : 32;
23610 typedef struct ALT_GIC_DIST_GICD_ICFGR2_s ALT_GIC_DIST_GICD_ICFGR2_t;
23614 #define ALT_GIC_DIST_GICD_ICFGR2_RESET 0x55555555
23616 #define ALT_GIC_DIST_GICD_ICFGR2_OFST 0xc08
23639 #define ALT_GIC_DIST_GICD_ICFGR3_FLD_LSB 0
23641 #define ALT_GIC_DIST_GICD_ICFGR3_FLD_MSB 31
23643 #define ALT_GIC_DIST_GICD_ICFGR3_FLD_WIDTH 32
23645 #define ALT_GIC_DIST_GICD_ICFGR3_FLD_SET_MSK 0xffffffff
23647 #define ALT_GIC_DIST_GICD_ICFGR3_FLD_CLR_MSK 0x00000000
23649 #define ALT_GIC_DIST_GICD_ICFGR3_FLD_RESET 0x55555555
23651 #define ALT_GIC_DIST_GICD_ICFGR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23653 #define ALT_GIC_DIST_GICD_ICFGR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
23655 #ifndef __ASSEMBLY__
23667 struct ALT_GIC_DIST_GICD_ICFGR3_s
23669 volatile uint32_t fld : 32;
23673 typedef struct ALT_GIC_DIST_GICD_ICFGR3_s ALT_GIC_DIST_GICD_ICFGR3_t;
23677 #define ALT_GIC_DIST_GICD_ICFGR3_RESET 0x55555555
23679 #define ALT_GIC_DIST_GICD_ICFGR3_OFST 0xc0c
23702 #define ALT_GIC_DIST_GICD_ICFGR4_FLD_LSB 0
23704 #define ALT_GIC_DIST_GICD_ICFGR4_FLD_MSB 31
23706 #define ALT_GIC_DIST_GICD_ICFGR4_FLD_WIDTH 32
23708 #define ALT_GIC_DIST_GICD_ICFGR4_FLD_SET_MSK 0xffffffff
23710 #define ALT_GIC_DIST_GICD_ICFGR4_FLD_CLR_MSK 0x00000000
23712 #define ALT_GIC_DIST_GICD_ICFGR4_FLD_RESET 0x55555555
23714 #define ALT_GIC_DIST_GICD_ICFGR4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23716 #define ALT_GIC_DIST_GICD_ICFGR4_FLD_SET(value) (((value) << 0) & 0xffffffff)
23718 #ifndef __ASSEMBLY__
23730 struct ALT_GIC_DIST_GICD_ICFGR4_s
23732 volatile uint32_t fld : 32;
23736 typedef struct ALT_GIC_DIST_GICD_ICFGR4_s ALT_GIC_DIST_GICD_ICFGR4_t;
23740 #define ALT_GIC_DIST_GICD_ICFGR4_RESET 0x55555555
23742 #define ALT_GIC_DIST_GICD_ICFGR4_OFST 0xc10
23765 #define ALT_GIC_DIST_GICD_ICFGR5_FLD_LSB 0
23767 #define ALT_GIC_DIST_GICD_ICFGR5_FLD_MSB 31
23769 #define ALT_GIC_DIST_GICD_ICFGR5_FLD_WIDTH 32
23771 #define ALT_GIC_DIST_GICD_ICFGR5_FLD_SET_MSK 0xffffffff
23773 #define ALT_GIC_DIST_GICD_ICFGR5_FLD_CLR_MSK 0x00000000
23775 #define ALT_GIC_DIST_GICD_ICFGR5_FLD_RESET 0x55555555
23777 #define ALT_GIC_DIST_GICD_ICFGR5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23779 #define ALT_GIC_DIST_GICD_ICFGR5_FLD_SET(value) (((value) << 0) & 0xffffffff)
23781 #ifndef __ASSEMBLY__
23793 struct ALT_GIC_DIST_GICD_ICFGR5_s
23795 volatile uint32_t fld : 32;
23799 typedef struct ALT_GIC_DIST_GICD_ICFGR5_s ALT_GIC_DIST_GICD_ICFGR5_t;
23803 #define ALT_GIC_DIST_GICD_ICFGR5_RESET 0x55555555
23805 #define ALT_GIC_DIST_GICD_ICFGR5_OFST 0xc14
23828 #define ALT_GIC_DIST_GICD_ICFGR6_FLD_LSB 0
23830 #define ALT_GIC_DIST_GICD_ICFGR6_FLD_MSB 31
23832 #define ALT_GIC_DIST_GICD_ICFGR6_FLD_WIDTH 32
23834 #define ALT_GIC_DIST_GICD_ICFGR6_FLD_SET_MSK 0xffffffff
23836 #define ALT_GIC_DIST_GICD_ICFGR6_FLD_CLR_MSK 0x00000000
23838 #define ALT_GIC_DIST_GICD_ICFGR6_FLD_RESET 0x55555555
23840 #define ALT_GIC_DIST_GICD_ICFGR6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23842 #define ALT_GIC_DIST_GICD_ICFGR6_FLD_SET(value) (((value) << 0) & 0xffffffff)
23844 #ifndef __ASSEMBLY__
23856 struct ALT_GIC_DIST_GICD_ICFGR6_s
23858 volatile uint32_t fld : 32;
23862 typedef struct ALT_GIC_DIST_GICD_ICFGR6_s ALT_GIC_DIST_GICD_ICFGR6_t;
23866 #define ALT_GIC_DIST_GICD_ICFGR6_RESET 0x55555555
23868 #define ALT_GIC_DIST_GICD_ICFGR6_OFST 0xc18
23891 #define ALT_GIC_DIST_GICD_ICFGR7_FLD_LSB 0
23893 #define ALT_GIC_DIST_GICD_ICFGR7_FLD_MSB 31
23895 #define ALT_GIC_DIST_GICD_ICFGR7_FLD_WIDTH 32
23897 #define ALT_GIC_DIST_GICD_ICFGR7_FLD_SET_MSK 0xffffffff
23899 #define ALT_GIC_DIST_GICD_ICFGR7_FLD_CLR_MSK 0x00000000
23901 #define ALT_GIC_DIST_GICD_ICFGR7_FLD_RESET 0x55555555
23903 #define ALT_GIC_DIST_GICD_ICFGR7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23905 #define ALT_GIC_DIST_GICD_ICFGR7_FLD_SET(value) (((value) << 0) & 0xffffffff)
23907 #ifndef __ASSEMBLY__
23919 struct ALT_GIC_DIST_GICD_ICFGR7_s
23921 volatile uint32_t fld : 32;
23925 typedef struct ALT_GIC_DIST_GICD_ICFGR7_s ALT_GIC_DIST_GICD_ICFGR7_t;
23929 #define ALT_GIC_DIST_GICD_ICFGR7_RESET 0x55555555
23931 #define ALT_GIC_DIST_GICD_ICFGR7_OFST 0xc1c
23954 #define ALT_GIC_DIST_GICD_ICFGR8_FLD_LSB 0
23956 #define ALT_GIC_DIST_GICD_ICFGR8_FLD_MSB 31
23958 #define ALT_GIC_DIST_GICD_ICFGR8_FLD_WIDTH 32
23960 #define ALT_GIC_DIST_GICD_ICFGR8_FLD_SET_MSK 0xffffffff
23962 #define ALT_GIC_DIST_GICD_ICFGR8_FLD_CLR_MSK 0x00000000
23964 #define ALT_GIC_DIST_GICD_ICFGR8_FLD_RESET 0x55555555
23966 #define ALT_GIC_DIST_GICD_ICFGR8_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23968 #define ALT_GIC_DIST_GICD_ICFGR8_FLD_SET(value) (((value) << 0) & 0xffffffff)
23970 #ifndef __ASSEMBLY__
23982 struct ALT_GIC_DIST_GICD_ICFGR8_s
23984 volatile uint32_t fld : 32;
23988 typedef struct ALT_GIC_DIST_GICD_ICFGR8_s ALT_GIC_DIST_GICD_ICFGR8_t;
23992 #define ALT_GIC_DIST_GICD_ICFGR8_RESET 0x55555555
23994 #define ALT_GIC_DIST_GICD_ICFGR8_OFST 0xc20
24017 #define ALT_GIC_DIST_GICD_ICFGR9_FLD_LSB 0
24019 #define ALT_GIC_DIST_GICD_ICFGR9_FLD_MSB 31
24021 #define ALT_GIC_DIST_GICD_ICFGR9_FLD_WIDTH 32
24023 #define ALT_GIC_DIST_GICD_ICFGR9_FLD_SET_MSK 0xffffffff
24025 #define ALT_GIC_DIST_GICD_ICFGR9_FLD_CLR_MSK 0x00000000
24027 #define ALT_GIC_DIST_GICD_ICFGR9_FLD_RESET 0x55555555
24029 #define ALT_GIC_DIST_GICD_ICFGR9_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24031 #define ALT_GIC_DIST_GICD_ICFGR9_FLD_SET(value) (((value) << 0) & 0xffffffff)
24033 #ifndef __ASSEMBLY__
24045 struct ALT_GIC_DIST_GICD_ICFGR9_s
24047 volatile uint32_t fld : 32;
24051 typedef struct ALT_GIC_DIST_GICD_ICFGR9_s ALT_GIC_DIST_GICD_ICFGR9_t;
24055 #define ALT_GIC_DIST_GICD_ICFGR9_RESET 0x55555555
24057 #define ALT_GIC_DIST_GICD_ICFGR9_OFST 0xc24
24080 #define ALT_GIC_DIST_GICD_ICFGR10_FLD_LSB 0
24082 #define ALT_GIC_DIST_GICD_ICFGR10_FLD_MSB 31
24084 #define ALT_GIC_DIST_GICD_ICFGR10_FLD_WIDTH 32
24086 #define ALT_GIC_DIST_GICD_ICFGR10_FLD_SET_MSK 0xffffffff
24088 #define ALT_GIC_DIST_GICD_ICFGR10_FLD_CLR_MSK 0x00000000
24090 #define ALT_GIC_DIST_GICD_ICFGR10_FLD_RESET 0x55555555
24092 #define ALT_GIC_DIST_GICD_ICFGR10_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24094 #define ALT_GIC_DIST_GICD_ICFGR10_FLD_SET(value) (((value) << 0) & 0xffffffff)
24096 #ifndef __ASSEMBLY__
24108 struct ALT_GIC_DIST_GICD_ICFGR10_s
24110 volatile uint32_t fld : 32;
24114 typedef struct ALT_GIC_DIST_GICD_ICFGR10_s ALT_GIC_DIST_GICD_ICFGR10_t;
24118 #define ALT_GIC_DIST_GICD_ICFGR10_RESET 0x55555555
24120 #define ALT_GIC_DIST_GICD_ICFGR10_OFST 0xc28
24143 #define ALT_GIC_DIST_GICD_ICFGR11_FLD_LSB 0
24145 #define ALT_GIC_DIST_GICD_ICFGR11_FLD_MSB 31
24147 #define ALT_GIC_DIST_GICD_ICFGR11_FLD_WIDTH 32
24149 #define ALT_GIC_DIST_GICD_ICFGR11_FLD_SET_MSK 0xffffffff
24151 #define ALT_GIC_DIST_GICD_ICFGR11_FLD_CLR_MSK 0x00000000
24153 #define ALT_GIC_DIST_GICD_ICFGR11_FLD_RESET 0x55555555
24155 #define ALT_GIC_DIST_GICD_ICFGR11_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24157 #define ALT_GIC_DIST_GICD_ICFGR11_FLD_SET(value) (((value) << 0) & 0xffffffff)
24159 #ifndef __ASSEMBLY__
24171 struct ALT_GIC_DIST_GICD_ICFGR11_s
24173 volatile uint32_t fld : 32;
24177 typedef struct ALT_GIC_DIST_GICD_ICFGR11_s ALT_GIC_DIST_GICD_ICFGR11_t;
24181 #define ALT_GIC_DIST_GICD_ICFGR11_RESET 0x55555555
24183 #define ALT_GIC_DIST_GICD_ICFGR11_OFST 0xc2c
24206 #define ALT_GIC_DIST_GICD_ICFGR12_FLD_LSB 0
24208 #define ALT_GIC_DIST_GICD_ICFGR12_FLD_MSB 31
24210 #define ALT_GIC_DIST_GICD_ICFGR12_FLD_WIDTH 32
24212 #define ALT_GIC_DIST_GICD_ICFGR12_FLD_SET_MSK 0xffffffff
24214 #define ALT_GIC_DIST_GICD_ICFGR12_FLD_CLR_MSK 0x00000000
24216 #define ALT_GIC_DIST_GICD_ICFGR12_FLD_RESET 0x55555555
24218 #define ALT_GIC_DIST_GICD_ICFGR12_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24220 #define ALT_GIC_DIST_GICD_ICFGR12_FLD_SET(value) (((value) << 0) & 0xffffffff)
24222 #ifndef __ASSEMBLY__
24234 struct ALT_GIC_DIST_GICD_ICFGR12_s
24236 volatile uint32_t fld : 32;
24240 typedef struct ALT_GIC_DIST_GICD_ICFGR12_s ALT_GIC_DIST_GICD_ICFGR12_t;
24244 #define ALT_GIC_DIST_GICD_ICFGR12_RESET 0x55555555
24246 #define ALT_GIC_DIST_GICD_ICFGR12_OFST 0xc30
24269 #define ALT_GIC_DIST_GICD_ICFGR13_FLD_LSB 0
24271 #define ALT_GIC_DIST_GICD_ICFGR13_FLD_MSB 31
24273 #define ALT_GIC_DIST_GICD_ICFGR13_FLD_WIDTH 32
24275 #define ALT_GIC_DIST_GICD_ICFGR13_FLD_SET_MSK 0xffffffff
24277 #define ALT_GIC_DIST_GICD_ICFGR13_FLD_CLR_MSK 0x00000000
24279 #define ALT_GIC_DIST_GICD_ICFGR13_FLD_RESET 0x55555555
24281 #define ALT_GIC_DIST_GICD_ICFGR13_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24283 #define ALT_GIC_DIST_GICD_ICFGR13_FLD_SET(value) (((value) << 0) & 0xffffffff)
24285 #ifndef __ASSEMBLY__
24297 struct ALT_GIC_DIST_GICD_ICFGR13_s
24299 volatile uint32_t fld : 32;
24303 typedef struct ALT_GIC_DIST_GICD_ICFGR13_s ALT_GIC_DIST_GICD_ICFGR13_t;
24307 #define ALT_GIC_DIST_GICD_ICFGR13_RESET 0x55555555
24309 #define ALT_GIC_DIST_GICD_ICFGR13_OFST 0xc34
24332 #define ALT_GIC_DIST_GICD_ICFGR14_FLD_LSB 0
24334 #define ALT_GIC_DIST_GICD_ICFGR14_FLD_MSB 31
24336 #define ALT_GIC_DIST_GICD_ICFGR14_FLD_WIDTH 32
24338 #define ALT_GIC_DIST_GICD_ICFGR14_FLD_SET_MSK 0xffffffff
24340 #define ALT_GIC_DIST_GICD_ICFGR14_FLD_CLR_MSK 0x00000000
24342 #define ALT_GIC_DIST_GICD_ICFGR14_FLD_RESET 0x55555555
24344 #define ALT_GIC_DIST_GICD_ICFGR14_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24346 #define ALT_GIC_DIST_GICD_ICFGR14_FLD_SET(value) (((value) << 0) & 0xffffffff)
24348 #ifndef __ASSEMBLY__
24360 struct ALT_GIC_DIST_GICD_ICFGR14_s
24362 volatile uint32_t fld : 32;
24366 typedef struct ALT_GIC_DIST_GICD_ICFGR14_s ALT_GIC_DIST_GICD_ICFGR14_t;
24370 #define ALT_GIC_DIST_GICD_ICFGR14_RESET 0x55555555
24372 #define ALT_GIC_DIST_GICD_ICFGR14_OFST 0xc38
24395 #define ALT_GIC_DIST_GICD_ICFGR15_FLD_LSB 0
24397 #define ALT_GIC_DIST_GICD_ICFGR15_FLD_MSB 31
24399 #define ALT_GIC_DIST_GICD_ICFGR15_FLD_WIDTH 32
24401 #define ALT_GIC_DIST_GICD_ICFGR15_FLD_SET_MSK 0xffffffff
24403 #define ALT_GIC_DIST_GICD_ICFGR15_FLD_CLR_MSK 0x00000000
24405 #define ALT_GIC_DIST_GICD_ICFGR15_FLD_RESET 0x55555555
24407 #define ALT_GIC_DIST_GICD_ICFGR15_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24409 #define ALT_GIC_DIST_GICD_ICFGR15_FLD_SET(value) (((value) << 0) & 0xffffffff)
24411 #ifndef __ASSEMBLY__
24423 struct ALT_GIC_DIST_GICD_ICFGR15_s
24425 volatile uint32_t fld : 32;
24429 typedef struct ALT_GIC_DIST_GICD_ICFGR15_s ALT_GIC_DIST_GICD_ICFGR15_t;
24433 #define ALT_GIC_DIST_GICD_ICFGR15_RESET 0x55555555
24435 #define ALT_GIC_DIST_GICD_ICFGR15_OFST 0xc3c
24458 #define ALT_GIC_DIST_GICD_ICFGR16_FLD_LSB 0
24460 #define ALT_GIC_DIST_GICD_ICFGR16_FLD_MSB 31
24462 #define ALT_GIC_DIST_GICD_ICFGR16_FLD_WIDTH 32
24464 #define ALT_GIC_DIST_GICD_ICFGR16_FLD_SET_MSK 0xffffffff
24466 #define ALT_GIC_DIST_GICD_ICFGR16_FLD_CLR_MSK 0x00000000
24468 #define ALT_GIC_DIST_GICD_ICFGR16_FLD_RESET 0x55555555
24470 #define ALT_GIC_DIST_GICD_ICFGR16_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24472 #define ALT_GIC_DIST_GICD_ICFGR16_FLD_SET(value) (((value) << 0) & 0xffffffff)
24474 #ifndef __ASSEMBLY__
24486 struct ALT_GIC_DIST_GICD_ICFGR16_s
24488 volatile uint32_t fld : 32;
24492 typedef struct ALT_GIC_DIST_GICD_ICFGR16_s ALT_GIC_DIST_GICD_ICFGR16_t;
24496 #define ALT_GIC_DIST_GICD_ICFGR16_RESET 0x55555555
24498 #define ALT_GIC_DIST_GICD_ICFGR16_OFST 0xc40
24521 #define ALT_GIC_DIST_GICD_ICFGR17_FLD_LSB 0
24523 #define ALT_GIC_DIST_GICD_ICFGR17_FLD_MSB 31
24525 #define ALT_GIC_DIST_GICD_ICFGR17_FLD_WIDTH 32
24527 #define ALT_GIC_DIST_GICD_ICFGR17_FLD_SET_MSK 0xffffffff
24529 #define ALT_GIC_DIST_GICD_ICFGR17_FLD_CLR_MSK 0x00000000
24531 #define ALT_GIC_DIST_GICD_ICFGR17_FLD_RESET 0x55555555
24533 #define ALT_GIC_DIST_GICD_ICFGR17_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24535 #define ALT_GIC_DIST_GICD_ICFGR17_FLD_SET(value) (((value) << 0) & 0xffffffff)
24537 #ifndef __ASSEMBLY__
24549 struct ALT_GIC_DIST_GICD_ICFGR17_s
24551 volatile uint32_t fld : 32;
24555 typedef struct ALT_GIC_DIST_GICD_ICFGR17_s ALT_GIC_DIST_GICD_ICFGR17_t;
24559 #define ALT_GIC_DIST_GICD_ICFGR17_RESET 0x55555555
24561 #define ALT_GIC_DIST_GICD_ICFGR17_OFST 0xc44
24584 #define ALT_GIC_DIST_GICD_ICFGR18_FLD_LSB 0
24586 #define ALT_GIC_DIST_GICD_ICFGR18_FLD_MSB 31
24588 #define ALT_GIC_DIST_GICD_ICFGR18_FLD_WIDTH 32
24590 #define ALT_GIC_DIST_GICD_ICFGR18_FLD_SET_MSK 0xffffffff
24592 #define ALT_GIC_DIST_GICD_ICFGR18_FLD_CLR_MSK 0x00000000
24594 #define ALT_GIC_DIST_GICD_ICFGR18_FLD_RESET 0x55555555
24596 #define ALT_GIC_DIST_GICD_ICFGR18_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24598 #define ALT_GIC_DIST_GICD_ICFGR18_FLD_SET(value) (((value) << 0) & 0xffffffff)
24600 #ifndef __ASSEMBLY__
24612 struct ALT_GIC_DIST_GICD_ICFGR18_s
24614 volatile uint32_t fld : 32;
24618 typedef struct ALT_GIC_DIST_GICD_ICFGR18_s ALT_GIC_DIST_GICD_ICFGR18_t;
24622 #define ALT_GIC_DIST_GICD_ICFGR18_RESET 0x55555555
24624 #define ALT_GIC_DIST_GICD_ICFGR18_OFST 0xc48
24647 #define ALT_GIC_DIST_GICD_ICFGR19_FLD_LSB 0
24649 #define ALT_GIC_DIST_GICD_ICFGR19_FLD_MSB 31
24651 #define ALT_GIC_DIST_GICD_ICFGR19_FLD_WIDTH 32
24653 #define ALT_GIC_DIST_GICD_ICFGR19_FLD_SET_MSK 0xffffffff
24655 #define ALT_GIC_DIST_GICD_ICFGR19_FLD_CLR_MSK 0x00000000
24657 #define ALT_GIC_DIST_GICD_ICFGR19_FLD_RESET 0x55555555
24659 #define ALT_GIC_DIST_GICD_ICFGR19_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24661 #define ALT_GIC_DIST_GICD_ICFGR19_FLD_SET(value) (((value) << 0) & 0xffffffff)
24663 #ifndef __ASSEMBLY__
24675 struct ALT_GIC_DIST_GICD_ICFGR19_s
24677 volatile uint32_t fld : 32;
24681 typedef struct ALT_GIC_DIST_GICD_ICFGR19_s ALT_GIC_DIST_GICD_ICFGR19_t;
24685 #define ALT_GIC_DIST_GICD_ICFGR19_RESET 0x55555555
24687 #define ALT_GIC_DIST_GICD_ICFGR19_OFST 0xc4c
24710 #define ALT_GIC_DIST_GICD_ICFGR20_FLD_LSB 0
24712 #define ALT_GIC_DIST_GICD_ICFGR20_FLD_MSB 31
24714 #define ALT_GIC_DIST_GICD_ICFGR20_FLD_WIDTH 32
24716 #define ALT_GIC_DIST_GICD_ICFGR20_FLD_SET_MSK 0xffffffff
24718 #define ALT_GIC_DIST_GICD_ICFGR20_FLD_CLR_MSK 0x00000000
24720 #define ALT_GIC_DIST_GICD_ICFGR20_FLD_RESET 0x55555555
24722 #define ALT_GIC_DIST_GICD_ICFGR20_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24724 #define ALT_GIC_DIST_GICD_ICFGR20_FLD_SET(value) (((value) << 0) & 0xffffffff)
24726 #ifndef __ASSEMBLY__
24738 struct ALT_GIC_DIST_GICD_ICFGR20_s
24740 volatile uint32_t fld : 32;
24744 typedef struct ALT_GIC_DIST_GICD_ICFGR20_s ALT_GIC_DIST_GICD_ICFGR20_t;
24748 #define ALT_GIC_DIST_GICD_ICFGR20_RESET 0x55555555
24750 #define ALT_GIC_DIST_GICD_ICFGR20_OFST 0xc50
24773 #define ALT_GIC_DIST_GICD_ICFGR21_FLD_LSB 0
24775 #define ALT_GIC_DIST_GICD_ICFGR21_FLD_MSB 31
24777 #define ALT_GIC_DIST_GICD_ICFGR21_FLD_WIDTH 32
24779 #define ALT_GIC_DIST_GICD_ICFGR21_FLD_SET_MSK 0xffffffff
24781 #define ALT_GIC_DIST_GICD_ICFGR21_FLD_CLR_MSK 0x00000000
24783 #define ALT_GIC_DIST_GICD_ICFGR21_FLD_RESET 0x55555555
24785 #define ALT_GIC_DIST_GICD_ICFGR21_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24787 #define ALT_GIC_DIST_GICD_ICFGR21_FLD_SET(value) (((value) << 0) & 0xffffffff)
24789 #ifndef __ASSEMBLY__
24801 struct ALT_GIC_DIST_GICD_ICFGR21_s
24803 volatile uint32_t fld : 32;
24807 typedef struct ALT_GIC_DIST_GICD_ICFGR21_s ALT_GIC_DIST_GICD_ICFGR21_t;
24811 #define ALT_GIC_DIST_GICD_ICFGR21_RESET 0x55555555
24813 #define ALT_GIC_DIST_GICD_ICFGR21_OFST 0xc54
24836 #define ALT_GIC_DIST_GICD_ICFGR22_FLD_LSB 0
24838 #define ALT_GIC_DIST_GICD_ICFGR22_FLD_MSB 31
24840 #define ALT_GIC_DIST_GICD_ICFGR22_FLD_WIDTH 32
24842 #define ALT_GIC_DIST_GICD_ICFGR22_FLD_SET_MSK 0xffffffff
24844 #define ALT_GIC_DIST_GICD_ICFGR22_FLD_CLR_MSK 0x00000000
24846 #define ALT_GIC_DIST_GICD_ICFGR22_FLD_RESET 0x55555555
24848 #define ALT_GIC_DIST_GICD_ICFGR22_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24850 #define ALT_GIC_DIST_GICD_ICFGR22_FLD_SET(value) (((value) << 0) & 0xffffffff)
24852 #ifndef __ASSEMBLY__
24864 struct ALT_GIC_DIST_GICD_ICFGR22_s
24866 volatile uint32_t fld : 32;
24870 typedef struct ALT_GIC_DIST_GICD_ICFGR22_s ALT_GIC_DIST_GICD_ICFGR22_t;
24874 #define ALT_GIC_DIST_GICD_ICFGR22_RESET 0x55555555
24876 #define ALT_GIC_DIST_GICD_ICFGR22_OFST 0xc58
24899 #define ALT_GIC_DIST_GICD_ICFGR23_FLD_LSB 0
24901 #define ALT_GIC_DIST_GICD_ICFGR23_FLD_MSB 31
24903 #define ALT_GIC_DIST_GICD_ICFGR23_FLD_WIDTH 32
24905 #define ALT_GIC_DIST_GICD_ICFGR23_FLD_SET_MSK 0xffffffff
24907 #define ALT_GIC_DIST_GICD_ICFGR23_FLD_CLR_MSK 0x00000000
24909 #define ALT_GIC_DIST_GICD_ICFGR23_FLD_RESET 0x55555555
24911 #define ALT_GIC_DIST_GICD_ICFGR23_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24913 #define ALT_GIC_DIST_GICD_ICFGR23_FLD_SET(value) (((value) << 0) & 0xffffffff)
24915 #ifndef __ASSEMBLY__
24927 struct ALT_GIC_DIST_GICD_ICFGR23_s
24929 volatile uint32_t fld : 32;
24933 typedef struct ALT_GIC_DIST_GICD_ICFGR23_s ALT_GIC_DIST_GICD_ICFGR23_t;
24937 #define ALT_GIC_DIST_GICD_ICFGR23_RESET 0x55555555
24939 #define ALT_GIC_DIST_GICD_ICFGR23_OFST 0xc5c
24962 #define ALT_GIC_DIST_GICD_ICFGR24_FLD_LSB 0
24964 #define ALT_GIC_DIST_GICD_ICFGR24_FLD_MSB 31
24966 #define ALT_GIC_DIST_GICD_ICFGR24_FLD_WIDTH 32
24968 #define ALT_GIC_DIST_GICD_ICFGR24_FLD_SET_MSK 0xffffffff
24970 #define ALT_GIC_DIST_GICD_ICFGR24_FLD_CLR_MSK 0x00000000
24972 #define ALT_GIC_DIST_GICD_ICFGR24_FLD_RESET 0x55555555
24974 #define ALT_GIC_DIST_GICD_ICFGR24_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24976 #define ALT_GIC_DIST_GICD_ICFGR24_FLD_SET(value) (((value) << 0) & 0xffffffff)
24978 #ifndef __ASSEMBLY__
24990 struct ALT_GIC_DIST_GICD_ICFGR24_s
24992 volatile uint32_t fld : 32;
24996 typedef struct ALT_GIC_DIST_GICD_ICFGR24_s ALT_GIC_DIST_GICD_ICFGR24_t;
25000 #define ALT_GIC_DIST_GICD_ICFGR24_RESET 0x55555555
25002 #define ALT_GIC_DIST_GICD_ICFGR24_OFST 0xc60
25025 #define ALT_GIC_DIST_GICD_ICFGR25_FLD_LSB 0
25027 #define ALT_GIC_DIST_GICD_ICFGR25_FLD_MSB 31
25029 #define ALT_GIC_DIST_GICD_ICFGR25_FLD_WIDTH 32
25031 #define ALT_GIC_DIST_GICD_ICFGR25_FLD_SET_MSK 0xffffffff
25033 #define ALT_GIC_DIST_GICD_ICFGR25_FLD_CLR_MSK 0x00000000
25035 #define ALT_GIC_DIST_GICD_ICFGR25_FLD_RESET 0x55555555
25037 #define ALT_GIC_DIST_GICD_ICFGR25_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25039 #define ALT_GIC_DIST_GICD_ICFGR25_FLD_SET(value) (((value) << 0) & 0xffffffff)
25041 #ifndef __ASSEMBLY__
25053 struct ALT_GIC_DIST_GICD_ICFGR25_s
25055 volatile uint32_t fld : 32;
25059 typedef struct ALT_GIC_DIST_GICD_ICFGR25_s ALT_GIC_DIST_GICD_ICFGR25_t;
25063 #define ALT_GIC_DIST_GICD_ICFGR25_RESET 0x55555555
25065 #define ALT_GIC_DIST_GICD_ICFGR25_OFST 0xc64
25088 #define ALT_GIC_DIST_GICD_ICFGR26_FLD_LSB 0
25090 #define ALT_GIC_DIST_GICD_ICFGR26_FLD_MSB 31
25092 #define ALT_GIC_DIST_GICD_ICFGR26_FLD_WIDTH 32
25094 #define ALT_GIC_DIST_GICD_ICFGR26_FLD_SET_MSK 0xffffffff
25096 #define ALT_GIC_DIST_GICD_ICFGR26_FLD_CLR_MSK 0x00000000
25098 #define ALT_GIC_DIST_GICD_ICFGR26_FLD_RESET 0x55555555
25100 #define ALT_GIC_DIST_GICD_ICFGR26_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25102 #define ALT_GIC_DIST_GICD_ICFGR26_FLD_SET(value) (((value) << 0) & 0xffffffff)
25104 #ifndef __ASSEMBLY__
25116 struct ALT_GIC_DIST_GICD_ICFGR26_s
25118 volatile uint32_t fld : 32;
25122 typedef struct ALT_GIC_DIST_GICD_ICFGR26_s ALT_GIC_DIST_GICD_ICFGR26_t;
25126 #define ALT_GIC_DIST_GICD_ICFGR26_RESET 0x55555555
25128 #define ALT_GIC_DIST_GICD_ICFGR26_OFST 0xc68
25151 #define ALT_GIC_DIST_GICD_ICFGR27_FLD_LSB 0
25153 #define ALT_GIC_DIST_GICD_ICFGR27_FLD_MSB 31
25155 #define ALT_GIC_DIST_GICD_ICFGR27_FLD_WIDTH 32
25157 #define ALT_GIC_DIST_GICD_ICFGR27_FLD_SET_MSK 0xffffffff
25159 #define ALT_GIC_DIST_GICD_ICFGR27_FLD_CLR_MSK 0x00000000
25161 #define ALT_GIC_DIST_GICD_ICFGR27_FLD_RESET 0x55555555
25163 #define ALT_GIC_DIST_GICD_ICFGR27_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25165 #define ALT_GIC_DIST_GICD_ICFGR27_FLD_SET(value) (((value) << 0) & 0xffffffff)
25167 #ifndef __ASSEMBLY__
25179 struct ALT_GIC_DIST_GICD_ICFGR27_s
25181 volatile uint32_t fld : 32;
25185 typedef struct ALT_GIC_DIST_GICD_ICFGR27_s ALT_GIC_DIST_GICD_ICFGR27_t;
25189 #define ALT_GIC_DIST_GICD_ICFGR27_RESET 0x55555555
25191 #define ALT_GIC_DIST_GICD_ICFGR27_OFST 0xc6c
25214 #define ALT_GIC_DIST_GICD_ICFGR28_FLD_LSB 0
25216 #define ALT_GIC_DIST_GICD_ICFGR28_FLD_MSB 31
25218 #define ALT_GIC_DIST_GICD_ICFGR28_FLD_WIDTH 32
25220 #define ALT_GIC_DIST_GICD_ICFGR28_FLD_SET_MSK 0xffffffff
25222 #define ALT_GIC_DIST_GICD_ICFGR28_FLD_CLR_MSK 0x00000000
25224 #define ALT_GIC_DIST_GICD_ICFGR28_FLD_RESET 0x55555555
25226 #define ALT_GIC_DIST_GICD_ICFGR28_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25228 #define ALT_GIC_DIST_GICD_ICFGR28_FLD_SET(value) (((value) << 0) & 0xffffffff)
25230 #ifndef __ASSEMBLY__
25242 struct ALT_GIC_DIST_GICD_ICFGR28_s
25244 volatile uint32_t fld : 32;
25248 typedef struct ALT_GIC_DIST_GICD_ICFGR28_s ALT_GIC_DIST_GICD_ICFGR28_t;
25252 #define ALT_GIC_DIST_GICD_ICFGR28_RESET 0x55555555
25254 #define ALT_GIC_DIST_GICD_ICFGR28_OFST 0xc70
25277 #define ALT_GIC_DIST_GICD_ICFGR29_FLD_LSB 0
25279 #define ALT_GIC_DIST_GICD_ICFGR29_FLD_MSB 31
25281 #define ALT_GIC_DIST_GICD_ICFGR29_FLD_WIDTH 32
25283 #define ALT_GIC_DIST_GICD_ICFGR29_FLD_SET_MSK 0xffffffff
25285 #define ALT_GIC_DIST_GICD_ICFGR29_FLD_CLR_MSK 0x00000000
25287 #define ALT_GIC_DIST_GICD_ICFGR29_FLD_RESET 0x55555555
25289 #define ALT_GIC_DIST_GICD_ICFGR29_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25291 #define ALT_GIC_DIST_GICD_ICFGR29_FLD_SET(value) (((value) << 0) & 0xffffffff)
25293 #ifndef __ASSEMBLY__
25305 struct ALT_GIC_DIST_GICD_ICFGR29_s
25307 volatile uint32_t fld : 32;
25311 typedef struct ALT_GIC_DIST_GICD_ICFGR29_s ALT_GIC_DIST_GICD_ICFGR29_t;
25315 #define ALT_GIC_DIST_GICD_ICFGR29_RESET 0x55555555
25317 #define ALT_GIC_DIST_GICD_ICFGR29_OFST 0xc74
25340 #define ALT_GIC_DIST_GICD_ICFGR30_FLD_LSB 0
25342 #define ALT_GIC_DIST_GICD_ICFGR30_FLD_MSB 31
25344 #define ALT_GIC_DIST_GICD_ICFGR30_FLD_WIDTH 32
25346 #define ALT_GIC_DIST_GICD_ICFGR30_FLD_SET_MSK 0xffffffff
25348 #define ALT_GIC_DIST_GICD_ICFGR30_FLD_CLR_MSK 0x00000000
25350 #define ALT_GIC_DIST_GICD_ICFGR30_FLD_RESET 0x55555555
25352 #define ALT_GIC_DIST_GICD_ICFGR30_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25354 #define ALT_GIC_DIST_GICD_ICFGR30_FLD_SET(value) (((value) << 0) & 0xffffffff)
25356 #ifndef __ASSEMBLY__
25368 struct ALT_GIC_DIST_GICD_ICFGR30_s
25370 volatile uint32_t fld : 32;
25374 typedef struct ALT_GIC_DIST_GICD_ICFGR30_s ALT_GIC_DIST_GICD_ICFGR30_t;
25378 #define ALT_GIC_DIST_GICD_ICFGR30_RESET 0x55555555
25380 #define ALT_GIC_DIST_GICD_ICFGR30_OFST 0xc78
25403 #define ALT_GIC_DIST_GICD_ICFGR31_FLD_LSB 0
25405 #define ALT_GIC_DIST_GICD_ICFGR31_FLD_MSB 31
25407 #define ALT_GIC_DIST_GICD_ICFGR31_FLD_WIDTH 32
25409 #define ALT_GIC_DIST_GICD_ICFGR31_FLD_SET_MSK 0xffffffff
25411 #define ALT_GIC_DIST_GICD_ICFGR31_FLD_CLR_MSK 0x00000000
25413 #define ALT_GIC_DIST_GICD_ICFGR31_FLD_RESET 0x55555555
25415 #define ALT_GIC_DIST_GICD_ICFGR31_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25417 #define ALT_GIC_DIST_GICD_ICFGR31_FLD_SET(value) (((value) << 0) & 0xffffffff)
25419 #ifndef __ASSEMBLY__
25431 struct ALT_GIC_DIST_GICD_ICFGR31_s
25433 volatile uint32_t fld : 32;
25437 typedef struct ALT_GIC_DIST_GICD_ICFGR31_s ALT_GIC_DIST_GICD_ICFGR31_t;
25441 #define ALT_GIC_DIST_GICD_ICFGR31_RESET 0x55555555
25443 #define ALT_GIC_DIST_GICD_ICFGR31_OFST 0xc7c
25466 #define ALT_GIC_DIST_GICD_PPISR_FLD_LSB 0
25468 #define ALT_GIC_DIST_GICD_PPISR_FLD_MSB 31
25470 #define ALT_GIC_DIST_GICD_PPISR_FLD_WIDTH 32
25472 #define ALT_GIC_DIST_GICD_PPISR_FLD_SET_MSK 0xffffffff
25474 #define ALT_GIC_DIST_GICD_PPISR_FLD_CLR_MSK 0x00000000
25476 #define ALT_GIC_DIST_GICD_PPISR_FLD_RESET 0x0
25478 #define ALT_GIC_DIST_GICD_PPISR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25480 #define ALT_GIC_DIST_GICD_PPISR_FLD_SET(value) (((value) << 0) & 0xffffffff)
25482 #ifndef __ASSEMBLY__
25494 struct ALT_GIC_DIST_GICD_PPISR_s
25496 volatile uint32_t fld : 32;
25500 typedef struct ALT_GIC_DIST_GICD_PPISR_s ALT_GIC_DIST_GICD_PPISR_t;
25504 #define ALT_GIC_DIST_GICD_PPISR_RESET 0x00000000
25506 #define ALT_GIC_DIST_GICD_PPISR_OFST 0xd00
25529 #define ALT_GIC_DIST_GICD_SPISR0_FLD_LSB 0
25531 #define ALT_GIC_DIST_GICD_SPISR0_FLD_MSB 31
25533 #define ALT_GIC_DIST_GICD_SPISR0_FLD_WIDTH 32
25535 #define ALT_GIC_DIST_GICD_SPISR0_FLD_SET_MSK 0xffffffff
25537 #define ALT_GIC_DIST_GICD_SPISR0_FLD_CLR_MSK 0x00000000
25539 #define ALT_GIC_DIST_GICD_SPISR0_FLD_RESET 0x0
25541 #define ALT_GIC_DIST_GICD_SPISR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25543 #define ALT_GIC_DIST_GICD_SPISR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
25545 #ifndef __ASSEMBLY__
25557 struct ALT_GIC_DIST_GICD_SPISR0_s
25559 volatile uint32_t fld : 32;
25563 typedef struct ALT_GIC_DIST_GICD_SPISR0_s ALT_GIC_DIST_GICD_SPISR0_t;
25567 #define ALT_GIC_DIST_GICD_SPISR0_RESET 0x00000000
25569 #define ALT_GIC_DIST_GICD_SPISR0_OFST 0xd04
25592 #define ALT_GIC_DIST_GICD_SPISR1_FLD_LSB 0
25594 #define ALT_GIC_DIST_GICD_SPISR1_FLD_MSB 31
25596 #define ALT_GIC_DIST_GICD_SPISR1_FLD_WIDTH 32
25598 #define ALT_GIC_DIST_GICD_SPISR1_FLD_SET_MSK 0xffffffff
25600 #define ALT_GIC_DIST_GICD_SPISR1_FLD_CLR_MSK 0x00000000
25602 #define ALT_GIC_DIST_GICD_SPISR1_FLD_RESET 0x0
25604 #define ALT_GIC_DIST_GICD_SPISR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25606 #define ALT_GIC_DIST_GICD_SPISR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
25608 #ifndef __ASSEMBLY__
25620 struct ALT_GIC_DIST_GICD_SPISR1_s
25622 volatile uint32_t fld : 32;
25626 typedef struct ALT_GIC_DIST_GICD_SPISR1_s ALT_GIC_DIST_GICD_SPISR1_t;
25630 #define ALT_GIC_DIST_GICD_SPISR1_RESET 0x00000000
25632 #define ALT_GIC_DIST_GICD_SPISR1_OFST 0xd08
25655 #define ALT_GIC_DIST_GICD_SPISR2_FLD_LSB 0
25657 #define ALT_GIC_DIST_GICD_SPISR2_FLD_MSB 31
25659 #define ALT_GIC_DIST_GICD_SPISR2_FLD_WIDTH 32
25661 #define ALT_GIC_DIST_GICD_SPISR2_FLD_SET_MSK 0xffffffff
25663 #define ALT_GIC_DIST_GICD_SPISR2_FLD_CLR_MSK 0x00000000
25665 #define ALT_GIC_DIST_GICD_SPISR2_FLD_RESET 0x0
25667 #define ALT_GIC_DIST_GICD_SPISR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25669 #define ALT_GIC_DIST_GICD_SPISR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
25671 #ifndef __ASSEMBLY__
25683 struct ALT_GIC_DIST_GICD_SPISR2_s
25685 volatile uint32_t fld : 32;
25689 typedef struct ALT_GIC_DIST_GICD_SPISR2_s ALT_GIC_DIST_GICD_SPISR2_t;
25693 #define ALT_GIC_DIST_GICD_SPISR2_RESET 0x00000000
25695 #define ALT_GIC_DIST_GICD_SPISR2_OFST 0xd0c
25718 #define ALT_GIC_DIST_GICD_SPISR3_FLD_LSB 0
25720 #define ALT_GIC_DIST_GICD_SPISR3_FLD_MSB 31
25722 #define ALT_GIC_DIST_GICD_SPISR3_FLD_WIDTH 32
25724 #define ALT_GIC_DIST_GICD_SPISR3_FLD_SET_MSK 0xffffffff
25726 #define ALT_GIC_DIST_GICD_SPISR3_FLD_CLR_MSK 0x00000000
25728 #define ALT_GIC_DIST_GICD_SPISR3_FLD_RESET 0x0
25730 #define ALT_GIC_DIST_GICD_SPISR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25732 #define ALT_GIC_DIST_GICD_SPISR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
25734 #ifndef __ASSEMBLY__
25746 struct ALT_GIC_DIST_GICD_SPISR3_s
25748 volatile uint32_t fld : 32;
25752 typedef struct ALT_GIC_DIST_GICD_SPISR3_s ALT_GIC_DIST_GICD_SPISR3_t;
25756 #define ALT_GIC_DIST_GICD_SPISR3_RESET 0x00000000
25758 #define ALT_GIC_DIST_GICD_SPISR3_OFST 0xd10
25781 #define ALT_GIC_DIST_GICD_SPISR4_FLD_LSB 0
25783 #define ALT_GIC_DIST_GICD_SPISR4_FLD_MSB 31
25785 #define ALT_GIC_DIST_GICD_SPISR4_FLD_WIDTH 32
25787 #define ALT_GIC_DIST_GICD_SPISR4_FLD_SET_MSK 0xffffffff
25789 #define ALT_GIC_DIST_GICD_SPISR4_FLD_CLR_MSK 0x00000000
25791 #define ALT_GIC_DIST_GICD_SPISR4_FLD_RESET 0x0
25793 #define ALT_GIC_DIST_GICD_SPISR4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25795 #define ALT_GIC_DIST_GICD_SPISR4_FLD_SET(value) (((value) << 0) & 0xffffffff)
25797 #ifndef __ASSEMBLY__
25809 struct ALT_GIC_DIST_GICD_SPISR4_s
25811 volatile uint32_t fld : 32;
25815 typedef struct ALT_GIC_DIST_GICD_SPISR4_s ALT_GIC_DIST_GICD_SPISR4_t;
25819 #define ALT_GIC_DIST_GICD_SPISR4_RESET 0x00000000
25821 #define ALT_GIC_DIST_GICD_SPISR4_OFST 0xd14
25844 #define ALT_GIC_DIST_GICD_SPISR5_FLD_LSB 0
25846 #define ALT_GIC_DIST_GICD_SPISR5_FLD_MSB 31
25848 #define ALT_GIC_DIST_GICD_SPISR5_FLD_WIDTH 32
25850 #define ALT_GIC_DIST_GICD_SPISR5_FLD_SET_MSK 0xffffffff
25852 #define ALT_GIC_DIST_GICD_SPISR5_FLD_CLR_MSK 0x00000000
25854 #define ALT_GIC_DIST_GICD_SPISR5_FLD_RESET 0x0
25856 #define ALT_GIC_DIST_GICD_SPISR5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25858 #define ALT_GIC_DIST_GICD_SPISR5_FLD_SET(value) (((value) << 0) & 0xffffffff)
25860 #ifndef __ASSEMBLY__
25872 struct ALT_GIC_DIST_GICD_SPISR5_s
25874 volatile uint32_t fld : 32;
25878 typedef struct ALT_GIC_DIST_GICD_SPISR5_s ALT_GIC_DIST_GICD_SPISR5_t;
25882 #define ALT_GIC_DIST_GICD_SPISR5_RESET 0x00000000
25884 #define ALT_GIC_DIST_GICD_SPISR5_OFST 0xd18
25907 #define ALT_GIC_DIST_GICD_SPISR6_FLD_LSB 0
25909 #define ALT_GIC_DIST_GICD_SPISR6_FLD_MSB 31
25911 #define ALT_GIC_DIST_GICD_SPISR6_FLD_WIDTH 32
25913 #define ALT_GIC_DIST_GICD_SPISR6_FLD_SET_MSK 0xffffffff
25915 #define ALT_GIC_DIST_GICD_SPISR6_FLD_CLR_MSK 0x00000000
25917 #define ALT_GIC_DIST_GICD_SPISR6_FLD_RESET 0x0
25919 #define ALT_GIC_DIST_GICD_SPISR6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25921 #define ALT_GIC_DIST_GICD_SPISR6_FLD_SET(value) (((value) << 0) & 0xffffffff)
25923 #ifndef __ASSEMBLY__
25935 struct ALT_GIC_DIST_GICD_SPISR6_s
25937 volatile uint32_t fld : 32;
25941 typedef struct ALT_GIC_DIST_GICD_SPISR6_s ALT_GIC_DIST_GICD_SPISR6_t;
25945 #define ALT_GIC_DIST_GICD_SPISR6_RESET 0x00000000
25947 #define ALT_GIC_DIST_GICD_SPISR6_OFST 0xd1c
25970 #define ALT_GIC_DIST_GICD_SPISR7_FLD_LSB 0
25972 #define ALT_GIC_DIST_GICD_SPISR7_FLD_MSB 31
25974 #define ALT_GIC_DIST_GICD_SPISR7_FLD_WIDTH 32
25976 #define ALT_GIC_DIST_GICD_SPISR7_FLD_SET_MSK 0xffffffff
25978 #define ALT_GIC_DIST_GICD_SPISR7_FLD_CLR_MSK 0x00000000
25980 #define ALT_GIC_DIST_GICD_SPISR7_FLD_RESET 0x0
25982 #define ALT_GIC_DIST_GICD_SPISR7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25984 #define ALT_GIC_DIST_GICD_SPISR7_FLD_SET(value) (((value) << 0) & 0xffffffff)
25986 #ifndef __ASSEMBLY__
25998 struct ALT_GIC_DIST_GICD_SPISR7_s
26000 volatile uint32_t fld : 32;
26004 typedef struct ALT_GIC_DIST_GICD_SPISR7_s ALT_GIC_DIST_GICD_SPISR7_t;
26008 #define ALT_GIC_DIST_GICD_SPISR7_RESET 0x00000000
26010 #define ALT_GIC_DIST_GICD_SPISR7_OFST 0xd20
26033 #define ALT_GIC_DIST_GICD_SPISR8_FLD_LSB 0
26035 #define ALT_GIC_DIST_GICD_SPISR8_FLD_MSB 31
26037 #define ALT_GIC_DIST_GICD_SPISR8_FLD_WIDTH 32
26039 #define ALT_GIC_DIST_GICD_SPISR8_FLD_SET_MSK 0xffffffff
26041 #define ALT_GIC_DIST_GICD_SPISR8_FLD_CLR_MSK 0x00000000
26043 #define ALT_GIC_DIST_GICD_SPISR8_FLD_RESET 0x0
26045 #define ALT_GIC_DIST_GICD_SPISR8_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26047 #define ALT_GIC_DIST_GICD_SPISR8_FLD_SET(value) (((value) << 0) & 0xffffffff)
26049 #ifndef __ASSEMBLY__
26061 struct ALT_GIC_DIST_GICD_SPISR8_s
26063 volatile uint32_t fld : 32;
26067 typedef struct ALT_GIC_DIST_GICD_SPISR8_s ALT_GIC_DIST_GICD_SPISR8_t;
26071 #define ALT_GIC_DIST_GICD_SPISR8_RESET 0x00000000
26073 #define ALT_GIC_DIST_GICD_SPISR8_OFST 0xd24
26096 #define ALT_GIC_DIST_GICD_SPISR9_FLD_LSB 0
26098 #define ALT_GIC_DIST_GICD_SPISR9_FLD_MSB 31
26100 #define ALT_GIC_DIST_GICD_SPISR9_FLD_WIDTH 32
26102 #define ALT_GIC_DIST_GICD_SPISR9_FLD_SET_MSK 0xffffffff
26104 #define ALT_GIC_DIST_GICD_SPISR9_FLD_CLR_MSK 0x00000000
26106 #define ALT_GIC_DIST_GICD_SPISR9_FLD_RESET 0x0
26108 #define ALT_GIC_DIST_GICD_SPISR9_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26110 #define ALT_GIC_DIST_GICD_SPISR9_FLD_SET(value) (((value) << 0) & 0xffffffff)
26112 #ifndef __ASSEMBLY__
26124 struct ALT_GIC_DIST_GICD_SPISR9_s
26126 volatile uint32_t fld : 32;
26130 typedef struct ALT_GIC_DIST_GICD_SPISR9_s ALT_GIC_DIST_GICD_SPISR9_t;
26134 #define ALT_GIC_DIST_GICD_SPISR9_RESET 0x00000000
26136 #define ALT_GIC_DIST_GICD_SPISR9_OFST 0xd28
26159 #define ALT_GIC_DIST_GICD_SPISR10_FLD_LSB 0
26161 #define ALT_GIC_DIST_GICD_SPISR10_FLD_MSB 31
26163 #define ALT_GIC_DIST_GICD_SPISR10_FLD_WIDTH 32
26165 #define ALT_GIC_DIST_GICD_SPISR10_FLD_SET_MSK 0xffffffff
26167 #define ALT_GIC_DIST_GICD_SPISR10_FLD_CLR_MSK 0x00000000
26169 #define ALT_GIC_DIST_GICD_SPISR10_FLD_RESET 0x0
26171 #define ALT_GIC_DIST_GICD_SPISR10_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26173 #define ALT_GIC_DIST_GICD_SPISR10_FLD_SET(value) (((value) << 0) & 0xffffffff)
26175 #ifndef __ASSEMBLY__
26187 struct ALT_GIC_DIST_GICD_SPISR10_s
26189 volatile uint32_t fld : 32;
26193 typedef struct ALT_GIC_DIST_GICD_SPISR10_s ALT_GIC_DIST_GICD_SPISR10_t;
26197 #define ALT_GIC_DIST_GICD_SPISR10_RESET 0x00000000
26199 #define ALT_GIC_DIST_GICD_SPISR10_OFST 0xd2c
26222 #define ALT_GIC_DIST_GICD_SPISR11_FLD_LSB 0
26224 #define ALT_GIC_DIST_GICD_SPISR11_FLD_MSB 31
26226 #define ALT_GIC_DIST_GICD_SPISR11_FLD_WIDTH 32
26228 #define ALT_GIC_DIST_GICD_SPISR11_FLD_SET_MSK 0xffffffff
26230 #define ALT_GIC_DIST_GICD_SPISR11_FLD_CLR_MSK 0x00000000
26232 #define ALT_GIC_DIST_GICD_SPISR11_FLD_RESET 0x0
26234 #define ALT_GIC_DIST_GICD_SPISR11_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26236 #define ALT_GIC_DIST_GICD_SPISR11_FLD_SET(value) (((value) << 0) & 0xffffffff)
26238 #ifndef __ASSEMBLY__
26250 struct ALT_GIC_DIST_GICD_SPISR11_s
26252 volatile uint32_t fld : 32;
26256 typedef struct ALT_GIC_DIST_GICD_SPISR11_s ALT_GIC_DIST_GICD_SPISR11_t;
26260 #define ALT_GIC_DIST_GICD_SPISR11_RESET 0x00000000
26262 #define ALT_GIC_DIST_GICD_SPISR11_OFST 0xd30
26285 #define ALT_GIC_DIST_GICD_SPISR12_FLD_LSB 0
26287 #define ALT_GIC_DIST_GICD_SPISR12_FLD_MSB 31
26289 #define ALT_GIC_DIST_GICD_SPISR12_FLD_WIDTH 32
26291 #define ALT_GIC_DIST_GICD_SPISR12_FLD_SET_MSK 0xffffffff
26293 #define ALT_GIC_DIST_GICD_SPISR12_FLD_CLR_MSK 0x00000000
26295 #define ALT_GIC_DIST_GICD_SPISR12_FLD_RESET 0x0
26297 #define ALT_GIC_DIST_GICD_SPISR12_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26299 #define ALT_GIC_DIST_GICD_SPISR12_FLD_SET(value) (((value) << 0) & 0xffffffff)
26301 #ifndef __ASSEMBLY__
26313 struct ALT_GIC_DIST_GICD_SPISR12_s
26315 volatile uint32_t fld : 32;
26319 typedef struct ALT_GIC_DIST_GICD_SPISR12_s ALT_GIC_DIST_GICD_SPISR12_t;
26323 #define ALT_GIC_DIST_GICD_SPISR12_RESET 0x00000000
26325 #define ALT_GIC_DIST_GICD_SPISR12_OFST 0xd34
26348 #define ALT_GIC_DIST_GICD_SPISR13_FLD_LSB 0
26350 #define ALT_GIC_DIST_GICD_SPISR13_FLD_MSB 31
26352 #define ALT_GIC_DIST_GICD_SPISR13_FLD_WIDTH 32
26354 #define ALT_GIC_DIST_GICD_SPISR13_FLD_SET_MSK 0xffffffff
26356 #define ALT_GIC_DIST_GICD_SPISR13_FLD_CLR_MSK 0x00000000
26358 #define ALT_GIC_DIST_GICD_SPISR13_FLD_RESET 0x0
26360 #define ALT_GIC_DIST_GICD_SPISR13_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26362 #define ALT_GIC_DIST_GICD_SPISR13_FLD_SET(value) (((value) << 0) & 0xffffffff)
26364 #ifndef __ASSEMBLY__
26376 struct ALT_GIC_DIST_GICD_SPISR13_s
26378 volatile uint32_t fld : 32;
26382 typedef struct ALT_GIC_DIST_GICD_SPISR13_s ALT_GIC_DIST_GICD_SPISR13_t;
26386 #define ALT_GIC_DIST_GICD_SPISR13_RESET 0x00000000
26388 #define ALT_GIC_DIST_GICD_SPISR13_OFST 0xd38
26411 #define ALT_GIC_DIST_GICD_SPISR14_FLD_LSB 0
26413 #define ALT_GIC_DIST_GICD_SPISR14_FLD_MSB 31
26415 #define ALT_GIC_DIST_GICD_SPISR14_FLD_WIDTH 32
26417 #define ALT_GIC_DIST_GICD_SPISR14_FLD_SET_MSK 0xffffffff
26419 #define ALT_GIC_DIST_GICD_SPISR14_FLD_CLR_MSK 0x00000000
26421 #define ALT_GIC_DIST_GICD_SPISR14_FLD_RESET 0x0
26423 #define ALT_GIC_DIST_GICD_SPISR14_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26425 #define ALT_GIC_DIST_GICD_SPISR14_FLD_SET(value) (((value) << 0) & 0xffffffff)
26427 #ifndef __ASSEMBLY__
26439 struct ALT_GIC_DIST_GICD_SPISR14_s
26441 volatile uint32_t fld : 32;
26445 typedef struct ALT_GIC_DIST_GICD_SPISR14_s ALT_GIC_DIST_GICD_SPISR14_t;
26449 #define ALT_GIC_DIST_GICD_SPISR14_RESET 0x00000000
26451 #define ALT_GIC_DIST_GICD_SPISR14_OFST 0xd3c
26474 #define ALT_GIC_DIST_GICD_SGIR_FLD_LSB 0
26476 #define ALT_GIC_DIST_GICD_SGIR_FLD_MSB 31
26478 #define ALT_GIC_DIST_GICD_SGIR_FLD_WIDTH 32
26480 #define ALT_GIC_DIST_GICD_SGIR_FLD_SET_MSK 0xffffffff
26482 #define ALT_GIC_DIST_GICD_SGIR_FLD_CLR_MSK 0x00000000
26484 #define ALT_GIC_DIST_GICD_SGIR_FLD_RESET 0x0
26486 #define ALT_GIC_DIST_GICD_SGIR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26488 #define ALT_GIC_DIST_GICD_SGIR_FLD_SET(value) (((value) << 0) & 0xffffffff)
26490 #ifndef __ASSEMBLY__
26502 struct ALT_GIC_DIST_GICD_SGIR_s
26504 volatile uint32_t fld : 32;
26508 typedef struct ALT_GIC_DIST_GICD_SGIR_s ALT_GIC_DIST_GICD_SGIR_t;
26512 #define ALT_GIC_DIST_GICD_SGIR_RESET 0x00000000
26514 #define ALT_GIC_DIST_GICD_SGIR_OFST 0xf00
26537 #define ALT_GIC_DIST_GICD_CPENDSGIR0_FLD_LSB 0
26539 #define ALT_GIC_DIST_GICD_CPENDSGIR0_FLD_MSB 31
26541 #define ALT_GIC_DIST_GICD_CPENDSGIR0_FLD_WIDTH 32
26543 #define ALT_GIC_DIST_GICD_CPENDSGIR0_FLD_SET_MSK 0xffffffff
26545 #define ALT_GIC_DIST_GICD_CPENDSGIR0_FLD_CLR_MSK 0x00000000
26547 #define ALT_GIC_DIST_GICD_CPENDSGIR0_FLD_RESET 0x0
26549 #define ALT_GIC_DIST_GICD_CPENDSGIR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26551 #define ALT_GIC_DIST_GICD_CPENDSGIR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
26553 #ifndef __ASSEMBLY__
26565 struct ALT_GIC_DIST_GICD_CPENDSGIR0_s
26567 volatile uint32_t fld : 32;
26571 typedef struct ALT_GIC_DIST_GICD_CPENDSGIR0_s ALT_GIC_DIST_GICD_CPENDSGIR0_t;
26575 #define ALT_GIC_DIST_GICD_CPENDSGIR0_RESET 0x00000000
26577 #define ALT_GIC_DIST_GICD_CPENDSGIR0_OFST 0xf10
26600 #define ALT_GIC_DIST_GICD_CPENDSGIR1_FLD_LSB 0
26602 #define ALT_GIC_DIST_GICD_CPENDSGIR1_FLD_MSB 31
26604 #define ALT_GIC_DIST_GICD_CPENDSGIR1_FLD_WIDTH 32
26606 #define ALT_GIC_DIST_GICD_CPENDSGIR1_FLD_SET_MSK 0xffffffff
26608 #define ALT_GIC_DIST_GICD_CPENDSGIR1_FLD_CLR_MSK 0x00000000
26610 #define ALT_GIC_DIST_GICD_CPENDSGIR1_FLD_RESET 0x0
26612 #define ALT_GIC_DIST_GICD_CPENDSGIR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26614 #define ALT_GIC_DIST_GICD_CPENDSGIR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
26616 #ifndef __ASSEMBLY__
26628 struct ALT_GIC_DIST_GICD_CPENDSGIR1_s
26630 volatile uint32_t fld : 32;
26634 typedef struct ALT_GIC_DIST_GICD_CPENDSGIR1_s ALT_GIC_DIST_GICD_CPENDSGIR1_t;
26638 #define ALT_GIC_DIST_GICD_CPENDSGIR1_RESET 0x00000000
26640 #define ALT_GIC_DIST_GICD_CPENDSGIR1_OFST 0xf14
26663 #define ALT_GIC_DIST_GICD_CPENDSGIR2_FLD_LSB 0
26665 #define ALT_GIC_DIST_GICD_CPENDSGIR2_FLD_MSB 31
26667 #define ALT_GIC_DIST_GICD_CPENDSGIR2_FLD_WIDTH 32
26669 #define ALT_GIC_DIST_GICD_CPENDSGIR2_FLD_SET_MSK 0xffffffff
26671 #define ALT_GIC_DIST_GICD_CPENDSGIR2_FLD_CLR_MSK 0x00000000
26673 #define ALT_GIC_DIST_GICD_CPENDSGIR2_FLD_RESET 0x0
26675 #define ALT_GIC_DIST_GICD_CPENDSGIR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26677 #define ALT_GIC_DIST_GICD_CPENDSGIR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
26679 #ifndef __ASSEMBLY__
26691 struct ALT_GIC_DIST_GICD_CPENDSGIR2_s
26693 volatile uint32_t fld : 32;
26697 typedef struct ALT_GIC_DIST_GICD_CPENDSGIR2_s ALT_GIC_DIST_GICD_CPENDSGIR2_t;
26701 #define ALT_GIC_DIST_GICD_CPENDSGIR2_RESET 0x00000000
26703 #define ALT_GIC_DIST_GICD_CPENDSGIR2_OFST 0xf18
26726 #define ALT_GIC_DIST_GICD_CPENDSGIR3_FLD_LSB 0
26728 #define ALT_GIC_DIST_GICD_CPENDSGIR3_FLD_MSB 31
26730 #define ALT_GIC_DIST_GICD_CPENDSGIR3_FLD_WIDTH 32
26732 #define ALT_GIC_DIST_GICD_CPENDSGIR3_FLD_SET_MSK 0xffffffff
26734 #define ALT_GIC_DIST_GICD_CPENDSGIR3_FLD_CLR_MSK 0x00000000
26736 #define ALT_GIC_DIST_GICD_CPENDSGIR3_FLD_RESET 0x0
26738 #define ALT_GIC_DIST_GICD_CPENDSGIR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26740 #define ALT_GIC_DIST_GICD_CPENDSGIR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
26742 #ifndef __ASSEMBLY__
26754 struct ALT_GIC_DIST_GICD_CPENDSGIR3_s
26756 volatile uint32_t fld : 32;
26760 typedef struct ALT_GIC_DIST_GICD_CPENDSGIR3_s ALT_GIC_DIST_GICD_CPENDSGIR3_t;
26764 #define ALT_GIC_DIST_GICD_CPENDSGIR3_RESET 0x00000000
26766 #define ALT_GIC_DIST_GICD_CPENDSGIR3_OFST 0xf1c
26789 #define ALT_GIC_DIST_GICD_SPENDSGIR0_FLD_LSB 0
26791 #define ALT_GIC_DIST_GICD_SPENDSGIR0_FLD_MSB 31
26793 #define ALT_GIC_DIST_GICD_SPENDSGIR0_FLD_WIDTH 32
26795 #define ALT_GIC_DIST_GICD_SPENDSGIR0_FLD_SET_MSK 0xffffffff
26797 #define ALT_GIC_DIST_GICD_SPENDSGIR0_FLD_CLR_MSK 0x00000000
26799 #define ALT_GIC_DIST_GICD_SPENDSGIR0_FLD_RESET 0x0
26801 #define ALT_GIC_DIST_GICD_SPENDSGIR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26803 #define ALT_GIC_DIST_GICD_SPENDSGIR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
26805 #ifndef __ASSEMBLY__
26817 struct ALT_GIC_DIST_GICD_SPENDSGIR0_s
26819 volatile uint32_t fld : 32;
26823 typedef struct ALT_GIC_DIST_GICD_SPENDSGIR0_s ALT_GIC_DIST_GICD_SPENDSGIR0_t;
26827 #define ALT_GIC_DIST_GICD_SPENDSGIR0_RESET 0x00000000
26829 #define ALT_GIC_DIST_GICD_SPENDSGIR0_OFST 0xf20
26852 #define ALT_GIC_DIST_GICD_SPENDSGIR1_FLD_LSB 0
26854 #define ALT_GIC_DIST_GICD_SPENDSGIR1_FLD_MSB 31
26856 #define ALT_GIC_DIST_GICD_SPENDSGIR1_FLD_WIDTH 32
26858 #define ALT_GIC_DIST_GICD_SPENDSGIR1_FLD_SET_MSK 0xffffffff
26860 #define ALT_GIC_DIST_GICD_SPENDSGIR1_FLD_CLR_MSK 0x00000000
26862 #define ALT_GIC_DIST_GICD_SPENDSGIR1_FLD_RESET 0x0
26864 #define ALT_GIC_DIST_GICD_SPENDSGIR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26866 #define ALT_GIC_DIST_GICD_SPENDSGIR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
26868 #ifndef __ASSEMBLY__
26880 struct ALT_GIC_DIST_GICD_SPENDSGIR1_s
26882 volatile uint32_t fld : 32;
26886 typedef struct ALT_GIC_DIST_GICD_SPENDSGIR1_s ALT_GIC_DIST_GICD_SPENDSGIR1_t;
26890 #define ALT_GIC_DIST_GICD_SPENDSGIR1_RESET 0x00000000
26892 #define ALT_GIC_DIST_GICD_SPENDSGIR1_OFST 0xf24
26915 #define ALT_GIC_DIST_GICD_SPENDSGIR2_FLD_LSB 0
26917 #define ALT_GIC_DIST_GICD_SPENDSGIR2_FLD_MSB 31
26919 #define ALT_GIC_DIST_GICD_SPENDSGIR2_FLD_WIDTH 32
26921 #define ALT_GIC_DIST_GICD_SPENDSGIR2_FLD_SET_MSK 0xffffffff
26923 #define ALT_GIC_DIST_GICD_SPENDSGIR2_FLD_CLR_MSK 0x00000000
26925 #define ALT_GIC_DIST_GICD_SPENDSGIR2_FLD_RESET 0x0
26927 #define ALT_GIC_DIST_GICD_SPENDSGIR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26929 #define ALT_GIC_DIST_GICD_SPENDSGIR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
26931 #ifndef __ASSEMBLY__
26943 struct ALT_GIC_DIST_GICD_SPENDSGIR2_s
26945 volatile uint32_t fld : 32;
26949 typedef struct ALT_GIC_DIST_GICD_SPENDSGIR2_s ALT_GIC_DIST_GICD_SPENDSGIR2_t;
26953 #define ALT_GIC_DIST_GICD_SPENDSGIR2_RESET 0x00000000
26955 #define ALT_GIC_DIST_GICD_SPENDSGIR2_OFST 0xf28
26978 #define ALT_GIC_DIST_GICD_SPENDSGIR3_FLD_LSB 0
26980 #define ALT_GIC_DIST_GICD_SPENDSGIR3_FLD_MSB 31
26982 #define ALT_GIC_DIST_GICD_SPENDSGIR3_FLD_WIDTH 32
26984 #define ALT_GIC_DIST_GICD_SPENDSGIR3_FLD_SET_MSK 0xffffffff
26986 #define ALT_GIC_DIST_GICD_SPENDSGIR3_FLD_CLR_MSK 0x00000000
26988 #define ALT_GIC_DIST_GICD_SPENDSGIR3_FLD_RESET 0x0
26990 #define ALT_GIC_DIST_GICD_SPENDSGIR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26992 #define ALT_GIC_DIST_GICD_SPENDSGIR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
26994 #ifndef __ASSEMBLY__
27006 struct ALT_GIC_DIST_GICD_SPENDSGIR3_s
27008 volatile uint32_t fld : 32;
27012 typedef struct ALT_GIC_DIST_GICD_SPENDSGIR3_s ALT_GIC_DIST_GICD_SPENDSGIR3_t;
27016 #define ALT_GIC_DIST_GICD_SPENDSGIR3_RESET 0x00000000
27018 #define ALT_GIC_DIST_GICD_SPENDSGIR3_OFST 0xf2c
27041 #define ALT_GIC_DIST_GICD_PIDR4_FLD_LSB 0
27043 #define ALT_GIC_DIST_GICD_PIDR4_FLD_MSB 31
27045 #define ALT_GIC_DIST_GICD_PIDR4_FLD_WIDTH 32
27047 #define ALT_GIC_DIST_GICD_PIDR4_FLD_SET_MSK 0xffffffff
27049 #define ALT_GIC_DIST_GICD_PIDR4_FLD_CLR_MSK 0x00000000
27051 #define ALT_GIC_DIST_GICD_PIDR4_FLD_RESET 0x4
27053 #define ALT_GIC_DIST_GICD_PIDR4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27055 #define ALT_GIC_DIST_GICD_PIDR4_FLD_SET(value) (((value) << 0) & 0xffffffff)
27057 #ifndef __ASSEMBLY__
27069 struct ALT_GIC_DIST_GICD_PIDR4_s
27071 volatile uint32_t fld : 32;
27075 typedef struct ALT_GIC_DIST_GICD_PIDR4_s ALT_GIC_DIST_GICD_PIDR4_t;
27079 #define ALT_GIC_DIST_GICD_PIDR4_RESET 0x00000004
27081 #define ALT_GIC_DIST_GICD_PIDR4_OFST 0xfd0
27104 #define ALT_GIC_DIST_GICD_PIDR5_FLD_LSB 0
27106 #define ALT_GIC_DIST_GICD_PIDR5_FLD_MSB 31
27108 #define ALT_GIC_DIST_GICD_PIDR5_FLD_WIDTH 32
27110 #define ALT_GIC_DIST_GICD_PIDR5_FLD_SET_MSK 0xffffffff
27112 #define ALT_GIC_DIST_GICD_PIDR5_FLD_CLR_MSK 0x00000000
27114 #define ALT_GIC_DIST_GICD_PIDR5_FLD_RESET 0x0
27116 #define ALT_GIC_DIST_GICD_PIDR5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27118 #define ALT_GIC_DIST_GICD_PIDR5_FLD_SET(value) (((value) << 0) & 0xffffffff)
27120 #ifndef __ASSEMBLY__
27132 struct ALT_GIC_DIST_GICD_PIDR5_s
27134 volatile uint32_t fld : 32;
27138 typedef struct ALT_GIC_DIST_GICD_PIDR5_s ALT_GIC_DIST_GICD_PIDR5_t;
27142 #define ALT_GIC_DIST_GICD_PIDR5_RESET 0x00000000
27144 #define ALT_GIC_DIST_GICD_PIDR5_OFST 0xfd4
27167 #define ALT_GIC_DIST_GICD_PIDR6_FLD_LSB 0
27169 #define ALT_GIC_DIST_GICD_PIDR6_FLD_MSB 31
27171 #define ALT_GIC_DIST_GICD_PIDR6_FLD_WIDTH 32
27173 #define ALT_GIC_DIST_GICD_PIDR6_FLD_SET_MSK 0xffffffff
27175 #define ALT_GIC_DIST_GICD_PIDR6_FLD_CLR_MSK 0x00000000
27177 #define ALT_GIC_DIST_GICD_PIDR6_FLD_RESET 0x0
27179 #define ALT_GIC_DIST_GICD_PIDR6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27181 #define ALT_GIC_DIST_GICD_PIDR6_FLD_SET(value) (((value) << 0) & 0xffffffff)
27183 #ifndef __ASSEMBLY__
27195 struct ALT_GIC_DIST_GICD_PIDR6_s
27197 volatile uint32_t fld : 32;
27201 typedef struct ALT_GIC_DIST_GICD_PIDR6_s ALT_GIC_DIST_GICD_PIDR6_t;
27205 #define ALT_GIC_DIST_GICD_PIDR6_RESET 0x00000000
27207 #define ALT_GIC_DIST_GICD_PIDR6_OFST 0xfd8
27230 #define ALT_GIC_DIST_GICD_PIDR7_FLD_LSB 0
27232 #define ALT_GIC_DIST_GICD_PIDR7_FLD_MSB 31
27234 #define ALT_GIC_DIST_GICD_PIDR7_FLD_WIDTH 32
27236 #define ALT_GIC_DIST_GICD_PIDR7_FLD_SET_MSK 0xffffffff
27238 #define ALT_GIC_DIST_GICD_PIDR7_FLD_CLR_MSK 0x00000000
27240 #define ALT_GIC_DIST_GICD_PIDR7_FLD_RESET 0x0
27242 #define ALT_GIC_DIST_GICD_PIDR7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27244 #define ALT_GIC_DIST_GICD_PIDR7_FLD_SET(value) (((value) << 0) & 0xffffffff)
27246 #ifndef __ASSEMBLY__
27258 struct ALT_GIC_DIST_GICD_PIDR7_s
27260 volatile uint32_t fld : 32;
27264 typedef struct ALT_GIC_DIST_GICD_PIDR7_s ALT_GIC_DIST_GICD_PIDR7_t;
27268 #define ALT_GIC_DIST_GICD_PIDR7_RESET 0x00000000
27270 #define ALT_GIC_DIST_GICD_PIDR7_OFST 0xfdc
27293 #define ALT_GIC_DIST_GICD_PIDR0_FLD_LSB 0
27295 #define ALT_GIC_DIST_GICD_PIDR0_FLD_MSB 31
27297 #define ALT_GIC_DIST_GICD_PIDR0_FLD_WIDTH 32
27299 #define ALT_GIC_DIST_GICD_PIDR0_FLD_SET_MSK 0xffffffff
27301 #define ALT_GIC_DIST_GICD_PIDR0_FLD_CLR_MSK 0x00000000
27303 #define ALT_GIC_DIST_GICD_PIDR0_FLD_RESET 0x90
27305 #define ALT_GIC_DIST_GICD_PIDR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27307 #define ALT_GIC_DIST_GICD_PIDR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
27309 #ifndef __ASSEMBLY__
27321 struct ALT_GIC_DIST_GICD_PIDR0_s
27323 volatile uint32_t fld : 32;
27327 typedef struct ALT_GIC_DIST_GICD_PIDR0_s ALT_GIC_DIST_GICD_PIDR0_t;
27331 #define ALT_GIC_DIST_GICD_PIDR0_RESET 0x00000090
27333 #define ALT_GIC_DIST_GICD_PIDR0_OFST 0xfe0
27356 #define ALT_GIC_DIST_GICD_PIDR1_FLD_LSB 0
27358 #define ALT_GIC_DIST_GICD_PIDR1_FLD_MSB 31
27360 #define ALT_GIC_DIST_GICD_PIDR1_FLD_WIDTH 32
27362 #define ALT_GIC_DIST_GICD_PIDR1_FLD_SET_MSK 0xffffffff
27364 #define ALT_GIC_DIST_GICD_PIDR1_FLD_CLR_MSK 0x00000000
27366 #define ALT_GIC_DIST_GICD_PIDR1_FLD_RESET 0xb4
27368 #define ALT_GIC_DIST_GICD_PIDR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27370 #define ALT_GIC_DIST_GICD_PIDR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
27372 #ifndef __ASSEMBLY__
27384 struct ALT_GIC_DIST_GICD_PIDR1_s
27386 volatile uint32_t fld : 32;
27390 typedef struct ALT_GIC_DIST_GICD_PIDR1_s ALT_GIC_DIST_GICD_PIDR1_t;
27394 #define ALT_GIC_DIST_GICD_PIDR1_RESET 0x000000b4
27396 #define ALT_GIC_DIST_GICD_PIDR1_OFST 0xfe4
27419 #define ALT_GIC_DIST_GICD_PIDR2_FLD_LSB 0
27421 #define ALT_GIC_DIST_GICD_PIDR2_FLD_MSB 31
27423 #define ALT_GIC_DIST_GICD_PIDR2_FLD_WIDTH 32
27425 #define ALT_GIC_DIST_GICD_PIDR2_FLD_SET_MSK 0xffffffff
27427 #define ALT_GIC_DIST_GICD_PIDR2_FLD_CLR_MSK 0x00000000
27429 #define ALT_GIC_DIST_GICD_PIDR2_FLD_RESET 0x2b
27431 #define ALT_GIC_DIST_GICD_PIDR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27433 #define ALT_GIC_DIST_GICD_PIDR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
27435 #ifndef __ASSEMBLY__
27447 struct ALT_GIC_DIST_GICD_PIDR2_s
27449 volatile uint32_t fld : 32;
27453 typedef struct ALT_GIC_DIST_GICD_PIDR2_s ALT_GIC_DIST_GICD_PIDR2_t;
27457 #define ALT_GIC_DIST_GICD_PIDR2_RESET 0x0000002b
27459 #define ALT_GIC_DIST_GICD_PIDR2_OFST 0xfe8
27482 #define ALT_GIC_DIST_GICD_PIDR3_FLD_LSB 0
27484 #define ALT_GIC_DIST_GICD_PIDR3_FLD_MSB 31
27486 #define ALT_GIC_DIST_GICD_PIDR3_FLD_WIDTH 32
27488 #define ALT_GIC_DIST_GICD_PIDR3_FLD_SET_MSK 0xffffffff
27490 #define ALT_GIC_DIST_GICD_PIDR3_FLD_CLR_MSK 0x00000000
27492 #define ALT_GIC_DIST_GICD_PIDR3_FLD_RESET 0x0
27494 #define ALT_GIC_DIST_GICD_PIDR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27496 #define ALT_GIC_DIST_GICD_PIDR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
27498 #ifndef __ASSEMBLY__
27510 struct ALT_GIC_DIST_GICD_PIDR3_s
27512 volatile uint32_t fld : 32;
27516 typedef struct ALT_GIC_DIST_GICD_PIDR3_s ALT_GIC_DIST_GICD_PIDR3_t;
27520 #define ALT_GIC_DIST_GICD_PIDR3_RESET 0x00000000
27522 #define ALT_GIC_DIST_GICD_PIDR3_OFST 0xfec
27545 #define ALT_GIC_DIST_GICD_CIDR0_FLD_LSB 0
27547 #define ALT_GIC_DIST_GICD_CIDR0_FLD_MSB 31
27549 #define ALT_GIC_DIST_GICD_CIDR0_FLD_WIDTH 32
27551 #define ALT_GIC_DIST_GICD_CIDR0_FLD_SET_MSK 0xffffffff
27553 #define ALT_GIC_DIST_GICD_CIDR0_FLD_CLR_MSK 0x00000000
27555 #define ALT_GIC_DIST_GICD_CIDR0_FLD_RESET 0xd
27557 #define ALT_GIC_DIST_GICD_CIDR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27559 #define ALT_GIC_DIST_GICD_CIDR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
27561 #ifndef __ASSEMBLY__
27573 struct ALT_GIC_DIST_GICD_CIDR0_s
27575 volatile uint32_t fld : 32;
27579 typedef struct ALT_GIC_DIST_GICD_CIDR0_s ALT_GIC_DIST_GICD_CIDR0_t;
27583 #define ALT_GIC_DIST_GICD_CIDR0_RESET 0x0000000d
27585 #define ALT_GIC_DIST_GICD_CIDR0_OFST 0xff0
27608 #define ALT_GIC_DIST_GICD_CIDR1_FLD_LSB 0
27610 #define ALT_GIC_DIST_GICD_CIDR1_FLD_MSB 31
27612 #define ALT_GIC_DIST_GICD_CIDR1_FLD_WIDTH 32
27614 #define ALT_GIC_DIST_GICD_CIDR1_FLD_SET_MSK 0xffffffff
27616 #define ALT_GIC_DIST_GICD_CIDR1_FLD_CLR_MSK 0x00000000
27618 #define ALT_GIC_DIST_GICD_CIDR1_FLD_RESET 0xf0
27620 #define ALT_GIC_DIST_GICD_CIDR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27622 #define ALT_GIC_DIST_GICD_CIDR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
27624 #ifndef __ASSEMBLY__
27636 struct ALT_GIC_DIST_GICD_CIDR1_s
27638 volatile uint32_t fld : 32;
27642 typedef struct ALT_GIC_DIST_GICD_CIDR1_s ALT_GIC_DIST_GICD_CIDR1_t;
27646 #define ALT_GIC_DIST_GICD_CIDR1_RESET 0x000000f0
27648 #define ALT_GIC_DIST_GICD_CIDR1_OFST 0xff4
27671 #define ALT_GIC_DIST_GICD_CIDR2_FLD_LSB 0
27673 #define ALT_GIC_DIST_GICD_CIDR2_FLD_MSB 31
27675 #define ALT_GIC_DIST_GICD_CIDR2_FLD_WIDTH 32
27677 #define ALT_GIC_DIST_GICD_CIDR2_FLD_SET_MSK 0xffffffff
27679 #define ALT_GIC_DIST_GICD_CIDR2_FLD_CLR_MSK 0x00000000
27681 #define ALT_GIC_DIST_GICD_CIDR2_FLD_RESET 0x5
27683 #define ALT_GIC_DIST_GICD_CIDR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27685 #define ALT_GIC_DIST_GICD_CIDR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
27687 #ifndef __ASSEMBLY__
27699 struct ALT_GIC_DIST_GICD_CIDR2_s
27701 volatile uint32_t fld : 32;
27705 typedef struct ALT_GIC_DIST_GICD_CIDR2_s ALT_GIC_DIST_GICD_CIDR2_t;
27709 #define ALT_GIC_DIST_GICD_CIDR2_RESET 0x00000005
27711 #define ALT_GIC_DIST_GICD_CIDR2_OFST 0xff8
27734 #define ALT_GIC_DIST_GICD_CIDR3_FLD_LSB 0
27736 #define ALT_GIC_DIST_GICD_CIDR3_FLD_MSB 31
27738 #define ALT_GIC_DIST_GICD_CIDR3_FLD_WIDTH 32
27740 #define ALT_GIC_DIST_GICD_CIDR3_FLD_SET_MSK 0xffffffff
27742 #define ALT_GIC_DIST_GICD_CIDR3_FLD_CLR_MSK 0x00000000
27744 #define ALT_GIC_DIST_GICD_CIDR3_FLD_RESET 0xb1
27746 #define ALT_GIC_DIST_GICD_CIDR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27748 #define ALT_GIC_DIST_GICD_CIDR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
27750 #ifndef __ASSEMBLY__
27762 struct ALT_GIC_DIST_GICD_CIDR3_s
27764 volatile uint32_t fld : 32;
27768 typedef struct ALT_GIC_DIST_GICD_CIDR3_s ALT_GIC_DIST_GICD_CIDR3_t;
27772 #define ALT_GIC_DIST_GICD_CIDR3_RESET 0x000000b1
27774 #define ALT_GIC_DIST_GICD_CIDR3_OFST 0xffc
27776 #ifndef __ASSEMBLY__
27788 struct ALT_GIC_DIST_s
27790 volatile ALT_GIC_DIST_GICD_CTLR_t GICD_CTLR;
27791 volatile ALT_GIC_DIST_GICD_TYPER_t GICD_TYPER;
27792 volatile ALT_GIC_DIST_GICD_IIDR_t GICD_IIDR;
27793 volatile uint32_t _pad_0xc_0x7f[29];
27794 volatile ALT_GIC_DIST_GICD_IGROUPR0_t GICD_IGROUPR0;
27795 volatile ALT_GIC_DIST_GICD_IGROUPR1_t GICD_IGROUPR1;
27796 volatile ALT_GIC_DIST_GICD_IGROUPR2_t GICD_IGROUPR2;
27797 volatile ALT_GIC_DIST_GICD_IGROUPR3_t GICD_IGROUPR3;
27798 volatile ALT_GIC_DIST_GICD_IGROUPR4_t GICD_IGROUPR4;
27799 volatile ALT_GIC_DIST_GICD_IGROUPR5_t GICD_IGROUPR5;
27800 volatile ALT_GIC_DIST_GICD_IGROUPR6_t GICD_IGROUPR6;
27801 volatile ALT_GIC_DIST_GICD_IGROUPR7_t GICD_IGROUPR7;
27802 volatile ALT_GIC_DIST_GICD_IGROUPR8_t GICD_IGROUPR8;
27803 volatile ALT_GIC_DIST_GICD_IGROUPR9_t GICD_IGROUPR9;
27804 volatile ALT_GIC_DIST_GICD_IGROUPR10_t GICD_IGROUPR10;
27805 volatile ALT_GIC_DIST_GICD_IGROUPR11_t GICD_IGROUPR11;
27806 volatile ALT_GIC_DIST_GICD_IGROUPR12_t GICD_IGROUPR12;
27807 volatile ALT_GIC_DIST_GICD_IGROUPR13_t GICD_IGROUPR13;
27808 volatile ALT_GIC_DIST_GICD_IGROUPR14_t GICD_IGROUPR14;
27809 volatile ALT_GIC_DIST_GICD_IGROUPR15_t GICD_IGROUPR15;
27810 volatile uint32_t _pad_0xc0_0xff[16];
27811 volatile ALT_GIC_DIST_GICD_ISENABLER0_t GICD_ISENABLER0;
27812 volatile ALT_GIC_DIST_GICD_ISENABLER1_t GICD_ISENABLER1;
27813 volatile ALT_GIC_DIST_GICD_ISENABLER2_t GICD_ISENABLER2;
27814 volatile ALT_GIC_DIST_GICD_ISENABLER3_t GICD_ISENABLER3;
27815 volatile ALT_GIC_DIST_GICD_ISENABLER4_t GICD_ISENABLER4;
27816 volatile ALT_GIC_DIST_GICD_ISENABLER5_t GICD_ISENABLER5;
27817 volatile ALT_GIC_DIST_GICD_ISENABLER6_t GICD_ISENABLER6;
27818 volatile ALT_GIC_DIST_GICD_ISENABLER7_t GICD_ISENABLER7;
27819 volatile ALT_GIC_DIST_GICD_ISENABLER8_t GICD_ISENABLER8;
27820 volatile ALT_GIC_DIST_GICD_ISENABLER9_t GICD_ISENABLER9;
27821 volatile ALT_GIC_DIST_GICD_ISENABLER10_t GICD_ISENABLER10;
27822 volatile ALT_GIC_DIST_GICD_ISENABLER11_t GICD_ISENABLER11;
27823 volatile ALT_GIC_DIST_GICD_ISENABLER12_t GICD_ISENABLER12;
27824 volatile ALT_GIC_DIST_GICD_ISENABLER13_t GICD_ISENABLER13;
27825 volatile ALT_GIC_DIST_GICD_ISENABLER14_t GICD_ISENABLER14;
27826 volatile ALT_GIC_DIST_GICD_ISENABLER15_t GICD_ISENABLER15;
27827 volatile uint32_t _pad_0x140_0x17f[16];
27828 volatile ALT_GIC_DIST_GICD_ICENABLER0_t GICD_ICENABLER0;
27829 volatile ALT_GIC_DIST_GICD_ICENABLER1_t GICD_ICENABLER1;
27830 volatile ALT_GIC_DIST_GICD_ICENABLER2_t GICD_ICENABLER2;
27831 volatile ALT_GIC_DIST_GICD_ICENABLER3_t GICD_ICENABLER3;
27832 volatile ALT_GIC_DIST_GICD_ICENABLER4_t GICD_ICENABLER4;
27833 volatile ALT_GIC_DIST_GICD_ICENABLER5_t GICD_ICENABLER5;
27834 volatile ALT_GIC_DIST_GICD_ICENABLER6_t GICD_ICENABLER6;
27835 volatile ALT_GIC_DIST_GICD_ICENABLER7_t GICD_ICENABLER7;
27836 volatile ALT_GIC_DIST_GICD_ICENABLER8_t GICD_ICENABLER8;
27837 volatile ALT_GIC_DIST_GICD_ICENABLER9_t GICD_ICENABLER9;
27838 volatile ALT_GIC_DIST_GICD_ICENABLER10_t GICD_ICENABLER10;
27839 volatile ALT_GIC_DIST_GICD_ICENABLER11_t GICD_ICENABLER11;
27840 volatile ALT_GIC_DIST_GICD_ICENABLER12_t GICD_ICENABLER12;
27841 volatile ALT_GIC_DIST_GICD_ICENABLER13_t GICD_ICENABLER13;
27842 volatile ALT_GIC_DIST_GICD_ICENABLER14_t GICD_ICENABLER14;
27843 volatile ALT_GIC_DIST_GICD_ICENABLER15_t GICD_ICENABLER15;
27844 volatile uint32_t _pad_0x1c0_0x1ff[16];
27845 volatile ALT_GIC_DIST_GICD_ISPENDR0_t GICD_ISPENDR0;
27846 volatile ALT_GIC_DIST_GICD_ISPENDR1_t GICD_ISPENDR1;
27847 volatile ALT_GIC_DIST_GICD_ISPENDR2_t GICD_ISPENDR2;
27848 volatile ALT_GIC_DIST_GICD_ISPENDR3_t GICD_ISPENDR3;
27849 volatile ALT_GIC_DIST_GICD_ISPENDR4_t GICD_ISPENDR4;
27850 volatile ALT_GIC_DIST_GICD_ISPENDR5_t GICD_ISPENDR5;
27851 volatile ALT_GIC_DIST_GICD_ISPENDR6_t GICD_ISPENDR6;
27852 volatile ALT_GIC_DIST_GICD_ISPENDR7_t GICD_ISPENDR7;
27853 volatile ALT_GIC_DIST_GICD_ISPENDR8_t GICD_ISPENDR8;
27854 volatile ALT_GIC_DIST_GICD_ISPENDR9_t GICD_ISPENDR9;
27855 volatile ALT_GIC_DIST_GICD_ISPENDR10_t GICD_ISPENDR10;
27856 volatile ALT_GIC_DIST_GICD_ISPENDR11_t GICD_ISPENDR11;
27857 volatile ALT_GIC_DIST_GICD_ISPENDR12_t GICD_ISPENDR12;
27858 volatile ALT_GIC_DIST_GICD_ISPENDR13_t GICD_ISPENDR13;
27859 volatile ALT_GIC_DIST_GICD_ISPENDR14_t GICD_ISPENDR14;
27860 volatile ALT_GIC_DIST_GICD_ISPENDR15_t GICD_ISPENDR15;
27861 volatile uint32_t _pad_0x240_0x27f[16];
27862 volatile ALT_GIC_DIST_GICD_ICPENDR0_t GICD_ICPENDR0;
27863 volatile ALT_GIC_DIST_GICD_ICPENDR1_t GICD_ICPENDR1;
27864 volatile ALT_GIC_DIST_GICD_ICPENDR2_t GICD_ICPENDR2;
27865 volatile ALT_GIC_DIST_GICD_ICPENDR3_t GICD_ICPENDR3;
27866 volatile ALT_GIC_DIST_GICD_ICPENDR4_t GICD_ICPENDR4;
27867 volatile ALT_GIC_DIST_GICD_ICPENDR5_t GICD_ICPENDR5;
27868 volatile ALT_GIC_DIST_GICD_ICPENDR6_t GICD_ICPENDR6;
27869 volatile ALT_GIC_DIST_GICD_ICPENDR7_t GICD_ICPENDR7;
27870 volatile ALT_GIC_DIST_GICD_ICPENDR8_t GICD_ICPENDR8;
27871 volatile ALT_GIC_DIST_GICD_ICPENDR9_t GICD_ICPENDR9;
27872 volatile ALT_GIC_DIST_GICD_ICPENDR10_t GICD_ICPENDR10;
27873 volatile ALT_GIC_DIST_GICD_ICPENDR11_t GICD_ICPENDR11;
27874 volatile ALT_GIC_DIST_GICD_ICPENDR12_t GICD_ICPENDR12;
27875 volatile ALT_GIC_DIST_GICD_ICPENDR13_t GICD_ICPENDR13;
27876 volatile ALT_GIC_DIST_GICD_ICPENDR14_t GICD_ICPENDR14;
27877 volatile ALT_GIC_DIST_GICD_ICPENDR15_t GICD_ICPENDR15;
27878 volatile uint32_t _pad_0x2c0_0x2ff[16];
27879 volatile ALT_GIC_DIST_GICD_ISACTIVER0_t GICD_ISACTIVER0;
27880 volatile ALT_GIC_DIST_GICD_ISACTIVER1_t GICD_ISACTIVER1;
27881 volatile ALT_GIC_DIST_GICD_ISACTIVER2_t GICD_ISACTIVER2;
27882 volatile ALT_GIC_DIST_GICD_ISACTIVER3_t GICD_ISACTIVER3;
27883 volatile ALT_GIC_DIST_GICD_ISACTIVER4_t GICD_ISACTIVER4;
27884 volatile ALT_GIC_DIST_GICD_ISACTIVER5_t GICD_ISACTIVER5;
27885 volatile ALT_GIC_DIST_GICD_ISACTIVER6_t GICD_ISACTIVER6;
27886 volatile ALT_GIC_DIST_GICD_ISACTIVER7_t GICD_ISACTIVER7;
27887 volatile ALT_GIC_DIST_GICD_ISACTIVER8_t GICD_ISACTIVER8;
27888 volatile ALT_GIC_DIST_GICD_ISACTIVER9_t GICD_ISACTIVER9;
27889 volatile ALT_GIC_DIST_GICD_ISACTIVER10_t GICD_ISACTIVER10;
27890 volatile ALT_GIC_DIST_GICD_ISACTIVER11_t GICD_ISACTIVER11;
27891 volatile ALT_GIC_DIST_GICD_ISACTIVER12_t GICD_ISACTIVER12;
27892 volatile ALT_GIC_DIST_GICD_ISACTIVER13_t GICD_ISACTIVER13;
27893 volatile ALT_GIC_DIST_GICD_ISACTIVER14_t GICD_ISACTIVER14;
27894 volatile ALT_GIC_DIST_GICD_ISACTIVER15_t GICD_ISACTIVER15;
27895 volatile uint32_t _pad_0x340_0x37f[16];
27896 volatile ALT_GIC_DIST_GICD_ICACTIVER0_t GICD_ICACTIVER0;
27897 volatile ALT_GIC_DIST_GICD_ICACTIVER1_t GICD_ICACTIVER1;
27898 volatile ALT_GIC_DIST_GICD_ICACTIVER2_t GICD_ICACTIVER2;
27899 volatile ALT_GIC_DIST_GICD_ICACTIVER3_t GICD_ICACTIVER3;
27900 volatile ALT_GIC_DIST_GICD_ICACTIVER4_t GICD_ICACTIVER4;
27901 volatile ALT_GIC_DIST_GICD_ICACTIVER5_t GICD_ICACTIVER5;
27902 volatile ALT_GIC_DIST_GICD_ICACTIVER6_t GICD_ICACTIVER6;
27903 volatile ALT_GIC_DIST_GICD_ICACTIVER7_t GICD_ICACTIVER7;
27904 volatile ALT_GIC_DIST_GICD_ICACTIVER8_t GICD_ICACTIVER8;
27905 volatile ALT_GIC_DIST_GICD_ICACTIVER9_t GICD_ICACTIVER9;
27906 volatile ALT_GIC_DIST_GICD_ICACTIVER10_t GICD_ICACTIVER10;
27907 volatile ALT_GIC_DIST_GICD_ICACTIVER11_t GICD_ICACTIVER11;
27908 volatile ALT_GIC_DIST_GICD_ICACTIVER12_t GICD_ICACTIVER12;
27909 volatile ALT_GIC_DIST_GICD_ICACTIVER13_t GICD_ICACTIVER13;
27910 volatile ALT_GIC_DIST_GICD_ICACTIVER14_t GICD_ICACTIVER14;
27911 volatile ALT_GIC_DIST_GICD_ICACTIVER15_t GICD_ICACTIVER15;
27912 volatile uint32_t _pad_0x3c0_0x3ff[16];
27913 volatile ALT_GIC_DIST_GICD_IPRIORITYR0_t GICD_IPRIORITYR0;
27914 volatile ALT_GIC_DIST_GICD_IPRIORITYR1_t GICD_IPRIORITYR1;
27915 volatile ALT_GIC_DIST_GICD_IPRIORITYR2_t GICD_IPRIORITYR2;
27916 volatile ALT_GIC_DIST_GICD_IPRIORITYR3_t GICD_IPRIORITYR3;
27917 volatile ALT_GIC_DIST_GICD_IPRIORITYR4_t GICD_IPRIORITYR4;
27918 volatile ALT_GIC_DIST_GICD_IPRIORITYR5_t GICD_IPRIORITYR5;
27919 volatile ALT_GIC_DIST_GICD_IPRIORITYR6_t GICD_IPRIORITYR6;
27920 volatile ALT_GIC_DIST_GICD_IPRIORITYR7_t GICD_IPRIORITYR7;
27921 volatile ALT_GIC_DIST_GICD_IPRIORITYR8_t GICD_IPRIORITYR8;
27922 volatile ALT_GIC_DIST_GICD_IPRIORITYR9_t GICD_IPRIORITYR9;
27923 volatile ALT_GIC_DIST_GICD_IPRIORITYR10_t GICD_IPRIORITYR10;
27924 volatile ALT_GIC_DIST_GICD_IPRIORITYR11_t GICD_IPRIORITYR11;
27925 volatile ALT_GIC_DIST_GICD_IPRIORITYR12_t GICD_IPRIORITYR12;
27926 volatile ALT_GIC_DIST_GICD_IPRIORITYR13_t GICD_IPRIORITYR13;
27927 volatile ALT_GIC_DIST_GICD_IPRIORITYR14_t GICD_IPRIORITYR14;
27928 volatile ALT_GIC_DIST_GICD_IPRIORITYR15_t GICD_IPRIORITYR15;
27929 volatile ALT_GIC_DIST_GICD_IPRIORITYR16_t GICD_IPRIORITYR16;
27930 volatile ALT_GIC_DIST_GICD_IPRIORITYR17_t GICD_IPRIORITYR17;
27931 volatile ALT_GIC_DIST_GICD_IPRIORITYR18_t GICD_IPRIORITYR18;
27932 volatile ALT_GIC_DIST_GICD_IPRIORITYR19_t GICD_IPRIORITYR19;
27933 volatile ALT_GIC_DIST_GICD_IPRIORITYR20_t GICD_IPRIORITYR20;
27934 volatile ALT_GIC_DIST_GICD_IPRIORITYR21_t GICD_IPRIORITYR21;
27935 volatile ALT_GIC_DIST_GICD_IPRIORITYR22_t GICD_IPRIORITYR22;
27936 volatile ALT_GIC_DIST_GICD_IPRIORITYR23_t GICD_IPRIORITYR23;
27937 volatile ALT_GIC_DIST_GICD_IPRIORITYR24_t GICD_IPRIORITYR24;
27938 volatile ALT_GIC_DIST_GICD_IPRIORITYR25_t GICD_IPRIORITYR25;
27939 volatile ALT_GIC_DIST_GICD_IPRIORITYR26_t GICD_IPRIORITYR26;
27940 volatile ALT_GIC_DIST_GICD_IPRIORITYR27_t GICD_IPRIORITYR27;
27941 volatile ALT_GIC_DIST_GICD_IPRIORITYR28_t GICD_IPRIORITYR28;
27942 volatile ALT_GIC_DIST_GICD_IPRIORITYR29_t GICD_IPRIORITYR29;
27943 volatile ALT_GIC_DIST_GICD_IPRIORITYR30_t GICD_IPRIORITYR30;
27944 volatile ALT_GIC_DIST_GICD_IPRIORITYR31_t GICD_IPRIORITYR31;
27945 volatile ALT_GIC_DIST_GICD_IPRIORITYR32_t GICD_IPRIORITYR32;
27946 volatile ALT_GIC_DIST_GICD_IPRIORITYR33_t GICD_IPRIORITYR33;
27947 volatile ALT_GIC_DIST_GICD_IPRIORITYR34_t GICD_IPRIORITYR34;
27948 volatile ALT_GIC_DIST_GICD_IPRIORITYR35_t GICD_IPRIORITYR35;
27949 volatile ALT_GIC_DIST_GICD_IPRIORITYR36_t GICD_IPRIORITYR36;
27950 volatile ALT_GIC_DIST_GICD_IPRIORITYR37_t GICD_IPRIORITYR37;
27951 volatile ALT_GIC_DIST_GICD_IPRIORITYR38_t GICD_IPRIORITYR38;
27952 volatile ALT_GIC_DIST_GICD_IPRIORITYR39_t GICD_IPRIORITYR39;
27953 volatile ALT_GIC_DIST_GICD_IPRIORITYR40_t GICD_IPRIORITYR40;
27954 volatile ALT_GIC_DIST_GICD_IPRIORITYR41_t GICD_IPRIORITYR41;
27955 volatile ALT_GIC_DIST_GICD_IPRIORITYR42_t GICD_IPRIORITYR42;
27956 volatile ALT_GIC_DIST_GICD_IPRIORITYR43_t GICD_IPRIORITYR43;
27957 volatile ALT_GIC_DIST_GICD_IPRIORITYR44_t GICD_IPRIORITYR44;
27958 volatile ALT_GIC_DIST_GICD_IPRIORITYR45_t GICD_IPRIORITYR45;
27959 volatile ALT_GIC_DIST_GICD_IPRIORITYR46_t GICD_IPRIORITYR46;
27960 volatile ALT_GIC_DIST_GICD_IPRIORITYR47_t GICD_IPRIORITYR47;
27961 volatile ALT_GIC_DIST_GICD_IPRIORITYR48_t GICD_IPRIORITYR48;
27962 volatile ALT_GIC_DIST_GICD_IPRIORITYR49_t GICD_IPRIORITYR49;
27963 volatile ALT_GIC_DIST_GICD_IPRIORITYR50_t GICD_IPRIORITYR50;
27964 volatile ALT_GIC_DIST_GICD_IPRIORITYR51_t GICD_IPRIORITYR51;
27965 volatile ALT_GIC_DIST_GICD_IPRIORITYR52_t GICD_IPRIORITYR52;
27966 volatile ALT_GIC_DIST_GICD_IPRIORITYR53_t GICD_IPRIORITYR53;
27967 volatile ALT_GIC_DIST_GICD_IPRIORITYR54_t GICD_IPRIORITYR54;
27968 volatile ALT_GIC_DIST_GICD_IPRIORITYR55_t GICD_IPRIORITYR55;
27969 volatile ALT_GIC_DIST_GICD_IPRIORITYR56_t GICD_IPRIORITYR56;
27970 volatile ALT_GIC_DIST_GICD_IPRIORITYR57_t GICD_IPRIORITYR57;
27971 volatile ALT_GIC_DIST_GICD_IPRIORITYR58_t GICD_IPRIORITYR58;
27972 volatile ALT_GIC_DIST_GICD_IPRIORITYR59_t GICD_IPRIORITYR59;
27973 volatile ALT_GIC_DIST_GICD_IPRIORITYR60_t GICD_IPRIORITYR60;
27974 volatile ALT_GIC_DIST_GICD_IPRIORITYR61_t GICD_IPRIORITYR61;
27975 volatile ALT_GIC_DIST_GICD_IPRIORITYR62_t GICD_IPRIORITYR62;
27976 volatile ALT_GIC_DIST_GICD_IPRIORITYR63_t GICD_IPRIORITYR63;
27977 volatile ALT_GIC_DIST_GICD_IPRIORITYR64_t GICD_IPRIORITYR64;
27978 volatile ALT_GIC_DIST_GICD_IPRIORITYR65_t GICD_IPRIORITYR65;
27979 volatile ALT_GIC_DIST_GICD_IPRIORITYR66_t GICD_IPRIORITYR66;
27980 volatile ALT_GIC_DIST_GICD_IPRIORITYR67_t GICD_IPRIORITYR67;
27981 volatile ALT_GIC_DIST_GICD_IPRIORITYR68_t GICD_IPRIORITYR68;
27982 volatile ALT_GIC_DIST_GICD_IPRIORITYR69_t GICD_IPRIORITYR69;
27983 volatile ALT_GIC_DIST_GICD_IPRIORITYR70_t GICD_IPRIORITYR70;
27984 volatile ALT_GIC_DIST_GICD_IPRIORITYR71_t GICD_IPRIORITYR71;
27985 volatile ALT_GIC_DIST_GICD_IPRIORITYR72_t GICD_IPRIORITYR72;
27986 volatile ALT_GIC_DIST_GICD_IPRIORITYR73_t GICD_IPRIORITYR73;
27987 volatile ALT_GIC_DIST_GICD_IPRIORITYR74_t GICD_IPRIORITYR74;
27988 volatile ALT_GIC_DIST_GICD_IPRIORITYR75_t GICD_IPRIORITYR75;
27989 volatile ALT_GIC_DIST_GICD_IPRIORITYR76_t GICD_IPRIORITYR76;
27990 volatile ALT_GIC_DIST_GICD_IPRIORITYR77_t GICD_IPRIORITYR77;
27991 volatile ALT_GIC_DIST_GICD_IPRIORITYR78_t GICD_IPRIORITYR78;
27992 volatile ALT_GIC_DIST_GICD_IPRIORITYR79_t GICD_IPRIORITYR79;
27993 volatile ALT_GIC_DIST_GICD_IPRIORITYR80_t GICD_IPRIORITYR80;
27994 volatile ALT_GIC_DIST_GICD_IPRIORITYR81_t GICD_IPRIORITYR81;
27995 volatile ALT_GIC_DIST_GICD_IPRIORITYR82_t GICD_IPRIORITYR82;
27996 volatile ALT_GIC_DIST_GICD_IPRIORITYR83_t GICD_IPRIORITYR83;
27997 volatile ALT_GIC_DIST_GICD_IPRIORITYR84_t GICD_IPRIORITYR84;
27998 volatile ALT_GIC_DIST_GICD_IPRIORITYR85_t GICD_IPRIORITYR85;
27999 volatile ALT_GIC_DIST_GICD_IPRIORITYR86_t GICD_IPRIORITYR86;
28000 volatile ALT_GIC_DIST_GICD_IPRIORITYR87_t GICD_IPRIORITYR87;
28001 volatile ALT_GIC_DIST_GICD_IPRIORITYR88_t GICD_IPRIORITYR88;
28002 volatile ALT_GIC_DIST_GICD_IPRIORITYR89_t GICD_IPRIORITYR89;
28003 volatile ALT_GIC_DIST_GICD_IPRIORITYR90_t GICD_IPRIORITYR90;
28004 volatile ALT_GIC_DIST_GICD_IPRIORITYR91_t GICD_IPRIORITYR91;
28005 volatile ALT_GIC_DIST_GICD_IPRIORITYR92_t GICD_IPRIORITYR92;
28006 volatile ALT_GIC_DIST_GICD_IPRIORITYR93_t GICD_IPRIORITYR93;
28007 volatile ALT_GIC_DIST_GICD_IPRIORITYR94_t GICD_IPRIORITYR94;
28008 volatile ALT_GIC_DIST_GICD_IPRIORITYR95_t GICD_IPRIORITYR95;
28009 volatile ALT_GIC_DIST_GICD_IPRIORITYR96_t GICD_IPRIORITYR96;
28010 volatile ALT_GIC_DIST_GICD_IPRIORITYR97_t GICD_IPRIORITYR97;
28011 volatile ALT_GIC_DIST_GICD_IPRIORITYR98_t GICD_IPRIORITYR98;
28012 volatile ALT_GIC_DIST_GICD_IPRIORITYR99_t GICD_IPRIORITYR99;
28013 volatile ALT_GIC_DIST_GICD_IPRIORITYR100_t GICD_IPRIORITYR100;
28014 volatile ALT_GIC_DIST_GICD_IPRIORITYR101_t GICD_IPRIORITYR101;
28015 volatile ALT_GIC_DIST_GICD_IPRIORITYR102_t GICD_IPRIORITYR102;
28016 volatile ALT_GIC_DIST_GICD_IPRIORITYR103_t GICD_IPRIORITYR103;
28017 volatile ALT_GIC_DIST_GICD_IPRIORITYR104_t GICD_IPRIORITYR104;
28018 volatile ALT_GIC_DIST_GICD_IPRIORITYR105_t GICD_IPRIORITYR105;
28019 volatile ALT_GIC_DIST_GICD_IPRIORITYR106_t GICD_IPRIORITYR106;
28020 volatile ALT_GIC_DIST_GICD_IPRIORITYR107_t GICD_IPRIORITYR107;
28021 volatile ALT_GIC_DIST_GICD_IPRIORITYR108_t GICD_IPRIORITYR108;
28022 volatile ALT_GIC_DIST_GICD_IPRIORITYR109_t GICD_IPRIORITYR109;
28023 volatile ALT_GIC_DIST_GICD_IPRIORITYR110_t GICD_IPRIORITYR110;
28024 volatile ALT_GIC_DIST_GICD_IPRIORITYR111_t GICD_IPRIORITYR111;
28025 volatile ALT_GIC_DIST_GICD_IPRIORITYR112_t GICD_IPRIORITYR112;
28026 volatile ALT_GIC_DIST_GICD_IPRIORITYR113_t GICD_IPRIORITYR113;
28027 volatile ALT_GIC_DIST_GICD_IPRIORITYR114_t GICD_IPRIORITYR114;
28028 volatile ALT_GIC_DIST_GICD_IPRIORITYR115_t GICD_IPRIORITYR115;
28029 volatile ALT_GIC_DIST_GICD_IPRIORITYR116_t GICD_IPRIORITYR116;
28030 volatile ALT_GIC_DIST_GICD_IPRIORITYR117_t GICD_IPRIORITYR117;
28031 volatile ALT_GIC_DIST_GICD_IPRIORITYR118_t GICD_IPRIORITYR118;
28032 volatile ALT_GIC_DIST_GICD_IPRIORITYR119_t GICD_IPRIORITYR119;
28033 volatile ALT_GIC_DIST_GICD_IPRIORITYR120_t GICD_IPRIORITYR120;
28034 volatile ALT_GIC_DIST_GICD_IPRIORITYR121_t GICD_IPRIORITYR121;
28035 volatile ALT_GIC_DIST_GICD_IPRIORITYR122_t GICD_IPRIORITYR122;
28036 volatile ALT_GIC_DIST_GICD_IPRIORITYR123_t GICD_IPRIORITYR123;
28037 volatile ALT_GIC_DIST_GICD_IPRIORITYR124_t GICD_IPRIORITYR124;
28038 volatile ALT_GIC_DIST_GICD_IPRIORITYR125_t GICD_IPRIORITYR125;
28039 volatile ALT_GIC_DIST_GICD_IPRIORITYR126_t GICD_IPRIORITYR126;
28040 volatile ALT_GIC_DIST_GICD_IPRIORITYR127_t GICD_IPRIORITYR127;
28041 volatile uint32_t _pad_0x600_0x7ff[128];
28042 volatile ALT_GIC_DIST_GICD_ITARGETSR0_t GICD_ITARGETSR0;
28043 volatile ALT_GIC_DIST_GICD_ITARGETSR1_t GICD_ITARGETSR1;
28044 volatile ALT_GIC_DIST_GICD_ITARGETSR2_t GICD_ITARGETSR2;
28045 volatile ALT_GIC_DIST_GICD_ITARGETSR3_t GICD_ITARGETSR3;
28046 volatile ALT_GIC_DIST_GICD_ITARGETSR4_t GICD_ITARGETSR4;
28047 volatile ALT_GIC_DIST_GICD_ITARGETSR5_t GICD_ITARGETSR5;
28048 volatile ALT_GIC_DIST_GICD_ITARGETSR6_t GICD_ITARGETSR6;
28049 volatile ALT_GIC_DIST_GICD_ITARGETSR7_t GICD_ITARGETSR7;
28050 volatile ALT_GIC_DIST_GICD_ITARGETSR8_t GICD_ITARGETSR8;
28051 volatile ALT_GIC_DIST_GICD_ITARGETSR9_t GICD_ITARGETSR9;
28052 volatile ALT_GIC_DIST_GICD_ITARGETSR10_t GICD_ITARGETSR10;
28053 volatile ALT_GIC_DIST_GICD_ITARGETSR11_t GICD_ITARGETSR11;
28054 volatile ALT_GIC_DIST_GICD_ITARGETSR12_t GICD_ITARGETSR12;
28055 volatile ALT_GIC_DIST_GICD_ITARGETSR13_t GICD_ITARGETSR13;
28056 volatile ALT_GIC_DIST_GICD_ITARGETSR14_t GICD_ITARGETSR14;
28057 volatile ALT_GIC_DIST_GICD_ITARGETSR15_t GICD_ITARGETSR15;
28058 volatile ALT_GIC_DIST_GICD_ITARGETSR16_t GICD_ITARGETSR16;
28059 volatile ALT_GIC_DIST_GICD_ITARGETSR17_t GICD_ITARGETSR17;
28060 volatile ALT_GIC_DIST_GICD_ITARGETSR18_t GICD_ITARGETSR18;
28061 volatile ALT_GIC_DIST_GICD_ITARGETSR19_t GICD_ITARGETSR19;
28062 volatile ALT_GIC_DIST_GICD_ITARGETSR20_t GICD_ITARGETSR20;
28063 volatile ALT_GIC_DIST_GICD_ITARGETSR21_t GICD_ITARGETSR21;
28064 volatile ALT_GIC_DIST_GICD_ITARGETSR22_t GICD_ITARGETSR22;
28065 volatile ALT_GIC_DIST_GICD_ITARGETSR23_t GICD_ITARGETSR23;
28066 volatile ALT_GIC_DIST_GICD_ITARGETSR24_t GICD_ITARGETSR24;
28067 volatile ALT_GIC_DIST_GICD_ITARGETSR25_t GICD_ITARGETSR25;
28068 volatile ALT_GIC_DIST_GICD_ITARGETSR26_t GICD_ITARGETSR26;
28069 volatile ALT_GIC_DIST_GICD_ITARGETSR27_t GICD_ITARGETSR27;
28070 volatile ALT_GIC_DIST_GICD_ITARGETSR28_t GICD_ITARGETSR28;
28071 volatile ALT_GIC_DIST_GICD_ITARGETSR29_t GICD_ITARGETSR29;
28072 volatile ALT_GIC_DIST_GICD_ITARGETSR30_t GICD_ITARGETSR30;
28073 volatile ALT_GIC_DIST_GICD_ITARGETSR31_t GICD_ITARGETSR31;
28074 volatile ALT_GIC_DIST_GICD_ITARGETSR32_t GICD_ITARGETSR32;
28075 volatile ALT_GIC_DIST_GICD_ITARGETSR33_t GICD_ITARGETSR33;
28076 volatile ALT_GIC_DIST_GICD_ITARGETSR34_t GICD_ITARGETSR34;
28077 volatile ALT_GIC_DIST_GICD_ITARGETSR35_t GICD_ITARGETSR35;
28078 volatile ALT_GIC_DIST_GICD_ITARGETSR36_t GICD_ITARGETSR36;
28079 volatile ALT_GIC_DIST_GICD_ITARGETSR37_t GICD_ITARGETSR37;
28080 volatile ALT_GIC_DIST_GICD_ITARGETSR38_t GICD_ITARGETSR38;
28081 volatile ALT_GIC_DIST_GICD_ITARGETSR39_t GICD_ITARGETSR39;
28082 volatile ALT_GIC_DIST_GICD_ITARGETSR40_t GICD_ITARGETSR40;
28083 volatile ALT_GIC_DIST_GICD_ITARGETSR41_t GICD_ITARGETSR41;
28084 volatile ALT_GIC_DIST_GICD_ITARGETSR42_t GICD_ITARGETSR42;
28085 volatile ALT_GIC_DIST_GICD_ITARGETSR43_t GICD_ITARGETSR43;
28086 volatile ALT_GIC_DIST_GICD_ITARGETSR44_t GICD_ITARGETSR44;
28087 volatile ALT_GIC_DIST_GICD_ITARGETSR45_t GICD_ITARGETSR45;
28088 volatile ALT_GIC_DIST_GICD_ITARGETSR46_t GICD_ITARGETSR46;
28089 volatile ALT_GIC_DIST_GICD_ITARGETSR47_t GICD_ITARGETSR47;
28090 volatile ALT_GIC_DIST_GICD_ITARGETSR48_t GICD_ITARGETSR48;
28091 volatile ALT_GIC_DIST_GICD_ITARGETSR49_t GICD_ITARGETSR49;
28092 volatile ALT_GIC_DIST_GICD_ITARGETSR50_t GICD_ITARGETSR50;
28093 volatile ALT_GIC_DIST_GICD_ITARGETSR51_t GICD_ITARGETSR51;
28094 volatile ALT_GIC_DIST_GICD_ITARGETSR52_t GICD_ITARGETSR52;
28095 volatile ALT_GIC_DIST_GICD_ITARGETSR53_t GICD_ITARGETSR53;
28096 volatile ALT_GIC_DIST_GICD_ITARGETSR54_t GICD_ITARGETSR54;
28097 volatile ALT_GIC_DIST_GICD_ITARGETSR55_t GICD_ITARGETSR55;
28098 volatile ALT_GIC_DIST_GICD_ITARGETSR56_t GICD_ITARGETSR56;
28099 volatile ALT_GIC_DIST_GICD_ITARGETSR57_t GICD_ITARGETSR57;
28100 volatile ALT_GIC_DIST_GICD_ITARGETSR58_t GICD_ITARGETSR58;
28101 volatile ALT_GIC_DIST_GICD_ITARGETSR59_t GICD_ITARGETSR59;
28102 volatile ALT_GIC_DIST_GICD_ITARGETSR60_t GICD_ITARGETSR60;
28103 volatile ALT_GIC_DIST_GICD_ITARGETSR61_t GICD_ITARGETSR61;
28104 volatile ALT_GIC_DIST_GICD_ITARGETSR62_t GICD_ITARGETSR62;
28105 volatile ALT_GIC_DIST_GICD_ITARGETSR63_t GICD_ITARGETSR63;
28106 volatile ALT_GIC_DIST_GICD_ITARGETSR64_t GICD_ITARGETSR64;
28107 volatile ALT_GIC_DIST_GICD_ITARGETSR65_t GICD_ITARGETSR65;
28108 volatile ALT_GIC_DIST_GICD_ITARGETSR66_t GICD_ITARGETSR66;
28109 volatile ALT_GIC_DIST_GICD_ITARGETSR67_t GICD_ITARGETSR67;
28110 volatile ALT_GIC_DIST_GICD_ITARGETSR68_t GICD_ITARGETSR68;
28111 volatile ALT_GIC_DIST_GICD_ITARGETSR69_t GICD_ITARGETSR69;
28112 volatile ALT_GIC_DIST_GICD_ITARGETSR70_t GICD_ITARGETSR70;
28113 volatile ALT_GIC_DIST_GICD_ITARGETSR71_t GICD_ITARGETSR71;
28114 volatile ALT_GIC_DIST_GICD_ITARGETSR72_t GICD_ITARGETSR72;
28115 volatile ALT_GIC_DIST_GICD_ITARGETSR73_t GICD_ITARGETSR73;
28116 volatile ALT_GIC_DIST_GICD_ITARGETSR74_t GICD_ITARGETSR74;
28117 volatile ALT_GIC_DIST_GICD_ITARGETSR75_t GICD_ITARGETSR75;
28118 volatile ALT_GIC_DIST_GICD_ITARGETSR76_t GICD_ITARGETSR76;
28119 volatile ALT_GIC_DIST_GICD_ITARGETSR77_t GICD_ITARGETSR77;
28120 volatile ALT_GIC_DIST_GICD_ITARGETSR78_t GICD_ITARGETSR78;
28121 volatile ALT_GIC_DIST_GICD_ITARGETSR79_t GICD_ITARGETSR79;
28122 volatile ALT_GIC_DIST_GICD_ITARGETSR80_t GICD_ITARGETSR80;
28123 volatile ALT_GIC_DIST_GICD_ITARGETSR81_t GICD_ITARGETSR81;
28124 volatile ALT_GIC_DIST_GICD_ITARGETSR82_t GICD_ITARGETSR82;
28125 volatile ALT_GIC_DIST_GICD_ITARGETSR83_t GICD_ITARGETSR83;
28126 volatile ALT_GIC_DIST_GICD_ITARGETSR84_t GICD_ITARGETSR84;
28127 volatile ALT_GIC_DIST_GICD_ITARGETSR85_t GICD_ITARGETSR85;
28128 volatile ALT_GIC_DIST_GICD_ITARGETSR86_t GICD_ITARGETSR86;
28129 volatile ALT_GIC_DIST_GICD_ITARGETSR87_t GICD_ITARGETSR87;
28130 volatile ALT_GIC_DIST_GICD_ITARGETSR88_t GICD_ITARGETSR88;
28131 volatile ALT_GIC_DIST_GICD_ITARGETSR89_t GICD_ITARGETSR89;
28132 volatile ALT_GIC_DIST_GICD_ITARGETSR90_t GICD_ITARGETSR90;
28133 volatile ALT_GIC_DIST_GICD_ITARGETSR91_t GICD_ITARGETSR91;
28134 volatile ALT_GIC_DIST_GICD_ITARGETSR92_t GICD_ITARGETSR92;
28135 volatile ALT_GIC_DIST_GICD_ITARGETSR93_t GICD_ITARGETSR93;
28136 volatile ALT_GIC_DIST_GICD_ITARGETSR94_t GICD_ITARGETSR94;
28137 volatile ALT_GIC_DIST_GICD_ITARGETSR95_t GICD_ITARGETSR95;
28138 volatile ALT_GIC_DIST_GICD_ITARGETSR96_t GICD_ITARGETSR96;
28139 volatile ALT_GIC_DIST_GICD_ITARGETSR97_t GICD_ITARGETSR97;
28140 volatile ALT_GIC_DIST_GICD_ITARGETSR98_t GICD_ITARGETSR98;
28141 volatile ALT_GIC_DIST_GICD_ITARGETSR99_t GICD_ITARGETSR99;
28142 volatile ALT_GIC_DIST_GICD_ITARGETSR100_t GICD_ITARGETSR100;
28143 volatile ALT_GIC_DIST_GICD_ITARGETSR101_t GICD_ITARGETSR101;
28144 volatile ALT_GIC_DIST_GICD_ITARGETSR102_t GICD_ITARGETSR102;
28145 volatile ALT_GIC_DIST_GICD_ITARGETSR103_t GICD_ITARGETSR103;
28146 volatile ALT_GIC_DIST_GICD_ITARGETSR104_t GICD_ITARGETSR104;
28147 volatile ALT_GIC_DIST_GICD_ITARGETSR105_t GICD_ITARGETSR105;
28148 volatile ALT_GIC_DIST_GICD_ITARGETSR106_t GICD_ITARGETSR106;
28149 volatile ALT_GIC_DIST_GICD_ITARGETSR107_t GICD_ITARGETSR107;
28150 volatile ALT_GIC_DIST_GICD_ITARGETSR108_t GICD_ITARGETSR108;
28151 volatile ALT_GIC_DIST_GICD_ITARGETSR109_t GICD_ITARGETSR109;
28152 volatile ALT_GIC_DIST_GICD_ITARGETSR110_t GICD_ITARGETSR110;
28153 volatile ALT_GIC_DIST_GICD_ITARGETSR111_t GICD_ITARGETSR111;
28154 volatile ALT_GIC_DIST_GICD_ITARGETSR112_t GICD_ITARGETSR112;
28155 volatile ALT_GIC_DIST_GICD_ITARGETSR113_t GICD_ITARGETSR113;
28156 volatile ALT_GIC_DIST_GICD_ITARGETSR114_t GICD_ITARGETSR114;
28157 volatile ALT_GIC_DIST_GICD_ITARGETSR115_t GICD_ITARGETSR115;
28158 volatile ALT_GIC_DIST_GICD_ITARGETSR116_t GICD_ITARGETSR116;
28159 volatile ALT_GIC_DIST_GICD_ITARGETSR117_t GICD_ITARGETSR117;
28160 volatile ALT_GIC_DIST_GICD_ITARGETSR118_t GICD_ITARGETSR118;
28161 volatile ALT_GIC_DIST_GICD_ITARGETSR119_t GICD_ITARGETSR119;
28162 volatile ALT_GIC_DIST_GICD_ITARGETSR120_t GICD_ITARGETSR120;
28163 volatile ALT_GIC_DIST_GICD_ITARGETSR121_t GICD_ITARGETSR121;
28164 volatile ALT_GIC_DIST_GICD_ITARGETSR122_t GICD_ITARGETSR122;
28165 volatile ALT_GIC_DIST_GICD_ITARGETSR123_t GICD_ITARGETSR123;
28166 volatile ALT_GIC_DIST_GICD_ITARGETSR124_t GICD_ITARGETSR124;
28167 volatile ALT_GIC_DIST_GICD_ITARGETSR125_t GICD_ITARGETSR125;
28168 volatile ALT_GIC_DIST_GICD_ITARGETSR126_t GICD_ITARGETSR126;
28169 volatile ALT_GIC_DIST_GICD_ITARGETSR127_t GICD_ITARGETSR127;
28170 volatile uint32_t _pad_0xa00_0xbff[128];
28171 volatile ALT_GIC_DIST_GICD_ICFGR0_t GICD_ICFGR0;
28172 volatile ALT_GIC_DIST_GICD_ICFGR1_t GICD_ICFGR1;
28173 volatile ALT_GIC_DIST_GICD_ICFGR2_t GICD_ICFGR2;
28174 volatile ALT_GIC_DIST_GICD_ICFGR3_t GICD_ICFGR3;
28175 volatile ALT_GIC_DIST_GICD_ICFGR4_t GICD_ICFGR4;
28176 volatile ALT_GIC_DIST_GICD_ICFGR5_t GICD_ICFGR5;
28177 volatile ALT_GIC_DIST_GICD_ICFGR6_t GICD_ICFGR6;
28178 volatile ALT_GIC_DIST_GICD_ICFGR7_t GICD_ICFGR7;
28179 volatile ALT_GIC_DIST_GICD_ICFGR8_t GICD_ICFGR8;
28180 volatile ALT_GIC_DIST_GICD_ICFGR9_t GICD_ICFGR9;
28181 volatile ALT_GIC_DIST_GICD_ICFGR10_t GICD_ICFGR10;
28182 volatile ALT_GIC_DIST_GICD_ICFGR11_t GICD_ICFGR11;
28183 volatile ALT_GIC_DIST_GICD_ICFGR12_t GICD_ICFGR12;
28184 volatile ALT_GIC_DIST_GICD_ICFGR13_t GICD_ICFGR13;
28185 volatile ALT_GIC_DIST_GICD_ICFGR14_t GICD_ICFGR14;
28186 volatile ALT_GIC_DIST_GICD_ICFGR15_t GICD_ICFGR15;
28187 volatile ALT_GIC_DIST_GICD_ICFGR16_t GICD_ICFGR16;
28188 volatile ALT_GIC_DIST_GICD_ICFGR17_t GICD_ICFGR17;
28189 volatile ALT_GIC_DIST_GICD_ICFGR18_t GICD_ICFGR18;
28190 volatile ALT_GIC_DIST_GICD_ICFGR19_t GICD_ICFGR19;
28191 volatile ALT_GIC_DIST_GICD_ICFGR20_t GICD_ICFGR20;
28192 volatile ALT_GIC_DIST_GICD_ICFGR21_t GICD_ICFGR21;
28193 volatile ALT_GIC_DIST_GICD_ICFGR22_t GICD_ICFGR22;
28194 volatile ALT_GIC_DIST_GICD_ICFGR23_t GICD_ICFGR23;
28195 volatile ALT_GIC_DIST_GICD_ICFGR24_t GICD_ICFGR24;
28196 volatile ALT_GIC_DIST_GICD_ICFGR25_t GICD_ICFGR25;
28197 volatile ALT_GIC_DIST_GICD_ICFGR26_t GICD_ICFGR26;
28198 volatile ALT_GIC_DIST_GICD_ICFGR27_t GICD_ICFGR27;
28199 volatile ALT_GIC_DIST_GICD_ICFGR28_t GICD_ICFGR28;
28200 volatile ALT_GIC_DIST_GICD_ICFGR29_t GICD_ICFGR29;
28201 volatile ALT_GIC_DIST_GICD_ICFGR30_t GICD_ICFGR30;
28202 volatile ALT_GIC_DIST_GICD_ICFGR31_t GICD_ICFGR31;
28203 volatile uint32_t _pad_0xc80_0xcff[32];
28204 volatile ALT_GIC_DIST_GICD_PPISR_t GICD_PPISR;
28205 volatile ALT_GIC_DIST_GICD_SPISR0_t GICD_SPISR0;
28206 volatile ALT_GIC_DIST_GICD_SPISR1_t GICD_SPISR1;
28207 volatile ALT_GIC_DIST_GICD_SPISR2_t GICD_SPISR2;
28208 volatile ALT_GIC_DIST_GICD_SPISR3_t GICD_SPISR3;
28209 volatile ALT_GIC_DIST_GICD_SPISR4_t GICD_SPISR4;
28210 volatile ALT_GIC_DIST_GICD_SPISR5_t GICD_SPISR5;
28211 volatile ALT_GIC_DIST_GICD_SPISR6_t GICD_SPISR6;
28212 volatile ALT_GIC_DIST_GICD_SPISR7_t GICD_SPISR7;
28213 volatile ALT_GIC_DIST_GICD_SPISR8_t GICD_SPISR8;
28214 volatile ALT_GIC_DIST_GICD_SPISR9_t GICD_SPISR9;
28215 volatile ALT_GIC_DIST_GICD_SPISR10_t GICD_SPISR10;
28216 volatile ALT_GIC_DIST_GICD_SPISR11_t GICD_SPISR11;
28217 volatile ALT_GIC_DIST_GICD_SPISR12_t GICD_SPISR12;
28218 volatile ALT_GIC_DIST_GICD_SPISR13_t GICD_SPISR13;
28219 volatile ALT_GIC_DIST_GICD_SPISR14_t GICD_SPISR14;
28220 volatile uint32_t _pad_0xd40_0xeff[112];
28221 volatile ALT_GIC_DIST_GICD_SGIR_t GICD_SGIR;
28222 volatile uint32_t _pad_0xf04_0xf0f[3];
28223 volatile ALT_GIC_DIST_GICD_CPENDSGIR0_t GICD_CPENDSGIR0;
28224 volatile ALT_GIC_DIST_GICD_CPENDSGIR1_t GICD_CPENDSGIR1;
28225 volatile ALT_GIC_DIST_GICD_CPENDSGIR2_t GICD_CPENDSGIR2;
28226 volatile ALT_GIC_DIST_GICD_CPENDSGIR3_t GICD_CPENDSGIR3;
28227 volatile ALT_GIC_DIST_GICD_SPENDSGIR0_t GICD_SPENDSGIR0;
28228 volatile ALT_GIC_DIST_GICD_SPENDSGIR1_t GICD_SPENDSGIR1;
28229 volatile ALT_GIC_DIST_GICD_SPENDSGIR2_t GICD_SPENDSGIR2;
28230 volatile ALT_GIC_DIST_GICD_SPENDSGIR3_t GICD_SPENDSGIR3;
28231 volatile uint32_t _pad_0xf30_0xfcf[40];
28232 volatile ALT_GIC_DIST_GICD_PIDR4_t GICD_PIDR4;
28233 volatile ALT_GIC_DIST_GICD_PIDR5_t GICD_PIDR5;
28234 volatile ALT_GIC_DIST_GICD_PIDR6_t GICD_PIDR6;
28235 volatile ALT_GIC_DIST_GICD_PIDR7_t GICD_PIDR7;
28236 volatile ALT_GIC_DIST_GICD_PIDR0_t GICD_PIDR0;
28237 volatile ALT_GIC_DIST_GICD_PIDR1_t GICD_PIDR1;
28238 volatile ALT_GIC_DIST_GICD_PIDR2_t GICD_PIDR2;
28239 volatile ALT_GIC_DIST_GICD_PIDR3_t GICD_PIDR3;
28240 volatile ALT_GIC_DIST_GICD_CIDR0_t GICD_CIDR0;
28241 volatile ALT_GIC_DIST_GICD_CIDR1_t GICD_CIDR1;
28242 volatile ALT_GIC_DIST_GICD_CIDR2_t GICD_CIDR2;
28243 volatile ALT_GIC_DIST_GICD_CIDR3_t GICD_CIDR3;
28247 typedef struct ALT_GIC_DIST_s ALT_GIC_DIST_t;
28249 struct ALT_GIC_DIST_raw_s
28251 volatile uint32_t GICD_CTLR;
28252 volatile uint32_t GICD_TYPER;
28253 volatile uint32_t GICD_IIDR;
28254 volatile uint32_t _pad_0xc_0x7f[29];
28255 volatile uint32_t GICD_IGROUPR0;
28256 volatile uint32_t GICD_IGROUPR1;
28257 volatile uint32_t GICD_IGROUPR2;
28258 volatile uint32_t GICD_IGROUPR3;
28259 volatile uint32_t GICD_IGROUPR4;
28260 volatile uint32_t GICD_IGROUPR5;
28261 volatile uint32_t GICD_IGROUPR6;
28262 volatile uint32_t GICD_IGROUPR7;
28263 volatile uint32_t GICD_IGROUPR8;
28264 volatile uint32_t GICD_IGROUPR9;
28265 volatile uint32_t GICD_IGROUPR10;
28266 volatile uint32_t GICD_IGROUPR11;
28267 volatile uint32_t GICD_IGROUPR12;
28268 volatile uint32_t GICD_IGROUPR13;
28269 volatile uint32_t GICD_IGROUPR14;
28270 volatile uint32_t GICD_IGROUPR15;
28271 volatile uint32_t _pad_0xc0_0xff[16];
28272 volatile uint32_t GICD_ISENABLER0;
28273 volatile uint32_t GICD_ISENABLER1;
28274 volatile uint32_t GICD_ISENABLER2;
28275 volatile uint32_t GICD_ISENABLER3;
28276 volatile uint32_t GICD_ISENABLER4;
28277 volatile uint32_t GICD_ISENABLER5;
28278 volatile uint32_t GICD_ISENABLER6;
28279 volatile uint32_t GICD_ISENABLER7;
28280 volatile uint32_t GICD_ISENABLER8;
28281 volatile uint32_t GICD_ISENABLER9;
28282 volatile uint32_t GICD_ISENABLER10;
28283 volatile uint32_t GICD_ISENABLER11;
28284 volatile uint32_t GICD_ISENABLER12;
28285 volatile uint32_t GICD_ISENABLER13;
28286 volatile uint32_t GICD_ISENABLER14;
28287 volatile uint32_t GICD_ISENABLER15;
28288 volatile uint32_t _pad_0x140_0x17f[16];
28289 volatile uint32_t GICD_ICENABLER0;
28290 volatile uint32_t GICD_ICENABLER1;
28291 volatile uint32_t GICD_ICENABLER2;
28292 volatile uint32_t GICD_ICENABLER3;
28293 volatile uint32_t GICD_ICENABLER4;
28294 volatile uint32_t GICD_ICENABLER5;
28295 volatile uint32_t GICD_ICENABLER6;
28296 volatile uint32_t GICD_ICENABLER7;
28297 volatile uint32_t GICD_ICENABLER8;
28298 volatile uint32_t GICD_ICENABLER9;
28299 volatile uint32_t GICD_ICENABLER10;
28300 volatile uint32_t GICD_ICENABLER11;
28301 volatile uint32_t GICD_ICENABLER12;
28302 volatile uint32_t GICD_ICENABLER13;
28303 volatile uint32_t GICD_ICENABLER14;
28304 volatile uint32_t GICD_ICENABLER15;
28305 volatile uint32_t _pad_0x1c0_0x1ff[16];
28306 volatile uint32_t GICD_ISPENDR0;
28307 volatile uint32_t GICD_ISPENDR1;
28308 volatile uint32_t GICD_ISPENDR2;
28309 volatile uint32_t GICD_ISPENDR3;
28310 volatile uint32_t GICD_ISPENDR4;
28311 volatile uint32_t GICD_ISPENDR5;
28312 volatile uint32_t GICD_ISPENDR6;
28313 volatile uint32_t GICD_ISPENDR7;
28314 volatile uint32_t GICD_ISPENDR8;
28315 volatile uint32_t GICD_ISPENDR9;
28316 volatile uint32_t GICD_ISPENDR10;
28317 volatile uint32_t GICD_ISPENDR11;
28318 volatile uint32_t GICD_ISPENDR12;
28319 volatile uint32_t GICD_ISPENDR13;
28320 volatile uint32_t GICD_ISPENDR14;
28321 volatile uint32_t GICD_ISPENDR15;
28322 volatile uint32_t _pad_0x240_0x27f[16];
28323 volatile uint32_t GICD_ICPENDR0;
28324 volatile uint32_t GICD_ICPENDR1;
28325 volatile uint32_t GICD_ICPENDR2;
28326 volatile uint32_t GICD_ICPENDR3;
28327 volatile uint32_t GICD_ICPENDR4;
28328 volatile uint32_t GICD_ICPENDR5;
28329 volatile uint32_t GICD_ICPENDR6;
28330 volatile uint32_t GICD_ICPENDR7;
28331 volatile uint32_t GICD_ICPENDR8;
28332 volatile uint32_t GICD_ICPENDR9;
28333 volatile uint32_t GICD_ICPENDR10;
28334 volatile uint32_t GICD_ICPENDR11;
28335 volatile uint32_t GICD_ICPENDR12;
28336 volatile uint32_t GICD_ICPENDR13;
28337 volatile uint32_t GICD_ICPENDR14;
28338 volatile uint32_t GICD_ICPENDR15;
28339 volatile uint32_t _pad_0x2c0_0x2ff[16];
28340 volatile uint32_t GICD_ISACTIVER0;
28341 volatile uint32_t GICD_ISACTIVER1;
28342 volatile uint32_t GICD_ISACTIVER2;
28343 volatile uint32_t GICD_ISACTIVER3;
28344 volatile uint32_t GICD_ISACTIVER4;
28345 volatile uint32_t GICD_ISACTIVER5;
28346 volatile uint32_t GICD_ISACTIVER6;
28347 volatile uint32_t GICD_ISACTIVER7;
28348 volatile uint32_t GICD_ISACTIVER8;
28349 volatile uint32_t GICD_ISACTIVER9;
28350 volatile uint32_t GICD_ISACTIVER10;
28351 volatile uint32_t GICD_ISACTIVER11;
28352 volatile uint32_t GICD_ISACTIVER12;
28353 volatile uint32_t GICD_ISACTIVER13;
28354 volatile uint32_t GICD_ISACTIVER14;
28355 volatile uint32_t GICD_ISACTIVER15;
28356 volatile uint32_t _pad_0x340_0x37f[16];
28357 volatile uint32_t GICD_ICACTIVER0;
28358 volatile uint32_t GICD_ICACTIVER1;
28359 volatile uint32_t GICD_ICACTIVER2;
28360 volatile uint32_t GICD_ICACTIVER3;
28361 volatile uint32_t GICD_ICACTIVER4;
28362 volatile uint32_t GICD_ICACTIVER5;
28363 volatile uint32_t GICD_ICACTIVER6;
28364 volatile uint32_t GICD_ICACTIVER7;
28365 volatile uint32_t GICD_ICACTIVER8;
28366 volatile uint32_t GICD_ICACTIVER9;
28367 volatile uint32_t GICD_ICACTIVER10;
28368 volatile uint32_t GICD_ICACTIVER11;
28369 volatile uint32_t GICD_ICACTIVER12;
28370 volatile uint32_t GICD_ICACTIVER13;
28371 volatile uint32_t GICD_ICACTIVER14;
28372 volatile uint32_t GICD_ICACTIVER15;
28373 volatile uint32_t _pad_0x3c0_0x3ff[16];
28374 volatile uint32_t GICD_IPRIORITYR0;
28375 volatile uint32_t GICD_IPRIORITYR1;
28376 volatile uint32_t GICD_IPRIORITYR2;
28377 volatile uint32_t GICD_IPRIORITYR3;
28378 volatile uint32_t GICD_IPRIORITYR4;
28379 volatile uint32_t GICD_IPRIORITYR5;
28380 volatile uint32_t GICD_IPRIORITYR6;
28381 volatile uint32_t GICD_IPRIORITYR7;
28382 volatile uint32_t GICD_IPRIORITYR8;
28383 volatile uint32_t GICD_IPRIORITYR9;
28384 volatile uint32_t GICD_IPRIORITYR10;
28385 volatile uint32_t GICD_IPRIORITYR11;
28386 volatile uint32_t GICD_IPRIORITYR12;
28387 volatile uint32_t GICD_IPRIORITYR13;
28388 volatile uint32_t GICD_IPRIORITYR14;
28389 volatile uint32_t GICD_IPRIORITYR15;
28390 volatile uint32_t GICD_IPRIORITYR16;
28391 volatile uint32_t GICD_IPRIORITYR17;
28392 volatile uint32_t GICD_IPRIORITYR18;
28393 volatile uint32_t GICD_IPRIORITYR19;
28394 volatile uint32_t GICD_IPRIORITYR20;
28395 volatile uint32_t GICD_IPRIORITYR21;
28396 volatile uint32_t GICD_IPRIORITYR22;
28397 volatile uint32_t GICD_IPRIORITYR23;
28398 volatile uint32_t GICD_IPRIORITYR24;
28399 volatile uint32_t GICD_IPRIORITYR25;
28400 volatile uint32_t GICD_IPRIORITYR26;
28401 volatile uint32_t GICD_IPRIORITYR27;
28402 volatile uint32_t GICD_IPRIORITYR28;
28403 volatile uint32_t GICD_IPRIORITYR29;
28404 volatile uint32_t GICD_IPRIORITYR30;
28405 volatile uint32_t GICD_IPRIORITYR31;
28406 volatile uint32_t GICD_IPRIORITYR32;
28407 volatile uint32_t GICD_IPRIORITYR33;
28408 volatile uint32_t GICD_IPRIORITYR34;
28409 volatile uint32_t GICD_IPRIORITYR35;
28410 volatile uint32_t GICD_IPRIORITYR36;
28411 volatile uint32_t GICD_IPRIORITYR37;
28412 volatile uint32_t GICD_IPRIORITYR38;
28413 volatile uint32_t GICD_IPRIORITYR39;
28414 volatile uint32_t GICD_IPRIORITYR40;
28415 volatile uint32_t GICD_IPRIORITYR41;
28416 volatile uint32_t GICD_IPRIORITYR42;
28417 volatile uint32_t GICD_IPRIORITYR43;
28418 volatile uint32_t GICD_IPRIORITYR44;
28419 volatile uint32_t GICD_IPRIORITYR45;
28420 volatile uint32_t GICD_IPRIORITYR46;
28421 volatile uint32_t GICD_IPRIORITYR47;
28422 volatile uint32_t GICD_IPRIORITYR48;
28423 volatile uint32_t GICD_IPRIORITYR49;
28424 volatile uint32_t GICD_IPRIORITYR50;
28425 volatile uint32_t GICD_IPRIORITYR51;
28426 volatile uint32_t GICD_IPRIORITYR52;
28427 volatile uint32_t GICD_IPRIORITYR53;
28428 volatile uint32_t GICD_IPRIORITYR54;
28429 volatile uint32_t GICD_IPRIORITYR55;
28430 volatile uint32_t GICD_IPRIORITYR56;
28431 volatile uint32_t GICD_IPRIORITYR57;
28432 volatile uint32_t GICD_IPRIORITYR58;
28433 volatile uint32_t GICD_IPRIORITYR59;
28434 volatile uint32_t GICD_IPRIORITYR60;
28435 volatile uint32_t GICD_IPRIORITYR61;
28436 volatile uint32_t GICD_IPRIORITYR62;
28437 volatile uint32_t GICD_IPRIORITYR63;
28438 volatile uint32_t GICD_IPRIORITYR64;
28439 volatile uint32_t GICD_IPRIORITYR65;
28440 volatile uint32_t GICD_IPRIORITYR66;
28441 volatile uint32_t GICD_IPRIORITYR67;
28442 volatile uint32_t GICD_IPRIORITYR68;
28443 volatile uint32_t GICD_IPRIORITYR69;
28444 volatile uint32_t GICD_IPRIORITYR70;
28445 volatile uint32_t GICD_IPRIORITYR71;
28446 volatile uint32_t GICD_IPRIORITYR72;
28447 volatile uint32_t GICD_IPRIORITYR73;
28448 volatile uint32_t GICD_IPRIORITYR74;
28449 volatile uint32_t GICD_IPRIORITYR75;
28450 volatile uint32_t GICD_IPRIORITYR76;
28451 volatile uint32_t GICD_IPRIORITYR77;
28452 volatile uint32_t GICD_IPRIORITYR78;
28453 volatile uint32_t GICD_IPRIORITYR79;
28454 volatile uint32_t GICD_IPRIORITYR80;
28455 volatile uint32_t GICD_IPRIORITYR81;
28456 volatile uint32_t GICD_IPRIORITYR82;
28457 volatile uint32_t GICD_IPRIORITYR83;
28458 volatile uint32_t GICD_IPRIORITYR84;
28459 volatile uint32_t GICD_IPRIORITYR85;
28460 volatile uint32_t GICD_IPRIORITYR86;
28461 volatile uint32_t GICD_IPRIORITYR87;
28462 volatile uint32_t GICD_IPRIORITYR88;
28463 volatile uint32_t GICD_IPRIORITYR89;
28464 volatile uint32_t GICD_IPRIORITYR90;
28465 volatile uint32_t GICD_IPRIORITYR91;
28466 volatile uint32_t GICD_IPRIORITYR92;
28467 volatile uint32_t GICD_IPRIORITYR93;
28468 volatile uint32_t GICD_IPRIORITYR94;
28469 volatile uint32_t GICD_IPRIORITYR95;
28470 volatile uint32_t GICD_IPRIORITYR96;
28471 volatile uint32_t GICD_IPRIORITYR97;
28472 volatile uint32_t GICD_IPRIORITYR98;
28473 volatile uint32_t GICD_IPRIORITYR99;
28474 volatile uint32_t GICD_IPRIORITYR100;
28475 volatile uint32_t GICD_IPRIORITYR101;
28476 volatile uint32_t GICD_IPRIORITYR102;
28477 volatile uint32_t GICD_IPRIORITYR103;
28478 volatile uint32_t GICD_IPRIORITYR104;
28479 volatile uint32_t GICD_IPRIORITYR105;
28480 volatile uint32_t GICD_IPRIORITYR106;
28481 volatile uint32_t GICD_IPRIORITYR107;
28482 volatile uint32_t GICD_IPRIORITYR108;
28483 volatile uint32_t GICD_IPRIORITYR109;
28484 volatile uint32_t GICD_IPRIORITYR110;
28485 volatile uint32_t GICD_IPRIORITYR111;
28486 volatile uint32_t GICD_IPRIORITYR112;
28487 volatile uint32_t GICD_IPRIORITYR113;
28488 volatile uint32_t GICD_IPRIORITYR114;
28489 volatile uint32_t GICD_IPRIORITYR115;
28490 volatile uint32_t GICD_IPRIORITYR116;
28491 volatile uint32_t GICD_IPRIORITYR117;
28492 volatile uint32_t GICD_IPRIORITYR118;
28493 volatile uint32_t GICD_IPRIORITYR119;
28494 volatile uint32_t GICD_IPRIORITYR120;
28495 volatile uint32_t GICD_IPRIORITYR121;
28496 volatile uint32_t GICD_IPRIORITYR122;
28497 volatile uint32_t GICD_IPRIORITYR123;
28498 volatile uint32_t GICD_IPRIORITYR124;
28499 volatile uint32_t GICD_IPRIORITYR125;
28500 volatile uint32_t GICD_IPRIORITYR126;
28501 volatile uint32_t GICD_IPRIORITYR127;
28502 volatile uint32_t _pad_0x600_0x7ff[128];
28503 volatile uint32_t GICD_ITARGETSR0;
28504 volatile uint32_t GICD_ITARGETSR1;
28505 volatile uint32_t GICD_ITARGETSR2;
28506 volatile uint32_t GICD_ITARGETSR3;
28507 volatile uint32_t GICD_ITARGETSR4;
28508 volatile uint32_t GICD_ITARGETSR5;
28509 volatile uint32_t GICD_ITARGETSR6;
28510 volatile uint32_t GICD_ITARGETSR7;
28511 volatile uint32_t GICD_ITARGETSR8;
28512 volatile uint32_t GICD_ITARGETSR9;
28513 volatile uint32_t GICD_ITARGETSR10;
28514 volatile uint32_t GICD_ITARGETSR11;
28515 volatile uint32_t GICD_ITARGETSR12;
28516 volatile uint32_t GICD_ITARGETSR13;
28517 volatile uint32_t GICD_ITARGETSR14;
28518 volatile uint32_t GICD_ITARGETSR15;
28519 volatile uint32_t GICD_ITARGETSR16;
28520 volatile uint32_t GICD_ITARGETSR17;
28521 volatile uint32_t GICD_ITARGETSR18;
28522 volatile uint32_t GICD_ITARGETSR19;
28523 volatile uint32_t GICD_ITARGETSR20;
28524 volatile uint32_t GICD_ITARGETSR21;
28525 volatile uint32_t GICD_ITARGETSR22;
28526 volatile uint32_t GICD_ITARGETSR23;
28527 volatile uint32_t GICD_ITARGETSR24;
28528 volatile uint32_t GICD_ITARGETSR25;
28529 volatile uint32_t GICD_ITARGETSR26;
28530 volatile uint32_t GICD_ITARGETSR27;
28531 volatile uint32_t GICD_ITARGETSR28;
28532 volatile uint32_t GICD_ITARGETSR29;
28533 volatile uint32_t GICD_ITARGETSR30;
28534 volatile uint32_t GICD_ITARGETSR31;
28535 volatile uint32_t GICD_ITARGETSR32;
28536 volatile uint32_t GICD_ITARGETSR33;
28537 volatile uint32_t GICD_ITARGETSR34;
28538 volatile uint32_t GICD_ITARGETSR35;
28539 volatile uint32_t GICD_ITARGETSR36;
28540 volatile uint32_t GICD_ITARGETSR37;
28541 volatile uint32_t GICD_ITARGETSR38;
28542 volatile uint32_t GICD_ITARGETSR39;
28543 volatile uint32_t GICD_ITARGETSR40;
28544 volatile uint32_t GICD_ITARGETSR41;
28545 volatile uint32_t GICD_ITARGETSR42;
28546 volatile uint32_t GICD_ITARGETSR43;
28547 volatile uint32_t GICD_ITARGETSR44;
28548 volatile uint32_t GICD_ITARGETSR45;
28549 volatile uint32_t GICD_ITARGETSR46;
28550 volatile uint32_t GICD_ITARGETSR47;
28551 volatile uint32_t GICD_ITARGETSR48;
28552 volatile uint32_t GICD_ITARGETSR49;
28553 volatile uint32_t GICD_ITARGETSR50;
28554 volatile uint32_t GICD_ITARGETSR51;
28555 volatile uint32_t GICD_ITARGETSR52;
28556 volatile uint32_t GICD_ITARGETSR53;
28557 volatile uint32_t GICD_ITARGETSR54;
28558 volatile uint32_t GICD_ITARGETSR55;
28559 volatile uint32_t GICD_ITARGETSR56;
28560 volatile uint32_t GICD_ITARGETSR57;
28561 volatile uint32_t GICD_ITARGETSR58;
28562 volatile uint32_t GICD_ITARGETSR59;
28563 volatile uint32_t GICD_ITARGETSR60;
28564 volatile uint32_t GICD_ITARGETSR61;
28565 volatile uint32_t GICD_ITARGETSR62;
28566 volatile uint32_t GICD_ITARGETSR63;
28567 volatile uint32_t GICD_ITARGETSR64;
28568 volatile uint32_t GICD_ITARGETSR65;
28569 volatile uint32_t GICD_ITARGETSR66;
28570 volatile uint32_t GICD_ITARGETSR67;
28571 volatile uint32_t GICD_ITARGETSR68;
28572 volatile uint32_t GICD_ITARGETSR69;
28573 volatile uint32_t GICD_ITARGETSR70;
28574 volatile uint32_t GICD_ITARGETSR71;
28575 volatile uint32_t GICD_ITARGETSR72;
28576 volatile uint32_t GICD_ITARGETSR73;
28577 volatile uint32_t GICD_ITARGETSR74;
28578 volatile uint32_t GICD_ITARGETSR75;
28579 volatile uint32_t GICD_ITARGETSR76;
28580 volatile uint32_t GICD_ITARGETSR77;
28581 volatile uint32_t GICD_ITARGETSR78;
28582 volatile uint32_t GICD_ITARGETSR79;
28583 volatile uint32_t GICD_ITARGETSR80;
28584 volatile uint32_t GICD_ITARGETSR81;
28585 volatile uint32_t GICD_ITARGETSR82;
28586 volatile uint32_t GICD_ITARGETSR83;
28587 volatile uint32_t GICD_ITARGETSR84;
28588 volatile uint32_t GICD_ITARGETSR85;
28589 volatile uint32_t GICD_ITARGETSR86;
28590 volatile uint32_t GICD_ITARGETSR87;
28591 volatile uint32_t GICD_ITARGETSR88;
28592 volatile uint32_t GICD_ITARGETSR89;
28593 volatile uint32_t GICD_ITARGETSR90;
28594 volatile uint32_t GICD_ITARGETSR91;
28595 volatile uint32_t GICD_ITARGETSR92;
28596 volatile uint32_t GICD_ITARGETSR93;
28597 volatile uint32_t GICD_ITARGETSR94;
28598 volatile uint32_t GICD_ITARGETSR95;
28599 volatile uint32_t GICD_ITARGETSR96;
28600 volatile uint32_t GICD_ITARGETSR97;
28601 volatile uint32_t GICD_ITARGETSR98;
28602 volatile uint32_t GICD_ITARGETSR99;
28603 volatile uint32_t GICD_ITARGETSR100;
28604 volatile uint32_t GICD_ITARGETSR101;
28605 volatile uint32_t GICD_ITARGETSR102;
28606 volatile uint32_t GICD_ITARGETSR103;
28607 volatile uint32_t GICD_ITARGETSR104;
28608 volatile uint32_t GICD_ITARGETSR105;
28609 volatile uint32_t GICD_ITARGETSR106;
28610 volatile uint32_t GICD_ITARGETSR107;
28611 volatile uint32_t GICD_ITARGETSR108;
28612 volatile uint32_t GICD_ITARGETSR109;
28613 volatile uint32_t GICD_ITARGETSR110;
28614 volatile uint32_t GICD_ITARGETSR111;
28615 volatile uint32_t GICD_ITARGETSR112;
28616 volatile uint32_t GICD_ITARGETSR113;
28617 volatile uint32_t GICD_ITARGETSR114;
28618 volatile uint32_t GICD_ITARGETSR115;
28619 volatile uint32_t GICD_ITARGETSR116;
28620 volatile uint32_t GICD_ITARGETSR117;
28621 volatile uint32_t GICD_ITARGETSR118;
28622 volatile uint32_t GICD_ITARGETSR119;
28623 volatile uint32_t GICD_ITARGETSR120;
28624 volatile uint32_t GICD_ITARGETSR121;
28625 volatile uint32_t GICD_ITARGETSR122;
28626 volatile uint32_t GICD_ITARGETSR123;
28627 volatile uint32_t GICD_ITARGETSR124;
28628 volatile uint32_t GICD_ITARGETSR125;
28629 volatile uint32_t GICD_ITARGETSR126;
28630 volatile uint32_t GICD_ITARGETSR127;
28631 volatile uint32_t _pad_0xa00_0xbff[128];
28632 volatile uint32_t GICD_ICFGR0;
28633 volatile uint32_t GICD_ICFGR1;
28634 volatile uint32_t GICD_ICFGR2;
28635 volatile uint32_t GICD_ICFGR3;
28636 volatile uint32_t GICD_ICFGR4;
28637 volatile uint32_t GICD_ICFGR5;
28638 volatile uint32_t GICD_ICFGR6;
28639 volatile uint32_t GICD_ICFGR7;
28640 volatile uint32_t GICD_ICFGR8;
28641 volatile uint32_t GICD_ICFGR9;
28642 volatile uint32_t GICD_ICFGR10;
28643 volatile uint32_t GICD_ICFGR11;
28644 volatile uint32_t GICD_ICFGR12;
28645 volatile uint32_t GICD_ICFGR13;
28646 volatile uint32_t GICD_ICFGR14;
28647 volatile uint32_t GICD_ICFGR15;
28648 volatile uint32_t GICD_ICFGR16;
28649 volatile uint32_t GICD_ICFGR17;
28650 volatile uint32_t GICD_ICFGR18;
28651 volatile uint32_t GICD_ICFGR19;
28652 volatile uint32_t GICD_ICFGR20;
28653 volatile uint32_t GICD_ICFGR21;
28654 volatile uint32_t GICD_ICFGR22;
28655 volatile uint32_t GICD_ICFGR23;
28656 volatile uint32_t GICD_ICFGR24;
28657 volatile uint32_t GICD_ICFGR25;
28658 volatile uint32_t GICD_ICFGR26;
28659 volatile uint32_t GICD_ICFGR27;
28660 volatile uint32_t GICD_ICFGR28;
28661 volatile uint32_t GICD_ICFGR29;
28662 volatile uint32_t GICD_ICFGR30;
28663 volatile uint32_t GICD_ICFGR31;
28664 volatile uint32_t _pad_0xc80_0xcff[32];
28665 volatile uint32_t GICD_PPISR;
28666 volatile uint32_t GICD_SPISR0;
28667 volatile uint32_t GICD_SPISR1;
28668 volatile uint32_t GICD_SPISR2;
28669 volatile uint32_t GICD_SPISR3;
28670 volatile uint32_t GICD_SPISR4;
28671 volatile uint32_t GICD_SPISR5;
28672 volatile uint32_t GICD_SPISR6;
28673 volatile uint32_t GICD_SPISR7;
28674 volatile uint32_t GICD_SPISR8;
28675 volatile uint32_t GICD_SPISR9;
28676 volatile uint32_t GICD_SPISR10;
28677 volatile uint32_t GICD_SPISR11;
28678 volatile uint32_t GICD_SPISR12;
28679 volatile uint32_t GICD_SPISR13;
28680 volatile uint32_t GICD_SPISR14;
28681 volatile uint32_t _pad_0xd40_0xeff[112];
28682 volatile uint32_t GICD_SGIR;
28683 volatile uint32_t _pad_0xf04_0xf0f[3];
28684 volatile uint32_t GICD_CPENDSGIR0;
28685 volatile uint32_t GICD_CPENDSGIR1;
28686 volatile uint32_t GICD_CPENDSGIR2;
28687 volatile uint32_t GICD_CPENDSGIR3;
28688 volatile uint32_t GICD_SPENDSGIR0;
28689 volatile uint32_t GICD_SPENDSGIR1;
28690 volatile uint32_t GICD_SPENDSGIR2;
28691 volatile uint32_t GICD_SPENDSGIR3;
28692 volatile uint32_t _pad_0xf30_0xfcf[40];
28693 volatile uint32_t GICD_PIDR4;
28694 volatile uint32_t GICD_PIDR5;
28695 volatile uint32_t GICD_PIDR6;
28696 volatile uint32_t GICD_PIDR7;
28697 volatile uint32_t GICD_PIDR0;
28698 volatile uint32_t GICD_PIDR1;
28699 volatile uint32_t GICD_PIDR2;
28700 volatile uint32_t GICD_PIDR3;
28701 volatile uint32_t GICD_CIDR0;
28702 volatile uint32_t GICD_CIDR1;
28703 volatile uint32_t GICD_CIDR2;
28704 volatile uint32_t GICD_CIDR3;
28708 typedef struct ALT_GIC_DIST_raw_s ALT_GIC_DIST_raw_t;
28741 #define ALT_GIC_CPUIF_GICC_CTLR_FLD_LSB 0
28743 #define ALT_GIC_CPUIF_GICC_CTLR_FLD_MSB 31
28745 #define ALT_GIC_CPUIF_GICC_CTLR_FLD_WIDTH 32
28747 #define ALT_GIC_CPUIF_GICC_CTLR_FLD_SET_MSK 0xffffffff
28749 #define ALT_GIC_CPUIF_GICC_CTLR_FLD_CLR_MSK 0x00000000
28751 #define ALT_GIC_CPUIF_GICC_CTLR_FLD_RESET 0x0
28753 #define ALT_GIC_CPUIF_GICC_CTLR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
28755 #define ALT_GIC_CPUIF_GICC_CTLR_FLD_SET(value) (((value) << 0) & 0xffffffff)
28757 #ifndef __ASSEMBLY__
28769 struct ALT_GIC_CPUIF_GICC_CTLR_s
28771 volatile uint32_t fld : 32;
28775 typedef struct ALT_GIC_CPUIF_GICC_CTLR_s ALT_GIC_CPUIF_GICC_CTLR_t;
28779 #define ALT_GIC_CPUIF_GICC_CTLR_RESET 0x00000000
28781 #define ALT_GIC_CPUIF_GICC_CTLR_OFST 0x0
28804 #define ALT_GIC_CPUIF_GICC_PMR_FLD_LSB 0
28806 #define ALT_GIC_CPUIF_GICC_PMR_FLD_MSB 31
28808 #define ALT_GIC_CPUIF_GICC_PMR_FLD_WIDTH 32
28810 #define ALT_GIC_CPUIF_GICC_PMR_FLD_SET_MSK 0xffffffff
28812 #define ALT_GIC_CPUIF_GICC_PMR_FLD_CLR_MSK 0x00000000
28814 #define ALT_GIC_CPUIF_GICC_PMR_FLD_RESET 0x0
28816 #define ALT_GIC_CPUIF_GICC_PMR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
28818 #define ALT_GIC_CPUIF_GICC_PMR_FLD_SET(value) (((value) << 0) & 0xffffffff)
28820 #ifndef __ASSEMBLY__
28832 struct ALT_GIC_CPUIF_GICC_PMR_s
28834 volatile uint32_t fld : 32;
28838 typedef struct ALT_GIC_CPUIF_GICC_PMR_s ALT_GIC_CPUIF_GICC_PMR_t;
28842 #define ALT_GIC_CPUIF_GICC_PMR_RESET 0x00000000
28844 #define ALT_GIC_CPUIF_GICC_PMR_OFST 0x4
28867 #define ALT_GIC_CPUIF_GICC_BPR_FLD_LSB 0
28869 #define ALT_GIC_CPUIF_GICC_BPR_FLD_MSB 31
28871 #define ALT_GIC_CPUIF_GICC_BPR_FLD_WIDTH 32
28873 #define ALT_GIC_CPUIF_GICC_BPR_FLD_SET_MSK 0xffffffff
28875 #define ALT_GIC_CPUIF_GICC_BPR_FLD_CLR_MSK 0x00000000
28877 #define ALT_GIC_CPUIF_GICC_BPR_FLD_RESET 0x0
28879 #define ALT_GIC_CPUIF_GICC_BPR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
28881 #define ALT_GIC_CPUIF_GICC_BPR_FLD_SET(value) (((value) << 0) & 0xffffffff)
28883 #ifndef __ASSEMBLY__
28895 struct ALT_GIC_CPUIF_GICC_BPR_s
28897 volatile uint32_t fld : 32;
28901 typedef struct ALT_GIC_CPUIF_GICC_BPR_s ALT_GIC_CPUIF_GICC_BPR_t;
28905 #define ALT_GIC_CPUIF_GICC_BPR_RESET 0x00000002
28907 #define ALT_GIC_CPUIF_GICC_BPR_OFST 0x8
28930 #define ALT_GIC_CPUIF_GICC_IAR_FLD_LSB 0
28932 #define ALT_GIC_CPUIF_GICC_IAR_FLD_MSB 31
28934 #define ALT_GIC_CPUIF_GICC_IAR_FLD_WIDTH 32
28936 #define ALT_GIC_CPUIF_GICC_IAR_FLD_SET_MSK 0xffffffff
28938 #define ALT_GIC_CPUIF_GICC_IAR_FLD_CLR_MSK 0x00000000
28940 #define ALT_GIC_CPUIF_GICC_IAR_FLD_RESET 0x0
28942 #define ALT_GIC_CPUIF_GICC_IAR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
28944 #define ALT_GIC_CPUIF_GICC_IAR_FLD_SET(value) (((value) << 0) & 0xffffffff)
28946 #ifndef __ASSEMBLY__
28958 struct ALT_GIC_CPUIF_GICC_IAR_s
28960 volatile uint32_t fld : 32;
28964 typedef struct ALT_GIC_CPUIF_GICC_IAR_s ALT_GIC_CPUIF_GICC_IAR_t;
28968 #define ALT_GIC_CPUIF_GICC_IAR_RESET 0x000003ff
28970 #define ALT_GIC_CPUIF_GICC_IAR_OFST 0xc
28993 #define ALT_GIC_CPUIF_GICC_EOIR_FLD_LSB 0
28995 #define ALT_GIC_CPUIF_GICC_EOIR_FLD_MSB 31
28997 #define ALT_GIC_CPUIF_GICC_EOIR_FLD_WIDTH 32
28999 #define ALT_GIC_CPUIF_GICC_EOIR_FLD_SET_MSK 0xffffffff
29001 #define ALT_GIC_CPUIF_GICC_EOIR_FLD_CLR_MSK 0x00000000
29003 #define ALT_GIC_CPUIF_GICC_EOIR_FLD_RESET 0x0
29005 #define ALT_GIC_CPUIF_GICC_EOIR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29007 #define ALT_GIC_CPUIF_GICC_EOIR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29009 #ifndef __ASSEMBLY__
29021 struct ALT_GIC_CPUIF_GICC_EOIR_s
29023 volatile uint32_t fld : 32;
29027 typedef struct ALT_GIC_CPUIF_GICC_EOIR_s ALT_GIC_CPUIF_GICC_EOIR_t;
29031 #define ALT_GIC_CPUIF_GICC_EOIR_RESET 0x00000000
29033 #define ALT_GIC_CPUIF_GICC_EOIR_OFST 0x10
29056 #define ALT_GIC_CPUIF_GICC_RPR_FLD_LSB 0
29058 #define ALT_GIC_CPUIF_GICC_RPR_FLD_MSB 31
29060 #define ALT_GIC_CPUIF_GICC_RPR_FLD_WIDTH 32
29062 #define ALT_GIC_CPUIF_GICC_RPR_FLD_SET_MSK 0xffffffff
29064 #define ALT_GIC_CPUIF_GICC_RPR_FLD_CLR_MSK 0x00000000
29066 #define ALT_GIC_CPUIF_GICC_RPR_FLD_RESET 0x0
29068 #define ALT_GIC_CPUIF_GICC_RPR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29070 #define ALT_GIC_CPUIF_GICC_RPR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29072 #ifndef __ASSEMBLY__
29084 struct ALT_GIC_CPUIF_GICC_RPR_s
29086 volatile uint32_t fld : 32;
29090 typedef struct ALT_GIC_CPUIF_GICC_RPR_s ALT_GIC_CPUIF_GICC_RPR_t;
29094 #define ALT_GIC_CPUIF_GICC_RPR_RESET 0x000000ff
29096 #define ALT_GIC_CPUIF_GICC_RPR_OFST 0x14
29119 #define ALT_GIC_CPUIF_GICC_HPPIR_FLD_LSB 0
29121 #define ALT_GIC_CPUIF_GICC_HPPIR_FLD_MSB 31
29123 #define ALT_GIC_CPUIF_GICC_HPPIR_FLD_WIDTH 32
29125 #define ALT_GIC_CPUIF_GICC_HPPIR_FLD_SET_MSK 0xffffffff
29127 #define ALT_GIC_CPUIF_GICC_HPPIR_FLD_CLR_MSK 0x00000000
29129 #define ALT_GIC_CPUIF_GICC_HPPIR_FLD_RESET 0x0
29131 #define ALT_GIC_CPUIF_GICC_HPPIR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29133 #define ALT_GIC_CPUIF_GICC_HPPIR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29135 #ifndef __ASSEMBLY__
29147 struct ALT_GIC_CPUIF_GICC_HPPIR_s
29149 volatile uint32_t fld : 32;
29153 typedef struct ALT_GIC_CPUIF_GICC_HPPIR_s ALT_GIC_CPUIF_GICC_HPPIR_t;
29157 #define ALT_GIC_CPUIF_GICC_HPPIR_RESET 0x000003ff
29159 #define ALT_GIC_CPUIF_GICC_HPPIR_OFST 0x18
29182 #define ALT_GIC_CPUIF_GICC_ABPR_FLD_LSB 0
29184 #define ALT_GIC_CPUIF_GICC_ABPR_FLD_MSB 31
29186 #define ALT_GIC_CPUIF_GICC_ABPR_FLD_WIDTH 32
29188 #define ALT_GIC_CPUIF_GICC_ABPR_FLD_SET_MSK 0xffffffff
29190 #define ALT_GIC_CPUIF_GICC_ABPR_FLD_CLR_MSK 0x00000000
29192 #define ALT_GIC_CPUIF_GICC_ABPR_FLD_RESET 0x0
29194 #define ALT_GIC_CPUIF_GICC_ABPR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29196 #define ALT_GIC_CPUIF_GICC_ABPR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29198 #ifndef __ASSEMBLY__
29210 struct ALT_GIC_CPUIF_GICC_ABPR_s
29212 volatile uint32_t fld : 32;
29216 typedef struct ALT_GIC_CPUIF_GICC_ABPR_s ALT_GIC_CPUIF_GICC_ABPR_t;
29220 #define ALT_GIC_CPUIF_GICC_ABPR_RESET 0x00000003
29222 #define ALT_GIC_CPUIF_GICC_ABPR_OFST 0x1c
29245 #define ALT_GIC_CPUIF_GICC_AIAR_FLD_LSB 0
29247 #define ALT_GIC_CPUIF_GICC_AIAR_FLD_MSB 31
29249 #define ALT_GIC_CPUIF_GICC_AIAR_FLD_WIDTH 32
29251 #define ALT_GIC_CPUIF_GICC_AIAR_FLD_SET_MSK 0xffffffff
29253 #define ALT_GIC_CPUIF_GICC_AIAR_FLD_CLR_MSK 0x00000000
29255 #define ALT_GIC_CPUIF_GICC_AIAR_FLD_RESET 0x0
29257 #define ALT_GIC_CPUIF_GICC_AIAR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29259 #define ALT_GIC_CPUIF_GICC_AIAR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29261 #ifndef __ASSEMBLY__
29273 struct ALT_GIC_CPUIF_GICC_AIAR_s
29275 volatile uint32_t fld : 32;
29279 typedef struct ALT_GIC_CPUIF_GICC_AIAR_s ALT_GIC_CPUIF_GICC_AIAR_t;
29283 #define ALT_GIC_CPUIF_GICC_AIAR_RESET 0x000003ff
29285 #define ALT_GIC_CPUIF_GICC_AIAR_OFST 0x20
29308 #define ALT_GIC_CPUIF_GICC_AEOIR_FLD_LSB 0
29310 #define ALT_GIC_CPUIF_GICC_AEOIR_FLD_MSB 31
29312 #define ALT_GIC_CPUIF_GICC_AEOIR_FLD_WIDTH 32
29314 #define ALT_GIC_CPUIF_GICC_AEOIR_FLD_SET_MSK 0xffffffff
29316 #define ALT_GIC_CPUIF_GICC_AEOIR_FLD_CLR_MSK 0x00000000
29318 #define ALT_GIC_CPUIF_GICC_AEOIR_FLD_RESET 0x0
29320 #define ALT_GIC_CPUIF_GICC_AEOIR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29322 #define ALT_GIC_CPUIF_GICC_AEOIR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29324 #ifndef __ASSEMBLY__
29336 struct ALT_GIC_CPUIF_GICC_AEOIR_s
29338 volatile uint32_t fld : 32;
29342 typedef struct ALT_GIC_CPUIF_GICC_AEOIR_s ALT_GIC_CPUIF_GICC_AEOIR_t;
29346 #define ALT_GIC_CPUIF_GICC_AEOIR_RESET 0x00000000
29348 #define ALT_GIC_CPUIF_GICC_AEOIR_OFST 0x24
29371 #define ALT_GIC_CPUIF_GICC_AHPPIR_FLD_LSB 0
29373 #define ALT_GIC_CPUIF_GICC_AHPPIR_FLD_MSB 31
29375 #define ALT_GIC_CPUIF_GICC_AHPPIR_FLD_WIDTH 32
29377 #define ALT_GIC_CPUIF_GICC_AHPPIR_FLD_SET_MSK 0xffffffff
29379 #define ALT_GIC_CPUIF_GICC_AHPPIR_FLD_CLR_MSK 0x00000000
29381 #define ALT_GIC_CPUIF_GICC_AHPPIR_FLD_RESET 0x0
29383 #define ALT_GIC_CPUIF_GICC_AHPPIR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29385 #define ALT_GIC_CPUIF_GICC_AHPPIR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29387 #ifndef __ASSEMBLY__
29399 struct ALT_GIC_CPUIF_GICC_AHPPIR_s
29401 volatile uint32_t fld : 32;
29405 typedef struct ALT_GIC_CPUIF_GICC_AHPPIR_s ALT_GIC_CPUIF_GICC_AHPPIR_t;
29409 #define ALT_GIC_CPUIF_GICC_AHPPIR_RESET 0x000003ff
29411 #define ALT_GIC_CPUIF_GICC_AHPPIR_OFST 0x28
29434 #define ALT_GIC_CPUIF_GICC_APR0_FLD_LSB 0
29436 #define ALT_GIC_CPUIF_GICC_APR0_FLD_MSB 31
29438 #define ALT_GIC_CPUIF_GICC_APR0_FLD_WIDTH 32
29440 #define ALT_GIC_CPUIF_GICC_APR0_FLD_SET_MSK 0xffffffff
29442 #define ALT_GIC_CPUIF_GICC_APR0_FLD_CLR_MSK 0x00000000
29444 #define ALT_GIC_CPUIF_GICC_APR0_FLD_RESET 0x0
29446 #define ALT_GIC_CPUIF_GICC_APR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29448 #define ALT_GIC_CPUIF_GICC_APR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
29450 #ifndef __ASSEMBLY__
29462 struct ALT_GIC_CPUIF_GICC_APR0_s
29464 volatile uint32_t fld : 32;
29468 typedef struct ALT_GIC_CPUIF_GICC_APR0_s ALT_GIC_CPUIF_GICC_APR0_t;
29472 #define ALT_GIC_CPUIF_GICC_APR0_RESET 0x00000000
29474 #define ALT_GIC_CPUIF_GICC_APR0_OFST 0xd0
29497 #define ALT_GIC_CPUIF_GICC_NSAPR0_FLD_LSB 0
29499 #define ALT_GIC_CPUIF_GICC_NSAPR0_FLD_MSB 31
29501 #define ALT_GIC_CPUIF_GICC_NSAPR0_FLD_WIDTH 32
29503 #define ALT_GIC_CPUIF_GICC_NSAPR0_FLD_SET_MSK 0xffffffff
29505 #define ALT_GIC_CPUIF_GICC_NSAPR0_FLD_CLR_MSK 0x00000000
29507 #define ALT_GIC_CPUIF_GICC_NSAPR0_FLD_RESET 0x0
29509 #define ALT_GIC_CPUIF_GICC_NSAPR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29511 #define ALT_GIC_CPUIF_GICC_NSAPR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
29513 #ifndef __ASSEMBLY__
29525 struct ALT_GIC_CPUIF_GICC_NSAPR0_s
29527 volatile uint32_t fld : 32;
29531 typedef struct ALT_GIC_CPUIF_GICC_NSAPR0_s ALT_GIC_CPUIF_GICC_NSAPR0_t;
29535 #define ALT_GIC_CPUIF_GICC_NSAPR0_RESET 0x00000000
29537 #define ALT_GIC_CPUIF_GICC_NSAPR0_OFST 0xe0
29560 #define ALT_GIC_CPUIF_GICC_IIDR_FLD_LSB 0
29562 #define ALT_GIC_CPUIF_GICC_IIDR_FLD_MSB 31
29564 #define ALT_GIC_CPUIF_GICC_IIDR_FLD_WIDTH 32
29566 #define ALT_GIC_CPUIF_GICC_IIDR_FLD_SET_MSK 0xffffffff
29568 #define ALT_GIC_CPUIF_GICC_IIDR_FLD_CLR_MSK 0x00000000
29570 #define ALT_GIC_CPUIF_GICC_IIDR_FLD_RESET 0x202143b
29572 #define ALT_GIC_CPUIF_GICC_IIDR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29574 #define ALT_GIC_CPUIF_GICC_IIDR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29576 #ifndef __ASSEMBLY__
29588 struct ALT_GIC_CPUIF_GICC_IIDR_s
29590 volatile uint32_t fld : 32;
29594 typedef struct ALT_GIC_CPUIF_GICC_IIDR_s ALT_GIC_CPUIF_GICC_IIDR_t;
29598 #define ALT_GIC_CPUIF_GICC_IIDR_RESET 0x0202143b
29600 #define ALT_GIC_CPUIF_GICC_IIDR_OFST 0xfc
29623 #define ALT_GIC_CPUIF_GICC_DIR_FLD_LSB 0
29625 #define ALT_GIC_CPUIF_GICC_DIR_FLD_MSB 31
29627 #define ALT_GIC_CPUIF_GICC_DIR_FLD_WIDTH 32
29629 #define ALT_GIC_CPUIF_GICC_DIR_FLD_SET_MSK 0xffffffff
29631 #define ALT_GIC_CPUIF_GICC_DIR_FLD_CLR_MSK 0x00000000
29633 #define ALT_GIC_CPUIF_GICC_DIR_FLD_RESET 0x0
29635 #define ALT_GIC_CPUIF_GICC_DIR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29637 #define ALT_GIC_CPUIF_GICC_DIR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29639 #ifndef __ASSEMBLY__
29651 struct ALT_GIC_CPUIF_GICC_DIR_s
29653 volatile uint32_t fld : 32;
29657 typedef struct ALT_GIC_CPUIF_GICC_DIR_s ALT_GIC_CPUIF_GICC_DIR_t;
29661 #define ALT_GIC_CPUIF_GICC_DIR_RESET 0x00000000
29663 #define ALT_GIC_CPUIF_GICC_DIR_OFST 0x1000
29665 #ifndef __ASSEMBLY__
29677 struct ALT_GIC_CPUIF_s
29679 volatile ALT_GIC_CPUIF_GICC_CTLR_t GICC_CTLR;
29680 volatile ALT_GIC_CPUIF_GICC_PMR_t GICC_PMR;
29681 volatile ALT_GIC_CPUIF_GICC_BPR_t GICC_BPR;
29682 volatile ALT_GIC_CPUIF_GICC_IAR_t GICC_IAR;
29683 volatile ALT_GIC_CPUIF_GICC_EOIR_t GICC_EOIR;
29684 volatile ALT_GIC_CPUIF_GICC_RPR_t GICC_RPR;
29685 volatile ALT_GIC_CPUIF_GICC_HPPIR_t GICC_HPPIR;
29686 volatile ALT_GIC_CPUIF_GICC_ABPR_t GICC_ABPR;
29687 volatile ALT_GIC_CPUIF_GICC_AIAR_t GICC_AIAR;
29688 volatile ALT_GIC_CPUIF_GICC_AEOIR_t GICC_AEOIR;
29689 volatile ALT_GIC_CPUIF_GICC_AHPPIR_t GICC_AHPPIR;
29690 volatile uint32_t _pad_0x2c_0xcf[41];
29691 volatile ALT_GIC_CPUIF_GICC_APR0_t GICC_APR0;
29692 volatile uint32_t _pad_0xd4_0xdf[3];
29693 volatile ALT_GIC_CPUIF_GICC_NSAPR0_t GICC_NSAPR0;
29694 volatile uint32_t _pad_0xe4_0xfb[6];
29695 volatile ALT_GIC_CPUIF_GICC_IIDR_t GICC_IIDR;
29696 volatile uint32_t _pad_0x100_0xfff[960];
29697 volatile ALT_GIC_CPUIF_GICC_DIR_t GICC_DIR;
29698 volatile uint32_t _pad_0x1004_0x2000[1023];
29702 typedef struct ALT_GIC_CPUIF_s ALT_GIC_CPUIF_t;
29704 struct ALT_GIC_CPUIF_raw_s
29706 volatile uint32_t GICC_CTLR;
29707 volatile uint32_t GICC_PMR;
29708 volatile uint32_t GICC_BPR;
29709 volatile uint32_t GICC_IAR;
29710 volatile uint32_t GICC_EOIR;
29711 volatile uint32_t GICC_RPR;
29712 volatile uint32_t GICC_HPPIR;
29713 volatile uint32_t GICC_ABPR;
29714 volatile uint32_t GICC_AIAR;
29715 volatile uint32_t GICC_AEOIR;
29716 volatile uint32_t GICC_AHPPIR;
29717 volatile uint32_t _pad_0x2c_0xcf[41];
29718 volatile uint32_t GICC_APR0;
29719 volatile uint32_t _pad_0xd4_0xdf[3];
29720 volatile uint32_t GICC_NSAPR0;
29721 volatile uint32_t _pad_0xe4_0xfb[6];
29722 volatile uint32_t GICC_IIDR;
29723 volatile uint32_t _pad_0x100_0xfff[960];
29724 volatile uint32_t GICC_DIR;
29725 volatile uint32_t _pad_0x1004_0x2000[1023];
29729 typedef struct ALT_GIC_CPUIF_raw_s ALT_GIC_CPUIF_raw_t;
29764 #define ALT_GIC_VCPUIF_GICH_HCR_FLD_LSB 0
29766 #define ALT_GIC_VCPUIF_GICH_HCR_FLD_MSB 31
29768 #define ALT_GIC_VCPUIF_GICH_HCR_FLD_WIDTH 32
29770 #define ALT_GIC_VCPUIF_GICH_HCR_FLD_SET_MSK 0xffffffff
29772 #define ALT_GIC_VCPUIF_GICH_HCR_FLD_CLR_MSK 0x00000000
29774 #define ALT_GIC_VCPUIF_GICH_HCR_FLD_RESET 0x0
29776 #define ALT_GIC_VCPUIF_GICH_HCR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29778 #define ALT_GIC_VCPUIF_GICH_HCR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29780 #ifndef __ASSEMBLY__
29792 struct ALT_GIC_VCPUIF_GICH_HCR_s
29794 volatile uint32_t fld : 32;
29798 typedef struct ALT_GIC_VCPUIF_GICH_HCR_s ALT_GIC_VCPUIF_GICH_HCR_t;
29802 #define ALT_GIC_VCPUIF_GICH_HCR_RESET 0x00000000
29804 #define ALT_GIC_VCPUIF_GICH_HCR_OFST 0x0
29806 #define ALT_GIC_VCPUIF_GICH_HCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GIC_VCPUIF_GICH_HCR_OFST))
29829 #define ALT_GIC_VCPUIF_GICH_VTR_FLD_LSB 0
29831 #define ALT_GIC_VCPUIF_GICH_VTR_FLD_MSB 31
29833 #define ALT_GIC_VCPUIF_GICH_VTR_FLD_WIDTH 32
29835 #define ALT_GIC_VCPUIF_GICH_VTR_FLD_SET_MSK 0xffffffff
29837 #define ALT_GIC_VCPUIF_GICH_VTR_FLD_CLR_MSK 0x00000000
29839 #define ALT_GIC_VCPUIF_GICH_VTR_FLD_RESET 0x90000003
29841 #define ALT_GIC_VCPUIF_GICH_VTR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29843 #define ALT_GIC_VCPUIF_GICH_VTR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29845 #ifndef __ASSEMBLY__
29857 struct ALT_GIC_VCPUIF_GICH_VTR_s
29859 volatile uint32_t fld : 32;
29863 typedef struct ALT_GIC_VCPUIF_GICH_VTR_s ALT_GIC_VCPUIF_GICH_VTR_t;
29867 #define ALT_GIC_VCPUIF_GICH_VTR_RESET 0x90000003
29869 #define ALT_GIC_VCPUIF_GICH_VTR_OFST 0x4
29871 #define ALT_GIC_VCPUIF_GICH_VTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GIC_VCPUIF_GICH_VTR_OFST))
29894 #define ALT_GIC_VCPUIF_GICH_VMCR_FLD_LSB 0
29896 #define ALT_GIC_VCPUIF_GICH_VMCR_FLD_MSB 31
29898 #define ALT_GIC_VCPUIF_GICH_VMCR_FLD_WIDTH 32
29900 #define ALT_GIC_VCPUIF_GICH_VMCR_FLD_SET_MSK 0xffffffff
29902 #define ALT_GIC_VCPUIF_GICH_VMCR_FLD_CLR_MSK 0x00000000
29904 #define ALT_GIC_VCPUIF_GICH_VMCR_FLD_RESET 0x0
29906 #define ALT_GIC_VCPUIF_GICH_VMCR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29908 #define ALT_GIC_VCPUIF_GICH_VMCR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29910 #ifndef __ASSEMBLY__
29922 struct ALT_GIC_VCPUIF_GICH_VMCR_s
29924 volatile uint32_t fld : 32;
29928 typedef struct ALT_GIC_VCPUIF_GICH_VMCR_s ALT_GIC_VCPUIF_GICH_VMCR_t;
29932 #define ALT_GIC_VCPUIF_GICH_VMCR_RESET 0x004c0000
29934 #define ALT_GIC_VCPUIF_GICH_VMCR_OFST 0x8
29936 #define ALT_GIC_VCPUIF_GICH_VMCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GIC_VCPUIF_GICH_VMCR_OFST))
29959 #define ALT_GIC_VCPUIF_GICH_MISR_FLD_LSB 0
29961 #define ALT_GIC_VCPUIF_GICH_MISR_FLD_MSB 31
29963 #define ALT_GIC_VCPUIF_GICH_MISR_FLD_WIDTH 32
29965 #define ALT_GIC_VCPUIF_GICH_MISR_FLD_SET_MSK 0xffffffff
29967 #define ALT_GIC_VCPUIF_GICH_MISR_FLD_CLR_MSK 0x00000000
29969 #define ALT_GIC_VCPUIF_GICH_MISR_FLD_RESET 0x0
29971 #define ALT_GIC_VCPUIF_GICH_MISR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29973 #define ALT_GIC_VCPUIF_GICH_MISR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29975 #ifndef __ASSEMBLY__
29987 struct ALT_GIC_VCPUIF_GICH_MISR_s
29989 volatile uint32_t fld : 32;
29993 typedef struct ALT_GIC_VCPUIF_GICH_MISR_s ALT_GIC_VCPUIF_GICH_MISR_t;
29997 #define ALT_GIC_VCPUIF_GICH_MISR_RESET 0x00000000
29999 #define ALT_GIC_VCPUIF_GICH_MISR_OFST 0x10
30001 #define ALT_GIC_VCPUIF_GICH_MISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GIC_VCPUIF_GICH_MISR_OFST))
30024 #define ALT_GIC_VCPUIF_GICH_EISR0_FLD_LSB 0
30026 #define ALT_GIC_VCPUIF_GICH_EISR0_FLD_MSB 31
30028 #define ALT_GIC_VCPUIF_GICH_EISR0_FLD_WIDTH 32
30030 #define ALT_GIC_VCPUIF_GICH_EISR0_FLD_SET_MSK 0xffffffff
30032 #define ALT_GIC_VCPUIF_GICH_EISR0_FLD_CLR_MSK 0x00000000
30034 #define ALT_GIC_VCPUIF_GICH_EISR0_FLD_RESET 0x0
30036 #define ALT_GIC_VCPUIF_GICH_EISR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30038 #define ALT_GIC_VCPUIF_GICH_EISR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
30040 #ifndef __ASSEMBLY__
30052 struct ALT_GIC_VCPUIF_GICH_EISR0_s
30054 volatile uint32_t fld : 32;
30058 typedef struct ALT_GIC_VCPUIF_GICH_EISR0_s ALT_GIC_VCPUIF_GICH_EISR0_t;
30062 #define ALT_GIC_VCPUIF_GICH_EISR0_RESET 0x00000000
30064 #define ALT_GIC_VCPUIF_GICH_EISR0_OFST 0x20
30066 #define ALT_GIC_VCPUIF_GICH_EISR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GIC_VCPUIF_GICH_EISR0_OFST))
30089 #define ALT_GIC_VCPUIF_GICH_ELSR0_FLD_LSB 0
30091 #define ALT_GIC_VCPUIF_GICH_ELSR0_FLD_MSB 31
30093 #define ALT_GIC_VCPUIF_GICH_ELSR0_FLD_WIDTH 32
30095 #define ALT_GIC_VCPUIF_GICH_ELSR0_FLD_SET_MSK 0xffffffff
30097 #define ALT_GIC_VCPUIF_GICH_ELSR0_FLD_CLR_MSK 0x00000000
30099 #define ALT_GIC_VCPUIF_GICH_ELSR0_FLD_RESET 0x0
30101 #define ALT_GIC_VCPUIF_GICH_ELSR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30103 #define ALT_GIC_VCPUIF_GICH_ELSR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
30105 #ifndef __ASSEMBLY__
30117 struct ALT_GIC_VCPUIF_GICH_ELSR0_s
30119 volatile uint32_t fld : 32;
30123 typedef struct ALT_GIC_VCPUIF_GICH_ELSR0_s ALT_GIC_VCPUIF_GICH_ELSR0_t;
30127 #define ALT_GIC_VCPUIF_GICH_ELSR0_RESET 0x0000000f
30129 #define ALT_GIC_VCPUIF_GICH_ELSR0_OFST 0x30
30131 #define ALT_GIC_VCPUIF_GICH_ELSR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GIC_VCPUIF_GICH_ELSR0_OFST))
30154 #define ALT_GIC_VCPUIF_GICH_APR0_FLD_LSB 0
30156 #define ALT_GIC_VCPUIF_GICH_APR0_FLD_MSB 31
30158 #define ALT_GIC_VCPUIF_GICH_APR0_FLD_WIDTH 32
30160 #define ALT_GIC_VCPUIF_GICH_APR0_FLD_SET_MSK 0xffffffff
30162 #define ALT_GIC_VCPUIF_GICH_APR0_FLD_CLR_MSK 0x00000000
30164 #define ALT_GIC_VCPUIF_GICH_APR0_FLD_RESET 0x0
30166 #define ALT_GIC_VCPUIF_GICH_APR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30168 #define ALT_GIC_VCPUIF_GICH_APR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
30170 #ifndef __ASSEMBLY__
30182 struct ALT_GIC_VCPUIF_GICH_APR0_s
30184 volatile uint32_t fld : 32;
30188 typedef struct ALT_GIC_VCPUIF_GICH_APR0_s ALT_GIC_VCPUIF_GICH_APR0_t;
30192 #define ALT_GIC_VCPUIF_GICH_APR0_RESET 0x00000000
30194 #define ALT_GIC_VCPUIF_GICH_APR0_OFST 0xf0
30196 #define ALT_GIC_VCPUIF_GICH_APR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GIC_VCPUIF_GICH_APR0_OFST))
30219 #define ALT_GIC_VCPUIF_GICH_LR0_FLD_LSB 0
30221 #define ALT_GIC_VCPUIF_GICH_LR0_FLD_MSB 31
30223 #define ALT_GIC_VCPUIF_GICH_LR0_FLD_WIDTH 32
30225 #define ALT_GIC_VCPUIF_GICH_LR0_FLD_SET_MSK 0xffffffff
30227 #define ALT_GIC_VCPUIF_GICH_LR0_FLD_CLR_MSK 0x00000000
30229 #define ALT_GIC_VCPUIF_GICH_LR0_FLD_RESET 0x0
30231 #define ALT_GIC_VCPUIF_GICH_LR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30233 #define ALT_GIC_VCPUIF_GICH_LR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
30235 #ifndef __ASSEMBLY__
30247 struct ALT_GIC_VCPUIF_GICH_LR0_s
30249 volatile uint32_t fld : 32;
30253 typedef struct ALT_GIC_VCPUIF_GICH_LR0_s ALT_GIC_VCPUIF_GICH_LR0_t;
30257 #define ALT_GIC_VCPUIF_GICH_LR0_RESET 0x00000000
30259 #define ALT_GIC_VCPUIF_GICH_LR0_OFST 0x100
30261 #define ALT_GIC_VCPUIF_GICH_LR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GIC_VCPUIF_GICH_LR0_OFST))
30284 #define ALT_GIC_VCPUIF_GICH_LR1_FLD_LSB 0
30286 #define ALT_GIC_VCPUIF_GICH_LR1_FLD_MSB 31
30288 #define ALT_GIC_VCPUIF_GICH_LR1_FLD_WIDTH 32
30290 #define ALT_GIC_VCPUIF_GICH_LR1_FLD_SET_MSK 0xffffffff
30292 #define ALT_GIC_VCPUIF_GICH_LR1_FLD_CLR_MSK 0x00000000
30294 #define ALT_GIC_VCPUIF_GICH_LR1_FLD_RESET 0x0
30296 #define ALT_GIC_VCPUIF_GICH_LR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30298 #define ALT_GIC_VCPUIF_GICH_LR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
30300 #ifndef __ASSEMBLY__
30312 struct ALT_GIC_VCPUIF_GICH_LR1_s
30314 volatile uint32_t fld : 32;
30318 typedef struct ALT_GIC_VCPUIF_GICH_LR1_s ALT_GIC_VCPUIF_GICH_LR1_t;
30322 #define ALT_GIC_VCPUIF_GICH_LR1_RESET 0x00000000
30324 #define ALT_GIC_VCPUIF_GICH_LR1_OFST 0x104
30326 #define ALT_GIC_VCPUIF_GICH_LR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GIC_VCPUIF_GICH_LR1_OFST))
30349 #define ALT_GIC_VCPUIF_GICH_LR2_FLD_LSB 0
30351 #define ALT_GIC_VCPUIF_GICH_LR2_FLD_MSB 31
30353 #define ALT_GIC_VCPUIF_GICH_LR2_FLD_WIDTH 32
30355 #define ALT_GIC_VCPUIF_GICH_LR2_FLD_SET_MSK 0xffffffff
30357 #define ALT_GIC_VCPUIF_GICH_LR2_FLD_CLR_MSK 0x00000000
30359 #define ALT_GIC_VCPUIF_GICH_LR2_FLD_RESET 0x0
30361 #define ALT_GIC_VCPUIF_GICH_LR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30363 #define ALT_GIC_VCPUIF_GICH_LR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
30365 #ifndef __ASSEMBLY__
30377 struct ALT_GIC_VCPUIF_GICH_LR2_s
30379 volatile uint32_t fld : 32;
30383 typedef struct ALT_GIC_VCPUIF_GICH_LR2_s ALT_GIC_VCPUIF_GICH_LR2_t;
30387 #define ALT_GIC_VCPUIF_GICH_LR2_RESET 0x00000000
30389 #define ALT_GIC_VCPUIF_GICH_LR2_OFST 0x108
30391 #define ALT_GIC_VCPUIF_GICH_LR2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GIC_VCPUIF_GICH_LR2_OFST))
30414 #define ALT_GIC_VCPUIF_GICH_LR3_FLD_LSB 0
30416 #define ALT_GIC_VCPUIF_GICH_LR3_FLD_MSB 31
30418 #define ALT_GIC_VCPUIF_GICH_LR3_FLD_WIDTH 32
30420 #define ALT_GIC_VCPUIF_GICH_LR3_FLD_SET_MSK 0xffffffff
30422 #define ALT_GIC_VCPUIF_GICH_LR3_FLD_CLR_MSK 0x00000000
30424 #define ALT_GIC_VCPUIF_GICH_LR3_FLD_RESET 0x0
30426 #define ALT_GIC_VCPUIF_GICH_LR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30428 #define ALT_GIC_VCPUIF_GICH_LR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
30430 #ifndef __ASSEMBLY__
30442 struct ALT_GIC_VCPUIF_GICH_LR3_s
30444 volatile uint32_t fld : 32;
30448 typedef struct ALT_GIC_VCPUIF_GICH_LR3_s ALT_GIC_VCPUIF_GICH_LR3_t;
30452 #define ALT_GIC_VCPUIF_GICH_LR3_RESET 0x00000000
30454 #define ALT_GIC_VCPUIF_GICH_LR3_OFST 0x10c
30456 #define ALT_GIC_VCPUIF_GICH_LR3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GIC_VCPUIF_GICH_LR3_OFST))
30458 #ifndef __ASSEMBLY__
30470 struct ALT_GIC_VCPUIF_s
30472 volatile ALT_GIC_VCPUIF_GICH_HCR_t GICH_HCR;
30473 volatile ALT_GIC_VCPUIF_GICH_VTR_t GICH_VTR;
30474 volatile ALT_GIC_VCPUIF_GICH_VMCR_t GICH_VMCR;
30475 volatile uint32_t _pad_0xc_0xf;
30476 volatile ALT_GIC_VCPUIF_GICH_MISR_t GICH_MISR;
30477 volatile uint32_t _pad_0x14_0x1f[3];
30478 volatile ALT_GIC_VCPUIF_GICH_EISR0_t GICH_EISR0;
30479 volatile uint32_t _pad_0x24_0x2f[3];
30480 volatile ALT_GIC_VCPUIF_GICH_ELSR0_t GICH_ELSR0;
30481 volatile uint32_t _pad_0x34_0xef[47];
30482 volatile ALT_GIC_VCPUIF_GICH_APR0_t GICH_APR0;
30483 volatile uint32_t _pad_0xf4_0xff[3];
30484 volatile ALT_GIC_VCPUIF_GICH_LR0_t GICH_LR0;
30485 volatile ALT_GIC_VCPUIF_GICH_LR1_t GICH_LR1;
30486 volatile ALT_GIC_VCPUIF_GICH_LR2_t GICH_LR2;
30487 volatile ALT_GIC_VCPUIF_GICH_LR3_t GICH_LR3;
30488 volatile uint32_t _pad_0x110_0x200[60];
30492 typedef struct ALT_GIC_VCPUIF_s ALT_GIC_VCPUIF_t;
30494 struct ALT_GIC_VCPUIF_raw_s
30496 volatile uint32_t GICH_HCR;
30497 volatile uint32_t GICH_VTR;
30498 volatile uint32_t GICH_VMCR;
30499 volatile uint32_t _pad_0xc_0xf;
30500 volatile uint32_t GICH_MISR;
30501 volatile uint32_t _pad_0x14_0x1f[3];
30502 volatile uint32_t GICH_EISR0;
30503 volatile uint32_t _pad_0x24_0x2f[3];
30504 volatile uint32_t GICH_ELSR0;
30505 volatile uint32_t _pad_0x34_0xef[47];
30506 volatile uint32_t GICH_APR0;
30507 volatile uint32_t _pad_0xf4_0xff[3];
30508 volatile uint32_t GICH_LR0;
30509 volatile uint32_t GICH_LR1;
30510 volatile uint32_t GICH_LR2;
30511 volatile uint32_t GICH_LR3;
30512 volatile uint32_t _pad_0x110_0x200[60];
30516 typedef struct ALT_GIC_VCPUIF_raw_s ALT_GIC_VCPUIF_raw_t;
30552 #define ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD_LSB 0
30554 #define ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD_MSB 31
30556 #define ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD_WIDTH 32
30558 #define ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD_SET_MSK 0xffffffff
30560 #define ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD_CLR_MSK 0x00000000
30562 #define ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD_RESET 0x0
30564 #define ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30566 #define ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD_SET(value) (((value) << 0) & 0xffffffff)
30568 #ifndef __ASSEMBLY__
30580 struct ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_s
30582 volatile uint32_t fld : 32;
30586 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_s ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_t;
30590 #define ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_RESET 0x00000000
30592 #define ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_OFST 0x0
30615 #define ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD_LSB 0
30617 #define ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD_MSB 31
30619 #define ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD_WIDTH 32
30621 #define ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD_SET_MSK 0xffffffff
30623 #define ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD_CLR_MSK 0x00000000
30625 #define ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD_RESET 0x0
30627 #define ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30629 #define ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD_SET(value) (((value) << 0) & 0xffffffff)
30631 #ifndef __ASSEMBLY__
30643 struct ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_s
30645 volatile uint32_t fld : 32;
30649 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_s ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_t;
30653 #define ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_RESET 0x00000000
30655 #define ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_OFST 0x4
30678 #define ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD_LSB 0
30680 #define ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD_MSB 31
30682 #define ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD_WIDTH 32
30684 #define ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD_SET_MSK 0xffffffff
30686 #define ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD_CLR_MSK 0x00000000
30688 #define ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD_RESET 0x0
30690 #define ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30692 #define ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD_SET(value) (((value) << 0) & 0xffffffff)
30694 #ifndef __ASSEMBLY__
30706 struct ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_s
30708 volatile uint32_t fld : 32;
30712 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_s ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_t;
30716 #define ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_RESET 0x00000002
30718 #define ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_OFST 0x8
30741 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD_LSB 0
30743 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD_MSB 31
30745 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD_WIDTH 32
30747 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD_SET_MSK 0xffffffff
30749 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD_CLR_MSK 0x00000000
30751 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD_RESET 0x0
30753 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30755 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD_SET(value) (((value) << 0) & 0xffffffff)
30757 #ifndef __ASSEMBLY__
30769 struct ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_s
30771 volatile uint32_t fld : 32;
30775 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_s ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_t;
30779 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_RESET 0x000003ff
30781 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_OFST 0xc
30804 #define ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD_LSB 0
30806 #define ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD_MSB 31
30808 #define ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD_WIDTH 32
30810 #define ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD_SET_MSK 0xffffffff
30812 #define ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD_CLR_MSK 0x00000000
30814 #define ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD_RESET 0x0
30816 #define ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30818 #define ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD_SET(value) (((value) << 0) & 0xffffffff)
30820 #ifndef __ASSEMBLY__
30832 struct ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_s
30834 volatile uint32_t fld : 32;
30838 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_s ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_t;
30842 #define ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_RESET 0x00000000
30844 #define ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_OFST 0x10
30867 #define ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD_LSB 0
30869 #define ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD_MSB 31
30871 #define ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD_WIDTH 32
30873 #define ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD_SET_MSK 0xffffffff
30875 #define ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD_CLR_MSK 0x00000000
30877 #define ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD_RESET 0x0
30879 #define ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30881 #define ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD_SET(value) (((value) << 0) & 0xffffffff)
30883 #ifndef __ASSEMBLY__
30895 struct ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_s
30897 volatile uint32_t fld : 32;
30901 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_s ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_t;
30905 #define ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_RESET 0x000000ff
30907 #define ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_OFST 0x14
30930 #define ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD_LSB 0
30932 #define ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD_MSB 31
30934 #define ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD_WIDTH 32
30936 #define ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD_SET_MSK 0xffffffff
30938 #define ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD_CLR_MSK 0x00000000
30940 #define ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD_RESET 0x0
30942 #define ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30944 #define ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD_SET(value) (((value) << 0) & 0xffffffff)
30946 #ifndef __ASSEMBLY__
30958 struct ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_s
30960 volatile uint32_t fld : 32;
30964 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_s ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_t;
30968 #define ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_RESET 0x000003ff
30970 #define ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_OFST 0x18
30993 #define ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD_LSB 0
30995 #define ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD_MSB 31
30997 #define ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD_WIDTH 32
30999 #define ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD_SET_MSK 0xffffffff
31001 #define ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD_CLR_MSK 0x00000000
31003 #define ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD_RESET 0x0
31005 #define ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
31007 #define ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD_SET(value) (((value) << 0) & 0xffffffff)
31009 #ifndef __ASSEMBLY__
31021 struct ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_s
31023 volatile uint32_t fld : 32;
31027 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_s ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_t;
31031 #define ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_RESET 0x00000003
31033 #define ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_OFST 0x1c
31056 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD_LSB 0
31058 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD_MSB 31
31060 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD_WIDTH 32
31062 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD_SET_MSK 0xffffffff
31064 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD_CLR_MSK 0x00000000
31066 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD_RESET 0x0
31068 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
31070 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD_SET(value) (((value) << 0) & 0xffffffff)
31072 #ifndef __ASSEMBLY__
31084 struct ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_s
31086 volatile uint32_t fld : 32;
31090 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_s ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_t;
31094 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_RESET 0x000003ff
31096 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_OFST 0x20
31119 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD_LSB 0
31121 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD_MSB 31
31123 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD_WIDTH 32
31125 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD_SET_MSK 0xffffffff
31127 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD_CLR_MSK 0x00000000
31129 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD_RESET 0x0
31131 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
31133 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD_SET(value) (((value) << 0) & 0xffffffff)
31135 #ifndef __ASSEMBLY__
31147 struct ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_s
31149 volatile uint32_t fld : 32;
31153 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_s ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_t;
31157 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_RESET 0x00000000
31159 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_OFST 0x24
31182 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD_LSB 0
31184 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD_MSB 31
31186 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD_WIDTH 32
31188 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD_SET_MSK 0xffffffff
31190 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD_CLR_MSK 0x00000000
31192 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD_RESET 0x0
31194 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
31196 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD_SET(value) (((value) << 0) & 0xffffffff)
31198 #ifndef __ASSEMBLY__
31210 struct ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_s
31212 volatile uint32_t fld : 32;
31216 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_s ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_t;
31220 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_RESET 0x000003ff
31222 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_OFST 0x28
31245 #define ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD_LSB 0
31247 #define ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD_MSB 31
31249 #define ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD_WIDTH 32
31251 #define ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD_SET_MSK 0xffffffff
31253 #define ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD_CLR_MSK 0x00000000
31255 #define ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD_RESET 0x0
31257 #define ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
31259 #define ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
31261 #ifndef __ASSEMBLY__
31273 struct ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_s
31275 volatile uint32_t fld : 32;
31279 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_s ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_t;
31283 #define ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_RESET 0x00000000
31285 #define ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_OFST 0xd0
31308 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD_LSB 0
31310 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD_MSB 31
31312 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD_WIDTH 32
31314 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD_SET_MSK 0xffffffff
31316 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD_CLR_MSK 0x00000000
31318 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD_RESET 0x202143b
31320 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
31322 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD_SET(value) (((value) << 0) & 0xffffffff)
31324 #ifndef __ASSEMBLY__
31336 struct ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_s
31338 volatile uint32_t fld : 32;
31342 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_s ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_t;
31346 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_RESET 0x0202143b
31348 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_OFST 0xfc
31371 #define ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD_LSB 0
31373 #define ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD_MSB 31
31375 #define ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD_WIDTH 32
31377 #define ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD_SET_MSK 0xffffffff
31379 #define ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD_CLR_MSK 0x00000000
31381 #define ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD_RESET 0x0
31383 #define ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
31385 #define ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD_SET(value) (((value) << 0) & 0xffffffff)
31387 #ifndef __ASSEMBLY__
31399 struct ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_s
31401 volatile uint32_t fld : 32;
31405 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_s ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_t;
31409 #define ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_RESET 0x00000000
31411 #define ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_OFST 0x1000
31413 #ifndef __ASSEMBLY__
31425 struct ALT_GIC_VCPUIF_HYP_VM_s
31427 volatile ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_t GICV_CTLR;
31428 volatile ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_t GICV_PMR;
31429 volatile ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_t GICV_BPR;
31430 volatile ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_t GICV_IAR;
31431 volatile ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_t GICV_EOIR;
31432 volatile ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_t GICV_RPR;
31433 volatile ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_t GICV_HPPIR;
31434 volatile ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_t GICV_ABPR;
31435 volatile ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_t GICV_AIAR;
31436 volatile ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_t GICV_AEOIR;
31437 volatile ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_t GICV_AHPPIR;
31438 volatile uint32_t _pad_0x2c_0xcf[41];
31439 volatile ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_t GICV_APR0;
31440 volatile uint32_t _pad_0xd4_0xfb[10];
31441 volatile ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_t GICV_IIDR;
31442 volatile uint32_t _pad_0x100_0xfff[960];
31443 volatile ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_t GICV_DIR;
31444 volatile uint32_t _pad_0x1004_0x2000[1023];
31448 typedef struct ALT_GIC_VCPUIF_HYP_VM_s ALT_GIC_VCPUIF_HYP_VM_t;
31450 struct ALT_GIC_VCPUIF_HYP_VM_raw_s
31452 volatile uint32_t GICV_CTLR;
31453 volatile uint32_t GICV_PMR;
31454 volatile uint32_t GICV_BPR;
31455 volatile uint32_t GICV_IAR;
31456 volatile uint32_t GICV_EOIR;
31457 volatile uint32_t GICV_RPR;
31458 volatile uint32_t GICV_HPPIR;
31459 volatile uint32_t GICV_ABPR;
31460 volatile uint32_t GICV_AIAR;
31461 volatile uint32_t GICV_AEOIR;
31462 volatile uint32_t GICV_AHPPIR;
31463 volatile uint32_t _pad_0x2c_0xcf[41];
31464 volatile uint32_t GICV_APR0;
31465 volatile uint32_t _pad_0xd4_0xfb[10];
31466 volatile uint32_t GICV_IIDR;
31467 volatile uint32_t _pad_0x100_0xfff[960];
31468 volatile uint32_t GICV_DIR;
31469 volatile uint32_t _pad_0x1004_0x2000[1023];
31473 typedef struct ALT_GIC_VCPUIF_HYP_VM_raw_s ALT_GIC_VCPUIF_HYP_VM_raw_t;