Hardware Libraries  20.1
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alt_qspi.h
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32 
33 /* Altera - ALT_QSPI */
34 
35 #ifndef __ALTERA_ALT_QSPI_H__
36 #define __ALTERA_ALT_QSPI_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
43 /*
44  * Component : QSPI Flash Controller Module Registers - ALT_QSPI
45  * QSPI Flash Controller Module Registers
46  *
47  * Registers in the QSPI Flash Controller module accessible via its APB slave
48  *
49  */
50 /*
51  * Register : QSPI Configuration Register - cfg
52  *
53  * Register Layout
54  *
55  * Bits | Access | Reset | Description
56  * :--------|:-------|:------|:-------------------------------------------
57  * [0] | RW | 0x0 | QSPI Enable
58  * [1] | RW | 0x0 | Clock Polarity
59  * [2] | RW | 0x0 | Select Clock Phase
60  * [6:3] | ??? | 0x0 | *UNDEFINED*
61  * [7] | RW | 0x0 | Enable Direct Access Controller
62  * [8] | RW | 0x0 | Legacy IP Mode Enable
63  * [9] | RW | 0x0 | Peripheral select decode
64  * [13:10] | RW | 0x0 | Peripheral Chip Select Lines
65  * [14] | RW | 0x0 | Write Protect Flash Pin
66  * [15] | RW | 0x0 | Enable DMA Peripheral Interface
67  * [16] | RW | 0x0 | Enable AHB Address Re-mapping
68  * [17] | RW | 0x0 | Enter XIP Mode on next READ
69  * [18] | RW | 0x0 | Enter XIP Mode Immediately
70  * [22:19] | RW | 0xf | Master Mode Baud Rate Divisor
71  * [30:23] | ??? | 0x0 | *UNDEFINED*
72  * [31] | R | 0x0 | Serial interface and QSPI pipeline is IDLE
73  *
74  */
75 /*
76  * Field : QSPI Enable - en
77  *
78  * If this bit is disabled, the QSPI will finish the current transfer of the data
79  * word (FF_W) and stop sending. When Enabled, and qspi_n_mo_en = 0, all output
80  * enables are inactive and all pins are set to input mode.
81  *
82  * Field Enumeration Values:
83  *
84  * Enum | Value | Description
85  * :----------------------|:------|:-----------------
86  * ALT_QSPI_CFG_EN_E_DIS | 0x0 | Disable the QSPI
87  * ALT_QSPI_CFG_EN_E_EN | 0x1 | Enable the QSPI
88  *
89  * Field Access Macros:
90  *
91  */
92 /*
93  * Enumerated value for register field ALT_QSPI_CFG_EN
94  *
95  * Disable the QSPI
96  */
97 #define ALT_QSPI_CFG_EN_E_DIS 0x0
98 /*
99  * Enumerated value for register field ALT_QSPI_CFG_EN
100  *
101  * Enable the QSPI
102  */
103 #define ALT_QSPI_CFG_EN_E_EN 0x1
104 
105 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_EN register field. */
106 #define ALT_QSPI_CFG_EN_LSB 0
107 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_EN register field. */
108 #define ALT_QSPI_CFG_EN_MSB 0
109 /* The width in bits of the ALT_QSPI_CFG_EN register field. */
110 #define ALT_QSPI_CFG_EN_WIDTH 1
111 /* The mask used to set the ALT_QSPI_CFG_EN register field value. */
112 #define ALT_QSPI_CFG_EN_SET_MSK 0x00000001
113 /* The mask used to clear the ALT_QSPI_CFG_EN register field value. */
114 #define ALT_QSPI_CFG_EN_CLR_MSK 0xfffffffe
115 /* The reset value of the ALT_QSPI_CFG_EN register field. */
116 #define ALT_QSPI_CFG_EN_RESET 0x0
117 /* Extracts the ALT_QSPI_CFG_EN field value from a register. */
118 #define ALT_QSPI_CFG_EN_GET(value) (((value) & 0x00000001) >> 0)
119 /* Produces a ALT_QSPI_CFG_EN register field value suitable for setting the register. */
120 #define ALT_QSPI_CFG_EN_SET(value) (((value) << 0) & 0x00000001)
121 
122 /*
123  * Field : Clock Polarity - selclkpol
124  *
125  * Controls spiclk modes of operation.
126  *
127  * Field Enumeration Values:
128  *
129  * Enum | Value | Description
130  * :------------------------------|:------|:----------------------------
131  * ALT_QSPI_CFG_SELCLKPOL_E_LOW | 0x1 | SPI clock is quiescent low
132  * ALT_QSPI_CFG_SELCLKPOL_E_HIGH | 0x0 | SPI clock is quiescent high
133  *
134  * Field Access Macros:
135  *
136  */
137 /*
138  * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL
139  *
140  * SPI clock is quiescent low
141  */
142 #define ALT_QSPI_CFG_SELCLKPOL_E_LOW 0x1
143 /*
144  * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL
145  *
146  * SPI clock is quiescent high
147  */
148 #define ALT_QSPI_CFG_SELCLKPOL_E_HIGH 0x0
149 
150 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */
151 #define ALT_QSPI_CFG_SELCLKPOL_LSB 1
152 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */
153 #define ALT_QSPI_CFG_SELCLKPOL_MSB 1
154 /* The width in bits of the ALT_QSPI_CFG_SELCLKPOL register field. */
155 #define ALT_QSPI_CFG_SELCLKPOL_WIDTH 1
156 /* The mask used to set the ALT_QSPI_CFG_SELCLKPOL register field value. */
157 #define ALT_QSPI_CFG_SELCLKPOL_SET_MSK 0x00000002
158 /* The mask used to clear the ALT_QSPI_CFG_SELCLKPOL register field value. */
159 #define ALT_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd
160 /* The reset value of the ALT_QSPI_CFG_SELCLKPOL register field. */
161 #define ALT_QSPI_CFG_SELCLKPOL_RESET 0x0
162 /* Extracts the ALT_QSPI_CFG_SELCLKPOL field value from a register. */
163 #define ALT_QSPI_CFG_SELCLKPOL_GET(value) (((value) & 0x00000002) >> 1)
164 /* Produces a ALT_QSPI_CFG_SELCLKPOL register field value suitable for setting the register. */
165 #define ALT_QSPI_CFG_SELCLKPOL_SET(value) (((value) << 1) & 0x00000002)
166 
167 /*
168  * Field : Select Clock Phase - selclkphase
169  *
170  * Selects whether the clock is in an active or inactive phase outside the SPI
171  * word.
172  *
173  * Field Enumeration Values:
174  *
175  * Enum | Value | Description
176  * :---------------------------------|:------|:---------------------------
177  * ALT_QSPI_CFG_SELCLKPHASE_E_ACT | 0x0 | SPI clock is quiescent low
178  * ALT_QSPI_CFG_SELCLKPHASE_E_INACT | 0x1 | Clock Inactive
179  *
180  * Field Access Macros:
181  *
182  */
183 /*
184  * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE
185  *
186  * SPI clock is quiescent low
187  */
188 #define ALT_QSPI_CFG_SELCLKPHASE_E_ACT 0x0
189 /*
190  * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE
191  *
192  * Clock Inactive
193  */
194 #define ALT_QSPI_CFG_SELCLKPHASE_E_INACT 0x1
195 
196 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */
197 #define ALT_QSPI_CFG_SELCLKPHASE_LSB 2
198 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */
199 #define ALT_QSPI_CFG_SELCLKPHASE_MSB 2
200 /* The width in bits of the ALT_QSPI_CFG_SELCLKPHASE register field. */
201 #define ALT_QSPI_CFG_SELCLKPHASE_WIDTH 1
202 /* The mask used to set the ALT_QSPI_CFG_SELCLKPHASE register field value. */
203 #define ALT_QSPI_CFG_SELCLKPHASE_SET_MSK 0x00000004
204 /* The mask used to clear the ALT_QSPI_CFG_SELCLKPHASE register field value. */
205 #define ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb
206 /* The reset value of the ALT_QSPI_CFG_SELCLKPHASE register field. */
207 #define ALT_QSPI_CFG_SELCLKPHASE_RESET 0x0
208 /* Extracts the ALT_QSPI_CFG_SELCLKPHASE field value from a register. */
209 #define ALT_QSPI_CFG_SELCLKPHASE_GET(value) (((value) & 0x00000004) >> 2)
210 /* Produces a ALT_QSPI_CFG_SELCLKPHASE register field value suitable for setting the register. */
211 #define ALT_QSPI_CFG_SELCLKPHASE_SET(value) (((value) << 2) & 0x00000004)
212 
213 /*
214  * Field : Enable Direct Access Controller - endiracc
215  *
216  * If disabled, the Direct Access Controller becomes inactive once the current
217  * transfer of the data word (FF_W) is complete. When the Direct Access Controller
218  * and Indirect Access Controller are both disabled, all AHB requests are completed
219  * with an error response.
220  *
221  * Field Enumeration Values:
222  *
223  * Enum | Value | Description
224  * :----------------------------|:------|:---------------------------
225  * ALT_QSPI_CFG_ENDIRACC_E_DIS | 0x0 | Disable Direct Access Ctrl
226  * ALT_QSPI_CFG_ENDIRACC_E_EN | 0x1 | Enable Direct Access Ctrl
227  *
228  * Field Access Macros:
229  *
230  */
231 /*
232  * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC
233  *
234  * Disable Direct Access Ctrl
235  */
236 #define ALT_QSPI_CFG_ENDIRACC_E_DIS 0x0
237 /*
238  * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC
239  *
240  * Enable Direct Access Ctrl
241  */
242 #define ALT_QSPI_CFG_ENDIRACC_E_EN 0x1
243 
244 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */
245 #define ALT_QSPI_CFG_ENDIRACC_LSB 7
246 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */
247 #define ALT_QSPI_CFG_ENDIRACC_MSB 7
248 /* The width in bits of the ALT_QSPI_CFG_ENDIRACC register field. */
249 #define ALT_QSPI_CFG_ENDIRACC_WIDTH 1
250 /* The mask used to set the ALT_QSPI_CFG_ENDIRACC register field value. */
251 #define ALT_QSPI_CFG_ENDIRACC_SET_MSK 0x00000080
252 /* The mask used to clear the ALT_QSPI_CFG_ENDIRACC register field value. */
253 #define ALT_QSPI_CFG_ENDIRACC_CLR_MSK 0xffffff7f
254 /* The reset value of the ALT_QSPI_CFG_ENDIRACC register field. */
255 #define ALT_QSPI_CFG_ENDIRACC_RESET 0x0
256 /* Extracts the ALT_QSPI_CFG_ENDIRACC field value from a register. */
257 #define ALT_QSPI_CFG_ENDIRACC_GET(value) (((value) & 0x00000080) >> 7)
258 /* Produces a ALT_QSPI_CFG_ENDIRACC register field value suitable for setting the register. */
259 #define ALT_QSPI_CFG_ENDIRACC_SET(value) (((value) << 7) & 0x00000080)
260 
261 /*
262  * Field : Legacy IP Mode Enable - enlegacyip
263  *
264  * This bit can select the Direct Access Controller/Indirect Access Controller or
265  * legacy mode.If legacy mode is selected, any write to the controller via the AHB
266  * interface is serialized and sent to the FLASH device. Any valid AHB read will
267  * pop the internal RX-FIFO, retrieving data that was forwarded by the external
268  * FLASH device on the SPI lines, byte transfers of 4, 2 or 1 are permitted and
269  * controlled via the HSIZE input.
270  *
271  * Field Enumeration Values:
272  *
273  * Enum | Value | Description
274  * :---------------------------------|:------|:--------------------------------------
275  * ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD | 0x1 | Legacy Mode
276  * ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD | 0x0 | Use Direct/Indirect Access Controller
277  *
278  * Field Access Macros:
279  *
280  */
281 /*
282  * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP
283  *
284  * Legacy Mode
285  */
286 #define ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD 0x1
287 /*
288  * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP
289  *
290  * Use Direct/Indirect Access Controller
291  */
292 #define ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD 0x0
293 
294 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */
295 #define ALT_QSPI_CFG_ENLEGACYIP_LSB 8
296 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */
297 #define ALT_QSPI_CFG_ENLEGACYIP_MSB 8
298 /* The width in bits of the ALT_QSPI_CFG_ENLEGACYIP register field. */
299 #define ALT_QSPI_CFG_ENLEGACYIP_WIDTH 1
300 /* The mask used to set the ALT_QSPI_CFG_ENLEGACYIP register field value. */
301 #define ALT_QSPI_CFG_ENLEGACYIP_SET_MSK 0x00000100
302 /* The mask used to clear the ALT_QSPI_CFG_ENLEGACYIP register field value. */
303 #define ALT_QSPI_CFG_ENLEGACYIP_CLR_MSK 0xfffffeff
304 /* The reset value of the ALT_QSPI_CFG_ENLEGACYIP register field. */
305 #define ALT_QSPI_CFG_ENLEGACYIP_RESET 0x0
306 /* Extracts the ALT_QSPI_CFG_ENLEGACYIP field value from a register. */
307 #define ALT_QSPI_CFG_ENLEGACYIP_GET(value) (((value) & 0x00000100) >> 8)
308 /* Produces a ALT_QSPI_CFG_ENLEGACYIP register field value suitable for setting the register. */
309 #define ALT_QSPI_CFG_ENLEGACYIP_SET(value) (((value) << 8) & 0x00000100)
310 
311 /*
312  * Field : Peripheral select decode - perseldec
313  *
314  * Select between '1 of 4 selects' or 'external 4-to-16 decode'. The
315  * qspi_n_ss_out[3:0] output signals are controlled.
316  *
317  * Field Enumeration Values:
318  *
319  * Enum | Value | Description
320  * :----------------------------------|:------|:----------------------------------
321  * ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 | 0x1 | Select external 4-to-16 decode
322  * ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 | 0x0 | Selects 1 of 4 qspi_n_ss_out[3:0]
323  *
324  * Field Access Macros:
325  *
326  */
327 /*
328  * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC
329  *
330  * Select external 4-to-16 decode
331  */
332 #define ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 0x1
333 /*
334  * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC
335  *
336  * Selects 1 of 4 qspi_n_ss_out[3:0]
337  */
338 #define ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 0x0
339 
340 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */
341 #define ALT_QSPI_CFG_PERSELDEC_LSB 9
342 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */
343 #define ALT_QSPI_CFG_PERSELDEC_MSB 9
344 /* The width in bits of the ALT_QSPI_CFG_PERSELDEC register field. */
345 #define ALT_QSPI_CFG_PERSELDEC_WIDTH 1
346 /* The mask used to set the ALT_QSPI_CFG_PERSELDEC register field value. */
347 #define ALT_QSPI_CFG_PERSELDEC_SET_MSK 0x00000200
348 /* The mask used to clear the ALT_QSPI_CFG_PERSELDEC register field value. */
349 #define ALT_QSPI_CFG_PERSELDEC_CLR_MSK 0xfffffdff
350 /* The reset value of the ALT_QSPI_CFG_PERSELDEC register field. */
351 #define ALT_QSPI_CFG_PERSELDEC_RESET 0x0
352 /* Extracts the ALT_QSPI_CFG_PERSELDEC field value from a register. */
353 #define ALT_QSPI_CFG_PERSELDEC_GET(value) (((value) & 0x00000200) >> 9)
354 /* Produces a ALT_QSPI_CFG_PERSELDEC register field value suitable for setting the register. */
355 #define ALT_QSPI_CFG_PERSELDEC_SET(value) (((value) << 9) & 0x00000200)
356 
357 /*
358  * Field : Peripheral Chip Select Lines - percslines
359  *
360  * Peripheral chip select line output decode type. As per perseldec, if perseldec =
361  * 0, the decode is select 1 of 4 decoding on signals, qspi_n_ss_out[3:0], The
362  * asserted decode line goes to 0. If perseldec = 1, the signals qspi_n_ss_out[3:0]
363  * require an external 4 to 16 decoder.
364  *
365  * Field Access Macros:
366  *
367  */
368 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */
369 #define ALT_QSPI_CFG_PERCSLINES_LSB 10
370 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */
371 #define ALT_QSPI_CFG_PERCSLINES_MSB 13
372 /* The width in bits of the ALT_QSPI_CFG_PERCSLINES register field. */
373 #define ALT_QSPI_CFG_PERCSLINES_WIDTH 4
374 /* The mask used to set the ALT_QSPI_CFG_PERCSLINES register field value. */
375 #define ALT_QSPI_CFG_PERCSLINES_SET_MSK 0x00003c00
376 /* The mask used to clear the ALT_QSPI_CFG_PERCSLINES register field value. */
377 #define ALT_QSPI_CFG_PERCSLINES_CLR_MSK 0xffffc3ff
378 /* The reset value of the ALT_QSPI_CFG_PERCSLINES register field. */
379 #define ALT_QSPI_CFG_PERCSLINES_RESET 0x0
380 /* Extracts the ALT_QSPI_CFG_PERCSLINES field value from a register. */
381 #define ALT_QSPI_CFG_PERCSLINES_GET(value) (((value) & 0x00003c00) >> 10)
382 /* Produces a ALT_QSPI_CFG_PERCSLINES register field value suitable for setting the register. */
383 #define ALT_QSPI_CFG_PERCSLINES_SET(value) (((value) << 10) & 0x00003c00)
384 
385 /*
386  * Field : Write Protect Flash Pin - wp
387  *
388  * This bit controls the write protect pin of the flash devices. The signal
389  * qspi_mo2_wpn needs to be resynchronized to the generated memory clock as
390  * necessary.
391  *
392  * Field Enumeration Values:
393  *
394  * Enum | Value | Description
395  * :-----------------------------|:------|:----------------------
396  * ALT_QSPI_CFG_WP_E_WRPROTON | 0x1 | Enable Write Protect
397  * ALT_QSPI_CFG_WP_E_WRTPROTOFF | 0x0 | Disable Write Protect
398  *
399  * Field Access Macros:
400  *
401  */
402 /*
403  * Enumerated value for register field ALT_QSPI_CFG_WP
404  *
405  * Enable Write Protect
406  */
407 #define ALT_QSPI_CFG_WP_E_WRPROTON 0x1
408 /*
409  * Enumerated value for register field ALT_QSPI_CFG_WP
410  *
411  * Disable Write Protect
412  */
413 #define ALT_QSPI_CFG_WP_E_WRTPROTOFF 0x0
414 
415 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_WP register field. */
416 #define ALT_QSPI_CFG_WP_LSB 14
417 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_WP register field. */
418 #define ALT_QSPI_CFG_WP_MSB 14
419 /* The width in bits of the ALT_QSPI_CFG_WP register field. */
420 #define ALT_QSPI_CFG_WP_WIDTH 1
421 /* The mask used to set the ALT_QSPI_CFG_WP register field value. */
422 #define ALT_QSPI_CFG_WP_SET_MSK 0x00004000
423 /* The mask used to clear the ALT_QSPI_CFG_WP register field value. */
424 #define ALT_QSPI_CFG_WP_CLR_MSK 0xffffbfff
425 /* The reset value of the ALT_QSPI_CFG_WP register field. */
426 #define ALT_QSPI_CFG_WP_RESET 0x0
427 /* Extracts the ALT_QSPI_CFG_WP field value from a register. */
428 #define ALT_QSPI_CFG_WP_GET(value) (((value) & 0x00004000) >> 14)
429 /* Produces a ALT_QSPI_CFG_WP register field value suitable for setting the register. */
430 #define ALT_QSPI_CFG_WP_SET(value) (((value) << 14) & 0x00004000)
431 
432 /*
433  * Field : Enable DMA Peripheral Interface - endma
434  *
435  * Allows DMA handshaking mode. When enabled the QSPI will trigger DMA transfer
436  * requests via the DMA peripheral interface.
437  *
438  * Field Enumeration Values:
439  *
440  * Enum | Value | Description
441  * :-------------------------|:------|:-----------------
442  * ALT_QSPI_CFG_ENDMA_E_EN | 0x1 | Enable DMA Mode
443  * ALT_QSPI_CFG_ENDMA_E_DIS | 0x0 | Disable DMA Mode
444  *
445  * Field Access Macros:
446  *
447  */
448 /*
449  * Enumerated value for register field ALT_QSPI_CFG_ENDMA
450  *
451  * Enable DMA Mode
452  */
453 #define ALT_QSPI_CFG_ENDMA_E_EN 0x1
454 /*
455  * Enumerated value for register field ALT_QSPI_CFG_ENDMA
456  *
457  * Disable DMA Mode
458  */
459 #define ALT_QSPI_CFG_ENDMA_E_DIS 0x0
460 
461 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDMA register field. */
462 #define ALT_QSPI_CFG_ENDMA_LSB 15
463 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDMA register field. */
464 #define ALT_QSPI_CFG_ENDMA_MSB 15
465 /* The width in bits of the ALT_QSPI_CFG_ENDMA register field. */
466 #define ALT_QSPI_CFG_ENDMA_WIDTH 1
467 /* The mask used to set the ALT_QSPI_CFG_ENDMA register field value. */
468 #define ALT_QSPI_CFG_ENDMA_SET_MSK 0x00008000
469 /* The mask used to clear the ALT_QSPI_CFG_ENDMA register field value. */
470 #define ALT_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff
471 /* The reset value of the ALT_QSPI_CFG_ENDMA register field. */
472 #define ALT_QSPI_CFG_ENDMA_RESET 0x0
473 /* Extracts the ALT_QSPI_CFG_ENDMA field value from a register. */
474 #define ALT_QSPI_CFG_ENDMA_GET(value) (((value) & 0x00008000) >> 15)
475 /* Produces a ALT_QSPI_CFG_ENDMA register field value suitable for setting the register. */
476 #define ALT_QSPI_CFG_ENDMA_SET(value) (((value) << 15) & 0x00008000)
477 
478 /*
479  * Field : Enable AHB Address Re-mapping - enahbremap
480  *
481  * (Direct Access Mode Only) When enabled, the incoming AHB address will be adapted
482  * and sent to the FLASH device as (address + N), where N is the value stored in
483  * the remap address register.
484  *
485  * Field Enumeration Values:
486  *
487  * Enum | Value | Description
488  * :------------------------------|:------|:-----------------------
489  * ALT_QSPI_CFG_ENAHBREMAP_E_EN | 0x1 | Enable AHB Re-mapping
490  * ALT_QSPI_CFG_ENAHBREMAP_E_DIS | 0x0 | Disable AHB Re-mapping
491  *
492  * Field Access Macros:
493  *
494  */
495 /*
496  * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP
497  *
498  * Enable AHB Re-mapping
499  */
500 #define ALT_QSPI_CFG_ENAHBREMAP_E_EN 0x1
501 /*
502  * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP
503  *
504  * Disable AHB Re-mapping
505  */
506 #define ALT_QSPI_CFG_ENAHBREMAP_E_DIS 0x0
507 
508 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */
509 #define ALT_QSPI_CFG_ENAHBREMAP_LSB 16
510 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */
511 #define ALT_QSPI_CFG_ENAHBREMAP_MSB 16
512 /* The width in bits of the ALT_QSPI_CFG_ENAHBREMAP register field. */
513 #define ALT_QSPI_CFG_ENAHBREMAP_WIDTH 1
514 /* The mask used to set the ALT_QSPI_CFG_ENAHBREMAP register field value. */
515 #define ALT_QSPI_CFG_ENAHBREMAP_SET_MSK 0x00010000
516 /* The mask used to clear the ALT_QSPI_CFG_ENAHBREMAP register field value. */
517 #define ALT_QSPI_CFG_ENAHBREMAP_CLR_MSK 0xfffeffff
518 /* The reset value of the ALT_QSPI_CFG_ENAHBREMAP register field. */
519 #define ALT_QSPI_CFG_ENAHBREMAP_RESET 0x0
520 /* Extracts the ALT_QSPI_CFG_ENAHBREMAP field value from a register. */
521 #define ALT_QSPI_CFG_ENAHBREMAP_GET(value) (((value) & 0x00010000) >> 16)
522 /* Produces a ALT_QSPI_CFG_ENAHBREMAP register field value suitable for setting the register. */
523 #define ALT_QSPI_CFG_ENAHBREMAP_SET(value) (((value) << 16) & 0x00010000)
524 
525 /*
526  * Field : Enter XIP Mode on next READ - enterxipnextrd
527  *
528  * If XIP is enabled, then setting to disabled will cause the controller to exit
529  * XIP mode on the next READ instruction. If XIP is disabled, then setting to
530  * enabled will inform the controller that the device is ready to enter XIP on the
531  * next READ instruction. The controller will therefore send the appropriate
532  * command sequence, including mode bits to cause the device to enter XIP mode. Use
533  * this register after the controller has ensured the FLASH device has been
534  * configured to be ready to enter XIP mode. Note : To exit XIP mode, this bit
535  * should be set to 0. This will take effect in the attached device only AFTER the
536  * next READ instruction is executed. Software should therefore ensure that at
537  * least one READ instruction is requested after resetting this bit before it can
538  * be sure XIP mode in the device is exited.
539  *
540  * Field Enumeration Values:
541  *
542  * Enum | Value | Description
543  * :----------------------------------|:------|:----------------------------------------
544  * ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN | 0x1 | Enter XIP Mode on next READ instruction
545  * ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS | 0x0 | Exit XIP Mode on next READ instruction
546  *
547  * Field Access Macros:
548  *
549  */
550 /*
551  * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD
552  *
553  * Enter XIP Mode on next READ instruction
554  */
555 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN 0x1
556 /*
557  * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD
558  *
559  * Exit XIP Mode on next READ instruction
560  */
561 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS 0x0
562 
563 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */
564 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_LSB 17
565 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */
566 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_MSB 17
567 /* The width in bits of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */
568 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_WIDTH 1
569 /* The mask used to set the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */
570 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET_MSK 0x00020000
571 /* The mask used to clear the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */
572 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_CLR_MSK 0xfffdffff
573 /* The reset value of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */
574 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_RESET 0x0
575 /* Extracts the ALT_QSPI_CFG_ENTERXIPNEXTRD field value from a register. */
576 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_GET(value) (((value) & 0x00020000) >> 17)
577 /* Produces a ALT_QSPI_CFG_ENTERXIPNEXTRD register field value suitable for setting the register. */
578 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET(value) (((value) << 17) & 0x00020000)
579 
580 /*
581  * Field : Enter XIP Mode Immediately - enterxipimm
582  *
583  * If XIP is enabled, then setting to disabled will cause the controller to exit
584  * XIP mode on the next READ instruction. If XIP is disabled, then setting enable
585  * will operate the device in XIP mode immediately. Use this register when the
586  * external device wakes up in XIP mode (as per the contents of its non- volatile
587  * configuration register). The controller will assume the next READ instruction
588  * will be passed to the device as an XIP instruction, and therefore will not
589  * require the READ opcode to be transferred. Note: To exit XIP mode, this bit
590  * should be set to 0. This will take effect in the attached device only after the
591  * next READ instruction is executed. Software therefore should ensure that at
592  * least one READ instruction is requested after resetting this bit in order to be
593  * sure that XIP mode is exited.
594  *
595  * Field Enumeration Values:
596  *
597  * Enum | Value | Description
598  * :-------------------------------|:------|:---------------------------------------
599  * ALT_QSPI_CFG_ENTERXIPIMM_E_EN | 0x1 | Enter XIP Mode immediately
600  * ALT_QSPI_CFG_ENTERXIPIMM_E_DIS | 0x0 | Exit XIP Mode on next READ instruction
601  *
602  * Field Access Macros:
603  *
604  */
605 /*
606  * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM
607  *
608  * Enter XIP Mode immediately
609  */
610 #define ALT_QSPI_CFG_ENTERXIPIMM_E_EN 0x1
611 /*
612  * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM
613  *
614  * Exit XIP Mode on next READ instruction
615  */
616 #define ALT_QSPI_CFG_ENTERXIPIMM_E_DIS 0x0
617 
618 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */
619 #define ALT_QSPI_CFG_ENTERXIPIMM_LSB 18
620 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */
621 #define ALT_QSPI_CFG_ENTERXIPIMM_MSB 18
622 /* The width in bits of the ALT_QSPI_CFG_ENTERXIPIMM register field. */
623 #define ALT_QSPI_CFG_ENTERXIPIMM_WIDTH 1
624 /* The mask used to set the ALT_QSPI_CFG_ENTERXIPIMM register field value. */
625 #define ALT_QSPI_CFG_ENTERXIPIMM_SET_MSK 0x00040000
626 /* The mask used to clear the ALT_QSPI_CFG_ENTERXIPIMM register field value. */
627 #define ALT_QSPI_CFG_ENTERXIPIMM_CLR_MSK 0xfffbffff
628 /* The reset value of the ALT_QSPI_CFG_ENTERXIPIMM register field. */
629 #define ALT_QSPI_CFG_ENTERXIPIMM_RESET 0x0
630 /* Extracts the ALT_QSPI_CFG_ENTERXIPIMM field value from a register. */
631 #define ALT_QSPI_CFG_ENTERXIPIMM_GET(value) (((value) & 0x00040000) >> 18)
632 /* Produces a ALT_QSPI_CFG_ENTERXIPIMM register field value suitable for setting the register. */
633 #define ALT_QSPI_CFG_ENTERXIPIMM_SET(value) (((value) << 18) & 0x00040000)
634 
635 /*
636  * Field : Master Mode Baud Rate Divisor - bauddiv
637  *
638  * SPI baud rate = ref_clk / (2 * baud_rate_divisor)
639  *
640  * Field Enumeration Values:
641  *
642  * Enum | Value | Description
643  * :------------------------------|:------|:-----------------
644  * ALT_QSPI_CFG_BAUDDIV_E_BAUD2 | 0x0 | Baud Rate Div/2
645  * ALT_QSPI_CFG_BAUDDIV_E_BAUD4 | 0x1 | Baud Rate Div/4
646  * ALT_QSPI_CFG_BAUDDIV_E_BAUD6 | 0x2 | Baud Rate Div/6
647  * ALT_QSPI_CFG_BAUDDIV_E_BAUD8 | 0x3 | Baud Rate Div/8
648  * ALT_QSPI_CFG_BAUDDIV_E_BAUD10 | 0x4 | Baud Rate Div/10
649  * ALT_QSPI_CFG_BAUDDIV_E_BAUD12 | 0x5 | Baud Rate Div/12
650  * ALT_QSPI_CFG_BAUDDIV_E_BAUD14 | 0x6 | Baud Rate Div/14
651  * ALT_QSPI_CFG_BAUDDIV_E_BAUD16 | 0x7 | Baud Rate Div/16
652  * ALT_QSPI_CFG_BAUDDIV_E_BAUD18 | 0x8 | Baud Rate Div/18
653  * ALT_QSPI_CFG_BAUDDIV_E_BAUD20 | 0x9 | Baud Rate Div/20
654  * ALT_QSPI_CFG_BAUDDIV_E_BAUD22 | 0xa | Baud Rate Div/22
655  * ALT_QSPI_CFG_BAUDDIV_E_BAUD24 | 0xb | Baud Rate Div/24
656  * ALT_QSPI_CFG_BAUDDIV_E_BAUD26 | 0xc | Baud Rate Div/26
657  * ALT_QSPI_CFG_BAUDDIV_E_BAUD28 | 0xd | Baud Rate Div/28
658  * ALT_QSPI_CFG_BAUDDIV_E_BAUD30 | 0xe | Baud Rate Div/30
659  * ALT_QSPI_CFG_BAUDDIV_E_BAUD32 | 0xf | Baud Rate Div/32
660  *
661  * Field Access Macros:
662  *
663  */
664 /*
665  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
666  *
667  * Baud Rate Div/2
668  */
669 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD2 0x0
670 /*
671  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
672  *
673  * Baud Rate Div/4
674  */
675 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD4 0x1
676 /*
677  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
678  *
679  * Baud Rate Div/6
680  */
681 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD6 0x2
682 /*
683  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
684  *
685  * Baud Rate Div/8
686  */
687 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD8 0x3
688 /*
689  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
690  *
691  * Baud Rate Div/10
692  */
693 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD10 0x4
694 /*
695  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
696  *
697  * Baud Rate Div/12
698  */
699 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD12 0x5
700 /*
701  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
702  *
703  * Baud Rate Div/14
704  */
705 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD14 0x6
706 /*
707  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
708  *
709  * Baud Rate Div/16
710  */
711 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD16 0x7
712 /*
713  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
714  *
715  * Baud Rate Div/18
716  */
717 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD18 0x8
718 /*
719  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
720  *
721  * Baud Rate Div/20
722  */
723 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD20 0x9
724 /*
725  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
726  *
727  * Baud Rate Div/22
728  */
729 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD22 0xa
730 /*
731  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
732  *
733  * Baud Rate Div/24
734  */
735 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD24 0xb
736 /*
737  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
738  *
739  * Baud Rate Div/26
740  */
741 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD26 0xc
742 /*
743  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
744  *
745  * Baud Rate Div/28
746  */
747 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD28 0xd
748 /*
749  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
750  *
751  * Baud Rate Div/30
752  */
753 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD30 0xe
754 /*
755  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
756  *
757  * Baud Rate Div/32
758  */
759 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD32 0xf
760 
761 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */
762 #define ALT_QSPI_CFG_BAUDDIV_LSB 19
763 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */
764 #define ALT_QSPI_CFG_BAUDDIV_MSB 22
765 /* The width in bits of the ALT_QSPI_CFG_BAUDDIV register field. */
766 #define ALT_QSPI_CFG_BAUDDIV_WIDTH 4
767 /* The mask used to set the ALT_QSPI_CFG_BAUDDIV register field value. */
768 #define ALT_QSPI_CFG_BAUDDIV_SET_MSK 0x00780000
769 /* The mask used to clear the ALT_QSPI_CFG_BAUDDIV register field value. */
770 #define ALT_QSPI_CFG_BAUDDIV_CLR_MSK 0xff87ffff
771 /* The reset value of the ALT_QSPI_CFG_BAUDDIV register field. */
772 #define ALT_QSPI_CFG_BAUDDIV_RESET 0xf
773 /* Extracts the ALT_QSPI_CFG_BAUDDIV field value from a register. */
774 #define ALT_QSPI_CFG_BAUDDIV_GET(value) (((value) & 0x00780000) >> 19)
775 /* Produces a ALT_QSPI_CFG_BAUDDIV register field value suitable for setting the register. */
776 #define ALT_QSPI_CFG_BAUDDIV_SET(value) (((value) << 19) & 0x00780000)
777 
778 /*
779  * Field : Serial interface and QSPI pipeline is IDLE - idle
780  *
781  * This is a STATUS read-only bit. Note this is a retimed signal, so there will be
782  * some inherent delay on the generation of this status signal.
783  *
784  * Field Enumeration Values:
785  *
786  * Enum | Value | Description
787  * :---------------------------|:------|:--------------
788  * ALT_QSPI_CFG_IDLE_E_SET | 0x1 | Idle Mode
789  * ALT_QSPI_CFG_IDLE_E_NOTSET | 0x0 | Non-Idle Mode
790  *
791  * Field Access Macros:
792  *
793  */
794 /*
795  * Enumerated value for register field ALT_QSPI_CFG_IDLE
796  *
797  * Idle Mode
798  */
799 #define ALT_QSPI_CFG_IDLE_E_SET 0x1
800 /*
801  * Enumerated value for register field ALT_QSPI_CFG_IDLE
802  *
803  * Non-Idle Mode
804  */
805 #define ALT_QSPI_CFG_IDLE_E_NOTSET 0x0
806 
807 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_IDLE register field. */
808 #define ALT_QSPI_CFG_IDLE_LSB 31
809 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_IDLE register field. */
810 #define ALT_QSPI_CFG_IDLE_MSB 31
811 /* The width in bits of the ALT_QSPI_CFG_IDLE register field. */
812 #define ALT_QSPI_CFG_IDLE_WIDTH 1
813 /* The mask used to set the ALT_QSPI_CFG_IDLE register field value. */
814 #define ALT_QSPI_CFG_IDLE_SET_MSK 0x80000000
815 /* The mask used to clear the ALT_QSPI_CFG_IDLE register field value. */
816 #define ALT_QSPI_CFG_IDLE_CLR_MSK 0x7fffffff
817 /* The reset value of the ALT_QSPI_CFG_IDLE register field. */
818 #define ALT_QSPI_CFG_IDLE_RESET 0x0
819 /* Extracts the ALT_QSPI_CFG_IDLE field value from a register. */
820 #define ALT_QSPI_CFG_IDLE_GET(value) (((value) & 0x80000000) >> 31)
821 /* Produces a ALT_QSPI_CFG_IDLE register field value suitable for setting the register. */
822 #define ALT_QSPI_CFG_IDLE_SET(value) (((value) << 31) & 0x80000000)
823 
824 #ifndef __ASSEMBLY__
825 /*
826  * WARNING: The C register and register group struct declarations are provided for
827  * convenience and illustrative purposes. They should, however, be used with
828  * caution as the C language standard provides no guarantees about the alignment or
829  * atomicity of device memory accesses. The recommended practice for writing
830  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
831  * alt_write_word() functions.
832  *
833  * The struct declaration for register ALT_QSPI_CFG.
834  */
835 struct ALT_QSPI_CFG_s
836 {
837  uint32_t en : 1; /* QSPI Enable */
838  uint32_t selclkpol : 1; /* Clock Polarity */
839  uint32_t selclkphase : 1; /* Select Clock Phase */
840  uint32_t : 4; /* *UNDEFINED* */
841  uint32_t endiracc : 1; /* Enable Direct Access Controller */
842  uint32_t enlegacyip : 1; /* Legacy IP Mode Enable */
843  uint32_t perseldec : 1; /* Peripheral select decode */
844  uint32_t percslines : 4; /* Peripheral Chip Select Lines */
845  uint32_t wp : 1; /* Write Protect Flash Pin */
846  uint32_t endma : 1; /* Enable DMA Peripheral Interface */
847  uint32_t enahbremap : 1; /* Enable AHB Address Re-mapping */
848  uint32_t enterxipnextrd : 1; /* Enter XIP Mode on next READ */
849  uint32_t enterxipimm : 1; /* Enter XIP Mode Immediately */
850  uint32_t bauddiv : 4; /* Master Mode Baud Rate Divisor */
851  uint32_t : 8; /* *UNDEFINED* */
852  const uint32_t idle : 1; /* Serial interface and QSPI pipeline is IDLE */
853 };
854 
855 /* The typedef declaration for register ALT_QSPI_CFG. */
856 typedef volatile struct ALT_QSPI_CFG_s ALT_QSPI_CFG_t;
857 #endif /* __ASSEMBLY__ */
858 
859 /* The byte offset of the ALT_QSPI_CFG register from the beginning of the component. */
860 #define ALT_QSPI_CFG_OFST 0x0
861 
862 /*
863  * Register : Device Read Instruction Register - devrd
864  *
865  * Register Layout
866  *
867  * Bits | Access | Reset | Description
868  * :--------|:-------|:------|:----------------------------
869  * [7:0] | RW | 0x3 | Read Opcode in non-XIP mode
870  * [9:8] | RW | 0x0 | Instruction Transfer Width
871  * [11:10] | ??? | 0x0 | *UNDEFINED*
872  * [13:12] | RW | 0x0 | Address Transfer Width
873  * [15:14] | ??? | 0x0 | *UNDEFINED*
874  * [17:16] | RW | 0x0 | Data Transfer Width
875  * [19:18] | ??? | 0x0 | *UNDEFINED*
876  * [20] | RW | 0x0 | Mode Bit Enable
877  * [23:21] | ??? | 0x0 | *UNDEFINED*
878  * [28:24] | RW | 0x0 | Dummy Read Clock Cycles
879  * [31:29] | ??? | 0x0 | *UNDEFINED*
880  *
881  */
882 /*
883  * Field : Read Opcode in non-XIP mode - rdopcode
884  *
885  * Read Opcode to use when not in XIP mode
886  *
887  * Field Enumeration Values:
888  *
889  * Enum | Value | Description
890  * :---------------------------------|:------|:----------------------------
891  * ALT_QSPI_DEVRD_RDOPCODE_E_RD | 0x3 | Read Opcode in Non-XIP mode
892  * ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD | 0xb | Fast Read in Non-XIP mode
893  *
894  * Field Access Macros:
895  *
896  */
897 /*
898  * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE
899  *
900  * Read Opcode in Non-XIP mode
901  */
902 #define ALT_QSPI_DEVRD_RDOPCODE_E_RD 0x3
903 /*
904  * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE
905  *
906  * Fast Read in Non-XIP mode
907  */
908 #define ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD 0xb
909 
910 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */
911 #define ALT_QSPI_DEVRD_RDOPCODE_LSB 0
912 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */
913 #define ALT_QSPI_DEVRD_RDOPCODE_MSB 7
914 /* The width in bits of the ALT_QSPI_DEVRD_RDOPCODE register field. */
915 #define ALT_QSPI_DEVRD_RDOPCODE_WIDTH 8
916 /* The mask used to set the ALT_QSPI_DEVRD_RDOPCODE register field value. */
917 #define ALT_QSPI_DEVRD_RDOPCODE_SET_MSK 0x000000ff
918 /* The mask used to clear the ALT_QSPI_DEVRD_RDOPCODE register field value. */
919 #define ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK 0xffffff00
920 /* The reset value of the ALT_QSPI_DEVRD_RDOPCODE register field. */
921 #define ALT_QSPI_DEVRD_RDOPCODE_RESET 0x3
922 /* Extracts the ALT_QSPI_DEVRD_RDOPCODE field value from a register. */
923 #define ALT_QSPI_DEVRD_RDOPCODE_GET(value) (((value) & 0x000000ff) >> 0)
924 /* Produces a ALT_QSPI_DEVRD_RDOPCODE register field value suitable for setting the register. */
925 #define ALT_QSPI_DEVRD_RDOPCODE_SET(value) (((value) << 0) & 0x000000ff)
926 
927 /*
928  * Field : Instruction Transfer Width - instwidth
929  *
930  * Sets instruction transfer width (1, 2, or 4 bits). Applies to all instructions
931  * sent to SPI flash device (not just read instructions).
932  *
933  * Field Enumeration Values:
934  *
935  * Enum | Value | Description
936  * :----------------------------------|:------|:-------------------------------------------------
937  * ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE | 0x0 | Instruction transferred on DQ0. Supported by all
938  * : | | SPI flash devices.
939  * ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL | 0x1 | Instruction transferred on DQ0 and DQ1.
940  * : | | Supported by all SPI flash devices that support
941  * : | | the Dual SP (DIO-SPI) Protocol.
942  * ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD | 0x2 | Instruction transferred on DQ0, DQ1, DQ2, and
943  * : | | DQ3. Supported by all SPI flash devices that
944  * : | | support the Quad SP (QIO-SPI) Protocol.
945  *
946  * Field Access Macros:
947  *
948  */
949 /*
950  * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH
951  *
952  * Instruction transferred on DQ0. Supported by all SPI flash devices.
953  */
954 #define ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE 0x0
955 /*
956  * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH
957  *
958  * Instruction transferred on DQ0 and DQ1. Supported by all SPI flash devices that
959  * support the Dual SP (DIO-SPI) Protocol.
960  */
961 #define ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL 0x1
962 /*
963  * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH
964  *
965  * Instruction transferred on DQ0, DQ1, DQ2, and DQ3. Supported by all SPI flash
966  * devices that support the Quad SP (QIO-SPI) Protocol.
967  */
968 #define ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD 0x2
969 
970 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */
971 #define ALT_QSPI_DEVRD_INSTWIDTH_LSB 8
972 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */
973 #define ALT_QSPI_DEVRD_INSTWIDTH_MSB 9
974 /* The width in bits of the ALT_QSPI_DEVRD_INSTWIDTH register field. */
975 #define ALT_QSPI_DEVRD_INSTWIDTH_WIDTH 2
976 /* The mask used to set the ALT_QSPI_DEVRD_INSTWIDTH register field value. */
977 #define ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK 0x00000300
978 /* The mask used to clear the ALT_QSPI_DEVRD_INSTWIDTH register field value. */
979 #define ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK 0xfffffcff
980 /* The reset value of the ALT_QSPI_DEVRD_INSTWIDTH register field. */
981 #define ALT_QSPI_DEVRD_INSTWIDTH_RESET 0x0
982 /* Extracts the ALT_QSPI_DEVRD_INSTWIDTH field value from a register. */
983 #define ALT_QSPI_DEVRD_INSTWIDTH_GET(value) (((value) & 0x00000300) >> 8)
984 /* Produces a ALT_QSPI_DEVRD_INSTWIDTH register field value suitable for setting the register. */
985 #define ALT_QSPI_DEVRD_INSTWIDTH_SET(value) (((value) << 8) & 0x00000300)
986 
987 /*
988  * Field : Address Transfer Width - addrwidth
989  *
990  * Sets read address transfer width (1, 2, or 4 bits).
991  *
992  * Field Enumeration Values:
993  *
994  * Enum | Value | Description
995  * :----------------------------------|:------|:-------------------------------------------------
996  * ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE | 0x0 | Read address transferred on DQ0. Supported by
997  * : | | all SPI flash devices
998  * ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL | 0x1 | Read address transferred on DQ0 and DQ1.
999  * : | | Supported by some SPI flash devices that support
1000  * : | | the Extended SPI Protocol and by all SPI flash
1001  * : | | devices that support the Dual SP (DIO-SPI)
1002  * : | | Protocol.
1003  * ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD | 0x2 | Read address transferred on DQ0, DQ1, DQ2, and
1004  * : | | DQ3. Supported by some SPI flash devices that
1005  * : | | support the Extended SPI Protocol and by all SPI
1006  * : | | flash devices that support the Quad SP (QIO-SPI)
1007  * : | | Protocol.
1008  *
1009  * Field Access Macros:
1010  *
1011  */
1012 /*
1013  * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH
1014  *
1015  * Read address transferred on DQ0. Supported by all SPI flash devices
1016  */
1017 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE 0x0
1018 /*
1019  * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH
1020  *
1021  * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices
1022  * that support the Extended SPI Protocol and by all SPI flash devices that support
1023  * the Dual SP (DIO-SPI) Protocol.
1024  */
1025 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL 0x1
1026 /*
1027  * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH
1028  *
1029  * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash
1030  * devices that support the Extended SPI Protocol and by all SPI flash devices that
1031  * support the Quad SP (QIO-SPI) Protocol.
1032  */
1033 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD 0x2
1034 
1035 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */
1036 #define ALT_QSPI_DEVRD_ADDRWIDTH_LSB 12
1037 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */
1038 #define ALT_QSPI_DEVRD_ADDRWIDTH_MSB 13
1039 /* The width in bits of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */
1040 #define ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH 2
1041 /* The mask used to set the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */
1042 #define ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK 0x00003000
1043 /* The mask used to clear the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */
1044 #define ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK 0xffffcfff
1045 /* The reset value of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */
1046 #define ALT_QSPI_DEVRD_ADDRWIDTH_RESET 0x0
1047 /* Extracts the ALT_QSPI_DEVRD_ADDRWIDTH field value from a register. */
1048 #define ALT_QSPI_DEVRD_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)
1049 /* Produces a ALT_QSPI_DEVRD_ADDRWIDTH register field value suitable for setting the register. */
1050 #define ALT_QSPI_DEVRD_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)
1051 
1052 /*
1053  * Field : Data Transfer Width - datawidth
1054  *
1055  * Sets read data transfer width (1, 2, or 4 bits).
1056  *
1057  * Field Enumeration Values:
1058  *
1059  * Enum | Value | Description
1060  * :----------------------------------|:------|:-------------------------------------------------
1061  * ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE | 0x0 | Read data transferred on DQ0. Supported by all
1062  * : | | SPI flash devices
1063  * ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL | 0x1 | Read data transferred on DQ0 and DQ1. Supported
1064  * : | | by some SPI flash devices that support the
1065  * : | | Extended SPI Protocol and by all SPI flash
1066  * : | | devices that support the Dual SP (DIO-SPI)
1067  * : | | Protocol.
1068  * ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD | 0x2 | Read data transferred on DQ0, DQ1, DQ2, and DQ3.
1069  * : | | Supported by some SPI flash devices that support
1070  * : | | the Extended SPI Protocol and by all SPI flash
1071  * : | | devices that support the Quad SP (QIO-SPI)
1072  * : | | Protocol.
1073  *
1074  * Field Access Macros:
1075  *
1076  */
1077 /*
1078  * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH
1079  *
1080  * Read data transferred on DQ0. Supported by all SPI flash devices
1081  */
1082 #define ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE 0x0
1083 /*
1084  * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH
1085  *
1086  * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that
1087  * support the Extended SPI Protocol and by all SPI flash devices that support the
1088  * Dual SP (DIO-SPI) Protocol.
1089  */
1090 #define ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL 0x1
1091 /*
1092  * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH
1093  *
1094  * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash
1095  * devices that support the Extended SPI Protocol and by all SPI flash devices that
1096  * support the Quad SP (QIO-SPI) Protocol.
1097  */
1098 #define ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD 0x2
1099 
1100 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */
1101 #define ALT_QSPI_DEVRD_DATAWIDTH_LSB 16
1102 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */
1103 #define ALT_QSPI_DEVRD_DATAWIDTH_MSB 17
1104 /* The width in bits of the ALT_QSPI_DEVRD_DATAWIDTH register field. */
1105 #define ALT_QSPI_DEVRD_DATAWIDTH_WIDTH 2
1106 /* The mask used to set the ALT_QSPI_DEVRD_DATAWIDTH register field value. */
1107 #define ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK 0x00030000
1108 /* The mask used to clear the ALT_QSPI_DEVRD_DATAWIDTH register field value. */
1109 #define ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK 0xfffcffff
1110 /* The reset value of the ALT_QSPI_DEVRD_DATAWIDTH register field. */
1111 #define ALT_QSPI_DEVRD_DATAWIDTH_RESET 0x0
1112 /* Extracts the ALT_QSPI_DEVRD_DATAWIDTH field value from a register. */
1113 #define ALT_QSPI_DEVRD_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)
1114 /* Produces a ALT_QSPI_DEVRD_DATAWIDTH register field value suitable for setting the register. */
1115 #define ALT_QSPI_DEVRD_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)
1116 
1117 /*
1118  * Field : Mode Bit Enable - enmodebits
1119  *
1120  * If this bit is set, the mode bits as defined in the Mode Bit Configuration
1121  * register are sent following the address bytes.
1122  *
1123  * Field Enumeration Values:
1124  *
1125  * Enum | Value | Description
1126  * :-----------------------------------|:------|:-------------------------------
1127  * ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER | 0x0 | No Order
1128  * ALT_QSPI_DEVRD_ENMODBITS_E_ORDER | 0x1 | Mode Bits follow address bytes
1129  *
1130  * Field Access Macros:
1131  *
1132  */
1133 /*
1134  * Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS
1135  *
1136  * No Order
1137  */
1138 #define ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER 0x0
1139 /*
1140  * Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS
1141  *
1142  * Mode Bits follow address bytes
1143  */
1144 #define ALT_QSPI_DEVRD_ENMODBITS_E_ORDER 0x1
1145 
1146 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field. */
1147 #define ALT_QSPI_DEVRD_ENMODBITS_LSB 20
1148 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field. */
1149 #define ALT_QSPI_DEVRD_ENMODBITS_MSB 20
1150 /* The width in bits of the ALT_QSPI_DEVRD_ENMODBITS register field. */
1151 #define ALT_QSPI_DEVRD_ENMODBITS_WIDTH 1
1152 /* The mask used to set the ALT_QSPI_DEVRD_ENMODBITS register field value. */
1153 #define ALT_QSPI_DEVRD_ENMODBITS_SET_MSK 0x00100000
1154 /* The mask used to clear the ALT_QSPI_DEVRD_ENMODBITS register field value. */
1155 #define ALT_QSPI_DEVRD_ENMODBITS_CLR_MSK 0xffefffff
1156 /* The reset value of the ALT_QSPI_DEVRD_ENMODBITS register field. */
1157 #define ALT_QSPI_DEVRD_ENMODBITS_RESET 0x0
1158 /* Extracts the ALT_QSPI_DEVRD_ENMODBITS field value from a register. */
1159 #define ALT_QSPI_DEVRD_ENMODBITS_GET(value) (((value) & 0x00100000) >> 20)
1160 /* Produces a ALT_QSPI_DEVRD_ENMODBITS register field value suitable for setting the register. */
1161 #define ALT_QSPI_DEVRD_ENMODBITS_SET(value) (((value) << 20) & 0x00100000)
1162 
1163 /*
1164  * Field : Dummy Read Clock Cycles - dummyrdclks
1165  *
1166  * Number of dummy clock cycles required by device for read instruction.
1167  *
1168  * Field Access Macros:
1169  *
1170  */
1171 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */
1172 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB 24
1173 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */
1174 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB 28
1175 /* The width in bits of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */
1176 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH 5
1177 /* The mask used to set the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */
1178 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK 0x1f000000
1179 /* The mask used to clear the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */
1180 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK 0xe0ffffff
1181 /* The reset value of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */
1182 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET 0x0
1183 /* Extracts the ALT_QSPI_DEVRD_DUMMYRDCLKS field value from a register. */
1184 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(value) (((value) & 0x1f000000) >> 24)
1185 /* Produces a ALT_QSPI_DEVRD_DUMMYRDCLKS register field value suitable for setting the register. */
1186 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(value) (((value) << 24) & 0x1f000000)
1187 
1188 #ifndef __ASSEMBLY__
1189 /*
1190  * WARNING: The C register and register group struct declarations are provided for
1191  * convenience and illustrative purposes. They should, however, be used with
1192  * caution as the C language standard provides no guarantees about the alignment or
1193  * atomicity of device memory accesses. The recommended practice for writing
1194  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1195  * alt_write_word() functions.
1196  *
1197  * The struct declaration for register ALT_QSPI_DEVRD.
1198  */
1199 struct ALT_QSPI_DEVRD_s
1200 {
1201  uint32_t rdopcode : 8; /* Read Opcode in non-XIP mode */
1202  uint32_t instwidth : 2; /* Instruction Transfer Width */
1203  uint32_t : 2; /* *UNDEFINED* */
1204  uint32_t addrwidth : 2; /* Address Transfer Width */
1205  uint32_t : 2; /* *UNDEFINED* */
1206  uint32_t datawidth : 2; /* Data Transfer Width */
1207  uint32_t : 2; /* *UNDEFINED* */
1208  uint32_t enmodebits : 1; /* Mode Bit Enable */
1209  uint32_t : 3; /* *UNDEFINED* */
1210  uint32_t dummyrdclks : 5; /* Dummy Read Clock Cycles */
1211  uint32_t : 3; /* *UNDEFINED* */
1212 };
1213 
1214 /* The typedef declaration for register ALT_QSPI_DEVRD. */
1215 typedef volatile struct ALT_QSPI_DEVRD_s ALT_QSPI_DEVRD_t;
1216 #endif /* __ASSEMBLY__ */
1217 
1218 /* The byte offset of the ALT_QSPI_DEVRD register from the beginning of the component. */
1219 #define ALT_QSPI_DEVRD_OFST 0x4
1220 
1221 /*
1222  * Register : Device Write Instruction Register - devwr
1223  *
1224  * Register Layout
1225  *
1226  * Bits | Access | Reset | Description
1227  * :--------|:-------|:------|:-------------------------
1228  * [7:0] | RW | 0x2 | Write Opcode
1229  * [11:8] | ??? | 0x0 | *UNDEFINED*
1230  * [13:12] | RW | 0x0 | Address Transfer Width
1231  * [15:14] | ??? | 0x0 | *UNDEFINED*
1232  * [17:16] | RW | 0x0 | Data Transfer Width
1233  * [23:18] | ??? | 0x0 | *UNDEFINED*
1234  * [28:24] | RW | 0x0 | Dummy Write Clock Cycles
1235  * [31:29] | ??? | 0x0 | *UNDEFINED*
1236  *
1237  */
1238 /*
1239  * Field : Write Opcode - wropcode
1240  *
1241  * Write Opcode
1242  *
1243  * Field Access Macros:
1244  *
1245  */
1246 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */
1247 #define ALT_QSPI_DEVWR_WROPCODE_LSB 0
1248 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */
1249 #define ALT_QSPI_DEVWR_WROPCODE_MSB 7
1250 /* The width in bits of the ALT_QSPI_DEVWR_WROPCODE register field. */
1251 #define ALT_QSPI_DEVWR_WROPCODE_WIDTH 8
1252 /* The mask used to set the ALT_QSPI_DEVWR_WROPCODE register field value. */
1253 #define ALT_QSPI_DEVWR_WROPCODE_SET_MSK 0x000000ff
1254 /* The mask used to clear the ALT_QSPI_DEVWR_WROPCODE register field value. */
1255 #define ALT_QSPI_DEVWR_WROPCODE_CLR_MSK 0xffffff00
1256 /* The reset value of the ALT_QSPI_DEVWR_WROPCODE register field. */
1257 #define ALT_QSPI_DEVWR_WROPCODE_RESET 0x2
1258 /* Extracts the ALT_QSPI_DEVWR_WROPCODE field value from a register. */
1259 #define ALT_QSPI_DEVWR_WROPCODE_GET(value) (((value) & 0x000000ff) >> 0)
1260 /* Produces a ALT_QSPI_DEVWR_WROPCODE register field value suitable for setting the register. */
1261 #define ALT_QSPI_DEVWR_WROPCODE_SET(value) (((value) << 0) & 0x000000ff)
1262 
1263 /*
1264  * Field : Address Transfer Width - addrwidth
1265  *
1266  * Sets write address transfer width (1, 2, or 4 bits).
1267  *
1268  * Field Enumeration Values:
1269  *
1270  * Enum | Value | Description
1271  * :----------------------------------|:------|:-------------------------------------------------
1272  * ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE | 0x0 | Write address transferred on DQ0. Supported by
1273  * : | | all SPI flash devices
1274  * ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL | 0x1 | Read address transferred on DQ0 and DQ1.
1275  * : | | Supported by some SPI flash devices that support
1276  * : | | the Extended SPI Protocol and by all SPI flash
1277  * : | | devices that support the Dual SP (DIO-SPI)
1278  * : | | Protocol.
1279  * ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD | 0x2 | Read address transferred on DQ0, DQ1, DQ2, and
1280  * : | | DQ3. Supported by some SPI flash devices that
1281  * : | | support the Extended SPI Protocol and by all SPI
1282  * : | | flash devices that support the Quad SP (QIO-SPI)
1283  * : | | Protocol.
1284  *
1285  * Field Access Macros:
1286  *
1287  */
1288 /*
1289  * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH
1290  *
1291  * Write address transferred on DQ0. Supported by all SPI flash devices
1292  */
1293 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE 0x0
1294 /*
1295  * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH
1296  *
1297  * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices
1298  * that support the Extended SPI Protocol and by all SPI flash devices that support
1299  * the Dual SP (DIO-SPI) Protocol.
1300  */
1301 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL 0x1
1302 /*
1303  * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH
1304  *
1305  * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash
1306  * devices that support the Extended SPI Protocol and by all SPI flash devices that
1307  * support the Quad SP (QIO-SPI) Protocol.
1308  */
1309 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD 0x2
1310 
1311 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */
1312 #define ALT_QSPI_DEVWR_ADDRWIDTH_LSB 12
1313 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */
1314 #define ALT_QSPI_DEVWR_ADDRWIDTH_MSB 13
1315 /* The width in bits of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */
1316 #define ALT_QSPI_DEVWR_ADDRWIDTH_WIDTH 2
1317 /* The mask used to set the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */
1318 #define ALT_QSPI_DEVWR_ADDRWIDTH_SET_MSK 0x00003000
1319 /* The mask used to clear the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */
1320 #define ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK 0xffffcfff
1321 /* The reset value of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */
1322 #define ALT_QSPI_DEVWR_ADDRWIDTH_RESET 0x0
1323 /* Extracts the ALT_QSPI_DEVWR_ADDRWIDTH field value from a register. */
1324 #define ALT_QSPI_DEVWR_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)
1325 /* Produces a ALT_QSPI_DEVWR_ADDRWIDTH register field value suitable for setting the register. */
1326 #define ALT_QSPI_DEVWR_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)
1327 
1328 /*
1329  * Field : Data Transfer Width - datawidth
1330  *
1331  * Sets write data transfer width (1, 2, or 4 bits).
1332  *
1333  * Field Enumeration Values:
1334  *
1335  * Enum | Value | Description
1336  * :----------------------------------|:------|:-------------------------------------------------
1337  * ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE | 0x0 | Write data transferred on DQ0. Supported by all
1338  * : | | SPI flash devices
1339  * ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL | 0x1 | Read data transferred on DQ0 and DQ1. Supported
1340  * : | | by some SPI flash devices that support the
1341  * : | | Extended SPI Protocol and by all SPI flash
1342  * : | | devices that support the Dual SP (DIO-SPI)
1343  * : | | Protocol.
1344  * ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD | 0x2 | Read data transferred on DQ0, DQ1, DQ2, and DQ3.
1345  * : | | Supported by some SPI flash devices that support
1346  * : | | the Extended SPI Protocol and by all SPI flash
1347  * : | | devices that support the Quad SP (QIO-SPI)
1348  * : | | Protocol.
1349  *
1350  * Field Access Macros:
1351  *
1352  */
1353 /*
1354  * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH
1355  *
1356  * Write data transferred on DQ0. Supported by all SPI flash devices
1357  */
1358 #define ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE 0x0
1359 /*
1360  * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH
1361  *
1362  * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that
1363  * support the Extended SPI Protocol and by all SPI flash devices that support the
1364  * Dual SP (DIO-SPI) Protocol.
1365  */
1366 #define ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL 0x1
1367 /*
1368  * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH
1369  *
1370  * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash
1371  * devices that support the Extended SPI Protocol and by all SPI flash devices that
1372  * support the Quad SP (QIO-SPI) Protocol.
1373  */
1374 #define ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD 0x2
1375 
1376 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */
1377 #define ALT_QSPI_DEVWR_DATAWIDTH_LSB 16
1378 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */
1379 #define ALT_QSPI_DEVWR_DATAWIDTH_MSB 17
1380 /* The width in bits of the ALT_QSPI_DEVWR_DATAWIDTH register field. */
1381 #define ALT_QSPI_DEVWR_DATAWIDTH_WIDTH 2
1382 /* The mask used to set the ALT_QSPI_DEVWR_DATAWIDTH register field value. */
1383 #define ALT_QSPI_DEVWR_DATAWIDTH_SET_MSK 0x00030000
1384 /* The mask used to clear the ALT_QSPI_DEVWR_DATAWIDTH register field value. */
1385 #define ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK 0xfffcffff
1386 /* The reset value of the ALT_QSPI_DEVWR_DATAWIDTH register field. */
1387 #define ALT_QSPI_DEVWR_DATAWIDTH_RESET 0x0
1388 /* Extracts the ALT_QSPI_DEVWR_DATAWIDTH field value from a register. */
1389 #define ALT_QSPI_DEVWR_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)
1390 /* Produces a ALT_QSPI_DEVWR_DATAWIDTH register field value suitable for setting the register. */
1391 #define ALT_QSPI_DEVWR_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)
1392 
1393 /*
1394  * Field : Dummy Write Clock Cycles - dummywrclks
1395  *
1396  * Number of dummy clock cycles required by device for write instruction.
1397  *
1398  * Field Access Macros:
1399  *
1400  */
1401 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */
1402 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_LSB 24
1403 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */
1404 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_MSB 28
1405 /* The width in bits of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */
1406 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH 5
1407 /* The mask used to set the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */
1408 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET_MSK 0x1f000000
1409 /* The mask used to clear the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */
1410 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK 0xe0ffffff
1411 /* The reset value of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */
1412 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_RESET 0x0
1413 /* Extracts the ALT_QSPI_DEVWR_DUMMYWRCLKS field value from a register. */
1414 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(value) (((value) & 0x1f000000) >> 24)
1415 /* Produces a ALT_QSPI_DEVWR_DUMMYWRCLKS register field value suitable for setting the register. */
1416 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(value) (((value) << 24) & 0x1f000000)
1417 
1418 #ifndef __ASSEMBLY__
1419 /*
1420  * WARNING: The C register and register group struct declarations are provided for
1421  * convenience and illustrative purposes. They should, however, be used with
1422  * caution as the C language standard provides no guarantees about the alignment or
1423  * atomicity of device memory accesses. The recommended practice for writing
1424  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1425  * alt_write_word() functions.
1426  *
1427  * The struct declaration for register ALT_QSPI_DEVWR.
1428  */
1429 struct ALT_QSPI_DEVWR_s
1430 {
1431  uint32_t wropcode : 8; /* Write Opcode */
1432  uint32_t : 4; /* *UNDEFINED* */
1433  uint32_t addrwidth : 2; /* Address Transfer Width */
1434  uint32_t : 2; /* *UNDEFINED* */
1435  uint32_t datawidth : 2; /* Data Transfer Width */
1436  uint32_t : 6; /* *UNDEFINED* */
1437  uint32_t dummywrclks : 5; /* Dummy Write Clock Cycles */
1438  uint32_t : 3; /* *UNDEFINED* */
1439 };
1440 
1441 /* The typedef declaration for register ALT_QSPI_DEVWR. */
1442 typedef volatile struct ALT_QSPI_DEVWR_s ALT_QSPI_DEVWR_t;
1443 #endif /* __ASSEMBLY__ */
1444 
1445 /* The byte offset of the ALT_QSPI_DEVWR register from the beginning of the component. */
1446 #define ALT_QSPI_DEVWR_OFST 0x8
1447 
1448 /*
1449  * Register : QSPI Device Delay Register - delay
1450  *
1451  * This register is used to introduce relative delays into the generation of the
1452  * master output signals. All timings are defined in cycles of the qspi_clk.
1453  *
1454  * Register Layout
1455  *
1456  * Bits | Access | Reset | Description
1457  * :--------|:-------|:------|:-----------------------------------------
1458  * [7:0] | RW | 0x0 | Clock Delay with qspi_n_ss_out
1459  * [15:8] | RW | 0x0 | Clock Delay for Last Transaction Bit
1460  * [23:16] | RW | 0x0 | Clock Delay for Chip Select Deactivation
1461  * [31:24] | RW | 0x0 | Clock Delay for Chip Select Deassert
1462  *
1463  */
1464 /*
1465  * Field : Clock Delay with qspi_n_ss_out - init
1466  *
1467  * Delay in master reference clocks between setting qspi_n_ss_out low and first bit
1468  * transfer.
1469  *
1470  * Field Access Macros:
1471  *
1472  */
1473 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_INIT register field. */
1474 #define ALT_QSPI_DELAY_INIT_LSB 0
1475 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_INIT register field. */
1476 #define ALT_QSPI_DELAY_INIT_MSB 7
1477 /* The width in bits of the ALT_QSPI_DELAY_INIT register field. */
1478 #define ALT_QSPI_DELAY_INIT_WIDTH 8
1479 /* The mask used to set the ALT_QSPI_DELAY_INIT register field value. */
1480 #define ALT_QSPI_DELAY_INIT_SET_MSK 0x000000ff
1481 /* The mask used to clear the ALT_QSPI_DELAY_INIT register field value. */
1482 #define ALT_QSPI_DELAY_INIT_CLR_MSK 0xffffff00
1483 /* The reset value of the ALT_QSPI_DELAY_INIT register field. */
1484 #define ALT_QSPI_DELAY_INIT_RESET 0x0
1485 /* Extracts the ALT_QSPI_DELAY_INIT field value from a register. */
1486 #define ALT_QSPI_DELAY_INIT_GET(value) (((value) & 0x000000ff) >> 0)
1487 /* Produces a ALT_QSPI_DELAY_INIT register field value suitable for setting the register. */
1488 #define ALT_QSPI_DELAY_INIT_SET(value) (((value) << 0) & 0x000000ff)
1489 
1490 /*
1491  * Field : Clock Delay for Last Transaction Bit - after
1492  *
1493  * Delay in master reference clocks between last bit of current transaction and
1494  * deasserting the device chip select (qspi_n_ss_out). By default, the chip select
1495  * will be deasserted on the cycle following the completion of the current
1496  * transaction.
1497  *
1498  * Field Access Macros:
1499  *
1500  */
1501 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_AFTER register field. */
1502 #define ALT_QSPI_DELAY_AFTER_LSB 8
1503 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_AFTER register field. */
1504 #define ALT_QSPI_DELAY_AFTER_MSB 15
1505 /* The width in bits of the ALT_QSPI_DELAY_AFTER register field. */
1506 #define ALT_QSPI_DELAY_AFTER_WIDTH 8
1507 /* The mask used to set the ALT_QSPI_DELAY_AFTER register field value. */
1508 #define ALT_QSPI_DELAY_AFTER_SET_MSK 0x0000ff00
1509 /* The mask used to clear the ALT_QSPI_DELAY_AFTER register field value. */
1510 #define ALT_QSPI_DELAY_AFTER_CLR_MSK 0xffff00ff
1511 /* The reset value of the ALT_QSPI_DELAY_AFTER register field. */
1512 #define ALT_QSPI_DELAY_AFTER_RESET 0x0
1513 /* Extracts the ALT_QSPI_DELAY_AFTER field value from a register. */
1514 #define ALT_QSPI_DELAY_AFTER_GET(value) (((value) & 0x0000ff00) >> 8)
1515 /* Produces a ALT_QSPI_DELAY_AFTER register field value suitable for setting the register. */
1516 #define ALT_QSPI_DELAY_AFTER_SET(value) (((value) << 8) & 0x0000ff00)
1517 
1518 /*
1519  * Field : Clock Delay for Chip Select Deactivation - btwn
1520  *
1521  * Delay in master reference clocks between one chip select being de-activated and
1522  * the activation of another. This is used to ensure a quiet period between the
1523  * selection of two different slaves and requires the transmit FIFO to be empty.
1524  *
1525  * Field Access Macros:
1526  *
1527  */
1528 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_BTWN register field. */
1529 #define ALT_QSPI_DELAY_BTWN_LSB 16
1530 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_BTWN register field. */
1531 #define ALT_QSPI_DELAY_BTWN_MSB 23
1532 /* The width in bits of the ALT_QSPI_DELAY_BTWN register field. */
1533 #define ALT_QSPI_DELAY_BTWN_WIDTH 8
1534 /* The mask used to set the ALT_QSPI_DELAY_BTWN register field value. */
1535 #define ALT_QSPI_DELAY_BTWN_SET_MSK 0x00ff0000
1536 /* The mask used to clear the ALT_QSPI_DELAY_BTWN register field value. */
1537 #define ALT_QSPI_DELAY_BTWN_CLR_MSK 0xff00ffff
1538 /* The reset value of the ALT_QSPI_DELAY_BTWN register field. */
1539 #define ALT_QSPI_DELAY_BTWN_RESET 0x0
1540 /* Extracts the ALT_QSPI_DELAY_BTWN field value from a register. */
1541 #define ALT_QSPI_DELAY_BTWN_GET(value) (((value) & 0x00ff0000) >> 16)
1542 /* Produces a ALT_QSPI_DELAY_BTWN register field value suitable for setting the register. */
1543 #define ALT_QSPI_DELAY_BTWN_SET(value) (((value) << 16) & 0x00ff0000)
1544 
1545 /*
1546  * Field : Clock Delay for Chip Select Deassert - nss
1547  *
1548  * Delay in master reference clocks for the length that the master mode chip select
1549  * outputs are de-asserted between transactions. The minimum delay is always
1550  * qspi_sck_out period to ensure the chip select is never re-asserted within an
1551  * qspi_sck_out period.
1552  *
1553  * Field Access Macros:
1554  *
1555  */
1556 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_NSS register field. */
1557 #define ALT_QSPI_DELAY_NSS_LSB 24
1558 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_NSS register field. */
1559 #define ALT_QSPI_DELAY_NSS_MSB 31
1560 /* The width in bits of the ALT_QSPI_DELAY_NSS register field. */
1561 #define ALT_QSPI_DELAY_NSS_WIDTH 8
1562 /* The mask used to set the ALT_QSPI_DELAY_NSS register field value. */
1563 #define ALT_QSPI_DELAY_NSS_SET_MSK 0xff000000
1564 /* The mask used to clear the ALT_QSPI_DELAY_NSS register field value. */
1565 #define ALT_QSPI_DELAY_NSS_CLR_MSK 0x00ffffff
1566 /* The reset value of the ALT_QSPI_DELAY_NSS register field. */
1567 #define ALT_QSPI_DELAY_NSS_RESET 0x0
1568 /* Extracts the ALT_QSPI_DELAY_NSS field value from a register. */
1569 #define ALT_QSPI_DELAY_NSS_GET(value) (((value) & 0xff000000) >> 24)
1570 /* Produces a ALT_QSPI_DELAY_NSS register field value suitable for setting the register. */
1571 #define ALT_QSPI_DELAY_NSS_SET(value) (((value) << 24) & 0xff000000)
1572 
1573 #ifndef __ASSEMBLY__
1574 /*
1575  * WARNING: The C register and register group struct declarations are provided for
1576  * convenience and illustrative purposes. They should, however, be used with
1577  * caution as the C language standard provides no guarantees about the alignment or
1578  * atomicity of device memory accesses. The recommended practice for writing
1579  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1580  * alt_write_word() functions.
1581  *
1582  * The struct declaration for register ALT_QSPI_DELAY.
1583  */
1584 struct ALT_QSPI_DELAY_s
1585 {
1586  uint32_t init : 8; /* Clock Delay with qspi_n_ss_out */
1587  uint32_t after : 8; /* Clock Delay for Last Transaction Bit */
1588  uint32_t btwn : 8; /* Clock Delay for Chip Select Deactivation */
1589  uint32_t nss : 8; /* Clock Delay for Chip Select Deassert */
1590 };
1591 
1592 /* The typedef declaration for register ALT_QSPI_DELAY. */
1593 typedef volatile struct ALT_QSPI_DELAY_s ALT_QSPI_DELAY_t;
1594 #endif /* __ASSEMBLY__ */
1595 
1596 /* The byte offset of the ALT_QSPI_DELAY register from the beginning of the component. */
1597 #define ALT_QSPI_DELAY_OFST 0xc
1598 
1599 /*
1600  * Register : Read Data Capture Register - rddatacap
1601  *
1602  * Register Layout
1603  *
1604  * Bits | Access | Reset | Description
1605  * :-------|:-------|:------|:------------
1606  * [0] | RW | 0x1 | Bypass
1607  * [4:1] | RW | 0x0 | Read Delay
1608  * [31:5] | ??? | 0x0 | *UNDEFINED*
1609  *
1610  */
1611 /*
1612  * Field : Bypass - byp
1613  *
1614  * Controls bypass of the adapted loopback clock circuit
1615  *
1616  * Field Enumeration Values:
1617  *
1618  * Enum | Value | Description
1619  * :----------------------------------|:------|:------------------------------
1620  * ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS | 0x0 | No Bypass
1621  * ALT_QSPI_RDDATACAP_BYP_E_BYPASS | 0x1 | Bypass loopback clock circuit
1622  *
1623  * Field Access Macros:
1624  *
1625  */
1626 /*
1627  * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP
1628  *
1629  * No Bypass
1630  */
1631 #define ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS 0x0
1632 /*
1633  * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP
1634  *
1635  * Bypass loopback clock circuit
1636  */
1637 #define ALT_QSPI_RDDATACAP_BYP_E_BYPASS 0x1
1638 
1639 /* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */
1640 #define ALT_QSPI_RDDATACAP_BYP_LSB 0
1641 /* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */
1642 #define ALT_QSPI_RDDATACAP_BYP_MSB 0
1643 /* The width in bits of the ALT_QSPI_RDDATACAP_BYP register field. */
1644 #define ALT_QSPI_RDDATACAP_BYP_WIDTH 1
1645 /* The mask used to set the ALT_QSPI_RDDATACAP_BYP register field value. */
1646 #define ALT_QSPI_RDDATACAP_BYP_SET_MSK 0x00000001
1647 /* The mask used to clear the ALT_QSPI_RDDATACAP_BYP register field value. */
1648 #define ALT_QSPI_RDDATACAP_BYP_CLR_MSK 0xfffffffe
1649 /* The reset value of the ALT_QSPI_RDDATACAP_BYP register field. */
1650 #define ALT_QSPI_RDDATACAP_BYP_RESET 0x1
1651 /* Extracts the ALT_QSPI_RDDATACAP_BYP field value from a register. */
1652 #define ALT_QSPI_RDDATACAP_BYP_GET(value) (((value) & 0x00000001) >> 0)
1653 /* Produces a ALT_QSPI_RDDATACAP_BYP register field value suitable for setting the register. */
1654 #define ALT_QSPI_RDDATACAP_BYP_SET(value) (((value) << 0) & 0x00000001)
1655 
1656 /*
1657  * Field : Read Delay - delay
1658  *
1659  * Delay the read data capturing logic by the programmed number of qspi_clk cycles
1660  *
1661  * Field Access Macros:
1662  *
1663  */
1664 /* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */
1665 #define ALT_QSPI_RDDATACAP_DELAY_LSB 1
1666 /* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */
1667 #define ALT_QSPI_RDDATACAP_DELAY_MSB 4
1668 /* The width in bits of the ALT_QSPI_RDDATACAP_DELAY register field. */
1669 #define ALT_QSPI_RDDATACAP_DELAY_WIDTH 4
1670 /* The mask used to set the ALT_QSPI_RDDATACAP_DELAY register field value. */
1671 #define ALT_QSPI_RDDATACAP_DELAY_SET_MSK 0x0000001e
1672 /* The mask used to clear the ALT_QSPI_RDDATACAP_DELAY register field value. */
1673 #define ALT_QSPI_RDDATACAP_DELAY_CLR_MSK 0xffffffe1
1674 /* The reset value of the ALT_QSPI_RDDATACAP_DELAY register field. */
1675 #define ALT_QSPI_RDDATACAP_DELAY_RESET 0x0
1676 /* Extracts the ALT_QSPI_RDDATACAP_DELAY field value from a register. */
1677 #define ALT_QSPI_RDDATACAP_DELAY_GET(value) (((value) & 0x0000001e) >> 1)
1678 /* Produces a ALT_QSPI_RDDATACAP_DELAY register field value suitable for setting the register. */
1679 #define ALT_QSPI_RDDATACAP_DELAY_SET(value) (((value) << 1) & 0x0000001e)
1680 
1681 #ifndef __ASSEMBLY__
1682 /*
1683  * WARNING: The C register and register group struct declarations are provided for
1684  * convenience and illustrative purposes. They should, however, be used with
1685  * caution as the C language standard provides no guarantees about the alignment or
1686  * atomicity of device memory accesses. The recommended practice for writing
1687  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1688  * alt_write_word() functions.
1689  *
1690  * The struct declaration for register ALT_QSPI_RDDATACAP.
1691  */
1692 struct ALT_QSPI_RDDATACAP_s
1693 {
1694  uint32_t byp : 1; /* Bypass */
1695  uint32_t delay : 4; /* Read Delay */
1696  uint32_t : 27; /* *UNDEFINED* */
1697 };
1698 
1699 /* The typedef declaration for register ALT_QSPI_RDDATACAP. */
1700 typedef volatile struct ALT_QSPI_RDDATACAP_s ALT_QSPI_RDDATACAP_t;
1701 #endif /* __ASSEMBLY__ */
1702 
1703 /* The byte offset of the ALT_QSPI_RDDATACAP register from the beginning of the component. */
1704 #define ALT_QSPI_RDDATACAP_OFST 0x10
1705 
1706 /*
1707  * Register : Device Size Register - devsz
1708  *
1709  * Register Layout
1710  *
1711  * Bits | Access | Reset | Description
1712  * :--------|:-------|:------|:--------------------------------
1713  * [3:0] | RW | 0x2 | Number of address Bytes
1714  * [15:4] | RW | 0x100 | Number of Bytes per Device Page
1715  * [20:16] | RW | 0x10 | Number of Bytes per Block
1716  * [31:21] | ??? | 0x0 | *UNDEFINED*
1717  *
1718  */
1719 /*
1720  * Field : Number of address Bytes - numaddrbytes
1721  *
1722  * Number of address bytes. A value of 0 indicates 1 byte.
1723  *
1724  * Field Access Macros:
1725  *
1726  */
1727 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */
1728 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_LSB 0
1729 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */
1730 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_MSB 3
1731 /* The width in bits of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */
1732 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_WIDTH 4
1733 /* The mask used to set the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */
1734 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET_MSK 0x0000000f
1735 /* The mask used to clear the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */
1736 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_CLR_MSK 0xfffffff0
1737 /* The reset value of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */
1738 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_RESET 0x2
1739 /* Extracts the ALT_QSPI_DEVSZ_NUMADDRBYTES field value from a register. */
1740 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_GET(value) (((value) & 0x0000000f) >> 0)
1741 /* Produces a ALT_QSPI_DEVSZ_NUMADDRBYTES register field value suitable for setting the register. */
1742 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET(value) (((value) << 0) & 0x0000000f)
1743 
1744 /*
1745  * Field : Number of Bytes per Device Page - bytesperdevicepage
1746  *
1747  * Number of bytes per device page. This is required by the controller for
1748  * performing FLASH writes up to and across page boundaries.
1749  *
1750  * Field Access Macros:
1751  *
1752  */
1753 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */
1754 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_LSB 4
1755 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */
1756 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_MSB 15
1757 /* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */
1758 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_WIDTH 12
1759 /* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */
1760 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET_MSK 0x0000fff0
1761 /* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */
1762 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_CLR_MSK 0xffff000f
1763 /* The reset value of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */
1764 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_RESET 0x100
1765 /* Extracts the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE field value from a register. */
1766 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_GET(value) (((value) & 0x0000fff0) >> 4)
1767 /* Produces a ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value suitable for setting the register. */
1768 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET(value) (((value) << 4) & 0x0000fff0)
1769 
1770 /*
1771  * Field : Number of Bytes per Block - bytespersubsector
1772  *
1773  * Number of bytes per Block. This is required by the controller for performing the
1774  * write protection logic. The number of bytes per block must be a power of 2
1775  * number.
1776  *
1777  * Field Access Macros:
1778  *
1779  */
1780 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */
1781 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_LSB 16
1782 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */
1783 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_MSB 20
1784 /* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */
1785 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_WIDTH 5
1786 /* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */
1787 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET_MSK 0x001f0000
1788 /* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */
1789 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_CLR_MSK 0xffe0ffff
1790 /* The reset value of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */
1791 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_RESET 0x10
1792 /* Extracts the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR field value from a register. */
1793 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_GET(value) (((value) & 0x001f0000) >> 16)
1794 /* Produces a ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value suitable for setting the register. */
1795 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET(value) (((value) << 16) & 0x001f0000)
1796 
1797 #ifndef __ASSEMBLY__
1798 /*
1799  * WARNING: The C register and register group struct declarations are provided for
1800  * convenience and illustrative purposes. They should, however, be used with
1801  * caution as the C language standard provides no guarantees about the alignment or
1802  * atomicity of device memory accesses. The recommended practice for writing
1803  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1804  * alt_write_word() functions.
1805  *
1806  * The struct declaration for register ALT_QSPI_DEVSZ.
1807  */
1808 struct ALT_QSPI_DEVSZ_s
1809 {
1810  uint32_t numaddrbytes : 4; /* Number of address Bytes */
1811  uint32_t bytesperdevicepage : 12; /* Number of Bytes per Device Page */
1812  uint32_t bytespersubsector : 5; /* Number of Bytes per Block */
1813  uint32_t : 11; /* *UNDEFINED* */
1814 };
1815 
1816 /* The typedef declaration for register ALT_QSPI_DEVSZ. */
1817 typedef volatile struct ALT_QSPI_DEVSZ_s ALT_QSPI_DEVSZ_t;
1818 #endif /* __ASSEMBLY__ */
1819 
1820 /* The byte offset of the ALT_QSPI_DEVSZ register from the beginning of the component. */
1821 #define ALT_QSPI_DEVSZ_OFST 0x14
1822 
1823 /*
1824  * Register : SRAM Partition Register - srampart
1825  *
1826  * Register Layout
1827  *
1828  * Bits | Access | Reset | Description
1829  * :-------|:-------|:------|:-----------------------------
1830  * [6:0] | RW | 0x40 | Indirect Read Partition Size
1831  * [31:7] | ??? | 0x0 | *UNDEFINED*
1832  *
1833  */
1834 /*
1835  * Field : Indirect Read Partition Size - addr
1836  *
1837  * Defines the size of the indirect read partition in the SRAM, in units of SRAM
1838  * locations. By default, half of the SRAM is reserved for indirect read operations
1839  * and half for indirect write operations.
1840  *
1841  * Field Access Macros:
1842  *
1843  */
1844 /* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */
1845 #define ALT_QSPI_SRAMPART_ADDR_LSB 0
1846 /* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */
1847 #define ALT_QSPI_SRAMPART_ADDR_MSB 6
1848 /* The width in bits of the ALT_QSPI_SRAMPART_ADDR register field. */
1849 #define ALT_QSPI_SRAMPART_ADDR_WIDTH 7
1850 /* The mask used to set the ALT_QSPI_SRAMPART_ADDR register field value. */
1851 #define ALT_QSPI_SRAMPART_ADDR_SET_MSK 0x0000007f
1852 /* The mask used to clear the ALT_QSPI_SRAMPART_ADDR register field value. */
1853 #define ALT_QSPI_SRAMPART_ADDR_CLR_MSK 0xffffff80
1854 /* The reset value of the ALT_QSPI_SRAMPART_ADDR register field. */
1855 #define ALT_QSPI_SRAMPART_ADDR_RESET 0x40
1856 /* Extracts the ALT_QSPI_SRAMPART_ADDR field value from a register. */
1857 #define ALT_QSPI_SRAMPART_ADDR_GET(value) (((value) & 0x0000007f) >> 0)
1858 /* Produces a ALT_QSPI_SRAMPART_ADDR register field value suitable for setting the register. */
1859 #define ALT_QSPI_SRAMPART_ADDR_SET(value) (((value) << 0) & 0x0000007f)
1860 
1861 #ifndef __ASSEMBLY__
1862 /*
1863  * WARNING: The C register and register group struct declarations are provided for
1864  * convenience and illustrative purposes. They should, however, be used with
1865  * caution as the C language standard provides no guarantees about the alignment or
1866  * atomicity of device memory accesses. The recommended practice for writing
1867  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1868  * alt_write_word() functions.
1869  *
1870  * The struct declaration for register ALT_QSPI_SRAMPART.
1871  */
1872 struct ALT_QSPI_SRAMPART_s
1873 {
1874  uint32_t addr : 7; /* Indirect Read Partition Size */
1875  uint32_t : 25; /* *UNDEFINED* */
1876 };
1877 
1878 /* The typedef declaration for register ALT_QSPI_SRAMPART. */
1879 typedef volatile struct ALT_QSPI_SRAMPART_s ALT_QSPI_SRAMPART_t;
1880 #endif /* __ASSEMBLY__ */
1881 
1882 /* The byte offset of the ALT_QSPI_SRAMPART register from the beginning of the component. */
1883 #define ALT_QSPI_SRAMPART_OFST 0x18
1884 
1885 /*
1886  * Register : Indirect AHB Address Trigger Register - indaddrtrig
1887  *
1888  * Register Layout
1889  *
1890  * Bits | Access | Reset | Description
1891  * :-------|:-------|:------|:----------------
1892  * [31:0] | RW | 0x0 | Trigger Address
1893  *
1894  */
1895 /*
1896  * Field : Trigger Address - addr
1897  *
1898  * This is the base address that will be used by the AHB controller. When the
1899  * incoming AHB read access address matches a range of addresses from this trigger
1900  * address to the trigger address + 15, then the AHB request will be completed by
1901  * fetching data from the Indirect Controllers SRAM.
1902  *
1903  * Field Access Macros:
1904  *
1905  */
1906 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */
1907 #define ALT_QSPI_INDADDRTRIG_ADDR_LSB 0
1908 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */
1909 #define ALT_QSPI_INDADDRTRIG_ADDR_MSB 31
1910 /* The width in bits of the ALT_QSPI_INDADDRTRIG_ADDR register field. */
1911 #define ALT_QSPI_INDADDRTRIG_ADDR_WIDTH 32
1912 /* The mask used to set the ALT_QSPI_INDADDRTRIG_ADDR register field value. */
1913 #define ALT_QSPI_INDADDRTRIG_ADDR_SET_MSK 0xffffffff
1914 /* The mask used to clear the ALT_QSPI_INDADDRTRIG_ADDR register field value. */
1915 #define ALT_QSPI_INDADDRTRIG_ADDR_CLR_MSK 0x00000000
1916 /* The reset value of the ALT_QSPI_INDADDRTRIG_ADDR register field. */
1917 #define ALT_QSPI_INDADDRTRIG_ADDR_RESET 0x0
1918 /* Extracts the ALT_QSPI_INDADDRTRIG_ADDR field value from a register. */
1919 #define ALT_QSPI_INDADDRTRIG_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
1920 /* Produces a ALT_QSPI_INDADDRTRIG_ADDR register field value suitable for setting the register. */
1921 #define ALT_QSPI_INDADDRTRIG_ADDR_SET(value) (((value) << 0) & 0xffffffff)
1922 
1923 #ifndef __ASSEMBLY__
1924 /*
1925  * WARNING: The C register and register group struct declarations are provided for
1926  * convenience and illustrative purposes. They should, however, be used with
1927  * caution as the C language standard provides no guarantees about the alignment or
1928  * atomicity of device memory accesses. The recommended practice for writing
1929  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1930  * alt_write_word() functions.
1931  *
1932  * The struct declaration for register ALT_QSPI_INDADDRTRIG.
1933  */
1934 struct ALT_QSPI_INDADDRTRIG_s
1935 {
1936  uint32_t addr : 32; /* Trigger Address */
1937 };
1938 
1939 /* The typedef declaration for register ALT_QSPI_INDADDRTRIG. */
1940 typedef volatile struct ALT_QSPI_INDADDRTRIG_s ALT_QSPI_INDADDRTRIG_t;
1941 #endif /* __ASSEMBLY__ */
1942 
1943 /* The byte offset of the ALT_QSPI_INDADDRTRIG register from the beginning of the component. */
1944 #define ALT_QSPI_INDADDRTRIG_OFST 0x1c
1945 
1946 /*
1947  * Register : DMA Peripheral Register - dmaper
1948  *
1949  * Register Layout
1950  *
1951  * Bits | Access | Reset | Description
1952  * :--------|:-------|:------|:-----------------------
1953  * [3:0] | RW | 0x0 | Number of Single Bytes
1954  * [7:4] | ??? | 0x0 | *UNDEFINED*
1955  * [11:8] | RW | 0x0 | Number of Burst Bytes
1956  * [31:12] | ??? | 0x0 | *UNDEFINED*
1957  *
1958  */
1959 /*
1960  * Field : Number of Single Bytes - numsglreqbytes
1961  *
1962  * Number of bytes in a single type request on the DMA peripheral request. A
1963  * programmed value of 0 represents a single byte. This should be setup before
1964  * starting the indirect read or write operation. The actual number of bytes used
1965  * is 2**(value in this register) which will simplify implementation.
1966  *
1967  * Field Access Macros:
1968  *
1969  */
1970 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */
1971 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_LSB 0
1972 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */
1973 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_MSB 3
1974 /* The width in bits of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */
1975 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_WIDTH 4
1976 /* The mask used to set the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */
1977 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET_MSK 0x0000000f
1978 /* The mask used to clear the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */
1979 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_CLR_MSK 0xfffffff0
1980 /* The reset value of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */
1981 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_RESET 0x0
1982 /* Extracts the ALT_QSPI_DMAPER_NUMSGLREQBYTES field value from a register. */
1983 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(value) (((value) & 0x0000000f) >> 0)
1984 /* Produces a ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value suitable for setting the register. */
1985 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET(value) (((value) << 0) & 0x0000000f)
1986 
1987 /*
1988  * Field : Number of Burst Bytes - numburstreqbytes
1989  *
1990  * Number of bytes in a burst type request on the DMA peripheral request. A
1991  * programmed value of 0 represents a single byte. This should be setup before
1992  * starting the indirect read or write operation. The actual number of bytes used
1993  * is 2**(value in this register) which will simplify implementation.
1994  *
1995  * Field Access Macros:
1996  *
1997  */
1998 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */
1999 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_LSB 8
2000 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */
2001 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_MSB 11
2002 /* The width in bits of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */
2003 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_WIDTH 4
2004 /* The mask used to set the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */
2005 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET_MSK 0x00000f00
2006 /* The mask used to clear the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */
2007 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_CLR_MSK 0xfffff0ff
2008 /* The reset value of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */
2009 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_RESET 0x0
2010 /* Extracts the ALT_QSPI_DMAPER_NUMBURSTREQBYTES field value from a register. */
2011 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(value) (((value) & 0x00000f00) >> 8)
2012 /* Produces a ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value suitable for setting the register. */
2013 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET(value) (((value) << 8) & 0x00000f00)
2014 
2015 #ifndef __ASSEMBLY__
2016 /*
2017  * WARNING: The C register and register group struct declarations are provided for
2018  * convenience and illustrative purposes. They should, however, be used with
2019  * caution as the C language standard provides no guarantees about the alignment or
2020  * atomicity of device memory accesses. The recommended practice for writing
2021  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2022  * alt_write_word() functions.
2023  *
2024  * The struct declaration for register ALT_QSPI_DMAPER.
2025  */
2026 struct ALT_QSPI_DMAPER_s
2027 {
2028  uint32_t numsglreqbytes : 4; /* Number of Single Bytes */
2029  uint32_t : 4; /* *UNDEFINED* */
2030  uint32_t numburstreqbytes : 4; /* Number of Burst Bytes */
2031  uint32_t : 20; /* *UNDEFINED* */
2032 };
2033 
2034 /* The typedef declaration for register ALT_QSPI_DMAPER. */
2035 typedef volatile struct ALT_QSPI_DMAPER_s ALT_QSPI_DMAPER_t;
2036 #endif /* __ASSEMBLY__ */
2037 
2038 /* The byte offset of the ALT_QSPI_DMAPER register from the beginning of the component. */
2039 #define ALT_QSPI_DMAPER_OFST 0x20
2040 
2041 /*
2042  * Register : Remap Address Register - remapaddr
2043  *
2044  * This register is used to remap an incoming AHB address to a different address
2045  * used by the FLASH device.
2046  *
2047  * Register Layout
2048  *
2049  * Bits | Access | Reset | Description
2050  * :-------|:-------|:------|:---------------------
2051  * [31:0] | RW | 0x0 | Remap Address Offset
2052  *
2053  */
2054 /*
2055  * Field : Remap Address Offset - value
2056  *
2057  * This offset is added to the incoming AHB address to determine the address used
2058  * by the FLASH device.
2059  *
2060  * Field Access Macros:
2061  *
2062  */
2063 /* The Least Significant Bit (LSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */
2064 #define ALT_QSPI_REMAPADDR_VALUE_LSB 0
2065 /* The Most Significant Bit (MSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */
2066 #define ALT_QSPI_REMAPADDR_VALUE_MSB 31
2067 /* The width in bits of the ALT_QSPI_REMAPADDR_VALUE register field. */
2068 #define ALT_QSPI_REMAPADDR_VALUE_WIDTH 32
2069 /* The mask used to set the ALT_QSPI_REMAPADDR_VALUE register field value. */
2070 #define ALT_QSPI_REMAPADDR_VALUE_SET_MSK 0xffffffff
2071 /* The mask used to clear the ALT_QSPI_REMAPADDR_VALUE register field value. */
2072 #define ALT_QSPI_REMAPADDR_VALUE_CLR_MSK 0x00000000
2073 /* The reset value of the ALT_QSPI_REMAPADDR_VALUE register field. */
2074 #define ALT_QSPI_REMAPADDR_VALUE_RESET 0x0
2075 /* Extracts the ALT_QSPI_REMAPADDR_VALUE field value from a register. */
2076 #define ALT_QSPI_REMAPADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
2077 /* Produces a ALT_QSPI_REMAPADDR_VALUE register field value suitable for setting the register. */
2078 #define ALT_QSPI_REMAPADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff)
2079 
2080 #ifndef __ASSEMBLY__
2081 /*
2082  * WARNING: The C register and register group struct declarations are provided for
2083  * convenience and illustrative purposes. They should, however, be used with
2084  * caution as the C language standard provides no guarantees about the alignment or
2085  * atomicity of device memory accesses. The recommended practice for writing
2086  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2087  * alt_write_word() functions.
2088  *
2089  * The struct declaration for register ALT_QSPI_REMAPADDR.
2090  */
2091 struct ALT_QSPI_REMAPADDR_s
2092 {
2093  uint32_t value : 32; /* Remap Address Offset */
2094 };
2095 
2096 /* The typedef declaration for register ALT_QSPI_REMAPADDR. */
2097 typedef volatile struct ALT_QSPI_REMAPADDR_s ALT_QSPI_REMAPADDR_t;
2098 #endif /* __ASSEMBLY__ */
2099 
2100 /* The byte offset of the ALT_QSPI_REMAPADDR register from the beginning of the component. */
2101 #define ALT_QSPI_REMAPADDR_OFST 0x24
2102 
2103 /*
2104  * Register : Mode Bit Register - modebit
2105  *
2106  * Register Layout
2107  *
2108  * Bits | Access | Reset | Description
2109  * :-------|:-------|:------|:------------
2110  * [7:0] | RW | 0x0 | Mode
2111  * [31:8] | ??? | 0x0 | *UNDEFINED*
2112  *
2113  */
2114 /*
2115  * Field : Mode - mode
2116  *
2117  * These are the 8 mode bits that are sent to the device following the address
2118  * bytes if mode bit transmission has been enabled.
2119  *
2120  * Field Access Macros:
2121  *
2122  */
2123 /* The Least Significant Bit (LSB) position of the ALT_QSPI_MODBIT_MOD register field. */
2124 #define ALT_QSPI_MODBIT_MOD_LSB 0
2125 /* The Most Significant Bit (MSB) position of the ALT_QSPI_MODBIT_MOD register field. */
2126 #define ALT_QSPI_MODBIT_MOD_MSB 7
2127 /* The width in bits of the ALT_QSPI_MODBIT_MOD register field. */
2128 #define ALT_QSPI_MODBIT_MOD_WIDTH 8
2129 /* The mask used to set the ALT_QSPI_MODBIT_MOD register field value. */
2130 #define ALT_QSPI_MODBIT_MOD_SET_MSK 0x000000ff
2131 /* The mask used to clear the ALT_QSPI_MODBIT_MOD register field value. */
2132 #define ALT_QSPI_MODBIT_MOD_CLR_MSK 0xffffff00
2133 /* The reset value of the ALT_QSPI_MODBIT_MOD register field. */
2134 #define ALT_QSPI_MODBIT_MOD_RESET 0x0
2135 /* Extracts the ALT_QSPI_MODBIT_MOD field value from a register. */
2136 #define ALT_QSPI_MODBIT_MOD_GET(value) (((value) & 0x000000ff) >> 0)
2137 /* Produces a ALT_QSPI_MODBIT_MOD register field value suitable for setting the register. */
2138 #define ALT_QSPI_MODBIT_MOD_SET(value) (((value) << 0) & 0x000000ff)
2139 
2140 #ifndef __ASSEMBLY__
2141 /*
2142  * WARNING: The C register and register group struct declarations are provided for
2143  * convenience and illustrative purposes. They should, however, be used with
2144  * caution as the C language standard provides no guarantees about the alignment or
2145  * atomicity of device memory accesses. The recommended practice for writing
2146  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2147  * alt_write_word() functions.
2148  *
2149  * The struct declaration for register ALT_QSPI_MODBIT.
2150  */
2151 struct ALT_QSPI_MODBIT_s
2152 {
2153  uint32_t mode : 8; /* Mode */
2154  uint32_t : 24; /* *UNDEFINED* */
2155 };
2156 
2157 /* The typedef declaration for register ALT_QSPI_MODBIT. */
2158 typedef volatile struct ALT_QSPI_MODBIT_s ALT_QSPI_MODBIT_t;
2159 #endif /* __ASSEMBLY__ */
2160 
2161 /* The byte offset of the ALT_QSPI_MODBIT register from the beginning of the component. */
2162 #define ALT_QSPI_MODBIT_OFST 0x28
2163 
2164 /*
2165  * Register : SRAM Fill Register - sramfill
2166  *
2167  * Register Layout
2168  *
2169  * Bits | Access | Reset | Description
2170  * :--------|:-------|:------|:-------------------------------------------------------------------
2171  * [15:0] | R | 0x0 | SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS
2172  * [31:16] | R | 0x0 | SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS
2173  *
2174  */
2175 /*
2176  * Field : SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS - indrdpart
2177  *
2178  * Field Access Macros:
2179  *
2180  */
2181 /* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */
2182 #define ALT_QSPI_SRAMFILL_INDRDPART_LSB 0
2183 /* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */
2184 #define ALT_QSPI_SRAMFILL_INDRDPART_MSB 15
2185 /* The width in bits of the ALT_QSPI_SRAMFILL_INDRDPART register field. */
2186 #define ALT_QSPI_SRAMFILL_INDRDPART_WIDTH 16
2187 /* The mask used to set the ALT_QSPI_SRAMFILL_INDRDPART register field value. */
2188 #define ALT_QSPI_SRAMFILL_INDRDPART_SET_MSK 0x0000ffff
2189 /* The mask used to clear the ALT_QSPI_SRAMFILL_INDRDPART register field value. */
2190 #define ALT_QSPI_SRAMFILL_INDRDPART_CLR_MSK 0xffff0000
2191 /* The reset value of the ALT_QSPI_SRAMFILL_INDRDPART register field. */
2192 #define ALT_QSPI_SRAMFILL_INDRDPART_RESET 0x0
2193 /* Extracts the ALT_QSPI_SRAMFILL_INDRDPART field value from a register. */
2194 #define ALT_QSPI_SRAMFILL_INDRDPART_GET(value) (((value) & 0x0000ffff) >> 0)
2195 /* Produces a ALT_QSPI_SRAMFILL_INDRDPART register field value suitable for setting the register. */
2196 #define ALT_QSPI_SRAMFILL_INDRDPART_SET(value) (((value) << 0) & 0x0000ffff)
2197 
2198 /*
2199  * Field : SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS - indwrpart
2200  *
2201  * Field Access Macros:
2202  *
2203  */
2204 /* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */
2205 #define ALT_QSPI_SRAMFILL_INDWRPART_LSB 16
2206 /* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */
2207 #define ALT_QSPI_SRAMFILL_INDWRPART_MSB 31
2208 /* The width in bits of the ALT_QSPI_SRAMFILL_INDWRPART register field. */
2209 #define ALT_QSPI_SRAMFILL_INDWRPART_WIDTH 16
2210 /* The mask used to set the ALT_QSPI_SRAMFILL_INDWRPART register field value. */
2211 #define ALT_QSPI_SRAMFILL_INDWRPART_SET_MSK 0xffff0000
2212 /* The mask used to clear the ALT_QSPI_SRAMFILL_INDWRPART register field value. */
2213 #define ALT_QSPI_SRAMFILL_INDWRPART_CLR_MSK 0x0000ffff
2214 /* The reset value of the ALT_QSPI_SRAMFILL_INDWRPART register field. */
2215 #define ALT_QSPI_SRAMFILL_INDWRPART_RESET 0x0
2216 /* Extracts the ALT_QSPI_SRAMFILL_INDWRPART field value from a register. */
2217 #define ALT_QSPI_SRAMFILL_INDWRPART_GET(value) (((value) & 0xffff0000) >> 16)
2218 /* Produces a ALT_QSPI_SRAMFILL_INDWRPART register field value suitable for setting the register. */
2219 #define ALT_QSPI_SRAMFILL_INDWRPART_SET(value) (((value) << 16) & 0xffff0000)
2220 
2221 #ifndef __ASSEMBLY__
2222 /*
2223  * WARNING: The C register and register group struct declarations are provided for
2224  * convenience and illustrative purposes. They should, however, be used with
2225  * caution as the C language standard provides no guarantees about the alignment or
2226  * atomicity of device memory accesses. The recommended practice for writing
2227  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2228  * alt_write_word() functions.
2229  *
2230  * The struct declaration for register ALT_QSPI_SRAMFILL.
2231  */
2232 struct ALT_QSPI_SRAMFILL_s
2233 {
2234  const uint32_t indrdpart : 16; /* SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS */
2235  const uint32_t indwrpart : 16; /* SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS */
2236 };
2237 
2238 /* The typedef declaration for register ALT_QSPI_SRAMFILL. */
2239 typedef volatile struct ALT_QSPI_SRAMFILL_s ALT_QSPI_SRAMFILL_t;
2240 #endif /* __ASSEMBLY__ */
2241 
2242 /* The byte offset of the ALT_QSPI_SRAMFILL register from the beginning of the component. */
2243 #define ALT_QSPI_SRAMFILL_OFST 0x2c
2244 
2245 /*
2246  * Register : TX Threshold Register - txthresh
2247  *
2248  * Register Layout
2249  *
2250  * Bits | Access | Reset | Description
2251  * :-------|:-------|:------|:------------
2252  * [3:0] | RW | 0x1 | Level
2253  * [31:4] | ??? | 0x0 | *UNDEFINED*
2254  *
2255  */
2256 /*
2257  * Field : Level - level
2258  *
2259  * Defines the level at which the transmit FIFO not full interrupt is generated
2260  *
2261  * Field Access Macros:
2262  *
2263  */
2264 /* The Least Significant Bit (LSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */
2265 #define ALT_QSPI_TXTHRESH_LEVEL_LSB 0
2266 /* The Most Significant Bit (MSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */
2267 #define ALT_QSPI_TXTHRESH_LEVEL_MSB 3
2268 /* The width in bits of the ALT_QSPI_TXTHRESH_LEVEL register field. */
2269 #define ALT_QSPI_TXTHRESH_LEVEL_WIDTH 4
2270 /* The mask used to set the ALT_QSPI_TXTHRESH_LEVEL register field value. */
2271 #define ALT_QSPI_TXTHRESH_LEVEL_SET_MSK 0x0000000f
2272 /* The mask used to clear the ALT_QSPI_TXTHRESH_LEVEL register field value. */
2273 #define ALT_QSPI_TXTHRESH_LEVEL_CLR_MSK 0xfffffff0
2274 /* The reset value of the ALT_QSPI_TXTHRESH_LEVEL register field. */
2275 #define ALT_QSPI_TXTHRESH_LEVEL_RESET 0x1
2276 /* Extracts the ALT_QSPI_TXTHRESH_LEVEL field value from a register. */
2277 #define ALT_QSPI_TXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
2278 /* Produces a ALT_QSPI_TXTHRESH_LEVEL register field value suitable for setting the register. */
2279 #define ALT_QSPI_TXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
2280 
2281 #ifndef __ASSEMBLY__
2282 /*
2283  * WARNING: The C register and register group struct declarations are provided for
2284  * convenience and illustrative purposes. They should, however, be used with
2285  * caution as the C language standard provides no guarantees about the alignment or
2286  * atomicity of device memory accesses. The recommended practice for writing
2287  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2288  * alt_write_word() functions.
2289  *
2290  * The struct declaration for register ALT_QSPI_TXTHRESH.
2291  */
2292 struct ALT_QSPI_TXTHRESH_s
2293 {
2294  uint32_t level : 4; /* Level */
2295  uint32_t : 28; /* *UNDEFINED* */
2296 };
2297 
2298 /* The typedef declaration for register ALT_QSPI_TXTHRESH. */
2299 typedef volatile struct ALT_QSPI_TXTHRESH_s ALT_QSPI_TXTHRESH_t;
2300 #endif /* __ASSEMBLY__ */
2301 
2302 /* The byte offset of the ALT_QSPI_TXTHRESH register from the beginning of the component. */
2303 #define ALT_QSPI_TXTHRESH_OFST 0x30
2304 
2305 /*
2306  * Register : RX Threshold Register - rxthresh
2307  *
2308  * Device Instruction Register
2309  *
2310  * Register Layout
2311  *
2312  * Bits | Access | Reset | Description
2313  * :-------|:-------|:------|:------------
2314  * [3:0] | RW | 0x1 | Level
2315  * [31:4] | ??? | 0x0 | *UNDEFINED*
2316  *
2317  */
2318 /*
2319  * Field : Level - level
2320  *
2321  * Defines the level at which the receive FIFO not empty interrupt is generated
2322  *
2323  * Field Access Macros:
2324  *
2325  */
2326 /* The Least Significant Bit (LSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */
2327 #define ALT_QSPI_RXTHRESH_LEVEL_LSB 0
2328 /* The Most Significant Bit (MSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */
2329 #define ALT_QSPI_RXTHRESH_LEVEL_MSB 3
2330 /* The width in bits of the ALT_QSPI_RXTHRESH_LEVEL register field. */
2331 #define ALT_QSPI_RXTHRESH_LEVEL_WIDTH 4
2332 /* The mask used to set the ALT_QSPI_RXTHRESH_LEVEL register field value. */
2333 #define ALT_QSPI_RXTHRESH_LEVEL_SET_MSK 0x0000000f
2334 /* The mask used to clear the ALT_QSPI_RXTHRESH_LEVEL register field value. */
2335 #define ALT_QSPI_RXTHRESH_LEVEL_CLR_MSK 0xfffffff0
2336 /* The reset value of the ALT_QSPI_RXTHRESH_LEVEL register field. */
2337 #define ALT_QSPI_RXTHRESH_LEVEL_RESET 0x1
2338 /* Extracts the ALT_QSPI_RXTHRESH_LEVEL field value from a register. */
2339 #define ALT_QSPI_RXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
2340 /* Produces a ALT_QSPI_RXTHRESH_LEVEL register field value suitable for setting the register. */
2341 #define ALT_QSPI_RXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
2342 
2343 #ifndef __ASSEMBLY__
2344 /*
2345  * WARNING: The C register and register group struct declarations are provided for
2346  * convenience and illustrative purposes. They should, however, be used with
2347  * caution as the C language standard provides no guarantees about the alignment or
2348  * atomicity of device memory accesses. The recommended practice for writing
2349  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2350  * alt_write_word() functions.
2351  *
2352  * The struct declaration for register ALT_QSPI_RXTHRESH.
2353  */
2354 struct ALT_QSPI_RXTHRESH_s
2355 {
2356  uint32_t level : 4; /* Level */
2357  uint32_t : 28; /* *UNDEFINED* */
2358 };
2359 
2360 /* The typedef declaration for register ALT_QSPI_RXTHRESH. */
2361 typedef volatile struct ALT_QSPI_RXTHRESH_s ALT_QSPI_RXTHRESH_t;
2362 #endif /* __ASSEMBLY__ */
2363 
2364 /* The byte offset of the ALT_QSPI_RXTHRESH register from the beginning of the component. */
2365 #define ALT_QSPI_RXTHRESH_OFST 0x34
2366 
2367 /*
2368  * Register : Interrupt Status Register - irqstat
2369  *
2370  * The status fields in this register are set when the described event occurs and
2371  * the interrupt is enabled in the mask register. When any of these bit fields are
2372  * set, the interrupt output is asserted high. The fields are each cleared by
2373  * writing a 1 to the field. Note that bit fields 7 thru 11 are only valid when
2374  * legacy SPI mode is active.
2375  *
2376  * Register Layout
2377  *
2378  * Bits | Access | Reset | Description
2379  * :--------|:-------|:------|:------------------------------------
2380  * [0] | ??? | 0x0 | *UNDEFINED*
2381  * [1] | RW | 0x0 | Underflow Detected
2382  * [2] | RW | 0x0 | Indirect Operation Complete
2383  * [3] | RW | 0x0 | Indirect Read Reject
2384  * [4] | RW | 0x0 | Protected Area Write Attempt
2385  * [5] | RW | 0x0 | Illegal AHB Access Detected
2386  * [6] | RW | 0x0 | Transfer Watermark Reached
2387  * [7] | RW | 0x0 | Receive Overflow
2388  * [8] | RW | 0x1 | Transmit FIFO Compared to Threshold
2389  * [9] | RW | 0x0 | Transmit FIFO Full
2390  * [10] | RW | 0x0 | Receive FIFO Compared to Threshold
2391  * [11] | RW | 0x0 | Receive FIFO Full
2392  * [12] | RW | 0x0 | Indirect Read Partition overflow
2393  * [31:13] | ??? | 0x0 | *UNDEFINED*
2394  *
2395  */
2396 /*
2397  * Field : Underflow Detected - underflowdet
2398  *
2399  * An underflow is detected when an attempt to transfer data is made when the
2400  * transmit FIFO is empty. This may occur when the AHB write data is being supplied
2401  * too slowly to keep up with the requested write operation. This bit is reset only
2402  * by a system reset and cleared only when the register is read.
2403  *
2404  * Field Enumeration Values:
2405  *
2406  * Enum | Value | Description
2407  * :--------------------------------------------|:------|:-------------
2408  * ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW | 0x1 | Underflow
2409  * ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW | 0x0 | No Underflow
2410  *
2411  * Field Access Macros:
2412  *
2413  */
2414 /*
2415  * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET
2416  *
2417  * Underflow
2418  */
2419 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW 0x1
2420 /*
2421  * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET
2422  *
2423  * No Underflow
2424  */
2425 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW 0x0
2426 
2427 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */
2428 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_LSB 1
2429 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */
2430 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_MSB 1
2431 /* The width in bits of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */
2432 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_WIDTH 1
2433 /* The mask used to set the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */
2434 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET_MSK 0x00000002
2435 /* The mask used to clear the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */
2436 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_CLR_MSK 0xfffffffd
2437 /* The reset value of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */
2438 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_RESET 0x0
2439 /* Extracts the ALT_QSPI_IRQSTAT_UNDERFLOWDET field value from a register. */
2440 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)
2441 /* Produces a ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value suitable for setting the register. */
2442 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)
2443 
2444 /*
2445  * Field : Indirect Operation Complete - indopdone
2446  *
2447  * Controller has completed last triggered indirect operation
2448  *
2449  * Field Enumeration Values:
2450  *
2451  * Enum | Value | Description
2452  * :------------------------------------------|:------|:-----------------------------
2453  * ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP | 0x1 | Completed Indirect Operation
2454  * ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP | 0x0 | No Indirect Operation
2455  *
2456  * Field Access Macros:
2457  *
2458  */
2459 /*
2460  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE
2461  *
2462  * Completed Indirect Operation
2463  */
2464 #define ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP 0x1
2465 /*
2466  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE
2467  *
2468  * No Indirect Operation
2469  */
2470 #define ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP 0x0
2471 
2472 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */
2473 #define ALT_QSPI_IRQSTAT_INDOPDONE_LSB 2
2474 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */
2475 #define ALT_QSPI_IRQSTAT_INDOPDONE_MSB 2
2476 /* The width in bits of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */
2477 #define ALT_QSPI_IRQSTAT_INDOPDONE_WIDTH 1
2478 /* The mask used to set the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */
2479 #define ALT_QSPI_IRQSTAT_INDOPDONE_SET_MSK 0x00000004
2480 /* The mask used to clear the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */
2481 #define ALT_QSPI_IRQSTAT_INDOPDONE_CLR_MSK 0xfffffffb
2482 /* The reset value of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */
2483 #define ALT_QSPI_IRQSTAT_INDOPDONE_RESET 0x0
2484 /* Extracts the ALT_QSPI_IRQSTAT_INDOPDONE field value from a register. */
2485 #define ALT_QSPI_IRQSTAT_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)
2486 /* Produces a ALT_QSPI_IRQSTAT_INDOPDONE register field value suitable for setting the register. */
2487 #define ALT_QSPI_IRQSTAT_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)
2488 
2489 /*
2490  * Field : Indirect Read Reject - indrdreject
2491  *
2492  * Indirect operation was requested but could not be accepted. Two indirect
2493  * operations already in storage.
2494  *
2495  * Field Enumeration Values:
2496  *
2497  * Enum | Value | Description
2498  * :---------------------------------------------|:------|:-----------------------------
2499  * ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ | 0x1 | Indirect Operation Requested
2500  * ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ | 0x0 | No Indirect Operation
2501  *
2502  * Field Access Macros:
2503  *
2504  */
2505 /*
2506  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT
2507  *
2508  * Indirect Operation Requested
2509  */
2510 #define ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ 0x1
2511 /*
2512  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT
2513  *
2514  * No Indirect Operation
2515  */
2516 #define ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ 0x0
2517 
2518 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */
2519 #define ALT_QSPI_IRQSTAT_INDRDREJECT_LSB 3
2520 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */
2521 #define ALT_QSPI_IRQSTAT_INDRDREJECT_MSB 3
2522 /* The width in bits of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */
2523 #define ALT_QSPI_IRQSTAT_INDRDREJECT_WIDTH 1
2524 /* The mask used to set the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */
2525 #define ALT_QSPI_IRQSTAT_INDRDREJECT_SET_MSK 0x00000008
2526 /* The mask used to clear the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */
2527 #define ALT_QSPI_IRQSTAT_INDRDREJECT_CLR_MSK 0xfffffff7
2528 /* The reset value of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */
2529 #define ALT_QSPI_IRQSTAT_INDRDREJECT_RESET 0x0
2530 /* Extracts the ALT_QSPI_IRQSTAT_INDRDREJECT field value from a register. */
2531 #define ALT_QSPI_IRQSTAT_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)
2532 /* Produces a ALT_QSPI_IRQSTAT_INDRDREJECT register field value suitable for setting the register. */
2533 #define ALT_QSPI_IRQSTAT_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)
2534 
2535 /*
2536  * Field : Protected Area Write Attempt - protwrattempt
2537  *
2538  * Write to protected area was attempted and rejected.
2539  *
2540  * Field Enumeration Values:
2541  *
2542  * Enum | Value | Description
2543  * :------------------------------------------|:------|:--------------------------------
2544  * ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT | 0x1 | Write Attempt to protected area
2545  * ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT | 0x0 | No Write Attempt
2546  *
2547  * Field Access Macros:
2548  *
2549  */
2550 /*
2551  * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT
2552  *
2553  * Write Attempt to protected area
2554  */
2555 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT 0x1
2556 /*
2557  * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT
2558  *
2559  * No Write Attempt
2560  */
2561 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT 0x0
2562 
2563 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */
2564 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_LSB 4
2565 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */
2566 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_MSB 4
2567 /* The width in bits of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */
2568 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_WIDTH 1
2569 /* The mask used to set the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */
2570 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET_MSK 0x00000010
2571 /* The mask used to clear the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */
2572 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_CLR_MSK 0xffffffef
2573 /* The reset value of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */
2574 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_RESET 0x0
2575 /* Extracts the ALT_QSPI_IRQSTAT_PROTWRATTEMPT field value from a register. */
2576 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)
2577 /* Produces a ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value suitable for setting the register. */
2578 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)
2579 
2580 /*
2581  * Field : Illegal AHB Access Detected - illegalacc
2582  *
2583  * Illegal AHB access has been detected. AHB wrapping bursts and the use of
2584  * SPLIT/RETRY accesses will cause this error interrupt to trigger.
2585  *
2586  * Field Enumeration Values:
2587  *
2588  * Enum | Value | Description
2589  * :-------------------------------------------|:------|:-----------------------
2590  * ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB | 0x1 | Illegal AHB attempt
2591  * ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB | 0x0 | No Illegal AHB attempt
2592  *
2593  * Field Access Macros:
2594  *
2595  */
2596 /*
2597  * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC
2598  *
2599  * Illegal AHB attempt
2600  */
2601 #define ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB 0x1
2602 /*
2603  * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC
2604  *
2605  * No Illegal AHB attempt
2606  */
2607 #define ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB 0x0
2608 
2609 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */
2610 #define ALT_QSPI_IRQSTAT_ILLEGALACC_LSB 5
2611 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */
2612 #define ALT_QSPI_IRQSTAT_ILLEGALACC_MSB 5
2613 /* The width in bits of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */
2614 #define ALT_QSPI_IRQSTAT_ILLEGALACC_WIDTH 1
2615 /* The mask used to set the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */
2616 #define ALT_QSPI_IRQSTAT_ILLEGALACC_SET_MSK 0x00000020
2617 /* The mask used to clear the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */
2618 #define ALT_QSPI_IRQSTAT_ILLEGALACC_CLR_MSK 0xffffffdf
2619 /* The reset value of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */
2620 #define ALT_QSPI_IRQSTAT_ILLEGALACC_RESET 0x0
2621 /* Extracts the ALT_QSPI_IRQSTAT_ILLEGALACC field value from a register. */
2622 #define ALT_QSPI_IRQSTAT_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)
2623 /* Produces a ALT_QSPI_IRQSTAT_ILLEGALACC register field value suitable for setting the register. */
2624 #define ALT_QSPI_IRQSTAT_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)
2625 
2626 /*
2627  * Field : Transfer Watermark Reached - indxfrlvl
2628  *
2629  * Indirect Transfer Watermark Level Reached
2630  *
2631  * Field Enumeration Values:
2632  *
2633  * Enum | Value | Description
2634  * :----------------------------------------|:------|:-----------------------
2635  * ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL | 0x1 | Water level reached
2636  * ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL | 0x0 | No water level reached
2637  *
2638  * Field Access Macros:
2639  *
2640  */
2641 /*
2642  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL
2643  *
2644  * Water level reached
2645  */
2646 #define ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL 0x1
2647 /*
2648  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL
2649  *
2650  * No water level reached
2651  */
2652 #define ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL 0x0
2653 
2654 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */
2655 #define ALT_QSPI_IRQSTAT_INDXFRLVL_LSB 6
2656 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */
2657 #define ALT_QSPI_IRQSTAT_INDXFRLVL_MSB 6
2658 /* The width in bits of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */
2659 #define ALT_QSPI_IRQSTAT_INDXFRLVL_WIDTH 1
2660 /* The mask used to set the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */
2661 #define ALT_QSPI_IRQSTAT_INDXFRLVL_SET_MSK 0x00000040
2662 /* The mask used to clear the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */
2663 #define ALT_QSPI_IRQSTAT_INDXFRLVL_CLR_MSK 0xffffffbf
2664 /* The reset value of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */
2665 #define ALT_QSPI_IRQSTAT_INDXFRLVL_RESET 0x0
2666 /* Extracts the ALT_QSPI_IRQSTAT_INDXFRLVL field value from a register. */
2667 #define ALT_QSPI_IRQSTAT_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)
2668 /* Produces a ALT_QSPI_IRQSTAT_INDXFRLVL register field value suitable for setting the register. */
2669 #define ALT_QSPI_IRQSTAT_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)
2670 
2671 /*
2672  * Field : Receive Overflow - rxover
2673  *
2674  * This should only occur in Legacy SPI mode. Set if an attempt is made to push the
2675  * RX FIFO when it is full. This bit is reset only by a system reset and cleared
2676  * only when this register is read. If a new push to the RX FIFO occurs coincident
2677  * with a register read this flag will remain set. 0 : no overflow has been
2678  * detected. 1 : an overflow has occurred.
2679  *
2680  * Field Enumeration Values:
2681  *
2682  * Enum | Value | Description
2683  * :------------------------------------|:------|:--------------------
2684  * ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER | 0x1 | Receive Overflow
2685  * ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER | 0x0 | No Receive Overflow
2686  *
2687  * Field Access Macros:
2688  *
2689  */
2690 /*
2691  * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER
2692  *
2693  * Receive Overflow
2694  */
2695 #define ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER 0x1
2696 /*
2697  * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER
2698  *
2699  * No Receive Overflow
2700  */
2701 #define ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER 0x0
2702 
2703 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */
2704 #define ALT_QSPI_IRQSTAT_RXOVER_LSB 7
2705 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */
2706 #define ALT_QSPI_IRQSTAT_RXOVER_MSB 7
2707 /* The width in bits of the ALT_QSPI_IRQSTAT_RXOVER register field. */
2708 #define ALT_QSPI_IRQSTAT_RXOVER_WIDTH 1
2709 /* The mask used to set the ALT_QSPI_IRQSTAT_RXOVER register field value. */
2710 #define ALT_QSPI_IRQSTAT_RXOVER_SET_MSK 0x00000080
2711 /* The mask used to clear the ALT_QSPI_IRQSTAT_RXOVER register field value. */
2712 #define ALT_QSPI_IRQSTAT_RXOVER_CLR_MSK 0xffffff7f
2713 /* The reset value of the ALT_QSPI_IRQSTAT_RXOVER register field. */
2714 #define ALT_QSPI_IRQSTAT_RXOVER_RESET 0x0
2715 /* Extracts the ALT_QSPI_IRQSTAT_RXOVER field value from a register. */
2716 #define ALT_QSPI_IRQSTAT_RXOVER_GET(value) (((value) & 0x00000080) >> 7)
2717 /* Produces a ALT_QSPI_IRQSTAT_RXOVER register field value suitable for setting the register. */
2718 #define ALT_QSPI_IRQSTAT_RXOVER_SET(value) (((value) << 7) & 0x00000080)
2719 
2720 /*
2721  * Field : Transmit FIFO Compared to Threshold - txthreshcmp
2722  *
2723  * Indicates the number of entries in the transmit FIFO with respect to the
2724  * threshold specified in the TXTHRESH register. Only relevant in SPI legacy mode.
2725  *
2726  * Field Enumeration Values:
2727  *
2728  * Enum | Value | Description
2729  * :----------------------------------|:------|:-----------------------------
2730  * ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT | 0x0 | FIFO has > TXTHRESH entries
2731  * ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE | 0x1 | FIFO has <= TXTHRESH entries
2732  *
2733  * Field Access Macros:
2734  *
2735  */
2736 /*
2737  * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP
2738  *
2739  * FIFO has > TXTHRESH entries
2740  */
2741 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT 0x0
2742 /*
2743  * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP
2744  *
2745  * FIFO has <= TXTHRESH entries
2746  */
2747 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE 0x1
2748 
2749 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */
2750 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_LSB 8
2751 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */
2752 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_MSB 8
2753 /* The width in bits of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */
2754 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_WIDTH 1
2755 /* The mask used to set the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */
2756 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET_MSK 0x00000100
2757 /* The mask used to clear the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */
2758 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_CLR_MSK 0xfffffeff
2759 /* The reset value of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */
2760 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_RESET 0x1
2761 /* Extracts the ALT_QSPI_IRQSTAT_TXTHRESHCMP field value from a register. */
2762 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)
2763 /* Produces a ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value suitable for setting the register. */
2764 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)
2765 
2766 /*
2767  * Field : Transmit FIFO Full - txfull
2768  *
2769  * Indicates that the transmit FIFO is full or not. Only relevant in SPI legacy
2770  * mode.
2771  *
2772  * Field Enumeration Values:
2773  *
2774  * Enum | Value | Description
2775  * :----------------------------------|:------|:-----------------------
2776  * ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL | 0x0 | Transmit FIFO Not Full
2777  * ALT_QSPI_IRQSTAT_TXFULL_E_FULL | 0x1 | Transmit FIFO Full
2778  *
2779  * Field Access Macros:
2780  *
2781  */
2782 /*
2783  * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL
2784  *
2785  * Transmit FIFO Not Full
2786  */
2787 #define ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL 0x0
2788 /*
2789  * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL
2790  *
2791  * Transmit FIFO Full
2792  */
2793 #define ALT_QSPI_IRQSTAT_TXFULL_E_FULL 0x1
2794 
2795 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */
2796 #define ALT_QSPI_IRQSTAT_TXFULL_LSB 9
2797 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */
2798 #define ALT_QSPI_IRQSTAT_TXFULL_MSB 9
2799 /* The width in bits of the ALT_QSPI_IRQSTAT_TXFULL register field. */
2800 #define ALT_QSPI_IRQSTAT_TXFULL_WIDTH 1
2801 /* The mask used to set the ALT_QSPI_IRQSTAT_TXFULL register field value. */
2802 #define ALT_QSPI_IRQSTAT_TXFULL_SET_MSK 0x00000200
2803 /* The mask used to clear the ALT_QSPI_IRQSTAT_TXFULL register field value. */
2804 #define ALT_QSPI_IRQSTAT_TXFULL_CLR_MSK 0xfffffdff
2805 /* The reset value of the ALT_QSPI_IRQSTAT_TXFULL register field. */
2806 #define ALT_QSPI_IRQSTAT_TXFULL_RESET 0x0
2807 /* Extracts the ALT_QSPI_IRQSTAT_TXFULL field value from a register. */
2808 #define ALT_QSPI_IRQSTAT_TXFULL_GET(value) (((value) & 0x00000200) >> 9)
2809 /* Produces a ALT_QSPI_IRQSTAT_TXFULL register field value suitable for setting the register. */
2810 #define ALT_QSPI_IRQSTAT_TXFULL_SET(value) (((value) << 9) & 0x00000200)
2811 
2812 /*
2813  * Field : Receive FIFO Compared to Threshold - rxthreshcmp
2814  *
2815  * Indicates the number of entries in the receive FIFO with respect to the
2816  * threshold specified in the RXTHRESH register. Only relevant in SPI legacy mode.
2817  *
2818  * Field Enumeration Values:
2819  *
2820  * Enum | Value | Description
2821  * :----------------------------------|:------|:-----------------------------
2822  * ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE | 0x0 | FIFO has <= RXTHRESH entries
2823  * ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT | 0x1 | FIFO has > RXTHRESH entries
2824  *
2825  * Field Access Macros:
2826  *
2827  */
2828 /*
2829  * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP
2830  *
2831  * FIFO has <= RXTHRESH entries
2832  */
2833 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE 0x0
2834 /*
2835  * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP
2836  *
2837  * FIFO has > RXTHRESH entries
2838  */
2839 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT 0x1
2840 
2841 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */
2842 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_LSB 10
2843 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */
2844 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_MSB 10
2845 /* The width in bits of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */
2846 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_WIDTH 1
2847 /* The mask used to set the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */
2848 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET_MSK 0x00000400
2849 /* The mask used to clear the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */
2850 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_CLR_MSK 0xfffffbff
2851 /* The reset value of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */
2852 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_RESET 0x0
2853 /* Extracts the ALT_QSPI_IRQSTAT_RXTHRESHCMP field value from a register. */
2854 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)
2855 /* Produces a ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value suitable for setting the register. */
2856 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)
2857 
2858 /*
2859  * Field : Receive FIFO Full - rxfull
2860  *
2861  * Indicates that the receive FIFO is full or not. Only relevant in SPI legacy
2862  * mode.
2863  *
2864  * Field Enumeration Values:
2865  *
2866  * Enum | Value | Description
2867  * :----------------------------------|:------|:----------------------
2868  * ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL | 0x0 | Receive FIFO Not Full
2869  * ALT_QSPI_IRQSTAT_RXFULL_E_FULL | 0x1 | Receive FIFO Full
2870  *
2871  * Field Access Macros:
2872  *
2873  */
2874 /*
2875  * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL
2876  *
2877  * Receive FIFO Not Full
2878  */
2879 #define ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL 0x0
2880 /*
2881  * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL
2882  *
2883  * Receive FIFO Full
2884  */
2885 #define ALT_QSPI_IRQSTAT_RXFULL_E_FULL 0x1
2886 
2887 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */
2888 #define ALT_QSPI_IRQSTAT_RXFULL_LSB 11
2889 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */
2890 #define ALT_QSPI_IRQSTAT_RXFULL_MSB 11
2891 /* The width in bits of the ALT_QSPI_IRQSTAT_RXFULL register field. */
2892 #define ALT_QSPI_IRQSTAT_RXFULL_WIDTH 1
2893 /* The mask used to set the ALT_QSPI_IRQSTAT_RXFULL register field value. */
2894 #define ALT_QSPI_IRQSTAT_RXFULL_SET_MSK 0x00000800
2895 /* The mask used to clear the ALT_QSPI_IRQSTAT_RXFULL register field value. */
2896 #define ALT_QSPI_IRQSTAT_RXFULL_CLR_MSK 0xfffff7ff
2897 /* The reset value of the ALT_QSPI_IRQSTAT_RXFULL register field. */
2898 #define ALT_QSPI_IRQSTAT_RXFULL_RESET 0x0
2899 /* Extracts the ALT_QSPI_IRQSTAT_RXFULL field value from a register. */
2900 #define ALT_QSPI_IRQSTAT_RXFULL_GET(value) (((value) & 0x00000800) >> 11)
2901 /* Produces a ALT_QSPI_IRQSTAT_RXFULL register field value suitable for setting the register. */
2902 #define ALT_QSPI_IRQSTAT_RXFULL_SET(value) (((value) << 11) & 0x00000800)
2903 
2904 /*
2905  * Field : Indirect Read Partition overflow - indsramfull
2906  *
2907  * Indirect Read Partition of SRAM is full and unable to immediately complete
2908  * indirect operation
2909  *
2910  * Field Enumeration Values:
2911  *
2912  * Enum | Value | Description
2913  * :---------------------------------------------|:------|:-----------------
2914  * ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL | 0x1 | SRAM is full
2915  * ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL | 0x0 | SRAM is not full
2916  *
2917  * Field Access Macros:
2918  *
2919  */
2920 /*
2921  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL
2922  *
2923  * SRAM is full
2924  */
2925 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL 0x1
2926 /*
2927  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL
2928  *
2929  * SRAM is not full
2930  */
2931 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL 0x0
2932 
2933 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */
2934 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_LSB 12
2935 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */
2936 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_MSB 12
2937 /* The width in bits of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */
2938 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_WIDTH 1
2939 /* The mask used to set the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */
2940 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET_MSK 0x00001000
2941 /* The mask used to clear the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */
2942 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_CLR_MSK 0xffffefff
2943 /* The reset value of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */
2944 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_RESET 0x0
2945 /* Extracts the ALT_QSPI_IRQSTAT_INDSRAMFULL field value from a register. */
2946 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)
2947 /* Produces a ALT_QSPI_IRQSTAT_INDSRAMFULL register field value suitable for setting the register. */
2948 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)
2949 
2950 #ifndef __ASSEMBLY__
2951 /*
2952  * WARNING: The C register and register group struct declarations are provided for
2953  * convenience and illustrative purposes. They should, however, be used with
2954  * caution as the C language standard provides no guarantees about the alignment or
2955  * atomicity of device memory accesses. The recommended practice for writing
2956  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2957  * alt_write_word() functions.
2958  *
2959  * The struct declaration for register ALT_QSPI_IRQSTAT.
2960  */
2961 struct ALT_QSPI_IRQSTAT_s
2962 {
2963  uint32_t : 1; /* *UNDEFINED* */
2964  uint32_t underflowdet : 1; /* Underflow Detected */
2965  uint32_t indopdone : 1; /* Indirect Operation Complete */
2966  uint32_t indrdreject : 1; /* Indirect Read Reject */
2967  uint32_t protwrattempt : 1; /* Protected Area Write Attempt */
2968  uint32_t illegalacc : 1; /* Illegal AHB Access Detected */
2969  uint32_t indxfrlvl : 1; /* Transfer Watermark Reached */
2970  uint32_t rxover : 1; /* Receive Overflow */
2971  uint32_t txthreshcmp : 1; /* Transmit FIFO Compared to Threshold */
2972  uint32_t txfull : 1; /* Transmit FIFO Full */
2973  uint32_t rxthreshcmp : 1; /* Receive FIFO Compared to Threshold */
2974  uint32_t rxfull : 1; /* Receive FIFO Full */
2975  uint32_t indsramfull : 1; /* Indirect Read Partition overflow */
2976  uint32_t : 19; /* *UNDEFINED* */
2977 };
2978 
2979 /* The typedef declaration for register ALT_QSPI_IRQSTAT. */
2980 typedef volatile struct ALT_QSPI_IRQSTAT_s ALT_QSPI_IRQSTAT_t;
2981 #endif /* __ASSEMBLY__ */
2982 
2983 /* The byte offset of the ALT_QSPI_IRQSTAT register from the beginning of the component. */
2984 #define ALT_QSPI_IRQSTAT_OFST 0x40
2985 
2986 /*
2987  * Register : Interrupt Mask - irqmask
2988  *
2989  * If disabled, the interrupt for the corresponding interrupt status register bit
2990  * is disabled. If enabled, the interrupt for the corresponding interrupt status
2991  * register bit is enabled.
2992  *
2993  * Register Layout
2994  *
2995  * Bits | Access | Reset | Description
2996  * :--------|:-------|:------|:--------------------------------------
2997  * [0] | ??? | 0x0 | *UNDEFINED*
2998  * [1] | RW | 0x0 | Underflow Detected Mask
2999  * [2] | RW | 0x0 | Mask
3000  * [3] | RW | 0x0 | Indirect Read Reject Mask
3001  * [4] | RW | 0x0 | Protected Area Write Attempt Mask
3002  * [5] | RW | 0x0 | Illegal Access Detected Mask
3003  * [6] | RW | 0x0 | Transfer Watermark Breach Mask
3004  * [7] | RW | 0x0 | Receive Overflow Mask
3005  * [8] | RW | 0x0 | Transmit FIFO Threshold Compare Mask
3006  * [9] | RW | 0x0 | Transmit FIFO Full Mask
3007  * [10] | RW | 0x0 | Receive FIFO Threshold Compare Mask
3008  * [11] | RW | 0x0 | Receive FIFO full Mask
3009  * [12] | RW | 0x0 | Indirect Read Partition overflow mask
3010  * [31:13] | ??? | 0x0 | *UNDEFINED*
3011  *
3012  */
3013 /*
3014  * Field : Underflow Detected Mask - underflowdet
3015  *
3016  * Field Enumeration Values:
3017  *
3018  * Enum | Value | Description
3019  * :------------------------------------|:------|:-----------------------------
3020  * ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD | 0x0 | Disable Interrupt by Masking
3021  * ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END | 0x1 | Enable Interrupt
3022  *
3023  * Field Access Macros:
3024  *
3025  */
3026 /*
3027  * Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET
3028  *
3029  * Disable Interrupt by Masking
3030  */
3031 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD 0x0
3032 /*
3033  * Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET
3034  *
3035  * Enable Interrupt
3036  */
3037 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END 0x1
3038 
3039 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */
3040 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_LSB 1
3041 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */
3042 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_MSB 1
3043 /* The width in bits of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */
3044 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_WIDTH 1
3045 /* The mask used to set the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value. */
3046 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET_MSK 0x00000002
3047 /* The mask used to clear the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value. */
3048 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_CLR_MSK 0xfffffffd
3049 /* The reset value of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */
3050 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_RESET 0x0
3051 /* Extracts the ALT_QSPI_IRQMSK_UNDERFLOWDET field value from a register. */
3052 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)
3053 /* Produces a ALT_QSPI_IRQMSK_UNDERFLOWDET register field value suitable for setting the register. */
3054 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)
3055 
3056 /*
3057  * Field : Mask - indopdone
3058  *
3059  * Field Enumeration Values:
3060  *
3061  * Enum | Value | Description
3062  * :---------------------------------|:------|:-----------------------------
3063  * ALT_QSPI_IRQMSK_INDOPDONE_E_DISD | 0x0 | Disable Interrupt by Masking
3064  * ALT_QSPI_IRQMSK_INDOPDONE_E_END | 0x1 | Enable Interrupt
3065  *
3066  * Field Access Macros:
3067  *
3068  */
3069 /*
3070  * Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE
3071  *
3072  * Disable Interrupt by Masking
3073  */
3074 #define ALT_QSPI_IRQMSK_INDOPDONE_E_DISD 0x0
3075 /*
3076  * Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE
3077  *
3078  * Enable Interrupt
3079  */
3080 #define ALT_QSPI_IRQMSK_INDOPDONE_E_END 0x1
3081 
3082 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field. */
3083 #define ALT_QSPI_IRQMSK_INDOPDONE_LSB 2
3084 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field. */
3085 #define ALT_QSPI_IRQMSK_INDOPDONE_MSB 2
3086 /* The width in bits of the ALT_QSPI_IRQMSK_INDOPDONE register field. */
3087 #define ALT_QSPI_IRQMSK_INDOPDONE_WIDTH 1
3088 /* The mask used to set the ALT_QSPI_IRQMSK_INDOPDONE register field value. */
3089 #define ALT_QSPI_IRQMSK_INDOPDONE_SET_MSK 0x00000004
3090 /* The mask used to clear the ALT_QSPI_IRQMSK_INDOPDONE register field value. */
3091 #define ALT_QSPI_IRQMSK_INDOPDONE_CLR_MSK 0xfffffffb
3092 /* The reset value of the ALT_QSPI_IRQMSK_INDOPDONE register field. */
3093 #define ALT_QSPI_IRQMSK_INDOPDONE_RESET 0x0
3094 /* Extracts the ALT_QSPI_IRQMSK_INDOPDONE field value from a register. */
3095 #define ALT_QSPI_IRQMSK_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)
3096 /* Produces a ALT_QSPI_IRQMSK_INDOPDONE register field value suitable for setting the register. */
3097 #define ALT_QSPI_IRQMSK_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)
3098 
3099 /*
3100  * Field : Indirect Read Reject Mask - indrdreject
3101  *
3102  * Field Enumeration Values:
3103  *
3104  * Enum | Value | Description
3105  * :-----------------------------------|:------|:-----------------------------
3106  * ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD | 0x0 | Disable Interrupt by Masking
3107  * ALT_QSPI_IRQMSK_INDRDREJECT_E_END | 0x1 | Enable Interrupt
3108  *
3109  * Field Access Macros:
3110  *
3111  */
3112 /*
3113  * Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT
3114  *
3115  * Disable Interrupt by Masking
3116  */
3117 #define ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD 0x0
3118 /*
3119  * Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT
3120  *
3121  * Enable Interrupt
3122  */
3123 #define ALT_QSPI_IRQMSK_INDRDREJECT_E_END 0x1
3124 
3125 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */
3126 #define ALT_QSPI_IRQMSK_INDRDREJECT_LSB 3
3127 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */
3128 #define ALT_QSPI_IRQMSK_INDRDREJECT_MSB 3
3129 /* The width in bits of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */
3130 #define ALT_QSPI_IRQMSK_INDRDREJECT_WIDTH 1
3131 /* The mask used to set the ALT_QSPI_IRQMSK_INDRDREJECT register field value. */
3132 #define ALT_QSPI_IRQMSK_INDRDREJECT_SET_MSK 0x00000008
3133 /* The mask used to clear the ALT_QSPI_IRQMSK_INDRDREJECT register field value. */
3134 #define ALT_QSPI_IRQMSK_INDRDREJECT_CLR_MSK 0xfffffff7
3135 /* The reset value of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */
3136 #define ALT_QSPI_IRQMSK_INDRDREJECT_RESET 0x0
3137 /* Extracts the ALT_QSPI_IRQMSK_INDRDREJECT field value from a register. */
3138 #define ALT_QSPI_IRQMSK_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)
3139 /* Produces a ALT_QSPI_IRQMSK_INDRDREJECT register field value suitable for setting the register. */
3140 #define ALT_QSPI_IRQMSK_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)
3141 
3142 /*
3143  * Field : Protected Area Write Attempt Mask - protwrattempt
3144  *
3145  * Field Enumeration Values:
3146  *
3147  * Enum | Value | Description
3148  * :-------------------------------------|:------|:-----------------------------
3149  * ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD | 0x0 | Disable Interrupt by Masking
3150  * ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END | 0x1 | Enable Interrupt
3151  *
3152  * Field Access Macros:
3153  *
3154  */
3155 /*
3156  * Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT
3157  *
3158  * Disable Interrupt by Masking
3159  */
3160 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD 0x0
3161 /*
3162  * Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT
3163  *
3164  * Enable Interrupt
3165  */
3166 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END 0x1
3167 
3168 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */
3169 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_LSB 4
3170 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */
3171 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_MSB 4
3172 /* The width in bits of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */
3173 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_WIDTH 1
3174 /* The mask used to set the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value. */
3175 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET_MSK 0x00000010
3176 /* The mask used to clear the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value. */
3177 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_CLR_MSK 0xffffffef
3178 /* The reset value of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */
3179 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_RESET 0x0
3180 /* Extracts the ALT_QSPI_IRQMSK_PROTWRATTEMPT field value from a register. */
3181 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)
3182 /* Produces a ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value suitable for setting the register. */
3183 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)
3184 
3185 /*
3186  * Field : Illegal Access Detected Mask - illegalacc
3187  *
3188  * Field Enumeration Values:
3189  *
3190  * Enum | Value | Description
3191  * :----------------------------------|:------|:-----------------------------
3192  * ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD | 0x0 | Disable Interrupt by Masking
3193  * ALT_QSPI_IRQMSK_ILLEGALACC_E_END | 0x1 | Enable Interrupt
3194  *
3195  * Field Access Macros:
3196  *
3197  */
3198 /*
3199  * Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC
3200  *
3201  * Disable Interrupt by Masking
3202  */
3203 #define ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD 0x0
3204 /*
3205  * Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC
3206  *
3207  * Enable Interrupt
3208  */
3209 #define ALT_QSPI_IRQMSK_ILLEGALACC_E_END 0x1
3210 
3211 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */
3212 #define ALT_QSPI_IRQMSK_ILLEGALACC_LSB 5
3213 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */
3214 #define ALT_QSPI_IRQMSK_ILLEGALACC_MSB 5
3215 /* The width in bits of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */
3216 #define ALT_QSPI_IRQMSK_ILLEGALACC_WIDTH 1
3217 /* The mask used to set the ALT_QSPI_IRQMSK_ILLEGALACC register field value. */
3218 #define ALT_QSPI_IRQMSK_ILLEGALACC_SET_MSK 0x00000020
3219 /* The mask used to clear the ALT_QSPI_IRQMSK_ILLEGALACC register field value. */
3220 #define ALT_QSPI_IRQMSK_ILLEGALACC_CLR_MSK 0xffffffdf
3221 /* The reset value of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */
3222 #define ALT_QSPI_IRQMSK_ILLEGALACC_RESET 0x0
3223 /* Extracts the ALT_QSPI_IRQMSK_ILLEGALACC field value from a register. */
3224 #define ALT_QSPI_IRQMSK_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)
3225 /* Produces a ALT_QSPI_IRQMSK_ILLEGALACC register field value suitable for setting the register. */
3226 #define ALT_QSPI_IRQMSK_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)
3227 
3228 /*
3229  * Field : Transfer Watermark Breach Mask - indxfrlvl
3230  *
3231  * Field Enumeration Values:
3232  *
3233  * Enum | Value | Description
3234  * :---------------------------------|:------|:-----------------------------
3235  * ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD | 0x0 | Disable Interrupt by Masking
3236  * ALT_QSPI_IRQMSK_INDXFRLVL_E_END | 0x1 | Enable Interrupt
3237  *
3238  * Field Access Macros:
3239  *
3240  */
3241 /*
3242  * Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL
3243  *
3244  * Disable Interrupt by Masking
3245  */
3246 #define ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD 0x0
3247 /*
3248  * Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL
3249  *
3250  * Enable Interrupt
3251  */
3252 #define ALT_QSPI_IRQMSK_INDXFRLVL_E_END 0x1
3253 
3254 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */
3255 #define ALT_QSPI_IRQMSK_INDXFRLVL_LSB 6
3256 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */
3257 #define ALT_QSPI_IRQMSK_INDXFRLVL_MSB 6
3258 /* The width in bits of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */
3259 #define ALT_QSPI_IRQMSK_INDXFRLVL_WIDTH 1
3260 /* The mask used to set the ALT_QSPI_IRQMSK_INDXFRLVL register field value. */
3261 #define ALT_QSPI_IRQMSK_INDXFRLVL_SET_MSK 0x00000040
3262 /* The mask used to clear the ALT_QSPI_IRQMSK_INDXFRLVL register field value. */
3263 #define ALT_QSPI_IRQMSK_INDXFRLVL_CLR_MSK 0xffffffbf
3264 /* The reset value of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */
3265 #define ALT_QSPI_IRQMSK_INDXFRLVL_RESET 0x0
3266 /* Extracts the ALT_QSPI_IRQMSK_INDXFRLVL field value from a register. */
3267 #define ALT_QSPI_IRQMSK_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)
3268 /* Produces a ALT_QSPI_IRQMSK_INDXFRLVL register field value suitable for setting the register. */
3269 #define ALT_QSPI_IRQMSK_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)
3270 
3271 /*
3272  * Field : Receive Overflow Mask - rxover
3273  *
3274  * Field Enumeration Values:
3275  *
3276  * Enum | Value | Description
3277  * :------------------------------|:------|:-----------------------------
3278  * ALT_QSPI_IRQMSK_RXOVER_E_DISD | 0x0 | Disable Interrupt by Masking
3279  * ALT_QSPI_IRQMSK_RXOVER_E_END | 0x1 | Enable Interrupt
3280  *
3281  * Field Access Macros:
3282  *
3283  */
3284 /*
3285  * Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER
3286  *
3287  * Disable Interrupt by Masking
3288  */
3289 #define ALT_QSPI_IRQMSK_RXOVER_E_DISD 0x0
3290 /*
3291  * Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER
3292  *
3293  * Enable Interrupt
3294  */
3295 #define ALT_QSPI_IRQMSK_RXOVER_E_END 0x1
3296 
3297 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXOVER register field. */
3298 #define ALT_QSPI_IRQMSK_RXOVER_LSB 7
3299 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXOVER register field. */
3300 #define ALT_QSPI_IRQMSK_RXOVER_MSB 7
3301 /* The width in bits of the ALT_QSPI_IRQMSK_RXOVER register field. */
3302 #define ALT_QSPI_IRQMSK_RXOVER_WIDTH 1
3303 /* The mask used to set the ALT_QSPI_IRQMSK_RXOVER register field value. */
3304 #define ALT_QSPI_IRQMSK_RXOVER_SET_MSK 0x00000080
3305 /* The mask used to clear the ALT_QSPI_IRQMSK_RXOVER register field value. */
3306 #define ALT_QSPI_IRQMSK_RXOVER_CLR_MSK 0xffffff7f
3307 /* The reset value of the ALT_QSPI_IRQMSK_RXOVER register field. */
3308 #define ALT_QSPI_IRQMSK_RXOVER_RESET 0x0
3309 /* Extracts the ALT_QSPI_IRQMSK_RXOVER field value from a register. */
3310 #define ALT_QSPI_IRQMSK_RXOVER_GET(value) (((value) & 0x00000080) >> 7)
3311 /* Produces a ALT_QSPI_IRQMSK_RXOVER register field value suitable for setting the register. */
3312 #define ALT_QSPI_IRQMSK_RXOVER_SET(value) (((value) << 7) & 0x00000080)
3313 
3314 /*
3315  * Field : Transmit FIFO Threshold Compare Mask - txthreshcmp
3316  *
3317  * Field Enumeration Values:
3318  *
3319  * Enum | Value | Description
3320  * :-----------------------------------|:------|:-----------------------------
3321  * ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD | 0x0 | Disable Interrupt by Masking
3322  * ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END | 0x1 | Enable Interrupt
3323  *
3324  * Field Access Macros:
3325  *
3326  */
3327 /*
3328  * Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP
3329  *
3330  * Disable Interrupt by Masking
3331  */
3332 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD 0x0
3333 /*
3334  * Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP
3335  *
3336  * Enable Interrupt
3337  */
3338 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END 0x1
3339 
3340 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */
3341 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_LSB 8
3342 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */
3343 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_MSB 8
3344 /* The width in bits of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */
3345 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_WIDTH 1
3346 /* The mask used to set the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value. */
3347 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET_MSK 0x00000100
3348 /* The mask used to clear the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value. */
3349 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_CLR_MSK 0xfffffeff
3350 /* The reset value of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */
3351 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_RESET 0x0
3352 /* Extracts the ALT_QSPI_IRQMSK_TXTHRESHCMP field value from a register. */
3353 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)
3354 /* Produces a ALT_QSPI_IRQMSK_TXTHRESHCMP register field value suitable for setting the register. */
3355 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)
3356 
3357 /*
3358  * Field : Transmit FIFO Full Mask - txfull
3359  *
3360  * Field Enumeration Values:
3361  *
3362  * Enum | Value | Description
3363  * :------------------------------|:------|:-----------------------------
3364  * ALT_QSPI_IRQMSK_TXFULL_E_DISD | 0x0 | Disable Interrupt by Masking
3365  * ALT_QSPI_IRQMSK_TXFULL_E_END | 0x1 | Enable Interrupt
3366  *
3367  * Field Access Macros:
3368  *
3369  */
3370 /*
3371  * Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL
3372  *
3373  * Disable Interrupt by Masking
3374  */
3375 #define ALT_QSPI_IRQMSK_TXFULL_E_DISD 0x0
3376 /*
3377  * Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL
3378  *
3379  * Enable Interrupt
3380  */
3381 #define ALT_QSPI_IRQMSK_TXFULL_E_END 0x1
3382 
3383 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXFULL register field. */
3384 #define ALT_QSPI_IRQMSK_TXFULL_LSB 9
3385 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXFULL register field. */
3386 #define ALT_QSPI_IRQMSK_TXFULL_MSB 9
3387 /* The width in bits of the ALT_QSPI_IRQMSK_TXFULL register field. */
3388 #define ALT_QSPI_IRQMSK_TXFULL_WIDTH 1
3389 /* The mask used to set the ALT_QSPI_IRQMSK_TXFULL register field value. */
3390 #define ALT_QSPI_IRQMSK_TXFULL_SET_MSK 0x00000200
3391 /* The mask used to clear the ALT_QSPI_IRQMSK_TXFULL register field value. */
3392 #define ALT_QSPI_IRQMSK_TXFULL_CLR_MSK 0xfffffdff
3393 /* The reset value of the ALT_QSPI_IRQMSK_TXFULL register field. */
3394 #define ALT_QSPI_IRQMSK_TXFULL_RESET 0x0
3395 /* Extracts the ALT_QSPI_IRQMSK_TXFULL field value from a register. */
3396 #define ALT_QSPI_IRQMSK_TXFULL_GET(value) (((value) & 0x00000200) >> 9)
3397 /* Produces a ALT_QSPI_IRQMSK_TXFULL register field value suitable for setting the register. */
3398 #define ALT_QSPI_IRQMSK_TXFULL_SET(value) (((value) << 9) & 0x00000200)
3399 
3400 /*
3401  * Field : Receive FIFO Threshold Compare Mask - rxthreshcmp
3402  *
3403  * Field Enumeration Values:
3404  *
3405  * Enum | Value | Description
3406  * :-----------------------------------|:------|:-----------------------------
3407  * ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD | 0x0 | Disable Interrupt by Masking
3408  * ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END | 0x1 | Enable Interrupt
3409  *
3410  * Field Access Macros:
3411  *
3412  */
3413 /*
3414  * Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP
3415  *
3416  * Disable Interrupt by Masking
3417  */
3418 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD 0x0
3419 /*
3420  * Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP
3421  *
3422  * Enable Interrupt
3423  */
3424 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END 0x1
3425 
3426 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */
3427 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_LSB 10
3428 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */
3429 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_MSB 10
3430 /* The width in bits of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */
3431 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_WIDTH 1
3432 /* The mask used to set the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value. */
3433 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET_MSK 0x00000400
3434 /* The mask used to clear the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value. */
3435 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_CLR_MSK 0xfffffbff
3436 /* The reset value of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */
3437 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_RESET 0x0
3438 /* Extracts the ALT_QSPI_IRQMSK_RXTHRESHCMP field value from a register. */
3439 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)
3440 /* Produces a ALT_QSPI_IRQMSK_RXTHRESHCMP register field value suitable for setting the register. */
3441 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)
3442 
3443 /*
3444  * Field : Receive FIFO full Mask - rxfull
3445  *
3446  * Field Enumeration Values:
3447  *
3448  * Enum | Value | Description
3449  * :------------------------------|:------|:-----------------------------
3450  * ALT_QSPI_IRQMSK_RXFULL_E_DISD | 0x0 | Disable Interrupt by Masking
3451  * ALT_QSPI_IRQMSK_RXFULL_E_END | 0x1 | Enable Interrupt
3452  *
3453  * Field Access Macros:
3454  *
3455  */
3456 /*
3457  * Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL
3458  *
3459  * Disable Interrupt by Masking
3460  */
3461 #define ALT_QSPI_IRQMSK_RXFULL_E_DISD 0x0
3462 /*
3463  * Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL
3464  *
3465  * Enable Interrupt
3466  */
3467 #define ALT_QSPI_IRQMSK_RXFULL_E_END 0x1
3468 
3469 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXFULL register field. */
3470 #define ALT_QSPI_IRQMSK_RXFULL_LSB 11
3471 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXFULL register field. */
3472 #define ALT_QSPI_IRQMSK_RXFULL_MSB 11
3473 /* The width in bits of the ALT_QSPI_IRQMSK_RXFULL register field. */
3474 #define ALT_QSPI_IRQMSK_RXFULL_WIDTH 1
3475 /* The mask used to set the ALT_QSPI_IRQMSK_RXFULL register field value. */
3476 #define ALT_QSPI_IRQMSK_RXFULL_SET_MSK 0x00000800
3477 /* The mask used to clear the ALT_QSPI_IRQMSK_RXFULL register field value. */
3478 #define ALT_QSPI_IRQMSK_RXFULL_CLR_MSK 0xfffff7ff
3479 /* The reset value of the ALT_QSPI_IRQMSK_RXFULL register field. */
3480 #define ALT_QSPI_IRQMSK_RXFULL_RESET 0x0
3481 /* Extracts the ALT_QSPI_IRQMSK_RXFULL field value from a register. */
3482 #define ALT_QSPI_IRQMSK_RXFULL_GET(value) (((value) & 0x00000800) >> 11)
3483 /* Produces a ALT_QSPI_IRQMSK_RXFULL register field value suitable for setting the register. */
3484 #define ALT_QSPI_IRQMSK_RXFULL_SET(value) (((value) << 11) & 0x00000800)
3485 
3486 /*
3487  * Field : Indirect Read Partition overflow mask - indsramfull
3488  *
3489  * Field Enumeration Values:
3490  *
3491  * Enum | Value | Description
3492  * :-----------------------------------|:------|:-----------------------------
3493  * ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD | 0x0 | Disable Interrupt by Masking
3494  * ALT_QSPI_IRQMSK_INDSRAMFULL_E_END | 0x1 | Enable Interrupt
3495  *
3496  * Field Access Macros:
3497  *
3498  */
3499 /*
3500  * Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL
3501  *
3502  * Disable Interrupt by Masking
3503  */
3504 #define ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD 0x0
3505 /*
3506  * Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL
3507  *
3508  * Enable Interrupt
3509  */
3510 #define ALT_QSPI_IRQMSK_INDSRAMFULL_E_END 0x1
3511 
3512 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */
3513 #define ALT_QSPI_IRQMSK_INDSRAMFULL_LSB 12
3514 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */
3515 #define ALT_QSPI_IRQMSK_INDSRAMFULL_MSB 12
3516 /* The width in bits of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */
3517 #define ALT_QSPI_IRQMSK_INDSRAMFULL_WIDTH 1
3518 /* The mask used to set the ALT_QSPI_IRQMSK_INDSRAMFULL register field value. */
3519 #define ALT_QSPI_IRQMSK_INDSRAMFULL_SET_MSK 0x00001000
3520 /* The mask used to clear the ALT_QSPI_IRQMSK_INDSRAMFULL register field value. */
3521 #define ALT_QSPI_IRQMSK_INDSRAMFULL_CLR_MSK 0xffffefff
3522 /* The reset value of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */
3523 #define ALT_QSPI_IRQMSK_INDSRAMFULL_RESET 0x0
3524 /* Extracts the ALT_QSPI_IRQMSK_INDSRAMFULL field value from a register. */
3525 #define ALT_QSPI_IRQMSK_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)
3526 /* Produces a ALT_QSPI_IRQMSK_INDSRAMFULL register field value suitable for setting the register. */
3527 #define ALT_QSPI_IRQMSK_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)
3528 
3529 #ifndef __ASSEMBLY__
3530 /*
3531  * WARNING: The C register and register group struct declarations are provided for
3532  * convenience and illustrative purposes. They should, however, be used with
3533  * caution as the C language standard provides no guarantees about the alignment or
3534  * atomicity of device memory accesses. The recommended practice for writing
3535  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3536  * alt_write_word() functions.
3537  *
3538  * The struct declaration for register ALT_QSPI_IRQMSK.
3539  */
3540 struct ALT_QSPI_IRQMSK_s
3541 {
3542  uint32_t : 1; /* *UNDEFINED* */
3543  uint32_t underflowdet : 1; /* Underflow Detected Mask */
3544  uint32_t indopdone : 1; /* Mask */
3545  uint32_t indrdreject : 1; /* Indirect Read Reject Mask */
3546  uint32_t protwrattempt : 1; /* Protected Area Write Attempt Mask */
3547  uint32_t illegalacc : 1; /* Illegal Access Detected Mask */
3548  uint32_t indxfrlvl : 1; /* Transfer Watermark Breach Mask */
3549  uint32_t rxover : 1; /* Receive Overflow Mask */
3550  uint32_t txthreshcmp : 1; /* Transmit FIFO Threshold Compare Mask */
3551  uint32_t txfull : 1; /* Transmit FIFO Full Mask */
3552  uint32_t rxthreshcmp : 1; /* Receive FIFO Threshold Compare Mask */
3553  uint32_t rxfull : 1; /* Receive FIFO full Mask */
3554  uint32_t indsramfull : 1; /* Indirect Read Partition overflow mask */
3555  uint32_t : 19; /* *UNDEFINED* */
3556 };
3557 
3558 /* The typedef declaration for register ALT_QSPI_IRQMSK. */
3559 typedef volatile struct ALT_QSPI_IRQMSK_s ALT_QSPI_IRQMSK_t;
3560 #endif /* __ASSEMBLY__ */
3561 
3562 /* The byte offset of the ALT_QSPI_IRQMSK register from the beginning of the component. */
3563 #define ALT_QSPI_IRQMSK_OFST 0x44
3564 
3565 /*
3566  * Register : Lower Write Protection Register - lowwrprot
3567  *
3568  * Register Layout
3569  *
3570  * Bits | Access | Reset | Description
3571  * :-------|:-------|:------|:-------------
3572  * [31:0] | RW | 0x0 | Block Number
3573  *
3574  */
3575 /*
3576  * Field : Block Number - subsector
3577  *
3578  * The block number that defines the lower block in the range of blocks that is to
3579  * be locked from writing. The definition of a block in terms of number of bytes is
3580  * programmable via the Device Size Configuration register.
3581  *
3582  * Field Access Macros:
3583  *
3584  */
3585 /* The Least Significant Bit (LSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */
3586 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_LSB 0
3587 /* The Most Significant Bit (MSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */
3588 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_MSB 31
3589 /* The width in bits of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */
3590 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_WIDTH 32
3591 /* The mask used to set the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */
3592 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET_MSK 0xffffffff
3593 /* The mask used to clear the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */
3594 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_CLR_MSK 0x00000000
3595 /* The reset value of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */
3596 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_RESET 0x0
3597 /* Extracts the ALT_QSPI_LOWWRPROT_SUBSECTOR field value from a register. */
3598 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)
3599 /* Produces a ALT_QSPI_LOWWRPROT_SUBSECTOR register field value suitable for setting the register. */
3600 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)
3601 
3602 #ifndef __ASSEMBLY__
3603 /*
3604  * WARNING: The C register and register group struct declarations are provided for
3605  * convenience and illustrative purposes. They should, however, be used with
3606  * caution as the C language standard provides no guarantees about the alignment or
3607  * atomicity of device memory accesses. The recommended practice for writing
3608  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3609  * alt_write_word() functions.
3610  *
3611  * The struct declaration for register ALT_QSPI_LOWWRPROT.
3612  */
3613 struct ALT_QSPI_LOWWRPROT_s
3614 {
3615  uint32_t subsector : 32; /* Block Number */
3616 };
3617 
3618 /* The typedef declaration for register ALT_QSPI_LOWWRPROT. */
3619 typedef volatile struct ALT_QSPI_LOWWRPROT_s ALT_QSPI_LOWWRPROT_t;
3620 #endif /* __ASSEMBLY__ */
3621 
3622 /* The byte offset of the ALT_QSPI_LOWWRPROT register from the beginning of the component. */
3623 #define ALT_QSPI_LOWWRPROT_OFST 0x50
3624 
3625 /*
3626  * Register : Upper Write Protection Register - uppwrprot
3627  *
3628  * Register Layout
3629  *
3630  * Bits | Access | Reset | Description
3631  * :-------|:-------|:------|:-------------
3632  * [31:0] | RW | 0x0 | Block Number
3633  *
3634  */
3635 /*
3636  * Field : Block Number - subsector
3637  *
3638  * The block number that defines the upper block in the range of blocks that is to
3639  * be locked from writing. The definition of a block in terms of number of bytes is
3640  * programmable via the Device Size Configuration register.
3641  *
3642  * Field Access Macros:
3643  *
3644  */
3645 /* The Least Significant Bit (LSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */
3646 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_LSB 0
3647 /* The Most Significant Bit (MSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */
3648 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_MSB 31
3649 /* The width in bits of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */
3650 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_WIDTH 32
3651 /* The mask used to set the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */
3652 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET_MSK 0xffffffff
3653 /* The mask used to clear the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */
3654 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_CLR_MSK 0x00000000
3655 /* The reset value of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */
3656 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_RESET 0x0
3657 /* Extracts the ALT_QSPI_UPPWRPROT_SUBSECTOR field value from a register. */
3658 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)
3659 /* Produces a ALT_QSPI_UPPWRPROT_SUBSECTOR register field value suitable for setting the register. */
3660 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)
3661 
3662 #ifndef __ASSEMBLY__
3663 /*
3664  * WARNING: The C register and register group struct declarations are provided for
3665  * convenience and illustrative purposes. They should, however, be used with
3666  * caution as the C language standard provides no guarantees about the alignment or
3667  * atomicity of device memory accesses. The recommended practice for writing
3668  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3669  * alt_write_word() functions.
3670  *
3671  * The struct declaration for register ALT_QSPI_UPPWRPROT.
3672  */
3673 struct ALT_QSPI_UPPWRPROT_s
3674 {
3675  uint32_t subsector : 32; /* Block Number */
3676 };
3677 
3678 /* The typedef declaration for register ALT_QSPI_UPPWRPROT. */
3679 typedef volatile struct ALT_QSPI_UPPWRPROT_s ALT_QSPI_UPPWRPROT_t;
3680 #endif /* __ASSEMBLY__ */
3681 
3682 /* The byte offset of the ALT_QSPI_UPPWRPROT register from the beginning of the component. */
3683 #define ALT_QSPI_UPPWRPROT_OFST 0x54
3684 
3685 /*
3686  * Register : Write Protection Register - wrprot
3687  *
3688  * Register Layout
3689  *
3690  * Bits | Access | Reset | Description
3691  * :-------|:-------|:------|:-------------------------------
3692  * [0] | RW | 0x0 | Write Protection Inversion Bit
3693  * [1] | RW | 0x0 | Write Protection Enable Bit
3694  * [31:2] | ??? | 0x0 | *UNDEFINED*
3695  *
3696  */
3697 /*
3698  * Field : Write Protection Inversion Bit - inv
3699  *
3700  * When enabled, the protection region defined in the lower and upper write
3701  * protection registers is inverted meaning it is the region that the system is
3702  * permitted to write to. When disabled, the protection region defined in the lower
3703  * and upper write protection registers is the region that the system is not
3704  * permitted to write to.
3705  *
3706  * Field Enumeration Values:
3707  *
3708  * Enum | Value | Description
3709  * :--------------------------|:------|:-------------------------
3710  * ALT_QSPI_WRPROT_INV_E_EN | 0x1 | Write Region allowed
3711  * ALT_QSPI_WRPROT_INV_E_DIS | 0x0 | Write Region not allowed
3712  *
3713  * Field Access Macros:
3714  *
3715  */
3716 /*
3717  * Enumerated value for register field ALT_QSPI_WRPROT_INV
3718  *
3719  * Write Region allowed
3720  */
3721 #define ALT_QSPI_WRPROT_INV_E_EN 0x1
3722 /*
3723  * Enumerated value for register field ALT_QSPI_WRPROT_INV
3724  *
3725  * Write Region not allowed
3726  */
3727 #define ALT_QSPI_WRPROT_INV_E_DIS 0x0
3728 
3729 /* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_INV register field. */
3730 #define ALT_QSPI_WRPROT_INV_LSB 0
3731 /* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_INV register field. */
3732 #define ALT_QSPI_WRPROT_INV_MSB 0
3733 /* The width in bits of the ALT_QSPI_WRPROT_INV register field. */
3734 #define ALT_QSPI_WRPROT_INV_WIDTH 1
3735 /* The mask used to set the ALT_QSPI_WRPROT_INV register field value. */
3736 #define ALT_QSPI_WRPROT_INV_SET_MSK 0x00000001
3737 /* The mask used to clear the ALT_QSPI_WRPROT_INV register field value. */
3738 #define ALT_QSPI_WRPROT_INV_CLR_MSK 0xfffffffe
3739 /* The reset value of the ALT_QSPI_WRPROT_INV register field. */
3740 #define ALT_QSPI_WRPROT_INV_RESET 0x0
3741 /* Extracts the ALT_QSPI_WRPROT_INV field value from a register. */
3742 #define ALT_QSPI_WRPROT_INV_GET(value) (((value) & 0x00000001) >> 0)
3743 /* Produces a ALT_QSPI_WRPROT_INV register field value suitable for setting the register. */
3744 #define ALT_QSPI_WRPROT_INV_SET(value) (((value) << 0) & 0x00000001)
3745 
3746 /*
3747  * Field : Write Protection Enable Bit - en
3748  *
3749  * When enabled, any AHB write access with an address within the protection region
3750  * defined in the lower and upper write protection registers is rejected. An AHB
3751  * error response is generated and an interrupt source triggered. When disabled,
3752  * the protection region is disabled.
3753  *
3754  * Field Enumeration Values:
3755  *
3756  * Enum | Value | Description
3757  * :-------------------------|:------|:---------------------------
3758  * ALT_QSPI_WRPROT_EN_E_EN | 0x1 | AHB Write Access rejected
3759  * ALT_QSPI_WRPROT_EN_E_DIS | 0x0 | Protection Region Disabled
3760  *
3761  * Field Access Macros:
3762  *
3763  */
3764 /*
3765  * Enumerated value for register field ALT_QSPI_WRPROT_EN
3766  *
3767  * AHB Write Access rejected
3768  */
3769 #define ALT_QSPI_WRPROT_EN_E_EN 0x1
3770 /*
3771  * Enumerated value for register field ALT_QSPI_WRPROT_EN
3772  *
3773  * Protection Region Disabled
3774  */
3775 #define ALT_QSPI_WRPROT_EN_E_DIS 0x0
3776 
3777 /* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_EN register field. */
3778 #define ALT_QSPI_WRPROT_EN_LSB 1
3779 /* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_EN register field. */
3780 #define ALT_QSPI_WRPROT_EN_MSB 1
3781 /* The width in bits of the ALT_QSPI_WRPROT_EN register field. */
3782 #define ALT_QSPI_WRPROT_EN_WIDTH 1
3783 /* The mask used to set the ALT_QSPI_WRPROT_EN register field value. */
3784 #define ALT_QSPI_WRPROT_EN_SET_MSK 0x00000002
3785 /* The mask used to clear the ALT_QSPI_WRPROT_EN register field value. */
3786 #define ALT_QSPI_WRPROT_EN_CLR_MSK 0xfffffffd
3787 /* The reset value of the ALT_QSPI_WRPROT_EN register field. */
3788 #define ALT_QSPI_WRPROT_EN_RESET 0x0
3789 /* Extracts the ALT_QSPI_WRPROT_EN field value from a register. */
3790 #define ALT_QSPI_WRPROT_EN_GET(value) (((value) & 0x00000002) >> 1)
3791 /* Produces a ALT_QSPI_WRPROT_EN register field value suitable for setting the register. */
3792 #define ALT_QSPI_WRPROT_EN_SET(value) (((value) << 1) & 0x00000002)
3793 
3794 #ifndef __ASSEMBLY__
3795 /*
3796  * WARNING: The C register and register group struct declarations are provided for
3797  * convenience and illustrative purposes. They should, however, be used with
3798  * caution as the C language standard provides no guarantees about the alignment or
3799  * atomicity of device memory accesses. The recommended practice for writing
3800  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3801  * alt_write_word() functions.
3802  *
3803  * The struct declaration for register ALT_QSPI_WRPROT.
3804  */
3805 struct ALT_QSPI_WRPROT_s
3806 {
3807  uint32_t inv : 1; /* Write Protection Inversion Bit */
3808  uint32_t en : 1; /* Write Protection Enable Bit */
3809  uint32_t : 30; /* *UNDEFINED* */
3810 };
3811 
3812 /* The typedef declaration for register ALT_QSPI_WRPROT. */
3813 typedef volatile struct ALT_QSPI_WRPROT_s ALT_QSPI_WRPROT_t;
3814 #endif /* __ASSEMBLY__ */
3815 
3816 /* The byte offset of the ALT_QSPI_WRPROT register from the beginning of the component. */
3817 #define ALT_QSPI_WRPROT_OFST 0x58
3818 
3819 /*
3820  * Register : Indirect Read Transfer Register - indrd
3821  *
3822  * Register Layout
3823  *
3824  * Bits | Access | Reset | Description
3825  * :-------|:-------|:--------|:--------------------------------
3826  * [0] | RW | 0x0 | Start Indirect Read
3827  * [1] | RW | 0x0 | Cancel Indirect Read
3828  * [2] | R | Unknown | Indirect Read Status
3829  * [3] | RW | Unknown | SRAM Full
3830  * [4] | R | Unknown | Queued Indirect Read Operations
3831  * [5] | RW | Unknown | Indirect Completion Status
3832  * [7:6] | R | Unknown | Completed Indirect Operations
3833  * [31:8] | ??? | 0x0 | *UNDEFINED*
3834  *
3835  */
3836 /*
3837  * Field : Start Indirect Read - start
3838  *
3839  * When this bit is enabled, it will trigger an indirect read operation. The
3840  * assumption is that the indirect start address and the indirect number of bytes
3841  * register is setup before triggering the indirect read operation.
3842  *
3843  * Field Enumeration Values:
3844  *
3845  * Enum | Value | Description
3846  * :----------------------------|:------|:----------------------
3847  * ALT_QSPI_INDRD_START_E_END | 0x1 | Trigger Indirect Read
3848  * ALT_QSPI_INDRD_START_E_DISD | 0x0 | No Indirect Read
3849  *
3850  * Field Access Macros:
3851  *
3852  */
3853 /*
3854  * Enumerated value for register field ALT_QSPI_INDRD_START
3855  *
3856  * Trigger Indirect Read
3857  */
3858 #define ALT_QSPI_INDRD_START_E_END 0x1
3859 /*
3860  * Enumerated value for register field ALT_QSPI_INDRD_START
3861  *
3862  * No Indirect Read
3863  */
3864 #define ALT_QSPI_INDRD_START_E_DISD 0x0
3865 
3866 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_START register field. */
3867 #define ALT_QSPI_INDRD_START_LSB 0
3868 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_START register field. */
3869 #define ALT_QSPI_INDRD_START_MSB 0
3870 /* The width in bits of the ALT_QSPI_INDRD_START register field. */
3871 #define ALT_QSPI_INDRD_START_WIDTH 1
3872 /* The mask used to set the ALT_QSPI_INDRD_START register field value. */
3873 #define ALT_QSPI_INDRD_START_SET_MSK 0x00000001
3874 /* The mask used to clear the ALT_QSPI_INDRD_START register field value. */
3875 #define ALT_QSPI_INDRD_START_CLR_MSK 0xfffffffe
3876 /* The reset value of the ALT_QSPI_INDRD_START register field. */
3877 #define ALT_QSPI_INDRD_START_RESET 0x0
3878 /* Extracts the ALT_QSPI_INDRD_START field value from a register. */
3879 #define ALT_QSPI_INDRD_START_GET(value) (((value) & 0x00000001) >> 0)
3880 /* Produces a ALT_QSPI_INDRD_START register field value suitable for setting the register. */
3881 #define ALT_QSPI_INDRD_START_SET(value) (((value) << 0) & 0x00000001)
3882 
3883 /*
3884  * Field : Cancel Indirect Read - cancel
3885  *
3886  * This bit will cancel all ongoing indirect read operations.
3887  *
3888  * Field Enumeration Values:
3889  *
3890  * Enum | Value | Description
3891  * :---------------------------------|:------|:----------------------------
3892  * ALT_QSPI_INDRD_CANCEL_E_CANCEL | 0x1 | Cancel Indirect Read
3893  * ALT_QSPI_INDRD_CANCEL_E_NOACTION | 0x0 | Do Not Cancel Indirect Read
3894  *
3895  * Field Access Macros:
3896  *
3897  */
3898 /*
3899  * Enumerated value for register field ALT_QSPI_INDRD_CANCEL
3900  *
3901  * Cancel Indirect Read
3902  */
3903 #define ALT_QSPI_INDRD_CANCEL_E_CANCEL 0x1
3904 /*
3905  * Enumerated value for register field ALT_QSPI_INDRD_CANCEL
3906  *
3907  * Do Not Cancel Indirect Read
3908  */
3909 #define ALT_QSPI_INDRD_CANCEL_E_NOACTION 0x0
3910 
3911 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_CANCEL register field. */
3912 #define ALT_QSPI_INDRD_CANCEL_LSB 1
3913 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_CANCEL register field. */
3914 #define ALT_QSPI_INDRD_CANCEL_MSB 1
3915 /* The width in bits of the ALT_QSPI_INDRD_CANCEL register field. */
3916 #define ALT_QSPI_INDRD_CANCEL_WIDTH 1
3917 /* The mask used to set the ALT_QSPI_INDRD_CANCEL register field value. */
3918 #define ALT_QSPI_INDRD_CANCEL_SET_MSK 0x00000002
3919 /* The mask used to clear the ALT_QSPI_INDRD_CANCEL register field value. */
3920 #define ALT_QSPI_INDRD_CANCEL_CLR_MSK 0xfffffffd
3921 /* The reset value of the ALT_QSPI_INDRD_CANCEL register field. */
3922 #define ALT_QSPI_INDRD_CANCEL_RESET 0x0
3923 /* Extracts the ALT_QSPI_INDRD_CANCEL field value from a register. */
3924 #define ALT_QSPI_INDRD_CANCEL_GET(value) (((value) & 0x00000002) >> 1)
3925 /* Produces a ALT_QSPI_INDRD_CANCEL register field value suitable for setting the register. */
3926 #define ALT_QSPI_INDRD_CANCEL_SET(value) (((value) << 1) & 0x00000002)
3927 
3928 /*
3929  * Field : Indirect Read Status - rd_status
3930  *
3931  * Indirect read operation in progress (status)
3932  *
3933  * Field Enumeration Values:
3934  *
3935  * Enum | Value | Description
3936  * :----------------------------------|:------|:------------------------------
3937  * ALT_QSPI_INDRD_RD_STAT_E_RDOP | 0x1 | Read Operation in progress
3938  * ALT_QSPI_INDRD_RD_STAT_E_NOACTION | 0x0 | No read operation in progress
3939  *
3940  * Field Access Macros:
3941  *
3942  */
3943 /*
3944  * Enumerated value for register field ALT_QSPI_INDRD_RD_STAT
3945  *
3946  * Read Operation in progress
3947  */
3948 #define ALT_QSPI_INDRD_RD_STAT_E_RDOP 0x1
3949 /*
3950  * Enumerated value for register field ALT_QSPI_INDRD_RD_STAT
3951  *
3952  * No read operation in progress
3953  */
3954 #define ALT_QSPI_INDRD_RD_STAT_E_NOACTION 0x0
3955 
3956 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_STAT register field. */
3957 #define ALT_QSPI_INDRD_RD_STAT_LSB 2
3958 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_STAT register field. */
3959 #define ALT_QSPI_INDRD_RD_STAT_MSB 2
3960 /* The width in bits of the ALT_QSPI_INDRD_RD_STAT register field. */
3961 #define ALT_QSPI_INDRD_RD_STAT_WIDTH 1
3962 /* The mask used to set the ALT_QSPI_INDRD_RD_STAT register field value. */
3963 #define ALT_QSPI_INDRD_RD_STAT_SET_MSK 0x00000004
3964 /* The mask used to clear the ALT_QSPI_INDRD_RD_STAT register field value. */
3965 #define ALT_QSPI_INDRD_RD_STAT_CLR_MSK 0xfffffffb
3966 /* The reset value of the ALT_QSPI_INDRD_RD_STAT register field is UNKNOWN. */
3967 #define ALT_QSPI_INDRD_RD_STAT_RESET 0x0
3968 /* Extracts the ALT_QSPI_INDRD_RD_STAT field value from a register. */
3969 #define ALT_QSPI_INDRD_RD_STAT_GET(value) (((value) & 0x00000004) >> 2)
3970 /* Produces a ALT_QSPI_INDRD_RD_STAT register field value suitable for setting the register. */
3971 #define ALT_QSPI_INDRD_RD_STAT_SET(value) (((value) << 2) & 0x00000004)
3972 
3973 /*
3974  * Field : SRAM Full - sram_full
3975  *
3976  * SRAM full and unable to immediately complete an indirect operation. Write a 1 to
3977  * this field to clear it. ; indirect operation (status)
3978  *
3979  * Field Enumeration Values:
3980  *
3981  * Enum | Value | Description
3982  * :------------------------------------|:------|:-----------------------------------
3983  * ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL | 0x1 | Sram Full- Cant complete operation
3984  * ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION | 0x0 | SRram Not Full
3985  *
3986  * Field Access Macros:
3987  *
3988  */
3989 /*
3990  * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL
3991  *
3992  * Sram Full- Cant complete operation
3993  */
3994 #define ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL 0x1
3995 /*
3996  * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL
3997  *
3998  * SRram Not Full
3999  */
4000 #define ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION 0x0
4001 
4002 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */
4003 #define ALT_QSPI_INDRD_SRAM_FULL_LSB 3
4004 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */
4005 #define ALT_QSPI_INDRD_SRAM_FULL_MSB 3
4006 /* The width in bits of the ALT_QSPI_INDRD_SRAM_FULL register field. */
4007 #define ALT_QSPI_INDRD_SRAM_FULL_WIDTH 1
4008 /* The mask used to set the ALT_QSPI_INDRD_SRAM_FULL register field value. */
4009 #define ALT_QSPI_INDRD_SRAM_FULL_SET_MSK 0x00000008
4010 /* The mask used to clear the ALT_QSPI_INDRD_SRAM_FULL register field value. */
4011 #define ALT_QSPI_INDRD_SRAM_FULL_CLR_MSK 0xfffffff7
4012 /* The reset value of the ALT_QSPI_INDRD_SRAM_FULL register field is UNKNOWN. */
4013 #define ALT_QSPI_INDRD_SRAM_FULL_RESET 0x0
4014 /* Extracts the ALT_QSPI_INDRD_SRAM_FULL field value from a register. */
4015 #define ALT_QSPI_INDRD_SRAM_FULL_GET(value) (((value) & 0x00000008) >> 3)
4016 /* Produces a ALT_QSPI_INDRD_SRAM_FULL register field value suitable for setting the register. */
4017 #define ALT_QSPI_INDRD_SRAM_FULL_SET(value) (((value) << 3) & 0x00000008)
4018 
4019 /*
4020  * Field : Queued Indirect Read Operations - rd_queued
4021  *
4022  * Two indirect read operations have been queued
4023  *
4024  * Field Enumeration Values:
4025  *
4026  * Enum | Value | Description
4027  * :----------------------------------------|:------|:---------------------
4028  * ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD | 0x1 | Queued Indirect Read
4029  * ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION | 0x0 | No Queued Read
4030  *
4031  * Field Access Macros:
4032  *
4033  */
4034 /*
4035  * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED
4036  *
4037  * Queued Indirect Read
4038  */
4039 #define ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD 0x1
4040 /*
4041  * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED
4042  *
4043  * No Queued Read
4044  */
4045 #define ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION 0x0
4046 
4047 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */
4048 #define ALT_QSPI_INDRD_RD_QUEUED_LSB 4
4049 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */
4050 #define ALT_QSPI_INDRD_RD_QUEUED_MSB 4
4051 /* The width in bits of the ALT_QSPI_INDRD_RD_QUEUED register field. */
4052 #define ALT_QSPI_INDRD_RD_QUEUED_WIDTH 1
4053 /* The mask used to set the ALT_QSPI_INDRD_RD_QUEUED register field value. */
4054 #define ALT_QSPI_INDRD_RD_QUEUED_SET_MSK 0x00000010
4055 /* The mask used to clear the ALT_QSPI_INDRD_RD_QUEUED register field value. */
4056 #define ALT_QSPI_INDRD_RD_QUEUED_CLR_MSK 0xffffffef
4057 /* The reset value of the ALT_QSPI_INDRD_RD_QUEUED register field is UNKNOWN. */
4058 #define ALT_QSPI_INDRD_RD_QUEUED_RESET 0x0
4059 /* Extracts the ALT_QSPI_INDRD_RD_QUEUED field value from a register. */
4060 #define ALT_QSPI_INDRD_RD_QUEUED_GET(value) (((value) & 0x00000010) >> 4)
4061 /* Produces a ALT_QSPI_INDRD_RD_QUEUED register field value suitable for setting the register. */
4062 #define ALT_QSPI_INDRD_RD_QUEUED_SET(value) (((value) << 4) & 0x00000010)
4063 
4064 /*
4065  * Field : Indirect Completion Status - ind_ops_done_status
4066  *
4067  * This field is set to 1 when an indirect operation has completed. Write a 1 to
4068  * this field to clear it.
4069  *
4070  * Field Enumeration Values:
4071  *
4072  * Enum | Value | Description
4073  * :--------------------------------------------|:------|:-------------------------------
4074  * ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP | 0x1 | Indirect Op Complete operation
4075  * ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION | 0x0 | Indirect Op Not Complete
4076  *
4077  * Field Access Macros:
4078  *
4079  */
4080 /*
4081  * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT
4082  *
4083  * Indirect Op Complete operation
4084  */
4085 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP 0x1
4086 /*
4087  * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT
4088  *
4089  * Indirect Op Not Complete
4090  */
4091 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION 0x0
4092 
4093 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */
4094 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_LSB 5
4095 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */
4096 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_MSB 5
4097 /* The width in bits of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */
4098 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_WIDTH 1
4099 /* The mask used to set the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value. */
4100 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK 0x00000020
4101 /* The mask used to clear the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value. */
4102 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_CLR_MSK 0xffffffdf
4103 /* The reset value of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field is UNKNOWN. */
4104 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_RESET 0x0
4105 /* Extracts the ALT_QSPI_INDRD_IND_OPS_DONE_STAT field value from a register. */
4106 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_GET(value) (((value) & 0x00000020) >> 5)
4107 /* Produces a ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value suitable for setting the register. */
4108 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET(value) (((value) << 5) & 0x00000020)
4109 
4110 /*
4111  * Field : Completed Indirect Operations - num_ind_ops_done
4112  *
4113  * This field contains the number of indirect operations which have been completed.
4114  * This is used in conjunction with the indirect completion status field (bit 5).
4115  *
4116  * Field Access Macros:
4117  *
4118  */
4119 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */
4120 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_LSB 6
4121 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */
4122 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_MSB 7
4123 /* The width in bits of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */
4124 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_WIDTH 2
4125 /* The mask used to set the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */
4126 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET_MSK 0x000000c0
4127 /* The mask used to clear the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */
4128 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_CLR_MSK 0xffffff3f
4129 /* The reset value of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field is UNKNOWN. */
4130 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_RESET 0x0
4131 /* Extracts the ALT_QSPI_INDRD_NUM_IND_OPS_DONE field value from a register. */
4132 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_GET(value) (((value) & 0x000000c0) >> 6)
4133 /* Produces a ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value suitable for setting the register. */
4134 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET(value) (((value) << 6) & 0x000000c0)
4135 
4136 #ifndef __ASSEMBLY__
4137 /*
4138  * WARNING: The C register and register group struct declarations are provided for
4139  * convenience and illustrative purposes. They should, however, be used with
4140  * caution as the C language standard provides no guarantees about the alignment or
4141  * atomicity of device memory accesses. The recommended practice for writing
4142  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4143  * alt_write_word() functions.
4144  *
4145  * The struct declaration for register ALT_QSPI_INDRD.
4146  */
4147 struct ALT_QSPI_INDRD_s
4148 {
4149  uint32_t start : 1; /* Start Indirect Read */
4150  uint32_t cancel : 1; /* Cancel Indirect Read */
4151  const uint32_t rd_status : 1; /* Indirect Read Status */
4152  uint32_t sram_full : 1; /* SRAM Full */
4153  const uint32_t rd_queued : 1; /* Queued Indirect Read Operations */
4154  uint32_t ind_ops_done_status : 1; /* Indirect Completion Status */
4155  const uint32_t num_ind_ops_done : 2; /* Completed Indirect Operations */
4156  uint32_t : 24; /* *UNDEFINED* */
4157 };
4158 
4159 /* The typedef declaration for register ALT_QSPI_INDRD. */
4160 typedef volatile struct ALT_QSPI_INDRD_s ALT_QSPI_INDRD_t;
4161 #endif /* __ASSEMBLY__ */
4162 
4163 /* The byte offset of the ALT_QSPI_INDRD register from the beginning of the component. */
4164 #define ALT_QSPI_INDRD_OFST 0x60
4165 
4166 /*
4167  * Register : Indirect Read Transfer Watermark Register - indrdwater
4168  *
4169  * Register Layout
4170  *
4171  * Bits | Access | Reset | Description
4172  * :-------|:-------|:------|:----------------
4173  * [31:0] | RW | 0x0 | Watermark Value
4174  *
4175  */
4176 /*
4177  * Field : Watermark Value - level
4178  *
4179  * This represents the minimum fill level of the SRAM before a DMA peripheral
4180  * access is permitted. When the SRAM fill level passes the watermark, an interrupt
4181  * is also generated. This field can be disabled by writing a value of all zeroes.
4182  * The units of this register are BYTES
4183  *
4184  * Field Access Macros:
4185  *
4186  */
4187 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */
4188 #define ALT_QSPI_INDRDWATER_LEVEL_LSB 0
4189 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */
4190 #define ALT_QSPI_INDRDWATER_LEVEL_MSB 31
4191 /* The width in bits of the ALT_QSPI_INDRDWATER_LEVEL register field. */
4192 #define ALT_QSPI_INDRDWATER_LEVEL_WIDTH 32
4193 /* The mask used to set the ALT_QSPI_INDRDWATER_LEVEL register field value. */
4194 #define ALT_QSPI_INDRDWATER_LEVEL_SET_MSK 0xffffffff
4195 /* The mask used to clear the ALT_QSPI_INDRDWATER_LEVEL register field value. */
4196 #define ALT_QSPI_INDRDWATER_LEVEL_CLR_MSK 0x00000000
4197 /* The reset value of the ALT_QSPI_INDRDWATER_LEVEL register field. */
4198 #define ALT_QSPI_INDRDWATER_LEVEL_RESET 0x0
4199 /* Extracts the ALT_QSPI_INDRDWATER_LEVEL field value from a register. */
4200 #define ALT_QSPI_INDRDWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
4201 /* Produces a ALT_QSPI_INDRDWATER_LEVEL register field value suitable for setting the register. */
4202 #define ALT_QSPI_INDRDWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
4203 
4204 #ifndef __ASSEMBLY__
4205 /*
4206  * WARNING: The C register and register group struct declarations are provided for
4207  * convenience and illustrative purposes. They should, however, be used with
4208  * caution as the C language standard provides no guarantees about the alignment or
4209  * atomicity of device memory accesses. The recommended practice for writing
4210  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4211  * alt_write_word() functions.
4212  *
4213  * The struct declaration for register ALT_QSPI_INDRDWATER.
4214  */
4215 struct ALT_QSPI_INDRDWATER_s
4216 {
4217  uint32_t level : 32; /* Watermark Value */
4218 };
4219 
4220 /* The typedef declaration for register ALT_QSPI_INDRDWATER. */
4221 typedef volatile struct ALT_QSPI_INDRDWATER_s ALT_QSPI_INDRDWATER_t;
4222 #endif /* __ASSEMBLY__ */
4223 
4224 /* The byte offset of the ALT_QSPI_INDRDWATER register from the beginning of the component. */
4225 #define ALT_QSPI_INDRDWATER_OFST 0x64
4226 
4227 /*
4228  * Register : Indirect Read Transfer Start Address Register - indrdstaddr
4229  *
4230  * Register Layout
4231  *
4232  * Bits | Access | Reset | Description
4233  * :-------|:-------|:------|:---------------------------------
4234  * [31:0] | RW | 0x0 | Start Address of Indirect Access
4235  *
4236  */
4237 /*
4238  * Field : Start Address of Indirect Access - addr
4239  *
4240  * This is the start address from which the indirect access will commence its READ
4241  * operation.
4242  *
4243  * Field Access Macros:
4244  *
4245  */
4246 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */
4247 #define ALT_QSPI_INDRDSTADDR_ADDR_LSB 0
4248 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */
4249 #define ALT_QSPI_INDRDSTADDR_ADDR_MSB 31
4250 /* The width in bits of the ALT_QSPI_INDRDSTADDR_ADDR register field. */
4251 #define ALT_QSPI_INDRDSTADDR_ADDR_WIDTH 32
4252 /* The mask used to set the ALT_QSPI_INDRDSTADDR_ADDR register field value. */
4253 #define ALT_QSPI_INDRDSTADDR_ADDR_SET_MSK 0xffffffff
4254 /* The mask used to clear the ALT_QSPI_INDRDSTADDR_ADDR register field value. */
4255 #define ALT_QSPI_INDRDSTADDR_ADDR_CLR_MSK 0x00000000
4256 /* The reset value of the ALT_QSPI_INDRDSTADDR_ADDR register field. */
4257 #define ALT_QSPI_INDRDSTADDR_ADDR_RESET 0x0
4258 /* Extracts the ALT_QSPI_INDRDSTADDR_ADDR field value from a register. */
4259 #define ALT_QSPI_INDRDSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4260 /* Produces a ALT_QSPI_INDRDSTADDR_ADDR register field value suitable for setting the register. */
4261 #define ALT_QSPI_INDRDSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4262 
4263 #ifndef __ASSEMBLY__
4264 /*
4265  * WARNING: The C register and register group struct declarations are provided for
4266  * convenience and illustrative purposes. They should, however, be used with
4267  * caution as the C language standard provides no guarantees about the alignment or
4268  * atomicity of device memory accesses. The recommended practice for writing
4269  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4270  * alt_write_word() functions.
4271  *
4272  * The struct declaration for register ALT_QSPI_INDRDSTADDR.
4273  */
4274 struct ALT_QSPI_INDRDSTADDR_s
4275 {
4276  uint32_t addr : 32; /* Start Address of Indirect Access */
4277 };
4278 
4279 /* The typedef declaration for register ALT_QSPI_INDRDSTADDR. */
4280 typedef volatile struct ALT_QSPI_INDRDSTADDR_s ALT_QSPI_INDRDSTADDR_t;
4281 #endif /* __ASSEMBLY__ */
4282 
4283 /* The byte offset of the ALT_QSPI_INDRDSTADDR register from the beginning of the component. */
4284 #define ALT_QSPI_INDRDSTADDR_OFST 0x68
4285 
4286 /*
4287  * Register : Indirect Read Transfer Number Bytes Register - indrdcnt
4288  *
4289  * Register Layout
4290  *
4291  * Bits | Access | Reset | Description
4292  * :-------|:-------|:------|:---------------
4293  * [31:0] | RW | 0x0 | Indirect Count
4294  *
4295  */
4296 /*
4297  * Field : Indirect Count - value
4298  *
4299  * This is the number of bytes that the indirect access will consume. This can be
4300  * bigger than the configured size of SRAM.
4301  *
4302  * Field Access Macros:
4303  *
4304  */
4305 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */
4306 #define ALT_QSPI_INDRDCNT_VALUE_LSB 0
4307 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */
4308 #define ALT_QSPI_INDRDCNT_VALUE_MSB 31
4309 /* The width in bits of the ALT_QSPI_INDRDCNT_VALUE register field. */
4310 #define ALT_QSPI_INDRDCNT_VALUE_WIDTH 32
4311 /* The mask used to set the ALT_QSPI_INDRDCNT_VALUE register field value. */
4312 #define ALT_QSPI_INDRDCNT_VALUE_SET_MSK 0xffffffff
4313 /* The mask used to clear the ALT_QSPI_INDRDCNT_VALUE register field value. */
4314 #define ALT_QSPI_INDRDCNT_VALUE_CLR_MSK 0x00000000
4315 /* The reset value of the ALT_QSPI_INDRDCNT_VALUE register field. */
4316 #define ALT_QSPI_INDRDCNT_VALUE_RESET 0x0
4317 /* Extracts the ALT_QSPI_INDRDCNT_VALUE field value from a register. */
4318 #define ALT_QSPI_INDRDCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
4319 /* Produces a ALT_QSPI_INDRDCNT_VALUE register field value suitable for setting the register. */
4320 #define ALT_QSPI_INDRDCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)
4321 
4322 #ifndef __ASSEMBLY__
4323 /*
4324  * WARNING: The C register and register group struct declarations are provided for
4325  * convenience and illustrative purposes. They should, however, be used with
4326  * caution as the C language standard provides no guarantees about the alignment or
4327  * atomicity of device memory accesses. The recommended practice for writing
4328  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4329  * alt_write_word() functions.
4330  *
4331  * The struct declaration for register ALT_QSPI_INDRDCNT.
4332  */
4333 struct ALT_QSPI_INDRDCNT_s
4334 {
4335  uint32_t value : 32; /* Indirect Count */
4336 };
4337 
4338 /* The typedef declaration for register ALT_QSPI_INDRDCNT. */
4339 typedef volatile struct ALT_QSPI_INDRDCNT_s ALT_QSPI_INDRDCNT_t;
4340 #endif /* __ASSEMBLY__ */
4341 
4342 /* The byte offset of the ALT_QSPI_INDRDCNT register from the beginning of the component. */
4343 #define ALT_QSPI_INDRDCNT_OFST 0x6c
4344 
4345 /*
4346  * Register : Indirect Write Transfer Register - indwr
4347  *
4348  * Register Layout
4349  *
4350  * Bits | Access | Reset | Description
4351  * :-------|:-------|:--------|:---------------------------------
4352  * [0] | RW | 0x0 | Start Indirect Write
4353  * [1] | RW | 0x0 | Cancel Indirect Write
4354  * [2] | R | Unknown | Indirect Write Status
4355  * [3] | R | 0x0 | Reserved
4356  * [4] | R | Unknown | Queued Indirect Write Operations
4357  * [5] | RW | Unknown | Indirect Completion Status
4358  * [7:6] | R | Unknown | Completed Indirect Operations
4359  * [31:8] | ??? | 0x0 | *UNDEFINED*
4360  *
4361  */
4362 /*
4363  * Field : Start Indirect Write - start
4364  *
4365  * Writing a 1 to this bit will trigger an indirect write operation. The assumption
4366  * is that the indirect start address and the indirect number of bytes register is
4367  * setup before triggering the indirect write operation.
4368  *
4369  * Field Enumeration Values:
4370  *
4371  * Enum | Value | Description
4372  * :----------------------------|:------|:---------------------------------
4373  * ALT_QSPI_INDWR_START_E_END | 0x1 | Trigger indirect write operation
4374  * ALT_QSPI_INDWR_START_E_DISD | 0x0 | No Action
4375  *
4376  * Field Access Macros:
4377  *
4378  */
4379 /*
4380  * Enumerated value for register field ALT_QSPI_INDWR_START
4381  *
4382  * Trigger indirect write operation
4383  */
4384 #define ALT_QSPI_INDWR_START_E_END 0x1
4385 /*
4386  * Enumerated value for register field ALT_QSPI_INDWR_START
4387  *
4388  * No Action
4389  */
4390 #define ALT_QSPI_INDWR_START_E_DISD 0x0
4391 
4392 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_START register field. */
4393 #define ALT_QSPI_INDWR_START_LSB 0
4394 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_START register field. */
4395 #define ALT_QSPI_INDWR_START_MSB 0
4396 /* The width in bits of the ALT_QSPI_INDWR_START register field. */
4397 #define ALT_QSPI_INDWR_START_WIDTH 1
4398 /* The mask used to set the ALT_QSPI_INDWR_START register field value. */
4399 #define ALT_QSPI_INDWR_START_SET_MSK 0x00000001
4400 /* The mask used to clear the ALT_QSPI_INDWR_START register field value. */
4401 #define ALT_QSPI_INDWR_START_CLR_MSK 0xfffffffe
4402 /* The reset value of the ALT_QSPI_INDWR_START register field. */
4403 #define ALT_QSPI_INDWR_START_RESET 0x0
4404 /* Extracts the ALT_QSPI_INDWR_START field value from a register. */
4405 #define ALT_QSPI_INDWR_START_GET(value) (((value) & 0x00000001) >> 0)
4406 /* Produces a ALT_QSPI_INDWR_START register field value suitable for setting the register. */
4407 #define ALT_QSPI_INDWR_START_SET(value) (((value) << 0) & 0x00000001)
4408 
4409 /*
4410  * Field : Cancel Indirect Write - cancel
4411  *
4412  * Writing a 1 to this bit will cancel all ongoing indirect write operations.
4413  *
4414  * Field Enumeration Values:
4415  *
4416  * Enum | Value | Description
4417  * :-----------------------------------|:------|:--------------------------------
4418  * ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR | 0x1 | Cancel Indirect write operation
4419  * ALT_QSPI_INDWR_CANCEL_E_NOACTION | 0x0 | No Action
4420  *
4421  * Field Access Macros:
4422  *
4423  */
4424 /*
4425  * Enumerated value for register field ALT_QSPI_INDWR_CANCEL
4426  *
4427  * Cancel Indirect write operation
4428  */
4429 #define ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR 0x1
4430 /*
4431  * Enumerated value for register field ALT_QSPI_INDWR_CANCEL
4432  *
4433  * No Action
4434  */
4435 #define ALT_QSPI_INDWR_CANCEL_E_NOACTION 0x0
4436 
4437 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_CANCEL register field. */
4438 #define ALT_QSPI_INDWR_CANCEL_LSB 1
4439 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_CANCEL register field. */
4440 #define ALT_QSPI_INDWR_CANCEL_MSB 1
4441 /* The width in bits of the ALT_QSPI_INDWR_CANCEL register field. */
4442 #define ALT_QSPI_INDWR_CANCEL_WIDTH 1
4443 /* The mask used to set the ALT_QSPI_INDWR_CANCEL register field value. */
4444 #define ALT_QSPI_INDWR_CANCEL_SET_MSK 0x00000002
4445 /* The mask used to clear the ALT_QSPI_INDWR_CANCEL register field value. */
4446 #define ALT_QSPI_INDWR_CANCEL_CLR_MSK 0xfffffffd
4447 /* The reset value of the ALT_QSPI_INDWR_CANCEL register field. */
4448 #define ALT_QSPI_INDWR_CANCEL_RESET 0x0
4449 /* Extracts the ALT_QSPI_INDWR_CANCEL field value from a register. */
4450 #define ALT_QSPI_INDWR_CANCEL_GET(value) (((value) & 0x00000002) >> 1)
4451 /* Produces a ALT_QSPI_INDWR_CANCEL register field value suitable for setting the register. */
4452 #define ALT_QSPI_INDWR_CANCEL_SET(value) (((value) << 1) & 0x00000002)
4453 
4454 /*
4455  * Field : Indirect Write Status - rdstat
4456  *
4457  * Indirect write operation in progress (status)
4458  *
4459  * Field Enumeration Values:
4460  *
4461  * Enum | Value | Description
4462  * :----------------------------------|:------|:-------------------------
4463  * ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT | 0x1 | Indirect write operation
4464  * ALT_QSPI_INDWR_RDSTAT_E_NOACTION | 0x0 | No Action
4465  *
4466  * Field Access Macros:
4467  *
4468  */
4469 /*
4470  * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT
4471  *
4472  * Indirect write operation
4473  */
4474 #define ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT 0x1
4475 /*
4476  * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT
4477  *
4478  * No Action
4479  */
4480 #define ALT_QSPI_INDWR_RDSTAT_E_NOACTION 0x0
4481 
4482 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */
4483 #define ALT_QSPI_INDWR_RDSTAT_LSB 2
4484 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */
4485 #define ALT_QSPI_INDWR_RDSTAT_MSB 2
4486 /* The width in bits of the ALT_QSPI_INDWR_RDSTAT register field. */
4487 #define ALT_QSPI_INDWR_RDSTAT_WIDTH 1
4488 /* The mask used to set the ALT_QSPI_INDWR_RDSTAT register field value. */
4489 #define ALT_QSPI_INDWR_RDSTAT_SET_MSK 0x00000004
4490 /* The mask used to clear the ALT_QSPI_INDWR_RDSTAT register field value. */
4491 #define ALT_QSPI_INDWR_RDSTAT_CLR_MSK 0xfffffffb
4492 /* The reset value of the ALT_QSPI_INDWR_RDSTAT register field is UNKNOWN. */
4493 #define ALT_QSPI_INDWR_RDSTAT_RESET 0x0
4494 /* Extracts the ALT_QSPI_INDWR_RDSTAT field value from a register. */
4495 #define ALT_QSPI_INDWR_RDSTAT_GET(value) (((value) & 0x00000004) >> 2)
4496 /* Produces a ALT_QSPI_INDWR_RDSTAT register field value suitable for setting the register. */
4497 #define ALT_QSPI_INDWR_RDSTAT_SET(value) (((value) << 2) & 0x00000004)
4498 
4499 /*
4500  * Field : Reserved - sramfull
4501  *
4502  * Field Access Macros:
4503  *
4504  */
4505 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_SRAMFULL register field. */
4506 #define ALT_QSPI_INDWR_SRAMFULL_LSB 3
4507 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_SRAMFULL register field. */
4508 #define ALT_QSPI_INDWR_SRAMFULL_MSB 3
4509 /* The width in bits of the ALT_QSPI_INDWR_SRAMFULL register field. */
4510 #define ALT_QSPI_INDWR_SRAMFULL_WIDTH 1
4511 /* The mask used to set the ALT_QSPI_INDWR_SRAMFULL register field value. */
4512 #define ALT_QSPI_INDWR_SRAMFULL_SET_MSK 0x00000008
4513 /* The mask used to clear the ALT_QSPI_INDWR_SRAMFULL register field value. */
4514 #define ALT_QSPI_INDWR_SRAMFULL_CLR_MSK 0xfffffff7
4515 /* The reset value of the ALT_QSPI_INDWR_SRAMFULL register field. */
4516 #define ALT_QSPI_INDWR_SRAMFULL_RESET 0x0
4517 /* Extracts the ALT_QSPI_INDWR_SRAMFULL field value from a register. */
4518 #define ALT_QSPI_INDWR_SRAMFULL_GET(value) (((value) & 0x00000008) >> 3)
4519 /* Produces a ALT_QSPI_INDWR_SRAMFULL register field value suitable for setting the register. */
4520 #define ALT_QSPI_INDWR_SRAMFULL_SET(value) (((value) << 3) & 0x00000008)
4521 
4522 /*
4523  * Field : Queued Indirect Write Operations - rdqueued
4524  *
4525  * Two indirect write operations have been queued
4526  *
4527  * Field Enumeration Values:
4528  *
4529  * Enum | Value | Description
4530  * :-----------------------------------|:------|:-----------------------------
4531  * ALT_QSPI_INDWR_RDQUEUED_E_INDWROP | 0x1 | Two Indirect write operation
4532  * ALT_QSPI_INDWR_RDQUEUED_E_NOACTION | 0x0 | No Action
4533  *
4534  * Field Access Macros:
4535  *
4536  */
4537 /*
4538  * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED
4539  *
4540  * Two Indirect write operation
4541  */
4542 #define ALT_QSPI_INDWR_RDQUEUED_E_INDWROP 0x1
4543 /*
4544  * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED
4545  *
4546  * No Action
4547  */
4548 #define ALT_QSPI_INDWR_RDQUEUED_E_NOACTION 0x0
4549 
4550 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */
4551 #define ALT_QSPI_INDWR_RDQUEUED_LSB 4
4552 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */
4553 #define ALT_QSPI_INDWR_RDQUEUED_MSB 4
4554 /* The width in bits of the ALT_QSPI_INDWR_RDQUEUED register field. */
4555 #define ALT_QSPI_INDWR_RDQUEUED_WIDTH 1
4556 /* The mask used to set the ALT_QSPI_INDWR_RDQUEUED register field value. */
4557 #define ALT_QSPI_INDWR_RDQUEUED_SET_MSK 0x00000010
4558 /* The mask used to clear the ALT_QSPI_INDWR_RDQUEUED register field value. */
4559 #define ALT_QSPI_INDWR_RDQUEUED_CLR_MSK 0xffffffef
4560 /* The reset value of the ALT_QSPI_INDWR_RDQUEUED register field is UNKNOWN. */
4561 #define ALT_QSPI_INDWR_RDQUEUED_RESET 0x0
4562 /* Extracts the ALT_QSPI_INDWR_RDQUEUED field value from a register. */
4563 #define ALT_QSPI_INDWR_RDQUEUED_GET(value) (((value) & 0x00000010) >> 4)
4564 /* Produces a ALT_QSPI_INDWR_RDQUEUED register field value suitable for setting the register. */
4565 #define ALT_QSPI_INDWR_RDQUEUED_SET(value) (((value) << 4) & 0x00000010)
4566 
4567 /*
4568  * Field : Indirect Completion Status - inddone
4569  *
4570  * This field is set to 1 when an indirect operation has completed. Write a 1 to
4571  * this field to clear it.
4572  *
4573  * Field Enumeration Values:
4574  *
4575  * Enum | Value | Description
4576  * :-----------------------------------|:------|:-----------------------------
4577  * ALT_QSPI_INDWR_INDDONE_E_INDCOMPST | 0x1 | Indirect operation completed
4578  * ALT_QSPI_INDWR_INDDONE_E_NOACTION | 0x0 | No Action
4579  *
4580  * Field Access Macros:
4581  *
4582  */
4583 /*
4584  * Enumerated value for register field ALT_QSPI_INDWR_INDDONE
4585  *
4586  * Indirect operation completed
4587  */
4588 #define ALT_QSPI_INDWR_INDDONE_E_INDCOMPST 0x1
4589 /*
4590  * Enumerated value for register field ALT_QSPI_INDWR_INDDONE
4591  *
4592  * No Action
4593  */
4594 #define ALT_QSPI_INDWR_INDDONE_E_NOACTION 0x0
4595 
4596 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDDONE register field. */
4597 #define ALT_QSPI_INDWR_INDDONE_LSB 5
4598 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDDONE register field. */
4599 #define ALT_QSPI_INDWR_INDDONE_MSB 5
4600 /* The width in bits of the ALT_QSPI_INDWR_INDDONE register field. */
4601 #define ALT_QSPI_INDWR_INDDONE_WIDTH 1
4602 /* The mask used to set the ALT_QSPI_INDWR_INDDONE register field value. */
4603 #define ALT_QSPI_INDWR_INDDONE_SET_MSK 0x00000020
4604 /* The mask used to clear the ALT_QSPI_INDWR_INDDONE register field value. */
4605 #define ALT_QSPI_INDWR_INDDONE_CLR_MSK 0xffffffdf
4606 /* The reset value of the ALT_QSPI_INDWR_INDDONE register field is UNKNOWN. */
4607 #define ALT_QSPI_INDWR_INDDONE_RESET 0x0
4608 /* Extracts the ALT_QSPI_INDWR_INDDONE field value from a register. */
4609 #define ALT_QSPI_INDWR_INDDONE_GET(value) (((value) & 0x00000020) >> 5)
4610 /* Produces a ALT_QSPI_INDWR_INDDONE register field value suitable for setting the register. */
4611 #define ALT_QSPI_INDWR_INDDONE_SET(value) (((value) << 5) & 0x00000020)
4612 
4613 /*
4614  * Field : Completed Indirect Operations - indcnt
4615  *
4616  * This field contains the count of indirect operations which have been completed.
4617  * This is used in conjunction with the indirect completion status field (bit 5).
4618  *
4619  * Field Access Macros:
4620  *
4621  */
4622 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDCNT register field. */
4623 #define ALT_QSPI_INDWR_INDCNT_LSB 6
4624 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDCNT register field. */
4625 #define ALT_QSPI_INDWR_INDCNT_MSB 7
4626 /* The width in bits of the ALT_QSPI_INDWR_INDCNT register field. */
4627 #define ALT_QSPI_INDWR_INDCNT_WIDTH 2
4628 /* The mask used to set the ALT_QSPI_INDWR_INDCNT register field value. */
4629 #define ALT_QSPI_INDWR_INDCNT_SET_MSK 0x000000c0
4630 /* The mask used to clear the ALT_QSPI_INDWR_INDCNT register field value. */
4631 #define ALT_QSPI_INDWR_INDCNT_CLR_MSK 0xffffff3f
4632 /* The reset value of the ALT_QSPI_INDWR_INDCNT register field is UNKNOWN. */
4633 #define ALT_QSPI_INDWR_INDCNT_RESET 0x0
4634 /* Extracts the ALT_QSPI_INDWR_INDCNT field value from a register. */
4635 #define ALT_QSPI_INDWR_INDCNT_GET(value) (((value) & 0x000000c0) >> 6)
4636 /* Produces a ALT_QSPI_INDWR_INDCNT register field value suitable for setting the register. */
4637 #define ALT_QSPI_INDWR_INDCNT_SET(value) (((value) << 6) & 0x000000c0)
4638 
4639 #ifndef __ASSEMBLY__
4640 /*
4641  * WARNING: The C register and register group struct declarations are provided for
4642  * convenience and illustrative purposes. They should, however, be used with
4643  * caution as the C language standard provides no guarantees about the alignment or
4644  * atomicity of device memory accesses. The recommended practice for writing
4645  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4646  * alt_write_word() functions.
4647  *
4648  * The struct declaration for register ALT_QSPI_INDWR.
4649  */
4650 struct ALT_QSPI_INDWR_s
4651 {
4652  uint32_t start : 1; /* Start Indirect Write */
4653  uint32_t cancel : 1; /* Cancel Indirect Write */
4654  const uint32_t rdstat : 1; /* Indirect Write Status */
4655  const uint32_t sramfull : 1; /* Reserved */
4656  const uint32_t rdqueued : 1; /* Queued Indirect Write Operations */
4657  uint32_t inddone : 1; /* Indirect Completion Status */
4658  const uint32_t indcnt : 2; /* Completed Indirect Operations */
4659  uint32_t : 24; /* *UNDEFINED* */
4660 };
4661 
4662 /* The typedef declaration for register ALT_QSPI_INDWR. */
4663 typedef volatile struct ALT_QSPI_INDWR_s ALT_QSPI_INDWR_t;
4664 #endif /* __ASSEMBLY__ */
4665 
4666 /* The byte offset of the ALT_QSPI_INDWR register from the beginning of the component. */
4667 #define ALT_QSPI_INDWR_OFST 0x70
4668 
4669 /*
4670  * Register : Indirect Write Transfer Watermark Register - indwrwater
4671  *
4672  * Register Layout
4673  *
4674  * Bits | Access | Reset | Description
4675  * :-------|:-------|:-----------|:----------------
4676  * [31:0] | RW | 0xffffffff | Watermark Value
4677  *
4678  */
4679 /*
4680  * Field : Watermark Value - level
4681  *
4682  * This represents the maximum fill level of the SRAM before a DMA peripheral
4683  * access is permitted. When the SRAM fill level falls below the watermark, an
4684  * interrupt is also generated. This field can be disabled by writing a value of
4685  * all ones. The units of this register are bytes.
4686  *
4687  * Field Access Macros:
4688  *
4689  */
4690 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */
4691 #define ALT_QSPI_INDWRWATER_LEVEL_LSB 0
4692 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */
4693 #define ALT_QSPI_INDWRWATER_LEVEL_MSB 31
4694 /* The width in bits of the ALT_QSPI_INDWRWATER_LEVEL register field. */
4695 #define ALT_QSPI_INDWRWATER_LEVEL_WIDTH 32
4696 /* The mask used to set the ALT_QSPI_INDWRWATER_LEVEL register field value. */
4697 #define ALT_QSPI_INDWRWATER_LEVEL_SET_MSK 0xffffffff
4698 /* The mask used to clear the ALT_QSPI_INDWRWATER_LEVEL register field value. */
4699 #define ALT_QSPI_INDWRWATER_LEVEL_CLR_MSK 0x00000000
4700 /* The reset value of the ALT_QSPI_INDWRWATER_LEVEL register field. */
4701 #define ALT_QSPI_INDWRWATER_LEVEL_RESET 0xffffffff
4702 /* Extracts the ALT_QSPI_INDWRWATER_LEVEL field value from a register. */
4703 #define ALT_QSPI_INDWRWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
4704 /* Produces a ALT_QSPI_INDWRWATER_LEVEL register field value suitable for setting the register. */
4705 #define ALT_QSPI_INDWRWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
4706 
4707 #ifndef __ASSEMBLY__
4708 /*
4709  * WARNING: The C register and register group struct declarations are provided for
4710  * convenience and illustrative purposes. They should, however, be used with
4711  * caution as the C language standard provides no guarantees about the alignment or
4712  * atomicity of device memory accesses. The recommended practice for writing
4713  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4714  * alt_write_word() functions.
4715  *
4716  * The struct declaration for register ALT_QSPI_INDWRWATER.
4717  */
4718 struct ALT_QSPI_INDWRWATER_s
4719 {
4720  uint32_t level : 32; /* Watermark Value */
4721 };
4722 
4723 /* The typedef declaration for register ALT_QSPI_INDWRWATER. */
4724 typedef volatile struct ALT_QSPI_INDWRWATER_s ALT_QSPI_INDWRWATER_t;
4725 #endif /* __ASSEMBLY__ */
4726 
4727 /* The byte offset of the ALT_QSPI_INDWRWATER register from the beginning of the component. */
4728 #define ALT_QSPI_INDWRWATER_OFST 0x74
4729 
4730 /*
4731  * Register : Indirect Write Transfer Start Address Register - indwrstaddr
4732  *
4733  * Register Layout
4734  *
4735  * Bits | Access | Reset | Description
4736  * :-------|:-------|:------|:-------------------------
4737  * [31:0] | RW | 0x0 | Start of Indirect Access
4738  *
4739  */
4740 /*
4741  * Field : Start of Indirect Access - addr
4742  *
4743  * This is the start address from which the indirect access will commence its write
4744  * operation.
4745  *
4746  * Field Access Macros:
4747  *
4748  */
4749 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */
4750 #define ALT_QSPI_INDWRSTADDR_ADDR_LSB 0
4751 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */
4752 #define ALT_QSPI_INDWRSTADDR_ADDR_MSB 31
4753 /* The width in bits of the ALT_QSPI_INDWRSTADDR_ADDR register field. */
4754 #define ALT_QSPI_INDWRSTADDR_ADDR_WIDTH 32
4755 /* The mask used to set the ALT_QSPI_INDWRSTADDR_ADDR register field value. */
4756 #define ALT_QSPI_INDWRSTADDR_ADDR_SET_MSK 0xffffffff
4757 /* The mask used to clear the ALT_QSPI_INDWRSTADDR_ADDR register field value. */
4758 #define ALT_QSPI_INDWRSTADDR_ADDR_CLR_MSK 0x00000000
4759 /* The reset value of the ALT_QSPI_INDWRSTADDR_ADDR register field. */
4760 #define ALT_QSPI_INDWRSTADDR_ADDR_RESET 0x0
4761 /* Extracts the ALT_QSPI_INDWRSTADDR_ADDR field value from a register. */
4762 #define ALT_QSPI_INDWRSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4763 /* Produces a ALT_QSPI_INDWRSTADDR_ADDR register field value suitable for setting the register. */
4764 #define ALT_QSPI_INDWRSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4765 
4766 #ifndef __ASSEMBLY__
4767 /*
4768  * WARNING: The C register and register group struct declarations are provided for
4769  * convenience and illustrative purposes. They should, however, be used with
4770  * caution as the C language standard provides no guarantees about the alignment or
4771  * atomicity of device memory accesses. The recommended practice for writing
4772  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4773  * alt_write_word() functions.
4774  *
4775  * The struct declaration for register ALT_QSPI_INDWRSTADDR.
4776  */
4777 struct ALT_QSPI_INDWRSTADDR_s
4778 {
4779  uint32_t addr : 32; /* Start of Indirect Access */
4780 };
4781 
4782 /* The typedef declaration for register ALT_QSPI_INDWRSTADDR. */
4783 typedef volatile struct ALT_QSPI_INDWRSTADDR_s ALT_QSPI_INDWRSTADDR_t;
4784 #endif /* __ASSEMBLY__ */
4785 
4786 /* The byte offset of the ALT_QSPI_INDWRSTADDR register from the beginning of the component. */
4787 #define ALT_QSPI_INDWRSTADDR_OFST 0x78
4788 
4789 /*
4790  * Register : Indirect Write Transfer Count Register - indwrcnt
4791  *
4792  * Register Layout
4793  *
4794  * Bits | Access | Reset | Description
4795  * :-------|:-------|:------|:-------------------------
4796  * [31:0] | RW | 0x0 | Indirect Number of Bytes
4797  *
4798  */
4799 /*
4800  * Field : Indirect Number of Bytes - value
4801  *
4802  * This is the number of bytes that the indirect access will consume. This can be
4803  * bigger than the configured size of SRAM.
4804  *
4805  * Field Access Macros:
4806  *
4807  */
4808 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */
4809 #define ALT_QSPI_INDWRCNT_VALUE_LSB 0
4810 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */
4811 #define ALT_QSPI_INDWRCNT_VALUE_MSB 31
4812 /* The width in bits of the ALT_QSPI_INDWRCNT_VALUE register field. */
4813 #define ALT_QSPI_INDWRCNT_VALUE_WIDTH 32
4814 /* The mask used to set the ALT_QSPI_INDWRCNT_VALUE register field value. */
4815 #define ALT_QSPI_INDWRCNT_VALUE_SET_MSK 0xffffffff
4816 /* The mask used to clear the ALT_QSPI_INDWRCNT_VALUE register field value. */
4817 #define ALT_QSPI_INDWRCNT_VALUE_CLR_MSK 0x00000000
4818 /* The reset value of the ALT_QSPI_INDWRCNT_VALUE register field. */
4819 #define ALT_QSPI_INDWRCNT_VALUE_RESET 0x0
4820 /* Extracts the ALT_QSPI_INDWRCNT_VALUE field value from a register. */
4821 #define ALT_QSPI_INDWRCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
4822 /* Produces a ALT_QSPI_INDWRCNT_VALUE register field value suitable for setting the register. */
4823 #define ALT_QSPI_INDWRCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)
4824 
4825 #ifndef __ASSEMBLY__
4826 /*
4827  * WARNING: The C register and register group struct declarations are provided for
4828  * convenience and illustrative purposes. They should, however, be used with
4829  * caution as the C language standard provides no guarantees about the alignment or
4830  * atomicity of device memory accesses. The recommended practice for writing
4831  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4832  * alt_write_word() functions.
4833  *
4834  * The struct declaration for register ALT_QSPI_INDWRCNT.
4835  */
4836 struct ALT_QSPI_INDWRCNT_s
4837 {
4838  uint32_t value : 32; /* Indirect Number of Bytes */
4839 };
4840 
4841 /* The typedef declaration for register ALT_QSPI_INDWRCNT. */
4842 typedef volatile struct ALT_QSPI_INDWRCNT_s ALT_QSPI_INDWRCNT_t;
4843 #endif /* __ASSEMBLY__ */
4844 
4845 /* The byte offset of the ALT_QSPI_INDWRCNT register from the beginning of the component. */
4846 #define ALT_QSPI_INDWRCNT_OFST 0x7c
4847 
4848 /*
4849  * Register : Flash Command Register - flashcmd
4850  *
4851  * Register Layout
4852  *
4853  * Bits | Access | Reset | Description
4854  * :--------|:-------|:------|:---------------------------
4855  * [0] | RW | 0x0 | Execute Command
4856  * [1] | R | 0x0 | Command Execution Status
4857  * [6:2] | ??? | 0x0 | *UNDEFINED*
4858  * [11:7] | RW | 0x0 | Number of Dummy Bytes
4859  * [14:12] | RW | 0x0 | Number of Write Data Bytes
4860  * [15] | RW | 0x0 | Write Data Enable
4861  * [17:16] | RW | 0x0 | Number of Address Bytes
4862  * [18] | RW | 0x0 | Mode Bit Enable
4863  * [19] | RW | 0x0 | Command Address Enable
4864  * [22:20] | RW | 0x0 | Number of Read Data Bytes
4865  * [23] | RW | 0x0 | Read Data Enable
4866  * [31:24] | RW | 0x0 | Command Opcode
4867  *
4868  */
4869 /*
4870  * Field : Execute Command - execcmd
4871  *
4872  * Execute the command.
4873  *
4874  * Field Enumeration Values:
4875  *
4876  * Enum | Value | Description
4877  * :------------------------------------|:------|:----------------
4878  * ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE | 0x1 | Execute Command
4879  * ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION | 0x0 | No Action
4880  *
4881  * Field Access Macros:
4882  *
4883  */
4884 /*
4885  * Enumerated value for register field ALT_QSPI_FLSHCMD_EXECCMD
4886  *
4887  * Execute Command
4888  */
4889 #define ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE 0x1
4890 /*
4891  * Enumerated value for register field ALT_QSPI_FLSHCMD_EXECCMD
4892  *
4893  * No Action
4894  */
4895 #define ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION 0x0
4896 
4897 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_EXECCMD register field. */
4898 #define ALT_QSPI_FLSHCMD_EXECCMD_LSB 0
4899 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_EXECCMD register field. */
4900 #define ALT_QSPI_FLSHCMD_EXECCMD_MSB 0
4901 /* The width in bits of the ALT_QSPI_FLSHCMD_EXECCMD register field. */
4902 #define ALT_QSPI_FLSHCMD_EXECCMD_WIDTH 1
4903 /* The mask used to set the ALT_QSPI_FLSHCMD_EXECCMD register field value. */
4904 #define ALT_QSPI_FLSHCMD_EXECCMD_SET_MSK 0x00000001
4905 /* The mask used to clear the ALT_QSPI_FLSHCMD_EXECCMD register field value. */
4906 #define ALT_QSPI_FLSHCMD_EXECCMD_CLR_MSK 0xfffffffe
4907 /* The reset value of the ALT_QSPI_FLSHCMD_EXECCMD register field. */
4908 #define ALT_QSPI_FLSHCMD_EXECCMD_RESET 0x0
4909 /* Extracts the ALT_QSPI_FLSHCMD_EXECCMD field value from a register. */
4910 #define ALT_QSPI_FLSHCMD_EXECCMD_GET(value) (((value) & 0x00000001) >> 0)
4911 /* Produces a ALT_QSPI_FLSHCMD_EXECCMD register field value suitable for setting the register. */
4912 #define ALT_QSPI_FLSHCMD_EXECCMD_SET(value) (((value) << 0) & 0x00000001)
4913 
4914 /*
4915  * Field : Command Execution Status - cmdexecstat
4916  *
4917  * Command execution in progress.
4918  *
4919  * Field Enumeration Values:
4920  *
4921  * Enum | Value | Description
4922  * :-------------------------------------------|:------|:-------------------------
4923  * ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT | 0x1 | Command Execution Status
4924  * ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION | 0x0 | No Action
4925  *
4926  * Field Access Macros:
4927  *
4928  */
4929 /*
4930  * Enumerated value for register field ALT_QSPI_FLSHCMD_CMDEXECSTAT
4931  *
4932  * Command Execution Status
4933  */
4934 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT 0x1
4935 /*
4936  * Enumerated value for register field ALT_QSPI_FLSHCMD_CMDEXECSTAT
4937  *
4938  * No Action
4939  */
4940 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION 0x0
4941 
4942 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */
4943 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_LSB 1
4944 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */
4945 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_MSB 1
4946 /* The width in bits of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */
4947 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_WIDTH 1
4948 /* The mask used to set the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value. */
4949 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET_MSK 0x00000002
4950 /* The mask used to clear the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value. */
4951 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_CLR_MSK 0xfffffffd
4952 /* The reset value of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */
4953 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_RESET 0x0
4954 /* Extracts the ALT_QSPI_FLSHCMD_CMDEXECSTAT field value from a register. */
4955 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_GET(value) (((value) & 0x00000002) >> 1)
4956 /* Produces a ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value suitable for setting the register. */
4957 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET(value) (((value) << 1) & 0x00000002)
4958 
4959 /*
4960  * Field : Number of Dummy Bytes - numdummybytes
4961  *
4962  * Set to the number of dummy bytes required This should be setup before triggering
4963  * the command via the execute field of this register.
4964  *
4965  * Field Access Macros:
4966  *
4967  */
4968 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */
4969 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_LSB 7
4970 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */
4971 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_MSB 11
4972 /* The width in bits of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */
4973 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH 5
4974 /* The mask used to set the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value. */
4975 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET_MSK 0x00000f80
4976 /* The mask used to clear the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value. */
4977 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_CLR_MSK 0xfffff07f
4978 /* The reset value of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */
4979 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_RESET 0x0
4980 /* Extracts the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES field value from a register. */
4981 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_GET(value) (((value) & 0x00000f80) >> 7)
4982 /* Produces a ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value suitable for setting the register. */
4983 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(value) (((value) << 7) & 0x00000f80)
4984 
4985 /*
4986  * Field : Number of Write Data Bytes - numwrdatabytes
4987  *
4988  * Up to 8 Data bytes may be written using this command.
4989  *
4990  * Field Enumeration Values:
4991  *
4992  * Enum | Value | Description
4993  * :------------------------------------------|:------|:-------------
4994  * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 | 0x0 | Write 1 Byte
4995  * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 | 0x1 | Write 2 Byte
4996  * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 | 0x2 | Write 3 Byte
4997  * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 | 0x3 | Write 4 Byte
4998  * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 | 0x4 | Write 5 Byte
4999  * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 | 0x5 | Write 6 Byte
5000  * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 | 0x6 | Write 7 Byte
5001  * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 | 0x7 | Write 8 Byte
5002  *
5003  * Field Access Macros:
5004  *
5005  */
5006 /*
5007  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5008  *
5009  * Write 1 Byte
5010  */
5011 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 0x0
5012 /*
5013  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5014  *
5015  * Write 2 Byte
5016  */
5017 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 0x1
5018 /*
5019  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5020  *
5021  * Write 3 Byte
5022  */
5023 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 0x2
5024 /*
5025  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5026  *
5027  * Write 4 Byte
5028  */
5029 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 0x3
5030 /*
5031  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5032  *
5033  * Write 5 Byte
5034  */
5035 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 0x4
5036 /*
5037  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5038  *
5039  * Write 6 Byte
5040  */
5041 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 0x5
5042 /*
5043  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5044  *
5045  * Write 7 Byte
5046  */
5047 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 0x6
5048 /*
5049  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5050  *
5051  * Write 8 Byte
5052  */
5053 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 0x7
5054 
5055 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */
5056 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_LSB 12
5057 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */
5058 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_MSB 14
5059 /* The width in bits of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */
5060 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_WIDTH 3
5061 /* The mask used to set the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value. */
5062 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET_MSK 0x00007000
5063 /* The mask used to clear the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value. */
5064 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_CLR_MSK 0xffff8fff
5065 /* The reset value of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */
5066 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_RESET 0x0
5067 /* Extracts the ALT_QSPI_FLSHCMD_NUMWRDATABYTES field value from a register. */
5068 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_GET(value) (((value) & 0x00007000) >> 12)
5069 /* Produces a ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value suitable for setting the register. */
5070 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(value) (((value) << 12) & 0x00007000)
5071 
5072 /*
5073  * Field : Write Data Enable - enwrdata
5074  *
5075  * Set to 1 if the command specified in the command opcode field requires write
5076  * data bytes to be sent to the device.
5077  *
5078  * Field Enumeration Values:
5079  *
5080  * Enum | Value | Description
5081  * :----------------------------------------|:------|:----------------------------------
5082  * ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES | 0x1 | Command requires write data bytes
5083  * ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION | 0x0 | No Action
5084  *
5085  * Field Access Macros:
5086  *
5087  */
5088 /*
5089  * Enumerated value for register field ALT_QSPI_FLSHCMD_ENWRDATA
5090  *
5091  * Command requires write data bytes
5092  */
5093 #define ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES 0x1
5094 /*
5095  * Enumerated value for register field ALT_QSPI_FLSHCMD_ENWRDATA
5096  *
5097  * No Action
5098  */
5099 #define ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION 0x0
5100 
5101 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */
5102 #define ALT_QSPI_FLSHCMD_ENWRDATA_LSB 15
5103 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */
5104 #define ALT_QSPI_FLSHCMD_ENWRDATA_MSB 15
5105 /* The width in bits of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */
5106 #define ALT_QSPI_FLSHCMD_ENWRDATA_WIDTH 1
5107 /* The mask used to set the ALT_QSPI_FLSHCMD_ENWRDATA register field value. */
5108 #define ALT_QSPI_FLSHCMD_ENWRDATA_SET_MSK 0x00008000
5109 /* The mask used to clear the ALT_QSPI_FLSHCMD_ENWRDATA register field value. */
5110 #define ALT_QSPI_FLSHCMD_ENWRDATA_CLR_MSK 0xffff7fff
5111 /* The reset value of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */
5112 #define ALT_QSPI_FLSHCMD_ENWRDATA_RESET 0x0
5113 /* Extracts the ALT_QSPI_FLSHCMD_ENWRDATA field value from a register. */
5114 #define ALT_QSPI_FLSHCMD_ENWRDATA_GET(value) (((value) & 0x00008000) >> 15)
5115 /* Produces a ALT_QSPI_FLSHCMD_ENWRDATA register field value suitable for setting the register. */
5116 #define ALT_QSPI_FLSHCMD_ENWRDATA_SET(value) (((value) << 15) & 0x00008000)
5117 
5118 /*
5119  * Field : Number of Address Bytes - numaddrbytes
5120  *
5121  * Set to the number of address bytes required (the address itself is programmed in
5122  * the FLASH COMMAND ADDRESS REGISTERS). This should be setup before triggering the
5123  * command via bit 0 of this register. 2'b00 : 1 address byte 2'b01 : 2 address
5124  * bytes 2'b10 : 3 address bytes 2'b11 : 4 address bytes
5125  *
5126  * Field Enumeration Values:
5127  *
5128  * Enum | Value | Description
5129  * :------------------------------------------|:------|:----------------------
5130  * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 | 0x0 | Write 1 Address Byte
5131  * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 | 0x1 | Write 2 Address Bytes
5132  * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 | 0x2 | Write 3 Address Bytes
5133  * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 | 0x3 | Write 4 Address Bytes
5134  *
5135  * Field Access Macros:
5136  *
5137  */
5138 /*
5139  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES
5140  *
5141  * Write 1 Address Byte
5142  */
5143 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 0x0
5144 /*
5145  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES
5146  *
5147  * Write 2 Address Bytes
5148  */
5149 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 0x1
5150 /*
5151  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES
5152  *
5153  * Write 3 Address Bytes
5154  */
5155 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 0x2
5156 /*
5157  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES
5158  *
5159  * Write 4 Address Bytes
5160  */
5161 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 0x3
5162 
5163 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */
5164 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_LSB 16
5165 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */
5166 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_MSB 17
5167 /* The width in bits of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */
5168 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_WIDTH 2
5169 /* The mask used to set the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value. */
5170 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET_MSK 0x00030000
5171 /* The mask used to clear the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value. */
5172 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_CLR_MSK 0xfffcffff
5173 /* The reset value of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */
5174 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_RESET 0x0
5175 /* Extracts the ALT_QSPI_FLSHCMD_NUMADDRBYTES field value from a register. */
5176 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_GET(value) (((value) & 0x00030000) >> 16)
5177 /* Produces a ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value suitable for setting the register. */
5178 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(value) (((value) << 16) & 0x00030000)
5179 
5180 /*
5181  * Field : Mode Bit Enable - enmodebit
5182  *
5183  * Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration
5184  * register are sent following the address bytes.
5185  *
5186  * Field Enumeration Values:
5187  *
5188  * Enum | Value | Description
5189  * :---------------------------------|:------|:-------------------------------
5190  * ALT_QSPI_FLSHCMD_ENMODBIT_E_END | 0x1 | Mode Bit follows address bytes
5191  * ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD | 0x0 | No Action
5192  *
5193  * Field Access Macros:
5194  *
5195  */
5196 /*
5197  * Enumerated value for register field ALT_QSPI_FLSHCMD_ENMODBIT
5198  *
5199  * Mode Bit follows address bytes
5200  */
5201 #define ALT_QSPI_FLSHCMD_ENMODBIT_E_END 0x1
5202 /*
5203  * Enumerated value for register field ALT_QSPI_FLSHCMD_ENMODBIT
5204  *
5205  * No Action
5206  */
5207 #define ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD 0x0
5208 
5209 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */
5210 #define ALT_QSPI_FLSHCMD_ENMODBIT_LSB 18
5211 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */
5212 #define ALT_QSPI_FLSHCMD_ENMODBIT_MSB 18
5213 /* The width in bits of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */
5214 #define ALT_QSPI_FLSHCMD_ENMODBIT_WIDTH 1
5215 /* The mask used to set the ALT_QSPI_FLSHCMD_ENMODBIT register field value. */
5216 #define ALT_QSPI_FLSHCMD_ENMODBIT_SET_MSK 0x00040000
5217 /* The mask used to clear the ALT_QSPI_FLSHCMD_ENMODBIT register field value. */
5218 #define ALT_QSPI_FLSHCMD_ENMODBIT_CLR_MSK 0xfffbffff
5219 /* The reset value of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */
5220 #define ALT_QSPI_FLSHCMD_ENMODBIT_RESET 0x0
5221 /* Extracts the ALT_QSPI_FLSHCMD_ENMODBIT field value from a register. */
5222 #define ALT_QSPI_FLSHCMD_ENMODBIT_GET(value) (((value) & 0x00040000) >> 18)
5223 /* Produces a ALT_QSPI_FLSHCMD_ENMODBIT register field value suitable for setting the register. */
5224 #define ALT_QSPI_FLSHCMD_ENMODBIT_SET(value) (((value) << 18) & 0x00040000)
5225 
5226 /*
5227  * Field : Command Address Enable - encmdaddr
5228  *
5229  * If enabled, the command specified in bits 31:24 requires an address. This should
5230  * be setup before triggering the command via writing a 1 to the execute field.
5231  *
5232  * Field Enumeration Values:
5233  *
5234  * Enum | Value | Description
5235  * :----------------------------------|:------|:---------------------------------------
5236  * ALT_QSPI_FLSHCMD_ENCMDADDR_E_END | 0x1 | Command in bits 31:24 requires address
5237  * ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD | 0x0 | No Action
5238  *
5239  * Field Access Macros:
5240  *
5241  */
5242 /*
5243  * Enumerated value for register field ALT_QSPI_FLSHCMD_ENCMDADDR
5244  *
5245  * Command in bits 31:24 requires address
5246  */
5247 #define ALT_QSPI_FLSHCMD_ENCMDADDR_E_END 0x1
5248 /*
5249  * Enumerated value for register field ALT_QSPI_FLSHCMD_ENCMDADDR
5250  *
5251  * No Action
5252  */
5253 #define ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD 0x0
5254 
5255 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */
5256 #define ALT_QSPI_FLSHCMD_ENCMDADDR_LSB 19
5257 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */
5258 #define ALT_QSPI_FLSHCMD_ENCMDADDR_MSB 19
5259 /* The width in bits of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */
5260 #define ALT_QSPI_FLSHCMD_ENCMDADDR_WIDTH 1
5261 /* The mask used to set the ALT_QSPI_FLSHCMD_ENCMDADDR register field value. */
5262 #define ALT_QSPI_FLSHCMD_ENCMDADDR_SET_MSK 0x00080000
5263 /* The mask used to clear the ALT_QSPI_FLSHCMD_ENCMDADDR register field value. */
5264 #define ALT_QSPI_FLSHCMD_ENCMDADDR_CLR_MSK 0xfff7ffff
5265 /* The reset value of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */
5266 #define ALT_QSPI_FLSHCMD_ENCMDADDR_RESET 0x0
5267 /* Extracts the ALT_QSPI_FLSHCMD_ENCMDADDR field value from a register. */
5268 #define ALT_QSPI_FLSHCMD_ENCMDADDR_GET(value) (((value) & 0x00080000) >> 19)
5269 /* Produces a ALT_QSPI_FLSHCMD_ENCMDADDR register field value suitable for setting the register. */
5270 #define ALT_QSPI_FLSHCMD_ENCMDADDR_SET(value) (((value) << 19) & 0x00080000)
5271 
5272 /*
5273  * Field : Number of Read Data Bytes - numrddatabytes
5274  *
5275  * Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for
5276  * 8 bytes.
5277  *
5278  * Field Enumeration Values:
5279  *
5280  * Enum | Value | Description
5281  * :------------------------------------------|:------|:------------
5282  * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 | 0x0 | Read 1 Byte
5283  * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 | 0x1 | Read 2 Byte
5284  * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 | 0x2 | Read 3 Byte
5285  * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 | 0x3 | Read 4 Byte
5286  * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 | 0x4 | Read 5 Byte
5287  * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 | 0x5 | Read 6 Byte
5288  * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 | 0x6 | Read 7 Byte
5289  * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 | 0x7 | Read 8 Byte
5290  *
5291  * Field Access Macros:
5292  *
5293  */
5294 /*
5295  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
5296  *
5297  * Read 1 Byte
5298  */
5299 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 0x0
5300 /*
5301  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
5302  *
5303  * Read 2 Byte
5304  */
5305 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 0x1
5306 /*
5307  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
5308  *
5309  * Read 3 Byte
5310  */
5311 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 0x2
5312 /*
5313  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
5314  *
5315  * Read 4 Byte
5316  */
5317 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 0x3
5318 /*
5319  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
5320  *
5321  * Read 5 Byte
5322  */
5323 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 0x4
5324 /*
5325  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
5326  *
5327  * Read 6 Byte
5328  */
5329 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 0x5
5330 /*
5331  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
5332  *
5333  * Read 7 Byte
5334  */
5335 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 0x6
5336 /*
5337  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
5338  *
5339  * Read 8 Byte
5340  */
5341 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 0x7
5342 
5343 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */
5344 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_LSB 20
5345 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */
5346 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_MSB 22
5347 /* The width in bits of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */
5348 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_WIDTH 3
5349 /* The mask used to set the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value. */
5350 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET_MSK 0x00700000
5351 /* The mask used to clear the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value. */
5352 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_CLR_MSK 0xff8fffff
5353 /* The reset value of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */
5354 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_RESET 0x0
5355 /* Extracts the ALT_QSPI_FLSHCMD_NUMRDDATABYTES field value from a register. */
5356 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_GET(value) (((value) & 0x00700000) >> 20)
5357 /* Produces a ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value suitable for setting the register. */
5358 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(value) (((value) << 20) & 0x00700000)
5359 
5360 /*
5361  * Field : Read Data Enable - enrddata
5362  *
5363  * If enabled, the command specified in the command opcode field (bits 31:24)
5364  * requires read data bytes to be received from the device.
5365  *
5366  * Field Enumeration Values:
5367  *
5368  * Enum | Value | Description
5369  * :-------------------------------------|:------|:---------------------------
5370  * ALT_QSPI_FLSHCMD_ENRDDATA_E_EN | 0x1 | Command Requires read data
5371  * ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION | 0x0 | No Action
5372  *
5373  * Field Access Macros:
5374  *
5375  */
5376 /*
5377  * Enumerated value for register field ALT_QSPI_FLSHCMD_ENRDDATA
5378  *
5379  * Command Requires read data
5380  */
5381 #define ALT_QSPI_FLSHCMD_ENRDDATA_E_EN 0x1
5382 /*
5383  * Enumerated value for register field ALT_QSPI_FLSHCMD_ENRDDATA
5384  *
5385  * No Action
5386  */
5387 #define ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION 0x0
5388 
5389 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */
5390 #define ALT_QSPI_FLSHCMD_ENRDDATA_LSB 23
5391 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */
5392 #define ALT_QSPI_FLSHCMD_ENRDDATA_MSB 23
5393 /* The width in bits of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */
5394 #define ALT_QSPI_FLSHCMD_ENRDDATA_WIDTH 1
5395 /* The mask used to set the ALT_QSPI_FLSHCMD_ENRDDATA register field value. */
5396 #define ALT_QSPI_FLSHCMD_ENRDDATA_SET_MSK 0x00800000
5397 /* The mask used to clear the ALT_QSPI_FLSHCMD_ENRDDATA register field value. */
5398 #define ALT_QSPI_FLSHCMD_ENRDDATA_CLR_MSK 0xff7fffff
5399 /* The reset value of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */
5400 #define ALT_QSPI_FLSHCMD_ENRDDATA_RESET 0x0
5401 /* Extracts the ALT_QSPI_FLSHCMD_ENRDDATA field value from a register. */
5402 #define ALT_QSPI_FLSHCMD_ENRDDATA_GET(value) (((value) & 0x00800000) >> 23)
5403 /* Produces a ALT_QSPI_FLSHCMD_ENRDDATA register field value suitable for setting the register. */
5404 #define ALT_QSPI_FLSHCMD_ENRDDATA_SET(value) (((value) << 23) & 0x00800000)
5405 
5406 /*
5407  * Field : Command Opcode - cmdopcode
5408  *
5409  * The command opcode field should be setup before triggering the command. For
5410  * example, 0x20 maps to SubSector Erase. Writeing to the execute field (bit 0) of
5411  * this register launches the command. NOTE : Using this approach to issue commands
5412  * to the device will make use of the instruction type of the device instruction
5413  * configuration register. If this field is set to 2'b00, then the command opcode,
5414  * command address, command dummy bytes and command data will all be transferred in
5415  * a serial fashion. If this field is set to 2'b01, then the command opcode,
5416  * command address, command dummy bytes and command data will all be transferred in
5417  * parallel using DQ0 and DQ1 pins. If this field is set to 2'b10, then the command
5418  * opcode, command address, command dummy bytes and command data will all be
5419  * transferred in parallel using DQ0, DQ1, DQ2 and DQ3 pins.
5420  *
5421  * Field Access Macros:
5422  *
5423  */
5424 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */
5425 #define ALT_QSPI_FLSHCMD_CMDOPCODE_LSB 24
5426 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */
5427 #define ALT_QSPI_FLSHCMD_CMDOPCODE_MSB 31
5428 /* The width in bits of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */
5429 #define ALT_QSPI_FLSHCMD_CMDOPCODE_WIDTH 8
5430 /* The mask used to set the ALT_QSPI_FLSHCMD_CMDOPCODE register field value. */
5431 #define ALT_QSPI_FLSHCMD_CMDOPCODE_SET_MSK 0xff000000
5432 /* The mask used to clear the ALT_QSPI_FLSHCMD_CMDOPCODE register field value. */
5433 #define ALT_QSPI_FLSHCMD_CMDOPCODE_CLR_MSK 0x00ffffff
5434 /* The reset value of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */
5435 #define ALT_QSPI_FLSHCMD_CMDOPCODE_RESET 0x0
5436 /* Extracts the ALT_QSPI_FLSHCMD_CMDOPCODE field value from a register. */
5437 #define ALT_QSPI_FLSHCMD_CMDOPCODE_GET(value) (((value) & 0xff000000) >> 24)
5438 /* Produces a ALT_QSPI_FLSHCMD_CMDOPCODE register field value suitable for setting the register. */
5439 #define ALT_QSPI_FLSHCMD_CMDOPCODE_SET(value) (((value) << 24) & 0xff000000)
5440 
5441 #ifndef __ASSEMBLY__
5442 /*
5443  * WARNING: The C register and register group struct declarations are provided for
5444  * convenience and illustrative purposes. They should, however, be used with
5445  * caution as the C language standard provides no guarantees about the alignment or
5446  * atomicity of device memory accesses. The recommended practice for writing
5447  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5448  * alt_write_word() functions.
5449  *
5450  * The struct declaration for register ALT_QSPI_FLSHCMD.
5451  */
5452 struct ALT_QSPI_FLSHCMD_s
5453 {
5454  uint32_t execcmd : 1; /* Execute Command */
5455  const uint32_t cmdexecstat : 1; /* Command Execution Status */
5456  uint32_t : 5; /* *UNDEFINED* */
5457  uint32_t numdummybytes : 5; /* Number of Dummy Bytes */
5458  uint32_t numwrdatabytes : 3; /* Number of Write Data Bytes */
5459  uint32_t enwrdata : 1; /* Write Data Enable */
5460  uint32_t numaddrbytes : 2; /* Number of Address Bytes */
5461  uint32_t enmodebit : 1; /* Mode Bit Enable */
5462  uint32_t encmdaddr : 1; /* Command Address Enable */
5463  uint32_t numrddatabytes : 3; /* Number of Read Data Bytes */
5464  uint32_t enrddata : 1; /* Read Data Enable */
5465  uint32_t cmdopcode : 8; /* Command Opcode */
5466 };
5467 
5468 /* The typedef declaration for register ALT_QSPI_FLSHCMD. */
5469 typedef volatile struct ALT_QSPI_FLSHCMD_s ALT_QSPI_FLSHCMD_t;
5470 #endif /* __ASSEMBLY__ */
5471 
5472 /* The byte offset of the ALT_QSPI_FLSHCMD register from the beginning of the component. */
5473 #define ALT_QSPI_FLSHCMD_OFST 0x90
5474 
5475 /*
5476  * Register : Flash Command Address Registers - flashcmdaddr
5477  *
5478  * Register Layout
5479  *
5480  * Bits | Access | Reset | Description
5481  * :-------|:-------|:------|:----------------
5482  * [31:0] | RW | 0x0 | Command Address
5483  *
5484  */
5485 /*
5486  * Field : Command Address - addr
5487  *
5488  * This should be setup before triggering the command with execute field (bit 0) of
5489  * the Flash Command Control register. It is the address used by the command
5490  * specified in the opcode field (bits 31:24) of the Flash Command Control
5491  * register.
5492  *
5493  * Field Access Macros:
5494  *
5495  */
5496 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */
5497 #define ALT_QSPI_FLSHCMDADDR_ADDR_LSB 0
5498 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */
5499 #define ALT_QSPI_FLSHCMDADDR_ADDR_MSB 31
5500 /* The width in bits of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */
5501 #define ALT_QSPI_FLSHCMDADDR_ADDR_WIDTH 32
5502 /* The mask used to set the ALT_QSPI_FLSHCMDADDR_ADDR register field value. */
5503 #define ALT_QSPI_FLSHCMDADDR_ADDR_SET_MSK 0xffffffff
5504 /* The mask used to clear the ALT_QSPI_FLSHCMDADDR_ADDR register field value. */
5505 #define ALT_QSPI_FLSHCMDADDR_ADDR_CLR_MSK 0x00000000
5506 /* The reset value of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */
5507 #define ALT_QSPI_FLSHCMDADDR_ADDR_RESET 0x0
5508 /* Extracts the ALT_QSPI_FLSHCMDADDR_ADDR field value from a register. */
5509 #define ALT_QSPI_FLSHCMDADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
5510 /* Produces a ALT_QSPI_FLSHCMDADDR_ADDR register field value suitable for setting the register. */
5511 #define ALT_QSPI_FLSHCMDADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
5512 
5513 #ifndef __ASSEMBLY__
5514 /*
5515  * WARNING: The C register and register group struct declarations are provided for
5516  * convenience and illustrative purposes. They should, however, be used with
5517  * caution as the C language standard provides no guarantees about the alignment or
5518  * atomicity of device memory accesses. The recommended practice for writing
5519  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5520  * alt_write_word() functions.
5521  *
5522  * The struct declaration for register ALT_QSPI_FLSHCMDADDR.
5523  */
5524 struct ALT_QSPI_FLSHCMDADDR_s
5525 {
5526  uint32_t addr : 32; /* Command Address */
5527 };
5528 
5529 /* The typedef declaration for register ALT_QSPI_FLSHCMDADDR. */
5530 typedef volatile struct ALT_QSPI_FLSHCMDADDR_s ALT_QSPI_FLSHCMDADDR_t;
5531 #endif /* __ASSEMBLY__ */
5532 
5533 /* The byte offset of the ALT_QSPI_FLSHCMDADDR register from the beginning of the component. */
5534 #define ALT_QSPI_FLSHCMDADDR_OFST 0x94
5535 
5536 /*
5537  * Register : Flash Command Read Data Register (Lower) - flashcmdrddatalo
5538  *
5539  * Register Layout
5540  *
5541  * Bits | Access | Reset | Description
5542  * :-------|:-------|:------|:-------------------------------
5543  * [31:0] | RW | 0x0 | Command Read Data (Lower byte)
5544  *
5545  */
5546 /*
5547  * Field : Command Read Data (Lower byte) - data
5548  *
5549  * This is the data that is returned by the flash device for any status or
5550  * configuration read operation carried out by triggering the event in the control
5551  * register. The register will be valid when the polling bit in the control
5552  * register is low.
5553  *
5554  * Field Access Macros:
5555  *
5556  */
5557 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */
5558 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_LSB 0
5559 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */
5560 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_MSB 31
5561 /* The width in bits of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */
5562 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_WIDTH 32
5563 /* The mask used to set the ALT_QSPI_FLSHCMDRDDATALO_DATA register field value. */
5564 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET_MSK 0xffffffff
5565 /* The mask used to clear the ALT_QSPI_FLSHCMDRDDATALO_DATA register field value. */
5566 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_CLR_MSK 0x00000000
5567 /* The reset value of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */
5568 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_RESET 0x0
5569 /* Extracts the ALT_QSPI_FLSHCMDRDDATALO_DATA field value from a register. */
5570 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)
5571 /* Produces a ALT_QSPI_FLSHCMDRDDATALO_DATA register field value suitable for setting the register. */
5572 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)
5573 
5574 #ifndef __ASSEMBLY__
5575 /*
5576  * WARNING: The C register and register group struct declarations are provided for
5577  * convenience and illustrative purposes. They should, however, be used with
5578  * caution as the C language standard provides no guarantees about the alignment or
5579  * atomicity of device memory accesses. The recommended practice for writing
5580  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5581  * alt_write_word() functions.
5582  *
5583  * The struct declaration for register ALT_QSPI_FLSHCMDRDDATALO.
5584  */
5585 struct ALT_QSPI_FLSHCMDRDDATALO_s
5586 {
5587  uint32_t data : 32; /* Command Read Data (Lower byte) */
5588 };
5589 
5590 /* The typedef declaration for register ALT_QSPI_FLSHCMDRDDATALO. */
5591 typedef volatile struct ALT_QSPI_FLSHCMDRDDATALO_s ALT_QSPI_FLSHCMDRDDATALO_t;
5592 #endif /* __ASSEMBLY__ */
5593 
5594 /* The byte offset of the ALT_QSPI_FLSHCMDRDDATALO register from the beginning of the component. */
5595 #define ALT_QSPI_FLSHCMDRDDATALO_OFST 0xa0
5596 
5597 /*
5598  * Register : Flash Command Read Data Register (Upper) - flashcmdrddataup
5599  *
5600  * Device Instruction Register
5601  *
5602  * Register Layout
5603  *
5604  * Bits | Access | Reset | Description
5605  * :-------|:-------|:------|:-------------------------------
5606  * [31:0] | RW | 0x0 | Command Read Data (Upper byte)
5607  *
5608  */
5609 /*
5610  * Field : Command Read Data (Upper byte) - data
5611  *
5612  * This is the data that is returned by the FLASH device for any status or
5613  * configuration read operation carried out by triggering the event in the control
5614  * register. The register will be valid when the polling bit in the control
5615  * register is low.
5616  *
5617  * Field Access Macros:
5618  *
5619  */
5620 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */
5621 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_LSB 0
5622 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */
5623 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_MSB 31
5624 /* The width in bits of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */
5625 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_WIDTH 32
5626 /* The mask used to set the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value. */
5627 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET_MSK 0xffffffff
5628 /* The mask used to clear the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value. */
5629 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_CLR_MSK 0x00000000
5630 /* The reset value of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */
5631 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_RESET 0x0
5632 /* Extracts the ALT_QSPI_FLSHCMDRDDATAUP_DATA field value from a register. */
5633 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)
5634 /* Produces a ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value suitable for setting the register. */
5635 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)
5636 
5637 #ifndef __ASSEMBLY__
5638 /*
5639  * WARNING: The C register and register group struct declarations are provided for
5640  * convenience and illustrative purposes. They should, however, be used with
5641  * caution as the C language standard provides no guarantees about the alignment or
5642  * atomicity of device memory accesses. The recommended practice for writing
5643  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5644  * alt_write_word() functions.
5645  *
5646  * The struct declaration for register ALT_QSPI_FLSHCMDRDDATAUP.
5647  */
5648 struct ALT_QSPI_FLSHCMDRDDATAUP_s
5649 {
5650  uint32_t data : 32; /* Command Read Data (Upper byte) */
5651 };
5652 
5653 /* The typedef declaration for register ALT_QSPI_FLSHCMDRDDATAUP. */
5654 typedef volatile struct ALT_QSPI_FLSHCMDRDDATAUP_s ALT_QSPI_FLSHCMDRDDATAUP_t;
5655 #endif /* __ASSEMBLY__ */
5656 
5657 /* The byte offset of the ALT_QSPI_FLSHCMDRDDATAUP register from the beginning of the component. */
5658 #define ALT_QSPI_FLSHCMDRDDATAUP_OFST 0xa4
5659 
5660 /*
5661  * Register : Flash Command Write Data Register (Lower) - flashcmdwrdatalo
5662  *
5663  * Register Layout
5664  *
5665  * Bits | Access | Reset | Description
5666  * :-------|:-------|:------|:------------------------------
5667  * [31:0] | RW | 0x0 | Command Write Data Lower Byte
5668  *
5669  */
5670 /*
5671  * Field : Command Write Data Lower Byte - data
5672  *
5673  * This is the command write data lower byte. This should be setup before
5674  * triggering the command with execute field (bit 0) of the Flash Command Control
5675  * register. It is the data that is to be written to the flash for any status or
5676  * configuration write operation carried out by triggering the event in the Flash
5677  * Command Control register.
5678  *
5679  * Field Access Macros:
5680  *
5681  */
5682 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */
5683 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_LSB 0
5684 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */
5685 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_MSB 31
5686 /* The width in bits of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */
5687 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_WIDTH 32
5688 /* The mask used to set the ALT_QSPI_FLSHCMDWRDATALO_DATA register field value. */
5689 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET_MSK 0xffffffff
5690 /* The mask used to clear the ALT_QSPI_FLSHCMDWRDATALO_DATA register field value. */
5691 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_CLR_MSK 0x00000000
5692 /* The reset value of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */
5693 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_RESET 0x0
5694 /* Extracts the ALT_QSPI_FLSHCMDWRDATALO_DATA field value from a register. */
5695 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)
5696 /* Produces a ALT_QSPI_FLSHCMDWRDATALO_DATA register field value suitable for setting the register. */
5697 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)
5698 
5699 #ifndef __ASSEMBLY__
5700 /*
5701  * WARNING: The C register and register group struct declarations are provided for
5702  * convenience and illustrative purposes. They should, however, be used with
5703  * caution as the C language standard provides no guarantees about the alignment or
5704  * atomicity of device memory accesses. The recommended practice for writing
5705  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5706  * alt_write_word() functions.
5707  *
5708  * The struct declaration for register ALT_QSPI_FLSHCMDWRDATALO.
5709  */
5710 struct ALT_QSPI_FLSHCMDWRDATALO_s
5711 {
5712  uint32_t data : 32; /* Command Write Data Lower Byte */
5713 };
5714 
5715 /* The typedef declaration for register ALT_QSPI_FLSHCMDWRDATALO. */
5716 typedef volatile struct ALT_QSPI_FLSHCMDWRDATALO_s ALT_QSPI_FLSHCMDWRDATALO_t;
5717 #endif /* __ASSEMBLY__ */
5718 
5719 /* The byte offset of the ALT_QSPI_FLSHCMDWRDATALO register from the beginning of the component. */
5720 #define ALT_QSPI_FLSHCMDWRDATALO_OFST 0xa8
5721 
5722 /*
5723  * Register : Flash Command Write Data Register (Upper) - flashcmdwrdataup
5724  *
5725  * Register Layout
5726  *
5727  * Bits | Access | Reset | Description
5728  * :-------|:-------|:------|:------------------------------
5729  * [31:0] | RW | 0x0 | ALT_QSPI_FLSHCMDWRDATAUP_DATA
5730  *
5731  */
5732 /*
5733  * Field : data
5734  *
5735  * This is the command write data upper byte. This should be setup before
5736  * triggering the command with execute field (bit 0) of the Flash Command Control
5737  * register. It is the data that is to be written to the flash for any status or
5738  * configuration write operation carried out by triggering the event in the Flash
5739  * Command Control register.
5740  *
5741  * Field Access Macros:
5742  *
5743  */
5744 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */
5745 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_LSB 0
5746 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */
5747 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_MSB 31
5748 /* The width in bits of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */
5749 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_WIDTH 32
5750 /* The mask used to set the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value. */
5751 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET_MSK 0xffffffff
5752 /* The mask used to clear the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value. */
5753 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_CLR_MSK 0x00000000
5754 /* The reset value of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */
5755 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_RESET 0x0
5756 /* Extracts the ALT_QSPI_FLSHCMDWRDATAUP_DATA field value from a register. */
5757 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)
5758 /* Produces a ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value suitable for setting the register. */
5759 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)
5760 
5761 #ifndef __ASSEMBLY__
5762 /*
5763  * WARNING: The C register and register group struct declarations are provided for
5764  * convenience and illustrative purposes. They should, however, be used with
5765  * caution as the C language standard provides no guarantees about the alignment or
5766  * atomicity of device memory accesses. The recommended practice for writing
5767  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5768  * alt_write_word() functions.
5769  *
5770  * The struct declaration for register ALT_QSPI_FLSHCMDWRDATAUP.
5771  */
5772 struct ALT_QSPI_FLSHCMDWRDATAUP_s
5773 {
5774  uint32_t data : 32; /* ALT_QSPI_FLSHCMDWRDATAUP_DATA */
5775 };
5776 
5777 /* The typedef declaration for register ALT_QSPI_FLSHCMDWRDATAUP. */
5778 typedef volatile struct ALT_QSPI_FLSHCMDWRDATAUP_s ALT_QSPI_FLSHCMDWRDATAUP_t;
5779 #endif /* __ASSEMBLY__ */
5780 
5781 /* The byte offset of the ALT_QSPI_FLSHCMDWRDATAUP register from the beginning of the component. */
5782 #define ALT_QSPI_FLSHCMDWRDATAUP_OFST 0xac
5783 
5784 /*
5785  * Register : Module ID Register - moduleid
5786  *
5787  * Register Layout
5788  *
5789  * Bits | Access | Reset | Description
5790  * :--------|:-------|:-------|:-----------------
5791  * [24:0] | R | 0x1001 | Module ID number
5792  * [31:25] | ??? | 0x0 | *UNDEFINED*
5793  *
5794  */
5795 /*
5796  * Field : Module ID number - value
5797  *
5798  * Field Access Macros:
5799  *
5800  */
5801 /* The Least Significant Bit (LSB) position of the ALT_QSPI_MODULEID_VALUE register field. */
5802 #define ALT_QSPI_MODULEID_VALUE_LSB 0
5803 /* The Most Significant Bit (MSB) position of the ALT_QSPI_MODULEID_VALUE register field. */
5804 #define ALT_QSPI_MODULEID_VALUE_MSB 24
5805 /* The width in bits of the ALT_QSPI_MODULEID_VALUE register field. */
5806 #define ALT_QSPI_MODULEID_VALUE_WIDTH 25
5807 /* The mask used to set the ALT_QSPI_MODULEID_VALUE register field value. */
5808 #define ALT_QSPI_MODULEID_VALUE_SET_MSK 0x01ffffff
5809 /* The mask used to clear the ALT_QSPI_MODULEID_VALUE register field value. */
5810 #define ALT_QSPI_MODULEID_VALUE_CLR_MSK 0xfe000000
5811 /* The reset value of the ALT_QSPI_MODULEID_VALUE register field. */
5812 #define ALT_QSPI_MODULEID_VALUE_RESET 0x1001
5813 /* Extracts the ALT_QSPI_MODULEID_VALUE field value from a register. */
5814 #define ALT_QSPI_MODULEID_VALUE_GET(value) (((value) & 0x01ffffff) >> 0)
5815 /* Produces a ALT_QSPI_MODULEID_VALUE register field value suitable for setting the register. */
5816 #define ALT_QSPI_MODULEID_VALUE_SET(value) (((value) << 0) & 0x01ffffff)
5817 
5818 #ifndef __ASSEMBLY__
5819 /*
5820  * WARNING: The C register and register group struct declarations are provided for
5821  * convenience and illustrative purposes. They should, however, be used with
5822  * caution as the C language standard provides no guarantees about the alignment or
5823  * atomicity of device memory accesses. The recommended practice for writing
5824  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5825  * alt_write_word() functions.
5826  *
5827  * The struct declaration for register ALT_QSPI_MODULEID.
5828  */
5829 struct ALT_QSPI_MODULEID_s
5830 {
5831  const uint32_t value : 25; /* Module ID number */
5832  uint32_t : 7; /* *UNDEFINED* */
5833 };
5834 
5835 /* The typedef declaration for register ALT_QSPI_MODULEID. */
5836 typedef volatile struct ALT_QSPI_MODULEID_s ALT_QSPI_MODULEID_t;
5837 #endif /* __ASSEMBLY__ */
5838 
5839 /* The byte offset of the ALT_QSPI_MODULEID register from the beginning of the component. */
5840 #define ALT_QSPI_MODULEID_OFST 0xfc
5841 
5842 #ifndef __ASSEMBLY__
5843 /*
5844  * WARNING: The C register and register group struct declarations are provided for
5845  * convenience and illustrative purposes. They should, however, be used with
5846  * caution as the C language standard provides no guarantees about the alignment or
5847  * atomicity of device memory accesses. The recommended practice for writing
5848  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5849  * alt_write_word() functions.
5850  *
5851  * The struct declaration for register group ALT_QSPI.
5852  */
5853 struct ALT_QSPI_s
5854 {
5855  ALT_QSPI_CFG_t cfg; /* ALT_QSPI_CFG */
5856  ALT_QSPI_DEVRD_t devrd; /* ALT_QSPI_DEVRD */
5857  ALT_QSPI_DEVWR_t devwr; /* ALT_QSPI_DEVWR */
5858  ALT_QSPI_DELAY_t delay; /* ALT_QSPI_DELAY */
5859  ALT_QSPI_RDDATACAP_t rddatacap; /* ALT_QSPI_RDDATACAP */
5860  ALT_QSPI_DEVSZ_t devsz; /* ALT_QSPI_DEVSZ */
5861  ALT_QSPI_SRAMPART_t srampart; /* ALT_QSPI_SRAMPART */
5862  ALT_QSPI_INDADDRTRIG_t indaddrtrig; /* ALT_QSPI_INDADDRTRIG */
5863  ALT_QSPI_DMAPER_t dmaper; /* ALT_QSPI_DMAPER */
5864  ALT_QSPI_REMAPADDR_t remapaddr; /* ALT_QSPI_REMAPADDR */
5865  ALT_QSPI_MODBIT_t modebit; /* ALT_QSPI_MODBIT */
5866  ALT_QSPI_SRAMFILL_t sramfill; /* ALT_QSPI_SRAMFILL */
5867  ALT_QSPI_TXTHRESH_t txthresh; /* ALT_QSPI_TXTHRESH */
5868  ALT_QSPI_RXTHRESH_t rxthresh; /* ALT_QSPI_RXTHRESH */
5869  volatile uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */
5870  ALT_QSPI_IRQSTAT_t irqstat; /* ALT_QSPI_IRQSTAT */
5871  ALT_QSPI_IRQMSK_t irqmask; /* ALT_QSPI_IRQMSK */
5872  volatile uint32_t _pad_0x48_0x4f[2]; /* *UNDEFINED* */
5873  ALT_QSPI_LOWWRPROT_t lowwrprot; /* ALT_QSPI_LOWWRPROT */
5874  ALT_QSPI_UPPWRPROT_t uppwrprot; /* ALT_QSPI_UPPWRPROT */
5875  ALT_QSPI_WRPROT_t wrprot; /* ALT_QSPI_WRPROT */
5876  volatile uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */
5877  ALT_QSPI_INDRD_t indrd; /* ALT_QSPI_INDRD */
5878  ALT_QSPI_INDRDWATER_t indrdwater; /* ALT_QSPI_INDRDWATER */
5879  ALT_QSPI_INDRDSTADDR_t indrdstaddr; /* ALT_QSPI_INDRDSTADDR */
5880  ALT_QSPI_INDRDCNT_t indrdcnt; /* ALT_QSPI_INDRDCNT */
5881  ALT_QSPI_INDWR_t indwr; /* ALT_QSPI_INDWR */
5882  ALT_QSPI_INDWRWATER_t indwrwater; /* ALT_QSPI_INDWRWATER */
5883  ALT_QSPI_INDWRSTADDR_t indwrstaddr; /* ALT_QSPI_INDWRSTADDR */
5884  ALT_QSPI_INDWRCNT_t indwrcnt; /* ALT_QSPI_INDWRCNT */
5885  volatile uint32_t _pad_0x80_0x8f[4]; /* *UNDEFINED* */
5886  ALT_QSPI_FLSHCMD_t flashcmd; /* ALT_QSPI_FLSHCMD */
5887  ALT_QSPI_FLSHCMDADDR_t flashcmdaddr; /* ALT_QSPI_FLSHCMDADDR */
5888  volatile uint32_t _pad_0x98_0x9f[2]; /* *UNDEFINED* */
5889  ALT_QSPI_FLSHCMDRDDATALO_t flashcmdrddatalo; /* ALT_QSPI_FLSHCMDRDDATALO */
5890  ALT_QSPI_FLSHCMDRDDATAUP_t flashcmdrddataup; /* ALT_QSPI_FLSHCMDRDDATAUP */
5891  ALT_QSPI_FLSHCMDWRDATALO_t flashcmdwrdatalo; /* ALT_QSPI_FLSHCMDWRDATALO */
5892  ALT_QSPI_FLSHCMDWRDATAUP_t flashcmdwrdataup; /* ALT_QSPI_FLSHCMDWRDATAUP */
5893  volatile uint32_t _pad_0xb0_0xfb[19]; /* *UNDEFINED* */
5894  ALT_QSPI_MODULEID_t moduleid; /* ALT_QSPI_MODULEID */
5895 };
5896 
5897 /* The typedef declaration for register group ALT_QSPI. */
5898 typedef volatile struct ALT_QSPI_s ALT_QSPI_t;
5899 /* The struct declaration for the raw register contents of register group ALT_QSPI. */
5900 struct ALT_QSPI_raw_s
5901 {
5902  volatile uint32_t cfg; /* ALT_QSPI_CFG */
5903  volatile uint32_t devrd; /* ALT_QSPI_DEVRD */
5904  volatile uint32_t devwr; /* ALT_QSPI_DEVWR */
5905  volatile uint32_t delay; /* ALT_QSPI_DELAY */
5906  volatile uint32_t rddatacap; /* ALT_QSPI_RDDATACAP */
5907  volatile uint32_t devsz; /* ALT_QSPI_DEVSZ */
5908  volatile uint32_t srampart; /* ALT_QSPI_SRAMPART */
5909  volatile uint32_t indaddrtrig; /* ALT_QSPI_INDADDRTRIG */
5910  volatile uint32_t dmaper; /* ALT_QSPI_DMAPER */
5911  volatile uint32_t remapaddr; /* ALT_QSPI_REMAPADDR */
5912  volatile uint32_t modebit; /* ALT_QSPI_MODBIT */
5913  volatile uint32_t sramfill; /* ALT_QSPI_SRAMFILL */
5914  volatile uint32_t txthresh; /* ALT_QSPI_TXTHRESH */
5915  volatile uint32_t rxthresh; /* ALT_QSPI_RXTHRESH */
5916  uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */
5917  volatile uint32_t irqstat; /* ALT_QSPI_IRQSTAT */
5918  volatile uint32_t irqmask; /* ALT_QSPI_IRQMSK */
5919  uint32_t _pad_0x48_0x4f[2]; /* *UNDEFINED* */
5920  volatile uint32_t lowwrprot; /* ALT_QSPI_LOWWRPROT */
5921  volatile uint32_t uppwrprot; /* ALT_QSPI_UPPWRPROT */
5922  volatile uint32_t wrprot; /* ALT_QSPI_WRPROT */
5923  uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */
5924  volatile uint32_t indrd; /* ALT_QSPI_INDRD */
5925  volatile uint32_t indrdwater; /* ALT_QSPI_INDRDWATER */
5926  volatile uint32_t indrdstaddr; /* ALT_QSPI_INDRDSTADDR */
5927  volatile uint32_t indrdcnt; /* ALT_QSPI_INDRDCNT */
5928  volatile uint32_t indwr; /* ALT_QSPI_INDWR */
5929  volatile uint32_t indwrwater; /* ALT_QSPI_INDWRWATER */
5930  volatile uint32_t indwrstaddr; /* ALT_QSPI_INDWRSTADDR */
5931  volatile uint32_t indwrcnt; /* ALT_QSPI_INDWRCNT */
5932  uint32_t _pad_0x80_0x8f[4]; /* *UNDEFINED* */
5933  volatile uint32_t flashcmd; /* ALT_QSPI_FLSHCMD */
5934  volatile uint32_t flashcmdaddr; /* ALT_QSPI_FLSHCMDADDR */
5935  uint32_t _pad_0x98_0x9f[2]; /* *UNDEFINED* */
5936  volatile uint32_t flashcmdrddatalo; /* ALT_QSPI_FLSHCMDRDDATALO */
5937  volatile uint32_t flashcmdrddataup; /* ALT_QSPI_FLSHCMDRDDATAUP */
5938  volatile uint32_t flashcmdwrdatalo; /* ALT_QSPI_FLSHCMDWRDATALO */
5939  volatile uint32_t flashcmdwrdataup; /* ALT_QSPI_FLSHCMDWRDATAUP */
5940  uint32_t _pad_0xb0_0xfb[19]; /* *UNDEFINED* */
5941  volatile uint32_t moduleid; /* ALT_QSPI_MODULEID */
5942 };
5943 
5944 /* The typedef declaration for the raw register contents of register group ALT_QSPI. */
5945 typedef volatile struct ALT_QSPI_raw_s ALT_QSPI_raw_t;
5946 #endif /* __ASSEMBLY__ */
5947 
5948 
5949 #ifdef __cplusplus
5950 }
5951 #endif /* __cplusplus */
5952 #endif /* __ALTERA_ALT_QSPI_H__ */
5953