35 #ifndef __ALT_SOCAL_IO48_HMC_MMR_H__
36 #define __ALT_SOCAL_IO48_HMC_MMR_H__
77 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_LSB 0
79 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_MSB 0
81 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_WIDTH 1
83 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_SET_MSK 0x00000001
85 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_CLR_MSK 0xfffffffe
87 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_RESET 0x0
89 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_GET(value) (((value) & 0x00000001) >> 0)
91 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_SET(value) (((value) << 0) & 0x00000001)
102 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_LSB 1
104 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_MSB 1
106 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_WIDTH 1
108 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_SET_MSK 0x00000002
110 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_CLR_MSK 0xfffffffd
112 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_RESET 0x0
114 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_GET(value) (((value) & 0x00000002) >> 1)
116 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_SET(value) (((value) << 1) & 0x00000002)
127 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_LSB 2
129 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_MSB 2
131 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_WIDTH 1
133 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_SET_MSK 0x00000004
135 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_CLR_MSK 0xfffffffb
137 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_RESET 0x0
139 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_GET(value) (((value) & 0x00000004) >> 2)
141 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_SET(value) (((value) << 2) & 0x00000004)
152 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_LSB 3
154 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_MSB 3
156 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_WIDTH 1
158 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_SET_MSK 0x00000008
160 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_CLR_MSK 0xfffffff7
162 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_RESET 0x0
164 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_GET(value) (((value) & 0x00000008) >> 3)
166 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_SET(value) (((value) << 3) & 0x00000008)
177 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_LSB 4
179 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_MSB 4
181 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_WIDTH 1
183 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_SET_MSK 0x00000010
185 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_CLR_MSK 0xffffffef
187 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_RESET 0x0
189 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_GET(value) (((value) & 0x00000010) >> 4)
191 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_SET(value) (((value) << 4) & 0x00000010)
202 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_LSB 5
204 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_MSB 8
206 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_WIDTH 4
208 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_SET_MSK 0x000001e0
210 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_CLR_MSK 0xfffffe1f
212 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_RESET 0x0
214 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_GET(value) (((value) & 0x000001e0) >> 5)
216 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_SET(value) (((value) << 5) & 0x000001e0)
229 struct ALT_IO48_HMC_MMR_DBGCFG0_s
231 uint32_t cfg_wdata_driver_sel : 1;
232 uint32_t cfg_prbs_ctrl_sel : 1;
233 uint32_t cfg_mmr_driver_sel : 1;
234 uint32_t cfg_loopback_en : 1;
235 uint32_t cfg_cmd_driver_sel : 1;
236 uint32_t cfg_dbg_mode : 4;
241 typedef volatile struct ALT_IO48_HMC_MMR_DBGCFG0_s ALT_IO48_HMC_MMR_DBGCFG0_t;
245 #define ALT_IO48_HMC_MMR_DBGCFG0_RESET 0x00000000
247 #define ALT_IO48_HMC_MMR_DBGCFG0_OFST 0x0
268 #define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_LSB 0
270 #define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_MSB 31
272 #define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_WIDTH 32
274 #define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_SET_MSK 0xffffffff
276 #define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_CLR_MSK 0x00000000
278 #define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_RESET 0x0
280 #define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_GET(value) (((value) & 0xffffffff) >> 0)
282 #define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_SET(value) (((value) << 0) & 0xffffffff)
295 struct ALT_IO48_HMC_MMR_DBGCFG1_s
297 uint32_t cfg_dbg_ctrl : 32;
301 typedef volatile struct ALT_IO48_HMC_MMR_DBGCFG1_s ALT_IO48_HMC_MMR_DBGCFG1_t;
305 #define ALT_IO48_HMC_MMR_DBGCFG1_RESET 0x00000000
307 #define ALT_IO48_HMC_MMR_DBGCFG1_OFST 0x4
328 #define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_LSB 0
330 #define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_MSB 31
332 #define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_WIDTH 32
334 #define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_SET_MSK 0xffffffff
336 #define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_CLR_MSK 0x00000000
338 #define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_RESET 0x0
340 #define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_GET(value) (((value) & 0xffffffff) >> 0)
342 #define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_SET(value) (((value) << 0) & 0xffffffff)
355 struct ALT_IO48_HMC_MMR_DBGCFG2_s
357 uint32_t cfg_bist_cmd0_u : 32;
361 typedef volatile struct ALT_IO48_HMC_MMR_DBGCFG2_s ALT_IO48_HMC_MMR_DBGCFG2_t;
365 #define ALT_IO48_HMC_MMR_DBGCFG2_RESET 0x00000000
367 #define ALT_IO48_HMC_MMR_DBGCFG2_OFST 0x8
388 #define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_LSB 0
390 #define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_MSB 31
392 #define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_WIDTH 32
394 #define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_SET_MSK 0xffffffff
396 #define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_CLR_MSK 0x00000000
398 #define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_RESET 0x0
400 #define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_GET(value) (((value) & 0xffffffff) >> 0)
402 #define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_SET(value) (((value) << 0) & 0xffffffff)
415 struct ALT_IO48_HMC_MMR_DBGCFG3_s
417 uint32_t cfg_bist_cmd0_l : 32;
421 typedef volatile struct ALT_IO48_HMC_MMR_DBGCFG3_s ALT_IO48_HMC_MMR_DBGCFG3_t;
425 #define ALT_IO48_HMC_MMR_DBGCFG3_RESET 0x00000000
427 #define ALT_IO48_HMC_MMR_DBGCFG3_OFST 0xc
448 #define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_LSB 0
450 #define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_MSB 31
452 #define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_WIDTH 32
454 #define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_SET_MSK 0xffffffff
456 #define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_CLR_MSK 0x00000000
458 #define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_RESET 0x0
460 #define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_GET(value) (((value) & 0xffffffff) >> 0)
462 #define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_SET(value) (((value) << 0) & 0xffffffff)
475 struct ALT_IO48_HMC_MMR_DBGCFG4_s
477 uint32_t cfg_bist_cmd1_u : 32;
481 typedef volatile struct ALT_IO48_HMC_MMR_DBGCFG4_s ALT_IO48_HMC_MMR_DBGCFG4_t;
485 #define ALT_IO48_HMC_MMR_DBGCFG4_RESET 0x00000000
487 #define ALT_IO48_HMC_MMR_DBGCFG4_OFST 0x10
508 #define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_LSB 0
510 #define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_MSB 31
512 #define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_WIDTH 32
514 #define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_SET_MSK 0xffffffff
516 #define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_CLR_MSK 0x00000000
518 #define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_RESET 0x0
520 #define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_GET(value) (((value) & 0xffffffff) >> 0)
522 #define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_SET(value) (((value) << 0) & 0xffffffff)
535 struct ALT_IO48_HMC_MMR_DBGCFG5_s
537 uint32_t cfg_bist_cmd1_l : 32;
541 typedef volatile struct ALT_IO48_HMC_MMR_DBGCFG5_s ALT_IO48_HMC_MMR_DBGCFG5_t;
545 #define ALT_IO48_HMC_MMR_DBGCFG5_RESET 0x00000000
547 #define ALT_IO48_HMC_MMR_DBGCFG5_OFST 0x14
569 #define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_LSB 0
571 #define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_MSB 15
573 #define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_WIDTH 16
575 #define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_SET_MSK 0x0000ffff
577 #define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_CLR_MSK 0xffff0000
579 #define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_RESET 0x0
581 #define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_GET(value) (((value) & 0x0000ffff) >> 0)
583 #define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_SET(value) (((value) << 0) & 0x0000ffff)
596 struct ALT_IO48_HMC_MMR_DBGCFG6_s
598 uint32_t cfg_dbg_out_sel : 16;
603 typedef volatile struct ALT_IO48_HMC_MMR_DBGCFG6_s ALT_IO48_HMC_MMR_DBGCFG6_t;
607 #define ALT_IO48_HMC_MMR_DBGCFG6_RESET 0x00000000
609 #define ALT_IO48_HMC_MMR_DBGCFG6_OFST 0x18
631 #define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_LSB 0
633 #define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_MSB 15
635 #define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_WIDTH 16
637 #define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_SET_MSK 0x0000ffff
639 #define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_CLR_MSK 0xffff0000
641 #define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_RESET 0x0
643 #define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_GET(value) (((value) & 0x0000ffff) >> 0)
645 #define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_SET(value) (((value) << 0) & 0x0000ffff)
658 struct ALT_IO48_HMC_MMR_RESERVE0_s
660 uint32_t cfg_reserve0 : 16;
665 typedef volatile struct ALT_IO48_HMC_MMR_RESERVE0_s ALT_IO48_HMC_MMR_RESERVE0_t;
669 #define ALT_IO48_HMC_MMR_RESERVE0_RESET 0x00000000
671 #define ALT_IO48_HMC_MMR_RESERVE0_OFST 0x1c
693 #define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_LSB 0
695 #define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_MSB 15
697 #define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_WIDTH 16
699 #define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_SET_MSK 0x0000ffff
701 #define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_CLR_MSK 0xffff0000
703 #define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_RESET 0x0
705 #define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_GET(value) (((value) & 0x0000ffff) >> 0)
707 #define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_SET(value) (((value) << 0) & 0x0000ffff)
720 struct ALT_IO48_HMC_MMR_RESERVE1_s
722 uint32_t cfg_reserve1 : 16;
727 typedef volatile struct ALT_IO48_HMC_MMR_RESERVE1_s ALT_IO48_HMC_MMR_RESERVE1_t;
731 #define ALT_IO48_HMC_MMR_RESERVE1_RESET 0x00000000
733 #define ALT_IO48_HMC_MMR_RESERVE1_OFST 0x20
755 #define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_LSB 0
757 #define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_MSB 15
759 #define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_WIDTH 16
761 #define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_SET_MSK 0x0000ffff
763 #define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_CLR_MSK 0xffff0000
765 #define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_RESET 0x0
767 #define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_GET(value) (((value) & 0x0000ffff) >> 0)
769 #define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_SET(value) (((value) << 0) & 0x0000ffff)
782 struct ALT_IO48_HMC_MMR_RESERVE2_s
784 uint32_t cfg_reserve2 : 16;
789 typedef volatile struct ALT_IO48_HMC_MMR_RESERVE2_s ALT_IO48_HMC_MMR_RESERVE2_t;
793 #define ALT_IO48_HMC_MMR_RESERVE2_RESET 0x00000000
795 #define ALT_IO48_HMC_MMR_RESERVE2_OFST 0x24
825 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_LSB 0
827 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_MSB 3
829 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_WIDTH 4
831 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_SET_MSK 0x0000000f
833 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_CLR_MSK 0xfffffff0
835 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_RESET 0x0
837 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_GET(value) (((value) & 0x0000000f) >> 0)
839 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_SET(value) (((value) << 0) & 0x0000000f)
851 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_LSB 4
853 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_MSB 6
855 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_WIDTH 3
857 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_SET_MSK 0x00000070
859 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_CLR_MSK 0xffffff8f
861 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_RESET 0x0
863 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_GET(value) (((value) & 0x00000070) >> 4)
865 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_SET(value) (((value) << 4) & 0x00000070)
876 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_LSB 7
878 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_MSB 8
880 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_WIDTH 2
882 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_SET_MSK 0x00000180
884 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_CLR_MSK 0xfffffe7f
886 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_RESET 0x0
888 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_GET(value) (((value) & 0x00000180) >> 7)
890 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_SET(value) (((value) << 7) & 0x00000180)
904 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_LSB 9
906 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_MSB 13
908 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_WIDTH 5
910 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_SET_MSK 0x00003e00
912 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_CLR_MSK 0xffffc1ff
914 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_RESET 0x0
916 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_GET(value) (((value) & 0x00003e00) >> 9)
918 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_SET(value) (((value) << 9) & 0x00003e00)
932 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_LSB 14
934 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_MSB 18
936 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_WIDTH 5
938 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_SET_MSK 0x0007c000
940 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_CLR_MSK 0xfff83fff
942 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_RESET 0x0
944 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_GET(value) (((value) & 0x0007c000) >> 14)
946 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_SET(value) (((value) << 14) & 0x0007c000)
960 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_LSB 19
962 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_MSB 23
964 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_WIDTH 5
966 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_SET_MSK 0x00f80000
968 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_CLR_MSK 0xff07ffff
970 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_RESET 0x0
972 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_GET(value) (((value) & 0x00f80000) >> 19)
974 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_SET(value) (((value) << 19) & 0x00f80000)
988 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_LSB 24
990 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_MSB 28
992 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_WIDTH 5
994 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_SET_MSK 0x1f000000
996 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_CLR_MSK 0xe0ffffff
998 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_RESET 0x0
1000 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_GET(value) (((value) & 0x1f000000) >> 24)
1002 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_SET(value) (((value) << 24) & 0x1f000000)
1004 #ifndef __ASSEMBLY__
1015 struct ALT_IO48_HMC_MMR_CTLCFG0_s
1017 uint32_t cfg_mem_type : 4;
1018 uint32_t cfg_dimm_type : 3;
1019 uint32_t cfg_ac_pos : 2;
1020 uint32_t cfg_ctrl_burst_length : 5;
1021 uint32_t cfg_dbc0_burst_length : 5;
1022 uint32_t cfg_dbc1_burst_length : 5;
1023 uint32_t cfg_dbc2_burst_length : 5;
1028 typedef volatile struct ALT_IO48_HMC_MMR_CTLCFG0_s ALT_IO48_HMC_MMR_CTLCFG0_t;
1032 #define ALT_IO48_HMC_MMR_CTLCFG0_RESET 0x00000000
1034 #define ALT_IO48_HMC_MMR_CTLCFG0_OFST 0x28
1079 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_LSB 0
1081 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_MSB 4
1083 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_WIDTH 5
1085 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_SET_MSK 0x0000001f
1087 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_CLR_MSK 0xffffffe0
1089 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_RESET 0x0
1091 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_GET(value) (((value) & 0x0000001f) >> 0)
1093 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_SET(value) (((value) << 0) & 0x0000001f)
1108 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_LSB 5
1110 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_MSB 6
1112 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_WIDTH 2
1114 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_SET_MSK 0x00000060
1116 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_CLR_MSK 0xffffff9f
1118 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_RESET 0x0
1120 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_GET(value) (((value) & 0x00000060) >> 5)
1122 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_SET(value) (((value) << 5) & 0x00000060)
1133 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_LSB 7
1135 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_MSB 7
1137 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_WIDTH 1
1139 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_SET_MSK 0x00000080
1141 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_CLR_MSK 0xffffff7f
1143 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_RESET 0x0
1145 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_GET(value) (((value) & 0x00000080) >> 7)
1147 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_SET(value) (((value) << 7) & 0x00000080)
1158 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_LSB 8
1160 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_MSB 8
1162 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_WIDTH 1
1164 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_SET_MSK 0x00000100
1166 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_CLR_MSK 0xfffffeff
1168 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_RESET 0x0
1170 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_GET(value) (((value) & 0x00000100) >> 8)
1172 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_SET(value) (((value) << 8) & 0x00000100)
1183 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_LSB 9
1185 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_MSB 9
1187 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_WIDTH 1
1189 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_SET_MSK 0x00000200
1191 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_CLR_MSK 0xfffffdff
1193 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_RESET 0x0
1195 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_GET(value) (((value) & 0x00000200) >> 9)
1197 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_SET(value) (((value) << 9) & 0x00000200)
1208 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_LSB 10
1210 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_MSB 10
1212 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_WIDTH 1
1214 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_SET_MSK 0x00000400
1216 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_CLR_MSK 0xfffffbff
1218 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_RESET 0x0
1220 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_GET(value) (((value) & 0x00000400) >> 10)
1222 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_SET(value) (((value) << 10) & 0x00000400)
1233 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_LSB 11
1235 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_MSB 11
1237 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_WIDTH 1
1239 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_SET_MSK 0x00000800
1241 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_CLR_MSK 0xfffff7ff
1243 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_RESET 0x0
1245 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_GET(value) (((value) & 0x00000800) >> 11)
1247 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_SET(value) (((value) << 11) & 0x00000800)
1259 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_LSB 12
1261 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_MSB 12
1263 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_WIDTH 1
1265 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_SET_MSK 0x00001000
1267 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_CLR_MSK 0xffffefff
1269 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_RESET 0x0
1271 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_GET(value) (((value) & 0x00001000) >> 12)
1273 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_SET(value) (((value) << 12) & 0x00001000)
1284 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_LSB 13
1286 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_MSB 13
1288 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_WIDTH 1
1290 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_SET_MSK 0x00002000
1292 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_CLR_MSK 0xffffdfff
1294 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_RESET 0x0
1296 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_GET(value) (((value) & 0x00002000) >> 13)
1298 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_SET(value) (((value) << 13) & 0x00002000)
1309 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_LSB 14
1311 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_MSB 14
1313 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_WIDTH 1
1315 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_SET_MSK 0x00004000
1317 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_CLR_MSK 0xffffbfff
1319 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_RESET 0x0
1321 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_GET(value) (((value) & 0x00004000) >> 14)
1323 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_SET(value) (((value) << 14) & 0x00004000)
1334 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_LSB 15
1336 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_MSB 15
1338 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_WIDTH 1
1340 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_SET_MSK 0x00008000
1342 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_CLR_MSK 0xffff7fff
1344 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_RESET 0x0
1346 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_GET(value) (((value) & 0x00008000) >> 15)
1348 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_SET(value) (((value) << 15) & 0x00008000)
1359 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_LSB 16
1361 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_MSB 16
1363 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_WIDTH 1
1365 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_SET_MSK 0x00010000
1367 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_CLR_MSK 0xfffeffff
1369 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_RESET 0x0
1371 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_GET(value) (((value) & 0x00010000) >> 16)
1373 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_SET(value) (((value) << 16) & 0x00010000)
1384 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_LSB 17
1386 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_MSB 17
1388 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_WIDTH 1
1390 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_SET_MSK 0x00020000
1392 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_CLR_MSK 0xfffdffff
1394 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_RESET 0x0
1396 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_GET(value) (((value) & 0x00020000) >> 17)
1398 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_SET(value) (((value) << 17) & 0x00020000)
1409 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_LSB 18
1411 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_MSB 18
1413 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_WIDTH 1
1415 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_SET_MSK 0x00040000
1417 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_CLR_MSK 0xfffbffff
1419 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_RESET 0x0
1421 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_GET(value) (((value) & 0x00040000) >> 18)
1423 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_SET(value) (((value) << 18) & 0x00040000)
1436 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_LSB 19
1438 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_MSB 24
1440 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_WIDTH 6
1442 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_SET_MSK 0x01f80000
1444 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_CLR_MSK 0xfe07ffff
1446 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_RESET 0x0
1448 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_GET(value) (((value) & 0x01f80000) >> 19)
1450 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_SET(value) (((value) << 19) & 0x01f80000)
1461 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_LSB 25
1463 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_MSB 25
1465 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_WIDTH 1
1467 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_SET_MSK 0x02000000
1469 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_CLR_MSK 0xfdffffff
1471 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_RESET 0x0
1473 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_GET(value) (((value) & 0x02000000) >> 25)
1475 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_SET(value) (((value) << 25) & 0x02000000)
1486 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_LSB 26
1488 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_MSB 26
1490 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_WIDTH 1
1492 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_SET_MSK 0x04000000
1494 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_CLR_MSK 0xfbffffff
1496 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_RESET 0x0
1498 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_GET(value) (((value) & 0x04000000) >> 26)
1500 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_SET(value) (((value) << 26) & 0x04000000)
1511 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_LSB 27
1513 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_MSB 27
1515 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_WIDTH 1
1517 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_SET_MSK 0x08000000
1519 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_CLR_MSK 0xf7ffffff
1521 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_RESET 0x0
1523 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_GET(value) (((value) & 0x08000000) >> 27)
1525 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_SET(value) (((value) << 27) & 0x08000000)
1536 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_LSB 28
1538 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_MSB 28
1540 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_WIDTH 1
1542 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_SET_MSK 0x10000000
1544 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_CLR_MSK 0xefffffff
1546 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_RESET 0x0
1548 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_GET(value) (((value) & 0x10000000) >> 28)
1550 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_SET(value) (((value) << 28) & 0x10000000)
1561 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_LSB 29
1563 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_MSB 29
1565 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_WIDTH 1
1567 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_SET_MSK 0x20000000
1569 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_CLR_MSK 0xdfffffff
1571 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_RESET 0x0
1573 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_GET(value) (((value) & 0x20000000) >> 29)
1575 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_SET(value) (((value) << 29) & 0x20000000)
1586 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_LSB 30
1588 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_MSB 30
1590 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_WIDTH 1
1592 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_SET_MSK 0x40000000
1594 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_CLR_MSK 0xbfffffff
1596 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_RESET 0x0
1598 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_GET(value) (((value) & 0x40000000) >> 30)
1600 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_SET(value) (((value) << 30) & 0x40000000)
1602 #ifndef __ASSEMBLY__
1613 struct ALT_IO48_HMC_MMR_CTLCFG1_s
1615 uint32_t cfg_dbc3_burst_length : 5;
1616 uint32_t cfg_addr_order : 2;
1617 uint32_t cfg_ctrl_enable_ecc : 1;
1618 uint32_t cfg_dbc0_enable_ecc : 1;
1619 uint32_t cfg_dbc1_enable_ecc : 1;
1620 uint32_t cfg_dbc2_enable_ecc : 1;
1621 uint32_t cfg_dbc3_enable_ecc : 1;
1622 uint32_t cfg_reorder_data : 1;
1623 uint32_t cfg_ctrl_reorder_rdata : 1;
1624 uint32_t cfg_dbc0_reorder_rdata : 1;
1625 uint32_t cfg_dbc1_reorder_rdata : 1;
1626 uint32_t cfg_dbc2_reorder_rdata : 1;
1627 uint32_t cfg_dbc3_reorder_rdata : 1;
1628 uint32_t cfg_reorder_read : 1;
1629 uint32_t cfg_starve_limit : 6;
1630 uint32_t cfg_dqstrk_en : 1;
1631 uint32_t cfg_ctrl_enable_dm : 1;
1632 uint32_t cfg_dbc0_enable_dm : 1;
1633 uint32_t cfg_dbc1_enable_dm : 1;
1634 uint32_t cfg_dbc2_enable_dm : 1;
1635 uint32_t cfg_dbc3_enable_dm : 1;
1640 typedef volatile struct ALT_IO48_HMC_MMR_CTLCFG1_s ALT_IO48_HMC_MMR_CTLCFG1_t;
1644 #define ALT_IO48_HMC_MMR_CTLCFG1_RESET 0x00000000
1646 #define ALT_IO48_HMC_MMR_CTLCFG1_OFST 0x2c
1683 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_LSB 0
1685 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_MSB 0
1687 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_WIDTH 1
1689 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_SET_MSK 0x00000001
1691 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_CLR_MSK 0xfffffffe
1693 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_RESET 0x0
1695 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_GET(value) (((value) & 0x00000001) >> 0)
1697 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_SET(value) (((value) << 0) & 0x00000001)
1708 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_LSB 1
1710 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_MSB 1
1712 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_WIDTH 1
1714 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_SET_MSK 0x00000002
1716 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_CLR_MSK 0xfffffffd
1718 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_RESET 0x0
1720 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_GET(value) (((value) & 0x00000002) >> 1)
1722 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_SET(value) (((value) << 1) & 0x00000002)
1733 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_LSB 2
1735 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_MSB 2
1737 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_WIDTH 1
1739 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_SET_MSK 0x00000004
1741 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_CLR_MSK 0xfffffffb
1743 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_RESET 0x0
1745 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_GET(value) (((value) & 0x00000004) >> 2)
1747 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_SET(value) (((value) << 2) & 0x00000004)
1758 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_LSB 3
1760 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_MSB 3
1762 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_WIDTH 1
1764 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_SET_MSK 0x00000008
1766 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_CLR_MSK 0xfffffff7
1768 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_RESET 0x0
1770 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_GET(value) (((value) & 0x00000008) >> 3)
1772 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_SET(value) (((value) << 3) & 0x00000008)
1783 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_LSB 4
1785 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_MSB 4
1787 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_WIDTH 1
1789 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_SET_MSK 0x00000010
1791 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_CLR_MSK 0xffffffef
1793 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_RESET 0x0
1795 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_GET(value) (((value) & 0x00000010) >> 4)
1797 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_SET(value) (((value) << 4) & 0x00000010)
1808 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_LSB 5
1810 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_MSB 6
1812 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_WIDTH 2
1814 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_SET_MSK 0x00000060
1816 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_CLR_MSK 0xffffff9f
1818 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_RESET 0x0
1820 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_GET(value) (((value) & 0x00000060) >> 5)
1822 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_SET(value) (((value) << 5) & 0x00000060)
1833 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_LSB 7
1835 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_MSB 8
1837 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_WIDTH 2
1839 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_SET_MSK 0x00000180
1841 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_CLR_MSK 0xfffffe7f
1843 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_RESET 0x0
1845 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_GET(value) (((value) & 0x00000180) >> 7)
1847 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_SET(value) (((value) << 7) & 0x00000180)
1858 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_LSB 9
1860 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_MSB 9
1862 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_WIDTH 1
1864 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_SET_MSK 0x00000200
1866 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_CLR_MSK 0xfffffdff
1868 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_RESET 0x0
1870 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_GET(value) (((value) & 0x00000200) >> 9)
1872 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_SET(value) (((value) << 9) & 0x00000200)
1883 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_LSB 10
1885 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_MSB 10
1887 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_WIDTH 1
1889 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_SET_MSK 0x00000400
1891 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_CLR_MSK 0xfffffbff
1893 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_RESET 0x0
1895 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_GET(value) (((value) & 0x00000400) >> 10)
1897 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_SET(value) (((value) << 10) & 0x00000400)
1908 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_LSB 11
1910 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_MSB 11
1912 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_WIDTH 1
1914 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_SET_MSK 0x00000800
1916 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_CLR_MSK 0xfffff7ff
1918 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_RESET 0x0
1920 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_GET(value) (((value) & 0x00000800) >> 11)
1922 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_SET(value) (((value) << 11) & 0x00000800)
1933 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_LSB 12
1935 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_MSB 12
1937 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_WIDTH 1
1939 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_SET_MSK 0x00001000
1941 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_CLR_MSK 0xffffefff
1943 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_RESET 0x0
1945 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_GET(value) (((value) & 0x00001000) >> 12)
1947 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_SET(value) (((value) << 12) & 0x00001000)
1958 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_LSB 13
1960 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_MSB 14
1962 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_WIDTH 2
1964 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_SET_MSK 0x00006000
1966 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_CLR_MSK 0xffff9fff
1968 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_RESET 0x0
1970 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_GET(value) (((value) & 0x00006000) >> 13)
1972 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_SET(value) (((value) << 13) & 0x00006000)
1984 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_LSB 15
1986 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_MSB 17
1988 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_WIDTH 3
1990 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_SET_MSK 0x00038000
1992 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_CLR_MSK 0xfffc7fff
1994 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_RESET 0x0
1996 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_GET(value) (((value) & 0x00038000) >> 15)
1998 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_SET(value) (((value) << 15) & 0x00038000)
2010 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_LSB 18
2012 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_MSB 20
2014 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_WIDTH 3
2016 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_SET_MSK 0x001c0000
2018 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_CLR_MSK 0xffe3ffff
2020 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_RESET 0x0
2022 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_GET(value) (((value) & 0x001c0000) >> 18)
2024 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_SET(value) (((value) << 18) & 0x001c0000)
2036 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_LSB 21
2038 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_MSB 23
2040 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_WIDTH 3
2042 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_SET_MSK 0x00e00000
2044 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_CLR_MSK 0xff1fffff
2046 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_RESET 0x0
2048 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_GET(value) (((value) & 0x00e00000) >> 21)
2050 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_SET(value) (((value) << 21) & 0x00e00000)
2062 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_LSB 24
2064 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_MSB 26
2066 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_WIDTH 3
2068 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_SET_MSK 0x07000000
2070 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_CLR_MSK 0xf8ffffff
2072 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_RESET 0x0
2074 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_GET(value) (((value) & 0x07000000) >> 24)
2076 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_SET(value) (((value) << 24) & 0x07000000)
2078 #ifndef __ASSEMBLY__
2089 struct ALT_IO48_HMC_MMR_CTLCFG2_s
2091 uint32_t cfg_ctrl_output_regd : 1;
2092 uint32_t cfg_dbc0_output_regd : 1;
2093 uint32_t cfg_dbc1_output_regd : 1;
2094 uint32_t cfg_dbc2_output_regd : 1;
2095 uint32_t cfg_dbc3_output_regd : 1;
2096 uint32_t cfg_ctrl2dbc_switch0 : 2;
2097 uint32_t cfg_ctrl2dbc_switch1 : 2;
2098 uint32_t cfg_dbc0_ctrl_sel : 1;
2099 uint32_t cfg_dbc1_ctrl_sel : 1;
2100 uint32_t cfg_dbc2_ctrl_sel : 1;
2101 uint32_t cfg_dbc3_ctrl_sel : 1;
2102 uint32_t cfg_dbc2ctrl_sel : 2;
2103 uint32_t cfg_dbc0_pipe_lat : 3;
2104 uint32_t cfg_dbc1_pipe_lat : 3;
2105 uint32_t cfg_dbc2_pipe_lat : 3;
2106 uint32_t cfg_dbc3_pipe_lat : 3;
2111 typedef volatile struct ALT_IO48_HMC_MMR_CTLCFG2_s ALT_IO48_HMC_MMR_CTLCFG2_t;
2115 #define ALT_IO48_HMC_MMR_CTLCFG2_RESET 0x00000000
2117 #define ALT_IO48_HMC_MMR_CTLCFG2_OFST 0x30
2157 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_LSB 0
2159 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_MSB 2
2161 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_WIDTH 3
2163 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_SET_MSK 0x00000007
2165 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_CLR_MSK 0xfffffff8
2167 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_RESET 0x0
2169 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_GET(value) (((value) & 0x00000007) >> 0)
2171 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_SET(value) (((value) << 0) & 0x00000007)
2182 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_LSB 3
2184 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_MSB 5
2186 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_WIDTH 3
2188 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_SET_MSK 0x00000038
2190 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_CLR_MSK 0xffffffc7
2192 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_RESET 0x0
2194 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_GET(value) (((value) & 0x00000038) >> 3)
2196 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_SET(value) (((value) << 3) & 0x00000038)
2207 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_LSB 6
2209 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_MSB 8
2211 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_WIDTH 3
2213 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_SET_MSK 0x000001c0
2215 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_CLR_MSK 0xfffffe3f
2217 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_RESET 0x0
2219 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_GET(value) (((value) & 0x000001c0) >> 6)
2221 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_SET(value) (((value) << 6) & 0x000001c0)
2232 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_LSB 9
2234 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_MSB 11
2236 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_WIDTH 3
2238 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_SET_MSK 0x00000e00
2240 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_CLR_MSK 0xfffff1ff
2242 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_RESET 0x0
2244 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_GET(value) (((value) & 0x00000e00) >> 9)
2246 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_SET(value) (((value) << 9) & 0x00000e00)
2257 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_LSB 12
2259 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_MSB 14
2261 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_WIDTH 3
2263 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_SET_MSK 0x00007000
2265 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_CLR_MSK 0xffff8fff
2267 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_RESET 0x0
2269 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_GET(value) (((value) & 0x00007000) >> 12)
2271 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_SET(value) (((value) << 12) & 0x00007000)
2282 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_LSB 15
2284 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_MSB 15
2286 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_WIDTH 1
2288 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_SET_MSK 0x00008000
2290 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_CLR_MSK 0xffff7fff
2292 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_RESET 0x0
2294 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_GET(value) (((value) & 0x00008000) >> 15)
2296 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_SET(value) (((value) << 15) & 0x00008000)
2307 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_LSB 16
2309 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_MSB 16
2311 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_WIDTH 1
2313 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_SET_MSK 0x00010000
2315 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_CLR_MSK 0xfffeffff
2317 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_RESET 0x0
2319 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_GET(value) (((value) & 0x00010000) >> 16)
2321 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_SET(value) (((value) << 16) & 0x00010000)
2332 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_LSB 17
2334 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_MSB 17
2336 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_WIDTH 1
2338 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_SET_MSK 0x00020000
2340 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_CLR_MSK 0xfffdffff
2342 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_RESET 0x0
2344 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_GET(value) (((value) & 0x00020000) >> 17)
2346 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_SET(value) (((value) << 17) & 0x00020000)
2357 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_LSB 18
2359 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_MSB 18
2361 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_WIDTH 1
2363 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_SET_MSK 0x00040000
2365 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_CLR_MSK 0xfffbffff
2367 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_RESET 0x0
2369 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_GET(value) (((value) & 0x00040000) >> 18)
2371 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_SET(value) (((value) << 18) & 0x00040000)
2382 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_LSB 19
2384 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_MSB 19
2386 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_WIDTH 1
2388 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_SET_MSK 0x00080000
2390 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_CLR_MSK 0xfff7ffff
2392 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_RESET 0x0
2394 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_GET(value) (((value) & 0x00080000) >> 19)
2396 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_SET(value) (((value) << 19) & 0x00080000)
2407 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_LSB 20
2409 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_MSB 20
2411 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_WIDTH 1
2413 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_SET_MSK 0x00100000
2415 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_CLR_MSK 0xffefffff
2417 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_RESET 0x0
2419 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_GET(value) (((value) & 0x00100000) >> 20)
2421 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_SET(value) (((value) << 20) & 0x00100000)
2432 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_LSB 21
2434 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_MSB 21
2436 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_WIDTH 1
2438 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_SET_MSK 0x00200000
2440 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_CLR_MSK 0xffdfffff
2442 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_RESET 0x0
2444 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_GET(value) (((value) & 0x00200000) >> 21)
2446 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_SET(value) (((value) << 21) & 0x00200000)
2457 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_LSB 22
2459 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_MSB 22
2461 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_WIDTH 1
2463 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_SET_MSK 0x00400000
2465 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_CLR_MSK 0xffbfffff
2467 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_RESET 0x0
2469 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_GET(value) (((value) & 0x00400000) >> 22)
2471 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_SET(value) (((value) << 22) & 0x00400000)
2482 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_LSB 23
2484 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_MSB 23
2486 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_WIDTH 1
2488 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_SET_MSK 0x00800000
2490 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_CLR_MSK 0xff7fffff
2492 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_RESET 0x0
2494 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_GET(value) (((value) & 0x00800000) >> 23)
2496 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_SET(value) (((value) << 23) & 0x00800000)
2507 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_LSB 24
2509 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_MSB 24
2511 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_WIDTH 1
2513 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_SET_MSK 0x01000000
2515 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_CLR_MSK 0xfeffffff
2517 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_RESET 0x0
2519 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_GET(value) (((value) & 0x01000000) >> 24)
2521 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_SET(value) (((value) << 24) & 0x01000000)
2532 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_LSB 25
2534 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_MSB 25
2536 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_WIDTH 1
2538 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_SET_MSK 0x02000000
2540 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_CLR_MSK 0xfdffffff
2542 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_RESET 0x0
2544 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_GET(value) (((value) & 0x02000000) >> 25)
2546 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_SET(value) (((value) << 25) & 0x02000000)
2558 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_LSB 26
2560 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_MSB 26
2562 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_WIDTH 1
2564 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_SET_MSK 0x04000000
2566 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_CLR_MSK 0xfbffffff
2568 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_RESET 0x0
2570 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_GET(value) (((value) & 0x04000000) >> 26)
2572 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_SET(value) (((value) << 26) & 0x04000000)
2583 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_LSB 27
2585 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_MSB 27
2587 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_WIDTH 1
2589 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_SET_MSK 0x08000000
2591 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_CLR_MSK 0xf7ffffff
2593 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_RESET 0x0
2595 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_GET(value) (((value) & 0x08000000) >> 27)
2597 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_SET(value) (((value) << 27) & 0x08000000)
2608 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_LSB 28
2610 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_MSB 30
2612 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_WIDTH 3
2614 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_SET_MSK 0x70000000
2616 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_CLR_MSK 0x8fffffff
2618 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_RESET 0x0
2620 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_GET(value) (((value) & 0x70000000) >> 28)
2622 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_SET(value) (((value) << 28) & 0x70000000)
2624 #ifndef __ASSEMBLY__
2635 struct ALT_IO48_HMC_MMR_CTLCFG3_s
2637 uint32_t cfg_ctrl_cmd_rate : 3;
2638 uint32_t cfg_dbc0_cmd_rate : 3;
2639 uint32_t cfg_dbc1_cmd_rate : 3;
2640 uint32_t cfg_dbc2_cmd_rate : 3;
2641 uint32_t cfg_dbc3_cmd_rate : 3;
2642 uint32_t cfg_ctrl_in_protocol : 1;
2643 uint32_t cfg_dbc0_in_protocol : 1;
2644 uint32_t cfg_dbc1_in_protocol : 1;
2645 uint32_t cfg_dbc2_in_protocol : 1;
2646 uint32_t cfg_dbc3_in_protocol : 1;
2647 uint32_t cfg_ctrl_dualport_en : 1;
2648 uint32_t cfg_dbc0_dualport_en : 1;
2649 uint32_t cfg_dbc1_dualport_en : 1;
2650 uint32_t cfg_dbc2_dualport_en : 1;
2651 uint32_t cfg_dbc3_dualport_en : 1;
2652 uint32_t cfg_arbiter_type : 1;
2653 uint32_t cfg_open_page_en : 1;
2654 uint32_t cfg_geardn_en : 1;
2655 uint32_t cfg_rld3_multibank_mode : 3;
2660 typedef volatile struct ALT_IO48_HMC_MMR_CTLCFG3_s ALT_IO48_HMC_MMR_CTLCFG3_t;
2664 #define ALT_IO48_HMC_MMR_CTLCFG3_RESET 0x00000000
2666 #define ALT_IO48_HMC_MMR_CTLCFG3_OFST 0x34
2698 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_LSB 0
2700 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_MSB 4
2702 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_WIDTH 5
2704 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_SET_MSK 0x0000001f
2706 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_CLR_MSK 0xffffffe0
2708 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_RESET 0x0
2710 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_GET(value) (((value) & 0x0000001f) >> 0)
2712 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_SET(value) (((value) << 0) & 0x0000001f)
2723 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_LSB 5
2725 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_MSB 6
2727 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_WIDTH 2
2729 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_SET_MSK 0x00000060
2731 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_CLR_MSK 0xffffff9f
2733 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_RESET 0x0
2735 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_GET(value) (((value) & 0x00000060) >> 5)
2737 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_SET(value) (((value) << 5) & 0x00000060)
2748 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_LSB 7
2750 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_MSB 9
2752 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_WIDTH 3
2754 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_SET_MSK 0x00000380
2756 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_CLR_MSK 0xfffffc7f
2758 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_RESET 0x0
2760 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_GET(value) (((value) & 0x00000380) >> 7)
2762 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_SET(value) (((value) << 7) & 0x00000380)
2773 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_LSB 10
2775 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_MSB 12
2777 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_WIDTH 3
2779 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_SET_MSK 0x00001c00
2781 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_CLR_MSK 0xffffe3ff
2783 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_RESET 0x0
2785 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_GET(value) (((value) & 0x00001c00) >> 10)
2787 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_SET(value) (((value) << 10) & 0x00001c00)
2798 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_LSB 13
2800 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_MSB 15
2802 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_WIDTH 3
2804 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_SET_MSK 0x0000e000
2806 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_CLR_MSK 0xffff1fff
2808 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_RESET 0x0
2810 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_GET(value) (((value) & 0x0000e000) >> 13)
2812 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_SET(value) (((value) << 13) & 0x0000e000)
2823 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_LSB 16
2825 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_MSB 18
2827 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_WIDTH 3
2829 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_SET_MSK 0x00070000
2831 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_CLR_MSK 0xfff8ffff
2833 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_RESET 0x0
2835 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_GET(value) (((value) & 0x00070000) >> 16)
2837 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_SET(value) (((value) << 16) & 0x00070000)
2848 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_LSB 19
2850 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_MSB 21
2852 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_WIDTH 3
2854 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_SET_MSK 0x00380000
2856 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_CLR_MSK 0xffc7ffff
2858 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_RESET 0x0
2860 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_GET(value) (((value) & 0x00380000) >> 19)
2862 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_SET(value) (((value) << 19) & 0x00380000)
2875 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_LSB 22
2877 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_MSB 23
2879 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_WIDTH 2
2881 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_SET_MSK 0x00c00000
2883 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_CLR_MSK 0xff3fffff
2885 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_RESET 0x0
2887 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_GET(value) (((value) & 0x00c00000) >> 22)
2889 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_SET(value) (((value) << 22) & 0x00c00000)
2902 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_LSB 24
2904 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_MSB 25
2906 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_WIDTH 2
2908 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_SET_MSK 0x03000000
2910 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_CLR_MSK 0xfcffffff
2912 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_RESET 0x0
2914 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_GET(value) (((value) & 0x03000000) >> 24)
2916 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_SET(value) (((value) << 24) & 0x03000000)
2929 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_LSB 26
2931 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_MSB 27
2933 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_WIDTH 2
2935 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_SET_MSK 0x0c000000
2937 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_CLR_MSK 0xf3ffffff
2939 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_RESET 0x0
2941 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_GET(value) (((value) & 0x0c000000) >> 26)
2943 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_SET(value) (((value) << 26) & 0x0c000000)
2956 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_LSB 28
2958 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_MSB 29
2960 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_WIDTH 2
2962 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_SET_MSK 0x30000000
2964 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_CLR_MSK 0xcfffffff
2966 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_RESET 0x0
2968 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_GET(value) (((value) & 0x30000000) >> 28)
2970 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_SET(value) (((value) << 28) & 0x30000000)
2983 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_LSB 30
2985 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_MSB 31
2987 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_WIDTH 2
2989 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_SET_MSK 0xc0000000
2991 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_CLR_MSK 0x3fffffff
2993 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_RESET 0x0
2995 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_GET(value) (((value) & 0xc0000000) >> 30)
2997 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_SET(value) (((value) << 30) & 0xc0000000)
2999 #ifndef __ASSEMBLY__
3010 struct ALT_IO48_HMC_MMR_CTLCFG4_s
3012 uint32_t cfg_tile_id : 5;
3013 uint32_t cfg_pingpong_mode : 2;
3014 uint32_t cfg_ctrl_slot_rotate_en : 3;
3015 uint32_t cfg_dbc0_slot_rotate_en : 3;
3016 uint32_t cfg_dbc1_slot_rotate_en : 3;
3017 uint32_t cfg_dbc2_slot_rotate_en : 3;
3018 uint32_t cfg_dbc3_slot_rotate_en : 3;
3019 uint32_t cfg_ctrl_slot_offset : 2;
3020 uint32_t cfg_dbc0_slot_offset : 2;
3021 uint32_t cfg_dbc1_slot_offset : 2;
3022 uint32_t cfg_dbc2_slot_offset : 2;
3023 uint32_t cfg_dbc3_slot_offset : 2;
3027 typedef volatile struct ALT_IO48_HMC_MMR_CTLCFG4_s ALT_IO48_HMC_MMR_CTLCFG4_t;
3031 #define ALT_IO48_HMC_MMR_CTLCFG4_RESET 0x00000000
3033 #define ALT_IO48_HMC_MMR_CTLCFG4_OFST 0x38
3061 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_LSB 0
3063 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_MSB 3
3065 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_WIDTH 4
3067 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_SET_MSK 0x0000000f
3069 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_CLR_MSK 0xfffffff0
3071 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_RESET 0x0
3073 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_GET(value) (((value) & 0x0000000f) >> 0)
3075 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_SET(value) (((value) << 0) & 0x0000000f)
3086 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_LSB 4
3088 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_MSB 7
3090 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_WIDTH 4
3092 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_SET_MSK 0x000000f0
3094 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_CLR_MSK 0xffffff0f
3096 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_RESET 0x0
3098 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_GET(value) (((value) & 0x000000f0) >> 4)
3100 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_SET(value) (((value) << 4) & 0x000000f0)
3112 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_LSB 8
3114 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_MSB 8
3116 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_WIDTH 1
3118 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_SET_MSK 0x00000100
3120 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_CLR_MSK 0xfffffeff
3122 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_RESET 0x0
3124 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_GET(value) (((value) & 0x00000100) >> 8)
3126 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_SET(value) (((value) << 8) & 0x00000100)
3138 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_LSB 9
3140 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_MSB 9
3142 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_WIDTH 1
3144 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_SET_MSK 0x00000200
3146 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_CLR_MSK 0xfffffdff
3148 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_RESET 0x0
3150 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_GET(value) (((value) & 0x00000200) >> 9)
3152 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_SET(value) (((value) << 9) & 0x00000200)
3164 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_LSB 10
3166 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_MSB 10
3168 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_WIDTH 1
3170 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_SET_MSK 0x00000400
3172 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_CLR_MSK 0xfffffbff
3174 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_RESET 0x0
3176 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_GET(value) (((value) & 0x00000400) >> 10)
3178 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_SET(value) (((value) << 10) & 0x00000400)
3190 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_LSB 11
3192 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_MSB 11
3194 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_WIDTH 1
3196 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_SET_MSK 0x00000800
3198 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_CLR_MSK 0xfffff7ff
3200 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_RESET 0x0
3202 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_GET(value) (((value) & 0x00000800) >> 11)
3204 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_SET(value) (((value) << 11) & 0x00000800)
3216 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_LSB 12
3218 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_MSB 12
3220 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_WIDTH 1
3222 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_SET_MSK 0x00001000
3224 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_CLR_MSK 0xffffefff
3226 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_RESET 0x0
3228 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_GET(value) (((value) & 0x00001000) >> 12)
3230 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_SET(value) (((value) << 12) & 0x00001000)
3232 #ifndef __ASSEMBLY__
3243 struct ALT_IO48_HMC_MMR_CTLCFG5_s
3245 uint32_t cfg_col_cmd_slot : 4;
3246 uint32_t cfg_row_cmd_slot : 4;
3247 uint32_t cfg_ctrl_rc_en : 1;
3248 uint32_t cfg_dbc0_rc_en : 1;
3249 uint32_t cfg_dbc1_rc_en : 1;
3250 uint32_t cfg_dbc2_rc_en : 1;
3251 uint32_t cfg_dbc3_rc_en : 1;
3256 typedef volatile struct ALT_IO48_HMC_MMR_CTLCFG5_s ALT_IO48_HMC_MMR_CTLCFG5_t;
3260 #define ALT_IO48_HMC_MMR_CTLCFG5_RESET 0x00000000
3262 #define ALT_IO48_HMC_MMR_CTLCFG5_OFST 0x3c
3286 #define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_LSB 0
3288 #define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_MSB 15
3290 #define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_WIDTH 16
3292 #define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_SET_MSK 0x0000ffff
3294 #define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_CLR_MSK 0xffff0000
3296 #define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_RESET 0x0
3298 #define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_GET(value) (((value) & 0x0000ffff) >> 0)
3300 #define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_SET(value) (((value) << 0) & 0x0000ffff)
3302 #ifndef __ASSEMBLY__
3313 struct ALT_IO48_HMC_MMR_CTLCFG6_s
3315 uint32_t cfg_cs_chip : 16;
3320 typedef volatile struct ALT_IO48_HMC_MMR_CTLCFG6_s ALT_IO48_HMC_MMR_CTLCFG6_t;
3324 #define ALT_IO48_HMC_MMR_CTLCFG6_RESET 0x00000000
3326 #define ALT_IO48_HMC_MMR_CTLCFG6_OFST 0x40
3350 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_LSB 0
3352 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_MSB 0
3354 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_WIDTH 1
3356 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_SET_MSK 0x00000001
3358 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_CLR_MSK 0xfffffffe
3360 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_RESET 0x0
3362 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_GET(value) (((value) & 0x00000001) >> 0)
3364 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_SET(value) (((value) << 0) & 0x00000001)
3376 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_LSB 1
3378 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_MSB 7
3380 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_WIDTH 7
3382 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_SET_MSK 0x000000fe
3384 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_CLR_MSK 0xffffff01
3386 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_RESET 0x0
3388 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_GET(value) (((value) & 0x000000fe) >> 1)
3390 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_SET(value) (((value) << 1) & 0x000000fe)
3402 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_LSB 8
3404 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_MSB 14
3406 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_WIDTH 7
3408 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_SET_MSK 0x00007f00
3410 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_CLR_MSK 0xffff80ff
3412 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_RESET 0x0
3414 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_GET(value) (((value) & 0x00007f00) >> 8)
3416 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_SET(value) (((value) << 8) & 0x00007f00)
3418 #ifndef __ASSEMBLY__
3429 struct ALT_IO48_HMC_MMR_CTLCFG7_s
3431 uint32_t cfg_clkgating_en : 1;
3432 uint32_t cfg_rb_reserved_entry : 7;
3433 uint32_t cfg_wb_reserved_entry : 7;
3438 typedef volatile struct ALT_IO48_HMC_MMR_CTLCFG7_s ALT_IO48_HMC_MMR_CTLCFG7_t;
3442 #define ALT_IO48_HMC_MMR_CTLCFG7_RESET 0x00000000
3444 #define ALT_IO48_HMC_MMR_CTLCFG7_OFST 0x44
3468 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_LSB 0
3470 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_MSB 0
3472 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_WIDTH 1
3474 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_SET_MSK 0x00000001
3476 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_CLR_MSK 0xfffffffe
3478 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_RESET 0x0
3480 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_GET(value) (((value) & 0x00000001) >> 0)
3482 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_SET(value) (((value) << 0) & 0x00000001)
3493 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_LSB 1
3495 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_MSB 1
3497 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_WIDTH 1
3499 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_SET_MSK 0x00000002
3501 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_CLR_MSK 0xfffffffd
3503 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_RESET 0x0
3505 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_GET(value) (((value) & 0x00000002) >> 1)
3507 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_SET(value) (((value) << 1) & 0x00000002)
3518 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_LSB 2
3520 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_MSB 2
3522 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_WIDTH 1
3524 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_SET_MSK 0x00000004
3526 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_CLR_MSK 0xfffffffb
3528 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_RESET 0x0
3530 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_GET(value) (((value) & 0x00000004) >> 2)
3532 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_SET(value) (((value) << 2) & 0x00000004)
3534 #ifndef __ASSEMBLY__
3545 struct ALT_IO48_HMC_MMR_CTLCFG8_s
3547 uint32_t cfg_3ds_en : 1;
3548 uint32_t cfg_ck_inv : 1;
3549 uint32_t cfg_addr_mplx_en : 1;
3554 typedef volatile struct ALT_IO48_HMC_MMR_CTLCFG8_s ALT_IO48_HMC_MMR_CTLCFG8_t;
3558 #define ALT_IO48_HMC_MMR_CTLCFG8_RESET 0x00000000
3560 #define ALT_IO48_HMC_MMR_CTLCFG8_OFST 0x48
3582 #define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_LSB 0
3584 #define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_MSB 0
3586 #define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_WIDTH 1
3588 #define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_SET_MSK 0x00000001
3590 #define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_CLR_MSK 0xfffffffe
3592 #define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_RESET 0x0
3594 #define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_GET(value) (((value) & 0x00000001) >> 0)
3596 #define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_SET(value) (((value) << 0) & 0x00000001)
3598 #ifndef __ASSEMBLY__
3609 struct ALT_IO48_HMC_MMR_CTLCFG9_s
3611 uint32_t cfg_dfx_bypass_en : 1;
3616 typedef volatile struct ALT_IO48_HMC_MMR_CTLCFG9_s ALT_IO48_HMC_MMR_CTLCFG9_t;
3620 #define ALT_IO48_HMC_MMR_CTLCFG9_RESET 0x00000000
3622 #define ALT_IO48_HMC_MMR_CTLCFG9_OFST 0x4c
3646 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_LSB 0
3648 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_MSB 6
3650 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_WIDTH 7
3652 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_SET_MSK 0x0000007f
3654 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_CLR_MSK 0xffffff80
3656 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_RESET 0x0
3658 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_GET(value) (((value) & 0x0000007f) >> 0)
3660 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_SET(value) (((value) << 0) & 0x0000007f)
3672 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_LSB 7
3674 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_MSB 12
3676 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_WIDTH 6
3678 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_SET_MSK 0x00001f80
3680 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_CLR_MSK 0xffffe07f
3682 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_RESET 0x0
3684 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_GET(value) (((value) & 0x00001f80) >> 7)
3686 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_SET(value) (((value) << 7) & 0x00001f80)
3699 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_LSB 13
3701 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_MSB 18
3703 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_WIDTH 6
3705 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_SET_MSK 0x0007e000
3707 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_CLR_MSK 0xfff81fff
3709 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_RESET 0x0
3711 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_GET(value) (((value) & 0x0007e000) >> 13)
3713 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_SET(value) (((value) << 13) & 0x0007e000)
3715 #ifndef __ASSEMBLY__
3726 struct ALT_IO48_HMC_MMR_DRAMTIMING0_s
3728 uint32_t cfg_tcl : 7;
3729 uint32_t cfg_power_saving_exit_cycles : 6;
3730 uint32_t cfg_mem_clk_disable_entry_cycles : 6;
3735 typedef volatile struct ALT_IO48_HMC_MMR_DRAMTIMING0_s ALT_IO48_HMC_MMR_DRAMTIMING0_t;
3739 #define ALT_IO48_HMC_MMR_DRAMTIMING0_RESET 0x00000000
3741 #define ALT_IO48_HMC_MMR_DRAMTIMING0_OFST 0x50
3765 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_LSB 0
3767 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_MSB 15
3769 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_WIDTH 16
3771 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_SET_MSK 0x0000ffff
3773 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_CLR_MSK 0xffff0000
3775 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_RESET 0x0
3777 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_GET(value) (((value) & 0x0000ffff) >> 0)
3779 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_SET(value) (((value) << 0) & 0x0000ffff)
3792 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_LSB 16
3794 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_MSB 31
3796 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_WIDTH 16
3798 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_SET_MSK 0xffff0000
3800 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_CLR_MSK 0x0000ffff
3802 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_RESET 0x0
3804 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_GET(value) (((value) & 0xffff0000) >> 16)
3806 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_SET(value) (((value) << 16) & 0xffff0000)
3808 #ifndef __ASSEMBLY__
3819 struct ALT_IO48_HMC_MMR_DRAMODT0_s
3821 uint32_t cfg_write_odt_chip : 16;
3822 uint32_t cfg_read_odt_chip : 16;
3826 typedef volatile struct ALT_IO48_HMC_MMR_DRAMODT0_s ALT_IO48_HMC_MMR_DRAMODT0_t;
3830 #define ALT_IO48_HMC_MMR_DRAMODT0_RESET 0x00000000
3832 #define ALT_IO48_HMC_MMR_DRAMODT0_OFST 0x54
3858 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_LSB 0
3860 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_MSB 5
3862 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_WIDTH 6
3864 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_SET_MSK 0x0000003f
3866 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_CLR_MSK 0xffffffc0
3868 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_RESET 0x0
3870 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_GET(value) (((value) & 0x0000003f) >> 0)
3872 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_SET(value) (((value) << 0) & 0x0000003f)
3884 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_LSB 6
3886 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_MSB 11
3888 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_WIDTH 6
3890 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_SET_MSK 0x00000fc0
3892 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_CLR_MSK 0xfffff03f
3894 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_RESET 0x0
3896 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_GET(value) (((value) & 0x00000fc0) >> 6)
3898 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_SET(value) (((value) << 6) & 0x00000fc0)
3910 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_LSB 12
3912 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_MSB 17
3914 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_WIDTH 6
3916 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_SET_MSK 0x0003f000
3918 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_CLR_MSK 0xfffc0fff
3920 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_RESET 0x0
3922 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_GET(value) (((value) & 0x0003f000) >> 12)
3924 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_SET(value) (((value) << 12) & 0x0003f000)
3936 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_LSB 18
3938 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_MSB 23
3940 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_WIDTH 6
3942 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_SET_MSK 0x00fc0000
3944 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_CLR_MSK 0xff03ffff
3946 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_RESET 0x0
3948 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_GET(value) (((value) & 0x00fc0000) >> 18)
3950 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_SET(value) (((value) << 18) & 0x00fc0000)
3952 #ifndef __ASSEMBLY__
3963 struct ALT_IO48_HMC_MMR_DRAMODT1_s
3965 uint32_t cfg_wr_odt_on : 6;
3966 uint32_t cfg_rd_odt_on : 6;
3967 uint32_t cfg_wr_odt_period : 6;
3968 uint32_t cfg_rd_odt_period : 6;
3973 typedef volatile struct ALT_IO48_HMC_MMR_DRAMODT1_s ALT_IO48_HMC_MMR_DRAMODT1_t;
3977 #define ALT_IO48_HMC_MMR_DRAMODT1_RESET 0x00000000
3979 #define ALT_IO48_HMC_MMR_DRAMODT1_OFST 0x58
4001 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_LSB 0
4003 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_MSB 15
4005 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_WIDTH 16
4007 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_SET_MSK 0x0000ffff
4009 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_CLR_MSK 0xffff0000
4011 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_RESET 0x0
4013 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_GET(value) (((value) & 0x0000ffff) >> 0)
4015 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_SET(value) (((value) << 0) & 0x0000ffff)
4026 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_LSB 16
4028 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_MSB 31
4030 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_WIDTH 16
4032 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_SET_MSK 0xffff0000
4034 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_CLR_MSK 0x0000ffff
4036 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_RESET 0x0
4038 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_GET(value) (((value) & 0xffff0000) >> 16)
4040 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_SET(value) (((value) << 16) & 0xffff0000)
4042 #ifndef __ASSEMBLY__
4053 struct ALT_IO48_HMC_MMR_SBCFG0_s
4055 uint32_t cfg_rld3_refresh_seq0 : 16;
4056 uint32_t cfg_rld3_refresh_seq1 : 16;
4060 typedef volatile struct ALT_IO48_HMC_MMR_SBCFG0_s ALT_IO48_HMC_MMR_SBCFG0_t;
4064 #define ALT_IO48_HMC_MMR_SBCFG0_RESET 0x00000000
4066 #define ALT_IO48_HMC_MMR_SBCFG0_OFST 0x5c
4088 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_LSB 0
4090 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_MSB 15
4092 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_WIDTH 16
4094 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_SET_MSK 0x0000ffff
4096 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_CLR_MSK 0xffff0000
4098 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_RESET 0x0
4100 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_GET(value) (((value) & 0x0000ffff) >> 0)
4102 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_SET(value) (((value) << 0) & 0x0000ffff)
4113 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_LSB 16
4115 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_MSB 31
4117 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_WIDTH 16
4119 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_SET_MSK 0xffff0000
4121 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_CLR_MSK 0x0000ffff
4123 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_RESET 0x0
4125 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_GET(value) (((value) & 0xffff0000) >> 16)
4127 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_SET(value) (((value) << 16) & 0xffff0000)
4129 #ifndef __ASSEMBLY__
4140 struct ALT_IO48_HMC_MMR_SBCFG1_s
4142 uint32_t cfg_rld3_refresh_seq2 : 16;
4143 uint32_t cfg_rld3_refresh_seq3 : 16;
4147 typedef volatile struct ALT_IO48_HMC_MMR_SBCFG1_s ALT_IO48_HMC_MMR_SBCFG1_t;
4151 #define ALT_IO48_HMC_MMR_SBCFG1_RESET 0x00000000
4153 #define ALT_IO48_HMC_MMR_SBCFG1_OFST 0x60
4181 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_LSB 0
4183 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_MSB 0
4185 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_WIDTH 1
4187 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_SET_MSK 0x00000001
4189 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_CLR_MSK 0xfffffffe
4191 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_RESET 0x0
4193 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_GET(value) (((value) & 0x00000001) >> 0)
4195 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_SET(value) (((value) << 0) & 0x00000001)
4206 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_LSB 1
4208 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_MSB 1
4210 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_WIDTH 1
4212 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_SET_MSK 0x00000002
4214 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_CLR_MSK 0xfffffffd
4216 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_RESET 0x0
4218 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_GET(value) (((value) & 0x00000002) >> 1)
4220 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_SET(value) (((value) << 1) & 0x00000002)
4231 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_LSB 2
4233 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_MSB 2
4235 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_WIDTH 1
4237 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_SET_MSK 0x00000004
4239 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_CLR_MSK 0xfffffffb
4241 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_RESET 0x0
4243 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_GET(value) (((value) & 0x00000004) >> 2)
4245 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_SET(value) (((value) << 2) & 0x00000004)
4256 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_LSB 3
4258 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_MSB 3
4260 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_WIDTH 1
4262 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_SET_MSK 0x00000008
4264 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_CLR_MSK 0xfffffff7
4266 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_RESET 0x0
4268 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_GET(value) (((value) & 0x00000008) >> 3)
4270 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_SET(value) (((value) << 3) & 0x00000008)
4281 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_LSB 4
4283 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_MSB 4
4285 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_WIDTH 1
4287 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_SET_MSK 0x00000010
4289 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_CLR_MSK 0xffffffef
4291 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_RESET 0x0
4293 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_GET(value) (((value) & 0x00000010) >> 4)
4295 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_SET(value) (((value) << 4) & 0x00000010)
4307 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_LSB 5
4309 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_MSB 5
4311 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_WIDTH 1
4313 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_SET_MSK 0x00000020
4315 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_CLR_MSK 0xffffffdf
4317 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_RESET 0x0
4319 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_GET(value) (((value) & 0x00000020) >> 5)
4321 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_SET(value) (((value) << 5) & 0x00000020)
4332 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_LSB 6
4334 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_MSB 7
4336 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_WIDTH 2
4338 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_SET_MSK 0x000000c0
4340 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_CLR_MSK 0xffffff3f
4342 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_RESET 0x0
4344 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_GET(value) (((value) & 0x000000c0) >> 6)
4346 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_SET(value) (((value) << 6) & 0x000000c0)
4348 #ifndef __ASSEMBLY__
4359 struct ALT_IO48_HMC_MMR_SBCFG2_s
4361 uint32_t cfg_srf_zqcal_disable : 1;
4362 uint32_t cfg_mps_zqcal_disable : 1;
4363 uint32_t cfg_mps_dqstrk_disable : 1;
4364 uint32_t cfg_sb_cg_disable : 1;
4365 uint32_t cfg_user_rfsh_en : 1;
4366 uint32_t cfg_srf_autoexit_en : 1;
4367 uint32_t cfg_srf_entry_exit_block : 2;
4372 typedef volatile struct ALT_IO48_HMC_MMR_SBCFG2_s ALT_IO48_HMC_MMR_SBCFG2_t;
4376 #define ALT_IO48_HMC_MMR_SBCFG2_RESET 0x00000000
4378 #define ALT_IO48_HMC_MMR_SBCFG2_OFST 0x64
4400 #define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_LSB 0
4402 #define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_MSB 19
4404 #define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_WIDTH 20
4406 #define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_SET_MSK 0x000fffff
4408 #define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_CLR_MSK 0xfff00000
4410 #define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_RESET 0x0
4412 #define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_GET(value) (((value) & 0x000fffff) >> 0)
4414 #define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_SET(value) (((value) << 0) & 0x000fffff)
4416 #ifndef __ASSEMBLY__
4427 struct ALT_IO48_HMC_MMR_SBCFG3_s
4429 uint32_t cfg_sb_ddr4_mr3 : 20;
4434 typedef volatile struct ALT_IO48_HMC_MMR_SBCFG3_s ALT_IO48_HMC_MMR_SBCFG3_t;
4438 #define ALT_IO48_HMC_MMR_SBCFG3_RESET 0x00000000
4440 #define ALT_IO48_HMC_MMR_SBCFG3_OFST 0x68
4462 #define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_LSB 0
4464 #define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_MSB 19
4466 #define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_WIDTH 20
4468 #define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_SET_MSK 0x000fffff
4470 #define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_CLR_MSK 0xfff00000
4472 #define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_RESET 0x0
4474 #define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_GET(value) (((value) & 0x000fffff) >> 0)
4476 #define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_SET(value) (((value) << 0) & 0x000fffff)
4478 #ifndef __ASSEMBLY__
4489 struct ALT_IO48_HMC_MMR_SBCFG4_s
4491 uint32_t cfg_sb_ddr4_mr4 : 20;
4496 typedef volatile struct ALT_IO48_HMC_MMR_SBCFG4_s ALT_IO48_HMC_MMR_SBCFG4_t;
4500 #define ALT_IO48_HMC_MMR_SBCFG4_RESET 0x00000000
4502 #define ALT_IO48_HMC_MMR_SBCFG4_OFST 0x6c
4526 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_LSB 0
4528 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_MSB 0
4530 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_WIDTH 1
4532 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_SET_MSK 0x00000001
4534 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_CLR_MSK 0xfffffffe
4536 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_RESET 0x0
4538 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_GET(value) (((value) & 0x00000001) >> 0)
4540 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_SET(value) (((value) << 0) & 0x00000001)
4551 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_LSB 1
4553 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_MSB 1
4555 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_WIDTH 1
4557 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_SET_MSK 0x00000002
4559 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_CLR_MSK 0xfffffffd
4561 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_RESET 0x0
4563 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_GET(value) (((value) & 0x00000002) >> 1)
4565 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_SET(value) (((value) << 1) & 0x00000002)
4567 #ifndef __ASSEMBLY__
4578 struct ALT_IO48_HMC_MMR_SBCFG5_s
4580 uint32_t cfg_short_dqstrk_ctrl_en : 1;
4581 uint32_t cfg_period_dqstrk_ctrl_en : 1;
4586 typedef volatile struct ALT_IO48_HMC_MMR_SBCFG5_s ALT_IO48_HMC_MMR_SBCFG5_t;
4590 #define ALT_IO48_HMC_MMR_SBCFG5_RESET 0x00000000
4592 #define ALT_IO48_HMC_MMR_SBCFG5_OFST 0x70
4615 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_LSB 0
4617 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_MSB 15
4619 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_WIDTH 16
4621 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_SET_MSK 0x0000ffff
4623 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_CLR_MSK 0xffff0000
4625 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_RESET 0x0
4627 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_GET(value) (((value) & 0x0000ffff) >> 0)
4629 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_SET(value) (((value) << 0) & 0x0000ffff)
4640 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_LSB 16
4642 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_MSB 23
4644 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_WIDTH 8
4646 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_SET_MSK 0x00ff0000
4648 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_CLR_MSK 0xff00ffff
4650 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_RESET 0x0
4652 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_GET(value) (((value) & 0x00ff0000) >> 16)
4654 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_SET(value) (((value) << 16) & 0x00ff0000)
4665 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LSB 24
4667 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_MSB 31
4669 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_WIDTH 8
4671 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_SET_MSK 0xff000000
4673 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_CLR_MSK 0x00ffffff
4675 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_RESET 0x0
4677 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_GET(value) (((value) & 0xff000000) >> 24)
4679 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_SET(value) (((value) << 24) & 0xff000000)
4681 #ifndef __ASSEMBLY__
4692 struct ALT_IO48_HMC_MMR_SBCFG6_s
4694 uint32_t cfg_period_dqstrk_interval : 16;
4695 uint32_t cfg_t_param_dqstrk_to_valid_last : 8;
4696 uint32_t cfg_t_param_dqstrk_to_valid : 8;
4700 typedef volatile struct ALT_IO48_HMC_MMR_SBCFG6_s ALT_IO48_HMC_MMR_SBCFG6_t;
4704 #define ALT_IO48_HMC_MMR_SBCFG6_RESET 0x00000000
4706 #define ALT_IO48_HMC_MMR_SBCFG6_OFST 0x74
4729 #define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_LSB 0
4731 #define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_MSB 6
4733 #define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_WIDTH 7
4735 #define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_SET_MSK 0x0000007f
4737 #define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_CLR_MSK 0xffffff80
4739 #define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_RESET 0x0
4741 #define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_GET(value) (((value) & 0x0000007f) >> 0)
4743 #define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_SET(value) (((value) << 0) & 0x0000007f)
4745 #ifndef __ASSEMBLY__
4756 struct ALT_IO48_HMC_MMR_SBCFG7_s
4758 uint32_t cfg_rfsh_warn_threshold : 7;
4763 typedef volatile struct ALT_IO48_HMC_MMR_SBCFG7_s ALT_IO48_HMC_MMR_SBCFG7_t;
4767 #define ALT_IO48_HMC_MMR_SBCFG7_RESET 0x00000000
4769 #define ALT_IO48_HMC_MMR_SBCFG7_OFST 0x78
4795 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_LSB 0
4797 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_MSB 5
4799 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_WIDTH 6
4801 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_SET_MSK 0x0000003f
4803 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_CLR_MSK 0xffffffc0
4805 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_RESET 0x0
4807 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_GET(value) (((value) & 0x0000003f) >> 0)
4809 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_SET(value) (((value) << 0) & 0x0000003f)
4820 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_LSB 6
4822 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_MSB 11
4824 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_WIDTH 6
4826 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_SET_MSK 0x00000fc0
4828 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_CLR_MSK 0xfffff03f
4830 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_RESET 0x0
4832 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_GET(value) (((value) & 0x00000fc0) >> 6)
4834 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_SET(value) (((value) << 6) & 0x00000fc0)
4845 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_LSB 12
4847 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_MSB 17
4849 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_WIDTH 6
4851 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_SET_MSK 0x0003f000
4853 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_CLR_MSK 0xfffc0fff
4855 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_RESET 0x0
4857 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_GET(value) (((value) & 0x0003f000) >> 12)
4859 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_SET(value) (((value) << 12) & 0x0003f000)
4870 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_LSB 18
4872 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_MSB 23
4874 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH 6
4876 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_SET_MSK 0x00fc0000
4878 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_CLR_MSK 0xff03ffff
4880 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_RESET 0x0
4882 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_GET(value) (((value) & 0x00fc0000) >> 18)
4884 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_SET(value) (((value) << 18) & 0x00fc0000)
4895 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_LSB 24
4897 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_MSB 29
4899 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_WIDTH 6
4901 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_SET_MSK 0x3f000000
4903 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_CLR_MSK 0xc0ffffff
4905 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_RESET 0x0
4907 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_GET(value) (((value) & 0x3f000000) >> 24)
4909 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_SET(value) (((value) << 24) & 0x3f000000)
4911 #ifndef __ASSEMBLY__
4922 struct ALT_IO48_HMC_MMR_CALTIMING0_s
4924 uint32_t cfg_t_param_act_to_rdwr : 6;
4925 uint32_t cfg_t_param_act_to_pch : 6;
4926 uint32_t cfg_t_param_act_to_act : 6;
4927 uint32_t cfg_t_param_act_to_act_diff_bank : 6;
4928 uint32_t cfg_t_param_act_to_act_diff_bg : 6;
4933 typedef volatile struct ALT_IO48_HMC_MMR_CALTIMING0_s ALT_IO48_HMC_MMR_CALTIMING0_t;
4937 #define ALT_IO48_HMC_MMR_CALTIMING0_RESET 0x00000000
4939 #define ALT_IO48_HMC_MMR_CALTIMING0_OFST 0x7c
4965 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_LSB 0
4967 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_MSB 5
4969 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_WIDTH 6
4971 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_SET_MSK 0x0000003f
4973 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_CLR_MSK 0xffffffc0
4975 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_RESET 0x0
4977 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_GET(value) (((value) & 0x0000003f) >> 0)
4979 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_SET(value) (((value) << 0) & 0x0000003f)
4990 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_LSB 6
4992 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_MSB 11
4994 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH 6
4996 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_SET_MSK 0x00000fc0
4998 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_CLR_MSK 0xfffff03f
5000 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_RESET 0x0
5002 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_GET(value) (((value) & 0x00000fc0) >> 6)
5004 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_SET(value) (((value) << 6) & 0x00000fc0)
5015 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_LSB 12
5017 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_MSB 17
5019 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_WIDTH 6
5021 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_SET_MSK 0x0003f000
5023 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_CLR_MSK 0xfffc0fff
5025 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_RESET 0x0
5027 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_GET(value) (((value) & 0x0003f000) >> 12)
5029 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_SET(value) (((value) << 12) & 0x0003f000)
5040 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_LSB 18
5042 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_MSB 23
5044 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_WIDTH 6
5046 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_SET_MSK 0x00fc0000
5048 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_CLR_MSK 0xff03ffff
5050 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_RESET 0x0
5052 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_GET(value) (((value) & 0x00fc0000) >> 18)
5054 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_SET(value) (((value) << 18) & 0x00fc0000)
5065 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_LSB 24
5067 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_MSB 29
5069 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH 6
5071 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_SET_MSK 0x3f000000
5073 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_CLR_MSK 0xc0ffffff
5075 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_RESET 0x0
5077 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_GET(value) (((value) & 0x3f000000) >> 24)
5079 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_SET(value) (((value) << 24) & 0x3f000000)
5081 #ifndef __ASSEMBLY__
5092 struct ALT_IO48_HMC_MMR_CALTIMING1_s
5094 uint32_t cfg_t_param_rd_to_rd : 6;
5095 uint32_t cfg_t_param_rd_to_rd_diff_chip : 6;
5096 uint32_t cfg_t_param_rd_to_rd_diff_bg : 6;
5097 uint32_t cfg_t_param_rd_to_wr : 6;
5098 uint32_t cfg_t_param_rd_to_wr_diff_chip : 6;
5103 typedef volatile struct ALT_IO48_HMC_MMR_CALTIMING1_s ALT_IO48_HMC_MMR_CALTIMING1_t;
5107 #define ALT_IO48_HMC_MMR_CALTIMING1_RESET 0x00000000
5109 #define ALT_IO48_HMC_MMR_CALTIMING1_OFST 0x80
5135 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_LSB 0
5137 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_MSB 5
5139 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_WIDTH 6
5141 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_SET_MSK 0x0000003f
5143 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_CLR_MSK 0xffffffc0
5145 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_RESET 0x0
5147 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_GET(value) (((value) & 0x0000003f) >> 0)
5149 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_SET(value) (((value) << 0) & 0x0000003f)
5160 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_LSB 6
5162 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_MSB 11
5164 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_WIDTH 6
5166 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_SET_MSK 0x00000fc0
5168 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_CLR_MSK 0xfffff03f
5170 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_RESET 0x0
5172 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_GET(value) (((value) & 0x00000fc0) >> 6)
5174 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_SET(value) (((value) << 6) & 0x00000fc0)
5185 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_LSB 12
5187 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_MSB 17
5189 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_WIDTH 6
5191 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_SET_MSK 0x0003f000
5193 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_CLR_MSK 0xfffc0fff
5195 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_RESET 0x0
5197 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_GET(value) (((value) & 0x0003f000) >> 12)
5199 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_SET(value) (((value) << 12) & 0x0003f000)
5210 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_LSB 18
5212 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_MSB 23
5214 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_WIDTH 6
5216 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_SET_MSK 0x00fc0000
5218 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_CLR_MSK 0xff03ffff
5220 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_RESET 0x0
5222 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_GET(value) (((value) & 0x00fc0000) >> 18)
5224 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_SET(value) (((value) << 18) & 0x00fc0000)
5235 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_LSB 24
5237 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_MSB 29
5239 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH 6
5241 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_SET_MSK 0x3f000000
5243 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_CLR_MSK 0xc0ffffff
5245 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_RESET 0x0
5247 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_GET(value) (((value) & 0x3f000000) >> 24)
5249 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_SET(value) (((value) << 24) & 0x3f000000)
5251 #ifndef __ASSEMBLY__
5262 struct ALT_IO48_HMC_MMR_CALTIMING2_s
5264 uint32_t cfg_t_param_rd_to_wr_diff_bg : 6;
5265 uint32_t cfg_t_param_rd_to_pch : 6;
5266 uint32_t cfg_t_param_rd_ap_to_valid : 6;
5267 uint32_t cfg_t_param_wr_to_wr : 6;
5268 uint32_t cfg_t_param_wr_to_wr_diff_chip : 6;
5273 typedef volatile struct ALT_IO48_HMC_MMR_CALTIMING2_s ALT_IO48_HMC_MMR_CALTIMING2_t;
5277 #define ALT_IO48_HMC_MMR_CALTIMING2_RESET 0x00000000
5279 #define ALT_IO48_HMC_MMR_CALTIMING2_OFST 0x84
5305 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_LSB 0
5307 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_MSB 5
5309 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_WIDTH 6
5311 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_SET_MSK 0x0000003f
5313 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_CLR_MSK 0xffffffc0
5315 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_RESET 0x0
5317 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_GET(value) (((value) & 0x0000003f) >> 0)
5319 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_SET(value) (((value) << 0) & 0x0000003f)
5330 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_LSB 6
5332 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_MSB 11
5334 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_WIDTH 6
5336 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_SET_MSK 0x00000fc0
5338 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_CLR_MSK 0xfffff03f
5340 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_RESET 0x0
5342 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_GET(value) (((value) & 0x00000fc0) >> 6)
5344 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_SET(value) (((value) << 6) & 0x00000fc0)
5355 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_LSB 12
5357 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_MSB 17
5359 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH 6
5361 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_SET_MSK 0x0003f000
5363 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_CLR_MSK 0xfffc0fff
5365 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_RESET 0x0
5367 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_GET(value) (((value) & 0x0003f000) >> 12)
5369 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_SET(value) (((value) << 12) & 0x0003f000)
5380 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_LSB 18
5382 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_MSB 23
5384 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_WIDTH 6
5386 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_SET_MSK 0x00fc0000
5388 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_CLR_MSK 0xff03ffff
5390 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_RESET 0x0
5392 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_GET(value) (((value) & 0x00fc0000) >> 18)
5394 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_SET(value) (((value) << 18) & 0x00fc0000)
5405 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_LSB 24
5407 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_MSB 29
5409 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_WIDTH 6
5411 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_SET_MSK 0x3f000000
5413 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_CLR_MSK 0xc0ffffff
5415 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_RESET 0x0
5417 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_GET(value) (((value) & 0x3f000000) >> 24)
5419 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_SET(value) (((value) << 24) & 0x3f000000)
5421 #ifndef __ASSEMBLY__
5432 struct ALT_IO48_HMC_MMR_CALTIMING3_s
5434 uint32_t cfg_t_param_wr_to_wr_diff_bg : 6;
5435 uint32_t cfg_t_param_wr_to_rd : 6;
5436 uint32_t cfg_t_param_wr_to_rd_diff_chip : 6;
5437 uint32_t cfg_t_param_wr_to_rd_diff_bg : 6;
5438 uint32_t cfg_t_param_wr_to_pch : 6;
5443 typedef volatile struct ALT_IO48_HMC_MMR_CALTIMING3_s ALT_IO48_HMC_MMR_CALTIMING3_t;
5447 #define ALT_IO48_HMC_MMR_CALTIMING3_RESET 0x00000000
5449 #define ALT_IO48_HMC_MMR_CALTIMING3_OFST 0x88
5474 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_LSB 0
5476 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_MSB 5
5478 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_WIDTH 6
5480 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_SET_MSK 0x0000003f
5482 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_CLR_MSK 0xffffffc0
5484 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_RESET 0x0
5486 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_GET(value) (((value) & 0x0000003f) >> 0)
5488 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_SET(value) (((value) << 0) & 0x0000003f)
5499 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_LSB 6
5501 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_MSB 11
5503 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_WIDTH 6
5505 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_SET_MSK 0x00000fc0
5507 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_CLR_MSK 0xfffff03f
5509 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_RESET 0x0
5511 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_GET(value) (((value) & 0x00000fc0) >> 6)
5513 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_SET(value) (((value) << 6) & 0x00000fc0)
5524 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_LSB 12
5526 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_MSB 17
5528 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_WIDTH 6
5530 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_SET_MSK 0x0003f000
5532 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_CLR_MSK 0xfffc0fff
5534 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_RESET 0x0
5536 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_GET(value) (((value) & 0x0003f000) >> 12)
5538 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_SET(value) (((value) << 12) & 0x0003f000)
5549 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_LSB 18
5551 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_MSB 25
5553 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_WIDTH 8
5555 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_SET_MSK 0x03fc0000
5557 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_CLR_MSK 0xfc03ffff
5559 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_RESET 0x0
5561 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_GET(value) (((value) & 0x03fc0000) >> 18)
5563 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_SET(value) (((value) << 18) & 0x03fc0000)
5574 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_LSB 26
5576 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_MSB 31
5578 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_WIDTH 6
5580 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_SET_MSK 0xfc000000
5582 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_CLR_MSK 0x03ffffff
5584 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_RESET 0x0
5586 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_GET(value) (((value) & 0xfc000000) >> 26)
5588 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_SET(value) (((value) << 26) & 0xfc000000)
5590 #ifndef __ASSEMBLY__
5601 struct ALT_IO48_HMC_MMR_CALTIMING4_s
5603 uint32_t cfg_t_param_wr_ap_to_valid : 6;
5604 uint32_t cfg_t_param_pch_to_valid : 6;
5605 uint32_t cfg_t_param_pch_all_to_valid : 6;
5606 uint32_t cfg_t_param_arf_to_valid : 8;
5607 uint32_t cfg_t_param_pdn_to_valid : 6;
5611 typedef volatile struct ALT_IO48_HMC_MMR_CALTIMING4_s ALT_IO48_HMC_MMR_CALTIMING4_t;
5615 #define ALT_IO48_HMC_MMR_CALTIMING4_RESET 0x00000000
5617 #define ALT_IO48_HMC_MMR_CALTIMING4_OFST 0x8c
5640 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_LSB 0
5642 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_MSB 9
5644 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_WIDTH 10
5646 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_SET_MSK 0x000003ff
5648 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_CLR_MSK 0xfffffc00
5650 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_RESET 0x0
5652 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_GET(value) (((value) & 0x000003ff) >> 0)
5654 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_SET(value) (((value) << 0) & 0x000003ff)
5665 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_LSB 10
5667 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_MSB 19
5669 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_WIDTH 10
5671 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_SET_MSK 0x000ffc00
5673 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_CLR_MSK 0xfff003ff
5675 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_RESET 0x0
5677 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_GET(value) (((value) & 0x000ffc00) >> 10)
5679 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_SET(value) (((value) << 10) & 0x000ffc00)
5681 #ifndef __ASSEMBLY__
5692 struct ALT_IO48_HMC_MMR_CALTIMING5_s
5694 uint32_t cfg_t_param_srf_to_valid : 10;
5695 uint32_t cfg_t_param_srf_to_zq_cal : 10;
5700 typedef volatile struct ALT_IO48_HMC_MMR_CALTIMING5_s ALT_IO48_HMC_MMR_CALTIMING5_t;
5704 #define ALT_IO48_HMC_MMR_CALTIMING5_RESET 0x00000000
5706 #define ALT_IO48_HMC_MMR_CALTIMING5_OFST 0x90
5729 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_LSB 0
5731 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_MSB 12
5733 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_WIDTH 13
5735 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_SET_MSK 0x00001fff
5737 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_CLR_MSK 0xffffe000
5739 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_RESET 0x0
5741 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_GET(value) (((value) & 0x00001fff) >> 0)
5743 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_SET(value) (((value) << 0) & 0x00001fff)
5754 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_LSB 13
5756 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_MSB 28
5758 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_WIDTH 16
5760 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_SET_MSK 0x1fffe000
5762 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_CLR_MSK 0xe0001fff
5764 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_RESET 0x0
5766 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_GET(value) (((value) & 0x1fffe000) >> 13)
5768 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_SET(value) (((value) << 13) & 0x1fffe000)
5770 #ifndef __ASSEMBLY__
5781 struct ALT_IO48_HMC_MMR_CALTIMING6_s
5783 uint32_t cfg_t_param_arf_period : 13;
5784 uint32_t cfg_t_param_pdn_period : 16;
5789 typedef volatile struct ALT_IO48_HMC_MMR_CALTIMING6_s ALT_IO48_HMC_MMR_CALTIMING6_t;
5793 #define ALT_IO48_HMC_MMR_CALTIMING6_RESET 0x00000000
5795 #define ALT_IO48_HMC_MMR_CALTIMING6_OFST 0x94
5820 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_LSB 0
5822 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_MSB 8
5824 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_WIDTH 9
5826 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_SET_MSK 0x000001ff
5828 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_CLR_MSK 0xfffffe00
5830 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_RESET 0x0
5832 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_GET(value) (((value) & 0x000001ff) >> 0)
5834 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_SET(value) (((value) << 0) & 0x000001ff)
5845 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_LSB 9
5847 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_MSB 15
5849 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_WIDTH 7
5851 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_SET_MSK 0x0000fe00
5853 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_CLR_MSK 0xffff01ff
5855 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_RESET 0x0
5857 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_GET(value) (((value) & 0x0000fe00) >> 9)
5859 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_SET(value) (((value) << 9) & 0x0000fe00)
5870 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_LSB 16
5872 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_MSB 19
5874 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_WIDTH 4
5876 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_SET_MSK 0x000f0000
5878 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_CLR_MSK 0xfff0ffff
5880 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_RESET 0x0
5882 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_GET(value) (((value) & 0x000f0000) >> 16)
5884 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_SET(value) (((value) << 16) & 0x000f0000)
5895 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_LSB 20
5897 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_MSB 29
5899 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_WIDTH 10
5901 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_SET_MSK 0x3ff00000
5903 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_CLR_MSK 0xc00fffff
5905 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_RESET 0x0
5907 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_GET(value) (((value) & 0x3ff00000) >> 20)
5909 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_SET(value) (((value) << 20) & 0x3ff00000)
5911 #ifndef __ASSEMBLY__
5922 struct ALT_IO48_HMC_MMR_CALTIMING7_s
5924 uint32_t cfg_t_param_zqcl_to_valid : 9;
5925 uint32_t cfg_t_param_zqcs_to_valid : 7;
5926 uint32_t cfg_t_param_mrs_to_valid : 4;
5927 uint32_t cfg_t_param_mps_to_valid : 10;
5932 typedef volatile struct ALT_IO48_HMC_MMR_CALTIMING7_s ALT_IO48_HMC_MMR_CALTIMING7_t;
5936 #define ALT_IO48_HMC_MMR_CALTIMING7_RESET 0x00000000
5938 #define ALT_IO48_HMC_MMR_CALTIMING7_OFST 0x98
5965 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_LSB 0
5967 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_MSB 3
5969 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_WIDTH 4
5971 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_SET_MSK 0x0000000f
5973 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_CLR_MSK 0xfffffff0
5975 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_RESET 0x0
5977 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_GET(value) (((value) & 0x0000000f) >> 0)
5979 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_SET(value) (((value) << 0) & 0x0000000f)
5990 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_LSB 4
5992 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_MSB 8
5994 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_WIDTH 5
5996 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_SET_MSK 0x000001f0
5998 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_CLR_MSK 0xfffffe0f
6000 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_RESET 0x0
6002 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_GET(value) (((value) & 0x000001f0) >> 4)
6004 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_SET(value) (((value) << 4) & 0x000001f0)
6016 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_LSB 9
6018 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_MSB 12
6020 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_WIDTH 4
6022 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_SET_MSK 0x00001e00
6024 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_CLR_MSK 0xffffe1ff
6026 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_RESET 0x0
6028 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_GET(value) (((value) & 0x00001e00) >> 9)
6030 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_SET(value) (((value) << 9) & 0x00001e00)
6042 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_LSB 13
6044 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_MSB 16
6046 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_WIDTH 4
6048 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_SET_MSK 0x0001e000
6050 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_CLR_MSK 0xfffe1fff
6052 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_RESET 0x0
6054 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_GET(value) (((value) & 0x0001e000) >> 13)
6056 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_SET(value) (((value) << 13) & 0x0001e000)
6067 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_LSB 17
6069 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_MSB 19
6071 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_WIDTH 3
6073 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_SET_MSK 0x000e0000
6075 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_CLR_MSK 0xfff1ffff
6077 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_RESET 0x0
6079 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_GET(value) (((value) & 0x000e0000) >> 17)
6081 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_SET(value) (((value) << 17) & 0x000e0000)
6092 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_LSB 20
6094 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_MSB 27
6096 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_WIDTH 8
6098 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_SET_MSK 0x0ff00000
6100 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_CLR_MSK 0xf00fffff
6102 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_RESET 0x0
6104 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_GET(value) (((value) & 0x0ff00000) >> 20)
6106 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_SET(value) (((value) << 20) & 0x0ff00000)
6108 #ifndef __ASSEMBLY__
6119 struct ALT_IO48_HMC_MMR_CALTIMING8_s
6121 uint32_t cfg_t_param_mrr_to_valid : 4;
6122 uint32_t cfg_t_param_mpr_to_valid : 5;
6123 uint32_t cfg_t_param_mps_exit_cs_to_cke : 4;
6124 uint32_t cfg_t_param_mps_exit_cke_to_cs : 4;
6125 uint32_t cfg_t_param_rld3_multibank_ref_delay : 3;
6126 uint32_t cfg_t_param_mmr_cmd_to_valid : 8;
6131 typedef volatile struct ALT_IO48_HMC_MMR_CALTIMING8_s ALT_IO48_HMC_MMR_CALTIMING8_t;
6135 #define ALT_IO48_HMC_MMR_CALTIMING8_RESET 0x00000000
6137 #define ALT_IO48_HMC_MMR_CALTIMING8_OFST 0x9c
6159 #define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_LSB 0
6161 #define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_MSB 7
6163 #define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_WIDTH 8
6165 #define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_SET_MSK 0x000000ff
6167 #define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_CLR_MSK 0xffffff00
6169 #define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_RESET 0x0
6171 #define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_GET(value) (((value) & 0x000000ff) >> 0)
6173 #define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_SET(value) (((value) << 0) & 0x000000ff)
6175 #ifndef __ASSEMBLY__
6186 struct ALT_IO48_HMC_MMR_CALTIMING9_s
6188 uint32_t cfg_t_param_4_act_to_act : 8;
6193 typedef volatile struct ALT_IO48_HMC_MMR_CALTIMING9_s ALT_IO48_HMC_MMR_CALTIMING9_t;
6197 #define ALT_IO48_HMC_MMR_CALTIMING9_RESET 0x00000000
6199 #define ALT_IO48_HMC_MMR_CALTIMING9_OFST 0xa0
6221 #define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_LSB 0
6223 #define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_MSB 7
6225 #define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_WIDTH 8
6227 #define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_SET_MSK 0x000000ff
6229 #define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_CLR_MSK 0xffffff00
6231 #define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_RESET 0x0
6233 #define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_GET(value) (((value) & 0x000000ff) >> 0)
6235 #define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_SET(value) (((value) << 0) & 0x000000ff)
6237 #ifndef __ASSEMBLY__
6248 struct ALT_IO48_HMC_MMR_CALTIMING10_s
6250 uint32_t cfg_t_param_16_act_to_act : 8;
6255 typedef volatile struct ALT_IO48_HMC_MMR_CALTIMING10_s ALT_IO48_HMC_MMR_CALTIMING10_t;
6259 #define ALT_IO48_HMC_MMR_CALTIMING10_RESET 0x00000000
6261 #define ALT_IO48_HMC_MMR_CALTIMING10_OFST 0xa4
6288 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_LSB 0
6290 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MSB 4
6292 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_WIDTH 5
6294 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_SET_MSK 0x0000001f
6296 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_CLR_MSK 0xffffffe0
6298 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_RESET 0x0
6300 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_GET(value) (((value) & 0x0000001f) >> 0)
6302 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_SET(value) (((value) << 0) & 0x0000001f)
6313 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_LSB 5
6315 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MSB 9
6317 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_WIDTH 5
6319 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SET_MSK 0x000003e0
6321 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_CLR_MSK 0xfffffc1f
6323 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_RESET 0x0
6325 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_GET(value) (((value) & 0x000003e0) >> 5)
6327 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SET(value) (((value) << 5) & 0x000003e0)
6338 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_LSB 10
6340 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MSB 13
6342 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_WIDTH 4
6344 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SET_MSK 0x00003c00
6346 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_CLR_MSK 0xffffc3ff
6348 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_RESET 0x0
6350 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_GET(value) (((value) & 0x00003c00) >> 10)
6352 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SET(value) (((value) << 10) & 0x00003c00)
6364 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_LSB 14
6366 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MSB 15
6368 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_WIDTH 2
6370 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SET_MSK 0x0000c000
6372 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_CLR_MSK 0xffff3fff
6374 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_RESET 0x0
6376 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_GET(value) (((value) & 0x0000c000) >> 14)
6378 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SET(value) (((value) << 14) & 0x0000c000)
6390 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_LSB 16
6392 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MSB 18
6394 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_WIDTH 3
6396 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SET_MSK 0x00070000
6398 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_CLR_MSK 0xfff8ffff
6400 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_RESET 0x0
6402 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_GET(value) (((value) & 0x00070000) >> 16)
6404 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SET(value) (((value) << 16) & 0x00070000)
6406 #ifndef __ASSEMBLY__
6417 struct ALT_IO48_HMC_MMR_DRAMADDRW_s
6419 uint32_t cfg_col_addr_width : 5;
6420 uint32_t cfg_row_addr_width : 5;
6421 uint32_t cfg_bank_addr_width : 4;
6422 uint32_t cfg_bank_group_addr_width : 2;
6423 uint32_t cfg_cs_addr_width : 3;
6428 typedef volatile struct ALT_IO48_HMC_MMR_DRAMADDRW_s ALT_IO48_HMC_MMR_DRAMADDRW_t;
6432 #define ALT_IO48_HMC_MMR_DRAMADDRW_RESET 0x00000000
6434 #define ALT_IO48_HMC_MMR_DRAMADDRW_OFST 0xa8
6456 #define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_LSB 0
6458 #define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_MSB 0
6460 #define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_WIDTH 1
6462 #define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_SET_MSK 0x00000001
6464 #define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_CLR_MSK 0xfffffffe
6466 #define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_RESET 0x0
6468 #define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_GET(value) (((value) & 0x00000001) >> 0)
6470 #define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_SET(value) (((value) << 0) & 0x00000001)
6472 #ifndef __ASSEMBLY__
6483 struct ALT_IO48_HMC_MMR_SIDEBAND0_s
6485 uint32_t mr_cmd_trigger : 1;
6490 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND0_s ALT_IO48_HMC_MMR_SIDEBAND0_t;
6494 #define ALT_IO48_HMC_MMR_SIDEBAND0_RESET 0x00000000
6496 #define ALT_IO48_HMC_MMR_SIDEBAND0_OFST 0xac
6519 #define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_LSB 0
6521 #define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_MSB 3
6523 #define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_WIDTH 4
6525 #define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_SET_MSK 0x0000000f
6527 #define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_CLR_MSK 0xfffffff0
6529 #define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_RESET 0x0
6531 #define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_GET(value) (((value) & 0x0000000f) >> 0)
6533 #define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_SET(value) (((value) << 0) & 0x0000000f)
6535 #ifndef __ASSEMBLY__
6546 struct ALT_IO48_HMC_MMR_SIDEBAND1_s
6548 uint32_t mmr_refresh_req : 4;
6553 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND1_s ALT_IO48_HMC_MMR_SIDEBAND1_t;
6557 #define ALT_IO48_HMC_MMR_SIDEBAND1_RESET 0x00000000
6559 #define ALT_IO48_HMC_MMR_SIDEBAND1_OFST 0xb0
6581 #define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_LSB 0
6583 #define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_MSB 0
6585 #define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_WIDTH 1
6587 #define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_SET_MSK 0x00000001
6589 #define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_CLR_MSK 0xfffffffe
6591 #define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_RESET 0x0
6593 #define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_GET(value) (((value) & 0x00000001) >> 0)
6595 #define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_SET(value) (((value) << 0) & 0x00000001)
6597 #ifndef __ASSEMBLY__
6608 struct ALT_IO48_HMC_MMR_SIDEBAND2_s
6610 uint32_t mmr_zqcal_long_req : 1;
6615 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND2_s ALT_IO48_HMC_MMR_SIDEBAND2_t;
6619 #define ALT_IO48_HMC_MMR_SIDEBAND2_RESET 0x00000000
6621 #define ALT_IO48_HMC_MMR_SIDEBAND2_OFST 0xb4
6643 #define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_LSB 0
6645 #define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_MSB 0
6647 #define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_WIDTH 1
6649 #define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_SET_MSK 0x00000001
6651 #define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_CLR_MSK 0xfffffffe
6653 #define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_RESET 0x0
6655 #define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_GET(value) (((value) & 0x00000001) >> 0)
6657 #define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_SET(value) (((value) << 0) & 0x00000001)
6659 #ifndef __ASSEMBLY__
6670 struct ALT_IO48_HMC_MMR_SIDEBAND3_s
6672 uint32_t mmr_zqcal_short_req : 1;
6677 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND3_s ALT_IO48_HMC_MMR_SIDEBAND3_t;
6681 #define ALT_IO48_HMC_MMR_SIDEBAND3_RESET 0x00000000
6683 #define ALT_IO48_HMC_MMR_SIDEBAND3_OFST 0xb8
6706 #define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_LSB 0
6708 #define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_MSB 3
6710 #define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_WIDTH 4
6712 #define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_SET_MSK 0x0000000f
6714 #define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_CLR_MSK 0xfffffff0
6716 #define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_RESET 0x0
6718 #define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_GET(value) (((value) & 0x0000000f) >> 0)
6720 #define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_SET(value) (((value) << 0) & 0x0000000f)
6722 #ifndef __ASSEMBLY__
6733 struct ALT_IO48_HMC_MMR_SIDEBAND4_s
6735 uint32_t mmr_self_rfsh_req : 4;
6740 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND4_s ALT_IO48_HMC_MMR_SIDEBAND4_t;
6744 #define ALT_IO48_HMC_MMR_SIDEBAND4_RESET 0x00000000
6746 #define ALT_IO48_HMC_MMR_SIDEBAND4_OFST 0xbc
6769 #define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_LSB 0
6771 #define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_MSB 0
6773 #define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_WIDTH 1
6775 #define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_SET_MSK 0x00000001
6777 #define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_CLR_MSK 0xfffffffe
6779 #define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_RESET 0x0
6781 #define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_GET(value) (((value) & 0x00000001) >> 0)
6783 #define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_SET(value) (((value) << 0) & 0x00000001)
6785 #ifndef __ASSEMBLY__
6796 struct ALT_IO48_HMC_MMR_SIDEBAND5_s
6798 uint32_t mmr_dpd_mps_req : 1;
6803 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND5_s ALT_IO48_HMC_MMR_SIDEBAND5_t;
6807 #define ALT_IO48_HMC_MMR_SIDEBAND5_RESET 0x00000000
6809 #define ALT_IO48_HMC_MMR_SIDEBAND5_OFST 0xc0
6831 #define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_LSB 0
6833 #define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_MSB 0
6835 #define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_WIDTH 1
6837 #define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_SET_MSK 0x00000001
6839 #define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_CLR_MSK 0xfffffffe
6841 #define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_RESET 0x0
6843 #define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_GET(value) (((value) & 0x00000001) >> 0)
6845 #define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_SET(value) (((value) << 0) & 0x00000001)
6847 #ifndef __ASSEMBLY__
6858 struct ALT_IO48_HMC_MMR_SIDEBAND6_s
6860 uint32_t mr_cmd_ack : 1;
6865 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND6_s ALT_IO48_HMC_MMR_SIDEBAND6_t;
6869 #define ALT_IO48_HMC_MMR_SIDEBAND6_RESET 0x00000000
6871 #define ALT_IO48_HMC_MMR_SIDEBAND6_OFST 0xc4
6893 #define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_LSB 0
6895 #define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_MSB 0
6897 #define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_WIDTH 1
6899 #define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_SET_MSK 0x00000001
6901 #define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_CLR_MSK 0xfffffffe
6903 #define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_RESET 0x0
6905 #define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_GET(value) (((value) & 0x00000001) >> 0)
6907 #define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_SET(value) (((value) << 0) & 0x00000001)
6909 #ifndef __ASSEMBLY__
6920 struct ALT_IO48_HMC_MMR_SIDEBAND7_s
6922 uint32_t mmr_refresh_ack : 1;
6927 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND7_s ALT_IO48_HMC_MMR_SIDEBAND7_t;
6931 #define ALT_IO48_HMC_MMR_SIDEBAND7_RESET 0x00000000
6933 #define ALT_IO48_HMC_MMR_SIDEBAND7_OFST 0xc8
6955 #define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_LSB 0
6957 #define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_MSB 0
6959 #define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_WIDTH 1
6961 #define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_SET_MSK 0x00000001
6963 #define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_CLR_MSK 0xfffffffe
6965 #define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_RESET 0x0
6967 #define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_GET(value) (((value) & 0x00000001) >> 0)
6969 #define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_SET(value) (((value) << 0) & 0x00000001)
6971 #ifndef __ASSEMBLY__
6982 struct ALT_IO48_HMC_MMR_SIDEBAND8_s
6984 uint32_t mmr_zqcal_ack : 1;
6989 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND8_s ALT_IO48_HMC_MMR_SIDEBAND8_t;
6993 #define ALT_IO48_HMC_MMR_SIDEBAND8_RESET 0x00000000
6995 #define ALT_IO48_HMC_MMR_SIDEBAND8_OFST 0xcc
7017 #define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_LSB 0
7019 #define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_MSB 0
7021 #define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_WIDTH 1
7023 #define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_SET_MSK 0x00000001
7025 #define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_CLR_MSK 0xfffffffe
7027 #define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_RESET 0x0
7029 #define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_GET(value) (((value) & 0x00000001) >> 0)
7031 #define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_SET(value) (((value) << 0) & 0x00000001)
7033 #ifndef __ASSEMBLY__
7044 struct ALT_IO48_HMC_MMR_SIDEBAND9_s
7046 uint32_t mmr_self_rfsh_ack : 1;
7051 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND9_s ALT_IO48_HMC_MMR_SIDEBAND9_t;
7055 #define ALT_IO48_HMC_MMR_SIDEBAND9_RESET 0x00000000
7057 #define ALT_IO48_HMC_MMR_SIDEBAND9_OFST 0xd0
7079 #define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_LSB 0
7081 #define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_MSB 0
7083 #define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_WIDTH 1
7085 #define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_SET_MSK 0x00000001
7087 #define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_CLR_MSK 0xfffffffe
7089 #define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_RESET 0x0
7091 #define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_GET(value) (((value) & 0x00000001) >> 0)
7093 #define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_SET(value) (((value) << 0) & 0x00000001)
7095 #ifndef __ASSEMBLY__
7106 struct ALT_IO48_HMC_MMR_SIDEBAND10_s
7108 uint32_t mmr_dpd_mps_ack : 1;
7113 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND10_s ALT_IO48_HMC_MMR_SIDEBAND10_t;
7117 #define ALT_IO48_HMC_MMR_SIDEBAND10_RESET 0x00000000
7119 #define ALT_IO48_HMC_MMR_SIDEBAND10_OFST 0xd4
7141 #define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_LSB 0
7143 #define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_MSB 0
7145 #define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_WIDTH 1
7147 #define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_SET_MSK 0x00000001
7149 #define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_CLR_MSK 0xfffffffe
7151 #define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_RESET 0x0
7153 #define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_GET(value) (((value) & 0x00000001) >> 0)
7155 #define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_SET(value) (((value) << 0) & 0x00000001)
7157 #ifndef __ASSEMBLY__
7168 struct ALT_IO48_HMC_MMR_SIDEBAND11_s
7170 uint32_t mmr_auto_pd_ack : 1;
7175 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND11_s ALT_IO48_HMC_MMR_SIDEBAND11_t;
7179 #define ALT_IO48_HMC_MMR_SIDEBAND11_RESET 0x00000000
7181 #define ALT_IO48_HMC_MMR_SIDEBAND11_OFST 0xd8
7204 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_LSB 0
7206 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_MSB 2
7208 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_WIDTH 3
7210 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_SET_MSK 0x00000007
7212 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_CLR_MSK 0xfffffff8
7214 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_RESET 0x0
7216 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_GET(value) (((value) & 0x00000007) >> 0)
7218 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_SET(value) (((value) << 0) & 0x00000007)
7229 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_LSB 3
7231 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_MSB 6
7233 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_WIDTH 4
7235 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_SET_MSK 0x00000078
7237 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_CLR_MSK 0xffffff87
7239 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_RESET 0x0
7241 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_GET(value) (((value) & 0x00000078) >> 3)
7243 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_SET(value) (((value) << 3) & 0x00000078)
7245 #ifndef __ASSEMBLY__
7256 struct ALT_IO48_HMC_MMR_SIDEBAND12_s
7258 uint32_t mr_cmd_type : 3;
7259 uint32_t mr_cmd_rank : 4;
7264 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND12_s ALT_IO48_HMC_MMR_SIDEBAND12_t;
7268 #define ALT_IO48_HMC_MMR_SIDEBAND12_RESET 0x00000000
7270 #define ALT_IO48_HMC_MMR_SIDEBAND12_OFST 0xdc
7296 #define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_LSB 0
7298 #define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_MSB 31
7300 #define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_WIDTH 32
7302 #define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_SET_MSK 0xffffffff
7304 #define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_CLR_MSK 0x00000000
7306 #define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_RESET 0x0
7308 #define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_GET(value) (((value) & 0xffffffff) >> 0)
7310 #define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_SET(value) (((value) << 0) & 0xffffffff)
7312 #ifndef __ASSEMBLY__
7323 struct ALT_IO48_HMC_MMR_SIDEBAND13_s
7325 uint32_t mr_cmd_opcode : 32;
7329 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND13_s ALT_IO48_HMC_MMR_SIDEBAND13_t;
7333 #define ALT_IO48_HMC_MMR_SIDEBAND13_RESET 0x00000000
7335 #define ALT_IO48_HMC_MMR_SIDEBAND13_OFST 0xe0
7358 #define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_LSB 0
7360 #define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_MSB 15
7362 #define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_WIDTH 16
7364 #define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_SET_MSK 0x0000ffff
7366 #define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_CLR_MSK 0xffff0000
7368 #define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_RESET 0x0
7370 #define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_GET(value) (((value) & 0x0000ffff) >> 0)
7372 #define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_SET(value) (((value) << 0) & 0x0000ffff)
7374 #ifndef __ASSEMBLY__
7385 struct ALT_IO48_HMC_MMR_SIDEBAND14_s
7387 uint32_t mmr_refresh_bank : 16;
7392 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND14_s ALT_IO48_HMC_MMR_SIDEBAND14_t;
7396 #define ALT_IO48_HMC_MMR_SIDEBAND14_RESET 0x00000000
7398 #define ALT_IO48_HMC_MMR_SIDEBAND14_OFST 0xe4
7420 #define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_LSB 0
7422 #define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_MSB 3
7424 #define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_WIDTH 4
7426 #define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_SET_MSK 0x0000000f
7428 #define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_CLR_MSK 0xfffffff0
7430 #define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_RESET 0x0
7432 #define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_GET(value) (((value) & 0x0000000f) >> 0)
7434 #define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_SET(value) (((value) << 0) & 0x0000000f)
7436 #ifndef __ASSEMBLY__
7447 struct ALT_IO48_HMC_MMR_SIDEBAND15_s
7449 uint32_t mmr_stall_rank : 4;
7454 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND15_s ALT_IO48_HMC_MMR_SIDEBAND15_t;
7458 #define ALT_IO48_HMC_MMR_SIDEBAND15_RESET 0x00000000
7460 #define ALT_IO48_HMC_MMR_SIDEBAND15_OFST 0xe8
7483 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_LSB 0
7485 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_MSB 0
7487 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_WIDTH 1
7489 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_SET_MSK 0x00000001
7491 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_CLR_MSK 0xfffffffe
7493 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_RESET 0x0
7495 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_GET(value) (((value) & 0x00000001) >> 0)
7497 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_SET(value) (((value) << 0) & 0x00000001)
7508 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_LSB 1
7510 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_MSB 1
7512 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_WIDTH 1
7514 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_SET_MSK 0x00000002
7516 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_CLR_MSK 0xfffffffd
7518 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_RESET 0x0
7520 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_GET(value) (((value) & 0x00000002) >> 1)
7522 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_SET(value) (((value) << 1) & 0x00000002)
7524 #ifndef __ASSEMBLY__
7535 struct ALT_IO48_HMC_MMR_DRAMSTS_s
7537 uint32_t phy_cal_success : 1;
7538 uint32_t phy_cal_fail : 1;
7543 typedef volatile struct ALT_IO48_HMC_MMR_DRAMSTS_s ALT_IO48_HMC_MMR_DRAMSTS_t;
7547 #define ALT_IO48_HMC_MMR_DRAMSTS_RESET 0x00000000
7549 #define ALT_IO48_HMC_MMR_DRAMSTS_OFST 0xec
7571 #define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_LSB 0
7573 #define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_MSB 0
7575 #define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_WIDTH 1
7577 #define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_SET_MSK 0x00000001
7579 #define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_CLR_MSK 0xfffffffe
7581 #define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_RESET 0x0
7583 #define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_GET(value) (((value) & 0x00000001) >> 0)
7585 #define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_SET(value) (((value) << 0) & 0x00000001)
7587 #ifndef __ASSEMBLY__
7598 struct ALT_IO48_HMC_MMR_DBGDONE_s
7600 uint32_t dbg_done : 1;
7605 typedef volatile struct ALT_IO48_HMC_MMR_DBGDONE_s ALT_IO48_HMC_MMR_DBGDONE_t;
7609 #define ALT_IO48_HMC_MMR_DBGDONE_RESET 0x00000000
7611 #define ALT_IO48_HMC_MMR_DBGDONE_OFST 0xf0
7632 #define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_LSB 0
7634 #define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_MSB 31
7636 #define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_WIDTH 32
7638 #define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_SET_MSK 0xffffffff
7640 #define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_CLR_MSK 0x00000000
7642 #define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_RESET 0x0
7644 #define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_GET(value) (((value) & 0xffffffff) >> 0)
7646 #define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_SET(value) (((value) << 0) & 0xffffffff)
7648 #ifndef __ASSEMBLY__
7659 struct ALT_IO48_HMC_MMR_DBGSIGNALS_s
7661 uint32_t dbg_signals_out : 32;
7665 typedef volatile struct ALT_IO48_HMC_MMR_DBGSIGNALS_s ALT_IO48_HMC_MMR_DBGSIGNALS_t;
7669 #define ALT_IO48_HMC_MMR_DBGSIGNALS_RESET 0x00000000
7671 #define ALT_IO48_HMC_MMR_DBGSIGNALS_OFST 0xf4
7695 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_LSB 0
7697 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_MSB 0
7699 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_WIDTH 1
7701 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_SET_MSK 0x00000001
7703 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_CLR_MSK 0xfffffffe
7705 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_RESET 0x0
7707 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_GET(value) (((value) & 0x00000001) >> 0)
7709 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_SET(value) (((value) << 0) & 0x00000001)
7721 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_LSB 1
7723 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_MSB 1
7725 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_WIDTH 1
7727 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_SET_MSK 0x00000002
7729 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_CLR_MSK 0xfffffffd
7731 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_RESET 0x0
7733 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_GET(value) (((value) & 0x00000002) >> 1)
7735 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_SET(value) (((value) << 1) & 0x00000002)
7737 #ifndef __ASSEMBLY__
7748 struct ALT_IO48_HMC_MMR_DBGRST_s
7750 uint32_t counter_zero_reset : 1;
7751 uint32_t counter_one_reset : 1;
7756 typedef volatile struct ALT_IO48_HMC_MMR_DBGRST_s ALT_IO48_HMC_MMR_DBGRST_t;
7760 #define ALT_IO48_HMC_MMR_DBGRST_RESET 0x00000000
7762 #define ALT_IO48_HMC_MMR_DBGRST_OFST 0xf8
7784 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_LSB 0
7786 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_MSB 15
7788 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_WIDTH 16
7790 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_SET_MSK 0x0000ffff
7792 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_CLR_MSK 0xffff0000
7794 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_RESET 0x0
7796 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_GET(value) (((value) & 0x0000ffff) >> 0)
7798 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_SET(value) (((value) << 0) & 0x0000ffff)
7809 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_LSB 16
7811 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_MSB 31
7813 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_WIDTH 16
7815 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_SET_MSK 0xffff0000
7817 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_CLR_MSK 0x0000ffff
7819 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_RESET 0x0
7821 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_GET(value) (((value) & 0xffff0000) >> 16)
7823 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_SET(value) (((value) << 16) & 0xffff0000)
7825 #ifndef __ASSEMBLY__
7836 struct ALT_IO48_HMC_MMR_DBGMATCH_s
7838 uint32_t counter_zero : 16;
7839 uint32_t counter_one : 16;
7843 typedef volatile struct ALT_IO48_HMC_MMR_DBGMATCH_s ALT_IO48_HMC_MMR_DBGMATCH_t;
7847 #define ALT_IO48_HMC_MMR_DBGMATCH_RESET 0x00000000
7849 #define ALT_IO48_HMC_MMR_DBGMATCH_OFST 0xfc
7872 #define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_LSB 0
7874 #define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_MSB 31
7876 #define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_WIDTH 32
7878 #define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_SET_MSK 0xffffffff
7880 #define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_CLR_MSK 0x00000000
7882 #define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_RESET 0x0
7884 #define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_GET(value) (((value) & 0xffffffff) >> 0)
7886 #define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_SET(value) (((value) << 0) & 0xffffffff)
7888 #ifndef __ASSEMBLY__
7899 struct ALT_IO48_HMC_MMR_CNTR0MSK_s
7901 uint32_t counter_zero_mask : 32;
7905 typedef volatile struct ALT_IO48_HMC_MMR_CNTR0MSK_s ALT_IO48_HMC_MMR_CNTR0MSK_t;
7909 #define ALT_IO48_HMC_MMR_CNTR0MSK_RESET 0x00000000
7911 #define ALT_IO48_HMC_MMR_CNTR0MSK_OFST 0x100
7934 #define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_LSB 0
7936 #define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_MSB 31
7938 #define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_WIDTH 32
7940 #define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_SET_MSK 0xffffffff
7942 #define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_CLR_MSK 0x00000000
7944 #define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_RESET 0x0
7946 #define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_GET(value) (((value) & 0xffffffff) >> 0)
7948 #define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_SET(value) (((value) << 0) & 0xffffffff)
7950 #ifndef __ASSEMBLY__
7961 struct ALT_IO48_HMC_MMR_CNTR1MSK_s
7963 uint32_t counter_one_mask : 32;
7967 typedef volatile struct ALT_IO48_HMC_MMR_CNTR1MSK_s ALT_IO48_HMC_MMR_CNTR1MSK_t;
7971 #define ALT_IO48_HMC_MMR_CNTR1MSK_RESET 0x00000000
7973 #define ALT_IO48_HMC_MMR_CNTR1MSK_OFST 0x104
7995 #define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_LSB 0
7997 #define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_MSB 31
7999 #define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_WIDTH 32
8001 #define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_SET_MSK 0xffffffff
8003 #define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_CLR_MSK 0x00000000
8005 #define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_RESET 0x0
8007 #define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_GET(value) (((value) & 0xffffffff) >> 0)
8009 #define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_SET(value) (((value) << 0) & 0xffffffff)
8011 #ifndef __ASSEMBLY__
8022 struct ALT_IO48_HMC_MMR_CNTR0MATCH_s
8024 uint32_t counter_zero_match : 32;
8028 typedef volatile struct ALT_IO48_HMC_MMR_CNTR0MATCH_s ALT_IO48_HMC_MMR_CNTR0MATCH_t;
8032 #define ALT_IO48_HMC_MMR_CNTR0MATCH_RESET 0x00000000
8034 #define ALT_IO48_HMC_MMR_CNTR0MATCH_OFST 0x108
8056 #define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_LSB 0
8058 #define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_MSB 31
8060 #define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_WIDTH 32
8062 #define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_SET_MSK 0xffffffff
8064 #define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_CLR_MSK 0x00000000
8066 #define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_RESET 0x0
8068 #define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_GET(value) (((value) & 0xffffffff) >> 0)
8070 #define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_SET(value) (((value) << 0) & 0xffffffff)
8072 #ifndef __ASSEMBLY__
8083 struct ALT_IO48_HMC_MMR_CNTR1MATCH_s
8085 uint32_t counter_one_match : 32;
8089 typedef volatile struct ALT_IO48_HMC_MMR_CNTR1MATCH_s ALT_IO48_HMC_MMR_CNTR1MATCH_t;
8093 #define ALT_IO48_HMC_MMR_CNTR1MATCH_RESET 0x00000000
8095 #define ALT_IO48_HMC_MMR_CNTR1MATCH_OFST 0x10c
8117 #define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_LSB 0
8119 #define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_MSB 15
8121 #define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_WIDTH 16
8123 #define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_SET_MSK 0x0000ffff
8125 #define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_CLR_MSK 0xffff0000
8127 #define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_RESET 0x0
8129 #define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_GET(value) (((value) & 0x0000ffff) >> 0)
8131 #define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_SET(value) (((value) << 0) & 0x0000ffff)
8133 #ifndef __ASSEMBLY__
8144 struct ALT_IO48_HMC_MMR_NIOSRESERVE0_s
8146 uint32_t nios_reserve0 : 16;
8151 typedef volatile struct ALT_IO48_HMC_MMR_NIOSRESERVE0_s ALT_IO48_HMC_MMR_NIOSRESERVE0_t;
8155 #define ALT_IO48_HMC_MMR_NIOSRESERVE0_RESET 0x00000000
8157 #define ALT_IO48_HMC_MMR_NIOSRESERVE0_OFST 0x110
8179 #define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_LSB 0
8181 #define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_MSB 15
8183 #define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_WIDTH 16
8185 #define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_SET_MSK 0x0000ffff
8187 #define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_CLR_MSK 0xffff0000
8189 #define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_RESET 0x0
8191 #define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_GET(value) (((value) & 0x0000ffff) >> 0)
8193 #define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_SET(value) (((value) << 0) & 0x0000ffff)
8195 #ifndef __ASSEMBLY__
8206 struct ALT_IO48_HMC_MMR_NIOSRESERVE1_s
8208 uint32_t nios_reserve1 : 16;
8213 typedef volatile struct ALT_IO48_HMC_MMR_NIOSRESERVE1_s ALT_IO48_HMC_MMR_NIOSRESERVE1_t;
8217 #define ALT_IO48_HMC_MMR_NIOSRESERVE1_RESET 0x00000000
8219 #define ALT_IO48_HMC_MMR_NIOSRESERVE1_OFST 0x114
8241 #define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_LSB 0
8243 #define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_MSB 15
8245 #define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_WIDTH 16
8247 #define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_SET_MSK 0x0000ffff
8249 #define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_CLR_MSK 0xffff0000
8251 #define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_RESET 0x0
8253 #define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_GET(value) (((value) & 0x0000ffff) >> 0)
8255 #define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_SET(value) (((value) << 0) & 0x0000ffff)
8257 #ifndef __ASSEMBLY__
8268 struct ALT_IO48_HMC_MMR_NIOSRESERVE2_s
8270 uint32_t nios_reserve2 : 16;
8275 typedef volatile struct ALT_IO48_HMC_MMR_NIOSRESERVE2_s ALT_IO48_HMC_MMR_NIOSRESERVE2_t;
8279 #define ALT_IO48_HMC_MMR_NIOSRESERVE2_RESET 0x00000000
8281 #define ALT_IO48_HMC_MMR_NIOSRESERVE2_OFST 0x118
8283 #ifndef __ASSEMBLY__
8294 struct ALT_IO48_HMC_MMR_s
8296 ALT_IO48_HMC_MMR_DBGCFG0_t dbgcfg0;
8297 ALT_IO48_HMC_MMR_DBGCFG1_t dbgcfg1;
8298 ALT_IO48_HMC_MMR_DBGCFG2_t dbgcfg2;
8299 ALT_IO48_HMC_MMR_DBGCFG3_t dbgcfg3;
8300 ALT_IO48_HMC_MMR_DBGCFG4_t dbgcfg4;
8301 ALT_IO48_HMC_MMR_DBGCFG5_t dbgcfg5;
8302 ALT_IO48_HMC_MMR_DBGCFG6_t dbgcfg6;
8303 ALT_IO48_HMC_MMR_RESERVE0_t reserve0;
8304 ALT_IO48_HMC_MMR_RESERVE1_t reserve1;
8305 ALT_IO48_HMC_MMR_RESERVE2_t reserve2;
8306 ALT_IO48_HMC_MMR_CTLCFG0_t ctrlcfg0;
8307 ALT_IO48_HMC_MMR_CTLCFG1_t ctrlcfg1;
8308 ALT_IO48_HMC_MMR_CTLCFG2_t ctrlcfg2;
8309 ALT_IO48_HMC_MMR_CTLCFG3_t ctrlcfg3;
8310 ALT_IO48_HMC_MMR_CTLCFG4_t ctrlcfg4;
8311 ALT_IO48_HMC_MMR_CTLCFG5_t ctrlcfg5;
8312 ALT_IO48_HMC_MMR_CTLCFG6_t ctrlcfg6;
8313 ALT_IO48_HMC_MMR_CTLCFG7_t ctrlcfg7;
8314 ALT_IO48_HMC_MMR_CTLCFG8_t ctrlcfg8;
8315 ALT_IO48_HMC_MMR_CTLCFG9_t ctrlcfg9;
8316 ALT_IO48_HMC_MMR_DRAMTIMING0_t dramtiming0;
8317 ALT_IO48_HMC_MMR_DRAMODT0_t dramodt0;
8318 ALT_IO48_HMC_MMR_DRAMODT1_t dramodt1;
8319 ALT_IO48_HMC_MMR_SBCFG0_t sbcfg0;
8320 ALT_IO48_HMC_MMR_SBCFG1_t sbcfg1;
8321 ALT_IO48_HMC_MMR_SBCFG2_t sbcfg2;
8322 ALT_IO48_HMC_MMR_SBCFG3_t sbcfg3;
8323 ALT_IO48_HMC_MMR_SBCFG4_t sbcfg4;
8324 ALT_IO48_HMC_MMR_SBCFG5_t sbcfg5;
8325 ALT_IO48_HMC_MMR_SBCFG6_t sbcfg6;
8326 ALT_IO48_HMC_MMR_SBCFG7_t sbcfg7;
8327 ALT_IO48_HMC_MMR_CALTIMING0_t caltiming0;
8328 ALT_IO48_HMC_MMR_CALTIMING1_t caltiming1;
8329 ALT_IO48_HMC_MMR_CALTIMING2_t caltiming2;
8330 ALT_IO48_HMC_MMR_CALTIMING3_t caltiming3;
8331 ALT_IO48_HMC_MMR_CALTIMING4_t caltiming4;
8332 ALT_IO48_HMC_MMR_CALTIMING5_t caltiming5;
8333 ALT_IO48_HMC_MMR_CALTIMING6_t caltiming6;
8334 ALT_IO48_HMC_MMR_CALTIMING7_t caltiming7;
8335 ALT_IO48_HMC_MMR_CALTIMING8_t caltiming8;
8336 ALT_IO48_HMC_MMR_CALTIMING9_t caltiming9;
8337 ALT_IO48_HMC_MMR_CALTIMING10_t caltiming10;
8338 ALT_IO48_HMC_MMR_DRAMADDRW_t dramaddrw;
8339 ALT_IO48_HMC_MMR_SIDEBAND0_t sideband0;
8340 ALT_IO48_HMC_MMR_SIDEBAND1_t sideband1;
8341 ALT_IO48_HMC_MMR_SIDEBAND2_t sideband2;
8342 ALT_IO48_HMC_MMR_SIDEBAND3_t sideband3;
8343 ALT_IO48_HMC_MMR_SIDEBAND4_t sideband4;
8344 ALT_IO48_HMC_MMR_SIDEBAND5_t sideband5;
8345 ALT_IO48_HMC_MMR_SIDEBAND6_t sideband6;
8346 ALT_IO48_HMC_MMR_SIDEBAND7_t sideband7;
8347 ALT_IO48_HMC_MMR_SIDEBAND8_t sideband8;
8348 ALT_IO48_HMC_MMR_SIDEBAND9_t sideband9;
8349 ALT_IO48_HMC_MMR_SIDEBAND10_t sideband10;
8350 ALT_IO48_HMC_MMR_SIDEBAND11_t sideband11;
8351 ALT_IO48_HMC_MMR_SIDEBAND12_t sideband12;
8352 ALT_IO48_HMC_MMR_SIDEBAND13_t sideband13;
8353 ALT_IO48_HMC_MMR_SIDEBAND14_t sideband14;
8354 ALT_IO48_HMC_MMR_SIDEBAND15_t sideband15;
8355 ALT_IO48_HMC_MMR_DRAMSTS_t dramsts;
8356 ALT_IO48_HMC_MMR_DBGDONE_t dbgdone;
8357 ALT_IO48_HMC_MMR_DBGSIGNALS_t dbgsignals;
8358 ALT_IO48_HMC_MMR_DBGRST_t dbgreset;
8359 ALT_IO48_HMC_MMR_DBGMATCH_t dbgmatch;
8360 ALT_IO48_HMC_MMR_CNTR0MSK_t counter0mask;
8361 ALT_IO48_HMC_MMR_CNTR1MSK_t counter1mask;
8362 ALT_IO48_HMC_MMR_CNTR0MATCH_t counter0match;
8363 ALT_IO48_HMC_MMR_CNTR1MATCH_t counter1match;
8364 ALT_IO48_HMC_MMR_NIOSRESERVE0_t niosreserve0;
8365 ALT_IO48_HMC_MMR_NIOSRESERVE1_t niosreserve1;
8366 ALT_IO48_HMC_MMR_NIOSRESERVE2_t niosreserve2;
8367 volatile uint32_t _pad_0x11c_0x1000[953];
8371 typedef volatile struct ALT_IO48_HMC_MMR_s ALT_IO48_HMC_MMR_t;
8373 struct ALT_IO48_HMC_MMR_raw_s
8375 volatile uint32_t dbgcfg0;
8376 volatile uint32_t dbgcfg1;
8377 volatile uint32_t dbgcfg2;
8378 volatile uint32_t dbgcfg3;
8379 volatile uint32_t dbgcfg4;
8380 volatile uint32_t dbgcfg5;
8381 volatile uint32_t dbgcfg6;
8382 volatile uint32_t reserve0;
8383 volatile uint32_t reserve1;
8384 volatile uint32_t reserve2;
8385 volatile uint32_t ctrlcfg0;
8386 volatile uint32_t ctrlcfg1;
8387 volatile uint32_t ctrlcfg2;
8388 volatile uint32_t ctrlcfg3;
8389 volatile uint32_t ctrlcfg4;
8390 volatile uint32_t ctrlcfg5;
8391 volatile uint32_t ctrlcfg6;
8392 volatile uint32_t ctrlcfg7;
8393 volatile uint32_t ctrlcfg8;
8394 volatile uint32_t ctrlcfg9;
8395 volatile uint32_t dramtiming0;
8396 volatile uint32_t dramodt0;
8397 volatile uint32_t dramodt1;
8398 volatile uint32_t sbcfg0;
8399 volatile uint32_t sbcfg1;
8400 volatile uint32_t sbcfg2;
8401 volatile uint32_t sbcfg3;
8402 volatile uint32_t sbcfg4;
8403 volatile uint32_t sbcfg5;
8404 volatile uint32_t sbcfg6;
8405 volatile uint32_t sbcfg7;
8406 volatile uint32_t caltiming0;
8407 volatile uint32_t caltiming1;
8408 volatile uint32_t caltiming2;
8409 volatile uint32_t caltiming3;
8410 volatile uint32_t caltiming4;
8411 volatile uint32_t caltiming5;
8412 volatile uint32_t caltiming6;
8413 volatile uint32_t caltiming7;
8414 volatile uint32_t caltiming8;
8415 volatile uint32_t caltiming9;
8416 volatile uint32_t caltiming10;
8417 volatile uint32_t dramaddrw;
8418 volatile uint32_t sideband0;
8419 volatile uint32_t sideband1;
8420 volatile uint32_t sideband2;
8421 volatile uint32_t sideband3;
8422 volatile uint32_t sideband4;
8423 volatile uint32_t sideband5;
8424 volatile uint32_t sideband6;
8425 volatile uint32_t sideband7;
8426 volatile uint32_t sideband8;
8427 volatile uint32_t sideband9;
8428 volatile uint32_t sideband10;
8429 volatile uint32_t sideband11;
8430 volatile uint32_t sideband12;
8431 volatile uint32_t sideband13;
8432 volatile uint32_t sideband14;
8433 volatile uint32_t sideband15;
8434 volatile uint32_t dramsts;
8435 volatile uint32_t dbgdone;
8436 volatile uint32_t dbgsignals;
8437 volatile uint32_t dbgreset;
8438 volatile uint32_t dbgmatch;
8439 volatile uint32_t counter0mask;
8440 volatile uint32_t counter1mask;
8441 volatile uint32_t counter0match;
8442 volatile uint32_t counter1match;
8443 volatile uint32_t niosreserve0;
8444 volatile uint32_t niosreserve1;
8445 volatile uint32_t niosreserve2;
8446 uint32_t _pad_0x11c_0x1000[953];
8450 typedef volatile struct ALT_IO48_HMC_MMR_raw_s ALT_IO48_HMC_MMR_raw_t;