Altera SoCAL  20.1
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alt_nand.h
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32 
33 /* Altera - ALT_NAND */
34 
35 #ifndef __ALTERA_ALT_NAND_H__
36 #define __ALTERA_ALT_NAND_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
43 /*
44  * Component : NAND Flash Controller Module Registers (AXI Slave) - ALT_NAND
45  * NAND Flash Controller Module Registers (AXI Slave)
46  *
47  * Registers in the NAND Flash Controller module accessible via its register AXI
48  * slave
49  *
50  */
51 /*
52  * Register Group : Configuration registers - ALT_NAND_CFG
53  * Configuration registers
54  *
55  * Common across all types of flash devices, configuration registers setup the
56  * basic operating modes of the controller
57  *
58  */
59 /*
60  * Register : device_reset
61  *
62  * Device reset. Controller sends a RESET command to device. Controller resets bit
63  * after sending command to device
64  *
65  * Register Layout
66  *
67  * Bits | Access | Reset | Description
68  * :-------|:-------|:------|:------------------------------
69  * [0] | RW | 0x0 | ALT_NAND_CFG_DEVICE_RST_BANK0
70  * [1] | RW | 0x0 | ALT_NAND_CFG_DEVICE_RST_BANK1
71  * [2] | RW | 0x0 | ALT_NAND_CFG_DEVICE_RST_BANK2
72  * [3] | RW | 0x0 | ALT_NAND_CFG_DEVICE_RST_BANK3
73  * [31:4] | ??? | 0x0 | *UNDEFINED*
74  *
75  */
76 /*
77  * Field : bank0
78  *
79  * Issues reset to bank 0. Controller resets the bit after reset command is issued
80  * to device.
81  *
82  * Field Access Macros:
83  *
84  */
85 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK0 register field. */
86 #define ALT_NAND_CFG_DEVICE_RST_BANK0_LSB 0
87 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK0 register field. */
88 #define ALT_NAND_CFG_DEVICE_RST_BANK0_MSB 0
89 /* The width in bits of the ALT_NAND_CFG_DEVICE_RST_BANK0 register field. */
90 #define ALT_NAND_CFG_DEVICE_RST_BANK0_WIDTH 1
91 /* The mask used to set the ALT_NAND_CFG_DEVICE_RST_BANK0 register field value. */
92 #define ALT_NAND_CFG_DEVICE_RST_BANK0_SET_MSK 0x00000001
93 /* The mask used to clear the ALT_NAND_CFG_DEVICE_RST_BANK0 register field value. */
94 #define ALT_NAND_CFG_DEVICE_RST_BANK0_CLR_MSK 0xfffffffe
95 /* The reset value of the ALT_NAND_CFG_DEVICE_RST_BANK0 register field. */
96 #define ALT_NAND_CFG_DEVICE_RST_BANK0_RESET 0x0
97 /* Extracts the ALT_NAND_CFG_DEVICE_RST_BANK0 field value from a register. */
98 #define ALT_NAND_CFG_DEVICE_RST_BANK0_GET(value) (((value) & 0x00000001) >> 0)
99 /* Produces a ALT_NAND_CFG_DEVICE_RST_BANK0 register field value suitable for setting the register. */
100 #define ALT_NAND_CFG_DEVICE_RST_BANK0_SET(value) (((value) << 0) & 0x00000001)
101 
102 /*
103  * Field : bank1
104  *
105  * Issues reset to bank 1. Controller resets the bit after reset command is issued
106  * to device.
107  *
108  * Field Access Macros:
109  *
110  */
111 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK1 register field. */
112 #define ALT_NAND_CFG_DEVICE_RST_BANK1_LSB 1
113 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK1 register field. */
114 #define ALT_NAND_CFG_DEVICE_RST_BANK1_MSB 1
115 /* The width in bits of the ALT_NAND_CFG_DEVICE_RST_BANK1 register field. */
116 #define ALT_NAND_CFG_DEVICE_RST_BANK1_WIDTH 1
117 /* The mask used to set the ALT_NAND_CFG_DEVICE_RST_BANK1 register field value. */
118 #define ALT_NAND_CFG_DEVICE_RST_BANK1_SET_MSK 0x00000002
119 /* The mask used to clear the ALT_NAND_CFG_DEVICE_RST_BANK1 register field value. */
120 #define ALT_NAND_CFG_DEVICE_RST_BANK1_CLR_MSK 0xfffffffd
121 /* The reset value of the ALT_NAND_CFG_DEVICE_RST_BANK1 register field. */
122 #define ALT_NAND_CFG_DEVICE_RST_BANK1_RESET 0x0
123 /* Extracts the ALT_NAND_CFG_DEVICE_RST_BANK1 field value from a register. */
124 #define ALT_NAND_CFG_DEVICE_RST_BANK1_GET(value) (((value) & 0x00000002) >> 1)
125 /* Produces a ALT_NAND_CFG_DEVICE_RST_BANK1 register field value suitable for setting the register. */
126 #define ALT_NAND_CFG_DEVICE_RST_BANK1_SET(value) (((value) << 1) & 0x00000002)
127 
128 /*
129  * Field : bank2
130  *
131  * Issues reset to bank 2. Controller resets the bit after reset command is issued
132  * to device.
133  *
134  * Field Access Macros:
135  *
136  */
137 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK2 register field. */
138 #define ALT_NAND_CFG_DEVICE_RST_BANK2_LSB 2
139 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK2 register field. */
140 #define ALT_NAND_CFG_DEVICE_RST_BANK2_MSB 2
141 /* The width in bits of the ALT_NAND_CFG_DEVICE_RST_BANK2 register field. */
142 #define ALT_NAND_CFG_DEVICE_RST_BANK2_WIDTH 1
143 /* The mask used to set the ALT_NAND_CFG_DEVICE_RST_BANK2 register field value. */
144 #define ALT_NAND_CFG_DEVICE_RST_BANK2_SET_MSK 0x00000004
145 /* The mask used to clear the ALT_NAND_CFG_DEVICE_RST_BANK2 register field value. */
146 #define ALT_NAND_CFG_DEVICE_RST_BANK2_CLR_MSK 0xfffffffb
147 /* The reset value of the ALT_NAND_CFG_DEVICE_RST_BANK2 register field. */
148 #define ALT_NAND_CFG_DEVICE_RST_BANK2_RESET 0x0
149 /* Extracts the ALT_NAND_CFG_DEVICE_RST_BANK2 field value from a register. */
150 #define ALT_NAND_CFG_DEVICE_RST_BANK2_GET(value) (((value) & 0x00000004) >> 2)
151 /* Produces a ALT_NAND_CFG_DEVICE_RST_BANK2 register field value suitable for setting the register. */
152 #define ALT_NAND_CFG_DEVICE_RST_BANK2_SET(value) (((value) << 2) & 0x00000004)
153 
154 /*
155  * Field : bank3
156  *
157  * Issues reset to bank 3. Controller resets the bit after reset command is issued
158  * to device.
159  *
160  * Field Access Macros:
161  *
162  */
163 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK3 register field. */
164 #define ALT_NAND_CFG_DEVICE_RST_BANK3_LSB 3
165 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK3 register field. */
166 #define ALT_NAND_CFG_DEVICE_RST_BANK3_MSB 3
167 /* The width in bits of the ALT_NAND_CFG_DEVICE_RST_BANK3 register field. */
168 #define ALT_NAND_CFG_DEVICE_RST_BANK3_WIDTH 1
169 /* The mask used to set the ALT_NAND_CFG_DEVICE_RST_BANK3 register field value. */
170 #define ALT_NAND_CFG_DEVICE_RST_BANK3_SET_MSK 0x00000008
171 /* The mask used to clear the ALT_NAND_CFG_DEVICE_RST_BANK3 register field value. */
172 #define ALT_NAND_CFG_DEVICE_RST_BANK3_CLR_MSK 0xfffffff7
173 /* The reset value of the ALT_NAND_CFG_DEVICE_RST_BANK3 register field. */
174 #define ALT_NAND_CFG_DEVICE_RST_BANK3_RESET 0x0
175 /* Extracts the ALT_NAND_CFG_DEVICE_RST_BANK3 field value from a register. */
176 #define ALT_NAND_CFG_DEVICE_RST_BANK3_GET(value) (((value) & 0x00000008) >> 3)
177 /* Produces a ALT_NAND_CFG_DEVICE_RST_BANK3 register field value suitable for setting the register. */
178 #define ALT_NAND_CFG_DEVICE_RST_BANK3_SET(value) (((value) << 3) & 0x00000008)
179 
180 #ifndef __ASSEMBLY__
181 /*
182  * WARNING: The C register and register group struct declarations are provided for
183  * convenience and illustrative purposes. They should, however, be used with
184  * caution as the C language standard provides no guarantees about the alignment or
185  * atomicity of device memory accesses. The recommended practice for writing
186  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
187  * alt_write_word() functions.
188  *
189  * The struct declaration for register ALT_NAND_CFG_DEVICE_RST.
190  */
191 struct ALT_NAND_CFG_DEVICE_RST_s
192 {
193  uint32_t bank0 : 1; /* ALT_NAND_CFG_DEVICE_RST_BANK0 */
194  uint32_t bank1 : 1; /* ALT_NAND_CFG_DEVICE_RST_BANK1 */
195  uint32_t bank2 : 1; /* ALT_NAND_CFG_DEVICE_RST_BANK2 */
196  uint32_t bank3 : 1; /* ALT_NAND_CFG_DEVICE_RST_BANK3 */
197  uint32_t : 28; /* *UNDEFINED* */
198 };
199 
200 /* The typedef declaration for register ALT_NAND_CFG_DEVICE_RST. */
201 typedef volatile struct ALT_NAND_CFG_DEVICE_RST_s ALT_NAND_CFG_DEVICE_RST_t;
202 #endif /* __ASSEMBLY__ */
203 
204 /* The byte offset of the ALT_NAND_CFG_DEVICE_RST register from the beginning of the component. */
205 #define ALT_NAND_CFG_DEVICE_RST_OFST 0x0
206 
207 /*
208  * Register : transfer_spare_reg
209  *
210  * Default data transfer mode. (Ignored during Spare only mode)
211  *
212  * Register Layout
213  *
214  * Bits | Access | Reset | Description
215  * :-------|:-------|:------|:--------------------------------
216  * [0] | RW | 0x0 | ALT_NAND_CFG_TFR_SPARE_REG_FLAG
217  * [31:1] | ??? | 0x0 | *UNDEFINED*
218  *
219  */
220 /*
221  * Field : flag
222  *
223  * On all read or write commands through Map 01, if this bit is set, data in spare
224  * area of memory will be transfered to host along with main area of data. The main
225  * area will be transfered followed by spare area.[list][*]1 - MAIN+SPARE [*]0 -
226  * MAIN[/list]
227  *
228  * Field Access Macros:
229  *
230  */
231 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TFR_SPARE_REG_FLAG register field. */
232 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_LSB 0
233 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TFR_SPARE_REG_FLAG register field. */
234 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_MSB 0
235 /* The width in bits of the ALT_NAND_CFG_TFR_SPARE_REG_FLAG register field. */
236 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_WIDTH 1
237 /* The mask used to set the ALT_NAND_CFG_TFR_SPARE_REG_FLAG register field value. */
238 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_SET_MSK 0x00000001
239 /* The mask used to clear the ALT_NAND_CFG_TFR_SPARE_REG_FLAG register field value. */
240 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_CLR_MSK 0xfffffffe
241 /* The reset value of the ALT_NAND_CFG_TFR_SPARE_REG_FLAG register field. */
242 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_RESET 0x0
243 /* Extracts the ALT_NAND_CFG_TFR_SPARE_REG_FLAG field value from a register. */
244 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_GET(value) (((value) & 0x00000001) >> 0)
245 /* Produces a ALT_NAND_CFG_TFR_SPARE_REG_FLAG register field value suitable for setting the register. */
246 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_SET(value) (((value) << 0) & 0x00000001)
247 
248 #ifndef __ASSEMBLY__
249 /*
250  * WARNING: The C register and register group struct declarations are provided for
251  * convenience and illustrative purposes. They should, however, be used with
252  * caution as the C language standard provides no guarantees about the alignment or
253  * atomicity of device memory accesses. The recommended practice for writing
254  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
255  * alt_write_word() functions.
256  *
257  * The struct declaration for register ALT_NAND_CFG_TFR_SPARE_REG.
258  */
259 struct ALT_NAND_CFG_TFR_SPARE_REG_s
260 {
261  uint32_t flag : 1; /* ALT_NAND_CFG_TFR_SPARE_REG_FLAG */
262  uint32_t : 31; /* *UNDEFINED* */
263 };
264 
265 /* The typedef declaration for register ALT_NAND_CFG_TFR_SPARE_REG. */
266 typedef volatile struct ALT_NAND_CFG_TFR_SPARE_REG_s ALT_NAND_CFG_TFR_SPARE_REG_t;
267 #endif /* __ASSEMBLY__ */
268 
269 /* The byte offset of the ALT_NAND_CFG_TFR_SPARE_REG register from the beginning of the component. */
270 #define ALT_NAND_CFG_TFR_SPARE_REG_OFST 0x10
271 
272 /*
273  * Register : load_wait_cnt
274  *
275  * Wait count value for Load operation
276  *
277  * Register Layout
278  *
279  * Bits | Access | Reset | Description
280  * :--------|:-------|:------|:-------------------------------
281  * [15:0] | RW | 0x1f4 | ALT_NAND_CFG_LD_WAIT_CNT_VALUE
282  * [31:16] | ??? | 0x0 | *UNDEFINED*
283  *
284  */
285 /*
286  * Field : value
287  *
288  * Number of clock cycles after issue of load operation before NAND Flash
289  * Controller polls for status. This values is of relevance for status polling mode
290  * of operation and has been provided to minimize redundant polling after issuing a
291  * command. After a load command, the first polling will happen after this many
292  * number of cycles have elapsed and then on polling will happen every
293  * int_mon_cyccnt cycles. The default values is equal to the default value of
294  * int_mon_cyccnt
295  *
296  * Field Access Macros:
297  *
298  */
299 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_LD_WAIT_CNT_VALUE register field. */
300 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_LSB 0
301 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_LD_WAIT_CNT_VALUE register field. */
302 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_MSB 15
303 /* The width in bits of the ALT_NAND_CFG_LD_WAIT_CNT_VALUE register field. */
304 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_WIDTH 16
305 /* The mask used to set the ALT_NAND_CFG_LD_WAIT_CNT_VALUE register field value. */
306 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
307 /* The mask used to clear the ALT_NAND_CFG_LD_WAIT_CNT_VALUE register field value. */
308 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
309 /* The reset value of the ALT_NAND_CFG_LD_WAIT_CNT_VALUE register field. */
310 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_RESET 0x1f4
311 /* Extracts the ALT_NAND_CFG_LD_WAIT_CNT_VALUE field value from a register. */
312 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
313 /* Produces a ALT_NAND_CFG_LD_WAIT_CNT_VALUE register field value suitable for setting the register. */
314 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
315 
316 #ifndef __ASSEMBLY__
317 /*
318  * WARNING: The C register and register group struct declarations are provided for
319  * convenience and illustrative purposes. They should, however, be used with
320  * caution as the C language standard provides no guarantees about the alignment or
321  * atomicity of device memory accesses. The recommended practice for writing
322  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
323  * alt_write_word() functions.
324  *
325  * The struct declaration for register ALT_NAND_CFG_LD_WAIT_CNT.
326  */
327 struct ALT_NAND_CFG_LD_WAIT_CNT_s
328 {
329  uint32_t value : 16; /* ALT_NAND_CFG_LD_WAIT_CNT_VALUE */
330  uint32_t : 16; /* *UNDEFINED* */
331 };
332 
333 /* The typedef declaration for register ALT_NAND_CFG_LD_WAIT_CNT. */
334 typedef volatile struct ALT_NAND_CFG_LD_WAIT_CNT_s ALT_NAND_CFG_LD_WAIT_CNT_t;
335 #endif /* __ASSEMBLY__ */
336 
337 /* The byte offset of the ALT_NAND_CFG_LD_WAIT_CNT register from the beginning of the component. */
338 #define ALT_NAND_CFG_LD_WAIT_CNT_OFST 0x20
339 
340 /*
341  * Register : program_wait_cnt
342  *
343  * Wait count value for Program operation
344  *
345  * Register Layout
346  *
347  * Bits | Access | Reset | Description
348  * :--------|:-------|:------|:------------------------------------
349  * [15:0] | RW | 0x1f4 | ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE
350  * [31:16] | ??? | 0x0 | *UNDEFINED*
351  *
352  */
353 /*
354  * Field : value
355  *
356  * Number of clock cycles after issue of program operation before NAND Flash
357  * Controller polls for status. This values is of relevance for status polling mode
358  * of operation and has been provided to minimize redundant polling after issuing a
359  * command. After a program command, the first polling will happen after this many
360  * number of cycles have elapsed and then on polling will happen every
361  * int_mon_cyccnt cycles. The default values is equal to the default value of
362  * int_mon_cyccnt. The controller internally multiplies the value programmed into
363  * this register by 16 to provide a wider range for polling.
364  *
365  * Field Access Macros:
366  *
367  */
368 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field. */
369 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_LSB 0
370 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field. */
371 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_MSB 15
372 /* The width in bits of the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field. */
373 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_WIDTH 16
374 /* The mask used to set the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field value. */
375 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
376 /* The mask used to clear the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field value. */
377 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
378 /* The reset value of the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field. */
379 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_RESET 0x1f4
380 /* Extracts the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE field value from a register. */
381 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
382 /* Produces a ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field value suitable for setting the register. */
383 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
384 
385 #ifndef __ASSEMBLY__
386 /*
387  * WARNING: The C register and register group struct declarations are provided for
388  * convenience and illustrative purposes. They should, however, be used with
389  * caution as the C language standard provides no guarantees about the alignment or
390  * atomicity of device memory accesses. The recommended practice for writing
391  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
392  * alt_write_word() functions.
393  *
394  * The struct declaration for register ALT_NAND_CFG_PROGRAM_WAIT_CNT.
395  */
396 struct ALT_NAND_CFG_PROGRAM_WAIT_CNT_s
397 {
398  uint32_t value : 16; /* ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE */
399  uint32_t : 16; /* *UNDEFINED* */
400 };
401 
402 /* The typedef declaration for register ALT_NAND_CFG_PROGRAM_WAIT_CNT. */
403 typedef volatile struct ALT_NAND_CFG_PROGRAM_WAIT_CNT_s ALT_NAND_CFG_PROGRAM_WAIT_CNT_t;
404 #endif /* __ASSEMBLY__ */
405 
406 /* The byte offset of the ALT_NAND_CFG_PROGRAM_WAIT_CNT register from the beginning of the component. */
407 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_OFST 0x30
408 
409 /*
410  * Register : erase_wait_cnt
411  *
412  * Wait count value for Erase operation
413  *
414  * Register Layout
415  *
416  * Bits | Access | Reset | Description
417  * :--------|:-------|:------|:----------------------------------
418  * [15:0] | RW | 0x1f4 | ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE
419  * [31:16] | ??? | 0x0 | *UNDEFINED*
420  *
421  */
422 /*
423  * Field : value
424  *
425  * Number of clock cycles after issue of erase operation before NAND Flash
426  * Controller polls for status. This values is of relevance for status polling mode
427  * of operation and has been provided to minimize redundant polling after issuing a
428  * command. After a erase command, the first polling will happen after this many
429  * number of cycles have elapsed and then on polling will happen every
430  * int_mon_cyccnt cycles. The default values is equal to the default value of
431  * int_mon_cyccnt. The controller internally multiplies the value programmed into
432  * this register by 16 to provide a wider range for polling.
433  *
434  * Field Access Macros:
435  *
436  */
437 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field. */
438 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_LSB 0
439 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field. */
440 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_MSB 15
441 /* The width in bits of the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field. */
442 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_WIDTH 16
443 /* The mask used to set the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field value. */
444 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
445 /* The mask used to clear the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field value. */
446 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
447 /* The reset value of the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field. */
448 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_RESET 0x1f4
449 /* Extracts the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE field value from a register. */
450 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
451 /* Produces a ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field value suitable for setting the register. */
452 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
453 
454 #ifndef __ASSEMBLY__
455 /*
456  * WARNING: The C register and register group struct declarations are provided for
457  * convenience and illustrative purposes. They should, however, be used with
458  * caution as the C language standard provides no guarantees about the alignment or
459  * atomicity of device memory accesses. The recommended practice for writing
460  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
461  * alt_write_word() functions.
462  *
463  * The struct declaration for register ALT_NAND_CFG_ERASE_WAIT_CNT.
464  */
465 struct ALT_NAND_CFG_ERASE_WAIT_CNT_s
466 {
467  uint32_t value : 16; /* ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE */
468  uint32_t : 16; /* *UNDEFINED* */
469 };
470 
471 /* The typedef declaration for register ALT_NAND_CFG_ERASE_WAIT_CNT. */
472 typedef volatile struct ALT_NAND_CFG_ERASE_WAIT_CNT_s ALT_NAND_CFG_ERASE_WAIT_CNT_t;
473 #endif /* __ASSEMBLY__ */
474 
475 /* The byte offset of the ALT_NAND_CFG_ERASE_WAIT_CNT register from the beginning of the component. */
476 #define ALT_NAND_CFG_ERASE_WAIT_CNT_OFST 0x40
477 
478 /*
479  * Register : int_mon_cyccnt
480  *
481  * Interrupt monitor cycle count value
482  *
483  * Register Layout
484  *
485  * Bits | Access | Reset | Description
486  * :--------|:-------|:------|:----------------------------------
487  * [15:0] | RW | 0x1f4 | ALT_NAND_CFG_INT_MON_CYCCNT_VALUE
488  * [31:16] | ??? | 0x0 | *UNDEFINED*
489  *
490  */
491 /*
492  * Field : value
493  *
494  * In polling mode, sets the number of cycles Denali Flash Controller must wait
495  * before checking the status register. This register is only used when R/B pins
496  * are not available to NAND Flash Controller.
497  *
498  * Field Access Macros:
499  *
500  */
501 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field. */
502 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_LSB 0
503 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field. */
504 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_MSB 15
505 /* The width in bits of the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field. */
506 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_WIDTH 16
507 /* The mask used to set the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field value. */
508 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_SET_MSK 0x0000ffff
509 /* The mask used to clear the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field value. */
510 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_CLR_MSK 0xffff0000
511 /* The reset value of the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field. */
512 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_RESET 0x1f4
513 /* Extracts the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE field value from a register. */
514 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
515 /* Produces a ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field value suitable for setting the register. */
516 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
517 
518 #ifndef __ASSEMBLY__
519 /*
520  * WARNING: The C register and register group struct declarations are provided for
521  * convenience and illustrative purposes. They should, however, be used with
522  * caution as the C language standard provides no guarantees about the alignment or
523  * atomicity of device memory accesses. The recommended practice for writing
524  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
525  * alt_write_word() functions.
526  *
527  * The struct declaration for register ALT_NAND_CFG_INT_MON_CYCCNT.
528  */
529 struct ALT_NAND_CFG_INT_MON_CYCCNT_s
530 {
531  uint32_t value : 16; /* ALT_NAND_CFG_INT_MON_CYCCNT_VALUE */
532  uint32_t : 16; /* *UNDEFINED* */
533 };
534 
535 /* The typedef declaration for register ALT_NAND_CFG_INT_MON_CYCCNT. */
536 typedef volatile struct ALT_NAND_CFG_INT_MON_CYCCNT_s ALT_NAND_CFG_INT_MON_CYCCNT_t;
537 #endif /* __ASSEMBLY__ */
538 
539 /* The byte offset of the ALT_NAND_CFG_INT_MON_CYCCNT register from the beginning of the component. */
540 #define ALT_NAND_CFG_INT_MON_CYCCNT_OFST 0x50
541 
542 /*
543  * Register : rb_pin_enabled
544  *
545  * Interrupt or polling mode. Ready/Busy pin is enabled from device.
546  *
547  * Register Layout
548  *
549  * Bits | Access | Reset | Description
550  * :-------|:-------|:------|:------------------------------
551  * [0] | RW | 0x1 | ALT_NAND_CFG_RB_PIN_END_BANK0
552  * [1] | RW | 0x0 | ALT_NAND_CFG_RB_PIN_END_BANK1
553  * [2] | RW | 0x0 | ALT_NAND_CFG_RB_PIN_END_BANK2
554  * [3] | RW | 0x0 | ALT_NAND_CFG_RB_PIN_END_BANK3
555  * [31:4] | ??? | 0x0 | *UNDEFINED*
556  *
557  */
558 /*
559  * Field : bank0
560  *
561  * Sets Denali Flash Controller in interrupt pin or polling mode [list][*]1 - R/B
562  * pin enabled for bank 0. Interrupt pin mode. [*]0 - R/B pin disabled for bank 0.
563  * Polling mode.[/list]
564  *
565  * Field Access Macros:
566  *
567  */
568 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK0 register field. */
569 #define ALT_NAND_CFG_RB_PIN_END_BANK0_LSB 0
570 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK0 register field. */
571 #define ALT_NAND_CFG_RB_PIN_END_BANK0_MSB 0
572 /* The width in bits of the ALT_NAND_CFG_RB_PIN_END_BANK0 register field. */
573 #define ALT_NAND_CFG_RB_PIN_END_BANK0_WIDTH 1
574 /* The mask used to set the ALT_NAND_CFG_RB_PIN_END_BANK0 register field value. */
575 #define ALT_NAND_CFG_RB_PIN_END_BANK0_SET_MSK 0x00000001
576 /* The mask used to clear the ALT_NAND_CFG_RB_PIN_END_BANK0 register field value. */
577 #define ALT_NAND_CFG_RB_PIN_END_BANK0_CLR_MSK 0xfffffffe
578 /* The reset value of the ALT_NAND_CFG_RB_PIN_END_BANK0 register field. */
579 #define ALT_NAND_CFG_RB_PIN_END_BANK0_RESET 0x1
580 /* Extracts the ALT_NAND_CFG_RB_PIN_END_BANK0 field value from a register. */
581 #define ALT_NAND_CFG_RB_PIN_END_BANK0_GET(value) (((value) & 0x00000001) >> 0)
582 /* Produces a ALT_NAND_CFG_RB_PIN_END_BANK0 register field value suitable for setting the register. */
583 #define ALT_NAND_CFG_RB_PIN_END_BANK0_SET(value) (((value) << 0) & 0x00000001)
584 
585 /*
586  * Field : bank1
587  *
588  * Sets Denali Flash Controller in interrupt pin or polling mode [list][*]1 - R/B
589  * pin enabled for bank 1. Interrupt pin mode. [*]0 - R/B pin disabled for bank 1.
590  * Polling mode.[/list]
591  *
592  * Field Access Macros:
593  *
594  */
595 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK1 register field. */
596 #define ALT_NAND_CFG_RB_PIN_END_BANK1_LSB 1
597 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK1 register field. */
598 #define ALT_NAND_CFG_RB_PIN_END_BANK1_MSB 1
599 /* The width in bits of the ALT_NAND_CFG_RB_PIN_END_BANK1 register field. */
600 #define ALT_NAND_CFG_RB_PIN_END_BANK1_WIDTH 1
601 /* The mask used to set the ALT_NAND_CFG_RB_PIN_END_BANK1 register field value. */
602 #define ALT_NAND_CFG_RB_PIN_END_BANK1_SET_MSK 0x00000002
603 /* The mask used to clear the ALT_NAND_CFG_RB_PIN_END_BANK1 register field value. */
604 #define ALT_NAND_CFG_RB_PIN_END_BANK1_CLR_MSK 0xfffffffd
605 /* The reset value of the ALT_NAND_CFG_RB_PIN_END_BANK1 register field. */
606 #define ALT_NAND_CFG_RB_PIN_END_BANK1_RESET 0x0
607 /* Extracts the ALT_NAND_CFG_RB_PIN_END_BANK1 field value from a register. */
608 #define ALT_NAND_CFG_RB_PIN_END_BANK1_GET(value) (((value) & 0x00000002) >> 1)
609 /* Produces a ALT_NAND_CFG_RB_PIN_END_BANK1 register field value suitable for setting the register. */
610 #define ALT_NAND_CFG_RB_PIN_END_BANK1_SET(value) (((value) << 1) & 0x00000002)
611 
612 /*
613  * Field : bank2
614  *
615  * Sets Denali Flash Controller in interrupt pin or polling mode [list][*]1 - R/B
616  * pin enabled for bank 2. Interrupt pin mode. [*]0 - R/B pin disabled for bank 2.
617  * Polling mode.[/list]
618  *
619  * Field Access Macros:
620  *
621  */
622 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK2 register field. */
623 #define ALT_NAND_CFG_RB_PIN_END_BANK2_LSB 2
624 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK2 register field. */
625 #define ALT_NAND_CFG_RB_PIN_END_BANK2_MSB 2
626 /* The width in bits of the ALT_NAND_CFG_RB_PIN_END_BANK2 register field. */
627 #define ALT_NAND_CFG_RB_PIN_END_BANK2_WIDTH 1
628 /* The mask used to set the ALT_NAND_CFG_RB_PIN_END_BANK2 register field value. */
629 #define ALT_NAND_CFG_RB_PIN_END_BANK2_SET_MSK 0x00000004
630 /* The mask used to clear the ALT_NAND_CFG_RB_PIN_END_BANK2 register field value. */
631 #define ALT_NAND_CFG_RB_PIN_END_BANK2_CLR_MSK 0xfffffffb
632 /* The reset value of the ALT_NAND_CFG_RB_PIN_END_BANK2 register field. */
633 #define ALT_NAND_CFG_RB_PIN_END_BANK2_RESET 0x0
634 /* Extracts the ALT_NAND_CFG_RB_PIN_END_BANK2 field value from a register. */
635 #define ALT_NAND_CFG_RB_PIN_END_BANK2_GET(value) (((value) & 0x00000004) >> 2)
636 /* Produces a ALT_NAND_CFG_RB_PIN_END_BANK2 register field value suitable for setting the register. */
637 #define ALT_NAND_CFG_RB_PIN_END_BANK2_SET(value) (((value) << 2) & 0x00000004)
638 
639 /*
640  * Field : bank3
641  *
642  * Sets Denali Flash Controller in interrupt pin or polling mode [list][*]1 - R/B
643  * pin enabled for bank 3. Interrupt pin mode. [*]0 - R/B pin disabled for bank 3.
644  * Polling mode.[/list]
645  *
646  * Field Access Macros:
647  *
648  */
649 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK3 register field. */
650 #define ALT_NAND_CFG_RB_PIN_END_BANK3_LSB 3
651 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK3 register field. */
652 #define ALT_NAND_CFG_RB_PIN_END_BANK3_MSB 3
653 /* The width in bits of the ALT_NAND_CFG_RB_PIN_END_BANK3 register field. */
654 #define ALT_NAND_CFG_RB_PIN_END_BANK3_WIDTH 1
655 /* The mask used to set the ALT_NAND_CFG_RB_PIN_END_BANK3 register field value. */
656 #define ALT_NAND_CFG_RB_PIN_END_BANK3_SET_MSK 0x00000008
657 /* The mask used to clear the ALT_NAND_CFG_RB_PIN_END_BANK3 register field value. */
658 #define ALT_NAND_CFG_RB_PIN_END_BANK3_CLR_MSK 0xfffffff7
659 /* The reset value of the ALT_NAND_CFG_RB_PIN_END_BANK3 register field. */
660 #define ALT_NAND_CFG_RB_PIN_END_BANK3_RESET 0x0
661 /* Extracts the ALT_NAND_CFG_RB_PIN_END_BANK3 field value from a register. */
662 #define ALT_NAND_CFG_RB_PIN_END_BANK3_GET(value) (((value) & 0x00000008) >> 3)
663 /* Produces a ALT_NAND_CFG_RB_PIN_END_BANK3 register field value suitable for setting the register. */
664 #define ALT_NAND_CFG_RB_PIN_END_BANK3_SET(value) (((value) << 3) & 0x00000008)
665 
666 #ifndef __ASSEMBLY__
667 /*
668  * WARNING: The C register and register group struct declarations are provided for
669  * convenience and illustrative purposes. They should, however, be used with
670  * caution as the C language standard provides no guarantees about the alignment or
671  * atomicity of device memory accesses. The recommended practice for writing
672  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
673  * alt_write_word() functions.
674  *
675  * The struct declaration for register ALT_NAND_CFG_RB_PIN_END.
676  */
677 struct ALT_NAND_CFG_RB_PIN_END_s
678 {
679  uint32_t bank0 : 1; /* ALT_NAND_CFG_RB_PIN_END_BANK0 */
680  uint32_t bank1 : 1; /* ALT_NAND_CFG_RB_PIN_END_BANK1 */
681  uint32_t bank2 : 1; /* ALT_NAND_CFG_RB_PIN_END_BANK2 */
682  uint32_t bank3 : 1; /* ALT_NAND_CFG_RB_PIN_END_BANK3 */
683  uint32_t : 28; /* *UNDEFINED* */
684 };
685 
686 /* The typedef declaration for register ALT_NAND_CFG_RB_PIN_END. */
687 typedef volatile struct ALT_NAND_CFG_RB_PIN_END_s ALT_NAND_CFG_RB_PIN_END_t;
688 #endif /* __ASSEMBLY__ */
689 
690 /* The byte offset of the ALT_NAND_CFG_RB_PIN_END register from the beginning of the component. */
691 #define ALT_NAND_CFG_RB_PIN_END_OFST 0x60
692 
693 /*
694  * Register : multiplane_operation
695  *
696  * Multiplane transfer mode. Pipelined read, copyback, erase and program commands
697  * are transfered in multiplane mode
698  *
699  * Register Layout
700  *
701  * Bits | Access | Reset | Description
702  * :-------|:-------|:------|:--------------------------------
703  * [0] | RW | 0x0 | ALT_NAND_CFG_MULTIPLANE_OP_FLAG
704  * [31:1] | ??? | 0x0 | *UNDEFINED*
705  *
706  */
707 /*
708  * Field : flag
709  *
710  * [list][*]1 - Multiplane operation enabled [*]0 - Multiplane operation
711  * disabled[/list]
712  *
713  * Field Access Macros:
714  *
715  */
716 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_MULTIPLANE_OP_FLAG register field. */
717 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_LSB 0
718 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_MULTIPLANE_OP_FLAG register field. */
719 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_MSB 0
720 /* The width in bits of the ALT_NAND_CFG_MULTIPLANE_OP_FLAG register field. */
721 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_WIDTH 1
722 /* The mask used to set the ALT_NAND_CFG_MULTIPLANE_OP_FLAG register field value. */
723 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_SET_MSK 0x00000001
724 /* The mask used to clear the ALT_NAND_CFG_MULTIPLANE_OP_FLAG register field value. */
725 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_CLR_MSK 0xfffffffe
726 /* The reset value of the ALT_NAND_CFG_MULTIPLANE_OP_FLAG register field. */
727 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_RESET 0x0
728 /* Extracts the ALT_NAND_CFG_MULTIPLANE_OP_FLAG field value from a register. */
729 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_GET(value) (((value) & 0x00000001) >> 0)
730 /* Produces a ALT_NAND_CFG_MULTIPLANE_OP_FLAG register field value suitable for setting the register. */
731 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_SET(value) (((value) << 0) & 0x00000001)
732 
733 #ifndef __ASSEMBLY__
734 /*
735  * WARNING: The C register and register group struct declarations are provided for
736  * convenience and illustrative purposes. They should, however, be used with
737  * caution as the C language standard provides no guarantees about the alignment or
738  * atomicity of device memory accesses. The recommended practice for writing
739  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
740  * alt_write_word() functions.
741  *
742  * The struct declaration for register ALT_NAND_CFG_MULTIPLANE_OP.
743  */
744 struct ALT_NAND_CFG_MULTIPLANE_OP_s
745 {
746  uint32_t flag : 1; /* ALT_NAND_CFG_MULTIPLANE_OP_FLAG */
747  uint32_t : 31; /* *UNDEFINED* */
748 };
749 
750 /* The typedef declaration for register ALT_NAND_CFG_MULTIPLANE_OP. */
751 typedef volatile struct ALT_NAND_CFG_MULTIPLANE_OP_s ALT_NAND_CFG_MULTIPLANE_OP_t;
752 #endif /* __ASSEMBLY__ */
753 
754 /* The byte offset of the ALT_NAND_CFG_MULTIPLANE_OP register from the beginning of the component. */
755 #define ALT_NAND_CFG_MULTIPLANE_OP_OFST 0x70
756 
757 /*
758  * Register : multiplane_read_enable
759  *
760  * Device supports multiplane read command sequence
761  *
762  * Register Layout
763  *
764  * Bits | Access | Reset | Description
765  * :-------|:-------|:------|:-----------------------------------
766  * [0] | RW | 0x0 | ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG
767  * [31:1] | ??? | 0x0 | *UNDEFINED*
768  *
769  */
770 /*
771  * Field : flag
772  *
773  * Certain devices support dedicated multiplane read command sequences to read data
774  * in the same fashion as is written with multiplane program commands. This bit set
775  * should be set for the above devices. When not set, pipeline reads in multiplane
776  * mode will still happen in the order of multiplane writes, though normal read
777  * command sequences will be issued to the device. [list][*]1 - Device supports
778  * multiplane read sequence [*]0 - Device does not support multiplane read
779  * sequence[/list]
780  *
781  * Field Access Macros:
782  *
783  */
784 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG register field. */
785 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_LSB 0
786 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG register field. */
787 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_MSB 0
788 /* The width in bits of the ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG register field. */
789 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_WIDTH 1
790 /* The mask used to set the ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG register field value. */
791 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_SET_MSK 0x00000001
792 /* The mask used to clear the ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG register field value. */
793 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_CLR_MSK 0xfffffffe
794 /* The reset value of the ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG register field. */
795 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_RESET 0x0
796 /* Extracts the ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG field value from a register. */
797 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
798 /* Produces a ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG register field value suitable for setting the register. */
799 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
800 
801 #ifndef __ASSEMBLY__
802 /*
803  * WARNING: The C register and register group struct declarations are provided for
804  * convenience and illustrative purposes. They should, however, be used with
805  * caution as the C language standard provides no guarantees about the alignment or
806  * atomicity of device memory accesses. The recommended practice for writing
807  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
808  * alt_write_word() functions.
809  *
810  * The struct declaration for register ALT_NAND_CFG_MULTIPLANE_RD_EN.
811  */
812 struct ALT_NAND_CFG_MULTIPLANE_RD_EN_s
813 {
814  uint32_t flag : 1; /* ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG */
815  uint32_t : 31; /* *UNDEFINED* */
816 };
817 
818 /* The typedef declaration for register ALT_NAND_CFG_MULTIPLANE_RD_EN. */
819 typedef volatile struct ALT_NAND_CFG_MULTIPLANE_RD_EN_s ALT_NAND_CFG_MULTIPLANE_RD_EN_t;
820 #endif /* __ASSEMBLY__ */
821 
822 /* The byte offset of the ALT_NAND_CFG_MULTIPLANE_RD_EN register from the beginning of the component. */
823 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_OFST 0x80
824 
825 /*
826  * Register : copyback_disable
827  *
828  * Device does not support copyback command sequence
829  *
830  * Register Layout
831  *
832  * Bits | Access | Reset | Description
833  * :-------|:-------|:------|:-------------------------------
834  * [0] | RW | 0x0 | ALT_NAND_CFG_COPYBACK_DIS_FLAG
835  * [31:1] | ??? | 0x0 | *UNDEFINED*
836  *
837  */
838 /*
839  * Field : flag
840  *
841  * [list][*]1 - Copyback disabled [*]0 - Copyback enabled[/list]
842  *
843  * Field Access Macros:
844  *
845  */
846 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_COPYBACK_DIS_FLAG register field. */
847 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_LSB 0
848 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_COPYBACK_DIS_FLAG register field. */
849 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_MSB 0
850 /* The width in bits of the ALT_NAND_CFG_COPYBACK_DIS_FLAG register field. */
851 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_WIDTH 1
852 /* The mask used to set the ALT_NAND_CFG_COPYBACK_DIS_FLAG register field value. */
853 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_SET_MSK 0x00000001
854 /* The mask used to clear the ALT_NAND_CFG_COPYBACK_DIS_FLAG register field value. */
855 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_CLR_MSK 0xfffffffe
856 /* The reset value of the ALT_NAND_CFG_COPYBACK_DIS_FLAG register field. */
857 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_RESET 0x0
858 /* Extracts the ALT_NAND_CFG_COPYBACK_DIS_FLAG field value from a register. */
859 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_GET(value) (((value) & 0x00000001) >> 0)
860 /* Produces a ALT_NAND_CFG_COPYBACK_DIS_FLAG register field value suitable for setting the register. */
861 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_SET(value) (((value) << 0) & 0x00000001)
862 
863 #ifndef __ASSEMBLY__
864 /*
865  * WARNING: The C register and register group struct declarations are provided for
866  * convenience and illustrative purposes. They should, however, be used with
867  * caution as the C language standard provides no guarantees about the alignment or
868  * atomicity of device memory accesses. The recommended practice for writing
869  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
870  * alt_write_word() functions.
871  *
872  * The struct declaration for register ALT_NAND_CFG_COPYBACK_DIS.
873  */
874 struct ALT_NAND_CFG_COPYBACK_DIS_s
875 {
876  uint32_t flag : 1; /* ALT_NAND_CFG_COPYBACK_DIS_FLAG */
877  uint32_t : 31; /* *UNDEFINED* */
878 };
879 
880 /* The typedef declaration for register ALT_NAND_CFG_COPYBACK_DIS. */
881 typedef volatile struct ALT_NAND_CFG_COPYBACK_DIS_s ALT_NAND_CFG_COPYBACK_DIS_t;
882 #endif /* __ASSEMBLY__ */
883 
884 /* The byte offset of the ALT_NAND_CFG_COPYBACK_DIS register from the beginning of the component. */
885 #define ALT_NAND_CFG_COPYBACK_DIS_OFST 0x90
886 
887 /*
888  * Register : cache_write_enable
889  *
890  * Device supports cache write command sequence
891  *
892  * Register Layout
893  *
894  * Bits | Access | Reset | Description
895  * :-------|:-------|:------|:------------------------------
896  * [0] | RW | 0x0 | ALT_NAND_CFG_CACHE_WR_EN_FLAG
897  * [31:1] | ??? | 0x0 | *UNDEFINED*
898  *
899  */
900 /*
901  * Field : flag
902  *
903  * [list][*]1 - Cache write supported [*]0 - Cache write not supported[/list]
904  *
905  * Field Access Macros:
906  *
907  */
908 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_CACHE_WR_EN_FLAG register field. */
909 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_LSB 0
910 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_CACHE_WR_EN_FLAG register field. */
911 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_MSB 0
912 /* The width in bits of the ALT_NAND_CFG_CACHE_WR_EN_FLAG register field. */
913 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_WIDTH 1
914 /* The mask used to set the ALT_NAND_CFG_CACHE_WR_EN_FLAG register field value. */
915 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_SET_MSK 0x00000001
916 /* The mask used to clear the ALT_NAND_CFG_CACHE_WR_EN_FLAG register field value. */
917 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_CLR_MSK 0xfffffffe
918 /* The reset value of the ALT_NAND_CFG_CACHE_WR_EN_FLAG register field. */
919 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_RESET 0x0
920 /* Extracts the ALT_NAND_CFG_CACHE_WR_EN_FLAG field value from a register. */
921 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
922 /* Produces a ALT_NAND_CFG_CACHE_WR_EN_FLAG register field value suitable for setting the register. */
923 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
924 
925 #ifndef __ASSEMBLY__
926 /*
927  * WARNING: The C register and register group struct declarations are provided for
928  * convenience and illustrative purposes. They should, however, be used with
929  * caution as the C language standard provides no guarantees about the alignment or
930  * atomicity of device memory accesses. The recommended practice for writing
931  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
932  * alt_write_word() functions.
933  *
934  * The struct declaration for register ALT_NAND_CFG_CACHE_WR_EN.
935  */
936 struct ALT_NAND_CFG_CACHE_WR_EN_s
937 {
938  uint32_t flag : 1; /* ALT_NAND_CFG_CACHE_WR_EN_FLAG */
939  uint32_t : 31; /* *UNDEFINED* */
940 };
941 
942 /* The typedef declaration for register ALT_NAND_CFG_CACHE_WR_EN. */
943 typedef volatile struct ALT_NAND_CFG_CACHE_WR_EN_s ALT_NAND_CFG_CACHE_WR_EN_t;
944 #endif /* __ASSEMBLY__ */
945 
946 /* The byte offset of the ALT_NAND_CFG_CACHE_WR_EN register from the beginning of the component. */
947 #define ALT_NAND_CFG_CACHE_WR_EN_OFST 0xa0
948 
949 /*
950  * Register : cache_read_enable
951  *
952  * Device supports cache read command sequence
953  *
954  * Register Layout
955  *
956  * Bits | Access | Reset | Description
957  * :-------|:-------|:------|:------------------------------
958  * [0] | RW | 0x0 | ALT_NAND_CFG_CACHE_RD_EN_FLAG
959  * [31:1] | ??? | 0x0 | *UNDEFINED*
960  *
961  */
962 /*
963  * Field : flag
964  *
965  * [list][*]1 - Cache read supported [*]0 - Cache read not supported[/list]
966  *
967  * Field Access Macros:
968  *
969  */
970 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_CACHE_RD_EN_FLAG register field. */
971 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_LSB 0
972 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_CACHE_RD_EN_FLAG register field. */
973 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_MSB 0
974 /* The width in bits of the ALT_NAND_CFG_CACHE_RD_EN_FLAG register field. */
975 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_WIDTH 1
976 /* The mask used to set the ALT_NAND_CFG_CACHE_RD_EN_FLAG register field value. */
977 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_SET_MSK 0x00000001
978 /* The mask used to clear the ALT_NAND_CFG_CACHE_RD_EN_FLAG register field value. */
979 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_CLR_MSK 0xfffffffe
980 /* The reset value of the ALT_NAND_CFG_CACHE_RD_EN_FLAG register field. */
981 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_RESET 0x0
982 /* Extracts the ALT_NAND_CFG_CACHE_RD_EN_FLAG field value from a register. */
983 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
984 /* Produces a ALT_NAND_CFG_CACHE_RD_EN_FLAG register field value suitable for setting the register. */
985 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
986 
987 #ifndef __ASSEMBLY__
988 /*
989  * WARNING: The C register and register group struct declarations are provided for
990  * convenience and illustrative purposes. They should, however, be used with
991  * caution as the C language standard provides no guarantees about the alignment or
992  * atomicity of device memory accesses. The recommended practice for writing
993  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
994  * alt_write_word() functions.
995  *
996  * The struct declaration for register ALT_NAND_CFG_CACHE_RD_EN.
997  */
998 struct ALT_NAND_CFG_CACHE_RD_EN_s
999 {
1000  uint32_t flag : 1; /* ALT_NAND_CFG_CACHE_RD_EN_FLAG */
1001  uint32_t : 31; /* *UNDEFINED* */
1002 };
1003 
1004 /* The typedef declaration for register ALT_NAND_CFG_CACHE_RD_EN. */
1005 typedef volatile struct ALT_NAND_CFG_CACHE_RD_EN_s ALT_NAND_CFG_CACHE_RD_EN_t;
1006 #endif /* __ASSEMBLY__ */
1007 
1008 /* The byte offset of the ALT_NAND_CFG_CACHE_RD_EN register from the beginning of the component. */
1009 #define ALT_NAND_CFG_CACHE_RD_EN_OFST 0xb0
1010 
1011 /*
1012  * Register : prefetch_mode
1013  *
1014  * Enables read data prefetching to faster performance
1015  *
1016  * Register Layout
1017  *
1018  * Bits | Access | Reset | Description
1019  * :--------|:-------|:------|:---------------------------------------------
1020  * [0] | RW | 0x1 | ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN
1021  * [3:1] | ??? | 0x0 | *UNDEFINED*
1022  * [15:4] | RW | 0x0 | ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN
1023  * [31:16] | ??? | 0x0 | *UNDEFINED*
1024  *
1025  */
1026 /*
1027  * Field : prefetch_en
1028  *
1029  * Enable prefetch of Data
1030  *
1031  * Field Access Macros:
1032  *
1033  */
1034 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN register field. */
1035 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_LSB 0
1036 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN register field. */
1037 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_MSB 0
1038 /* The width in bits of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN register field. */
1039 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_WIDTH 1
1040 /* The mask used to set the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN register field value. */
1041 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_SET_MSK 0x00000001
1042 /* The mask used to clear the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN register field value. */
1043 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_CLR_MSK 0xfffffffe
1044 /* The reset value of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN register field. */
1045 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_RESET 0x1
1046 /* Extracts the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN field value from a register. */
1047 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_GET(value) (((value) & 0x00000001) >> 0)
1048 /* Produces a ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN register field value suitable for setting the register. */
1049 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_SET(value) (((value) << 0) & 0x00000001)
1050 
1051 /*
1052  * Field : prefetch_burst_length
1053  *
1054  * If prefetch_en is set and prefetch_burst_length is set to ZERO, the controller
1055  * will start prefetching data only after the receiving the first Map01 read
1056  * command for the page. If prefetch_en is set and prefetch_burst_length is set to
1057  * a non-ZERO, valid value, the controller will start prefetching data
1058  * corresponding to this value even before the first Map01 for the current page has
1059  * been received. The value written here should be in bytes.
1060  *
1061  * Field Access Macros:
1062  *
1063  */
1064 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN register field. */
1065 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_LSB 4
1066 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN register field. */
1067 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_MSB 15
1068 /* The width in bits of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN register field. */
1069 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_WIDTH 12
1070 /* The mask used to set the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN register field value. */
1071 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_SET_MSK 0x0000fff0
1072 /* The mask used to clear the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN register field value. */
1073 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_CLR_MSK 0xffff000f
1074 /* The reset value of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN register field. */
1075 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_RESET 0x0
1076 /* Extracts the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN field value from a register. */
1077 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_GET(value) (((value) & 0x0000fff0) >> 4)
1078 /* Produces a ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN register field value suitable for setting the register. */
1079 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_SET(value) (((value) << 4) & 0x0000fff0)
1080 
1081 #ifndef __ASSEMBLY__
1082 /*
1083  * WARNING: The C register and register group struct declarations are provided for
1084  * convenience and illustrative purposes. They should, however, be used with
1085  * caution as the C language standard provides no guarantees about the alignment or
1086  * atomicity of device memory accesses. The recommended practice for writing
1087  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1088  * alt_write_word() functions.
1089  *
1090  * The struct declaration for register ALT_NAND_CFG_PREFETCH_MOD.
1091  */
1092 struct ALT_NAND_CFG_PREFETCH_MOD_s
1093 {
1094  uint32_t prefetch_en : 1; /* ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN */
1095  uint32_t : 3; /* *UNDEFINED* */
1096  uint32_t prefetch_burst_length : 12; /* ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN */
1097  uint32_t : 16; /* *UNDEFINED* */
1098 };
1099 
1100 /* The typedef declaration for register ALT_NAND_CFG_PREFETCH_MOD. */
1101 typedef volatile struct ALT_NAND_CFG_PREFETCH_MOD_s ALT_NAND_CFG_PREFETCH_MOD_t;
1102 #endif /* __ASSEMBLY__ */
1103 
1104 /* The byte offset of the ALT_NAND_CFG_PREFETCH_MOD register from the beginning of the component. */
1105 #define ALT_NAND_CFG_PREFETCH_MOD_OFST 0xc0
1106 
1107 /*
1108  * Register : chip_enable_dont_care
1109  *
1110  * Device can work in the chip enable dont care mode
1111  *
1112  * Register Layout
1113  *
1114  * Bits | Access | Reset | Description
1115  * :-------|:-------|:------|:------------------------------------
1116  * [0] | RW | 0x0 | ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG
1117  * [31:1] | ??? | 0x0 | *UNDEFINED*
1118  *
1119  */
1120 /*
1121  * Field : flag
1122  *
1123  * Controller can interleave commands between banks when this feature is enabled.
1124  * [list][*]1 - Device in dont care mode [*]0 - Device cares for chip enable[/list]
1125  *
1126  * Field Access Macros:
1127  *
1128  */
1129 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG register field. */
1130 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_LSB 0
1131 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG register field. */
1132 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_MSB 0
1133 /* The width in bits of the ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG register field. */
1134 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_WIDTH 1
1135 /* The mask used to set the ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG register field value. */
1136 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_SET_MSK 0x00000001
1137 /* The mask used to clear the ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG register field value. */
1138 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_CLR_MSK 0xfffffffe
1139 /* The reset value of the ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG register field. */
1140 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_RESET 0x0
1141 /* Extracts the ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG field value from a register. */
1142 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1143 /* Produces a ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG register field value suitable for setting the register. */
1144 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_SET(value) (((value) << 0) & 0x00000001)
1145 
1146 #ifndef __ASSEMBLY__
1147 /*
1148  * WARNING: The C register and register group struct declarations are provided for
1149  * convenience and illustrative purposes. They should, however, be used with
1150  * caution as the C language standard provides no guarantees about the alignment or
1151  * atomicity of device memory accesses. The recommended practice for writing
1152  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1153  * alt_write_word() functions.
1154  *
1155  * The struct declaration for register ALT_NAND_CFG_CHIP_EN_DONT_CARE.
1156  */
1157 struct ALT_NAND_CFG_CHIP_EN_DONT_CARE_s
1158 {
1159  uint32_t flag : 1; /* ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG */
1160  uint32_t : 31; /* *UNDEFINED* */
1161 };
1162 
1163 /* The typedef declaration for register ALT_NAND_CFG_CHIP_EN_DONT_CARE. */
1164 typedef volatile struct ALT_NAND_CFG_CHIP_EN_DONT_CARE_s ALT_NAND_CFG_CHIP_EN_DONT_CARE_t;
1165 #endif /* __ASSEMBLY__ */
1166 
1167 /* The byte offset of the ALT_NAND_CFG_CHIP_EN_DONT_CARE register from the beginning of the component. */
1168 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_OFST 0xd0
1169 
1170 /*
1171  * Register : ecc_enable
1172  *
1173  * Enable controller ECC check bit generation and correction
1174  *
1175  * Register Layout
1176  *
1177  * Bits | Access | Reset | Description
1178  * :-------|:-------|:------|:-------------------------
1179  * [0] | RW | 0x1 | ALT_NAND_CFG_ECC_EN_FLAG
1180  * [31:1] | ??? | 0x0 | *UNDEFINED*
1181  *
1182  */
1183 /*
1184  * Field : flag
1185  *
1186  * Enables or disables controller ECC capabilities. When enabled, controller
1187  * calculates ECC check-bits and writes them onto device on program operation. On
1188  * page reads, check-bits are recomputed and errors reported, if any, after
1189  * comparing with stored check-bits. When disabled, controller does not compute
1190  * check-bits. [list][*]1 - ECC Enabled [*]0 - ECC disabled[/list]
1191  *
1192  * Field Access Macros:
1193  *
1194  */
1195 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_ECC_EN_FLAG register field. */
1196 #define ALT_NAND_CFG_ECC_EN_FLAG_LSB 0
1197 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_ECC_EN_FLAG register field. */
1198 #define ALT_NAND_CFG_ECC_EN_FLAG_MSB 0
1199 /* The width in bits of the ALT_NAND_CFG_ECC_EN_FLAG register field. */
1200 #define ALT_NAND_CFG_ECC_EN_FLAG_WIDTH 1
1201 /* The mask used to set the ALT_NAND_CFG_ECC_EN_FLAG register field value. */
1202 #define ALT_NAND_CFG_ECC_EN_FLAG_SET_MSK 0x00000001
1203 /* The mask used to clear the ALT_NAND_CFG_ECC_EN_FLAG register field value. */
1204 #define ALT_NAND_CFG_ECC_EN_FLAG_CLR_MSK 0xfffffffe
1205 /* The reset value of the ALT_NAND_CFG_ECC_EN_FLAG register field. */
1206 #define ALT_NAND_CFG_ECC_EN_FLAG_RESET 0x1
1207 /* Extracts the ALT_NAND_CFG_ECC_EN_FLAG field value from a register. */
1208 #define ALT_NAND_CFG_ECC_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1209 /* Produces a ALT_NAND_CFG_ECC_EN_FLAG register field value suitable for setting the register. */
1210 #define ALT_NAND_CFG_ECC_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
1211 
1212 #ifndef __ASSEMBLY__
1213 /*
1214  * WARNING: The C register and register group struct declarations are provided for
1215  * convenience and illustrative purposes. They should, however, be used with
1216  * caution as the C language standard provides no guarantees about the alignment or
1217  * atomicity of device memory accesses. The recommended practice for writing
1218  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1219  * alt_write_word() functions.
1220  *
1221  * The struct declaration for register ALT_NAND_CFG_ECC_EN.
1222  */
1223 struct ALT_NAND_CFG_ECC_EN_s
1224 {
1225  uint32_t flag : 1; /* ALT_NAND_CFG_ECC_EN_FLAG */
1226  uint32_t : 31; /* *UNDEFINED* */
1227 };
1228 
1229 /* The typedef declaration for register ALT_NAND_CFG_ECC_EN. */
1230 typedef volatile struct ALT_NAND_CFG_ECC_EN_s ALT_NAND_CFG_ECC_EN_t;
1231 #endif /* __ASSEMBLY__ */
1232 
1233 /* The byte offset of the ALT_NAND_CFG_ECC_EN register from the beginning of the component. */
1234 #define ALT_NAND_CFG_ECC_EN_OFST 0xe0
1235 
1236 /*
1237  * Register : global_int_enable
1238  *
1239  * Global Interrupt enable and Error/Timeout disable.
1240  *
1241  * Register Layout
1242  *
1243  * Bits | Access | Reset | Description
1244  * :-------|:-------|:------|:---------------------------------------
1245  * [0] | RW | 0x0 | ALT_NAND_CFG_GLOB_INT_EN_FLAG
1246  * [3:1] | ??? | 0x0 | *UNDEFINED*
1247  * [4] | RW | 0x0 | ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS
1248  * [7:5] | ??? | 0x0 | *UNDEFINED*
1249  * [8] | RW | 0x0 | ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS
1250  * [31:9] | ??? | 0x0 | *UNDEFINED*
1251  *
1252  */
1253 /*
1254  * Field : flag
1255  *
1256  * Host will receive an interrupt only when this bit is set.
1257  *
1258  * Field Access Macros:
1259  *
1260  */
1261 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_GLOB_INT_EN_FLAG register field. */
1262 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_LSB 0
1263 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_GLOB_INT_EN_FLAG register field. */
1264 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_MSB 0
1265 /* The width in bits of the ALT_NAND_CFG_GLOB_INT_EN_FLAG register field. */
1266 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_WIDTH 1
1267 /* The mask used to set the ALT_NAND_CFG_GLOB_INT_EN_FLAG register field value. */
1268 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_SET_MSK 0x00000001
1269 /* The mask used to clear the ALT_NAND_CFG_GLOB_INT_EN_FLAG register field value. */
1270 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_CLR_MSK 0xfffffffe
1271 /* The reset value of the ALT_NAND_CFG_GLOB_INT_EN_FLAG register field. */
1272 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_RESET 0x0
1273 /* Extracts the ALT_NAND_CFG_GLOB_INT_EN_FLAG field value from a register. */
1274 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1275 /* Produces a ALT_NAND_CFG_GLOB_INT_EN_FLAG register field value suitable for setting the register. */
1276 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
1277 
1278 /*
1279  * Field : timeout_disable
1280  *
1281  * Watchdog timer logic will be de-activated when this bit is set.
1282  *
1283  * Field Access Macros:
1284  *
1285  */
1286 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS register field. */
1287 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_LSB 4
1288 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS register field. */
1289 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_MSB 4
1290 /* The width in bits of the ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS register field. */
1291 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_WIDTH 1
1292 /* The mask used to set the ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS register field value. */
1293 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_SET_MSK 0x00000010
1294 /* The mask used to clear the ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS register field value. */
1295 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_CLR_MSK 0xffffffef
1296 /* The reset value of the ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS register field. */
1297 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_RESET 0x0
1298 /* Extracts the ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS field value from a register. */
1299 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_GET(value) (((value) & 0x00000010) >> 4)
1300 /* Produces a ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS register field value suitable for setting the register. */
1301 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_SET(value) (((value) << 4) & 0x00000010)
1302 
1303 /*
1304  * Field : error_rpt_disable
1305  *
1306  * Command and ECC uncorrectable failures will not be reported when this bit is set
1307  *
1308  * Field Access Macros:
1309  *
1310  */
1311 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS register field. */
1312 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_LSB 8
1313 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS register field. */
1314 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_MSB 8
1315 /* The width in bits of the ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS register field. */
1316 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_WIDTH 1
1317 /* The mask used to set the ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS register field value. */
1318 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_SET_MSK 0x00000100
1319 /* The mask used to clear the ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS register field value. */
1320 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_CLR_MSK 0xfffffeff
1321 /* The reset value of the ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS register field. */
1322 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_RESET 0x0
1323 /* Extracts the ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS field value from a register. */
1324 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_GET(value) (((value) & 0x00000100) >> 8)
1325 /* Produces a ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS register field value suitable for setting the register. */
1326 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_SET(value) (((value) << 8) & 0x00000100)
1327 
1328 #ifndef __ASSEMBLY__
1329 /*
1330  * WARNING: The C register and register group struct declarations are provided for
1331  * convenience and illustrative purposes. They should, however, be used with
1332  * caution as the C language standard provides no guarantees about the alignment or
1333  * atomicity of device memory accesses. The recommended practice for writing
1334  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1335  * alt_write_word() functions.
1336  *
1337  * The struct declaration for register ALT_NAND_CFG_GLOB_INT_EN.
1338  */
1339 struct ALT_NAND_CFG_GLOB_INT_EN_s
1340 {
1341  uint32_t flag : 1; /* ALT_NAND_CFG_GLOB_INT_EN_FLAG */
1342  uint32_t : 3; /* *UNDEFINED* */
1343  uint32_t timeout_disable : 1; /* ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS */
1344  uint32_t : 3; /* *UNDEFINED* */
1345  uint32_t error_rpt_disable : 1; /* ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS */
1346  uint32_t : 23; /* *UNDEFINED* */
1347 };
1348 
1349 /* The typedef declaration for register ALT_NAND_CFG_GLOB_INT_EN. */
1350 typedef volatile struct ALT_NAND_CFG_GLOB_INT_EN_s ALT_NAND_CFG_GLOB_INT_EN_t;
1351 #endif /* __ASSEMBLY__ */
1352 
1353 /* The byte offset of the ALT_NAND_CFG_GLOB_INT_EN register from the beginning of the component. */
1354 #define ALT_NAND_CFG_GLOB_INT_EN_OFST 0xf0
1355 
1356 /*
1357  * Register : twhr2_and_we_2_re
1358  *
1359  * Register Layout
1360  *
1361  * Bits | Access | Reset | Description
1362  * :--------|:-------|:------|:---------------------------------------
1363  * [5:0] | RW | 0x32 | ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE
1364  * [7:6] | ??? | 0x0 | *UNDEFINED*
1365  * [13:8] | RW | 0x14 | ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2
1366  * [31:14] | ??? | 0x0 | *UNDEFINED*
1367  *
1368  */
1369 /*
1370  * Field : we_2_re
1371  *
1372  * Signifies the number of bus interface nand_mp_clk clocks that should be
1373  * introduced between write enable going high to read enable going low. The number
1374  * of clocks is the function of device parameter Twhr and controller clock
1375  * frequency.
1376  *
1377  * Field Access Macros:
1378  *
1379  */
1380 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field. */
1381 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_LSB 0
1382 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field. */
1383 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_MSB 5
1384 /* The width in bits of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field. */
1385 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_WIDTH 6
1386 /* The mask used to set the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field value. */
1387 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_SET_MSK 0x0000003f
1388 /* The mask used to clear the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field value. */
1389 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_CLR_MSK 0xffffffc0
1390 /* The reset value of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field. */
1391 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_RESET 0x32
1392 /* Extracts the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE field value from a register. */
1393 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_GET(value) (((value) & 0x0000003f) >> 0)
1394 /* Produces a ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field value suitable for setting the register. */
1395 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_SET(value) (((value) << 0) & 0x0000003f)
1396 
1397 /*
1398  * Field : twhr2
1399  *
1400  * Signifies the number of controller clocks that should be introduced between the
1401  * last command of a random data output command to the start of the data transfer.
1402  *
1403  * Field Access Macros:
1404  *
1405  */
1406 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field. */
1407 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_LSB 8
1408 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field. */
1409 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_MSB 13
1410 /* The width in bits of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field. */
1411 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_WIDTH 6
1412 /* The mask used to set the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field value. */
1413 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_SET_MSK 0x00003f00
1414 /* The mask used to clear the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field value. */
1415 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_CLR_MSK 0xffffc0ff
1416 /* The reset value of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field. */
1417 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_RESET 0x14
1418 /* Extracts the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 field value from a register. */
1419 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_GET(value) (((value) & 0x00003f00) >> 8)
1420 /* Produces a ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field value suitable for setting the register. */
1421 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_SET(value) (((value) << 8) & 0x00003f00)
1422 
1423 #ifndef __ASSEMBLY__
1424 /*
1425  * WARNING: The C register and register group struct declarations are provided for
1426  * convenience and illustrative purposes. They should, however, be used with
1427  * caution as the C language standard provides no guarantees about the alignment or
1428  * atomicity of device memory accesses. The recommended practice for writing
1429  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1430  * alt_write_word() functions.
1431  *
1432  * The struct declaration for register ALT_NAND_CFG_TWHR2_AND_WE_2_RE.
1433  */
1434 struct ALT_NAND_CFG_TWHR2_AND_WE_2_RE_s
1435 {
1436  uint32_t we_2_re : 6; /* ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE */
1437  uint32_t : 2; /* *UNDEFINED* */
1438  uint32_t twhr2 : 6; /* ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 */
1439  uint32_t : 18; /* *UNDEFINED* */
1440 };
1441 
1442 /* The typedef declaration for register ALT_NAND_CFG_TWHR2_AND_WE_2_RE. */
1443 typedef volatile struct ALT_NAND_CFG_TWHR2_AND_WE_2_RE_s ALT_NAND_CFG_TWHR2_AND_WE_2_RE_t;
1444 #endif /* __ASSEMBLY__ */
1445 
1446 /* The byte offset of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE register from the beginning of the component. */
1447 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_OFST 0x100
1448 
1449 /*
1450  * Register : tcwaw_and_addr_2_data
1451  *
1452  * Register Layout
1453  *
1454  * Bits | Access | Reset | Description
1455  * :--------|:-------|:------|:-----------------------------------------------
1456  * [5:0] | RW | 0x32 | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA
1457  * [7:6] | ??? | 0x0 | *UNDEFINED*
1458  * [13:8] | RW | 0x14 | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW
1459  * [31:14] | ??? | 0x0 | *UNDEFINED*
1460  *
1461  */
1462 /*
1463  * Field : addr_2_data
1464  *
1465  * Signifies the number of bus interface nand_mp_clk clocks that should be
1466  * introduced between address latch enable going low to write enable going low. The
1467  * number of clocks is the function of device parameter Tadl and controller clock
1468  * frequency.
1469  *
1470  * Field Access Macros:
1471  *
1472  */
1473 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field. */
1474 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_LSB 0
1475 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field. */
1476 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_MSB 5
1477 /* The width in bits of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field. */
1478 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_WIDTH 6
1479 /* The mask used to set the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field value. */
1480 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_SET_MSK 0x0000003f
1481 /* The mask used to clear the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field value. */
1482 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_CLR_MSK 0xffffffc0
1483 /* The reset value of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field. */
1484 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_RESET 0x32
1485 /* Extracts the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA field value from a register. */
1486 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_GET(value) (((value) & 0x0000003f) >> 0)
1487 /* Produces a ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field value suitable for setting the register. */
1488 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_SET(value) (((value) << 0) & 0x0000003f)
1489 
1490 /*
1491  * Field : tcwaw
1492  *
1493  * Signifies the number of controller clocks that should be introduced between the
1494  * command cycle of a random data input command to the address cycle of the random
1495  * data input command.
1496  *
1497  * Field Access Macros:
1498  *
1499  */
1500 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field. */
1501 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_LSB 8
1502 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field. */
1503 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_MSB 13
1504 /* The width in bits of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field. */
1505 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_WIDTH 6
1506 /* The mask used to set the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field value. */
1507 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_SET_MSK 0x00003f00
1508 /* The mask used to clear the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field value. */
1509 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_CLR_MSK 0xffffc0ff
1510 /* The reset value of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field. */
1511 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_RESET 0x14
1512 /* Extracts the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW field value from a register. */
1513 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_GET(value) (((value) & 0x00003f00) >> 8)
1514 /* Produces a ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field value suitable for setting the register. */
1515 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_SET(value) (((value) << 8) & 0x00003f00)
1516 
1517 #ifndef __ASSEMBLY__
1518 /*
1519  * WARNING: The C register and register group struct declarations are provided for
1520  * convenience and illustrative purposes. They should, however, be used with
1521  * caution as the C language standard provides no guarantees about the alignment or
1522  * atomicity of device memory accesses. The recommended practice for writing
1523  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1524  * alt_write_word() functions.
1525  *
1526  * The struct declaration for register ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA.
1527  */
1528 struct ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_s
1529 {
1530  uint32_t addr_2_data : 6; /* ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA */
1531  uint32_t : 2; /* *UNDEFINED* */
1532  uint32_t tcwaw : 6; /* ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW */
1533  uint32_t : 18; /* *UNDEFINED* */
1534 };
1535 
1536 /* The typedef declaration for register ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA. */
1537 typedef volatile struct ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_s ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_t;
1538 #endif /* __ASSEMBLY__ */
1539 
1540 /* The byte offset of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA register from the beginning of the component. */
1541 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_OFST 0x110
1542 
1543 /*
1544  * Register : re_2_we
1545  *
1546  * Timing parameter between re high to we low (Trhw)
1547  *
1548  * Register Layout
1549  *
1550  * Bits | Access | Reset | Description
1551  * :-------|:-------|:------|:---------------------------
1552  * [5:0] | RW | 0x32 | ALT_NAND_CFG_RE_2_WE_VALUE
1553  * [31:6] | ??? | 0x0 | *UNDEFINED*
1554  *
1555  */
1556 /*
1557  * Field : value
1558  *
1559  * Signifies the number of bus interface nand_mp_clk clocks that should be
1560  * introduced between read enable going high to write enable going low. The number
1561  * of clocks is the function of device parameter Trhw and controller clock
1562  * frequency.
1563  *
1564  * Field Access Macros:
1565  *
1566  */
1567 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RE_2_WE_VALUE register field. */
1568 #define ALT_NAND_CFG_RE_2_WE_VALUE_LSB 0
1569 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RE_2_WE_VALUE register field. */
1570 #define ALT_NAND_CFG_RE_2_WE_VALUE_MSB 5
1571 /* The width in bits of the ALT_NAND_CFG_RE_2_WE_VALUE register field. */
1572 #define ALT_NAND_CFG_RE_2_WE_VALUE_WIDTH 6
1573 /* The mask used to set the ALT_NAND_CFG_RE_2_WE_VALUE register field value. */
1574 #define ALT_NAND_CFG_RE_2_WE_VALUE_SET_MSK 0x0000003f
1575 /* The mask used to clear the ALT_NAND_CFG_RE_2_WE_VALUE register field value. */
1576 #define ALT_NAND_CFG_RE_2_WE_VALUE_CLR_MSK 0xffffffc0
1577 /* The reset value of the ALT_NAND_CFG_RE_2_WE_VALUE register field. */
1578 #define ALT_NAND_CFG_RE_2_WE_VALUE_RESET 0x32
1579 /* Extracts the ALT_NAND_CFG_RE_2_WE_VALUE field value from a register. */
1580 #define ALT_NAND_CFG_RE_2_WE_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
1581 /* Produces a ALT_NAND_CFG_RE_2_WE_VALUE register field value suitable for setting the register. */
1582 #define ALT_NAND_CFG_RE_2_WE_VALUE_SET(value) (((value) << 0) & 0x0000003f)
1583 
1584 #ifndef __ASSEMBLY__
1585 /*
1586  * WARNING: The C register and register group struct declarations are provided for
1587  * convenience and illustrative purposes. They should, however, be used with
1588  * caution as the C language standard provides no guarantees about the alignment or
1589  * atomicity of device memory accesses. The recommended practice for writing
1590  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1591  * alt_write_word() functions.
1592  *
1593  * The struct declaration for register ALT_NAND_CFG_RE_2_WE.
1594  */
1595 struct ALT_NAND_CFG_RE_2_WE_s
1596 {
1597  uint32_t value : 6; /* ALT_NAND_CFG_RE_2_WE_VALUE */
1598  uint32_t : 26; /* *UNDEFINED* */
1599 };
1600 
1601 /* The typedef declaration for register ALT_NAND_CFG_RE_2_WE. */
1602 typedef volatile struct ALT_NAND_CFG_RE_2_WE_s ALT_NAND_CFG_RE_2_WE_t;
1603 #endif /* __ASSEMBLY__ */
1604 
1605 /* The byte offset of the ALT_NAND_CFG_RE_2_WE register from the beginning of the component. */
1606 #define ALT_NAND_CFG_RE_2_WE_OFST 0x120
1607 
1608 /*
1609  * Register : acc_clks
1610  *
1611  * Timing parameter from read enable going low to capture read data
1612  *
1613  * Register Layout
1614  *
1615  * Bits | Access | Reset | Description
1616  * :-------|:-------|:------|:----------------------------
1617  * [3:0] | RW | 0x0 | ALT_NAND_CFG_ACC_CLKS_VALUE
1618  * [31:4] | ??? | 0x0 | *UNDEFINED*
1619  *
1620  */
1621 /*
1622  * Field : value
1623  *
1624  * Signifies the number of bus interface nand_mp_clk clock cycles, controller
1625  * should wait from read enable going low to sending out a strobe of nand_mp_clk
1626  * for capturing of incoming data.
1627  *
1628  * Field Access Macros:
1629  *
1630  */
1631 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_ACC_CLKS_VALUE register field. */
1632 #define ALT_NAND_CFG_ACC_CLKS_VALUE_LSB 0
1633 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_ACC_CLKS_VALUE register field. */
1634 #define ALT_NAND_CFG_ACC_CLKS_VALUE_MSB 3
1635 /* The width in bits of the ALT_NAND_CFG_ACC_CLKS_VALUE register field. */
1636 #define ALT_NAND_CFG_ACC_CLKS_VALUE_WIDTH 4
1637 /* The mask used to set the ALT_NAND_CFG_ACC_CLKS_VALUE register field value. */
1638 #define ALT_NAND_CFG_ACC_CLKS_VALUE_SET_MSK 0x0000000f
1639 /* The mask used to clear the ALT_NAND_CFG_ACC_CLKS_VALUE register field value. */
1640 #define ALT_NAND_CFG_ACC_CLKS_VALUE_CLR_MSK 0xfffffff0
1641 /* The reset value of the ALT_NAND_CFG_ACC_CLKS_VALUE register field. */
1642 #define ALT_NAND_CFG_ACC_CLKS_VALUE_RESET 0x0
1643 /* Extracts the ALT_NAND_CFG_ACC_CLKS_VALUE field value from a register. */
1644 #define ALT_NAND_CFG_ACC_CLKS_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
1645 /* Produces a ALT_NAND_CFG_ACC_CLKS_VALUE register field value suitable for setting the register. */
1646 #define ALT_NAND_CFG_ACC_CLKS_VALUE_SET(value) (((value) << 0) & 0x0000000f)
1647 
1648 #ifndef __ASSEMBLY__
1649 /*
1650  * WARNING: The C register and register group struct declarations are provided for
1651  * convenience and illustrative purposes. They should, however, be used with
1652  * caution as the C language standard provides no guarantees about the alignment or
1653  * atomicity of device memory accesses. The recommended practice for writing
1654  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1655  * alt_write_word() functions.
1656  *
1657  * The struct declaration for register ALT_NAND_CFG_ACC_CLKS.
1658  */
1659 struct ALT_NAND_CFG_ACC_CLKS_s
1660 {
1661  uint32_t value : 4; /* ALT_NAND_CFG_ACC_CLKS_VALUE */
1662  uint32_t : 28; /* *UNDEFINED* */
1663 };
1664 
1665 /* The typedef declaration for register ALT_NAND_CFG_ACC_CLKS. */
1666 typedef volatile struct ALT_NAND_CFG_ACC_CLKS_s ALT_NAND_CFG_ACC_CLKS_t;
1667 #endif /* __ASSEMBLY__ */
1668 
1669 /* The byte offset of the ALT_NAND_CFG_ACC_CLKS register from the beginning of the component. */
1670 #define ALT_NAND_CFG_ACC_CLKS_OFST 0x130
1671 
1672 /*
1673  * Register : number_of_planes
1674  *
1675  * Number of planes in the device
1676  *
1677  * Register Layout
1678  *
1679  * Bits | Access | Reset | Description
1680  * :-------|:-------|:------|:------------------------------------
1681  * [2:0] | RW | 0x0 | ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE
1682  * [31:3] | ??? | 0x0 | *UNDEFINED*
1683  *
1684  */
1685 /*
1686  * Field : value
1687  *
1688  * Controller will read Electronic Signature of devices and populate this field as
1689  * the number of planes information is present in the signature. For 512B device,
1690  * this information needs to be programmed by software. Software could also choose
1691  * to override the populated value. The values in the fields should be as
1692  * follows[list] [*]3'h0 - Monoplane device [*]3'h1 - Two plane device [*]3'h3 - 4
1693  * plane device [*]3'h7 - 8 plane device [*]All other values - Reserved[/list]
1694  *
1695  * Field Access Macros:
1696  *
1697  */
1698 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field. */
1699 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_LSB 0
1700 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field. */
1701 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_MSB 2
1702 /* The width in bits of the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field. */
1703 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_WIDTH 3
1704 /* The mask used to set the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field value. */
1705 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_SET_MSK 0x00000007
1706 /* The mask used to clear the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field value. */
1707 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_CLR_MSK 0xfffffff8
1708 /* The reset value of the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field. */
1709 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_RESET 0x0
1710 /* Extracts the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE field value from a register. */
1711 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_GET(value) (((value) & 0x00000007) >> 0)
1712 /* Produces a ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field value suitable for setting the register. */
1713 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_SET(value) (((value) << 0) & 0x00000007)
1714 
1715 #ifndef __ASSEMBLY__
1716 /*
1717  * WARNING: The C register and register group struct declarations are provided for
1718  * convenience and illustrative purposes. They should, however, be used with
1719  * caution as the C language standard provides no guarantees about the alignment or
1720  * atomicity of device memory accesses. The recommended practice for writing
1721  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1722  * alt_write_word() functions.
1723  *
1724  * The struct declaration for register ALT_NAND_CFG_NUMBER_OF_PLANES.
1725  */
1726 struct ALT_NAND_CFG_NUMBER_OF_PLANES_s
1727 {
1728  uint32_t value : 3; /* ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE */
1729  uint32_t : 29; /* *UNDEFINED* */
1730 };
1731 
1732 /* The typedef declaration for register ALT_NAND_CFG_NUMBER_OF_PLANES. */
1733 typedef volatile struct ALT_NAND_CFG_NUMBER_OF_PLANES_s ALT_NAND_CFG_NUMBER_OF_PLANES_t;
1734 #endif /* __ASSEMBLY__ */
1735 
1736 /* The byte offset of the ALT_NAND_CFG_NUMBER_OF_PLANES register from the beginning of the component. */
1737 #define ALT_NAND_CFG_NUMBER_OF_PLANES_OFST 0x140
1738 
1739 /*
1740  * Register : pages_per_block
1741  *
1742  * Number of pages in a block
1743  *
1744  * Register Layout
1745  *
1746  * Bits | Access | Reset | Description
1747  * :--------|:-------|:------|:-----------------------------------
1748  * [15:0] | RW | 0x0 | ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE
1749  * [31:16] | ??? | 0x0 | *UNDEFINED*
1750  *
1751  */
1752 /*
1753  * Field : value
1754  *
1755  * Controller will read Electronic Signature of devices and populate this field.
1756  * The PAGE512 field of the System Manager NANDGRP_BOOTSTRAP register will
1757  * determine the value of this field to be of 32. Software could also choose to
1758  * override the populated value.
1759  *
1760  * Field Access Macros:
1761  *
1762  */
1763 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field. */
1764 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_LSB 0
1765 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field. */
1766 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_MSB 15
1767 /* The width in bits of the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field. */
1768 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_WIDTH 16
1769 /* The mask used to set the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field value. */
1770 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_SET_MSK 0x0000ffff
1771 /* The mask used to clear the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field value. */
1772 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_CLR_MSK 0xffff0000
1773 /* The reset value of the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field. */
1774 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_RESET 0x0
1775 /* Extracts the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE field value from a register. */
1776 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
1777 /* Produces a ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field value suitable for setting the register. */
1778 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
1779 
1780 #ifndef __ASSEMBLY__
1781 /*
1782  * WARNING: The C register and register group struct declarations are provided for
1783  * convenience and illustrative purposes. They should, however, be used with
1784  * caution as the C language standard provides no guarantees about the alignment or
1785  * atomicity of device memory accesses. The recommended practice for writing
1786  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1787  * alt_write_word() functions.
1788  *
1789  * The struct declaration for register ALT_NAND_CFG_PAGES_PER_BLOCK.
1790  */
1791 struct ALT_NAND_CFG_PAGES_PER_BLOCK_s
1792 {
1793  uint32_t value : 16; /* ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE */
1794  uint32_t : 16; /* *UNDEFINED* */
1795 };
1796 
1797 /* The typedef declaration for register ALT_NAND_CFG_PAGES_PER_BLOCK. */
1798 typedef volatile struct ALT_NAND_CFG_PAGES_PER_BLOCK_s ALT_NAND_CFG_PAGES_PER_BLOCK_t;
1799 #endif /* __ASSEMBLY__ */
1800 
1801 /* The byte offset of the ALT_NAND_CFG_PAGES_PER_BLOCK register from the beginning of the component. */
1802 #define ALT_NAND_CFG_PAGES_PER_BLOCK_OFST 0x150
1803 
1804 /*
1805  * Register : device_width
1806  *
1807  * I/O width of attached devices
1808  *
1809  * Register Layout
1810  *
1811  * Bits | Access | Reset | Description
1812  * :-------|:-------|:------|:--------------------------------
1813  * [1:0] | RW | 0x3 | ALT_NAND_CFG_DEVICE_WIDTH_VALUE
1814  * [31:2] | ??? | 0x0 | *UNDEFINED*
1815  *
1816  */
1817 /*
1818  * Field : value
1819  *
1820  * Controller will read Electronic Signature of devices and populate this field.
1821  * Software could also choose to override the populated value although only one
1822  * value is supported. The values in this field should be as follows[list][*]2'h00
1823  * - 8bit device[*]All other values - Reserved[/list]
1824  *
1825  * Field Access Macros:
1826  *
1827  */
1828 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field. */
1829 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_LSB 0
1830 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field. */
1831 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_MSB 1
1832 /* The width in bits of the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field. */
1833 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_WIDTH 2
1834 /* The mask used to set the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field value. */
1835 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_SET_MSK 0x00000003
1836 /* The mask used to clear the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field value. */
1837 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_CLR_MSK 0xfffffffc
1838 /* The reset value of the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field. */
1839 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_RESET 0x3
1840 /* Extracts the ALT_NAND_CFG_DEVICE_WIDTH_VALUE field value from a register. */
1841 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_GET(value) (((value) & 0x00000003) >> 0)
1842 /* Produces a ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field value suitable for setting the register. */
1843 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_SET(value) (((value) << 0) & 0x00000003)
1844 
1845 #ifndef __ASSEMBLY__
1846 /*
1847  * WARNING: The C register and register group struct declarations are provided for
1848  * convenience and illustrative purposes. They should, however, be used with
1849  * caution as the C language standard provides no guarantees about the alignment or
1850  * atomicity of device memory accesses. The recommended practice for writing
1851  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1852  * alt_write_word() functions.
1853  *
1854  * The struct declaration for register ALT_NAND_CFG_DEVICE_WIDTH.
1855  */
1856 struct ALT_NAND_CFG_DEVICE_WIDTH_s
1857 {
1858  uint32_t value : 2; /* ALT_NAND_CFG_DEVICE_WIDTH_VALUE */
1859  uint32_t : 30; /* *UNDEFINED* */
1860 };
1861 
1862 /* The typedef declaration for register ALT_NAND_CFG_DEVICE_WIDTH. */
1863 typedef volatile struct ALT_NAND_CFG_DEVICE_WIDTH_s ALT_NAND_CFG_DEVICE_WIDTH_t;
1864 #endif /* __ASSEMBLY__ */
1865 
1866 /* The byte offset of the ALT_NAND_CFG_DEVICE_WIDTH register from the beginning of the component. */
1867 #define ALT_NAND_CFG_DEVICE_WIDTH_OFST 0x160
1868 
1869 /*
1870  * Register : device_main_area_size
1871  *
1872  * Page main area size of device in bytes
1873  *
1874  * Register Layout
1875  *
1876  * Bits | Access | Reset | Description
1877  * :--------|:-------|:------|:-----------------------------------------
1878  * [15:0] | RW | 0x0 | ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE
1879  * [31:16] | ??? | 0x0 | *UNDEFINED*
1880  *
1881  */
1882 /*
1883  * Field : value
1884  *
1885  * Controller will read Electronic Signature of devices and populate this field.
1886  * The PAGE512 field of the System Manager NANDGRP_BOOTSTRAP register will
1887  * determine the value of this field to be 512. Software could also choose to
1888  * override the populated value.
1889  *
1890  * Field Access Macros:
1891  *
1892  */
1893 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field. */
1894 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_LSB 0
1895 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field. */
1896 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_MSB 15
1897 /* The width in bits of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field. */
1898 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_WIDTH 16
1899 /* The mask used to set the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field value. */
1900 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_SET_MSK 0x0000ffff
1901 /* The mask used to clear the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field value. */
1902 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_CLR_MSK 0xffff0000
1903 /* The reset value of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field. */
1904 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_RESET 0x0
1905 /* Extracts the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE field value from a register. */
1906 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
1907 /* Produces a ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field value suitable for setting the register. */
1908 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
1909 
1910 #ifndef __ASSEMBLY__
1911 /*
1912  * WARNING: The C register and register group struct declarations are provided for
1913  * convenience and illustrative purposes. They should, however, be used with
1914  * caution as the C language standard provides no guarantees about the alignment or
1915  * atomicity of device memory accesses. The recommended practice for writing
1916  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1917  * alt_write_word() functions.
1918  *
1919  * The struct declaration for register ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE.
1920  */
1921 struct ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_s
1922 {
1923  uint32_t value : 16; /* ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE */
1924  uint32_t : 16; /* *UNDEFINED* */
1925 };
1926 
1927 /* The typedef declaration for register ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE. */
1928 typedef volatile struct ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_s ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_t;
1929 #endif /* __ASSEMBLY__ */
1930 
1931 /* The byte offset of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE register from the beginning of the component. */
1932 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_OFST 0x170
1933 
1934 /*
1935  * Register : device_spare_area_size
1936  *
1937  * Page spare area size of device in bytes
1938  *
1939  * Register Layout
1940  *
1941  * Bits | Access | Reset | Description
1942  * :--------|:-------|:------|:------------------------------------------
1943  * [15:0] | RW | 0x0 | ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE
1944  * [31:16] | ??? | 0x0 | *UNDEFINED*
1945  *
1946  */
1947 /*
1948  * Field : value
1949  *
1950  * Controller will read Electronic Signature of devices and populate this field.
1951  * The PAGE512 field of the System Manager NANDGRP_BOOTSTRAP register will
1952  * determine the value of this field to be 16. Software could also choose to
1953  * override the populated value.
1954  *
1955  * Field Access Macros:
1956  *
1957  */
1958 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field. */
1959 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_LSB 0
1960 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field. */
1961 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_MSB 15
1962 /* The width in bits of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field. */
1963 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_WIDTH 16
1964 /* The mask used to set the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field value. */
1965 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_SET_MSK 0x0000ffff
1966 /* The mask used to clear the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field value. */
1967 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_CLR_MSK 0xffff0000
1968 /* The reset value of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field. */
1969 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_RESET 0x0
1970 /* Extracts the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE field value from a register. */
1971 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
1972 /* Produces a ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field value suitable for setting the register. */
1973 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
1974 
1975 #ifndef __ASSEMBLY__
1976 /*
1977  * WARNING: The C register and register group struct declarations are provided for
1978  * convenience and illustrative purposes. They should, however, be used with
1979  * caution as the C language standard provides no guarantees about the alignment or
1980  * atomicity of device memory accesses. The recommended practice for writing
1981  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1982  * alt_write_word() functions.
1983  *
1984  * The struct declaration for register ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE.
1985  */
1986 struct ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_s
1987 {
1988  uint32_t value : 16; /* ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE */
1989  uint32_t : 16; /* *UNDEFINED* */
1990 };
1991 
1992 /* The typedef declaration for register ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE. */
1993 typedef volatile struct ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_s ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_t;
1994 #endif /* __ASSEMBLY__ */
1995 
1996 /* The byte offset of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE register from the beginning of the component. */
1997 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_OFST 0x180
1998 
1999 /*
2000  * Register : two_row_addr_cycles
2001  *
2002  * Attached device has only 2 ROW address cycles
2003  *
2004  * Register Layout
2005  *
2006  * Bits | Access | Reset | Description
2007  * :-------|:-------|:------|:--------------------------------------
2008  * [0] | RW | 0x0 | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG
2009  * [31:1] | ??? | 0x0 | *UNDEFINED*
2010  *
2011  */
2012 /*
2013  * Field : flag
2014  *
2015  * This flag must be set for devices which allow for 2 ROW address cycles instead
2016  * of the usual 3. Alternatively, the TWOROWADDR field of the System Manager
2017  * NANDGRP_BOOTSTRAP register when asserted will set this flag.
2018  *
2019  * Field Access Macros:
2020  *
2021  */
2022 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field. */
2023 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_LSB 0
2024 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field. */
2025 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_MSB 0
2026 /* The width in bits of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field. */
2027 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_WIDTH 1
2028 /* The mask used to set the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field value. */
2029 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_SET_MSK 0x00000001
2030 /* The mask used to clear the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field value. */
2031 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_CLR_MSK 0xfffffffe
2032 /* The reset value of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field. */
2033 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_RESET 0x0
2034 /* Extracts the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG field value from a register. */
2035 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_GET(value) (((value) & 0x00000001) >> 0)
2036 /* Produces a ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field value suitable for setting the register. */
2037 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_SET(value) (((value) << 0) & 0x00000001)
2038 
2039 #ifndef __ASSEMBLY__
2040 /*
2041  * WARNING: The C register and register group struct declarations are provided for
2042  * convenience and illustrative purposes. They should, however, be used with
2043  * caution as the C language standard provides no guarantees about the alignment or
2044  * atomicity of device memory accesses. The recommended practice for writing
2045  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2046  * alt_write_word() functions.
2047  *
2048  * The struct declaration for register ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES.
2049  */
2050 struct ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_s
2051 {
2052  uint32_t flag : 1; /* ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG */
2053  uint32_t : 31; /* *UNDEFINED* */
2054 };
2055 
2056 /* The typedef declaration for register ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES. */
2057 typedef volatile struct ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_s ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_t;
2058 #endif /* __ASSEMBLY__ */
2059 
2060 /* The byte offset of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES register from the beginning of the component. */
2061 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_OFST 0x190
2062 
2063 /*
2064  * Register : multiplane_addr_restrict
2065  *
2066  * Address restriction for multiplane commands
2067  *
2068  * Register Layout
2069  *
2070  * Bits | Access | Reset | Description
2071  * :-------|:-------|:------|:-------------------------------------------
2072  * [0] | RW | 0x0 | ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG
2073  * [31:1] | ??? | 0x0 | *UNDEFINED*
2074  *
2075  */
2076 /*
2077  * Field : flag
2078  *
2079  * This flag must be set for devices which require that during multiplane
2080  * operations all but the address for the last plane should have their address
2081  * cycles tied low. The last plane address cycles has proper values. This ensures
2082  * multiplane address restrictions in the device.
2083  *
2084  * Field Access Macros:
2085  *
2086  */
2087 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field. */
2088 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_LSB 0
2089 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field. */
2090 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_MSB 0
2091 /* The width in bits of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field. */
2092 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_WIDTH 1
2093 /* The mask used to set the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field value. */
2094 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_SET_MSK 0x00000001
2095 /* The mask used to clear the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field value. */
2096 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_CLR_MSK 0xfffffffe
2097 /* The reset value of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field. */
2098 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_RESET 0x0
2099 /* Extracts the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG field value from a register. */
2100 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_GET(value) (((value) & 0x00000001) >> 0)
2101 /* Produces a ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field value suitable for setting the register. */
2102 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_SET(value) (((value) << 0) & 0x00000001)
2103 
2104 #ifndef __ASSEMBLY__
2105 /*
2106  * WARNING: The C register and register group struct declarations are provided for
2107  * convenience and illustrative purposes. They should, however, be used with
2108  * caution as the C language standard provides no guarantees about the alignment or
2109  * atomicity of device memory accesses. The recommended practice for writing
2110  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2111  * alt_write_word() functions.
2112  *
2113  * The struct declaration for register ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT.
2114  */
2115 struct ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_s
2116 {
2117  uint32_t flag : 1; /* ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG */
2118  uint32_t : 31; /* *UNDEFINED* */
2119 };
2120 
2121 /* The typedef declaration for register ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT. */
2122 typedef volatile struct ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_s ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_t;
2123 #endif /* __ASSEMBLY__ */
2124 
2125 /* The byte offset of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT register from the beginning of the component. */
2126 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_OFST 0x1a0
2127 
2128 /*
2129  * Register : ecc_correction
2130  *
2131  * Correction capability required
2132  *
2133  * Register Layout
2134  *
2135  * Bits | Access | Reset | Description
2136  * :-------|:-------|:------|:----------------------------------
2137  * [7:0] | RW | 0x8 | ALT_NAND_CFG_ECC_CORRECTION_VALUE
2138  * [31:8] | ??? | 0x0 | *UNDEFINED*
2139  *
2140  */
2141 /*
2142  * Field : value
2143  *
2144  * The required correction capability can be a number less than the configured
2145  * error correction capability. A smaller correction capability will lead to lesser
2146  * number of ECC check-bits being written per ECC sector.
2147  *
2148  * Field Access Macros:
2149  *
2150  */
2151 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field. */
2152 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_LSB 0
2153 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field. */
2154 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_MSB 7
2155 /* The width in bits of the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field. */
2156 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_WIDTH 8
2157 /* The mask used to set the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field value. */
2158 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_SET_MSK 0x000000ff
2159 /* The mask used to clear the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field value. */
2160 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_CLR_MSK 0xffffff00
2161 /* The reset value of the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field. */
2162 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_RESET 0x8
2163 /* Extracts the ALT_NAND_CFG_ECC_CORRECTION_VALUE field value from a register. */
2164 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
2165 /* Produces a ALT_NAND_CFG_ECC_CORRECTION_VALUE register field value suitable for setting the register. */
2166 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_SET(value) (((value) << 0) & 0x000000ff)
2167 
2168 #ifndef __ASSEMBLY__
2169 /*
2170  * WARNING: The C register and register group struct declarations are provided for
2171  * convenience and illustrative purposes. They should, however, be used with
2172  * caution as the C language standard provides no guarantees about the alignment or
2173  * atomicity of device memory accesses. The recommended practice for writing
2174  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2175  * alt_write_word() functions.
2176  *
2177  * The struct declaration for register ALT_NAND_CFG_ECC_CORRECTION.
2178  */
2179 struct ALT_NAND_CFG_ECC_CORRECTION_s
2180 {
2181  uint32_t value : 8; /* ALT_NAND_CFG_ECC_CORRECTION_VALUE */
2182  uint32_t : 24; /* *UNDEFINED* */
2183 };
2184 
2185 /* The typedef declaration for register ALT_NAND_CFG_ECC_CORRECTION. */
2186 typedef volatile struct ALT_NAND_CFG_ECC_CORRECTION_s ALT_NAND_CFG_ECC_CORRECTION_t;
2187 #endif /* __ASSEMBLY__ */
2188 
2189 /* The byte offset of the ALT_NAND_CFG_ECC_CORRECTION register from the beginning of the component. */
2190 #define ALT_NAND_CFG_ECC_CORRECTION_OFST 0x1b0
2191 
2192 /*
2193  * Register : read_mode
2194  *
2195  * The type of read sequence that the controller will follow for pipe read
2196  * commands.
2197  *
2198  * Register Layout
2199  *
2200  * Bits | Access | Reset | Description
2201  * :-------|:-------|:------|:--------------------------
2202  * [3:0] | RW | 0x0 | ALT_NAND_CFG_RD_MOD_VALUE
2203  * [31:4] | ??? | 0x0 | *UNDEFINED*
2204  *
2205  */
2206 /*
2207  * Field : value
2208  *
2209  * The values in the field should be as follows[list] [*]4'h0 - This value informs
2210  * the controller that the pipe read sequence to follow is of a normal read. For
2211  * 512 byte page devices, Normal read sequence is, C00, Address, Data, ..... For
2212  * devices with page size greater that 512 bytes, the sequence is, C00, Address,
2213  * C30, Data..... [*]4'h1 - This value informs the controller that the pipe read
2214  * sequence to follow is of a Cache Read with the following sequence, C00, Address,
2215  * C30, C31, Data, C31, Data, ....., C3F, Data. [*]4'h2 - This value informs the
2216  * controller that the pipe read sequence to follow is of a Cache Read with the
2217  * following sequence, C00, Address, C31, Data, Data, ....., C34. [*]4'h3 - This
2218  * value informs the controller that the pipe read sequence to follow is of a 'N'
2219  * Plane Read with the following sequence, C00, Address, C00, Address, C30, Data,
2220  * C06, Address, CE0, Data..... [*]4'h4 - This value informs the controller that
2221  * the pipe read sequence to follow is of a 'N' Plane Read with the following
2222  * sequence, C60, Address, C60, Address, C30, C00, Address, C05, Address, CE0,
2223  * Data, C00, Address, C05, Address, CE0, Data..... [*]4'h5 - This value informs
2224  * the controller that the pipe read sequence to follow is of a 'N' Plane Cache
2225  * Read with the following sequence, C60, Address, C60, Address, C30, C31, C00,
2226  * Address, C05, Address, CE0, Data, C00, Address, C05, Address, CE0, Data, .....,
2227  * C3F, C00, Address, C05, Address, CE0, Data, C00, Address, C05, Address, CE0,
2228  * Data [*]4'h6 - This value informs the controller that the pipe read sequence to
2229  * follow is of a 'N' Plane Read with the following sequence, C00, Address, C32,
2230  * .., C00, Address, C30, C06, Address, CE0, Data, C06, Address, CE0, Data,....
2231  * [*]4'h7 - This value informs the controller that the pipe read sequence to
2232  * follow is of a 'N' Plane Cache Read with the following sequence, C00, Address,
2233  * C32,..., C00, Address, C30, C31,C06, Address, CE0, Data, C31, C06, Address, CE0,
2234  * Data, C3F, C06, Address, CE0, Data.... [*]4'h8 - This value informs the
2235  * controller that the pipe read sequence to follow is of a 'N' Plane Cache Read
2236  * with the following sequence, C60, Address, C60, Address, C33, C31, C00, Address,
2237  * C05, Address, CE0, Data, C00, Address, C05, Address, CE0, Data, ....., C3F, C00,
2238  * Address, C05, Address, CE0, Data, C00, Address, C05, Address, CE0, Data [*]4'h9
2239  * - 4'h15 - Reserved. [/list] ..... indicates that the previous sequence is
2240  * repeated till the last page.
2241  *
2242  * Field Access Macros:
2243  *
2244  */
2245 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RD_MOD_VALUE register field. */
2246 #define ALT_NAND_CFG_RD_MOD_VALUE_LSB 0
2247 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RD_MOD_VALUE register field. */
2248 #define ALT_NAND_CFG_RD_MOD_VALUE_MSB 3
2249 /* The width in bits of the ALT_NAND_CFG_RD_MOD_VALUE register field. */
2250 #define ALT_NAND_CFG_RD_MOD_VALUE_WIDTH 4
2251 /* The mask used to set the ALT_NAND_CFG_RD_MOD_VALUE register field value. */
2252 #define ALT_NAND_CFG_RD_MOD_VALUE_SET_MSK 0x0000000f
2253 /* The mask used to clear the ALT_NAND_CFG_RD_MOD_VALUE register field value. */
2254 #define ALT_NAND_CFG_RD_MOD_VALUE_CLR_MSK 0xfffffff0
2255 /* The reset value of the ALT_NAND_CFG_RD_MOD_VALUE register field. */
2256 #define ALT_NAND_CFG_RD_MOD_VALUE_RESET 0x0
2257 /* Extracts the ALT_NAND_CFG_RD_MOD_VALUE field value from a register. */
2258 #define ALT_NAND_CFG_RD_MOD_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2259 /* Produces a ALT_NAND_CFG_RD_MOD_VALUE register field value suitable for setting the register. */
2260 #define ALT_NAND_CFG_RD_MOD_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2261 
2262 #ifndef __ASSEMBLY__
2263 /*
2264  * WARNING: The C register and register group struct declarations are provided for
2265  * convenience and illustrative purposes. They should, however, be used with
2266  * caution as the C language standard provides no guarantees about the alignment or
2267  * atomicity of device memory accesses. The recommended practice for writing
2268  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2269  * alt_write_word() functions.
2270  *
2271  * The struct declaration for register ALT_NAND_CFG_RD_MOD.
2272  */
2273 struct ALT_NAND_CFG_RD_MOD_s
2274 {
2275  uint32_t value : 4; /* ALT_NAND_CFG_RD_MOD_VALUE */
2276  uint32_t : 28; /* *UNDEFINED* */
2277 };
2278 
2279 /* The typedef declaration for register ALT_NAND_CFG_RD_MOD. */
2280 typedef volatile struct ALT_NAND_CFG_RD_MOD_s ALT_NAND_CFG_RD_MOD_t;
2281 #endif /* __ASSEMBLY__ */
2282 
2283 /* The byte offset of the ALT_NAND_CFG_RD_MOD register from the beginning of the component. */
2284 #define ALT_NAND_CFG_RD_MOD_OFST 0x1c0
2285 
2286 /*
2287  * Register : write_mode
2288  *
2289  * The type of write sequence that the controller will follow for pipe write
2290  * commands.
2291  *
2292  * Register Layout
2293  *
2294  * Bits | Access | Reset | Description
2295  * :-------|:-------|:------|:--------------------------
2296  * [3:0] | RW | 0x0 | ALT_NAND_CFG_WR_MOD_VALUE
2297  * [31:4] | ??? | 0x0 | *UNDEFINED*
2298  *
2299  */
2300 /*
2301  * Field : value
2302  *
2303  * The values in the field should be as follows[list] [*]4'h0 - This value informs
2304  * the controller that the pipe write sequence to follow is of a normal write with
2305  * the following sequence, C80, Address, Data, C10..... [*]4'h1 - This value
2306  * informs the controller that the pipe write sequence to follow is of a Cache
2307  * Program with the following sequence, C80, Address, Data, C15, ....., C80,
2308  * Address, Data, C10. [*]4'h2 - This value informs the controller that the pipe
2309  * write sequence to follow is of a Two/Four Plane Program with the following
2310  * sequence, C80, Address, Data, C11, C81, Address, Data, C10..... [*]4'h3 - This
2311  * value informs the controller that the pipe write sequence to follow is of a 'N'
2312  * Plane Program with the following sequence, C80, Address, Data, C11, C80,
2313  * Address, Data, C10..... [*]4'h4 - This value informs the controller that the
2314  * pipe write sequence to follow is of a 'N' Plane Cache Program with the following
2315  * sequence, C80, Address, Data, C11, C80, Address, Data, C15.....C80, Address,
2316  * Data, C11, C80, Address, Data, C10. [*]4'h5 - This value informs the controller
2317  * that the pipe write sequence to follow is of a 'N' Plane Cache Program with the
2318  * following sequence, C80, Address, Data, C11, C81, Address, Data, C15.....C80,
2319  * Address, Data, C11, C81, Address, Data, C10. [*]4'h6 - 4'h15 - Reserved. [/list]
2320  * ..... indicates that the previous sequence is repeated till the last page.
2321  *
2322  * Field Access Macros:
2323  *
2324  */
2325 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_WR_MOD_VALUE register field. */
2326 #define ALT_NAND_CFG_WR_MOD_VALUE_LSB 0
2327 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_WR_MOD_VALUE register field. */
2328 #define ALT_NAND_CFG_WR_MOD_VALUE_MSB 3
2329 /* The width in bits of the ALT_NAND_CFG_WR_MOD_VALUE register field. */
2330 #define ALT_NAND_CFG_WR_MOD_VALUE_WIDTH 4
2331 /* The mask used to set the ALT_NAND_CFG_WR_MOD_VALUE register field value. */
2332 #define ALT_NAND_CFG_WR_MOD_VALUE_SET_MSK 0x0000000f
2333 /* The mask used to clear the ALT_NAND_CFG_WR_MOD_VALUE register field value. */
2334 #define ALT_NAND_CFG_WR_MOD_VALUE_CLR_MSK 0xfffffff0
2335 /* The reset value of the ALT_NAND_CFG_WR_MOD_VALUE register field. */
2336 #define ALT_NAND_CFG_WR_MOD_VALUE_RESET 0x0
2337 /* Extracts the ALT_NAND_CFG_WR_MOD_VALUE field value from a register. */
2338 #define ALT_NAND_CFG_WR_MOD_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2339 /* Produces a ALT_NAND_CFG_WR_MOD_VALUE register field value suitable for setting the register. */
2340 #define ALT_NAND_CFG_WR_MOD_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2341 
2342 #ifndef __ASSEMBLY__
2343 /*
2344  * WARNING: The C register and register group struct declarations are provided for
2345  * convenience and illustrative purposes. They should, however, be used with
2346  * caution as the C language standard provides no guarantees about the alignment or
2347  * atomicity of device memory accesses. The recommended practice for writing
2348  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2349  * alt_write_word() functions.
2350  *
2351  * The struct declaration for register ALT_NAND_CFG_WR_MOD.
2352  */
2353 struct ALT_NAND_CFG_WR_MOD_s
2354 {
2355  uint32_t value : 4; /* ALT_NAND_CFG_WR_MOD_VALUE */
2356  uint32_t : 28; /* *UNDEFINED* */
2357 };
2358 
2359 /* The typedef declaration for register ALT_NAND_CFG_WR_MOD. */
2360 typedef volatile struct ALT_NAND_CFG_WR_MOD_s ALT_NAND_CFG_WR_MOD_t;
2361 #endif /* __ASSEMBLY__ */
2362 
2363 /* The byte offset of the ALT_NAND_CFG_WR_MOD register from the beginning of the component. */
2364 #define ALT_NAND_CFG_WR_MOD_OFST 0x1d0
2365 
2366 /*
2367  * Register : copyback_mode
2368  *
2369  * The type of copyback sequence that the controller will follow.
2370  *
2371  * Register Layout
2372  *
2373  * Bits | Access | Reset | Description
2374  * :-------|:-------|:------|:--------------------------------
2375  * [3:0] | RW | 0x0 | ALT_NAND_CFG_COPYBACK_MOD_VALUE
2376  * [31:4] | ??? | 0x0 | *UNDEFINED*
2377  *
2378  */
2379 /*
2380  * Field : value
2381  *
2382  * The values in the field should be as follows[list] [*]4'h0 - This value informs
2383  * the controller that the copyback sequence to follow is, C00, Address, C35, C85,
2384  * Address, C10 [*]4'h1 - This value informs the controller that the copyback
2385  * sequence to follow is, C00, Address, C30, C8C, Address, C10 [*]4'h2 - This value
2386  * informs the controller that the copyback sequence to follow is, C00, Address,
2387  * C8A, Address, C10 [*]4'h3 - This value informs the controller that the copyback
2388  * sequence to follow is of a four plane copyback sequence, C00, Address, C03,
2389  * Address, C03, Address, C03, Address, C8A, Address, C11, C8A, Address, C11, C8A,
2390  * Address, C11, C8A, Address, C10. [*]4'h4 - This value informs the controller
2391  * that the copyback sequence to follow is of a two plane copyback sequence, C00,
2392  * Address, C35, C00, Address, C35, C85, Address, C11, C81, Address, C10. [*]4'h5 -
2393  * This value informs the controller that the copyback sequence to follow is of a
2394  * two plane copyback sequence, C60, Address, C60, Address, C35, C85, Address, C11,
2395  * C81, Address, C10. [*]4'h6 - This value informs the controller that the copyback
2396  * sequence to follow is of a two plane copyback sequence, C00, Address, C00,
2397  * Address, C35, C85, Address, C11, C80, Address, C10. [*]4'h7 - This value informs
2398  * the controller that the copyback sequence to follow is of a two plane copyback
2399  * sequence, C60, Address, C60, Address, C30, C8C, Address, C11, C8C, Address, C10.
2400  * [*]4'h8 - 4'h15 - Reserved.[/list]
2401  *
2402  * Field Access Macros:
2403  *
2404  */
2405 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_COPYBACK_MOD_VALUE register field. */
2406 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_LSB 0
2407 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_COPYBACK_MOD_VALUE register field. */
2408 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_MSB 3
2409 /* The width in bits of the ALT_NAND_CFG_COPYBACK_MOD_VALUE register field. */
2410 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_WIDTH 4
2411 /* The mask used to set the ALT_NAND_CFG_COPYBACK_MOD_VALUE register field value. */
2412 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_SET_MSK 0x0000000f
2413 /* The mask used to clear the ALT_NAND_CFG_COPYBACK_MOD_VALUE register field value. */
2414 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_CLR_MSK 0xfffffff0
2415 /* The reset value of the ALT_NAND_CFG_COPYBACK_MOD_VALUE register field. */
2416 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_RESET 0x0
2417 /* Extracts the ALT_NAND_CFG_COPYBACK_MOD_VALUE field value from a register. */
2418 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2419 /* Produces a ALT_NAND_CFG_COPYBACK_MOD_VALUE register field value suitable for setting the register. */
2420 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2421 
2422 #ifndef __ASSEMBLY__
2423 /*
2424  * WARNING: The C register and register group struct declarations are provided for
2425  * convenience and illustrative purposes. They should, however, be used with
2426  * caution as the C language standard provides no guarantees about the alignment or
2427  * atomicity of device memory accesses. The recommended practice for writing
2428  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2429  * alt_write_word() functions.
2430  *
2431  * The struct declaration for register ALT_NAND_CFG_COPYBACK_MOD.
2432  */
2433 struct ALT_NAND_CFG_COPYBACK_MOD_s
2434 {
2435  uint32_t value : 4; /* ALT_NAND_CFG_COPYBACK_MOD_VALUE */
2436  uint32_t : 28; /* *UNDEFINED* */
2437 };
2438 
2439 /* The typedef declaration for register ALT_NAND_CFG_COPYBACK_MOD. */
2440 typedef volatile struct ALT_NAND_CFG_COPYBACK_MOD_s ALT_NAND_CFG_COPYBACK_MOD_t;
2441 #endif /* __ASSEMBLY__ */
2442 
2443 /* The byte offset of the ALT_NAND_CFG_COPYBACK_MOD register from the beginning of the component. */
2444 #define ALT_NAND_CFG_COPYBACK_MOD_OFST 0x1e0
2445 
2446 /*
2447  * Register : rdwr_en_lo_cnt
2448  *
2449  * Read/Write Enable low pulse width
2450  *
2451  * Register Layout
2452  *
2453  * Bits | Access | Reset | Description
2454  * :-------|:-------|:------|:----------------------------------
2455  * [4:0] | RW | 0x12 | ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE
2456  * [31:5] | ??? | 0x0 | *UNDEFINED*
2457  *
2458  */
2459 /*
2460  * Field : value
2461  *
2462  * Number of nand_mp_clk cycles that read or write enable will kept low to meet the
2463  * min Trp/Twp parameter of the device. The value in this register plus
2464  * rdwr_en_hi_cnt register value should meet the min cycle time of the device
2465  * connected. The default value is calculated assuming the max nand_mp_clk time
2466  * period of 4ns to work with ONFI Mode 0 mode of 100ns device cycle time. This
2467  * assumes a 1x/4x clocking scheme.
2468  *
2469  * Field Access Macros:
2470  *
2471  */
2472 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field. */
2473 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_LSB 0
2474 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field. */
2475 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_MSB 4
2476 /* The width in bits of the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field. */
2477 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_WIDTH 5
2478 /* The mask used to set the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field value. */
2479 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_SET_MSK 0x0000001f
2480 /* The mask used to clear the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field value. */
2481 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_CLR_MSK 0xffffffe0
2482 /* The reset value of the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field. */
2483 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_RESET 0x12
2484 /* Extracts the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE field value from a register. */
2485 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
2486 /* Produces a ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field value suitable for setting the register. */
2487 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
2488 
2489 #ifndef __ASSEMBLY__
2490 /*
2491  * WARNING: The C register and register group struct declarations are provided for
2492  * convenience and illustrative purposes. They should, however, be used with
2493  * caution as the C language standard provides no guarantees about the alignment or
2494  * atomicity of device memory accesses. The recommended practice for writing
2495  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2496  * alt_write_word() functions.
2497  *
2498  * The struct declaration for register ALT_NAND_CFG_RDWR_EN_LO_CNT.
2499  */
2500 struct ALT_NAND_CFG_RDWR_EN_LO_CNT_s
2501 {
2502  uint32_t value : 5; /* ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE */
2503  uint32_t : 27; /* *UNDEFINED* */
2504 };
2505 
2506 /* The typedef declaration for register ALT_NAND_CFG_RDWR_EN_LO_CNT. */
2507 typedef volatile struct ALT_NAND_CFG_RDWR_EN_LO_CNT_s ALT_NAND_CFG_RDWR_EN_LO_CNT_t;
2508 #endif /* __ASSEMBLY__ */
2509 
2510 /* The byte offset of the ALT_NAND_CFG_RDWR_EN_LO_CNT register from the beginning of the component. */
2511 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_OFST 0x1f0
2512 
2513 /*
2514  * Register : rdwr_en_hi_cnt
2515  *
2516  * Read/Write Enable high pulse width
2517  *
2518  * Register Layout
2519  *
2520  * Bits | Access | Reset | Description
2521  * :-------|:-------|:------|:----------------------------------
2522  * [4:0] | RW | 0xc | ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE
2523  * [31:5] | ??? | 0x0 | *UNDEFINED*
2524  *
2525  */
2526 /*
2527  * Field : value
2528  *
2529  * Number of nand_mp_clk cycles that read or write enable will kept high to meet
2530  * the min Treh/Tweh parameter of the device. The value in this register plus
2531  * rdwr_en_lo_cnt register value should meet the min cycle time of the device
2532  * connected. The default value is calculated assuming the max nand_mp_clk time
2533  * period of 4ns to work with ONFI Mode 0 mode of 100ns device cycle time. This
2534  * assumes a 1x/4x clocking scheme.
2535  *
2536  * Field Access Macros:
2537  *
2538  */
2539 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field. */
2540 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_LSB 0
2541 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field. */
2542 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_MSB 4
2543 /* The width in bits of the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field. */
2544 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_WIDTH 5
2545 /* The mask used to set the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field value. */
2546 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_SET_MSK 0x0000001f
2547 /* The mask used to clear the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field value. */
2548 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_CLR_MSK 0xffffffe0
2549 /* The reset value of the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field. */
2550 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_RESET 0xc
2551 /* Extracts the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE field value from a register. */
2552 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
2553 /* Produces a ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field value suitable for setting the register. */
2554 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
2555 
2556 #ifndef __ASSEMBLY__
2557 /*
2558  * WARNING: The C register and register group struct declarations are provided for
2559  * convenience and illustrative purposes. They should, however, be used with
2560  * caution as the C language standard provides no guarantees about the alignment or
2561  * atomicity of device memory accesses. The recommended practice for writing
2562  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2563  * alt_write_word() functions.
2564  *
2565  * The struct declaration for register ALT_NAND_CFG_RDWR_EN_HI_CNT.
2566  */
2567 struct ALT_NAND_CFG_RDWR_EN_HI_CNT_s
2568 {
2569  uint32_t value : 5; /* ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE */
2570  uint32_t : 27; /* *UNDEFINED* */
2571 };
2572 
2573 /* The typedef declaration for register ALT_NAND_CFG_RDWR_EN_HI_CNT. */
2574 typedef volatile struct ALT_NAND_CFG_RDWR_EN_HI_CNT_s ALT_NAND_CFG_RDWR_EN_HI_CNT_t;
2575 #endif /* __ASSEMBLY__ */
2576 
2577 /* The byte offset of the ALT_NAND_CFG_RDWR_EN_HI_CNT register from the beginning of the component. */
2578 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_OFST 0x200
2579 
2580 /*
2581  * Register : max_rd_delay
2582  *
2583  * Max round trip read data delay for data capture
2584  *
2585  * Register Layout
2586  *
2587  * Bits | Access | Reset | Description
2588  * :-------|:-------|:------|:--------------------------------
2589  * [3:0] | RW | 0x0 | ALT_NAND_CFG_MAX_RD_DELAY_VALUE
2590  * [31:4] | ??? | 0x0 | *UNDEFINED*
2591  *
2592  */
2593 /*
2594  * Field : value
2595  *
2596  * Number of nand_mp_clk cycles after generation of feedback nand_mp_clk pulse when
2597  * it is safe to synchronize received data to nand_mp_clk domain. Data should have
2598  * been registered with nand_mp_clk and stable by the time max_rd_delay cycles has
2599  * elapsed. A default value of zero will mean a value of nand_mp_clk multiple minus
2600  * one.
2601  *
2602  * Field Access Macros:
2603  *
2604  */
2605 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field. */
2606 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_LSB 0
2607 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field. */
2608 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_MSB 3
2609 /* The width in bits of the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field. */
2610 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_WIDTH 4
2611 /* The mask used to set the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field value. */
2612 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_SET_MSK 0x0000000f
2613 /* The mask used to clear the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field value. */
2614 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_CLR_MSK 0xfffffff0
2615 /* The reset value of the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field. */
2616 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_RESET 0x0
2617 /* Extracts the ALT_NAND_CFG_MAX_RD_DELAY_VALUE field value from a register. */
2618 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2619 /* Produces a ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field value suitable for setting the register. */
2620 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2621 
2622 #ifndef __ASSEMBLY__
2623 /*
2624  * WARNING: The C register and register group struct declarations are provided for
2625  * convenience and illustrative purposes. They should, however, be used with
2626  * caution as the C language standard provides no guarantees about the alignment or
2627  * atomicity of device memory accesses. The recommended practice for writing
2628  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2629  * alt_write_word() functions.
2630  *
2631  * The struct declaration for register ALT_NAND_CFG_MAX_RD_DELAY.
2632  */
2633 struct ALT_NAND_CFG_MAX_RD_DELAY_s
2634 {
2635  uint32_t value : 4; /* ALT_NAND_CFG_MAX_RD_DELAY_VALUE */
2636  uint32_t : 28; /* *UNDEFINED* */
2637 };
2638 
2639 /* The typedef declaration for register ALT_NAND_CFG_MAX_RD_DELAY. */
2640 typedef volatile struct ALT_NAND_CFG_MAX_RD_DELAY_s ALT_NAND_CFG_MAX_RD_DELAY_t;
2641 #endif /* __ASSEMBLY__ */
2642 
2643 /* The byte offset of the ALT_NAND_CFG_MAX_RD_DELAY register from the beginning of the component. */
2644 #define ALT_NAND_CFG_MAX_RD_DELAY_OFST 0x210
2645 
2646 /*
2647  * Register : cs_setup_cnt
2648  *
2649  * Chip select setup time
2650  *
2651  * Register Layout
2652  *
2653  * Bits | Access | Reset | Description
2654  * :-------|:-------|:------|:--------------------------------
2655  * [4:0] | RW | 0x3 | ALT_NAND_CFG_CS_SETUP_CNT_VALUE
2656  * [31:5] | ??? | 0x0 | *UNDEFINED*
2657  *
2658  */
2659 /*
2660  * Field : value
2661  *
2662  * Number of nand_mp_clk cycles required for meeting chip select setup time. This
2663  * register refers to device timing parameter Tcs. The value in this registers
2664  * reflects the extra setup cycles for chip select before read/write enable signal
2665  * is set low. The default value is calculated for ONFI Timing mode 0 Tcs = 70ns
2666  * and maximum nand_mp_clk period of 4ns for 1x/4x clock multiple for 16ns cycle
2667  * time device. Please refer to Figure 3.3 for the relationship between the
2668  * cs_setup_cnt and rdwr_en_lo_cnt values.
2669  *
2670  * Field Access Macros:
2671  *
2672  */
2673 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field. */
2674 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_LSB 0
2675 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field. */
2676 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_MSB 4
2677 /* The width in bits of the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field. */
2678 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_WIDTH 5
2679 /* The mask used to set the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field value. */
2680 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_SET_MSK 0x0000001f
2681 /* The mask used to clear the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field value. */
2682 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_CLR_MSK 0xffffffe0
2683 /* The reset value of the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field. */
2684 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_RESET 0x3
2685 /* Extracts the ALT_NAND_CFG_CS_SETUP_CNT_VALUE field value from a register. */
2686 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
2687 /* Produces a ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field value suitable for setting the register. */
2688 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
2689 
2690 #ifndef __ASSEMBLY__
2691 /*
2692  * WARNING: The C register and register group struct declarations are provided for
2693  * convenience and illustrative purposes. They should, however, be used with
2694  * caution as the C language standard provides no guarantees about the alignment or
2695  * atomicity of device memory accesses. The recommended practice for writing
2696  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2697  * alt_write_word() functions.
2698  *
2699  * The struct declaration for register ALT_NAND_CFG_CS_SETUP_CNT.
2700  */
2701 struct ALT_NAND_CFG_CS_SETUP_CNT_s
2702 {
2703  uint32_t value : 5; /* ALT_NAND_CFG_CS_SETUP_CNT_VALUE */
2704  uint32_t : 27; /* *UNDEFINED* */
2705 };
2706 
2707 /* The typedef declaration for register ALT_NAND_CFG_CS_SETUP_CNT. */
2708 typedef volatile struct ALT_NAND_CFG_CS_SETUP_CNT_s ALT_NAND_CFG_CS_SETUP_CNT_t;
2709 #endif /* __ASSEMBLY__ */
2710 
2711 /* The byte offset of the ALT_NAND_CFG_CS_SETUP_CNT register from the beginning of the component. */
2712 #define ALT_NAND_CFG_CS_SETUP_CNT_OFST 0x220
2713 
2714 /*
2715  * Register : spare_area_skip_bytes
2716  *
2717  * Spare area skip bytes
2718  *
2719  * Register Layout
2720  *
2721  * Bits | Access | Reset | Description
2722  * :-------|:-------|:------|:-----------------------------------------
2723  * [5:0] | RW | 0x0 | ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE
2724  * [31:6] | ??? | 0x0 | *UNDEFINED*
2725  *
2726  */
2727 /*
2728  * Field : value
2729  *
2730  * Number of bytes to skip from start of spare area before last ECC sector data
2731  * starts. The bytes will be written with the value programmed in the
2732  * spare_area_marker register. This register could be potentially used to preserve
2733  * the bad block marker in the spare area by marking it good. The default value is
2734  * zero which means no bytes will be skipped and last ECC sector will start from
2735  * the beginning of spare area.
2736  *
2737  * Field Access Macros:
2738  *
2739  */
2740 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field. */
2741 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_LSB 0
2742 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field. */
2743 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_MSB 5
2744 /* The width in bits of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field. */
2745 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_WIDTH 6
2746 /* The mask used to set the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field value. */
2747 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_SET_MSK 0x0000003f
2748 /* The mask used to clear the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field value. */
2749 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_CLR_MSK 0xffffffc0
2750 /* The reset value of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field. */
2751 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_RESET 0x0
2752 /* Extracts the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE field value from a register. */
2753 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
2754 /* Produces a ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field value suitable for setting the register. */
2755 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_SET(value) (((value) << 0) & 0x0000003f)
2756 
2757 #ifndef __ASSEMBLY__
2758 /*
2759  * WARNING: The C register and register group struct declarations are provided for
2760  * convenience and illustrative purposes. They should, however, be used with
2761  * caution as the C language standard provides no guarantees about the alignment or
2762  * atomicity of device memory accesses. The recommended practice for writing
2763  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2764  * alt_write_word() functions.
2765  *
2766  * The struct declaration for register ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES.
2767  */
2768 struct ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_s
2769 {
2770  uint32_t value : 6; /* ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE */
2771  uint32_t : 26; /* *UNDEFINED* */
2772 };
2773 
2774 /* The typedef declaration for register ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES. */
2775 typedef volatile struct ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_s ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_t;
2776 #endif /* __ASSEMBLY__ */
2777 
2778 /* The byte offset of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES register from the beginning of the component. */
2779 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_OFST 0x230
2780 
2781 /*
2782  * Register : spare_area_marker
2783  *
2784  * Spare area marker value
2785  *
2786  * Register Layout
2787  *
2788  * Bits | Access | Reset | Description
2789  * :--------|:-------|:-------|:-------------------------------------
2790  * [15:0] | RW | 0xffff | ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE
2791  * [31:16] | ??? | 0x0 | *UNDEFINED*
2792  *
2793  */
2794 /*
2795  * Field : value
2796  *
2797  * The value that will be written in the spare area skip bytes. This value will be
2798  * used by controller while in the MAIN mode of data transfer. Only the least-
2799  * significant 8 bits of the field value are used.
2800  *
2801  * Field Access Macros:
2802  *
2803  */
2804 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field. */
2805 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_LSB 0
2806 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field. */
2807 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_MSB 15
2808 /* The width in bits of the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field. */
2809 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_WIDTH 16
2810 /* The mask used to set the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field value. */
2811 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_SET_MSK 0x0000ffff
2812 /* The mask used to clear the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field value. */
2813 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_CLR_MSK 0xffff0000
2814 /* The reset value of the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field. */
2815 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_RESET 0xffff
2816 /* Extracts the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE field value from a register. */
2817 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
2818 /* Produces a ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field value suitable for setting the register. */
2819 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
2820 
2821 #ifndef __ASSEMBLY__
2822 /*
2823  * WARNING: The C register and register group struct declarations are provided for
2824  * convenience and illustrative purposes. They should, however, be used with
2825  * caution as the C language standard provides no guarantees about the alignment or
2826  * atomicity of device memory accesses. The recommended practice for writing
2827  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2828  * alt_write_word() functions.
2829  *
2830  * The struct declaration for register ALT_NAND_CFG_SPARE_AREA_MARKER.
2831  */
2832 struct ALT_NAND_CFG_SPARE_AREA_MARKER_s
2833 {
2834  uint32_t value : 16; /* ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE */
2835  uint32_t : 16; /* *UNDEFINED* */
2836 };
2837 
2838 /* The typedef declaration for register ALT_NAND_CFG_SPARE_AREA_MARKER. */
2839 typedef volatile struct ALT_NAND_CFG_SPARE_AREA_MARKER_s ALT_NAND_CFG_SPARE_AREA_MARKER_t;
2840 #endif /* __ASSEMBLY__ */
2841 
2842 /* The byte offset of the ALT_NAND_CFG_SPARE_AREA_MARKER register from the beginning of the component. */
2843 #define ALT_NAND_CFG_SPARE_AREA_MARKER_OFST 0x240
2844 
2845 /*
2846  * Register : devices_connected
2847  *
2848  * Number of Devices connected on one bank
2849  *
2850  * Register Layout
2851  *
2852  * Bits | Access | Reset | Description
2853  * :-------|:-------|:------|:-------------------------------------
2854  * [2:0] | RW | 0x0 | ALT_NAND_CFG_DEVICES_CONNECTED_VALUE
2855  * [31:3] | ??? | 0x0 | *UNDEFINED*
2856  *
2857  */
2858 /*
2859  * Field : value
2860  *
2861  * Indicates the number of devices connected to a bank. At reset, the value loaded
2862  * is the maximum possible devices that could be connected in this configuration.
2863  *
2864  * Field Access Macros:
2865  *
2866  */
2867 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field. */
2868 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_LSB 0
2869 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field. */
2870 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_MSB 2
2871 /* The width in bits of the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field. */
2872 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_WIDTH 3
2873 /* The mask used to set the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field value. */
2874 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_SET_MSK 0x00000007
2875 /* The mask used to clear the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field value. */
2876 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_CLR_MSK 0xfffffff8
2877 /* The reset value of the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field. */
2878 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_RESET 0x0
2879 /* Extracts the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE field value from a register. */
2880 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_GET(value) (((value) & 0x00000007) >> 0)
2881 /* Produces a ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field value suitable for setting the register. */
2882 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_SET(value) (((value) << 0) & 0x00000007)
2883 
2884 #ifndef __ASSEMBLY__
2885 /*
2886  * WARNING: The C register and register group struct declarations are provided for
2887  * convenience and illustrative purposes. They should, however, be used with
2888  * caution as the C language standard provides no guarantees about the alignment or
2889  * atomicity of device memory accesses. The recommended practice for writing
2890  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2891  * alt_write_word() functions.
2892  *
2893  * The struct declaration for register ALT_NAND_CFG_DEVICES_CONNECTED.
2894  */
2895 struct ALT_NAND_CFG_DEVICES_CONNECTED_s
2896 {
2897  uint32_t value : 3; /* ALT_NAND_CFG_DEVICES_CONNECTED_VALUE */
2898  uint32_t : 29; /* *UNDEFINED* */
2899 };
2900 
2901 /* The typedef declaration for register ALT_NAND_CFG_DEVICES_CONNECTED. */
2902 typedef volatile struct ALT_NAND_CFG_DEVICES_CONNECTED_s ALT_NAND_CFG_DEVICES_CONNECTED_t;
2903 #endif /* __ASSEMBLY__ */
2904 
2905 /* The byte offset of the ALT_NAND_CFG_DEVICES_CONNECTED register from the beginning of the component. */
2906 #define ALT_NAND_CFG_DEVICES_CONNECTED_OFST 0x250
2907 
2908 /*
2909  * Register : die_mask
2910  *
2911  * Indicates the die differentiator in case of NAND devices with stacked dies.
2912  *
2913  * Register Layout
2914  *
2915  * Bits | Access | Reset | Description
2916  * :-------|:-------|:------|:---------------------------
2917  * [7:0] | RW | 0x0 | ALT_NAND_CFG_DIE_MSK_VALUE
2918  * [31:8] | ??? | 0x0 | *UNDEFINED*
2919  *
2920  */
2921 /*
2922  * Field : value
2923  *
2924  * The die_mask register information will be used for devices having address
2925  * restrictions. For example, in certain Samsung devices, when the first address in
2926  * a two-plane command is being sent, it is expected that the address is all zeros.
2927  * But if the NAND device internally has multiple dies stacked, the die information
2928  * (MSB of final row address) has to be sent. The value programmed in this register
2929  * will be used to mask the address while sending out the last row address.
2930  *
2931  * Field Access Macros:
2932  *
2933  */
2934 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DIE_MSK_VALUE register field. */
2935 #define ALT_NAND_CFG_DIE_MSK_VALUE_LSB 0
2936 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DIE_MSK_VALUE register field. */
2937 #define ALT_NAND_CFG_DIE_MSK_VALUE_MSB 7
2938 /* The width in bits of the ALT_NAND_CFG_DIE_MSK_VALUE register field. */
2939 #define ALT_NAND_CFG_DIE_MSK_VALUE_WIDTH 8
2940 /* The mask used to set the ALT_NAND_CFG_DIE_MSK_VALUE register field value. */
2941 #define ALT_NAND_CFG_DIE_MSK_VALUE_SET_MSK 0x000000ff
2942 /* The mask used to clear the ALT_NAND_CFG_DIE_MSK_VALUE register field value. */
2943 #define ALT_NAND_CFG_DIE_MSK_VALUE_CLR_MSK 0xffffff00
2944 /* The reset value of the ALT_NAND_CFG_DIE_MSK_VALUE register field. */
2945 #define ALT_NAND_CFG_DIE_MSK_VALUE_RESET 0x0
2946 /* Extracts the ALT_NAND_CFG_DIE_MSK_VALUE field value from a register. */
2947 #define ALT_NAND_CFG_DIE_MSK_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
2948 /* Produces a ALT_NAND_CFG_DIE_MSK_VALUE register field value suitable for setting the register. */
2949 #define ALT_NAND_CFG_DIE_MSK_VALUE_SET(value) (((value) << 0) & 0x000000ff)
2950 
2951 #ifndef __ASSEMBLY__
2952 /*
2953  * WARNING: The C register and register group struct declarations are provided for
2954  * convenience and illustrative purposes. They should, however, be used with
2955  * caution as the C language standard provides no guarantees about the alignment or
2956  * atomicity of device memory accesses. The recommended practice for writing
2957  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2958  * alt_write_word() functions.
2959  *
2960  * The struct declaration for register ALT_NAND_CFG_DIE_MSK.
2961  */
2962 struct ALT_NAND_CFG_DIE_MSK_s
2963 {
2964  uint32_t value : 8; /* ALT_NAND_CFG_DIE_MSK_VALUE */
2965  uint32_t : 24; /* *UNDEFINED* */
2966 };
2967 
2968 /* The typedef declaration for register ALT_NAND_CFG_DIE_MSK. */
2969 typedef volatile struct ALT_NAND_CFG_DIE_MSK_s ALT_NAND_CFG_DIE_MSK_t;
2970 #endif /* __ASSEMBLY__ */
2971 
2972 /* The byte offset of the ALT_NAND_CFG_DIE_MSK register from the beginning of the component. */
2973 #define ALT_NAND_CFG_DIE_MSK_OFST 0x260
2974 
2975 /*
2976  * Register : first_block_of_next_plane
2977  *
2978  * The starting block address of the next plane in a multi plane device.
2979  *
2980  * Register Layout
2981  *
2982  * Bits | Access | Reset | Description
2983  * :--------|:-------|:------|:---------------------------------------------
2984  * [15:0] | RW | 0x1 | ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE
2985  * [31:16] | ??? | 0x0 | *UNDEFINED*
2986  *
2987  */
2988 /*
2989  * Field : value
2990  *
2991  * This values informs the controller of the plane structure of the device. In case
2992  * the device is a multi plane device and the value here is 1, the controller
2993  * understands that the next plane starts from Block number 1 and in conjunction
2994  * with the number of planes parameter can decide upon the distribution of blocks
2995  * in a plane in the device.
2996  *
2997  * Field Access Macros:
2998  *
2999  */
3000 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field. */
3001 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_LSB 0
3002 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field. */
3003 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_MSB 15
3004 /* The width in bits of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field. */
3005 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_WIDTH 16
3006 /* The mask used to set the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field value. */
3007 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_SET_MSK 0x0000ffff
3008 /* The mask used to clear the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field value. */
3009 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_CLR_MSK 0xffff0000
3010 /* The reset value of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field. */
3011 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_RESET 0x1
3012 /* Extracts the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE field value from a register. */
3013 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3014 /* Produces a ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field value suitable for setting the register. */
3015 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3016 
3017 #ifndef __ASSEMBLY__
3018 /*
3019  * WARNING: The C register and register group struct declarations are provided for
3020  * convenience and illustrative purposes. They should, however, be used with
3021  * caution as the C language standard provides no guarantees about the alignment or
3022  * atomicity of device memory accesses. The recommended practice for writing
3023  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3024  * alt_write_word() functions.
3025  *
3026  * The struct declaration for register ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE.
3027  */
3028 struct ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_s
3029 {
3030  uint32_t value : 16; /* ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE */
3031  uint32_t : 16; /* *UNDEFINED* */
3032 };
3033 
3034 /* The typedef declaration for register ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE. */
3035 typedef volatile struct ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_s ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_t;
3036 #endif /* __ASSEMBLY__ */
3037 
3038 /* The byte offset of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE register from the beginning of the component. */
3039 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_OFST 0x270
3040 
3041 /*
3042  * Register : write_protect
3043  *
3044  * This register is used to control the assertion/de-assertion of the WP# pin to
3045  * the device.
3046  *
3047  * Register Layout
3048  *
3049  * Bits | Access | Reset | Description
3050  * :-------|:-------|:------|:-----------------------------
3051  * [0] | RW | 0x1 | ALT_NAND_CFG_WR_PROTECT_FLAG
3052  * [31:1] | ??? | 0x0 | *UNDEFINED*
3053  *
3054  */
3055 /*
3056  * Field : flag
3057  *
3058  * When the controller is in reset, the WP# pin is always asserted to the device.
3059  * Once the reset is removed, the WP# is de-asserted. The software will then have
3060  * to come and program this bit to assert/de-assert the same. [list][*]1 - Write
3061  * protect de-assert [*]0 - Write protect assert[/list]
3062  *
3063  * Field Access Macros:
3064  *
3065  */
3066 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_WR_PROTECT_FLAG register field. */
3067 #define ALT_NAND_CFG_WR_PROTECT_FLAG_LSB 0
3068 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_WR_PROTECT_FLAG register field. */
3069 #define ALT_NAND_CFG_WR_PROTECT_FLAG_MSB 0
3070 /* The width in bits of the ALT_NAND_CFG_WR_PROTECT_FLAG register field. */
3071 #define ALT_NAND_CFG_WR_PROTECT_FLAG_WIDTH 1
3072 /* The mask used to set the ALT_NAND_CFG_WR_PROTECT_FLAG register field value. */
3073 #define ALT_NAND_CFG_WR_PROTECT_FLAG_SET_MSK 0x00000001
3074 /* The mask used to clear the ALT_NAND_CFG_WR_PROTECT_FLAG register field value. */
3075 #define ALT_NAND_CFG_WR_PROTECT_FLAG_CLR_MSK 0xfffffffe
3076 /* The reset value of the ALT_NAND_CFG_WR_PROTECT_FLAG register field. */
3077 #define ALT_NAND_CFG_WR_PROTECT_FLAG_RESET 0x1
3078 /* Extracts the ALT_NAND_CFG_WR_PROTECT_FLAG field value from a register. */
3079 #define ALT_NAND_CFG_WR_PROTECT_FLAG_GET(value) (((value) & 0x00000001) >> 0)
3080 /* Produces a ALT_NAND_CFG_WR_PROTECT_FLAG register field value suitable for setting the register. */
3081 #define ALT_NAND_CFG_WR_PROTECT_FLAG_SET(value) (((value) << 0) & 0x00000001)
3082 
3083 #ifndef __ASSEMBLY__
3084 /*
3085  * WARNING: The C register and register group struct declarations are provided for
3086  * convenience and illustrative purposes. They should, however, be used with
3087  * caution as the C language standard provides no guarantees about the alignment or
3088  * atomicity of device memory accesses. The recommended practice for writing
3089  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3090  * alt_write_word() functions.
3091  *
3092  * The struct declaration for register ALT_NAND_CFG_WR_PROTECT.
3093  */
3094 struct ALT_NAND_CFG_WR_PROTECT_s
3095 {
3096  uint32_t flag : 1; /* ALT_NAND_CFG_WR_PROTECT_FLAG */
3097  uint32_t : 31; /* *UNDEFINED* */
3098 };
3099 
3100 /* The typedef declaration for register ALT_NAND_CFG_WR_PROTECT. */
3101 typedef volatile struct ALT_NAND_CFG_WR_PROTECT_s ALT_NAND_CFG_WR_PROTECT_t;
3102 #endif /* __ASSEMBLY__ */
3103 
3104 /* The byte offset of the ALT_NAND_CFG_WR_PROTECT register from the beginning of the component. */
3105 #define ALT_NAND_CFG_WR_PROTECT_OFST 0x280
3106 
3107 /*
3108  * Register : re_2_re
3109  *
3110  * Timing parameter between re high to re low (Trhz) for the next bank
3111  *
3112  * Register Layout
3113  *
3114  * Bits | Access | Reset | Description
3115  * :-------|:-------|:------|:---------------------------
3116  * [5:0] | RW | 0x32 | ALT_NAND_CFG_RE_2_RE_VALUE
3117  * [31:6] | ??? | 0x0 | *UNDEFINED*
3118  *
3119  */
3120 /*
3121  * Field : value
3122  *
3123  * Signifies the number of bus interface nand_mp_clk clocks that should be
3124  * introduced between read enable going high to a bank to the read enable going low
3125  * to the next bank. The number of clocks is the function of device parameter Trhz
3126  * and controller clock frequency.
3127  *
3128  * Field Access Macros:
3129  *
3130  */
3131 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RE_2_RE_VALUE register field. */
3132 #define ALT_NAND_CFG_RE_2_RE_VALUE_LSB 0
3133 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RE_2_RE_VALUE register field. */
3134 #define ALT_NAND_CFG_RE_2_RE_VALUE_MSB 5
3135 /* The width in bits of the ALT_NAND_CFG_RE_2_RE_VALUE register field. */
3136 #define ALT_NAND_CFG_RE_2_RE_VALUE_WIDTH 6
3137 /* The mask used to set the ALT_NAND_CFG_RE_2_RE_VALUE register field value. */
3138 #define ALT_NAND_CFG_RE_2_RE_VALUE_SET_MSK 0x0000003f
3139 /* The mask used to clear the ALT_NAND_CFG_RE_2_RE_VALUE register field value. */
3140 #define ALT_NAND_CFG_RE_2_RE_VALUE_CLR_MSK 0xffffffc0
3141 /* The reset value of the ALT_NAND_CFG_RE_2_RE_VALUE register field. */
3142 #define ALT_NAND_CFG_RE_2_RE_VALUE_RESET 0x32
3143 /* Extracts the ALT_NAND_CFG_RE_2_RE_VALUE field value from a register. */
3144 #define ALT_NAND_CFG_RE_2_RE_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
3145 /* Produces a ALT_NAND_CFG_RE_2_RE_VALUE register field value suitable for setting the register. */
3146 #define ALT_NAND_CFG_RE_2_RE_VALUE_SET(value) (((value) << 0) & 0x0000003f)
3147 
3148 #ifndef __ASSEMBLY__
3149 /*
3150  * WARNING: The C register and register group struct declarations are provided for
3151  * convenience and illustrative purposes. They should, however, be used with
3152  * caution as the C language standard provides no guarantees about the alignment or
3153  * atomicity of device memory accesses. The recommended practice for writing
3154  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3155  * alt_write_word() functions.
3156  *
3157  * The struct declaration for register ALT_NAND_CFG_RE_2_RE.
3158  */
3159 struct ALT_NAND_CFG_RE_2_RE_s
3160 {
3161  uint32_t value : 6; /* ALT_NAND_CFG_RE_2_RE_VALUE */
3162  uint32_t : 26; /* *UNDEFINED* */
3163 };
3164 
3165 /* The typedef declaration for register ALT_NAND_CFG_RE_2_RE. */
3166 typedef volatile struct ALT_NAND_CFG_RE_2_RE_s ALT_NAND_CFG_RE_2_RE_t;
3167 #endif /* __ASSEMBLY__ */
3168 
3169 /* The byte offset of the ALT_NAND_CFG_RE_2_RE register from the beginning of the component. */
3170 #define ALT_NAND_CFG_RE_2_RE_OFST 0x290
3171 
3172 /*
3173  * Register : por_reset_count
3174  *
3175  * The number of cycles the controller waits after reset to issue the first RESET
3176  * command to the device.
3177  *
3178  * Register Layout
3179  *
3180  * Bits | Access | Reset | Description
3181  * :--------|:-------|:------|:---------------------------------
3182  * [15:0] | RW | 0x13b | ALT_NAND_CFG_POR_RST_COUNT_VALUE
3183  * [31:16] | ??? | 0x0 | *UNDEFINED*
3184  *
3185  */
3186 /*
3187  * Field : value
3188  *
3189  * The controller waits for this number of cycles before issuing the first RESET
3190  * command to the device. The number in this register is multiplied internally by
3191  * 16 in the controller to form the final reset wait count.
3192  *
3193  * Field Access Macros:
3194  *
3195  */
3196 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field. */
3197 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_LSB 0
3198 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field. */
3199 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_MSB 15
3200 /* The width in bits of the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field. */
3201 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_WIDTH 16
3202 /* The mask used to set the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field value. */
3203 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_SET_MSK 0x0000ffff
3204 /* The mask used to clear the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field value. */
3205 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_CLR_MSK 0xffff0000
3206 /* The reset value of the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field. */
3207 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_RESET 0x13b
3208 /* Extracts the ALT_NAND_CFG_POR_RST_COUNT_VALUE field value from a register. */
3209 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3210 /* Produces a ALT_NAND_CFG_POR_RST_COUNT_VALUE register field value suitable for setting the register. */
3211 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3212 
3213 #ifndef __ASSEMBLY__
3214 /*
3215  * WARNING: The C register and register group struct declarations are provided for
3216  * convenience and illustrative purposes. They should, however, be used with
3217  * caution as the C language standard provides no guarantees about the alignment or
3218  * atomicity of device memory accesses. The recommended practice for writing
3219  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3220  * alt_write_word() functions.
3221  *
3222  * The struct declaration for register ALT_NAND_CFG_POR_RST_COUNT.
3223  */
3224 struct ALT_NAND_CFG_POR_RST_COUNT_s
3225 {
3226  uint32_t value : 16; /* ALT_NAND_CFG_POR_RST_COUNT_VALUE */
3227  uint32_t : 16; /* *UNDEFINED* */
3228 };
3229 
3230 /* The typedef declaration for register ALT_NAND_CFG_POR_RST_COUNT. */
3231 typedef volatile struct ALT_NAND_CFG_POR_RST_COUNT_s ALT_NAND_CFG_POR_RST_COUNT_t;
3232 #endif /* __ASSEMBLY__ */
3233 
3234 /* The byte offset of the ALT_NAND_CFG_POR_RST_COUNT register from the beginning of the component. */
3235 #define ALT_NAND_CFG_POR_RST_COUNT_OFST 0x2a0
3236 
3237 /*
3238  * Register : watchdog_reset_count
3239  *
3240  * The number of cycles the controller waits before flagging a watchdog timeout
3241  * interrupt.
3242  *
3243  * Register Layout
3244  *
3245  * Bits | Access | Reset | Description
3246  * :--------|:-------|:-------|:--------------------------------
3247  * [15:0] | RW | 0x5b9a | ALT_NAND_CFG_WD_RST_COUNT_VALUE
3248  * [31:16] | ??? | 0x0 | *UNDEFINED*
3249  *
3250  */
3251 /*
3252  * Field : value
3253  *
3254  * The controller waits for this number of cycles before issuing a watchdog timeout
3255  * interrupt. The value in this register is multiplied internally by 32 in the
3256  * controller to form the final watchdog counter.
3257  *
3258  * Field Access Macros:
3259  *
3260  */
3261 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_WD_RST_COUNT_VALUE register field. */
3262 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_LSB 0
3263 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_WD_RST_COUNT_VALUE register field. */
3264 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_MSB 15
3265 /* The width in bits of the ALT_NAND_CFG_WD_RST_COUNT_VALUE register field. */
3266 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_WIDTH 16
3267 /* The mask used to set the ALT_NAND_CFG_WD_RST_COUNT_VALUE register field value. */
3268 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_SET_MSK 0x0000ffff
3269 /* The mask used to clear the ALT_NAND_CFG_WD_RST_COUNT_VALUE register field value. */
3270 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_CLR_MSK 0xffff0000
3271 /* The reset value of the ALT_NAND_CFG_WD_RST_COUNT_VALUE register field. */
3272 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_RESET 0x5b9a
3273 /* Extracts the ALT_NAND_CFG_WD_RST_COUNT_VALUE field value from a register. */
3274 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3275 /* Produces a ALT_NAND_CFG_WD_RST_COUNT_VALUE register field value suitable for setting the register. */
3276 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3277 
3278 #ifndef __ASSEMBLY__
3279 /*
3280  * WARNING: The C register and register group struct declarations are provided for
3281  * convenience and illustrative purposes. They should, however, be used with
3282  * caution as the C language standard provides no guarantees about the alignment or
3283  * atomicity of device memory accesses. The recommended practice for writing
3284  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3285  * alt_write_word() functions.
3286  *
3287  * The struct declaration for register ALT_NAND_CFG_WD_RST_COUNT.
3288  */
3289 struct ALT_NAND_CFG_WD_RST_COUNT_s
3290 {
3291  uint32_t value : 16; /* ALT_NAND_CFG_WD_RST_COUNT_VALUE */
3292  uint32_t : 16; /* *UNDEFINED* */
3293 };
3294 
3295 /* The typedef declaration for register ALT_NAND_CFG_WD_RST_COUNT. */
3296 typedef volatile struct ALT_NAND_CFG_WD_RST_COUNT_s ALT_NAND_CFG_WD_RST_COUNT_t;
3297 #endif /* __ASSEMBLY__ */
3298 
3299 /* The byte offset of the ALT_NAND_CFG_WD_RST_COUNT register from the beginning of the component. */
3300 #define ALT_NAND_CFG_WD_RST_COUNT_OFST 0x2b0
3301 
3302 #ifndef __ASSEMBLY__
3303 /*
3304  * WARNING: The C register and register group struct declarations are provided for
3305  * convenience and illustrative purposes. They should, however, be used with
3306  * caution as the C language standard provides no guarantees about the alignment or
3307  * atomicity of device memory accesses. The recommended practice for writing
3308  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3309  * alt_write_word() functions.
3310  *
3311  * The struct declaration for register group ALT_NAND_CFG.
3312  */
3313 struct ALT_NAND_CFG_s
3314 {
3315  ALT_NAND_CFG_DEVICE_RST_t device_reset; /* ALT_NAND_CFG_DEVICE_RST */
3316  volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
3317  ALT_NAND_CFG_TFR_SPARE_REG_t transfer_spare_reg; /* ALT_NAND_CFG_TFR_SPARE_REG */
3318  volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
3319  ALT_NAND_CFG_LD_WAIT_CNT_t load_wait_cnt; /* ALT_NAND_CFG_LD_WAIT_CNT */
3320  volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
3321  ALT_NAND_CFG_PROGRAM_WAIT_CNT_t program_wait_cnt; /* ALT_NAND_CFG_PROGRAM_WAIT_CNT */
3322  volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
3323  ALT_NAND_CFG_ERASE_WAIT_CNT_t erase_wait_cnt; /* ALT_NAND_CFG_ERASE_WAIT_CNT */
3324  volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
3325  ALT_NAND_CFG_INT_MON_CYCCNT_t int_mon_cyccnt; /* ALT_NAND_CFG_INT_MON_CYCCNT */
3326  volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
3327  ALT_NAND_CFG_RB_PIN_END_t rb_pin_enabled; /* ALT_NAND_CFG_RB_PIN_END */
3328  volatile uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */
3329  ALT_NAND_CFG_MULTIPLANE_OP_t multiplane_operation; /* ALT_NAND_CFG_MULTIPLANE_OP */
3330  volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
3331  ALT_NAND_CFG_MULTIPLANE_RD_EN_t multiplane_read_enable; /* ALT_NAND_CFG_MULTIPLANE_RD_EN */
3332  volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
3333  ALT_NAND_CFG_COPYBACK_DIS_t copyback_disable; /* ALT_NAND_CFG_COPYBACK_DIS */
3334  volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
3335  ALT_NAND_CFG_CACHE_WR_EN_t cache_write_enable; /* ALT_NAND_CFG_CACHE_WR_EN */
3336  volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
3337  ALT_NAND_CFG_CACHE_RD_EN_t cache_read_enable; /* ALT_NAND_CFG_CACHE_RD_EN */
3338  volatile uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */
3339  ALT_NAND_CFG_PREFETCH_MOD_t prefetch_mode; /* ALT_NAND_CFG_PREFETCH_MOD */
3340  volatile uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */
3341  ALT_NAND_CFG_CHIP_EN_DONT_CARE_t chip_enable_dont_care; /* ALT_NAND_CFG_CHIP_EN_DONT_CARE */
3342  volatile uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */
3343  ALT_NAND_CFG_ECC_EN_t ecc_enable; /* ALT_NAND_CFG_ECC_EN */
3344  volatile uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */
3345  ALT_NAND_CFG_GLOB_INT_EN_t global_int_enable; /* ALT_NAND_CFG_GLOB_INT_EN */
3346  volatile uint32_t _pad_0xf4_0xff[3]; /* *UNDEFINED* */
3347  ALT_NAND_CFG_TWHR2_AND_WE_2_RE_t twhr2_and_we_2_re; /* ALT_NAND_CFG_TWHR2_AND_WE_2_RE */
3348  volatile uint32_t _pad_0x104_0x10f[3]; /* *UNDEFINED* */
3349  ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_t tcwaw_and_addr_2_data; /* ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA */
3350  volatile uint32_t _pad_0x114_0x11f[3]; /* *UNDEFINED* */
3351  ALT_NAND_CFG_RE_2_WE_t re_2_we; /* ALT_NAND_CFG_RE_2_WE */
3352  volatile uint32_t _pad_0x124_0x12f[3]; /* *UNDEFINED* */
3353  ALT_NAND_CFG_ACC_CLKS_t acc_clks; /* ALT_NAND_CFG_ACC_CLKS */
3354  volatile uint32_t _pad_0x134_0x13f[3]; /* *UNDEFINED* */
3355  ALT_NAND_CFG_NUMBER_OF_PLANES_t number_of_planes; /* ALT_NAND_CFG_NUMBER_OF_PLANES */
3356  volatile uint32_t _pad_0x144_0x14f[3]; /* *UNDEFINED* */
3357  ALT_NAND_CFG_PAGES_PER_BLOCK_t pages_per_block; /* ALT_NAND_CFG_PAGES_PER_BLOCK */
3358  volatile uint32_t _pad_0x154_0x15f[3]; /* *UNDEFINED* */
3359  ALT_NAND_CFG_DEVICE_WIDTH_t device_width; /* ALT_NAND_CFG_DEVICE_WIDTH */
3360  volatile uint32_t _pad_0x164_0x16f[3]; /* *UNDEFINED* */
3361  ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_t device_main_area_size; /* ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE */
3362  volatile uint32_t _pad_0x174_0x17f[3]; /* *UNDEFINED* */
3363  ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_t device_spare_area_size; /* ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE */
3364  volatile uint32_t _pad_0x184_0x18f[3]; /* *UNDEFINED* */
3365  ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_t two_row_addr_cycles; /* ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES */
3366  volatile uint32_t _pad_0x194_0x19f[3]; /* *UNDEFINED* */
3367  ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_t multiplane_addr_restrict; /* ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT */
3368  volatile uint32_t _pad_0x1a4_0x1af[3]; /* *UNDEFINED* */
3369  ALT_NAND_CFG_ECC_CORRECTION_t ecc_correction; /* ALT_NAND_CFG_ECC_CORRECTION */
3370  volatile uint32_t _pad_0x1b4_0x1bf[3]; /* *UNDEFINED* */
3371  ALT_NAND_CFG_RD_MOD_t read_mode; /* ALT_NAND_CFG_RD_MOD */
3372  volatile uint32_t _pad_0x1c4_0x1cf[3]; /* *UNDEFINED* */
3373  ALT_NAND_CFG_WR_MOD_t write_mode; /* ALT_NAND_CFG_WR_MOD */
3374  volatile uint32_t _pad_0x1d4_0x1df[3]; /* *UNDEFINED* */
3375  ALT_NAND_CFG_COPYBACK_MOD_t copyback_mode; /* ALT_NAND_CFG_COPYBACK_MOD */
3376  volatile uint32_t _pad_0x1e4_0x1ef[3]; /* *UNDEFINED* */
3377  ALT_NAND_CFG_RDWR_EN_LO_CNT_t rdwr_en_lo_cnt; /* ALT_NAND_CFG_RDWR_EN_LO_CNT */
3378  volatile uint32_t _pad_0x1f4_0x1ff[3]; /* *UNDEFINED* */
3379  ALT_NAND_CFG_RDWR_EN_HI_CNT_t rdwr_en_hi_cnt; /* ALT_NAND_CFG_RDWR_EN_HI_CNT */
3380  volatile uint32_t _pad_0x204_0x20f[3]; /* *UNDEFINED* */
3381  ALT_NAND_CFG_MAX_RD_DELAY_t max_rd_delay; /* ALT_NAND_CFG_MAX_RD_DELAY */
3382  volatile uint32_t _pad_0x214_0x21f[3]; /* *UNDEFINED* */
3383  ALT_NAND_CFG_CS_SETUP_CNT_t cs_setup_cnt; /* ALT_NAND_CFG_CS_SETUP_CNT */
3384  volatile uint32_t _pad_0x224_0x22f[3]; /* *UNDEFINED* */
3385  ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_t spare_area_skip_bytes; /* ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES */
3386  volatile uint32_t _pad_0x234_0x23f[3]; /* *UNDEFINED* */
3387  ALT_NAND_CFG_SPARE_AREA_MARKER_t spare_area_marker; /* ALT_NAND_CFG_SPARE_AREA_MARKER */
3388  volatile uint32_t _pad_0x244_0x24f[3]; /* *UNDEFINED* */
3389  ALT_NAND_CFG_DEVICES_CONNECTED_t devices_connected; /* ALT_NAND_CFG_DEVICES_CONNECTED */
3390  volatile uint32_t _pad_0x254_0x25f[3]; /* *UNDEFINED* */
3391  ALT_NAND_CFG_DIE_MSK_t die_mask; /* ALT_NAND_CFG_DIE_MSK */
3392  volatile uint32_t _pad_0x264_0x26f[3]; /* *UNDEFINED* */
3393  ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_t first_block_of_next_plane; /* ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE */
3394  volatile uint32_t _pad_0x274_0x27f[3]; /* *UNDEFINED* */
3395  ALT_NAND_CFG_WR_PROTECT_t write_protect; /* ALT_NAND_CFG_WR_PROTECT */
3396  volatile uint32_t _pad_0x284_0x28f[3]; /* *UNDEFINED* */
3397  ALT_NAND_CFG_RE_2_RE_t re_2_re; /* ALT_NAND_CFG_RE_2_RE */
3398  volatile uint32_t _pad_0x294_0x29f[3]; /* *UNDEFINED* */
3399  ALT_NAND_CFG_POR_RST_COUNT_t por_reset_count; /* ALT_NAND_CFG_POR_RST_COUNT */
3400  volatile uint32_t _pad_0x2a4_0x2af[3]; /* *UNDEFINED* */
3401  ALT_NAND_CFG_WD_RST_COUNT_t watchdog_reset_count; /* ALT_NAND_CFG_WD_RST_COUNT */
3402 };
3403 
3404 /* The typedef declaration for register group ALT_NAND_CFG. */
3405 typedef volatile struct ALT_NAND_CFG_s ALT_NAND_CFG_t;
3406 /* The struct declaration for the raw register contents of register group ALT_NAND_CFG. */
3407 struct ALT_NAND_CFG_raw_s
3408 {
3409  volatile uint32_t device_reset; /* ALT_NAND_CFG_DEVICE_RST */
3410  uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
3411  volatile uint32_t transfer_spare_reg; /* ALT_NAND_CFG_TFR_SPARE_REG */
3412  uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
3413  volatile uint32_t load_wait_cnt; /* ALT_NAND_CFG_LD_WAIT_CNT */
3414  uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
3415  volatile uint32_t program_wait_cnt; /* ALT_NAND_CFG_PROGRAM_WAIT_CNT */
3416  uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
3417  volatile uint32_t erase_wait_cnt; /* ALT_NAND_CFG_ERASE_WAIT_CNT */
3418  uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
3419  volatile uint32_t int_mon_cyccnt; /* ALT_NAND_CFG_INT_MON_CYCCNT */
3420  uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
3421  volatile uint32_t rb_pin_enabled; /* ALT_NAND_CFG_RB_PIN_END */
3422  uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */
3423  volatile uint32_t multiplane_operation; /* ALT_NAND_CFG_MULTIPLANE_OP */
3424  uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
3425  volatile uint32_t multiplane_read_enable; /* ALT_NAND_CFG_MULTIPLANE_RD_EN */
3426  uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
3427  volatile uint32_t copyback_disable; /* ALT_NAND_CFG_COPYBACK_DIS */
3428  uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
3429  volatile uint32_t cache_write_enable; /* ALT_NAND_CFG_CACHE_WR_EN */
3430  uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
3431  volatile uint32_t cache_read_enable; /* ALT_NAND_CFG_CACHE_RD_EN */
3432  uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */
3433  volatile uint32_t prefetch_mode; /* ALT_NAND_CFG_PREFETCH_MOD */
3434  uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */
3435  volatile uint32_t chip_enable_dont_care; /* ALT_NAND_CFG_CHIP_EN_DONT_CARE */
3436  uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */
3437  volatile uint32_t ecc_enable; /* ALT_NAND_CFG_ECC_EN */
3438  uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */
3439  volatile uint32_t global_int_enable; /* ALT_NAND_CFG_GLOB_INT_EN */
3440  uint32_t _pad_0xf4_0xff[3]; /* *UNDEFINED* */
3441  volatile uint32_t twhr2_and_we_2_re; /* ALT_NAND_CFG_TWHR2_AND_WE_2_RE */
3442  uint32_t _pad_0x104_0x10f[3]; /* *UNDEFINED* */
3443  volatile uint32_t tcwaw_and_addr_2_data; /* ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA */
3444  uint32_t _pad_0x114_0x11f[3]; /* *UNDEFINED* */
3445  volatile uint32_t re_2_we; /* ALT_NAND_CFG_RE_2_WE */
3446  uint32_t _pad_0x124_0x12f[3]; /* *UNDEFINED* */
3447  volatile uint32_t acc_clks; /* ALT_NAND_CFG_ACC_CLKS */
3448  uint32_t _pad_0x134_0x13f[3]; /* *UNDEFINED* */
3449  volatile uint32_t number_of_planes; /* ALT_NAND_CFG_NUMBER_OF_PLANES */
3450  uint32_t _pad_0x144_0x14f[3]; /* *UNDEFINED* */
3451  volatile uint32_t pages_per_block; /* ALT_NAND_CFG_PAGES_PER_BLOCK */
3452  uint32_t _pad_0x154_0x15f[3]; /* *UNDEFINED* */
3453  volatile uint32_t device_width; /* ALT_NAND_CFG_DEVICE_WIDTH */
3454  uint32_t _pad_0x164_0x16f[3]; /* *UNDEFINED* */
3455  volatile uint32_t device_main_area_size; /* ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE */
3456  uint32_t _pad_0x174_0x17f[3]; /* *UNDEFINED* */
3457  volatile uint32_t device_spare_area_size; /* ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE */
3458  uint32_t _pad_0x184_0x18f[3]; /* *UNDEFINED* */
3459  volatile uint32_t two_row_addr_cycles; /* ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES */
3460  uint32_t _pad_0x194_0x19f[3]; /* *UNDEFINED* */
3461  volatile uint32_t multiplane_addr_restrict; /* ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT */
3462  uint32_t _pad_0x1a4_0x1af[3]; /* *UNDEFINED* */
3463  volatile uint32_t ecc_correction; /* ALT_NAND_CFG_ECC_CORRECTION */
3464  uint32_t _pad_0x1b4_0x1bf[3]; /* *UNDEFINED* */
3465  volatile uint32_t read_mode; /* ALT_NAND_CFG_RD_MOD */
3466  uint32_t _pad_0x1c4_0x1cf[3]; /* *UNDEFINED* */
3467  volatile uint32_t write_mode; /* ALT_NAND_CFG_WR_MOD */
3468  uint32_t _pad_0x1d4_0x1df[3]; /* *UNDEFINED* */
3469  volatile uint32_t copyback_mode; /* ALT_NAND_CFG_COPYBACK_MOD */
3470  uint32_t _pad_0x1e4_0x1ef[3]; /* *UNDEFINED* */
3471  volatile uint32_t rdwr_en_lo_cnt; /* ALT_NAND_CFG_RDWR_EN_LO_CNT */
3472  uint32_t _pad_0x1f4_0x1ff[3]; /* *UNDEFINED* */
3473  volatile uint32_t rdwr_en_hi_cnt; /* ALT_NAND_CFG_RDWR_EN_HI_CNT */
3474  uint32_t _pad_0x204_0x20f[3]; /* *UNDEFINED* */
3475  volatile uint32_t max_rd_delay; /* ALT_NAND_CFG_MAX_RD_DELAY */
3476  uint32_t _pad_0x214_0x21f[3]; /* *UNDEFINED* */
3477  volatile uint32_t cs_setup_cnt; /* ALT_NAND_CFG_CS_SETUP_CNT */
3478  uint32_t _pad_0x224_0x22f[3]; /* *UNDEFINED* */
3479  volatile uint32_t spare_area_skip_bytes; /* ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES */
3480  uint32_t _pad_0x234_0x23f[3]; /* *UNDEFINED* */
3481  volatile uint32_t spare_area_marker; /* ALT_NAND_CFG_SPARE_AREA_MARKER */
3482  uint32_t _pad_0x244_0x24f[3]; /* *UNDEFINED* */
3483  volatile uint32_t devices_connected; /* ALT_NAND_CFG_DEVICES_CONNECTED */
3484  uint32_t _pad_0x254_0x25f[3]; /* *UNDEFINED* */
3485  volatile uint32_t die_mask; /* ALT_NAND_CFG_DIE_MSK */
3486  uint32_t _pad_0x264_0x26f[3]; /* *UNDEFINED* */
3487  volatile uint32_t first_block_of_next_plane; /* ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE */
3488  uint32_t _pad_0x274_0x27f[3]; /* *UNDEFINED* */
3489  volatile uint32_t write_protect; /* ALT_NAND_CFG_WR_PROTECT */
3490  uint32_t _pad_0x284_0x28f[3]; /* *UNDEFINED* */
3491  volatile uint32_t re_2_re; /* ALT_NAND_CFG_RE_2_RE */
3492  uint32_t _pad_0x294_0x29f[3]; /* *UNDEFINED* */
3493  volatile uint32_t por_reset_count; /* ALT_NAND_CFG_POR_RST_COUNT */
3494  uint32_t _pad_0x2a4_0x2af[3]; /* *UNDEFINED* */
3495  volatile uint32_t watchdog_reset_count; /* ALT_NAND_CFG_WD_RST_COUNT */
3496 };
3497 
3498 /* The typedef declaration for the raw register contents of register group ALT_NAND_CFG. */
3499 typedef volatile struct ALT_NAND_CFG_raw_s ALT_NAND_CFG_raw_t;
3500 #endif /* __ASSEMBLY__ */
3501 
3502 
3503 /*
3504  * Register Group : Device parameters - ALT_NAND_PARAM
3505  * Device parameters
3506  *
3507  * Controller reads device parameters after initialization and stores in the
3508  * following registers for software
3509  *
3510  */
3511 /*
3512  * Register : manufacturer_id
3513  *
3514  * Register Layout
3515  *
3516  * Bits | Access | Reset | Description
3517  * :-------|:-------|:------|:-------------------------------------
3518  * [7:0] | RW | 0x0 | ALT_NAND_PARAM_MANUFACTURER_ID_VALUE
3519  * [31:8] | ??? | 0x0 | *UNDEFINED*
3520  *
3521  */
3522 /*
3523  * Field : value
3524  *
3525  * Manufacturer ID
3526  *
3527  * Field Access Macros:
3528  *
3529  */
3530 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field. */
3531 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_LSB 0
3532 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field. */
3533 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_MSB 7
3534 /* The width in bits of the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field. */
3535 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_WIDTH 8
3536 /* The mask used to set the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field value. */
3537 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_SET_MSK 0x000000ff
3538 /* The mask used to clear the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field value. */
3539 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_CLR_MSK 0xffffff00
3540 /* The reset value of the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field. */
3541 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_RESET 0x0
3542 /* Extracts the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE field value from a register. */
3543 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
3544 /* Produces a ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field value suitable for setting the register. */
3545 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_SET(value) (((value) << 0) & 0x000000ff)
3546 
3547 #ifndef __ASSEMBLY__
3548 /*
3549  * WARNING: The C register and register group struct declarations are provided for
3550  * convenience and illustrative purposes. They should, however, be used with
3551  * caution as the C language standard provides no guarantees about the alignment or
3552  * atomicity of device memory accesses. The recommended practice for writing
3553  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3554  * alt_write_word() functions.
3555  *
3556  * The struct declaration for register ALT_NAND_PARAM_MANUFACTURER_ID.
3557  */
3558 struct ALT_NAND_PARAM_MANUFACTURER_ID_s
3559 {
3560  uint32_t value : 8; /* ALT_NAND_PARAM_MANUFACTURER_ID_VALUE */
3561  uint32_t : 24; /* *UNDEFINED* */
3562 };
3563 
3564 /* The typedef declaration for register ALT_NAND_PARAM_MANUFACTURER_ID. */
3565 typedef volatile struct ALT_NAND_PARAM_MANUFACTURER_ID_s ALT_NAND_PARAM_MANUFACTURER_ID_t;
3566 #endif /* __ASSEMBLY__ */
3567 
3568 /* The byte offset of the ALT_NAND_PARAM_MANUFACTURER_ID register from the beginning of the component. */
3569 #define ALT_NAND_PARAM_MANUFACTURER_ID_OFST 0x0
3570 
3571 /*
3572  * Register : device_id
3573  *
3574  * Register Layout
3575  *
3576  * Bits | Access | Reset | Description
3577  * :-------|:-------|:------|:-------------------------------
3578  * [7:0] | R | 0x0 | ALT_NAND_PARAM_DEVICE_ID_VALUE
3579  * [31:8] | ??? | 0x0 | *UNDEFINED*
3580  *
3581  */
3582 /*
3583  * Field : value
3584  *
3585  * Device ID. This register is updated only for Legacy NAND devices.
3586  *
3587  * Field Access Macros:
3588  *
3589  */
3590 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_DEVICE_ID_VALUE register field. */
3591 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_LSB 0
3592 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_DEVICE_ID_VALUE register field. */
3593 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_MSB 7
3594 /* The width in bits of the ALT_NAND_PARAM_DEVICE_ID_VALUE register field. */
3595 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_WIDTH 8
3596 /* The mask used to set the ALT_NAND_PARAM_DEVICE_ID_VALUE register field value. */
3597 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_SET_MSK 0x000000ff
3598 /* The mask used to clear the ALT_NAND_PARAM_DEVICE_ID_VALUE register field value. */
3599 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_CLR_MSK 0xffffff00
3600 /* The reset value of the ALT_NAND_PARAM_DEVICE_ID_VALUE register field. */
3601 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_RESET 0x0
3602 /* Extracts the ALT_NAND_PARAM_DEVICE_ID_VALUE field value from a register. */
3603 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
3604 /* Produces a ALT_NAND_PARAM_DEVICE_ID_VALUE register field value suitable for setting the register. */
3605 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_SET(value) (((value) << 0) & 0x000000ff)
3606 
3607 #ifndef __ASSEMBLY__
3608 /*
3609  * WARNING: The C register and register group struct declarations are provided for
3610  * convenience and illustrative purposes. They should, however, be used with
3611  * caution as the C language standard provides no guarantees about the alignment or
3612  * atomicity of device memory accesses. The recommended practice for writing
3613  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3614  * alt_write_word() functions.
3615  *
3616  * The struct declaration for register ALT_NAND_PARAM_DEVICE_ID.
3617  */
3618 struct ALT_NAND_PARAM_DEVICE_ID_s
3619 {
3620  const uint32_t value : 8; /* ALT_NAND_PARAM_DEVICE_ID_VALUE */
3621  uint32_t : 24; /* *UNDEFINED* */
3622 };
3623 
3624 /* The typedef declaration for register ALT_NAND_PARAM_DEVICE_ID. */
3625 typedef volatile struct ALT_NAND_PARAM_DEVICE_ID_s ALT_NAND_PARAM_DEVICE_ID_t;
3626 #endif /* __ASSEMBLY__ */
3627 
3628 /* The byte offset of the ALT_NAND_PARAM_DEVICE_ID register from the beginning of the component. */
3629 #define ALT_NAND_PARAM_DEVICE_ID_OFST 0x10
3630 
3631 /*
3632  * Register : device_param_0
3633  *
3634  * Register Layout
3635  *
3636  * Bits | Access | Reset | Description
3637  * :-------|:-------|:------|:------------------------------------
3638  * [7:0] | R | 0x0 | ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE
3639  * [31:8] | ??? | 0x0 | *UNDEFINED*
3640  *
3641  */
3642 /*
3643  * Field : value
3644  *
3645  * 3rd byte relating to Device Signature. This register is updated only for Legacy
3646  * NAND devices.
3647  *
3648  * Field Access Macros:
3649  *
3650  */
3651 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field. */
3652 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_LSB 0
3653 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field. */
3654 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_MSB 7
3655 /* The width in bits of the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field. */
3656 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_WIDTH 8
3657 /* The mask used to set the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field value. */
3658 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_SET_MSK 0x000000ff
3659 /* The mask used to clear the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field value. */
3660 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_CLR_MSK 0xffffff00
3661 /* The reset value of the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field. */
3662 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_RESET 0x0
3663 /* Extracts the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE field value from a register. */
3664 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
3665 /* Produces a ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field value suitable for setting the register. */
3666 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_SET(value) (((value) << 0) & 0x000000ff)
3667 
3668 #ifndef __ASSEMBLY__
3669 /*
3670  * WARNING: The C register and register group struct declarations are provided for
3671  * convenience and illustrative purposes. They should, however, be used with
3672  * caution as the C language standard provides no guarantees about the alignment or
3673  * atomicity of device memory accesses. The recommended practice for writing
3674  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3675  * alt_write_word() functions.
3676  *
3677  * The struct declaration for register ALT_NAND_PARAM_DEVICE_PARAM_0.
3678  */
3679 struct ALT_NAND_PARAM_DEVICE_PARAM_0_s
3680 {
3681  const uint32_t value : 8; /* ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE */
3682  uint32_t : 24; /* *UNDEFINED* */
3683 };
3684 
3685 /* The typedef declaration for register ALT_NAND_PARAM_DEVICE_PARAM_0. */
3686 typedef volatile struct ALT_NAND_PARAM_DEVICE_PARAM_0_s ALT_NAND_PARAM_DEVICE_PARAM_0_t;
3687 #endif /* __ASSEMBLY__ */
3688 
3689 /* The byte offset of the ALT_NAND_PARAM_DEVICE_PARAM_0 register from the beginning of the component. */
3690 #define ALT_NAND_PARAM_DEVICE_PARAM_0_OFST 0x20
3691 
3692 /*
3693  * Register : device_param_1
3694  *
3695  * Register Layout
3696  *
3697  * Bits | Access | Reset | Description
3698  * :-------|:-------|:------|:------------------------------------
3699  * [7:0] | R | 0x0 | ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE
3700  * [31:8] | ??? | 0x0 | *UNDEFINED*
3701  *
3702  */
3703 /*
3704  * Field : value
3705  *
3706  * 4th byte relating to Device Signature. This register is updated only for Legacy
3707  * NAND devices.
3708  *
3709  * Field Access Macros:
3710  *
3711  */
3712 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field. */
3713 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_LSB 0
3714 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field. */
3715 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_MSB 7
3716 /* The width in bits of the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field. */
3717 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_WIDTH 8
3718 /* The mask used to set the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field value. */
3719 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_SET_MSK 0x000000ff
3720 /* The mask used to clear the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field value. */
3721 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_CLR_MSK 0xffffff00
3722 /* The reset value of the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field. */
3723 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_RESET 0x0
3724 /* Extracts the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE field value from a register. */
3725 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
3726 /* Produces a ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field value suitable for setting the register. */
3727 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_SET(value) (((value) << 0) & 0x000000ff)
3728 
3729 #ifndef __ASSEMBLY__
3730 /*
3731  * WARNING: The C register and register group struct declarations are provided for
3732  * convenience and illustrative purposes. They should, however, be used with
3733  * caution as the C language standard provides no guarantees about the alignment or
3734  * atomicity of device memory accesses. The recommended practice for writing
3735  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3736  * alt_write_word() functions.
3737  *
3738  * The struct declaration for register ALT_NAND_PARAM_DEVICE_PARAM_1.
3739  */
3740 struct ALT_NAND_PARAM_DEVICE_PARAM_1_s
3741 {
3742  const uint32_t value : 8; /* ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE */
3743  uint32_t : 24; /* *UNDEFINED* */
3744 };
3745 
3746 /* The typedef declaration for register ALT_NAND_PARAM_DEVICE_PARAM_1. */
3747 typedef volatile struct ALT_NAND_PARAM_DEVICE_PARAM_1_s ALT_NAND_PARAM_DEVICE_PARAM_1_t;
3748 #endif /* __ASSEMBLY__ */
3749 
3750 /* The byte offset of the ALT_NAND_PARAM_DEVICE_PARAM_1 register from the beginning of the component. */
3751 #define ALT_NAND_PARAM_DEVICE_PARAM_1_OFST 0x30
3752 
3753 /*
3754  * Register : device_param_2
3755  *
3756  * Register Layout
3757  *
3758  * Bits | Access | Reset | Description
3759  * :-------|:-------|:------|:------------------------------------
3760  * [7:0] | R | 0x0 | ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE
3761  * [31:8] | ??? | 0x0 | *UNDEFINED*
3762  *
3763  */
3764 /*
3765  * Field : value
3766  *
3767  * Reserved.
3768  *
3769  * Field Access Macros:
3770  *
3771  */
3772 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field. */
3773 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_LSB 0
3774 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field. */
3775 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_MSB 7
3776 /* The width in bits of the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field. */
3777 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_WIDTH 8
3778 /* The mask used to set the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field value. */
3779 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_SET_MSK 0x000000ff
3780 /* The mask used to clear the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field value. */
3781 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_CLR_MSK 0xffffff00
3782 /* The reset value of the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field. */
3783 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_RESET 0x0
3784 /* Extracts the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE field value from a register. */
3785 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
3786 /* Produces a ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field value suitable for setting the register. */
3787 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_SET(value) (((value) << 0) & 0x000000ff)
3788 
3789 #ifndef __ASSEMBLY__
3790 /*
3791  * WARNING: The C register and register group struct declarations are provided for
3792  * convenience and illustrative purposes. They should, however, be used with
3793  * caution as the C language standard provides no guarantees about the alignment or
3794  * atomicity of device memory accesses. The recommended practice for writing
3795  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3796  * alt_write_word() functions.
3797  *
3798  * The struct declaration for register ALT_NAND_PARAM_DEVICE_PARAM_2.
3799  */
3800 struct ALT_NAND_PARAM_DEVICE_PARAM_2_s
3801 {
3802  const uint32_t value : 8; /* ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE */
3803  uint32_t : 24; /* *UNDEFINED* */
3804 };
3805 
3806 /* The typedef declaration for register ALT_NAND_PARAM_DEVICE_PARAM_2. */
3807 typedef volatile struct ALT_NAND_PARAM_DEVICE_PARAM_2_s ALT_NAND_PARAM_DEVICE_PARAM_2_t;
3808 #endif /* __ASSEMBLY__ */
3809 
3810 /* The byte offset of the ALT_NAND_PARAM_DEVICE_PARAM_2 register from the beginning of the component. */
3811 #define ALT_NAND_PARAM_DEVICE_PARAM_2_OFST 0x40
3812 
3813 /*
3814  * Register : logical_page_data_size
3815  *
3816  * Logical page data area size in bytes
3817  *
3818  * Register Layout
3819  *
3820  * Bits | Access | Reset | Description
3821  * :--------|:-------|:------|:--------------------------------------------
3822  * [15:0] | R | 0x0 | ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE
3823  * [31:16] | ??? | 0x0 | *UNDEFINED*
3824  *
3825  */
3826 /*
3827  * Field : value
3828  *
3829  * Logical page spare area size in bytes. If multiple devices are connected on a
3830  * single chip select, physical page data size will be multiplied by the number of
3831  * devices to arrive at logical page size.
3832  *
3833  * Field Access Macros:
3834  *
3835  */
3836 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field. */
3837 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_LSB 0
3838 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field. */
3839 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_MSB 15
3840 /* The width in bits of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field. */
3841 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_WIDTH 16
3842 /* The mask used to set the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field value. */
3843 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_SET_MSK 0x0000ffff
3844 /* The mask used to clear the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field value. */
3845 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_CLR_MSK 0xffff0000
3846 /* The reset value of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field. */
3847 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_RESET 0x0
3848 /* Extracts the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE field value from a register. */
3849 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3850 /* Produces a ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field value suitable for setting the register. */
3851 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3852 
3853 #ifndef __ASSEMBLY__
3854 /*
3855  * WARNING: The C register and register group struct declarations are provided for
3856  * convenience and illustrative purposes. They should, however, be used with
3857  * caution as the C language standard provides no guarantees about the alignment or
3858  * atomicity of device memory accesses. The recommended practice for writing
3859  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3860  * alt_write_word() functions.
3861  *
3862  * The struct declaration for register ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE.
3863  */
3864 struct ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_s
3865 {
3866  const uint32_t value : 16; /* ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE */
3867  uint32_t : 16; /* *UNDEFINED* */
3868 };
3869 
3870 /* The typedef declaration for register ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE. */
3871 typedef volatile struct ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_s ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_t;
3872 #endif /* __ASSEMBLY__ */
3873 
3874 /* The byte offset of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE register from the beginning of the component. */
3875 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_OFST 0x50
3876 
3877 /*
3878  * Register : logical_page_spare_size
3879  *
3880  * Logical page data area size in bytes
3881  *
3882  * Register Layout
3883  *
3884  * Bits | Access | Reset | Description
3885  * :--------|:-------|:------|:---------------------------------------------
3886  * [15:0] | R | 0x0 | ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE
3887  * [31:16] | ??? | 0x0 | *UNDEFINED*
3888  *
3889  */
3890 /*
3891  * Field : value
3892  *
3893  * Logical page spare area size in bytes. If multiple devices are connected on a
3894  * single chip select, physical page spare size will be multiplied by the number of
3895  * devices to arrive at logical page size.
3896  *
3897  * Field Access Macros:
3898  *
3899  */
3900 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field. */
3901 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_LSB 0
3902 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field. */
3903 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_MSB 15
3904 /* The width in bits of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field. */
3905 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_WIDTH 16
3906 /* The mask used to set the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field value. */
3907 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_SET_MSK 0x0000ffff
3908 /* The mask used to clear the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field value. */
3909 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_CLR_MSK 0xffff0000
3910 /* The reset value of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field. */
3911 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_RESET 0x0
3912 /* Extracts the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE field value from a register. */
3913 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3914 /* Produces a ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field value suitable for setting the register. */
3915 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3916 
3917 #ifndef __ASSEMBLY__
3918 /*
3919  * WARNING: The C register and register group struct declarations are provided for
3920  * convenience and illustrative purposes. They should, however, be used with
3921  * caution as the C language standard provides no guarantees about the alignment or
3922  * atomicity of device memory accesses. The recommended practice for writing
3923  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3924  * alt_write_word() functions.
3925  *
3926  * The struct declaration for register ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE.
3927  */
3928 struct ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_s
3929 {
3930  const uint32_t value : 16; /* ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE */
3931  uint32_t : 16; /* *UNDEFINED* */
3932 };
3933 
3934 /* The typedef declaration for register ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE. */
3935 typedef volatile struct ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_s ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_t;
3936 #endif /* __ASSEMBLY__ */
3937 
3938 /* The byte offset of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE register from the beginning of the component. */
3939 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_OFST 0x60
3940 
3941 /*
3942  * Register : revision
3943  *
3944  * Controller revision number
3945  *
3946  * Register Layout
3947  *
3948  * Bits | Access | Reset | Description
3949  * :--------|:-------|:------|:------------------------------
3950  * [15:0] | R | 0x5 | ALT_NAND_PARAM_REVISION_VALUE
3951  * [31:16] | ??? | 0x0 | *UNDEFINED*
3952  *
3953  */
3954 /*
3955  * Field : value
3956  *
3957  * Controller revision number
3958  *
3959  * Field Access Macros:
3960  *
3961  */
3962 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_REVISION_VALUE register field. */
3963 #define ALT_NAND_PARAM_REVISION_VALUE_LSB 0
3964 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_REVISION_VALUE register field. */
3965 #define ALT_NAND_PARAM_REVISION_VALUE_MSB 15
3966 /* The width in bits of the ALT_NAND_PARAM_REVISION_VALUE register field. */
3967 #define ALT_NAND_PARAM_REVISION_VALUE_WIDTH 16
3968 /* The mask used to set the ALT_NAND_PARAM_REVISION_VALUE register field value. */
3969 #define ALT_NAND_PARAM_REVISION_VALUE_SET_MSK 0x0000ffff
3970 /* The mask used to clear the ALT_NAND_PARAM_REVISION_VALUE register field value. */
3971 #define ALT_NAND_PARAM_REVISION_VALUE_CLR_MSK 0xffff0000
3972 /* The reset value of the ALT_NAND_PARAM_REVISION_VALUE register field. */
3973 #define ALT_NAND_PARAM_REVISION_VALUE_RESET 0x5
3974 /* Extracts the ALT_NAND_PARAM_REVISION_VALUE field value from a register. */
3975 #define ALT_NAND_PARAM_REVISION_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3976 /* Produces a ALT_NAND_PARAM_REVISION_VALUE register field value suitable for setting the register. */
3977 #define ALT_NAND_PARAM_REVISION_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3978 
3979 #ifndef __ASSEMBLY__
3980 /*
3981  * WARNING: The C register and register group struct declarations are provided for
3982  * convenience and illustrative purposes. They should, however, be used with
3983  * caution as the C language standard provides no guarantees about the alignment or
3984  * atomicity of device memory accesses. The recommended practice for writing
3985  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3986  * alt_write_word() functions.
3987  *
3988  * The struct declaration for register ALT_NAND_PARAM_REVISION.
3989  */
3990 struct ALT_NAND_PARAM_REVISION_s
3991 {
3992  const uint32_t value : 16; /* ALT_NAND_PARAM_REVISION_VALUE */
3993  uint32_t : 16; /* *UNDEFINED* */
3994 };
3995 
3996 /* The typedef declaration for register ALT_NAND_PARAM_REVISION. */
3997 typedef volatile struct ALT_NAND_PARAM_REVISION_s ALT_NAND_PARAM_REVISION_t;
3998 #endif /* __ASSEMBLY__ */
3999 
4000 /* The byte offset of the ALT_NAND_PARAM_REVISION register from the beginning of the component. */
4001 #define ALT_NAND_PARAM_REVISION_OFST 0x70
4002 
4003 /*
4004  * Register : onfi_device_features
4005  *
4006  * Features supported by the connected ONFI device
4007  *
4008  * Register Layout
4009  *
4010  * Bits | Access | Reset | Description
4011  * :--------|:-------|:------|:---------------------------------------
4012  * [15:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE
4013  * [31:16] | ??? | 0x0 | *UNDEFINED*
4014  *
4015  */
4016 /*
4017  * Field : value
4018  *
4019  * The values in the field should be interpreted as follows[list] [*]Bit 0 -
4020  * Supports 16 bit data bus width. [*]Bit 1 - Supports multiple LUN operations.
4021  * [*]Bit 2 - Supports non-sequential page programming. [*]Bit 3 - Supports
4022  * interleaved program and erase operations. [*]Bit 4 - Supports odd to even page
4023  * copyback. [*]Bit 5 - Supports source synchronous. [*]Bit 6 - Supports
4024  * interleaved read operations. [*]Bit 7 - Supports extended parameter page. [*]Bit
4025  * 8 - Supports program page register clear enhancement. [*]Bit 9-15 -
4026  * Reserved.[/list]
4027  *
4028  * Field Access Macros:
4029  *
4030  */
4031 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE register field. */
4032 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_LSB 0
4033 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE register field. */
4034 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_MSB 15
4035 /* The width in bits of the ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE register field. */
4036 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_WIDTH 16
4037 /* The mask used to set the ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE register field value. */
4038 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_SET_MSK 0x0000ffff
4039 /* The mask used to clear the ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE register field value. */
4040 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_CLR_MSK 0xffff0000
4041 /* The reset value of the ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE register field. */
4042 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_RESET 0x0
4043 /* Extracts the ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE field value from a register. */
4044 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4045 /* Produces a ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE register field value suitable for setting the register. */
4046 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4047 
4048 #ifndef __ASSEMBLY__
4049 /*
4050  * WARNING: The C register and register group struct declarations are provided for
4051  * convenience and illustrative purposes. They should, however, be used with
4052  * caution as the C language standard provides no guarantees about the alignment or
4053  * atomicity of device memory accesses. The recommended practice for writing
4054  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4055  * alt_write_word() functions.
4056  *
4057  * The struct declaration for register ALT_NAND_PARAM_ONFI_DEV_FEATURES.
4058  */
4059 struct ALT_NAND_PARAM_ONFI_DEV_FEATURES_s
4060 {
4061  const uint32_t value : 16; /* ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE */
4062  uint32_t : 16; /* *UNDEFINED* */
4063 };
4064 
4065 /* The typedef declaration for register ALT_NAND_PARAM_ONFI_DEV_FEATURES. */
4066 typedef volatile struct ALT_NAND_PARAM_ONFI_DEV_FEATURES_s ALT_NAND_PARAM_ONFI_DEV_FEATURES_t;
4067 #endif /* __ASSEMBLY__ */
4068 
4069 /* The byte offset of the ALT_NAND_PARAM_ONFI_DEV_FEATURES register from the beginning of the component. */
4070 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_OFST 0x80
4071 
4072 /*
4073  * Register : onfi_optional_commands
4074  *
4075  * Optional commands supported by the connected ONFI device
4076  *
4077  * Register Layout
4078  *
4079  * Bits | Access | Reset | Description
4080  * :--------|:-------|:------|:----------------------------------------
4081  * [15:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE
4082  * [31:16] | ??? | 0x0 | *UNDEFINED*
4083  *
4084  */
4085 /*
4086  * Field : value
4087  *
4088  * The values in the field should be interpreted as follows[list] [*]Bit 0 -
4089  * Supports page cache program command. [*]Bit 1 - Supports read cache commands.
4090  * [*]Bit 2 - Supports get and set features. [*]Bit 3 - Supports read status
4091  * enhanced commands. [*]Bit 4 - Supports copyback. [*]Bit 5 - Supports Read Unique
4092  * Id. [*]Bit 6 - Supports Change Read Column Enhanced. [*]Bit 7 - Supports change
4093  * row address. [*]Bit 8 - Supports Change small data move. [*]Bit 9 - Supports
4094  * RESET Lun. [*]Bit 10-15 - Reserved.[/list]
4095  *
4096  * Field Access Macros:
4097  *
4098  */
4099 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE register field. */
4100 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_LSB 0
4101 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE register field. */
4102 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_MSB 15
4103 /* The width in bits of the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE register field. */
4104 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_WIDTH 16
4105 /* The mask used to set the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE register field value. */
4106 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_SET_MSK 0x0000ffff
4107 /* The mask used to clear the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE register field value. */
4108 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_CLR_MSK 0xffff0000
4109 /* The reset value of the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE register field. */
4110 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_RESET 0x0
4111 /* Extracts the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE field value from a register. */
4112 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4113 /* Produces a ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE register field value suitable for setting the register. */
4114 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4115 
4116 #ifndef __ASSEMBLY__
4117 /*
4118  * WARNING: The C register and register group struct declarations are provided for
4119  * convenience and illustrative purposes. They should, however, be used with
4120  * caution as the C language standard provides no guarantees about the alignment or
4121  * atomicity of device memory accesses. The recommended practice for writing
4122  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4123  * alt_write_word() functions.
4124  *
4125  * The struct declaration for register ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS.
4126  */
4127 struct ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_s
4128 {
4129  const uint32_t value : 16; /* ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE */
4130  uint32_t : 16; /* *UNDEFINED* */
4131 };
4132 
4133 /* The typedef declaration for register ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS. */
4134 typedef volatile struct ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_s ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_t;
4135 #endif /* __ASSEMBLY__ */
4136 
4137 /* The byte offset of the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS register from the beginning of the component. */
4138 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_OFST 0x90
4139 
4140 /*
4141  * Register : onfi_timing_mode
4142  *
4143  * Asynchronous Timing modes supported by the connected ONFI device
4144  *
4145  * Register Layout
4146  *
4147  * Bits | Access | Reset | Description
4148  * :-------|:-------|:------|:-------------------------------------
4149  * [5:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE
4150  * [31:6] | ??? | 0x0 | *UNDEFINED*
4151  *
4152  */
4153 /*
4154  * Field : value
4155  *
4156  * The values in the field should be interpreted as follows[list] [*]Bit 0 -
4157  * Supports Timing mode 0. [*]Bit 1 - Supports Timing mode 1. [*]Bit 2 - Supports
4158  * Timing mode 2. [*]Bit 3 - Supports Timing mode 3. [*]Bit 4 - Supports Timing
4159  * mode 4. [*]Bit 5 - Supports Timing mode 5.[/list]
4160  *
4161  * Field Access Macros:
4162  *
4163  */
4164 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field. */
4165 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_LSB 0
4166 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field. */
4167 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_MSB 5
4168 /* The width in bits of the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field. */
4169 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_WIDTH 6
4170 /* The mask used to set the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field value. */
4171 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_SET_MSK 0x0000003f
4172 /* The mask used to clear the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field value. */
4173 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_CLR_MSK 0xffffffc0
4174 /* The reset value of the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field. */
4175 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_RESET 0x0
4176 /* Extracts the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE field value from a register. */
4177 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
4178 /* Produces a ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field value suitable for setting the register. */
4179 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_SET(value) (((value) << 0) & 0x0000003f)
4180 
4181 #ifndef __ASSEMBLY__
4182 /*
4183  * WARNING: The C register and register group struct declarations are provided for
4184  * convenience and illustrative purposes. They should, however, be used with
4185  * caution as the C language standard provides no guarantees about the alignment or
4186  * atomicity of device memory accesses. The recommended practice for writing
4187  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4188  * alt_write_word() functions.
4189  *
4190  * The struct declaration for register ALT_NAND_PARAM_ONFI_TIMING_MOD.
4191  */
4192 struct ALT_NAND_PARAM_ONFI_TIMING_MOD_s
4193 {
4194  const uint32_t value : 6; /* ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE */
4195  uint32_t : 26; /* *UNDEFINED* */
4196 };
4197 
4198 /* The typedef declaration for register ALT_NAND_PARAM_ONFI_TIMING_MOD. */
4199 typedef volatile struct ALT_NAND_PARAM_ONFI_TIMING_MOD_s ALT_NAND_PARAM_ONFI_TIMING_MOD_t;
4200 #endif /* __ASSEMBLY__ */
4201 
4202 /* The byte offset of the ALT_NAND_PARAM_ONFI_TIMING_MOD register from the beginning of the component. */
4203 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_OFST 0xa0
4204 
4205 /*
4206  * Register : onfi_pgm_cache_timing_mode
4207  *
4208  * Asynchronous Program Cache Timing modes supported by the connected ONFI device
4209  *
4210  * Register Layout
4211  *
4212  * Bits | Access | Reset | Description
4213  * :-------|:-------|:------|:-----------------------------------------------
4214  * [5:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE
4215  * [31:6] | ??? | 0x0 | *UNDEFINED*
4216  *
4217  */
4218 /*
4219  * Field : value
4220  *
4221  * The values in the field should be interpreted as follows[list] [*]Bit 0 -
4222  * Supports Timing mode 0. [*]Bit 1 - Supports Timing mode 1. [*]Bit 2 - Supports
4223  * Timing mode 2. [*]Bit 3 - Supports Timing mode 3. [*]Bit 4 - Supports Timing
4224  * mode 4. [*]Bit 5 - Supports Timing mode 5.[/list]
4225  *
4226  * Field Access Macros:
4227  *
4228  */
4229 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE register field. */
4230 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_LSB 0
4231 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE register field. */
4232 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_MSB 5
4233 /* The width in bits of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE register field. */
4234 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_WIDTH 6
4235 /* The mask used to set the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE register field value. */
4236 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_SET_MSK 0x0000003f
4237 /* The mask used to clear the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE register field value. */
4238 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_CLR_MSK 0xffffffc0
4239 /* The reset value of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE register field. */
4240 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_RESET 0x0
4241 /* Extracts the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE field value from a register. */
4242 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
4243 /* Produces a ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE register field value suitable for setting the register. */
4244 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_SET(value) (((value) << 0) & 0x0000003f)
4245 
4246 #ifndef __ASSEMBLY__
4247 /*
4248  * WARNING: The C register and register group struct declarations are provided for
4249  * convenience and illustrative purposes. They should, however, be used with
4250  * caution as the C language standard provides no guarantees about the alignment or
4251  * atomicity of device memory accesses. The recommended practice for writing
4252  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4253  * alt_write_word() functions.
4254  *
4255  * The struct declaration for register ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD.
4256  */
4257 struct ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_s
4258 {
4259  const uint32_t value : 6; /* ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE */
4260  uint32_t : 26; /* *UNDEFINED* */
4261 };
4262 
4263 /* The typedef declaration for register ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD. */
4264 typedef volatile struct ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_s ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_t;
4265 #endif /* __ASSEMBLY__ */
4266 
4267 /* The byte offset of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD register from the beginning of the component. */
4268 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_OFST 0xb0
4269 
4270 /*
4271  * Register : onfi_device_no_of_luns
4272  *
4273  * Indicates if the device is an ONFI compliant device and the number of LUNS
4274  * present in the device
4275  *
4276  * Register Layout
4277  *
4278  * Bits | Access | Reset | Description
4279  * :-------|:-------|:------|:-----------------------------------------------
4280  * [7:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS
4281  * [8] | RW | 0x0 | ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE
4282  * [31:9] | ??? | 0x0 | *UNDEFINED*
4283  *
4284  */
4285 /*
4286  * Field : no_of_luns
4287  *
4288  * Indicates the number of LUNS present in the device
4289  *
4290  * Field Access Macros:
4291  *
4292  */
4293 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS register field. */
4294 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_LSB 0
4295 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS register field. */
4296 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_MSB 7
4297 /* The width in bits of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS register field. */
4298 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_WIDTH 8
4299 /* The mask used to set the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS register field value. */
4300 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_SET_MSK 0x000000ff
4301 /* The mask used to clear the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS register field value. */
4302 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_CLR_MSK 0xffffff00
4303 /* The reset value of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS register field. */
4304 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_RESET 0x0
4305 /* Extracts the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS field value from a register. */
4306 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_GET(value) (((value) & 0x000000ff) >> 0)
4307 /* Produces a ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS register field value suitable for setting the register. */
4308 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_SET(value) (((value) << 0) & 0x000000ff)
4309 
4310 /*
4311  * Field : onfi_device
4312  *
4313  * Indicates if the device is an ONFI compliant device.[list] [*]0 - Non-ONFI
4314  * compliant device [*]1 - ONFI compliant device[/list]
4315  *
4316  * Field Access Macros:
4317  *
4318  */
4319 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE register field. */
4320 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_LSB 8
4321 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE register field. */
4322 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_MSB 8
4323 /* The width in bits of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE register field. */
4324 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_WIDTH 1
4325 /* The mask used to set the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE register field value. */
4326 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_SET_MSK 0x00000100
4327 /* The mask used to clear the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE register field value. */
4328 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_CLR_MSK 0xfffffeff
4329 /* The reset value of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE register field. */
4330 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_RESET 0x0
4331 /* Extracts the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE field value from a register. */
4332 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_GET(value) (((value) & 0x00000100) >> 8)
4333 /* Produces a ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE register field value suitable for setting the register. */
4334 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_SET(value) (((value) << 8) & 0x00000100)
4335 
4336 #ifndef __ASSEMBLY__
4337 /*
4338  * WARNING: The C register and register group struct declarations are provided for
4339  * convenience and illustrative purposes. They should, however, be used with
4340  * caution as the C language standard provides no guarantees about the alignment or
4341  * atomicity of device memory accesses. The recommended practice for writing
4342  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4343  * alt_write_word() functions.
4344  *
4345  * The struct declaration for register ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS.
4346  */
4347 struct ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_s
4348 {
4349  const uint32_t no_of_luns : 8; /* ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS */
4350  uint32_t onfi_device : 1; /* ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE */
4351  uint32_t : 23; /* *UNDEFINED* */
4352 };
4353 
4354 /* The typedef declaration for register ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS. */
4355 typedef volatile struct ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_s ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_t;
4356 #endif /* __ASSEMBLY__ */
4357 
4358 /* The byte offset of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS register from the beginning of the component. */
4359 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_OFST 0xc0
4360 
4361 /*
4362  * Register : onfi_device_no_of_blocks_per_lun_l
4363  *
4364  * Lower bits of number of blocks per LUN present in the ONFI complaint device.
4365  *
4366  * Register Layout
4367  *
4368  * Bits | Access | Reset | Description
4369  * :--------|:-------|:------|:---------------------------------------------
4370  * [15:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE
4371  * [31:16] | ??? | 0x0 | *UNDEFINED*
4372  *
4373  */
4374 /*
4375  * Field : value
4376  *
4377  * Indicates the lower bits of number of blocks per LUN present in the ONFI
4378  * complaint device.
4379  *
4380  * Field Access Macros:
4381  *
4382  */
4383 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE register field. */
4384 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_LSB 0
4385 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE register field. */
4386 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_MSB 15
4387 /* The width in bits of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE register field. */
4388 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_WIDTH 16
4389 /* The mask used to set the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE register field value. */
4390 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_SET_MSK 0x0000ffff
4391 /* The mask used to clear the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE register field value. */
4392 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_CLR_MSK 0xffff0000
4393 /* The reset value of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE register field. */
4394 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_RESET 0x0
4395 /* Extracts the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE field value from a register. */
4396 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4397 /* Produces a ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE register field value suitable for setting the register. */
4398 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4399 
4400 #ifndef __ASSEMBLY__
4401 /*
4402  * WARNING: The C register and register group struct declarations are provided for
4403  * convenience and illustrative purposes. They should, however, be used with
4404  * caution as the C language standard provides no guarantees about the alignment or
4405  * atomicity of device memory accesses. The recommended practice for writing
4406  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4407  * alt_write_word() functions.
4408  *
4409  * The struct declaration for register ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L.
4410  */
4411 struct ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_s
4412 {
4413  const uint32_t value : 16; /* ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE */
4414  uint32_t : 16; /* *UNDEFINED* */
4415 };
4416 
4417 /* The typedef declaration for register ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L. */
4418 typedef volatile struct ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_s ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_t;
4419 #endif /* __ASSEMBLY__ */
4420 
4421 /* The byte offset of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L register from the beginning of the component. */
4422 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_OFST 0xd0
4423 
4424 /*
4425  * Register : onfi_device_no_of_blocks_per_lun_u
4426  *
4427  * Upper bits of number of blocks per LUN present in the ONFI complaint device.
4428  *
4429  * Register Layout
4430  *
4431  * Bits | Access | Reset | Description
4432  * :--------|:-------|:------|:---------------------------------------------
4433  * [15:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE
4434  * [31:16] | ??? | 0x0 | *UNDEFINED*
4435  *
4436  */
4437 /*
4438  * Field : value
4439  *
4440  * Indicates the upper bits of number of blocks per LUN present in the ONFI
4441  * complaint device.
4442  *
4443  * Field Access Macros:
4444  *
4445  */
4446 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE register field. */
4447 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_LSB 0
4448 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE register field. */
4449 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_MSB 15
4450 /* The width in bits of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE register field. */
4451 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_WIDTH 16
4452 /* The mask used to set the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE register field value. */
4453 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_SET_MSK 0x0000ffff
4454 /* The mask used to clear the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE register field value. */
4455 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_CLR_MSK 0xffff0000
4456 /* The reset value of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE register field. */
4457 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_RESET 0x0
4458 /* Extracts the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE field value from a register. */
4459 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4460 /* Produces a ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE register field value suitable for setting the register. */
4461 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4462 
4463 #ifndef __ASSEMBLY__
4464 /*
4465  * WARNING: The C register and register group struct declarations are provided for
4466  * convenience and illustrative purposes. They should, however, be used with
4467  * caution as the C language standard provides no guarantees about the alignment or
4468  * atomicity of device memory accesses. The recommended practice for writing
4469  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4470  * alt_write_word() functions.
4471  *
4472  * The struct declaration for register ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U.
4473  */
4474 struct ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_s
4475 {
4476  const uint32_t value : 16; /* ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE */
4477  uint32_t : 16; /* *UNDEFINED* */
4478 };
4479 
4480 /* The typedef declaration for register ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U. */
4481 typedef volatile struct ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_s ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_t;
4482 #endif /* __ASSEMBLY__ */
4483 
4484 /* The byte offset of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U register from the beginning of the component. */
4485 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_OFST 0xe0
4486 
4487 /*
4488  * Register : features
4489  *
4490  * Shows Available hardware features or attributes
4491  *
4492  * Register Layout
4493  *
4494  * Bits | Access | Reset | Description
4495  * :--------|:-------|:------|:--------------------------------------
4496  * [1:0] | R | 0x1 | ALT_NAND_PARAM_FEATURES_N_BANKS
4497  * [5:2] | ??? | 0x0 | *UNDEFINED*
4498  * [6] | R | 0x1 | ALT_NAND_PARAM_FEATURES_DMA
4499  * [7] | R | 0x0 | ALT_NAND_PARAM_FEATURES_CMD_DMA
4500  * [8] | R | 0x0 | ALT_NAND_PARAM_FEATURES_PARTITION
4501  * [9] | R | 0x0 | ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND
4502  * [10] | R | 0x0 | ALT_NAND_PARAM_FEATURES_GPREG
4503  * [11] | R | 0x1 | ALT_NAND_PARAM_FEATURES_INDEX_ADDR
4504  * [12] | R | 0x0 | ALT_NAND_PARAM_FEATURES_DFI_INTF
4505  * [13] | R | 0x0 | ALT_NAND_PARAM_FEATURES_LBA
4506  * [31:14] | ??? | 0x0 | *UNDEFINED*
4507  *
4508  */
4509 /*
4510  * Field : n_banks
4511  *
4512  * Maximum number of banks supported by hardware. This is an encoded value.
4513  * [list][*]0 - Two banks [*]1 - Four banks [*]2 - Eight banks [*]3 - Sixteen
4514  * banks[/list]
4515  *
4516  * Field Access Macros:
4517  *
4518  */
4519 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_N_BANKS register field. */
4520 #define ALT_NAND_PARAM_FEATURES_N_BANKS_LSB 0
4521 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_N_BANKS register field. */
4522 #define ALT_NAND_PARAM_FEATURES_N_BANKS_MSB 1
4523 /* The width in bits of the ALT_NAND_PARAM_FEATURES_N_BANKS register field. */
4524 #define ALT_NAND_PARAM_FEATURES_N_BANKS_WIDTH 2
4525 /* The mask used to set the ALT_NAND_PARAM_FEATURES_N_BANKS register field value. */
4526 #define ALT_NAND_PARAM_FEATURES_N_BANKS_SET_MSK 0x00000003
4527 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_N_BANKS register field value. */
4528 #define ALT_NAND_PARAM_FEATURES_N_BANKS_CLR_MSK 0xfffffffc
4529 /* The reset value of the ALT_NAND_PARAM_FEATURES_N_BANKS register field. */
4530 #define ALT_NAND_PARAM_FEATURES_N_BANKS_RESET 0x1
4531 /* Extracts the ALT_NAND_PARAM_FEATURES_N_BANKS field value from a register. */
4532 #define ALT_NAND_PARAM_FEATURES_N_BANKS_GET(value) (((value) & 0x00000003) >> 0)
4533 /* Produces a ALT_NAND_PARAM_FEATURES_N_BANKS register field value suitable for setting the register. */
4534 #define ALT_NAND_PARAM_FEATURES_N_BANKS_SET(value) (((value) << 0) & 0x00000003)
4535 
4536 /*
4537  * Field : dma
4538  *
4539  * if set, DATA-DMA is present in hardware.
4540  *
4541  * Field Access Macros:
4542  *
4543  */
4544 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_DMA register field. */
4545 #define ALT_NAND_PARAM_FEATURES_DMA_LSB 6
4546 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_DMA register field. */
4547 #define ALT_NAND_PARAM_FEATURES_DMA_MSB 6
4548 /* The width in bits of the ALT_NAND_PARAM_FEATURES_DMA register field. */
4549 #define ALT_NAND_PARAM_FEATURES_DMA_WIDTH 1
4550 /* The mask used to set the ALT_NAND_PARAM_FEATURES_DMA register field value. */
4551 #define ALT_NAND_PARAM_FEATURES_DMA_SET_MSK 0x00000040
4552 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_DMA register field value. */
4553 #define ALT_NAND_PARAM_FEATURES_DMA_CLR_MSK 0xffffffbf
4554 /* The reset value of the ALT_NAND_PARAM_FEATURES_DMA register field. */
4555 #define ALT_NAND_PARAM_FEATURES_DMA_RESET 0x1
4556 /* Extracts the ALT_NAND_PARAM_FEATURES_DMA field value from a register. */
4557 #define ALT_NAND_PARAM_FEATURES_DMA_GET(value) (((value) & 0x00000040) >> 6)
4558 /* Produces a ALT_NAND_PARAM_FEATURES_DMA register field value suitable for setting the register. */
4559 #define ALT_NAND_PARAM_FEATURES_DMA_SET(value) (((value) << 6) & 0x00000040)
4560 
4561 /*
4562  * Field : cmd_dma
4563  *
4564  * Not implemented.
4565  *
4566  * Field Access Macros:
4567  *
4568  */
4569 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_CMD_DMA register field. */
4570 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_LSB 7
4571 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_CMD_DMA register field. */
4572 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_MSB 7
4573 /* The width in bits of the ALT_NAND_PARAM_FEATURES_CMD_DMA register field. */
4574 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_WIDTH 1
4575 /* The mask used to set the ALT_NAND_PARAM_FEATURES_CMD_DMA register field value. */
4576 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_SET_MSK 0x00000080
4577 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_CMD_DMA register field value. */
4578 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_CLR_MSK 0xffffff7f
4579 /* The reset value of the ALT_NAND_PARAM_FEATURES_CMD_DMA register field. */
4580 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_RESET 0x0
4581 /* Extracts the ALT_NAND_PARAM_FEATURES_CMD_DMA field value from a register. */
4582 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_GET(value) (((value) & 0x00000080) >> 7)
4583 /* Produces a ALT_NAND_PARAM_FEATURES_CMD_DMA register field value suitable for setting the register. */
4584 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_SET(value) (((value) << 7) & 0x00000080)
4585 
4586 /*
4587  * Field : partition
4588  *
4589  * if set, Partition logic is present in hardware.
4590  *
4591  * Field Access Macros:
4592  *
4593  */
4594 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_PARTITION register field. */
4595 #define ALT_NAND_PARAM_FEATURES_PARTITION_LSB 8
4596 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_PARTITION register field. */
4597 #define ALT_NAND_PARAM_FEATURES_PARTITION_MSB 8
4598 /* The width in bits of the ALT_NAND_PARAM_FEATURES_PARTITION register field. */
4599 #define ALT_NAND_PARAM_FEATURES_PARTITION_WIDTH 1
4600 /* The mask used to set the ALT_NAND_PARAM_FEATURES_PARTITION register field value. */
4601 #define ALT_NAND_PARAM_FEATURES_PARTITION_SET_MSK 0x00000100
4602 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_PARTITION register field value. */
4603 #define ALT_NAND_PARAM_FEATURES_PARTITION_CLR_MSK 0xfffffeff
4604 /* The reset value of the ALT_NAND_PARAM_FEATURES_PARTITION register field. */
4605 #define ALT_NAND_PARAM_FEATURES_PARTITION_RESET 0x0
4606 /* Extracts the ALT_NAND_PARAM_FEATURES_PARTITION field value from a register. */
4607 #define ALT_NAND_PARAM_FEATURES_PARTITION_GET(value) (((value) & 0x00000100) >> 8)
4608 /* Produces a ALT_NAND_PARAM_FEATURES_PARTITION register field value suitable for setting the register. */
4609 #define ALT_NAND_PARAM_FEATURES_PARTITION_SET(value) (((value) << 8) & 0x00000100)
4610 
4611 /*
4612  * Field : xdma_sideband
4613  *
4614  * if set, Side band DMA signals are present in hardware.
4615  *
4616  * Field Access Macros:
4617  *
4618  */
4619 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field. */
4620 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_LSB 9
4621 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field. */
4622 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_MSB 9
4623 /* The width in bits of the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field. */
4624 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_WIDTH 1
4625 /* The mask used to set the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field value. */
4626 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_SET_MSK 0x00000200
4627 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field value. */
4628 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_CLR_MSK 0xfffffdff
4629 /* The reset value of the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field. */
4630 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_RESET 0x0
4631 /* Extracts the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND field value from a register. */
4632 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_GET(value) (((value) & 0x00000200) >> 9)
4633 /* Produces a ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field value suitable for setting the register. */
4634 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_SET(value) (((value) << 9) & 0x00000200)
4635 
4636 /*
4637  * Field : gpreg
4638  *
4639  * if set, General purpose registers are is present in hardware.
4640  *
4641  * Field Access Macros:
4642  *
4643  */
4644 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_GPREG register field. */
4645 #define ALT_NAND_PARAM_FEATURES_GPREG_LSB 10
4646 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_GPREG register field. */
4647 #define ALT_NAND_PARAM_FEATURES_GPREG_MSB 10
4648 /* The width in bits of the ALT_NAND_PARAM_FEATURES_GPREG register field. */
4649 #define ALT_NAND_PARAM_FEATURES_GPREG_WIDTH 1
4650 /* The mask used to set the ALT_NAND_PARAM_FEATURES_GPREG register field value. */
4651 #define ALT_NAND_PARAM_FEATURES_GPREG_SET_MSK 0x00000400
4652 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_GPREG register field value. */
4653 #define ALT_NAND_PARAM_FEATURES_GPREG_CLR_MSK 0xfffffbff
4654 /* The reset value of the ALT_NAND_PARAM_FEATURES_GPREG register field. */
4655 #define ALT_NAND_PARAM_FEATURES_GPREG_RESET 0x0
4656 /* Extracts the ALT_NAND_PARAM_FEATURES_GPREG field value from a register. */
4657 #define ALT_NAND_PARAM_FEATURES_GPREG_GET(value) (((value) & 0x00000400) >> 10)
4658 /* Produces a ALT_NAND_PARAM_FEATURES_GPREG register field value suitable for setting the register. */
4659 #define ALT_NAND_PARAM_FEATURES_GPREG_SET(value) (((value) << 10) & 0x00000400)
4660 
4661 /*
4662  * Field : index_addr
4663  *
4664  * if set, hardware support only Indexed addressing.
4665  *
4666  * Field Access Macros:
4667  *
4668  */
4669 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field. */
4670 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_LSB 11
4671 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field. */
4672 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_MSB 11
4673 /* The width in bits of the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field. */
4674 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_WIDTH 1
4675 /* The mask used to set the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field value. */
4676 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_SET_MSK 0x00000800
4677 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field value. */
4678 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_CLR_MSK 0xfffff7ff
4679 /* The reset value of the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field. */
4680 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_RESET 0x1
4681 /* Extracts the ALT_NAND_PARAM_FEATURES_INDEX_ADDR field value from a register. */
4682 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_GET(value) (((value) & 0x00000800) >> 11)
4683 /* Produces a ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field value suitable for setting the register. */
4684 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_SET(value) (((value) << 11) & 0x00000800)
4685 
4686 /*
4687  * Field : dfi_intf
4688  *
4689  * if set, hardware supports ONFI2.x synchronous interface.
4690  *
4691  * Field Access Macros:
4692  *
4693  */
4694 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_DFI_INTF register field. */
4695 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_LSB 12
4696 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_DFI_INTF register field. */
4697 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_MSB 12
4698 /* The width in bits of the ALT_NAND_PARAM_FEATURES_DFI_INTF register field. */
4699 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_WIDTH 1
4700 /* The mask used to set the ALT_NAND_PARAM_FEATURES_DFI_INTF register field value. */
4701 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_SET_MSK 0x00001000
4702 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_DFI_INTF register field value. */
4703 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_CLR_MSK 0xffffefff
4704 /* The reset value of the ALT_NAND_PARAM_FEATURES_DFI_INTF register field. */
4705 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_RESET 0x0
4706 /* Extracts the ALT_NAND_PARAM_FEATURES_DFI_INTF field value from a register. */
4707 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_GET(value) (((value) & 0x00001000) >> 12)
4708 /* Produces a ALT_NAND_PARAM_FEATURES_DFI_INTF register field value suitable for setting the register. */
4709 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_SET(value) (((value) << 12) & 0x00001000)
4710 
4711 /*
4712  * Field : lba
4713  *
4714  * if set, hardware supports Toshiba LBA devices.
4715  *
4716  * Field Access Macros:
4717  *
4718  */
4719 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_LBA register field. */
4720 #define ALT_NAND_PARAM_FEATURES_LBA_LSB 13
4721 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_LBA register field. */
4722 #define ALT_NAND_PARAM_FEATURES_LBA_MSB 13
4723 /* The width in bits of the ALT_NAND_PARAM_FEATURES_LBA register field. */
4724 #define ALT_NAND_PARAM_FEATURES_LBA_WIDTH 1
4725 /* The mask used to set the ALT_NAND_PARAM_FEATURES_LBA register field value. */
4726 #define ALT_NAND_PARAM_FEATURES_LBA_SET_MSK 0x00002000
4727 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_LBA register field value. */
4728 #define ALT_NAND_PARAM_FEATURES_LBA_CLR_MSK 0xffffdfff
4729 /* The reset value of the ALT_NAND_PARAM_FEATURES_LBA register field. */
4730 #define ALT_NAND_PARAM_FEATURES_LBA_RESET 0x0
4731 /* Extracts the ALT_NAND_PARAM_FEATURES_LBA field value from a register. */
4732 #define ALT_NAND_PARAM_FEATURES_LBA_GET(value) (((value) & 0x00002000) >> 13)
4733 /* Produces a ALT_NAND_PARAM_FEATURES_LBA register field value suitable for setting the register. */
4734 #define ALT_NAND_PARAM_FEATURES_LBA_SET(value) (((value) << 13) & 0x00002000)
4735 
4736 #ifndef __ASSEMBLY__
4737 /*
4738  * WARNING: The C register and register group struct declarations are provided for
4739  * convenience and illustrative purposes. They should, however, be used with
4740  * caution as the C language standard provides no guarantees about the alignment or
4741  * atomicity of device memory accesses. The recommended practice for writing
4742  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4743  * alt_write_word() functions.
4744  *
4745  * The struct declaration for register ALT_NAND_PARAM_FEATURES.
4746  */
4747 struct ALT_NAND_PARAM_FEATURES_s
4748 {
4749  const uint32_t n_banks : 2; /* ALT_NAND_PARAM_FEATURES_N_BANKS */
4750  uint32_t : 4; /* *UNDEFINED* */
4751  const uint32_t dma : 1; /* ALT_NAND_PARAM_FEATURES_DMA */
4752  const uint32_t cmd_dma : 1; /* ALT_NAND_PARAM_FEATURES_CMD_DMA */
4753  const uint32_t partition : 1; /* ALT_NAND_PARAM_FEATURES_PARTITION */
4754  const uint32_t xdma_sideband : 1; /* ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND */
4755  const uint32_t gpreg : 1; /* ALT_NAND_PARAM_FEATURES_GPREG */
4756  const uint32_t index_addr : 1; /* ALT_NAND_PARAM_FEATURES_INDEX_ADDR */
4757  const uint32_t dfi_intf : 1; /* ALT_NAND_PARAM_FEATURES_DFI_INTF */
4758  const uint32_t lba : 1; /* ALT_NAND_PARAM_FEATURES_LBA */
4759  uint32_t : 18; /* *UNDEFINED* */
4760 };
4761 
4762 /* The typedef declaration for register ALT_NAND_PARAM_FEATURES. */
4763 typedef volatile struct ALT_NAND_PARAM_FEATURES_s ALT_NAND_PARAM_FEATURES_t;
4764 #endif /* __ASSEMBLY__ */
4765 
4766 /* The byte offset of the ALT_NAND_PARAM_FEATURES register from the beginning of the component. */
4767 #define ALT_NAND_PARAM_FEATURES_OFST 0xf0
4768 
4769 #ifndef __ASSEMBLY__
4770 /*
4771  * WARNING: The C register and register group struct declarations are provided for
4772  * convenience and illustrative purposes. They should, however, be used with
4773  * caution as the C language standard provides no guarantees about the alignment or
4774  * atomicity of device memory accesses. The recommended practice for writing
4775  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4776  * alt_write_word() functions.
4777  *
4778  * The struct declaration for register group ALT_NAND_PARAM.
4779  */
4780 struct ALT_NAND_PARAM_s
4781 {
4782  ALT_NAND_PARAM_MANUFACTURER_ID_t manufacturer_id; /* ALT_NAND_PARAM_MANUFACTURER_ID */
4783  volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
4784  ALT_NAND_PARAM_DEVICE_ID_t device_id; /* ALT_NAND_PARAM_DEVICE_ID */
4785  volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
4786  ALT_NAND_PARAM_DEVICE_PARAM_0_t device_param_0; /* ALT_NAND_PARAM_DEVICE_PARAM_0 */
4787  volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
4788  ALT_NAND_PARAM_DEVICE_PARAM_1_t device_param_1; /* ALT_NAND_PARAM_DEVICE_PARAM_1 */
4789  volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
4790  ALT_NAND_PARAM_DEVICE_PARAM_2_t device_param_2; /* ALT_NAND_PARAM_DEVICE_PARAM_2 */
4791  volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
4792  ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_t logical_page_data_size; /* ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE */
4793  volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
4794  ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_t logical_page_spare_size; /* ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE */
4795  volatile uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */
4796  ALT_NAND_PARAM_REVISION_t revision; /* ALT_NAND_PARAM_REVISION */
4797  volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
4798  ALT_NAND_PARAM_ONFI_DEV_FEATURES_t onfi_device_features; /* ALT_NAND_PARAM_ONFI_DEV_FEATURES */
4799  volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
4800  ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_t onfi_optional_commands; /* ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS */
4801  volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
4802  ALT_NAND_PARAM_ONFI_TIMING_MOD_t onfi_timing_mode; /* ALT_NAND_PARAM_ONFI_TIMING_MOD */
4803  volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
4804  ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_t onfi_pgm_cache_timing_mode; /* ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD */
4805  volatile uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */
4806  ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_t onfi_device_no_of_luns; /* ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS */
4807  volatile uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */
4808  ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_t onfi_device_no_of_blocks_per_lun_l; /* ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L */
4809  volatile uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */
4810  ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_t onfi_device_no_of_blocks_per_lun_u; /* ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U */
4811  volatile uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */
4812  ALT_NAND_PARAM_FEATURES_t features; /* ALT_NAND_PARAM_FEATURES */
4813 };
4814 
4815 /* The typedef declaration for register group ALT_NAND_PARAM. */
4816 typedef volatile struct ALT_NAND_PARAM_s ALT_NAND_PARAM_t;
4817 /* The struct declaration for the raw register contents of register group ALT_NAND_PARAM. */
4818 struct ALT_NAND_PARAM_raw_s
4819 {
4820  volatile uint32_t manufacturer_id; /* ALT_NAND_PARAM_MANUFACTURER_ID */
4821  uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
4822  volatile uint32_t device_id; /* ALT_NAND_PARAM_DEVICE_ID */
4823  uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
4824  volatile uint32_t device_param_0; /* ALT_NAND_PARAM_DEVICE_PARAM_0 */
4825  uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
4826  volatile uint32_t device_param_1; /* ALT_NAND_PARAM_DEVICE_PARAM_1 */
4827  uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
4828  volatile uint32_t device_param_2; /* ALT_NAND_PARAM_DEVICE_PARAM_2 */
4829  uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
4830  volatile uint32_t logical_page_data_size; /* ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE */
4831  uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
4832  volatile uint32_t logical_page_spare_size; /* ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE */
4833  uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */
4834  volatile uint32_t revision; /* ALT_NAND_PARAM_REVISION */
4835  uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
4836  volatile uint32_t onfi_device_features; /* ALT_NAND_PARAM_ONFI_DEV_FEATURES */
4837  uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
4838  volatile uint32_t onfi_optional_commands; /* ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS */
4839  uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
4840  volatile uint32_t onfi_timing_mode; /* ALT_NAND_PARAM_ONFI_TIMING_MOD */
4841  uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
4842  volatile uint32_t onfi_pgm_cache_timing_mode; /* ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD */
4843  uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */
4844  volatile uint32_t onfi_device_no_of_luns; /* ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS */
4845  uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */
4846  volatile uint32_t onfi_device_no_of_blocks_per_lun_l; /* ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L */
4847  uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */
4848  volatile uint32_t onfi_device_no_of_blocks_per_lun_u; /* ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U */
4849  uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */
4850  volatile uint32_t features; /* ALT_NAND_PARAM_FEATURES */
4851 };
4852 
4853 /* The typedef declaration for the raw register contents of register group ALT_NAND_PARAM. */
4854 typedef volatile struct ALT_NAND_PARAM_raw_s ALT_NAND_PARAM_raw_t;
4855 #endif /* __ASSEMBLY__ */
4856 
4857 
4858 /*
4859  * Register Group : Interrupt and Status Registers - ALT_NAND_STAT
4860  * Interrupt and Status Registers
4861  *
4862  * Contains interrupt and status registers of controller accessible by software.
4863  *
4864  */
4865 /*
4866  * Register : transfer_mode
4867  *
4868  * Current data transfer mode is Main only, Spare only or Main+Spare. This
4869  * information is per bank.
4870  *
4871  * Register Layout
4872  *
4873  * Bits | Access | Reset | Description
4874  * :-------|:-------|:------|:-----------------------------
4875  * [1:0] | R | 0x0 | ALT_NAND_STAT_TFR_MOD_VALUE0
4876  * [3:2] | R | 0x0 | ALT_NAND_STAT_TFR_MOD_VALUE1
4877  * [5:4] | R | 0x0 | ALT_NAND_STAT_TFR_MOD_VALUE2
4878  * [7:6] | R | 0x0 | ALT_NAND_STAT_TFR_MOD_VALUE3
4879  * [31:8] | ??? | 0x0 | *UNDEFINED*
4880  *
4881  */
4882 /*
4883  * Field : value0
4884  *
4885  * [list][*]00 - Bank 0 is in Main mode [*]01 - Bank 0 is in Spare mode [*]10 -
4886  * Bank 0 is in Main+Spare mode[/list]
4887  *
4888  * Field Access Macros:
4889  *
4890  */
4891 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE0 register field. */
4892 #define ALT_NAND_STAT_TFR_MOD_VALUE0_LSB 0
4893 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE0 register field. */
4894 #define ALT_NAND_STAT_TFR_MOD_VALUE0_MSB 1
4895 /* The width in bits of the ALT_NAND_STAT_TFR_MOD_VALUE0 register field. */
4896 #define ALT_NAND_STAT_TFR_MOD_VALUE0_WIDTH 2
4897 /* The mask used to set the ALT_NAND_STAT_TFR_MOD_VALUE0 register field value. */
4898 #define ALT_NAND_STAT_TFR_MOD_VALUE0_SET_MSK 0x00000003
4899 /* The mask used to clear the ALT_NAND_STAT_TFR_MOD_VALUE0 register field value. */
4900 #define ALT_NAND_STAT_TFR_MOD_VALUE0_CLR_MSK 0xfffffffc
4901 /* The reset value of the ALT_NAND_STAT_TFR_MOD_VALUE0 register field. */
4902 #define ALT_NAND_STAT_TFR_MOD_VALUE0_RESET 0x0
4903 /* Extracts the ALT_NAND_STAT_TFR_MOD_VALUE0 field value from a register. */
4904 #define ALT_NAND_STAT_TFR_MOD_VALUE0_GET(value) (((value) & 0x00000003) >> 0)
4905 /* Produces a ALT_NAND_STAT_TFR_MOD_VALUE0 register field value suitable for setting the register. */
4906 #define ALT_NAND_STAT_TFR_MOD_VALUE0_SET(value) (((value) << 0) & 0x00000003)
4907 
4908 /*
4909  * Field : value1
4910  *
4911  * [list][*]00 - Bank 1 is in Main mode [*]01 - Bank 1 is in Spare mode [*]10 -
4912  * Bank 1 is in Main+Spare mode[/list]
4913  *
4914  * Field Access Macros:
4915  *
4916  */
4917 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE1 register field. */
4918 #define ALT_NAND_STAT_TFR_MOD_VALUE1_LSB 2
4919 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE1 register field. */
4920 #define ALT_NAND_STAT_TFR_MOD_VALUE1_MSB 3
4921 /* The width in bits of the ALT_NAND_STAT_TFR_MOD_VALUE1 register field. */
4922 #define ALT_NAND_STAT_TFR_MOD_VALUE1_WIDTH 2
4923 /* The mask used to set the ALT_NAND_STAT_TFR_MOD_VALUE1 register field value. */
4924 #define ALT_NAND_STAT_TFR_MOD_VALUE1_SET_MSK 0x0000000c
4925 /* The mask used to clear the ALT_NAND_STAT_TFR_MOD_VALUE1 register field value. */
4926 #define ALT_NAND_STAT_TFR_MOD_VALUE1_CLR_MSK 0xfffffff3
4927 /* The reset value of the ALT_NAND_STAT_TFR_MOD_VALUE1 register field. */
4928 #define ALT_NAND_STAT_TFR_MOD_VALUE1_RESET 0x0
4929 /* Extracts the ALT_NAND_STAT_TFR_MOD_VALUE1 field value from a register. */
4930 #define ALT_NAND_STAT_TFR_MOD_VALUE1_GET(value) (((value) & 0x0000000c) >> 2)
4931 /* Produces a ALT_NAND_STAT_TFR_MOD_VALUE1 register field value suitable for setting the register. */
4932 #define ALT_NAND_STAT_TFR_MOD_VALUE1_SET(value) (((value) << 2) & 0x0000000c)
4933 
4934 /*
4935  * Field : value2
4936  *
4937  * [list][*]00 - Bank 2 is in Main mode [*]01 - Bank 2 is in Spare mode [*]10 -
4938  * Bank 2 is in Main+Spare mode[/list]
4939  *
4940  * Field Access Macros:
4941  *
4942  */
4943 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE2 register field. */
4944 #define ALT_NAND_STAT_TFR_MOD_VALUE2_LSB 4
4945 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE2 register field. */
4946 #define ALT_NAND_STAT_TFR_MOD_VALUE2_MSB 5
4947 /* The width in bits of the ALT_NAND_STAT_TFR_MOD_VALUE2 register field. */
4948 #define ALT_NAND_STAT_TFR_MOD_VALUE2_WIDTH 2
4949 /* The mask used to set the ALT_NAND_STAT_TFR_MOD_VALUE2 register field value. */
4950 #define ALT_NAND_STAT_TFR_MOD_VALUE2_SET_MSK 0x00000030
4951 /* The mask used to clear the ALT_NAND_STAT_TFR_MOD_VALUE2 register field value. */
4952 #define ALT_NAND_STAT_TFR_MOD_VALUE2_CLR_MSK 0xffffffcf
4953 /* The reset value of the ALT_NAND_STAT_TFR_MOD_VALUE2 register field. */
4954 #define ALT_NAND_STAT_TFR_MOD_VALUE2_RESET 0x0
4955 /* Extracts the ALT_NAND_STAT_TFR_MOD_VALUE2 field value from a register. */
4956 #define ALT_NAND_STAT_TFR_MOD_VALUE2_GET(value) (((value) & 0x00000030) >> 4)
4957 /* Produces a ALT_NAND_STAT_TFR_MOD_VALUE2 register field value suitable for setting the register. */
4958 #define ALT_NAND_STAT_TFR_MOD_VALUE2_SET(value) (((value) << 4) & 0x00000030)
4959 
4960 /*
4961  * Field : value3
4962  *
4963  * [list][*]00 - Bank 3 is in Main mode [*]01 - Bank 3 is in Spare mode [*]10 -
4964  * Bank 3 is in Main+Spare mode[/list]
4965  *
4966  * Field Access Macros:
4967  *
4968  */
4969 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE3 register field. */
4970 #define ALT_NAND_STAT_TFR_MOD_VALUE3_LSB 6
4971 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE3 register field. */
4972 #define ALT_NAND_STAT_TFR_MOD_VALUE3_MSB 7
4973 /* The width in bits of the ALT_NAND_STAT_TFR_MOD_VALUE3 register field. */
4974 #define ALT_NAND_STAT_TFR_MOD_VALUE3_WIDTH 2
4975 /* The mask used to set the ALT_NAND_STAT_TFR_MOD_VALUE3 register field value. */
4976 #define ALT_NAND_STAT_TFR_MOD_VALUE3_SET_MSK 0x000000c0
4977 /* The mask used to clear the ALT_NAND_STAT_TFR_MOD_VALUE3 register field value. */
4978 #define ALT_NAND_STAT_TFR_MOD_VALUE3_CLR_MSK 0xffffff3f
4979 /* The reset value of the ALT_NAND_STAT_TFR_MOD_VALUE3 register field. */
4980 #define ALT_NAND_STAT_TFR_MOD_VALUE3_RESET 0x0
4981 /* Extracts the ALT_NAND_STAT_TFR_MOD_VALUE3 field value from a register. */
4982 #define ALT_NAND_STAT_TFR_MOD_VALUE3_GET(value) (((value) & 0x000000c0) >> 6)
4983 /* Produces a ALT_NAND_STAT_TFR_MOD_VALUE3 register field value suitable for setting the register. */
4984 #define ALT_NAND_STAT_TFR_MOD_VALUE3_SET(value) (((value) << 6) & 0x000000c0)
4985 
4986 #ifndef __ASSEMBLY__
4987 /*
4988  * WARNING: The C register and register group struct declarations are provided for
4989  * convenience and illustrative purposes. They should, however, be used with
4990  * caution as the C language standard provides no guarantees about the alignment or
4991  * atomicity of device memory accesses. The recommended practice for writing
4992  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4993  * alt_write_word() functions.
4994  *
4995  * The struct declaration for register ALT_NAND_STAT_TFR_MOD.
4996  */
4997 struct ALT_NAND_STAT_TFR_MOD_s
4998 {
4999  const uint32_t value0 : 2; /* ALT_NAND_STAT_TFR_MOD_VALUE0 */
5000  const uint32_t value1 : 2; /* ALT_NAND_STAT_TFR_MOD_VALUE1 */
5001  const uint32_t value2 : 2; /* ALT_NAND_STAT_TFR_MOD_VALUE2 */
5002  const uint32_t value3 : 2; /* ALT_NAND_STAT_TFR_MOD_VALUE3 */
5003  uint32_t : 24; /* *UNDEFINED* */
5004 };
5005 
5006 /* The typedef declaration for register ALT_NAND_STAT_TFR_MOD. */
5007 typedef volatile struct ALT_NAND_STAT_TFR_MOD_s ALT_NAND_STAT_TFR_MOD_t;
5008 #endif /* __ASSEMBLY__ */
5009 
5010 /* The byte offset of the ALT_NAND_STAT_TFR_MOD register from the beginning of the component. */
5011 #define ALT_NAND_STAT_TFR_MOD_OFST 0x0
5012 
5013 /*
5014  * Register : intr_status0
5015  *
5016  * Interrupt status register for bank 0
5017  *
5018  * Register Layout
5019  *
5020  * Bits | Access | Reset | Description
5021  * :--------|:-------|:------|:----------------------------------------------
5022  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR
5023  * [1] | ??? | 0x0 | *UNDEFINED*
5024  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP
5025  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_TIME_OUT
5026  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL
5027  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL
5028  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_LD_COMP
5029  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP
5030  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_ERASE_COMP
5031  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP
5032  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK
5033  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD
5034  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_INT_ACT
5035  * [13] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_RST_COMP
5036  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR
5037  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC
5038  * [31:16] | ??? | 0x0 | *UNDEFINED*
5039  *
5040  */
5041 /*
5042  * Field : ecc_uncor_err
5043  *
5044  * Ecc logic detected uncorrectable error while reading data from flash device.
5045  *
5046  * Field Access Macros:
5047  *
5048  */
5049 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR register field. */
5050 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_LSB 0
5051 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR register field. */
5052 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_MSB 0
5053 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR register field. */
5054 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_WIDTH 1
5055 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR register field value. */
5056 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_SET_MSK 0x00000001
5057 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR register field value. */
5058 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
5059 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR register field. */
5060 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_RESET 0x0
5061 /* Extracts the ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR field value from a register. */
5062 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
5063 /* Produces a ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR register field value suitable for setting the register. */
5064 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
5065 
5066 /*
5067  * Field : dma_cmd_comp
5068  *
5069  * Not implemented.
5070  *
5071  * Field Access Macros:
5072  *
5073  */
5074 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP register field. */
5075 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_LSB 2
5076 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP register field. */
5077 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_MSB 2
5078 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP register field. */
5079 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_WIDTH 1
5080 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP register field value. */
5081 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_SET_MSK 0x00000004
5082 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP register field value. */
5083 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_CLR_MSK 0xfffffffb
5084 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP register field. */
5085 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_RESET 0x0
5086 /* Extracts the ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP field value from a register. */
5087 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
5088 /* Produces a ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP register field value suitable for setting the register. */
5089 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
5090 
5091 /*
5092  * Field : time_out
5093  *
5094  * Watchdog timer has triggered in the controller due to one of the reasons like
5095  * device not responding or controller state machine did not get back to idle
5096  *
5097  * Field Access Macros:
5098  *
5099  */
5100 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_TIME_OUT register field. */
5101 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_LSB 3
5102 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_TIME_OUT register field. */
5103 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_MSB 3
5104 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_TIME_OUT register field. */
5105 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_WIDTH 1
5106 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_TIME_OUT register field value. */
5107 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_SET_MSK 0x00000008
5108 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_TIME_OUT register field value. */
5109 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_CLR_MSK 0xfffffff7
5110 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_TIME_OUT register field. */
5111 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_RESET 0x0
5112 /* Extracts the ALT_NAND_STAT_INTR_STAT0_TIME_OUT field value from a register. */
5113 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
5114 /* Produces a ALT_NAND_STAT_INTR_STAT0_TIME_OUT register field value suitable for setting the register. */
5115 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
5116 
5117 /*
5118  * Field : program_fail
5119  *
5120  * Program failure occurred in the device on issuance of a program command.
5121  * err_block_addr and err_page_addr contain the block address and page address that
5122  * failed program operation.
5123  *
5124  * Field Access Macros:
5125  *
5126  */
5127 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL register field. */
5128 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_LSB 4
5129 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL register field. */
5130 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_MSB 4
5131 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL register field. */
5132 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_WIDTH 1
5133 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL register field value. */
5134 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_SET_MSK 0x00000010
5135 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL register field value. */
5136 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_CLR_MSK 0xffffffef
5137 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL register field. */
5138 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_RESET 0x0
5139 /* Extracts the ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL field value from a register. */
5140 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
5141 /* Produces a ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL register field value suitable for setting the register. */
5142 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
5143 
5144 /*
5145  * Field : erase_fail
5146  *
5147  * Erase failure occurred in the device on issuance of a erase command.
5148  * err_block_addr and err_page_addr contain the block address and page address that
5149  * failed erase operation.
5150  *
5151  * Field Access Macros:
5152  *
5153  */
5154 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL register field. */
5155 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_LSB 5
5156 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL register field. */
5157 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_MSB 5
5158 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL register field. */
5159 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_WIDTH 1
5160 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL register field value. */
5161 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_SET_MSK 0x00000020
5162 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL register field value. */
5163 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_CLR_MSK 0xffffffdf
5164 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL register field. */
5165 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_RESET 0x0
5166 /* Extracts the ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL field value from a register. */
5167 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
5168 /* Produces a ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL register field value suitable for setting the register. */
5169 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
5170 
5171 /*
5172  * Field : load_comp
5173  *
5174  * Device finished the last issued load command.
5175  *
5176  * Field Access Macros:
5177  *
5178  */
5179 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_LD_COMP register field. */
5180 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_LSB 6
5181 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_LD_COMP register field. */
5182 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_MSB 6
5183 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_LD_COMP register field. */
5184 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_WIDTH 1
5185 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_LD_COMP register field value. */
5186 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_SET_MSK 0x00000040
5187 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_LD_COMP register field value. */
5188 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_CLR_MSK 0xffffffbf
5189 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_LD_COMP register field. */
5190 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_RESET 0x0
5191 /* Extracts the ALT_NAND_STAT_INTR_STAT0_LD_COMP field value from a register. */
5192 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
5193 /* Produces a ALT_NAND_STAT_INTR_STAT0_LD_COMP register field value suitable for setting the register. */
5194 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
5195 
5196 /*
5197  * Field : program_comp
5198  *
5199  * Device finished the last issued program command.
5200  *
5201  * Field Access Macros:
5202  *
5203  */
5204 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP register field. */
5205 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_LSB 7
5206 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP register field. */
5207 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_MSB 7
5208 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP register field. */
5209 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_WIDTH 1
5210 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP register field value. */
5211 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_SET_MSK 0x00000080
5212 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP register field value. */
5213 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_CLR_MSK 0xffffff7f
5214 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP register field. */
5215 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_RESET 0x0
5216 /* Extracts the ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP field value from a register. */
5217 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
5218 /* Produces a ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP register field value suitable for setting the register. */
5219 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
5220 
5221 /*
5222  * Field : erase_comp
5223  *
5224  * Device erase operation complete
5225  *
5226  * Field Access Macros:
5227  *
5228  */
5229 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_ERASE_COMP register field. */
5230 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_LSB 8
5231 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_ERASE_COMP register field. */
5232 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_MSB 8
5233 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_ERASE_COMP register field. */
5234 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_WIDTH 1
5235 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_ERASE_COMP register field value. */
5236 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_SET_MSK 0x00000100
5237 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_ERASE_COMP register field value. */
5238 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_CLR_MSK 0xfffffeff
5239 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_ERASE_COMP register field. */
5240 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_RESET 0x0
5241 /* Extracts the ALT_NAND_STAT_INTR_STAT0_ERASE_COMP field value from a register. */
5242 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
5243 /* Produces a ALT_NAND_STAT_INTR_STAT0_ERASE_COMP register field value suitable for setting the register. */
5244 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
5245 
5246 /*
5247  * Field : pipe_cpybck_cmd_comp
5248  *
5249  * A pipeline command or a copyback bank command has completed on this particular
5250  * bank
5251  *
5252  * Field Access Macros:
5253  *
5254  */
5255 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP register field. */
5256 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_LSB 9
5257 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP register field. */
5258 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_MSB 9
5259 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP register field. */
5260 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_WIDTH 1
5261 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP register field value. */
5262 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
5263 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP register field value. */
5264 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
5265 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP register field. */
5266 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_RESET 0x0
5267 /* Extracts the ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP field value from a register. */
5268 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
5269 /* Produces a ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
5270 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
5271 
5272 /*
5273  * Field : locked_blk
5274  *
5275  * The address to program or erase operation is to a locked block and the operation
5276  * failed due to this reason
5277  *
5278  * Field Access Macros:
5279  *
5280  */
5281 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK register field. */
5282 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_LSB 10
5283 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK register field. */
5284 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_MSB 10
5285 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK register field. */
5286 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_WIDTH 1
5287 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK register field value. */
5288 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_SET_MSK 0x00000400
5289 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK register field value. */
5290 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_CLR_MSK 0xfffffbff
5291 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK register field. */
5292 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_RESET 0x0
5293 /* Extracts the ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK field value from a register. */
5294 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
5295 /* Produces a ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK register field value suitable for setting the register. */
5296 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
5297 
5298 /*
5299  * Field : unsup_cmd
5300  *
5301  * An unsupported command was received. This interrupt is set when an invalid
5302  * command is received, or when a command sequence is broken.
5303  *
5304  * Field Access Macros:
5305  *
5306  */
5307 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD register field. */
5308 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_LSB 11
5309 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD register field. */
5310 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_MSB 11
5311 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD register field. */
5312 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_WIDTH 1
5313 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD register field value. */
5314 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_SET_MSK 0x00000800
5315 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD register field value. */
5316 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_CLR_MSK 0xfffff7ff
5317 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD register field. */
5318 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_RESET 0x0
5319 /* Extracts the ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD field value from a register. */
5320 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
5321 /* Produces a ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD register field value suitable for setting the register. */
5322 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
5323 
5324 /*
5325  * Field : INT_act
5326  *
5327  * R/B pin of device transitioned from low to high
5328  *
5329  * Field Access Macros:
5330  *
5331  */
5332 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_INT_ACT register field. */
5333 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_LSB 12
5334 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_INT_ACT register field. */
5335 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_MSB 12
5336 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_INT_ACT register field. */
5337 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_WIDTH 1
5338 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_INT_ACT register field value. */
5339 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_SET_MSK 0x00001000
5340 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_INT_ACT register field value. */
5341 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_CLR_MSK 0xffffefff
5342 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_INT_ACT register field. */
5343 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_RESET 0x0
5344 /* Extracts the ALT_NAND_STAT_INTR_STAT0_INT_ACT field value from a register. */
5345 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
5346 /* Produces a ALT_NAND_STAT_INTR_STAT0_INT_ACT register field value suitable for setting the register. */
5347 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
5348 
5349 /*
5350  * Field : rst_comp
5351  *
5352  * Controller has finished reset and initialization process
5353  *
5354  * Field Access Macros:
5355  *
5356  */
5357 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_RST_COMP register field. */
5358 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_LSB 13
5359 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_RST_COMP register field. */
5360 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_MSB 13
5361 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_RST_COMP register field. */
5362 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_WIDTH 1
5363 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_RST_COMP register field value. */
5364 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_SET_MSK 0x00002000
5365 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_RST_COMP register field value. */
5366 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_CLR_MSK 0xffffdfff
5367 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_RST_COMP register field. */
5368 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_RESET 0x0
5369 /* Extracts the ALT_NAND_STAT_INTR_STAT0_RST_COMP field value from a register. */
5370 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
5371 /* Produces a ALT_NAND_STAT_INTR_STAT0_RST_COMP register field value suitable for setting the register. */
5372 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
5373 
5374 /*
5375  * Field : pipe_cmd_err
5376  *
5377  * A pipeline command sequence has been violated. This occurs when Map 01 page
5378  * read/write address does not match the corresponding expected address from the
5379  * pipeline commands issued earlier.
5380  *
5381  * Field Access Macros:
5382  *
5383  */
5384 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR register field. */
5385 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_LSB 14
5386 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR register field. */
5387 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_MSB 14
5388 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR register field. */
5389 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_WIDTH 1
5390 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR register field value. */
5391 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_SET_MSK 0x00004000
5392 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR register field value. */
5393 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
5394 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR register field. */
5395 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_RESET 0x0
5396 /* Extracts the ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR field value from a register. */
5397 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
5398 /* Produces a ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR register field value suitable for setting the register. */
5399 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
5400 
5401 /*
5402  * Field : page_xfer_inc
5403  *
5404  * For every page of data transfer to or from the device, this bit will be set.
5405  *
5406  * Field Access Macros:
5407  *
5408  */
5409 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC register field. */
5410 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_LSB 15
5411 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC register field. */
5412 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_MSB 15
5413 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC register field. */
5414 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_WIDTH 1
5415 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC register field value. */
5416 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_SET_MSK 0x00008000
5417 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC register field value. */
5418 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_CLR_MSK 0xffff7fff
5419 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC register field. */
5420 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_RESET 0x0
5421 /* Extracts the ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC field value from a register. */
5422 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
5423 /* Produces a ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC register field value suitable for setting the register. */
5424 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
5425 
5426 #ifndef __ASSEMBLY__
5427 /*
5428  * WARNING: The C register and register group struct declarations are provided for
5429  * convenience and illustrative purposes. They should, however, be used with
5430  * caution as the C language standard provides no guarantees about the alignment or
5431  * atomicity of device memory accesses. The recommended practice for writing
5432  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5433  * alt_write_word() functions.
5434  *
5435  * The struct declaration for register ALT_NAND_STAT_INTR_STAT0.
5436  */
5437 struct ALT_NAND_STAT_INTR_STAT0_s
5438 {
5439  uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR */
5440  uint32_t : 1; /* *UNDEFINED* */
5441  uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP */
5442  uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_STAT0_TIME_OUT */
5443  uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL */
5444  uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL */
5445  uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_STAT0_LD_COMP */
5446  uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP */
5447  uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_STAT0_ERASE_COMP */
5448  uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP */
5449  uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK */
5450  uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD */
5451  uint32_t INT_act : 1; /* ALT_NAND_STAT_INTR_STAT0_INT_ACT */
5452  uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_STAT0_RST_COMP */
5453  uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR */
5454  uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC */
5455  uint32_t : 16; /* *UNDEFINED* */
5456 };
5457 
5458 /* The typedef declaration for register ALT_NAND_STAT_INTR_STAT0. */
5459 typedef volatile struct ALT_NAND_STAT_INTR_STAT0_s ALT_NAND_STAT_INTR_STAT0_t;
5460 #endif /* __ASSEMBLY__ */
5461 
5462 /* The byte offset of the ALT_NAND_STAT_INTR_STAT0 register from the beginning of the component. */
5463 #define ALT_NAND_STAT_INTR_STAT0_OFST 0x10
5464 
5465 /*
5466  * Register : intr_en0
5467  *
5468  * Enables corresponding interrupt bit in interrupt register for bank 0
5469  *
5470  * Register Layout
5471  *
5472  * Bits | Access | Reset | Description
5473  * :--------|:-------|:------|:--------------------------------------------
5474  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR
5475  * [1] | ??? | 0x0 | *UNDEFINED*
5476  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP
5477  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_TIME_OUT
5478  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL
5479  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_ERASE_FAIL
5480  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_LD_COMP
5481  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP
5482  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_ERASE_COMP
5483  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP
5484  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_LOCKED_BLK
5485  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_UNSUP_CMD
5486  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_INT_ACT
5487  * [13] | RW | 0x1 | ALT_NAND_STAT_INTR_EN0_RST_COMP
5488  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR
5489  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC
5490  * [31:16] | ??? | 0x0 | *UNDEFINED*
5491  *
5492  */
5493 /*
5494  * Field : ecc_uncor_err
5495  *
5496  * If set, Controller will interrupt processor when Ecc logic detects uncorrectable
5497  * error.
5498  *
5499  * Field Access Macros:
5500  *
5501  */
5502 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field. */
5503 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_LSB 0
5504 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field. */
5505 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_MSB 0
5506 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field. */
5507 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_WIDTH 1
5508 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field value. */
5509 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_SET_MSK 0x00000001
5510 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field value. */
5511 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
5512 /* The reset value of the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field. */
5513 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_RESET 0x0
5514 /* Extracts the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR field value from a register. */
5515 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
5516 /* Produces a ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field value suitable for setting the register. */
5517 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
5518 
5519 /*
5520  * Field : dma_cmd_comp
5521  *
5522  * Not implemented.
5523  *
5524  * Field Access Macros:
5525  *
5526  */
5527 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field. */
5528 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_LSB 2
5529 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field. */
5530 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_MSB 2
5531 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field. */
5532 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_WIDTH 1
5533 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field value. */
5534 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_SET_MSK 0x00000004
5535 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field value. */
5536 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_CLR_MSK 0xfffffffb
5537 /* The reset value of the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field. */
5538 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_RESET 0x0
5539 /* Extracts the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP field value from a register. */
5540 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
5541 /* Produces a ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field value suitable for setting the register. */
5542 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
5543 
5544 /*
5545  * Field : time_out
5546  *
5547  * Watchdog timer has triggered in the controller due to one of the reasons like
5548  * device not responding or controller state machine did not get back to idle
5549  *
5550  * Field Access Macros:
5551  *
5552  */
5553 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field. */
5554 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_LSB 3
5555 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field. */
5556 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_MSB 3
5557 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field. */
5558 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_WIDTH 1
5559 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field value. */
5560 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_SET_MSK 0x00000008
5561 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field value. */
5562 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_CLR_MSK 0xfffffff7
5563 /* The reset value of the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field. */
5564 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_RESET 0x0
5565 /* Extracts the ALT_NAND_STAT_INTR_EN0_TIME_OUT field value from a register. */
5566 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
5567 /* Produces a ALT_NAND_STAT_INTR_EN0_TIME_OUT register field value suitable for setting the register. */
5568 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
5569 
5570 /*
5571  * Field : program_fail
5572  *
5573  * Program failure occurred in the device on issuance of a program command.
5574  * err_block_addr and err_page_addr contain the block address and page address that
5575  * failed program operation.
5576  *
5577  * Field Access Macros:
5578  *
5579  */
5580 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field. */
5581 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_LSB 4
5582 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field. */
5583 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_MSB 4
5584 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field. */
5585 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_WIDTH 1
5586 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field value. */
5587 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_SET_MSK 0x00000010
5588 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field value. */
5589 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_CLR_MSK 0xffffffef
5590 /* The reset value of the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field. */
5591 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_RESET 0x0
5592 /* Extracts the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL field value from a register. */
5593 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
5594 /* Produces a ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field value suitable for setting the register. */
5595 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
5596 
5597 /*
5598  * Field : erase_fail
5599  *
5600  * Erase failure occurred in the device on issuance of a erase command.
5601  * err_block_addr and err_page_addr contain the block address and page address that
5602  * failed erase operation.
5603  *
5604  * Field Access Macros:
5605  *
5606  */
5607 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field. */
5608 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_LSB 5
5609 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field. */
5610 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_MSB 5
5611 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field. */
5612 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_WIDTH 1
5613 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field value. */
5614 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_SET_MSK 0x00000020
5615 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field value. */
5616 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_CLR_MSK 0xffffffdf
5617 /* The reset value of the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field. */
5618 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_RESET 0x0
5619 /* Extracts the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL field value from a register. */
5620 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
5621 /* Produces a ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field value suitable for setting the register. */
5622 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
5623 
5624 /*
5625  * Field : load_comp
5626  *
5627  * Device finished the last issued load command.
5628  *
5629  * Field Access Macros:
5630  *
5631  */
5632 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_LD_COMP register field. */
5633 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_LSB 6
5634 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_LD_COMP register field. */
5635 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_MSB 6
5636 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_LD_COMP register field. */
5637 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_WIDTH 1
5638 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_LD_COMP register field value. */
5639 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_SET_MSK 0x00000040
5640 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_LD_COMP register field value. */
5641 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_CLR_MSK 0xffffffbf
5642 /* The reset value of the ALT_NAND_STAT_INTR_EN0_LD_COMP register field. */
5643 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_RESET 0x0
5644 /* Extracts the ALT_NAND_STAT_INTR_EN0_LD_COMP field value from a register. */
5645 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
5646 /* Produces a ALT_NAND_STAT_INTR_EN0_LD_COMP register field value suitable for setting the register. */
5647 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
5648 
5649 /*
5650  * Field : program_comp
5651  *
5652  * Device finished the last issued program command.
5653  *
5654  * Field Access Macros:
5655  *
5656  */
5657 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field. */
5658 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_LSB 7
5659 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field. */
5660 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_MSB 7
5661 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field. */
5662 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_WIDTH 1
5663 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field value. */
5664 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_SET_MSK 0x00000080
5665 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field value. */
5666 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_CLR_MSK 0xffffff7f
5667 /* The reset value of the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field. */
5668 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_RESET 0x0
5669 /* Extracts the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP field value from a register. */
5670 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
5671 /* Produces a ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field value suitable for setting the register. */
5672 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
5673 
5674 /*
5675  * Field : erase_comp
5676  *
5677  * Device erase operation complete
5678  *
5679  * Field Access Macros:
5680  *
5681  */
5682 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field. */
5683 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_LSB 8
5684 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field. */
5685 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_MSB 8
5686 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field. */
5687 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_WIDTH 1
5688 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field value. */
5689 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_SET_MSK 0x00000100
5690 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field value. */
5691 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_CLR_MSK 0xfffffeff
5692 /* The reset value of the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field. */
5693 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_RESET 0x0
5694 /* Extracts the ALT_NAND_STAT_INTR_EN0_ERASE_COMP field value from a register. */
5695 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
5696 /* Produces a ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field value suitable for setting the register. */
5697 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
5698 
5699 /*
5700  * Field : pipe_cpybck_cmd_comp
5701  *
5702  * A pipeline command or a copyback bank command has completed on this particular
5703  * bank
5704  *
5705  * Field Access Macros:
5706  *
5707  */
5708 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field. */
5709 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_LSB 9
5710 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field. */
5711 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_MSB 9
5712 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field. */
5713 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_WIDTH 1
5714 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field value. */
5715 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
5716 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field value. */
5717 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
5718 /* The reset value of the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field. */
5719 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_RESET 0x0
5720 /* Extracts the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP field value from a register. */
5721 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
5722 /* Produces a ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
5723 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
5724 
5725 /*
5726  * Field : locked_blk
5727  *
5728  * The address to program or erase operation is to a locked block and the operation
5729  * failed due to this reason
5730  *
5731  * Field Access Macros:
5732  *
5733  */
5734 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field. */
5735 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_LSB 10
5736 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field. */
5737 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_MSB 10
5738 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field. */
5739 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_WIDTH 1
5740 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field value. */
5741 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_SET_MSK 0x00000400
5742 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field value. */
5743 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_CLR_MSK 0xfffffbff
5744 /* The reset value of the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field. */
5745 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_RESET 0x0
5746 /* Extracts the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK field value from a register. */
5747 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
5748 /* Produces a ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field value suitable for setting the register. */
5749 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
5750 
5751 /*
5752  * Field : unsup_cmd
5753  *
5754  * An unsupported command was received. This interrupt is set when an invalid
5755  * command is received, or when a command sequence is broken.
5756  *
5757  * Field Access Macros:
5758  *
5759  */
5760 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field. */
5761 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_LSB 11
5762 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field. */
5763 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_MSB 11
5764 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field. */
5765 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_WIDTH 1
5766 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field value. */
5767 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_SET_MSK 0x00000800
5768 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field value. */
5769 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_CLR_MSK 0xfffff7ff
5770 /* The reset value of the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field. */
5771 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_RESET 0x0
5772 /* Extracts the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD field value from a register. */
5773 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
5774 /* Produces a ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field value suitable for setting the register. */
5775 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
5776 
5777 /*
5778  * Field : INT_act
5779  *
5780  * R/B pin of device transitioned from low to high
5781  *
5782  * Field Access Macros:
5783  *
5784  */
5785 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_INT_ACT register field. */
5786 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_LSB 12
5787 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_INT_ACT register field. */
5788 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_MSB 12
5789 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_INT_ACT register field. */
5790 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_WIDTH 1
5791 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_INT_ACT register field value. */
5792 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_SET_MSK 0x00001000
5793 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_INT_ACT register field value. */
5794 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_CLR_MSK 0xffffefff
5795 /* The reset value of the ALT_NAND_STAT_INTR_EN0_INT_ACT register field. */
5796 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_RESET 0x0
5797 /* Extracts the ALT_NAND_STAT_INTR_EN0_INT_ACT field value from a register. */
5798 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
5799 /* Produces a ALT_NAND_STAT_INTR_EN0_INT_ACT register field value suitable for setting the register. */
5800 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
5801 
5802 /*
5803  * Field : rst_comp
5804  *
5805  * A reset command has completed on this bank
5806  *
5807  * Field Access Macros:
5808  *
5809  */
5810 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_RST_COMP register field. */
5811 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_LSB 13
5812 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_RST_COMP register field. */
5813 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_MSB 13
5814 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_RST_COMP register field. */
5815 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_WIDTH 1
5816 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_RST_COMP register field value. */
5817 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_SET_MSK 0x00002000
5818 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_RST_COMP register field value. */
5819 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_CLR_MSK 0xffffdfff
5820 /* The reset value of the ALT_NAND_STAT_INTR_EN0_RST_COMP register field. */
5821 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_RESET 0x1
5822 /* Extracts the ALT_NAND_STAT_INTR_EN0_RST_COMP field value from a register. */
5823 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
5824 /* Produces a ALT_NAND_STAT_INTR_EN0_RST_COMP register field value suitable for setting the register. */
5825 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
5826 
5827 /*
5828  * Field : pipe_cmd_err
5829  *
5830  * A pipeline command sequence has been violated. This occurs when Map 01 page
5831  * read/write address does not match the corresponding expected address from the
5832  * pipeline commands issued earlier.
5833  *
5834  * Field Access Macros:
5835  *
5836  */
5837 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field. */
5838 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_LSB 14
5839 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field. */
5840 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_MSB 14
5841 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field. */
5842 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_WIDTH 1
5843 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field value. */
5844 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_SET_MSK 0x00004000
5845 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field value. */
5846 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
5847 /* The reset value of the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field. */
5848 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_RESET 0x0
5849 /* Extracts the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR field value from a register. */
5850 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
5851 /* Produces a ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field value suitable for setting the register. */
5852 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
5853 
5854 /*
5855  * Field : page_xfer_inc
5856  *
5857  * For every page of data transfer to or from the device, this bit will be set.
5858  *
5859  * Field Access Macros:
5860  *
5861  */
5862 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field. */
5863 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_LSB 15
5864 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field. */
5865 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_MSB 15
5866 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field. */
5867 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_WIDTH 1
5868 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field value. */
5869 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_SET_MSK 0x00008000
5870 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field value. */
5871 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_CLR_MSK 0xffff7fff
5872 /* The reset value of the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field. */
5873 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_RESET 0x0
5874 /* Extracts the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC field value from a register. */
5875 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
5876 /* Produces a ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field value suitable for setting the register. */
5877 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
5878 
5879 #ifndef __ASSEMBLY__
5880 /*
5881  * WARNING: The C register and register group struct declarations are provided for
5882  * convenience and illustrative purposes. They should, however, be used with
5883  * caution as the C language standard provides no guarantees about the alignment or
5884  * atomicity of device memory accesses. The recommended practice for writing
5885  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5886  * alt_write_word() functions.
5887  *
5888  * The struct declaration for register ALT_NAND_STAT_INTR_EN0.
5889  */
5890 struct ALT_NAND_STAT_INTR_EN0_s
5891 {
5892  uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR */
5893  uint32_t : 1; /* *UNDEFINED* */
5894  uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP */
5895  uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_EN0_TIME_OUT */
5896  uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL */
5897  uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_EN0_ERASE_FAIL */
5898  uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_EN0_LD_COMP */
5899  uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP */
5900  uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_EN0_ERASE_COMP */
5901  uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP */
5902  uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_EN0_LOCKED_BLK */
5903  uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_EN0_UNSUP_CMD */
5904  uint32_t INT_act : 1; /* ALT_NAND_STAT_INTR_EN0_INT_ACT */
5905  uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_EN0_RST_COMP */
5906  uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR */
5907  uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC */
5908  uint32_t : 16; /* *UNDEFINED* */
5909 };
5910 
5911 /* The typedef declaration for register ALT_NAND_STAT_INTR_EN0. */
5912 typedef volatile struct ALT_NAND_STAT_INTR_EN0_s ALT_NAND_STAT_INTR_EN0_t;
5913 #endif /* __ASSEMBLY__ */
5914 
5915 /* The byte offset of the ALT_NAND_STAT_INTR_EN0 register from the beginning of the component. */
5916 #define ALT_NAND_STAT_INTR_EN0_OFST 0x20
5917 
5918 /*
5919  * Register : page_cnt0
5920  *
5921  * Decrementing page count bank 0
5922  *
5923  * Register Layout
5924  *
5925  * Bits | Access | Reset | Description
5926  * :-------|:-------|:------|:------------------------------
5927  * [7:0] | R | 0x0 | ALT_NAND_STAT_PAGE_CNT0_VALUE
5928  * [31:8] | ??? | 0x0 | *UNDEFINED*
5929  *
5930  */
5931 /*
5932  * Field : value
5933  *
5934  * Maintains a decrementing count of the number of pages in the multi-page
5935  * (pipeline and copyback) command being executed.
5936  *
5937  * Field Access Macros:
5938  *
5939  */
5940 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_PAGE_CNT0_VALUE register field. */
5941 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_LSB 0
5942 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_PAGE_CNT0_VALUE register field. */
5943 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_MSB 7
5944 /* The width in bits of the ALT_NAND_STAT_PAGE_CNT0_VALUE register field. */
5945 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_WIDTH 8
5946 /* The mask used to set the ALT_NAND_STAT_PAGE_CNT0_VALUE register field value. */
5947 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_SET_MSK 0x000000ff
5948 /* The mask used to clear the ALT_NAND_STAT_PAGE_CNT0_VALUE register field value. */
5949 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_CLR_MSK 0xffffff00
5950 /* The reset value of the ALT_NAND_STAT_PAGE_CNT0_VALUE register field. */
5951 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_RESET 0x0
5952 /* Extracts the ALT_NAND_STAT_PAGE_CNT0_VALUE field value from a register. */
5953 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
5954 /* Produces a ALT_NAND_STAT_PAGE_CNT0_VALUE register field value suitable for setting the register. */
5955 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_SET(value) (((value) << 0) & 0x000000ff)
5956 
5957 #ifndef __ASSEMBLY__
5958 /*
5959  * WARNING: The C register and register group struct declarations are provided for
5960  * convenience and illustrative purposes. They should, however, be used with
5961  * caution as the C language standard provides no guarantees about the alignment or
5962  * atomicity of device memory accesses. The recommended practice for writing
5963  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5964  * alt_write_word() functions.
5965  *
5966  * The struct declaration for register ALT_NAND_STAT_PAGE_CNT0.
5967  */
5968 struct ALT_NAND_STAT_PAGE_CNT0_s
5969 {
5970  const uint32_t value : 8; /* ALT_NAND_STAT_PAGE_CNT0_VALUE */
5971  uint32_t : 24; /* *UNDEFINED* */
5972 };
5973 
5974 /* The typedef declaration for register ALT_NAND_STAT_PAGE_CNT0. */
5975 typedef volatile struct ALT_NAND_STAT_PAGE_CNT0_s ALT_NAND_STAT_PAGE_CNT0_t;
5976 #endif /* __ASSEMBLY__ */
5977 
5978 /* The byte offset of the ALT_NAND_STAT_PAGE_CNT0 register from the beginning of the component. */
5979 #define ALT_NAND_STAT_PAGE_CNT0_OFST 0x30
5980 
5981 /*
5982  * Register : err_page_addr0
5983  *
5984  * Erred page address bank 0
5985  *
5986  * Register Layout
5987  *
5988  * Bits | Access | Reset | Description
5989  * :--------|:-------|:------|:-----------------------------------
5990  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE
5991  * [31:16] | ??? | 0x0 | *UNDEFINED*
5992  *
5993  */
5994 /*
5995  * Field : value
5996  *
5997  * Holds the page address that resulted in a failure on program or erase operation.
5998  *
5999  * Field Access Macros:
6000  *
6001  */
6002 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field. */
6003 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_LSB 0
6004 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field. */
6005 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_MSB 15
6006 /* The width in bits of the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field. */
6007 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_WIDTH 16
6008 /* The mask used to set the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field value. */
6009 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_SET_MSK 0x0000ffff
6010 /* The mask used to clear the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field value. */
6011 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_CLR_MSK 0xffff0000
6012 /* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field. */
6013 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_RESET 0x0
6014 /* Extracts the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE field value from a register. */
6015 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
6016 /* Produces a ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field value suitable for setting the register. */
6017 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
6018 
6019 #ifndef __ASSEMBLY__
6020 /*
6021  * WARNING: The C register and register group struct declarations are provided for
6022  * convenience and illustrative purposes. They should, however, be used with
6023  * caution as the C language standard provides no guarantees about the alignment or
6024  * atomicity of device memory accesses. The recommended practice for writing
6025  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6026  * alt_write_word() functions.
6027  *
6028  * The struct declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR0.
6029  */
6030 struct ALT_NAND_STAT_ERR_PAGE_ADDR0_s
6031 {
6032  const uint32_t value : 16; /* ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE */
6033  uint32_t : 16; /* *UNDEFINED* */
6034 };
6035 
6036 /* The typedef declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR0. */
6037 typedef volatile struct ALT_NAND_STAT_ERR_PAGE_ADDR0_s ALT_NAND_STAT_ERR_PAGE_ADDR0_t;
6038 #endif /* __ASSEMBLY__ */
6039 
6040 /* The byte offset of the ALT_NAND_STAT_ERR_PAGE_ADDR0 register from the beginning of the component. */
6041 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_OFST 0x40
6042 
6043 /*
6044  * Register : err_block_addr0
6045  *
6046  * Erred block address bank 0
6047  *
6048  * Register Layout
6049  *
6050  * Bits | Access | Reset | Description
6051  * :--------|:-------|:------|:------------------------------------
6052  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE
6053  * [31:16] | ??? | 0x0 | *UNDEFINED*
6054  *
6055  */
6056 /*
6057  * Field : value
6058  *
6059  * Holds the block address that resulted in a failure on program or erase
6060  * operation.
6061  *
6062  * Field Access Macros:
6063  *
6064  */
6065 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field. */
6066 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_LSB 0
6067 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field. */
6068 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_MSB 15
6069 /* The width in bits of the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field. */
6070 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_WIDTH 16
6071 /* The mask used to set the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field value. */
6072 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_SET_MSK 0x0000ffff
6073 /* The mask used to clear the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field value. */
6074 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_CLR_MSK 0xffff0000
6075 /* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field. */
6076 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_RESET 0x0
6077 /* Extracts the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE field value from a register. */
6078 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
6079 /* Produces a ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field value suitable for setting the register. */
6080 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
6081 
6082 #ifndef __ASSEMBLY__
6083 /*
6084  * WARNING: The C register and register group struct declarations are provided for
6085  * convenience and illustrative purposes. They should, however, be used with
6086  * caution as the C language standard provides no guarantees about the alignment or
6087  * atomicity of device memory accesses. The recommended practice for writing
6088  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6089  * alt_write_word() functions.
6090  *
6091  * The struct declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR0.
6092  */
6093 struct ALT_NAND_STAT_ERR_BLOCK_ADDR0_s
6094 {
6095  const uint32_t value : 16; /* ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE */
6096  uint32_t : 16; /* *UNDEFINED* */
6097 };
6098 
6099 /* The typedef declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR0. */
6100 typedef volatile struct ALT_NAND_STAT_ERR_BLOCK_ADDR0_s ALT_NAND_STAT_ERR_BLOCK_ADDR0_t;
6101 #endif /* __ASSEMBLY__ */
6102 
6103 /* The byte offset of the ALT_NAND_STAT_ERR_BLOCK_ADDR0 register from the beginning of the component. */
6104 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_OFST 0x50
6105 
6106 /*
6107  * Register : intr_status1
6108  *
6109  * Interrupt status register for bank 1
6110  *
6111  * Register Layout
6112  *
6113  * Bits | Access | Reset | Description
6114  * :--------|:-------|:------|:----------------------------------------------
6115  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR
6116  * [1] | ??? | 0x0 | *UNDEFINED*
6117  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP
6118  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_TIME_OUT
6119  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL
6120  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL
6121  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_LD_COMP
6122  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP
6123  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_ERASE_COMP
6124  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP
6125  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK
6126  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD
6127  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_INT_ACT
6128  * [13] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_RST_COMP
6129  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR
6130  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC
6131  * [31:16] | ??? | 0x0 | *UNDEFINED*
6132  *
6133  */
6134 /*
6135  * Field : ecc_uncor_err
6136  *
6137  * Ecc logic detected uncorrectable error while reading data from flash device.
6138  *
6139  * Field Access Macros:
6140  *
6141  */
6142 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR register field. */
6143 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_LSB 0
6144 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR register field. */
6145 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_MSB 0
6146 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR register field. */
6147 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_WIDTH 1
6148 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR register field value. */
6149 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_SET_MSK 0x00000001
6150 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR register field value. */
6151 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
6152 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR register field. */
6153 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_RESET 0x0
6154 /* Extracts the ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR field value from a register. */
6155 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
6156 /* Produces a ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR register field value suitable for setting the register. */
6157 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
6158 
6159 /*
6160  * Field : dma_cmd_comp
6161  *
6162  * Not implemented.
6163  *
6164  * Field Access Macros:
6165  *
6166  */
6167 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP register field. */
6168 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_LSB 2
6169 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP register field. */
6170 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_MSB 2
6171 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP register field. */
6172 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_WIDTH 1
6173 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP register field value. */
6174 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_SET_MSK 0x00000004
6175 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP register field value. */
6176 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_CLR_MSK 0xfffffffb
6177 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP register field. */
6178 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_RESET 0x0
6179 /* Extracts the ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP field value from a register. */
6180 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
6181 /* Produces a ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP register field value suitable for setting the register. */
6182 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
6183 
6184 /*
6185  * Field : time_out
6186  *
6187  * Watchdog timer has triggered in the controller due to one of the reasons like
6188  * device not responding or controller state machine did not get back to idle
6189  *
6190  * Field Access Macros:
6191  *
6192  */
6193 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_TIME_OUT register field. */
6194 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_LSB 3
6195 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_TIME_OUT register field. */
6196 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_MSB 3
6197 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_TIME_OUT register field. */
6198 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_WIDTH 1
6199 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_TIME_OUT register field value. */
6200 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_SET_MSK 0x00000008
6201 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_TIME_OUT register field value. */
6202 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_CLR_MSK 0xfffffff7
6203 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_TIME_OUT register field. */
6204 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_RESET 0x0
6205 /* Extracts the ALT_NAND_STAT_INTR_STAT1_TIME_OUT field value from a register. */
6206 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
6207 /* Produces a ALT_NAND_STAT_INTR_STAT1_TIME_OUT register field value suitable for setting the register. */
6208 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
6209 
6210 /*
6211  * Field : program_fail
6212  *
6213  * Program failure occurred in the device on issuance of a program command.
6214  * err_block_addr and err_page_addr contain the block address and page address that
6215  * failed program operation.
6216  *
6217  * Field Access Macros:
6218  *
6219  */
6220 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL register field. */
6221 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_LSB 4
6222 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL register field. */
6223 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_MSB 4
6224 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL register field. */
6225 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_WIDTH 1
6226 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL register field value. */
6227 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_SET_MSK 0x00000010
6228 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL register field value. */
6229 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_CLR_MSK 0xffffffef
6230 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL register field. */
6231 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_RESET 0x0
6232 /* Extracts the ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL field value from a register. */
6233 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
6234 /* Produces a ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL register field value suitable for setting the register. */
6235 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
6236 
6237 /*
6238  * Field : erase_fail
6239  *
6240  * Erase failure occurred in the device on issuance of a erase command.
6241  * err_block_addr and err_page_addr contain the block address and page address that
6242  * failed erase operation.
6243  *
6244  * Field Access Macros:
6245  *
6246  */
6247 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL register field. */
6248 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_LSB 5
6249 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL register field. */
6250 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_MSB 5
6251 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL register field. */
6252 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_WIDTH 1
6253 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL register field value. */
6254 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_SET_MSK 0x00000020
6255 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL register field value. */
6256 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_CLR_MSK 0xffffffdf
6257 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL register field. */
6258 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_RESET 0x0
6259 /* Extracts the ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL field value from a register. */
6260 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
6261 /* Produces a ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL register field value suitable for setting the register. */
6262 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
6263 
6264 /*
6265  * Field : load_comp
6266  *
6267  * Device finished the last issued load command.
6268  *
6269  * Field Access Macros:
6270  *
6271  */
6272 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_LD_COMP register field. */
6273 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_LSB 6
6274 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_LD_COMP register field. */
6275 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_MSB 6
6276 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_LD_COMP register field. */
6277 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_WIDTH 1
6278 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_LD_COMP register field value. */
6279 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_SET_MSK 0x00000040
6280 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_LD_COMP register field value. */
6281 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_CLR_MSK 0xffffffbf
6282 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_LD_COMP register field. */
6283 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_RESET 0x0
6284 /* Extracts the ALT_NAND_STAT_INTR_STAT1_LD_COMP field value from a register. */
6285 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
6286 /* Produces a ALT_NAND_STAT_INTR_STAT1_LD_COMP register field value suitable for setting the register. */
6287 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
6288 
6289 /*
6290  * Field : program_comp
6291  *
6292  * Device finished the last issued program command.
6293  *
6294  * Field Access Macros:
6295  *
6296  */
6297 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP register field. */
6298 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_LSB 7
6299 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP register field. */
6300 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_MSB 7
6301 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP register field. */
6302 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_WIDTH 1
6303 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP register field value. */
6304 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_SET_MSK 0x00000080
6305 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP register field value. */
6306 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_CLR_MSK 0xffffff7f
6307 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP register field. */
6308 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_RESET 0x0
6309 /* Extracts the ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP field value from a register. */
6310 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
6311 /* Produces a ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP register field value suitable for setting the register. */
6312 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
6313 
6314 /*
6315  * Field : erase_comp
6316  *
6317  * Device erase operation complete
6318  *
6319  * Field Access Macros:
6320  *
6321  */
6322 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_ERASE_COMP register field. */
6323 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_LSB 8
6324 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_ERASE_COMP register field. */
6325 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_MSB 8
6326 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_ERASE_COMP register field. */
6327 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_WIDTH 1
6328 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_ERASE_COMP register field value. */
6329 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_SET_MSK 0x00000100
6330 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_ERASE_COMP register field value. */
6331 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_CLR_MSK 0xfffffeff
6332 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_ERASE_COMP register field. */
6333 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_RESET 0x0
6334 /* Extracts the ALT_NAND_STAT_INTR_STAT1_ERASE_COMP field value from a register. */
6335 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
6336 /* Produces a ALT_NAND_STAT_INTR_STAT1_ERASE_COMP register field value suitable for setting the register. */
6337 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
6338 
6339 /*
6340  * Field : pipe_cpybck_cmd_comp
6341  *
6342  * A pipeline command or a copyback bank command has completed on this particular
6343  * bank
6344  *
6345  * Field Access Macros:
6346  *
6347  */
6348 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP register field. */
6349 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_LSB 9
6350 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP register field. */
6351 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_MSB 9
6352 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP register field. */
6353 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_WIDTH 1
6354 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP register field value. */
6355 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
6356 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP register field value. */
6357 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
6358 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP register field. */
6359 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_RESET 0x0
6360 /* Extracts the ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP field value from a register. */
6361 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
6362 /* Produces a ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
6363 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
6364 
6365 /*
6366  * Field : locked_blk
6367  *
6368  * The address to program or erase operation is to a locked block and the operation
6369  * failed due to this reason
6370  *
6371  * Field Access Macros:
6372  *
6373  */
6374 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK register field. */
6375 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_LSB 10
6376 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK register field. */
6377 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_MSB 10
6378 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK register field. */
6379 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_WIDTH 1
6380 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK register field value. */
6381 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_SET_MSK 0x00000400
6382 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK register field value. */
6383 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_CLR_MSK 0xfffffbff
6384 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK register field. */
6385 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_RESET 0x0
6386 /* Extracts the ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK field value from a register. */
6387 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
6388 /* Produces a ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK register field value suitable for setting the register. */
6389 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
6390 
6391 /*
6392  * Field : unsup_cmd
6393  *
6394  * An unsupported command was received. This interrupt is set when an invalid
6395  * command is received, or when a command sequence is broken.
6396  *
6397  * Field Access Macros:
6398  *
6399  */
6400 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD register field. */
6401 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_LSB 11
6402 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD register field. */
6403 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_MSB 11
6404 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD register field. */
6405 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_WIDTH 1
6406 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD register field value. */
6407 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_SET_MSK 0x00000800
6408 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD register field value. */
6409 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_CLR_MSK 0xfffff7ff
6410 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD register field. */
6411 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_RESET 0x0
6412 /* Extracts the ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD field value from a register. */
6413 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
6414 /* Produces a ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD register field value suitable for setting the register. */
6415 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
6416 
6417 /*
6418  * Field : INT_act
6419  *
6420  * R/B pin of device transitioned from low to high
6421  *
6422  * Field Access Macros:
6423  *
6424  */
6425 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_INT_ACT register field. */
6426 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_LSB 12
6427 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_INT_ACT register field. */
6428 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_MSB 12
6429 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_INT_ACT register field. */
6430 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_WIDTH 1
6431 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_INT_ACT register field value. */
6432 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_SET_MSK 0x00001000
6433 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_INT_ACT register field value. */
6434 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_CLR_MSK 0xffffefff
6435 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_INT_ACT register field. */
6436 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_RESET 0x0
6437 /* Extracts the ALT_NAND_STAT_INTR_STAT1_INT_ACT field value from a register. */
6438 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
6439 /* Produces a ALT_NAND_STAT_INTR_STAT1_INT_ACT register field value suitable for setting the register. */
6440 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
6441 
6442 /*
6443  * Field : rst_comp
6444  *
6445  * The NAND Flash Memory Controller has completed its reset and initialization
6446  * process
6447  *
6448  * Field Access Macros:
6449  *
6450  */
6451 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_RST_COMP register field. */
6452 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_LSB 13
6453 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_RST_COMP register field. */
6454 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_MSB 13
6455 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_RST_COMP register field. */
6456 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_WIDTH 1
6457 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_RST_COMP register field value. */
6458 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_SET_MSK 0x00002000
6459 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_RST_COMP register field value. */
6460 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_CLR_MSK 0xffffdfff
6461 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_RST_COMP register field. */
6462 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_RESET 0x0
6463 /* Extracts the ALT_NAND_STAT_INTR_STAT1_RST_COMP field value from a register. */
6464 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
6465 /* Produces a ALT_NAND_STAT_INTR_STAT1_RST_COMP register field value suitable for setting the register. */
6466 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
6467 
6468 /*
6469  * Field : pipe_cmd_err
6470  *
6471  * A pipeline command sequence has been violated. This occurs when Map 01 page
6472  * read/write address does not match the corresponding expected address from the
6473  * pipeline commands issued earlier.
6474  *
6475  * Field Access Macros:
6476  *
6477  */
6478 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR register field. */
6479 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_LSB 14
6480 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR register field. */
6481 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_MSB 14
6482 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR register field. */
6483 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_WIDTH 1
6484 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR register field value. */
6485 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_SET_MSK 0x00004000
6486 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR register field value. */
6487 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
6488 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR register field. */
6489 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_RESET 0x0
6490 /* Extracts the ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR field value from a register. */
6491 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
6492 /* Produces a ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR register field value suitable for setting the register. */
6493 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
6494 
6495 /*
6496  * Field : page_xfer_inc
6497  *
6498  * For every page of data transfer to or from the device, this bit will be set.
6499  *
6500  * Field Access Macros:
6501  *
6502  */
6503 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC register field. */
6504 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_LSB 15
6505 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC register field. */
6506 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_MSB 15
6507 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC register field. */
6508 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_WIDTH 1
6509 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC register field value. */
6510 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_SET_MSK 0x00008000
6511 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC register field value. */
6512 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_CLR_MSK 0xffff7fff
6513 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC register field. */
6514 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_RESET 0x0
6515 /* Extracts the ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC field value from a register. */
6516 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
6517 /* Produces a ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC register field value suitable for setting the register. */
6518 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
6519 
6520 #ifndef __ASSEMBLY__
6521 /*
6522  * WARNING: The C register and register group struct declarations are provided for
6523  * convenience and illustrative purposes. They should, however, be used with
6524  * caution as the C language standard provides no guarantees about the alignment or
6525  * atomicity of device memory accesses. The recommended practice for writing
6526  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6527  * alt_write_word() functions.
6528  *
6529  * The struct declaration for register ALT_NAND_STAT_INTR_STAT1.
6530  */
6531 struct ALT_NAND_STAT_INTR_STAT1_s
6532 {
6533  uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR */
6534  uint32_t : 1; /* *UNDEFINED* */
6535  uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP */
6536  uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_STAT1_TIME_OUT */
6537  uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL */
6538  uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL */
6539  uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_STAT1_LD_COMP */
6540  uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP */
6541  uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_STAT1_ERASE_COMP */
6542  uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP */
6543  uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK */
6544  uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD */
6545  uint32_t INT_act : 1; /* ALT_NAND_STAT_INTR_STAT1_INT_ACT */
6546  uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_STAT1_RST_COMP */
6547  uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR */
6548  uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC */
6549  uint32_t : 16; /* *UNDEFINED* */
6550 };
6551 
6552 /* The typedef declaration for register ALT_NAND_STAT_INTR_STAT1. */
6553 typedef volatile struct ALT_NAND_STAT_INTR_STAT1_s ALT_NAND_STAT_INTR_STAT1_t;
6554 #endif /* __ASSEMBLY__ */
6555 
6556 /* The byte offset of the ALT_NAND_STAT_INTR_STAT1 register from the beginning of the component. */
6557 #define ALT_NAND_STAT_INTR_STAT1_OFST 0x60
6558 
6559 /*
6560  * Register : intr_en1
6561  *
6562  * Enables corresponding interrupt bit in interrupt register for bank 1
6563  *
6564  * Register Layout
6565  *
6566  * Bits | Access | Reset | Description
6567  * :--------|:-------|:------|:--------------------------------------------
6568  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR
6569  * [1] | ??? | 0x0 | *UNDEFINED*
6570  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP
6571  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_TIME_OUT
6572  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL
6573  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_ERASE_FAIL
6574  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_LD_COMP
6575  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP
6576  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_ERASE_COMP
6577  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP
6578  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_LOCKED_BLK
6579  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_UNSUP_CMD
6580  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_INT_ACT
6581  * [13] | RW | 0x1 | ALT_NAND_STAT_INTR_EN1_RST_COMP
6582  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR
6583  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC
6584  * [31:16] | ??? | 0x0 | *UNDEFINED*
6585  *
6586  */
6587 /*
6588  * Field : ecc_uncor_err
6589  *
6590  * If set, Controller will interrupt processor when Ecc logic detects uncorrectable
6591  * error.
6592  *
6593  * Field Access Macros:
6594  *
6595  */
6596 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field. */
6597 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_LSB 0
6598 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field. */
6599 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_MSB 0
6600 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field. */
6601 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_WIDTH 1
6602 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field value. */
6603 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_SET_MSK 0x00000001
6604 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field value. */
6605 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
6606 /* The reset value of the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field. */
6607 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_RESET 0x0
6608 /* Extracts the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR field value from a register. */
6609 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
6610 /* Produces a ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field value suitable for setting the register. */
6611 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
6612 
6613 /*
6614  * Field : dma_cmd_comp
6615  *
6616  * Not implemented.
6617  *
6618  * Field Access Macros:
6619  *
6620  */
6621 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field. */
6622 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_LSB 2
6623 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field. */
6624 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_MSB 2
6625 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field. */
6626 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_WIDTH 1
6627 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field value. */
6628 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_SET_MSK 0x00000004
6629 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field value. */
6630 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_CLR_MSK 0xfffffffb
6631 /* The reset value of the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field. */
6632 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_RESET 0x0
6633 /* Extracts the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP field value from a register. */
6634 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
6635 /* Produces a ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field value suitable for setting the register. */
6636 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
6637 
6638 /*
6639  * Field : time_out
6640  *
6641  * Watchdog timer has triggered in the controller due to one of the reasons like
6642  * device not responding or controller state machine did not get back to idle
6643  *
6644  * Field Access Macros:
6645  *
6646  */
6647 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field. */
6648 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_LSB 3
6649 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field. */
6650 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_MSB 3
6651 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field. */
6652 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_WIDTH 1
6653 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field value. */
6654 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_SET_MSK 0x00000008
6655 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field value. */
6656 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_CLR_MSK 0xfffffff7
6657 /* The reset value of the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field. */
6658 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_RESET 0x0
6659 /* Extracts the ALT_NAND_STAT_INTR_EN1_TIME_OUT field value from a register. */
6660 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
6661 /* Produces a ALT_NAND_STAT_INTR_EN1_TIME_OUT register field value suitable for setting the register. */
6662 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
6663 
6664 /*
6665  * Field : program_fail
6666  *
6667  * Program failure occurred in the device on issuance of a program command.
6668  * err_block_addr and err_page_addr contain the block address and page address that
6669  * failed program operation.
6670  *
6671  * Field Access Macros:
6672  *
6673  */
6674 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field. */
6675 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_LSB 4
6676 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field. */
6677 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_MSB 4
6678 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field. */
6679 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_WIDTH 1
6680 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field value. */
6681 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_SET_MSK 0x00000010
6682 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field value. */
6683 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_CLR_MSK 0xffffffef
6684 /* The reset value of the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field. */
6685 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_RESET 0x0
6686 /* Extracts the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL field value from a register. */
6687 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
6688 /* Produces a ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field value suitable for setting the register. */
6689 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
6690 
6691 /*
6692  * Field : erase_fail
6693  *
6694  * Erase failure occurred in the device on issuance of a erase command.
6695  * err_block_addr and err_page_addr contain the block address and page address that
6696  * failed erase operation.
6697  *
6698  * Field Access Macros:
6699  *
6700  */
6701 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field. */
6702 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_LSB 5
6703 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field. */
6704 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_MSB 5
6705 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field. */
6706 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_WIDTH 1
6707 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field value. */
6708 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_SET_MSK 0x00000020
6709 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field value. */
6710 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_CLR_MSK 0xffffffdf
6711 /* The reset value of the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field. */
6712 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_RESET 0x0
6713 /* Extracts the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL field value from a register. */
6714 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
6715 /* Produces a ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field value suitable for setting the register. */
6716 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
6717 
6718 /*
6719  * Field : load_comp
6720  *
6721  * Device finished the last issued load command.
6722  *
6723  * Field Access Macros:
6724  *
6725  */
6726 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_LD_COMP register field. */
6727 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_LSB 6
6728 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_LD_COMP register field. */
6729 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_MSB 6
6730 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_LD_COMP register field. */
6731 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_WIDTH 1
6732 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_LD_COMP register field value. */
6733 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_SET_MSK 0x00000040
6734 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_LD_COMP register field value. */
6735 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_CLR_MSK 0xffffffbf
6736 /* The reset value of the ALT_NAND_STAT_INTR_EN1_LD_COMP register field. */
6737 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_RESET 0x0
6738 /* Extracts the ALT_NAND_STAT_INTR_EN1_LD_COMP field value from a register. */
6739 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
6740 /* Produces a ALT_NAND_STAT_INTR_EN1_LD_COMP register field value suitable for setting the register. */
6741 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
6742 
6743 /*
6744  * Field : program_comp
6745  *
6746  * Device finished the last issued program command.
6747  *
6748  * Field Access Macros:
6749  *
6750  */
6751 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field. */
6752 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_LSB 7
6753 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field. */
6754 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_MSB 7
6755 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field. */
6756 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_WIDTH 1
6757 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field value. */
6758 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_SET_MSK 0x00000080
6759 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field value. */
6760 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_CLR_MSK 0xffffff7f
6761 /* The reset value of the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field. */
6762 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_RESET 0x0
6763 /* Extracts the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP field value from a register. */
6764 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
6765 /* Produces a ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field value suitable for setting the register. */
6766 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
6767 
6768 /*
6769  * Field : erase_comp
6770  *
6771  * Device erase operation complete
6772  *
6773  * Field Access Macros:
6774  *
6775  */
6776 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field. */
6777 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_LSB 8
6778 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field. */
6779 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_MSB 8
6780 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field. */
6781 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_WIDTH 1
6782 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field value. */
6783 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_SET_MSK 0x00000100
6784 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field value. */
6785 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_CLR_MSK 0xfffffeff
6786 /* The reset value of the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field. */
6787 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_RESET 0x0
6788 /* Extracts the ALT_NAND_STAT_INTR_EN1_ERASE_COMP field value from a register. */
6789 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
6790 /* Produces a ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field value suitable for setting the register. */
6791 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
6792 
6793 /*
6794  * Field : pipe_cpybck_cmd_comp
6795  *
6796  * A pipeline command or a copyback bank command has completed on this particular
6797  * bank
6798  *
6799  * Field Access Macros:
6800  *
6801  */
6802 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field. */
6803 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_LSB 9
6804 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field. */
6805 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_MSB 9
6806 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field. */
6807 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_WIDTH 1
6808 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field value. */
6809 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
6810 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field value. */
6811 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
6812 /* The reset value of the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field. */
6813 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_RESET 0x0
6814 /* Extracts the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP field value from a register. */
6815 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
6816 /* Produces a ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
6817 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
6818 
6819 /*
6820  * Field : locked_blk
6821  *
6822  * The address to program or erase operation is to a locked block and the operation
6823  * failed due to this reason
6824  *
6825  * Field Access Macros:
6826  *
6827  */
6828 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field. */
6829 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_LSB 10
6830 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field. */
6831 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_MSB 10
6832 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field. */
6833 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_WIDTH 1
6834 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field value. */
6835 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_SET_MSK 0x00000400
6836 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field value. */
6837 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_CLR_MSK 0xfffffbff
6838 /* The reset value of the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field. */
6839 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_RESET 0x0
6840 /* Extracts the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK field value from a register. */
6841 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
6842 /* Produces a ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field value suitable for setting the register. */
6843 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
6844 
6845 /*
6846  * Field : unsup_cmd
6847  *
6848  * An unsupported command was received. This interrupt is set when an invalid
6849  * command is received, or when a command sequence is broken.
6850  *
6851  * Field Access Macros:
6852  *
6853  */
6854 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field. */
6855 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_LSB 11
6856 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field. */
6857 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_MSB 11
6858 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field. */
6859 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_WIDTH 1
6860 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field value. */
6861 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_SET_MSK 0x00000800
6862 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field value. */
6863 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_CLR_MSK 0xfffff7ff
6864 /* The reset value of the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field. */
6865 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_RESET 0x0
6866 /* Extracts the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD field value from a register. */
6867 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
6868 /* Produces a ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field value suitable for setting the register. */
6869 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
6870 
6871 /*
6872  * Field : INT_act
6873  *
6874  * R/B pin of device transitioned from low to high
6875  *
6876  * Field Access Macros:
6877  *
6878  */
6879 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_INT_ACT register field. */
6880 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_LSB 12
6881 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_INT_ACT register field. */
6882 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_MSB 12
6883 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_INT_ACT register field. */
6884 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_WIDTH 1
6885 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_INT_ACT register field value. */
6886 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_SET_MSK 0x00001000
6887 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_INT_ACT register field value. */
6888 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_CLR_MSK 0xffffefff
6889 /* The reset value of the ALT_NAND_STAT_INTR_EN1_INT_ACT register field. */
6890 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_RESET 0x0
6891 /* Extracts the ALT_NAND_STAT_INTR_EN1_INT_ACT field value from a register. */
6892 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
6893 /* Produces a ALT_NAND_STAT_INTR_EN1_INT_ACT register field value suitable for setting the register. */
6894 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
6895 
6896 /*
6897  * Field : rst_comp
6898  *
6899  * A reset command has completed on this bank
6900  *
6901  * Field Access Macros:
6902  *
6903  */
6904 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_RST_COMP register field. */
6905 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_LSB 13
6906 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_RST_COMP register field. */
6907 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_MSB 13
6908 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_RST_COMP register field. */
6909 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_WIDTH 1
6910 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_RST_COMP register field value. */
6911 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_SET_MSK 0x00002000
6912 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_RST_COMP register field value. */
6913 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_CLR_MSK 0xffffdfff
6914 /* The reset value of the ALT_NAND_STAT_INTR_EN1_RST_COMP register field. */
6915 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_RESET 0x1
6916 /* Extracts the ALT_NAND_STAT_INTR_EN1_RST_COMP field value from a register. */
6917 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
6918 /* Produces a ALT_NAND_STAT_INTR_EN1_RST_COMP register field value suitable for setting the register. */
6919 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
6920 
6921 /*
6922  * Field : pipe_cmd_err
6923  *
6924  * A pipeline command sequence has been violated. This occurs when Map 01 page
6925  * read/write address does not match the corresponding expected address from the
6926  * pipeline commands issued earlier.
6927  *
6928  * Field Access Macros:
6929  *
6930  */
6931 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field. */
6932 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_LSB 14
6933 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field. */
6934 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_MSB 14
6935 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field. */
6936 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_WIDTH 1
6937 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field value. */
6938 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_SET_MSK 0x00004000
6939 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field value. */
6940 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
6941 /* The reset value of the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field. */
6942 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_RESET 0x0
6943 /* Extracts the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR field value from a register. */
6944 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
6945 /* Produces a ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field value suitable for setting the register. */
6946 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
6947 
6948 /*
6949  * Field : page_xfer_inc
6950  *
6951  * For every page of data transfer to or from the device, this bit will be set.
6952  *
6953  * Field Access Macros:
6954  *
6955  */
6956 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field. */
6957 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_LSB 15
6958 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field. */
6959 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_MSB 15
6960 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field. */
6961 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_WIDTH 1
6962 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field value. */
6963 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_SET_MSK 0x00008000
6964 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field value. */
6965 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_CLR_MSK 0xffff7fff
6966 /* The reset value of the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field. */
6967 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_RESET 0x0
6968 /* Extracts the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC field value from a register. */
6969 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
6970 /* Produces a ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field value suitable for setting the register. */
6971 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
6972 
6973 #ifndef __ASSEMBLY__
6974 /*
6975  * WARNING: The C register and register group struct declarations are provided for
6976  * convenience and illustrative purposes. They should, however, be used with
6977  * caution as the C language standard provides no guarantees about the alignment or
6978  * atomicity of device memory accesses. The recommended practice for writing
6979  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6980  * alt_write_word() functions.
6981  *
6982  * The struct declaration for register ALT_NAND_STAT_INTR_EN1.
6983  */
6984 struct ALT_NAND_STAT_INTR_EN1_s
6985 {
6986  uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR */
6987  uint32_t : 1; /* *UNDEFINED* */
6988  uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP */
6989  uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_EN1_TIME_OUT */
6990  uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL */
6991  uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_EN1_ERASE_FAIL */
6992  uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_EN1_LD_COMP */
6993  uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP */
6994  uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_EN1_ERASE_COMP */
6995  uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP */
6996  uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_EN1_LOCKED_BLK */
6997  uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_EN1_UNSUP_CMD */
6998  uint32_t INT_act : 1; /* ALT_NAND_STAT_INTR_EN1_INT_ACT */
6999  uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_EN1_RST_COMP */
7000  uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR */
7001  uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC */
7002  uint32_t : 16; /* *UNDEFINED* */
7003 };
7004 
7005 /* The typedef declaration for register ALT_NAND_STAT_INTR_EN1. */
7006 typedef volatile struct ALT_NAND_STAT_INTR_EN1_s ALT_NAND_STAT_INTR_EN1_t;
7007 #endif /* __ASSEMBLY__ */
7008 
7009 /* The byte offset of the ALT_NAND_STAT_INTR_EN1 register from the beginning of the component. */
7010 #define ALT_NAND_STAT_INTR_EN1_OFST 0x70
7011 
7012 /*
7013  * Register : page_cnt1
7014  *
7015  * Decrementing page count bank 1
7016  *
7017  * Register Layout
7018  *
7019  * Bits | Access | Reset | Description
7020  * :-------|:-------|:------|:------------------------------
7021  * [7:0] | R | 0x0 | ALT_NAND_STAT_PAGE_CNT1_VALUE
7022  * [31:8] | ??? | 0x0 | *UNDEFINED*
7023  *
7024  */
7025 /*
7026  * Field : value
7027  *
7028  * Maintains a decrementing count of the number of pages in the multi-page
7029  * (pipeline and copyback) command being executed.
7030  *
7031  * Field Access Macros:
7032  *
7033  */
7034 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_PAGE_CNT1_VALUE register field. */
7035 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_LSB 0
7036 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_PAGE_CNT1_VALUE register field. */
7037 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_MSB 7
7038 /* The width in bits of the ALT_NAND_STAT_PAGE_CNT1_VALUE register field. */
7039 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_WIDTH 8
7040 /* The mask used to set the ALT_NAND_STAT_PAGE_CNT1_VALUE register field value. */
7041 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_SET_MSK 0x000000ff
7042 /* The mask used to clear the ALT_NAND_STAT_PAGE_CNT1_VALUE register field value. */
7043 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_CLR_MSK 0xffffff00
7044 /* The reset value of the ALT_NAND_STAT_PAGE_CNT1_VALUE register field. */
7045 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_RESET 0x0
7046 /* Extracts the ALT_NAND_STAT_PAGE_CNT1_VALUE field value from a register. */
7047 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
7048 /* Produces a ALT_NAND_STAT_PAGE_CNT1_VALUE register field value suitable for setting the register. */
7049 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_SET(value) (((value) << 0) & 0x000000ff)
7050 
7051 #ifndef __ASSEMBLY__
7052 /*
7053  * WARNING: The C register and register group struct declarations are provided for
7054  * convenience and illustrative purposes. They should, however, be used with
7055  * caution as the C language standard provides no guarantees about the alignment or
7056  * atomicity of device memory accesses. The recommended practice for writing
7057  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7058  * alt_write_word() functions.
7059  *
7060  * The struct declaration for register ALT_NAND_STAT_PAGE_CNT1.
7061  */
7062 struct ALT_NAND_STAT_PAGE_CNT1_s
7063 {
7064  const uint32_t value : 8; /* ALT_NAND_STAT_PAGE_CNT1_VALUE */
7065  uint32_t : 24; /* *UNDEFINED* */
7066 };
7067 
7068 /* The typedef declaration for register ALT_NAND_STAT_PAGE_CNT1. */
7069 typedef volatile struct ALT_NAND_STAT_PAGE_CNT1_s ALT_NAND_STAT_PAGE_CNT1_t;
7070 #endif /* __ASSEMBLY__ */
7071 
7072 /* The byte offset of the ALT_NAND_STAT_PAGE_CNT1 register from the beginning of the component. */
7073 #define ALT_NAND_STAT_PAGE_CNT1_OFST 0x80
7074 
7075 /*
7076  * Register : err_page_addr1
7077  *
7078  * Erred page address bank 1
7079  *
7080  * Register Layout
7081  *
7082  * Bits | Access | Reset | Description
7083  * :--------|:-------|:------|:-----------------------------------
7084  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE
7085  * [31:16] | ??? | 0x0 | *UNDEFINED*
7086  *
7087  */
7088 /*
7089  * Field : value
7090  *
7091  * Holds the page address that resulted in a failure on program or erase operation.
7092  *
7093  * Field Access Macros:
7094  *
7095  */
7096 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field. */
7097 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_LSB 0
7098 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field. */
7099 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_MSB 15
7100 /* The width in bits of the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field. */
7101 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_WIDTH 16
7102 /* The mask used to set the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field value. */
7103 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_SET_MSK 0x0000ffff
7104 /* The mask used to clear the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field value. */
7105 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_CLR_MSK 0xffff0000
7106 /* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field. */
7107 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_RESET 0x0
7108 /* Extracts the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE field value from a register. */
7109 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
7110 /* Produces a ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field value suitable for setting the register. */
7111 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
7112 
7113 #ifndef __ASSEMBLY__
7114 /*
7115  * WARNING: The C register and register group struct declarations are provided for
7116  * convenience and illustrative purposes. They should, however, be used with
7117  * caution as the C language standard provides no guarantees about the alignment or
7118  * atomicity of device memory accesses. The recommended practice for writing
7119  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7120  * alt_write_word() functions.
7121  *
7122  * The struct declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR1.
7123  */
7124 struct ALT_NAND_STAT_ERR_PAGE_ADDR1_s
7125 {
7126  const uint32_t value : 16; /* ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE */
7127  uint32_t : 16; /* *UNDEFINED* */
7128 };
7129 
7130 /* The typedef declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR1. */
7131 typedef volatile struct ALT_NAND_STAT_ERR_PAGE_ADDR1_s ALT_NAND_STAT_ERR_PAGE_ADDR1_t;
7132 #endif /* __ASSEMBLY__ */
7133 
7134 /* The byte offset of the ALT_NAND_STAT_ERR_PAGE_ADDR1 register from the beginning of the component. */
7135 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_OFST 0x90
7136 
7137 /*
7138  * Register : err_block_addr1
7139  *
7140  * Erred block address bank 1
7141  *
7142  * Register Layout
7143  *
7144  * Bits | Access | Reset | Description
7145  * :--------|:-------|:------|:------------------------------------
7146  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE
7147  * [31:16] | ??? | 0x0 | *UNDEFINED*
7148  *
7149  */
7150 /*
7151  * Field : value
7152  *
7153  * Holds the block address that resulted in a failure on program or erase
7154  * operation.
7155  *
7156  * Field Access Macros:
7157  *
7158  */
7159 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field. */
7160 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_LSB 0
7161 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field. */
7162 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_MSB 15
7163 /* The width in bits of the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field. */
7164 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_WIDTH 16
7165 /* The mask used to set the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field value. */
7166 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_SET_MSK 0x0000ffff
7167 /* The mask used to clear the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field value. */
7168 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_CLR_MSK 0xffff0000
7169 /* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field. */
7170 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_RESET 0x0
7171 /* Extracts the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE field value from a register. */
7172 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
7173 /* Produces a ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field value suitable for setting the register. */
7174 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
7175 
7176 #ifndef __ASSEMBLY__
7177 /*
7178  * WARNING: The C register and register group struct declarations are provided for
7179  * convenience and illustrative purposes. They should, however, be used with
7180  * caution as the C language standard provides no guarantees about the alignment or
7181  * atomicity of device memory accesses. The recommended practice for writing
7182  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7183  * alt_write_word() functions.
7184  *
7185  * The struct declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR1.
7186  */
7187 struct ALT_NAND_STAT_ERR_BLOCK_ADDR1_s
7188 {
7189  const uint32_t value : 16; /* ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE */
7190  uint32_t : 16; /* *UNDEFINED* */
7191 };
7192 
7193 /* The typedef declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR1. */
7194 typedef volatile struct ALT_NAND_STAT_ERR_BLOCK_ADDR1_s ALT_NAND_STAT_ERR_BLOCK_ADDR1_t;
7195 #endif /* __ASSEMBLY__ */
7196 
7197 /* The byte offset of the ALT_NAND_STAT_ERR_BLOCK_ADDR1 register from the beginning of the component. */
7198 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_OFST 0xa0
7199 
7200 /*
7201  * Register : intr_status2
7202  *
7203  * Interrupt status register for bank 2
7204  *
7205  * Register Layout
7206  *
7207  * Bits | Access | Reset | Description
7208  * :--------|:-------|:------|:----------------------------------------------
7209  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR
7210  * [1] | ??? | 0x0 | *UNDEFINED*
7211  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP
7212  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_TIME_OUT
7213  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL
7214  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL
7215  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_LD_COMP
7216  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP
7217  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_ERASE_COMP
7218  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP
7219  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK
7220  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD
7221  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_INT_ACT
7222  * [13] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_RST_COMP
7223  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR
7224  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC
7225  * [31:16] | ??? | 0x0 | *UNDEFINED*
7226  *
7227  */
7228 /*
7229  * Field : ecc_uncor_err
7230  *
7231  * Ecc logic detected uncorrectable error while reading data from flash device.
7232  *
7233  * Field Access Macros:
7234  *
7235  */
7236 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR register field. */
7237 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_LSB 0
7238 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR register field. */
7239 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_MSB 0
7240 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR register field. */
7241 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_WIDTH 1
7242 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR register field value. */
7243 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_SET_MSK 0x00000001
7244 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR register field value. */
7245 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
7246 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR register field. */
7247 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_RESET 0x0
7248 /* Extracts the ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR field value from a register. */
7249 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
7250 /* Produces a ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR register field value suitable for setting the register. */
7251 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
7252 
7253 /*
7254  * Field : dma_cmd_comp
7255  *
7256  * Not implemented.
7257  *
7258  * Field Access Macros:
7259  *
7260  */
7261 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP register field. */
7262 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_LSB 2
7263 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP register field. */
7264 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_MSB 2
7265 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP register field. */
7266 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_WIDTH 1
7267 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP register field value. */
7268 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_SET_MSK 0x00000004
7269 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP register field value. */
7270 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_CLR_MSK 0xfffffffb
7271 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP register field. */
7272 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_RESET 0x0
7273 /* Extracts the ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP field value from a register. */
7274 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
7275 /* Produces a ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP register field value suitable for setting the register. */
7276 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
7277 
7278 /*
7279  * Field : time_out
7280  *
7281  * Watchdog timer has triggered in the controller due to one of the reasons like
7282  * device not responding or controller state machine did not get back to idle
7283  *
7284  * Field Access Macros:
7285  *
7286  */
7287 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_TIME_OUT register field. */
7288 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_LSB 3
7289 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_TIME_OUT register field. */
7290 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_MSB 3
7291 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_TIME_OUT register field. */
7292 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_WIDTH 1
7293 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_TIME_OUT register field value. */
7294 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_SET_MSK 0x00000008
7295 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_TIME_OUT register field value. */
7296 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_CLR_MSK 0xfffffff7
7297 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_TIME_OUT register field. */
7298 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_RESET 0x0
7299 /* Extracts the ALT_NAND_STAT_INTR_STAT2_TIME_OUT field value from a register. */
7300 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
7301 /* Produces a ALT_NAND_STAT_INTR_STAT2_TIME_OUT register field value suitable for setting the register. */
7302 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
7303 
7304 /*
7305  * Field : program_fail
7306  *
7307  * Program failure occurred in the device on issuance of a program command.
7308  * err_block_addr and err_page_addr contain the block address and page address that
7309  * failed program operation.
7310  *
7311  * Field Access Macros:
7312  *
7313  */
7314 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL register field. */
7315 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_LSB 4
7316 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL register field. */
7317 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_MSB 4
7318 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL register field. */
7319 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_WIDTH 1
7320 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL register field value. */
7321 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_SET_MSK 0x00000010
7322 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL register field value. */
7323 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_CLR_MSK 0xffffffef
7324 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL register field. */
7325 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_RESET 0x0
7326 /* Extracts the ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL field value from a register. */
7327 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
7328 /* Produces a ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL register field value suitable for setting the register. */
7329 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
7330 
7331 /*
7332  * Field : erase_fail
7333  *
7334  * Erase failure occurred in the device on issuance of a erase command.
7335  * err_block_addr and err_page_addr contain the block address and page address that
7336  * failed erase operation.
7337  *
7338  * Field Access Macros:
7339  *
7340  */
7341 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL register field. */
7342 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_LSB 5
7343 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL register field. */
7344 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_MSB 5
7345 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL register field. */
7346 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_WIDTH 1
7347 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL register field value. */
7348 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_SET_MSK 0x00000020
7349 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL register field value. */
7350 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_CLR_MSK 0xffffffdf
7351 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL register field. */
7352 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_RESET 0x0
7353 /* Extracts the ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL field value from a register. */
7354 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
7355 /* Produces a ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL register field value suitable for setting the register. */
7356 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
7357 
7358 /*
7359  * Field : load_comp
7360  *
7361  * Device finished the last issued load command.
7362  *
7363  * Field Access Macros:
7364  *
7365  */
7366 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_LD_COMP register field. */
7367 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_LSB 6
7368 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_LD_COMP register field. */
7369 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_MSB 6
7370 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_LD_COMP register field. */
7371 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_WIDTH 1
7372 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_LD_COMP register field value. */
7373 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_SET_MSK 0x00000040
7374 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_LD_COMP register field value. */
7375 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_CLR_MSK 0xffffffbf
7376 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_LD_COMP register field. */
7377 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_RESET 0x0
7378 /* Extracts the ALT_NAND_STAT_INTR_STAT2_LD_COMP field value from a register. */
7379 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
7380 /* Produces a ALT_NAND_STAT_INTR_STAT2_LD_COMP register field value suitable for setting the register. */
7381 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
7382 
7383 /*
7384  * Field : program_comp
7385  *
7386  * Device finished the last issued program command.
7387  *
7388  * Field Access Macros:
7389  *
7390  */
7391 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP register field. */
7392 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_LSB 7
7393 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP register field. */
7394 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_MSB 7
7395 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP register field. */
7396 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_WIDTH 1
7397 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP register field value. */
7398 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_SET_MSK 0x00000080
7399 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP register field value. */
7400 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_CLR_MSK 0xffffff7f
7401 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP register field. */
7402 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_RESET 0x0
7403 /* Extracts the ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP field value from a register. */
7404 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
7405 /* Produces a ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP register field value suitable for setting the register. */
7406 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
7407 
7408 /*
7409  * Field : erase_comp
7410  *
7411  * Device erase operation complete
7412  *
7413  * Field Access Macros:
7414  *
7415  */
7416 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_ERASE_COMP register field. */
7417 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_LSB 8
7418 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_ERASE_COMP register field. */
7419 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_MSB 8
7420 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_ERASE_COMP register field. */
7421 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_WIDTH 1
7422 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_ERASE_COMP register field value. */
7423 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_SET_MSK 0x00000100
7424 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_ERASE_COMP register field value. */
7425 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_CLR_MSK 0xfffffeff
7426 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_ERASE_COMP register field. */
7427 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_RESET 0x0
7428 /* Extracts the ALT_NAND_STAT_INTR_STAT2_ERASE_COMP field value from a register. */
7429 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
7430 /* Produces a ALT_NAND_STAT_INTR_STAT2_ERASE_COMP register field value suitable for setting the register. */
7431 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
7432 
7433 /*
7434  * Field : pipe_cpybck_cmd_comp
7435  *
7436  * A pipeline command or a copyback bank command has completed on this particular
7437  * bank
7438  *
7439  * Field Access Macros:
7440  *
7441  */
7442 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP register field. */
7443 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_LSB 9
7444 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP register field. */
7445 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_MSB 9
7446 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP register field. */
7447 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_WIDTH 1
7448 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP register field value. */
7449 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
7450 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP register field value. */
7451 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
7452 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP register field. */
7453 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_RESET 0x0
7454 /* Extracts the ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP field value from a register. */
7455 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
7456 /* Produces a ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
7457 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
7458 
7459 /*
7460  * Field : locked_blk
7461  *
7462  * The address to program or erase operation is to a locked block and the operation
7463  * failed due to this reason
7464  *
7465  * Field Access Macros:
7466  *
7467  */
7468 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK register field. */
7469 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_LSB 10
7470 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK register field. */
7471 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_MSB 10
7472 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK register field. */
7473 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_WIDTH 1
7474 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK register field value. */
7475 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_SET_MSK 0x00000400
7476 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK register field value. */
7477 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_CLR_MSK 0xfffffbff
7478 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK register field. */
7479 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_RESET 0x0
7480 /* Extracts the ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK field value from a register. */
7481 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
7482 /* Produces a ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK register field value suitable for setting the register. */
7483 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
7484 
7485 /*
7486  * Field : unsup_cmd
7487  *
7488  * An unsupported command was received. This interrupt is set when an invalid
7489  * command is received, or when a command sequence is broken.
7490  *
7491  * Field Access Macros:
7492  *
7493  */
7494 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD register field. */
7495 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_LSB 11
7496 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD register field. */
7497 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_MSB 11
7498 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD register field. */
7499 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_WIDTH 1
7500 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD register field value. */
7501 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_SET_MSK 0x00000800
7502 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD register field value. */
7503 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_CLR_MSK 0xfffff7ff
7504 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD register field. */
7505 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_RESET 0x0
7506 /* Extracts the ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD field value from a register. */
7507 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
7508 /* Produces a ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD register field value suitable for setting the register. */
7509 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
7510 
7511 /*
7512  * Field : INT_act
7513  *
7514  * R/B pin of device transitioned from low to high
7515  *
7516  * Field Access Macros:
7517  *
7518  */
7519 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_INT_ACT register field. */
7520 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_LSB 12
7521 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_INT_ACT register field. */
7522 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_MSB 12
7523 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_INT_ACT register field. */
7524 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_WIDTH 1
7525 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_INT_ACT register field value. */
7526 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_SET_MSK 0x00001000
7527 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_INT_ACT register field value. */
7528 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_CLR_MSK 0xffffefff
7529 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_INT_ACT register field. */
7530 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_RESET 0x0
7531 /* Extracts the ALT_NAND_STAT_INTR_STAT2_INT_ACT field value from a register. */
7532 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
7533 /* Produces a ALT_NAND_STAT_INTR_STAT2_INT_ACT register field value suitable for setting the register. */
7534 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
7535 
7536 /*
7537  * Field : rst_comp
7538  *
7539  * The NAND Flash Memory Controller has completed its reset and initialization
7540  * process
7541  *
7542  * Field Access Macros:
7543  *
7544  */
7545 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_RST_COMP register field. */
7546 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_LSB 13
7547 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_RST_COMP register field. */
7548 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_MSB 13
7549 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_RST_COMP register field. */
7550 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_WIDTH 1
7551 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_RST_COMP register field value. */
7552 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_SET_MSK 0x00002000
7553 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_RST_COMP register field value. */
7554 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_CLR_MSK 0xffffdfff
7555 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_RST_COMP register field. */
7556 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_RESET 0x0
7557 /* Extracts the ALT_NAND_STAT_INTR_STAT2_RST_COMP field value from a register. */
7558 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
7559 /* Produces a ALT_NAND_STAT_INTR_STAT2_RST_COMP register field value suitable for setting the register. */
7560 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
7561 
7562 /*
7563  * Field : pipe_cmd_err
7564  *
7565  * A pipeline command sequence has been violated. This occurs when Map 01 page
7566  * read/write address does not match the corresponding expected address from the
7567  * pipeline commands issued earlier.
7568  *
7569  * Field Access Macros:
7570  *
7571  */
7572 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR register field. */
7573 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_LSB 14
7574 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR register field. */
7575 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_MSB 14
7576 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR register field. */
7577 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_WIDTH 1
7578 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR register field value. */
7579 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_SET_MSK 0x00004000
7580 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR register field value. */
7581 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
7582 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR register field. */
7583 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_RESET 0x0
7584 /* Extracts the ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR field value from a register. */
7585 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
7586 /* Produces a ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR register field value suitable for setting the register. */
7587 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
7588 
7589 /*
7590  * Field : page_xfer_inc
7591  *
7592  * For every page of data transfer to or from the device, this bit will be set.
7593  *
7594  * Field Access Macros:
7595  *
7596  */
7597 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC register field. */
7598 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_LSB 15
7599 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC register field. */
7600 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_MSB 15
7601 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC register field. */
7602 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_WIDTH 1
7603 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC register field value. */
7604 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_SET_MSK 0x00008000
7605 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC register field value. */
7606 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_CLR_MSK 0xffff7fff
7607 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC register field. */
7608 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_RESET 0x0
7609 /* Extracts the ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC field value from a register. */
7610 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
7611 /* Produces a ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC register field value suitable for setting the register. */
7612 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
7613 
7614 #ifndef __ASSEMBLY__
7615 /*
7616  * WARNING: The C register and register group struct declarations are provided for
7617  * convenience and illustrative purposes. They should, however, be used with
7618  * caution as the C language standard provides no guarantees about the alignment or
7619  * atomicity of device memory accesses. The recommended practice for writing
7620  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7621  * alt_write_word() functions.
7622  *
7623  * The struct declaration for register ALT_NAND_STAT_INTR_STAT2.
7624  */
7625 struct ALT_NAND_STAT_INTR_STAT2_s
7626 {
7627  uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR */
7628  uint32_t : 1; /* *UNDEFINED* */
7629  uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP */
7630  uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_STAT2_TIME_OUT */
7631  uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL */
7632  uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL */
7633  uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_STAT2_LD_COMP */
7634  uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP */
7635  uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_STAT2_ERASE_COMP */
7636  uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP */
7637  uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK */
7638  uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD */
7639  uint32_t INT_act : 1; /* ALT_NAND_STAT_INTR_STAT2_INT_ACT */
7640  uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_STAT2_RST_COMP */
7641  uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR */
7642  uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC */
7643  uint32_t : 16; /* *UNDEFINED* */
7644 };
7645 
7646 /* The typedef declaration for register ALT_NAND_STAT_INTR_STAT2. */
7647 typedef volatile struct ALT_NAND_STAT_INTR_STAT2_s ALT_NAND_STAT_INTR_STAT2_t;
7648 #endif /* __ASSEMBLY__ */
7649 
7650 /* The byte offset of the ALT_NAND_STAT_INTR_STAT2 register from the beginning of the component. */
7651 #define ALT_NAND_STAT_INTR_STAT2_OFST 0xb0
7652 
7653 /*
7654  * Register : intr_en2
7655  *
7656  * Enables corresponding interrupt bit in interrupt register for bank 2
7657  *
7658  * Register Layout
7659  *
7660  * Bits | Access | Reset | Description
7661  * :--------|:-------|:------|:--------------------------------------------
7662  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR
7663  * [1] | ??? | 0x0 | *UNDEFINED*
7664  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP
7665  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_TIME_OUT
7666  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL
7667  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_ERASE_FAIL
7668  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_LD_COMP
7669  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP
7670  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_ERASE_COMP
7671  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP
7672  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_LOCKED_BLK
7673  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_UNSUP_CMD
7674  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_INT_ACT
7675  * [13] | RW | 0x1 | ALT_NAND_STAT_INTR_EN2_RST_COMP
7676  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR
7677  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC
7678  * [31:16] | ??? | 0x0 | *UNDEFINED*
7679  *
7680  */
7681 /*
7682  * Field : ecc_uncor_err
7683  *
7684  * If set, Controller will interrupt processor when Ecc logic detects uncorrectable
7685  * error.
7686  *
7687  * Field Access Macros:
7688  *
7689  */
7690 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field. */
7691 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_LSB 0
7692 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field. */
7693 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_MSB 0
7694 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field. */
7695 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_WIDTH 1
7696 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field value. */
7697 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_SET_MSK 0x00000001
7698 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field value. */
7699 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
7700 /* The reset value of the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field. */
7701 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_RESET 0x0
7702 /* Extracts the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR field value from a register. */
7703 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
7704 /* Produces a ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field value suitable for setting the register. */
7705 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
7706 
7707 /*
7708  * Field : dma_cmd_comp
7709  *
7710  * Not implemented.
7711  *
7712  * Field Access Macros:
7713  *
7714  */
7715 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field. */
7716 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_LSB 2
7717 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field. */
7718 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_MSB 2
7719 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field. */
7720 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_WIDTH 1
7721 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field value. */
7722 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_SET_MSK 0x00000004
7723 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field value. */
7724 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_CLR_MSK 0xfffffffb
7725 /* The reset value of the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field. */
7726 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_RESET 0x0
7727 /* Extracts the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP field value from a register. */
7728 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
7729 /* Produces a ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field value suitable for setting the register. */
7730 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
7731 
7732 /*
7733  * Field : time_out
7734  *
7735  * Watchdog timer has triggered in the controller due to one of the reasons like
7736  * device not responding or controller state machine did not get back to idle
7737  *
7738  * Field Access Macros:
7739  *
7740  */
7741 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field. */
7742 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_LSB 3
7743 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field. */
7744 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_MSB 3
7745 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field. */
7746 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_WIDTH 1
7747 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field value. */
7748 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_SET_MSK 0x00000008
7749 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field value. */
7750 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_CLR_MSK 0xfffffff7
7751 /* The reset value of the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field. */
7752 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_RESET 0x0
7753 /* Extracts the ALT_NAND_STAT_INTR_EN2_TIME_OUT field value from a register. */
7754 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
7755 /* Produces a ALT_NAND_STAT_INTR_EN2_TIME_OUT register field value suitable for setting the register. */
7756 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
7757 
7758 /*
7759  * Field : program_fail
7760  *
7761  * Program failure occurred in the device on issuance of a program command.
7762  * err_block_addr and err_page_addr contain the block address and page address that
7763  * failed program operation.
7764  *
7765  * Field Access Macros:
7766  *
7767  */
7768 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field. */
7769 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_LSB 4
7770 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field. */
7771 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_MSB 4
7772 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field. */
7773 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_WIDTH 1
7774 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field value. */
7775 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_SET_MSK 0x00000010
7776 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field value. */
7777 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_CLR_MSK 0xffffffef
7778 /* The reset value of the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field. */
7779 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_RESET 0x0
7780 /* Extracts the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL field value from a register. */
7781 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
7782 /* Produces a ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field value suitable for setting the register. */
7783 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
7784 
7785 /*
7786  * Field : erase_fail
7787  *
7788  * Erase failure occurred in the device on issuance of a erase command.
7789  * err_block_addr and err_page_addr contain the block address and page address that
7790  * failed erase operation.
7791  *
7792  * Field Access Macros:
7793  *
7794  */
7795 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field. */
7796 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_LSB 5
7797 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field. */
7798 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_MSB 5
7799 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field. */
7800 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_WIDTH 1
7801 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field value. */
7802 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_SET_MSK 0x00000020
7803 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field value. */
7804 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_CLR_MSK 0xffffffdf
7805 /* The reset value of the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field. */
7806 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_RESET 0x0
7807 /* Extracts the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL field value from a register. */
7808 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
7809 /* Produces a ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field value suitable for setting the register. */
7810 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
7811 
7812 /*
7813  * Field : load_comp
7814  *
7815  * Device finished the last issued load command.
7816  *
7817  * Field Access Macros:
7818  *
7819  */
7820 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_LD_COMP register field. */
7821 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_LSB 6
7822 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_LD_COMP register field. */
7823 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_MSB 6
7824 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_LD_COMP register field. */
7825 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_WIDTH 1
7826 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_LD_COMP register field value. */
7827 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_SET_MSK 0x00000040
7828 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_LD_COMP register field value. */
7829 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_CLR_MSK 0xffffffbf
7830 /* The reset value of the ALT_NAND_STAT_INTR_EN2_LD_COMP register field. */
7831 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_RESET 0x0
7832 /* Extracts the ALT_NAND_STAT_INTR_EN2_LD_COMP field value from a register. */
7833 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
7834 /* Produces a ALT_NAND_STAT_INTR_EN2_LD_COMP register field value suitable for setting the register. */
7835 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
7836 
7837 /*
7838  * Field : program_comp
7839  *
7840  * Device finished the last issued program command.
7841  *
7842  * Field Access Macros:
7843  *
7844  */
7845 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field. */
7846 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_LSB 7
7847 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field. */
7848 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_MSB 7
7849 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field. */
7850 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_WIDTH 1
7851 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field value. */
7852 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_SET_MSK 0x00000080
7853 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field value. */
7854 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_CLR_MSK 0xffffff7f
7855 /* The reset value of the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field. */
7856 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_RESET 0x0
7857 /* Extracts the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP field value from a register. */
7858 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
7859 /* Produces a ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field value suitable for setting the register. */
7860 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
7861 
7862 /*
7863  * Field : erase_comp
7864  *
7865  * Device erase operation complete
7866  *
7867  * Field Access Macros:
7868  *
7869  */
7870 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field. */
7871 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_LSB 8
7872 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field. */
7873 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_MSB 8
7874 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field. */
7875 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_WIDTH 1
7876 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field value. */
7877 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_SET_MSK 0x00000100
7878 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field value. */
7879 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_CLR_MSK 0xfffffeff
7880 /* The reset value of the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field. */
7881 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_RESET 0x0
7882 /* Extracts the ALT_NAND_STAT_INTR_EN2_ERASE_COMP field value from a register. */
7883 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
7884 /* Produces a ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field value suitable for setting the register. */
7885 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
7886 
7887 /*
7888  * Field : pipe_cpybck_cmd_comp
7889  *
7890  * A pipeline command or a copyback bank command has completed on this particular
7891  * bank
7892  *
7893  * Field Access Macros:
7894  *
7895  */
7896 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field. */
7897 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_LSB 9
7898 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field. */
7899 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_MSB 9
7900 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field. */
7901 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_WIDTH 1
7902 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field value. */
7903 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
7904 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field value. */
7905 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
7906 /* The reset value of the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field. */
7907 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_RESET 0x0
7908 /* Extracts the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP field value from a register. */
7909 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
7910 /* Produces a ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
7911 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
7912 
7913 /*
7914  * Field : locked_blk
7915  *
7916  * The address to program or erase operation is to a locked block and the operation
7917  * failed due to this reason
7918  *
7919  * Field Access Macros:
7920  *
7921  */
7922 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field. */
7923 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_LSB 10
7924 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field. */
7925 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_MSB 10
7926 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field. */
7927 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_WIDTH 1
7928 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field value. */
7929 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_SET_MSK 0x00000400
7930 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field value. */
7931 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_CLR_MSK 0xfffffbff
7932 /* The reset value of the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field. */
7933 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_RESET 0x0
7934 /* Extracts the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK field value from a register. */
7935 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
7936 /* Produces a ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field value suitable for setting the register. */
7937 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
7938 
7939 /*
7940  * Field : unsup_cmd
7941  *
7942  * An unsupported command was received. This interrupt is set when an invalid
7943  * command is received, or when a command sequence is broken.
7944  *
7945  * Field Access Macros:
7946  *
7947  */
7948 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field. */
7949 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_LSB 11
7950 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field. */
7951 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_MSB 11
7952 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field. */
7953 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_WIDTH 1
7954 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field value. */
7955 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_SET_MSK 0x00000800
7956 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field value. */
7957 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_CLR_MSK 0xfffff7ff
7958 /* The reset value of the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field. */
7959 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_RESET 0x0
7960 /* Extracts the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD field value from a register. */
7961 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
7962 /* Produces a ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field value suitable for setting the register. */
7963 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
7964 
7965 /*
7966  * Field : INT_act
7967  *
7968  * R/B pin of device transitioned from low to high
7969  *
7970  * Field Access Macros:
7971  *
7972  */
7973 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_INT_ACT register field. */
7974 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_LSB 12
7975 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_INT_ACT register field. */
7976 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_MSB 12
7977 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_INT_ACT register field. */
7978 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_WIDTH 1
7979 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_INT_ACT register field value. */
7980 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_SET_MSK 0x00001000
7981 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_INT_ACT register field value. */
7982 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_CLR_MSK 0xffffefff
7983 /* The reset value of the ALT_NAND_STAT_INTR_EN2_INT_ACT register field. */
7984 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_RESET 0x0
7985 /* Extracts the ALT_NAND_STAT_INTR_EN2_INT_ACT field value from a register. */
7986 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
7987 /* Produces a ALT_NAND_STAT_INTR_EN2_INT_ACT register field value suitable for setting the register. */
7988 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
7989 
7990 /*
7991  * Field : rst_comp
7992  *
7993  * A reset command has completed on this bank
7994  *
7995  * Field Access Macros:
7996  *
7997  */
7998 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_RST_COMP register field. */
7999 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_LSB 13
8000 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_RST_COMP register field. */
8001 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_MSB 13
8002 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_RST_COMP register field. */
8003 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_WIDTH 1
8004 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_RST_COMP register field value. */
8005 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_SET_MSK 0x00002000
8006 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_RST_COMP register field value. */
8007 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_CLR_MSK 0xffffdfff
8008 /* The reset value of the ALT_NAND_STAT_INTR_EN2_RST_COMP register field. */
8009 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_RESET 0x1
8010 /* Extracts the ALT_NAND_STAT_INTR_EN2_RST_COMP field value from a register. */
8011 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
8012 /* Produces a ALT_NAND_STAT_INTR_EN2_RST_COMP register field value suitable for setting the register. */
8013 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
8014 
8015 /*
8016  * Field : pipe_cmd_err
8017  *
8018  * A pipeline command sequence has been violated. This occurs when Map 01 page
8019  * read/write address does not match the corresponding expected address from the
8020  * pipeline commands issued earlier.
8021  *
8022  * Field Access Macros:
8023  *
8024  */
8025 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field. */
8026 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_LSB 14
8027 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field. */
8028 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_MSB 14
8029 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field. */
8030 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_WIDTH 1
8031 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field value. */
8032 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_SET_MSK 0x00004000
8033 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field value. */
8034 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
8035 /* The reset value of the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field. */
8036 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_RESET 0x0
8037 /* Extracts the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR field value from a register. */
8038 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
8039 /* Produces a ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field value suitable for setting the register. */
8040 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
8041 
8042 /*
8043  * Field : page_xfer_inc
8044  *
8045  * For every page of data transfer to or from the device, this bit will be set.
8046  *
8047  * Field Access Macros:
8048  *
8049  */
8050 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field. */
8051 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_LSB 15
8052 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field. */
8053 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_MSB 15
8054 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field. */
8055 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_WIDTH 1
8056 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field value. */
8057 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_SET_MSK 0x00008000
8058 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field value. */
8059 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_CLR_MSK 0xffff7fff
8060 /* The reset value of the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field. */
8061 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_RESET 0x0
8062 /* Extracts the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC field value from a register. */
8063 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
8064 /* Produces a ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field value suitable for setting the register. */
8065 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
8066 
8067 #ifndef __ASSEMBLY__
8068 /*
8069  * WARNING: The C register and register group struct declarations are provided for
8070  * convenience and illustrative purposes. They should, however, be used with
8071  * caution as the C language standard provides no guarantees about the alignment or
8072  * atomicity of device memory accesses. The recommended practice for writing
8073  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8074  * alt_write_word() functions.
8075  *
8076  * The struct declaration for register ALT_NAND_STAT_INTR_EN2.
8077  */
8078 struct ALT_NAND_STAT_INTR_EN2_s
8079 {
8080  uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR */
8081  uint32_t : 1; /* *UNDEFINED* */
8082  uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP */
8083  uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_EN2_TIME_OUT */
8084  uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL */
8085  uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_EN2_ERASE_FAIL */
8086  uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_EN2_LD_COMP */
8087  uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP */
8088  uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_EN2_ERASE_COMP */
8089  uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP */
8090  uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_EN2_LOCKED_BLK */
8091  uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_EN2_UNSUP_CMD */
8092  uint32_t INT_act : 1; /* ALT_NAND_STAT_INTR_EN2_INT_ACT */
8093  uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_EN2_RST_COMP */
8094  uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR */
8095  uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC */
8096  uint32_t : 16; /* *UNDEFINED* */
8097 };
8098 
8099 /* The typedef declaration for register ALT_NAND_STAT_INTR_EN2. */
8100 typedef volatile struct ALT_NAND_STAT_INTR_EN2_s ALT_NAND_STAT_INTR_EN2_t;
8101 #endif /* __ASSEMBLY__ */
8102 
8103 /* The byte offset of the ALT_NAND_STAT_INTR_EN2 register from the beginning of the component. */
8104 #define ALT_NAND_STAT_INTR_EN2_OFST 0xc0
8105 
8106 /*
8107  * Register : page_cnt2
8108  *
8109  * Decrementing page count bank 2
8110  *
8111  * Register Layout
8112  *
8113  * Bits | Access | Reset | Description
8114  * :-------|:-------|:------|:------------------------------
8115  * [7:0] | R | 0x0 | ALT_NAND_STAT_PAGE_CNT2_VALUE
8116  * [31:8] | ??? | 0x0 | *UNDEFINED*
8117  *
8118  */
8119 /*
8120  * Field : value
8121  *
8122  * Maintains a decrementing count of the number of pages in the multi-page
8123  * (pipeline and copyback) command being executed.
8124  *
8125  * Field Access Macros:
8126  *
8127  */
8128 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_PAGE_CNT2_VALUE register field. */
8129 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_LSB 0
8130 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_PAGE_CNT2_VALUE register field. */
8131 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_MSB 7
8132 /* The width in bits of the ALT_NAND_STAT_PAGE_CNT2_VALUE register field. */
8133 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_WIDTH 8
8134 /* The mask used to set the ALT_NAND_STAT_PAGE_CNT2_VALUE register field value. */
8135 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_SET_MSK 0x000000ff
8136 /* The mask used to clear the ALT_NAND_STAT_PAGE_CNT2_VALUE register field value. */
8137 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_CLR_MSK 0xffffff00
8138 /* The reset value of the ALT_NAND_STAT_PAGE_CNT2_VALUE register field. */
8139 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_RESET 0x0
8140 /* Extracts the ALT_NAND_STAT_PAGE_CNT2_VALUE field value from a register. */
8141 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
8142 /* Produces a ALT_NAND_STAT_PAGE_CNT2_VALUE register field value suitable for setting the register. */
8143 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_SET(value) (((value) << 0) & 0x000000ff)
8144 
8145 #ifndef __ASSEMBLY__
8146 /*
8147  * WARNING: The C register and register group struct declarations are provided for
8148  * convenience and illustrative purposes. They should, however, be used with
8149  * caution as the C language standard provides no guarantees about the alignment or
8150  * atomicity of device memory accesses. The recommended practice for writing
8151  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8152  * alt_write_word() functions.
8153  *
8154  * The struct declaration for register ALT_NAND_STAT_PAGE_CNT2.
8155  */
8156 struct ALT_NAND_STAT_PAGE_CNT2_s
8157 {
8158  const uint32_t value : 8; /* ALT_NAND_STAT_PAGE_CNT2_VALUE */
8159  uint32_t : 24; /* *UNDEFINED* */
8160 };
8161 
8162 /* The typedef declaration for register ALT_NAND_STAT_PAGE_CNT2. */
8163 typedef volatile struct ALT_NAND_STAT_PAGE_CNT2_s ALT_NAND_STAT_PAGE_CNT2_t;
8164 #endif /* __ASSEMBLY__ */
8165 
8166 /* The byte offset of the ALT_NAND_STAT_PAGE_CNT2 register from the beginning of the component. */
8167 #define ALT_NAND_STAT_PAGE_CNT2_OFST 0xd0
8168 
8169 /*
8170  * Register : err_page_addr2
8171  *
8172  * Erred page address bank 2
8173  *
8174  * Register Layout
8175  *
8176  * Bits | Access | Reset | Description
8177  * :--------|:-------|:------|:-----------------------------------
8178  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE
8179  * [31:16] | ??? | 0x0 | *UNDEFINED*
8180  *
8181  */
8182 /*
8183  * Field : value
8184  *
8185  * Holds the page address that resulted in a failure on program or erase operation.
8186  *
8187  * Field Access Macros:
8188  *
8189  */
8190 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field. */
8191 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_LSB 0
8192 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field. */
8193 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_MSB 15
8194 /* The width in bits of the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field. */
8195 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_WIDTH 16
8196 /* The mask used to set the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field value. */
8197 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_SET_MSK 0x0000ffff
8198 /* The mask used to clear the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field value. */
8199 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_CLR_MSK 0xffff0000
8200 /* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field. */
8201 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_RESET 0x0
8202 /* Extracts the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE field value from a register. */
8203 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
8204 /* Produces a ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field value suitable for setting the register. */
8205 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
8206 
8207 #ifndef __ASSEMBLY__
8208 /*
8209  * WARNING: The C register and register group struct declarations are provided for
8210  * convenience and illustrative purposes. They should, however, be used with
8211  * caution as the C language standard provides no guarantees about the alignment or
8212  * atomicity of device memory accesses. The recommended practice for writing
8213  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8214  * alt_write_word() functions.
8215  *
8216  * The struct declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR2.
8217  */
8218 struct ALT_NAND_STAT_ERR_PAGE_ADDR2_s
8219 {
8220  const uint32_t value : 16; /* ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE */
8221  uint32_t : 16; /* *UNDEFINED* */
8222 };
8223 
8224 /* The typedef declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR2. */
8225 typedef volatile struct ALT_NAND_STAT_ERR_PAGE_ADDR2_s ALT_NAND_STAT_ERR_PAGE_ADDR2_t;
8226 #endif /* __ASSEMBLY__ */
8227 
8228 /* The byte offset of the ALT_NAND_STAT_ERR_PAGE_ADDR2 register from the beginning of the component. */
8229 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_OFST 0xe0
8230 
8231 /*
8232  * Register : err_block_addr2
8233  *
8234  * Erred block address bank 2
8235  *
8236  * Register Layout
8237  *
8238  * Bits | Access | Reset | Description
8239  * :--------|:-------|:------|:------------------------------------
8240  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE
8241  * [31:16] | ??? | 0x0 | *UNDEFINED*
8242  *
8243  */
8244 /*
8245  * Field : value
8246  *
8247  * Holds the block address that resulted in a failure on program or erase
8248  * operation.
8249  *
8250  * Field Access Macros:
8251  *
8252  */
8253 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field. */
8254 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_LSB 0
8255 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field. */
8256 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_MSB 15
8257 /* The width in bits of the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field. */
8258 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_WIDTH 16
8259 /* The mask used to set the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field value. */
8260 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_SET_MSK 0x0000ffff
8261 /* The mask used to clear the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field value. */
8262 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_CLR_MSK 0xffff0000
8263 /* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field. */
8264 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_RESET 0x0
8265 /* Extracts the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE field value from a register. */
8266 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
8267 /* Produces a ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field value suitable for setting the register. */
8268 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
8269 
8270 #ifndef __ASSEMBLY__
8271 /*
8272  * WARNING: The C register and register group struct declarations are provided for
8273  * convenience and illustrative purposes. They should, however, be used with
8274  * caution as the C language standard provides no guarantees about the alignment or
8275  * atomicity of device memory accesses. The recommended practice for writing
8276  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8277  * alt_write_word() functions.
8278  *
8279  * The struct declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR2.
8280  */
8281 struct ALT_NAND_STAT_ERR_BLOCK_ADDR2_s
8282 {
8283  const uint32_t value : 16; /* ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE */
8284  uint32_t : 16; /* *UNDEFINED* */
8285 };
8286 
8287 /* The typedef declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR2. */
8288 typedef volatile struct ALT_NAND_STAT_ERR_BLOCK_ADDR2_s ALT_NAND_STAT_ERR_BLOCK_ADDR2_t;
8289 #endif /* __ASSEMBLY__ */
8290 
8291 /* The byte offset of the ALT_NAND_STAT_ERR_BLOCK_ADDR2 register from the beginning of the component. */
8292 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_OFST 0xf0
8293 
8294 /*
8295  * Register : intr_status3
8296  *
8297  * Interrupt status register for bank 3
8298  *
8299  * Register Layout
8300  *
8301  * Bits | Access | Reset | Description
8302  * :--------|:-------|:------|:----------------------------------------------
8303  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR
8304  * [1] | ??? | 0x0 | *UNDEFINED*
8305  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP
8306  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_TIME_OUT
8307  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL
8308  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL
8309  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_LD_COMP
8310  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP
8311  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_ERASE_COMP
8312  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP
8313  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK
8314  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD
8315  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_INT_ACT
8316  * [13] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_RST_COMP
8317  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR
8318  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC
8319  * [31:16] | ??? | 0x0 | *UNDEFINED*
8320  *
8321  */
8322 /*
8323  * Field : ecc_uncor_err
8324  *
8325  * Ecc logic detected uncorrectable error while reading data from flash device.
8326  *
8327  * Field Access Macros:
8328  *
8329  */
8330 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field. */
8331 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_LSB 0
8332 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field. */
8333 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_MSB 0
8334 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field. */
8335 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_WIDTH 1
8336 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field value. */
8337 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_SET_MSK 0x00000001
8338 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field value. */
8339 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
8340 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field. */
8341 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_RESET 0x0
8342 /* Extracts the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR field value from a register. */
8343 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
8344 /* Produces a ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field value suitable for setting the register. */
8345 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
8346 
8347 /*
8348  * Field : dma_cmd_comp
8349  *
8350  * Not implemented.
8351  *
8352  * Field Access Macros:
8353  *
8354  */
8355 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field. */
8356 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_LSB 2
8357 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field. */
8358 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_MSB 2
8359 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field. */
8360 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_WIDTH 1
8361 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field value. */
8362 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_SET_MSK 0x00000004
8363 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field value. */
8364 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_CLR_MSK 0xfffffffb
8365 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field. */
8366 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_RESET 0x0
8367 /* Extracts the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP field value from a register. */
8368 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
8369 /* Produces a ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field value suitable for setting the register. */
8370 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
8371 
8372 /*
8373  * Field : time_out
8374  *
8375  * Watchdog timer has triggered in the controller due to one of the reasons like
8376  * device not responding or controller state machine did not get back to idle
8377  *
8378  * Field Access Macros:
8379  *
8380  */
8381 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field. */
8382 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_LSB 3
8383 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field. */
8384 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_MSB 3
8385 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field. */
8386 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_WIDTH 1
8387 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field value. */
8388 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_SET_MSK 0x00000008
8389 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field value. */
8390 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_CLR_MSK 0xfffffff7
8391 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field. */
8392 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_RESET 0x0
8393 /* Extracts the ALT_NAND_STAT_INTR_STAT3_TIME_OUT field value from a register. */
8394 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
8395 /* Produces a ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field value suitable for setting the register. */
8396 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
8397 
8398 /*
8399  * Field : program_fail
8400  *
8401  * Program failure occurred in the device on issuance of a program command.
8402  * err_block_addr and err_page_addr contain the block address and page address that
8403  * failed program operation.
8404  *
8405  * Field Access Macros:
8406  *
8407  */
8408 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field. */
8409 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_LSB 4
8410 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field. */
8411 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_MSB 4
8412 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field. */
8413 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_WIDTH 1
8414 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field value. */
8415 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_SET_MSK 0x00000010
8416 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field value. */
8417 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_CLR_MSK 0xffffffef
8418 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field. */
8419 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_RESET 0x0
8420 /* Extracts the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL field value from a register. */
8421 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
8422 /* Produces a ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field value suitable for setting the register. */
8423 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
8424 
8425 /*
8426  * Field : erase_fail
8427  *
8428  * Erase failure occurred in the device on issuance of a erase command.
8429  * err_block_addr and err_page_addr contain the block address and page address that
8430  * failed erase operation.
8431  *
8432  * Field Access Macros:
8433  *
8434  */
8435 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field. */
8436 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_LSB 5
8437 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field. */
8438 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_MSB 5
8439 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field. */
8440 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_WIDTH 1
8441 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field value. */
8442 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_SET_MSK 0x00000020
8443 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field value. */
8444 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_CLR_MSK 0xffffffdf
8445 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field. */
8446 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_RESET 0x0
8447 /* Extracts the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL field value from a register. */
8448 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
8449 /* Produces a ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field value suitable for setting the register. */
8450 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
8451 
8452 /*
8453  * Field : load_comp
8454  *
8455  * Device finished the last issued load command.
8456  *
8457  * Field Access Macros:
8458  *
8459  */
8460 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field. */
8461 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_LSB 6
8462 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field. */
8463 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_MSB 6
8464 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field. */
8465 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_WIDTH 1
8466 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field value. */
8467 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_SET_MSK 0x00000040
8468 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field value. */
8469 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_CLR_MSK 0xffffffbf
8470 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field. */
8471 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_RESET 0x0
8472 /* Extracts the ALT_NAND_STAT_INTR_STAT3_LD_COMP field value from a register. */
8473 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
8474 /* Produces a ALT_NAND_STAT_INTR_STAT3_LD_COMP register field value suitable for setting the register. */
8475 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
8476 
8477 /*
8478  * Field : program_comp
8479  *
8480  * Device finished the last issued program command.
8481  *
8482  * Field Access Macros:
8483  *
8484  */
8485 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field. */
8486 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_LSB 7
8487 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field. */
8488 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_MSB 7
8489 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field. */
8490 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_WIDTH 1
8491 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field value. */
8492 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_SET_MSK 0x00000080
8493 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field value. */
8494 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_CLR_MSK 0xffffff7f
8495 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field. */
8496 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_RESET 0x0
8497 /* Extracts the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP field value from a register. */
8498 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
8499 /* Produces a ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field value suitable for setting the register. */
8500 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
8501 
8502 /*
8503  * Field : erase_comp
8504  *
8505  * Device erase operation complete
8506  *
8507  * Field Access Macros:
8508  *
8509  */
8510 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field. */
8511 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_LSB 8
8512 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field. */
8513 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_MSB 8
8514 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field. */
8515 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_WIDTH 1
8516 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field value. */
8517 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_SET_MSK 0x00000100
8518 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field value. */
8519 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_CLR_MSK 0xfffffeff
8520 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field. */
8521 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_RESET 0x0
8522 /* Extracts the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP field value from a register. */
8523 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
8524 /* Produces a ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field value suitable for setting the register. */
8525 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
8526 
8527 /*
8528  * Field : pipe_cpybck_cmd_comp
8529  *
8530  * A pipeline command or a copyback bank command has completed on this particular
8531  * bank
8532  *
8533  * Field Access Macros:
8534  *
8535  */
8536 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field. */
8537 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_LSB 9
8538 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field. */
8539 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_MSB 9
8540 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field. */
8541 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_WIDTH 1
8542 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field value. */
8543 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
8544 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field value. */
8545 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
8546 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field. */
8547 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_RESET 0x0
8548 /* Extracts the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP field value from a register. */
8549 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
8550 /* Produces a ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
8551 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
8552 
8553 /*
8554  * Field : locked_blk
8555  *
8556  * The address to program or erase operation is to a locked block and the operation
8557  * failed due to this reason
8558  *
8559  * Field Access Macros:
8560  *
8561  */
8562 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field. */
8563 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_LSB 10
8564 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field. */
8565 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_MSB 10
8566 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field. */
8567 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_WIDTH 1
8568 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field value. */
8569 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_SET_MSK 0x00000400
8570 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field value. */
8571 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_CLR_MSK 0xfffffbff
8572 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field. */
8573 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_RESET 0x0
8574 /* Extracts the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK field value from a register. */
8575 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
8576 /* Produces a ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field value suitable for setting the register. */
8577 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
8578 
8579 /*
8580  * Field : unsup_cmd
8581  *
8582  * An unsupported command was received. This interrupt is set when an invalid
8583  * command is received, or when a command sequence is broken.
8584  *
8585  * Field Access Macros:
8586  *
8587  */
8588 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field. */
8589 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_LSB 11
8590 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field. */
8591 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_MSB 11
8592 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field. */
8593 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_WIDTH 1
8594 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field value. */
8595 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_SET_MSK 0x00000800
8596 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field value. */
8597 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_CLR_MSK 0xfffff7ff
8598 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field. */
8599 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_RESET 0x0
8600 /* Extracts the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD field value from a register. */
8601 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
8602 /* Produces a ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field value suitable for setting the register. */
8603 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
8604 
8605 /*
8606  * Field : INT_act
8607  *
8608  * R/B pin of device transitioned from low to high
8609  *
8610  * Field Access Macros:
8611  *
8612  */
8613 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field. */
8614 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_LSB 12
8615 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field. */
8616 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_MSB 12
8617 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field. */
8618 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_WIDTH 1
8619 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field value. */
8620 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_SET_MSK 0x00001000
8621 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field value. */
8622 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_CLR_MSK 0xffffefff
8623 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field. */
8624 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_RESET 0x0
8625 /* Extracts the ALT_NAND_STAT_INTR_STAT3_INT_ACT field value from a register. */
8626 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
8627 /* Produces a ALT_NAND_STAT_INTR_STAT3_INT_ACT register field value suitable for setting the register. */
8628 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
8629 
8630 /*
8631  * Field : rst_comp
8632  *
8633  * The NAND Flash Memory Controller has completed its reset and initialization
8634  * process
8635  *
8636  * Field Access Macros:
8637  *
8638  */
8639 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field. */
8640 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_LSB 13
8641 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field. */
8642 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_MSB 13
8643 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field. */
8644 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_WIDTH 1
8645 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field value. */
8646 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_SET_MSK 0x00002000
8647 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field value. */
8648 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_CLR_MSK 0xffffdfff
8649 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field. */
8650 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_RESET 0x0
8651 /* Extracts the ALT_NAND_STAT_INTR_STAT3_RST_COMP field value from a register. */
8652 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
8653 /* Produces a ALT_NAND_STAT_INTR_STAT3_RST_COMP register field value suitable for setting the register. */
8654 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
8655 
8656 /*
8657  * Field : pipe_cmd_err
8658  *
8659  * A pipeline command sequence has been violated. This occurs when Map 01 page
8660  * read/write address does not match the corresponding expected address from the
8661  * pipeline commands issued earlier.
8662  *
8663  * Field Access Macros:
8664  *
8665  */
8666 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field. */
8667 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_LSB 14
8668 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field. */
8669 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_MSB 14
8670 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field. */
8671 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_WIDTH 1
8672 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field value. */
8673 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_SET_MSK 0x00004000
8674 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field value. */
8675 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
8676 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field. */
8677 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_RESET 0x0
8678 /* Extracts the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR field value from a register. */
8679 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
8680 /* Produces a ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field value suitable for setting the register. */
8681 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
8682 
8683 /*
8684  * Field : page_xfer_inc
8685  *
8686  * For every page of data transfer to or from the device, this bit will be set.
8687  *
8688  * Field Access Macros:
8689  *
8690  */
8691 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field. */
8692 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_LSB 15
8693 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field. */
8694 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_MSB 15
8695 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field. */
8696 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_WIDTH 1
8697 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field value. */
8698 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_SET_MSK 0x00008000
8699 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field value. */
8700 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_CLR_MSK 0xffff7fff
8701 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field. */
8702 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_RESET 0x0
8703 /* Extracts the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC field value from a register. */
8704 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
8705 /* Produces a ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field value suitable for setting the register. */
8706 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
8707 
8708 #ifndef __ASSEMBLY__
8709 /*
8710  * WARNING: The C register and register group struct declarations are provided for
8711  * convenience and illustrative purposes. They should, however, be used with
8712  * caution as the C language standard provides no guarantees about the alignment or
8713  * atomicity of device memory accesses. The recommended practice for writing
8714  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8715  * alt_write_word() functions.
8716  *
8717  * The struct declaration for register ALT_NAND_STAT_INTR_STAT3.
8718  */
8719 struct ALT_NAND_STAT_INTR_STAT3_s
8720 {
8721  uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR */
8722  uint32_t : 1; /* *UNDEFINED* */
8723  uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP */
8724  uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_STAT3_TIME_OUT */
8725  uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL */
8726  uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL */
8727  uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_STAT3_LD_COMP */
8728  uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP */
8729  uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_STAT3_ERASE_COMP */
8730  uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP */
8731  uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK */
8732  uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD */
8733  uint32_t INT_act : 1; /* ALT_NAND_STAT_INTR_STAT3_INT_ACT */
8734  uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_STAT3_RST_COMP */
8735  uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR */
8736  uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC */
8737  uint32_t : 16; /* *UNDEFINED* */
8738 };
8739 
8740 /* The typedef declaration for register ALT_NAND_STAT_INTR_STAT3. */
8741 typedef volatile struct ALT_NAND_STAT_INTR_STAT3_s ALT_NAND_STAT_INTR_STAT3_t;
8742 #endif /* __ASSEMBLY__ */
8743 
8744 /* The byte offset of the ALT_NAND_STAT_INTR_STAT3 register from the beginning of the component. */
8745 #define ALT_NAND_STAT_INTR_STAT3_OFST 0x100
8746 
8747 /*
8748  * Register : intr_en3
8749  *
8750  * Enables corresponding interrupt bit in interrupt register for bank 3
8751  *
8752  * Register Layout
8753  *
8754  * Bits | Access | Reset | Description
8755  * :--------|:-------|:------|:--------------------------------------------
8756  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR
8757  * [1] | ??? | 0x0 | *UNDEFINED*
8758  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP
8759  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_TIME_OUT
8760  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL
8761  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_ERASE_FAIL
8762  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_LD_COMP
8763  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP
8764  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_ERASE_COMP
8765  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP
8766  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_LOCKED_BLK
8767  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_UNSUP_CMD
8768  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_INT_ACT
8769  * [13] | RW | 0x1 | ALT_NAND_STAT_INTR_EN3_RST_COMP
8770  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR
8771  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC
8772  * [31:16] | ??? | 0x0 | *UNDEFINED*
8773  *
8774  */
8775 /*
8776  * Field : ecc_uncor_err
8777  *
8778  * If set, Controller will interrupt processor when Ecc logic detects uncorrectable
8779  * error.
8780  *
8781  * Field Access Macros:
8782  *
8783  */
8784 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field. */
8785 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_LSB 0
8786 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field. */
8787 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_MSB 0
8788 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field. */
8789 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_WIDTH 1
8790 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field value. */
8791 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_SET_MSK 0x00000001
8792 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field value. */
8793 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
8794 /* The reset value of the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field. */
8795 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_RESET 0x0
8796 /* Extracts the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR field value from a register. */
8797 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
8798 /* Produces a ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field value suitable for setting the register. */
8799 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
8800 
8801 /*
8802  * Field : dma_cmd_comp
8803  *
8804  * Not implemented.
8805  *
8806  * Field Access Macros:
8807  *
8808  */
8809 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field. */
8810 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_LSB 2
8811 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field. */
8812 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_MSB 2
8813 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field. */
8814 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_WIDTH 1
8815 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field value. */
8816 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_SET_MSK 0x00000004
8817 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field value. */
8818 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_CLR_MSK 0xfffffffb
8819 /* The reset value of the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field. */
8820 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_RESET 0x0
8821 /* Extracts the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP field value from a register. */
8822 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
8823 /* Produces a ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field value suitable for setting the register. */
8824 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
8825 
8826 /*
8827  * Field : time_out
8828  *
8829  * Watchdog timer has triggered in the controller due to one of the reasons like
8830  * device not responding or controller state machine did not get back to idle
8831  *
8832  * Field Access Macros:
8833  *
8834  */
8835 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field. */
8836 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_LSB 3
8837 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field. */
8838 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_MSB 3
8839 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field. */
8840 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_WIDTH 1
8841 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field value. */
8842 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_SET_MSK 0x00000008
8843 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field value. */
8844 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_CLR_MSK 0xfffffff7
8845 /* The reset value of the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field. */
8846 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_RESET 0x0
8847 /* Extracts the ALT_NAND_STAT_INTR_EN3_TIME_OUT field value from a register. */
8848 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
8849 /* Produces a ALT_NAND_STAT_INTR_EN3_TIME_OUT register field value suitable for setting the register. */
8850 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
8851 
8852 /*
8853  * Field : program_fail
8854  *
8855  * Program failure occurred in the device on issuance of a program command.
8856  * err_block_addr and err_page_addr contain the block address and page address that
8857  * failed program operation.
8858  *
8859  * Field Access Macros:
8860  *
8861  */
8862 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field. */
8863 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_LSB 4
8864 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field. */
8865 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_MSB 4
8866 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field. */
8867 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_WIDTH 1
8868 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field value. */
8869 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_SET_MSK 0x00000010
8870 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field value. */
8871 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_CLR_MSK 0xffffffef
8872 /* The reset value of the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field. */
8873 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_RESET 0x0
8874 /* Extracts the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL field value from a register. */
8875 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
8876 /* Produces a ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field value suitable for setting the register. */
8877 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
8878 
8879 /*
8880  * Field : erase_fail
8881  *
8882  * Erase failure occurred in the device on issuance of a erase command.
8883  * err_block_addr and err_page_addr contain the block address and page address that
8884  * failed erase operation.
8885  *
8886  * Field Access Macros:
8887  *
8888  */
8889 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field. */
8890 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_LSB 5
8891 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field. */
8892 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_MSB 5
8893 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field. */
8894 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_WIDTH 1
8895 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field value. */
8896 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_SET_MSK 0x00000020
8897 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field value. */
8898 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_CLR_MSK 0xffffffdf
8899 /* The reset value of the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field. */
8900 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_RESET 0x0
8901 /* Extracts the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL field value from a register. */
8902 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
8903 /* Produces a ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field value suitable for setting the register. */
8904 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
8905 
8906 /*
8907  * Field : load_comp
8908  *
8909  * Device finished the last issued load command.
8910  *
8911  * Field Access Macros:
8912  *
8913  */
8914 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_LD_COMP register field. */
8915 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_LSB 6
8916 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_LD_COMP register field. */
8917 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_MSB 6
8918 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_LD_COMP register field. */
8919 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_WIDTH 1
8920 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_LD_COMP register field value. */
8921 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_SET_MSK 0x00000040
8922 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_LD_COMP register field value. */
8923 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_CLR_MSK 0xffffffbf
8924 /* The reset value of the ALT_NAND_STAT_INTR_EN3_LD_COMP register field. */
8925 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_RESET 0x0
8926 /* Extracts the ALT_NAND_STAT_INTR_EN3_LD_COMP field value from a register. */
8927 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
8928 /* Produces a ALT_NAND_STAT_INTR_EN3_LD_COMP register field value suitable for setting the register. */
8929 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
8930 
8931 /*
8932  * Field : program_comp
8933  *
8934  * Device finished the last issued program command.
8935  *
8936  * Field Access Macros:
8937  *
8938  */
8939 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field. */
8940 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_LSB 7
8941 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field. */
8942 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_MSB 7
8943 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field. */
8944 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_WIDTH 1
8945 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field value. */
8946 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_SET_MSK 0x00000080
8947 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field value. */
8948 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_CLR_MSK 0xffffff7f
8949 /* The reset value of the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field. */
8950 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_RESET 0x0
8951 /* Extracts the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP field value from a register. */
8952 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
8953 /* Produces a ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field value suitable for setting the register. */
8954 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
8955 
8956 /*
8957  * Field : erase_comp
8958  *
8959  * Device erase operation complete
8960  *
8961  * Field Access Macros:
8962  *
8963  */
8964 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field. */
8965 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_LSB 8
8966 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field. */
8967 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_MSB 8
8968 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field. */
8969 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_WIDTH 1
8970 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field value. */
8971 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_SET_MSK 0x00000100
8972 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field value. */
8973 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_CLR_MSK 0xfffffeff
8974 /* The reset value of the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field. */
8975 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_RESET 0x0
8976 /* Extracts the ALT_NAND_STAT_INTR_EN3_ERASE_COMP field value from a register. */
8977 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
8978 /* Produces a ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field value suitable for setting the register. */
8979 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
8980 
8981 /*
8982  * Field : pipe_cpybck_cmd_comp
8983  *
8984  * A pipeline command or a copyback bank command has completed on this particular
8985  * bank
8986  *
8987  * Field Access Macros:
8988  *
8989  */
8990 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field. */
8991 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_LSB 9
8992 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field. */
8993 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_MSB 9
8994 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field. */
8995 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_WIDTH 1
8996 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field value. */
8997 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
8998 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field value. */
8999 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
9000 /* The reset value of the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field. */
9001 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_RESET 0x0
9002 /* Extracts the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP field value from a register. */
9003 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
9004 /* Produces a ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
9005 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
9006 
9007 /*
9008  * Field : locked_blk
9009  *
9010  * The address to program or erase operation is to a locked block and the operation
9011  * failed due to this reason
9012  *
9013  * Field Access Macros:
9014  *
9015  */
9016 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field. */
9017 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_LSB 10
9018 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field. */
9019 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_MSB 10
9020 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field. */
9021 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_WIDTH 1
9022 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field value. */
9023 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_SET_MSK 0x00000400
9024 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field value. */
9025 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_CLR_MSK 0xfffffbff
9026 /* The reset value of the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field. */
9027 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_RESET 0x0
9028 /* Extracts the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK field value from a register. */
9029 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
9030 /* Produces a ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field value suitable for setting the register. */
9031 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
9032 
9033 /*
9034  * Field : unsup_cmd
9035  *
9036  * An unsupported command was received. This interrupt is set when an invalid
9037  * command is received, or when a command sequence is broken.
9038  *
9039  * Field Access Macros:
9040  *
9041  */
9042 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field. */
9043 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_LSB 11
9044 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field. */
9045 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_MSB 11
9046 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field. */
9047 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_WIDTH 1
9048 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field value. */
9049 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_SET_MSK 0x00000800
9050 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field value. */
9051 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_CLR_MSK 0xfffff7ff
9052 /* The reset value of the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field. */
9053 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_RESET 0x0
9054 /* Extracts the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD field value from a register. */
9055 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
9056 /* Produces a ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field value suitable for setting the register. */
9057 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
9058 
9059 /*
9060  * Field : INT_act
9061  *
9062  * R/B pin of device transitioned from low to high
9063  *
9064  * Field Access Macros:
9065  *
9066  */
9067 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_INT_ACT register field. */
9068 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_LSB 12
9069 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_INT_ACT register field. */
9070 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_MSB 12
9071 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_INT_ACT register field. */
9072 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_WIDTH 1
9073 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_INT_ACT register field value. */
9074 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_SET_MSK 0x00001000
9075 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_INT_ACT register field value. */
9076 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_CLR_MSK 0xffffefff
9077 /* The reset value of the ALT_NAND_STAT_INTR_EN3_INT_ACT register field. */
9078 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_RESET 0x0
9079 /* Extracts the ALT_NAND_STAT_INTR_EN3_INT_ACT field value from a register. */
9080 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
9081 /* Produces a ALT_NAND_STAT_INTR_EN3_INT_ACT register field value suitable for setting the register. */
9082 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
9083 
9084 /*
9085  * Field : rst_comp
9086  *
9087  * A reset command has completed on this bank
9088  *
9089  * Field Access Macros:
9090  *
9091  */
9092 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_RST_COMP register field. */
9093 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_LSB 13
9094 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_RST_COMP register field. */
9095 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_MSB 13
9096 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_RST_COMP register field. */
9097 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_WIDTH 1
9098 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_RST_COMP register field value. */
9099 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_SET_MSK 0x00002000
9100 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_RST_COMP register field value. */
9101 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_CLR_MSK 0xffffdfff
9102 /* The reset value of the ALT_NAND_STAT_INTR_EN3_RST_COMP register field. */
9103 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_RESET 0x1
9104 /* Extracts the ALT_NAND_STAT_INTR_EN3_RST_COMP field value from a register. */
9105 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
9106 /* Produces a ALT_NAND_STAT_INTR_EN3_RST_COMP register field value suitable for setting the register. */
9107 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
9108 
9109 /*
9110  * Field : pipe_cmd_err
9111  *
9112  * A pipeline command sequence has been violated. This occurs when Map 01 page
9113  * read/write address does not match the corresponding expected address from the
9114  * pipeline commands issued earlier.
9115  *
9116  * Field Access Macros:
9117  *
9118  */
9119 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field. */
9120 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_LSB 14
9121 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field. */
9122 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_MSB 14
9123 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field. */
9124 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_WIDTH 1
9125 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field value. */
9126 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_SET_MSK 0x00004000
9127 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field value. */
9128 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
9129 /* The reset value of the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field. */
9130 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_RESET 0x0
9131 /* Extracts the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR field value from a register. */
9132 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
9133 /* Produces a ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field value suitable for setting the register. */
9134 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
9135 
9136 /*
9137  * Field : page_xfer_inc
9138  *
9139  * For every page of data transfer to or from the device, this bit will be set.
9140  *
9141  * Field Access Macros:
9142  *
9143  */
9144 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field. */
9145 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_LSB 15
9146 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field. */
9147 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_MSB 15
9148 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field. */
9149 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_WIDTH 1
9150 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field value. */
9151 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_SET_MSK 0x00008000
9152 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field value. */
9153 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_CLR_MSK 0xffff7fff
9154 /* The reset value of the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field. */
9155 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_RESET 0x0
9156 /* Extracts the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC field value from a register. */
9157 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
9158 /* Produces a ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field value suitable for setting the register. */
9159 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
9160 
9161 #ifndef __ASSEMBLY__
9162 /*
9163  * WARNING: The C register and register group struct declarations are provided for
9164  * convenience and illustrative purposes. They should, however, be used with
9165  * caution as the C language standard provides no guarantees about the alignment or
9166  * atomicity of device memory accesses. The recommended practice for writing
9167  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9168  * alt_write_word() functions.
9169  *
9170  * The struct declaration for register ALT_NAND_STAT_INTR_EN3.
9171  */
9172 struct ALT_NAND_STAT_INTR_EN3_s
9173 {
9174  uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR */
9175  uint32_t : 1; /* *UNDEFINED* */
9176  uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP */
9177  uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_EN3_TIME_OUT */
9178  uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL */
9179  uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_EN3_ERASE_FAIL */
9180  uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_EN3_LD_COMP */
9181  uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP */
9182  uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_EN3_ERASE_COMP */
9183  uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP */
9184  uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_EN3_LOCKED_BLK */
9185  uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_EN3_UNSUP_CMD */
9186  uint32_t INT_act : 1; /* ALT_NAND_STAT_INTR_EN3_INT_ACT */
9187  uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_EN3_RST_COMP */
9188  uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR */
9189  uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC */
9190  uint32_t : 16; /* *UNDEFINED* */
9191 };
9192 
9193 /* The typedef declaration for register ALT_NAND_STAT_INTR_EN3. */
9194 typedef volatile struct ALT_NAND_STAT_INTR_EN3_s ALT_NAND_STAT_INTR_EN3_t;
9195 #endif /* __ASSEMBLY__ */
9196 
9197 /* The byte offset of the ALT_NAND_STAT_INTR_EN3 register from the beginning of the component. */
9198 #define ALT_NAND_STAT_INTR_EN3_OFST 0x110
9199 
9200 /*
9201  * Register : page_cnt3
9202  *
9203  * Decrementing page count bank 3
9204  *
9205  * Register Layout
9206  *
9207  * Bits | Access | Reset | Description
9208  * :-------|:-------|:------|:------------------------------
9209  * [7:0] | R | 0x0 | ALT_NAND_STAT_PAGE_CNT3_VALUE
9210  * [31:8] | ??? | 0x0 | *UNDEFINED*
9211  *
9212  */
9213 /*
9214  * Field : value
9215  *
9216  * Maintains a decrementing count of the number of pages in the multi-page
9217  * (pipeline and copyback) command being executed.
9218  *
9219  * Field Access Macros:
9220  *
9221  */
9222 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_PAGE_CNT3_VALUE register field. */
9223 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_LSB 0
9224 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_PAGE_CNT3_VALUE register field. */
9225 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_MSB 7
9226 /* The width in bits of the ALT_NAND_STAT_PAGE_CNT3_VALUE register field. */
9227 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_WIDTH 8
9228 /* The mask used to set the ALT_NAND_STAT_PAGE_CNT3_VALUE register field value. */
9229 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_SET_MSK 0x000000ff
9230 /* The mask used to clear the ALT_NAND_STAT_PAGE_CNT3_VALUE register field value. */
9231 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_CLR_MSK 0xffffff00
9232 /* The reset value of the ALT_NAND_STAT_PAGE_CNT3_VALUE register field. */
9233 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_RESET 0x0
9234 /* Extracts the ALT_NAND_STAT_PAGE_CNT3_VALUE field value from a register. */
9235 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
9236 /* Produces a ALT_NAND_STAT_PAGE_CNT3_VALUE register field value suitable for setting the register. */
9237 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_SET(value) (((value) << 0) & 0x000000ff)
9238 
9239 #ifndef __ASSEMBLY__
9240 /*
9241  * WARNING: The C register and register group struct declarations are provided for
9242  * convenience and illustrative purposes. They should, however, be used with
9243  * caution as the C language standard provides no guarantees about the alignment or
9244  * atomicity of device memory accesses. The recommended practice for writing
9245  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9246  * alt_write_word() functions.
9247  *
9248  * The struct declaration for register ALT_NAND_STAT_PAGE_CNT3.
9249  */
9250 struct ALT_NAND_STAT_PAGE_CNT3_s
9251 {
9252  const uint32_t value : 8; /* ALT_NAND_STAT_PAGE_CNT3_VALUE */
9253  uint32_t : 24; /* *UNDEFINED* */
9254 };
9255 
9256 /* The typedef declaration for register ALT_NAND_STAT_PAGE_CNT3. */
9257 typedef volatile struct ALT_NAND_STAT_PAGE_CNT3_s ALT_NAND_STAT_PAGE_CNT3_t;
9258 #endif /* __ASSEMBLY__ */
9259 
9260 /* The byte offset of the ALT_NAND_STAT_PAGE_CNT3 register from the beginning of the component. */
9261 #define ALT_NAND_STAT_PAGE_CNT3_OFST 0x120
9262 
9263 /*
9264  * Register : err_page_addr3
9265  *
9266  * Erred page address bank 3
9267  *
9268  * Register Layout
9269  *
9270  * Bits | Access | Reset | Description
9271  * :--------|:-------|:------|:-----------------------------------
9272  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE
9273  * [31:16] | ??? | 0x0 | *UNDEFINED*
9274  *
9275  */
9276 /*
9277  * Field : value
9278  *
9279  * Holds the page address that resulted in a failure on program or erase operation.
9280  *
9281  * Field Access Macros:
9282  *
9283  */
9284 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field. */
9285 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_LSB 0
9286 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field. */
9287 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_MSB 15
9288 /* The width in bits of the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field. */
9289 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_WIDTH 16
9290 /* The mask used to set the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field value. */
9291 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_SET_MSK 0x0000ffff
9292 /* The mask used to clear the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field value. */
9293 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_CLR_MSK 0xffff0000
9294 /* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field. */
9295 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_RESET 0x0
9296 /* Extracts the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE field value from a register. */
9297 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
9298 /* Produces a ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field value suitable for setting the register. */
9299 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
9300 
9301 #ifndef __ASSEMBLY__
9302 /*
9303  * WARNING: The C register and register group struct declarations are provided for
9304  * convenience and illustrative purposes. They should, however, be used with
9305  * caution as the C language standard provides no guarantees about the alignment or
9306  * atomicity of device memory accesses. The recommended practice for writing
9307  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9308  * alt_write_word() functions.
9309  *
9310  * The struct declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR3.
9311  */
9312 struct ALT_NAND_STAT_ERR_PAGE_ADDR3_s
9313 {
9314  const uint32_t value : 16; /* ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE */
9315  uint32_t : 16; /* *UNDEFINED* */
9316 };
9317 
9318 /* The typedef declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR3. */
9319 typedef volatile struct ALT_NAND_STAT_ERR_PAGE_ADDR3_s ALT_NAND_STAT_ERR_PAGE_ADDR3_t;
9320 #endif /* __ASSEMBLY__ */
9321 
9322 /* The byte offset of the ALT_NAND_STAT_ERR_PAGE_ADDR3 register from the beginning of the component. */
9323 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_OFST 0x130
9324 
9325 /*
9326  * Register : err_block_addr3
9327  *
9328  * Erred block address bank 3
9329  *
9330  * Register Layout
9331  *
9332  * Bits | Access | Reset | Description
9333  * :--------|:-------|:------|:------------------------------------
9334  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE
9335  * [31:16] | ??? | 0x0 | *UNDEFINED*
9336  *
9337  */
9338 /*
9339  * Field : value
9340  *
9341  * Holds the block address that resulted in a failure on program or erase
9342  * operation.
9343  *
9344  * Field Access Macros:
9345  *
9346  */
9347 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field. */
9348 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_LSB 0
9349 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field. */
9350 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_MSB 15
9351 /* The width in bits of the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field. */
9352 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_WIDTH 16
9353 /* The mask used to set the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field value. */
9354 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_SET_MSK 0x0000ffff
9355 /* The mask used to clear the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field value. */
9356 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_CLR_MSK 0xffff0000
9357 /* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field. */
9358 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_RESET 0x0
9359 /* Extracts the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE field value from a register. */
9360 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
9361 /* Produces a ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field value suitable for setting the register. */
9362 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
9363 
9364 #ifndef __ASSEMBLY__
9365 /*
9366  * WARNING: The C register and register group struct declarations are provided for
9367  * convenience and illustrative purposes. They should, however, be used with
9368  * caution as the C language standard provides no guarantees about the alignment or
9369  * atomicity of device memory accesses. The recommended practice for writing
9370  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9371  * alt_write_word() functions.
9372  *
9373  * The struct declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR3.
9374  */
9375 struct ALT_NAND_STAT_ERR_BLOCK_ADDR3_s
9376 {
9377  const uint32_t value : 16; /* ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE */
9378  uint32_t : 16; /* *UNDEFINED* */
9379 };
9380 
9381 /* The typedef declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR3. */
9382 typedef volatile struct ALT_NAND_STAT_ERR_BLOCK_ADDR3_s ALT_NAND_STAT_ERR_BLOCK_ADDR3_t;
9383 #endif /* __ASSEMBLY__ */
9384 
9385 /* The byte offset of the ALT_NAND_STAT_ERR_BLOCK_ADDR3 register from the beginning of the component. */
9386 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_OFST 0x140
9387 
9388 #ifndef __ASSEMBLY__
9389 /*
9390  * WARNING: The C register and register group struct declarations are provided for
9391  * convenience and illustrative purposes. They should, however, be used with
9392  * caution as the C language standard provides no guarantees about the alignment or
9393  * atomicity of device memory accesses. The recommended practice for writing
9394  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9395  * alt_write_word() functions.
9396  *
9397  * The struct declaration for register group ALT_NAND_STAT.
9398  */
9399 struct ALT_NAND_STAT_s
9400 {
9401  ALT_NAND_STAT_TFR_MOD_t transfer_mode; /* ALT_NAND_STAT_TFR_MOD */
9402  volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
9403  ALT_NAND_STAT_INTR_STAT0_t intr_status0; /* ALT_NAND_STAT_INTR_STAT0 */
9404  volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
9405  ALT_NAND_STAT_INTR_EN0_t intr_en0; /* ALT_NAND_STAT_INTR_EN0 */
9406  volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
9407  ALT_NAND_STAT_PAGE_CNT0_t page_cnt0; /* ALT_NAND_STAT_PAGE_CNT0 */
9408  volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
9409  ALT_NAND_STAT_ERR_PAGE_ADDR0_t err_page_addr0; /* ALT_NAND_STAT_ERR_PAGE_ADDR0 */
9410  volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
9411  ALT_NAND_STAT_ERR_BLOCK_ADDR0_t err_block_addr0; /* ALT_NAND_STAT_ERR_BLOCK_ADDR0 */
9412  volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
9413  ALT_NAND_STAT_INTR_STAT1_t intr_status1; /* ALT_NAND_STAT_INTR_STAT1 */
9414  volatile uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */
9415  ALT_NAND_STAT_INTR_EN1_t intr_en1; /* ALT_NAND_STAT_INTR_EN1 */
9416  volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
9417  ALT_NAND_STAT_PAGE_CNT1_t page_cnt1; /* ALT_NAND_STAT_PAGE_CNT1 */
9418  volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
9419  ALT_NAND_STAT_ERR_PAGE_ADDR1_t err_page_addr1; /* ALT_NAND_STAT_ERR_PAGE_ADDR1 */
9420  volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
9421  ALT_NAND_STAT_ERR_BLOCK_ADDR1_t err_block_addr1; /* ALT_NAND_STAT_ERR_BLOCK_ADDR1 */
9422  volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
9423  ALT_NAND_STAT_INTR_STAT2_t intr_status2; /* ALT_NAND_STAT_INTR_STAT2 */
9424  volatile uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */
9425  ALT_NAND_STAT_INTR_EN2_t intr_en2; /* ALT_NAND_STAT_INTR_EN2 */
9426  volatile uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */
9427  ALT_NAND_STAT_PAGE_CNT2_t page_cnt2; /* ALT_NAND_STAT_PAGE_CNT2 */
9428  volatile uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */
9429  ALT_NAND_STAT_ERR_PAGE_ADDR2_t err_page_addr2; /* ALT_NAND_STAT_ERR_PAGE_ADDR2 */
9430  volatile uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */
9431  ALT_NAND_STAT_ERR_BLOCK_ADDR2_t err_block_addr2; /* ALT_NAND_STAT_ERR_BLOCK_ADDR2 */
9432  volatile uint32_t _pad_0xf4_0xff[3]; /* *UNDEFINED* */
9433  ALT_NAND_STAT_INTR_STAT3_t intr_status3; /* ALT_NAND_STAT_INTR_STAT3 */
9434  volatile uint32_t _pad_0x104_0x10f[3]; /* *UNDEFINED* */
9435  ALT_NAND_STAT_INTR_EN3_t intr_en3; /* ALT_NAND_STAT_INTR_EN3 */
9436  volatile uint32_t _pad_0x114_0x11f[3]; /* *UNDEFINED* */
9437  ALT_NAND_STAT_PAGE_CNT3_t page_cnt3; /* ALT_NAND_STAT_PAGE_CNT3 */
9438  volatile uint32_t _pad_0x124_0x12f[3]; /* *UNDEFINED* */
9439  ALT_NAND_STAT_ERR_PAGE_ADDR3_t err_page_addr3; /* ALT_NAND_STAT_ERR_PAGE_ADDR3 */
9440  volatile uint32_t _pad_0x134_0x13f[3]; /* *UNDEFINED* */
9441  ALT_NAND_STAT_ERR_BLOCK_ADDR3_t err_block_addr3; /* ALT_NAND_STAT_ERR_BLOCK_ADDR3 */
9442 };
9443 
9444 /* The typedef declaration for register group ALT_NAND_STAT. */
9445 typedef volatile struct ALT_NAND_STAT_s ALT_NAND_STAT_t;
9446 /* The struct declaration for the raw register contents of register group ALT_NAND_STAT. */
9447 struct ALT_NAND_STAT_raw_s
9448 {
9449  volatile uint32_t transfer_mode; /* ALT_NAND_STAT_TFR_MOD */
9450  uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
9451  volatile uint32_t intr_status0; /* ALT_NAND_STAT_INTR_STAT0 */
9452  uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
9453  volatile uint32_t intr_en0; /* ALT_NAND_STAT_INTR_EN0 */
9454  uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
9455  volatile uint32_t page_cnt0; /* ALT_NAND_STAT_PAGE_CNT0 */
9456  uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
9457  volatile uint32_t err_page_addr0; /* ALT_NAND_STAT_ERR_PAGE_ADDR0 */
9458  uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
9459  volatile uint32_t err_block_addr0; /* ALT_NAND_STAT_ERR_BLOCK_ADDR0 */
9460  uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
9461  volatile uint32_t intr_status1; /* ALT_NAND_STAT_INTR_STAT1 */
9462  uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */
9463  volatile uint32_t intr_en1; /* ALT_NAND_STAT_INTR_EN1 */
9464  uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
9465  volatile uint32_t page_cnt1; /* ALT_NAND_STAT_PAGE_CNT1 */
9466  uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
9467  volatile uint32_t err_page_addr1; /* ALT_NAND_STAT_ERR_PAGE_ADDR1 */
9468  uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
9469  volatile uint32_t err_block_addr1; /* ALT_NAND_STAT_ERR_BLOCK_ADDR1 */
9470  uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
9471  volatile uint32_t intr_status2; /* ALT_NAND_STAT_INTR_STAT2 */
9472  uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */
9473  volatile uint32_t intr_en2; /* ALT_NAND_STAT_INTR_EN2 */
9474  uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */
9475  volatile uint32_t page_cnt2; /* ALT_NAND_STAT_PAGE_CNT2 */
9476  uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */
9477  volatile uint32_t err_page_addr2; /* ALT_NAND_STAT_ERR_PAGE_ADDR2 */
9478  uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */
9479  volatile uint32_t err_block_addr2; /* ALT_NAND_STAT_ERR_BLOCK_ADDR2 */
9480  uint32_t _pad_0xf4_0xff[3]; /* *UNDEFINED* */
9481  volatile uint32_t intr_status3; /* ALT_NAND_STAT_INTR_STAT3 */
9482  uint32_t _pad_0x104_0x10f[3]; /* *UNDEFINED* */
9483  volatile uint32_t intr_en3; /* ALT_NAND_STAT_INTR_EN3 */
9484  uint32_t _pad_0x114_0x11f[3]; /* *UNDEFINED* */
9485  volatile uint32_t page_cnt3; /* ALT_NAND_STAT_PAGE_CNT3 */
9486  uint32_t _pad_0x124_0x12f[3]; /* *UNDEFINED* */
9487  volatile uint32_t err_page_addr3; /* ALT_NAND_STAT_ERR_PAGE_ADDR3 */
9488  uint32_t _pad_0x134_0x13f[3]; /* *UNDEFINED* */
9489  volatile uint32_t err_block_addr3; /* ALT_NAND_STAT_ERR_BLOCK_ADDR3 */
9490 };
9491 
9492 /* The typedef declaration for the raw register contents of register group ALT_NAND_STAT. */
9493 typedef volatile struct ALT_NAND_STAT_raw_s ALT_NAND_STAT_raw_t;
9494 #endif /* __ASSEMBLY__ */
9495 
9496 
9497 /*
9498  * Register Group : ECC registers - ALT_NAND_ECC
9499  * ECC registers
9500  *
9501  *
9502  */
9503 /*
9504  * Register : ECCCorInfo_b01
9505  *
9506  * ECC Error correction Information register. Controller updates this register when
9507  * it completes a transaction. The values are held in this register till a new
9508  * transaction completes.
9509  *
9510  * Register Layout
9511  *
9512  * Bits | Access | Reset | Description
9513  * :--------|:-------|:------|:------------------------------------------
9514  * [6:0] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0
9515  * [7] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0
9516  * [14:8] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1
9517  * [15] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1
9518  * [31:16] | ??? | 0x0 | *UNDEFINED*
9519  *
9520  */
9521 /*
9522  * Field : max_errors_b0
9523  *
9524  * Maximum of number of errors corrected per sector in Bank0. This field is not
9525  * valid for uncorrectable errors. A value of zero indicates that no ECC error
9526  * occurred in last completed transaction.
9527  *
9528  * Field Access Macros:
9529  *
9530  */
9531 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field. */
9532 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_LSB 0
9533 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field. */
9534 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_MSB 6
9535 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field. */
9536 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_WIDTH 7
9537 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field value. */
9538 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_SET_MSK 0x0000007f
9539 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field value. */
9540 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_CLR_MSK 0xffffff80
9541 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field. */
9542 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_RESET 0x0
9543 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 field value from a register. */
9544 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_GET(value) (((value) & 0x0000007f) >> 0)
9545 /* Produces a ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field value suitable for setting the register. */
9546 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_SET(value) (((value) << 0) & 0x0000007f)
9547 
9548 /*
9549  * Field : uncor_err_b0
9550  *
9551  * Uncorrectable error occurred while reading pages for last transaction in Bank0.
9552  * Uncorrectable errors also generate interrupts in intr_statusx register.
9553  *
9554  * Field Access Macros:
9555  *
9556  */
9557 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field. */
9558 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_LSB 7
9559 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field. */
9560 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_MSB 7
9561 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field. */
9562 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_WIDTH 1
9563 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field value. */
9564 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_SET_MSK 0x00000080
9565 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field value. */
9566 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_CLR_MSK 0xffffff7f
9567 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field. */
9568 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_RESET 0x0
9569 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 field value from a register. */
9570 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_GET(value) (((value) & 0x00000080) >> 7)
9571 /* Produces a ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field value suitable for setting the register. */
9572 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_SET(value) (((value) << 7) & 0x00000080)
9573 
9574 /*
9575  * Field : max_errors_b1
9576  *
9577  * Maximum of number of errors corrected per sector in Bank1. This field is not
9578  * valid for uncorrectable errors. A value of zero indicates that no ECC error
9579  * occurred in last completed transaction.
9580  *
9581  * Field Access Macros:
9582  *
9583  */
9584 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field. */
9585 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_LSB 8
9586 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field. */
9587 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_MSB 14
9588 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field. */
9589 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_WIDTH 7
9590 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field value. */
9591 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_SET_MSK 0x00007f00
9592 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field value. */
9593 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_CLR_MSK 0xffff80ff
9594 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field. */
9595 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_RESET 0x0
9596 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 field value from a register. */
9597 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_GET(value) (((value) & 0x00007f00) >> 8)
9598 /* Produces a ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field value suitable for setting the register. */
9599 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_SET(value) (((value) << 8) & 0x00007f00)
9600 
9601 /*
9602  * Field : uncor_err_b1
9603  *
9604  * Uncorrectable error occurred while reading pages for last transaction in Bank1.
9605  * Uncorrectable errors also generate interrupts in intr_statusx register.
9606  *
9607  * Field Access Macros:
9608  *
9609  */
9610 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field. */
9611 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_LSB 15
9612 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field. */
9613 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_MSB 15
9614 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field. */
9615 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_WIDTH 1
9616 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field value. */
9617 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_SET_MSK 0x00008000
9618 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field value. */
9619 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_CLR_MSK 0xffff7fff
9620 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field. */
9621 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_RESET 0x0
9622 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 field value from a register. */
9623 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_GET(value) (((value) & 0x00008000) >> 15)
9624 /* Produces a ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field value suitable for setting the register. */
9625 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_SET(value) (((value) << 15) & 0x00008000)
9626 
9627 #ifndef __ASSEMBLY__
9628 /*
9629  * WARNING: The C register and register group struct declarations are provided for
9630  * convenience and illustrative purposes. They should, however, be used with
9631  * caution as the C language standard provides no guarantees about the alignment or
9632  * atomicity of device memory accesses. The recommended practice for writing
9633  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9634  * alt_write_word() functions.
9635  *
9636  * The struct declaration for register ALT_NAND_ECC_ECCCORINFO_B01.
9637  */
9638 struct ALT_NAND_ECC_ECCCORINFO_B01_s
9639 {
9640  const uint32_t max_errors_b0 : 7; /* ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 */
9641  const uint32_t uncor_err_b0 : 1; /* ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 */
9642  const uint32_t max_errors_b1 : 7; /* ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 */
9643  const uint32_t uncor_err_b1 : 1; /* ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 */
9644  uint32_t : 16; /* *UNDEFINED* */
9645 };
9646 
9647 /* The typedef declaration for register ALT_NAND_ECC_ECCCORINFO_B01. */
9648 typedef volatile struct ALT_NAND_ECC_ECCCORINFO_B01_s ALT_NAND_ECC_ECCCORINFO_B01_t;
9649 #endif /* __ASSEMBLY__ */
9650 
9651 /* The byte offset of the ALT_NAND_ECC_ECCCORINFO_B01 register from the beginning of the component. */
9652 #define ALT_NAND_ECC_ECCCORINFO_B01_OFST 0x0
9653 
9654 /*
9655  * Register : ECCCorInfo_b23
9656  *
9657  * ECC Error correction Information register. Controller updates this register when
9658  * it completes a transaction. The values are held in this register till a new
9659  * transaction completes.
9660  *
9661  * Register Layout
9662  *
9663  * Bits | Access | Reset | Description
9664  * :--------|:-------|:------|:------------------------------------------
9665  * [6:0] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2
9666  * [7] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2
9667  * [14:8] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3
9668  * [15] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3
9669  * [31:16] | ??? | 0x0 | *UNDEFINED*
9670  *
9671  */
9672 /*
9673  * Field : max_errors_b2
9674  *
9675  * Maximum of number of errors corrected per sector in Bank2. This field is not
9676  * valid for uncorrectable errors. A value of zero indicates that no ECC error
9677  * occurred in last completed transaction.
9678  *
9679  * Field Access Macros:
9680  *
9681  */
9682 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field. */
9683 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_LSB 0
9684 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field. */
9685 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_MSB 6
9686 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field. */
9687 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_WIDTH 7
9688 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field value. */
9689 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_SET_MSK 0x0000007f
9690 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field value. */
9691 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_CLR_MSK 0xffffff80
9692 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field. */
9693 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_RESET 0x0
9694 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 field value from a register. */
9695 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_GET(value) (((value) & 0x0000007f) >> 0)
9696 /* Produces a ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field value suitable for setting the register. */
9697 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_SET(value) (((value) << 0) & 0x0000007f)
9698 
9699 /*
9700  * Field : uncor_err_b2
9701  *
9702  * Uncorrectable error occurred while reading pages for last transaction in Bank2.
9703  * Uncorrectable errors also generate interrupts in intr_statusx register.
9704  *
9705  * Field Access Macros:
9706  *
9707  */
9708 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field. */
9709 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_LSB 7
9710 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field. */
9711 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_MSB 7
9712 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field. */
9713 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_WIDTH 1
9714 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field value. */
9715 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_SET_MSK 0x00000080
9716 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field value. */
9717 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_CLR_MSK 0xffffff7f
9718 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field. */
9719 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_RESET 0x0
9720 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 field value from a register. */
9721 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_GET(value) (((value) & 0x00000080) >> 7)
9722 /* Produces a ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field value suitable for setting the register. */
9723 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_SET(value) (((value) << 7) & 0x00000080)
9724 
9725 /*
9726  * Field : max_errors_b3
9727  *
9728  * Maximum of number of errors corrected per sector in Bank3. This field is not
9729  * valid for uncorrectable errors. A value of zero indicates that no ECC error
9730  * occurred in last completed transaction.
9731  *
9732  * Field Access Macros:
9733  *
9734  */
9735 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field. */
9736 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_LSB 8
9737 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field. */
9738 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_MSB 14
9739 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field. */
9740 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_WIDTH 7
9741 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field value. */
9742 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_SET_MSK 0x00007f00
9743 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field value. */
9744 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_CLR_MSK 0xffff80ff
9745 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field. */
9746 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_RESET 0x0
9747 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 field value from a register. */
9748 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_GET(value) (((value) & 0x00007f00) >> 8)
9749 /* Produces a ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field value suitable for setting the register. */
9750 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_SET(value) (((value) << 8) & 0x00007f00)
9751 
9752 /*
9753  * Field : uncor_err_b3
9754  *
9755  * Uncorrectable error occurred while reading pages for last transaction in Bank3.
9756  * Uncorrectable errors also generate interrupts in intr_statusx register.
9757  *
9758  * Field Access Macros:
9759  *
9760  */
9761 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field. */
9762 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_LSB 15
9763 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field. */
9764 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_MSB 15
9765 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field. */
9766 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_WIDTH 1
9767 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field value. */
9768 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_SET_MSK 0x00008000
9769 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field value. */
9770 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_CLR_MSK 0xffff7fff
9771 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field. */
9772 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_RESET 0x0
9773 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 field value from a register. */
9774 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_GET(value) (((value) & 0x00008000) >> 15)
9775 /* Produces a ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field value suitable for setting the register. */
9776 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_SET(value) (((value) << 15) & 0x00008000)
9777 
9778 #ifndef __ASSEMBLY__
9779 /*
9780  * WARNING: The C register and register group struct declarations are provided for
9781  * convenience and illustrative purposes. They should, however, be used with
9782  * caution as the C language standard provides no guarantees about the alignment or
9783  * atomicity of device memory accesses. The recommended practice for writing
9784  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9785  * alt_write_word() functions.
9786  *
9787  * The struct declaration for register ALT_NAND_ECC_ECCCORINFO_B23.
9788  */
9789 struct ALT_NAND_ECC_ECCCORINFO_B23_s
9790 {
9791  const uint32_t max_errors_b2 : 7; /* ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 */
9792  const uint32_t uncor_err_b2 : 1; /* ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 */
9793  const uint32_t max_errors_b3 : 7; /* ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 */
9794  const uint32_t uncor_err_b3 : 1; /* ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 */
9795  uint32_t : 16; /* *UNDEFINED* */
9796 };
9797 
9798 /* The typedef declaration for register ALT_NAND_ECC_ECCCORINFO_B23. */
9799 typedef volatile struct ALT_NAND_ECC_ECCCORINFO_B23_s ALT_NAND_ECC_ECCCORINFO_B23_t;
9800 #endif /* __ASSEMBLY__ */
9801 
9802 /* The byte offset of the ALT_NAND_ECC_ECCCORINFO_B23 register from the beginning of the component. */
9803 #define ALT_NAND_ECC_ECCCORINFO_B23_OFST 0x10
9804 
9805 #ifndef __ASSEMBLY__
9806 /*
9807  * WARNING: The C register and register group struct declarations are provided for
9808  * convenience and illustrative purposes. They should, however, be used with
9809  * caution as the C language standard provides no guarantees about the alignment or
9810  * atomicity of device memory accesses. The recommended practice for writing
9811  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9812  * alt_write_word() functions.
9813  *
9814  * The struct declaration for register group ALT_NAND_ECC.
9815  */
9816 struct ALT_NAND_ECC_s
9817 {
9818  ALT_NAND_ECC_ECCCORINFO_B01_t ECCCorInfo_b01; /* ALT_NAND_ECC_ECCCORINFO_B01 */
9819  volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
9820  ALT_NAND_ECC_ECCCORINFO_B23_t ECCCorInfo_b23; /* ALT_NAND_ECC_ECCCORINFO_B23 */
9821 };
9822 
9823 /* The typedef declaration for register group ALT_NAND_ECC. */
9824 typedef volatile struct ALT_NAND_ECC_s ALT_NAND_ECC_t;
9825 /* The struct declaration for the raw register contents of register group ALT_NAND_ECC. */
9826 struct ALT_NAND_ECC_raw_s
9827 {
9828  volatile uint32_t ECCCorInfo_b01; /* ALT_NAND_ECC_ECCCORINFO_B01 */
9829  uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
9830  volatile uint32_t ECCCorInfo_b23; /* ALT_NAND_ECC_ECCCORINFO_B23 */
9831 };
9832 
9833 /* The typedef declaration for the raw register contents of register group ALT_NAND_ECC. */
9834 typedef volatile struct ALT_NAND_ECC_raw_s ALT_NAND_ECC_raw_t;
9835 #endif /* __ASSEMBLY__ */
9836 
9837 
9838 /*
9839  * Register Group : DMA registers - ALT_NAND_DMA
9840  * DMA registers
9841  *
9842  *
9843  */
9844 /*
9845  * Register : dma_enable
9846  *
9847  * Register Layout
9848  *
9849  * Bits | Access | Reset | Description
9850  * :-------|:-------|:------|:-------------------------
9851  * [0] | RW | 0x0 | ALT_NAND_DMA_DMA_EN_FLAG
9852  * [31:1] | ??? | 0x0 | *UNDEFINED*
9853  *
9854  */
9855 /*
9856  * Field : flag
9857  *
9858  * Enables data DMA operation in the controller 1 - Enable DMA 0 - Disable DMA
9859  *
9860  * Field Access Macros:
9861  *
9862  */
9863 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_EN_FLAG register field. */
9864 #define ALT_NAND_DMA_DMA_EN_FLAG_LSB 0
9865 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_EN_FLAG register field. */
9866 #define ALT_NAND_DMA_DMA_EN_FLAG_MSB 0
9867 /* The width in bits of the ALT_NAND_DMA_DMA_EN_FLAG register field. */
9868 #define ALT_NAND_DMA_DMA_EN_FLAG_WIDTH 1
9869 /* The mask used to set the ALT_NAND_DMA_DMA_EN_FLAG register field value. */
9870 #define ALT_NAND_DMA_DMA_EN_FLAG_SET_MSK 0x00000001
9871 /* The mask used to clear the ALT_NAND_DMA_DMA_EN_FLAG register field value. */
9872 #define ALT_NAND_DMA_DMA_EN_FLAG_CLR_MSK 0xfffffffe
9873 /* The reset value of the ALT_NAND_DMA_DMA_EN_FLAG register field. */
9874 #define ALT_NAND_DMA_DMA_EN_FLAG_RESET 0x0
9875 /* Extracts the ALT_NAND_DMA_DMA_EN_FLAG field value from a register. */
9876 #define ALT_NAND_DMA_DMA_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
9877 /* Produces a ALT_NAND_DMA_DMA_EN_FLAG register field value suitable for setting the register. */
9878 #define ALT_NAND_DMA_DMA_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
9879 
9880 #ifndef __ASSEMBLY__
9881 /*
9882  * WARNING: The C register and register group struct declarations are provided for
9883  * convenience and illustrative purposes. They should, however, be used with
9884  * caution as the C language standard provides no guarantees about the alignment or
9885  * atomicity of device memory accesses. The recommended practice for writing
9886  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9887  * alt_write_word() functions.
9888  *
9889  * The struct declaration for register ALT_NAND_DMA_DMA_EN.
9890  */
9891 struct ALT_NAND_DMA_DMA_EN_s
9892 {
9893  uint32_t flag : 1; /* ALT_NAND_DMA_DMA_EN_FLAG */
9894  uint32_t : 31; /* *UNDEFINED* */
9895 };
9896 
9897 /* The typedef declaration for register ALT_NAND_DMA_DMA_EN. */
9898 typedef volatile struct ALT_NAND_DMA_DMA_EN_s ALT_NAND_DMA_DMA_EN_t;
9899 #endif /* __ASSEMBLY__ */
9900 
9901 /* The byte offset of the ALT_NAND_DMA_DMA_EN register from the beginning of the component. */
9902 #define ALT_NAND_DMA_DMA_EN_OFST 0x0
9903 
9904 /*
9905  * Register : dma_intr
9906  *
9907  * DMA interrupt register
9908  *
9909  * Register Layout
9910  *
9911  * Bits | Access | Reset | Description
9912  * :-------|:-------|:------|:--------------------------------
9913  * [0] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_TGT_ERROR
9914  * [31:1] | ??? | 0x0 | *UNDEFINED*
9915  *
9916  */
9917 /*
9918  * Field : target_error
9919  *
9920  * Controller initiator interface received an ERROR target response for a
9921  * transaction.
9922  *
9923  * Field Access Macros:
9924  *
9925  */
9926 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_TGT_ERROR register field. */
9927 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_LSB 0
9928 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_TGT_ERROR register field. */
9929 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_MSB 0
9930 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_TGT_ERROR register field. */
9931 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_WIDTH 1
9932 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_TGT_ERROR register field value. */
9933 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_SET_MSK 0x00000001
9934 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_TGT_ERROR register field value. */
9935 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_CLR_MSK 0xfffffffe
9936 /* The reset value of the ALT_NAND_DMA_DMA_INTR_TGT_ERROR register field. */
9937 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_RESET 0x0
9938 /* Extracts the ALT_NAND_DMA_DMA_INTR_TGT_ERROR field value from a register. */
9939 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_GET(value) (((value) & 0x00000001) >> 0)
9940 /* Produces a ALT_NAND_DMA_DMA_INTR_TGT_ERROR register field value suitable for setting the register. */
9941 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_SET(value) (((value) << 0) & 0x00000001)
9942 
9943 #ifndef __ASSEMBLY__
9944 /*
9945  * WARNING: The C register and register group struct declarations are provided for
9946  * convenience and illustrative purposes. They should, however, be used with
9947  * caution as the C language standard provides no guarantees about the alignment or
9948  * atomicity of device memory accesses. The recommended practice for writing
9949  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9950  * alt_write_word() functions.
9951  *
9952  * The struct declaration for register ALT_NAND_DMA_DMA_INTR.
9953  */
9954 struct ALT_NAND_DMA_DMA_INTR_s
9955 {
9956  uint32_t target_error : 1; /* ALT_NAND_DMA_DMA_INTR_TGT_ERROR */
9957  uint32_t : 31; /* *UNDEFINED* */
9958 };
9959 
9960 /* The typedef declaration for register ALT_NAND_DMA_DMA_INTR. */
9961 typedef volatile struct ALT_NAND_DMA_DMA_INTR_s ALT_NAND_DMA_DMA_INTR_t;
9962 #endif /* __ASSEMBLY__ */
9963 
9964 /* The byte offset of the ALT_NAND_DMA_DMA_INTR register from the beginning of the component. */
9965 #define ALT_NAND_DMA_DMA_INTR_OFST 0x20
9966 
9967 /*
9968  * Register : dma_intr_en
9969  *
9970  * Enables corresponding interrupt bit in dma interrupt register
9971  *
9972  * Register Layout
9973  *
9974  * Bits | Access | Reset | Description
9975  * :-------|:-------|:------|:-----------------------------------
9976  * [0] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR
9977  * [31:1] | ??? | 0x0 | *UNDEFINED*
9978  *
9979  */
9980 /*
9981  * Field : target_error
9982  *
9983  * Controller initiator interface received an ERROR target response for a
9984  * transaction.
9985  *
9986  * Field Access Macros:
9987  *
9988  */
9989 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field. */
9990 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_LSB 0
9991 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field. */
9992 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_MSB 0
9993 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field. */
9994 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_WIDTH 1
9995 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field value. */
9996 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_SET_MSK 0x00000001
9997 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field value. */
9998 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_CLR_MSK 0xfffffffe
9999 /* The reset value of the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field. */
10000 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_RESET 0x0
10001 /* Extracts the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR field value from a register. */
10002 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_GET(value) (((value) & 0x00000001) >> 0)
10003 /* Produces a ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field value suitable for setting the register. */
10004 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_SET(value) (((value) << 0) & 0x00000001)
10005 
10006 #ifndef __ASSEMBLY__
10007 /*
10008  * WARNING: The C register and register group struct declarations are provided for
10009  * convenience and illustrative purposes. They should, however, be used with
10010  * caution as the C language standard provides no guarantees about the alignment or
10011  * atomicity of device memory accesses. The recommended practice for writing
10012  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10013  * alt_write_word() functions.
10014  *
10015  * The struct declaration for register ALT_NAND_DMA_DMA_INTR_EN.
10016  */
10017 struct ALT_NAND_DMA_DMA_INTR_EN_s
10018 {
10019  uint32_t target_error : 1; /* ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR */
10020  uint32_t : 31; /* *UNDEFINED* */
10021 };
10022 
10023 /* The typedef declaration for register ALT_NAND_DMA_DMA_INTR_EN. */
10024 typedef volatile struct ALT_NAND_DMA_DMA_INTR_EN_s ALT_NAND_DMA_DMA_INTR_EN_t;
10025 #endif /* __ASSEMBLY__ */
10026 
10027 /* The byte offset of the ALT_NAND_DMA_DMA_INTR_EN register from the beginning of the component. */
10028 #define ALT_NAND_DMA_DMA_INTR_EN_OFST 0x30
10029 
10030 /*
10031  * Register : target_err_addr_lo
10032  *
10033  * Transaction address for which controller initiator interface received an ERROR
10034  * target response.
10035  *
10036  * Register Layout
10037  *
10038  * Bits | Access | Reset | Description
10039  * :--------|:-------|:------|:-----------------------------------
10040  * [15:0] | R | 0x0 | ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE
10041  * [31:16] | ??? | 0x0 | *UNDEFINED*
10042  *
10043  */
10044 /*
10045  * Field : value
10046  *
10047  * Least significant 16 bits
10048  *
10049  * Field Access Macros:
10050  *
10051  */
10052 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE register field. */
10053 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_LSB 0
10054 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE register field. */
10055 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_MSB 15
10056 /* The width in bits of the ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE register field. */
10057 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_WIDTH 16
10058 /* The mask used to set the ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE register field value. */
10059 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_SET_MSK 0x0000ffff
10060 /* The mask used to clear the ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE register field value. */
10061 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_CLR_MSK 0xffff0000
10062 /* The reset value of the ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE register field. */
10063 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_RESET 0x0
10064 /* Extracts the ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE field value from a register. */
10065 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
10066 /* Produces a ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE register field value suitable for setting the register. */
10067 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
10068 
10069 #ifndef __ASSEMBLY__
10070 /*
10071  * WARNING: The C register and register group struct declarations are provided for
10072  * convenience and illustrative purposes. They should, however, be used with
10073  * caution as the C language standard provides no guarantees about the alignment or
10074  * atomicity of device memory accesses. The recommended practice for writing
10075  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10076  * alt_write_word() functions.
10077  *
10078  * The struct declaration for register ALT_NAND_DMA_TGT_ERR_ADDR_LO.
10079  */
10080 struct ALT_NAND_DMA_TGT_ERR_ADDR_LO_s
10081 {
10082  const uint32_t value : 16; /* ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE */
10083  uint32_t : 16; /* *UNDEFINED* */
10084 };
10085 
10086 /* The typedef declaration for register ALT_NAND_DMA_TGT_ERR_ADDR_LO. */
10087 typedef volatile struct ALT_NAND_DMA_TGT_ERR_ADDR_LO_s ALT_NAND_DMA_TGT_ERR_ADDR_LO_t;
10088 #endif /* __ASSEMBLY__ */
10089 
10090 /* The byte offset of the ALT_NAND_DMA_TGT_ERR_ADDR_LO register from the beginning of the component. */
10091 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_OFST 0x40
10092 
10093 /*
10094  * Register : target_err_addr_hi
10095  *
10096  * Transaction address for which controller initiator interface received an ERROR
10097  * target response.
10098  *
10099  * Register Layout
10100  *
10101  * Bits | Access | Reset | Description
10102  * :--------|:-------|:------|:-----------------------------------
10103  * [15:0] | R | 0x0 | ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE
10104  * [31:16] | ??? | 0x0 | *UNDEFINED*
10105  *
10106  */
10107 /*
10108  * Field : value
10109  *
10110  * Most significant 16 bits
10111  *
10112  * Field Access Macros:
10113  *
10114  */
10115 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE register field. */
10116 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_LSB 0
10117 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE register field. */
10118 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_MSB 15
10119 /* The width in bits of the ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE register field. */
10120 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_WIDTH 16
10121 /* The mask used to set the ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE register field value. */
10122 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_SET_MSK 0x0000ffff
10123 /* The mask used to clear the ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE register field value. */
10124 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_CLR_MSK 0xffff0000
10125 /* The reset value of the ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE register field. */
10126 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_RESET 0x0
10127 /* Extracts the ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE field value from a register. */
10128 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
10129 /* Produces a ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE register field value suitable for setting the register. */
10130 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
10131 
10132 #ifndef __ASSEMBLY__
10133 /*
10134  * WARNING: The C register and register group struct declarations are provided for
10135  * convenience and illustrative purposes. They should, however, be used with
10136  * caution as the C language standard provides no guarantees about the alignment or
10137  * atomicity of device memory accesses. The recommended practice for writing
10138  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10139  * alt_write_word() functions.
10140  *
10141  * The struct declaration for register ALT_NAND_DMA_TGT_ERR_ADDR_HI.
10142  */
10143 struct ALT_NAND_DMA_TGT_ERR_ADDR_HI_s
10144 {
10145  const uint32_t value : 16; /* ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE */
10146  uint32_t : 16; /* *UNDEFINED* */
10147 };
10148 
10149 /* The typedef declaration for register ALT_NAND_DMA_TGT_ERR_ADDR_HI. */
10150 typedef volatile struct ALT_NAND_DMA_TGT_ERR_ADDR_HI_s ALT_NAND_DMA_TGT_ERR_ADDR_HI_t;
10151 #endif /* __ASSEMBLY__ */
10152 
10153 /* The byte offset of the ALT_NAND_DMA_TGT_ERR_ADDR_HI register from the beginning of the component. */
10154 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_OFST 0x50
10155 
10156 /*
10157  * Register : flash_burst_length
10158  *
10159  * Register Layout
10160  *
10161  * Bits | Access | Reset | Description
10162  * :-------|:-------|:------|:--------------------------------------------
10163  * [1:0] | RW | 0x1 | ALT_NAND_DMA_FLSH_BURST_LEN_VALUE
10164  * [3:2] | ??? | 0x0 | *UNDEFINED*
10165  * [4] | RW | 0x0 | ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST
10166  * [7:5] | ??? | 0x0 | *UNDEFINED*
10167  * [31:8] | RW | 0x0 | ALT_NAND_DMA_FLSH_BURST_LEN_RSVD
10168  *
10169  */
10170 /*
10171  * Field : value
10172  *
10173  * Sets the burst used by data dma for transferring data to/from flash device. This
10174  * burst length is different and is larger than the burst length on the host bus so
10175  * that larger amount of data can be transferred to/from device, descreasing
10176  * controller data transfer overhead in the process. 00 - 64 bytes, 01 - 128 bytes,
10177  * 10 - 256 bytes, 11 - 512 bytes. The host burst size multiplied by the number of
10178  * outstanding requests on the host side should be greater than equal to this
10179  * value. If not, the device side burst length will be equal to host side burst
10180  * length.
10181  *
10182  * Field Access Macros:
10183  *
10184  */
10185 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field. */
10186 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_LSB 0
10187 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field. */
10188 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_MSB 1
10189 /* The width in bits of the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field. */
10190 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_WIDTH 2
10191 /* The mask used to set the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field value. */
10192 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_SET_MSK 0x00000003
10193 /* The mask used to clear the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field value. */
10194 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_CLR_MSK 0xfffffffc
10195 /* The reset value of the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field. */
10196 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_RESET 0x1
10197 /* Extracts the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE field value from a register. */
10198 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_GET(value) (((value) & 0x00000003) >> 0)
10199 /* Produces a ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field value suitable for setting the register. */
10200 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_SET(value) (((value) << 0) & 0x00000003)
10201 
10202 /*
10203  * Field : continous_burst
10204  *
10205  * When this bit is set, the Data DMA will burst the entire page from/to the flash
10206  * device. Please make sure that the host system can provide/sink data at a fast
10207  * pace to avoid unnecessary pausing of data on the device interface.
10208  *
10209  * Field Access Macros:
10210  *
10211  */
10212 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field. */
10213 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_LSB 4
10214 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field. */
10215 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_MSB 4
10216 /* The width in bits of the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field. */
10217 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_WIDTH 1
10218 /* The mask used to set the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field value. */
10219 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_SET_MSK 0x00000010
10220 /* The mask used to clear the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field value. */
10221 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_CLR_MSK 0xffffffef
10222 /* The reset value of the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field. */
10223 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_RESET 0x0
10224 /* Extracts the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST field value from a register. */
10225 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_GET(value) (((value) & 0x00000010) >> 4)
10226 /* Produces a ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field value suitable for setting the register. */
10227 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_SET(value) (((value) << 4) & 0x00000010)
10228 
10229 /*
10230  * Field : reserved
10231  *
10232  * Reserved
10233  *
10234  * Field Access Macros:
10235  *
10236  */
10237 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_RSVD register field. */
10238 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_LSB 8
10239 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_RSVD register field. */
10240 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_MSB 31
10241 /* The width in bits of the ALT_NAND_DMA_FLSH_BURST_LEN_RSVD register field. */
10242 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_WIDTH 24
10243 /* The mask used to set the ALT_NAND_DMA_FLSH_BURST_LEN_RSVD register field value. */
10244 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_SET_MSK 0xffffff00
10245 /* The mask used to clear the ALT_NAND_DMA_FLSH_BURST_LEN_RSVD register field value. */
10246 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_CLR_MSK 0x000000ff
10247 /* The reset value of the ALT_NAND_DMA_FLSH_BURST_LEN_RSVD register field. */
10248 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_RESET 0x0
10249 /* Extracts the ALT_NAND_DMA_FLSH_BURST_LEN_RSVD field value from a register. */
10250 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_GET(value) (((value) & 0xffffff00) >> 8)
10251 /* Produces a ALT_NAND_DMA_FLSH_BURST_LEN_RSVD register field value suitable for setting the register. */
10252 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_SET(value) (((value) << 8) & 0xffffff00)
10253 
10254 #ifndef __ASSEMBLY__
10255 /*
10256  * WARNING: The C register and register group struct declarations are provided for
10257  * convenience and illustrative purposes. They should, however, be used with
10258  * caution as the C language standard provides no guarantees about the alignment or
10259  * atomicity of device memory accesses. The recommended practice for writing
10260  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10261  * alt_write_word() functions.
10262  *
10263  * The struct declaration for register ALT_NAND_DMA_FLSH_BURST_LEN.
10264  */
10265 struct ALT_NAND_DMA_FLSH_BURST_LEN_s
10266 {
10267  uint32_t value : 2; /* ALT_NAND_DMA_FLSH_BURST_LEN_VALUE */
10268  uint32_t : 2; /* *UNDEFINED* */
10269  uint32_t continous_burst : 1; /* ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST */
10270  uint32_t : 3; /* *UNDEFINED* */
10271  uint32_t reserved : 24; /* ALT_NAND_DMA_FLSH_BURST_LEN_RSVD */
10272 };
10273 
10274 /* The typedef declaration for register ALT_NAND_DMA_FLSH_BURST_LEN. */
10275 typedef volatile struct ALT_NAND_DMA_FLSH_BURST_LEN_s ALT_NAND_DMA_FLSH_BURST_LEN_t;
10276 #endif /* __ASSEMBLY__ */
10277 
10278 /* The byte offset of the ALT_NAND_DMA_FLSH_BURST_LEN register from the beginning of the component. */
10279 #define ALT_NAND_DMA_FLSH_BURST_LEN_OFST 0x70
10280 
10281 /*
10282  * Register : chip_interleave_enable_and_allow_int_reads
10283  *
10284  * Register Layout
10285  *
10286  * Bits | Access | Reset | Description
10287  * :-------|:-------|:------|:----------------------------------------------
10288  * [0] | RW | 0x0 | ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN
10289  * [3:1] | ??? | 0x0 | *UNDEFINED*
10290  * [4] | RW | 0x1 | ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS
10291  * [31:5] | ??? | 0x0 | *UNDEFINED*
10292  *
10293  */
10294 /*
10295  * Field : chip_interleave_enable
10296  *
10297  * This bit informs the controller to enable or disable interleaving among
10298  * banks/LUNS to increase the net performance of the controller. [list][*]1 -
10299  * Enable interleaving [*]0 - Disable Interleaving[/list]
10300  *
10301  * Field Access Macros:
10302  *
10303  */
10304 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field. */
10305 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_LSB 0
10306 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field. */
10307 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_MSB 0
10308 /* The width in bits of the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field. */
10309 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_WIDTH 1
10310 /* The mask used to set the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field value. */
10311 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_SET_MSK 0x00000001
10312 /* The mask used to clear the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field value. */
10313 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_CLR_MSK 0xfffffffe
10314 /* The reset value of the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field. */
10315 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_RESET 0x0
10316 /* Extracts the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN field value from a register. */
10317 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_GET(value) (((value) & 0x00000001) >> 0)
10318 /* Produces a ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field value suitable for setting the register. */
10319 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_SET(value) (((value) << 0) & 0x00000001)
10320 
10321 /*
10322  * Field : allow_int_reads_within_luns
10323  *
10324  * This bit informs the controller to enable or disable simultaneous read accesses
10325  * to different LUNS in the same bank. This bit is of importance only if the
10326  * controller supports interleaved operations among LUNs and if the device has
10327  * multiple LUNS. If the bit is disabled, the controller will send read commands to
10328  * different LUNS of of the same bank only sequentially and if enabled, the
10329  * controller will issue simultaneous read accesses to LUNS of same bank if
10330  * required. [list][*]1 - Enable [*]0 - Disable[/list]
10331  *
10332  * Field Access Macros:
10333  *
10334  */
10335 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field. */
10336 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_LSB 4
10337 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field. */
10338 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_MSB 4
10339 /* The width in bits of the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field. */
10340 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_WIDTH 1
10341 /* The mask used to set the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field value. */
10342 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_SET_MSK 0x00000010
10343 /* The mask used to clear the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field value. */
10344 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_CLR_MSK 0xffffffef
10345 /* The reset value of the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field. */
10346 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_RESET 0x1
10347 /* Extracts the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS field value from a register. */
10348 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_GET(value) (((value) & 0x00000010) >> 4)
10349 /* Produces a ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field value suitable for setting the register. */
10350 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_SET(value) (((value) << 4) & 0x00000010)
10351 
10352 #ifndef __ASSEMBLY__
10353 /*
10354  * WARNING: The C register and register group struct declarations are provided for
10355  * convenience and illustrative purposes. They should, however, be used with
10356  * caution as the C language standard provides no guarantees about the alignment or
10357  * atomicity of device memory accesses. The recommended practice for writing
10358  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10359  * alt_write_word() functions.
10360  *
10361  * The struct declaration for register ALT_NAND_DMA_INTRLV.
10362  */
10363 struct ALT_NAND_DMA_INTRLV_s
10364 {
10365  uint32_t chip_interleave_enable : 1; /* ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN */
10366  uint32_t : 3; /* *UNDEFINED* */
10367  uint32_t allow_int_reads_within_luns : 1; /* ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS */
10368  uint32_t : 27; /* *UNDEFINED* */
10369 };
10370 
10371 /* The typedef declaration for register ALT_NAND_DMA_INTRLV. */
10372 typedef volatile struct ALT_NAND_DMA_INTRLV_s ALT_NAND_DMA_INTRLV_t;
10373 #endif /* __ASSEMBLY__ */
10374 
10375 /* The byte offset of the ALT_NAND_DMA_INTRLV register from the beginning of the component. */
10376 #define ALT_NAND_DMA_INTRLV_OFST 0x80
10377 
10378 /*
10379  * Register : no_of_blocks_per_lun
10380  *
10381  * Register Layout
10382  *
10383  * Bits | Access | Reset | Description
10384  * :-------|:-------|:------|:----------------------------------------
10385  * [3:0] | RW | 0xf | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE
10386  * [31:4] | ??? | 0x0 | *UNDEFINED*
10387  *
10388  */
10389 /*
10390  * Field : value
10391  *
10392  * Indicates the first block of next LUN. This information is used for extracting
10393  * the target LUN during LUN interleaving. After Initialization, if the controller
10394  * detects an ONFi device, this field is automatically updated by the controller.
10395  * For other devices, software will need to write to this register for proper
10396  * interleaving. The value in this register is interpreted as follows- [list][*]0 -
10397  * Next LUN starts from 1024. [*]1 - Next LUN starts from 2048. [*]2 - Next LUN
10398  * starts from 4096 and so on... [/list]
10399  *
10400  * Field Access Macros:
10401  *
10402  */
10403 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field. */
10404 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_LSB 0
10405 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field. */
10406 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_MSB 3
10407 /* The width in bits of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field. */
10408 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_WIDTH 4
10409 /* The mask used to set the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field value. */
10410 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_SET_MSK 0x0000000f
10411 /* The mask used to clear the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field value. */
10412 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_CLR_MSK 0xfffffff0
10413 /* The reset value of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field. */
10414 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_RESET 0xf
10415 /* Extracts the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE field value from a register. */
10416 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
10417 /* Produces a ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field value suitable for setting the register. */
10418 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_SET(value) (((value) << 0) & 0x0000000f)
10419 
10420 #ifndef __ASSEMBLY__
10421 /*
10422  * WARNING: The C register and register group struct declarations are provided for
10423  * convenience and illustrative purposes. They should, however, be used with
10424  * caution as the C language standard provides no guarantees about the alignment or
10425  * atomicity of device memory accesses. The recommended practice for writing
10426  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10427  * alt_write_word() functions.
10428  *
10429  * The struct declaration for register ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN.
10430  */
10431 struct ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_s
10432 {
10433  uint32_t value : 4; /* ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE */
10434  uint32_t : 28; /* *UNDEFINED* */
10435 };
10436 
10437 /* The typedef declaration for register ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN. */
10438 typedef volatile struct ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_s ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_t;
10439 #endif /* __ASSEMBLY__ */
10440 
10441 /* The byte offset of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN register from the beginning of the component. */
10442 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_OFST 0x90
10443 
10444 /*
10445  * Register : lun_status_cmd
10446  *
10447  * Indicates the command to be sent while checking status of the next LUN.
10448  *
10449  * Register Layout
10450  *
10451  * Bits | Access | Reset | Description
10452  * :--------|:-------|:-------|:--------------------------------
10453  * [15:0] | RW | 0x7878 | ALT_NAND_DMA_LUN_STAT_CMD_VALUE
10454  * [31:16] | ??? | 0x0 | *UNDEFINED*
10455  *
10456  */
10457 /*
10458  * Field : value
10459  *
10460  * [list][*]7:0 - Indicates the command to check the status of the first LUN/Die.
10461  * [*]15:8 - Indicates the command to check the status of the other LUN/Die.[/list]
10462  *
10463  * Field Access Macros:
10464  *
10465  */
10466 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_LUN_STAT_CMD_VALUE register field. */
10467 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_LSB 0
10468 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_LUN_STAT_CMD_VALUE register field. */
10469 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_MSB 15
10470 /* The width in bits of the ALT_NAND_DMA_LUN_STAT_CMD_VALUE register field. */
10471 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_WIDTH 16
10472 /* The mask used to set the ALT_NAND_DMA_LUN_STAT_CMD_VALUE register field value. */
10473 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_SET_MSK 0x0000ffff
10474 /* The mask used to clear the ALT_NAND_DMA_LUN_STAT_CMD_VALUE register field value. */
10475 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_CLR_MSK 0xffff0000
10476 /* The reset value of the ALT_NAND_DMA_LUN_STAT_CMD_VALUE register field. */
10477 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_RESET 0x7878
10478 /* Extracts the ALT_NAND_DMA_LUN_STAT_CMD_VALUE field value from a register. */
10479 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
10480 /* Produces a ALT_NAND_DMA_LUN_STAT_CMD_VALUE register field value suitable for setting the register. */
10481 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
10482 
10483 #ifndef __ASSEMBLY__
10484 /*
10485  * WARNING: The C register and register group struct declarations are provided for
10486  * convenience and illustrative purposes. They should, however, be used with
10487  * caution as the C language standard provides no guarantees about the alignment or
10488  * atomicity of device memory accesses. The recommended practice for writing
10489  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10490  * alt_write_word() functions.
10491  *
10492  * The struct declaration for register ALT_NAND_DMA_LUN_STAT_CMD.
10493  */
10494 struct ALT_NAND_DMA_LUN_STAT_CMD_s
10495 {
10496  uint32_t value : 16; /* ALT_NAND_DMA_LUN_STAT_CMD_VALUE */
10497  uint32_t : 16; /* *UNDEFINED* */
10498 };
10499 
10500 /* The typedef declaration for register ALT_NAND_DMA_LUN_STAT_CMD. */
10501 typedef volatile struct ALT_NAND_DMA_LUN_STAT_CMD_s ALT_NAND_DMA_LUN_STAT_CMD_t;
10502 #endif /* __ASSEMBLY__ */
10503 
10504 /* The byte offset of the ALT_NAND_DMA_LUN_STAT_CMD register from the beginning of the component. */
10505 #define ALT_NAND_DMA_LUN_STAT_CMD_OFST 0xa0
10506 
10507 #ifndef __ASSEMBLY__
10508 /*
10509  * WARNING: The C register and register group struct declarations are provided for
10510  * convenience and illustrative purposes. They should, however, be used with
10511  * caution as the C language standard provides no guarantees about the alignment or
10512  * atomicity of device memory accesses. The recommended practice for writing
10513  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10514  * alt_write_word() functions.
10515  *
10516  * The struct declaration for register group ALT_NAND_DMA.
10517  */
10518 struct ALT_NAND_DMA_s
10519 {
10520  ALT_NAND_DMA_DMA_EN_t dma_enable; /* ALT_NAND_DMA_DMA_EN */
10521  volatile uint32_t _pad_0x4_0x1f[7]; /* *UNDEFINED* */
10522  ALT_NAND_DMA_DMA_INTR_t dma_intr; /* ALT_NAND_DMA_DMA_INTR */
10523  volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
10524  ALT_NAND_DMA_DMA_INTR_EN_t dma_intr_en; /* ALT_NAND_DMA_DMA_INTR_EN */
10525  volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
10526  ALT_NAND_DMA_TGT_ERR_ADDR_LO_t target_err_addr_lo; /* ALT_NAND_DMA_TGT_ERR_ADDR_LO */
10527  volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
10528  ALT_NAND_DMA_TGT_ERR_ADDR_HI_t target_err_addr_hi; /* ALT_NAND_DMA_TGT_ERR_ADDR_HI */
10529  volatile uint32_t _pad_0x54_0x6f[7]; /* *UNDEFINED* */
10530  ALT_NAND_DMA_FLSH_BURST_LEN_t flash_burst_length; /* ALT_NAND_DMA_FLSH_BURST_LEN */
10531  volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
10532  ALT_NAND_DMA_INTRLV_t chip_interleave_enable_and_allow_int_reads; /* ALT_NAND_DMA_INTRLV */
10533  volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
10534  ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_t no_of_blocks_per_lun; /* ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN */
10535  volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
10536  ALT_NAND_DMA_LUN_STAT_CMD_t lun_status_cmd; /* ALT_NAND_DMA_LUN_STAT_CMD */
10537 };
10538 
10539 /* The typedef declaration for register group ALT_NAND_DMA. */
10540 typedef volatile struct ALT_NAND_DMA_s ALT_NAND_DMA_t;
10541 /* The struct declaration for the raw register contents of register group ALT_NAND_DMA. */
10542 struct ALT_NAND_DMA_raw_s
10543 {
10544  volatile uint32_t dma_enable; /* ALT_NAND_DMA_DMA_EN */
10545  uint32_t _pad_0x4_0x1f[7]; /* *UNDEFINED* */
10546  volatile uint32_t dma_intr; /* ALT_NAND_DMA_DMA_INTR */
10547  uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
10548  volatile uint32_t dma_intr_en; /* ALT_NAND_DMA_DMA_INTR_EN */
10549  uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
10550  volatile uint32_t target_err_addr_lo; /* ALT_NAND_DMA_TGT_ERR_ADDR_LO */
10551  uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
10552  volatile uint32_t target_err_addr_hi; /* ALT_NAND_DMA_TGT_ERR_ADDR_HI */
10553  uint32_t _pad_0x54_0x6f[7]; /* *UNDEFINED* */
10554  volatile uint32_t flash_burst_length; /* ALT_NAND_DMA_FLSH_BURST_LEN */
10555  uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
10556  volatile uint32_t chip_interleave_enable_and_allow_int_reads; /* ALT_NAND_DMA_INTRLV */
10557  uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
10558  volatile uint32_t no_of_blocks_per_lun; /* ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN */
10559  uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
10560  volatile uint32_t lun_status_cmd; /* ALT_NAND_DMA_LUN_STAT_CMD */
10561 };
10562 
10563 /* The typedef declaration for the raw register contents of register group ALT_NAND_DMA. */
10564 typedef volatile struct ALT_NAND_DMA_raw_s ALT_NAND_DMA_raw_t;
10565 #endif /* __ASSEMBLY__ */
10566 
10567 
10568 #ifndef __ASSEMBLY__
10569 /*
10570  * WARNING: The C register and register group struct declarations are provided for
10571  * convenience and illustrative purposes. They should, however, be used with
10572  * caution as the C language standard provides no guarantees about the alignment or
10573  * atomicity of device memory accesses. The recommended practice for writing
10574  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10575  * alt_write_word() functions.
10576  *
10577  * The struct declaration for register group ALT_NAND.
10578  */
10579 struct ALT_NAND_s
10580 {
10581  ALT_NAND_CFG_t config; /* ALT_NAND_CFG */
10582  volatile uint32_t _pad_0x2b4_0x2ff[19]; /* *UNDEFINED* */
10583  ALT_NAND_PARAM_t param; /* ALT_NAND_PARAM */
10584  volatile uint32_t _pad_0x3f4_0x3ff[3]; /* *UNDEFINED* */
10585  ALT_NAND_STAT_t status; /* ALT_NAND_STAT */
10586  volatile uint32_t _pad_0x544_0x64f[67]; /* *UNDEFINED* */
10587  ALT_NAND_ECC_t ecc; /* ALT_NAND_ECC */
10588  volatile uint32_t _pad_0x664_0x6ff[39]; /* *UNDEFINED* */
10589  ALT_NAND_DMA_t dma; /* ALT_NAND_DMA */
10590  volatile uint32_t _pad_0x7a4_0x800[23]; /* *UNDEFINED* */
10591 };
10592 
10593 /* The typedef declaration for register group ALT_NAND. */
10594 typedef volatile struct ALT_NAND_s ALT_NAND_t;
10595 /* The struct declaration for the raw register contents of register group ALT_NAND. */
10596 struct ALT_NAND_raw_s
10597 {
10598  ALT_NAND_CFG_raw_t config; /* ALT_NAND_CFG */
10599  uint32_t _pad_0x2b4_0x2ff[19]; /* *UNDEFINED* */
10600  ALT_NAND_PARAM_raw_t param; /* ALT_NAND_PARAM */
10601  uint32_t _pad_0x3f4_0x3ff[3]; /* *UNDEFINED* */
10602  ALT_NAND_STAT_raw_t status; /* ALT_NAND_STAT */
10603  uint32_t _pad_0x544_0x64f[67]; /* *UNDEFINED* */
10604  ALT_NAND_ECC_raw_t ecc; /* ALT_NAND_ECC */
10605  uint32_t _pad_0x664_0x6ff[39]; /* *UNDEFINED* */
10606  ALT_NAND_DMA_raw_t dma; /* ALT_NAND_DMA */
10607  uint32_t _pad_0x7a4_0x800[23]; /* *UNDEFINED* */
10608 };
10609 
10610 /* The typedef declaration for the raw register contents of register group ALT_NAND. */
10611 typedef volatile struct ALT_NAND_raw_s ALT_NAND_raw_t;
10612 #endif /* __ASSEMBLY__ */
10613 
10614 
10615 #ifdef __cplusplus
10616 }
10617 #endif /* __cplusplus */
10618 #endif /* __ALTERA_ALT_NAND_H__ */
10619