Hardware Libraries  20.1
Stratix 10 SoC Hardware Manager
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System Level Cache Management API

Description

This API group provides cache maintenance operations which affects multiple cache levels.

As all caches are built into the MPCore, this API is provided mostly for backwards compatability with previous HWLibs caching API.

Macros

#define ALT_CACHE_LINE_SIZE   (64)
 

Functions

ALT_STATUS_CODE alt_cache_system_enable (void)
 
ALT_STATUS_CODE alt_cache_system_disable (void)
 
ALT_STATUS_CODE alt_cache_system_data_invalidate (void *va, size_t length)
 
ALT_STATUS_CODE alt_cache_system_data_clean (void *va, size_t length)
 
ALT_STATUS_CODE alt_cache_system_data_purge (void *va, size_t length)
 

Macro Definitions

#define ALT_CACHE_LINE_SIZE   (64)

This is the system wide cache line size, given in bytes.

Function Documentation

ALT_STATUS_CODE alt_cache_system_enable ( void  )

Enables all caches and features which improve reliability and speed on all cache controllers visible to the current CPU core. All necessary cache maintenance operations will be done automatically.

The MMU must be enabled before calling this API. It is not recommended to enable/disable the cache frequently. The system may run into undetermined state.

Return values
ALT_E_SUCCESSThe operation was successful.
ALT_E_ERRORThe operation failed.
ALT_STATUS_CODE alt_cache_system_disable ( void  )

Disables all cache controllers visible to the current CPU core. All necessary cache maintenance operations will be done automatically.

It is not recommended to enable/disable the cache frequently. The system may run into undetermined state.

Return values
ALT_E_SUCCESSThe operation was successful.
ALT_E_ERRORThe operation failed.
ALT_STATUS_CODE alt_cache_system_data_invalidate ( void *  va,
size_t  length 
)

Invalidates the specified contents of all cache levels visible to the current CPU core for the given memory segment.

The memory segment address and length specified must align to the characteristics of the cache line. This means the address and length must be multiples of the cache line size. To determine the cache line size, use the ALT_CACHE_LINE_SIZE macro.

For the most part, calling this API on memory backed by SDRAM and OCRAM is unnecessary because the CCU (Cache Coherency Unit), which is part of the interconnect, will automatically maintain cache coherency with the Cortex-A53. If memory is backed with another RAM, such as FPGA memory, calling this API is required with the default CCU setup.

Parameters
vaThe virtual address of the memory segment to be invalidated.
lengthThe length of the memory segment to be invalidated.
Return values
ALT_E_SUCCESSThe operation was successful.
ALT_E_ERRORThe operation failed.
ALT_E_BAD_ARGThe memory segment is invalid.
ALT_STATUS_CODE alt_cache_system_data_clean ( void *  va,
size_t  length 
)

Cleans the specified contents of all cache levels visible to the current CPU core for the given memory segment.

The memory segment address and length specified must align to the characteristics of the cache line. This means the address and length must be multiples of the cache line size. To determine the cache line size, use the ALT_CACHE_LINE_SIZE macro.

For the most part, calling this API on memory backed by SDRAM and OCRAM is unnecessary because the CCU (Cache Coherency Unit), which is part of the interconnect, will automatically maintain cache coherency with the Cortex-A53. If memory is backed with another RAM, such as FPGA memory, calling this API is required with the default CCU setup.

Parameters
vaThe virtual address of the memory segment to be cleaned.
lengthThe length of the memory segment to be cleaned.
Return values
ALT_E_SUCCESSThe operation was successful.
ALT_E_ERRORThe operation failed.
ALT_E_BAD_ARGThe memory segment is invalid.
ALT_STATUS_CODE alt_cache_system_data_purge ( void *  va,
size_t  length 
)

Cleans and invalidates the specified contents of all cache levels visible to the current CPU core for the given memory segment.

The memory segment address and length specified must align to the characteristics of the cache line. This means the address and length must be multiples of the cache line size. To determine the cache line size, use the ALT_CACHE_LINE_SIZE macro.

For the most part, calling this API on memory backed by SDRAM and OCRAM is unnecessary because the CCU (Cache Coherency Unit), which is part of the interconnect, will automatically maintain cache coherency with the Cortex-A53. If memory is backed with another RAM, such as FPGA memory, calling this API is required with the default CCU setup.

Parameters
vaThe virtual address of the memory segment to be purged.
lengthThe length of the memory segment to be purged.
Return values
ALT_E_SUCCESSThe operation was successful.
ALT_E_ERRORThe operation failed.
ALT_E_BAD_ARGThe memory segment is invalid.