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alt_wdt.h
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32 
33 /* Altera - ALT_WDT */
34 
35 #ifndef __ALT_SOCAL_WDT_H__
36 #define __ALT_SOCAL_WDT_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : WDT
50  *
51  */
52 /*
53  * Register : Control Register - WDT_CR
54  *
55  * Control Register
56  *
57  * Register Layout
58  *
59  * Bits | Access | Reset | Description
60  * :-------|:-------|:------|:----------------------
61  * [0] | RW | 0x0 | ALT_WDT_WDT_CR_WDT_EN
62  * [1] | RW | 0x0 | ALT_WDT_WDT_CR_RMOD
63  * [4:2] | RW | 0x4 | ALT_WDT_WDT_CR_RPL
64  * [31:5] | ??? | 0x0 | *UNDEFINED*
65  *
66  */
67 /*
68  * Field : WDT_EN
69  *
70  * When the configuration parameter WDT_ALWAYS_EN = 0, this bit can be set
71  *
72  * otherwise, it is read-only. This bit is used to enable and disable the
73  * DW_apb_wdt.
74  *
75  * When disabled, the counter does not decrement. Thus, no interrupts or system
76  * resets
77  *
78  * are generated.
79  *
80  * The DW_apb_wdt is used to prevent system lock-up. To prevent a software bug from
81  *
82  * disabling the DW_apb_wdt, once this bit has been enabled, it can be cleared only
83  * by
84  *
85  * a system reset.
86  *
87  * 0 = WDT disabled.
88  *
89  * 1 = WDT enabled.
90  *
91  * Field Enumeration Values:
92  *
93  * Enum | Value | Description
94  * :---------------------------------|:------|:------------------------
95  * ALT_WDT_WDT_CR_WDT_EN_E_DISABLED | 0x0 | Watchdog timer disabled
96  * ALT_WDT_WDT_CR_WDT_EN_E_ENABLED | 0x1 | Watchdog timer enabled
97  *
98  * Field Access Macros:
99  *
100  */
101 /*
102  * Enumerated value for register field ALT_WDT_WDT_CR_WDT_EN
103  *
104  * Watchdog timer disabled
105  */
106 #define ALT_WDT_WDT_CR_WDT_EN_E_DISABLED 0x0
107 /*
108  * Enumerated value for register field ALT_WDT_WDT_CR_WDT_EN
109  *
110  * Watchdog timer enabled
111  */
112 #define ALT_WDT_WDT_CR_WDT_EN_E_ENABLED 0x1
113 
114 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_CR_WDT_EN register field. */
115 #define ALT_WDT_WDT_CR_WDT_EN_LSB 0
116 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_CR_WDT_EN register field. */
117 #define ALT_WDT_WDT_CR_WDT_EN_MSB 0
118 /* The width in bits of the ALT_WDT_WDT_CR_WDT_EN register field. */
119 #define ALT_WDT_WDT_CR_WDT_EN_WIDTH 1
120 /* The mask used to set the ALT_WDT_WDT_CR_WDT_EN register field value. */
121 #define ALT_WDT_WDT_CR_WDT_EN_SET_MSK 0x00000001
122 /* The mask used to clear the ALT_WDT_WDT_CR_WDT_EN register field value. */
123 #define ALT_WDT_WDT_CR_WDT_EN_CLR_MSK 0xfffffffe
124 /* The reset value of the ALT_WDT_WDT_CR_WDT_EN register field. */
125 #define ALT_WDT_WDT_CR_WDT_EN_RESET 0x0
126 /* Extracts the ALT_WDT_WDT_CR_WDT_EN field value from a register. */
127 #define ALT_WDT_WDT_CR_WDT_EN_GET(value) (((value) & 0x00000001) >> 0)
128 /* Produces a ALT_WDT_WDT_CR_WDT_EN register field value suitable for setting the register. */
129 #define ALT_WDT_WDT_CR_WDT_EN_SET(value) (((value) << 0) & 0x00000001)
130 
131 /*
132  * Field : RMOD
133  *
134  * Response mode. Writes have no effect when the parameter
135  *
136  * WDT_HC_RMOD = 1, thus this register becomes read-only.
137  *
138  * Selects the output response generated to a timeout.
139  *
140  * 0 = Generate a system reset.
141  *
142  * 1 = First generate an interrupt and if it is not cleared by the time
143  *
144  * a second timeout occurs then generate a system reset.
145  *
146  * Field Enumeration Values:
147  *
148  * Enum | Value | Description
149  * :--------------------------------|:------|:-------------------------------------------------
150  * ALT_WDT_WDT_CR_RMOD_E_RESET | 0x0 | Generate a system reset
151  * ALT_WDT_WDT_CR_RMOD_E_INTERRUPT | 0x1 | First generate an interrupt and if it is not
152  * : | | cleared by
153  * : | | the time a second timeout occurs then generate a
154  * : | | system reset
155  *
156  * Field Access Macros:
157  *
158  */
159 /*
160  * Enumerated value for register field ALT_WDT_WDT_CR_RMOD
161  *
162  * Generate a system reset
163  */
164 #define ALT_WDT_WDT_CR_RMOD_E_RESET 0x0
165 /*
166  * Enumerated value for register field ALT_WDT_WDT_CR_RMOD
167  *
168  * First generate an interrupt and if it is not cleared by
169  *
170  * the time a second timeout occurs then generate a system reset
171  */
172 #define ALT_WDT_WDT_CR_RMOD_E_INTERRUPT 0x1
173 
174 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_CR_RMOD register field. */
175 #define ALT_WDT_WDT_CR_RMOD_LSB 1
176 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_CR_RMOD register field. */
177 #define ALT_WDT_WDT_CR_RMOD_MSB 1
178 /* The width in bits of the ALT_WDT_WDT_CR_RMOD register field. */
179 #define ALT_WDT_WDT_CR_RMOD_WIDTH 1
180 /* The mask used to set the ALT_WDT_WDT_CR_RMOD register field value. */
181 #define ALT_WDT_WDT_CR_RMOD_SET_MSK 0x00000002
182 /* The mask used to clear the ALT_WDT_WDT_CR_RMOD register field value. */
183 #define ALT_WDT_WDT_CR_RMOD_CLR_MSK 0xfffffffd
184 /* The reset value of the ALT_WDT_WDT_CR_RMOD register field. */
185 #define ALT_WDT_WDT_CR_RMOD_RESET 0x0
186 /* Extracts the ALT_WDT_WDT_CR_RMOD field value from a register. */
187 #define ALT_WDT_WDT_CR_RMOD_GET(value) (((value) & 0x00000002) >> 1)
188 /* Produces a ALT_WDT_WDT_CR_RMOD register field value suitable for setting the register. */
189 #define ALT_WDT_WDT_CR_RMOD_SET(value) (((value) << 1) & 0x00000002)
190 
191 /*
192  * Field : RPL
193  *
194  * Reset pulse length. Writes have no effect when the configuration parameter
195  *
196  * WDT_HC_RPL is 1, making the register bits read-only. This is used to select
197  *
198  * the number of pclk cycles for which the system reset stays asserted. The
199  *
200  * range of values available is 2 to 256 pclk cycles.
201  *
202  * 000 - 2 pclk cycles
203  *
204  * 001 - 4 pclk cycles
205  *
206  * 010 - 8 pclk cycles
207  *
208  * 011 - 16 pclk cycles
209  *
210  * 100 - 32 pclk cycles
211  *
212  * 101 - 64 pclk cycles
213  *
214  * 110 - 128 pclk cycles
215  *
216  * 111 - 256 pclk cycles
217  *
218  * Field Enumeration Values:
219  *
220  * Enum | Value | Description
221  * :------------------------------------|:------|:----------------
222  * ALT_WDT_WDT_CR_RPL_E_PCLK_CYCLES2 | 0x0 | 2 pclk cycles
223  * ALT_WDT_WDT_CR_RPL_E_PCLK_CYCLES4 | 0x1 | 4 pclk cycles
224  * ALT_WDT_WDT_CR_RPL_E_PCLK_CYCLES8 | 0x2 | 8 pclk cycles
225  * ALT_WDT_WDT_CR_RPL_E_PCLK_CYCLES16 | 0x3 | 16 pclk cycles
226  * ALT_WDT_WDT_CR_RPL_E_PCLK_CYCLES32 | 0x4 | 32 pclk cycles
227  * ALT_WDT_WDT_CR_RPL_E_PCLK_CYCLES64 | 0x5 | 64 pclk cycles
228  * ALT_WDT_WDT_CR_RPL_E_PCLK_CYCLES128 | 0x6 | 128 pclk cycles
229  * ALT_WDT_WDT_CR_RPL_E_PCLK_CYCLES256 | 0x7 | 256 pclk cycles
230  *
231  * Field Access Macros:
232  *
233  */
234 /*
235  * Enumerated value for register field ALT_WDT_WDT_CR_RPL
236  *
237  * 2 pclk cycles
238  */
239 #define ALT_WDT_WDT_CR_RPL_E_PCLK_CYCLES2 0x0
240 /*
241  * Enumerated value for register field ALT_WDT_WDT_CR_RPL
242  *
243  * 4 pclk cycles
244  */
245 #define ALT_WDT_WDT_CR_RPL_E_PCLK_CYCLES4 0x1
246 /*
247  * Enumerated value for register field ALT_WDT_WDT_CR_RPL
248  *
249  * 8 pclk cycles
250  */
251 #define ALT_WDT_WDT_CR_RPL_E_PCLK_CYCLES8 0x2
252 /*
253  * Enumerated value for register field ALT_WDT_WDT_CR_RPL
254  *
255  * 16 pclk cycles
256  */
257 #define ALT_WDT_WDT_CR_RPL_E_PCLK_CYCLES16 0x3
258 /*
259  * Enumerated value for register field ALT_WDT_WDT_CR_RPL
260  *
261  * 32 pclk cycles
262  */
263 #define ALT_WDT_WDT_CR_RPL_E_PCLK_CYCLES32 0x4
264 /*
265  * Enumerated value for register field ALT_WDT_WDT_CR_RPL
266  *
267  * 64 pclk cycles
268  */
269 #define ALT_WDT_WDT_CR_RPL_E_PCLK_CYCLES64 0x5
270 /*
271  * Enumerated value for register field ALT_WDT_WDT_CR_RPL
272  *
273  * 128 pclk cycles
274  */
275 #define ALT_WDT_WDT_CR_RPL_E_PCLK_CYCLES128 0x6
276 /*
277  * Enumerated value for register field ALT_WDT_WDT_CR_RPL
278  *
279  * 256 pclk cycles
280  */
281 #define ALT_WDT_WDT_CR_RPL_E_PCLK_CYCLES256 0x7
282 
283 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_CR_RPL register field. */
284 #define ALT_WDT_WDT_CR_RPL_LSB 2
285 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_CR_RPL register field. */
286 #define ALT_WDT_WDT_CR_RPL_MSB 4
287 /* The width in bits of the ALT_WDT_WDT_CR_RPL register field. */
288 #define ALT_WDT_WDT_CR_RPL_WIDTH 3
289 /* The mask used to set the ALT_WDT_WDT_CR_RPL register field value. */
290 #define ALT_WDT_WDT_CR_RPL_SET_MSK 0x0000001c
291 /* The mask used to clear the ALT_WDT_WDT_CR_RPL register field value. */
292 #define ALT_WDT_WDT_CR_RPL_CLR_MSK 0xffffffe3
293 /* The reset value of the ALT_WDT_WDT_CR_RPL register field. */
294 #define ALT_WDT_WDT_CR_RPL_RESET 0x4
295 /* Extracts the ALT_WDT_WDT_CR_RPL field value from a register. */
296 #define ALT_WDT_WDT_CR_RPL_GET(value) (((value) & 0x0000001c) >> 2)
297 /* Produces a ALT_WDT_WDT_CR_RPL register field value suitable for setting the register. */
298 #define ALT_WDT_WDT_CR_RPL_SET(value) (((value) << 2) & 0x0000001c)
299 
300 #ifndef __ASSEMBLY__
301 /*
302  * WARNING: The C register and register group struct declarations are provided for
303  * convenience and illustrative purposes. They should, however, be used with
304  * caution as the C language standard provides no guarantees about the alignment or
305  * atomicity of device memory accesses. The recommended practice for coding device
306  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
307  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
308  * alt_write_dword() functions for 64 bit registers.
309  *
310  * The struct declaration for register ALT_WDT_WDT_CR.
311  */
312 struct ALT_WDT_WDT_CR_s
313 {
314  volatile uint32_t WDT_EN : 1; /* ALT_WDT_WDT_CR_WDT_EN */
315  volatile uint32_t RMOD : 1; /* ALT_WDT_WDT_CR_RMOD */
316  volatile uint32_t RPL : 3; /* ALT_WDT_WDT_CR_RPL */
317  uint32_t : 27; /* *UNDEFINED* */
318 };
319 
320 /* The typedef declaration for register ALT_WDT_WDT_CR. */
321 typedef struct ALT_WDT_WDT_CR_s ALT_WDT_WDT_CR_t;
322 #endif /* __ASSEMBLY__ */
323 
324 /* The reset value of the ALT_WDT_WDT_CR register. */
325 #define ALT_WDT_WDT_CR_RESET 0x00000010
326 /* The byte offset of the ALT_WDT_WDT_CR register from the beginning of the component. */
327 #define ALT_WDT_WDT_CR_OFST 0x0
328 /* The address of the ALT_WDT_WDT_CR register. */
329 #define ALT_WDT_WDT_CR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_WDT_WDT_CR_OFST))
330 
331 /*
332  * Register : Timeout Range Register - WDT_TORR
333  *
334  * Timeout Range Register
335  *
336  * Register Layout
337  *
338  * Bits | Access | Reset | Description
339  * :-------|:-------|:------|:--------------------------
340  * [3:0] | RW | 0xf | ALT_WDT_WDT_TORR_TOP
341  * [7:4] | RW | 0xf | ALT_WDT_WDT_TORR_TOP_INIT
342  * [31:8] | R | 0x0 | ALT_WDT_WDT_TORR_RESERVED
343  *
344  */
345 /*
346  * Field : TOP
347  *
348  * Timeout period. Writes have no effect when the configuration parameter
349  *
350  * WDT_HC_TOP = 1, thus making this register read-only. This field is used
351  *
352  * to select the timeout period from which the watchdog counter restarts.
353  *
354  * A change of the timeout period takes effect only after the next counter
355  *
356  * restart (kick). The range of values is limited by the WDT_CNT_WIDTH. If
357  *
358  * TOP is programmed to select a range that is greater than the counter width,
359  *
360  * the timeout period is truncated to fit to the counter width. This affects
361  *
362  * only the non-user specified values as users are limited to these boundaries
363  *
364  * during configuration. The range of values available for a 32-bit watchdog
365  *
366  * counter are:
367  *
368  * Where i = TOP and
369  *
370  * t = timeout period
371  *
372  * For i = 0 to 15
373  *
374  * if WDT_USE_FIX_TOP==1
375  *
376  * t = 2(16 + i)
377  *
378  * else
379  *
380  * t = WDT_USER_TOP_(i)
381  *
382  * Field Enumeration Values:
383  *
384  * Enum | Value | Description
385  * :--------------------------------------|:------|:-------------------------------------------
386  * ALT_WDT_WDT_TORR_TOP_E_USER0_OR_64K | 0x0 | Time out of WDT_USER_TOP_0 or 64K Clocks
387  * ALT_WDT_WDT_TORR_TOP_E_USER1_OR_128K | 0x1 | Time out of WDT_USER_TOP_1 or 128K Clocks
388  * ALT_WDT_WDT_TORR_TOP_E_USER2_OR_256K | 0x2 | Time out of WDT_USER_TOP_2 or 256K Clocks
389  * ALT_WDT_WDT_TORR_TOP_E_USER3_OR_512K | 0x3 | Time out of WDT_USER_TOP_3 or 512K Clocks
390  * ALT_WDT_WDT_TORR_TOP_E_USER4_OR_1M | 0x4 | Time out of WDT_USER_TOP_4 or 1M Clocks
391  * ALT_WDT_WDT_TORR_TOP_E_USER5_OR_2M | 0x5 | Time out of WDT_USER_TOP_5 or 2M Clocks
392  * ALT_WDT_WDT_TORR_TOP_E_USER6_OR_4M | 0x6 | Time out of WDT_USER_TOP_6 or 4M Clocks
393  * ALT_WDT_WDT_TORR_TOP_E_USER7_OR_8M | 0x7 | Time out of WDT_USER_TOP_7 or 8M Clocks
394  * ALT_WDT_WDT_TORR_TOP_E_USER8_OR_16M | 0x8 | Time out of WDT_USER_TOP_8 or 16M Clocks
395  * ALT_WDT_WDT_TORR_TOP_E_USER9_OR_32M | 0x9 | Time out of WDT_USER_TOP_9 or 32M Clocks
396  * ALT_WDT_WDT_TORR_TOP_E_USER10_OR_64M | 0xa | Time out of WDT_USER_TOP_10 or 64M Clocks
397  * ALT_WDT_WDT_TORR_TOP_E_USER11_OR_128M | 0xb | Time out of WDT_USER_TOP_11 or 128M Clocks
398  * ALT_WDT_WDT_TORR_TOP_E_USER12_OR_256M | 0xc | Time out of WDT_USER_TOP_12 or 256M Clocks
399  * ALT_WDT_WDT_TORR_TOP_E_USER13_OR_512M | 0xd | Time out of WDT_USER_TOP_13 or 512M Clocks
400  * ALT_WDT_WDT_TORR_TOP_E_USER14_OR_1G | 0xe | Time out of WDT_USER_TOP_14 or 1G Clocks
401  * ALT_WDT_WDT_TORR_TOP_E_USER15_OR_2G | 0xf | Time out of WDT_USER_TOP_15 or 2G Clocks
402  *
403  * Field Access Macros:
404  *
405  */
406 /*
407  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP
408  *
409  * Time out of WDT_USER_TOP_0 or 64K Clocks
410  */
411 #define ALT_WDT_WDT_TORR_TOP_E_USER0_OR_64K 0x0
412 /*
413  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP
414  *
415  * Time out of WDT_USER_TOP_1 or 128K Clocks
416  */
417 #define ALT_WDT_WDT_TORR_TOP_E_USER1_OR_128K 0x1
418 /*
419  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP
420  *
421  * Time out of WDT_USER_TOP_2 or 256K Clocks
422  */
423 #define ALT_WDT_WDT_TORR_TOP_E_USER2_OR_256K 0x2
424 /*
425  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP
426  *
427  * Time out of WDT_USER_TOP_3 or 512K Clocks
428  */
429 #define ALT_WDT_WDT_TORR_TOP_E_USER3_OR_512K 0x3
430 /*
431  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP
432  *
433  * Time out of WDT_USER_TOP_4 or 1M Clocks
434  */
435 #define ALT_WDT_WDT_TORR_TOP_E_USER4_OR_1M 0x4
436 /*
437  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP
438  *
439  * Time out of WDT_USER_TOP_5 or 2M Clocks
440  */
441 #define ALT_WDT_WDT_TORR_TOP_E_USER5_OR_2M 0x5
442 /*
443  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP
444  *
445  * Time out of WDT_USER_TOP_6 or 4M Clocks
446  */
447 #define ALT_WDT_WDT_TORR_TOP_E_USER6_OR_4M 0x6
448 /*
449  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP
450  *
451  * Time out of WDT_USER_TOP_7 or 8M Clocks
452  */
453 #define ALT_WDT_WDT_TORR_TOP_E_USER7_OR_8M 0x7
454 /*
455  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP
456  *
457  * Time out of WDT_USER_TOP_8 or 16M Clocks
458  */
459 #define ALT_WDT_WDT_TORR_TOP_E_USER8_OR_16M 0x8
460 /*
461  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP
462  *
463  * Time out of WDT_USER_TOP_9 or 32M Clocks
464  */
465 #define ALT_WDT_WDT_TORR_TOP_E_USER9_OR_32M 0x9
466 /*
467  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP
468  *
469  * Time out of WDT_USER_TOP_10 or 64M Clocks
470  */
471 #define ALT_WDT_WDT_TORR_TOP_E_USER10_OR_64M 0xa
472 /*
473  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP
474  *
475  * Time out of WDT_USER_TOP_11 or 128M Clocks
476  */
477 #define ALT_WDT_WDT_TORR_TOP_E_USER11_OR_128M 0xb
478 /*
479  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP
480  *
481  * Time out of WDT_USER_TOP_12 or 256M Clocks
482  */
483 #define ALT_WDT_WDT_TORR_TOP_E_USER12_OR_256M 0xc
484 /*
485  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP
486  *
487  * Time out of WDT_USER_TOP_13 or 512M Clocks
488  */
489 #define ALT_WDT_WDT_TORR_TOP_E_USER13_OR_512M 0xd
490 /*
491  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP
492  *
493  * Time out of WDT_USER_TOP_14 or 1G Clocks
494  */
495 #define ALT_WDT_WDT_TORR_TOP_E_USER14_OR_1G 0xe
496 /*
497  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP
498  *
499  * Time out of WDT_USER_TOP_15 or 2G Clocks
500  */
501 #define ALT_WDT_WDT_TORR_TOP_E_USER15_OR_2G 0xf
502 
503 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_TORR_TOP register field. */
504 #define ALT_WDT_WDT_TORR_TOP_LSB 0
505 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_TORR_TOP register field. */
506 #define ALT_WDT_WDT_TORR_TOP_MSB 3
507 /* The width in bits of the ALT_WDT_WDT_TORR_TOP register field. */
508 #define ALT_WDT_WDT_TORR_TOP_WIDTH 4
509 /* The mask used to set the ALT_WDT_WDT_TORR_TOP register field value. */
510 #define ALT_WDT_WDT_TORR_TOP_SET_MSK 0x0000000f
511 /* The mask used to clear the ALT_WDT_WDT_TORR_TOP register field value. */
512 #define ALT_WDT_WDT_TORR_TOP_CLR_MSK 0xfffffff0
513 /* The reset value of the ALT_WDT_WDT_TORR_TOP register field. */
514 #define ALT_WDT_WDT_TORR_TOP_RESET 0xf
515 /* Extracts the ALT_WDT_WDT_TORR_TOP field value from a register. */
516 #define ALT_WDT_WDT_TORR_TOP_GET(value) (((value) & 0x0000000f) >> 0)
517 /* Produces a ALT_WDT_WDT_TORR_TOP register field value suitable for setting the register. */
518 #define ALT_WDT_WDT_TORR_TOP_SET(value) (((value) << 0) & 0x0000000f)
519 
520 /*
521  * Field : TOP_INIT
522  *
523  * Timeout period for initialization.
524  *
525  * Writes to these register bits have no effect when the configuration
526  *
527  * parameter WDT_HC_TOP = 1 or WDT_ALWAYS_EN = 1. Used to
528  *
529  * select the timeout period that the watchdog counter restarts from for
530  *
531  * the first counter restart (kick). This register should be written after
532  *
533  * reset and before the WDT is enabled.
534  *
535  * A change of the TOP_INIT is seen only once the WDT has been
536  *
537  * enabled, and any change after the first kick is not seen as subsequent
538  *
539  * kicks use the period specified by the TOP bits.
540  *
541  * The range of values is limited by the WDT_CNT_WIDTH. If
542  *
543  * TOP_INIT is programmed to select a range that is greater than the
544  *
545  * counter width, the timeout period is truncated to fit to the counter
546  *
547  * width. This affects only the non-user specified values as users are
548  *
549  * limited to these boundaries during configuration.
550  *
551  * The range of values available for a 32-bit watchdog counter are:
552  *
553  * Where i = TOP_INIT and
554  *
555  * t = timeout period
556  *
557  * For i = 0 to 15
558  *
559  * if WDT_USE_FIX_TOP==1
560  *
561  * t = 2(16 + i)
562  *
563  * else
564  *
565  * t = WDT_USER_TOP_INIT_(i)
566  *
567  * NOTE: These bits exist only when the configuration parameter
568  *
569  * WDT_DUAL_TOP = 1, otherwise, they are fixed at zero.
570  *
571  * Field Enumeration Values:
572  *
573  * Enum | Value | Description
574  * :-------------------------------------------|:------|:------------------------------------------------
575  * ALT_WDT_WDT_TORR_TOP_INIT_E_USER0_OR_64K | 0x0 | Time out of WDT_USER_TOP_INIT_0 or 64K Clocks
576  * ALT_WDT_WDT_TORR_TOP_INIT_E_USER1_OR_128K | 0x1 | Time out of WDT_USER_TOP_INIT_1 or 128K Clocks
577  * ALT_WDT_WDT_TORR_TOP_INIT_E_USER2_OR_256K | 0x2 | Time out of WDT_USER_TOP_INIT_2 or 256K Clocks
578  * ALT_WDT_WDT_TORR_TOP_INIT_E_USER3_OR_512K | 0x3 | Time out of WDT_USER_TOP_INIT_3 or 512K Clocks
579  * ALT_WDT_WDT_TORR_TOP_INIT_E_USER4_OR_1M | 0x4 | Time out of WDT_USER_TOP_INIT_4 or 1M Clocks
580  * ALT_WDT_WDT_TORR_TOP_INIT_E_USER5_OR_2M | 0x5 | Time out of WDT_USER_TOP_INIT_5 or 2M Clocks
581  * ALT_WDT_WDT_TORR_TOP_INIT_E_USER6_OR_4M | 0x6 | Time out of WDT_USER_TOP_INIT_6 or 4M Clocks
582  * ALT_WDT_WDT_TORR_TOP_INIT_E_USER7_OR_8M | 0x7 | Time out of WDT_USER_TOP_INIT_7 or 8M Clocks
583  * ALT_WDT_WDT_TORR_TOP_INIT_E_USER8_OR_16M | 0x8 | Time out of WDT_USER_TOP_INIT_8 or 16M Clocks
584  * ALT_WDT_WDT_TORR_TOP_INIT_E_USER9_OR_32M | 0x9 | Time out of WDT_USER_TOP_INIT_9 or 32M Clocks
585  * ALT_WDT_WDT_TORR_TOP_INIT_E_USER10_OR_64M | 0xa | Time out of WDT_USER_TOP_INIT_10 or 64M Clocks
586  * ALT_WDT_WDT_TORR_TOP_INIT_E_USER11_OR_128M | 0xb | Time out of WDT_USER_TOP_INIT_11 or 128M Clocks
587  * ALT_WDT_WDT_TORR_TOP_INIT_E_USER12_OR_256M | 0xc | Time out of WDT_USER_TOP_INIT_12 or 256M Clocks
588  * ALT_WDT_WDT_TORR_TOP_INIT_E_USER13_OR_512M | 0xd | Time out of WDT_USER_TOP_INIT_13 or 512M Clocks
589  * ALT_WDT_WDT_TORR_TOP_INIT_E_USER14_OR_1G | 0xe | Time out of WDT_USER_TOP_INIT_14 or 1G Clocks
590  * ALT_WDT_WDT_TORR_TOP_INIT_E_USER15_OR_2G | 0xf | Time out of WDT_USER_TOP_INIT_15 or 2G Clocks
591  *
592  * Field Access Macros:
593  *
594  */
595 /*
596  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP_INIT
597  *
598  * Time out of WDT_USER_TOP_INIT_0 or 64K Clocks
599  */
600 #define ALT_WDT_WDT_TORR_TOP_INIT_E_USER0_OR_64K 0x0
601 /*
602  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP_INIT
603  *
604  * Time out of WDT_USER_TOP_INIT_1 or 128K Clocks
605  */
606 #define ALT_WDT_WDT_TORR_TOP_INIT_E_USER1_OR_128K 0x1
607 /*
608  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP_INIT
609  *
610  * Time out of WDT_USER_TOP_INIT_2 or 256K Clocks
611  */
612 #define ALT_WDT_WDT_TORR_TOP_INIT_E_USER2_OR_256K 0x2
613 /*
614  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP_INIT
615  *
616  * Time out of WDT_USER_TOP_INIT_3 or 512K Clocks
617  */
618 #define ALT_WDT_WDT_TORR_TOP_INIT_E_USER3_OR_512K 0x3
619 /*
620  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP_INIT
621  *
622  * Time out of WDT_USER_TOP_INIT_4 or 1M Clocks
623  */
624 #define ALT_WDT_WDT_TORR_TOP_INIT_E_USER4_OR_1M 0x4
625 /*
626  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP_INIT
627  *
628  * Time out of WDT_USER_TOP_INIT_5 or 2M Clocks
629  */
630 #define ALT_WDT_WDT_TORR_TOP_INIT_E_USER5_OR_2M 0x5
631 /*
632  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP_INIT
633  *
634  * Time out of WDT_USER_TOP_INIT_6 or 4M Clocks
635  */
636 #define ALT_WDT_WDT_TORR_TOP_INIT_E_USER6_OR_4M 0x6
637 /*
638  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP_INIT
639  *
640  * Time out of WDT_USER_TOP_INIT_7 or 8M Clocks
641  */
642 #define ALT_WDT_WDT_TORR_TOP_INIT_E_USER7_OR_8M 0x7
643 /*
644  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP_INIT
645  *
646  * Time out of WDT_USER_TOP_INIT_8 or 16M Clocks
647  */
648 #define ALT_WDT_WDT_TORR_TOP_INIT_E_USER8_OR_16M 0x8
649 /*
650  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP_INIT
651  *
652  * Time out of WDT_USER_TOP_INIT_9 or 32M Clocks
653  */
654 #define ALT_WDT_WDT_TORR_TOP_INIT_E_USER9_OR_32M 0x9
655 /*
656  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP_INIT
657  *
658  * Time out of WDT_USER_TOP_INIT_10 or 64M Clocks
659  */
660 #define ALT_WDT_WDT_TORR_TOP_INIT_E_USER10_OR_64M 0xa
661 /*
662  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP_INIT
663  *
664  * Time out of WDT_USER_TOP_INIT_11 or 128M Clocks
665  */
666 #define ALT_WDT_WDT_TORR_TOP_INIT_E_USER11_OR_128M 0xb
667 /*
668  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP_INIT
669  *
670  * Time out of WDT_USER_TOP_INIT_12 or 256M Clocks
671  */
672 #define ALT_WDT_WDT_TORR_TOP_INIT_E_USER12_OR_256M 0xc
673 /*
674  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP_INIT
675  *
676  * Time out of WDT_USER_TOP_INIT_13 or 512M Clocks
677  */
678 #define ALT_WDT_WDT_TORR_TOP_INIT_E_USER13_OR_512M 0xd
679 /*
680  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP_INIT
681  *
682  * Time out of WDT_USER_TOP_INIT_14 or 1G Clocks
683  */
684 #define ALT_WDT_WDT_TORR_TOP_INIT_E_USER14_OR_1G 0xe
685 /*
686  * Enumerated value for register field ALT_WDT_WDT_TORR_TOP_INIT
687  *
688  * Time out of WDT_USER_TOP_INIT_15 or 2G Clocks
689  */
690 #define ALT_WDT_WDT_TORR_TOP_INIT_E_USER15_OR_2G 0xf
691 
692 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_TORR_TOP_INIT register field. */
693 #define ALT_WDT_WDT_TORR_TOP_INIT_LSB 4
694 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_TORR_TOP_INIT register field. */
695 #define ALT_WDT_WDT_TORR_TOP_INIT_MSB 7
696 /* The width in bits of the ALT_WDT_WDT_TORR_TOP_INIT register field. */
697 #define ALT_WDT_WDT_TORR_TOP_INIT_WIDTH 4
698 /* The mask used to set the ALT_WDT_WDT_TORR_TOP_INIT register field value. */
699 #define ALT_WDT_WDT_TORR_TOP_INIT_SET_MSK 0x000000f0
700 /* The mask used to clear the ALT_WDT_WDT_TORR_TOP_INIT register field value. */
701 #define ALT_WDT_WDT_TORR_TOP_INIT_CLR_MSK 0xffffff0f
702 /* The reset value of the ALT_WDT_WDT_TORR_TOP_INIT register field. */
703 #define ALT_WDT_WDT_TORR_TOP_INIT_RESET 0xf
704 /* Extracts the ALT_WDT_WDT_TORR_TOP_INIT field value from a register. */
705 #define ALT_WDT_WDT_TORR_TOP_INIT_GET(value) (((value) & 0x000000f0) >> 4)
706 /* Produces a ALT_WDT_WDT_TORR_TOP_INIT register field value suitable for setting the register. */
707 #define ALT_WDT_WDT_TORR_TOP_INIT_SET(value) (((value) << 4) & 0x000000f0)
708 
709 /*
710  * Field : Reserved
711  *
712  * Reserved and read as 0.
713  *
714  * Field Access Macros:
715  *
716  */
717 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_TORR_RESERVED register field. */
718 #define ALT_WDT_WDT_TORR_RESERVED_LSB 8
719 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_TORR_RESERVED register field. */
720 #define ALT_WDT_WDT_TORR_RESERVED_MSB 31
721 /* The width in bits of the ALT_WDT_WDT_TORR_RESERVED register field. */
722 #define ALT_WDT_WDT_TORR_RESERVED_WIDTH 24
723 /* The mask used to set the ALT_WDT_WDT_TORR_RESERVED register field value. */
724 #define ALT_WDT_WDT_TORR_RESERVED_SET_MSK 0xffffff00
725 /* The mask used to clear the ALT_WDT_WDT_TORR_RESERVED register field value. */
726 #define ALT_WDT_WDT_TORR_RESERVED_CLR_MSK 0x000000ff
727 /* The reset value of the ALT_WDT_WDT_TORR_RESERVED register field. */
728 #define ALT_WDT_WDT_TORR_RESERVED_RESET 0x0
729 /* Extracts the ALT_WDT_WDT_TORR_RESERVED field value from a register. */
730 #define ALT_WDT_WDT_TORR_RESERVED_GET(value) (((value) & 0xffffff00) >> 8)
731 /* Produces a ALT_WDT_WDT_TORR_RESERVED register field value suitable for setting the register. */
732 #define ALT_WDT_WDT_TORR_RESERVED_SET(value) (((value) << 8) & 0xffffff00)
733 
734 #ifndef __ASSEMBLY__
735 /*
736  * WARNING: The C register and register group struct declarations are provided for
737  * convenience and illustrative purposes. They should, however, be used with
738  * caution as the C language standard provides no guarantees about the alignment or
739  * atomicity of device memory accesses. The recommended practice for coding device
740  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
741  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
742  * alt_write_dword() functions for 64 bit registers.
743  *
744  * The struct declaration for register ALT_WDT_WDT_TORR.
745  */
746 struct ALT_WDT_WDT_TORR_s
747 {
748  volatile uint32_t TOP : 4; /* ALT_WDT_WDT_TORR_TOP */
749  volatile uint32_t TOP_INIT : 4; /* ALT_WDT_WDT_TORR_TOP_INIT */
750  const volatile uint32_t Reserved : 24; /* ALT_WDT_WDT_TORR_RESERVED */
751 };
752 
753 /* The typedef declaration for register ALT_WDT_WDT_TORR. */
754 typedef struct ALT_WDT_WDT_TORR_s ALT_WDT_WDT_TORR_t;
755 #endif /* __ASSEMBLY__ */
756 
757 /* The reset value of the ALT_WDT_WDT_TORR register. */
758 #define ALT_WDT_WDT_TORR_RESET 0x000000ff
759 /* The byte offset of the ALT_WDT_WDT_TORR register from the beginning of the component. */
760 #define ALT_WDT_WDT_TORR_OFST 0x4
761 /* The address of the ALT_WDT_WDT_TORR register. */
762 #define ALT_WDT_WDT_TORR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_WDT_WDT_TORR_OFST))
763 
764 /*
765  * Register : Current Counter Value Register - WDT_CCVR
766  *
767  * Current Counter Value Register.
768  *
769  * Register Layout
770  *
771  * Bits | Access | Reset | Description
772  * :-------|:-------|:-----------|:--------------------------
773  * [31:0] | R | 0x7fffffff | ALT_WDT_WDT_CCVR_WDT_CCVR
774  *
775  */
776 /*
777  * Field : wdt_ccvr
778  *
779  * This register, when read, is the current value of the internal
780  *
781  * counter. This value is read coherently when ever it is read,
782  *
783  * which is relevant when the APB_DATA_WIDTH is less than the
784  *
785  * counter width.
786  *
787  * Field Access Macros:
788  *
789  */
790 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_CCVR_WDT_CCVR register field. */
791 #define ALT_WDT_WDT_CCVR_WDT_CCVR_LSB 0
792 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_CCVR_WDT_CCVR register field. */
793 #define ALT_WDT_WDT_CCVR_WDT_CCVR_MSB 31
794 /* The width in bits of the ALT_WDT_WDT_CCVR_WDT_CCVR register field. */
795 #define ALT_WDT_WDT_CCVR_WDT_CCVR_WIDTH 32
796 /* The mask used to set the ALT_WDT_WDT_CCVR_WDT_CCVR register field value. */
797 #define ALT_WDT_WDT_CCVR_WDT_CCVR_SET_MSK 0xffffffff
798 /* The mask used to clear the ALT_WDT_WDT_CCVR_WDT_CCVR register field value. */
799 #define ALT_WDT_WDT_CCVR_WDT_CCVR_CLR_MSK 0x00000000
800 /* The reset value of the ALT_WDT_WDT_CCVR_WDT_CCVR register field. */
801 #define ALT_WDT_WDT_CCVR_WDT_CCVR_RESET 0x7fffffff
802 /* Extracts the ALT_WDT_WDT_CCVR_WDT_CCVR field value from a register. */
803 #define ALT_WDT_WDT_CCVR_WDT_CCVR_GET(value) (((value) & 0xffffffff) >> 0)
804 /* Produces a ALT_WDT_WDT_CCVR_WDT_CCVR register field value suitable for setting the register. */
805 #define ALT_WDT_WDT_CCVR_WDT_CCVR_SET(value) (((value) << 0) & 0xffffffff)
806 
807 #ifndef __ASSEMBLY__
808 /*
809  * WARNING: The C register and register group struct declarations are provided for
810  * convenience and illustrative purposes. They should, however, be used with
811  * caution as the C language standard provides no guarantees about the alignment or
812  * atomicity of device memory accesses. The recommended practice for coding device
813  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
814  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
815  * alt_write_dword() functions for 64 bit registers.
816  *
817  * The struct declaration for register ALT_WDT_WDT_CCVR.
818  */
819 struct ALT_WDT_WDT_CCVR_s
820 {
821  const volatile uint32_t wdt_ccvr : 32; /* ALT_WDT_WDT_CCVR_WDT_CCVR */
822 };
823 
824 /* The typedef declaration for register ALT_WDT_WDT_CCVR. */
825 typedef struct ALT_WDT_WDT_CCVR_s ALT_WDT_WDT_CCVR_t;
826 #endif /* __ASSEMBLY__ */
827 
828 /* The reset value of the ALT_WDT_WDT_CCVR register. */
829 #define ALT_WDT_WDT_CCVR_RESET 0x7fffffff
830 /* The byte offset of the ALT_WDT_WDT_CCVR register from the beginning of the component. */
831 #define ALT_WDT_WDT_CCVR_OFST 0x8
832 /* The address of the ALT_WDT_WDT_CCVR register. */
833 #define ALT_WDT_WDT_CCVR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_WDT_WDT_CCVR_OFST))
834 
835 /*
836  * Register : Counter Restart Register - WDT_CRR
837  *
838  * Counter Restart Register.
839  *
840  * Register Layout
841  *
842  * Bits | Access | Reset | Description
843  * :-------|:-------|:------|:------------------------
844  * [7:0] | W | 0x0 | ALT_WDT_WDT_CRR_WDT_CRR
845  * [31:8] | ??? | 0x0 | *UNDEFINED*
846  *
847  */
848 /*
849  * Field : wdt_crr
850  *
851  * This register is used to restart the WDT counter. As a safety feature to
852  *
853  * prevent accidental restarts, the value 0x76 must be written. A restart also
854  *
855  * clears the WDT interrupt. Reading this register returns zero.
856  *
857  * Field Enumeration Values:
858  *
859  * Enum | Value | Description
860  * :----------------------------------|:------|:-------------------------------
861  * ALT_WDT_WDT_CRR_WDT_CRR_E_RESTART | 0x76 | Watchdog timer restart command
862  *
863  * Field Access Macros:
864  *
865  */
866 /*
867  * Enumerated value for register field ALT_WDT_WDT_CRR_WDT_CRR
868  *
869  * Watchdog timer restart command
870  */
871 #define ALT_WDT_WDT_CRR_WDT_CRR_E_RESTART 0x76
872 
873 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_CRR_WDT_CRR register field. */
874 #define ALT_WDT_WDT_CRR_WDT_CRR_LSB 0
875 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_CRR_WDT_CRR register field. */
876 #define ALT_WDT_WDT_CRR_WDT_CRR_MSB 7
877 /* The width in bits of the ALT_WDT_WDT_CRR_WDT_CRR register field. */
878 #define ALT_WDT_WDT_CRR_WDT_CRR_WIDTH 8
879 /* The mask used to set the ALT_WDT_WDT_CRR_WDT_CRR register field value. */
880 #define ALT_WDT_WDT_CRR_WDT_CRR_SET_MSK 0x000000ff
881 /* The mask used to clear the ALT_WDT_WDT_CRR_WDT_CRR register field value. */
882 #define ALT_WDT_WDT_CRR_WDT_CRR_CLR_MSK 0xffffff00
883 /* The reset value of the ALT_WDT_WDT_CRR_WDT_CRR register field. */
884 #define ALT_WDT_WDT_CRR_WDT_CRR_RESET 0x0
885 /* Extracts the ALT_WDT_WDT_CRR_WDT_CRR field value from a register. */
886 #define ALT_WDT_WDT_CRR_WDT_CRR_GET(value) (((value) & 0x000000ff) >> 0)
887 /* Produces a ALT_WDT_WDT_CRR_WDT_CRR register field value suitable for setting the register. */
888 #define ALT_WDT_WDT_CRR_WDT_CRR_SET(value) (((value) << 0) & 0x000000ff)
889 
890 #ifndef __ASSEMBLY__
891 /*
892  * WARNING: The C register and register group struct declarations are provided for
893  * convenience and illustrative purposes. They should, however, be used with
894  * caution as the C language standard provides no guarantees about the alignment or
895  * atomicity of device memory accesses. The recommended practice for coding device
896  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
897  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
898  * alt_write_dword() functions for 64 bit registers.
899  *
900  * The struct declaration for register ALT_WDT_WDT_CRR.
901  */
902 struct ALT_WDT_WDT_CRR_s
903 {
904  volatile uint32_t wdt_crr : 8; /* ALT_WDT_WDT_CRR_WDT_CRR */
905  uint32_t : 24; /* *UNDEFINED* */
906 };
907 
908 /* The typedef declaration for register ALT_WDT_WDT_CRR. */
909 typedef struct ALT_WDT_WDT_CRR_s ALT_WDT_WDT_CRR_t;
910 #endif /* __ASSEMBLY__ */
911 
912 /* The reset value of the ALT_WDT_WDT_CRR register. */
913 #define ALT_WDT_WDT_CRR_RESET 0x00000000
914 /* The byte offset of the ALT_WDT_WDT_CRR register from the beginning of the component. */
915 #define ALT_WDT_WDT_CRR_OFST 0xc
916 /* The address of the ALT_WDT_WDT_CRR register. */
917 #define ALT_WDT_WDT_CRR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_WDT_WDT_CRR_OFST))
918 
919 /*
920  * Register : Interrupt Status Register - WDT_STAT
921  *
922  * Interrupt Status Register.
923  *
924  * Register Layout
925  *
926  * Bits | Access | Reset | Description
927  * :-------|:-------|:------|:--------------------------
928  * [0] | R | 0x0 | ALT_WDT_WDT_STAT_WDT_STAT
929  * [31:1] | ??? | 0x0 | *UNDEFINED*
930  *
931  */
932 /*
933  * Field : wdt_stat
934  *
935  * This register shows the interrupt status of the WDT.
936  *
937  * 1 = Interrupt is active regardless of polarity.
938  *
939  * 0 = Interrupt is inactive.
940  *
941  * Field Enumeration Values:
942  *
943  * Enum | Value | Description
944  * :-------------------------------------|:------|:-------------------------------------------
945  * ALT_WDT_WDT_STAT_WDT_STAT_E_INACTIVE | 0x0 | Interrupt is inactive
946  * ALT_WDT_WDT_STAT_WDT_STAT_E_ACTIVE | 0x1 | Interrupt is active regardless of polarity
947  *
948  * Field Access Macros:
949  *
950  */
951 /*
952  * Enumerated value for register field ALT_WDT_WDT_STAT_WDT_STAT
953  *
954  * Interrupt is inactive
955  */
956 #define ALT_WDT_WDT_STAT_WDT_STAT_E_INACTIVE 0x0
957 /*
958  * Enumerated value for register field ALT_WDT_WDT_STAT_WDT_STAT
959  *
960  * Interrupt is active regardless of polarity
961  */
962 #define ALT_WDT_WDT_STAT_WDT_STAT_E_ACTIVE 0x1
963 
964 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_STAT_WDT_STAT register field. */
965 #define ALT_WDT_WDT_STAT_WDT_STAT_LSB 0
966 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_STAT_WDT_STAT register field. */
967 #define ALT_WDT_WDT_STAT_WDT_STAT_MSB 0
968 /* The width in bits of the ALT_WDT_WDT_STAT_WDT_STAT register field. */
969 #define ALT_WDT_WDT_STAT_WDT_STAT_WIDTH 1
970 /* The mask used to set the ALT_WDT_WDT_STAT_WDT_STAT register field value. */
971 #define ALT_WDT_WDT_STAT_WDT_STAT_SET_MSK 0x00000001
972 /* The mask used to clear the ALT_WDT_WDT_STAT_WDT_STAT register field value. */
973 #define ALT_WDT_WDT_STAT_WDT_STAT_CLR_MSK 0xfffffffe
974 /* The reset value of the ALT_WDT_WDT_STAT_WDT_STAT register field. */
975 #define ALT_WDT_WDT_STAT_WDT_STAT_RESET 0x0
976 /* Extracts the ALT_WDT_WDT_STAT_WDT_STAT field value from a register. */
977 #define ALT_WDT_WDT_STAT_WDT_STAT_GET(value) (((value) & 0x00000001) >> 0)
978 /* Produces a ALT_WDT_WDT_STAT_WDT_STAT register field value suitable for setting the register. */
979 #define ALT_WDT_WDT_STAT_WDT_STAT_SET(value) (((value) << 0) & 0x00000001)
980 
981 #ifndef __ASSEMBLY__
982 /*
983  * WARNING: The C register and register group struct declarations are provided for
984  * convenience and illustrative purposes. They should, however, be used with
985  * caution as the C language standard provides no guarantees about the alignment or
986  * atomicity of device memory accesses. The recommended practice for coding device
987  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
988  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
989  * alt_write_dword() functions for 64 bit registers.
990  *
991  * The struct declaration for register ALT_WDT_WDT_STAT.
992  */
993 struct ALT_WDT_WDT_STAT_s
994 {
995  const volatile uint32_t wdt_stat : 1; /* ALT_WDT_WDT_STAT_WDT_STAT */
996  uint32_t : 31; /* *UNDEFINED* */
997 };
998 
999 /* The typedef declaration for register ALT_WDT_WDT_STAT. */
1000 typedef struct ALT_WDT_WDT_STAT_s ALT_WDT_WDT_STAT_t;
1001 #endif /* __ASSEMBLY__ */
1002 
1003 /* The reset value of the ALT_WDT_WDT_STAT register. */
1004 #define ALT_WDT_WDT_STAT_RESET 0x00000000
1005 /* The byte offset of the ALT_WDT_WDT_STAT register from the beginning of the component. */
1006 #define ALT_WDT_WDT_STAT_OFST 0x10
1007 /* The address of the ALT_WDT_WDT_STAT register. */
1008 #define ALT_WDT_WDT_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_WDT_WDT_STAT_OFST))
1009 
1010 /*
1011  * Register : Interrupt Clear Register - WDT_EOI
1012  *
1013  * Interrupt Clear Register.
1014  *
1015  * Register Layout
1016  *
1017  * Bits | Access | Reset | Description
1018  * :-------|:-------|:------|:------------------------
1019  * [0] | R | 0x0 | ALT_WDT_WDT_EOI_WDT_EOI
1020  * [31:1] | ??? | 0x0 | *UNDEFINED*
1021  *
1022  */
1023 /*
1024  * Field : wdt_eoi
1025  *
1026  * Clears the watchdog interrupt. This can be used to clear the interrupt
1027  *
1028  * without restarting the watchdog counter.
1029  *
1030  * Field Access Macros:
1031  *
1032  */
1033 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_EOI_WDT_EOI register field. */
1034 #define ALT_WDT_WDT_EOI_WDT_EOI_LSB 0
1035 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_EOI_WDT_EOI register field. */
1036 #define ALT_WDT_WDT_EOI_WDT_EOI_MSB 0
1037 /* The width in bits of the ALT_WDT_WDT_EOI_WDT_EOI register field. */
1038 #define ALT_WDT_WDT_EOI_WDT_EOI_WIDTH 1
1039 /* The mask used to set the ALT_WDT_WDT_EOI_WDT_EOI register field value. */
1040 #define ALT_WDT_WDT_EOI_WDT_EOI_SET_MSK 0x00000001
1041 /* The mask used to clear the ALT_WDT_WDT_EOI_WDT_EOI register field value. */
1042 #define ALT_WDT_WDT_EOI_WDT_EOI_CLR_MSK 0xfffffffe
1043 /* The reset value of the ALT_WDT_WDT_EOI_WDT_EOI register field. */
1044 #define ALT_WDT_WDT_EOI_WDT_EOI_RESET 0x0
1045 /* Extracts the ALT_WDT_WDT_EOI_WDT_EOI field value from a register. */
1046 #define ALT_WDT_WDT_EOI_WDT_EOI_GET(value) (((value) & 0x00000001) >> 0)
1047 /* Produces a ALT_WDT_WDT_EOI_WDT_EOI register field value suitable for setting the register. */
1048 #define ALT_WDT_WDT_EOI_WDT_EOI_SET(value) (((value) << 0) & 0x00000001)
1049 
1050 #ifndef __ASSEMBLY__
1051 /*
1052  * WARNING: The C register and register group struct declarations are provided for
1053  * convenience and illustrative purposes. They should, however, be used with
1054  * caution as the C language standard provides no guarantees about the alignment or
1055  * atomicity of device memory accesses. The recommended practice for coding device
1056  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1057  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1058  * alt_write_dword() functions for 64 bit registers.
1059  *
1060  * The struct declaration for register ALT_WDT_WDT_EOI.
1061  */
1062 struct ALT_WDT_WDT_EOI_s
1063 {
1064  const volatile uint32_t wdt_eoi : 1; /* ALT_WDT_WDT_EOI_WDT_EOI */
1065  uint32_t : 31; /* *UNDEFINED* */
1066 };
1067 
1068 /* The typedef declaration for register ALT_WDT_WDT_EOI. */
1069 typedef struct ALT_WDT_WDT_EOI_s ALT_WDT_WDT_EOI_t;
1070 #endif /* __ASSEMBLY__ */
1071 
1072 /* The reset value of the ALT_WDT_WDT_EOI register. */
1073 #define ALT_WDT_WDT_EOI_RESET 0x00000000
1074 /* The byte offset of the ALT_WDT_WDT_EOI register from the beginning of the component. */
1075 #define ALT_WDT_WDT_EOI_OFST 0x14
1076 /* The address of the ALT_WDT_WDT_EOI register. */
1077 #define ALT_WDT_WDT_EOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_WDT_WDT_EOI_OFST))
1078 
1079 /*
1080  * Register : Component Parameters Register 5 - WDT_COMP_PARAM_5
1081  *
1082  * Component Parameters Register 5
1083  *
1084  * Register Layout
1085  *
1086  * Bits | Access | Reset | Description
1087  * :-------|:-------|:------|:------------
1088  * [31:0] | RW | 0x0 | Empty
1089  *
1090  */
1091 /*
1092  * Field : Empty - fld
1093  *
1094  * Placeholder
1095  *
1096  * Field Access Macros:
1097  *
1098  */
1099 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_COMP_PARAM_5_FLD register field. */
1100 #define ALT_WDT_WDT_COMP_PARAM_5_FLD_LSB 0
1101 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_COMP_PARAM_5_FLD register field. */
1102 #define ALT_WDT_WDT_COMP_PARAM_5_FLD_MSB 31
1103 /* The width in bits of the ALT_WDT_WDT_COMP_PARAM_5_FLD register field. */
1104 #define ALT_WDT_WDT_COMP_PARAM_5_FLD_WIDTH 32
1105 /* The mask used to set the ALT_WDT_WDT_COMP_PARAM_5_FLD register field value. */
1106 #define ALT_WDT_WDT_COMP_PARAM_5_FLD_SET_MSK 0xffffffff
1107 /* The mask used to clear the ALT_WDT_WDT_COMP_PARAM_5_FLD register field value. */
1108 #define ALT_WDT_WDT_COMP_PARAM_5_FLD_CLR_MSK 0x00000000
1109 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_5_FLD register field. */
1110 #define ALT_WDT_WDT_COMP_PARAM_5_FLD_RESET 0x0
1111 /* Extracts the ALT_WDT_WDT_COMP_PARAM_5_FLD field value from a register. */
1112 #define ALT_WDT_WDT_COMP_PARAM_5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1113 /* Produces a ALT_WDT_WDT_COMP_PARAM_5_FLD register field value suitable for setting the register. */
1114 #define ALT_WDT_WDT_COMP_PARAM_5_FLD_SET(value) (((value) << 0) & 0xffffffff)
1115 
1116 #ifndef __ASSEMBLY__
1117 /*
1118  * WARNING: The C register and register group struct declarations are provided for
1119  * convenience and illustrative purposes. They should, however, be used with
1120  * caution as the C language standard provides no guarantees about the alignment or
1121  * atomicity of device memory accesses. The recommended practice for coding device
1122  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1123  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1124  * alt_write_dword() functions for 64 bit registers.
1125  *
1126  * The struct declaration for register ALT_WDT_WDT_COMP_PARAM_5.
1127  */
1128 struct ALT_WDT_WDT_COMP_PARAM_5_s
1129 {
1130  volatile uint32_t fld : 32; /* Empty */
1131 };
1132 
1133 /* The typedef declaration for register ALT_WDT_WDT_COMP_PARAM_5. */
1134 typedef struct ALT_WDT_WDT_COMP_PARAM_5_s ALT_WDT_WDT_COMP_PARAM_5_t;
1135 #endif /* __ASSEMBLY__ */
1136 
1137 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_5 register. */
1138 #define ALT_WDT_WDT_COMP_PARAM_5_RESET 0x00000000
1139 /* The byte offset of the ALT_WDT_WDT_COMP_PARAM_5 register from the beginning of the component. */
1140 #define ALT_WDT_WDT_COMP_PARAM_5_OFST 0xe4
1141 /* The address of the ALT_WDT_WDT_COMP_PARAM_5 register. */
1142 #define ALT_WDT_WDT_COMP_PARAM_5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_WDT_WDT_COMP_PARAM_5_OFST))
1143 
1144 /*
1145  * Register : Component Parameters Register 4 - WDT_COMP_PARAM_4
1146  *
1147  * Component Parameters Register 4
1148  *
1149  * Register Layout
1150  *
1151  * Bits | Access | Reset | Description
1152  * :-------|:-------|:------|:------------
1153  * [31:0] | RW | 0x0 | Empty
1154  *
1155  */
1156 /*
1157  * Field : Empty - fld
1158  *
1159  * Placeholder
1160  *
1161  * Field Access Macros:
1162  *
1163  */
1164 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_COMP_PARAM_4_FLD register field. */
1165 #define ALT_WDT_WDT_COMP_PARAM_4_FLD_LSB 0
1166 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_COMP_PARAM_4_FLD register field. */
1167 #define ALT_WDT_WDT_COMP_PARAM_4_FLD_MSB 31
1168 /* The width in bits of the ALT_WDT_WDT_COMP_PARAM_4_FLD register field. */
1169 #define ALT_WDT_WDT_COMP_PARAM_4_FLD_WIDTH 32
1170 /* The mask used to set the ALT_WDT_WDT_COMP_PARAM_4_FLD register field value. */
1171 #define ALT_WDT_WDT_COMP_PARAM_4_FLD_SET_MSK 0xffffffff
1172 /* The mask used to clear the ALT_WDT_WDT_COMP_PARAM_4_FLD register field value. */
1173 #define ALT_WDT_WDT_COMP_PARAM_4_FLD_CLR_MSK 0x00000000
1174 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_4_FLD register field. */
1175 #define ALT_WDT_WDT_COMP_PARAM_4_FLD_RESET 0x0
1176 /* Extracts the ALT_WDT_WDT_COMP_PARAM_4_FLD field value from a register. */
1177 #define ALT_WDT_WDT_COMP_PARAM_4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1178 /* Produces a ALT_WDT_WDT_COMP_PARAM_4_FLD register field value suitable for setting the register. */
1179 #define ALT_WDT_WDT_COMP_PARAM_4_FLD_SET(value) (((value) << 0) & 0xffffffff)
1180 
1181 #ifndef __ASSEMBLY__
1182 /*
1183  * WARNING: The C register and register group struct declarations are provided for
1184  * convenience and illustrative purposes. They should, however, be used with
1185  * caution as the C language standard provides no guarantees about the alignment or
1186  * atomicity of device memory accesses. The recommended practice for coding device
1187  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1188  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1189  * alt_write_dword() functions for 64 bit registers.
1190  *
1191  * The struct declaration for register ALT_WDT_WDT_COMP_PARAM_4.
1192  */
1193 struct ALT_WDT_WDT_COMP_PARAM_4_s
1194 {
1195  volatile uint32_t fld : 32; /* Empty */
1196 };
1197 
1198 /* The typedef declaration for register ALT_WDT_WDT_COMP_PARAM_4. */
1199 typedef struct ALT_WDT_WDT_COMP_PARAM_4_s ALT_WDT_WDT_COMP_PARAM_4_t;
1200 #endif /* __ASSEMBLY__ */
1201 
1202 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_4 register. */
1203 #define ALT_WDT_WDT_COMP_PARAM_4_RESET 0x00000000
1204 /* The byte offset of the ALT_WDT_WDT_COMP_PARAM_4 register from the beginning of the component. */
1205 #define ALT_WDT_WDT_COMP_PARAM_4_OFST 0xe8
1206 /* The address of the ALT_WDT_WDT_COMP_PARAM_4 register. */
1207 #define ALT_WDT_WDT_COMP_PARAM_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_WDT_WDT_COMP_PARAM_4_OFST))
1208 
1209 /*
1210  * Register : Component Parameters Register 3 - WDT_COMP_PARAM_3
1211  *
1212  * Component Parameters Register 3
1213  *
1214  * Register Layout
1215  *
1216  * Bits | Access | Reset | Description
1217  * :-------|:-------|:------|:------------
1218  * [31:0] | RW | 0xff | Empty
1219  *
1220  */
1221 /*
1222  * Field : Empty - fld
1223  *
1224  * Placeholder
1225  *
1226  * Field Access Macros:
1227  *
1228  */
1229 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_COMP_PARAM_3_FLD register field. */
1230 #define ALT_WDT_WDT_COMP_PARAM_3_FLD_LSB 0
1231 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_COMP_PARAM_3_FLD register field. */
1232 #define ALT_WDT_WDT_COMP_PARAM_3_FLD_MSB 31
1233 /* The width in bits of the ALT_WDT_WDT_COMP_PARAM_3_FLD register field. */
1234 #define ALT_WDT_WDT_COMP_PARAM_3_FLD_WIDTH 32
1235 /* The mask used to set the ALT_WDT_WDT_COMP_PARAM_3_FLD register field value. */
1236 #define ALT_WDT_WDT_COMP_PARAM_3_FLD_SET_MSK 0xffffffff
1237 /* The mask used to clear the ALT_WDT_WDT_COMP_PARAM_3_FLD register field value. */
1238 #define ALT_WDT_WDT_COMP_PARAM_3_FLD_CLR_MSK 0x00000000
1239 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_3_FLD register field. */
1240 #define ALT_WDT_WDT_COMP_PARAM_3_FLD_RESET 0xff
1241 /* Extracts the ALT_WDT_WDT_COMP_PARAM_3_FLD field value from a register. */
1242 #define ALT_WDT_WDT_COMP_PARAM_3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1243 /* Produces a ALT_WDT_WDT_COMP_PARAM_3_FLD register field value suitable for setting the register. */
1244 #define ALT_WDT_WDT_COMP_PARAM_3_FLD_SET(value) (((value) << 0) & 0xffffffff)
1245 
1246 #ifndef __ASSEMBLY__
1247 /*
1248  * WARNING: The C register and register group struct declarations are provided for
1249  * convenience and illustrative purposes. They should, however, be used with
1250  * caution as the C language standard provides no guarantees about the alignment or
1251  * atomicity of device memory accesses. The recommended practice for coding device
1252  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1253  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1254  * alt_write_dword() functions for 64 bit registers.
1255  *
1256  * The struct declaration for register ALT_WDT_WDT_COMP_PARAM_3.
1257  */
1258 struct ALT_WDT_WDT_COMP_PARAM_3_s
1259 {
1260  volatile uint32_t fld : 32; /* Empty */
1261 };
1262 
1263 /* The typedef declaration for register ALT_WDT_WDT_COMP_PARAM_3. */
1264 typedef struct ALT_WDT_WDT_COMP_PARAM_3_s ALT_WDT_WDT_COMP_PARAM_3_t;
1265 #endif /* __ASSEMBLY__ */
1266 
1267 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_3 register. */
1268 #define ALT_WDT_WDT_COMP_PARAM_3_RESET 0x000000ff
1269 /* The byte offset of the ALT_WDT_WDT_COMP_PARAM_3 register from the beginning of the component. */
1270 #define ALT_WDT_WDT_COMP_PARAM_3_OFST 0xec
1271 /* The address of the ALT_WDT_WDT_COMP_PARAM_3 register. */
1272 #define ALT_WDT_WDT_COMP_PARAM_3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_WDT_WDT_COMP_PARAM_3_OFST))
1273 
1274 /*
1275  * Register : Component Parameters Register 2 - WDT_COMP_PARAM_2
1276  *
1277  * Component Parameters Register 2
1278  *
1279  * Register Layout
1280  *
1281  * Bits | Access | Reset | Description
1282  * :-------|:-------|:-----------|:------------
1283  * [31:0] | RW | 0x7fffffff | Empty
1284  *
1285  */
1286 /*
1287  * Field : Empty - fld
1288  *
1289  * Placeholder
1290  *
1291  * Field Access Macros:
1292  *
1293  */
1294 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_COMP_PARAM_2_FLD register field. */
1295 #define ALT_WDT_WDT_COMP_PARAM_2_FLD_LSB 0
1296 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_COMP_PARAM_2_FLD register field. */
1297 #define ALT_WDT_WDT_COMP_PARAM_2_FLD_MSB 31
1298 /* The width in bits of the ALT_WDT_WDT_COMP_PARAM_2_FLD register field. */
1299 #define ALT_WDT_WDT_COMP_PARAM_2_FLD_WIDTH 32
1300 /* The mask used to set the ALT_WDT_WDT_COMP_PARAM_2_FLD register field value. */
1301 #define ALT_WDT_WDT_COMP_PARAM_2_FLD_SET_MSK 0xffffffff
1302 /* The mask used to clear the ALT_WDT_WDT_COMP_PARAM_2_FLD register field value. */
1303 #define ALT_WDT_WDT_COMP_PARAM_2_FLD_CLR_MSK 0x00000000
1304 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_2_FLD register field. */
1305 #define ALT_WDT_WDT_COMP_PARAM_2_FLD_RESET 0x7fffffff
1306 /* Extracts the ALT_WDT_WDT_COMP_PARAM_2_FLD field value from a register. */
1307 #define ALT_WDT_WDT_COMP_PARAM_2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1308 /* Produces a ALT_WDT_WDT_COMP_PARAM_2_FLD register field value suitable for setting the register. */
1309 #define ALT_WDT_WDT_COMP_PARAM_2_FLD_SET(value) (((value) << 0) & 0xffffffff)
1310 
1311 #ifndef __ASSEMBLY__
1312 /*
1313  * WARNING: The C register and register group struct declarations are provided for
1314  * convenience and illustrative purposes. They should, however, be used with
1315  * caution as the C language standard provides no guarantees about the alignment or
1316  * atomicity of device memory accesses. The recommended practice for coding device
1317  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1318  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1319  * alt_write_dword() functions for 64 bit registers.
1320  *
1321  * The struct declaration for register ALT_WDT_WDT_COMP_PARAM_2.
1322  */
1323 struct ALT_WDT_WDT_COMP_PARAM_2_s
1324 {
1325  volatile uint32_t fld : 32; /* Empty */
1326 };
1327 
1328 /* The typedef declaration for register ALT_WDT_WDT_COMP_PARAM_2. */
1329 typedef struct ALT_WDT_WDT_COMP_PARAM_2_s ALT_WDT_WDT_COMP_PARAM_2_t;
1330 #endif /* __ASSEMBLY__ */
1331 
1332 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_2 register. */
1333 #define ALT_WDT_WDT_COMP_PARAM_2_RESET 0x7fffffff
1334 /* The byte offset of the ALT_WDT_WDT_COMP_PARAM_2 register from the beginning of the component. */
1335 #define ALT_WDT_WDT_COMP_PARAM_2_OFST 0xf0
1336 /* The address of the ALT_WDT_WDT_COMP_PARAM_2 register. */
1337 #define ALT_WDT_WDT_COMP_PARAM_2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_WDT_WDT_COMP_PARAM_2_OFST))
1338 
1339 /*
1340  * Register : Component Parameters Register 1 - WDT_COMP_PARAM_1
1341  *
1342  * Component Parameters Register 1
1343  *
1344  * Register Layout
1345  *
1346  * Bits | Access | Reset | Description
1347  * :--------|:-------|:------|:-------------------------------------------
1348  * [0] | R | 0x0 | ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN
1349  * [1] | R | 0x0 | ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD
1350  * [2] | R | 0x1 | ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP
1351  * [3] | R | 0x0 | ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD
1352  * [4] | R | 0x0 | ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL
1353  * [5] | R | 0x0 | ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP
1354  * [6] | R | 0x1 | ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP
1355  * [7] | R | 0x0 | ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE
1356  * [9:8] | R | 0x2 | ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH
1357  * [12:10] | R | 0x4 | ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL
1358  * [15:13] | R | 0x0 | ALT_WDT_WDT_COMP_PARAM_1_RSVD_15_13
1359  * [19:16] | R | 0xf | ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP
1360  * [23:20] | R | 0xf | ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT
1361  * [28:24] | R | 0x10 | ALT_WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH
1362  * [31:29] | R | 0x0 | ALT_WDT_WDT_COMP_PARAM_1_RSVD_31_29
1363  *
1364  */
1365 /*
1366  * Field : WDT_ALWAYS_EN
1367  *
1368  * Field Enumeration Values:
1369  *
1370  * Enum | Value | Description
1371  * :--------------------------------------------------|:------|:---------------------------------
1372  * ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN_E_DISABLED | 0x0 | Watchdog timer disabled on reset
1373  * ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN_E_ENABLED | 0x1 | Watchdog timer enabled on reset
1374  *
1375  * Field Access Macros:
1376  *
1377  */
1378 /*
1379  * Enumerated value for register field ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN
1380  *
1381  * Watchdog timer disabled on reset
1382  */
1383 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN_E_DISABLED 0x0
1384 /*
1385  * Enumerated value for register field ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN
1386  *
1387  * Watchdog timer enabled on reset
1388  */
1389 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN_E_ENABLED 0x1
1390 
1391 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN register field. */
1392 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN_LSB 0
1393 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN register field. */
1394 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN_MSB 0
1395 /* The width in bits of the ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN register field. */
1396 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN_WIDTH 1
1397 /* The mask used to set the ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN register field value. */
1398 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN_SET_MSK 0x00000001
1399 /* The mask used to clear the ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN register field value. */
1400 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN_CLR_MSK 0xfffffffe
1401 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN register field. */
1402 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN_RESET 0x0
1403 /* Extracts the ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN field value from a register. */
1404 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN_GET(value) (((value) & 0x00000001) >> 0)
1405 /* Produces a ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN register field value suitable for setting the register. */
1406 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN_SET(value) (((value) << 0) & 0x00000001)
1407 
1408 /*
1409  * Field : WDT_DFLT_RMOD
1410  *
1411  * Field Enumeration Values:
1412  *
1413  * Enum | Value | Description
1414  * :--------------------------------------------------|:------|:---------------------------
1415  * ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD_E_DISABLED | 0x0 | System reset only
1416  * ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD_E_ENABLED | 0x1 | Interrupt and system reset
1417  *
1418  * Field Access Macros:
1419  *
1420  */
1421 /*
1422  * Enumerated value for register field ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD
1423  *
1424  * System reset only
1425  */
1426 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD_E_DISABLED 0x0
1427 /*
1428  * Enumerated value for register field ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD
1429  *
1430  * Interrupt and system reset
1431  */
1432 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD_E_ENABLED 0x1
1433 
1434 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD register field. */
1435 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD_LSB 1
1436 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD register field. */
1437 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD_MSB 1
1438 /* The width in bits of the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD register field. */
1439 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD_WIDTH 1
1440 /* The mask used to set the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD register field value. */
1441 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD_SET_MSK 0x00000002
1442 /* The mask used to clear the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD register field value. */
1443 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD_CLR_MSK 0xfffffffd
1444 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD register field. */
1445 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD_RESET 0x0
1446 /* Extracts the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD field value from a register. */
1447 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD_GET(value) (((value) & 0x00000002) >> 1)
1448 /* Produces a ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD register field value suitable for setting the register. */
1449 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD_SET(value) (((value) << 1) & 0x00000002)
1450 
1451 /*
1452  * Field : WDT_DUAL_TOP
1453  *
1454  * Field Enumeration Values:
1455  *
1456  * Enum | Value | Description
1457  * :-------------------------------------------------|:------|:-------------------------------------
1458  * ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP_E_DISABLED | 0x0 | Second timeout period is not present
1459  * ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP_E_ENABLED | 0x1 | Second timeout period is present
1460  *
1461  * Field Access Macros:
1462  *
1463  */
1464 /*
1465  * Enumerated value for register field ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP
1466  *
1467  * Second timeout period is not present
1468  */
1469 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP_E_DISABLED 0x0
1470 /*
1471  * Enumerated value for register field ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP
1472  *
1473  * Second timeout period is present
1474  */
1475 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP_E_ENABLED 0x1
1476 
1477 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP register field. */
1478 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP_LSB 2
1479 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP register field. */
1480 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP_MSB 2
1481 /* The width in bits of the ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP register field. */
1482 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP_WIDTH 1
1483 /* The mask used to set the ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP register field value. */
1484 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP_SET_MSK 0x00000004
1485 /* The mask used to clear the ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP register field value. */
1486 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP_CLR_MSK 0xfffffffb
1487 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP register field. */
1488 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP_RESET 0x1
1489 /* Extracts the ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP field value from a register. */
1490 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP_GET(value) (((value) & 0x00000004) >> 2)
1491 /* Produces a ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP register field value suitable for setting the register. */
1492 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP_SET(value) (((value) << 2) & 0x00000004)
1493 
1494 /*
1495  * Field : WDT_HC_RMOD
1496  *
1497  * Field Enumeration Values:
1498  *
1499  * Enum | Value | Description
1500  * :----------------------------------------------------|:------|:-------------------------------------
1501  * ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD_E_PROGRAMMABLE | 0x0 | Output response mode is programmable
1502  * ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD_E_HARDCODED | 0x1 | Output response mode is hard coded
1503  *
1504  * Field Access Macros:
1505  *
1506  */
1507 /*
1508  * Enumerated value for register field ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD
1509  *
1510  * Output response mode is programmable
1511  */
1512 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD_E_PROGRAMMABLE 0x0
1513 /*
1514  * Enumerated value for register field ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD
1515  *
1516  * Output response mode is hard coded
1517  */
1518 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD_E_HARDCODED 0x1
1519 
1520 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD register field. */
1521 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD_LSB 3
1522 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD register field. */
1523 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD_MSB 3
1524 /* The width in bits of the ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD register field. */
1525 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD_WIDTH 1
1526 /* The mask used to set the ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD register field value. */
1527 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD_SET_MSK 0x00000008
1528 /* The mask used to clear the ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD register field value. */
1529 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD_CLR_MSK 0xfffffff7
1530 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD register field. */
1531 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD_RESET 0x0
1532 /* Extracts the ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD field value from a register. */
1533 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD_GET(value) (((value) & 0x00000008) >> 3)
1534 /* Produces a ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD register field value suitable for setting the register. */
1535 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD_SET(value) (((value) << 3) & 0x00000008)
1536 
1537 /*
1538  * Field : WDT_HC_RPL
1539  *
1540  * Field Enumeration Values:
1541  *
1542  * Enum | Value | Description
1543  * :---------------------------------------------------|:------|:-----------------------------------
1544  * ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL_E_PROGRAMMABLE | 0x0 | Reset pulse length is programmable
1545  * ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL_E_HARDCODED | 0x1 | Reset pulse length is hardcoded
1546  *
1547  * Field Access Macros:
1548  *
1549  */
1550 /*
1551  * Enumerated value for register field ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL
1552  *
1553  * Reset pulse length is programmable
1554  */
1555 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL_E_PROGRAMMABLE 0x0
1556 /*
1557  * Enumerated value for register field ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL
1558  *
1559  * Reset pulse length is hardcoded
1560  */
1561 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL_E_HARDCODED 0x1
1562 
1563 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL register field. */
1564 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL_LSB 4
1565 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL register field. */
1566 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL_MSB 4
1567 /* The width in bits of the ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL register field. */
1568 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL_WIDTH 1
1569 /* The mask used to set the ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL register field value. */
1570 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL_SET_MSK 0x00000010
1571 /* The mask used to clear the ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL register field value. */
1572 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL_CLR_MSK 0xffffffef
1573 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL register field. */
1574 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL_RESET 0x0
1575 /* Extracts the ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL field value from a register. */
1576 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL_GET(value) (((value) & 0x00000010) >> 4)
1577 /* Produces a ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL register field value suitable for setting the register. */
1578 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL_SET(value) (((value) << 4) & 0x00000010)
1579 
1580 /*
1581  * Field : WDT_HC_TOP
1582  *
1583  * Field Enumeration Values:
1584  *
1585  * Enum | Value | Description
1586  * :---------------------------------------------------|:------|:-------------------------------
1587  * ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP_E_PROGRAMMABLE | 0x0 | Timeout period is programmable
1588  * ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP_E_HARDCODED | 0x1 | Timeout period is hard coded
1589  *
1590  * Field Access Macros:
1591  *
1592  */
1593 /*
1594  * Enumerated value for register field ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP
1595  *
1596  * Timeout period is programmable
1597  */
1598 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP_E_PROGRAMMABLE 0x0
1599 /*
1600  * Enumerated value for register field ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP
1601  *
1602  * Timeout period is hard coded
1603  */
1604 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP_E_HARDCODED 0x1
1605 
1606 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP register field. */
1607 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP_LSB 5
1608 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP register field. */
1609 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP_MSB 5
1610 /* The width in bits of the ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP register field. */
1611 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP_WIDTH 1
1612 /* The mask used to set the ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP register field value. */
1613 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP_SET_MSK 0x00000020
1614 /* The mask used to clear the ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP register field value. */
1615 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP_CLR_MSK 0xffffffdf
1616 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP register field. */
1617 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP_RESET 0x0
1618 /* Extracts the ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP field value from a register. */
1619 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP_GET(value) (((value) & 0x00000020) >> 5)
1620 /* Produces a ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP register field value suitable for setting the register. */
1621 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP_SET(value) (((value) << 5) & 0x00000020)
1622 
1623 /*
1624  * Field : WDT_USE_FIX_TOP
1625  *
1626  * Field Enumeration Values:
1627  *
1628  * Enum | Value | Description
1629  * :-------------------------------------------------------|:------|:--------------------------------
1630  * ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP_E_USERDEFINED | 0x0 | User must define timeout values
1631  * ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP_E_PREDEFINED | 0x1 | Use predefined timeout values
1632  *
1633  * Field Access Macros:
1634  *
1635  */
1636 /*
1637  * Enumerated value for register field ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP
1638  *
1639  * User must define timeout values
1640  */
1641 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP_E_USERDEFINED 0x0
1642 /*
1643  * Enumerated value for register field ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP
1644  *
1645  * Use predefined timeout values
1646  */
1647 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP_E_PREDEFINED 0x1
1648 
1649 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP register field. */
1650 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP_LSB 6
1651 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP register field. */
1652 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP_MSB 6
1653 /* The width in bits of the ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP register field. */
1654 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP_WIDTH 1
1655 /* The mask used to set the ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP register field value. */
1656 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP_SET_MSK 0x00000040
1657 /* The mask used to clear the ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP register field value. */
1658 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP_CLR_MSK 0xffffffbf
1659 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP register field. */
1660 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP_RESET 0x1
1661 /* Extracts the ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP field value from a register. */
1662 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP_GET(value) (((value) & 0x00000040) >> 6)
1663 /* Produces a ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP register field value suitable for setting the register. */
1664 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP_SET(value) (((value) << 6) & 0x00000040)
1665 
1666 /*
1667  * Field : WDT_PAUSE
1668  *
1669  * Field Enumeration Values:
1670  *
1671  * Enum | Value | Description
1672  * :----------------------------------------------|:------|:------------------------------------
1673  * ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE_E_DISABLED | 0x0 | Pause enable signal is non existent
1674  * ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE_E_ENABLED | 0x1 | Pause enable signal is included
1675  *
1676  * Field Access Macros:
1677  *
1678  */
1679 /*
1680  * Enumerated value for register field ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE
1681  *
1682  * Pause enable signal is non existent
1683  */
1684 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE_E_DISABLED 0x0
1685 /*
1686  * Enumerated value for register field ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE
1687  *
1688  * Pause enable signal is included
1689  */
1690 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE_E_ENABLED 0x1
1691 
1692 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE register field. */
1693 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE_LSB 7
1694 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE register field. */
1695 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE_MSB 7
1696 /* The width in bits of the ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE register field. */
1697 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE_WIDTH 1
1698 /* The mask used to set the ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE register field value. */
1699 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE_SET_MSK 0x00000080
1700 /* The mask used to clear the ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE register field value. */
1701 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE_CLR_MSK 0xffffff7f
1702 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE register field. */
1703 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE_RESET 0x0
1704 /* Extracts the ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE field value from a register. */
1705 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE_GET(value) (((value) & 0x00000080) >> 7)
1706 /* Produces a ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE register field value suitable for setting the register. */
1707 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE_SET(value) (((value) << 7) & 0x00000080)
1708 
1709 /*
1710  * Field : APB_DATA_WIDTH
1711  *
1712  * Field Enumeration Values:
1713  *
1714  * Enum | Value | Description
1715  * :-----------------------------------------------------|:------|:--------------------------
1716  * ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH_E_APB_8BITS | 0x0 | APB data width is 8 bits
1717  * ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH_E_APB_16BITS | 0x1 | APB data width is 16 bits
1718  * ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH_E_APB_32BITS | 0x2 | APB data width is 32 bits
1719  *
1720  * Field Access Macros:
1721  *
1722  */
1723 /*
1724  * Enumerated value for register field ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH
1725  *
1726  * APB data width is 8 bits
1727  */
1728 #define ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH_E_APB_8BITS 0x0
1729 /*
1730  * Enumerated value for register field ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH
1731  *
1732  * APB data width is 16 bits
1733  */
1734 #define ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH_E_APB_16BITS 0x1
1735 /*
1736  * Enumerated value for register field ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH
1737  *
1738  * APB data width is 32 bits
1739  */
1740 #define ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH_E_APB_32BITS 0x2
1741 
1742 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH register field. */
1743 #define ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH_LSB 8
1744 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH register field. */
1745 #define ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH_MSB 9
1746 /* The width in bits of the ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH register field. */
1747 #define ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH_WIDTH 2
1748 /* The mask used to set the ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH register field value. */
1749 #define ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH_SET_MSK 0x00000300
1750 /* The mask used to clear the ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH register field value. */
1751 #define ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH_CLR_MSK 0xfffffcff
1752 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH register field. */
1753 #define ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH_RESET 0x2
1754 /* Extracts the ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH field value from a register. */
1755 #define ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000300) >> 8)
1756 /* Produces a ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH register field value suitable for setting the register. */
1757 #define ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH_SET(value) (((value) << 8) & 0x00000300)
1758 
1759 /*
1760  * Field : WDT_DFLT_RPL
1761  *
1762  * Field Access Macros:
1763  *
1764  */
1765 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL register field. */
1766 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL_LSB 10
1767 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL register field. */
1768 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL_MSB 12
1769 /* The width in bits of the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL register field. */
1770 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL_WIDTH 3
1771 /* The mask used to set the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL register field value. */
1772 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL_SET_MSK 0x00001c00
1773 /* The mask used to clear the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL register field value. */
1774 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL_CLR_MSK 0xffffe3ff
1775 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL register field. */
1776 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL_RESET 0x4
1777 /* Extracts the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL field value from a register. */
1778 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL_GET(value) (((value) & 0x00001c00) >> 10)
1779 /* Produces a ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL register field value suitable for setting the register. */
1780 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL_SET(value) (((value) << 10) & 0x00001c00)
1781 
1782 /*
1783  * Field : RSVD_15_13
1784  *
1785  * Field Access Macros:
1786  *
1787  */
1788 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_COMP_PARAM_1_RSVD_15_13 register field. */
1789 #define ALT_WDT_WDT_COMP_PARAM_1_RSVD_15_13_LSB 13
1790 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_COMP_PARAM_1_RSVD_15_13 register field. */
1791 #define ALT_WDT_WDT_COMP_PARAM_1_RSVD_15_13_MSB 15
1792 /* The width in bits of the ALT_WDT_WDT_COMP_PARAM_1_RSVD_15_13 register field. */
1793 #define ALT_WDT_WDT_COMP_PARAM_1_RSVD_15_13_WIDTH 3
1794 /* The mask used to set the ALT_WDT_WDT_COMP_PARAM_1_RSVD_15_13 register field value. */
1795 #define ALT_WDT_WDT_COMP_PARAM_1_RSVD_15_13_SET_MSK 0x0000e000
1796 /* The mask used to clear the ALT_WDT_WDT_COMP_PARAM_1_RSVD_15_13 register field value. */
1797 #define ALT_WDT_WDT_COMP_PARAM_1_RSVD_15_13_CLR_MSK 0xffff1fff
1798 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_1_RSVD_15_13 register field. */
1799 #define ALT_WDT_WDT_COMP_PARAM_1_RSVD_15_13_RESET 0x0
1800 /* Extracts the ALT_WDT_WDT_COMP_PARAM_1_RSVD_15_13 field value from a register. */
1801 #define ALT_WDT_WDT_COMP_PARAM_1_RSVD_15_13_GET(value) (((value) & 0x0000e000) >> 13)
1802 /* Produces a ALT_WDT_WDT_COMP_PARAM_1_RSVD_15_13 register field value suitable for setting the register. */
1803 #define ALT_WDT_WDT_COMP_PARAM_1_RSVD_15_13_SET(value) (((value) << 13) & 0x0000e000)
1804 
1805 /*
1806  * Field : WDT_DFLT_TOP
1807  *
1808  * Field Access Macros:
1809  *
1810  */
1811 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP register field. */
1812 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_LSB 16
1813 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP register field. */
1814 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_MSB 19
1815 /* The width in bits of the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP register field. */
1816 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_WIDTH 4
1817 /* The mask used to set the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP register field value. */
1818 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_SET_MSK 0x000f0000
1819 /* The mask used to clear the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP register field value. */
1820 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_CLR_MSK 0xfff0ffff
1821 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP register field. */
1822 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_RESET 0xf
1823 /* Extracts the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP field value from a register. */
1824 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_GET(value) (((value) & 0x000f0000) >> 16)
1825 /* Produces a ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP register field value suitable for setting the register. */
1826 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_SET(value) (((value) << 16) & 0x000f0000)
1827 
1828 /*
1829  * Field : WDT_DFLT_TOP_INIT
1830  *
1831  * Field Access Macros:
1832  *
1833  */
1834 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT register field. */
1835 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT_LSB 20
1836 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT register field. */
1837 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT_MSB 23
1838 /* The width in bits of the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT register field. */
1839 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT_WIDTH 4
1840 /* The mask used to set the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT register field value. */
1841 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT_SET_MSK 0x00f00000
1842 /* The mask used to clear the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT register field value. */
1843 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT_CLR_MSK 0xff0fffff
1844 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT register field. */
1845 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT_RESET 0xf
1846 /* Extracts the ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT field value from a register. */
1847 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT_GET(value) (((value) & 0x00f00000) >> 20)
1848 /* Produces a ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT register field value suitable for setting the register. */
1849 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT_SET(value) (((value) << 20) & 0x00f00000)
1850 
1851 /*
1852  * Field : WDT_CNT_WIDTH
1853  *
1854  * Field Access Macros:
1855  *
1856  */
1857 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH register field. */
1858 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH_LSB 24
1859 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH register field. */
1860 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH_MSB 28
1861 /* The width in bits of the ALT_WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH register field. */
1862 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH_WIDTH 5
1863 /* The mask used to set the ALT_WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH register field value. */
1864 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH_SET_MSK 0x1f000000
1865 /* The mask used to clear the ALT_WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH register field value. */
1866 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH_CLR_MSK 0xe0ffffff
1867 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH register field. */
1868 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH_RESET 0x10
1869 /* Extracts the ALT_WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH field value from a register. */
1870 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH_GET(value) (((value) & 0x1f000000) >> 24)
1871 /* Produces a ALT_WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH register field value suitable for setting the register. */
1872 #define ALT_WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH_SET(value) (((value) << 24) & 0x1f000000)
1873 
1874 /*
1875  * Field : RSVD_31_29
1876  *
1877  * Field Access Macros:
1878  *
1879  */
1880 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_COMP_PARAM_1_RSVD_31_29 register field. */
1881 #define ALT_WDT_WDT_COMP_PARAM_1_RSVD_31_29_LSB 29
1882 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_COMP_PARAM_1_RSVD_31_29 register field. */
1883 #define ALT_WDT_WDT_COMP_PARAM_1_RSVD_31_29_MSB 31
1884 /* The width in bits of the ALT_WDT_WDT_COMP_PARAM_1_RSVD_31_29 register field. */
1885 #define ALT_WDT_WDT_COMP_PARAM_1_RSVD_31_29_WIDTH 3
1886 /* The mask used to set the ALT_WDT_WDT_COMP_PARAM_1_RSVD_31_29 register field value. */
1887 #define ALT_WDT_WDT_COMP_PARAM_1_RSVD_31_29_SET_MSK 0xe0000000
1888 /* The mask used to clear the ALT_WDT_WDT_COMP_PARAM_1_RSVD_31_29 register field value. */
1889 #define ALT_WDT_WDT_COMP_PARAM_1_RSVD_31_29_CLR_MSK 0x1fffffff
1890 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_1_RSVD_31_29 register field. */
1891 #define ALT_WDT_WDT_COMP_PARAM_1_RSVD_31_29_RESET 0x0
1892 /* Extracts the ALT_WDT_WDT_COMP_PARAM_1_RSVD_31_29 field value from a register. */
1893 #define ALT_WDT_WDT_COMP_PARAM_1_RSVD_31_29_GET(value) (((value) & 0xe0000000) >> 29)
1894 /* Produces a ALT_WDT_WDT_COMP_PARAM_1_RSVD_31_29 register field value suitable for setting the register. */
1895 #define ALT_WDT_WDT_COMP_PARAM_1_RSVD_31_29_SET(value) (((value) << 29) & 0xe0000000)
1896 
1897 #ifndef __ASSEMBLY__
1898 /*
1899  * WARNING: The C register and register group struct declarations are provided for
1900  * convenience and illustrative purposes. They should, however, be used with
1901  * caution as the C language standard provides no guarantees about the alignment or
1902  * atomicity of device memory accesses. The recommended practice for coding device
1903  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1904  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1905  * alt_write_dword() functions for 64 bit registers.
1906  *
1907  * The struct declaration for register ALT_WDT_WDT_COMP_PARAM_1.
1908  */
1909 struct ALT_WDT_WDT_COMP_PARAM_1_s
1910 {
1911  const volatile uint32_t WDT_ALWAYS_EN : 1; /* ALT_WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN */
1912  const volatile uint32_t WDT_DFLT_RMOD : 1; /* ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD */
1913  const volatile uint32_t WDT_DUAL_TOP : 1; /* ALT_WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP */
1914  const volatile uint32_t WDT_HC_RMOD : 1; /* ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD */
1915  const volatile uint32_t WDT_HC_RPL : 1; /* ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_RPL */
1916  const volatile uint32_t WDT_HC_TOP : 1; /* ALT_WDT_WDT_COMP_PARAM_1_WDT_HC_TOP */
1917  const volatile uint32_t WDT_USE_FIX_TOP : 1; /* ALT_WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP */
1918  const volatile uint32_t WDT_PAUSE : 1; /* ALT_WDT_WDT_COMP_PARAM_1_WDT_PAUSE */
1919  const volatile uint32_t APB_DATA_WIDTH : 2; /* ALT_WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH */
1920  const volatile uint32_t WDT_DFLT_RPL : 3; /* ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL */
1921  const volatile uint32_t RSVD_15_13 : 3; /* ALT_WDT_WDT_COMP_PARAM_1_RSVD_15_13 */
1922  const volatile uint32_t WDT_DFLT_TOP : 4; /* ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP */
1923  const volatile uint32_t WDT_DFLT_TOP_INIT : 4; /* ALT_WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT */
1924  const volatile uint32_t WDT_CNT_WIDTH : 5; /* ALT_WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH */
1925  const volatile uint32_t RSVD_31_29 : 3; /* ALT_WDT_WDT_COMP_PARAM_1_RSVD_31_29 */
1926 };
1927 
1928 /* The typedef declaration for register ALT_WDT_WDT_COMP_PARAM_1. */
1929 typedef struct ALT_WDT_WDT_COMP_PARAM_1_s ALT_WDT_WDT_COMP_PARAM_1_t;
1930 #endif /* __ASSEMBLY__ */
1931 
1932 /* The reset value of the ALT_WDT_WDT_COMP_PARAM_1 register. */
1933 #define ALT_WDT_WDT_COMP_PARAM_1_RESET 0x10ff1244
1934 /* The byte offset of the ALT_WDT_WDT_COMP_PARAM_1 register from the beginning of the component. */
1935 #define ALT_WDT_WDT_COMP_PARAM_1_OFST 0xf4
1936 /* The address of the ALT_WDT_WDT_COMP_PARAM_1 register. */
1937 #define ALT_WDT_WDT_COMP_PARAM_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_WDT_WDT_COMP_PARAM_1_OFST))
1938 
1939 /*
1940  * Register : Component Version Register - WDT_COMP_VERSION
1941  *
1942  * Component Version Register
1943  *
1944  * Register Layout
1945  *
1946  * Bits | Access | Reset | Description
1947  * :-------|:-------|:-----------|:------------------------------------------
1948  * [31:0] | R | 0x3130382a | ALT_WDT_WDT_COMP_VERSION_WDT_COMP_VERSION
1949  *
1950  */
1951 /*
1952  * Field : wdt_comp_version
1953  *
1954  * ASCII value for each number in the version, followed by *. For example,
1955  *
1956  * 32_30_31_2A represents the version 2.01*. Reset Value: See the Releases
1957  *
1958  * table in the DW_apb_rtc Release Notes.
1959  *
1960  * Field Access Macros:
1961  *
1962  */
1963 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_COMP_VERSION_WDT_COMP_VERSION register field. */
1964 #define ALT_WDT_WDT_COMP_VERSION_WDT_COMP_VERSION_LSB 0
1965 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_COMP_VERSION_WDT_COMP_VERSION register field. */
1966 #define ALT_WDT_WDT_COMP_VERSION_WDT_COMP_VERSION_MSB 31
1967 /* The width in bits of the ALT_WDT_WDT_COMP_VERSION_WDT_COMP_VERSION register field. */
1968 #define ALT_WDT_WDT_COMP_VERSION_WDT_COMP_VERSION_WIDTH 32
1969 /* The mask used to set the ALT_WDT_WDT_COMP_VERSION_WDT_COMP_VERSION register field value. */
1970 #define ALT_WDT_WDT_COMP_VERSION_WDT_COMP_VERSION_SET_MSK 0xffffffff
1971 /* The mask used to clear the ALT_WDT_WDT_COMP_VERSION_WDT_COMP_VERSION register field value. */
1972 #define ALT_WDT_WDT_COMP_VERSION_WDT_COMP_VERSION_CLR_MSK 0x00000000
1973 /* The reset value of the ALT_WDT_WDT_COMP_VERSION_WDT_COMP_VERSION register field. */
1974 #define ALT_WDT_WDT_COMP_VERSION_WDT_COMP_VERSION_RESET 0x3130382a
1975 /* Extracts the ALT_WDT_WDT_COMP_VERSION_WDT_COMP_VERSION field value from a register. */
1976 #define ALT_WDT_WDT_COMP_VERSION_WDT_COMP_VERSION_GET(value) (((value) & 0xffffffff) >> 0)
1977 /* Produces a ALT_WDT_WDT_COMP_VERSION_WDT_COMP_VERSION register field value suitable for setting the register. */
1978 #define ALT_WDT_WDT_COMP_VERSION_WDT_COMP_VERSION_SET(value) (((value) << 0) & 0xffffffff)
1979 
1980 #ifndef __ASSEMBLY__
1981 /*
1982  * WARNING: The C register and register group struct declarations are provided for
1983  * convenience and illustrative purposes. They should, however, be used with
1984  * caution as the C language standard provides no guarantees about the alignment or
1985  * atomicity of device memory accesses. The recommended practice for coding device
1986  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1987  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1988  * alt_write_dword() functions for 64 bit registers.
1989  *
1990  * The struct declaration for register ALT_WDT_WDT_COMP_VERSION.
1991  */
1992 struct ALT_WDT_WDT_COMP_VERSION_s
1993 {
1994  const volatile uint32_t wdt_comp_version : 32; /* ALT_WDT_WDT_COMP_VERSION_WDT_COMP_VERSION */
1995 };
1996 
1997 /* The typedef declaration for register ALT_WDT_WDT_COMP_VERSION. */
1998 typedef struct ALT_WDT_WDT_COMP_VERSION_s ALT_WDT_WDT_COMP_VERSION_t;
1999 #endif /* __ASSEMBLY__ */
2000 
2001 /* The reset value of the ALT_WDT_WDT_COMP_VERSION register. */
2002 #define ALT_WDT_WDT_COMP_VERSION_RESET 0x3130382a
2003 /* The byte offset of the ALT_WDT_WDT_COMP_VERSION register from the beginning of the component. */
2004 #define ALT_WDT_WDT_COMP_VERSION_OFST 0xf8
2005 /* The address of the ALT_WDT_WDT_COMP_VERSION register. */
2006 #define ALT_WDT_WDT_COMP_VERSION_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_WDT_WDT_COMP_VERSION_OFST))
2007 
2008 /*
2009  * Register : Component Type Register - WDT_COMP_TYPE
2010  *
2011  * Component Type Register
2012  *
2013  * Register Layout
2014  *
2015  * Bits | Access | Reset | Description
2016  * :-------|:-------|:-----------|:------------------------------------
2017  * [31:0] | R | 0x44570120 | ALT_WDT_WDT_COMP_TYPE_WDT_COMP_TYPE
2018  *
2019  */
2020 /*
2021  * Field : wdt_comp_type
2022  *
2023  * Component Type Register
2024  *
2025  * Field Access Macros:
2026  *
2027  */
2028 /* The Least Significant Bit (LSB) position of the ALT_WDT_WDT_COMP_TYPE_WDT_COMP_TYPE register field. */
2029 #define ALT_WDT_WDT_COMP_TYPE_WDT_COMP_TYPE_LSB 0
2030 /* The Most Significant Bit (MSB) position of the ALT_WDT_WDT_COMP_TYPE_WDT_COMP_TYPE register field. */
2031 #define ALT_WDT_WDT_COMP_TYPE_WDT_COMP_TYPE_MSB 31
2032 /* The width in bits of the ALT_WDT_WDT_COMP_TYPE_WDT_COMP_TYPE register field. */
2033 #define ALT_WDT_WDT_COMP_TYPE_WDT_COMP_TYPE_WIDTH 32
2034 /* The mask used to set the ALT_WDT_WDT_COMP_TYPE_WDT_COMP_TYPE register field value. */
2035 #define ALT_WDT_WDT_COMP_TYPE_WDT_COMP_TYPE_SET_MSK 0xffffffff
2036 /* The mask used to clear the ALT_WDT_WDT_COMP_TYPE_WDT_COMP_TYPE register field value. */
2037 #define ALT_WDT_WDT_COMP_TYPE_WDT_COMP_TYPE_CLR_MSK 0x00000000
2038 /* The reset value of the ALT_WDT_WDT_COMP_TYPE_WDT_COMP_TYPE register field. */
2039 #define ALT_WDT_WDT_COMP_TYPE_WDT_COMP_TYPE_RESET 0x44570120
2040 /* Extracts the ALT_WDT_WDT_COMP_TYPE_WDT_COMP_TYPE field value from a register. */
2041 #define ALT_WDT_WDT_COMP_TYPE_WDT_COMP_TYPE_GET(value) (((value) & 0xffffffff) >> 0)
2042 /* Produces a ALT_WDT_WDT_COMP_TYPE_WDT_COMP_TYPE register field value suitable for setting the register. */
2043 #define ALT_WDT_WDT_COMP_TYPE_WDT_COMP_TYPE_SET(value) (((value) << 0) & 0xffffffff)
2044 
2045 #ifndef __ASSEMBLY__
2046 /*
2047  * WARNING: The C register and register group struct declarations are provided for
2048  * convenience and illustrative purposes. They should, however, be used with
2049  * caution as the C language standard provides no guarantees about the alignment or
2050  * atomicity of device memory accesses. The recommended practice for coding device
2051  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2052  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2053  * alt_write_dword() functions for 64 bit registers.
2054  *
2055  * The struct declaration for register ALT_WDT_WDT_COMP_TYPE.
2056  */
2057 struct ALT_WDT_WDT_COMP_TYPE_s
2058 {
2059  const volatile uint32_t wdt_comp_type : 32; /* ALT_WDT_WDT_COMP_TYPE_WDT_COMP_TYPE */
2060 };
2061 
2062 /* The typedef declaration for register ALT_WDT_WDT_COMP_TYPE. */
2063 typedef struct ALT_WDT_WDT_COMP_TYPE_s ALT_WDT_WDT_COMP_TYPE_t;
2064 #endif /* __ASSEMBLY__ */
2065 
2066 /* The reset value of the ALT_WDT_WDT_COMP_TYPE register. */
2067 #define ALT_WDT_WDT_COMP_TYPE_RESET 0x44570120
2068 /* The byte offset of the ALT_WDT_WDT_COMP_TYPE register from the beginning of the component. */
2069 #define ALT_WDT_WDT_COMP_TYPE_OFST 0xfc
2070 /* The address of the ALT_WDT_WDT_COMP_TYPE register. */
2071 #define ALT_WDT_WDT_COMP_TYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_WDT_WDT_COMP_TYPE_OFST))
2072 
2073 #ifndef __ASSEMBLY__
2074 /*
2075  * WARNING: The C register and register group struct declarations are provided for
2076  * convenience and illustrative purposes. They should, however, be used with
2077  * caution as the C language standard provides no guarantees about the alignment or
2078  * atomicity of device memory accesses. The recommended practice for coding device
2079  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2080  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2081  * alt_write_dword() functions for 64 bit registers.
2082  *
2083  * The struct declaration for register group ALT_WDT.
2084  */
2085 struct ALT_WDT_s
2086 {
2087  volatile ALT_WDT_WDT_CR_t WDT_CR; /* ALT_WDT_WDT_CR */
2088  volatile ALT_WDT_WDT_TORR_t WDT_TORR; /* ALT_WDT_WDT_TORR */
2089  volatile ALT_WDT_WDT_CCVR_t WDT_CCVR; /* ALT_WDT_WDT_CCVR */
2090  volatile ALT_WDT_WDT_CRR_t WDT_CRR; /* ALT_WDT_WDT_CRR */
2091  volatile ALT_WDT_WDT_STAT_t WDT_STAT; /* ALT_WDT_WDT_STAT */
2092  volatile ALT_WDT_WDT_EOI_t WDT_EOI; /* ALT_WDT_WDT_EOI */
2093  volatile uint32_t _pad_0x18_0xe3[51]; /* *UNDEFINED* */
2094  volatile ALT_WDT_WDT_COMP_PARAM_5_t WDT_COMP_PARAM_5; /* ALT_WDT_WDT_COMP_PARAM_5 */
2095  volatile ALT_WDT_WDT_COMP_PARAM_4_t WDT_COMP_PARAM_4; /* ALT_WDT_WDT_COMP_PARAM_4 */
2096  volatile ALT_WDT_WDT_COMP_PARAM_3_t WDT_COMP_PARAM_3; /* ALT_WDT_WDT_COMP_PARAM_3 */
2097  volatile ALT_WDT_WDT_COMP_PARAM_2_t WDT_COMP_PARAM_2; /* ALT_WDT_WDT_COMP_PARAM_2 */
2098  volatile ALT_WDT_WDT_COMP_PARAM_1_t WDT_COMP_PARAM_1; /* ALT_WDT_WDT_COMP_PARAM_1 */
2099  volatile ALT_WDT_WDT_COMP_VERSION_t WDT_COMP_VERSION; /* ALT_WDT_WDT_COMP_VERSION */
2100  volatile ALT_WDT_WDT_COMP_TYPE_t WDT_COMP_TYPE; /* ALT_WDT_WDT_COMP_TYPE */
2101 };
2102 
2103 /* The typedef declaration for register group ALT_WDT. */
2104 typedef struct ALT_WDT_s ALT_WDT_t;
2105 /* The struct declaration for the raw register contents of register group ALT_WDT. */
2106 struct ALT_WDT_raw_s
2107 {
2108  volatile uint32_t WDT_CR; /* ALT_WDT_WDT_CR */
2109  volatile uint32_t WDT_TORR; /* ALT_WDT_WDT_TORR */
2110  volatile uint32_t WDT_CCVR; /* ALT_WDT_WDT_CCVR */
2111  volatile uint32_t WDT_CRR; /* ALT_WDT_WDT_CRR */
2112  volatile uint32_t WDT_STAT; /* ALT_WDT_WDT_STAT */
2113  volatile uint32_t WDT_EOI; /* ALT_WDT_WDT_EOI */
2114  volatile uint32_t _pad_0x18_0xe3[51]; /* *UNDEFINED* */
2115  volatile uint32_t WDT_COMP_PARAM_5; /* ALT_WDT_WDT_COMP_PARAM_5 */
2116  volatile uint32_t WDT_COMP_PARAM_4; /* ALT_WDT_WDT_COMP_PARAM_4 */
2117  volatile uint32_t WDT_COMP_PARAM_3; /* ALT_WDT_WDT_COMP_PARAM_3 */
2118  volatile uint32_t WDT_COMP_PARAM_2; /* ALT_WDT_WDT_COMP_PARAM_2 */
2119  volatile uint32_t WDT_COMP_PARAM_1; /* ALT_WDT_WDT_COMP_PARAM_1 */
2120  volatile uint32_t WDT_COMP_VERSION; /* ALT_WDT_WDT_COMP_VERSION */
2121  volatile uint32_t WDT_COMP_TYPE; /* ALT_WDT_WDT_COMP_TYPE */
2122 };
2123 
2124 /* The typedef declaration for the raw register contents of register group ALT_WDT. */
2125 typedef struct ALT_WDT_raw_s ALT_WDT_raw_t;
2126 #endif /* __ASSEMBLY__ */
2127 
2128 
2129 #ifdef __cplusplus
2130 }
2131 #endif /* __cplusplus */
2132 #endif /* __ALT_SOCAL_WDT_H__ */
2133