35 #ifndef __ALTERA_ALT_SPIS_H__
36 #define __ALTERA_ALT_SPIS_H__
101 #define ALT_SPIS_CTLR0_DFS_E_WIDTH4BIT 0x3
107 #define ALT_SPIS_CTLR0_DFS_E_WIDTH5BIT 0x4
113 #define ALT_SPIS_CTLR0_DFS_E_WIDTH6BIT 0x5
119 #define ALT_SPIS_CTLR0_DFS_E_WIDTH7BIT 0x6
125 #define ALT_SPIS_CTLR0_DFS_E_WIDTH8BIT 0x7
131 #define ALT_SPIS_CTLR0_DFS_E_WIDTH9BIT 0x8
137 #define ALT_SPIS_CTLR0_DFS_E_WIDTH10BIT 0x9
140 #define ALT_SPIS_CTLR0_DFS_LSB 0
142 #define ALT_SPIS_CTLR0_DFS_MSB 3
144 #define ALT_SPIS_CTLR0_DFS_WIDTH 4
146 #define ALT_SPIS_CTLR0_DFS_SET_MSK 0x0000000f
148 #define ALT_SPIS_CTLR0_DFS_CLR_MSK 0xfffffff0
150 #define ALT_SPIS_CTLR0_DFS_RESET 0x7
152 #define ALT_SPIS_CTLR0_DFS_GET(value) (((value) & 0x0000000f) >> 0)
154 #define ALT_SPIS_CTLR0_DFS_SET(value) (((value) << 0) & 0x0000000f)
177 #define ALT_SPIS_CTLR0_FRF_E_MOTSPI 0x0
183 #define ALT_SPIS_CTLR0_FRF_E_TISSP 0x1
189 #define ALT_SPIS_CTLR0_FRF_E_NATMW 0x2
192 #define ALT_SPIS_CTLR0_FRF_LSB 4
194 #define ALT_SPIS_CTLR0_FRF_MSB 5
196 #define ALT_SPIS_CTLR0_FRF_WIDTH 2
198 #define ALT_SPIS_CTLR0_FRF_SET_MSK 0x00000030
200 #define ALT_SPIS_CTLR0_FRF_CLR_MSK 0xffffffcf
202 #define ALT_SPIS_CTLR0_FRF_RESET 0x0
204 #define ALT_SPIS_CTLR0_FRF_GET(value) (((value) & 0x00000030) >> 4)
206 #define ALT_SPIS_CTLR0_FRF_SET(value) (((value) << 4) & 0x00000030)
232 #define ALT_SPIS_CTLR0_SCPH_E_INACTLOW 0x0
238 #define ALT_SPIS_CTLR0_SCPH_E_INACTHIGH 0x1
241 #define ALT_SPIS_CTLR0_SCPH_LSB 6
243 #define ALT_SPIS_CTLR0_SCPH_MSB 6
245 #define ALT_SPIS_CTLR0_SCPH_WIDTH 1
247 #define ALT_SPIS_CTLR0_SCPH_SET_MSK 0x00000040
249 #define ALT_SPIS_CTLR0_SCPH_CLR_MSK 0xffffffbf
251 #define ALT_SPIS_CTLR0_SCPH_RESET 0x0
253 #define ALT_SPIS_CTLR0_SCPH_GET(value) (((value) & 0x00000040) >> 6)
255 #define ALT_SPIS_CTLR0_SCPH_SET(value) (((value) << 6) & 0x00000040)
279 #define ALT_SPIS_CTLR0_SCPOL_E_MIDBIT 0x0
285 #define ALT_SPIS_CTLR0_SCPOL_E_STARTBIT 0x1
288 #define ALT_SPIS_CTLR0_SCPOL_LSB 7
290 #define ALT_SPIS_CTLR0_SCPOL_MSB 7
292 #define ALT_SPIS_CTLR0_SCPOL_WIDTH 1
294 #define ALT_SPIS_CTLR0_SCPOL_SET_MSK 0x00000080
296 #define ALT_SPIS_CTLR0_SCPOL_CLR_MSK 0xffffff7f
298 #define ALT_SPIS_CTLR0_SCPOL_RESET 0x0
300 #define ALT_SPIS_CTLR0_SCPOL_GET(value) (((value) & 0x00000080) >> 7)
302 #define ALT_SPIS_CTLR0_SCPOL_SET(value) (((value) << 7) & 0x00000080)
333 #define ALT_SPIS_CTLR0_TMOD_E_TXRX 0x0
339 #define ALT_SPIS_CTLR0_TMOD_E_TXONLY 0x1
345 #define ALT_SPIS_CTLR0_TMOD_E_RXONLY 0x2
348 #define ALT_SPIS_CTLR0_TMOD_LSB 8
350 #define ALT_SPIS_CTLR0_TMOD_MSB 9
352 #define ALT_SPIS_CTLR0_TMOD_WIDTH 2
354 #define ALT_SPIS_CTLR0_TMOD_SET_MSK 0x00000300
356 #define ALT_SPIS_CTLR0_TMOD_CLR_MSK 0xfffffcff
358 #define ALT_SPIS_CTLR0_TMOD_RESET 0x0
360 #define ALT_SPIS_CTLR0_TMOD_GET(value) (((value) & 0x00000300) >> 8)
362 #define ALT_SPIS_CTLR0_TMOD_SET(value) (((value) << 8) & 0x00000300)
392 #define ALT_SPIS_CTLR0_SLV_OE_E_END 0x0
398 #define ALT_SPIS_CTLR0_SLV_OE_E_DISD 0x1
401 #define ALT_SPIS_CTLR0_SLV_OE_LSB 10
403 #define ALT_SPIS_CTLR0_SLV_OE_MSB 10
405 #define ALT_SPIS_CTLR0_SLV_OE_WIDTH 1
407 #define ALT_SPIS_CTLR0_SLV_OE_SET_MSK 0x00000400
409 #define ALT_SPIS_CTLR0_SLV_OE_CLR_MSK 0xfffffbff
411 #define ALT_SPIS_CTLR0_SLV_OE_RESET 0x0
413 #define ALT_SPIS_CTLR0_SLV_OE_GET(value) (((value) & 0x00000400) >> 10)
415 #define ALT_SPIS_CTLR0_SLV_OE_SET(value) (((value) << 10) & 0x00000400)
438 #define ALT_SPIS_CTLR0_SRL_E_NORMMOD 0x0
444 #define ALT_SPIS_CTLR0_SRL_E_TESTMOD 0x1
447 #define ALT_SPIS_CTLR0_SRL_LSB 11
449 #define ALT_SPIS_CTLR0_SRL_MSB 11
451 #define ALT_SPIS_CTLR0_SRL_WIDTH 1
453 #define ALT_SPIS_CTLR0_SRL_SET_MSK 0x00000800
455 #define ALT_SPIS_CTLR0_SRL_CLR_MSK 0xfffff7ff
457 #define ALT_SPIS_CTLR0_SRL_RESET 0x0
459 #define ALT_SPIS_CTLR0_SRL_GET(value) (((value) & 0x00000800) >> 11)
461 #define ALT_SPIS_CTLR0_SRL_SET(value) (((value) << 11) & 0x00000800)
473 #define ALT_SPIS_CTLR0_CFS_LSB 12
475 #define ALT_SPIS_CTLR0_CFS_MSB 15
477 #define ALT_SPIS_CTLR0_CFS_WIDTH 4
479 #define ALT_SPIS_CTLR0_CFS_SET_MSK 0x0000f000
481 #define ALT_SPIS_CTLR0_CFS_CLR_MSK 0xffff0fff
483 #define ALT_SPIS_CTLR0_CFS_RESET 0x0
485 #define ALT_SPIS_CTLR0_CFS_GET(value) (((value) & 0x0000f000) >> 12)
487 #define ALT_SPIS_CTLR0_CFS_SET(value) (((value) << 12) & 0x0000f000)
500 struct ALT_SPIS_CTLR0_s
514 typedef volatile struct ALT_SPIS_CTLR0_s ALT_SPIS_CTLR0_t;
518 #define ALT_SPIS_CTLR0_OFST 0x0
520 #define ALT_SPIS_CTLR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_CTLR0_OFST))
557 #define ALT_SPIS_SPIENR_SPI_EN_E_DISD 0x0
563 #define ALT_SPIS_SPIENR_SPI_EN_E_END 0x1
566 #define ALT_SPIS_SPIENR_SPI_EN_LSB 0
568 #define ALT_SPIS_SPIENR_SPI_EN_MSB 0
570 #define ALT_SPIS_SPIENR_SPI_EN_WIDTH 1
572 #define ALT_SPIS_SPIENR_SPI_EN_SET_MSK 0x00000001
574 #define ALT_SPIS_SPIENR_SPI_EN_CLR_MSK 0xfffffffe
576 #define ALT_SPIS_SPIENR_SPI_EN_RESET 0x0
578 #define ALT_SPIS_SPIENR_SPI_EN_GET(value) (((value) & 0x00000001) >> 0)
580 #define ALT_SPIS_SPIENR_SPI_EN_SET(value) (((value) << 0) & 0x00000001)
593 struct ALT_SPIS_SPIENR_s
600 typedef volatile struct ALT_SPIS_SPIENR_s ALT_SPIS_SPIENR_t;
604 #define ALT_SPIS_SPIENR_OFST 0x8
606 #define ALT_SPIS_SPIENR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SPIENR_OFST))
648 #define ALT_SPIS_MWCR_MWMOD_E_NONSEQ 0x0
654 #define ALT_SPIS_MWCR_MWMOD_E_SEQ 0x1
657 #define ALT_SPIS_MWCR_MWMOD_LSB 0
659 #define ALT_SPIS_MWCR_MWMOD_MSB 0
661 #define ALT_SPIS_MWCR_MWMOD_WIDTH 1
663 #define ALT_SPIS_MWCR_MWMOD_SET_MSK 0x00000001
665 #define ALT_SPIS_MWCR_MWMOD_CLR_MSK 0xfffffffe
667 #define ALT_SPIS_MWCR_MWMOD_RESET 0x0
669 #define ALT_SPIS_MWCR_MWMOD_GET(value) (((value) & 0x00000001) >> 0)
671 #define ALT_SPIS_MWCR_MWMOD_SET(value) (((value) << 0) & 0x00000001)
694 #define ALT_SPIS_MWCR_MDD_E_RXMOD 0x0
700 #define ALT_SPIS_MWCR_MDD_E_TXMOD 0x1
703 #define ALT_SPIS_MWCR_MDD_LSB 1
705 #define ALT_SPIS_MWCR_MDD_MSB 1
707 #define ALT_SPIS_MWCR_MDD_WIDTH 1
709 #define ALT_SPIS_MWCR_MDD_SET_MSK 0x00000002
711 #define ALT_SPIS_MWCR_MDD_CLR_MSK 0xfffffffd
713 #define ALT_SPIS_MWCR_MDD_RESET 0x0
715 #define ALT_SPIS_MWCR_MDD_GET(value) (((value) & 0x00000002) >> 1)
717 #define ALT_SPIS_MWCR_MDD_SET(value) (((value) << 1) & 0x00000002)
730 struct ALT_SPIS_MWCR_s
738 typedef volatile struct ALT_SPIS_MWCR_s ALT_SPIS_MWCR_t;
742 #define ALT_SPIS_MWCR_OFST 0xc
744 #define ALT_SPIS_MWCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_MWCR_OFST))
772 #define ALT_SPIS_TXFTLR_TFT_LSB 0
774 #define ALT_SPIS_TXFTLR_TFT_MSB 7
776 #define ALT_SPIS_TXFTLR_TFT_WIDTH 8
778 #define ALT_SPIS_TXFTLR_TFT_SET_MSK 0x000000ff
780 #define ALT_SPIS_TXFTLR_TFT_CLR_MSK 0xffffff00
782 #define ALT_SPIS_TXFTLR_TFT_RESET 0x0
784 #define ALT_SPIS_TXFTLR_TFT_GET(value) (((value) & 0x000000ff) >> 0)
786 #define ALT_SPIS_TXFTLR_TFT_SET(value) (((value) << 0) & 0x000000ff)
799 struct ALT_SPIS_TXFTLR_s
806 typedef volatile struct ALT_SPIS_TXFTLR_s ALT_SPIS_TXFTLR_t;
810 #define ALT_SPIS_TXFTLR_OFST 0x18
812 #define ALT_SPIS_TXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXFTLR_OFST))
840 #define ALT_SPIS_RXFTLR_RFT_LSB 0
842 #define ALT_SPIS_RXFTLR_RFT_MSB 7
844 #define ALT_SPIS_RXFTLR_RFT_WIDTH 8
846 #define ALT_SPIS_RXFTLR_RFT_SET_MSK 0x000000ff
848 #define ALT_SPIS_RXFTLR_RFT_CLR_MSK 0xffffff00
850 #define ALT_SPIS_RXFTLR_RFT_RESET 0x0
852 #define ALT_SPIS_RXFTLR_RFT_GET(value) (((value) & 0x000000ff) >> 0)
854 #define ALT_SPIS_RXFTLR_RFT_SET(value) (((value) << 0) & 0x000000ff)
867 struct ALT_SPIS_RXFTLR_s
874 typedef volatile struct ALT_SPIS_RXFTLR_s ALT_SPIS_RXFTLR_t;
878 #define ALT_SPIS_RXFTLR_OFST 0x1c
880 #define ALT_SPIS_RXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXFTLR_OFST))
905 #define ALT_SPIS_TXFLR_TXTFL_LSB 0
907 #define ALT_SPIS_TXFLR_TXTFL_MSB 8
909 #define ALT_SPIS_TXFLR_TXTFL_WIDTH 9
911 #define ALT_SPIS_TXFLR_TXTFL_SET_MSK 0x000001ff
913 #define ALT_SPIS_TXFLR_TXTFL_CLR_MSK 0xfffffe00
915 #define ALT_SPIS_TXFLR_TXTFL_RESET 0x0
917 #define ALT_SPIS_TXFLR_TXTFL_GET(value) (((value) & 0x000001ff) >> 0)
919 #define ALT_SPIS_TXFLR_TXTFL_SET(value) (((value) << 0) & 0x000001ff)
932 struct ALT_SPIS_TXFLR_s
934 const uint32_t txtfl : 9;
939 typedef volatile struct ALT_SPIS_TXFLR_s ALT_SPIS_TXFLR_t;
943 #define ALT_SPIS_TXFLR_OFST 0x20
945 #define ALT_SPIS_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXFLR_OFST))
970 #define ALT_SPIS_RXFLR_RXTFL_LSB 0
972 #define ALT_SPIS_RXFLR_RXTFL_MSB 8
974 #define ALT_SPIS_RXFLR_RXTFL_WIDTH 9
976 #define ALT_SPIS_RXFLR_RXTFL_SET_MSK 0x000001ff
978 #define ALT_SPIS_RXFLR_RXTFL_CLR_MSK 0xfffffe00
980 #define ALT_SPIS_RXFLR_RXTFL_RESET 0x0
982 #define ALT_SPIS_RXFLR_RXTFL_GET(value) (((value) & 0x000001ff) >> 0)
984 #define ALT_SPIS_RXFLR_RXTFL_SET(value) (((value) << 0) & 0x000001ff)
997 struct ALT_SPIS_RXFLR_s
999 const uint32_t rxtfl : 9;
1004 typedef volatile struct ALT_SPIS_RXFLR_s ALT_SPIS_RXFLR_t;
1008 #define ALT_SPIS_RXFLR_OFST 0x24
1010 #define ALT_SPIS_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXFLR_OFST))
1052 #define ALT_SPIS_SR_BUSY_E_INACT 0x0
1058 #define ALT_SPIS_SR_BUSY_E_ACT 0x1
1061 #define ALT_SPIS_SR_BUSY_LSB 0
1063 #define ALT_SPIS_SR_BUSY_MSB 0
1065 #define ALT_SPIS_SR_BUSY_WIDTH 1
1067 #define ALT_SPIS_SR_BUSY_SET_MSK 0x00000001
1069 #define ALT_SPIS_SR_BUSY_CLR_MSK 0xfffffffe
1071 #define ALT_SPIS_SR_BUSY_RESET 0x0
1073 #define ALT_SPIS_SR_BUSY_GET(value) (((value) & 0x00000001) >> 0)
1075 #define ALT_SPIS_SR_BUSY_SET(value) (((value) << 0) & 0x00000001)
1097 #define ALT_SPIS_SR_TFNF_E_FULL 0x0
1103 #define ALT_SPIS_SR_TFNF_E_NOTFULL 0x1
1106 #define ALT_SPIS_SR_TFNF_LSB 1
1108 #define ALT_SPIS_SR_TFNF_MSB 1
1110 #define ALT_SPIS_SR_TFNF_WIDTH 1
1112 #define ALT_SPIS_SR_TFNF_SET_MSK 0x00000002
1114 #define ALT_SPIS_SR_TFNF_CLR_MSK 0xfffffffd
1116 #define ALT_SPIS_SR_TFNF_RESET 0x1
1118 #define ALT_SPIS_SR_TFNF_GET(value) (((value) & 0x00000002) >> 1)
1120 #define ALT_SPIS_SR_TFNF_SET(value) (((value) << 1) & 0x00000002)
1143 #define ALT_SPIS_SR_TFE_E_EMPTY 0x1
1149 #define ALT_SPIS_SR_TFE_E_NOTEMPTY 0x0
1152 #define ALT_SPIS_SR_TFE_LSB 2
1154 #define ALT_SPIS_SR_TFE_MSB 2
1156 #define ALT_SPIS_SR_TFE_WIDTH 1
1158 #define ALT_SPIS_SR_TFE_SET_MSK 0x00000004
1160 #define ALT_SPIS_SR_TFE_CLR_MSK 0xfffffffb
1162 #define ALT_SPIS_SR_TFE_RESET 0x1
1164 #define ALT_SPIS_SR_TFE_GET(value) (((value) & 0x00000004) >> 2)
1166 #define ALT_SPIS_SR_TFE_SET(value) (((value) << 2) & 0x00000004)
1188 #define ALT_SPIS_SR_RFNE_E_EMPTY 0x0
1194 #define ALT_SPIS_SR_RFNE_E_NOTEMPTY 0x1
1197 #define ALT_SPIS_SR_RFNE_LSB 3
1199 #define ALT_SPIS_SR_RFNE_MSB 3
1201 #define ALT_SPIS_SR_RFNE_WIDTH 1
1203 #define ALT_SPIS_SR_RFNE_SET_MSK 0x00000008
1205 #define ALT_SPIS_SR_RFNE_CLR_MSK 0xfffffff7
1207 #define ALT_SPIS_SR_RFNE_RESET 0x0
1209 #define ALT_SPIS_SR_RFNE_GET(value) (((value) & 0x00000008) >> 3)
1211 #define ALT_SPIS_SR_RFNE_SET(value) (((value) << 3) & 0x00000008)
1233 #define ALT_SPIS_SR_RFF_E_NOTFULL 0x0
1239 #define ALT_SPIS_SR_RFF_E_FULL 0x1
1242 #define ALT_SPIS_SR_RFF_LSB 4
1244 #define ALT_SPIS_SR_RFF_MSB 4
1246 #define ALT_SPIS_SR_RFF_WIDTH 1
1248 #define ALT_SPIS_SR_RFF_SET_MSK 0x00000010
1250 #define ALT_SPIS_SR_RFF_CLR_MSK 0xffffffef
1252 #define ALT_SPIS_SR_RFF_RESET 0x0
1254 #define ALT_SPIS_SR_RFF_GET(value) (((value) & 0x00000010) >> 4)
1256 #define ALT_SPIS_SR_RFF_SET(value) (((value) << 4) & 0x00000010)
1279 #define ALT_SPIS_SR_TXE_E_NOERROR 0x0
1285 #define ALT_SPIS_SR_TXE_E_ERROR 0x1
1288 #define ALT_SPIS_SR_TXE_LSB 5
1290 #define ALT_SPIS_SR_TXE_MSB 5
1292 #define ALT_SPIS_SR_TXE_WIDTH 1
1294 #define ALT_SPIS_SR_TXE_SET_MSK 0x00000020
1296 #define ALT_SPIS_SR_TXE_CLR_MSK 0xffffffdf
1298 #define ALT_SPIS_SR_TXE_RESET 0x0
1300 #define ALT_SPIS_SR_TXE_GET(value) (((value) & 0x00000020) >> 5)
1302 #define ALT_SPIS_SR_TXE_SET(value) (((value) << 5) & 0x00000020)
1304 #ifndef __ASSEMBLY__
1315 struct ALT_SPIS_SR_s
1317 const uint32_t busy : 1;
1318 const uint32_t tfnf : 1;
1319 const uint32_t tfe : 1;
1320 const uint32_t rfne : 1;
1321 const uint32_t rff : 1;
1322 const uint32_t txe : 1;
1327 typedef volatile struct ALT_SPIS_SR_s ALT_SPIS_SR_t;
1331 #define ALT_SPIS_SR_OFST 0x28
1333 #define ALT_SPIS_SR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SR_OFST))
1372 #define ALT_SPIS_IMR_TXEIM_E_MSKED 0x0
1378 #define ALT_SPIS_IMR_TXEIM_E_END 0x1
1381 #define ALT_SPIS_IMR_TXEIM_LSB 0
1383 #define ALT_SPIS_IMR_TXEIM_MSB 0
1385 #define ALT_SPIS_IMR_TXEIM_WIDTH 1
1387 #define ALT_SPIS_IMR_TXEIM_SET_MSK 0x00000001
1389 #define ALT_SPIS_IMR_TXEIM_CLR_MSK 0xfffffffe
1391 #define ALT_SPIS_IMR_TXEIM_RESET 0x1
1393 #define ALT_SPIS_IMR_TXEIM_GET(value) (((value) & 0x00000001) >> 0)
1395 #define ALT_SPIS_IMR_TXEIM_SET(value) (((value) << 0) & 0x00000001)
1417 #define ALT_SPIS_IMR_TXOIM_E_MSKED 0x0
1423 #define ALT_SPIS_IMR_TXOIM_E_END 0x1
1426 #define ALT_SPIS_IMR_TXOIM_LSB 1
1428 #define ALT_SPIS_IMR_TXOIM_MSB 1
1430 #define ALT_SPIS_IMR_TXOIM_WIDTH 1
1432 #define ALT_SPIS_IMR_TXOIM_SET_MSK 0x00000002
1434 #define ALT_SPIS_IMR_TXOIM_CLR_MSK 0xfffffffd
1436 #define ALT_SPIS_IMR_TXOIM_RESET 0x1
1438 #define ALT_SPIS_IMR_TXOIM_GET(value) (((value) & 0x00000002) >> 1)
1440 #define ALT_SPIS_IMR_TXOIM_SET(value) (((value) << 1) & 0x00000002)
1462 #define ALT_SPIS_IMR_RXUIM_E_MSKED 0x0
1468 #define ALT_SPIS_IMR_RXUIM_E_END 0x1
1471 #define ALT_SPIS_IMR_RXUIM_LSB 2
1473 #define ALT_SPIS_IMR_RXUIM_MSB 2
1475 #define ALT_SPIS_IMR_RXUIM_WIDTH 1
1477 #define ALT_SPIS_IMR_RXUIM_SET_MSK 0x00000004
1479 #define ALT_SPIS_IMR_RXUIM_CLR_MSK 0xfffffffb
1481 #define ALT_SPIS_IMR_RXUIM_RESET 0x1
1483 #define ALT_SPIS_IMR_RXUIM_GET(value) (((value) & 0x00000004) >> 2)
1485 #define ALT_SPIS_IMR_RXUIM_SET(value) (((value) << 2) & 0x00000004)
1507 #define ALT_SPIS_IMR_RXOIM_E_MSKED 0x0
1513 #define ALT_SPIS_IMR_RXOIM_E_END 0x1
1516 #define ALT_SPIS_IMR_RXOIM_LSB 3
1518 #define ALT_SPIS_IMR_RXOIM_MSB 3
1520 #define ALT_SPIS_IMR_RXOIM_WIDTH 1
1522 #define ALT_SPIS_IMR_RXOIM_SET_MSK 0x00000008
1524 #define ALT_SPIS_IMR_RXOIM_CLR_MSK 0xfffffff7
1526 #define ALT_SPIS_IMR_RXOIM_RESET 0x1
1528 #define ALT_SPIS_IMR_RXOIM_GET(value) (((value) & 0x00000008) >> 3)
1530 #define ALT_SPIS_IMR_RXOIM_SET(value) (((value) << 3) & 0x00000008)
1552 #define ALT_SPIS_IMR_RXFIM_E_MSKED 0x0
1558 #define ALT_SPIS_IMR_RXFIM_E_END 0x1
1561 #define ALT_SPIS_IMR_RXFIM_LSB 4
1563 #define ALT_SPIS_IMR_RXFIM_MSB 4
1565 #define ALT_SPIS_IMR_RXFIM_WIDTH 1
1567 #define ALT_SPIS_IMR_RXFIM_SET_MSK 0x00000010
1569 #define ALT_SPIS_IMR_RXFIM_CLR_MSK 0xffffffef
1571 #define ALT_SPIS_IMR_RXFIM_RESET 0x1
1573 #define ALT_SPIS_IMR_RXFIM_GET(value) (((value) & 0x00000010) >> 4)
1575 #define ALT_SPIS_IMR_RXFIM_SET(value) (((value) << 4) & 0x00000010)
1577 #ifndef __ASSEMBLY__
1588 struct ALT_SPIS_IMR_s
1599 typedef volatile struct ALT_SPIS_IMR_s ALT_SPIS_IMR_t;
1603 #define ALT_SPIS_IMR_OFST 0x2c
1605 #define ALT_SPIS_IMR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_IMR_OFST))
1646 #define ALT_SPIS_ISR_TXEIS_E_INACT 0x0
1652 #define ALT_SPIS_ISR_TXEIS_E_ACT 0x1
1655 #define ALT_SPIS_ISR_TXEIS_LSB 0
1657 #define ALT_SPIS_ISR_TXEIS_MSB 0
1659 #define ALT_SPIS_ISR_TXEIS_WIDTH 1
1661 #define ALT_SPIS_ISR_TXEIS_SET_MSK 0x00000001
1663 #define ALT_SPIS_ISR_TXEIS_CLR_MSK 0xfffffffe
1665 #define ALT_SPIS_ISR_TXEIS_RESET 0x0
1667 #define ALT_SPIS_ISR_TXEIS_GET(value) (((value) & 0x00000001) >> 0)
1669 #define ALT_SPIS_ISR_TXEIS_SET(value) (((value) << 0) & 0x00000001)
1692 #define ALT_SPIS_ISR_TXOIS_E_INACT 0x0
1698 #define ALT_SPIS_ISR_TXOIS_E_ACT 0x1
1701 #define ALT_SPIS_ISR_TXOIS_LSB 1
1703 #define ALT_SPIS_ISR_TXOIS_MSB 1
1705 #define ALT_SPIS_ISR_TXOIS_WIDTH 1
1707 #define ALT_SPIS_ISR_TXOIS_SET_MSK 0x00000002
1709 #define ALT_SPIS_ISR_TXOIS_CLR_MSK 0xfffffffd
1711 #define ALT_SPIS_ISR_TXOIS_RESET 0x0
1713 #define ALT_SPIS_ISR_TXOIS_GET(value) (((value) & 0x00000002) >> 1)
1715 #define ALT_SPIS_ISR_TXOIS_SET(value) (((value) << 1) & 0x00000002)
1738 #define ALT_SPIS_ISR_RXUIS_E_INACT 0x0
1744 #define ALT_SPIS_ISR_RXUIS_E_ACT 0x1
1747 #define ALT_SPIS_ISR_RXUIS_LSB 2
1749 #define ALT_SPIS_ISR_RXUIS_MSB 2
1751 #define ALT_SPIS_ISR_RXUIS_WIDTH 1
1753 #define ALT_SPIS_ISR_RXUIS_SET_MSK 0x00000004
1755 #define ALT_SPIS_ISR_RXUIS_CLR_MSK 0xfffffffb
1757 #define ALT_SPIS_ISR_RXUIS_RESET 0x0
1759 #define ALT_SPIS_ISR_RXUIS_GET(value) (((value) & 0x00000004) >> 2)
1761 #define ALT_SPIS_ISR_RXUIS_SET(value) (((value) << 2) & 0x00000004)
1784 #define ALT_SPIS_ISR_RXOIS_E_INACT 0x0
1790 #define ALT_SPIS_ISR_RXOIS_E_ACT 0x1
1793 #define ALT_SPIS_ISR_RXOIS_LSB 3
1795 #define ALT_SPIS_ISR_RXOIS_MSB 3
1797 #define ALT_SPIS_ISR_RXOIS_WIDTH 1
1799 #define ALT_SPIS_ISR_RXOIS_SET_MSK 0x00000008
1801 #define ALT_SPIS_ISR_RXOIS_CLR_MSK 0xfffffff7
1803 #define ALT_SPIS_ISR_RXOIS_RESET 0x0
1805 #define ALT_SPIS_ISR_RXOIS_GET(value) (((value) & 0x00000008) >> 3)
1807 #define ALT_SPIS_ISR_RXOIS_SET(value) (((value) << 3) & 0x00000008)
1830 #define ALT_SPIS_ISR_RXFIS_E_INACT 0x0
1836 #define ALT_SPIS_ISR_RXFIS_E_ACT 0x1
1839 #define ALT_SPIS_ISR_RXFIS_LSB 4
1841 #define ALT_SPIS_ISR_RXFIS_MSB 4
1843 #define ALT_SPIS_ISR_RXFIS_WIDTH 1
1845 #define ALT_SPIS_ISR_RXFIS_SET_MSK 0x00000010
1847 #define ALT_SPIS_ISR_RXFIS_CLR_MSK 0xffffffef
1849 #define ALT_SPIS_ISR_RXFIS_RESET 0x0
1851 #define ALT_SPIS_ISR_RXFIS_GET(value) (((value) & 0x00000010) >> 4)
1853 #define ALT_SPIS_ISR_RXFIS_SET(value) (((value) << 4) & 0x00000010)
1855 #ifndef __ASSEMBLY__
1866 struct ALT_SPIS_ISR_s
1868 const uint32_t txeis : 1;
1869 const uint32_t txois : 1;
1870 const uint32_t rxuis : 1;
1871 const uint32_t rxois : 1;
1872 const uint32_t rxfis : 1;
1877 typedef volatile struct ALT_SPIS_ISR_s ALT_SPIS_ISR_t;
1881 #define ALT_SPIS_ISR_OFST 0x30
1883 #define ALT_SPIS_ISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_ISR_OFST))
1923 #define ALT_SPIS_RISR_TXEIR_E_INACT 0x0
1929 #define ALT_SPIS_RISR_TXEIR_E_ACT 0x1
1932 #define ALT_SPIS_RISR_TXEIR_LSB 0
1934 #define ALT_SPIS_RISR_TXEIR_MSB 0
1936 #define ALT_SPIS_RISR_TXEIR_WIDTH 1
1938 #define ALT_SPIS_RISR_TXEIR_SET_MSK 0x00000001
1940 #define ALT_SPIS_RISR_TXEIR_CLR_MSK 0xfffffffe
1942 #define ALT_SPIS_RISR_TXEIR_RESET 0x0
1944 #define ALT_SPIS_RISR_TXEIR_GET(value) (((value) & 0x00000001) >> 0)
1946 #define ALT_SPIS_RISR_TXEIR_SET(value) (((value) << 0) & 0x00000001)
1969 #define ALT_SPIS_RISR_TXOIR_E_INACT 0x0
1975 #define ALT_SPIS_RISR_TXOIR_E_ACT 0x1
1978 #define ALT_SPIS_RISR_TXOIR_LSB 1
1980 #define ALT_SPIS_RISR_TXOIR_MSB 1
1982 #define ALT_SPIS_RISR_TXOIR_WIDTH 1
1984 #define ALT_SPIS_RISR_TXOIR_SET_MSK 0x00000002
1986 #define ALT_SPIS_RISR_TXOIR_CLR_MSK 0xfffffffd
1988 #define ALT_SPIS_RISR_TXOIR_RESET 0x0
1990 #define ALT_SPIS_RISR_TXOIR_GET(value) (((value) & 0x00000002) >> 1)
1992 #define ALT_SPIS_RISR_TXOIR_SET(value) (((value) << 1) & 0x00000002)
2016 #define ALT_SPIS_RISR_RXUIR_E_INACT 0x0
2022 #define ALT_SPIS_RISR_RXUIR_E_ACT 0x1
2025 #define ALT_SPIS_RISR_RXUIR_LSB 2
2027 #define ALT_SPIS_RISR_RXUIR_MSB 2
2029 #define ALT_SPIS_RISR_RXUIR_WIDTH 1
2031 #define ALT_SPIS_RISR_RXUIR_SET_MSK 0x00000004
2033 #define ALT_SPIS_RISR_RXUIR_CLR_MSK 0xfffffffb
2035 #define ALT_SPIS_RISR_RXUIR_RESET 0x0
2037 #define ALT_SPIS_RISR_RXUIR_GET(value) (((value) & 0x00000004) >> 2)
2039 #define ALT_SPIS_RISR_RXUIR_SET(value) (((value) << 2) & 0x00000004)
2062 #define ALT_SPIS_RISR_RXOIR_E_INACT 0x0
2068 #define ALT_SPIS_RISR_RXOIR_E_ACT 0x1
2071 #define ALT_SPIS_RISR_RXOIR_LSB 3
2073 #define ALT_SPIS_RISR_RXOIR_MSB 3
2075 #define ALT_SPIS_RISR_RXOIR_WIDTH 1
2077 #define ALT_SPIS_RISR_RXOIR_SET_MSK 0x00000008
2079 #define ALT_SPIS_RISR_RXOIR_CLR_MSK 0xfffffff7
2081 #define ALT_SPIS_RISR_RXOIR_RESET 0x0
2083 #define ALT_SPIS_RISR_RXOIR_GET(value) (((value) & 0x00000008) >> 3)
2085 #define ALT_SPIS_RISR_RXOIR_SET(value) (((value) << 3) & 0x00000008)
2109 #define ALT_SPIS_RISR_RXFIR_E_INACT 0x0
2115 #define ALT_SPIS_RISR_RXFIR_E_ACT 0x1
2118 #define ALT_SPIS_RISR_RXFIR_LSB 4
2120 #define ALT_SPIS_RISR_RXFIR_MSB 4
2122 #define ALT_SPIS_RISR_RXFIR_WIDTH 1
2124 #define ALT_SPIS_RISR_RXFIR_SET_MSK 0x00000010
2126 #define ALT_SPIS_RISR_RXFIR_CLR_MSK 0xffffffef
2128 #define ALT_SPIS_RISR_RXFIR_RESET 0x0
2130 #define ALT_SPIS_RISR_RXFIR_GET(value) (((value) & 0x00000010) >> 4)
2132 #define ALT_SPIS_RISR_RXFIR_SET(value) (((value) << 4) & 0x00000010)
2134 #ifndef __ASSEMBLY__
2145 struct ALT_SPIS_RISR_s
2147 const uint32_t txeir : 1;
2148 const uint32_t txoir : 1;
2149 const uint32_t rxuir : 1;
2150 const uint32_t rxoir : 1;
2151 const uint32_t rxfir : 1;
2156 typedef volatile struct ALT_SPIS_RISR_s ALT_SPIS_RISR_t;
2160 #define ALT_SPIS_RISR_OFST 0x34
2162 #define ALT_SPIS_RISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RISR_OFST))
2185 #define ALT_SPIS_TXOICR_TXOICR_LSB 0
2187 #define ALT_SPIS_TXOICR_TXOICR_MSB 0
2189 #define ALT_SPIS_TXOICR_TXOICR_WIDTH 1
2191 #define ALT_SPIS_TXOICR_TXOICR_SET_MSK 0x00000001
2193 #define ALT_SPIS_TXOICR_TXOICR_CLR_MSK 0xfffffffe
2195 #define ALT_SPIS_TXOICR_TXOICR_RESET 0x0
2197 #define ALT_SPIS_TXOICR_TXOICR_GET(value) (((value) & 0x00000001) >> 0)
2199 #define ALT_SPIS_TXOICR_TXOICR_SET(value) (((value) << 0) & 0x00000001)
2201 #ifndef __ASSEMBLY__
2212 struct ALT_SPIS_TXOICR_s
2214 const uint32_t txoicr : 1;
2219 typedef volatile struct ALT_SPIS_TXOICR_s ALT_SPIS_TXOICR_t;
2223 #define ALT_SPIS_TXOICR_OFST 0x38
2225 #define ALT_SPIS_TXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXOICR_OFST))
2248 #define ALT_SPIS_RXOICR_RXOICR_LSB 0
2250 #define ALT_SPIS_RXOICR_RXOICR_MSB 0
2252 #define ALT_SPIS_RXOICR_RXOICR_WIDTH 1
2254 #define ALT_SPIS_RXOICR_RXOICR_SET_MSK 0x00000001
2256 #define ALT_SPIS_RXOICR_RXOICR_CLR_MSK 0xfffffffe
2258 #define ALT_SPIS_RXOICR_RXOICR_RESET 0x0
2260 #define ALT_SPIS_RXOICR_RXOICR_GET(value) (((value) & 0x00000001) >> 0)
2262 #define ALT_SPIS_RXOICR_RXOICR_SET(value) (((value) << 0) & 0x00000001)
2264 #ifndef __ASSEMBLY__
2275 struct ALT_SPIS_RXOICR_s
2277 const uint32_t rxoicr : 1;
2282 typedef volatile struct ALT_SPIS_RXOICR_s ALT_SPIS_RXOICR_t;
2286 #define ALT_SPIS_RXOICR_OFST 0x3c
2288 #define ALT_SPIS_RXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXOICR_OFST))
2311 #define ALT_SPIS_RXUICR_RXUICR_LSB 0
2313 #define ALT_SPIS_RXUICR_RXUICR_MSB 0
2315 #define ALT_SPIS_RXUICR_RXUICR_WIDTH 1
2317 #define ALT_SPIS_RXUICR_RXUICR_SET_MSK 0x00000001
2319 #define ALT_SPIS_RXUICR_RXUICR_CLR_MSK 0xfffffffe
2321 #define ALT_SPIS_RXUICR_RXUICR_RESET 0x0
2323 #define ALT_SPIS_RXUICR_RXUICR_GET(value) (((value) & 0x00000001) >> 0)
2325 #define ALT_SPIS_RXUICR_RXUICR_SET(value) (((value) << 0) & 0x00000001)
2327 #ifndef __ASSEMBLY__
2338 struct ALT_SPIS_RXUICR_s
2340 const uint32_t rxuicr : 1;
2345 typedef volatile struct ALT_SPIS_RXUICR_s ALT_SPIS_RXUICR_t;
2349 #define ALT_SPIS_RXUICR_OFST 0x40
2351 #define ALT_SPIS_RXUICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXUICR_OFST))
2375 #define ALT_SPIS_ICR_ICR_LSB 0
2377 #define ALT_SPIS_ICR_ICR_MSB 0
2379 #define ALT_SPIS_ICR_ICR_WIDTH 1
2381 #define ALT_SPIS_ICR_ICR_SET_MSK 0x00000001
2383 #define ALT_SPIS_ICR_ICR_CLR_MSK 0xfffffffe
2385 #define ALT_SPIS_ICR_ICR_RESET 0x0
2387 #define ALT_SPIS_ICR_ICR_GET(value) (((value) & 0x00000001) >> 0)
2389 #define ALT_SPIS_ICR_ICR_SET(value) (((value) << 0) & 0x00000001)
2391 #ifndef __ASSEMBLY__
2402 struct ALT_SPIS_ICR_s
2404 const uint32_t icr : 1;
2409 typedef volatile struct ALT_SPIS_ICR_s ALT_SPIS_ICR_t;
2413 #define ALT_SPIS_ICR_OFST 0x48
2415 #define ALT_SPIS_ICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_ICR_OFST))
2451 #define ALT_SPIS_DMACR_RDMAE_E_DISD 0x0
2457 #define ALT_SPIS_DMACR_RDMAE_E_END 0x1
2460 #define ALT_SPIS_DMACR_RDMAE_LSB 0
2462 #define ALT_SPIS_DMACR_RDMAE_MSB 0
2464 #define ALT_SPIS_DMACR_RDMAE_WIDTH 1
2466 #define ALT_SPIS_DMACR_RDMAE_SET_MSK 0x00000001
2468 #define ALT_SPIS_DMACR_RDMAE_CLR_MSK 0xfffffffe
2470 #define ALT_SPIS_DMACR_RDMAE_RESET 0x0
2472 #define ALT_SPIS_DMACR_RDMAE_GET(value) (((value) & 0x00000001) >> 0)
2474 #define ALT_SPIS_DMACR_RDMAE_SET(value) (((value) << 0) & 0x00000001)
2496 #define ALT_SPIS_DMACR_TDMAE_E_DISD 0x0
2502 #define ALT_SPIS_DMACR_TDMAE_E_END 0x1
2505 #define ALT_SPIS_DMACR_TDMAE_LSB 1
2507 #define ALT_SPIS_DMACR_TDMAE_MSB 1
2509 #define ALT_SPIS_DMACR_TDMAE_WIDTH 1
2511 #define ALT_SPIS_DMACR_TDMAE_SET_MSK 0x00000002
2513 #define ALT_SPIS_DMACR_TDMAE_CLR_MSK 0xfffffffd
2515 #define ALT_SPIS_DMACR_TDMAE_RESET 0x0
2517 #define ALT_SPIS_DMACR_TDMAE_GET(value) (((value) & 0x00000002) >> 1)
2519 #define ALT_SPIS_DMACR_TDMAE_SET(value) (((value) << 1) & 0x00000002)
2521 #ifndef __ASSEMBLY__
2532 struct ALT_SPIS_DMACR_s
2540 typedef volatile struct ALT_SPIS_DMACR_s ALT_SPIS_DMACR_t;
2544 #define ALT_SPIS_DMACR_OFST 0x4c
2546 #define ALT_SPIS_DMACR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMACR_OFST))
2573 #define ALT_SPIS_DMATDLR_DMATDL_LSB 0
2575 #define ALT_SPIS_DMATDLR_DMATDL_MSB 7
2577 #define ALT_SPIS_DMATDLR_DMATDL_WIDTH 8
2579 #define ALT_SPIS_DMATDLR_DMATDL_SET_MSK 0x000000ff
2581 #define ALT_SPIS_DMATDLR_DMATDL_CLR_MSK 0xffffff00
2583 #define ALT_SPIS_DMATDLR_DMATDL_RESET 0x0
2585 #define ALT_SPIS_DMATDLR_DMATDL_GET(value) (((value) & 0x000000ff) >> 0)
2587 #define ALT_SPIS_DMATDLR_DMATDL_SET(value) (((value) << 0) & 0x000000ff)
2589 #ifndef __ASSEMBLY__
2600 struct ALT_SPIS_DMATDLR_s
2602 uint32_t dmatdl : 8;
2607 typedef volatile struct ALT_SPIS_DMATDLR_s ALT_SPIS_DMATDLR_t;
2611 #define ALT_SPIS_DMATDLR_OFST 0x50
2613 #define ALT_SPIS_DMATDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMATDLR_OFST))
2640 #define ALT_SPIS_DMARDLR_DMARDL_LSB 0
2642 #define ALT_SPIS_DMARDLR_DMARDL_MSB 7
2644 #define ALT_SPIS_DMARDLR_DMARDL_WIDTH 8
2646 #define ALT_SPIS_DMARDLR_DMARDL_SET_MSK 0x000000ff
2648 #define ALT_SPIS_DMARDLR_DMARDL_CLR_MSK 0xffffff00
2650 #define ALT_SPIS_DMARDLR_DMARDL_RESET 0x0
2652 #define ALT_SPIS_DMARDLR_DMARDL_GET(value) (((value) & 0x000000ff) >> 0)
2654 #define ALT_SPIS_DMARDLR_DMARDL_SET(value) (((value) << 0) & 0x000000ff)
2656 #ifndef __ASSEMBLY__
2667 struct ALT_SPIS_DMARDLR_s
2669 uint32_t dmardl : 8;
2674 typedef volatile struct ALT_SPIS_DMARDLR_s ALT_SPIS_DMARDLR_t;
2678 #define ALT_SPIS_DMARDLR_OFST 0x54
2680 #define ALT_SPIS_DMARDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMARDLR_OFST))
2703 #define ALT_SPIS_IDR_IDR_LSB 0
2705 #define ALT_SPIS_IDR_IDR_MSB 31
2707 #define ALT_SPIS_IDR_IDR_WIDTH 32
2709 #define ALT_SPIS_IDR_IDR_SET_MSK 0xffffffff
2711 #define ALT_SPIS_IDR_IDR_CLR_MSK 0x00000000
2713 #define ALT_SPIS_IDR_IDR_RESET 0x5510005
2715 #define ALT_SPIS_IDR_IDR_GET(value) (((value) & 0xffffffff) >> 0)
2717 #define ALT_SPIS_IDR_IDR_SET(value) (((value) << 0) & 0xffffffff)
2719 #ifndef __ASSEMBLY__
2730 struct ALT_SPIS_IDR_s
2732 const uint32_t idr : 32;
2736 typedef volatile struct ALT_SPIS_IDR_s ALT_SPIS_IDR_t;
2740 #define ALT_SPIS_IDR_OFST 0x58
2742 #define ALT_SPIS_IDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_IDR_OFST))
2766 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_LSB 0
2768 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_MSB 31
2770 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_WIDTH 32
2772 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_SET_MSK 0xffffffff
2774 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_CLR_MSK 0x00000000
2776 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_RESET 0x3332302a
2778 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_GET(value) (((value) & 0xffffffff) >> 0)
2780 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_SET(value) (((value) << 0) & 0xffffffff)
2782 #ifndef __ASSEMBLY__
2793 struct ALT_SPIS_SPI_VER_ID_s
2795 uint32_t spi_version_id : 32;
2799 typedef volatile struct ALT_SPIS_SPI_VER_ID_s ALT_SPIS_SPI_VER_ID_t;
2803 #define ALT_SPIS_SPI_VER_ID_OFST 0x5c
2805 #define ALT_SPIS_SPI_VER_ID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SPI_VER_ID_OFST))
2837 #define ALT_SPIS_DR_DR_LSB 0
2839 #define ALT_SPIS_DR_DR_MSB 15
2841 #define ALT_SPIS_DR_DR_WIDTH 16
2843 #define ALT_SPIS_DR_DR_SET_MSK 0x0000ffff
2845 #define ALT_SPIS_DR_DR_CLR_MSK 0xffff0000
2847 #define ALT_SPIS_DR_DR_RESET 0x0
2849 #define ALT_SPIS_DR_DR_GET(value) (((value) & 0x0000ffff) >> 0)
2851 #define ALT_SPIS_DR_DR_SET(value) (((value) << 0) & 0x0000ffff)
2853 #ifndef __ASSEMBLY__
2864 struct ALT_SPIS_DR_s
2871 typedef volatile struct ALT_SPIS_DR_s ALT_SPIS_DR_t;
2875 #define ALT_SPIS_DR_OFST 0x60
2877 #define ALT_SPIS_DR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR_OFST))
2879 #ifndef __ASSEMBLY__
2892 ALT_SPIS_CTLR0_t ctrlr0;
2893 volatile uint32_t _pad_0x4_0x7;
2894 ALT_SPIS_SPIENR_t spienr;
2895 ALT_SPIS_MWCR_t mwcr;
2896 volatile uint32_t _pad_0x10_0x17[2];
2897 ALT_SPIS_TXFTLR_t txftlr;
2898 ALT_SPIS_RXFTLR_t rxftlr;
2899 ALT_SPIS_TXFLR_t txflr;
2900 ALT_SPIS_RXFLR_t rxflr;
2904 ALT_SPIS_RISR_t risr;
2905 ALT_SPIS_TXOICR_t txoicr;
2906 ALT_SPIS_RXOICR_t rxoicr;
2907 ALT_SPIS_RXUICR_t rxuicr;
2908 volatile uint32_t _pad_0x44_0x47;
2910 ALT_SPIS_DMACR_t dmacr;
2911 ALT_SPIS_DMATDLR_t dmatdlr;
2912 ALT_SPIS_DMARDLR_t dmardlr;
2914 ALT_SPIS_SPI_VER_ID_t spi_version_id;
2916 volatile uint32_t _pad_0x64_0x80[7];
2920 typedef volatile struct ALT_SPIS_s ALT_SPIS_t;
2922 struct ALT_SPIS_raw_s
2924 volatile uint32_t ctrlr0;
2925 uint32_t _pad_0x4_0x7;
2926 volatile uint32_t spienr;
2927 volatile uint32_t mwcr;
2928 uint32_t _pad_0x10_0x17[2];
2929 volatile uint32_t txftlr;
2930 volatile uint32_t rxftlr;
2931 volatile uint32_t txflr;
2932 volatile uint32_t rxflr;
2933 volatile uint32_t sr;
2934 volatile uint32_t imr;
2935 volatile uint32_t isr;
2936 volatile uint32_t risr;
2937 volatile uint32_t txoicr;
2938 volatile uint32_t rxoicr;
2939 volatile uint32_t rxuicr;
2940 uint32_t _pad_0x44_0x47;
2941 volatile uint32_t icr;
2942 volatile uint32_t dmacr;
2943 volatile uint32_t dmatdlr;
2944 volatile uint32_t dmardlr;
2945 volatile uint32_t idr;
2946 volatile uint32_t spi_version_id;
2947 volatile uint32_t dr;
2948 uint32_t _pad_0x64_0x80[7];
2952 typedef volatile struct ALT_SPIS_raw_s ALT_SPIS_raw_t;