35 #ifndef __ALT_SOCAL_SPIS_H__
36 #define __ALT_SOCAL_SPIS_H__
121 #define ALT_SPIS_CTLR0_DFS_E_WIDTH4BIT 0x3
127 #define ALT_SPIS_CTLR0_DFS_E_WIDTH5BIT 0x4
133 #define ALT_SPIS_CTLR0_DFS_E_WIDTH6BIT 0x5
139 #define ALT_SPIS_CTLR0_DFS_E_WIDTH7BIT 0x6
145 #define ALT_SPIS_CTLR0_DFS_E_WIDTH8BIT 0x7
151 #define ALT_SPIS_CTLR0_DFS_E_WIDTH9BIT 0x8
157 #define ALT_SPIS_CTLR0_DFS_E_WIDTH10BIT 0x9
163 #define ALT_SPIS_CTLR0_DFS_E_WIDTH11BIT 0xa
169 #define ALT_SPIS_CTLR0_DFS_E_WIDTH12BIT 0xb
175 #define ALT_SPIS_CTLR0_DFS_E_WIDTH13BIT 0xc
181 #define ALT_SPIS_CTLR0_DFS_E_WIDTH14BIT 0xd
187 #define ALT_SPIS_CTLR0_DFS_E_WIDTH15BIT 0xe
193 #define ALT_SPIS_CTLR0_DFS_E_WIDTH16BIT 0xf
196 #define ALT_SPIS_CTLR0_DFS_LSB 0
198 #define ALT_SPIS_CTLR0_DFS_MSB 3
200 #define ALT_SPIS_CTLR0_DFS_WIDTH 4
202 #define ALT_SPIS_CTLR0_DFS_SET_MSK 0x0000000f
204 #define ALT_SPIS_CTLR0_DFS_CLR_MSK 0xfffffff0
206 #define ALT_SPIS_CTLR0_DFS_RESET 0x7
208 #define ALT_SPIS_CTLR0_DFS_GET(value) (((value) & 0x0000000f) >> 0)
210 #define ALT_SPIS_CTLR0_DFS_SET(value) (((value) << 0) & 0x0000000f)
243 #define ALT_SPIS_CTLR0_FRF_E_MOTSPI 0x0
249 #define ALT_SPIS_CTLR0_FRF_E_TISSP 0x1
255 #define ALT_SPIS_CTLR0_FRF_E_NATMW 0x2
258 #define ALT_SPIS_CTLR0_FRF_LSB 4
260 #define ALT_SPIS_CTLR0_FRF_MSB 5
262 #define ALT_SPIS_CTLR0_FRF_WIDTH 2
264 #define ALT_SPIS_CTLR0_FRF_SET_MSK 0x00000030
266 #define ALT_SPIS_CTLR0_FRF_CLR_MSK 0xffffffcf
268 #define ALT_SPIS_CTLR0_FRF_RESET 0x0
270 #define ALT_SPIS_CTLR0_FRF_GET(value) (((value) & 0x00000030) >> 4)
272 #define ALT_SPIS_CTLR0_FRF_SET(value) (((value) << 4) & 0x00000030)
310 #define ALT_SPIS_CTLR0_SCPH_E_INACTLOW 0x0
316 #define ALT_SPIS_CTLR0_SCPH_E_INACTHIGH 0x1
319 #define ALT_SPIS_CTLR0_SCPH_LSB 6
321 #define ALT_SPIS_CTLR0_SCPH_MSB 6
323 #define ALT_SPIS_CTLR0_SCPH_WIDTH 1
325 #define ALT_SPIS_CTLR0_SCPH_SET_MSK 0x00000040
327 #define ALT_SPIS_CTLR0_SCPH_CLR_MSK 0xffffffbf
329 #define ALT_SPIS_CTLR0_SCPH_RESET 0x0
331 #define ALT_SPIS_CTLR0_SCPH_GET(value) (((value) & 0x00000040) >> 6)
333 #define ALT_SPIS_CTLR0_SCPH_SET(value) (((value) << 6) & 0x00000040)
365 #define ALT_SPIS_CTLR0_SCPOL_E_MIDBIT 0x0
371 #define ALT_SPIS_CTLR0_SCPOL_E_STARTBIT 0x1
374 #define ALT_SPIS_CTLR0_SCPOL_LSB 7
376 #define ALT_SPIS_CTLR0_SCPOL_MSB 7
378 #define ALT_SPIS_CTLR0_SCPOL_WIDTH 1
380 #define ALT_SPIS_CTLR0_SCPOL_SET_MSK 0x00000080
382 #define ALT_SPIS_CTLR0_SCPOL_CLR_MSK 0xffffff7f
384 #define ALT_SPIS_CTLR0_SCPOL_RESET 0x0
386 #define ALT_SPIS_CTLR0_SCPOL_GET(value) (((value) & 0x00000080) >> 7)
388 #define ALT_SPIS_CTLR0_SCPOL_SET(value) (((value) << 7) & 0x00000080)
441 #define ALT_SPIS_CTLR0_TMOD_E_TXRX 0x0
447 #define ALT_SPIS_CTLR0_TMOD_E_TXONLY 0x1
453 #define ALT_SPIS_CTLR0_TMOD_E_RXONLY 0x2
456 #define ALT_SPIS_CTLR0_TMOD_LSB 8
458 #define ALT_SPIS_CTLR0_TMOD_MSB 9
460 #define ALT_SPIS_CTLR0_TMOD_WIDTH 2
462 #define ALT_SPIS_CTLR0_TMOD_SET_MSK 0x00000300
464 #define ALT_SPIS_CTLR0_TMOD_CLR_MSK 0xfffffcff
466 #define ALT_SPIS_CTLR0_TMOD_RESET 0x0
468 #define ALT_SPIS_CTLR0_TMOD_GET(value) (((value) & 0x00000300) >> 8)
470 #define ALT_SPIS_CTLR0_TMOD_SET(value) (((value) << 8) & 0x00000300)
520 #define ALT_SPIS_CTLR0_SLV_OE_E_END 0x0
526 #define ALT_SPIS_CTLR0_SLV_OE_E_DISD 0x1
529 #define ALT_SPIS_CTLR0_SLV_OE_LSB 10
531 #define ALT_SPIS_CTLR0_SLV_OE_MSB 10
533 #define ALT_SPIS_CTLR0_SLV_OE_WIDTH 1
535 #define ALT_SPIS_CTLR0_SLV_OE_SET_MSK 0x00000400
537 #define ALT_SPIS_CTLR0_SLV_OE_CLR_MSK 0xfffffbff
539 #define ALT_SPIS_CTLR0_SLV_OE_RESET 0x0
541 #define ALT_SPIS_CTLR0_SLV_OE_GET(value) (((value) & 0x00000400) >> 10)
543 #define ALT_SPIS_CTLR0_SLV_OE_SET(value) (((value) << 10) & 0x00000400)
573 #define ALT_SPIS_CTLR0_SRL_E_NORMMOD 0x0
579 #define ALT_SPIS_CTLR0_SRL_E_TESTMOD 0x1
582 #define ALT_SPIS_CTLR0_SRL_LSB 11
584 #define ALT_SPIS_CTLR0_SRL_MSB 11
586 #define ALT_SPIS_CTLR0_SRL_WIDTH 1
588 #define ALT_SPIS_CTLR0_SRL_SET_MSK 0x00000800
590 #define ALT_SPIS_CTLR0_SRL_CLR_MSK 0xfffff7ff
592 #define ALT_SPIS_CTLR0_SRL_RESET 0x0
594 #define ALT_SPIS_CTLR0_SRL_GET(value) (((value) & 0x00000800) >> 11)
596 #define ALT_SPIS_CTLR0_SRL_SET(value) (((value) << 11) & 0x00000800)
634 #define ALT_SPIS_CTLR0_CFS_E_SIZE1BIT 0x0
640 #define ALT_SPIS_CTLR0_CFS_E_SIZE2BIT 0x1
646 #define ALT_SPIS_CTLR0_CFS_E_SIZE3BIT 0x2
652 #define ALT_SPIS_CTLR0_CFS_E_SIZE4BIT 0x3
658 #define ALT_SPIS_CTLR0_CFS_E_SIZE5BIT 0x4
664 #define ALT_SPIS_CTLR0_CFS_E_SIZE6BIT 0x5
670 #define ALT_SPIS_CTLR0_CFS_E_SIZE7BIT 0x6
676 #define ALT_SPIS_CTLR0_CFS_E_SIZE8BIT 0x7
682 #define ALT_SPIS_CTLR0_CFS_E_SIZE9BIT 0x8
688 #define ALT_SPIS_CTLR0_CFS_E_SIZE10BIT 0x9
694 #define ALT_SPIS_CTLR0_CFS_E_SIZE11BIT 0xa
700 #define ALT_SPIS_CTLR0_CFS_E_SIZE12BIT 0xb
706 #define ALT_SPIS_CTLR0_CFS_E_SIZE13BIT 0xc
712 #define ALT_SPIS_CTLR0_CFS_E_SIZE14BIT 0xd
718 #define ALT_SPIS_CTLR0_CFS_E_SIZE15BIT 0xe
724 #define ALT_SPIS_CTLR0_CFS_E_SIZE16BIT 0xf
727 #define ALT_SPIS_CTLR0_CFS_LSB 12
729 #define ALT_SPIS_CTLR0_CFS_MSB 15
731 #define ALT_SPIS_CTLR0_CFS_WIDTH 4
733 #define ALT_SPIS_CTLR0_CFS_SET_MSK 0x0000f000
735 #define ALT_SPIS_CTLR0_CFS_CLR_MSK 0xffff0fff
737 #define ALT_SPIS_CTLR0_CFS_RESET 0x0
739 #define ALT_SPIS_CTLR0_CFS_GET(value) (((value) & 0x0000f000) >> 12)
741 #define ALT_SPIS_CTLR0_CFS_SET(value) (((value) << 12) & 0x0000f000)
754 struct ALT_SPIS_CTLR0_s
768 typedef volatile struct ALT_SPIS_CTLR0_s ALT_SPIS_CTLR0_t;
772 #define ALT_SPIS_CTLR0_RESET 0x00000007
774 #define ALT_SPIS_CTLR0_OFST 0x0
776 #define ALT_SPIS_CTLR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_CTLR0_OFST))
823 #define ALT_SPIS_SPIENR_SPI_EN_E_DISD 0x0
829 #define ALT_SPIS_SPIENR_SPI_EN_E_END 0x1
832 #define ALT_SPIS_SPIENR_SPI_EN_LSB 0
834 #define ALT_SPIS_SPIENR_SPI_EN_MSB 0
836 #define ALT_SPIS_SPIENR_SPI_EN_WIDTH 1
838 #define ALT_SPIS_SPIENR_SPI_EN_SET_MSK 0x00000001
840 #define ALT_SPIS_SPIENR_SPI_EN_CLR_MSK 0xfffffffe
842 #define ALT_SPIS_SPIENR_SPI_EN_RESET 0x0
844 #define ALT_SPIS_SPIENR_SPI_EN_GET(value) (((value) & 0x00000001) >> 0)
846 #define ALT_SPIS_SPIENR_SPI_EN_SET(value) (((value) << 0) & 0x00000001)
859 struct ALT_SPIS_SPIENR_s
866 typedef volatile struct ALT_SPIS_SPIENR_s ALT_SPIS_SPIENR_t;
870 #define ALT_SPIS_SPIENR_RESET 0x00000000
872 #define ALT_SPIS_SPIENR_OFST 0x8
874 #define ALT_SPIS_SPIENR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SPIENR_OFST))
932 #define ALT_SPIS_MWCR_MWMOD_E_NONSEQ 0x0
938 #define ALT_SPIS_MWCR_MWMOD_E_SEQ 0x1
941 #define ALT_SPIS_MWCR_MWMOD_LSB 0
943 #define ALT_SPIS_MWCR_MWMOD_MSB 0
945 #define ALT_SPIS_MWCR_MWMOD_WIDTH 1
947 #define ALT_SPIS_MWCR_MWMOD_SET_MSK 0x00000001
949 #define ALT_SPIS_MWCR_MWMOD_CLR_MSK 0xfffffffe
951 #define ALT_SPIS_MWCR_MWMOD_RESET 0x0
953 #define ALT_SPIS_MWCR_MWMOD_GET(value) (((value) & 0x00000001) >> 0)
955 #define ALT_SPIS_MWCR_MWMOD_SET(value) (((value) << 0) & 0x00000001)
987 #define ALT_SPIS_MWCR_MDD_E_RXMOD 0x0
993 #define ALT_SPIS_MWCR_MDD_E_TXMOD 0x1
996 #define ALT_SPIS_MWCR_MDD_LSB 1
998 #define ALT_SPIS_MWCR_MDD_MSB 1
1000 #define ALT_SPIS_MWCR_MDD_WIDTH 1
1002 #define ALT_SPIS_MWCR_MDD_SET_MSK 0x00000002
1004 #define ALT_SPIS_MWCR_MDD_CLR_MSK 0xfffffffd
1006 #define ALT_SPIS_MWCR_MDD_RESET 0x0
1008 #define ALT_SPIS_MWCR_MDD_GET(value) (((value) & 0x00000002) >> 1)
1010 #define ALT_SPIS_MWCR_MDD_SET(value) (((value) << 1) & 0x00000002)
1012 #ifndef __ASSEMBLY__
1023 struct ALT_SPIS_MWCR_s
1031 typedef volatile struct ALT_SPIS_MWCR_s ALT_SPIS_MWCR_t;
1035 #define ALT_SPIS_MWCR_RESET 0x00000000
1037 #define ALT_SPIS_MWCR_OFST 0xc
1039 #define ALT_SPIS_MWCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_MWCR_OFST))
1081 #define ALT_SPIS_TXFTLR_TFT_LSB 0
1083 #define ALT_SPIS_TXFTLR_TFT_MSB 7
1085 #define ALT_SPIS_TXFTLR_TFT_WIDTH 8
1087 #define ALT_SPIS_TXFTLR_TFT_SET_MSK 0x000000ff
1089 #define ALT_SPIS_TXFTLR_TFT_CLR_MSK 0xffffff00
1091 #define ALT_SPIS_TXFTLR_TFT_RESET 0x0
1093 #define ALT_SPIS_TXFTLR_TFT_GET(value) (((value) & 0x000000ff) >> 0)
1095 #define ALT_SPIS_TXFTLR_TFT_SET(value) (((value) << 0) & 0x000000ff)
1097 #ifndef __ASSEMBLY__
1108 struct ALT_SPIS_TXFTLR_s
1115 typedef volatile struct ALT_SPIS_TXFTLR_s ALT_SPIS_TXFTLR_t;
1119 #define ALT_SPIS_TXFTLR_RESET 0x00000000
1121 #define ALT_SPIS_TXFTLR_OFST 0x18
1123 #define ALT_SPIS_TXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXFTLR_OFST))
1165 #define ALT_SPIS_RXFTLR_RFT_LSB 0
1167 #define ALT_SPIS_RXFTLR_RFT_MSB 7
1169 #define ALT_SPIS_RXFTLR_RFT_WIDTH 8
1171 #define ALT_SPIS_RXFTLR_RFT_SET_MSK 0x000000ff
1173 #define ALT_SPIS_RXFTLR_RFT_CLR_MSK 0xffffff00
1175 #define ALT_SPIS_RXFTLR_RFT_RESET 0x0
1177 #define ALT_SPIS_RXFTLR_RFT_GET(value) (((value) & 0x000000ff) >> 0)
1179 #define ALT_SPIS_RXFTLR_RFT_SET(value) (((value) << 0) & 0x000000ff)
1181 #ifndef __ASSEMBLY__
1192 struct ALT_SPIS_RXFTLR_s
1199 typedef volatile struct ALT_SPIS_RXFTLR_s ALT_SPIS_RXFTLR_t;
1203 #define ALT_SPIS_RXFTLR_RESET 0x00000000
1205 #define ALT_SPIS_RXFTLR_OFST 0x1c
1207 #define ALT_SPIS_RXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXFTLR_OFST))
1233 #define ALT_SPIS_TXFLR_TXTFL_LSB 0
1235 #define ALT_SPIS_TXFLR_TXTFL_MSB 8
1237 #define ALT_SPIS_TXFLR_TXTFL_WIDTH 9
1239 #define ALT_SPIS_TXFLR_TXTFL_SET_MSK 0x000001ff
1241 #define ALT_SPIS_TXFLR_TXTFL_CLR_MSK 0xfffffe00
1243 #define ALT_SPIS_TXFLR_TXTFL_RESET 0x0
1245 #define ALT_SPIS_TXFLR_TXTFL_GET(value) (((value) & 0x000001ff) >> 0)
1247 #define ALT_SPIS_TXFLR_TXTFL_SET(value) (((value) << 0) & 0x000001ff)
1249 #ifndef __ASSEMBLY__
1260 struct ALT_SPIS_TXFLR_s
1262 const uint32_t txtfl : 9;
1267 typedef volatile struct ALT_SPIS_TXFLR_s ALT_SPIS_TXFLR_t;
1271 #define ALT_SPIS_TXFLR_RESET 0x00000000
1273 #define ALT_SPIS_TXFLR_OFST 0x20
1275 #define ALT_SPIS_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXFLR_OFST))
1301 #define ALT_SPIS_RXFLR_RXTFL_LSB 0
1303 #define ALT_SPIS_RXFLR_RXTFL_MSB 8
1305 #define ALT_SPIS_RXFLR_RXTFL_WIDTH 9
1307 #define ALT_SPIS_RXFLR_RXTFL_SET_MSK 0x000001ff
1309 #define ALT_SPIS_RXFLR_RXTFL_CLR_MSK 0xfffffe00
1311 #define ALT_SPIS_RXFLR_RXTFL_RESET 0x0
1313 #define ALT_SPIS_RXFLR_RXTFL_GET(value) (((value) & 0x000001ff) >> 0)
1315 #define ALT_SPIS_RXFLR_RXTFL_SET(value) (((value) << 0) & 0x000001ff)
1317 #ifndef __ASSEMBLY__
1328 struct ALT_SPIS_RXFLR_s
1330 const uint32_t rxtfl : 9;
1335 typedef volatile struct ALT_SPIS_RXFLR_s ALT_SPIS_RXFLR_t;
1339 #define ALT_SPIS_RXFLR_RESET 0x00000000
1341 #define ALT_SPIS_RXFLR_OFST 0x24
1343 #define ALT_SPIS_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXFLR_OFST))
1399 #define ALT_SPIS_SR_BUSY_E_INACT 0x0
1405 #define ALT_SPIS_SR_BUSY_E_ACT 0x1
1408 #define ALT_SPIS_SR_BUSY_LSB 0
1410 #define ALT_SPIS_SR_BUSY_MSB 0
1412 #define ALT_SPIS_SR_BUSY_WIDTH 1
1414 #define ALT_SPIS_SR_BUSY_SET_MSK 0x00000001
1416 #define ALT_SPIS_SR_BUSY_CLR_MSK 0xfffffffe
1418 #define ALT_SPIS_SR_BUSY_RESET 0x0
1420 #define ALT_SPIS_SR_BUSY_GET(value) (((value) & 0x00000001) >> 0)
1422 #define ALT_SPIS_SR_BUSY_SET(value) (((value) << 0) & 0x00000001)
1450 #define ALT_SPIS_SR_TFNF_E_FULL 0x0
1456 #define ALT_SPIS_SR_TFNF_E_NOTFULL 0x1
1459 #define ALT_SPIS_SR_TFNF_LSB 1
1461 #define ALT_SPIS_SR_TFNF_MSB 1
1463 #define ALT_SPIS_SR_TFNF_WIDTH 1
1465 #define ALT_SPIS_SR_TFNF_SET_MSK 0x00000002
1467 #define ALT_SPIS_SR_TFNF_CLR_MSK 0xfffffffd
1469 #define ALT_SPIS_SR_TFNF_RESET 0x1
1471 #define ALT_SPIS_SR_TFNF_GET(value) (((value) & 0x00000002) >> 1)
1473 #define ALT_SPIS_SR_TFNF_SET(value) (((value) << 1) & 0x00000002)
1505 #define ALT_SPIS_SR_TFE_E_NOTEMPTY 0x0
1511 #define ALT_SPIS_SR_TFE_E_EMPTY 0x1
1514 #define ALT_SPIS_SR_TFE_LSB 2
1516 #define ALT_SPIS_SR_TFE_MSB 2
1518 #define ALT_SPIS_SR_TFE_WIDTH 1
1520 #define ALT_SPIS_SR_TFE_SET_MSK 0x00000004
1522 #define ALT_SPIS_SR_TFE_CLR_MSK 0xfffffffb
1524 #define ALT_SPIS_SR_TFE_RESET 0x1
1526 #define ALT_SPIS_SR_TFE_GET(value) (((value) & 0x00000004) >> 2)
1528 #define ALT_SPIS_SR_TFE_SET(value) (((value) << 2) & 0x00000004)
1560 #define ALT_SPIS_SR_RFNE_E_EMPTY 0x0
1566 #define ALT_SPIS_SR_RFNE_E_NOTEMPTY 0x1
1569 #define ALT_SPIS_SR_RFNE_LSB 3
1571 #define ALT_SPIS_SR_RFNE_MSB 3
1573 #define ALT_SPIS_SR_RFNE_WIDTH 1
1575 #define ALT_SPIS_SR_RFNE_SET_MSK 0x00000008
1577 #define ALT_SPIS_SR_RFNE_CLR_MSK 0xfffffff7
1579 #define ALT_SPIS_SR_RFNE_RESET 0x0
1581 #define ALT_SPIS_SR_RFNE_GET(value) (((value) & 0x00000008) >> 3)
1583 #define ALT_SPIS_SR_RFNE_SET(value) (((value) << 3) & 0x00000008)
1613 #define ALT_SPIS_SR_RFF_E_NOTFULL 0x0
1619 #define ALT_SPIS_SR_RFF_E_FULL 0x1
1622 #define ALT_SPIS_SR_RFF_LSB 4
1624 #define ALT_SPIS_SR_RFF_MSB 4
1626 #define ALT_SPIS_SR_RFF_WIDTH 1
1628 #define ALT_SPIS_SR_RFF_SET_MSK 0x00000010
1630 #define ALT_SPIS_SR_RFF_CLR_MSK 0xffffffef
1632 #define ALT_SPIS_SR_RFF_RESET 0x0
1634 #define ALT_SPIS_SR_RFF_GET(value) (((value) & 0x00000010) >> 4)
1636 #define ALT_SPIS_SR_RFF_SET(value) (((value) << 4) & 0x00000010)
1670 #define ALT_SPIS_SR_TXE_E_NOERROR 0x0
1676 #define ALT_SPIS_SR_TXE_E_ERROR 0x1
1679 #define ALT_SPIS_SR_TXE_LSB 5
1681 #define ALT_SPIS_SR_TXE_MSB 5
1683 #define ALT_SPIS_SR_TXE_WIDTH 1
1685 #define ALT_SPIS_SR_TXE_SET_MSK 0x00000020
1687 #define ALT_SPIS_SR_TXE_CLR_MSK 0xffffffdf
1689 #define ALT_SPIS_SR_TXE_RESET 0x0
1691 #define ALT_SPIS_SR_TXE_GET(value) (((value) & 0x00000020) >> 5)
1693 #define ALT_SPIS_SR_TXE_SET(value) (((value) << 5) & 0x00000020)
1695 #ifndef __ASSEMBLY__
1706 struct ALT_SPIS_SR_s
1708 const uint32_t busy : 1;
1709 const uint32_t tfnf : 1;
1710 const uint32_t tfe : 1;
1711 const uint32_t rfne : 1;
1712 const uint32_t rff : 1;
1713 const uint32_t txe : 1;
1718 typedef volatile struct ALT_SPIS_SR_s ALT_SPIS_SR_t;
1722 #define ALT_SPIS_SR_RESET 0x00000006
1724 #define ALT_SPIS_SR_OFST 0x28
1726 #define ALT_SPIS_SR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SR_OFST))
1769 #define ALT_SPIS_IMR_TXEIM_E_MSKED 0x0
1775 #define ALT_SPIS_IMR_TXEIM_E_END 0x1
1778 #define ALT_SPIS_IMR_TXEIM_LSB 0
1780 #define ALT_SPIS_IMR_TXEIM_MSB 0
1782 #define ALT_SPIS_IMR_TXEIM_WIDTH 1
1784 #define ALT_SPIS_IMR_TXEIM_SET_MSK 0x00000001
1786 #define ALT_SPIS_IMR_TXEIM_CLR_MSK 0xfffffffe
1788 #define ALT_SPIS_IMR_TXEIM_RESET 0x1
1790 #define ALT_SPIS_IMR_TXEIM_GET(value) (((value) & 0x00000001) >> 0)
1792 #define ALT_SPIS_IMR_TXEIM_SET(value) (((value) << 0) & 0x00000001)
1818 #define ALT_SPIS_IMR_TXOIM_E_MSKED 0x0
1824 #define ALT_SPIS_IMR_TXOIM_E_END 0x1
1827 #define ALT_SPIS_IMR_TXOIM_LSB 1
1829 #define ALT_SPIS_IMR_TXOIM_MSB 1
1831 #define ALT_SPIS_IMR_TXOIM_WIDTH 1
1833 #define ALT_SPIS_IMR_TXOIM_SET_MSK 0x00000002
1835 #define ALT_SPIS_IMR_TXOIM_CLR_MSK 0xfffffffd
1837 #define ALT_SPIS_IMR_TXOIM_RESET 0x1
1839 #define ALT_SPIS_IMR_TXOIM_GET(value) (((value) & 0x00000002) >> 1)
1841 #define ALT_SPIS_IMR_TXOIM_SET(value) (((value) << 1) & 0x00000002)
1867 #define ALT_SPIS_IMR_RXUIM_E_MSKED 0x0
1873 #define ALT_SPIS_IMR_RXUIM_E_END 0x1
1876 #define ALT_SPIS_IMR_RXUIM_LSB 2
1878 #define ALT_SPIS_IMR_RXUIM_MSB 2
1880 #define ALT_SPIS_IMR_RXUIM_WIDTH 1
1882 #define ALT_SPIS_IMR_RXUIM_SET_MSK 0x00000004
1884 #define ALT_SPIS_IMR_RXUIM_CLR_MSK 0xfffffffb
1886 #define ALT_SPIS_IMR_RXUIM_RESET 0x1
1888 #define ALT_SPIS_IMR_RXUIM_GET(value) (((value) & 0x00000004) >> 2)
1890 #define ALT_SPIS_IMR_RXUIM_SET(value) (((value) << 2) & 0x00000004)
1916 #define ALT_SPIS_IMR_RXOIM_E_MSKED 0x0
1922 #define ALT_SPIS_IMR_RXOIM_E_END 0x1
1925 #define ALT_SPIS_IMR_RXOIM_LSB 3
1927 #define ALT_SPIS_IMR_RXOIM_MSB 3
1929 #define ALT_SPIS_IMR_RXOIM_WIDTH 1
1931 #define ALT_SPIS_IMR_RXOIM_SET_MSK 0x00000008
1933 #define ALT_SPIS_IMR_RXOIM_CLR_MSK 0xfffffff7
1935 #define ALT_SPIS_IMR_RXOIM_RESET 0x1
1937 #define ALT_SPIS_IMR_RXOIM_GET(value) (((value) & 0x00000008) >> 3)
1939 #define ALT_SPIS_IMR_RXOIM_SET(value) (((value) << 3) & 0x00000008)
1965 #define ALT_SPIS_IMR_RXFIM_E_MSKED 0x0
1971 #define ALT_SPIS_IMR_RXFIM_E_END 0x1
1974 #define ALT_SPIS_IMR_RXFIM_LSB 4
1976 #define ALT_SPIS_IMR_RXFIM_MSB 4
1978 #define ALT_SPIS_IMR_RXFIM_WIDTH 1
1980 #define ALT_SPIS_IMR_RXFIM_SET_MSK 0x00000010
1982 #define ALT_SPIS_IMR_RXFIM_CLR_MSK 0xffffffef
1984 #define ALT_SPIS_IMR_RXFIM_RESET 0x1
1986 #define ALT_SPIS_IMR_RXFIM_GET(value) (((value) & 0x00000010) >> 4)
1988 #define ALT_SPIS_IMR_RXFIM_SET(value) (((value) << 4) & 0x00000010)
1990 #ifndef __ASSEMBLY__
2001 struct ALT_SPIS_IMR_s
2012 typedef volatile struct ALT_SPIS_IMR_s ALT_SPIS_IMR_t;
2016 #define ALT_SPIS_IMR_RESET 0x0000001f
2018 #define ALT_SPIS_IMR_OFST 0x2c
2020 #define ALT_SPIS_IMR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_IMR_OFST))
2064 #define ALT_SPIS_ISR_TXEIS_E_INACT 0x0
2070 #define ALT_SPIS_ISR_TXEIS_E_ACT 0x1
2073 #define ALT_SPIS_ISR_TXEIS_LSB 0
2075 #define ALT_SPIS_ISR_TXEIS_MSB 0
2077 #define ALT_SPIS_ISR_TXEIS_WIDTH 1
2079 #define ALT_SPIS_ISR_TXEIS_SET_MSK 0x00000001
2081 #define ALT_SPIS_ISR_TXEIS_CLR_MSK 0xfffffffe
2083 #define ALT_SPIS_ISR_TXEIS_RESET 0x0
2085 #define ALT_SPIS_ISR_TXEIS_GET(value) (((value) & 0x00000001) >> 0)
2087 #define ALT_SPIS_ISR_TXEIS_SET(value) (((value) << 0) & 0x00000001)
2114 #define ALT_SPIS_ISR_TXOIS_E_INACT 0x0
2120 #define ALT_SPIS_ISR_TXOIS_E_ACT 0x1
2123 #define ALT_SPIS_ISR_TXOIS_LSB 1
2125 #define ALT_SPIS_ISR_TXOIS_MSB 1
2127 #define ALT_SPIS_ISR_TXOIS_WIDTH 1
2129 #define ALT_SPIS_ISR_TXOIS_SET_MSK 0x00000002
2131 #define ALT_SPIS_ISR_TXOIS_CLR_MSK 0xfffffffd
2133 #define ALT_SPIS_ISR_TXOIS_RESET 0x0
2135 #define ALT_SPIS_ISR_TXOIS_GET(value) (((value) & 0x00000002) >> 1)
2137 #define ALT_SPIS_ISR_TXOIS_SET(value) (((value) << 1) & 0x00000002)
2164 #define ALT_SPIS_ISR_RXUIS_E_INACT 0x0
2170 #define ALT_SPIS_ISR_RXUIS_E_ACT 0x1
2173 #define ALT_SPIS_ISR_RXUIS_LSB 2
2175 #define ALT_SPIS_ISR_RXUIS_MSB 2
2177 #define ALT_SPIS_ISR_RXUIS_WIDTH 1
2179 #define ALT_SPIS_ISR_RXUIS_SET_MSK 0x00000004
2181 #define ALT_SPIS_ISR_RXUIS_CLR_MSK 0xfffffffb
2183 #define ALT_SPIS_ISR_RXUIS_RESET 0x0
2185 #define ALT_SPIS_ISR_RXUIS_GET(value) (((value) & 0x00000004) >> 2)
2187 #define ALT_SPIS_ISR_RXUIS_SET(value) (((value) << 2) & 0x00000004)
2214 #define ALT_SPIS_ISR_RXOIS_E_INACT 0x0
2220 #define ALT_SPIS_ISR_RXOIS_E_ACT 0x1
2223 #define ALT_SPIS_ISR_RXOIS_LSB 3
2225 #define ALT_SPIS_ISR_RXOIS_MSB 3
2227 #define ALT_SPIS_ISR_RXOIS_WIDTH 1
2229 #define ALT_SPIS_ISR_RXOIS_SET_MSK 0x00000008
2231 #define ALT_SPIS_ISR_RXOIS_CLR_MSK 0xfffffff7
2233 #define ALT_SPIS_ISR_RXOIS_RESET 0x0
2235 #define ALT_SPIS_ISR_RXOIS_GET(value) (((value) & 0x00000008) >> 3)
2237 #define ALT_SPIS_ISR_RXOIS_SET(value) (((value) << 3) & 0x00000008)
2264 #define ALT_SPIS_ISR_RXFIS_E_INACT 0x0
2270 #define ALT_SPIS_ISR_RXFIS_E_ACT 0x1
2273 #define ALT_SPIS_ISR_RXFIS_LSB 4
2275 #define ALT_SPIS_ISR_RXFIS_MSB 4
2277 #define ALT_SPIS_ISR_RXFIS_WIDTH 1
2279 #define ALT_SPIS_ISR_RXFIS_SET_MSK 0x00000010
2281 #define ALT_SPIS_ISR_RXFIS_CLR_MSK 0xffffffef
2283 #define ALT_SPIS_ISR_RXFIS_RESET 0x0
2285 #define ALT_SPIS_ISR_RXFIS_GET(value) (((value) & 0x00000010) >> 4)
2287 #define ALT_SPIS_ISR_RXFIS_SET(value) (((value) << 4) & 0x00000010)
2289 #ifndef __ASSEMBLY__
2300 struct ALT_SPIS_ISR_s
2302 const uint32_t txeis : 1;
2303 const uint32_t txois : 1;
2304 const uint32_t rxuis : 1;
2305 const uint32_t rxois : 1;
2306 const uint32_t rxfis : 1;
2311 typedef volatile struct ALT_SPIS_ISR_s ALT_SPIS_ISR_t;
2315 #define ALT_SPIS_ISR_RESET 0x00000000
2317 #define ALT_SPIS_ISR_OFST 0x30
2319 #define ALT_SPIS_ISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_ISR_OFST))
2363 #define ALT_SPIS_RISR_TXEIR_E_INACT 0x0
2369 #define ALT_SPIS_RISR_TXEIR_E_ACT 0x1
2372 #define ALT_SPIS_RISR_TXEIR_LSB 0
2374 #define ALT_SPIS_RISR_TXEIR_MSB 0
2376 #define ALT_SPIS_RISR_TXEIR_WIDTH 1
2378 #define ALT_SPIS_RISR_TXEIR_SET_MSK 0x00000001
2380 #define ALT_SPIS_RISR_TXEIR_CLR_MSK 0xfffffffe
2382 #define ALT_SPIS_RISR_TXEIR_RESET 0x0
2384 #define ALT_SPIS_RISR_TXEIR_GET(value) (((value) & 0x00000001) >> 0)
2386 #define ALT_SPIS_RISR_TXEIR_SET(value) (((value) << 0) & 0x00000001)
2413 #define ALT_SPIS_RISR_TXOIR_E_INACT 0x0
2419 #define ALT_SPIS_RISR_TXOIR_E_ACT 0x1
2422 #define ALT_SPIS_RISR_TXOIR_LSB 1
2424 #define ALT_SPIS_RISR_TXOIR_MSB 1
2426 #define ALT_SPIS_RISR_TXOIR_WIDTH 1
2428 #define ALT_SPIS_RISR_TXOIR_SET_MSK 0x00000002
2430 #define ALT_SPIS_RISR_TXOIR_CLR_MSK 0xfffffffd
2432 #define ALT_SPIS_RISR_TXOIR_RESET 0x0
2434 #define ALT_SPIS_RISR_TXOIR_GET(value) (((value) & 0x00000002) >> 1)
2436 #define ALT_SPIS_RISR_TXOIR_SET(value) (((value) << 1) & 0x00000002)
2464 #define ALT_SPIS_RISR_RXUIR_E_INACT 0x0
2470 #define ALT_SPIS_RISR_RXUIR_E_ACT 0x1
2473 #define ALT_SPIS_RISR_RXUIR_LSB 2
2475 #define ALT_SPIS_RISR_RXUIR_MSB 2
2477 #define ALT_SPIS_RISR_RXUIR_WIDTH 1
2479 #define ALT_SPIS_RISR_RXUIR_SET_MSK 0x00000004
2481 #define ALT_SPIS_RISR_RXUIR_CLR_MSK 0xfffffffb
2483 #define ALT_SPIS_RISR_RXUIR_RESET 0x0
2485 #define ALT_SPIS_RISR_RXUIR_GET(value) (((value) & 0x00000004) >> 2)
2487 #define ALT_SPIS_RISR_RXUIR_SET(value) (((value) << 2) & 0x00000004)
2514 #define ALT_SPIS_RISR_RXOIR_E_INACT 0x0
2520 #define ALT_SPIS_RISR_RXOIR_E_ACT 0x1
2523 #define ALT_SPIS_RISR_RXOIR_LSB 3
2525 #define ALT_SPIS_RISR_RXOIR_MSB 3
2527 #define ALT_SPIS_RISR_RXOIR_WIDTH 1
2529 #define ALT_SPIS_RISR_RXOIR_SET_MSK 0x00000008
2531 #define ALT_SPIS_RISR_RXOIR_CLR_MSK 0xfffffff7
2533 #define ALT_SPIS_RISR_RXOIR_RESET 0x0
2535 #define ALT_SPIS_RISR_RXOIR_GET(value) (((value) & 0x00000008) >> 3)
2537 #define ALT_SPIS_RISR_RXOIR_SET(value) (((value) << 3) & 0x00000008)
2565 #define ALT_SPIS_RISR_RXFIR_E_INACT 0x0
2571 #define ALT_SPIS_RISR_RXFIR_E_ACT 0x1
2574 #define ALT_SPIS_RISR_RXFIR_LSB 4
2576 #define ALT_SPIS_RISR_RXFIR_MSB 4
2578 #define ALT_SPIS_RISR_RXFIR_WIDTH 1
2580 #define ALT_SPIS_RISR_RXFIR_SET_MSK 0x00000010
2582 #define ALT_SPIS_RISR_RXFIR_CLR_MSK 0xffffffef
2584 #define ALT_SPIS_RISR_RXFIR_RESET 0x0
2586 #define ALT_SPIS_RISR_RXFIR_GET(value) (((value) & 0x00000010) >> 4)
2588 #define ALT_SPIS_RISR_RXFIR_SET(value) (((value) << 4) & 0x00000010)
2590 #ifndef __ASSEMBLY__
2601 struct ALT_SPIS_RISR_s
2603 const uint32_t txeir : 1;
2604 const uint32_t txoir : 1;
2605 const uint32_t rxuir : 1;
2606 const uint32_t rxoir : 1;
2607 const uint32_t rxfir : 1;
2612 typedef volatile struct ALT_SPIS_RISR_s ALT_SPIS_RISR_t;
2616 #define ALT_SPIS_RISR_RESET 0x00000000
2618 #define ALT_SPIS_RISR_OFST 0x34
2620 #define ALT_SPIS_RISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RISR_OFST))
2648 #define ALT_SPIS_TXOICR_TXOICR_LSB 0
2650 #define ALT_SPIS_TXOICR_TXOICR_MSB 0
2652 #define ALT_SPIS_TXOICR_TXOICR_WIDTH 1
2654 #define ALT_SPIS_TXOICR_TXOICR_SET_MSK 0x00000001
2656 #define ALT_SPIS_TXOICR_TXOICR_CLR_MSK 0xfffffffe
2658 #define ALT_SPIS_TXOICR_TXOICR_RESET 0x0
2660 #define ALT_SPIS_TXOICR_TXOICR_GET(value) (((value) & 0x00000001) >> 0)
2662 #define ALT_SPIS_TXOICR_TXOICR_SET(value) (((value) << 0) & 0x00000001)
2664 #ifndef __ASSEMBLY__
2675 struct ALT_SPIS_TXOICR_s
2677 const uint32_t txoicr : 1;
2682 typedef volatile struct ALT_SPIS_TXOICR_s ALT_SPIS_TXOICR_t;
2686 #define ALT_SPIS_TXOICR_RESET 0x00000000
2688 #define ALT_SPIS_TXOICR_OFST 0x38
2690 #define ALT_SPIS_TXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXOICR_OFST))
2718 #define ALT_SPIS_RXOICR_RXOICR_LSB 0
2720 #define ALT_SPIS_RXOICR_RXOICR_MSB 0
2722 #define ALT_SPIS_RXOICR_RXOICR_WIDTH 1
2724 #define ALT_SPIS_RXOICR_RXOICR_SET_MSK 0x00000001
2726 #define ALT_SPIS_RXOICR_RXOICR_CLR_MSK 0xfffffffe
2728 #define ALT_SPIS_RXOICR_RXOICR_RESET 0x0
2730 #define ALT_SPIS_RXOICR_RXOICR_GET(value) (((value) & 0x00000001) >> 0)
2732 #define ALT_SPIS_RXOICR_RXOICR_SET(value) (((value) << 0) & 0x00000001)
2734 #ifndef __ASSEMBLY__
2745 struct ALT_SPIS_RXOICR_s
2747 const uint32_t rxoicr : 1;
2752 typedef volatile struct ALT_SPIS_RXOICR_s ALT_SPIS_RXOICR_t;
2756 #define ALT_SPIS_RXOICR_RESET 0x00000000
2758 #define ALT_SPIS_RXOICR_OFST 0x3c
2760 #define ALT_SPIS_RXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXOICR_OFST))
2788 #define ALT_SPIS_RXUICR_RXUICR_LSB 0
2790 #define ALT_SPIS_RXUICR_RXUICR_MSB 0
2792 #define ALT_SPIS_RXUICR_RXUICR_WIDTH 1
2794 #define ALT_SPIS_RXUICR_RXUICR_SET_MSK 0x00000001
2796 #define ALT_SPIS_RXUICR_RXUICR_CLR_MSK 0xfffffffe
2798 #define ALT_SPIS_RXUICR_RXUICR_RESET 0x0
2800 #define ALT_SPIS_RXUICR_RXUICR_GET(value) (((value) & 0x00000001) >> 0)
2802 #define ALT_SPIS_RXUICR_RXUICR_SET(value) (((value) << 0) & 0x00000001)
2804 #ifndef __ASSEMBLY__
2815 struct ALT_SPIS_RXUICR_s
2817 const uint32_t rxuicr : 1;
2822 typedef volatile struct ALT_SPIS_RXUICR_s ALT_SPIS_RXUICR_t;
2826 #define ALT_SPIS_RXUICR_RESET 0x00000000
2828 #define ALT_SPIS_RXUICR_OFST 0x40
2830 #define ALT_SPIS_RXUICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXUICR_OFST))
2858 #define ALT_SPIS_MSTICR_MSTICR_LSB 0
2860 #define ALT_SPIS_MSTICR_MSTICR_MSB 0
2862 #define ALT_SPIS_MSTICR_MSTICR_WIDTH 1
2864 #define ALT_SPIS_MSTICR_MSTICR_SET_MSK 0x00000001
2866 #define ALT_SPIS_MSTICR_MSTICR_CLR_MSK 0xfffffffe
2868 #define ALT_SPIS_MSTICR_MSTICR_RESET 0x0
2870 #define ALT_SPIS_MSTICR_MSTICR_GET(value) (((value) & 0x00000001) >> 0)
2872 #define ALT_SPIS_MSTICR_MSTICR_SET(value) (((value) << 0) & 0x00000001)
2874 #ifndef __ASSEMBLY__
2885 struct ALT_SPIS_MSTICR_s
2887 const uint32_t msticr : 1;
2892 typedef volatile struct ALT_SPIS_MSTICR_s ALT_SPIS_MSTICR_t;
2896 #define ALT_SPIS_MSTICR_RESET 0x00000000
2898 #define ALT_SPIS_MSTICR_OFST 0x44
2900 #define ALT_SPIS_MSTICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_MSTICR_OFST))
2930 #define ALT_SPIS_ICR_ICR_LSB 0
2932 #define ALT_SPIS_ICR_ICR_MSB 0
2934 #define ALT_SPIS_ICR_ICR_WIDTH 1
2936 #define ALT_SPIS_ICR_ICR_SET_MSK 0x00000001
2938 #define ALT_SPIS_ICR_ICR_CLR_MSK 0xfffffffe
2940 #define ALT_SPIS_ICR_ICR_RESET 0x0
2942 #define ALT_SPIS_ICR_ICR_GET(value) (((value) & 0x00000001) >> 0)
2944 #define ALT_SPIS_ICR_ICR_SET(value) (((value) << 0) & 0x00000001)
2946 #ifndef __ASSEMBLY__
2957 struct ALT_SPIS_ICR_s
2959 const uint32_t icr : 1;
2964 typedef volatile struct ALT_SPIS_ICR_s ALT_SPIS_ICR_t;
2968 #define ALT_SPIS_ICR_RESET 0x00000000
2970 #define ALT_SPIS_ICR_OFST 0x48
2972 #define ALT_SPIS_ICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_ICR_OFST))
3026 #define ALT_SPIS_DMACR_RDMAE_E_DISD 0x0
3032 #define ALT_SPIS_DMACR_RDMAE_E_END 0x1
3035 #define ALT_SPIS_DMACR_RDMAE_LSB 0
3037 #define ALT_SPIS_DMACR_RDMAE_MSB 0
3039 #define ALT_SPIS_DMACR_RDMAE_WIDTH 1
3041 #define ALT_SPIS_DMACR_RDMAE_SET_MSK 0x00000001
3043 #define ALT_SPIS_DMACR_RDMAE_CLR_MSK 0xfffffffe
3045 #define ALT_SPIS_DMACR_RDMAE_RESET 0x0
3047 #define ALT_SPIS_DMACR_RDMAE_GET(value) (((value) & 0x00000001) >> 0)
3049 #define ALT_SPIS_DMACR_RDMAE_SET(value) (((value) << 0) & 0x00000001)
3077 #define ALT_SPIS_DMACR_TDMAE_E_DISD 0x0
3083 #define ALT_SPIS_DMACR_TDMAE_E_END 0x1
3086 #define ALT_SPIS_DMACR_TDMAE_LSB 1
3088 #define ALT_SPIS_DMACR_TDMAE_MSB 1
3090 #define ALT_SPIS_DMACR_TDMAE_WIDTH 1
3092 #define ALT_SPIS_DMACR_TDMAE_SET_MSK 0x00000002
3094 #define ALT_SPIS_DMACR_TDMAE_CLR_MSK 0xfffffffd
3096 #define ALT_SPIS_DMACR_TDMAE_RESET 0x0
3098 #define ALT_SPIS_DMACR_TDMAE_GET(value) (((value) & 0x00000002) >> 1)
3100 #define ALT_SPIS_DMACR_TDMAE_SET(value) (((value) << 1) & 0x00000002)
3102 #ifndef __ASSEMBLY__
3113 struct ALT_SPIS_DMACR_s
3121 typedef volatile struct ALT_SPIS_DMACR_s ALT_SPIS_DMACR_t;
3125 #define ALT_SPIS_DMACR_RESET 0x00000000
3127 #define ALT_SPIS_DMACR_OFST 0x4c
3129 #define ALT_SPIS_DMACR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMACR_OFST))
3171 #define ALT_SPIS_DMATDLR_DMATDL_LSB 0
3173 #define ALT_SPIS_DMATDLR_DMATDL_MSB 7
3175 #define ALT_SPIS_DMATDLR_DMATDL_WIDTH 8
3177 #define ALT_SPIS_DMATDLR_DMATDL_SET_MSK 0x000000ff
3179 #define ALT_SPIS_DMATDLR_DMATDL_CLR_MSK 0xffffff00
3181 #define ALT_SPIS_DMATDLR_DMATDL_RESET 0x0
3183 #define ALT_SPIS_DMATDLR_DMATDL_GET(value) (((value) & 0x000000ff) >> 0)
3185 #define ALT_SPIS_DMATDLR_DMATDL_SET(value) (((value) << 0) & 0x000000ff)
3187 #ifndef __ASSEMBLY__
3198 struct ALT_SPIS_DMATDLR_s
3200 uint32_t dmatdl : 8;
3205 typedef volatile struct ALT_SPIS_DMATDLR_s ALT_SPIS_DMATDLR_t;
3209 #define ALT_SPIS_DMATDLR_RESET 0x00000000
3211 #define ALT_SPIS_DMATDLR_OFST 0x50
3213 #define ALT_SPIS_DMATDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMATDLR_OFST))
3253 #define ALT_SPIS_DMARDLR_DMARDL_LSB 0
3255 #define ALT_SPIS_DMARDLR_DMARDL_MSB 7
3257 #define ALT_SPIS_DMARDLR_DMARDL_WIDTH 8
3259 #define ALT_SPIS_DMARDLR_DMARDL_SET_MSK 0x000000ff
3261 #define ALT_SPIS_DMARDLR_DMARDL_CLR_MSK 0xffffff00
3263 #define ALT_SPIS_DMARDLR_DMARDL_RESET 0x0
3265 #define ALT_SPIS_DMARDLR_DMARDL_GET(value) (((value) & 0x000000ff) >> 0)
3267 #define ALT_SPIS_DMARDLR_DMARDL_SET(value) (((value) << 0) & 0x000000ff)
3269 #ifndef __ASSEMBLY__
3280 struct ALT_SPIS_DMARDLR_s
3282 uint32_t dmardl : 8;
3287 typedef volatile struct ALT_SPIS_DMARDLR_s ALT_SPIS_DMARDLR_t;
3291 #define ALT_SPIS_DMARDLR_RESET 0x00000000
3293 #define ALT_SPIS_DMARDLR_OFST 0x54
3295 #define ALT_SPIS_DMARDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMARDLR_OFST))
3322 #define ALT_SPIS_IDR_IDR_LSB 0
3324 #define ALT_SPIS_IDR_IDR_MSB 31
3326 #define ALT_SPIS_IDR_IDR_WIDTH 32
3328 #define ALT_SPIS_IDR_IDR_SET_MSK 0xffffffff
3330 #define ALT_SPIS_IDR_IDR_CLR_MSK 0x00000000
3332 #define ALT_SPIS_IDR_IDR_RESET 0x5510005
3334 #define ALT_SPIS_IDR_IDR_GET(value) (((value) & 0xffffffff) >> 0)
3336 #define ALT_SPIS_IDR_IDR_SET(value) (((value) << 0) & 0xffffffff)
3338 #ifndef __ASSEMBLY__
3349 struct ALT_SPIS_IDR_s
3351 const uint32_t idr : 32;
3355 typedef volatile struct ALT_SPIS_IDR_s ALT_SPIS_IDR_t;
3359 #define ALT_SPIS_IDR_RESET 0x05510005
3361 #define ALT_SPIS_IDR_OFST 0x58
3363 #define ALT_SPIS_IDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_IDR_OFST))
3387 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_LSB 0
3389 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_MSB 31
3391 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_WIDTH 32
3393 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_SET_MSK 0xffffffff
3395 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_CLR_MSK 0x00000000
3397 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_RESET 0x3332322a
3399 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_GET(value) (((value) & 0xffffffff) >> 0)
3401 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_SET(value) (((value) << 0) & 0xffffffff)
3403 #ifndef __ASSEMBLY__
3414 struct ALT_SPIS_SPI_VER_ID_s
3416 uint32_t spi_version_id : 32;
3420 typedef volatile struct ALT_SPIS_SPI_VER_ID_s ALT_SPIS_SPI_VER_ID_t;
3424 #define ALT_SPIS_SPI_VER_ID_RESET 0x3332322a
3426 #define ALT_SPIS_SPI_VER_ID_OFST 0x5c
3428 #define ALT_SPIS_SPI_VER_ID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SPI_VER_ID_OFST))
3468 #define ALT_SPIS_DR_DR_LSB 0
3470 #define ALT_SPIS_DR_DR_MSB 15
3472 #define ALT_SPIS_DR_DR_WIDTH 16
3474 #define ALT_SPIS_DR_DR_SET_MSK 0x0000ffff
3476 #define ALT_SPIS_DR_DR_CLR_MSK 0xffff0000
3478 #define ALT_SPIS_DR_DR_RESET 0x0
3480 #define ALT_SPIS_DR_DR_GET(value) (((value) & 0x0000ffff) >> 0)
3482 #define ALT_SPIS_DR_DR_SET(value) (((value) << 0) & 0x0000ffff)
3484 #ifndef __ASSEMBLY__
3495 struct ALT_SPIS_DR_s
3502 typedef volatile struct ALT_SPIS_DR_s ALT_SPIS_DR_t;
3506 #define ALT_SPIS_DR_RESET 0x00000000
3508 #define ALT_SPIS_DR_OFST 0x60
3510 #define ALT_SPIS_DR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR_OFST))
3512 #ifndef __ASSEMBLY__
3525 ALT_SPIS_CTLR0_t ctrlr0;
3526 volatile uint32_t _pad_0x4_0x7;
3527 ALT_SPIS_SPIENR_t spienr;
3528 ALT_SPIS_MWCR_t mwcr;
3529 volatile uint32_t _pad_0x10_0x17[2];
3530 ALT_SPIS_TXFTLR_t txftlr;
3531 ALT_SPIS_RXFTLR_t rxftlr;
3532 ALT_SPIS_TXFLR_t txflr;
3533 ALT_SPIS_RXFLR_t rxflr;
3537 ALT_SPIS_RISR_t risr;
3538 ALT_SPIS_TXOICR_t txoicr;
3539 ALT_SPIS_RXOICR_t rxoicr;
3540 ALT_SPIS_RXUICR_t rxuicr;
3541 ALT_SPIS_MSTICR_t msticr;
3543 ALT_SPIS_DMACR_t dmacr;
3544 ALT_SPIS_DMATDLR_t dmatdlr;
3545 ALT_SPIS_DMARDLR_t dmardlr;
3547 ALT_SPIS_SPI_VER_ID_t spi_version_id;
3549 volatile uint32_t _pad_0x64_0x80[7];
3553 typedef volatile struct ALT_SPIS_s ALT_SPIS_t;
3555 struct ALT_SPIS_raw_s
3557 volatile uint32_t ctrlr0;
3558 uint32_t _pad_0x4_0x7;
3559 volatile uint32_t spienr;
3560 volatile uint32_t mwcr;
3561 uint32_t _pad_0x10_0x17[2];
3562 volatile uint32_t txftlr;
3563 volatile uint32_t rxftlr;
3564 volatile uint32_t txflr;
3565 volatile uint32_t rxflr;
3566 volatile uint32_t sr;
3567 volatile uint32_t imr;
3568 volatile uint32_t isr;
3569 volatile uint32_t risr;
3570 volatile uint32_t txoicr;
3571 volatile uint32_t rxoicr;
3572 volatile uint32_t rxuicr;
3573 volatile uint32_t msticr;
3574 volatile uint32_t icr;
3575 volatile uint32_t dmacr;
3576 volatile uint32_t dmatdlr;
3577 volatile uint32_t dmardlr;
3578 volatile uint32_t idr;
3579 volatile uint32_t spi_version_id;
3580 volatile uint32_t dr;
3581 uint32_t _pad_0x64_0x80[7];
3585 typedef volatile struct ALT_SPIS_raw_s ALT_SPIS_raw_t;