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alt_pinmux.h
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32 
33 /* Altera - ALT_PINMUX_SHARED_3V_IO_GRP */
34 
35 #ifndef __ALT_SOCAL_PINMUX_H__
36 #define __ALT_SOCAL_PINMUX_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_PINMUX_SHARED_3V_IO_GRP
50  *
51  */
52 /*
53  * Register : Shared IO 48 Q1 1 Mux Selection Register - pinmux_shared_io_q1_1
54  *
55  * This register is used to control the peripherals connected to shared IO48 pin Q1
56  * 1
57  *
58  * Only reset by a cold reset (ignores warm reset).
59  *
60  * NOTE: These registers should not be modified after IO configuration.There is no
61  * support for dynamically changing the Pin Mux selections.
62  *
63  * Register Layout
64  *
65  * Bits | Access | Reset | Description
66  * :-------|:-------|:------|:-------------------------------------
67  * [3:0] | RW | 0xf | Shared IO48 Q1 1 Mux Selection Field
68  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q1_1_RSVD
69  *
70  */
71 /*
72  * Field : Shared IO48 Q1 1 Mux Selection Field - sel
73  *
74  * Select peripheral signals connected shared IO48 Q1 1
75  *
76  * 0000 (0) Pin is connected to Peripheral signal not applicable
77  *
78  * 0001 (1) Pin is connected to Peripheral signal not applicable
79  *
80  * 0010 (2) Pin is connected to Peripheral signal spis0.clk
81  *
82  * 0011 (3) Pin is connected to Peripheral signal spim0.ss1_n
83  *
84  * 0100 (4) Pin is connected to Peripheral signal sdmmc.data0
85  *
86  * 0101 (5) Pin is connected to Peripheral signal not applicable
87  *
88  * 0110 (6) Pin is connected to Peripheral signal not applicable
89  *
90  * 0111 (7) Pin is connected to Peripheral signal not applicable
91  *
92  * 1000 (8) Pin is connected to Peripheral signal usb0.clk
93  *
94  * 1001 (9) Pin is connected to Peripheral signal not applicable
95  *
96  * 1010 (10) Pin is connected to Peripheral signal not applicable
97  *
98  * 1011 (11) Pin is connected to Peripheral signal not applicable
99  *
100  * 1100 (12) Pin is connected to Peripheral signal not applicable
101  *
102  * 1101 (13) Pin is connected to Peripheral signal uart0.cts_n
103  *
104  * 1110 (14) Pin is connected to Peripheral signal nand.adq0
105  *
106  * 1111 (15) Pin is connected to Peripheral signal gpio0.io0
107  *
108  * Field Access Macros:
109  *
110  */
111 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_1_SEL register field. */
112 #define ALT_PINMUX_SHARED_3V_IO_Q1_1_SEL_LSB 0
113 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_1_SEL register field. */
114 #define ALT_PINMUX_SHARED_3V_IO_Q1_1_SEL_MSB 3
115 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_1_SEL register field. */
116 #define ALT_PINMUX_SHARED_3V_IO_Q1_1_SEL_WIDTH 4
117 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_1_SEL register field value. */
118 #define ALT_PINMUX_SHARED_3V_IO_Q1_1_SEL_SET_MSK 0x0000000f
119 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_1_SEL register field value. */
120 #define ALT_PINMUX_SHARED_3V_IO_Q1_1_SEL_CLR_MSK 0xfffffff0
121 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_1_SEL register field. */
122 #define ALT_PINMUX_SHARED_3V_IO_Q1_1_SEL_RESET 0xf
123 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_1_SEL field value from a register. */
124 #define ALT_PINMUX_SHARED_3V_IO_Q1_1_SEL_GET(value) (((value) & 0x0000000f) >> 0)
125 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_1_SEL register field value suitable for setting the register. */
126 #define ALT_PINMUX_SHARED_3V_IO_Q1_1_SEL_SET(value) (((value) << 0) & 0x0000000f)
127 
128 /*
129  * Field : Reserved
130  *
131  * Reserved
132  *
133  * Field Access Macros:
134  *
135  */
136 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_1_RSVD register field. */
137 #define ALT_PINMUX_SHARED_3V_IO_Q1_1_RSVD_LSB 4
138 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_1_RSVD register field. */
139 #define ALT_PINMUX_SHARED_3V_IO_Q1_1_RSVD_MSB 31
140 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_1_RSVD register field. */
141 #define ALT_PINMUX_SHARED_3V_IO_Q1_1_RSVD_WIDTH 28
142 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_1_RSVD register field value. */
143 #define ALT_PINMUX_SHARED_3V_IO_Q1_1_RSVD_SET_MSK 0xfffffff0
144 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_1_RSVD register field value. */
145 #define ALT_PINMUX_SHARED_3V_IO_Q1_1_RSVD_CLR_MSK 0x0000000f
146 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_1_RSVD register field. */
147 #define ALT_PINMUX_SHARED_3V_IO_Q1_1_RSVD_RESET 0x0
148 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_1_RSVD field value from a register. */
149 #define ALT_PINMUX_SHARED_3V_IO_Q1_1_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
150 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_1_RSVD register field value suitable for setting the register. */
151 #define ALT_PINMUX_SHARED_3V_IO_Q1_1_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
152 
153 #ifndef __ASSEMBLY__
154 /*
155  * WARNING: The C register and register group struct declarations are provided for
156  * convenience and illustrative purposes. They should, however, be used with
157  * caution as the C language standard provides no guarantees about the alignment or
158  * atomicity of device memory accesses. The recommended practice for writing
159  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
160  * alt_write_word() functions.
161  *
162  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_1.
163  */
164 struct ALT_PINMUX_SHARED_3V_IO_Q1_1_s
165 {
166  uint32_t sel : 4; /* Shared IO48 Q1 1 Mux Selection Field */
167  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q1_1_RSVD */
168 };
169 
170 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_1. */
171 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q1_1_s ALT_PINMUX_SHARED_3V_IO_Q1_1_t;
172 #endif /* __ASSEMBLY__ */
173 
174 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_1 register. */
175 #define ALT_PINMUX_SHARED_3V_IO_Q1_1_RESET 0x0000000f
176 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q1_1 register from the beginning of the component. */
177 #define ALT_PINMUX_SHARED_3V_IO_Q1_1_OFST 0x0
178 
179 /*
180  * Register : Shared IO 48 Q1 2 Mux Selection Register - pinmux_shared_io_q1_2
181  *
182  * This register is used to control the peripherals connected to shared IO48 pin Q1
183  * 2
184  *
185  * Only reset by a cold reset (ignores warm reset).
186  *
187  * NOTE: These registers should not be modified after IO configuration.There is no
188  * support for dynamically changing the Pin Mux selections.
189  *
190  * Register Layout
191  *
192  * Bits | Access | Reset | Description
193  * :-------|:-------|:------|:-------------------------------------
194  * [3:0] | RW | 0xf | Shared IO48 Q1 2 Mux Selection Field
195  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q1_2_RSVD
196  *
197  */
198 /*
199  * Field : Shared IO48 Q1 2 Mux Selection Field - sel
200  *
201  * Select peripheral signals connected shared IO48 Q1 2
202  *
203  * 0000 (0) Pin is connected to Peripheral signal not applicable
204  *
205  * 0001 (1) Pin is connected to Peripheral signal not applicable
206  *
207  * 0010 (2) Pin is connected to Peripheral signal spis0.mosi
208  *
209  * 0011 (3) Pin is connected to Peripheral signal spim1.ss1_n
210  *
211  * 0100 (4) Pin is connected to Peripheral signal sdmmc.cmd
212  *
213  * 0101 (5) Pin is connected to Peripheral signal not applicable
214  *
215  * 0110 (6) Pin is connected to Peripheral signal not applicable
216  *
217  * 0111 (7) Pin is connected to Peripheral signal not applicable
218  *
219  * 1000 (8) Pin is connected to Peripheral signal usb0.stp
220  *
221  * 1001 (9) Pin is connected to Peripheral signal not applicable
222  *
223  * 1010 (10) Pin is connected to Peripheral signal not applicable
224  *
225  * 1011 (11) Pin is connected to Peripheral signal not applicable
226  *
227  * 1100 (12) Pin is connected to Peripheral signal not applicable
228  *
229  * 1101 (13) Pin is connected to Peripheral signal uart0.rts_n
230  *
231  * 1110 (14) Pin is connected to Peripheral signal nand.adq1
232  *
233  * 1111 (15) Pin is connected to Peripheral signal gpio0.io1
234  *
235  * Field Access Macros:
236  *
237  */
238 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_2_SEL register field. */
239 #define ALT_PINMUX_SHARED_3V_IO_Q1_2_SEL_LSB 0
240 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_2_SEL register field. */
241 #define ALT_PINMUX_SHARED_3V_IO_Q1_2_SEL_MSB 3
242 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_2_SEL register field. */
243 #define ALT_PINMUX_SHARED_3V_IO_Q1_2_SEL_WIDTH 4
244 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_2_SEL register field value. */
245 #define ALT_PINMUX_SHARED_3V_IO_Q1_2_SEL_SET_MSK 0x0000000f
246 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_2_SEL register field value. */
247 #define ALT_PINMUX_SHARED_3V_IO_Q1_2_SEL_CLR_MSK 0xfffffff0
248 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_2_SEL register field. */
249 #define ALT_PINMUX_SHARED_3V_IO_Q1_2_SEL_RESET 0xf
250 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_2_SEL field value from a register. */
251 #define ALT_PINMUX_SHARED_3V_IO_Q1_2_SEL_GET(value) (((value) & 0x0000000f) >> 0)
252 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_2_SEL register field value suitable for setting the register. */
253 #define ALT_PINMUX_SHARED_3V_IO_Q1_2_SEL_SET(value) (((value) << 0) & 0x0000000f)
254 
255 /*
256  * Field : Reserved
257  *
258  * Reserved
259  *
260  * Field Access Macros:
261  *
262  */
263 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_2_RSVD register field. */
264 #define ALT_PINMUX_SHARED_3V_IO_Q1_2_RSVD_LSB 4
265 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_2_RSVD register field. */
266 #define ALT_PINMUX_SHARED_3V_IO_Q1_2_RSVD_MSB 31
267 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_2_RSVD register field. */
268 #define ALT_PINMUX_SHARED_3V_IO_Q1_2_RSVD_WIDTH 28
269 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_2_RSVD register field value. */
270 #define ALT_PINMUX_SHARED_3V_IO_Q1_2_RSVD_SET_MSK 0xfffffff0
271 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_2_RSVD register field value. */
272 #define ALT_PINMUX_SHARED_3V_IO_Q1_2_RSVD_CLR_MSK 0x0000000f
273 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_2_RSVD register field. */
274 #define ALT_PINMUX_SHARED_3V_IO_Q1_2_RSVD_RESET 0x0
275 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_2_RSVD field value from a register. */
276 #define ALT_PINMUX_SHARED_3V_IO_Q1_2_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
277 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_2_RSVD register field value suitable for setting the register. */
278 #define ALT_PINMUX_SHARED_3V_IO_Q1_2_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
279 
280 #ifndef __ASSEMBLY__
281 /*
282  * WARNING: The C register and register group struct declarations are provided for
283  * convenience and illustrative purposes. They should, however, be used with
284  * caution as the C language standard provides no guarantees about the alignment or
285  * atomicity of device memory accesses. The recommended practice for writing
286  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
287  * alt_write_word() functions.
288  *
289  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_2.
290  */
291 struct ALT_PINMUX_SHARED_3V_IO_Q1_2_s
292 {
293  uint32_t sel : 4; /* Shared IO48 Q1 2 Mux Selection Field */
294  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q1_2_RSVD */
295 };
296 
297 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_2. */
298 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q1_2_s ALT_PINMUX_SHARED_3V_IO_Q1_2_t;
299 #endif /* __ASSEMBLY__ */
300 
301 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_2 register. */
302 #define ALT_PINMUX_SHARED_3V_IO_Q1_2_RESET 0x0000000f
303 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q1_2 register from the beginning of the component. */
304 #define ALT_PINMUX_SHARED_3V_IO_Q1_2_OFST 0x4
305 
306 /*
307  * Register : Shared IO 48 Q1 3 Mux Selection Register - pinmux_shared_io_q1_3
308  *
309  * This register is used to control the peripherals connected to shared IO48 pin Q1
310  * 3
311  *
312  * Only reset by a cold reset (ignores warm reset).
313  *
314  * NOTE: These registers should not be modified after IO configuration.There is no
315  * support for dynamically changing the Pin Mux selections.
316  *
317  * Register Layout
318  *
319  * Bits | Access | Reset | Description
320  * :-------|:-------|:------|:-------------------------------------
321  * [3:0] | RW | 0xf | Shared IO48 Q1 3 Mux Selection Field
322  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q1_3_RSVD
323  *
324  */
325 /*
326  * Field : Shared IO48 Q1 3 Mux Selection Field - sel
327  *
328  * Select peripheral signals connected shared IO48 Q1 3
329  *
330  * 0000 (0) Pin is connected to Peripheral signal i2c1.sda
331  *
332  * 0001 (1) Pin is connected to Peripheral signal not applicable
333  *
334  * 0010 (2) Pin is connected to Peripheral signal spis0.ss0_n
335  *
336  * 0011 (3) Pin is connected to Peripheral signal not applicable
337  *
338  * 0100 (4) Pin is connected to Peripheral signal sdmmc.cclk
339  *
340  * 0101 (5) Pin is connected to Peripheral signal not applicable
341  *
342  * 0110 (6) Pin is connected to Peripheral signal not applicable
343  *
344  * 0111 (7) Pin is connected to Peripheral signal not applicable
345  *
346  * 1000 (8) Pin is connected to Peripheral signal usb0.dir
347  *
348  * 1001 (9) Pin is connected to Peripheral signal not applicable
349  *
350  * 1010 (10) Pin is connected to Peripheral signal not applicable
351  *
352  * 1011 (11) Pin is connected to Peripheral signal not applicable
353  *
354  * 1100 (12) Pin is connected to Peripheral signal not applicable
355  *
356  * 1101 (13) Pin is connected to Peripheral signal uart0.tx
357  *
358  * 1110 (14) Pin is connected to Peripheral signal nand.we_n
359  *
360  * 1111 (15) Pin is connected to Peripheral signal gpio0.io2
361  *
362  * Field Access Macros:
363  *
364  */
365 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_3_SEL register field. */
366 #define ALT_PINMUX_SHARED_3V_IO_Q1_3_SEL_LSB 0
367 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_3_SEL register field. */
368 #define ALT_PINMUX_SHARED_3V_IO_Q1_3_SEL_MSB 3
369 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_3_SEL register field. */
370 #define ALT_PINMUX_SHARED_3V_IO_Q1_3_SEL_WIDTH 4
371 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_3_SEL register field value. */
372 #define ALT_PINMUX_SHARED_3V_IO_Q1_3_SEL_SET_MSK 0x0000000f
373 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_3_SEL register field value. */
374 #define ALT_PINMUX_SHARED_3V_IO_Q1_3_SEL_CLR_MSK 0xfffffff0
375 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_3_SEL register field. */
376 #define ALT_PINMUX_SHARED_3V_IO_Q1_3_SEL_RESET 0xf
377 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_3_SEL field value from a register. */
378 #define ALT_PINMUX_SHARED_3V_IO_Q1_3_SEL_GET(value) (((value) & 0x0000000f) >> 0)
379 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_3_SEL register field value suitable for setting the register. */
380 #define ALT_PINMUX_SHARED_3V_IO_Q1_3_SEL_SET(value) (((value) << 0) & 0x0000000f)
381 
382 /*
383  * Field : Reserved
384  *
385  * Reserved
386  *
387  * Field Access Macros:
388  *
389  */
390 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_3_RSVD register field. */
391 #define ALT_PINMUX_SHARED_3V_IO_Q1_3_RSVD_LSB 4
392 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_3_RSVD register field. */
393 #define ALT_PINMUX_SHARED_3V_IO_Q1_3_RSVD_MSB 31
394 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_3_RSVD register field. */
395 #define ALT_PINMUX_SHARED_3V_IO_Q1_3_RSVD_WIDTH 28
396 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_3_RSVD register field value. */
397 #define ALT_PINMUX_SHARED_3V_IO_Q1_3_RSVD_SET_MSK 0xfffffff0
398 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_3_RSVD register field value. */
399 #define ALT_PINMUX_SHARED_3V_IO_Q1_3_RSVD_CLR_MSK 0x0000000f
400 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_3_RSVD register field. */
401 #define ALT_PINMUX_SHARED_3V_IO_Q1_3_RSVD_RESET 0x0
402 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_3_RSVD field value from a register. */
403 #define ALT_PINMUX_SHARED_3V_IO_Q1_3_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
404 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_3_RSVD register field value suitable for setting the register. */
405 #define ALT_PINMUX_SHARED_3V_IO_Q1_3_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
406 
407 #ifndef __ASSEMBLY__
408 /*
409  * WARNING: The C register and register group struct declarations are provided for
410  * convenience and illustrative purposes. They should, however, be used with
411  * caution as the C language standard provides no guarantees about the alignment or
412  * atomicity of device memory accesses. The recommended practice for writing
413  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
414  * alt_write_word() functions.
415  *
416  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_3.
417  */
418 struct ALT_PINMUX_SHARED_3V_IO_Q1_3_s
419 {
420  uint32_t sel : 4; /* Shared IO48 Q1 3 Mux Selection Field */
421  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q1_3_RSVD */
422 };
423 
424 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_3. */
425 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q1_3_s ALT_PINMUX_SHARED_3V_IO_Q1_3_t;
426 #endif /* __ASSEMBLY__ */
427 
428 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_3 register. */
429 #define ALT_PINMUX_SHARED_3V_IO_Q1_3_RESET 0x0000000f
430 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q1_3 register from the beginning of the component. */
431 #define ALT_PINMUX_SHARED_3V_IO_Q1_3_OFST 0x8
432 
433 /*
434  * Register : Shared IO 48 Q1 4 Mux Selection Register - pinmux_shared_io_q1_4
435  *
436  * This register is used to control the peripherals connected to shared IO48 pin Q1
437  * 4
438  *
439  * Only reset by a cold reset (ignores warm reset).
440  *
441  * NOTE: These registers should not be modified after IO configuration.There is no
442  * support for dynamically changing the Pin Mux selections.
443  *
444  * Register Layout
445  *
446  * Bits | Access | Reset | Description
447  * :-------|:-------|:------|:-------------------------------------
448  * [3:0] | RW | 0xf | Shared IO48 Q1 4 Mux Selection Field
449  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q1_4_RSVD
450  *
451  */
452 /*
453  * Field : Shared IO48 Q1 4 Mux Selection Field - sel
454  *
455  * Select peripheral signals connected shared IO48 Q1 4
456  *
457  * 0000 (0) Pin is connected to Peripheral signal i2c1.scl
458  *
459  * 0001 (1) Pin is connected to Peripheral signal not applicable
460  *
461  * 0010 (2) Pin is connected to Peripheral signal spis0.miso
462  *
463  * 0011 (3) Pin is connected to Peripheral signal not applicable
464  *
465  * 0100 (4) Pin is connected to Peripheral signal sdmmc.data1
466  *
467  * 0101 (5) Pin is connected to Peripheral signal not applicable
468  *
469  * 0110 (6) Pin is connected to Peripheral signal not applicable
470  *
471  * 0111 (7) Pin is connected to Peripheral signal not applicable
472  *
473  * 1000 (8) Pin is connected to Peripheral signal usb0.data0
474  *
475  * 1001 (9) Pin is connected to Peripheral signal not applicable
476  *
477  * 1010 (10) Pin is connected to Peripheral signal not applicable
478  *
479  * 1011 (11) Pin is connected to Peripheral signal not applicable
480  *
481  * 1100 (12) Pin is connected to Peripheral signal not applicable
482  *
483  * 1101 (13) Pin is connected to Peripheral signal uart0.rx
484  *
485  * 1110 (14) Pin is connected to Peripheral signal nand.re_n
486  *
487  * 1111 (15) Pin is connected to Peripheral signal gpio0.io3
488  *
489  * Field Access Macros:
490  *
491  */
492 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_4_SEL register field. */
493 #define ALT_PINMUX_SHARED_3V_IO_Q1_4_SEL_LSB 0
494 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_4_SEL register field. */
495 #define ALT_PINMUX_SHARED_3V_IO_Q1_4_SEL_MSB 3
496 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_4_SEL register field. */
497 #define ALT_PINMUX_SHARED_3V_IO_Q1_4_SEL_WIDTH 4
498 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_4_SEL register field value. */
499 #define ALT_PINMUX_SHARED_3V_IO_Q1_4_SEL_SET_MSK 0x0000000f
500 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_4_SEL register field value. */
501 #define ALT_PINMUX_SHARED_3V_IO_Q1_4_SEL_CLR_MSK 0xfffffff0
502 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_4_SEL register field. */
503 #define ALT_PINMUX_SHARED_3V_IO_Q1_4_SEL_RESET 0xf
504 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_4_SEL field value from a register. */
505 #define ALT_PINMUX_SHARED_3V_IO_Q1_4_SEL_GET(value) (((value) & 0x0000000f) >> 0)
506 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_4_SEL register field value suitable for setting the register. */
507 #define ALT_PINMUX_SHARED_3V_IO_Q1_4_SEL_SET(value) (((value) << 0) & 0x0000000f)
508 
509 /*
510  * Field : Reserved
511  *
512  * Reserved
513  *
514  * Field Access Macros:
515  *
516  */
517 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_4_RSVD register field. */
518 #define ALT_PINMUX_SHARED_3V_IO_Q1_4_RSVD_LSB 4
519 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_4_RSVD register field. */
520 #define ALT_PINMUX_SHARED_3V_IO_Q1_4_RSVD_MSB 31
521 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_4_RSVD register field. */
522 #define ALT_PINMUX_SHARED_3V_IO_Q1_4_RSVD_WIDTH 28
523 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_4_RSVD register field value. */
524 #define ALT_PINMUX_SHARED_3V_IO_Q1_4_RSVD_SET_MSK 0xfffffff0
525 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_4_RSVD register field value. */
526 #define ALT_PINMUX_SHARED_3V_IO_Q1_4_RSVD_CLR_MSK 0x0000000f
527 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_4_RSVD register field. */
528 #define ALT_PINMUX_SHARED_3V_IO_Q1_4_RSVD_RESET 0x0
529 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_4_RSVD field value from a register. */
530 #define ALT_PINMUX_SHARED_3V_IO_Q1_4_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
531 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_4_RSVD register field value suitable for setting the register. */
532 #define ALT_PINMUX_SHARED_3V_IO_Q1_4_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
533 
534 #ifndef __ASSEMBLY__
535 /*
536  * WARNING: The C register and register group struct declarations are provided for
537  * convenience and illustrative purposes. They should, however, be used with
538  * caution as the C language standard provides no guarantees about the alignment or
539  * atomicity of device memory accesses. The recommended practice for writing
540  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
541  * alt_write_word() functions.
542  *
543  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_4.
544  */
545 struct ALT_PINMUX_SHARED_3V_IO_Q1_4_s
546 {
547  uint32_t sel : 4; /* Shared IO48 Q1 4 Mux Selection Field */
548  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q1_4_RSVD */
549 };
550 
551 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_4. */
552 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q1_4_s ALT_PINMUX_SHARED_3V_IO_Q1_4_t;
553 #endif /* __ASSEMBLY__ */
554 
555 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_4 register. */
556 #define ALT_PINMUX_SHARED_3V_IO_Q1_4_RESET 0x0000000f
557 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q1_4 register from the beginning of the component. */
558 #define ALT_PINMUX_SHARED_3V_IO_Q1_4_OFST 0xc
559 
560 /*
561  * Register : Shared IO 48 Q1 5 Mux Selection Register - pinmux_shared_io_q1_5
562  *
563  * This register is used to control the peripherals connected to shared IO48 pin Q1
564  * 5
565  *
566  * Only reset by a cold reset (ignores warm reset).
567  *
568  * NOTE: These registers should not be modified after IO configuration.There is no
569  * support for dynamically changing the Pin Mux selections.
570  *
571  * Register Layout
572  *
573  * Bits | Access | Reset | Description
574  * :-------|:-------|:------|:-------------------------------------
575  * [3:0] | RW | 0xf | Shared IO48 Q1 5 Mux Selection Field
576  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q1_5_RSVD
577  *
578  */
579 /*
580  * Field : Shared IO48 Q1 5 Mux Selection Field - sel
581  *
582  * Select peripheral signals connected shared IO48 Q1 5
583  *
584  * 0000 (0) Pin is connected to Peripheral signal i2c0.sda
585  *
586  * 0001 (1) Pin is connected to Peripheral signal not applicable
587  *
588  * 0010 (2) Pin is connected to Peripheral signal not applicable
589  *
590  * 0011 (3) Pin is connected to Peripheral signal spim0.clk
591  *
592  * 0100 (4) Pin is connected to Peripheral signal sdmmc.data2
593  *
594  * 0101 (5) Pin is connected to Peripheral signal not applicable
595  *
596  * 0110 (6) Pin is connected to Peripheral signal not applicable
597  *
598  * 0111 (7) Pin is connected to Peripheral signal not applicable
599  *
600  * 1000 (8) Pin is connected to Peripheral signal usb0.data1
601  *
602  * 1001 (9) Pin is connected to Peripheral signal not applicable
603  *
604  * 1010 (10) Pin is connected to Peripheral signal not applicable
605  *
606  * 1011 (11) Pin is connected to Peripheral signal not applicable
607  *
608  * 1100 (12) Pin is connected to Peripheral signal qspi.ss2
609  *
610  * 1101 (13) Pin is connected to Peripheral signal uart1.cts_n
611  *
612  * 1110 (14) Pin is connected to Peripheral signal nand.wp_n
613  *
614  * 1111 (15) Pin is connected to Peripheral signal gpio0.io4
615  *
616  * Field Access Macros:
617  *
618  */
619 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_5_SEL register field. */
620 #define ALT_PINMUX_SHARED_3V_IO_Q1_5_SEL_LSB 0
621 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_5_SEL register field. */
622 #define ALT_PINMUX_SHARED_3V_IO_Q1_5_SEL_MSB 3
623 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_5_SEL register field. */
624 #define ALT_PINMUX_SHARED_3V_IO_Q1_5_SEL_WIDTH 4
625 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_5_SEL register field value. */
626 #define ALT_PINMUX_SHARED_3V_IO_Q1_5_SEL_SET_MSK 0x0000000f
627 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_5_SEL register field value. */
628 #define ALT_PINMUX_SHARED_3V_IO_Q1_5_SEL_CLR_MSK 0xfffffff0
629 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_5_SEL register field. */
630 #define ALT_PINMUX_SHARED_3V_IO_Q1_5_SEL_RESET 0xf
631 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_5_SEL field value from a register. */
632 #define ALT_PINMUX_SHARED_3V_IO_Q1_5_SEL_GET(value) (((value) & 0x0000000f) >> 0)
633 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_5_SEL register field value suitable for setting the register. */
634 #define ALT_PINMUX_SHARED_3V_IO_Q1_5_SEL_SET(value) (((value) << 0) & 0x0000000f)
635 
636 /*
637  * Field : Reserved
638  *
639  * Reserved
640  *
641  * Field Access Macros:
642  *
643  */
644 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_5_RSVD register field. */
645 #define ALT_PINMUX_SHARED_3V_IO_Q1_5_RSVD_LSB 4
646 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_5_RSVD register field. */
647 #define ALT_PINMUX_SHARED_3V_IO_Q1_5_RSVD_MSB 31
648 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_5_RSVD register field. */
649 #define ALT_PINMUX_SHARED_3V_IO_Q1_5_RSVD_WIDTH 28
650 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_5_RSVD register field value. */
651 #define ALT_PINMUX_SHARED_3V_IO_Q1_5_RSVD_SET_MSK 0xfffffff0
652 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_5_RSVD register field value. */
653 #define ALT_PINMUX_SHARED_3V_IO_Q1_5_RSVD_CLR_MSK 0x0000000f
654 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_5_RSVD register field. */
655 #define ALT_PINMUX_SHARED_3V_IO_Q1_5_RSVD_RESET 0x0
656 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_5_RSVD field value from a register. */
657 #define ALT_PINMUX_SHARED_3V_IO_Q1_5_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
658 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_5_RSVD register field value suitable for setting the register. */
659 #define ALT_PINMUX_SHARED_3V_IO_Q1_5_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
660 
661 #ifndef __ASSEMBLY__
662 /*
663  * WARNING: The C register and register group struct declarations are provided for
664  * convenience and illustrative purposes. They should, however, be used with
665  * caution as the C language standard provides no guarantees about the alignment or
666  * atomicity of device memory accesses. The recommended practice for writing
667  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
668  * alt_write_word() functions.
669  *
670  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_5.
671  */
672 struct ALT_PINMUX_SHARED_3V_IO_Q1_5_s
673 {
674  uint32_t sel : 4; /* Shared IO48 Q1 5 Mux Selection Field */
675  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q1_5_RSVD */
676 };
677 
678 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_5. */
679 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q1_5_s ALT_PINMUX_SHARED_3V_IO_Q1_5_t;
680 #endif /* __ASSEMBLY__ */
681 
682 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_5 register. */
683 #define ALT_PINMUX_SHARED_3V_IO_Q1_5_RESET 0x0000000f
684 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q1_5 register from the beginning of the component. */
685 #define ALT_PINMUX_SHARED_3V_IO_Q1_5_OFST 0x10
686 
687 /*
688  * Register : Shared IO 48 Q1 6 Mux Selection Register - pinmux_shared_io_q1_6
689  *
690  * This register is used to control the peripherals connected to shared IO48 pin Q1
691  * 6
692  *
693  * Only reset by a cold reset (ignores warm reset)
694  *
695  * .NOTE: These registers should not be modified after IO configuration.There is no
696  * support for dynamically changing the Pin Mux selections.
697  *
698  * Register Layout
699  *
700  * Bits | Access | Reset | Description
701  * :-------|:-------|:------|:-------------------------------------
702  * [3:0] | RW | 0xf | Shared IO48 Q1 6 Mux Selection Field
703  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q1_6_RSVD
704  *
705  */
706 /*
707  * Field : Shared IO48 Q1 6 Mux Selection Field - sel
708  *
709  * Select peripheral signals connected shared IO48 Q1 6
710  *
711  * 0000 (0) Pin is connected to Peripheral signal i2c0.scl
712  *
713  * 0001 (1) Pin is connected to Peripheral signal not applicable
714  *
715  * 0010 (2) Pin is connected to Peripheral signal not applicable
716  *
717  * 0011 (3) Pin is connected to Peripheral signal spim0.mosi
718  *
719  * 0100 (4) Pin is connected to Peripheral signal sdmmc.data3
720  *
721  * 0101 (5) Pin is connected to Peripheral signal not applicable
722  *
723  * 0110 (6) Pin is connected to Peripheral signal not applicable
724  *
725  * 0111 (7) Pin is connected to Peripheral signal not applicable
726  *
727  * 1000 (8) Pin is connected to Peripheral signal usb0.nxt
728  *
729  * 1001 (9) Pin is connected to Peripheral signal not applicable
730  *
731  * 1010 (10) Pin is connected to Peripheral signal not applicable
732  *
733  * 1011 (11) Pin is connected to Peripheral signal not applicable
734  *
735  * 1100 (12) Pin is connected to Peripheral signal qspi.ss3
736  *
737  * 1101 (13) Pin is connected to Peripheral signal uart1.rts_n
738  *
739  * 1110 (14) Pin is connected to Peripheral signal nand.adq2
740  *
741  * 1111 (15) Pin is connected to Peripheral signal gpio0.io5
742  *
743  * Field Access Macros:
744  *
745  */
746 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_6_SEL register field. */
747 #define ALT_PINMUX_SHARED_3V_IO_Q1_6_SEL_LSB 0
748 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_6_SEL register field. */
749 #define ALT_PINMUX_SHARED_3V_IO_Q1_6_SEL_MSB 3
750 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_6_SEL register field. */
751 #define ALT_PINMUX_SHARED_3V_IO_Q1_6_SEL_WIDTH 4
752 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_6_SEL register field value. */
753 #define ALT_PINMUX_SHARED_3V_IO_Q1_6_SEL_SET_MSK 0x0000000f
754 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_6_SEL register field value. */
755 #define ALT_PINMUX_SHARED_3V_IO_Q1_6_SEL_CLR_MSK 0xfffffff0
756 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_6_SEL register field. */
757 #define ALT_PINMUX_SHARED_3V_IO_Q1_6_SEL_RESET 0xf
758 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_6_SEL field value from a register. */
759 #define ALT_PINMUX_SHARED_3V_IO_Q1_6_SEL_GET(value) (((value) & 0x0000000f) >> 0)
760 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_6_SEL register field value suitable for setting the register. */
761 #define ALT_PINMUX_SHARED_3V_IO_Q1_6_SEL_SET(value) (((value) << 0) & 0x0000000f)
762 
763 /*
764  * Field : Reserved
765  *
766  * Reserved
767  *
768  * Field Access Macros:
769  *
770  */
771 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_6_RSVD register field. */
772 #define ALT_PINMUX_SHARED_3V_IO_Q1_6_RSVD_LSB 4
773 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_6_RSVD register field. */
774 #define ALT_PINMUX_SHARED_3V_IO_Q1_6_RSVD_MSB 31
775 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_6_RSVD register field. */
776 #define ALT_PINMUX_SHARED_3V_IO_Q1_6_RSVD_WIDTH 28
777 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_6_RSVD register field value. */
778 #define ALT_PINMUX_SHARED_3V_IO_Q1_6_RSVD_SET_MSK 0xfffffff0
779 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_6_RSVD register field value. */
780 #define ALT_PINMUX_SHARED_3V_IO_Q1_6_RSVD_CLR_MSK 0x0000000f
781 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_6_RSVD register field. */
782 #define ALT_PINMUX_SHARED_3V_IO_Q1_6_RSVD_RESET 0x0
783 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_6_RSVD field value from a register. */
784 #define ALT_PINMUX_SHARED_3V_IO_Q1_6_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
785 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_6_RSVD register field value suitable for setting the register. */
786 #define ALT_PINMUX_SHARED_3V_IO_Q1_6_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
787 
788 #ifndef __ASSEMBLY__
789 /*
790  * WARNING: The C register and register group struct declarations are provided for
791  * convenience and illustrative purposes. They should, however, be used with
792  * caution as the C language standard provides no guarantees about the alignment or
793  * atomicity of device memory accesses. The recommended practice for writing
794  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
795  * alt_write_word() functions.
796  *
797  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_6.
798  */
799 struct ALT_PINMUX_SHARED_3V_IO_Q1_6_s
800 {
801  uint32_t sel : 4; /* Shared IO48 Q1 6 Mux Selection Field */
802  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q1_6_RSVD */
803 };
804 
805 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_6. */
806 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q1_6_s ALT_PINMUX_SHARED_3V_IO_Q1_6_t;
807 #endif /* __ASSEMBLY__ */
808 
809 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_6 register. */
810 #define ALT_PINMUX_SHARED_3V_IO_Q1_6_RESET 0x0000000f
811 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q1_6 register from the beginning of the component. */
812 #define ALT_PINMUX_SHARED_3V_IO_Q1_6_OFST 0x14
813 
814 /*
815  * Register : Shared IO 48 Q1 7 Mux Selection Register - pinmux_shared_io_q1_7
816  *
817  * This register is used to control the peripherals connected to shared IO48 pin Q1
818  * 7
819  *
820  * Only reset by a cold reset (ignores warm reset).
821  *
822  * NOTE: These registers should not be modified after IO configuration.There is no
823  * support for dynamically changing the Pin Mux selections.
824  *
825  * Register Layout
826  *
827  * Bits | Access | Reset | Description
828  * :-------|:-------|:------|:-------------------------------------
829  * [3:0] | RW | 0xf | Shared IO48 Q1 7 Mux Selection Field
830  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q1_7_RSVD
831  *
832  */
833 /*
834  * Field : Shared IO48 Q1 7 Mux Selection Field - sel
835  *
836  * Select peripheral signals connected shared IO48 Q1 7
837  *
838  * 0000 (0) Pin is connected to Peripheral signal i2c_emac2.sda
839  *
840  * 0001 (1) Pin is connected to Peripheral signal emac2.mdio
841  *
842  * 0010 (2) Pin is connected to Peripheral signal not applicable
843  *
844  * 0011 (3) Pin is connected to Peripheral signal spim0.miso
845  *
846  * 0100 (4) Pin is connected to Peripheral signal sdmmc.data4
847  *
848  * 0101 (5) Pin is connected to Peripheral signal not applicable
849  *
850  * 0110 (6) Pin is connected to Peripheral signal not applicable
851  *
852  * 0111 (7) Pin is connected to Peripheral signal not applicable
853  *
854  * 1000 (8) Pin is connected to Peripheral signal usb0.data2
855  *
856  * 1001 (9) Pin is connected to Peripheral signal not applicable
857  *
858  * 1010 (10) Pin is connected to Peripheral signal not applicable
859  *
860  * 1011 (11) Pin is connected to Peripheral signal not applicable
861  *
862  * 1100 (12) Pin is connected to Peripheral signal not applicable
863  *
864  * 1101 (13) Pin is connected to Peripheral signal uart1.tx
865  *
866  * 1110 (14) Pin is connected to Peripheral signal nand.adq3
867  *
868  * 1111 (15) Pin is connected to Peripheral signal gpio0.io6
869  *
870  * Field Access Macros:
871  *
872  */
873 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_7_SEL register field. */
874 #define ALT_PINMUX_SHARED_3V_IO_Q1_7_SEL_LSB 0
875 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_7_SEL register field. */
876 #define ALT_PINMUX_SHARED_3V_IO_Q1_7_SEL_MSB 3
877 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_7_SEL register field. */
878 #define ALT_PINMUX_SHARED_3V_IO_Q1_7_SEL_WIDTH 4
879 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_7_SEL register field value. */
880 #define ALT_PINMUX_SHARED_3V_IO_Q1_7_SEL_SET_MSK 0x0000000f
881 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_7_SEL register field value. */
882 #define ALT_PINMUX_SHARED_3V_IO_Q1_7_SEL_CLR_MSK 0xfffffff0
883 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_7_SEL register field. */
884 #define ALT_PINMUX_SHARED_3V_IO_Q1_7_SEL_RESET 0xf
885 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_7_SEL field value from a register. */
886 #define ALT_PINMUX_SHARED_3V_IO_Q1_7_SEL_GET(value) (((value) & 0x0000000f) >> 0)
887 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_7_SEL register field value suitable for setting the register. */
888 #define ALT_PINMUX_SHARED_3V_IO_Q1_7_SEL_SET(value) (((value) << 0) & 0x0000000f)
889 
890 /*
891  * Field : Reserved
892  *
893  * Reserved
894  *
895  * Field Access Macros:
896  *
897  */
898 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_7_RSVD register field. */
899 #define ALT_PINMUX_SHARED_3V_IO_Q1_7_RSVD_LSB 4
900 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_7_RSVD register field. */
901 #define ALT_PINMUX_SHARED_3V_IO_Q1_7_RSVD_MSB 31
902 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_7_RSVD register field. */
903 #define ALT_PINMUX_SHARED_3V_IO_Q1_7_RSVD_WIDTH 28
904 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_7_RSVD register field value. */
905 #define ALT_PINMUX_SHARED_3V_IO_Q1_7_RSVD_SET_MSK 0xfffffff0
906 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_7_RSVD register field value. */
907 #define ALT_PINMUX_SHARED_3V_IO_Q1_7_RSVD_CLR_MSK 0x0000000f
908 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_7_RSVD register field. */
909 #define ALT_PINMUX_SHARED_3V_IO_Q1_7_RSVD_RESET 0x0
910 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_7_RSVD field value from a register. */
911 #define ALT_PINMUX_SHARED_3V_IO_Q1_7_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
912 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_7_RSVD register field value suitable for setting the register. */
913 #define ALT_PINMUX_SHARED_3V_IO_Q1_7_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
914 
915 #ifndef __ASSEMBLY__
916 /*
917  * WARNING: The C register and register group struct declarations are provided for
918  * convenience and illustrative purposes. They should, however, be used with
919  * caution as the C language standard provides no guarantees about the alignment or
920  * atomicity of device memory accesses. The recommended practice for writing
921  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
922  * alt_write_word() functions.
923  *
924  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_7.
925  */
926 struct ALT_PINMUX_SHARED_3V_IO_Q1_7_s
927 {
928  uint32_t sel : 4; /* Shared IO48 Q1 7 Mux Selection Field */
929  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q1_7_RSVD */
930 };
931 
932 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_7. */
933 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q1_7_s ALT_PINMUX_SHARED_3V_IO_Q1_7_t;
934 #endif /* __ASSEMBLY__ */
935 
936 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_7 register. */
937 #define ALT_PINMUX_SHARED_3V_IO_Q1_7_RESET 0x0000000f
938 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q1_7 register from the beginning of the component. */
939 #define ALT_PINMUX_SHARED_3V_IO_Q1_7_OFST 0x18
940 
941 /*
942  * Register : Shared IO 48 Q1 8 Mux Selection Register - pinmux_shared_io_q1_8
943  *
944  * This register is used to control the peripherals connected to shared IO48 pin Q1
945  * 8
946  *
947  * Only reset by a cold reset (ignores warm reset).
948  *
949  * NOTE: These registers should not be modified after IO configuration.There is no
950  * support for dynamically changing the Pin Mux selections.
951  *
952  * Register Layout
953  *
954  * Bits | Access | Reset | Description
955  * :-------|:-------|:------|:-------------------------------------
956  * [3:0] | RW | 0xf | Shared IO48 Q1 8 Mux Selection Field
957  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q1_8_RSVD
958  *
959  */
960 /*
961  * Field : Shared IO48 Q1 8 Mux Selection Field - sel
962  *
963  * Select peripheral signals connected shared IO48 Q1 8
964  *
965  * 0000 (0) Pin is connected to Peripheral signal i2c_emac2.scl
966  *
967  * 0001 (1) Pin is connected to Peripheral signal emac2.mdc
968  *
969  * 0010 (2) Pin is connected to Peripheral signal not applicable
970  *
971  * 0011 (3) Pin is connected to Peripheral signal spim0.ss0_n
972  *
973  * 0100 (4) Pin is connected to Peripheral signal sdmmc.data5
974  *
975  * 0101 (5) Pin is connected to Peripheral signal not applicable
976  *
977  * 0110 (6) Pin is connected to Peripheral signal not applicable
978  *
979  * 0111 (7) Pin is connected to Peripheral signal not applicable
980  *
981  * 1000 (8) Pin is connected to Peripheral signal usb0.data3
982  *
983  * 1001 (9) Pin is connected to Peripheral signal not applicable
984  *
985  * 1010 (10) Pin is connected to Peripheral signal not applicable
986  *
987  * 1011 (11) Pin is connected to Peripheral signal not applicable
988  *
989  * 1100 (12) Pin is connected to Peripheral signal not applicable
990  *
991  * 1101 (13) Pin is connected to Peripheral signal uart1.rx
992  *
993  * 1110 (14) Pin is connected to Peripheral signal nand.cle
994  *
995  * 1111 (15) Pin is connected to Peripheral signal gpio0.io7
996  *
997  * Field Access Macros:
998  *
999  */
1000 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_8_SEL register field. */
1001 #define ALT_PINMUX_SHARED_3V_IO_Q1_8_SEL_LSB 0
1002 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_8_SEL register field. */
1003 #define ALT_PINMUX_SHARED_3V_IO_Q1_8_SEL_MSB 3
1004 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_8_SEL register field. */
1005 #define ALT_PINMUX_SHARED_3V_IO_Q1_8_SEL_WIDTH 4
1006 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_8_SEL register field value. */
1007 #define ALT_PINMUX_SHARED_3V_IO_Q1_8_SEL_SET_MSK 0x0000000f
1008 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_8_SEL register field value. */
1009 #define ALT_PINMUX_SHARED_3V_IO_Q1_8_SEL_CLR_MSK 0xfffffff0
1010 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_8_SEL register field. */
1011 #define ALT_PINMUX_SHARED_3V_IO_Q1_8_SEL_RESET 0xf
1012 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_8_SEL field value from a register. */
1013 #define ALT_PINMUX_SHARED_3V_IO_Q1_8_SEL_GET(value) (((value) & 0x0000000f) >> 0)
1014 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_8_SEL register field value suitable for setting the register. */
1015 #define ALT_PINMUX_SHARED_3V_IO_Q1_8_SEL_SET(value) (((value) << 0) & 0x0000000f)
1016 
1017 /*
1018  * Field : Reserved
1019  *
1020  * Reserved
1021  *
1022  * Field Access Macros:
1023  *
1024  */
1025 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_8_RSVD register field. */
1026 #define ALT_PINMUX_SHARED_3V_IO_Q1_8_RSVD_LSB 4
1027 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_8_RSVD register field. */
1028 #define ALT_PINMUX_SHARED_3V_IO_Q1_8_RSVD_MSB 31
1029 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_8_RSVD register field. */
1030 #define ALT_PINMUX_SHARED_3V_IO_Q1_8_RSVD_WIDTH 28
1031 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_8_RSVD register field value. */
1032 #define ALT_PINMUX_SHARED_3V_IO_Q1_8_RSVD_SET_MSK 0xfffffff0
1033 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_8_RSVD register field value. */
1034 #define ALT_PINMUX_SHARED_3V_IO_Q1_8_RSVD_CLR_MSK 0x0000000f
1035 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_8_RSVD register field. */
1036 #define ALT_PINMUX_SHARED_3V_IO_Q1_8_RSVD_RESET 0x0
1037 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_8_RSVD field value from a register. */
1038 #define ALT_PINMUX_SHARED_3V_IO_Q1_8_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
1039 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_8_RSVD register field value suitable for setting the register. */
1040 #define ALT_PINMUX_SHARED_3V_IO_Q1_8_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
1041 
1042 #ifndef __ASSEMBLY__
1043 /*
1044  * WARNING: The C register and register group struct declarations are provided for
1045  * convenience and illustrative purposes. They should, however, be used with
1046  * caution as the C language standard provides no guarantees about the alignment or
1047  * atomicity of device memory accesses. The recommended practice for writing
1048  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1049  * alt_write_word() functions.
1050  *
1051  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_8.
1052  */
1053 struct ALT_PINMUX_SHARED_3V_IO_Q1_8_s
1054 {
1055  uint32_t sel : 4; /* Shared IO48 Q1 8 Mux Selection Field */
1056  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q1_8_RSVD */
1057 };
1058 
1059 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_8. */
1060 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q1_8_s ALT_PINMUX_SHARED_3V_IO_Q1_8_t;
1061 #endif /* __ASSEMBLY__ */
1062 
1063 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_8 register. */
1064 #define ALT_PINMUX_SHARED_3V_IO_Q1_8_RESET 0x0000000f
1065 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q1_8 register from the beginning of the component. */
1066 #define ALT_PINMUX_SHARED_3V_IO_Q1_8_OFST 0x1c
1067 
1068 /*
1069  * Register : Shared IO 48 Q1 9 Mux Selection Register - pinmux_shared_io_q1_9
1070  *
1071  * This register is used to control the peripherals connected to shared IO48 pin Q1
1072  * 9
1073  *
1074  * Only reset by a cold reset (ignores warm reset).
1075  *
1076  * NOTE: These registers should not be modified after IO configuration.There is no
1077  * support for dynamically changing the Pin Mux selections.
1078  *
1079  * Register Layout
1080  *
1081  * Bits | Access | Reset | Description
1082  * :-------|:-------|:------|:-------------------------------------
1083  * [3:0] | RW | 0xf | Shared IO48 Q1 9 Mux Selection Field
1084  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q1_9_RSVD
1085  *
1086  */
1087 /*
1088  * Field : Shared IO48 Q1 9 Mux Selection Field - sel
1089  *
1090  * Select peripheral signals connected shared IO48 Q1 9
1091  *
1092  * 0000 (0) Pin is connected to Peripheral signal i2c_emac1.sda
1093  *
1094  * 0001 (1) Pin is connected to Peripheral signal emac1.mdio
1095  *
1096  * 0010 (2) Pin is connected to Peripheral signal spis1.clk
1097  *
1098  * 0011 (3) Pin is connected to Peripheral signal spim1.clk
1099  *
1100  * 0100 (4) Pin is connected to Peripheral signal sdmmc.data6
1101  *
1102  * 0101 (5) Pin is connected to Peripheral signal not applicable
1103  *
1104  * 0110 (6) Pin is connected to Peripheral signal not applicable
1105  *
1106  * 0111 (7) Pin is connected to Peripheral signal not applicable
1107  *
1108  * 1000 (8) Pin is connected to Peripheral signal usb0.data4
1109  *
1110  * 1001 (9) Pin is connected to Peripheral signal not applicable
1111  *
1112  * 1010 (10) Pin is connected to Peripheral signal not applicable
1113  *
1114  * 1011 (11) Pin is connected to Peripheral signal not applicable
1115  *
1116  * 1100 (12) Pin is connected to Peripheral signal not applicable
1117  *
1118  * 1101 (13) Pin is connected to Peripheral signal not applicable
1119  *
1120  * 1110 (14) Pin is connected to Peripheral signal nand.adq4
1121  *
1122  * 1111 (15) Pin is connected to Peripheral signal gpio0.io8
1123  *
1124  * Field Access Macros:
1125  *
1126  */
1127 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_9_SEL register field. */
1128 #define ALT_PINMUX_SHARED_3V_IO_Q1_9_SEL_LSB 0
1129 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_9_SEL register field. */
1130 #define ALT_PINMUX_SHARED_3V_IO_Q1_9_SEL_MSB 3
1131 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_9_SEL register field. */
1132 #define ALT_PINMUX_SHARED_3V_IO_Q1_9_SEL_WIDTH 4
1133 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_9_SEL register field value. */
1134 #define ALT_PINMUX_SHARED_3V_IO_Q1_9_SEL_SET_MSK 0x0000000f
1135 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_9_SEL register field value. */
1136 #define ALT_PINMUX_SHARED_3V_IO_Q1_9_SEL_CLR_MSK 0xfffffff0
1137 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_9_SEL register field. */
1138 #define ALT_PINMUX_SHARED_3V_IO_Q1_9_SEL_RESET 0xf
1139 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_9_SEL field value from a register. */
1140 #define ALT_PINMUX_SHARED_3V_IO_Q1_9_SEL_GET(value) (((value) & 0x0000000f) >> 0)
1141 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_9_SEL register field value suitable for setting the register. */
1142 #define ALT_PINMUX_SHARED_3V_IO_Q1_9_SEL_SET(value) (((value) << 0) & 0x0000000f)
1143 
1144 /*
1145  * Field : Reserved
1146  *
1147  * Reserved
1148  *
1149  * Field Access Macros:
1150  *
1151  */
1152 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_9_RSVD register field. */
1153 #define ALT_PINMUX_SHARED_3V_IO_Q1_9_RSVD_LSB 4
1154 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_9_RSVD register field. */
1155 #define ALT_PINMUX_SHARED_3V_IO_Q1_9_RSVD_MSB 31
1156 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_9_RSVD register field. */
1157 #define ALT_PINMUX_SHARED_3V_IO_Q1_9_RSVD_WIDTH 28
1158 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_9_RSVD register field value. */
1159 #define ALT_PINMUX_SHARED_3V_IO_Q1_9_RSVD_SET_MSK 0xfffffff0
1160 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_9_RSVD register field value. */
1161 #define ALT_PINMUX_SHARED_3V_IO_Q1_9_RSVD_CLR_MSK 0x0000000f
1162 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_9_RSVD register field. */
1163 #define ALT_PINMUX_SHARED_3V_IO_Q1_9_RSVD_RESET 0x0
1164 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_9_RSVD field value from a register. */
1165 #define ALT_PINMUX_SHARED_3V_IO_Q1_9_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
1166 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_9_RSVD register field value suitable for setting the register. */
1167 #define ALT_PINMUX_SHARED_3V_IO_Q1_9_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
1168 
1169 #ifndef __ASSEMBLY__
1170 /*
1171  * WARNING: The C register and register group struct declarations are provided for
1172  * convenience and illustrative purposes. They should, however, be used with
1173  * caution as the C language standard provides no guarantees about the alignment or
1174  * atomicity of device memory accesses. The recommended practice for writing
1175  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1176  * alt_write_word() functions.
1177  *
1178  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_9.
1179  */
1180 struct ALT_PINMUX_SHARED_3V_IO_Q1_9_s
1181 {
1182  uint32_t sel : 4; /* Shared IO48 Q1 9 Mux Selection Field */
1183  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q1_9_RSVD */
1184 };
1185 
1186 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_9. */
1187 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q1_9_s ALT_PINMUX_SHARED_3V_IO_Q1_9_t;
1188 #endif /* __ASSEMBLY__ */
1189 
1190 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_9 register. */
1191 #define ALT_PINMUX_SHARED_3V_IO_Q1_9_RESET 0x0000000f
1192 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q1_9 register from the beginning of the component. */
1193 #define ALT_PINMUX_SHARED_3V_IO_Q1_9_OFST 0x20
1194 
1195 /*
1196  * Register : Shared IO 48 Q1 10 Mux Selection Register - pinmux_shared_io_q1_10
1197  *
1198  * This register is used to control the peripherals connected to shared IO48 pin Q1
1199  * 10
1200  *
1201  * Only reset by a cold reset (ignores warm reset).
1202  *
1203  * NOTE: These registers should not be modified after IO configuration.There is no
1204  * support for dynamically changing the Pin Mux selections.
1205  *
1206  * Register Layout
1207  *
1208  * Bits | Access | Reset | Description
1209  * :-------|:-------|:------|:--------------------------------------
1210  * [3:0] | RW | 0xf | Shared IO48 Q1 10 Mux Selection Field
1211  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q1_10_RSVD
1212  *
1213  */
1214 /*
1215  * Field : Shared IO48 Q1 10 Mux Selection Field - sel
1216  *
1217  * Select peripheral signals connected shared IO48 Q1 10
1218  *
1219  * 0000 (0) Pin is connected to Peripheral signal i2c_emac1.scl
1220  *
1221  * 0001 (1) Pin is connected to Peripheral signal emac1.mdc
1222  *
1223  * 0010 (2) Pin is connected to Peripheral signal spis1.mosi
1224  *
1225  * 0011 (3) Pin is connected to Peripheral signal spim1.mosi
1226  *
1227  * 0100 (4) Pin is connected to Peripheral signal sdmmc.data7
1228  *
1229  * 0101 (5) Pin is connected to Peripheral signal not applicable
1230  *
1231  * 0110 (6) Pin is connected to Peripheral signal not applicable
1232  *
1233  * 0111 (7) Pin is connected to Peripheral signal not applicable
1234  *
1235  * 1000 (8) Pin is connected to Peripheral signal usb0.data5
1236  *
1237  * 1001 (9) Pin is connected to Peripheral signal not applicable
1238  *
1239  * 1010 (10) Pin is connected to Peripheral signal not applicable
1240  *
1241  * 1011 (11) Pin is connected to Peripheral signal not applicable
1242  *
1243  * 1100 (12) Pin is connected to Peripheral signal not applicable
1244  *
1245  * 1101 (13) Pin is connected to Peripheral signal not applicable
1246  *
1247  * 1110 (14) Pin is connected to Peripheral signal nand.adq5
1248  *
1249  * 1111 (15) Pin is connected to Peripheral signal gpio0.io9
1250  *
1251  * Field Access Macros:
1252  *
1253  */
1254 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_10_SEL register field. */
1255 #define ALT_PINMUX_SHARED_3V_IO_Q1_10_SEL_LSB 0
1256 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_10_SEL register field. */
1257 #define ALT_PINMUX_SHARED_3V_IO_Q1_10_SEL_MSB 3
1258 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_10_SEL register field. */
1259 #define ALT_PINMUX_SHARED_3V_IO_Q1_10_SEL_WIDTH 4
1260 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_10_SEL register field value. */
1261 #define ALT_PINMUX_SHARED_3V_IO_Q1_10_SEL_SET_MSK 0x0000000f
1262 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_10_SEL register field value. */
1263 #define ALT_PINMUX_SHARED_3V_IO_Q1_10_SEL_CLR_MSK 0xfffffff0
1264 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_10_SEL register field. */
1265 #define ALT_PINMUX_SHARED_3V_IO_Q1_10_SEL_RESET 0xf
1266 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_10_SEL field value from a register. */
1267 #define ALT_PINMUX_SHARED_3V_IO_Q1_10_SEL_GET(value) (((value) & 0x0000000f) >> 0)
1268 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_10_SEL register field value suitable for setting the register. */
1269 #define ALT_PINMUX_SHARED_3V_IO_Q1_10_SEL_SET(value) (((value) << 0) & 0x0000000f)
1270 
1271 /*
1272  * Field : Reserved
1273  *
1274  * Reserved
1275  *
1276  * Field Access Macros:
1277  *
1278  */
1279 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_10_RSVD register field. */
1280 #define ALT_PINMUX_SHARED_3V_IO_Q1_10_RSVD_LSB 4
1281 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_10_RSVD register field. */
1282 #define ALT_PINMUX_SHARED_3V_IO_Q1_10_RSVD_MSB 31
1283 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_10_RSVD register field. */
1284 #define ALT_PINMUX_SHARED_3V_IO_Q1_10_RSVD_WIDTH 28
1285 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_10_RSVD register field value. */
1286 #define ALT_PINMUX_SHARED_3V_IO_Q1_10_RSVD_SET_MSK 0xfffffff0
1287 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_10_RSVD register field value. */
1288 #define ALT_PINMUX_SHARED_3V_IO_Q1_10_RSVD_CLR_MSK 0x0000000f
1289 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_10_RSVD register field. */
1290 #define ALT_PINMUX_SHARED_3V_IO_Q1_10_RSVD_RESET 0x0
1291 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_10_RSVD field value from a register. */
1292 #define ALT_PINMUX_SHARED_3V_IO_Q1_10_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
1293 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_10_RSVD register field value suitable for setting the register. */
1294 #define ALT_PINMUX_SHARED_3V_IO_Q1_10_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
1295 
1296 #ifndef __ASSEMBLY__
1297 /*
1298  * WARNING: The C register and register group struct declarations are provided for
1299  * convenience and illustrative purposes. They should, however, be used with
1300  * caution as the C language standard provides no guarantees about the alignment or
1301  * atomicity of device memory accesses. The recommended practice for writing
1302  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1303  * alt_write_word() functions.
1304  *
1305  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_10.
1306  */
1307 struct ALT_PINMUX_SHARED_3V_IO_Q1_10_s
1308 {
1309  uint32_t sel : 4; /* Shared IO48 Q1 10 Mux Selection Field */
1310  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q1_10_RSVD */
1311 };
1312 
1313 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_10. */
1314 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q1_10_s ALT_PINMUX_SHARED_3V_IO_Q1_10_t;
1315 #endif /* __ASSEMBLY__ */
1316 
1317 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_10 register. */
1318 #define ALT_PINMUX_SHARED_3V_IO_Q1_10_RESET 0x0000000f
1319 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q1_10 register from the beginning of the component. */
1320 #define ALT_PINMUX_SHARED_3V_IO_Q1_10_OFST 0x24
1321 
1322 /*
1323  * Register : Shared IO 48 Q1 11 Mux Selection Register - pinmux_shared_io_q1_11
1324  *
1325  * This register is used to control the peripherals connected to shared IO48 pin Q1
1326  * 11
1327  *
1328  * Only reset by a cold reset (ignores warm reset).
1329  *
1330  * NOTE: These registers should not be modified after IO configuration.There is no
1331  * support for dynamically changing the Pin Mux selections.
1332  *
1333  * Register Layout
1334  *
1335  * Bits | Access | Reset | Description
1336  * :-------|:-------|:------|:--------------------------------------
1337  * [3:0] | RW | 0xf | Shared IO48 Q1 11 Mux Selection Field
1338  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q1_11_RSVD
1339  *
1340  */
1341 /*
1342  * Field : Shared IO48 Q1 11 Mux Selection Field - sel
1343  *
1344  * Select peripheral signals connected shared IO48 Q1 11
1345  *
1346  * 0000 (0) Pin is connected to Peripheral signal i2c_emac0.sda
1347  *
1348  * 0001 (1) Pin is connected to Peripheral signal emac0.mdio
1349  *
1350  * 0010 (2) Pin is connected to Peripheral signal spis1.ss0_n
1351  *
1352  * 0011 (3) Pin is connected to Peripheral signal spim1.miso
1353  *
1354  * 0100 (4) Pin is connected to Peripheral signal not applicable
1355  *
1356  * 0101 (5) Pin is connected to Peripheral signal not applicable
1357  *
1358  * 0110 (6) Pin is connected to Peripheral signal not applicable
1359  *
1360  * 0111 (7) Pin is connected to Peripheral signal not applicable
1361  *
1362  * 1000 (8) Pin is connected to Peripheral signal usb0.data6
1363  *
1364  * 1001 (9) Pin is connected to Peripheral signal not applicable
1365  *
1366  * 1010 (10) Pin is connected to Peripheral signal not applicable
1367  *
1368  * 1011 (11) Pin is connected to Peripheral signal not applicable
1369  *
1370  * 1100 (12) Pin is connected to Peripheral signal not applicable
1371  *
1372  * 1101 (13) Pin is connected to Peripheral signal not applicable
1373  *
1374  * 1110 (14) Pin is connected to Peripheral signal nand.adq6
1375  *
1376  * 1111 (15) Pin is connected to Peripheral signal gpio0.io10
1377  *
1378  * Field Access Macros:
1379  *
1380  */
1381 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_11_SEL register field. */
1382 #define ALT_PINMUX_SHARED_3V_IO_Q1_11_SEL_LSB 0
1383 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_11_SEL register field. */
1384 #define ALT_PINMUX_SHARED_3V_IO_Q1_11_SEL_MSB 3
1385 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_11_SEL register field. */
1386 #define ALT_PINMUX_SHARED_3V_IO_Q1_11_SEL_WIDTH 4
1387 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_11_SEL register field value. */
1388 #define ALT_PINMUX_SHARED_3V_IO_Q1_11_SEL_SET_MSK 0x0000000f
1389 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_11_SEL register field value. */
1390 #define ALT_PINMUX_SHARED_3V_IO_Q1_11_SEL_CLR_MSK 0xfffffff0
1391 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_11_SEL register field. */
1392 #define ALT_PINMUX_SHARED_3V_IO_Q1_11_SEL_RESET 0xf
1393 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_11_SEL field value from a register. */
1394 #define ALT_PINMUX_SHARED_3V_IO_Q1_11_SEL_GET(value) (((value) & 0x0000000f) >> 0)
1395 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_11_SEL register field value suitable for setting the register. */
1396 #define ALT_PINMUX_SHARED_3V_IO_Q1_11_SEL_SET(value) (((value) << 0) & 0x0000000f)
1397 
1398 /*
1399  * Field : Reserved
1400  *
1401  * Reserved
1402  *
1403  * Field Access Macros:
1404  *
1405  */
1406 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_11_RSVD register field. */
1407 #define ALT_PINMUX_SHARED_3V_IO_Q1_11_RSVD_LSB 4
1408 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_11_RSVD register field. */
1409 #define ALT_PINMUX_SHARED_3V_IO_Q1_11_RSVD_MSB 31
1410 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_11_RSVD register field. */
1411 #define ALT_PINMUX_SHARED_3V_IO_Q1_11_RSVD_WIDTH 28
1412 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_11_RSVD register field value. */
1413 #define ALT_PINMUX_SHARED_3V_IO_Q1_11_RSVD_SET_MSK 0xfffffff0
1414 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_11_RSVD register field value. */
1415 #define ALT_PINMUX_SHARED_3V_IO_Q1_11_RSVD_CLR_MSK 0x0000000f
1416 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_11_RSVD register field. */
1417 #define ALT_PINMUX_SHARED_3V_IO_Q1_11_RSVD_RESET 0x0
1418 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_11_RSVD field value from a register. */
1419 #define ALT_PINMUX_SHARED_3V_IO_Q1_11_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
1420 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_11_RSVD register field value suitable for setting the register. */
1421 #define ALT_PINMUX_SHARED_3V_IO_Q1_11_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
1422 
1423 #ifndef __ASSEMBLY__
1424 /*
1425  * WARNING: The C register and register group struct declarations are provided for
1426  * convenience and illustrative purposes. They should, however, be used with
1427  * caution as the C language standard provides no guarantees about the alignment or
1428  * atomicity of device memory accesses. The recommended practice for writing
1429  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1430  * alt_write_word() functions.
1431  *
1432  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_11.
1433  */
1434 struct ALT_PINMUX_SHARED_3V_IO_Q1_11_s
1435 {
1436  uint32_t sel : 4; /* Shared IO48 Q1 11 Mux Selection Field */
1437  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q1_11_RSVD */
1438 };
1439 
1440 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_11. */
1441 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q1_11_s ALT_PINMUX_SHARED_3V_IO_Q1_11_t;
1442 #endif /* __ASSEMBLY__ */
1443 
1444 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_11 register. */
1445 #define ALT_PINMUX_SHARED_3V_IO_Q1_11_RESET 0x0000000f
1446 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q1_11 register from the beginning of the component. */
1447 #define ALT_PINMUX_SHARED_3V_IO_Q1_11_OFST 0x28
1448 
1449 /*
1450  * Register : Shared IO 48 Q1 12 Mux Selection Register - pinmux_shared_io_q1_12
1451  *
1452  * This register is used to control the peripherals connected to shared IO48 pin Q1
1453  * 12
1454  *
1455  * Only reset by a cold reset (ignores warm reset).
1456  *
1457  * NOTE: These registers should not be modified after IO configuration.There is no
1458  * support for dynamically changing the Pin Mux selections.
1459  *
1460  * Register Layout
1461  *
1462  * Bits | Access | Reset | Description
1463  * :-------|:-------|:------|:--------------------------------------
1464  * [3:0] | RW | 0xf | Shared IO48 Q1 12 Mux Selection Field
1465  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q1_12_RSVD
1466  *
1467  */
1468 /*
1469  * Field : Shared IO48 Q1 12 Mux Selection Field - sel
1470  *
1471  * Select peripheral signals connected shared IO48 Q1 12
1472  *
1473  * 0000 (0) Pin is connected to Peripheral signal i2c_emac0.scl
1474  *
1475  * 0001 (1) Pin is connected to Peripheral signal emac0.mdc
1476  *
1477  * 0010 (2) Pin is connected to Peripheral signal spis1.miso
1478  *
1479  * 0011 (3) Pin is connected to Peripheral signal spim1.ss0_n
1480  *
1481  * 0100 (4) Pin is connected to Peripheral signal not applicable
1482  *
1483  * 0101 (5) Pin is connected to Peripheral signal not applicable
1484  *
1485  * 0110 (6) Pin is connected to Peripheral signal not applicable
1486  *
1487  * 0111 (7) Pin is connected to Peripheral signal not applicable
1488  *
1489  * 1000 (8) Pin is connected to Peripheral signal usb0.data7
1490  *
1491  * 1001 (9) Pin is connected to Peripheral signal not applicable
1492  *
1493  * 1010 (10) Pin is connected to Peripheral signal not applicable
1494  *
1495  * 1011 (11) Pin is connected to Peripheral signal not applicable
1496  *
1497  * 1100 (12) Pin is connected to Peripheral signal not applicable
1498  *
1499  * 1101 (13) Pin is connected to Peripheral signal not applicable
1500  *
1501  * 1110 (14) Pin is connected to Peripheral signal nand.adq7
1502  *
1503  * 1111 (15) Pin is connected to Peripheral signal gpio0.io11
1504  *
1505  * Field Access Macros:
1506  *
1507  */
1508 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_12_SEL register field. */
1509 #define ALT_PINMUX_SHARED_3V_IO_Q1_12_SEL_LSB 0
1510 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_12_SEL register field. */
1511 #define ALT_PINMUX_SHARED_3V_IO_Q1_12_SEL_MSB 3
1512 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_12_SEL register field. */
1513 #define ALT_PINMUX_SHARED_3V_IO_Q1_12_SEL_WIDTH 4
1514 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_12_SEL register field value. */
1515 #define ALT_PINMUX_SHARED_3V_IO_Q1_12_SEL_SET_MSK 0x0000000f
1516 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_12_SEL register field value. */
1517 #define ALT_PINMUX_SHARED_3V_IO_Q1_12_SEL_CLR_MSK 0xfffffff0
1518 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_12_SEL register field. */
1519 #define ALT_PINMUX_SHARED_3V_IO_Q1_12_SEL_RESET 0xf
1520 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_12_SEL field value from a register. */
1521 #define ALT_PINMUX_SHARED_3V_IO_Q1_12_SEL_GET(value) (((value) & 0x0000000f) >> 0)
1522 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_12_SEL register field value suitable for setting the register. */
1523 #define ALT_PINMUX_SHARED_3V_IO_Q1_12_SEL_SET(value) (((value) << 0) & 0x0000000f)
1524 
1525 /*
1526  * Field : Reserved
1527  *
1528  * Reserved
1529  *
1530  * Field Access Macros:
1531  *
1532  */
1533 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_12_RSVD register field. */
1534 #define ALT_PINMUX_SHARED_3V_IO_Q1_12_RSVD_LSB 4
1535 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q1_12_RSVD register field. */
1536 #define ALT_PINMUX_SHARED_3V_IO_Q1_12_RSVD_MSB 31
1537 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q1_12_RSVD register field. */
1538 #define ALT_PINMUX_SHARED_3V_IO_Q1_12_RSVD_WIDTH 28
1539 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q1_12_RSVD register field value. */
1540 #define ALT_PINMUX_SHARED_3V_IO_Q1_12_RSVD_SET_MSK 0xfffffff0
1541 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q1_12_RSVD register field value. */
1542 #define ALT_PINMUX_SHARED_3V_IO_Q1_12_RSVD_CLR_MSK 0x0000000f
1543 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_12_RSVD register field. */
1544 #define ALT_PINMUX_SHARED_3V_IO_Q1_12_RSVD_RESET 0x0
1545 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q1_12_RSVD field value from a register. */
1546 #define ALT_PINMUX_SHARED_3V_IO_Q1_12_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
1547 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q1_12_RSVD register field value suitable for setting the register. */
1548 #define ALT_PINMUX_SHARED_3V_IO_Q1_12_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
1549 
1550 #ifndef __ASSEMBLY__
1551 /*
1552  * WARNING: The C register and register group struct declarations are provided for
1553  * convenience and illustrative purposes. They should, however, be used with
1554  * caution as the C language standard provides no guarantees about the alignment or
1555  * atomicity of device memory accesses. The recommended practice for writing
1556  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1557  * alt_write_word() functions.
1558  *
1559  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_12.
1560  */
1561 struct ALT_PINMUX_SHARED_3V_IO_Q1_12_s
1562 {
1563  uint32_t sel : 4; /* Shared IO48 Q1 12 Mux Selection Field */
1564  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q1_12_RSVD */
1565 };
1566 
1567 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q1_12. */
1568 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q1_12_s ALT_PINMUX_SHARED_3V_IO_Q1_12_t;
1569 #endif /* __ASSEMBLY__ */
1570 
1571 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q1_12 register. */
1572 #define ALT_PINMUX_SHARED_3V_IO_Q1_12_RESET 0x0000000f
1573 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q1_12 register from the beginning of the component. */
1574 #define ALT_PINMUX_SHARED_3V_IO_Q1_12_OFST 0x2c
1575 
1576 /*
1577  * Register : Shared IO 48 Q2 1 Mux Selection Register - pinmux_shared_io_q2_1
1578  *
1579  * This register is used to control the peripherals connected to shared IO48 pin Q2
1580  * 1
1581  *
1582  * Only reset by a cold reset (ignores warm reset).
1583  *
1584  * NOTE: These registers should not be modified after IO configuration.There is no
1585  * support for dynamically changing the Pin Mux selections.
1586  *
1587  * Register Layout
1588  *
1589  * Bits | Access | Reset | Description
1590  * :-------|:-------|:------|:-------------------------------------
1591  * [3:0] | RW | 0xf | Shared IO48 Q2 1 Mux Selection Field
1592  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q2_1_RSVD
1593  *
1594  */
1595 /*
1596  * Field : Shared IO48 Q2 1 Mux Selection Field - sel
1597  *
1598  * Select peripheral signals connected shared IO48 Q2 1
1599  *
1600  * 0000 (0) Pin is connected to Peripheral signal not applicable
1601  *
1602  * 0001 (1) Pin is connected to Peripheral signal not applicable
1603  *
1604  * 0010 (2) Pin is connected to Peripheral signal not applicable
1605  *
1606  * 0011 (3) Pin is connected to Peripheral signal not applicable
1607  *
1608  * 0100 (4) Pin is connected to Peripheral signal emac0.tx_clk
1609  *
1610  * 0101 (5) Pin is connected to Peripheral signal not applicable
1611  *
1612  * 0110 (6) Pin is connected to Peripheral signal not applicable
1613  *
1614  * 0111 (7) Pin is connected to Peripheral signal not applicable
1615  *
1616  * 1000 (8) Pin is connected to Peripheral signal usb1.clk
1617  *
1618  * 1001 (9) Pin is connected to Peripheral signal not applicable
1619  *
1620  * 1010 (10) Pin is connected to Peripheral signal not applicable
1621  *
1622  * 1011 (11) Pin is connected to Peripheral signal not applicable
1623  *
1624  * 1100 (12) Pin is connected to Peripheral signal not applicable
1625  *
1626  * 1101 (13) Pin is connected to Peripheral signal not applicable
1627  *
1628  * 1110 (14) Pin is connected to Peripheral signal nand.ale
1629  *
1630  * 1111 (15) Pin is connected to Peripheral signal gpio0.io12
1631  *
1632  * Field Access Macros:
1633  *
1634  */
1635 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_1_SEL register field. */
1636 #define ALT_PINMUX_SHARED_3V_IO_Q2_1_SEL_LSB 0
1637 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_1_SEL register field. */
1638 #define ALT_PINMUX_SHARED_3V_IO_Q2_1_SEL_MSB 3
1639 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_1_SEL register field. */
1640 #define ALT_PINMUX_SHARED_3V_IO_Q2_1_SEL_WIDTH 4
1641 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_1_SEL register field value. */
1642 #define ALT_PINMUX_SHARED_3V_IO_Q2_1_SEL_SET_MSK 0x0000000f
1643 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_1_SEL register field value. */
1644 #define ALT_PINMUX_SHARED_3V_IO_Q2_1_SEL_CLR_MSK 0xfffffff0
1645 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_1_SEL register field. */
1646 #define ALT_PINMUX_SHARED_3V_IO_Q2_1_SEL_RESET 0xf
1647 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_1_SEL field value from a register. */
1648 #define ALT_PINMUX_SHARED_3V_IO_Q2_1_SEL_GET(value) (((value) & 0x0000000f) >> 0)
1649 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_1_SEL register field value suitable for setting the register. */
1650 #define ALT_PINMUX_SHARED_3V_IO_Q2_1_SEL_SET(value) (((value) << 0) & 0x0000000f)
1651 
1652 /*
1653  * Field : Reserved
1654  *
1655  * Reserved
1656  *
1657  * Field Access Macros:
1658  *
1659  */
1660 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_1_RSVD register field. */
1661 #define ALT_PINMUX_SHARED_3V_IO_Q2_1_RSVD_LSB 4
1662 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_1_RSVD register field. */
1663 #define ALT_PINMUX_SHARED_3V_IO_Q2_1_RSVD_MSB 31
1664 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_1_RSVD register field. */
1665 #define ALT_PINMUX_SHARED_3V_IO_Q2_1_RSVD_WIDTH 28
1666 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_1_RSVD register field value. */
1667 #define ALT_PINMUX_SHARED_3V_IO_Q2_1_RSVD_SET_MSK 0xfffffff0
1668 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_1_RSVD register field value. */
1669 #define ALT_PINMUX_SHARED_3V_IO_Q2_1_RSVD_CLR_MSK 0x0000000f
1670 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_1_RSVD register field. */
1671 #define ALT_PINMUX_SHARED_3V_IO_Q2_1_RSVD_RESET 0x0
1672 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_1_RSVD field value from a register. */
1673 #define ALT_PINMUX_SHARED_3V_IO_Q2_1_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
1674 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_1_RSVD register field value suitable for setting the register. */
1675 #define ALT_PINMUX_SHARED_3V_IO_Q2_1_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
1676 
1677 #ifndef __ASSEMBLY__
1678 /*
1679  * WARNING: The C register and register group struct declarations are provided for
1680  * convenience and illustrative purposes. They should, however, be used with
1681  * caution as the C language standard provides no guarantees about the alignment or
1682  * atomicity of device memory accesses. The recommended practice for writing
1683  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1684  * alt_write_word() functions.
1685  *
1686  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_1.
1687  */
1688 struct ALT_PINMUX_SHARED_3V_IO_Q2_1_s
1689 {
1690  uint32_t sel : 4; /* Shared IO48 Q2 1 Mux Selection Field */
1691  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q2_1_RSVD */
1692 };
1693 
1694 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_1. */
1695 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q2_1_s ALT_PINMUX_SHARED_3V_IO_Q2_1_t;
1696 #endif /* __ASSEMBLY__ */
1697 
1698 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_1 register. */
1699 #define ALT_PINMUX_SHARED_3V_IO_Q2_1_RESET 0x0000000f
1700 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q2_1 register from the beginning of the component. */
1701 #define ALT_PINMUX_SHARED_3V_IO_Q2_1_OFST 0x30
1702 
1703 /*
1704  * Register : Shared IO 48 Q2 2 Mux Selection Register - pinmux_shared_io_q2_2
1705  *
1706  * This register is used to control the peripherals connected to shared IO48 pin Q2
1707  * 2
1708  *
1709  * Only reset by a cold reset (ignores warm reset).
1710  *
1711  * NOTE: These registers should not be modified after IO configuration.There is no
1712  * support for dynamically changing the Pin Mux selections.
1713  *
1714  * Register Layout
1715  *
1716  * Bits | Access | Reset | Description
1717  * :-------|:-------|:------|:-------------------------------------
1718  * [3:0] | RW | 0xf | Shared IO48 Q2 2 Mux Selection Field
1719  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q2_2_RSVD
1720  *
1721  */
1722 /*
1723  * Field : Shared IO48 Q2 2 Mux Selection Field - sel
1724  *
1725  * Select peripheral signals connected shared IO48 Q2 2
1726  *
1727  * 0000 (0) Pin is connected to Peripheral signal not applicable
1728  *
1729  * 0001 (1) Pin is connected to Peripheral signal not applicable
1730  *
1731  * 0010 (2) Pin is connected to Peripheral signal not applicable
1732  *
1733  * 0011 (3) Pin is connected to Peripheral signal not applicable
1734  *
1735  * 0100 (4) Pin is connected to Peripheral signal emac0.tx_ctl
1736  *
1737  * 0101 (5) Pin is connected to Peripheral signal not applicable
1738  *
1739  * 0110 (6) Pin is connected to Peripheral signal not applicable
1740  *
1741  * 0111 (7) Pin is connected to Peripheral signal not applicable
1742  *
1743  * 1000 (8) Pin is connected to Peripheral signal usb1.stp
1744  *
1745  * 1001 (9) Pin is connected to Peripheral signal not applicable
1746  *
1747  * 1010 (10) Pin is connected to Peripheral signal not applicable
1748  *
1749  * 1011 (11) Pin is connected to Peripheral signal not applicable
1750  *
1751  * 1100 (12) Pin is connected to Peripheral signal not applicable
1752  *
1753  * 1101 (13) Pin is connected to Peripheral signal not applicable
1754  *
1755  * 1110 (14) Pin is connected to Peripheral signal nand.rb
1756  *
1757  * 1111 (15) Pin is connected to Peripheral signal gpio0.io13
1758  *
1759  * Field Access Macros:
1760  *
1761  */
1762 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_2_SEL register field. */
1763 #define ALT_PINMUX_SHARED_3V_IO_Q2_2_SEL_LSB 0
1764 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_2_SEL register field. */
1765 #define ALT_PINMUX_SHARED_3V_IO_Q2_2_SEL_MSB 3
1766 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_2_SEL register field. */
1767 #define ALT_PINMUX_SHARED_3V_IO_Q2_2_SEL_WIDTH 4
1768 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_2_SEL register field value. */
1769 #define ALT_PINMUX_SHARED_3V_IO_Q2_2_SEL_SET_MSK 0x0000000f
1770 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_2_SEL register field value. */
1771 #define ALT_PINMUX_SHARED_3V_IO_Q2_2_SEL_CLR_MSK 0xfffffff0
1772 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_2_SEL register field. */
1773 #define ALT_PINMUX_SHARED_3V_IO_Q2_2_SEL_RESET 0xf
1774 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_2_SEL field value from a register. */
1775 #define ALT_PINMUX_SHARED_3V_IO_Q2_2_SEL_GET(value) (((value) & 0x0000000f) >> 0)
1776 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_2_SEL register field value suitable for setting the register. */
1777 #define ALT_PINMUX_SHARED_3V_IO_Q2_2_SEL_SET(value) (((value) << 0) & 0x0000000f)
1778 
1779 /*
1780  * Field : Reserved
1781  *
1782  * Reserved
1783  *
1784  * Field Access Macros:
1785  *
1786  */
1787 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_2_RSVD register field. */
1788 #define ALT_PINMUX_SHARED_3V_IO_Q2_2_RSVD_LSB 4
1789 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_2_RSVD register field. */
1790 #define ALT_PINMUX_SHARED_3V_IO_Q2_2_RSVD_MSB 31
1791 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_2_RSVD register field. */
1792 #define ALT_PINMUX_SHARED_3V_IO_Q2_2_RSVD_WIDTH 28
1793 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_2_RSVD register field value. */
1794 #define ALT_PINMUX_SHARED_3V_IO_Q2_2_RSVD_SET_MSK 0xfffffff0
1795 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_2_RSVD register field value. */
1796 #define ALT_PINMUX_SHARED_3V_IO_Q2_2_RSVD_CLR_MSK 0x0000000f
1797 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_2_RSVD register field. */
1798 #define ALT_PINMUX_SHARED_3V_IO_Q2_2_RSVD_RESET 0x0
1799 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_2_RSVD field value from a register. */
1800 #define ALT_PINMUX_SHARED_3V_IO_Q2_2_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
1801 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_2_RSVD register field value suitable for setting the register. */
1802 #define ALT_PINMUX_SHARED_3V_IO_Q2_2_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
1803 
1804 #ifndef __ASSEMBLY__
1805 /*
1806  * WARNING: The C register and register group struct declarations are provided for
1807  * convenience and illustrative purposes. They should, however, be used with
1808  * caution as the C language standard provides no guarantees about the alignment or
1809  * atomicity of device memory accesses. The recommended practice for writing
1810  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1811  * alt_write_word() functions.
1812  *
1813  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_2.
1814  */
1815 struct ALT_PINMUX_SHARED_3V_IO_Q2_2_s
1816 {
1817  uint32_t sel : 4; /* Shared IO48 Q2 2 Mux Selection Field */
1818  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q2_2_RSVD */
1819 };
1820 
1821 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_2. */
1822 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q2_2_s ALT_PINMUX_SHARED_3V_IO_Q2_2_t;
1823 #endif /* __ASSEMBLY__ */
1824 
1825 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_2 register. */
1826 #define ALT_PINMUX_SHARED_3V_IO_Q2_2_RESET 0x0000000f
1827 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q2_2 register from the beginning of the component. */
1828 #define ALT_PINMUX_SHARED_3V_IO_Q2_2_OFST 0x34
1829 
1830 /*
1831  * Register : Shared IO 48 Q2 3 Mux Selection Register - pinmux_shared_io_q2_3
1832  *
1833  * This register is used to control the peripherals connected to shared IO48 pin Q2
1834  * 3
1835  *
1836  * Only reset by a cold reset (ignores warm reset).
1837  *
1838  * NOTE: These registers should not be modified after IO configuration.There is no
1839  * support for dynamically changing the Pin Mux selections.
1840  *
1841  * Register Layout
1842  *
1843  * Bits | Access | Reset | Description
1844  * :-------|:-------|:------|:-------------------------------------
1845  * [3:0] | RW | 0xf | Shared IO48 Q2 3 Mux Selection Field
1846  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q2_3_RSVD
1847  *
1848  */
1849 /*
1850  * Field : Shared IO48 Q2 3 Mux Selection Field - sel
1851  *
1852  * Select peripheral signals connected shared IO48 Q2 3
1853  *
1854  * 0000 (0) Pin is connected to Peripheral signal not applicable
1855  *
1856  * 0001 (1) Pin is connected to Peripheral signal not applicable
1857  *
1858  * 0010 (2) Pin is connected to Peripheral signal not applicable
1859  *
1860  * 0011 (3) Pin is connected to Peripheral signal not applicable
1861  *
1862  * 0100 (4) Pin is connected to Peripheral signal emac0.rx_clk
1863  *
1864  * 0101 (5) Pin is connected to Peripheral signal not applicable
1865  *
1866  * 0110 (6) Pin is connected to Peripheral signal not applicable
1867  *
1868  * 0111 (7) Pin is connected to Peripheral signal not applicable
1869  *
1870  * 1000 (8) Pin is connected to Peripheral signal usb1.dir
1871  *
1872  * 1001 (9) Pin is connected to Peripheral signal not applicable
1873  *
1874  * 1010 (10) Pin is connected to Peripheral signal not applicable
1875  *
1876  * 1011 (11) Pin is connected to Peripheral signal not applicable
1877  *
1878  * 1100 (12) Pin is connected to Peripheral signal not applicable
1879  *
1880  * 1101 (13) Pin is connected to Peripheral signal not applicable
1881  *
1882  * 1110 (14) Pin is connected to Peripheral signal nand.ce_n
1883  *
1884  * 1111 (15) Pin is connected to Peripheral signal gpio0.io14
1885  *
1886  * Field Access Macros:
1887  *
1888  */
1889 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_3_SEL register field. */
1890 #define ALT_PINMUX_SHARED_3V_IO_Q2_3_SEL_LSB 0
1891 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_3_SEL register field. */
1892 #define ALT_PINMUX_SHARED_3V_IO_Q2_3_SEL_MSB 3
1893 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_3_SEL register field. */
1894 #define ALT_PINMUX_SHARED_3V_IO_Q2_3_SEL_WIDTH 4
1895 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_3_SEL register field value. */
1896 #define ALT_PINMUX_SHARED_3V_IO_Q2_3_SEL_SET_MSK 0x0000000f
1897 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_3_SEL register field value. */
1898 #define ALT_PINMUX_SHARED_3V_IO_Q2_3_SEL_CLR_MSK 0xfffffff0
1899 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_3_SEL register field. */
1900 #define ALT_PINMUX_SHARED_3V_IO_Q2_3_SEL_RESET 0xf
1901 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_3_SEL field value from a register. */
1902 #define ALT_PINMUX_SHARED_3V_IO_Q2_3_SEL_GET(value) (((value) & 0x0000000f) >> 0)
1903 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_3_SEL register field value suitable for setting the register. */
1904 #define ALT_PINMUX_SHARED_3V_IO_Q2_3_SEL_SET(value) (((value) << 0) & 0x0000000f)
1905 
1906 /*
1907  * Field : Reserved
1908  *
1909  * Reserved
1910  *
1911  * Field Access Macros:
1912  *
1913  */
1914 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_3_RSVD register field. */
1915 #define ALT_PINMUX_SHARED_3V_IO_Q2_3_RSVD_LSB 4
1916 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_3_RSVD register field. */
1917 #define ALT_PINMUX_SHARED_3V_IO_Q2_3_RSVD_MSB 31
1918 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_3_RSVD register field. */
1919 #define ALT_PINMUX_SHARED_3V_IO_Q2_3_RSVD_WIDTH 28
1920 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_3_RSVD register field value. */
1921 #define ALT_PINMUX_SHARED_3V_IO_Q2_3_RSVD_SET_MSK 0xfffffff0
1922 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_3_RSVD register field value. */
1923 #define ALT_PINMUX_SHARED_3V_IO_Q2_3_RSVD_CLR_MSK 0x0000000f
1924 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_3_RSVD register field. */
1925 #define ALT_PINMUX_SHARED_3V_IO_Q2_3_RSVD_RESET 0x0
1926 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_3_RSVD field value from a register. */
1927 #define ALT_PINMUX_SHARED_3V_IO_Q2_3_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
1928 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_3_RSVD register field value suitable for setting the register. */
1929 #define ALT_PINMUX_SHARED_3V_IO_Q2_3_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
1930 
1931 #ifndef __ASSEMBLY__
1932 /*
1933  * WARNING: The C register and register group struct declarations are provided for
1934  * convenience and illustrative purposes. They should, however, be used with
1935  * caution as the C language standard provides no guarantees about the alignment or
1936  * atomicity of device memory accesses. The recommended practice for writing
1937  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1938  * alt_write_word() functions.
1939  *
1940  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_3.
1941  */
1942 struct ALT_PINMUX_SHARED_3V_IO_Q2_3_s
1943 {
1944  uint32_t sel : 4; /* Shared IO48 Q2 3 Mux Selection Field */
1945  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q2_3_RSVD */
1946 };
1947 
1948 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_3. */
1949 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q2_3_s ALT_PINMUX_SHARED_3V_IO_Q2_3_t;
1950 #endif /* __ASSEMBLY__ */
1951 
1952 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_3 register. */
1953 #define ALT_PINMUX_SHARED_3V_IO_Q2_3_RESET 0x0000000f
1954 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q2_3 register from the beginning of the component. */
1955 #define ALT_PINMUX_SHARED_3V_IO_Q2_3_OFST 0x38
1956 
1957 /*
1958  * Register : Shared IO 48 Q2 4 Mux Selection Register - pinmux_shared_io_q2_4
1959  *
1960  * This register is used to control the peripherals connected to shared IO48 pin Q2
1961  * 4
1962  *
1963  * Only reset by a cold reset (ignores warm reset).
1964  *
1965  * NOTE: These registers should not be modified after IO configuration.There is no
1966  * support for dynamically changing the Pin Mux selections.
1967  *
1968  * Register Layout
1969  *
1970  * Bits | Access | Reset | Description
1971  * :-------|:-------|:------|:-------------------------------------
1972  * [3:0] | RW | 0xf | Shared IO48 Q2 4 Mux Selection Field
1973  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q2_4_RSVD
1974  *
1975  */
1976 /*
1977  * Field : Shared IO48 Q2 4 Mux Selection Field - sel
1978  *
1979  * Select peripheral signals connected shared IO48 Q2 4
1980  *
1981  * 0000 (0) Pin is connected to Peripheral signal not applicable
1982  *
1983  * 0001 (1) Pin is connected to Peripheral signal not applicable
1984  *
1985  * 0010 (2) Pin is connected to Peripheral signal not applicable
1986  *
1987  * 0011 (3) Pin is connected to Peripheral signal not applicable
1988  *
1989  * 0100 (4) Pin is connected to Peripheral signal emac0.rx_ctl
1990  *
1991  * 0101 (5) Pin is connected to Peripheral signal not applicable
1992  *
1993  * 0110 (6) Pin is connected to Peripheral signal not applicable
1994  *
1995  * 0111 (7) Pin is connected to Peripheral signal not applicable
1996  *
1997  * 1000 (8) Pin is connected to Peripheral signal usb1.data0
1998  *
1999  * 1001 (9) Pin is connected to Peripheral signal not applicable
2000  *
2001  * 1010 (10) Pin is connected to Peripheral signal not applicable
2002  *
2003  * 1011 (11) Pin is connected to Peripheral signal not applicable
2004  *
2005  * 1100 (12) Pin is connected to Peripheral signal not applicable
2006  *
2007  * 1101 (13) Pin is connected to Peripheral signal not applicable
2008  *
2009  * 1110 (14) Pin is connected to Peripheral signal not applicable
2010  *
2011  * 1111 (15) Pin is connected to Peripheral signal gpio0.io15
2012  *
2013  * Field Access Macros:
2014  *
2015  */
2016 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_4_SEL register field. */
2017 #define ALT_PINMUX_SHARED_3V_IO_Q2_4_SEL_LSB 0
2018 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_4_SEL register field. */
2019 #define ALT_PINMUX_SHARED_3V_IO_Q2_4_SEL_MSB 3
2020 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_4_SEL register field. */
2021 #define ALT_PINMUX_SHARED_3V_IO_Q2_4_SEL_WIDTH 4
2022 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_4_SEL register field value. */
2023 #define ALT_PINMUX_SHARED_3V_IO_Q2_4_SEL_SET_MSK 0x0000000f
2024 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_4_SEL register field value. */
2025 #define ALT_PINMUX_SHARED_3V_IO_Q2_4_SEL_CLR_MSK 0xfffffff0
2026 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_4_SEL register field. */
2027 #define ALT_PINMUX_SHARED_3V_IO_Q2_4_SEL_RESET 0xf
2028 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_4_SEL field value from a register. */
2029 #define ALT_PINMUX_SHARED_3V_IO_Q2_4_SEL_GET(value) (((value) & 0x0000000f) >> 0)
2030 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_4_SEL register field value suitable for setting the register. */
2031 #define ALT_PINMUX_SHARED_3V_IO_Q2_4_SEL_SET(value) (((value) << 0) & 0x0000000f)
2032 
2033 /*
2034  * Field : Reserved
2035  *
2036  * Reserved
2037  *
2038  * Field Access Macros:
2039  *
2040  */
2041 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_4_RSVD register field. */
2042 #define ALT_PINMUX_SHARED_3V_IO_Q2_4_RSVD_LSB 4
2043 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_4_RSVD register field. */
2044 #define ALT_PINMUX_SHARED_3V_IO_Q2_4_RSVD_MSB 31
2045 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_4_RSVD register field. */
2046 #define ALT_PINMUX_SHARED_3V_IO_Q2_4_RSVD_WIDTH 28
2047 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_4_RSVD register field value. */
2048 #define ALT_PINMUX_SHARED_3V_IO_Q2_4_RSVD_SET_MSK 0xfffffff0
2049 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_4_RSVD register field value. */
2050 #define ALT_PINMUX_SHARED_3V_IO_Q2_4_RSVD_CLR_MSK 0x0000000f
2051 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_4_RSVD register field. */
2052 #define ALT_PINMUX_SHARED_3V_IO_Q2_4_RSVD_RESET 0x0
2053 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_4_RSVD field value from a register. */
2054 #define ALT_PINMUX_SHARED_3V_IO_Q2_4_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
2055 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_4_RSVD register field value suitable for setting the register. */
2056 #define ALT_PINMUX_SHARED_3V_IO_Q2_4_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
2057 
2058 #ifndef __ASSEMBLY__
2059 /*
2060  * WARNING: The C register and register group struct declarations are provided for
2061  * convenience and illustrative purposes. They should, however, be used with
2062  * caution as the C language standard provides no guarantees about the alignment or
2063  * atomicity of device memory accesses. The recommended practice for writing
2064  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2065  * alt_write_word() functions.
2066  *
2067  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_4.
2068  */
2069 struct ALT_PINMUX_SHARED_3V_IO_Q2_4_s
2070 {
2071  uint32_t sel : 4; /* Shared IO48 Q2 4 Mux Selection Field */
2072  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q2_4_RSVD */
2073 };
2074 
2075 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_4. */
2076 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q2_4_s ALT_PINMUX_SHARED_3V_IO_Q2_4_t;
2077 #endif /* __ASSEMBLY__ */
2078 
2079 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_4 register. */
2080 #define ALT_PINMUX_SHARED_3V_IO_Q2_4_RESET 0x0000000f
2081 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q2_4 register from the beginning of the component. */
2082 #define ALT_PINMUX_SHARED_3V_IO_Q2_4_OFST 0x3c
2083 
2084 /*
2085  * Register : Shared IO 48 Q2 5 Mux Selection Register - pinmux_shared_io_q2_5
2086  *
2087  * This register is used to control the peripherals connected to shared IO48 pin Q2
2088  * 5
2089  *
2090  * Only reset by a cold reset (ignores warm reset).
2091  *
2092  * NOTE: These registers should not be modified after IO configuration.There is no
2093  * support for dynamically changing the Pin Mux selections.
2094  *
2095  * Register Layout
2096  *
2097  * Bits | Access | Reset | Description
2098  * :-------|:-------|:------|:-------------------------------------
2099  * [3:0] | RW | 0xf | Shared IO48 Q2 5 Mux Selection Field
2100  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD
2101  *
2102  */
2103 /*
2104  * Field : Shared IO48 Q2 5 Mux Selection Field - sel
2105  *
2106  * Select peripheral signals connected shared IO48 Q2 5
2107  *
2108  * 0000 (0) Pin is connected to Peripheral signal not applicable
2109  *
2110  * 0001 (1) Pin is connected to Peripheral signal not applicable
2111  *
2112  * 0010 (2) Pin is connected to Peripheral signal not applicable
2113  *
2114  * 0011 (3) Pin is connected to Peripheral signal not applicable
2115  *
2116  * 0100 (4) Pin is connected to Peripheral signal emac0.txd0
2117  *
2118  * 0101 (5) Pin is connected to Peripheral signal not applicable
2119  *
2120  * 0110 (6) Pin is connected to Peripheral signal not applicable
2121  *
2122  * 0111 (7) Pin is connected to Peripheral signal not applicable
2123  *
2124  * 1000 (8) Pin is connected to Peripheral signal usb1.data1
2125  *
2126  * 1001 (9) Pin is connected to Peripheral signal not applicable
2127  *
2128  * 1010 (10) Pin is connected to Peripheral signal not applicable
2129  *
2130  * 1011 (11) Pin is connected to Peripheral signal not applicable
2131  *
2132  * 1100 (12) Pin is connected to Peripheral signal not applicable
2133  *
2134  * 1101 (13) Pin is connected to Peripheral signal not applicable
2135  *
2136  * 1110 (14) Pin is connected to Peripheral signal nand.adq8
2137  *
2138  * 1111 (15) Pin is connected to Peripheral signal gpio0.io16
2139  *
2140  * Field Access Macros:
2141  *
2142  */
2143 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL register field. */
2144 #define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_LSB 0
2145 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL register field. */
2146 #define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_MSB 3
2147 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL register field. */
2148 #define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_WIDTH 4
2149 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL register field value. */
2150 #define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_SET_MSK 0x0000000f
2151 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL register field value. */
2152 #define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_CLR_MSK 0xfffffff0
2153 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL register field. */
2154 #define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_RESET 0xf
2155 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL field value from a register. */
2156 #define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_GET(value) (((value) & 0x0000000f) >> 0)
2157 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL register field value suitable for setting the register. */
2158 #define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_SET(value) (((value) << 0) & 0x0000000f)
2159 
2160 /*
2161  * Field : Reserved
2162  *
2163  * Reserved
2164  *
2165  * Field Access Macros:
2166  *
2167  */
2168 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD register field. */
2169 #define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_LSB 4
2170 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD register field. */
2171 #define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_MSB 31
2172 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD register field. */
2173 #define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_WIDTH 28
2174 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD register field value. */
2175 #define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_SET_MSK 0xfffffff0
2176 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD register field value. */
2177 #define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_CLR_MSK 0x0000000f
2178 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD register field. */
2179 #define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_RESET 0x0
2180 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD field value from a register. */
2181 #define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
2182 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD register field value suitable for setting the register. */
2183 #define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
2184 
2185 #ifndef __ASSEMBLY__
2186 /*
2187  * WARNING: The C register and register group struct declarations are provided for
2188  * convenience and illustrative purposes. They should, however, be used with
2189  * caution as the C language standard provides no guarantees about the alignment or
2190  * atomicity of device memory accesses. The recommended practice for writing
2191  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2192  * alt_write_word() functions.
2193  *
2194  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_5.
2195  */
2196 struct ALT_PINMUX_SHARED_3V_IO_Q2_5_s
2197 {
2198  uint32_t sel : 4; /* Shared IO48 Q2 5 Mux Selection Field */
2199  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD */
2200 };
2201 
2202 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_5. */
2203 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q2_5_s ALT_PINMUX_SHARED_3V_IO_Q2_5_t;
2204 #endif /* __ASSEMBLY__ */
2205 
2206 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_5 register. */
2207 #define ALT_PINMUX_SHARED_3V_IO_Q2_5_RESET 0x0000000f
2208 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q2_5 register from the beginning of the component. */
2209 #define ALT_PINMUX_SHARED_3V_IO_Q2_5_OFST 0x40
2210 
2211 /*
2212  * Register : Shared IO 48 Q2 6 Mux Selection Register - pinmux_shared_io_q2_6
2213  *
2214  * This register is used to control the peripherals connected to shared IO48 pin Q2
2215  * 6
2216  *
2217  * Only reset by a cold reset (ignores warm reset).
2218  *
2219  * NOTE: These registers should not be modified after IO configuration.There is no
2220  * support for dynamically changing the Pin Mux selections.
2221  *
2222  * Register Layout
2223  *
2224  * Bits | Access | Reset | Description
2225  * :-------|:-------|:------|:-------------------------------------
2226  * [3:0] | RW | 0xf | Shared IO48 Q2 6 Mux Selection Field
2227  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q2_6_RSVD
2228  *
2229  */
2230 /*
2231  * Field : Shared IO48 Q2 6 Mux Selection Field - sel
2232  *
2233  * Select peripheral signals connected shared IO48 Q2 6
2234  *
2235  * 0000 (0) Pin is connected to Peripheral signal not applicable
2236  *
2237  * 0001 (1) Pin is connected to Peripheral signal not applicable
2238  *
2239  * 0010 (2) Pin is connected to Peripheral signal not applicable
2240  *
2241  * 0011 (3) Pin is connected to Peripheral signal not applicable
2242  *
2243  * 0100 (4) Pin is connected to Peripheral signal emac0.txd1
2244  *
2245  * 0101 (5) Pin is connected to Peripheral signal not applicable
2246  *
2247  * 0110 (6) Pin is connected to Peripheral signal not applicable
2248  *
2249  * 0111 (7) Pin is connected to Peripheral signal not applicable
2250  *
2251  * 1000 (8) Pin is connected to Peripheral signal usb1.nxt
2252  *
2253  * 1001 (9) Pin is connected to Peripheral signal not applicable
2254  *
2255  * 1010 (10) Pin is connected to Peripheral signal not applicable
2256  *
2257  * 1011 (11) Pin is connected to Peripheral signal not applicable
2258  *
2259  * 1100 (12) Pin is connected to Peripheral signal not applicable
2260  *
2261  * 1101 (13) Pin is connected to Peripheral signal not applicable
2262  *
2263  * 1110 (14) Pin is connected to Peripheral signal nand.adq9
2264  *
2265  * 1111 (15) Pin is connected to Peripheral signal gpio0.io17
2266  *
2267  * Field Access Macros:
2268  *
2269  */
2270 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_6_SEL register field. */
2271 #define ALT_PINMUX_SHARED_3V_IO_Q2_6_SEL_LSB 0
2272 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_6_SEL register field. */
2273 #define ALT_PINMUX_SHARED_3V_IO_Q2_6_SEL_MSB 3
2274 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_6_SEL register field. */
2275 #define ALT_PINMUX_SHARED_3V_IO_Q2_6_SEL_WIDTH 4
2276 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_6_SEL register field value. */
2277 #define ALT_PINMUX_SHARED_3V_IO_Q2_6_SEL_SET_MSK 0x0000000f
2278 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_6_SEL register field value. */
2279 #define ALT_PINMUX_SHARED_3V_IO_Q2_6_SEL_CLR_MSK 0xfffffff0
2280 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_6_SEL register field. */
2281 #define ALT_PINMUX_SHARED_3V_IO_Q2_6_SEL_RESET 0xf
2282 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_6_SEL field value from a register. */
2283 #define ALT_PINMUX_SHARED_3V_IO_Q2_6_SEL_GET(value) (((value) & 0x0000000f) >> 0)
2284 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_6_SEL register field value suitable for setting the register. */
2285 #define ALT_PINMUX_SHARED_3V_IO_Q2_6_SEL_SET(value) (((value) << 0) & 0x0000000f)
2286 
2287 /*
2288  * Field : Reserved
2289  *
2290  * Reserved
2291  *
2292  * Field Access Macros:
2293  *
2294  */
2295 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_6_RSVD register field. */
2296 #define ALT_PINMUX_SHARED_3V_IO_Q2_6_RSVD_LSB 4
2297 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_6_RSVD register field. */
2298 #define ALT_PINMUX_SHARED_3V_IO_Q2_6_RSVD_MSB 31
2299 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_6_RSVD register field. */
2300 #define ALT_PINMUX_SHARED_3V_IO_Q2_6_RSVD_WIDTH 28
2301 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_6_RSVD register field value. */
2302 #define ALT_PINMUX_SHARED_3V_IO_Q2_6_RSVD_SET_MSK 0xfffffff0
2303 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_6_RSVD register field value. */
2304 #define ALT_PINMUX_SHARED_3V_IO_Q2_6_RSVD_CLR_MSK 0x0000000f
2305 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_6_RSVD register field. */
2306 #define ALT_PINMUX_SHARED_3V_IO_Q2_6_RSVD_RESET 0x0
2307 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_6_RSVD field value from a register. */
2308 #define ALT_PINMUX_SHARED_3V_IO_Q2_6_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
2309 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_6_RSVD register field value suitable for setting the register. */
2310 #define ALT_PINMUX_SHARED_3V_IO_Q2_6_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
2311 
2312 #ifndef __ASSEMBLY__
2313 /*
2314  * WARNING: The C register and register group struct declarations are provided for
2315  * convenience and illustrative purposes. They should, however, be used with
2316  * caution as the C language standard provides no guarantees about the alignment or
2317  * atomicity of device memory accesses. The recommended practice for writing
2318  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2319  * alt_write_word() functions.
2320  *
2321  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_6.
2322  */
2323 struct ALT_PINMUX_SHARED_3V_IO_Q2_6_s
2324 {
2325  uint32_t sel : 4; /* Shared IO48 Q2 6 Mux Selection Field */
2326  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q2_6_RSVD */
2327 };
2328 
2329 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_6. */
2330 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q2_6_s ALT_PINMUX_SHARED_3V_IO_Q2_6_t;
2331 #endif /* __ASSEMBLY__ */
2332 
2333 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_6 register. */
2334 #define ALT_PINMUX_SHARED_3V_IO_Q2_6_RESET 0x0000000f
2335 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q2_6 register from the beginning of the component. */
2336 #define ALT_PINMUX_SHARED_3V_IO_Q2_6_OFST 0x44
2337 
2338 /*
2339  * Register : Shared IO 48 Q2 7 Mux Selection Register - pinmux_shared_io_q2_7
2340  *
2341  * This register is used to control the peripherals connected to shared IO48 pin Q2
2342  * 7
2343  *
2344  * Only reset by a cold reset (ignores warm reset).
2345  *
2346  * NOTE: These registers should not be modified after IO configuration.There is no
2347  * support for dynamically changing the Pin Mux selections.
2348  *
2349  * Register Layout
2350  *
2351  * Bits | Access | Reset | Description
2352  * :-------|:-------|:------|:-------------------------------------
2353  * [3:0] | RW | 0xf | Shared IO48 Q2 7 Mux Selection Field
2354  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q2_7_RSVD
2355  *
2356  */
2357 /*
2358  * Field : Shared IO48 Q2 7 Mux Selection Field - sel
2359  *
2360  * Select peripheral signals connected shared IO48 Q2 7
2361  *
2362  * 0000 (0) Pin is connected to Peripheral signal not applicable
2363  *
2364  * 0001 (1) Pin is connected to Peripheral signal not applicable
2365  *
2366  * 0010 (2) Pin is connected to Peripheral signal not applicable
2367  *
2368  * 0011 (3) Pin is connected to Peripheral signal not applicable
2369  *
2370  * 0100 (4) Pin is connected to Peripheral signal emac0.rxd0
2371  *
2372  * 0101 (5) Pin is connected to Peripheral signal not applicable
2373  *
2374  * 0110 (6) Pin is connected to Peripheral signal not applicable
2375  *
2376  * 0111 (7) Pin is connected to Peripheral signal not applicable
2377  *
2378  * 1000 (8) Pin is connected to Peripheral signal usb1.data2
2379  *
2380  * 1001 (9) Pin is connected to Peripheral signal not applicable
2381  *
2382  * 1010 (10) Pin is connected to Peripheral signal not applicable
2383  *
2384  * 1011 (11) Pin is connected to Peripheral signal not applicable
2385  *
2386  * 1100 (12) Pin is connected to Peripheral signal not applicable
2387  *
2388  * 1101 (13) Pin is connected to Peripheral signal not applicable
2389  *
2390  * 1110 (14) Pin is connected to Peripheral signal nand.adq10
2391  *
2392  * 1111 (15) Pin is connected to Peripheral signal gpio0.io18
2393  *
2394  * Field Access Macros:
2395  *
2396  */
2397 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_7_SEL register field. */
2398 #define ALT_PINMUX_SHARED_3V_IO_Q2_7_SEL_LSB 0
2399 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_7_SEL register field. */
2400 #define ALT_PINMUX_SHARED_3V_IO_Q2_7_SEL_MSB 3
2401 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_7_SEL register field. */
2402 #define ALT_PINMUX_SHARED_3V_IO_Q2_7_SEL_WIDTH 4
2403 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_7_SEL register field value. */
2404 #define ALT_PINMUX_SHARED_3V_IO_Q2_7_SEL_SET_MSK 0x0000000f
2405 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_7_SEL register field value. */
2406 #define ALT_PINMUX_SHARED_3V_IO_Q2_7_SEL_CLR_MSK 0xfffffff0
2407 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_7_SEL register field. */
2408 #define ALT_PINMUX_SHARED_3V_IO_Q2_7_SEL_RESET 0xf
2409 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_7_SEL field value from a register. */
2410 #define ALT_PINMUX_SHARED_3V_IO_Q2_7_SEL_GET(value) (((value) & 0x0000000f) >> 0)
2411 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_7_SEL register field value suitable for setting the register. */
2412 #define ALT_PINMUX_SHARED_3V_IO_Q2_7_SEL_SET(value) (((value) << 0) & 0x0000000f)
2413 
2414 /*
2415  * Field : Reserved
2416  *
2417  * Reserved
2418  *
2419  * Field Access Macros:
2420  *
2421  */
2422 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_7_RSVD register field. */
2423 #define ALT_PINMUX_SHARED_3V_IO_Q2_7_RSVD_LSB 4
2424 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_7_RSVD register field. */
2425 #define ALT_PINMUX_SHARED_3V_IO_Q2_7_RSVD_MSB 31
2426 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_7_RSVD register field. */
2427 #define ALT_PINMUX_SHARED_3V_IO_Q2_7_RSVD_WIDTH 28
2428 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_7_RSVD register field value. */
2429 #define ALT_PINMUX_SHARED_3V_IO_Q2_7_RSVD_SET_MSK 0xfffffff0
2430 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_7_RSVD register field value. */
2431 #define ALT_PINMUX_SHARED_3V_IO_Q2_7_RSVD_CLR_MSK 0x0000000f
2432 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_7_RSVD register field. */
2433 #define ALT_PINMUX_SHARED_3V_IO_Q2_7_RSVD_RESET 0x0
2434 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_7_RSVD field value from a register. */
2435 #define ALT_PINMUX_SHARED_3V_IO_Q2_7_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
2436 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_7_RSVD register field value suitable for setting the register. */
2437 #define ALT_PINMUX_SHARED_3V_IO_Q2_7_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
2438 
2439 #ifndef __ASSEMBLY__
2440 /*
2441  * WARNING: The C register and register group struct declarations are provided for
2442  * convenience and illustrative purposes. They should, however, be used with
2443  * caution as the C language standard provides no guarantees about the alignment or
2444  * atomicity of device memory accesses. The recommended practice for writing
2445  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2446  * alt_write_word() functions.
2447  *
2448  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_7.
2449  */
2450 struct ALT_PINMUX_SHARED_3V_IO_Q2_7_s
2451 {
2452  uint32_t sel : 4; /* Shared IO48 Q2 7 Mux Selection Field */
2453  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q2_7_RSVD */
2454 };
2455 
2456 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_7. */
2457 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q2_7_s ALT_PINMUX_SHARED_3V_IO_Q2_7_t;
2458 #endif /* __ASSEMBLY__ */
2459 
2460 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_7 register. */
2461 #define ALT_PINMUX_SHARED_3V_IO_Q2_7_RESET 0x0000000f
2462 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q2_7 register from the beginning of the component. */
2463 #define ALT_PINMUX_SHARED_3V_IO_Q2_7_OFST 0x48
2464 
2465 /*
2466  * Register : Shared IO 48 Q2 8 Mux Selection Register - pinmux_shared_io_q2_8
2467  *
2468  * This register is used to control the peripherals connected to shared IO48 pin Q2
2469  * 8
2470  *
2471  * Only reset by a cold reset (ignores warm reset).
2472  *
2473  * NOTE: These registers should not be modified after IO configuration.There is no
2474  * support for dynamically changing the Pin Mux selections.
2475  *
2476  * Register Layout
2477  *
2478  * Bits | Access | Reset | Description
2479  * :-------|:-------|:------|:-------------------------------------
2480  * [3:0] | RW | 0xf | Shared IO48 Q2 8 Mux Selection Field
2481  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q2_8_RSVD
2482  *
2483  */
2484 /*
2485  * Field : Shared IO48 Q2 8 Mux Selection Field - sel
2486  *
2487  * Select peripheral signals connected shared IO48 Q2 8
2488  *
2489  * 0000 (0) Pin is connected to Peripheral signal not applicable
2490  *
2491  * 0001 (1) Pin is connected to Peripheral signal not applicable
2492  *
2493  * 0010 (2) Pin is connected to Peripheral signal not applicable
2494  *
2495  * 0011 (3) Pin is connected to Peripheral signal spim1.ss1_n
2496  *
2497  * 0100 (4) Pin is connected to Peripheral signal emac0.rxd1
2498  *
2499  * 0101 (5) Pin is connected to Peripheral signal not applicable
2500  *
2501  * 0110 (6) Pin is connected to Peripheral signal not applicable
2502  *
2503  * 0111 (7) Pin is connected to Peripheral signal not applicable
2504  *
2505  * 1000 (8) Pin is connected to Peripheral signal usb1.data3
2506  *
2507  * 1001 (9) Pin is connected to Peripheral signal not applicable
2508  *
2509  * 1010 (10) Pin is connected to Peripheral signal not applicable
2510  *
2511  * 1011 (11) Pin is connected to Peripheral signal not applicable
2512  *
2513  * 1100 (12) Pin is connected to Peripheral signal not applicable
2514  *
2515  * 1101 (13) Pin is connected to Peripheral signal not applicable
2516  *
2517  * 1110 (14) Pin is connected to Peripheral signal nand.adq11
2518  *
2519  * 1111 (15) Pin is connected to Peripheral signal gpio0.io19
2520  *
2521  * Field Access Macros:
2522  *
2523  */
2524 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_8_SEL register field. */
2525 #define ALT_PINMUX_SHARED_3V_IO_Q2_8_SEL_LSB 0
2526 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_8_SEL register field. */
2527 #define ALT_PINMUX_SHARED_3V_IO_Q2_8_SEL_MSB 3
2528 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_8_SEL register field. */
2529 #define ALT_PINMUX_SHARED_3V_IO_Q2_8_SEL_WIDTH 4
2530 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_8_SEL register field value. */
2531 #define ALT_PINMUX_SHARED_3V_IO_Q2_8_SEL_SET_MSK 0x0000000f
2532 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_8_SEL register field value. */
2533 #define ALT_PINMUX_SHARED_3V_IO_Q2_8_SEL_CLR_MSK 0xfffffff0
2534 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_8_SEL register field. */
2535 #define ALT_PINMUX_SHARED_3V_IO_Q2_8_SEL_RESET 0xf
2536 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_8_SEL field value from a register. */
2537 #define ALT_PINMUX_SHARED_3V_IO_Q2_8_SEL_GET(value) (((value) & 0x0000000f) >> 0)
2538 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_8_SEL register field value suitable for setting the register. */
2539 #define ALT_PINMUX_SHARED_3V_IO_Q2_8_SEL_SET(value) (((value) << 0) & 0x0000000f)
2540 
2541 /*
2542  * Field : Reserved
2543  *
2544  * Reserved
2545  *
2546  * Field Access Macros:
2547  *
2548  */
2549 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_8_RSVD register field. */
2550 #define ALT_PINMUX_SHARED_3V_IO_Q2_8_RSVD_LSB 4
2551 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_8_RSVD register field. */
2552 #define ALT_PINMUX_SHARED_3V_IO_Q2_8_RSVD_MSB 31
2553 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_8_RSVD register field. */
2554 #define ALT_PINMUX_SHARED_3V_IO_Q2_8_RSVD_WIDTH 28
2555 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_8_RSVD register field value. */
2556 #define ALT_PINMUX_SHARED_3V_IO_Q2_8_RSVD_SET_MSK 0xfffffff0
2557 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_8_RSVD register field value. */
2558 #define ALT_PINMUX_SHARED_3V_IO_Q2_8_RSVD_CLR_MSK 0x0000000f
2559 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_8_RSVD register field. */
2560 #define ALT_PINMUX_SHARED_3V_IO_Q2_8_RSVD_RESET 0x0
2561 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_8_RSVD field value from a register. */
2562 #define ALT_PINMUX_SHARED_3V_IO_Q2_8_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
2563 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_8_RSVD register field value suitable for setting the register. */
2564 #define ALT_PINMUX_SHARED_3V_IO_Q2_8_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
2565 
2566 #ifndef __ASSEMBLY__
2567 /*
2568  * WARNING: The C register and register group struct declarations are provided for
2569  * convenience and illustrative purposes. They should, however, be used with
2570  * caution as the C language standard provides no guarantees about the alignment or
2571  * atomicity of device memory accesses. The recommended practice for writing
2572  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2573  * alt_write_word() functions.
2574  *
2575  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_8.
2576  */
2577 struct ALT_PINMUX_SHARED_3V_IO_Q2_8_s
2578 {
2579  uint32_t sel : 4; /* Shared IO48 Q2 8 Mux Selection Field */
2580  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q2_8_RSVD */
2581 };
2582 
2583 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_8. */
2584 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q2_8_s ALT_PINMUX_SHARED_3V_IO_Q2_8_t;
2585 #endif /* __ASSEMBLY__ */
2586 
2587 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_8 register. */
2588 #define ALT_PINMUX_SHARED_3V_IO_Q2_8_RESET 0x0000000f
2589 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q2_8 register from the beginning of the component. */
2590 #define ALT_PINMUX_SHARED_3V_IO_Q2_8_OFST 0x4c
2591 
2592 /*
2593  * Register : Shared IO 48 Q2 9 Mux Selection Register - pinmux_shared_io_q2_9
2594  *
2595  * This register is used to control the peripherals connected to shared IO48 pin Q2
2596  * 9
2597  *
2598  * Only reset by a cold reset (ignores warm reset).
2599  *
2600  * NOTE: These registers should not be modified after IO configuration.There is no
2601  * support for dynamically changing the Pin Mux selections.
2602  *
2603  * Register Layout
2604  *
2605  * Bits | Access | Reset | Description
2606  * :-------|:-------|:------|:-------------------------------------
2607  * [3:0] | RW | 0xf | Shared IO48 Q2 9 Mux Selection Field
2608  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q2_9_RSVD
2609  *
2610  */
2611 /*
2612  * Field : Shared IO48 Q2 9 Mux Selection Field - sel
2613  *
2614  * Select peripheral signals connected shared IO48 Q2 9
2615  *
2616  * 0000 (0) Pin is connected to Peripheral signal i2c1.sda
2617  *
2618  * 0001 (1) Pin is connected to Peripheral signal not applicable
2619  *
2620  * 0010 (2) Pin is connected to Peripheral signal spis0.clk
2621  *
2622  * 0011 (3) Pin is connected to Peripheral signal spim1.clk
2623  *
2624  * 0100 (4) Pin is connected to Peripheral signal emac0.txd2
2625  *
2626  * 0101 (5) Pin is connected to Peripheral signal not applicable
2627  *
2628  * 0110 (6) Pin is connected to Peripheral signal not applicable
2629  *
2630  * 0111 (7) Pin is connected to Peripheral signal not applicable
2631  *
2632  * 1000 (8) Pin is connected to Peripheral signal usb1.data4
2633  *
2634  * 1001 (9) Pin is connected to Peripheral signal not applicable
2635  *
2636  * 1010 (10) Pin is connected to Peripheral signal not applicable
2637  *
2638  * 1011 (11) Pin is connected to Peripheral signal not applicable
2639  *
2640  * 1100 (12) Pin is connected to Peripheral signal not applicable
2641  *
2642  * 1101 (13) Pin is connected to Peripheral signal uart0.cts_n
2643  *
2644  * 1110 (14) Pin is connected to Peripheral signal nand.adq12
2645  *
2646  * 1111 (15) Pin is connected to Peripheral signal gpio0.io20
2647  *
2648  * Field Access Macros:
2649  *
2650  */
2651 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_9_SEL register field. */
2652 #define ALT_PINMUX_SHARED_3V_IO_Q2_9_SEL_LSB 0
2653 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_9_SEL register field. */
2654 #define ALT_PINMUX_SHARED_3V_IO_Q2_9_SEL_MSB 3
2655 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_9_SEL register field. */
2656 #define ALT_PINMUX_SHARED_3V_IO_Q2_9_SEL_WIDTH 4
2657 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_9_SEL register field value. */
2658 #define ALT_PINMUX_SHARED_3V_IO_Q2_9_SEL_SET_MSK 0x0000000f
2659 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_9_SEL register field value. */
2660 #define ALT_PINMUX_SHARED_3V_IO_Q2_9_SEL_CLR_MSK 0xfffffff0
2661 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_9_SEL register field. */
2662 #define ALT_PINMUX_SHARED_3V_IO_Q2_9_SEL_RESET 0xf
2663 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_9_SEL field value from a register. */
2664 #define ALT_PINMUX_SHARED_3V_IO_Q2_9_SEL_GET(value) (((value) & 0x0000000f) >> 0)
2665 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_9_SEL register field value suitable for setting the register. */
2666 #define ALT_PINMUX_SHARED_3V_IO_Q2_9_SEL_SET(value) (((value) << 0) & 0x0000000f)
2667 
2668 /*
2669  * Field : Reserved
2670  *
2671  * Reserved
2672  *
2673  * Field Access Macros:
2674  *
2675  */
2676 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_9_RSVD register field. */
2677 #define ALT_PINMUX_SHARED_3V_IO_Q2_9_RSVD_LSB 4
2678 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_9_RSVD register field. */
2679 #define ALT_PINMUX_SHARED_3V_IO_Q2_9_RSVD_MSB 31
2680 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_9_RSVD register field. */
2681 #define ALT_PINMUX_SHARED_3V_IO_Q2_9_RSVD_WIDTH 28
2682 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_9_RSVD register field value. */
2683 #define ALT_PINMUX_SHARED_3V_IO_Q2_9_RSVD_SET_MSK 0xfffffff0
2684 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_9_RSVD register field value. */
2685 #define ALT_PINMUX_SHARED_3V_IO_Q2_9_RSVD_CLR_MSK 0x0000000f
2686 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_9_RSVD register field. */
2687 #define ALT_PINMUX_SHARED_3V_IO_Q2_9_RSVD_RESET 0x0
2688 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_9_RSVD field value from a register. */
2689 #define ALT_PINMUX_SHARED_3V_IO_Q2_9_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
2690 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_9_RSVD register field value suitable for setting the register. */
2691 #define ALT_PINMUX_SHARED_3V_IO_Q2_9_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
2692 
2693 #ifndef __ASSEMBLY__
2694 /*
2695  * WARNING: The C register and register group struct declarations are provided for
2696  * convenience and illustrative purposes. They should, however, be used with
2697  * caution as the C language standard provides no guarantees about the alignment or
2698  * atomicity of device memory accesses. The recommended practice for writing
2699  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2700  * alt_write_word() functions.
2701  *
2702  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_9.
2703  */
2704 struct ALT_PINMUX_SHARED_3V_IO_Q2_9_s
2705 {
2706  uint32_t sel : 4; /* Shared IO48 Q2 9 Mux Selection Field */
2707  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q2_9_RSVD */
2708 };
2709 
2710 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_9. */
2711 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q2_9_s ALT_PINMUX_SHARED_3V_IO_Q2_9_t;
2712 #endif /* __ASSEMBLY__ */
2713 
2714 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_9 register. */
2715 #define ALT_PINMUX_SHARED_3V_IO_Q2_9_RESET 0x0000000f
2716 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q2_9 register from the beginning of the component. */
2717 #define ALT_PINMUX_SHARED_3V_IO_Q2_9_OFST 0x50
2718 
2719 /*
2720  * Register : Shared IO 48 Q2 10 Mux Selection Register - pinmux_shared_io_q2_10
2721  *
2722  * This register is used to control the peripherals connected to shared IO48 pin Q2
2723  * 10
2724  *
2725  * Only reset by a cold reset (ignores warm reset).
2726  *
2727  * NOTE: These registers should not be modified after IO configuration.There is no
2728  * support for dynamically changing the Pin Mux selections.
2729  *
2730  * Register Layout
2731  *
2732  * Bits | Access | Reset | Description
2733  * :-------|:-------|:------|:--------------------------------------
2734  * [3:0] | RW | 0xf | Shared IO48 Q2 10 Mux Selection Field
2735  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q2_10_RSVD
2736  *
2737  */
2738 /*
2739  * Field : Shared IO48 Q2 10 Mux Selection Field - sel
2740  *
2741  * Select peripheral signals connected shared IO48 Q2 10
2742  *
2743  * 0000 (0) Pin is connected to Peripheral signal i2c1.scl
2744  *
2745  * 0001 (1) Pin is connected to Peripheral signal not applicable
2746  *
2747  * 0010 (2) Pin is connected to Peripheral signal spis0.mosi
2748  *
2749  * 0011 (3) Pin is connected to Peripheral signal spim1.mosi
2750  *
2751  * 0100 (4) Pin is connected to Peripheral signal emac0.txd3
2752  *
2753  * 0101 (5) Pin is connected to Peripheral signal not applicable
2754  *
2755  * 0110 (6) Pin is connected to Peripheral signal not applicable
2756  *
2757  * 0111 (7) Pin is connected to Peripheral signal not applicable
2758  *
2759  * 1000 (8) Pin is connected to Peripheral signal usb1.data5
2760  *
2761  * 1001 (9) Pin is connected to Peripheral signal not applicable
2762  *
2763  * 1010 (10) Pin is connected to Peripheral signal not applicable
2764  *
2765  * 1011 (11) Pin is connected to Peripheral signal not applicable
2766  *
2767  * 1100 (12) Pin is connected to Peripheral signal not applicable
2768  *
2769  * 1101 (13) Pin is connected to Peripheral signal uart0.rts_n
2770  *
2771  * 1110 (14) Pin is connected to Peripheral signal nand.adq13
2772  *
2773  * 1111 (15) Pin is connected to Peripheral signal gpio0.io21
2774  *
2775  * Field Access Macros:
2776  *
2777  */
2778 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_10_SEL register field. */
2779 #define ALT_PINMUX_SHARED_3V_IO_Q2_10_SEL_LSB 0
2780 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_10_SEL register field. */
2781 #define ALT_PINMUX_SHARED_3V_IO_Q2_10_SEL_MSB 3
2782 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_10_SEL register field. */
2783 #define ALT_PINMUX_SHARED_3V_IO_Q2_10_SEL_WIDTH 4
2784 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_10_SEL register field value. */
2785 #define ALT_PINMUX_SHARED_3V_IO_Q2_10_SEL_SET_MSK 0x0000000f
2786 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_10_SEL register field value. */
2787 #define ALT_PINMUX_SHARED_3V_IO_Q2_10_SEL_CLR_MSK 0xfffffff0
2788 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_10_SEL register field. */
2789 #define ALT_PINMUX_SHARED_3V_IO_Q2_10_SEL_RESET 0xf
2790 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_10_SEL field value from a register. */
2791 #define ALT_PINMUX_SHARED_3V_IO_Q2_10_SEL_GET(value) (((value) & 0x0000000f) >> 0)
2792 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_10_SEL register field value suitable for setting the register. */
2793 #define ALT_PINMUX_SHARED_3V_IO_Q2_10_SEL_SET(value) (((value) << 0) & 0x0000000f)
2794 
2795 /*
2796  * Field : Reserved
2797  *
2798  * Reserved
2799  *
2800  * Field Access Macros:
2801  *
2802  */
2803 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_10_RSVD register field. */
2804 #define ALT_PINMUX_SHARED_3V_IO_Q2_10_RSVD_LSB 4
2805 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_10_RSVD register field. */
2806 #define ALT_PINMUX_SHARED_3V_IO_Q2_10_RSVD_MSB 31
2807 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_10_RSVD register field. */
2808 #define ALT_PINMUX_SHARED_3V_IO_Q2_10_RSVD_WIDTH 28
2809 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_10_RSVD register field value. */
2810 #define ALT_PINMUX_SHARED_3V_IO_Q2_10_RSVD_SET_MSK 0xfffffff0
2811 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_10_RSVD register field value. */
2812 #define ALT_PINMUX_SHARED_3V_IO_Q2_10_RSVD_CLR_MSK 0x0000000f
2813 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_10_RSVD register field. */
2814 #define ALT_PINMUX_SHARED_3V_IO_Q2_10_RSVD_RESET 0x0
2815 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_10_RSVD field value from a register. */
2816 #define ALT_PINMUX_SHARED_3V_IO_Q2_10_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
2817 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_10_RSVD register field value suitable for setting the register. */
2818 #define ALT_PINMUX_SHARED_3V_IO_Q2_10_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
2819 
2820 #ifndef __ASSEMBLY__
2821 /*
2822  * WARNING: The C register and register group struct declarations are provided for
2823  * convenience and illustrative purposes. They should, however, be used with
2824  * caution as the C language standard provides no guarantees about the alignment or
2825  * atomicity of device memory accesses. The recommended practice for writing
2826  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2827  * alt_write_word() functions.
2828  *
2829  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_10.
2830  */
2831 struct ALT_PINMUX_SHARED_3V_IO_Q2_10_s
2832 {
2833  uint32_t sel : 4; /* Shared IO48 Q2 10 Mux Selection Field */
2834  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q2_10_RSVD */
2835 };
2836 
2837 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_10. */
2838 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q2_10_s ALT_PINMUX_SHARED_3V_IO_Q2_10_t;
2839 #endif /* __ASSEMBLY__ */
2840 
2841 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_10 register. */
2842 #define ALT_PINMUX_SHARED_3V_IO_Q2_10_RESET 0x0000000f
2843 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q2_10 register from the beginning of the component. */
2844 #define ALT_PINMUX_SHARED_3V_IO_Q2_10_OFST 0x54
2845 
2846 /*
2847  * Register : Shared IO 48 Q2 11 Mux Selection Register - pinmux_shared_io_q2_11
2848  *
2849  * This register is used to control the peripherals connected to shared IO48 pin Q2
2850  * 11
2851  *
2852  * Only reset by a cold reset (ignores warm reset).
2853  *
2854  * NOTE: These registers should not be modified after IO configuration.There is no
2855  * support for dynamically changing the Pin Mux selections.
2856  *
2857  * Register Layout
2858  *
2859  * Bits | Access | Reset | Description
2860  * :-------|:-------|:------|:--------------------------------------
2861  * [3:0] | RW | 0xf | Shared IO48 Q2 11 Mux Selection Field
2862  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q2_11_RSVD
2863  *
2864  */
2865 /*
2866  * Field : Shared IO48 Q2 11 Mux Selection Field - sel
2867  *
2868  * Select peripheral signals connected shared IO48 Q2 11
2869  *
2870  * 0000 (0) Pin is connected to Peripheral signal i2c0.sda
2871  *
2872  * 0001 (1) Pin is connected to Peripheral signal not applicable
2873  *
2874  * 0010 (2) Pin is connected to Peripheral signal spis0.ss0_n
2875  *
2876  * 0011 (3) Pin is connected to Peripheral signal spim1.miso
2877  *
2878  * 0100 (4) Pin is connected to Peripheral signal emac0.rxd2
2879  *
2880  * 0101 (5) Pin is connected to Peripheral signal not applicable
2881  *
2882  * 0110 (6) Pin is connected to Peripheral signal not applicable
2883  *
2884  * 0111 (7) Pin is connected to Peripheral signal not applicable
2885  *
2886  * 1000 (8) Pin is connected to Peripheral signal usb1.data6
2887  *
2888  * 1001 (9) Pin is connected to Peripheral signal not applicable
2889  *
2890  * 1010 (10) Pin is connected to Peripheral signal not applicable
2891  *
2892  * 1011 (11) Pin is connected to Peripheral signal not applicable
2893  *
2894  * 1100 (12) Pin is connected to Peripheral signal not applicable
2895  *
2896  * 1101 (13) Pin is connected to Peripheral signal uart0.tx
2897  *
2898  * 1110 (14) Pin is connected to Peripheral signal nand.adq14
2899  *
2900  * 1111 (15) Pin is connected to Peripheral signal gpio0.io22
2901  *
2902  * Field Access Macros:
2903  *
2904  */
2905 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_11_SEL register field. */
2906 #define ALT_PINMUX_SHARED_3V_IO_Q2_11_SEL_LSB 0
2907 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_11_SEL register field. */
2908 #define ALT_PINMUX_SHARED_3V_IO_Q2_11_SEL_MSB 3
2909 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_11_SEL register field. */
2910 #define ALT_PINMUX_SHARED_3V_IO_Q2_11_SEL_WIDTH 4
2911 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_11_SEL register field value. */
2912 #define ALT_PINMUX_SHARED_3V_IO_Q2_11_SEL_SET_MSK 0x0000000f
2913 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_11_SEL register field value. */
2914 #define ALT_PINMUX_SHARED_3V_IO_Q2_11_SEL_CLR_MSK 0xfffffff0
2915 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_11_SEL register field. */
2916 #define ALT_PINMUX_SHARED_3V_IO_Q2_11_SEL_RESET 0xf
2917 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_11_SEL field value from a register. */
2918 #define ALT_PINMUX_SHARED_3V_IO_Q2_11_SEL_GET(value) (((value) & 0x0000000f) >> 0)
2919 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_11_SEL register field value suitable for setting the register. */
2920 #define ALT_PINMUX_SHARED_3V_IO_Q2_11_SEL_SET(value) (((value) << 0) & 0x0000000f)
2921 
2922 /*
2923  * Field : Reserved
2924  *
2925  * Reserved
2926  *
2927  * Field Access Macros:
2928  *
2929  */
2930 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_11_RSVD register field. */
2931 #define ALT_PINMUX_SHARED_3V_IO_Q2_11_RSVD_LSB 4
2932 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_11_RSVD register field. */
2933 #define ALT_PINMUX_SHARED_3V_IO_Q2_11_RSVD_MSB 31
2934 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_11_RSVD register field. */
2935 #define ALT_PINMUX_SHARED_3V_IO_Q2_11_RSVD_WIDTH 28
2936 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_11_RSVD register field value. */
2937 #define ALT_PINMUX_SHARED_3V_IO_Q2_11_RSVD_SET_MSK 0xfffffff0
2938 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_11_RSVD register field value. */
2939 #define ALT_PINMUX_SHARED_3V_IO_Q2_11_RSVD_CLR_MSK 0x0000000f
2940 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_11_RSVD register field. */
2941 #define ALT_PINMUX_SHARED_3V_IO_Q2_11_RSVD_RESET 0x0
2942 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_11_RSVD field value from a register. */
2943 #define ALT_PINMUX_SHARED_3V_IO_Q2_11_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
2944 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_11_RSVD register field value suitable for setting the register. */
2945 #define ALT_PINMUX_SHARED_3V_IO_Q2_11_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
2946 
2947 #ifndef __ASSEMBLY__
2948 /*
2949  * WARNING: The C register and register group struct declarations are provided for
2950  * convenience and illustrative purposes. They should, however, be used with
2951  * caution as the C language standard provides no guarantees about the alignment or
2952  * atomicity of device memory accesses. The recommended practice for writing
2953  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2954  * alt_write_word() functions.
2955  *
2956  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_11.
2957  */
2958 struct ALT_PINMUX_SHARED_3V_IO_Q2_11_s
2959 {
2960  uint32_t sel : 4; /* Shared IO48 Q2 11 Mux Selection Field */
2961  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q2_11_RSVD */
2962 };
2963 
2964 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_11. */
2965 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q2_11_s ALT_PINMUX_SHARED_3V_IO_Q2_11_t;
2966 #endif /* __ASSEMBLY__ */
2967 
2968 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_11 register. */
2969 #define ALT_PINMUX_SHARED_3V_IO_Q2_11_RESET 0x0000000f
2970 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q2_11 register from the beginning of the component. */
2971 #define ALT_PINMUX_SHARED_3V_IO_Q2_11_OFST 0x58
2972 
2973 /*
2974  * Register : Shared IO 48 Q2 12 Mux Selection Register - pinmux_shared_io_q2_12
2975  *
2976  * This register is used to control the peripherals connected to shared IO48 pin Q2
2977  * 12
2978  *
2979  * Only reset by a cold reset (ignores warm reset).
2980  *
2981  * NOTE: These registers should not be modified after IO configuration.There is no
2982  * support for dynamically changing the Pin Mux selections.
2983  *
2984  * Register Layout
2985  *
2986  * Bits | Access | Reset | Description
2987  * :-------|:-------|:------|:--------------------------------------
2988  * [3:0] | RW | 0xf | Shared IO48 Q2 12 Mux Selection Field
2989  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q2_12_RSVD
2990  *
2991  */
2992 /*
2993  * Field : Shared IO48 Q2 12 Mux Selection Field - sel
2994  *
2995  * Select peripheral signals connected shared IO48 Q2 12
2996  *
2997  * 0000 (0) Pin is connected to Peripheral signal i2c0.scl
2998  *
2999  * 0001 (1) Pin is connected to Peripheral signal not applicable
3000  *
3001  * 0010 (2) Pin is connected to Peripheral signal spis0.miso
3002  *
3003  * 0011 (3) Pin is connected to Peripheral signal spim1.ss0_n
3004  *
3005  * 0100 (4) Pin is connected to Peripheral signal emac0.rxd3
3006  *
3007  * 0101 (5) Pin is connected to Peripheral signal not applicable
3008  *
3009  * 0110 (6) Pin is connected to Peripheral signal not applicable
3010  *
3011  * 0111 (7) Pin is connected to Peripheral signal not applicable
3012  *
3013  * 1000 (8) Pin is connected to Peripheral signal usb1.data7
3014  *
3015  * 1001 (9) Pin is connected to Peripheral signal not applicable
3016  *
3017  * 1010 (10) Pin is connected to Peripheral signal not applicable
3018  *
3019  * 1011 (11) Pin is connected to Peripheral signal not applicable
3020  *
3021  * 1100 (12) Pin is connected to Peripheral signal not applicable
3022  *
3023  * 1101 (13) Pin is connected to Peripheral signal uart0.rx
3024  *
3025  * 1110 (14) Pin is connected to Peripheral signal nand.adq15
3026  *
3027  * 1111 (15) Pin is connected to Peripheral signal gpio0.io23
3028  *
3029  * Field Access Macros:
3030  *
3031  */
3032 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_12_SEL register field. */
3033 #define ALT_PINMUX_SHARED_3V_IO_Q2_12_SEL_LSB 0
3034 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_12_SEL register field. */
3035 #define ALT_PINMUX_SHARED_3V_IO_Q2_12_SEL_MSB 3
3036 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_12_SEL register field. */
3037 #define ALT_PINMUX_SHARED_3V_IO_Q2_12_SEL_WIDTH 4
3038 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_12_SEL register field value. */
3039 #define ALT_PINMUX_SHARED_3V_IO_Q2_12_SEL_SET_MSK 0x0000000f
3040 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_12_SEL register field value. */
3041 #define ALT_PINMUX_SHARED_3V_IO_Q2_12_SEL_CLR_MSK 0xfffffff0
3042 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_12_SEL register field. */
3043 #define ALT_PINMUX_SHARED_3V_IO_Q2_12_SEL_RESET 0xf
3044 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_12_SEL field value from a register. */
3045 #define ALT_PINMUX_SHARED_3V_IO_Q2_12_SEL_GET(value) (((value) & 0x0000000f) >> 0)
3046 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_12_SEL register field value suitable for setting the register. */
3047 #define ALT_PINMUX_SHARED_3V_IO_Q2_12_SEL_SET(value) (((value) << 0) & 0x0000000f)
3048 
3049 /*
3050  * Field : Reserved
3051  *
3052  * Reserved
3053  *
3054  * Field Access Macros:
3055  *
3056  */
3057 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_12_RSVD register field. */
3058 #define ALT_PINMUX_SHARED_3V_IO_Q2_12_RSVD_LSB 4
3059 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_12_RSVD register field. */
3060 #define ALT_PINMUX_SHARED_3V_IO_Q2_12_RSVD_MSB 31
3061 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_12_RSVD register field. */
3062 #define ALT_PINMUX_SHARED_3V_IO_Q2_12_RSVD_WIDTH 28
3063 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_12_RSVD register field value. */
3064 #define ALT_PINMUX_SHARED_3V_IO_Q2_12_RSVD_SET_MSK 0xfffffff0
3065 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_12_RSVD register field value. */
3066 #define ALT_PINMUX_SHARED_3V_IO_Q2_12_RSVD_CLR_MSK 0x0000000f
3067 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_12_RSVD register field. */
3068 #define ALT_PINMUX_SHARED_3V_IO_Q2_12_RSVD_RESET 0x0
3069 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_12_RSVD field value from a register. */
3070 #define ALT_PINMUX_SHARED_3V_IO_Q2_12_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
3071 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q2_12_RSVD register field value suitable for setting the register. */
3072 #define ALT_PINMUX_SHARED_3V_IO_Q2_12_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
3073 
3074 #ifndef __ASSEMBLY__
3075 /*
3076  * WARNING: The C register and register group struct declarations are provided for
3077  * convenience and illustrative purposes. They should, however, be used with
3078  * caution as the C language standard provides no guarantees about the alignment or
3079  * atomicity of device memory accesses. The recommended practice for writing
3080  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3081  * alt_write_word() functions.
3082  *
3083  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_12.
3084  */
3085 struct ALT_PINMUX_SHARED_3V_IO_Q2_12_s
3086 {
3087  uint32_t sel : 4; /* Shared IO48 Q2 12 Mux Selection Field */
3088  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q2_12_RSVD */
3089 };
3090 
3091 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_12. */
3092 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q2_12_s ALT_PINMUX_SHARED_3V_IO_Q2_12_t;
3093 #endif /* __ASSEMBLY__ */
3094 
3095 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_12 register. */
3096 #define ALT_PINMUX_SHARED_3V_IO_Q2_12_RESET 0x0000000f
3097 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q2_12 register from the beginning of the component. */
3098 #define ALT_PINMUX_SHARED_3V_IO_Q2_12_OFST 0x5c
3099 
3100 /*
3101  * Register : Shared IO 48 Q3 1 Mux Selection Register - pinmux_shared_io_q3_1
3102  *
3103  * This register is used to control the peripherals connected to shared IO48 pin Q3
3104  * 1
3105  *
3106  * Only reset by a cold reset (ignores warm reset).
3107  *
3108  * NOTE: These registers should not be modified after IO configuration.There is no
3109  * support for dynamically changing the Pin Mux selections.
3110  *
3111  * Register Layout
3112  *
3113  * Bits | Access | Reset | Description
3114  * :-------|:-------|:------|:-------------------------------------
3115  * [3:0] | RW | 0xf | Shared IO48 Q3 1 Mux Selection Field
3116  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q3_1_RSVD
3117  *
3118  */
3119 /*
3120  * Field : Shared IO48 Q3 1 Mux Selection Field - sel
3121  *
3122  * Select peripheral signals connected shared IO48 Q3 1
3123  *
3124  * 0000 (0) Pin is connected to Peripheral signal not applicable
3125  *
3126  * 0001 (1) Pin is connected to Peripheral signal not applicable
3127  *
3128  * 0010 (2) Pin is connected to Peripheral signal not applicable
3129  *
3130  * 0011 (3) Pin is connected to Peripheral signal spim1.clk
3131  *
3132  * 0100 (4) Pin is connected to Peripheral signal not applicable
3133  *
3134  * 0101 (5) Pin is connected to Peripheral signal not applicable
3135  *
3136  * 0110 (6) Pin is connected to Peripheral signal not applicable
3137  *
3138  * 0111 (7) Pin is connected to Peripheral signal not applicable
3139  *
3140  * 1000 (8) Pin is connected to Peripheral signal emac1.tx_clk
3141  *
3142  * 1001 (9) Pin is connected to Peripheral signal not applicable
3143  *
3144  * 1010 (10) Pin is connected to Peripheral signal not applicable
3145  *
3146  * 1011 (11) Pin is connected to Peripheral signal not applicable
3147  *
3148  * 1100 (12) Pin is connected to Peripheral signal not applicable
3149  *
3150  * 1101 (13) Pin is connected to Peripheral signal uart0.cts_n
3151  *
3152  * 1110 (14) Pin is connected to Peripheral signal nand.adq0
3153  *
3154  * 1111 (15) Pin is connected to Peripheral signal gpio1.io0
3155  *
3156  * Field Access Macros:
3157  *
3158  */
3159 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_1_SEL register field. */
3160 #define ALT_PINMUX_SHARED_3V_IO_Q3_1_SEL_LSB 0
3161 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_1_SEL register field. */
3162 #define ALT_PINMUX_SHARED_3V_IO_Q3_1_SEL_MSB 3
3163 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_1_SEL register field. */
3164 #define ALT_PINMUX_SHARED_3V_IO_Q3_1_SEL_WIDTH 4
3165 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_1_SEL register field value. */
3166 #define ALT_PINMUX_SHARED_3V_IO_Q3_1_SEL_SET_MSK 0x0000000f
3167 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_1_SEL register field value. */
3168 #define ALT_PINMUX_SHARED_3V_IO_Q3_1_SEL_CLR_MSK 0xfffffff0
3169 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_1_SEL register field. */
3170 #define ALT_PINMUX_SHARED_3V_IO_Q3_1_SEL_RESET 0xf
3171 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_1_SEL field value from a register. */
3172 #define ALT_PINMUX_SHARED_3V_IO_Q3_1_SEL_GET(value) (((value) & 0x0000000f) >> 0)
3173 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_1_SEL register field value suitable for setting the register. */
3174 #define ALT_PINMUX_SHARED_3V_IO_Q3_1_SEL_SET(value) (((value) << 0) & 0x0000000f)
3175 
3176 /*
3177  * Field : Reserved
3178  *
3179  * Reserved
3180  *
3181  * Field Access Macros:
3182  *
3183  */
3184 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_1_RSVD register field. */
3185 #define ALT_PINMUX_SHARED_3V_IO_Q3_1_RSVD_LSB 4
3186 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_1_RSVD register field. */
3187 #define ALT_PINMUX_SHARED_3V_IO_Q3_1_RSVD_MSB 31
3188 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_1_RSVD register field. */
3189 #define ALT_PINMUX_SHARED_3V_IO_Q3_1_RSVD_WIDTH 28
3190 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_1_RSVD register field value. */
3191 #define ALT_PINMUX_SHARED_3V_IO_Q3_1_RSVD_SET_MSK 0xfffffff0
3192 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_1_RSVD register field value. */
3193 #define ALT_PINMUX_SHARED_3V_IO_Q3_1_RSVD_CLR_MSK 0x0000000f
3194 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_1_RSVD register field. */
3195 #define ALT_PINMUX_SHARED_3V_IO_Q3_1_RSVD_RESET 0x0
3196 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_1_RSVD field value from a register. */
3197 #define ALT_PINMUX_SHARED_3V_IO_Q3_1_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
3198 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_1_RSVD register field value suitable for setting the register. */
3199 #define ALT_PINMUX_SHARED_3V_IO_Q3_1_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
3200 
3201 #ifndef __ASSEMBLY__
3202 /*
3203  * WARNING: The C register and register group struct declarations are provided for
3204  * convenience and illustrative purposes. They should, however, be used with
3205  * caution as the C language standard provides no guarantees about the alignment or
3206  * atomicity of device memory accesses. The recommended practice for writing
3207  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3208  * alt_write_word() functions.
3209  *
3210  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_1.
3211  */
3212 struct ALT_PINMUX_SHARED_3V_IO_Q3_1_s
3213 {
3214  uint32_t sel : 4; /* Shared IO48 Q3 1 Mux Selection Field */
3215  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q3_1_RSVD */
3216 };
3217 
3218 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_1. */
3219 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q3_1_s ALT_PINMUX_SHARED_3V_IO_Q3_1_t;
3220 #endif /* __ASSEMBLY__ */
3221 
3222 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_1 register. */
3223 #define ALT_PINMUX_SHARED_3V_IO_Q3_1_RESET 0x0000000f
3224 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q3_1 register from the beginning of the component. */
3225 #define ALT_PINMUX_SHARED_3V_IO_Q3_1_OFST 0x60
3226 
3227 /*
3228  * Register : Shared IO 48 Q3 2 Mux Selection Register - pinmux_shared_io_q3_2
3229  *
3230  * This register is used to control the peripherals connected to shared IO48 pin Q3
3231  * 2
3232  *
3233  * Only reset by a cold reset (ignores warm reset).
3234  *
3235  * NOTE: These registers should not be modified after IO configuration.There is no
3236  * support for dynamically changing the Pin Mux selections.
3237  *
3238  * Register Layout
3239  *
3240  * Bits | Access | Reset | Description
3241  * :-------|:-------|:------|:-------------------------------------
3242  * [3:0] | RW | 0xf | Shared IO48 Q3 2 Mux Selection Field
3243  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q3_2_RSVD
3244  *
3245  */
3246 /*
3247  * Field : Shared IO48 Q3 2 Mux Selection Field - sel
3248  *
3249  * Select peripheral signals connected shared IO48 Q3 2
3250  *
3251  * 0000 (0) Pin is connected to Peripheral signal not applicable
3252  *
3253  * 0001 (1) Pin is connected to Peripheral signal not applicable
3254  *
3255  * 0010 (2) Pin is connected to Peripheral signal not applicable
3256  *
3257  * 0011 (3) Pin is connected to Peripheral signal spim1.mosi
3258  *
3259  * 0100 (4) Pin is connected to Peripheral signal not applicable
3260  *
3261  * 0101 (5) Pin is connected to Peripheral signal not applicable
3262  *
3263  * 0110 (6) Pin is connected to Peripheral signal not applicable
3264  *
3265  * 0111 (7) Pin is connected to Peripheral signal not applicable
3266  *
3267  * 1000 (8) Pin is connected to Peripheral signal emac1.tx_ctl
3268  *
3269  * 1001 (9) Pin is connected to Peripheral signal not applicable
3270  *
3271  * 1010 (10) Pin is connected to Peripheral signal not applicable
3272  *
3273  * 1011 (11) Pin is connected to Peripheral signal not applicable
3274  *
3275  * 1100 (12) Pin is connected to Peripheral signal not applicable
3276  *
3277  * 1101 (13) Pin is connected to Peripheral signal uart0.rts_n
3278  *
3279  * 1110 (14) Pin is connected to Peripheral signal nand.adq1
3280  *
3281  * 1111 (15) Pin is connected to Peripheral signal gpio1.io1
3282  *
3283  * Field Access Macros:
3284  *
3285  */
3286 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_2_SEL register field. */
3287 #define ALT_PINMUX_SHARED_3V_IO_Q3_2_SEL_LSB 0
3288 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_2_SEL register field. */
3289 #define ALT_PINMUX_SHARED_3V_IO_Q3_2_SEL_MSB 3
3290 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_2_SEL register field. */
3291 #define ALT_PINMUX_SHARED_3V_IO_Q3_2_SEL_WIDTH 4
3292 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_2_SEL register field value. */
3293 #define ALT_PINMUX_SHARED_3V_IO_Q3_2_SEL_SET_MSK 0x0000000f
3294 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_2_SEL register field value. */
3295 #define ALT_PINMUX_SHARED_3V_IO_Q3_2_SEL_CLR_MSK 0xfffffff0
3296 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_2_SEL register field. */
3297 #define ALT_PINMUX_SHARED_3V_IO_Q3_2_SEL_RESET 0xf
3298 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_2_SEL field value from a register. */
3299 #define ALT_PINMUX_SHARED_3V_IO_Q3_2_SEL_GET(value) (((value) & 0x0000000f) >> 0)
3300 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_2_SEL register field value suitable for setting the register. */
3301 #define ALT_PINMUX_SHARED_3V_IO_Q3_2_SEL_SET(value) (((value) << 0) & 0x0000000f)
3302 
3303 /*
3304  * Field : Reserved
3305  *
3306  * Reserved
3307  *
3308  * Field Access Macros:
3309  *
3310  */
3311 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_2_RSVD register field. */
3312 #define ALT_PINMUX_SHARED_3V_IO_Q3_2_RSVD_LSB 4
3313 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_2_RSVD register field. */
3314 #define ALT_PINMUX_SHARED_3V_IO_Q3_2_RSVD_MSB 31
3315 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_2_RSVD register field. */
3316 #define ALT_PINMUX_SHARED_3V_IO_Q3_2_RSVD_WIDTH 28
3317 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_2_RSVD register field value. */
3318 #define ALT_PINMUX_SHARED_3V_IO_Q3_2_RSVD_SET_MSK 0xfffffff0
3319 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_2_RSVD register field value. */
3320 #define ALT_PINMUX_SHARED_3V_IO_Q3_2_RSVD_CLR_MSK 0x0000000f
3321 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_2_RSVD register field. */
3322 #define ALT_PINMUX_SHARED_3V_IO_Q3_2_RSVD_RESET 0x0
3323 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_2_RSVD field value from a register. */
3324 #define ALT_PINMUX_SHARED_3V_IO_Q3_2_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
3325 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_2_RSVD register field value suitable for setting the register. */
3326 #define ALT_PINMUX_SHARED_3V_IO_Q3_2_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
3327 
3328 #ifndef __ASSEMBLY__
3329 /*
3330  * WARNING: The C register and register group struct declarations are provided for
3331  * convenience and illustrative purposes. They should, however, be used with
3332  * caution as the C language standard provides no guarantees about the alignment or
3333  * atomicity of device memory accesses. The recommended practice for writing
3334  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3335  * alt_write_word() functions.
3336  *
3337  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_2.
3338  */
3339 struct ALT_PINMUX_SHARED_3V_IO_Q3_2_s
3340 {
3341  uint32_t sel : 4; /* Shared IO48 Q3 2 Mux Selection Field */
3342  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q3_2_RSVD */
3343 };
3344 
3345 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_2. */
3346 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q3_2_s ALT_PINMUX_SHARED_3V_IO_Q3_2_t;
3347 #endif /* __ASSEMBLY__ */
3348 
3349 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_2 register. */
3350 #define ALT_PINMUX_SHARED_3V_IO_Q3_2_RESET 0x0000000f
3351 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q3_2 register from the beginning of the component. */
3352 #define ALT_PINMUX_SHARED_3V_IO_Q3_2_OFST 0x64
3353 
3354 /*
3355  * Register : Shared IO 48 Q3 3 Mux Selection Register - pinmux_shared_io_q3_3
3356  *
3357  * This register is used to control the peripherals connected to shared IO48 pin Q3
3358  * 3
3359  *
3360  * Only reset by a cold reset (ignores warm reset).
3361  *
3362  * NOTE: These registers should not be modified after IO configuration.There is no
3363  * support for dynamically changing the Pin Mux selections.
3364  *
3365  * Register Layout
3366  *
3367  * Bits | Access | Reset | Description
3368  * :-------|:-------|:------|:-------------------------------------
3369  * [3:0] | RW | 0xf | Shared IO48 Q3 3 Mux Selection Field
3370  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q3_3_RSVD
3371  *
3372  */
3373 /*
3374  * Field : Shared IO48 Q3 3 Mux Selection Field - sel
3375  *
3376  * Select peripheral signals connected shared IO48 Q3 3
3377  *
3378  * 0000 (0) Pin is connected to Peripheral signal i2c0.sda
3379  *
3380  * 0001 (1) Pin is connected to Peripheral signal not applicable
3381  *
3382  * 0010 (2) Pin is connected to Peripheral signal not applicable
3383  *
3384  * 0011 (3) Pin is connected to Peripheral signal spim1.miso
3385  *
3386  * 0100 (4) Pin is connected to Peripheral signal not applicable
3387  *
3388  * 0101 (5) Pin is connected to Peripheral signal not applicable
3389  *
3390  * 0110 (6) Pin is connected to Peripheral signal not applicable
3391  *
3392  * 0111 (7) Pin is connected to Peripheral signal not applicable
3393  *
3394  * 1000 (8) Pin is connected to Peripheral signal emac1.rx_clk
3395  *
3396  * 1001 (9) Pin is connected to Peripheral signal not applicable
3397  *
3398  * 1010 (10) Pin is connected to Peripheral signal not applicable
3399  *
3400  * 1011 (11) Pin is connected to Peripheral signal not applicable
3401  *
3402  * 1100 (12) Pin is connected to Peripheral signal not applicable
3403  *
3404  * 1101 (13) Pin is connected to Peripheral signal uart0.tx
3405  *
3406  * 1110 (14) Pin is connected to Peripheral signal nand.we_n
3407  *
3408  * 1111 (15) Pin is connected to Peripheral signal gpio1.io2
3409  *
3410  * Field Access Macros:
3411  *
3412  */
3413 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_3_SEL register field. */
3414 #define ALT_PINMUX_SHARED_3V_IO_Q3_3_SEL_LSB 0
3415 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_3_SEL register field. */
3416 #define ALT_PINMUX_SHARED_3V_IO_Q3_3_SEL_MSB 3
3417 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_3_SEL register field. */
3418 #define ALT_PINMUX_SHARED_3V_IO_Q3_3_SEL_WIDTH 4
3419 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_3_SEL register field value. */
3420 #define ALT_PINMUX_SHARED_3V_IO_Q3_3_SEL_SET_MSK 0x0000000f
3421 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_3_SEL register field value. */
3422 #define ALT_PINMUX_SHARED_3V_IO_Q3_3_SEL_CLR_MSK 0xfffffff0
3423 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_3_SEL register field. */
3424 #define ALT_PINMUX_SHARED_3V_IO_Q3_3_SEL_RESET 0xf
3425 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_3_SEL field value from a register. */
3426 #define ALT_PINMUX_SHARED_3V_IO_Q3_3_SEL_GET(value) (((value) & 0x0000000f) >> 0)
3427 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_3_SEL register field value suitable for setting the register. */
3428 #define ALT_PINMUX_SHARED_3V_IO_Q3_3_SEL_SET(value) (((value) << 0) & 0x0000000f)
3429 
3430 /*
3431  * Field : Reserved
3432  *
3433  * Reserved
3434  *
3435  * Field Access Macros:
3436  *
3437  */
3438 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_3_RSVD register field. */
3439 #define ALT_PINMUX_SHARED_3V_IO_Q3_3_RSVD_LSB 4
3440 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_3_RSVD register field. */
3441 #define ALT_PINMUX_SHARED_3V_IO_Q3_3_RSVD_MSB 31
3442 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_3_RSVD register field. */
3443 #define ALT_PINMUX_SHARED_3V_IO_Q3_3_RSVD_WIDTH 28
3444 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_3_RSVD register field value. */
3445 #define ALT_PINMUX_SHARED_3V_IO_Q3_3_RSVD_SET_MSK 0xfffffff0
3446 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_3_RSVD register field value. */
3447 #define ALT_PINMUX_SHARED_3V_IO_Q3_3_RSVD_CLR_MSK 0x0000000f
3448 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_3_RSVD register field. */
3449 #define ALT_PINMUX_SHARED_3V_IO_Q3_3_RSVD_RESET 0x0
3450 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_3_RSVD field value from a register. */
3451 #define ALT_PINMUX_SHARED_3V_IO_Q3_3_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
3452 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_3_RSVD register field value suitable for setting the register. */
3453 #define ALT_PINMUX_SHARED_3V_IO_Q3_3_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
3454 
3455 #ifndef __ASSEMBLY__
3456 /*
3457  * WARNING: The C register and register group struct declarations are provided for
3458  * convenience and illustrative purposes. They should, however, be used with
3459  * caution as the C language standard provides no guarantees about the alignment or
3460  * atomicity of device memory accesses. The recommended practice for writing
3461  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3462  * alt_write_word() functions.
3463  *
3464  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_3.
3465  */
3466 struct ALT_PINMUX_SHARED_3V_IO_Q3_3_s
3467 {
3468  uint32_t sel : 4; /* Shared IO48 Q3 3 Mux Selection Field */
3469  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q3_3_RSVD */
3470 };
3471 
3472 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_3. */
3473 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q3_3_s ALT_PINMUX_SHARED_3V_IO_Q3_3_t;
3474 #endif /* __ASSEMBLY__ */
3475 
3476 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_3 register. */
3477 #define ALT_PINMUX_SHARED_3V_IO_Q3_3_RESET 0x0000000f
3478 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q3_3 register from the beginning of the component. */
3479 #define ALT_PINMUX_SHARED_3V_IO_Q3_3_OFST 0x68
3480 
3481 /*
3482  * Register : Shared IO 48 Q3 4 Mux Selection Register - pinmux_shared_io_q3_4
3483  *
3484  * This register is used to control the peripherals connected to shared IO48 pin Q3
3485  * 4
3486  *
3487  * Only reset by a cold reset (ignores warm reset).
3488  *
3489  * NOTE: These registers should not be modified after IO configuration.There is no
3490  * support for dynamically changing the Pin Mux selections.
3491  *
3492  * Register Layout
3493  *
3494  * Bits | Access | Reset | Description
3495  * :-------|:-------|:------|:-------------------------------------
3496  * [3:0] | RW | 0xf | Shared IO48 Q3 4 Mux Selection Field
3497  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q3_4_RSVD
3498  *
3499  */
3500 /*
3501  * Field : Shared IO48 Q3 4 Mux Selection Field - sel
3502  *
3503  * Select peripheral signals connected shared IO48 Q3 4
3504  *
3505  * 0000 (0) Pin is connected to Peripheral signal i2c0.scl
3506  *
3507  * 0001 (1) Pin is connected to Peripheral signal not applicable
3508  *
3509  * 0010 (2) Pin is connected to Peripheral signal not applicable
3510  *
3511  * 0011 (3) Pin is connected to Peripheral signal spim1.ss0_n
3512  *
3513  * 0100 (4) Pin is connected to Peripheral signal not applicable
3514  *
3515  * 0101 (5) Pin is connected to Peripheral signal not applicable
3516  *
3517  * 0110 (6) Pin is connected to Peripheral signal not applicable
3518  *
3519  * 0111 (7) Pin is connected to Peripheral signal not applicable
3520  *
3521  * 1000 (8) Pin is connected to Peripheral signal emac1.rx_ctl
3522  *
3523  * 1001 (9) Pin is connected to Peripheral signal not applicable
3524  *
3525  * 1010 (10) Pin is connected to Peripheral signal not applicable
3526  *
3527  * 1011 (11) Pin is connected to Peripheral signal not applicable
3528  *
3529  * 1100 (12) Pin is connected to Peripheral signal not applicable
3530  *
3531  * 1101 (13) Pin is connected to Peripheral signal uart0.rx
3532  *
3533  * 1110 (14) Pin is connected to Peripheral signal nand.re_n
3534  *
3535  * 1111 (15) Pin is connected to Peripheral signal gpio1.io3
3536  *
3537  * Field Access Macros:
3538  *
3539  */
3540 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_4_SEL register field. */
3541 #define ALT_PINMUX_SHARED_3V_IO_Q3_4_SEL_LSB 0
3542 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_4_SEL register field. */
3543 #define ALT_PINMUX_SHARED_3V_IO_Q3_4_SEL_MSB 3
3544 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_4_SEL register field. */
3545 #define ALT_PINMUX_SHARED_3V_IO_Q3_4_SEL_WIDTH 4
3546 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_4_SEL register field value. */
3547 #define ALT_PINMUX_SHARED_3V_IO_Q3_4_SEL_SET_MSK 0x0000000f
3548 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_4_SEL register field value. */
3549 #define ALT_PINMUX_SHARED_3V_IO_Q3_4_SEL_CLR_MSK 0xfffffff0
3550 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_4_SEL register field. */
3551 #define ALT_PINMUX_SHARED_3V_IO_Q3_4_SEL_RESET 0xf
3552 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_4_SEL field value from a register. */
3553 #define ALT_PINMUX_SHARED_3V_IO_Q3_4_SEL_GET(value) (((value) & 0x0000000f) >> 0)
3554 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_4_SEL register field value suitable for setting the register. */
3555 #define ALT_PINMUX_SHARED_3V_IO_Q3_4_SEL_SET(value) (((value) << 0) & 0x0000000f)
3556 
3557 /*
3558  * Field : Reserved
3559  *
3560  * Reserved
3561  *
3562  * Field Access Macros:
3563  *
3564  */
3565 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_4_RSVD register field. */
3566 #define ALT_PINMUX_SHARED_3V_IO_Q3_4_RSVD_LSB 4
3567 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_4_RSVD register field. */
3568 #define ALT_PINMUX_SHARED_3V_IO_Q3_4_RSVD_MSB 31
3569 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_4_RSVD register field. */
3570 #define ALT_PINMUX_SHARED_3V_IO_Q3_4_RSVD_WIDTH 28
3571 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_4_RSVD register field value. */
3572 #define ALT_PINMUX_SHARED_3V_IO_Q3_4_RSVD_SET_MSK 0xfffffff0
3573 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_4_RSVD register field value. */
3574 #define ALT_PINMUX_SHARED_3V_IO_Q3_4_RSVD_CLR_MSK 0x0000000f
3575 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_4_RSVD register field. */
3576 #define ALT_PINMUX_SHARED_3V_IO_Q3_4_RSVD_RESET 0x0
3577 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_4_RSVD field value from a register. */
3578 #define ALT_PINMUX_SHARED_3V_IO_Q3_4_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
3579 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_4_RSVD register field value suitable for setting the register. */
3580 #define ALT_PINMUX_SHARED_3V_IO_Q3_4_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
3581 
3582 #ifndef __ASSEMBLY__
3583 /*
3584  * WARNING: The C register and register group struct declarations are provided for
3585  * convenience and illustrative purposes. They should, however, be used with
3586  * caution as the C language standard provides no guarantees about the alignment or
3587  * atomicity of device memory accesses. The recommended practice for writing
3588  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3589  * alt_write_word() functions.
3590  *
3591  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_4.
3592  */
3593 struct ALT_PINMUX_SHARED_3V_IO_Q3_4_s
3594 {
3595  uint32_t sel : 4; /* Shared IO48 Q3 4 Mux Selection Field */
3596  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q3_4_RSVD */
3597 };
3598 
3599 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_4. */
3600 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q3_4_s ALT_PINMUX_SHARED_3V_IO_Q3_4_t;
3601 #endif /* __ASSEMBLY__ */
3602 
3603 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_4 register. */
3604 #define ALT_PINMUX_SHARED_3V_IO_Q3_4_RESET 0x0000000f
3605 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q3_4 register from the beginning of the component. */
3606 #define ALT_PINMUX_SHARED_3V_IO_Q3_4_OFST 0x6c
3607 
3608 /*
3609  * Register : Shared IO 48 Q3 5 Mux Selection Register - pinmux_shared_io_q3_5
3610  *
3611  * This register is used to control the peripherals connected to shared IO48 pin Q3
3612  * 5
3613  *
3614  * Only reset by a cold reset (ignores warm reset).
3615  *
3616  * NOTE: These registers should not be modified after IO configuration.There is no
3617  * support for dynamically changing the Pin Mux selections.
3618  *
3619  * Register Layout
3620  *
3621  * Bits | Access | Reset | Description
3622  * :-------|:-------|:------|:-------------------------------------
3623  * [3:0] | RW | 0xf | Shared IO48 Q3 5 Mux Selection Field
3624  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q3_5_RSVD
3625  *
3626  */
3627 /*
3628  * Field : Shared IO48 Q3 5 Mux Selection Field - sel
3629  *
3630  * Select peripheral signals connected shared IO48 Q3 5
3631  *
3632  * 0000 (0) Pin is connected to Peripheral signal not applicable
3633  *
3634  * 0001 (1) Pin is connected to Peripheral signal not applicable
3635  *
3636  * 0010 (2) Pin is connected to Peripheral signal spis1.clk
3637  *
3638  * 0011 (3) Pin is connected to Peripheral signal spim1.ss1_n
3639  *
3640  * 0100 (4) Pin is connected to Peripheral signal not applicable
3641  *
3642  * 0101 (5) Pin is connected to Peripheral signal not applicable
3643  *
3644  * 0110 (6) Pin is connected to Peripheral signal not applicable
3645  *
3646  * 0111 (7) Pin is connected to Peripheral signal not applicable
3647  *
3648  * 1000 (8) Pin is connected to Peripheral signal emac1.txd0
3649  *
3650  * 1001 (9) Pin is connected to Peripheral signal not applicable
3651  *
3652  * 1010 (10) Pin is connected to Peripheral signal not applicable
3653  *
3654  * 1011 (11) Pin is connected to Peripheral signal not applicable
3655  *
3656  * 1100 (12) Pin is connected to Peripheral signal not applicable
3657  *
3658  * 1101 (13) Pin is connected to Peripheral signal uart1.cts_n
3659  *
3660  * 1110 (14) Pin is connected to Peripheral signal nand.wp_n
3661  *
3662  * 1111 (15) Pin is connected to Peripheral signal gpio1.io4
3663  *
3664  * Field Access Macros:
3665  *
3666  */
3667 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_5_SEL register field. */
3668 #define ALT_PINMUX_SHARED_3V_IO_Q3_5_SEL_LSB 0
3669 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_5_SEL register field. */
3670 #define ALT_PINMUX_SHARED_3V_IO_Q3_5_SEL_MSB 3
3671 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_5_SEL register field. */
3672 #define ALT_PINMUX_SHARED_3V_IO_Q3_5_SEL_WIDTH 4
3673 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_5_SEL register field value. */
3674 #define ALT_PINMUX_SHARED_3V_IO_Q3_5_SEL_SET_MSK 0x0000000f
3675 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_5_SEL register field value. */
3676 #define ALT_PINMUX_SHARED_3V_IO_Q3_5_SEL_CLR_MSK 0xfffffff0
3677 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_5_SEL register field. */
3678 #define ALT_PINMUX_SHARED_3V_IO_Q3_5_SEL_RESET 0xf
3679 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_5_SEL field value from a register. */
3680 #define ALT_PINMUX_SHARED_3V_IO_Q3_5_SEL_GET(value) (((value) & 0x0000000f) >> 0)
3681 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_5_SEL register field value suitable for setting the register. */
3682 #define ALT_PINMUX_SHARED_3V_IO_Q3_5_SEL_SET(value) (((value) << 0) & 0x0000000f)
3683 
3684 /*
3685  * Field : Reserved
3686  *
3687  * Reserved
3688  *
3689  * Field Access Macros:
3690  *
3691  */
3692 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_5_RSVD register field. */
3693 #define ALT_PINMUX_SHARED_3V_IO_Q3_5_RSVD_LSB 4
3694 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_5_RSVD register field. */
3695 #define ALT_PINMUX_SHARED_3V_IO_Q3_5_RSVD_MSB 31
3696 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_5_RSVD register field. */
3697 #define ALT_PINMUX_SHARED_3V_IO_Q3_5_RSVD_WIDTH 28
3698 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_5_RSVD register field value. */
3699 #define ALT_PINMUX_SHARED_3V_IO_Q3_5_RSVD_SET_MSK 0xfffffff0
3700 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_5_RSVD register field value. */
3701 #define ALT_PINMUX_SHARED_3V_IO_Q3_5_RSVD_CLR_MSK 0x0000000f
3702 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_5_RSVD register field. */
3703 #define ALT_PINMUX_SHARED_3V_IO_Q3_5_RSVD_RESET 0x0
3704 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_5_RSVD field value from a register. */
3705 #define ALT_PINMUX_SHARED_3V_IO_Q3_5_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
3706 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_5_RSVD register field value suitable for setting the register. */
3707 #define ALT_PINMUX_SHARED_3V_IO_Q3_5_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
3708 
3709 #ifndef __ASSEMBLY__
3710 /*
3711  * WARNING: The C register and register group struct declarations are provided for
3712  * convenience and illustrative purposes. They should, however, be used with
3713  * caution as the C language standard provides no guarantees about the alignment or
3714  * atomicity of device memory accesses. The recommended practice for writing
3715  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3716  * alt_write_word() functions.
3717  *
3718  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_5.
3719  */
3720 struct ALT_PINMUX_SHARED_3V_IO_Q3_5_s
3721 {
3722  uint32_t sel : 4; /* Shared IO48 Q3 5 Mux Selection Field */
3723  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q3_5_RSVD */
3724 };
3725 
3726 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_5. */
3727 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q3_5_s ALT_PINMUX_SHARED_3V_IO_Q3_5_t;
3728 #endif /* __ASSEMBLY__ */
3729 
3730 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_5 register. */
3731 #define ALT_PINMUX_SHARED_3V_IO_Q3_5_RESET 0x0000000f
3732 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q3_5 register from the beginning of the component. */
3733 #define ALT_PINMUX_SHARED_3V_IO_Q3_5_OFST 0x70
3734 
3735 /*
3736  * Register : Shared IO 48 Q3 6 Mux Selection Register - pinmux_shared_io_q3_6
3737  *
3738  * This register is used to control the peripherals connected to shared IO48 pin Q3
3739  * 6
3740  *
3741  * Only reset by a cold reset (ignores warm reset).
3742  *
3743  * NOTE: These registers should not be modified after IO configuration.There is no
3744  * support for dynamically changing the Pin Mux selections.
3745  *
3746  * Register Layout
3747  *
3748  * Bits | Access | Reset | Description
3749  * :-------|:-------|:------|:-------------------------------------
3750  * [3:0] | RW | 0xf | Shared IO48 Q3 6 Mux Selection Field
3751  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q3_6_RSVD
3752  *
3753  */
3754 /*
3755  * Field : Shared IO48 Q3 6 Mux Selection Field - sel
3756  *
3757  * Select peripheral signals connected shared IO48 Q3 6
3758  *
3759  * 0000 (0) Pin is connected to Peripheral signal not applicable
3760  *
3761  * 0001 (1) Pin is connected to Peripheral signal not applicable
3762  *
3763  * 0010 (2) Pin is connected to Peripheral signal spis1.mosi
3764  *
3765  * 0011 (3) Pin is connected to Peripheral signal not applicable
3766  *
3767  * 0100 (4) Pin is connected to Peripheral signal not applicable
3768  *
3769  * 0101 (5) Pin is connected to Peripheral signal not applicable
3770  *
3771  * 0110 (6) Pin is connected to Peripheral signal not applicable
3772  *
3773  * 0111 (7) Pin is connected to Peripheral signal not applicable
3774  *
3775  * 1000 (8) Pin is connected to Peripheral signal emac1.txd1
3776  *
3777  * 1001 (9) Pin is connected to Peripheral signal not applicable
3778  *
3779  * 1010 (10) Pin is connected to Peripheral signal not applicable
3780  *
3781  * 1011 (11) Pin is connected to Peripheral signal not applicable
3782  *
3783  * 1100 (12) Pin is connected to Peripheral signal not applicable
3784  *
3785  * 1101 (13) Pin is connected to Peripheral signal uart1.rts_n
3786  *
3787  * 1110 (14) Pin is connected to Peripheral signal nand.adq2
3788  *
3789  * 1111 (15) Pin is connected to Peripheral signal gpio1.io5
3790  *
3791  * Field Access Macros:
3792  *
3793  */
3794 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_6_SEL register field. */
3795 #define ALT_PINMUX_SHARED_3V_IO_Q3_6_SEL_LSB 0
3796 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_6_SEL register field. */
3797 #define ALT_PINMUX_SHARED_3V_IO_Q3_6_SEL_MSB 3
3798 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_6_SEL register field. */
3799 #define ALT_PINMUX_SHARED_3V_IO_Q3_6_SEL_WIDTH 4
3800 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_6_SEL register field value. */
3801 #define ALT_PINMUX_SHARED_3V_IO_Q3_6_SEL_SET_MSK 0x0000000f
3802 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_6_SEL register field value. */
3803 #define ALT_PINMUX_SHARED_3V_IO_Q3_6_SEL_CLR_MSK 0xfffffff0
3804 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_6_SEL register field. */
3805 #define ALT_PINMUX_SHARED_3V_IO_Q3_6_SEL_RESET 0xf
3806 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_6_SEL field value from a register. */
3807 #define ALT_PINMUX_SHARED_3V_IO_Q3_6_SEL_GET(value) (((value) & 0x0000000f) >> 0)
3808 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_6_SEL register field value suitable for setting the register. */
3809 #define ALT_PINMUX_SHARED_3V_IO_Q3_6_SEL_SET(value) (((value) << 0) & 0x0000000f)
3810 
3811 /*
3812  * Field : Reserved
3813  *
3814  * Reserved
3815  *
3816  * Field Access Macros:
3817  *
3818  */
3819 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_6_RSVD register field. */
3820 #define ALT_PINMUX_SHARED_3V_IO_Q3_6_RSVD_LSB 4
3821 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_6_RSVD register field. */
3822 #define ALT_PINMUX_SHARED_3V_IO_Q3_6_RSVD_MSB 31
3823 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_6_RSVD register field. */
3824 #define ALT_PINMUX_SHARED_3V_IO_Q3_6_RSVD_WIDTH 28
3825 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_6_RSVD register field value. */
3826 #define ALT_PINMUX_SHARED_3V_IO_Q3_6_RSVD_SET_MSK 0xfffffff0
3827 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_6_RSVD register field value. */
3828 #define ALT_PINMUX_SHARED_3V_IO_Q3_6_RSVD_CLR_MSK 0x0000000f
3829 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_6_RSVD register field. */
3830 #define ALT_PINMUX_SHARED_3V_IO_Q3_6_RSVD_RESET 0x0
3831 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_6_RSVD field value from a register. */
3832 #define ALT_PINMUX_SHARED_3V_IO_Q3_6_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
3833 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_6_RSVD register field value suitable for setting the register. */
3834 #define ALT_PINMUX_SHARED_3V_IO_Q3_6_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
3835 
3836 #ifndef __ASSEMBLY__
3837 /*
3838  * WARNING: The C register and register group struct declarations are provided for
3839  * convenience and illustrative purposes. They should, however, be used with
3840  * caution as the C language standard provides no guarantees about the alignment or
3841  * atomicity of device memory accesses. The recommended practice for writing
3842  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3843  * alt_write_word() functions.
3844  *
3845  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_6.
3846  */
3847 struct ALT_PINMUX_SHARED_3V_IO_Q3_6_s
3848 {
3849  uint32_t sel : 4; /* Shared IO48 Q3 6 Mux Selection Field */
3850  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q3_6_RSVD */
3851 };
3852 
3853 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_6. */
3854 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q3_6_s ALT_PINMUX_SHARED_3V_IO_Q3_6_t;
3855 #endif /* __ASSEMBLY__ */
3856 
3857 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_6 register. */
3858 #define ALT_PINMUX_SHARED_3V_IO_Q3_6_RESET 0x0000000f
3859 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q3_6 register from the beginning of the component. */
3860 #define ALT_PINMUX_SHARED_3V_IO_Q3_6_OFST 0x74
3861 
3862 /*
3863  * Register : Shared IO 48 Q3 7 Mux Selection Register - pinmux_shared_io_q3_7
3864  *
3865  * This register is used to control the peripherals connected to shared IO48 pin Q3
3866  * 7
3867  *
3868  * Only reset by a cold reset (ignores warm reset).
3869  *
3870  * NOTE: These registers should not be modified after IO configuration.There is no
3871  * support for dynamically changing the Pin Mux selections.
3872  *
3873  * Register Layout
3874  *
3875  * Bits | Access | Reset | Description
3876  * :-------|:-------|:------|:-------------------------------------
3877  * [3:0] | RW | 0xf | Shared IO48 Q3 7 Mux Selection Field
3878  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q3_7_RSVD
3879  *
3880  */
3881 /*
3882  * Field : Shared IO48 Q3 7 Mux Selection Field - sel
3883  *
3884  * Select peripheral signals connected shared IO48 Q3 7
3885  *
3886  * 0000 (0) Pin is connected to Peripheral signal i2c1.sda
3887  *
3888  * 0001 (1) Pin is connected to Peripheral signal not applicable
3889  *
3890  * 0010 (2) Pin is connected to Peripheral signal spis1.ss0_n
3891  *
3892  * 0011 (3) Pin is connected to Peripheral signal not applicable
3893  *
3894  * 0100 (4) Pin is connected to Peripheral signal not applicable
3895  *
3896  * 0101 (5) Pin is connected to Peripheral signal not applicable
3897  *
3898  * 0110 (6) Pin is connected to Peripheral signal not applicable
3899  *
3900  * 0111 (7) Pin is connected to Peripheral signal not applicable
3901  *
3902  * 1000 (8) Pin is connected to Peripheral signal emac1.rxd0
3903  *
3904  * 1001 (9) Pin is connected to Peripheral signal not applicable
3905  *
3906  * 1010 (10) Pin is connected to Peripheral signal not applicable
3907  *
3908  * 1011 (11) Pin is connected to Peripheral signal not applicable
3909  *
3910  * 1100 (12) Pin is connected to Peripheral signal not applicable
3911  *
3912  * 1101 (13) Pin is connected to Peripheral signal uart1.tx
3913  *
3914  * 1110 (14) Pin is connected to Peripheral signal nand.adq3
3915  *
3916  * 1111 (15) Pin is connected to Peripheral signal gpio1.io6
3917  *
3918  * Field Access Macros:
3919  *
3920  */
3921 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_7_SEL register field. */
3922 #define ALT_PINMUX_SHARED_3V_IO_Q3_7_SEL_LSB 0
3923 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_7_SEL register field. */
3924 #define ALT_PINMUX_SHARED_3V_IO_Q3_7_SEL_MSB 3
3925 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_7_SEL register field. */
3926 #define ALT_PINMUX_SHARED_3V_IO_Q3_7_SEL_WIDTH 4
3927 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_7_SEL register field value. */
3928 #define ALT_PINMUX_SHARED_3V_IO_Q3_7_SEL_SET_MSK 0x0000000f
3929 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_7_SEL register field value. */
3930 #define ALT_PINMUX_SHARED_3V_IO_Q3_7_SEL_CLR_MSK 0xfffffff0
3931 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_7_SEL register field. */
3932 #define ALT_PINMUX_SHARED_3V_IO_Q3_7_SEL_RESET 0xf
3933 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_7_SEL field value from a register. */
3934 #define ALT_PINMUX_SHARED_3V_IO_Q3_7_SEL_GET(value) (((value) & 0x0000000f) >> 0)
3935 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_7_SEL register field value suitable for setting the register. */
3936 #define ALT_PINMUX_SHARED_3V_IO_Q3_7_SEL_SET(value) (((value) << 0) & 0x0000000f)
3937 
3938 /*
3939  * Field : Reserved
3940  *
3941  * Reserved
3942  *
3943  * Field Access Macros:
3944  *
3945  */
3946 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_7_RSVD register field. */
3947 #define ALT_PINMUX_SHARED_3V_IO_Q3_7_RSVD_LSB 4
3948 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_7_RSVD register field. */
3949 #define ALT_PINMUX_SHARED_3V_IO_Q3_7_RSVD_MSB 31
3950 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_7_RSVD register field. */
3951 #define ALT_PINMUX_SHARED_3V_IO_Q3_7_RSVD_WIDTH 28
3952 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_7_RSVD register field value. */
3953 #define ALT_PINMUX_SHARED_3V_IO_Q3_7_RSVD_SET_MSK 0xfffffff0
3954 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_7_RSVD register field value. */
3955 #define ALT_PINMUX_SHARED_3V_IO_Q3_7_RSVD_CLR_MSK 0x0000000f
3956 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_7_RSVD register field. */
3957 #define ALT_PINMUX_SHARED_3V_IO_Q3_7_RSVD_RESET 0x0
3958 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_7_RSVD field value from a register. */
3959 #define ALT_PINMUX_SHARED_3V_IO_Q3_7_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
3960 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_7_RSVD register field value suitable for setting the register. */
3961 #define ALT_PINMUX_SHARED_3V_IO_Q3_7_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
3962 
3963 #ifndef __ASSEMBLY__
3964 /*
3965  * WARNING: The C register and register group struct declarations are provided for
3966  * convenience and illustrative purposes. They should, however, be used with
3967  * caution as the C language standard provides no guarantees about the alignment or
3968  * atomicity of device memory accesses. The recommended practice for writing
3969  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3970  * alt_write_word() functions.
3971  *
3972  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_7.
3973  */
3974 struct ALT_PINMUX_SHARED_3V_IO_Q3_7_s
3975 {
3976  uint32_t sel : 4; /* Shared IO48 Q3 7 Mux Selection Field */
3977  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q3_7_RSVD */
3978 };
3979 
3980 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_7. */
3981 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q3_7_s ALT_PINMUX_SHARED_3V_IO_Q3_7_t;
3982 #endif /* __ASSEMBLY__ */
3983 
3984 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_7 register. */
3985 #define ALT_PINMUX_SHARED_3V_IO_Q3_7_RESET 0x0000000f
3986 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q3_7 register from the beginning of the component. */
3987 #define ALT_PINMUX_SHARED_3V_IO_Q3_7_OFST 0x78
3988 
3989 /*
3990  * Register : Shared IO 48 Q3 8 Mux Selection Register - pinmux_shared_io_q3_8
3991  *
3992  * This register is used to control the peripherals connected to shared IO48 pin Q3
3993  * 8
3994  *
3995  * Only reset by a cold reset (ignores warm reset).
3996  *
3997  * NOTE: These registers should not be modified after IO configuration.There is no
3998  * support for dynamically changing the Pin Mux selections.
3999  *
4000  * Register Layout
4001  *
4002  * Bits | Access | Reset | Description
4003  * :-------|:-------|:------|:-------------------------------------
4004  * [3:0] | RW | 0xf | Shared IO48 Q3 8 Mux Selection Field
4005  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q3_8_RSVD
4006  *
4007  */
4008 /*
4009  * Field : Shared IO48 Q3 8 Mux Selection Field - sel
4010  *
4011  * Select peripheral signals connected shared IO48 Q3 8
4012  *
4013  * 0000 (0) Pin is connected to Peripheral signal i2c1.scl
4014  *
4015  * 0001 (1) Pin is connected to Peripheral signal not applicable
4016  *
4017  * 0010 (2) Pin is connected to Peripheral signal spis1.miso
4018  *
4019  * 0011 (3) Pin is connected to Peripheral signal not applicable
4020  *
4021  * 0100 (4) Pin is connected to Peripheral signal not applicable
4022  *
4023  * 0101 (5) Pin is connected to Peripheral signal not applicable
4024  *
4025  * 0110 (6) Pin is connected to Peripheral signal not applicable
4026  *
4027  * 0111 (7) Pin is connected to Peripheral signal not applicable
4028  *
4029  * 1000 (8) Pin is connected to Peripheral signal emac1.rxd1
4030  *
4031  * 1001 (9) Pin is connected to Peripheral signal not applicable
4032  *
4033  * 1010 (10) Pin is connected to Peripheral signal not applicable
4034  *
4035  * 1011 (11) Pin is connected to Peripheral signal not applicable
4036  *
4037  * 1100 (12) Pin is connected to Peripheral signal not applicable
4038  *
4039  * 1101 (13) Pin is connected to Peripheral signal uart1.rx
4040  *
4041  * 1110 (14) Pin is connected to Peripheral signal nand.cle
4042  *
4043  * 1111 (15) Pin is connected to Peripheral signal gpio1.io7
4044  *
4045  * Field Access Macros:
4046  *
4047  */
4048 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_8_SEL register field. */
4049 #define ALT_PINMUX_SHARED_3V_IO_Q3_8_SEL_LSB 0
4050 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_8_SEL register field. */
4051 #define ALT_PINMUX_SHARED_3V_IO_Q3_8_SEL_MSB 3
4052 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_8_SEL register field. */
4053 #define ALT_PINMUX_SHARED_3V_IO_Q3_8_SEL_WIDTH 4
4054 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_8_SEL register field value. */
4055 #define ALT_PINMUX_SHARED_3V_IO_Q3_8_SEL_SET_MSK 0x0000000f
4056 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_8_SEL register field value. */
4057 #define ALT_PINMUX_SHARED_3V_IO_Q3_8_SEL_CLR_MSK 0xfffffff0
4058 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_8_SEL register field. */
4059 #define ALT_PINMUX_SHARED_3V_IO_Q3_8_SEL_RESET 0xf
4060 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_8_SEL field value from a register. */
4061 #define ALT_PINMUX_SHARED_3V_IO_Q3_8_SEL_GET(value) (((value) & 0x0000000f) >> 0)
4062 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_8_SEL register field value suitable for setting the register. */
4063 #define ALT_PINMUX_SHARED_3V_IO_Q3_8_SEL_SET(value) (((value) << 0) & 0x0000000f)
4064 
4065 /*
4066  * Field : Reserved
4067  *
4068  * Reserved
4069  *
4070  * Field Access Macros:
4071  *
4072  */
4073 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_8_RSVD register field. */
4074 #define ALT_PINMUX_SHARED_3V_IO_Q3_8_RSVD_LSB 4
4075 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_8_RSVD register field. */
4076 #define ALT_PINMUX_SHARED_3V_IO_Q3_8_RSVD_MSB 31
4077 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_8_RSVD register field. */
4078 #define ALT_PINMUX_SHARED_3V_IO_Q3_8_RSVD_WIDTH 28
4079 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_8_RSVD register field value. */
4080 #define ALT_PINMUX_SHARED_3V_IO_Q3_8_RSVD_SET_MSK 0xfffffff0
4081 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_8_RSVD register field value. */
4082 #define ALT_PINMUX_SHARED_3V_IO_Q3_8_RSVD_CLR_MSK 0x0000000f
4083 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_8_RSVD register field. */
4084 #define ALT_PINMUX_SHARED_3V_IO_Q3_8_RSVD_RESET 0x0
4085 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_8_RSVD field value from a register. */
4086 #define ALT_PINMUX_SHARED_3V_IO_Q3_8_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
4087 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_8_RSVD register field value suitable for setting the register. */
4088 #define ALT_PINMUX_SHARED_3V_IO_Q3_8_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
4089 
4090 #ifndef __ASSEMBLY__
4091 /*
4092  * WARNING: The C register and register group struct declarations are provided for
4093  * convenience and illustrative purposes. They should, however, be used with
4094  * caution as the C language standard provides no guarantees about the alignment or
4095  * atomicity of device memory accesses. The recommended practice for writing
4096  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4097  * alt_write_word() functions.
4098  *
4099  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_8.
4100  */
4101 struct ALT_PINMUX_SHARED_3V_IO_Q3_8_s
4102 {
4103  uint32_t sel : 4; /* Shared IO48 Q3 8 Mux Selection Field */
4104  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q3_8_RSVD */
4105 };
4106 
4107 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_8. */
4108 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q3_8_s ALT_PINMUX_SHARED_3V_IO_Q3_8_t;
4109 #endif /* __ASSEMBLY__ */
4110 
4111 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_8 register. */
4112 #define ALT_PINMUX_SHARED_3V_IO_Q3_8_RESET 0x0000000f
4113 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q3_8 register from the beginning of the component. */
4114 #define ALT_PINMUX_SHARED_3V_IO_Q3_8_OFST 0x7c
4115 
4116 /*
4117  * Register : Shared IO 48 Q3 9 Mux Selection Register - pinmux_shared_io_q3_9
4118  *
4119  * This register is used to control the peripherals connected to shared IO48 pin Q3
4120  * 9
4121  *
4122  * Only reset by a cold reset (ignores warm reset).
4123  *
4124  * NOTE: These registers should not be modified after IO configuration.There is no
4125  * support for dynamically changing the Pin Mux selections.
4126  *
4127  * Register Layout
4128  *
4129  * Bits | Access | Reset | Description
4130  * :-------|:-------|:------|:-------------------------------------
4131  * [3:0] | RW | 0xf | Shared IO48 Q3 9 Mux Selection Field
4132  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q3_9_RSVD
4133  *
4134  */
4135 /*
4136  * Field : Shared IO48 Q3 9 Mux Selection Field - sel
4137  *
4138  * Select peripheral signals connected shared IO48 Q3 9
4139  *
4140  * 0000 (0) Pin is connected to Peripheral signal i2c_emac2.sda
4141  *
4142  * 0001 (1) Pin is connected to Peripheral signal emac2.mdio
4143  *
4144  * 0010 (2) Pin is connected to Peripheral signal spis0.clk
4145  *
4146  * 0011 (3) Pin is connected to Peripheral signal not applicable
4147  *
4148  * 0100 (4) Pin is connected to Peripheral signal not applicable
4149  *
4150  * 0101 (5) Pin is connected to Peripheral signal not applicable
4151  *
4152  * 0110 (6) Pin is connected to Peripheral signal not applicable
4153  *
4154  * 0111 (7) Pin is connected to Peripheral signal not applicable
4155  *
4156  * 1000 (8) Pin is connected to Peripheral signal emac1.txd2
4157  *
4158  * 1001 (9) Pin is connected to Peripheral signal not applicable
4159  *
4160  * 1010 (10) Pin is connected to Peripheral signal not applicable
4161  *
4162  * 1011 (11) Pin is connected to Peripheral signal not applicable
4163  *
4164  * 1100 (12) Pin is connected to Peripheral signal not applicable
4165  *
4166  * 1101 (13) Pin is connected to Peripheral signal not applicable
4167  *
4168  * 1110 (14) Pin is connected to Peripheral signal nand.adq4
4169  *
4170  * 1111 (15) Pin is connected to Peripheral signal gpio1.io8
4171  *
4172  * Field Access Macros:
4173  *
4174  */
4175 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_9_SEL register field. */
4176 #define ALT_PINMUX_SHARED_3V_IO_Q3_9_SEL_LSB 0
4177 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_9_SEL register field. */
4178 #define ALT_PINMUX_SHARED_3V_IO_Q3_9_SEL_MSB 3
4179 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_9_SEL register field. */
4180 #define ALT_PINMUX_SHARED_3V_IO_Q3_9_SEL_WIDTH 4
4181 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_9_SEL register field value. */
4182 #define ALT_PINMUX_SHARED_3V_IO_Q3_9_SEL_SET_MSK 0x0000000f
4183 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_9_SEL register field value. */
4184 #define ALT_PINMUX_SHARED_3V_IO_Q3_9_SEL_CLR_MSK 0xfffffff0
4185 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_9_SEL register field. */
4186 #define ALT_PINMUX_SHARED_3V_IO_Q3_9_SEL_RESET 0xf
4187 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_9_SEL field value from a register. */
4188 #define ALT_PINMUX_SHARED_3V_IO_Q3_9_SEL_GET(value) (((value) & 0x0000000f) >> 0)
4189 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_9_SEL register field value suitable for setting the register. */
4190 #define ALT_PINMUX_SHARED_3V_IO_Q3_9_SEL_SET(value) (((value) << 0) & 0x0000000f)
4191 
4192 /*
4193  * Field : Reserved
4194  *
4195  * Reserved
4196  *
4197  * Field Access Macros:
4198  *
4199  */
4200 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_9_RSVD register field. */
4201 #define ALT_PINMUX_SHARED_3V_IO_Q3_9_RSVD_LSB 4
4202 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_9_RSVD register field. */
4203 #define ALT_PINMUX_SHARED_3V_IO_Q3_9_RSVD_MSB 31
4204 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_9_RSVD register field. */
4205 #define ALT_PINMUX_SHARED_3V_IO_Q3_9_RSVD_WIDTH 28
4206 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_9_RSVD register field value. */
4207 #define ALT_PINMUX_SHARED_3V_IO_Q3_9_RSVD_SET_MSK 0xfffffff0
4208 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_9_RSVD register field value. */
4209 #define ALT_PINMUX_SHARED_3V_IO_Q3_9_RSVD_CLR_MSK 0x0000000f
4210 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_9_RSVD register field. */
4211 #define ALT_PINMUX_SHARED_3V_IO_Q3_9_RSVD_RESET 0x0
4212 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_9_RSVD field value from a register. */
4213 #define ALT_PINMUX_SHARED_3V_IO_Q3_9_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
4214 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_9_RSVD register field value suitable for setting the register. */
4215 #define ALT_PINMUX_SHARED_3V_IO_Q3_9_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
4216 
4217 #ifndef __ASSEMBLY__
4218 /*
4219  * WARNING: The C register and register group struct declarations are provided for
4220  * convenience and illustrative purposes. They should, however, be used with
4221  * caution as the C language standard provides no guarantees about the alignment or
4222  * atomicity of device memory accesses. The recommended practice for writing
4223  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4224  * alt_write_word() functions.
4225  *
4226  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_9.
4227  */
4228 struct ALT_PINMUX_SHARED_3V_IO_Q3_9_s
4229 {
4230  uint32_t sel : 4; /* Shared IO48 Q3 9 Mux Selection Field */
4231  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q3_9_RSVD */
4232 };
4233 
4234 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_9. */
4235 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q3_9_s ALT_PINMUX_SHARED_3V_IO_Q3_9_t;
4236 #endif /* __ASSEMBLY__ */
4237 
4238 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_9 register. */
4239 #define ALT_PINMUX_SHARED_3V_IO_Q3_9_RESET 0x0000000f
4240 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q3_9 register from the beginning of the component. */
4241 #define ALT_PINMUX_SHARED_3V_IO_Q3_9_OFST 0x80
4242 
4243 /*
4244  * Register : Shared IO 48 Q3 10 Mux Selection Register - pinmux_shared_io_q3_10
4245  *
4246  * This register is used to control the peripherals connected to shared IO48 pin Q3
4247  * 10
4248  *
4249  * Only reset by a cold reset (ignores warm reset).
4250  *
4251  * NOTE: These registers should not be modified after IO configuration.There is no
4252  * support for dynamically changing the Pin Mux selections.
4253  *
4254  * Register Layout
4255  *
4256  * Bits | Access | Reset | Description
4257  * :-------|:-------|:------|:--------------------------------------
4258  * [3:0] | RW | 0xf | Shared IO48 Q3 10 Mux Selection Field
4259  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q3_10_RSVD
4260  *
4261  */
4262 /*
4263  * Field : Shared IO48 Q3 10 Mux Selection Field - sel
4264  *
4265  * Select peripheral signals connected shared IO48 Q3 10
4266  *
4267  * 0000 (0) Pin is connected to Peripheral signal i2c_emac2.scl
4268  *
4269  * 0001 (1) Pin is connected to Peripheral signal emac2.mdc
4270  *
4271  * 0010 (2) Pin is connected to Peripheral signal spis0.mosi
4272  *
4273  * 0011 (3) Pin is connected to Peripheral signal not applicable
4274  *
4275  * 0100 (4) Pin is connected to Peripheral signal not applicable
4276  *
4277  * 0101 (5) Pin is connected to Peripheral signal not applicable
4278  *
4279  * 0110 (6) Pin is connected to Peripheral signal not applicable
4280  *
4281  * 0111 (7) Pin is connected to Peripheral signal not applicable
4282  *
4283  * 1000 (8) Pin is connected to Peripheral signal emac1.txd3
4284  *
4285  * 1001 (9) Pin is connected to Peripheral signal not applicable
4286  *
4287  * 1010 (10) Pin is connected to Peripheral signal not applicable
4288  *
4289  * 1011 (11) Pin is connected to Peripheral signal not applicable
4290  *
4291  * 1100 (12) Pin is connected to Peripheral signal not applicable
4292  *
4293  * 1101 (13) Pin is connected to Peripheral signal not applicable
4294  *
4295  * 1110 (14) Pin is connected to Peripheral signal nand.adq5
4296  *
4297  * 1111 (15) Pin is connected to Peripheral signal gpio1.io9
4298  *
4299  * Field Access Macros:
4300  *
4301  */
4302 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_10_SEL register field. */
4303 #define ALT_PINMUX_SHARED_3V_IO_Q3_10_SEL_LSB 0
4304 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_10_SEL register field. */
4305 #define ALT_PINMUX_SHARED_3V_IO_Q3_10_SEL_MSB 3
4306 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_10_SEL register field. */
4307 #define ALT_PINMUX_SHARED_3V_IO_Q3_10_SEL_WIDTH 4
4308 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_10_SEL register field value. */
4309 #define ALT_PINMUX_SHARED_3V_IO_Q3_10_SEL_SET_MSK 0x0000000f
4310 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_10_SEL register field value. */
4311 #define ALT_PINMUX_SHARED_3V_IO_Q3_10_SEL_CLR_MSK 0xfffffff0
4312 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_10_SEL register field. */
4313 #define ALT_PINMUX_SHARED_3V_IO_Q3_10_SEL_RESET 0xf
4314 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_10_SEL field value from a register. */
4315 #define ALT_PINMUX_SHARED_3V_IO_Q3_10_SEL_GET(value) (((value) & 0x0000000f) >> 0)
4316 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_10_SEL register field value suitable for setting the register. */
4317 #define ALT_PINMUX_SHARED_3V_IO_Q3_10_SEL_SET(value) (((value) << 0) & 0x0000000f)
4318 
4319 /*
4320  * Field : Reserved
4321  *
4322  * Reserved
4323  *
4324  * Field Access Macros:
4325  *
4326  */
4327 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_10_RSVD register field. */
4328 #define ALT_PINMUX_SHARED_3V_IO_Q3_10_RSVD_LSB 4
4329 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_10_RSVD register field. */
4330 #define ALT_PINMUX_SHARED_3V_IO_Q3_10_RSVD_MSB 31
4331 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_10_RSVD register field. */
4332 #define ALT_PINMUX_SHARED_3V_IO_Q3_10_RSVD_WIDTH 28
4333 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_10_RSVD register field value. */
4334 #define ALT_PINMUX_SHARED_3V_IO_Q3_10_RSVD_SET_MSK 0xfffffff0
4335 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_10_RSVD register field value. */
4336 #define ALT_PINMUX_SHARED_3V_IO_Q3_10_RSVD_CLR_MSK 0x0000000f
4337 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_10_RSVD register field. */
4338 #define ALT_PINMUX_SHARED_3V_IO_Q3_10_RSVD_RESET 0x0
4339 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_10_RSVD field value from a register. */
4340 #define ALT_PINMUX_SHARED_3V_IO_Q3_10_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
4341 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_10_RSVD register field value suitable for setting the register. */
4342 #define ALT_PINMUX_SHARED_3V_IO_Q3_10_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
4343 
4344 #ifndef __ASSEMBLY__
4345 /*
4346  * WARNING: The C register and register group struct declarations are provided for
4347  * convenience and illustrative purposes. They should, however, be used with
4348  * caution as the C language standard provides no guarantees about the alignment or
4349  * atomicity of device memory accesses. The recommended practice for writing
4350  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4351  * alt_write_word() functions.
4352  *
4353  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_10.
4354  */
4355 struct ALT_PINMUX_SHARED_3V_IO_Q3_10_s
4356 {
4357  uint32_t sel : 4; /* Shared IO48 Q3 10 Mux Selection Field */
4358  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q3_10_RSVD */
4359 };
4360 
4361 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_10. */
4362 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q3_10_s ALT_PINMUX_SHARED_3V_IO_Q3_10_t;
4363 #endif /* __ASSEMBLY__ */
4364 
4365 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_10 register. */
4366 #define ALT_PINMUX_SHARED_3V_IO_Q3_10_RESET 0x0000000f
4367 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q3_10 register from the beginning of the component. */
4368 #define ALT_PINMUX_SHARED_3V_IO_Q3_10_OFST 0x84
4369 
4370 /*
4371  * Register : Shared IO 48 Q3 11 Mux Selection Register - pinmux_shared_io_q3_11
4372  *
4373  * This register is used to control the peripherals connected to shared IO48 pin Q3
4374  * 11
4375  *
4376  * Only reset by a cold reset (ignores warm reset).
4377  *
4378  * NOTE: These registers should not be modified after IO configuration.There is no
4379  * support for dynamically changing the Pin Mux selections.
4380  *
4381  * Register Layout
4382  *
4383  * Bits | Access | Reset | Description
4384  * :-------|:-------|:------|:--------------------------------------
4385  * [3:0] | RW | 0xf | Shared IO48 Q3 11 Mux Selection Field
4386  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q3_11_RSVD
4387  *
4388  */
4389 /*
4390  * Field : Shared IO48 Q3 11 Mux Selection Field - sel
4391  *
4392  * Select peripheral signals connected shared IO48 Q3 11
4393  *
4394  * 0000 (0) Pin is connected to Peripheral signal i2c_emac0.sda
4395  *
4396  * 0001 (1) Pin is connected to Peripheral signal emac0.mdio
4397  *
4398  * 0010 (2) Pin is connected to Peripheral signal spis0.ss0_n
4399  *
4400  * 0011 (3) Pin is connected to Peripheral signal not applicable
4401  *
4402  * 0100 (4) Pin is connected to Peripheral signal not applicable
4403  *
4404  * 0101 (5) Pin is connected to Peripheral signal not applicable
4405  *
4406  * 0110 (6) Pin is connected to Peripheral signal not applicable
4407  *
4408  * 0111 (7) Pin is connected to Peripheral signal not applicable
4409  *
4410  * 1000 (8) Pin is connected to Peripheral signal emac1.rxd2
4411  *
4412  * 1001 (9) Pin is connected to Peripheral signal not applicable
4413  *
4414  * 1010 (10) Pin is connected to Peripheral signal not applicable
4415  *
4416  * 1011 (11) Pin is connected to Peripheral signal not applicable
4417  *
4418  * 1100 (12) Pin is connected to Peripheral signal not applicable
4419  *
4420  * 1101 (13) Pin is connected to Peripheral signal not applicable
4421  *
4422  * 1110 (14) Pin is connected to Peripheral signal nand.adq6
4423  *
4424  * 1111 (15) Pin is connected to Peripheral signal gpio1.io10
4425  *
4426  * Field Access Macros:
4427  *
4428  */
4429 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_11_SEL register field. */
4430 #define ALT_PINMUX_SHARED_3V_IO_Q3_11_SEL_LSB 0
4431 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_11_SEL register field. */
4432 #define ALT_PINMUX_SHARED_3V_IO_Q3_11_SEL_MSB 3
4433 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_11_SEL register field. */
4434 #define ALT_PINMUX_SHARED_3V_IO_Q3_11_SEL_WIDTH 4
4435 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_11_SEL register field value. */
4436 #define ALT_PINMUX_SHARED_3V_IO_Q3_11_SEL_SET_MSK 0x0000000f
4437 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_11_SEL register field value. */
4438 #define ALT_PINMUX_SHARED_3V_IO_Q3_11_SEL_CLR_MSK 0xfffffff0
4439 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_11_SEL register field. */
4440 #define ALT_PINMUX_SHARED_3V_IO_Q3_11_SEL_RESET 0xf
4441 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_11_SEL field value from a register. */
4442 #define ALT_PINMUX_SHARED_3V_IO_Q3_11_SEL_GET(value) (((value) & 0x0000000f) >> 0)
4443 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_11_SEL register field value suitable for setting the register. */
4444 #define ALT_PINMUX_SHARED_3V_IO_Q3_11_SEL_SET(value) (((value) << 0) & 0x0000000f)
4445 
4446 /*
4447  * Field : Reserved
4448  *
4449  * Reserved
4450  *
4451  * Field Access Macros:
4452  *
4453  */
4454 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_11_RSVD register field. */
4455 #define ALT_PINMUX_SHARED_3V_IO_Q3_11_RSVD_LSB 4
4456 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_11_RSVD register field. */
4457 #define ALT_PINMUX_SHARED_3V_IO_Q3_11_RSVD_MSB 31
4458 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_11_RSVD register field. */
4459 #define ALT_PINMUX_SHARED_3V_IO_Q3_11_RSVD_WIDTH 28
4460 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_11_RSVD register field value. */
4461 #define ALT_PINMUX_SHARED_3V_IO_Q3_11_RSVD_SET_MSK 0xfffffff0
4462 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_11_RSVD register field value. */
4463 #define ALT_PINMUX_SHARED_3V_IO_Q3_11_RSVD_CLR_MSK 0x0000000f
4464 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_11_RSVD register field. */
4465 #define ALT_PINMUX_SHARED_3V_IO_Q3_11_RSVD_RESET 0x0
4466 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_11_RSVD field value from a register. */
4467 #define ALT_PINMUX_SHARED_3V_IO_Q3_11_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
4468 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_11_RSVD register field value suitable for setting the register. */
4469 #define ALT_PINMUX_SHARED_3V_IO_Q3_11_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
4470 
4471 #ifndef __ASSEMBLY__
4472 /*
4473  * WARNING: The C register and register group struct declarations are provided for
4474  * convenience and illustrative purposes. They should, however, be used with
4475  * caution as the C language standard provides no guarantees about the alignment or
4476  * atomicity of device memory accesses. The recommended practice for writing
4477  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4478  * alt_write_word() functions.
4479  *
4480  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_11.
4481  */
4482 struct ALT_PINMUX_SHARED_3V_IO_Q3_11_s
4483 {
4484  uint32_t sel : 4; /* Shared IO48 Q3 11 Mux Selection Field */
4485  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q3_11_RSVD */
4486 };
4487 
4488 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_11. */
4489 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q3_11_s ALT_PINMUX_SHARED_3V_IO_Q3_11_t;
4490 #endif /* __ASSEMBLY__ */
4491 
4492 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_11 register. */
4493 #define ALT_PINMUX_SHARED_3V_IO_Q3_11_RESET 0x0000000f
4494 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q3_11 register from the beginning of the component. */
4495 #define ALT_PINMUX_SHARED_3V_IO_Q3_11_OFST 0x88
4496 
4497 /*
4498  * Register : Shared IO 48 Q3 12 Mux Selection Register - pinmux_shared_io_q3_12
4499  *
4500  * This register is used to control the peripherals connected to shared IO48 pin Q3
4501  * 12
4502  *
4503  * Only reset by a cold reset (ignores warm reset).
4504  *
4505  * NOTE: These registers should not be modified after IO configuration.There is no
4506  * support for dynamically changing the Pin Mux selections.
4507  *
4508  * Register Layout
4509  *
4510  * Bits | Access | Reset | Description
4511  * :-------|:-------|:------|:--------------------------------------
4512  * [3:0] | RW | 0xf | Shared IO48 Q3 12 Mux Selection Field
4513  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q3_12_RSVD
4514  *
4515  */
4516 /*
4517  * Field : Shared IO48 Q3 12 Mux Selection Field - sel
4518  *
4519  * Select peripheral signals connected shared IO48 Q3 12
4520  *
4521  * 0000 (0) Pin is connected to Peripheral signal i2c_emac0.scl
4522  *
4523  * 0001 (1) Pin is connected to Peripheral signal emac0.mdc
4524  *
4525  * 0010 (2) Pin is connected to Peripheral signal spis0.miso
4526  *
4527  * 0011 (3) Pin is connected to Peripheral signal not applicable
4528  *
4529  * 0100 (4) Pin is connected to Peripheral signal not applicable
4530  *
4531  * 0101 (5) Pin is connected to Peripheral signal not applicable
4532  *
4533  * 0110 (6) Pin is connected to Peripheral signal not applicable
4534  *
4535  * 0111 (7) Pin is connected to Peripheral signal not applicable
4536  *
4537  * 1000 (8) Pin is connected to Peripheral signal emac1.rxd3
4538  *
4539  * 1001 (9) Pin is connected to Peripheral signal not applicable
4540  *
4541  * 1010 (10) Pin is connected to Peripheral signal not applicable
4542  *
4543  * 1011 (11) Pin is connected to Peripheral signal not applicable
4544  *
4545  * 1100 (12) Pin is connected to Peripheral signal not applicable
4546  *
4547  * 1101 (13) Pin is connected to Peripheral signal not applicable
4548  *
4549  * 1110 (14) Pin is connected to Peripheral signal nand.adq7
4550  *
4551  * 1111 (15) Pin is connected to Peripheral signal gpio1.io11
4552  *
4553  * Field Access Macros:
4554  *
4555  */
4556 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_12_SEL register field. */
4557 #define ALT_PINMUX_SHARED_3V_IO_Q3_12_SEL_LSB 0
4558 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_12_SEL register field. */
4559 #define ALT_PINMUX_SHARED_3V_IO_Q3_12_SEL_MSB 3
4560 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_12_SEL register field. */
4561 #define ALT_PINMUX_SHARED_3V_IO_Q3_12_SEL_WIDTH 4
4562 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_12_SEL register field value. */
4563 #define ALT_PINMUX_SHARED_3V_IO_Q3_12_SEL_SET_MSK 0x0000000f
4564 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_12_SEL register field value. */
4565 #define ALT_PINMUX_SHARED_3V_IO_Q3_12_SEL_CLR_MSK 0xfffffff0
4566 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_12_SEL register field. */
4567 #define ALT_PINMUX_SHARED_3V_IO_Q3_12_SEL_RESET 0xf
4568 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_12_SEL field value from a register. */
4569 #define ALT_PINMUX_SHARED_3V_IO_Q3_12_SEL_GET(value) (((value) & 0x0000000f) >> 0)
4570 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_12_SEL register field value suitable for setting the register. */
4571 #define ALT_PINMUX_SHARED_3V_IO_Q3_12_SEL_SET(value) (((value) << 0) & 0x0000000f)
4572 
4573 /*
4574  * Field : Reserved
4575  *
4576  * Reserved
4577  *
4578  * Field Access Macros:
4579  *
4580  */
4581 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_12_RSVD register field. */
4582 #define ALT_PINMUX_SHARED_3V_IO_Q3_12_RSVD_LSB 4
4583 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q3_12_RSVD register field. */
4584 #define ALT_PINMUX_SHARED_3V_IO_Q3_12_RSVD_MSB 31
4585 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q3_12_RSVD register field. */
4586 #define ALT_PINMUX_SHARED_3V_IO_Q3_12_RSVD_WIDTH 28
4587 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q3_12_RSVD register field value. */
4588 #define ALT_PINMUX_SHARED_3V_IO_Q3_12_RSVD_SET_MSK 0xfffffff0
4589 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q3_12_RSVD register field value. */
4590 #define ALT_PINMUX_SHARED_3V_IO_Q3_12_RSVD_CLR_MSK 0x0000000f
4591 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_12_RSVD register field. */
4592 #define ALT_PINMUX_SHARED_3V_IO_Q3_12_RSVD_RESET 0x0
4593 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q3_12_RSVD field value from a register. */
4594 #define ALT_PINMUX_SHARED_3V_IO_Q3_12_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
4595 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q3_12_RSVD register field value suitable for setting the register. */
4596 #define ALT_PINMUX_SHARED_3V_IO_Q3_12_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
4597 
4598 #ifndef __ASSEMBLY__
4599 /*
4600  * WARNING: The C register and register group struct declarations are provided for
4601  * convenience and illustrative purposes. They should, however, be used with
4602  * caution as the C language standard provides no guarantees about the alignment or
4603  * atomicity of device memory accesses. The recommended practice for writing
4604  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4605  * alt_write_word() functions.
4606  *
4607  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_12.
4608  */
4609 struct ALT_PINMUX_SHARED_3V_IO_Q3_12_s
4610 {
4611  uint32_t sel : 4; /* Shared IO48 Q3 12 Mux Selection Field */
4612  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q3_12_RSVD */
4613 };
4614 
4615 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q3_12. */
4616 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q3_12_s ALT_PINMUX_SHARED_3V_IO_Q3_12_t;
4617 #endif /* __ASSEMBLY__ */
4618 
4619 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q3_12 register. */
4620 #define ALT_PINMUX_SHARED_3V_IO_Q3_12_RESET 0x0000000f
4621 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q3_12 register from the beginning of the component. */
4622 #define ALT_PINMUX_SHARED_3V_IO_Q3_12_OFST 0x8c
4623 
4624 /*
4625  * Register : Shared IO 48 Q4 1 Mux Selection Register - pinmux_shared_io_q4_1
4626  *
4627  * This register is used to control the peripherals connected to shared IO48 pin Q4
4628  * 1
4629  *
4630  * Only reset by a cold reset (ignores warm reset).
4631  *
4632  * NOTE: These registers should not be modified after IO configuration.There is no
4633  * support for dynamically changing the Pin Mux selections.
4634  *
4635  * Register Layout
4636  *
4637  * Bits | Access | Reset | Description
4638  * :-------|:-------|:------|:-------------------------------------
4639  * [3:0] | RW | 0xf | Shared IO48 Q4 1 Mux Selection Field
4640  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q4_1_RSVD
4641  *
4642  */
4643 /*
4644  * Field : Shared IO48 Q4 1 Mux Selection Field - sel
4645  *
4646  * Select peripheral signals connected shared IO48 Q4 1
4647  *
4648  * 0000 (0) Pin is connected to Peripheral signal i2c1.sda
4649  *
4650  * 0001 (1) Pin is connected to Peripheral signal not applicable
4651  *
4652  * 0010 (2) Pin is connected to Peripheral signal not applicable
4653  *
4654  * 0011 (3) Pin is connected to Peripheral signal not applicable
4655  *
4656  * 0100 (4) Pin is connected to Peripheral signal sdmmc.data0
4657  *
4658  * 0101 (5) Pin is connected to Peripheral signal not applicable
4659  *
4660  * 0110 (6) Pin is connected to Peripheral signal not applicable
4661  *
4662  * 0111 (7) Pin is connected to Peripheral signal not applicable
4663  *
4664  * 1000 (8) Pin is connected to Peripheral signal emac2.tx_clk
4665  *
4666  * 1001 (9) Pin is connected to Peripheral signal not applicable
4667  *
4668  * 1010 (10) Pin is connected to Peripheral signal not applicable
4669  *
4670  * 1011 (11) Pin is connected to Peripheral signal not applicable
4671  *
4672  * 1100 (12) Pin is connected to Peripheral signal not applicable
4673  *
4674  * 1101 (13) Pin is connected to Peripheral signal not applicable
4675  *
4676  * 1110 (14) Pin is connected to Peripheral signal nand.ale
4677  *
4678  * 1111 (15) Pin is connected to Peripheral signal gpio1.io12
4679  *
4680  * Field Access Macros:
4681  *
4682  */
4683 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_1_SEL register field. */
4684 #define ALT_PINMUX_SHARED_3V_IO_Q4_1_SEL_LSB 0
4685 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_1_SEL register field. */
4686 #define ALT_PINMUX_SHARED_3V_IO_Q4_1_SEL_MSB 3
4687 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_1_SEL register field. */
4688 #define ALT_PINMUX_SHARED_3V_IO_Q4_1_SEL_WIDTH 4
4689 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_1_SEL register field value. */
4690 #define ALT_PINMUX_SHARED_3V_IO_Q4_1_SEL_SET_MSK 0x0000000f
4691 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_1_SEL register field value. */
4692 #define ALT_PINMUX_SHARED_3V_IO_Q4_1_SEL_CLR_MSK 0xfffffff0
4693 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_1_SEL register field. */
4694 #define ALT_PINMUX_SHARED_3V_IO_Q4_1_SEL_RESET 0xf
4695 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_1_SEL field value from a register. */
4696 #define ALT_PINMUX_SHARED_3V_IO_Q4_1_SEL_GET(value) (((value) & 0x0000000f) >> 0)
4697 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_1_SEL register field value suitable for setting the register. */
4698 #define ALT_PINMUX_SHARED_3V_IO_Q4_1_SEL_SET(value) (((value) << 0) & 0x0000000f)
4699 
4700 /*
4701  * Field : Reserved
4702  *
4703  * Reserved
4704  *
4705  * Field Access Macros:
4706  *
4707  */
4708 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_1_RSVD register field. */
4709 #define ALT_PINMUX_SHARED_3V_IO_Q4_1_RSVD_LSB 4
4710 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_1_RSVD register field. */
4711 #define ALT_PINMUX_SHARED_3V_IO_Q4_1_RSVD_MSB 31
4712 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_1_RSVD register field. */
4713 #define ALT_PINMUX_SHARED_3V_IO_Q4_1_RSVD_WIDTH 28
4714 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_1_RSVD register field value. */
4715 #define ALT_PINMUX_SHARED_3V_IO_Q4_1_RSVD_SET_MSK 0xfffffff0
4716 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_1_RSVD register field value. */
4717 #define ALT_PINMUX_SHARED_3V_IO_Q4_1_RSVD_CLR_MSK 0x0000000f
4718 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_1_RSVD register field. */
4719 #define ALT_PINMUX_SHARED_3V_IO_Q4_1_RSVD_RESET 0x0
4720 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_1_RSVD field value from a register. */
4721 #define ALT_PINMUX_SHARED_3V_IO_Q4_1_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
4722 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_1_RSVD register field value suitable for setting the register. */
4723 #define ALT_PINMUX_SHARED_3V_IO_Q4_1_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
4724 
4725 #ifndef __ASSEMBLY__
4726 /*
4727  * WARNING: The C register and register group struct declarations are provided for
4728  * convenience and illustrative purposes. They should, however, be used with
4729  * caution as the C language standard provides no guarantees about the alignment or
4730  * atomicity of device memory accesses. The recommended practice for writing
4731  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4732  * alt_write_word() functions.
4733  *
4734  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_1.
4735  */
4736 struct ALT_PINMUX_SHARED_3V_IO_Q4_1_s
4737 {
4738  uint32_t sel : 4; /* Shared IO48 Q4 1 Mux Selection Field */
4739  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q4_1_RSVD */
4740 };
4741 
4742 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_1. */
4743 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q4_1_s ALT_PINMUX_SHARED_3V_IO_Q4_1_t;
4744 #endif /* __ASSEMBLY__ */
4745 
4746 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_1 register. */
4747 #define ALT_PINMUX_SHARED_3V_IO_Q4_1_RESET 0x0000000f
4748 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q4_1 register from the beginning of the component. */
4749 #define ALT_PINMUX_SHARED_3V_IO_Q4_1_OFST 0x90
4750 
4751 /*
4752  * Register : Shared IO 48 Q4 2 Mux Selection Register - pinmux_shared_io_q4_2
4753  *
4754  * This register is used to control the peripherals connected to shared IO48 pin Q4
4755  * 2
4756  *
4757  * Only reset by a cold reset (ignores warm reset).
4758  *
4759  * NOTE: These registers should not be modified after IO configuration.There is no
4760  * support for dynamically changing the Pin Mux selections.
4761  *
4762  * Register Layout
4763  *
4764  * Bits | Access | Reset | Description
4765  * :-------|:-------|:------|:-------------------------------------
4766  * [3:0] | RW | 0xf | Shared IO48 Q4 2 Mux Selection Field
4767  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q4_2_RSVD
4768  *
4769  */
4770 /*
4771  * Field : Shared IO48 Q4 2 Mux Selection Field - sel
4772  *
4773  * Select peripheral signals connected shared IO48 Q4 2
4774  *
4775  * 0000 (0) Pin is connected to Peripheral signal i2c1.scl
4776  *
4777  * 0001 (1) Pin is connected to Peripheral signal not applicable
4778  *
4779  * 0010 (2) Pin is connected to Peripheral signal not applicable
4780  *
4781  * 0011 (3) Pin is connected to Peripheral signal not applicable
4782  *
4783  * 0100 (4) Pin is connected to Peripheral signal sdmmc.cmd
4784  *
4785  * 0101 (5) Pin is connected to Peripheral signal not applicable
4786  *
4787  * 0110 (6) Pin is connected to Peripheral signal not applicable
4788  *
4789  * 0111 (7) Pin is connected to Peripheral signal not applicable
4790  *
4791  * 1000 (8) Pin is connected to Peripheral signal emac2.tx_ctl
4792  *
4793  * 1001 (9) Pin is connected to Peripheral signal not applicable
4794  *
4795  * 1010 (10) Pin is connected to Peripheral signal not applicable
4796  *
4797  * 1011 (11) Pin is connected to Peripheral signal not applicable
4798  *
4799  * 1100 (12) Pin is connected to Peripheral signal not applicable
4800  *
4801  * 1101 (13) Pin is connected to Peripheral signal not applicable
4802  *
4803  * 1110 (14) Pin is connected to Peripheral signal nand.rb
4804  *
4805  * 1111 (15) Pin is connected to Peripheral signal gpio1.io13
4806  *
4807  * Field Access Macros:
4808  *
4809  */
4810 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_2_SEL register field. */
4811 #define ALT_PINMUX_SHARED_3V_IO_Q4_2_SEL_LSB 0
4812 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_2_SEL register field. */
4813 #define ALT_PINMUX_SHARED_3V_IO_Q4_2_SEL_MSB 3
4814 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_2_SEL register field. */
4815 #define ALT_PINMUX_SHARED_3V_IO_Q4_2_SEL_WIDTH 4
4816 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_2_SEL register field value. */
4817 #define ALT_PINMUX_SHARED_3V_IO_Q4_2_SEL_SET_MSK 0x0000000f
4818 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_2_SEL register field value. */
4819 #define ALT_PINMUX_SHARED_3V_IO_Q4_2_SEL_CLR_MSK 0xfffffff0
4820 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_2_SEL register field. */
4821 #define ALT_PINMUX_SHARED_3V_IO_Q4_2_SEL_RESET 0xf
4822 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_2_SEL field value from a register. */
4823 #define ALT_PINMUX_SHARED_3V_IO_Q4_2_SEL_GET(value) (((value) & 0x0000000f) >> 0)
4824 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_2_SEL register field value suitable for setting the register. */
4825 #define ALT_PINMUX_SHARED_3V_IO_Q4_2_SEL_SET(value) (((value) << 0) & 0x0000000f)
4826 
4827 /*
4828  * Field : Reserved
4829  *
4830  * Reserved
4831  *
4832  * Field Access Macros:
4833  *
4834  */
4835 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_2_RSVD register field. */
4836 #define ALT_PINMUX_SHARED_3V_IO_Q4_2_RSVD_LSB 4
4837 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_2_RSVD register field. */
4838 #define ALT_PINMUX_SHARED_3V_IO_Q4_2_RSVD_MSB 31
4839 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_2_RSVD register field. */
4840 #define ALT_PINMUX_SHARED_3V_IO_Q4_2_RSVD_WIDTH 28
4841 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_2_RSVD register field value. */
4842 #define ALT_PINMUX_SHARED_3V_IO_Q4_2_RSVD_SET_MSK 0xfffffff0
4843 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_2_RSVD register field value. */
4844 #define ALT_PINMUX_SHARED_3V_IO_Q4_2_RSVD_CLR_MSK 0x0000000f
4845 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_2_RSVD register field. */
4846 #define ALT_PINMUX_SHARED_3V_IO_Q4_2_RSVD_RESET 0x0
4847 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_2_RSVD field value from a register. */
4848 #define ALT_PINMUX_SHARED_3V_IO_Q4_2_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
4849 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_2_RSVD register field value suitable for setting the register. */
4850 #define ALT_PINMUX_SHARED_3V_IO_Q4_2_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
4851 
4852 #ifndef __ASSEMBLY__
4853 /*
4854  * WARNING: The C register and register group struct declarations are provided for
4855  * convenience and illustrative purposes. They should, however, be used with
4856  * caution as the C language standard provides no guarantees about the alignment or
4857  * atomicity of device memory accesses. The recommended practice for writing
4858  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4859  * alt_write_word() functions.
4860  *
4861  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_2.
4862  */
4863 struct ALT_PINMUX_SHARED_3V_IO_Q4_2_s
4864 {
4865  uint32_t sel : 4; /* Shared IO48 Q4 2 Mux Selection Field */
4866  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q4_2_RSVD */
4867 };
4868 
4869 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_2. */
4870 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q4_2_s ALT_PINMUX_SHARED_3V_IO_Q4_2_t;
4871 #endif /* __ASSEMBLY__ */
4872 
4873 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_2 register. */
4874 #define ALT_PINMUX_SHARED_3V_IO_Q4_2_RESET 0x0000000f
4875 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q4_2 register from the beginning of the component. */
4876 #define ALT_PINMUX_SHARED_3V_IO_Q4_2_OFST 0x94
4877 
4878 /*
4879  * Register : Shared IO 48 Q4 3 Mux Selection Register - pinmux_shared_io_q4_3
4880  *
4881  * This register is used to control the peripherals connected to shared IO48 pin Q4
4882  * 3
4883  *
4884  * Only reset by a cold reset (ignores warm reset).
4885  *
4886  * NOTE: These registers should not be modified after IO configuration.There is no
4887  * support for dynamically changing the Pin Mux selections.
4888  *
4889  * Register Layout
4890  *
4891  * Bits | Access | Reset | Description
4892  * :-------|:-------|:------|:-------------------------------------
4893  * [3:0] | RW | 0xf | Shared IO48 Q4 3 Mux Selection Field
4894  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q4_3_RSVD
4895  *
4896  */
4897 /*
4898  * Field : Shared IO48 Q4 3 Mux Selection Field - sel
4899  *
4900  * Select peripheral signals connected shared IO48 Q4 3
4901  *
4902  * 0000 (0) Pin is connected to Peripheral signal not applicable
4903  *
4904  * 0001 (1) Pin is connected to Peripheral signal not applicable
4905  *
4906  * 0010 (2) Pin is connected to Peripheral signal not applicable
4907  *
4908  * 0011 (3) Pin is connected to Peripheral signal not applicable
4909  *
4910  * 0100 (4) Pin is connected to Peripheral signal sdmmc.cclk
4911  *
4912  * 0101 (5) Pin is connected to Peripheral signal not applicable
4913  *
4914  * 0110 (6) Pin is connected to Peripheral signal not applicable
4915  *
4916  * 0111 (7) Pin is connected to Peripheral signal not applicable
4917  *
4918  * 1000 (8) Pin is connected to Peripheral signal emac2.rx_clk
4919  *
4920  * 1001 (9) Pin is connected to Peripheral signal not applicable
4921  *
4922  * 1010 (10) Pin is connected to Peripheral signal not applicable
4923  *
4924  * 1011 (11) Pin is connected to Peripheral signal not applicable
4925  *
4926  * 1100 (12) Pin is connected to Peripheral signal not applicable
4927  *
4928  * 1101 (13) Pin is connected to Peripheral signal uart1.tx
4929  *
4930  * 1110 (14) Pin is connected to Peripheral signal nand.ce_n
4931  *
4932  * 1111 (15) Pin is connected to Peripheral signal gpio1.io14
4933  *
4934  * Field Access Macros:
4935  *
4936  */
4937 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_3_SEL register field. */
4938 #define ALT_PINMUX_SHARED_3V_IO_Q4_3_SEL_LSB 0
4939 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_3_SEL register field. */
4940 #define ALT_PINMUX_SHARED_3V_IO_Q4_3_SEL_MSB 3
4941 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_3_SEL register field. */
4942 #define ALT_PINMUX_SHARED_3V_IO_Q4_3_SEL_WIDTH 4
4943 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_3_SEL register field value. */
4944 #define ALT_PINMUX_SHARED_3V_IO_Q4_3_SEL_SET_MSK 0x0000000f
4945 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_3_SEL register field value. */
4946 #define ALT_PINMUX_SHARED_3V_IO_Q4_3_SEL_CLR_MSK 0xfffffff0
4947 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_3_SEL register field. */
4948 #define ALT_PINMUX_SHARED_3V_IO_Q4_3_SEL_RESET 0xf
4949 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_3_SEL field value from a register. */
4950 #define ALT_PINMUX_SHARED_3V_IO_Q4_3_SEL_GET(value) (((value) & 0x0000000f) >> 0)
4951 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_3_SEL register field value suitable for setting the register. */
4952 #define ALT_PINMUX_SHARED_3V_IO_Q4_3_SEL_SET(value) (((value) << 0) & 0x0000000f)
4953 
4954 /*
4955  * Field : Reserved
4956  *
4957  * Reserved
4958  *
4959  * Field Access Macros:
4960  *
4961  */
4962 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_3_RSVD register field. */
4963 #define ALT_PINMUX_SHARED_3V_IO_Q4_3_RSVD_LSB 4
4964 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_3_RSVD register field. */
4965 #define ALT_PINMUX_SHARED_3V_IO_Q4_3_RSVD_MSB 31
4966 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_3_RSVD register field. */
4967 #define ALT_PINMUX_SHARED_3V_IO_Q4_3_RSVD_WIDTH 28
4968 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_3_RSVD register field value. */
4969 #define ALT_PINMUX_SHARED_3V_IO_Q4_3_RSVD_SET_MSK 0xfffffff0
4970 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_3_RSVD register field value. */
4971 #define ALT_PINMUX_SHARED_3V_IO_Q4_3_RSVD_CLR_MSK 0x0000000f
4972 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_3_RSVD register field. */
4973 #define ALT_PINMUX_SHARED_3V_IO_Q4_3_RSVD_RESET 0x0
4974 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_3_RSVD field value from a register. */
4975 #define ALT_PINMUX_SHARED_3V_IO_Q4_3_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
4976 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_3_RSVD register field value suitable for setting the register. */
4977 #define ALT_PINMUX_SHARED_3V_IO_Q4_3_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
4978 
4979 #ifndef __ASSEMBLY__
4980 /*
4981  * WARNING: The C register and register group struct declarations are provided for
4982  * convenience and illustrative purposes. They should, however, be used with
4983  * caution as the C language standard provides no guarantees about the alignment or
4984  * atomicity of device memory accesses. The recommended practice for writing
4985  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4986  * alt_write_word() functions.
4987  *
4988  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_3.
4989  */
4990 struct ALT_PINMUX_SHARED_3V_IO_Q4_3_s
4991 {
4992  uint32_t sel : 4; /* Shared IO48 Q4 3 Mux Selection Field */
4993  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q4_3_RSVD */
4994 };
4995 
4996 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_3. */
4997 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q4_3_s ALT_PINMUX_SHARED_3V_IO_Q4_3_t;
4998 #endif /* __ASSEMBLY__ */
4999 
5000 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_3 register. */
5001 #define ALT_PINMUX_SHARED_3V_IO_Q4_3_RESET 0x0000000f
5002 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q4_3 register from the beginning of the component. */
5003 #define ALT_PINMUX_SHARED_3V_IO_Q4_3_OFST 0x98
5004 
5005 /*
5006  * Register : Shared IO 48 Q4 4 Mux Selection Register - pinmux_shared_io_q4_4
5007  *
5008  * This register is used to control the peripherals connected to shared IO48 pin Q4
5009  * 4
5010  *
5011  * Only reset by a cold reset (ignores warm reset).
5012  *
5013  * NOTE: These registers should not be modified after IO configuration.There is no
5014  * support for dynamically changing the Pin Mux selections.
5015  *
5016  * Register Layout
5017  *
5018  * Bits | Access | Reset | Description
5019  * :-------|:-------|:------|:-------------------------------------
5020  * [3:0] | RW | 0xf | Shared IO48 Q4 4 Mux Selection Field
5021  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q4_4_RSVD
5022  *
5023  */
5024 /*
5025  * Field : Shared IO48 Q4 4 Mux Selection Field - sel
5026  *
5027  * Select peripheral signals connected shared IO48 Q4 4
5028  *
5029  * 0000 (0) Pin is connected to Peripheral signal not applicable
5030  *
5031  * 0001 (1) Pin is connected to Peripheral signal not applicable
5032  *
5033  * 0010 (2) Pin is connected to Peripheral signal not applicable
5034  *
5035  * 0011 (3) Pin is connected to Peripheral signal not applicable
5036  *
5037  * 0100 (4) Pin is connected to Peripheral signal sdmmc.data1
5038  *
5039  * 0101 (5) Pin is connected to Peripheral signal not applicable
5040  *
5041  * 0110 (6) Pin is connected to Peripheral signal not applicable
5042  *
5043  * 0111 (7) Pin is connected to Peripheral signal not applicable
5044  *
5045  * 1000 (8) Pin is connected to Peripheral signal emac2.rx_ctl
5046  *
5047  * 1001 (9) Pin is connected to Peripheral signal not applicable
5048  *
5049  * 1010 (10) Pin is connected to Peripheral signal not applicable
5050  *
5051  * 1011 (11) Pin is connected to Peripheral signal not applicable
5052  *
5053  * 1100 (12) Pin is connected to Peripheral signal trace.clk
5054  *
5055  * 1101 (13) Pin is connected to Peripheral signal uart1.rx
5056  *
5057  * 1110 (14) Pin is connected to Peripheral signal not applicable
5058  *
5059  * 1111 (15) Pin is connected to Peripheral signal gpio1.io15
5060  *
5061  * Field Access Macros:
5062  *
5063  */
5064 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_4_SEL register field. */
5065 #define ALT_PINMUX_SHARED_3V_IO_Q4_4_SEL_LSB 0
5066 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_4_SEL register field. */
5067 #define ALT_PINMUX_SHARED_3V_IO_Q4_4_SEL_MSB 3
5068 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_4_SEL register field. */
5069 #define ALT_PINMUX_SHARED_3V_IO_Q4_4_SEL_WIDTH 4
5070 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_4_SEL register field value. */
5071 #define ALT_PINMUX_SHARED_3V_IO_Q4_4_SEL_SET_MSK 0x0000000f
5072 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_4_SEL register field value. */
5073 #define ALT_PINMUX_SHARED_3V_IO_Q4_4_SEL_CLR_MSK 0xfffffff0
5074 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_4_SEL register field. */
5075 #define ALT_PINMUX_SHARED_3V_IO_Q4_4_SEL_RESET 0xf
5076 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_4_SEL field value from a register. */
5077 #define ALT_PINMUX_SHARED_3V_IO_Q4_4_SEL_GET(value) (((value) & 0x0000000f) >> 0)
5078 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_4_SEL register field value suitable for setting the register. */
5079 #define ALT_PINMUX_SHARED_3V_IO_Q4_4_SEL_SET(value) (((value) << 0) & 0x0000000f)
5080 
5081 /*
5082  * Field : Reserved
5083  *
5084  * Reserved
5085  *
5086  * Field Access Macros:
5087  *
5088  */
5089 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_4_RSVD register field. */
5090 #define ALT_PINMUX_SHARED_3V_IO_Q4_4_RSVD_LSB 4
5091 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_4_RSVD register field. */
5092 #define ALT_PINMUX_SHARED_3V_IO_Q4_4_RSVD_MSB 31
5093 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_4_RSVD register field. */
5094 #define ALT_PINMUX_SHARED_3V_IO_Q4_4_RSVD_WIDTH 28
5095 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_4_RSVD register field value. */
5096 #define ALT_PINMUX_SHARED_3V_IO_Q4_4_RSVD_SET_MSK 0xfffffff0
5097 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_4_RSVD register field value. */
5098 #define ALT_PINMUX_SHARED_3V_IO_Q4_4_RSVD_CLR_MSK 0x0000000f
5099 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_4_RSVD register field. */
5100 #define ALT_PINMUX_SHARED_3V_IO_Q4_4_RSVD_RESET 0x0
5101 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_4_RSVD field value from a register. */
5102 #define ALT_PINMUX_SHARED_3V_IO_Q4_4_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
5103 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_4_RSVD register field value suitable for setting the register. */
5104 #define ALT_PINMUX_SHARED_3V_IO_Q4_4_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
5105 
5106 #ifndef __ASSEMBLY__
5107 /*
5108  * WARNING: The C register and register group struct declarations are provided for
5109  * convenience and illustrative purposes. They should, however, be used with
5110  * caution as the C language standard provides no guarantees about the alignment or
5111  * atomicity of device memory accesses. The recommended practice for writing
5112  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5113  * alt_write_word() functions.
5114  *
5115  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_4.
5116  */
5117 struct ALT_PINMUX_SHARED_3V_IO_Q4_4_s
5118 {
5119  uint32_t sel : 4; /* Shared IO48 Q4 4 Mux Selection Field */
5120  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q4_4_RSVD */
5121 };
5122 
5123 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_4. */
5124 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q4_4_s ALT_PINMUX_SHARED_3V_IO_Q4_4_t;
5125 #endif /* __ASSEMBLY__ */
5126 
5127 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_4 register. */
5128 #define ALT_PINMUX_SHARED_3V_IO_Q4_4_RESET 0x0000000f
5129 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q4_4 register from the beginning of the component. */
5130 #define ALT_PINMUX_SHARED_3V_IO_Q4_4_OFST 0x9c
5131 
5132 /*
5133  * Register : Shared IO 48 Q4 5 Mux Selection Register - pinmux_shared_io_q4_5
5134  *
5135  * This register is used to control the peripherals connected to shared IO48 pin Q4
5136  * 5
5137  *
5138  * Only reset by a cold reset (ignores warm reset).
5139  *
5140  * NOTE: These registers should not be modified after IO configuration.There is no
5141  * support for dynamically changing the Pin Mux selections.
5142  *
5143  * Register Layout
5144  *
5145  * Bits | Access | Reset | Description
5146  * :-------|:-------|:------|:-------------------------------------
5147  * [3:0] | RW | 0xf | Shared IO48 Q4 5 Mux Selection Field
5148  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q4_5_RSVD
5149  *
5150  */
5151 /*
5152  * Field : Shared IO48 Q4 5 Mux Selection Field - sel
5153  *
5154  * Select peripheral signals connected shared IO48 Q4 5
5155  *
5156  * 0000 (0) Pin is connected to Peripheral signal not applicable
5157  *
5158  * 0001 (1) Pin is connected to Peripheral signal not applicable
5159  *
5160  * 0010 (2) Pin is connected to Peripheral signal not applicable
5161  *
5162  * 0011 (3) Pin is connected to Peripheral signal not applicable
5163  *
5164  * 0100 (4) Pin is connected to Peripheral signal sdmmc.data2
5165  *
5166  * 0101 (5) Pin is connected to Peripheral signal not applicable
5167  *
5168  * 0110 (6) Pin is connected to Peripheral signal not applicable
5169  *
5170  * 0111 (7) Pin is connected to Peripheral signal not applicable
5171  *
5172  * 1000 (8) Pin is connected to Peripheral signal emac2.txd0
5173  *
5174  * 1001 (9) Pin is connected to Peripheral signal not applicable
5175  *
5176  * 1010 (10) Pin is connected to Peripheral signal not applicable
5177  *
5178  * 1011 (11) Pin is connected to Peripheral signal not applicable
5179  *
5180  * 1100 (12) Pin is connected to Peripheral signal qspi.ss2
5181  *
5182  * 1101 (13) Pin is connected to Peripheral signal uart1.cts_n
5183  *
5184  * 1110 (14) Pin is connected to Peripheral signal nand.adq8
5185  *
5186  * 1111 (15) Pin is connected to Peripheral signal gpio1.io16
5187  *
5188  * Field Access Macros:
5189  *
5190  */
5191 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_5_SEL register field. */
5192 #define ALT_PINMUX_SHARED_3V_IO_Q4_5_SEL_LSB 0
5193 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_5_SEL register field. */
5194 #define ALT_PINMUX_SHARED_3V_IO_Q4_5_SEL_MSB 3
5195 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_5_SEL register field. */
5196 #define ALT_PINMUX_SHARED_3V_IO_Q4_5_SEL_WIDTH 4
5197 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_5_SEL register field value. */
5198 #define ALT_PINMUX_SHARED_3V_IO_Q4_5_SEL_SET_MSK 0x0000000f
5199 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_5_SEL register field value. */
5200 #define ALT_PINMUX_SHARED_3V_IO_Q4_5_SEL_CLR_MSK 0xfffffff0
5201 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_5_SEL register field. */
5202 #define ALT_PINMUX_SHARED_3V_IO_Q4_5_SEL_RESET 0xf
5203 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_5_SEL field value from a register. */
5204 #define ALT_PINMUX_SHARED_3V_IO_Q4_5_SEL_GET(value) (((value) & 0x0000000f) >> 0)
5205 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_5_SEL register field value suitable for setting the register. */
5206 #define ALT_PINMUX_SHARED_3V_IO_Q4_5_SEL_SET(value) (((value) << 0) & 0x0000000f)
5207 
5208 /*
5209  * Field : Reserved
5210  *
5211  * Reserved
5212  *
5213  * Field Access Macros:
5214  *
5215  */
5216 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_5_RSVD register field. */
5217 #define ALT_PINMUX_SHARED_3V_IO_Q4_5_RSVD_LSB 4
5218 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_5_RSVD register field. */
5219 #define ALT_PINMUX_SHARED_3V_IO_Q4_5_RSVD_MSB 31
5220 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_5_RSVD register field. */
5221 #define ALT_PINMUX_SHARED_3V_IO_Q4_5_RSVD_WIDTH 28
5222 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_5_RSVD register field value. */
5223 #define ALT_PINMUX_SHARED_3V_IO_Q4_5_RSVD_SET_MSK 0xfffffff0
5224 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_5_RSVD register field value. */
5225 #define ALT_PINMUX_SHARED_3V_IO_Q4_5_RSVD_CLR_MSK 0x0000000f
5226 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_5_RSVD register field. */
5227 #define ALT_PINMUX_SHARED_3V_IO_Q4_5_RSVD_RESET 0x0
5228 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_5_RSVD field value from a register. */
5229 #define ALT_PINMUX_SHARED_3V_IO_Q4_5_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
5230 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_5_RSVD register field value suitable for setting the register. */
5231 #define ALT_PINMUX_SHARED_3V_IO_Q4_5_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
5232 
5233 #ifndef __ASSEMBLY__
5234 /*
5235  * WARNING: The C register and register group struct declarations are provided for
5236  * convenience and illustrative purposes. They should, however, be used with
5237  * caution as the C language standard provides no guarantees about the alignment or
5238  * atomicity of device memory accesses. The recommended practice for writing
5239  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5240  * alt_write_word() functions.
5241  *
5242  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_5.
5243  */
5244 struct ALT_PINMUX_SHARED_3V_IO_Q4_5_s
5245 {
5246  uint32_t sel : 4; /* Shared IO48 Q4 5 Mux Selection Field */
5247  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q4_5_RSVD */
5248 };
5249 
5250 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_5. */
5251 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q4_5_s ALT_PINMUX_SHARED_3V_IO_Q4_5_t;
5252 #endif /* __ASSEMBLY__ */
5253 
5254 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_5 register. */
5255 #define ALT_PINMUX_SHARED_3V_IO_Q4_5_RESET 0x0000000f
5256 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q4_5 register from the beginning of the component. */
5257 #define ALT_PINMUX_SHARED_3V_IO_Q4_5_OFST 0xa0
5258 
5259 /*
5260  * Register : Shared IO 48 Q4 6 Mux Selection Register - pinmux_shared_io_q4_6
5261  *
5262  * This register is used to control the peripherals connected to shared IO48 pin Q4
5263  * 6
5264  *
5265  * Only reset by a cold reset (ignores warm reset).
5266  *
5267  * NOTE: These registers should not be modified after IO configuration.There is no
5268  * support for dynamically changing the Pin Mux selections.
5269  *
5270  * Register Layout
5271  *
5272  * Bits | Access | Reset | Description
5273  * :-------|:-------|:------|:-------------------------------------
5274  * [3:0] | RW | 0xf | Shared IO48 Q4 6 Mux Selection Field
5275  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q4_6_RSVD
5276  *
5277  */
5278 /*
5279  * Field : Shared IO48 Q4 6 Mux Selection Field - sel
5280  *
5281  * Select peripheral signals connected shared IO48 Q4 6
5282  *
5283  * 0000 (0) Pin is connected to Peripheral signal not applicable
5284  *
5285  * 0001 (1) Pin is connected to Peripheral signal not applicable
5286  *
5287  * 0010 (2) Pin is connected to Peripheral signal not applicable
5288  *
5289  * 0011 (3) Pin is connected to Peripheral signal spim0.ss1_n
5290  *
5291  * 0100 (4) Pin is connected to Peripheral signal sdmmc.data3
5292  *
5293  * 0101 (5) Pin is connected to Peripheral signal not applicable
5294  *
5295  * 0110 (6) Pin is connected to Peripheral signal not applicable
5296  *
5297  * 0111 (7) Pin is connected to Peripheral signal not applicable
5298  *
5299  * 1000 (8) Pin is connected to Peripheral signal emac2.txd1
5300  *
5301  * 1001 (9) Pin is connected to Peripheral signal not applicable
5302  *
5303  * 1010 (10) Pin is connected to Peripheral signal not applicable
5304  *
5305  * 1011 (11) Pin is connected to Peripheral signal not applicable
5306  *
5307  * 1100 (12) Pin is connected to Peripheral signal qspi.ss3
5308  *
5309  * 1101 (13) Pin is connected to Peripheral signal uart1.rts_n
5310  *
5311  * 1110 (14) Pin is connected to Peripheral signal nand.adq9
5312  *
5313  * 1111 (15) Pin is connected to Peripheral signal gpio1.io17
5314  *
5315  * Field Access Macros:
5316  *
5317  */
5318 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_6_SEL register field. */
5319 #define ALT_PINMUX_SHARED_3V_IO_Q4_6_SEL_LSB 0
5320 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_6_SEL register field. */
5321 #define ALT_PINMUX_SHARED_3V_IO_Q4_6_SEL_MSB 3
5322 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_6_SEL register field. */
5323 #define ALT_PINMUX_SHARED_3V_IO_Q4_6_SEL_WIDTH 4
5324 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_6_SEL register field value. */
5325 #define ALT_PINMUX_SHARED_3V_IO_Q4_6_SEL_SET_MSK 0x0000000f
5326 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_6_SEL register field value. */
5327 #define ALT_PINMUX_SHARED_3V_IO_Q4_6_SEL_CLR_MSK 0xfffffff0
5328 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_6_SEL register field. */
5329 #define ALT_PINMUX_SHARED_3V_IO_Q4_6_SEL_RESET 0xf
5330 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_6_SEL field value from a register. */
5331 #define ALT_PINMUX_SHARED_3V_IO_Q4_6_SEL_GET(value) (((value) & 0x0000000f) >> 0)
5332 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_6_SEL register field value suitable for setting the register. */
5333 #define ALT_PINMUX_SHARED_3V_IO_Q4_6_SEL_SET(value) (((value) << 0) & 0x0000000f)
5334 
5335 /*
5336  * Field : Reserved
5337  *
5338  * Reserved
5339  *
5340  * Field Access Macros:
5341  *
5342  */
5343 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_6_RSVD register field. */
5344 #define ALT_PINMUX_SHARED_3V_IO_Q4_6_RSVD_LSB 4
5345 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_6_RSVD register field. */
5346 #define ALT_PINMUX_SHARED_3V_IO_Q4_6_RSVD_MSB 31
5347 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_6_RSVD register field. */
5348 #define ALT_PINMUX_SHARED_3V_IO_Q4_6_RSVD_WIDTH 28
5349 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_6_RSVD register field value. */
5350 #define ALT_PINMUX_SHARED_3V_IO_Q4_6_RSVD_SET_MSK 0xfffffff0
5351 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_6_RSVD register field value. */
5352 #define ALT_PINMUX_SHARED_3V_IO_Q4_6_RSVD_CLR_MSK 0x0000000f
5353 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_6_RSVD register field. */
5354 #define ALT_PINMUX_SHARED_3V_IO_Q4_6_RSVD_RESET 0x0
5355 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_6_RSVD field value from a register. */
5356 #define ALT_PINMUX_SHARED_3V_IO_Q4_6_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
5357 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_6_RSVD register field value suitable for setting the register. */
5358 #define ALT_PINMUX_SHARED_3V_IO_Q4_6_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
5359 
5360 #ifndef __ASSEMBLY__
5361 /*
5362  * WARNING: The C register and register group struct declarations are provided for
5363  * convenience and illustrative purposes. They should, however, be used with
5364  * caution as the C language standard provides no guarantees about the alignment or
5365  * atomicity of device memory accesses. The recommended practice for writing
5366  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5367  * alt_write_word() functions.
5368  *
5369  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_6.
5370  */
5371 struct ALT_PINMUX_SHARED_3V_IO_Q4_6_s
5372 {
5373  uint32_t sel : 4; /* Shared IO48 Q4 6 Mux Selection Field */
5374  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q4_6_RSVD */
5375 };
5376 
5377 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_6. */
5378 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q4_6_s ALT_PINMUX_SHARED_3V_IO_Q4_6_t;
5379 #endif /* __ASSEMBLY__ */
5380 
5381 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_6 register. */
5382 #define ALT_PINMUX_SHARED_3V_IO_Q4_6_RESET 0x0000000f
5383 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q4_6 register from the beginning of the component. */
5384 #define ALT_PINMUX_SHARED_3V_IO_Q4_6_OFST 0xa4
5385 
5386 /*
5387  * Register : Shared IO 48 Q4 7 Mux Selection Register - pinmux_shared_io_q4_7
5388  *
5389  * This register is used to control the peripherals connected to shared IO48 pin Q4
5390  * 7
5391  *
5392  * Only reset by a cold reset (ignores warm reset).
5393  *
5394  * NOTE: These registers should not be modified after IO configuration.There is no
5395  * support for dynamically changing the Pin Mux selections.
5396  *
5397  * Register Layout
5398  *
5399  * Bits | Access | Reset | Description
5400  * :-------|:-------|:------|:-------------------------------------
5401  * [3:0] | RW | 0xf | Shared IO48 Q4 7 Mux Selection Field
5402  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q4_7_RSVD
5403  *
5404  */
5405 /*
5406  * Field : Shared IO48 Q4 7 Mux Selection Field - sel
5407  *
5408  * Select peripheral signals connected shared IO48 Q4 7
5409  *
5410  * 0000 (0) Pin is connected to Peripheral signal i2c_emac1.sda
5411  *
5412  * 0001 (1) Pin is connected to Peripheral signal emac1.mdio
5413  *
5414  * 0010 (2) Pin is connected to Peripheral signal not applicable
5415  *
5416  * 0011 (3) Pin is connected to Peripheral signal spim0.miso
5417  *
5418  * 0100 (4) Pin is connected to Peripheral signal sdmmc.data4
5419  *
5420  * 0101 (5) Pin is connected to Peripheral signal not applicable
5421  *
5422  * 0110 (6) Pin is connected to Peripheral signal not applicable
5423  *
5424  * 0111 (7) Pin is connected to Peripheral signal not applicable
5425  *
5426  * 1000 (8) Pin is connected to Peripheral signal emac2.rxd0
5427  *
5428  * 1001 (9) Pin is connected to Peripheral signal not applicable
5429  *
5430  * 1010 (10) Pin is connected to Peripheral signal not applicable
5431  *
5432  * 1011 (11) Pin is connected to Peripheral signal not applicable
5433  *
5434  * 1100 (12) Pin is connected to Peripheral signal not applicable
5435  *
5436  * 1101 (13) Pin is connected to Peripheral signal not applicable
5437  *
5438  * 1110 (14) Pin is connected to Peripheral signal nand.adq10
5439  *
5440  * 1111 (15) Pin is connected to Peripheral signal gpio1.io18
5441  *
5442  * Field Access Macros:
5443  *
5444  */
5445 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_7_SEL register field. */
5446 #define ALT_PINMUX_SHARED_3V_IO_Q4_7_SEL_LSB 0
5447 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_7_SEL register field. */
5448 #define ALT_PINMUX_SHARED_3V_IO_Q4_7_SEL_MSB 3
5449 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_7_SEL register field. */
5450 #define ALT_PINMUX_SHARED_3V_IO_Q4_7_SEL_WIDTH 4
5451 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_7_SEL register field value. */
5452 #define ALT_PINMUX_SHARED_3V_IO_Q4_7_SEL_SET_MSK 0x0000000f
5453 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_7_SEL register field value. */
5454 #define ALT_PINMUX_SHARED_3V_IO_Q4_7_SEL_CLR_MSK 0xfffffff0
5455 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_7_SEL register field. */
5456 #define ALT_PINMUX_SHARED_3V_IO_Q4_7_SEL_RESET 0xf
5457 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_7_SEL field value from a register. */
5458 #define ALT_PINMUX_SHARED_3V_IO_Q4_7_SEL_GET(value) (((value) & 0x0000000f) >> 0)
5459 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_7_SEL register field value suitable for setting the register. */
5460 #define ALT_PINMUX_SHARED_3V_IO_Q4_7_SEL_SET(value) (((value) << 0) & 0x0000000f)
5461 
5462 /*
5463  * Field : Reserved
5464  *
5465  * Reserved
5466  *
5467  * Field Access Macros:
5468  *
5469  */
5470 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_7_RSVD register field. */
5471 #define ALT_PINMUX_SHARED_3V_IO_Q4_7_RSVD_LSB 4
5472 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_7_RSVD register field. */
5473 #define ALT_PINMUX_SHARED_3V_IO_Q4_7_RSVD_MSB 31
5474 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_7_RSVD register field. */
5475 #define ALT_PINMUX_SHARED_3V_IO_Q4_7_RSVD_WIDTH 28
5476 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_7_RSVD register field value. */
5477 #define ALT_PINMUX_SHARED_3V_IO_Q4_7_RSVD_SET_MSK 0xfffffff0
5478 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_7_RSVD register field value. */
5479 #define ALT_PINMUX_SHARED_3V_IO_Q4_7_RSVD_CLR_MSK 0x0000000f
5480 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_7_RSVD register field. */
5481 #define ALT_PINMUX_SHARED_3V_IO_Q4_7_RSVD_RESET 0x0
5482 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_7_RSVD field value from a register. */
5483 #define ALT_PINMUX_SHARED_3V_IO_Q4_7_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
5484 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_7_RSVD register field value suitable for setting the register. */
5485 #define ALT_PINMUX_SHARED_3V_IO_Q4_7_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
5486 
5487 #ifndef __ASSEMBLY__
5488 /*
5489  * WARNING: The C register and register group struct declarations are provided for
5490  * convenience and illustrative purposes. They should, however, be used with
5491  * caution as the C language standard provides no guarantees about the alignment or
5492  * atomicity of device memory accesses. The recommended practice for writing
5493  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5494  * alt_write_word() functions.
5495  *
5496  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_7.
5497  */
5498 struct ALT_PINMUX_SHARED_3V_IO_Q4_7_s
5499 {
5500  uint32_t sel : 4; /* Shared IO48 Q4 7 Mux Selection Field */
5501  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q4_7_RSVD */
5502 };
5503 
5504 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_7. */
5505 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q4_7_s ALT_PINMUX_SHARED_3V_IO_Q4_7_t;
5506 #endif /* __ASSEMBLY__ */
5507 
5508 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_7 register. */
5509 #define ALT_PINMUX_SHARED_3V_IO_Q4_7_RESET 0x0000000f
5510 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q4_7 register from the beginning of the component. */
5511 #define ALT_PINMUX_SHARED_3V_IO_Q4_7_OFST 0xa8
5512 
5513 /*
5514  * Register : Shared IO 48 Q4 8 Mux Selection Register - pinmux_shared_io_q4_8
5515  *
5516  * This register is used to control the peripherals connected to shared IO48 pin Q4
5517  * 8
5518  *
5519  * Only reset by a cold reset (ignores warm reset).
5520  *
5521  * NOTE: These registers should not be modified after IO configuration.There is no
5522  * support for dynamically changing the Pin Mux selections.
5523  *
5524  * Register Layout
5525  *
5526  * Bits | Access | Reset | Description
5527  * :-------|:-------|:------|:-------------------------------------
5528  * [3:0] | RW | 0xf | Shared IO48 Q4 8 Mux Selection Field
5529  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q4_8_RSVD
5530  *
5531  */
5532 /*
5533  * Field : Shared IO48 Q4 8 Mux Selection Field - sel
5534  *
5535  * Select peripheral signals connected shared IO48 Q4 8
5536  *
5537  * 0000 (0) Pin is connected to Peripheral signal i2c_emac1.scl
5538  *
5539  * 0001 (1) Pin is connected to Peripheral signal emac1.mdc
5540  *
5541  * 0010 (2) Pin is connected to Peripheral signal not applicable
5542  *
5543  * 0011 (3) Pin is connected to Peripheral signal spim0.ss0_n
5544  *
5545  * 0100 (4) Pin is connected to Peripheral signal sdmmc.data5
5546  *
5547  * 0101 (5) Pin is connected to Peripheral signal not applicable
5548  *
5549  * 0110 (6) Pin is connected to Peripheral signal not applicable
5550  *
5551  * 0111 (7) Pin is connected to Peripheral signal not applicable
5552  *
5553  * 1000 (8) Pin is connected to Peripheral signal emac2.rxd1
5554  *
5555  * 1001 (9) Pin is connected to Peripheral signal not applicable
5556  *
5557  * 1010 (10) Pin is connected to Peripheral signal not applicable
5558  *
5559  * 1011 (11) Pin is connected to Peripheral signal not applicable
5560  *
5561  * 1100 (12) Pin is connected to Peripheral signal trace.clk
5562  *
5563  * 1101 (13) Pin is connected to Peripheral signal not applicable
5564  *
5565  * 1110 (14) Pin is connected to Peripheral signal nand.adq11
5566  *
5567  * 1111 (15) Pin is connected to Peripheral signal gpio1.io19
5568  *
5569  * Field Access Macros:
5570  *
5571  */
5572 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_8_SEL register field. */
5573 #define ALT_PINMUX_SHARED_3V_IO_Q4_8_SEL_LSB 0
5574 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_8_SEL register field. */
5575 #define ALT_PINMUX_SHARED_3V_IO_Q4_8_SEL_MSB 3
5576 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_8_SEL register field. */
5577 #define ALT_PINMUX_SHARED_3V_IO_Q4_8_SEL_WIDTH 4
5578 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_8_SEL register field value. */
5579 #define ALT_PINMUX_SHARED_3V_IO_Q4_8_SEL_SET_MSK 0x0000000f
5580 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_8_SEL register field value. */
5581 #define ALT_PINMUX_SHARED_3V_IO_Q4_8_SEL_CLR_MSK 0xfffffff0
5582 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_8_SEL register field. */
5583 #define ALT_PINMUX_SHARED_3V_IO_Q4_8_SEL_RESET 0xf
5584 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_8_SEL field value from a register. */
5585 #define ALT_PINMUX_SHARED_3V_IO_Q4_8_SEL_GET(value) (((value) & 0x0000000f) >> 0)
5586 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_8_SEL register field value suitable for setting the register. */
5587 #define ALT_PINMUX_SHARED_3V_IO_Q4_8_SEL_SET(value) (((value) << 0) & 0x0000000f)
5588 
5589 /*
5590  * Field : Reserved
5591  *
5592  * Reserved
5593  *
5594  * Field Access Macros:
5595  *
5596  */
5597 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_8_RSVD register field. */
5598 #define ALT_PINMUX_SHARED_3V_IO_Q4_8_RSVD_LSB 4
5599 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_8_RSVD register field. */
5600 #define ALT_PINMUX_SHARED_3V_IO_Q4_8_RSVD_MSB 31
5601 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_8_RSVD register field. */
5602 #define ALT_PINMUX_SHARED_3V_IO_Q4_8_RSVD_WIDTH 28
5603 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_8_RSVD register field value. */
5604 #define ALT_PINMUX_SHARED_3V_IO_Q4_8_RSVD_SET_MSK 0xfffffff0
5605 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_8_RSVD register field value. */
5606 #define ALT_PINMUX_SHARED_3V_IO_Q4_8_RSVD_CLR_MSK 0x0000000f
5607 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_8_RSVD register field. */
5608 #define ALT_PINMUX_SHARED_3V_IO_Q4_8_RSVD_RESET 0x0
5609 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_8_RSVD field value from a register. */
5610 #define ALT_PINMUX_SHARED_3V_IO_Q4_8_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
5611 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_8_RSVD register field value suitable for setting the register. */
5612 #define ALT_PINMUX_SHARED_3V_IO_Q4_8_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
5613 
5614 #ifndef __ASSEMBLY__
5615 /*
5616  * WARNING: The C register and register group struct declarations are provided for
5617  * convenience and illustrative purposes. They should, however, be used with
5618  * caution as the C language standard provides no guarantees about the alignment or
5619  * atomicity of device memory accesses. The recommended practice for writing
5620  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5621  * alt_write_word() functions.
5622  *
5623  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_8.
5624  */
5625 struct ALT_PINMUX_SHARED_3V_IO_Q4_8_s
5626 {
5627  uint32_t sel : 4; /* Shared IO48 Q4 8 Mux Selection Field */
5628  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q4_8_RSVD */
5629 };
5630 
5631 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_8. */
5632 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q4_8_s ALT_PINMUX_SHARED_3V_IO_Q4_8_t;
5633 #endif /* __ASSEMBLY__ */
5634 
5635 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_8 register. */
5636 #define ALT_PINMUX_SHARED_3V_IO_Q4_8_RESET 0x0000000f
5637 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q4_8 register from the beginning of the component. */
5638 #define ALT_PINMUX_SHARED_3V_IO_Q4_8_OFST 0xac
5639 
5640 /*
5641  * Register : Shared IO 48 Q4 9 Mux Selection Register - pinmux_shared_io_q4_9
5642  *
5643  * This register is used to control the peripherals connected to shared IO48 pin Q4
5644  * 9
5645  *
5646  * Only reset by a cold reset (ignores warm reset).
5647  *
5648  * NOTE: These registers should not be modified after IO configuration.There is no
5649  * support for dynamically changing the Pin Mux selections.
5650  *
5651  * Register Layout
5652  *
5653  * Bits | Access | Reset | Description
5654  * :-------|:-------|:------|:-------------------------------------
5655  * [3:0] | RW | 0xf | Shared IO48 Q4 9 Mux Selection Field
5656  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q4_9_RSVD
5657  *
5658  */
5659 /*
5660  * Field : Shared IO48 Q4 9 Mux Selection Field - sel
5661  *
5662  * Select peripheral signals connected shared IO48 Q4 9
5663  *
5664  * 0000 (0) Pin is connected to Peripheral signal i2c_emac2.sda
5665  *
5666  * 0001 (1) Pin is connected to Peripheral signal not applicable
5667  *
5668  * 0010 (2) Pin is connected to Peripheral signal spis1.clk
5669  *
5670  * 0011 (3) Pin is connected to Peripheral signal spim0.clk
5671  *
5672  * 0100 (4) Pin is connected to Peripheral signal sdmmc.data6
5673  *
5674  * 0101 (5) Pin is connected to Peripheral signal not applicable
5675  *
5676  * 0110 (6) Pin is connected to Peripheral signal not applicable
5677  *
5678  * 0111 (7) Pin is connected to Peripheral signal not applicable
5679  *
5680  * 1000 (8) Pin is connected to Peripheral signal emac2.txd2
5681  *
5682  * 1001 (9) Pin is connected to Peripheral signal not applicable
5683  *
5684  * 1010 (10) Pin is connected to Peripheral signal not applicable
5685  *
5686  * 1011 (11) Pin is connected to Peripheral signal not applicable
5687  *
5688  * 1100 (12) Pin is connected to Peripheral signal trace.d0
5689  *
5690  * 1101 (13) Pin is connected to Peripheral signal not applicable
5691  *
5692  * 1110 (14) Pin is connected to Peripheral signal nand.adq12
5693  *
5694  * 1111 (15) Pin is connected to Peripheral signal gpio1.io20
5695  *
5696  * Field Access Macros:
5697  *
5698  */
5699 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_9_SEL register field. */
5700 #define ALT_PINMUX_SHARED_3V_IO_Q4_9_SEL_LSB 0
5701 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_9_SEL register field. */
5702 #define ALT_PINMUX_SHARED_3V_IO_Q4_9_SEL_MSB 3
5703 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_9_SEL register field. */
5704 #define ALT_PINMUX_SHARED_3V_IO_Q4_9_SEL_WIDTH 4
5705 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_9_SEL register field value. */
5706 #define ALT_PINMUX_SHARED_3V_IO_Q4_9_SEL_SET_MSK 0x0000000f
5707 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_9_SEL register field value. */
5708 #define ALT_PINMUX_SHARED_3V_IO_Q4_9_SEL_CLR_MSK 0xfffffff0
5709 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_9_SEL register field. */
5710 #define ALT_PINMUX_SHARED_3V_IO_Q4_9_SEL_RESET 0xf
5711 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_9_SEL field value from a register. */
5712 #define ALT_PINMUX_SHARED_3V_IO_Q4_9_SEL_GET(value) (((value) & 0x0000000f) >> 0)
5713 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_9_SEL register field value suitable for setting the register. */
5714 #define ALT_PINMUX_SHARED_3V_IO_Q4_9_SEL_SET(value) (((value) << 0) & 0x0000000f)
5715 
5716 /*
5717  * Field : Reserved
5718  *
5719  * Reserved
5720  *
5721  * Field Access Macros:
5722  *
5723  */
5724 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_9_RSVD register field. */
5725 #define ALT_PINMUX_SHARED_3V_IO_Q4_9_RSVD_LSB 4
5726 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_9_RSVD register field. */
5727 #define ALT_PINMUX_SHARED_3V_IO_Q4_9_RSVD_MSB 31
5728 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_9_RSVD register field. */
5729 #define ALT_PINMUX_SHARED_3V_IO_Q4_9_RSVD_WIDTH 28
5730 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_9_RSVD register field value. */
5731 #define ALT_PINMUX_SHARED_3V_IO_Q4_9_RSVD_SET_MSK 0xfffffff0
5732 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_9_RSVD register field value. */
5733 #define ALT_PINMUX_SHARED_3V_IO_Q4_9_RSVD_CLR_MSK 0x0000000f
5734 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_9_RSVD register field. */
5735 #define ALT_PINMUX_SHARED_3V_IO_Q4_9_RSVD_RESET 0x0
5736 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_9_RSVD field value from a register. */
5737 #define ALT_PINMUX_SHARED_3V_IO_Q4_9_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
5738 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_9_RSVD register field value suitable for setting the register. */
5739 #define ALT_PINMUX_SHARED_3V_IO_Q4_9_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
5740 
5741 #ifndef __ASSEMBLY__
5742 /*
5743  * WARNING: The C register and register group struct declarations are provided for
5744  * convenience and illustrative purposes. They should, however, be used with
5745  * caution as the C language standard provides no guarantees about the alignment or
5746  * atomicity of device memory accesses. The recommended practice for writing
5747  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5748  * alt_write_word() functions.
5749  *
5750  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_9.
5751  */
5752 struct ALT_PINMUX_SHARED_3V_IO_Q4_9_s
5753 {
5754  uint32_t sel : 4; /* Shared IO48 Q4 9 Mux Selection Field */
5755  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q4_9_RSVD */
5756 };
5757 
5758 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_9. */
5759 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q4_9_s ALT_PINMUX_SHARED_3V_IO_Q4_9_t;
5760 #endif /* __ASSEMBLY__ */
5761 
5762 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_9 register. */
5763 #define ALT_PINMUX_SHARED_3V_IO_Q4_9_RESET 0x0000000f
5764 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q4_9 register from the beginning of the component. */
5765 #define ALT_PINMUX_SHARED_3V_IO_Q4_9_OFST 0xb0
5766 
5767 /*
5768  * Register : Shared IO 48 Q4 10 Mux Selection Register - pinmux_shared_io_q4_10
5769  *
5770  * This register is used to control the peripherals connected to shared IO48 pin Q4
5771  * 10
5772  *
5773  * Only reset by a cold reset (ignores warm reset).
5774  *
5775  * NOTE: These registers should not be modified after IO configuration.There is no
5776  * support for dynamically changing the Pin Mux selections.
5777  *
5778  * Register Layout
5779  *
5780  * Bits | Access | Reset | Description
5781  * :-------|:-------|:------|:--------------------------------------
5782  * [3:0] | RW | 0xf | Shared IO48 Q4 10 Mux Selection Field
5783  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q4_10_RSVD
5784  *
5785  */
5786 /*
5787  * Field : Shared IO48 Q4 10 Mux Selection Field - sel
5788  *
5789  * Select peripheral signals connected shared IO48 Q4 10
5790  *
5791  * 0000 (0) Pin is connected to Peripheral signal i2c_emac2.scl
5792  *
5793  * 0001 (1) Pin is connected to Peripheral signal not applicable
5794  *
5795  * 0010 (2) Pin is connected to Peripheral signal spis1.mosi
5796  *
5797  * 0011 (3) Pin is connected to Peripheral signal spim0.mosi
5798  *
5799  * 0100 (4) Pin is connected to Peripheral signal sdmmc.data7
5800  *
5801  * 0101 (5) Pin is connected to Peripheral signal not applicable
5802  *
5803  * 0110 (6) Pin is connected to Peripheral signal not applicable
5804  *
5805  * 0111 (7) Pin is connected to Peripheral signal not applicable
5806  *
5807  * 1000 (8) Pin is connected to Peripheral signal emac2.txd3
5808  *
5809  * 1001 (9) Pin is connected to Peripheral signal not applicable
5810  *
5811  * 1010 (10) Pin is connected to Peripheral signal not applicable
5812  *
5813  * 1011 (11) Pin is connected to Peripheral signal not applicable
5814  *
5815  * 1100 (12) Pin is connected to Peripheral signal trace.d1
5816  *
5817  * 1101 (13) Pin is connected to Peripheral signal not applicable
5818  *
5819  * 1110 (14) Pin is connected to Peripheral signal nand.adq13
5820  *
5821  * 1111 (15) Pin is connected to Peripheral signal gpio1.io21
5822  *
5823  * Field Access Macros:
5824  *
5825  */
5826 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_10_SEL register field. */
5827 #define ALT_PINMUX_SHARED_3V_IO_Q4_10_SEL_LSB 0
5828 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_10_SEL register field. */
5829 #define ALT_PINMUX_SHARED_3V_IO_Q4_10_SEL_MSB 3
5830 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_10_SEL register field. */
5831 #define ALT_PINMUX_SHARED_3V_IO_Q4_10_SEL_WIDTH 4
5832 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_10_SEL register field value. */
5833 #define ALT_PINMUX_SHARED_3V_IO_Q4_10_SEL_SET_MSK 0x0000000f
5834 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_10_SEL register field value. */
5835 #define ALT_PINMUX_SHARED_3V_IO_Q4_10_SEL_CLR_MSK 0xfffffff0
5836 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_10_SEL register field. */
5837 #define ALT_PINMUX_SHARED_3V_IO_Q4_10_SEL_RESET 0xf
5838 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_10_SEL field value from a register. */
5839 #define ALT_PINMUX_SHARED_3V_IO_Q4_10_SEL_GET(value) (((value) & 0x0000000f) >> 0)
5840 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_10_SEL register field value suitable for setting the register. */
5841 #define ALT_PINMUX_SHARED_3V_IO_Q4_10_SEL_SET(value) (((value) << 0) & 0x0000000f)
5842 
5843 /*
5844  * Field : Reserved
5845  *
5846  * Reserved
5847  *
5848  * Field Access Macros:
5849  *
5850  */
5851 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_10_RSVD register field. */
5852 #define ALT_PINMUX_SHARED_3V_IO_Q4_10_RSVD_LSB 4
5853 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_10_RSVD register field. */
5854 #define ALT_PINMUX_SHARED_3V_IO_Q4_10_RSVD_MSB 31
5855 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_10_RSVD register field. */
5856 #define ALT_PINMUX_SHARED_3V_IO_Q4_10_RSVD_WIDTH 28
5857 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_10_RSVD register field value. */
5858 #define ALT_PINMUX_SHARED_3V_IO_Q4_10_RSVD_SET_MSK 0xfffffff0
5859 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_10_RSVD register field value. */
5860 #define ALT_PINMUX_SHARED_3V_IO_Q4_10_RSVD_CLR_MSK 0x0000000f
5861 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_10_RSVD register field. */
5862 #define ALT_PINMUX_SHARED_3V_IO_Q4_10_RSVD_RESET 0x0
5863 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_10_RSVD field value from a register. */
5864 #define ALT_PINMUX_SHARED_3V_IO_Q4_10_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
5865 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_10_RSVD register field value suitable for setting the register. */
5866 #define ALT_PINMUX_SHARED_3V_IO_Q4_10_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
5867 
5868 #ifndef __ASSEMBLY__
5869 /*
5870  * WARNING: The C register and register group struct declarations are provided for
5871  * convenience and illustrative purposes. They should, however, be used with
5872  * caution as the C language standard provides no guarantees about the alignment or
5873  * atomicity of device memory accesses. The recommended practice for writing
5874  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5875  * alt_write_word() functions.
5876  *
5877  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_10.
5878  */
5879 struct ALT_PINMUX_SHARED_3V_IO_Q4_10_s
5880 {
5881  uint32_t sel : 4; /* Shared IO48 Q4 10 Mux Selection Field */
5882  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q4_10_RSVD */
5883 };
5884 
5885 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_10. */
5886 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q4_10_s ALT_PINMUX_SHARED_3V_IO_Q4_10_t;
5887 #endif /* __ASSEMBLY__ */
5888 
5889 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_10 register. */
5890 #define ALT_PINMUX_SHARED_3V_IO_Q4_10_RESET 0x0000000f
5891 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q4_10 register from the beginning of the component. */
5892 #define ALT_PINMUX_SHARED_3V_IO_Q4_10_OFST 0xb4
5893 
5894 /*
5895  * Register : Shared IO 48 Q4 11 Mux Selection Register - pinmux_shared_io_q4_11
5896  *
5897  * This register is used to control the peripherals connected to shared IO48 pin Q4
5898  * 11
5899  *
5900  * Only reset by a cold reset (ignores warm reset).
5901  *
5902  * NOTE: These registers should not be modified after IO configuration.There is no
5903  * support for dynamically changing the Pin Mux selections.
5904  *
5905  * Register Layout
5906  *
5907  * Bits | Access | Reset | Description
5908  * :-------|:-------|:------|:--------------------------------------
5909  * [3:0] | RW | 0xf | Shared IO48 Q4 11 Mux Selection Field
5910  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q4_11_RSVD
5911  *
5912  */
5913 /*
5914  * Field : Shared IO48 Q4 11 Mux Selection Field - sel
5915  *
5916  * Select peripheral signals connected shared IO48 Q4 11
5917  *
5918  * 0000 (0) Pin is connected to Peripheral signal i2c_emac0.sda
5919  *
5920  * 0001 (1) Pin is connected to Peripheral signal emac0.mdio
5921  *
5922  * 0010 (2) Pin is connected to Peripheral signal spis1.ss0_n
5923  *
5924  * 0011 (3) Pin is connected to Peripheral signal spim0.miso
5925  *
5926  * 0100 (4) Pin is connected to Peripheral signal not applicable
5927  *
5928  * 0101 (5) Pin is connected to Peripheral signal not applicable
5929  *
5930  * 0110 (6) Pin is connected to Peripheral signal not applicable
5931  *
5932  * 0111 (7) Pin is connected to Peripheral signal not applicable
5933  *
5934  * 1000 (8) Pin is connected to Peripheral signal emac2.rxd2
5935  *
5936  * 1001 (9) Pin is connected to Peripheral signal not applicable
5937  *
5938  * 1010 (10) Pin is connected to Peripheral signal not applicable
5939  *
5940  * 1011 (11) Pin is connected to Peripheral signal not applicable
5941  *
5942  * 1100 (12) Pin is connected to Peripheral signal trace.d2
5943  *
5944  * 1101 (13) Pin is connected to Peripheral signal not applicable
5945  *
5946  * 1110 (14) Pin is connected to Peripheral signal nand.adq14
5947  *
5948  * 1111 (15) Pin is connected to Peripheral signal gpio1.io22
5949  *
5950  * Field Access Macros:
5951  *
5952  */
5953 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_11_SEL register field. */
5954 #define ALT_PINMUX_SHARED_3V_IO_Q4_11_SEL_LSB 0
5955 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_11_SEL register field. */
5956 #define ALT_PINMUX_SHARED_3V_IO_Q4_11_SEL_MSB 3
5957 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_11_SEL register field. */
5958 #define ALT_PINMUX_SHARED_3V_IO_Q4_11_SEL_WIDTH 4
5959 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_11_SEL register field value. */
5960 #define ALT_PINMUX_SHARED_3V_IO_Q4_11_SEL_SET_MSK 0x0000000f
5961 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_11_SEL register field value. */
5962 #define ALT_PINMUX_SHARED_3V_IO_Q4_11_SEL_CLR_MSK 0xfffffff0
5963 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_11_SEL register field. */
5964 #define ALT_PINMUX_SHARED_3V_IO_Q4_11_SEL_RESET 0xf
5965 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_11_SEL field value from a register. */
5966 #define ALT_PINMUX_SHARED_3V_IO_Q4_11_SEL_GET(value) (((value) & 0x0000000f) >> 0)
5967 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_11_SEL register field value suitable for setting the register. */
5968 #define ALT_PINMUX_SHARED_3V_IO_Q4_11_SEL_SET(value) (((value) << 0) & 0x0000000f)
5969 
5970 /*
5971  * Field : Reserved
5972  *
5973  * Reserved
5974  *
5975  * Field Access Macros:
5976  *
5977  */
5978 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_11_RSVD register field. */
5979 #define ALT_PINMUX_SHARED_3V_IO_Q4_11_RSVD_LSB 4
5980 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_11_RSVD register field. */
5981 #define ALT_PINMUX_SHARED_3V_IO_Q4_11_RSVD_MSB 31
5982 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_11_RSVD register field. */
5983 #define ALT_PINMUX_SHARED_3V_IO_Q4_11_RSVD_WIDTH 28
5984 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_11_RSVD register field value. */
5985 #define ALT_PINMUX_SHARED_3V_IO_Q4_11_RSVD_SET_MSK 0xfffffff0
5986 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_11_RSVD register field value. */
5987 #define ALT_PINMUX_SHARED_3V_IO_Q4_11_RSVD_CLR_MSK 0x0000000f
5988 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_11_RSVD register field. */
5989 #define ALT_PINMUX_SHARED_3V_IO_Q4_11_RSVD_RESET 0x0
5990 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_11_RSVD field value from a register. */
5991 #define ALT_PINMUX_SHARED_3V_IO_Q4_11_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
5992 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_11_RSVD register field value suitable for setting the register. */
5993 #define ALT_PINMUX_SHARED_3V_IO_Q4_11_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
5994 
5995 #ifndef __ASSEMBLY__
5996 /*
5997  * WARNING: The C register and register group struct declarations are provided for
5998  * convenience and illustrative purposes. They should, however, be used with
5999  * caution as the C language standard provides no guarantees about the alignment or
6000  * atomicity of device memory accesses. The recommended practice for writing
6001  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6002  * alt_write_word() functions.
6003  *
6004  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_11.
6005  */
6006 struct ALT_PINMUX_SHARED_3V_IO_Q4_11_s
6007 {
6008  uint32_t sel : 4; /* Shared IO48 Q4 11 Mux Selection Field */
6009  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q4_11_RSVD */
6010 };
6011 
6012 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_11. */
6013 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q4_11_s ALT_PINMUX_SHARED_3V_IO_Q4_11_t;
6014 #endif /* __ASSEMBLY__ */
6015 
6016 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_11 register. */
6017 #define ALT_PINMUX_SHARED_3V_IO_Q4_11_RESET 0x0000000f
6018 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q4_11 register from the beginning of the component. */
6019 #define ALT_PINMUX_SHARED_3V_IO_Q4_11_OFST 0xb8
6020 
6021 /*
6022  * Register : Shared IO 48 Q4 12 Mux Selection Register - pinmux_shared_io_q4_12
6023  *
6024  * This register is used to control the peripherals connected to shared IO48 pin Q4
6025  * 12
6026  *
6027  * Only reset by a cold reset (ignores warm reset).
6028  *
6029  * NOTE: These registers should not be modified after IO configuration.There is no
6030  * support for dynamically changing the Pin Mux selections.
6031  *
6032  * Register Layout
6033  *
6034  * Bits | Access | Reset | Description
6035  * :-------|:-------|:------|:--------------------------------------
6036  * [3:0] | RW | 0xf | Shared IO48 Q4 12 Mux Selection Field
6037  * [31:4] | R | 0x0 | ALT_PINMUX_SHARED_3V_IO_Q4_12_RSVD
6038  *
6039  */
6040 /*
6041  * Field : Shared IO48 Q4 12 Mux Selection Field - sel
6042  *
6043  * Select peripheral signals connected shared IO48 Q4 12
6044  *
6045  * 0000 (0) Pin is connected to Peripheral signal i2c_emac0.scl
6046  *
6047  * 0001 (1) Pin is connected to Peripheral signal emac0.mdc
6048  *
6049  * 0010 (2) Pin is connected to Peripheral signal spis1.miso
6050  *
6051  * 0011 (3) Pin is connected to Peripheral signal spim0.ss0_n
6052  *
6053  * 0100 (4) Pin is connected to Peripheral signal not applicable
6054  *
6055  * 0101 (5) Pin is connected to Peripheral signal not applicable
6056  *
6057  * 0110 (6) Pin is connected to Peripheral signal not applicable
6058  *
6059  * 0111 (7) Pin is connected to Peripheral signal not applicable
6060  *
6061  * 1000 (8) Pin is connected to Peripheral signal emac2.rxd3
6062  *
6063  * 1001 (9) Pin is connected to Peripheral signal not applicable
6064  *
6065  * 1010 (10) Pin is connected to Peripheral signal not applicable
6066  *
6067  * 1011 (11) Pin is connected to Peripheral signal not applicable
6068  *
6069  * 1100 (12) Pin is connected to Peripheral signal trace.d3
6070  *
6071  * 1101 (13) Pin is connected to Peripheral signal not applicable
6072  *
6073  * 1110 (14) Pin is connected to Peripheral signal nand.adq15
6074  *
6075  * 1111 (15) Pin is connected to Peripheral signal gpio1.io23
6076  *
6077  * Field Access Macros:
6078  *
6079  */
6080 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_12_SEL register field. */
6081 #define ALT_PINMUX_SHARED_3V_IO_Q4_12_SEL_LSB 0
6082 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_12_SEL register field. */
6083 #define ALT_PINMUX_SHARED_3V_IO_Q4_12_SEL_MSB 3
6084 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_12_SEL register field. */
6085 #define ALT_PINMUX_SHARED_3V_IO_Q4_12_SEL_WIDTH 4
6086 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_12_SEL register field value. */
6087 #define ALT_PINMUX_SHARED_3V_IO_Q4_12_SEL_SET_MSK 0x0000000f
6088 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_12_SEL register field value. */
6089 #define ALT_PINMUX_SHARED_3V_IO_Q4_12_SEL_CLR_MSK 0xfffffff0
6090 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_12_SEL register field. */
6091 #define ALT_PINMUX_SHARED_3V_IO_Q4_12_SEL_RESET 0xf
6092 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_12_SEL field value from a register. */
6093 #define ALT_PINMUX_SHARED_3V_IO_Q4_12_SEL_GET(value) (((value) & 0x0000000f) >> 0)
6094 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_12_SEL register field value suitable for setting the register. */
6095 #define ALT_PINMUX_SHARED_3V_IO_Q4_12_SEL_SET(value) (((value) << 0) & 0x0000000f)
6096 
6097 /*
6098  * Field : Reserved
6099  *
6100  * Reserved
6101  *
6102  * Field Access Macros:
6103  *
6104  */
6105 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_12_RSVD register field. */
6106 #define ALT_PINMUX_SHARED_3V_IO_Q4_12_RSVD_LSB 4
6107 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q4_12_RSVD register field. */
6108 #define ALT_PINMUX_SHARED_3V_IO_Q4_12_RSVD_MSB 31
6109 /* The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q4_12_RSVD register field. */
6110 #define ALT_PINMUX_SHARED_3V_IO_Q4_12_RSVD_WIDTH 28
6111 /* The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q4_12_RSVD register field value. */
6112 #define ALT_PINMUX_SHARED_3V_IO_Q4_12_RSVD_SET_MSK 0xfffffff0
6113 /* The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q4_12_RSVD register field value. */
6114 #define ALT_PINMUX_SHARED_3V_IO_Q4_12_RSVD_CLR_MSK 0x0000000f
6115 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_12_RSVD register field. */
6116 #define ALT_PINMUX_SHARED_3V_IO_Q4_12_RSVD_RESET 0x0
6117 /* Extracts the ALT_PINMUX_SHARED_3V_IO_Q4_12_RSVD field value from a register. */
6118 #define ALT_PINMUX_SHARED_3V_IO_Q4_12_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
6119 /* Produces a ALT_PINMUX_SHARED_3V_IO_Q4_12_RSVD register field value suitable for setting the register. */
6120 #define ALT_PINMUX_SHARED_3V_IO_Q4_12_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
6121 
6122 #ifndef __ASSEMBLY__
6123 /*
6124  * WARNING: The C register and register group struct declarations are provided for
6125  * convenience and illustrative purposes. They should, however, be used with
6126  * caution as the C language standard provides no guarantees about the alignment or
6127  * atomicity of device memory accesses. The recommended practice for writing
6128  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6129  * alt_write_word() functions.
6130  *
6131  * The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_12.
6132  */
6133 struct ALT_PINMUX_SHARED_3V_IO_Q4_12_s
6134 {
6135  uint32_t sel : 4; /* Shared IO48 Q4 12 Mux Selection Field */
6136  const uint32_t Reserved : 28; /* ALT_PINMUX_SHARED_3V_IO_Q4_12_RSVD */
6137 };
6138 
6139 /* The typedef declaration for register ALT_PINMUX_SHARED_3V_IO_Q4_12. */
6140 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_Q4_12_s ALT_PINMUX_SHARED_3V_IO_Q4_12_t;
6141 #endif /* __ASSEMBLY__ */
6142 
6143 /* The reset value of the ALT_PINMUX_SHARED_3V_IO_Q4_12 register. */
6144 #define ALT_PINMUX_SHARED_3V_IO_Q4_12_RESET 0x0000000f
6145 /* The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q4_12 register from the beginning of the component. */
6146 #define ALT_PINMUX_SHARED_3V_IO_Q4_12_OFST 0xbc
6147 
6148 #ifndef __ASSEMBLY__
6149 /*
6150  * WARNING: The C register and register group struct declarations are provided for
6151  * convenience and illustrative purposes. They should, however, be used with
6152  * caution as the C language standard provides no guarantees about the alignment or
6153  * atomicity of device memory accesses. The recommended practice for writing
6154  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6155  * alt_write_word() functions.
6156  *
6157  * The struct declaration for register group ALT_PINMUX_SHARED_3V_IO_GRP.
6158  */
6159 struct ALT_PINMUX_SHARED_3V_IO_GRP_s
6160 {
6161  ALT_PINMUX_SHARED_3V_IO_Q1_1_t pinmux_shared_io_q1_1; /* ALT_PINMUX_SHARED_3V_IO_Q1_1 */
6162  ALT_PINMUX_SHARED_3V_IO_Q1_2_t pinmux_shared_io_q1_2; /* ALT_PINMUX_SHARED_3V_IO_Q1_2 */
6163  ALT_PINMUX_SHARED_3V_IO_Q1_3_t pinmux_shared_io_q1_3; /* ALT_PINMUX_SHARED_3V_IO_Q1_3 */
6164  ALT_PINMUX_SHARED_3V_IO_Q1_4_t pinmux_shared_io_q1_4; /* ALT_PINMUX_SHARED_3V_IO_Q1_4 */
6165  ALT_PINMUX_SHARED_3V_IO_Q1_5_t pinmux_shared_io_q1_5; /* ALT_PINMUX_SHARED_3V_IO_Q1_5 */
6166  ALT_PINMUX_SHARED_3V_IO_Q1_6_t pinmux_shared_io_q1_6; /* ALT_PINMUX_SHARED_3V_IO_Q1_6 */
6167  ALT_PINMUX_SHARED_3V_IO_Q1_7_t pinmux_shared_io_q1_7; /* ALT_PINMUX_SHARED_3V_IO_Q1_7 */
6168  ALT_PINMUX_SHARED_3V_IO_Q1_8_t pinmux_shared_io_q1_8; /* ALT_PINMUX_SHARED_3V_IO_Q1_8 */
6169  ALT_PINMUX_SHARED_3V_IO_Q1_9_t pinmux_shared_io_q1_9; /* ALT_PINMUX_SHARED_3V_IO_Q1_9 */
6170  ALT_PINMUX_SHARED_3V_IO_Q1_10_t pinmux_shared_io_q1_10; /* ALT_PINMUX_SHARED_3V_IO_Q1_10 */
6171  ALT_PINMUX_SHARED_3V_IO_Q1_11_t pinmux_shared_io_q1_11; /* ALT_PINMUX_SHARED_3V_IO_Q1_11 */
6172  ALT_PINMUX_SHARED_3V_IO_Q1_12_t pinmux_shared_io_q1_12; /* ALT_PINMUX_SHARED_3V_IO_Q1_12 */
6173  ALT_PINMUX_SHARED_3V_IO_Q2_1_t pinmux_shared_io_q2_1; /* ALT_PINMUX_SHARED_3V_IO_Q2_1 */
6174  ALT_PINMUX_SHARED_3V_IO_Q2_2_t pinmux_shared_io_q2_2; /* ALT_PINMUX_SHARED_3V_IO_Q2_2 */
6175  ALT_PINMUX_SHARED_3V_IO_Q2_3_t pinmux_shared_io_q2_3; /* ALT_PINMUX_SHARED_3V_IO_Q2_3 */
6176  ALT_PINMUX_SHARED_3V_IO_Q2_4_t pinmux_shared_io_q2_4; /* ALT_PINMUX_SHARED_3V_IO_Q2_4 */
6177  ALT_PINMUX_SHARED_3V_IO_Q2_5_t pinmux_shared_io_q2_5; /* ALT_PINMUX_SHARED_3V_IO_Q2_5 */
6178  ALT_PINMUX_SHARED_3V_IO_Q2_6_t pinmux_shared_io_q2_6; /* ALT_PINMUX_SHARED_3V_IO_Q2_6 */
6179  ALT_PINMUX_SHARED_3V_IO_Q2_7_t pinmux_shared_io_q2_7; /* ALT_PINMUX_SHARED_3V_IO_Q2_7 */
6180  ALT_PINMUX_SHARED_3V_IO_Q2_8_t pinmux_shared_io_q2_8; /* ALT_PINMUX_SHARED_3V_IO_Q2_8 */
6181  ALT_PINMUX_SHARED_3V_IO_Q2_9_t pinmux_shared_io_q2_9; /* ALT_PINMUX_SHARED_3V_IO_Q2_9 */
6182  ALT_PINMUX_SHARED_3V_IO_Q2_10_t pinmux_shared_io_q2_10; /* ALT_PINMUX_SHARED_3V_IO_Q2_10 */
6183  ALT_PINMUX_SHARED_3V_IO_Q2_11_t pinmux_shared_io_q2_11; /* ALT_PINMUX_SHARED_3V_IO_Q2_11 */
6184  ALT_PINMUX_SHARED_3V_IO_Q2_12_t pinmux_shared_io_q2_12; /* ALT_PINMUX_SHARED_3V_IO_Q2_12 */
6185  ALT_PINMUX_SHARED_3V_IO_Q3_1_t pinmux_shared_io_q3_1; /* ALT_PINMUX_SHARED_3V_IO_Q3_1 */
6186  ALT_PINMUX_SHARED_3V_IO_Q3_2_t pinmux_shared_io_q3_2; /* ALT_PINMUX_SHARED_3V_IO_Q3_2 */
6187  ALT_PINMUX_SHARED_3V_IO_Q3_3_t pinmux_shared_io_q3_3; /* ALT_PINMUX_SHARED_3V_IO_Q3_3 */
6188  ALT_PINMUX_SHARED_3V_IO_Q3_4_t pinmux_shared_io_q3_4; /* ALT_PINMUX_SHARED_3V_IO_Q3_4 */
6189  ALT_PINMUX_SHARED_3V_IO_Q3_5_t pinmux_shared_io_q3_5; /* ALT_PINMUX_SHARED_3V_IO_Q3_5 */
6190  ALT_PINMUX_SHARED_3V_IO_Q3_6_t pinmux_shared_io_q3_6; /* ALT_PINMUX_SHARED_3V_IO_Q3_6 */
6191  ALT_PINMUX_SHARED_3V_IO_Q3_7_t pinmux_shared_io_q3_7; /* ALT_PINMUX_SHARED_3V_IO_Q3_7 */
6192  ALT_PINMUX_SHARED_3V_IO_Q3_8_t pinmux_shared_io_q3_8; /* ALT_PINMUX_SHARED_3V_IO_Q3_8 */
6193  ALT_PINMUX_SHARED_3V_IO_Q3_9_t pinmux_shared_io_q3_9; /* ALT_PINMUX_SHARED_3V_IO_Q3_9 */
6194  ALT_PINMUX_SHARED_3V_IO_Q3_10_t pinmux_shared_io_q3_10; /* ALT_PINMUX_SHARED_3V_IO_Q3_10 */
6195  ALT_PINMUX_SHARED_3V_IO_Q3_11_t pinmux_shared_io_q3_11; /* ALT_PINMUX_SHARED_3V_IO_Q3_11 */
6196  ALT_PINMUX_SHARED_3V_IO_Q3_12_t pinmux_shared_io_q3_12; /* ALT_PINMUX_SHARED_3V_IO_Q3_12 */
6197  ALT_PINMUX_SHARED_3V_IO_Q4_1_t pinmux_shared_io_q4_1; /* ALT_PINMUX_SHARED_3V_IO_Q4_1 */
6198  ALT_PINMUX_SHARED_3V_IO_Q4_2_t pinmux_shared_io_q4_2; /* ALT_PINMUX_SHARED_3V_IO_Q4_2 */
6199  ALT_PINMUX_SHARED_3V_IO_Q4_3_t pinmux_shared_io_q4_3; /* ALT_PINMUX_SHARED_3V_IO_Q4_3 */
6200  ALT_PINMUX_SHARED_3V_IO_Q4_4_t pinmux_shared_io_q4_4; /* ALT_PINMUX_SHARED_3V_IO_Q4_4 */
6201  ALT_PINMUX_SHARED_3V_IO_Q4_5_t pinmux_shared_io_q4_5; /* ALT_PINMUX_SHARED_3V_IO_Q4_5 */
6202  ALT_PINMUX_SHARED_3V_IO_Q4_6_t pinmux_shared_io_q4_6; /* ALT_PINMUX_SHARED_3V_IO_Q4_6 */
6203  ALT_PINMUX_SHARED_3V_IO_Q4_7_t pinmux_shared_io_q4_7; /* ALT_PINMUX_SHARED_3V_IO_Q4_7 */
6204  ALT_PINMUX_SHARED_3V_IO_Q4_8_t pinmux_shared_io_q4_8; /* ALT_PINMUX_SHARED_3V_IO_Q4_8 */
6205  ALT_PINMUX_SHARED_3V_IO_Q4_9_t pinmux_shared_io_q4_9; /* ALT_PINMUX_SHARED_3V_IO_Q4_9 */
6206  ALT_PINMUX_SHARED_3V_IO_Q4_10_t pinmux_shared_io_q4_10; /* ALT_PINMUX_SHARED_3V_IO_Q4_10 */
6207  ALT_PINMUX_SHARED_3V_IO_Q4_11_t pinmux_shared_io_q4_11; /* ALT_PINMUX_SHARED_3V_IO_Q4_11 */
6208  ALT_PINMUX_SHARED_3V_IO_Q4_12_t pinmux_shared_io_q4_12; /* ALT_PINMUX_SHARED_3V_IO_Q4_12 */
6209  volatile uint32_t _pad_0xc0_0x200[80]; /* *UNDEFINED* */
6210 };
6211 
6212 /* The typedef declaration for register group ALT_PINMUX_SHARED_3V_IO_GRP. */
6213 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_GRP_s ALT_PINMUX_SHARED_3V_IO_GRP_t;
6214 /* The struct declaration for the raw register contents of register group ALT_PINMUX_SHARED_3V_IO_GRP. */
6215 struct ALT_PINMUX_SHARED_3V_IO_GRP_raw_s
6216 {
6217  volatile uint32_t pinmux_shared_io_q1_1; /* ALT_PINMUX_SHARED_3V_IO_Q1_1 */
6218  volatile uint32_t pinmux_shared_io_q1_2; /* ALT_PINMUX_SHARED_3V_IO_Q1_2 */
6219  volatile uint32_t pinmux_shared_io_q1_3; /* ALT_PINMUX_SHARED_3V_IO_Q1_3 */
6220  volatile uint32_t pinmux_shared_io_q1_4; /* ALT_PINMUX_SHARED_3V_IO_Q1_4 */
6221  volatile uint32_t pinmux_shared_io_q1_5; /* ALT_PINMUX_SHARED_3V_IO_Q1_5 */
6222  volatile uint32_t pinmux_shared_io_q1_6; /* ALT_PINMUX_SHARED_3V_IO_Q1_6 */
6223  volatile uint32_t pinmux_shared_io_q1_7; /* ALT_PINMUX_SHARED_3V_IO_Q1_7 */
6224  volatile uint32_t pinmux_shared_io_q1_8; /* ALT_PINMUX_SHARED_3V_IO_Q1_8 */
6225  volatile uint32_t pinmux_shared_io_q1_9; /* ALT_PINMUX_SHARED_3V_IO_Q1_9 */
6226  volatile uint32_t pinmux_shared_io_q1_10; /* ALT_PINMUX_SHARED_3V_IO_Q1_10 */
6227  volatile uint32_t pinmux_shared_io_q1_11; /* ALT_PINMUX_SHARED_3V_IO_Q1_11 */
6228  volatile uint32_t pinmux_shared_io_q1_12; /* ALT_PINMUX_SHARED_3V_IO_Q1_12 */
6229  volatile uint32_t pinmux_shared_io_q2_1; /* ALT_PINMUX_SHARED_3V_IO_Q2_1 */
6230  volatile uint32_t pinmux_shared_io_q2_2; /* ALT_PINMUX_SHARED_3V_IO_Q2_2 */
6231  volatile uint32_t pinmux_shared_io_q2_3; /* ALT_PINMUX_SHARED_3V_IO_Q2_3 */
6232  volatile uint32_t pinmux_shared_io_q2_4; /* ALT_PINMUX_SHARED_3V_IO_Q2_4 */
6233  volatile uint32_t pinmux_shared_io_q2_5; /* ALT_PINMUX_SHARED_3V_IO_Q2_5 */
6234  volatile uint32_t pinmux_shared_io_q2_6; /* ALT_PINMUX_SHARED_3V_IO_Q2_6 */
6235  volatile uint32_t pinmux_shared_io_q2_7; /* ALT_PINMUX_SHARED_3V_IO_Q2_7 */
6236  volatile uint32_t pinmux_shared_io_q2_8; /* ALT_PINMUX_SHARED_3V_IO_Q2_8 */
6237  volatile uint32_t pinmux_shared_io_q2_9; /* ALT_PINMUX_SHARED_3V_IO_Q2_9 */
6238  volatile uint32_t pinmux_shared_io_q2_10; /* ALT_PINMUX_SHARED_3V_IO_Q2_10 */
6239  volatile uint32_t pinmux_shared_io_q2_11; /* ALT_PINMUX_SHARED_3V_IO_Q2_11 */
6240  volatile uint32_t pinmux_shared_io_q2_12; /* ALT_PINMUX_SHARED_3V_IO_Q2_12 */
6241  volatile uint32_t pinmux_shared_io_q3_1; /* ALT_PINMUX_SHARED_3V_IO_Q3_1 */
6242  volatile uint32_t pinmux_shared_io_q3_2; /* ALT_PINMUX_SHARED_3V_IO_Q3_2 */
6243  volatile uint32_t pinmux_shared_io_q3_3; /* ALT_PINMUX_SHARED_3V_IO_Q3_3 */
6244  volatile uint32_t pinmux_shared_io_q3_4; /* ALT_PINMUX_SHARED_3V_IO_Q3_4 */
6245  volatile uint32_t pinmux_shared_io_q3_5; /* ALT_PINMUX_SHARED_3V_IO_Q3_5 */
6246  volatile uint32_t pinmux_shared_io_q3_6; /* ALT_PINMUX_SHARED_3V_IO_Q3_6 */
6247  volatile uint32_t pinmux_shared_io_q3_7; /* ALT_PINMUX_SHARED_3V_IO_Q3_7 */
6248  volatile uint32_t pinmux_shared_io_q3_8; /* ALT_PINMUX_SHARED_3V_IO_Q3_8 */
6249  volatile uint32_t pinmux_shared_io_q3_9; /* ALT_PINMUX_SHARED_3V_IO_Q3_9 */
6250  volatile uint32_t pinmux_shared_io_q3_10; /* ALT_PINMUX_SHARED_3V_IO_Q3_10 */
6251  volatile uint32_t pinmux_shared_io_q3_11; /* ALT_PINMUX_SHARED_3V_IO_Q3_11 */
6252  volatile uint32_t pinmux_shared_io_q3_12; /* ALT_PINMUX_SHARED_3V_IO_Q3_12 */
6253  volatile uint32_t pinmux_shared_io_q4_1; /* ALT_PINMUX_SHARED_3V_IO_Q4_1 */
6254  volatile uint32_t pinmux_shared_io_q4_2; /* ALT_PINMUX_SHARED_3V_IO_Q4_2 */
6255  volatile uint32_t pinmux_shared_io_q4_3; /* ALT_PINMUX_SHARED_3V_IO_Q4_3 */
6256  volatile uint32_t pinmux_shared_io_q4_4; /* ALT_PINMUX_SHARED_3V_IO_Q4_4 */
6257  volatile uint32_t pinmux_shared_io_q4_5; /* ALT_PINMUX_SHARED_3V_IO_Q4_5 */
6258  volatile uint32_t pinmux_shared_io_q4_6; /* ALT_PINMUX_SHARED_3V_IO_Q4_6 */
6259  volatile uint32_t pinmux_shared_io_q4_7; /* ALT_PINMUX_SHARED_3V_IO_Q4_7 */
6260  volatile uint32_t pinmux_shared_io_q4_8; /* ALT_PINMUX_SHARED_3V_IO_Q4_8 */
6261  volatile uint32_t pinmux_shared_io_q4_9; /* ALT_PINMUX_SHARED_3V_IO_Q4_9 */
6262  volatile uint32_t pinmux_shared_io_q4_10; /* ALT_PINMUX_SHARED_3V_IO_Q4_10 */
6263  volatile uint32_t pinmux_shared_io_q4_11; /* ALT_PINMUX_SHARED_3V_IO_Q4_11 */
6264  volatile uint32_t pinmux_shared_io_q4_12; /* ALT_PINMUX_SHARED_3V_IO_Q4_12 */
6265  uint32_t _pad_0xc0_0x200[80]; /* *UNDEFINED* */
6266 };
6267 
6268 /* The typedef declaration for the raw register contents of register group ALT_PINMUX_SHARED_3V_IO_GRP. */
6269 typedef volatile struct ALT_PINMUX_SHARED_3V_IO_GRP_raw_s ALT_PINMUX_SHARED_3V_IO_GRP_raw_t;
6270 #endif /* __ASSEMBLY__ */
6271 
6272 
6273 /*
6274  * Component : ALT_PINMUX_DCTD_IO_GRP
6275  *
6276  */
6277 /*
6278  * Register : Dedicated IO 1 OSC_CLK - pinmux_dedicated_io_1
6279  *
6280  * reserved
6281  *
6282  * Register Layout
6283  *
6284  * Bits | Access | Reset | Description
6285  * :-------|:-------|:------|:--------------------------
6286  * [31:0] | R | 0x0 | ALT_PINMUX_DCTD_IO_1_RSVD
6287  *
6288  */
6289 /*
6290  * Field : Reserved
6291  *
6292  * Field Access Macros:
6293  *
6294  */
6295 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_1_RSVD register field. */
6296 #define ALT_PINMUX_DCTD_IO_1_RSVD_LSB 0
6297 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_1_RSVD register field. */
6298 #define ALT_PINMUX_DCTD_IO_1_RSVD_MSB 31
6299 /* The width in bits of the ALT_PINMUX_DCTD_IO_1_RSVD register field. */
6300 #define ALT_PINMUX_DCTD_IO_1_RSVD_WIDTH 32
6301 /* The mask used to set the ALT_PINMUX_DCTD_IO_1_RSVD register field value. */
6302 #define ALT_PINMUX_DCTD_IO_1_RSVD_SET_MSK 0xffffffff
6303 /* The mask used to clear the ALT_PINMUX_DCTD_IO_1_RSVD register field value. */
6304 #define ALT_PINMUX_DCTD_IO_1_RSVD_CLR_MSK 0x00000000
6305 /* The reset value of the ALT_PINMUX_DCTD_IO_1_RSVD register field. */
6306 #define ALT_PINMUX_DCTD_IO_1_RSVD_RESET 0x0
6307 /* Extracts the ALT_PINMUX_DCTD_IO_1_RSVD field value from a register. */
6308 #define ALT_PINMUX_DCTD_IO_1_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
6309 /* Produces a ALT_PINMUX_DCTD_IO_1_RSVD register field value suitable for setting the register. */
6310 #define ALT_PINMUX_DCTD_IO_1_RSVD_SET(value) (((value) << 0) & 0xffffffff)
6311 
6312 #ifndef __ASSEMBLY__
6313 /*
6314  * WARNING: The C register and register group struct declarations are provided for
6315  * convenience and illustrative purposes. They should, however, be used with
6316  * caution as the C language standard provides no guarantees about the alignment or
6317  * atomicity of device memory accesses. The recommended practice for writing
6318  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6319  * alt_write_word() functions.
6320  *
6321  * The struct declaration for register ALT_PINMUX_DCTD_IO_1.
6322  */
6323 struct ALT_PINMUX_DCTD_IO_1_s
6324 {
6325  const uint32_t Reserved : 32; /* ALT_PINMUX_DCTD_IO_1_RSVD */
6326 };
6327 
6328 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_1. */
6329 typedef volatile struct ALT_PINMUX_DCTD_IO_1_s ALT_PINMUX_DCTD_IO_1_t;
6330 #endif /* __ASSEMBLY__ */
6331 
6332 /* The reset value of the ALT_PINMUX_DCTD_IO_1 register. */
6333 #define ALT_PINMUX_DCTD_IO_1_RESET 0x00000000
6334 /* The byte offset of the ALT_PINMUX_DCTD_IO_1 register from the beginning of the component. */
6335 #define ALT_PINMUX_DCTD_IO_1_OFST 0x0
6336 
6337 /*
6338  * Register : Dedicated IO 2 nPOR - pinmux_dedicated_io_2
6339  *
6340  * reserved
6341  *
6342  * Register Layout
6343  *
6344  * Bits | Access | Reset | Description
6345  * :-------|:-------|:------|:--------------------------
6346  * [31:0] | R | 0x0 | ALT_PINMUX_DCTD_IO_2_RSVD
6347  *
6348  */
6349 /*
6350  * Field : Reserved
6351  *
6352  * Field Access Macros:
6353  *
6354  */
6355 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_2_RSVD register field. */
6356 #define ALT_PINMUX_DCTD_IO_2_RSVD_LSB 0
6357 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_2_RSVD register field. */
6358 #define ALT_PINMUX_DCTD_IO_2_RSVD_MSB 31
6359 /* The width in bits of the ALT_PINMUX_DCTD_IO_2_RSVD register field. */
6360 #define ALT_PINMUX_DCTD_IO_2_RSVD_WIDTH 32
6361 /* The mask used to set the ALT_PINMUX_DCTD_IO_2_RSVD register field value. */
6362 #define ALT_PINMUX_DCTD_IO_2_RSVD_SET_MSK 0xffffffff
6363 /* The mask used to clear the ALT_PINMUX_DCTD_IO_2_RSVD register field value. */
6364 #define ALT_PINMUX_DCTD_IO_2_RSVD_CLR_MSK 0x00000000
6365 /* The reset value of the ALT_PINMUX_DCTD_IO_2_RSVD register field. */
6366 #define ALT_PINMUX_DCTD_IO_2_RSVD_RESET 0x0
6367 /* Extracts the ALT_PINMUX_DCTD_IO_2_RSVD field value from a register. */
6368 #define ALT_PINMUX_DCTD_IO_2_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
6369 /* Produces a ALT_PINMUX_DCTD_IO_2_RSVD register field value suitable for setting the register. */
6370 #define ALT_PINMUX_DCTD_IO_2_RSVD_SET(value) (((value) << 0) & 0xffffffff)
6371 
6372 #ifndef __ASSEMBLY__
6373 /*
6374  * WARNING: The C register and register group struct declarations are provided for
6375  * convenience and illustrative purposes. They should, however, be used with
6376  * caution as the C language standard provides no guarantees about the alignment or
6377  * atomicity of device memory accesses. The recommended practice for writing
6378  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6379  * alt_write_word() functions.
6380  *
6381  * The struct declaration for register ALT_PINMUX_DCTD_IO_2.
6382  */
6383 struct ALT_PINMUX_DCTD_IO_2_s
6384 {
6385  const uint32_t Reserved : 32; /* ALT_PINMUX_DCTD_IO_2_RSVD */
6386 };
6387 
6388 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_2. */
6389 typedef volatile struct ALT_PINMUX_DCTD_IO_2_s ALT_PINMUX_DCTD_IO_2_t;
6390 #endif /* __ASSEMBLY__ */
6391 
6392 /* The reset value of the ALT_PINMUX_DCTD_IO_2 register. */
6393 #define ALT_PINMUX_DCTD_IO_2_RESET 0x00000000
6394 /* The byte offset of the ALT_PINMUX_DCTD_IO_2 register from the beginning of the component. */
6395 #define ALT_PINMUX_DCTD_IO_2_OFST 0x4
6396 
6397 /*
6398  * Register : Dedicated IO 3 nRST - pinmux_dedicated_io_3
6399  *
6400  * reserved
6401  *
6402  * Register Layout
6403  *
6404  * Bits | Access | Reset | Description
6405  * :-------|:-------|:------|:--------------------------
6406  * [31:0] | R | 0x0 | ALT_PINMUX_DCTD_IO_3_RSVD
6407  *
6408  */
6409 /*
6410  * Field : Reserved
6411  *
6412  * Field Access Macros:
6413  *
6414  */
6415 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_3_RSVD register field. */
6416 #define ALT_PINMUX_DCTD_IO_3_RSVD_LSB 0
6417 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_3_RSVD register field. */
6418 #define ALT_PINMUX_DCTD_IO_3_RSVD_MSB 31
6419 /* The width in bits of the ALT_PINMUX_DCTD_IO_3_RSVD register field. */
6420 #define ALT_PINMUX_DCTD_IO_3_RSVD_WIDTH 32
6421 /* The mask used to set the ALT_PINMUX_DCTD_IO_3_RSVD register field value. */
6422 #define ALT_PINMUX_DCTD_IO_3_RSVD_SET_MSK 0xffffffff
6423 /* The mask used to clear the ALT_PINMUX_DCTD_IO_3_RSVD register field value. */
6424 #define ALT_PINMUX_DCTD_IO_3_RSVD_CLR_MSK 0x00000000
6425 /* The reset value of the ALT_PINMUX_DCTD_IO_3_RSVD register field. */
6426 #define ALT_PINMUX_DCTD_IO_3_RSVD_RESET 0x0
6427 /* Extracts the ALT_PINMUX_DCTD_IO_3_RSVD field value from a register. */
6428 #define ALT_PINMUX_DCTD_IO_3_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
6429 /* Produces a ALT_PINMUX_DCTD_IO_3_RSVD register field value suitable for setting the register. */
6430 #define ALT_PINMUX_DCTD_IO_3_RSVD_SET(value) (((value) << 0) & 0xffffffff)
6431 
6432 #ifndef __ASSEMBLY__
6433 /*
6434  * WARNING: The C register and register group struct declarations are provided for
6435  * convenience and illustrative purposes. They should, however, be used with
6436  * caution as the C language standard provides no guarantees about the alignment or
6437  * atomicity of device memory accesses. The recommended practice for writing
6438  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6439  * alt_write_word() functions.
6440  *
6441  * The struct declaration for register ALT_PINMUX_DCTD_IO_3.
6442  */
6443 struct ALT_PINMUX_DCTD_IO_3_s
6444 {
6445  const uint32_t Reserved : 32; /* ALT_PINMUX_DCTD_IO_3_RSVD */
6446 };
6447 
6448 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_3. */
6449 typedef volatile struct ALT_PINMUX_DCTD_IO_3_s ALT_PINMUX_DCTD_IO_3_t;
6450 #endif /* __ASSEMBLY__ */
6451 
6452 /* The reset value of the ALT_PINMUX_DCTD_IO_3 register. */
6453 #define ALT_PINMUX_DCTD_IO_3_RESET 0x00000000
6454 /* The byte offset of the ALT_PINMUX_DCTD_IO_3 register from the beginning of the component. */
6455 #define ALT_PINMUX_DCTD_IO_3_OFST 0x8
6456 
6457 /*
6458  * Register : Dedicated IO 4 Mux Selection Register - pinmux_dedicated_io_4
6459  *
6460  * This register is used to control the peripherals connected to dedicated IO pin 4
6461  *
6462  * Only reset by a cold reset (ignores warm reset).
6463  *
6464  * NOTE: These registers should not be modified after IO configuration.There is no
6465  * support for dynamically changing the Pin Mux selections.
6466  *
6467  * Register Layout
6468  *
6469  * Bits | Access | Reset | Description
6470  * :-------|:-------|:------|:-----------------------------------
6471  * [3:0] | RW | 0xf | Dedicated IO 4 Mux Selection Field
6472  * [31:4] | R | 0x0 | ALT_PINMUX_DCTD_IO_4_RSVD
6473  *
6474  */
6475 /*
6476  * Field : Dedicated IO 4 Mux Selection Field - sel
6477  *
6478  * Select peripheral signals connected Dedicated IO 4
6479  *
6480  * 0000 (0) Pin is connected to Peripheral signal not applicable
6481  *
6482  * 0001 (1) Pin is connected to Peripheral signal not applicable
6483  *
6484  * 0010 (2) Pin is connected to Peripheral signal not applicable
6485  *
6486  * 0011 (3) Pin is connected to Peripheral signal not applicable
6487  *
6488  * 0100 (4) Pin is connected to Peripheral signal qspi.clk
6489  *
6490  * 0101 (5) Pin is connected to Peripheral signal not applicable
6491  *
6492  * 0110 (6) Pin is connected to Peripheral signal not applicable
6493  *
6494  * 0111 (7) Pin is connected to Peripheral signal not applicable
6495  *
6496  * 1000 (8) Pin is connected to Peripheral signal sdmmc.data0
6497  *
6498  * 1001 (9) Pin is connected to Peripheral signal not applicable
6499  *
6500  * 1010 (10) Pin is connected to Peripheral signal not applicable
6501  *
6502  * 1011 (11) Pin is connected to Peripheral signal not applicable
6503  *
6504  * 1100 (12) Pin is connected to Peripheral signal not applicable
6505  *
6506  * 1101 (13) Pin is connected to Peripheral signal not applicable
6507  *
6508  * 1110 (14) Pin is connected to Peripheral signal nand.adq0
6509  *
6510  * 1111 (15) Pin is connected to Peripheral signal gpio2.io0
6511  *
6512  * Field Access Macros:
6513  *
6514  */
6515 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_4_SEL register field. */
6516 #define ALT_PINMUX_DCTD_IO_4_SEL_LSB 0
6517 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_4_SEL register field. */
6518 #define ALT_PINMUX_DCTD_IO_4_SEL_MSB 3
6519 /* The width in bits of the ALT_PINMUX_DCTD_IO_4_SEL register field. */
6520 #define ALT_PINMUX_DCTD_IO_4_SEL_WIDTH 4
6521 /* The mask used to set the ALT_PINMUX_DCTD_IO_4_SEL register field value. */
6522 #define ALT_PINMUX_DCTD_IO_4_SEL_SET_MSK 0x0000000f
6523 /* The mask used to clear the ALT_PINMUX_DCTD_IO_4_SEL register field value. */
6524 #define ALT_PINMUX_DCTD_IO_4_SEL_CLR_MSK 0xfffffff0
6525 /* The reset value of the ALT_PINMUX_DCTD_IO_4_SEL register field. */
6526 #define ALT_PINMUX_DCTD_IO_4_SEL_RESET 0xf
6527 /* Extracts the ALT_PINMUX_DCTD_IO_4_SEL field value from a register. */
6528 #define ALT_PINMUX_DCTD_IO_4_SEL_GET(value) (((value) & 0x0000000f) >> 0)
6529 /* Produces a ALT_PINMUX_DCTD_IO_4_SEL register field value suitable for setting the register. */
6530 #define ALT_PINMUX_DCTD_IO_4_SEL_SET(value) (((value) << 0) & 0x0000000f)
6531 
6532 /*
6533  * Field : Reserved
6534  *
6535  * Reserved
6536  *
6537  * Field Access Macros:
6538  *
6539  */
6540 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_4_RSVD register field. */
6541 #define ALT_PINMUX_DCTD_IO_4_RSVD_LSB 4
6542 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_4_RSVD register field. */
6543 #define ALT_PINMUX_DCTD_IO_4_RSVD_MSB 31
6544 /* The width in bits of the ALT_PINMUX_DCTD_IO_4_RSVD register field. */
6545 #define ALT_PINMUX_DCTD_IO_4_RSVD_WIDTH 28
6546 /* The mask used to set the ALT_PINMUX_DCTD_IO_4_RSVD register field value. */
6547 #define ALT_PINMUX_DCTD_IO_4_RSVD_SET_MSK 0xfffffff0
6548 /* The mask used to clear the ALT_PINMUX_DCTD_IO_4_RSVD register field value. */
6549 #define ALT_PINMUX_DCTD_IO_4_RSVD_CLR_MSK 0x0000000f
6550 /* The reset value of the ALT_PINMUX_DCTD_IO_4_RSVD register field. */
6551 #define ALT_PINMUX_DCTD_IO_4_RSVD_RESET 0x0
6552 /* Extracts the ALT_PINMUX_DCTD_IO_4_RSVD field value from a register. */
6553 #define ALT_PINMUX_DCTD_IO_4_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
6554 /* Produces a ALT_PINMUX_DCTD_IO_4_RSVD register field value suitable for setting the register. */
6555 #define ALT_PINMUX_DCTD_IO_4_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
6556 
6557 #ifndef __ASSEMBLY__
6558 /*
6559  * WARNING: The C register and register group struct declarations are provided for
6560  * convenience and illustrative purposes. They should, however, be used with
6561  * caution as the C language standard provides no guarantees about the alignment or
6562  * atomicity of device memory accesses. The recommended practice for writing
6563  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6564  * alt_write_word() functions.
6565  *
6566  * The struct declaration for register ALT_PINMUX_DCTD_IO_4.
6567  */
6568 struct ALT_PINMUX_DCTD_IO_4_s
6569 {
6570  uint32_t sel : 4; /* Dedicated IO 4 Mux Selection Field */
6571  const uint32_t Reserved : 28; /* ALT_PINMUX_DCTD_IO_4_RSVD */
6572 };
6573 
6574 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_4. */
6575 typedef volatile struct ALT_PINMUX_DCTD_IO_4_s ALT_PINMUX_DCTD_IO_4_t;
6576 #endif /* __ASSEMBLY__ */
6577 
6578 /* The reset value of the ALT_PINMUX_DCTD_IO_4 register. */
6579 #define ALT_PINMUX_DCTD_IO_4_RESET 0x0000000f
6580 /* The byte offset of the ALT_PINMUX_DCTD_IO_4 register from the beginning of the component. */
6581 #define ALT_PINMUX_DCTD_IO_4_OFST 0xc
6582 
6583 /*
6584  * Register : Dedicated IO 5 Mux Selection Register - pinmux_dedicated_io_5
6585  *
6586  * This register is used to control the peripherals connected to dedicated IO pin 5
6587  *
6588  * Only reset by a cold reset (ignores warm reset).
6589  *
6590  * NOTE: These registers should not be modified after IO configuration.There is no
6591  * support for dynamically changing the Pin Mux selections.
6592  *
6593  * Register Layout
6594  *
6595  * Bits | Access | Reset | Description
6596  * :-------|:-------|:------|:-----------------------------------
6597  * [3:0] | RW | 0xf | Dedicated IO 5 Mux Selection Field
6598  * [31:4] | R | 0x0 | ALT_PINMUX_DCTD_IO_5_RSVD
6599  *
6600  */
6601 /*
6602  * Field : Dedicated IO 5 Mux Selection Field - sel
6603  *
6604  * Select peripheral signals connected Dedicated IO 5
6605  *
6606  * 0000 (0) Pin is connected to Peripheral signal not applicable
6607  *
6608  * 0001 (1) Pin is connected to Peripheral signal not applicable
6609  *
6610  * 0010 (2) Pin is connected to Peripheral signal not applicable
6611  *
6612  * 0011 (3) Pin is connected to Peripheral signal not applicable
6613  *
6614  * 0100 (4) Pin is connected to Peripheral signal qspi.io0
6615  *
6616  * 0101 (5) Pin is connected to Peripheral signal not applicable
6617  *
6618  * 0110 (6) Pin is connected to Peripheral signal not applicable
6619  *
6620  * 0111 (7) Pin is connected to Peripheral signal not applicable
6621  *
6622  * 1000 (8) Pin is connected to Peripheral signal sdmmc.cmd
6623  *
6624  * 1001 (9) Pin is connected to Peripheral signal not applicable
6625  *
6626  * 1010 (10) Pin is connected to Peripheral signal not applicable
6627  *
6628  * 1011 (11) Pin is connected to Peripheral signal not applicable
6629  *
6630  * 1100 (12) Pin is connected to Peripheral signal not applicable
6631  *
6632  * 1101 (13) Pin is connected to Peripheral signal not applicable
6633  *
6634  * 1110 (14) Pin is connected to Peripheral signal nand.adq1
6635  *
6636  * 1111 (15) Pin is connected to Peripheral signal gpio2.io1
6637  *
6638  * Field Access Macros:
6639  *
6640  */
6641 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_5_SEL register field. */
6642 #define ALT_PINMUX_DCTD_IO_5_SEL_LSB 0
6643 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_5_SEL register field. */
6644 #define ALT_PINMUX_DCTD_IO_5_SEL_MSB 3
6645 /* The width in bits of the ALT_PINMUX_DCTD_IO_5_SEL register field. */
6646 #define ALT_PINMUX_DCTD_IO_5_SEL_WIDTH 4
6647 /* The mask used to set the ALT_PINMUX_DCTD_IO_5_SEL register field value. */
6648 #define ALT_PINMUX_DCTD_IO_5_SEL_SET_MSK 0x0000000f
6649 /* The mask used to clear the ALT_PINMUX_DCTD_IO_5_SEL register field value. */
6650 #define ALT_PINMUX_DCTD_IO_5_SEL_CLR_MSK 0xfffffff0
6651 /* The reset value of the ALT_PINMUX_DCTD_IO_5_SEL register field. */
6652 #define ALT_PINMUX_DCTD_IO_5_SEL_RESET 0xf
6653 /* Extracts the ALT_PINMUX_DCTD_IO_5_SEL field value from a register. */
6654 #define ALT_PINMUX_DCTD_IO_5_SEL_GET(value) (((value) & 0x0000000f) >> 0)
6655 /* Produces a ALT_PINMUX_DCTD_IO_5_SEL register field value suitable for setting the register. */
6656 #define ALT_PINMUX_DCTD_IO_5_SEL_SET(value) (((value) << 0) & 0x0000000f)
6657 
6658 /*
6659  * Field : Reserved
6660  *
6661  * Reserved
6662  *
6663  * Field Access Macros:
6664  *
6665  */
6666 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_5_RSVD register field. */
6667 #define ALT_PINMUX_DCTD_IO_5_RSVD_LSB 4
6668 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_5_RSVD register field. */
6669 #define ALT_PINMUX_DCTD_IO_5_RSVD_MSB 31
6670 /* The width in bits of the ALT_PINMUX_DCTD_IO_5_RSVD register field. */
6671 #define ALT_PINMUX_DCTD_IO_5_RSVD_WIDTH 28
6672 /* The mask used to set the ALT_PINMUX_DCTD_IO_5_RSVD register field value. */
6673 #define ALT_PINMUX_DCTD_IO_5_RSVD_SET_MSK 0xfffffff0
6674 /* The mask used to clear the ALT_PINMUX_DCTD_IO_5_RSVD register field value. */
6675 #define ALT_PINMUX_DCTD_IO_5_RSVD_CLR_MSK 0x0000000f
6676 /* The reset value of the ALT_PINMUX_DCTD_IO_5_RSVD register field. */
6677 #define ALT_PINMUX_DCTD_IO_5_RSVD_RESET 0x0
6678 /* Extracts the ALT_PINMUX_DCTD_IO_5_RSVD field value from a register. */
6679 #define ALT_PINMUX_DCTD_IO_5_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
6680 /* Produces a ALT_PINMUX_DCTD_IO_5_RSVD register field value suitable for setting the register. */
6681 #define ALT_PINMUX_DCTD_IO_5_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
6682 
6683 #ifndef __ASSEMBLY__
6684 /*
6685  * WARNING: The C register and register group struct declarations are provided for
6686  * convenience and illustrative purposes. They should, however, be used with
6687  * caution as the C language standard provides no guarantees about the alignment or
6688  * atomicity of device memory accesses. The recommended practice for writing
6689  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6690  * alt_write_word() functions.
6691  *
6692  * The struct declaration for register ALT_PINMUX_DCTD_IO_5.
6693  */
6694 struct ALT_PINMUX_DCTD_IO_5_s
6695 {
6696  uint32_t sel : 4; /* Dedicated IO 5 Mux Selection Field */
6697  const uint32_t Reserved : 28; /* ALT_PINMUX_DCTD_IO_5_RSVD */
6698 };
6699 
6700 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_5. */
6701 typedef volatile struct ALT_PINMUX_DCTD_IO_5_s ALT_PINMUX_DCTD_IO_5_t;
6702 #endif /* __ASSEMBLY__ */
6703 
6704 /* The reset value of the ALT_PINMUX_DCTD_IO_5 register. */
6705 #define ALT_PINMUX_DCTD_IO_5_RESET 0x0000000f
6706 /* The byte offset of the ALT_PINMUX_DCTD_IO_5 register from the beginning of the component. */
6707 #define ALT_PINMUX_DCTD_IO_5_OFST 0x10
6708 
6709 /*
6710  * Register : Dedicated IO 6 Mux Selection Register - pinmux_dedicated_io_6
6711  *
6712  * This register is used to control the peripherals connected to dedicated IO pin 6
6713  *
6714  * Only reset by a cold reset (ignores warm reset).
6715  *
6716  * NOTE: These registers should not be modified after IO configuration.There is no
6717  * support for dynamically changing the Pin Mux selections.
6718  *
6719  * Register Layout
6720  *
6721  * Bits | Access | Reset | Description
6722  * :-------|:-------|:------|:-----------------------------------
6723  * [3:0] | RW | 0xf | Dedicated IO 6 Mux Selection Field
6724  * [31:4] | R | 0x0 | ALT_PINMUX_DCTD_IO_6_RSVD
6725  *
6726  */
6727 /*
6728  * Field : Dedicated IO 6 Mux Selection Field - sel
6729  *
6730  * Select peripheral signals connected Dedicated IO 6
6731  *
6732  * 0000 (0) Pin is connected to Peripheral signal not applicable
6733  *
6734  * 0001 (1) Pin is connected to Peripheral signal not applicable
6735  *
6736  * 0010 (2) Pin is connected to Peripheral signal not applicable
6737  *
6738  * 0011 (3) Pin is connected to Peripheral signal not applicable
6739  *
6740  * 0100 (4) Pin is connected to Peripheral signal qspi.ss0
6741  *
6742  * 0101 (5) Pin is connected to Peripheral signal not applicable
6743  *
6744  * 0110 (6) Pin is connected to Peripheral signal not applicable
6745  *
6746  * 0111 (7) Pin is connected to Peripheral signal not applicable
6747  *
6748  * 1000 (8) Pin is connected to Peripheral signal sdmmc.cclk
6749  *
6750  * 1001 (9) Pin is connected to Peripheral signal not applicable
6751  *
6752  * 1010 (10) Pin is connected to Peripheral signal not applicable
6753  *
6754  * 1011 (11) Pin is connected to Peripheral signal not applicable
6755  *
6756  * 1100 (12) Pin is connected to Peripheral signal not applicable
6757  *
6758  * 1101 (13) Pin is connected to Peripheral signal not applicable
6759  *
6760  * 1110 (14) Pin is connected to Peripheral signal nand.we_n
6761  *
6762  * 1111 (15) Pin is connected to Peripheral signal gpio2.io2
6763  *
6764  * Field Access Macros:
6765  *
6766  */
6767 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_6_SEL register field. */
6768 #define ALT_PINMUX_DCTD_IO_6_SEL_LSB 0
6769 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_6_SEL register field. */
6770 #define ALT_PINMUX_DCTD_IO_6_SEL_MSB 3
6771 /* The width in bits of the ALT_PINMUX_DCTD_IO_6_SEL register field. */
6772 #define ALT_PINMUX_DCTD_IO_6_SEL_WIDTH 4
6773 /* The mask used to set the ALT_PINMUX_DCTD_IO_6_SEL register field value. */
6774 #define ALT_PINMUX_DCTD_IO_6_SEL_SET_MSK 0x0000000f
6775 /* The mask used to clear the ALT_PINMUX_DCTD_IO_6_SEL register field value. */
6776 #define ALT_PINMUX_DCTD_IO_6_SEL_CLR_MSK 0xfffffff0
6777 /* The reset value of the ALT_PINMUX_DCTD_IO_6_SEL register field. */
6778 #define ALT_PINMUX_DCTD_IO_6_SEL_RESET 0xf
6779 /* Extracts the ALT_PINMUX_DCTD_IO_6_SEL field value from a register. */
6780 #define ALT_PINMUX_DCTD_IO_6_SEL_GET(value) (((value) & 0x0000000f) >> 0)
6781 /* Produces a ALT_PINMUX_DCTD_IO_6_SEL register field value suitable for setting the register. */
6782 #define ALT_PINMUX_DCTD_IO_6_SEL_SET(value) (((value) << 0) & 0x0000000f)
6783 
6784 /*
6785  * Field : Reserved
6786  *
6787  * Reserved
6788  *
6789  * Field Access Macros:
6790  *
6791  */
6792 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_6_RSVD register field. */
6793 #define ALT_PINMUX_DCTD_IO_6_RSVD_LSB 4
6794 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_6_RSVD register field. */
6795 #define ALT_PINMUX_DCTD_IO_6_RSVD_MSB 31
6796 /* The width in bits of the ALT_PINMUX_DCTD_IO_6_RSVD register field. */
6797 #define ALT_PINMUX_DCTD_IO_6_RSVD_WIDTH 28
6798 /* The mask used to set the ALT_PINMUX_DCTD_IO_6_RSVD register field value. */
6799 #define ALT_PINMUX_DCTD_IO_6_RSVD_SET_MSK 0xfffffff0
6800 /* The mask used to clear the ALT_PINMUX_DCTD_IO_6_RSVD register field value. */
6801 #define ALT_PINMUX_DCTD_IO_6_RSVD_CLR_MSK 0x0000000f
6802 /* The reset value of the ALT_PINMUX_DCTD_IO_6_RSVD register field. */
6803 #define ALT_PINMUX_DCTD_IO_6_RSVD_RESET 0x0
6804 /* Extracts the ALT_PINMUX_DCTD_IO_6_RSVD field value from a register. */
6805 #define ALT_PINMUX_DCTD_IO_6_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
6806 /* Produces a ALT_PINMUX_DCTD_IO_6_RSVD register field value suitable for setting the register. */
6807 #define ALT_PINMUX_DCTD_IO_6_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
6808 
6809 #ifndef __ASSEMBLY__
6810 /*
6811  * WARNING: The C register and register group struct declarations are provided for
6812  * convenience and illustrative purposes. They should, however, be used with
6813  * caution as the C language standard provides no guarantees about the alignment or
6814  * atomicity of device memory accesses. The recommended practice for writing
6815  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6816  * alt_write_word() functions.
6817  *
6818  * The struct declaration for register ALT_PINMUX_DCTD_IO_6.
6819  */
6820 struct ALT_PINMUX_DCTD_IO_6_s
6821 {
6822  uint32_t sel : 4; /* Dedicated IO 6 Mux Selection Field */
6823  const uint32_t Reserved : 28; /* ALT_PINMUX_DCTD_IO_6_RSVD */
6824 };
6825 
6826 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_6. */
6827 typedef volatile struct ALT_PINMUX_DCTD_IO_6_s ALT_PINMUX_DCTD_IO_6_t;
6828 #endif /* __ASSEMBLY__ */
6829 
6830 /* The reset value of the ALT_PINMUX_DCTD_IO_6 register. */
6831 #define ALT_PINMUX_DCTD_IO_6_RESET 0x0000000f
6832 /* The byte offset of the ALT_PINMUX_DCTD_IO_6 register from the beginning of the component. */
6833 #define ALT_PINMUX_DCTD_IO_6_OFST 0x14
6834 
6835 /*
6836  * Register : Dedicated IO 7 Mux Selection Register - pinmux_dedicated_io_7
6837  *
6838  * This register is used to control the peripherals connected to dedicated IO pin 7
6839  *
6840  * Only reset by a cold reset (ignores warm reset).
6841  *
6842  * NOTE: These registers should not be modified after IO configuration.There is no
6843  * support for dynamically changing the Pin Mux selections.
6844  *
6845  * Register Layout
6846  *
6847  * Bits | Access | Reset | Description
6848  * :-------|:-------|:------|:-----------------------------------
6849  * [3:0] | RW | 0xf | Dedicated IO 7 Mux Selection Field
6850  * [31:4] | R | 0x0 | ALT_PINMUX_DCTD_IO_7_RSVD
6851  *
6852  */
6853 /*
6854  * Field : Dedicated IO 7 Mux Selection Field - sel
6855  *
6856  * Select peripheral signals connected Dedicated IO 7
6857  *
6858  * 0000 (0) Pin is connected to Peripheral signal not applicable
6859  *
6860  * 0001 (1) Pin is connected to Peripheral signal not applicable
6861  *
6862  * 0010 (2) Pin is connected to Peripheral signal not applicable
6863  *
6864  * 0011 (3) Pin is connected to Peripheral signal not applicable
6865  *
6866  * 0100 (4) Pin is connected to Peripheral signal qspi.io1
6867  *
6868  * 0101 (5) Pin is connected to Peripheral signal not applicable
6869  *
6870  * 0110 (6) Pin is connected to Peripheral signal not applicable
6871  *
6872  * 0111 (7) Pin is connected to Peripheral signal not applicable
6873  *
6874  * 1000 (8) Pin is connected to Peripheral signal sdmmc.data1
6875  *
6876  * 1001 (9) Pin is connected to Peripheral signal not applicable
6877  *
6878  * 1010 (10) Pin is connected to Peripheral signal not applicable
6879  *
6880  * 1011 (11) Pin is connected to Peripheral signal not applicable
6881  *
6882  * 1100 (12) Pin is connected to Peripheral signal not applicable
6883  *
6884  * 1101 (13) Pin is connected to Peripheral signal not applicable
6885  *
6886  * 1110 (14) Pin is connected to Peripheral signal nand.re_n
6887  *
6888  * 1111 (15) Pin is connected to Peripheral signal gpio2.io3
6889  *
6890  * Field Access Macros:
6891  *
6892  */
6893 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_7_SEL register field. */
6894 #define ALT_PINMUX_DCTD_IO_7_SEL_LSB 0
6895 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_7_SEL register field. */
6896 #define ALT_PINMUX_DCTD_IO_7_SEL_MSB 3
6897 /* The width in bits of the ALT_PINMUX_DCTD_IO_7_SEL register field. */
6898 #define ALT_PINMUX_DCTD_IO_7_SEL_WIDTH 4
6899 /* The mask used to set the ALT_PINMUX_DCTD_IO_7_SEL register field value. */
6900 #define ALT_PINMUX_DCTD_IO_7_SEL_SET_MSK 0x0000000f
6901 /* The mask used to clear the ALT_PINMUX_DCTD_IO_7_SEL register field value. */
6902 #define ALT_PINMUX_DCTD_IO_7_SEL_CLR_MSK 0xfffffff0
6903 /* The reset value of the ALT_PINMUX_DCTD_IO_7_SEL register field. */
6904 #define ALT_PINMUX_DCTD_IO_7_SEL_RESET 0xf
6905 /* Extracts the ALT_PINMUX_DCTD_IO_7_SEL field value from a register. */
6906 #define ALT_PINMUX_DCTD_IO_7_SEL_GET(value) (((value) & 0x0000000f) >> 0)
6907 /* Produces a ALT_PINMUX_DCTD_IO_7_SEL register field value suitable for setting the register. */
6908 #define ALT_PINMUX_DCTD_IO_7_SEL_SET(value) (((value) << 0) & 0x0000000f)
6909 
6910 /*
6911  * Field : Reserved
6912  *
6913  * Reserved
6914  *
6915  * Field Access Macros:
6916  *
6917  */
6918 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_7_RSVD register field. */
6919 #define ALT_PINMUX_DCTD_IO_7_RSVD_LSB 4
6920 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_7_RSVD register field. */
6921 #define ALT_PINMUX_DCTD_IO_7_RSVD_MSB 31
6922 /* The width in bits of the ALT_PINMUX_DCTD_IO_7_RSVD register field. */
6923 #define ALT_PINMUX_DCTD_IO_7_RSVD_WIDTH 28
6924 /* The mask used to set the ALT_PINMUX_DCTD_IO_7_RSVD register field value. */
6925 #define ALT_PINMUX_DCTD_IO_7_RSVD_SET_MSK 0xfffffff0
6926 /* The mask used to clear the ALT_PINMUX_DCTD_IO_7_RSVD register field value. */
6927 #define ALT_PINMUX_DCTD_IO_7_RSVD_CLR_MSK 0x0000000f
6928 /* The reset value of the ALT_PINMUX_DCTD_IO_7_RSVD register field. */
6929 #define ALT_PINMUX_DCTD_IO_7_RSVD_RESET 0x0
6930 /* Extracts the ALT_PINMUX_DCTD_IO_7_RSVD field value from a register. */
6931 #define ALT_PINMUX_DCTD_IO_7_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
6932 /* Produces a ALT_PINMUX_DCTD_IO_7_RSVD register field value suitable for setting the register. */
6933 #define ALT_PINMUX_DCTD_IO_7_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
6934 
6935 #ifndef __ASSEMBLY__
6936 /*
6937  * WARNING: The C register and register group struct declarations are provided for
6938  * convenience and illustrative purposes. They should, however, be used with
6939  * caution as the C language standard provides no guarantees about the alignment or
6940  * atomicity of device memory accesses. The recommended practice for writing
6941  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6942  * alt_write_word() functions.
6943  *
6944  * The struct declaration for register ALT_PINMUX_DCTD_IO_7.
6945  */
6946 struct ALT_PINMUX_DCTD_IO_7_s
6947 {
6948  uint32_t sel : 4; /* Dedicated IO 7 Mux Selection Field */
6949  const uint32_t Reserved : 28; /* ALT_PINMUX_DCTD_IO_7_RSVD */
6950 };
6951 
6952 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_7. */
6953 typedef volatile struct ALT_PINMUX_DCTD_IO_7_s ALT_PINMUX_DCTD_IO_7_t;
6954 #endif /* __ASSEMBLY__ */
6955 
6956 /* The reset value of the ALT_PINMUX_DCTD_IO_7 register. */
6957 #define ALT_PINMUX_DCTD_IO_7_RESET 0x0000000f
6958 /* The byte offset of the ALT_PINMUX_DCTD_IO_7 register from the beginning of the component. */
6959 #define ALT_PINMUX_DCTD_IO_7_OFST 0x18
6960 
6961 /*
6962  * Register : Dedicated IO 8 Mux Selection Register - pinmux_dedicated_io_8
6963  *
6964  * This register is used to control the peripherals connected to dedicated IO pin 8
6965  *
6966  * Only reset by a cold reset (ignores warm reset).
6967  *
6968  * NOTE: These registers should not be modified after IO configuration.There is no
6969  * support for dynamically changing the Pin Mux selections.
6970  *
6971  * Register Layout
6972  *
6973  * Bits | Access | Reset | Description
6974  * :-------|:-------|:------|:-----------------------------------
6975  * [3:0] | RW | 0xf | Dedicated IO 8 Mux Selection Field
6976  * [31:4] | R | 0x0 | ALT_PINMUX_DCTD_IO_8_RSVD
6977  *
6978  */
6979 /*
6980  * Field : Dedicated IO 8 Mux Selection Field - sel
6981  *
6982  * Select peripheral signals connected Dedicated IO 8
6983  *
6984  * 0000 (0) Pin is connected to Peripheral signal not applicable
6985  *
6986  * 0001 (1) Pin is connected to Peripheral signal not applicable
6987  *
6988  * 0010 (2) Pin is connected to Peripheral signal not applicable
6989  *
6990  * 0011 (3) Pin is connected to Peripheral signal not applicable
6991  *
6992  * 0100 (4) Pin is connected to Peripheral signal qspi.io2_wpn
6993  *
6994  * 0101 (5) Pin is connected to Peripheral signal not applicable
6995  *
6996  * 0110 (6) Pin is connected to Peripheral signal not applicable
6997  *
6998  * 0111 (7) Pin is connected to Peripheral signal not applicable
6999  *
7000  * 1000 (8) Pin is connected to Peripheral signal sdmmc.data2
7001  *
7002  * 1001 (9) Pin is connected to Peripheral signal not applicable
7003  *
7004  * 1010 (10) Pin is connected to Peripheral signal not applicable
7005  *
7006  * 1011 (11) Pin is connected to Peripheral signal not applicable
7007  *
7008  * 1100 (12) Pin is connected to Peripheral signal not applicable
7009  *
7010  * 1101 (13) Pin is connected to Peripheral signal not applicable
7011  *
7012  * 1110 (14) Pin is connected to Peripheral signal nand.adq2
7013  *
7014  * 1111 (15) Pin is connected to Peripheral signal gpio2.io4
7015  *
7016  * Field Access Macros:
7017  *
7018  */
7019 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_8_SEL register field. */
7020 #define ALT_PINMUX_DCTD_IO_8_SEL_LSB 0
7021 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_8_SEL register field. */
7022 #define ALT_PINMUX_DCTD_IO_8_SEL_MSB 3
7023 /* The width in bits of the ALT_PINMUX_DCTD_IO_8_SEL register field. */
7024 #define ALT_PINMUX_DCTD_IO_8_SEL_WIDTH 4
7025 /* The mask used to set the ALT_PINMUX_DCTD_IO_8_SEL register field value. */
7026 #define ALT_PINMUX_DCTD_IO_8_SEL_SET_MSK 0x0000000f
7027 /* The mask used to clear the ALT_PINMUX_DCTD_IO_8_SEL register field value. */
7028 #define ALT_PINMUX_DCTD_IO_8_SEL_CLR_MSK 0xfffffff0
7029 /* The reset value of the ALT_PINMUX_DCTD_IO_8_SEL register field. */
7030 #define ALT_PINMUX_DCTD_IO_8_SEL_RESET 0xf
7031 /* Extracts the ALT_PINMUX_DCTD_IO_8_SEL field value from a register. */
7032 #define ALT_PINMUX_DCTD_IO_8_SEL_GET(value) (((value) & 0x0000000f) >> 0)
7033 /* Produces a ALT_PINMUX_DCTD_IO_8_SEL register field value suitable for setting the register. */
7034 #define ALT_PINMUX_DCTD_IO_8_SEL_SET(value) (((value) << 0) & 0x0000000f)
7035 
7036 /*
7037  * Field : Reserved
7038  *
7039  * Reserved
7040  *
7041  * Field Access Macros:
7042  *
7043  */
7044 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_8_RSVD register field. */
7045 #define ALT_PINMUX_DCTD_IO_8_RSVD_LSB 4
7046 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_8_RSVD register field. */
7047 #define ALT_PINMUX_DCTD_IO_8_RSVD_MSB 31
7048 /* The width in bits of the ALT_PINMUX_DCTD_IO_8_RSVD register field. */
7049 #define ALT_PINMUX_DCTD_IO_8_RSVD_WIDTH 28
7050 /* The mask used to set the ALT_PINMUX_DCTD_IO_8_RSVD register field value. */
7051 #define ALT_PINMUX_DCTD_IO_8_RSVD_SET_MSK 0xfffffff0
7052 /* The mask used to clear the ALT_PINMUX_DCTD_IO_8_RSVD register field value. */
7053 #define ALT_PINMUX_DCTD_IO_8_RSVD_CLR_MSK 0x0000000f
7054 /* The reset value of the ALT_PINMUX_DCTD_IO_8_RSVD register field. */
7055 #define ALT_PINMUX_DCTD_IO_8_RSVD_RESET 0x0
7056 /* Extracts the ALT_PINMUX_DCTD_IO_8_RSVD field value from a register. */
7057 #define ALT_PINMUX_DCTD_IO_8_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
7058 /* Produces a ALT_PINMUX_DCTD_IO_8_RSVD register field value suitable for setting the register. */
7059 #define ALT_PINMUX_DCTD_IO_8_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
7060 
7061 #ifndef __ASSEMBLY__
7062 /*
7063  * WARNING: The C register and register group struct declarations are provided for
7064  * convenience and illustrative purposes. They should, however, be used with
7065  * caution as the C language standard provides no guarantees about the alignment or
7066  * atomicity of device memory accesses. The recommended practice for writing
7067  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7068  * alt_write_word() functions.
7069  *
7070  * The struct declaration for register ALT_PINMUX_DCTD_IO_8.
7071  */
7072 struct ALT_PINMUX_DCTD_IO_8_s
7073 {
7074  uint32_t sel : 4; /* Dedicated IO 8 Mux Selection Field */
7075  const uint32_t Reserved : 28; /* ALT_PINMUX_DCTD_IO_8_RSVD */
7076 };
7077 
7078 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_8. */
7079 typedef volatile struct ALT_PINMUX_DCTD_IO_8_s ALT_PINMUX_DCTD_IO_8_t;
7080 #endif /* __ASSEMBLY__ */
7081 
7082 /* The reset value of the ALT_PINMUX_DCTD_IO_8 register. */
7083 #define ALT_PINMUX_DCTD_IO_8_RESET 0x0000000f
7084 /* The byte offset of the ALT_PINMUX_DCTD_IO_8 register from the beginning of the component. */
7085 #define ALT_PINMUX_DCTD_IO_8_OFST 0x1c
7086 
7087 /*
7088  * Register : Dedicated IO 9 Mux Selection Register - pinmux_dedicated_io_9
7089  *
7090  * This register is used to control the peripherals connected to dedicated IO pin 9
7091  *
7092  * Only reset by a cold reset (ignores warm reset).
7093  *
7094  * NOTE: These registers should not be modified after IO configuration.There is no
7095  * support for dynamically changing the Pin Mux selections.
7096  *
7097  * Register Layout
7098  *
7099  * Bits | Access | Reset | Description
7100  * :-------|:-------|:------|:-----------------------------------
7101  * [3:0] | RW | 0xf | Dedicated IO 9 Mux Selection Field
7102  * [31:4] | R | 0x0 | ALT_PINMUX_DCTD_IO_9_RSVD
7103  *
7104  */
7105 /*
7106  * Field : Dedicated IO 9 Mux Selection Field - sel
7107  *
7108  * Select peripheral signals connected Dedicated IO 9
7109  *
7110  * 0000 (0) Pin is connected to Peripheral signal not applicable
7111  *
7112  * 0001 (1) Pin is connected to Peripheral signal not applicable
7113  *
7114  * 0010 (2) Pin is connected to Peripheral signal not applicable
7115  *
7116  * 0011 (3) Pin is connected to Peripheral signal not applicable
7117  *
7118  * 0100 (4) Pin is connected to Peripheral signal qspi.io3_hold
7119  *
7120  * 0101 (5) Pin is connected to Peripheral signal not applicable
7121  *
7122  * 0110 (6) Pin is connected to Peripheral signal not applicable
7123  *
7124  * 0111 (7) Pin is connected to Peripheral signal not applicable
7125  *
7126  * 1000 (8) Pin is connected to Peripheral signal sdmmc.data3
7127  *
7128  * 1001 (9) Pin is connected to Peripheral signal not applicable
7129  *
7130  * 1010 (10) Pin is connected to Peripheral signal not applicable
7131  *
7132  * 1011 (11) Pin is connected to Peripheral signal not applicable
7133  *
7134  * 1100 (12) Pin is connected to Peripheral signal not applicable
7135  *
7136  * 1101 (13) Pin is connected to Peripheral signal not applicable
7137  *
7138  * 1110 (14) Pin is connected to Peripheral signal nand.adq3
7139  *
7140  * 1111 (15) Pin is connected to Peripheral signal gpio2.io5
7141  *
7142  * Field Access Macros:
7143  *
7144  */
7145 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_9_SEL register field. */
7146 #define ALT_PINMUX_DCTD_IO_9_SEL_LSB 0
7147 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_9_SEL register field. */
7148 #define ALT_PINMUX_DCTD_IO_9_SEL_MSB 3
7149 /* The width in bits of the ALT_PINMUX_DCTD_IO_9_SEL register field. */
7150 #define ALT_PINMUX_DCTD_IO_9_SEL_WIDTH 4
7151 /* The mask used to set the ALT_PINMUX_DCTD_IO_9_SEL register field value. */
7152 #define ALT_PINMUX_DCTD_IO_9_SEL_SET_MSK 0x0000000f
7153 /* The mask used to clear the ALT_PINMUX_DCTD_IO_9_SEL register field value. */
7154 #define ALT_PINMUX_DCTD_IO_9_SEL_CLR_MSK 0xfffffff0
7155 /* The reset value of the ALT_PINMUX_DCTD_IO_9_SEL register field. */
7156 #define ALT_PINMUX_DCTD_IO_9_SEL_RESET 0xf
7157 /* Extracts the ALT_PINMUX_DCTD_IO_9_SEL field value from a register. */
7158 #define ALT_PINMUX_DCTD_IO_9_SEL_GET(value) (((value) & 0x0000000f) >> 0)
7159 /* Produces a ALT_PINMUX_DCTD_IO_9_SEL register field value suitable for setting the register. */
7160 #define ALT_PINMUX_DCTD_IO_9_SEL_SET(value) (((value) << 0) & 0x0000000f)
7161 
7162 /*
7163  * Field : Reserved
7164  *
7165  * Reserved
7166  *
7167  * Field Access Macros:
7168  *
7169  */
7170 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_9_RSVD register field. */
7171 #define ALT_PINMUX_DCTD_IO_9_RSVD_LSB 4
7172 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_9_RSVD register field. */
7173 #define ALT_PINMUX_DCTD_IO_9_RSVD_MSB 31
7174 /* The width in bits of the ALT_PINMUX_DCTD_IO_9_RSVD register field. */
7175 #define ALT_PINMUX_DCTD_IO_9_RSVD_WIDTH 28
7176 /* The mask used to set the ALT_PINMUX_DCTD_IO_9_RSVD register field value. */
7177 #define ALT_PINMUX_DCTD_IO_9_RSVD_SET_MSK 0xfffffff0
7178 /* The mask used to clear the ALT_PINMUX_DCTD_IO_9_RSVD register field value. */
7179 #define ALT_PINMUX_DCTD_IO_9_RSVD_CLR_MSK 0x0000000f
7180 /* The reset value of the ALT_PINMUX_DCTD_IO_9_RSVD register field. */
7181 #define ALT_PINMUX_DCTD_IO_9_RSVD_RESET 0x0
7182 /* Extracts the ALT_PINMUX_DCTD_IO_9_RSVD field value from a register. */
7183 #define ALT_PINMUX_DCTD_IO_9_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
7184 /* Produces a ALT_PINMUX_DCTD_IO_9_RSVD register field value suitable for setting the register. */
7185 #define ALT_PINMUX_DCTD_IO_9_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
7186 
7187 #ifndef __ASSEMBLY__
7188 /*
7189  * WARNING: The C register and register group struct declarations are provided for
7190  * convenience and illustrative purposes. They should, however, be used with
7191  * caution as the C language standard provides no guarantees about the alignment or
7192  * atomicity of device memory accesses. The recommended practice for writing
7193  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7194  * alt_write_word() functions.
7195  *
7196  * The struct declaration for register ALT_PINMUX_DCTD_IO_9.
7197  */
7198 struct ALT_PINMUX_DCTD_IO_9_s
7199 {
7200  uint32_t sel : 4; /* Dedicated IO 9 Mux Selection Field */
7201  const uint32_t Reserved : 28; /* ALT_PINMUX_DCTD_IO_9_RSVD */
7202 };
7203 
7204 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_9. */
7205 typedef volatile struct ALT_PINMUX_DCTD_IO_9_s ALT_PINMUX_DCTD_IO_9_t;
7206 #endif /* __ASSEMBLY__ */
7207 
7208 /* The reset value of the ALT_PINMUX_DCTD_IO_9 register. */
7209 #define ALT_PINMUX_DCTD_IO_9_RESET 0x0000000f
7210 /* The byte offset of the ALT_PINMUX_DCTD_IO_9 register from the beginning of the component. */
7211 #define ALT_PINMUX_DCTD_IO_9_OFST 0x20
7212 
7213 /*
7214  * Register : Dedicated IO 10 Mux Selection Register - pinmux_dedicated_io_10
7215  *
7216  * This register is used to control the peripherals connected to dedicated IO pin
7217  * 10
7218  *
7219  * Only reset by a cold reset (ignores warm reset).
7220  *
7221  * NOTE: These registers should not be modified after IO configuration.There is no
7222  * support for dynamically changing the Pin Mux selections.
7223  *
7224  * Register Layout
7225  *
7226  * Bits | Access | Reset | Description
7227  * :-------|:-------|:------|:------------------------------------
7228  * [3:0] | RW | 0xf | Dedicated IO 10 Mux Selection Field
7229  * [31:4] | R | 0x0 | ALT_PINMUX_DCTD_IO_10_RSVD
7230  *
7231  */
7232 /*
7233  * Field : Dedicated IO 10 Mux Selection Field - sel
7234  *
7235  * Select peripheral signals connected Dedicated IO 10
7236  *
7237  * 0000 (0) Pin is connected to Peripheral signal not applicable
7238  *
7239  * 0001 (1) Pin is connected to Peripheral signal not applicable
7240  *
7241  * 0010 (2) Pin is connected to Peripheral signal spis0.miso
7242  *
7243  * 0011 (3) Pin is connected to Peripheral signal spim0.ss1_n
7244  *
7245  * 0100 (4) Pin is connected to Peripheral signal not applicable
7246  *
7247  * 0101 (5) Pin is connected to Peripheral signal not applicable
7248  *
7249  * 0110 (6) Pin is connected to Peripheral signal not applicable
7250  *
7251  * 0111 (7) Pin is connected to Peripheral signal not applicable
7252  *
7253  * 1000 (8) Pin is connected to Peripheral signal sdmmc.pwr_ena
7254  *
7255  * 1001 (9) Pin is connected to Peripheral signal not applicable
7256  *
7257  * 1010 (10) Pin is connected to Peripheral signal not applicable
7258  *
7259  * 1011 (11) Pin is connected to Peripheral signal not applicable
7260  *
7261  * 1100 (12) Pin is connected to Peripheral signal not applicable
7262  *
7263  * 1101 (13) Pin is connected to Peripheral signal not applicable
7264  *
7265  * 1110 (14) Pin is connected to Peripheral signal nand.cle
7266  *
7267  * 1111 (15) Pin is connected to Peripheral signal gpio2.io6
7268  *
7269  * Field Access Macros:
7270  *
7271  */
7272 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_10_SEL register field. */
7273 #define ALT_PINMUX_DCTD_IO_10_SEL_LSB 0
7274 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_10_SEL register field. */
7275 #define ALT_PINMUX_DCTD_IO_10_SEL_MSB 3
7276 /* The width in bits of the ALT_PINMUX_DCTD_IO_10_SEL register field. */
7277 #define ALT_PINMUX_DCTD_IO_10_SEL_WIDTH 4
7278 /* The mask used to set the ALT_PINMUX_DCTD_IO_10_SEL register field value. */
7279 #define ALT_PINMUX_DCTD_IO_10_SEL_SET_MSK 0x0000000f
7280 /* The mask used to clear the ALT_PINMUX_DCTD_IO_10_SEL register field value. */
7281 #define ALT_PINMUX_DCTD_IO_10_SEL_CLR_MSK 0xfffffff0
7282 /* The reset value of the ALT_PINMUX_DCTD_IO_10_SEL register field. */
7283 #define ALT_PINMUX_DCTD_IO_10_SEL_RESET 0xf
7284 /* Extracts the ALT_PINMUX_DCTD_IO_10_SEL field value from a register. */
7285 #define ALT_PINMUX_DCTD_IO_10_SEL_GET(value) (((value) & 0x0000000f) >> 0)
7286 /* Produces a ALT_PINMUX_DCTD_IO_10_SEL register field value suitable for setting the register. */
7287 #define ALT_PINMUX_DCTD_IO_10_SEL_SET(value) (((value) << 0) & 0x0000000f)
7288 
7289 /*
7290  * Field : Reserved
7291  *
7292  * Reserved
7293  *
7294  * Field Access Macros:
7295  *
7296  */
7297 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_10_RSVD register field. */
7298 #define ALT_PINMUX_DCTD_IO_10_RSVD_LSB 4
7299 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_10_RSVD register field. */
7300 #define ALT_PINMUX_DCTD_IO_10_RSVD_MSB 31
7301 /* The width in bits of the ALT_PINMUX_DCTD_IO_10_RSVD register field. */
7302 #define ALT_PINMUX_DCTD_IO_10_RSVD_WIDTH 28
7303 /* The mask used to set the ALT_PINMUX_DCTD_IO_10_RSVD register field value. */
7304 #define ALT_PINMUX_DCTD_IO_10_RSVD_SET_MSK 0xfffffff0
7305 /* The mask used to clear the ALT_PINMUX_DCTD_IO_10_RSVD register field value. */
7306 #define ALT_PINMUX_DCTD_IO_10_RSVD_CLR_MSK 0x0000000f
7307 /* The reset value of the ALT_PINMUX_DCTD_IO_10_RSVD register field. */
7308 #define ALT_PINMUX_DCTD_IO_10_RSVD_RESET 0x0
7309 /* Extracts the ALT_PINMUX_DCTD_IO_10_RSVD field value from a register. */
7310 #define ALT_PINMUX_DCTD_IO_10_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
7311 /* Produces a ALT_PINMUX_DCTD_IO_10_RSVD register field value suitable for setting the register. */
7312 #define ALT_PINMUX_DCTD_IO_10_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
7313 
7314 #ifndef __ASSEMBLY__
7315 /*
7316  * WARNING: The C register and register group struct declarations are provided for
7317  * convenience and illustrative purposes. They should, however, be used with
7318  * caution as the C language standard provides no guarantees about the alignment or
7319  * atomicity of device memory accesses. The recommended practice for writing
7320  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7321  * alt_write_word() functions.
7322  *
7323  * The struct declaration for register ALT_PINMUX_DCTD_IO_10.
7324  */
7325 struct ALT_PINMUX_DCTD_IO_10_s
7326 {
7327  uint32_t sel : 4; /* Dedicated IO 10 Mux Selection Field */
7328  const uint32_t Reserved : 28; /* ALT_PINMUX_DCTD_IO_10_RSVD */
7329 };
7330 
7331 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_10. */
7332 typedef volatile struct ALT_PINMUX_DCTD_IO_10_s ALT_PINMUX_DCTD_IO_10_t;
7333 #endif /* __ASSEMBLY__ */
7334 
7335 /* The reset value of the ALT_PINMUX_DCTD_IO_10 register. */
7336 #define ALT_PINMUX_DCTD_IO_10_RESET 0x0000000f
7337 /* The byte offset of the ALT_PINMUX_DCTD_IO_10 register from the beginning of the component. */
7338 #define ALT_PINMUX_DCTD_IO_10_OFST 0x24
7339 
7340 /*
7341  * Register : Dedicated IO 11 Mux Selection Register - pinmux_dedicated_io_11
7342  *
7343  * This register is used to control the peripherals connected to dedicated IO pin
7344  * 11
7345  *
7346  * Only reset by a cold reset (ignores warm reset).
7347  *
7348  * NOTE: These registers should not be modified after IO configuration.There is no
7349  * support for dynamically changing the Pin Mux selections.
7350  *
7351  * Register Layout
7352  *
7353  * Bits | Access | Reset | Description
7354  * :-------|:-------|:------|:------------------------------------
7355  * [3:0] | RW | 0xf | Dedicated IO 11 Mux Selection Field
7356  * [31:4] | R | 0x0 | ALT_PINMUX_DCTD_IO_11_RSVD
7357  *
7358  */
7359 /*
7360  * Field : Dedicated IO 11 Mux Selection Field - sel
7361  *
7362  * Select peripheral signals connected Dedicated IO 11
7363  *
7364  * 0000 (0) Pin is connected to Peripheral signal not applicable
7365  *
7366  * 0001 (1) Pin is connected to Peripheral signal not applicable
7367  *
7368  * 0010 (2) Pin is connected to Peripheral signal not applicable
7369  *
7370  * 0011 (3) Pin is connected to Peripheral signal spim0.clk
7371  *
7372  * 0100 (4) Pin is connected to Peripheral signal cm.pll_clk0
7373  *
7374  * 0101 (5) Pin is connected to Peripheral signal not applicable
7375  *
7376  * 0110 (6) Pin is connected to Peripheral signal not applicable
7377  *
7378  * 0111 (7) Pin is connected to Peripheral signal not applicable
7379  *
7380  * 1000 (8) Pin is connected to Peripheral signal qspi.ss1
7381  *
7382  * 1001 (9) Pin is connected to Peripheral signal not applicable
7383  *
7384  * 1010 (10) Pin is connected to Peripheral signal not applicable
7385  *
7386  * 1011 (11) Pin is connected to Peripheral signal not applicable
7387  *
7388  * 1100 (12) Pin is connected to Peripheral signal not applicable
7389  *
7390  * 1101 (13) Pin is connected to Peripheral signal not applicable
7391  *
7392  * 1110 (14) Pin is connected to Peripheral signal nand.ale
7393  *
7394  * 1111 (15) Pin is connected to Peripheral signal gpio2.io7
7395  *
7396  * Field Access Macros:
7397  *
7398  */
7399 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_11_SEL register field. */
7400 #define ALT_PINMUX_DCTD_IO_11_SEL_LSB 0
7401 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_11_SEL register field. */
7402 #define ALT_PINMUX_DCTD_IO_11_SEL_MSB 3
7403 /* The width in bits of the ALT_PINMUX_DCTD_IO_11_SEL register field. */
7404 #define ALT_PINMUX_DCTD_IO_11_SEL_WIDTH 4
7405 /* The mask used to set the ALT_PINMUX_DCTD_IO_11_SEL register field value. */
7406 #define ALT_PINMUX_DCTD_IO_11_SEL_SET_MSK 0x0000000f
7407 /* The mask used to clear the ALT_PINMUX_DCTD_IO_11_SEL register field value. */
7408 #define ALT_PINMUX_DCTD_IO_11_SEL_CLR_MSK 0xfffffff0
7409 /* The reset value of the ALT_PINMUX_DCTD_IO_11_SEL register field. */
7410 #define ALT_PINMUX_DCTD_IO_11_SEL_RESET 0xf
7411 /* Extracts the ALT_PINMUX_DCTD_IO_11_SEL field value from a register. */
7412 #define ALT_PINMUX_DCTD_IO_11_SEL_GET(value) (((value) & 0x0000000f) >> 0)
7413 /* Produces a ALT_PINMUX_DCTD_IO_11_SEL register field value suitable for setting the register. */
7414 #define ALT_PINMUX_DCTD_IO_11_SEL_SET(value) (((value) << 0) & 0x0000000f)
7415 
7416 /*
7417  * Field : Reserved
7418  *
7419  * Reserved
7420  *
7421  * Field Access Macros:
7422  *
7423  */
7424 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_11_RSVD register field. */
7425 #define ALT_PINMUX_DCTD_IO_11_RSVD_LSB 4
7426 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_11_RSVD register field. */
7427 #define ALT_PINMUX_DCTD_IO_11_RSVD_MSB 31
7428 /* The width in bits of the ALT_PINMUX_DCTD_IO_11_RSVD register field. */
7429 #define ALT_PINMUX_DCTD_IO_11_RSVD_WIDTH 28
7430 /* The mask used to set the ALT_PINMUX_DCTD_IO_11_RSVD register field value. */
7431 #define ALT_PINMUX_DCTD_IO_11_RSVD_SET_MSK 0xfffffff0
7432 /* The mask used to clear the ALT_PINMUX_DCTD_IO_11_RSVD register field value. */
7433 #define ALT_PINMUX_DCTD_IO_11_RSVD_CLR_MSK 0x0000000f
7434 /* The reset value of the ALT_PINMUX_DCTD_IO_11_RSVD register field. */
7435 #define ALT_PINMUX_DCTD_IO_11_RSVD_RESET 0x0
7436 /* Extracts the ALT_PINMUX_DCTD_IO_11_RSVD field value from a register. */
7437 #define ALT_PINMUX_DCTD_IO_11_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
7438 /* Produces a ALT_PINMUX_DCTD_IO_11_RSVD register field value suitable for setting the register. */
7439 #define ALT_PINMUX_DCTD_IO_11_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
7440 
7441 #ifndef __ASSEMBLY__
7442 /*
7443  * WARNING: The C register and register group struct declarations are provided for
7444  * convenience and illustrative purposes. They should, however, be used with
7445  * caution as the C language standard provides no guarantees about the alignment or
7446  * atomicity of device memory accesses. The recommended practice for writing
7447  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7448  * alt_write_word() functions.
7449  *
7450  * The struct declaration for register ALT_PINMUX_DCTD_IO_11.
7451  */
7452 struct ALT_PINMUX_DCTD_IO_11_s
7453 {
7454  uint32_t sel : 4; /* Dedicated IO 11 Mux Selection Field */
7455  const uint32_t Reserved : 28; /* ALT_PINMUX_DCTD_IO_11_RSVD */
7456 };
7457 
7458 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_11. */
7459 typedef volatile struct ALT_PINMUX_DCTD_IO_11_s ALT_PINMUX_DCTD_IO_11_t;
7460 #endif /* __ASSEMBLY__ */
7461 
7462 /* The reset value of the ALT_PINMUX_DCTD_IO_11 register. */
7463 #define ALT_PINMUX_DCTD_IO_11_RESET 0x0000000f
7464 /* The byte offset of the ALT_PINMUX_DCTD_IO_11 register from the beginning of the component. */
7465 #define ALT_PINMUX_DCTD_IO_11_OFST 0x28
7466 
7467 /*
7468  * Register : Dedicated IO 12 Mux Selection Register - pinmux_dedicated_io_12
7469  *
7470  * This register is used to control the peripherals connected to dedicated IO pin
7471  * 12
7472  *
7473  * Only reset by a cold reset (ignores warm reset).
7474  *
7475  * NOTE: These registers should not be modified after IO configuration.There is no
7476  * support for dynamically changing the Pin Mux selections.
7477  *
7478  * Register Layout
7479  *
7480  * Bits | Access | Reset | Description
7481  * :-------|:-------|:------|:------------------------------------
7482  * [3:0] | RW | 0xf | Dedicated IO 12 Mux Selection Field
7483  * [31:4] | R | 0x0 | ALT_PINMUX_DCTD_IO_12_RSVD
7484  *
7485  */
7486 /*
7487  * Field : Dedicated IO 12 Mux Selection Field - sel
7488  *
7489  * Select peripheral signals connected Dedicated IO 12
7490  *
7491  * 0000 (0) Pin is connected to Peripheral signal i2c_emac1.sda
7492  *
7493  * 0001 (1) Pin is connected to Peripheral signal emac1.mdio
7494  *
7495  * 0010 (2) Pin is connected to Peripheral signal not applicable
7496  *
7497  * 0011 (3) Pin is connected to Peripheral signal spim0.mosi
7498  *
7499  * 0100 (4) Pin is connected to Peripheral signal cm.pll_clk1
7500  *
7501  * 0101 (5) Pin is connected to Peripheral signal not applicable
7502  *
7503  * 0110 (6) Pin is connected to Peripheral signal not applicable
7504  *
7505  * 0111 (7) Pin is connected to Peripheral signal not applicable
7506  *
7507  * 1000 (8) Pin is connected to Peripheral signal sdmmc.data4
7508  *
7509  * 1001 (9) Pin is connected to Peripheral signal not applicable
7510  *
7511  * 1010 (10) Pin is connected to Peripheral signal not applicable
7512  *
7513  * 1011 (11) Pin is connected to Peripheral signal not applicable
7514  *
7515  * 1100 (12) Pin is connected to Peripheral signal not applicable
7516  *
7517  * 1101 (13) Pin is connected to Peripheral signal uart1.tx
7518  *
7519  * 1110 (14) Pin is connected to Peripheral signal nand.rb
7520  *
7521  * 1111 (15) Pin is connected to Peripheral signal gpio2.io8
7522  *
7523  * Field Access Macros:
7524  *
7525  */
7526 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_12_SEL register field. */
7527 #define ALT_PINMUX_DCTD_IO_12_SEL_LSB 0
7528 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_12_SEL register field. */
7529 #define ALT_PINMUX_DCTD_IO_12_SEL_MSB 3
7530 /* The width in bits of the ALT_PINMUX_DCTD_IO_12_SEL register field. */
7531 #define ALT_PINMUX_DCTD_IO_12_SEL_WIDTH 4
7532 /* The mask used to set the ALT_PINMUX_DCTD_IO_12_SEL register field value. */
7533 #define ALT_PINMUX_DCTD_IO_12_SEL_SET_MSK 0x0000000f
7534 /* The mask used to clear the ALT_PINMUX_DCTD_IO_12_SEL register field value. */
7535 #define ALT_PINMUX_DCTD_IO_12_SEL_CLR_MSK 0xfffffff0
7536 /* The reset value of the ALT_PINMUX_DCTD_IO_12_SEL register field. */
7537 #define ALT_PINMUX_DCTD_IO_12_SEL_RESET 0xf
7538 /* Extracts the ALT_PINMUX_DCTD_IO_12_SEL field value from a register. */
7539 #define ALT_PINMUX_DCTD_IO_12_SEL_GET(value) (((value) & 0x0000000f) >> 0)
7540 /* Produces a ALT_PINMUX_DCTD_IO_12_SEL register field value suitable for setting the register. */
7541 #define ALT_PINMUX_DCTD_IO_12_SEL_SET(value) (((value) << 0) & 0x0000000f)
7542 
7543 /*
7544  * Field : Reserved
7545  *
7546  * Reserved
7547  *
7548  * Field Access Macros:
7549  *
7550  */
7551 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_12_RSVD register field. */
7552 #define ALT_PINMUX_DCTD_IO_12_RSVD_LSB 4
7553 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_12_RSVD register field. */
7554 #define ALT_PINMUX_DCTD_IO_12_RSVD_MSB 31
7555 /* The width in bits of the ALT_PINMUX_DCTD_IO_12_RSVD register field. */
7556 #define ALT_PINMUX_DCTD_IO_12_RSVD_WIDTH 28
7557 /* The mask used to set the ALT_PINMUX_DCTD_IO_12_RSVD register field value. */
7558 #define ALT_PINMUX_DCTD_IO_12_RSVD_SET_MSK 0xfffffff0
7559 /* The mask used to clear the ALT_PINMUX_DCTD_IO_12_RSVD register field value. */
7560 #define ALT_PINMUX_DCTD_IO_12_RSVD_CLR_MSK 0x0000000f
7561 /* The reset value of the ALT_PINMUX_DCTD_IO_12_RSVD register field. */
7562 #define ALT_PINMUX_DCTD_IO_12_RSVD_RESET 0x0
7563 /* Extracts the ALT_PINMUX_DCTD_IO_12_RSVD field value from a register. */
7564 #define ALT_PINMUX_DCTD_IO_12_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
7565 /* Produces a ALT_PINMUX_DCTD_IO_12_RSVD register field value suitable for setting the register. */
7566 #define ALT_PINMUX_DCTD_IO_12_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
7567 
7568 #ifndef __ASSEMBLY__
7569 /*
7570  * WARNING: The C register and register group struct declarations are provided for
7571  * convenience and illustrative purposes. They should, however, be used with
7572  * caution as the C language standard provides no guarantees about the alignment or
7573  * atomicity of device memory accesses. The recommended practice for writing
7574  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7575  * alt_write_word() functions.
7576  *
7577  * The struct declaration for register ALT_PINMUX_DCTD_IO_12.
7578  */
7579 struct ALT_PINMUX_DCTD_IO_12_s
7580 {
7581  uint32_t sel : 4; /* Dedicated IO 12 Mux Selection Field */
7582  const uint32_t Reserved : 28; /* ALT_PINMUX_DCTD_IO_12_RSVD */
7583 };
7584 
7585 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_12. */
7586 typedef volatile struct ALT_PINMUX_DCTD_IO_12_s ALT_PINMUX_DCTD_IO_12_t;
7587 #endif /* __ASSEMBLY__ */
7588 
7589 /* The reset value of the ALT_PINMUX_DCTD_IO_12 register. */
7590 #define ALT_PINMUX_DCTD_IO_12_RESET 0x0000000f
7591 /* The byte offset of the ALT_PINMUX_DCTD_IO_12 register from the beginning of the component. */
7592 #define ALT_PINMUX_DCTD_IO_12_OFST 0x2c
7593 
7594 /*
7595  * Register : Dedicated IO 13 Mux Selection Register - pinmux_dedicated_io_13
7596  *
7597  * This register is used to control the peripherals connected to dedicated IO pin
7598  * 13
7599  *
7600  * Only reset by a cold reset (ignores warm reset).
7601  *
7602  * NOTE: These registers should not be modified after IO configuration.There is no
7603  * support for dynamically changing the Pin Mux selections.
7604  *
7605  * Register Layout
7606  *
7607  * Bits | Access | Reset | Description
7608  * :-------|:-------|:------|:------------------------------------
7609  * [3:0] | RW | 0xf | Dedicated IO 13 Mux Selection Field
7610  * [31:4] | R | 0x0 | ALT_PINMUX_DCTD_IO_13_RSVD
7611  *
7612  */
7613 /*
7614  * Field : Dedicated IO 13 Mux Selection Field - sel
7615  *
7616  * Select peripheral signals connected Dedicated IO 13
7617  *
7618  * 0000 (0) Pin is connected to Peripheral signal i2c_emac1.scl
7619  *
7620  * 0001 (1) Pin is connected to Peripheral signal emac1.mdc
7621  *
7622  * 0010 (2) Pin is connected to Peripheral signal not applicable
7623  *
7624  * 0011 (3) Pin is connected to Peripheral signal spim0.miso
7625  *
7626  * 0100 (4) Pin is connected to Peripheral signal cm.pll_clk2
7627  *
7628  * 0101 (5) Pin is connected to Peripheral signal not applicable
7629  *
7630  * 0110 (6) Pin is connected to Peripheral signal not applicable
7631  *
7632  * 0111 (7) Pin is connected to Peripheral signal not applicable
7633  *
7634  * 1000 (8) Pin is connected to Peripheral signal sdmmc.data5
7635  *
7636  * 1001 (9) Pin is connected to Peripheral signal not applicable
7637  *
7638  * 1010 (10) Pin is connected to Peripheral signal not applicable
7639  *
7640  * 1011 (11) Pin is connected to Peripheral signal not applicable
7641  *
7642  * 1100 (12) Pin is connected to Peripheral signal not applicable
7643  *
7644  * 1101 (13) Pin is connected to Peripheral signal uart1.rts_n
7645  *
7646  * 1110 (14) Pin is connected to Peripheral signal nand.ce_n
7647  *
7648  * 1111 (15) Pin is connected to Peripheral signal gpio2.io9
7649  *
7650  * Field Access Macros:
7651  *
7652  */
7653 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_13_SEL register field. */
7654 #define ALT_PINMUX_DCTD_IO_13_SEL_LSB 0
7655 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_13_SEL register field. */
7656 #define ALT_PINMUX_DCTD_IO_13_SEL_MSB 3
7657 /* The width in bits of the ALT_PINMUX_DCTD_IO_13_SEL register field. */
7658 #define ALT_PINMUX_DCTD_IO_13_SEL_WIDTH 4
7659 /* The mask used to set the ALT_PINMUX_DCTD_IO_13_SEL register field value. */
7660 #define ALT_PINMUX_DCTD_IO_13_SEL_SET_MSK 0x0000000f
7661 /* The mask used to clear the ALT_PINMUX_DCTD_IO_13_SEL register field value. */
7662 #define ALT_PINMUX_DCTD_IO_13_SEL_CLR_MSK 0xfffffff0
7663 /* The reset value of the ALT_PINMUX_DCTD_IO_13_SEL register field. */
7664 #define ALT_PINMUX_DCTD_IO_13_SEL_RESET 0xf
7665 /* Extracts the ALT_PINMUX_DCTD_IO_13_SEL field value from a register. */
7666 #define ALT_PINMUX_DCTD_IO_13_SEL_GET(value) (((value) & 0x0000000f) >> 0)
7667 /* Produces a ALT_PINMUX_DCTD_IO_13_SEL register field value suitable for setting the register. */
7668 #define ALT_PINMUX_DCTD_IO_13_SEL_SET(value) (((value) << 0) & 0x0000000f)
7669 
7670 /*
7671  * Field : Reserved
7672  *
7673  * Reserved
7674  *
7675  * Field Access Macros:
7676  *
7677  */
7678 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_13_RSVD register field. */
7679 #define ALT_PINMUX_DCTD_IO_13_RSVD_LSB 4
7680 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_13_RSVD register field. */
7681 #define ALT_PINMUX_DCTD_IO_13_RSVD_MSB 31
7682 /* The width in bits of the ALT_PINMUX_DCTD_IO_13_RSVD register field. */
7683 #define ALT_PINMUX_DCTD_IO_13_RSVD_WIDTH 28
7684 /* The mask used to set the ALT_PINMUX_DCTD_IO_13_RSVD register field value. */
7685 #define ALT_PINMUX_DCTD_IO_13_RSVD_SET_MSK 0xfffffff0
7686 /* The mask used to clear the ALT_PINMUX_DCTD_IO_13_RSVD register field value. */
7687 #define ALT_PINMUX_DCTD_IO_13_RSVD_CLR_MSK 0x0000000f
7688 /* The reset value of the ALT_PINMUX_DCTD_IO_13_RSVD register field. */
7689 #define ALT_PINMUX_DCTD_IO_13_RSVD_RESET 0x0
7690 /* Extracts the ALT_PINMUX_DCTD_IO_13_RSVD field value from a register. */
7691 #define ALT_PINMUX_DCTD_IO_13_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
7692 /* Produces a ALT_PINMUX_DCTD_IO_13_RSVD register field value suitable for setting the register. */
7693 #define ALT_PINMUX_DCTD_IO_13_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
7694 
7695 #ifndef __ASSEMBLY__
7696 /*
7697  * WARNING: The C register and register group struct declarations are provided for
7698  * convenience and illustrative purposes. They should, however, be used with
7699  * caution as the C language standard provides no guarantees about the alignment or
7700  * atomicity of device memory accesses. The recommended practice for writing
7701  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7702  * alt_write_word() functions.
7703  *
7704  * The struct declaration for register ALT_PINMUX_DCTD_IO_13.
7705  */
7706 struct ALT_PINMUX_DCTD_IO_13_s
7707 {
7708  uint32_t sel : 4; /* Dedicated IO 13 Mux Selection Field */
7709  const uint32_t Reserved : 28; /* ALT_PINMUX_DCTD_IO_13_RSVD */
7710 };
7711 
7712 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_13. */
7713 typedef volatile struct ALT_PINMUX_DCTD_IO_13_s ALT_PINMUX_DCTD_IO_13_t;
7714 #endif /* __ASSEMBLY__ */
7715 
7716 /* The reset value of the ALT_PINMUX_DCTD_IO_13 register. */
7717 #define ALT_PINMUX_DCTD_IO_13_RESET 0x0000000f
7718 /* The byte offset of the ALT_PINMUX_DCTD_IO_13 register from the beginning of the component. */
7719 #define ALT_PINMUX_DCTD_IO_13_OFST 0x30
7720 
7721 /*
7722  * Register : Dedicated IO 14 Mux Selection Register - pinmux_dedicated_io_14
7723  *
7724  * This register is used to control the peripherals connected to dedicated IO pin
7725  * 14
7726  *
7727  * Only reset by a cold reset (ignores warm reset).
7728  *
7729  * NOTE: These registers should not be modified after IO configuration.There is no
7730  * support for dynamically changing the Pin Mux selections.
7731  *
7732  * Register Layout
7733  *
7734  * Bits | Access | Reset | Description
7735  * :-------|:-------|:------|:------------------------------------
7736  * [3:0] | RW | 0xf | Dedicated IO 14 Mux Selection Field
7737  * [31:4] | R | 0x0 | ALT_PINMUX_DCTD_IO_14_RSVD
7738  *
7739  */
7740 /*
7741  * Field : Dedicated IO 14 Mux Selection Field - sel
7742  *
7743  * Select peripheral signals connected Dedicated IO 14
7744  *
7745  * 0000 (0) Pin is connected to Peripheral signal i2c_emac2.sda
7746  *
7747  * 0001 (1) Pin is connected to Peripheral signal emac2.mdio
7748  *
7749  * 0010 (2) Pin is connected to Peripheral signal not applicable
7750  *
7751  * 0011 (3) Pin is connected to Peripheral signal spim0.ss0_n
7752  *
7753  * 0100 (4) Pin is connected to Peripheral signal cm.pll_clk3
7754  *
7755  * 0101 (5) Pin is connected to Peripheral signal not applicable
7756  *
7757  * 0110 (6) Pin is connected to Peripheral signal not applicable
7758  *
7759  * 0111 (7) Pin is connected to Peripheral signal not applicable
7760  *
7761  * 1000 (8) Pin is connected to Peripheral signal sdmmc.data6
7762  *
7763  * 1001 (9) Pin is connected to Peripheral signal not applicable
7764  *
7765  * 1010 (10) Pin is connected to Peripheral signal not applicable
7766  *
7767  * 1011 (11) Pin is connected to Peripheral signal not applicable
7768  *
7769  * 1100 (12) Pin is connected to Peripheral signal not applicable
7770  *
7771  * 1101 (13) Pin is connected to Peripheral signal uart1.cts_n
7772  *
7773  * 1110 (14) Pin is connected to Peripheral signal nand.adq4
7774  *
7775  * 1111 (15) Pin is connected to Peripheral signal gpio2.io10
7776  *
7777  * Field Access Macros:
7778  *
7779  */
7780 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_14_SEL register field. */
7781 #define ALT_PINMUX_DCTD_IO_14_SEL_LSB 0
7782 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_14_SEL register field. */
7783 #define ALT_PINMUX_DCTD_IO_14_SEL_MSB 3
7784 /* The width in bits of the ALT_PINMUX_DCTD_IO_14_SEL register field. */
7785 #define ALT_PINMUX_DCTD_IO_14_SEL_WIDTH 4
7786 /* The mask used to set the ALT_PINMUX_DCTD_IO_14_SEL register field value. */
7787 #define ALT_PINMUX_DCTD_IO_14_SEL_SET_MSK 0x0000000f
7788 /* The mask used to clear the ALT_PINMUX_DCTD_IO_14_SEL register field value. */
7789 #define ALT_PINMUX_DCTD_IO_14_SEL_CLR_MSK 0xfffffff0
7790 /* The reset value of the ALT_PINMUX_DCTD_IO_14_SEL register field. */
7791 #define ALT_PINMUX_DCTD_IO_14_SEL_RESET 0xf
7792 /* Extracts the ALT_PINMUX_DCTD_IO_14_SEL field value from a register. */
7793 #define ALT_PINMUX_DCTD_IO_14_SEL_GET(value) (((value) & 0x0000000f) >> 0)
7794 /* Produces a ALT_PINMUX_DCTD_IO_14_SEL register field value suitable for setting the register. */
7795 #define ALT_PINMUX_DCTD_IO_14_SEL_SET(value) (((value) << 0) & 0x0000000f)
7796 
7797 /*
7798  * Field : Reserved
7799  *
7800  * Reserved
7801  *
7802  * Field Access Macros:
7803  *
7804  */
7805 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_14_RSVD register field. */
7806 #define ALT_PINMUX_DCTD_IO_14_RSVD_LSB 4
7807 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_14_RSVD register field. */
7808 #define ALT_PINMUX_DCTD_IO_14_RSVD_MSB 31
7809 /* The width in bits of the ALT_PINMUX_DCTD_IO_14_RSVD register field. */
7810 #define ALT_PINMUX_DCTD_IO_14_RSVD_WIDTH 28
7811 /* The mask used to set the ALT_PINMUX_DCTD_IO_14_RSVD register field value. */
7812 #define ALT_PINMUX_DCTD_IO_14_RSVD_SET_MSK 0xfffffff0
7813 /* The mask used to clear the ALT_PINMUX_DCTD_IO_14_RSVD register field value. */
7814 #define ALT_PINMUX_DCTD_IO_14_RSVD_CLR_MSK 0x0000000f
7815 /* The reset value of the ALT_PINMUX_DCTD_IO_14_RSVD register field. */
7816 #define ALT_PINMUX_DCTD_IO_14_RSVD_RESET 0x0
7817 /* Extracts the ALT_PINMUX_DCTD_IO_14_RSVD field value from a register. */
7818 #define ALT_PINMUX_DCTD_IO_14_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
7819 /* Produces a ALT_PINMUX_DCTD_IO_14_RSVD register field value suitable for setting the register. */
7820 #define ALT_PINMUX_DCTD_IO_14_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
7821 
7822 #ifndef __ASSEMBLY__
7823 /*
7824  * WARNING: The C register and register group struct declarations are provided for
7825  * convenience and illustrative purposes. They should, however, be used with
7826  * caution as the C language standard provides no guarantees about the alignment or
7827  * atomicity of device memory accesses. The recommended practice for writing
7828  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7829  * alt_write_word() functions.
7830  *
7831  * The struct declaration for register ALT_PINMUX_DCTD_IO_14.
7832  */
7833 struct ALT_PINMUX_DCTD_IO_14_s
7834 {
7835  uint32_t sel : 4; /* Dedicated IO 14 Mux Selection Field */
7836  const uint32_t Reserved : 28; /* ALT_PINMUX_DCTD_IO_14_RSVD */
7837 };
7838 
7839 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_14. */
7840 typedef volatile struct ALT_PINMUX_DCTD_IO_14_s ALT_PINMUX_DCTD_IO_14_t;
7841 #endif /* __ASSEMBLY__ */
7842 
7843 /* The reset value of the ALT_PINMUX_DCTD_IO_14 register. */
7844 #define ALT_PINMUX_DCTD_IO_14_RESET 0x0000000f
7845 /* The byte offset of the ALT_PINMUX_DCTD_IO_14 register from the beginning of the component. */
7846 #define ALT_PINMUX_DCTD_IO_14_OFST 0x34
7847 
7848 /*
7849  * Register : Dedicated IO 15 Mux Selection Register - pinmux_dedicated_io_15
7850  *
7851  * This register is used to control the peripherals connected to dedicated IO pin
7852  * 15
7853  *
7854  * Only reset by a cold reset (ignores warm reset).
7855  *
7856  * NOTE: These registers should not be modified after IO configuration.There is no
7857  * support for dynamically changing the Pin Mux selections.
7858  *
7859  * Register Layout
7860  *
7861  * Bits | Access | Reset | Description
7862  * :-------|:-------|:------|:------------------------------------
7863  * [3:0] | RW | 0xf | Dedicated IO 15 Mux Selection Field
7864  * [31:4] | R | 0x0 | ALT_PINMUX_DCTD_IO_15_RSVD
7865  *
7866  */
7867 /*
7868  * Field : Dedicated IO 15 Mux Selection Field - sel
7869  *
7870  * Select peripheral signals connected Dedicated IO 15
7871  *
7872  * 0000 (0) Pin is connected to Peripheral signal i2c_emac2.scl
7873  *
7874  * 0001 (1) Pin is connected to Peripheral signal emac2.mdc
7875  *
7876  * 0010 (2) Pin is connected to Peripheral signal spis0.clk
7877  *
7878  * 0011 (3) Pin is connected to Peripheral signal not applicable
7879  *
7880  * 0100 (4) Pin is connected to Peripheral signal cm.pll_clk4
7881  *
7882  * 0101 (5) Pin is connected to Peripheral signal not applicable
7883  *
7884  * 0110 (6) Pin is connected to Peripheral signal not applicable
7885  *
7886  * 0111 (7) Pin is connected to Peripheral signal not applicable
7887  *
7888  * 1000 (8) Pin is connected to Peripheral signal sdmmc.data7
7889  *
7890  * 1001 (9) Pin is connected to Peripheral signal not applicable
7891  *
7892  * 1010 (10) Pin is connected to Peripheral signal not applicable
7893  *
7894  * 1011 (11) Pin is connected to Peripheral signal not applicable
7895  *
7896  * 1100 (12) Pin is connected to Peripheral signal not applicable
7897  *
7898  * 1101 (13) Pin is connected to Peripheral signal uart1.rx
7899  *
7900  * 1110 (14) Pin is connected to Peripheral signal nand.adq5
7901  *
7902  * 1111 (15) Pin is connected to Peripheral signal gpio2.io11
7903  *
7904  * Field Access Macros:
7905  *
7906  */
7907 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_15_SEL register field. */
7908 #define ALT_PINMUX_DCTD_IO_15_SEL_LSB 0
7909 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_15_SEL register field. */
7910 #define ALT_PINMUX_DCTD_IO_15_SEL_MSB 3
7911 /* The width in bits of the ALT_PINMUX_DCTD_IO_15_SEL register field. */
7912 #define ALT_PINMUX_DCTD_IO_15_SEL_WIDTH 4
7913 /* The mask used to set the ALT_PINMUX_DCTD_IO_15_SEL register field value. */
7914 #define ALT_PINMUX_DCTD_IO_15_SEL_SET_MSK 0x0000000f
7915 /* The mask used to clear the ALT_PINMUX_DCTD_IO_15_SEL register field value. */
7916 #define ALT_PINMUX_DCTD_IO_15_SEL_CLR_MSK 0xfffffff0
7917 /* The reset value of the ALT_PINMUX_DCTD_IO_15_SEL register field. */
7918 #define ALT_PINMUX_DCTD_IO_15_SEL_RESET 0xf
7919 /* Extracts the ALT_PINMUX_DCTD_IO_15_SEL field value from a register. */
7920 #define ALT_PINMUX_DCTD_IO_15_SEL_GET(value) (((value) & 0x0000000f) >> 0)
7921 /* Produces a ALT_PINMUX_DCTD_IO_15_SEL register field value suitable for setting the register. */
7922 #define ALT_PINMUX_DCTD_IO_15_SEL_SET(value) (((value) << 0) & 0x0000000f)
7923 
7924 /*
7925  * Field : Reserved
7926  *
7927  * Reserved
7928  *
7929  * Field Access Macros:
7930  *
7931  */
7932 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_15_RSVD register field. */
7933 #define ALT_PINMUX_DCTD_IO_15_RSVD_LSB 4
7934 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_15_RSVD register field. */
7935 #define ALT_PINMUX_DCTD_IO_15_RSVD_MSB 31
7936 /* The width in bits of the ALT_PINMUX_DCTD_IO_15_RSVD register field. */
7937 #define ALT_PINMUX_DCTD_IO_15_RSVD_WIDTH 28
7938 /* The mask used to set the ALT_PINMUX_DCTD_IO_15_RSVD register field value. */
7939 #define ALT_PINMUX_DCTD_IO_15_RSVD_SET_MSK 0xfffffff0
7940 /* The mask used to clear the ALT_PINMUX_DCTD_IO_15_RSVD register field value. */
7941 #define ALT_PINMUX_DCTD_IO_15_RSVD_CLR_MSK 0x0000000f
7942 /* The reset value of the ALT_PINMUX_DCTD_IO_15_RSVD register field. */
7943 #define ALT_PINMUX_DCTD_IO_15_RSVD_RESET 0x0
7944 /* Extracts the ALT_PINMUX_DCTD_IO_15_RSVD field value from a register. */
7945 #define ALT_PINMUX_DCTD_IO_15_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
7946 /* Produces a ALT_PINMUX_DCTD_IO_15_RSVD register field value suitable for setting the register. */
7947 #define ALT_PINMUX_DCTD_IO_15_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
7948 
7949 #ifndef __ASSEMBLY__
7950 /*
7951  * WARNING: The C register and register group struct declarations are provided for
7952  * convenience and illustrative purposes. They should, however, be used with
7953  * caution as the C language standard provides no guarantees about the alignment or
7954  * atomicity of device memory accesses. The recommended practice for writing
7955  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7956  * alt_write_word() functions.
7957  *
7958  * The struct declaration for register ALT_PINMUX_DCTD_IO_15.
7959  */
7960 struct ALT_PINMUX_DCTD_IO_15_s
7961 {
7962  uint32_t sel : 4; /* Dedicated IO 15 Mux Selection Field */
7963  const uint32_t Reserved : 28; /* ALT_PINMUX_DCTD_IO_15_RSVD */
7964 };
7965 
7966 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_15. */
7967 typedef volatile struct ALT_PINMUX_DCTD_IO_15_s ALT_PINMUX_DCTD_IO_15_t;
7968 #endif /* __ASSEMBLY__ */
7969 
7970 /* The reset value of the ALT_PINMUX_DCTD_IO_15 register. */
7971 #define ALT_PINMUX_DCTD_IO_15_RESET 0x0000000f
7972 /* The byte offset of the ALT_PINMUX_DCTD_IO_15 register from the beginning of the component. */
7973 #define ALT_PINMUX_DCTD_IO_15_OFST 0x38
7974 
7975 /*
7976  * Register : Dedicated IO 16 Mux Selection Register - pinmux_dedicated_io_16
7977  *
7978  * This register is used to control the peripherals connected to dedicated IO pin
7979  * 16
7980  *
7981  * Only reset by a cold reset (ignores warm reset).
7982  *
7983  * NOTE: These registers should not be modified after IO configuration.There is no
7984  * support for dynamically changing the Pin Mux selections.
7985  *
7986  * Register Layout
7987  *
7988  * Bits | Access | Reset | Description
7989  * :-------|:-------|:------|:------------------------------------
7990  * [3:0] | RW | 0xf | Dedicated IO 16 Mux Selection Field
7991  * [31:4] | R | 0x0 | ALT_PINMUX_DCTD_IO_16_RSVD
7992  *
7993  */
7994 /*
7995  * Field : Dedicated IO 16 Mux Selection Field - sel
7996  *
7997  * Select peripheral signals connected Dedicated IO 16
7998  *
7999  * 0000 (0) Pin is connected to Peripheral signal i2c_emac0.sda
8000  *
8001  * 0001 (1) Pin is connected to Peripheral signal emac0.mdio
8002  *
8003  * 0010 (2) Pin is connected to Peripheral signal spis0.mosi
8004  *
8005  * 0011 (3) Pin is connected to Peripheral signal not applicable
8006  *
8007  * 0100 (4) Pin is connected to Peripheral signal not applicable
8008  *
8009  * 0101 (5) Pin is connected to Peripheral signal not applicable
8010  *
8011  * 0110 (6) Pin is connected to Peripheral signal not applicable
8012  *
8013  * 0111 (7) Pin is connected to Peripheral signal not applicable
8014  *
8015  * 1000 (8) Pin is connected to Peripheral signal qspi.ss2
8016  *
8017  * 1001 (9) Pin is connected to Peripheral signal not applicable
8018  *
8019  * 1010 (10) Pin is connected to Peripheral signal not applicable
8020  *
8021  * 1011 (11) Pin is connected to Peripheral signal not applicable
8022  *
8023  * 1100 (12) Pin is connected to Peripheral signal not applicable
8024  *
8025  * 1101 (13) Pin is connected to Peripheral signal uart1.tx
8026  *
8027  * 1110 (14) Pin is connected to Peripheral signal nand.adq6
8028  *
8029  * 1111 (15) Pin is connected to Peripheral signal gpio2.io12
8030  *
8031  * Field Access Macros:
8032  *
8033  */
8034 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_16_SEL register field. */
8035 #define ALT_PINMUX_DCTD_IO_16_SEL_LSB 0
8036 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_16_SEL register field. */
8037 #define ALT_PINMUX_DCTD_IO_16_SEL_MSB 3
8038 /* The width in bits of the ALT_PINMUX_DCTD_IO_16_SEL register field. */
8039 #define ALT_PINMUX_DCTD_IO_16_SEL_WIDTH 4
8040 /* The mask used to set the ALT_PINMUX_DCTD_IO_16_SEL register field value. */
8041 #define ALT_PINMUX_DCTD_IO_16_SEL_SET_MSK 0x0000000f
8042 /* The mask used to clear the ALT_PINMUX_DCTD_IO_16_SEL register field value. */
8043 #define ALT_PINMUX_DCTD_IO_16_SEL_CLR_MSK 0xfffffff0
8044 /* The reset value of the ALT_PINMUX_DCTD_IO_16_SEL register field. */
8045 #define ALT_PINMUX_DCTD_IO_16_SEL_RESET 0xf
8046 /* Extracts the ALT_PINMUX_DCTD_IO_16_SEL field value from a register. */
8047 #define ALT_PINMUX_DCTD_IO_16_SEL_GET(value) (((value) & 0x0000000f) >> 0)
8048 /* Produces a ALT_PINMUX_DCTD_IO_16_SEL register field value suitable for setting the register. */
8049 #define ALT_PINMUX_DCTD_IO_16_SEL_SET(value) (((value) << 0) & 0x0000000f)
8050 
8051 /*
8052  * Field : Reserved
8053  *
8054  * Reserved
8055  *
8056  * Field Access Macros:
8057  *
8058  */
8059 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_16_RSVD register field. */
8060 #define ALT_PINMUX_DCTD_IO_16_RSVD_LSB 4
8061 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_16_RSVD register field. */
8062 #define ALT_PINMUX_DCTD_IO_16_RSVD_MSB 31
8063 /* The width in bits of the ALT_PINMUX_DCTD_IO_16_RSVD register field. */
8064 #define ALT_PINMUX_DCTD_IO_16_RSVD_WIDTH 28
8065 /* The mask used to set the ALT_PINMUX_DCTD_IO_16_RSVD register field value. */
8066 #define ALT_PINMUX_DCTD_IO_16_RSVD_SET_MSK 0xfffffff0
8067 /* The mask used to clear the ALT_PINMUX_DCTD_IO_16_RSVD register field value. */
8068 #define ALT_PINMUX_DCTD_IO_16_RSVD_CLR_MSK 0x0000000f
8069 /* The reset value of the ALT_PINMUX_DCTD_IO_16_RSVD register field. */
8070 #define ALT_PINMUX_DCTD_IO_16_RSVD_RESET 0x0
8071 /* Extracts the ALT_PINMUX_DCTD_IO_16_RSVD field value from a register. */
8072 #define ALT_PINMUX_DCTD_IO_16_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
8073 /* Produces a ALT_PINMUX_DCTD_IO_16_RSVD register field value suitable for setting the register. */
8074 #define ALT_PINMUX_DCTD_IO_16_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
8075 
8076 #ifndef __ASSEMBLY__
8077 /*
8078  * WARNING: The C register and register group struct declarations are provided for
8079  * convenience and illustrative purposes. They should, however, be used with
8080  * caution as the C language standard provides no guarantees about the alignment or
8081  * atomicity of device memory accesses. The recommended practice for writing
8082  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8083  * alt_write_word() functions.
8084  *
8085  * The struct declaration for register ALT_PINMUX_DCTD_IO_16.
8086  */
8087 struct ALT_PINMUX_DCTD_IO_16_s
8088 {
8089  uint32_t sel : 4; /* Dedicated IO 16 Mux Selection Field */
8090  const uint32_t Reserved : 28; /* ALT_PINMUX_DCTD_IO_16_RSVD */
8091 };
8092 
8093 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_16. */
8094 typedef volatile struct ALT_PINMUX_DCTD_IO_16_s ALT_PINMUX_DCTD_IO_16_t;
8095 #endif /* __ASSEMBLY__ */
8096 
8097 /* The reset value of the ALT_PINMUX_DCTD_IO_16 register. */
8098 #define ALT_PINMUX_DCTD_IO_16_RESET 0x0000000f
8099 /* The byte offset of the ALT_PINMUX_DCTD_IO_16 register from the beginning of the component. */
8100 #define ALT_PINMUX_DCTD_IO_16_OFST 0x3c
8101 
8102 /*
8103  * Register : Dedicated IO 17 Mux Selection Register - pinmux_dedicated_io_17
8104  *
8105  * This register is used to control the peripherals connected to dedicated IO pin
8106  * 17
8107  *
8108  * Only reset by a cold reset (ignores warm reset).
8109  *
8110  * NOTE: These registers should not be modified after IO configuration.There is no
8111  * support for dynamically changing the Pin Mux selections.
8112  *
8113  * Register Layout
8114  *
8115  * Bits | Access | Reset | Description
8116  * :-------|:-------|:------|:------------------------------------
8117  * [3:0] | RW | 0xf | Dedicated IO 17 Mux Selection Field
8118  * [31:4] | R | 0x0 | ALT_PINMUX_DCTD_IO_17_RSVD
8119  *
8120  */
8121 /*
8122  * Field : Dedicated IO 17 Mux Selection Field - sel
8123  *
8124  * Select peripheral signals connected Dedicated IO 17
8125  *
8126  * 0000 (0) Pin is connected to Peripheral signal i2c_emac0.scl
8127  *
8128  * 0001 (1) Pin is connected to Peripheral signal emac0.mdc
8129  *
8130  * 0010 (2) Pin is connected to Peripheral signal spis0.ss0_n
8131  *
8132  * 0011 (3) Pin is connected to Peripheral signal not applicable
8133  *
8134  * 0100 (4) Pin is connected to Peripheral signal not applicable
8135  *
8136  * 0101 (5) Pin is connected to Peripheral signal not applicable
8137  *
8138  * 0110 (6) Pin is connected to Peripheral signal not applicable
8139  *
8140  * 0111 (7) Pin is connected to Peripheral signal not applicable
8141  *
8142  * 1000 (8) Pin is connected to Peripheral signal qspi.ss3
8143  *
8144  * 1001 (9) Pin is connected to Peripheral signal not applicable
8145  *
8146  * 1010 (10) Pin is connected to Peripheral signal not applicable
8147  *
8148  * 1011 (11) Pin is connected to Peripheral signal not applicable
8149  *
8150  * 1100 (12) Pin is connected to Peripheral signal not applicable
8151  *
8152  * 1101 (13) Pin is connected to Peripheral signal uart1.rx
8153  *
8154  * 1110 (14) Pin is connected to Peripheral signal nand.adq7
8155  *
8156  * 1111 (15) Pin is connected to Peripheral signal gpio2.io13
8157  *
8158  * Field Access Macros:
8159  *
8160  */
8161 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_17_SEL register field. */
8162 #define ALT_PINMUX_DCTD_IO_17_SEL_LSB 0
8163 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_17_SEL register field. */
8164 #define ALT_PINMUX_DCTD_IO_17_SEL_MSB 3
8165 /* The width in bits of the ALT_PINMUX_DCTD_IO_17_SEL register field. */
8166 #define ALT_PINMUX_DCTD_IO_17_SEL_WIDTH 4
8167 /* The mask used to set the ALT_PINMUX_DCTD_IO_17_SEL register field value. */
8168 #define ALT_PINMUX_DCTD_IO_17_SEL_SET_MSK 0x0000000f
8169 /* The mask used to clear the ALT_PINMUX_DCTD_IO_17_SEL register field value. */
8170 #define ALT_PINMUX_DCTD_IO_17_SEL_CLR_MSK 0xfffffff0
8171 /* The reset value of the ALT_PINMUX_DCTD_IO_17_SEL register field. */
8172 #define ALT_PINMUX_DCTD_IO_17_SEL_RESET 0xf
8173 /* Extracts the ALT_PINMUX_DCTD_IO_17_SEL field value from a register. */
8174 #define ALT_PINMUX_DCTD_IO_17_SEL_GET(value) (((value) & 0x0000000f) >> 0)
8175 /* Produces a ALT_PINMUX_DCTD_IO_17_SEL register field value suitable for setting the register. */
8176 #define ALT_PINMUX_DCTD_IO_17_SEL_SET(value) (((value) << 0) & 0x0000000f)
8177 
8178 /*
8179  * Field : Reserved
8180  *
8181  * Reserved
8182  *
8183  * Field Access Macros:
8184  *
8185  */
8186 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_17_RSVD register field. */
8187 #define ALT_PINMUX_DCTD_IO_17_RSVD_LSB 4
8188 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_17_RSVD register field. */
8189 #define ALT_PINMUX_DCTD_IO_17_RSVD_MSB 31
8190 /* The width in bits of the ALT_PINMUX_DCTD_IO_17_RSVD register field. */
8191 #define ALT_PINMUX_DCTD_IO_17_RSVD_WIDTH 28
8192 /* The mask used to set the ALT_PINMUX_DCTD_IO_17_RSVD register field value. */
8193 #define ALT_PINMUX_DCTD_IO_17_RSVD_SET_MSK 0xfffffff0
8194 /* The mask used to clear the ALT_PINMUX_DCTD_IO_17_RSVD register field value. */
8195 #define ALT_PINMUX_DCTD_IO_17_RSVD_CLR_MSK 0x0000000f
8196 /* The reset value of the ALT_PINMUX_DCTD_IO_17_RSVD register field. */
8197 #define ALT_PINMUX_DCTD_IO_17_RSVD_RESET 0x0
8198 /* Extracts the ALT_PINMUX_DCTD_IO_17_RSVD field value from a register. */
8199 #define ALT_PINMUX_DCTD_IO_17_RSVD_GET(value) (((value) & 0xfffffff0) >> 4)
8200 /* Produces a ALT_PINMUX_DCTD_IO_17_RSVD register field value suitable for setting the register. */
8201 #define ALT_PINMUX_DCTD_IO_17_RSVD_SET(value) (((value) << 4) & 0xfffffff0)
8202 
8203 #ifndef __ASSEMBLY__
8204 /*
8205  * WARNING: The C register and register group struct declarations are provided for
8206  * convenience and illustrative purposes. They should, however, be used with
8207  * caution as the C language standard provides no guarantees about the alignment or
8208  * atomicity of device memory accesses. The recommended practice for writing
8209  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8210  * alt_write_word() functions.
8211  *
8212  * The struct declaration for register ALT_PINMUX_DCTD_IO_17.
8213  */
8214 struct ALT_PINMUX_DCTD_IO_17_s
8215 {
8216  uint32_t sel : 4; /* Dedicated IO 17 Mux Selection Field */
8217  const uint32_t Reserved : 28; /* ALT_PINMUX_DCTD_IO_17_RSVD */
8218 };
8219 
8220 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_17. */
8221 typedef volatile struct ALT_PINMUX_DCTD_IO_17_s ALT_PINMUX_DCTD_IO_17_t;
8222 #endif /* __ASSEMBLY__ */
8223 
8224 /* The reset value of the ALT_PINMUX_DCTD_IO_17 register. */
8225 #define ALT_PINMUX_DCTD_IO_17_RESET 0x0000000f
8226 /* The byte offset of the ALT_PINMUX_DCTD_IO_17 register from the beginning of the component. */
8227 #define ALT_PINMUX_DCTD_IO_17_OFST 0x40
8228 
8229 /*
8230  * Register : Voltage Level Configuration Register - configuration_dedicated_io_bank
8231  *
8232  * This register is used to control the voltage select for all dedicated IO.
8233  *
8234  * Register Layout
8235  *
8236  * Bits | Access | Reset | Description
8237  * :--------|:-------|:------|:----------------------------------------
8238  * [1:0] | RW | 0x0 | Voltage select
8239  * [7:2] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2
8240  * [9:8] | RW | 0x0 | Voltage select
8241  * [31:10] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10
8242  *
8243  */
8244 /*
8245  * Field : Voltage select - VOLTAGE_SEL_PERI_IO
8246  *
8247  * Configuration bits for voltage select. This only affects peripheral IO (exclude
8248  * CLK and RST IO).
8249  *
8250  * 00 : 3.0V operation
8251  *
8252  * 01 : 1.8V operation
8253  *
8254  * 10 : 2.5V operation
8255  *
8256  * 11 : RSVD
8257  *
8258  * Field Access Macros:
8259  *
8260  */
8261 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO register field. */
8262 #define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_LSB 0
8263 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO register field. */
8264 #define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_MSB 1
8265 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO register field. */
8266 #define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_WIDTH 2
8267 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO register field value. */
8268 #define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_SET_MSK 0x00000003
8269 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO register field value. */
8270 #define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_CLR_MSK 0xfffffffc
8271 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO register field. */
8272 #define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_RESET 0x0
8273 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO field value from a register. */
8274 #define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_GET(value) (((value) & 0x00000003) >> 0)
8275 /* Produces a ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO register field value suitable for setting the register. */
8276 #define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_SET(value) (((value) << 0) & 0x00000003)
8277 
8278 /*
8279  * Field : Reserved_7to2
8280  *
8281  * Reserved
8282  *
8283  * Field Access Macros:
8284  *
8285  */
8286 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2 register field. */
8287 #define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_LSB 2
8288 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2 register field. */
8289 #define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_MSB 7
8290 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2 register field. */
8291 #define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_WIDTH 6
8292 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2 register field value. */
8293 #define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_SET_MSK 0x000000fc
8294 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2 register field value. */
8295 #define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_CLR_MSK 0xffffff03
8296 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2 register field. */
8297 #define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_RESET 0x0
8298 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2 field value from a register. */
8299 #define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_GET(value) (((value) & 0x000000fc) >> 2)
8300 /* Produces a ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2 register field value suitable for setting the register. */
8301 #define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_SET(value) (((value) << 2) & 0x000000fc)
8302 
8303 /*
8304  * Field : Voltage select - VOLTAGE_SEL_CLKRST_IO
8305  *
8306  * Configuration bits for voltage select. This only affects CLK and RST IO.
8307  *
8308  * 00 : 3.0V operation
8309  *
8310  * 01 : 1.8V operation
8311  *
8312  * 10 : 2.5V operation
8313  *
8314  * 11 : RSVD
8315  *
8316  * Field Access Macros:
8317  *
8318  */
8319 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO register field. */
8320 #define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_LSB 8
8321 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO register field. */
8322 #define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_MSB 9
8323 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO register field. */
8324 #define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_WIDTH 2
8325 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO register field value. */
8326 #define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_SET_MSK 0x00000300
8327 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO register field value. */
8328 #define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_CLR_MSK 0xfffffcff
8329 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO register field. */
8330 #define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_RESET 0x0
8331 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO field value from a register. */
8332 #define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_GET(value) (((value) & 0x00000300) >> 8)
8333 /* Produces a ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO register field value suitable for setting the register. */
8334 #define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_SET(value) (((value) << 8) & 0x00000300)
8335 
8336 /*
8337  * Field : Reserved_31to10
8338  *
8339  * Reserved
8340  *
8341  * Field Access Macros:
8342  *
8343  */
8344 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10 register field. */
8345 #define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_LSB 10
8346 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10 register field. */
8347 #define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_MSB 31
8348 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10 register field. */
8349 #define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_WIDTH 22
8350 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10 register field value. */
8351 #define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_SET_MSK 0xfffffc00
8352 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10 register field value. */
8353 #define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_CLR_MSK 0x000003ff
8354 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10 register field. */
8355 #define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_RESET 0x0
8356 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10 field value from a register. */
8357 #define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_GET(value) (((value) & 0xfffffc00) >> 10)
8358 /* Produces a ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10 register field value suitable for setting the register. */
8359 #define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_SET(value) (((value) << 10) & 0xfffffc00)
8360 
8361 #ifndef __ASSEMBLY__
8362 /*
8363  * WARNING: The C register and register group struct declarations are provided for
8364  * convenience and illustrative purposes. They should, however, be used with
8365  * caution as the C language standard provides no guarantees about the alignment or
8366  * atomicity of device memory accesses. The recommended practice for writing
8367  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8368  * alt_write_word() functions.
8369  *
8370  * The struct declaration for register ALT_PINMUX_DCTD_IO_CFG_BANK.
8371  */
8372 struct ALT_PINMUX_DCTD_IO_CFG_BANK_s
8373 {
8374  uint32_t VOLTAGE_SEL_PERI_IO : 2; /* Voltage select */
8375  const uint32_t Reserved_7to2 : 6; /* ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2 */
8376  uint32_t VOLTAGE_SEL_CLKRST_IO : 2; /* Voltage select */
8377  const uint32_t Reserved_31to10 : 22; /* ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10 */
8378 };
8379 
8380 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_CFG_BANK. */
8381 typedef volatile struct ALT_PINMUX_DCTD_IO_CFG_BANK_s ALT_PINMUX_DCTD_IO_CFG_BANK_t;
8382 #endif /* __ASSEMBLY__ */
8383 
8384 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_BANK register. */
8385 #define ALT_PINMUX_DCTD_IO_CFG_BANK_RESET 0x00000000
8386 /* The byte offset of the ALT_PINMUX_DCTD_IO_CFG_BANK register from the beginning of the component. */
8387 #define ALT_PINMUX_DCTD_IO_CFG_BANK_OFST 0x100
8388 
8389 /*
8390  * Register : Dedicated IO 1 Configuration Register - configuration_dedicated_io_1
8391  *
8392  * This register is used to control the electrical behavior and direction of
8393  * Dedicated IO 1
8394  *
8395  * Only reset by a cold reset (ignores warm reset).
8396  *
8397  * Register Layout
8398  *
8399  * Bits | Access | Reset | Description
8400  * :--------|:-------|:------|:-------------------------------------
8401  * [4:0] | RW | 0x0 | Pull down drive strength
8402  * [5] | RW | 0x0 | NMOS slew rate
8403  * [7:6] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_1_RSVD_7TO6
8404  * [12:8] | RW | 0x0 | Pull up drive strength
8405  * [13] | RW | 0x0 | PMOS slew rate
8406  * [15:14] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_1_RSVD_15TO14
8407  * [16] | RW | 0x1 | Weak pull up signal
8408  * [18:17] | RW | 0x2 | LVTTL input buffer enable signal
8409  * [21:19] | RW | 0x1 | Bias trim bits
8410  * [31:22] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_1_RSVD_31TO22
8411  *
8412  */
8413 /*
8414  * Field : Pull down drive strength - PD_DRV_STRG
8415  *
8416  * Configuration bits for NMOS pull down drive strength.
8417  *
8418  * Pending Characterization
8419  *
8420  * Field Access Macros:
8421  *
8422  */
8423 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_1_PD_DRV_STRG register field. */
8424 #define ALT_PINMUX_DCTD_IO_CFG_1_PD_DRV_STRG_LSB 0
8425 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_1_PD_DRV_STRG register field. */
8426 #define ALT_PINMUX_DCTD_IO_CFG_1_PD_DRV_STRG_MSB 4
8427 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_1_PD_DRV_STRG register field. */
8428 #define ALT_PINMUX_DCTD_IO_CFG_1_PD_DRV_STRG_WIDTH 5
8429 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_1_PD_DRV_STRG register field value. */
8430 #define ALT_PINMUX_DCTD_IO_CFG_1_PD_DRV_STRG_SET_MSK 0x0000001f
8431 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_1_PD_DRV_STRG register field value. */
8432 #define ALT_PINMUX_DCTD_IO_CFG_1_PD_DRV_STRG_CLR_MSK 0xffffffe0
8433 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_1_PD_DRV_STRG register field. */
8434 #define ALT_PINMUX_DCTD_IO_CFG_1_PD_DRV_STRG_RESET 0x0
8435 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_1_PD_DRV_STRG field value from a register. */
8436 #define ALT_PINMUX_DCTD_IO_CFG_1_PD_DRV_STRG_GET(value) (((value) & 0x0000001f) >> 0)
8437 /* Produces a ALT_PINMUX_DCTD_IO_CFG_1_PD_DRV_STRG register field value suitable for setting the register. */
8438 #define ALT_PINMUX_DCTD_IO_CFG_1_PD_DRV_STRG_SET(value) (((value) << 0) & 0x0000001f)
8439 
8440 /*
8441  * Field : NMOS slew rate - PD_SLW_RT
8442  *
8443  * Configuration bit for output pull down slew rate control
8444  *
8445  * 0 : slow N slew
8446  *
8447  * 1 : fast N slew
8448  *
8449  * Field Access Macros:
8450  *
8451  */
8452 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_1_PD_SLW_RT register field. */
8453 #define ALT_PINMUX_DCTD_IO_CFG_1_PD_SLW_RT_LSB 5
8454 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_1_PD_SLW_RT register field. */
8455 #define ALT_PINMUX_DCTD_IO_CFG_1_PD_SLW_RT_MSB 5
8456 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_1_PD_SLW_RT register field. */
8457 #define ALT_PINMUX_DCTD_IO_CFG_1_PD_SLW_RT_WIDTH 1
8458 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_1_PD_SLW_RT register field value. */
8459 #define ALT_PINMUX_DCTD_IO_CFG_1_PD_SLW_RT_SET_MSK 0x00000020
8460 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_1_PD_SLW_RT register field value. */
8461 #define ALT_PINMUX_DCTD_IO_CFG_1_PD_SLW_RT_CLR_MSK 0xffffffdf
8462 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_1_PD_SLW_RT register field. */
8463 #define ALT_PINMUX_DCTD_IO_CFG_1_PD_SLW_RT_RESET 0x0
8464 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_1_PD_SLW_RT field value from a register. */
8465 #define ALT_PINMUX_DCTD_IO_CFG_1_PD_SLW_RT_GET(value) (((value) & 0x00000020) >> 5)
8466 /* Produces a ALT_PINMUX_DCTD_IO_CFG_1_PD_SLW_RT register field value suitable for setting the register. */
8467 #define ALT_PINMUX_DCTD_IO_CFG_1_PD_SLW_RT_SET(value) (((value) << 5) & 0x00000020)
8468 
8469 /*
8470  * Field : Reserved_7to6
8471  *
8472  * Reserved
8473  *
8474  * Field Access Macros:
8475  *
8476  */
8477 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_1_RSVD_7TO6 register field. */
8478 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_7TO6_LSB 6
8479 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_1_RSVD_7TO6 register field. */
8480 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_7TO6_MSB 7
8481 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_1_RSVD_7TO6 register field. */
8482 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_7TO6_WIDTH 2
8483 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_1_RSVD_7TO6 register field value. */
8484 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_7TO6_SET_MSK 0x000000c0
8485 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_1_RSVD_7TO6 register field value. */
8486 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_7TO6_CLR_MSK 0xffffff3f
8487 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_1_RSVD_7TO6 register field. */
8488 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_7TO6_RESET 0x0
8489 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_1_RSVD_7TO6 field value from a register. */
8490 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_7TO6_GET(value) (((value) & 0x000000c0) >> 6)
8491 /* Produces a ALT_PINMUX_DCTD_IO_CFG_1_RSVD_7TO6 register field value suitable for setting the register. */
8492 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_7TO6_SET(value) (((value) << 6) & 0x000000c0)
8493 
8494 /*
8495  * Field : Pull up drive strength - PU_DRV_STRG
8496  *
8497  * Configuration bits for PMOS pull up drive strength
8498  *
8499  * Pending Characterization
8500  *
8501  * Field Access Macros:
8502  *
8503  */
8504 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_1_PU_DRV_STRG register field. */
8505 #define ALT_PINMUX_DCTD_IO_CFG_1_PU_DRV_STRG_LSB 8
8506 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_1_PU_DRV_STRG register field. */
8507 #define ALT_PINMUX_DCTD_IO_CFG_1_PU_DRV_STRG_MSB 12
8508 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_1_PU_DRV_STRG register field. */
8509 #define ALT_PINMUX_DCTD_IO_CFG_1_PU_DRV_STRG_WIDTH 5
8510 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_1_PU_DRV_STRG register field value. */
8511 #define ALT_PINMUX_DCTD_IO_CFG_1_PU_DRV_STRG_SET_MSK 0x00001f00
8512 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_1_PU_DRV_STRG register field value. */
8513 #define ALT_PINMUX_DCTD_IO_CFG_1_PU_DRV_STRG_CLR_MSK 0xffffe0ff
8514 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_1_PU_DRV_STRG register field. */
8515 #define ALT_PINMUX_DCTD_IO_CFG_1_PU_DRV_STRG_RESET 0x0
8516 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_1_PU_DRV_STRG field value from a register. */
8517 #define ALT_PINMUX_DCTD_IO_CFG_1_PU_DRV_STRG_GET(value) (((value) & 0x00001f00) >> 8)
8518 /* Produces a ALT_PINMUX_DCTD_IO_CFG_1_PU_DRV_STRG register field value suitable for setting the register. */
8519 #define ALT_PINMUX_DCTD_IO_CFG_1_PU_DRV_STRG_SET(value) (((value) << 8) & 0x00001f00)
8520 
8521 /*
8522  * Field : PMOS slew rate - PU_SLW_RT
8523  *
8524  * Configuration bit for output pull up slew rate control
8525  *
8526  * 0 : slow P slew
8527  *
8528  * 1 : fast P slew
8529  *
8530  * Field Access Macros:
8531  *
8532  */
8533 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_1_PU_SLW_RT register field. */
8534 #define ALT_PINMUX_DCTD_IO_CFG_1_PU_SLW_RT_LSB 13
8535 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_1_PU_SLW_RT register field. */
8536 #define ALT_PINMUX_DCTD_IO_CFG_1_PU_SLW_RT_MSB 13
8537 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_1_PU_SLW_RT register field. */
8538 #define ALT_PINMUX_DCTD_IO_CFG_1_PU_SLW_RT_WIDTH 1
8539 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_1_PU_SLW_RT register field value. */
8540 #define ALT_PINMUX_DCTD_IO_CFG_1_PU_SLW_RT_SET_MSK 0x00002000
8541 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_1_PU_SLW_RT register field value. */
8542 #define ALT_PINMUX_DCTD_IO_CFG_1_PU_SLW_RT_CLR_MSK 0xffffdfff
8543 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_1_PU_SLW_RT register field. */
8544 #define ALT_PINMUX_DCTD_IO_CFG_1_PU_SLW_RT_RESET 0x0
8545 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_1_PU_SLW_RT field value from a register. */
8546 #define ALT_PINMUX_DCTD_IO_CFG_1_PU_SLW_RT_GET(value) (((value) & 0x00002000) >> 13)
8547 /* Produces a ALT_PINMUX_DCTD_IO_CFG_1_PU_SLW_RT register field value suitable for setting the register. */
8548 #define ALT_PINMUX_DCTD_IO_CFG_1_PU_SLW_RT_SET(value) (((value) << 13) & 0x00002000)
8549 
8550 /*
8551  * Field : Reserved_15to14
8552  *
8553  * Reserved
8554  *
8555  * Field Access Macros:
8556  *
8557  */
8558 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_1_RSVD_15TO14 register field. */
8559 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_15TO14_LSB 14
8560 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_1_RSVD_15TO14 register field. */
8561 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_15TO14_MSB 15
8562 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_1_RSVD_15TO14 register field. */
8563 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_15TO14_WIDTH 2
8564 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_1_RSVD_15TO14 register field value. */
8565 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_15TO14_SET_MSK 0x0000c000
8566 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_1_RSVD_15TO14 register field value. */
8567 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_15TO14_CLR_MSK 0xffff3fff
8568 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_1_RSVD_15TO14 register field. */
8569 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_15TO14_RESET 0x0
8570 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_1_RSVD_15TO14 field value from a register. */
8571 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_15TO14_GET(value) (((value) & 0x0000c000) >> 14)
8572 /* Produces a ALT_PINMUX_DCTD_IO_CFG_1_RSVD_15TO14 register field value suitable for setting the register. */
8573 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_15TO14_SET(value) (((value) << 14) & 0x0000c000)
8574 
8575 /*
8576  * Field : Weak pull up signal - WK_PU_EN
8577  *
8578  * Configuration bit for weak pull up enable
8579  *
8580  * 0 : weak pull up disable
8581  *
8582  * 1 : weak pull up enable
8583  *
8584  * Field Access Macros:
8585  *
8586  */
8587 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_1_WK_PU_EN register field. */
8588 #define ALT_PINMUX_DCTD_IO_CFG_1_WK_PU_EN_LSB 16
8589 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_1_WK_PU_EN register field. */
8590 #define ALT_PINMUX_DCTD_IO_CFG_1_WK_PU_EN_MSB 16
8591 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_1_WK_PU_EN register field. */
8592 #define ALT_PINMUX_DCTD_IO_CFG_1_WK_PU_EN_WIDTH 1
8593 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_1_WK_PU_EN register field value. */
8594 #define ALT_PINMUX_DCTD_IO_CFG_1_WK_PU_EN_SET_MSK 0x00010000
8595 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_1_WK_PU_EN register field value. */
8596 #define ALT_PINMUX_DCTD_IO_CFG_1_WK_PU_EN_CLR_MSK 0xfffeffff
8597 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_1_WK_PU_EN register field. */
8598 #define ALT_PINMUX_DCTD_IO_CFG_1_WK_PU_EN_RESET 0x1
8599 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_1_WK_PU_EN field value from a register. */
8600 #define ALT_PINMUX_DCTD_IO_CFG_1_WK_PU_EN_GET(value) (((value) & 0x00010000) >> 16)
8601 /* Produces a ALT_PINMUX_DCTD_IO_CFG_1_WK_PU_EN register field value suitable for setting the register. */
8602 #define ALT_PINMUX_DCTD_IO_CFG_1_WK_PU_EN_SET(value) (((value) << 16) & 0x00010000)
8603 
8604 /*
8605  * Field : LVTTL input buffer enable signal - INPUT_BUF_EN
8606  *
8607  * Configuration bits for LVTTL input buffer enable
8608  *
8609  * 00 : disable
8610  *
8611  * 01 : 1.8V TTL
8612  *
8613  * 10 : 2.5V/3.0V TTL
8614  *
8615  * 11 : 1.8V TTL
8616  *
8617  * Field Access Macros:
8618  *
8619  */
8620 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_1_INPUT_BUF_EN register field. */
8621 #define ALT_PINMUX_DCTD_IO_CFG_1_INPUT_BUF_EN_LSB 17
8622 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_1_INPUT_BUF_EN register field. */
8623 #define ALT_PINMUX_DCTD_IO_CFG_1_INPUT_BUF_EN_MSB 18
8624 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_1_INPUT_BUF_EN register field. */
8625 #define ALT_PINMUX_DCTD_IO_CFG_1_INPUT_BUF_EN_WIDTH 2
8626 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_1_INPUT_BUF_EN register field value. */
8627 #define ALT_PINMUX_DCTD_IO_CFG_1_INPUT_BUF_EN_SET_MSK 0x00060000
8628 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_1_INPUT_BUF_EN register field value. */
8629 #define ALT_PINMUX_DCTD_IO_CFG_1_INPUT_BUF_EN_CLR_MSK 0xfff9ffff
8630 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_1_INPUT_BUF_EN register field. */
8631 #define ALT_PINMUX_DCTD_IO_CFG_1_INPUT_BUF_EN_RESET 0x2
8632 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_1_INPUT_BUF_EN field value from a register. */
8633 #define ALT_PINMUX_DCTD_IO_CFG_1_INPUT_BUF_EN_GET(value) (((value) & 0x00060000) >> 17)
8634 /* Produces a ALT_PINMUX_DCTD_IO_CFG_1_INPUT_BUF_EN register field value suitable for setting the register. */
8635 #define ALT_PINMUX_DCTD_IO_CFG_1_INPUT_BUF_EN_SET(value) (((value) << 17) & 0x00060000)
8636 
8637 /*
8638  * Field : Bias trim bits - RTRIM
8639  *
8640  * Configuration bits for bias trim
8641  *
8642  * 000 : disable
8643  *
8644  * 001 : default
8645  *
8646  * 010 : trim low
8647  *
8648  * 100 : trim high
8649  *
8650  * others : invalid/reserved
8651  *
8652  * Field Access Macros:
8653  *
8654  */
8655 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_1_RTRIM register field. */
8656 #define ALT_PINMUX_DCTD_IO_CFG_1_RTRIM_LSB 19
8657 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_1_RTRIM register field. */
8658 #define ALT_PINMUX_DCTD_IO_CFG_1_RTRIM_MSB 21
8659 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_1_RTRIM register field. */
8660 #define ALT_PINMUX_DCTD_IO_CFG_1_RTRIM_WIDTH 3
8661 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_1_RTRIM register field value. */
8662 #define ALT_PINMUX_DCTD_IO_CFG_1_RTRIM_SET_MSK 0x00380000
8663 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_1_RTRIM register field value. */
8664 #define ALT_PINMUX_DCTD_IO_CFG_1_RTRIM_CLR_MSK 0xffc7ffff
8665 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_1_RTRIM register field. */
8666 #define ALT_PINMUX_DCTD_IO_CFG_1_RTRIM_RESET 0x1
8667 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_1_RTRIM field value from a register. */
8668 #define ALT_PINMUX_DCTD_IO_CFG_1_RTRIM_GET(value) (((value) & 0x00380000) >> 19)
8669 /* Produces a ALT_PINMUX_DCTD_IO_CFG_1_RTRIM register field value suitable for setting the register. */
8670 #define ALT_PINMUX_DCTD_IO_CFG_1_RTRIM_SET(value) (((value) << 19) & 0x00380000)
8671 
8672 /*
8673  * Field : Reserved_31to22
8674  *
8675  * Reserved
8676  *
8677  * Field Access Macros:
8678  *
8679  */
8680 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_1_RSVD_31TO22 register field. */
8681 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_31TO22_LSB 22
8682 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_1_RSVD_31TO22 register field. */
8683 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_31TO22_MSB 31
8684 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_1_RSVD_31TO22 register field. */
8685 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_31TO22_WIDTH 10
8686 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_1_RSVD_31TO22 register field value. */
8687 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_31TO22_SET_MSK 0xffc00000
8688 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_1_RSVD_31TO22 register field value. */
8689 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_31TO22_CLR_MSK 0x003fffff
8690 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_1_RSVD_31TO22 register field. */
8691 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_31TO22_RESET 0x0
8692 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_1_RSVD_31TO22 field value from a register. */
8693 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_31TO22_GET(value) (((value) & 0xffc00000) >> 22)
8694 /* Produces a ALT_PINMUX_DCTD_IO_CFG_1_RSVD_31TO22 register field value suitable for setting the register. */
8695 #define ALT_PINMUX_DCTD_IO_CFG_1_RSVD_31TO22_SET(value) (((value) << 22) & 0xffc00000)
8696 
8697 #ifndef __ASSEMBLY__
8698 /*
8699  * WARNING: The C register and register group struct declarations are provided for
8700  * convenience and illustrative purposes. They should, however, be used with
8701  * caution as the C language standard provides no guarantees about the alignment or
8702  * atomicity of device memory accesses. The recommended practice for writing
8703  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8704  * alt_write_word() functions.
8705  *
8706  * The struct declaration for register ALT_PINMUX_DCTD_IO_CFG_1.
8707  */
8708 struct ALT_PINMUX_DCTD_IO_CFG_1_s
8709 {
8710  uint32_t PD_DRV_STRG : 5; /* Pull down drive strength */
8711  uint32_t PD_SLW_RT : 1; /* NMOS slew rate */
8712  const uint32_t Reserved_7to6 : 2; /* ALT_PINMUX_DCTD_IO_CFG_1_RSVD_7TO6 */
8713  uint32_t PU_DRV_STRG : 5; /* Pull up drive strength */
8714  uint32_t PU_SLW_RT : 1; /* PMOS slew rate */
8715  const uint32_t Reserved_15to14 : 2; /* ALT_PINMUX_DCTD_IO_CFG_1_RSVD_15TO14 */
8716  uint32_t WK_PU_EN : 1; /* Weak pull up signal */
8717  uint32_t INPUT_BUF_EN : 2; /* LVTTL input buffer enable signal */
8718  uint32_t RTRIM : 3; /* Bias trim bits */
8719  const uint32_t Reserved_31to22 : 10; /* ALT_PINMUX_DCTD_IO_CFG_1_RSVD_31TO22 */
8720 };
8721 
8722 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_CFG_1. */
8723 typedef volatile struct ALT_PINMUX_DCTD_IO_CFG_1_s ALT_PINMUX_DCTD_IO_CFG_1_t;
8724 #endif /* __ASSEMBLY__ */
8725 
8726 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_1 register. */
8727 #define ALT_PINMUX_DCTD_IO_CFG_1_RESET 0x000d0000
8728 /* The byte offset of the ALT_PINMUX_DCTD_IO_CFG_1 register from the beginning of the component. */
8729 #define ALT_PINMUX_DCTD_IO_CFG_1_OFST 0x104
8730 
8731 /*
8732  * Register : Dedicated IO 2 Configuration Register - configuration_dedicated_io_2
8733  *
8734  * This register is used to control the electrical behavior and direction of
8735  * Dedicated IO 2
8736  *
8737  * Only reset by a cold reset (ignores warm reset).
8738  *
8739  * Register Layout
8740  *
8741  * Bits | Access | Reset | Description
8742  * :--------|:-------|:------|:-------------------------------------
8743  * [4:0] | RW | 0x0 | Pull down drive strength
8744  * [5] | RW | 0x0 | NMOS slew rate
8745  * [7:6] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_2_RSVD_7TO6
8746  * [12:8] | RW | 0x0 | Pull up drive strength
8747  * [13] | RW | 0x0 | PMOS slew rate
8748  * [15:14] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_2_RSVD_15TO14
8749  * [16] | RW | 0x1 | Weak pull up signal
8750  * [18:17] | RW | 0x2 | LVTTL input buffer enable signal
8751  * [21:19] | RW | 0x1 | Bias trim bits
8752  * [31:22] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_2_RSVD_31TO22
8753  *
8754  */
8755 /*
8756  * Field : Pull down drive strength - PD_DRV_STRG
8757  *
8758  * Configuration bits for NMOS pull down drive strength.
8759  *
8760  * Pending Characterization
8761  *
8762  * Field Access Macros:
8763  *
8764  */
8765 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_2_PD_DRV_STRG register field. */
8766 #define ALT_PINMUX_DCTD_IO_CFG_2_PD_DRV_STRG_LSB 0
8767 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_2_PD_DRV_STRG register field. */
8768 #define ALT_PINMUX_DCTD_IO_CFG_2_PD_DRV_STRG_MSB 4
8769 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_2_PD_DRV_STRG register field. */
8770 #define ALT_PINMUX_DCTD_IO_CFG_2_PD_DRV_STRG_WIDTH 5
8771 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_2_PD_DRV_STRG register field value. */
8772 #define ALT_PINMUX_DCTD_IO_CFG_2_PD_DRV_STRG_SET_MSK 0x0000001f
8773 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_2_PD_DRV_STRG register field value. */
8774 #define ALT_PINMUX_DCTD_IO_CFG_2_PD_DRV_STRG_CLR_MSK 0xffffffe0
8775 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_2_PD_DRV_STRG register field. */
8776 #define ALT_PINMUX_DCTD_IO_CFG_2_PD_DRV_STRG_RESET 0x0
8777 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_2_PD_DRV_STRG field value from a register. */
8778 #define ALT_PINMUX_DCTD_IO_CFG_2_PD_DRV_STRG_GET(value) (((value) & 0x0000001f) >> 0)
8779 /* Produces a ALT_PINMUX_DCTD_IO_CFG_2_PD_DRV_STRG register field value suitable for setting the register. */
8780 #define ALT_PINMUX_DCTD_IO_CFG_2_PD_DRV_STRG_SET(value) (((value) << 0) & 0x0000001f)
8781 
8782 /*
8783  * Field : NMOS slew rate - PD_SLW_RT
8784  *
8785  * Configuration bit for output pull down slew rate control
8786  *
8787  * 0 : slow N slew
8788  *
8789  * 1 : fast N slew
8790  *
8791  * Field Access Macros:
8792  *
8793  */
8794 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_2_PD_SLW_RT register field. */
8795 #define ALT_PINMUX_DCTD_IO_CFG_2_PD_SLW_RT_LSB 5
8796 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_2_PD_SLW_RT register field. */
8797 #define ALT_PINMUX_DCTD_IO_CFG_2_PD_SLW_RT_MSB 5
8798 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_2_PD_SLW_RT register field. */
8799 #define ALT_PINMUX_DCTD_IO_CFG_2_PD_SLW_RT_WIDTH 1
8800 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_2_PD_SLW_RT register field value. */
8801 #define ALT_PINMUX_DCTD_IO_CFG_2_PD_SLW_RT_SET_MSK 0x00000020
8802 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_2_PD_SLW_RT register field value. */
8803 #define ALT_PINMUX_DCTD_IO_CFG_2_PD_SLW_RT_CLR_MSK 0xffffffdf
8804 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_2_PD_SLW_RT register field. */
8805 #define ALT_PINMUX_DCTD_IO_CFG_2_PD_SLW_RT_RESET 0x0
8806 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_2_PD_SLW_RT field value from a register. */
8807 #define ALT_PINMUX_DCTD_IO_CFG_2_PD_SLW_RT_GET(value) (((value) & 0x00000020) >> 5)
8808 /* Produces a ALT_PINMUX_DCTD_IO_CFG_2_PD_SLW_RT register field value suitable for setting the register. */
8809 #define ALT_PINMUX_DCTD_IO_CFG_2_PD_SLW_RT_SET(value) (((value) << 5) & 0x00000020)
8810 
8811 /*
8812  * Field : Reserved_7to6
8813  *
8814  * Reserved
8815  *
8816  * Field Access Macros:
8817  *
8818  */
8819 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_2_RSVD_7TO6 register field. */
8820 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_7TO6_LSB 6
8821 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_2_RSVD_7TO6 register field. */
8822 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_7TO6_MSB 7
8823 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_2_RSVD_7TO6 register field. */
8824 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_7TO6_WIDTH 2
8825 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_2_RSVD_7TO6 register field value. */
8826 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_7TO6_SET_MSK 0x000000c0
8827 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_2_RSVD_7TO6 register field value. */
8828 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_7TO6_CLR_MSK 0xffffff3f
8829 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_2_RSVD_7TO6 register field. */
8830 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_7TO6_RESET 0x0
8831 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_2_RSVD_7TO6 field value from a register. */
8832 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_7TO6_GET(value) (((value) & 0x000000c0) >> 6)
8833 /* Produces a ALT_PINMUX_DCTD_IO_CFG_2_RSVD_7TO6 register field value suitable for setting the register. */
8834 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_7TO6_SET(value) (((value) << 6) & 0x000000c0)
8835 
8836 /*
8837  * Field : Pull up drive strength - PU_DRV_STRG
8838  *
8839  * Configuration bits for PMOS pull up drive strength
8840  *
8841  * Pending Characterization
8842  *
8843  * Field Access Macros:
8844  *
8845  */
8846 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_2_PU_DRV_STRG register field. */
8847 #define ALT_PINMUX_DCTD_IO_CFG_2_PU_DRV_STRG_LSB 8
8848 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_2_PU_DRV_STRG register field. */
8849 #define ALT_PINMUX_DCTD_IO_CFG_2_PU_DRV_STRG_MSB 12
8850 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_2_PU_DRV_STRG register field. */
8851 #define ALT_PINMUX_DCTD_IO_CFG_2_PU_DRV_STRG_WIDTH 5
8852 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_2_PU_DRV_STRG register field value. */
8853 #define ALT_PINMUX_DCTD_IO_CFG_2_PU_DRV_STRG_SET_MSK 0x00001f00
8854 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_2_PU_DRV_STRG register field value. */
8855 #define ALT_PINMUX_DCTD_IO_CFG_2_PU_DRV_STRG_CLR_MSK 0xffffe0ff
8856 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_2_PU_DRV_STRG register field. */
8857 #define ALT_PINMUX_DCTD_IO_CFG_2_PU_DRV_STRG_RESET 0x0
8858 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_2_PU_DRV_STRG field value from a register. */
8859 #define ALT_PINMUX_DCTD_IO_CFG_2_PU_DRV_STRG_GET(value) (((value) & 0x00001f00) >> 8)
8860 /* Produces a ALT_PINMUX_DCTD_IO_CFG_2_PU_DRV_STRG register field value suitable for setting the register. */
8861 #define ALT_PINMUX_DCTD_IO_CFG_2_PU_DRV_STRG_SET(value) (((value) << 8) & 0x00001f00)
8862 
8863 /*
8864  * Field : PMOS slew rate - PU_SLW_RT
8865  *
8866  * Configuration bit for output pull up slew rate control
8867  *
8868  * 0 : slow P slew
8869  *
8870  * 1 : fast P slew
8871  *
8872  * Field Access Macros:
8873  *
8874  */
8875 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_2_PU_SLW_RT register field. */
8876 #define ALT_PINMUX_DCTD_IO_CFG_2_PU_SLW_RT_LSB 13
8877 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_2_PU_SLW_RT register field. */
8878 #define ALT_PINMUX_DCTD_IO_CFG_2_PU_SLW_RT_MSB 13
8879 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_2_PU_SLW_RT register field. */
8880 #define ALT_PINMUX_DCTD_IO_CFG_2_PU_SLW_RT_WIDTH 1
8881 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_2_PU_SLW_RT register field value. */
8882 #define ALT_PINMUX_DCTD_IO_CFG_2_PU_SLW_RT_SET_MSK 0x00002000
8883 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_2_PU_SLW_RT register field value. */
8884 #define ALT_PINMUX_DCTD_IO_CFG_2_PU_SLW_RT_CLR_MSK 0xffffdfff
8885 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_2_PU_SLW_RT register field. */
8886 #define ALT_PINMUX_DCTD_IO_CFG_2_PU_SLW_RT_RESET 0x0
8887 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_2_PU_SLW_RT field value from a register. */
8888 #define ALT_PINMUX_DCTD_IO_CFG_2_PU_SLW_RT_GET(value) (((value) & 0x00002000) >> 13)
8889 /* Produces a ALT_PINMUX_DCTD_IO_CFG_2_PU_SLW_RT register field value suitable for setting the register. */
8890 #define ALT_PINMUX_DCTD_IO_CFG_2_PU_SLW_RT_SET(value) (((value) << 13) & 0x00002000)
8891 
8892 /*
8893  * Field : Reserved_15to14
8894  *
8895  * Reserved
8896  *
8897  * Field Access Macros:
8898  *
8899  */
8900 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_2_RSVD_15TO14 register field. */
8901 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_15TO14_LSB 14
8902 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_2_RSVD_15TO14 register field. */
8903 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_15TO14_MSB 15
8904 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_2_RSVD_15TO14 register field. */
8905 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_15TO14_WIDTH 2
8906 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_2_RSVD_15TO14 register field value. */
8907 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_15TO14_SET_MSK 0x0000c000
8908 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_2_RSVD_15TO14 register field value. */
8909 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_15TO14_CLR_MSK 0xffff3fff
8910 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_2_RSVD_15TO14 register field. */
8911 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_15TO14_RESET 0x0
8912 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_2_RSVD_15TO14 field value from a register. */
8913 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_15TO14_GET(value) (((value) & 0x0000c000) >> 14)
8914 /* Produces a ALT_PINMUX_DCTD_IO_CFG_2_RSVD_15TO14 register field value suitable for setting the register. */
8915 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_15TO14_SET(value) (((value) << 14) & 0x0000c000)
8916 
8917 /*
8918  * Field : Weak pull up signal - WK_PU_EN
8919  *
8920  * Configuration bit for weak pull up enable
8921  *
8922  * 0 : weak pull up disable
8923  *
8924  * 1 : weak pull up enable
8925  *
8926  * Field Access Macros:
8927  *
8928  */
8929 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_2_WK_PU_EN register field. */
8930 #define ALT_PINMUX_DCTD_IO_CFG_2_WK_PU_EN_LSB 16
8931 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_2_WK_PU_EN register field. */
8932 #define ALT_PINMUX_DCTD_IO_CFG_2_WK_PU_EN_MSB 16
8933 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_2_WK_PU_EN register field. */
8934 #define ALT_PINMUX_DCTD_IO_CFG_2_WK_PU_EN_WIDTH 1
8935 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_2_WK_PU_EN register field value. */
8936 #define ALT_PINMUX_DCTD_IO_CFG_2_WK_PU_EN_SET_MSK 0x00010000
8937 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_2_WK_PU_EN register field value. */
8938 #define ALT_PINMUX_DCTD_IO_CFG_2_WK_PU_EN_CLR_MSK 0xfffeffff
8939 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_2_WK_PU_EN register field. */
8940 #define ALT_PINMUX_DCTD_IO_CFG_2_WK_PU_EN_RESET 0x1
8941 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_2_WK_PU_EN field value from a register. */
8942 #define ALT_PINMUX_DCTD_IO_CFG_2_WK_PU_EN_GET(value) (((value) & 0x00010000) >> 16)
8943 /* Produces a ALT_PINMUX_DCTD_IO_CFG_2_WK_PU_EN register field value suitable for setting the register. */
8944 #define ALT_PINMUX_DCTD_IO_CFG_2_WK_PU_EN_SET(value) (((value) << 16) & 0x00010000)
8945 
8946 /*
8947  * Field : LVTTL input buffer enable signal - INPUT_BUF_EN
8948  *
8949  * Configuration bits for LVTTL input buffer enable
8950  *
8951  * 00 : disable
8952  *
8953  * 01 : 1.8V TTL
8954  *
8955  * 10 : 2.5V/3.0V TTL
8956  *
8957  * 11 : 1.8V TTL
8958  *
8959  * Field Access Macros:
8960  *
8961  */
8962 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_2_INPUT_BUF_EN register field. */
8963 #define ALT_PINMUX_DCTD_IO_CFG_2_INPUT_BUF_EN_LSB 17
8964 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_2_INPUT_BUF_EN register field. */
8965 #define ALT_PINMUX_DCTD_IO_CFG_2_INPUT_BUF_EN_MSB 18
8966 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_2_INPUT_BUF_EN register field. */
8967 #define ALT_PINMUX_DCTD_IO_CFG_2_INPUT_BUF_EN_WIDTH 2
8968 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_2_INPUT_BUF_EN register field value. */
8969 #define ALT_PINMUX_DCTD_IO_CFG_2_INPUT_BUF_EN_SET_MSK 0x00060000
8970 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_2_INPUT_BUF_EN register field value. */
8971 #define ALT_PINMUX_DCTD_IO_CFG_2_INPUT_BUF_EN_CLR_MSK 0xfff9ffff
8972 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_2_INPUT_BUF_EN register field. */
8973 #define ALT_PINMUX_DCTD_IO_CFG_2_INPUT_BUF_EN_RESET 0x2
8974 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_2_INPUT_BUF_EN field value from a register. */
8975 #define ALT_PINMUX_DCTD_IO_CFG_2_INPUT_BUF_EN_GET(value) (((value) & 0x00060000) >> 17)
8976 /* Produces a ALT_PINMUX_DCTD_IO_CFG_2_INPUT_BUF_EN register field value suitable for setting the register. */
8977 #define ALT_PINMUX_DCTD_IO_CFG_2_INPUT_BUF_EN_SET(value) (((value) << 17) & 0x00060000)
8978 
8979 /*
8980  * Field : Bias trim bits - RTRIM
8981  *
8982  * Configuration bits for bias trim
8983  *
8984  * 000 : disable
8985  *
8986  * 001 : default
8987  *
8988  * 010 : trim low
8989  *
8990  * 100 : trim high
8991  *
8992  * others : invalid/reserved
8993  *
8994  * Field Access Macros:
8995  *
8996  */
8997 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_2_RTRIM register field. */
8998 #define ALT_PINMUX_DCTD_IO_CFG_2_RTRIM_LSB 19
8999 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_2_RTRIM register field. */
9000 #define ALT_PINMUX_DCTD_IO_CFG_2_RTRIM_MSB 21
9001 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_2_RTRIM register field. */
9002 #define ALT_PINMUX_DCTD_IO_CFG_2_RTRIM_WIDTH 3
9003 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_2_RTRIM register field value. */
9004 #define ALT_PINMUX_DCTD_IO_CFG_2_RTRIM_SET_MSK 0x00380000
9005 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_2_RTRIM register field value. */
9006 #define ALT_PINMUX_DCTD_IO_CFG_2_RTRIM_CLR_MSK 0xffc7ffff
9007 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_2_RTRIM register field. */
9008 #define ALT_PINMUX_DCTD_IO_CFG_2_RTRIM_RESET 0x1
9009 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_2_RTRIM field value from a register. */
9010 #define ALT_PINMUX_DCTD_IO_CFG_2_RTRIM_GET(value) (((value) & 0x00380000) >> 19)
9011 /* Produces a ALT_PINMUX_DCTD_IO_CFG_2_RTRIM register field value suitable for setting the register. */
9012 #define ALT_PINMUX_DCTD_IO_CFG_2_RTRIM_SET(value) (((value) << 19) & 0x00380000)
9013 
9014 /*
9015  * Field : Reserved_31to22
9016  *
9017  * Reserved
9018  *
9019  * Field Access Macros:
9020  *
9021  */
9022 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_2_RSVD_31TO22 register field. */
9023 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_31TO22_LSB 22
9024 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_2_RSVD_31TO22 register field. */
9025 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_31TO22_MSB 31
9026 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_2_RSVD_31TO22 register field. */
9027 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_31TO22_WIDTH 10
9028 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_2_RSVD_31TO22 register field value. */
9029 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_31TO22_SET_MSK 0xffc00000
9030 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_2_RSVD_31TO22 register field value. */
9031 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_31TO22_CLR_MSK 0x003fffff
9032 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_2_RSVD_31TO22 register field. */
9033 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_31TO22_RESET 0x0
9034 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_2_RSVD_31TO22 field value from a register. */
9035 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_31TO22_GET(value) (((value) & 0xffc00000) >> 22)
9036 /* Produces a ALT_PINMUX_DCTD_IO_CFG_2_RSVD_31TO22 register field value suitable for setting the register. */
9037 #define ALT_PINMUX_DCTD_IO_CFG_2_RSVD_31TO22_SET(value) (((value) << 22) & 0xffc00000)
9038 
9039 #ifndef __ASSEMBLY__
9040 /*
9041  * WARNING: The C register and register group struct declarations are provided for
9042  * convenience and illustrative purposes. They should, however, be used with
9043  * caution as the C language standard provides no guarantees about the alignment or
9044  * atomicity of device memory accesses. The recommended practice for writing
9045  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9046  * alt_write_word() functions.
9047  *
9048  * The struct declaration for register ALT_PINMUX_DCTD_IO_CFG_2.
9049  */
9050 struct ALT_PINMUX_DCTD_IO_CFG_2_s
9051 {
9052  uint32_t PD_DRV_STRG : 5; /* Pull down drive strength */
9053  uint32_t PD_SLW_RT : 1; /* NMOS slew rate */
9054  const uint32_t Reserved_7to6 : 2; /* ALT_PINMUX_DCTD_IO_CFG_2_RSVD_7TO6 */
9055  uint32_t PU_DRV_STRG : 5; /* Pull up drive strength */
9056  uint32_t PU_SLW_RT : 1; /* PMOS slew rate */
9057  const uint32_t Reserved_15to14 : 2; /* ALT_PINMUX_DCTD_IO_CFG_2_RSVD_15TO14 */
9058  uint32_t WK_PU_EN : 1; /* Weak pull up signal */
9059  uint32_t INPUT_BUF_EN : 2; /* LVTTL input buffer enable signal */
9060  uint32_t RTRIM : 3; /* Bias trim bits */
9061  const uint32_t Reserved_31to22 : 10; /* ALT_PINMUX_DCTD_IO_CFG_2_RSVD_31TO22 */
9062 };
9063 
9064 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_CFG_2. */
9065 typedef volatile struct ALT_PINMUX_DCTD_IO_CFG_2_s ALT_PINMUX_DCTD_IO_CFG_2_t;
9066 #endif /* __ASSEMBLY__ */
9067 
9068 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_2 register. */
9069 #define ALT_PINMUX_DCTD_IO_CFG_2_RESET 0x000d0000
9070 /* The byte offset of the ALT_PINMUX_DCTD_IO_CFG_2 register from the beginning of the component. */
9071 #define ALT_PINMUX_DCTD_IO_CFG_2_OFST 0x108
9072 
9073 /*
9074  * Register : Dedicated IO 3 Configuration Register - configuration_dedicated_io_3
9075  *
9076  * This register is used to control the electrical behavior and direction of
9077  * Dedicated IO 3
9078  *
9079  * Only reset by a cold reset (ignores warm reset).
9080  *
9081  * Register Layout
9082  *
9083  * Bits | Access | Reset | Description
9084  * :--------|:-------|:------|:-------------------------------------
9085  * [4:0] | RW | 0x8 | Pull down drive strength
9086  * [5] | RW | 0x0 | NMOS slew rate
9087  * [7:6] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6
9088  * [12:8] | RW | 0x0 | Pull up drive strength
9089  * [13] | RW | 0x0 | PMOS slew rate
9090  * [15:14] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14
9091  * [16] | RW | 0x0 | Weak pull up signal
9092  * [18:17] | RW | 0x2 | LVTTL input buffer enable signal
9093  * [21:19] | RW | 0x1 | Bias trim bits
9094  * [31:22] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22
9095  *
9096  */
9097 /*
9098  * Field : Pull down drive strength - PD_DRV_STRG
9099  *
9100  * Configuration bits for NMOS pull down drive strength.
9101  *
9102  * Pending Characterization
9103  *
9104  * Field Access Macros:
9105  *
9106  */
9107 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG register field. */
9108 #define ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_LSB 0
9109 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG register field. */
9110 #define ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_MSB 4
9111 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG register field. */
9112 #define ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_WIDTH 5
9113 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG register field value. */
9114 #define ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_SET_MSK 0x0000001f
9115 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG register field value. */
9116 #define ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_CLR_MSK 0xffffffe0
9117 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG register field. */
9118 #define ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_RESET 0x8
9119 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG field value from a register. */
9120 #define ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_GET(value) (((value) & 0x0000001f) >> 0)
9121 /* Produces a ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG register field value suitable for setting the register. */
9122 #define ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_SET(value) (((value) << 0) & 0x0000001f)
9123 
9124 /*
9125  * Field : NMOS slew rate - PD_SLW_RT
9126  *
9127  * Configuration bit for output pull down slew rate control
9128  *
9129  * 0 : slow N slew
9130  *
9131  * 1 : fast N slew
9132  *
9133  * Field Access Macros:
9134  *
9135  */
9136 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT register field. */
9137 #define ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_LSB 5
9138 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT register field. */
9139 #define ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_MSB 5
9140 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT register field. */
9141 #define ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_WIDTH 1
9142 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT register field value. */
9143 #define ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_SET_MSK 0x00000020
9144 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT register field value. */
9145 #define ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_CLR_MSK 0xffffffdf
9146 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT register field. */
9147 #define ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_RESET 0x0
9148 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT field value from a register. */
9149 #define ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_GET(value) (((value) & 0x00000020) >> 5)
9150 /* Produces a ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT register field value suitable for setting the register. */
9151 #define ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_SET(value) (((value) << 5) & 0x00000020)
9152 
9153 /*
9154  * Field : Reserved_7to6
9155  *
9156  * Reserved
9157  *
9158  * Field Access Macros:
9159  *
9160  */
9161 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6 register field. */
9162 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_LSB 6
9163 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6 register field. */
9164 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_MSB 7
9165 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6 register field. */
9166 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_WIDTH 2
9167 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6 register field value. */
9168 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_SET_MSK 0x000000c0
9169 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6 register field value. */
9170 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_CLR_MSK 0xffffff3f
9171 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6 register field. */
9172 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_RESET 0x0
9173 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6 field value from a register. */
9174 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_GET(value) (((value) & 0x000000c0) >> 6)
9175 /* Produces a ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6 register field value suitable for setting the register. */
9176 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_SET(value) (((value) << 6) & 0x000000c0)
9177 
9178 /*
9179  * Field : Pull up drive strength - PU_DRV_STRG
9180  *
9181  * Configuration bits for PMOS pull up drive strength
9182  *
9183  * Pending Characterization
9184  *
9185  * Field Access Macros:
9186  *
9187  */
9188 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG register field. */
9189 #define ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_LSB 8
9190 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG register field. */
9191 #define ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_MSB 12
9192 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG register field. */
9193 #define ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_WIDTH 5
9194 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG register field value. */
9195 #define ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_SET_MSK 0x00001f00
9196 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG register field value. */
9197 #define ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_CLR_MSK 0xffffe0ff
9198 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG register field. */
9199 #define ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_RESET 0x0
9200 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG field value from a register. */
9201 #define ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_GET(value) (((value) & 0x00001f00) >> 8)
9202 /* Produces a ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG register field value suitable for setting the register. */
9203 #define ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_SET(value) (((value) << 8) & 0x00001f00)
9204 
9205 /*
9206  * Field : PMOS slew rate - PU_SLW_RT
9207  *
9208  * Configuration bit for output pull up slew rate control
9209  *
9210  * 0 : slow P slew
9211  *
9212  * 1 : fast P slew
9213  *
9214  * Field Access Macros:
9215  *
9216  */
9217 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT register field. */
9218 #define ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_LSB 13
9219 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT register field. */
9220 #define ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_MSB 13
9221 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT register field. */
9222 #define ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_WIDTH 1
9223 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT register field value. */
9224 #define ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_SET_MSK 0x00002000
9225 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT register field value. */
9226 #define ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_CLR_MSK 0xffffdfff
9227 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT register field. */
9228 #define ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_RESET 0x0
9229 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT field value from a register. */
9230 #define ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_GET(value) (((value) & 0x00002000) >> 13)
9231 /* Produces a ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT register field value suitable for setting the register. */
9232 #define ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_SET(value) (((value) << 13) & 0x00002000)
9233 
9234 /*
9235  * Field : Reserved_15to14
9236  *
9237  * Reserved
9238  *
9239  * Field Access Macros:
9240  *
9241  */
9242 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14 register field. */
9243 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_LSB 14
9244 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14 register field. */
9245 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_MSB 15
9246 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14 register field. */
9247 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_WIDTH 2
9248 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14 register field value. */
9249 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_SET_MSK 0x0000c000
9250 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14 register field value. */
9251 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_CLR_MSK 0xffff3fff
9252 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14 register field. */
9253 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_RESET 0x0
9254 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14 field value from a register. */
9255 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_GET(value) (((value) & 0x0000c000) >> 14)
9256 /* Produces a ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14 register field value suitable for setting the register. */
9257 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_SET(value) (((value) << 14) & 0x0000c000)
9258 
9259 /*
9260  * Field : Weak pull up signal - WK_PU_EN
9261  *
9262  * Configuration bit for weak pull up enable
9263  *
9264  * 0 : weak pull up disable
9265  *
9266  * 1 : weak pull up enable
9267  *
9268  * Field Access Macros:
9269  *
9270  */
9271 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN register field. */
9272 #define ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_LSB 16
9273 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN register field. */
9274 #define ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_MSB 16
9275 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN register field. */
9276 #define ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_WIDTH 1
9277 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN register field value. */
9278 #define ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_SET_MSK 0x00010000
9279 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN register field value. */
9280 #define ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_CLR_MSK 0xfffeffff
9281 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN register field. */
9282 #define ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_RESET 0x0
9283 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN field value from a register. */
9284 #define ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_GET(value) (((value) & 0x00010000) >> 16)
9285 /* Produces a ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN register field value suitable for setting the register. */
9286 #define ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_SET(value) (((value) << 16) & 0x00010000)
9287 
9288 /*
9289  * Field : LVTTL input buffer enable signal - INPUT_BUF_EN
9290  *
9291  * Configuration bits for LVTTL input buffer enable
9292  *
9293  * 00 : disable
9294  *
9295  * 01 : 1.8V TTL
9296  *
9297  * 10 : 2.5V/3.0V TTL
9298  *
9299  * 11 : 1.8V TTL
9300  *
9301  * Field Access Macros:
9302  *
9303  */
9304 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN register field. */
9305 #define ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_LSB 17
9306 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN register field. */
9307 #define ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_MSB 18
9308 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN register field. */
9309 #define ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_WIDTH 2
9310 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN register field value. */
9311 #define ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_SET_MSK 0x00060000
9312 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN register field value. */
9313 #define ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_CLR_MSK 0xfff9ffff
9314 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN register field. */
9315 #define ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_RESET 0x2
9316 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN field value from a register. */
9317 #define ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_GET(value) (((value) & 0x00060000) >> 17)
9318 /* Produces a ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN register field value suitable for setting the register. */
9319 #define ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_SET(value) (((value) << 17) & 0x00060000)
9320 
9321 /*
9322  * Field : Bias trim bits - RTRIM
9323  *
9324  * Configuration bits for bias trim
9325  *
9326  * 000 : disable
9327  *
9328  * 001 : default
9329  *
9330  * 010 : trim low
9331  *
9332  * 100 : trim high
9333  *
9334  * others : invalid/reserved
9335  *
9336  * Field Access Macros:
9337  *
9338  */
9339 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_RTRIM register field. */
9340 #define ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_LSB 19
9341 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_RTRIM register field. */
9342 #define ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_MSB 21
9343 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_3_RTRIM register field. */
9344 #define ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_WIDTH 3
9345 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_3_RTRIM register field value. */
9346 #define ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_SET_MSK 0x00380000
9347 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_3_RTRIM register field value. */
9348 #define ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_CLR_MSK 0xffc7ffff
9349 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_3_RTRIM register field. */
9350 #define ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_RESET 0x1
9351 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_3_RTRIM field value from a register. */
9352 #define ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_GET(value) (((value) & 0x00380000) >> 19)
9353 /* Produces a ALT_PINMUX_DCTD_IO_CFG_3_RTRIM register field value suitable for setting the register. */
9354 #define ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_SET(value) (((value) << 19) & 0x00380000)
9355 
9356 /*
9357  * Field : Reserved_31to22
9358  *
9359  * Reserved
9360  *
9361  * Field Access Macros:
9362  *
9363  */
9364 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22 register field. */
9365 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_LSB 22
9366 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22 register field. */
9367 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_MSB 31
9368 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22 register field. */
9369 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_WIDTH 10
9370 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22 register field value. */
9371 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_SET_MSK 0xffc00000
9372 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22 register field value. */
9373 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_CLR_MSK 0x003fffff
9374 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22 register field. */
9375 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_RESET 0x0
9376 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22 field value from a register. */
9377 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_GET(value) (((value) & 0xffc00000) >> 22)
9378 /* Produces a ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22 register field value suitable for setting the register. */
9379 #define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_SET(value) (((value) << 22) & 0xffc00000)
9380 
9381 #ifndef __ASSEMBLY__
9382 /*
9383  * WARNING: The C register and register group struct declarations are provided for
9384  * convenience and illustrative purposes. They should, however, be used with
9385  * caution as the C language standard provides no guarantees about the alignment or
9386  * atomicity of device memory accesses. The recommended practice for writing
9387  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9388  * alt_write_word() functions.
9389  *
9390  * The struct declaration for register ALT_PINMUX_DCTD_IO_CFG_3.
9391  */
9392 struct ALT_PINMUX_DCTD_IO_CFG_3_s
9393 {
9394  uint32_t PD_DRV_STRG : 5; /* Pull down drive strength */
9395  uint32_t PD_SLW_RT : 1; /* NMOS slew rate */
9396  const uint32_t Reserved_7to6 : 2; /* ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6 */
9397  uint32_t PU_DRV_STRG : 5; /* Pull up drive strength */
9398  uint32_t PU_SLW_RT : 1; /* PMOS slew rate */
9399  const uint32_t Reserved_15to14 : 2; /* ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14 */
9400  uint32_t WK_PU_EN : 1; /* Weak pull up signal */
9401  uint32_t INPUT_BUF_EN : 2; /* LVTTL input buffer enable signal */
9402  uint32_t RTRIM : 3; /* Bias trim bits */
9403  const uint32_t Reserved_31to22 : 10; /* ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22 */
9404 };
9405 
9406 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_CFG_3. */
9407 typedef volatile struct ALT_PINMUX_DCTD_IO_CFG_3_s ALT_PINMUX_DCTD_IO_CFG_3_t;
9408 #endif /* __ASSEMBLY__ */
9409 
9410 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_3 register. */
9411 #define ALT_PINMUX_DCTD_IO_CFG_3_RESET 0x000c0008
9412 /* The byte offset of the ALT_PINMUX_DCTD_IO_CFG_3 register from the beginning of the component. */
9413 #define ALT_PINMUX_DCTD_IO_CFG_3_OFST 0x10c
9414 
9415 /*
9416  * Register : Dedicated IO 4 Configuration Register - configuration_dedicated_io_4
9417  *
9418  * This register is used to control the electrical behavior and direction of
9419  * Dedicated IO 4
9420  *
9421  * Only reset by a cold reset (ignores warm reset).
9422  *
9423  * Register Layout
9424  *
9425  * Bits | Access | Reset | Description
9426  * :--------|:-------|:------|:-------------------------------------
9427  * [4:0] | RW | 0x8 | Pull down drive strength
9428  * [5] | RW | 0x0 | NMOS slew rate
9429  * [7:6] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_4_RSVD_7TO6
9430  * [12:8] | RW | 0x0 | Pull up drive strength
9431  * [13] | RW | 0x0 | PMOS slew rate
9432  * [15:14] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_4_RSVD_15TO14
9433  * [16] | RW | 0x1 | Weak pull up signal
9434  * [18:17] | RW | 0x2 | LVTTL input buffer enable signal
9435  * [21:19] | RW | 0x1 | Bias trim bits
9436  * [31:22] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_4_RSVD_31TO22
9437  *
9438  */
9439 /*
9440  * Field : Pull down drive strength - PD_DRV_STRG
9441  *
9442  * Configuration bits for NMOS pull down drive strength.
9443  *
9444  * Pending Characterization
9445  *
9446  * Field Access Macros:
9447  *
9448  */
9449 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_4_PD_DRV_STRG register field. */
9450 #define ALT_PINMUX_DCTD_IO_CFG_4_PD_DRV_STRG_LSB 0
9451 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_4_PD_DRV_STRG register field. */
9452 #define ALT_PINMUX_DCTD_IO_CFG_4_PD_DRV_STRG_MSB 4
9453 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_4_PD_DRV_STRG register field. */
9454 #define ALT_PINMUX_DCTD_IO_CFG_4_PD_DRV_STRG_WIDTH 5
9455 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_4_PD_DRV_STRG register field value. */
9456 #define ALT_PINMUX_DCTD_IO_CFG_4_PD_DRV_STRG_SET_MSK 0x0000001f
9457 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_4_PD_DRV_STRG register field value. */
9458 #define ALT_PINMUX_DCTD_IO_CFG_4_PD_DRV_STRG_CLR_MSK 0xffffffe0
9459 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_4_PD_DRV_STRG register field. */
9460 #define ALT_PINMUX_DCTD_IO_CFG_4_PD_DRV_STRG_RESET 0x8
9461 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_4_PD_DRV_STRG field value from a register. */
9462 #define ALT_PINMUX_DCTD_IO_CFG_4_PD_DRV_STRG_GET(value) (((value) & 0x0000001f) >> 0)
9463 /* Produces a ALT_PINMUX_DCTD_IO_CFG_4_PD_DRV_STRG register field value suitable for setting the register. */
9464 #define ALT_PINMUX_DCTD_IO_CFG_4_PD_DRV_STRG_SET(value) (((value) << 0) & 0x0000001f)
9465 
9466 /*
9467  * Field : NMOS slew rate - PD_SLW_RT
9468  *
9469  * Configuration bit for output pull down slew rate control
9470  *
9471  * 0 : slow N slew
9472  *
9473  * 1 : fast N slew
9474  *
9475  * Field Access Macros:
9476  *
9477  */
9478 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_4_PD_SLW_RT register field. */
9479 #define ALT_PINMUX_DCTD_IO_CFG_4_PD_SLW_RT_LSB 5
9480 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_4_PD_SLW_RT register field. */
9481 #define ALT_PINMUX_DCTD_IO_CFG_4_PD_SLW_RT_MSB 5
9482 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_4_PD_SLW_RT register field. */
9483 #define ALT_PINMUX_DCTD_IO_CFG_4_PD_SLW_RT_WIDTH 1
9484 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_4_PD_SLW_RT register field value. */
9485 #define ALT_PINMUX_DCTD_IO_CFG_4_PD_SLW_RT_SET_MSK 0x00000020
9486 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_4_PD_SLW_RT register field value. */
9487 #define ALT_PINMUX_DCTD_IO_CFG_4_PD_SLW_RT_CLR_MSK 0xffffffdf
9488 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_4_PD_SLW_RT register field. */
9489 #define ALT_PINMUX_DCTD_IO_CFG_4_PD_SLW_RT_RESET 0x0
9490 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_4_PD_SLW_RT field value from a register. */
9491 #define ALT_PINMUX_DCTD_IO_CFG_4_PD_SLW_RT_GET(value) (((value) & 0x00000020) >> 5)
9492 /* Produces a ALT_PINMUX_DCTD_IO_CFG_4_PD_SLW_RT register field value suitable for setting the register. */
9493 #define ALT_PINMUX_DCTD_IO_CFG_4_PD_SLW_RT_SET(value) (((value) << 5) & 0x00000020)
9494 
9495 /*
9496  * Field : Reserved_7to6
9497  *
9498  * Reserved
9499  *
9500  * Field Access Macros:
9501  *
9502  */
9503 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_4_RSVD_7TO6 register field. */
9504 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_7TO6_LSB 6
9505 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_4_RSVD_7TO6 register field. */
9506 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_7TO6_MSB 7
9507 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_4_RSVD_7TO6 register field. */
9508 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_7TO6_WIDTH 2
9509 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_4_RSVD_7TO6 register field value. */
9510 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_7TO6_SET_MSK 0x000000c0
9511 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_4_RSVD_7TO6 register field value. */
9512 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_7TO6_CLR_MSK 0xffffff3f
9513 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_4_RSVD_7TO6 register field. */
9514 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_7TO6_RESET 0x0
9515 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_4_RSVD_7TO6 field value from a register. */
9516 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_7TO6_GET(value) (((value) & 0x000000c0) >> 6)
9517 /* Produces a ALT_PINMUX_DCTD_IO_CFG_4_RSVD_7TO6 register field value suitable for setting the register. */
9518 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_7TO6_SET(value) (((value) << 6) & 0x000000c0)
9519 
9520 /*
9521  * Field : Pull up drive strength - PU_DRV_STRG
9522  *
9523  * Configuration bits for PMOS pull up drive strength
9524  *
9525  * Pending Characterization
9526  *
9527  * Field Access Macros:
9528  *
9529  */
9530 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_4_PU_DRV_STRG register field. */
9531 #define ALT_PINMUX_DCTD_IO_CFG_4_PU_DRV_STRG_LSB 8
9532 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_4_PU_DRV_STRG register field. */
9533 #define ALT_PINMUX_DCTD_IO_CFG_4_PU_DRV_STRG_MSB 12
9534 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_4_PU_DRV_STRG register field. */
9535 #define ALT_PINMUX_DCTD_IO_CFG_4_PU_DRV_STRG_WIDTH 5
9536 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_4_PU_DRV_STRG register field value. */
9537 #define ALT_PINMUX_DCTD_IO_CFG_4_PU_DRV_STRG_SET_MSK 0x00001f00
9538 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_4_PU_DRV_STRG register field value. */
9539 #define ALT_PINMUX_DCTD_IO_CFG_4_PU_DRV_STRG_CLR_MSK 0xffffe0ff
9540 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_4_PU_DRV_STRG register field. */
9541 #define ALT_PINMUX_DCTD_IO_CFG_4_PU_DRV_STRG_RESET 0x0
9542 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_4_PU_DRV_STRG field value from a register. */
9543 #define ALT_PINMUX_DCTD_IO_CFG_4_PU_DRV_STRG_GET(value) (((value) & 0x00001f00) >> 8)
9544 /* Produces a ALT_PINMUX_DCTD_IO_CFG_4_PU_DRV_STRG register field value suitable for setting the register. */
9545 #define ALT_PINMUX_DCTD_IO_CFG_4_PU_DRV_STRG_SET(value) (((value) << 8) & 0x00001f00)
9546 
9547 /*
9548  * Field : PMOS slew rate - PU_SLW_RT
9549  *
9550  * Configuration bit for output pull up slew rate control
9551  *
9552  * 0 : slow P slew
9553  *
9554  * 1 : fast P slew
9555  *
9556  * Field Access Macros:
9557  *
9558  */
9559 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_4_PU_SLW_RT register field. */
9560 #define ALT_PINMUX_DCTD_IO_CFG_4_PU_SLW_RT_LSB 13
9561 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_4_PU_SLW_RT register field. */
9562 #define ALT_PINMUX_DCTD_IO_CFG_4_PU_SLW_RT_MSB 13
9563 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_4_PU_SLW_RT register field. */
9564 #define ALT_PINMUX_DCTD_IO_CFG_4_PU_SLW_RT_WIDTH 1
9565 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_4_PU_SLW_RT register field value. */
9566 #define ALT_PINMUX_DCTD_IO_CFG_4_PU_SLW_RT_SET_MSK 0x00002000
9567 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_4_PU_SLW_RT register field value. */
9568 #define ALT_PINMUX_DCTD_IO_CFG_4_PU_SLW_RT_CLR_MSK 0xffffdfff
9569 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_4_PU_SLW_RT register field. */
9570 #define ALT_PINMUX_DCTD_IO_CFG_4_PU_SLW_RT_RESET 0x0
9571 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_4_PU_SLW_RT field value from a register. */
9572 #define ALT_PINMUX_DCTD_IO_CFG_4_PU_SLW_RT_GET(value) (((value) & 0x00002000) >> 13)
9573 /* Produces a ALT_PINMUX_DCTD_IO_CFG_4_PU_SLW_RT register field value suitable for setting the register. */
9574 #define ALT_PINMUX_DCTD_IO_CFG_4_PU_SLW_RT_SET(value) (((value) << 13) & 0x00002000)
9575 
9576 /*
9577  * Field : Reserved_15to14
9578  *
9579  * Reserved
9580  *
9581  * Field Access Macros:
9582  *
9583  */
9584 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_4_RSVD_15TO14 register field. */
9585 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_15TO14_LSB 14
9586 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_4_RSVD_15TO14 register field. */
9587 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_15TO14_MSB 15
9588 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_4_RSVD_15TO14 register field. */
9589 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_15TO14_WIDTH 2
9590 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_4_RSVD_15TO14 register field value. */
9591 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_15TO14_SET_MSK 0x0000c000
9592 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_4_RSVD_15TO14 register field value. */
9593 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_15TO14_CLR_MSK 0xffff3fff
9594 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_4_RSVD_15TO14 register field. */
9595 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_15TO14_RESET 0x0
9596 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_4_RSVD_15TO14 field value from a register. */
9597 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_15TO14_GET(value) (((value) & 0x0000c000) >> 14)
9598 /* Produces a ALT_PINMUX_DCTD_IO_CFG_4_RSVD_15TO14 register field value suitable for setting the register. */
9599 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_15TO14_SET(value) (((value) << 14) & 0x0000c000)
9600 
9601 /*
9602  * Field : Weak pull up signal - WK_PU_EN
9603  *
9604  * Configuration bit for weak pull up enable
9605  *
9606  * 0 : weak pull up disable
9607  *
9608  * 1 : weak pull up enable
9609  *
9610  * Field Access Macros:
9611  *
9612  */
9613 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_4_WK_PU_EN register field. */
9614 #define ALT_PINMUX_DCTD_IO_CFG_4_WK_PU_EN_LSB 16
9615 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_4_WK_PU_EN register field. */
9616 #define ALT_PINMUX_DCTD_IO_CFG_4_WK_PU_EN_MSB 16
9617 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_4_WK_PU_EN register field. */
9618 #define ALT_PINMUX_DCTD_IO_CFG_4_WK_PU_EN_WIDTH 1
9619 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_4_WK_PU_EN register field value. */
9620 #define ALT_PINMUX_DCTD_IO_CFG_4_WK_PU_EN_SET_MSK 0x00010000
9621 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_4_WK_PU_EN register field value. */
9622 #define ALT_PINMUX_DCTD_IO_CFG_4_WK_PU_EN_CLR_MSK 0xfffeffff
9623 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_4_WK_PU_EN register field. */
9624 #define ALT_PINMUX_DCTD_IO_CFG_4_WK_PU_EN_RESET 0x1
9625 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_4_WK_PU_EN field value from a register. */
9626 #define ALT_PINMUX_DCTD_IO_CFG_4_WK_PU_EN_GET(value) (((value) & 0x00010000) >> 16)
9627 /* Produces a ALT_PINMUX_DCTD_IO_CFG_4_WK_PU_EN register field value suitable for setting the register. */
9628 #define ALT_PINMUX_DCTD_IO_CFG_4_WK_PU_EN_SET(value) (((value) << 16) & 0x00010000)
9629 
9630 /*
9631  * Field : LVTTL input buffer enable signal - INPUT_BUF_EN
9632  *
9633  * Configuration bits for LVTTL input buffer enable
9634  *
9635  * 00 : disable
9636  *
9637  * 01 : 1.8V TTL
9638  *
9639  * 10 : 2.5V/3.0V TTL
9640  *
9641  * 11 : 1.8V TTL
9642  *
9643  * Field Access Macros:
9644  *
9645  */
9646 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_4_INPUT_BUF_EN register field. */
9647 #define ALT_PINMUX_DCTD_IO_CFG_4_INPUT_BUF_EN_LSB 17
9648 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_4_INPUT_BUF_EN register field. */
9649 #define ALT_PINMUX_DCTD_IO_CFG_4_INPUT_BUF_EN_MSB 18
9650 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_4_INPUT_BUF_EN register field. */
9651 #define ALT_PINMUX_DCTD_IO_CFG_4_INPUT_BUF_EN_WIDTH 2
9652 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_4_INPUT_BUF_EN register field value. */
9653 #define ALT_PINMUX_DCTD_IO_CFG_4_INPUT_BUF_EN_SET_MSK 0x00060000
9654 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_4_INPUT_BUF_EN register field value. */
9655 #define ALT_PINMUX_DCTD_IO_CFG_4_INPUT_BUF_EN_CLR_MSK 0xfff9ffff
9656 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_4_INPUT_BUF_EN register field. */
9657 #define ALT_PINMUX_DCTD_IO_CFG_4_INPUT_BUF_EN_RESET 0x2
9658 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_4_INPUT_BUF_EN field value from a register. */
9659 #define ALT_PINMUX_DCTD_IO_CFG_4_INPUT_BUF_EN_GET(value) (((value) & 0x00060000) >> 17)
9660 /* Produces a ALT_PINMUX_DCTD_IO_CFG_4_INPUT_BUF_EN register field value suitable for setting the register. */
9661 #define ALT_PINMUX_DCTD_IO_CFG_4_INPUT_BUF_EN_SET(value) (((value) << 17) & 0x00060000)
9662 
9663 /*
9664  * Field : Bias trim bits - RTRIM
9665  *
9666  * Configuration bits for bias trim
9667  *
9668  * 000 : disable
9669  *
9670  * 001 : default
9671  *
9672  * 010 : trim low
9673  *
9674  * 100 : trim high
9675  *
9676  * others : invalid/reserved
9677  *
9678  * Field Access Macros:
9679  *
9680  */
9681 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_4_RTRIM register field. */
9682 #define ALT_PINMUX_DCTD_IO_CFG_4_RTRIM_LSB 19
9683 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_4_RTRIM register field. */
9684 #define ALT_PINMUX_DCTD_IO_CFG_4_RTRIM_MSB 21
9685 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_4_RTRIM register field. */
9686 #define ALT_PINMUX_DCTD_IO_CFG_4_RTRIM_WIDTH 3
9687 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_4_RTRIM register field value. */
9688 #define ALT_PINMUX_DCTD_IO_CFG_4_RTRIM_SET_MSK 0x00380000
9689 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_4_RTRIM register field value. */
9690 #define ALT_PINMUX_DCTD_IO_CFG_4_RTRIM_CLR_MSK 0xffc7ffff
9691 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_4_RTRIM register field. */
9692 #define ALT_PINMUX_DCTD_IO_CFG_4_RTRIM_RESET 0x1
9693 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_4_RTRIM field value from a register. */
9694 #define ALT_PINMUX_DCTD_IO_CFG_4_RTRIM_GET(value) (((value) & 0x00380000) >> 19)
9695 /* Produces a ALT_PINMUX_DCTD_IO_CFG_4_RTRIM register field value suitable for setting the register. */
9696 #define ALT_PINMUX_DCTD_IO_CFG_4_RTRIM_SET(value) (((value) << 19) & 0x00380000)
9697 
9698 /*
9699  * Field : Reserved_31to22
9700  *
9701  * Reserved
9702  *
9703  * Field Access Macros:
9704  *
9705  */
9706 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_4_RSVD_31TO22 register field. */
9707 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_31TO22_LSB 22
9708 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_4_RSVD_31TO22 register field. */
9709 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_31TO22_MSB 31
9710 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_4_RSVD_31TO22 register field. */
9711 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_31TO22_WIDTH 10
9712 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_4_RSVD_31TO22 register field value. */
9713 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_31TO22_SET_MSK 0xffc00000
9714 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_4_RSVD_31TO22 register field value. */
9715 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_31TO22_CLR_MSK 0x003fffff
9716 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_4_RSVD_31TO22 register field. */
9717 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_31TO22_RESET 0x0
9718 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_4_RSVD_31TO22 field value from a register. */
9719 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_31TO22_GET(value) (((value) & 0xffc00000) >> 22)
9720 /* Produces a ALT_PINMUX_DCTD_IO_CFG_4_RSVD_31TO22 register field value suitable for setting the register. */
9721 #define ALT_PINMUX_DCTD_IO_CFG_4_RSVD_31TO22_SET(value) (((value) << 22) & 0xffc00000)
9722 
9723 #ifndef __ASSEMBLY__
9724 /*
9725  * WARNING: The C register and register group struct declarations are provided for
9726  * convenience and illustrative purposes. They should, however, be used with
9727  * caution as the C language standard provides no guarantees about the alignment or
9728  * atomicity of device memory accesses. The recommended practice for writing
9729  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9730  * alt_write_word() functions.
9731  *
9732  * The struct declaration for register ALT_PINMUX_DCTD_IO_CFG_4.
9733  */
9734 struct ALT_PINMUX_DCTD_IO_CFG_4_s
9735 {
9736  uint32_t PD_DRV_STRG : 5; /* Pull down drive strength */
9737  uint32_t PD_SLW_RT : 1; /* NMOS slew rate */
9738  const uint32_t Reserved_7to6 : 2; /* ALT_PINMUX_DCTD_IO_CFG_4_RSVD_7TO6 */
9739  uint32_t PU_DRV_STRG : 5; /* Pull up drive strength */
9740  uint32_t PU_SLW_RT : 1; /* PMOS slew rate */
9741  const uint32_t Reserved_15to14 : 2; /* ALT_PINMUX_DCTD_IO_CFG_4_RSVD_15TO14 */
9742  uint32_t WK_PU_EN : 1; /* Weak pull up signal */
9743  uint32_t INPUT_BUF_EN : 2; /* LVTTL input buffer enable signal */
9744  uint32_t RTRIM : 3; /* Bias trim bits */
9745  const uint32_t Reserved_31to22 : 10; /* ALT_PINMUX_DCTD_IO_CFG_4_RSVD_31TO22 */
9746 };
9747 
9748 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_CFG_4. */
9749 typedef volatile struct ALT_PINMUX_DCTD_IO_CFG_4_s ALT_PINMUX_DCTD_IO_CFG_4_t;
9750 #endif /* __ASSEMBLY__ */
9751 
9752 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_4 register. */
9753 #define ALT_PINMUX_DCTD_IO_CFG_4_RESET 0x000d0008
9754 /* The byte offset of the ALT_PINMUX_DCTD_IO_CFG_4 register from the beginning of the component. */
9755 #define ALT_PINMUX_DCTD_IO_CFG_4_OFST 0x110
9756 
9757 /*
9758  * Register : Dedicated IO 5 Configuration Register - configuration_dedicated_io_5
9759  *
9760  * This register is used to control the electrical behavior and direction of
9761  * Dedicated IO 5
9762  *
9763  * Only reset by a cold reset (ignores warm reset).
9764  *
9765  * Register Layout
9766  *
9767  * Bits | Access | Reset | Description
9768  * :--------|:-------|:------|:-------------------------------------
9769  * [4:0] | RW | 0x8 | Pull down drive strength
9770  * [5] | RW | 0x0 | NMOS slew rate
9771  * [7:6] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_5_RSVD_7TO6
9772  * [12:8] | RW | 0x0 | Pull up drive strength
9773  * [13] | RW | 0x0 | PMOS slew rate
9774  * [15:14] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_5_RSVD_15TO14
9775  * [16] | RW | 0x1 | Weak pull up signal
9776  * [18:17] | RW | 0x2 | LVTTL input buffer enable signal
9777  * [21:19] | RW | 0x1 | Bias trim bits
9778  * [31:22] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_5_RSVD_31TO22
9779  *
9780  */
9781 /*
9782  * Field : Pull down drive strength - PD_DRV_STRG
9783  *
9784  * Configuration bits for NMOS pull down drive strength.
9785  *
9786  * Pending Characterization
9787  *
9788  * Field Access Macros:
9789  *
9790  */
9791 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_5_PD_DRV_STRG register field. */
9792 #define ALT_PINMUX_DCTD_IO_CFG_5_PD_DRV_STRG_LSB 0
9793 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_5_PD_DRV_STRG register field. */
9794 #define ALT_PINMUX_DCTD_IO_CFG_5_PD_DRV_STRG_MSB 4
9795 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_5_PD_DRV_STRG register field. */
9796 #define ALT_PINMUX_DCTD_IO_CFG_5_PD_DRV_STRG_WIDTH 5
9797 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_5_PD_DRV_STRG register field value. */
9798 #define ALT_PINMUX_DCTD_IO_CFG_5_PD_DRV_STRG_SET_MSK 0x0000001f
9799 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_5_PD_DRV_STRG register field value. */
9800 #define ALT_PINMUX_DCTD_IO_CFG_5_PD_DRV_STRG_CLR_MSK 0xffffffe0
9801 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_5_PD_DRV_STRG register field. */
9802 #define ALT_PINMUX_DCTD_IO_CFG_5_PD_DRV_STRG_RESET 0x8
9803 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_5_PD_DRV_STRG field value from a register. */
9804 #define ALT_PINMUX_DCTD_IO_CFG_5_PD_DRV_STRG_GET(value) (((value) & 0x0000001f) >> 0)
9805 /* Produces a ALT_PINMUX_DCTD_IO_CFG_5_PD_DRV_STRG register field value suitable for setting the register. */
9806 #define ALT_PINMUX_DCTD_IO_CFG_5_PD_DRV_STRG_SET(value) (((value) << 0) & 0x0000001f)
9807 
9808 /*
9809  * Field : NMOS slew rate - PD_SLW_RT
9810  *
9811  * Configuration bit for output pull down slew rate control
9812  *
9813  * 0 : slow N slew
9814  *
9815  * 1 : fast N slew
9816  *
9817  * Field Access Macros:
9818  *
9819  */
9820 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_5_PD_SLW_RT register field. */
9821 #define ALT_PINMUX_DCTD_IO_CFG_5_PD_SLW_RT_LSB 5
9822 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_5_PD_SLW_RT register field. */
9823 #define ALT_PINMUX_DCTD_IO_CFG_5_PD_SLW_RT_MSB 5
9824 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_5_PD_SLW_RT register field. */
9825 #define ALT_PINMUX_DCTD_IO_CFG_5_PD_SLW_RT_WIDTH 1
9826 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_5_PD_SLW_RT register field value. */
9827 #define ALT_PINMUX_DCTD_IO_CFG_5_PD_SLW_RT_SET_MSK 0x00000020
9828 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_5_PD_SLW_RT register field value. */
9829 #define ALT_PINMUX_DCTD_IO_CFG_5_PD_SLW_RT_CLR_MSK 0xffffffdf
9830 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_5_PD_SLW_RT register field. */
9831 #define ALT_PINMUX_DCTD_IO_CFG_5_PD_SLW_RT_RESET 0x0
9832 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_5_PD_SLW_RT field value from a register. */
9833 #define ALT_PINMUX_DCTD_IO_CFG_5_PD_SLW_RT_GET(value) (((value) & 0x00000020) >> 5)
9834 /* Produces a ALT_PINMUX_DCTD_IO_CFG_5_PD_SLW_RT register field value suitable for setting the register. */
9835 #define ALT_PINMUX_DCTD_IO_CFG_5_PD_SLW_RT_SET(value) (((value) << 5) & 0x00000020)
9836 
9837 /*
9838  * Field : Reserved_7to6
9839  *
9840  * Reserved
9841  *
9842  * Field Access Macros:
9843  *
9844  */
9845 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_5_RSVD_7TO6 register field. */
9846 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_7TO6_LSB 6
9847 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_5_RSVD_7TO6 register field. */
9848 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_7TO6_MSB 7
9849 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_5_RSVD_7TO6 register field. */
9850 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_7TO6_WIDTH 2
9851 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_5_RSVD_7TO6 register field value. */
9852 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_7TO6_SET_MSK 0x000000c0
9853 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_5_RSVD_7TO6 register field value. */
9854 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_7TO6_CLR_MSK 0xffffff3f
9855 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_5_RSVD_7TO6 register field. */
9856 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_7TO6_RESET 0x0
9857 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_5_RSVD_7TO6 field value from a register. */
9858 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_7TO6_GET(value) (((value) & 0x000000c0) >> 6)
9859 /* Produces a ALT_PINMUX_DCTD_IO_CFG_5_RSVD_7TO6 register field value suitable for setting the register. */
9860 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_7TO6_SET(value) (((value) << 6) & 0x000000c0)
9861 
9862 /*
9863  * Field : Pull up drive strength - PU_DRV_STRG
9864  *
9865  * Configuration bits for PMOS pull up drive strength
9866  *
9867  * Pending Characterization
9868  *
9869  * Field Access Macros:
9870  *
9871  */
9872 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_5_PU_DRV_STRG register field. */
9873 #define ALT_PINMUX_DCTD_IO_CFG_5_PU_DRV_STRG_LSB 8
9874 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_5_PU_DRV_STRG register field. */
9875 #define ALT_PINMUX_DCTD_IO_CFG_5_PU_DRV_STRG_MSB 12
9876 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_5_PU_DRV_STRG register field. */
9877 #define ALT_PINMUX_DCTD_IO_CFG_5_PU_DRV_STRG_WIDTH 5
9878 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_5_PU_DRV_STRG register field value. */
9879 #define ALT_PINMUX_DCTD_IO_CFG_5_PU_DRV_STRG_SET_MSK 0x00001f00
9880 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_5_PU_DRV_STRG register field value. */
9881 #define ALT_PINMUX_DCTD_IO_CFG_5_PU_DRV_STRG_CLR_MSK 0xffffe0ff
9882 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_5_PU_DRV_STRG register field. */
9883 #define ALT_PINMUX_DCTD_IO_CFG_5_PU_DRV_STRG_RESET 0x0
9884 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_5_PU_DRV_STRG field value from a register. */
9885 #define ALT_PINMUX_DCTD_IO_CFG_5_PU_DRV_STRG_GET(value) (((value) & 0x00001f00) >> 8)
9886 /* Produces a ALT_PINMUX_DCTD_IO_CFG_5_PU_DRV_STRG register field value suitable for setting the register. */
9887 #define ALT_PINMUX_DCTD_IO_CFG_5_PU_DRV_STRG_SET(value) (((value) << 8) & 0x00001f00)
9888 
9889 /*
9890  * Field : PMOS slew rate - PU_SLW_RT
9891  *
9892  * Configuration bit for output pull up slew rate control
9893  *
9894  * 0 : slow P slew
9895  *
9896  * 1 : fast P slew
9897  *
9898  * Field Access Macros:
9899  *
9900  */
9901 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_5_PU_SLW_RT register field. */
9902 #define ALT_PINMUX_DCTD_IO_CFG_5_PU_SLW_RT_LSB 13
9903 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_5_PU_SLW_RT register field. */
9904 #define ALT_PINMUX_DCTD_IO_CFG_5_PU_SLW_RT_MSB 13
9905 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_5_PU_SLW_RT register field. */
9906 #define ALT_PINMUX_DCTD_IO_CFG_5_PU_SLW_RT_WIDTH 1
9907 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_5_PU_SLW_RT register field value. */
9908 #define ALT_PINMUX_DCTD_IO_CFG_5_PU_SLW_RT_SET_MSK 0x00002000
9909 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_5_PU_SLW_RT register field value. */
9910 #define ALT_PINMUX_DCTD_IO_CFG_5_PU_SLW_RT_CLR_MSK 0xffffdfff
9911 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_5_PU_SLW_RT register field. */
9912 #define ALT_PINMUX_DCTD_IO_CFG_5_PU_SLW_RT_RESET 0x0
9913 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_5_PU_SLW_RT field value from a register. */
9914 #define ALT_PINMUX_DCTD_IO_CFG_5_PU_SLW_RT_GET(value) (((value) & 0x00002000) >> 13)
9915 /* Produces a ALT_PINMUX_DCTD_IO_CFG_5_PU_SLW_RT register field value suitable for setting the register. */
9916 #define ALT_PINMUX_DCTD_IO_CFG_5_PU_SLW_RT_SET(value) (((value) << 13) & 0x00002000)
9917 
9918 /*
9919  * Field : Reserved_15to14
9920  *
9921  * Reserved
9922  *
9923  * Field Access Macros:
9924  *
9925  */
9926 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_5_RSVD_15TO14 register field. */
9927 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_15TO14_LSB 14
9928 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_5_RSVD_15TO14 register field. */
9929 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_15TO14_MSB 15
9930 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_5_RSVD_15TO14 register field. */
9931 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_15TO14_WIDTH 2
9932 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_5_RSVD_15TO14 register field value. */
9933 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_15TO14_SET_MSK 0x0000c000
9934 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_5_RSVD_15TO14 register field value. */
9935 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_15TO14_CLR_MSK 0xffff3fff
9936 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_5_RSVD_15TO14 register field. */
9937 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_15TO14_RESET 0x0
9938 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_5_RSVD_15TO14 field value from a register. */
9939 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_15TO14_GET(value) (((value) & 0x0000c000) >> 14)
9940 /* Produces a ALT_PINMUX_DCTD_IO_CFG_5_RSVD_15TO14 register field value suitable for setting the register. */
9941 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_15TO14_SET(value) (((value) << 14) & 0x0000c000)
9942 
9943 /*
9944  * Field : Weak pull up signal - WK_PU_EN
9945  *
9946  * Configuration bit for weak pull up enable
9947  *
9948  * 0 : weak pull up disable
9949  *
9950  * 1 : weak pull up enable
9951  *
9952  * Field Access Macros:
9953  *
9954  */
9955 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_5_WK_PU_EN register field. */
9956 #define ALT_PINMUX_DCTD_IO_CFG_5_WK_PU_EN_LSB 16
9957 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_5_WK_PU_EN register field. */
9958 #define ALT_PINMUX_DCTD_IO_CFG_5_WK_PU_EN_MSB 16
9959 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_5_WK_PU_EN register field. */
9960 #define ALT_PINMUX_DCTD_IO_CFG_5_WK_PU_EN_WIDTH 1
9961 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_5_WK_PU_EN register field value. */
9962 #define ALT_PINMUX_DCTD_IO_CFG_5_WK_PU_EN_SET_MSK 0x00010000
9963 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_5_WK_PU_EN register field value. */
9964 #define ALT_PINMUX_DCTD_IO_CFG_5_WK_PU_EN_CLR_MSK 0xfffeffff
9965 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_5_WK_PU_EN register field. */
9966 #define ALT_PINMUX_DCTD_IO_CFG_5_WK_PU_EN_RESET 0x1
9967 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_5_WK_PU_EN field value from a register. */
9968 #define ALT_PINMUX_DCTD_IO_CFG_5_WK_PU_EN_GET(value) (((value) & 0x00010000) >> 16)
9969 /* Produces a ALT_PINMUX_DCTD_IO_CFG_5_WK_PU_EN register field value suitable for setting the register. */
9970 #define ALT_PINMUX_DCTD_IO_CFG_5_WK_PU_EN_SET(value) (((value) << 16) & 0x00010000)
9971 
9972 /*
9973  * Field : LVTTL input buffer enable signal - INPUT_BUF_EN
9974  *
9975  * Configuration bits for LVTTL input buffer enable
9976  *
9977  * 00 : disable
9978  *
9979  * 01 : 1.8V TTL
9980  *
9981  * 10 : 2.5V/3.0V TTL
9982  *
9983  * 11 : 1.8V TTL
9984  *
9985  * Field Access Macros:
9986  *
9987  */
9988 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_5_INPUT_BUF_EN register field. */
9989 #define ALT_PINMUX_DCTD_IO_CFG_5_INPUT_BUF_EN_LSB 17
9990 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_5_INPUT_BUF_EN register field. */
9991 #define ALT_PINMUX_DCTD_IO_CFG_5_INPUT_BUF_EN_MSB 18
9992 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_5_INPUT_BUF_EN register field. */
9993 #define ALT_PINMUX_DCTD_IO_CFG_5_INPUT_BUF_EN_WIDTH 2
9994 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_5_INPUT_BUF_EN register field value. */
9995 #define ALT_PINMUX_DCTD_IO_CFG_5_INPUT_BUF_EN_SET_MSK 0x00060000
9996 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_5_INPUT_BUF_EN register field value. */
9997 #define ALT_PINMUX_DCTD_IO_CFG_5_INPUT_BUF_EN_CLR_MSK 0xfff9ffff
9998 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_5_INPUT_BUF_EN register field. */
9999 #define ALT_PINMUX_DCTD_IO_CFG_5_INPUT_BUF_EN_RESET 0x2
10000 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_5_INPUT_BUF_EN field value from a register. */
10001 #define ALT_PINMUX_DCTD_IO_CFG_5_INPUT_BUF_EN_GET(value) (((value) & 0x00060000) >> 17)
10002 /* Produces a ALT_PINMUX_DCTD_IO_CFG_5_INPUT_BUF_EN register field value suitable for setting the register. */
10003 #define ALT_PINMUX_DCTD_IO_CFG_5_INPUT_BUF_EN_SET(value) (((value) << 17) & 0x00060000)
10004 
10005 /*
10006  * Field : Bias trim bits - RTRIM
10007  *
10008  * Configuration bits for bias trim
10009  *
10010  * 000 : disable
10011  *
10012  * 001 : default
10013  *
10014  * 010 : trim low
10015  *
10016  * 100 : trim high
10017  *
10018  * others : invalid/reserved
10019  *
10020  * Field Access Macros:
10021  *
10022  */
10023 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_5_RTRIM register field. */
10024 #define ALT_PINMUX_DCTD_IO_CFG_5_RTRIM_LSB 19
10025 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_5_RTRIM register field. */
10026 #define ALT_PINMUX_DCTD_IO_CFG_5_RTRIM_MSB 21
10027 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_5_RTRIM register field. */
10028 #define ALT_PINMUX_DCTD_IO_CFG_5_RTRIM_WIDTH 3
10029 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_5_RTRIM register field value. */
10030 #define ALT_PINMUX_DCTD_IO_CFG_5_RTRIM_SET_MSK 0x00380000
10031 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_5_RTRIM register field value. */
10032 #define ALT_PINMUX_DCTD_IO_CFG_5_RTRIM_CLR_MSK 0xffc7ffff
10033 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_5_RTRIM register field. */
10034 #define ALT_PINMUX_DCTD_IO_CFG_5_RTRIM_RESET 0x1
10035 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_5_RTRIM field value from a register. */
10036 #define ALT_PINMUX_DCTD_IO_CFG_5_RTRIM_GET(value) (((value) & 0x00380000) >> 19)
10037 /* Produces a ALT_PINMUX_DCTD_IO_CFG_5_RTRIM register field value suitable for setting the register. */
10038 #define ALT_PINMUX_DCTD_IO_CFG_5_RTRIM_SET(value) (((value) << 19) & 0x00380000)
10039 
10040 /*
10041  * Field : Reserved_31to22
10042  *
10043  * Reserved
10044  *
10045  * Field Access Macros:
10046  *
10047  */
10048 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_5_RSVD_31TO22 register field. */
10049 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_31TO22_LSB 22
10050 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_5_RSVD_31TO22 register field. */
10051 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_31TO22_MSB 31
10052 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_5_RSVD_31TO22 register field. */
10053 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_31TO22_WIDTH 10
10054 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_5_RSVD_31TO22 register field value. */
10055 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_31TO22_SET_MSK 0xffc00000
10056 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_5_RSVD_31TO22 register field value. */
10057 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_31TO22_CLR_MSK 0x003fffff
10058 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_5_RSVD_31TO22 register field. */
10059 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_31TO22_RESET 0x0
10060 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_5_RSVD_31TO22 field value from a register. */
10061 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_31TO22_GET(value) (((value) & 0xffc00000) >> 22)
10062 /* Produces a ALT_PINMUX_DCTD_IO_CFG_5_RSVD_31TO22 register field value suitable for setting the register. */
10063 #define ALT_PINMUX_DCTD_IO_CFG_5_RSVD_31TO22_SET(value) (((value) << 22) & 0xffc00000)
10064 
10065 #ifndef __ASSEMBLY__
10066 /*
10067  * WARNING: The C register and register group struct declarations are provided for
10068  * convenience and illustrative purposes. They should, however, be used with
10069  * caution as the C language standard provides no guarantees about the alignment or
10070  * atomicity of device memory accesses. The recommended practice for writing
10071  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10072  * alt_write_word() functions.
10073  *
10074  * The struct declaration for register ALT_PINMUX_DCTD_IO_CFG_5.
10075  */
10076 struct ALT_PINMUX_DCTD_IO_CFG_5_s
10077 {
10078  uint32_t PD_DRV_STRG : 5; /* Pull down drive strength */
10079  uint32_t PD_SLW_RT : 1; /* NMOS slew rate */
10080  const uint32_t Reserved_7to6 : 2; /* ALT_PINMUX_DCTD_IO_CFG_5_RSVD_7TO6 */
10081  uint32_t PU_DRV_STRG : 5; /* Pull up drive strength */
10082  uint32_t PU_SLW_RT : 1; /* PMOS slew rate */
10083  const uint32_t Reserved_15to14 : 2; /* ALT_PINMUX_DCTD_IO_CFG_5_RSVD_15TO14 */
10084  uint32_t WK_PU_EN : 1; /* Weak pull up signal */
10085  uint32_t INPUT_BUF_EN : 2; /* LVTTL input buffer enable signal */
10086  uint32_t RTRIM : 3; /* Bias trim bits */
10087  const uint32_t Reserved_31to22 : 10; /* ALT_PINMUX_DCTD_IO_CFG_5_RSVD_31TO22 */
10088 };
10089 
10090 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_CFG_5. */
10091 typedef volatile struct ALT_PINMUX_DCTD_IO_CFG_5_s ALT_PINMUX_DCTD_IO_CFG_5_t;
10092 #endif /* __ASSEMBLY__ */
10093 
10094 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_5 register. */
10095 #define ALT_PINMUX_DCTD_IO_CFG_5_RESET 0x000d0008
10096 /* The byte offset of the ALT_PINMUX_DCTD_IO_CFG_5 register from the beginning of the component. */
10097 #define ALT_PINMUX_DCTD_IO_CFG_5_OFST 0x114
10098 
10099 /*
10100  * Register : Dedicated IO 6 Configuration Register - configuration_dedicated_io_6
10101  *
10102  * This register is used to control the electrical behavior and direction of
10103  * Dedicated IO 6
10104  *
10105  * Only reset by a cold reset (ignores warm reset).
10106  *
10107  * Register Layout
10108  *
10109  * Bits | Access | Reset | Description
10110  * :--------|:-------|:------|:-------------------------------------
10111  * [4:0] | RW | 0x8 | Pull down drive strength
10112  * [5] | RW | 0x0 | NMOS slew rate
10113  * [7:6] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_6_RSVD_7TO6
10114  * [12:8] | RW | 0x0 | Pull up drive strength
10115  * [13] | RW | 0x0 | PMOS slew rate
10116  * [15:14] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_6_RSVD_15TO14
10117  * [16] | RW | 0x1 | Weak pull up signal
10118  * [18:17] | RW | 0x2 | LVTTL input buffer enable signal
10119  * [21:19] | RW | 0x1 | Bias trim bits
10120  * [31:22] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_6_RSVD_31TO22
10121  *
10122  */
10123 /*
10124  * Field : Pull down drive strength - PD_DRV_STRG
10125  *
10126  * Configuration bits for NMOS pull down drive strength.
10127  *
10128  * Pending Characterization
10129  *
10130  * Field Access Macros:
10131  *
10132  */
10133 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_6_PD_DRV_STRG register field. */
10134 #define ALT_PINMUX_DCTD_IO_CFG_6_PD_DRV_STRG_LSB 0
10135 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_6_PD_DRV_STRG register field. */
10136 #define ALT_PINMUX_DCTD_IO_CFG_6_PD_DRV_STRG_MSB 4
10137 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_6_PD_DRV_STRG register field. */
10138 #define ALT_PINMUX_DCTD_IO_CFG_6_PD_DRV_STRG_WIDTH 5
10139 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_6_PD_DRV_STRG register field value. */
10140 #define ALT_PINMUX_DCTD_IO_CFG_6_PD_DRV_STRG_SET_MSK 0x0000001f
10141 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_6_PD_DRV_STRG register field value. */
10142 #define ALT_PINMUX_DCTD_IO_CFG_6_PD_DRV_STRG_CLR_MSK 0xffffffe0
10143 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_6_PD_DRV_STRG register field. */
10144 #define ALT_PINMUX_DCTD_IO_CFG_6_PD_DRV_STRG_RESET 0x8
10145 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_6_PD_DRV_STRG field value from a register. */
10146 #define ALT_PINMUX_DCTD_IO_CFG_6_PD_DRV_STRG_GET(value) (((value) & 0x0000001f) >> 0)
10147 /* Produces a ALT_PINMUX_DCTD_IO_CFG_6_PD_DRV_STRG register field value suitable for setting the register. */
10148 #define ALT_PINMUX_DCTD_IO_CFG_6_PD_DRV_STRG_SET(value) (((value) << 0) & 0x0000001f)
10149 
10150 /*
10151  * Field : NMOS slew rate - PD_SLW_RT
10152  *
10153  * Configuration bit for output pull down slew rate control
10154  *
10155  * 0 : slow N slew
10156  *
10157  * 1 : fast N slew
10158  *
10159  * Field Access Macros:
10160  *
10161  */
10162 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_6_PD_SLW_RT register field. */
10163 #define ALT_PINMUX_DCTD_IO_CFG_6_PD_SLW_RT_LSB 5
10164 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_6_PD_SLW_RT register field. */
10165 #define ALT_PINMUX_DCTD_IO_CFG_6_PD_SLW_RT_MSB 5
10166 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_6_PD_SLW_RT register field. */
10167 #define ALT_PINMUX_DCTD_IO_CFG_6_PD_SLW_RT_WIDTH 1
10168 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_6_PD_SLW_RT register field value. */
10169 #define ALT_PINMUX_DCTD_IO_CFG_6_PD_SLW_RT_SET_MSK 0x00000020
10170 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_6_PD_SLW_RT register field value. */
10171 #define ALT_PINMUX_DCTD_IO_CFG_6_PD_SLW_RT_CLR_MSK 0xffffffdf
10172 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_6_PD_SLW_RT register field. */
10173 #define ALT_PINMUX_DCTD_IO_CFG_6_PD_SLW_RT_RESET 0x0
10174 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_6_PD_SLW_RT field value from a register. */
10175 #define ALT_PINMUX_DCTD_IO_CFG_6_PD_SLW_RT_GET(value) (((value) & 0x00000020) >> 5)
10176 /* Produces a ALT_PINMUX_DCTD_IO_CFG_6_PD_SLW_RT register field value suitable for setting the register. */
10177 #define ALT_PINMUX_DCTD_IO_CFG_6_PD_SLW_RT_SET(value) (((value) << 5) & 0x00000020)
10178 
10179 /*
10180  * Field : Reserved_7to6
10181  *
10182  * Reserved
10183  *
10184  * Field Access Macros:
10185  *
10186  */
10187 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_6_RSVD_7TO6 register field. */
10188 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_7TO6_LSB 6
10189 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_6_RSVD_7TO6 register field. */
10190 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_7TO6_MSB 7
10191 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_6_RSVD_7TO6 register field. */
10192 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_7TO6_WIDTH 2
10193 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_6_RSVD_7TO6 register field value. */
10194 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_7TO6_SET_MSK 0x000000c0
10195 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_6_RSVD_7TO6 register field value. */
10196 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_7TO6_CLR_MSK 0xffffff3f
10197 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_6_RSVD_7TO6 register field. */
10198 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_7TO6_RESET 0x0
10199 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_6_RSVD_7TO6 field value from a register. */
10200 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_7TO6_GET(value) (((value) & 0x000000c0) >> 6)
10201 /* Produces a ALT_PINMUX_DCTD_IO_CFG_6_RSVD_7TO6 register field value suitable for setting the register. */
10202 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_7TO6_SET(value) (((value) << 6) & 0x000000c0)
10203 
10204 /*
10205  * Field : Pull up drive strength - PU_DRV_STRG
10206  *
10207  * Configuration bits for PMOS pull up drive strength
10208  *
10209  * Pending Characterization
10210  *
10211  * Field Access Macros:
10212  *
10213  */
10214 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_6_PU_DRV_STRG register field. */
10215 #define ALT_PINMUX_DCTD_IO_CFG_6_PU_DRV_STRG_LSB 8
10216 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_6_PU_DRV_STRG register field. */
10217 #define ALT_PINMUX_DCTD_IO_CFG_6_PU_DRV_STRG_MSB 12
10218 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_6_PU_DRV_STRG register field. */
10219 #define ALT_PINMUX_DCTD_IO_CFG_6_PU_DRV_STRG_WIDTH 5
10220 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_6_PU_DRV_STRG register field value. */
10221 #define ALT_PINMUX_DCTD_IO_CFG_6_PU_DRV_STRG_SET_MSK 0x00001f00
10222 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_6_PU_DRV_STRG register field value. */
10223 #define ALT_PINMUX_DCTD_IO_CFG_6_PU_DRV_STRG_CLR_MSK 0xffffe0ff
10224 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_6_PU_DRV_STRG register field. */
10225 #define ALT_PINMUX_DCTD_IO_CFG_6_PU_DRV_STRG_RESET 0x0
10226 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_6_PU_DRV_STRG field value from a register. */
10227 #define ALT_PINMUX_DCTD_IO_CFG_6_PU_DRV_STRG_GET(value) (((value) & 0x00001f00) >> 8)
10228 /* Produces a ALT_PINMUX_DCTD_IO_CFG_6_PU_DRV_STRG register field value suitable for setting the register. */
10229 #define ALT_PINMUX_DCTD_IO_CFG_6_PU_DRV_STRG_SET(value) (((value) << 8) & 0x00001f00)
10230 
10231 /*
10232  * Field : PMOS slew rate - PU_SLW_RT
10233  *
10234  * Configuration bit for output pull up slew rate control
10235  *
10236  * 0 : slow P slew
10237  *
10238  * 1 : fast P slew
10239  *
10240  * Field Access Macros:
10241  *
10242  */
10243 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_6_PU_SLW_RT register field. */
10244 #define ALT_PINMUX_DCTD_IO_CFG_6_PU_SLW_RT_LSB 13
10245 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_6_PU_SLW_RT register field. */
10246 #define ALT_PINMUX_DCTD_IO_CFG_6_PU_SLW_RT_MSB 13
10247 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_6_PU_SLW_RT register field. */
10248 #define ALT_PINMUX_DCTD_IO_CFG_6_PU_SLW_RT_WIDTH 1
10249 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_6_PU_SLW_RT register field value. */
10250 #define ALT_PINMUX_DCTD_IO_CFG_6_PU_SLW_RT_SET_MSK 0x00002000
10251 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_6_PU_SLW_RT register field value. */
10252 #define ALT_PINMUX_DCTD_IO_CFG_6_PU_SLW_RT_CLR_MSK 0xffffdfff
10253 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_6_PU_SLW_RT register field. */
10254 #define ALT_PINMUX_DCTD_IO_CFG_6_PU_SLW_RT_RESET 0x0
10255 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_6_PU_SLW_RT field value from a register. */
10256 #define ALT_PINMUX_DCTD_IO_CFG_6_PU_SLW_RT_GET(value) (((value) & 0x00002000) >> 13)
10257 /* Produces a ALT_PINMUX_DCTD_IO_CFG_6_PU_SLW_RT register field value suitable for setting the register. */
10258 #define ALT_PINMUX_DCTD_IO_CFG_6_PU_SLW_RT_SET(value) (((value) << 13) & 0x00002000)
10259 
10260 /*
10261  * Field : Reserved_15to14
10262  *
10263  * Reserved
10264  *
10265  * Field Access Macros:
10266  *
10267  */
10268 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_6_RSVD_15TO14 register field. */
10269 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_15TO14_LSB 14
10270 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_6_RSVD_15TO14 register field. */
10271 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_15TO14_MSB 15
10272 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_6_RSVD_15TO14 register field. */
10273 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_15TO14_WIDTH 2
10274 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_6_RSVD_15TO14 register field value. */
10275 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_15TO14_SET_MSK 0x0000c000
10276 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_6_RSVD_15TO14 register field value. */
10277 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_15TO14_CLR_MSK 0xffff3fff
10278 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_6_RSVD_15TO14 register field. */
10279 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_15TO14_RESET 0x0
10280 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_6_RSVD_15TO14 field value from a register. */
10281 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_15TO14_GET(value) (((value) & 0x0000c000) >> 14)
10282 /* Produces a ALT_PINMUX_DCTD_IO_CFG_6_RSVD_15TO14 register field value suitable for setting the register. */
10283 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_15TO14_SET(value) (((value) << 14) & 0x0000c000)
10284 
10285 /*
10286  * Field : Weak pull up signal - WK_PU_EN
10287  *
10288  * Configuration bit for weak pull up enable
10289  *
10290  * 0 : weak pull up disable
10291  *
10292  * 1 : weak pull up enable
10293  *
10294  * Field Access Macros:
10295  *
10296  */
10297 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_6_WK_PU_EN register field. */
10298 #define ALT_PINMUX_DCTD_IO_CFG_6_WK_PU_EN_LSB 16
10299 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_6_WK_PU_EN register field. */
10300 #define ALT_PINMUX_DCTD_IO_CFG_6_WK_PU_EN_MSB 16
10301 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_6_WK_PU_EN register field. */
10302 #define ALT_PINMUX_DCTD_IO_CFG_6_WK_PU_EN_WIDTH 1
10303 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_6_WK_PU_EN register field value. */
10304 #define ALT_PINMUX_DCTD_IO_CFG_6_WK_PU_EN_SET_MSK 0x00010000
10305 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_6_WK_PU_EN register field value. */
10306 #define ALT_PINMUX_DCTD_IO_CFG_6_WK_PU_EN_CLR_MSK 0xfffeffff
10307 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_6_WK_PU_EN register field. */
10308 #define ALT_PINMUX_DCTD_IO_CFG_6_WK_PU_EN_RESET 0x1
10309 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_6_WK_PU_EN field value from a register. */
10310 #define ALT_PINMUX_DCTD_IO_CFG_6_WK_PU_EN_GET(value) (((value) & 0x00010000) >> 16)
10311 /* Produces a ALT_PINMUX_DCTD_IO_CFG_6_WK_PU_EN register field value suitable for setting the register. */
10312 #define ALT_PINMUX_DCTD_IO_CFG_6_WK_PU_EN_SET(value) (((value) << 16) & 0x00010000)
10313 
10314 /*
10315  * Field : LVTTL input buffer enable signal - INPUT_BUF_EN
10316  *
10317  * Configuration bits for LVTTL input buffer enable
10318  *
10319  * 00 : disable
10320  *
10321  * 01 : 1.8V TTL
10322  *
10323  * 10 : 2.5V/3.0V TTL
10324  *
10325  * 11 : 1.8V TTL
10326  *
10327  * Field Access Macros:
10328  *
10329  */
10330 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_6_INPUT_BUF_EN register field. */
10331 #define ALT_PINMUX_DCTD_IO_CFG_6_INPUT_BUF_EN_LSB 17
10332 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_6_INPUT_BUF_EN register field. */
10333 #define ALT_PINMUX_DCTD_IO_CFG_6_INPUT_BUF_EN_MSB 18
10334 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_6_INPUT_BUF_EN register field. */
10335 #define ALT_PINMUX_DCTD_IO_CFG_6_INPUT_BUF_EN_WIDTH 2
10336 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_6_INPUT_BUF_EN register field value. */
10337 #define ALT_PINMUX_DCTD_IO_CFG_6_INPUT_BUF_EN_SET_MSK 0x00060000
10338 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_6_INPUT_BUF_EN register field value. */
10339 #define ALT_PINMUX_DCTD_IO_CFG_6_INPUT_BUF_EN_CLR_MSK 0xfff9ffff
10340 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_6_INPUT_BUF_EN register field. */
10341 #define ALT_PINMUX_DCTD_IO_CFG_6_INPUT_BUF_EN_RESET 0x2
10342 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_6_INPUT_BUF_EN field value from a register. */
10343 #define ALT_PINMUX_DCTD_IO_CFG_6_INPUT_BUF_EN_GET(value) (((value) & 0x00060000) >> 17)
10344 /* Produces a ALT_PINMUX_DCTD_IO_CFG_6_INPUT_BUF_EN register field value suitable for setting the register. */
10345 #define ALT_PINMUX_DCTD_IO_CFG_6_INPUT_BUF_EN_SET(value) (((value) << 17) & 0x00060000)
10346 
10347 /*
10348  * Field : Bias trim bits - RTRIM
10349  *
10350  * Configuration bits for bias trim
10351  *
10352  * 000 : disable
10353  *
10354  * 001 : default
10355  *
10356  * 010 : trim low
10357  *
10358  * 100 : trim high
10359  *
10360  * others : invalid/reserved
10361  *
10362  * Field Access Macros:
10363  *
10364  */
10365 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_6_RTRIM register field. */
10366 #define ALT_PINMUX_DCTD_IO_CFG_6_RTRIM_LSB 19
10367 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_6_RTRIM register field. */
10368 #define ALT_PINMUX_DCTD_IO_CFG_6_RTRIM_MSB 21
10369 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_6_RTRIM register field. */
10370 #define ALT_PINMUX_DCTD_IO_CFG_6_RTRIM_WIDTH 3
10371 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_6_RTRIM register field value. */
10372 #define ALT_PINMUX_DCTD_IO_CFG_6_RTRIM_SET_MSK 0x00380000
10373 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_6_RTRIM register field value. */
10374 #define ALT_PINMUX_DCTD_IO_CFG_6_RTRIM_CLR_MSK 0xffc7ffff
10375 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_6_RTRIM register field. */
10376 #define ALT_PINMUX_DCTD_IO_CFG_6_RTRIM_RESET 0x1
10377 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_6_RTRIM field value from a register. */
10378 #define ALT_PINMUX_DCTD_IO_CFG_6_RTRIM_GET(value) (((value) & 0x00380000) >> 19)
10379 /* Produces a ALT_PINMUX_DCTD_IO_CFG_6_RTRIM register field value suitable for setting the register. */
10380 #define ALT_PINMUX_DCTD_IO_CFG_6_RTRIM_SET(value) (((value) << 19) & 0x00380000)
10381 
10382 /*
10383  * Field : Reserved_31to22
10384  *
10385  * Reserved
10386  *
10387  * Field Access Macros:
10388  *
10389  */
10390 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_6_RSVD_31TO22 register field. */
10391 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_31TO22_LSB 22
10392 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_6_RSVD_31TO22 register field. */
10393 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_31TO22_MSB 31
10394 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_6_RSVD_31TO22 register field. */
10395 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_31TO22_WIDTH 10
10396 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_6_RSVD_31TO22 register field value. */
10397 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_31TO22_SET_MSK 0xffc00000
10398 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_6_RSVD_31TO22 register field value. */
10399 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_31TO22_CLR_MSK 0x003fffff
10400 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_6_RSVD_31TO22 register field. */
10401 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_31TO22_RESET 0x0
10402 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_6_RSVD_31TO22 field value from a register. */
10403 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_31TO22_GET(value) (((value) & 0xffc00000) >> 22)
10404 /* Produces a ALT_PINMUX_DCTD_IO_CFG_6_RSVD_31TO22 register field value suitable for setting the register. */
10405 #define ALT_PINMUX_DCTD_IO_CFG_6_RSVD_31TO22_SET(value) (((value) << 22) & 0xffc00000)
10406 
10407 #ifndef __ASSEMBLY__
10408 /*
10409  * WARNING: The C register and register group struct declarations are provided for
10410  * convenience and illustrative purposes. They should, however, be used with
10411  * caution as the C language standard provides no guarantees about the alignment or
10412  * atomicity of device memory accesses. The recommended practice for writing
10413  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10414  * alt_write_word() functions.
10415  *
10416  * The struct declaration for register ALT_PINMUX_DCTD_IO_CFG_6.
10417  */
10418 struct ALT_PINMUX_DCTD_IO_CFG_6_s
10419 {
10420  uint32_t PD_DRV_STRG : 5; /* Pull down drive strength */
10421  uint32_t PD_SLW_RT : 1; /* NMOS slew rate */
10422  const uint32_t Reserved_7to6 : 2; /* ALT_PINMUX_DCTD_IO_CFG_6_RSVD_7TO6 */
10423  uint32_t PU_DRV_STRG : 5; /* Pull up drive strength */
10424  uint32_t PU_SLW_RT : 1; /* PMOS slew rate */
10425  const uint32_t Reserved_15to14 : 2; /* ALT_PINMUX_DCTD_IO_CFG_6_RSVD_15TO14 */
10426  uint32_t WK_PU_EN : 1; /* Weak pull up signal */
10427  uint32_t INPUT_BUF_EN : 2; /* LVTTL input buffer enable signal */
10428  uint32_t RTRIM : 3; /* Bias trim bits */
10429  const uint32_t Reserved_31to22 : 10; /* ALT_PINMUX_DCTD_IO_CFG_6_RSVD_31TO22 */
10430 };
10431 
10432 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_CFG_6. */
10433 typedef volatile struct ALT_PINMUX_DCTD_IO_CFG_6_s ALT_PINMUX_DCTD_IO_CFG_6_t;
10434 #endif /* __ASSEMBLY__ */
10435 
10436 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_6 register. */
10437 #define ALT_PINMUX_DCTD_IO_CFG_6_RESET 0x000d0008
10438 /* The byte offset of the ALT_PINMUX_DCTD_IO_CFG_6 register from the beginning of the component. */
10439 #define ALT_PINMUX_DCTD_IO_CFG_6_OFST 0x118
10440 
10441 /*
10442  * Register : Dedicated IO 7 Configuration Register - configuration_dedicated_io_7
10443  *
10444  * This register is used to control the electrical behavior and direction of
10445  * Dedicated IO 7
10446  *
10447  * Only reset by a cold reset (ignores warm reset).
10448  *
10449  * Register Layout
10450  *
10451  * Bits | Access | Reset | Description
10452  * :--------|:-------|:------|:-------------------------------------
10453  * [4:0] | RW | 0x8 | Pull down drive strength
10454  * [5] | RW | 0x0 | NMOS slew rate
10455  * [7:6] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_7_RSVD_7TO6
10456  * [12:8] | RW | 0x0 | Pull up drive strength
10457  * [13] | RW | 0x0 | PMOS slew rate
10458  * [15:14] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_7_RSVD_15TO14
10459  * [16] | RW | 0x1 | Weak pull up signal
10460  * [18:17] | RW | 0x2 | LVTTL input buffer enable signal
10461  * [21:19] | RW | 0x1 | Bias trim bits
10462  * [31:22] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_7_RSVD_31TO22
10463  *
10464  */
10465 /*
10466  * Field : Pull down drive strength - PD_DRV_STRG
10467  *
10468  * Configuration bits for NMOS pull down drive strength.
10469  *
10470  * Pending Characterization
10471  *
10472  * Field Access Macros:
10473  *
10474  */
10475 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_7_PD_DRV_STRG register field. */
10476 #define ALT_PINMUX_DCTD_IO_CFG_7_PD_DRV_STRG_LSB 0
10477 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_7_PD_DRV_STRG register field. */
10478 #define ALT_PINMUX_DCTD_IO_CFG_7_PD_DRV_STRG_MSB 4
10479 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_7_PD_DRV_STRG register field. */
10480 #define ALT_PINMUX_DCTD_IO_CFG_7_PD_DRV_STRG_WIDTH 5
10481 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_7_PD_DRV_STRG register field value. */
10482 #define ALT_PINMUX_DCTD_IO_CFG_7_PD_DRV_STRG_SET_MSK 0x0000001f
10483 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_7_PD_DRV_STRG register field value. */
10484 #define ALT_PINMUX_DCTD_IO_CFG_7_PD_DRV_STRG_CLR_MSK 0xffffffe0
10485 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_7_PD_DRV_STRG register field. */
10486 #define ALT_PINMUX_DCTD_IO_CFG_7_PD_DRV_STRG_RESET 0x8
10487 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_7_PD_DRV_STRG field value from a register. */
10488 #define ALT_PINMUX_DCTD_IO_CFG_7_PD_DRV_STRG_GET(value) (((value) & 0x0000001f) >> 0)
10489 /* Produces a ALT_PINMUX_DCTD_IO_CFG_7_PD_DRV_STRG register field value suitable for setting the register. */
10490 #define ALT_PINMUX_DCTD_IO_CFG_7_PD_DRV_STRG_SET(value) (((value) << 0) & 0x0000001f)
10491 
10492 /*
10493  * Field : NMOS slew rate - PD_SLW_RT
10494  *
10495  * Configuration bit for output pull down slew rate control
10496  *
10497  * 0 : slow N slew
10498  *
10499  * 1 : fast N slew
10500  *
10501  * Field Access Macros:
10502  *
10503  */
10504 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_7_PD_SLW_RT register field. */
10505 #define ALT_PINMUX_DCTD_IO_CFG_7_PD_SLW_RT_LSB 5
10506 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_7_PD_SLW_RT register field. */
10507 #define ALT_PINMUX_DCTD_IO_CFG_7_PD_SLW_RT_MSB 5
10508 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_7_PD_SLW_RT register field. */
10509 #define ALT_PINMUX_DCTD_IO_CFG_7_PD_SLW_RT_WIDTH 1
10510 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_7_PD_SLW_RT register field value. */
10511 #define ALT_PINMUX_DCTD_IO_CFG_7_PD_SLW_RT_SET_MSK 0x00000020
10512 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_7_PD_SLW_RT register field value. */
10513 #define ALT_PINMUX_DCTD_IO_CFG_7_PD_SLW_RT_CLR_MSK 0xffffffdf
10514 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_7_PD_SLW_RT register field. */
10515 #define ALT_PINMUX_DCTD_IO_CFG_7_PD_SLW_RT_RESET 0x0
10516 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_7_PD_SLW_RT field value from a register. */
10517 #define ALT_PINMUX_DCTD_IO_CFG_7_PD_SLW_RT_GET(value) (((value) & 0x00000020) >> 5)
10518 /* Produces a ALT_PINMUX_DCTD_IO_CFG_7_PD_SLW_RT register field value suitable for setting the register. */
10519 #define ALT_PINMUX_DCTD_IO_CFG_7_PD_SLW_RT_SET(value) (((value) << 5) & 0x00000020)
10520 
10521 /*
10522  * Field : Reserved_7to6
10523  *
10524  * Reserved
10525  *
10526  * Field Access Macros:
10527  *
10528  */
10529 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_7_RSVD_7TO6 register field. */
10530 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_7TO6_LSB 6
10531 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_7_RSVD_7TO6 register field. */
10532 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_7TO6_MSB 7
10533 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_7_RSVD_7TO6 register field. */
10534 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_7TO6_WIDTH 2
10535 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_7_RSVD_7TO6 register field value. */
10536 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_7TO6_SET_MSK 0x000000c0
10537 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_7_RSVD_7TO6 register field value. */
10538 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_7TO6_CLR_MSK 0xffffff3f
10539 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_7_RSVD_7TO6 register field. */
10540 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_7TO6_RESET 0x0
10541 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_7_RSVD_7TO6 field value from a register. */
10542 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_7TO6_GET(value) (((value) & 0x000000c0) >> 6)
10543 /* Produces a ALT_PINMUX_DCTD_IO_CFG_7_RSVD_7TO6 register field value suitable for setting the register. */
10544 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_7TO6_SET(value) (((value) << 6) & 0x000000c0)
10545 
10546 /*
10547  * Field : Pull up drive strength - PU_DRV_STRG
10548  *
10549  * Configuration bits for PMOS pull up drive strength
10550  *
10551  * Pending Characterization
10552  *
10553  * Field Access Macros:
10554  *
10555  */
10556 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_7_PU_DRV_STRG register field. */
10557 #define ALT_PINMUX_DCTD_IO_CFG_7_PU_DRV_STRG_LSB 8
10558 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_7_PU_DRV_STRG register field. */
10559 #define ALT_PINMUX_DCTD_IO_CFG_7_PU_DRV_STRG_MSB 12
10560 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_7_PU_DRV_STRG register field. */
10561 #define ALT_PINMUX_DCTD_IO_CFG_7_PU_DRV_STRG_WIDTH 5
10562 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_7_PU_DRV_STRG register field value. */
10563 #define ALT_PINMUX_DCTD_IO_CFG_7_PU_DRV_STRG_SET_MSK 0x00001f00
10564 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_7_PU_DRV_STRG register field value. */
10565 #define ALT_PINMUX_DCTD_IO_CFG_7_PU_DRV_STRG_CLR_MSK 0xffffe0ff
10566 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_7_PU_DRV_STRG register field. */
10567 #define ALT_PINMUX_DCTD_IO_CFG_7_PU_DRV_STRG_RESET 0x0
10568 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_7_PU_DRV_STRG field value from a register. */
10569 #define ALT_PINMUX_DCTD_IO_CFG_7_PU_DRV_STRG_GET(value) (((value) & 0x00001f00) >> 8)
10570 /* Produces a ALT_PINMUX_DCTD_IO_CFG_7_PU_DRV_STRG register field value suitable for setting the register. */
10571 #define ALT_PINMUX_DCTD_IO_CFG_7_PU_DRV_STRG_SET(value) (((value) << 8) & 0x00001f00)
10572 
10573 /*
10574  * Field : PMOS slew rate - PU_SLW_RT
10575  *
10576  * Configuration bit for output pull up slew rate control
10577  *
10578  * 0 : slow P slew
10579  *
10580  * 1 : fast P slew
10581  *
10582  * Field Access Macros:
10583  *
10584  */
10585 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_7_PU_SLW_RT register field. */
10586 #define ALT_PINMUX_DCTD_IO_CFG_7_PU_SLW_RT_LSB 13
10587 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_7_PU_SLW_RT register field. */
10588 #define ALT_PINMUX_DCTD_IO_CFG_7_PU_SLW_RT_MSB 13
10589 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_7_PU_SLW_RT register field. */
10590 #define ALT_PINMUX_DCTD_IO_CFG_7_PU_SLW_RT_WIDTH 1
10591 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_7_PU_SLW_RT register field value. */
10592 #define ALT_PINMUX_DCTD_IO_CFG_7_PU_SLW_RT_SET_MSK 0x00002000
10593 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_7_PU_SLW_RT register field value. */
10594 #define ALT_PINMUX_DCTD_IO_CFG_7_PU_SLW_RT_CLR_MSK 0xffffdfff
10595 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_7_PU_SLW_RT register field. */
10596 #define ALT_PINMUX_DCTD_IO_CFG_7_PU_SLW_RT_RESET 0x0
10597 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_7_PU_SLW_RT field value from a register. */
10598 #define ALT_PINMUX_DCTD_IO_CFG_7_PU_SLW_RT_GET(value) (((value) & 0x00002000) >> 13)
10599 /* Produces a ALT_PINMUX_DCTD_IO_CFG_7_PU_SLW_RT register field value suitable for setting the register. */
10600 #define ALT_PINMUX_DCTD_IO_CFG_7_PU_SLW_RT_SET(value) (((value) << 13) & 0x00002000)
10601 
10602 /*
10603  * Field : Reserved_15to14
10604  *
10605  * Reserved
10606  *
10607  * Field Access Macros:
10608  *
10609  */
10610 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_7_RSVD_15TO14 register field. */
10611 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_15TO14_LSB 14
10612 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_7_RSVD_15TO14 register field. */
10613 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_15TO14_MSB 15
10614 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_7_RSVD_15TO14 register field. */
10615 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_15TO14_WIDTH 2
10616 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_7_RSVD_15TO14 register field value. */
10617 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_15TO14_SET_MSK 0x0000c000
10618 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_7_RSVD_15TO14 register field value. */
10619 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_15TO14_CLR_MSK 0xffff3fff
10620 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_7_RSVD_15TO14 register field. */
10621 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_15TO14_RESET 0x0
10622 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_7_RSVD_15TO14 field value from a register. */
10623 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_15TO14_GET(value) (((value) & 0x0000c000) >> 14)
10624 /* Produces a ALT_PINMUX_DCTD_IO_CFG_7_RSVD_15TO14 register field value suitable for setting the register. */
10625 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_15TO14_SET(value) (((value) << 14) & 0x0000c000)
10626 
10627 /*
10628  * Field : Weak pull up signal - WK_PU_EN
10629  *
10630  * Configuration bit for weak pull up enable
10631  *
10632  * 0 : weak pull up disable
10633  *
10634  * 1 : weak pull up enable
10635  *
10636  * Field Access Macros:
10637  *
10638  */
10639 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_7_WK_PU_EN register field. */
10640 #define ALT_PINMUX_DCTD_IO_CFG_7_WK_PU_EN_LSB 16
10641 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_7_WK_PU_EN register field. */
10642 #define ALT_PINMUX_DCTD_IO_CFG_7_WK_PU_EN_MSB 16
10643 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_7_WK_PU_EN register field. */
10644 #define ALT_PINMUX_DCTD_IO_CFG_7_WK_PU_EN_WIDTH 1
10645 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_7_WK_PU_EN register field value. */
10646 #define ALT_PINMUX_DCTD_IO_CFG_7_WK_PU_EN_SET_MSK 0x00010000
10647 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_7_WK_PU_EN register field value. */
10648 #define ALT_PINMUX_DCTD_IO_CFG_7_WK_PU_EN_CLR_MSK 0xfffeffff
10649 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_7_WK_PU_EN register field. */
10650 #define ALT_PINMUX_DCTD_IO_CFG_7_WK_PU_EN_RESET 0x1
10651 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_7_WK_PU_EN field value from a register. */
10652 #define ALT_PINMUX_DCTD_IO_CFG_7_WK_PU_EN_GET(value) (((value) & 0x00010000) >> 16)
10653 /* Produces a ALT_PINMUX_DCTD_IO_CFG_7_WK_PU_EN register field value suitable for setting the register. */
10654 #define ALT_PINMUX_DCTD_IO_CFG_7_WK_PU_EN_SET(value) (((value) << 16) & 0x00010000)
10655 
10656 /*
10657  * Field : LVTTL input buffer enable signal - INPUT_BUF_EN
10658  *
10659  * Configuration bits for LVTTL input buffer enable
10660  *
10661  * 00 : disable
10662  *
10663  * 01 : 1.8V TTL
10664  *
10665  * 10 : 2.5V/3.0V TTL
10666  *
10667  * 11 : 1.8V TTL
10668  *
10669  * Field Access Macros:
10670  *
10671  */
10672 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_7_INPUT_BUF_EN register field. */
10673 #define ALT_PINMUX_DCTD_IO_CFG_7_INPUT_BUF_EN_LSB 17
10674 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_7_INPUT_BUF_EN register field. */
10675 #define ALT_PINMUX_DCTD_IO_CFG_7_INPUT_BUF_EN_MSB 18
10676 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_7_INPUT_BUF_EN register field. */
10677 #define ALT_PINMUX_DCTD_IO_CFG_7_INPUT_BUF_EN_WIDTH 2
10678 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_7_INPUT_BUF_EN register field value. */
10679 #define ALT_PINMUX_DCTD_IO_CFG_7_INPUT_BUF_EN_SET_MSK 0x00060000
10680 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_7_INPUT_BUF_EN register field value. */
10681 #define ALT_PINMUX_DCTD_IO_CFG_7_INPUT_BUF_EN_CLR_MSK 0xfff9ffff
10682 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_7_INPUT_BUF_EN register field. */
10683 #define ALT_PINMUX_DCTD_IO_CFG_7_INPUT_BUF_EN_RESET 0x2
10684 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_7_INPUT_BUF_EN field value from a register. */
10685 #define ALT_PINMUX_DCTD_IO_CFG_7_INPUT_BUF_EN_GET(value) (((value) & 0x00060000) >> 17)
10686 /* Produces a ALT_PINMUX_DCTD_IO_CFG_7_INPUT_BUF_EN register field value suitable for setting the register. */
10687 #define ALT_PINMUX_DCTD_IO_CFG_7_INPUT_BUF_EN_SET(value) (((value) << 17) & 0x00060000)
10688 
10689 /*
10690  * Field : Bias trim bits - RTRIM
10691  *
10692  * Configuration bits for bias trim
10693  *
10694  * 000 : disable
10695  *
10696  * 001 : default
10697  *
10698  * 010 : trim low
10699  *
10700  * 100 : trim high
10701  *
10702  * others : invalid/reserved
10703  *
10704  * Field Access Macros:
10705  *
10706  */
10707 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_7_RTRIM register field. */
10708 #define ALT_PINMUX_DCTD_IO_CFG_7_RTRIM_LSB 19
10709 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_7_RTRIM register field. */
10710 #define ALT_PINMUX_DCTD_IO_CFG_7_RTRIM_MSB 21
10711 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_7_RTRIM register field. */
10712 #define ALT_PINMUX_DCTD_IO_CFG_7_RTRIM_WIDTH 3
10713 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_7_RTRIM register field value. */
10714 #define ALT_PINMUX_DCTD_IO_CFG_7_RTRIM_SET_MSK 0x00380000
10715 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_7_RTRIM register field value. */
10716 #define ALT_PINMUX_DCTD_IO_CFG_7_RTRIM_CLR_MSK 0xffc7ffff
10717 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_7_RTRIM register field. */
10718 #define ALT_PINMUX_DCTD_IO_CFG_7_RTRIM_RESET 0x1
10719 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_7_RTRIM field value from a register. */
10720 #define ALT_PINMUX_DCTD_IO_CFG_7_RTRIM_GET(value) (((value) & 0x00380000) >> 19)
10721 /* Produces a ALT_PINMUX_DCTD_IO_CFG_7_RTRIM register field value suitable for setting the register. */
10722 #define ALT_PINMUX_DCTD_IO_CFG_7_RTRIM_SET(value) (((value) << 19) & 0x00380000)
10723 
10724 /*
10725  * Field : Reserved_31to22
10726  *
10727  * Reserved
10728  *
10729  * Field Access Macros:
10730  *
10731  */
10732 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_7_RSVD_31TO22 register field. */
10733 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_31TO22_LSB 22
10734 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_7_RSVD_31TO22 register field. */
10735 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_31TO22_MSB 31
10736 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_7_RSVD_31TO22 register field. */
10737 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_31TO22_WIDTH 10
10738 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_7_RSVD_31TO22 register field value. */
10739 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_31TO22_SET_MSK 0xffc00000
10740 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_7_RSVD_31TO22 register field value. */
10741 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_31TO22_CLR_MSK 0x003fffff
10742 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_7_RSVD_31TO22 register field. */
10743 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_31TO22_RESET 0x0
10744 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_7_RSVD_31TO22 field value from a register. */
10745 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_31TO22_GET(value) (((value) & 0xffc00000) >> 22)
10746 /* Produces a ALT_PINMUX_DCTD_IO_CFG_7_RSVD_31TO22 register field value suitable for setting the register. */
10747 #define ALT_PINMUX_DCTD_IO_CFG_7_RSVD_31TO22_SET(value) (((value) << 22) & 0xffc00000)
10748 
10749 #ifndef __ASSEMBLY__
10750 /*
10751  * WARNING: The C register and register group struct declarations are provided for
10752  * convenience and illustrative purposes. They should, however, be used with
10753  * caution as the C language standard provides no guarantees about the alignment or
10754  * atomicity of device memory accesses. The recommended practice for writing
10755  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10756  * alt_write_word() functions.
10757  *
10758  * The struct declaration for register ALT_PINMUX_DCTD_IO_CFG_7.
10759  */
10760 struct ALT_PINMUX_DCTD_IO_CFG_7_s
10761 {
10762  uint32_t PD_DRV_STRG : 5; /* Pull down drive strength */
10763  uint32_t PD_SLW_RT : 1; /* NMOS slew rate */
10764  const uint32_t Reserved_7to6 : 2; /* ALT_PINMUX_DCTD_IO_CFG_7_RSVD_7TO6 */
10765  uint32_t PU_DRV_STRG : 5; /* Pull up drive strength */
10766  uint32_t PU_SLW_RT : 1; /* PMOS slew rate */
10767  const uint32_t Reserved_15to14 : 2; /* ALT_PINMUX_DCTD_IO_CFG_7_RSVD_15TO14 */
10768  uint32_t WK_PU_EN : 1; /* Weak pull up signal */
10769  uint32_t INPUT_BUF_EN : 2; /* LVTTL input buffer enable signal */
10770  uint32_t RTRIM : 3; /* Bias trim bits */
10771  const uint32_t Reserved_31to22 : 10; /* ALT_PINMUX_DCTD_IO_CFG_7_RSVD_31TO22 */
10772 };
10773 
10774 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_CFG_7. */
10775 typedef volatile struct ALT_PINMUX_DCTD_IO_CFG_7_s ALT_PINMUX_DCTD_IO_CFG_7_t;
10776 #endif /* __ASSEMBLY__ */
10777 
10778 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_7 register. */
10779 #define ALT_PINMUX_DCTD_IO_CFG_7_RESET 0x000d0008
10780 /* The byte offset of the ALT_PINMUX_DCTD_IO_CFG_7 register from the beginning of the component. */
10781 #define ALT_PINMUX_DCTD_IO_CFG_7_OFST 0x11c
10782 
10783 /*
10784  * Register : Dedicated IO 8 Configuration Register - configuration_dedicated_io_8
10785  *
10786  * This register is used to control the electrical behavior and direction of
10787  * Dedicated IO 8
10788  *
10789  * Only reset by a cold reset (ignores warm reset).
10790  *
10791  * Register Layout
10792  *
10793  * Bits | Access | Reset | Description
10794  * :--------|:-------|:------|:-------------------------------------
10795  * [4:0] | RW | 0x8 | Pull down drive strength
10796  * [5] | RW | 0x0 | NMOS slew rate
10797  * [7:6] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_8_RSVD_7TO6
10798  * [12:8] | RW | 0x0 | Pull up drive strength
10799  * [13] | RW | 0x0 | PMOS slew rate
10800  * [15:14] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_8_RSVD_15TO14
10801  * [16] | RW | 0x1 | Weak pull up signal
10802  * [18:17] | RW | 0x2 | LVTTL input buffer enable signal
10803  * [21:19] | RW | 0x1 | Bias trim bits
10804  * [31:22] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_8_RSVD_31TO22
10805  *
10806  */
10807 /*
10808  * Field : Pull down drive strength - PD_DRV_STRG
10809  *
10810  * Configuration bits for NMOS pull down drive strength.
10811  *
10812  * Pending Characterization
10813  *
10814  * Field Access Macros:
10815  *
10816  */
10817 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_8_PD_DRV_STRG register field. */
10818 #define ALT_PINMUX_DCTD_IO_CFG_8_PD_DRV_STRG_LSB 0
10819 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_8_PD_DRV_STRG register field. */
10820 #define ALT_PINMUX_DCTD_IO_CFG_8_PD_DRV_STRG_MSB 4
10821 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_8_PD_DRV_STRG register field. */
10822 #define ALT_PINMUX_DCTD_IO_CFG_8_PD_DRV_STRG_WIDTH 5
10823 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_8_PD_DRV_STRG register field value. */
10824 #define ALT_PINMUX_DCTD_IO_CFG_8_PD_DRV_STRG_SET_MSK 0x0000001f
10825 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_8_PD_DRV_STRG register field value. */
10826 #define ALT_PINMUX_DCTD_IO_CFG_8_PD_DRV_STRG_CLR_MSK 0xffffffe0
10827 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_8_PD_DRV_STRG register field. */
10828 #define ALT_PINMUX_DCTD_IO_CFG_8_PD_DRV_STRG_RESET 0x8
10829 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_8_PD_DRV_STRG field value from a register. */
10830 #define ALT_PINMUX_DCTD_IO_CFG_8_PD_DRV_STRG_GET(value) (((value) & 0x0000001f) >> 0)
10831 /* Produces a ALT_PINMUX_DCTD_IO_CFG_8_PD_DRV_STRG register field value suitable for setting the register. */
10832 #define ALT_PINMUX_DCTD_IO_CFG_8_PD_DRV_STRG_SET(value) (((value) << 0) & 0x0000001f)
10833 
10834 /*
10835  * Field : NMOS slew rate - PD_SLW_RT
10836  *
10837  * Configuration bit for output pull down slew rate control
10838  *
10839  * 0 : slow N slew
10840  *
10841  * 1 : fast N slew
10842  *
10843  * Field Access Macros:
10844  *
10845  */
10846 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_8_PD_SLW_RT register field. */
10847 #define ALT_PINMUX_DCTD_IO_CFG_8_PD_SLW_RT_LSB 5
10848 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_8_PD_SLW_RT register field. */
10849 #define ALT_PINMUX_DCTD_IO_CFG_8_PD_SLW_RT_MSB 5
10850 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_8_PD_SLW_RT register field. */
10851 #define ALT_PINMUX_DCTD_IO_CFG_8_PD_SLW_RT_WIDTH 1
10852 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_8_PD_SLW_RT register field value. */
10853 #define ALT_PINMUX_DCTD_IO_CFG_8_PD_SLW_RT_SET_MSK 0x00000020
10854 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_8_PD_SLW_RT register field value. */
10855 #define ALT_PINMUX_DCTD_IO_CFG_8_PD_SLW_RT_CLR_MSK 0xffffffdf
10856 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_8_PD_SLW_RT register field. */
10857 #define ALT_PINMUX_DCTD_IO_CFG_8_PD_SLW_RT_RESET 0x0
10858 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_8_PD_SLW_RT field value from a register. */
10859 #define ALT_PINMUX_DCTD_IO_CFG_8_PD_SLW_RT_GET(value) (((value) & 0x00000020) >> 5)
10860 /* Produces a ALT_PINMUX_DCTD_IO_CFG_8_PD_SLW_RT register field value suitable for setting the register. */
10861 #define ALT_PINMUX_DCTD_IO_CFG_8_PD_SLW_RT_SET(value) (((value) << 5) & 0x00000020)
10862 
10863 /*
10864  * Field : Reserved_7to6
10865  *
10866  * Reserved
10867  *
10868  * Field Access Macros:
10869  *
10870  */
10871 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_8_RSVD_7TO6 register field. */
10872 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_7TO6_LSB 6
10873 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_8_RSVD_7TO6 register field. */
10874 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_7TO6_MSB 7
10875 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_8_RSVD_7TO6 register field. */
10876 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_7TO6_WIDTH 2
10877 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_8_RSVD_7TO6 register field value. */
10878 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_7TO6_SET_MSK 0x000000c0
10879 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_8_RSVD_7TO6 register field value. */
10880 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_7TO6_CLR_MSK 0xffffff3f
10881 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_8_RSVD_7TO6 register field. */
10882 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_7TO6_RESET 0x0
10883 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_8_RSVD_7TO6 field value from a register. */
10884 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_7TO6_GET(value) (((value) & 0x000000c0) >> 6)
10885 /* Produces a ALT_PINMUX_DCTD_IO_CFG_8_RSVD_7TO6 register field value suitable for setting the register. */
10886 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_7TO6_SET(value) (((value) << 6) & 0x000000c0)
10887 
10888 /*
10889  * Field : Pull up drive strength - PU_DRV_STRG
10890  *
10891  * Configuration bits for PMOS pull up drive strength
10892  *
10893  * Pending Characterization
10894  *
10895  * Field Access Macros:
10896  *
10897  */
10898 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_8_PU_DRV_STRG register field. */
10899 #define ALT_PINMUX_DCTD_IO_CFG_8_PU_DRV_STRG_LSB 8
10900 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_8_PU_DRV_STRG register field. */
10901 #define ALT_PINMUX_DCTD_IO_CFG_8_PU_DRV_STRG_MSB 12
10902 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_8_PU_DRV_STRG register field. */
10903 #define ALT_PINMUX_DCTD_IO_CFG_8_PU_DRV_STRG_WIDTH 5
10904 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_8_PU_DRV_STRG register field value. */
10905 #define ALT_PINMUX_DCTD_IO_CFG_8_PU_DRV_STRG_SET_MSK 0x00001f00
10906 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_8_PU_DRV_STRG register field value. */
10907 #define ALT_PINMUX_DCTD_IO_CFG_8_PU_DRV_STRG_CLR_MSK 0xffffe0ff
10908 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_8_PU_DRV_STRG register field. */
10909 #define ALT_PINMUX_DCTD_IO_CFG_8_PU_DRV_STRG_RESET 0x0
10910 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_8_PU_DRV_STRG field value from a register. */
10911 #define ALT_PINMUX_DCTD_IO_CFG_8_PU_DRV_STRG_GET(value) (((value) & 0x00001f00) >> 8)
10912 /* Produces a ALT_PINMUX_DCTD_IO_CFG_8_PU_DRV_STRG register field value suitable for setting the register. */
10913 #define ALT_PINMUX_DCTD_IO_CFG_8_PU_DRV_STRG_SET(value) (((value) << 8) & 0x00001f00)
10914 
10915 /*
10916  * Field : PMOS slew rate - PU_SLW_RT
10917  *
10918  * Configuration bit for output pull up slew rate control
10919  *
10920  * 0 : slow P slew
10921  *
10922  * 1 : fast P slew
10923  *
10924  * Field Access Macros:
10925  *
10926  */
10927 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_8_PU_SLW_RT register field. */
10928 #define ALT_PINMUX_DCTD_IO_CFG_8_PU_SLW_RT_LSB 13
10929 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_8_PU_SLW_RT register field. */
10930 #define ALT_PINMUX_DCTD_IO_CFG_8_PU_SLW_RT_MSB 13
10931 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_8_PU_SLW_RT register field. */
10932 #define ALT_PINMUX_DCTD_IO_CFG_8_PU_SLW_RT_WIDTH 1
10933 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_8_PU_SLW_RT register field value. */
10934 #define ALT_PINMUX_DCTD_IO_CFG_8_PU_SLW_RT_SET_MSK 0x00002000
10935 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_8_PU_SLW_RT register field value. */
10936 #define ALT_PINMUX_DCTD_IO_CFG_8_PU_SLW_RT_CLR_MSK 0xffffdfff
10937 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_8_PU_SLW_RT register field. */
10938 #define ALT_PINMUX_DCTD_IO_CFG_8_PU_SLW_RT_RESET 0x0
10939 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_8_PU_SLW_RT field value from a register. */
10940 #define ALT_PINMUX_DCTD_IO_CFG_8_PU_SLW_RT_GET(value) (((value) & 0x00002000) >> 13)
10941 /* Produces a ALT_PINMUX_DCTD_IO_CFG_8_PU_SLW_RT register field value suitable for setting the register. */
10942 #define ALT_PINMUX_DCTD_IO_CFG_8_PU_SLW_RT_SET(value) (((value) << 13) & 0x00002000)
10943 
10944 /*
10945  * Field : Reserved_15to14
10946  *
10947  * Reserved
10948  *
10949  * Field Access Macros:
10950  *
10951  */
10952 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_8_RSVD_15TO14 register field. */
10953 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_15TO14_LSB 14
10954 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_8_RSVD_15TO14 register field. */
10955 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_15TO14_MSB 15
10956 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_8_RSVD_15TO14 register field. */
10957 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_15TO14_WIDTH 2
10958 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_8_RSVD_15TO14 register field value. */
10959 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_15TO14_SET_MSK 0x0000c000
10960 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_8_RSVD_15TO14 register field value. */
10961 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_15TO14_CLR_MSK 0xffff3fff
10962 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_8_RSVD_15TO14 register field. */
10963 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_15TO14_RESET 0x0
10964 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_8_RSVD_15TO14 field value from a register. */
10965 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_15TO14_GET(value) (((value) & 0x0000c000) >> 14)
10966 /* Produces a ALT_PINMUX_DCTD_IO_CFG_8_RSVD_15TO14 register field value suitable for setting the register. */
10967 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_15TO14_SET(value) (((value) << 14) & 0x0000c000)
10968 
10969 /*
10970  * Field : Weak pull up signal - WK_PU_EN
10971  *
10972  * Configuration bit for weak pull up enable
10973  *
10974  * 0 : weak pull up disable
10975  *
10976  * 1 : weak pull up enable
10977  *
10978  * Field Access Macros:
10979  *
10980  */
10981 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_8_WK_PU_EN register field. */
10982 #define ALT_PINMUX_DCTD_IO_CFG_8_WK_PU_EN_LSB 16
10983 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_8_WK_PU_EN register field. */
10984 #define ALT_PINMUX_DCTD_IO_CFG_8_WK_PU_EN_MSB 16
10985 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_8_WK_PU_EN register field. */
10986 #define ALT_PINMUX_DCTD_IO_CFG_8_WK_PU_EN_WIDTH 1
10987 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_8_WK_PU_EN register field value. */
10988 #define ALT_PINMUX_DCTD_IO_CFG_8_WK_PU_EN_SET_MSK 0x00010000
10989 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_8_WK_PU_EN register field value. */
10990 #define ALT_PINMUX_DCTD_IO_CFG_8_WK_PU_EN_CLR_MSK 0xfffeffff
10991 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_8_WK_PU_EN register field. */
10992 #define ALT_PINMUX_DCTD_IO_CFG_8_WK_PU_EN_RESET 0x1
10993 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_8_WK_PU_EN field value from a register. */
10994 #define ALT_PINMUX_DCTD_IO_CFG_8_WK_PU_EN_GET(value) (((value) & 0x00010000) >> 16)
10995 /* Produces a ALT_PINMUX_DCTD_IO_CFG_8_WK_PU_EN register field value suitable for setting the register. */
10996 #define ALT_PINMUX_DCTD_IO_CFG_8_WK_PU_EN_SET(value) (((value) << 16) & 0x00010000)
10997 
10998 /*
10999  * Field : LVTTL input buffer enable signal - INPUT_BUF_EN
11000  *
11001  * Configuration bits for LVTTL input buffer enable
11002  *
11003  * 00 : disable
11004  *
11005  * 01 : 1.8V TTL
11006  *
11007  * 10 : 2.5V/3.0V TTL
11008  *
11009  * 11 : 1.8V TTL
11010  *
11011  * Field Access Macros:
11012  *
11013  */
11014 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_8_INPUT_BUF_EN register field. */
11015 #define ALT_PINMUX_DCTD_IO_CFG_8_INPUT_BUF_EN_LSB 17
11016 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_8_INPUT_BUF_EN register field. */
11017 #define ALT_PINMUX_DCTD_IO_CFG_8_INPUT_BUF_EN_MSB 18
11018 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_8_INPUT_BUF_EN register field. */
11019 #define ALT_PINMUX_DCTD_IO_CFG_8_INPUT_BUF_EN_WIDTH 2
11020 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_8_INPUT_BUF_EN register field value. */
11021 #define ALT_PINMUX_DCTD_IO_CFG_8_INPUT_BUF_EN_SET_MSK 0x00060000
11022 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_8_INPUT_BUF_EN register field value. */
11023 #define ALT_PINMUX_DCTD_IO_CFG_8_INPUT_BUF_EN_CLR_MSK 0xfff9ffff
11024 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_8_INPUT_BUF_EN register field. */
11025 #define ALT_PINMUX_DCTD_IO_CFG_8_INPUT_BUF_EN_RESET 0x2
11026 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_8_INPUT_BUF_EN field value from a register. */
11027 #define ALT_PINMUX_DCTD_IO_CFG_8_INPUT_BUF_EN_GET(value) (((value) & 0x00060000) >> 17)
11028 /* Produces a ALT_PINMUX_DCTD_IO_CFG_8_INPUT_BUF_EN register field value suitable for setting the register. */
11029 #define ALT_PINMUX_DCTD_IO_CFG_8_INPUT_BUF_EN_SET(value) (((value) << 17) & 0x00060000)
11030 
11031 /*
11032  * Field : Bias trim bits - RTRIM
11033  *
11034  * Configuration bits for bias trim
11035  *
11036  * 000 : disable
11037  *
11038  * 001 : default
11039  *
11040  * 010 : trim low
11041  *
11042  * 100 : trim high
11043  *
11044  * others : invalid/reserved
11045  *
11046  * Field Access Macros:
11047  *
11048  */
11049 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_8_RTRIM register field. */
11050 #define ALT_PINMUX_DCTD_IO_CFG_8_RTRIM_LSB 19
11051 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_8_RTRIM register field. */
11052 #define ALT_PINMUX_DCTD_IO_CFG_8_RTRIM_MSB 21
11053 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_8_RTRIM register field. */
11054 #define ALT_PINMUX_DCTD_IO_CFG_8_RTRIM_WIDTH 3
11055 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_8_RTRIM register field value. */
11056 #define ALT_PINMUX_DCTD_IO_CFG_8_RTRIM_SET_MSK 0x00380000
11057 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_8_RTRIM register field value. */
11058 #define ALT_PINMUX_DCTD_IO_CFG_8_RTRIM_CLR_MSK 0xffc7ffff
11059 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_8_RTRIM register field. */
11060 #define ALT_PINMUX_DCTD_IO_CFG_8_RTRIM_RESET 0x1
11061 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_8_RTRIM field value from a register. */
11062 #define ALT_PINMUX_DCTD_IO_CFG_8_RTRIM_GET(value) (((value) & 0x00380000) >> 19)
11063 /* Produces a ALT_PINMUX_DCTD_IO_CFG_8_RTRIM register field value suitable for setting the register. */
11064 #define ALT_PINMUX_DCTD_IO_CFG_8_RTRIM_SET(value) (((value) << 19) & 0x00380000)
11065 
11066 /*
11067  * Field : Reserved_31to22
11068  *
11069  * Reserved
11070  *
11071  * Field Access Macros:
11072  *
11073  */
11074 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_8_RSVD_31TO22 register field. */
11075 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_31TO22_LSB 22
11076 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_8_RSVD_31TO22 register field. */
11077 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_31TO22_MSB 31
11078 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_8_RSVD_31TO22 register field. */
11079 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_31TO22_WIDTH 10
11080 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_8_RSVD_31TO22 register field value. */
11081 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_31TO22_SET_MSK 0xffc00000
11082 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_8_RSVD_31TO22 register field value. */
11083 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_31TO22_CLR_MSK 0x003fffff
11084 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_8_RSVD_31TO22 register field. */
11085 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_31TO22_RESET 0x0
11086 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_8_RSVD_31TO22 field value from a register. */
11087 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_31TO22_GET(value) (((value) & 0xffc00000) >> 22)
11088 /* Produces a ALT_PINMUX_DCTD_IO_CFG_8_RSVD_31TO22 register field value suitable for setting the register. */
11089 #define ALT_PINMUX_DCTD_IO_CFG_8_RSVD_31TO22_SET(value) (((value) << 22) & 0xffc00000)
11090 
11091 #ifndef __ASSEMBLY__
11092 /*
11093  * WARNING: The C register and register group struct declarations are provided for
11094  * convenience and illustrative purposes. They should, however, be used with
11095  * caution as the C language standard provides no guarantees about the alignment or
11096  * atomicity of device memory accesses. The recommended practice for writing
11097  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11098  * alt_write_word() functions.
11099  *
11100  * The struct declaration for register ALT_PINMUX_DCTD_IO_CFG_8.
11101  */
11102 struct ALT_PINMUX_DCTD_IO_CFG_8_s
11103 {
11104  uint32_t PD_DRV_STRG : 5; /* Pull down drive strength */
11105  uint32_t PD_SLW_RT : 1; /* NMOS slew rate */
11106  const uint32_t Reserved_7to6 : 2; /* ALT_PINMUX_DCTD_IO_CFG_8_RSVD_7TO6 */
11107  uint32_t PU_DRV_STRG : 5; /* Pull up drive strength */
11108  uint32_t PU_SLW_RT : 1; /* PMOS slew rate */
11109  const uint32_t Reserved_15to14 : 2; /* ALT_PINMUX_DCTD_IO_CFG_8_RSVD_15TO14 */
11110  uint32_t WK_PU_EN : 1; /* Weak pull up signal */
11111  uint32_t INPUT_BUF_EN : 2; /* LVTTL input buffer enable signal */
11112  uint32_t RTRIM : 3; /* Bias trim bits */
11113  const uint32_t Reserved_31to22 : 10; /* ALT_PINMUX_DCTD_IO_CFG_8_RSVD_31TO22 */
11114 };
11115 
11116 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_CFG_8. */
11117 typedef volatile struct ALT_PINMUX_DCTD_IO_CFG_8_s ALT_PINMUX_DCTD_IO_CFG_8_t;
11118 #endif /* __ASSEMBLY__ */
11119 
11120 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_8 register. */
11121 #define ALT_PINMUX_DCTD_IO_CFG_8_RESET 0x000d0008
11122 /* The byte offset of the ALT_PINMUX_DCTD_IO_CFG_8 register from the beginning of the component. */
11123 #define ALT_PINMUX_DCTD_IO_CFG_8_OFST 0x120
11124 
11125 /*
11126  * Register : Dedicated IO 9 Configuration Register - configuration_dedicated_io_9
11127  *
11128  * This register is used to control the electrical behavior and direction of
11129  * Dedicated IO 9
11130  *
11131  * Only reset by a cold reset (ignores warm reset).
11132  *
11133  * Register Layout
11134  *
11135  * Bits | Access | Reset | Description
11136  * :--------|:-------|:------|:-------------------------------------
11137  * [4:0] | RW | 0x8 | Pull down drive strength
11138  * [5] | RW | 0x0 | NMOS slew rate
11139  * [7:6] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_9_RSVD_7TO6
11140  * [12:8] | RW | 0x0 | Pull up drive strength
11141  * [13] | RW | 0x0 | PMOS slew rate
11142  * [15:14] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_9_RSVD_15TO14
11143  * [16] | RW | 0x1 | Weak pull up signal
11144  * [18:17] | RW | 0x2 | LVTTL input buffer enable signal
11145  * [21:19] | RW | 0x1 | Bias trim bits
11146  * [31:22] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_9_RSVD_31TO22
11147  *
11148  */
11149 /*
11150  * Field : Pull down drive strength - PD_DRV_STRG
11151  *
11152  * Configuration bits for NMOS pull down drive strength.
11153  *
11154  * Pending Characterization
11155  *
11156  * Field Access Macros:
11157  *
11158  */
11159 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_9_PD_DRV_STRG register field. */
11160 #define ALT_PINMUX_DCTD_IO_CFG_9_PD_DRV_STRG_LSB 0
11161 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_9_PD_DRV_STRG register field. */
11162 #define ALT_PINMUX_DCTD_IO_CFG_9_PD_DRV_STRG_MSB 4
11163 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_9_PD_DRV_STRG register field. */
11164 #define ALT_PINMUX_DCTD_IO_CFG_9_PD_DRV_STRG_WIDTH 5
11165 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_9_PD_DRV_STRG register field value. */
11166 #define ALT_PINMUX_DCTD_IO_CFG_9_PD_DRV_STRG_SET_MSK 0x0000001f
11167 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_9_PD_DRV_STRG register field value. */
11168 #define ALT_PINMUX_DCTD_IO_CFG_9_PD_DRV_STRG_CLR_MSK 0xffffffe0
11169 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_9_PD_DRV_STRG register field. */
11170 #define ALT_PINMUX_DCTD_IO_CFG_9_PD_DRV_STRG_RESET 0x8
11171 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_9_PD_DRV_STRG field value from a register. */
11172 #define ALT_PINMUX_DCTD_IO_CFG_9_PD_DRV_STRG_GET(value) (((value) & 0x0000001f) >> 0)
11173 /* Produces a ALT_PINMUX_DCTD_IO_CFG_9_PD_DRV_STRG register field value suitable for setting the register. */
11174 #define ALT_PINMUX_DCTD_IO_CFG_9_PD_DRV_STRG_SET(value) (((value) << 0) & 0x0000001f)
11175 
11176 /*
11177  * Field : NMOS slew rate - PD_SLW_RT
11178  *
11179  * Configuration bit for output pull down slew rate control
11180  *
11181  * 0 : slow N slew
11182  *
11183  * 1 : fast N slew
11184  *
11185  * Field Access Macros:
11186  *
11187  */
11188 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_9_PD_SLW_RT register field. */
11189 #define ALT_PINMUX_DCTD_IO_CFG_9_PD_SLW_RT_LSB 5
11190 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_9_PD_SLW_RT register field. */
11191 #define ALT_PINMUX_DCTD_IO_CFG_9_PD_SLW_RT_MSB 5
11192 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_9_PD_SLW_RT register field. */
11193 #define ALT_PINMUX_DCTD_IO_CFG_9_PD_SLW_RT_WIDTH 1
11194 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_9_PD_SLW_RT register field value. */
11195 #define ALT_PINMUX_DCTD_IO_CFG_9_PD_SLW_RT_SET_MSK 0x00000020
11196 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_9_PD_SLW_RT register field value. */
11197 #define ALT_PINMUX_DCTD_IO_CFG_9_PD_SLW_RT_CLR_MSK 0xffffffdf
11198 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_9_PD_SLW_RT register field. */
11199 #define ALT_PINMUX_DCTD_IO_CFG_9_PD_SLW_RT_RESET 0x0
11200 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_9_PD_SLW_RT field value from a register. */
11201 #define ALT_PINMUX_DCTD_IO_CFG_9_PD_SLW_RT_GET(value) (((value) & 0x00000020) >> 5)
11202 /* Produces a ALT_PINMUX_DCTD_IO_CFG_9_PD_SLW_RT register field value suitable for setting the register. */
11203 #define ALT_PINMUX_DCTD_IO_CFG_9_PD_SLW_RT_SET(value) (((value) << 5) & 0x00000020)
11204 
11205 /*
11206  * Field : Reserved_7to6
11207  *
11208  * Reserved
11209  *
11210  * Field Access Macros:
11211  *
11212  */
11213 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_9_RSVD_7TO6 register field. */
11214 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_7TO6_LSB 6
11215 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_9_RSVD_7TO6 register field. */
11216 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_7TO6_MSB 7
11217 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_9_RSVD_7TO6 register field. */
11218 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_7TO6_WIDTH 2
11219 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_9_RSVD_7TO6 register field value. */
11220 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_7TO6_SET_MSK 0x000000c0
11221 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_9_RSVD_7TO6 register field value. */
11222 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_7TO6_CLR_MSK 0xffffff3f
11223 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_9_RSVD_7TO6 register field. */
11224 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_7TO6_RESET 0x0
11225 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_9_RSVD_7TO6 field value from a register. */
11226 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_7TO6_GET(value) (((value) & 0x000000c0) >> 6)
11227 /* Produces a ALT_PINMUX_DCTD_IO_CFG_9_RSVD_7TO6 register field value suitable for setting the register. */
11228 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_7TO6_SET(value) (((value) << 6) & 0x000000c0)
11229 
11230 /*
11231  * Field : Pull up drive strength - PU_DRV_STRG
11232  *
11233  * Configuration bits for PMOS pull up drive strength
11234  *
11235  * Pending Characterization
11236  *
11237  * Field Access Macros:
11238  *
11239  */
11240 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_9_PU_DRV_STRG register field. */
11241 #define ALT_PINMUX_DCTD_IO_CFG_9_PU_DRV_STRG_LSB 8
11242 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_9_PU_DRV_STRG register field. */
11243 #define ALT_PINMUX_DCTD_IO_CFG_9_PU_DRV_STRG_MSB 12
11244 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_9_PU_DRV_STRG register field. */
11245 #define ALT_PINMUX_DCTD_IO_CFG_9_PU_DRV_STRG_WIDTH 5
11246 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_9_PU_DRV_STRG register field value. */
11247 #define ALT_PINMUX_DCTD_IO_CFG_9_PU_DRV_STRG_SET_MSK 0x00001f00
11248 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_9_PU_DRV_STRG register field value. */
11249 #define ALT_PINMUX_DCTD_IO_CFG_9_PU_DRV_STRG_CLR_MSK 0xffffe0ff
11250 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_9_PU_DRV_STRG register field. */
11251 #define ALT_PINMUX_DCTD_IO_CFG_9_PU_DRV_STRG_RESET 0x0
11252 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_9_PU_DRV_STRG field value from a register. */
11253 #define ALT_PINMUX_DCTD_IO_CFG_9_PU_DRV_STRG_GET(value) (((value) & 0x00001f00) >> 8)
11254 /* Produces a ALT_PINMUX_DCTD_IO_CFG_9_PU_DRV_STRG register field value suitable for setting the register. */
11255 #define ALT_PINMUX_DCTD_IO_CFG_9_PU_DRV_STRG_SET(value) (((value) << 8) & 0x00001f00)
11256 
11257 /*
11258  * Field : PMOS slew rate - PU_SLW_RT
11259  *
11260  * Configuration bit for output pull up slew rate control
11261  *
11262  * 0 : slow P slew
11263  *
11264  * 1 : fast P slew
11265  *
11266  * Field Access Macros:
11267  *
11268  */
11269 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_9_PU_SLW_RT register field. */
11270 #define ALT_PINMUX_DCTD_IO_CFG_9_PU_SLW_RT_LSB 13
11271 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_9_PU_SLW_RT register field. */
11272 #define ALT_PINMUX_DCTD_IO_CFG_9_PU_SLW_RT_MSB 13
11273 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_9_PU_SLW_RT register field. */
11274 #define ALT_PINMUX_DCTD_IO_CFG_9_PU_SLW_RT_WIDTH 1
11275 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_9_PU_SLW_RT register field value. */
11276 #define ALT_PINMUX_DCTD_IO_CFG_9_PU_SLW_RT_SET_MSK 0x00002000
11277 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_9_PU_SLW_RT register field value. */
11278 #define ALT_PINMUX_DCTD_IO_CFG_9_PU_SLW_RT_CLR_MSK 0xffffdfff
11279 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_9_PU_SLW_RT register field. */
11280 #define ALT_PINMUX_DCTD_IO_CFG_9_PU_SLW_RT_RESET 0x0
11281 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_9_PU_SLW_RT field value from a register. */
11282 #define ALT_PINMUX_DCTD_IO_CFG_9_PU_SLW_RT_GET(value) (((value) & 0x00002000) >> 13)
11283 /* Produces a ALT_PINMUX_DCTD_IO_CFG_9_PU_SLW_RT register field value suitable for setting the register. */
11284 #define ALT_PINMUX_DCTD_IO_CFG_9_PU_SLW_RT_SET(value) (((value) << 13) & 0x00002000)
11285 
11286 /*
11287  * Field : Reserved_15to14
11288  *
11289  * Reserved
11290  *
11291  * Field Access Macros:
11292  *
11293  */
11294 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_9_RSVD_15TO14 register field. */
11295 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_15TO14_LSB 14
11296 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_9_RSVD_15TO14 register field. */
11297 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_15TO14_MSB 15
11298 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_9_RSVD_15TO14 register field. */
11299 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_15TO14_WIDTH 2
11300 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_9_RSVD_15TO14 register field value. */
11301 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_15TO14_SET_MSK 0x0000c000
11302 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_9_RSVD_15TO14 register field value. */
11303 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_15TO14_CLR_MSK 0xffff3fff
11304 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_9_RSVD_15TO14 register field. */
11305 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_15TO14_RESET 0x0
11306 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_9_RSVD_15TO14 field value from a register. */
11307 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_15TO14_GET(value) (((value) & 0x0000c000) >> 14)
11308 /* Produces a ALT_PINMUX_DCTD_IO_CFG_9_RSVD_15TO14 register field value suitable for setting the register. */
11309 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_15TO14_SET(value) (((value) << 14) & 0x0000c000)
11310 
11311 /*
11312  * Field : Weak pull up signal - WK_PU_EN
11313  *
11314  * Configuration bit for weak pull up enable
11315  *
11316  * 0 : weak pull up disable
11317  *
11318  * 1 : weak pull up enable
11319  *
11320  * Field Access Macros:
11321  *
11322  */
11323 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_9_WK_PU_EN register field. */
11324 #define ALT_PINMUX_DCTD_IO_CFG_9_WK_PU_EN_LSB 16
11325 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_9_WK_PU_EN register field. */
11326 #define ALT_PINMUX_DCTD_IO_CFG_9_WK_PU_EN_MSB 16
11327 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_9_WK_PU_EN register field. */
11328 #define ALT_PINMUX_DCTD_IO_CFG_9_WK_PU_EN_WIDTH 1
11329 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_9_WK_PU_EN register field value. */
11330 #define ALT_PINMUX_DCTD_IO_CFG_9_WK_PU_EN_SET_MSK 0x00010000
11331 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_9_WK_PU_EN register field value. */
11332 #define ALT_PINMUX_DCTD_IO_CFG_9_WK_PU_EN_CLR_MSK 0xfffeffff
11333 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_9_WK_PU_EN register field. */
11334 #define ALT_PINMUX_DCTD_IO_CFG_9_WK_PU_EN_RESET 0x1
11335 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_9_WK_PU_EN field value from a register. */
11336 #define ALT_PINMUX_DCTD_IO_CFG_9_WK_PU_EN_GET(value) (((value) & 0x00010000) >> 16)
11337 /* Produces a ALT_PINMUX_DCTD_IO_CFG_9_WK_PU_EN register field value suitable for setting the register. */
11338 #define ALT_PINMUX_DCTD_IO_CFG_9_WK_PU_EN_SET(value) (((value) << 16) & 0x00010000)
11339 
11340 /*
11341  * Field : LVTTL input buffer enable signal - INPUT_BUF_EN
11342  *
11343  * Configuration bits for LVTTL input buffer enable
11344  *
11345  * 00 : disable
11346  *
11347  * 01 : 1.8V TTL
11348  *
11349  * 10 : 2.5V/3.0V TTL
11350  *
11351  * 11 : 1.8V TTL
11352  *
11353  * Field Access Macros:
11354  *
11355  */
11356 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_9_INPUT_BUF_EN register field. */
11357 #define ALT_PINMUX_DCTD_IO_CFG_9_INPUT_BUF_EN_LSB 17
11358 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_9_INPUT_BUF_EN register field. */
11359 #define ALT_PINMUX_DCTD_IO_CFG_9_INPUT_BUF_EN_MSB 18
11360 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_9_INPUT_BUF_EN register field. */
11361 #define ALT_PINMUX_DCTD_IO_CFG_9_INPUT_BUF_EN_WIDTH 2
11362 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_9_INPUT_BUF_EN register field value. */
11363 #define ALT_PINMUX_DCTD_IO_CFG_9_INPUT_BUF_EN_SET_MSK 0x00060000
11364 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_9_INPUT_BUF_EN register field value. */
11365 #define ALT_PINMUX_DCTD_IO_CFG_9_INPUT_BUF_EN_CLR_MSK 0xfff9ffff
11366 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_9_INPUT_BUF_EN register field. */
11367 #define ALT_PINMUX_DCTD_IO_CFG_9_INPUT_BUF_EN_RESET 0x2
11368 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_9_INPUT_BUF_EN field value from a register. */
11369 #define ALT_PINMUX_DCTD_IO_CFG_9_INPUT_BUF_EN_GET(value) (((value) & 0x00060000) >> 17)
11370 /* Produces a ALT_PINMUX_DCTD_IO_CFG_9_INPUT_BUF_EN register field value suitable for setting the register. */
11371 #define ALT_PINMUX_DCTD_IO_CFG_9_INPUT_BUF_EN_SET(value) (((value) << 17) & 0x00060000)
11372 
11373 /*
11374  * Field : Bias trim bits - RTRIM
11375  *
11376  * Configuration bits for bias trim
11377  *
11378  * 000 : disable
11379  *
11380  * 001 : default
11381  *
11382  * 010 : trim low
11383  *
11384  * 100 : trim high
11385  *
11386  * others : invalid/reserved
11387  *
11388  * Field Access Macros:
11389  *
11390  */
11391 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_9_RTRIM register field. */
11392 #define ALT_PINMUX_DCTD_IO_CFG_9_RTRIM_LSB 19
11393 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_9_RTRIM register field. */
11394 #define ALT_PINMUX_DCTD_IO_CFG_9_RTRIM_MSB 21
11395 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_9_RTRIM register field. */
11396 #define ALT_PINMUX_DCTD_IO_CFG_9_RTRIM_WIDTH 3
11397 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_9_RTRIM register field value. */
11398 #define ALT_PINMUX_DCTD_IO_CFG_9_RTRIM_SET_MSK 0x00380000
11399 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_9_RTRIM register field value. */
11400 #define ALT_PINMUX_DCTD_IO_CFG_9_RTRIM_CLR_MSK 0xffc7ffff
11401 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_9_RTRIM register field. */
11402 #define ALT_PINMUX_DCTD_IO_CFG_9_RTRIM_RESET 0x1
11403 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_9_RTRIM field value from a register. */
11404 #define ALT_PINMUX_DCTD_IO_CFG_9_RTRIM_GET(value) (((value) & 0x00380000) >> 19)
11405 /* Produces a ALT_PINMUX_DCTD_IO_CFG_9_RTRIM register field value suitable for setting the register. */
11406 #define ALT_PINMUX_DCTD_IO_CFG_9_RTRIM_SET(value) (((value) << 19) & 0x00380000)
11407 
11408 /*
11409  * Field : Reserved_31to22
11410  *
11411  * Reserved
11412  *
11413  * Field Access Macros:
11414  *
11415  */
11416 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_9_RSVD_31TO22 register field. */
11417 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_31TO22_LSB 22
11418 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_9_RSVD_31TO22 register field. */
11419 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_31TO22_MSB 31
11420 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_9_RSVD_31TO22 register field. */
11421 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_31TO22_WIDTH 10
11422 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_9_RSVD_31TO22 register field value. */
11423 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_31TO22_SET_MSK 0xffc00000
11424 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_9_RSVD_31TO22 register field value. */
11425 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_31TO22_CLR_MSK 0x003fffff
11426 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_9_RSVD_31TO22 register field. */
11427 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_31TO22_RESET 0x0
11428 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_9_RSVD_31TO22 field value from a register. */
11429 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_31TO22_GET(value) (((value) & 0xffc00000) >> 22)
11430 /* Produces a ALT_PINMUX_DCTD_IO_CFG_9_RSVD_31TO22 register field value suitable for setting the register. */
11431 #define ALT_PINMUX_DCTD_IO_CFG_9_RSVD_31TO22_SET(value) (((value) << 22) & 0xffc00000)
11432 
11433 #ifndef __ASSEMBLY__
11434 /*
11435  * WARNING: The C register and register group struct declarations are provided for
11436  * convenience and illustrative purposes. They should, however, be used with
11437  * caution as the C language standard provides no guarantees about the alignment or
11438  * atomicity of device memory accesses. The recommended practice for writing
11439  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11440  * alt_write_word() functions.
11441  *
11442  * The struct declaration for register ALT_PINMUX_DCTD_IO_CFG_9.
11443  */
11444 struct ALT_PINMUX_DCTD_IO_CFG_9_s
11445 {
11446  uint32_t PD_DRV_STRG : 5; /* Pull down drive strength */
11447  uint32_t PD_SLW_RT : 1; /* NMOS slew rate */
11448  const uint32_t Reserved_7to6 : 2; /* ALT_PINMUX_DCTD_IO_CFG_9_RSVD_7TO6 */
11449  uint32_t PU_DRV_STRG : 5; /* Pull up drive strength */
11450  uint32_t PU_SLW_RT : 1; /* PMOS slew rate */
11451  const uint32_t Reserved_15to14 : 2; /* ALT_PINMUX_DCTD_IO_CFG_9_RSVD_15TO14 */
11452  uint32_t WK_PU_EN : 1; /* Weak pull up signal */
11453  uint32_t INPUT_BUF_EN : 2; /* LVTTL input buffer enable signal */
11454  uint32_t RTRIM : 3; /* Bias trim bits */
11455  const uint32_t Reserved_31to22 : 10; /* ALT_PINMUX_DCTD_IO_CFG_9_RSVD_31TO22 */
11456 };
11457 
11458 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_CFG_9. */
11459 typedef volatile struct ALT_PINMUX_DCTD_IO_CFG_9_s ALT_PINMUX_DCTD_IO_CFG_9_t;
11460 #endif /* __ASSEMBLY__ */
11461 
11462 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_9 register. */
11463 #define ALT_PINMUX_DCTD_IO_CFG_9_RESET 0x000d0008
11464 /* The byte offset of the ALT_PINMUX_DCTD_IO_CFG_9 register from the beginning of the component. */
11465 #define ALT_PINMUX_DCTD_IO_CFG_9_OFST 0x124
11466 
11467 /*
11468  * Register : Dedicated IO 10 Configuration Register - configuration_dedicated_io_10
11469  *
11470  * This register is used to control the electrical behavior and direction of
11471  * Dedicated IO 10
11472  *
11473  * Only reset by a cold reset (ignores warm reset).
11474  *
11475  * Register Layout
11476  *
11477  * Bits | Access | Reset | Description
11478  * :--------|:-------|:------|:--------------------------------------
11479  * [4:0] | RW | 0x8 | Pull down drive strength
11480  * [5] | RW | 0x0 | NMOS slew rate
11481  * [7:6] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_10_RSVD_7TO6
11482  * [12:8] | RW | 0x0 | Pull up drive strength
11483  * [13] | RW | 0x0 | PMOS slew rate
11484  * [15:14] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_10_RSVD_15TO14
11485  * [16] | RW | 0x1 | Weak pull up signal
11486  * [18:17] | RW | 0x2 | LVTTL input buffer enable signal
11487  * [21:19] | RW | 0x1 | Bias trim bits
11488  * [31:22] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_10_RSVD_31TO22
11489  *
11490  */
11491 /*
11492  * Field : Pull down drive strength - PD_DRV_STRG
11493  *
11494  * Configuration bits for NMOS pull down drive strength.
11495  *
11496  * Pending Characterization
11497  *
11498  * Field Access Macros:
11499  *
11500  */
11501 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_10_PD_DRV_STRG register field. */
11502 #define ALT_PINMUX_DCTD_IO_CFG_10_PD_DRV_STRG_LSB 0
11503 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_10_PD_DRV_STRG register field. */
11504 #define ALT_PINMUX_DCTD_IO_CFG_10_PD_DRV_STRG_MSB 4
11505 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_10_PD_DRV_STRG register field. */
11506 #define ALT_PINMUX_DCTD_IO_CFG_10_PD_DRV_STRG_WIDTH 5
11507 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_10_PD_DRV_STRG register field value. */
11508 #define ALT_PINMUX_DCTD_IO_CFG_10_PD_DRV_STRG_SET_MSK 0x0000001f
11509 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_10_PD_DRV_STRG register field value. */
11510 #define ALT_PINMUX_DCTD_IO_CFG_10_PD_DRV_STRG_CLR_MSK 0xffffffe0
11511 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_10_PD_DRV_STRG register field. */
11512 #define ALT_PINMUX_DCTD_IO_CFG_10_PD_DRV_STRG_RESET 0x8
11513 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_10_PD_DRV_STRG field value from a register. */
11514 #define ALT_PINMUX_DCTD_IO_CFG_10_PD_DRV_STRG_GET(value) (((value) & 0x0000001f) >> 0)
11515 /* Produces a ALT_PINMUX_DCTD_IO_CFG_10_PD_DRV_STRG register field value suitable for setting the register. */
11516 #define ALT_PINMUX_DCTD_IO_CFG_10_PD_DRV_STRG_SET(value) (((value) << 0) & 0x0000001f)
11517 
11518 /*
11519  * Field : NMOS slew rate - PD_SLW_RT
11520  *
11521  * Configuration bit for output pull down slew rate control
11522  *
11523  * 0 : slow N slew
11524  *
11525  * 1 : fast N slew
11526  *
11527  * Field Access Macros:
11528  *
11529  */
11530 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_10_PD_SLW_RT register field. */
11531 #define ALT_PINMUX_DCTD_IO_CFG_10_PD_SLW_RT_LSB 5
11532 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_10_PD_SLW_RT register field. */
11533 #define ALT_PINMUX_DCTD_IO_CFG_10_PD_SLW_RT_MSB 5
11534 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_10_PD_SLW_RT register field. */
11535 #define ALT_PINMUX_DCTD_IO_CFG_10_PD_SLW_RT_WIDTH 1
11536 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_10_PD_SLW_RT register field value. */
11537 #define ALT_PINMUX_DCTD_IO_CFG_10_PD_SLW_RT_SET_MSK 0x00000020
11538 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_10_PD_SLW_RT register field value. */
11539 #define ALT_PINMUX_DCTD_IO_CFG_10_PD_SLW_RT_CLR_MSK 0xffffffdf
11540 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_10_PD_SLW_RT register field. */
11541 #define ALT_PINMUX_DCTD_IO_CFG_10_PD_SLW_RT_RESET 0x0
11542 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_10_PD_SLW_RT field value from a register. */
11543 #define ALT_PINMUX_DCTD_IO_CFG_10_PD_SLW_RT_GET(value) (((value) & 0x00000020) >> 5)
11544 /* Produces a ALT_PINMUX_DCTD_IO_CFG_10_PD_SLW_RT register field value suitable for setting the register. */
11545 #define ALT_PINMUX_DCTD_IO_CFG_10_PD_SLW_RT_SET(value) (((value) << 5) & 0x00000020)
11546 
11547 /*
11548  * Field : Reserved_7to6
11549  *
11550  * Reserved
11551  *
11552  * Field Access Macros:
11553  *
11554  */
11555 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_10_RSVD_7TO6 register field. */
11556 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_7TO6_LSB 6
11557 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_10_RSVD_7TO6 register field. */
11558 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_7TO6_MSB 7
11559 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_10_RSVD_7TO6 register field. */
11560 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_7TO6_WIDTH 2
11561 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_10_RSVD_7TO6 register field value. */
11562 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_7TO6_SET_MSK 0x000000c0
11563 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_10_RSVD_7TO6 register field value. */
11564 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_7TO6_CLR_MSK 0xffffff3f
11565 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_10_RSVD_7TO6 register field. */
11566 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_7TO6_RESET 0x0
11567 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_10_RSVD_7TO6 field value from a register. */
11568 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_7TO6_GET(value) (((value) & 0x000000c0) >> 6)
11569 /* Produces a ALT_PINMUX_DCTD_IO_CFG_10_RSVD_7TO6 register field value suitable for setting the register. */
11570 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_7TO6_SET(value) (((value) << 6) & 0x000000c0)
11571 
11572 /*
11573  * Field : Pull up drive strength - PU_DRV_STRG
11574  *
11575  * Configuration bits for PMOS pull up drive strength
11576  *
11577  * Pending Characterization
11578  *
11579  * Field Access Macros:
11580  *
11581  */
11582 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_10_PU_DRV_STRG register field. */
11583 #define ALT_PINMUX_DCTD_IO_CFG_10_PU_DRV_STRG_LSB 8
11584 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_10_PU_DRV_STRG register field. */
11585 #define ALT_PINMUX_DCTD_IO_CFG_10_PU_DRV_STRG_MSB 12
11586 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_10_PU_DRV_STRG register field. */
11587 #define ALT_PINMUX_DCTD_IO_CFG_10_PU_DRV_STRG_WIDTH 5
11588 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_10_PU_DRV_STRG register field value. */
11589 #define ALT_PINMUX_DCTD_IO_CFG_10_PU_DRV_STRG_SET_MSK 0x00001f00
11590 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_10_PU_DRV_STRG register field value. */
11591 #define ALT_PINMUX_DCTD_IO_CFG_10_PU_DRV_STRG_CLR_MSK 0xffffe0ff
11592 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_10_PU_DRV_STRG register field. */
11593 #define ALT_PINMUX_DCTD_IO_CFG_10_PU_DRV_STRG_RESET 0x0
11594 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_10_PU_DRV_STRG field value from a register. */
11595 #define ALT_PINMUX_DCTD_IO_CFG_10_PU_DRV_STRG_GET(value) (((value) & 0x00001f00) >> 8)
11596 /* Produces a ALT_PINMUX_DCTD_IO_CFG_10_PU_DRV_STRG register field value suitable for setting the register. */
11597 #define ALT_PINMUX_DCTD_IO_CFG_10_PU_DRV_STRG_SET(value) (((value) << 8) & 0x00001f00)
11598 
11599 /*
11600  * Field : PMOS slew rate - PU_SLW_RT
11601  *
11602  * Configuration bit for output pull up slew rate control
11603  *
11604  * 0 : slow P slew
11605  *
11606  * 1 : fast P slew
11607  *
11608  * Field Access Macros:
11609  *
11610  */
11611 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_10_PU_SLW_RT register field. */
11612 #define ALT_PINMUX_DCTD_IO_CFG_10_PU_SLW_RT_LSB 13
11613 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_10_PU_SLW_RT register field. */
11614 #define ALT_PINMUX_DCTD_IO_CFG_10_PU_SLW_RT_MSB 13
11615 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_10_PU_SLW_RT register field. */
11616 #define ALT_PINMUX_DCTD_IO_CFG_10_PU_SLW_RT_WIDTH 1
11617 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_10_PU_SLW_RT register field value. */
11618 #define ALT_PINMUX_DCTD_IO_CFG_10_PU_SLW_RT_SET_MSK 0x00002000
11619 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_10_PU_SLW_RT register field value. */
11620 #define ALT_PINMUX_DCTD_IO_CFG_10_PU_SLW_RT_CLR_MSK 0xffffdfff
11621 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_10_PU_SLW_RT register field. */
11622 #define ALT_PINMUX_DCTD_IO_CFG_10_PU_SLW_RT_RESET 0x0
11623 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_10_PU_SLW_RT field value from a register. */
11624 #define ALT_PINMUX_DCTD_IO_CFG_10_PU_SLW_RT_GET(value) (((value) & 0x00002000) >> 13)
11625 /* Produces a ALT_PINMUX_DCTD_IO_CFG_10_PU_SLW_RT register field value suitable for setting the register. */
11626 #define ALT_PINMUX_DCTD_IO_CFG_10_PU_SLW_RT_SET(value) (((value) << 13) & 0x00002000)
11627 
11628 /*
11629  * Field : Reserved_15to14
11630  *
11631  * Reserved
11632  *
11633  * Field Access Macros:
11634  *
11635  */
11636 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_10_RSVD_15TO14 register field. */
11637 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_15TO14_LSB 14
11638 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_10_RSVD_15TO14 register field. */
11639 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_15TO14_MSB 15
11640 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_10_RSVD_15TO14 register field. */
11641 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_15TO14_WIDTH 2
11642 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_10_RSVD_15TO14 register field value. */
11643 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_15TO14_SET_MSK 0x0000c000
11644 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_10_RSVD_15TO14 register field value. */
11645 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_15TO14_CLR_MSK 0xffff3fff
11646 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_10_RSVD_15TO14 register field. */
11647 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_15TO14_RESET 0x0
11648 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_10_RSVD_15TO14 field value from a register. */
11649 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_15TO14_GET(value) (((value) & 0x0000c000) >> 14)
11650 /* Produces a ALT_PINMUX_DCTD_IO_CFG_10_RSVD_15TO14 register field value suitable for setting the register. */
11651 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_15TO14_SET(value) (((value) << 14) & 0x0000c000)
11652 
11653 /*
11654  * Field : Weak pull up signal - WK_PU_EN
11655  *
11656  * Configuration bit for weak pull up enable
11657  *
11658  * 0 : weak pull up disable
11659  *
11660  * 1 : weak pull up enable
11661  *
11662  * Field Access Macros:
11663  *
11664  */
11665 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_10_WK_PU_EN register field. */
11666 #define ALT_PINMUX_DCTD_IO_CFG_10_WK_PU_EN_LSB 16
11667 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_10_WK_PU_EN register field. */
11668 #define ALT_PINMUX_DCTD_IO_CFG_10_WK_PU_EN_MSB 16
11669 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_10_WK_PU_EN register field. */
11670 #define ALT_PINMUX_DCTD_IO_CFG_10_WK_PU_EN_WIDTH 1
11671 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_10_WK_PU_EN register field value. */
11672 #define ALT_PINMUX_DCTD_IO_CFG_10_WK_PU_EN_SET_MSK 0x00010000
11673 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_10_WK_PU_EN register field value. */
11674 #define ALT_PINMUX_DCTD_IO_CFG_10_WK_PU_EN_CLR_MSK 0xfffeffff
11675 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_10_WK_PU_EN register field. */
11676 #define ALT_PINMUX_DCTD_IO_CFG_10_WK_PU_EN_RESET 0x1
11677 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_10_WK_PU_EN field value from a register. */
11678 #define ALT_PINMUX_DCTD_IO_CFG_10_WK_PU_EN_GET(value) (((value) & 0x00010000) >> 16)
11679 /* Produces a ALT_PINMUX_DCTD_IO_CFG_10_WK_PU_EN register field value suitable for setting the register. */
11680 #define ALT_PINMUX_DCTD_IO_CFG_10_WK_PU_EN_SET(value) (((value) << 16) & 0x00010000)
11681 
11682 /*
11683  * Field : LVTTL input buffer enable signal - INPUT_BUF_EN
11684  *
11685  * Configuration bits for LVTTL input buffer enable
11686  *
11687  * 00 : disable
11688  *
11689  * 01 : 1.8V TTL
11690  *
11691  * 10 : 2.5V/3.0V TTL
11692  *
11693  * 11 : 1.8V TTL
11694  *
11695  * Field Access Macros:
11696  *
11697  */
11698 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_10_INPUT_BUF_EN register field. */
11699 #define ALT_PINMUX_DCTD_IO_CFG_10_INPUT_BUF_EN_LSB 17
11700 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_10_INPUT_BUF_EN register field. */
11701 #define ALT_PINMUX_DCTD_IO_CFG_10_INPUT_BUF_EN_MSB 18
11702 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_10_INPUT_BUF_EN register field. */
11703 #define ALT_PINMUX_DCTD_IO_CFG_10_INPUT_BUF_EN_WIDTH 2
11704 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_10_INPUT_BUF_EN register field value. */
11705 #define ALT_PINMUX_DCTD_IO_CFG_10_INPUT_BUF_EN_SET_MSK 0x00060000
11706 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_10_INPUT_BUF_EN register field value. */
11707 #define ALT_PINMUX_DCTD_IO_CFG_10_INPUT_BUF_EN_CLR_MSK 0xfff9ffff
11708 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_10_INPUT_BUF_EN register field. */
11709 #define ALT_PINMUX_DCTD_IO_CFG_10_INPUT_BUF_EN_RESET 0x2
11710 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_10_INPUT_BUF_EN field value from a register. */
11711 #define ALT_PINMUX_DCTD_IO_CFG_10_INPUT_BUF_EN_GET(value) (((value) & 0x00060000) >> 17)
11712 /* Produces a ALT_PINMUX_DCTD_IO_CFG_10_INPUT_BUF_EN register field value suitable for setting the register. */
11713 #define ALT_PINMUX_DCTD_IO_CFG_10_INPUT_BUF_EN_SET(value) (((value) << 17) & 0x00060000)
11714 
11715 /*
11716  * Field : Bias trim bits - RTRIM
11717  *
11718  * Configuration bits for bias trim
11719  *
11720  * 000 : disable
11721  *
11722  * 001 : default
11723  *
11724  * 010 : trim low
11725  *
11726  * 100 : trim high
11727  *
11728  * others : invalid/reserved
11729  *
11730  * Field Access Macros:
11731  *
11732  */
11733 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_10_RTRIM register field. */
11734 #define ALT_PINMUX_DCTD_IO_CFG_10_RTRIM_LSB 19
11735 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_10_RTRIM register field. */
11736 #define ALT_PINMUX_DCTD_IO_CFG_10_RTRIM_MSB 21
11737 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_10_RTRIM register field. */
11738 #define ALT_PINMUX_DCTD_IO_CFG_10_RTRIM_WIDTH 3
11739 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_10_RTRIM register field value. */
11740 #define ALT_PINMUX_DCTD_IO_CFG_10_RTRIM_SET_MSK 0x00380000
11741 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_10_RTRIM register field value. */
11742 #define ALT_PINMUX_DCTD_IO_CFG_10_RTRIM_CLR_MSK 0xffc7ffff
11743 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_10_RTRIM register field. */
11744 #define ALT_PINMUX_DCTD_IO_CFG_10_RTRIM_RESET 0x1
11745 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_10_RTRIM field value from a register. */
11746 #define ALT_PINMUX_DCTD_IO_CFG_10_RTRIM_GET(value) (((value) & 0x00380000) >> 19)
11747 /* Produces a ALT_PINMUX_DCTD_IO_CFG_10_RTRIM register field value suitable for setting the register. */
11748 #define ALT_PINMUX_DCTD_IO_CFG_10_RTRIM_SET(value) (((value) << 19) & 0x00380000)
11749 
11750 /*
11751  * Field : Reserved_31to22
11752  *
11753  * Reserved
11754  *
11755  * Field Access Macros:
11756  *
11757  */
11758 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_10_RSVD_31TO22 register field. */
11759 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_31TO22_LSB 22
11760 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_10_RSVD_31TO22 register field. */
11761 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_31TO22_MSB 31
11762 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_10_RSVD_31TO22 register field. */
11763 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_31TO22_WIDTH 10
11764 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_10_RSVD_31TO22 register field value. */
11765 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_31TO22_SET_MSK 0xffc00000
11766 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_10_RSVD_31TO22 register field value. */
11767 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_31TO22_CLR_MSK 0x003fffff
11768 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_10_RSVD_31TO22 register field. */
11769 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_31TO22_RESET 0x0
11770 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_10_RSVD_31TO22 field value from a register. */
11771 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_31TO22_GET(value) (((value) & 0xffc00000) >> 22)
11772 /* Produces a ALT_PINMUX_DCTD_IO_CFG_10_RSVD_31TO22 register field value suitable for setting the register. */
11773 #define ALT_PINMUX_DCTD_IO_CFG_10_RSVD_31TO22_SET(value) (((value) << 22) & 0xffc00000)
11774 
11775 #ifndef __ASSEMBLY__
11776 /*
11777  * WARNING: The C register and register group struct declarations are provided for
11778  * convenience and illustrative purposes. They should, however, be used with
11779  * caution as the C language standard provides no guarantees about the alignment or
11780  * atomicity of device memory accesses. The recommended practice for writing
11781  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11782  * alt_write_word() functions.
11783  *
11784  * The struct declaration for register ALT_PINMUX_DCTD_IO_CFG_10.
11785  */
11786 struct ALT_PINMUX_DCTD_IO_CFG_10_s
11787 {
11788  uint32_t PD_DRV_STRG : 5; /* Pull down drive strength */
11789  uint32_t PD_SLW_RT : 1; /* NMOS slew rate */
11790  const uint32_t Reserved_7to6 : 2; /* ALT_PINMUX_DCTD_IO_CFG_10_RSVD_7TO6 */
11791  uint32_t PU_DRV_STRG : 5; /* Pull up drive strength */
11792  uint32_t PU_SLW_RT : 1; /* PMOS slew rate */
11793  const uint32_t Reserved_15to14 : 2; /* ALT_PINMUX_DCTD_IO_CFG_10_RSVD_15TO14 */
11794  uint32_t WK_PU_EN : 1; /* Weak pull up signal */
11795  uint32_t INPUT_BUF_EN : 2; /* LVTTL input buffer enable signal */
11796  uint32_t RTRIM : 3; /* Bias trim bits */
11797  const uint32_t Reserved_31to22 : 10; /* ALT_PINMUX_DCTD_IO_CFG_10_RSVD_31TO22 */
11798 };
11799 
11800 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_CFG_10. */
11801 typedef volatile struct ALT_PINMUX_DCTD_IO_CFG_10_s ALT_PINMUX_DCTD_IO_CFG_10_t;
11802 #endif /* __ASSEMBLY__ */
11803 
11804 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_10 register. */
11805 #define ALT_PINMUX_DCTD_IO_CFG_10_RESET 0x000d0008
11806 /* The byte offset of the ALT_PINMUX_DCTD_IO_CFG_10 register from the beginning of the component. */
11807 #define ALT_PINMUX_DCTD_IO_CFG_10_OFST 0x128
11808 
11809 /*
11810  * Register : Dedicated IO 11 Configuration Register - configuration_dedicated_io_11
11811  *
11812  * This register is used to control the electrical behavior and direction of
11813  * Dedicated IO 11
11814  *
11815  * Only reset by a cold reset (ignores warm reset).
11816  *
11817  * Register Layout
11818  *
11819  * Bits | Access | Reset | Description
11820  * :--------|:-------|:------|:--------------------------------------
11821  * [4:0] | RW | 0x8 | Pull down drive strength
11822  * [5] | RW | 0x0 | NMOS slew rate
11823  * [7:6] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_11_RSVD_7TO6
11824  * [12:8] | RW | 0x0 | Pull up drive strength
11825  * [13] | RW | 0x0 | PMOS slew rate
11826  * [15:14] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_11_RSVD_15TO14
11827  * [16] | RW | 0x1 | Weak pull up signal
11828  * [18:17] | RW | 0x2 | LVTTL input buffer enable signal
11829  * [21:19] | RW | 0x1 | Bias trim bits
11830  * [31:22] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_11_RSVD_31TO22
11831  *
11832  */
11833 /*
11834  * Field : Pull down drive strength - PD_DRV_STRG
11835  *
11836  * Configuration bits for NMOS pull down drive strength.
11837  *
11838  * Pending Characterization
11839  *
11840  * Field Access Macros:
11841  *
11842  */
11843 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_11_PD_DRV_STRG register field. */
11844 #define ALT_PINMUX_DCTD_IO_CFG_11_PD_DRV_STRG_LSB 0
11845 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_11_PD_DRV_STRG register field. */
11846 #define ALT_PINMUX_DCTD_IO_CFG_11_PD_DRV_STRG_MSB 4
11847 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_11_PD_DRV_STRG register field. */
11848 #define ALT_PINMUX_DCTD_IO_CFG_11_PD_DRV_STRG_WIDTH 5
11849 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_11_PD_DRV_STRG register field value. */
11850 #define ALT_PINMUX_DCTD_IO_CFG_11_PD_DRV_STRG_SET_MSK 0x0000001f
11851 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_11_PD_DRV_STRG register field value. */
11852 #define ALT_PINMUX_DCTD_IO_CFG_11_PD_DRV_STRG_CLR_MSK 0xffffffe0
11853 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_11_PD_DRV_STRG register field. */
11854 #define ALT_PINMUX_DCTD_IO_CFG_11_PD_DRV_STRG_RESET 0x8
11855 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_11_PD_DRV_STRG field value from a register. */
11856 #define ALT_PINMUX_DCTD_IO_CFG_11_PD_DRV_STRG_GET(value) (((value) & 0x0000001f) >> 0)
11857 /* Produces a ALT_PINMUX_DCTD_IO_CFG_11_PD_DRV_STRG register field value suitable for setting the register. */
11858 #define ALT_PINMUX_DCTD_IO_CFG_11_PD_DRV_STRG_SET(value) (((value) << 0) & 0x0000001f)
11859 
11860 /*
11861  * Field : NMOS slew rate - PD_SLW_RT
11862  *
11863  * Configuration bit for output pull down slew rate control
11864  *
11865  * 0 : slow N slew
11866  *
11867  * 1 : fast N slew
11868  *
11869  * Field Access Macros:
11870  *
11871  */
11872 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_11_PD_SLW_RT register field. */
11873 #define ALT_PINMUX_DCTD_IO_CFG_11_PD_SLW_RT_LSB 5
11874 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_11_PD_SLW_RT register field. */
11875 #define ALT_PINMUX_DCTD_IO_CFG_11_PD_SLW_RT_MSB 5
11876 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_11_PD_SLW_RT register field. */
11877 #define ALT_PINMUX_DCTD_IO_CFG_11_PD_SLW_RT_WIDTH 1
11878 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_11_PD_SLW_RT register field value. */
11879 #define ALT_PINMUX_DCTD_IO_CFG_11_PD_SLW_RT_SET_MSK 0x00000020
11880 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_11_PD_SLW_RT register field value. */
11881 #define ALT_PINMUX_DCTD_IO_CFG_11_PD_SLW_RT_CLR_MSK 0xffffffdf
11882 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_11_PD_SLW_RT register field. */
11883 #define ALT_PINMUX_DCTD_IO_CFG_11_PD_SLW_RT_RESET 0x0
11884 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_11_PD_SLW_RT field value from a register. */
11885 #define ALT_PINMUX_DCTD_IO_CFG_11_PD_SLW_RT_GET(value) (((value) & 0x00000020) >> 5)
11886 /* Produces a ALT_PINMUX_DCTD_IO_CFG_11_PD_SLW_RT register field value suitable for setting the register. */
11887 #define ALT_PINMUX_DCTD_IO_CFG_11_PD_SLW_RT_SET(value) (((value) << 5) & 0x00000020)
11888 
11889 /*
11890  * Field : Reserved_7to6
11891  *
11892  * Reserved
11893  *
11894  * Field Access Macros:
11895  *
11896  */
11897 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_11_RSVD_7TO6 register field. */
11898 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_7TO6_LSB 6
11899 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_11_RSVD_7TO6 register field. */
11900 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_7TO6_MSB 7
11901 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_11_RSVD_7TO6 register field. */
11902 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_7TO6_WIDTH 2
11903 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_11_RSVD_7TO6 register field value. */
11904 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_7TO6_SET_MSK 0x000000c0
11905 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_11_RSVD_7TO6 register field value. */
11906 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_7TO6_CLR_MSK 0xffffff3f
11907 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_11_RSVD_7TO6 register field. */
11908 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_7TO6_RESET 0x0
11909 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_11_RSVD_7TO6 field value from a register. */
11910 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_7TO6_GET(value) (((value) & 0x000000c0) >> 6)
11911 /* Produces a ALT_PINMUX_DCTD_IO_CFG_11_RSVD_7TO6 register field value suitable for setting the register. */
11912 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_7TO6_SET(value) (((value) << 6) & 0x000000c0)
11913 
11914 /*
11915  * Field : Pull up drive strength - PU_DRV_STRG
11916  *
11917  * Configuration bits for PMOS pull up drive strength
11918  *
11919  * Pending Characterization
11920  *
11921  * Field Access Macros:
11922  *
11923  */
11924 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_11_PU_DRV_STRG register field. */
11925 #define ALT_PINMUX_DCTD_IO_CFG_11_PU_DRV_STRG_LSB 8
11926 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_11_PU_DRV_STRG register field. */
11927 #define ALT_PINMUX_DCTD_IO_CFG_11_PU_DRV_STRG_MSB 12
11928 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_11_PU_DRV_STRG register field. */
11929 #define ALT_PINMUX_DCTD_IO_CFG_11_PU_DRV_STRG_WIDTH 5
11930 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_11_PU_DRV_STRG register field value. */
11931 #define ALT_PINMUX_DCTD_IO_CFG_11_PU_DRV_STRG_SET_MSK 0x00001f00
11932 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_11_PU_DRV_STRG register field value. */
11933 #define ALT_PINMUX_DCTD_IO_CFG_11_PU_DRV_STRG_CLR_MSK 0xffffe0ff
11934 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_11_PU_DRV_STRG register field. */
11935 #define ALT_PINMUX_DCTD_IO_CFG_11_PU_DRV_STRG_RESET 0x0
11936 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_11_PU_DRV_STRG field value from a register. */
11937 #define ALT_PINMUX_DCTD_IO_CFG_11_PU_DRV_STRG_GET(value) (((value) & 0x00001f00) >> 8)
11938 /* Produces a ALT_PINMUX_DCTD_IO_CFG_11_PU_DRV_STRG register field value suitable for setting the register. */
11939 #define ALT_PINMUX_DCTD_IO_CFG_11_PU_DRV_STRG_SET(value) (((value) << 8) & 0x00001f00)
11940 
11941 /*
11942  * Field : PMOS slew rate - PU_SLW_RT
11943  *
11944  * Configuration bit for output pull up slew rate control
11945  *
11946  * 0 : slow P slew
11947  *
11948  * 1 : fast P slew
11949  *
11950  * Field Access Macros:
11951  *
11952  */
11953 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_11_PU_SLW_RT register field. */
11954 #define ALT_PINMUX_DCTD_IO_CFG_11_PU_SLW_RT_LSB 13
11955 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_11_PU_SLW_RT register field. */
11956 #define ALT_PINMUX_DCTD_IO_CFG_11_PU_SLW_RT_MSB 13
11957 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_11_PU_SLW_RT register field. */
11958 #define ALT_PINMUX_DCTD_IO_CFG_11_PU_SLW_RT_WIDTH 1
11959 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_11_PU_SLW_RT register field value. */
11960 #define ALT_PINMUX_DCTD_IO_CFG_11_PU_SLW_RT_SET_MSK 0x00002000
11961 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_11_PU_SLW_RT register field value. */
11962 #define ALT_PINMUX_DCTD_IO_CFG_11_PU_SLW_RT_CLR_MSK 0xffffdfff
11963 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_11_PU_SLW_RT register field. */
11964 #define ALT_PINMUX_DCTD_IO_CFG_11_PU_SLW_RT_RESET 0x0
11965 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_11_PU_SLW_RT field value from a register. */
11966 #define ALT_PINMUX_DCTD_IO_CFG_11_PU_SLW_RT_GET(value) (((value) & 0x00002000) >> 13)
11967 /* Produces a ALT_PINMUX_DCTD_IO_CFG_11_PU_SLW_RT register field value suitable for setting the register. */
11968 #define ALT_PINMUX_DCTD_IO_CFG_11_PU_SLW_RT_SET(value) (((value) << 13) & 0x00002000)
11969 
11970 /*
11971  * Field : Reserved_15to14
11972  *
11973  * Reserved
11974  *
11975  * Field Access Macros:
11976  *
11977  */
11978 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_11_RSVD_15TO14 register field. */
11979 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_15TO14_LSB 14
11980 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_11_RSVD_15TO14 register field. */
11981 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_15TO14_MSB 15
11982 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_11_RSVD_15TO14 register field. */
11983 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_15TO14_WIDTH 2
11984 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_11_RSVD_15TO14 register field value. */
11985 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_15TO14_SET_MSK 0x0000c000
11986 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_11_RSVD_15TO14 register field value. */
11987 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_15TO14_CLR_MSK 0xffff3fff
11988 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_11_RSVD_15TO14 register field. */
11989 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_15TO14_RESET 0x0
11990 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_11_RSVD_15TO14 field value from a register. */
11991 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_15TO14_GET(value) (((value) & 0x0000c000) >> 14)
11992 /* Produces a ALT_PINMUX_DCTD_IO_CFG_11_RSVD_15TO14 register field value suitable for setting the register. */
11993 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_15TO14_SET(value) (((value) << 14) & 0x0000c000)
11994 
11995 /*
11996  * Field : Weak pull up signal - WK_PU_EN
11997  *
11998  * Configuration bit for weak pull up enable
11999  *
12000  * 0 : weak pull up disable
12001  *
12002  * 1 : weak pull up enable
12003  *
12004  * Field Access Macros:
12005  *
12006  */
12007 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_11_WK_PU_EN register field. */
12008 #define ALT_PINMUX_DCTD_IO_CFG_11_WK_PU_EN_LSB 16
12009 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_11_WK_PU_EN register field. */
12010 #define ALT_PINMUX_DCTD_IO_CFG_11_WK_PU_EN_MSB 16
12011 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_11_WK_PU_EN register field. */
12012 #define ALT_PINMUX_DCTD_IO_CFG_11_WK_PU_EN_WIDTH 1
12013 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_11_WK_PU_EN register field value. */
12014 #define ALT_PINMUX_DCTD_IO_CFG_11_WK_PU_EN_SET_MSK 0x00010000
12015 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_11_WK_PU_EN register field value. */
12016 #define ALT_PINMUX_DCTD_IO_CFG_11_WK_PU_EN_CLR_MSK 0xfffeffff
12017 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_11_WK_PU_EN register field. */
12018 #define ALT_PINMUX_DCTD_IO_CFG_11_WK_PU_EN_RESET 0x1
12019 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_11_WK_PU_EN field value from a register. */
12020 #define ALT_PINMUX_DCTD_IO_CFG_11_WK_PU_EN_GET(value) (((value) & 0x00010000) >> 16)
12021 /* Produces a ALT_PINMUX_DCTD_IO_CFG_11_WK_PU_EN register field value suitable for setting the register. */
12022 #define ALT_PINMUX_DCTD_IO_CFG_11_WK_PU_EN_SET(value) (((value) << 16) & 0x00010000)
12023 
12024 /*
12025  * Field : LVTTL input buffer enable signal - INPUT_BUF_EN
12026  *
12027  * Configuration bits for LVTTL input buffer enable
12028  *
12029  * 00 : disable
12030  *
12031  * 01 : 1.8V TTL
12032  *
12033  * 10 : 2.5V/3.0V TTL
12034  *
12035  * 11 : 1.8V TTL
12036  *
12037  * Field Access Macros:
12038  *
12039  */
12040 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_11_INPUT_BUF_EN register field. */
12041 #define ALT_PINMUX_DCTD_IO_CFG_11_INPUT_BUF_EN_LSB 17
12042 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_11_INPUT_BUF_EN register field. */
12043 #define ALT_PINMUX_DCTD_IO_CFG_11_INPUT_BUF_EN_MSB 18
12044 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_11_INPUT_BUF_EN register field. */
12045 #define ALT_PINMUX_DCTD_IO_CFG_11_INPUT_BUF_EN_WIDTH 2
12046 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_11_INPUT_BUF_EN register field value. */
12047 #define ALT_PINMUX_DCTD_IO_CFG_11_INPUT_BUF_EN_SET_MSK 0x00060000
12048 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_11_INPUT_BUF_EN register field value. */
12049 #define ALT_PINMUX_DCTD_IO_CFG_11_INPUT_BUF_EN_CLR_MSK 0xfff9ffff
12050 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_11_INPUT_BUF_EN register field. */
12051 #define ALT_PINMUX_DCTD_IO_CFG_11_INPUT_BUF_EN_RESET 0x2
12052 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_11_INPUT_BUF_EN field value from a register. */
12053 #define ALT_PINMUX_DCTD_IO_CFG_11_INPUT_BUF_EN_GET(value) (((value) & 0x00060000) >> 17)
12054 /* Produces a ALT_PINMUX_DCTD_IO_CFG_11_INPUT_BUF_EN register field value suitable for setting the register. */
12055 #define ALT_PINMUX_DCTD_IO_CFG_11_INPUT_BUF_EN_SET(value) (((value) << 17) & 0x00060000)
12056 
12057 /*
12058  * Field : Bias trim bits - RTRIM
12059  *
12060  * Configuration bits for bias trim
12061  *
12062  * 000 : disable
12063  *
12064  * 001 : default
12065  *
12066  * 010 : trim low
12067  *
12068  * 100 : trim high
12069  *
12070  * others : invalid/reserved
12071  *
12072  * Field Access Macros:
12073  *
12074  */
12075 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_11_RTRIM register field. */
12076 #define ALT_PINMUX_DCTD_IO_CFG_11_RTRIM_LSB 19
12077 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_11_RTRIM register field. */
12078 #define ALT_PINMUX_DCTD_IO_CFG_11_RTRIM_MSB 21
12079 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_11_RTRIM register field. */
12080 #define ALT_PINMUX_DCTD_IO_CFG_11_RTRIM_WIDTH 3
12081 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_11_RTRIM register field value. */
12082 #define ALT_PINMUX_DCTD_IO_CFG_11_RTRIM_SET_MSK 0x00380000
12083 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_11_RTRIM register field value. */
12084 #define ALT_PINMUX_DCTD_IO_CFG_11_RTRIM_CLR_MSK 0xffc7ffff
12085 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_11_RTRIM register field. */
12086 #define ALT_PINMUX_DCTD_IO_CFG_11_RTRIM_RESET 0x1
12087 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_11_RTRIM field value from a register. */
12088 #define ALT_PINMUX_DCTD_IO_CFG_11_RTRIM_GET(value) (((value) & 0x00380000) >> 19)
12089 /* Produces a ALT_PINMUX_DCTD_IO_CFG_11_RTRIM register field value suitable for setting the register. */
12090 #define ALT_PINMUX_DCTD_IO_CFG_11_RTRIM_SET(value) (((value) << 19) & 0x00380000)
12091 
12092 /*
12093  * Field : Reserved_31to22
12094  *
12095  * Reserved
12096  *
12097  * Field Access Macros:
12098  *
12099  */
12100 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_11_RSVD_31TO22 register field. */
12101 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_31TO22_LSB 22
12102 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_11_RSVD_31TO22 register field. */
12103 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_31TO22_MSB 31
12104 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_11_RSVD_31TO22 register field. */
12105 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_31TO22_WIDTH 10
12106 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_11_RSVD_31TO22 register field value. */
12107 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_31TO22_SET_MSK 0xffc00000
12108 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_11_RSVD_31TO22 register field value. */
12109 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_31TO22_CLR_MSK 0x003fffff
12110 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_11_RSVD_31TO22 register field. */
12111 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_31TO22_RESET 0x0
12112 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_11_RSVD_31TO22 field value from a register. */
12113 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_31TO22_GET(value) (((value) & 0xffc00000) >> 22)
12114 /* Produces a ALT_PINMUX_DCTD_IO_CFG_11_RSVD_31TO22 register field value suitable for setting the register. */
12115 #define ALT_PINMUX_DCTD_IO_CFG_11_RSVD_31TO22_SET(value) (((value) << 22) & 0xffc00000)
12116 
12117 #ifndef __ASSEMBLY__
12118 /*
12119  * WARNING: The C register and register group struct declarations are provided for
12120  * convenience and illustrative purposes. They should, however, be used with
12121  * caution as the C language standard provides no guarantees about the alignment or
12122  * atomicity of device memory accesses. The recommended practice for writing
12123  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12124  * alt_write_word() functions.
12125  *
12126  * The struct declaration for register ALT_PINMUX_DCTD_IO_CFG_11.
12127  */
12128 struct ALT_PINMUX_DCTD_IO_CFG_11_s
12129 {
12130  uint32_t PD_DRV_STRG : 5; /* Pull down drive strength */
12131  uint32_t PD_SLW_RT : 1; /* NMOS slew rate */
12132  const uint32_t Reserved_7to6 : 2; /* ALT_PINMUX_DCTD_IO_CFG_11_RSVD_7TO6 */
12133  uint32_t PU_DRV_STRG : 5; /* Pull up drive strength */
12134  uint32_t PU_SLW_RT : 1; /* PMOS slew rate */
12135  const uint32_t Reserved_15to14 : 2; /* ALT_PINMUX_DCTD_IO_CFG_11_RSVD_15TO14 */
12136  uint32_t WK_PU_EN : 1; /* Weak pull up signal */
12137  uint32_t INPUT_BUF_EN : 2; /* LVTTL input buffer enable signal */
12138  uint32_t RTRIM : 3; /* Bias trim bits */
12139  const uint32_t Reserved_31to22 : 10; /* ALT_PINMUX_DCTD_IO_CFG_11_RSVD_31TO22 */
12140 };
12141 
12142 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_CFG_11. */
12143 typedef volatile struct ALT_PINMUX_DCTD_IO_CFG_11_s ALT_PINMUX_DCTD_IO_CFG_11_t;
12144 #endif /* __ASSEMBLY__ */
12145 
12146 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_11 register. */
12147 #define ALT_PINMUX_DCTD_IO_CFG_11_RESET 0x000d0008
12148 /* The byte offset of the ALT_PINMUX_DCTD_IO_CFG_11 register from the beginning of the component. */
12149 #define ALT_PINMUX_DCTD_IO_CFG_11_OFST 0x12c
12150 
12151 /*
12152  * Register : Dedicated IO 12 Configuration Register - configuration_dedicated_io_12
12153  *
12154  * This register is used to control the electrical behavior and direction of
12155  * Dedicated IO 12
12156  *
12157  * Only reset by a cold reset (ignores warm reset).
12158  *
12159  * Register Layout
12160  *
12161  * Bits | Access | Reset | Description
12162  * :--------|:-------|:------|:--------------------------------------
12163  * [4:0] | RW | 0x8 | Pull down drive strength
12164  * [5] | RW | 0x0 | NMOS slew rate
12165  * [7:6] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_12_RSVD_7TO6
12166  * [12:8] | RW | 0x0 | Pull up drive strength
12167  * [13] | RW | 0x0 | PMOS slew rate
12168  * [15:14] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_12_RSVD_15TO14
12169  * [16] | RW | 0x1 | Weak pull up signal
12170  * [18:17] | RW | 0x2 | LVTTL input buffer enable signal
12171  * [21:19] | RW | 0x1 | Bias trim bits
12172  * [31:22] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_12_RSVD_31TO22
12173  *
12174  */
12175 /*
12176  * Field : Pull down drive strength - PD_DRV_STRG
12177  *
12178  * Configuration bits for NMOS pull down drive strength.
12179  *
12180  * Pending Characterization
12181  *
12182  * Field Access Macros:
12183  *
12184  */
12185 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_12_PD_DRV_STRG register field. */
12186 #define ALT_PINMUX_DCTD_IO_CFG_12_PD_DRV_STRG_LSB 0
12187 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_12_PD_DRV_STRG register field. */
12188 #define ALT_PINMUX_DCTD_IO_CFG_12_PD_DRV_STRG_MSB 4
12189 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_12_PD_DRV_STRG register field. */
12190 #define ALT_PINMUX_DCTD_IO_CFG_12_PD_DRV_STRG_WIDTH 5
12191 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_12_PD_DRV_STRG register field value. */
12192 #define ALT_PINMUX_DCTD_IO_CFG_12_PD_DRV_STRG_SET_MSK 0x0000001f
12193 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_12_PD_DRV_STRG register field value. */
12194 #define ALT_PINMUX_DCTD_IO_CFG_12_PD_DRV_STRG_CLR_MSK 0xffffffe0
12195 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_12_PD_DRV_STRG register field. */
12196 #define ALT_PINMUX_DCTD_IO_CFG_12_PD_DRV_STRG_RESET 0x8
12197 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_12_PD_DRV_STRG field value from a register. */
12198 #define ALT_PINMUX_DCTD_IO_CFG_12_PD_DRV_STRG_GET(value) (((value) & 0x0000001f) >> 0)
12199 /* Produces a ALT_PINMUX_DCTD_IO_CFG_12_PD_DRV_STRG register field value suitable for setting the register. */
12200 #define ALT_PINMUX_DCTD_IO_CFG_12_PD_DRV_STRG_SET(value) (((value) << 0) & 0x0000001f)
12201 
12202 /*
12203  * Field : NMOS slew rate - PD_SLW_RT
12204  *
12205  * Configuration bit for output pull down slew rate control
12206  *
12207  * 0 : slow N slew
12208  *
12209  * 1 : fast N slew
12210  *
12211  * Field Access Macros:
12212  *
12213  */
12214 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_12_PD_SLW_RT register field. */
12215 #define ALT_PINMUX_DCTD_IO_CFG_12_PD_SLW_RT_LSB 5
12216 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_12_PD_SLW_RT register field. */
12217 #define ALT_PINMUX_DCTD_IO_CFG_12_PD_SLW_RT_MSB 5
12218 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_12_PD_SLW_RT register field. */
12219 #define ALT_PINMUX_DCTD_IO_CFG_12_PD_SLW_RT_WIDTH 1
12220 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_12_PD_SLW_RT register field value. */
12221 #define ALT_PINMUX_DCTD_IO_CFG_12_PD_SLW_RT_SET_MSK 0x00000020
12222 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_12_PD_SLW_RT register field value. */
12223 #define ALT_PINMUX_DCTD_IO_CFG_12_PD_SLW_RT_CLR_MSK 0xffffffdf
12224 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_12_PD_SLW_RT register field. */
12225 #define ALT_PINMUX_DCTD_IO_CFG_12_PD_SLW_RT_RESET 0x0
12226 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_12_PD_SLW_RT field value from a register. */
12227 #define ALT_PINMUX_DCTD_IO_CFG_12_PD_SLW_RT_GET(value) (((value) & 0x00000020) >> 5)
12228 /* Produces a ALT_PINMUX_DCTD_IO_CFG_12_PD_SLW_RT register field value suitable for setting the register. */
12229 #define ALT_PINMUX_DCTD_IO_CFG_12_PD_SLW_RT_SET(value) (((value) << 5) & 0x00000020)
12230 
12231 /*
12232  * Field : Reserved_7to6
12233  *
12234  * Reserved
12235  *
12236  * Field Access Macros:
12237  *
12238  */
12239 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_12_RSVD_7TO6 register field. */
12240 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_7TO6_LSB 6
12241 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_12_RSVD_7TO6 register field. */
12242 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_7TO6_MSB 7
12243 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_12_RSVD_7TO6 register field. */
12244 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_7TO6_WIDTH 2
12245 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_12_RSVD_7TO6 register field value. */
12246 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_7TO6_SET_MSK 0x000000c0
12247 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_12_RSVD_7TO6 register field value. */
12248 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_7TO6_CLR_MSK 0xffffff3f
12249 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_12_RSVD_7TO6 register field. */
12250 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_7TO6_RESET 0x0
12251 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_12_RSVD_7TO6 field value from a register. */
12252 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_7TO6_GET(value) (((value) & 0x000000c0) >> 6)
12253 /* Produces a ALT_PINMUX_DCTD_IO_CFG_12_RSVD_7TO6 register field value suitable for setting the register. */
12254 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_7TO6_SET(value) (((value) << 6) & 0x000000c0)
12255 
12256 /*
12257  * Field : Pull up drive strength - PU_DRV_STRG
12258  *
12259  * Configuration bits for PMOS pull up drive strength
12260  *
12261  * Pending Characterization
12262  *
12263  * Field Access Macros:
12264  *
12265  */
12266 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_12_PU_DRV_STRG register field. */
12267 #define ALT_PINMUX_DCTD_IO_CFG_12_PU_DRV_STRG_LSB 8
12268 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_12_PU_DRV_STRG register field. */
12269 #define ALT_PINMUX_DCTD_IO_CFG_12_PU_DRV_STRG_MSB 12
12270 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_12_PU_DRV_STRG register field. */
12271 #define ALT_PINMUX_DCTD_IO_CFG_12_PU_DRV_STRG_WIDTH 5
12272 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_12_PU_DRV_STRG register field value. */
12273 #define ALT_PINMUX_DCTD_IO_CFG_12_PU_DRV_STRG_SET_MSK 0x00001f00
12274 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_12_PU_DRV_STRG register field value. */
12275 #define ALT_PINMUX_DCTD_IO_CFG_12_PU_DRV_STRG_CLR_MSK 0xffffe0ff
12276 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_12_PU_DRV_STRG register field. */
12277 #define ALT_PINMUX_DCTD_IO_CFG_12_PU_DRV_STRG_RESET 0x0
12278 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_12_PU_DRV_STRG field value from a register. */
12279 #define ALT_PINMUX_DCTD_IO_CFG_12_PU_DRV_STRG_GET(value) (((value) & 0x00001f00) >> 8)
12280 /* Produces a ALT_PINMUX_DCTD_IO_CFG_12_PU_DRV_STRG register field value suitable for setting the register. */
12281 #define ALT_PINMUX_DCTD_IO_CFG_12_PU_DRV_STRG_SET(value) (((value) << 8) & 0x00001f00)
12282 
12283 /*
12284  * Field : PMOS slew rate - PU_SLW_RT
12285  *
12286  * Configuration bit for output pull up slew rate control
12287  *
12288  * 0 : slow P slew
12289  *
12290  * 1 : fast P slew
12291  *
12292  * Field Access Macros:
12293  *
12294  */
12295 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_12_PU_SLW_RT register field. */
12296 #define ALT_PINMUX_DCTD_IO_CFG_12_PU_SLW_RT_LSB 13
12297 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_12_PU_SLW_RT register field. */
12298 #define ALT_PINMUX_DCTD_IO_CFG_12_PU_SLW_RT_MSB 13
12299 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_12_PU_SLW_RT register field. */
12300 #define ALT_PINMUX_DCTD_IO_CFG_12_PU_SLW_RT_WIDTH 1
12301 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_12_PU_SLW_RT register field value. */
12302 #define ALT_PINMUX_DCTD_IO_CFG_12_PU_SLW_RT_SET_MSK 0x00002000
12303 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_12_PU_SLW_RT register field value. */
12304 #define ALT_PINMUX_DCTD_IO_CFG_12_PU_SLW_RT_CLR_MSK 0xffffdfff
12305 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_12_PU_SLW_RT register field. */
12306 #define ALT_PINMUX_DCTD_IO_CFG_12_PU_SLW_RT_RESET 0x0
12307 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_12_PU_SLW_RT field value from a register. */
12308 #define ALT_PINMUX_DCTD_IO_CFG_12_PU_SLW_RT_GET(value) (((value) & 0x00002000) >> 13)
12309 /* Produces a ALT_PINMUX_DCTD_IO_CFG_12_PU_SLW_RT register field value suitable for setting the register. */
12310 #define ALT_PINMUX_DCTD_IO_CFG_12_PU_SLW_RT_SET(value) (((value) << 13) & 0x00002000)
12311 
12312 /*
12313  * Field : Reserved_15to14
12314  *
12315  * Reserved
12316  *
12317  * Field Access Macros:
12318  *
12319  */
12320 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_12_RSVD_15TO14 register field. */
12321 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_15TO14_LSB 14
12322 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_12_RSVD_15TO14 register field. */
12323 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_15TO14_MSB 15
12324 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_12_RSVD_15TO14 register field. */
12325 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_15TO14_WIDTH 2
12326 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_12_RSVD_15TO14 register field value. */
12327 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_15TO14_SET_MSK 0x0000c000
12328 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_12_RSVD_15TO14 register field value. */
12329 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_15TO14_CLR_MSK 0xffff3fff
12330 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_12_RSVD_15TO14 register field. */
12331 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_15TO14_RESET 0x0
12332 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_12_RSVD_15TO14 field value from a register. */
12333 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_15TO14_GET(value) (((value) & 0x0000c000) >> 14)
12334 /* Produces a ALT_PINMUX_DCTD_IO_CFG_12_RSVD_15TO14 register field value suitable for setting the register. */
12335 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_15TO14_SET(value) (((value) << 14) & 0x0000c000)
12336 
12337 /*
12338  * Field : Weak pull up signal - WK_PU_EN
12339  *
12340  * Configuration bit for weak pull up enable
12341  *
12342  * 0 : weak pull up disable
12343  *
12344  * 1 : weak pull up enable
12345  *
12346  * Field Access Macros:
12347  *
12348  */
12349 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_12_WK_PU_EN register field. */
12350 #define ALT_PINMUX_DCTD_IO_CFG_12_WK_PU_EN_LSB 16
12351 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_12_WK_PU_EN register field. */
12352 #define ALT_PINMUX_DCTD_IO_CFG_12_WK_PU_EN_MSB 16
12353 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_12_WK_PU_EN register field. */
12354 #define ALT_PINMUX_DCTD_IO_CFG_12_WK_PU_EN_WIDTH 1
12355 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_12_WK_PU_EN register field value. */
12356 #define ALT_PINMUX_DCTD_IO_CFG_12_WK_PU_EN_SET_MSK 0x00010000
12357 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_12_WK_PU_EN register field value. */
12358 #define ALT_PINMUX_DCTD_IO_CFG_12_WK_PU_EN_CLR_MSK 0xfffeffff
12359 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_12_WK_PU_EN register field. */
12360 #define ALT_PINMUX_DCTD_IO_CFG_12_WK_PU_EN_RESET 0x1
12361 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_12_WK_PU_EN field value from a register. */
12362 #define ALT_PINMUX_DCTD_IO_CFG_12_WK_PU_EN_GET(value) (((value) & 0x00010000) >> 16)
12363 /* Produces a ALT_PINMUX_DCTD_IO_CFG_12_WK_PU_EN register field value suitable for setting the register. */
12364 #define ALT_PINMUX_DCTD_IO_CFG_12_WK_PU_EN_SET(value) (((value) << 16) & 0x00010000)
12365 
12366 /*
12367  * Field : LVTTL input buffer enable signal - INPUT_BUF_EN
12368  *
12369  * Configuration bits for LVTTL input buffer enable
12370  *
12371  * 00 : disable
12372  *
12373  * 01 : 1.8V TTL
12374  *
12375  * 10 : 2.5V/3.0V TTL
12376  *
12377  * 11 : 1.8V TTL
12378  *
12379  * Field Access Macros:
12380  *
12381  */
12382 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_12_INPUT_BUF_EN register field. */
12383 #define ALT_PINMUX_DCTD_IO_CFG_12_INPUT_BUF_EN_LSB 17
12384 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_12_INPUT_BUF_EN register field. */
12385 #define ALT_PINMUX_DCTD_IO_CFG_12_INPUT_BUF_EN_MSB 18
12386 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_12_INPUT_BUF_EN register field. */
12387 #define ALT_PINMUX_DCTD_IO_CFG_12_INPUT_BUF_EN_WIDTH 2
12388 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_12_INPUT_BUF_EN register field value. */
12389 #define ALT_PINMUX_DCTD_IO_CFG_12_INPUT_BUF_EN_SET_MSK 0x00060000
12390 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_12_INPUT_BUF_EN register field value. */
12391 #define ALT_PINMUX_DCTD_IO_CFG_12_INPUT_BUF_EN_CLR_MSK 0xfff9ffff
12392 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_12_INPUT_BUF_EN register field. */
12393 #define ALT_PINMUX_DCTD_IO_CFG_12_INPUT_BUF_EN_RESET 0x2
12394 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_12_INPUT_BUF_EN field value from a register. */
12395 #define ALT_PINMUX_DCTD_IO_CFG_12_INPUT_BUF_EN_GET(value) (((value) & 0x00060000) >> 17)
12396 /* Produces a ALT_PINMUX_DCTD_IO_CFG_12_INPUT_BUF_EN register field value suitable for setting the register. */
12397 #define ALT_PINMUX_DCTD_IO_CFG_12_INPUT_BUF_EN_SET(value) (((value) << 17) & 0x00060000)
12398 
12399 /*
12400  * Field : Bias trim bits - RTRIM
12401  *
12402  * Configuration bits for bias trim
12403  *
12404  * 000 : disable
12405  *
12406  * 001 : default
12407  *
12408  * 010 : trim low
12409  *
12410  * 100 : trim high
12411  *
12412  * others : invalid/reserved
12413  *
12414  * Field Access Macros:
12415  *
12416  */
12417 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_12_RTRIM register field. */
12418 #define ALT_PINMUX_DCTD_IO_CFG_12_RTRIM_LSB 19
12419 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_12_RTRIM register field. */
12420 #define ALT_PINMUX_DCTD_IO_CFG_12_RTRIM_MSB 21
12421 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_12_RTRIM register field. */
12422 #define ALT_PINMUX_DCTD_IO_CFG_12_RTRIM_WIDTH 3
12423 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_12_RTRIM register field value. */
12424 #define ALT_PINMUX_DCTD_IO_CFG_12_RTRIM_SET_MSK 0x00380000
12425 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_12_RTRIM register field value. */
12426 #define ALT_PINMUX_DCTD_IO_CFG_12_RTRIM_CLR_MSK 0xffc7ffff
12427 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_12_RTRIM register field. */
12428 #define ALT_PINMUX_DCTD_IO_CFG_12_RTRIM_RESET 0x1
12429 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_12_RTRIM field value from a register. */
12430 #define ALT_PINMUX_DCTD_IO_CFG_12_RTRIM_GET(value) (((value) & 0x00380000) >> 19)
12431 /* Produces a ALT_PINMUX_DCTD_IO_CFG_12_RTRIM register field value suitable for setting the register. */
12432 #define ALT_PINMUX_DCTD_IO_CFG_12_RTRIM_SET(value) (((value) << 19) & 0x00380000)
12433 
12434 /*
12435  * Field : Reserved_31to22
12436  *
12437  * Reserved
12438  *
12439  * Field Access Macros:
12440  *
12441  */
12442 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_12_RSVD_31TO22 register field. */
12443 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_31TO22_LSB 22
12444 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_12_RSVD_31TO22 register field. */
12445 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_31TO22_MSB 31
12446 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_12_RSVD_31TO22 register field. */
12447 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_31TO22_WIDTH 10
12448 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_12_RSVD_31TO22 register field value. */
12449 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_31TO22_SET_MSK 0xffc00000
12450 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_12_RSVD_31TO22 register field value. */
12451 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_31TO22_CLR_MSK 0x003fffff
12452 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_12_RSVD_31TO22 register field. */
12453 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_31TO22_RESET 0x0
12454 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_12_RSVD_31TO22 field value from a register. */
12455 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_31TO22_GET(value) (((value) & 0xffc00000) >> 22)
12456 /* Produces a ALT_PINMUX_DCTD_IO_CFG_12_RSVD_31TO22 register field value suitable for setting the register. */
12457 #define ALT_PINMUX_DCTD_IO_CFG_12_RSVD_31TO22_SET(value) (((value) << 22) & 0xffc00000)
12458 
12459 #ifndef __ASSEMBLY__
12460 /*
12461  * WARNING: The C register and register group struct declarations are provided for
12462  * convenience and illustrative purposes. They should, however, be used with
12463  * caution as the C language standard provides no guarantees about the alignment or
12464  * atomicity of device memory accesses. The recommended practice for writing
12465  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12466  * alt_write_word() functions.
12467  *
12468  * The struct declaration for register ALT_PINMUX_DCTD_IO_CFG_12.
12469  */
12470 struct ALT_PINMUX_DCTD_IO_CFG_12_s
12471 {
12472  uint32_t PD_DRV_STRG : 5; /* Pull down drive strength */
12473  uint32_t PD_SLW_RT : 1; /* NMOS slew rate */
12474  const uint32_t Reserved_7to6 : 2; /* ALT_PINMUX_DCTD_IO_CFG_12_RSVD_7TO6 */
12475  uint32_t PU_DRV_STRG : 5; /* Pull up drive strength */
12476  uint32_t PU_SLW_RT : 1; /* PMOS slew rate */
12477  const uint32_t Reserved_15to14 : 2; /* ALT_PINMUX_DCTD_IO_CFG_12_RSVD_15TO14 */
12478  uint32_t WK_PU_EN : 1; /* Weak pull up signal */
12479  uint32_t INPUT_BUF_EN : 2; /* LVTTL input buffer enable signal */
12480  uint32_t RTRIM : 3; /* Bias trim bits */
12481  const uint32_t Reserved_31to22 : 10; /* ALT_PINMUX_DCTD_IO_CFG_12_RSVD_31TO22 */
12482 };
12483 
12484 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_CFG_12. */
12485 typedef volatile struct ALT_PINMUX_DCTD_IO_CFG_12_s ALT_PINMUX_DCTD_IO_CFG_12_t;
12486 #endif /* __ASSEMBLY__ */
12487 
12488 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_12 register. */
12489 #define ALT_PINMUX_DCTD_IO_CFG_12_RESET 0x000d0008
12490 /* The byte offset of the ALT_PINMUX_DCTD_IO_CFG_12 register from the beginning of the component. */
12491 #define ALT_PINMUX_DCTD_IO_CFG_12_OFST 0x130
12492 
12493 /*
12494  * Register : Dedicated IO 13 Configuration Register - configuration_dedicated_io_13
12495  *
12496  * This register is used to control the electrical behavior and direction of
12497  * Dedicated IO 13
12498  *
12499  * Only reset by a cold reset (ignores warm reset).
12500  *
12501  * Register Layout
12502  *
12503  * Bits | Access | Reset | Description
12504  * :--------|:-------|:------|:--------------------------------------
12505  * [4:0] | RW | 0x8 | Pull down drive strength
12506  * [5] | RW | 0x0 | NMOS slew rate
12507  * [7:6] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_13_RSVD_7TO6
12508  * [12:8] | RW | 0x0 | Pull up drive strength
12509  * [13] | RW | 0x0 | PMOS slew rate
12510  * [15:14] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_13_RSVD_15TO14
12511  * [16] | RW | 0x1 | Weak pull up signal
12512  * [18:17] | RW | 0x2 | LVTTL input buffer enable signal
12513  * [21:19] | RW | 0x1 | Bias trim bits
12514  * [31:22] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_13_RSVD_31TO22
12515  *
12516  */
12517 /*
12518  * Field : Pull down drive strength - PD_DRV_STRG
12519  *
12520  * Configuration bits for NMOS pull down drive strength.
12521  *
12522  * Pending Characterization
12523  *
12524  * Field Access Macros:
12525  *
12526  */
12527 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_13_PD_DRV_STRG register field. */
12528 #define ALT_PINMUX_DCTD_IO_CFG_13_PD_DRV_STRG_LSB 0
12529 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_13_PD_DRV_STRG register field. */
12530 #define ALT_PINMUX_DCTD_IO_CFG_13_PD_DRV_STRG_MSB 4
12531 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_13_PD_DRV_STRG register field. */
12532 #define ALT_PINMUX_DCTD_IO_CFG_13_PD_DRV_STRG_WIDTH 5
12533 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_13_PD_DRV_STRG register field value. */
12534 #define ALT_PINMUX_DCTD_IO_CFG_13_PD_DRV_STRG_SET_MSK 0x0000001f
12535 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_13_PD_DRV_STRG register field value. */
12536 #define ALT_PINMUX_DCTD_IO_CFG_13_PD_DRV_STRG_CLR_MSK 0xffffffe0
12537 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_13_PD_DRV_STRG register field. */
12538 #define ALT_PINMUX_DCTD_IO_CFG_13_PD_DRV_STRG_RESET 0x8
12539 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_13_PD_DRV_STRG field value from a register. */
12540 #define ALT_PINMUX_DCTD_IO_CFG_13_PD_DRV_STRG_GET(value) (((value) & 0x0000001f) >> 0)
12541 /* Produces a ALT_PINMUX_DCTD_IO_CFG_13_PD_DRV_STRG register field value suitable for setting the register. */
12542 #define ALT_PINMUX_DCTD_IO_CFG_13_PD_DRV_STRG_SET(value) (((value) << 0) & 0x0000001f)
12543 
12544 /*
12545  * Field : NMOS slew rate - PD_SLW_RT
12546  *
12547  * Configuration bit for output pull down slew rate control
12548  *
12549  * 0 : slow N slew
12550  *
12551  * 1 : fast N slew
12552  *
12553  * Field Access Macros:
12554  *
12555  */
12556 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_13_PD_SLW_RT register field. */
12557 #define ALT_PINMUX_DCTD_IO_CFG_13_PD_SLW_RT_LSB 5
12558 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_13_PD_SLW_RT register field. */
12559 #define ALT_PINMUX_DCTD_IO_CFG_13_PD_SLW_RT_MSB 5
12560 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_13_PD_SLW_RT register field. */
12561 #define ALT_PINMUX_DCTD_IO_CFG_13_PD_SLW_RT_WIDTH 1
12562 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_13_PD_SLW_RT register field value. */
12563 #define ALT_PINMUX_DCTD_IO_CFG_13_PD_SLW_RT_SET_MSK 0x00000020
12564 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_13_PD_SLW_RT register field value. */
12565 #define ALT_PINMUX_DCTD_IO_CFG_13_PD_SLW_RT_CLR_MSK 0xffffffdf
12566 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_13_PD_SLW_RT register field. */
12567 #define ALT_PINMUX_DCTD_IO_CFG_13_PD_SLW_RT_RESET 0x0
12568 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_13_PD_SLW_RT field value from a register. */
12569 #define ALT_PINMUX_DCTD_IO_CFG_13_PD_SLW_RT_GET(value) (((value) & 0x00000020) >> 5)
12570 /* Produces a ALT_PINMUX_DCTD_IO_CFG_13_PD_SLW_RT register field value suitable for setting the register. */
12571 #define ALT_PINMUX_DCTD_IO_CFG_13_PD_SLW_RT_SET(value) (((value) << 5) & 0x00000020)
12572 
12573 /*
12574  * Field : Reserved_7to6
12575  *
12576  * Reserved
12577  *
12578  * Field Access Macros:
12579  *
12580  */
12581 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_13_RSVD_7TO6 register field. */
12582 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_7TO6_LSB 6
12583 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_13_RSVD_7TO6 register field. */
12584 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_7TO6_MSB 7
12585 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_13_RSVD_7TO6 register field. */
12586 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_7TO6_WIDTH 2
12587 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_13_RSVD_7TO6 register field value. */
12588 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_7TO6_SET_MSK 0x000000c0
12589 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_13_RSVD_7TO6 register field value. */
12590 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_7TO6_CLR_MSK 0xffffff3f
12591 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_13_RSVD_7TO6 register field. */
12592 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_7TO6_RESET 0x0
12593 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_13_RSVD_7TO6 field value from a register. */
12594 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_7TO6_GET(value) (((value) & 0x000000c0) >> 6)
12595 /* Produces a ALT_PINMUX_DCTD_IO_CFG_13_RSVD_7TO6 register field value suitable for setting the register. */
12596 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_7TO6_SET(value) (((value) << 6) & 0x000000c0)
12597 
12598 /*
12599  * Field : Pull up drive strength - PU_DRV_STRG
12600  *
12601  * Configuration bits for PMOS pull up drive strength
12602  *
12603  * Pending Characterization
12604  *
12605  * Field Access Macros:
12606  *
12607  */
12608 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_13_PU_DRV_STRG register field. */
12609 #define ALT_PINMUX_DCTD_IO_CFG_13_PU_DRV_STRG_LSB 8
12610 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_13_PU_DRV_STRG register field. */
12611 #define ALT_PINMUX_DCTD_IO_CFG_13_PU_DRV_STRG_MSB 12
12612 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_13_PU_DRV_STRG register field. */
12613 #define ALT_PINMUX_DCTD_IO_CFG_13_PU_DRV_STRG_WIDTH 5
12614 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_13_PU_DRV_STRG register field value. */
12615 #define ALT_PINMUX_DCTD_IO_CFG_13_PU_DRV_STRG_SET_MSK 0x00001f00
12616 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_13_PU_DRV_STRG register field value. */
12617 #define ALT_PINMUX_DCTD_IO_CFG_13_PU_DRV_STRG_CLR_MSK 0xffffe0ff
12618 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_13_PU_DRV_STRG register field. */
12619 #define ALT_PINMUX_DCTD_IO_CFG_13_PU_DRV_STRG_RESET 0x0
12620 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_13_PU_DRV_STRG field value from a register. */
12621 #define ALT_PINMUX_DCTD_IO_CFG_13_PU_DRV_STRG_GET(value) (((value) & 0x00001f00) >> 8)
12622 /* Produces a ALT_PINMUX_DCTD_IO_CFG_13_PU_DRV_STRG register field value suitable for setting the register. */
12623 #define ALT_PINMUX_DCTD_IO_CFG_13_PU_DRV_STRG_SET(value) (((value) << 8) & 0x00001f00)
12624 
12625 /*
12626  * Field : PMOS slew rate - PU_SLW_RT
12627  *
12628  * Configuration bit for output pull up slew rate control
12629  *
12630  * 0 : slow P slew
12631  *
12632  * 1 : fast P slew
12633  *
12634  * Field Access Macros:
12635  *
12636  */
12637 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_13_PU_SLW_RT register field. */
12638 #define ALT_PINMUX_DCTD_IO_CFG_13_PU_SLW_RT_LSB 13
12639 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_13_PU_SLW_RT register field. */
12640 #define ALT_PINMUX_DCTD_IO_CFG_13_PU_SLW_RT_MSB 13
12641 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_13_PU_SLW_RT register field. */
12642 #define ALT_PINMUX_DCTD_IO_CFG_13_PU_SLW_RT_WIDTH 1
12643 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_13_PU_SLW_RT register field value. */
12644 #define ALT_PINMUX_DCTD_IO_CFG_13_PU_SLW_RT_SET_MSK 0x00002000
12645 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_13_PU_SLW_RT register field value. */
12646 #define ALT_PINMUX_DCTD_IO_CFG_13_PU_SLW_RT_CLR_MSK 0xffffdfff
12647 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_13_PU_SLW_RT register field. */
12648 #define ALT_PINMUX_DCTD_IO_CFG_13_PU_SLW_RT_RESET 0x0
12649 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_13_PU_SLW_RT field value from a register. */
12650 #define ALT_PINMUX_DCTD_IO_CFG_13_PU_SLW_RT_GET(value) (((value) & 0x00002000) >> 13)
12651 /* Produces a ALT_PINMUX_DCTD_IO_CFG_13_PU_SLW_RT register field value suitable for setting the register. */
12652 #define ALT_PINMUX_DCTD_IO_CFG_13_PU_SLW_RT_SET(value) (((value) << 13) & 0x00002000)
12653 
12654 /*
12655  * Field : Reserved_15to14
12656  *
12657  * Reserved
12658  *
12659  * Field Access Macros:
12660  *
12661  */
12662 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_13_RSVD_15TO14 register field. */
12663 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_15TO14_LSB 14
12664 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_13_RSVD_15TO14 register field. */
12665 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_15TO14_MSB 15
12666 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_13_RSVD_15TO14 register field. */
12667 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_15TO14_WIDTH 2
12668 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_13_RSVD_15TO14 register field value. */
12669 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_15TO14_SET_MSK 0x0000c000
12670 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_13_RSVD_15TO14 register field value. */
12671 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_15TO14_CLR_MSK 0xffff3fff
12672 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_13_RSVD_15TO14 register field. */
12673 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_15TO14_RESET 0x0
12674 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_13_RSVD_15TO14 field value from a register. */
12675 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_15TO14_GET(value) (((value) & 0x0000c000) >> 14)
12676 /* Produces a ALT_PINMUX_DCTD_IO_CFG_13_RSVD_15TO14 register field value suitable for setting the register. */
12677 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_15TO14_SET(value) (((value) << 14) & 0x0000c000)
12678 
12679 /*
12680  * Field : Weak pull up signal - WK_PU_EN
12681  *
12682  * Configuration bit for weak pull up enable
12683  *
12684  * 0 : weak pull up disable
12685  *
12686  * 1 : weak pull up enable
12687  *
12688  * Field Access Macros:
12689  *
12690  */
12691 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_13_WK_PU_EN register field. */
12692 #define ALT_PINMUX_DCTD_IO_CFG_13_WK_PU_EN_LSB 16
12693 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_13_WK_PU_EN register field. */
12694 #define ALT_PINMUX_DCTD_IO_CFG_13_WK_PU_EN_MSB 16
12695 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_13_WK_PU_EN register field. */
12696 #define ALT_PINMUX_DCTD_IO_CFG_13_WK_PU_EN_WIDTH 1
12697 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_13_WK_PU_EN register field value. */
12698 #define ALT_PINMUX_DCTD_IO_CFG_13_WK_PU_EN_SET_MSK 0x00010000
12699 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_13_WK_PU_EN register field value. */
12700 #define ALT_PINMUX_DCTD_IO_CFG_13_WK_PU_EN_CLR_MSK 0xfffeffff
12701 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_13_WK_PU_EN register field. */
12702 #define ALT_PINMUX_DCTD_IO_CFG_13_WK_PU_EN_RESET 0x1
12703 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_13_WK_PU_EN field value from a register. */
12704 #define ALT_PINMUX_DCTD_IO_CFG_13_WK_PU_EN_GET(value) (((value) & 0x00010000) >> 16)
12705 /* Produces a ALT_PINMUX_DCTD_IO_CFG_13_WK_PU_EN register field value suitable for setting the register. */
12706 #define ALT_PINMUX_DCTD_IO_CFG_13_WK_PU_EN_SET(value) (((value) << 16) & 0x00010000)
12707 
12708 /*
12709  * Field : LVTTL input buffer enable signal - INPUT_BUF_EN
12710  *
12711  * Configuration bits for LVTTL input buffer enable
12712  *
12713  * 00 : disable
12714  *
12715  * 01 : 1.8V TTL
12716  *
12717  * 10 : 2.5V/3.0V TTL
12718  *
12719  * 11 : 1.8V TTL
12720  *
12721  * Field Access Macros:
12722  *
12723  */
12724 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_13_INPUT_BUF_EN register field. */
12725 #define ALT_PINMUX_DCTD_IO_CFG_13_INPUT_BUF_EN_LSB 17
12726 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_13_INPUT_BUF_EN register field. */
12727 #define ALT_PINMUX_DCTD_IO_CFG_13_INPUT_BUF_EN_MSB 18
12728 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_13_INPUT_BUF_EN register field. */
12729 #define ALT_PINMUX_DCTD_IO_CFG_13_INPUT_BUF_EN_WIDTH 2
12730 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_13_INPUT_BUF_EN register field value. */
12731 #define ALT_PINMUX_DCTD_IO_CFG_13_INPUT_BUF_EN_SET_MSK 0x00060000
12732 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_13_INPUT_BUF_EN register field value. */
12733 #define ALT_PINMUX_DCTD_IO_CFG_13_INPUT_BUF_EN_CLR_MSK 0xfff9ffff
12734 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_13_INPUT_BUF_EN register field. */
12735 #define ALT_PINMUX_DCTD_IO_CFG_13_INPUT_BUF_EN_RESET 0x2
12736 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_13_INPUT_BUF_EN field value from a register. */
12737 #define ALT_PINMUX_DCTD_IO_CFG_13_INPUT_BUF_EN_GET(value) (((value) & 0x00060000) >> 17)
12738 /* Produces a ALT_PINMUX_DCTD_IO_CFG_13_INPUT_BUF_EN register field value suitable for setting the register. */
12739 #define ALT_PINMUX_DCTD_IO_CFG_13_INPUT_BUF_EN_SET(value) (((value) << 17) & 0x00060000)
12740 
12741 /*
12742  * Field : Bias trim bits - RTRIM
12743  *
12744  * Configuration bits for bias trim
12745  *
12746  * 000 : disable
12747  *
12748  * 001 : default
12749  *
12750  * 010 : trim low
12751  *
12752  * 100 : trim high
12753  *
12754  * others : invalid/reserved
12755  *
12756  * Field Access Macros:
12757  *
12758  */
12759 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_13_RTRIM register field. */
12760 #define ALT_PINMUX_DCTD_IO_CFG_13_RTRIM_LSB 19
12761 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_13_RTRIM register field. */
12762 #define ALT_PINMUX_DCTD_IO_CFG_13_RTRIM_MSB 21
12763 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_13_RTRIM register field. */
12764 #define ALT_PINMUX_DCTD_IO_CFG_13_RTRIM_WIDTH 3
12765 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_13_RTRIM register field value. */
12766 #define ALT_PINMUX_DCTD_IO_CFG_13_RTRIM_SET_MSK 0x00380000
12767 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_13_RTRIM register field value. */
12768 #define ALT_PINMUX_DCTD_IO_CFG_13_RTRIM_CLR_MSK 0xffc7ffff
12769 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_13_RTRIM register field. */
12770 #define ALT_PINMUX_DCTD_IO_CFG_13_RTRIM_RESET 0x1
12771 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_13_RTRIM field value from a register. */
12772 #define ALT_PINMUX_DCTD_IO_CFG_13_RTRIM_GET(value) (((value) & 0x00380000) >> 19)
12773 /* Produces a ALT_PINMUX_DCTD_IO_CFG_13_RTRIM register field value suitable for setting the register. */
12774 #define ALT_PINMUX_DCTD_IO_CFG_13_RTRIM_SET(value) (((value) << 19) & 0x00380000)
12775 
12776 /*
12777  * Field : Reserved_31to22
12778  *
12779  * Reserved
12780  *
12781  * Field Access Macros:
12782  *
12783  */
12784 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_13_RSVD_31TO22 register field. */
12785 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_31TO22_LSB 22
12786 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_13_RSVD_31TO22 register field. */
12787 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_31TO22_MSB 31
12788 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_13_RSVD_31TO22 register field. */
12789 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_31TO22_WIDTH 10
12790 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_13_RSVD_31TO22 register field value. */
12791 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_31TO22_SET_MSK 0xffc00000
12792 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_13_RSVD_31TO22 register field value. */
12793 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_31TO22_CLR_MSK 0x003fffff
12794 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_13_RSVD_31TO22 register field. */
12795 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_31TO22_RESET 0x0
12796 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_13_RSVD_31TO22 field value from a register. */
12797 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_31TO22_GET(value) (((value) & 0xffc00000) >> 22)
12798 /* Produces a ALT_PINMUX_DCTD_IO_CFG_13_RSVD_31TO22 register field value suitable for setting the register. */
12799 #define ALT_PINMUX_DCTD_IO_CFG_13_RSVD_31TO22_SET(value) (((value) << 22) & 0xffc00000)
12800 
12801 #ifndef __ASSEMBLY__
12802 /*
12803  * WARNING: The C register and register group struct declarations are provided for
12804  * convenience and illustrative purposes. They should, however, be used with
12805  * caution as the C language standard provides no guarantees about the alignment or
12806  * atomicity of device memory accesses. The recommended practice for writing
12807  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12808  * alt_write_word() functions.
12809  *
12810  * The struct declaration for register ALT_PINMUX_DCTD_IO_CFG_13.
12811  */
12812 struct ALT_PINMUX_DCTD_IO_CFG_13_s
12813 {
12814  uint32_t PD_DRV_STRG : 5; /* Pull down drive strength */
12815  uint32_t PD_SLW_RT : 1; /* NMOS slew rate */
12816  const uint32_t Reserved_7to6 : 2; /* ALT_PINMUX_DCTD_IO_CFG_13_RSVD_7TO6 */
12817  uint32_t PU_DRV_STRG : 5; /* Pull up drive strength */
12818  uint32_t PU_SLW_RT : 1; /* PMOS slew rate */
12819  const uint32_t Reserved_15to14 : 2; /* ALT_PINMUX_DCTD_IO_CFG_13_RSVD_15TO14 */
12820  uint32_t WK_PU_EN : 1; /* Weak pull up signal */
12821  uint32_t INPUT_BUF_EN : 2; /* LVTTL input buffer enable signal */
12822  uint32_t RTRIM : 3; /* Bias trim bits */
12823  const uint32_t Reserved_31to22 : 10; /* ALT_PINMUX_DCTD_IO_CFG_13_RSVD_31TO22 */
12824 };
12825 
12826 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_CFG_13. */
12827 typedef volatile struct ALT_PINMUX_DCTD_IO_CFG_13_s ALT_PINMUX_DCTD_IO_CFG_13_t;
12828 #endif /* __ASSEMBLY__ */
12829 
12830 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_13 register. */
12831 #define ALT_PINMUX_DCTD_IO_CFG_13_RESET 0x000d0008
12832 /* The byte offset of the ALT_PINMUX_DCTD_IO_CFG_13 register from the beginning of the component. */
12833 #define ALT_PINMUX_DCTD_IO_CFG_13_OFST 0x134
12834 
12835 /*
12836  * Register : Dedicated IO 14 Configuration Register - configuration_dedicated_io_14
12837  *
12838  * This register is used to control the electrical behavior and direction of
12839  * Dedicated IO 14
12840  *
12841  * Only reset by a cold reset (ignores warm reset).
12842  *
12843  * Register Layout
12844  *
12845  * Bits | Access | Reset | Description
12846  * :--------|:-------|:------|:--------------------------------------
12847  * [4:0] | RW | 0x8 | Pull down drive strength
12848  * [5] | RW | 0x0 | NMOS slew rate
12849  * [7:6] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_14_RSVD_7TO6
12850  * [12:8] | RW | 0x0 | Pull up drive strength
12851  * [13] | RW | 0x0 | PMOS slew rate
12852  * [15:14] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_14_RSVD_15TO14
12853  * [16] | RW | 0x1 | Weak pull up signal
12854  * [18:17] | RW | 0x2 | LVTTL input buffer enable signal
12855  * [21:19] | RW | 0x1 | Bias trim bits
12856  * [31:22] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_14_RSVD_31TO22
12857  *
12858  */
12859 /*
12860  * Field : Pull down drive strength - PD_DRV_STRG
12861  *
12862  * Configuration bits for NMOS pull down drive strength.
12863  *
12864  * Pending Characterization
12865  *
12866  * Field Access Macros:
12867  *
12868  */
12869 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_14_PD_DRV_STRG register field. */
12870 #define ALT_PINMUX_DCTD_IO_CFG_14_PD_DRV_STRG_LSB 0
12871 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_14_PD_DRV_STRG register field. */
12872 #define ALT_PINMUX_DCTD_IO_CFG_14_PD_DRV_STRG_MSB 4
12873 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_14_PD_DRV_STRG register field. */
12874 #define ALT_PINMUX_DCTD_IO_CFG_14_PD_DRV_STRG_WIDTH 5
12875 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_14_PD_DRV_STRG register field value. */
12876 #define ALT_PINMUX_DCTD_IO_CFG_14_PD_DRV_STRG_SET_MSK 0x0000001f
12877 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_14_PD_DRV_STRG register field value. */
12878 #define ALT_PINMUX_DCTD_IO_CFG_14_PD_DRV_STRG_CLR_MSK 0xffffffe0
12879 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_14_PD_DRV_STRG register field. */
12880 #define ALT_PINMUX_DCTD_IO_CFG_14_PD_DRV_STRG_RESET 0x8
12881 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_14_PD_DRV_STRG field value from a register. */
12882 #define ALT_PINMUX_DCTD_IO_CFG_14_PD_DRV_STRG_GET(value) (((value) & 0x0000001f) >> 0)
12883 /* Produces a ALT_PINMUX_DCTD_IO_CFG_14_PD_DRV_STRG register field value suitable for setting the register. */
12884 #define ALT_PINMUX_DCTD_IO_CFG_14_PD_DRV_STRG_SET(value) (((value) << 0) & 0x0000001f)
12885 
12886 /*
12887  * Field : NMOS slew rate - PD_SLW_RT
12888  *
12889  * Configuration bit for output pull down slew rate control
12890  *
12891  * 0 : slow N slew
12892  *
12893  * 1 : fast N slew
12894  *
12895  * Field Access Macros:
12896  *
12897  */
12898 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_14_PD_SLW_RT register field. */
12899 #define ALT_PINMUX_DCTD_IO_CFG_14_PD_SLW_RT_LSB 5
12900 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_14_PD_SLW_RT register field. */
12901 #define ALT_PINMUX_DCTD_IO_CFG_14_PD_SLW_RT_MSB 5
12902 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_14_PD_SLW_RT register field. */
12903 #define ALT_PINMUX_DCTD_IO_CFG_14_PD_SLW_RT_WIDTH 1
12904 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_14_PD_SLW_RT register field value. */
12905 #define ALT_PINMUX_DCTD_IO_CFG_14_PD_SLW_RT_SET_MSK 0x00000020
12906 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_14_PD_SLW_RT register field value. */
12907 #define ALT_PINMUX_DCTD_IO_CFG_14_PD_SLW_RT_CLR_MSK 0xffffffdf
12908 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_14_PD_SLW_RT register field. */
12909 #define ALT_PINMUX_DCTD_IO_CFG_14_PD_SLW_RT_RESET 0x0
12910 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_14_PD_SLW_RT field value from a register. */
12911 #define ALT_PINMUX_DCTD_IO_CFG_14_PD_SLW_RT_GET(value) (((value) & 0x00000020) >> 5)
12912 /* Produces a ALT_PINMUX_DCTD_IO_CFG_14_PD_SLW_RT register field value suitable for setting the register. */
12913 #define ALT_PINMUX_DCTD_IO_CFG_14_PD_SLW_RT_SET(value) (((value) << 5) & 0x00000020)
12914 
12915 /*
12916  * Field : Reserved_7to6
12917  *
12918  * Reserved
12919  *
12920  * Field Access Macros:
12921  *
12922  */
12923 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_14_RSVD_7TO6 register field. */
12924 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_7TO6_LSB 6
12925 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_14_RSVD_7TO6 register field. */
12926 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_7TO6_MSB 7
12927 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_14_RSVD_7TO6 register field. */
12928 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_7TO6_WIDTH 2
12929 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_14_RSVD_7TO6 register field value. */
12930 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_7TO6_SET_MSK 0x000000c0
12931 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_14_RSVD_7TO6 register field value. */
12932 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_7TO6_CLR_MSK 0xffffff3f
12933 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_14_RSVD_7TO6 register field. */
12934 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_7TO6_RESET 0x0
12935 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_14_RSVD_7TO6 field value from a register. */
12936 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_7TO6_GET(value) (((value) & 0x000000c0) >> 6)
12937 /* Produces a ALT_PINMUX_DCTD_IO_CFG_14_RSVD_7TO6 register field value suitable for setting the register. */
12938 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_7TO6_SET(value) (((value) << 6) & 0x000000c0)
12939 
12940 /*
12941  * Field : Pull up drive strength - PU_DRV_STRG
12942  *
12943  * Configuration bits for PMOS pull up drive strength
12944  *
12945  * Pending Characterization
12946  *
12947  * Field Access Macros:
12948  *
12949  */
12950 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_14_PU_DRV_STRG register field. */
12951 #define ALT_PINMUX_DCTD_IO_CFG_14_PU_DRV_STRG_LSB 8
12952 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_14_PU_DRV_STRG register field. */
12953 #define ALT_PINMUX_DCTD_IO_CFG_14_PU_DRV_STRG_MSB 12
12954 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_14_PU_DRV_STRG register field. */
12955 #define ALT_PINMUX_DCTD_IO_CFG_14_PU_DRV_STRG_WIDTH 5
12956 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_14_PU_DRV_STRG register field value. */
12957 #define ALT_PINMUX_DCTD_IO_CFG_14_PU_DRV_STRG_SET_MSK 0x00001f00
12958 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_14_PU_DRV_STRG register field value. */
12959 #define ALT_PINMUX_DCTD_IO_CFG_14_PU_DRV_STRG_CLR_MSK 0xffffe0ff
12960 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_14_PU_DRV_STRG register field. */
12961 #define ALT_PINMUX_DCTD_IO_CFG_14_PU_DRV_STRG_RESET 0x0
12962 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_14_PU_DRV_STRG field value from a register. */
12963 #define ALT_PINMUX_DCTD_IO_CFG_14_PU_DRV_STRG_GET(value) (((value) & 0x00001f00) >> 8)
12964 /* Produces a ALT_PINMUX_DCTD_IO_CFG_14_PU_DRV_STRG register field value suitable for setting the register. */
12965 #define ALT_PINMUX_DCTD_IO_CFG_14_PU_DRV_STRG_SET(value) (((value) << 8) & 0x00001f00)
12966 
12967 /*
12968  * Field : PMOS slew rate - PU_SLW_RT
12969  *
12970  * Configuration bit for output pull up slew rate control
12971  *
12972  * 0 : slow P slew
12973  *
12974  * 1 : fast P slew
12975  *
12976  * Field Access Macros:
12977  *
12978  */
12979 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_14_PU_SLW_RT register field. */
12980 #define ALT_PINMUX_DCTD_IO_CFG_14_PU_SLW_RT_LSB 13
12981 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_14_PU_SLW_RT register field. */
12982 #define ALT_PINMUX_DCTD_IO_CFG_14_PU_SLW_RT_MSB 13
12983 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_14_PU_SLW_RT register field. */
12984 #define ALT_PINMUX_DCTD_IO_CFG_14_PU_SLW_RT_WIDTH 1
12985 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_14_PU_SLW_RT register field value. */
12986 #define ALT_PINMUX_DCTD_IO_CFG_14_PU_SLW_RT_SET_MSK 0x00002000
12987 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_14_PU_SLW_RT register field value. */
12988 #define ALT_PINMUX_DCTD_IO_CFG_14_PU_SLW_RT_CLR_MSK 0xffffdfff
12989 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_14_PU_SLW_RT register field. */
12990 #define ALT_PINMUX_DCTD_IO_CFG_14_PU_SLW_RT_RESET 0x0
12991 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_14_PU_SLW_RT field value from a register. */
12992 #define ALT_PINMUX_DCTD_IO_CFG_14_PU_SLW_RT_GET(value) (((value) & 0x00002000) >> 13)
12993 /* Produces a ALT_PINMUX_DCTD_IO_CFG_14_PU_SLW_RT register field value suitable for setting the register. */
12994 #define ALT_PINMUX_DCTD_IO_CFG_14_PU_SLW_RT_SET(value) (((value) << 13) & 0x00002000)
12995 
12996 /*
12997  * Field : Reserved_15to14
12998  *
12999  * Reserved
13000  *
13001  * Field Access Macros:
13002  *
13003  */
13004 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_14_RSVD_15TO14 register field. */
13005 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_15TO14_LSB 14
13006 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_14_RSVD_15TO14 register field. */
13007 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_15TO14_MSB 15
13008 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_14_RSVD_15TO14 register field. */
13009 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_15TO14_WIDTH 2
13010 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_14_RSVD_15TO14 register field value. */
13011 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_15TO14_SET_MSK 0x0000c000
13012 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_14_RSVD_15TO14 register field value. */
13013 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_15TO14_CLR_MSK 0xffff3fff
13014 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_14_RSVD_15TO14 register field. */
13015 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_15TO14_RESET 0x0
13016 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_14_RSVD_15TO14 field value from a register. */
13017 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_15TO14_GET(value) (((value) & 0x0000c000) >> 14)
13018 /* Produces a ALT_PINMUX_DCTD_IO_CFG_14_RSVD_15TO14 register field value suitable for setting the register. */
13019 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_15TO14_SET(value) (((value) << 14) & 0x0000c000)
13020 
13021 /*
13022  * Field : Weak pull up signal - WK_PU_EN
13023  *
13024  * Configuration bit for weak pull up enable
13025  *
13026  * 0 : weak pull up disable
13027  *
13028  * 1 : weak pull up enable
13029  *
13030  * Field Access Macros:
13031  *
13032  */
13033 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_14_WK_PU_EN register field. */
13034 #define ALT_PINMUX_DCTD_IO_CFG_14_WK_PU_EN_LSB 16
13035 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_14_WK_PU_EN register field. */
13036 #define ALT_PINMUX_DCTD_IO_CFG_14_WK_PU_EN_MSB 16
13037 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_14_WK_PU_EN register field. */
13038 #define ALT_PINMUX_DCTD_IO_CFG_14_WK_PU_EN_WIDTH 1
13039 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_14_WK_PU_EN register field value. */
13040 #define ALT_PINMUX_DCTD_IO_CFG_14_WK_PU_EN_SET_MSK 0x00010000
13041 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_14_WK_PU_EN register field value. */
13042 #define ALT_PINMUX_DCTD_IO_CFG_14_WK_PU_EN_CLR_MSK 0xfffeffff
13043 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_14_WK_PU_EN register field. */
13044 #define ALT_PINMUX_DCTD_IO_CFG_14_WK_PU_EN_RESET 0x1
13045 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_14_WK_PU_EN field value from a register. */
13046 #define ALT_PINMUX_DCTD_IO_CFG_14_WK_PU_EN_GET(value) (((value) & 0x00010000) >> 16)
13047 /* Produces a ALT_PINMUX_DCTD_IO_CFG_14_WK_PU_EN register field value suitable for setting the register. */
13048 #define ALT_PINMUX_DCTD_IO_CFG_14_WK_PU_EN_SET(value) (((value) << 16) & 0x00010000)
13049 
13050 /*
13051  * Field : LVTTL input buffer enable signal - INPUT_BUF_EN
13052  *
13053  * Configuration bits for LVTTL input buffer enable
13054  *
13055  * 00 : disable
13056  *
13057  * 01 : 1.8V TTL
13058  *
13059  * 10 : 2.5V/3.0V TTL
13060  *
13061  * 11 : 1.8V TTL
13062  *
13063  * Field Access Macros:
13064  *
13065  */
13066 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_14_INPUT_BUF_EN register field. */
13067 #define ALT_PINMUX_DCTD_IO_CFG_14_INPUT_BUF_EN_LSB 17
13068 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_14_INPUT_BUF_EN register field. */
13069 #define ALT_PINMUX_DCTD_IO_CFG_14_INPUT_BUF_EN_MSB 18
13070 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_14_INPUT_BUF_EN register field. */
13071 #define ALT_PINMUX_DCTD_IO_CFG_14_INPUT_BUF_EN_WIDTH 2
13072 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_14_INPUT_BUF_EN register field value. */
13073 #define ALT_PINMUX_DCTD_IO_CFG_14_INPUT_BUF_EN_SET_MSK 0x00060000
13074 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_14_INPUT_BUF_EN register field value. */
13075 #define ALT_PINMUX_DCTD_IO_CFG_14_INPUT_BUF_EN_CLR_MSK 0xfff9ffff
13076 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_14_INPUT_BUF_EN register field. */
13077 #define ALT_PINMUX_DCTD_IO_CFG_14_INPUT_BUF_EN_RESET 0x2
13078 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_14_INPUT_BUF_EN field value from a register. */
13079 #define ALT_PINMUX_DCTD_IO_CFG_14_INPUT_BUF_EN_GET(value) (((value) & 0x00060000) >> 17)
13080 /* Produces a ALT_PINMUX_DCTD_IO_CFG_14_INPUT_BUF_EN register field value suitable for setting the register. */
13081 #define ALT_PINMUX_DCTD_IO_CFG_14_INPUT_BUF_EN_SET(value) (((value) << 17) & 0x00060000)
13082 
13083 /*
13084  * Field : Bias trim bits - RTRIM
13085  *
13086  * Configuration bits for bias trim
13087  *
13088  * 000 : disable
13089  *
13090  * 001 : default
13091  *
13092  * 010 : trim low
13093  *
13094  * 100 : trim high
13095  *
13096  * others : invalid/reserved
13097  *
13098  * Field Access Macros:
13099  *
13100  */
13101 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_14_RTRIM register field. */
13102 #define ALT_PINMUX_DCTD_IO_CFG_14_RTRIM_LSB 19
13103 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_14_RTRIM register field. */
13104 #define ALT_PINMUX_DCTD_IO_CFG_14_RTRIM_MSB 21
13105 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_14_RTRIM register field. */
13106 #define ALT_PINMUX_DCTD_IO_CFG_14_RTRIM_WIDTH 3
13107 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_14_RTRIM register field value. */
13108 #define ALT_PINMUX_DCTD_IO_CFG_14_RTRIM_SET_MSK 0x00380000
13109 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_14_RTRIM register field value. */
13110 #define ALT_PINMUX_DCTD_IO_CFG_14_RTRIM_CLR_MSK 0xffc7ffff
13111 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_14_RTRIM register field. */
13112 #define ALT_PINMUX_DCTD_IO_CFG_14_RTRIM_RESET 0x1
13113 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_14_RTRIM field value from a register. */
13114 #define ALT_PINMUX_DCTD_IO_CFG_14_RTRIM_GET(value) (((value) & 0x00380000) >> 19)
13115 /* Produces a ALT_PINMUX_DCTD_IO_CFG_14_RTRIM register field value suitable for setting the register. */
13116 #define ALT_PINMUX_DCTD_IO_CFG_14_RTRIM_SET(value) (((value) << 19) & 0x00380000)
13117 
13118 /*
13119  * Field : Reserved_31to22
13120  *
13121  * Reserved
13122  *
13123  * Field Access Macros:
13124  *
13125  */
13126 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_14_RSVD_31TO22 register field. */
13127 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_31TO22_LSB 22
13128 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_14_RSVD_31TO22 register field. */
13129 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_31TO22_MSB 31
13130 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_14_RSVD_31TO22 register field. */
13131 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_31TO22_WIDTH 10
13132 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_14_RSVD_31TO22 register field value. */
13133 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_31TO22_SET_MSK 0xffc00000
13134 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_14_RSVD_31TO22 register field value. */
13135 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_31TO22_CLR_MSK 0x003fffff
13136 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_14_RSVD_31TO22 register field. */
13137 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_31TO22_RESET 0x0
13138 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_14_RSVD_31TO22 field value from a register. */
13139 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_31TO22_GET(value) (((value) & 0xffc00000) >> 22)
13140 /* Produces a ALT_PINMUX_DCTD_IO_CFG_14_RSVD_31TO22 register field value suitable for setting the register. */
13141 #define ALT_PINMUX_DCTD_IO_CFG_14_RSVD_31TO22_SET(value) (((value) << 22) & 0xffc00000)
13142 
13143 #ifndef __ASSEMBLY__
13144 /*
13145  * WARNING: The C register and register group struct declarations are provided for
13146  * convenience and illustrative purposes. They should, however, be used with
13147  * caution as the C language standard provides no guarantees about the alignment or
13148  * atomicity of device memory accesses. The recommended practice for writing
13149  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13150  * alt_write_word() functions.
13151  *
13152  * The struct declaration for register ALT_PINMUX_DCTD_IO_CFG_14.
13153  */
13154 struct ALT_PINMUX_DCTD_IO_CFG_14_s
13155 {
13156  uint32_t PD_DRV_STRG : 5; /* Pull down drive strength */
13157  uint32_t PD_SLW_RT : 1; /* NMOS slew rate */
13158  const uint32_t Reserved_7to6 : 2; /* ALT_PINMUX_DCTD_IO_CFG_14_RSVD_7TO6 */
13159  uint32_t PU_DRV_STRG : 5; /* Pull up drive strength */
13160  uint32_t PU_SLW_RT : 1; /* PMOS slew rate */
13161  const uint32_t Reserved_15to14 : 2; /* ALT_PINMUX_DCTD_IO_CFG_14_RSVD_15TO14 */
13162  uint32_t WK_PU_EN : 1; /* Weak pull up signal */
13163  uint32_t INPUT_BUF_EN : 2; /* LVTTL input buffer enable signal */
13164  uint32_t RTRIM : 3; /* Bias trim bits */
13165  const uint32_t Reserved_31to22 : 10; /* ALT_PINMUX_DCTD_IO_CFG_14_RSVD_31TO22 */
13166 };
13167 
13168 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_CFG_14. */
13169 typedef volatile struct ALT_PINMUX_DCTD_IO_CFG_14_s ALT_PINMUX_DCTD_IO_CFG_14_t;
13170 #endif /* __ASSEMBLY__ */
13171 
13172 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_14 register. */
13173 #define ALT_PINMUX_DCTD_IO_CFG_14_RESET 0x000d0008
13174 /* The byte offset of the ALT_PINMUX_DCTD_IO_CFG_14 register from the beginning of the component. */
13175 #define ALT_PINMUX_DCTD_IO_CFG_14_OFST 0x138
13176 
13177 /*
13178  * Register : Dedicated IO 15 Configuration Register - configuration_dedicated_io_15
13179  *
13180  * This register is used to control the electrical behavior and direction of
13181  * Dedicated IO 15
13182  *
13183  * Only reset by a cold reset (ignores warm reset).
13184  *
13185  * Register Layout
13186  *
13187  * Bits | Access | Reset | Description
13188  * :--------|:-------|:------|:--------------------------------------
13189  * [4:0] | RW | 0x8 | Pull down drive strength
13190  * [5] | RW | 0x0 | NMOS slew rate
13191  * [7:6] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_15_RSVD_7TO6
13192  * [12:8] | RW | 0x0 | Pull up drive strength
13193  * [13] | RW | 0x0 | PMOS slew rate
13194  * [15:14] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_15_RSVD_15TO14
13195  * [16] | RW | 0x1 | Weak pull up signal
13196  * [18:17] | RW | 0x2 | LVTTL input buffer enable signal
13197  * [21:19] | RW | 0x1 | Bias trim bits
13198  * [31:22] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_15_RSVD_31TO22
13199  *
13200  */
13201 /*
13202  * Field : Pull down drive strength - PD_DRV_STRG
13203  *
13204  * Configuration bits for NMOS pull down drive strength.
13205  *
13206  * Pending Characterization
13207  *
13208  * Field Access Macros:
13209  *
13210  */
13211 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_15_PD_DRV_STRG register field. */
13212 #define ALT_PINMUX_DCTD_IO_CFG_15_PD_DRV_STRG_LSB 0
13213 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_15_PD_DRV_STRG register field. */
13214 #define ALT_PINMUX_DCTD_IO_CFG_15_PD_DRV_STRG_MSB 4
13215 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_15_PD_DRV_STRG register field. */
13216 #define ALT_PINMUX_DCTD_IO_CFG_15_PD_DRV_STRG_WIDTH 5
13217 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_15_PD_DRV_STRG register field value. */
13218 #define ALT_PINMUX_DCTD_IO_CFG_15_PD_DRV_STRG_SET_MSK 0x0000001f
13219 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_15_PD_DRV_STRG register field value. */
13220 #define ALT_PINMUX_DCTD_IO_CFG_15_PD_DRV_STRG_CLR_MSK 0xffffffe0
13221 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_15_PD_DRV_STRG register field. */
13222 #define ALT_PINMUX_DCTD_IO_CFG_15_PD_DRV_STRG_RESET 0x8
13223 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_15_PD_DRV_STRG field value from a register. */
13224 #define ALT_PINMUX_DCTD_IO_CFG_15_PD_DRV_STRG_GET(value) (((value) & 0x0000001f) >> 0)
13225 /* Produces a ALT_PINMUX_DCTD_IO_CFG_15_PD_DRV_STRG register field value suitable for setting the register. */
13226 #define ALT_PINMUX_DCTD_IO_CFG_15_PD_DRV_STRG_SET(value) (((value) << 0) & 0x0000001f)
13227 
13228 /*
13229  * Field : NMOS slew rate - PD_SLW_RT
13230  *
13231  * Configuration bit for output pull down slew rate control
13232  *
13233  * 0 : slow N slew
13234  *
13235  * 1 : fast N slew
13236  *
13237  * Field Access Macros:
13238  *
13239  */
13240 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_15_PD_SLW_RT register field. */
13241 #define ALT_PINMUX_DCTD_IO_CFG_15_PD_SLW_RT_LSB 5
13242 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_15_PD_SLW_RT register field. */
13243 #define ALT_PINMUX_DCTD_IO_CFG_15_PD_SLW_RT_MSB 5
13244 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_15_PD_SLW_RT register field. */
13245 #define ALT_PINMUX_DCTD_IO_CFG_15_PD_SLW_RT_WIDTH 1
13246 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_15_PD_SLW_RT register field value. */
13247 #define ALT_PINMUX_DCTD_IO_CFG_15_PD_SLW_RT_SET_MSK 0x00000020
13248 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_15_PD_SLW_RT register field value. */
13249 #define ALT_PINMUX_DCTD_IO_CFG_15_PD_SLW_RT_CLR_MSK 0xffffffdf
13250 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_15_PD_SLW_RT register field. */
13251 #define ALT_PINMUX_DCTD_IO_CFG_15_PD_SLW_RT_RESET 0x0
13252 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_15_PD_SLW_RT field value from a register. */
13253 #define ALT_PINMUX_DCTD_IO_CFG_15_PD_SLW_RT_GET(value) (((value) & 0x00000020) >> 5)
13254 /* Produces a ALT_PINMUX_DCTD_IO_CFG_15_PD_SLW_RT register field value suitable for setting the register. */
13255 #define ALT_PINMUX_DCTD_IO_CFG_15_PD_SLW_RT_SET(value) (((value) << 5) & 0x00000020)
13256 
13257 /*
13258  * Field : Reserved_7to6
13259  *
13260  * Reserved
13261  *
13262  * Field Access Macros:
13263  *
13264  */
13265 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_15_RSVD_7TO6 register field. */
13266 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_7TO6_LSB 6
13267 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_15_RSVD_7TO6 register field. */
13268 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_7TO6_MSB 7
13269 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_15_RSVD_7TO6 register field. */
13270 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_7TO6_WIDTH 2
13271 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_15_RSVD_7TO6 register field value. */
13272 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_7TO6_SET_MSK 0x000000c0
13273 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_15_RSVD_7TO6 register field value. */
13274 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_7TO6_CLR_MSK 0xffffff3f
13275 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_15_RSVD_7TO6 register field. */
13276 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_7TO6_RESET 0x0
13277 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_15_RSVD_7TO6 field value from a register. */
13278 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_7TO6_GET(value) (((value) & 0x000000c0) >> 6)
13279 /* Produces a ALT_PINMUX_DCTD_IO_CFG_15_RSVD_7TO6 register field value suitable for setting the register. */
13280 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_7TO6_SET(value) (((value) << 6) & 0x000000c0)
13281 
13282 /*
13283  * Field : Pull up drive strength - PU_DRV_STRG
13284  *
13285  * Configuration bits for PMOS pull up drive strength
13286  *
13287  * Pending Characterization
13288  *
13289  * Field Access Macros:
13290  *
13291  */
13292 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_15_PU_DRV_STRG register field. */
13293 #define ALT_PINMUX_DCTD_IO_CFG_15_PU_DRV_STRG_LSB 8
13294 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_15_PU_DRV_STRG register field. */
13295 #define ALT_PINMUX_DCTD_IO_CFG_15_PU_DRV_STRG_MSB 12
13296 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_15_PU_DRV_STRG register field. */
13297 #define ALT_PINMUX_DCTD_IO_CFG_15_PU_DRV_STRG_WIDTH 5
13298 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_15_PU_DRV_STRG register field value. */
13299 #define ALT_PINMUX_DCTD_IO_CFG_15_PU_DRV_STRG_SET_MSK 0x00001f00
13300 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_15_PU_DRV_STRG register field value. */
13301 #define ALT_PINMUX_DCTD_IO_CFG_15_PU_DRV_STRG_CLR_MSK 0xffffe0ff
13302 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_15_PU_DRV_STRG register field. */
13303 #define ALT_PINMUX_DCTD_IO_CFG_15_PU_DRV_STRG_RESET 0x0
13304 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_15_PU_DRV_STRG field value from a register. */
13305 #define ALT_PINMUX_DCTD_IO_CFG_15_PU_DRV_STRG_GET(value) (((value) & 0x00001f00) >> 8)
13306 /* Produces a ALT_PINMUX_DCTD_IO_CFG_15_PU_DRV_STRG register field value suitable for setting the register. */
13307 #define ALT_PINMUX_DCTD_IO_CFG_15_PU_DRV_STRG_SET(value) (((value) << 8) & 0x00001f00)
13308 
13309 /*
13310  * Field : PMOS slew rate - PU_SLW_RT
13311  *
13312  * Configuration bit for output pull up slew rate control
13313  *
13314  * 0 : slow P slew
13315  *
13316  * 1 : fast P slew
13317  *
13318  * Field Access Macros:
13319  *
13320  */
13321 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_15_PU_SLW_RT register field. */
13322 #define ALT_PINMUX_DCTD_IO_CFG_15_PU_SLW_RT_LSB 13
13323 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_15_PU_SLW_RT register field. */
13324 #define ALT_PINMUX_DCTD_IO_CFG_15_PU_SLW_RT_MSB 13
13325 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_15_PU_SLW_RT register field. */
13326 #define ALT_PINMUX_DCTD_IO_CFG_15_PU_SLW_RT_WIDTH 1
13327 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_15_PU_SLW_RT register field value. */
13328 #define ALT_PINMUX_DCTD_IO_CFG_15_PU_SLW_RT_SET_MSK 0x00002000
13329 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_15_PU_SLW_RT register field value. */
13330 #define ALT_PINMUX_DCTD_IO_CFG_15_PU_SLW_RT_CLR_MSK 0xffffdfff
13331 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_15_PU_SLW_RT register field. */
13332 #define ALT_PINMUX_DCTD_IO_CFG_15_PU_SLW_RT_RESET 0x0
13333 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_15_PU_SLW_RT field value from a register. */
13334 #define ALT_PINMUX_DCTD_IO_CFG_15_PU_SLW_RT_GET(value) (((value) & 0x00002000) >> 13)
13335 /* Produces a ALT_PINMUX_DCTD_IO_CFG_15_PU_SLW_RT register field value suitable for setting the register. */
13336 #define ALT_PINMUX_DCTD_IO_CFG_15_PU_SLW_RT_SET(value) (((value) << 13) & 0x00002000)
13337 
13338 /*
13339  * Field : Reserved_15to14
13340  *
13341  * Reserved
13342  *
13343  * Field Access Macros:
13344  *
13345  */
13346 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_15_RSVD_15TO14 register field. */
13347 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_15TO14_LSB 14
13348 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_15_RSVD_15TO14 register field. */
13349 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_15TO14_MSB 15
13350 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_15_RSVD_15TO14 register field. */
13351 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_15TO14_WIDTH 2
13352 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_15_RSVD_15TO14 register field value. */
13353 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_15TO14_SET_MSK 0x0000c000
13354 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_15_RSVD_15TO14 register field value. */
13355 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_15TO14_CLR_MSK 0xffff3fff
13356 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_15_RSVD_15TO14 register field. */
13357 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_15TO14_RESET 0x0
13358 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_15_RSVD_15TO14 field value from a register. */
13359 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_15TO14_GET(value) (((value) & 0x0000c000) >> 14)
13360 /* Produces a ALT_PINMUX_DCTD_IO_CFG_15_RSVD_15TO14 register field value suitable for setting the register. */
13361 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_15TO14_SET(value) (((value) << 14) & 0x0000c000)
13362 
13363 /*
13364  * Field : Weak pull up signal - WK_PU_EN
13365  *
13366  * Configuration bit for weak pull up enable
13367  *
13368  * 0 : weak pull up disable
13369  *
13370  * 1 : weak pull up enable
13371  *
13372  * Field Access Macros:
13373  *
13374  */
13375 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_15_WK_PU_EN register field. */
13376 #define ALT_PINMUX_DCTD_IO_CFG_15_WK_PU_EN_LSB 16
13377 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_15_WK_PU_EN register field. */
13378 #define ALT_PINMUX_DCTD_IO_CFG_15_WK_PU_EN_MSB 16
13379 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_15_WK_PU_EN register field. */
13380 #define ALT_PINMUX_DCTD_IO_CFG_15_WK_PU_EN_WIDTH 1
13381 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_15_WK_PU_EN register field value. */
13382 #define ALT_PINMUX_DCTD_IO_CFG_15_WK_PU_EN_SET_MSK 0x00010000
13383 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_15_WK_PU_EN register field value. */
13384 #define ALT_PINMUX_DCTD_IO_CFG_15_WK_PU_EN_CLR_MSK 0xfffeffff
13385 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_15_WK_PU_EN register field. */
13386 #define ALT_PINMUX_DCTD_IO_CFG_15_WK_PU_EN_RESET 0x1
13387 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_15_WK_PU_EN field value from a register. */
13388 #define ALT_PINMUX_DCTD_IO_CFG_15_WK_PU_EN_GET(value) (((value) & 0x00010000) >> 16)
13389 /* Produces a ALT_PINMUX_DCTD_IO_CFG_15_WK_PU_EN register field value suitable for setting the register. */
13390 #define ALT_PINMUX_DCTD_IO_CFG_15_WK_PU_EN_SET(value) (((value) << 16) & 0x00010000)
13391 
13392 /*
13393  * Field : LVTTL input buffer enable signal - INPUT_BUF_EN
13394  *
13395  * Configuration bits for LVTTL input buffer enable
13396  *
13397  * 00 : disable
13398  *
13399  * 01 : 1.8V TTL
13400  *
13401  * 10 : 2.5V/3.0V TTL
13402  *
13403  * 11 : 1.8V TTL
13404  *
13405  * Field Access Macros:
13406  *
13407  */
13408 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_15_INPUT_BUF_EN register field. */
13409 #define ALT_PINMUX_DCTD_IO_CFG_15_INPUT_BUF_EN_LSB 17
13410 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_15_INPUT_BUF_EN register field. */
13411 #define ALT_PINMUX_DCTD_IO_CFG_15_INPUT_BUF_EN_MSB 18
13412 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_15_INPUT_BUF_EN register field. */
13413 #define ALT_PINMUX_DCTD_IO_CFG_15_INPUT_BUF_EN_WIDTH 2
13414 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_15_INPUT_BUF_EN register field value. */
13415 #define ALT_PINMUX_DCTD_IO_CFG_15_INPUT_BUF_EN_SET_MSK 0x00060000
13416 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_15_INPUT_BUF_EN register field value. */
13417 #define ALT_PINMUX_DCTD_IO_CFG_15_INPUT_BUF_EN_CLR_MSK 0xfff9ffff
13418 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_15_INPUT_BUF_EN register field. */
13419 #define ALT_PINMUX_DCTD_IO_CFG_15_INPUT_BUF_EN_RESET 0x2
13420 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_15_INPUT_BUF_EN field value from a register. */
13421 #define ALT_PINMUX_DCTD_IO_CFG_15_INPUT_BUF_EN_GET(value) (((value) & 0x00060000) >> 17)
13422 /* Produces a ALT_PINMUX_DCTD_IO_CFG_15_INPUT_BUF_EN register field value suitable for setting the register. */
13423 #define ALT_PINMUX_DCTD_IO_CFG_15_INPUT_BUF_EN_SET(value) (((value) << 17) & 0x00060000)
13424 
13425 /*
13426  * Field : Bias trim bits - RTRIM
13427  *
13428  * Configuration bits for bias trim
13429  *
13430  * 000 : disable
13431  *
13432  * 001 : default
13433  *
13434  * 010 : trim low
13435  *
13436  * 100 : trim high
13437  *
13438  * others : invalid/reserved
13439  *
13440  * Field Access Macros:
13441  *
13442  */
13443 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_15_RTRIM register field. */
13444 #define ALT_PINMUX_DCTD_IO_CFG_15_RTRIM_LSB 19
13445 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_15_RTRIM register field. */
13446 #define ALT_PINMUX_DCTD_IO_CFG_15_RTRIM_MSB 21
13447 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_15_RTRIM register field. */
13448 #define ALT_PINMUX_DCTD_IO_CFG_15_RTRIM_WIDTH 3
13449 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_15_RTRIM register field value. */
13450 #define ALT_PINMUX_DCTD_IO_CFG_15_RTRIM_SET_MSK 0x00380000
13451 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_15_RTRIM register field value. */
13452 #define ALT_PINMUX_DCTD_IO_CFG_15_RTRIM_CLR_MSK 0xffc7ffff
13453 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_15_RTRIM register field. */
13454 #define ALT_PINMUX_DCTD_IO_CFG_15_RTRIM_RESET 0x1
13455 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_15_RTRIM field value from a register. */
13456 #define ALT_PINMUX_DCTD_IO_CFG_15_RTRIM_GET(value) (((value) & 0x00380000) >> 19)
13457 /* Produces a ALT_PINMUX_DCTD_IO_CFG_15_RTRIM register field value suitable for setting the register. */
13458 #define ALT_PINMUX_DCTD_IO_CFG_15_RTRIM_SET(value) (((value) << 19) & 0x00380000)
13459 
13460 /*
13461  * Field : Reserved_31to22
13462  *
13463  * Reserved
13464  *
13465  * Field Access Macros:
13466  *
13467  */
13468 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_15_RSVD_31TO22 register field. */
13469 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_31TO22_LSB 22
13470 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_15_RSVD_31TO22 register field. */
13471 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_31TO22_MSB 31
13472 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_15_RSVD_31TO22 register field. */
13473 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_31TO22_WIDTH 10
13474 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_15_RSVD_31TO22 register field value. */
13475 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_31TO22_SET_MSK 0xffc00000
13476 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_15_RSVD_31TO22 register field value. */
13477 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_31TO22_CLR_MSK 0x003fffff
13478 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_15_RSVD_31TO22 register field. */
13479 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_31TO22_RESET 0x0
13480 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_15_RSVD_31TO22 field value from a register. */
13481 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_31TO22_GET(value) (((value) & 0xffc00000) >> 22)
13482 /* Produces a ALT_PINMUX_DCTD_IO_CFG_15_RSVD_31TO22 register field value suitable for setting the register. */
13483 #define ALT_PINMUX_DCTD_IO_CFG_15_RSVD_31TO22_SET(value) (((value) << 22) & 0xffc00000)
13484 
13485 #ifndef __ASSEMBLY__
13486 /*
13487  * WARNING: The C register and register group struct declarations are provided for
13488  * convenience and illustrative purposes. They should, however, be used with
13489  * caution as the C language standard provides no guarantees about the alignment or
13490  * atomicity of device memory accesses. The recommended practice for writing
13491  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13492  * alt_write_word() functions.
13493  *
13494  * The struct declaration for register ALT_PINMUX_DCTD_IO_CFG_15.
13495  */
13496 struct ALT_PINMUX_DCTD_IO_CFG_15_s
13497 {
13498  uint32_t PD_DRV_STRG : 5; /* Pull down drive strength */
13499  uint32_t PD_SLW_RT : 1; /* NMOS slew rate */
13500  const uint32_t Reserved_7to6 : 2; /* ALT_PINMUX_DCTD_IO_CFG_15_RSVD_7TO6 */
13501  uint32_t PU_DRV_STRG : 5; /* Pull up drive strength */
13502  uint32_t PU_SLW_RT : 1; /* PMOS slew rate */
13503  const uint32_t Reserved_15to14 : 2; /* ALT_PINMUX_DCTD_IO_CFG_15_RSVD_15TO14 */
13504  uint32_t WK_PU_EN : 1; /* Weak pull up signal */
13505  uint32_t INPUT_BUF_EN : 2; /* LVTTL input buffer enable signal */
13506  uint32_t RTRIM : 3; /* Bias trim bits */
13507  const uint32_t Reserved_31to22 : 10; /* ALT_PINMUX_DCTD_IO_CFG_15_RSVD_31TO22 */
13508 };
13509 
13510 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_CFG_15. */
13511 typedef volatile struct ALT_PINMUX_DCTD_IO_CFG_15_s ALT_PINMUX_DCTD_IO_CFG_15_t;
13512 #endif /* __ASSEMBLY__ */
13513 
13514 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_15 register. */
13515 #define ALT_PINMUX_DCTD_IO_CFG_15_RESET 0x000d0008
13516 /* The byte offset of the ALT_PINMUX_DCTD_IO_CFG_15 register from the beginning of the component. */
13517 #define ALT_PINMUX_DCTD_IO_CFG_15_OFST 0x13c
13518 
13519 /*
13520  * Register : Dedicated IO 16 Configuration Register - configuration_dedicated_io_16
13521  *
13522  * This register is used to control the electrical behavior and direction of
13523  * Dedicated IO 16
13524  *
13525  * Only reset by a cold reset (ignores warm reset).
13526  *
13527  * Register Layout
13528  *
13529  * Bits | Access | Reset | Description
13530  * :--------|:-------|:------|:--------------------------------------
13531  * [4:0] | RW | 0x8 | Pull down drive strength
13532  * [5] | RW | 0x0 | NMOS slew rate
13533  * [7:6] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_16_RSVD_7TO6
13534  * [12:8] | RW | 0x0 | Pull up drive strength
13535  * [13] | RW | 0x0 | PMOS slew rate
13536  * [15:14] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_16_RSVD_15TO14
13537  * [16] | RW | 0x1 | Weak pull up signal
13538  * [18:17] | RW | 0x2 | LVTTL input buffer enable signal
13539  * [21:19] | RW | 0x1 | Bias trim bits
13540  * [31:22] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_16_RSVD_31TO22
13541  *
13542  */
13543 /*
13544  * Field : Pull down drive strength - PD_DRV_STRG
13545  *
13546  * Configuration bits for NMOS pull down drive strength.
13547  *
13548  * Pending Characterization
13549  *
13550  * Field Access Macros:
13551  *
13552  */
13553 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_16_PD_DRV_STRG register field. */
13554 #define ALT_PINMUX_DCTD_IO_CFG_16_PD_DRV_STRG_LSB 0
13555 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_16_PD_DRV_STRG register field. */
13556 #define ALT_PINMUX_DCTD_IO_CFG_16_PD_DRV_STRG_MSB 4
13557 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_16_PD_DRV_STRG register field. */
13558 #define ALT_PINMUX_DCTD_IO_CFG_16_PD_DRV_STRG_WIDTH 5
13559 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_16_PD_DRV_STRG register field value. */
13560 #define ALT_PINMUX_DCTD_IO_CFG_16_PD_DRV_STRG_SET_MSK 0x0000001f
13561 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_16_PD_DRV_STRG register field value. */
13562 #define ALT_PINMUX_DCTD_IO_CFG_16_PD_DRV_STRG_CLR_MSK 0xffffffe0
13563 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_16_PD_DRV_STRG register field. */
13564 #define ALT_PINMUX_DCTD_IO_CFG_16_PD_DRV_STRG_RESET 0x8
13565 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_16_PD_DRV_STRG field value from a register. */
13566 #define ALT_PINMUX_DCTD_IO_CFG_16_PD_DRV_STRG_GET(value) (((value) & 0x0000001f) >> 0)
13567 /* Produces a ALT_PINMUX_DCTD_IO_CFG_16_PD_DRV_STRG register field value suitable for setting the register. */
13568 #define ALT_PINMUX_DCTD_IO_CFG_16_PD_DRV_STRG_SET(value) (((value) << 0) & 0x0000001f)
13569 
13570 /*
13571  * Field : NMOS slew rate - PD_SLW_RT
13572  *
13573  * Configuration bit for output pull down slew rate control
13574  *
13575  * 0 : slow N slew
13576  *
13577  * 1 : fast N slew
13578  *
13579  * Field Access Macros:
13580  *
13581  */
13582 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_16_PD_SLW_RT register field. */
13583 #define ALT_PINMUX_DCTD_IO_CFG_16_PD_SLW_RT_LSB 5
13584 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_16_PD_SLW_RT register field. */
13585 #define ALT_PINMUX_DCTD_IO_CFG_16_PD_SLW_RT_MSB 5
13586 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_16_PD_SLW_RT register field. */
13587 #define ALT_PINMUX_DCTD_IO_CFG_16_PD_SLW_RT_WIDTH 1
13588 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_16_PD_SLW_RT register field value. */
13589 #define ALT_PINMUX_DCTD_IO_CFG_16_PD_SLW_RT_SET_MSK 0x00000020
13590 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_16_PD_SLW_RT register field value. */
13591 #define ALT_PINMUX_DCTD_IO_CFG_16_PD_SLW_RT_CLR_MSK 0xffffffdf
13592 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_16_PD_SLW_RT register field. */
13593 #define ALT_PINMUX_DCTD_IO_CFG_16_PD_SLW_RT_RESET 0x0
13594 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_16_PD_SLW_RT field value from a register. */
13595 #define ALT_PINMUX_DCTD_IO_CFG_16_PD_SLW_RT_GET(value) (((value) & 0x00000020) >> 5)
13596 /* Produces a ALT_PINMUX_DCTD_IO_CFG_16_PD_SLW_RT register field value suitable for setting the register. */
13597 #define ALT_PINMUX_DCTD_IO_CFG_16_PD_SLW_RT_SET(value) (((value) << 5) & 0x00000020)
13598 
13599 /*
13600  * Field : Reserved_7to6
13601  *
13602  * Reserved
13603  *
13604  * Field Access Macros:
13605  *
13606  */
13607 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_16_RSVD_7TO6 register field. */
13608 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_7TO6_LSB 6
13609 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_16_RSVD_7TO6 register field. */
13610 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_7TO6_MSB 7
13611 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_16_RSVD_7TO6 register field. */
13612 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_7TO6_WIDTH 2
13613 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_16_RSVD_7TO6 register field value. */
13614 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_7TO6_SET_MSK 0x000000c0
13615 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_16_RSVD_7TO6 register field value. */
13616 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_7TO6_CLR_MSK 0xffffff3f
13617 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_16_RSVD_7TO6 register field. */
13618 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_7TO6_RESET 0x0
13619 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_16_RSVD_7TO6 field value from a register. */
13620 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_7TO6_GET(value) (((value) & 0x000000c0) >> 6)
13621 /* Produces a ALT_PINMUX_DCTD_IO_CFG_16_RSVD_7TO6 register field value suitable for setting the register. */
13622 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_7TO6_SET(value) (((value) << 6) & 0x000000c0)
13623 
13624 /*
13625  * Field : Pull up drive strength - PU_DRV_STRG
13626  *
13627  * Configuration bits for PMOS pull up drive strength
13628  *
13629  * Pending Characterization
13630  *
13631  * Field Access Macros:
13632  *
13633  */
13634 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_16_PU_DRV_STRG register field. */
13635 #define ALT_PINMUX_DCTD_IO_CFG_16_PU_DRV_STRG_LSB 8
13636 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_16_PU_DRV_STRG register field. */
13637 #define ALT_PINMUX_DCTD_IO_CFG_16_PU_DRV_STRG_MSB 12
13638 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_16_PU_DRV_STRG register field. */
13639 #define ALT_PINMUX_DCTD_IO_CFG_16_PU_DRV_STRG_WIDTH 5
13640 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_16_PU_DRV_STRG register field value. */
13641 #define ALT_PINMUX_DCTD_IO_CFG_16_PU_DRV_STRG_SET_MSK 0x00001f00
13642 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_16_PU_DRV_STRG register field value. */
13643 #define ALT_PINMUX_DCTD_IO_CFG_16_PU_DRV_STRG_CLR_MSK 0xffffe0ff
13644 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_16_PU_DRV_STRG register field. */
13645 #define ALT_PINMUX_DCTD_IO_CFG_16_PU_DRV_STRG_RESET 0x0
13646 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_16_PU_DRV_STRG field value from a register. */
13647 #define ALT_PINMUX_DCTD_IO_CFG_16_PU_DRV_STRG_GET(value) (((value) & 0x00001f00) >> 8)
13648 /* Produces a ALT_PINMUX_DCTD_IO_CFG_16_PU_DRV_STRG register field value suitable for setting the register. */
13649 #define ALT_PINMUX_DCTD_IO_CFG_16_PU_DRV_STRG_SET(value) (((value) << 8) & 0x00001f00)
13650 
13651 /*
13652  * Field : PMOS slew rate - PU_SLW_RT
13653  *
13654  * Configuration bit for output pull up slew rate control
13655  *
13656  * 0 : slow P slew
13657  *
13658  * 1 : fast P slew
13659  *
13660  * Field Access Macros:
13661  *
13662  */
13663 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_16_PU_SLW_RT register field. */
13664 #define ALT_PINMUX_DCTD_IO_CFG_16_PU_SLW_RT_LSB 13
13665 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_16_PU_SLW_RT register field. */
13666 #define ALT_PINMUX_DCTD_IO_CFG_16_PU_SLW_RT_MSB 13
13667 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_16_PU_SLW_RT register field. */
13668 #define ALT_PINMUX_DCTD_IO_CFG_16_PU_SLW_RT_WIDTH 1
13669 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_16_PU_SLW_RT register field value. */
13670 #define ALT_PINMUX_DCTD_IO_CFG_16_PU_SLW_RT_SET_MSK 0x00002000
13671 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_16_PU_SLW_RT register field value. */
13672 #define ALT_PINMUX_DCTD_IO_CFG_16_PU_SLW_RT_CLR_MSK 0xffffdfff
13673 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_16_PU_SLW_RT register field. */
13674 #define ALT_PINMUX_DCTD_IO_CFG_16_PU_SLW_RT_RESET 0x0
13675 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_16_PU_SLW_RT field value from a register. */
13676 #define ALT_PINMUX_DCTD_IO_CFG_16_PU_SLW_RT_GET(value) (((value) & 0x00002000) >> 13)
13677 /* Produces a ALT_PINMUX_DCTD_IO_CFG_16_PU_SLW_RT register field value suitable for setting the register. */
13678 #define ALT_PINMUX_DCTD_IO_CFG_16_PU_SLW_RT_SET(value) (((value) << 13) & 0x00002000)
13679 
13680 /*
13681  * Field : Reserved_15to14
13682  *
13683  * Reserved
13684  *
13685  * Field Access Macros:
13686  *
13687  */
13688 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_16_RSVD_15TO14 register field. */
13689 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_15TO14_LSB 14
13690 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_16_RSVD_15TO14 register field. */
13691 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_15TO14_MSB 15
13692 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_16_RSVD_15TO14 register field. */
13693 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_15TO14_WIDTH 2
13694 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_16_RSVD_15TO14 register field value. */
13695 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_15TO14_SET_MSK 0x0000c000
13696 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_16_RSVD_15TO14 register field value. */
13697 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_15TO14_CLR_MSK 0xffff3fff
13698 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_16_RSVD_15TO14 register field. */
13699 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_15TO14_RESET 0x0
13700 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_16_RSVD_15TO14 field value from a register. */
13701 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_15TO14_GET(value) (((value) & 0x0000c000) >> 14)
13702 /* Produces a ALT_PINMUX_DCTD_IO_CFG_16_RSVD_15TO14 register field value suitable for setting the register. */
13703 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_15TO14_SET(value) (((value) << 14) & 0x0000c000)
13704 
13705 /*
13706  * Field : Weak pull up signal - WK_PU_EN
13707  *
13708  * Configuration bit for weak pull up enable
13709  *
13710  * 0 : weak pull up disable
13711  *
13712  * 1 : weak pull up enable
13713  *
13714  * Field Access Macros:
13715  *
13716  */
13717 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_16_WK_PU_EN register field. */
13718 #define ALT_PINMUX_DCTD_IO_CFG_16_WK_PU_EN_LSB 16
13719 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_16_WK_PU_EN register field. */
13720 #define ALT_PINMUX_DCTD_IO_CFG_16_WK_PU_EN_MSB 16
13721 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_16_WK_PU_EN register field. */
13722 #define ALT_PINMUX_DCTD_IO_CFG_16_WK_PU_EN_WIDTH 1
13723 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_16_WK_PU_EN register field value. */
13724 #define ALT_PINMUX_DCTD_IO_CFG_16_WK_PU_EN_SET_MSK 0x00010000
13725 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_16_WK_PU_EN register field value. */
13726 #define ALT_PINMUX_DCTD_IO_CFG_16_WK_PU_EN_CLR_MSK 0xfffeffff
13727 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_16_WK_PU_EN register field. */
13728 #define ALT_PINMUX_DCTD_IO_CFG_16_WK_PU_EN_RESET 0x1
13729 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_16_WK_PU_EN field value from a register. */
13730 #define ALT_PINMUX_DCTD_IO_CFG_16_WK_PU_EN_GET(value) (((value) & 0x00010000) >> 16)
13731 /* Produces a ALT_PINMUX_DCTD_IO_CFG_16_WK_PU_EN register field value suitable for setting the register. */
13732 #define ALT_PINMUX_DCTD_IO_CFG_16_WK_PU_EN_SET(value) (((value) << 16) & 0x00010000)
13733 
13734 /*
13735  * Field : LVTTL input buffer enable signal - INPUT_BUF_EN
13736  *
13737  * Configuration bits for LVTTL input buffer enable
13738  *
13739  * 00 : disable
13740  *
13741  * 01 : 1.8V TTL
13742  *
13743  * 10 : 2.5V/3.0V TTL
13744  *
13745  * 11 : 1.8V TTL
13746  *
13747  * Field Access Macros:
13748  *
13749  */
13750 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_16_INPUT_BUF_EN register field. */
13751 #define ALT_PINMUX_DCTD_IO_CFG_16_INPUT_BUF_EN_LSB 17
13752 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_16_INPUT_BUF_EN register field. */
13753 #define ALT_PINMUX_DCTD_IO_CFG_16_INPUT_BUF_EN_MSB 18
13754 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_16_INPUT_BUF_EN register field. */
13755 #define ALT_PINMUX_DCTD_IO_CFG_16_INPUT_BUF_EN_WIDTH 2
13756 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_16_INPUT_BUF_EN register field value. */
13757 #define ALT_PINMUX_DCTD_IO_CFG_16_INPUT_BUF_EN_SET_MSK 0x00060000
13758 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_16_INPUT_BUF_EN register field value. */
13759 #define ALT_PINMUX_DCTD_IO_CFG_16_INPUT_BUF_EN_CLR_MSK 0xfff9ffff
13760 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_16_INPUT_BUF_EN register field. */
13761 #define ALT_PINMUX_DCTD_IO_CFG_16_INPUT_BUF_EN_RESET 0x2
13762 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_16_INPUT_BUF_EN field value from a register. */
13763 #define ALT_PINMUX_DCTD_IO_CFG_16_INPUT_BUF_EN_GET(value) (((value) & 0x00060000) >> 17)
13764 /* Produces a ALT_PINMUX_DCTD_IO_CFG_16_INPUT_BUF_EN register field value suitable for setting the register. */
13765 #define ALT_PINMUX_DCTD_IO_CFG_16_INPUT_BUF_EN_SET(value) (((value) << 17) & 0x00060000)
13766 
13767 /*
13768  * Field : Bias trim bits - RTRIM
13769  *
13770  * Configuration bits for bias trim
13771  *
13772  * 000 : disable
13773  *
13774  * 001 : default
13775  *
13776  * 010 : trim low
13777  *
13778  * 100 : trim high
13779  *
13780  * others : invalid/reserved
13781  *
13782  * Field Access Macros:
13783  *
13784  */
13785 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_16_RTRIM register field. */
13786 #define ALT_PINMUX_DCTD_IO_CFG_16_RTRIM_LSB 19
13787 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_16_RTRIM register field. */
13788 #define ALT_PINMUX_DCTD_IO_CFG_16_RTRIM_MSB 21
13789 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_16_RTRIM register field. */
13790 #define ALT_PINMUX_DCTD_IO_CFG_16_RTRIM_WIDTH 3
13791 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_16_RTRIM register field value. */
13792 #define ALT_PINMUX_DCTD_IO_CFG_16_RTRIM_SET_MSK 0x00380000
13793 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_16_RTRIM register field value. */
13794 #define ALT_PINMUX_DCTD_IO_CFG_16_RTRIM_CLR_MSK 0xffc7ffff
13795 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_16_RTRIM register field. */
13796 #define ALT_PINMUX_DCTD_IO_CFG_16_RTRIM_RESET 0x1
13797 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_16_RTRIM field value from a register. */
13798 #define ALT_PINMUX_DCTD_IO_CFG_16_RTRIM_GET(value) (((value) & 0x00380000) >> 19)
13799 /* Produces a ALT_PINMUX_DCTD_IO_CFG_16_RTRIM register field value suitable for setting the register. */
13800 #define ALT_PINMUX_DCTD_IO_CFG_16_RTRIM_SET(value) (((value) << 19) & 0x00380000)
13801 
13802 /*
13803  * Field : Reserved_31to22
13804  *
13805  * Reserved
13806  *
13807  * Field Access Macros:
13808  *
13809  */
13810 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_16_RSVD_31TO22 register field. */
13811 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_31TO22_LSB 22
13812 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_16_RSVD_31TO22 register field. */
13813 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_31TO22_MSB 31
13814 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_16_RSVD_31TO22 register field. */
13815 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_31TO22_WIDTH 10
13816 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_16_RSVD_31TO22 register field value. */
13817 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_31TO22_SET_MSK 0xffc00000
13818 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_16_RSVD_31TO22 register field value. */
13819 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_31TO22_CLR_MSK 0x003fffff
13820 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_16_RSVD_31TO22 register field. */
13821 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_31TO22_RESET 0x0
13822 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_16_RSVD_31TO22 field value from a register. */
13823 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_31TO22_GET(value) (((value) & 0xffc00000) >> 22)
13824 /* Produces a ALT_PINMUX_DCTD_IO_CFG_16_RSVD_31TO22 register field value suitable for setting the register. */
13825 #define ALT_PINMUX_DCTD_IO_CFG_16_RSVD_31TO22_SET(value) (((value) << 22) & 0xffc00000)
13826 
13827 #ifndef __ASSEMBLY__
13828 /*
13829  * WARNING: The C register and register group struct declarations are provided for
13830  * convenience and illustrative purposes. They should, however, be used with
13831  * caution as the C language standard provides no guarantees about the alignment or
13832  * atomicity of device memory accesses. The recommended practice for writing
13833  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13834  * alt_write_word() functions.
13835  *
13836  * The struct declaration for register ALT_PINMUX_DCTD_IO_CFG_16.
13837  */
13838 struct ALT_PINMUX_DCTD_IO_CFG_16_s
13839 {
13840  uint32_t PD_DRV_STRG : 5; /* Pull down drive strength */
13841  uint32_t PD_SLW_RT : 1; /* NMOS slew rate */
13842  const uint32_t Reserved_7to6 : 2; /* ALT_PINMUX_DCTD_IO_CFG_16_RSVD_7TO6 */
13843  uint32_t PU_DRV_STRG : 5; /* Pull up drive strength */
13844  uint32_t PU_SLW_RT : 1; /* PMOS slew rate */
13845  const uint32_t Reserved_15to14 : 2; /* ALT_PINMUX_DCTD_IO_CFG_16_RSVD_15TO14 */
13846  uint32_t WK_PU_EN : 1; /* Weak pull up signal */
13847  uint32_t INPUT_BUF_EN : 2; /* LVTTL input buffer enable signal */
13848  uint32_t RTRIM : 3; /* Bias trim bits */
13849  const uint32_t Reserved_31to22 : 10; /* ALT_PINMUX_DCTD_IO_CFG_16_RSVD_31TO22 */
13850 };
13851 
13852 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_CFG_16. */
13853 typedef volatile struct ALT_PINMUX_DCTD_IO_CFG_16_s ALT_PINMUX_DCTD_IO_CFG_16_t;
13854 #endif /* __ASSEMBLY__ */
13855 
13856 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_16 register. */
13857 #define ALT_PINMUX_DCTD_IO_CFG_16_RESET 0x000d0008
13858 /* The byte offset of the ALT_PINMUX_DCTD_IO_CFG_16 register from the beginning of the component. */
13859 #define ALT_PINMUX_DCTD_IO_CFG_16_OFST 0x140
13860 
13861 /*
13862  * Register : Dedicated IO 17 Configuration Register - configuration_dedicated_io_17
13863  *
13864  * This register is used to control the electrical behavior and direction of
13865  * Dedicated IO 17
13866  *
13867  * Only reset by a cold reset (ignores warm reset).
13868  *
13869  * Register Layout
13870  *
13871  * Bits | Access | Reset | Description
13872  * :--------|:-------|:------|:--------------------------------------
13873  * [4:0] | RW | 0x8 | Pull down drive strength
13874  * [5] | RW | 0x0 | NMOS slew rate
13875  * [7:6] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_17_RSVD_7TO6
13876  * [12:8] | RW | 0x0 | Pull up drive strength
13877  * [13] | RW | 0x0 | PMOS slew rate
13878  * [15:14] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_17_RSVD_15TO14
13879  * [16] | RW | 0x1 | Weak pull up signal
13880  * [18:17] | RW | 0x2 | LVTTL input buffer enable signal
13881  * [21:19] | RW | 0x1 | Bias trim bits
13882  * [31:22] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_17_RSVD_31TO22
13883  *
13884  */
13885 /*
13886  * Field : Pull down drive strength - PD_DRV_STRG
13887  *
13888  * Configuration bits for NMOS pull down drive strength.
13889  *
13890  * Pending Characterization
13891  *
13892  * Field Access Macros:
13893  *
13894  */
13895 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_17_PD_DRV_STRG register field. */
13896 #define ALT_PINMUX_DCTD_IO_CFG_17_PD_DRV_STRG_LSB 0
13897 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_17_PD_DRV_STRG register field. */
13898 #define ALT_PINMUX_DCTD_IO_CFG_17_PD_DRV_STRG_MSB 4
13899 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_17_PD_DRV_STRG register field. */
13900 #define ALT_PINMUX_DCTD_IO_CFG_17_PD_DRV_STRG_WIDTH 5
13901 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_17_PD_DRV_STRG register field value. */
13902 #define ALT_PINMUX_DCTD_IO_CFG_17_PD_DRV_STRG_SET_MSK 0x0000001f
13903 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_17_PD_DRV_STRG register field value. */
13904 #define ALT_PINMUX_DCTD_IO_CFG_17_PD_DRV_STRG_CLR_MSK 0xffffffe0
13905 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_17_PD_DRV_STRG register field. */
13906 #define ALT_PINMUX_DCTD_IO_CFG_17_PD_DRV_STRG_RESET 0x8
13907 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_17_PD_DRV_STRG field value from a register. */
13908 #define ALT_PINMUX_DCTD_IO_CFG_17_PD_DRV_STRG_GET(value) (((value) & 0x0000001f) >> 0)
13909 /* Produces a ALT_PINMUX_DCTD_IO_CFG_17_PD_DRV_STRG register field value suitable for setting the register. */
13910 #define ALT_PINMUX_DCTD_IO_CFG_17_PD_DRV_STRG_SET(value) (((value) << 0) & 0x0000001f)
13911 
13912 /*
13913  * Field : NMOS slew rate - PD_SLW_RT
13914  *
13915  * Configuration bit for output pull down slew rate control
13916  *
13917  * 0 : slow N slew
13918  *
13919  * 1 : fast N slew
13920  *
13921  * Field Access Macros:
13922  *
13923  */
13924 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_17_PD_SLW_RT register field. */
13925 #define ALT_PINMUX_DCTD_IO_CFG_17_PD_SLW_RT_LSB 5
13926 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_17_PD_SLW_RT register field. */
13927 #define ALT_PINMUX_DCTD_IO_CFG_17_PD_SLW_RT_MSB 5
13928 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_17_PD_SLW_RT register field. */
13929 #define ALT_PINMUX_DCTD_IO_CFG_17_PD_SLW_RT_WIDTH 1
13930 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_17_PD_SLW_RT register field value. */
13931 #define ALT_PINMUX_DCTD_IO_CFG_17_PD_SLW_RT_SET_MSK 0x00000020
13932 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_17_PD_SLW_RT register field value. */
13933 #define ALT_PINMUX_DCTD_IO_CFG_17_PD_SLW_RT_CLR_MSK 0xffffffdf
13934 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_17_PD_SLW_RT register field. */
13935 #define ALT_PINMUX_DCTD_IO_CFG_17_PD_SLW_RT_RESET 0x0
13936 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_17_PD_SLW_RT field value from a register. */
13937 #define ALT_PINMUX_DCTD_IO_CFG_17_PD_SLW_RT_GET(value) (((value) & 0x00000020) >> 5)
13938 /* Produces a ALT_PINMUX_DCTD_IO_CFG_17_PD_SLW_RT register field value suitable for setting the register. */
13939 #define ALT_PINMUX_DCTD_IO_CFG_17_PD_SLW_RT_SET(value) (((value) << 5) & 0x00000020)
13940 
13941 /*
13942  * Field : Reserved_7to6
13943  *
13944  * Reserved
13945  *
13946  * Field Access Macros:
13947  *
13948  */
13949 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_17_RSVD_7TO6 register field. */
13950 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_7TO6_LSB 6
13951 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_17_RSVD_7TO6 register field. */
13952 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_7TO6_MSB 7
13953 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_17_RSVD_7TO6 register field. */
13954 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_7TO6_WIDTH 2
13955 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_17_RSVD_7TO6 register field value. */
13956 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_7TO6_SET_MSK 0x000000c0
13957 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_17_RSVD_7TO6 register field value. */
13958 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_7TO6_CLR_MSK 0xffffff3f
13959 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_17_RSVD_7TO6 register field. */
13960 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_7TO6_RESET 0x0
13961 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_17_RSVD_7TO6 field value from a register. */
13962 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_7TO6_GET(value) (((value) & 0x000000c0) >> 6)
13963 /* Produces a ALT_PINMUX_DCTD_IO_CFG_17_RSVD_7TO6 register field value suitable for setting the register. */
13964 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_7TO6_SET(value) (((value) << 6) & 0x000000c0)
13965 
13966 /*
13967  * Field : Pull up drive strength - PU_DRV_STRG
13968  *
13969  * Configuration bits for PMOS pull up drive strength
13970  *
13971  * Pending Characterization
13972  *
13973  * Field Access Macros:
13974  *
13975  */
13976 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_17_PU_DRV_STRG register field. */
13977 #define ALT_PINMUX_DCTD_IO_CFG_17_PU_DRV_STRG_LSB 8
13978 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_17_PU_DRV_STRG register field. */
13979 #define ALT_PINMUX_DCTD_IO_CFG_17_PU_DRV_STRG_MSB 12
13980 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_17_PU_DRV_STRG register field. */
13981 #define ALT_PINMUX_DCTD_IO_CFG_17_PU_DRV_STRG_WIDTH 5
13982 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_17_PU_DRV_STRG register field value. */
13983 #define ALT_PINMUX_DCTD_IO_CFG_17_PU_DRV_STRG_SET_MSK 0x00001f00
13984 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_17_PU_DRV_STRG register field value. */
13985 #define ALT_PINMUX_DCTD_IO_CFG_17_PU_DRV_STRG_CLR_MSK 0xffffe0ff
13986 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_17_PU_DRV_STRG register field. */
13987 #define ALT_PINMUX_DCTD_IO_CFG_17_PU_DRV_STRG_RESET 0x0
13988 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_17_PU_DRV_STRG field value from a register. */
13989 #define ALT_PINMUX_DCTD_IO_CFG_17_PU_DRV_STRG_GET(value) (((value) & 0x00001f00) >> 8)
13990 /* Produces a ALT_PINMUX_DCTD_IO_CFG_17_PU_DRV_STRG register field value suitable for setting the register. */
13991 #define ALT_PINMUX_DCTD_IO_CFG_17_PU_DRV_STRG_SET(value) (((value) << 8) & 0x00001f00)
13992 
13993 /*
13994  * Field : PMOS slew rate - PU_SLW_RT
13995  *
13996  * Configuration bit for output pull up slew rate control
13997  *
13998  * 0 : slow P slew
13999  *
14000  * 1 : fast P slew
14001  *
14002  * Field Access Macros:
14003  *
14004  */
14005 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_17_PU_SLW_RT register field. */
14006 #define ALT_PINMUX_DCTD_IO_CFG_17_PU_SLW_RT_LSB 13
14007 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_17_PU_SLW_RT register field. */
14008 #define ALT_PINMUX_DCTD_IO_CFG_17_PU_SLW_RT_MSB 13
14009 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_17_PU_SLW_RT register field. */
14010 #define ALT_PINMUX_DCTD_IO_CFG_17_PU_SLW_RT_WIDTH 1
14011 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_17_PU_SLW_RT register field value. */
14012 #define ALT_PINMUX_DCTD_IO_CFG_17_PU_SLW_RT_SET_MSK 0x00002000
14013 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_17_PU_SLW_RT register field value. */
14014 #define ALT_PINMUX_DCTD_IO_CFG_17_PU_SLW_RT_CLR_MSK 0xffffdfff
14015 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_17_PU_SLW_RT register field. */
14016 #define ALT_PINMUX_DCTD_IO_CFG_17_PU_SLW_RT_RESET 0x0
14017 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_17_PU_SLW_RT field value from a register. */
14018 #define ALT_PINMUX_DCTD_IO_CFG_17_PU_SLW_RT_GET(value) (((value) & 0x00002000) >> 13)
14019 /* Produces a ALT_PINMUX_DCTD_IO_CFG_17_PU_SLW_RT register field value suitable for setting the register. */
14020 #define ALT_PINMUX_DCTD_IO_CFG_17_PU_SLW_RT_SET(value) (((value) << 13) & 0x00002000)
14021 
14022 /*
14023  * Field : Reserved_15to14
14024  *
14025  * Reserved
14026  *
14027  * Field Access Macros:
14028  *
14029  */
14030 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_17_RSVD_15TO14 register field. */
14031 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_15TO14_LSB 14
14032 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_17_RSVD_15TO14 register field. */
14033 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_15TO14_MSB 15
14034 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_17_RSVD_15TO14 register field. */
14035 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_15TO14_WIDTH 2
14036 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_17_RSVD_15TO14 register field value. */
14037 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_15TO14_SET_MSK 0x0000c000
14038 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_17_RSVD_15TO14 register field value. */
14039 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_15TO14_CLR_MSK 0xffff3fff
14040 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_17_RSVD_15TO14 register field. */
14041 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_15TO14_RESET 0x0
14042 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_17_RSVD_15TO14 field value from a register. */
14043 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_15TO14_GET(value) (((value) & 0x0000c000) >> 14)
14044 /* Produces a ALT_PINMUX_DCTD_IO_CFG_17_RSVD_15TO14 register field value suitable for setting the register. */
14045 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_15TO14_SET(value) (((value) << 14) & 0x0000c000)
14046 
14047 /*
14048  * Field : Weak pull up signal - WK_PU_EN
14049  *
14050  * Configuration bit for weak pull up enable
14051  *
14052  * 0 : weak pull up disable
14053  *
14054  * 1 : weak pull up enable
14055  *
14056  * Field Access Macros:
14057  *
14058  */
14059 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_17_WK_PU_EN register field. */
14060 #define ALT_PINMUX_DCTD_IO_CFG_17_WK_PU_EN_LSB 16
14061 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_17_WK_PU_EN register field. */
14062 #define ALT_PINMUX_DCTD_IO_CFG_17_WK_PU_EN_MSB 16
14063 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_17_WK_PU_EN register field. */
14064 #define ALT_PINMUX_DCTD_IO_CFG_17_WK_PU_EN_WIDTH 1
14065 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_17_WK_PU_EN register field value. */
14066 #define ALT_PINMUX_DCTD_IO_CFG_17_WK_PU_EN_SET_MSK 0x00010000
14067 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_17_WK_PU_EN register field value. */
14068 #define ALT_PINMUX_DCTD_IO_CFG_17_WK_PU_EN_CLR_MSK 0xfffeffff
14069 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_17_WK_PU_EN register field. */
14070 #define ALT_PINMUX_DCTD_IO_CFG_17_WK_PU_EN_RESET 0x1
14071 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_17_WK_PU_EN field value from a register. */
14072 #define ALT_PINMUX_DCTD_IO_CFG_17_WK_PU_EN_GET(value) (((value) & 0x00010000) >> 16)
14073 /* Produces a ALT_PINMUX_DCTD_IO_CFG_17_WK_PU_EN register field value suitable for setting the register. */
14074 #define ALT_PINMUX_DCTD_IO_CFG_17_WK_PU_EN_SET(value) (((value) << 16) & 0x00010000)
14075 
14076 /*
14077  * Field : LVTTL input buffer enable signal - INPUT_BUF_EN
14078  *
14079  * Configuration bits for LVTTL input buffer enable
14080  *
14081  * 00 : disable
14082  *
14083  * 01 : 1.8V TTL
14084  *
14085  * 10 : 2.5V/3.0V TTL
14086  *
14087  * 11 : 1.8V TTL
14088  *
14089  * Field Access Macros:
14090  *
14091  */
14092 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_17_INPUT_BUF_EN register field. */
14093 #define ALT_PINMUX_DCTD_IO_CFG_17_INPUT_BUF_EN_LSB 17
14094 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_17_INPUT_BUF_EN register field. */
14095 #define ALT_PINMUX_DCTD_IO_CFG_17_INPUT_BUF_EN_MSB 18
14096 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_17_INPUT_BUF_EN register field. */
14097 #define ALT_PINMUX_DCTD_IO_CFG_17_INPUT_BUF_EN_WIDTH 2
14098 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_17_INPUT_BUF_EN register field value. */
14099 #define ALT_PINMUX_DCTD_IO_CFG_17_INPUT_BUF_EN_SET_MSK 0x00060000
14100 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_17_INPUT_BUF_EN register field value. */
14101 #define ALT_PINMUX_DCTD_IO_CFG_17_INPUT_BUF_EN_CLR_MSK 0xfff9ffff
14102 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_17_INPUT_BUF_EN register field. */
14103 #define ALT_PINMUX_DCTD_IO_CFG_17_INPUT_BUF_EN_RESET 0x2
14104 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_17_INPUT_BUF_EN field value from a register. */
14105 #define ALT_PINMUX_DCTD_IO_CFG_17_INPUT_BUF_EN_GET(value) (((value) & 0x00060000) >> 17)
14106 /* Produces a ALT_PINMUX_DCTD_IO_CFG_17_INPUT_BUF_EN register field value suitable for setting the register. */
14107 #define ALT_PINMUX_DCTD_IO_CFG_17_INPUT_BUF_EN_SET(value) (((value) << 17) & 0x00060000)
14108 
14109 /*
14110  * Field : Bias trim bits - RTRIM
14111  *
14112  * Configuration bits for bias trim
14113  *
14114  * 000 : disable
14115  *
14116  * 001 : default
14117  *
14118  * 010 : trim low
14119  *
14120  * 100 : trim high
14121  *
14122  * others : invalid/reserved
14123  *
14124  * Field Access Macros:
14125  *
14126  */
14127 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_17_RTRIM register field. */
14128 #define ALT_PINMUX_DCTD_IO_CFG_17_RTRIM_LSB 19
14129 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_17_RTRIM register field. */
14130 #define ALT_PINMUX_DCTD_IO_CFG_17_RTRIM_MSB 21
14131 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_17_RTRIM register field. */
14132 #define ALT_PINMUX_DCTD_IO_CFG_17_RTRIM_WIDTH 3
14133 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_17_RTRIM register field value. */
14134 #define ALT_PINMUX_DCTD_IO_CFG_17_RTRIM_SET_MSK 0x00380000
14135 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_17_RTRIM register field value. */
14136 #define ALT_PINMUX_DCTD_IO_CFG_17_RTRIM_CLR_MSK 0xffc7ffff
14137 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_17_RTRIM register field. */
14138 #define ALT_PINMUX_DCTD_IO_CFG_17_RTRIM_RESET 0x1
14139 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_17_RTRIM field value from a register. */
14140 #define ALT_PINMUX_DCTD_IO_CFG_17_RTRIM_GET(value) (((value) & 0x00380000) >> 19)
14141 /* Produces a ALT_PINMUX_DCTD_IO_CFG_17_RTRIM register field value suitable for setting the register. */
14142 #define ALT_PINMUX_DCTD_IO_CFG_17_RTRIM_SET(value) (((value) << 19) & 0x00380000)
14143 
14144 /*
14145  * Field : Reserved_31to22
14146  *
14147  * Reserved
14148  *
14149  * Field Access Macros:
14150  *
14151  */
14152 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_17_RSVD_31TO22 register field. */
14153 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_31TO22_LSB 22
14154 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_17_RSVD_31TO22 register field. */
14155 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_31TO22_MSB 31
14156 /* The width in bits of the ALT_PINMUX_DCTD_IO_CFG_17_RSVD_31TO22 register field. */
14157 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_31TO22_WIDTH 10
14158 /* The mask used to set the ALT_PINMUX_DCTD_IO_CFG_17_RSVD_31TO22 register field value. */
14159 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_31TO22_SET_MSK 0xffc00000
14160 /* The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_17_RSVD_31TO22 register field value. */
14161 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_31TO22_CLR_MSK 0x003fffff
14162 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_17_RSVD_31TO22 register field. */
14163 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_31TO22_RESET 0x0
14164 /* Extracts the ALT_PINMUX_DCTD_IO_CFG_17_RSVD_31TO22 field value from a register. */
14165 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_31TO22_GET(value) (((value) & 0xffc00000) >> 22)
14166 /* Produces a ALT_PINMUX_DCTD_IO_CFG_17_RSVD_31TO22 register field value suitable for setting the register. */
14167 #define ALT_PINMUX_DCTD_IO_CFG_17_RSVD_31TO22_SET(value) (((value) << 22) & 0xffc00000)
14168 
14169 #ifndef __ASSEMBLY__
14170 /*
14171  * WARNING: The C register and register group struct declarations are provided for
14172  * convenience and illustrative purposes. They should, however, be used with
14173  * caution as the C language standard provides no guarantees about the alignment or
14174  * atomicity of device memory accesses. The recommended practice for writing
14175  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14176  * alt_write_word() functions.
14177  *
14178  * The struct declaration for register ALT_PINMUX_DCTD_IO_CFG_17.
14179  */
14180 struct ALT_PINMUX_DCTD_IO_CFG_17_s
14181 {
14182  uint32_t PD_DRV_STRG : 5; /* Pull down drive strength */
14183  uint32_t PD_SLW_RT : 1; /* NMOS slew rate */
14184  const uint32_t Reserved_7to6 : 2; /* ALT_PINMUX_DCTD_IO_CFG_17_RSVD_7TO6 */
14185  uint32_t PU_DRV_STRG : 5; /* Pull up drive strength */
14186  uint32_t PU_SLW_RT : 1; /* PMOS slew rate */
14187  const uint32_t Reserved_15to14 : 2; /* ALT_PINMUX_DCTD_IO_CFG_17_RSVD_15TO14 */
14188  uint32_t WK_PU_EN : 1; /* Weak pull up signal */
14189  uint32_t INPUT_BUF_EN : 2; /* LVTTL input buffer enable signal */
14190  uint32_t RTRIM : 3; /* Bias trim bits */
14191  const uint32_t Reserved_31to22 : 10; /* ALT_PINMUX_DCTD_IO_CFG_17_RSVD_31TO22 */
14192 };
14193 
14194 /* The typedef declaration for register ALT_PINMUX_DCTD_IO_CFG_17. */
14195 typedef volatile struct ALT_PINMUX_DCTD_IO_CFG_17_s ALT_PINMUX_DCTD_IO_CFG_17_t;
14196 #endif /* __ASSEMBLY__ */
14197 
14198 /* The reset value of the ALT_PINMUX_DCTD_IO_CFG_17 register. */
14199 #define ALT_PINMUX_DCTD_IO_CFG_17_RESET 0x000d0008
14200 /* The byte offset of the ALT_PINMUX_DCTD_IO_CFG_17 register from the beginning of the component. */
14201 #define ALT_PINMUX_DCTD_IO_CFG_17_OFST 0x144
14202 
14203 #ifndef __ASSEMBLY__
14204 /*
14205  * WARNING: The C register and register group struct declarations are provided for
14206  * convenience and illustrative purposes. They should, however, be used with
14207  * caution as the C language standard provides no guarantees about the alignment or
14208  * atomicity of device memory accesses. The recommended practice for writing
14209  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14210  * alt_write_word() functions.
14211  *
14212  * The struct declaration for register group ALT_PINMUX_DCTD_IO_GRP.
14213  */
14214 struct ALT_PINMUX_DCTD_IO_GRP_s
14215 {
14216  ALT_PINMUX_DCTD_IO_1_t pinmux_dedicated_io_1; /* ALT_PINMUX_DCTD_IO_1 */
14217  ALT_PINMUX_DCTD_IO_2_t pinmux_dedicated_io_2; /* ALT_PINMUX_DCTD_IO_2 */
14218  ALT_PINMUX_DCTD_IO_3_t pinmux_dedicated_io_3; /* ALT_PINMUX_DCTD_IO_3 */
14219  ALT_PINMUX_DCTD_IO_4_t pinmux_dedicated_io_4; /* ALT_PINMUX_DCTD_IO_4 */
14220  ALT_PINMUX_DCTD_IO_5_t pinmux_dedicated_io_5; /* ALT_PINMUX_DCTD_IO_5 */
14221  ALT_PINMUX_DCTD_IO_6_t pinmux_dedicated_io_6; /* ALT_PINMUX_DCTD_IO_6 */
14222  ALT_PINMUX_DCTD_IO_7_t pinmux_dedicated_io_7; /* ALT_PINMUX_DCTD_IO_7 */
14223  ALT_PINMUX_DCTD_IO_8_t pinmux_dedicated_io_8; /* ALT_PINMUX_DCTD_IO_8 */
14224  ALT_PINMUX_DCTD_IO_9_t pinmux_dedicated_io_9; /* ALT_PINMUX_DCTD_IO_9 */
14225  ALT_PINMUX_DCTD_IO_10_t pinmux_dedicated_io_10; /* ALT_PINMUX_DCTD_IO_10 */
14226  ALT_PINMUX_DCTD_IO_11_t pinmux_dedicated_io_11; /* ALT_PINMUX_DCTD_IO_11 */
14227  ALT_PINMUX_DCTD_IO_12_t pinmux_dedicated_io_12; /* ALT_PINMUX_DCTD_IO_12 */
14228  ALT_PINMUX_DCTD_IO_13_t pinmux_dedicated_io_13; /* ALT_PINMUX_DCTD_IO_13 */
14229  ALT_PINMUX_DCTD_IO_14_t pinmux_dedicated_io_14; /* ALT_PINMUX_DCTD_IO_14 */
14230  ALT_PINMUX_DCTD_IO_15_t pinmux_dedicated_io_15; /* ALT_PINMUX_DCTD_IO_15 */
14231  ALT_PINMUX_DCTD_IO_16_t pinmux_dedicated_io_16; /* ALT_PINMUX_DCTD_IO_16 */
14232  ALT_PINMUX_DCTD_IO_17_t pinmux_dedicated_io_17; /* ALT_PINMUX_DCTD_IO_17 */
14233  volatile uint32_t _pad_0x44_0xff[47]; /* *UNDEFINED* */
14234  ALT_PINMUX_DCTD_IO_CFG_BANK_t configuration_dedicated_io_bank; /* ALT_PINMUX_DCTD_IO_CFG_BANK */
14235  ALT_PINMUX_DCTD_IO_CFG_1_t configuration_dedicated_io_1; /* ALT_PINMUX_DCTD_IO_CFG_1 */
14236  ALT_PINMUX_DCTD_IO_CFG_2_t configuration_dedicated_io_2; /* ALT_PINMUX_DCTD_IO_CFG_2 */
14237  ALT_PINMUX_DCTD_IO_CFG_3_t configuration_dedicated_io_3; /* ALT_PINMUX_DCTD_IO_CFG_3 */
14238  ALT_PINMUX_DCTD_IO_CFG_4_t configuration_dedicated_io_4; /* ALT_PINMUX_DCTD_IO_CFG_4 */
14239  ALT_PINMUX_DCTD_IO_CFG_5_t configuration_dedicated_io_5; /* ALT_PINMUX_DCTD_IO_CFG_5 */
14240  ALT_PINMUX_DCTD_IO_CFG_6_t configuration_dedicated_io_6; /* ALT_PINMUX_DCTD_IO_CFG_6 */
14241  ALT_PINMUX_DCTD_IO_CFG_7_t configuration_dedicated_io_7; /* ALT_PINMUX_DCTD_IO_CFG_7 */
14242  ALT_PINMUX_DCTD_IO_CFG_8_t configuration_dedicated_io_8; /* ALT_PINMUX_DCTD_IO_CFG_8 */
14243  ALT_PINMUX_DCTD_IO_CFG_9_t configuration_dedicated_io_9; /* ALT_PINMUX_DCTD_IO_CFG_9 */
14244  ALT_PINMUX_DCTD_IO_CFG_10_t configuration_dedicated_io_10; /* ALT_PINMUX_DCTD_IO_CFG_10 */
14245  ALT_PINMUX_DCTD_IO_CFG_11_t configuration_dedicated_io_11; /* ALT_PINMUX_DCTD_IO_CFG_11 */
14246  ALT_PINMUX_DCTD_IO_CFG_12_t configuration_dedicated_io_12; /* ALT_PINMUX_DCTD_IO_CFG_12 */
14247  ALT_PINMUX_DCTD_IO_CFG_13_t configuration_dedicated_io_13; /* ALT_PINMUX_DCTD_IO_CFG_13 */
14248  ALT_PINMUX_DCTD_IO_CFG_14_t configuration_dedicated_io_14; /* ALT_PINMUX_DCTD_IO_CFG_14 */
14249  ALT_PINMUX_DCTD_IO_CFG_15_t configuration_dedicated_io_15; /* ALT_PINMUX_DCTD_IO_CFG_15 */
14250  ALT_PINMUX_DCTD_IO_CFG_16_t configuration_dedicated_io_16; /* ALT_PINMUX_DCTD_IO_CFG_16 */
14251  ALT_PINMUX_DCTD_IO_CFG_17_t configuration_dedicated_io_17; /* ALT_PINMUX_DCTD_IO_CFG_17 */
14252  volatile uint32_t _pad_0x148_0x200[46]; /* *UNDEFINED* */
14253 };
14254 
14255 /* The typedef declaration for register group ALT_PINMUX_DCTD_IO_GRP. */
14256 typedef volatile struct ALT_PINMUX_DCTD_IO_GRP_s ALT_PINMUX_DCTD_IO_GRP_t;
14257 /* The struct declaration for the raw register contents of register group ALT_PINMUX_DCTD_IO_GRP. */
14258 struct ALT_PINMUX_DCTD_IO_GRP_raw_s
14259 {
14260  volatile uint32_t pinmux_dedicated_io_1; /* ALT_PINMUX_DCTD_IO_1 */
14261  volatile uint32_t pinmux_dedicated_io_2; /* ALT_PINMUX_DCTD_IO_2 */
14262  volatile uint32_t pinmux_dedicated_io_3; /* ALT_PINMUX_DCTD_IO_3 */
14263  volatile uint32_t pinmux_dedicated_io_4; /* ALT_PINMUX_DCTD_IO_4 */
14264  volatile uint32_t pinmux_dedicated_io_5; /* ALT_PINMUX_DCTD_IO_5 */
14265  volatile uint32_t pinmux_dedicated_io_6; /* ALT_PINMUX_DCTD_IO_6 */
14266  volatile uint32_t pinmux_dedicated_io_7; /* ALT_PINMUX_DCTD_IO_7 */
14267  volatile uint32_t pinmux_dedicated_io_8; /* ALT_PINMUX_DCTD_IO_8 */
14268  volatile uint32_t pinmux_dedicated_io_9; /* ALT_PINMUX_DCTD_IO_9 */
14269  volatile uint32_t pinmux_dedicated_io_10; /* ALT_PINMUX_DCTD_IO_10 */
14270  volatile uint32_t pinmux_dedicated_io_11; /* ALT_PINMUX_DCTD_IO_11 */
14271  volatile uint32_t pinmux_dedicated_io_12; /* ALT_PINMUX_DCTD_IO_12 */
14272  volatile uint32_t pinmux_dedicated_io_13; /* ALT_PINMUX_DCTD_IO_13 */
14273  volatile uint32_t pinmux_dedicated_io_14; /* ALT_PINMUX_DCTD_IO_14 */
14274  volatile uint32_t pinmux_dedicated_io_15; /* ALT_PINMUX_DCTD_IO_15 */
14275  volatile uint32_t pinmux_dedicated_io_16; /* ALT_PINMUX_DCTD_IO_16 */
14276  volatile uint32_t pinmux_dedicated_io_17; /* ALT_PINMUX_DCTD_IO_17 */
14277  uint32_t _pad_0x44_0xff[47]; /* *UNDEFINED* */
14278  volatile uint32_t configuration_dedicated_io_bank; /* ALT_PINMUX_DCTD_IO_CFG_BANK */
14279  volatile uint32_t configuration_dedicated_io_1; /* ALT_PINMUX_DCTD_IO_CFG_1 */
14280  volatile uint32_t configuration_dedicated_io_2; /* ALT_PINMUX_DCTD_IO_CFG_2 */
14281  volatile uint32_t configuration_dedicated_io_3; /* ALT_PINMUX_DCTD_IO_CFG_3 */
14282  volatile uint32_t configuration_dedicated_io_4; /* ALT_PINMUX_DCTD_IO_CFG_4 */
14283  volatile uint32_t configuration_dedicated_io_5; /* ALT_PINMUX_DCTD_IO_CFG_5 */
14284  volatile uint32_t configuration_dedicated_io_6; /* ALT_PINMUX_DCTD_IO_CFG_6 */
14285  volatile uint32_t configuration_dedicated_io_7; /* ALT_PINMUX_DCTD_IO_CFG_7 */
14286  volatile uint32_t configuration_dedicated_io_8; /* ALT_PINMUX_DCTD_IO_CFG_8 */
14287  volatile uint32_t configuration_dedicated_io_9; /* ALT_PINMUX_DCTD_IO_CFG_9 */
14288  volatile uint32_t configuration_dedicated_io_10; /* ALT_PINMUX_DCTD_IO_CFG_10 */
14289  volatile uint32_t configuration_dedicated_io_11; /* ALT_PINMUX_DCTD_IO_CFG_11 */
14290  volatile uint32_t configuration_dedicated_io_12; /* ALT_PINMUX_DCTD_IO_CFG_12 */
14291  volatile uint32_t configuration_dedicated_io_13; /* ALT_PINMUX_DCTD_IO_CFG_13 */
14292  volatile uint32_t configuration_dedicated_io_14; /* ALT_PINMUX_DCTD_IO_CFG_14 */
14293  volatile uint32_t configuration_dedicated_io_15; /* ALT_PINMUX_DCTD_IO_CFG_15 */
14294  volatile uint32_t configuration_dedicated_io_16; /* ALT_PINMUX_DCTD_IO_CFG_16 */
14295  volatile uint32_t configuration_dedicated_io_17; /* ALT_PINMUX_DCTD_IO_CFG_17 */
14296  uint32_t _pad_0x148_0x200[46]; /* *UNDEFINED* */
14297 };
14298 
14299 /* The typedef declaration for the raw register contents of register group ALT_PINMUX_DCTD_IO_GRP. */
14300 typedef volatile struct ALT_PINMUX_DCTD_IO_GRP_raw_s ALT_PINMUX_DCTD_IO_GRP_raw_t;
14301 #endif /* __ASSEMBLY__ */
14302 
14303 
14304 /*
14305  * Component : ALT_PINMUX_FPGA_INTERFACE_GRP
14306  *
14307  */
14308 /*
14309  * Register : Select source for EMAC0 signals (HPS Pins or FPGA Interface) - pinmux_emac0_usefpga
14310  *
14311  * Selection between HPS Pin and FPGA Interface for EMAC0 signals
14312  *
14313  * Only reset by a cold reset (ignores warm reset).
14314  *
14315  * NOTE: These registers should not be modified after IO configuration.There is no
14316  * support for dynamically changing the Pin Mux selections.
14317  *
14318  * Register Layout
14319  *
14320  * Bits | Access | Reset | Description
14321  * :-------|:-------|:------|:-----------------------------------
14322  * [0] | RW | 0x0 | Selection for EMAC0 signals
14323  * [31:1] | R | 0x0 | ALT_PINMUX_FPGA_EMAC0_USEFPGA_RSVD
14324  *
14325  */
14326 /*
14327  * Field : Selection for EMAC0 signals - sel
14328  *
14329  * Select connection for EMAC0.
14330  *
14331  * 0 : EMAC0 uses HPS IO Pins.
14332  *
14333  * 1 : EMAC0 uses the FPGA Inteface.
14334  *
14335  * Field Access Macros:
14336  *
14337  */
14338 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_EMAC0_USEFPGA_SEL register field. */
14339 #define ALT_PINMUX_FPGA_EMAC0_USEFPGA_SEL_LSB 0
14340 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_EMAC0_USEFPGA_SEL register field. */
14341 #define ALT_PINMUX_FPGA_EMAC0_USEFPGA_SEL_MSB 0
14342 /* The width in bits of the ALT_PINMUX_FPGA_EMAC0_USEFPGA_SEL register field. */
14343 #define ALT_PINMUX_FPGA_EMAC0_USEFPGA_SEL_WIDTH 1
14344 /* The mask used to set the ALT_PINMUX_FPGA_EMAC0_USEFPGA_SEL register field value. */
14345 #define ALT_PINMUX_FPGA_EMAC0_USEFPGA_SEL_SET_MSK 0x00000001
14346 /* The mask used to clear the ALT_PINMUX_FPGA_EMAC0_USEFPGA_SEL register field value. */
14347 #define ALT_PINMUX_FPGA_EMAC0_USEFPGA_SEL_CLR_MSK 0xfffffffe
14348 /* The reset value of the ALT_PINMUX_FPGA_EMAC0_USEFPGA_SEL register field. */
14349 #define ALT_PINMUX_FPGA_EMAC0_USEFPGA_SEL_RESET 0x0
14350 /* Extracts the ALT_PINMUX_FPGA_EMAC0_USEFPGA_SEL field value from a register. */
14351 #define ALT_PINMUX_FPGA_EMAC0_USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
14352 /* Produces a ALT_PINMUX_FPGA_EMAC0_USEFPGA_SEL register field value suitable for setting the register. */
14353 #define ALT_PINMUX_FPGA_EMAC0_USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
14354 
14355 /*
14356  * Field : Reserved
14357  *
14358  * Reserved
14359  *
14360  * Field Access Macros:
14361  *
14362  */
14363 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_EMAC0_USEFPGA_RSVD register field. */
14364 #define ALT_PINMUX_FPGA_EMAC0_USEFPGA_RSVD_LSB 1
14365 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_EMAC0_USEFPGA_RSVD register field. */
14366 #define ALT_PINMUX_FPGA_EMAC0_USEFPGA_RSVD_MSB 31
14367 /* The width in bits of the ALT_PINMUX_FPGA_EMAC0_USEFPGA_RSVD register field. */
14368 #define ALT_PINMUX_FPGA_EMAC0_USEFPGA_RSVD_WIDTH 31
14369 /* The mask used to set the ALT_PINMUX_FPGA_EMAC0_USEFPGA_RSVD register field value. */
14370 #define ALT_PINMUX_FPGA_EMAC0_USEFPGA_RSVD_SET_MSK 0xfffffffe
14371 /* The mask used to clear the ALT_PINMUX_FPGA_EMAC0_USEFPGA_RSVD register field value. */
14372 #define ALT_PINMUX_FPGA_EMAC0_USEFPGA_RSVD_CLR_MSK 0x00000001
14373 /* The reset value of the ALT_PINMUX_FPGA_EMAC0_USEFPGA_RSVD register field. */
14374 #define ALT_PINMUX_FPGA_EMAC0_USEFPGA_RSVD_RESET 0x0
14375 /* Extracts the ALT_PINMUX_FPGA_EMAC0_USEFPGA_RSVD field value from a register. */
14376 #define ALT_PINMUX_FPGA_EMAC0_USEFPGA_RSVD_GET(value) (((value) & 0xfffffffe) >> 1)
14377 /* Produces a ALT_PINMUX_FPGA_EMAC0_USEFPGA_RSVD register field value suitable for setting the register. */
14378 #define ALT_PINMUX_FPGA_EMAC0_USEFPGA_RSVD_SET(value) (((value) << 1) & 0xfffffffe)
14379 
14380 #ifndef __ASSEMBLY__
14381 /*
14382  * WARNING: The C register and register group struct declarations are provided for
14383  * convenience and illustrative purposes. They should, however, be used with
14384  * caution as the C language standard provides no guarantees about the alignment or
14385  * atomicity of device memory accesses. The recommended practice for writing
14386  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14387  * alt_write_word() functions.
14388  *
14389  * The struct declaration for register ALT_PINMUX_FPGA_EMAC0_USEFPGA.
14390  */
14391 struct ALT_PINMUX_FPGA_EMAC0_USEFPGA_s
14392 {
14393  uint32_t sel : 1; /* Selection for EMAC0 signals */
14394  const uint32_t Reserved : 31; /* ALT_PINMUX_FPGA_EMAC0_USEFPGA_RSVD */
14395 };
14396 
14397 /* The typedef declaration for register ALT_PINMUX_FPGA_EMAC0_USEFPGA. */
14398 typedef volatile struct ALT_PINMUX_FPGA_EMAC0_USEFPGA_s ALT_PINMUX_FPGA_EMAC0_USEFPGA_t;
14399 #endif /* __ASSEMBLY__ */
14400 
14401 /* The reset value of the ALT_PINMUX_FPGA_EMAC0_USEFPGA register. */
14402 #define ALT_PINMUX_FPGA_EMAC0_USEFPGA_RESET 0x00000000
14403 /* The byte offset of the ALT_PINMUX_FPGA_EMAC0_USEFPGA register from the beginning of the component. */
14404 #define ALT_PINMUX_FPGA_EMAC0_USEFPGA_OFST 0x0
14405 
14406 /*
14407  * Register : Select source for EMAC1 signals (HPS Pins or FPGA Interface) - pinmux_emac1_usefpga
14408  *
14409  * Selection between HPS Pin and FPGA Interface for EMAC1 signals
14410  *
14411  * Only reset by a cold reset (ignores warm reset).
14412  *
14413  * NOTE: These registers should not be modified after IO configuration.There is no
14414  * support for dynamically changing the Pin Mux selections.
14415  *
14416  * Register Layout
14417  *
14418  * Bits | Access | Reset | Description
14419  * :-------|:-------|:------|:-----------------------------------
14420  * [0] | RW | 0x0 | Selection for EMAC1 signals
14421  * [31:1] | R | 0x0 | ALT_PINMUX_FPGA_EMAC1_USEFPGA_RSVD
14422  *
14423  */
14424 /*
14425  * Field : Selection for EMAC1 signals - sel
14426  *
14427  * Select connection for EMAC1.
14428  *
14429  * 0 : EMAC1 uses HPS IO Pins.
14430  *
14431  * 1 : EMAC1 uses the FPGA Inteface.
14432  *
14433  * Field Access Macros:
14434  *
14435  */
14436 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_EMAC1_USEFPGA_SEL register field. */
14437 #define ALT_PINMUX_FPGA_EMAC1_USEFPGA_SEL_LSB 0
14438 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_EMAC1_USEFPGA_SEL register field. */
14439 #define ALT_PINMUX_FPGA_EMAC1_USEFPGA_SEL_MSB 0
14440 /* The width in bits of the ALT_PINMUX_FPGA_EMAC1_USEFPGA_SEL register field. */
14441 #define ALT_PINMUX_FPGA_EMAC1_USEFPGA_SEL_WIDTH 1
14442 /* The mask used to set the ALT_PINMUX_FPGA_EMAC1_USEFPGA_SEL register field value. */
14443 #define ALT_PINMUX_FPGA_EMAC1_USEFPGA_SEL_SET_MSK 0x00000001
14444 /* The mask used to clear the ALT_PINMUX_FPGA_EMAC1_USEFPGA_SEL register field value. */
14445 #define ALT_PINMUX_FPGA_EMAC1_USEFPGA_SEL_CLR_MSK 0xfffffffe
14446 /* The reset value of the ALT_PINMUX_FPGA_EMAC1_USEFPGA_SEL register field. */
14447 #define ALT_PINMUX_FPGA_EMAC1_USEFPGA_SEL_RESET 0x0
14448 /* Extracts the ALT_PINMUX_FPGA_EMAC1_USEFPGA_SEL field value from a register. */
14449 #define ALT_PINMUX_FPGA_EMAC1_USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
14450 /* Produces a ALT_PINMUX_FPGA_EMAC1_USEFPGA_SEL register field value suitable for setting the register. */
14451 #define ALT_PINMUX_FPGA_EMAC1_USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
14452 
14453 /*
14454  * Field : Reserved
14455  *
14456  * Reserved
14457  *
14458  * Field Access Macros:
14459  *
14460  */
14461 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_EMAC1_USEFPGA_RSVD register field. */
14462 #define ALT_PINMUX_FPGA_EMAC1_USEFPGA_RSVD_LSB 1
14463 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_EMAC1_USEFPGA_RSVD register field. */
14464 #define ALT_PINMUX_FPGA_EMAC1_USEFPGA_RSVD_MSB 31
14465 /* The width in bits of the ALT_PINMUX_FPGA_EMAC1_USEFPGA_RSVD register field. */
14466 #define ALT_PINMUX_FPGA_EMAC1_USEFPGA_RSVD_WIDTH 31
14467 /* The mask used to set the ALT_PINMUX_FPGA_EMAC1_USEFPGA_RSVD register field value. */
14468 #define ALT_PINMUX_FPGA_EMAC1_USEFPGA_RSVD_SET_MSK 0xfffffffe
14469 /* The mask used to clear the ALT_PINMUX_FPGA_EMAC1_USEFPGA_RSVD register field value. */
14470 #define ALT_PINMUX_FPGA_EMAC1_USEFPGA_RSVD_CLR_MSK 0x00000001
14471 /* The reset value of the ALT_PINMUX_FPGA_EMAC1_USEFPGA_RSVD register field. */
14472 #define ALT_PINMUX_FPGA_EMAC1_USEFPGA_RSVD_RESET 0x0
14473 /* Extracts the ALT_PINMUX_FPGA_EMAC1_USEFPGA_RSVD field value from a register. */
14474 #define ALT_PINMUX_FPGA_EMAC1_USEFPGA_RSVD_GET(value) (((value) & 0xfffffffe) >> 1)
14475 /* Produces a ALT_PINMUX_FPGA_EMAC1_USEFPGA_RSVD register field value suitable for setting the register. */
14476 #define ALT_PINMUX_FPGA_EMAC1_USEFPGA_RSVD_SET(value) (((value) << 1) & 0xfffffffe)
14477 
14478 #ifndef __ASSEMBLY__
14479 /*
14480  * WARNING: The C register and register group struct declarations are provided for
14481  * convenience and illustrative purposes. They should, however, be used with
14482  * caution as the C language standard provides no guarantees about the alignment or
14483  * atomicity of device memory accesses. The recommended practice for writing
14484  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14485  * alt_write_word() functions.
14486  *
14487  * The struct declaration for register ALT_PINMUX_FPGA_EMAC1_USEFPGA.
14488  */
14489 struct ALT_PINMUX_FPGA_EMAC1_USEFPGA_s
14490 {
14491  uint32_t sel : 1; /* Selection for EMAC1 signals */
14492  const uint32_t Reserved : 31; /* ALT_PINMUX_FPGA_EMAC1_USEFPGA_RSVD */
14493 };
14494 
14495 /* The typedef declaration for register ALT_PINMUX_FPGA_EMAC1_USEFPGA. */
14496 typedef volatile struct ALT_PINMUX_FPGA_EMAC1_USEFPGA_s ALT_PINMUX_FPGA_EMAC1_USEFPGA_t;
14497 #endif /* __ASSEMBLY__ */
14498 
14499 /* The reset value of the ALT_PINMUX_FPGA_EMAC1_USEFPGA register. */
14500 #define ALT_PINMUX_FPGA_EMAC1_USEFPGA_RESET 0x00000000
14501 /* The byte offset of the ALT_PINMUX_FPGA_EMAC1_USEFPGA register from the beginning of the component. */
14502 #define ALT_PINMUX_FPGA_EMAC1_USEFPGA_OFST 0x4
14503 
14504 /*
14505  * Register : Select source for EMAC2 signals (HPS Pins or FPGA Interface) - pinmux_emac2_usefpga
14506  *
14507  * Selection between HPS Pin and FPGA Interface for EMAC2 signals
14508  *
14509  * Only reset by a cold reset (ignores warm reset).
14510  *
14511  * NOTE: These registers should not be modified after IO configuration.There is no
14512  * support for dynamically changing the Pin Mux selections.
14513  *
14514  * Register Layout
14515  *
14516  * Bits | Access | Reset | Description
14517  * :-------|:-------|:------|:-----------------------------------
14518  * [0] | RW | 0x0 | Selection for EMAC2 signals
14519  * [31:1] | R | 0x0 | ALT_PINMUX_FPGA_EMAC2_USEFPGA_RSVD
14520  *
14521  */
14522 /*
14523  * Field : Selection for EMAC2 signals - sel
14524  *
14525  * Select connection for EMAC2.
14526  *
14527  * 0 : EMAC2 uses HPS IO Pins.
14528  *
14529  * 1 : EMAC2 uses the FPGA Inteface.
14530  *
14531  * Field Access Macros:
14532  *
14533  */
14534 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_EMAC2_USEFPGA_SEL register field. */
14535 #define ALT_PINMUX_FPGA_EMAC2_USEFPGA_SEL_LSB 0
14536 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_EMAC2_USEFPGA_SEL register field. */
14537 #define ALT_PINMUX_FPGA_EMAC2_USEFPGA_SEL_MSB 0
14538 /* The width in bits of the ALT_PINMUX_FPGA_EMAC2_USEFPGA_SEL register field. */
14539 #define ALT_PINMUX_FPGA_EMAC2_USEFPGA_SEL_WIDTH 1
14540 /* The mask used to set the ALT_PINMUX_FPGA_EMAC2_USEFPGA_SEL register field value. */
14541 #define ALT_PINMUX_FPGA_EMAC2_USEFPGA_SEL_SET_MSK 0x00000001
14542 /* The mask used to clear the ALT_PINMUX_FPGA_EMAC2_USEFPGA_SEL register field value. */
14543 #define ALT_PINMUX_FPGA_EMAC2_USEFPGA_SEL_CLR_MSK 0xfffffffe
14544 /* The reset value of the ALT_PINMUX_FPGA_EMAC2_USEFPGA_SEL register field. */
14545 #define ALT_PINMUX_FPGA_EMAC2_USEFPGA_SEL_RESET 0x0
14546 /* Extracts the ALT_PINMUX_FPGA_EMAC2_USEFPGA_SEL field value from a register. */
14547 #define ALT_PINMUX_FPGA_EMAC2_USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
14548 /* Produces a ALT_PINMUX_FPGA_EMAC2_USEFPGA_SEL register field value suitable for setting the register. */
14549 #define ALT_PINMUX_FPGA_EMAC2_USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
14550 
14551 /*
14552  * Field : Reserved
14553  *
14554  * Reserved
14555  *
14556  * Field Access Macros:
14557  *
14558  */
14559 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_EMAC2_USEFPGA_RSVD register field. */
14560 #define ALT_PINMUX_FPGA_EMAC2_USEFPGA_RSVD_LSB 1
14561 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_EMAC2_USEFPGA_RSVD register field. */
14562 #define ALT_PINMUX_FPGA_EMAC2_USEFPGA_RSVD_MSB 31
14563 /* The width in bits of the ALT_PINMUX_FPGA_EMAC2_USEFPGA_RSVD register field. */
14564 #define ALT_PINMUX_FPGA_EMAC2_USEFPGA_RSVD_WIDTH 31
14565 /* The mask used to set the ALT_PINMUX_FPGA_EMAC2_USEFPGA_RSVD register field value. */
14566 #define ALT_PINMUX_FPGA_EMAC2_USEFPGA_RSVD_SET_MSK 0xfffffffe
14567 /* The mask used to clear the ALT_PINMUX_FPGA_EMAC2_USEFPGA_RSVD register field value. */
14568 #define ALT_PINMUX_FPGA_EMAC2_USEFPGA_RSVD_CLR_MSK 0x00000001
14569 /* The reset value of the ALT_PINMUX_FPGA_EMAC2_USEFPGA_RSVD register field. */
14570 #define ALT_PINMUX_FPGA_EMAC2_USEFPGA_RSVD_RESET 0x0
14571 /* Extracts the ALT_PINMUX_FPGA_EMAC2_USEFPGA_RSVD field value from a register. */
14572 #define ALT_PINMUX_FPGA_EMAC2_USEFPGA_RSVD_GET(value) (((value) & 0xfffffffe) >> 1)
14573 /* Produces a ALT_PINMUX_FPGA_EMAC2_USEFPGA_RSVD register field value suitable for setting the register. */
14574 #define ALT_PINMUX_FPGA_EMAC2_USEFPGA_RSVD_SET(value) (((value) << 1) & 0xfffffffe)
14575 
14576 #ifndef __ASSEMBLY__
14577 /*
14578  * WARNING: The C register and register group struct declarations are provided for
14579  * convenience and illustrative purposes. They should, however, be used with
14580  * caution as the C language standard provides no guarantees about the alignment or
14581  * atomicity of device memory accesses. The recommended practice for writing
14582  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14583  * alt_write_word() functions.
14584  *
14585  * The struct declaration for register ALT_PINMUX_FPGA_EMAC2_USEFPGA.
14586  */
14587 struct ALT_PINMUX_FPGA_EMAC2_USEFPGA_s
14588 {
14589  uint32_t sel : 1; /* Selection for EMAC2 signals */
14590  const uint32_t Reserved : 31; /* ALT_PINMUX_FPGA_EMAC2_USEFPGA_RSVD */
14591 };
14592 
14593 /* The typedef declaration for register ALT_PINMUX_FPGA_EMAC2_USEFPGA. */
14594 typedef volatile struct ALT_PINMUX_FPGA_EMAC2_USEFPGA_s ALT_PINMUX_FPGA_EMAC2_USEFPGA_t;
14595 #endif /* __ASSEMBLY__ */
14596 
14597 /* The reset value of the ALT_PINMUX_FPGA_EMAC2_USEFPGA register. */
14598 #define ALT_PINMUX_FPGA_EMAC2_USEFPGA_RESET 0x00000000
14599 /* The byte offset of the ALT_PINMUX_FPGA_EMAC2_USEFPGA register from the beginning of the component. */
14600 #define ALT_PINMUX_FPGA_EMAC2_USEFPGA_OFST 0x8
14601 
14602 /*
14603  * Register : Select source for I2C0 signals (HPS Pins or FPGA Interface) - pinmux_i2c0_usefpga
14604  *
14605  * Selection between HPS Pin and FPGA Interface for I2C0 signals
14606  *
14607  * Only reset by a cold reset (ignores warm reset).
14608  *
14609  * NOTE: These registers should not be modified after IO configuration.There is no
14610  * support for dynamically changing the Pin Mux selections.
14611  *
14612  * Register Layout
14613  *
14614  * Bits | Access | Reset | Description
14615  * :-------|:-------|:------|:----------------------------------
14616  * [0] | RW | 0x0 | Selection for I2C0 signals
14617  * [31:1] | R | 0x0 | ALT_PINMUX_FPGA_I2C0_USEFPGA_RSVD
14618  *
14619  */
14620 /*
14621  * Field : Selection for I2C0 signals - sel
14622  *
14623  * Select connection for I2C0.
14624  *
14625  * 0 : I2C0 uses HPS IO Pins.
14626  *
14627  * 1 : I2C0 uses the FPGA Inteface.
14628  *
14629  * Field Access Macros:
14630  *
14631  */
14632 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_I2C0_USEFPGA_SEL register field. */
14633 #define ALT_PINMUX_FPGA_I2C0_USEFPGA_SEL_LSB 0
14634 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_I2C0_USEFPGA_SEL register field. */
14635 #define ALT_PINMUX_FPGA_I2C0_USEFPGA_SEL_MSB 0
14636 /* The width in bits of the ALT_PINMUX_FPGA_I2C0_USEFPGA_SEL register field. */
14637 #define ALT_PINMUX_FPGA_I2C0_USEFPGA_SEL_WIDTH 1
14638 /* The mask used to set the ALT_PINMUX_FPGA_I2C0_USEFPGA_SEL register field value. */
14639 #define ALT_PINMUX_FPGA_I2C0_USEFPGA_SEL_SET_MSK 0x00000001
14640 /* The mask used to clear the ALT_PINMUX_FPGA_I2C0_USEFPGA_SEL register field value. */
14641 #define ALT_PINMUX_FPGA_I2C0_USEFPGA_SEL_CLR_MSK 0xfffffffe
14642 /* The reset value of the ALT_PINMUX_FPGA_I2C0_USEFPGA_SEL register field. */
14643 #define ALT_PINMUX_FPGA_I2C0_USEFPGA_SEL_RESET 0x0
14644 /* Extracts the ALT_PINMUX_FPGA_I2C0_USEFPGA_SEL field value from a register. */
14645 #define ALT_PINMUX_FPGA_I2C0_USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
14646 /* Produces a ALT_PINMUX_FPGA_I2C0_USEFPGA_SEL register field value suitable for setting the register. */
14647 #define ALT_PINMUX_FPGA_I2C0_USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
14648 
14649 /*
14650  * Field : Reserved
14651  *
14652  * Reserved
14653  *
14654  * Field Access Macros:
14655  *
14656  */
14657 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_I2C0_USEFPGA_RSVD register field. */
14658 #define ALT_PINMUX_FPGA_I2C0_USEFPGA_RSVD_LSB 1
14659 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_I2C0_USEFPGA_RSVD register field. */
14660 #define ALT_PINMUX_FPGA_I2C0_USEFPGA_RSVD_MSB 31
14661 /* The width in bits of the ALT_PINMUX_FPGA_I2C0_USEFPGA_RSVD register field. */
14662 #define ALT_PINMUX_FPGA_I2C0_USEFPGA_RSVD_WIDTH 31
14663 /* The mask used to set the ALT_PINMUX_FPGA_I2C0_USEFPGA_RSVD register field value. */
14664 #define ALT_PINMUX_FPGA_I2C0_USEFPGA_RSVD_SET_MSK 0xfffffffe
14665 /* The mask used to clear the ALT_PINMUX_FPGA_I2C0_USEFPGA_RSVD register field value. */
14666 #define ALT_PINMUX_FPGA_I2C0_USEFPGA_RSVD_CLR_MSK 0x00000001
14667 /* The reset value of the ALT_PINMUX_FPGA_I2C0_USEFPGA_RSVD register field. */
14668 #define ALT_PINMUX_FPGA_I2C0_USEFPGA_RSVD_RESET 0x0
14669 /* Extracts the ALT_PINMUX_FPGA_I2C0_USEFPGA_RSVD field value from a register. */
14670 #define ALT_PINMUX_FPGA_I2C0_USEFPGA_RSVD_GET(value) (((value) & 0xfffffffe) >> 1)
14671 /* Produces a ALT_PINMUX_FPGA_I2C0_USEFPGA_RSVD register field value suitable for setting the register. */
14672 #define ALT_PINMUX_FPGA_I2C0_USEFPGA_RSVD_SET(value) (((value) << 1) & 0xfffffffe)
14673 
14674 #ifndef __ASSEMBLY__
14675 /*
14676  * WARNING: The C register and register group struct declarations are provided for
14677  * convenience and illustrative purposes. They should, however, be used with
14678  * caution as the C language standard provides no guarantees about the alignment or
14679  * atomicity of device memory accesses. The recommended practice for writing
14680  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14681  * alt_write_word() functions.
14682  *
14683  * The struct declaration for register ALT_PINMUX_FPGA_I2C0_USEFPGA.
14684  */
14685 struct ALT_PINMUX_FPGA_I2C0_USEFPGA_s
14686 {
14687  uint32_t sel : 1; /* Selection for I2C0 signals */
14688  const uint32_t Reserved : 31; /* ALT_PINMUX_FPGA_I2C0_USEFPGA_RSVD */
14689 };
14690 
14691 /* The typedef declaration for register ALT_PINMUX_FPGA_I2C0_USEFPGA. */
14692 typedef volatile struct ALT_PINMUX_FPGA_I2C0_USEFPGA_s ALT_PINMUX_FPGA_I2C0_USEFPGA_t;
14693 #endif /* __ASSEMBLY__ */
14694 
14695 /* The reset value of the ALT_PINMUX_FPGA_I2C0_USEFPGA register. */
14696 #define ALT_PINMUX_FPGA_I2C0_USEFPGA_RESET 0x00000000
14697 /* The byte offset of the ALT_PINMUX_FPGA_I2C0_USEFPGA register from the beginning of the component. */
14698 #define ALT_PINMUX_FPGA_I2C0_USEFPGA_OFST 0xc
14699 
14700 /*
14701  * Register : Select source for I2C1 signals (HPS Pins or FPGA Interface) - pinmux_i2c1_usefpga
14702  *
14703  * Selection between HPS Pin and FPGA Interface for I2C1 signals
14704  *
14705  * Only reset by a cold reset (ignores warm reset).
14706  *
14707  * NOTE: These registers should not be modified after IO configuration.There is no
14708  * support for dynamically changing the Pin Mux selections.
14709  *
14710  * Register Layout
14711  *
14712  * Bits | Access | Reset | Description
14713  * :-------|:-------|:------|:----------------------------------
14714  * [0] | RW | 0x0 | Selection for I2C1 signals
14715  * [31:1] | R | 0x0 | ALT_PINMUX_FPGA_I2C1_USEFPGA_RSVD
14716  *
14717  */
14718 /*
14719  * Field : Selection for I2C1 signals - sel
14720  *
14721  * Select connection for I2C1.
14722  *
14723  * 0 : I2C1 uses HPS IO Pins.
14724  *
14725  * 1 : I2C1 uses the FPGA Inteface.
14726  *
14727  * Field Access Macros:
14728  *
14729  */
14730 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_I2C1_USEFPGA_SEL register field. */
14731 #define ALT_PINMUX_FPGA_I2C1_USEFPGA_SEL_LSB 0
14732 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_I2C1_USEFPGA_SEL register field. */
14733 #define ALT_PINMUX_FPGA_I2C1_USEFPGA_SEL_MSB 0
14734 /* The width in bits of the ALT_PINMUX_FPGA_I2C1_USEFPGA_SEL register field. */
14735 #define ALT_PINMUX_FPGA_I2C1_USEFPGA_SEL_WIDTH 1
14736 /* The mask used to set the ALT_PINMUX_FPGA_I2C1_USEFPGA_SEL register field value. */
14737 #define ALT_PINMUX_FPGA_I2C1_USEFPGA_SEL_SET_MSK 0x00000001
14738 /* The mask used to clear the ALT_PINMUX_FPGA_I2C1_USEFPGA_SEL register field value. */
14739 #define ALT_PINMUX_FPGA_I2C1_USEFPGA_SEL_CLR_MSK 0xfffffffe
14740 /* The reset value of the ALT_PINMUX_FPGA_I2C1_USEFPGA_SEL register field. */
14741 #define ALT_PINMUX_FPGA_I2C1_USEFPGA_SEL_RESET 0x0
14742 /* Extracts the ALT_PINMUX_FPGA_I2C1_USEFPGA_SEL field value from a register. */
14743 #define ALT_PINMUX_FPGA_I2C1_USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
14744 /* Produces a ALT_PINMUX_FPGA_I2C1_USEFPGA_SEL register field value suitable for setting the register. */
14745 #define ALT_PINMUX_FPGA_I2C1_USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
14746 
14747 /*
14748  * Field : Reserved
14749  *
14750  * Reserved
14751  *
14752  * Field Access Macros:
14753  *
14754  */
14755 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_I2C1_USEFPGA_RSVD register field. */
14756 #define ALT_PINMUX_FPGA_I2C1_USEFPGA_RSVD_LSB 1
14757 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_I2C1_USEFPGA_RSVD register field. */
14758 #define ALT_PINMUX_FPGA_I2C1_USEFPGA_RSVD_MSB 31
14759 /* The width in bits of the ALT_PINMUX_FPGA_I2C1_USEFPGA_RSVD register field. */
14760 #define ALT_PINMUX_FPGA_I2C1_USEFPGA_RSVD_WIDTH 31
14761 /* The mask used to set the ALT_PINMUX_FPGA_I2C1_USEFPGA_RSVD register field value. */
14762 #define ALT_PINMUX_FPGA_I2C1_USEFPGA_RSVD_SET_MSK 0xfffffffe
14763 /* The mask used to clear the ALT_PINMUX_FPGA_I2C1_USEFPGA_RSVD register field value. */
14764 #define ALT_PINMUX_FPGA_I2C1_USEFPGA_RSVD_CLR_MSK 0x00000001
14765 /* The reset value of the ALT_PINMUX_FPGA_I2C1_USEFPGA_RSVD register field. */
14766 #define ALT_PINMUX_FPGA_I2C1_USEFPGA_RSVD_RESET 0x0
14767 /* Extracts the ALT_PINMUX_FPGA_I2C1_USEFPGA_RSVD field value from a register. */
14768 #define ALT_PINMUX_FPGA_I2C1_USEFPGA_RSVD_GET(value) (((value) & 0xfffffffe) >> 1)
14769 /* Produces a ALT_PINMUX_FPGA_I2C1_USEFPGA_RSVD register field value suitable for setting the register. */
14770 #define ALT_PINMUX_FPGA_I2C1_USEFPGA_RSVD_SET(value) (((value) << 1) & 0xfffffffe)
14771 
14772 #ifndef __ASSEMBLY__
14773 /*
14774  * WARNING: The C register and register group struct declarations are provided for
14775  * convenience and illustrative purposes. They should, however, be used with
14776  * caution as the C language standard provides no guarantees about the alignment or
14777  * atomicity of device memory accesses. The recommended practice for writing
14778  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14779  * alt_write_word() functions.
14780  *
14781  * The struct declaration for register ALT_PINMUX_FPGA_I2C1_USEFPGA.
14782  */
14783 struct ALT_PINMUX_FPGA_I2C1_USEFPGA_s
14784 {
14785  uint32_t sel : 1; /* Selection for I2C1 signals */
14786  const uint32_t Reserved : 31; /* ALT_PINMUX_FPGA_I2C1_USEFPGA_RSVD */
14787 };
14788 
14789 /* The typedef declaration for register ALT_PINMUX_FPGA_I2C1_USEFPGA. */
14790 typedef volatile struct ALT_PINMUX_FPGA_I2C1_USEFPGA_s ALT_PINMUX_FPGA_I2C1_USEFPGA_t;
14791 #endif /* __ASSEMBLY__ */
14792 
14793 /* The reset value of the ALT_PINMUX_FPGA_I2C1_USEFPGA register. */
14794 #define ALT_PINMUX_FPGA_I2C1_USEFPGA_RESET 0x00000000
14795 /* The byte offset of the ALT_PINMUX_FPGA_I2C1_USEFPGA register from the beginning of the component. */
14796 #define ALT_PINMUX_FPGA_I2C1_USEFPGA_OFST 0x10
14797 
14798 /*
14799  * Register : Select source for I2C_EMAC0 signals (HPS Pins or FPGA Interface) - pinmux_i2c_emac0_usefpga
14800  *
14801  * Selection between HPS Pin and FPGA Interface for I2C_EMAC0 signals
14802  *
14803  * Only reset by a cold reset (ignores warm reset).
14804  *
14805  * NOTE: These registers should not be modified after IO configuration.There is no
14806  * support for dynamically changing the Pin Mux selections.
14807  *
14808  * Register Layout
14809  *
14810  * Bits | Access | Reset | Description
14811  * :-------|:-------|:------|:---------------------------------------
14812  * [0] | RW | 0x0 | Selection for I2C_EMAC0 signals
14813  * [31:1] | R | 0x0 | ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_RSVD
14814  *
14815  */
14816 /*
14817  * Field : Selection for I2C_EMAC0 signals - sel
14818  *
14819  * Select connection for I2C_EMAC0.
14820  *
14821  * 0 : I2C_EMAC0 uses HPS IO Pins.
14822  *
14823  * 1 : I2C_EMAC0 uses the FPGA Inteface.
14824  *
14825  * Field Access Macros:
14826  *
14827  */
14828 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_SEL register field. */
14829 #define ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_SEL_LSB 0
14830 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_SEL register field. */
14831 #define ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_SEL_MSB 0
14832 /* The width in bits of the ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_SEL register field. */
14833 #define ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_SEL_WIDTH 1
14834 /* The mask used to set the ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_SEL register field value. */
14835 #define ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_SEL_SET_MSK 0x00000001
14836 /* The mask used to clear the ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_SEL register field value. */
14837 #define ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_SEL_CLR_MSK 0xfffffffe
14838 /* The reset value of the ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_SEL register field. */
14839 #define ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_SEL_RESET 0x0
14840 /* Extracts the ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_SEL field value from a register. */
14841 #define ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
14842 /* Produces a ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_SEL register field value suitable for setting the register. */
14843 #define ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
14844 
14845 /*
14846  * Field : Reserved
14847  *
14848  * Reserved
14849  *
14850  * Field Access Macros:
14851  *
14852  */
14853 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_RSVD register field. */
14854 #define ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_RSVD_LSB 1
14855 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_RSVD register field. */
14856 #define ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_RSVD_MSB 31
14857 /* The width in bits of the ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_RSVD register field. */
14858 #define ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_RSVD_WIDTH 31
14859 /* The mask used to set the ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_RSVD register field value. */
14860 #define ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_RSVD_SET_MSK 0xfffffffe
14861 /* The mask used to clear the ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_RSVD register field value. */
14862 #define ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_RSVD_CLR_MSK 0x00000001
14863 /* The reset value of the ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_RSVD register field. */
14864 #define ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_RSVD_RESET 0x0
14865 /* Extracts the ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_RSVD field value from a register. */
14866 #define ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_RSVD_GET(value) (((value) & 0xfffffffe) >> 1)
14867 /* Produces a ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_RSVD register field value suitable for setting the register. */
14868 #define ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_RSVD_SET(value) (((value) << 1) & 0xfffffffe)
14869 
14870 #ifndef __ASSEMBLY__
14871 /*
14872  * WARNING: The C register and register group struct declarations are provided for
14873  * convenience and illustrative purposes. They should, however, be used with
14874  * caution as the C language standard provides no guarantees about the alignment or
14875  * atomicity of device memory accesses. The recommended practice for writing
14876  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14877  * alt_write_word() functions.
14878  *
14879  * The struct declaration for register ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA.
14880  */
14881 struct ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_s
14882 {
14883  uint32_t sel : 1; /* Selection for I2C_EMAC0 signals */
14884  const uint32_t Reserved : 31; /* ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_RSVD */
14885 };
14886 
14887 /* The typedef declaration for register ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA. */
14888 typedef volatile struct ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_s ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_t;
14889 #endif /* __ASSEMBLY__ */
14890 
14891 /* The reset value of the ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA register. */
14892 #define ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_RESET 0x00000000
14893 /* The byte offset of the ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA register from the beginning of the component. */
14894 #define ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_OFST 0x14
14895 
14896 /*
14897  * Register : Select source for I2C_EMAC1 signals (HPS Pins or FPGA Interface) - pinmux_i2c_emac1_usefpga
14898  *
14899  * Selection between HPS Pin and FPGA Interface for I2C_EMAC1 signals
14900  *
14901  * Only reset by a cold reset (ignores warm reset).
14902  *
14903  * NOTE: These registers should not be modified after IO configuration.There is no
14904  * support for dynamically changing the Pin Mux selections.
14905  *
14906  * Register Layout
14907  *
14908  * Bits | Access | Reset | Description
14909  * :-------|:-------|:------|:---------------------------------------
14910  * [0] | RW | 0x0 | Selection for I2C_EMAC1 signals
14911  * [31:1] | R | 0x0 | ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_RSVD
14912  *
14913  */
14914 /*
14915  * Field : Selection for I2C_EMAC1 signals - sel
14916  *
14917  * Select connection for I2C_EMAC1.
14918  *
14919  * 0 : I2C_EMAC1 uses HPS IO Pins.
14920  *
14921  * 1 : I2C_EMAC1 uses the FPGA Inteface.
14922  *
14923  * Field Access Macros:
14924  *
14925  */
14926 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_SEL register field. */
14927 #define ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_SEL_LSB 0
14928 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_SEL register field. */
14929 #define ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_SEL_MSB 0
14930 /* The width in bits of the ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_SEL register field. */
14931 #define ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_SEL_WIDTH 1
14932 /* The mask used to set the ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_SEL register field value. */
14933 #define ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_SEL_SET_MSK 0x00000001
14934 /* The mask used to clear the ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_SEL register field value. */
14935 #define ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_SEL_CLR_MSK 0xfffffffe
14936 /* The reset value of the ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_SEL register field. */
14937 #define ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_SEL_RESET 0x0
14938 /* Extracts the ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_SEL field value from a register. */
14939 #define ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
14940 /* Produces a ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_SEL register field value suitable for setting the register. */
14941 #define ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
14942 
14943 /*
14944  * Field : Reserved
14945  *
14946  * Reserved
14947  *
14948  * Field Access Macros:
14949  *
14950  */
14951 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_RSVD register field. */
14952 #define ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_RSVD_LSB 1
14953 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_RSVD register field. */
14954 #define ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_RSVD_MSB 31
14955 /* The width in bits of the ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_RSVD register field. */
14956 #define ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_RSVD_WIDTH 31
14957 /* The mask used to set the ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_RSVD register field value. */
14958 #define ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_RSVD_SET_MSK 0xfffffffe
14959 /* The mask used to clear the ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_RSVD register field value. */
14960 #define ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_RSVD_CLR_MSK 0x00000001
14961 /* The reset value of the ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_RSVD register field. */
14962 #define ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_RSVD_RESET 0x0
14963 /* Extracts the ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_RSVD field value from a register. */
14964 #define ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_RSVD_GET(value) (((value) & 0xfffffffe) >> 1)
14965 /* Produces a ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_RSVD register field value suitable for setting the register. */
14966 #define ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_RSVD_SET(value) (((value) << 1) & 0xfffffffe)
14967 
14968 #ifndef __ASSEMBLY__
14969 /*
14970  * WARNING: The C register and register group struct declarations are provided for
14971  * convenience and illustrative purposes. They should, however, be used with
14972  * caution as the C language standard provides no guarantees about the alignment or
14973  * atomicity of device memory accesses. The recommended practice for writing
14974  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14975  * alt_write_word() functions.
14976  *
14977  * The struct declaration for register ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA.
14978  */
14979 struct ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_s
14980 {
14981  uint32_t sel : 1; /* Selection for I2C_EMAC1 signals */
14982  const uint32_t Reserved : 31; /* ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_RSVD */
14983 };
14984 
14985 /* The typedef declaration for register ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA. */
14986 typedef volatile struct ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_s ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_t;
14987 #endif /* __ASSEMBLY__ */
14988 
14989 /* The reset value of the ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA register. */
14990 #define ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_RESET 0x00000000
14991 /* The byte offset of the ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA register from the beginning of the component. */
14992 #define ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_OFST 0x18
14993 
14994 /*
14995  * Register : Select source for I2C_EMAC2 signals (HPS Pins or FPGA Interface) - pinmux_i2c_emac2_usefpga
14996  *
14997  * Selection between HPS Pin and FPGA Interface for I2C_EMAC2 signals
14998  *
14999  * Only reset by a cold reset (ignores warm reset).
15000  *
15001  * NOTE: These registers should not be modified after IO configuration.There is no
15002  * support for dynamically changing the Pin Mux selections.
15003  *
15004  * Register Layout
15005  *
15006  * Bits | Access | Reset | Description
15007  * :-------|:-------|:------|:---------------------------------------
15008  * [0] | RW | 0x0 | Selection for I2C_EMAC2 signals
15009  * [31:1] | R | 0x0 | ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_RSVD
15010  *
15011  */
15012 /*
15013  * Field : Selection for I2C_EMAC2 signals - sel
15014  *
15015  * Select connection for I2C_EMAC2.
15016  *
15017  * 0 : I2C_EMAC2 uses HPS IO Pins.
15018  *
15019  * 1 : I2C_EMAC2 uses the FPGA Inteface.
15020  *
15021  * Field Access Macros:
15022  *
15023  */
15024 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_SEL register field. */
15025 #define ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_SEL_LSB 0
15026 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_SEL register field. */
15027 #define ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_SEL_MSB 0
15028 /* The width in bits of the ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_SEL register field. */
15029 #define ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_SEL_WIDTH 1
15030 /* The mask used to set the ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_SEL register field value. */
15031 #define ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_SEL_SET_MSK 0x00000001
15032 /* The mask used to clear the ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_SEL register field value. */
15033 #define ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_SEL_CLR_MSK 0xfffffffe
15034 /* The reset value of the ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_SEL register field. */
15035 #define ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_SEL_RESET 0x0
15036 /* Extracts the ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_SEL field value from a register. */
15037 #define ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
15038 /* Produces a ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_SEL register field value suitable for setting the register. */
15039 #define ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
15040 
15041 /*
15042  * Field : Reserved
15043  *
15044  * Reserved
15045  *
15046  * Field Access Macros:
15047  *
15048  */
15049 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_RSVD register field. */
15050 #define ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_RSVD_LSB 1
15051 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_RSVD register field. */
15052 #define ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_RSVD_MSB 31
15053 /* The width in bits of the ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_RSVD register field. */
15054 #define ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_RSVD_WIDTH 31
15055 /* The mask used to set the ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_RSVD register field value. */
15056 #define ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_RSVD_SET_MSK 0xfffffffe
15057 /* The mask used to clear the ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_RSVD register field value. */
15058 #define ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_RSVD_CLR_MSK 0x00000001
15059 /* The reset value of the ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_RSVD register field. */
15060 #define ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_RSVD_RESET 0x0
15061 /* Extracts the ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_RSVD field value from a register. */
15062 #define ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_RSVD_GET(value) (((value) & 0xfffffffe) >> 1)
15063 /* Produces a ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_RSVD register field value suitable for setting the register. */
15064 #define ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_RSVD_SET(value) (((value) << 1) & 0xfffffffe)
15065 
15066 #ifndef __ASSEMBLY__
15067 /*
15068  * WARNING: The C register and register group struct declarations are provided for
15069  * convenience and illustrative purposes. They should, however, be used with
15070  * caution as the C language standard provides no guarantees about the alignment or
15071  * atomicity of device memory accesses. The recommended practice for writing
15072  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15073  * alt_write_word() functions.
15074  *
15075  * The struct declaration for register ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA.
15076  */
15077 struct ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_s
15078 {
15079  uint32_t sel : 1; /* Selection for I2C_EMAC2 signals */
15080  const uint32_t Reserved : 31; /* ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_RSVD */
15081 };
15082 
15083 /* The typedef declaration for register ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA. */
15084 typedef volatile struct ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_s ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_t;
15085 #endif /* __ASSEMBLY__ */
15086 
15087 /* The reset value of the ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA register. */
15088 #define ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_RESET 0x00000000
15089 /* The byte offset of the ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA register from the beginning of the component. */
15090 #define ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_OFST 0x1c
15091 
15092 /*
15093  * Register : Select source for NAND signals (HPS Pins or FPGA Interface) - pinmux_nand_usefpga
15094  *
15095  * Selection between HPS Pin and FPGA Interface for NAND signals
15096  *
15097  * Only reset by a cold reset (ignores warm reset).
15098  *
15099  * NOTE: These registers should not be modified after IO configuration.There is no
15100  * support for dynamically changing the Pin Mux selections.
15101  *
15102  * Register Layout
15103  *
15104  * Bits | Access | Reset | Description
15105  * :-------|:-------|:------|:----------------------------------
15106  * [0] | RW | 0x0 | Selection for NAND signals
15107  * [31:1] | R | 0x0 | ALT_PINMUX_FPGA_NAND_USEFPGA_RSVD
15108  *
15109  */
15110 /*
15111  * Field : Selection for NAND signals - sel
15112  *
15113  * Select connection for NAND.
15114  *
15115  * 0 : NAND uses HPS IO Pins.
15116  *
15117  * 1 : NAND uses the FPGA Inteface.
15118  *
15119  * Field Access Macros:
15120  *
15121  */
15122 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_NAND_USEFPGA_SEL register field. */
15123 #define ALT_PINMUX_FPGA_NAND_USEFPGA_SEL_LSB 0
15124 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_NAND_USEFPGA_SEL register field. */
15125 #define ALT_PINMUX_FPGA_NAND_USEFPGA_SEL_MSB 0
15126 /* The width in bits of the ALT_PINMUX_FPGA_NAND_USEFPGA_SEL register field. */
15127 #define ALT_PINMUX_FPGA_NAND_USEFPGA_SEL_WIDTH 1
15128 /* The mask used to set the ALT_PINMUX_FPGA_NAND_USEFPGA_SEL register field value. */
15129 #define ALT_PINMUX_FPGA_NAND_USEFPGA_SEL_SET_MSK 0x00000001
15130 /* The mask used to clear the ALT_PINMUX_FPGA_NAND_USEFPGA_SEL register field value. */
15131 #define ALT_PINMUX_FPGA_NAND_USEFPGA_SEL_CLR_MSK 0xfffffffe
15132 /* The reset value of the ALT_PINMUX_FPGA_NAND_USEFPGA_SEL register field. */
15133 #define ALT_PINMUX_FPGA_NAND_USEFPGA_SEL_RESET 0x0
15134 /* Extracts the ALT_PINMUX_FPGA_NAND_USEFPGA_SEL field value from a register. */
15135 #define ALT_PINMUX_FPGA_NAND_USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
15136 /* Produces a ALT_PINMUX_FPGA_NAND_USEFPGA_SEL register field value suitable for setting the register. */
15137 #define ALT_PINMUX_FPGA_NAND_USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
15138 
15139 /*
15140  * Field : Reserved
15141  *
15142  * Reserved
15143  *
15144  * Field Access Macros:
15145  *
15146  */
15147 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_NAND_USEFPGA_RSVD register field. */
15148 #define ALT_PINMUX_FPGA_NAND_USEFPGA_RSVD_LSB 1
15149 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_NAND_USEFPGA_RSVD register field. */
15150 #define ALT_PINMUX_FPGA_NAND_USEFPGA_RSVD_MSB 31
15151 /* The width in bits of the ALT_PINMUX_FPGA_NAND_USEFPGA_RSVD register field. */
15152 #define ALT_PINMUX_FPGA_NAND_USEFPGA_RSVD_WIDTH 31
15153 /* The mask used to set the ALT_PINMUX_FPGA_NAND_USEFPGA_RSVD register field value. */
15154 #define ALT_PINMUX_FPGA_NAND_USEFPGA_RSVD_SET_MSK 0xfffffffe
15155 /* The mask used to clear the ALT_PINMUX_FPGA_NAND_USEFPGA_RSVD register field value. */
15156 #define ALT_PINMUX_FPGA_NAND_USEFPGA_RSVD_CLR_MSK 0x00000001
15157 /* The reset value of the ALT_PINMUX_FPGA_NAND_USEFPGA_RSVD register field. */
15158 #define ALT_PINMUX_FPGA_NAND_USEFPGA_RSVD_RESET 0x0
15159 /* Extracts the ALT_PINMUX_FPGA_NAND_USEFPGA_RSVD field value from a register. */
15160 #define ALT_PINMUX_FPGA_NAND_USEFPGA_RSVD_GET(value) (((value) & 0xfffffffe) >> 1)
15161 /* Produces a ALT_PINMUX_FPGA_NAND_USEFPGA_RSVD register field value suitable for setting the register. */
15162 #define ALT_PINMUX_FPGA_NAND_USEFPGA_RSVD_SET(value) (((value) << 1) & 0xfffffffe)
15163 
15164 #ifndef __ASSEMBLY__
15165 /*
15166  * WARNING: The C register and register group struct declarations are provided for
15167  * convenience and illustrative purposes. They should, however, be used with
15168  * caution as the C language standard provides no guarantees about the alignment or
15169  * atomicity of device memory accesses. The recommended practice for writing
15170  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15171  * alt_write_word() functions.
15172  *
15173  * The struct declaration for register ALT_PINMUX_FPGA_NAND_USEFPGA.
15174  */
15175 struct ALT_PINMUX_FPGA_NAND_USEFPGA_s
15176 {
15177  uint32_t sel : 1; /* Selection for NAND signals */
15178  const uint32_t Reserved : 31; /* ALT_PINMUX_FPGA_NAND_USEFPGA_RSVD */
15179 };
15180 
15181 /* The typedef declaration for register ALT_PINMUX_FPGA_NAND_USEFPGA. */
15182 typedef volatile struct ALT_PINMUX_FPGA_NAND_USEFPGA_s ALT_PINMUX_FPGA_NAND_USEFPGA_t;
15183 #endif /* __ASSEMBLY__ */
15184 
15185 /* The reset value of the ALT_PINMUX_FPGA_NAND_USEFPGA register. */
15186 #define ALT_PINMUX_FPGA_NAND_USEFPGA_RESET 0x00000000
15187 /* The byte offset of the ALT_PINMUX_FPGA_NAND_USEFPGA register from the beginning of the component. */
15188 #define ALT_PINMUX_FPGA_NAND_USEFPGA_OFST 0x20
15189 
15190 /*
15191  * Register : Select source for QSPI signals (HPS Pins or FPGA Interface) - pinmux_qspi_usefpga
15192  *
15193  * Selection between HPS Pin and FPGA Interface for QSPI signals
15194  *
15195  * Only reset by a cold reset (ignores warm reset).
15196  *
15197  * NOTE: These registers should not be modified after IO configuration.There is no
15198  * support for dynamically changing the Pin Mux selections.
15199  *
15200  * Register Layout
15201  *
15202  * Bits | Access | Reset | Description
15203  * :-------|:-------|:------|:----------------------------------
15204  * [0] | RW | 0x0 | Selection for QSPI signals
15205  * [31:1] | R | 0x0 | ALT_PINMUX_FPGA_QSPI_USEFPGA_RSVD
15206  *
15207  */
15208 /*
15209  * Field : Selection for QSPI signals - sel
15210  *
15211  * Select connection for QSPI.
15212  *
15213  * 0 : QPSI uses HPS IO Pins.
15214  *
15215  * 1 : QSPI uses the FPGA Inteface.
15216  *
15217  * Field Access Macros:
15218  *
15219  */
15220 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_QSPI_USEFPGA_SEL register field. */
15221 #define ALT_PINMUX_FPGA_QSPI_USEFPGA_SEL_LSB 0
15222 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_QSPI_USEFPGA_SEL register field. */
15223 #define ALT_PINMUX_FPGA_QSPI_USEFPGA_SEL_MSB 0
15224 /* The width in bits of the ALT_PINMUX_FPGA_QSPI_USEFPGA_SEL register field. */
15225 #define ALT_PINMUX_FPGA_QSPI_USEFPGA_SEL_WIDTH 1
15226 /* The mask used to set the ALT_PINMUX_FPGA_QSPI_USEFPGA_SEL register field value. */
15227 #define ALT_PINMUX_FPGA_QSPI_USEFPGA_SEL_SET_MSK 0x00000001
15228 /* The mask used to clear the ALT_PINMUX_FPGA_QSPI_USEFPGA_SEL register field value. */
15229 #define ALT_PINMUX_FPGA_QSPI_USEFPGA_SEL_CLR_MSK 0xfffffffe
15230 /* The reset value of the ALT_PINMUX_FPGA_QSPI_USEFPGA_SEL register field. */
15231 #define ALT_PINMUX_FPGA_QSPI_USEFPGA_SEL_RESET 0x0
15232 /* Extracts the ALT_PINMUX_FPGA_QSPI_USEFPGA_SEL field value from a register. */
15233 #define ALT_PINMUX_FPGA_QSPI_USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
15234 /* Produces a ALT_PINMUX_FPGA_QSPI_USEFPGA_SEL register field value suitable for setting the register. */
15235 #define ALT_PINMUX_FPGA_QSPI_USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
15236 
15237 /*
15238  * Field : Reserved
15239  *
15240  * Reserved
15241  *
15242  * Field Access Macros:
15243  *
15244  */
15245 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_QSPI_USEFPGA_RSVD register field. */
15246 #define ALT_PINMUX_FPGA_QSPI_USEFPGA_RSVD_LSB 1
15247 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_QSPI_USEFPGA_RSVD register field. */
15248 #define ALT_PINMUX_FPGA_QSPI_USEFPGA_RSVD_MSB 31
15249 /* The width in bits of the ALT_PINMUX_FPGA_QSPI_USEFPGA_RSVD register field. */
15250 #define ALT_PINMUX_FPGA_QSPI_USEFPGA_RSVD_WIDTH 31
15251 /* The mask used to set the ALT_PINMUX_FPGA_QSPI_USEFPGA_RSVD register field value. */
15252 #define ALT_PINMUX_FPGA_QSPI_USEFPGA_RSVD_SET_MSK 0xfffffffe
15253 /* The mask used to clear the ALT_PINMUX_FPGA_QSPI_USEFPGA_RSVD register field value. */
15254 #define ALT_PINMUX_FPGA_QSPI_USEFPGA_RSVD_CLR_MSK 0x00000001
15255 /* The reset value of the ALT_PINMUX_FPGA_QSPI_USEFPGA_RSVD register field. */
15256 #define ALT_PINMUX_FPGA_QSPI_USEFPGA_RSVD_RESET 0x0
15257 /* Extracts the ALT_PINMUX_FPGA_QSPI_USEFPGA_RSVD field value from a register. */
15258 #define ALT_PINMUX_FPGA_QSPI_USEFPGA_RSVD_GET(value) (((value) & 0xfffffffe) >> 1)
15259 /* Produces a ALT_PINMUX_FPGA_QSPI_USEFPGA_RSVD register field value suitable for setting the register. */
15260 #define ALT_PINMUX_FPGA_QSPI_USEFPGA_RSVD_SET(value) (((value) << 1) & 0xfffffffe)
15261 
15262 #ifndef __ASSEMBLY__
15263 /*
15264  * WARNING: The C register and register group struct declarations are provided for
15265  * convenience and illustrative purposes. They should, however, be used with
15266  * caution as the C language standard provides no guarantees about the alignment or
15267  * atomicity of device memory accesses. The recommended practice for writing
15268  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15269  * alt_write_word() functions.
15270  *
15271  * The struct declaration for register ALT_PINMUX_FPGA_QSPI_USEFPGA.
15272  */
15273 struct ALT_PINMUX_FPGA_QSPI_USEFPGA_s
15274 {
15275  uint32_t sel : 1; /* Selection for QSPI signals */
15276  const uint32_t Reserved : 31; /* ALT_PINMUX_FPGA_QSPI_USEFPGA_RSVD */
15277 };
15278 
15279 /* The typedef declaration for register ALT_PINMUX_FPGA_QSPI_USEFPGA. */
15280 typedef volatile struct ALT_PINMUX_FPGA_QSPI_USEFPGA_s ALT_PINMUX_FPGA_QSPI_USEFPGA_t;
15281 #endif /* __ASSEMBLY__ */
15282 
15283 /* The reset value of the ALT_PINMUX_FPGA_QSPI_USEFPGA register. */
15284 #define ALT_PINMUX_FPGA_QSPI_USEFPGA_RESET 0x00000000
15285 /* The byte offset of the ALT_PINMUX_FPGA_QSPI_USEFPGA register from the beginning of the component. */
15286 #define ALT_PINMUX_FPGA_QSPI_USEFPGA_OFST 0x24
15287 
15288 /*
15289  * Register : Select source for SDMMC signals (HPS Pins or FPGA Interface) - pinmux_sdmmc_usefpga
15290  *
15291  * Selection between HPS Pin and FPGA Interface for SDMMC signals
15292  *
15293  * Only reset by a cold reset (ignores warm reset).
15294  *
15295  * NOTE: These registers should not be modified after IO configuration.There is no
15296  * support for dynamically changing the Pin Mux selections.
15297  *
15298  * Register Layout
15299  *
15300  * Bits | Access | Reset | Description
15301  * :-------|:-------|:------|:-----------------------------------
15302  * [0] | RW | 0x0 | Selection for SDMMC signals
15303  * [31:1] | R | 0x0 | ALT_PINMUX_FPGA_SDMMC_USEFPGA_RSVD
15304  *
15305  */
15306 /*
15307  * Field : Selection for SDMMC signals - sel
15308  *
15309  * Select connection for SDMMC.
15310  *
15311  * 0 : SDMMC uses HPS IO Pins.
15312  *
15313  * 1 : SDMMC uses the FPGA Inteface.
15314  *
15315  * Field Access Macros:
15316  *
15317  */
15318 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_SDMMC_USEFPGA_SEL register field. */
15319 #define ALT_PINMUX_FPGA_SDMMC_USEFPGA_SEL_LSB 0
15320 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_SDMMC_USEFPGA_SEL register field. */
15321 #define ALT_PINMUX_FPGA_SDMMC_USEFPGA_SEL_MSB 0
15322 /* The width in bits of the ALT_PINMUX_FPGA_SDMMC_USEFPGA_SEL register field. */
15323 #define ALT_PINMUX_FPGA_SDMMC_USEFPGA_SEL_WIDTH 1
15324 /* The mask used to set the ALT_PINMUX_FPGA_SDMMC_USEFPGA_SEL register field value. */
15325 #define ALT_PINMUX_FPGA_SDMMC_USEFPGA_SEL_SET_MSK 0x00000001
15326 /* The mask used to clear the ALT_PINMUX_FPGA_SDMMC_USEFPGA_SEL register field value. */
15327 #define ALT_PINMUX_FPGA_SDMMC_USEFPGA_SEL_CLR_MSK 0xfffffffe
15328 /* The reset value of the ALT_PINMUX_FPGA_SDMMC_USEFPGA_SEL register field. */
15329 #define ALT_PINMUX_FPGA_SDMMC_USEFPGA_SEL_RESET 0x0
15330 /* Extracts the ALT_PINMUX_FPGA_SDMMC_USEFPGA_SEL field value from a register. */
15331 #define ALT_PINMUX_FPGA_SDMMC_USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
15332 /* Produces a ALT_PINMUX_FPGA_SDMMC_USEFPGA_SEL register field value suitable for setting the register. */
15333 #define ALT_PINMUX_FPGA_SDMMC_USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
15334 
15335 /*
15336  * Field : Reserved
15337  *
15338  * Reserved
15339  *
15340  * Field Access Macros:
15341  *
15342  */
15343 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_SDMMC_USEFPGA_RSVD register field. */
15344 #define ALT_PINMUX_FPGA_SDMMC_USEFPGA_RSVD_LSB 1
15345 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_SDMMC_USEFPGA_RSVD register field. */
15346 #define ALT_PINMUX_FPGA_SDMMC_USEFPGA_RSVD_MSB 31
15347 /* The width in bits of the ALT_PINMUX_FPGA_SDMMC_USEFPGA_RSVD register field. */
15348 #define ALT_PINMUX_FPGA_SDMMC_USEFPGA_RSVD_WIDTH 31
15349 /* The mask used to set the ALT_PINMUX_FPGA_SDMMC_USEFPGA_RSVD register field value. */
15350 #define ALT_PINMUX_FPGA_SDMMC_USEFPGA_RSVD_SET_MSK 0xfffffffe
15351 /* The mask used to clear the ALT_PINMUX_FPGA_SDMMC_USEFPGA_RSVD register field value. */
15352 #define ALT_PINMUX_FPGA_SDMMC_USEFPGA_RSVD_CLR_MSK 0x00000001
15353 /* The reset value of the ALT_PINMUX_FPGA_SDMMC_USEFPGA_RSVD register field. */
15354 #define ALT_PINMUX_FPGA_SDMMC_USEFPGA_RSVD_RESET 0x0
15355 /* Extracts the ALT_PINMUX_FPGA_SDMMC_USEFPGA_RSVD field value from a register. */
15356 #define ALT_PINMUX_FPGA_SDMMC_USEFPGA_RSVD_GET(value) (((value) & 0xfffffffe) >> 1)
15357 /* Produces a ALT_PINMUX_FPGA_SDMMC_USEFPGA_RSVD register field value suitable for setting the register. */
15358 #define ALT_PINMUX_FPGA_SDMMC_USEFPGA_RSVD_SET(value) (((value) << 1) & 0xfffffffe)
15359 
15360 #ifndef __ASSEMBLY__
15361 /*
15362  * WARNING: The C register and register group struct declarations are provided for
15363  * convenience and illustrative purposes. They should, however, be used with
15364  * caution as the C language standard provides no guarantees about the alignment or
15365  * atomicity of device memory accesses. The recommended practice for writing
15366  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15367  * alt_write_word() functions.
15368  *
15369  * The struct declaration for register ALT_PINMUX_FPGA_SDMMC_USEFPGA.
15370  */
15371 struct ALT_PINMUX_FPGA_SDMMC_USEFPGA_s
15372 {
15373  uint32_t sel : 1; /* Selection for SDMMC signals */
15374  const uint32_t Reserved : 31; /* ALT_PINMUX_FPGA_SDMMC_USEFPGA_RSVD */
15375 };
15376 
15377 /* The typedef declaration for register ALT_PINMUX_FPGA_SDMMC_USEFPGA. */
15378 typedef volatile struct ALT_PINMUX_FPGA_SDMMC_USEFPGA_s ALT_PINMUX_FPGA_SDMMC_USEFPGA_t;
15379 #endif /* __ASSEMBLY__ */
15380 
15381 /* The reset value of the ALT_PINMUX_FPGA_SDMMC_USEFPGA register. */
15382 #define ALT_PINMUX_FPGA_SDMMC_USEFPGA_RESET 0x00000000
15383 /* The byte offset of the ALT_PINMUX_FPGA_SDMMC_USEFPGA register from the beginning of the component. */
15384 #define ALT_PINMUX_FPGA_SDMMC_USEFPGA_OFST 0x28
15385 
15386 /*
15387  * Register : Select source for SPIM0 signals (HPS Pins or FPGA Interface) - pinmux_spim0_usefpga
15388  *
15389  * Selection between HPS Pin and FPGA Interface for SPIM0 signals
15390  *
15391  * Only reset by a cold reset (ignores warm reset).
15392  *
15393  * NOTE: These registers should not be modified after IO configuration.There is no
15394  * support for dynamically changing the Pin Mux selections.
15395  *
15396  * Register Layout
15397  *
15398  * Bits | Access | Reset | Description
15399  * :-------|:-------|:------|:-----------------------------------
15400  * [0] | RW | 0x0 | Selection for SPIM0 signals
15401  * [31:1] | R | 0x0 | ALT_PINMUX_FPGA_SPIM0_USEFPGA_RSVD
15402  *
15403  */
15404 /*
15405  * Field : Selection for SPIM0 signals - sel
15406  *
15407  * Select connection for SPIM0.
15408  *
15409  * 0 : SPIM0 uses HPS IO Pins.
15410  *
15411  * 1 : SPIM0 uses the FPGA Inteface.
15412  *
15413  * Field Access Macros:
15414  *
15415  */
15416 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_SPIM0_USEFPGA_SEL register field. */
15417 #define ALT_PINMUX_FPGA_SPIM0_USEFPGA_SEL_LSB 0
15418 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_SPIM0_USEFPGA_SEL register field. */
15419 #define ALT_PINMUX_FPGA_SPIM0_USEFPGA_SEL_MSB 0
15420 /* The width in bits of the ALT_PINMUX_FPGA_SPIM0_USEFPGA_SEL register field. */
15421 #define ALT_PINMUX_FPGA_SPIM0_USEFPGA_SEL_WIDTH 1
15422 /* The mask used to set the ALT_PINMUX_FPGA_SPIM0_USEFPGA_SEL register field value. */
15423 #define ALT_PINMUX_FPGA_SPIM0_USEFPGA_SEL_SET_MSK 0x00000001
15424 /* The mask used to clear the ALT_PINMUX_FPGA_SPIM0_USEFPGA_SEL register field value. */
15425 #define ALT_PINMUX_FPGA_SPIM0_USEFPGA_SEL_CLR_MSK 0xfffffffe
15426 /* The reset value of the ALT_PINMUX_FPGA_SPIM0_USEFPGA_SEL register field. */
15427 #define ALT_PINMUX_FPGA_SPIM0_USEFPGA_SEL_RESET 0x0
15428 /* Extracts the ALT_PINMUX_FPGA_SPIM0_USEFPGA_SEL field value from a register. */
15429 #define ALT_PINMUX_FPGA_SPIM0_USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
15430 /* Produces a ALT_PINMUX_FPGA_SPIM0_USEFPGA_SEL register field value suitable for setting the register. */
15431 #define ALT_PINMUX_FPGA_SPIM0_USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
15432 
15433 /*
15434  * Field : Reserved
15435  *
15436  * Reserved
15437  *
15438  * Field Access Macros:
15439  *
15440  */
15441 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_SPIM0_USEFPGA_RSVD register field. */
15442 #define ALT_PINMUX_FPGA_SPIM0_USEFPGA_RSVD_LSB 1
15443 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_SPIM0_USEFPGA_RSVD register field. */
15444 #define ALT_PINMUX_FPGA_SPIM0_USEFPGA_RSVD_MSB 31
15445 /* The width in bits of the ALT_PINMUX_FPGA_SPIM0_USEFPGA_RSVD register field. */
15446 #define ALT_PINMUX_FPGA_SPIM0_USEFPGA_RSVD_WIDTH 31
15447 /* The mask used to set the ALT_PINMUX_FPGA_SPIM0_USEFPGA_RSVD register field value. */
15448 #define ALT_PINMUX_FPGA_SPIM0_USEFPGA_RSVD_SET_MSK 0xfffffffe
15449 /* The mask used to clear the ALT_PINMUX_FPGA_SPIM0_USEFPGA_RSVD register field value. */
15450 #define ALT_PINMUX_FPGA_SPIM0_USEFPGA_RSVD_CLR_MSK 0x00000001
15451 /* The reset value of the ALT_PINMUX_FPGA_SPIM0_USEFPGA_RSVD register field. */
15452 #define ALT_PINMUX_FPGA_SPIM0_USEFPGA_RSVD_RESET 0x0
15453 /* Extracts the ALT_PINMUX_FPGA_SPIM0_USEFPGA_RSVD field value from a register. */
15454 #define ALT_PINMUX_FPGA_SPIM0_USEFPGA_RSVD_GET(value) (((value) & 0xfffffffe) >> 1)
15455 /* Produces a ALT_PINMUX_FPGA_SPIM0_USEFPGA_RSVD register field value suitable for setting the register. */
15456 #define ALT_PINMUX_FPGA_SPIM0_USEFPGA_RSVD_SET(value) (((value) << 1) & 0xfffffffe)
15457 
15458 #ifndef __ASSEMBLY__
15459 /*
15460  * WARNING: The C register and register group struct declarations are provided for
15461  * convenience and illustrative purposes. They should, however, be used with
15462  * caution as the C language standard provides no guarantees about the alignment or
15463  * atomicity of device memory accesses. The recommended practice for writing
15464  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15465  * alt_write_word() functions.
15466  *
15467  * The struct declaration for register ALT_PINMUX_FPGA_SPIM0_USEFPGA.
15468  */
15469 struct ALT_PINMUX_FPGA_SPIM0_USEFPGA_s
15470 {
15471  uint32_t sel : 1; /* Selection for SPIM0 signals */
15472  const uint32_t Reserved : 31; /* ALT_PINMUX_FPGA_SPIM0_USEFPGA_RSVD */
15473 };
15474 
15475 /* The typedef declaration for register ALT_PINMUX_FPGA_SPIM0_USEFPGA. */
15476 typedef volatile struct ALT_PINMUX_FPGA_SPIM0_USEFPGA_s ALT_PINMUX_FPGA_SPIM0_USEFPGA_t;
15477 #endif /* __ASSEMBLY__ */
15478 
15479 /* The reset value of the ALT_PINMUX_FPGA_SPIM0_USEFPGA register. */
15480 #define ALT_PINMUX_FPGA_SPIM0_USEFPGA_RESET 0x00000000
15481 /* The byte offset of the ALT_PINMUX_FPGA_SPIM0_USEFPGA register from the beginning of the component. */
15482 #define ALT_PINMUX_FPGA_SPIM0_USEFPGA_OFST 0x2c
15483 
15484 /*
15485  * Register : Select source for SPIM1 signals (HPS Pins or FPGA Interface) - pinmux_spim1_usefpga
15486  *
15487  * Selection between HPS Pin and FPGA Interface for SPIM1 signals
15488  *
15489  * Only reset by a cold reset (ignores warm reset).
15490  *
15491  * NOTE: These registers should not be modified after IO configuration.There is no
15492  * support for dynamically changing the Pin Mux selections.
15493  *
15494  * Register Layout
15495  *
15496  * Bits | Access | Reset | Description
15497  * :-------|:-------|:------|:-----------------------------------
15498  * [0] | RW | 0x0 | Selection for SPIM1 signals
15499  * [31:1] | R | 0x0 | ALT_PINMUX_FPGA_SPIM1_USEFPGA_RSVD
15500  *
15501  */
15502 /*
15503  * Field : Selection for SPIM1 signals - sel
15504  *
15505  * Select connection for SPIM1.
15506  *
15507  * 0 : SPIM1 uses HPS IO Pins.
15508  *
15509  * 1 : SPIM1 uses the FPGA Inteface.
15510  *
15511  * Field Access Macros:
15512  *
15513  */
15514 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_SPIM1_USEFPGA_SEL register field. */
15515 #define ALT_PINMUX_FPGA_SPIM1_USEFPGA_SEL_LSB 0
15516 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_SPIM1_USEFPGA_SEL register field. */
15517 #define ALT_PINMUX_FPGA_SPIM1_USEFPGA_SEL_MSB 0
15518 /* The width in bits of the ALT_PINMUX_FPGA_SPIM1_USEFPGA_SEL register field. */
15519 #define ALT_PINMUX_FPGA_SPIM1_USEFPGA_SEL_WIDTH 1
15520 /* The mask used to set the ALT_PINMUX_FPGA_SPIM1_USEFPGA_SEL register field value. */
15521 #define ALT_PINMUX_FPGA_SPIM1_USEFPGA_SEL_SET_MSK 0x00000001
15522 /* The mask used to clear the ALT_PINMUX_FPGA_SPIM1_USEFPGA_SEL register field value. */
15523 #define ALT_PINMUX_FPGA_SPIM1_USEFPGA_SEL_CLR_MSK 0xfffffffe
15524 /* The reset value of the ALT_PINMUX_FPGA_SPIM1_USEFPGA_SEL register field. */
15525 #define ALT_PINMUX_FPGA_SPIM1_USEFPGA_SEL_RESET 0x0
15526 /* Extracts the ALT_PINMUX_FPGA_SPIM1_USEFPGA_SEL field value from a register. */
15527 #define ALT_PINMUX_FPGA_SPIM1_USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
15528 /* Produces a ALT_PINMUX_FPGA_SPIM1_USEFPGA_SEL register field value suitable for setting the register. */
15529 #define ALT_PINMUX_FPGA_SPIM1_USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
15530 
15531 /*
15532  * Field : Reserved
15533  *
15534  * Reserved
15535  *
15536  * Field Access Macros:
15537  *
15538  */
15539 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_SPIM1_USEFPGA_RSVD register field. */
15540 #define ALT_PINMUX_FPGA_SPIM1_USEFPGA_RSVD_LSB 1
15541 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_SPIM1_USEFPGA_RSVD register field. */
15542 #define ALT_PINMUX_FPGA_SPIM1_USEFPGA_RSVD_MSB 31
15543 /* The width in bits of the ALT_PINMUX_FPGA_SPIM1_USEFPGA_RSVD register field. */
15544 #define ALT_PINMUX_FPGA_SPIM1_USEFPGA_RSVD_WIDTH 31
15545 /* The mask used to set the ALT_PINMUX_FPGA_SPIM1_USEFPGA_RSVD register field value. */
15546 #define ALT_PINMUX_FPGA_SPIM1_USEFPGA_RSVD_SET_MSK 0xfffffffe
15547 /* The mask used to clear the ALT_PINMUX_FPGA_SPIM1_USEFPGA_RSVD register field value. */
15548 #define ALT_PINMUX_FPGA_SPIM1_USEFPGA_RSVD_CLR_MSK 0x00000001
15549 /* The reset value of the ALT_PINMUX_FPGA_SPIM1_USEFPGA_RSVD register field. */
15550 #define ALT_PINMUX_FPGA_SPIM1_USEFPGA_RSVD_RESET 0x0
15551 /* Extracts the ALT_PINMUX_FPGA_SPIM1_USEFPGA_RSVD field value from a register. */
15552 #define ALT_PINMUX_FPGA_SPIM1_USEFPGA_RSVD_GET(value) (((value) & 0xfffffffe) >> 1)
15553 /* Produces a ALT_PINMUX_FPGA_SPIM1_USEFPGA_RSVD register field value suitable for setting the register. */
15554 #define ALT_PINMUX_FPGA_SPIM1_USEFPGA_RSVD_SET(value) (((value) << 1) & 0xfffffffe)
15555 
15556 #ifndef __ASSEMBLY__
15557 /*
15558  * WARNING: The C register and register group struct declarations are provided for
15559  * convenience and illustrative purposes. They should, however, be used with
15560  * caution as the C language standard provides no guarantees about the alignment or
15561  * atomicity of device memory accesses. The recommended practice for writing
15562  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15563  * alt_write_word() functions.
15564  *
15565  * The struct declaration for register ALT_PINMUX_FPGA_SPIM1_USEFPGA.
15566  */
15567 struct ALT_PINMUX_FPGA_SPIM1_USEFPGA_s
15568 {
15569  uint32_t sel : 1; /* Selection for SPIM1 signals */
15570  const uint32_t Reserved : 31; /* ALT_PINMUX_FPGA_SPIM1_USEFPGA_RSVD */
15571 };
15572 
15573 /* The typedef declaration for register ALT_PINMUX_FPGA_SPIM1_USEFPGA. */
15574 typedef volatile struct ALT_PINMUX_FPGA_SPIM1_USEFPGA_s ALT_PINMUX_FPGA_SPIM1_USEFPGA_t;
15575 #endif /* __ASSEMBLY__ */
15576 
15577 /* The reset value of the ALT_PINMUX_FPGA_SPIM1_USEFPGA register. */
15578 #define ALT_PINMUX_FPGA_SPIM1_USEFPGA_RESET 0x00000000
15579 /* The byte offset of the ALT_PINMUX_FPGA_SPIM1_USEFPGA register from the beginning of the component. */
15580 #define ALT_PINMUX_FPGA_SPIM1_USEFPGA_OFST 0x30
15581 
15582 /*
15583  * Register : Select source for SPIS0 signals (HPS Pins or FPGA Interface) - pinmux_spis0_usefpga
15584  *
15585  * Selection between HPS Pin and FPGA Interface for SPIS0 signals
15586  *
15587  * Only reset by a cold reset (ignores warm reset).
15588  *
15589  * NOTE: These registers should not be modified after IO configuration.There is no
15590  * support for dynamically changing the Pin Mux selections.
15591  *
15592  * Register Layout
15593  *
15594  * Bits | Access | Reset | Description
15595  * :-------|:-------|:------|:-----------------------------------
15596  * [0] | RW | 0x0 | Selection for SPIS0 signals
15597  * [31:1] | R | 0x0 | ALT_PINMUX_FPGA_SPIS0_USEFPGA_RSVD
15598  *
15599  */
15600 /*
15601  * Field : Selection for SPIS0 signals - sel
15602  *
15603  * Select connection for SPIS0.
15604  *
15605  * 0 : SPIS0 uses HPS IO Pins.
15606  *
15607  * 1 : SPIS0 uses the FPGA Inteface.
15608  *
15609  * Field Access Macros:
15610  *
15611  */
15612 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_SPIS0_USEFPGA_SEL register field. */
15613 #define ALT_PINMUX_FPGA_SPIS0_USEFPGA_SEL_LSB 0
15614 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_SPIS0_USEFPGA_SEL register field. */
15615 #define ALT_PINMUX_FPGA_SPIS0_USEFPGA_SEL_MSB 0
15616 /* The width in bits of the ALT_PINMUX_FPGA_SPIS0_USEFPGA_SEL register field. */
15617 #define ALT_PINMUX_FPGA_SPIS0_USEFPGA_SEL_WIDTH 1
15618 /* The mask used to set the ALT_PINMUX_FPGA_SPIS0_USEFPGA_SEL register field value. */
15619 #define ALT_PINMUX_FPGA_SPIS0_USEFPGA_SEL_SET_MSK 0x00000001
15620 /* The mask used to clear the ALT_PINMUX_FPGA_SPIS0_USEFPGA_SEL register field value. */
15621 #define ALT_PINMUX_FPGA_SPIS0_USEFPGA_SEL_CLR_MSK 0xfffffffe
15622 /* The reset value of the ALT_PINMUX_FPGA_SPIS0_USEFPGA_SEL register field. */
15623 #define ALT_PINMUX_FPGA_SPIS0_USEFPGA_SEL_RESET 0x0
15624 /* Extracts the ALT_PINMUX_FPGA_SPIS0_USEFPGA_SEL field value from a register. */
15625 #define ALT_PINMUX_FPGA_SPIS0_USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
15626 /* Produces a ALT_PINMUX_FPGA_SPIS0_USEFPGA_SEL register field value suitable for setting the register. */
15627 #define ALT_PINMUX_FPGA_SPIS0_USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
15628 
15629 /*
15630  * Field : Reserved
15631  *
15632  * Reserved
15633  *
15634  * Field Access Macros:
15635  *
15636  */
15637 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_SPIS0_USEFPGA_RSVD register field. */
15638 #define ALT_PINMUX_FPGA_SPIS0_USEFPGA_RSVD_LSB 1
15639 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_SPIS0_USEFPGA_RSVD register field. */
15640 #define ALT_PINMUX_FPGA_SPIS0_USEFPGA_RSVD_MSB 31
15641 /* The width in bits of the ALT_PINMUX_FPGA_SPIS0_USEFPGA_RSVD register field. */
15642 #define ALT_PINMUX_FPGA_SPIS0_USEFPGA_RSVD_WIDTH 31
15643 /* The mask used to set the ALT_PINMUX_FPGA_SPIS0_USEFPGA_RSVD register field value. */
15644 #define ALT_PINMUX_FPGA_SPIS0_USEFPGA_RSVD_SET_MSK 0xfffffffe
15645 /* The mask used to clear the ALT_PINMUX_FPGA_SPIS0_USEFPGA_RSVD register field value. */
15646 #define ALT_PINMUX_FPGA_SPIS0_USEFPGA_RSVD_CLR_MSK 0x00000001
15647 /* The reset value of the ALT_PINMUX_FPGA_SPIS0_USEFPGA_RSVD register field. */
15648 #define ALT_PINMUX_FPGA_SPIS0_USEFPGA_RSVD_RESET 0x0
15649 /* Extracts the ALT_PINMUX_FPGA_SPIS0_USEFPGA_RSVD field value from a register. */
15650 #define ALT_PINMUX_FPGA_SPIS0_USEFPGA_RSVD_GET(value) (((value) & 0xfffffffe) >> 1)
15651 /* Produces a ALT_PINMUX_FPGA_SPIS0_USEFPGA_RSVD register field value suitable for setting the register. */
15652 #define ALT_PINMUX_FPGA_SPIS0_USEFPGA_RSVD_SET(value) (((value) << 1) & 0xfffffffe)
15653 
15654 #ifndef __ASSEMBLY__
15655 /*
15656  * WARNING: The C register and register group struct declarations are provided for
15657  * convenience and illustrative purposes. They should, however, be used with
15658  * caution as the C language standard provides no guarantees about the alignment or
15659  * atomicity of device memory accesses. The recommended practice for writing
15660  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15661  * alt_write_word() functions.
15662  *
15663  * The struct declaration for register ALT_PINMUX_FPGA_SPIS0_USEFPGA.
15664  */
15665 struct ALT_PINMUX_FPGA_SPIS0_USEFPGA_s
15666 {
15667  uint32_t sel : 1; /* Selection for SPIS0 signals */
15668  const uint32_t Reserved : 31; /* ALT_PINMUX_FPGA_SPIS0_USEFPGA_RSVD */
15669 };
15670 
15671 /* The typedef declaration for register ALT_PINMUX_FPGA_SPIS0_USEFPGA. */
15672 typedef volatile struct ALT_PINMUX_FPGA_SPIS0_USEFPGA_s ALT_PINMUX_FPGA_SPIS0_USEFPGA_t;
15673 #endif /* __ASSEMBLY__ */
15674 
15675 /* The reset value of the ALT_PINMUX_FPGA_SPIS0_USEFPGA register. */
15676 #define ALT_PINMUX_FPGA_SPIS0_USEFPGA_RESET 0x00000000
15677 /* The byte offset of the ALT_PINMUX_FPGA_SPIS0_USEFPGA register from the beginning of the component. */
15678 #define ALT_PINMUX_FPGA_SPIS0_USEFPGA_OFST 0x34
15679 
15680 /*
15681  * Register : Select source for SPIS1 signals (HPS Pins or FPGA Interface) - pinmux_spis1_usefpga
15682  *
15683  * Selection between HPS Pin and FPGA Interface for SPIS1 signals
15684  *
15685  * Only reset by a cold reset (ignores warm reset).
15686  *
15687  * NOTE: These registers should not be modified after IO configuration.There is no
15688  * support for dynamically changing the Pin Mux selections.
15689  *
15690  * Register Layout
15691  *
15692  * Bits | Access | Reset | Description
15693  * :-------|:-------|:------|:-----------------------------------
15694  * [0] | RW | 0x0 | Selection for SPIS1 signals
15695  * [31:1] | R | 0x0 | ALT_PINMUX_FPGA_SPIS1_USEFPGA_RSVD
15696  *
15697  */
15698 /*
15699  * Field : Selection for SPIS1 signals - sel
15700  *
15701  * Select connection for SPIS1.
15702  *
15703  * 0 : SPIS1 uses HPS IO Pins.
15704  *
15705  * 1 : SPIS1 uses the FPGA Inteface.
15706  *
15707  * Field Access Macros:
15708  *
15709  */
15710 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_SPIS1_USEFPGA_SEL register field. */
15711 #define ALT_PINMUX_FPGA_SPIS1_USEFPGA_SEL_LSB 0
15712 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_SPIS1_USEFPGA_SEL register field. */
15713 #define ALT_PINMUX_FPGA_SPIS1_USEFPGA_SEL_MSB 0
15714 /* The width in bits of the ALT_PINMUX_FPGA_SPIS1_USEFPGA_SEL register field. */
15715 #define ALT_PINMUX_FPGA_SPIS1_USEFPGA_SEL_WIDTH 1
15716 /* The mask used to set the ALT_PINMUX_FPGA_SPIS1_USEFPGA_SEL register field value. */
15717 #define ALT_PINMUX_FPGA_SPIS1_USEFPGA_SEL_SET_MSK 0x00000001
15718 /* The mask used to clear the ALT_PINMUX_FPGA_SPIS1_USEFPGA_SEL register field value. */
15719 #define ALT_PINMUX_FPGA_SPIS1_USEFPGA_SEL_CLR_MSK 0xfffffffe
15720 /* The reset value of the ALT_PINMUX_FPGA_SPIS1_USEFPGA_SEL register field. */
15721 #define ALT_PINMUX_FPGA_SPIS1_USEFPGA_SEL_RESET 0x0
15722 /* Extracts the ALT_PINMUX_FPGA_SPIS1_USEFPGA_SEL field value from a register. */
15723 #define ALT_PINMUX_FPGA_SPIS1_USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
15724 /* Produces a ALT_PINMUX_FPGA_SPIS1_USEFPGA_SEL register field value suitable for setting the register. */
15725 #define ALT_PINMUX_FPGA_SPIS1_USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
15726 
15727 /*
15728  * Field : Reserved
15729  *
15730  * Reserved
15731  *
15732  * Field Access Macros:
15733  *
15734  */
15735 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_SPIS1_USEFPGA_RSVD register field. */
15736 #define ALT_PINMUX_FPGA_SPIS1_USEFPGA_RSVD_LSB 1
15737 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_SPIS1_USEFPGA_RSVD register field. */
15738 #define ALT_PINMUX_FPGA_SPIS1_USEFPGA_RSVD_MSB 31
15739 /* The width in bits of the ALT_PINMUX_FPGA_SPIS1_USEFPGA_RSVD register field. */
15740 #define ALT_PINMUX_FPGA_SPIS1_USEFPGA_RSVD_WIDTH 31
15741 /* The mask used to set the ALT_PINMUX_FPGA_SPIS1_USEFPGA_RSVD register field value. */
15742 #define ALT_PINMUX_FPGA_SPIS1_USEFPGA_RSVD_SET_MSK 0xfffffffe
15743 /* The mask used to clear the ALT_PINMUX_FPGA_SPIS1_USEFPGA_RSVD register field value. */
15744 #define ALT_PINMUX_FPGA_SPIS1_USEFPGA_RSVD_CLR_MSK 0x00000001
15745 /* The reset value of the ALT_PINMUX_FPGA_SPIS1_USEFPGA_RSVD register field. */
15746 #define ALT_PINMUX_FPGA_SPIS1_USEFPGA_RSVD_RESET 0x0
15747 /* Extracts the ALT_PINMUX_FPGA_SPIS1_USEFPGA_RSVD field value from a register. */
15748 #define ALT_PINMUX_FPGA_SPIS1_USEFPGA_RSVD_GET(value) (((value) & 0xfffffffe) >> 1)
15749 /* Produces a ALT_PINMUX_FPGA_SPIS1_USEFPGA_RSVD register field value suitable for setting the register. */
15750 #define ALT_PINMUX_FPGA_SPIS1_USEFPGA_RSVD_SET(value) (((value) << 1) & 0xfffffffe)
15751 
15752 #ifndef __ASSEMBLY__
15753 /*
15754  * WARNING: The C register and register group struct declarations are provided for
15755  * convenience and illustrative purposes. They should, however, be used with
15756  * caution as the C language standard provides no guarantees about the alignment or
15757  * atomicity of device memory accesses. The recommended practice for writing
15758  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15759  * alt_write_word() functions.
15760  *
15761  * The struct declaration for register ALT_PINMUX_FPGA_SPIS1_USEFPGA.
15762  */
15763 struct ALT_PINMUX_FPGA_SPIS1_USEFPGA_s
15764 {
15765  uint32_t sel : 1; /* Selection for SPIS1 signals */
15766  const uint32_t Reserved : 31; /* ALT_PINMUX_FPGA_SPIS1_USEFPGA_RSVD */
15767 };
15768 
15769 /* The typedef declaration for register ALT_PINMUX_FPGA_SPIS1_USEFPGA. */
15770 typedef volatile struct ALT_PINMUX_FPGA_SPIS1_USEFPGA_s ALT_PINMUX_FPGA_SPIS1_USEFPGA_t;
15771 #endif /* __ASSEMBLY__ */
15772 
15773 /* The reset value of the ALT_PINMUX_FPGA_SPIS1_USEFPGA register. */
15774 #define ALT_PINMUX_FPGA_SPIS1_USEFPGA_RESET 0x00000000
15775 /* The byte offset of the ALT_PINMUX_FPGA_SPIS1_USEFPGA register from the beginning of the component. */
15776 #define ALT_PINMUX_FPGA_SPIS1_USEFPGA_OFST 0x38
15777 
15778 /*
15779  * Register : Select source for UART0 signals (HPS Pins or FPGA Interface) - pinmux_uart0_usefpga
15780  *
15781  * Selection between HPS Pin and FPGA Interface for UART0 signals
15782  *
15783  * Only reset by a cold reset (ignores warm reset).
15784  *
15785  * NOTE: These registers should not be modified after IO configuration.There is no
15786  * support for dynamically changing the Pin Mux selections.
15787  *
15788  * Register Layout
15789  *
15790  * Bits | Access | Reset | Description
15791  * :-------|:-------|:------|:-----------------------------------
15792  * [0] | RW | 0x0 | Selection for UART0 signals
15793  * [31:1] | R | 0x0 | ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD
15794  *
15795  */
15796 /*
15797  * Field : Selection for UART0 signals - sel
15798  *
15799  * Select connection for UART0.
15800  *
15801  * 0 : UART0 uses HPS IO Pins.
15802  *
15803  * 1 : UART0 uses the FPGA Inteface.
15804  *
15805  * Field Access Macros:
15806  *
15807  */
15808 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_UART0_USEFPGA_SEL register field. */
15809 #define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_LSB 0
15810 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_UART0_USEFPGA_SEL register field. */
15811 #define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_MSB 0
15812 /* The width in bits of the ALT_PINMUX_FPGA_UART0_USEFPGA_SEL register field. */
15813 #define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_WIDTH 1
15814 /* The mask used to set the ALT_PINMUX_FPGA_UART0_USEFPGA_SEL register field value. */
15815 #define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_SET_MSK 0x00000001
15816 /* The mask used to clear the ALT_PINMUX_FPGA_UART0_USEFPGA_SEL register field value. */
15817 #define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_CLR_MSK 0xfffffffe
15818 /* The reset value of the ALT_PINMUX_FPGA_UART0_USEFPGA_SEL register field. */
15819 #define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_RESET 0x0
15820 /* Extracts the ALT_PINMUX_FPGA_UART0_USEFPGA_SEL field value from a register. */
15821 #define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
15822 /* Produces a ALT_PINMUX_FPGA_UART0_USEFPGA_SEL register field value suitable for setting the register. */
15823 #define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
15824 
15825 /*
15826  * Field : Reserved
15827  *
15828  * Reserved
15829  *
15830  * Field Access Macros:
15831  *
15832  */
15833 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD register field. */
15834 #define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_LSB 1
15835 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD register field. */
15836 #define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_MSB 31
15837 /* The width in bits of the ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD register field. */
15838 #define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_WIDTH 31
15839 /* The mask used to set the ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD register field value. */
15840 #define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_SET_MSK 0xfffffffe
15841 /* The mask used to clear the ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD register field value. */
15842 #define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_CLR_MSK 0x00000001
15843 /* The reset value of the ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD register field. */
15844 #define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_RESET 0x0
15845 /* Extracts the ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD field value from a register. */
15846 #define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_GET(value) (((value) & 0xfffffffe) >> 1)
15847 /* Produces a ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD register field value suitable for setting the register. */
15848 #define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_SET(value) (((value) << 1) & 0xfffffffe)
15849 
15850 #ifndef __ASSEMBLY__
15851 /*
15852  * WARNING: The C register and register group struct declarations are provided for
15853  * convenience and illustrative purposes. They should, however, be used with
15854  * caution as the C language standard provides no guarantees about the alignment or
15855  * atomicity of device memory accesses. The recommended practice for writing
15856  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15857  * alt_write_word() functions.
15858  *
15859  * The struct declaration for register ALT_PINMUX_FPGA_UART0_USEFPGA.
15860  */
15861 struct ALT_PINMUX_FPGA_UART0_USEFPGA_s
15862 {
15863  uint32_t sel : 1; /* Selection for UART0 signals */
15864  const uint32_t Reserved : 31; /* ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD */
15865 };
15866 
15867 /* The typedef declaration for register ALT_PINMUX_FPGA_UART0_USEFPGA. */
15868 typedef volatile struct ALT_PINMUX_FPGA_UART0_USEFPGA_s ALT_PINMUX_FPGA_UART0_USEFPGA_t;
15869 #endif /* __ASSEMBLY__ */
15870 
15871 /* The reset value of the ALT_PINMUX_FPGA_UART0_USEFPGA register. */
15872 #define ALT_PINMUX_FPGA_UART0_USEFPGA_RESET 0x00000000
15873 /* The byte offset of the ALT_PINMUX_FPGA_UART0_USEFPGA register from the beginning of the component. */
15874 #define ALT_PINMUX_FPGA_UART0_USEFPGA_OFST 0x3c
15875 
15876 /*
15877  * Register : Select source for UART1 signals (HPS Pins or FPGA Interface) - pinmux_uart1_usefpga
15878  *
15879  * Selection between HPS Pin and FPGA Interface for UART1 signals
15880  *
15881  * Only reset by a cold reset (ignores warm reset).
15882  *
15883  * NOTE: These registers should not be modified after IO configuration.There is no
15884  * support for dynamically changing the Pin Mux selections.
15885  *
15886  * Register Layout
15887  *
15888  * Bits | Access | Reset | Description
15889  * :-------|:-------|:------|:-----------------------------------
15890  * [0] | RW | 0x0 | Selection for UART1 signals
15891  * [31:1] | R | 0x0 | ALT_PINMUX_FPGA_UART1_USEFPGA_RSVD
15892  *
15893  */
15894 /*
15895  * Field : Selection for UART1 signals - sel
15896  *
15897  * Select connection for UART1.
15898  *
15899  * 0 : UART1 uses HPS IO Pins.
15900  *
15901  * 1 : UART1 uses the FPGA Inteface.
15902  *
15903  * Field Access Macros:
15904  *
15905  */
15906 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_UART1_USEFPGA_SEL register field. */
15907 #define ALT_PINMUX_FPGA_UART1_USEFPGA_SEL_LSB 0
15908 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_UART1_USEFPGA_SEL register field. */
15909 #define ALT_PINMUX_FPGA_UART1_USEFPGA_SEL_MSB 0
15910 /* The width in bits of the ALT_PINMUX_FPGA_UART1_USEFPGA_SEL register field. */
15911 #define ALT_PINMUX_FPGA_UART1_USEFPGA_SEL_WIDTH 1
15912 /* The mask used to set the ALT_PINMUX_FPGA_UART1_USEFPGA_SEL register field value. */
15913 #define ALT_PINMUX_FPGA_UART1_USEFPGA_SEL_SET_MSK 0x00000001
15914 /* The mask used to clear the ALT_PINMUX_FPGA_UART1_USEFPGA_SEL register field value. */
15915 #define ALT_PINMUX_FPGA_UART1_USEFPGA_SEL_CLR_MSK 0xfffffffe
15916 /* The reset value of the ALT_PINMUX_FPGA_UART1_USEFPGA_SEL register field. */
15917 #define ALT_PINMUX_FPGA_UART1_USEFPGA_SEL_RESET 0x0
15918 /* Extracts the ALT_PINMUX_FPGA_UART1_USEFPGA_SEL field value from a register. */
15919 #define ALT_PINMUX_FPGA_UART1_USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
15920 /* Produces a ALT_PINMUX_FPGA_UART1_USEFPGA_SEL register field value suitable for setting the register. */
15921 #define ALT_PINMUX_FPGA_UART1_USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
15922 
15923 /*
15924  * Field : Reserved
15925  *
15926  * Reserved
15927  *
15928  * Field Access Macros:
15929  *
15930  */
15931 /* The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_UART1_USEFPGA_RSVD register field. */
15932 #define ALT_PINMUX_FPGA_UART1_USEFPGA_RSVD_LSB 1
15933 /* The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_UART1_USEFPGA_RSVD register field. */
15934 #define ALT_PINMUX_FPGA_UART1_USEFPGA_RSVD_MSB 31
15935 /* The width in bits of the ALT_PINMUX_FPGA_UART1_USEFPGA_RSVD register field. */
15936 #define ALT_PINMUX_FPGA_UART1_USEFPGA_RSVD_WIDTH 31
15937 /* The mask used to set the ALT_PINMUX_FPGA_UART1_USEFPGA_RSVD register field value. */
15938 #define ALT_PINMUX_FPGA_UART1_USEFPGA_RSVD_SET_MSK 0xfffffffe
15939 /* The mask used to clear the ALT_PINMUX_FPGA_UART1_USEFPGA_RSVD register field value. */
15940 #define ALT_PINMUX_FPGA_UART1_USEFPGA_RSVD_CLR_MSK 0x00000001
15941 /* The reset value of the ALT_PINMUX_FPGA_UART1_USEFPGA_RSVD register field. */
15942 #define ALT_PINMUX_FPGA_UART1_USEFPGA_RSVD_RESET 0x0
15943 /* Extracts the ALT_PINMUX_FPGA_UART1_USEFPGA_RSVD field value from a register. */
15944 #define ALT_PINMUX_FPGA_UART1_USEFPGA_RSVD_GET(value) (((value) & 0xfffffffe) >> 1)
15945 /* Produces a ALT_PINMUX_FPGA_UART1_USEFPGA_RSVD register field value suitable for setting the register. */
15946 #define ALT_PINMUX_FPGA_UART1_USEFPGA_RSVD_SET(value) (((value) << 1) & 0xfffffffe)
15947 
15948 #ifndef __ASSEMBLY__
15949 /*
15950  * WARNING: The C register and register group struct declarations are provided for
15951  * convenience and illustrative purposes. They should, however, be used with
15952  * caution as the C language standard provides no guarantees about the alignment or
15953  * atomicity of device memory accesses. The recommended practice for writing
15954  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15955  * alt_write_word() functions.
15956  *
15957  * The struct declaration for register ALT_PINMUX_FPGA_UART1_USEFPGA.
15958  */
15959 struct ALT_PINMUX_FPGA_UART1_USEFPGA_s
15960 {
15961  uint32_t sel : 1; /* Selection for UART1 signals */
15962  const uint32_t Reserved : 31; /* ALT_PINMUX_FPGA_UART1_USEFPGA_RSVD */
15963 };
15964 
15965 /* The typedef declaration for register ALT_PINMUX_FPGA_UART1_USEFPGA. */
15966 typedef volatile struct ALT_PINMUX_FPGA_UART1_USEFPGA_s ALT_PINMUX_FPGA_UART1_USEFPGA_t;
15967 #endif /* __ASSEMBLY__ */
15968 
15969 /* The reset value of the ALT_PINMUX_FPGA_UART1_USEFPGA register. */
15970 #define ALT_PINMUX_FPGA_UART1_USEFPGA_RESET 0x00000000
15971 /* The byte offset of the ALT_PINMUX_FPGA_UART1_USEFPGA register from the beginning of the component. */
15972 #define ALT_PINMUX_FPGA_UART1_USEFPGA_OFST 0x40
15973 
15974 #ifndef __ASSEMBLY__
15975 /*
15976  * WARNING: The C register and register group struct declarations are provided for
15977  * convenience and illustrative purposes. They should, however, be used with
15978  * caution as the C language standard provides no guarantees about the alignment or
15979  * atomicity of device memory accesses. The recommended practice for writing
15980  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15981  * alt_write_word() functions.
15982  *
15983  * The struct declaration for register group ALT_PINMUX_FPGA_INTERFACE_GRP.
15984  */
15985 struct ALT_PINMUX_FPGA_INTERFACE_GRP_s
15986 {
15987  ALT_PINMUX_FPGA_EMAC0_USEFPGA_t pinmux_emac0_usefpga; /* ALT_PINMUX_FPGA_EMAC0_USEFPGA */
15988  ALT_PINMUX_FPGA_EMAC1_USEFPGA_t pinmux_emac1_usefpga; /* ALT_PINMUX_FPGA_EMAC1_USEFPGA */
15989  ALT_PINMUX_FPGA_EMAC2_USEFPGA_t pinmux_emac2_usefpga; /* ALT_PINMUX_FPGA_EMAC2_USEFPGA */
15990  ALT_PINMUX_FPGA_I2C0_USEFPGA_t pinmux_i2c0_usefpga; /* ALT_PINMUX_FPGA_I2C0_USEFPGA */
15991  ALT_PINMUX_FPGA_I2C1_USEFPGA_t pinmux_i2c1_usefpga; /* ALT_PINMUX_FPGA_I2C1_USEFPGA */
15992  ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA_t pinmux_i2c_emac0_usefpga; /* ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA */
15993  ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA_t pinmux_i2c_emac1_usefpga; /* ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA */
15994  ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA_t pinmux_i2c_emac2_usefpga; /* ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA */
15995  ALT_PINMUX_FPGA_NAND_USEFPGA_t pinmux_nand_usefpga; /* ALT_PINMUX_FPGA_NAND_USEFPGA */
15996  ALT_PINMUX_FPGA_QSPI_USEFPGA_t pinmux_qspi_usefpga; /* ALT_PINMUX_FPGA_QSPI_USEFPGA */
15997  ALT_PINMUX_FPGA_SDMMC_USEFPGA_t pinmux_sdmmc_usefpga; /* ALT_PINMUX_FPGA_SDMMC_USEFPGA */
15998  ALT_PINMUX_FPGA_SPIM0_USEFPGA_t pinmux_spim0_usefpga; /* ALT_PINMUX_FPGA_SPIM0_USEFPGA */
15999  ALT_PINMUX_FPGA_SPIM1_USEFPGA_t pinmux_spim1_usefpga; /* ALT_PINMUX_FPGA_SPIM1_USEFPGA */
16000  ALT_PINMUX_FPGA_SPIS0_USEFPGA_t pinmux_spis0_usefpga; /* ALT_PINMUX_FPGA_SPIS0_USEFPGA */
16001  ALT_PINMUX_FPGA_SPIS1_USEFPGA_t pinmux_spis1_usefpga; /* ALT_PINMUX_FPGA_SPIS1_USEFPGA */
16002  ALT_PINMUX_FPGA_UART0_USEFPGA_t pinmux_uart0_usefpga; /* ALT_PINMUX_FPGA_UART0_USEFPGA */
16003  ALT_PINMUX_FPGA_UART1_USEFPGA_t pinmux_uart1_usefpga; /* ALT_PINMUX_FPGA_UART1_USEFPGA */
16004  volatile uint32_t _pad_0x44_0x100[47]; /* *UNDEFINED* */
16005 };
16006 
16007 /* The typedef declaration for register group ALT_PINMUX_FPGA_INTERFACE_GRP. */
16008 typedef volatile struct ALT_PINMUX_FPGA_INTERFACE_GRP_s ALT_PINMUX_FPGA_INTERFACE_GRP_t;
16009 /* The struct declaration for the raw register contents of register group ALT_PINMUX_FPGA_INTERFACE_GRP. */
16010 struct ALT_PINMUX_FPGA_INTERFACE_GRP_raw_s
16011 {
16012  volatile uint32_t pinmux_emac0_usefpga; /* ALT_PINMUX_FPGA_EMAC0_USEFPGA */
16013  volatile uint32_t pinmux_emac1_usefpga; /* ALT_PINMUX_FPGA_EMAC1_USEFPGA */
16014  volatile uint32_t pinmux_emac2_usefpga; /* ALT_PINMUX_FPGA_EMAC2_USEFPGA */
16015  volatile uint32_t pinmux_i2c0_usefpga; /* ALT_PINMUX_FPGA_I2C0_USEFPGA */
16016  volatile uint32_t pinmux_i2c1_usefpga; /* ALT_PINMUX_FPGA_I2C1_USEFPGA */
16017  volatile uint32_t pinmux_i2c_emac0_usefpga; /* ALT_PINMUX_FPGA_I2C_EMAC0_USEFPGA */
16018  volatile uint32_t pinmux_i2c_emac1_usefpga; /* ALT_PINMUX_FPGA_I2C_EMAC1_USEFPGA */
16019  volatile uint32_t pinmux_i2c_emac2_usefpga; /* ALT_PINMUX_FPGA_I2C_EMAC2_USEFPGA */
16020  volatile uint32_t pinmux_nand_usefpga; /* ALT_PINMUX_FPGA_NAND_USEFPGA */
16021  volatile uint32_t pinmux_qspi_usefpga; /* ALT_PINMUX_FPGA_QSPI_USEFPGA */
16022  volatile uint32_t pinmux_sdmmc_usefpga; /* ALT_PINMUX_FPGA_SDMMC_USEFPGA */
16023  volatile uint32_t pinmux_spim0_usefpga; /* ALT_PINMUX_FPGA_SPIM0_USEFPGA */
16024  volatile uint32_t pinmux_spim1_usefpga; /* ALT_PINMUX_FPGA_SPIM1_USEFPGA */
16025  volatile uint32_t pinmux_spis0_usefpga; /* ALT_PINMUX_FPGA_SPIS0_USEFPGA */
16026  volatile uint32_t pinmux_spis1_usefpga; /* ALT_PINMUX_FPGA_SPIS1_USEFPGA */
16027  volatile uint32_t pinmux_uart0_usefpga; /* ALT_PINMUX_FPGA_UART0_USEFPGA */
16028  volatile uint32_t pinmux_uart1_usefpga; /* ALT_PINMUX_FPGA_UART1_USEFPGA */
16029  uint32_t _pad_0x44_0x100[47]; /* *UNDEFINED* */
16030 };
16031 
16032 /* The typedef declaration for the raw register contents of register group ALT_PINMUX_FPGA_INTERFACE_GRP. */
16033 typedef volatile struct ALT_PINMUX_FPGA_INTERFACE_GRP_raw_s ALT_PINMUX_FPGA_INTERFACE_GRP_raw_t;
16034 #endif /* __ASSEMBLY__ */
16035 
16036 
16037 #ifdef __cplusplus
16038 }
16039 #endif /* __cplusplus */
16040 #endif /* __ALT_SOCAL_PINMUX_H__ */
16041