35 #ifndef __ALT_SOCAL_ECC_EMAC1_TX_ECC_H__
36 #define __ALT_SOCAL_ECC_EMAC1_TX_ECC_H__
74 #define ALT_ECC_EMAC1_TX_ECC_IP_REV_ID_SIREV_LSB 0
76 #define ALT_ECC_EMAC1_TX_ECC_IP_REV_ID_SIREV_MSB 15
78 #define ALT_ECC_EMAC1_TX_ECC_IP_REV_ID_SIREV_WIDTH 16
80 #define ALT_ECC_EMAC1_TX_ECC_IP_REV_ID_SIREV_SET_MSK 0x0000ffff
82 #define ALT_ECC_EMAC1_TX_ECC_IP_REV_ID_SIREV_CLR_MSK 0xffff0000
84 #define ALT_ECC_EMAC1_TX_ECC_IP_REV_ID_SIREV_RESET 0x0
86 #define ALT_ECC_EMAC1_TX_ECC_IP_REV_ID_SIREV_GET(value) (((value) & 0x0000ffff) >> 0)
88 #define ALT_ECC_EMAC1_TX_ECC_IP_REV_ID_SIREV_SET(value) (((value) << 0) & 0x0000ffff)
101 struct ALT_ECC_EMAC1_TX_ECC_IP_REV_ID_s
103 const uint32_t SIREV : 16;
108 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_IP_REV_ID_s ALT_ECC_EMAC1_TX_ECC_IP_REV_ID_t;
112 #define ALT_ECC_EMAC1_TX_ECC_IP_REV_ID_RESET 0x00000000
114 #define ALT_ECC_EMAC1_TX_ECC_IP_REV_ID_OFST 0x0
142 #define ALT_ECC_EMAC1_TX_ECC_CTL_ECC_EN_LSB 0
144 #define ALT_ECC_EMAC1_TX_ECC_CTL_ECC_EN_MSB 0
146 #define ALT_ECC_EMAC1_TX_ECC_CTL_ECC_EN_WIDTH 1
148 #define ALT_ECC_EMAC1_TX_ECC_CTL_ECC_EN_SET_MSK 0x00000001
150 #define ALT_ECC_EMAC1_TX_ECC_CTL_ECC_EN_CLR_MSK 0xfffffffe
152 #define ALT_ECC_EMAC1_TX_ECC_CTL_ECC_EN_RESET 0x0
154 #define ALT_ECC_EMAC1_TX_ECC_CTL_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
156 #define ALT_ECC_EMAC1_TX_ECC_CTL_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
167 #define ALT_ECC_EMAC1_TX_ECC_CTL_CNT_RSTA_LSB 8
169 #define ALT_ECC_EMAC1_TX_ECC_CTL_CNT_RSTA_MSB 8
171 #define ALT_ECC_EMAC1_TX_ECC_CTL_CNT_RSTA_WIDTH 1
173 #define ALT_ECC_EMAC1_TX_ECC_CTL_CNT_RSTA_SET_MSK 0x00000100
175 #define ALT_ECC_EMAC1_TX_ECC_CTL_CNT_RSTA_CLR_MSK 0xfffffeff
177 #define ALT_ECC_EMAC1_TX_ECC_CTL_CNT_RSTA_RESET 0x0
179 #define ALT_ECC_EMAC1_TX_ECC_CTL_CNT_RSTA_GET(value) (((value) & 0x00000100) >> 8)
181 #define ALT_ECC_EMAC1_TX_ECC_CTL_CNT_RSTA_SET(value) (((value) << 8) & 0x00000100)
192 #define ALT_ECC_EMAC1_TX_ECC_CTL_INITA_LSB 16
194 #define ALT_ECC_EMAC1_TX_ECC_CTL_INITA_MSB 16
196 #define ALT_ECC_EMAC1_TX_ECC_CTL_INITA_WIDTH 1
198 #define ALT_ECC_EMAC1_TX_ECC_CTL_INITA_SET_MSK 0x00010000
200 #define ALT_ECC_EMAC1_TX_ECC_CTL_INITA_CLR_MSK 0xfffeffff
202 #define ALT_ECC_EMAC1_TX_ECC_CTL_INITA_RESET 0x0
204 #define ALT_ECC_EMAC1_TX_ECC_CTL_INITA_GET(value) (((value) & 0x00010000) >> 16)
206 #define ALT_ECC_EMAC1_TX_ECC_CTL_INITA_SET(value) (((value) << 16) & 0x00010000)
219 struct ALT_ECC_EMAC1_TX_ECC_CTL_s
223 uint32_t CNT_RSTA : 1;
230 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_CTL_s ALT_ECC_EMAC1_TX_ECC_CTL_t;
234 #define ALT_ECC_EMAC1_TX_ECC_CTL_RESET 0x00000000
236 #define ALT_ECC_EMAC1_TX_ECC_CTL_OFST 0x8
261 #define ALT_ECC_EMAC1_TX_ECC_INITSTAT_INITCOMPLETEA_LSB 0
263 #define ALT_ECC_EMAC1_TX_ECC_INITSTAT_INITCOMPLETEA_MSB 0
265 #define ALT_ECC_EMAC1_TX_ECC_INITSTAT_INITCOMPLETEA_WIDTH 1
267 #define ALT_ECC_EMAC1_TX_ECC_INITSTAT_INITCOMPLETEA_SET_MSK 0x00000001
269 #define ALT_ECC_EMAC1_TX_ECC_INITSTAT_INITCOMPLETEA_CLR_MSK 0xfffffffe
271 #define ALT_ECC_EMAC1_TX_ECC_INITSTAT_INITCOMPLETEA_RESET 0x0
273 #define ALT_ECC_EMAC1_TX_ECC_INITSTAT_INITCOMPLETEA_GET(value) (((value) & 0x00000001) >> 0)
275 #define ALT_ECC_EMAC1_TX_ECC_INITSTAT_INITCOMPLETEA_SET(value) (((value) << 0) & 0x00000001)
288 struct ALT_ECC_EMAC1_TX_ECC_INITSTAT_s
290 uint32_t INITCOMPLETEA : 1;
295 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_INITSTAT_s ALT_ECC_EMAC1_TX_ECC_INITSTAT_t;
299 #define ALT_ECC_EMAC1_TX_ECC_INITSTAT_RESET 0x00000000
301 #define ALT_ECC_EMAC1_TX_ECC_INITSTAT_OFST 0xc
325 #define ALT_ECC_EMAC1_TX_ECC_ERRINTEN_SERRINTEN_LSB 0
327 #define ALT_ECC_EMAC1_TX_ECC_ERRINTEN_SERRINTEN_MSB 0
329 #define ALT_ECC_EMAC1_TX_ECC_ERRINTEN_SERRINTEN_WIDTH 1
331 #define ALT_ECC_EMAC1_TX_ECC_ERRINTEN_SERRINTEN_SET_MSK 0x00000001
333 #define ALT_ECC_EMAC1_TX_ECC_ERRINTEN_SERRINTEN_CLR_MSK 0xfffffffe
335 #define ALT_ECC_EMAC1_TX_ECC_ERRINTEN_SERRINTEN_RESET 0x0
337 #define ALT_ECC_EMAC1_TX_ECC_ERRINTEN_SERRINTEN_GET(value) (((value) & 0x00000001) >> 0)
339 #define ALT_ECC_EMAC1_TX_ECC_ERRINTEN_SERRINTEN_SET(value) (((value) << 0) & 0x00000001)
352 struct ALT_ECC_EMAC1_TX_ECC_ERRINTEN_s
354 uint32_t SERRINTEN : 1;
359 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_ERRINTEN_s ALT_ECC_EMAC1_TX_ECC_ERRINTEN_t;
363 #define ALT_ECC_EMAC1_TX_ECC_ERRINTEN_RESET 0x00000000
365 #define ALT_ECC_EMAC1_TX_ECC_ERRINTEN_OFST 0x10
389 #define ALT_ECC_EMAC1_TX_ECC_ERRINTENS_SERRINTS_LSB 0
391 #define ALT_ECC_EMAC1_TX_ECC_ERRINTENS_SERRINTS_MSB 0
393 #define ALT_ECC_EMAC1_TX_ECC_ERRINTENS_SERRINTS_WIDTH 1
395 #define ALT_ECC_EMAC1_TX_ECC_ERRINTENS_SERRINTS_SET_MSK 0x00000001
397 #define ALT_ECC_EMAC1_TX_ECC_ERRINTENS_SERRINTS_CLR_MSK 0xfffffffe
399 #define ALT_ECC_EMAC1_TX_ECC_ERRINTENS_SERRINTS_RESET 0x0
401 #define ALT_ECC_EMAC1_TX_ECC_ERRINTENS_SERRINTS_GET(value) (((value) & 0x00000001) >> 0)
403 #define ALT_ECC_EMAC1_TX_ECC_ERRINTENS_SERRINTS_SET(value) (((value) << 0) & 0x00000001)
416 struct ALT_ECC_EMAC1_TX_ECC_ERRINTENS_s
418 uint32_t SERRINTS : 1;
423 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_ERRINTENS_s ALT_ECC_EMAC1_TX_ECC_ERRINTENS_t;
427 #define ALT_ECC_EMAC1_TX_ECC_ERRINTENS_RESET 0x00000000
429 #define ALT_ECC_EMAC1_TX_ECC_ERRINTENS_OFST 0x14
460 #define ALT_ECC_EMAC1_TX_ECC_ERRINTENR_SERRINTR_LSB 0
462 #define ALT_ECC_EMAC1_TX_ECC_ERRINTENR_SERRINTR_MSB 0
464 #define ALT_ECC_EMAC1_TX_ECC_ERRINTENR_SERRINTR_WIDTH 1
466 #define ALT_ECC_EMAC1_TX_ECC_ERRINTENR_SERRINTR_SET_MSK 0x00000001
468 #define ALT_ECC_EMAC1_TX_ECC_ERRINTENR_SERRINTR_CLR_MSK 0xfffffffe
470 #define ALT_ECC_EMAC1_TX_ECC_ERRINTENR_SERRINTR_RESET 0x0
472 #define ALT_ECC_EMAC1_TX_ECC_ERRINTENR_SERRINTR_GET(value) (((value) & 0x00000001) >> 0)
474 #define ALT_ECC_EMAC1_TX_ECC_ERRINTENR_SERRINTR_SET(value) (((value) << 0) & 0x00000001)
487 struct ALT_ECC_EMAC1_TX_ECC_ERRINTENR_s
489 uint32_t SERRINTR : 1;
494 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_ERRINTENR_s ALT_ECC_EMAC1_TX_ECC_ERRINTENR_t;
498 #define ALT_ECC_EMAC1_TX_ECC_ERRINTENR_RESET 0x00000000
500 #define ALT_ECC_EMAC1_TX_ECC_ERRINTENR_OFST 0x18
528 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTMOD_LSB 0
530 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTMOD_MSB 0
532 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTMOD_WIDTH 1
534 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTMOD_SET_MSK 0x00000001
536 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTMOD_CLR_MSK 0xfffffffe
538 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTMOD_RESET 0x0
540 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTMOD_GET(value) (((value) & 0x00000001) >> 0)
542 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTMOD_SET(value) (((value) << 0) & 0x00000001)
553 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTONOVF_LSB 8
555 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTONOVF_MSB 8
557 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTONOVF_WIDTH 1
559 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTONOVF_SET_MSK 0x00000100
561 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTONOVF_CLR_MSK 0xfffffeff
563 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTONOVF_RESET 0x0
565 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTONOVF_GET(value) (((value) & 0x00000100) >> 8)
567 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTONOVF_SET(value) (((value) << 8) & 0x00000100)
578 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTONCMP_LSB 16
580 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTONCMP_MSB 16
582 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTONCMP_WIDTH 1
584 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTONCMP_SET_MSK 0x00010000
586 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTONCMP_CLR_MSK 0xfffeffff
588 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTONCMP_RESET 0x0
590 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTONCMP_GET(value) (((value) & 0x00010000) >> 16)
592 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_INTONCMP_SET(value) (((value) << 16) & 0x00010000)
605 struct ALT_ECC_EMAC1_TX_ECC_INTMOD_s
607 uint32_t INTMODE : 1;
609 uint32_t INTONOVF : 1;
611 uint32_t INTONCMP : 1;
616 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_INTMOD_s ALT_ECC_EMAC1_TX_ECC_INTMOD_t;
620 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_RESET 0x00000000
622 #define ALT_ECC_EMAC1_TX_ECC_INTMOD_OFST 0x1c
648 #define ALT_ECC_EMAC1_TX_ECC_INTTEST_TSERRA_LSB 0
650 #define ALT_ECC_EMAC1_TX_ECC_INTTEST_TSERRA_MSB 0
652 #define ALT_ECC_EMAC1_TX_ECC_INTTEST_TSERRA_WIDTH 1
654 #define ALT_ECC_EMAC1_TX_ECC_INTTEST_TSERRA_SET_MSK 0x00000001
656 #define ALT_ECC_EMAC1_TX_ECC_INTTEST_TSERRA_CLR_MSK 0xfffffffe
658 #define ALT_ECC_EMAC1_TX_ECC_INTTEST_TSERRA_RESET 0x0
660 #define ALT_ECC_EMAC1_TX_ECC_INTTEST_TSERRA_GET(value) (((value) & 0x00000001) >> 0)
662 #define ALT_ECC_EMAC1_TX_ECC_INTTEST_TSERRA_SET(value) (((value) << 0) & 0x00000001)
673 #define ALT_ECC_EMAC1_TX_ECC_INTTEST_TDERRA_LSB 8
675 #define ALT_ECC_EMAC1_TX_ECC_INTTEST_TDERRA_MSB 8
677 #define ALT_ECC_EMAC1_TX_ECC_INTTEST_TDERRA_WIDTH 1
679 #define ALT_ECC_EMAC1_TX_ECC_INTTEST_TDERRA_SET_MSK 0x00000100
681 #define ALT_ECC_EMAC1_TX_ECC_INTTEST_TDERRA_CLR_MSK 0xfffffeff
683 #define ALT_ECC_EMAC1_TX_ECC_INTTEST_TDERRA_RESET 0x0
685 #define ALT_ECC_EMAC1_TX_ECC_INTTEST_TDERRA_GET(value) (((value) & 0x00000100) >> 8)
687 #define ALT_ECC_EMAC1_TX_ECC_INTTEST_TDERRA_SET(value) (((value) << 8) & 0x00000100)
700 struct ALT_ECC_EMAC1_TX_ECC_INTTEST_s
709 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_INTTEST_s ALT_ECC_EMAC1_TX_ECC_INTTEST_t;
713 #define ALT_ECC_EMAC1_TX_ECC_INTTEST_RESET 0x00000000
715 #define ALT_ECC_EMAC1_TX_ECC_INTTEST_OFST 0x24
739 #define ALT_ECC_EMAC1_TX_ECC_MODSTAT_CMPFLGA_LSB 0
741 #define ALT_ECC_EMAC1_TX_ECC_MODSTAT_CMPFLGA_MSB 0
743 #define ALT_ECC_EMAC1_TX_ECC_MODSTAT_CMPFLGA_WIDTH 1
745 #define ALT_ECC_EMAC1_TX_ECC_MODSTAT_CMPFLGA_SET_MSK 0x00000001
747 #define ALT_ECC_EMAC1_TX_ECC_MODSTAT_CMPFLGA_CLR_MSK 0xfffffffe
749 #define ALT_ECC_EMAC1_TX_ECC_MODSTAT_CMPFLGA_RESET 0x0
751 #define ALT_ECC_EMAC1_TX_ECC_MODSTAT_CMPFLGA_GET(value) (((value) & 0x00000001) >> 0)
753 #define ALT_ECC_EMAC1_TX_ECC_MODSTAT_CMPFLGA_SET(value) (((value) << 0) & 0x00000001)
766 struct ALT_ECC_EMAC1_TX_ECC_MODSTAT_s
768 uint32_t CMPFLGA : 1;
773 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_MODSTAT_s ALT_ECC_EMAC1_TX_ECC_MODSTAT_t;
777 #define ALT_ECC_EMAC1_TX_ECC_MODSTAT_RESET 0x00000000
779 #define ALT_ECC_EMAC1_TX_ECC_MODSTAT_OFST 0x28
804 #define ALT_ECC_EMAC1_TX_ECC_DERRADDRA_ADDR_LSB 0
806 #define ALT_ECC_EMAC1_TX_ECC_DERRADDRA_ADDR_MSB 9
808 #define ALT_ECC_EMAC1_TX_ECC_DERRADDRA_ADDR_WIDTH 10
810 #define ALT_ECC_EMAC1_TX_ECC_DERRADDRA_ADDR_SET_MSK 0x000003ff
812 #define ALT_ECC_EMAC1_TX_ECC_DERRADDRA_ADDR_CLR_MSK 0xfffffc00
814 #define ALT_ECC_EMAC1_TX_ECC_DERRADDRA_ADDR_RESET 0x0
816 #define ALT_ECC_EMAC1_TX_ECC_DERRADDRA_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
818 #define ALT_ECC_EMAC1_TX_ECC_DERRADDRA_ADDR_SET(value) (((value) << 0) & 0x000003ff)
831 struct ALT_ECC_EMAC1_TX_ECC_DERRADDRA_s
833 uint32_t Address : 10;
838 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_DERRADDRA_s ALT_ECC_EMAC1_TX_ECC_DERRADDRA_t;
842 #define ALT_ECC_EMAC1_TX_ECC_DERRADDRA_RESET 0x00000000
844 #define ALT_ECC_EMAC1_TX_ECC_DERRADDRA_OFST 0x2c
869 #define ALT_ECC_EMAC1_TX_ECC_SERRADDRA_ADDR_LSB 0
871 #define ALT_ECC_EMAC1_TX_ECC_SERRADDRA_ADDR_MSB 9
873 #define ALT_ECC_EMAC1_TX_ECC_SERRADDRA_ADDR_WIDTH 10
875 #define ALT_ECC_EMAC1_TX_ECC_SERRADDRA_ADDR_SET_MSK 0x000003ff
877 #define ALT_ECC_EMAC1_TX_ECC_SERRADDRA_ADDR_CLR_MSK 0xfffffc00
879 #define ALT_ECC_EMAC1_TX_ECC_SERRADDRA_ADDR_RESET 0x0
881 #define ALT_ECC_EMAC1_TX_ECC_SERRADDRA_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
883 #define ALT_ECC_EMAC1_TX_ECC_SERRADDRA_ADDR_SET(value) (((value) << 0) & 0x000003ff)
896 struct ALT_ECC_EMAC1_TX_ECC_SERRADDRA_s
898 uint32_t Address : 10;
903 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_SERRADDRA_s ALT_ECC_EMAC1_TX_ECC_SERRADDRA_t;
907 #define ALT_ECC_EMAC1_TX_ECC_SERRADDRA_RESET 0x00000000
909 #define ALT_ECC_EMAC1_TX_ECC_SERRADDRA_OFST 0x30
937 #define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_LSB 0
939 #define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_MSB 0
941 #define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_WIDTH 1
943 #define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_SET_MSK 0x00000001
945 #define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_CLR_MSK 0xfffffffe
947 #define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_RESET 0x0
949 #define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_GET(value) (((value) & 0x00000001) >> 0)
951 #define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_SET(value) (((value) << 0) & 0x00000001)
962 #define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_LSB 8
964 #define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_MSB 8
966 #define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_WIDTH 1
968 #define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_SET_MSK 0x00000100
970 #define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_CLR_MSK 0xfffffeff
972 #define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_RESET 0x0
974 #define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_GET(value) (((value) & 0x00000100) >> 8)
976 #define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_SET(value) (((value) << 8) & 0x00000100)
989 struct ALT_ECC_EMAC1_TX_ECC_INTSTAT_s
991 uint32_t SERRPENA : 1;
993 uint32_t DERRPENA : 1;
998 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_INTSTAT_s ALT_ECC_EMAC1_TX_ECC_INTSTAT_t;
1002 #define ALT_ECC_EMAC1_TX_ECC_INTSTAT_RESET 0x00000000
1004 #define ALT_ECC_EMAC1_TX_ECC_INTSTAT_OFST 0x20
1027 #define ALT_ECC_EMAC1_TX_ECC_SERRCNTREG_SERRCNT_LSB 0
1029 #define ALT_ECC_EMAC1_TX_ECC_SERRCNTREG_SERRCNT_MSB 31
1031 #define ALT_ECC_EMAC1_TX_ECC_SERRCNTREG_SERRCNT_WIDTH 32
1033 #define ALT_ECC_EMAC1_TX_ECC_SERRCNTREG_SERRCNT_SET_MSK 0xffffffff
1035 #define ALT_ECC_EMAC1_TX_ECC_SERRCNTREG_SERRCNT_CLR_MSK 0x00000000
1037 #define ALT_ECC_EMAC1_TX_ECC_SERRCNTREG_SERRCNT_RESET 0x0
1039 #define ALT_ECC_EMAC1_TX_ECC_SERRCNTREG_SERRCNT_GET(value) (((value) & 0xffffffff) >> 0)
1041 #define ALT_ECC_EMAC1_TX_ECC_SERRCNTREG_SERRCNT_SET(value) (((value) << 0) & 0xffffffff)
1043 #ifndef __ASSEMBLY__
1054 struct ALT_ECC_EMAC1_TX_ECC_SERRCNTREG_s
1056 uint32_t SERRCNT : 32;
1060 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_SERRCNTREG_s ALT_ECC_EMAC1_TX_ECC_SERRCNTREG_t;
1064 #define ALT_ECC_EMAC1_TX_ECC_SERRCNTREG_RESET 0x00000000
1066 #define ALT_ECC_EMAC1_TX_ECC_SERRCNTREG_OFST 0x3c
1091 #define ALT_ECC_EMAC1_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_LSB 0
1093 #define ALT_ECC_EMAC1_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_MSB 9
1095 #define ALT_ECC_EMAC1_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_WIDTH 10
1097 #define ALT_ECC_EMAC1_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_SET_MSK 0x000003ff
1099 #define ALT_ECC_EMAC1_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_CLR_MSK 0xfffffc00
1101 #define ALT_ECC_EMAC1_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_RESET 0x0
1103 #define ALT_ECC_EMAC1_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_GET(value) (((value) & 0x000003ff) >> 0)
1105 #define ALT_ECC_EMAC1_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_SET(value) (((value) << 0) & 0x000003ff)
1107 #ifndef __ASSEMBLY__
1118 struct ALT_ECC_EMAC1_TX_ECC_ECC_ADDRBUS_s
1120 uint32_t ECC_AddrBUS : 10;
1125 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_ECC_ADDRBUS_s ALT_ECC_EMAC1_TX_ECC_ECC_ADDRBUS_t;
1129 #define ALT_ECC_EMAC1_TX_ECC_ECC_ADDRBUS_RESET 0x00000000
1131 #define ALT_ECC_EMAC1_TX_ECC_ECC_ADDRBUS_OFST 0x40
1154 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_LSB 0
1156 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_MSB 31
1158 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_WIDTH 32
1160 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1162 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1164 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_RESET 0x0
1166 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1168 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1170 #ifndef __ASSEMBLY__
1181 struct ALT_ECC_EMAC1_TX_ECC_ECC_RDATA0BUS_s
1183 uint32_t ECC_RDataBUS : 32;
1187 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_ECC_RDATA0BUS_s ALT_ECC_EMAC1_TX_ECC_ECC_RDATA0BUS_t;
1191 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA0BUS_RESET 0x00000000
1193 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA0BUS_OFST 0x44
1217 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_LSB 0
1219 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_MSB 2
1221 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_WIDTH 3
1223 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_SET_MSK 0x00000007
1225 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_CLR_MSK 0xfffffff8
1227 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_RESET 0x0
1229 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_GET(value) (((value) & 0x00000007) >> 0)
1231 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0x00000007)
1233 #ifndef __ASSEMBLY__
1244 struct ALT_ECC_EMAC1_TX_ECC_ECC_RDATA1BUS_s
1246 uint32_t ECC_RDataBUS : 3;
1251 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_ECC_RDATA1BUS_s ALT_ECC_EMAC1_TX_ECC_ECC_RDATA1BUS_t;
1255 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA1BUS_RESET 0x00000000
1257 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA1BUS_OFST 0x48
1280 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_LSB 0
1282 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_MSB 31
1284 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_WIDTH 32
1286 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1288 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1290 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_RESET 0x0
1292 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1294 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1296 #ifndef __ASSEMBLY__
1307 struct ALT_ECC_EMAC1_TX_ECC_ECC_RDATA2BUS_s
1309 uint32_t ECC_RDataBUS : 32;
1313 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_ECC_RDATA2BUS_s ALT_ECC_EMAC1_TX_ECC_ECC_RDATA2BUS_t;
1317 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA2BUS_RESET 0x00000000
1319 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA2BUS_OFST 0x4c
1342 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_LSB 0
1344 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_MSB 31
1346 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_WIDTH 32
1348 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1350 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1352 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_RESET 0x0
1354 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1356 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1358 #ifndef __ASSEMBLY__
1369 struct ALT_ECC_EMAC1_TX_ECC_ECC_RDATA3BUS_s
1371 uint32_t ECC_RDataBUS : 32;
1375 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_ECC_RDATA3BUS_s ALT_ECC_EMAC1_TX_ECC_ECC_RDATA3BUS_t;
1379 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA3BUS_RESET 0x00000000
1381 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATA3BUS_OFST 0x50
1404 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_LSB 0
1406 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_MSB 31
1408 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_WIDTH 32
1410 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1412 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1414 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_RESET 0x0
1416 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1418 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1420 #ifndef __ASSEMBLY__
1431 struct ALT_ECC_EMAC1_TX_ECC_ECC_WDATA0BUS_s
1433 uint32_t ECC_WDataBUS : 32;
1437 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_ECC_WDATA0BUS_s ALT_ECC_EMAC1_TX_ECC_ECC_WDATA0BUS_t;
1441 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA0BUS_RESET 0x00000000
1443 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA0BUS_OFST 0x54
1467 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_LSB 0
1469 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_MSB 2
1471 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_WIDTH 3
1473 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_SET_MSK 0x00000007
1475 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_CLR_MSK 0xfffffff8
1477 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_RESET 0x0
1479 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_GET(value) (((value) & 0x00000007) >> 0)
1481 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0x00000007)
1483 #ifndef __ASSEMBLY__
1494 struct ALT_ECC_EMAC1_TX_ECC_ECC_WDATA1BUS_s
1496 uint32_t ECC_WDataBUS : 3;
1501 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_ECC_WDATA1BUS_s ALT_ECC_EMAC1_TX_ECC_ECC_WDATA1BUS_t;
1505 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA1BUS_RESET 0x00000000
1507 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA1BUS_OFST 0x58
1530 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_LSB 0
1532 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_MSB 31
1534 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_WIDTH 32
1536 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1538 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1540 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_RESET 0x0
1542 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1544 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1546 #ifndef __ASSEMBLY__
1557 struct ALT_ECC_EMAC1_TX_ECC_ECC_WDATA2BUS_s
1559 uint32_t ECC_WDataBUS : 32;
1563 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_ECC_WDATA2BUS_s ALT_ECC_EMAC1_TX_ECC_ECC_WDATA2BUS_t;
1567 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA2BUS_RESET 0x00000000
1569 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA2BUS_OFST 0x5c
1592 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_LSB 0
1594 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_MSB 31
1596 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_WIDTH 32
1598 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1600 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1602 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_RESET 0x0
1604 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1606 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1608 #ifndef __ASSEMBLY__
1619 struct ALT_ECC_EMAC1_TX_ECC_ECC_WDATA3BUS_s
1621 uint32_t ECC_WDataBUS : 32;
1625 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_ECC_WDATA3BUS_s ALT_ECC_EMAC1_TX_ECC_ECC_WDATA3BUS_t;
1629 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA3BUS_RESET 0x00000000
1631 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATA3BUS_OFST 0x60
1662 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_LSB 0
1664 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_MSB 6
1666 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_WIDTH 7
1668 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET_MSK 0x0000007f
1670 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_CLR_MSK 0xffffff80
1672 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_RESET 0x0
1674 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_GET(value) (((value) & 0x0000007f) >> 0)
1676 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET(value) (((value) << 0) & 0x0000007f)
1687 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_LSB 8
1689 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_MSB 14
1691 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_WIDTH 7
1693 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET_MSK 0x00007f00
1695 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_CLR_MSK 0xffff80ff
1697 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_RESET 0x0
1699 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_GET(value) (((value) & 0x00007f00) >> 8)
1701 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET(value) (((value) << 8) & 0x00007f00)
1712 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_LSB 16
1714 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_MSB 22
1716 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_WIDTH 7
1718 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET_MSK 0x007f0000
1720 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_CLR_MSK 0xff80ffff
1722 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_RESET 0x0
1724 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_GET(value) (((value) & 0x007f0000) >> 16)
1726 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET(value) (((value) << 16) & 0x007f0000)
1737 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_LSB 24
1739 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_MSB 30
1741 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_WIDTH 7
1743 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET_MSK 0x7f000000
1745 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_CLR_MSK 0x80ffffff
1747 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_RESET 0x0
1749 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_GET(value) (((value) & 0x7f000000) >> 24)
1751 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET(value) (((value) << 24) & 0x7f000000)
1753 #ifndef __ASSEMBLY__
1764 struct ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_s
1766 uint32_t ECC_RDataecc0BUS : 7;
1768 uint32_t ECC_RDataecc1BUS : 7;
1770 uint32_t ECC_RDataecc2BUS : 7;
1772 uint32_t ECC_RDataecc3BUS : 7;
1777 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_s ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_t;
1781 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_RESET 0x00000000
1783 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_OFST 0x64
1814 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_LSB 0
1816 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_MSB 6
1818 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_WIDTH 7
1820 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET_MSK 0x0000007f
1822 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_CLR_MSK 0xffffff80
1824 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_RESET 0x0
1826 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_GET(value) (((value) & 0x0000007f) >> 0)
1828 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET(value) (((value) << 0) & 0x0000007f)
1839 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_LSB 8
1841 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_MSB 14
1843 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_WIDTH 7
1845 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET_MSK 0x00007f00
1847 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_CLR_MSK 0xffff80ff
1849 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_RESET 0x0
1851 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_GET(value) (((value) & 0x00007f00) >> 8)
1853 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET(value) (((value) << 8) & 0x00007f00)
1864 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_LSB 16
1866 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_MSB 22
1868 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_WIDTH 7
1870 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET_MSK 0x007f0000
1872 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_CLR_MSK 0xff80ffff
1874 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_RESET 0x0
1876 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_GET(value) (((value) & 0x007f0000) >> 16)
1878 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET(value) (((value) << 16) & 0x007f0000)
1889 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_LSB 24
1891 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_MSB 30
1893 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_WIDTH 7
1895 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET_MSK 0x7f000000
1897 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_CLR_MSK 0x80ffffff
1899 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_RESET 0x0
1901 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_GET(value) (((value) & 0x7f000000) >> 24)
1903 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET(value) (((value) << 24) & 0x7f000000)
1905 #ifndef __ASSEMBLY__
1916 struct ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_s
1918 uint32_t ECC_RDataecc4BUS : 7;
1920 uint32_t ECC_RDataecc5BUS : 7;
1922 uint32_t ECC_RDataecc6BUS : 7;
1924 uint32_t ECC_RDataecc7BUS : 7;
1929 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_s ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_t;
1933 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_RESET 0x00000000
1935 #define ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_OFST 0x68
1966 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_LSB 0
1968 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_MSB 6
1970 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_WIDTH 7
1972 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET_MSK 0x0000007f
1974 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_CLR_MSK 0xffffff80
1976 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_RESET 0x0
1978 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_GET(value) (((value) & 0x0000007f) >> 0)
1980 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET(value) (((value) << 0) & 0x0000007f)
1991 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_LSB 8
1993 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_MSB 14
1995 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_WIDTH 7
1997 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET_MSK 0x00007f00
1999 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_CLR_MSK 0xffff80ff
2001 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_RESET 0x0
2003 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_GET(value) (((value) & 0x00007f00) >> 8)
2005 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET(value) (((value) << 8) & 0x00007f00)
2016 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_LSB 16
2018 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_MSB 22
2020 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_WIDTH 7
2022 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET_MSK 0x007f0000
2024 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_CLR_MSK 0xff80ffff
2026 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_RESET 0x0
2028 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_GET(value) (((value) & 0x007f0000) >> 16)
2030 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET(value) (((value) << 16) & 0x007f0000)
2041 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_LSB 24
2043 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_MSB 30
2045 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_WIDTH 7
2047 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET_MSK 0x7f000000
2049 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_CLR_MSK 0x80ffffff
2051 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_RESET 0x0
2053 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_GET(value) (((value) & 0x7f000000) >> 24)
2055 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET(value) (((value) << 24) & 0x7f000000)
2057 #ifndef __ASSEMBLY__
2068 struct ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_s
2070 uint32_t ECC_WDataecc0BUS : 7;
2072 uint32_t ECC_WDataecc1BUS : 7;
2074 uint32_t ECC_WDataecc2BUS : 7;
2076 uint32_t ECC_WDataecc3BUS : 7;
2081 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_s ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_t;
2085 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_RESET 0x00000000
2087 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_OFST 0x6c
2118 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_LSB 0
2120 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_MSB 6
2122 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_WIDTH 7
2124 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET_MSK 0x0000007f
2126 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_CLR_MSK 0xffffff80
2128 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_RESET 0x0
2130 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_GET(value) (((value) & 0x0000007f) >> 0)
2132 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET(value) (((value) << 0) & 0x0000007f)
2143 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_LSB 8
2145 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_MSB 14
2147 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_WIDTH 7
2149 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET_MSK 0x00007f00
2151 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_CLR_MSK 0xffff80ff
2153 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_RESET 0x0
2155 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_GET(value) (((value) & 0x00007f00) >> 8)
2157 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET(value) (((value) << 8) & 0x00007f00)
2168 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_LSB 16
2170 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_MSB 22
2172 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_WIDTH 7
2174 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET_MSK 0x007f0000
2176 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_CLR_MSK 0xff80ffff
2178 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_RESET 0x0
2180 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_GET(value) (((value) & 0x007f0000) >> 16)
2182 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET(value) (((value) << 16) & 0x007f0000)
2193 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_LSB 24
2195 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_MSB 30
2197 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_WIDTH 7
2199 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET_MSK 0x7f000000
2201 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_CLR_MSK 0x80ffffff
2203 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_RESET 0x0
2205 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_GET(value) (((value) & 0x7f000000) >> 24)
2207 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET(value) (((value) << 24) & 0x7f000000)
2209 #ifndef __ASSEMBLY__
2220 struct ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_s
2222 uint32_t ECC_WDataecc4BUS : 7;
2224 uint32_t ECC_WDataecc5BUS : 7;
2226 uint32_t ECC_WDataecc6BUS : 7;
2228 uint32_t ECC_WDataecc7BUS : 7;
2233 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_s ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_t;
2237 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_RESET 0x00000000
2239 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_OFST 0x70
2263 #define ALT_ECC_EMAC1_TX_ECC_ECC_DBYTECTL_DBEN_LSB 0
2265 #define ALT_ECC_EMAC1_TX_ECC_ECC_DBYTECTL_DBEN_MSB 0
2267 #define ALT_ECC_EMAC1_TX_ECC_ECC_DBYTECTL_DBEN_WIDTH 1
2269 #define ALT_ECC_EMAC1_TX_ECC_ECC_DBYTECTL_DBEN_SET_MSK 0x00000001
2271 #define ALT_ECC_EMAC1_TX_ECC_ECC_DBYTECTL_DBEN_CLR_MSK 0xfffffffe
2273 #define ALT_ECC_EMAC1_TX_ECC_ECC_DBYTECTL_DBEN_RESET 0x0
2275 #define ALT_ECC_EMAC1_TX_ECC_ECC_DBYTECTL_DBEN_GET(value) (((value) & 0x00000001) >> 0)
2277 #define ALT_ECC_EMAC1_TX_ECC_ECC_DBYTECTL_DBEN_SET(value) (((value) << 0) & 0x00000001)
2279 #ifndef __ASSEMBLY__
2290 struct ALT_ECC_EMAC1_TX_ECC_ECC_DBYTECTL_s
2297 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_ECC_DBYTECTL_s ALT_ECC_EMAC1_TX_ECC_ECC_DBYTECTL_t;
2301 #define ALT_ECC_EMAC1_TX_ECC_ECC_DBYTECTL_RESET 0x00000000
2303 #define ALT_ECC_EMAC1_TX_ECC_ECC_DBYTECTL_OFST 0x74
2335 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_DATAOVR_LSB 0
2337 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_DATAOVR_MSB 0
2339 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_DATAOVR_WIDTH 1
2341 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_DATAOVR_SET_MSK 0x00000001
2343 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_DATAOVR_CLR_MSK 0xfffffffe
2345 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_DATAOVR_RESET 0x0
2347 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_DATAOVR_GET(value) (((value) & 0x00000001) >> 0)
2349 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_DATAOVR_SET(value) (((value) << 0) & 0x00000001)
2360 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_ECCOVR_LSB 1
2362 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_ECCOVR_MSB 1
2364 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_ECCOVR_WIDTH 1
2366 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_ECCOVR_SET_MSK 0x00000002
2368 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_ECCOVR_CLR_MSK 0xfffffffd
2370 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_ECCOVR_RESET 0x0
2372 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_ECCOVR_GET(value) (((value) & 0x00000002) >> 1)
2374 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_ECCOVR_SET(value) (((value) << 1) & 0x00000002)
2385 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_RDWR_LSB 8
2387 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_RDWR_MSB 8
2389 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_RDWR_WIDTH 1
2391 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_RDWR_SET_MSK 0x00000100
2393 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_RDWR_CLR_MSK 0xfffffeff
2395 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_RDWR_RESET 0x0
2397 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_RDWR_GET(value) (((value) & 0x00000100) >> 8)
2399 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_RDWR_SET(value) (((value) << 8) & 0x00000100)
2401 #ifndef __ASSEMBLY__
2412 struct ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_s
2414 uint32_t DATAOVR : 1;
2415 uint32_t ECCOVR : 1;
2422 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_s ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_t;
2426 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_RESET 0x00000000
2428 #define ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_OFST 0x78
2453 #define ALT_ECC_EMAC1_TX_ECC_ECC_STARTACC_ENBUSA_LSB 16
2455 #define ALT_ECC_EMAC1_TX_ECC_ECC_STARTACC_ENBUSA_MSB 16
2457 #define ALT_ECC_EMAC1_TX_ECC_ECC_STARTACC_ENBUSA_WIDTH 1
2459 #define ALT_ECC_EMAC1_TX_ECC_ECC_STARTACC_ENBUSA_SET_MSK 0x00010000
2461 #define ALT_ECC_EMAC1_TX_ECC_ECC_STARTACC_ENBUSA_CLR_MSK 0xfffeffff
2463 #define ALT_ECC_EMAC1_TX_ECC_ECC_STARTACC_ENBUSA_RESET 0x0
2465 #define ALT_ECC_EMAC1_TX_ECC_ECC_STARTACC_ENBUSA_GET(value) (((value) & 0x00010000) >> 16)
2467 #define ALT_ECC_EMAC1_TX_ECC_ECC_STARTACC_ENBUSA_SET(value) (((value) << 16) & 0x00010000)
2469 #ifndef __ASSEMBLY__
2480 struct ALT_ECC_EMAC1_TX_ECC_ECC_STARTACC_s
2483 uint32_t ENBUSA : 1;
2488 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_ECC_STARTACC_s ALT_ECC_EMAC1_TX_ECC_ECC_STARTACC_t;
2492 #define ALT_ECC_EMAC1_TX_ECC_ECC_STARTACC_RESET 0x00000000
2494 #define ALT_ECC_EMAC1_TX_ECC_ECC_STARTACC_OFST 0x7c
2518 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_LSB 0
2520 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_MSB 0
2522 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_WIDTH 1
2524 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_SET_MSK 0x00000001
2526 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_CLR_MSK 0xfffffffe
2528 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_RESET 0x0
2530 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_GET(value) (((value) & 0x00000001) >> 0)
2532 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_SET(value) (((value) << 0) & 0x00000001)
2534 #ifndef __ASSEMBLY__
2545 struct ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_s
2547 uint32_t WDEN_RAM : 1;
2552 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_s ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_t;
2556 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_RESET 0x00000000
2558 #define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_OFST 0x80
2587 #define ALT_ECC_EMAC1_TX_ECC_SERRLKUPA0_ADDR_LSB 0
2589 #define ALT_ECC_EMAC1_TX_ECC_SERRLKUPA0_ADDR_MSB 9
2591 #define ALT_ECC_EMAC1_TX_ECC_SERRLKUPA0_ADDR_WIDTH 10
2593 #define ALT_ECC_EMAC1_TX_ECC_SERRLKUPA0_ADDR_SET_MSK 0x000003ff
2595 #define ALT_ECC_EMAC1_TX_ECC_SERRLKUPA0_ADDR_CLR_MSK 0xfffffc00
2597 #define ALT_ECC_EMAC1_TX_ECC_SERRLKUPA0_ADDR_RESET 0x0
2599 #define ALT_ECC_EMAC1_TX_ECC_SERRLKUPA0_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
2601 #define ALT_ECC_EMAC1_TX_ECC_SERRLKUPA0_ADDR_SET(value) (((value) << 0) & 0x000003ff)
2613 #define ALT_ECC_EMAC1_TX_ECC_SERRLKUPA0_VALID_LSB 31
2615 #define ALT_ECC_EMAC1_TX_ECC_SERRLKUPA0_VALID_MSB 31
2617 #define ALT_ECC_EMAC1_TX_ECC_SERRLKUPA0_VALID_WIDTH 1
2619 #define ALT_ECC_EMAC1_TX_ECC_SERRLKUPA0_VALID_SET_MSK 0x80000000
2621 #define ALT_ECC_EMAC1_TX_ECC_SERRLKUPA0_VALID_CLR_MSK 0x7fffffff
2623 #define ALT_ECC_EMAC1_TX_ECC_SERRLKUPA0_VALID_RESET 0x0
2625 #define ALT_ECC_EMAC1_TX_ECC_SERRLKUPA0_VALID_GET(value) (((value) & 0x80000000) >> 31)
2627 #define ALT_ECC_EMAC1_TX_ECC_SERRLKUPA0_VALID_SET(value) (((value) << 31) & 0x80000000)
2629 #ifndef __ASSEMBLY__
2640 struct ALT_ECC_EMAC1_TX_ECC_SERRLKUPA0_s
2642 const uint32_t Address : 10;
2648 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_SERRLKUPA0_s ALT_ECC_EMAC1_TX_ECC_SERRLKUPA0_t;
2652 #define ALT_ECC_EMAC1_TX_ECC_SERRLKUPA0_RESET 0x00000000
2654 #define ALT_ECC_EMAC1_TX_ECC_SERRLKUPA0_OFST 0x90
2656 #ifndef __ASSEMBLY__
2667 struct ALT_ECC_EMAC1_TX_ECC_s
2669 ALT_ECC_EMAC1_TX_ECC_IP_REV_ID_t IP_REV_ID;
2670 volatile uint32_t _pad_0x4_0x7;
2671 ALT_ECC_EMAC1_TX_ECC_CTL_t CTRL;
2672 ALT_ECC_EMAC1_TX_ECC_INITSTAT_t INITSTAT;
2673 ALT_ECC_EMAC1_TX_ECC_ERRINTEN_t ERRINTEN;
2674 ALT_ECC_EMAC1_TX_ECC_ERRINTENS_t ERRINTENS;
2675 ALT_ECC_EMAC1_TX_ECC_ERRINTENR_t ERRINTENR;
2676 ALT_ECC_EMAC1_TX_ECC_INTMOD_t INTMODE;
2677 ALT_ECC_EMAC1_TX_ECC_INTSTAT_t INTSTAT;
2678 ALT_ECC_EMAC1_TX_ECC_INTTEST_t INTTEST;
2679 ALT_ECC_EMAC1_TX_ECC_MODSTAT_t MODSTAT;
2680 ALT_ECC_EMAC1_TX_ECC_DERRADDRA_t DERRADDRA;
2681 ALT_ECC_EMAC1_TX_ECC_SERRADDRA_t SERRADDRA;
2682 volatile uint32_t _pad_0x34_0x3b[2];
2683 ALT_ECC_EMAC1_TX_ECC_SERRCNTREG_t SERRCNTREG;
2684 ALT_ECC_EMAC1_TX_ECC_ECC_ADDRBUS_t ECC_Addrbus;
2685 ALT_ECC_EMAC1_TX_ECC_ECC_RDATA0BUS_t ECC_RData0bus;
2686 ALT_ECC_EMAC1_TX_ECC_ECC_RDATA1BUS_t ECC_RData1bus;
2687 ALT_ECC_EMAC1_TX_ECC_ECC_RDATA2BUS_t ECC_RData2bus;
2688 ALT_ECC_EMAC1_TX_ECC_ECC_RDATA3BUS_t ECC_RData3bus;
2689 ALT_ECC_EMAC1_TX_ECC_ECC_WDATA0BUS_t ECC_WData0bus;
2690 ALT_ECC_EMAC1_TX_ECC_ECC_WDATA1BUS_t ECC_WData1bus;
2691 ALT_ECC_EMAC1_TX_ECC_ECC_WDATA2BUS_t ECC_WData2bus;
2692 ALT_ECC_EMAC1_TX_ECC_ECC_WDATA3BUS_t ECC_WData3bus;
2693 ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC0BUS_t ECC_RDataecc0bus;
2694 ALT_ECC_EMAC1_TX_ECC_ECC_RDATAECC1BUS_t ECC_RDataecc1bus;
2695 ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC0BUS_t ECC_WDataecc0bus;
2696 ALT_ECC_EMAC1_TX_ECC_ECC_WDATAECC1BUS_t ECC_WDataecc1bus;
2697 ALT_ECC_EMAC1_TX_ECC_ECC_DBYTECTL_t ECC_dbytectrl;
2698 ALT_ECC_EMAC1_TX_ECC_ECC_ACCCTL_t ECC_accctrl;
2699 ALT_ECC_EMAC1_TX_ECC_ECC_STARTACC_t ECC_startacc;
2700 ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_t ECC_wdctrl;
2701 volatile uint32_t _pad_0x84_0x8f[3];
2702 ALT_ECC_EMAC1_TX_ECC_SERRLKUPA0_t SERRLKUPA0;
2703 volatile uint32_t _pad_0x94_0x400[219];
2707 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_s ALT_ECC_EMAC1_TX_ECC_t;
2709 struct ALT_ECC_EMAC1_TX_ECC_raw_s
2711 volatile uint32_t IP_REV_ID;
2712 uint32_t _pad_0x4_0x7;
2713 volatile uint32_t CTRL;
2714 volatile uint32_t INITSTAT;
2715 volatile uint32_t ERRINTEN;
2716 volatile uint32_t ERRINTENS;
2717 volatile uint32_t ERRINTENR;
2718 volatile uint32_t INTMODE;
2719 volatile uint32_t INTSTAT;
2720 volatile uint32_t INTTEST;
2721 volatile uint32_t MODSTAT;
2722 volatile uint32_t DERRADDRA;
2723 volatile uint32_t SERRADDRA;
2724 uint32_t _pad_0x34_0x3b[2];
2725 volatile uint32_t SERRCNTREG;
2726 volatile uint32_t ECC_Addrbus;
2727 volatile uint32_t ECC_RData0bus;
2728 volatile uint32_t ECC_RData1bus;
2729 volatile uint32_t ECC_RData2bus;
2730 volatile uint32_t ECC_RData3bus;
2731 volatile uint32_t ECC_WData0bus;
2732 volatile uint32_t ECC_WData1bus;
2733 volatile uint32_t ECC_WData2bus;
2734 volatile uint32_t ECC_WData3bus;
2735 volatile uint32_t ECC_RDataecc0bus;
2736 volatile uint32_t ECC_RDataecc1bus;
2737 volatile uint32_t ECC_WDataecc0bus;
2738 volatile uint32_t ECC_WDataecc1bus;
2739 volatile uint32_t ECC_dbytectrl;
2740 volatile uint32_t ECC_accctrl;
2741 volatile uint32_t ECC_startacc;
2742 volatile uint32_t ECC_wdctrl;
2743 uint32_t _pad_0x84_0x8f[3];
2744 volatile uint32_t SERRLKUPA0;
2745 uint32_t _pad_0x94_0x400[219];
2749 typedef volatile struct ALT_ECC_EMAC1_TX_ECC_raw_s ALT_ECC_EMAC1_TX_ECC_raw_t;