Hardware Libraries  20.1
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alt_mpfe.h
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2 * *
3 * Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
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32 
33 /* Altera - ALT_MPFE_DDR_MAIN_PRB */
34 
35 #ifndef __ALT_SOCAL_MPFE_H__
36 #define __ALT_SOCAL_MPFE_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : MPFE_DDR_MAIN_PRB
50  *
51  */
52 /*
53  * Register : ddr_T_main_Probe_Id_CoreId
54  *
55  * Register Layout
56  *
57  * Bits | Access | Reset | Description
58  * :-------|:-------|:---------|:--------------------------------------------------------------
59  * [7:0] | R | 0x6 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID
60  * [31:8] | R | 0x298113 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM
61  *
62  */
63 /*
64  * Field : CORETYPEID
65  *
66  * Field identifying the type of IP.
67  *
68  * Field Access Macros:
69  *
70  */
71 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID register field. */
72 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID_LSB 0
73 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID register field. */
74 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID_MSB 7
75 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID register field. */
76 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID_WIDTH 8
77 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID register field value. */
78 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
79 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID register field value. */
80 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
81 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID register field. */
82 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID_RESET 0x6
83 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID field value from a register. */
84 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
85 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID register field value suitable for setting the register. */
86 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
87 
88 /*
89  * Field : CORECHECKSUM
90  *
91  * Field containing a checksum of the parameters of the IP.
92  *
93  * Field Access Macros:
94  *
95  */
96 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM register field. */
97 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM_LSB 8
98 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM register field. */
99 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM_MSB 31
100 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM register field. */
101 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM_WIDTH 24
102 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM register field value. */
103 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
104 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM register field value. */
105 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
106 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM register field. */
107 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM_RESET 0x298113
108 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM field value from a register. */
109 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
110 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM register field value suitable for setting the register. */
111 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
112 
113 #ifndef __ASSEMBLY__
114 /*
115  * WARNING: The C register and register group struct declarations are provided for
116  * convenience and illustrative purposes. They should, however, be used with
117  * caution as the C language standard provides no guarantees about the alignment or
118  * atomicity of device memory accesses. The recommended practice for coding device
119  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
120  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
121  * alt_write_dword() functions for 64 bit registers.
122  *
123  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID.
124  */
125 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_s
126 {
127  const volatile uint32_t CORETYPEID : 8; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID */
128  const volatile uint32_t CORECHECKSUM : 24; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM */
129 };
130 
131 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID. */
132 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_t;
133 #endif /* __ASSEMBLY__ */
134 
135 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID register. */
136 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_RESET 0x29811306
137 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID register from the beginning of the component. */
138 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_OFST 0x0
139 
140 /*
141  * Register : ddr_T_main_Probe_Id_RevisionId
142  *
143  * Register Layout
144  *
145  * Bits | Access | Reset | Description
146  * :-------|:-------|:------|:---------------------------------------------------------------
147  * [7:0] | R | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID
148  * [31:8] | R | 0x148 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID
149  *
150  */
151 /*
152  * Field : USERID
153  *
154  * Field containing a user defined value, not used anywhere inside the IP itself.
155  *
156  * Field Access Macros:
157  *
158  */
159 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID register field. */
160 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID_LSB 0
161 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID register field. */
162 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID_MSB 7
163 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID register field. */
164 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID_WIDTH 8
165 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID register field value. */
166 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID_SET_MSK 0x000000ff
167 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID register field value. */
168 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
169 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID register field. */
170 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID_RESET 0x0
171 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID field value from a register. */
172 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
173 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID register field value suitable for setting the register. */
174 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
175 
176 /*
177  * Field : FLEXNOCID
178  *
179  * Field containing the build revision of the software used to generate the IP HDL
180  * code.
181  *
182  * Field Access Macros:
183  *
184  */
185 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID register field. */
186 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_LSB 8
187 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID register field. */
188 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_MSB 31
189 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID register field. */
190 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_WIDTH 24
191 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID register field value. */
192 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
193 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID register field value. */
194 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
195 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID register field. */
196 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_RESET 0x148
197 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID field value from a register. */
198 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
199 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID register field value suitable for setting the register. */
200 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
201 
202 #ifndef __ASSEMBLY__
203 /*
204  * WARNING: The C register and register group struct declarations are provided for
205  * convenience and illustrative purposes. They should, however, be used with
206  * caution as the C language standard provides no guarantees about the alignment or
207  * atomicity of device memory accesses. The recommended practice for coding device
208  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
209  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
210  * alt_write_dword() functions for 64 bit registers.
211  *
212  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID.
213  */
214 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_s
215 {
216  const volatile uint32_t USERID : 8; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID */
217  const volatile uint32_t FLEXNOCID : 24; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID */
218 };
219 
220 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID. */
221 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_t;
222 #endif /* __ASSEMBLY__ */
223 
224 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID register. */
225 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_RESET 0x00014800
226 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID register from the beginning of the component. */
227 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_OFST 0x4
228 
229 /*
230  * Register : ddr_T_main_Probe_MainCtl
231  *
232  * Register MainCtl contains probe global control bits. The register has seven bit
233  * fields:
234  *
235  * Register Layout
236  *
237  * Bits | Access | Reset | Description
238  * :-------|:-------|:--------|:-------------------------------------------------------------------------
239  * [0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN
240  * [1] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN
241  * [2] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN
242  * [3] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN
243  * [4] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN
244  * [5] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP
245  * [6] | R | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE
246  * [7] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN
247  * [31:8] | ??? | Unknown | *UNDEFINED*
248  *
249  */
250 /*
251  * Field : ERREN
252  *
253  * Register field ErrEn enables the probe to send on the ObsTx output any packet
254  * with Error status, independently of filtering mechanisms, thus constituting a
255  * simple supplementary global filter.
256  *
257  * Field Access Macros:
258  *
259  */
260 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN register field. */
261 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN_LSB 0
262 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN register field. */
263 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN_MSB 0
264 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN register field. */
265 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN_WIDTH 1
266 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN register field value. */
267 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN_SET_MSK 0x00000001
268 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN register field value. */
269 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN_CLR_MSK 0xfffffffe
270 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN register field. */
271 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN_RESET 0x0
272 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN field value from a register. */
273 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN_GET(value) (((value) & 0x00000001) >> 0)
274 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN register field value suitable for setting the register. */
275 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN_SET(value) (((value) << 0) & 0x00000001)
276 
277 /*
278  * Field : TRACEEN
279  *
280  * Register field TraceEn enables the probe to send filtered packets (Trace) on the
281  * ObsTx observation output.
282  *
283  * Field Access Macros:
284  *
285  */
286 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN register field. */
287 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN_LSB 1
288 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN register field. */
289 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN_MSB 1
290 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN register field. */
291 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN_WIDTH 1
292 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN register field value. */
293 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN_SET_MSK 0x00000002
294 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN register field value. */
295 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN_CLR_MSK 0xfffffffd
296 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN register field. */
297 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN_RESET 0x0
298 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN field value from a register. */
299 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN_GET(value) (((value) & 0x00000002) >> 1)
300 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN register field value suitable for setting the register. */
301 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN_SET(value) (((value) << 1) & 0x00000002)
302 
303 /*
304  * Field : PAYLOADEN
305  *
306  * Register field PayloadEn, when set to 1, enables traces to contain headers and
307  * payload. When set ot 0, only headers are reported.
308  *
309  * Field Access Macros:
310  *
311  */
312 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN register field. */
313 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN_LSB 2
314 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN register field. */
315 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN_MSB 2
316 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN register field. */
317 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN_WIDTH 1
318 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN register field value. */
319 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN_SET_MSK 0x00000004
320 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN register field value. */
321 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN_CLR_MSK 0xfffffffb
322 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN register field. */
323 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN_RESET 0x0
324 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN field value from a register. */
325 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN_GET(value) (((value) & 0x00000004) >> 2)
326 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN register field value suitable for setting the register. */
327 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN_SET(value) (((value) << 2) & 0x00000004)
328 
329 /*
330  * Field : STATEN
331  *
332  * When set to 1, register field StatEn enables statistics profiling. The probe
333  * sendS statistics results to the output for signal ObsTx. All statistics counters
334  * are cleared when the StatEn bit goes from 0 to 1. When set to 0, counters are
335  * disabled.
336  *
337  * Field Access Macros:
338  *
339  */
340 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN register field. */
341 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN_LSB 3
342 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN register field. */
343 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN_MSB 3
344 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN register field. */
345 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN_WIDTH 1
346 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN register field value. */
347 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN_SET_MSK 0x00000008
348 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN register field value. */
349 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN_CLR_MSK 0xfffffff7
350 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN register field. */
351 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN_RESET 0x0
352 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN field value from a register. */
353 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN_GET(value) (((value) & 0x00000008) >> 3)
354 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN register field value suitable for setting the register. */
355 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN_SET(value) (((value) << 3) & 0x00000008)
356 
357 /*
358  * Field : ALARMEN
359  *
360  * When set, register field AlarmEn enables the probe to collect alarm-related
361  * information. When the register field bit is null, both TraceAlarm and StatAlarm
362  * outputs are driven to 0.
363  *
364  * Field Access Macros:
365  *
366  */
367 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN register field. */
368 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN_LSB 4
369 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN register field. */
370 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN_MSB 4
371 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN register field. */
372 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN_WIDTH 1
373 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN register field value. */
374 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN_SET_MSK 0x00000010
375 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN register field value. */
376 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN_CLR_MSK 0xffffffef
377 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN register field. */
378 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN_RESET 0x0
379 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN field value from a register. */
380 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN_GET(value) (((value) & 0x00000010) >> 4)
381 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN register field value suitable for setting the register. */
382 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN_SET(value) (((value) << 4) & 0x00000010)
383 
384 /*
385  * Field : STATCONDDUMP
386  *
387  * When set, register field StatCondDump enables the dump of a statistics frame to
388  * the range of counter values set for registers StatAlarmMin, StatAlarmMax, and
389  * AlarmMode. This field also renders register StatAlarmStatus inoperative. When
390  * parameter statisticsCounterAlarm is set to False, the StatCondDump register bit
391  * is reserved.
392  *
393  * Field Access Macros:
394  *
395  */
396 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP register field. */
397 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP_LSB 5
398 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP register field. */
399 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP_MSB 5
400 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP register field. */
401 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP_WIDTH 1
402 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP register field value. */
403 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP_SET_MSK 0x00000020
404 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP register field value. */
405 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP_CLR_MSK 0xffffffdf
406 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP register field. */
407 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP_RESET 0x0
408 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP field value from a register. */
409 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP_GET(value) (((value) & 0x00000020) >> 5)
410 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP register field value suitable for setting the register. */
411 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP_SET(value) (((value) << 5) & 0x00000020)
412 
413 /*
414  * Field : INTRUSIVEMODE
415  *
416  * When set to 1, register field IntrusiveMode enables trace operation in Intrusive
417  * flow-control mode. When set to 0, the register enables trace operation in
418  * Overflow flow-control mode
419  *
420  * Field Access Macros:
421  *
422  */
423 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE register field. */
424 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_LSB 6
425 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE register field. */
426 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MSB 6
427 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE register field. */
428 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_WIDTH 1
429 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE register field value. */
430 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SET_MSK 0x00000040
431 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE register field value. */
432 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_CLR_MSK 0xffffffbf
433 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE register field. */
434 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_RESET 0x0
435 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE field value from a register. */
436 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_GET(value) (((value) & 0x00000040) >> 6)
437 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE register field value suitable for setting the register. */
438 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SET(value) (((value) << 6) & 0x00000040)
439 
440 /*
441  * Field : FILTBYTEALWAYSCHAINABLEEN
442  *
443  * When set to 0, filters are mapped to all statistic counters when counting bytes
444  * or enabled bytes. Therefore, only filter events mapped to even counters can be
445  * counted using a pair of chained counters.When set to 1, filters are mapped only
446  * to even statistic counters when counting bytes or enabled bytes. Thus events
447  * from any filter can be counted using a pair of chained counters.
448  *
449  * Field Access Macros:
450  *
451  */
452 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
453 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_LSB 7
454 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
455 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MSB 7
456 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
457 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_WIDTH 1
458 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field value. */
459 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET_MSK 0x00000080
460 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field value. */
461 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_CLR_MSK 0xffffff7f
462 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
463 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_RESET 0x0
464 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN field value from a register. */
465 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_GET(value) (((value) & 0x00000080) >> 7)
466 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field value suitable for setting the register. */
467 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET(value) (((value) << 7) & 0x00000080)
468 
469 #ifndef __ASSEMBLY__
470 /*
471  * WARNING: The C register and register group struct declarations are provided for
472  * convenience and illustrative purposes. They should, however, be used with
473  * caution as the C language standard provides no guarantees about the alignment or
474  * atomicity of device memory accesses. The recommended practice for coding device
475  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
476  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
477  * alt_write_dword() functions for 64 bit registers.
478  *
479  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL.
480  */
481 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_s
482 {
483  volatile uint32_t ERREN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN */
484  volatile uint32_t TRACEEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN */
485  volatile uint32_t PAYLOADEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN */
486  volatile uint32_t STATEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN */
487  volatile uint32_t ALARMEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN */
488  volatile uint32_t STATCONDDUMP : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP */
489  const volatile uint32_t INTRUSIVEMODE : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE */
490  volatile uint32_t FILTBYTEALWAYSCHAINABLEEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN */
491  uint32_t : 24; /* *UNDEFINED* */
492 };
493 
494 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL. */
495 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_t;
496 #endif /* __ASSEMBLY__ */
497 
498 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL register. */
499 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_RESET 0x00000000
500 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL register from the beginning of the component. */
501 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_OFST 0x8
502 
503 /*
504  * Register : ddr_T_main_Probe_CfgCtl
505  *
506  * Register Layout
507  *
508  * Bits | Access | Reset | Description
509  * :-------|:-------|:--------|:-------------------------------------------------------
510  * [0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN
511  * [1] | R | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE
512  * [31:2] | ??? | Unknown | *UNDEFINED*
513  *
514  */
515 /*
516  * Field : GLOBALEN
517  *
518  * Field Access Macros:
519  *
520  */
521 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN register field. */
522 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN_LSB 0
523 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN register field. */
524 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN_MSB 0
525 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN register field. */
526 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN_WIDTH 1
527 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN register field value. */
528 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN_SET_MSK 0x00000001
529 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN register field value. */
530 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN_CLR_MSK 0xfffffffe
531 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN register field. */
532 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN_RESET 0x0
533 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN field value from a register. */
534 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN_GET(value) (((value) & 0x00000001) >> 0)
535 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN register field value suitable for setting the register. */
536 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN_SET(value) (((value) << 0) & 0x00000001)
537 
538 /*
539  * Field : ACTIVE
540  *
541  * Field Access Macros:
542  *
543  */
544 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE register field. */
545 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE_LSB 1
546 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE register field. */
547 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE_MSB 1
548 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE register field. */
549 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE_WIDTH 1
550 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE register field value. */
551 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE_SET_MSK 0x00000002
552 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE register field value. */
553 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE_CLR_MSK 0xfffffffd
554 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE register field. */
555 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE_RESET 0x0
556 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE field value from a register. */
557 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE_GET(value) (((value) & 0x00000002) >> 1)
558 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE register field value suitable for setting the register. */
559 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE_SET(value) (((value) << 1) & 0x00000002)
560 
561 #ifndef __ASSEMBLY__
562 /*
563  * WARNING: The C register and register group struct declarations are provided for
564  * convenience and illustrative purposes. They should, however, be used with
565  * caution as the C language standard provides no guarantees about the alignment or
566  * atomicity of device memory accesses. The recommended practice for coding device
567  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
568  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
569  * alt_write_dword() functions for 64 bit registers.
570  *
571  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL.
572  */
573 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_s
574 {
575  volatile uint32_t GLOBALEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN */
576  const volatile uint32_t ACTIVE : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE */
577  uint32_t : 30; /* *UNDEFINED* */
578 };
579 
580 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL. */
581 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_t;
582 #endif /* __ASSEMBLY__ */
583 
584 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL register. */
585 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_RESET 0x00000000
586 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL register from the beginning of the component. */
587 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_OFST 0xc
588 
589 /*
590  * Register : ddr_T_main_Probe_FilterLut
591  *
592  * Register Layout
593  *
594  * Bits | Access | Reset | Description
595  * :--------|:-------|:--------|:-----------------------------------------------------------
596  * [15:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT
597  * [31:16] | ??? | Unknown | *UNDEFINED*
598  *
599  */
600 /*
601  * Field : FILTERLUT
602  *
603  * Register FilterLut contains a look-up table that is used to combine filter
604  * outputs in order to trace packets. Packet tracing is enabled when the FilterLut
605  * bit of index (FNout ... F0out) is equal to 1.The number of bits in register
606  * FilterLut is determined by the setting for parameter nFilter, calculated as
607  * 2**nFilter.When parameter nFilter is set to None, FilterLut is reserved.
608  *
609  * Field Access Macros:
610  *
611  */
612 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT register field. */
613 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT_LSB 0
614 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT register field. */
615 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT_MSB 15
616 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT register field. */
617 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT_WIDTH 16
618 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT register field value. */
619 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT_SET_MSK 0x0000ffff
620 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT register field value. */
621 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT_CLR_MSK 0xffff0000
622 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT register field. */
623 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT_RESET 0x0
624 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT field value from a register. */
625 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT_GET(value) (((value) & 0x0000ffff) >> 0)
626 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT register field value suitable for setting the register. */
627 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT_SET(value) (((value) << 0) & 0x0000ffff)
628 
629 #ifndef __ASSEMBLY__
630 /*
631  * WARNING: The C register and register group struct declarations are provided for
632  * convenience and illustrative purposes. They should, however, be used with
633  * caution as the C language standard provides no guarantees about the alignment or
634  * atomicity of device memory accesses. The recommended practice for coding device
635  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
636  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
637  * alt_write_dword() functions for 64 bit registers.
638  *
639  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT.
640  */
641 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_s
642 {
643  volatile uint32_t FILTERLUT : 16; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT */
644  uint32_t : 16; /* *UNDEFINED* */
645 };
646 
647 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT. */
648 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_t;
649 #endif /* __ASSEMBLY__ */
650 
651 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT register. */
652 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_RESET 0x00000000
653 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT register from the beginning of the component. */
654 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_OFST 0x14
655 
656 /*
657  * Register : ddr_T_main_Probe_TraceAlarmEn
658  *
659  * Register Layout
660  *
661  * Bits | Access | Reset | Description
662  * :-------|:-------|:--------|:-----------------------------------------------------------------
663  * [4:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN
664  * [31:5] | ??? | Unknown | *UNDEFINED*
665  *
666  */
667 /*
668  * Field : TRACEALARMEN
669  *
670  * Register TraceAlarmEn controls which lookup table or filter can set the
671  * TraceAlarm signal output once the trace alarm status is set. The number of bits
672  * in register TraceAlarmEn is determined by the value set for parameter nFilter +
673  * 1.Bit nFilter controls the lookup table output, and bits nFilter:0 control the
674  * corresponding filter output. When parameter nFilter is set to None, TraceAlarmEn
675  * is reserved.
676  *
677  * Field Access Macros:
678  *
679  */
680 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN register field. */
681 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_LSB 0
682 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN register field. */
683 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_MSB 4
684 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN register field. */
685 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_WIDTH 5
686 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN register field value. */
687 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_SET_MSK 0x0000001f
688 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN register field value. */
689 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_CLR_MSK 0xffffffe0
690 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN register field. */
691 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_RESET 0x0
692 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN field value from a register. */
693 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_GET(value) (((value) & 0x0000001f) >> 0)
694 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN register field value suitable for setting the register. */
695 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_SET(value) (((value) << 0) & 0x0000001f)
696 
697 #ifndef __ASSEMBLY__
698 /*
699  * WARNING: The C register and register group struct declarations are provided for
700  * convenience and illustrative purposes. They should, however, be used with
701  * caution as the C language standard provides no guarantees about the alignment or
702  * atomicity of device memory accesses. The recommended practice for coding device
703  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
704  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
705  * alt_write_dword() functions for 64 bit registers.
706  *
707  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN.
708  */
709 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_s
710 {
711  volatile uint32_t TRACEALARMEN : 5; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN */
712  uint32_t : 27; /* *UNDEFINED* */
713 };
714 
715 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN. */
716 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_t;
717 #endif /* __ASSEMBLY__ */
718 
719 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN register. */
720 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_RESET 0x00000000
721 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN register from the beginning of the component. */
722 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_OFST 0x18
723 
724 /*
725  * Register : ddr_T_main_Probe_TraceAlarmStatus
726  *
727  * Register Layout
728  *
729  * Bits | Access | Reset | Description
730  * :-------|:-------|:--------|:-------------------------------------------------------------------------
731  * [4:0] | R | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS
732  * [31:5] | ??? | Unknown | *UNDEFINED*
733  *
734  */
735 /*
736  * Field : TRACEALARMSTATUS
737  *
738  * Register TraceAlarmStatus is a read-only register that indicates which lookup
739  * table or filter has been matched by a packet, independently of register
740  * TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is
741  * determined by the value set for parameter nFilter + 1.When nFilter is set to
742  * None, TraceAlarmStatus is reserved.
743  *
744  * Field Access Macros:
745  *
746  */
747 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS register field. */
748 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_LSB 0
749 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS register field. */
750 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_MSB 4
751 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS register field. */
752 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_WIDTH 5
753 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS register field value. */
754 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_SET_MSK 0x0000001f
755 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS register field value. */
756 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_CLR_MSK 0xffffffe0
757 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS register field. */
758 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_RESET 0x0
759 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS field value from a register. */
760 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_GET(value) (((value) & 0x0000001f) >> 0)
761 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS register field value suitable for setting the register. */
762 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_SET(value) (((value) << 0) & 0x0000001f)
763 
764 #ifndef __ASSEMBLY__
765 /*
766  * WARNING: The C register and register group struct declarations are provided for
767  * convenience and illustrative purposes. They should, however, be used with
768  * caution as the C language standard provides no guarantees about the alignment or
769  * atomicity of device memory accesses. The recommended practice for coding device
770  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
771  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
772  * alt_write_dword() functions for 64 bit registers.
773  *
774  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS.
775  */
776 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_s
777 {
778  const volatile uint32_t TRACEALARMSTATUS : 5; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS */
779  uint32_t : 27; /* *UNDEFINED* */
780 };
781 
782 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS. */
783 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_t;
784 #endif /* __ASSEMBLY__ */
785 
786 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS register. */
787 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_RESET 0x00000000
788 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS register from the beginning of the component. */
789 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_OFST 0x1c
790 
791 /*
792  * Register : ddr_T_main_Probe_TraceAlarmClr
793  *
794  * Register Layout
795  *
796  * Bits | Access | Reset | Description
797  * :-------|:-------|:--------|:-------------------------------------------------------------------
798  * [4:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR
799  * [31:5] | ??? | Unknown | *UNDEFINED*
800  *
801  */
802 /*
803  * Field : TRACEALARMCLR
804  *
805  * Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in
806  * register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal
807  * to (nFilter + 1). When nFilter is set to 0, TraceAlarmClr is reserved.NOTE The
808  * written value is not stored in TraceAlarmClr. A read always returns 0.
809  *
810  * Field Access Macros:
811  *
812  */
813 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR register field. */
814 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_LSB 0
815 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR register field. */
816 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_MSB 4
817 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR register field. */
818 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_WIDTH 5
819 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR register field value. */
820 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_SET_MSK 0x0000001f
821 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR register field value. */
822 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_CLR_MSK 0xffffffe0
823 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR register field. */
824 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_RESET 0x0
825 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR field value from a register. */
826 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_GET(value) (((value) & 0x0000001f) >> 0)
827 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR register field value suitable for setting the register. */
828 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_SET(value) (((value) << 0) & 0x0000001f)
829 
830 #ifndef __ASSEMBLY__
831 /*
832  * WARNING: The C register and register group struct declarations are provided for
833  * convenience and illustrative purposes. They should, however, be used with
834  * caution as the C language standard provides no guarantees about the alignment or
835  * atomicity of device memory accesses. The recommended practice for coding device
836  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
837  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
838  * alt_write_dword() functions for 64 bit registers.
839  *
840  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR.
841  */
842 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_s
843 {
844  volatile uint32_t TRACEALARMCLR : 5; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR */
845  uint32_t : 27; /* *UNDEFINED* */
846 };
847 
848 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR. */
849 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_t;
850 #endif /* __ASSEMBLY__ */
851 
852 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR register. */
853 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_RESET 0x00000000
854 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR register from the beginning of the component. */
855 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_OFST 0x20
856 
857 /*
858  * Register : ddr_T_main_Probe_StatPeriod
859  *
860  * Register Layout
861  *
862  * Bits | Access | Reset | Description
863  * :-------|:-------|:--------|:-------------------------------------------------------------
864  * [4:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD
865  * [31:5] | ??? | Unknown | *UNDEFINED*
866  *
867  */
868 /*
869  * Field : STATPERIOD
870  *
871  * Register StatPeriod is a 5-bit register that sets a period, within a range of 2
872  * cycles to 2 gigacycles, during which statistics are collected before being
873  * dumped automatically. Setting the register implicitly enables automatic mode
874  * operation for statistics collection. The period is calculated with the formula:
875  * N_Cycle = 2**StatPeriodWhen register StatPeriod is set to its default value 0,
876  * automatic dump mode is disabled, and register StatGo is activated for manual
877  * mode operation. Note: When parameter statisticsCollection is set to False,
878  * StatPeriod is reserved.
879  *
880  * Field Access Macros:
881  *
882  */
883 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD register field. */
884 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD_LSB 0
885 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD register field. */
886 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD_MSB 4
887 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD register field. */
888 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD_WIDTH 5
889 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD register field value. */
890 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD_SET_MSK 0x0000001f
891 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD register field value. */
892 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD_CLR_MSK 0xffffffe0
893 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD register field. */
894 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD_RESET 0x0
895 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD field value from a register. */
896 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD_GET(value) (((value) & 0x0000001f) >> 0)
897 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD register field value suitable for setting the register. */
898 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD_SET(value) (((value) << 0) & 0x0000001f)
899 
900 #ifndef __ASSEMBLY__
901 /*
902  * WARNING: The C register and register group struct declarations are provided for
903  * convenience and illustrative purposes. They should, however, be used with
904  * caution as the C language standard provides no guarantees about the alignment or
905  * atomicity of device memory accesses. The recommended practice for coding device
906  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
907  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
908  * alt_write_dword() functions for 64 bit registers.
909  *
910  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD.
911  */
912 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_s
913 {
914  volatile uint32_t STATPERIOD : 5; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD */
915  uint32_t : 27; /* *UNDEFINED* */
916 };
917 
918 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD. */
919 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_t;
920 #endif /* __ASSEMBLY__ */
921 
922 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD register. */
923 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_RESET 0x00000000
924 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD register from the beginning of the component. */
925 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_OFST 0x24
926 
927 /*
928  * Register : ddr_T_main_Probe_StatGo
929  *
930  * Register Layout
931  *
932  * Bits | Access | Reset | Description
933  * :-------|:-------|:--------|:-----------------------------------------------------
934  * [0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO
935  * [31:1] | ??? | Unknown | *UNDEFINED*
936  *
937  */
938 /*
939  * Field : STATGO
940  *
941  * Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The
942  * register is active when statistics collection operates in manual mode, that is,
943  * when register StatPeriod is set to 0.NOTE The written value is not stored in
944  * StatGo. A read always returns 0.
945  *
946  * Field Access Macros:
947  *
948  */
949 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO register field. */
950 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO_LSB 0
951 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO register field. */
952 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO_MSB 0
953 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO register field. */
954 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO_WIDTH 1
955 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO register field value. */
956 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO_SET_MSK 0x00000001
957 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO register field value. */
958 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO_CLR_MSK 0xfffffffe
959 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO register field. */
960 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO_RESET 0x0
961 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO field value from a register. */
962 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO_GET(value) (((value) & 0x00000001) >> 0)
963 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO register field value suitable for setting the register. */
964 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO_SET(value) (((value) << 0) & 0x00000001)
965 
966 #ifndef __ASSEMBLY__
967 /*
968  * WARNING: The C register and register group struct declarations are provided for
969  * convenience and illustrative purposes. They should, however, be used with
970  * caution as the C language standard provides no guarantees about the alignment or
971  * atomicity of device memory accesses. The recommended practice for coding device
972  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
973  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
974  * alt_write_dword() functions for 64 bit registers.
975  *
976  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO.
977  */
978 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_s
979 {
980  volatile uint32_t STATGO : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO */
981  uint32_t : 31; /* *UNDEFINED* */
982 };
983 
984 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO. */
985 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_t;
986 #endif /* __ASSEMBLY__ */
987 
988 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO register. */
989 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_RESET 0x00000000
990 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO register from the beginning of the component. */
991 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_OFST 0x28
992 
993 /*
994  * Register : ddr_T_main_Probe_StatAlarmMin
995  *
996  * Register Layout
997  *
998  * Bits | Access | Reset | Description
999  * :-------|:-------|:------|:-----------------------------------------------------------------
1000  * [31:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN
1001  *
1002  */
1003 /*
1004  * Field : STATALARMMIN
1005  *
1006  * Register StatAlarmMin contains the minimum count value used in statistics alarm
1007  * comparisons. The number of bits is equal to twice the value set forparameter
1008  * wStatisticsCounter. When parameter statisticsCounterAlarm is set to False,
1009  * StatAlarmMin is reserved.
1010  *
1011  * Field Access Macros:
1012  *
1013  */
1014 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN register field. */
1015 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN_LSB 0
1016 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN register field. */
1017 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN_MSB 31
1018 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN register field. */
1019 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN_WIDTH 32
1020 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN register field value. */
1021 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN_SET_MSK 0xffffffff
1022 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN register field value. */
1023 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN_CLR_MSK 0x00000000
1024 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN register field. */
1025 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN_RESET 0x0
1026 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN field value from a register. */
1027 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN_GET(value) (((value) & 0xffffffff) >> 0)
1028 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN register field value suitable for setting the register. */
1029 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN_SET(value) (((value) << 0) & 0xffffffff)
1030 
1031 #ifndef __ASSEMBLY__
1032 /*
1033  * WARNING: The C register and register group struct declarations are provided for
1034  * convenience and illustrative purposes. They should, however, be used with
1035  * caution as the C language standard provides no guarantees about the alignment or
1036  * atomicity of device memory accesses. The recommended practice for coding device
1037  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1038  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1039  * alt_write_dword() functions for 64 bit registers.
1040  *
1041  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN.
1042  */
1043 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_s
1044 {
1045  volatile uint32_t STATALARMMIN : 32; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN */
1046 };
1047 
1048 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN. */
1049 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_t;
1050 #endif /* __ASSEMBLY__ */
1051 
1052 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN register. */
1053 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_RESET 0x00000000
1054 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN register from the beginning of the component. */
1055 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_OFST 0x2c
1056 
1057 /*
1058  * Register : ddr_T_main_Probe_StatAlarmMax
1059  *
1060  * Register Layout
1061  *
1062  * Bits | Access | Reset | Description
1063  * :-------|:-------|:------|:-----------------------------------------------------------------
1064  * [31:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX
1065  *
1066  */
1067 /*
1068  * Field : STATALARMMAX
1069  *
1070  * Register StatAlarmMax contains the maximum count value used in statistics alarm
1071  * comparisons.The number of bits is equal to twice the value set for parameter
1072  * wStatisticsCounter. When parameter statisticsCounterAlarm is set to False,
1073  * StatAlarmMax is reserved.
1074  *
1075  * Field Access Macros:
1076  *
1077  */
1078 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX register field. */
1079 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX_LSB 0
1080 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX register field. */
1081 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX_MSB 31
1082 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX register field. */
1083 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX_WIDTH 32
1084 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX register field value. */
1085 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX_SET_MSK 0xffffffff
1086 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX register field value. */
1087 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX_CLR_MSK 0x00000000
1088 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX register field. */
1089 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX_RESET 0x0
1090 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX field value from a register. */
1091 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX_GET(value) (((value) & 0xffffffff) >> 0)
1092 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX register field value suitable for setting the register. */
1093 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX_SET(value) (((value) << 0) & 0xffffffff)
1094 
1095 #ifndef __ASSEMBLY__
1096 /*
1097  * WARNING: The C register and register group struct declarations are provided for
1098  * convenience and illustrative purposes. They should, however, be used with
1099  * caution as the C language standard provides no guarantees about the alignment or
1100  * atomicity of device memory accesses. The recommended practice for coding device
1101  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1102  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1103  * alt_write_dword() functions for 64 bit registers.
1104  *
1105  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX.
1106  */
1107 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_s
1108 {
1109  volatile uint32_t STATALARMMAX : 32; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX */
1110 };
1111 
1112 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX. */
1113 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_t;
1114 #endif /* __ASSEMBLY__ */
1115 
1116 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX register. */
1117 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_RESET 0x00000000
1118 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX register from the beginning of the component. */
1119 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_OFST 0x30
1120 
1121 /*
1122  * Register : ddr_T_main_Probe_StatAlarmStatus
1123  *
1124  * Register Layout
1125  *
1126  * Bits | Access | Reset | Description
1127  * :-------|:-------|:--------|:-----------------------------------------------------------------------
1128  * [0] | R | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS
1129  * [31:1] | ??? | Unknown | *UNDEFINED*
1130  *
1131  */
1132 /*
1133  * Field : STATALARMSTATUS
1134  *
1135  * Register StatAlarmStatus is a read-only 1-bit register indicating that at least
1136  * one statistics counter has exceeded the programmed values for registers
1137  * StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values
1138  * stored in register MainCtl fields StatAlarmStatus and AlarmEn. When parameter
1139  * statisticsCounterAlarm is set to False, StatAlarmStatus is reserved.
1140  *
1141  * Field Access Macros:
1142  *
1143  */
1144 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS register field. */
1145 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_LSB 0
1146 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS register field. */
1147 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_MSB 0
1148 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS register field. */
1149 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_WIDTH 1
1150 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS register field value. */
1151 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_SET_MSK 0x00000001
1152 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS register field value. */
1153 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_CLR_MSK 0xfffffffe
1154 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS register field. */
1155 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_RESET 0x0
1156 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS field value from a register. */
1157 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_GET(value) (((value) & 0x00000001) >> 0)
1158 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS register field value suitable for setting the register. */
1159 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_SET(value) (((value) << 0) & 0x00000001)
1160 
1161 #ifndef __ASSEMBLY__
1162 /*
1163  * WARNING: The C register and register group struct declarations are provided for
1164  * convenience and illustrative purposes. They should, however, be used with
1165  * caution as the C language standard provides no guarantees about the alignment or
1166  * atomicity of device memory accesses. The recommended practice for coding device
1167  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1168  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1169  * alt_write_dword() functions for 64 bit registers.
1170  *
1171  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS.
1172  */
1173 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_s
1174 {
1175  const volatile uint32_t STATALARMSTATUS : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS */
1176  uint32_t : 31; /* *UNDEFINED* */
1177 };
1178 
1179 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS. */
1180 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_t;
1181 #endif /* __ASSEMBLY__ */
1182 
1183 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS register. */
1184 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_RESET 0x00000000
1185 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS register from the beginning of the component. */
1186 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_OFST 0x34
1187 
1188 /*
1189  * Register : ddr_T_main_Probe_StatAlarmClr
1190  *
1191  * Register Layout
1192  *
1193  * Bits | Access | Reset | Description
1194  * :-------|:-------|:--------|:-----------------------------------------------------------------
1195  * [0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR
1196  * [31:1] | ??? | Unknown | *UNDEFINED*
1197  *
1198  */
1199 /*
1200  * Field : STATALARMCLR
1201  *
1202  * Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears
1203  * the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to
1204  * False, StatAlarmClr is reserved.NOTE The written value is not stored in
1205  * StatAlarmClr. A read always returns 0.
1206  *
1207  * Field Access Macros:
1208  *
1209  */
1210 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR register field. */
1211 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR_LSB 0
1212 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR register field. */
1213 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR_MSB 0
1214 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR register field. */
1215 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR_WIDTH 1
1216 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR register field value. */
1217 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR_SET_MSK 0x00000001
1218 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR register field value. */
1219 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR_CLR_MSK 0xfffffffe
1220 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR register field. */
1221 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR_RESET 0x0
1222 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR field value from a register. */
1223 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR_GET(value) (((value) & 0x00000001) >> 0)
1224 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR register field value suitable for setting the register. */
1225 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR_SET(value) (((value) << 0) & 0x00000001)
1226 
1227 #ifndef __ASSEMBLY__
1228 /*
1229  * WARNING: The C register and register group struct declarations are provided for
1230  * convenience and illustrative purposes. They should, however, be used with
1231  * caution as the C language standard provides no guarantees about the alignment or
1232  * atomicity of device memory accesses. The recommended practice for coding device
1233  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1234  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1235  * alt_write_dword() functions for 64 bit registers.
1236  *
1237  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR.
1238  */
1239 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_s
1240 {
1241  volatile uint32_t STATALARMCLR : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR */
1242  uint32_t : 31; /* *UNDEFINED* */
1243 };
1244 
1245 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR. */
1246 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_t;
1247 #endif /* __ASSEMBLY__ */
1248 
1249 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR register. */
1250 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_RESET 0x00000000
1251 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR register from the beginning of the component. */
1252 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_OFST 0x38
1253 
1254 /*
1255  * Register : ddr_T_main_Probe_StatAlarmEn
1256  *
1257  * Register Layout
1258  *
1259  * Bits | Access | Reset | Description
1260  * :-------|:-------|:--------|:---------------------------------------------------------------
1261  * [0] | RW | 0x1 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN
1262  * [31:1] | ??? | Unknown | *UNDEFINED*
1263  *
1264  */
1265 /*
1266  * Field : STATALARMEN
1267  *
1268  * Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and
1269  * CtiTrigOut(1) signal interrupts.
1270  *
1271  * Field Access Macros:
1272  *
1273  */
1274 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN register field. */
1275 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN_LSB 0
1276 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN register field. */
1277 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN_MSB 0
1278 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN register field. */
1279 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN_WIDTH 1
1280 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN register field value. */
1281 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN_SET_MSK 0x00000001
1282 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN register field value. */
1283 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN_CLR_MSK 0xfffffffe
1284 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN register field. */
1285 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN_RESET 0x1
1286 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN field value from a register. */
1287 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN_GET(value) (((value) & 0x00000001) >> 0)
1288 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN register field value suitable for setting the register. */
1289 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN_SET(value) (((value) << 0) & 0x00000001)
1290 
1291 #ifndef __ASSEMBLY__
1292 /*
1293  * WARNING: The C register and register group struct declarations are provided for
1294  * convenience and illustrative purposes. They should, however, be used with
1295  * caution as the C language standard provides no guarantees about the alignment or
1296  * atomicity of device memory accesses. The recommended practice for coding device
1297  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1298  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1299  * alt_write_dword() functions for 64 bit registers.
1300  *
1301  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN.
1302  */
1303 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_s
1304 {
1305  volatile uint32_t STATALARMEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN */
1306  uint32_t : 31; /* *UNDEFINED* */
1307 };
1308 
1309 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN. */
1310 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_t;
1311 #endif /* __ASSEMBLY__ */
1312 
1313 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN register. */
1314 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_RESET 0x00000001
1315 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN register from the beginning of the component. */
1316 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_OFST 0x3c
1317 
1318 /*
1319  * Register : ddr_T_main_Probe_Filters_0_RouteIdBase
1320  *
1321  * Register Layout
1322  *
1323  * Bits | Access | Reset | Description
1324  * :--------|:-------|:--------|:-----------------------------------------------------------------------------------
1325  * [13:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE
1326  * [31:14] | ??? | Unknown | *UNDEFINED*
1327  *
1328  */
1329 /*
1330  * Field : FILTERS_0_ROUTEIDBASE
1331  *
1332  * Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to
1333  * filter packets.
1334  *
1335  * Field Access Macros:
1336  *
1337  */
1338 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE register field. */
1339 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_LSB 0
1340 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE register field. */
1341 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_MSB 13
1342 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE register field. */
1343 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_WIDTH 14
1344 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE register field value. */
1345 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_SET_MSK 0x00003fff
1346 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE register field value. */
1347 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_CLR_MSK 0xffffc000
1348 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE register field. */
1349 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_RESET 0x0
1350 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE field value from a register. */
1351 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_GET(value) (((value) & 0x00003fff) >> 0)
1352 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE register field value suitable for setting the register. */
1353 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_SET(value) (((value) << 0) & 0x00003fff)
1354 
1355 #ifndef __ASSEMBLY__
1356 /*
1357  * WARNING: The C register and register group struct declarations are provided for
1358  * convenience and illustrative purposes. They should, however, be used with
1359  * caution as the C language standard provides no guarantees about the alignment or
1360  * atomicity of device memory accesses. The recommended practice for coding device
1361  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1362  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1363  * alt_write_dword() functions for 64 bit registers.
1364  *
1365  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE.
1366  */
1367 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_s
1368 {
1369  volatile uint32_t FILTERS_0_ROUTEIDBASE : 14; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE */
1370  uint32_t : 18; /* *UNDEFINED* */
1371 };
1372 
1373 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE. */
1374 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_t;
1375 #endif /* __ASSEMBLY__ */
1376 
1377 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE register. */
1378 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_RESET 0x00000000
1379 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE register from the beginning of the component. */
1380 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_OFST 0x44
1381 
1382 /*
1383  * Register : ddr_T_main_Probe_Filters_0_RouteIdMask
1384  *
1385  * Register Layout
1386  *
1387  * Bits | Access | Reset | Description
1388  * :--------|:-------|:--------|:-----------------------------------------------------------------------------------
1389  * [13:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK
1390  * [31:14] | ??? | Unknown | *UNDEFINED*
1391  *
1392  */
1393 /*
1394  * Field : FILTERS_0_ROUTEIDMASK
1395  *
1396  * Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter
1397  * packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &
1398  * RouteIdMask = RouteIdBase & RouteIdMask.
1399  *
1400  * Field Access Macros:
1401  *
1402  */
1403 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK register field. */
1404 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_LSB 0
1405 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK register field. */
1406 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_MSB 13
1407 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK register field. */
1408 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_WIDTH 14
1409 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK register field value. */
1410 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_SET_MSK 0x00003fff
1411 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK register field value. */
1412 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_CLR_MSK 0xffffc000
1413 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK register field. */
1414 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_RESET 0x0
1415 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK field value from a register. */
1416 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_GET(value) (((value) & 0x00003fff) >> 0)
1417 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK register field value suitable for setting the register. */
1418 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_SET(value) (((value) << 0) & 0x00003fff)
1419 
1420 #ifndef __ASSEMBLY__
1421 /*
1422  * WARNING: The C register and register group struct declarations are provided for
1423  * convenience and illustrative purposes. They should, however, be used with
1424  * caution as the C language standard provides no guarantees about the alignment or
1425  * atomicity of device memory accesses. The recommended practice for coding device
1426  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1427  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1428  * alt_write_dword() functions for 64 bit registers.
1429  *
1430  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK.
1431  */
1432 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_s
1433 {
1434  volatile uint32_t FILTERS_0_ROUTEIDMASK : 14; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK */
1435  uint32_t : 18; /* *UNDEFINED* */
1436 };
1437 
1438 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK. */
1439 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_t;
1440 #endif /* __ASSEMBLY__ */
1441 
1442 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK register. */
1443 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_RESET 0x00000000
1444 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK register from the beginning of the component. */
1445 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_OFST 0x48
1446 
1447 /*
1448  * Register : ddr_T_main_Probe_Filters_0_AddrBase_Low
1449  *
1450  * Register Layout
1451  *
1452  * Bits | Access | Reset | Description
1453  * :-------|:-------|:------|:-------------------------------------------------------------------------------------
1454  * [31:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW
1455  *
1456  */
1457 /*
1458  * Field : FILTERS_0_ADDRBASE_LOW
1459  *
1460  * Address LSB register.
1461  *
1462  * Field Access Macros:
1463  *
1464  */
1465 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW register field. */
1466 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_LSB 0
1467 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW register field. */
1468 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_MSB 31
1469 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW register field. */
1470 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_WIDTH 32
1471 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW register field value. */
1472 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_SET_MSK 0xffffffff
1473 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW register field value. */
1474 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_CLR_MSK 0x00000000
1475 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW register field. */
1476 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_RESET 0x0
1477 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW field value from a register. */
1478 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
1479 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW register field value suitable for setting the register. */
1480 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
1481 
1482 #ifndef __ASSEMBLY__
1483 /*
1484  * WARNING: The C register and register group struct declarations are provided for
1485  * convenience and illustrative purposes. They should, however, be used with
1486  * caution as the C language standard provides no guarantees about the alignment or
1487  * atomicity of device memory accesses. The recommended practice for coding device
1488  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1489  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1490  * alt_write_dword() functions for 64 bit registers.
1491  *
1492  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW.
1493  */
1494 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_s
1495 {
1496  volatile uint32_t FILTERS_0_ADDRBASE_LOW : 32; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW */
1497 };
1498 
1499 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW. */
1500 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_t;
1501 #endif /* __ASSEMBLY__ */
1502 
1503 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW register. */
1504 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_RESET 0x00000000
1505 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW register from the beginning of the component. */
1506 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_OFST 0x4c
1507 
1508 /*
1509  * Register : ddr_T_main_Probe_Filters_0_AddrBase_High
1510  *
1511  * Register Layout
1512  *
1513  * Bits | Access | Reset | Description
1514  * :-------|:-------|:--------|:---------------------------------------------------------------------------------------
1515  * [4:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH
1516  * [31:5] | ??? | Unknown | *UNDEFINED*
1517  *
1518  */
1519 /*
1520  * Field : FILTERS_0_ADDRBASE_HIGH
1521  *
1522  * Address MSB register.
1523  *
1524  * Field Access Macros:
1525  *
1526  */
1527 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH register field. */
1528 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_LSB 0
1529 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH register field. */
1530 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_MSB 4
1531 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH register field. */
1532 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_WIDTH 5
1533 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH register field value. */
1534 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_SET_MSK 0x0000001f
1535 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH register field value. */
1536 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_CLR_MSK 0xffffffe0
1537 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH register field. */
1538 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_RESET 0x0
1539 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH field value from a register. */
1540 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_GET(value) (((value) & 0x0000001f) >> 0)
1541 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH register field value suitable for setting the register. */
1542 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_SET(value) (((value) << 0) & 0x0000001f)
1543 
1544 #ifndef __ASSEMBLY__
1545 /*
1546  * WARNING: The C register and register group struct declarations are provided for
1547  * convenience and illustrative purposes. They should, however, be used with
1548  * caution as the C language standard provides no guarantees about the alignment or
1549  * atomicity of device memory accesses. The recommended practice for coding device
1550  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1551  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1552  * alt_write_dword() functions for 64 bit registers.
1553  *
1554  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH.
1555  */
1556 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_s
1557 {
1558  volatile uint32_t FILTERS_0_ADDRBASE_HIGH : 5; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH */
1559  uint32_t : 27; /* *UNDEFINED* */
1560 };
1561 
1562 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH. */
1563 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_t;
1564 #endif /* __ASSEMBLY__ */
1565 
1566 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH register. */
1567 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_RESET 0x00000000
1568 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH register from the beginning of the component. */
1569 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_OFST 0x50
1570 
1571 /*
1572  * Register : ddr_T_main_Probe_Filters_0_WindowSize
1573  *
1574  * Register Layout
1575  *
1576  * Bits | Access | Reset | Description
1577  * :-------|:-------|:--------|:---------------------------------------------------------------------------------
1578  * [5:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE
1579  * [31:6] | ??? | Unknown | *UNDEFINED*
1580  *
1581  */
1582 /*
1583  * Field : FILTERS_0_WINDOWSIZE
1584  *
1585  * Register WindowSize contains the encoded address mask used to filter packets.
1586  * The effective Mask value is equal to ~(2max(WindowSize, packet.Len) - 1). A
1587  * packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows
1588  * filteringof packets having an intersection with the AddrBase/WindowSize burst
1589  * aligned region, even if the region is smaller than the packet.
1590  *
1591  * Field Access Macros:
1592  *
1593  */
1594 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE register field. */
1595 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_LSB 0
1596 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE register field. */
1597 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_MSB 5
1598 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE register field. */
1599 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_WIDTH 6
1600 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE register field value. */
1601 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_SET_MSK 0x0000003f
1602 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE register field value. */
1603 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_CLR_MSK 0xffffffc0
1604 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE register field. */
1605 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_RESET 0x0
1606 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE field value from a register. */
1607 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
1608 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE register field value suitable for setting the register. */
1609 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
1610 
1611 #ifndef __ASSEMBLY__
1612 /*
1613  * WARNING: The C register and register group struct declarations are provided for
1614  * convenience and illustrative purposes. They should, however, be used with
1615  * caution as the C language standard provides no guarantees about the alignment or
1616  * atomicity of device memory accesses. The recommended practice for coding device
1617  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1618  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1619  * alt_write_dword() functions for 64 bit registers.
1620  *
1621  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE.
1622  */
1623 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_s
1624 {
1625  volatile uint32_t FILTERS_0_WINDOWSIZE : 6; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE */
1626  uint32_t : 26; /* *UNDEFINED* */
1627 };
1628 
1629 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE. */
1630 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_t;
1631 #endif /* __ASSEMBLY__ */
1632 
1633 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE register. */
1634 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_RESET 0x00000000
1635 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE register from the beginning of the component. */
1636 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_OFST 0x54
1637 
1638 /*
1639  * Register : ddr_T_main_Probe_Filters_0_SecurityBase
1640  *
1641  * Register Layout
1642  *
1643  * Bits | Access | Reset | Description
1644  * :-------|:-------|:--------|:-------------------------------------------------------------------------------------
1645  * [1:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE
1646  * [31:2] | ??? | Unknown | *UNDEFINED*
1647  *
1648  */
1649 /*
1650  * Field : FILTERS_0_SECURITYBASE
1651  *
1652  * Register SecurityBase contains the security base used to filter packets.
1653  *
1654  * Field Access Macros:
1655  *
1656  */
1657 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE register field. */
1658 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_LSB 0
1659 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE register field. */
1660 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_MSB 1
1661 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE register field. */
1662 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_WIDTH 2
1663 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE register field value. */
1664 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_SET_MSK 0x00000003
1665 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE register field value. */
1666 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_CLR_MSK 0xfffffffc
1667 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE register field. */
1668 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_RESET 0x0
1669 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE field value from a register. */
1670 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_GET(value) (((value) & 0x00000003) >> 0)
1671 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE register field value suitable for setting the register. */
1672 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_SET(value) (((value) << 0) & 0x00000003)
1673 
1674 #ifndef __ASSEMBLY__
1675 /*
1676  * WARNING: The C register and register group struct declarations are provided for
1677  * convenience and illustrative purposes. They should, however, be used with
1678  * caution as the C language standard provides no guarantees about the alignment or
1679  * atomicity of device memory accesses. The recommended practice for coding device
1680  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1681  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1682  * alt_write_dword() functions for 64 bit registers.
1683  *
1684  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE.
1685  */
1686 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_s
1687 {
1688  volatile uint32_t FILTERS_0_SECURITYBASE : 2; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE */
1689  uint32_t : 30; /* *UNDEFINED* */
1690 };
1691 
1692 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE. */
1693 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_t;
1694 #endif /* __ASSEMBLY__ */
1695 
1696 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE register. */
1697 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_RESET 0x00000000
1698 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE register from the beginning of the component. */
1699 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_OFST 0x58
1700 
1701 /*
1702  * Register : ddr_T_main_Probe_Filters_0_SecurityMask
1703  *
1704  * Register Layout
1705  *
1706  * Bits | Access | Reset | Description
1707  * :-------|:-------|:--------|:-------------------------------------------------------------------------------------
1708  * [1:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK
1709  * [31:2] | ??? | Unknown | *UNDEFINED*
1710  *
1711  */
1712 /*
1713  * Field : FILTERS_0_SECURITYMASK
1714  *
1715  * Register SecurityMask is contains the security mask used to filter packets. A
1716  * packet is a candidate when: packet.Security & SecurityMask = SecurityBase &
1717  * SecurityMasks.
1718  *
1719  * Field Access Macros:
1720  *
1721  */
1722 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK register field. */
1723 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_LSB 0
1724 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK register field. */
1725 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_MSB 1
1726 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK register field. */
1727 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_WIDTH 2
1728 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK register field value. */
1729 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_SET_MSK 0x00000003
1730 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK register field value. */
1731 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_CLR_MSK 0xfffffffc
1732 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK register field. */
1733 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_RESET 0x0
1734 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK field value from a register. */
1735 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_GET(value) (((value) & 0x00000003) >> 0)
1736 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK register field value suitable for setting the register. */
1737 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_SET(value) (((value) << 0) & 0x00000003)
1738 
1739 #ifndef __ASSEMBLY__
1740 /*
1741  * WARNING: The C register and register group struct declarations are provided for
1742  * convenience and illustrative purposes. They should, however, be used with
1743  * caution as the C language standard provides no guarantees about the alignment or
1744  * atomicity of device memory accesses. The recommended practice for coding device
1745  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1746  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1747  * alt_write_dword() functions for 64 bit registers.
1748  *
1749  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK.
1750  */
1751 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_s
1752 {
1753  volatile uint32_t FILTERS_0_SECURITYMASK : 2; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK */
1754  uint32_t : 30; /* *UNDEFINED* */
1755 };
1756 
1757 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK. */
1758 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_t;
1759 #endif /* __ASSEMBLY__ */
1760 
1761 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK register. */
1762 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_RESET 0x00000000
1763 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK register from the beginning of the component. */
1764 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_OFST 0x5c
1765 
1766 /*
1767  * Register : ddr_T_main_Probe_Filters_0_Opcode
1768  *
1769  * Packet Probe register Opcode is a 4-bit register that selects candidate packets
1770  * based on packet opcodes (0 disables the filter):
1771  *
1772  * Register Layout
1773  *
1774  * Bits | Access | Reset | Description
1775  * :-------|:-------|:--------|:---------------------------------------------------------------
1776  * [0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN
1777  * [1] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN
1778  * [2] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN
1779  * [3] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN
1780  * [31:4] | ??? | Unknown | *UNDEFINED*
1781  *
1782  */
1783 /*
1784  * Field : RDEN
1785  *
1786  * Selects RD packets.
1787  *
1788  * Field Access Macros:
1789  *
1790  */
1791 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN register field. */
1792 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_LSB 0
1793 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN register field. */
1794 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_MSB 0
1795 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN register field. */
1796 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_WIDTH 1
1797 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN register field value. */
1798 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_SET_MSK 0x00000001
1799 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN register field value. */
1800 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_CLR_MSK 0xfffffffe
1801 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN register field. */
1802 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_RESET 0x0
1803 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN field value from a register. */
1804 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
1805 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN register field value suitable for setting the register. */
1806 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
1807 
1808 /*
1809  * Field : WREN
1810  *
1811  * Selects WR packets.
1812  *
1813  * Field Access Macros:
1814  *
1815  */
1816 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN register field. */
1817 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN_LSB 1
1818 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN register field. */
1819 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN_MSB 1
1820 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN register field. */
1821 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN_WIDTH 1
1822 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN register field value. */
1823 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN_SET_MSK 0x00000002
1824 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN register field value. */
1825 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN_CLR_MSK 0xfffffffd
1826 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN register field. */
1827 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN_RESET 0x0
1828 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN field value from a register. */
1829 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
1830 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN register field value suitable for setting the register. */
1831 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
1832 
1833 /*
1834  * Field : LOCKEN
1835  *
1836  * Selects RDX-WR, RDL, WRC and Linked sequence.
1837  *
1838  * Field Access Macros:
1839  *
1840  */
1841 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN register field. */
1842 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_LSB 2
1843 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN register field. */
1844 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_MSB 2
1845 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN register field. */
1846 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_WIDTH 1
1847 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN register field value. */
1848 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_SET_MSK 0x00000004
1849 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN register field value. */
1850 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
1851 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN register field. */
1852 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_RESET 0x0
1853 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN field value from a register. */
1854 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
1855 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN register field value suitable for setting the register. */
1856 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
1857 
1858 /*
1859  * Field : URGEN
1860  *
1861  * Selects URG packets (urgency).
1862  *
1863  * Field Access Macros:
1864  *
1865  */
1866 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN register field. */
1867 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_LSB 3
1868 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN register field. */
1869 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_MSB 3
1870 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN register field. */
1871 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_WIDTH 1
1872 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN register field value. */
1873 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_SET_MSK 0x00000008
1874 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN register field value. */
1875 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_CLR_MSK 0xfffffff7
1876 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN register field. */
1877 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_RESET 0x0
1878 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN field value from a register. */
1879 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
1880 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN register field value suitable for setting the register. */
1881 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
1882 
1883 #ifndef __ASSEMBLY__
1884 /*
1885  * WARNING: The C register and register group struct declarations are provided for
1886  * convenience and illustrative purposes. They should, however, be used with
1887  * caution as the C language standard provides no guarantees about the alignment or
1888  * atomicity of device memory accesses. The recommended practice for coding device
1889  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1890  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1891  * alt_write_dword() functions for 64 bit registers.
1892  *
1893  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE.
1894  */
1895 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_s
1896 {
1897  volatile uint32_t RDEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN */
1898  volatile uint32_t WREN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN */
1899  volatile uint32_t LOCKEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN */
1900  volatile uint32_t URGEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN */
1901  uint32_t : 28; /* *UNDEFINED* */
1902 };
1903 
1904 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE. */
1905 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_t;
1906 #endif /* __ASSEMBLY__ */
1907 
1908 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE register. */
1909 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RESET 0x00000000
1910 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE register from the beginning of the component. */
1911 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_OFST 0x60
1912 
1913 /*
1914  * Register : ddr_T_main_Probe_Filters_0_Status
1915  *
1916  * Register Status is 2-bit register that selects candidate packets based on packet
1917  * status.
1918  *
1919  * Register Layout
1920  *
1921  * Bits | Access | Reset | Description
1922  * :-------|:-------|:--------|:--------------------------------------------------------------
1923  * [0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN
1924  * [1] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN
1925  * [31:2] | ??? | Unknown | *UNDEFINED*
1926  *
1927  */
1928 /*
1929  * Field : REQEN
1930  *
1931  * Selects REQ status packets.
1932  *
1933  * Field Access Macros:
1934  *
1935  */
1936 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN register field. */
1937 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN_LSB 0
1938 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN register field. */
1939 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN_MSB 0
1940 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN register field. */
1941 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN_WIDTH 1
1942 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN register field value. */
1943 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN_SET_MSK 0x00000001
1944 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN register field value. */
1945 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN_CLR_MSK 0xfffffffe
1946 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN register field. */
1947 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN_RESET 0x0
1948 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN field value from a register. */
1949 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN_GET(value) (((value) & 0x00000001) >> 0)
1950 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN register field value suitable for setting the register. */
1951 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN_SET(value) (((value) << 0) & 0x00000001)
1952 
1953 /*
1954  * Field : RSPEN
1955  *
1956  * Selects RSP and FAIL-CONT status packets.
1957  *
1958  * Field Access Macros:
1959  *
1960  */
1961 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN register field. */
1962 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_LSB 1
1963 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN register field. */
1964 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_MSB 1
1965 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN register field. */
1966 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_WIDTH 1
1967 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN register field value. */
1968 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_SET_MSK 0x00000002
1969 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN register field value. */
1970 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_CLR_MSK 0xfffffffd
1971 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN register field. */
1972 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_RESET 0x0
1973 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN field value from a register. */
1974 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
1975 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN register field value suitable for setting the register. */
1976 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_SET(value) (((value) << 1) & 0x00000002)
1977 
1978 #ifndef __ASSEMBLY__
1979 /*
1980  * WARNING: The C register and register group struct declarations are provided for
1981  * convenience and illustrative purposes. They should, however, be used with
1982  * caution as the C language standard provides no guarantees about the alignment or
1983  * atomicity of device memory accesses. The recommended practice for coding device
1984  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1985  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1986  * alt_write_dword() functions for 64 bit registers.
1987  *
1988  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS.
1989  */
1990 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_s
1991 {
1992  volatile uint32_t REQEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN */
1993  volatile uint32_t RSPEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN */
1994  uint32_t : 30; /* *UNDEFINED* */
1995 };
1996 
1997 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS. */
1998 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_t;
1999 #endif /* __ASSEMBLY__ */
2000 
2001 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS register. */
2002 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RESET 0x00000000
2003 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS register from the beginning of the component. */
2004 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_OFST 0x64
2005 
2006 /*
2007  * Register : ddr_T_main_Probe_Filters_0_Length
2008  *
2009  * Register Layout
2010  *
2011  * Bits | Access | Reset | Description
2012  * :-------|:-------|:--------|:-------------------------------------------------------------------------
2013  * [3:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH
2014  * [31:4] | ??? | Unknown | *UNDEFINED*
2015  *
2016  */
2017 /*
2018  * Field : FILTERS_0_LENGTH
2019  *
2020  * Register Length is 4-bit register that selects candidate packets if their number
2021  * of bytes is less than or equal to 2**Length.
2022  *
2023  * Field Access Macros:
2024  *
2025  */
2026 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH register field. */
2027 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_LSB 0
2028 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH register field. */
2029 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_MSB 3
2030 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH register field. */
2031 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_WIDTH 4
2032 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH register field value. */
2033 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_SET_MSK 0x0000000f
2034 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH register field value. */
2035 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_CLR_MSK 0xfffffff0
2036 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH register field. */
2037 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_RESET 0x0
2038 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH field value from a register. */
2039 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_GET(value) (((value) & 0x0000000f) >> 0)
2040 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH register field value suitable for setting the register. */
2041 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_SET(value) (((value) << 0) & 0x0000000f)
2042 
2043 #ifndef __ASSEMBLY__
2044 /*
2045  * WARNING: The C register and register group struct declarations are provided for
2046  * convenience and illustrative purposes. They should, however, be used with
2047  * caution as the C language standard provides no guarantees about the alignment or
2048  * atomicity of device memory accesses. The recommended practice for coding device
2049  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2050  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2051  * alt_write_dword() functions for 64 bit registers.
2052  *
2053  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH.
2054  */
2055 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_s
2056 {
2057  volatile uint32_t FILTERS_0_LENGTH : 4; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH */
2058  uint32_t : 28; /* *UNDEFINED* */
2059 };
2060 
2061 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH. */
2062 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_t;
2063 #endif /* __ASSEMBLY__ */
2064 
2065 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH register. */
2066 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_RESET 0x00000000
2067 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH register from the beginning of the component. */
2068 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_OFST 0x68
2069 
2070 /*
2071  * Register : ddr_T_main_Probe_Filters_0_Urgency
2072  *
2073  * Register Layout
2074  *
2075  * Bits | Access | Reset | Description
2076  * :-------|:-------|:--------|:---------------------------------------------------------------------------
2077  * [1:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY
2078  * [31:2] | ??? | Unknown | *UNDEFINED*
2079  *
2080  */
2081 /*
2082  * Field : FILTERS_0_URGENCY
2083  *
2084  * Register Urgency contains the minimum urgency level used to filter packets. A
2085  * packet is a candidate when its socket urgency is greater than or equal to the
2086  * urgency specified in the register.
2087  *
2088  * Field Access Macros:
2089  *
2090  */
2091 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY register field. */
2092 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_LSB 0
2093 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY register field. */
2094 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_MSB 1
2095 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY register field. */
2096 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_WIDTH 2
2097 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY register field value. */
2098 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_SET_MSK 0x00000003
2099 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY register field value. */
2100 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_CLR_MSK 0xfffffffc
2101 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY register field. */
2102 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_RESET 0x0
2103 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY field value from a register. */
2104 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
2105 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY register field value suitable for setting the register. */
2106 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_SET(value) (((value) << 0) & 0x00000003)
2107 
2108 #ifndef __ASSEMBLY__
2109 /*
2110  * WARNING: The C register and register group struct declarations are provided for
2111  * convenience and illustrative purposes. They should, however, be used with
2112  * caution as the C language standard provides no guarantees about the alignment or
2113  * atomicity of device memory accesses. The recommended practice for coding device
2114  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2115  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2116  * alt_write_dword() functions for 64 bit registers.
2117  *
2118  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY.
2119  */
2120 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_s
2121 {
2122  volatile uint32_t FILTERS_0_URGENCY : 2; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY */
2123  uint32_t : 30; /* *UNDEFINED* */
2124 };
2125 
2126 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY. */
2127 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_t;
2128 #endif /* __ASSEMBLY__ */
2129 
2130 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY register. */
2131 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_RESET 0x00000000
2132 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY register from the beginning of the component. */
2133 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_OFST 0x6c
2134 
2135 /*
2136  * Register : ddr_T_main_Probe_Filters_1_RouteIdBase
2137  *
2138  * Register Layout
2139  *
2140  * Bits | Access | Reset | Description
2141  * :--------|:-------|:--------|:-----------------------------------------------------------------------------------
2142  * [13:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE
2143  * [31:14] | ??? | Unknown | *UNDEFINED*
2144  *
2145  */
2146 /*
2147  * Field : FILTERS_1_ROUTEIDBASE
2148  *
2149  * Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to
2150  * filter packets.
2151  *
2152  * Field Access Macros:
2153  *
2154  */
2155 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE register field. */
2156 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_LSB 0
2157 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE register field. */
2158 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_MSB 13
2159 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE register field. */
2160 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_WIDTH 14
2161 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE register field value. */
2162 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_SET_MSK 0x00003fff
2163 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE register field value. */
2164 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_CLR_MSK 0xffffc000
2165 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE register field. */
2166 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_RESET 0x0
2167 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE field value from a register. */
2168 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_GET(value) (((value) & 0x00003fff) >> 0)
2169 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE register field value suitable for setting the register. */
2170 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_SET(value) (((value) << 0) & 0x00003fff)
2171 
2172 #ifndef __ASSEMBLY__
2173 /*
2174  * WARNING: The C register and register group struct declarations are provided for
2175  * convenience and illustrative purposes. They should, however, be used with
2176  * caution as the C language standard provides no guarantees about the alignment or
2177  * atomicity of device memory accesses. The recommended practice for coding device
2178  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2179  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2180  * alt_write_dword() functions for 64 bit registers.
2181  *
2182  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE.
2183  */
2184 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_s
2185 {
2186  volatile uint32_t FILTERS_1_ROUTEIDBASE : 14; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE */
2187  uint32_t : 18; /* *UNDEFINED* */
2188 };
2189 
2190 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE. */
2191 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_t;
2192 #endif /* __ASSEMBLY__ */
2193 
2194 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE register. */
2195 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_RESET 0x00000000
2196 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE register from the beginning of the component. */
2197 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_OFST 0x80
2198 
2199 /*
2200  * Register : ddr_T_main_Probe_Filters_1_RouteIdMask
2201  *
2202  * Register Layout
2203  *
2204  * Bits | Access | Reset | Description
2205  * :--------|:-------|:--------|:-----------------------------------------------------------------------------------
2206  * [13:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK
2207  * [31:14] | ??? | Unknown | *UNDEFINED*
2208  *
2209  */
2210 /*
2211  * Field : FILTERS_1_ROUTEIDMASK
2212  *
2213  * Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter
2214  * packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &
2215  * RouteIdMask = RouteIdBase & RouteIdMask.
2216  *
2217  * Field Access Macros:
2218  *
2219  */
2220 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK register field. */
2221 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_LSB 0
2222 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK register field. */
2223 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_MSB 13
2224 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK register field. */
2225 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_WIDTH 14
2226 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK register field value. */
2227 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_SET_MSK 0x00003fff
2228 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK register field value. */
2229 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_CLR_MSK 0xffffc000
2230 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK register field. */
2231 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_RESET 0x0
2232 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK field value from a register. */
2233 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_GET(value) (((value) & 0x00003fff) >> 0)
2234 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK register field value suitable for setting the register. */
2235 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_SET(value) (((value) << 0) & 0x00003fff)
2236 
2237 #ifndef __ASSEMBLY__
2238 /*
2239  * WARNING: The C register and register group struct declarations are provided for
2240  * convenience and illustrative purposes. They should, however, be used with
2241  * caution as the C language standard provides no guarantees about the alignment or
2242  * atomicity of device memory accesses. The recommended practice for coding device
2243  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2244  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2245  * alt_write_dword() functions for 64 bit registers.
2246  *
2247  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK.
2248  */
2249 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_s
2250 {
2251  volatile uint32_t FILTERS_1_ROUTEIDMASK : 14; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK */
2252  uint32_t : 18; /* *UNDEFINED* */
2253 };
2254 
2255 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK. */
2256 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_t;
2257 #endif /* __ASSEMBLY__ */
2258 
2259 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK register. */
2260 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_RESET 0x00000000
2261 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK register from the beginning of the component. */
2262 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_OFST 0x84
2263 
2264 /*
2265  * Register : ddr_T_main_Probe_Filters_1_AddrBase_Low
2266  *
2267  * Register Layout
2268  *
2269  * Bits | Access | Reset | Description
2270  * :-------|:-------|:------|:-------------------------------------------------------------------------------------
2271  * [31:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW
2272  *
2273  */
2274 /*
2275  * Field : FILTERS_1_ADDRBASE_LOW
2276  *
2277  * Address LSB register.
2278  *
2279  * Field Access Macros:
2280  *
2281  */
2282 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW register field. */
2283 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_LSB 0
2284 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW register field. */
2285 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_MSB 31
2286 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW register field. */
2287 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_WIDTH 32
2288 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW register field value. */
2289 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_SET_MSK 0xffffffff
2290 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW register field value. */
2291 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_CLR_MSK 0x00000000
2292 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW register field. */
2293 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_RESET 0x0
2294 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW field value from a register. */
2295 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
2296 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW register field value suitable for setting the register. */
2297 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
2298 
2299 #ifndef __ASSEMBLY__
2300 /*
2301  * WARNING: The C register and register group struct declarations are provided for
2302  * convenience and illustrative purposes. They should, however, be used with
2303  * caution as the C language standard provides no guarantees about the alignment or
2304  * atomicity of device memory accesses. The recommended practice for coding device
2305  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2306  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2307  * alt_write_dword() functions for 64 bit registers.
2308  *
2309  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW.
2310  */
2311 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_s
2312 {
2313  volatile uint32_t FILTERS_1_ADDRBASE_LOW : 32; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW */
2314 };
2315 
2316 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW. */
2317 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_t;
2318 #endif /* __ASSEMBLY__ */
2319 
2320 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW register. */
2321 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_RESET 0x00000000
2322 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW register from the beginning of the component. */
2323 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_OFST 0x88
2324 
2325 /*
2326  * Register : ddr_T_main_Probe_Filters_1_AddrBase_High
2327  *
2328  * Register Layout
2329  *
2330  * Bits | Access | Reset | Description
2331  * :-------|:-------|:--------|:---------------------------------------------------------------------------------------
2332  * [4:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH
2333  * [31:5] | ??? | Unknown | *UNDEFINED*
2334  *
2335  */
2336 /*
2337  * Field : FILTERS_1_ADDRBASE_HIGH
2338  *
2339  * Address MSB register.
2340  *
2341  * Field Access Macros:
2342  *
2343  */
2344 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH register field. */
2345 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_LSB 0
2346 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH register field. */
2347 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_MSB 4
2348 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH register field. */
2349 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_WIDTH 5
2350 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH register field value. */
2351 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_SET_MSK 0x0000001f
2352 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH register field value. */
2353 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_CLR_MSK 0xffffffe0
2354 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH register field. */
2355 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_RESET 0x0
2356 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH field value from a register. */
2357 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_GET(value) (((value) & 0x0000001f) >> 0)
2358 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH register field value suitable for setting the register. */
2359 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_SET(value) (((value) << 0) & 0x0000001f)
2360 
2361 #ifndef __ASSEMBLY__
2362 /*
2363  * WARNING: The C register and register group struct declarations are provided for
2364  * convenience and illustrative purposes. They should, however, be used with
2365  * caution as the C language standard provides no guarantees about the alignment or
2366  * atomicity of device memory accesses. The recommended practice for coding device
2367  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2368  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2369  * alt_write_dword() functions for 64 bit registers.
2370  *
2371  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH.
2372  */
2373 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_s
2374 {
2375  volatile uint32_t FILTERS_1_ADDRBASE_HIGH : 5; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH */
2376  uint32_t : 27; /* *UNDEFINED* */
2377 };
2378 
2379 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH. */
2380 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_t;
2381 #endif /* __ASSEMBLY__ */
2382 
2383 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH register. */
2384 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_RESET 0x00000000
2385 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH register from the beginning of the component. */
2386 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_OFST 0x8c
2387 
2388 /*
2389  * Register : ddr_T_main_Probe_Filters_1_WindowSize
2390  *
2391  * Register Layout
2392  *
2393  * Bits | Access | Reset | Description
2394  * :-------|:-------|:--------|:---------------------------------------------------------------------------------
2395  * [5:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE
2396  * [31:6] | ??? | Unknown | *UNDEFINED*
2397  *
2398  */
2399 /*
2400  * Field : FILTERS_1_WINDOWSIZE
2401  *
2402  * Register WindowSize contains the encoded address mask used to filter packets.
2403  * The effective Mask value is equal to ~(2max(WindowSize, packet.Len) - 1). A
2404  * packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows
2405  * filteringof packets having an intersection with the AddrBase/WindowSize burst
2406  * aligned region, even if the region is smaller than the packet.
2407  *
2408  * Field Access Macros:
2409  *
2410  */
2411 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE register field. */
2412 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_LSB 0
2413 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE register field. */
2414 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_MSB 5
2415 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE register field. */
2416 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_WIDTH 6
2417 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE register field value. */
2418 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_SET_MSK 0x0000003f
2419 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE register field value. */
2420 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_CLR_MSK 0xffffffc0
2421 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE register field. */
2422 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_RESET 0x0
2423 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE field value from a register. */
2424 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
2425 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE register field value suitable for setting the register. */
2426 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
2427 
2428 #ifndef __ASSEMBLY__
2429 /*
2430  * WARNING: The C register and register group struct declarations are provided for
2431  * convenience and illustrative purposes. They should, however, be used with
2432  * caution as the C language standard provides no guarantees about the alignment or
2433  * atomicity of device memory accesses. The recommended practice for coding device
2434  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2435  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2436  * alt_write_dword() functions for 64 bit registers.
2437  *
2438  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE.
2439  */
2440 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_s
2441 {
2442  volatile uint32_t FILTERS_1_WINDOWSIZE : 6; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE */
2443  uint32_t : 26; /* *UNDEFINED* */
2444 };
2445 
2446 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE. */
2447 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_t;
2448 #endif /* __ASSEMBLY__ */
2449 
2450 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE register. */
2451 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_RESET 0x00000000
2452 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE register from the beginning of the component. */
2453 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_OFST 0x90
2454 
2455 /*
2456  * Register : ddr_T_main_Probe_Filters_1_SecurityBase
2457  *
2458  * Register Layout
2459  *
2460  * Bits | Access | Reset | Description
2461  * :-------|:-------|:--------|:-------------------------------------------------------------------------------------
2462  * [1:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE
2463  * [31:2] | ??? | Unknown | *UNDEFINED*
2464  *
2465  */
2466 /*
2467  * Field : FILTERS_1_SECURITYBASE
2468  *
2469  * Register SecurityBase contains the security base used to filter packets.
2470  *
2471  * Field Access Macros:
2472  *
2473  */
2474 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE register field. */
2475 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_LSB 0
2476 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE register field. */
2477 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_MSB 1
2478 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE register field. */
2479 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_WIDTH 2
2480 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE register field value. */
2481 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_SET_MSK 0x00000003
2482 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE register field value. */
2483 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_CLR_MSK 0xfffffffc
2484 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE register field. */
2485 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_RESET 0x0
2486 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE field value from a register. */
2487 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_GET(value) (((value) & 0x00000003) >> 0)
2488 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE register field value suitable for setting the register. */
2489 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_SET(value) (((value) << 0) & 0x00000003)
2490 
2491 #ifndef __ASSEMBLY__
2492 /*
2493  * WARNING: The C register and register group struct declarations are provided for
2494  * convenience and illustrative purposes. They should, however, be used with
2495  * caution as the C language standard provides no guarantees about the alignment or
2496  * atomicity of device memory accesses. The recommended practice for coding device
2497  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2498  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2499  * alt_write_dword() functions for 64 bit registers.
2500  *
2501  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE.
2502  */
2503 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_s
2504 {
2505  volatile uint32_t FILTERS_1_SECURITYBASE : 2; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE */
2506  uint32_t : 30; /* *UNDEFINED* */
2507 };
2508 
2509 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE. */
2510 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_t;
2511 #endif /* __ASSEMBLY__ */
2512 
2513 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE register. */
2514 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_RESET 0x00000000
2515 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE register from the beginning of the component. */
2516 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_OFST 0x94
2517 
2518 /*
2519  * Register : ddr_T_main_Probe_Filters_1_SecurityMask
2520  *
2521  * Register Layout
2522  *
2523  * Bits | Access | Reset | Description
2524  * :-------|:-------|:--------|:-------------------------------------------------------------------------------------
2525  * [1:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK
2526  * [31:2] | ??? | Unknown | *UNDEFINED*
2527  *
2528  */
2529 /*
2530  * Field : FILTERS_1_SECURITYMASK
2531  *
2532  * Register SecurityMask is contains the security mask used to filter packets. A
2533  * packet is a candidate when: packet.Security & SecurityMask = SecurityBase &
2534  * SecurityMasks.
2535  *
2536  * Field Access Macros:
2537  *
2538  */
2539 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK register field. */
2540 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_LSB 0
2541 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK register field. */
2542 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_MSB 1
2543 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK register field. */
2544 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_WIDTH 2
2545 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK register field value. */
2546 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_SET_MSK 0x00000003
2547 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK register field value. */
2548 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_CLR_MSK 0xfffffffc
2549 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK register field. */
2550 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_RESET 0x0
2551 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK field value from a register. */
2552 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_GET(value) (((value) & 0x00000003) >> 0)
2553 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK register field value suitable for setting the register. */
2554 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_SET(value) (((value) << 0) & 0x00000003)
2555 
2556 #ifndef __ASSEMBLY__
2557 /*
2558  * WARNING: The C register and register group struct declarations are provided for
2559  * convenience and illustrative purposes. They should, however, be used with
2560  * caution as the C language standard provides no guarantees about the alignment or
2561  * atomicity of device memory accesses. The recommended practice for coding device
2562  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2563  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2564  * alt_write_dword() functions for 64 bit registers.
2565  *
2566  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK.
2567  */
2568 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_s
2569 {
2570  volatile uint32_t FILTERS_1_SECURITYMASK : 2; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK */
2571  uint32_t : 30; /* *UNDEFINED* */
2572 };
2573 
2574 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK. */
2575 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_t;
2576 #endif /* __ASSEMBLY__ */
2577 
2578 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK register. */
2579 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_RESET 0x00000000
2580 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK register from the beginning of the component. */
2581 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_OFST 0x98
2582 
2583 /*
2584  * Register : ddr_T_main_Probe_Filters_1_Opcode
2585  *
2586  * Packet Probe register Opcode is a 4-bit register that selects candidate packets
2587  * based on packet opcodes (0 disables the filter):
2588  *
2589  * Register Layout
2590  *
2591  * Bits | Access | Reset | Description
2592  * :-------|:-------|:--------|:---------------------------------------------------------------
2593  * [0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN
2594  * [1] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN
2595  * [2] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN
2596  * [3] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN
2597  * [31:4] | ??? | Unknown | *UNDEFINED*
2598  *
2599  */
2600 /*
2601  * Field : RDEN
2602  *
2603  * Selects RD packets.
2604  *
2605  * Field Access Macros:
2606  *
2607  */
2608 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN register field. */
2609 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_LSB 0
2610 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN register field. */
2611 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_MSB 0
2612 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN register field. */
2613 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_WIDTH 1
2614 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN register field value. */
2615 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_SET_MSK 0x00000001
2616 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN register field value. */
2617 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_CLR_MSK 0xfffffffe
2618 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN register field. */
2619 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_RESET 0x0
2620 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN field value from a register. */
2621 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
2622 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN register field value suitable for setting the register. */
2623 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
2624 
2625 /*
2626  * Field : WREN
2627  *
2628  * Selects WR packets.
2629  *
2630  * Field Access Macros:
2631  *
2632  */
2633 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN register field. */
2634 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN_LSB 1
2635 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN register field. */
2636 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN_MSB 1
2637 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN register field. */
2638 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN_WIDTH 1
2639 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN register field value. */
2640 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN_SET_MSK 0x00000002
2641 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN register field value. */
2642 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN_CLR_MSK 0xfffffffd
2643 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN register field. */
2644 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN_RESET 0x0
2645 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN field value from a register. */
2646 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
2647 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN register field value suitable for setting the register. */
2648 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
2649 
2650 /*
2651  * Field : LOCKEN
2652  *
2653  * Selects RDX-WR, RDL, WRC and Linked sequence.
2654  *
2655  * Field Access Macros:
2656  *
2657  */
2658 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN register field. */
2659 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_LSB 2
2660 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN register field. */
2661 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_MSB 2
2662 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN register field. */
2663 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_WIDTH 1
2664 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN register field value. */
2665 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_SET_MSK 0x00000004
2666 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN register field value. */
2667 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
2668 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN register field. */
2669 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_RESET 0x0
2670 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN field value from a register. */
2671 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
2672 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN register field value suitable for setting the register. */
2673 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
2674 
2675 /*
2676  * Field : URGEN
2677  *
2678  * Selects URG packets (urgency).
2679  *
2680  * Field Access Macros:
2681  *
2682  */
2683 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN register field. */
2684 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_LSB 3
2685 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN register field. */
2686 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_MSB 3
2687 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN register field. */
2688 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_WIDTH 1
2689 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN register field value. */
2690 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_SET_MSK 0x00000008
2691 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN register field value. */
2692 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_CLR_MSK 0xfffffff7
2693 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN register field. */
2694 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_RESET 0x0
2695 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN field value from a register. */
2696 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
2697 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN register field value suitable for setting the register. */
2698 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
2699 
2700 #ifndef __ASSEMBLY__
2701 /*
2702  * WARNING: The C register and register group struct declarations are provided for
2703  * convenience and illustrative purposes. They should, however, be used with
2704  * caution as the C language standard provides no guarantees about the alignment or
2705  * atomicity of device memory accesses. The recommended practice for coding device
2706  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2707  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2708  * alt_write_dword() functions for 64 bit registers.
2709  *
2710  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE.
2711  */
2712 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_s
2713 {
2714  volatile uint32_t RDEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN */
2715  volatile uint32_t WREN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN */
2716  volatile uint32_t LOCKEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN */
2717  volatile uint32_t URGEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN */
2718  uint32_t : 28; /* *UNDEFINED* */
2719 };
2720 
2721 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE. */
2722 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_t;
2723 #endif /* __ASSEMBLY__ */
2724 
2725 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE register. */
2726 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RESET 0x00000000
2727 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE register from the beginning of the component. */
2728 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_OFST 0x9c
2729 
2730 /*
2731  * Register : ddr_T_main_Probe_Filters_1_Status
2732  *
2733  * Register Status is 2-bit register that selects candidate packets based on packet
2734  * status.
2735  *
2736  * Register Layout
2737  *
2738  * Bits | Access | Reset | Description
2739  * :-------|:-------|:--------|:--------------------------------------------------------------
2740  * [0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN
2741  * [1] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN
2742  * [31:2] | ??? | Unknown | *UNDEFINED*
2743  *
2744  */
2745 /*
2746  * Field : REQEN
2747  *
2748  * Selects REQ status packets.
2749  *
2750  * Field Access Macros:
2751  *
2752  */
2753 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN register field. */
2754 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN_LSB 0
2755 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN register field. */
2756 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN_MSB 0
2757 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN register field. */
2758 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN_WIDTH 1
2759 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN register field value. */
2760 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN_SET_MSK 0x00000001
2761 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN register field value. */
2762 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN_CLR_MSK 0xfffffffe
2763 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN register field. */
2764 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN_RESET 0x0
2765 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN field value from a register. */
2766 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN_GET(value) (((value) & 0x00000001) >> 0)
2767 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN register field value suitable for setting the register. */
2768 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN_SET(value) (((value) << 0) & 0x00000001)
2769 
2770 /*
2771  * Field : RSPEN
2772  *
2773  * Selects RSP and FAIL-CONT status packets.
2774  *
2775  * Field Access Macros:
2776  *
2777  */
2778 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN register field. */
2779 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_LSB 1
2780 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN register field. */
2781 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_MSB 1
2782 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN register field. */
2783 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_WIDTH 1
2784 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN register field value. */
2785 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_SET_MSK 0x00000002
2786 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN register field value. */
2787 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_CLR_MSK 0xfffffffd
2788 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN register field. */
2789 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_RESET 0x0
2790 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN field value from a register. */
2791 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
2792 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN register field value suitable for setting the register. */
2793 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_SET(value) (((value) << 1) & 0x00000002)
2794 
2795 #ifndef __ASSEMBLY__
2796 /*
2797  * WARNING: The C register and register group struct declarations are provided for
2798  * convenience and illustrative purposes. They should, however, be used with
2799  * caution as the C language standard provides no guarantees about the alignment or
2800  * atomicity of device memory accesses. The recommended practice for coding device
2801  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2802  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2803  * alt_write_dword() functions for 64 bit registers.
2804  *
2805  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS.
2806  */
2807 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_s
2808 {
2809  volatile uint32_t REQEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN */
2810  volatile uint32_t RSPEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN */
2811  uint32_t : 30; /* *UNDEFINED* */
2812 };
2813 
2814 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS. */
2815 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_t;
2816 #endif /* __ASSEMBLY__ */
2817 
2818 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS register. */
2819 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RESET 0x00000000
2820 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS register from the beginning of the component. */
2821 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_OFST 0xa0
2822 
2823 /*
2824  * Register : ddr_T_main_Probe_Filters_1_Length
2825  *
2826  * Register Layout
2827  *
2828  * Bits | Access | Reset | Description
2829  * :-------|:-------|:--------|:-------------------------------------------------------------------------
2830  * [3:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH
2831  * [31:4] | ??? | Unknown | *UNDEFINED*
2832  *
2833  */
2834 /*
2835  * Field : FILTERS_1_LENGTH
2836  *
2837  * Register Length is 4-bit register that selects candidate packets if their number
2838  * of bytes is less than or equal to 2**Length.
2839  *
2840  * Field Access Macros:
2841  *
2842  */
2843 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH register field. */
2844 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_LSB 0
2845 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH register field. */
2846 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_MSB 3
2847 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH register field. */
2848 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_WIDTH 4
2849 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH register field value. */
2850 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_SET_MSK 0x0000000f
2851 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH register field value. */
2852 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_CLR_MSK 0xfffffff0
2853 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH register field. */
2854 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_RESET 0x0
2855 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH field value from a register. */
2856 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_GET(value) (((value) & 0x0000000f) >> 0)
2857 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH register field value suitable for setting the register. */
2858 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_SET(value) (((value) << 0) & 0x0000000f)
2859 
2860 #ifndef __ASSEMBLY__
2861 /*
2862  * WARNING: The C register and register group struct declarations are provided for
2863  * convenience and illustrative purposes. They should, however, be used with
2864  * caution as the C language standard provides no guarantees about the alignment or
2865  * atomicity of device memory accesses. The recommended practice for coding device
2866  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2867  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2868  * alt_write_dword() functions for 64 bit registers.
2869  *
2870  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH.
2871  */
2872 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_s
2873 {
2874  volatile uint32_t FILTERS_1_LENGTH : 4; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH */
2875  uint32_t : 28; /* *UNDEFINED* */
2876 };
2877 
2878 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH. */
2879 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_t;
2880 #endif /* __ASSEMBLY__ */
2881 
2882 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH register. */
2883 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_RESET 0x00000000
2884 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH register from the beginning of the component. */
2885 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_OFST 0xa4
2886 
2887 /*
2888  * Register : ddr_T_main_Probe_Filters_1_Urgency
2889  *
2890  * Register Layout
2891  *
2892  * Bits | Access | Reset | Description
2893  * :-------|:-------|:--------|:---------------------------------------------------------------------------
2894  * [1:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY
2895  * [31:2] | ??? | Unknown | *UNDEFINED*
2896  *
2897  */
2898 /*
2899  * Field : FILTERS_1_URGENCY
2900  *
2901  * Register Urgency contains the minimum urgency level used to filter packets. A
2902  * packet is a candidate when its socket urgency is greater than or equal to the
2903  * urgency specified in the register.
2904  *
2905  * Field Access Macros:
2906  *
2907  */
2908 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY register field. */
2909 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_LSB 0
2910 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY register field. */
2911 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_MSB 1
2912 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY register field. */
2913 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_WIDTH 2
2914 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY register field value. */
2915 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_SET_MSK 0x00000003
2916 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY register field value. */
2917 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_CLR_MSK 0xfffffffc
2918 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY register field. */
2919 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_RESET 0x0
2920 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY field value from a register. */
2921 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
2922 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY register field value suitable for setting the register. */
2923 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_SET(value) (((value) << 0) & 0x00000003)
2924 
2925 #ifndef __ASSEMBLY__
2926 /*
2927  * WARNING: The C register and register group struct declarations are provided for
2928  * convenience and illustrative purposes. They should, however, be used with
2929  * caution as the C language standard provides no guarantees about the alignment or
2930  * atomicity of device memory accesses. The recommended practice for coding device
2931  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2932  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2933  * alt_write_dword() functions for 64 bit registers.
2934  *
2935  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY.
2936  */
2937 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_s
2938 {
2939  volatile uint32_t FILTERS_1_URGENCY : 2; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY */
2940  uint32_t : 30; /* *UNDEFINED* */
2941 };
2942 
2943 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY. */
2944 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_t;
2945 #endif /* __ASSEMBLY__ */
2946 
2947 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY register. */
2948 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_RESET 0x00000000
2949 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY register from the beginning of the component. */
2950 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_OFST 0xa8
2951 
2952 /*
2953  * Register : ddr_T_main_Probe_Filters_2_RouteIdBase
2954  *
2955  * Register Layout
2956  *
2957  * Bits | Access | Reset | Description
2958  * :--------|:-------|:--------|:-----------------------------------------------------------------------------------
2959  * [13:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE
2960  * [31:14] | ??? | Unknown | *UNDEFINED*
2961  *
2962  */
2963 /*
2964  * Field : FILTERS_2_ROUTEIDBASE
2965  *
2966  * Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to
2967  * filter packets.
2968  *
2969  * Field Access Macros:
2970  *
2971  */
2972 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE register field. */
2973 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE_LSB 0
2974 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE register field. */
2975 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE_MSB 13
2976 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE register field. */
2977 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE_WIDTH 14
2978 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE register field value. */
2979 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE_SET_MSK 0x00003fff
2980 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE register field value. */
2981 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE_CLR_MSK 0xffffc000
2982 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE register field. */
2983 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE_RESET 0x0
2984 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE field value from a register. */
2985 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE_GET(value) (((value) & 0x00003fff) >> 0)
2986 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE register field value suitable for setting the register. */
2987 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE_SET(value) (((value) << 0) & 0x00003fff)
2988 
2989 #ifndef __ASSEMBLY__
2990 /*
2991  * WARNING: The C register and register group struct declarations are provided for
2992  * convenience and illustrative purposes. They should, however, be used with
2993  * caution as the C language standard provides no guarantees about the alignment or
2994  * atomicity of device memory accesses. The recommended practice for coding device
2995  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2996  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2997  * alt_write_dword() functions for 64 bit registers.
2998  *
2999  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE.
3000  */
3001 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_s
3002 {
3003  volatile uint32_t FILTERS_2_ROUTEIDBASE : 14; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE */
3004  uint32_t : 18; /* *UNDEFINED* */
3005 };
3006 
3007 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE. */
3008 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_t;
3009 #endif /* __ASSEMBLY__ */
3010 
3011 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE register. */
3012 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_RESET 0x00000000
3013 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE register from the beginning of the component. */
3014 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_OFST 0xbc
3015 
3016 /*
3017  * Register : ddr_T_main_Probe_Filters_2_RouteIdMask
3018  *
3019  * Register Layout
3020  *
3021  * Bits | Access | Reset | Description
3022  * :--------|:-------|:--------|:-----------------------------------------------------------------------------------
3023  * [13:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK
3024  * [31:14] | ??? | Unknown | *UNDEFINED*
3025  *
3026  */
3027 /*
3028  * Field : FILTERS_2_ROUTEIDMASK
3029  *
3030  * Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter
3031  * packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &
3032  * RouteIdMask = RouteIdBase & RouteIdMask.
3033  *
3034  * Field Access Macros:
3035  *
3036  */
3037 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK register field. */
3038 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK_LSB 0
3039 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK register field. */
3040 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK_MSB 13
3041 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK register field. */
3042 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK_WIDTH 14
3043 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK register field value. */
3044 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK_SET_MSK 0x00003fff
3045 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK register field value. */
3046 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK_CLR_MSK 0xffffc000
3047 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK register field. */
3048 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK_RESET 0x0
3049 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK field value from a register. */
3050 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK_GET(value) (((value) & 0x00003fff) >> 0)
3051 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK register field value suitable for setting the register. */
3052 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK_SET(value) (((value) << 0) & 0x00003fff)
3053 
3054 #ifndef __ASSEMBLY__
3055 /*
3056  * WARNING: The C register and register group struct declarations are provided for
3057  * convenience and illustrative purposes. They should, however, be used with
3058  * caution as the C language standard provides no guarantees about the alignment or
3059  * atomicity of device memory accesses. The recommended practice for coding device
3060  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3061  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3062  * alt_write_dword() functions for 64 bit registers.
3063  *
3064  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK.
3065  */
3066 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_s
3067 {
3068  volatile uint32_t FILTERS_2_ROUTEIDMASK : 14; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK */
3069  uint32_t : 18; /* *UNDEFINED* */
3070 };
3071 
3072 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK. */
3073 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_t;
3074 #endif /* __ASSEMBLY__ */
3075 
3076 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK register. */
3077 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_RESET 0x00000000
3078 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK register from the beginning of the component. */
3079 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_OFST 0xc0
3080 
3081 /*
3082  * Register : ddr_T_main_Probe_Filters_2_AddrBase_Low
3083  *
3084  * Register Layout
3085  *
3086  * Bits | Access | Reset | Description
3087  * :-------|:-------|:------|:-------------------------------------------------------------------------------------
3088  * [31:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW
3089  *
3090  */
3091 /*
3092  * Field : FILTERS_2_ADDRBASE_LOW
3093  *
3094  * Address LSB register.
3095  *
3096  * Field Access Macros:
3097  *
3098  */
3099 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW register field. */
3100 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW_LSB 0
3101 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW register field. */
3102 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW_MSB 31
3103 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW register field. */
3104 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW_WIDTH 32
3105 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW register field value. */
3106 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW_SET_MSK 0xffffffff
3107 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW register field value. */
3108 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW_CLR_MSK 0x00000000
3109 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW register field. */
3110 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW_RESET 0x0
3111 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW field value from a register. */
3112 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
3113 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW register field value suitable for setting the register. */
3114 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
3115 
3116 #ifndef __ASSEMBLY__
3117 /*
3118  * WARNING: The C register and register group struct declarations are provided for
3119  * convenience and illustrative purposes. They should, however, be used with
3120  * caution as the C language standard provides no guarantees about the alignment or
3121  * atomicity of device memory accesses. The recommended practice for coding device
3122  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3123  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3124  * alt_write_dword() functions for 64 bit registers.
3125  *
3126  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW.
3127  */
3128 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_s
3129 {
3130  volatile uint32_t FILTERS_2_ADDRBASE_LOW : 32; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW */
3131 };
3132 
3133 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW. */
3134 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_t;
3135 #endif /* __ASSEMBLY__ */
3136 
3137 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW register. */
3138 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_RESET 0x00000000
3139 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW register from the beginning of the component. */
3140 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_OFST 0xc4
3141 
3142 /*
3143  * Register : ddr_T_main_Probe_Filters_2_AddrBase_High
3144  *
3145  * Register Layout
3146  *
3147  * Bits | Access | Reset | Description
3148  * :-------|:-------|:--------|:---------------------------------------------------------------------------------------
3149  * [4:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH
3150  * [31:5] | ??? | Unknown | *UNDEFINED*
3151  *
3152  */
3153 /*
3154  * Field : FILTERS_2_ADDRBASE_HIGH
3155  *
3156  * Address MSB register.
3157  *
3158  * Field Access Macros:
3159  *
3160  */
3161 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH register field. */
3162 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH_LSB 0
3163 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH register field. */
3164 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH_MSB 4
3165 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH register field. */
3166 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH_WIDTH 5
3167 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH register field value. */
3168 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH_SET_MSK 0x0000001f
3169 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH register field value. */
3170 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH_CLR_MSK 0xffffffe0
3171 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH register field. */
3172 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH_RESET 0x0
3173 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH field value from a register. */
3174 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH_GET(value) (((value) & 0x0000001f) >> 0)
3175 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH register field value suitable for setting the register. */
3176 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH_SET(value) (((value) << 0) & 0x0000001f)
3177 
3178 #ifndef __ASSEMBLY__
3179 /*
3180  * WARNING: The C register and register group struct declarations are provided for
3181  * convenience and illustrative purposes. They should, however, be used with
3182  * caution as the C language standard provides no guarantees about the alignment or
3183  * atomicity of device memory accesses. The recommended practice for coding device
3184  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3185  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3186  * alt_write_dword() functions for 64 bit registers.
3187  *
3188  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH.
3189  */
3190 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_s
3191 {
3192  volatile uint32_t FILTERS_2_ADDRBASE_HIGH : 5; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH */
3193  uint32_t : 27; /* *UNDEFINED* */
3194 };
3195 
3196 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH. */
3197 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_t;
3198 #endif /* __ASSEMBLY__ */
3199 
3200 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH register. */
3201 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_RESET 0x00000000
3202 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH register from the beginning of the component. */
3203 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_OFST 0xc8
3204 
3205 /*
3206  * Register : ddr_T_main_Probe_Filters_2_WindowSize
3207  *
3208  * Register Layout
3209  *
3210  * Bits | Access | Reset | Description
3211  * :-------|:-------|:--------|:---------------------------------------------------------------------------------
3212  * [5:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE
3213  * [31:6] | ??? | Unknown | *UNDEFINED*
3214  *
3215  */
3216 /*
3217  * Field : FILTERS_2_WINDOWSIZE
3218  *
3219  * Register WindowSize contains the encoded address mask used to filter packets.
3220  * The effective Mask value is equal to ~(2max(WindowSize, packet.Len) - 1). A
3221  * packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows
3222  * filteringof packets having an intersection with the AddrBase/WindowSize burst
3223  * aligned region, even if the region is smaller than the packet.
3224  *
3225  * Field Access Macros:
3226  *
3227  */
3228 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE register field. */
3229 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE_LSB 0
3230 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE register field. */
3231 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE_MSB 5
3232 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE register field. */
3233 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE_WIDTH 6
3234 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE register field value. */
3235 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE_SET_MSK 0x0000003f
3236 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE register field value. */
3237 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE_CLR_MSK 0xffffffc0
3238 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE register field. */
3239 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE_RESET 0x0
3240 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE field value from a register. */
3241 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
3242 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE register field value suitable for setting the register. */
3243 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
3244 
3245 #ifndef __ASSEMBLY__
3246 /*
3247  * WARNING: The C register and register group struct declarations are provided for
3248  * convenience and illustrative purposes. They should, however, be used with
3249  * caution as the C language standard provides no guarantees about the alignment or
3250  * atomicity of device memory accesses. The recommended practice for coding device
3251  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3252  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3253  * alt_write_dword() functions for 64 bit registers.
3254  *
3255  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE.
3256  */
3257 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_s
3258 {
3259  volatile uint32_t FILTERS_2_WINDOWSIZE : 6; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE */
3260  uint32_t : 26; /* *UNDEFINED* */
3261 };
3262 
3263 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE. */
3264 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_t;
3265 #endif /* __ASSEMBLY__ */
3266 
3267 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE register. */
3268 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_RESET 0x00000000
3269 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE register from the beginning of the component. */
3270 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_OFST 0xcc
3271 
3272 /*
3273  * Register : ddr_T_main_Probe_Filters_2_SecurityBase
3274  *
3275  * Register Layout
3276  *
3277  * Bits | Access | Reset | Description
3278  * :-------|:-------|:--------|:-------------------------------------------------------------------------------------
3279  * [1:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE
3280  * [31:2] | ??? | Unknown | *UNDEFINED*
3281  *
3282  */
3283 /*
3284  * Field : FILTERS_2_SECURITYBASE
3285  *
3286  * Register SecurityBase contains the security base used to filter packets.
3287  *
3288  * Field Access Macros:
3289  *
3290  */
3291 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE register field. */
3292 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE_LSB 0
3293 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE register field. */
3294 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE_MSB 1
3295 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE register field. */
3296 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE_WIDTH 2
3297 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE register field value. */
3298 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE_SET_MSK 0x00000003
3299 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE register field value. */
3300 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE_CLR_MSK 0xfffffffc
3301 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE register field. */
3302 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE_RESET 0x0
3303 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE field value from a register. */
3304 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE_GET(value) (((value) & 0x00000003) >> 0)
3305 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE register field value suitable for setting the register. */
3306 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE_SET(value) (((value) << 0) & 0x00000003)
3307 
3308 #ifndef __ASSEMBLY__
3309 /*
3310  * WARNING: The C register and register group struct declarations are provided for
3311  * convenience and illustrative purposes. They should, however, be used with
3312  * caution as the C language standard provides no guarantees about the alignment or
3313  * atomicity of device memory accesses. The recommended practice for coding device
3314  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3315  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3316  * alt_write_dword() functions for 64 bit registers.
3317  *
3318  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE.
3319  */
3320 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_s
3321 {
3322  volatile uint32_t FILTERS_2_SECURITYBASE : 2; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE */
3323  uint32_t : 30; /* *UNDEFINED* */
3324 };
3325 
3326 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE. */
3327 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_t;
3328 #endif /* __ASSEMBLY__ */
3329 
3330 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE register. */
3331 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_RESET 0x00000000
3332 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE register from the beginning of the component. */
3333 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_OFST 0xd0
3334 
3335 /*
3336  * Register : ddr_T_main_Probe_Filters_2_SecurityMask
3337  *
3338  * Register Layout
3339  *
3340  * Bits | Access | Reset | Description
3341  * :-------|:-------|:--------|:-------------------------------------------------------------------------------------
3342  * [1:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK
3343  * [31:2] | ??? | Unknown | *UNDEFINED*
3344  *
3345  */
3346 /*
3347  * Field : FILTERS_2_SECURITYMASK
3348  *
3349  * Register SecurityMask is contains the security mask used to filter packets. A
3350  * packet is a candidate when: packet.Security & SecurityMask = SecurityBase &
3351  * SecurityMasks.
3352  *
3353  * Field Access Macros:
3354  *
3355  */
3356 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK register field. */
3357 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK_LSB 0
3358 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK register field. */
3359 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK_MSB 1
3360 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK register field. */
3361 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK_WIDTH 2
3362 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK register field value. */
3363 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK_SET_MSK 0x00000003
3364 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK register field value. */
3365 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK_CLR_MSK 0xfffffffc
3366 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK register field. */
3367 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK_RESET 0x0
3368 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK field value from a register. */
3369 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK_GET(value) (((value) & 0x00000003) >> 0)
3370 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK register field value suitable for setting the register. */
3371 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK_SET(value) (((value) << 0) & 0x00000003)
3372 
3373 #ifndef __ASSEMBLY__
3374 /*
3375  * WARNING: The C register and register group struct declarations are provided for
3376  * convenience and illustrative purposes. They should, however, be used with
3377  * caution as the C language standard provides no guarantees about the alignment or
3378  * atomicity of device memory accesses. The recommended practice for coding device
3379  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3380  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3381  * alt_write_dword() functions for 64 bit registers.
3382  *
3383  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK.
3384  */
3385 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_s
3386 {
3387  volatile uint32_t FILTERS_2_SECURITYMASK : 2; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK */
3388  uint32_t : 30; /* *UNDEFINED* */
3389 };
3390 
3391 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK. */
3392 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_t;
3393 #endif /* __ASSEMBLY__ */
3394 
3395 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK register. */
3396 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_RESET 0x00000000
3397 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK register from the beginning of the component. */
3398 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_OFST 0xd4
3399 
3400 /*
3401  * Register : ddr_T_main_Probe_Filters_2_Opcode
3402  *
3403  * Packet Probe register Opcode is a 4-bit register that selects candidate packets
3404  * based on packet opcodes (0 disables the filter):
3405  *
3406  * Register Layout
3407  *
3408  * Bits | Access | Reset | Description
3409  * :-------|:-------|:--------|:---------------------------------------------------------------
3410  * [0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN
3411  * [1] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN
3412  * [2] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN
3413  * [3] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN
3414  * [31:4] | ??? | Unknown | *UNDEFINED*
3415  *
3416  */
3417 /*
3418  * Field : RDEN
3419  *
3420  * Selects RD packets.
3421  *
3422  * Field Access Macros:
3423  *
3424  */
3425 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN register field. */
3426 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN_LSB 0
3427 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN register field. */
3428 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN_MSB 0
3429 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN register field. */
3430 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN_WIDTH 1
3431 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN register field value. */
3432 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN_SET_MSK 0x00000001
3433 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN register field value. */
3434 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN_CLR_MSK 0xfffffffe
3435 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN register field. */
3436 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN_RESET 0x0
3437 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN field value from a register. */
3438 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
3439 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN register field value suitable for setting the register. */
3440 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
3441 
3442 /*
3443  * Field : WREN
3444  *
3445  * Selects WR packets.
3446  *
3447  * Field Access Macros:
3448  *
3449  */
3450 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN register field. */
3451 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN_LSB 1
3452 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN register field. */
3453 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN_MSB 1
3454 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN register field. */
3455 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN_WIDTH 1
3456 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN register field value. */
3457 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN_SET_MSK 0x00000002
3458 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN register field value. */
3459 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN_CLR_MSK 0xfffffffd
3460 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN register field. */
3461 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN_RESET 0x0
3462 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN field value from a register. */
3463 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
3464 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN register field value suitable for setting the register. */
3465 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
3466 
3467 /*
3468  * Field : LOCKEN
3469  *
3470  * Selects RDX-WR, RDL, WRC and Linked sequence.
3471  *
3472  * Field Access Macros:
3473  *
3474  */
3475 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN register field. */
3476 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN_LSB 2
3477 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN register field. */
3478 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN_MSB 2
3479 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN register field. */
3480 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN_WIDTH 1
3481 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN register field value. */
3482 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN_SET_MSK 0x00000004
3483 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN register field value. */
3484 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
3485 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN register field. */
3486 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN_RESET 0x0
3487 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN field value from a register. */
3488 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
3489 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN register field value suitable for setting the register. */
3490 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
3491 
3492 /*
3493  * Field : URGEN
3494  *
3495  * Selects URG packets (urgency).
3496  *
3497  * Field Access Macros:
3498  *
3499  */
3500 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN register field. */
3501 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN_LSB 3
3502 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN register field. */
3503 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN_MSB 3
3504 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN register field. */
3505 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN_WIDTH 1
3506 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN register field value. */
3507 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN_SET_MSK 0x00000008
3508 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN register field value. */
3509 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN_CLR_MSK 0xfffffff7
3510 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN register field. */
3511 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN_RESET 0x0
3512 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN field value from a register. */
3513 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
3514 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN register field value suitable for setting the register. */
3515 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
3516 
3517 #ifndef __ASSEMBLY__
3518 /*
3519  * WARNING: The C register and register group struct declarations are provided for
3520  * convenience and illustrative purposes. They should, however, be used with
3521  * caution as the C language standard provides no guarantees about the alignment or
3522  * atomicity of device memory accesses. The recommended practice for coding device
3523  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3524  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3525  * alt_write_dword() functions for 64 bit registers.
3526  *
3527  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE.
3528  */
3529 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_s
3530 {
3531  volatile uint32_t RDEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN */
3532  volatile uint32_t WREN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN */
3533  volatile uint32_t LOCKEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN */
3534  volatile uint32_t URGEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN */
3535  uint32_t : 28; /* *UNDEFINED* */
3536 };
3537 
3538 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE. */
3539 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_t;
3540 #endif /* __ASSEMBLY__ */
3541 
3542 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE register. */
3543 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RESET 0x00000000
3544 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE register from the beginning of the component. */
3545 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_OFST 0xd8
3546 
3547 /*
3548  * Register : ddr_T_main_Probe_Filters_2_Status
3549  *
3550  * Register Status is 2-bit register that selects candidate packets based on packet
3551  * status.
3552  *
3553  * Register Layout
3554  *
3555  * Bits | Access | Reset | Description
3556  * :-------|:-------|:--------|:--------------------------------------------------------------
3557  * [0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN
3558  * [1] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN
3559  * [31:2] | ??? | Unknown | *UNDEFINED*
3560  *
3561  */
3562 /*
3563  * Field : REQEN
3564  *
3565  * Selects REQ status packets.
3566  *
3567  * Field Access Macros:
3568  *
3569  */
3570 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN register field. */
3571 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN_LSB 0
3572 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN register field. */
3573 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN_MSB 0
3574 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN register field. */
3575 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN_WIDTH 1
3576 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN register field value. */
3577 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN_SET_MSK 0x00000001
3578 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN register field value. */
3579 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN_CLR_MSK 0xfffffffe
3580 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN register field. */
3581 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN_RESET 0x0
3582 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN field value from a register. */
3583 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN_GET(value) (((value) & 0x00000001) >> 0)
3584 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN register field value suitable for setting the register. */
3585 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN_SET(value) (((value) << 0) & 0x00000001)
3586 
3587 /*
3588  * Field : RSPEN
3589  *
3590  * Selects RSP and FAIL-CONT status packets.
3591  *
3592  * Field Access Macros:
3593  *
3594  */
3595 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN register field. */
3596 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN_LSB 1
3597 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN register field. */
3598 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN_MSB 1
3599 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN register field. */
3600 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN_WIDTH 1
3601 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN register field value. */
3602 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN_SET_MSK 0x00000002
3603 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN register field value. */
3604 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN_CLR_MSK 0xfffffffd
3605 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN register field. */
3606 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN_RESET 0x0
3607 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN field value from a register. */
3608 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
3609 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN register field value suitable for setting the register. */
3610 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN_SET(value) (((value) << 1) & 0x00000002)
3611 
3612 #ifndef __ASSEMBLY__
3613 /*
3614  * WARNING: The C register and register group struct declarations are provided for
3615  * convenience and illustrative purposes. They should, however, be used with
3616  * caution as the C language standard provides no guarantees about the alignment or
3617  * atomicity of device memory accesses. The recommended practice for coding device
3618  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3619  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3620  * alt_write_dword() functions for 64 bit registers.
3621  *
3622  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS.
3623  */
3624 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_s
3625 {
3626  volatile uint32_t REQEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN */
3627  volatile uint32_t RSPEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN */
3628  uint32_t : 30; /* *UNDEFINED* */
3629 };
3630 
3631 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS. */
3632 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_t;
3633 #endif /* __ASSEMBLY__ */
3634 
3635 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS register. */
3636 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RESET 0x00000000
3637 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS register from the beginning of the component. */
3638 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_OFST 0xdc
3639 
3640 /*
3641  * Register : ddr_T_main_Probe_Filters_2_Length
3642  *
3643  * Register Layout
3644  *
3645  * Bits | Access | Reset | Description
3646  * :-------|:-------|:--------|:-------------------------------------------------------------------------
3647  * [3:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH
3648  * [31:4] | ??? | Unknown | *UNDEFINED*
3649  *
3650  */
3651 /*
3652  * Field : FILTERS_2_LENGTH
3653  *
3654  * Register Length is 4-bit register that selects candidate packets if their number
3655  * of bytes is less than or equal to 2**Length.
3656  *
3657  * Field Access Macros:
3658  *
3659  */
3660 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH register field. */
3661 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH_LSB 0
3662 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH register field. */
3663 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH_MSB 3
3664 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH register field. */
3665 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH_WIDTH 4
3666 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH register field value. */
3667 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH_SET_MSK 0x0000000f
3668 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH register field value. */
3669 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH_CLR_MSK 0xfffffff0
3670 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH register field. */
3671 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH_RESET 0x0
3672 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH field value from a register. */
3673 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH_GET(value) (((value) & 0x0000000f) >> 0)
3674 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH register field value suitable for setting the register. */
3675 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH_SET(value) (((value) << 0) & 0x0000000f)
3676 
3677 #ifndef __ASSEMBLY__
3678 /*
3679  * WARNING: The C register and register group struct declarations are provided for
3680  * convenience and illustrative purposes. They should, however, be used with
3681  * caution as the C language standard provides no guarantees about the alignment or
3682  * atomicity of device memory accesses. The recommended practice for coding device
3683  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3684  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3685  * alt_write_dword() functions for 64 bit registers.
3686  *
3687  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH.
3688  */
3689 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_s
3690 {
3691  volatile uint32_t FILTERS_2_LENGTH : 4; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH */
3692  uint32_t : 28; /* *UNDEFINED* */
3693 };
3694 
3695 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH. */
3696 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_t;
3697 #endif /* __ASSEMBLY__ */
3698 
3699 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH register. */
3700 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_RESET 0x00000000
3701 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH register from the beginning of the component. */
3702 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_OFST 0xe0
3703 
3704 /*
3705  * Register : ddr_T_main_Probe_Filters_2_Urgency
3706  *
3707  * Register Layout
3708  *
3709  * Bits | Access | Reset | Description
3710  * :-------|:-------|:--------|:---------------------------------------------------------------------------
3711  * [1:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY
3712  * [31:2] | ??? | Unknown | *UNDEFINED*
3713  *
3714  */
3715 /*
3716  * Field : FILTERS_2_URGENCY
3717  *
3718  * Register Urgency contains the minimum urgency level used to filter packets. A
3719  * packet is a candidate when its socket urgency is greater than or equal to the
3720  * urgency specified in the register.
3721  *
3722  * Field Access Macros:
3723  *
3724  */
3725 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY register field. */
3726 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY_LSB 0
3727 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY register field. */
3728 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY_MSB 1
3729 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY register field. */
3730 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY_WIDTH 2
3731 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY register field value. */
3732 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY_SET_MSK 0x00000003
3733 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY register field value. */
3734 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY_CLR_MSK 0xfffffffc
3735 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY register field. */
3736 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY_RESET 0x0
3737 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY field value from a register. */
3738 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
3739 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY register field value suitable for setting the register. */
3740 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY_SET(value) (((value) << 0) & 0x00000003)
3741 
3742 #ifndef __ASSEMBLY__
3743 /*
3744  * WARNING: The C register and register group struct declarations are provided for
3745  * convenience and illustrative purposes. They should, however, be used with
3746  * caution as the C language standard provides no guarantees about the alignment or
3747  * atomicity of device memory accesses. The recommended practice for coding device
3748  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3749  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3750  * alt_write_dword() functions for 64 bit registers.
3751  *
3752  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY.
3753  */
3754 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_s
3755 {
3756  volatile uint32_t FILTERS_2_URGENCY : 2; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY */
3757  uint32_t : 30; /* *UNDEFINED* */
3758 };
3759 
3760 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY. */
3761 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_t;
3762 #endif /* __ASSEMBLY__ */
3763 
3764 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY register. */
3765 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_RESET 0x00000000
3766 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY register from the beginning of the component. */
3767 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_OFST 0xe4
3768 
3769 /*
3770  * Register : ddr_T_main_Probe_Filters_3_RouteIdBase
3771  *
3772  * Register Layout
3773  *
3774  * Bits | Access | Reset | Description
3775  * :--------|:-------|:--------|:-----------------------------------------------------------------------------------
3776  * [13:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE
3777  * [31:14] | ??? | Unknown | *UNDEFINED*
3778  *
3779  */
3780 /*
3781  * Field : FILTERS_3_ROUTEIDBASE
3782  *
3783  * Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to
3784  * filter packets.
3785  *
3786  * Field Access Macros:
3787  *
3788  */
3789 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE register field. */
3790 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE_LSB 0
3791 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE register field. */
3792 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE_MSB 13
3793 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE register field. */
3794 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE_WIDTH 14
3795 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE register field value. */
3796 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE_SET_MSK 0x00003fff
3797 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE register field value. */
3798 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE_CLR_MSK 0xffffc000
3799 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE register field. */
3800 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE_RESET 0x0
3801 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE field value from a register. */
3802 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE_GET(value) (((value) & 0x00003fff) >> 0)
3803 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE register field value suitable for setting the register. */
3804 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE_SET(value) (((value) << 0) & 0x00003fff)
3805 
3806 #ifndef __ASSEMBLY__
3807 /*
3808  * WARNING: The C register and register group struct declarations are provided for
3809  * convenience and illustrative purposes. They should, however, be used with
3810  * caution as the C language standard provides no guarantees about the alignment or
3811  * atomicity of device memory accesses. The recommended practice for coding device
3812  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3813  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3814  * alt_write_dword() functions for 64 bit registers.
3815  *
3816  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE.
3817  */
3818 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_s
3819 {
3820  volatile uint32_t FILTERS_3_ROUTEIDBASE : 14; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE */
3821  uint32_t : 18; /* *UNDEFINED* */
3822 };
3823 
3824 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE. */
3825 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_t;
3826 #endif /* __ASSEMBLY__ */
3827 
3828 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE register. */
3829 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_RESET 0x00000000
3830 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE register from the beginning of the component. */
3831 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_OFST 0xf8
3832 
3833 /*
3834  * Register : ddr_T_main_Probe_Filters_3_RouteIdMask
3835  *
3836  * Register Layout
3837  *
3838  * Bits | Access | Reset | Description
3839  * :--------|:-------|:--------|:-----------------------------------------------------------------------------------
3840  * [13:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK
3841  * [31:14] | ??? | Unknown | *UNDEFINED*
3842  *
3843  */
3844 /*
3845  * Field : FILTERS_3_ROUTEIDMASK
3846  *
3847  * Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter
3848  * packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &
3849  * RouteIdMask = RouteIdBase & RouteIdMask.
3850  *
3851  * Field Access Macros:
3852  *
3853  */
3854 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK register field. */
3855 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK_LSB 0
3856 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK register field. */
3857 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK_MSB 13
3858 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK register field. */
3859 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK_WIDTH 14
3860 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK register field value. */
3861 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK_SET_MSK 0x00003fff
3862 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK register field value. */
3863 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK_CLR_MSK 0xffffc000
3864 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK register field. */
3865 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK_RESET 0x0
3866 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK field value from a register. */
3867 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK_GET(value) (((value) & 0x00003fff) >> 0)
3868 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK register field value suitable for setting the register. */
3869 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK_SET(value) (((value) << 0) & 0x00003fff)
3870 
3871 #ifndef __ASSEMBLY__
3872 /*
3873  * WARNING: The C register and register group struct declarations are provided for
3874  * convenience and illustrative purposes. They should, however, be used with
3875  * caution as the C language standard provides no guarantees about the alignment or
3876  * atomicity of device memory accesses. The recommended practice for coding device
3877  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3878  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3879  * alt_write_dword() functions for 64 bit registers.
3880  *
3881  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK.
3882  */
3883 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_s
3884 {
3885  volatile uint32_t FILTERS_3_ROUTEIDMASK : 14; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK */
3886  uint32_t : 18; /* *UNDEFINED* */
3887 };
3888 
3889 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK. */
3890 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_t;
3891 #endif /* __ASSEMBLY__ */
3892 
3893 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK register. */
3894 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_RESET 0x00000000
3895 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK register from the beginning of the component. */
3896 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_OFST 0xfc
3897 
3898 /*
3899  * Register : ddr_T_main_Probe_Filters_3_AddrBase_Low
3900  *
3901  * Register Layout
3902  *
3903  * Bits | Access | Reset | Description
3904  * :-------|:-------|:------|:-------------------------------------------------------------------------------------
3905  * [31:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW
3906  *
3907  */
3908 /*
3909  * Field : FILTERS_3_ADDRBASE_LOW
3910  *
3911  * Address LSB register.
3912  *
3913  * Field Access Macros:
3914  *
3915  */
3916 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW register field. */
3917 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW_LSB 0
3918 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW register field. */
3919 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW_MSB 31
3920 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW register field. */
3921 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW_WIDTH 32
3922 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW register field value. */
3923 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW_SET_MSK 0xffffffff
3924 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW register field value. */
3925 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW_CLR_MSK 0x00000000
3926 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW register field. */
3927 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW_RESET 0x0
3928 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW field value from a register. */
3929 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
3930 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW register field value suitable for setting the register. */
3931 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
3932 
3933 #ifndef __ASSEMBLY__
3934 /*
3935  * WARNING: The C register and register group struct declarations are provided for
3936  * convenience and illustrative purposes. They should, however, be used with
3937  * caution as the C language standard provides no guarantees about the alignment or
3938  * atomicity of device memory accesses. The recommended practice for coding device
3939  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3940  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3941  * alt_write_dword() functions for 64 bit registers.
3942  *
3943  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW.
3944  */
3945 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_s
3946 {
3947  volatile uint32_t FILTERS_3_ADDRBASE_LOW : 32; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW */
3948 };
3949 
3950 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW. */
3951 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_t;
3952 #endif /* __ASSEMBLY__ */
3953 
3954 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW register. */
3955 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_RESET 0x00000000
3956 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW register from the beginning of the component. */
3957 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_OFST 0x100
3958 
3959 /*
3960  * Register : ddr_T_main_Probe_Filters_3_AddrBase_High
3961  *
3962  * Register Layout
3963  *
3964  * Bits | Access | Reset | Description
3965  * :-------|:-------|:--------|:---------------------------------------------------------------------------------------
3966  * [4:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH
3967  * [31:5] | ??? | Unknown | *UNDEFINED*
3968  *
3969  */
3970 /*
3971  * Field : FILTERS_3_ADDRBASE_HIGH
3972  *
3973  * Address MSB register.
3974  *
3975  * Field Access Macros:
3976  *
3977  */
3978 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH register field. */
3979 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH_LSB 0
3980 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH register field. */
3981 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH_MSB 4
3982 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH register field. */
3983 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH_WIDTH 5
3984 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH register field value. */
3985 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH_SET_MSK 0x0000001f
3986 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH register field value. */
3987 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH_CLR_MSK 0xffffffe0
3988 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH register field. */
3989 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH_RESET 0x0
3990 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH field value from a register. */
3991 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH_GET(value) (((value) & 0x0000001f) >> 0)
3992 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH register field value suitable for setting the register. */
3993 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH_SET(value) (((value) << 0) & 0x0000001f)
3994 
3995 #ifndef __ASSEMBLY__
3996 /*
3997  * WARNING: The C register and register group struct declarations are provided for
3998  * convenience and illustrative purposes. They should, however, be used with
3999  * caution as the C language standard provides no guarantees about the alignment or
4000  * atomicity of device memory accesses. The recommended practice for coding device
4001  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4002  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4003  * alt_write_dword() functions for 64 bit registers.
4004  *
4005  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH.
4006  */
4007 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_s
4008 {
4009  volatile uint32_t FILTERS_3_ADDRBASE_HIGH : 5; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH */
4010  uint32_t : 27; /* *UNDEFINED* */
4011 };
4012 
4013 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH. */
4014 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_t;
4015 #endif /* __ASSEMBLY__ */
4016 
4017 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH register. */
4018 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_RESET 0x00000000
4019 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH register from the beginning of the component. */
4020 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_OFST 0x104
4021 
4022 /*
4023  * Register : ddr_T_main_Probe_Filters_3_WindowSize
4024  *
4025  * Register Layout
4026  *
4027  * Bits | Access | Reset | Description
4028  * :-------|:-------|:--------|:---------------------------------------------------------------------------------
4029  * [5:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE
4030  * [31:6] | ??? | Unknown | *UNDEFINED*
4031  *
4032  */
4033 /*
4034  * Field : FILTERS_3_WINDOWSIZE
4035  *
4036  * Register WindowSize contains the encoded address mask used to filter packets.
4037  * The effective Mask value is equal to ~(2max(WindowSize, packet.Len) - 1). A
4038  * packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows
4039  * filteringof packets having an intersection with the AddrBase/WindowSize burst
4040  * aligned region, even if the region is smaller than the packet.
4041  *
4042  * Field Access Macros:
4043  *
4044  */
4045 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE register field. */
4046 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE_LSB 0
4047 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE register field. */
4048 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE_MSB 5
4049 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE register field. */
4050 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE_WIDTH 6
4051 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE register field value. */
4052 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE_SET_MSK 0x0000003f
4053 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE register field value. */
4054 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE_CLR_MSK 0xffffffc0
4055 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE register field. */
4056 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE_RESET 0x0
4057 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE field value from a register. */
4058 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
4059 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE register field value suitable for setting the register. */
4060 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
4061 
4062 #ifndef __ASSEMBLY__
4063 /*
4064  * WARNING: The C register and register group struct declarations are provided for
4065  * convenience and illustrative purposes. They should, however, be used with
4066  * caution as the C language standard provides no guarantees about the alignment or
4067  * atomicity of device memory accesses. The recommended practice for coding device
4068  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4069  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4070  * alt_write_dword() functions for 64 bit registers.
4071  *
4072  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE.
4073  */
4074 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_s
4075 {
4076  volatile uint32_t FILTERS_3_WINDOWSIZE : 6; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE */
4077  uint32_t : 26; /* *UNDEFINED* */
4078 };
4079 
4080 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE. */
4081 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_t;
4082 #endif /* __ASSEMBLY__ */
4083 
4084 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE register. */
4085 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_RESET 0x00000000
4086 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE register from the beginning of the component. */
4087 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_OFST 0x108
4088 
4089 /*
4090  * Register : ddr_T_main_Probe_Filters_3_SecurityBase
4091  *
4092  * Register Layout
4093  *
4094  * Bits | Access | Reset | Description
4095  * :-------|:-------|:--------|:-------------------------------------------------------------------------------------
4096  * [1:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE
4097  * [31:2] | ??? | Unknown | *UNDEFINED*
4098  *
4099  */
4100 /*
4101  * Field : FILTERS_3_SECURITYBASE
4102  *
4103  * Register SecurityBase contains the security base used to filter packets.
4104  *
4105  * Field Access Macros:
4106  *
4107  */
4108 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE register field. */
4109 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE_LSB 0
4110 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE register field. */
4111 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE_MSB 1
4112 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE register field. */
4113 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE_WIDTH 2
4114 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE register field value. */
4115 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE_SET_MSK 0x00000003
4116 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE register field value. */
4117 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE_CLR_MSK 0xfffffffc
4118 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE register field. */
4119 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE_RESET 0x0
4120 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE field value from a register. */
4121 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE_GET(value) (((value) & 0x00000003) >> 0)
4122 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE register field value suitable for setting the register. */
4123 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE_SET(value) (((value) << 0) & 0x00000003)
4124 
4125 #ifndef __ASSEMBLY__
4126 /*
4127  * WARNING: The C register and register group struct declarations are provided for
4128  * convenience and illustrative purposes. They should, however, be used with
4129  * caution as the C language standard provides no guarantees about the alignment or
4130  * atomicity of device memory accesses. The recommended practice for coding device
4131  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4132  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4133  * alt_write_dword() functions for 64 bit registers.
4134  *
4135  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE.
4136  */
4137 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_s
4138 {
4139  volatile uint32_t FILTERS_3_SECURITYBASE : 2; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE */
4140  uint32_t : 30; /* *UNDEFINED* */
4141 };
4142 
4143 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE. */
4144 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_t;
4145 #endif /* __ASSEMBLY__ */
4146 
4147 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE register. */
4148 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_RESET 0x00000000
4149 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE register from the beginning of the component. */
4150 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_OFST 0x10c
4151 
4152 /*
4153  * Register : ddr_T_main_Probe_Filters_3_SecurityMask
4154  *
4155  * Register Layout
4156  *
4157  * Bits | Access | Reset | Description
4158  * :-------|:-------|:--------|:-------------------------------------------------------------------------------------
4159  * [1:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK
4160  * [31:2] | ??? | Unknown | *UNDEFINED*
4161  *
4162  */
4163 /*
4164  * Field : FILTERS_3_SECURITYMASK
4165  *
4166  * Register SecurityMask is contains the security mask used to filter packets. A
4167  * packet is a candidate when: packet.Security & SecurityMask = SecurityBase &
4168  * SecurityMasks.
4169  *
4170  * Field Access Macros:
4171  *
4172  */
4173 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK register field. */
4174 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK_LSB 0
4175 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK register field. */
4176 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK_MSB 1
4177 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK register field. */
4178 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK_WIDTH 2
4179 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK register field value. */
4180 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK_SET_MSK 0x00000003
4181 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK register field value. */
4182 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK_CLR_MSK 0xfffffffc
4183 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK register field. */
4184 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK_RESET 0x0
4185 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK field value from a register. */
4186 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK_GET(value) (((value) & 0x00000003) >> 0)
4187 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK register field value suitable for setting the register. */
4188 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK_SET(value) (((value) << 0) & 0x00000003)
4189 
4190 #ifndef __ASSEMBLY__
4191 /*
4192  * WARNING: The C register and register group struct declarations are provided for
4193  * convenience and illustrative purposes. They should, however, be used with
4194  * caution as the C language standard provides no guarantees about the alignment or
4195  * atomicity of device memory accesses. The recommended practice for coding device
4196  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4197  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4198  * alt_write_dword() functions for 64 bit registers.
4199  *
4200  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK.
4201  */
4202 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_s
4203 {
4204  volatile uint32_t FILTERS_3_SECURITYMASK : 2; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK */
4205  uint32_t : 30; /* *UNDEFINED* */
4206 };
4207 
4208 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK. */
4209 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_t;
4210 #endif /* __ASSEMBLY__ */
4211 
4212 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK register. */
4213 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_RESET 0x00000000
4214 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK register from the beginning of the component. */
4215 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_OFST 0x110
4216 
4217 /*
4218  * Register : ddr_T_main_Probe_Filters_3_Opcode
4219  *
4220  * Packet Probe register Opcode is a 4-bit register that selects candidate packets
4221  * based on packet opcodes (0 disables the filter):
4222  *
4223  * Register Layout
4224  *
4225  * Bits | Access | Reset | Description
4226  * :-------|:-------|:--------|:---------------------------------------------------------------
4227  * [0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN
4228  * [1] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN
4229  * [2] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN
4230  * [3] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN
4231  * [31:4] | ??? | Unknown | *UNDEFINED*
4232  *
4233  */
4234 /*
4235  * Field : RDEN
4236  *
4237  * Selects RD packets.
4238  *
4239  * Field Access Macros:
4240  *
4241  */
4242 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN register field. */
4243 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN_LSB 0
4244 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN register field. */
4245 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN_MSB 0
4246 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN register field. */
4247 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN_WIDTH 1
4248 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN register field value. */
4249 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN_SET_MSK 0x00000001
4250 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN register field value. */
4251 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN_CLR_MSK 0xfffffffe
4252 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN register field. */
4253 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN_RESET 0x0
4254 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN field value from a register. */
4255 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
4256 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN register field value suitable for setting the register. */
4257 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
4258 
4259 /*
4260  * Field : WREN
4261  *
4262  * Selects WR packets.
4263  *
4264  * Field Access Macros:
4265  *
4266  */
4267 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN register field. */
4268 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN_LSB 1
4269 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN register field. */
4270 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN_MSB 1
4271 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN register field. */
4272 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN_WIDTH 1
4273 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN register field value. */
4274 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN_SET_MSK 0x00000002
4275 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN register field value. */
4276 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN_CLR_MSK 0xfffffffd
4277 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN register field. */
4278 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN_RESET 0x0
4279 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN field value from a register. */
4280 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
4281 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN register field value suitable for setting the register. */
4282 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
4283 
4284 /*
4285  * Field : LOCKEN
4286  *
4287  * Selects RDX-WR, RDL, WRC and Linked sequence.
4288  *
4289  * Field Access Macros:
4290  *
4291  */
4292 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN register field. */
4293 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN_LSB 2
4294 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN register field. */
4295 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN_MSB 2
4296 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN register field. */
4297 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN_WIDTH 1
4298 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN register field value. */
4299 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN_SET_MSK 0x00000004
4300 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN register field value. */
4301 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
4302 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN register field. */
4303 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN_RESET 0x0
4304 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN field value from a register. */
4305 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
4306 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN register field value suitable for setting the register. */
4307 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
4308 
4309 /*
4310  * Field : URGEN
4311  *
4312  * Selects URG packets (urgency).
4313  *
4314  * Field Access Macros:
4315  *
4316  */
4317 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN register field. */
4318 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN_LSB 3
4319 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN register field. */
4320 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN_MSB 3
4321 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN register field. */
4322 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN_WIDTH 1
4323 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN register field value. */
4324 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN_SET_MSK 0x00000008
4325 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN register field value. */
4326 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN_CLR_MSK 0xfffffff7
4327 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN register field. */
4328 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN_RESET 0x0
4329 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN field value from a register. */
4330 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
4331 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN register field value suitable for setting the register. */
4332 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
4333 
4334 #ifndef __ASSEMBLY__
4335 /*
4336  * WARNING: The C register and register group struct declarations are provided for
4337  * convenience and illustrative purposes. They should, however, be used with
4338  * caution as the C language standard provides no guarantees about the alignment or
4339  * atomicity of device memory accesses. The recommended practice for coding device
4340  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4341  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4342  * alt_write_dword() functions for 64 bit registers.
4343  *
4344  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE.
4345  */
4346 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_s
4347 {
4348  volatile uint32_t RDEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN */
4349  volatile uint32_t WREN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN */
4350  volatile uint32_t LOCKEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN */
4351  volatile uint32_t URGEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN */
4352  uint32_t : 28; /* *UNDEFINED* */
4353 };
4354 
4355 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE. */
4356 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_t;
4357 #endif /* __ASSEMBLY__ */
4358 
4359 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE register. */
4360 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RESET 0x00000000
4361 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE register from the beginning of the component. */
4362 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_OFST 0x114
4363 
4364 /*
4365  * Register : ddr_T_main_Probe_Filters_3_Status
4366  *
4367  * Register Status is 2-bit register that selects candidate packets based on packet
4368  * status.
4369  *
4370  * Register Layout
4371  *
4372  * Bits | Access | Reset | Description
4373  * :-------|:-------|:--------|:--------------------------------------------------------------
4374  * [0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN
4375  * [1] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN
4376  * [31:2] | ??? | Unknown | *UNDEFINED*
4377  *
4378  */
4379 /*
4380  * Field : REQEN
4381  *
4382  * Selects REQ status packets.
4383  *
4384  * Field Access Macros:
4385  *
4386  */
4387 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN register field. */
4388 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN_LSB 0
4389 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN register field. */
4390 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN_MSB 0
4391 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN register field. */
4392 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN_WIDTH 1
4393 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN register field value. */
4394 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN_SET_MSK 0x00000001
4395 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN register field value. */
4396 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN_CLR_MSK 0xfffffffe
4397 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN register field. */
4398 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN_RESET 0x0
4399 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN field value from a register. */
4400 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN_GET(value) (((value) & 0x00000001) >> 0)
4401 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN register field value suitable for setting the register. */
4402 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN_SET(value) (((value) << 0) & 0x00000001)
4403 
4404 /*
4405  * Field : RSPEN
4406  *
4407  * Selects RSP and FAIL-CONT status packets.
4408  *
4409  * Field Access Macros:
4410  *
4411  */
4412 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN register field. */
4413 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN_LSB 1
4414 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN register field. */
4415 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN_MSB 1
4416 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN register field. */
4417 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN_WIDTH 1
4418 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN register field value. */
4419 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN_SET_MSK 0x00000002
4420 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN register field value. */
4421 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN_CLR_MSK 0xfffffffd
4422 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN register field. */
4423 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN_RESET 0x0
4424 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN field value from a register. */
4425 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
4426 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN register field value suitable for setting the register. */
4427 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN_SET(value) (((value) << 1) & 0x00000002)
4428 
4429 #ifndef __ASSEMBLY__
4430 /*
4431  * WARNING: The C register and register group struct declarations are provided for
4432  * convenience and illustrative purposes. They should, however, be used with
4433  * caution as the C language standard provides no guarantees about the alignment or
4434  * atomicity of device memory accesses. The recommended practice for coding device
4435  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4436  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4437  * alt_write_dword() functions for 64 bit registers.
4438  *
4439  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS.
4440  */
4441 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_s
4442 {
4443  volatile uint32_t REQEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN */
4444  volatile uint32_t RSPEN : 1; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN */
4445  uint32_t : 30; /* *UNDEFINED* */
4446 };
4447 
4448 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS. */
4449 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_t;
4450 #endif /* __ASSEMBLY__ */
4451 
4452 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS register. */
4453 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RESET 0x00000000
4454 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS register from the beginning of the component. */
4455 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_OFST 0x118
4456 
4457 /*
4458  * Register : ddr_T_main_Probe_Filters_3_Length
4459  *
4460  * Register Layout
4461  *
4462  * Bits | Access | Reset | Description
4463  * :-------|:-------|:--------|:-------------------------------------------------------------------------
4464  * [3:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH
4465  * [31:4] | ??? | Unknown | *UNDEFINED*
4466  *
4467  */
4468 /*
4469  * Field : FILTERS_3_LENGTH
4470  *
4471  * Register Length is 4-bit register that selects candidate packets if their number
4472  * of bytes is less than or equal to 2**Length.
4473  *
4474  * Field Access Macros:
4475  *
4476  */
4477 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH register field. */
4478 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH_LSB 0
4479 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH register field. */
4480 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH_MSB 3
4481 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH register field. */
4482 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH_WIDTH 4
4483 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH register field value. */
4484 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH_SET_MSK 0x0000000f
4485 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH register field value. */
4486 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH_CLR_MSK 0xfffffff0
4487 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH register field. */
4488 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH_RESET 0x0
4489 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH field value from a register. */
4490 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH_GET(value) (((value) & 0x0000000f) >> 0)
4491 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH register field value suitable for setting the register. */
4492 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH_SET(value) (((value) << 0) & 0x0000000f)
4493 
4494 #ifndef __ASSEMBLY__
4495 /*
4496  * WARNING: The C register and register group struct declarations are provided for
4497  * convenience and illustrative purposes. They should, however, be used with
4498  * caution as the C language standard provides no guarantees about the alignment or
4499  * atomicity of device memory accesses. The recommended practice for coding device
4500  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4501  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4502  * alt_write_dword() functions for 64 bit registers.
4503  *
4504  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH.
4505  */
4506 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_s
4507 {
4508  volatile uint32_t FILTERS_3_LENGTH : 4; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH */
4509  uint32_t : 28; /* *UNDEFINED* */
4510 };
4511 
4512 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH. */
4513 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_t;
4514 #endif /* __ASSEMBLY__ */
4515 
4516 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH register. */
4517 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_RESET 0x00000000
4518 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH register from the beginning of the component. */
4519 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_OFST 0x11c
4520 
4521 /*
4522  * Register : ddr_T_main_Probe_Filters_3_Urgency
4523  *
4524  * Register Layout
4525  *
4526  * Bits | Access | Reset | Description
4527  * :-------|:-------|:--------|:---------------------------------------------------------------------------
4528  * [1:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY
4529  * [31:2] | ??? | Unknown | *UNDEFINED*
4530  *
4531  */
4532 /*
4533  * Field : FILTERS_3_URGENCY
4534  *
4535  * Register Urgency contains the minimum urgency level used to filter packets. A
4536  * packet is a candidate when its socket urgency is greater than or equal to the
4537  * urgency specified in the register.
4538  *
4539  * Field Access Macros:
4540  *
4541  */
4542 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY register field. */
4543 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY_LSB 0
4544 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY register field. */
4545 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY_MSB 1
4546 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY register field. */
4547 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY_WIDTH 2
4548 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY register field value. */
4549 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY_SET_MSK 0x00000003
4550 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY register field value. */
4551 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY_CLR_MSK 0xfffffffc
4552 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY register field. */
4553 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY_RESET 0x0
4554 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY field value from a register. */
4555 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
4556 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY register field value suitable for setting the register. */
4557 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY_SET(value) (((value) << 0) & 0x00000003)
4558 
4559 #ifndef __ASSEMBLY__
4560 /*
4561  * WARNING: The C register and register group struct declarations are provided for
4562  * convenience and illustrative purposes. They should, however, be used with
4563  * caution as the C language standard provides no guarantees about the alignment or
4564  * atomicity of device memory accesses. The recommended practice for coding device
4565  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4566  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4567  * alt_write_dword() functions for 64 bit registers.
4568  *
4569  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY.
4570  */
4571 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_s
4572 {
4573  volatile uint32_t FILTERS_3_URGENCY : 2; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY */
4574  uint32_t : 30; /* *UNDEFINED* */
4575 };
4576 
4577 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY. */
4578 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_t;
4579 #endif /* __ASSEMBLY__ */
4580 
4581 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY register. */
4582 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_RESET 0x00000000
4583 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY register from the beginning of the component. */
4584 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_OFST 0x120
4585 
4586 /*
4587  * Register : ddr_T_main_Probe_Counters_0_Src
4588  *
4589  * Register CntSrc indicates the event source used to increment the counter.
4590  * Unassigned values (non-existing Press level or ExtEvent index, or unimplemented
4591  * Filter) are equivalent to OFF.
4592  *
4593  * Register Layout
4594  *
4595  * Bits | Access | Reset | Description
4596  * :-------|:-------|:--------|:---------------------------------------------------------------
4597  * [4:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT
4598  * [31:5] | ??? | Unknown | *UNDEFINED*
4599  *
4600  */
4601 /*
4602  * Field : INTEVENT
4603  *
4604  * Internal packet event
4605  *
4606  * Field Access Macros:
4607  *
4608  */
4609 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT register field. */
4610 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_LSB 0
4611 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT register field. */
4612 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_MSB 4
4613 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT register field. */
4614 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_WIDTH 5
4615 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT register field value. */
4616 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_SET_MSK 0x0000001f
4617 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT register field value. */
4618 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_CLR_MSK 0xffffffe0
4619 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT register field. */
4620 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_RESET 0x0
4621 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT field value from a register. */
4622 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
4623 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT register field value suitable for setting the register. */
4624 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
4625 
4626 #ifndef __ASSEMBLY__
4627 /*
4628  * WARNING: The C register and register group struct declarations are provided for
4629  * convenience and illustrative purposes. They should, however, be used with
4630  * caution as the C language standard provides no guarantees about the alignment or
4631  * atomicity of device memory accesses. The recommended practice for coding device
4632  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4633  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4634  * alt_write_dword() functions for 64 bit registers.
4635  *
4636  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC.
4637  */
4638 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_s
4639 {
4640  volatile uint32_t INTEVENT : 5; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT */
4641  uint32_t : 27; /* *UNDEFINED* */
4642 };
4643 
4644 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC. */
4645 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_t;
4646 #endif /* __ASSEMBLY__ */
4647 
4648 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC register. */
4649 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_RESET 0x00000000
4650 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC register from the beginning of the component. */
4651 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_OFST 0x138
4652 
4653 /*
4654  * Register : ddr_T_main_Probe_Counters_0_AlarmMode
4655  *
4656  * Register Layout
4657  *
4658  * Bits | Access | Reset | Description
4659  * :-------|:-------|:--------|:---------------------------------------------------------------------------------
4660  * [1:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE
4661  * [31:2] | ??? | Unknown | *UNDEFINED*
4662  *
4663  */
4664 /*
4665  * Field : COUNTERS_0_ALARMMODE
4666  *
4667  * Register AlarmMode is a 2-bit register that is present when parameter
4668  * statisticsCounterAlarm is set to True. The register defines the statistics-alarm
4669  * behavior of the counter.
4670  *
4671  * Field Access Macros:
4672  *
4673  */
4674 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE register field. */
4675 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_LSB 0
4676 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE register field. */
4677 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_MSB 1
4678 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE register field. */
4679 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_WIDTH 2
4680 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE register field value. */
4681 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_SET_MSK 0x00000003
4682 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE register field value. */
4683 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_CLR_MSK 0xfffffffc
4684 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE register field. */
4685 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_RESET 0x0
4686 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE field value from a register. */
4687 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_GET(value) (((value) & 0x00000003) >> 0)
4688 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE register field value suitable for setting the register. */
4689 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_SET(value) (((value) << 0) & 0x00000003)
4690 
4691 #ifndef __ASSEMBLY__
4692 /*
4693  * WARNING: The C register and register group struct declarations are provided for
4694  * convenience and illustrative purposes. They should, however, be used with
4695  * caution as the C language standard provides no guarantees about the alignment or
4696  * atomicity of device memory accesses. The recommended practice for coding device
4697  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4698  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4699  * alt_write_dword() functions for 64 bit registers.
4700  *
4701  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE.
4702  */
4703 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_s
4704 {
4705  volatile uint32_t COUNTERS_0_ALARMMODE : 2; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE */
4706  uint32_t : 30; /* *UNDEFINED* */
4707 };
4708 
4709 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE. */
4710 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_t;
4711 #endif /* __ASSEMBLY__ */
4712 
4713 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE register. */
4714 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_RESET 0x00000000
4715 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE register from the beginning of the component. */
4716 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_OFST 0x13c
4717 
4718 /*
4719  * Register : ddr_T_main_Probe_Counters_0_Val
4720  *
4721  * Register Layout
4722  *
4723  * Bits | Access | Reset | Description
4724  * :--------|:-------|:--------|:---------------------------------------------------------------------
4725  * [15:0] | R | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL
4726  * [31:16] | ??? | Unknown | *UNDEFINED*
4727  *
4728  */
4729 /*
4730  * Field : COUNTERS_0_VAL
4731  *
4732  * Register Val is a read-only register that is always present. The register
4733  * containsthe statistics counter value either pending StatAlarm output, or when
4734  * statisticscollection is suspended subsequent to triggers or signal statSuspend.
4735  *
4736  * Field Access Macros:
4737  *
4738  */
4739 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL register field. */
4740 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_LSB 0
4741 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL register field. */
4742 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_MSB 15
4743 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL register field. */
4744 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_WIDTH 16
4745 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL register field value. */
4746 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_SET_MSK 0x0000ffff
4747 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL register field value. */
4748 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_CLR_MSK 0xffff0000
4749 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL register field. */
4750 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_RESET 0x0
4751 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL field value from a register. */
4752 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
4753 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL register field value suitable for setting the register. */
4754 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_SET(value) (((value) << 0) & 0x0000ffff)
4755 
4756 #ifndef __ASSEMBLY__
4757 /*
4758  * WARNING: The C register and register group struct declarations are provided for
4759  * convenience and illustrative purposes. They should, however, be used with
4760  * caution as the C language standard provides no guarantees about the alignment or
4761  * atomicity of device memory accesses. The recommended practice for coding device
4762  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4763  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4764  * alt_write_dword() functions for 64 bit registers.
4765  *
4766  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL.
4767  */
4768 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_s
4769 {
4770  const volatile uint32_t COUNTERS_0_VAL : 16; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL */
4771  uint32_t : 16; /* *UNDEFINED* */
4772 };
4773 
4774 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL. */
4775 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_t;
4776 #endif /* __ASSEMBLY__ */
4777 
4778 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL register. */
4779 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_RESET 0x00000000
4780 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL register from the beginning of the component. */
4781 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_OFST 0x140
4782 
4783 /*
4784  * Register : ddr_T_main_Probe_Counters_1_Src
4785  *
4786  * Register CntSrc indicates the event source used to increment the counter.
4787  * Unassigned values (non-existing Press level or ExtEvent index, or unimplemented
4788  * Filter) are equivalent to OFF.
4789  *
4790  * Register Layout
4791  *
4792  * Bits | Access | Reset | Description
4793  * :-------|:-------|:--------|:---------------------------------------------------------------
4794  * [4:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT
4795  * [31:5] | ??? | Unknown | *UNDEFINED*
4796  *
4797  */
4798 /*
4799  * Field : INTEVENT
4800  *
4801  * Internal packet event
4802  *
4803  * Field Access Macros:
4804  *
4805  */
4806 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT register field. */
4807 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_LSB 0
4808 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT register field. */
4809 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_MSB 4
4810 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT register field. */
4811 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_WIDTH 5
4812 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT register field value. */
4813 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_SET_MSK 0x0000001f
4814 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT register field value. */
4815 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_CLR_MSK 0xffffffe0
4816 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT register field. */
4817 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_RESET 0x0
4818 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT field value from a register. */
4819 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
4820 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT register field value suitable for setting the register. */
4821 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
4822 
4823 #ifndef __ASSEMBLY__
4824 /*
4825  * WARNING: The C register and register group struct declarations are provided for
4826  * convenience and illustrative purposes. They should, however, be used with
4827  * caution as the C language standard provides no guarantees about the alignment or
4828  * atomicity of device memory accesses. The recommended practice for coding device
4829  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4830  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4831  * alt_write_dword() functions for 64 bit registers.
4832  *
4833  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC.
4834  */
4835 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_s
4836 {
4837  volatile uint32_t INTEVENT : 5; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT */
4838  uint32_t : 27; /* *UNDEFINED* */
4839 };
4840 
4841 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC. */
4842 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_t;
4843 #endif /* __ASSEMBLY__ */
4844 
4845 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC register. */
4846 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_RESET 0x00000000
4847 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC register from the beginning of the component. */
4848 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_OFST 0x14c
4849 
4850 /*
4851  * Register : ddr_T_main_Probe_Counters_1_AlarmMode
4852  *
4853  * Register Layout
4854  *
4855  * Bits | Access | Reset | Description
4856  * :-------|:-------|:--------|:---------------------------------------------------------------------------------
4857  * [1:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE
4858  * [31:2] | ??? | Unknown | *UNDEFINED*
4859  *
4860  */
4861 /*
4862  * Field : COUNTERS_1_ALARMMODE
4863  *
4864  * Register AlarmMode is a 2-bit register that is present when parameter
4865  * statisticsCounterAlarm is set to True. The register defines the statistics-alarm
4866  * behavior of the counter.
4867  *
4868  * Field Access Macros:
4869  *
4870  */
4871 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE register field. */
4872 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_LSB 0
4873 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE register field. */
4874 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_MSB 1
4875 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE register field. */
4876 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_WIDTH 2
4877 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE register field value. */
4878 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_SET_MSK 0x00000003
4879 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE register field value. */
4880 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_CLR_MSK 0xfffffffc
4881 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE register field. */
4882 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_RESET 0x0
4883 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE field value from a register. */
4884 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_GET(value) (((value) & 0x00000003) >> 0)
4885 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE register field value suitable for setting the register. */
4886 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_SET(value) (((value) << 0) & 0x00000003)
4887 
4888 #ifndef __ASSEMBLY__
4889 /*
4890  * WARNING: The C register and register group struct declarations are provided for
4891  * convenience and illustrative purposes. They should, however, be used with
4892  * caution as the C language standard provides no guarantees about the alignment or
4893  * atomicity of device memory accesses. The recommended practice for coding device
4894  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4895  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4896  * alt_write_dword() functions for 64 bit registers.
4897  *
4898  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE.
4899  */
4900 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_s
4901 {
4902  volatile uint32_t COUNTERS_1_ALARMMODE : 2; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE */
4903  uint32_t : 30; /* *UNDEFINED* */
4904 };
4905 
4906 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE. */
4907 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_t;
4908 #endif /* __ASSEMBLY__ */
4909 
4910 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE register. */
4911 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_RESET 0x00000000
4912 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE register from the beginning of the component. */
4913 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_OFST 0x150
4914 
4915 /*
4916  * Register : ddr_T_main_Probe_Counters_1_Val
4917  *
4918  * Register Layout
4919  *
4920  * Bits | Access | Reset | Description
4921  * :--------|:-------|:--------|:---------------------------------------------------------------------
4922  * [15:0] | R | 0x0 | ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL
4923  * [31:16] | ??? | Unknown | *UNDEFINED*
4924  *
4925  */
4926 /*
4927  * Field : COUNTERS_1_VAL
4928  *
4929  * Register Val is a read-only register that is always present. The register
4930  * containsthe statistics counter value either pending StatAlarm output, or when
4931  * statisticscollection is suspended subsequent to triggers or signal statSuspend.
4932  *
4933  * Field Access Macros:
4934  *
4935  */
4936 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL register field. */
4937 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_LSB 0
4938 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL register field. */
4939 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_MSB 15
4940 /* The width in bits of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL register field. */
4941 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_WIDTH 16
4942 /* The mask used to set the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL register field value. */
4943 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_SET_MSK 0x0000ffff
4944 /* The mask used to clear the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL register field value. */
4945 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_CLR_MSK 0xffff0000
4946 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL register field. */
4947 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_RESET 0x0
4948 /* Extracts the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL field value from a register. */
4949 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
4950 /* Produces a ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL register field value suitable for setting the register. */
4951 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_SET(value) (((value) << 0) & 0x0000ffff)
4952 
4953 #ifndef __ASSEMBLY__
4954 /*
4955  * WARNING: The C register and register group struct declarations are provided for
4956  * convenience and illustrative purposes. They should, however, be used with
4957  * caution as the C language standard provides no guarantees about the alignment or
4958  * atomicity of device memory accesses. The recommended practice for coding device
4959  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4960  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4961  * alt_write_dword() functions for 64 bit registers.
4962  *
4963  * The struct declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL.
4964  */
4965 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_s
4966 {
4967  const volatile uint32_t COUNTERS_1_VAL : 16; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL */
4968  uint32_t : 16; /* *UNDEFINED* */
4969 };
4970 
4971 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL. */
4972 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_t;
4973 #endif /* __ASSEMBLY__ */
4974 
4975 /* The reset value of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL register. */
4976 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_RESET 0x00000000
4977 /* The byte offset of the ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL register from the beginning of the component. */
4978 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_OFST 0x154
4979 
4980 #ifndef __ASSEMBLY__
4981 /*
4982  * WARNING: The C register and register group struct declarations are provided for
4983  * convenience and illustrative purposes. They should, however, be used with
4984  * caution as the C language standard provides no guarantees about the alignment or
4985  * atomicity of device memory accesses. The recommended practice for coding device
4986  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4987  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4988  * alt_write_dword() functions for 64 bit registers.
4989  *
4990  * The struct declaration for register group ALT_MPFE_DDR_MAIN_PRB.
4991  */
4992 struct ALT_MPFE_DDR_MAIN_PRB_s
4993 {
4994  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_t ddr_T_main_Probe_Id_CoreId; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID */
4995  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_t ddr_T_main_Probe_Id_RevisionId; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID */
4996  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_t ddr_T_main_Probe_MainCtl; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL */
4997  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_t ddr_T_main_Probe_CfgCtl; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL */
4998  volatile uint32_t _pad_0x10_0x13; /* *UNDEFINED* */
4999  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_t ddr_T_main_Probe_FilterLut; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT */
5000  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_t ddr_T_main_Probe_TraceAlarmEn; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN */
5001  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_t ddr_T_main_Probe_TraceAlarmStatus; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS */
5002  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_t ddr_T_main_Probe_TraceAlarmClr; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR */
5003  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_t ddr_T_main_Probe_StatPeriod; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD */
5004  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_t ddr_T_main_Probe_StatGo; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO */
5005  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_t ddr_T_main_Probe_StatAlarmMin; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN */
5006  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_t ddr_T_main_Probe_StatAlarmMax; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX */
5007  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_t ddr_T_main_Probe_StatAlarmStatus; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS */
5008  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_t ddr_T_main_Probe_StatAlarmClr; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR */
5009  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_t ddr_T_main_Probe_StatAlarmEn; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN */
5010  volatile uint32_t _pad_0x40_0x43; /* *UNDEFINED* */
5011  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_t ddr_T_main_Probe_Filters_0_RouteIdBase; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE */
5012  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_t ddr_T_main_Probe_Filters_0_RouteIdMask; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK */
5013  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_t ddr_T_main_Probe_Filters_0_AddrBase_Low; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW */
5014  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_t ddr_T_main_Probe_Filters_0_AddrBase_High; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH */
5015  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_t ddr_T_main_Probe_Filters_0_WindowSize; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE */
5016  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_t ddr_T_main_Probe_Filters_0_SecurityBase; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE */
5017  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_t ddr_T_main_Probe_Filters_0_SecurityMask; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK */
5018  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_t ddr_T_main_Probe_Filters_0_Opcode; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE */
5019  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_t ddr_T_main_Probe_Filters_0_Status; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS */
5020  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_t ddr_T_main_Probe_Filters_0_Length; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH */
5021  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_t ddr_T_main_Probe_Filters_0_Urgency; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY */
5022  volatile uint32_t _pad_0x70_0x7f[4]; /* *UNDEFINED* */
5023  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_t ddr_T_main_Probe_Filters_1_RouteIdBase; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE */
5024  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_t ddr_T_main_Probe_Filters_1_RouteIdMask; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK */
5025  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_t ddr_T_main_Probe_Filters_1_AddrBase_Low; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW */
5026  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_t ddr_T_main_Probe_Filters_1_AddrBase_High; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH */
5027  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_t ddr_T_main_Probe_Filters_1_WindowSize; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE */
5028  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_t ddr_T_main_Probe_Filters_1_SecurityBase; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE */
5029  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_t ddr_T_main_Probe_Filters_1_SecurityMask; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK */
5030  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_t ddr_T_main_Probe_Filters_1_Opcode; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE */
5031  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_t ddr_T_main_Probe_Filters_1_Status; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS */
5032  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_t ddr_T_main_Probe_Filters_1_Length; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH */
5033  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_t ddr_T_main_Probe_Filters_1_Urgency; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY */
5034  volatile uint32_t _pad_0xac_0xbb[4]; /* *UNDEFINED* */
5035  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_t ddr_T_main_Probe_Filters_2_RouteIdBase; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE */
5036  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_t ddr_T_main_Probe_Filters_2_RouteIdMask; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK */
5037  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_t ddr_T_main_Probe_Filters_2_AddrBase_Low; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW */
5038  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_t ddr_T_main_Probe_Filters_2_AddrBase_High; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH */
5039  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_t ddr_T_main_Probe_Filters_2_WindowSize; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE */
5040  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_t ddr_T_main_Probe_Filters_2_SecurityBase; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE */
5041  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_t ddr_T_main_Probe_Filters_2_SecurityMask; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK */
5042  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_t ddr_T_main_Probe_Filters_2_Opcode; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE */
5043  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_t ddr_T_main_Probe_Filters_2_Status; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS */
5044  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_t ddr_T_main_Probe_Filters_2_Length; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH */
5045  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_t ddr_T_main_Probe_Filters_2_Urgency; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY */
5046  volatile uint32_t _pad_0xe8_0xf7[4]; /* *UNDEFINED* */
5047  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_t ddr_T_main_Probe_Filters_3_RouteIdBase; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE */
5048  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_t ddr_T_main_Probe_Filters_3_RouteIdMask; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK */
5049  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_t ddr_T_main_Probe_Filters_3_AddrBase_Low; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW */
5050  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_t ddr_T_main_Probe_Filters_3_AddrBase_High; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH */
5051  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_t ddr_T_main_Probe_Filters_3_WindowSize; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE */
5052  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_t ddr_T_main_Probe_Filters_3_SecurityBase; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE */
5053  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_t ddr_T_main_Probe_Filters_3_SecurityMask; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK */
5054  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_t ddr_T_main_Probe_Filters_3_Opcode; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE */
5055  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_t ddr_T_main_Probe_Filters_3_Status; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS */
5056  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_t ddr_T_main_Probe_Filters_3_Length; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH */
5057  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_t ddr_T_main_Probe_Filters_3_Urgency; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY */
5058  volatile uint32_t _pad_0x124_0x137[5]; /* *UNDEFINED* */
5059  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_t ddr_T_main_Probe_Counters_0_Src; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC */
5060  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_t ddr_T_main_Probe_Counters_0_AlarmMode; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE */
5061  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_t ddr_T_main_Probe_Counters_0_Val; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL */
5062  volatile uint32_t _pad_0x144_0x14b[2]; /* *UNDEFINED* */
5063  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_t ddr_T_main_Probe_Counters_1_Src; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC */
5064  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_t ddr_T_main_Probe_Counters_1_AlarmMode; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE */
5065  volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_t ddr_T_main_Probe_Counters_1_Val; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL */
5066  volatile uint32_t _pad_0x158_0x400[170]; /* *UNDEFINED* */
5067 };
5068 
5069 /* The typedef declaration for register group ALT_MPFE_DDR_MAIN_PRB. */
5070 typedef struct ALT_MPFE_DDR_MAIN_PRB_s ALT_MPFE_DDR_MAIN_PRB_t;
5071 /* The struct declaration for the raw register contents of register group ALT_MPFE_DDR_MAIN_PRB. */
5072 struct ALT_MPFE_DDR_MAIN_PRB_raw_s
5073 {
5074  volatile uint32_t ddr_T_main_Probe_Id_CoreId; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID */
5075  volatile uint32_t ddr_T_main_Probe_Id_RevisionId; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID */
5076  volatile uint32_t ddr_T_main_Probe_MainCtl; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL */
5077  volatile uint32_t ddr_T_main_Probe_CfgCtl; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL */
5078  volatile uint32_t _pad_0x10_0x13; /* *UNDEFINED* */
5079  volatile uint32_t ddr_T_main_Probe_FilterLut; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT */
5080  volatile uint32_t ddr_T_main_Probe_TraceAlarmEn; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN */
5081  volatile uint32_t ddr_T_main_Probe_TraceAlarmStatus; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS */
5082  volatile uint32_t ddr_T_main_Probe_TraceAlarmClr; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR */
5083  volatile uint32_t ddr_T_main_Probe_StatPeriod; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD */
5084  volatile uint32_t ddr_T_main_Probe_StatGo; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO */
5085  volatile uint32_t ddr_T_main_Probe_StatAlarmMin; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN */
5086  volatile uint32_t ddr_T_main_Probe_StatAlarmMax; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX */
5087  volatile uint32_t ddr_T_main_Probe_StatAlarmStatus; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS */
5088  volatile uint32_t ddr_T_main_Probe_StatAlarmClr; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR */
5089  volatile uint32_t ddr_T_main_Probe_StatAlarmEn; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN */
5090  volatile uint32_t _pad_0x40_0x43; /* *UNDEFINED* */
5091  volatile uint32_t ddr_T_main_Probe_Filters_0_RouteIdBase; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE */
5092  volatile uint32_t ddr_T_main_Probe_Filters_0_RouteIdMask; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK */
5093  volatile uint32_t ddr_T_main_Probe_Filters_0_AddrBase_Low; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW */
5094  volatile uint32_t ddr_T_main_Probe_Filters_0_AddrBase_High; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH */
5095  volatile uint32_t ddr_T_main_Probe_Filters_0_WindowSize; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE */
5096  volatile uint32_t ddr_T_main_Probe_Filters_0_SecurityBase; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE */
5097  volatile uint32_t ddr_T_main_Probe_Filters_0_SecurityMask; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK */
5098  volatile uint32_t ddr_T_main_Probe_Filters_0_Opcode; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE */
5099  volatile uint32_t ddr_T_main_Probe_Filters_0_Status; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS */
5100  volatile uint32_t ddr_T_main_Probe_Filters_0_Length; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH */
5101  volatile uint32_t ddr_T_main_Probe_Filters_0_Urgency; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY */
5102  volatile uint32_t _pad_0x70_0x7f[4]; /* *UNDEFINED* */
5103  volatile uint32_t ddr_T_main_Probe_Filters_1_RouteIdBase; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE */
5104  volatile uint32_t ddr_T_main_Probe_Filters_1_RouteIdMask; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK */
5105  volatile uint32_t ddr_T_main_Probe_Filters_1_AddrBase_Low; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW */
5106  volatile uint32_t ddr_T_main_Probe_Filters_1_AddrBase_High; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH */
5107  volatile uint32_t ddr_T_main_Probe_Filters_1_WindowSize; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE */
5108  volatile uint32_t ddr_T_main_Probe_Filters_1_SecurityBase; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE */
5109  volatile uint32_t ddr_T_main_Probe_Filters_1_SecurityMask; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK */
5110  volatile uint32_t ddr_T_main_Probe_Filters_1_Opcode; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE */
5111  volatile uint32_t ddr_T_main_Probe_Filters_1_Status; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS */
5112  volatile uint32_t ddr_T_main_Probe_Filters_1_Length; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH */
5113  volatile uint32_t ddr_T_main_Probe_Filters_1_Urgency; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY */
5114  volatile uint32_t _pad_0xac_0xbb[4]; /* *UNDEFINED* */
5115  volatile uint32_t ddr_T_main_Probe_Filters_2_RouteIdBase; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE */
5116  volatile uint32_t ddr_T_main_Probe_Filters_2_RouteIdMask; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK */
5117  volatile uint32_t ddr_T_main_Probe_Filters_2_AddrBase_Low; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW */
5118  volatile uint32_t ddr_T_main_Probe_Filters_2_AddrBase_High; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH */
5119  volatile uint32_t ddr_T_main_Probe_Filters_2_WindowSize; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE */
5120  volatile uint32_t ddr_T_main_Probe_Filters_2_SecurityBase; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE */
5121  volatile uint32_t ddr_T_main_Probe_Filters_2_SecurityMask; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK */
5122  volatile uint32_t ddr_T_main_Probe_Filters_2_Opcode; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE */
5123  volatile uint32_t ddr_T_main_Probe_Filters_2_Status; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS */
5124  volatile uint32_t ddr_T_main_Probe_Filters_2_Length; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH */
5125  volatile uint32_t ddr_T_main_Probe_Filters_2_Urgency; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY */
5126  volatile uint32_t _pad_0xe8_0xf7[4]; /* *UNDEFINED* */
5127  volatile uint32_t ddr_T_main_Probe_Filters_3_RouteIdBase; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE */
5128  volatile uint32_t ddr_T_main_Probe_Filters_3_RouteIdMask; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK */
5129  volatile uint32_t ddr_T_main_Probe_Filters_3_AddrBase_Low; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW */
5130  volatile uint32_t ddr_T_main_Probe_Filters_3_AddrBase_High; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH */
5131  volatile uint32_t ddr_T_main_Probe_Filters_3_WindowSize; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE */
5132  volatile uint32_t ddr_T_main_Probe_Filters_3_SecurityBase; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE */
5133  volatile uint32_t ddr_T_main_Probe_Filters_3_SecurityMask; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK */
5134  volatile uint32_t ddr_T_main_Probe_Filters_3_Opcode; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE */
5135  volatile uint32_t ddr_T_main_Probe_Filters_3_Status; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS */
5136  volatile uint32_t ddr_T_main_Probe_Filters_3_Length; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH */
5137  volatile uint32_t ddr_T_main_Probe_Filters_3_Urgency; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY */
5138  volatile uint32_t _pad_0x124_0x137[5]; /* *UNDEFINED* */
5139  volatile uint32_t ddr_T_main_Probe_Counters_0_Src; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC */
5140  volatile uint32_t ddr_T_main_Probe_Counters_0_AlarmMode; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE */
5141  volatile uint32_t ddr_T_main_Probe_Counters_0_Val; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL */
5142  volatile uint32_t _pad_0x144_0x14b[2]; /* *UNDEFINED* */
5143  volatile uint32_t ddr_T_main_Probe_Counters_1_Src; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC */
5144  volatile uint32_t ddr_T_main_Probe_Counters_1_AlarmMode; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE */
5145  volatile uint32_t ddr_T_main_Probe_Counters_1_Val; /* ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL */
5146  volatile uint32_t _pad_0x158_0x400[170]; /* *UNDEFINED* */
5147 };
5148 
5149 /* The typedef declaration for the raw register contents of register group ALT_MPFE_DDR_MAIN_PRB. */
5150 typedef struct ALT_MPFE_DDR_MAIN_PRB_raw_s ALT_MPFE_DDR_MAIN_PRB_raw_t;
5151 #endif /* __ASSEMBLY__ */
5152 
5153 
5154 /*
5155  * Component : MPFE_DDR_MAIN_SCHED
5156  *
5157  */
5158 /*
5159  * Register : ddr_T_main_Scheduler_Id_CoreId
5160  *
5161  * Register Layout
5162  *
5163  * Bits | Access | Reset | Description
5164  * :-------|:-------|:---------|:--------------------------------------------------------------------
5165  * [7:0] | R | 0x2 | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID
5166  * [31:8] | R | 0x6471be | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM
5167  *
5168  */
5169 /*
5170  * Field : CORETYPEID
5171  *
5172  * Field identifying the type of IP.
5173  *
5174  * Field Access Macros:
5175  *
5176  */
5177 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID register field. */
5178 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID_LSB 0
5179 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID register field. */
5180 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID_MSB 7
5181 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID register field. */
5182 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID_WIDTH 8
5183 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID register field value. */
5184 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
5185 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID register field value. */
5186 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
5187 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID register field. */
5188 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID_RESET 0x2
5189 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID field value from a register. */
5190 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
5191 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID register field value suitable for setting the register. */
5192 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
5193 
5194 /*
5195  * Field : CORECHECKSUM
5196  *
5197  * Field containing a checksum of the parameters of the IP.
5198  *
5199  * Field Access Macros:
5200  *
5201  */
5202 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM register field. */
5203 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM_LSB 8
5204 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM register field. */
5205 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM_MSB 31
5206 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM register field. */
5207 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM_WIDTH 24
5208 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM register field value. */
5209 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
5210 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM register field value. */
5211 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
5212 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM register field. */
5213 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM_RESET 0x6471be
5214 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM field value from a register. */
5215 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
5216 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM register field value suitable for setting the register. */
5217 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
5218 
5219 #ifndef __ASSEMBLY__
5220 /*
5221  * WARNING: The C register and register group struct declarations are provided for
5222  * convenience and illustrative purposes. They should, however, be used with
5223  * caution as the C language standard provides no guarantees about the alignment or
5224  * atomicity of device memory accesses. The recommended practice for coding device
5225  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5226  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5227  * alt_write_dword() functions for 64 bit registers.
5228  *
5229  * The struct declaration for register ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID.
5230  */
5231 struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_s
5232 {
5233  const volatile uint32_t CORETYPEID : 8; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID */
5234  const volatile uint32_t CORECHECKSUM : 24; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM */
5235 };
5236 
5237 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID. */
5238 typedef struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_s ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_t;
5239 #endif /* __ASSEMBLY__ */
5240 
5241 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID register. */
5242 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_RESET 0x6471be02
5243 /* The byte offset of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID register from the beginning of the component. */
5244 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_OFST 0x0
5245 
5246 /*
5247  * Register : ddr_T_main_Scheduler_Id_RevisionId
5248  *
5249  * Register Layout
5250  *
5251  * Bits | Access | Reset | Description
5252  * :-------|:-------|:------|:---------------------------------------------------------------------
5253  * [7:0] | R | 0x0 | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID
5254  * [31:8] | R | 0x148 | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID
5255  *
5256  */
5257 /*
5258  * Field : USERID
5259  *
5260  * Field containing a user defined value, not used anywhere inside the IP itself.
5261  *
5262  * Field Access Macros:
5263  *
5264  */
5265 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID register field. */
5266 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID_LSB 0
5267 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID register field. */
5268 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID_MSB 7
5269 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID register field. */
5270 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID_WIDTH 8
5271 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID register field value. */
5272 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID_SET_MSK 0x000000ff
5273 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID register field value. */
5274 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
5275 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID register field. */
5276 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID_RESET 0x0
5277 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID field value from a register. */
5278 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
5279 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID register field value suitable for setting the register. */
5280 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
5281 
5282 /*
5283  * Field : FLEXNOCID
5284  *
5285  * Field containing the build revision of the software used to generate the IP HDL
5286  * code.
5287  *
5288  * Field Access Macros:
5289  *
5290  */
5291 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID register field. */
5292 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID_LSB 8
5293 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID register field. */
5294 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID_MSB 31
5295 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID register field. */
5296 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID_WIDTH 24
5297 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID register field value. */
5298 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
5299 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID register field value. */
5300 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
5301 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID register field. */
5302 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID_RESET 0x148
5303 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID field value from a register. */
5304 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
5305 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID register field value suitable for setting the register. */
5306 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
5307 
5308 #ifndef __ASSEMBLY__
5309 /*
5310  * WARNING: The C register and register group struct declarations are provided for
5311  * convenience and illustrative purposes. They should, however, be used with
5312  * caution as the C language standard provides no guarantees about the alignment or
5313  * atomicity of device memory accesses. The recommended practice for coding device
5314  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5315  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5316  * alt_write_dword() functions for 64 bit registers.
5317  *
5318  * The struct declaration for register ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID.
5319  */
5320 struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_s
5321 {
5322  const volatile uint32_t USERID : 8; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID */
5323  const volatile uint32_t FLEXNOCID : 24; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID */
5324 };
5325 
5326 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID. */
5327 typedef struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_s ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_t;
5328 #endif /* __ASSEMBLY__ */
5329 
5330 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID register. */
5331 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_RESET 0x00014800
5332 /* The byte offset of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID register from the beginning of the component. */
5333 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_OFST 0x4
5334 
5335 /*
5336  * Register : ddr_T_main_Scheduler_DdrConf
5337  *
5338  * ddr configuration definition.
5339  *
5340  * Register Layout
5341  *
5342  * Bits | Access | Reset | Description
5343  * :-------|:-------|:--------|:-------------------------------------------------------------
5344  * [4:0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF
5345  * [31:5] | ??? | Unknown | *UNDEFINED*
5346  *
5347  */
5348 /*
5349  * Field : DDRCONF
5350  *
5351  * Selection of a configuration of mappings of address bits to memory device, bank,
5352  * row, and column. <See SoC-specific DDR Conf documentation>
5353  *
5354  * Field Enumeration Values:
5355  *
5356  * Enum | Value | Description
5357  * :--------------------------------------------------------------------------|:------|:------------
5358  * ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R12_B3_C10 | 0x00 |
5359  * ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R13_B3_C9 | 0x01 |
5360  * ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R13_B3_C10 | 0x02 |
5361  * ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R14_B3_C9 | 0x03 |
5362  * ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R14_B3_C10 | 0x04 |
5363  * ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R15_B3_C10 | 0x05 |
5364  * ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R14_B3_C11 | 0x06 |
5365  * ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R15_B3_C11 | 0x07 |
5366  * ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R16_B3_C10 | 0x08 |
5367  * ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R16_B3_C11 | 0x09 |
5368  * ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R15_B3_C12 | 0x0A |
5369  * ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B3_R14_C10 | 0x0B |
5370  * ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B4_R14_C10 | 0x0C |
5371  * ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B3_R15_C10 | 0x0D |
5372  * ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B4_R15_C10 | 0x0E |
5373  * ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B3_R16_C10 | 0x0F |
5374  * ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B4_R16_C10 | 0x10 |
5375  * ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B3_R17_C10 | 0x11 |
5376  * ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B4_R17_C10 | 0x12 |
5377  *
5378  * Field Access Macros:
5379  *
5380  */
5381 /*
5382  * Enumerated value for register field ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF
5383  *
5384  * DDR3 or LPDDR3
5385  */
5386 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R12_B3_C10 0x00
5387 /*
5388  * Enumerated value for register field ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF
5389  *
5390  * DDR3 or LPDDR3
5391  */
5392 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R13_B3_C9 0x01
5393 /*
5394  * Enumerated value for register field ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF
5395  *
5396  * DDR3 or LPDDR3
5397  */
5398 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R13_B3_C10 0x02
5399 /*
5400  * Enumerated value for register field ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF
5401  *
5402  * DDR3 or LPDDR3
5403  */
5404 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R14_B3_C9 0x03
5405 /*
5406  * Enumerated value for register field ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF
5407  *
5408  * DDR3 or LPDDR3
5409  */
5410 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R14_B3_C10 0x04
5411 /*
5412  * Enumerated value for register field ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF
5413  *
5414  * DDR3 or LPDDR3
5415  */
5416 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R15_B3_C10 0x05
5417 /*
5418  * Enumerated value for register field ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF
5419  *
5420  * DDR3 or LPDDR3
5421  */
5422 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R14_B3_C11 0x06
5423 /*
5424  * Enumerated value for register field ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF
5425  *
5426  * DDR3 or LPDDR3
5427  */
5428 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R15_B3_C11 0x07
5429 /*
5430  * Enumerated value for register field ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF
5431  *
5432  * DDR3 or LPDDR3
5433  */
5434 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R16_B3_C10 0x08
5435 /*
5436  * Enumerated value for register field ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF
5437  *
5438  * DDR3 or LPDDR3
5439  */
5440 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R16_B3_C11 0x09
5441 /*
5442  * Enumerated value for register field ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF
5443  *
5444  * DDR3 or LPDDR3
5445  */
5446 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R15_B3_C12 0x0A
5447 /*
5448  * Enumerated value for register field ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF
5449  *
5450  * DDR4 only
5451  */
5452 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B3_R14_C10 0x0B
5453 /*
5454  * Enumerated value for register field ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF
5455  *
5456  * DDR4 only
5457  */
5458 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B4_R14_C10 0x0C
5459 /*
5460  * Enumerated value for register field ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF
5461  *
5462  * DDR4 only
5463  */
5464 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B3_R15_C10 0x0D
5465 /*
5466  * Enumerated value for register field ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF
5467  *
5468  * DDR4 only
5469  */
5470 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B4_R15_C10 0x0E
5471 /*
5472  * Enumerated value for register field ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF
5473  *
5474  * DDR4 only
5475  */
5476 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B3_R16_C10 0x0F
5477 /*
5478  * Enumerated value for register field ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF
5479  *
5480  * DDR4 only
5481  */
5482 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B4_R16_C10 0x10
5483 /*
5484  * Enumerated value for register field ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF
5485  *
5486  * DDR4 only
5487  */
5488 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B3_R17_C10 0x11
5489 /*
5490  * Enumerated value for register field ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF
5491  *
5492  * DDR4 only
5493  */
5494 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B4_R17_C10 0x12
5495 
5496 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF register field. */
5497 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_LSB 0
5498 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF register field. */
5499 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_MSB 4
5500 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF register field. */
5501 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_WIDTH 5
5502 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF register field value. */
5503 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_SET_MSK 0x0000001f
5504 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF register field value. */
5505 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_CLR_MSK 0xffffffe0
5506 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF register field. */
5507 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_RESET 0x0
5508 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF field value from a register. */
5509 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_GET(value) (((value) & 0x0000001f) >> 0)
5510 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF register field value suitable for setting the register. */
5511 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_SET(value) (((value) << 0) & 0x0000001f)
5512 
5513 #ifndef __ASSEMBLY__
5514 /*
5515  * WARNING: The C register and register group struct declarations are provided for
5516  * convenience and illustrative purposes. They should, however, be used with
5517  * caution as the C language standard provides no guarantees about the alignment or
5518  * atomicity of device memory accesses. The recommended practice for coding device
5519  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5520  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5521  * alt_write_dword() functions for 64 bit registers.
5522  *
5523  * The struct declaration for register ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF.
5524  */
5525 struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_s
5526 {
5527  volatile uint32_t DDRCONF : 5; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF */
5528  uint32_t : 27; /* *UNDEFINED* */
5529 };
5530 
5531 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF. */
5532 typedef struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_s ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_t;
5533 #endif /* __ASSEMBLY__ */
5534 
5535 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF register. */
5536 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_RESET 0x00000000
5537 /* The byte offset of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF register from the beginning of the component. */
5538 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_OFST 0x8
5539 
5540 /*
5541  * Register : ddr_T_main_Scheduler_DdrTiming
5542  *
5543  * ddr timing definition.
5544  *
5545  * Register Layout
5546  *
5547  * Bits | Access | Reset | Description
5548  * :--------|:-------|:------|:----------------------------------------------------------------
5549  * [5:0] | RW | 0x1f | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT
5550  * [11:6] | RW | 0x15 | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS
5551  * [17:12] | RW | 0x25 | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS
5552  * [20:18] | RW | 0x3 | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN
5553  * [25:21] | RW | 0x2 | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR
5554  * [30:26] | RW | 0xc | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD
5555  * [31] | RW | 0x1 | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO
5556  *
5557  */
5558 /*
5559  * Field : ACTTOACT
5560  *
5561  * The minimum number of scheduler clock cycles between two consecutive DRAM
5562  * Activate commands on the same bank (tRC/ tCkG). tCkG is the clock period of the
5563  * SoC DRAM scheduler.
5564  *
5565  * Field Access Macros:
5566  *
5567  */
5568 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT register field. */
5569 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT_LSB 0
5570 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT register field. */
5571 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT_MSB 5
5572 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT register field. */
5573 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT_WIDTH 6
5574 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT register field value. */
5575 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT_SET_MSK 0x0000003f
5576 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT register field value. */
5577 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT_CLR_MSK 0xffffffc0
5578 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT register field. */
5579 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT_RESET 0x1f
5580 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT field value from a register. */
5581 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT_GET(value) (((value) & 0x0000003f) >> 0)
5582 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT register field value suitable for setting the register. */
5583 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT_SET(value) (((value) << 0) & 0x0000003f)
5584 
5585 /*
5586  * Field : RDTOMISS
5587  *
5588  * The minimum number of scheduler clock cycles between the last DRAM Read command
5589  * and a new Read or Write command in another page of the same bank (tRTP + tRP +
5590  * tRCD - BL x tCkD / 2). tCkD is the DRAM clock period.
5591  *
5592  * Field Access Macros:
5593  *
5594  */
5595 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS register field. */
5596 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS_LSB 6
5597 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS register field. */
5598 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS_MSB 11
5599 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS register field. */
5600 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS_WIDTH 6
5601 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS register field value. */
5602 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS_SET_MSK 0x00000fc0
5603 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS register field value. */
5604 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS_CLR_MSK 0xfffff03f
5605 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS register field. */
5606 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS_RESET 0x15
5607 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS field value from a register. */
5608 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS_GET(value) (((value) & 0x00000fc0) >> 6)
5609 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS register field value suitable for setting the register. */
5610 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS_SET(value) (((value) << 6) & 0x00000fc0)
5611 
5612 /*
5613  * Field : WRTOMISS
5614  *
5615  * The minimum number of scheduler clock cycles between the last DRAM Write command
5616  * and a new Read or Write command in another page of the same bank (WL x tCkD +
5617  * tWR + tRP + tRCD). tCkD is the DRAM clock period.
5618  *
5619  * Field Access Macros:
5620  *
5621  */
5622 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS register field. */
5623 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS_LSB 12
5624 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS register field. */
5625 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS_MSB 17
5626 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS register field. */
5627 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS_WIDTH 6
5628 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS register field value. */
5629 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS_SET_MSK 0x0003f000
5630 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS register field value. */
5631 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS_CLR_MSK 0xfffc0fff
5632 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS register field. */
5633 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS_RESET 0x25
5634 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS field value from a register. */
5635 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS_GET(value) (((value) & 0x0003f000) >> 12)
5636 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS register field value suitable for setting the register. */
5637 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS_SET(value) (((value) << 12) & 0x0003f000)
5638 
5639 /*
5640  * Field : BURSTLEN
5641  *
5642  * The DRAM burst duration on the DRAM data bus in scheduler clock cycles. Also
5643  * equal to scheduler clock cycles between two DRAM commands (BL / 2 x tCkD). tCkD
5644  * is the DRAM clock period.
5645  *
5646  * Field Access Macros:
5647  *
5648  */
5649 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN register field. */
5650 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN_LSB 18
5651 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN register field. */
5652 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN_MSB 20
5653 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN register field. */
5654 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN_WIDTH 3
5655 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN register field value. */
5656 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN_SET_MSK 0x001c0000
5657 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN register field value. */
5658 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN_CLR_MSK 0xffe3ffff
5659 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN register field. */
5660 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN_RESET 0x3
5661 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN field value from a register. */
5662 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN_GET(value) (((value) & 0x001c0000) >> 18)
5663 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN register field value suitable for setting the register. */
5664 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN_SET(value) (((value) << 18) & 0x001c0000)
5665 
5666 /*
5667  * Field : RDTOWR
5668  *
5669  * The minimum number of scheduler clock cycles between the last DRAM Read command
5670  * and a Write command (DDR2: 2 x tCkD, DDR3: (RL - WL + 2) x tCkD). tCkD is the
5671  * DRAM clock period.
5672  *
5673  * Field Access Macros:
5674  *
5675  */
5676 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR register field. */
5677 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR_LSB 21
5678 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR register field. */
5679 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR_MSB 25
5680 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR register field. */
5681 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR_WIDTH 5
5682 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR register field value. */
5683 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR_SET_MSK 0x03e00000
5684 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR register field value. */
5685 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR_CLR_MSK 0xfc1fffff
5686 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR register field. */
5687 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR_RESET 0x2
5688 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR field value from a register. */
5689 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR_GET(value) (((value) & 0x03e00000) >> 21)
5690 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR register field value suitable for setting the register. */
5691 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR_SET(value) (((value) << 21) & 0x03e00000)
5692 
5693 /*
5694  * Field : WRTORD
5695  *
5696  * The minimum number of scheduler clock cycles between the last DRAM Write command
5697  * and a Read command (WL x tCkD + tWTR). tCkD is the DRAM clock period.
5698  *
5699  * Field Access Macros:
5700  *
5701  */
5702 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD register field. */
5703 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD_LSB 26
5704 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD register field. */
5705 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD_MSB 30
5706 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD register field. */
5707 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD_WIDTH 5
5708 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD register field value. */
5709 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD_SET_MSK 0x7c000000
5710 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD register field value. */
5711 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD_CLR_MSK 0x83ffffff
5712 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD register field. */
5713 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD_RESET 0xc
5714 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD field value from a register. */
5715 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD_GET(value) (((value) & 0x7c000000) >> 26)
5716 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD register field value suitable for setting the register. */
5717 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD_SET(value) (((value) << 26) & 0x7c000000)
5718 
5719 /*
5720  * Field : BWRATIO
5721  *
5722  * When set to zero, one DRAM clock cycle (two DDR transfers) is used to transfer
5723  * each word of data. When set to one, two DRAM clock cycles (four DDR transfers)
5724  * are used to transfer each word of data. This is applicable when half of a DRAM
5725  * data bus width is used.
5726  *
5727  * Field Access Macros:
5728  *
5729  */
5730 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO register field. */
5731 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO_LSB 31
5732 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO register field. */
5733 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO_MSB 31
5734 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO register field. */
5735 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO_WIDTH 1
5736 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO register field value. */
5737 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO_SET_MSK 0x80000000
5738 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO register field value. */
5739 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO_CLR_MSK 0x7fffffff
5740 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO register field. */
5741 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO_RESET 0x1
5742 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO field value from a register. */
5743 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO_GET(value) (((value) & 0x80000000) >> 31)
5744 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO register field value suitable for setting the register. */
5745 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO_SET(value) (((value) << 31) & 0x80000000)
5746 
5747 #ifndef __ASSEMBLY__
5748 /*
5749  * WARNING: The C register and register group struct declarations are provided for
5750  * convenience and illustrative purposes. They should, however, be used with
5751  * caution as the C language standard provides no guarantees about the alignment or
5752  * atomicity of device memory accesses. The recommended practice for coding device
5753  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5754  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5755  * alt_write_dword() functions for 64 bit registers.
5756  *
5757  * The struct declaration for register ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING.
5758  */
5759 struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_s
5760 {
5761  volatile uint32_t ACTTOACT : 6; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT */
5762  volatile uint32_t RDTOMISS : 6; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS */
5763  volatile uint32_t WRTOMISS : 6; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS */
5764  volatile uint32_t BURSTLEN : 3; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN */
5765  volatile uint32_t RDTOWR : 5; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR */
5766  volatile uint32_t WRTORD : 5; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD */
5767  volatile uint32_t BWRATIO : 1; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO */
5768 };
5769 
5770 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING. */
5771 typedef struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_s ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_t;
5772 #endif /* __ASSEMBLY__ */
5773 
5774 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING register. */
5775 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RESET 0xb04e555f
5776 /* The byte offset of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING register from the beginning of the component. */
5777 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_OFST 0xc
5778 
5779 /*
5780  * Register : ddr_T_main_Scheduler_DdrMode
5781  *
5782  * ddr mode definition.
5783  *
5784  * Register Layout
5785  *
5786  * Bits | Access | Reset | Description
5787  * :-------|:-------|:--------|:---------------------------------------------------------------------
5788  * [0] | RW | 0x0 | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE
5789  * [1] | RW | 0x0 | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED
5790  * [31:2] | ??? | Unknown | *UNDEFINED*
5791  *
5792  */
5793 /*
5794  * Field : AUTOPRECHARGE
5795  *
5796  * When set to one, pages are automatically closed after each access, when set to
5797  * zero, pages are left opened until an access in a different page occurs
5798  *
5799  * Field Access Macros:
5800  *
5801  */
5802 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE register field. */
5803 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE_LSB 0
5804 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE register field. */
5805 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE_MSB 0
5806 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE register field. */
5807 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE_WIDTH 1
5808 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE register field value. */
5809 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE_SET_MSK 0x00000001
5810 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE register field value. */
5811 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE_CLR_MSK 0xfffffffe
5812 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE register field. */
5813 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE_RESET 0x0
5814 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE field value from a register. */
5815 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE_GET(value) (((value) & 0x00000001) >> 0)
5816 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE register field value suitable for setting the register. */
5817 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE_SET(value) (((value) << 0) & 0x00000001)
5818 
5819 /*
5820  * Field : BWRATIOEXTENDED
5821  *
5822  * When set to 1, support for 4x Bwratio.
5823  *
5824  * Field Access Macros:
5825  *
5826  */
5827 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED register field. */
5828 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED_LSB 1
5829 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED register field. */
5830 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED_MSB 1
5831 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED register field. */
5832 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED_WIDTH 1
5833 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED register field value. */
5834 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED_SET_MSK 0x00000002
5835 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED register field value. */
5836 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED_CLR_MSK 0xfffffffd
5837 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED register field. */
5838 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED_RESET 0x0
5839 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED field value from a register. */
5840 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED_GET(value) (((value) & 0x00000002) >> 1)
5841 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED register field value suitable for setting the register. */
5842 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED_SET(value) (((value) << 1) & 0x00000002)
5843 
5844 #ifndef __ASSEMBLY__
5845 /*
5846  * WARNING: The C register and register group struct declarations are provided for
5847  * convenience and illustrative purposes. They should, however, be used with
5848  * caution as the C language standard provides no guarantees about the alignment or
5849  * atomicity of device memory accesses. The recommended practice for coding device
5850  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5851  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5852  * alt_write_dword() functions for 64 bit registers.
5853  *
5854  * The struct declaration for register ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE.
5855  */
5856 struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_s
5857 {
5858  volatile uint32_t AUTOPRECHARGE : 1; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE */
5859  volatile uint32_t BWRATIOEXTENDED : 1; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED */
5860  uint32_t : 30; /* *UNDEFINED* */
5861 };
5862 
5863 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE. */
5864 typedef struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_s ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_t;
5865 #endif /* __ASSEMBLY__ */
5866 
5867 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE register. */
5868 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_RESET 0x00000000
5869 /* The byte offset of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE register from the beginning of the component. */
5870 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_OFST 0x10
5871 
5872 /*
5873  * Register : ddr_T_main_Scheduler_ReadLatency
5874  *
5875  * Register Layout
5876  *
5877  * Bits | Access | Reset | Description
5878  * :-------|:-------|:--------|:---------------------------------------------------------------------
5879  * [7:0] | RW | 0x3d | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY
5880  * [31:8] | ??? | Unknown | *UNDEFINED*
5881  *
5882  */
5883 /*
5884  * Field : READLATENCY
5885  *
5886  * The DRAM type-specific number of cycles from a scheduler request to a protocol
5887  * controller response. This is a fixed value depending on the type of DRAM memory.
5888  * <See SoC-specific memory controller documentation>.
5889  *
5890  * Field Access Macros:
5891  *
5892  */
5893 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY register field. */
5894 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY_LSB 0
5895 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY register field. */
5896 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY_MSB 7
5897 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY register field. */
5898 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY_WIDTH 8
5899 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY register field value. */
5900 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY_SET_MSK 0x000000ff
5901 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY register field value. */
5902 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY_CLR_MSK 0xffffff00
5903 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY register field. */
5904 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY_RESET 0x3d
5905 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY field value from a register. */
5906 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY_GET(value) (((value) & 0x000000ff) >> 0)
5907 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY register field value suitable for setting the register. */
5908 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY_SET(value) (((value) << 0) & 0x000000ff)
5909 
5910 #ifndef __ASSEMBLY__
5911 /*
5912  * WARNING: The C register and register group struct declarations are provided for
5913  * convenience and illustrative purposes. They should, however, be used with
5914  * caution as the C language standard provides no guarantees about the alignment or
5915  * atomicity of device memory accesses. The recommended practice for coding device
5916  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5917  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5918  * alt_write_dword() functions for 64 bit registers.
5919  *
5920  * The struct declaration for register ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY.
5921  */
5922 struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_s
5923 {
5924  volatile uint32_t READLATENCY : 8; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY */
5925  uint32_t : 24; /* *UNDEFINED* */
5926 };
5927 
5928 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY. */
5929 typedef struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_s ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_t;
5930 #endif /* __ASSEMBLY__ */
5931 
5932 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY register. */
5933 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_RESET 0x0000003d
5934 /* The byte offset of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY register from the beginning of the component. */
5935 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_OFST 0x14
5936 
5937 /*
5938  * Register : ddr_T_main_Scheduler_Activate
5939  *
5940  * timing values concerning Activate commands, in Generic clock unit.
5941  *
5942  * Register Layout
5943  *
5944  * Bits | Access | Reset | Description
5945  * :--------|:-------|:--------|:--------------------------------------------------------------
5946  * [3:0] | RW | 0x3 | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD
5947  * [9:4] | RW | 0xf | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW
5948  * [10] | RW | 0x1 | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK
5949  * [31:11] | ??? | Unknown | *UNDEFINED*
5950  *
5951  */
5952 /*
5953  * Field : RRD
5954  *
5955  * 'The number of cycles between two consecutive Activate commands on different
5956  * Banks of the same device (tRRD).
5957  *
5958  * Field Access Macros:
5959  *
5960  */
5961 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD register field. */
5962 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD_LSB 0
5963 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD register field. */
5964 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD_MSB 3
5965 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD register field. */
5966 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD_WIDTH 4
5967 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD register field value. */
5968 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD_SET_MSK 0x0000000f
5969 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD register field value. */
5970 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD_CLR_MSK 0xfffffff0
5971 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD register field. */
5972 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD_RESET 0x3
5973 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD field value from a register. */
5974 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD_GET(value) (((value) & 0x0000000f) >> 0)
5975 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD register field value suitable for setting the register. */
5976 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD_SET(value) (((value) << 0) & 0x0000000f)
5977 
5978 /*
5979  * Field : FAW
5980  *
5981  * The number of cycles for the four bank activate (FAW) period (tFAW).
5982  *
5983  * Field Access Macros:
5984  *
5985  */
5986 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW register field. */
5987 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW_LSB 4
5988 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW register field. */
5989 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW_MSB 9
5990 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW register field. */
5991 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW_WIDTH 6
5992 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW register field value. */
5993 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW_SET_MSK 0x000003f0
5994 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW register field value. */
5995 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW_CLR_MSK 0xfffffc0f
5996 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW register field. */
5997 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW_RESET 0xf
5998 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW field value from a register. */
5999 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW_GET(value) (((value) & 0x000003f0) >> 4)
6000 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW register field value suitable for setting the register. */
6001 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW_SET(value) (((value) << 4) & 0x000003f0)
6002 
6003 /*
6004  * Field : FAWBANK
6005  *
6006  * The number of Banks of a given device involved in the FAW period. Set to zero
6007  * for 2-bank memories (WideIO). Set to one for memories with 4 banks or more
6008  * (DDR).
6009  *
6010  * Field Access Macros:
6011  *
6012  */
6013 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK register field. */
6014 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK_LSB 10
6015 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK register field. */
6016 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK_MSB 10
6017 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK register field. */
6018 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK_WIDTH 1
6019 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK register field value. */
6020 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK_SET_MSK 0x00000400
6021 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK register field value. */
6022 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK_CLR_MSK 0xfffffbff
6023 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK register field. */
6024 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK_RESET 0x1
6025 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK field value from a register. */
6026 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK_GET(value) (((value) & 0x00000400) >> 10)
6027 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK register field value suitable for setting the register. */
6028 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK_SET(value) (((value) << 10) & 0x00000400)
6029 
6030 #ifndef __ASSEMBLY__
6031 /*
6032  * WARNING: The C register and register group struct declarations are provided for
6033  * convenience and illustrative purposes. They should, however, be used with
6034  * caution as the C language standard provides no guarantees about the alignment or
6035  * atomicity of device memory accesses. The recommended practice for coding device
6036  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6037  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6038  * alt_write_dword() functions for 64 bit registers.
6039  *
6040  * The struct declaration for register ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE.
6041  */
6042 struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_s
6043 {
6044  volatile uint32_t RRD : 4; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD */
6045  volatile uint32_t FAW : 6; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW */
6046  volatile uint32_t FAWBANK : 1; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK */
6047  uint32_t : 21; /* *UNDEFINED* */
6048 };
6049 
6050 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE. */
6051 typedef struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_s ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_t;
6052 #endif /* __ASSEMBLY__ */
6053 
6054 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE register. */
6055 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RESET 0x000004f3
6056 /* The byte offset of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE register from the beginning of the component. */
6057 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_OFST 0x38
6058 
6059 /*
6060  * Register : ddr_T_main_Scheduler_DevToDev
6061  *
6062  * timing values concerning device to device data bus ownership change, in Generic
6063  * clock unit.
6064  *
6065  * Register Layout
6066  *
6067  * Bits | Access | Reset | Description
6068  * :-------|:-------|:--------|:----------------------------------------------------------------
6069  * [1:0] | RW | 0x1 | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD
6070  * [3:2] | RW | 0x2 | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR
6071  * [5:4] | RW | 0x2 | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD
6072  * [31:6] | ??? | Unknown | *UNDEFINED*
6073  *
6074  */
6075 /*
6076  * Field : BUSRDTORD
6077  *
6078  * The number of cycles between the last read data of a device and the first read
6079  * data of another device of a memory array with multiple ranks (tCkD). tCkD is the
6080  * DRAM clock period.
6081  *
6082  * Field Access Macros:
6083  *
6084  */
6085 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD register field. */
6086 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD_LSB 0
6087 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD register field. */
6088 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD_MSB 1
6089 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD register field. */
6090 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD_WIDTH 2
6091 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD register field value. */
6092 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD_SET_MSK 0x00000003
6093 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD register field value. */
6094 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD_CLR_MSK 0xfffffffc
6095 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD register field. */
6096 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD_RESET 0x1
6097 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD field value from a register. */
6098 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD_GET(value) (((value) & 0x00000003) >> 0)
6099 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD register field value suitable for setting the register. */
6100 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD_SET(value) (((value) << 0) & 0x00000003)
6101 
6102 /*
6103  * Field : BUSRDTOWR
6104  *
6105  * The number of cycles between the last read data of a device and the first write
6106  * data to another device of a memory array with multiple ranks (2 x tCkD). tCkD is
6107  * the DRAM clock period.
6108  *
6109  * Field Access Macros:
6110  *
6111  */
6112 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR register field. */
6113 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR_LSB 2
6114 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR register field. */
6115 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR_MSB 3
6116 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR register field. */
6117 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR_WIDTH 2
6118 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR register field value. */
6119 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR_SET_MSK 0x0000000c
6120 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR register field value. */
6121 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR_CLR_MSK 0xfffffff3
6122 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR register field. */
6123 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR_RESET 0x2
6124 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR field value from a register. */
6125 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR_GET(value) (((value) & 0x0000000c) >> 2)
6126 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR register field value suitable for setting the register. */
6127 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR_SET(value) (((value) << 2) & 0x0000000c)
6128 
6129 /*
6130  * Field : BUSWRTORD
6131  *
6132  * The number of cycles between the last write data to a device and the first read
6133  * data of another device of a memory array with multiple ranks (2 x tCkD). tCkD is
6134  * the DRAM clock period.
6135  *
6136  * Field Access Macros:
6137  *
6138  */
6139 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD register field. */
6140 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD_LSB 4
6141 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD register field. */
6142 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD_MSB 5
6143 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD register field. */
6144 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD_WIDTH 2
6145 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD register field value. */
6146 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD_SET_MSK 0x00000030
6147 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD register field value. */
6148 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD_CLR_MSK 0xffffffcf
6149 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD register field. */
6150 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD_RESET 0x2
6151 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD field value from a register. */
6152 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD_GET(value) (((value) & 0x00000030) >> 4)
6153 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD register field value suitable for setting the register. */
6154 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD_SET(value) (((value) << 4) & 0x00000030)
6155 
6156 #ifndef __ASSEMBLY__
6157 /*
6158  * WARNING: The C register and register group struct declarations are provided for
6159  * convenience and illustrative purposes. They should, however, be used with
6160  * caution as the C language standard provides no guarantees about the alignment or
6161  * atomicity of device memory accesses. The recommended practice for coding device
6162  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6163  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6164  * alt_write_dword() functions for 64 bit registers.
6165  *
6166  * The struct declaration for register ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV.
6167  */
6168 struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_s
6169 {
6170  volatile uint32_t BUSRDTORD : 2; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD */
6171  volatile uint32_t BUSRDTOWR : 2; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR */
6172  volatile uint32_t BUSWRTORD : 2; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD */
6173  uint32_t : 26; /* *UNDEFINED* */
6174 };
6175 
6176 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV. */
6177 typedef struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_s ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_t;
6178 #endif /* __ASSEMBLY__ */
6179 
6180 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV register. */
6181 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_RESET 0x00000029
6182 /* The byte offset of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV register from the beginning of the component. */
6183 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_OFST 0x3c
6184 
6185 /*
6186  * Register : ddr_T_main_Scheduler_Ddr4Timing
6187  *
6188  * Long timing for DDR4 Bank Group support.
6189  *
6190  * Register Layout
6191  *
6192  * Bits | Access | Reset | Description
6193  * :--------|:-------|:--------|:----------------------------------------------------------------
6194  * [2:0] | RW | 0x7 | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL
6195  * [7:3] | RW | 0xc | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL
6196  * [11:8] | RW | 0x3 | ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL
6197  * [31:12] | ??? | Unknown | *UNDEFINED*
6198  *
6199  */
6200 /*
6201  * Field : CCDL
6202  *
6203  * Project-Id-Version: 2.11.4
6204  *
6205  * Report-Msgid-Bugs-To:
6206  *
6207  * POT-Creation-Date: 2015-03-03 12:49+CET
6208  *
6209  * PO-Revision-Date: 2009-01-19 17:46+0100
6210  *
6211  * Last-Translator: ARTERIS <twt@arteris.com>
6212  *
6213  * Language-Team: en_US <twt@arteris.com>
6214  *
6215  * MIME-Version: 1.0
6216  *
6217  * Content-Type: text/plain; charset=UTF-8
6218  *
6219  * Content-Transfer-Encoding: 8bit
6220  *
6221  * Field Access Macros:
6222  *
6223  */
6224 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL register field. */
6225 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL_LSB 0
6226 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL register field. */
6227 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL_MSB 2
6228 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL register field. */
6229 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL_WIDTH 3
6230 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL register field value. */
6231 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL_SET_MSK 0x00000007
6232 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL register field value. */
6233 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL_CLR_MSK 0xfffffff8
6234 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL register field. */
6235 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL_RESET 0x7
6236 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL field value from a register. */
6237 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL_GET(value) (((value) & 0x00000007) >> 0)
6238 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL register field value suitable for setting the register. */
6239 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL_SET(value) (((value) << 0) & 0x00000007)
6240 
6241 /*
6242  * Field : WRTORDL
6243  *
6244  * Project-Id-Version: 2.11.4
6245  *
6246  * Report-Msgid-Bugs-To:
6247  *
6248  * POT-Creation-Date: 2015-03-03 12:49+CET
6249  *
6250  * PO-Revision-Date: 2009-01-19 17:46+0100
6251  *
6252  * Last-Translator: ARTERIS <twt@arteris.com>
6253  *
6254  * Language-Team: en_US <twt@arteris.com>
6255  *
6256  * MIME-Version: 1.0
6257  *
6258  * Content-Type: text/plain; charset=UTF-8
6259  *
6260  * Content-Transfer-Encoding: 8bit
6261  *
6262  * Field Access Macros:
6263  *
6264  */
6265 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL register field. */
6266 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL_LSB 3
6267 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL register field. */
6268 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL_MSB 7
6269 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL register field. */
6270 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL_WIDTH 5
6271 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL register field value. */
6272 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL_SET_MSK 0x000000f8
6273 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL register field value. */
6274 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL_CLR_MSK 0xffffff07
6275 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL register field. */
6276 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL_RESET 0xc
6277 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL field value from a register. */
6278 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL_GET(value) (((value) & 0x000000f8) >> 3)
6279 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL register field value suitable for setting the register. */
6280 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL_SET(value) (((value) << 3) & 0x000000f8)
6281 
6282 /*
6283  * Field : RRDL
6284  *
6285  * Project-Id-Version: 2.11.4
6286  *
6287  * Report-Msgid-Bugs-To:
6288  *
6289  * POT-Creation-Date: 2015-03-03 12:49+CET
6290  *
6291  * PO-Revision-Date: 2009-01-19 17:46+0100
6292  *
6293  * Last-Translator: ARTERIS <twt@arteris.com>
6294  *
6295  * Language-Team: en_US <twt@arteris.com>
6296  *
6297  * MIME-Version: 1.0
6298  *
6299  * Content-Type: text/plain; charset=UTF-8
6300  *
6301  * Content-Transfer-Encoding: 8bit
6302  *
6303  * Field Access Macros:
6304  *
6305  */
6306 /* The Least Significant Bit (LSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL register field. */
6307 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL_LSB 8
6308 /* The Most Significant Bit (MSB) position of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL register field. */
6309 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL_MSB 11
6310 /* The width in bits of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL register field. */
6311 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL_WIDTH 4
6312 /* The mask used to set the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL register field value. */
6313 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL_SET_MSK 0x00000f00
6314 /* The mask used to clear the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL register field value. */
6315 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL_CLR_MSK 0xfffff0ff
6316 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL register field. */
6317 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL_RESET 0x3
6318 /* Extracts the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL field value from a register. */
6319 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL_GET(value) (((value) & 0x00000f00) >> 8)
6320 /* Produces a ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL register field value suitable for setting the register. */
6321 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL_SET(value) (((value) << 8) & 0x00000f00)
6322 
6323 #ifndef __ASSEMBLY__
6324 /*
6325  * WARNING: The C register and register group struct declarations are provided for
6326  * convenience and illustrative purposes. They should, however, be used with
6327  * caution as the C language standard provides no guarantees about the alignment or
6328  * atomicity of device memory accesses. The recommended practice for coding device
6329  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6330  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6331  * alt_write_dword() functions for 64 bit registers.
6332  *
6333  * The struct declaration for register ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING.
6334  */
6335 struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_s
6336 {
6337  volatile uint32_t CCDL : 3; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL */
6338  volatile uint32_t WRTORDL : 5; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL */
6339  volatile uint32_t RRDL : 4; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL */
6340  uint32_t : 20; /* *UNDEFINED* */
6341 };
6342 
6343 /* The typedef declaration for register ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING. */
6344 typedef struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_s ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_t;
6345 #endif /* __ASSEMBLY__ */
6346 
6347 /* The reset value of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING register. */
6348 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RESET 0x00000367
6349 /* The byte offset of the ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING register from the beginning of the component. */
6350 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_OFST 0x40
6351 
6352 #ifndef __ASSEMBLY__
6353 /*
6354  * WARNING: The C register and register group struct declarations are provided for
6355  * convenience and illustrative purposes. They should, however, be used with
6356  * caution as the C language standard provides no guarantees about the alignment or
6357  * atomicity of device memory accesses. The recommended practice for coding device
6358  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6359  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6360  * alt_write_dword() functions for 64 bit registers.
6361  *
6362  * The struct declaration for register group ALT_MPFE_DDR_MAIN_SCHED.
6363  */
6364 struct ALT_MPFE_DDR_MAIN_SCHED_s
6365 {
6366  volatile ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_t ddr_T_main_Scheduler_Id_CoreId; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID */
6367  volatile ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_t ddr_T_main_Scheduler_Id_RevisionId; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID */
6368  volatile ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_t ddr_T_main_Scheduler_DdrConf; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF */
6369  volatile ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_t ddr_T_main_Scheduler_DdrTiming; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING */
6370  volatile ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_t ddr_T_main_Scheduler_DdrMode; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE */
6371  volatile ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_t ddr_T_main_Scheduler_ReadLatency; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY */
6372  volatile uint32_t _pad_0x18_0x37[8]; /* *UNDEFINED* */
6373  volatile ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_t ddr_T_main_Scheduler_Activate; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE */
6374  volatile ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_t ddr_T_main_Scheduler_DevToDev; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV */
6375  volatile ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_t ddr_T_main_Scheduler_Ddr4Timing; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING */
6376  volatile uint32_t _pad_0x44_0x80[15]; /* *UNDEFINED* */
6377 };
6378 
6379 /* The typedef declaration for register group ALT_MPFE_DDR_MAIN_SCHED. */
6380 typedef struct ALT_MPFE_DDR_MAIN_SCHED_s ALT_MPFE_DDR_MAIN_SCHED_t;
6381 /* The struct declaration for the raw register contents of register group ALT_MPFE_DDR_MAIN_SCHED. */
6382 struct ALT_MPFE_DDR_MAIN_SCHED_raw_s
6383 {
6384  volatile uint32_t ddr_T_main_Scheduler_Id_CoreId; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID */
6385  volatile uint32_t ddr_T_main_Scheduler_Id_RevisionId; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID */
6386  volatile uint32_t ddr_T_main_Scheduler_DdrConf; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF */
6387  volatile uint32_t ddr_T_main_Scheduler_DdrTiming; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING */
6388  volatile uint32_t ddr_T_main_Scheduler_DdrMode; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE */
6389  volatile uint32_t ddr_T_main_Scheduler_ReadLatency; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY */
6390  volatile uint32_t _pad_0x18_0x37[8]; /* *UNDEFINED* */
6391  volatile uint32_t ddr_T_main_Scheduler_Activate; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE */
6392  volatile uint32_t ddr_T_main_Scheduler_DevToDev; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV */
6393  volatile uint32_t ddr_T_main_Scheduler_Ddr4Timing; /* ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING */
6394  volatile uint32_t _pad_0x44_0x80[15]; /* *UNDEFINED* */
6395 };
6396 
6397 /* The typedef declaration for the raw register contents of register group ALT_MPFE_DDR_MAIN_SCHED. */
6398 typedef struct ALT_MPFE_DDR_MAIN_SCHED_raw_s ALT_MPFE_DDR_MAIN_SCHED_raw_t;
6399 #endif /* __ASSEMBLY__ */
6400 
6401 
6402 /*
6403  * Component : MPFE_IOHMC
6404  * iohmc_ctrl_mmr_top_inst.register_control
6405  *
6406  */
6407 /*
6408  * Register : reg_dbgcfg0
6409  *
6410  * Register Layout
6411  *
6412  * Bits | Access | Reset | Description
6413  * :-------|:-------|:--------|:--------------------------------------------------
6414  * [0] | RW | Unknown | ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL
6415  * [1] | RW | Unknown | ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL
6416  * [2] | RW | Unknown | ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N
6417  * [3] | RW | Unknown | ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN
6418  * [4] | RW | Unknown | ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL
6419  * [8:5] | RW | Unknown | ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE
6420  * [31:9] | ??? | Unknown | *UNDEFINED*
6421  *
6422  */
6423 /*
6424  * Field : cfg_wdata_driver_sel
6425  *
6426  * iohmc_ctrl_mmr_top_inst.cfg_wdata_driver_sel
6427  *
6428  * Name:Wr Data Driver Select
6429  *
6430  * Description:1’b0 – write data from core, 1’b1 – write data from PRBS
6431  *
6432  * Field Access Macros:
6433  *
6434  */
6435 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL register field. */
6436 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL_LSB 0
6437 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL register field. */
6438 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL_MSB 0
6439 /* The width in bits of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL register field. */
6440 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL_WIDTH 1
6441 /* The mask used to set the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL register field value. */
6442 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL_SET_MSK 0x00000001
6443 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL register field value. */
6444 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL_CLR_MSK 0xfffffffe
6445 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL register field is UNKNOWN. */
6446 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL_RESET 0x0
6447 /* Extracts the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL field value from a register. */
6448 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL_GET(value) (((value) & 0x00000001) >> 0)
6449 /* Produces a ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL register field value suitable for setting the register. */
6450 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL_SET(value) (((value) << 0) & 0x00000001)
6451 
6452 /*
6453  * Field : cfg_prbs_ctrl_sel
6454  *
6455  * iohmc_ctrl_mmr_top_inst.cfg_prbs_ctrl_sel
6456  *
6457  * Name:PRBS Control Select
6458  *
6459  * Description:1’b0 – PRBS controlled by HMC, 1’b1 – PRBS controlled by
6460  * sequencer
6461  *
6462  * Field Access Macros:
6463  *
6464  */
6465 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL register field. */
6466 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL_LSB 1
6467 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL register field. */
6468 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL_MSB 1
6469 /* The width in bits of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL register field. */
6470 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL_WIDTH 1
6471 /* The mask used to set the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL register field value. */
6472 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL_SET_MSK 0x00000002
6473 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL register field value. */
6474 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL_CLR_MSK 0xfffffffd
6475 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL register field is UNKNOWN. */
6476 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL_RESET 0x0
6477 /* Extracts the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL field value from a register. */
6478 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL_GET(value) (((value) & 0x00000002) >> 1)
6479 /* Produces a ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL register field value suitable for setting the register. */
6480 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL_SET(value) (((value) << 1) & 0x00000002)
6481 
6482 /*
6483  * Field : cfg_cb_seq_en_fix_en_n
6484  *
6485  * iohmc_ctrl_mmr_top_inst.cfg_cb_seq_en_fix_en_n
6486  *
6487  * Name:Sequencer enable fix
6488  *
6489  * Description:Chicken Bit for DBC Fix (DQS Tracking) in Sequencer Enable mode:
6490  * 1’b0 – Fix Enabled, 1’b1 – Fix Disabled
6491  *
6492  * Field Access Macros:
6493  *
6494  */
6495 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N register field. */
6496 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N_LSB 2
6497 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N register field. */
6498 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N_MSB 2
6499 /* The width in bits of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N register field. */
6500 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N_WIDTH 1
6501 /* The mask used to set the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N register field value. */
6502 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N_SET_MSK 0x00000004
6503 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N register field value. */
6504 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N_CLR_MSK 0xfffffffb
6505 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N register field is UNKNOWN. */
6506 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N_RESET 0x0
6507 /* Extracts the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N field value from a register. */
6508 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N_GET(value) (((value) & 0x00000004) >> 2)
6509 /* Produces a ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N register field value suitable for setting the register. */
6510 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N_SET(value) (((value) << 2) & 0x00000004)
6511 
6512 /*
6513  * Field : cfg_loopback_en
6514  *
6515  * iohmc_ctrl_mmr_top_inst.cfg_loopback_en
6516  *
6517  * Name:Loopback Mode Enable
6518  *
6519  * Description:1’b0 – Disable the loopback mode, 1’b1 – Enable the loopback
6520  * mode for testing
6521  *
6522  * Field Access Macros:
6523  *
6524  */
6525 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN register field. */
6526 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN_LSB 3
6527 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN register field. */
6528 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN_MSB 3
6529 /* The width in bits of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN register field. */
6530 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN_WIDTH 1
6531 /* The mask used to set the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN register field value. */
6532 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN_SET_MSK 0x00000008
6533 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN register field value. */
6534 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN_CLR_MSK 0xfffffff7
6535 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN register field is UNKNOWN. */
6536 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN_RESET 0x0
6537 /* Extracts the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN field value from a register. */
6538 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN_GET(value) (((value) & 0x00000008) >> 3)
6539 /* Produces a ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN register field value suitable for setting the register. */
6540 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN_SET(value) (((value) << 3) & 0x00000008)
6541 
6542 /*
6543  * Field : cfg_cmd_driver_sel
6544  *
6545  * iohmc_ctrl_mmr_top_inst.cfg_cmd_driver_sel
6546  *
6547  * Name:Cmd Driver Select
6548  *
6549  * Description:1’b0 – cmd interface driven by core, 1’b1 - cmd interface
6550  * driven by MMR
6551  *
6552  * Field Access Macros:
6553  *
6554  */
6555 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL register field. */
6556 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL_LSB 4
6557 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL register field. */
6558 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL_MSB 4
6559 /* The width in bits of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL register field. */
6560 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL_WIDTH 1
6561 /* The mask used to set the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL register field value. */
6562 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL_SET_MSK 0x00000010
6563 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL register field value. */
6564 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL_CLR_MSK 0xffffffef
6565 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL register field is UNKNOWN. */
6566 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL_RESET 0x0
6567 /* Extracts the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL field value from a register. */
6568 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL_GET(value) (((value) & 0x00000010) >> 4)
6569 /* Produces a ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL register field value suitable for setting the register. */
6570 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL_SET(value) (((value) << 4) & 0x00000010)
6571 
6572 /*
6573  * Field : cfg_dbg_mode
6574  *
6575  * iohmc_ctrl_mmr_top_inst.cfg_dbg_mode[3:0]
6576  *
6577  * Name:Debug Mode
6578  *
6579  * Description:4’b0000 – functional mode, TBD
6580  *
6581  * Field Access Macros:
6582  *
6583  */
6584 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE register field. */
6585 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE_LSB 5
6586 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE register field. */
6587 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE_MSB 8
6588 /* The width in bits of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE register field. */
6589 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE_WIDTH 4
6590 /* The mask used to set the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE register field value. */
6591 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE_SET_MSK 0x000001e0
6592 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE register field value. */
6593 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE_CLR_MSK 0xfffffe1f
6594 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE register field is UNKNOWN. */
6595 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE_RESET 0x0
6596 /* Extracts the ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE field value from a register. */
6597 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE_GET(value) (((value) & 0x000001e0) >> 5)
6598 /* Produces a ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE register field value suitable for setting the register. */
6599 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE_SET(value) (((value) << 5) & 0x000001e0)
6600 
6601 #ifndef __ASSEMBLY__
6602 /*
6603  * WARNING: The C register and register group struct declarations are provided for
6604  * convenience and illustrative purposes. They should, however, be used with
6605  * caution as the C language standard provides no guarantees about the alignment or
6606  * atomicity of device memory accesses. The recommended practice for coding device
6607  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6608  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6609  * alt_write_dword() functions for 64 bit registers.
6610  *
6611  * The struct declaration for register ALT_MPFE_IOHMC_REG_DBGCFG0.
6612  */
6613 struct ALT_MPFE_IOHMC_REG_DBGCFG0_s
6614 {
6615  volatile uint32_t cfg_wdata_driver_sel : 1; /* ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL */
6616  volatile uint32_t cfg_prbs_ctrl_sel : 1; /* ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL */
6617  volatile uint32_t cfg_cb_seq_en_fix_en_n : 1; /* ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N */
6618  volatile uint32_t cfg_loopback_en : 1; /* ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN */
6619  volatile uint32_t cfg_cmd_driver_sel : 1; /* ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL */
6620  volatile uint32_t cfg_dbg_mode : 4; /* ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE */
6621  uint32_t : 23; /* *UNDEFINED* */
6622 };
6623 
6624 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_DBGCFG0. */
6625 typedef struct ALT_MPFE_IOHMC_REG_DBGCFG0_s ALT_MPFE_IOHMC_REG_DBGCFG0_t;
6626 #endif /* __ASSEMBLY__ */
6627 
6628 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGCFG0 register. */
6629 #define ALT_MPFE_IOHMC_REG_DBGCFG0_RESET 0x00000000
6630 /* The byte offset of the ALT_MPFE_IOHMC_REG_DBGCFG0 register from the beginning of the component. */
6631 #define ALT_MPFE_IOHMC_REG_DBGCFG0_OFST 0x0
6632 
6633 /*
6634  * Register : reg_dbgcfg1
6635  *
6636  * Register Layout
6637  *
6638  * Bits | Access | Reset | Description
6639  * :-------|:-------|:--------|:----------------------------------------
6640  * [31:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL
6641  *
6642  */
6643 /*
6644  * Field : cfg_dbg_ctrl
6645  *
6646  * iohmc_ctrl_mmr_top_inst.cfg_dbg_ctrl[31:0]
6647  *
6648  * Name:Debug Control
6649  *
6650  * Description:TBD
6651  *
6652  * Field Access Macros:
6653  *
6654  */
6655 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL register field. */
6656 #define ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL_LSB 0
6657 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL register field. */
6658 #define ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL_MSB 31
6659 /* The width in bits of the ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL register field. */
6660 #define ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL_WIDTH 32
6661 /* The mask used to set the ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL register field value. */
6662 #define ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL_SET_MSK 0xffffffff
6663 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL register field value. */
6664 #define ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL_CLR_MSK 0x00000000
6665 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL register field is UNKNOWN. */
6666 #define ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL_RESET 0x0
6667 /* Extracts the ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL field value from a register. */
6668 #define ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL_GET(value) (((value) & 0xffffffff) >> 0)
6669 /* Produces a ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL register field value suitable for setting the register. */
6670 #define ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL_SET(value) (((value) << 0) & 0xffffffff)
6671 
6672 #ifndef __ASSEMBLY__
6673 /*
6674  * WARNING: The C register and register group struct declarations are provided for
6675  * convenience and illustrative purposes. They should, however, be used with
6676  * caution as the C language standard provides no guarantees about the alignment or
6677  * atomicity of device memory accesses. The recommended practice for coding device
6678  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6679  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6680  * alt_write_dword() functions for 64 bit registers.
6681  *
6682  * The struct declaration for register ALT_MPFE_IOHMC_REG_DBGCFG1.
6683  */
6684 struct ALT_MPFE_IOHMC_REG_DBGCFG1_s
6685 {
6686  volatile uint32_t cfg_dbg_ctrl : 32; /* ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL */
6687 };
6688 
6689 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_DBGCFG1. */
6690 typedef struct ALT_MPFE_IOHMC_REG_DBGCFG1_s ALT_MPFE_IOHMC_REG_DBGCFG1_t;
6691 #endif /* __ASSEMBLY__ */
6692 
6693 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGCFG1 register. */
6694 #define ALT_MPFE_IOHMC_REG_DBGCFG1_RESET 0x00000000
6695 /* The byte offset of the ALT_MPFE_IOHMC_REG_DBGCFG1 register from the beginning of the component. */
6696 #define ALT_MPFE_IOHMC_REG_DBGCFG1_OFST 0x4
6697 
6698 /*
6699  * Register : reg_dbgcfg2
6700  *
6701  * Register Layout
6702  *
6703  * Bits | Access | Reset | Description
6704  * :-------|:-------|:--------|:-------------------------------------------
6705  * [31:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U
6706  *
6707  */
6708 /*
6709  * Field : cfg_bist_cmd0_u
6710  *
6711  * iohmc_ctrl_mmr_top_inst.cfg_bist_cmd0_u[31:0]
6712  *
6713  * Name:BIST mode cmd0 upper bits
6714  *
6715  * Description:TBD
6716  *
6717  * Field Access Macros:
6718  *
6719  */
6720 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U register field. */
6721 #define ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U_LSB 0
6722 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U register field. */
6723 #define ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U_MSB 31
6724 /* The width in bits of the ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U register field. */
6725 #define ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U_WIDTH 32
6726 /* The mask used to set the ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U register field value. */
6727 #define ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U_SET_MSK 0xffffffff
6728 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U register field value. */
6729 #define ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U_CLR_MSK 0x00000000
6730 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U register field is UNKNOWN. */
6731 #define ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U_RESET 0x0
6732 /* Extracts the ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U field value from a register. */
6733 #define ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U_GET(value) (((value) & 0xffffffff) >> 0)
6734 /* Produces a ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U register field value suitable for setting the register. */
6735 #define ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U_SET(value) (((value) << 0) & 0xffffffff)
6736 
6737 #ifndef __ASSEMBLY__
6738 /*
6739  * WARNING: The C register and register group struct declarations are provided for
6740  * convenience and illustrative purposes. They should, however, be used with
6741  * caution as the C language standard provides no guarantees about the alignment or
6742  * atomicity of device memory accesses. The recommended practice for coding device
6743  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6744  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6745  * alt_write_dword() functions for 64 bit registers.
6746  *
6747  * The struct declaration for register ALT_MPFE_IOHMC_REG_DBGCFG2.
6748  */
6749 struct ALT_MPFE_IOHMC_REG_DBGCFG2_s
6750 {
6751  volatile uint32_t cfg_bist_cmd0_u : 32; /* ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U */
6752 };
6753 
6754 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_DBGCFG2. */
6755 typedef struct ALT_MPFE_IOHMC_REG_DBGCFG2_s ALT_MPFE_IOHMC_REG_DBGCFG2_t;
6756 #endif /* __ASSEMBLY__ */
6757 
6758 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGCFG2 register. */
6759 #define ALT_MPFE_IOHMC_REG_DBGCFG2_RESET 0x00000000
6760 /* The byte offset of the ALT_MPFE_IOHMC_REG_DBGCFG2 register from the beginning of the component. */
6761 #define ALT_MPFE_IOHMC_REG_DBGCFG2_OFST 0x8
6762 
6763 /*
6764  * Register : reg_dbgcfg3
6765  *
6766  * Register Layout
6767  *
6768  * Bits | Access | Reset | Description
6769  * :-------|:-------|:--------|:-------------------------------------------
6770  * [31:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L
6771  *
6772  */
6773 /*
6774  * Field : cfg_bist_cmd0_l
6775  *
6776  * iohmc_ctrl_mmr_top_inst.cfg_bist_cmd0_l[31:0]
6777  *
6778  * Name:BIST mode cmd0 lower bits
6779  *
6780  * Description:TBD
6781  *
6782  * Field Access Macros:
6783  *
6784  */
6785 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L register field. */
6786 #define ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L_LSB 0
6787 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L register field. */
6788 #define ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L_MSB 31
6789 /* The width in bits of the ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L register field. */
6790 #define ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L_WIDTH 32
6791 /* The mask used to set the ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L register field value. */
6792 #define ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L_SET_MSK 0xffffffff
6793 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L register field value. */
6794 #define ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L_CLR_MSK 0x00000000
6795 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L register field is UNKNOWN. */
6796 #define ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L_RESET 0x0
6797 /* Extracts the ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L field value from a register. */
6798 #define ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L_GET(value) (((value) & 0xffffffff) >> 0)
6799 /* Produces a ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L register field value suitable for setting the register. */
6800 #define ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L_SET(value) (((value) << 0) & 0xffffffff)
6801 
6802 #ifndef __ASSEMBLY__
6803 /*
6804  * WARNING: The C register and register group struct declarations are provided for
6805  * convenience and illustrative purposes. They should, however, be used with
6806  * caution as the C language standard provides no guarantees about the alignment or
6807  * atomicity of device memory accesses. The recommended practice for coding device
6808  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6809  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6810  * alt_write_dword() functions for 64 bit registers.
6811  *
6812  * The struct declaration for register ALT_MPFE_IOHMC_REG_DBGCFG3.
6813  */
6814 struct ALT_MPFE_IOHMC_REG_DBGCFG3_s
6815 {
6816  volatile uint32_t cfg_bist_cmd0_l : 32; /* ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L */
6817 };
6818 
6819 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_DBGCFG3. */
6820 typedef struct ALT_MPFE_IOHMC_REG_DBGCFG3_s ALT_MPFE_IOHMC_REG_DBGCFG3_t;
6821 #endif /* __ASSEMBLY__ */
6822 
6823 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGCFG3 register. */
6824 #define ALT_MPFE_IOHMC_REG_DBGCFG3_RESET 0x00000000
6825 /* The byte offset of the ALT_MPFE_IOHMC_REG_DBGCFG3 register from the beginning of the component. */
6826 #define ALT_MPFE_IOHMC_REG_DBGCFG3_OFST 0xc
6827 
6828 /*
6829  * Register : reg_dbgcfg4
6830  *
6831  * Register Layout
6832  *
6833  * Bits | Access | Reset | Description
6834  * :-------|:-------|:--------|:-------------------------------------------
6835  * [31:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U
6836  *
6837  */
6838 /*
6839  * Field : cfg_bist_cmd1_u
6840  *
6841  * iohmc_ctrl_mmr_top_inst.cfg_bist_cmd1_u[31:0]
6842  *
6843  * Name:BIST mode cmd1 upper bits
6844  *
6845  * Description:TBD
6846  *
6847  * Field Access Macros:
6848  *
6849  */
6850 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U register field. */
6851 #define ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U_LSB 0
6852 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U register field. */
6853 #define ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U_MSB 31
6854 /* The width in bits of the ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U register field. */
6855 #define ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U_WIDTH 32
6856 /* The mask used to set the ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U register field value. */
6857 #define ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U_SET_MSK 0xffffffff
6858 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U register field value. */
6859 #define ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U_CLR_MSK 0x00000000
6860 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U register field is UNKNOWN. */
6861 #define ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U_RESET 0x0
6862 /* Extracts the ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U field value from a register. */
6863 #define ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U_GET(value) (((value) & 0xffffffff) >> 0)
6864 /* Produces a ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U register field value suitable for setting the register. */
6865 #define ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U_SET(value) (((value) << 0) & 0xffffffff)
6866 
6867 #ifndef __ASSEMBLY__
6868 /*
6869  * WARNING: The C register and register group struct declarations are provided for
6870  * convenience and illustrative purposes. They should, however, be used with
6871  * caution as the C language standard provides no guarantees about the alignment or
6872  * atomicity of device memory accesses. The recommended practice for coding device
6873  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6874  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6875  * alt_write_dword() functions for 64 bit registers.
6876  *
6877  * The struct declaration for register ALT_MPFE_IOHMC_REG_DBGCFG4.
6878  */
6879 struct ALT_MPFE_IOHMC_REG_DBGCFG4_s
6880 {
6881  volatile uint32_t cfg_bist_cmd1_u : 32; /* ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U */
6882 };
6883 
6884 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_DBGCFG4. */
6885 typedef struct ALT_MPFE_IOHMC_REG_DBGCFG4_s ALT_MPFE_IOHMC_REG_DBGCFG4_t;
6886 #endif /* __ASSEMBLY__ */
6887 
6888 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGCFG4 register. */
6889 #define ALT_MPFE_IOHMC_REG_DBGCFG4_RESET 0x00000000
6890 /* The byte offset of the ALT_MPFE_IOHMC_REG_DBGCFG4 register from the beginning of the component. */
6891 #define ALT_MPFE_IOHMC_REG_DBGCFG4_OFST 0x10
6892 
6893 /*
6894  * Register : reg_dbgcfg5
6895  *
6896  * Register Layout
6897  *
6898  * Bits | Access | Reset | Description
6899  * :-------|:-------|:--------|:-------------------------------------------
6900  * [31:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L
6901  *
6902  */
6903 /*
6904  * Field : cfg_bist_cmd1_l
6905  *
6906  * iohmc_ctrl_mmr_top_inst.cfg_bist_cmd1_l[31:0]
6907  *
6908  * Name:BIST mode cmd1 lower bits
6909  *
6910  * Description:TBD
6911  *
6912  * Field Access Macros:
6913  *
6914  */
6915 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L register field. */
6916 #define ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L_LSB 0
6917 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L register field. */
6918 #define ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L_MSB 31
6919 /* The width in bits of the ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L register field. */
6920 #define ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L_WIDTH 32
6921 /* The mask used to set the ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L register field value. */
6922 #define ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L_SET_MSK 0xffffffff
6923 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L register field value. */
6924 #define ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L_CLR_MSK 0x00000000
6925 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L register field is UNKNOWN. */
6926 #define ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L_RESET 0x0
6927 /* Extracts the ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L field value from a register. */
6928 #define ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L_GET(value) (((value) & 0xffffffff) >> 0)
6929 /* Produces a ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L register field value suitable for setting the register. */
6930 #define ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L_SET(value) (((value) << 0) & 0xffffffff)
6931 
6932 #ifndef __ASSEMBLY__
6933 /*
6934  * WARNING: The C register and register group struct declarations are provided for
6935  * convenience and illustrative purposes. They should, however, be used with
6936  * caution as the C language standard provides no guarantees about the alignment or
6937  * atomicity of device memory accesses. The recommended practice for coding device
6938  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6939  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6940  * alt_write_dword() functions for 64 bit registers.
6941  *
6942  * The struct declaration for register ALT_MPFE_IOHMC_REG_DBGCFG5.
6943  */
6944 struct ALT_MPFE_IOHMC_REG_DBGCFG5_s
6945 {
6946  volatile uint32_t cfg_bist_cmd1_l : 32; /* ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L */
6947 };
6948 
6949 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_DBGCFG5. */
6950 typedef struct ALT_MPFE_IOHMC_REG_DBGCFG5_s ALT_MPFE_IOHMC_REG_DBGCFG5_t;
6951 #endif /* __ASSEMBLY__ */
6952 
6953 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGCFG5 register. */
6954 #define ALT_MPFE_IOHMC_REG_DBGCFG5_RESET 0x00000000
6955 /* The byte offset of the ALT_MPFE_IOHMC_REG_DBGCFG5 register from the beginning of the component. */
6956 #define ALT_MPFE_IOHMC_REG_DBGCFG5_OFST 0x14
6957 
6958 /*
6959  * Register : reg_dbgcfg6
6960  *
6961  * Register Layout
6962  *
6963  * Bits | Access | Reset | Description
6964  * :--------|:-------|:--------|:-------------------------------------------
6965  * [15:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL
6966  * [31:16] | ??? | Unknown | *UNDEFINED*
6967  *
6968  */
6969 /*
6970  * Field : cfg_dbg_out_sel
6971  *
6972  * iohmc_ctrl_mmr_top_inst.cfg_dbg_out_sel[15:0]
6973  *
6974  * Name:Debug Signal Output Select
6975  *
6976  * Description:Select which debug signals sent out for observation
6977  *
6978  * Field Access Macros:
6979  *
6980  */
6981 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL register field. */
6982 #define ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL_LSB 0
6983 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL register field. */
6984 #define ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL_MSB 15
6985 /* The width in bits of the ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL register field. */
6986 #define ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL_WIDTH 16
6987 /* The mask used to set the ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL register field value. */
6988 #define ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL_SET_MSK 0x0000ffff
6989 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL register field value. */
6990 #define ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL_CLR_MSK 0xffff0000
6991 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL register field is UNKNOWN. */
6992 #define ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL_RESET 0x0
6993 /* Extracts the ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL field value from a register. */
6994 #define ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL_GET(value) (((value) & 0x0000ffff) >> 0)
6995 /* Produces a ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL register field value suitable for setting the register. */
6996 #define ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL_SET(value) (((value) << 0) & 0x0000ffff)
6997 
6998 #ifndef __ASSEMBLY__
6999 /*
7000  * WARNING: The C register and register group struct declarations are provided for
7001  * convenience and illustrative purposes. They should, however, be used with
7002  * caution as the C language standard provides no guarantees about the alignment or
7003  * atomicity of device memory accesses. The recommended practice for coding device
7004  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7005  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7006  * alt_write_dword() functions for 64 bit registers.
7007  *
7008  * The struct declaration for register ALT_MPFE_IOHMC_REG_DBGCFG6.
7009  */
7010 struct ALT_MPFE_IOHMC_REG_DBGCFG6_s
7011 {
7012  volatile uint32_t cfg_dbg_out_sel : 16; /* ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL */
7013  uint32_t : 16; /* *UNDEFINED* */
7014 };
7015 
7016 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_DBGCFG6. */
7017 typedef struct ALT_MPFE_IOHMC_REG_DBGCFG6_s ALT_MPFE_IOHMC_REG_DBGCFG6_t;
7018 #endif /* __ASSEMBLY__ */
7019 
7020 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGCFG6 register. */
7021 #define ALT_MPFE_IOHMC_REG_DBGCFG6_RESET 0x00000000
7022 /* The byte offset of the ALT_MPFE_IOHMC_REG_DBGCFG6 register from the beginning of the component. */
7023 #define ALT_MPFE_IOHMC_REG_DBGCFG6_OFST 0x18
7024 
7025 /*
7026  * Register : reg_reserve0
7027  *
7028  * Register Layout
7029  *
7030  * Bits | Access | Reset | Description
7031  * :--------|:-------|:--------|:-----------------------------------------
7032  * [15:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0
7033  * [31:16] | ??? | Unknown | *UNDEFINED*
7034  *
7035  */
7036 /*
7037  * Field : cfg_reserve0
7038  *
7039  * iohmc_ctrl_mmr_top_inst.cfg_reserve0[15:0]
7040  *
7041  * Name:Reserve0
7042  *
7043  * Description:General purpose reserve register
7044  *
7045  * Field Access Macros:
7046  *
7047  */
7048 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0 register field. */
7049 #define ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0_LSB 0
7050 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0 register field. */
7051 #define ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0_MSB 15
7052 /* The width in bits of the ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0 register field. */
7053 #define ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0_WIDTH 16
7054 /* The mask used to set the ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0 register field value. */
7055 #define ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0_SET_MSK 0x0000ffff
7056 /* The mask used to clear the ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0 register field value. */
7057 #define ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0_CLR_MSK 0xffff0000
7058 /* The reset value of the ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0 register field is UNKNOWN. */
7059 #define ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0_RESET 0x0
7060 /* Extracts the ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0 field value from a register. */
7061 #define ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0_GET(value) (((value) & 0x0000ffff) >> 0)
7062 /* Produces a ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0 register field value suitable for setting the register. */
7063 #define ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0_SET(value) (((value) << 0) & 0x0000ffff)
7064 
7065 #ifndef __ASSEMBLY__
7066 /*
7067  * WARNING: The C register and register group struct declarations are provided for
7068  * convenience and illustrative purposes. They should, however, be used with
7069  * caution as the C language standard provides no guarantees about the alignment or
7070  * atomicity of device memory accesses. The recommended practice for coding device
7071  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7072  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7073  * alt_write_dword() functions for 64 bit registers.
7074  *
7075  * The struct declaration for register ALT_MPFE_IOHMC_REG_RESERVE0.
7076  */
7077 struct ALT_MPFE_IOHMC_REG_RESERVE0_s
7078 {
7079  volatile uint32_t cfg_reserve0 : 16; /* ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0 */
7080  uint32_t : 16; /* *UNDEFINED* */
7081 };
7082 
7083 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_RESERVE0. */
7084 typedef struct ALT_MPFE_IOHMC_REG_RESERVE0_s ALT_MPFE_IOHMC_REG_RESERVE0_t;
7085 #endif /* __ASSEMBLY__ */
7086 
7087 /* The reset value of the ALT_MPFE_IOHMC_REG_RESERVE0 register. */
7088 #define ALT_MPFE_IOHMC_REG_RESERVE0_RESET 0x00000000
7089 /* The byte offset of the ALT_MPFE_IOHMC_REG_RESERVE0 register from the beginning of the component. */
7090 #define ALT_MPFE_IOHMC_REG_RESERVE0_OFST 0x1c
7091 
7092 /*
7093  * Register : reg_reserve1
7094  *
7095  * Register Layout
7096  *
7097  * Bits | Access | Reset | Description
7098  * :--------|:-------|:--------|:-----------------------------------------
7099  * [15:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1
7100  * [31:16] | ??? | Unknown | *UNDEFINED*
7101  *
7102  */
7103 /*
7104  * Field : cfg_reserve1
7105  *
7106  * iohmc_ctrl_mmr_top_inst.cfg_reserve1[15:0]
7107  *
7108  * Name:Reserve1
7109  *
7110  * Description:General purpose reserve register
7111  *
7112  * Field Access Macros:
7113  *
7114  */
7115 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1 register field. */
7116 #define ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1_LSB 0
7117 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1 register field. */
7118 #define ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1_MSB 15
7119 /* The width in bits of the ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1 register field. */
7120 #define ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1_WIDTH 16
7121 /* The mask used to set the ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1 register field value. */
7122 #define ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1_SET_MSK 0x0000ffff
7123 /* The mask used to clear the ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1 register field value. */
7124 #define ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1_CLR_MSK 0xffff0000
7125 /* The reset value of the ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1 register field is UNKNOWN. */
7126 #define ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1_RESET 0x0
7127 /* Extracts the ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1 field value from a register. */
7128 #define ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1_GET(value) (((value) & 0x0000ffff) >> 0)
7129 /* Produces a ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1 register field value suitable for setting the register. */
7130 #define ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1_SET(value) (((value) << 0) & 0x0000ffff)
7131 
7132 #ifndef __ASSEMBLY__
7133 /*
7134  * WARNING: The C register and register group struct declarations are provided for
7135  * convenience and illustrative purposes. They should, however, be used with
7136  * caution as the C language standard provides no guarantees about the alignment or
7137  * atomicity of device memory accesses. The recommended practice for coding device
7138  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7139  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7140  * alt_write_dword() functions for 64 bit registers.
7141  *
7142  * The struct declaration for register ALT_MPFE_IOHMC_REG_RESERVE1.
7143  */
7144 struct ALT_MPFE_IOHMC_REG_RESERVE1_s
7145 {
7146  volatile uint32_t cfg_reserve1 : 16; /* ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1 */
7147  uint32_t : 16; /* *UNDEFINED* */
7148 };
7149 
7150 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_RESERVE1. */
7151 typedef struct ALT_MPFE_IOHMC_REG_RESERVE1_s ALT_MPFE_IOHMC_REG_RESERVE1_t;
7152 #endif /* __ASSEMBLY__ */
7153 
7154 /* The reset value of the ALT_MPFE_IOHMC_REG_RESERVE1 register. */
7155 #define ALT_MPFE_IOHMC_REG_RESERVE1_RESET 0x00000000
7156 /* The byte offset of the ALT_MPFE_IOHMC_REG_RESERVE1 register from the beginning of the component. */
7157 #define ALT_MPFE_IOHMC_REG_RESERVE1_OFST 0x20
7158 
7159 /*
7160  * Register : reg_reserve2
7161  *
7162  * Register Layout
7163  *
7164  * Bits | Access | Reset | Description
7165  * :--------|:-------|:--------|:-----------------------------------------
7166  * [15:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2
7167  * [31:16] | ??? | Unknown | *UNDEFINED*
7168  *
7169  */
7170 /*
7171  * Field : cfg_reserve2
7172  *
7173  * iohmc_ctrl_mmr_top_inst.cfg_reserve2[15:0]
7174  *
7175  * Name:Reserve2
7176  *
7177  * Description:General purpose reserve register
7178  *
7179  * Field Access Macros:
7180  *
7181  */
7182 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2 register field. */
7183 #define ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2_LSB 0
7184 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2 register field. */
7185 #define ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2_MSB 15
7186 /* The width in bits of the ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2 register field. */
7187 #define ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2_WIDTH 16
7188 /* The mask used to set the ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2 register field value. */
7189 #define ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2_SET_MSK 0x0000ffff
7190 /* The mask used to clear the ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2 register field value. */
7191 #define ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2_CLR_MSK 0xffff0000
7192 /* The reset value of the ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2 register field is UNKNOWN. */
7193 #define ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2_RESET 0x0
7194 /* Extracts the ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2 field value from a register. */
7195 #define ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2_GET(value) (((value) & 0x0000ffff) >> 0)
7196 /* Produces a ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2 register field value suitable for setting the register. */
7197 #define ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2_SET(value) (((value) << 0) & 0x0000ffff)
7198 
7199 #ifndef __ASSEMBLY__
7200 /*
7201  * WARNING: The C register and register group struct declarations are provided for
7202  * convenience and illustrative purposes. They should, however, be used with
7203  * caution as the C language standard provides no guarantees about the alignment or
7204  * atomicity of device memory accesses. The recommended practice for coding device
7205  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7206  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7207  * alt_write_dword() functions for 64 bit registers.
7208  *
7209  * The struct declaration for register ALT_MPFE_IOHMC_REG_RESERVE2.
7210  */
7211 struct ALT_MPFE_IOHMC_REG_RESERVE2_s
7212 {
7213  volatile uint32_t cfg_reserve2 : 16; /* ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2 */
7214  uint32_t : 16; /* *UNDEFINED* */
7215 };
7216 
7217 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_RESERVE2. */
7218 typedef struct ALT_MPFE_IOHMC_REG_RESERVE2_s ALT_MPFE_IOHMC_REG_RESERVE2_t;
7219 #endif /* __ASSEMBLY__ */
7220 
7221 /* The reset value of the ALT_MPFE_IOHMC_REG_RESERVE2 register. */
7222 #define ALT_MPFE_IOHMC_REG_RESERVE2_RESET 0x00000000
7223 /* The byte offset of the ALT_MPFE_IOHMC_REG_RESERVE2 register from the beginning of the component. */
7224 #define ALT_MPFE_IOHMC_REG_RESERVE2_OFST 0x24
7225 
7226 /*
7227  * Register : reg_ctrlcfg0
7228  *
7229  * Register Layout
7230  *
7231  * Bits | Access | Reset | Description
7232  * :--------|:-------|:--------|:--------------------------------------------------
7233  * [3:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE
7234  * [6:4] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE
7235  * [8:7] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS
7236  * [13:9] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH
7237  * [18:14] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH
7238  * [23:19] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH
7239  * [28:24] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH
7240  * [31:29] | ??? | Unknown | *UNDEFINED*
7241  *
7242  */
7243 /*
7244  * Field : cfg_mem_type
7245  *
7246  * iohmc_ctrl_mmr_top_inst.cfg_mem_type[3:0]
7247  *
7248  * Name:DRAM Memory Type
7249  *
7250  * Description:Selects memory type. Program this field with one of the following
7251  * binary values, “0000” for DDR3 SDRAM, “0001” for DDR4 SDRAM and
7252  * “0010” for LPDDR3 SDRAM.
7253  *
7254  * Field Access Macros:
7255  *
7256  */
7257 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE register field. */
7258 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE_LSB 0
7259 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE register field. */
7260 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE_MSB 3
7261 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE register field. */
7262 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE_WIDTH 4
7263 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE register field value. */
7264 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE_SET_MSK 0x0000000f
7265 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE register field value. */
7266 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE_CLR_MSK 0xfffffff0
7267 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE register field is UNKNOWN. */
7268 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE_RESET 0x0
7269 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE field value from a register. */
7270 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE_GET(value) (((value) & 0x0000000f) >> 0)
7271 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE register field value suitable for setting the register. */
7272 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE_SET(value) (((value) << 0) & 0x0000000f)
7273 
7274 /*
7275  * Field : cfg_dimm_type
7276  *
7277  * iohmc_ctrl_mmr_top_inst.cfg_dimm_type[2:0]
7278  *
7279  * Name:DIMM Type
7280  *
7281  * Description:Selects dimm type. Program this field with one of the following
7282  * binary values, “3’b000” for Component, “3’b001” for UDIMM,
7283  * “3’b010” for RDIMM, “3’b011” for LRDIMM and “3’b100” for
7284  * SODIMM.
7285  *
7286  * Field Access Macros:
7287  *
7288  */
7289 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE register field. */
7290 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE_LSB 4
7291 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE register field. */
7292 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE_MSB 6
7293 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE register field. */
7294 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE_WIDTH 3
7295 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE register field value. */
7296 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE_SET_MSK 0x00000070
7297 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE register field value. */
7298 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE_CLR_MSK 0xffffff8f
7299 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE register field is UNKNOWN. */
7300 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE_RESET 0x0
7301 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE field value from a register. */
7302 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE_GET(value) (((value) & 0x00000070) >> 4)
7303 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE register field value suitable for setting the register. */
7304 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE_SET(value) (((value) << 4) & 0x00000070)
7305 
7306 /*
7307  * Field : cfg_ac_pos
7308  *
7309  * iohmc_ctrl_mmr_top_inst.cfg_ac_pos[1:0]
7310  *
7311  * Name:A/C pin position
7312  *
7313  * Description:Specify C/A (command/address) pin position. 2’b00 – three lanes
7314  * are used as C/A pins, Lane0, 1 and 2; 2’b01 - three lanes are used as C/A
7315  * pins, Lane1, 2 and 3; 2’b10 - All four lanes are used as C/A pins.
7316  *
7317  * Field Access Macros:
7318  *
7319  */
7320 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS register field. */
7321 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS_LSB 7
7322 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS register field. */
7323 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS_MSB 8
7324 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS register field. */
7325 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS_WIDTH 2
7326 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS register field value. */
7327 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS_SET_MSK 0x00000180
7328 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS register field value. */
7329 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS_CLR_MSK 0xfffffe7f
7330 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS register field is UNKNOWN. */
7331 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS_RESET 0x0
7332 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS field value from a register. */
7333 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS_GET(value) (((value) & 0x00000180) >> 7)
7334 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS register field value suitable for setting the register. */
7335 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS_SET(value) (((value) << 7) & 0x00000180)
7336 
7337 /*
7338  * Field : cfg_ctrl_burst_length
7339  *
7340  * iohmc_ctrl_mmr_top_inst.cfg_ctrl_burst_length[4:0]
7341  *
7342  * Name:Control – DRAM Memory Burst Length
7343  *
7344  * Description:Configures burst length for control path. Legal values are valid
7345  * for JEDEC allowed DRAM values for the DRAM selected in cfg_type. For DDR3, DDR4
7346  * and LPDDR3, this should be programmed with 8 (binary “01000”).
7347  *
7348  * Field Access Macros:
7349  *
7350  */
7351 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH register field. */
7352 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH_LSB 9
7353 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH register field. */
7354 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH_MSB 13
7355 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH register field. */
7356 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH_WIDTH 5
7357 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH register field value. */
7358 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH_SET_MSK 0x00003e00
7359 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH register field value. */
7360 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH_CLR_MSK 0xffffc1ff
7361 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH register field is UNKNOWN. */
7362 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH_RESET 0x0
7363 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH field value from a register. */
7364 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH_GET(value) (((value) & 0x00003e00) >> 9)
7365 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH register field value suitable for setting the register. */
7366 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH_SET(value) (((value) << 9) & 0x00003e00)
7367 
7368 /*
7369  * Field : cfg_dbc0_burst_length
7370  *
7371  * iohmc_ctrl_mmr_top_inst.cfg_dbc0_burst_length[4:0]
7372  *
7373  * Name:DBC0 – DRAM Memory Burst Length
7374  *
7375  * Description:Configures burst length for DBC0. Legal values are valid for JEDEC
7376  * allowed DRAM values for the DRAM selected in cfg_type. For DDR3, DDR4 and
7377  * LPDDR3, this should be programmed with 8 (binary “01000”).
7378  *
7379  * Field Access Macros:
7380  *
7381  */
7382 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH register field. */
7383 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH_LSB 14
7384 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH register field. */
7385 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH_MSB 18
7386 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH register field. */
7387 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH_WIDTH 5
7388 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH register field value. */
7389 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH_SET_MSK 0x0007c000
7390 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH register field value. */
7391 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH_CLR_MSK 0xfff83fff
7392 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH register field is UNKNOWN. */
7393 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH_RESET 0x0
7394 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH field value from a register. */
7395 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH_GET(value) (((value) & 0x0007c000) >> 14)
7396 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH register field value suitable for setting the register. */
7397 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH_SET(value) (((value) << 14) & 0x0007c000)
7398 
7399 /*
7400  * Field : cfg_dbc1_burst_length
7401  *
7402  * iohmc_ctrl_mmr_top_inst.cfg_dbc1_burst_length[4:0]
7403  *
7404  * Name:DBC1 – DRAM Memory Burst Length
7405  *
7406  * Description:Configures burst length for DBC1. Legal values are valid for JEDEC
7407  * allowed DRAM values for the DRAM selected in cfg_type. For DDR3, DDR4 and
7408  * LPDDR3, this should be programmed with 8 (binary “01000”).
7409  *
7410  * Field Access Macros:
7411  *
7412  */
7413 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH register field. */
7414 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH_LSB 19
7415 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH register field. */
7416 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH_MSB 23
7417 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH register field. */
7418 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH_WIDTH 5
7419 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH register field value. */
7420 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH_SET_MSK 0x00f80000
7421 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH register field value. */
7422 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH_CLR_MSK 0xff07ffff
7423 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH register field is UNKNOWN. */
7424 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH_RESET 0x0
7425 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH field value from a register. */
7426 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH_GET(value) (((value) & 0x00f80000) >> 19)
7427 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH register field value suitable for setting the register. */
7428 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH_SET(value) (((value) << 19) & 0x00f80000)
7429 
7430 /*
7431  * Field : cfg_dbc2_burst_length
7432  *
7433  * iohmc_ctrl_mmr_top_inst.cfg_dbc2_burst_length[4:0]
7434  *
7435  * Name:DBC2 – DRAM Memory Burst Length
7436  *
7437  * Description:Configures burst length for DBC2. Legal values are valid for JEDEC
7438  * allowed DRAM values for the DRAM selected in cfg_type. For DDR3, DDR4 and
7439  * LPDDR3, this should be programmed with 8 (binary “01000”).
7440  *
7441  * Field Access Macros:
7442  *
7443  */
7444 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH register field. */
7445 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH_LSB 24
7446 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH register field. */
7447 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH_MSB 28
7448 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH register field. */
7449 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH_WIDTH 5
7450 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH register field value. */
7451 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH_SET_MSK 0x1f000000
7452 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH register field value. */
7453 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH_CLR_MSK 0xe0ffffff
7454 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH register field is UNKNOWN. */
7455 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH_RESET 0x0
7456 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH field value from a register. */
7457 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH_GET(value) (((value) & 0x1f000000) >> 24)
7458 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH register field value suitable for setting the register. */
7459 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH_SET(value) (((value) << 24) & 0x1f000000)
7460 
7461 #ifndef __ASSEMBLY__
7462 /*
7463  * WARNING: The C register and register group struct declarations are provided for
7464  * convenience and illustrative purposes. They should, however, be used with
7465  * caution as the C language standard provides no guarantees about the alignment or
7466  * atomicity of device memory accesses. The recommended practice for coding device
7467  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7468  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7469  * alt_write_dword() functions for 64 bit registers.
7470  *
7471  * The struct declaration for register ALT_MPFE_IOHMC_REG_CTRLCFG0.
7472  */
7473 struct ALT_MPFE_IOHMC_REG_CTRLCFG0_s
7474 {
7475  volatile uint32_t cfg_mem_type : 4; /* ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE */
7476  volatile uint32_t cfg_dimm_type : 3; /* ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE */
7477  volatile uint32_t cfg_ac_pos : 2; /* ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS */
7478  volatile uint32_t cfg_ctrl_burst_length : 5; /* ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH */
7479  volatile uint32_t cfg_dbc0_burst_length : 5; /* ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH */
7480  volatile uint32_t cfg_dbc1_burst_length : 5; /* ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH */
7481  volatile uint32_t cfg_dbc2_burst_length : 5; /* ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH */
7482  uint32_t : 3; /* *UNDEFINED* */
7483 };
7484 
7485 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_CTRLCFG0. */
7486 typedef struct ALT_MPFE_IOHMC_REG_CTRLCFG0_s ALT_MPFE_IOHMC_REG_CTRLCFG0_t;
7487 #endif /* __ASSEMBLY__ */
7488 
7489 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG0 register. */
7490 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_RESET 0x00000000
7491 /* The byte offset of the ALT_MPFE_IOHMC_REG_CTRLCFG0 register from the beginning of the component. */
7492 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_OFST 0x28
7493 
7494 /*
7495  * Register : reg_ctrlcfg1
7496  *
7497  * Register Layout
7498  *
7499  * Bits | Access | Reset | Description
7500  * :--------|:-------|:--------|:---------------------------------------------------
7501  * [4:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH
7502  * [6:5] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER
7503  * [7] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC
7504  * [8] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC
7505  * [9] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC
7506  * [10] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC
7507  * [11] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC
7508  * [12] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA
7509  * [13] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA
7510  * [14] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA
7511  * [15] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA
7512  * [16] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA
7513  * [17] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA
7514  * [18] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ
7515  * [24:19] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT
7516  * [25] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN
7517  * [26] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM
7518  * [27] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM
7519  * [28] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM
7520  * [29] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM
7521  * [30] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM
7522  * [31] | ??? | Unknown | *UNDEFINED*
7523  *
7524  */
7525 /*
7526  * Field : cfg_dbc3_burst_length
7527  *
7528  * iohmc_ctrl_mmr_top_inst.cfg_dbc3_burst_length[4:0]
7529  *
7530  * Name:DBC3 – DRAM Memory Burst Length
7531  *
7532  * Description:Configures burst length for DBC3. Legal values are valid for JEDEC
7533  * allowed DRAM values for the DRAM selected in cfg_type. For DDR3, DDR4 and
7534  * LPDDR3, this should be programmed with 8 (binary “01000”).
7535  *
7536  * Field Access Macros:
7537  *
7538  */
7539 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH register field. */
7540 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH_LSB 0
7541 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH register field. */
7542 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH_MSB 4
7543 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH register field. */
7544 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH_WIDTH 5
7545 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH register field value. */
7546 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH_SET_MSK 0x0000001f
7547 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH register field value. */
7548 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH_CLR_MSK 0xffffffe0
7549 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH register field is UNKNOWN. */
7550 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH_RESET 0x0
7551 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH field value from a register. */
7552 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH_GET(value) (((value) & 0x0000001f) >> 0)
7553 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH register field value suitable for setting the register. */
7554 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH_SET(value) (((value) << 0) & 0x0000001f)
7555 
7556 /*
7557  * Field : cfg_addr_order
7558  *
7559  * iohmc_ctrl_mmr_top_inst.cfg_addr_order[1:0]
7560  *
7561  * Name:Address Interleaving Order
7562  *
7563  * Description:Selects the order for address interleaving. Programming this field
7564  * with different values gives different mappings between the AXI or Avalon-MM
7565  * address and the SDRAM address. Program this field with the following binary
7566  * values to select the ordering. “00” – chip, row, bank, column; “01”
7567  * – chip, bank, row, column; “10”-row, chip, bank, column
7568  *
7569  * Field Access Macros:
7570  *
7571  */
7572 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER register field. */
7573 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER_LSB 5
7574 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER register field. */
7575 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER_MSB 6
7576 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER register field. */
7577 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER_WIDTH 2
7578 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER register field value. */
7579 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER_SET_MSK 0x00000060
7580 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER register field value. */
7581 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER_CLR_MSK 0xffffff9f
7582 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER register field is UNKNOWN. */
7583 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER_RESET 0x0
7584 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER field value from a register. */
7585 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER_GET(value) (((value) & 0x00000060) >> 5)
7586 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER register field value suitable for setting the register. */
7587 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER_SET(value) (((value) << 5) & 0x00000060)
7588 
7589 /*
7590  * Field : cfg_ctrl_enable_ecc
7591  *
7592  * iohmc_ctrl_mmr_top_inst.cfg_ctrl_enable_ecc
7593  *
7594  * Name:Ctrl – ECC Enable
7595  *
7596  * Description:Enable the generation and checking of ECC.
7597  *
7598  * Field Access Macros:
7599  *
7600  */
7601 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC register field. */
7602 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC_LSB 7
7603 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC register field. */
7604 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC_MSB 7
7605 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC register field. */
7606 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC_WIDTH 1
7607 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC register field value. */
7608 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC_SET_MSK 0x00000080
7609 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC register field value. */
7610 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC_CLR_MSK 0xffffff7f
7611 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC register field is UNKNOWN. */
7612 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC_RESET 0x0
7613 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC field value from a register. */
7614 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC_GET(value) (((value) & 0x00000080) >> 7)
7615 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC register field value suitable for setting the register. */
7616 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC_SET(value) (((value) << 7) & 0x00000080)
7617 
7618 /*
7619  * Field : cfg_dbc0_enable_ecc
7620  *
7621  * iohmc_ctrl_mmr_top_inst.cfg_dbc0_enable_ecc
7622  *
7623  * Name:DBC0 – ECC Enable
7624  *
7625  * Description:Enable the generation and checking of ECC.
7626  *
7627  * Field Access Macros:
7628  *
7629  */
7630 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC register field. */
7631 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC_LSB 8
7632 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC register field. */
7633 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC_MSB 8
7634 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC register field. */
7635 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC_WIDTH 1
7636 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC register field value. */
7637 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC_SET_MSK 0x00000100
7638 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC register field value. */
7639 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC_CLR_MSK 0xfffffeff
7640 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC register field is UNKNOWN. */
7641 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC_RESET 0x0
7642 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC field value from a register. */
7643 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC_GET(value) (((value) & 0x00000100) >> 8)
7644 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC register field value suitable for setting the register. */
7645 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC_SET(value) (((value) << 8) & 0x00000100)
7646 
7647 /*
7648  * Field : cfg_dbc1_enable_ecc
7649  *
7650  * iohmc_ctrl_mmr_top_inst.cfg_dbc1_enable_ecc
7651  *
7652  * Name:DBC1 – ECC Enable
7653  *
7654  * Description:Enable the generation and checking of ECC.
7655  *
7656  * Field Access Macros:
7657  *
7658  */
7659 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC register field. */
7660 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC_LSB 9
7661 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC register field. */
7662 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC_MSB 9
7663 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC register field. */
7664 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC_WIDTH 1
7665 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC register field value. */
7666 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC_SET_MSK 0x00000200
7667 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC register field value. */
7668 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC_CLR_MSK 0xfffffdff
7669 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC register field is UNKNOWN. */
7670 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC_RESET 0x0
7671 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC field value from a register. */
7672 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC_GET(value) (((value) & 0x00000200) >> 9)
7673 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC register field value suitable for setting the register. */
7674 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC_SET(value) (((value) << 9) & 0x00000200)
7675 
7676 /*
7677  * Field : cfg_dbc2_enable_ecc
7678  *
7679  * iohmc_ctrl_mmr_top_inst.cfg_dbc2_enable_ecc
7680  *
7681  * Name:DBC2 – ECC Enable
7682  *
7683  * Description:Enable the generation and checking of ECC.
7684  *
7685  * Field Access Macros:
7686  *
7687  */
7688 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC register field. */
7689 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC_LSB 10
7690 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC register field. */
7691 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC_MSB 10
7692 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC register field. */
7693 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC_WIDTH 1
7694 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC register field value. */
7695 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC_SET_MSK 0x00000400
7696 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC register field value. */
7697 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC_CLR_MSK 0xfffffbff
7698 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC register field is UNKNOWN. */
7699 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC_RESET 0x0
7700 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC field value from a register. */
7701 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC_GET(value) (((value) & 0x00000400) >> 10)
7702 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC register field value suitable for setting the register. */
7703 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC_SET(value) (((value) << 10) & 0x00000400)
7704 
7705 /*
7706  * Field : cfg_dbc3_enable_ecc
7707  *
7708  * iohmc_ctrl_mmr_top_inst.cfg_dbc3_enable_ecc
7709  *
7710  * Name:DBC3 – ECC Enable
7711  *
7712  * Description:Enable the generation and checking of ECC.
7713  *
7714  * Field Access Macros:
7715  *
7716  */
7717 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC register field. */
7718 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC_LSB 11
7719 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC register field. */
7720 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC_MSB 11
7721 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC register field. */
7722 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC_WIDTH 1
7723 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC register field value. */
7724 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC_SET_MSK 0x00000800
7725 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC register field value. */
7726 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC_CLR_MSK 0xfffff7ff
7727 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC register field is UNKNOWN. */
7728 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC_RESET 0x0
7729 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC field value from a register. */
7730 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC_GET(value) (((value) & 0x00000800) >> 11)
7731 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC register field value suitable for setting the register. */
7732 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC_SET(value) (((value) << 11) & 0x00000800)
7733 
7734 /*
7735  * Field : cfg_reorder_data
7736  *
7737  * iohmc_ctrl_mmr_top_inst.cfg_reorder_data
7738  *
7739  * Name:Column Command Reorder Enable
7740  *
7741  * Description:This bit controls whether the controller can re-order operations to
7742  * optimize SDRAM bandwidth. It should generally be set to a one.
7743  *
7744  * Field Access Macros:
7745  *
7746  */
7747 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA register field. */
7748 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA_LSB 12
7749 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA register field. */
7750 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA_MSB 12
7751 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA register field. */
7752 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA_WIDTH 1
7753 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA register field value. */
7754 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA_SET_MSK 0x00001000
7755 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA register field value. */
7756 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA_CLR_MSK 0xffffefff
7757 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA register field is UNKNOWN. */
7758 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA_RESET 0x0
7759 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA field value from a register. */
7760 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA_GET(value) (((value) & 0x00001000) >> 12)
7761 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA register field value suitable for setting the register. */
7762 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA_SET(value) (((value) << 12) & 0x00001000)
7763 
7764 /*
7765  * Field : cfg_ctrl_reorder_rdata
7766  *
7767  * iohmc_ctrl_mmr_top_inst.cfg_ctrl_reorder_rdata
7768  *
7769  * Name:CTRL – Read Data Reorder Enable
7770  *
7771  * Description:This bit controls whether the controller need to re-order the read
7772  * return data.
7773  *
7774  * Field Access Macros:
7775  *
7776  */
7777 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA register field. */
7778 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA_LSB 13
7779 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA register field. */
7780 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA_MSB 13
7781 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA register field. */
7782 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA_WIDTH 1
7783 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA register field value. */
7784 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA_SET_MSK 0x00002000
7785 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA register field value. */
7786 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA_CLR_MSK 0xffffdfff
7787 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA register field is UNKNOWN. */
7788 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA_RESET 0x0
7789 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA field value from a register. */
7790 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA_GET(value) (((value) & 0x00002000) >> 13)
7791 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA register field value suitable for setting the register. */
7792 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA_SET(value) (((value) << 13) & 0x00002000)
7793 
7794 /*
7795  * Field : cfg_dbc0_reorder_rdata
7796  *
7797  * iohmc_ctrl_mmr_top_inst.cfg_dbc0_reorder_rdata
7798  *
7799  * Name:DBC0 – Read Data Reorder Enable
7800  *
7801  * Description:This bit controls whether the controller need to re-order the read
7802  * return data.
7803  *
7804  * Field Access Macros:
7805  *
7806  */
7807 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA register field. */
7808 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA_LSB 14
7809 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA register field. */
7810 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA_MSB 14
7811 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA register field. */
7812 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA_WIDTH 1
7813 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA register field value. */
7814 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA_SET_MSK 0x00004000
7815 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA register field value. */
7816 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA_CLR_MSK 0xffffbfff
7817 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA register field is UNKNOWN. */
7818 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA_RESET 0x0
7819 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA field value from a register. */
7820 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA_GET(value) (((value) & 0x00004000) >> 14)
7821 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA register field value suitable for setting the register. */
7822 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA_SET(value) (((value) << 14) & 0x00004000)
7823 
7824 /*
7825  * Field : cfg_dbc1_reorder_rdata
7826  *
7827  * iohmc_ctrl_mmr_top_inst.cfg_dbc1_reorder_rdata
7828  *
7829  * Name:DBC1 – Read Data Reorder Enable
7830  *
7831  * Description:This bit controls whether the controller need to re-order the read
7832  * return data.
7833  *
7834  * Field Access Macros:
7835  *
7836  */
7837 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA register field. */
7838 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA_LSB 15
7839 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA register field. */
7840 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA_MSB 15
7841 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA register field. */
7842 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA_WIDTH 1
7843 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA register field value. */
7844 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA_SET_MSK 0x00008000
7845 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA register field value. */
7846 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA_CLR_MSK 0xffff7fff
7847 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA register field is UNKNOWN. */
7848 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA_RESET 0x0
7849 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA field value from a register. */
7850 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA_GET(value) (((value) & 0x00008000) >> 15)
7851 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA register field value suitable for setting the register. */
7852 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA_SET(value) (((value) << 15) & 0x00008000)
7853 
7854 /*
7855  * Field : cfg_dbc2_reorder_rdata
7856  *
7857  * iohmc_ctrl_mmr_top_inst.cfg_dbc2_reorder_rdata
7858  *
7859  * Name:DBC2 – Read Data Reorder Enable
7860  *
7861  * Description:This bit controls whether the controller need to re-order the read
7862  * return data.
7863  *
7864  * Field Access Macros:
7865  *
7866  */
7867 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA register field. */
7868 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA_LSB 16
7869 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA register field. */
7870 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA_MSB 16
7871 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA register field. */
7872 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA_WIDTH 1
7873 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA register field value. */
7874 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA_SET_MSK 0x00010000
7875 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA register field value. */
7876 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA_CLR_MSK 0xfffeffff
7877 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA register field is UNKNOWN. */
7878 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA_RESET 0x0
7879 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA field value from a register. */
7880 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA_GET(value) (((value) & 0x00010000) >> 16)
7881 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA register field value suitable for setting the register. */
7882 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA_SET(value) (((value) << 16) & 0x00010000)
7883 
7884 /*
7885  * Field : cfg_dbc3_reorder_rdata
7886  *
7887  * iohmc_ctrl_mmr_top_inst.cfg_dbc3_reorder_rdata
7888  *
7889  * Name:DBC3 – Read Data Reorder Enable
7890  *
7891  * Description:This bit controls whether the controller need to re-order the read
7892  * return data.
7893  *
7894  * Field Access Macros:
7895  *
7896  */
7897 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA register field. */
7898 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA_LSB 17
7899 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA register field. */
7900 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA_MSB 17
7901 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA register field. */
7902 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA_WIDTH 1
7903 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA register field value. */
7904 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA_SET_MSK 0x00020000
7905 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA register field value. */
7906 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA_CLR_MSK 0xfffdffff
7907 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA register field is UNKNOWN. */
7908 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA_RESET 0x0
7909 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA field value from a register. */
7910 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA_GET(value) (((value) & 0x00020000) >> 17)
7911 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA register field value suitable for setting the register. */
7912 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA_SET(value) (((value) << 17) & 0x00020000)
7913 
7914 /*
7915  * Field : cfg_reorder_read
7916  *
7917  * iohmc_ctrl_mmr_top_inst.cfg_reorder_read
7918  *
7919  * Name:Read Command Reorder Enable
7920  *
7921  * Description:This bit controls whether the controller can re-order read command
7922  * to. 1’b0 – Disable, 1’b1 – Enable
7923  *
7924  * Field Access Macros:
7925  *
7926  */
7927 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ register field. */
7928 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ_LSB 18
7929 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ register field. */
7930 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ_MSB 18
7931 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ register field. */
7932 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ_WIDTH 1
7933 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ register field value. */
7934 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ_SET_MSK 0x00040000
7935 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ register field value. */
7936 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ_CLR_MSK 0xfffbffff
7937 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ register field is UNKNOWN. */
7938 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ_RESET 0x0
7939 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ field value from a register. */
7940 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ_GET(value) (((value) & 0x00040000) >> 18)
7941 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ register field value suitable for setting the register. */
7942 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ_SET(value) (((value) << 18) & 0x00040000)
7943 
7944 /*
7945  * Field : cfg_starve_limit
7946  *
7947  * iohmc_ctrl_mmr_top_inst.cfg_starve_limit[5:0]
7948  *
7949  * Name:Starvation Limit
7950  *
7951  * Description:Specifies the number of DRAM burst transactions an individual
7952  * transaction will allow to reorder ahead of it before its priority is raised in
7953  * the memory controller.
7954  *
7955  * Field Access Macros:
7956  *
7957  */
7958 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT register field. */
7959 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT_LSB 19
7960 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT register field. */
7961 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT_MSB 24
7962 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT register field. */
7963 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT_WIDTH 6
7964 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT register field value. */
7965 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT_SET_MSK 0x01f80000
7966 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT register field value. */
7967 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT_CLR_MSK 0xfe07ffff
7968 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT register field is UNKNOWN. */
7969 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT_RESET 0x0
7970 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT field value from a register. */
7971 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT_GET(value) (((value) & 0x01f80000) >> 19)
7972 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT register field value suitable for setting the register. */
7973 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT_SET(value) (((value) << 19) & 0x01f80000)
7974 
7975 /*
7976  * Field : cfg_dqstrk_en
7977  *
7978  * iohmc_ctrl_mmr_top_inst.cfg_dqstrk_en
7979  *
7980  * Name:DQS Tracking Enable
7981  *
7982  * Description:Enables DQS tracking in the PHY.
7983  *
7984  * 1’b1 – Enable Long/Short DQS Tracking
7985  *
7986  * Post-REFRESH-EXIT – Refer to cfg_short_dqstrk_ctrl_en
7987  *
7988  * Post-SELFREFRESH-EXIT – IOPHYSEQ performs Long DQS Tracking
7989  *
7990  * 1’b0 – Disable DQS Tracking
7991  *
7992  * Field Access Macros:
7993  *
7994  */
7995 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN register field. */
7996 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN_LSB 25
7997 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN register field. */
7998 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN_MSB 25
7999 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN register field. */
8000 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN_WIDTH 1
8001 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN register field value. */
8002 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN_SET_MSK 0x02000000
8003 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN register field value. */
8004 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN_CLR_MSK 0xfdffffff
8005 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN register field is UNKNOWN. */
8006 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN_RESET 0x0
8007 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN field value from a register. */
8008 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN_GET(value) (((value) & 0x02000000) >> 25)
8009 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN register field value suitable for setting the register. */
8010 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN_SET(value) (((value) << 25) & 0x02000000)
8011 
8012 /*
8013  * Field : cfg_ctrl_enable_dm
8014  *
8015  * iohmc_ctrl_mmr_top_inst.cfg_ctrl_enable_dm
8016  *
8017  * Name:DM Pins Present
8018  *
8019  * Description:Set to a one to enable DRAM operation if DM pins are connected.
8020  *
8021  * Field Access Macros:
8022  *
8023  */
8024 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM register field. */
8025 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM_LSB 26
8026 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM register field. */
8027 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM_MSB 26
8028 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM register field. */
8029 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM_WIDTH 1
8030 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM register field value. */
8031 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM_SET_MSK 0x04000000
8032 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM register field value. */
8033 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM_CLR_MSK 0xfbffffff
8034 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM register field is UNKNOWN. */
8035 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM_RESET 0x0
8036 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM field value from a register. */
8037 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM_GET(value) (((value) & 0x04000000) >> 26)
8038 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM register field value suitable for setting the register. */
8039 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM_SET(value) (((value) << 26) & 0x04000000)
8040 
8041 /*
8042  * Field : cfg_dbc0_enable_dm
8043  *
8044  * iohmc_ctrl_mmr_top_inst.cfg_dbc0_enable_dm
8045  *
8046  * Name:DM Pins Present
8047  *
8048  * Description:Set to a one to enable DRAM operation if DM pins are connected.
8049  *
8050  * Field Access Macros:
8051  *
8052  */
8053 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM register field. */
8054 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM_LSB 27
8055 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM register field. */
8056 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM_MSB 27
8057 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM register field. */
8058 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM_WIDTH 1
8059 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM register field value. */
8060 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM_SET_MSK 0x08000000
8061 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM register field value. */
8062 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM_CLR_MSK 0xf7ffffff
8063 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM register field is UNKNOWN. */
8064 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM_RESET 0x0
8065 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM field value from a register. */
8066 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM_GET(value) (((value) & 0x08000000) >> 27)
8067 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM register field value suitable for setting the register. */
8068 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM_SET(value) (((value) << 27) & 0x08000000)
8069 
8070 /*
8071  * Field : cfg_dbc1_enable_dm
8072  *
8073  * iohmc_ctrl_mmr_top_inst.cfg_dbc1_enable_dm
8074  *
8075  * Name:DM Pins Present
8076  *
8077  * Description:Set to a one to enable DRAM operation if DM pins are connected.
8078  *
8079  * Field Access Macros:
8080  *
8081  */
8082 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM register field. */
8083 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM_LSB 28
8084 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM register field. */
8085 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM_MSB 28
8086 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM register field. */
8087 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM_WIDTH 1
8088 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM register field value. */
8089 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM_SET_MSK 0x10000000
8090 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM register field value. */
8091 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM_CLR_MSK 0xefffffff
8092 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM register field is UNKNOWN. */
8093 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM_RESET 0x0
8094 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM field value from a register. */
8095 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM_GET(value) (((value) & 0x10000000) >> 28)
8096 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM register field value suitable for setting the register. */
8097 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM_SET(value) (((value) << 28) & 0x10000000)
8098 
8099 /*
8100  * Field : cfg_dbc2_enable_dm
8101  *
8102  * iohmc_ctrl_mmr_top_inst.cfg_dbc2_enable_dm
8103  *
8104  * Name:DM Pins Present
8105  *
8106  * Description:Set to a one to enable DRAM operation if DM pins are connected.
8107  *
8108  * Field Access Macros:
8109  *
8110  */
8111 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM register field. */
8112 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM_LSB 29
8113 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM register field. */
8114 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM_MSB 29
8115 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM register field. */
8116 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM_WIDTH 1
8117 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM register field value. */
8118 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM_SET_MSK 0x20000000
8119 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM register field value. */
8120 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM_CLR_MSK 0xdfffffff
8121 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM register field is UNKNOWN. */
8122 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM_RESET 0x0
8123 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM field value from a register. */
8124 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM_GET(value) (((value) & 0x20000000) >> 29)
8125 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM register field value suitable for setting the register. */
8126 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM_SET(value) (((value) << 29) & 0x20000000)
8127 
8128 /*
8129  * Field : cfg_dbc3_enable_dm
8130  *
8131  * iohmc_ctrl_mmr_top_inst.cfg_dbc3_enable_dm
8132  *
8133  * Name:DM Pins Present
8134  *
8135  * Description:Set to a one to enable DRAM operation if DM pins are connected.
8136  *
8137  * Field Access Macros:
8138  *
8139  */
8140 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM register field. */
8141 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM_LSB 30
8142 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM register field. */
8143 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM_MSB 30
8144 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM register field. */
8145 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM_WIDTH 1
8146 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM register field value. */
8147 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM_SET_MSK 0x40000000
8148 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM register field value. */
8149 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM_CLR_MSK 0xbfffffff
8150 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM register field is UNKNOWN. */
8151 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM_RESET 0x0
8152 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM field value from a register. */
8153 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM_GET(value) (((value) & 0x40000000) >> 30)
8154 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM register field value suitable for setting the register. */
8155 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM_SET(value) (((value) << 30) & 0x40000000)
8156 
8157 #ifndef __ASSEMBLY__
8158 /*
8159  * WARNING: The C register and register group struct declarations are provided for
8160  * convenience and illustrative purposes. They should, however, be used with
8161  * caution as the C language standard provides no guarantees about the alignment or
8162  * atomicity of device memory accesses. The recommended practice for coding device
8163  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8164  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8165  * alt_write_dword() functions for 64 bit registers.
8166  *
8167  * The struct declaration for register ALT_MPFE_IOHMC_REG_CTRLCFG1.
8168  */
8169 struct ALT_MPFE_IOHMC_REG_CTRLCFG1_s
8170 {
8171  volatile uint32_t cfg_dbc3_burst_length : 5; /* ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH */
8172  volatile uint32_t cfg_addr_order : 2; /* ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER */
8173  volatile uint32_t cfg_ctrl_enable_ecc : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC */
8174  volatile uint32_t cfg_dbc0_enable_ecc : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC */
8175  volatile uint32_t cfg_dbc1_enable_ecc : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC */
8176  volatile uint32_t cfg_dbc2_enable_ecc : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC */
8177  volatile uint32_t cfg_dbc3_enable_ecc : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC */
8178  volatile uint32_t cfg_reorder_data : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA */
8179  volatile uint32_t cfg_ctrl_reorder_rdata : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA */
8180  volatile uint32_t cfg_dbc0_reorder_rdata : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA */
8181  volatile uint32_t cfg_dbc1_reorder_rdata : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA */
8182  volatile uint32_t cfg_dbc2_reorder_rdata : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA */
8183  volatile uint32_t cfg_dbc3_reorder_rdata : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA */
8184  volatile uint32_t cfg_reorder_read : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ */
8185  volatile uint32_t cfg_starve_limit : 6; /* ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT */
8186  volatile uint32_t cfg_dqstrk_en : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN */
8187  volatile uint32_t cfg_ctrl_enable_dm : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM */
8188  volatile uint32_t cfg_dbc0_enable_dm : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM */
8189  volatile uint32_t cfg_dbc1_enable_dm : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM */
8190  volatile uint32_t cfg_dbc2_enable_dm : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM */
8191  volatile uint32_t cfg_dbc3_enable_dm : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM */
8192  uint32_t : 1; /* *UNDEFINED* */
8193 };
8194 
8195 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_CTRLCFG1. */
8196 typedef struct ALT_MPFE_IOHMC_REG_CTRLCFG1_s ALT_MPFE_IOHMC_REG_CTRLCFG1_t;
8197 #endif /* __ASSEMBLY__ */
8198 
8199 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG1 register. */
8200 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_RESET 0x00000000
8201 /* The byte offset of the ALT_MPFE_IOHMC_REG_CTRLCFG1 register from the beginning of the component. */
8202 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_OFST 0x2c
8203 
8204 /*
8205  * Register : reg_ctrlcfg2
8206  *
8207  * Register Layout
8208  *
8209  * Bits | Access | Reset | Description
8210  * :--------|:-------|:--------|:-------------------------------------------------
8211  * [0] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD
8212  * [1] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD
8213  * [2] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD
8214  * [3] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD
8215  * [4] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD
8216  * [6:5] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0
8217  * [8:7] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1
8218  * [9] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL
8219  * [10] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL
8220  * [11] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL
8221  * [12] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL
8222  * [14:13] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL
8223  * [17:15] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT
8224  * [20:18] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT
8225  * [23:21] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT
8226  * [26:24] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT
8227  * [31:27] | ??? | Unknown | *UNDEFINED*
8228  *
8229  */
8230 /*
8231  * Field : cfg_ctrl_output_regd
8232  *
8233  * iohmc_ctrl_mmr_top_inst.cfg_ctrl_output_regd
8234  *
8235  * Name:Reserved
8236  *
8237  * Description:TBD
8238  *
8239  * Field Access Macros:
8240  *
8241  */
8242 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD register field. */
8243 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD_LSB 0
8244 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD register field. */
8245 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD_MSB 0
8246 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD register field. */
8247 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD_WIDTH 1
8248 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD register field value. */
8249 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD_SET_MSK 0x00000001
8250 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD register field value. */
8251 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD_CLR_MSK 0xfffffffe
8252 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD register field is UNKNOWN. */
8253 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD_RESET 0x0
8254 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD field value from a register. */
8255 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD_GET(value) (((value) & 0x00000001) >> 0)
8256 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD register field value suitable for setting the register. */
8257 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD_SET(value) (((value) << 0) & 0x00000001)
8258 
8259 /*
8260  * Field : cfg_dbc0_output_regd
8261  *
8262  * iohmc_ctrl_mmr_top_inst.cfg_dbc0_output_regd
8263  *
8264  * Name:Reserved
8265  *
8266  * Description:TBD
8267  *
8268  * Field Access Macros:
8269  *
8270  */
8271 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD register field. */
8272 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD_LSB 1
8273 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD register field. */
8274 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD_MSB 1
8275 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD register field. */
8276 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD_WIDTH 1
8277 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD register field value. */
8278 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD_SET_MSK 0x00000002
8279 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD register field value. */
8280 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD_CLR_MSK 0xfffffffd
8281 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD register field is UNKNOWN. */
8282 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD_RESET 0x0
8283 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD field value from a register. */
8284 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD_GET(value) (((value) & 0x00000002) >> 1)
8285 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD register field value suitable for setting the register. */
8286 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD_SET(value) (((value) << 1) & 0x00000002)
8287 
8288 /*
8289  * Field : cfg_dbc1_output_regd
8290  *
8291  * iohmc_ctrl_mmr_top_inst.cfg_dbc1_output_regd
8292  *
8293  * Name:Reserved
8294  *
8295  * Description:TBD
8296  *
8297  * Field Access Macros:
8298  *
8299  */
8300 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD register field. */
8301 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD_LSB 2
8302 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD register field. */
8303 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD_MSB 2
8304 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD register field. */
8305 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD_WIDTH 1
8306 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD register field value. */
8307 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD_SET_MSK 0x00000004
8308 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD register field value. */
8309 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD_CLR_MSK 0xfffffffb
8310 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD register field is UNKNOWN. */
8311 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD_RESET 0x0
8312 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD field value from a register. */
8313 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD_GET(value) (((value) & 0x00000004) >> 2)
8314 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD register field value suitable for setting the register. */
8315 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD_SET(value) (((value) << 2) & 0x00000004)
8316 
8317 /*
8318  * Field : cfg_dbc2_output_regd
8319  *
8320  * iohmc_ctrl_mmr_top_inst.cfg_dbc2_output_regd
8321  *
8322  * Name:Reserved
8323  *
8324  * Description:TBD
8325  *
8326  * Field Access Macros:
8327  *
8328  */
8329 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD register field. */
8330 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD_LSB 3
8331 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD register field. */
8332 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD_MSB 3
8333 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD register field. */
8334 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD_WIDTH 1
8335 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD register field value. */
8336 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD_SET_MSK 0x00000008
8337 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD register field value. */
8338 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD_CLR_MSK 0xfffffff7
8339 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD register field is UNKNOWN. */
8340 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD_RESET 0x0
8341 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD field value from a register. */
8342 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD_GET(value) (((value) & 0x00000008) >> 3)
8343 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD register field value suitable for setting the register. */
8344 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD_SET(value) (((value) << 3) & 0x00000008)
8345 
8346 /*
8347  * Field : cfg_dbc3_output_regd
8348  *
8349  * iohmc_ctrl_mmr_top_inst.cfg_dbc3_output_regd
8350  *
8351  * Name:Reserved
8352  *
8353  * Description:TBD
8354  *
8355  * Field Access Macros:
8356  *
8357  */
8358 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD register field. */
8359 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD_LSB 4
8360 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD register field. */
8361 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD_MSB 4
8362 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD register field. */
8363 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD_WIDTH 1
8364 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD register field value. */
8365 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD_SET_MSK 0x00000010
8366 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD register field value. */
8367 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD_CLR_MSK 0xffffffef
8368 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD register field is UNKNOWN. */
8369 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD_RESET 0x0
8370 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD field value from a register. */
8371 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD_GET(value) (((value) & 0x00000010) >> 4)
8372 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD register field value suitable for setting the register. */
8373 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD_SET(value) (((value) << 4) & 0x00000010)
8374 
8375 /*
8376  * Field : cfg_ctrl2dbc_switch0
8377  *
8378  * iohmc_ctrl_mmr_top_inst.cfg_ctrl2dbc_switch0[1:0]
8379  *
8380  * Name:Control source switch0 select
8381  *
8382  * Description:Select of the MUX ctrl2dbc_switch0. 2’b00 – selects the control
8383  * path from upper tiles. 2’b01 – selects the local control path. 2’b10 –
8384  * selects the control path from lower tiles. 2’b11 – illegal selection.
8385  *
8386  * Field Access Macros:
8387  *
8388  */
8389 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0 register field. */
8390 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0_LSB 5
8391 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0 register field. */
8392 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0_MSB 6
8393 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0 register field. */
8394 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0_WIDTH 2
8395 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0 register field value. */
8396 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0_SET_MSK 0x00000060
8397 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0 register field value. */
8398 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0_CLR_MSK 0xffffff9f
8399 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0 register field is UNKNOWN. */
8400 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0_RESET 0x0
8401 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0 field value from a register. */
8402 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0_GET(value) (((value) & 0x00000060) >> 5)
8403 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0 register field value suitable for setting the register. */
8404 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0_SET(value) (((value) << 5) & 0x00000060)
8405 
8406 /*
8407  * Field : cfg_ctrl2dbc_switch1
8408  *
8409  * iohmc_ctrl_mmr_top_inst.cfg_ctrl2dbc_switch1[1:0]
8410  *
8411  * Name:Control source switch1 select
8412  *
8413  * Description:Select of the MUX ctrl2dbc_switch1. 2’b00 – selects the control
8414  * path from upper tiles. 2’b01 – selects the local control path. 2’b10 –
8415  * selects the control path from lower tiles. 2’b11 – illegal selection.
8416  *
8417  * Field Access Macros:
8418  *
8419  */
8420 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1 register field. */
8421 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1_LSB 7
8422 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1 register field. */
8423 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1_MSB 8
8424 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1 register field. */
8425 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1_WIDTH 2
8426 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1 register field value. */
8427 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1_SET_MSK 0x00000180
8428 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1 register field value. */
8429 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1_CLR_MSK 0xfffffe7f
8430 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1 register field is UNKNOWN. */
8431 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1_RESET 0x0
8432 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1 field value from a register. */
8433 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1_GET(value) (((value) & 0x00000180) >> 7)
8434 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1 register field value suitable for setting the register. */
8435 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1_SET(value) (((value) << 7) & 0x00000180)
8436 
8437 /*
8438  * Field : cfg_dbc0_ctrl_sel
8439  *
8440  * iohmc_ctrl_mmr_top_inst.cfg_dbc0_ctrl_sel
8441  *
8442  * Name:DBC0 – control path select
8443  *
8444  * Description:DBC0 – control path select. 1’b0: The upper MUX in
8445  * io_hmc_dbc_switch is selected; 1’b1: The lower mux is selected.
8446  *
8447  * Field Access Macros:
8448  *
8449  */
8450 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL register field. */
8451 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL_LSB 9
8452 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL register field. */
8453 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL_MSB 9
8454 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL register field. */
8455 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL_WIDTH 1
8456 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL register field value. */
8457 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL_SET_MSK 0x00000200
8458 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL register field value. */
8459 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL_CLR_MSK 0xfffffdff
8460 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL register field is UNKNOWN. */
8461 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL_RESET 0x0
8462 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL field value from a register. */
8463 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL_GET(value) (((value) & 0x00000200) >> 9)
8464 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL register field value suitable for setting the register. */
8465 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL_SET(value) (((value) << 9) & 0x00000200)
8466 
8467 /*
8468  * Field : cfg_dbc1_ctrl_sel
8469  *
8470  * iohmc_ctrl_mmr_top_inst.cfg_dbc1_ctrl_sel
8471  *
8472  * Name:DBC1 – control path select
8473  *
8474  * Description:DBC1 – control path select. 1’b0: The upper MUX in
8475  * io_hmc_dbc_switch is selected; 1’b1: The lower mux is selected.
8476  *
8477  * Field Access Macros:
8478  *
8479  */
8480 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL register field. */
8481 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL_LSB 10
8482 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL register field. */
8483 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL_MSB 10
8484 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL register field. */
8485 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL_WIDTH 1
8486 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL register field value. */
8487 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL_SET_MSK 0x00000400
8488 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL register field value. */
8489 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL_CLR_MSK 0xfffffbff
8490 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL register field is UNKNOWN. */
8491 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL_RESET 0x0
8492 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL field value from a register. */
8493 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL_GET(value) (((value) & 0x00000400) >> 10)
8494 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL register field value suitable for setting the register. */
8495 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL_SET(value) (((value) << 10) & 0x00000400)
8496 
8497 /*
8498  * Field : cfg_dbc2_ctrl_sel
8499  *
8500  * iohmc_ctrl_mmr_top_inst.cfg_dbc2_ctrl_sel
8501  *
8502  * Name:DBC2 – control path select
8503  *
8504  * Description:DBC2 – control path select. 1’b0: The upper MUX in
8505  * io_hmc_dbc_switch is selected; 1’b1: The lower mux is selected.
8506  *
8507  * Field Access Macros:
8508  *
8509  */
8510 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL register field. */
8511 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL_LSB 11
8512 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL register field. */
8513 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL_MSB 11
8514 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL register field. */
8515 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL_WIDTH 1
8516 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL register field value. */
8517 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL_SET_MSK 0x00000800
8518 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL register field value. */
8519 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL_CLR_MSK 0xfffff7ff
8520 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL register field is UNKNOWN. */
8521 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL_RESET 0x0
8522 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL field value from a register. */
8523 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL_GET(value) (((value) & 0x00000800) >> 11)
8524 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL register field value suitable for setting the register. */
8525 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL_SET(value) (((value) << 11) & 0x00000800)
8526 
8527 /*
8528  * Field : cfg_dbc3_ctrl_sel
8529  *
8530  * iohmc_ctrl_mmr_top_inst.cfg_dbc3_ctrl_sel
8531  *
8532  * Name:DBC3 – control path select
8533  *
8534  * Description:DBC3 – control path select. 1’b0: The upper MUX in
8535  * io_hmc_dbc_switch is selected; 1’b1: The lower mux is selected.
8536  *
8537  * Field Access Macros:
8538  *
8539  */
8540 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL register field. */
8541 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL_LSB 12
8542 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL register field. */
8543 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL_MSB 12
8544 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL register field. */
8545 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL_WIDTH 1
8546 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL register field value. */
8547 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL_SET_MSK 0x00001000
8548 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL register field value. */
8549 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL_CLR_MSK 0xffffefff
8550 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL register field is UNKNOWN. */
8551 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL_RESET 0x0
8552 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL field value from a register. */
8553 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL_GET(value) (((value) & 0x00001000) >> 12)
8554 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL register field value suitable for setting the register. */
8555 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL_SET(value) (((value) << 12) & 0x00001000)
8556 
8557 /*
8558  * Field : cfg_dbc2ctrl_sel
8559  *
8560  * iohmc_ctrl_mmr_top_inst.cfg_dbc2ctrl_sel[1:0]
8561  *
8562  * Name:Control path-DBC select
8563  *
8564  * Description:Specifies which DBC is driven by the local control path. 2’b00:
8565  * DBC0; 2’b01: DBC1; 2’b10: DBC2; 2’b11: DBC3.
8566  *
8567  * Field Access Macros:
8568  *
8569  */
8570 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL register field. */
8571 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL_LSB 13
8572 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL register field. */
8573 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL_MSB 14
8574 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL register field. */
8575 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL_WIDTH 2
8576 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL register field value. */
8577 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL_SET_MSK 0x00006000
8578 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL register field value. */
8579 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL_CLR_MSK 0xffff9fff
8580 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL register field is UNKNOWN. */
8581 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL_RESET 0x0
8582 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL field value from a register. */
8583 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL_GET(value) (((value) & 0x00006000) >> 13)
8584 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL register field value suitable for setting the register. */
8585 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL_SET(value) (((value) << 13) & 0x00006000)
8586 
8587 /*
8588  * Field : cfg_dbc0_pipe_lat
8589  *
8590  * iohmc_ctrl_mmr_top_inst.cfg_dbc0_pipe_lat[2:0]
8591  *
8592  * Name:DBC0 – pipeline latency
8593  *
8594  * Description:Specifies in number of controller clock cycles the latency of
8595  * pipelining the signals from control path to DBC0.
8596  *
8597  * Field Access Macros:
8598  *
8599  */
8600 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT register field. */
8601 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT_LSB 15
8602 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT register field. */
8603 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT_MSB 17
8604 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT register field. */
8605 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT_WIDTH 3
8606 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT register field value. */
8607 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT_SET_MSK 0x00038000
8608 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT register field value. */
8609 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT_CLR_MSK 0xfffc7fff
8610 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT register field is UNKNOWN. */
8611 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT_RESET 0x0
8612 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT field value from a register. */
8613 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT_GET(value) (((value) & 0x00038000) >> 15)
8614 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT register field value suitable for setting the register. */
8615 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT_SET(value) (((value) << 15) & 0x00038000)
8616 
8617 /*
8618  * Field : cfg_dbc1_pipe_lat
8619  *
8620  * iohmc_ctrl_mmr_top_inst.cfg_dbc1_pipe_lat[2:0]
8621  *
8622  * Name:DBC1 – pipeline latency
8623  *
8624  * Description:Specifies in number of controller clock cycles the latency of
8625  * pipelining the signals from control path to DBC1.
8626  *
8627  * Field Access Macros:
8628  *
8629  */
8630 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT register field. */
8631 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT_LSB 18
8632 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT register field. */
8633 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT_MSB 20
8634 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT register field. */
8635 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT_WIDTH 3
8636 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT register field value. */
8637 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT_SET_MSK 0x001c0000
8638 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT register field value. */
8639 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT_CLR_MSK 0xffe3ffff
8640 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT register field is UNKNOWN. */
8641 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT_RESET 0x0
8642 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT field value from a register. */
8643 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT_GET(value) (((value) & 0x001c0000) >> 18)
8644 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT register field value suitable for setting the register. */
8645 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT_SET(value) (((value) << 18) & 0x001c0000)
8646 
8647 /*
8648  * Field : cfg_dbc2_pipe_lat
8649  *
8650  * iohmc_ctrl_mmr_top_inst.cfg_dbc2_pipe_lat[2:0]
8651  *
8652  * Name:DBC2 – pipeline latency
8653  *
8654  * Description:Specifies in number of controller clock cycles the latency of
8655  * pipelining the signals from control path to DBC2.
8656  *
8657  * Field Access Macros:
8658  *
8659  */
8660 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT register field. */
8661 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT_LSB 21
8662 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT register field. */
8663 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT_MSB 23
8664 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT register field. */
8665 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT_WIDTH 3
8666 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT register field value. */
8667 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT_SET_MSK 0x00e00000
8668 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT register field value. */
8669 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT_CLR_MSK 0xff1fffff
8670 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT register field is UNKNOWN. */
8671 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT_RESET 0x0
8672 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT field value from a register. */
8673 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT_GET(value) (((value) & 0x00e00000) >> 21)
8674 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT register field value suitable for setting the register. */
8675 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT_SET(value) (((value) << 21) & 0x00e00000)
8676 
8677 /*
8678  * Field : cfg_dbc3_pipe_lat
8679  *
8680  * iohmc_ctrl_mmr_top_inst.cfg_dbc3_pipe_lat[2:0]
8681  *
8682  * Name:DBC3 – pipeline latency
8683  *
8684  * Description:Specifies in number of controller clock cycles the latency of
8685  * pipelining the signals from control path to DBC3.
8686  *
8687  * Field Access Macros:
8688  *
8689  */
8690 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT register field. */
8691 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT_LSB 24
8692 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT register field. */
8693 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT_MSB 26
8694 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT register field. */
8695 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT_WIDTH 3
8696 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT register field value. */
8697 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT_SET_MSK 0x07000000
8698 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT register field value. */
8699 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT_CLR_MSK 0xf8ffffff
8700 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT register field is UNKNOWN. */
8701 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT_RESET 0x0
8702 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT field value from a register. */
8703 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT_GET(value) (((value) & 0x07000000) >> 24)
8704 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT register field value suitable for setting the register. */
8705 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT_SET(value) (((value) << 24) & 0x07000000)
8706 
8707 #ifndef __ASSEMBLY__
8708 /*
8709  * WARNING: The C register and register group struct declarations are provided for
8710  * convenience and illustrative purposes. They should, however, be used with
8711  * caution as the C language standard provides no guarantees about the alignment or
8712  * atomicity of device memory accesses. The recommended practice for coding device
8713  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8714  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8715  * alt_write_dword() functions for 64 bit registers.
8716  *
8717  * The struct declaration for register ALT_MPFE_IOHMC_REG_CTRLCFG2.
8718  */
8719 struct ALT_MPFE_IOHMC_REG_CTRLCFG2_s
8720 {
8721  volatile uint32_t cfg_ctrl_output_regd : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD */
8722  volatile uint32_t cfg_dbc0_output_regd : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD */
8723  volatile uint32_t cfg_dbc1_output_regd : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD */
8724  volatile uint32_t cfg_dbc2_output_regd : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD */
8725  volatile uint32_t cfg_dbc3_output_regd : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD */
8726  volatile uint32_t cfg_ctrl2dbc_switch0 : 2; /* ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0 */
8727  volatile uint32_t cfg_ctrl2dbc_switch1 : 2; /* ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1 */
8728  volatile uint32_t cfg_dbc0_ctrl_sel : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL */
8729  volatile uint32_t cfg_dbc1_ctrl_sel : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL */
8730  volatile uint32_t cfg_dbc2_ctrl_sel : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL */
8731  volatile uint32_t cfg_dbc3_ctrl_sel : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL */
8732  volatile uint32_t cfg_dbc2ctrl_sel : 2; /* ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL */
8733  volatile uint32_t cfg_dbc0_pipe_lat : 3; /* ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT */
8734  volatile uint32_t cfg_dbc1_pipe_lat : 3; /* ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT */
8735  volatile uint32_t cfg_dbc2_pipe_lat : 3; /* ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT */
8736  volatile uint32_t cfg_dbc3_pipe_lat : 3; /* ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT */
8737  uint32_t : 5; /* *UNDEFINED* */
8738 };
8739 
8740 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_CTRLCFG2. */
8741 typedef struct ALT_MPFE_IOHMC_REG_CTRLCFG2_s ALT_MPFE_IOHMC_REG_CTRLCFG2_t;
8742 #endif /* __ASSEMBLY__ */
8743 
8744 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG2 register. */
8745 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_RESET 0x00000000
8746 /* The byte offset of the ALT_MPFE_IOHMC_REG_CTRLCFG2 register from the beginning of the component. */
8747 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_OFST 0x30
8748 
8749 /*
8750  * Register : reg_ctrlcfg3
8751  *
8752  * Register Layout
8753  *
8754  * Bits | Access | Reset | Description
8755  * :--------|:-------|:--------|:-------------------------------------------------------
8756  * [2:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE
8757  * [5:3] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE
8758  * [8:6] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE
8759  * [11:9] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE
8760  * [14:12] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE
8761  * [15] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL
8762  * [16] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL
8763  * [17] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL
8764  * [18] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL
8765  * [19] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL
8766  * [20] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN
8767  * [21] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN
8768  * [22] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN
8769  * [23] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN
8770  * [24] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN
8771  * [25] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE
8772  * [26] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN
8773  * [27] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN
8774  * [28] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE
8775  * [29] | ??? | Unknown | *UNDEFINED*
8776  * [30] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT
8777  * [31] | ??? | Unknown | *UNDEFINED*
8778  *
8779  */
8780 /*
8781  * Field : cfg_ctrl_cmd_rate
8782  *
8783  * iohmc_ctrl_mmr_top_inst.cfg_ctrl_cmd_rate[2:0]
8784  *
8785  * Name:Control path – Command Rate
8786  *
8787  * Description:3’b010 – HALF rate. 3’b100 – Quarter rate. The remaining
8788  * values are reserved.
8789  *
8790  * Field Access Macros:
8791  *
8792  */
8793 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE register field. */
8794 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE_LSB 0
8795 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE register field. */
8796 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE_MSB 2
8797 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE register field. */
8798 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE_WIDTH 3
8799 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE register field value. */
8800 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE_SET_MSK 0x00000007
8801 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE register field value. */
8802 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE_CLR_MSK 0xfffffff8
8803 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE register field is UNKNOWN. */
8804 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE_RESET 0x0
8805 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE field value from a register. */
8806 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE_GET(value) (((value) & 0x00000007) >> 0)
8807 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE register field value suitable for setting the register. */
8808 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE_SET(value) (((value) << 0) & 0x00000007)
8809 
8810 /*
8811  * Field : cfg_dbc0_cmd_rate
8812  *
8813  * iohmc_ctrl_mmr_top_inst.cfg_dbc0_cmd_rate[2:0]
8814  *
8815  * Name:DBC0 – Command Rate
8816  *
8817  * Description:3’b010 – HALF rate. 3’b100 – Quarter rate. The remaining
8818  * values are reserved.
8819  *
8820  * Field Access Macros:
8821  *
8822  */
8823 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE register field. */
8824 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE_LSB 3
8825 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE register field. */
8826 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE_MSB 5
8827 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE register field. */
8828 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE_WIDTH 3
8829 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE register field value. */
8830 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE_SET_MSK 0x00000038
8831 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE register field value. */
8832 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE_CLR_MSK 0xffffffc7
8833 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE register field is UNKNOWN. */
8834 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE_RESET 0x0
8835 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE field value from a register. */
8836 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE_GET(value) (((value) & 0x00000038) >> 3)
8837 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE register field value suitable for setting the register. */
8838 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE_SET(value) (((value) << 3) & 0x00000038)
8839 
8840 /*
8841  * Field : cfg_dbc1_cmd_rate
8842  *
8843  * iohmc_ctrl_mmr_top_inst.cfg_dbc1_cmd_rate[2:0]
8844  *
8845  * Name:DBC1 – Command Rate
8846  *
8847  * Description:3’b010 – HALF rate. 3’b100 – Quarter rate. The remaining
8848  * values are reserved.
8849  *
8850  * Field Access Macros:
8851  *
8852  */
8853 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE register field. */
8854 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE_LSB 6
8855 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE register field. */
8856 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE_MSB 8
8857 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE register field. */
8858 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE_WIDTH 3
8859 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE register field value. */
8860 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE_SET_MSK 0x000001c0
8861 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE register field value. */
8862 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE_CLR_MSK 0xfffffe3f
8863 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE register field is UNKNOWN. */
8864 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE_RESET 0x0
8865 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE field value from a register. */
8866 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE_GET(value) (((value) & 0x000001c0) >> 6)
8867 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE register field value suitable for setting the register. */
8868 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE_SET(value) (((value) << 6) & 0x000001c0)
8869 
8870 /*
8871  * Field : cfg_dbc2_cmd_rate
8872  *
8873  * iohmc_ctrl_mmr_top_inst.cfg_dbc2_cmd_rate[2:0]
8874  *
8875  * Name:DBC2 – Command Rate
8876  *
8877  * Description:3’b010 – HALF rate. 3’b100 – Quarter rate. The remaining
8878  * values are reserved.
8879  *
8880  * Field Access Macros:
8881  *
8882  */
8883 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE register field. */
8884 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE_LSB 9
8885 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE register field. */
8886 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE_MSB 11
8887 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE register field. */
8888 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE_WIDTH 3
8889 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE register field value. */
8890 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE_SET_MSK 0x00000e00
8891 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE register field value. */
8892 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE_CLR_MSK 0xfffff1ff
8893 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE register field is UNKNOWN. */
8894 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE_RESET 0x0
8895 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE field value from a register. */
8896 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE_GET(value) (((value) & 0x00000e00) >> 9)
8897 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE register field value suitable for setting the register. */
8898 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE_SET(value) (((value) << 9) & 0x00000e00)
8899 
8900 /*
8901  * Field : cfg_dbc3_cmd_rate
8902  *
8903  * iohmc_ctrl_mmr_top_inst.cfg_dbc3_cmd_rate[2:0]
8904  *
8905  * Name:DBC3 – Command Rate
8906  *
8907  * Description:3’b010 – HALF rate. 3’b100 – Quarter rate. The remaining
8908  * values are reserved.
8909  *
8910  * Field Access Macros:
8911  *
8912  */
8913 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE register field. */
8914 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE_LSB 12
8915 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE register field. */
8916 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE_MSB 14
8917 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE register field. */
8918 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE_WIDTH 3
8919 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE register field value. */
8920 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE_SET_MSK 0x00007000
8921 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE register field value. */
8922 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE_CLR_MSK 0xffff8fff
8923 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE register field is UNKNOWN. */
8924 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE_RESET 0x0
8925 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE field value from a register. */
8926 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE_GET(value) (((value) & 0x00007000) >> 12)
8927 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE register field value suitable for setting the register. */
8928 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE_SET(value) (((value) << 12) & 0x00007000)
8929 
8930 /*
8931  * Field : cfg_ctrl_in_protocol
8932  *
8933  * iohmc_ctrl_mmr_top_inst.cfg_ctrl_in_protocol
8934  *
8935  * Name:Control path Input interface protocol
8936  *
8937  * Description:1’b0 – AST , 1’b1 – AMM
8938  *
8939  * Field Access Macros:
8940  *
8941  */
8942 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL register field. */
8943 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL_LSB 15
8944 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL register field. */
8945 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL_MSB 15
8946 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL register field. */
8947 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL_WIDTH 1
8948 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL register field value. */
8949 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL_SET_MSK 0x00008000
8950 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL register field value. */
8951 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL_CLR_MSK 0xffff7fff
8952 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL register field is UNKNOWN. */
8953 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL_RESET 0x0
8954 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL field value from a register. */
8955 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL_GET(value) (((value) & 0x00008000) >> 15)
8956 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL register field value suitable for setting the register. */
8957 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL_SET(value) (((value) << 15) & 0x00008000)
8958 
8959 /*
8960  * Field : cfg_dbc0_in_protocol
8961  *
8962  * iohmc_ctrl_mmr_top_inst.cfg_dbc0_in_protocol
8963  *
8964  * Name:DBC0 Input interface protocol
8965  *
8966  * Description:1’b0 – AST , 1’b1 – AMM
8967  *
8968  * Field Access Macros:
8969  *
8970  */
8971 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL register field. */
8972 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL_LSB 16
8973 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL register field. */
8974 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL_MSB 16
8975 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL register field. */
8976 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL_WIDTH 1
8977 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL register field value. */
8978 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL_SET_MSK 0x00010000
8979 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL register field value. */
8980 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL_CLR_MSK 0xfffeffff
8981 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL register field is UNKNOWN. */
8982 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL_RESET 0x0
8983 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL field value from a register. */
8984 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL_GET(value) (((value) & 0x00010000) >> 16)
8985 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL register field value suitable for setting the register. */
8986 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL_SET(value) (((value) << 16) & 0x00010000)
8987 
8988 /*
8989  * Field : cfg_dbc1_in_protocol
8990  *
8991  * iohmc_ctrl_mmr_top_inst.cfg_dbc1_in_protocol
8992  *
8993  * Name:DBC1 Input interface protocol
8994  *
8995  * Description:1’b0 – AST , 1’b1 – AMM
8996  *
8997  * Field Access Macros:
8998  *
8999  */
9000 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL register field. */
9001 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL_LSB 17
9002 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL register field. */
9003 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL_MSB 17
9004 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL register field. */
9005 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL_WIDTH 1
9006 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL register field value. */
9007 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL_SET_MSK 0x00020000
9008 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL register field value. */
9009 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL_CLR_MSK 0xfffdffff
9010 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL register field is UNKNOWN. */
9011 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL_RESET 0x0
9012 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL field value from a register. */
9013 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL_GET(value) (((value) & 0x00020000) >> 17)
9014 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL register field value suitable for setting the register. */
9015 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL_SET(value) (((value) << 17) & 0x00020000)
9016 
9017 /*
9018  * Field : cfg_dbc2_in_protocol
9019  *
9020  * iohmc_ctrl_mmr_top_inst.cfg_dbc2_in_protocol
9021  *
9022  * Name:DBC2 Input interface protocol
9023  *
9024  * Description:1’b0 – AST , 1’b1 – AMM
9025  *
9026  * Field Access Macros:
9027  *
9028  */
9029 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL register field. */
9030 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL_LSB 18
9031 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL register field. */
9032 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL_MSB 18
9033 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL register field. */
9034 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL_WIDTH 1
9035 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL register field value. */
9036 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL_SET_MSK 0x00040000
9037 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL register field value. */
9038 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL_CLR_MSK 0xfffbffff
9039 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL register field is UNKNOWN. */
9040 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL_RESET 0x0
9041 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL field value from a register. */
9042 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL_GET(value) (((value) & 0x00040000) >> 18)
9043 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL register field value suitable for setting the register. */
9044 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL_SET(value) (((value) << 18) & 0x00040000)
9045 
9046 /*
9047  * Field : cfg_dbc3_in_protocol
9048  *
9049  * iohmc_ctrl_mmr_top_inst.cfg_dbc3_in_protocol
9050  *
9051  * Name:DBC3 Input interface protocol
9052  *
9053  * Description:1’b0 – AST , 1’b1 – AMM
9054  *
9055  * Field Access Macros:
9056  *
9057  */
9058 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL register field. */
9059 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL_LSB 19
9060 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL register field. */
9061 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL_MSB 19
9062 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL register field. */
9063 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL_WIDTH 1
9064 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL register field value. */
9065 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL_SET_MSK 0x00080000
9066 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL register field value. */
9067 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL_CLR_MSK 0xfff7ffff
9068 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL register field is UNKNOWN. */
9069 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL_RESET 0x0
9070 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL field value from a register. */
9071 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL_GET(value) (((value) & 0x00080000) >> 19)
9072 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL register field value suitable for setting the register. */
9073 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL_SET(value) (((value) << 19) & 0x00080000)
9074 
9075 /*
9076  * Field : cfg_ctrl_dualport_en
9077  *
9078  * iohmc_ctrl_mmr_top_inst.cfg_ctrl_dualport_en
9079  *
9080  * Name:Reserved
9081  *
9082  * Description:TBD
9083  *
9084  * Field Access Macros:
9085  *
9086  */
9087 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN register field. */
9088 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN_LSB 20
9089 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN register field. */
9090 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN_MSB 20
9091 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN register field. */
9092 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN_WIDTH 1
9093 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN register field value. */
9094 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN_SET_MSK 0x00100000
9095 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN register field value. */
9096 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN_CLR_MSK 0xffefffff
9097 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN register field is UNKNOWN. */
9098 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN_RESET 0x0
9099 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN field value from a register. */
9100 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN_GET(value) (((value) & 0x00100000) >> 20)
9101 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN register field value suitable for setting the register. */
9102 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN_SET(value) (((value) << 20) & 0x00100000)
9103 
9104 /*
9105  * Field : cfg_dbc0_dualport_en
9106  *
9107  * iohmc_ctrl_mmr_top_inst.cfg_dbc0_dualport_en
9108  *
9109  * Name:Reserved
9110  *
9111  * Description:TBD
9112  *
9113  * Field Access Macros:
9114  *
9115  */
9116 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN register field. */
9117 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN_LSB 21
9118 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN register field. */
9119 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN_MSB 21
9120 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN register field. */
9121 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN_WIDTH 1
9122 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN register field value. */
9123 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN_SET_MSK 0x00200000
9124 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN register field value. */
9125 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN_CLR_MSK 0xffdfffff
9126 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN register field is UNKNOWN. */
9127 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN_RESET 0x0
9128 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN field value from a register. */
9129 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN_GET(value) (((value) & 0x00200000) >> 21)
9130 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN register field value suitable for setting the register. */
9131 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN_SET(value) (((value) << 21) & 0x00200000)
9132 
9133 /*
9134  * Field : cfg_dbc1_dualport_en
9135  *
9136  * iohmc_ctrl_mmr_top_inst.cfg_dbc1_dualport_en
9137  *
9138  * Name:Reserved
9139  *
9140  * Description:TBD
9141  *
9142  * Field Access Macros:
9143  *
9144  */
9145 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN register field. */
9146 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN_LSB 22
9147 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN register field. */
9148 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN_MSB 22
9149 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN register field. */
9150 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN_WIDTH 1
9151 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN register field value. */
9152 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN_SET_MSK 0x00400000
9153 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN register field value. */
9154 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN_CLR_MSK 0xffbfffff
9155 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN register field is UNKNOWN. */
9156 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN_RESET 0x0
9157 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN field value from a register. */
9158 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN_GET(value) (((value) & 0x00400000) >> 22)
9159 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN register field value suitable for setting the register. */
9160 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN_SET(value) (((value) << 22) & 0x00400000)
9161 
9162 /*
9163  * Field : cfg_dbc2_dualport_en
9164  *
9165  * iohmc_ctrl_mmr_top_inst.cfg_dbc2_dualport_en
9166  *
9167  * Name:Reserved
9168  *
9169  * Description:TBD
9170  *
9171  * Field Access Macros:
9172  *
9173  */
9174 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN register field. */
9175 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN_LSB 23
9176 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN register field. */
9177 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN_MSB 23
9178 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN register field. */
9179 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN_WIDTH 1
9180 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN register field value. */
9181 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN_SET_MSK 0x00800000
9182 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN register field value. */
9183 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN_CLR_MSK 0xff7fffff
9184 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN register field is UNKNOWN. */
9185 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN_RESET 0x0
9186 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN field value from a register. */
9187 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN_GET(value) (((value) & 0x00800000) >> 23)
9188 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN register field value suitable for setting the register. */
9189 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN_SET(value) (((value) << 23) & 0x00800000)
9190 
9191 /*
9192  * Field : cfg_dbc3_dualport_en
9193  *
9194  * iohmc_ctrl_mmr_top_inst.cfg_dbc3_dualport_en
9195  *
9196  * Name:Reserved
9197  *
9198  * Description:TBD
9199  *
9200  * Field Access Macros:
9201  *
9202  */
9203 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN register field. */
9204 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN_LSB 24
9205 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN register field. */
9206 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN_MSB 24
9207 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN register field. */
9208 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN_WIDTH 1
9209 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN register field value. */
9210 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN_SET_MSK 0x01000000
9211 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN register field value. */
9212 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN_CLR_MSK 0xfeffffff
9213 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN register field is UNKNOWN. */
9214 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN_RESET 0x0
9215 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN field value from a register. */
9216 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN_GET(value) (((value) & 0x01000000) >> 24)
9217 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN register field value suitable for setting the register. */
9218 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN_SET(value) (((value) << 24) & 0x01000000)
9219 
9220 /*
9221  * Field : cfg_arbiter_type
9222  *
9223  * iohmc_ctrl_mmr_top_inst.cfg_arbiter_type
9224  *
9225  * Name:Arbiter Type
9226  *
9227  * Description:Indicates controller arbiter operating mode. Set this to:
9228  *
9229  * * 1’b0 for non-quasi (single cmd) mode
9230  *
9231  * * 1’b1 for quasi (dual cmd) mode
9232  *
9233  * Field Access Macros:
9234  *
9235  */
9236 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE register field. */
9237 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE_LSB 25
9238 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE register field. */
9239 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE_MSB 25
9240 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE register field. */
9241 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE_WIDTH 1
9242 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE register field value. */
9243 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE_SET_MSK 0x02000000
9244 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE register field value. */
9245 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE_CLR_MSK 0xfdffffff
9246 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE register field is UNKNOWN. */
9247 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE_RESET 0x0
9248 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE field value from a register. */
9249 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE_GET(value) (((value) & 0x02000000) >> 25)
9250 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE register field value suitable for setting the register. */
9251 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE_SET(value) (((value) << 25) & 0x02000000)
9252 
9253 /*
9254  * Field : cfg_open_page_en
9255  *
9256  * iohmc_ctrl_mmr_top_inst.cfg_open_page_en
9257  *
9258  * Name:Open Page Policy Enable
9259  *
9260  * Description:Set to 1 to enable the open page policy when command reordering is
9261  * disabled (cfg_cmd_reorder=0). This bit does not matter when cfg_cmd_reorder is
9262  * 1.
9263  *
9264  * Field Access Macros:
9265  *
9266  */
9267 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN register field. */
9268 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN_LSB 26
9269 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN register field. */
9270 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN_MSB 26
9271 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN register field. */
9272 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN_WIDTH 1
9273 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN register field value. */
9274 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN_SET_MSK 0x04000000
9275 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN register field value. */
9276 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN_CLR_MSK 0xfbffffff
9277 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN register field is UNKNOWN. */
9278 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN_RESET 0x0
9279 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN field value from a register. */
9280 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN_GET(value) (((value) & 0x04000000) >> 26)
9281 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN register field value suitable for setting the register. */
9282 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN_SET(value) (((value) << 26) & 0x04000000)
9283 
9284 /*
9285  * Field : cfg_geardn_en
9286  *
9287  * iohmc_ctrl_mmr_top_inst.cfg_geardn_en
9288  *
9289  * Name:Gear Down Mode Enable
9290  *
9291  * Description:Set to 1 to enable the gear down mode for DDR4
9292  *
9293  * Field Access Macros:
9294  *
9295  */
9296 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN register field. */
9297 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN_LSB 27
9298 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN register field. */
9299 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN_MSB 27
9300 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN register field. */
9301 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN_WIDTH 1
9302 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN register field value. */
9303 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN_SET_MSK 0x08000000
9304 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN register field value. */
9305 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN_CLR_MSK 0xf7ffffff
9306 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN register field is UNKNOWN. */
9307 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN_RESET 0x0
9308 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN field value from a register. */
9309 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN_GET(value) (((value) & 0x08000000) >> 27)
9310 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN register field value suitable for setting the register. */
9311 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN_SET(value) (((value) << 27) & 0x08000000)
9312 
9313 /*
9314  * Field : cfg_3dsref_ack_on_done
9315  *
9316  * iohmc_ctrl_mmr_top_inst.cfg_3dsref_ack_on_done
9317  *
9318  * Name:3DS Refresh Ack on Done
9319  *
9320  * Description:When set to 1, the ack pulse for 3DS Refresh is asserted when tRFC
9321  * has expired.
9322  *
9323  * When set to 0, the ack pulse for 3DS Refresh is asserted on the launch of
9324  * Refresh command to DRAM.
9325  *
9326  * Field Access Macros:
9327  *
9328  */
9329 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE register field. */
9330 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE_LSB 28
9331 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE register field. */
9332 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE_MSB 28
9333 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE register field. */
9334 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE_WIDTH 1
9335 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE register field value. */
9336 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE_SET_MSK 0x10000000
9337 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE register field value. */
9338 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE_CLR_MSK 0xefffffff
9339 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE register field is UNKNOWN. */
9340 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE_RESET 0x0
9341 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE field value from a register. */
9342 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE_GET(value) (((value) & 0x10000000) >> 28)
9343 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE register field value suitable for setting the register. */
9344 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE_SET(value) (((value) << 28) & 0x10000000)
9345 
9346 /*
9347  * Field : cfg_cb_memclk_gate_default
9348  *
9349  * iohmc_ctrl_mmr_top_inst.cfg_cb_memclk_gate_default
9350  *
9351  * Name:Memory Clock Gating Default Value Chicken Bit
9352  *
9353  * Description:When set to 0, both mem_ck/mem_ck_n are driven to LOW when clock
9354  * gating is enabled.
9355  *
9356  * When set to 1, mem_ck is driven to LOW and mem_ck_n is driven to HIGH when clock
9357  * gating is enabled.
9358  *
9359  * Field Access Macros:
9360  *
9361  */
9362 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT register field. */
9363 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT_LSB 30
9364 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT register field. */
9365 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT_MSB 30
9366 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT register field. */
9367 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT_WIDTH 1
9368 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT register field value. */
9369 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT_SET_MSK 0x40000000
9370 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT register field value. */
9371 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT_CLR_MSK 0xbfffffff
9372 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT register field is UNKNOWN. */
9373 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT_RESET 0x0
9374 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT field value from a register. */
9375 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT_GET(value) (((value) & 0x40000000) >> 30)
9376 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT register field value suitable for setting the register. */
9377 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT_SET(value) (((value) << 30) & 0x40000000)
9378 
9379 #ifndef __ASSEMBLY__
9380 /*
9381  * WARNING: The C register and register group struct declarations are provided for
9382  * convenience and illustrative purposes. They should, however, be used with
9383  * caution as the C language standard provides no guarantees about the alignment or
9384  * atomicity of device memory accesses. The recommended practice for coding device
9385  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9386  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9387  * alt_write_dword() functions for 64 bit registers.
9388  *
9389  * The struct declaration for register ALT_MPFE_IOHMC_REG_CTRLCFG3.
9390  */
9391 struct ALT_MPFE_IOHMC_REG_CTRLCFG3_s
9392 {
9393  volatile uint32_t cfg_ctrl_cmd_rate : 3; /* ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE */
9394  volatile uint32_t cfg_dbc0_cmd_rate : 3; /* ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE */
9395  volatile uint32_t cfg_dbc1_cmd_rate : 3; /* ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE */
9396  volatile uint32_t cfg_dbc2_cmd_rate : 3; /* ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE */
9397  volatile uint32_t cfg_dbc3_cmd_rate : 3; /* ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE */
9398  volatile uint32_t cfg_ctrl_in_protocol : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL */
9399  volatile uint32_t cfg_dbc0_in_protocol : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL */
9400  volatile uint32_t cfg_dbc1_in_protocol : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL */
9401  volatile uint32_t cfg_dbc2_in_protocol : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL */
9402  volatile uint32_t cfg_dbc3_in_protocol : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL */
9403  volatile uint32_t cfg_ctrl_dualport_en : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN */
9404  volatile uint32_t cfg_dbc0_dualport_en : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN */
9405  volatile uint32_t cfg_dbc1_dualport_en : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN */
9406  volatile uint32_t cfg_dbc2_dualport_en : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN */
9407  volatile uint32_t cfg_dbc3_dualport_en : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN */
9408  volatile uint32_t cfg_arbiter_type : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE */
9409  volatile uint32_t cfg_open_page_en : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN */
9410  volatile uint32_t cfg_geardn_en : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN */
9411  volatile uint32_t cfg_3dsref_ack_on_done : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE */
9412  uint32_t : 1; /* *UNDEFINED* */
9413  volatile uint32_t cfg_cb_memclk_gate_default : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT */
9414  uint32_t : 1; /* *UNDEFINED* */
9415 };
9416 
9417 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_CTRLCFG3. */
9418 typedef struct ALT_MPFE_IOHMC_REG_CTRLCFG3_s ALT_MPFE_IOHMC_REG_CTRLCFG3_t;
9419 #endif /* __ASSEMBLY__ */
9420 
9421 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG3 register. */
9422 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_RESET 0x00000000
9423 /* The byte offset of the ALT_MPFE_IOHMC_REG_CTRLCFG3 register from the beginning of the component. */
9424 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_OFST 0x34
9425 
9426 /*
9427  * Register : reg_ctrlcfg4
9428  *
9429  * Register Layout
9430  *
9431  * Bits | Access | Reset | Description
9432  * :--------|:-------|:--------|:----------------------------------------------------
9433  * [4:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID
9434  * [6:5] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE
9435  * [9:7] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN
9436  * [12:10] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN
9437  * [15:13] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN
9438  * [18:16] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN
9439  * [21:19] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN
9440  * [23:22] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET
9441  * [25:24] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET
9442  * [27:26] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET
9443  * [29:28] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET
9444  * [31:30] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET
9445  *
9446  */
9447 /*
9448  * Field : cfg_tile_id
9449  *
9450  * iohmc_ctrl_mmr_top_inst.cfg_tile_id[4:0]
9451  *
9452  * Name:Tile ID
9453  *
9454  * Description:Tile ID
9455  *
9456  * Field Access Macros:
9457  *
9458  */
9459 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID register field. */
9460 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID_LSB 0
9461 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID register field. */
9462 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID_MSB 4
9463 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID register field. */
9464 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID_WIDTH 5
9465 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID register field value. */
9466 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID_SET_MSK 0x0000001f
9467 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID register field value. */
9468 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID_CLR_MSK 0xffffffe0
9469 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID register field is UNKNOWN. */
9470 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID_RESET 0x0
9471 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID field value from a register. */
9472 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID_GET(value) (((value) & 0x0000001f) >> 0)
9473 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID register field value suitable for setting the register. */
9474 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID_SET(value) (((value) << 0) & 0x0000001f)
9475 
9476 /*
9477  * Field : cfg_pingpong_mode
9478  *
9479  * iohmc_ctrl_mmr_top_inst.cfg_pingpong_mode[1:0]
9480  *
9481  * Name:Ping Pong mode
9482  *
9483  * Description:Ping Pong mode: 2’b00 – Ping Pong support off, 2’b01 – Ping
9484  * Pong master0 (driving C/A pins), 2’b10 – Ping Pong master1.
9485  *
9486  * Field Access Macros:
9487  *
9488  */
9489 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE register field. */
9490 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE_LSB 5
9491 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE register field. */
9492 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE_MSB 6
9493 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE register field. */
9494 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE_WIDTH 2
9495 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE register field value. */
9496 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE_SET_MSK 0x00000060
9497 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE register field value. */
9498 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE_CLR_MSK 0xffffff9f
9499 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE register field is UNKNOWN. */
9500 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE_RESET 0x0
9501 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE field value from a register. */
9502 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE_GET(value) (((value) & 0x00000060) >> 5)
9503 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE register field value suitable for setting the register. */
9504 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE_SET(value) (((value) << 5) & 0x00000060)
9505 
9506 /*
9507  * Field : cfg_ctrl_slot_rotate_en
9508  *
9509  * iohmc_ctrl_mmr_top_inst.cfg_ctrl_slot_rotate_en[2:0]
9510  *
9511  * Name:Cmd Slot Rotate Enable
9512  *
9513  * Description:Cmd slot rotate enable: Bit[0] controls write, 1’b0 – disable
9514  * (fixed slot), 1’b1 – enable (allow cmd slot rotation). Bit[1] controls read,
9515  * 1’b0 – disable (fixed slot), 1’b1 – enable (allow cmd slot rotation).
9516  * Bit[2] controls always rotate. 1’b0 disabled (fixed slot), 1’b1 – enable
9517  * (always rotate cmd)
9518  *
9519  * Field Access Macros:
9520  *
9521  */
9522 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN register field. */
9523 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN_LSB 7
9524 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN register field. */
9525 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN_MSB 9
9526 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN register field. */
9527 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN_WIDTH 3
9528 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN register field value. */
9529 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN_SET_MSK 0x00000380
9530 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN register field value. */
9531 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN_CLR_MSK 0xfffffc7f
9532 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN register field is UNKNOWN. */
9533 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN_RESET 0x0
9534 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN field value from a register. */
9535 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN_GET(value) (((value) & 0x00000380) >> 7)
9536 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN register field value suitable for setting the register. */
9537 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN_SET(value) (((value) << 7) & 0x00000380)
9538 
9539 /*
9540  * Field : cfg_dbc0_slot_rotate_en
9541  *
9542  * iohmc_ctrl_mmr_top_inst.cfg_dbc0_slot_rotate_en[2:0]
9543  *
9544  * Name:DBC0 Slot Rotate Enable
9545  *
9546  * Description:DBC0 slot rotate enable: Bit[0] controls write, 1’b0 – disable
9547  * (fixed slot), 1’b1 – enable (allow cmd slot rotation). Bit[1] controls read,
9548  * 1’b0 – disable (fixed slot), 1’b1 – enable (allow cmd slot rotation).
9549  * Bit[2] controls always rotate, 1’b0 disabled (fixed slot), 1’b1 – enable
9550  * (always rotate cmd)
9551  *
9552  * Field Access Macros:
9553  *
9554  */
9555 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN register field. */
9556 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN_LSB 10
9557 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN register field. */
9558 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN_MSB 12
9559 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN register field. */
9560 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN_WIDTH 3
9561 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN register field value. */
9562 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN_SET_MSK 0x00001c00
9563 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN register field value. */
9564 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN_CLR_MSK 0xffffe3ff
9565 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN register field is UNKNOWN. */
9566 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN_RESET 0x0
9567 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN field value from a register. */
9568 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN_GET(value) (((value) & 0x00001c00) >> 10)
9569 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN register field value suitable for setting the register. */
9570 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN_SET(value) (((value) << 10) & 0x00001c00)
9571 
9572 /*
9573  * Field : cfg_dbc1_slot_rotate_en
9574  *
9575  * iohmc_ctrl_mmr_top_inst.cfg_dbc1_slot_rotate_en[2:0]
9576  *
9577  * Name:DBC1 Slot Rotate Enable
9578  *
9579  * Description:DBC1 slot rotate enable: Bit[0] controls write, 1’b0 – disable
9580  * (fixed slot), 1’b1 – enable (allow cmd slot rotation). Bit[1] controls read,
9581  * 1’b0 – disable (fixed slot), 1’b1 – enable (allow cmd slot rotation).
9582  * Bit[2] controls always rotate, 1’b0 disabled (fixed slot), 1’b1 – enable
9583  * (always rotate cmd)
9584  *
9585  * Field Access Macros:
9586  *
9587  */
9588 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN register field. */
9589 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN_LSB 13
9590 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN register field. */
9591 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN_MSB 15
9592 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN register field. */
9593 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN_WIDTH 3
9594 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN register field value. */
9595 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN_SET_MSK 0x0000e000
9596 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN register field value. */
9597 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN_CLR_MSK 0xffff1fff
9598 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN register field is UNKNOWN. */
9599 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN_RESET 0x0
9600 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN field value from a register. */
9601 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN_GET(value) (((value) & 0x0000e000) >> 13)
9602 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN register field value suitable for setting the register. */
9603 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN_SET(value) (((value) << 13) & 0x0000e000)
9604 
9605 /*
9606  * Field : cfg_dbc2_slot_rotate_en
9607  *
9608  * iohmc_ctrl_mmr_top_inst.cfg_dbc2_slot_rotate_en[2:0]
9609  *
9610  * Name:DBC2 Slot Rotate Enable
9611  *
9612  * Description:DBC2 slot rotate enable: Bit[0] controls write, 1’b0 – disable
9613  * (fixed slot), 1’b1 – enable (allow cmd slot rotation). Bit[1] controls read,
9614  * 1’b0 – disable (fixed slot), 1’b1 – enable (allow cmd slot rotation).
9615  * Bit[2] controls always rotate, 1’b0 disabled (fixed slot), 1’b1 – enable
9616  * (always rotate cmd)
9617  *
9618  * Field Access Macros:
9619  *
9620  */
9621 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN register field. */
9622 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN_LSB 16
9623 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN register field. */
9624 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN_MSB 18
9625 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN register field. */
9626 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN_WIDTH 3
9627 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN register field value. */
9628 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN_SET_MSK 0x00070000
9629 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN register field value. */
9630 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN_CLR_MSK 0xfff8ffff
9631 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN register field is UNKNOWN. */
9632 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN_RESET 0x0
9633 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN field value from a register. */
9634 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN_GET(value) (((value) & 0x00070000) >> 16)
9635 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN register field value suitable for setting the register. */
9636 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN_SET(value) (((value) << 16) & 0x00070000)
9637 
9638 /*
9639  * Field : cfg_dbc3_slot_rotate_en
9640  *
9641  * iohmc_ctrl_mmr_top_inst.cfg_dbc3_slot_rotate_en[2:0]
9642  *
9643  * Name:DBC3 Slot Rotate Enable
9644  *
9645  * Description:DBC3 slot rotate enable: Bit[0] controls write, 1’b0 – disable
9646  * (fixed slot), 1’b1 – enable (allow cmd slot rotation). Bit[1] controls read,
9647  * 1’b0 – disable (fixed slot), 1’b1 – enable (allow cmd slot rotation).
9648  * Bit[2] controls always rotate, 1’b0 disabled (fixed slot), 1’b1 – enable
9649  * (always rotate cmd)
9650  *
9651  * Field Access Macros:
9652  *
9653  */
9654 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN register field. */
9655 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN_LSB 19
9656 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN register field. */
9657 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN_MSB 21
9658 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN register field. */
9659 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN_WIDTH 3
9660 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN register field value. */
9661 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN_SET_MSK 0x00380000
9662 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN register field value. */
9663 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN_CLR_MSK 0xffc7ffff
9664 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN register field is UNKNOWN. */
9665 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN_RESET 0x0
9666 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN field value from a register. */
9667 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN_GET(value) (((value) & 0x00380000) >> 19)
9668 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN register field value suitable for setting the register. */
9669 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN_SET(value) (((value) << 19) & 0x00380000)
9670 
9671 /*
9672  * Field : cfg_ctrl_slot_offset
9673  *
9674  * iohmc_ctrl_mmr_top_inst.cfg_ctrl_slot_offset[1:0]
9675  *
9676  * Name:Cmd Slot Offset
9677  *
9678  * Description:Enables afi information to be offset by numbers of FR cycles.
9679  *
9680  * Affected afi signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid,
9681  * afi_dqs_burst, afi_mrnk_write and afi_mrnk_read.
9682  *
9683  * Set this to:
9684  *
9685  * * 2’b00 to have 0 FR cycle offset in HR and QR.
9686  *
9687  * * 2’b01 to have 1 FR cycle offset in QR.
9688  *
9689  * * 2’b10 to have ½ FR cycle offset in HR/QR.
9690  *
9691  * * 2’b11 to have 3 FR cycle offset in QR.
9692  *
9693  * Field Access Macros:
9694  *
9695  */
9696 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET register field. */
9697 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET_LSB 22
9698 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET register field. */
9699 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET_MSB 23
9700 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET register field. */
9701 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET_WIDTH 2
9702 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET register field value. */
9703 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET_SET_MSK 0x00c00000
9704 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET register field value. */
9705 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET_CLR_MSK 0xff3fffff
9706 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET register field is UNKNOWN. */
9707 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET_RESET 0x0
9708 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET field value from a register. */
9709 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET_GET(value) (((value) & 0x00c00000) >> 22)
9710 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET register field value suitable for setting the register. */
9711 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET_SET(value) (((value) << 22) & 0x00c00000)
9712 
9713 /*
9714  * Field : cfg_dbc0_slot_offset
9715  *
9716  * iohmc_ctrl_mmr_top_inst.cfg_dbc0_slot_offset[1:0]
9717  *
9718  * Name:DBC0 Cmd Slot Offset
9719  *
9720  * Description:Enables afi information to be offset by numbers of FR cycles.
9721  *
9722  * Affected afi signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid,
9723  * afi_dqs_burst, afi_mrnk_write and afi_mrnk_read.
9724  *
9725  * Set this to:
9726  *
9727  * * 2’b00 to have 0 FR cycle offset in HR and QR.
9728  *
9729  * * 2’b01 to have 1 FR cycle offset in QR.
9730  *
9731  * * 2’b10 to have ½ FR cycle offset in HR/QR.
9732  *
9733  * * 2’b11 to have 3 FR cycle offset in QR.
9734  *
9735  * Field Access Macros:
9736  *
9737  */
9738 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET register field. */
9739 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET_LSB 24
9740 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET register field. */
9741 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET_MSB 25
9742 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET register field. */
9743 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET_WIDTH 2
9744 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET register field value. */
9745 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET_SET_MSK 0x03000000
9746 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET register field value. */
9747 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET_CLR_MSK 0xfcffffff
9748 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET register field is UNKNOWN. */
9749 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET_RESET 0x0
9750 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET field value from a register. */
9751 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET_GET(value) (((value) & 0x03000000) >> 24)
9752 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET register field value suitable for setting the register. */
9753 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET_SET(value) (((value) << 24) & 0x03000000)
9754 
9755 /*
9756  * Field : cfg_dbc1_slot_offset
9757  *
9758  * iohmc_ctrl_mmr_top_inst.cfg_dbc1_slot_offset[1:0]
9759  *
9760  * Name:DBC1 Cmd Slot Offset
9761  *
9762  * Description:Enables afi information to be offset by numbers of FR cycles.
9763  *
9764  * Affected afi signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid,
9765  * afi_dqs_burst, afi_mrnk_write and afi_mrnk_read.
9766  *
9767  * Set this to:
9768  *
9769  * * 2’b00 to have 0 FR cycle offset in HR and QR.
9770  *
9771  * * 2’b01 to have 1 FR cycle offset in QR.
9772  *
9773  * * 2’b10 to have ½ FR cycle offset in HR/QR.
9774  *
9775  * * 2’b11 to have 3 FR cycle offset in QR.
9776  *
9777  * Field Access Macros:
9778  *
9779  */
9780 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET register field. */
9781 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET_LSB 26
9782 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET register field. */
9783 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET_MSB 27
9784 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET register field. */
9785 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET_WIDTH 2
9786 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET register field value. */
9787 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET_SET_MSK 0x0c000000
9788 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET register field value. */
9789 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET_CLR_MSK 0xf3ffffff
9790 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET register field is UNKNOWN. */
9791 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET_RESET 0x0
9792 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET field value from a register. */
9793 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET_GET(value) (((value) & 0x0c000000) >> 26)
9794 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET register field value suitable for setting the register. */
9795 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET_SET(value) (((value) << 26) & 0x0c000000)
9796 
9797 /*
9798  * Field : cfg_dbc2_slot_offset
9799  *
9800  * iohmc_ctrl_mmr_top_inst.cfg_dbc2_slot_offset[1:0]
9801  *
9802  * Name:DBC2 Cmd Slot Offset
9803  *
9804  * Description:Enables afi information to be offset by numbers of FR cycles.
9805  *
9806  * Affected afi signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid,
9807  * afi_dqs_burst, afi_mrnk_write and afi_mrnk_read.
9808  *
9809  * Set this to:
9810  *
9811  * * 2’b00 to have 0 FR cycle offset in HR and QR.
9812  *
9813  * * 2’b01 to have 1 FR cycle offset in QR.
9814  *
9815  * * 2’b10 to have ½ FR cycle offset in HR/QR.
9816  *
9817  * * 2’b11 to have 3 FR cycle offset in QR.
9818  *
9819  * Field Access Macros:
9820  *
9821  */
9822 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET register field. */
9823 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET_LSB 28
9824 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET register field. */
9825 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET_MSB 29
9826 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET register field. */
9827 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET_WIDTH 2
9828 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET register field value. */
9829 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET_SET_MSK 0x30000000
9830 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET register field value. */
9831 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET_CLR_MSK 0xcfffffff
9832 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET register field is UNKNOWN. */
9833 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET_RESET 0x0
9834 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET field value from a register. */
9835 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET_GET(value) (((value) & 0x30000000) >> 28)
9836 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET register field value suitable for setting the register. */
9837 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET_SET(value) (((value) << 28) & 0x30000000)
9838 
9839 /*
9840  * Field : cfg_dbc3_slot_offset
9841  *
9842  * iohmc_ctrl_mmr_top_inst.cfg_dbc3_slot_offset[1:0]
9843  *
9844  * Name:DBC3 Cmd Slot Offset
9845  *
9846  * Description:Enables afi information to be offset by numbers of FR cycles.
9847  *
9848  * Affected afi signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid,
9849  * afi_dqs_burst, afi_mrnk_write and afi_mrnk_read.
9850  *
9851  * Set this to:
9852  *
9853  * * 2’b00 to have 0 FR cycle offset in HR and QR.
9854  *
9855  * * 2’b01 to have 1 FR cycle offset in QR.
9856  *
9857  * * 2’b10 to have ½ FR cycle offset in HR/QR.
9858  *
9859  * * 2’b11 to have 3 FR cycle offset in QR.
9860  *
9861  * Field Access Macros:
9862  *
9863  */
9864 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET register field. */
9865 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET_LSB 30
9866 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET register field. */
9867 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET_MSB 31
9868 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET register field. */
9869 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET_WIDTH 2
9870 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET register field value. */
9871 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET_SET_MSK 0xc0000000
9872 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET register field value. */
9873 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET_CLR_MSK 0x3fffffff
9874 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET register field is UNKNOWN. */
9875 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET_RESET 0x0
9876 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET field value from a register. */
9877 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET_GET(value) (((value) & 0xc0000000) >> 30)
9878 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET register field value suitable for setting the register. */
9879 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET_SET(value) (((value) << 30) & 0xc0000000)
9880 
9881 #ifndef __ASSEMBLY__
9882 /*
9883  * WARNING: The C register and register group struct declarations are provided for
9884  * convenience and illustrative purposes. They should, however, be used with
9885  * caution as the C language standard provides no guarantees about the alignment or
9886  * atomicity of device memory accesses. The recommended practice for coding device
9887  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9888  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9889  * alt_write_dword() functions for 64 bit registers.
9890  *
9891  * The struct declaration for register ALT_MPFE_IOHMC_REG_CTRLCFG4.
9892  */
9893 struct ALT_MPFE_IOHMC_REG_CTRLCFG4_s
9894 {
9895  volatile uint32_t cfg_tile_id : 5; /* ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID */
9896  volatile uint32_t cfg_pingpong_mode : 2; /* ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE */
9897  volatile uint32_t cfg_ctrl_slot_rotate_en : 3; /* ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN */
9898  volatile uint32_t cfg_dbc0_slot_rotate_en : 3; /* ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN */
9899  volatile uint32_t cfg_dbc1_slot_rotate_en : 3; /* ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN */
9900  volatile uint32_t cfg_dbc2_slot_rotate_en : 3; /* ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN */
9901  volatile uint32_t cfg_dbc3_slot_rotate_en : 3; /* ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN */
9902  volatile uint32_t cfg_ctrl_slot_offset : 2; /* ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET */
9903  volatile uint32_t cfg_dbc0_slot_offset : 2; /* ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET */
9904  volatile uint32_t cfg_dbc1_slot_offset : 2; /* ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET */
9905  volatile uint32_t cfg_dbc2_slot_offset : 2; /* ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET */
9906  volatile uint32_t cfg_dbc3_slot_offset : 2; /* ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET */
9907 };
9908 
9909 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_CTRLCFG4. */
9910 typedef struct ALT_MPFE_IOHMC_REG_CTRLCFG4_s ALT_MPFE_IOHMC_REG_CTRLCFG4_t;
9911 #endif /* __ASSEMBLY__ */
9912 
9913 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG4 register. */
9914 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_RESET 0x00000000
9915 /* The byte offset of the ALT_MPFE_IOHMC_REG_CTRLCFG4 register from the beginning of the component. */
9916 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_OFST 0x38
9917 
9918 /*
9919  * Register : reg_ctrlcfg5
9920  *
9921  * Register Layout
9922  *
9923  * Bits | Access | Reset | Description
9924  * :--------|:-------|:--------|:---------------------------------------------
9925  * [3:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT
9926  * [7:4] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT
9927  * [8] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN
9928  * [9] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN
9929  * [10] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN
9930  * [11] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN
9931  * [12] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN
9932  * [31:13] | ??? | Unknown | *UNDEFINED*
9933  *
9934  */
9935 /*
9936  * Field : cfg_col_cmd_slot
9937  *
9938  * iohmc_ctrl_mmr_top_inst.cfg_col_cmd_slot[3:0]
9939  *
9940  * Name:Column Cmd Slot
9941  *
9942  * Description:Specify the col cmd slot. One hot encoding.
9943  *
9944  * Field Access Macros:
9945  *
9946  */
9947 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT register field. */
9948 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT_LSB 0
9949 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT register field. */
9950 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT_MSB 3
9951 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT register field. */
9952 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT_WIDTH 4
9953 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT register field value. */
9954 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT_SET_MSK 0x0000000f
9955 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT register field value. */
9956 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT_CLR_MSK 0xfffffff0
9957 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT register field is UNKNOWN. */
9958 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT_RESET 0x0
9959 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT field value from a register. */
9960 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT_GET(value) (((value) & 0x0000000f) >> 0)
9961 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT register field value suitable for setting the register. */
9962 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT_SET(value) (((value) << 0) & 0x0000000f)
9963 
9964 /*
9965  * Field : cfg_row_cmd_slot
9966  *
9967  * iohmc_ctrl_mmr_top_inst.cfg_row_cmd_slot[3:0]
9968  *
9969  * Name:Row Cmd Slot
9970  *
9971  * Description:Specify the row cmd slot. One hot encoding.
9972  *
9973  * Field Access Macros:
9974  *
9975  */
9976 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT register field. */
9977 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT_LSB 4
9978 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT register field. */
9979 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT_MSB 7
9980 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT register field. */
9981 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT_WIDTH 4
9982 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT register field value. */
9983 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT_SET_MSK 0x000000f0
9984 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT register field value. */
9985 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT_CLR_MSK 0xffffff0f
9986 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT register field is UNKNOWN. */
9987 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT_RESET 0x0
9988 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT field value from a register. */
9989 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT_GET(value) (((value) & 0x000000f0) >> 4)
9990 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT register field value suitable for setting the register. */
9991 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT_SET(value) (((value) << 4) & 0x000000f0)
9992 
9993 /*
9994  * Field : cfg_ctrl_rc_en
9995  *
9996  * iohmc_ctrl_mmr_top_inst.cfg_ctrl_rc_en
9997  *
9998  * Name:Control Path Rate Conversion Enable
9999  *
10000  * Description:Set to 1 to enable the rate conversion. It converts QR input from
10001  * core to HR inside HMC
10002  *
10003  * Field Access Macros:
10004  *
10005  */
10006 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN register field. */
10007 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN_LSB 8
10008 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN register field. */
10009 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN_MSB 8
10010 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN register field. */
10011 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN_WIDTH 1
10012 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN register field value. */
10013 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN_SET_MSK 0x00000100
10014 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN register field value. */
10015 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN_CLR_MSK 0xfffffeff
10016 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN register field is UNKNOWN. */
10017 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN_RESET 0x0
10018 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN field value from a register. */
10019 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN_GET(value) (((value) & 0x00000100) >> 8)
10020 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN register field value suitable for setting the register. */
10021 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN_SET(value) (((value) << 8) & 0x00000100)
10022 
10023 /*
10024  * Field : cfg_dbc0_rc_en
10025  *
10026  * iohmc_ctrl_mmr_top_inst.cfg_dbc0_rc_en
10027  *
10028  * Name:DBC0 Rate Conversion Enable
10029  *
10030  * Description:Set to 1 to enable the rate conversion. It converts QR input from
10031  * core to HR inside HMC
10032  *
10033  * Field Access Macros:
10034  *
10035  */
10036 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN register field. */
10037 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN_LSB 9
10038 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN register field. */
10039 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN_MSB 9
10040 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN register field. */
10041 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN_WIDTH 1
10042 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN register field value. */
10043 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN_SET_MSK 0x00000200
10044 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN register field value. */
10045 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN_CLR_MSK 0xfffffdff
10046 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN register field is UNKNOWN. */
10047 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN_RESET 0x0
10048 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN field value from a register. */
10049 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN_GET(value) (((value) & 0x00000200) >> 9)
10050 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN register field value suitable for setting the register. */
10051 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN_SET(value) (((value) << 9) & 0x00000200)
10052 
10053 /*
10054  * Field : cfg_dbc1_rc_en
10055  *
10056  * iohmc_ctrl_mmr_top_inst.cfg_dbc1_rc_en
10057  *
10058  * Name:DBC1 Rate Conversion Enable
10059  *
10060  * Description:Set to 1 to enable the rate conversion. It converts QR input from
10061  * core to HR inside HMC
10062  *
10063  * Field Access Macros:
10064  *
10065  */
10066 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN register field. */
10067 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN_LSB 10
10068 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN register field. */
10069 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN_MSB 10
10070 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN register field. */
10071 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN_WIDTH 1
10072 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN register field value. */
10073 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN_SET_MSK 0x00000400
10074 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN register field value. */
10075 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN_CLR_MSK 0xfffffbff
10076 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN register field is UNKNOWN. */
10077 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN_RESET 0x0
10078 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN field value from a register. */
10079 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN_GET(value) (((value) & 0x00000400) >> 10)
10080 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN register field value suitable for setting the register. */
10081 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN_SET(value) (((value) << 10) & 0x00000400)
10082 
10083 /*
10084  * Field : cfg_dbc2_rc_en
10085  *
10086  * iohmc_ctrl_mmr_top_inst.cfg_dbc2_rc_en
10087  *
10088  * Name:DBC2 Rate Conversion Enable
10089  *
10090  * Description:Set to 1 to enable the rate conversion. It converts QR input from
10091  * core to HR inside HMC
10092  *
10093  * Field Access Macros:
10094  *
10095  */
10096 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN register field. */
10097 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN_LSB 11
10098 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN register field. */
10099 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN_MSB 11
10100 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN register field. */
10101 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN_WIDTH 1
10102 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN register field value. */
10103 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN_SET_MSK 0x00000800
10104 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN register field value. */
10105 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN_CLR_MSK 0xfffff7ff
10106 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN register field is UNKNOWN. */
10107 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN_RESET 0x0
10108 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN field value from a register. */
10109 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN_GET(value) (((value) & 0x00000800) >> 11)
10110 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN register field value suitable for setting the register. */
10111 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN_SET(value) (((value) << 11) & 0x00000800)
10112 
10113 /*
10114  * Field : cfg_dbc3_rc_en
10115  *
10116  * iohmc_ctrl_mmr_top_inst.cfg_dbc3_rc_en
10117  *
10118  * Name:DBC3 Rate Conversion Enable
10119  *
10120  * Description:Set to 1 to enable the rate conversion. It converts QR input from
10121  * core to HR inside HMC
10122  *
10123  * Field Access Macros:
10124  *
10125  */
10126 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN register field. */
10127 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN_LSB 12
10128 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN register field. */
10129 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN_MSB 12
10130 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN register field. */
10131 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN_WIDTH 1
10132 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN register field value. */
10133 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN_SET_MSK 0x00001000
10134 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN register field value. */
10135 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN_CLR_MSK 0xffffefff
10136 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN register field is UNKNOWN. */
10137 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN_RESET 0x0
10138 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN field value from a register. */
10139 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN_GET(value) (((value) & 0x00001000) >> 12)
10140 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN register field value suitable for setting the register. */
10141 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN_SET(value) (((value) << 12) & 0x00001000)
10142 
10143 #ifndef __ASSEMBLY__
10144 /*
10145  * WARNING: The C register and register group struct declarations are provided for
10146  * convenience and illustrative purposes. They should, however, be used with
10147  * caution as the C language standard provides no guarantees about the alignment or
10148  * atomicity of device memory accesses. The recommended practice for coding device
10149  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10150  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10151  * alt_write_dword() functions for 64 bit registers.
10152  *
10153  * The struct declaration for register ALT_MPFE_IOHMC_REG_CTRLCFG5.
10154  */
10155 struct ALT_MPFE_IOHMC_REG_CTRLCFG5_s
10156 {
10157  volatile uint32_t cfg_col_cmd_slot : 4; /* ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT */
10158  volatile uint32_t cfg_row_cmd_slot : 4; /* ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT */
10159  volatile uint32_t cfg_ctrl_rc_en : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN */
10160  volatile uint32_t cfg_dbc0_rc_en : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN */
10161  volatile uint32_t cfg_dbc1_rc_en : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN */
10162  volatile uint32_t cfg_dbc2_rc_en : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN */
10163  volatile uint32_t cfg_dbc3_rc_en : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN */
10164  uint32_t : 19; /* *UNDEFINED* */
10165 };
10166 
10167 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_CTRLCFG5. */
10168 typedef struct ALT_MPFE_IOHMC_REG_CTRLCFG5_s ALT_MPFE_IOHMC_REG_CTRLCFG5_t;
10169 #endif /* __ASSEMBLY__ */
10170 
10171 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG5 register. */
10172 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_RESET 0x00000000
10173 /* The byte offset of the ALT_MPFE_IOHMC_REG_CTRLCFG5 register from the beginning of the component. */
10174 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_OFST 0x3c
10175 
10176 /*
10177  * Register : reg_ctrlcfg6
10178  *
10179  * Register Layout
10180  *
10181  * Bits | Access | Reset | Description
10182  * :--------|:-------|:--------|:----------------------------------------
10183  * [15:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP
10184  * [31:16] | ??? | Unknown | *UNDEFINED*
10185  *
10186  */
10187 /*
10188  * Field : cfg_cs_chip
10189  *
10190  * iohmc_ctrl_mmr_top_inst.cfg_cs_chip[15:0]
10191  *
10192  * Name:CS to Chip Mapping
10193  *
10194  * Description:Chip select mapping scheme.
10195  *
10196  * Mapping separated into 4 sections: [CS3][CS2][CS1][CS0]
10197  *
10198  * Each section consists of 4 bits to indicate which CS_n signal should be active
10199  * when command goes to current CS.
10200  *
10201  * Eg: if we set to 16’b0000_0000_0010_0001, CS_n signal will be active on CS0
10202  * and CS1 when command occurs on CS0 and CS1 respectively.
10203  *
10204  * Default value should be 16’b1000_0100_0010_0001, only change it for RDIMM
10205  * single rank design where each RDIMM have 2 CS_n signal but only one is used for
10206  * actual memory access, one more CS_n bit for RDIMM control word access.
10207  *
10208  * Field Access Macros:
10209  *
10210  */
10211 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP register field. */
10212 #define ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP_LSB 0
10213 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP register field. */
10214 #define ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP_MSB 15
10215 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP register field. */
10216 #define ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP_WIDTH 16
10217 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP register field value. */
10218 #define ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP_SET_MSK 0x0000ffff
10219 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP register field value. */
10220 #define ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP_CLR_MSK 0xffff0000
10221 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP register field is UNKNOWN. */
10222 #define ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP_RESET 0x0
10223 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP field value from a register. */
10224 #define ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP_GET(value) (((value) & 0x0000ffff) >> 0)
10225 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP register field value suitable for setting the register. */
10226 #define ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP_SET(value) (((value) << 0) & 0x0000ffff)
10227 
10228 #ifndef __ASSEMBLY__
10229 /*
10230  * WARNING: The C register and register group struct declarations are provided for
10231  * convenience and illustrative purposes. They should, however, be used with
10232  * caution as the C language standard provides no guarantees about the alignment or
10233  * atomicity of device memory accesses. The recommended practice for coding device
10234  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10235  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10236  * alt_write_dword() functions for 64 bit registers.
10237  *
10238  * The struct declaration for register ALT_MPFE_IOHMC_REG_CTRLCFG6.
10239  */
10240 struct ALT_MPFE_IOHMC_REG_CTRLCFG6_s
10241 {
10242  volatile uint32_t cfg_cs_chip : 16; /* ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP */
10243  uint32_t : 16; /* *UNDEFINED* */
10244 };
10245 
10246 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_CTRLCFG6. */
10247 typedef struct ALT_MPFE_IOHMC_REG_CTRLCFG6_s ALT_MPFE_IOHMC_REG_CTRLCFG6_t;
10248 #endif /* __ASSEMBLY__ */
10249 
10250 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG6 register. */
10251 #define ALT_MPFE_IOHMC_REG_CTRLCFG6_RESET 0x00000000
10252 /* The byte offset of the ALT_MPFE_IOHMC_REG_CTRLCFG6 register from the beginning of the component. */
10253 #define ALT_MPFE_IOHMC_REG_CTRLCFG6_OFST 0x40
10254 
10255 /*
10256  * Register : reg_ctrlcfg7
10257  *
10258  * Register Layout
10259  *
10260  * Bits | Access | Reset | Description
10261  * :--------|:-------|:--------|:------------------------------------------------
10262  * [0] | ??? | Unknown | *UNDEFINED*
10263  * [7:1] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY
10264  * [14:8] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY
10265  * [31:15] | ??? | Unknown | *UNDEFINED*
10266  *
10267  */
10268 /*
10269  * Field : cfg_rb_backup_entry
10270  *
10271  * iohmc_ctrl_mmr_top_inst.cfg_rb_reserved_entry[6:0]
10272  *
10273  * Name:Number of Reserved Entries in Read Buffer
10274  *
10275  * Description:Specify how many entries are reserved in read buffer before almost
10276  * full is asserted.
10277  *
10278  * Field Access Macros:
10279  *
10280  */
10281 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY register field. */
10282 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY_LSB 1
10283 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY register field. */
10284 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY_MSB 7
10285 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY register field. */
10286 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY_WIDTH 7
10287 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY register field value. */
10288 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY_SET_MSK 0x000000fe
10289 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY register field value. */
10290 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY_CLR_MSK 0xffffff01
10291 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY register field is UNKNOWN. */
10292 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY_RESET 0x0
10293 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY field value from a register. */
10294 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY_GET(value) (((value) & 0x000000fe) >> 1)
10295 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY register field value suitable for setting the register. */
10296 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY_SET(value) (((value) << 1) & 0x000000fe)
10297 
10298 /*
10299  * Field : cfg_wb_backup_entry
10300  *
10301  * iohmc_ctrl_mmr_top_inst.cfg_wb_reserved_entry[6:0]
10302  *
10303  * Name:Number of Reserved Entries in Write Buffer
10304  *
10305  * Description:Specify how many entries are reserved in write buffer before almost
10306  * full is asserted.
10307  *
10308  * Field Access Macros:
10309  *
10310  */
10311 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY register field. */
10312 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY_LSB 8
10313 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY register field. */
10314 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY_MSB 14
10315 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY register field. */
10316 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY_WIDTH 7
10317 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY register field value. */
10318 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY_SET_MSK 0x00007f00
10319 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY register field value. */
10320 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY_CLR_MSK 0xffff80ff
10321 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY register field is UNKNOWN. */
10322 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY_RESET 0x0
10323 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY field value from a register. */
10324 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY_GET(value) (((value) & 0x00007f00) >> 8)
10325 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY register field value suitable for setting the register. */
10326 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY_SET(value) (((value) << 8) & 0x00007f00)
10327 
10328 #ifndef __ASSEMBLY__
10329 /*
10330  * WARNING: The C register and register group struct declarations are provided for
10331  * convenience and illustrative purposes. They should, however, be used with
10332  * caution as the C language standard provides no guarantees about the alignment or
10333  * atomicity of device memory accesses. The recommended practice for coding device
10334  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10335  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10336  * alt_write_dword() functions for 64 bit registers.
10337  *
10338  * The struct declaration for register ALT_MPFE_IOHMC_REG_CTRLCFG7.
10339  */
10340 struct ALT_MPFE_IOHMC_REG_CTRLCFG7_s
10341 {
10342  uint32_t : 1; /* *UNDEFINED* */
10343  volatile uint32_t cfg_rb_backup_entry : 7; /* ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY */
10344  volatile uint32_t cfg_wb_backup_entry : 7; /* ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY */
10345  uint32_t : 17; /* *UNDEFINED* */
10346 };
10347 
10348 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_CTRLCFG7. */
10349 typedef struct ALT_MPFE_IOHMC_REG_CTRLCFG7_s ALT_MPFE_IOHMC_REG_CTRLCFG7_t;
10350 #endif /* __ASSEMBLY__ */
10351 
10352 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG7 register. */
10353 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_RESET 0x00000000
10354 /* The byte offset of the ALT_MPFE_IOHMC_REG_CTRLCFG7 register from the beginning of the component. */
10355 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_OFST 0x44
10356 
10357 /*
10358  * Register : reg_ctrlcfg8
10359  *
10360  * Register Layout
10361  *
10362  * Bits | Access | Reset | Description
10363  * :-------|:-------|:--------|:---------------------------------------
10364  * [0] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN
10365  * [1] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV
10366  * [31:2] | ??? | Unknown | *UNDEFINED*
10367  *
10368  */
10369 /*
10370  * Field : cfg_3ds_en
10371  *
10372  * iohmc_ctrl_mmr_top_inst.cfg_3ds_en
10373  *
10374  * Name:3DS Mode Enable
10375  *
10376  * Description:1’b0: Disable 3DS Logic
10377  *
10378  * 1’b1: Enable 3DS Logic
10379  *
10380  * Field Access Macros:
10381  *
10382  */
10383 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN register field. */
10384 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN_LSB 0
10385 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN register field. */
10386 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN_MSB 0
10387 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN register field. */
10388 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN_WIDTH 1
10389 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN register field value. */
10390 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN_SET_MSK 0x00000001
10391 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN register field value. */
10392 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN_CLR_MSK 0xfffffffe
10393 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN register field is UNKNOWN. */
10394 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN_RESET 0x0
10395 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN field value from a register. */
10396 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN_GET(value) (((value) & 0x00000001) >> 0)
10397 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN register field value suitable for setting the register. */
10398 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN_SET(value) (((value) << 0) & 0x00000001)
10399 
10400 /*
10401  * Field : cfg_ck_inv
10402  *
10403  * iohmc_ctrl_mmr_top_inst.cfg_ck_inv
10404  *
10405  * Name:Invert CK polarity
10406  *
10407  * Description:Use to program CK polarity.
10408  *
10409  * 1’b0: 10101010, 1’b1: 01010101
10410  *
10411  * Field Access Macros:
10412  *
10413  */
10414 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV register field. */
10415 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV_LSB 1
10416 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV register field. */
10417 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV_MSB 1
10418 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV register field. */
10419 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV_WIDTH 1
10420 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV register field value. */
10421 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV_SET_MSK 0x00000002
10422 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV register field value. */
10423 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV_CLR_MSK 0xfffffffd
10424 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV register field is UNKNOWN. */
10425 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV_RESET 0x0
10426 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV field value from a register. */
10427 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV_GET(value) (((value) & 0x00000002) >> 1)
10428 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV register field value suitable for setting the register. */
10429 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV_SET(value) (((value) << 1) & 0x00000002)
10430 
10431 #ifndef __ASSEMBLY__
10432 /*
10433  * WARNING: The C register and register group struct declarations are provided for
10434  * convenience and illustrative purposes. They should, however, be used with
10435  * caution as the C language standard provides no guarantees about the alignment or
10436  * atomicity of device memory accesses. The recommended practice for coding device
10437  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10438  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10439  * alt_write_dword() functions for 64 bit registers.
10440  *
10441  * The struct declaration for register ALT_MPFE_IOHMC_REG_CTRLCFG8.
10442  */
10443 struct ALT_MPFE_IOHMC_REG_CTRLCFG8_s
10444 {
10445  volatile uint32_t cfg_3ds_en : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN */
10446  volatile uint32_t cfg_ck_inv : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV */
10447  uint32_t : 30; /* *UNDEFINED* */
10448 };
10449 
10450 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_CTRLCFG8. */
10451 typedef struct ALT_MPFE_IOHMC_REG_CTRLCFG8_s ALT_MPFE_IOHMC_REG_CTRLCFG8_t;
10452 #endif /* __ASSEMBLY__ */
10453 
10454 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG8 register. */
10455 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_RESET 0x00000000
10456 /* The byte offset of the ALT_MPFE_IOHMC_REG_CTRLCFG8 register from the beginning of the component. */
10457 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_OFST 0x48
10458 
10459 /*
10460  * Register : reg_ctrlcfg9
10461  *
10462  * Register Layout
10463  *
10464  * Bits | Access | Reset | Description
10465  * :-------|:-------|:--------|:----------------------------------------------
10466  * [0] | RW | Unknown | ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN
10467  * [31:1] | ??? | Unknown | *UNDEFINED*
10468  *
10469  */
10470 /*
10471  * Field : cfg_dfx_bypass_en
10472  *
10473  * iohmc_ctrl_mmr_top_inst.cfg_dfx_bypass_en
10474  *
10475  * Name:DFX Bypass Mode Enable
10476  *
10477  * Description:Used for dft and timing characterization only.
10478  *
10479  * 1’b0: Normal functional mode, 1’b1: DFX bypass mode.
10480  *
10481  * Field Access Macros:
10482  *
10483  */
10484 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN register field. */
10485 #define ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN_LSB 0
10486 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN register field. */
10487 #define ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN_MSB 0
10488 /* The width in bits of the ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN register field. */
10489 #define ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN_WIDTH 1
10490 /* The mask used to set the ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN register field value. */
10491 #define ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN_SET_MSK 0x00000001
10492 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN register field value. */
10493 #define ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN_CLR_MSK 0xfffffffe
10494 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN register field is UNKNOWN. */
10495 #define ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN_RESET 0x0
10496 /* Extracts the ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN field value from a register. */
10497 #define ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN_GET(value) (((value) & 0x00000001) >> 0)
10498 /* Produces a ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN register field value suitable for setting the register. */
10499 #define ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN_SET(value) (((value) << 0) & 0x00000001)
10500 
10501 #ifndef __ASSEMBLY__
10502 /*
10503  * WARNING: The C register and register group struct declarations are provided for
10504  * convenience and illustrative purposes. They should, however, be used with
10505  * caution as the C language standard provides no guarantees about the alignment or
10506  * atomicity of device memory accesses. The recommended practice for coding device
10507  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10508  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10509  * alt_write_dword() functions for 64 bit registers.
10510  *
10511  * The struct declaration for register ALT_MPFE_IOHMC_REG_CTRLCFG9.
10512  */
10513 struct ALT_MPFE_IOHMC_REG_CTRLCFG9_s
10514 {
10515  volatile uint32_t cfg_dfx_bypass_en : 1; /* ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN */
10516  uint32_t : 31; /* *UNDEFINED* */
10517 };
10518 
10519 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_CTRLCFG9. */
10520 typedef struct ALT_MPFE_IOHMC_REG_CTRLCFG9_s ALT_MPFE_IOHMC_REG_CTRLCFG9_t;
10521 #endif /* __ASSEMBLY__ */
10522 
10523 /* The reset value of the ALT_MPFE_IOHMC_REG_CTRLCFG9 register. */
10524 #define ALT_MPFE_IOHMC_REG_CTRLCFG9_RESET 0x00000000
10525 /* The byte offset of the ALT_MPFE_IOHMC_REG_CTRLCFG9 register from the beginning of the component. */
10526 #define ALT_MPFE_IOHMC_REG_CTRLCFG9_OFST 0x4c
10527 
10528 /*
10529  * Register : reg_dramtiming0
10530  *
10531  * Register Layout
10532  *
10533  * Bits | Access | Reset | Description
10534  * :--------|:-------|:--------|:----------------------------------------------------------------
10535  * [6:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL
10536  * [12:7] | RW | Unknown | ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES
10537  * [18:13] | RW | Unknown | ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES
10538  * [31:19] | ??? | Unknown | *UNDEFINED*
10539  *
10540  */
10541 /*
10542  * Field : cfg_tcl
10543  *
10544  * iohmc_ctrl_mmr_top_inst.cfg_tcl[6:0]
10545  *
10546  * Name:CAS Read Latency
10547  *
10548  * Description:Memory read latency.
10549  *
10550  * Field Access Macros:
10551  *
10552  */
10553 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL register field. */
10554 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL_LSB 0
10555 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL register field. */
10556 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL_MSB 6
10557 /* The width in bits of the ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL register field. */
10558 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL_WIDTH 7
10559 /* The mask used to set the ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL register field value. */
10560 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL_SET_MSK 0x0000007f
10561 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL register field value. */
10562 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL_CLR_MSK 0xffffff80
10563 /* The reset value of the ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL register field is UNKNOWN. */
10564 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL_RESET 0x0
10565 /* Extracts the ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL field value from a register. */
10566 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL_GET(value) (((value) & 0x0000007f) >> 0)
10567 /* Produces a ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL register field value suitable for setting the register. */
10568 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL_SET(value) (((value) << 0) & 0x0000007f)
10569 
10570 /*
10571  * Field : cfg_power_saving_exit_cycles
10572  *
10573  * iohmc_ctrl_mmr_top_inst.cfg_power_saving_exit_cycles[5:0]
10574  *
10575  * Name:Minimum Low Power State Cycles
10576  *
10577  * Description:The minimum number of cycles to stay in a low power state. This
10578  * applies to both power down and self-refresh and should be set to the greater of
10579  * tPD and tCKESR.
10580  *
10581  * Field Access Macros:
10582  *
10583  */
10584 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES register field. */
10585 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_LSB 7
10586 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES register field. */
10587 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_MSB 12
10588 /* The width in bits of the ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES register field. */
10589 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_WIDTH 6
10590 /* The mask used to set the ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES register field value. */
10591 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_SET_MSK 0x00001f80
10592 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES register field value. */
10593 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_CLR_MSK 0xffffe07f
10594 /* The reset value of the ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES register field is UNKNOWN. */
10595 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_RESET 0x0
10596 /* Extracts the ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES field value from a register. */
10597 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_GET(value) (((value) & 0x00001f80) >> 7)
10598 /* Produces a ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES register field value suitable for setting the register. */
10599 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_SET(value) (((value) << 7) & 0x00001f80)
10600 
10601 /*
10602  * Field : cfg_mem_clk_disable_entry_cycles
10603  *
10604  * iohmc_ctrl_mmr_top_inst.cfg_mem_clk_disable_entry_cycles[5:0]
10605  *
10606  * Name:Clock Disable Delay Cycles
10607  *
10608  * Description:Set to a the number of clocks after the execution of an self-refresh
10609  * to stop the clock. This register is generally set based on PHY design latency
10610  * and should generally not be changed.
10611  *
10612  * Field Access Macros:
10613  *
10614  */
10615 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES register field. */
10616 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES_LSB 13
10617 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES register field. */
10618 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES_MSB 18
10619 /* The width in bits of the ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES register field. */
10620 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES_WIDTH 6
10621 /* The mask used to set the ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES register field value. */
10622 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES_SET_MSK 0x0007e000
10623 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES register field value. */
10624 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES_CLR_MSK 0xfff81fff
10625 /* The reset value of the ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES register field is UNKNOWN. */
10626 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES_RESET 0x0
10627 /* Extracts the ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES field value from a register. */
10628 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES_GET(value) (((value) & 0x0007e000) >> 13)
10629 /* Produces a ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES register field value suitable for setting the register. */
10630 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES_SET(value) (((value) << 13) & 0x0007e000)
10631 
10632 #ifndef __ASSEMBLY__
10633 /*
10634  * WARNING: The C register and register group struct declarations are provided for
10635  * convenience and illustrative purposes. They should, however, be used with
10636  * caution as the C language standard provides no guarantees about the alignment or
10637  * atomicity of device memory accesses. The recommended practice for coding device
10638  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10639  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10640  * alt_write_dword() functions for 64 bit registers.
10641  *
10642  * The struct declaration for register ALT_MPFE_IOHMC_REG_DRAMTIMING0.
10643  */
10644 struct ALT_MPFE_IOHMC_REG_DRAMTIMING0_s
10645 {
10646  volatile uint32_t cfg_tcl : 7; /* ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL */
10647  volatile uint32_t cfg_power_saving_exit_cycles : 6; /* ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES */
10648  volatile uint32_t cfg_mem_clk_disable_entry_cycles : 6; /* ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES */
10649  uint32_t : 13; /* *UNDEFINED* */
10650 };
10651 
10652 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_DRAMTIMING0. */
10653 typedef struct ALT_MPFE_IOHMC_REG_DRAMTIMING0_s ALT_MPFE_IOHMC_REG_DRAMTIMING0_t;
10654 #endif /* __ASSEMBLY__ */
10655 
10656 /* The reset value of the ALT_MPFE_IOHMC_REG_DRAMTIMING0 register. */
10657 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_RESET 0x00000000
10658 /* The byte offset of the ALT_MPFE_IOHMC_REG_DRAMTIMING0 register from the beginning of the component. */
10659 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_OFST 0x50
10660 
10661 /*
10662  * Register : reg_dramodt0
10663  *
10664  * Register Layout
10665  *
10666  * Bits | Access | Reset | Description
10667  * :--------|:-------|:--------|:-----------------------------------------------
10668  * [15:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP
10669  * [31:16] | RW | Unknown | ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP
10670  *
10671  */
10672 /*
10673  * Field : cfg_write_odt_chip
10674  *
10675  * iohmc_ctrl_mmr_top_inst.cfg_write_odt_chip[15:0]
10676  *
10677  * Name:Write ODT Control
10678  *
10679  * Description:ODT scheme setting for write command.
10680  *
10681  * Setting separated into 4 sections: [CS3][CS2][CS1][CS0]
10682  *
10683  * Each section consists of 4 bits to indicate which chip should ODT be asserted
10684  * when write occurs on current CS.
10685  *
10686  * Eg: if we set to 16’b0000_0000_0010_0001, ODT will be asserted to chip0 and
10687  * chip1 when write occurs to CS0 and CS1 respectively.
10688  *
10689  * Field Access Macros:
10690  *
10691  */
10692 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP register field. */
10693 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP_LSB 0
10694 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP register field. */
10695 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP_MSB 15
10696 /* The width in bits of the ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP register field. */
10697 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP_WIDTH 16
10698 /* The mask used to set the ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP register field value. */
10699 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP_SET_MSK 0x0000ffff
10700 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP register field value. */
10701 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP_CLR_MSK 0xffff0000
10702 /* The reset value of the ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP register field is UNKNOWN. */
10703 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP_RESET 0x0
10704 /* Extracts the ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP field value from a register. */
10705 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP_GET(value) (((value) & 0x0000ffff) >> 0)
10706 /* Produces a ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP register field value suitable for setting the register. */
10707 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP_SET(value) (((value) << 0) & 0x0000ffff)
10708 
10709 /*
10710  * Field : cfg_read_odt_chip
10711  *
10712  * iohmc_ctrl_mmr_top_inst.cfg_read_odt_chip[15:0]
10713  *
10714  * Name:Read ODT Control
10715  *
10716  * Description:ODT scheme setting for read command.
10717  *
10718  * Setting separated into 4 sections: [CS3][CS2][CS1][CS0]
10719  *
10720  * Each section consists of 4 bits to indicate which chip should ODT be asserted
10721  * when write occurs on current CS.
10722  *
10723  * Eg: if we set to 16’b0000_0000_0010_0001, ODT will be asserted to chip0 and
10724  * chip1 when write occurs to CS0 and CS1 respectively.
10725  *
10726  * Field Access Macros:
10727  *
10728  */
10729 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP register field. */
10730 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP_LSB 16
10731 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP register field. */
10732 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP_MSB 31
10733 /* The width in bits of the ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP register field. */
10734 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP_WIDTH 16
10735 /* The mask used to set the ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP register field value. */
10736 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP_SET_MSK 0xffff0000
10737 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP register field value. */
10738 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP_CLR_MSK 0x0000ffff
10739 /* The reset value of the ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP register field is UNKNOWN. */
10740 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP_RESET 0x0
10741 /* Extracts the ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP field value from a register. */
10742 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP_GET(value) (((value) & 0xffff0000) >> 16)
10743 /* Produces a ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP register field value suitable for setting the register. */
10744 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP_SET(value) (((value) << 16) & 0xffff0000)
10745 
10746 #ifndef __ASSEMBLY__
10747 /*
10748  * WARNING: The C register and register group struct declarations are provided for
10749  * convenience and illustrative purposes. They should, however, be used with
10750  * caution as the C language standard provides no guarantees about the alignment or
10751  * atomicity of device memory accesses. The recommended practice for coding device
10752  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10753  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10754  * alt_write_dword() functions for 64 bit registers.
10755  *
10756  * The struct declaration for register ALT_MPFE_IOHMC_REG_DRAMODT0.
10757  */
10758 struct ALT_MPFE_IOHMC_REG_DRAMODT0_s
10759 {
10760  volatile uint32_t cfg_write_odt_chip : 16; /* ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP */
10761  volatile uint32_t cfg_read_odt_chip : 16; /* ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP */
10762 };
10763 
10764 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_DRAMODT0. */
10765 typedef struct ALT_MPFE_IOHMC_REG_DRAMODT0_s ALT_MPFE_IOHMC_REG_DRAMODT0_t;
10766 #endif /* __ASSEMBLY__ */
10767 
10768 /* The reset value of the ALT_MPFE_IOHMC_REG_DRAMODT0 register. */
10769 #define ALT_MPFE_IOHMC_REG_DRAMODT0_RESET 0x00000000
10770 /* The byte offset of the ALT_MPFE_IOHMC_REG_DRAMODT0 register from the beginning of the component. */
10771 #define ALT_MPFE_IOHMC_REG_DRAMODT0_OFST 0x54
10772 
10773 /*
10774  * Register : reg_dramodt1
10775  *
10776  * Register Layout
10777  *
10778  * Bits | Access | Reset | Description
10779  * :--------|:-------|:--------|:----------------------------------------------
10780  * [5:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON
10781  * [11:6] | RW | Unknown | ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON
10782  * [17:12] | RW | Unknown | ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD
10783  * [23:18] | RW | Unknown | ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD
10784  * [31:24] | ??? | Unknown | *UNDEFINED*
10785  *
10786  */
10787 /*
10788  * Field : cfg_wr_odt_on
10789  *
10790  * iohmc_ctrl_mmr_top_inst.cfg_wr_odt_on[5:0]
10791  *
10792  * Name:Write ODT On Time
10793  *
10794  * Description:Indicates number of memory clock cycle gap between write command and
10795  * ODT signal rising edge.
10796  *
10797  * Field Access Macros:
10798  *
10799  */
10800 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON register field. */
10801 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON_LSB 0
10802 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON register field. */
10803 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON_MSB 5
10804 /* The width in bits of the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON register field. */
10805 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON_WIDTH 6
10806 /* The mask used to set the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON register field value. */
10807 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON_SET_MSK 0x0000003f
10808 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON register field value. */
10809 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON_CLR_MSK 0xffffffc0
10810 /* The reset value of the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON register field is UNKNOWN. */
10811 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON_RESET 0x0
10812 /* Extracts the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON field value from a register. */
10813 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON_GET(value) (((value) & 0x0000003f) >> 0)
10814 /* Produces a ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON register field value suitable for setting the register. */
10815 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON_SET(value) (((value) << 0) & 0x0000003f)
10816 
10817 /*
10818  * Field : cfg_rd_odt_on
10819  *
10820  * iohmc_ctrl_mmr_top_inst.cfg_rd_odt_on[5:0]
10821  *
10822  * Name:Read ODT On Time
10823  *
10824  * Description:Indicates number of memory clock cycle gap between read command and
10825  * ODT signal rising edge.
10826  *
10827  * Field Access Macros:
10828  *
10829  */
10830 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON register field. */
10831 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON_LSB 6
10832 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON register field. */
10833 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON_MSB 11
10834 /* The width in bits of the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON register field. */
10835 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON_WIDTH 6
10836 /* The mask used to set the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON register field value. */
10837 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON_SET_MSK 0x00000fc0
10838 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON register field value. */
10839 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON_CLR_MSK 0xfffff03f
10840 /* The reset value of the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON register field is UNKNOWN. */
10841 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON_RESET 0x0
10842 /* Extracts the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON field value from a register. */
10843 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON_GET(value) (((value) & 0x00000fc0) >> 6)
10844 /* Produces a ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON register field value suitable for setting the register. */
10845 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON_SET(value) (((value) << 6) & 0x00000fc0)
10846 
10847 /*
10848  * Field : cfg_wr_odt_period
10849  *
10850  * iohmc_ctrl_mmr_top_inst.cfg_wr_odt_period[5:0]
10851  *
10852  * Name:Write ODT Period
10853  *
10854  * Description:Indicates number of memory clock cycle write ODT signal should stay
10855  * asserted after rising edge.
10856  *
10857  * Field Access Macros:
10858  *
10859  */
10860 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD register field. */
10861 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD_LSB 12
10862 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD register field. */
10863 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD_MSB 17
10864 /* The width in bits of the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD register field. */
10865 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD_WIDTH 6
10866 /* The mask used to set the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD register field value. */
10867 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD_SET_MSK 0x0003f000
10868 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD register field value. */
10869 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD_CLR_MSK 0xfffc0fff
10870 /* The reset value of the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD register field is UNKNOWN. */
10871 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD_RESET 0x0
10872 /* Extracts the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD field value from a register. */
10873 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD_GET(value) (((value) & 0x0003f000) >> 12)
10874 /* Produces a ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD register field value suitable for setting the register. */
10875 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD_SET(value) (((value) << 12) & 0x0003f000)
10876 
10877 /*
10878  * Field : cfg_rd_odt_period
10879  *
10880  * iohmc_ctrl_mmr_top_inst.cfg_rd_odt_period[5:0]
10881  *
10882  * Name:Read ODT Period
10883  *
10884  * Description:Indicates number of memory clock cycle read ODT signal should stay
10885  * asserted after rising edge.
10886  *
10887  * Field Access Macros:
10888  *
10889  */
10890 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD register field. */
10891 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD_LSB 18
10892 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD register field. */
10893 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD_MSB 23
10894 /* The width in bits of the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD register field. */
10895 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD_WIDTH 6
10896 /* The mask used to set the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD register field value. */
10897 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD_SET_MSK 0x00fc0000
10898 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD register field value. */
10899 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD_CLR_MSK 0xff03ffff
10900 /* The reset value of the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD register field is UNKNOWN. */
10901 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD_RESET 0x0
10902 /* Extracts the ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD field value from a register. */
10903 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD_GET(value) (((value) & 0x00fc0000) >> 18)
10904 /* Produces a ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD register field value suitable for setting the register. */
10905 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD_SET(value) (((value) << 18) & 0x00fc0000)
10906 
10907 #ifndef __ASSEMBLY__
10908 /*
10909  * WARNING: The C register and register group struct declarations are provided for
10910  * convenience and illustrative purposes. They should, however, be used with
10911  * caution as the C language standard provides no guarantees about the alignment or
10912  * atomicity of device memory accesses. The recommended practice for coding device
10913  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10914  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10915  * alt_write_dword() functions for 64 bit registers.
10916  *
10917  * The struct declaration for register ALT_MPFE_IOHMC_REG_DRAMODT1.
10918  */
10919 struct ALT_MPFE_IOHMC_REG_DRAMODT1_s
10920 {
10921  volatile uint32_t cfg_wr_odt_on : 6; /* ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON */
10922  volatile uint32_t cfg_rd_odt_on : 6; /* ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON */
10923  volatile uint32_t cfg_wr_odt_period : 6; /* ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD */
10924  volatile uint32_t cfg_rd_odt_period : 6; /* ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD */
10925  uint32_t : 8; /* *UNDEFINED* */
10926 };
10927 
10928 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_DRAMODT1. */
10929 typedef struct ALT_MPFE_IOHMC_REG_DRAMODT1_s ALT_MPFE_IOHMC_REG_DRAMODT1_t;
10930 #endif /* __ASSEMBLY__ */
10931 
10932 /* The reset value of the ALT_MPFE_IOHMC_REG_DRAMODT1 register. */
10933 #define ALT_MPFE_IOHMC_REG_DRAMODT1_RESET 0x00000000
10934 /* The byte offset of the ALT_MPFE_IOHMC_REG_DRAMODT1 register from the beginning of the component. */
10935 #define ALT_MPFE_IOHMC_REG_DRAMODT1_OFST 0x58
10936 
10937 /*
10938  * Register : reg_sbcfg0
10939  *
10940  * Register Layout
10941  *
10942  * Bits | Access | Reset | Description
10943  * :--------|:-------|:--------|:------------------------------------------------------------------
10944  * [3:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH
10945  * [4] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK
10946  * [5] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL
10947  * [6] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX
10948  * [7] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE
10949  * [8] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX
10950  * [9] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX
10951  * [10] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE
10952  * [11] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN
10953  * [15:12] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0
10954  * [31:16] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1
10955  *
10956  */
10957 /*
10958  * Field : cfg_no_of_ref_for_self_rfsh
10959  *
10960  * iohmc_ctrl_mmr_top_inst.cfg_no_of_ref_for_self_rfsh[3:0]
10961  *
10962  * Name:No of Refresh prior to Self Refresh Entry
10963  *
10964  * Description:Configure the number of Refresh prior to Self Refresh Entry.
10965  *
10966  * Field Access Macros:
10967  *
10968  */
10969 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH register field. */
10970 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH_LSB 0
10971 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH register field. */
10972 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH_MSB 3
10973 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH register field. */
10974 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH_WIDTH 4
10975 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH register field value. */
10976 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH_SET_MSK 0x0000000f
10977 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH register field value. */
10978 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH_CLR_MSK 0xfffffff0
10979 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH register field is UNKNOWN. */
10980 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH_RESET 0x0
10981 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH field value from a register. */
10982 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH_GET(value) (((value) & 0x0000000f) >> 0)
10983 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH register field value suitable for setting the register. */
10984 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH_SET(value) (((value) << 0) & 0x0000000f)
10985 
10986 /*
10987  * Field : cfg_exit_pdn_for_dqstrk
10988  *
10989  * iohmc_ctrl_mmr_top_inst.cfg_exit_pdn_for_dqstrk
10990  *
10991  * Name:Exit Power Down For Periodic DQS
10992  *
10993  * Description:When asserted, Periodic DQS Tracking has higher priority compared to
10994  * Power Down.
10995  *
10996  * Field Access Macros:
10997  *
10998  */
10999 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK register field. */
11000 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK_LSB 4
11001 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK register field. */
11002 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK_MSB 4
11003 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK register field. */
11004 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK_WIDTH 1
11005 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK register field value. */
11006 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK_SET_MSK 0x00000010
11007 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK register field value. */
11008 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK_CLR_MSK 0xffffffef
11009 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK register field is UNKNOWN. */
11010 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK_RESET 0x0
11011 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK field value from a register. */
11012 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK_GET(value) (((value) & 0x00000010) >> 4)
11013 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK register field value suitable for setting the register. */
11014 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK_SET(value) (((value) << 4) & 0x00000010)
11015 
11016 /*
11017  * Field : cfg_cb_revert_ref_qual
11018  *
11019  * iohmc_ctrl_mmr_top_inst.cfg_cb_revert_ref_qual
11020  *
11021  * Name:Refresh and Self Refresh Behaviour Chicken Bit
11022  *
11023  * Description:When set to 0, do_refresh is ignored for Refresh state machine
11024  * transition.
11025  *
11026  * When set to 1, do_refresh is considered for Refresh state machine transition
11027  * similar to Nightfury.
11028  *
11029  * Field Access Macros:
11030  *
11031  */
11032 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL register field. */
11033 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL_LSB 5
11034 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL register field. */
11035 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL_MSB 5
11036 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL register field. */
11037 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL_WIDTH 1
11038 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL register field value. */
11039 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL_SET_MSK 0x00000020
11040 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL register field value. */
11041 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL_CLR_MSK 0xffffffdf
11042 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL register field is UNKNOWN. */
11043 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL_RESET 0x0
11044 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL field value from a register. */
11045 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL_GET(value) (((value) & 0x00000020) >> 5)
11046 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL register field value suitable for setting the register. */
11047 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL_SET(value) (((value) << 5) & 0x00000020)
11048 
11049 /*
11050  * Field : cfg_cb_en_cmd_valid_ungate_fix
11051  *
11052  * iohmc_ctrl_mmr_top_inst.cfg_cb_en_cmd_valid_ungate_fix
11053  *
11054  * Name:Chicken bit for command valid ungated fix
11055  *
11056  * Description:Set to 1’b1 to enable fix.
11057  *
11058  * Field Access Macros:
11059  *
11060  */
11061 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX register field. */
11062 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX_LSB 6
11063 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX register field. */
11064 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX_MSB 6
11065 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX register field. */
11066 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX_WIDTH 1
11067 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX register field value. */
11068 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX_SET_MSK 0x00000040
11069 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX register field value. */
11070 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX_CLR_MSK 0xffffffbf
11071 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX register field is UNKNOWN. */
11072 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX_RESET 0x0
11073 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX field value from a register. */
11074 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX_GET(value) (((value) & 0x00000040) >> 6)
11075 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX register field value suitable for setting the register. */
11076 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX_SET(value) (((value) << 6) & 0x00000040)
11077 
11078 /*
11079  * Field : cfg_cb_3ds_mixed_height_ref_ack_disable
11080  *
11081  * iohmc_ctrl_mmr_top_inst.cfg_cb_3ds_mixed_height_ref_ack_disable
11082  *
11083  * Name:3DS Mixed Height Physical Staggering Off Refresh Ack Chicken Bit
11084  *
11085  * Description:When set to 0, enable fix for 3DS Mixed Height Physical Staggering
11086  * Off Refresh Ack where iohmc refers to respective cfg_lr_num* for Refresh Ack
11087  * assertion
11088  *
11089  * When set to 1, disable fix for 3DS Mixed Height Physical Staggering Off Refresh
11090  * Ack where iohmc refers to cfg_lr_num0 for Refresh Ack assertion.
11091  *
11092  * Field Access Macros:
11093  *
11094  */
11095 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE register field. */
11096 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE_LSB 7
11097 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE register field. */
11098 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE_MSB 7
11099 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE register field. */
11100 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE_WIDTH 1
11101 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE register field value. */
11102 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE_SET_MSK 0x00000080
11103 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE register field value. */
11104 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE_CLR_MSK 0xffffff7f
11105 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE register field is UNKNOWN. */
11106 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE_RESET 0x0
11107 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE field value from a register. */
11108 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE_GET(value) (((value) & 0x00000080) >> 7)
11109 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE register field value suitable for setting the register. */
11110 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE_SET(value) (((value) << 7) & 0x00000080)
11111 
11112 /*
11113  * Field : cfg_cb_en_mrnk_rd_fix
11114  *
11115  * iohmc_ctrl_mmr_top_inst.cfg_cb_en_mrnk_rd_fix
11116  *
11117  * Name:Chicken bit for read mrnk fix
11118  *
11119  * Description:Set to 1’b1 to enable fix.
11120  *
11121  * Field Access Macros:
11122  *
11123  */
11124 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX register field. */
11125 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX_LSB 8
11126 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX register field. */
11127 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX_MSB 8
11128 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX register field. */
11129 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX_WIDTH 1
11130 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX register field value. */
11131 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX_SET_MSK 0x00000100
11132 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX register field value. */
11133 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX_CLR_MSK 0xfffffeff
11134 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX register field is UNKNOWN. */
11135 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX_RESET 0x0
11136 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX field value from a register. */
11137 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX_GET(value) (((value) & 0x00000100) >> 8)
11138 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX register field value suitable for setting the register. */
11139 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX_SET(value) (((value) << 8) & 0x00000100)
11140 
11141 /*
11142  * Field : cfg_cb_3ds_mixed_height_req_fix
11143  *
11144  * iohmc_ctrl_mmr_top_inst.cfg_cb_3ds_mixed_height_req_fix
11145  *
11146  * Name:3DS Mixed Height Physical Staggering Off Disable Precharge to non-existent
11147  * Lower Logical Rank Chicken Bit
11148  *
11149  * Description:When set to 0, enable fix where iohmc does not Precharge non
11150  * existent Logical Rank in Physical Staggering Off Mode
11151  *
11152  * When set to 1, disable fix where iohm Precharge non existent Logical Rank in
11153  * Physical Staggering Off Mode.
11154  *
11155  * Field Access Macros:
11156  *
11157  */
11158 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX register field. */
11159 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX_LSB 9
11160 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX register field. */
11161 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX_MSB 9
11162 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX register field. */
11163 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX_WIDTH 1
11164 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX register field value. */
11165 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX_SET_MSK 0x00000200
11166 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX register field value. */
11167 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX_CLR_MSK 0xfffffdff
11168 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX register field is UNKNOWN. */
11169 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX_RESET 0x0
11170 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX field value from a register. */
11171 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX_GET(value) (((value) & 0x00000200) >> 9)
11172 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX register field value suitable for setting the register. */
11173 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX_SET(value) (((value) << 9) & 0x00000200)
11174 
11175 /*
11176  * Field : cfg_cb_pdqs_perf_fix_disable
11177  *
11178  * iohmc_ctrl_mmr_top_inst.cfg_cb_pdqs_perf_fix_disable
11179  *
11180  * Name:Periodic DQS Tracking Performance Chicken Bit
11181  *
11182  * Description:When set to 0, enable fix where Periodic DQS Tracking is issued
11183  * earlier.
11184  *
11185  * When set to 1, disable fix where Periodic DQS Tracking is issued after a fixed
11186  * delay.
11187  *
11188  * Field Access Macros:
11189  *
11190  */
11191 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE register field. */
11192 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE_LSB 10
11193 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE register field. */
11194 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE_MSB 10
11195 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE register field. */
11196 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE_WIDTH 1
11197 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE register field value. */
11198 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE_SET_MSK 0x00000400
11199 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE register field value. */
11200 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE_CLR_MSK 0xfffffbff
11201 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE register field is UNKNOWN. */
11202 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE_RESET 0x0
11203 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE field value from a register. */
11204 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE_GET(value) (((value) & 0x00000400) >> 10)
11205 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE register field value suitable for setting the register. */
11206 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE_SET(value) (((value) << 10) & 0x00000400)
11207 
11208 /*
11209  * Field : cfg_self_rfsh_dqstrk_en
11210  *
11211  * iohmc_ctrl_mmr_top_inst.cfg_self_rfsh_dqstrk_en
11212  *
11213  * Name:Enable DQS Tracking After Self Refresh Exit
11214  *
11215  * Description:When set to 1, enable DQS Tracking after Self Refresh exit.
11216  *
11217  * When set to 0, disable DQS Tracking after Self Refresh exit.
11218  *
11219  * Field Access Macros:
11220  *
11221  */
11222 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN register field. */
11223 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN_LSB 11
11224 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN register field. */
11225 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN_MSB 11
11226 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN register field. */
11227 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN_WIDTH 1
11228 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN register field value. */
11229 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN_SET_MSK 0x00000800
11230 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN register field value. */
11231 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN_CLR_MSK 0xfffff7ff
11232 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN register field is UNKNOWN. */
11233 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN_RESET 0x0
11234 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN field value from a register. */
11235 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN_GET(value) (((value) & 0x00000800) >> 11)
11236 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN register field value suitable for setting the register. */
11237 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN_SET(value) (((value) << 11) & 0x00000800)
11238 
11239 /*
11240  * Field : cfg_rld3_refresh_seq0
11241  *
11242  * iohmc_ctrl_mmr_top_inst.cfg_rld3_refresh_seq0[3:0]
11243  *
11244  * Name:Reserved
11245  *
11246  * Description:TBD
11247  *
11248  * Field Access Macros:
11249  *
11250  */
11251 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0 register field. */
11252 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0_LSB 12
11253 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0 register field. */
11254 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0_MSB 15
11255 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0 register field. */
11256 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0_WIDTH 4
11257 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0 register field value. */
11258 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0_SET_MSK 0x0000f000
11259 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0 register field value. */
11260 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0_CLR_MSK 0xffff0fff
11261 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0 register field is UNKNOWN. */
11262 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0_RESET 0x0
11263 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0 field value from a register. */
11264 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0_GET(value) (((value) & 0x0000f000) >> 12)
11265 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0 register field value suitable for setting the register. */
11266 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0_SET(value) (((value) << 12) & 0x0000f000)
11267 
11268 /*
11269  * Field : cfg_rld3_refresh_seq1
11270  *
11271  * iohmc_ctrl_mmr_top_inst.cfg_rld3_refresh_seq1[15:0]
11272  *
11273  * Name:Reserved
11274  *
11275  * Description:TBD
11276  *
11277  * Field Access Macros:
11278  *
11279  */
11280 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1 register field. */
11281 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1_LSB 16
11282 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1 register field. */
11283 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1_MSB 31
11284 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1 register field. */
11285 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1_WIDTH 16
11286 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1 register field value. */
11287 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1_SET_MSK 0xffff0000
11288 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1 register field value. */
11289 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1_CLR_MSK 0x0000ffff
11290 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1 register field is UNKNOWN. */
11291 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1_RESET 0x0
11292 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1 field value from a register. */
11293 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1_GET(value) (((value) & 0xffff0000) >> 16)
11294 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1 register field value suitable for setting the register. */
11295 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1_SET(value) (((value) << 16) & 0xffff0000)
11296 
11297 #ifndef __ASSEMBLY__
11298 /*
11299  * WARNING: The C register and register group struct declarations are provided for
11300  * convenience and illustrative purposes. They should, however, be used with
11301  * caution as the C language standard provides no guarantees about the alignment or
11302  * atomicity of device memory accesses. The recommended practice for coding device
11303  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11304  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11305  * alt_write_dword() functions for 64 bit registers.
11306  *
11307  * The struct declaration for register ALT_MPFE_IOHMC_REG_SBCFG0.
11308  */
11309 struct ALT_MPFE_IOHMC_REG_SBCFG0_s
11310 {
11311  volatile uint32_t cfg_no_of_ref_for_self_rfsh : 4; /* ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH */
11312  volatile uint32_t cfg_exit_pdn_for_dqstrk : 1; /* ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK */
11313  volatile uint32_t cfg_cb_revert_ref_qual : 1; /* ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL */
11314  volatile uint32_t cfg_cb_en_cmd_valid_ungate_fix : 1; /* ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX */
11315  volatile uint32_t cfg_cb_3ds_mixed_height_ref_ack_disable : 1; /* ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE */
11316  volatile uint32_t cfg_cb_en_mrnk_rd_fix : 1; /* ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX */
11317  volatile uint32_t cfg_cb_3ds_mixed_height_req_fix : 1; /* ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX */
11318  volatile uint32_t cfg_cb_pdqs_perf_fix_disable : 1; /* ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE */
11319  volatile uint32_t cfg_self_rfsh_dqstrk_en : 1; /* ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN */
11320  volatile uint32_t cfg_rld3_refresh_seq0 : 4; /* ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0 */
11321  volatile uint32_t cfg_rld3_refresh_seq1 : 16; /* ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1 */
11322 };
11323 
11324 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SBCFG0. */
11325 typedef struct ALT_MPFE_IOHMC_REG_SBCFG0_s ALT_MPFE_IOHMC_REG_SBCFG0_t;
11326 #endif /* __ASSEMBLY__ */
11327 
11328 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG0 register. */
11329 #define ALT_MPFE_IOHMC_REG_SBCFG0_RESET 0x00000000
11330 /* The byte offset of the ALT_MPFE_IOHMC_REG_SBCFG0 register from the beginning of the component. */
11331 #define ALT_MPFE_IOHMC_REG_SBCFG0_OFST 0x5c
11332 
11333 /*
11334  * Register : reg_sbcfg1
11335  *
11336  * Register Layout
11337  *
11338  * Bits | Access | Reset | Description
11339  * :--------|:-------|:--------|:------------------------------------------------
11340  * [15:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2
11341  * [31:16] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3
11342  *
11343  */
11344 /*
11345  * Field : cfg_rld3_refresh_seq2
11346  *
11347  * iohmc_ctrl_mmr_top_inst.cfg_rld3_refresh_seq2[15:0]
11348  *
11349  * Name:Reserved
11350  *
11351  * Description:TBD
11352  *
11353  * Field Access Macros:
11354  *
11355  */
11356 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2 register field. */
11357 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2_LSB 0
11358 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2 register field. */
11359 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2_MSB 15
11360 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2 register field. */
11361 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2_WIDTH 16
11362 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2 register field value. */
11363 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2_SET_MSK 0x0000ffff
11364 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2 register field value. */
11365 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2_CLR_MSK 0xffff0000
11366 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2 register field is UNKNOWN. */
11367 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2_RESET 0x0
11368 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2 field value from a register. */
11369 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2_GET(value) (((value) & 0x0000ffff) >> 0)
11370 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2 register field value suitable for setting the register. */
11371 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2_SET(value) (((value) << 0) & 0x0000ffff)
11372 
11373 /*
11374  * Field : cfg_rld3_refresh_seq3
11375  *
11376  * iohmc_ctrl_mmr_top_inst.cfg_rld3_refresh_seq3[15:0]
11377  *
11378  * Name:Reserved
11379  *
11380  * Description:TBD
11381  *
11382  * Field Access Macros:
11383  *
11384  */
11385 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3 register field. */
11386 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3_LSB 16
11387 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3 register field. */
11388 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3_MSB 31
11389 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3 register field. */
11390 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3_WIDTH 16
11391 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3 register field value. */
11392 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3_SET_MSK 0xffff0000
11393 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3 register field value. */
11394 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3_CLR_MSK 0x0000ffff
11395 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3 register field is UNKNOWN. */
11396 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3_RESET 0x0
11397 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3 field value from a register. */
11398 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3_GET(value) (((value) & 0xffff0000) >> 16)
11399 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3 register field value suitable for setting the register. */
11400 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3_SET(value) (((value) << 16) & 0xffff0000)
11401 
11402 #ifndef __ASSEMBLY__
11403 /*
11404  * WARNING: The C register and register group struct declarations are provided for
11405  * convenience and illustrative purposes. They should, however, be used with
11406  * caution as the C language standard provides no guarantees about the alignment or
11407  * atomicity of device memory accesses. The recommended practice for coding device
11408  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11409  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11410  * alt_write_dword() functions for 64 bit registers.
11411  *
11412  * The struct declaration for register ALT_MPFE_IOHMC_REG_SBCFG1.
11413  */
11414 struct ALT_MPFE_IOHMC_REG_SBCFG1_s
11415 {
11416  volatile uint32_t cfg_rld3_refresh_seq2 : 16; /* ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2 */
11417  volatile uint32_t cfg_rld3_refresh_seq3 : 16; /* ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3 */
11418 };
11419 
11420 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SBCFG1. */
11421 typedef struct ALT_MPFE_IOHMC_REG_SBCFG1_s ALT_MPFE_IOHMC_REG_SBCFG1_t;
11422 #endif /* __ASSEMBLY__ */
11423 
11424 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG1 register. */
11425 #define ALT_MPFE_IOHMC_REG_SBCFG1_RESET 0x00000000
11426 /* The byte offset of the ALT_MPFE_IOHMC_REG_SBCFG1 register from the beginning of the component. */
11427 #define ALT_MPFE_IOHMC_REG_SBCFG1_OFST 0x60
11428 
11429 /*
11430  * Register : reg_sbcfg2
11431  *
11432  * Register Layout
11433  *
11434  * Bits | Access | Reset | Description
11435  * :-------|:-------|:--------|:---------------------------------------------------
11436  * [0] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE
11437  * [1] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE
11438  * [2] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE
11439  * [3] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE
11440  * [4] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN
11441  * [5] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN
11442  * [7:6] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK
11443  * [31:8] | ??? | Unknown | *UNDEFINED*
11444  *
11445  */
11446 /*
11447  * Field : cfg_srf_zqcal_disable
11448  *
11449  * iohmc_ctrl_mmr_top_inst.cfg_srf_zqcal_disable
11450  *
11451  * Name:ZQCal after Self Refresh Disable
11452  *
11453  * Description:Setting to 1 to disable ZQ Calibration after self refresh.
11454  *
11455  * Field Access Macros:
11456  *
11457  */
11458 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE register field. */
11459 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE_LSB 0
11460 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE register field. */
11461 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE_MSB 0
11462 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE register field. */
11463 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE_WIDTH 1
11464 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE register field value. */
11465 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE_SET_MSK 0x00000001
11466 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE register field value. */
11467 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE_CLR_MSK 0xfffffffe
11468 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE register field is UNKNOWN. */
11469 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE_RESET 0x0
11470 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE field value from a register. */
11471 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE_GET(value) (((value) & 0x00000001) >> 0)
11472 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE register field value suitable for setting the register. */
11473 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE_SET(value) (((value) << 0) & 0x00000001)
11474 
11475 /*
11476  * Field : cfg_mps_zqcal_disable
11477  *
11478  * iohmc_ctrl_mmr_top_inst.cfg_mps_zqcal_disable
11479  *
11480  * Name:ZQCal after MPS Disable
11481  *
11482  * Description:Setting to 1 to disable ZQ Calibration after Maximum Power Saving
11483  * exit.
11484  *
11485  * Field Access Macros:
11486  *
11487  */
11488 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE register field. */
11489 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE_LSB 1
11490 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE register field. */
11491 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE_MSB 1
11492 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE register field. */
11493 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE_WIDTH 1
11494 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE register field value. */
11495 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE_SET_MSK 0x00000002
11496 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE register field value. */
11497 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE_CLR_MSK 0xfffffffd
11498 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE register field is UNKNOWN. */
11499 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE_RESET 0x0
11500 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE field value from a register. */
11501 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE_GET(value) (((value) & 0x00000002) >> 1)
11502 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE register field value suitable for setting the register. */
11503 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE_SET(value) (((value) << 1) & 0x00000002)
11504 
11505 /*
11506  * Field : cfg_mps_dqstrk_disable
11507  *
11508  * iohmc_ctrl_mmr_top_inst.cfg_mps_dqstrk_disable
11509  *
11510  * Name:DQS Tracking after MPS Disable
11511  *
11512  * Description:Setting to 1 to disable DQS Tracking after Maximum Power Saving exit
11513  *
11514  * 1’b1 – Disable Reinitialization
11515  *
11516  * 1’b0 – Enable Reinitialization
11517  *
11518  * Field Access Macros:
11519  *
11520  */
11521 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE register field. */
11522 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE_LSB 2
11523 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE register field. */
11524 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE_MSB 2
11525 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE register field. */
11526 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE_WIDTH 1
11527 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE register field value. */
11528 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE_SET_MSK 0x00000004
11529 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE register field value. */
11530 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE_CLR_MSK 0xfffffffb
11531 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE register field is UNKNOWN. */
11532 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE_RESET 0x0
11533 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE field value from a register. */
11534 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE_GET(value) (((value) & 0x00000004) >> 2)
11535 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE register field value suitable for setting the register. */
11536 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE_SET(value) (((value) << 2) & 0x00000004)
11537 
11538 /*
11539  * Field : cfg_sb_cg_disable
11540  *
11541  * iohmc_ctrl_mmr_top_inst.cfg_sb_cg_disable
11542  *
11543  * Name:Clock Gating Disable During Sideband Operations
11544  *
11545  * Description:Setting to 1 to disable mem_ck gating during self refresh and deep
11546  * power down.
11547  *
11548  * Field Access Macros:
11549  *
11550  */
11551 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE register field. */
11552 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE_LSB 3
11553 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE register field. */
11554 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE_MSB 3
11555 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE register field. */
11556 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE_WIDTH 1
11557 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE register field value. */
11558 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE_SET_MSK 0x00000008
11559 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE register field value. */
11560 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE_CLR_MSK 0xfffffff7
11561 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE register field is UNKNOWN. */
11562 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE_RESET 0x0
11563 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE field value from a register. */
11564 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE_GET(value) (((value) & 0x00000008) >> 3)
11565 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE register field value suitable for setting the register. */
11566 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE_SET(value) (((value) << 3) & 0x00000008)
11567 
11568 /*
11569  * Field : cfg_user_rfsh_en
11570  *
11571  * iohmc_ctrl_mmr_top_inst.cfg_user_rfsh_en
11572  *
11573  * Name:User Refresh Enable
11574  *
11575  * Description:Setting to 1 to enable user refresh.
11576  *
11577  * Field Access Macros:
11578  *
11579  */
11580 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN register field. */
11581 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN_LSB 4
11582 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN register field. */
11583 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN_MSB 4
11584 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN register field. */
11585 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN_WIDTH 1
11586 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN register field value. */
11587 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN_SET_MSK 0x00000010
11588 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN register field value. */
11589 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN_CLR_MSK 0xffffffef
11590 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN register field is UNKNOWN. */
11591 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN_RESET 0x0
11592 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN field value from a register. */
11593 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN_GET(value) (((value) & 0x00000010) >> 4)
11594 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN register field value suitable for setting the register. */
11595 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN_SET(value) (((value) << 4) & 0x00000010)
11596 
11597 /*
11598  * Field : cfg_srf_autoexit_en
11599  *
11600  * iohmc_ctrl_mmr_top_inst.cfg_srf_autoexit_en
11601  *
11602  * Name:Self Refresh Auto Exit Enable
11603  *
11604  * Description:Setting to 1 to enable controller to exit Self Refresh when new
11605  * command is detected.
11606  *
11607  * Field Access Macros:
11608  *
11609  */
11610 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN register field. */
11611 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN_LSB 5
11612 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN register field. */
11613 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN_MSB 5
11614 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN register field. */
11615 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN_WIDTH 1
11616 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN register field value. */
11617 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN_SET_MSK 0x00000020
11618 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN register field value. */
11619 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN_CLR_MSK 0xffffffdf
11620 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN register field is UNKNOWN. */
11621 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN_RESET 0x0
11622 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN field value from a register. */
11623 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN_GET(value) (((value) & 0x00000020) >> 5)
11624 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN register field value suitable for setting the register. */
11625 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN_SET(value) (((value) << 5) & 0x00000020)
11626 
11627 /*
11628  * Field : cfg_srf_entry_exit_block
11629  *
11630  * iohmc_ctrl_mmr_top_inst.cfg_srf_entry_exit_block[1:0]
11631  *
11632  * Name:Pre/Post Self Refresh Block
11633  *
11634  * Description:Blocking arbiter from issuing cmds for the 4 cases,
11635  *
11636  * 2’b00 – Pre Self Refresh Enter
11637  *
11638  * 2’b01 – Post Self Refresh Enter
11639  *
11640  * 2’b10 – Pre Self Refresh Exit
11641  *
11642  * 2’b11 Post Self Refresh Exit
11643  *
11644  * Field Access Macros:
11645  *
11646  */
11647 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK register field. */
11648 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_LSB 6
11649 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK register field. */
11650 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_MSB 7
11651 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK register field. */
11652 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_WIDTH 2
11653 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK register field value. */
11654 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_SET_MSK 0x000000c0
11655 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK register field value. */
11656 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_CLR_MSK 0xffffff3f
11657 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK register field is UNKNOWN. */
11658 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_RESET 0x0
11659 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK field value from a register. */
11660 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_GET(value) (((value) & 0x000000c0) >> 6)
11661 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK register field value suitable for setting the register. */
11662 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_SET(value) (((value) << 6) & 0x000000c0)
11663 
11664 #ifndef __ASSEMBLY__
11665 /*
11666  * WARNING: The C register and register group struct declarations are provided for
11667  * convenience and illustrative purposes. They should, however, be used with
11668  * caution as the C language standard provides no guarantees about the alignment or
11669  * atomicity of device memory accesses. The recommended practice for coding device
11670  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11671  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11672  * alt_write_dword() functions for 64 bit registers.
11673  *
11674  * The struct declaration for register ALT_MPFE_IOHMC_REG_SBCFG2.
11675  */
11676 struct ALT_MPFE_IOHMC_REG_SBCFG2_s
11677 {
11678  volatile uint32_t cfg_srf_zqcal_disable : 1; /* ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE */
11679  volatile uint32_t cfg_mps_zqcal_disable : 1; /* ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE */
11680  volatile uint32_t cfg_mps_dqstrk_disable : 1; /* ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE */
11681  volatile uint32_t cfg_sb_cg_disable : 1; /* ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE */
11682  volatile uint32_t cfg_user_rfsh_en : 1; /* ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN */
11683  volatile uint32_t cfg_srf_autoexit_en : 1; /* ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN */
11684  volatile uint32_t cfg_srf_entry_exit_block : 2; /* ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK */
11685  uint32_t : 24; /* *UNDEFINED* */
11686 };
11687 
11688 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SBCFG2. */
11689 typedef struct ALT_MPFE_IOHMC_REG_SBCFG2_s ALT_MPFE_IOHMC_REG_SBCFG2_t;
11690 #endif /* __ASSEMBLY__ */
11691 
11692 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG2 register. */
11693 #define ALT_MPFE_IOHMC_REG_SBCFG2_RESET 0x00000000
11694 /* The byte offset of the ALT_MPFE_IOHMC_REG_SBCFG2 register from the beginning of the component. */
11695 #define ALT_MPFE_IOHMC_REG_SBCFG2_OFST 0x64
11696 
11697 /*
11698  * Register : reg_sbcfg3
11699  *
11700  * Register Layout
11701  *
11702  * Bits | Access | Reset | Description
11703  * :--------|:-------|:--------|:------------------------------------------
11704  * [19:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3
11705  * [31:20] | ??? | Unknown | *UNDEFINED*
11706  *
11707  */
11708 /*
11709  * Field : cfg_sb_ddr4_mr3
11710  *
11711  * iohmc_ctrl_mmr_top_inst.cfg_sb_ddr4_mr3[19:0]
11712  *
11713  * Name:DDR4 MR3 content
11714  *
11715  * Description:This register stores the DDR4 MR3 Content.
11716  *
11717  * Field Access Macros:
11718  *
11719  */
11720 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3 register field. */
11721 #define ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3_LSB 0
11722 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3 register field. */
11723 #define ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3_MSB 19
11724 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3 register field. */
11725 #define ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3_WIDTH 20
11726 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3 register field value. */
11727 #define ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3_SET_MSK 0x000fffff
11728 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3 register field value. */
11729 #define ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3_CLR_MSK 0xfff00000
11730 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3 register field is UNKNOWN. */
11731 #define ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3_RESET 0x0
11732 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3 field value from a register. */
11733 #define ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3_GET(value) (((value) & 0x000fffff) >> 0)
11734 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3 register field value suitable for setting the register. */
11735 #define ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3_SET(value) (((value) << 0) & 0x000fffff)
11736 
11737 #ifndef __ASSEMBLY__
11738 /*
11739  * WARNING: The C register and register group struct declarations are provided for
11740  * convenience and illustrative purposes. They should, however, be used with
11741  * caution as the C language standard provides no guarantees about the alignment or
11742  * atomicity of device memory accesses. The recommended practice for coding device
11743  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11744  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11745  * alt_write_dword() functions for 64 bit registers.
11746  *
11747  * The struct declaration for register ALT_MPFE_IOHMC_REG_SBCFG3.
11748  */
11749 struct ALT_MPFE_IOHMC_REG_SBCFG3_s
11750 {
11751  volatile uint32_t cfg_sb_ddr4_mr3 : 20; /* ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3 */
11752  uint32_t : 12; /* *UNDEFINED* */
11753 };
11754 
11755 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SBCFG3. */
11756 typedef struct ALT_MPFE_IOHMC_REG_SBCFG3_s ALT_MPFE_IOHMC_REG_SBCFG3_t;
11757 #endif /* __ASSEMBLY__ */
11758 
11759 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG3 register. */
11760 #define ALT_MPFE_IOHMC_REG_SBCFG3_RESET 0x00000000
11761 /* The byte offset of the ALT_MPFE_IOHMC_REG_SBCFG3 register from the beginning of the component. */
11762 #define ALT_MPFE_IOHMC_REG_SBCFG3_OFST 0x68
11763 
11764 /*
11765  * Register : reg_sbcfg4
11766  *
11767  * Register Layout
11768  *
11769  * Bits | Access | Reset | Description
11770  * :--------|:-------|:--------|:------------------------------------------
11771  * [19:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4
11772  * [31:20] | ??? | Unknown | *UNDEFINED*
11773  *
11774  */
11775 /*
11776  * Field : cfg_sb_ddr4_mr4
11777  *
11778  * iohmc_ctrl_mmr_top_inst.cfg_sb_ddr4_mr4[19:0]
11779  *
11780  * Name:DDR4 MR4 content
11781  *
11782  * Description:This register stores the DDR4 MR4 Content.
11783  *
11784  * Field Access Macros:
11785  *
11786  */
11787 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4 register field. */
11788 #define ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4_LSB 0
11789 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4 register field. */
11790 #define ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4_MSB 19
11791 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4 register field. */
11792 #define ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4_WIDTH 20
11793 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4 register field value. */
11794 #define ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4_SET_MSK 0x000fffff
11795 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4 register field value. */
11796 #define ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4_CLR_MSK 0xfff00000
11797 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4 register field is UNKNOWN. */
11798 #define ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4_RESET 0x0
11799 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4 field value from a register. */
11800 #define ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4_GET(value) (((value) & 0x000fffff) >> 0)
11801 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4 register field value suitable for setting the register. */
11802 #define ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4_SET(value) (((value) << 0) & 0x000fffff)
11803 
11804 #ifndef __ASSEMBLY__
11805 /*
11806  * WARNING: The C register and register group struct declarations are provided for
11807  * convenience and illustrative purposes. They should, however, be used with
11808  * caution as the C language standard provides no guarantees about the alignment or
11809  * atomicity of device memory accesses. The recommended practice for coding device
11810  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11811  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11812  * alt_write_dword() functions for 64 bit registers.
11813  *
11814  * The struct declaration for register ALT_MPFE_IOHMC_REG_SBCFG4.
11815  */
11816 struct ALT_MPFE_IOHMC_REG_SBCFG4_s
11817 {
11818  volatile uint32_t cfg_sb_ddr4_mr4 : 20; /* ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4 */
11819  uint32_t : 12; /* *UNDEFINED* */
11820 };
11821 
11822 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SBCFG4. */
11823 typedef struct ALT_MPFE_IOHMC_REG_SBCFG4_s ALT_MPFE_IOHMC_REG_SBCFG4_t;
11824 #endif /* __ASSEMBLY__ */
11825 
11826 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG4 register. */
11827 #define ALT_MPFE_IOHMC_REG_SBCFG4_RESET 0x00000000
11828 /* The byte offset of the ALT_MPFE_IOHMC_REG_SBCFG4 register from the beginning of the component. */
11829 #define ALT_MPFE_IOHMC_REG_SBCFG4_OFST 0x6c
11830 
11831 /*
11832  * Register : reg_sbcfg5
11833  *
11834  * Register Layout
11835  *
11836  * Bits | Access | Reset | Description
11837  * :-------|:-------|:--------|:----------------------------------------------------
11838  * [0] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN
11839  * [1] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN
11840  * [31:2] | ??? | Unknown | *UNDEFINED*
11841  *
11842  */
11843 /*
11844  * Field : cfg_short_dqstrk_ctrl_en
11845  *
11846  * iohmc_ctrl_mmr_top_inst.cfg_short_dqstrk_ctrl_en
11847  *
11848  * Name:Controller Controlled Short DQS Tracking Enable
11849  *
11850  * Description:Set to 1 to enable controller controlled DQS short tracking,
11851  *
11852  * Set to 0 to enable sequencer controlled DQS short tracking.
11853  *
11854  * Field Access Macros:
11855  *
11856  */
11857 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN register field. */
11858 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN_LSB 0
11859 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN register field. */
11860 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN_MSB 0
11861 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN register field. */
11862 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN_WIDTH 1
11863 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN register field value. */
11864 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN_SET_MSK 0x00000001
11865 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN register field value. */
11866 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN_CLR_MSK 0xfffffffe
11867 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN register field is UNKNOWN. */
11868 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN_RESET 0x0
11869 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN field value from a register. */
11870 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN_GET(value) (((value) & 0x00000001) >> 0)
11871 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN register field value suitable for setting the register. */
11872 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN_SET(value) (((value) << 0) & 0x00000001)
11873 
11874 /*
11875  * Field : cfg_period_dqstrk_ctrl_en
11876  *
11877  * iohmc_ctrl_mmr_top_inst.cfg_period_dqstrk_ctrl_en
11878  *
11879  * Name:Controller Controlled Periodic DQS Tracking Enable
11880  *
11881  * Description:Set to 1 to enable controller to issue periodic DQS tracking.
11882  *
11883  * Field Access Macros:
11884  *
11885  */
11886 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN register field. */
11887 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN_LSB 1
11888 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN register field. */
11889 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN_MSB 1
11890 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN register field. */
11891 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN_WIDTH 1
11892 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN register field value. */
11893 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN_SET_MSK 0x00000002
11894 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN register field value. */
11895 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN_CLR_MSK 0xfffffffd
11896 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN register field is UNKNOWN. */
11897 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN_RESET 0x0
11898 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN field value from a register. */
11899 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN_GET(value) (((value) & 0x00000002) >> 1)
11900 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN register field value suitable for setting the register. */
11901 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN_SET(value) (((value) << 1) & 0x00000002)
11902 
11903 #ifndef __ASSEMBLY__
11904 /*
11905  * WARNING: The C register and register group struct declarations are provided for
11906  * convenience and illustrative purposes. They should, however, be used with
11907  * caution as the C language standard provides no guarantees about the alignment or
11908  * atomicity of device memory accesses. The recommended practice for coding device
11909  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11910  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11911  * alt_write_dword() functions for 64 bit registers.
11912  *
11913  * The struct declaration for register ALT_MPFE_IOHMC_REG_SBCFG5.
11914  */
11915 struct ALT_MPFE_IOHMC_REG_SBCFG5_s
11916 {
11917  volatile uint32_t cfg_short_dqstrk_ctrl_en : 1; /* ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN */
11918  volatile uint32_t cfg_period_dqstrk_ctrl_en : 1; /* ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN */
11919  uint32_t : 30; /* *UNDEFINED* */
11920 };
11921 
11922 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SBCFG5. */
11923 typedef struct ALT_MPFE_IOHMC_REG_SBCFG5_s ALT_MPFE_IOHMC_REG_SBCFG5_t;
11924 #endif /* __ASSEMBLY__ */
11925 
11926 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG5 register. */
11927 #define ALT_MPFE_IOHMC_REG_SBCFG5_RESET 0x00000000
11928 /* The byte offset of the ALT_MPFE_IOHMC_REG_SBCFG5 register from the beginning of the component. */
11929 #define ALT_MPFE_IOHMC_REG_SBCFG5_OFST 0x70
11930 
11931 /*
11932  * Register : reg_sbcfg6
11933  *
11934  * Register Layout
11935  *
11936  * Bits | Access | Reset | Description
11937  * :--------|:-------|:--------|:-----------------------------------------------------------
11938  * [15:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL
11939  * [23:16] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST
11940  * [31:24] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID
11941  *
11942  */
11943 /*
11944  * Field : cfg_period_dqstrk_interval
11945  *
11946  * iohmc_ctrl_mmr_top_inst.cfg_period_dqstrk_interval[15:0]
11947  *
11948  * Name:Periodic DQS Tracking Interval
11949  *
11950  * Description:Interval between two controller controlled periodic DQS tracking.
11951  *
11952  * Field Access Macros:
11953  *
11954  */
11955 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL register field. */
11956 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_LSB 0
11957 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL register field. */
11958 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_MSB 15
11959 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL register field. */
11960 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_WIDTH 16
11961 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL register field value. */
11962 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_SET_MSK 0x0000ffff
11963 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL register field value. */
11964 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_CLR_MSK 0xffff0000
11965 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL register field is UNKNOWN. */
11966 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_RESET 0x0
11967 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL field value from a register. */
11968 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_GET(value) (((value) & 0x0000ffff) >> 0)
11969 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL register field value suitable for setting the register. */
11970 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_SET(value) (((value) << 0) & 0x0000ffff)
11971 
11972 /*
11973  * Field : cfg_t_param_dqstrk_to_valid_last
11974  *
11975  * iohmc_ctrl_mmr_top_inst.cfg_t_param_dqstrk_to_valid_last[7:0]
11976  *
11977  * Name:DQS Tracking Rd to Valid timing for the last Rank
11978  *
11979  * Description:DQS Tracking Rd to Valid timing for the last Rank.
11980  *
11981  * Field Access Macros:
11982  *
11983  */
11984 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST register field. */
11985 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_LSB 16
11986 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST register field. */
11987 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_MSB 23
11988 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST register field. */
11989 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_WIDTH 8
11990 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST register field value. */
11991 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_SET_MSK 0x00ff0000
11992 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST register field value. */
11993 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_CLR_MSK 0xff00ffff
11994 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST register field is UNKNOWN. */
11995 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_RESET 0x0
11996 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST field value from a register. */
11997 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_GET(value) (((value) & 0x00ff0000) >> 16)
11998 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST register field value suitable for setting the register. */
11999 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_SET(value) (((value) << 16) & 0x00ff0000)
12000 
12001 /*
12002  * Field : cfg_t_param_dqstrk_to_valid
12003  *
12004  * iohmc_ctrl_mmr_top_inst.cfg_t_param_dqstrk_to_valid[7:0]
12005  *
12006  * Name:DQS Tracking Rd to Valid timing for Ranks other than the Last
12007  *
12008  * Description:DQS Tracking Rd to Valid timing for Ranks other than the Last.
12009  *
12010  * Field Access Macros:
12011  *
12012  */
12013 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID register field. */
12014 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LSB 24
12015 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID register field. */
12016 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_MSB 31
12017 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID register field. */
12018 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_WIDTH 8
12019 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID register field value. */
12020 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_SET_MSK 0xff000000
12021 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID register field value. */
12022 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_CLR_MSK 0x00ffffff
12023 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID register field is UNKNOWN. */
12024 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_RESET 0x0
12025 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID field value from a register. */
12026 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_GET(value) (((value) & 0xff000000) >> 24)
12027 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID register field value suitable for setting the register. */
12028 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_SET(value) (((value) << 24) & 0xff000000)
12029 
12030 #ifndef __ASSEMBLY__
12031 /*
12032  * WARNING: The C register and register group struct declarations are provided for
12033  * convenience and illustrative purposes. They should, however, be used with
12034  * caution as the C language standard provides no guarantees about the alignment or
12035  * atomicity of device memory accesses. The recommended practice for coding device
12036  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12037  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12038  * alt_write_dword() functions for 64 bit registers.
12039  *
12040  * The struct declaration for register ALT_MPFE_IOHMC_REG_SBCFG6.
12041  */
12042 struct ALT_MPFE_IOHMC_REG_SBCFG6_s
12043 {
12044  volatile uint32_t cfg_period_dqstrk_interval : 16; /* ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL */
12045  volatile uint32_t cfg_t_param_dqstrk_to_valid_last : 8; /* ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST */
12046  volatile uint32_t cfg_t_param_dqstrk_to_valid : 8; /* ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID */
12047 };
12048 
12049 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SBCFG6. */
12050 typedef struct ALT_MPFE_IOHMC_REG_SBCFG6_s ALT_MPFE_IOHMC_REG_SBCFG6_t;
12051 #endif /* __ASSEMBLY__ */
12052 
12053 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG6 register. */
12054 #define ALT_MPFE_IOHMC_REG_SBCFG6_RESET 0x00000000
12055 /* The byte offset of the ALT_MPFE_IOHMC_REG_SBCFG6 register from the beginning of the component. */
12056 #define ALT_MPFE_IOHMC_REG_SBCFG6_OFST 0x74
12057 
12058 /*
12059  * Register : reg_sbcfg7
12060  *
12061  * Register Layout
12062  *
12063  * Bits | Access | Reset | Description
12064  * :-------|:-------|:--------|:--------------------------------------------------
12065  * [6:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD
12066  * [31:7] | ??? | Unknown | *UNDEFINED*
12067  *
12068  */
12069 /*
12070  * Field : cfg_rfsh_warn_threshold
12071  *
12072  * iohmc_ctrl_mmr_top_inst.cfg_rfsh_warn_threshold[6:0]
12073  *
12074  * Name:Threshold to Warn Refresh is Coming
12075  *
12076  * Description:Threshold to warn a refresh is needed within the number of
12077  * controller clock cycles specified by the threshold.
12078  *
12079  * Field Access Macros:
12080  *
12081  */
12082 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD register field. */
12083 #define ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD_LSB 0
12084 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD register field. */
12085 #define ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD_MSB 6
12086 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD register field. */
12087 #define ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD_WIDTH 7
12088 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD register field value. */
12089 #define ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD_SET_MSK 0x0000007f
12090 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD register field value. */
12091 #define ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD_CLR_MSK 0xffffff80
12092 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD register field is UNKNOWN. */
12093 #define ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD_RESET 0x0
12094 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD field value from a register. */
12095 #define ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD_GET(value) (((value) & 0x0000007f) >> 0)
12096 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD register field value suitable for setting the register. */
12097 #define ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD_SET(value) (((value) << 0) & 0x0000007f)
12098 
12099 #ifndef __ASSEMBLY__
12100 /*
12101  * WARNING: The C register and register group struct declarations are provided for
12102  * convenience and illustrative purposes. They should, however, be used with
12103  * caution as the C language standard provides no guarantees about the alignment or
12104  * atomicity of device memory accesses. The recommended practice for coding device
12105  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12106  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12107  * alt_write_dword() functions for 64 bit registers.
12108  *
12109  * The struct declaration for register ALT_MPFE_IOHMC_REG_SBCFG7.
12110  */
12111 struct ALT_MPFE_IOHMC_REG_SBCFG7_s
12112 {
12113  volatile uint32_t cfg_rfsh_warn_threshold : 7; /* ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD */
12114  uint32_t : 25; /* *UNDEFINED* */
12115 };
12116 
12117 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SBCFG7. */
12118 typedef struct ALT_MPFE_IOHMC_REG_SBCFG7_s ALT_MPFE_IOHMC_REG_SBCFG7_t;
12119 #endif /* __ASSEMBLY__ */
12120 
12121 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG7 register. */
12122 #define ALT_MPFE_IOHMC_REG_SBCFG7_RESET 0x00000000
12123 /* The byte offset of the ALT_MPFE_IOHMC_REG_SBCFG7 register from the beginning of the component. */
12124 #define ALT_MPFE_IOHMC_REG_SBCFG7_OFST 0x78
12125 
12126 /*
12127  * Register : reg_caltiming0
12128  *
12129  * Register Layout
12130  *
12131  * Bits | Access | Reset | Description
12132  * :--------|:-------|:--------|:---------------------------------------------------------------
12133  * [5:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR
12134  * [11:6] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH
12135  * [17:12] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT
12136  * [23:18] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK
12137  * [29:24] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG
12138  * [31:30] | ??? | Unknown | *UNDEFINED*
12139  *
12140  */
12141 /*
12142  * Field : cfg_t_param_act_to_rdwr
12143  *
12144  * iohmc_ctrl_mmr_top_inst.cfg_t_param_act_to_rdwr[5:0]
12145  *
12146  * Name:Act to RW Timing
12147  *
12148  * Description:Activate to Read/write command timing.
12149  *
12150  * Field Access Macros:
12151  *
12152  */
12153 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR register field. */
12154 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_LSB 0
12155 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR register field. */
12156 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_MSB 5
12157 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR register field. */
12158 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_WIDTH 6
12159 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR register field value. */
12160 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_SET_MSK 0x0000003f
12161 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR register field value. */
12162 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_CLR_MSK 0xffffffc0
12163 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR register field is UNKNOWN. */
12164 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_RESET 0x0
12165 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR field value from a register. */
12166 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_GET(value) (((value) & 0x0000003f) >> 0)
12167 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR register field value suitable for setting the register. */
12168 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_SET(value) (((value) << 0) & 0x0000003f)
12169 
12170 /*
12171  * Field : cfg_t_param_act_to_pch
12172  *
12173  * iohmc_ctrl_mmr_top_inst.cfg_t_param_act_to_pch[5:0]
12174  *
12175  * Name:Act to Precharge Timing
12176  *
12177  * Description:Activate to Precharge Timing.
12178  *
12179  * Field Access Macros:
12180  *
12181  */
12182 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH register field. */
12183 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_LSB 6
12184 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH register field. */
12185 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_MSB 11
12186 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH register field. */
12187 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_WIDTH 6
12188 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH register field value. */
12189 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_SET_MSK 0x00000fc0
12190 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH register field value. */
12191 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_CLR_MSK 0xfffff03f
12192 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH register field is UNKNOWN. */
12193 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_RESET 0x0
12194 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH field value from a register. */
12195 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_GET(value) (((value) & 0x00000fc0) >> 6)
12196 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH register field value suitable for setting the register. */
12197 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_SET(value) (((value) << 6) & 0x00000fc0)
12198 
12199 /*
12200  * Field : cfg_t_param_act_to_act
12201  *
12202  * iohmc_ctrl_mmr_top_inst.cfg_t_param_act_to_act[5:0]
12203  *
12204  * Name:Act to Act Same Bank
12205  *
12206  * Description:Active to activate timing on same bank.
12207  *
12208  * Field Access Macros:
12209  *
12210  */
12211 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT register field. */
12212 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_LSB 12
12213 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT register field. */
12214 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_MSB 17
12215 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT register field. */
12216 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_WIDTH 6
12217 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT register field value. */
12218 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_SET_MSK 0x0003f000
12219 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT register field value. */
12220 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_CLR_MSK 0xfffc0fff
12221 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT register field is UNKNOWN. */
12222 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_RESET 0x0
12223 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT field value from a register. */
12224 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_GET(value) (((value) & 0x0003f000) >> 12)
12225 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT register field value suitable for setting the register. */
12226 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_SET(value) (((value) << 12) & 0x0003f000)
12227 
12228 /*
12229  * Field : cfg_t_param_act_to_act_diff_bank
12230  *
12231  * iohmc_ctrl_mmr_top_inst.cfg_t_param_act_to_act_diff_bank[5:0]
12232  *
12233  * Name:Act to Act Diff Bank
12234  *
12235  * Description:Active to activate timing on different banks, for DDR4 same bank
12236  * group.
12237  *
12238  * Field Access Macros:
12239  *
12240  */
12241 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK register field. */
12242 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_LSB 18
12243 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK register field. */
12244 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_MSB 23
12245 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK register field. */
12246 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH 6
12247 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK register field value. */
12248 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_SET_MSK 0x00fc0000
12249 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK register field value. */
12250 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_CLR_MSK 0xff03ffff
12251 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK register field is UNKNOWN. */
12252 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_RESET 0x0
12253 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK field value from a register. */
12254 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_GET(value) (((value) & 0x00fc0000) >> 18)
12255 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK register field value suitable for setting the register. */
12256 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_SET(value) (((value) << 18) & 0x00fc0000)
12257 
12258 /*
12259  * Field : cfg_t_param_act_to_act_diff_bg
12260  *
12261  * iohmc_ctrl_mmr_top_inst.cfg_t_param_act_to_act_diff_bg[5:0]
12262  *
12263  * Name:Act to Act Diff Bank Group
12264  *
12265  * Description:Active to activate timing on different bank groups, DDR4 only.
12266  *
12267  * Field Access Macros:
12268  *
12269  */
12270 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG register field. */
12271 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_LSB 24
12272 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG register field. */
12273 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_MSB 29
12274 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG register field. */
12275 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_WIDTH 6
12276 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG register field value. */
12277 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_SET_MSK 0x3f000000
12278 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG register field value. */
12279 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_CLR_MSK 0xc0ffffff
12280 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG register field is UNKNOWN. */
12281 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_RESET 0x0
12282 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG field value from a register. */
12283 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_GET(value) (((value) & 0x3f000000) >> 24)
12284 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG register field value suitable for setting the register. */
12285 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_SET(value) (((value) << 24) & 0x3f000000)
12286 
12287 #ifndef __ASSEMBLY__
12288 /*
12289  * WARNING: The C register and register group struct declarations are provided for
12290  * convenience and illustrative purposes. They should, however, be used with
12291  * caution as the C language standard provides no guarantees about the alignment or
12292  * atomicity of device memory accesses. The recommended practice for coding device
12293  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12294  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12295  * alt_write_dword() functions for 64 bit registers.
12296  *
12297  * The struct declaration for register ALT_MPFE_IOHMC_REG_CALTIMING0.
12298  */
12299 struct ALT_MPFE_IOHMC_REG_CALTIMING0_s
12300 {
12301  volatile uint32_t cfg_t_param_act_to_rdwr : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR */
12302  volatile uint32_t cfg_t_param_act_to_pch : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH */
12303  volatile uint32_t cfg_t_param_act_to_act : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT */
12304  volatile uint32_t cfg_t_param_act_to_act_diff_bank : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK */
12305  volatile uint32_t cfg_t_param_act_to_act_diff_bg : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG */
12306  uint32_t : 2; /* *UNDEFINED* */
12307 };
12308 
12309 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_CALTIMING0. */
12310 typedef struct ALT_MPFE_IOHMC_REG_CALTIMING0_s ALT_MPFE_IOHMC_REG_CALTIMING0_t;
12311 #endif /* __ASSEMBLY__ */
12312 
12313 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING0 register. */
12314 #define ALT_MPFE_IOHMC_REG_CALTIMING0_RESET 0x00000000
12315 /* The byte offset of the ALT_MPFE_IOHMC_REG_CALTIMING0 register from the beginning of the component. */
12316 #define ALT_MPFE_IOHMC_REG_CALTIMING0_OFST 0x7c
12317 
12318 /*
12319  * Register : reg_caltiming1
12320  *
12321  * Register Layout
12322  *
12323  * Bits | Access | Reset | Description
12324  * :--------|:-------|:--------|:-------------------------------------------------------------
12325  * [5:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD
12326  * [11:6] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP
12327  * [17:12] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG
12328  * [23:18] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR
12329  * [29:24] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP
12330  * [31:30] | ??? | Unknown | *UNDEFINED*
12331  *
12332  */
12333 /*
12334  * Field : cfg_t_param_rd_to_rd
12335  *
12336  * iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_to_rd[5:0]
12337  *
12338  * Name:Rd to Rd Same Bank
12339  *
12340  * Description:Read to read command timing on same bank.
12341  *
12342  * Field Access Macros:
12343  *
12344  */
12345 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD register field. */
12346 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_LSB 0
12347 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD register field. */
12348 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_MSB 5
12349 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD register field. */
12350 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_WIDTH 6
12351 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD register field value. */
12352 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_SET_MSK 0x0000003f
12353 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD register field value. */
12354 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_CLR_MSK 0xffffffc0
12355 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD register field is UNKNOWN. */
12356 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_RESET 0x0
12357 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD field value from a register. */
12358 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_GET(value) (((value) & 0x0000003f) >> 0)
12359 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD register field value suitable for setting the register. */
12360 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_SET(value) (((value) << 0) & 0x0000003f)
12361 
12362 /*
12363  * Field : cfg_t_param_rd_to_rd_diff_chip
12364  *
12365  * iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_to_rd_diff_chip[5:0]
12366  *
12367  * Name:Rd to Rd Diff Chip
12368  *
12369  * Description:Read to read command timing on different chips.
12370  *
12371  * Field Access Macros:
12372  *
12373  */
12374 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP register field. */
12375 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_LSB 6
12376 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP register field. */
12377 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_MSB 11
12378 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP register field. */
12379 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH 6
12380 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP register field value. */
12381 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_SET_MSK 0x00000fc0
12382 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP register field value. */
12383 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_CLR_MSK 0xfffff03f
12384 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP register field is UNKNOWN. */
12385 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_RESET 0x0
12386 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP field value from a register. */
12387 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_GET(value) (((value) & 0x00000fc0) >> 6)
12388 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP register field value suitable for setting the register. */
12389 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_SET(value) (((value) << 6) & 0x00000fc0)
12390 
12391 /*
12392  * Field : cfg_t_param_rd_to_rd_diff_bg
12393  *
12394  * iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_to_rd_diff_bg[5:0]
12395  *
12396  * Name:Rd to Rd Diff Bank Group
12397  *
12398  * Description:Read to read command timing on different bank groups, DDR4 only.
12399  *
12400  * Field Access Macros:
12401  *
12402  */
12403 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG register field. */
12404 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_LSB 12
12405 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG register field. */
12406 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_MSB 17
12407 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG register field. */
12408 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_WIDTH 6
12409 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG register field value. */
12410 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_SET_MSK 0x0003f000
12411 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG register field value. */
12412 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_CLR_MSK 0xfffc0fff
12413 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG register field is UNKNOWN. */
12414 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_RESET 0x0
12415 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG field value from a register. */
12416 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_GET(value) (((value) & 0x0003f000) >> 12)
12417 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG register field value suitable for setting the register. */
12418 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_SET(value) (((value) << 12) & 0x0003f000)
12419 
12420 /*
12421  * Field : cfg_t_param_rd_to_wr
12422  *
12423  * iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_to_wr[5:0]
12424  *
12425  * Name:Rd to Wr Same Bank
12426  *
12427  * Description:Write to read command timing on same bank.
12428  *
12429  * Field Access Macros:
12430  *
12431  */
12432 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR register field. */
12433 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_LSB 18
12434 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR register field. */
12435 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_MSB 23
12436 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR register field. */
12437 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_WIDTH 6
12438 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR register field value. */
12439 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_SET_MSK 0x00fc0000
12440 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR register field value. */
12441 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_CLR_MSK 0xff03ffff
12442 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR register field is UNKNOWN. */
12443 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_RESET 0x0
12444 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR field value from a register. */
12445 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_GET(value) (((value) & 0x00fc0000) >> 18)
12446 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR register field value suitable for setting the register. */
12447 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_SET(value) (((value) << 18) & 0x00fc0000)
12448 
12449 /*
12450  * Field : cfg_t_param_rd_to_wr_diff_chip
12451  *
12452  * iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_to_wr_diff_chip[5:0]
12453  *
12454  * Name:Rd to Wr Diff Chip
12455  *
12456  * Description:Read to write command timing on different chips.
12457  *
12458  * Field Access Macros:
12459  *
12460  */
12461 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP register field. */
12462 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_LSB 24
12463 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP register field. */
12464 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_MSB 29
12465 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP register field. */
12466 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH 6
12467 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP register field value. */
12468 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_SET_MSK 0x3f000000
12469 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP register field value. */
12470 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_CLR_MSK 0xc0ffffff
12471 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP register field is UNKNOWN. */
12472 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_RESET 0x0
12473 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP field value from a register. */
12474 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_GET(value) (((value) & 0x3f000000) >> 24)
12475 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP register field value suitable for setting the register. */
12476 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_SET(value) (((value) << 24) & 0x3f000000)
12477 
12478 #ifndef __ASSEMBLY__
12479 /*
12480  * WARNING: The C register and register group struct declarations are provided for
12481  * convenience and illustrative purposes. They should, however, be used with
12482  * caution as the C language standard provides no guarantees about the alignment or
12483  * atomicity of device memory accesses. The recommended practice for coding device
12484  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12485  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12486  * alt_write_dword() functions for 64 bit registers.
12487  *
12488  * The struct declaration for register ALT_MPFE_IOHMC_REG_CALTIMING1.
12489  */
12490 struct ALT_MPFE_IOHMC_REG_CALTIMING1_s
12491 {
12492  volatile uint32_t cfg_t_param_rd_to_rd : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD */
12493  volatile uint32_t cfg_t_param_rd_to_rd_diff_chip : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP */
12494  volatile uint32_t cfg_t_param_rd_to_rd_diff_bg : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG */
12495  volatile uint32_t cfg_t_param_rd_to_wr : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR */
12496  volatile uint32_t cfg_t_param_rd_to_wr_diff_chip : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP */
12497  uint32_t : 2; /* *UNDEFINED* */
12498 };
12499 
12500 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_CALTIMING1. */
12501 typedef struct ALT_MPFE_IOHMC_REG_CALTIMING1_s ALT_MPFE_IOHMC_REG_CALTIMING1_t;
12502 #endif /* __ASSEMBLY__ */
12503 
12504 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING1 register. */
12505 #define ALT_MPFE_IOHMC_REG_CALTIMING1_RESET 0x00000000
12506 /* The byte offset of the ALT_MPFE_IOHMC_REG_CALTIMING1 register from the beginning of the component. */
12507 #define ALT_MPFE_IOHMC_REG_CALTIMING1_OFST 0x80
12508 
12509 /*
12510  * Register : reg_caltiming2
12511  *
12512  * Register Layout
12513  *
12514  * Bits | Access | Reset | Description
12515  * :--------|:-------|:--------|:-------------------------------------------------------------
12516  * [5:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG
12517  * [11:6] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH
12518  * [17:12] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID
12519  * [23:18] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR
12520  * [29:24] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP
12521  * [31:30] | ??? | Unknown | *UNDEFINED*
12522  *
12523  */
12524 /*
12525  * Field : cfg_t_param_rd_to_wr_diff_bg
12526  *
12527  * iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_to_wr_diff_bg[5:0]
12528  *
12529  * Name:Rd to Wr Diff Bank Group
12530  *
12531  * Description:Read to write command timing on different bank groups, DDR4 only.
12532  *
12533  * Field Access Macros:
12534  *
12535  */
12536 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG register field. */
12537 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_LSB 0
12538 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG register field. */
12539 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_MSB 5
12540 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG register field. */
12541 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_WIDTH 6
12542 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG register field value. */
12543 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_SET_MSK 0x0000003f
12544 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG register field value. */
12545 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_CLR_MSK 0xffffffc0
12546 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG register field is UNKNOWN. */
12547 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_RESET 0x0
12548 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG field value from a register. */
12549 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_GET(value) (((value) & 0x0000003f) >> 0)
12550 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG register field value suitable for setting the register. */
12551 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_SET(value) (((value) << 0) & 0x0000003f)
12552 
12553 /*
12554  * Field : cfg_t_param_rd_to_pch
12555  *
12556  * iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_to_pch[5:0]
12557  *
12558  * Name:Rd to Precharge
12559  *
12560  * Description:Read to precharge command timing.
12561  *
12562  * Field Access Macros:
12563  *
12564  */
12565 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH register field. */
12566 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_LSB 6
12567 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH register field. */
12568 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_MSB 11
12569 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH register field. */
12570 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_WIDTH 6
12571 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH register field value. */
12572 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_SET_MSK 0x00000fc0
12573 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH register field value. */
12574 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_CLR_MSK 0xfffff03f
12575 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH register field is UNKNOWN. */
12576 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_RESET 0x0
12577 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH field value from a register. */
12578 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_GET(value) (((value) & 0x00000fc0) >> 6)
12579 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH register field value suitable for setting the register. */
12580 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_SET(value) (((value) << 6) & 0x00000fc0)
12581 
12582 /*
12583  * Field : cfg_t_param_rd_ap_to_valid
12584  *
12585  * iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_ap_to_valid[5:0]
12586  *
12587  * Name:Rd with Auto Precharge to Valid Cmd
12588  *
12589  * Description:Read command with autoprecharge to data valid timing.
12590  *
12591  * Field Access Macros:
12592  *
12593  */
12594 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID register field. */
12595 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_LSB 12
12596 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID register field. */
12597 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_MSB 17
12598 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID register field. */
12599 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_WIDTH 6
12600 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID register field value. */
12601 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_SET_MSK 0x0003f000
12602 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID register field value. */
12603 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_CLR_MSK 0xfffc0fff
12604 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID register field is UNKNOWN. */
12605 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_RESET 0x0
12606 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID field value from a register. */
12607 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_GET(value) (((value) & 0x0003f000) >> 12)
12608 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID register field value suitable for setting the register. */
12609 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_SET(value) (((value) << 12) & 0x0003f000)
12610 
12611 /*
12612  * Field : cfg_t_param_wr_to_wr
12613  *
12614  * iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_to_wr[5:0]
12615  *
12616  * Name:Wr to Wr Same bank
12617  *
12618  * Description:Write to write command timing on same bank.
12619  *
12620  * Field Access Macros:
12621  *
12622  */
12623 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR register field. */
12624 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_LSB 18
12625 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR register field. */
12626 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_MSB 23
12627 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR register field. */
12628 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_WIDTH 6
12629 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR register field value. */
12630 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_SET_MSK 0x00fc0000
12631 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR register field value. */
12632 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_CLR_MSK 0xff03ffff
12633 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR register field is UNKNOWN. */
12634 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_RESET 0x0
12635 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR field value from a register. */
12636 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_GET(value) (((value) & 0x00fc0000) >> 18)
12637 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR register field value suitable for setting the register. */
12638 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_SET(value) (((value) << 18) & 0x00fc0000)
12639 
12640 /*
12641  * Field : cfg_t_param_wr_to_wr_diff_chip
12642  *
12643  * iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_to_wr_diff_chip[5:0]
12644  *
12645  * Name:Wr to Wr Diff Chip
12646  *
12647  * Description:Write to write command timing on different chips.
12648  *
12649  * Field Access Macros:
12650  *
12651  */
12652 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP register field. */
12653 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_LSB 24
12654 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP register field. */
12655 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_MSB 29
12656 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP register field. */
12657 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH 6
12658 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP register field value. */
12659 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_SET_MSK 0x3f000000
12660 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP register field value. */
12661 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_CLR_MSK 0xc0ffffff
12662 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP register field is UNKNOWN. */
12663 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_RESET 0x0
12664 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP field value from a register. */
12665 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_GET(value) (((value) & 0x3f000000) >> 24)
12666 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP register field value suitable for setting the register. */
12667 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_SET(value) (((value) << 24) & 0x3f000000)
12668 
12669 #ifndef __ASSEMBLY__
12670 /*
12671  * WARNING: The C register and register group struct declarations are provided for
12672  * convenience and illustrative purposes. They should, however, be used with
12673  * caution as the C language standard provides no guarantees about the alignment or
12674  * atomicity of device memory accesses. The recommended practice for coding device
12675  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12676  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12677  * alt_write_dword() functions for 64 bit registers.
12678  *
12679  * The struct declaration for register ALT_MPFE_IOHMC_REG_CALTIMING2.
12680  */
12681 struct ALT_MPFE_IOHMC_REG_CALTIMING2_s
12682 {
12683  volatile uint32_t cfg_t_param_rd_to_wr_diff_bg : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG */
12684  volatile uint32_t cfg_t_param_rd_to_pch : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH */
12685  volatile uint32_t cfg_t_param_rd_ap_to_valid : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID */
12686  volatile uint32_t cfg_t_param_wr_to_wr : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR */
12687  volatile uint32_t cfg_t_param_wr_to_wr_diff_chip : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP */
12688  uint32_t : 2; /* *UNDEFINED* */
12689 };
12690 
12691 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_CALTIMING2. */
12692 typedef struct ALT_MPFE_IOHMC_REG_CALTIMING2_s ALT_MPFE_IOHMC_REG_CALTIMING2_t;
12693 #endif /* __ASSEMBLY__ */
12694 
12695 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING2 register. */
12696 #define ALT_MPFE_IOHMC_REG_CALTIMING2_RESET 0x00000000
12697 /* The byte offset of the ALT_MPFE_IOHMC_REG_CALTIMING2 register from the beginning of the component. */
12698 #define ALT_MPFE_IOHMC_REG_CALTIMING2_OFST 0x84
12699 
12700 /*
12701  * Register : reg_caltiming3
12702  *
12703  * Register Layout
12704  *
12705  * Bits | Access | Reset | Description
12706  * :--------|:-------|:--------|:-------------------------------------------------------------
12707  * [5:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG
12708  * [11:6] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD
12709  * [17:12] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP
12710  * [23:18] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG
12711  * [29:24] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH
12712  * [31:30] | ??? | Unknown | *UNDEFINED*
12713  *
12714  */
12715 /*
12716  * Field : cfg_t_param_wr_to_wr_diff_bg
12717  *
12718  * iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_to_wr_diff_bg[5:0]
12719  *
12720  * Name:Wr to Wr Diff Bank Group
12721  *
12722  * Description:Write to write command timing on different bank groups, DDR4 only.
12723  *
12724  * Field Access Macros:
12725  *
12726  */
12727 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG register field. */
12728 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_LSB 0
12729 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG register field. */
12730 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_MSB 5
12731 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG register field. */
12732 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_WIDTH 6
12733 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG register field value. */
12734 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_SET_MSK 0x0000003f
12735 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG register field value. */
12736 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_CLR_MSK 0xffffffc0
12737 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG register field is UNKNOWN. */
12738 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_RESET 0x0
12739 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG field value from a register. */
12740 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_GET(value) (((value) & 0x0000003f) >> 0)
12741 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG register field value suitable for setting the register. */
12742 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_SET(value) (((value) << 0) & 0x0000003f)
12743 
12744 /*
12745  * Field : cfg_t_param_wr_to_rd
12746  *
12747  * iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_to_rd[5:0]
12748  *
12749  * Name:Wr to Rd Same Bank
12750  *
12751  * Description:Write to read command timing.
12752  *
12753  * Field Access Macros:
12754  *
12755  */
12756 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD register field. */
12757 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_LSB 6
12758 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD register field. */
12759 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_MSB 11
12760 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD register field. */
12761 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_WIDTH 6
12762 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD register field value. */
12763 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_SET_MSK 0x00000fc0
12764 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD register field value. */
12765 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_CLR_MSK 0xfffff03f
12766 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD register field is UNKNOWN. */
12767 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_RESET 0x0
12768 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD field value from a register. */
12769 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_GET(value) (((value) & 0x00000fc0) >> 6)
12770 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD register field value suitable for setting the register. */
12771 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_SET(value) (((value) << 6) & 0x00000fc0)
12772 
12773 /*
12774  * Field : cfg_t_param_wr_to_rd_diff_chip
12775  *
12776  * iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_to_rd_diff_chip[5:0]
12777  *
12778  * Name:Wr to Rd Diff Chip
12779  *
12780  * Description:Write to read command timing on different chips.
12781  *
12782  * Field Access Macros:
12783  *
12784  */
12785 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP register field. */
12786 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_LSB 12
12787 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP register field. */
12788 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_MSB 17
12789 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP register field. */
12790 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH 6
12791 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP register field value. */
12792 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_SET_MSK 0x0003f000
12793 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP register field value. */
12794 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_CLR_MSK 0xfffc0fff
12795 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP register field is UNKNOWN. */
12796 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_RESET 0x0
12797 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP field value from a register. */
12798 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_GET(value) (((value) & 0x0003f000) >> 12)
12799 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP register field value suitable for setting the register. */
12800 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_SET(value) (((value) << 12) & 0x0003f000)
12801 
12802 /*
12803  * Field : cfg_t_param_wr_to_rd_diff_bg
12804  *
12805  * iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_to_rd_diff_bg[5:0]
12806  *
12807  * Name:Wr to Rd Diff bank Group
12808  *
12809  * Description:Write to read command timing on different bank groups, DDR4 only.
12810  *
12811  * Field Access Macros:
12812  *
12813  */
12814 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG register field. */
12815 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_LSB 18
12816 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG register field. */
12817 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_MSB 23
12818 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG register field. */
12819 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_WIDTH 6
12820 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG register field value. */
12821 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_SET_MSK 0x00fc0000
12822 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG register field value. */
12823 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_CLR_MSK 0xff03ffff
12824 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG register field is UNKNOWN. */
12825 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_RESET 0x0
12826 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG field value from a register. */
12827 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_GET(value) (((value) & 0x00fc0000) >> 18)
12828 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG register field value suitable for setting the register. */
12829 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_SET(value) (((value) << 18) & 0x00fc0000)
12830 
12831 /*
12832  * Field : cfg_t_param_wr_to_pch
12833  *
12834  * iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_to_pch[5:0]
12835  *
12836  * Name:Wr to Precharge
12837  *
12838  * Description:Write to precharge command timing.
12839  *
12840  * Field Access Macros:
12841  *
12842  */
12843 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH register field. */
12844 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_LSB 24
12845 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH register field. */
12846 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_MSB 29
12847 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH register field. */
12848 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_WIDTH 6
12849 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH register field value. */
12850 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_SET_MSK 0x3f000000
12851 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH register field value. */
12852 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_CLR_MSK 0xc0ffffff
12853 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH register field is UNKNOWN. */
12854 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_RESET 0x0
12855 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH field value from a register. */
12856 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_GET(value) (((value) & 0x3f000000) >> 24)
12857 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH register field value suitable for setting the register. */
12858 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_SET(value) (((value) << 24) & 0x3f000000)
12859 
12860 #ifndef __ASSEMBLY__
12861 /*
12862  * WARNING: The C register and register group struct declarations are provided for
12863  * convenience and illustrative purposes. They should, however, be used with
12864  * caution as the C language standard provides no guarantees about the alignment or
12865  * atomicity of device memory accesses. The recommended practice for coding device
12866  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12867  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12868  * alt_write_dword() functions for 64 bit registers.
12869  *
12870  * The struct declaration for register ALT_MPFE_IOHMC_REG_CALTIMING3.
12871  */
12872 struct ALT_MPFE_IOHMC_REG_CALTIMING3_s
12873 {
12874  volatile uint32_t cfg_t_param_wr_to_wr_diff_bg : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG */
12875  volatile uint32_t cfg_t_param_wr_to_rd : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD */
12876  volatile uint32_t cfg_t_param_wr_to_rd_diff_chip : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP */
12877  volatile uint32_t cfg_t_param_wr_to_rd_diff_bg : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG */
12878  volatile uint32_t cfg_t_param_wr_to_pch : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH */
12879  uint32_t : 2; /* *UNDEFINED* */
12880 };
12881 
12882 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_CALTIMING3. */
12883 typedef struct ALT_MPFE_IOHMC_REG_CALTIMING3_s ALT_MPFE_IOHMC_REG_CALTIMING3_t;
12884 #endif /* __ASSEMBLY__ */
12885 
12886 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING3 register. */
12887 #define ALT_MPFE_IOHMC_REG_CALTIMING3_RESET 0x00000000
12888 /* The byte offset of the ALT_MPFE_IOHMC_REG_CALTIMING3 register from the beginning of the component. */
12889 #define ALT_MPFE_IOHMC_REG_CALTIMING3_OFST 0x88
12890 
12891 /*
12892  * Register : reg_caltiming4
12893  *
12894  * Register Layout
12895  *
12896  * Bits | Access | Reset | Description
12897  * :--------|:-------|:--------|:-----------------------------------------------------------
12898  * [5:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID
12899  * [11:6] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID
12900  * [17:12] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID
12901  * [25:18] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID
12902  * [31:26] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID
12903  *
12904  */
12905 /*
12906  * Field : cfg_t_param_wr_ap_to_valid
12907  *
12908  * iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_ap_to_valid[5:0]
12909  *
12910  * Name:Wr with Auto Precharge to Valid
12911  *
12912  * Description:Write with autoprecharge to valid command timing.
12913  *
12914  * Field Access Macros:
12915  *
12916  */
12917 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID register field. */
12918 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_LSB 0
12919 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID register field. */
12920 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_MSB 5
12921 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID register field. */
12922 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_WIDTH 6
12923 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID register field value. */
12924 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_SET_MSK 0x0000003f
12925 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID register field value. */
12926 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_CLR_MSK 0xffffffc0
12927 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID register field is UNKNOWN. */
12928 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_RESET 0x0
12929 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID field value from a register. */
12930 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_GET(value) (((value) & 0x0000003f) >> 0)
12931 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID register field value suitable for setting the register. */
12932 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_SET(value) (((value) << 0) & 0x0000003f)
12933 
12934 /*
12935  * Field : cfg_t_param_pch_to_valid
12936  *
12937  * iohmc_ctrl_mmr_top_inst.cfg_t_param_pch_to_valid[5:0]
12938  *
12939  * Name:Precharge to Valid
12940  *
12941  * Description:Precharge to valid command timing.
12942  *
12943  * Field Access Macros:
12944  *
12945  */
12946 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID register field. */
12947 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_LSB 6
12948 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID register field. */
12949 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_MSB 11
12950 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID register field. */
12951 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_WIDTH 6
12952 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID register field value. */
12953 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_SET_MSK 0x00000fc0
12954 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID register field value. */
12955 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_CLR_MSK 0xfffff03f
12956 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID register field is UNKNOWN. */
12957 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_RESET 0x0
12958 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID field value from a register. */
12959 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_GET(value) (((value) & 0x00000fc0) >> 6)
12960 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID register field value suitable for setting the register. */
12961 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_SET(value) (((value) << 6) & 0x00000fc0)
12962 
12963 /*
12964  * Field : cfg_t_param_pch_all_to_valid
12965  *
12966  * iohmc_ctrl_mmr_top_inst.cfg_t_param_pch_all_to_valid[5:0]
12967  *
12968  * Name:Precharge All to Valid
12969  *
12970  * Description:Precharge all to banks being ready for bank activation command.
12971  *
12972  * Field Access Macros:
12973  *
12974  */
12975 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID register field. */
12976 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_LSB 12
12977 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID register field. */
12978 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_MSB 17
12979 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID register field. */
12980 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_WIDTH 6
12981 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID register field value. */
12982 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_SET_MSK 0x0003f000
12983 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID register field value. */
12984 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_CLR_MSK 0xfffc0fff
12985 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID register field is UNKNOWN. */
12986 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_RESET 0x0
12987 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID field value from a register. */
12988 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_GET(value) (((value) & 0x0003f000) >> 12)
12989 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID register field value suitable for setting the register. */
12990 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_SET(value) (((value) << 12) & 0x0003f000)
12991 
12992 /*
12993  * Field : cfg_t_param_arf_to_valid
12994  *
12995  * iohmc_ctrl_mmr_top_inst.cfg_t_param_arf_to_valid[7:0]
12996  *
12997  * Name:Auto Refresh to Valid
12998  *
12999  * Description:Auto Refresh to valid DRAM command window. When operating in DDR4
13000  * 3DS mode, this register serves as the SLR (same logical rank) variant of tRFC.
13001  *
13002  * Field Access Macros:
13003  *
13004  */
13005 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID register field. */
13006 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_LSB 18
13007 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID register field. */
13008 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_MSB 25
13009 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID register field. */
13010 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_WIDTH 8
13011 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID register field value. */
13012 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_SET_MSK 0x03fc0000
13013 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID register field value. */
13014 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_CLR_MSK 0xfc03ffff
13015 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID register field is UNKNOWN. */
13016 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_RESET 0x0
13017 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID field value from a register. */
13018 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_GET(value) (((value) & 0x03fc0000) >> 18)
13019 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID register field value suitable for setting the register. */
13020 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_SET(value) (((value) << 18) & 0x03fc0000)
13021 
13022 /*
13023  * Field : cfg_t_param_pdn_to_valid
13024  *
13025  * iohmc_ctrl_mmr_top_inst.cfg_t_param_pdn_to_valid[5:0]
13026  *
13027  * Name:Power Down to Valid
13028  *
13029  * Description:Power down to valid bank command window.
13030  *
13031  * Field Access Macros:
13032  *
13033  */
13034 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID register field. */
13035 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_LSB 26
13036 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID register field. */
13037 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_MSB 31
13038 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID register field. */
13039 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_WIDTH 6
13040 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID register field value. */
13041 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_SET_MSK 0xfc000000
13042 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID register field value. */
13043 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_CLR_MSK 0x03ffffff
13044 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID register field is UNKNOWN. */
13045 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_RESET 0x0
13046 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID field value from a register. */
13047 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_GET(value) (((value) & 0xfc000000) >> 26)
13048 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID register field value suitable for setting the register. */
13049 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_SET(value) (((value) << 26) & 0xfc000000)
13050 
13051 #ifndef __ASSEMBLY__
13052 /*
13053  * WARNING: The C register and register group struct declarations are provided for
13054  * convenience and illustrative purposes. They should, however, be used with
13055  * caution as the C language standard provides no guarantees about the alignment or
13056  * atomicity of device memory accesses. The recommended practice for coding device
13057  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13058  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13059  * alt_write_dword() functions for 64 bit registers.
13060  *
13061  * The struct declaration for register ALT_MPFE_IOHMC_REG_CALTIMING4.
13062  */
13063 struct ALT_MPFE_IOHMC_REG_CALTIMING4_s
13064 {
13065  volatile uint32_t cfg_t_param_wr_ap_to_valid : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID */
13066  volatile uint32_t cfg_t_param_pch_to_valid : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID */
13067  volatile uint32_t cfg_t_param_pch_all_to_valid : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID */
13068  volatile uint32_t cfg_t_param_arf_to_valid : 8; /* ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID */
13069  volatile uint32_t cfg_t_param_pdn_to_valid : 6; /* ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID */
13070 };
13071 
13072 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_CALTIMING4. */
13073 typedef struct ALT_MPFE_IOHMC_REG_CALTIMING4_s ALT_MPFE_IOHMC_REG_CALTIMING4_t;
13074 #endif /* __ASSEMBLY__ */
13075 
13076 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING4 register. */
13077 #define ALT_MPFE_IOHMC_REG_CALTIMING4_RESET 0x00000000
13078 /* The byte offset of the ALT_MPFE_IOHMC_REG_CALTIMING4 register from the beginning of the component. */
13079 #define ALT_MPFE_IOHMC_REG_CALTIMING4_OFST 0x8c
13080 
13081 /*
13082  * Register : reg_caltiming5
13083  *
13084  * Register Layout
13085  *
13086  * Bits | Access | Reset | Description
13087  * :--------|:-------|:--------|:--------------------------------------------------------
13088  * [9:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID
13089  * [19:10] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL
13090  * [31:20] | ??? | Unknown | *UNDEFINED*
13091  *
13092  */
13093 /*
13094  * Field : cfg_t_param_srf_to_valid
13095  *
13096  * iohmc_ctrl_mmr_top_inst.cfg_t_param_srf_to_valid[9:0]
13097  *
13098  * Name:Self Refresh to Valid
13099  *
13100  * Description:Self-refresh to valid bank command window.
13101  *
13102  * Field Access Macros:
13103  *
13104  */
13105 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID register field. */
13106 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_LSB 0
13107 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID register field. */
13108 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_MSB 9
13109 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID register field. */
13110 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_WIDTH 10
13111 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID register field value. */
13112 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_SET_MSK 0x000003ff
13113 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID register field value. */
13114 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_CLR_MSK 0xfffffc00
13115 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID register field is UNKNOWN. */
13116 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_RESET 0x0
13117 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID field value from a register. */
13118 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_GET(value) (((value) & 0x000003ff) >> 0)
13119 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID register field value suitable for setting the register. */
13120 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_SET(value) (((value) << 0) & 0x000003ff)
13121 
13122 /*
13123  * Field : cfg_t_param_srf_to_zq_cal
13124  *
13125  * iohmc_ctrl_mmr_top_inst.cfg_t_param_srf_to_zq_cal[9:0]
13126  *
13127  * Name:Self Refresh to ZQCAL
13128  *
13129  * Description:Self refresh to ZQ calibration window.
13130  *
13131  * Field Access Macros:
13132  *
13133  */
13134 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL register field. */
13135 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_LSB 10
13136 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL register field. */
13137 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_MSB 19
13138 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL register field. */
13139 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_WIDTH 10
13140 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL register field value. */
13141 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_SET_MSK 0x000ffc00
13142 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL register field value. */
13143 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_CLR_MSK 0xfff003ff
13144 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL register field is UNKNOWN. */
13145 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_RESET 0x0
13146 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL field value from a register. */
13147 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_GET(value) (((value) & 0x000ffc00) >> 10)
13148 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL register field value suitable for setting the register. */
13149 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_SET(value) (((value) << 10) & 0x000ffc00)
13150 
13151 #ifndef __ASSEMBLY__
13152 /*
13153  * WARNING: The C register and register group struct declarations are provided for
13154  * convenience and illustrative purposes. They should, however, be used with
13155  * caution as the C language standard provides no guarantees about the alignment or
13156  * atomicity of device memory accesses. The recommended practice for coding device
13157  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13158  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13159  * alt_write_dword() functions for 64 bit registers.
13160  *
13161  * The struct declaration for register ALT_MPFE_IOHMC_REG_CALTIMING5.
13162  */
13163 struct ALT_MPFE_IOHMC_REG_CALTIMING5_s
13164 {
13165  volatile uint32_t cfg_t_param_srf_to_valid : 10; /* ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID */
13166  volatile uint32_t cfg_t_param_srf_to_zq_cal : 10; /* ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL */
13167  uint32_t : 12; /* *UNDEFINED* */
13168 };
13169 
13170 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_CALTIMING5. */
13171 typedef struct ALT_MPFE_IOHMC_REG_CALTIMING5_s ALT_MPFE_IOHMC_REG_CALTIMING5_t;
13172 #endif /* __ASSEMBLY__ */
13173 
13174 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING5 register. */
13175 #define ALT_MPFE_IOHMC_REG_CALTIMING5_RESET 0x00000000
13176 /* The byte offset of the ALT_MPFE_IOHMC_REG_CALTIMING5 register from the beginning of the component. */
13177 #define ALT_MPFE_IOHMC_REG_CALTIMING5_OFST 0x90
13178 
13179 /*
13180  * Register : reg_caltiming6
13181  *
13182  * Register Layout
13183  *
13184  * Bits | Access | Reset | Description
13185  * :--------|:-------|:--------|:-----------------------------------------------------
13186  * [12:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD
13187  * [28:13] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD
13188  * [31:29] | ??? | Unknown | *UNDEFINED*
13189  *
13190  */
13191 /*
13192  * Field : cfg_t_param_arf_period
13193  *
13194  * iohmc_ctrl_mmr_top_inst.cfg_t_param_arf_period[12:0]
13195  *
13196  * Name:Auto Refresh Period
13197  *
13198  * Description:Auto-refresh period.
13199  *
13200  * Field Access Macros:
13201  *
13202  */
13203 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD register field. */
13204 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_LSB 0
13205 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD register field. */
13206 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_MSB 12
13207 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD register field. */
13208 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_WIDTH 13
13209 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD register field value. */
13210 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_SET_MSK 0x00001fff
13211 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD register field value. */
13212 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_CLR_MSK 0xffffe000
13213 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD register field is UNKNOWN. */
13214 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_RESET 0x0
13215 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD field value from a register. */
13216 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_GET(value) (((value) & 0x00001fff) >> 0)
13217 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD register field value suitable for setting the register. */
13218 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_SET(value) (((value) << 0) & 0x00001fff)
13219 
13220 /*
13221  * Field : cfg_t_param_pdn_period
13222  *
13223  * iohmc_ctrl_mmr_top_inst.cfg_t_param_pdn_period[15:0]
13224  *
13225  * Name:Power Down Period
13226  *
13227  * Description:Clock power down recovery period.
13228  *
13229  * Field Access Macros:
13230  *
13231  */
13232 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD register field. */
13233 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_LSB 13
13234 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD register field. */
13235 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_MSB 28
13236 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD register field. */
13237 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_WIDTH 16
13238 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD register field value. */
13239 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_SET_MSK 0x1fffe000
13240 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD register field value. */
13241 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_CLR_MSK 0xe0001fff
13242 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD register field is UNKNOWN. */
13243 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_RESET 0x0
13244 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD field value from a register. */
13245 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_GET(value) (((value) & 0x1fffe000) >> 13)
13246 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD register field value suitable for setting the register. */
13247 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_SET(value) (((value) << 13) & 0x1fffe000)
13248 
13249 #ifndef __ASSEMBLY__
13250 /*
13251  * WARNING: The C register and register group struct declarations are provided for
13252  * convenience and illustrative purposes. They should, however, be used with
13253  * caution as the C language standard provides no guarantees about the alignment or
13254  * atomicity of device memory accesses. The recommended practice for coding device
13255  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13256  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13257  * alt_write_dword() functions for 64 bit registers.
13258  *
13259  * The struct declaration for register ALT_MPFE_IOHMC_REG_CALTIMING6.
13260  */
13261 struct ALT_MPFE_IOHMC_REG_CALTIMING6_s
13262 {
13263  volatile uint32_t cfg_t_param_arf_period : 13; /* ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD */
13264  volatile uint32_t cfg_t_param_pdn_period : 16; /* ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD */
13265  uint32_t : 3; /* *UNDEFINED* */
13266 };
13267 
13268 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_CALTIMING6. */
13269 typedef struct ALT_MPFE_IOHMC_REG_CALTIMING6_s ALT_MPFE_IOHMC_REG_CALTIMING6_t;
13270 #endif /* __ASSEMBLY__ */
13271 
13272 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING6 register. */
13273 #define ALT_MPFE_IOHMC_REG_CALTIMING6_RESET 0x00000000
13274 /* The byte offset of the ALT_MPFE_IOHMC_REG_CALTIMING6 register from the beginning of the component. */
13275 #define ALT_MPFE_IOHMC_REG_CALTIMING6_OFST 0x94
13276 
13277 /*
13278  * Register : reg_caltiming7
13279  *
13280  * Register Layout
13281  *
13282  * Bits | Access | Reset | Description
13283  * :--------|:-------|:--------|:--------------------------------------------------------
13284  * [8:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID
13285  * [15:9] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID
13286  * [19:16] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID
13287  * [29:20] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID
13288  * [31:30] | ??? | Unknown | *UNDEFINED*
13289  *
13290  */
13291 /*
13292  * Field : cfg_t_param_zqcl_to_valid
13293  *
13294  * iohmc_ctrl_mmr_top_inst.cfg_t_param_zqcl_to_valid[8:0]
13295  *
13296  * Name:ZQCAL Long to Valid
13297  *
13298  * Description:Long ZQ calibration to valid.
13299  *
13300  * Field Access Macros:
13301  *
13302  */
13303 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID register field. */
13304 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_LSB 0
13305 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID register field. */
13306 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_MSB 8
13307 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID register field. */
13308 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_WIDTH 9
13309 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID register field value. */
13310 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_SET_MSK 0x000001ff
13311 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID register field value. */
13312 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_CLR_MSK 0xfffffe00
13313 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID register field is UNKNOWN. */
13314 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_RESET 0x0
13315 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID field value from a register. */
13316 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_GET(value) (((value) & 0x000001ff) >> 0)
13317 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID register field value suitable for setting the register. */
13318 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_SET(value) (((value) << 0) & 0x000001ff)
13319 
13320 /*
13321  * Field : cfg_t_param_zqcs_to_valid
13322  *
13323  * iohmc_ctrl_mmr_top_inst.cfg_t_param_zqcs_to_valid[6:0]
13324  *
13325  * Name:ZQCAL Short to Valid
13326  *
13327  * Description:Short ZQ calibration to valid.
13328  *
13329  * Field Access Macros:
13330  *
13331  */
13332 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID register field. */
13333 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_LSB 9
13334 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID register field. */
13335 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_MSB 15
13336 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID register field. */
13337 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_WIDTH 7
13338 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID register field value. */
13339 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_SET_MSK 0x0000fe00
13340 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID register field value. */
13341 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_CLR_MSK 0xffff01ff
13342 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID register field is UNKNOWN. */
13343 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_RESET 0x0
13344 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID field value from a register. */
13345 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_GET(value) (((value) & 0x0000fe00) >> 9)
13346 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID register field value suitable for setting the register. */
13347 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_SET(value) (((value) << 9) & 0x0000fe00)
13348 
13349 /*
13350  * Field : cfg_t_param_mrs_to_valid
13351  *
13352  * iohmc_ctrl_mmr_top_inst.cfg_t_param_mrs_to_valid[3:0]
13353  *
13354  * Name:Mode Register Set to Valid
13355  *
13356  * Description:Mode Register Setting to valid.
13357  *
13358  * Field Access Macros:
13359  *
13360  */
13361 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID register field. */
13362 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_LSB 16
13363 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID register field. */
13364 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_MSB 19
13365 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID register field. */
13366 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_WIDTH 4
13367 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID register field value. */
13368 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_SET_MSK 0x000f0000
13369 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID register field value. */
13370 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_CLR_MSK 0xfff0ffff
13371 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID register field is UNKNOWN. */
13372 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_RESET 0x0
13373 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID field value from a register. */
13374 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_GET(value) (((value) & 0x000f0000) >> 16)
13375 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID register field value suitable for setting the register. */
13376 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_SET(value) (((value) << 16) & 0x000f0000)
13377 
13378 /*
13379  * Field : cfg_t_param_mps_to_valid
13380  *
13381  * iohmc_ctrl_mmr_top_inst.cfg_t_param_mps_to_valid[9:0]
13382  *
13383  * Name:Max Power Saving to Valid
13384  *
13385  * Description:Timing parameter for Maximum Power Saving to any valid command.
13386  * tXMP.
13387  *
13388  * Field Access Macros:
13389  *
13390  */
13391 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID register field. */
13392 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_LSB 20
13393 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID register field. */
13394 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_MSB 29
13395 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID register field. */
13396 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_WIDTH 10
13397 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID register field value. */
13398 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_SET_MSK 0x3ff00000
13399 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID register field value. */
13400 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_CLR_MSK 0xc00fffff
13401 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID register field is UNKNOWN. */
13402 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_RESET 0x0
13403 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID field value from a register. */
13404 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_GET(value) (((value) & 0x3ff00000) >> 20)
13405 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID register field value suitable for setting the register. */
13406 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_SET(value) (((value) << 20) & 0x3ff00000)
13407 
13408 #ifndef __ASSEMBLY__
13409 /*
13410  * WARNING: The C register and register group struct declarations are provided for
13411  * convenience and illustrative purposes. They should, however, be used with
13412  * caution as the C language standard provides no guarantees about the alignment or
13413  * atomicity of device memory accesses. The recommended practice for coding device
13414  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13415  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13416  * alt_write_dword() functions for 64 bit registers.
13417  *
13418  * The struct declaration for register ALT_MPFE_IOHMC_REG_CALTIMING7.
13419  */
13420 struct ALT_MPFE_IOHMC_REG_CALTIMING7_s
13421 {
13422  volatile uint32_t cfg_t_param_zqcl_to_valid : 9; /* ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID */
13423  volatile uint32_t cfg_t_param_zqcs_to_valid : 7; /* ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID */
13424  volatile uint32_t cfg_t_param_mrs_to_valid : 4; /* ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID */
13425  volatile uint32_t cfg_t_param_mps_to_valid : 10; /* ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID */
13426  uint32_t : 2; /* *UNDEFINED* */
13427 };
13428 
13429 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_CALTIMING7. */
13430 typedef struct ALT_MPFE_IOHMC_REG_CALTIMING7_s ALT_MPFE_IOHMC_REG_CALTIMING7_t;
13431 #endif /* __ASSEMBLY__ */
13432 
13433 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING7 register. */
13434 #define ALT_MPFE_IOHMC_REG_CALTIMING7_RESET 0x00000000
13435 /* The byte offset of the ALT_MPFE_IOHMC_REG_CALTIMING7 register from the beginning of the component. */
13436 #define ALT_MPFE_IOHMC_REG_CALTIMING7_OFST 0x98
13437 
13438 /*
13439  * Register : reg_caltiming8
13440  *
13441  * Register Layout
13442  *
13443  * Bits | Access | Reset | Description
13444  * :--------|:-------|:--------|:-------------------------------------------------------------------
13445  * [3:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID
13446  * [8:4] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID
13447  * [12:9] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE
13448  * [16:13] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS
13449  * [19:17] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY
13450  * [27:20] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID
13451  * [31:28] | ??? | Unknown | *UNDEFINED*
13452  *
13453  */
13454 /*
13455  * Field : cfg_t_param_mrr_to_valid
13456  *
13457  * iohmc_ctrl_mmr_top_inst.cfg_t_param_mrr_to_valid[3:0]
13458  *
13459  * Name:Mode Register Read to Valid
13460  *
13461  * Description:Timing parameter for Mode Register Read to any valid command.
13462  *
13463  * Field Access Macros:
13464  *
13465  */
13466 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID register field. */
13467 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_LSB 0
13468 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID register field. */
13469 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_MSB 3
13470 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID register field. */
13471 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_WIDTH 4
13472 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID register field value. */
13473 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_SET_MSK 0x0000000f
13474 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID register field value. */
13475 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_CLR_MSK 0xfffffff0
13476 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID register field is UNKNOWN. */
13477 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_RESET 0x0
13478 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID field value from a register. */
13479 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_GET(value) (((value) & 0x0000000f) >> 0)
13480 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID register field value suitable for setting the register. */
13481 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_SET(value) (((value) << 0) & 0x0000000f)
13482 
13483 /*
13484  * Field : cfg_t_param_mpr_to_valid
13485  *
13486  * iohmc_ctrl_mmr_top_inst.cfg_t_param_mpr_to_valid[4:0]
13487  *
13488  * Name:Multi Purpose Register Read to Valid
13489  *
13490  * Description:Timing parameter for Multi Purpose Register Read to any valid
13491  * command.
13492  *
13493  * Field Access Macros:
13494  *
13495  */
13496 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID register field. */
13497 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_LSB 4
13498 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID register field. */
13499 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_MSB 8
13500 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID register field. */
13501 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_WIDTH 5
13502 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID register field value. */
13503 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_SET_MSK 0x000001f0
13504 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID register field value. */
13505 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_CLR_MSK 0xfffffe0f
13506 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID register field is UNKNOWN. */
13507 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_RESET 0x0
13508 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID field value from a register. */
13509 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_GET(value) (((value) & 0x000001f0) >> 4)
13510 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID register field value suitable for setting the register. */
13511 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_SET(value) (((value) << 4) & 0x000001f0)
13512 
13513 /*
13514  * Field : cfg_t_param_mps_exit_cs_to_cke
13515  *
13516  * iohmc_ctrl_mmr_top_inst.cfg_t_param_mps_exit_cs_to_cke[3:0]
13517  *
13518  * Name:Max Power Saving CS to CKE
13519  *
13520  * Description:Timing parameter for exit Maximum Power Saving. Timing requirement
13521  * for CS assertion vs CKE de-assertion. tMPX_S.
13522  *
13523  * Field Access Macros:
13524  *
13525  */
13526 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE register field. */
13527 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_LSB 9
13528 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE register field. */
13529 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_MSB 12
13530 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE register field. */
13531 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_WIDTH 4
13532 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE register field value. */
13533 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_SET_MSK 0x00001e00
13534 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE register field value. */
13535 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_CLR_MSK 0xffffe1ff
13536 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE register field is UNKNOWN. */
13537 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_RESET 0x0
13538 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE field value from a register. */
13539 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_GET(value) (((value) & 0x00001e00) >> 9)
13540 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE register field value suitable for setting the register. */
13541 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_SET(value) (((value) << 9) & 0x00001e00)
13542 
13543 /*
13544  * Field : cfg_t_param_mps_exit_cke_to_cs
13545  *
13546  * iohmc_ctrl_mmr_top_inst.cfg_t_param_mps_exit_cke_to_cs[3:0]
13547  *
13548  * Name:Max Power Saving CKE to CS
13549  *
13550  * Description:Timing parameter for exit Maximum Power Saving. Timing requirement
13551  * for CKE de-assertion vs CS de-assertion. tMPX_LH.
13552  *
13553  * Field Access Macros:
13554  *
13555  */
13556 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS register field. */
13557 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_LSB 13
13558 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS register field. */
13559 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_MSB 16
13560 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS register field. */
13561 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_WIDTH 4
13562 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS register field value. */
13563 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_SET_MSK 0x0001e000
13564 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS register field value. */
13565 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_CLR_MSK 0xfffe1fff
13566 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS register field is UNKNOWN. */
13567 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_RESET 0x0
13568 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS field value from a register. */
13569 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_GET(value) (((value) & 0x0001e000) >> 13)
13570 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS register field value suitable for setting the register. */
13571 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_SET(value) (((value) << 13) & 0x0001e000)
13572 
13573 /*
13574  * Field : cfg_t_param_rld3_multibank_ref_delay
13575  *
13576  * iohmc_ctrl_mmr_top_inst.cfg_t_param_rld3_multibank_ref_delay[2:0]
13577  *
13578  * Name:Reserved
13579  *
13580  * Description:TBD
13581  *
13582  * Field Access Macros:
13583  *
13584  */
13585 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY register field. */
13586 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_LSB 17
13587 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY register field. */
13588 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_MSB 19
13589 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY register field. */
13590 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_WIDTH 3
13591 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY register field value. */
13592 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_SET_MSK 0x000e0000
13593 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY register field value. */
13594 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_CLR_MSK 0xfff1ffff
13595 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY register field is UNKNOWN. */
13596 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_RESET 0x0
13597 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY field value from a register. */
13598 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_GET(value) (((value) & 0x000e0000) >> 17)
13599 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY register field value suitable for setting the register. */
13600 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_SET(value) (((value) << 17) & 0x000e0000)
13601 
13602 /*
13603  * Field : cfg_t_param_mmr_cmd_to_valid
13604  *
13605  * iohmc_ctrl_mmr_top_inst.cfg_t_param_mmr_cmd_to_valid[7:0]
13606  *
13607  * Name:MMR Cmd to Valid Timing
13608  *
13609  * Description:MMR cmd to valid delay.
13610  *
13611  * Field Access Macros:
13612  *
13613  */
13614 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID register field. */
13615 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_LSB 20
13616 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID register field. */
13617 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_MSB 27
13618 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID register field. */
13619 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_WIDTH 8
13620 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID register field value. */
13621 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_SET_MSK 0x0ff00000
13622 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID register field value. */
13623 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_CLR_MSK 0xf00fffff
13624 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID register field is UNKNOWN. */
13625 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_RESET 0x0
13626 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID field value from a register. */
13627 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_GET(value) (((value) & 0x0ff00000) >> 20)
13628 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID register field value suitable for setting the register. */
13629 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_SET(value) (((value) << 20) & 0x0ff00000)
13630 
13631 #ifndef __ASSEMBLY__
13632 /*
13633  * WARNING: The C register and register group struct declarations are provided for
13634  * convenience and illustrative purposes. They should, however, be used with
13635  * caution as the C language standard provides no guarantees about the alignment or
13636  * atomicity of device memory accesses. The recommended practice for coding device
13637  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13638  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13639  * alt_write_dword() functions for 64 bit registers.
13640  *
13641  * The struct declaration for register ALT_MPFE_IOHMC_REG_CALTIMING8.
13642  */
13643 struct ALT_MPFE_IOHMC_REG_CALTIMING8_s
13644 {
13645  volatile uint32_t cfg_t_param_mrr_to_valid : 4; /* ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID */
13646  volatile uint32_t cfg_t_param_mpr_to_valid : 5; /* ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID */
13647  volatile uint32_t cfg_t_param_mps_exit_cs_to_cke : 4; /* ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE */
13648  volatile uint32_t cfg_t_param_mps_exit_cke_to_cs : 4; /* ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS */
13649  volatile uint32_t cfg_t_param_rld3_multibank_ref_delay : 3; /* ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY */
13650  volatile uint32_t cfg_t_param_mmr_cmd_to_valid : 8; /* ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID */
13651  uint32_t : 4; /* *UNDEFINED* */
13652 };
13653 
13654 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_CALTIMING8. */
13655 typedef struct ALT_MPFE_IOHMC_REG_CALTIMING8_s ALT_MPFE_IOHMC_REG_CALTIMING8_t;
13656 #endif /* __ASSEMBLY__ */
13657 
13658 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING8 register. */
13659 #define ALT_MPFE_IOHMC_REG_CALTIMING8_RESET 0x00000000
13660 /* The byte offset of the ALT_MPFE_IOHMC_REG_CALTIMING8 register from the beginning of the component. */
13661 #define ALT_MPFE_IOHMC_REG_CALTIMING8_OFST 0x9c
13662 
13663 /*
13664  * Register : reg_caltiming9
13665  *
13666  * Register Layout
13667  *
13668  * Bits | Access | Reset | Description
13669  * :-------|:-------|:--------|:-------------------------------------------------------
13670  * [7:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT
13671  * [31:8] | ??? | Unknown | *UNDEFINED*
13672  *
13673  */
13674 /*
13675  * Field : cfg_t_param_4_act_to_act
13676  *
13677  * iohmc_ctrl_mmr_top_inst.cfg_t_param_4_act_to_act[7:0]
13678  *
13679  * Name:Four Activate Window Time
13680  *
13681  * Description:The four-activate window timing parameter.
13682  *
13683  * Field Access Macros:
13684  *
13685  */
13686 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT register field. */
13687 #define ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_LSB 0
13688 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT register field. */
13689 #define ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_MSB 7
13690 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT register field. */
13691 #define ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_WIDTH 8
13692 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT register field value. */
13693 #define ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_SET_MSK 0x000000ff
13694 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT register field value. */
13695 #define ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_CLR_MSK 0xffffff00
13696 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT register field is UNKNOWN. */
13697 #define ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_RESET 0x0
13698 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT field value from a register. */
13699 #define ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_GET(value) (((value) & 0x000000ff) >> 0)
13700 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT register field value suitable for setting the register. */
13701 #define ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_SET(value) (((value) << 0) & 0x000000ff)
13702 
13703 #ifndef __ASSEMBLY__
13704 /*
13705  * WARNING: The C register and register group struct declarations are provided for
13706  * convenience and illustrative purposes. They should, however, be used with
13707  * caution as the C language standard provides no guarantees about the alignment or
13708  * atomicity of device memory accesses. The recommended practice for coding device
13709  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13710  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13711  * alt_write_dword() functions for 64 bit registers.
13712  *
13713  * The struct declaration for register ALT_MPFE_IOHMC_REG_CALTIMING9.
13714  */
13715 struct ALT_MPFE_IOHMC_REG_CALTIMING9_s
13716 {
13717  volatile uint32_t cfg_t_param_4_act_to_act : 8; /* ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT */
13718  uint32_t : 24; /* *UNDEFINED* */
13719 };
13720 
13721 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_CALTIMING9. */
13722 typedef struct ALT_MPFE_IOHMC_REG_CALTIMING9_s ALT_MPFE_IOHMC_REG_CALTIMING9_t;
13723 #endif /* __ASSEMBLY__ */
13724 
13725 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING9 register. */
13726 #define ALT_MPFE_IOHMC_REG_CALTIMING9_RESET 0x00000000
13727 /* The byte offset of the ALT_MPFE_IOHMC_REG_CALTIMING9 register from the beginning of the component. */
13728 #define ALT_MPFE_IOHMC_REG_CALTIMING9_OFST 0xa0
13729 
13730 /*
13731  * Register : reg_caltiming10
13732  *
13733  * Register Layout
13734  *
13735  * Bits | Access | Reset | Description
13736  * :-------|:-------|:--------|:---------------------------------------------------------
13737  * [7:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT
13738  * [31:8] | ??? | Unknown | *UNDEFINED*
13739  *
13740  */
13741 /*
13742  * Field : cfg_t_param_16_act_to_act
13743  *
13744  * iohmc_ctrl_mmr_top_inst.cfg_t_param_16_act_to_act[7:0]
13745  *
13746  * Name:Reserved
13747  *
13748  * Description:TBD
13749  *
13750  * Field Access Macros:
13751  *
13752  */
13753 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT register field. */
13754 #define ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_LSB 0
13755 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT register field. */
13756 #define ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_MSB 7
13757 /* The width in bits of the ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT register field. */
13758 #define ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_WIDTH 8
13759 /* The mask used to set the ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT register field value. */
13760 #define ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_SET_MSK 0x000000ff
13761 /* The mask used to clear the ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT register field value. */
13762 #define ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_CLR_MSK 0xffffff00
13763 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT register field is UNKNOWN. */
13764 #define ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_RESET 0x0
13765 /* Extracts the ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT field value from a register. */
13766 #define ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_GET(value) (((value) & 0x000000ff) >> 0)
13767 /* Produces a ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT register field value suitable for setting the register. */
13768 #define ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_SET(value) (((value) << 0) & 0x000000ff)
13769 
13770 #ifndef __ASSEMBLY__
13771 /*
13772  * WARNING: The C register and register group struct declarations are provided for
13773  * convenience and illustrative purposes. They should, however, be used with
13774  * caution as the C language standard provides no guarantees about the alignment or
13775  * atomicity of device memory accesses. The recommended practice for coding device
13776  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13777  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13778  * alt_write_dword() functions for 64 bit registers.
13779  *
13780  * The struct declaration for register ALT_MPFE_IOHMC_REG_CALTIMING10.
13781  */
13782 struct ALT_MPFE_IOHMC_REG_CALTIMING10_s
13783 {
13784  volatile uint32_t cfg_t_param_16_act_to_act : 8; /* ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT */
13785  uint32_t : 24; /* *UNDEFINED* */
13786 };
13787 
13788 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_CALTIMING10. */
13789 typedef struct ALT_MPFE_IOHMC_REG_CALTIMING10_s ALT_MPFE_IOHMC_REG_CALTIMING10_t;
13790 #endif /* __ASSEMBLY__ */
13791 
13792 /* The reset value of the ALT_MPFE_IOHMC_REG_CALTIMING10 register. */
13793 #define ALT_MPFE_IOHMC_REG_CALTIMING10_RESET 0x00000000
13794 /* The byte offset of the ALT_MPFE_IOHMC_REG_CALTIMING10 register from the beginning of the component. */
13795 #define ALT_MPFE_IOHMC_REG_CALTIMING10_OFST 0xa4
13796 
13797 /*
13798  * Register : reg_dramaddrw
13799  *
13800  * Register Layout
13801  *
13802  * Bits | Access | Reset | Description
13803  * :--------|:-------|:--------|:-------------------------------------------------------
13804  * [4:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH
13805  * [9:5] | RW | Unknown | ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH
13806  * [13:10] | RW | Unknown | ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH
13807  * [15:14] | RW | Unknown | ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH
13808  * [18:16] | RW | Unknown | ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH
13809  * [31:19] | ??? | Unknown | *UNDEFINED*
13810  *
13811  */
13812 /*
13813  * Field : cfg_col_addr_width
13814  *
13815  * iohmc_ctrl_mmr_top_inst.cfg_col_addr_width[4:0]
13816  *
13817  * Name:DRAM Column Address Bits
13818  *
13819  * Description:The number of column address bits for the memory devices in your
13820  * memory interface.
13821  *
13822  * Field Access Macros:
13823  *
13824  */
13825 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH register field. */
13826 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH_LSB 0
13827 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH register field. */
13828 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH_MSB 4
13829 /* The width in bits of the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH register field. */
13830 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH_WIDTH 5
13831 /* The mask used to set the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH register field value. */
13832 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH_SET_MSK 0x0000001f
13833 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH register field value. */
13834 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH_CLR_MSK 0xffffffe0
13835 /* The reset value of the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH register field is UNKNOWN. */
13836 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH_RESET 0x0
13837 /* Extracts the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH field value from a register. */
13838 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH_GET(value) (((value) & 0x0000001f) >> 0)
13839 /* Produces a ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH register field value suitable for setting the register. */
13840 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH_SET(value) (((value) << 0) & 0x0000001f)
13841 
13842 /*
13843  * Field : cfg_row_addr_width
13844  *
13845  * iohmc_ctrl_mmr_top_inst.cfg_row_addr_width[4:0]
13846  *
13847  * Name:DRAM Row Address Bits
13848  *
13849  * Description:The number of row address bits for the memory devices in your memory
13850  * interface.
13851  *
13852  * Field Access Macros:
13853  *
13854  */
13855 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH register field. */
13856 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH_LSB 5
13857 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH register field. */
13858 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MSB 9
13859 /* The width in bits of the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH register field. */
13860 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH_WIDTH 5
13861 /* The mask used to set the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH register field value. */
13862 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SET_MSK 0x000003e0
13863 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH register field value. */
13864 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH_CLR_MSK 0xfffffc1f
13865 /* The reset value of the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH register field is UNKNOWN. */
13866 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH_RESET 0x0
13867 /* Extracts the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH field value from a register. */
13868 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH_GET(value) (((value) & 0x000003e0) >> 5)
13869 /* Produces a ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH register field value suitable for setting the register. */
13870 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SET(value) (((value) << 5) & 0x000003e0)
13871 
13872 /*
13873  * Field : cfg_bank_addr_width
13874  *
13875  * iohmc_ctrl_mmr_top_inst.cfg_bank_addr_width[3:0]
13876  *
13877  * Name:DRAM Bank Address Bits
13878  *
13879  * Description:The number of bank address bits for the memory devices in your
13880  * memory interface.
13881  *
13882  * Field Access Macros:
13883  *
13884  */
13885 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH register field. */
13886 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH_LSB 10
13887 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH register field. */
13888 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MSB 13
13889 /* The width in bits of the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH register field. */
13890 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH_WIDTH 4
13891 /* The mask used to set the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH register field value. */
13892 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SET_MSK 0x00003c00
13893 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH register field value. */
13894 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH_CLR_MSK 0xffffc3ff
13895 /* The reset value of the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH register field is UNKNOWN. */
13896 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH_RESET 0x0
13897 /* Extracts the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH field value from a register. */
13898 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH_GET(value) (((value) & 0x00003c00) >> 10)
13899 /* Produces a ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH register field value suitable for setting the register. */
13900 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SET(value) (((value) << 10) & 0x00003c00)
13901 
13902 /*
13903  * Field : cfg_bank_group_addr_width
13904  *
13905  * iohmc_ctrl_mmr_top_inst.cfg_bank_group_addr_width[1:0]
13906  *
13907  * Name:DRAM Bank Group Address Bits
13908  *
13909  * Description:The number of bank group address bits for the memory devices in your
13910  * memory interface.
13911  *
13912  * Field Access Macros:
13913  *
13914  */
13915 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH register field. */
13916 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_LSB 14
13917 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH register field. */
13918 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MSB 15
13919 /* The width in bits of the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH register field. */
13920 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_WIDTH 2
13921 /* The mask used to set the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH register field value. */
13922 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SET_MSK 0x0000c000
13923 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH register field value. */
13924 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_CLR_MSK 0xffff3fff
13925 /* The reset value of the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH register field is UNKNOWN. */
13926 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_RESET 0x0
13927 /* Extracts the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH field value from a register. */
13928 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_GET(value) (((value) & 0x0000c000) >> 14)
13929 /* Produces a ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH register field value suitable for setting the register. */
13930 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SET(value) (((value) << 14) & 0x0000c000)
13931 
13932 /*
13933  * Field : cfg_cs_addr_width
13934  *
13935  * iohmc_ctrl_mmr_top_inst.cfg_cs_addr_width[2:0]
13936  *
13937  * Name:DRAM Chip Address Bits
13938  *
13939  * Description:The number of chip select address bits for the memory devices in
13940  * your memory interface.
13941  *
13942  * Field Access Macros:
13943  *
13944  */
13945 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH register field. */
13946 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH_LSB 16
13947 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH register field. */
13948 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH_MSB 18
13949 /* The width in bits of the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH register field. */
13950 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH_WIDTH 3
13951 /* The mask used to set the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH register field value. */
13952 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH_SET_MSK 0x00070000
13953 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH register field value. */
13954 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH_CLR_MSK 0xfff8ffff
13955 /* The reset value of the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH register field is UNKNOWN. */
13956 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH_RESET 0x0
13957 /* Extracts the ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH field value from a register. */
13958 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH_GET(value) (((value) & 0x00070000) >> 16)
13959 /* Produces a ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH register field value suitable for setting the register. */
13960 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH_SET(value) (((value) << 16) & 0x00070000)
13961 
13962 #ifndef __ASSEMBLY__
13963 /*
13964  * WARNING: The C register and register group struct declarations are provided for
13965  * convenience and illustrative purposes. They should, however, be used with
13966  * caution as the C language standard provides no guarantees about the alignment or
13967  * atomicity of device memory accesses. The recommended practice for coding device
13968  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13969  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13970  * alt_write_dword() functions for 64 bit registers.
13971  *
13972  * The struct declaration for register ALT_MPFE_IOHMC_REG_DRAMADDRW.
13973  */
13974 struct ALT_MPFE_IOHMC_REG_DRAMADDRW_s
13975 {
13976  volatile uint32_t cfg_col_addr_width : 5; /* ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH */
13977  volatile uint32_t cfg_row_addr_width : 5; /* ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH */
13978  volatile uint32_t cfg_bank_addr_width : 4; /* ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH */
13979  volatile uint32_t cfg_bank_group_addr_width : 2; /* ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH */
13980  volatile uint32_t cfg_cs_addr_width : 3; /* ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH */
13981  uint32_t : 13; /* *UNDEFINED* */
13982 };
13983 
13984 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_DRAMADDRW. */
13985 typedef struct ALT_MPFE_IOHMC_REG_DRAMADDRW_s ALT_MPFE_IOHMC_REG_DRAMADDRW_t;
13986 #endif /* __ASSEMBLY__ */
13987 
13988 /* The reset value of the ALT_MPFE_IOHMC_REG_DRAMADDRW register. */
13989 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_RESET 0x00000000
13990 /* The byte offset of the ALT_MPFE_IOHMC_REG_DRAMADDRW register from the beginning of the component. */
13991 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_OFST 0xa8
13992 
13993 /*
13994  * Register : reg_sideband0
13995  *
13996  * Register Layout
13997  *
13998  * Bits | Access | Reset | Description
13999  * :-------|:-------|:--------|:--------------------------------------------
14000  * [0] | RW | Unknown | ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER
14001  * [31:1] | ??? | Unknown | *UNDEFINED*
14002  *
14003  */
14004 /*
14005  * Field : mr_cmd_trigger
14006  *
14007  * iohmc_ctrl_mmr_top_inst.mr_cmd_trigger
14008  *
14009  * Name:Mode Register Command Execution Trigger
14010  *
14011  * Description:Write to 1 to trigger the execution of the mode register command.
14012  * It’s write clear.
14013  *
14014  * Field Access Macros:
14015  *
14016  */
14017 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER register field. */
14018 #define ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER_LSB 0
14019 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER register field. */
14020 #define ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER_MSB 0
14021 /* The width in bits of the ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER register field. */
14022 #define ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER_WIDTH 1
14023 /* The mask used to set the ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER register field value. */
14024 #define ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER_SET_MSK 0x00000001
14025 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER register field value. */
14026 #define ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER_CLR_MSK 0xfffffffe
14027 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER register field is UNKNOWN. */
14028 #define ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER_RESET 0x0
14029 /* Extracts the ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER field value from a register. */
14030 #define ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER_GET(value) (((value) & 0x00000001) >> 0)
14031 /* Produces a ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER register field value suitable for setting the register. */
14032 #define ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER_SET(value) (((value) << 0) & 0x00000001)
14033 
14034 #ifndef __ASSEMBLY__
14035 /*
14036  * WARNING: The C register and register group struct declarations are provided for
14037  * convenience and illustrative purposes. They should, however, be used with
14038  * caution as the C language standard provides no guarantees about the alignment or
14039  * atomicity of device memory accesses. The recommended practice for coding device
14040  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14041  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14042  * alt_write_dword() functions for 64 bit registers.
14043  *
14044  * The struct declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND0.
14045  */
14046 struct ALT_MPFE_IOHMC_REG_SIDEBAND0_s
14047 {
14048  volatile uint32_t mr_cmd_trigger : 1; /* ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER */
14049  uint32_t : 31; /* *UNDEFINED* */
14050 };
14051 
14052 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND0. */
14053 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND0_s ALT_MPFE_IOHMC_REG_SIDEBAND0_t;
14054 #endif /* __ASSEMBLY__ */
14055 
14056 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND0 register. */
14057 #define ALT_MPFE_IOHMC_REG_SIDEBAND0_RESET 0x00000000
14058 /* The byte offset of the ALT_MPFE_IOHMC_REG_SIDEBAND0 register from the beginning of the component. */
14059 #define ALT_MPFE_IOHMC_REG_SIDEBAND0_OFST 0xac
14060 
14061 /*
14062  * Register : reg_sideband1
14063  *
14064  * Register Layout
14065  *
14066  * Bits | Access | Reset | Description
14067  * :-------|:-------|:--------|:---------------------------------------------
14068  * [3:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ
14069  * [31:4] | ??? | Unknown | *UNDEFINED*
14070  *
14071  */
14072 /*
14073  * Field : mmr_refresh_req
14074  *
14075  * iohmc_ctrl_mmr_top_inst.mmr_refresh_req[3:0]
14076  *
14077  * Name:User Refresh Request
14078  *
14079  * Description:When asserted, indicates Refresh request to the specific rank. Each
14080  * bit corresponds to each rank. Controller clear this bit to ‘0’ once Refresh
14081  * is executed.
14082  *
14083  * Note: User may program any combination of values.
14084  *
14085  * Field Access Macros:
14086  *
14087  */
14088 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ register field. */
14089 #define ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ_LSB 0
14090 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ register field. */
14091 #define ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ_MSB 3
14092 /* The width in bits of the ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ register field. */
14093 #define ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ_WIDTH 4
14094 /* The mask used to set the ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ register field value. */
14095 #define ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ_SET_MSK 0x0000000f
14096 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ register field value. */
14097 #define ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ_CLR_MSK 0xfffffff0
14098 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ register field is UNKNOWN. */
14099 #define ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ_RESET 0x0
14100 /* Extracts the ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ field value from a register. */
14101 #define ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ_GET(value) (((value) & 0x0000000f) >> 0)
14102 /* Produces a ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ register field value suitable for setting the register. */
14103 #define ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ_SET(value) (((value) << 0) & 0x0000000f)
14104 
14105 #ifndef __ASSEMBLY__
14106 /*
14107  * WARNING: The C register and register group struct declarations are provided for
14108  * convenience and illustrative purposes. They should, however, be used with
14109  * caution as the C language standard provides no guarantees about the alignment or
14110  * atomicity of device memory accesses. The recommended practice for coding device
14111  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14112  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14113  * alt_write_dword() functions for 64 bit registers.
14114  *
14115  * The struct declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND1.
14116  */
14117 struct ALT_MPFE_IOHMC_REG_SIDEBAND1_s
14118 {
14119  volatile uint32_t mmr_refresh_req : 4; /* ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ */
14120  uint32_t : 28; /* *UNDEFINED* */
14121 };
14122 
14123 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND1. */
14124 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND1_s ALT_MPFE_IOHMC_REG_SIDEBAND1_t;
14125 #endif /* __ASSEMBLY__ */
14126 
14127 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND1 register. */
14128 #define ALT_MPFE_IOHMC_REG_SIDEBAND1_RESET 0x00000000
14129 /* The byte offset of the ALT_MPFE_IOHMC_REG_SIDEBAND1 register from the beginning of the component. */
14130 #define ALT_MPFE_IOHMC_REG_SIDEBAND1_OFST 0xb0
14131 
14132 /*
14133  * Register : reg_sideband2
14134  *
14135  * Register Layout
14136  *
14137  * Bits | Access | Reset | Description
14138  * :-------|:-------|:--------|:------------------------------------------------
14139  * [0] | RW | Unknown | ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ
14140  * [31:1] | ??? | Unknown | *UNDEFINED*
14141  *
14142  */
14143 /*
14144  * Field : mmr_zqcal_long_req
14145  *
14146  * iohmc_ctrl_mmr_top_inst.mmr_zqcal_long_req
14147  *
14148  * Name:User Long ZQ Cal Request
14149  *
14150  * Description:When asserted, indicates long ZQ cal request. This bit is write
14151  * clear.
14152  *
14153  * Field Access Macros:
14154  *
14155  */
14156 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ register field. */
14157 #define ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ_LSB 0
14158 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ register field. */
14159 #define ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ_MSB 0
14160 /* The width in bits of the ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ register field. */
14161 #define ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ_WIDTH 1
14162 /* The mask used to set the ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ register field value. */
14163 #define ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ_SET_MSK 0x00000001
14164 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ register field value. */
14165 #define ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ_CLR_MSK 0xfffffffe
14166 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ register field is UNKNOWN. */
14167 #define ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ_RESET 0x0
14168 /* Extracts the ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ field value from a register. */
14169 #define ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ_GET(value) (((value) & 0x00000001) >> 0)
14170 /* Produces a ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ register field value suitable for setting the register. */
14171 #define ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ_SET(value) (((value) << 0) & 0x00000001)
14172 
14173 #ifndef __ASSEMBLY__
14174 /*
14175  * WARNING: The C register and register group struct declarations are provided for
14176  * convenience and illustrative purposes. They should, however, be used with
14177  * caution as the C language standard provides no guarantees about the alignment or
14178  * atomicity of device memory accesses. The recommended practice for coding device
14179  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14180  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14181  * alt_write_dword() functions for 64 bit registers.
14182  *
14183  * The struct declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND2.
14184  */
14185 struct ALT_MPFE_IOHMC_REG_SIDEBAND2_s
14186 {
14187  volatile uint32_t mmr_zqcal_long_req : 1; /* ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ */
14188  uint32_t : 31; /* *UNDEFINED* */
14189 };
14190 
14191 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND2. */
14192 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND2_s ALT_MPFE_IOHMC_REG_SIDEBAND2_t;
14193 #endif /* __ASSEMBLY__ */
14194 
14195 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND2 register. */
14196 #define ALT_MPFE_IOHMC_REG_SIDEBAND2_RESET 0x00000000
14197 /* The byte offset of the ALT_MPFE_IOHMC_REG_SIDEBAND2 register from the beginning of the component. */
14198 #define ALT_MPFE_IOHMC_REG_SIDEBAND2_OFST 0xb4
14199 
14200 /*
14201  * Register : reg_sideband3
14202  *
14203  * Register Layout
14204  *
14205  * Bits | Access | Reset | Description
14206  * :-------|:-------|:--------|:-------------------------------------------------
14207  * [0] | RW | Unknown | ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ
14208  * [31:1] | ??? | Unknown | *UNDEFINED*
14209  *
14210  */
14211 /*
14212  * Field : mmr_zqcal_short_req
14213  *
14214  * iohmc_ctrl_mmr_top_inst.mmr_zqcal_short_req
14215  *
14216  * Name:User Short ZQ Cal Request
14217  *
14218  * Description:When asserted, indicates short ZQ cal request. This bit is write
14219  * clear.
14220  *
14221  * Field Access Macros:
14222  *
14223  */
14224 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ register field. */
14225 #define ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_LSB 0
14226 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ register field. */
14227 #define ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_MSB 0
14228 /* The width in bits of the ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ register field. */
14229 #define ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_WIDTH 1
14230 /* The mask used to set the ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ register field value. */
14231 #define ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_SET_MSK 0x00000001
14232 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ register field value. */
14233 #define ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_CLR_MSK 0xfffffffe
14234 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ register field is UNKNOWN. */
14235 #define ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_RESET 0x0
14236 /* Extracts the ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ field value from a register. */
14237 #define ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_GET(value) (((value) & 0x00000001) >> 0)
14238 /* Produces a ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ register field value suitable for setting the register. */
14239 #define ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_SET(value) (((value) << 0) & 0x00000001)
14240 
14241 #ifndef __ASSEMBLY__
14242 /*
14243  * WARNING: The C register and register group struct declarations are provided for
14244  * convenience and illustrative purposes. They should, however, be used with
14245  * caution as the C language standard provides no guarantees about the alignment or
14246  * atomicity of device memory accesses. The recommended practice for coding device
14247  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14248  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14249  * alt_write_dword() functions for 64 bit registers.
14250  *
14251  * The struct declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND3.
14252  */
14253 struct ALT_MPFE_IOHMC_REG_SIDEBAND3_s
14254 {
14255  volatile uint32_t mmr_zqcal_short_req : 1; /* ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ */
14256  uint32_t : 31; /* *UNDEFINED* */
14257 };
14258 
14259 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND3. */
14260 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND3_s ALT_MPFE_IOHMC_REG_SIDEBAND3_t;
14261 #endif /* __ASSEMBLY__ */
14262 
14263 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND3 register. */
14264 #define ALT_MPFE_IOHMC_REG_SIDEBAND3_RESET 0x00000000
14265 /* The byte offset of the ALT_MPFE_IOHMC_REG_SIDEBAND3 register from the beginning of the component. */
14266 #define ALT_MPFE_IOHMC_REG_SIDEBAND3_OFST 0xb8
14267 
14268 /*
14269  * Register : reg_sideband4
14270  *
14271  * Register Layout
14272  *
14273  * Bits | Access | Reset | Description
14274  * :-------|:-------|:--------|:-----------------------------------------------
14275  * [3:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ
14276  * [31:4] | ??? | Unknown | *UNDEFINED*
14277  *
14278  */
14279 /*
14280  * Field : mmr_self_rfsh_req
14281  *
14282  * iohmc_ctrl_mmr_top_inst.mmr_self_rfsh_req[3:0]
14283  *
14284  * Name:User Self Refresh Request
14285  *
14286  * Description:When asserted, indicates self refresh request to the specific rank.
14287  * Each bit corresponds to each rank. These bits are write clear.
14288  *
14289  * Note: User may NOT program any combination of values. Legal Values are 0(hex)
14290  * and F(hex). All other values are ILLEGAL.
14291  *
14292  * Field Access Macros:
14293  *
14294  */
14295 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ register field. */
14296 #define ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ_LSB 0
14297 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ register field. */
14298 #define ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ_MSB 3
14299 /* The width in bits of the ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ register field. */
14300 #define ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ_WIDTH 4
14301 /* The mask used to set the ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ register field value. */
14302 #define ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ_SET_MSK 0x0000000f
14303 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ register field value. */
14304 #define ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ_CLR_MSK 0xfffffff0
14305 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ register field is UNKNOWN. */
14306 #define ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ_RESET 0x0
14307 /* Extracts the ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ field value from a register. */
14308 #define ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ_GET(value) (((value) & 0x0000000f) >> 0)
14309 /* Produces a ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ register field value suitable for setting the register. */
14310 #define ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ_SET(value) (((value) << 0) & 0x0000000f)
14311 
14312 #ifndef __ASSEMBLY__
14313 /*
14314  * WARNING: The C register and register group struct declarations are provided for
14315  * convenience and illustrative purposes. They should, however, be used with
14316  * caution as the C language standard provides no guarantees about the alignment or
14317  * atomicity of device memory accesses. The recommended practice for coding device
14318  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14319  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14320  * alt_write_dword() functions for 64 bit registers.
14321  *
14322  * The struct declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND4.
14323  */
14324 struct ALT_MPFE_IOHMC_REG_SIDEBAND4_s
14325 {
14326  volatile uint32_t mmr_self_rfsh_req : 4; /* ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ */
14327  uint32_t : 28; /* *UNDEFINED* */
14328 };
14329 
14330 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND4. */
14331 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND4_s ALT_MPFE_IOHMC_REG_SIDEBAND4_t;
14332 #endif /* __ASSEMBLY__ */
14333 
14334 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND4 register. */
14335 #define ALT_MPFE_IOHMC_REG_SIDEBAND4_RESET 0x00000000
14336 /* The byte offset of the ALT_MPFE_IOHMC_REG_SIDEBAND4 register from the beginning of the component. */
14337 #define ALT_MPFE_IOHMC_REG_SIDEBAND4_OFST 0xbc
14338 
14339 /*
14340  * Register : reg_sideband5
14341  *
14342  * Register Layout
14343  *
14344  * Bits | Access | Reset | Description
14345  * :-------|:-------|:--------|:---------------------------------------------
14346  * [0] | RW | Unknown | ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ
14347  * [31:1] | ??? | Unknown | *UNDEFINED*
14348  *
14349  */
14350 /*
14351  * Field : mmr_dpd_mps_req
14352  *
14353  * iohmc_ctrl_mmr_top_inst.mmr_dpd_mps_req
14354  *
14355  * Name:User Deep Power Down/Max Power Saving Request
14356  *
14357  * Description:When asserted, indicates deep power down or max power saving
14358  * request. This bit is write clear.
14359  *
14360  * Field Access Macros:
14361  *
14362  */
14363 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ register field. */
14364 #define ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ_LSB 0
14365 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ register field. */
14366 #define ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ_MSB 0
14367 /* The width in bits of the ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ register field. */
14368 #define ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ_WIDTH 1
14369 /* The mask used to set the ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ register field value. */
14370 #define ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ_SET_MSK 0x00000001
14371 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ register field value. */
14372 #define ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ_CLR_MSK 0xfffffffe
14373 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ register field is UNKNOWN. */
14374 #define ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ_RESET 0x0
14375 /* Extracts the ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ field value from a register. */
14376 #define ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ_GET(value) (((value) & 0x00000001) >> 0)
14377 /* Produces a ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ register field value suitable for setting the register. */
14378 #define ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ_SET(value) (((value) << 0) & 0x00000001)
14379 
14380 #ifndef __ASSEMBLY__
14381 /*
14382  * WARNING: The C register and register group struct declarations are provided for
14383  * convenience and illustrative purposes. They should, however, be used with
14384  * caution as the C language standard provides no guarantees about the alignment or
14385  * atomicity of device memory accesses. The recommended practice for coding device
14386  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14387  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14388  * alt_write_dword() functions for 64 bit registers.
14389  *
14390  * The struct declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND5.
14391  */
14392 struct ALT_MPFE_IOHMC_REG_SIDEBAND5_s
14393 {
14394  volatile uint32_t mmr_dpd_mps_req : 1; /* ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ */
14395  uint32_t : 31; /* *UNDEFINED* */
14396 };
14397 
14398 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND5. */
14399 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND5_s ALT_MPFE_IOHMC_REG_SIDEBAND5_t;
14400 #endif /* __ASSEMBLY__ */
14401 
14402 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND5 register. */
14403 #define ALT_MPFE_IOHMC_REG_SIDEBAND5_RESET 0x00000000
14404 /* The byte offset of the ALT_MPFE_IOHMC_REG_SIDEBAND5 register from the beginning of the component. */
14405 #define ALT_MPFE_IOHMC_REG_SIDEBAND5_OFST 0xc0
14406 
14407 /*
14408  * Register : reg_sideband6
14409  *
14410  * Register Layout
14411  *
14412  * Bits | Access | Reset | Description
14413  * :-------|:-------|:--------|:----------------------------------------
14414  * [0] | R | Unknown | ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK
14415  * [31:1] | ??? | Unknown | *UNDEFINED*
14416  *
14417  */
14418 /*
14419  * Field : mr_cmd_ack
14420  *
14421  * iohmc_ctrl_mmr_top_inst.mr_cmd_ack
14422  *
14423  * Name:Mode Register Command Ack
14424  *
14425  * Description:Acknowledge to mode register command.
14426  *
14427  * Field Access Macros:
14428  *
14429  */
14430 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK register field. */
14431 #define ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK_LSB 0
14432 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK register field. */
14433 #define ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK_MSB 0
14434 /* The width in bits of the ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK register field. */
14435 #define ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK_WIDTH 1
14436 /* The mask used to set the ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK register field value. */
14437 #define ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK_SET_MSK 0x00000001
14438 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK register field value. */
14439 #define ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK_CLR_MSK 0xfffffffe
14440 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK register field is UNKNOWN. */
14441 #define ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK_RESET 0x0
14442 /* Extracts the ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK field value from a register. */
14443 #define ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK_GET(value) (((value) & 0x00000001) >> 0)
14444 /* Produces a ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK register field value suitable for setting the register. */
14445 #define ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK_SET(value) (((value) << 0) & 0x00000001)
14446 
14447 #ifndef __ASSEMBLY__
14448 /*
14449  * WARNING: The C register and register group struct declarations are provided for
14450  * convenience and illustrative purposes. They should, however, be used with
14451  * caution as the C language standard provides no guarantees about the alignment or
14452  * atomicity of device memory accesses. The recommended practice for coding device
14453  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14454  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14455  * alt_write_dword() functions for 64 bit registers.
14456  *
14457  * The struct declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND6.
14458  */
14459 struct ALT_MPFE_IOHMC_REG_SIDEBAND6_s
14460 {
14461  const volatile uint32_t mr_cmd_ack : 1; /* ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK */
14462  uint32_t : 31; /* *UNDEFINED* */
14463 };
14464 
14465 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND6. */
14466 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND6_s ALT_MPFE_IOHMC_REG_SIDEBAND6_t;
14467 #endif /* __ASSEMBLY__ */
14468 
14469 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND6 register. */
14470 #define ALT_MPFE_IOHMC_REG_SIDEBAND6_RESET 0x00000000
14471 /* The byte offset of the ALT_MPFE_IOHMC_REG_SIDEBAND6 register from the beginning of the component. */
14472 #define ALT_MPFE_IOHMC_REG_SIDEBAND6_OFST 0xc4
14473 
14474 /*
14475  * Register : reg_sideband7
14476  *
14477  * Register Layout
14478  *
14479  * Bits | Access | Reset | Description
14480  * :-------|:-------|:--------|:---------------------------------------------
14481  * [0] | R | Unknown | ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK
14482  * [31:1] | ??? | Unknown | *UNDEFINED*
14483  *
14484  */
14485 /*
14486  * Field : mmr_refresh_ack
14487  *
14488  * iohmc_ctrl_mmr_top_inst.mmr_refresh_ack
14489  *
14490  * Name:Refresh Acknowlege (non-3DS)
14491  *
14492  * Description:Acknowledge to indicate refresh is in progress (non-3DS).
14493  *
14494  * Field Access Macros:
14495  *
14496  */
14497 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK register field. */
14498 #define ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK_LSB 0
14499 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK register field. */
14500 #define ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK_MSB 0
14501 /* The width in bits of the ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK register field. */
14502 #define ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK_WIDTH 1
14503 /* The mask used to set the ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK register field value. */
14504 #define ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK_SET_MSK 0x00000001
14505 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK register field value. */
14506 #define ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK_CLR_MSK 0xfffffffe
14507 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK register field is UNKNOWN. */
14508 #define ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK_RESET 0x0
14509 /* Extracts the ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK field value from a register. */
14510 #define ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK_GET(value) (((value) & 0x00000001) >> 0)
14511 /* Produces a ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK register field value suitable for setting the register. */
14512 #define ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK_SET(value) (((value) << 0) & 0x00000001)
14513 
14514 #ifndef __ASSEMBLY__
14515 /*
14516  * WARNING: The C register and register group struct declarations are provided for
14517  * convenience and illustrative purposes. They should, however, be used with
14518  * caution as the C language standard provides no guarantees about the alignment or
14519  * atomicity of device memory accesses. The recommended practice for coding device
14520  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14521  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14522  * alt_write_dword() functions for 64 bit registers.
14523  *
14524  * The struct declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND7.
14525  */
14526 struct ALT_MPFE_IOHMC_REG_SIDEBAND7_s
14527 {
14528  const volatile uint32_t mmr_refresh_ack : 1; /* ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK */
14529  uint32_t : 31; /* *UNDEFINED* */
14530 };
14531 
14532 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND7. */
14533 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND7_s ALT_MPFE_IOHMC_REG_SIDEBAND7_t;
14534 #endif /* __ASSEMBLY__ */
14535 
14536 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND7 register. */
14537 #define ALT_MPFE_IOHMC_REG_SIDEBAND7_RESET 0x00000000
14538 /* The byte offset of the ALT_MPFE_IOHMC_REG_SIDEBAND7 register from the beginning of the component. */
14539 #define ALT_MPFE_IOHMC_REG_SIDEBAND7_OFST 0xc8
14540 
14541 /*
14542  * Register : reg_sideband8
14543  *
14544  * Register Layout
14545  *
14546  * Bits | Access | Reset | Description
14547  * :-------|:-------|:--------|:-------------------------------------------
14548  * [0] | R | Unknown | ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK
14549  * [31:1] | ??? | Unknown | *UNDEFINED*
14550  *
14551  */
14552 /*
14553  * Field : mmr_zqcal_ack
14554  *
14555  * iohmc_ctrl_mmr_top_inst.mmr_zqcal_ack
14556  *
14557  * Name:ZQCAL Acknowlege
14558  *
14559  * Description:Acknowledge to indicate ZQCAL is progress.
14560  *
14561  * Field Access Macros:
14562  *
14563  */
14564 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK register field. */
14565 #define ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK_LSB 0
14566 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK register field. */
14567 #define ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK_MSB 0
14568 /* The width in bits of the ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK register field. */
14569 #define ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK_WIDTH 1
14570 /* The mask used to set the ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK register field value. */
14571 #define ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK_SET_MSK 0x00000001
14572 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK register field value. */
14573 #define ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK_CLR_MSK 0xfffffffe
14574 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK register field is UNKNOWN. */
14575 #define ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK_RESET 0x0
14576 /* Extracts the ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK field value from a register. */
14577 #define ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK_GET(value) (((value) & 0x00000001) >> 0)
14578 /* Produces a ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK register field value suitable for setting the register. */
14579 #define ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK_SET(value) (((value) << 0) & 0x00000001)
14580 
14581 #ifndef __ASSEMBLY__
14582 /*
14583  * WARNING: The C register and register group struct declarations are provided for
14584  * convenience and illustrative purposes. They should, however, be used with
14585  * caution as the C language standard provides no guarantees about the alignment or
14586  * atomicity of device memory accesses. The recommended practice for coding device
14587  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14588  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14589  * alt_write_dword() functions for 64 bit registers.
14590  *
14591  * The struct declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND8.
14592  */
14593 struct ALT_MPFE_IOHMC_REG_SIDEBAND8_s
14594 {
14595  const volatile uint32_t mmr_zqcal_ack : 1; /* ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK */
14596  uint32_t : 31; /* *UNDEFINED* */
14597 };
14598 
14599 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND8. */
14600 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND8_s ALT_MPFE_IOHMC_REG_SIDEBAND8_t;
14601 #endif /* __ASSEMBLY__ */
14602 
14603 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND8 register. */
14604 #define ALT_MPFE_IOHMC_REG_SIDEBAND8_RESET 0x00000000
14605 /* The byte offset of the ALT_MPFE_IOHMC_REG_SIDEBAND8 register from the beginning of the component. */
14606 #define ALT_MPFE_IOHMC_REG_SIDEBAND8_OFST 0xcc
14607 
14608 /*
14609  * Register : reg_sideband9
14610  *
14611  * Register Layout
14612  *
14613  * Bits | Access | Reset | Description
14614  * :-------|:-------|:--------|:-----------------------------------------------
14615  * [0] | R | Unknown | ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK
14616  * [31:1] | ??? | Unknown | *UNDEFINED*
14617  *
14618  */
14619 /*
14620  * Field : mmr_self_rfsh_ack
14621  *
14622  * iohmc_ctrl_mmr_top_inst.mmr_self_rfsh_ack
14623  *
14624  * Name:Self Refresh Acknowlege
14625  *
14626  * Description:Acknowledge to indicate self refresh is progress.
14627  *
14628  * Field Access Macros:
14629  *
14630  */
14631 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK register field. */
14632 #define ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK_LSB 0
14633 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK register field. */
14634 #define ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK_MSB 0
14635 /* The width in bits of the ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK register field. */
14636 #define ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK_WIDTH 1
14637 /* The mask used to set the ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK register field value. */
14638 #define ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK_SET_MSK 0x00000001
14639 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK register field value. */
14640 #define ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK_CLR_MSK 0xfffffffe
14641 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK register field is UNKNOWN. */
14642 #define ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK_RESET 0x0
14643 /* Extracts the ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK field value from a register. */
14644 #define ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK_GET(value) (((value) & 0x00000001) >> 0)
14645 /* Produces a ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK register field value suitable for setting the register. */
14646 #define ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK_SET(value) (((value) << 0) & 0x00000001)
14647 
14648 #ifndef __ASSEMBLY__
14649 /*
14650  * WARNING: The C register and register group struct declarations are provided for
14651  * convenience and illustrative purposes. They should, however, be used with
14652  * caution as the C language standard provides no guarantees about the alignment or
14653  * atomicity of device memory accesses. The recommended practice for coding device
14654  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14655  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14656  * alt_write_dword() functions for 64 bit registers.
14657  *
14658  * The struct declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND9.
14659  */
14660 struct ALT_MPFE_IOHMC_REG_SIDEBAND9_s
14661 {
14662  const volatile uint32_t mmr_self_rfsh_ack : 1; /* ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK */
14663  uint32_t : 31; /* *UNDEFINED* */
14664 };
14665 
14666 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND9. */
14667 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND9_s ALT_MPFE_IOHMC_REG_SIDEBAND9_t;
14668 #endif /* __ASSEMBLY__ */
14669 
14670 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND9 register. */
14671 #define ALT_MPFE_IOHMC_REG_SIDEBAND9_RESET 0x00000000
14672 /* The byte offset of the ALT_MPFE_IOHMC_REG_SIDEBAND9 register from the beginning of the component. */
14673 #define ALT_MPFE_IOHMC_REG_SIDEBAND9_OFST 0xd0
14674 
14675 /*
14676  * Register : reg_sideband10
14677  *
14678  * Register Layout
14679  *
14680  * Bits | Access | Reset | Description
14681  * :-------|:-------|:--------|:----------------------------------------------
14682  * [0] | R | Unknown | ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK
14683  * [31:1] | ??? | Unknown | *UNDEFINED*
14684  *
14685  */
14686 /*
14687  * Field : mmr_dpd_mps_ack
14688  *
14689  * iohmc_ctrl_mmr_top_inst.mmr_dpd_mps_ack
14690  *
14691  * Name:Deep Power Down/Max Power Saving Acknowlege
14692  *
14693  * Description:Acknowledge to indicate deep power down/max power saving is in
14694  * progress.
14695  *
14696  * Field Access Macros:
14697  *
14698  */
14699 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK register field. */
14700 #define ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK_LSB 0
14701 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK register field. */
14702 #define ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK_MSB 0
14703 /* The width in bits of the ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK register field. */
14704 #define ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK_WIDTH 1
14705 /* The mask used to set the ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK register field value. */
14706 #define ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK_SET_MSK 0x00000001
14707 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK register field value. */
14708 #define ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK_CLR_MSK 0xfffffffe
14709 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK register field is UNKNOWN. */
14710 #define ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK_RESET 0x0
14711 /* Extracts the ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK field value from a register. */
14712 #define ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK_GET(value) (((value) & 0x00000001) >> 0)
14713 /* Produces a ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK register field value suitable for setting the register. */
14714 #define ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK_SET(value) (((value) << 0) & 0x00000001)
14715 
14716 #ifndef __ASSEMBLY__
14717 /*
14718  * WARNING: The C register and register group struct declarations are provided for
14719  * convenience and illustrative purposes. They should, however, be used with
14720  * caution as the C language standard provides no guarantees about the alignment or
14721  * atomicity of device memory accesses. The recommended practice for coding device
14722  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14723  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14724  * alt_write_dword() functions for 64 bit registers.
14725  *
14726  * The struct declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND10.
14727  */
14728 struct ALT_MPFE_IOHMC_REG_SIDEBAND10_s
14729 {
14730  const volatile uint32_t mmr_dpd_mps_ack : 1; /* ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK */
14731  uint32_t : 31; /* *UNDEFINED* */
14732 };
14733 
14734 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND10. */
14735 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND10_s ALT_MPFE_IOHMC_REG_SIDEBAND10_t;
14736 #endif /* __ASSEMBLY__ */
14737 
14738 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND10 register. */
14739 #define ALT_MPFE_IOHMC_REG_SIDEBAND10_RESET 0x00000000
14740 /* The byte offset of the ALT_MPFE_IOHMC_REG_SIDEBAND10 register from the beginning of the component. */
14741 #define ALT_MPFE_IOHMC_REG_SIDEBAND10_OFST 0xd4
14742 
14743 /*
14744  * Register : reg_sideband11
14745  *
14746  * Register Layout
14747  *
14748  * Bits | Access | Reset | Description
14749  * :-------|:-------|:--------|:----------------------------------------------
14750  * [0] | R | Unknown | ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK
14751  * [31:1] | ??? | Unknown | *UNDEFINED*
14752  *
14753  */
14754 /*
14755  * Field : mmr_auto_pd_ack
14756  *
14757  * iohmc_ctrl_mmr_top_inst.mmr_auto_pd_ack
14758  *
14759  * Name:Auto Power Down Acknowlege
14760  *
14761  * Description:Acknowledge to indicate auto power down is in progress.
14762  *
14763  * Field Access Macros:
14764  *
14765  */
14766 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK register field. */
14767 #define ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK_LSB 0
14768 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK register field. */
14769 #define ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK_MSB 0
14770 /* The width in bits of the ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK register field. */
14771 #define ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK_WIDTH 1
14772 /* The mask used to set the ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK register field value. */
14773 #define ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK_SET_MSK 0x00000001
14774 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK register field value. */
14775 #define ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK_CLR_MSK 0xfffffffe
14776 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK register field is UNKNOWN. */
14777 #define ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK_RESET 0x0
14778 /* Extracts the ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK field value from a register. */
14779 #define ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK_GET(value) (((value) & 0x00000001) >> 0)
14780 /* Produces a ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK register field value suitable for setting the register. */
14781 #define ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK_SET(value) (((value) << 0) & 0x00000001)
14782 
14783 #ifndef __ASSEMBLY__
14784 /*
14785  * WARNING: The C register and register group struct declarations are provided for
14786  * convenience and illustrative purposes. They should, however, be used with
14787  * caution as the C language standard provides no guarantees about the alignment or
14788  * atomicity of device memory accesses. The recommended practice for coding device
14789  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14790  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14791  * alt_write_dword() functions for 64 bit registers.
14792  *
14793  * The struct declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND11.
14794  */
14795 struct ALT_MPFE_IOHMC_REG_SIDEBAND11_s
14796 {
14797  const volatile uint32_t mmr_auto_pd_ack : 1; /* ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK */
14798  uint32_t : 31; /* *UNDEFINED* */
14799 };
14800 
14801 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND11. */
14802 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND11_s ALT_MPFE_IOHMC_REG_SIDEBAND11_t;
14803 #endif /* __ASSEMBLY__ */
14804 
14805 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND11 register. */
14806 #define ALT_MPFE_IOHMC_REG_SIDEBAND11_RESET 0x00000000
14807 /* The byte offset of the ALT_MPFE_IOHMC_REG_SIDEBAND11 register from the beginning of the component. */
14808 #define ALT_MPFE_IOHMC_REG_SIDEBAND11_OFST 0xd8
14809 
14810 /*
14811  * Register : reg_sideband12
14812  *
14813  * Register Layout
14814  *
14815  * Bits | Access | Reset | Description
14816  * :-------|:-------|:--------|:------------------------------------------
14817  * [2:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE
14818  * [6:3] | RW | Unknown | ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK
14819  * [31:7] | ??? | Unknown | *UNDEFINED*
14820  *
14821  */
14822 /*
14823  * Field : mr_cmd_type
14824  *
14825  * iohmc_ctrl_mmr_top_inst.mr_cmd_type[2:0]
14826  *
14827  * Name:Mode Register Command Type
14828  *
14829  * Description:Indicates the type of Mode Register Command
14830  *
14831  * ‘000’ – Mode Register Set.
14832  *
14833  * ‘001’ – Mode Register Read.
14834  *
14835  * ‘010’ – Multi Purpose Register Read.
14836  *
14837  * Others – Reserved.
14838  *
14839  * Field Access Macros:
14840  *
14841  */
14842 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE register field. */
14843 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE_LSB 0
14844 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE register field. */
14845 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE_MSB 2
14846 /* The width in bits of the ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE register field. */
14847 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE_WIDTH 3
14848 /* The mask used to set the ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE register field value. */
14849 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE_SET_MSK 0x00000007
14850 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE register field value. */
14851 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE_CLR_MSK 0xfffffff8
14852 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE register field is UNKNOWN. */
14853 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE_RESET 0x0
14854 /* Extracts the ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE field value from a register. */
14855 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE_GET(value) (((value) & 0x00000007) >> 0)
14856 /* Produces a ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE register field value suitable for setting the register. */
14857 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE_SET(value) (((value) << 0) & 0x00000007)
14858 
14859 /*
14860  * Field : mr_cmd_rank
14861  *
14862  * iohmc_ctrl_mmr_top_inst.mr_cmd_rank[3:0]
14863  *
14864  * Name:Mode Register Command Rank
14865  *
14866  * Description:Indicates which rank the mode register command is intended to.
14867  *
14868  * Field Access Macros:
14869  *
14870  */
14871 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK register field. */
14872 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK_LSB 3
14873 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK register field. */
14874 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK_MSB 6
14875 /* The width in bits of the ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK register field. */
14876 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK_WIDTH 4
14877 /* The mask used to set the ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK register field value. */
14878 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK_SET_MSK 0x00000078
14879 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK register field value. */
14880 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK_CLR_MSK 0xffffff87
14881 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK register field is UNKNOWN. */
14882 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK_RESET 0x0
14883 /* Extracts the ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK field value from a register. */
14884 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK_GET(value) (((value) & 0x00000078) >> 3)
14885 /* Produces a ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK register field value suitable for setting the register. */
14886 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK_SET(value) (((value) << 3) & 0x00000078)
14887 
14888 #ifndef __ASSEMBLY__
14889 /*
14890  * WARNING: The C register and register group struct declarations are provided for
14891  * convenience and illustrative purposes. They should, however, be used with
14892  * caution as the C language standard provides no guarantees about the alignment or
14893  * atomicity of device memory accesses. The recommended practice for coding device
14894  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14895  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14896  * alt_write_dword() functions for 64 bit registers.
14897  *
14898  * The struct declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND12.
14899  */
14900 struct ALT_MPFE_IOHMC_REG_SIDEBAND12_s
14901 {
14902  volatile uint32_t mr_cmd_type : 3; /* ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE */
14903  volatile uint32_t mr_cmd_rank : 4; /* ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK */
14904  uint32_t : 25; /* *UNDEFINED* */
14905 };
14906 
14907 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND12. */
14908 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND12_s ALT_MPFE_IOHMC_REG_SIDEBAND12_t;
14909 #endif /* __ASSEMBLY__ */
14910 
14911 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND12 register. */
14912 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_RESET 0x00000000
14913 /* The byte offset of the ALT_MPFE_IOHMC_REG_SIDEBAND12 register from the beginning of the component. */
14914 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_OFST 0xdc
14915 
14916 /*
14917  * Register : reg_sideband13
14918  *
14919  * Register Layout
14920  *
14921  * Bits | Access | Reset | Description
14922  * :-------|:-------|:--------|:--------------------------------------------
14923  * [31:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE
14924  *
14925  */
14926 /*
14927  * Field : mr_cmd_opcode
14928  *
14929  * iohmc_ctrl_mmr_top_inst.mr_cmd_opcode[31:0]
14930  *
14931  * Name:Mode Register Command Opcode
14932  *
14933  * Description:[31:27] reserved.
14934  *
14935  * Register Command Opcode
14936  *
14937  * Information to be used for Register Command
14938  *
14939  * LPDDR3
14940  *
14941  * [26:20] Reserved
14942  *
14943  * [19:10] falling edge CA.
14944  *
14945  * [9:0] rising edge CA
14946  *
14947  * DDR4
14948  *
14949  * [26:24] C2:C0
14950  *
14951  * [23] ACT
14952  *
14953  * [22:21] BG1:BG0
14954  *
14955  * [20] Reserved
14956  *
14957  * [19:18] BA1:BA0
14958  *
14959  * [17] A17
14960  *
14961  * [16] RAS
14962  *
14963  * [15] CAS
14964  *
14965  * [14] WE
14966  *
14967  * [13:0] A13:A0
14968  *
14969  * DDR3
14970  *
14971  * [26:21] Reserved
14972  *
14973  * [20:18] BA2:BA0
14974  *
14975  * [17] A17
14976  *
14977  * [16] RAS
14978  *
14979  * [15] CAS
14980  *
14981  * [14] WE
14982  *
14983  * [13] Reserved
14984  *
14985  * [12:0] A12:A0
14986  *
14987  * RLDRAM3
14988  *
14989  * [26] Reserved
14990  *
14991  * [25:22] BA3:BA0
14992  *
14993  * [21] REF
14994  *
14995  * [20] WE
14996  *
14997  * [19:0] A19:A0
14998  *
14999  * Field Access Macros:
15000  *
15001  */
15002 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE register field. */
15003 #define ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE_LSB 0
15004 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE register field. */
15005 #define ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE_MSB 31
15006 /* The width in bits of the ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE register field. */
15007 #define ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE_WIDTH 32
15008 /* The mask used to set the ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE register field value. */
15009 #define ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE_SET_MSK 0xffffffff
15010 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE register field value. */
15011 #define ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE_CLR_MSK 0x00000000
15012 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE register field is UNKNOWN. */
15013 #define ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE_RESET 0x0
15014 /* Extracts the ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE field value from a register. */
15015 #define ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE_GET(value) (((value) & 0xffffffff) >> 0)
15016 /* Produces a ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE register field value suitable for setting the register. */
15017 #define ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE_SET(value) (((value) << 0) & 0xffffffff)
15018 
15019 #ifndef __ASSEMBLY__
15020 /*
15021  * WARNING: The C register and register group struct declarations are provided for
15022  * convenience and illustrative purposes. They should, however, be used with
15023  * caution as the C language standard provides no guarantees about the alignment or
15024  * atomicity of device memory accesses. The recommended practice for coding device
15025  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15026  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15027  * alt_write_dword() functions for 64 bit registers.
15028  *
15029  * The struct declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND13.
15030  */
15031 struct ALT_MPFE_IOHMC_REG_SIDEBAND13_s
15032 {
15033  volatile uint32_t mr_cmd_opcode : 32; /* ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE */
15034 };
15035 
15036 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND13. */
15037 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND13_s ALT_MPFE_IOHMC_REG_SIDEBAND13_t;
15038 #endif /* __ASSEMBLY__ */
15039 
15040 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND13 register. */
15041 #define ALT_MPFE_IOHMC_REG_SIDEBAND13_RESET 0x00000000
15042 /* The byte offset of the ALT_MPFE_IOHMC_REG_SIDEBAND13 register from the beginning of the component. */
15043 #define ALT_MPFE_IOHMC_REG_SIDEBAND13_OFST 0xe0
15044 
15045 /*
15046  * Register : reg_sideband14
15047  *
15048  * Register Layout
15049  *
15050  * Bits | Access | Reset | Description
15051  * :--------|:-------|:--------|:-----------------------------------------------
15052  * [15:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK
15053  * [31:16] | ??? | Unknown | *UNDEFINED*
15054  *
15055  */
15056 /*
15057  * Field : mmr_refresh_bank
15058  *
15059  * iohmc_ctrl_mmr_top_inst.mmr_refresh_bank[15:0]
15060  *
15061  * Name:LPDDR3 Per Bank Refresh
15062  *
15063  * Description:When asserted, indictates LPDDR3 per bank Refresh. When not
15064  * asserted, indicates LPDDR3 all bank refresh.
15065  *
15066  * Field Access Macros:
15067  *
15068  */
15069 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK register field. */
15070 #define ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK_LSB 0
15071 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK register field. */
15072 #define ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK_MSB 15
15073 /* The width in bits of the ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK register field. */
15074 #define ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK_WIDTH 16
15075 /* The mask used to set the ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK register field value. */
15076 #define ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK_SET_MSK 0x0000ffff
15077 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK register field value. */
15078 #define ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK_CLR_MSK 0xffff0000
15079 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK register field is UNKNOWN. */
15080 #define ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK_RESET 0x0
15081 /* Extracts the ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK field value from a register. */
15082 #define ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK_GET(value) (((value) & 0x0000ffff) >> 0)
15083 /* Produces a ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK register field value suitable for setting the register. */
15084 #define ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK_SET(value) (((value) << 0) & 0x0000ffff)
15085 
15086 #ifndef __ASSEMBLY__
15087 /*
15088  * WARNING: The C register and register group struct declarations are provided for
15089  * convenience and illustrative purposes. They should, however, be used with
15090  * caution as the C language standard provides no guarantees about the alignment or
15091  * atomicity of device memory accesses. The recommended practice for coding device
15092  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15093  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15094  * alt_write_dword() functions for 64 bit registers.
15095  *
15096  * The struct declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND14.
15097  */
15098 struct ALT_MPFE_IOHMC_REG_SIDEBAND14_s
15099 {
15100  volatile uint32_t mmr_refresh_bank : 16; /* ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK */
15101  uint32_t : 16; /* *UNDEFINED* */
15102 };
15103 
15104 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND14. */
15105 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND14_s ALT_MPFE_IOHMC_REG_SIDEBAND14_t;
15106 #endif /* __ASSEMBLY__ */
15107 
15108 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND14 register. */
15109 #define ALT_MPFE_IOHMC_REG_SIDEBAND14_RESET 0x00000000
15110 /* The byte offset of the ALT_MPFE_IOHMC_REG_SIDEBAND14 register from the beginning of the component. */
15111 #define ALT_MPFE_IOHMC_REG_SIDEBAND14_OFST 0xe4
15112 
15113 /*
15114  * Register : reg_sideband15
15115  *
15116  * Register Layout
15117  *
15118  * Bits | Access | Reset | Description
15119  * :-------|:-------|:--------|:---------------------------------------------
15120  * [3:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK
15121  * [31:4] | ??? | Unknown | *UNDEFINED*
15122  *
15123  */
15124 /*
15125  * Field : mmr_stall_rank
15126  *
15127  * iohmc_ctrl_mmr_top_inst.mmr_stall_rank[3:0]
15128  *
15129  * Name:Stall Rank
15130  *
15131  * Description:Setting to 1 to stall the corresponding rank.
15132  *
15133  * Field Access Macros:
15134  *
15135  */
15136 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK register field. */
15137 #define ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK_LSB 0
15138 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK register field. */
15139 #define ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK_MSB 3
15140 /* The width in bits of the ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK register field. */
15141 #define ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK_WIDTH 4
15142 /* The mask used to set the ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK register field value. */
15143 #define ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK_SET_MSK 0x0000000f
15144 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK register field value. */
15145 #define ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK_CLR_MSK 0xfffffff0
15146 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK register field is UNKNOWN. */
15147 #define ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK_RESET 0x0
15148 /* Extracts the ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK field value from a register. */
15149 #define ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK_GET(value) (((value) & 0x0000000f) >> 0)
15150 /* Produces a ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK register field value suitable for setting the register. */
15151 #define ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK_SET(value) (((value) << 0) & 0x0000000f)
15152 
15153 #ifndef __ASSEMBLY__
15154 /*
15155  * WARNING: The C register and register group struct declarations are provided for
15156  * convenience and illustrative purposes. They should, however, be used with
15157  * caution as the C language standard provides no guarantees about the alignment or
15158  * atomicity of device memory accesses. The recommended practice for coding device
15159  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15160  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15161  * alt_write_dword() functions for 64 bit registers.
15162  *
15163  * The struct declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND15.
15164  */
15165 struct ALT_MPFE_IOHMC_REG_SIDEBAND15_s
15166 {
15167  volatile uint32_t mmr_stall_rank : 4; /* ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK */
15168  uint32_t : 28; /* *UNDEFINED* */
15169 };
15170 
15171 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND15. */
15172 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND15_s ALT_MPFE_IOHMC_REG_SIDEBAND15_t;
15173 #endif /* __ASSEMBLY__ */
15174 
15175 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND15 register. */
15176 #define ALT_MPFE_IOHMC_REG_SIDEBAND15_RESET 0x00000000
15177 /* The byte offset of the ALT_MPFE_IOHMC_REG_SIDEBAND15 register from the beginning of the component. */
15178 #define ALT_MPFE_IOHMC_REG_SIDEBAND15_OFST 0xe8
15179 
15180 /*
15181  * Register : reg_dramsts
15182  *
15183  * Register Layout
15184  *
15185  * Bits | Access | Reset | Description
15186  * :-------|:-------|:--------|:-------------------------------------------
15187  * [0] | R | Unknown | ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS
15188  * [1] | R | Unknown | ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL
15189  * [31:2] | ??? | Unknown | *UNDEFINED*
15190  *
15191  */
15192 /*
15193  * Field : phy_cal_success
15194  *
15195  * iohmc_ctrl_mmr_top_inst.phy_cal_success
15196  *
15197  * Name:PHY Calibration Successful
15198  *
15199  * Description:This bit will be set to 1 if the PHY was able to successfully
15200  * calibrate.
15201  *
15202  * Field Access Macros:
15203  *
15204  */
15205 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS register field. */
15206 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS_LSB 0
15207 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS register field. */
15208 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS_MSB 0
15209 /* The width in bits of the ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS register field. */
15210 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS_WIDTH 1
15211 /* The mask used to set the ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS register field value. */
15212 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS_SET_MSK 0x00000001
15213 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS register field value. */
15214 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS_CLR_MSK 0xfffffffe
15215 /* The reset value of the ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS register field is UNKNOWN. */
15216 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS_RESET 0x0
15217 /* Extracts the ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS field value from a register. */
15218 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS_GET(value) (((value) & 0x00000001) >> 0)
15219 /* Produces a ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS register field value suitable for setting the register. */
15220 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS_SET(value) (((value) << 0) & 0x00000001)
15221 
15222 /*
15223  * Field : phy_cal_fail
15224  *
15225  * iohmc_ctrl_mmr_top_inst.phy_cal_fail
15226  *
15227  * Name:PHY Calibration Failed
15228  *
15229  * Description:This bit will be set to 1 if the PHY was unable to calibrate.
15230  *
15231  * Field Access Macros:
15232  *
15233  */
15234 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL register field. */
15235 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL_LSB 1
15236 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL register field. */
15237 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL_MSB 1
15238 /* The width in bits of the ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL register field. */
15239 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL_WIDTH 1
15240 /* The mask used to set the ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL register field value. */
15241 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL_SET_MSK 0x00000002
15242 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL register field value. */
15243 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL_CLR_MSK 0xfffffffd
15244 /* The reset value of the ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL register field is UNKNOWN. */
15245 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL_RESET 0x0
15246 /* Extracts the ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL field value from a register. */
15247 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL_GET(value) (((value) & 0x00000002) >> 1)
15248 /* Produces a ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL register field value suitable for setting the register. */
15249 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL_SET(value) (((value) << 1) & 0x00000002)
15250 
15251 #ifndef __ASSEMBLY__
15252 /*
15253  * WARNING: The C register and register group struct declarations are provided for
15254  * convenience and illustrative purposes. They should, however, be used with
15255  * caution as the C language standard provides no guarantees about the alignment or
15256  * atomicity of device memory accesses. The recommended practice for coding device
15257  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15258  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15259  * alt_write_dword() functions for 64 bit registers.
15260  *
15261  * The struct declaration for register ALT_MPFE_IOHMC_REG_DRAMSTS.
15262  */
15263 struct ALT_MPFE_IOHMC_REG_DRAMSTS_s
15264 {
15265  const volatile uint32_t phy_cal_success : 1; /* ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS */
15266  const volatile uint32_t phy_cal_fail : 1; /* ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL */
15267  uint32_t : 30; /* *UNDEFINED* */
15268 };
15269 
15270 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_DRAMSTS. */
15271 typedef struct ALT_MPFE_IOHMC_REG_DRAMSTS_s ALT_MPFE_IOHMC_REG_DRAMSTS_t;
15272 #endif /* __ASSEMBLY__ */
15273 
15274 /* The reset value of the ALT_MPFE_IOHMC_REG_DRAMSTS register. */
15275 #define ALT_MPFE_IOHMC_REG_DRAMSTS_RESET 0x00000000
15276 /* The byte offset of the ALT_MPFE_IOHMC_REG_DRAMSTS register from the beginning of the component. */
15277 #define ALT_MPFE_IOHMC_REG_DRAMSTS_OFST 0xec
15278 
15279 /*
15280  * Register : reg_dbgdone
15281  *
15282  * Register Layout
15283  *
15284  * Bits | Access | Reset | Description
15285  * :-------|:-------|:--------|:------------------------------------
15286  * [0] | R | Unknown | ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE
15287  * [31:1] | ??? | Unknown | *UNDEFINED*
15288  *
15289  */
15290 /*
15291  * Field : dbg_done
15292  *
15293  * iohmc_ctrl_mmr_top_inst.dbg_done
15294  *
15295  * Name:Debug Test Done
15296  *
15297  * Description:Indicates the debug test is completed.
15298  *
15299  * Field Access Macros:
15300  *
15301  */
15302 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE register field. */
15303 #define ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE_LSB 0
15304 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE register field. */
15305 #define ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE_MSB 0
15306 /* The width in bits of the ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE register field. */
15307 #define ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE_WIDTH 1
15308 /* The mask used to set the ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE register field value. */
15309 #define ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE_SET_MSK 0x00000001
15310 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE register field value. */
15311 #define ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE_CLR_MSK 0xfffffffe
15312 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE register field is UNKNOWN. */
15313 #define ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE_RESET 0x0
15314 /* Extracts the ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE field value from a register. */
15315 #define ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE_GET(value) (((value) & 0x00000001) >> 0)
15316 /* Produces a ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE register field value suitable for setting the register. */
15317 #define ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE_SET(value) (((value) << 0) & 0x00000001)
15318 
15319 #ifndef __ASSEMBLY__
15320 /*
15321  * WARNING: The C register and register group struct declarations are provided for
15322  * convenience and illustrative purposes. They should, however, be used with
15323  * caution as the C language standard provides no guarantees about the alignment or
15324  * atomicity of device memory accesses. The recommended practice for coding device
15325  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15326  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15327  * alt_write_dword() functions for 64 bit registers.
15328  *
15329  * The struct declaration for register ALT_MPFE_IOHMC_REG_DBGDONE.
15330  */
15331 struct ALT_MPFE_IOHMC_REG_DBGDONE_s
15332 {
15333  const volatile uint32_t dbg_done : 1; /* ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE */
15334  uint32_t : 31; /* *UNDEFINED* */
15335 };
15336 
15337 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_DBGDONE. */
15338 typedef struct ALT_MPFE_IOHMC_REG_DBGDONE_s ALT_MPFE_IOHMC_REG_DBGDONE_t;
15339 #endif /* __ASSEMBLY__ */
15340 
15341 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGDONE register. */
15342 #define ALT_MPFE_IOHMC_REG_DBGDONE_RESET 0x00000000
15343 /* The byte offset of the ALT_MPFE_IOHMC_REG_DBGDONE register from the beginning of the component. */
15344 #define ALT_MPFE_IOHMC_REG_DBGDONE_OFST 0xf0
15345 
15346 /*
15347  * Register : reg_dbgsignals
15348  *
15349  * Register Layout
15350  *
15351  * Bits | Access | Reset | Description
15352  * :-------|:-------|:--------|:----------------------------------------------
15353  * [31:0] | R | Unknown | ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT
15354  *
15355  */
15356 /*
15357  * Field : dbg_signals_out
15358  *
15359  * iohmc_ctrl_mmr_top_inst.dbg_signals_out[31:0]
15360  *
15361  * Name:Debug Signals
15362  *
15363  * Description:Available debug signals.
15364  *
15365  * Field Access Macros:
15366  *
15367  */
15368 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT register field. */
15369 #define ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT_LSB 0
15370 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT register field. */
15371 #define ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT_MSB 31
15372 /* The width in bits of the ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT register field. */
15373 #define ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT_WIDTH 32
15374 /* The mask used to set the ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT register field value. */
15375 #define ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT_SET_MSK 0xffffffff
15376 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT register field value. */
15377 #define ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT_CLR_MSK 0x00000000
15378 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT register field is UNKNOWN. */
15379 #define ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT_RESET 0x0
15380 /* Extracts the ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT field value from a register. */
15381 #define ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT_GET(value) (((value) & 0xffffffff) >> 0)
15382 /* Produces a ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT register field value suitable for setting the register. */
15383 #define ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT_SET(value) (((value) << 0) & 0xffffffff)
15384 
15385 #ifndef __ASSEMBLY__
15386 /*
15387  * WARNING: The C register and register group struct declarations are provided for
15388  * convenience and illustrative purposes. They should, however, be used with
15389  * caution as the C language standard provides no guarantees about the alignment or
15390  * atomicity of device memory accesses. The recommended practice for coding device
15391  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15392  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15393  * alt_write_dword() functions for 64 bit registers.
15394  *
15395  * The struct declaration for register ALT_MPFE_IOHMC_REG_DBGSIGNALS.
15396  */
15397 struct ALT_MPFE_IOHMC_REG_DBGSIGNALS_s
15398 {
15399  const volatile uint32_t dbg_signals_out : 32; /* ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT */
15400 };
15401 
15402 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_DBGSIGNALS. */
15403 typedef struct ALT_MPFE_IOHMC_REG_DBGSIGNALS_s ALT_MPFE_IOHMC_REG_DBGSIGNALS_t;
15404 #endif /* __ASSEMBLY__ */
15405 
15406 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGSIGNALS register. */
15407 #define ALT_MPFE_IOHMC_REG_DBGSIGNALS_RESET 0x00000000
15408 /* The byte offset of the ALT_MPFE_IOHMC_REG_DBGSIGNALS register from the beginning of the component. */
15409 #define ALT_MPFE_IOHMC_REG_DBGSIGNALS_OFST 0xf4
15410 
15411 /*
15412  * Register : reg_dbgreset
15413  *
15414  * Register Layout
15415  *
15416  * Bits | Access | Reset | Description
15417  * :-------|:-------|:--------|:-----------------------------------------------
15418  * [0] | RW | Unknown | ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET
15419  * [1] | RW | Unknown | ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET
15420  * [31:2] | ??? | Unknown | *UNDEFINED*
15421  *
15422  */
15423 /*
15424  * Field : counter_zero_reset
15425  *
15426  * iohmc_ctrl_mmr_top_inst.counter_zero_reset
15427  *
15428  * Name:Reserved
15429  *
15430  * Description:TBD
15431  *
15432  * Field Access Macros:
15433  *
15434  */
15435 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET register field. */
15436 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET_LSB 0
15437 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET register field. */
15438 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET_MSB 0
15439 /* The width in bits of the ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET register field. */
15440 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET_WIDTH 1
15441 /* The mask used to set the ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET register field value. */
15442 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET_SET_MSK 0x00000001
15443 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET register field value. */
15444 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET_CLR_MSK 0xfffffffe
15445 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET register field is UNKNOWN. */
15446 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET_RESET 0x0
15447 /* Extracts the ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET field value from a register. */
15448 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET_GET(value) (((value) & 0x00000001) >> 0)
15449 /* Produces a ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET register field value suitable for setting the register. */
15450 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET_SET(value) (((value) << 0) & 0x00000001)
15451 
15452 /*
15453  * Field : counter_one_reset
15454  *
15455  * iohmc_ctrl_mmr_top_inst.counter_one_reset
15456  *
15457  * Name:Reserved
15458  *
15459  * Description:TBD
15460  *
15461  * Field Access Macros:
15462  *
15463  */
15464 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET register field. */
15465 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET_LSB 1
15466 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET register field. */
15467 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET_MSB 1
15468 /* The width in bits of the ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET register field. */
15469 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET_WIDTH 1
15470 /* The mask used to set the ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET register field value. */
15471 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET_SET_MSK 0x00000002
15472 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET register field value. */
15473 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET_CLR_MSK 0xfffffffd
15474 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET register field is UNKNOWN. */
15475 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET_RESET 0x0
15476 /* Extracts the ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET field value from a register. */
15477 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET_GET(value) (((value) & 0x00000002) >> 1)
15478 /* Produces a ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET register field value suitable for setting the register. */
15479 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET_SET(value) (((value) << 1) & 0x00000002)
15480 
15481 #ifndef __ASSEMBLY__
15482 /*
15483  * WARNING: The C register and register group struct declarations are provided for
15484  * convenience and illustrative purposes. They should, however, be used with
15485  * caution as the C language standard provides no guarantees about the alignment or
15486  * atomicity of device memory accesses. The recommended practice for coding device
15487  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15488  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15489  * alt_write_dword() functions for 64 bit registers.
15490  *
15491  * The struct declaration for register ALT_MPFE_IOHMC_REG_DBGRESET.
15492  */
15493 struct ALT_MPFE_IOHMC_REG_DBGRESET_s
15494 {
15495  volatile uint32_t counter_zero_reset : 1; /* ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET */
15496  volatile uint32_t counter_one_reset : 1; /* ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET */
15497  uint32_t : 30; /* *UNDEFINED* */
15498 };
15499 
15500 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_DBGRESET. */
15501 typedef struct ALT_MPFE_IOHMC_REG_DBGRESET_s ALT_MPFE_IOHMC_REG_DBGRESET_t;
15502 #endif /* __ASSEMBLY__ */
15503 
15504 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGRESET register. */
15505 #define ALT_MPFE_IOHMC_REG_DBGRESET_RESET 0x00000000
15506 /* The byte offset of the ALT_MPFE_IOHMC_REG_DBGRESET register from the beginning of the component. */
15507 #define ALT_MPFE_IOHMC_REG_DBGRESET_OFST 0xf8
15508 
15509 /*
15510  * Register : reg_dbgmatch
15511  *
15512  * Register Layout
15513  *
15514  * Bits | Access | Reset | Description
15515  * :-------|:-------|:--------|:----------------------------------------
15516  * [31:0] | R | Unknown | ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE
15517  *
15518  */
15519 /*
15520  * Field : counter_one
15521  *
15522  * iohmc_ctrl_mmr_top_inst.counter_one[31:0]
15523  *
15524  * Name:Reserved
15525  *
15526  * Description:TBD
15527  *
15528  * Field Access Macros:
15529  *
15530  */
15531 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE register field. */
15532 #define ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE_LSB 0
15533 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE register field. */
15534 #define ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE_MSB 31
15535 /* The width in bits of the ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE register field. */
15536 #define ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE_WIDTH 32
15537 /* The mask used to set the ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE register field value. */
15538 #define ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE_SET_MSK 0xffffffff
15539 /* The mask used to clear the ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE register field value. */
15540 #define ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE_CLR_MSK 0x00000000
15541 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE register field is UNKNOWN. */
15542 #define ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE_RESET 0x0
15543 /* Extracts the ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE field value from a register. */
15544 #define ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE_GET(value) (((value) & 0xffffffff) >> 0)
15545 /* Produces a ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE register field value suitable for setting the register. */
15546 #define ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE_SET(value) (((value) << 0) & 0xffffffff)
15547 
15548 #ifndef __ASSEMBLY__
15549 /*
15550  * WARNING: The C register and register group struct declarations are provided for
15551  * convenience and illustrative purposes. They should, however, be used with
15552  * caution as the C language standard provides no guarantees about the alignment or
15553  * atomicity of device memory accesses. The recommended practice for coding device
15554  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15555  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15556  * alt_write_dword() functions for 64 bit registers.
15557  *
15558  * The struct declaration for register ALT_MPFE_IOHMC_REG_DBGMATCH.
15559  */
15560 struct ALT_MPFE_IOHMC_REG_DBGMATCH_s
15561 {
15562  const volatile uint32_t counter_one : 32; /* ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE */
15563 };
15564 
15565 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_DBGMATCH. */
15566 typedef struct ALT_MPFE_IOHMC_REG_DBGMATCH_s ALT_MPFE_IOHMC_REG_DBGMATCH_t;
15567 #endif /* __ASSEMBLY__ */
15568 
15569 /* The reset value of the ALT_MPFE_IOHMC_REG_DBGMATCH register. */
15570 #define ALT_MPFE_IOHMC_REG_DBGMATCH_RESET 0x00000000
15571 /* The byte offset of the ALT_MPFE_IOHMC_REG_DBGMATCH register from the beginning of the component. */
15572 #define ALT_MPFE_IOHMC_REG_DBGMATCH_OFST 0xfc
15573 
15574 /*
15575  * Register : reg_counter0mask
15576  *
15577  * Register Layout
15578  *
15579  * Bits | Access | Reset | Description
15580  * :-------|:-------|:--------|:--------------------------------------------------
15581  * [31:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK
15582  *
15583  */
15584 /*
15585  * Field : counter_zero_mask
15586  *
15587  * iohmc_ctrl_mmr_top_inst.counter_zero_mask[31:0]
15588  *
15589  * Name:Reserved
15590  *
15591  * Description:TBD
15592  *
15593  * Field Access Macros:
15594  *
15595  */
15596 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK register field. */
15597 #define ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK_LSB 0
15598 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK register field. */
15599 #define ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK_MSB 31
15600 /* The width in bits of the ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK register field. */
15601 #define ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK_WIDTH 32
15602 /* The mask used to set the ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK register field value. */
15603 #define ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK_SET_MSK 0xffffffff
15604 /* The mask used to clear the ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK register field value. */
15605 #define ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK_CLR_MSK 0x00000000
15606 /* The reset value of the ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK register field is UNKNOWN. */
15607 #define ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK_RESET 0x0
15608 /* Extracts the ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK field value from a register. */
15609 #define ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK_GET(value) (((value) & 0xffffffff) >> 0)
15610 /* Produces a ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK register field value suitable for setting the register. */
15611 #define ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK_SET(value) (((value) << 0) & 0xffffffff)
15612 
15613 #ifndef __ASSEMBLY__
15614 /*
15615  * WARNING: The C register and register group struct declarations are provided for
15616  * convenience and illustrative purposes. They should, however, be used with
15617  * caution as the C language standard provides no guarantees about the alignment or
15618  * atomicity of device memory accesses. The recommended practice for coding device
15619  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15620  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15621  * alt_write_dword() functions for 64 bit registers.
15622  *
15623  * The struct declaration for register ALT_MPFE_IOHMC_REG_COUNTER0MASK.
15624  */
15625 struct ALT_MPFE_IOHMC_REG_COUNTER0MASK_s
15626 {
15627  volatile uint32_t counter_zero_mask : 32; /* ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK */
15628 };
15629 
15630 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_COUNTER0MASK. */
15631 typedef struct ALT_MPFE_IOHMC_REG_COUNTER0MASK_s ALT_MPFE_IOHMC_REG_COUNTER0MASK_t;
15632 #endif /* __ASSEMBLY__ */
15633 
15634 /* The reset value of the ALT_MPFE_IOHMC_REG_COUNTER0MASK register. */
15635 #define ALT_MPFE_IOHMC_REG_COUNTER0MASK_RESET 0x00000000
15636 /* The byte offset of the ALT_MPFE_IOHMC_REG_COUNTER0MASK register from the beginning of the component. */
15637 #define ALT_MPFE_IOHMC_REG_COUNTER0MASK_OFST 0x100
15638 
15639 /*
15640  * Register : reg_counter1mask
15641  *
15642  * Register Layout
15643  *
15644  * Bits | Access | Reset | Description
15645  * :-------|:-------|:--------|:-------------------------------------------------
15646  * [31:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK
15647  *
15648  */
15649 /*
15650  * Field : counter_one_mask
15651  *
15652  * iohmc_ctrl_mmr_top_inst.counter_one_mask[31:0]
15653  *
15654  * Name:Reserved
15655  *
15656  * Description:TBD
15657  *
15658  * Field Access Macros:
15659  *
15660  */
15661 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK register field. */
15662 #define ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK_LSB 0
15663 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK register field. */
15664 #define ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK_MSB 31
15665 /* The width in bits of the ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK register field. */
15666 #define ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK_WIDTH 32
15667 /* The mask used to set the ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK register field value. */
15668 #define ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK_SET_MSK 0xffffffff
15669 /* The mask used to clear the ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK register field value. */
15670 #define ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK_CLR_MSK 0x00000000
15671 /* The reset value of the ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK register field is UNKNOWN. */
15672 #define ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK_RESET 0x0
15673 /* Extracts the ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK field value from a register. */
15674 #define ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK_GET(value) (((value) & 0xffffffff) >> 0)
15675 /* Produces a ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK register field value suitable for setting the register. */
15676 #define ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK_SET(value) (((value) << 0) & 0xffffffff)
15677 
15678 #ifndef __ASSEMBLY__
15679 /*
15680  * WARNING: The C register and register group struct declarations are provided for
15681  * convenience and illustrative purposes. They should, however, be used with
15682  * caution as the C language standard provides no guarantees about the alignment or
15683  * atomicity of device memory accesses. The recommended practice for coding device
15684  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15685  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15686  * alt_write_dword() functions for 64 bit registers.
15687  *
15688  * The struct declaration for register ALT_MPFE_IOHMC_REG_COUNTER1MASK.
15689  */
15690 struct ALT_MPFE_IOHMC_REG_COUNTER1MASK_s
15691 {
15692  volatile uint32_t counter_one_mask : 32; /* ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK */
15693 };
15694 
15695 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_COUNTER1MASK. */
15696 typedef struct ALT_MPFE_IOHMC_REG_COUNTER1MASK_s ALT_MPFE_IOHMC_REG_COUNTER1MASK_t;
15697 #endif /* __ASSEMBLY__ */
15698 
15699 /* The reset value of the ALT_MPFE_IOHMC_REG_COUNTER1MASK register. */
15700 #define ALT_MPFE_IOHMC_REG_COUNTER1MASK_RESET 0x00000000
15701 /* The byte offset of the ALT_MPFE_IOHMC_REG_COUNTER1MASK register from the beginning of the component. */
15702 #define ALT_MPFE_IOHMC_REG_COUNTER1MASK_OFST 0x104
15703 
15704 /*
15705  * Register : reg_counter0match
15706  *
15707  * Register Layout
15708  *
15709  * Bits | Access | Reset | Description
15710  * :-------|:-------|:--------|:----------------------------------------------------
15711  * [31:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH
15712  *
15713  */
15714 /*
15715  * Field : counter_zero_match
15716  *
15717  * iohmc_ctrl_mmr_top_inst.counter_zero_match[31:0]
15718  *
15719  * Name:Reserved
15720  *
15721  * Description:TBD
15722  *
15723  * Field Access Macros:
15724  *
15725  */
15726 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH register field. */
15727 #define ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH_LSB 0
15728 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH register field. */
15729 #define ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH_MSB 31
15730 /* The width in bits of the ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH register field. */
15731 #define ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH_WIDTH 32
15732 /* The mask used to set the ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH register field value. */
15733 #define ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH_SET_MSK 0xffffffff
15734 /* The mask used to clear the ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH register field value. */
15735 #define ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH_CLR_MSK 0x00000000
15736 /* The reset value of the ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH register field is UNKNOWN. */
15737 #define ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH_RESET 0x0
15738 /* Extracts the ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH field value from a register. */
15739 #define ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH_GET(value) (((value) & 0xffffffff) >> 0)
15740 /* Produces a ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH register field value suitable for setting the register. */
15741 #define ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH_SET(value) (((value) << 0) & 0xffffffff)
15742 
15743 #ifndef __ASSEMBLY__
15744 /*
15745  * WARNING: The C register and register group struct declarations are provided for
15746  * convenience and illustrative purposes. They should, however, be used with
15747  * caution as the C language standard provides no guarantees about the alignment or
15748  * atomicity of device memory accesses. The recommended practice for coding device
15749  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15750  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15751  * alt_write_dword() functions for 64 bit registers.
15752  *
15753  * The struct declaration for register ALT_MPFE_IOHMC_REG_COUNTER0MATCH.
15754  */
15755 struct ALT_MPFE_IOHMC_REG_COUNTER0MATCH_s
15756 {
15757  volatile uint32_t counter_zero_match : 32; /* ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH */
15758 };
15759 
15760 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_COUNTER0MATCH. */
15761 typedef struct ALT_MPFE_IOHMC_REG_COUNTER0MATCH_s ALT_MPFE_IOHMC_REG_COUNTER0MATCH_t;
15762 #endif /* __ASSEMBLY__ */
15763 
15764 /* The reset value of the ALT_MPFE_IOHMC_REG_COUNTER0MATCH register. */
15765 #define ALT_MPFE_IOHMC_REG_COUNTER0MATCH_RESET 0x00000000
15766 /* The byte offset of the ALT_MPFE_IOHMC_REG_COUNTER0MATCH register from the beginning of the component. */
15767 #define ALT_MPFE_IOHMC_REG_COUNTER0MATCH_OFST 0x108
15768 
15769 /*
15770  * Register : reg_counter1match
15771  *
15772  * Register Layout
15773  *
15774  * Bits | Access | Reset | Description
15775  * :-------|:-------|:--------|:---------------------------------------------------
15776  * [31:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH
15777  *
15778  */
15779 /*
15780  * Field : counter_one_match
15781  *
15782  * iohmc_ctrl_mmr_top_inst.counter_one_match[31:0]
15783  *
15784  * Name:Reserved
15785  *
15786  * Description:TBD
15787  *
15788  * Field Access Macros:
15789  *
15790  */
15791 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH register field. */
15792 #define ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH_LSB 0
15793 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH register field. */
15794 #define ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH_MSB 31
15795 /* The width in bits of the ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH register field. */
15796 #define ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH_WIDTH 32
15797 /* The mask used to set the ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH register field value. */
15798 #define ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH_SET_MSK 0xffffffff
15799 /* The mask used to clear the ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH register field value. */
15800 #define ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH_CLR_MSK 0x00000000
15801 /* The reset value of the ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH register field is UNKNOWN. */
15802 #define ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH_RESET 0x0
15803 /* Extracts the ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH field value from a register. */
15804 #define ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH_GET(value) (((value) & 0xffffffff) >> 0)
15805 /* Produces a ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH register field value suitable for setting the register. */
15806 #define ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH_SET(value) (((value) << 0) & 0xffffffff)
15807 
15808 #ifndef __ASSEMBLY__
15809 /*
15810  * WARNING: The C register and register group struct declarations are provided for
15811  * convenience and illustrative purposes. They should, however, be used with
15812  * caution as the C language standard provides no guarantees about the alignment or
15813  * atomicity of device memory accesses. The recommended practice for coding device
15814  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15815  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15816  * alt_write_dword() functions for 64 bit registers.
15817  *
15818  * The struct declaration for register ALT_MPFE_IOHMC_REG_COUNTER1MATCH.
15819  */
15820 struct ALT_MPFE_IOHMC_REG_COUNTER1MATCH_s
15821 {
15822  volatile uint32_t counter_one_match : 32; /* ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH */
15823 };
15824 
15825 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_COUNTER1MATCH. */
15826 typedef struct ALT_MPFE_IOHMC_REG_COUNTER1MATCH_s ALT_MPFE_IOHMC_REG_COUNTER1MATCH_t;
15827 #endif /* __ASSEMBLY__ */
15828 
15829 /* The reset value of the ALT_MPFE_IOHMC_REG_COUNTER1MATCH register. */
15830 #define ALT_MPFE_IOHMC_REG_COUNTER1MATCH_RESET 0x00000000
15831 /* The byte offset of the ALT_MPFE_IOHMC_REG_COUNTER1MATCH register from the beginning of the component. */
15832 #define ALT_MPFE_IOHMC_REG_COUNTER1MATCH_OFST 0x10c
15833 
15834 /*
15835  * Register : reg_niosreserve0
15836  *
15837  * Register Layout
15838  *
15839  * Bits | Access | Reset | Description
15840  * :--------|:-------|:--------|:----------------------------------------------
15841  * [15:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0
15842  * [31:16] | ??? | Unknown | *UNDEFINED*
15843  *
15844  */
15845 /*
15846  * Field : nios_reserve0
15847  *
15848  * iohmc_ctrl_mmr_top_inst.nios_reserve0[15:0]
15849  *
15850  * Name:Reserved
15851  *
15852  * Description:TBD
15853  *
15854  * Field Access Macros:
15855  *
15856  */
15857 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0 register field. */
15858 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0_LSB 0
15859 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0 register field. */
15860 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0_MSB 15
15861 /* The width in bits of the ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0 register field. */
15862 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0_WIDTH 16
15863 /* The mask used to set the ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0 register field value. */
15864 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0_SET_MSK 0x0000ffff
15865 /* The mask used to clear the ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0 register field value. */
15866 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0_CLR_MSK 0xffff0000
15867 /* The reset value of the ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0 register field is UNKNOWN. */
15868 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0_RESET 0x0
15869 /* Extracts the ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0 field value from a register. */
15870 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0_GET(value) (((value) & 0x0000ffff) >> 0)
15871 /* Produces a ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0 register field value suitable for setting the register. */
15872 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0_SET(value) (((value) << 0) & 0x0000ffff)
15873 
15874 #ifndef __ASSEMBLY__
15875 /*
15876  * WARNING: The C register and register group struct declarations are provided for
15877  * convenience and illustrative purposes. They should, however, be used with
15878  * caution as the C language standard provides no guarantees about the alignment or
15879  * atomicity of device memory accesses. The recommended practice for coding device
15880  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15881  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15882  * alt_write_dword() functions for 64 bit registers.
15883  *
15884  * The struct declaration for register ALT_MPFE_IOHMC_REG_NIOSRESERVE0.
15885  */
15886 struct ALT_MPFE_IOHMC_REG_NIOSRESERVE0_s
15887 {
15888  volatile uint32_t nios_reserve0 : 16; /* ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0 */
15889  uint32_t : 16; /* *UNDEFINED* */
15890 };
15891 
15892 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_NIOSRESERVE0. */
15893 typedef struct ALT_MPFE_IOHMC_REG_NIOSRESERVE0_s ALT_MPFE_IOHMC_REG_NIOSRESERVE0_t;
15894 #endif /* __ASSEMBLY__ */
15895 
15896 /* The reset value of the ALT_MPFE_IOHMC_REG_NIOSRESERVE0 register. */
15897 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE0_RESET 0x00000000
15898 /* The byte offset of the ALT_MPFE_IOHMC_REG_NIOSRESERVE0 register from the beginning of the component. */
15899 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE0_OFST 0x110
15900 
15901 /*
15902  * Register : reg_niosreserve1
15903  *
15904  * Register Layout
15905  *
15906  * Bits | Access | Reset | Description
15907  * :--------|:-------|:--------|:----------------------------------------------
15908  * [15:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1
15909  * [31:16] | ??? | Unknown | *UNDEFINED*
15910  *
15911  */
15912 /*
15913  * Field : nios_reserve1
15914  *
15915  * iohmc_ctrl_mmr_top_inst.nios_reserve1[15:0]
15916  *
15917  * Name:Reserved
15918  *
15919  * Description:TBD
15920  *
15921  * Field Access Macros:
15922  *
15923  */
15924 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1 register field. */
15925 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1_LSB 0
15926 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1 register field. */
15927 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1_MSB 15
15928 /* The width in bits of the ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1 register field. */
15929 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1_WIDTH 16
15930 /* The mask used to set the ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1 register field value. */
15931 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1_SET_MSK 0x0000ffff
15932 /* The mask used to clear the ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1 register field value. */
15933 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1_CLR_MSK 0xffff0000
15934 /* The reset value of the ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1 register field is UNKNOWN. */
15935 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1_RESET 0x0
15936 /* Extracts the ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1 field value from a register. */
15937 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1_GET(value) (((value) & 0x0000ffff) >> 0)
15938 /* Produces a ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1 register field value suitable for setting the register. */
15939 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1_SET(value) (((value) << 0) & 0x0000ffff)
15940 
15941 #ifndef __ASSEMBLY__
15942 /*
15943  * WARNING: The C register and register group struct declarations are provided for
15944  * convenience and illustrative purposes. They should, however, be used with
15945  * caution as the C language standard provides no guarantees about the alignment or
15946  * atomicity of device memory accesses. The recommended practice for coding device
15947  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15948  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15949  * alt_write_dword() functions for 64 bit registers.
15950  *
15951  * The struct declaration for register ALT_MPFE_IOHMC_REG_NIOSRESERVE1.
15952  */
15953 struct ALT_MPFE_IOHMC_REG_NIOSRESERVE1_s
15954 {
15955  volatile uint32_t nios_reserve1 : 16; /* ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1 */
15956  uint32_t : 16; /* *UNDEFINED* */
15957 };
15958 
15959 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_NIOSRESERVE1. */
15960 typedef struct ALT_MPFE_IOHMC_REG_NIOSRESERVE1_s ALT_MPFE_IOHMC_REG_NIOSRESERVE1_t;
15961 #endif /* __ASSEMBLY__ */
15962 
15963 /* The reset value of the ALT_MPFE_IOHMC_REG_NIOSRESERVE1 register. */
15964 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE1_RESET 0x00000000
15965 /* The byte offset of the ALT_MPFE_IOHMC_REG_NIOSRESERVE1 register from the beginning of the component. */
15966 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE1_OFST 0x114
15967 
15968 /*
15969  * Register : reg_niosreserve2
15970  *
15971  * Register Layout
15972  *
15973  * Bits | Access | Reset | Description
15974  * :--------|:-------|:--------|:----------------------------------------------
15975  * [15:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2
15976  * [31:16] | ??? | Unknown | *UNDEFINED*
15977  *
15978  */
15979 /*
15980  * Field : nios_reserve2
15981  *
15982  * iohmc_ctrl_mmr_top_inst.nios_reserve2[15:0]
15983  *
15984  * Name:Reserved
15985  *
15986  * Description:TBD
15987  *
15988  * Field Access Macros:
15989  *
15990  */
15991 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2 register field. */
15992 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2_LSB 0
15993 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2 register field. */
15994 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2_MSB 15
15995 /* The width in bits of the ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2 register field. */
15996 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2_WIDTH 16
15997 /* The mask used to set the ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2 register field value. */
15998 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2_SET_MSK 0x0000ffff
15999 /* The mask used to clear the ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2 register field value. */
16000 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2_CLR_MSK 0xffff0000
16001 /* The reset value of the ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2 register field is UNKNOWN. */
16002 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2_RESET 0x0
16003 /* Extracts the ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2 field value from a register. */
16004 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2_GET(value) (((value) & 0x0000ffff) >> 0)
16005 /* Produces a ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2 register field value suitable for setting the register. */
16006 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2_SET(value) (((value) << 0) & 0x0000ffff)
16007 
16008 #ifndef __ASSEMBLY__
16009 /*
16010  * WARNING: The C register and register group struct declarations are provided for
16011  * convenience and illustrative purposes. They should, however, be used with
16012  * caution as the C language standard provides no guarantees about the alignment or
16013  * atomicity of device memory accesses. The recommended practice for coding device
16014  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16015  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16016  * alt_write_dword() functions for 64 bit registers.
16017  *
16018  * The struct declaration for register ALT_MPFE_IOHMC_REG_NIOSRESERVE2.
16019  */
16020 struct ALT_MPFE_IOHMC_REG_NIOSRESERVE2_s
16021 {
16022  volatile uint32_t nios_reserve2 : 16; /* ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2 */
16023  uint32_t : 16; /* *UNDEFINED* */
16024 };
16025 
16026 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_NIOSRESERVE2. */
16027 typedef struct ALT_MPFE_IOHMC_REG_NIOSRESERVE2_s ALT_MPFE_IOHMC_REG_NIOSRESERVE2_t;
16028 #endif /* __ASSEMBLY__ */
16029 
16030 /* The reset value of the ALT_MPFE_IOHMC_REG_NIOSRESERVE2 register. */
16031 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE2_RESET 0x00000000
16032 /* The byte offset of the ALT_MPFE_IOHMC_REG_NIOSRESERVE2 register from the beginning of the component. */
16033 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE2_OFST 0x118
16034 
16035 /*
16036  * Register : reg_sbcfg8
16037  *
16038  * Register Layout
16039  *
16040  * Bits | Access | Reset | Description
16041  * :--------|:-------|:--------|:------------------------------------------
16042  * [19:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5
16043  * [31:20] | ??? | Unknown | *UNDEFINED*
16044  *
16045  */
16046 /*
16047  * Field : cfg_sb_ddr4_mr5
16048  *
16049  * iohmc_ctrl_mmr_top_inst.cfg_sb_ddr4_mr5[19:0]
16050  *
16051  * Name:DDR4 MR5 content
16052  *
16053  * Description:This register stores the DDR4 MR5 content.
16054  *
16055  * Field Access Macros:
16056  *
16057  */
16058 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5 register field. */
16059 #define ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5_LSB 0
16060 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5 register field. */
16061 #define ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5_MSB 19
16062 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5 register field. */
16063 #define ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5_WIDTH 20
16064 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5 register field value. */
16065 #define ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5_SET_MSK 0x000fffff
16066 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5 register field value. */
16067 #define ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5_CLR_MSK 0xfff00000
16068 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5 register field is UNKNOWN. */
16069 #define ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5_RESET 0x0
16070 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5 field value from a register. */
16071 #define ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5_GET(value) (((value) & 0x000fffff) >> 0)
16072 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5 register field value suitable for setting the register. */
16073 #define ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5_SET(value) (((value) << 0) & 0x000fffff)
16074 
16075 #ifndef __ASSEMBLY__
16076 /*
16077  * WARNING: The C register and register group struct declarations are provided for
16078  * convenience and illustrative purposes. They should, however, be used with
16079  * caution as the C language standard provides no guarantees about the alignment or
16080  * atomicity of device memory accesses. The recommended practice for coding device
16081  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16082  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16083  * alt_write_dword() functions for 64 bit registers.
16084  *
16085  * The struct declaration for register ALT_MPFE_IOHMC_REG_SBCFG8.
16086  */
16087 struct ALT_MPFE_IOHMC_REG_SBCFG8_s
16088 {
16089  volatile uint32_t cfg_sb_ddr4_mr5 : 20; /* ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5 */
16090  uint32_t : 12; /* *UNDEFINED* */
16091 };
16092 
16093 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SBCFG8. */
16094 typedef struct ALT_MPFE_IOHMC_REG_SBCFG8_s ALT_MPFE_IOHMC_REG_SBCFG8_t;
16095 #endif /* __ASSEMBLY__ */
16096 
16097 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG8 register. */
16098 #define ALT_MPFE_IOHMC_REG_SBCFG8_RESET 0x00000000
16099 /* The byte offset of the ALT_MPFE_IOHMC_REG_SBCFG8 register from the beginning of the component. */
16100 #define ALT_MPFE_IOHMC_REG_SBCFG8_OFST 0x11c
16101 
16102 /*
16103  * Register : reg_sbcfg9
16104  *
16105  * Register Layout
16106  *
16107  * Bits | Access | Reset | Description
16108  * :-------|:-------|:--------|:--------------------------------------------------
16109  * [0] | RW | Unknown | ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR
16110  * [31:1] | ??? | Unknown | *UNDEFINED*
16111  *
16112  */
16113 /*
16114  * Field : cfg_ddr4_mps_addrmirror
16115  *
16116  * iohmc_ctrl_mmr_top_inst.cfg_ddr4_mps_addrmirror
16117  *
16118  * Name:DDR4 MPS Address Mirroring
16119  *
16120  * Description:Set to 1 to enable address mirror option during MPS.
16121  *
16122  * Set to 0 to disable address mirror option during MPS.
16123  *
16124  * Field Access Macros:
16125  *
16126  */
16127 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR register field. */
16128 #define ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR_LSB 0
16129 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR register field. */
16130 #define ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR_MSB 0
16131 /* The width in bits of the ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR register field. */
16132 #define ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR_WIDTH 1
16133 /* The mask used to set the ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR register field value. */
16134 #define ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR_SET_MSK 0x00000001
16135 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR register field value. */
16136 #define ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR_CLR_MSK 0xfffffffe
16137 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR register field is UNKNOWN. */
16138 #define ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR_RESET 0x0
16139 /* Extracts the ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR field value from a register. */
16140 #define ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR_GET(value) (((value) & 0x00000001) >> 0)
16141 /* Produces a ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR register field value suitable for setting the register. */
16142 #define ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR_SET(value) (((value) << 0) & 0x00000001)
16143 
16144 #ifndef __ASSEMBLY__
16145 /*
16146  * WARNING: The C register and register group struct declarations are provided for
16147  * convenience and illustrative purposes. They should, however, be used with
16148  * caution as the C language standard provides no guarantees about the alignment or
16149  * atomicity of device memory accesses. The recommended practice for coding device
16150  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16151  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16152  * alt_write_dword() functions for 64 bit registers.
16153  *
16154  * The struct declaration for register ALT_MPFE_IOHMC_REG_SBCFG9.
16155  */
16156 struct ALT_MPFE_IOHMC_REG_SBCFG9_s
16157 {
16158  volatile uint32_t cfg_ddr4_mps_addrmirror : 1; /* ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR */
16159  uint32_t : 31; /* *UNDEFINED* */
16160 };
16161 
16162 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SBCFG9. */
16163 typedef struct ALT_MPFE_IOHMC_REG_SBCFG9_s ALT_MPFE_IOHMC_REG_SBCFG9_t;
16164 #endif /* __ASSEMBLY__ */
16165 
16166 /* The reset value of the ALT_MPFE_IOHMC_REG_SBCFG9 register. */
16167 #define ALT_MPFE_IOHMC_REG_SBCFG9_RESET 0x00000000
16168 /* The byte offset of the ALT_MPFE_IOHMC_REG_SBCFG9 register from the beginning of the component. */
16169 #define ALT_MPFE_IOHMC_REG_SBCFG9_OFST 0x120
16170 
16171 /*
16172  * Register : reg_3ds0
16173  *
16174  * Register Layout
16175  *
16176  * Bits | Access | Reset | Description
16177  * :--------|:-------|:--------|:-----------------------------------------------
16178  * [3:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0
16179  * [7:4] | RW | Unknown | ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1
16180  * [11:8] | RW | Unknown | ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2
16181  * [15:12] | RW | Unknown | ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3
16182  * [17:16] | RW | Unknown | ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH
16183  * [18] | RW | Unknown | ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE
16184  * [31:19] | ??? | Unknown | *UNDEFINED*
16185  *
16186  */
16187 /*
16188  * Field : cfg_3ds_lr_num0
16189  *
16190  * iohmc_ctrl_mmr_top_inst.cfg_3ds_lr_num0[3:0]
16191  *
16192  * Name:Number of 3DS Logical Ranks on Physical Rank 0
16193  *
16194  * Description:4’b0000: Disable 3DS Logic
16195  *
16196  * 4’b0001: 1H (engineering feature i.e. 3DS logic running in non-3DS mode)
16197  *
16198  * 4’b0010: 2H
16199  *
16200  * 4’b0100: 4H
16201  *
16202  * 4’b1000: 8H (engineering feature)
16203  *
16204  * All other values are reserved.
16205  *
16206  * Field Access Macros:
16207  *
16208  */
16209 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0 register field. */
16210 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0_LSB 0
16211 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0 register field. */
16212 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0_MSB 3
16213 /* The width in bits of the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0 register field. */
16214 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0_WIDTH 4
16215 /* The mask used to set the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0 register field value. */
16216 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0_SET_MSK 0x0000000f
16217 /* The mask used to clear the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0 register field value. */
16218 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0_CLR_MSK 0xfffffff0
16219 /* The reset value of the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0 register field is UNKNOWN. */
16220 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0_RESET 0x0
16221 /* Extracts the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0 field value from a register. */
16222 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0_GET(value) (((value) & 0x0000000f) >> 0)
16223 /* Produces a ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0 register field value suitable for setting the register. */
16224 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0_SET(value) (((value) << 0) & 0x0000000f)
16225 
16226 /*
16227  * Field : cfg_3ds_lr_num1
16228  *
16229  * iohmc_ctrl_mmr_top_inst.cfg_3ds_lr_num1[3:0]
16230  *
16231  * Name:Number of 3DS Logical Ranks on Physical Rank 1
16232  *
16233  * Description:4’b0000: Disable 3DS Logic
16234  *
16235  * 4’b0001: 1H (engineering feature i.e. 3DS logic running in non-3DS mode)
16236  *
16237  * 4’b0010: 2H
16238  *
16239  * 4’b0100: 4H
16240  *
16241  * 4’b1000: 8H (engineering feature)
16242  *
16243  * All other values are reserved.
16244  *
16245  * Field Access Macros:
16246  *
16247  */
16248 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1 register field. */
16249 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1_LSB 4
16250 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1 register field. */
16251 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1_MSB 7
16252 /* The width in bits of the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1 register field. */
16253 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1_WIDTH 4
16254 /* The mask used to set the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1 register field value. */
16255 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1_SET_MSK 0x000000f0
16256 /* The mask used to clear the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1 register field value. */
16257 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1_CLR_MSK 0xffffff0f
16258 /* The reset value of the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1 register field is UNKNOWN. */
16259 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1_RESET 0x0
16260 /* Extracts the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1 field value from a register. */
16261 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1_GET(value) (((value) & 0x000000f0) >> 4)
16262 /* Produces a ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1 register field value suitable for setting the register. */
16263 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1_SET(value) (((value) << 4) & 0x000000f0)
16264 
16265 /*
16266  * Field : cfg_3ds_lr_num2
16267  *
16268  * iohmc_ctrl_mmr_top_inst.cfg_3ds_lr_num2[3:0]
16269  *
16270  * Name:Number of 3DS Logical Ranks on Physical Rank 2
16271  *
16272  * Description:4’b0000: Disable 3DS Logic
16273  *
16274  * 4’b0001: 1H (engineering feature i.e. 3DS logic running in non-3DS mode)
16275  *
16276  * 4’b0010: 2H
16277  *
16278  * 4’b0100: 4H
16279  *
16280  * 4’b1000: 8H (engineering feature)
16281  *
16282  * All other values are reserved.
16283  *
16284  * Field Access Macros:
16285  *
16286  */
16287 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2 register field. */
16288 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2_LSB 8
16289 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2 register field. */
16290 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2_MSB 11
16291 /* The width in bits of the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2 register field. */
16292 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2_WIDTH 4
16293 /* The mask used to set the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2 register field value. */
16294 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2_SET_MSK 0x00000f00
16295 /* The mask used to clear the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2 register field value. */
16296 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2_CLR_MSK 0xfffff0ff
16297 /* The reset value of the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2 register field is UNKNOWN. */
16298 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2_RESET 0x0
16299 /* Extracts the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2 field value from a register. */
16300 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2_GET(value) (((value) & 0x00000f00) >> 8)
16301 /* Produces a ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2 register field value suitable for setting the register. */
16302 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2_SET(value) (((value) << 8) & 0x00000f00)
16303 
16304 /*
16305  * Field : cfg_3ds_lr_num3
16306  *
16307  * iohmc_ctrl_mmr_top_inst.cfg_3ds_lr_num3[3:0]
16308  *
16309  * Name:Number of 3DS Logical Ranks on Physical Rank 3
16310  *
16311  * Description:4’b0000: Disable 3DS Logic
16312  *
16313  * 4’b0001: 1H (engineering feature i.e. 3DS logic running in non-3DS mode)
16314  *
16315  * 4’b0010: 2H
16316  *
16317  * 4’b0100: 4H
16318  *
16319  * 4’b1000: 8H (engineering feature)
16320  *
16321  * All other values are reserved.
16322  *
16323  * Field Access Macros:
16324  *
16325  */
16326 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3 register field. */
16327 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3_LSB 12
16328 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3 register field. */
16329 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3_MSB 15
16330 /* The width in bits of the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3 register field. */
16331 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3_WIDTH 4
16332 /* The mask used to set the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3 register field value. */
16333 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3_SET_MSK 0x0000f000
16334 /* The mask used to clear the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3 register field value. */
16335 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3_CLR_MSK 0xffff0fff
16336 /* The reset value of the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3 register field is UNKNOWN. */
16337 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3_RESET 0x0
16338 /* Extracts the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3 field value from a register. */
16339 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3_GET(value) (((value) & 0x0000f000) >> 12)
16340 /* Produces a ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3 register field value suitable for setting the register. */
16341 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3_SET(value) (((value) << 12) & 0x0000f000)
16342 
16343 /*
16344  * Field : cfg_cid_addr_width
16345  *
16346  * iohmc_ctrl_mmr_top_inst.cfg_cid_addr_width[1:0]
16347  *
16348  * Name:3DS Chip ID Address Width
16349  *
16350  * Description:To configure the width of the 3DS Chip ID signal, range 0-3.
16351  *
16352  * Field Access Macros:
16353  *
16354  */
16355 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH register field. */
16356 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH_LSB 16
16357 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH register field. */
16358 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH_MSB 17
16359 /* The width in bits of the ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH register field. */
16360 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH_WIDTH 2
16361 /* The mask used to set the ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH register field value. */
16362 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH_SET_MSK 0x00030000
16363 /* The mask used to clear the ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH register field value. */
16364 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH_CLR_MSK 0xfffcffff
16365 /* The reset value of the ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH register field is UNKNOWN. */
16366 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH_RESET 0x0
16367 /* Extracts the ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH field value from a register. */
16368 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH_GET(value) (((value) & 0x00030000) >> 16)
16369 /* Produces a ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH register field value suitable for setting the register. */
16370 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH_SET(value) (((value) << 16) & 0x00030000)
16371 
16372 /*
16373  * Field : cfg_3ds_pr_stag_enable
16374  *
16375  * iohmc_ctrl_mmr_top_inst.cfg_3ds_pr_stag_enable
16376  *
16377  * Name:Enable Physical Rank Staggering to 3DS devices
16378  *
16379  * Description:1’b0 – Disable 3DS Physical Rank Refresh Staggering (Default)
16380  *
16381  * 1’b1 – Enable 3DS Physical Rank Refresh Staggering.
16382  *
16383  * Note: This is the global enable bit. There is no per rank option.
16384  *
16385  * Field Access Macros:
16386  *
16387  */
16388 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE register field. */
16389 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE_LSB 18
16390 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE register field. */
16391 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE_MSB 18
16392 /* The width in bits of the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE register field. */
16393 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE_WIDTH 1
16394 /* The mask used to set the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE register field value. */
16395 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE_SET_MSK 0x00040000
16396 /* The mask used to clear the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE register field value. */
16397 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE_CLR_MSK 0xfffbffff
16398 /* The reset value of the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE register field is UNKNOWN. */
16399 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE_RESET 0x0
16400 /* Extracts the ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE field value from a register. */
16401 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE_GET(value) (((value) & 0x00040000) >> 18)
16402 /* Produces a ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE register field value suitable for setting the register. */
16403 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE_SET(value) (((value) << 18) & 0x00040000)
16404 
16405 #ifndef __ASSEMBLY__
16406 /*
16407  * WARNING: The C register and register group struct declarations are provided for
16408  * convenience and illustrative purposes. They should, however, be used with
16409  * caution as the C language standard provides no guarantees about the alignment or
16410  * atomicity of device memory accesses. The recommended practice for coding device
16411  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16412  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16413  * alt_write_dword() functions for 64 bit registers.
16414  *
16415  * The struct declaration for register ALT_MPFE_IOHMC_REG_3DS0.
16416  */
16417 struct ALT_MPFE_IOHMC_REG_3DS0_s
16418 {
16419  volatile uint32_t cfg_3ds_lr_num0 : 4; /* ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0 */
16420  volatile uint32_t cfg_3ds_lr_num1 : 4; /* ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1 */
16421  volatile uint32_t cfg_3ds_lr_num2 : 4; /* ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2 */
16422  volatile uint32_t cfg_3ds_lr_num3 : 4; /* ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3 */
16423  volatile uint32_t cfg_cid_addr_width : 2; /* ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH */
16424  volatile uint32_t cfg_3ds_pr_stag_enable : 1; /* ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE */
16425  uint32_t : 13; /* *UNDEFINED* */
16426 };
16427 
16428 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_3DS0. */
16429 typedef struct ALT_MPFE_IOHMC_REG_3DS0_s ALT_MPFE_IOHMC_REG_3DS0_t;
16430 #endif /* __ASSEMBLY__ */
16431 
16432 /* The reset value of the ALT_MPFE_IOHMC_REG_3DS0 register. */
16433 #define ALT_MPFE_IOHMC_REG_3DS0_RESET 0x00000000
16434 /* The byte offset of the ALT_MPFE_IOHMC_REG_3DS0 register from the beginning of the component. */
16435 #define ALT_MPFE_IOHMC_REG_3DS0_OFST 0x124
16436 
16437 /*
16438  * Register : reg_3ds1
16439  *
16440  * Register Layout
16441  *
16442  * Bits | Access | Reset | Description
16443  * :-------|:-------|:--------|:--------------------------------------------
16444  * [6:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR
16445  * [31:7] | ??? | Unknown | *UNDEFINED*
16446  *
16447  */
16448 /*
16449  * Field : cfg_3ds_ref2ref_dlr
16450  *
16451  * iohmc_ctrl_mmr_top_inst.cfg_3ds_ref2ref_dlr[6:0]
16452  *
16453  * Name:Refresh-to-refresh timing (Between Different Logical Ranks)
16454  *
16455  * Description:Timing parameter for refreshes between different logical ranks i.e.
16456  * tRFC (DLR).
16457  *
16458  * Field Access Macros:
16459  *
16460  */
16461 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR register field. */
16462 #define ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR_LSB 0
16463 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR register field. */
16464 #define ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR_MSB 6
16465 /* The width in bits of the ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR register field. */
16466 #define ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR_WIDTH 7
16467 /* The mask used to set the ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR register field value. */
16468 #define ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR_SET_MSK 0x0000007f
16469 /* The mask used to clear the ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR register field value. */
16470 #define ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR_CLR_MSK 0xffffff80
16471 /* The reset value of the ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR register field is UNKNOWN. */
16472 #define ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR_RESET 0x0
16473 /* Extracts the ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR field value from a register. */
16474 #define ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR_GET(value) (((value) & 0x0000007f) >> 0)
16475 /* Produces a ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR register field value suitable for setting the register. */
16476 #define ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR_SET(value) (((value) << 0) & 0x0000007f)
16477 
16478 #ifndef __ASSEMBLY__
16479 /*
16480  * WARNING: The C register and register group struct declarations are provided for
16481  * convenience and illustrative purposes. They should, however, be used with
16482  * caution as the C language standard provides no guarantees about the alignment or
16483  * atomicity of device memory accesses. The recommended practice for coding device
16484  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16485  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16486  * alt_write_dword() functions for 64 bit registers.
16487  *
16488  * The struct declaration for register ALT_MPFE_IOHMC_REG_3DS1.
16489  */
16490 struct ALT_MPFE_IOHMC_REG_3DS1_s
16491 {
16492  volatile uint32_t cfg_3ds_ref2ref_dlr : 7; /* ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR */
16493  uint32_t : 25; /* *UNDEFINED* */
16494 };
16495 
16496 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_3DS1. */
16497 typedef struct ALT_MPFE_IOHMC_REG_3DS1_s ALT_MPFE_IOHMC_REG_3DS1_t;
16498 #endif /* __ASSEMBLY__ */
16499 
16500 /* The reset value of the ALT_MPFE_IOHMC_REG_3DS1 register. */
16501 #define ALT_MPFE_IOHMC_REG_3DS1_RESET 0x00000000
16502 /* The byte offset of the ALT_MPFE_IOHMC_REG_3DS1 register from the beginning of the component. */
16503 #define ALT_MPFE_IOHMC_REG_3DS1_OFST 0x128
16504 
16505 /*
16506  * Register : reg_3ds2
16507  *
16508  * Register Layout
16509  *
16510  * Bits | Access | Reset | Description
16511  * :-------|:-------|:--------|:------------------------------------
16512  * [8:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID
16513  * [31:9] | ??? | Unknown | *UNDEFINED*
16514  *
16515  */
16516 /*
16517  * Field : cfg_chip_id
16518  *
16519  * iohmc_ctrl_mmr_top_inst.cfg_chip_id[8:0]
16520  *
16521  * Name:3DS Chip ID Mapping
16522  *
16523  * Description:Configure this register to change 3DS pin mapping
16524  *
16525  * [8:6] – CID[2] map
16526  *
16527  * [5:3] – CID[1] map
16528  *
16529  * [2:0] – CID[0] map
16530  *
16531  * where
16532  *
16533  * [8] – Map CID[2] to default CID[2] pin
16534  *
16535  * [7] – Map CID[2] to default CID[1] pin
16536  *
16537  * [6] – Map CID[2] to default CID[0] pin
16538  *
16539  * [5] – Map CID[1] to default CID[2] pin
16540  *
16541  * [4] – Map CID[1] to default CID[1] pin
16542  *
16543  * [3] – Map CID[1] to default CID[0] pin
16544  *
16545  * [2] – Map CID[0] to default CID[2] pin
16546  *
16547  * [1] – Map CID[0] to default CID[1] pin
16548  *
16549  * [0] – Map CID[0] to default CID[0] pin
16550  *
16551  * Field Access Macros:
16552  *
16553  */
16554 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID register field. */
16555 #define ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID_LSB 0
16556 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID register field. */
16557 #define ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID_MSB 8
16558 /* The width in bits of the ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID register field. */
16559 #define ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID_WIDTH 9
16560 /* The mask used to set the ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID register field value. */
16561 #define ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID_SET_MSK 0x000001ff
16562 /* The mask used to clear the ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID register field value. */
16563 #define ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID_CLR_MSK 0xfffffe00
16564 /* The reset value of the ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID register field is UNKNOWN. */
16565 #define ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID_RESET 0x0
16566 /* Extracts the ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID field value from a register. */
16567 #define ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID_GET(value) (((value) & 0x000001ff) >> 0)
16568 /* Produces a ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID register field value suitable for setting the register. */
16569 #define ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID_SET(value) (((value) << 0) & 0x000001ff)
16570 
16571 #ifndef __ASSEMBLY__
16572 /*
16573  * WARNING: The C register and register group struct declarations are provided for
16574  * convenience and illustrative purposes. They should, however, be used with
16575  * caution as the C language standard provides no guarantees about the alignment or
16576  * atomicity of device memory accesses. The recommended practice for coding device
16577  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16578  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16579  * alt_write_dword() functions for 64 bit registers.
16580  *
16581  * The struct declaration for register ALT_MPFE_IOHMC_REG_3DS2.
16582  */
16583 struct ALT_MPFE_IOHMC_REG_3DS2_s
16584 {
16585  volatile uint32_t cfg_chip_id : 9; /* ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID */
16586  uint32_t : 23; /* *UNDEFINED* */
16587 };
16588 
16589 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_3DS2. */
16590 typedef struct ALT_MPFE_IOHMC_REG_3DS2_s ALT_MPFE_IOHMC_REG_3DS2_t;
16591 #endif /* __ASSEMBLY__ */
16592 
16593 /* The reset value of the ALT_MPFE_IOHMC_REG_3DS2 register. */
16594 #define ALT_MPFE_IOHMC_REG_3DS2_RESET 0x00000000
16595 /* The byte offset of the ALT_MPFE_IOHMC_REG_3DS2 register from the beginning of the component. */
16596 #define ALT_MPFE_IOHMC_REG_3DS2_OFST 0x12c
16597 
16598 /*
16599  * Register : reg_pipeline0
16600  *
16601  * Register Layout
16602  *
16603  * Bits | Access | Reset | Description
16604  * :-------|:-------|:--------|:------------------------------------------------------
16605  * [0] | RW | Unknown | ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA
16606  * [1] | RW | Unknown | ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA
16607  * [2] | RW | Unknown | ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA
16608  * [3] | RW | Unknown | ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA
16609  * [4] | ??? | Unknown | *UNDEFINED*
16610  * [5] | RW | Unknown | ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA
16611  * [6] | RW | Unknown | ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA
16612  * [7] | RW | Unknown | ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN
16613  * [31:8] | ??? | Unknown | *UNDEFINED*
16614  *
16615  */
16616 /*
16617  * Field : cfg_arbiter_reg_ena
16618  *
16619  * iohmc_ctrl_mmr_top_inst.cfg_arbiter_reg_ena
16620  *
16621  * Name:Reserved
16622  *
16623  * Description:TBD
16624  *
16625  * Field Access Macros:
16626  *
16627  */
16628 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA register field. */
16629 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA_LSB 0
16630 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA register field. */
16631 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA_MSB 0
16632 /* The width in bits of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA register field. */
16633 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA_WIDTH 1
16634 /* The mask used to set the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA register field value. */
16635 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA_SET_MSK 0x00000001
16636 /* The mask used to clear the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA register field value. */
16637 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA_CLR_MSK 0xfffffffe
16638 /* The reset value of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA register field is UNKNOWN. */
16639 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA_RESET 0x0
16640 /* Extracts the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA field value from a register. */
16641 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA_GET(value) (((value) & 0x00000001) >> 0)
16642 /* Produces a ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA register field value suitable for setting the register. */
16643 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA_SET(value) (((value) << 0) & 0x00000001)
16644 
16645 /*
16646  * Field : cfg_wb_ptr_reg_ena
16647  *
16648  * iohmc_ctrl_mmr_top_inst.cfg_wb_ptr_reg_ena
16649  *
16650  * Name:Bypass Write Buffer (WB) Retire Pointer
16651  *
16652  * Description:1’b0 – Live WB Retire Pointer path (Default)
16653  *
16654  * 1’b1 – Flop WB Retire Pointer path
16655  *
16656  * Field Access Macros:
16657  *
16658  */
16659 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA register field. */
16660 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA_LSB 1
16661 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA register field. */
16662 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA_MSB 1
16663 /* The width in bits of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA register field. */
16664 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA_WIDTH 1
16665 /* The mask used to set the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA register field value. */
16666 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA_SET_MSK 0x00000002
16667 /* The mask used to clear the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA register field value. */
16668 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA_CLR_MSK 0xfffffffd
16669 /* The reset value of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA register field is UNKNOWN. */
16670 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA_RESET 0x0
16671 /* Extracts the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA field value from a register. */
16672 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA_GET(value) (((value) & 0x00000002) >> 1)
16673 /* Produces a ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA register field value suitable for setting the register. */
16674 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA_SET(value) (((value) << 1) & 0x00000002)
16675 
16676 /*
16677  * Field : cfg_rb_ptr_reg_ena
16678  *
16679  * iohmc_ctrl_mmr_top_inst.cfg_rb_ptr_reg_ena
16680  *
16681  * Name:Bypass Read Buffer (RB) Retire Pointer
16682  *
16683  * Description:1’b0 – Live RB Retire Pointer path (Default)
16684  *
16685  * 1’b0 – Flop RB Retire Pointer path
16686  *
16687  * Field Access Macros:
16688  *
16689  */
16690 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA register field. */
16691 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA_LSB 2
16692 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA register field. */
16693 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA_MSB 2
16694 /* The width in bits of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA register field. */
16695 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA_WIDTH 1
16696 /* The mask used to set the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA register field value. */
16697 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA_SET_MSK 0x00000004
16698 /* The mask used to clear the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA register field value. */
16699 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA_CLR_MSK 0xfffffffb
16700 /* The reset value of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA register field is UNKNOWN. */
16701 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA_RESET 0x0
16702 /* Extracts the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA field value from a register. */
16703 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA_GET(value) (((value) & 0x00000004) >> 2)
16704 /* Produces a ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA register field value suitable for setting the register. */
16705 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA_SET(value) (((value) << 2) & 0x00000004)
16706 
16707 /*
16708  * Field : cfg_ctl2dbc_reg_ena
16709  *
16710  * iohmc_ctrl_mmr_top_inst.cfg_ctl2dbc_reg_ena
16711  *
16712  * Name:Reserved
16713  *
16714  * Description:TBD
16715  *
16716  * Field Access Macros:
16717  *
16718  */
16719 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA register field. */
16720 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA_LSB 3
16721 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA register field. */
16722 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA_MSB 3
16723 /* The width in bits of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA register field. */
16724 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA_WIDTH 1
16725 /* The mask used to set the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA register field value. */
16726 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA_SET_MSK 0x00000008
16727 /* The mask used to clear the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA register field value. */
16728 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA_CLR_MSK 0xfffffff7
16729 /* The reset value of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA register field is UNKNOWN. */
16730 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA_RESET 0x0
16731 /* Extracts the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA field value from a register. */
16732 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA_GET(value) (((value) & 0x00000008) >> 3)
16733 /* Produces a ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA register field value suitable for setting the register. */
16734 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA_SET(value) (((value) << 3) & 0x00000008)
16735 
16736 /*
16737  * Field : cfg_ctl2dbc_tile_reg_ena
16738  *
16739  * iohmc_ctrl_mmr_top_inst.cfg_ctl2dbc_tile_reg_ena
16740  *
16741  * Name:Reserved
16742  *
16743  * Description:TBD
16744  *
16745  * Field Access Macros:
16746  *
16747  */
16748 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA register field. */
16749 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA_LSB 5
16750 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA register field. */
16751 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA_MSB 5
16752 /* The width in bits of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA register field. */
16753 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA_WIDTH 1
16754 /* The mask used to set the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA register field value. */
16755 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA_SET_MSK 0x00000020
16756 /* The mask used to clear the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA register field value. */
16757 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA_CLR_MSK 0xffffffdf
16758 /* The reset value of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA register field is UNKNOWN. */
16759 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA_RESET 0x0
16760 /* Extracts the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA field value from a register. */
16761 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA_GET(value) (((value) & 0x00000020) >> 5)
16762 /* Produces a ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA register field value suitable for setting the register. */
16763 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA_SET(value) (((value) << 5) & 0x00000020)
16764 
16765 /*
16766  * Field : cfg_ac_tile_reg_ena
16767  *
16768  * iohmc_ctrl_mmr_top_inst.cfg_ac_tile_reg_ena
16769  *
16770  * Name:AC Pipe Stage Enable (Tile)
16771  *
16772  * Description:Set to 1 to enable address/command tile pipe stage.
16773  *
16774  * Set to 0 to disable address/command tile pipe stage.
16775  *
16776  * Field Access Macros:
16777  *
16778  */
16779 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA register field. */
16780 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA_LSB 6
16781 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA register field. */
16782 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA_MSB 6
16783 /* The width in bits of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA register field. */
16784 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA_WIDTH 1
16785 /* The mask used to set the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA register field value. */
16786 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA_SET_MSK 0x00000040
16787 /* The mask used to clear the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA register field value. */
16788 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA_CLR_MSK 0xffffffbf
16789 /* The reset value of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA register field is UNKNOWN. */
16790 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA_RESET 0x0
16791 /* Extracts the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA field value from a register. */
16792 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA_GET(value) (((value) & 0x00000040) >> 6)
16793 /* Produces a ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA register field value suitable for setting the register. */
16794 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA_SET(value) (((value) << 6) & 0x00000040)
16795 
16796 /*
16797  * Field : cfg_cmd_fifo_pipeline_en
16798  *
16799  * iohmc_ctrl_mmr_top_inst.cfg_cmd_fifo_reserve_en
16800  *
16801  * Name:Avalon Almost-Ready Enable
16802  *
16803  * Description:Enables Almost-Ready behavior in input command FIFO.
16804  *
16805  * Field Access Macros:
16806  *
16807  */
16808 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN register field. */
16809 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN_LSB 7
16810 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN register field. */
16811 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN_MSB 7
16812 /* The width in bits of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN register field. */
16813 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN_WIDTH 1
16814 /* The mask used to set the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN register field value. */
16815 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN_SET_MSK 0x00000080
16816 /* The mask used to clear the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN register field value. */
16817 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN_CLR_MSK 0xffffff7f
16818 /* The reset value of the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN register field is UNKNOWN. */
16819 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN_RESET 0x0
16820 /* Extracts the ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN field value from a register. */
16821 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN_GET(value) (((value) & 0x00000080) >> 7)
16822 /* Produces a ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN register field value suitable for setting the register. */
16823 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN_SET(value) (((value) << 7) & 0x00000080)
16824 
16825 #ifndef __ASSEMBLY__
16826 /*
16827  * WARNING: The C register and register group struct declarations are provided for
16828  * convenience and illustrative purposes. They should, however, be used with
16829  * caution as the C language standard provides no guarantees about the alignment or
16830  * atomicity of device memory accesses. The recommended practice for coding device
16831  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16832  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16833  * alt_write_dword() functions for 64 bit registers.
16834  *
16835  * The struct declaration for register ALT_MPFE_IOHMC_REG_PIPELINE0.
16836  */
16837 struct ALT_MPFE_IOHMC_REG_PIPELINE0_s
16838 {
16839  volatile uint32_t cfg_arbiter_reg_ena : 1; /* ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA */
16840  volatile uint32_t cfg_wb_ptr_reg_ena : 1; /* ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA */
16841  volatile uint32_t cfg_rb_ptr_reg_ena : 1; /* ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA */
16842  volatile uint32_t cfg_ctl2dbc_reg_ena : 1; /* ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA */
16843  uint32_t : 1; /* *UNDEFINED* */
16844  volatile uint32_t cfg_ctl2dbc_tile_reg_ena : 1; /* ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA */
16845  volatile uint32_t cfg_ac_tile_reg_ena : 1; /* ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA */
16846  volatile uint32_t cfg_cmd_fifo_pipeline_en : 1; /* ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN */
16847  uint32_t : 24; /* *UNDEFINED* */
16848 };
16849 
16850 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_PIPELINE0. */
16851 typedef struct ALT_MPFE_IOHMC_REG_PIPELINE0_s ALT_MPFE_IOHMC_REG_PIPELINE0_t;
16852 #endif /* __ASSEMBLY__ */
16853 
16854 /* The reset value of the ALT_MPFE_IOHMC_REG_PIPELINE0 register. */
16855 #define ALT_MPFE_IOHMC_REG_PIPELINE0_RESET 0x00000000
16856 /* The byte offset of the ALT_MPFE_IOHMC_REG_PIPELINE0 register from the beginning of the component. */
16857 #define ALT_MPFE_IOHMC_REG_PIPELINE0_OFST 0x130
16858 
16859 /*
16860  * Register : reg_memclockgating0
16861  *
16862  * Register Layout
16863  *
16864  * Bits | Access | Reset | Description
16865  * :-------|:-------|:--------|:----------------------------------------------------------
16866  * [7:0] | RW | Unknown | ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING
16867  * [31:8] | ??? | Unknown | *UNDEFINED*
16868  *
16869  */
16870 /*
16871  * Field : cfg_memclkgate_setting
16872  *
16873  * iohmc_ctrl_mmr_top_inst.cfg_memclkgate_setting
16874  *
16875  * Name:Memory Clock Control Setting
16876  *
16877  * Description:Set memory clocks behavior for Hard Memory Controller
16878  *
16879  * Each 2-bit field controls a specific memory clock pair.
16880  *
16881  * [7:6] – memory clock pair #3
16882  *
16883  * [5:4] – memory clock pair #2
16884  *
16885  * [3:2] – memory clock pair #1
16886  *
16887  * [1:0] – memory clock pair #0
16888  *
16889  * Memory clock behavior is controlled as follows:
16890  *
16891  * 2’b11 – Reserved
16892  *
16893  * 2’b10 – clock always enabled
16894  *
16895  * 2’b11 – clock disabled in low power states
16896  *
16897  * 2’b00 – clock always disabled
16898  *
16899  * Field Access Macros:
16900  *
16901  */
16902 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING register field. */
16903 #define ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING_LSB 0
16904 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING register field. */
16905 #define ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING_MSB 7
16906 /* The width in bits of the ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING register field. */
16907 #define ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING_WIDTH 8
16908 /* The mask used to set the ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING register field value. */
16909 #define ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING_SET_MSK 0x000000ff
16910 /* The mask used to clear the ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING register field value. */
16911 #define ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING_CLR_MSK 0xffffff00
16912 /* The reset value of the ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING register field is UNKNOWN. */
16913 #define ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING_RESET 0x0
16914 /* Extracts the ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING field value from a register. */
16915 #define ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING_GET(value) (((value) & 0x000000ff) >> 0)
16916 /* Produces a ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING register field value suitable for setting the register. */
16917 #define ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING_SET(value) (((value) << 0) & 0x000000ff)
16918 
16919 #ifndef __ASSEMBLY__
16920 /*
16921  * WARNING: The C register and register group struct declarations are provided for
16922  * convenience and illustrative purposes. They should, however, be used with
16923  * caution as the C language standard provides no guarantees about the alignment or
16924  * atomicity of device memory accesses. The recommended practice for coding device
16925  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16926  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16927  * alt_write_dword() functions for 64 bit registers.
16928  *
16929  * The struct declaration for register ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0.
16930  */
16931 struct ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_s
16932 {
16933  volatile uint32_t cfg_memclkgate_setting : 8; /* ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING */
16934  uint32_t : 24; /* *UNDEFINED* */
16935 };
16936 
16937 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0. */
16938 typedef struct ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_s ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_t;
16939 #endif /* __ASSEMBLY__ */
16940 
16941 /* The reset value of the ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0 register. */
16942 #define ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_RESET 0x00000000
16943 /* The byte offset of the ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0 register from the beginning of the component. */
16944 #define ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_OFST 0x138
16945 
16946 /*
16947  * Register : reg_sideband16
16948  *
16949  * Register Layout
16950  *
16951  * Bits | Access | Reset | Description
16952  * :-------|:-------|:--------|:--------------------------------------------------
16953  * [31:0] | R | Unknown | ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK
16954  *
16955  */
16956 /*
16957  * Field : mmr_3ds_refresh_ack
16958  *
16959  * iohmc_ctrl_mmr_top_inst.mmr_3ds_refresh_ack[31:0]
16960  *
16961  * Name:3DS Refresh Acknowledge
16962  *
16963  * Description:Acknowledge to indicate 3DS refresh is done.
16964  *
16965  * Bit0: PR0, LR0
16966  *
16967  * Bit1: PR0, LR1
16968  *
16969  * Bit2: PR0, LR2
16970  *
16971  * Bit3: PR0, LR3
16972  *
16973  * Bits4-7: Reserved
16974  *
16975  * Bit8: PR1, LR0
16976  *
16977  * Bit9: PR1, LR1
16978  *
16979  * Bit10: PR1, LR2
16980  *
16981  * Bit11: PR1, LR3
16982  *
16983  * Bits12-15: Reserved
16984  *
16985  * Bit16: PR2, LR0
16986  *
16987  * Bit17: PR2, LR1
16988  *
16989  * Bit18: PR2, LR2
16990  *
16991  * Bit19: PR2, LR3
16992  *
16993  * Bits20-23: Reserved
16994  *
16995  * Bit24: PR3, LR0
16996  *
16997  * Bit25: PR3, LR1
16998  *
16999  * Bit26: PR3, LR2
17000  *
17001  * Bit27: PR3, LR3
17002  *
17003  * Bits 28-32: Reserved
17004  *
17005  * Note1: PR=Physical Rank
17006  *
17007  * Note2: LR=Logical Rank
17008  *
17009  * Field Access Macros:
17010  *
17011  */
17012 /* The Least Significant Bit (LSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK register field. */
17013 #define ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK_LSB 0
17014 /* The Most Significant Bit (MSB) position of the ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK register field. */
17015 #define ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK_MSB 31
17016 /* The width in bits of the ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK register field. */
17017 #define ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK_WIDTH 32
17018 /* The mask used to set the ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK register field value. */
17019 #define ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK_SET_MSK 0xffffffff
17020 /* The mask used to clear the ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK register field value. */
17021 #define ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK_CLR_MSK 0x00000000
17022 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK register field is UNKNOWN. */
17023 #define ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK_RESET 0x0
17024 /* Extracts the ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK field value from a register. */
17025 #define ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK_GET(value) (((value) & 0xffffffff) >> 0)
17026 /* Produces a ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK register field value suitable for setting the register. */
17027 #define ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK_SET(value) (((value) << 0) & 0xffffffff)
17028 
17029 #ifndef __ASSEMBLY__
17030 /*
17031  * WARNING: The C register and register group struct declarations are provided for
17032  * convenience and illustrative purposes. They should, however, be used with
17033  * caution as the C language standard provides no guarantees about the alignment or
17034  * atomicity of device memory accesses. The recommended practice for coding device
17035  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17036  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17037  * alt_write_dword() functions for 64 bit registers.
17038  *
17039  * The struct declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND16.
17040  */
17041 struct ALT_MPFE_IOHMC_REG_SIDEBAND16_s
17042 {
17043  const volatile uint32_t mmr_3ds_refresh_ack : 32; /* ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK */
17044 };
17045 
17046 /* The typedef declaration for register ALT_MPFE_IOHMC_REG_SIDEBAND16. */
17047 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND16_s ALT_MPFE_IOHMC_REG_SIDEBAND16_t;
17048 #endif /* __ASSEMBLY__ */
17049 
17050 /* The reset value of the ALT_MPFE_IOHMC_REG_SIDEBAND16 register. */
17051 #define ALT_MPFE_IOHMC_REG_SIDEBAND16_RESET 0x00000000
17052 /* The byte offset of the ALT_MPFE_IOHMC_REG_SIDEBAND16 register from the beginning of the component. */
17053 #define ALT_MPFE_IOHMC_REG_SIDEBAND16_OFST 0x13c
17054 
17055 #ifndef __ASSEMBLY__
17056 /*
17057  * WARNING: The C register and register group struct declarations are provided for
17058  * convenience and illustrative purposes. They should, however, be used with
17059  * caution as the C language standard provides no guarantees about the alignment or
17060  * atomicity of device memory accesses. The recommended practice for coding device
17061  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17062  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17063  * alt_write_dword() functions for 64 bit registers.
17064  *
17065  * The struct declaration for register group ALT_MPFE_IOHMC.
17066  */
17067 struct ALT_MPFE_IOHMC_s
17068 {
17069  volatile ALT_MPFE_IOHMC_REG_DBGCFG0_t reg_dbgcfg0; /* ALT_MPFE_IOHMC_REG_DBGCFG0 */
17070  volatile ALT_MPFE_IOHMC_REG_DBGCFG1_t reg_dbgcfg1; /* ALT_MPFE_IOHMC_REG_DBGCFG1 */
17071  volatile ALT_MPFE_IOHMC_REG_DBGCFG2_t reg_dbgcfg2; /* ALT_MPFE_IOHMC_REG_DBGCFG2 */
17072  volatile ALT_MPFE_IOHMC_REG_DBGCFG3_t reg_dbgcfg3; /* ALT_MPFE_IOHMC_REG_DBGCFG3 */
17073  volatile ALT_MPFE_IOHMC_REG_DBGCFG4_t reg_dbgcfg4; /* ALT_MPFE_IOHMC_REG_DBGCFG4 */
17074  volatile ALT_MPFE_IOHMC_REG_DBGCFG5_t reg_dbgcfg5; /* ALT_MPFE_IOHMC_REG_DBGCFG5 */
17075  volatile ALT_MPFE_IOHMC_REG_DBGCFG6_t reg_dbgcfg6; /* ALT_MPFE_IOHMC_REG_DBGCFG6 */
17076  volatile ALT_MPFE_IOHMC_REG_RESERVE0_t reg_reserve0; /* ALT_MPFE_IOHMC_REG_RESERVE0 */
17077  volatile ALT_MPFE_IOHMC_REG_RESERVE1_t reg_reserve1; /* ALT_MPFE_IOHMC_REG_RESERVE1 */
17078  volatile ALT_MPFE_IOHMC_REG_RESERVE2_t reg_reserve2; /* ALT_MPFE_IOHMC_REG_RESERVE2 */
17079  volatile ALT_MPFE_IOHMC_REG_CTRLCFG0_t reg_ctrlcfg0; /* ALT_MPFE_IOHMC_REG_CTRLCFG0 */
17080  volatile ALT_MPFE_IOHMC_REG_CTRLCFG1_t reg_ctrlcfg1; /* ALT_MPFE_IOHMC_REG_CTRLCFG1 */
17081  volatile ALT_MPFE_IOHMC_REG_CTRLCFG2_t reg_ctrlcfg2; /* ALT_MPFE_IOHMC_REG_CTRLCFG2 */
17082  volatile ALT_MPFE_IOHMC_REG_CTRLCFG3_t reg_ctrlcfg3; /* ALT_MPFE_IOHMC_REG_CTRLCFG3 */
17083  volatile ALT_MPFE_IOHMC_REG_CTRLCFG4_t reg_ctrlcfg4; /* ALT_MPFE_IOHMC_REG_CTRLCFG4 */
17084  volatile ALT_MPFE_IOHMC_REG_CTRLCFG5_t reg_ctrlcfg5; /* ALT_MPFE_IOHMC_REG_CTRLCFG5 */
17085  volatile ALT_MPFE_IOHMC_REG_CTRLCFG6_t reg_ctrlcfg6; /* ALT_MPFE_IOHMC_REG_CTRLCFG6 */
17086  volatile ALT_MPFE_IOHMC_REG_CTRLCFG7_t reg_ctrlcfg7; /* ALT_MPFE_IOHMC_REG_CTRLCFG7 */
17087  volatile ALT_MPFE_IOHMC_REG_CTRLCFG8_t reg_ctrlcfg8; /* ALT_MPFE_IOHMC_REG_CTRLCFG8 */
17088  volatile ALT_MPFE_IOHMC_REG_CTRLCFG9_t reg_ctrlcfg9; /* ALT_MPFE_IOHMC_REG_CTRLCFG9 */
17089  volatile ALT_MPFE_IOHMC_REG_DRAMTIMING0_t reg_dramtiming0; /* ALT_MPFE_IOHMC_REG_DRAMTIMING0 */
17090  volatile ALT_MPFE_IOHMC_REG_DRAMODT0_t reg_dramodt0; /* ALT_MPFE_IOHMC_REG_DRAMODT0 */
17091  volatile ALT_MPFE_IOHMC_REG_DRAMODT1_t reg_dramodt1; /* ALT_MPFE_IOHMC_REG_DRAMODT1 */
17092  volatile ALT_MPFE_IOHMC_REG_SBCFG0_t reg_sbcfg0; /* ALT_MPFE_IOHMC_REG_SBCFG0 */
17093  volatile ALT_MPFE_IOHMC_REG_SBCFG1_t reg_sbcfg1; /* ALT_MPFE_IOHMC_REG_SBCFG1 */
17094  volatile ALT_MPFE_IOHMC_REG_SBCFG2_t reg_sbcfg2; /* ALT_MPFE_IOHMC_REG_SBCFG2 */
17095  volatile ALT_MPFE_IOHMC_REG_SBCFG3_t reg_sbcfg3; /* ALT_MPFE_IOHMC_REG_SBCFG3 */
17096  volatile ALT_MPFE_IOHMC_REG_SBCFG4_t reg_sbcfg4; /* ALT_MPFE_IOHMC_REG_SBCFG4 */
17097  volatile ALT_MPFE_IOHMC_REG_SBCFG5_t reg_sbcfg5; /* ALT_MPFE_IOHMC_REG_SBCFG5 */
17098  volatile ALT_MPFE_IOHMC_REG_SBCFG6_t reg_sbcfg6; /* ALT_MPFE_IOHMC_REG_SBCFG6 */
17099  volatile ALT_MPFE_IOHMC_REG_SBCFG7_t reg_sbcfg7; /* ALT_MPFE_IOHMC_REG_SBCFG7 */
17100  volatile ALT_MPFE_IOHMC_REG_CALTIMING0_t reg_caltiming0; /* ALT_MPFE_IOHMC_REG_CALTIMING0 */
17101  volatile ALT_MPFE_IOHMC_REG_CALTIMING1_t reg_caltiming1; /* ALT_MPFE_IOHMC_REG_CALTIMING1 */
17102  volatile ALT_MPFE_IOHMC_REG_CALTIMING2_t reg_caltiming2; /* ALT_MPFE_IOHMC_REG_CALTIMING2 */
17103  volatile ALT_MPFE_IOHMC_REG_CALTIMING3_t reg_caltiming3; /* ALT_MPFE_IOHMC_REG_CALTIMING3 */
17104  volatile ALT_MPFE_IOHMC_REG_CALTIMING4_t reg_caltiming4; /* ALT_MPFE_IOHMC_REG_CALTIMING4 */
17105  volatile ALT_MPFE_IOHMC_REG_CALTIMING5_t reg_caltiming5; /* ALT_MPFE_IOHMC_REG_CALTIMING5 */
17106  volatile ALT_MPFE_IOHMC_REG_CALTIMING6_t reg_caltiming6; /* ALT_MPFE_IOHMC_REG_CALTIMING6 */
17107  volatile ALT_MPFE_IOHMC_REG_CALTIMING7_t reg_caltiming7; /* ALT_MPFE_IOHMC_REG_CALTIMING7 */
17108  volatile ALT_MPFE_IOHMC_REG_CALTIMING8_t reg_caltiming8; /* ALT_MPFE_IOHMC_REG_CALTIMING8 */
17109  volatile ALT_MPFE_IOHMC_REG_CALTIMING9_t reg_caltiming9; /* ALT_MPFE_IOHMC_REG_CALTIMING9 */
17110  volatile ALT_MPFE_IOHMC_REG_CALTIMING10_t reg_caltiming10; /* ALT_MPFE_IOHMC_REG_CALTIMING10 */
17111  volatile ALT_MPFE_IOHMC_REG_DRAMADDRW_t reg_dramaddrw; /* ALT_MPFE_IOHMC_REG_DRAMADDRW */
17112  volatile ALT_MPFE_IOHMC_REG_SIDEBAND0_t reg_sideband0; /* ALT_MPFE_IOHMC_REG_SIDEBAND0 */
17113  volatile ALT_MPFE_IOHMC_REG_SIDEBAND1_t reg_sideband1; /* ALT_MPFE_IOHMC_REG_SIDEBAND1 */
17114  volatile ALT_MPFE_IOHMC_REG_SIDEBAND2_t reg_sideband2; /* ALT_MPFE_IOHMC_REG_SIDEBAND2 */
17115  volatile ALT_MPFE_IOHMC_REG_SIDEBAND3_t reg_sideband3; /* ALT_MPFE_IOHMC_REG_SIDEBAND3 */
17116  volatile ALT_MPFE_IOHMC_REG_SIDEBAND4_t reg_sideband4; /* ALT_MPFE_IOHMC_REG_SIDEBAND4 */
17117  volatile ALT_MPFE_IOHMC_REG_SIDEBAND5_t reg_sideband5; /* ALT_MPFE_IOHMC_REG_SIDEBAND5 */
17118  volatile ALT_MPFE_IOHMC_REG_SIDEBAND6_t reg_sideband6; /* ALT_MPFE_IOHMC_REG_SIDEBAND6 */
17119  volatile ALT_MPFE_IOHMC_REG_SIDEBAND7_t reg_sideband7; /* ALT_MPFE_IOHMC_REG_SIDEBAND7 */
17120  volatile ALT_MPFE_IOHMC_REG_SIDEBAND8_t reg_sideband8; /* ALT_MPFE_IOHMC_REG_SIDEBAND8 */
17121  volatile ALT_MPFE_IOHMC_REG_SIDEBAND9_t reg_sideband9; /* ALT_MPFE_IOHMC_REG_SIDEBAND9 */
17122  volatile ALT_MPFE_IOHMC_REG_SIDEBAND10_t reg_sideband10; /* ALT_MPFE_IOHMC_REG_SIDEBAND10 */
17123  volatile ALT_MPFE_IOHMC_REG_SIDEBAND11_t reg_sideband11; /* ALT_MPFE_IOHMC_REG_SIDEBAND11 */
17124  volatile ALT_MPFE_IOHMC_REG_SIDEBAND12_t reg_sideband12; /* ALT_MPFE_IOHMC_REG_SIDEBAND12 */
17125  volatile ALT_MPFE_IOHMC_REG_SIDEBAND13_t reg_sideband13; /* ALT_MPFE_IOHMC_REG_SIDEBAND13 */
17126  volatile ALT_MPFE_IOHMC_REG_SIDEBAND14_t reg_sideband14; /* ALT_MPFE_IOHMC_REG_SIDEBAND14 */
17127  volatile ALT_MPFE_IOHMC_REG_SIDEBAND15_t reg_sideband15; /* ALT_MPFE_IOHMC_REG_SIDEBAND15 */
17128  volatile ALT_MPFE_IOHMC_REG_DRAMSTS_t reg_dramsts; /* ALT_MPFE_IOHMC_REG_DRAMSTS */
17129  volatile ALT_MPFE_IOHMC_REG_DBGDONE_t reg_dbgdone; /* ALT_MPFE_IOHMC_REG_DBGDONE */
17130  volatile ALT_MPFE_IOHMC_REG_DBGSIGNALS_t reg_dbgsignals; /* ALT_MPFE_IOHMC_REG_DBGSIGNALS */
17131  volatile ALT_MPFE_IOHMC_REG_DBGRESET_t reg_dbgreset; /* ALT_MPFE_IOHMC_REG_DBGRESET */
17132  volatile ALT_MPFE_IOHMC_REG_DBGMATCH_t reg_dbgmatch; /* ALT_MPFE_IOHMC_REG_DBGMATCH */
17133  volatile ALT_MPFE_IOHMC_REG_COUNTER0MASK_t reg_counter0mask; /* ALT_MPFE_IOHMC_REG_COUNTER0MASK */
17134  volatile ALT_MPFE_IOHMC_REG_COUNTER1MASK_t reg_counter1mask; /* ALT_MPFE_IOHMC_REG_COUNTER1MASK */
17135  volatile ALT_MPFE_IOHMC_REG_COUNTER0MATCH_t reg_counter0match; /* ALT_MPFE_IOHMC_REG_COUNTER0MATCH */
17136  volatile ALT_MPFE_IOHMC_REG_COUNTER1MATCH_t reg_counter1match; /* ALT_MPFE_IOHMC_REG_COUNTER1MATCH */
17137  volatile ALT_MPFE_IOHMC_REG_NIOSRESERVE0_t reg_niosreserve0; /* ALT_MPFE_IOHMC_REG_NIOSRESERVE0 */
17138  volatile ALT_MPFE_IOHMC_REG_NIOSRESERVE1_t reg_niosreserve1; /* ALT_MPFE_IOHMC_REG_NIOSRESERVE1 */
17139  volatile ALT_MPFE_IOHMC_REG_NIOSRESERVE2_t reg_niosreserve2; /* ALT_MPFE_IOHMC_REG_NIOSRESERVE2 */
17140  volatile ALT_MPFE_IOHMC_REG_SBCFG8_t reg_sbcfg8; /* ALT_MPFE_IOHMC_REG_SBCFG8 */
17141  volatile ALT_MPFE_IOHMC_REG_SBCFG9_t reg_sbcfg9; /* ALT_MPFE_IOHMC_REG_SBCFG9 */
17142  volatile ALT_MPFE_IOHMC_REG_3DS0_t reg_3ds0; /* ALT_MPFE_IOHMC_REG_3DS0 */
17143  volatile ALT_MPFE_IOHMC_REG_3DS1_t reg_3ds1; /* ALT_MPFE_IOHMC_REG_3DS1 */
17144  volatile ALT_MPFE_IOHMC_REG_3DS2_t reg_3ds2; /* ALT_MPFE_IOHMC_REG_3DS2 */
17145  volatile ALT_MPFE_IOHMC_REG_PIPELINE0_t reg_pipeline0; /* ALT_MPFE_IOHMC_REG_PIPELINE0 */
17146  volatile uint32_t _pad_0x134_0x137; /* *UNDEFINED* */
17147  volatile ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_t reg_memclockgating0; /* ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0 */
17148  volatile ALT_MPFE_IOHMC_REG_SIDEBAND16_t reg_sideband16; /* ALT_MPFE_IOHMC_REG_SIDEBAND16 */
17149  volatile uint32_t _pad_0x140_0x190[20]; /* *UNDEFINED* */
17150 };
17151 
17152 /* The typedef declaration for register group ALT_MPFE_IOHMC. */
17153 typedef struct ALT_MPFE_IOHMC_s ALT_MPFE_IOHMC_t;
17154 /* The struct declaration for the raw register contents of register group ALT_MPFE_IOHMC. */
17155 struct ALT_MPFE_IOHMC_raw_s
17156 {
17157  volatile uint32_t reg_dbgcfg0; /* ALT_MPFE_IOHMC_REG_DBGCFG0 */
17158  volatile uint32_t reg_dbgcfg1; /* ALT_MPFE_IOHMC_REG_DBGCFG1 */
17159  volatile uint32_t reg_dbgcfg2; /* ALT_MPFE_IOHMC_REG_DBGCFG2 */
17160  volatile uint32_t reg_dbgcfg3; /* ALT_MPFE_IOHMC_REG_DBGCFG3 */
17161  volatile uint32_t reg_dbgcfg4; /* ALT_MPFE_IOHMC_REG_DBGCFG4 */
17162  volatile uint32_t reg_dbgcfg5; /* ALT_MPFE_IOHMC_REG_DBGCFG5 */
17163  volatile uint32_t reg_dbgcfg6; /* ALT_MPFE_IOHMC_REG_DBGCFG6 */
17164  volatile uint32_t reg_reserve0; /* ALT_MPFE_IOHMC_REG_RESERVE0 */
17165  volatile uint32_t reg_reserve1; /* ALT_MPFE_IOHMC_REG_RESERVE1 */
17166  volatile uint32_t reg_reserve2; /* ALT_MPFE_IOHMC_REG_RESERVE2 */
17167  volatile uint32_t reg_ctrlcfg0; /* ALT_MPFE_IOHMC_REG_CTRLCFG0 */
17168  volatile uint32_t reg_ctrlcfg1; /* ALT_MPFE_IOHMC_REG_CTRLCFG1 */
17169  volatile uint32_t reg_ctrlcfg2; /* ALT_MPFE_IOHMC_REG_CTRLCFG2 */
17170  volatile uint32_t reg_ctrlcfg3; /* ALT_MPFE_IOHMC_REG_CTRLCFG3 */
17171  volatile uint32_t reg_ctrlcfg4; /* ALT_MPFE_IOHMC_REG_CTRLCFG4 */
17172  volatile uint32_t reg_ctrlcfg5; /* ALT_MPFE_IOHMC_REG_CTRLCFG5 */
17173  volatile uint32_t reg_ctrlcfg6; /* ALT_MPFE_IOHMC_REG_CTRLCFG6 */
17174  volatile uint32_t reg_ctrlcfg7; /* ALT_MPFE_IOHMC_REG_CTRLCFG7 */
17175  volatile uint32_t reg_ctrlcfg8; /* ALT_MPFE_IOHMC_REG_CTRLCFG8 */
17176  volatile uint32_t reg_ctrlcfg9; /* ALT_MPFE_IOHMC_REG_CTRLCFG9 */
17177  volatile uint32_t reg_dramtiming0; /* ALT_MPFE_IOHMC_REG_DRAMTIMING0 */
17178  volatile uint32_t reg_dramodt0; /* ALT_MPFE_IOHMC_REG_DRAMODT0 */
17179  volatile uint32_t reg_dramodt1; /* ALT_MPFE_IOHMC_REG_DRAMODT1 */
17180  volatile uint32_t reg_sbcfg0; /* ALT_MPFE_IOHMC_REG_SBCFG0 */
17181  volatile uint32_t reg_sbcfg1; /* ALT_MPFE_IOHMC_REG_SBCFG1 */
17182  volatile uint32_t reg_sbcfg2; /* ALT_MPFE_IOHMC_REG_SBCFG2 */
17183  volatile uint32_t reg_sbcfg3; /* ALT_MPFE_IOHMC_REG_SBCFG3 */
17184  volatile uint32_t reg_sbcfg4; /* ALT_MPFE_IOHMC_REG_SBCFG4 */
17185  volatile uint32_t reg_sbcfg5; /* ALT_MPFE_IOHMC_REG_SBCFG5 */
17186  volatile uint32_t reg_sbcfg6; /* ALT_MPFE_IOHMC_REG_SBCFG6 */
17187  volatile uint32_t reg_sbcfg7; /* ALT_MPFE_IOHMC_REG_SBCFG7 */
17188  volatile uint32_t reg_caltiming0; /* ALT_MPFE_IOHMC_REG_CALTIMING0 */
17189  volatile uint32_t reg_caltiming1; /* ALT_MPFE_IOHMC_REG_CALTIMING1 */
17190  volatile uint32_t reg_caltiming2; /* ALT_MPFE_IOHMC_REG_CALTIMING2 */
17191  volatile uint32_t reg_caltiming3; /* ALT_MPFE_IOHMC_REG_CALTIMING3 */
17192  volatile uint32_t reg_caltiming4; /* ALT_MPFE_IOHMC_REG_CALTIMING4 */
17193  volatile uint32_t reg_caltiming5; /* ALT_MPFE_IOHMC_REG_CALTIMING5 */
17194  volatile uint32_t reg_caltiming6; /* ALT_MPFE_IOHMC_REG_CALTIMING6 */
17195  volatile uint32_t reg_caltiming7; /* ALT_MPFE_IOHMC_REG_CALTIMING7 */
17196  volatile uint32_t reg_caltiming8; /* ALT_MPFE_IOHMC_REG_CALTIMING8 */
17197  volatile uint32_t reg_caltiming9; /* ALT_MPFE_IOHMC_REG_CALTIMING9 */
17198  volatile uint32_t reg_caltiming10; /* ALT_MPFE_IOHMC_REG_CALTIMING10 */
17199  volatile uint32_t reg_dramaddrw; /* ALT_MPFE_IOHMC_REG_DRAMADDRW */
17200  volatile uint32_t reg_sideband0; /* ALT_MPFE_IOHMC_REG_SIDEBAND0 */
17201  volatile uint32_t reg_sideband1; /* ALT_MPFE_IOHMC_REG_SIDEBAND1 */
17202  volatile uint32_t reg_sideband2; /* ALT_MPFE_IOHMC_REG_SIDEBAND2 */
17203  volatile uint32_t reg_sideband3; /* ALT_MPFE_IOHMC_REG_SIDEBAND3 */
17204  volatile uint32_t reg_sideband4; /* ALT_MPFE_IOHMC_REG_SIDEBAND4 */
17205  volatile uint32_t reg_sideband5; /* ALT_MPFE_IOHMC_REG_SIDEBAND5 */
17206  volatile uint32_t reg_sideband6; /* ALT_MPFE_IOHMC_REG_SIDEBAND6 */
17207  volatile uint32_t reg_sideband7; /* ALT_MPFE_IOHMC_REG_SIDEBAND7 */
17208  volatile uint32_t reg_sideband8; /* ALT_MPFE_IOHMC_REG_SIDEBAND8 */
17209  volatile uint32_t reg_sideband9; /* ALT_MPFE_IOHMC_REG_SIDEBAND9 */
17210  volatile uint32_t reg_sideband10; /* ALT_MPFE_IOHMC_REG_SIDEBAND10 */
17211  volatile uint32_t reg_sideband11; /* ALT_MPFE_IOHMC_REG_SIDEBAND11 */
17212  volatile uint32_t reg_sideband12; /* ALT_MPFE_IOHMC_REG_SIDEBAND12 */
17213  volatile uint32_t reg_sideband13; /* ALT_MPFE_IOHMC_REG_SIDEBAND13 */
17214  volatile uint32_t reg_sideband14; /* ALT_MPFE_IOHMC_REG_SIDEBAND14 */
17215  volatile uint32_t reg_sideband15; /* ALT_MPFE_IOHMC_REG_SIDEBAND15 */
17216  volatile uint32_t reg_dramsts; /* ALT_MPFE_IOHMC_REG_DRAMSTS */
17217  volatile uint32_t reg_dbgdone; /* ALT_MPFE_IOHMC_REG_DBGDONE */
17218  volatile uint32_t reg_dbgsignals; /* ALT_MPFE_IOHMC_REG_DBGSIGNALS */
17219  volatile uint32_t reg_dbgreset; /* ALT_MPFE_IOHMC_REG_DBGRESET */
17220  volatile uint32_t reg_dbgmatch; /* ALT_MPFE_IOHMC_REG_DBGMATCH */
17221  volatile uint32_t reg_counter0mask; /* ALT_MPFE_IOHMC_REG_COUNTER0MASK */
17222  volatile uint32_t reg_counter1mask; /* ALT_MPFE_IOHMC_REG_COUNTER1MASK */
17223  volatile uint32_t reg_counter0match; /* ALT_MPFE_IOHMC_REG_COUNTER0MATCH */
17224  volatile uint32_t reg_counter1match; /* ALT_MPFE_IOHMC_REG_COUNTER1MATCH */
17225  volatile uint32_t reg_niosreserve0; /* ALT_MPFE_IOHMC_REG_NIOSRESERVE0 */
17226  volatile uint32_t reg_niosreserve1; /* ALT_MPFE_IOHMC_REG_NIOSRESERVE1 */
17227  volatile uint32_t reg_niosreserve2; /* ALT_MPFE_IOHMC_REG_NIOSRESERVE2 */
17228  volatile uint32_t reg_sbcfg8; /* ALT_MPFE_IOHMC_REG_SBCFG8 */
17229  volatile uint32_t reg_sbcfg9; /* ALT_MPFE_IOHMC_REG_SBCFG9 */
17230  volatile uint32_t reg_3ds0; /* ALT_MPFE_IOHMC_REG_3DS0 */
17231  volatile uint32_t reg_3ds1; /* ALT_MPFE_IOHMC_REG_3DS1 */
17232  volatile uint32_t reg_3ds2; /* ALT_MPFE_IOHMC_REG_3DS2 */
17233  volatile uint32_t reg_pipeline0; /* ALT_MPFE_IOHMC_REG_PIPELINE0 */
17234  volatile uint32_t _pad_0x134_0x137; /* *UNDEFINED* */
17235  volatile uint32_t reg_memclockgating0; /* ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0 */
17236  volatile uint32_t reg_sideband16; /* ALT_MPFE_IOHMC_REG_SIDEBAND16 */
17237  volatile uint32_t _pad_0x140_0x190[20]; /* *UNDEFINED* */
17238 };
17239 
17240 /* The typedef declaration for the raw register contents of register group ALT_MPFE_IOHMC. */
17241 typedef struct ALT_MPFE_IOHMC_raw_s ALT_MPFE_IOHMC_raw_t;
17242 #endif /* __ASSEMBLY__ */
17243 
17244 
17245 /*
17246  * Component : MPFE_HMC_ADP
17247  * Block
17248  *
17249  */
17250 /*
17251  * Register : IP_REV_ID - IP_REV_ID
17252  *
17253  * IDO Register
17254  *
17255  * Register Layout
17256  *
17257  * Bits | Access | Reset | Description
17258  * :--------|:-------|:------|:---------------------------------
17259  * [15:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV
17260  * [31:16] | ??? | 0x0 | *UNDEFINED*
17261  *
17262  */
17263 /*
17264  * Field : SIREV
17265  *
17266  * IP Rev #These bits indicate the silicon revision number
17267  *
17268  * Field Access Macros:
17269  *
17270  */
17271 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV register field. */
17272 #define ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV_LSB 0
17273 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV register field. */
17274 #define ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV_MSB 15
17275 /* The width in bits of the ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV register field. */
17276 #define ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV_WIDTH 16
17277 /* The mask used to set the ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV register field value. */
17278 #define ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV_SET_MSK 0x0000ffff
17279 /* The mask used to clear the ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV register field value. */
17280 #define ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV_CLR_MSK 0xffff0000
17281 /* The reset value of the ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV register field. */
17282 #define ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV_RESET 0x0
17283 /* Extracts the ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV field value from a register. */
17284 #define ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV_GET(value) (((value) & 0x0000ffff) >> 0)
17285 /* Produces a ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV register field value suitable for setting the register. */
17286 #define ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV_SET(value) (((value) << 0) & 0x0000ffff)
17287 
17288 #ifndef __ASSEMBLY__
17289 /*
17290  * WARNING: The C register and register group struct declarations are provided for
17291  * convenience and illustrative purposes. They should, however, be used with
17292  * caution as the C language standard provides no guarantees about the alignment or
17293  * atomicity of device memory accesses. The recommended practice for coding device
17294  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17295  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17296  * alt_write_dword() functions for 64 bit registers.
17297  *
17298  * The struct declaration for register ALT_MPFE_HMC_ADP_IP_REV_ID.
17299  */
17300 struct ALT_MPFE_HMC_ADP_IP_REV_ID_s
17301 {
17302  volatile uint32_t SIREV : 16; /* ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV */
17303  uint32_t : 16; /* *UNDEFINED* */
17304 };
17305 
17306 /* The typedef declaration for register ALT_MPFE_HMC_ADP_IP_REV_ID. */
17307 typedef struct ALT_MPFE_HMC_ADP_IP_REV_ID_s ALT_MPFE_HMC_ADP_IP_REV_ID_t;
17308 #endif /* __ASSEMBLY__ */
17309 
17310 /* The reset value of the ALT_MPFE_HMC_ADP_IP_REV_ID register. */
17311 #define ALT_MPFE_HMC_ADP_IP_REV_ID_RESET 0x00000000
17312 /* The byte offset of the ALT_MPFE_HMC_ADP_IP_REV_ID register from the beginning of the component. */
17313 #define ALT_MPFE_HMC_ADP_IP_REV_ID_OFST 0x0
17314 
17315 /*
17316  * Register : DDRIOCTRL
17317  *
17318  * DDR IO Control Register
17319  *
17320  * Register Layout
17321  *
17322  * Bits | Access | Reset | Description
17323  * :-------|:-------|:------|:-----------------------------------
17324  * [1:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE
17325  * [31:2] | ??? | 0x0 | *UNDEFINED*
17326  *
17327  */
17328 /*
17329  * Field : IO_SIZE
17330  *
17331  * External Configuration of DDR IO size.
17332  *
17333  * These bits are configured at start to indicate the external DDR IO size.
17334  *
17335  * 2b00 = DDR IO x16. default value after reset
17336  *
17337  * 2b01 = DDR IO x32
17338  *
17339  * 2b10 = DDR IO x64
17340  *
17341  * Field Enumeration Values:
17342  *
17343  * Enum | Value | Description
17344  * :-----------------------------------------|:------|:------------
17345  * ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_E_X16 | 0x0 |
17346  * ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_E_X32 | 0x1 |
17347  * ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_E_X64 | 0x2 |
17348  *
17349  * Field Access Macros:
17350  *
17351  */
17352 /*
17353  * Enumerated value for register field ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE
17354  *
17355  */
17356 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_E_X16 0x0
17357 /*
17358  * Enumerated value for register field ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE
17359  *
17360  */
17361 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_E_X32 0x1
17362 /*
17363  * Enumerated value for register field ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE
17364  *
17365  */
17366 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_E_X64 0x2
17367 
17368 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE register field. */
17369 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_LSB 0
17370 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE register field. */
17371 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_MSB 1
17372 /* The width in bits of the ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE register field. */
17373 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_WIDTH 2
17374 /* The mask used to set the ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE register field value. */
17375 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_SET_MSK 0x00000003
17376 /* The mask used to clear the ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE register field value. */
17377 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_CLR_MSK 0xfffffffc
17378 /* The reset value of the ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE register field. */
17379 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_RESET 0x0
17380 /* Extracts the ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE field value from a register. */
17381 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_GET(value) (((value) & 0x00000003) >> 0)
17382 /* Produces a ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE register field value suitable for setting the register. */
17383 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_SET(value) (((value) << 0) & 0x00000003)
17384 
17385 #ifndef __ASSEMBLY__
17386 /*
17387  * WARNING: The C register and register group struct declarations are provided for
17388  * convenience and illustrative purposes. They should, however, be used with
17389  * caution as the C language standard provides no guarantees about the alignment or
17390  * atomicity of device memory accesses. The recommended practice for coding device
17391  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17392  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17393  * alt_write_dword() functions for 64 bit registers.
17394  *
17395  * The struct declaration for register ALT_MPFE_HMC_ADP_DDRIOCTRL.
17396  */
17397 struct ALT_MPFE_HMC_ADP_DDRIOCTRL_s
17398 {
17399  volatile uint32_t IO_SIZE : 2; /* ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE */
17400  uint32_t : 30; /* *UNDEFINED* */
17401 };
17402 
17403 /* The typedef declaration for register ALT_MPFE_HMC_ADP_DDRIOCTRL. */
17404 typedef struct ALT_MPFE_HMC_ADP_DDRIOCTRL_s ALT_MPFE_HMC_ADP_DDRIOCTRL_t;
17405 #endif /* __ASSEMBLY__ */
17406 
17407 /* The reset value of the ALT_MPFE_HMC_ADP_DDRIOCTRL register. */
17408 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_RESET 0x00000000
17409 /* The byte offset of the ALT_MPFE_HMC_ADP_DDRIOCTRL register from the beginning of the component. */
17410 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_OFST 0x8
17411 
17412 /*
17413  * Register : DDRCALSTAT
17414  *
17415  * DDR Calibration Status Register
17416  *
17417  * Register Layout
17418  *
17419  * Bits | Access | Reset | Description
17420  * :-------|:-------|:------|:---------------------------------
17421  * [0] | RW | 0x0 | ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL
17422  * [1] | RW | 0x0 | ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL
17423  * [31:2] | ??? | 0x0 | *UNDEFINED*
17424  *
17425  */
17426 /*
17427  * Field : CAL
17428  *
17429  * DDR calibration status.
17430  *
17431  * Indicates the DDR calibration was successful.
17432  *
17433  * 1'b0: When set to 0, calibration is either on going, hasn't started or failed.
17434  *
17435  * 1'b1: When set to 1, calibration has succeeded.
17436  *
17437  * Field Access Macros:
17438  *
17439  */
17440 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL register field. */
17441 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL_LSB 0
17442 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL register field. */
17443 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL_MSB 0
17444 /* The width in bits of the ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL register field. */
17445 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL_WIDTH 1
17446 /* The mask used to set the ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL register field value. */
17447 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL_SET_MSK 0x00000001
17448 /* The mask used to clear the ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL register field value. */
17449 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL_CLR_MSK 0xfffffffe
17450 /* The reset value of the ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL register field. */
17451 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL_RESET 0x0
17452 /* Extracts the ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL field value from a register. */
17453 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL_GET(value) (((value) & 0x00000001) >> 0)
17454 /* Produces a ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL register field value suitable for setting the register. */
17455 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL_SET(value) (((value) << 0) & 0x00000001)
17456 
17457 /*
17458  * Field : FAIL
17459  *
17460  * DDR calibration failure status.
17461  *
17462  * Indicates whether DDR calibration has failed.
17463  *
17464  * 1'b0: Calibration is in progress or did not fail.
17465  *
17466  * 1'b1: Calibration failed.
17467  *
17468  * Field Access Macros:
17469  *
17470  */
17471 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL register field. */
17472 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL_LSB 1
17473 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL register field. */
17474 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL_MSB 1
17475 /* The width in bits of the ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL register field. */
17476 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL_WIDTH 1
17477 /* The mask used to set the ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL register field value. */
17478 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL_SET_MSK 0x00000002
17479 /* The mask used to clear the ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL register field value. */
17480 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL_CLR_MSK 0xfffffffd
17481 /* The reset value of the ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL register field. */
17482 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL_RESET 0x0
17483 /* Extracts the ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL field value from a register. */
17484 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL_GET(value) (((value) & 0x00000002) >> 1)
17485 /* Produces a ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL register field value suitable for setting the register. */
17486 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL_SET(value) (((value) << 1) & 0x00000002)
17487 
17488 #ifndef __ASSEMBLY__
17489 /*
17490  * WARNING: The C register and register group struct declarations are provided for
17491  * convenience and illustrative purposes. They should, however, be used with
17492  * caution as the C language standard provides no guarantees about the alignment or
17493  * atomicity of device memory accesses. The recommended practice for coding device
17494  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17495  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17496  * alt_write_dword() functions for 64 bit registers.
17497  *
17498  * The struct declaration for register ALT_MPFE_HMC_ADP_DDRCALSTAT.
17499  */
17500 struct ALT_MPFE_HMC_ADP_DDRCALSTAT_s
17501 {
17502  volatile uint32_t CAL : 1; /* ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL */
17503  volatile uint32_t FAIL : 1; /* ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL */
17504  uint32_t : 30; /* *UNDEFINED* */
17505 };
17506 
17507 /* The typedef declaration for register ALT_MPFE_HMC_ADP_DDRCALSTAT. */
17508 typedef struct ALT_MPFE_HMC_ADP_DDRCALSTAT_s ALT_MPFE_HMC_ADP_DDRCALSTAT_t;
17509 #endif /* __ASSEMBLY__ */
17510 
17511 /* The reset value of the ALT_MPFE_HMC_ADP_DDRCALSTAT register. */
17512 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_RESET 0x00000000
17513 /* The byte offset of the ALT_MPFE_HMC_ADP_DDRCALSTAT register from the beginning of the component. */
17514 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_OFST 0xc
17515 
17516 /*
17517  * Register : MPR_0BEAT1
17518  *
17519  * MPR register [31:0] for first beat
17520  *
17521  * Register Layout
17522  *
17523  * Bits | Access | Reset | Description
17524  * :-------|:-------|:------|:---------------------------------
17525  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0
17526  *
17527  */
17528 /*
17529  * Field : MPR0
17530  *
17531  * MPR reg[31:0] for first beat
17532  *
17533  * Field Access Macros:
17534  *
17535  */
17536 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0 register field. */
17537 #define ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0_LSB 0
17538 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0 register field. */
17539 #define ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0_MSB 31
17540 /* The width in bits of the ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0 register field. */
17541 #define ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0_WIDTH 32
17542 /* The mask used to set the ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0 register field value. */
17543 #define ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0_SET_MSK 0xffffffff
17544 /* The mask used to clear the ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0 register field value. */
17545 #define ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0_CLR_MSK 0x00000000
17546 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0 register field. */
17547 #define ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0_RESET 0x0
17548 /* Extracts the ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0 field value from a register. */
17549 #define ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0_GET(value) (((value) & 0xffffffff) >> 0)
17550 /* Produces a ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0 register field value suitable for setting the register. */
17551 #define ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0_SET(value) (((value) << 0) & 0xffffffff)
17552 
17553 #ifndef __ASSEMBLY__
17554 /*
17555  * WARNING: The C register and register group struct declarations are provided for
17556  * convenience and illustrative purposes. They should, however, be used with
17557  * caution as the C language standard provides no guarantees about the alignment or
17558  * atomicity of device memory accesses. The recommended practice for coding device
17559  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17560  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17561  * alt_write_dword() functions for 64 bit registers.
17562  *
17563  * The struct declaration for register ALT_MPFE_HMC_ADP_MPR_0BEAT1.
17564  */
17565 struct ALT_MPFE_HMC_ADP_MPR_0BEAT1_s
17566 {
17567  volatile uint32_t MPR0 : 32; /* ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0 */
17568 };
17569 
17570 /* The typedef declaration for register ALT_MPFE_HMC_ADP_MPR_0BEAT1. */
17571 typedef struct ALT_MPFE_HMC_ADP_MPR_0BEAT1_s ALT_MPFE_HMC_ADP_MPR_0BEAT1_t;
17572 #endif /* __ASSEMBLY__ */
17573 
17574 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_0BEAT1 register. */
17575 #define ALT_MPFE_HMC_ADP_MPR_0BEAT1_RESET 0x00000000
17576 /* The byte offset of the ALT_MPFE_HMC_ADP_MPR_0BEAT1 register from the beginning of the component. */
17577 #define ALT_MPFE_HMC_ADP_MPR_0BEAT1_OFST 0x10
17578 
17579 /*
17580  * Register : MPR_1BEAT1
17581  *
17582  * MPR register [63:32] for first beat
17583  *
17584  * Register Layout
17585  *
17586  * Bits | Access | Reset | Description
17587  * :-------|:-------|:------|:----------------------------------
17588  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32
17589  *
17590  */
17591 /*
17592  * Field : MPR32
17593  *
17594  * MPR reg[63:32] for first beat
17595  *
17596  * Field Access Macros:
17597  *
17598  */
17599 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32 register field. */
17600 #define ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32_LSB 0
17601 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32 register field. */
17602 #define ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32_MSB 31
17603 /* The width in bits of the ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32 register field. */
17604 #define ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32_WIDTH 32
17605 /* The mask used to set the ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32 register field value. */
17606 #define ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32_SET_MSK 0xffffffff
17607 /* The mask used to clear the ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32 register field value. */
17608 #define ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32_CLR_MSK 0x00000000
17609 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32 register field. */
17610 #define ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32_RESET 0x0
17611 /* Extracts the ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32 field value from a register. */
17612 #define ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32_GET(value) (((value) & 0xffffffff) >> 0)
17613 /* Produces a ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32 register field value suitable for setting the register. */
17614 #define ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32_SET(value) (((value) << 0) & 0xffffffff)
17615 
17616 #ifndef __ASSEMBLY__
17617 /*
17618  * WARNING: The C register and register group struct declarations are provided for
17619  * convenience and illustrative purposes. They should, however, be used with
17620  * caution as the C language standard provides no guarantees about the alignment or
17621  * atomicity of device memory accesses. The recommended practice for coding device
17622  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17623  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17624  * alt_write_dword() functions for 64 bit registers.
17625  *
17626  * The struct declaration for register ALT_MPFE_HMC_ADP_MPR_1BEAT1.
17627  */
17628 struct ALT_MPFE_HMC_ADP_MPR_1BEAT1_s
17629 {
17630  volatile uint32_t MPR32 : 32; /* ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32 */
17631 };
17632 
17633 /* The typedef declaration for register ALT_MPFE_HMC_ADP_MPR_1BEAT1. */
17634 typedef struct ALT_MPFE_HMC_ADP_MPR_1BEAT1_s ALT_MPFE_HMC_ADP_MPR_1BEAT1_t;
17635 #endif /* __ASSEMBLY__ */
17636 
17637 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_1BEAT1 register. */
17638 #define ALT_MPFE_HMC_ADP_MPR_1BEAT1_RESET 0x00000000
17639 /* The byte offset of the ALT_MPFE_HMC_ADP_MPR_1BEAT1 register from the beginning of the component. */
17640 #define ALT_MPFE_HMC_ADP_MPR_1BEAT1_OFST 0x14
17641 
17642 /*
17643  * Register : MPR_2BEAT1
17644  *
17645  * MPR register [95:64] for first beat
17646  *
17647  * Register Layout
17648  *
17649  * Bits | Access | Reset | Description
17650  * :-------|:-------|:------|:----------------------------------
17651  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64
17652  *
17653  */
17654 /*
17655  * Field : MPR64
17656  *
17657  * MPR reg[95:64] for first beat
17658  *
17659  * Field Access Macros:
17660  *
17661  */
17662 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64 register field. */
17663 #define ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64_LSB 0
17664 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64 register field. */
17665 #define ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64_MSB 31
17666 /* The width in bits of the ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64 register field. */
17667 #define ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64_WIDTH 32
17668 /* The mask used to set the ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64 register field value. */
17669 #define ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64_SET_MSK 0xffffffff
17670 /* The mask used to clear the ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64 register field value. */
17671 #define ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64_CLR_MSK 0x00000000
17672 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64 register field. */
17673 #define ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64_RESET 0x0
17674 /* Extracts the ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64 field value from a register. */
17675 #define ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64_GET(value) (((value) & 0xffffffff) >> 0)
17676 /* Produces a ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64 register field value suitable for setting the register. */
17677 #define ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64_SET(value) (((value) << 0) & 0xffffffff)
17678 
17679 #ifndef __ASSEMBLY__
17680 /*
17681  * WARNING: The C register and register group struct declarations are provided for
17682  * convenience and illustrative purposes. They should, however, be used with
17683  * caution as the C language standard provides no guarantees about the alignment or
17684  * atomicity of device memory accesses. The recommended practice for coding device
17685  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17686  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17687  * alt_write_dword() functions for 64 bit registers.
17688  *
17689  * The struct declaration for register ALT_MPFE_HMC_ADP_MPR_2BEAT1.
17690  */
17691 struct ALT_MPFE_HMC_ADP_MPR_2BEAT1_s
17692 {
17693  volatile uint32_t MPR64 : 32; /* ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64 */
17694 };
17695 
17696 /* The typedef declaration for register ALT_MPFE_HMC_ADP_MPR_2BEAT1. */
17697 typedef struct ALT_MPFE_HMC_ADP_MPR_2BEAT1_s ALT_MPFE_HMC_ADP_MPR_2BEAT1_t;
17698 #endif /* __ASSEMBLY__ */
17699 
17700 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_2BEAT1 register. */
17701 #define ALT_MPFE_HMC_ADP_MPR_2BEAT1_RESET 0x00000000
17702 /* The byte offset of the ALT_MPFE_HMC_ADP_MPR_2BEAT1 register from the beginning of the component. */
17703 #define ALT_MPFE_HMC_ADP_MPR_2BEAT1_OFST 0x18
17704 
17705 /*
17706  * Register : MPR_3BEAT1
17707  *
17708  * MPR register [127:96] for first beat
17709  *
17710  * Register Layout
17711  *
17712  * Bits | Access | Reset | Description
17713  * :-------|:-------|:------|:----------------------------------
17714  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96
17715  *
17716  */
17717 /*
17718  * Field : MPR96
17719  *
17720  * MPR reg[127:96] for first beat
17721  *
17722  * Field Access Macros:
17723  *
17724  */
17725 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96 register field. */
17726 #define ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96_LSB 0
17727 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96 register field. */
17728 #define ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96_MSB 31
17729 /* The width in bits of the ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96 register field. */
17730 #define ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96_WIDTH 32
17731 /* The mask used to set the ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96 register field value. */
17732 #define ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96_SET_MSK 0xffffffff
17733 /* The mask used to clear the ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96 register field value. */
17734 #define ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96_CLR_MSK 0x00000000
17735 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96 register field. */
17736 #define ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96_RESET 0x0
17737 /* Extracts the ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96 field value from a register. */
17738 #define ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96_GET(value) (((value) & 0xffffffff) >> 0)
17739 /* Produces a ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96 register field value suitable for setting the register. */
17740 #define ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96_SET(value) (((value) << 0) & 0xffffffff)
17741 
17742 #ifndef __ASSEMBLY__
17743 /*
17744  * WARNING: The C register and register group struct declarations are provided for
17745  * convenience and illustrative purposes. They should, however, be used with
17746  * caution as the C language standard provides no guarantees about the alignment or
17747  * atomicity of device memory accesses. The recommended practice for coding device
17748  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17749  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17750  * alt_write_dword() functions for 64 bit registers.
17751  *
17752  * The struct declaration for register ALT_MPFE_HMC_ADP_MPR_3BEAT1.
17753  */
17754 struct ALT_MPFE_HMC_ADP_MPR_3BEAT1_s
17755 {
17756  volatile uint32_t MPR96 : 32; /* ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96 */
17757 };
17758 
17759 /* The typedef declaration for register ALT_MPFE_HMC_ADP_MPR_3BEAT1. */
17760 typedef struct ALT_MPFE_HMC_ADP_MPR_3BEAT1_s ALT_MPFE_HMC_ADP_MPR_3BEAT1_t;
17761 #endif /* __ASSEMBLY__ */
17762 
17763 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_3BEAT1 register. */
17764 #define ALT_MPFE_HMC_ADP_MPR_3BEAT1_RESET 0x00000000
17765 /* The byte offset of the ALT_MPFE_HMC_ADP_MPR_3BEAT1 register from the beginning of the component. */
17766 #define ALT_MPFE_HMC_ADP_MPR_3BEAT1_OFST 0x1c
17767 
17768 /*
17769  * Register : MPR_4BEAT1
17770  *
17771  * MPR register [159:128] for first beat
17772  *
17773  * Register Layout
17774  *
17775  * Bits | Access | Reset | Description
17776  * :-------|:-------|:------|:-----------------------------------
17777  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128
17778  *
17779  */
17780 /*
17781  * Field : MPR128
17782  *
17783  * MPR reg[159:128] for first beat
17784  *
17785  * Field Access Macros:
17786  *
17787  */
17788 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128 register field. */
17789 #define ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128_LSB 0
17790 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128 register field. */
17791 #define ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128_MSB 31
17792 /* The width in bits of the ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128 register field. */
17793 #define ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128_WIDTH 32
17794 /* The mask used to set the ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128 register field value. */
17795 #define ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128_SET_MSK 0xffffffff
17796 /* The mask used to clear the ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128 register field value. */
17797 #define ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128_CLR_MSK 0x00000000
17798 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128 register field. */
17799 #define ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128_RESET 0x0
17800 /* Extracts the ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128 field value from a register. */
17801 #define ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128_GET(value) (((value) & 0xffffffff) >> 0)
17802 /* Produces a ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128 register field value suitable for setting the register. */
17803 #define ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128_SET(value) (((value) << 0) & 0xffffffff)
17804 
17805 #ifndef __ASSEMBLY__
17806 /*
17807  * WARNING: The C register and register group struct declarations are provided for
17808  * convenience and illustrative purposes. They should, however, be used with
17809  * caution as the C language standard provides no guarantees about the alignment or
17810  * atomicity of device memory accesses. The recommended practice for coding device
17811  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17812  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17813  * alt_write_dword() functions for 64 bit registers.
17814  *
17815  * The struct declaration for register ALT_MPFE_HMC_ADP_MPR_4BEAT1.
17816  */
17817 struct ALT_MPFE_HMC_ADP_MPR_4BEAT1_s
17818 {
17819  volatile uint32_t MPR128 : 32; /* ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128 */
17820 };
17821 
17822 /* The typedef declaration for register ALT_MPFE_HMC_ADP_MPR_4BEAT1. */
17823 typedef struct ALT_MPFE_HMC_ADP_MPR_4BEAT1_s ALT_MPFE_HMC_ADP_MPR_4BEAT1_t;
17824 #endif /* __ASSEMBLY__ */
17825 
17826 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_4BEAT1 register. */
17827 #define ALT_MPFE_HMC_ADP_MPR_4BEAT1_RESET 0x00000000
17828 /* The byte offset of the ALT_MPFE_HMC_ADP_MPR_4BEAT1 register from the beginning of the component. */
17829 #define ALT_MPFE_HMC_ADP_MPR_4BEAT1_OFST 0x20
17830 
17831 /*
17832  * Register : MPR_5BEAT1
17833  *
17834  * MPR register [191:160] for first beat
17835  *
17836  * Register Layout
17837  *
17838  * Bits | Access | Reset | Description
17839  * :-------|:-------|:------|:-----------------------------------
17840  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160
17841  *
17842  */
17843 /*
17844  * Field : MPR160
17845  *
17846  * MPR reg[191:160] for first beat
17847  *
17848  * Field Access Macros:
17849  *
17850  */
17851 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160 register field. */
17852 #define ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160_LSB 0
17853 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160 register field. */
17854 #define ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160_MSB 31
17855 /* The width in bits of the ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160 register field. */
17856 #define ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160_WIDTH 32
17857 /* The mask used to set the ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160 register field value. */
17858 #define ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160_SET_MSK 0xffffffff
17859 /* The mask used to clear the ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160 register field value. */
17860 #define ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160_CLR_MSK 0x00000000
17861 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160 register field. */
17862 #define ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160_RESET 0x0
17863 /* Extracts the ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160 field value from a register. */
17864 #define ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160_GET(value) (((value) & 0xffffffff) >> 0)
17865 /* Produces a ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160 register field value suitable for setting the register. */
17866 #define ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160_SET(value) (((value) << 0) & 0xffffffff)
17867 
17868 #ifndef __ASSEMBLY__
17869 /*
17870  * WARNING: The C register and register group struct declarations are provided for
17871  * convenience and illustrative purposes. They should, however, be used with
17872  * caution as the C language standard provides no guarantees about the alignment or
17873  * atomicity of device memory accesses. The recommended practice for coding device
17874  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17875  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17876  * alt_write_dword() functions for 64 bit registers.
17877  *
17878  * The struct declaration for register ALT_MPFE_HMC_ADP_MPR_5BEAT1.
17879  */
17880 struct ALT_MPFE_HMC_ADP_MPR_5BEAT1_s
17881 {
17882  volatile uint32_t MPR160 : 32; /* ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160 */
17883 };
17884 
17885 /* The typedef declaration for register ALT_MPFE_HMC_ADP_MPR_5BEAT1. */
17886 typedef struct ALT_MPFE_HMC_ADP_MPR_5BEAT1_s ALT_MPFE_HMC_ADP_MPR_5BEAT1_t;
17887 #endif /* __ASSEMBLY__ */
17888 
17889 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_5BEAT1 register. */
17890 #define ALT_MPFE_HMC_ADP_MPR_5BEAT1_RESET 0x00000000
17891 /* The byte offset of the ALT_MPFE_HMC_ADP_MPR_5BEAT1 register from the beginning of the component. */
17892 #define ALT_MPFE_HMC_ADP_MPR_5BEAT1_OFST 0x24
17893 
17894 /*
17895  * Register : MPR_6BEAT1
17896  *
17897  * MPR register [223:192] for first beat
17898  *
17899  * Register Layout
17900  *
17901  * Bits | Access | Reset | Description
17902  * :-------|:-------|:------|:-----------------------------------
17903  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192
17904  *
17905  */
17906 /*
17907  * Field : MPR192
17908  *
17909  * MPR reg[223:192] for first beat
17910  *
17911  * Field Access Macros:
17912  *
17913  */
17914 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192 register field. */
17915 #define ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192_LSB 0
17916 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192 register field. */
17917 #define ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192_MSB 31
17918 /* The width in bits of the ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192 register field. */
17919 #define ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192_WIDTH 32
17920 /* The mask used to set the ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192 register field value. */
17921 #define ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192_SET_MSK 0xffffffff
17922 /* The mask used to clear the ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192 register field value. */
17923 #define ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192_CLR_MSK 0x00000000
17924 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192 register field. */
17925 #define ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192_RESET 0x0
17926 /* Extracts the ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192 field value from a register. */
17927 #define ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192_GET(value) (((value) & 0xffffffff) >> 0)
17928 /* Produces a ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192 register field value suitable for setting the register. */
17929 #define ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192_SET(value) (((value) << 0) & 0xffffffff)
17930 
17931 #ifndef __ASSEMBLY__
17932 /*
17933  * WARNING: The C register and register group struct declarations are provided for
17934  * convenience and illustrative purposes. They should, however, be used with
17935  * caution as the C language standard provides no guarantees about the alignment or
17936  * atomicity of device memory accesses. The recommended practice for coding device
17937  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17938  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17939  * alt_write_dword() functions for 64 bit registers.
17940  *
17941  * The struct declaration for register ALT_MPFE_HMC_ADP_MPR_6BEAT1.
17942  */
17943 struct ALT_MPFE_HMC_ADP_MPR_6BEAT1_s
17944 {
17945  volatile uint32_t MPR192 : 32; /* ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192 */
17946 };
17947 
17948 /* The typedef declaration for register ALT_MPFE_HMC_ADP_MPR_6BEAT1. */
17949 typedef struct ALT_MPFE_HMC_ADP_MPR_6BEAT1_s ALT_MPFE_HMC_ADP_MPR_6BEAT1_t;
17950 #endif /* __ASSEMBLY__ */
17951 
17952 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_6BEAT1 register. */
17953 #define ALT_MPFE_HMC_ADP_MPR_6BEAT1_RESET 0x00000000
17954 /* The byte offset of the ALT_MPFE_HMC_ADP_MPR_6BEAT1 register from the beginning of the component. */
17955 #define ALT_MPFE_HMC_ADP_MPR_6BEAT1_OFST 0x28
17956 
17957 /*
17958  * Register : MPR_7BEAT1
17959  *
17960  * MPR register [255:224] for first beat
17961  *
17962  * Register Layout
17963  *
17964  * Bits | Access | Reset | Description
17965  * :-------|:-------|:------|:-----------------------------------
17966  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224
17967  *
17968  */
17969 /*
17970  * Field : MPR224
17971  *
17972  * MPR reg[255:224] for first beat
17973  *
17974  * Field Access Macros:
17975  *
17976  */
17977 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224 register field. */
17978 #define ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224_LSB 0
17979 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224 register field. */
17980 #define ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224_MSB 31
17981 /* The width in bits of the ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224 register field. */
17982 #define ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224_WIDTH 32
17983 /* The mask used to set the ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224 register field value. */
17984 #define ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224_SET_MSK 0xffffffff
17985 /* The mask used to clear the ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224 register field value. */
17986 #define ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224_CLR_MSK 0x00000000
17987 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224 register field. */
17988 #define ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224_RESET 0x0
17989 /* Extracts the ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224 field value from a register. */
17990 #define ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224_GET(value) (((value) & 0xffffffff) >> 0)
17991 /* Produces a ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224 register field value suitable for setting the register. */
17992 #define ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224_SET(value) (((value) << 0) & 0xffffffff)
17993 
17994 #ifndef __ASSEMBLY__
17995 /*
17996  * WARNING: The C register and register group struct declarations are provided for
17997  * convenience and illustrative purposes. They should, however, be used with
17998  * caution as the C language standard provides no guarantees about the alignment or
17999  * atomicity of device memory accesses. The recommended practice for coding device
18000  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18001  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18002  * alt_write_dword() functions for 64 bit registers.
18003  *
18004  * The struct declaration for register ALT_MPFE_HMC_ADP_MPR_7BEAT1.
18005  */
18006 struct ALT_MPFE_HMC_ADP_MPR_7BEAT1_s
18007 {
18008  volatile uint32_t MPR224 : 32; /* ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224 */
18009 };
18010 
18011 /* The typedef declaration for register ALT_MPFE_HMC_ADP_MPR_7BEAT1. */
18012 typedef struct ALT_MPFE_HMC_ADP_MPR_7BEAT1_s ALT_MPFE_HMC_ADP_MPR_7BEAT1_t;
18013 #endif /* __ASSEMBLY__ */
18014 
18015 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_7BEAT1 register. */
18016 #define ALT_MPFE_HMC_ADP_MPR_7BEAT1_RESET 0x00000000
18017 /* The byte offset of the ALT_MPFE_HMC_ADP_MPR_7BEAT1 register from the beginning of the component. */
18018 #define ALT_MPFE_HMC_ADP_MPR_7BEAT1_OFST 0x2c
18019 
18020 /*
18021  * Register : MPR_8BEAT1
18022  *
18023  * MPR register [287:256] for first beat
18024  *
18025  * Register Layout
18026  *
18027  * Bits | Access | Reset | Description
18028  * :-------|:-------|:------|:-----------------------------------
18029  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256
18030  *
18031  */
18032 /*
18033  * Field : MPR256
18034  *
18035  * MPR reg[287:256] for first beat
18036  *
18037  * Field Access Macros:
18038  *
18039  */
18040 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256 register field. */
18041 #define ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256_LSB 0
18042 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256 register field. */
18043 #define ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256_MSB 31
18044 /* The width in bits of the ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256 register field. */
18045 #define ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256_WIDTH 32
18046 /* The mask used to set the ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256 register field value. */
18047 #define ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256_SET_MSK 0xffffffff
18048 /* The mask used to clear the ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256 register field value. */
18049 #define ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256_CLR_MSK 0x00000000
18050 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256 register field. */
18051 #define ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256_RESET 0x0
18052 /* Extracts the ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256 field value from a register. */
18053 #define ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256_GET(value) (((value) & 0xffffffff) >> 0)
18054 /* Produces a ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256 register field value suitable for setting the register. */
18055 #define ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256_SET(value) (((value) << 0) & 0xffffffff)
18056 
18057 #ifndef __ASSEMBLY__
18058 /*
18059  * WARNING: The C register and register group struct declarations are provided for
18060  * convenience and illustrative purposes. They should, however, be used with
18061  * caution as the C language standard provides no guarantees about the alignment or
18062  * atomicity of device memory accesses. The recommended practice for coding device
18063  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18064  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18065  * alt_write_dword() functions for 64 bit registers.
18066  *
18067  * The struct declaration for register ALT_MPFE_HMC_ADP_MPR_8BEAT1.
18068  */
18069 struct ALT_MPFE_HMC_ADP_MPR_8BEAT1_s
18070 {
18071  volatile uint32_t MPR256 : 32; /* ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256 */
18072 };
18073 
18074 /* The typedef declaration for register ALT_MPFE_HMC_ADP_MPR_8BEAT1. */
18075 typedef struct ALT_MPFE_HMC_ADP_MPR_8BEAT1_s ALT_MPFE_HMC_ADP_MPR_8BEAT1_t;
18076 #endif /* __ASSEMBLY__ */
18077 
18078 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_8BEAT1 register. */
18079 #define ALT_MPFE_HMC_ADP_MPR_8BEAT1_RESET 0x00000000
18080 /* The byte offset of the ALT_MPFE_HMC_ADP_MPR_8BEAT1 register from the beginning of the component. */
18081 #define ALT_MPFE_HMC_ADP_MPR_8BEAT1_OFST 0x30
18082 
18083 /*
18084  * Register : MPR_0BEAT2
18085  *
18086  * MPR register [31:0] for second beat
18087  *
18088  * Register Layout
18089  *
18090  * Bits | Access | Reset | Description
18091  * :-------|:-------|:------|:---------------------------------
18092  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0
18093  *
18094  */
18095 /*
18096  * Field : MPR0
18097  *
18098  * MPR reg[31:0] for second beat
18099  *
18100  * Field Access Macros:
18101  *
18102  */
18103 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0 register field. */
18104 #define ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0_LSB 0
18105 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0 register field. */
18106 #define ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0_MSB 31
18107 /* The width in bits of the ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0 register field. */
18108 #define ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0_WIDTH 32
18109 /* The mask used to set the ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0 register field value. */
18110 #define ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0_SET_MSK 0xffffffff
18111 /* The mask used to clear the ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0 register field value. */
18112 #define ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0_CLR_MSK 0x00000000
18113 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0 register field. */
18114 #define ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0_RESET 0x0
18115 /* Extracts the ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0 field value from a register. */
18116 #define ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0_GET(value) (((value) & 0xffffffff) >> 0)
18117 /* Produces a ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0 register field value suitable for setting the register. */
18118 #define ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0_SET(value) (((value) << 0) & 0xffffffff)
18119 
18120 #ifndef __ASSEMBLY__
18121 /*
18122  * WARNING: The C register and register group struct declarations are provided for
18123  * convenience and illustrative purposes. They should, however, be used with
18124  * caution as the C language standard provides no guarantees about the alignment or
18125  * atomicity of device memory accesses. The recommended practice for coding device
18126  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18127  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18128  * alt_write_dword() functions for 64 bit registers.
18129  *
18130  * The struct declaration for register ALT_MPFE_HMC_ADP_MPR_0BEAT2.
18131  */
18132 struct ALT_MPFE_HMC_ADP_MPR_0BEAT2_s
18133 {
18134  volatile uint32_t MPR0 : 32; /* ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0 */
18135 };
18136 
18137 /* The typedef declaration for register ALT_MPFE_HMC_ADP_MPR_0BEAT2. */
18138 typedef struct ALT_MPFE_HMC_ADP_MPR_0BEAT2_s ALT_MPFE_HMC_ADP_MPR_0BEAT2_t;
18139 #endif /* __ASSEMBLY__ */
18140 
18141 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_0BEAT2 register. */
18142 #define ALT_MPFE_HMC_ADP_MPR_0BEAT2_RESET 0x00000000
18143 /* The byte offset of the ALT_MPFE_HMC_ADP_MPR_0BEAT2 register from the beginning of the component. */
18144 #define ALT_MPFE_HMC_ADP_MPR_0BEAT2_OFST 0x34
18145 
18146 /*
18147  * Register : MPR_1BEAT2
18148  *
18149  * MPR register [63:32] for second beat
18150  *
18151  * Register Layout
18152  *
18153  * Bits | Access | Reset | Description
18154  * :-------|:-------|:------|:----------------------------------
18155  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32
18156  *
18157  */
18158 /*
18159  * Field : MPR32
18160  *
18161  * MPR reg[63:32] for second beat
18162  *
18163  * Field Access Macros:
18164  *
18165  */
18166 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32 register field. */
18167 #define ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32_LSB 0
18168 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32 register field. */
18169 #define ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32_MSB 31
18170 /* The width in bits of the ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32 register field. */
18171 #define ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32_WIDTH 32
18172 /* The mask used to set the ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32 register field value. */
18173 #define ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32_SET_MSK 0xffffffff
18174 /* The mask used to clear the ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32 register field value. */
18175 #define ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32_CLR_MSK 0x00000000
18176 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32 register field. */
18177 #define ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32_RESET 0x0
18178 /* Extracts the ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32 field value from a register. */
18179 #define ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32_GET(value) (((value) & 0xffffffff) >> 0)
18180 /* Produces a ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32 register field value suitable for setting the register. */
18181 #define ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32_SET(value) (((value) << 0) & 0xffffffff)
18182 
18183 #ifndef __ASSEMBLY__
18184 /*
18185  * WARNING: The C register and register group struct declarations are provided for
18186  * convenience and illustrative purposes. They should, however, be used with
18187  * caution as the C language standard provides no guarantees about the alignment or
18188  * atomicity of device memory accesses. The recommended practice for coding device
18189  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18190  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18191  * alt_write_dword() functions for 64 bit registers.
18192  *
18193  * The struct declaration for register ALT_MPFE_HMC_ADP_MPR_1BEAT2.
18194  */
18195 struct ALT_MPFE_HMC_ADP_MPR_1BEAT2_s
18196 {
18197  volatile uint32_t MPR32 : 32; /* ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32 */
18198 };
18199 
18200 /* The typedef declaration for register ALT_MPFE_HMC_ADP_MPR_1BEAT2. */
18201 typedef struct ALT_MPFE_HMC_ADP_MPR_1BEAT2_s ALT_MPFE_HMC_ADP_MPR_1BEAT2_t;
18202 #endif /* __ASSEMBLY__ */
18203 
18204 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_1BEAT2 register. */
18205 #define ALT_MPFE_HMC_ADP_MPR_1BEAT2_RESET 0x00000000
18206 /* The byte offset of the ALT_MPFE_HMC_ADP_MPR_1BEAT2 register from the beginning of the component. */
18207 #define ALT_MPFE_HMC_ADP_MPR_1BEAT2_OFST 0x38
18208 
18209 /*
18210  * Register : MPR_2BEAT2
18211  *
18212  * MPR register [95:64] for second beat
18213  *
18214  * Register Layout
18215  *
18216  * Bits | Access | Reset | Description
18217  * :-------|:-------|:------|:----------------------------------
18218  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64
18219  *
18220  */
18221 /*
18222  * Field : MPR64
18223  *
18224  * MPR reg[95:64] for second beat
18225  *
18226  * Field Access Macros:
18227  *
18228  */
18229 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64 register field. */
18230 #define ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64_LSB 0
18231 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64 register field. */
18232 #define ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64_MSB 31
18233 /* The width in bits of the ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64 register field. */
18234 #define ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64_WIDTH 32
18235 /* The mask used to set the ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64 register field value. */
18236 #define ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64_SET_MSK 0xffffffff
18237 /* The mask used to clear the ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64 register field value. */
18238 #define ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64_CLR_MSK 0x00000000
18239 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64 register field. */
18240 #define ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64_RESET 0x0
18241 /* Extracts the ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64 field value from a register. */
18242 #define ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64_GET(value) (((value) & 0xffffffff) >> 0)
18243 /* Produces a ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64 register field value suitable for setting the register. */
18244 #define ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64_SET(value) (((value) << 0) & 0xffffffff)
18245 
18246 #ifndef __ASSEMBLY__
18247 /*
18248  * WARNING: The C register and register group struct declarations are provided for
18249  * convenience and illustrative purposes. They should, however, be used with
18250  * caution as the C language standard provides no guarantees about the alignment or
18251  * atomicity of device memory accesses. The recommended practice for coding device
18252  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18253  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18254  * alt_write_dword() functions for 64 bit registers.
18255  *
18256  * The struct declaration for register ALT_MPFE_HMC_ADP_MPR_2BEAT2.
18257  */
18258 struct ALT_MPFE_HMC_ADP_MPR_2BEAT2_s
18259 {
18260  volatile uint32_t MPR64 : 32; /* ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64 */
18261 };
18262 
18263 /* The typedef declaration for register ALT_MPFE_HMC_ADP_MPR_2BEAT2. */
18264 typedef struct ALT_MPFE_HMC_ADP_MPR_2BEAT2_s ALT_MPFE_HMC_ADP_MPR_2BEAT2_t;
18265 #endif /* __ASSEMBLY__ */
18266 
18267 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_2BEAT2 register. */
18268 #define ALT_MPFE_HMC_ADP_MPR_2BEAT2_RESET 0x00000000
18269 /* The byte offset of the ALT_MPFE_HMC_ADP_MPR_2BEAT2 register from the beginning of the component. */
18270 #define ALT_MPFE_HMC_ADP_MPR_2BEAT2_OFST 0x3c
18271 
18272 /*
18273  * Register : MPR_3BEAT2
18274  *
18275  * MPR register [127:96] for second beat
18276  *
18277  * Register Layout
18278  *
18279  * Bits | Access | Reset | Description
18280  * :-------|:-------|:------|:----------------------------------
18281  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96
18282  *
18283  */
18284 /*
18285  * Field : MPR96
18286  *
18287  * MPR reg[127:96] for second beat
18288  *
18289  * Field Access Macros:
18290  *
18291  */
18292 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96 register field. */
18293 #define ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96_LSB 0
18294 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96 register field. */
18295 #define ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96_MSB 31
18296 /* The width in bits of the ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96 register field. */
18297 #define ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96_WIDTH 32
18298 /* The mask used to set the ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96 register field value. */
18299 #define ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96_SET_MSK 0xffffffff
18300 /* The mask used to clear the ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96 register field value. */
18301 #define ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96_CLR_MSK 0x00000000
18302 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96 register field. */
18303 #define ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96_RESET 0x0
18304 /* Extracts the ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96 field value from a register. */
18305 #define ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96_GET(value) (((value) & 0xffffffff) >> 0)
18306 /* Produces a ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96 register field value suitable for setting the register. */
18307 #define ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96_SET(value) (((value) << 0) & 0xffffffff)
18308 
18309 #ifndef __ASSEMBLY__
18310 /*
18311  * WARNING: The C register and register group struct declarations are provided for
18312  * convenience and illustrative purposes. They should, however, be used with
18313  * caution as the C language standard provides no guarantees about the alignment or
18314  * atomicity of device memory accesses. The recommended practice for coding device
18315  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18316  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18317  * alt_write_dword() functions for 64 bit registers.
18318  *
18319  * The struct declaration for register ALT_MPFE_HMC_ADP_MPR_3BEAT2.
18320  */
18321 struct ALT_MPFE_HMC_ADP_MPR_3BEAT2_s
18322 {
18323  volatile uint32_t MPR96 : 32; /* ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96 */
18324 };
18325 
18326 /* The typedef declaration for register ALT_MPFE_HMC_ADP_MPR_3BEAT2. */
18327 typedef struct ALT_MPFE_HMC_ADP_MPR_3BEAT2_s ALT_MPFE_HMC_ADP_MPR_3BEAT2_t;
18328 #endif /* __ASSEMBLY__ */
18329 
18330 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_3BEAT2 register. */
18331 #define ALT_MPFE_HMC_ADP_MPR_3BEAT2_RESET 0x00000000
18332 /* The byte offset of the ALT_MPFE_HMC_ADP_MPR_3BEAT2 register from the beginning of the component. */
18333 #define ALT_MPFE_HMC_ADP_MPR_3BEAT2_OFST 0x40
18334 
18335 /*
18336  * Register : MPR_4BEAT2
18337  *
18338  * MPR register [159:128] for second beat
18339  *
18340  * Register Layout
18341  *
18342  * Bits | Access | Reset | Description
18343  * :-------|:-------|:------|:-----------------------------------
18344  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128
18345  *
18346  */
18347 /*
18348  * Field : MPR128
18349  *
18350  * MPR reg[159:128] for second beat
18351  *
18352  * Field Access Macros:
18353  *
18354  */
18355 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128 register field. */
18356 #define ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128_LSB 0
18357 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128 register field. */
18358 #define ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128_MSB 31
18359 /* The width in bits of the ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128 register field. */
18360 #define ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128_WIDTH 32
18361 /* The mask used to set the ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128 register field value. */
18362 #define ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128_SET_MSK 0xffffffff
18363 /* The mask used to clear the ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128 register field value. */
18364 #define ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128_CLR_MSK 0x00000000
18365 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128 register field. */
18366 #define ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128_RESET 0x0
18367 /* Extracts the ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128 field value from a register. */
18368 #define ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128_GET(value) (((value) & 0xffffffff) >> 0)
18369 /* Produces a ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128 register field value suitable for setting the register. */
18370 #define ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128_SET(value) (((value) << 0) & 0xffffffff)
18371 
18372 #ifndef __ASSEMBLY__
18373 /*
18374  * WARNING: The C register and register group struct declarations are provided for
18375  * convenience and illustrative purposes. They should, however, be used with
18376  * caution as the C language standard provides no guarantees about the alignment or
18377  * atomicity of device memory accesses. The recommended practice for coding device
18378  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18379  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18380  * alt_write_dword() functions for 64 bit registers.
18381  *
18382  * The struct declaration for register ALT_MPFE_HMC_ADP_MPR_4BEAT2.
18383  */
18384 struct ALT_MPFE_HMC_ADP_MPR_4BEAT2_s
18385 {
18386  volatile uint32_t MPR128 : 32; /* ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128 */
18387 };
18388 
18389 /* The typedef declaration for register ALT_MPFE_HMC_ADP_MPR_4BEAT2. */
18390 typedef struct ALT_MPFE_HMC_ADP_MPR_4BEAT2_s ALT_MPFE_HMC_ADP_MPR_4BEAT2_t;
18391 #endif /* __ASSEMBLY__ */
18392 
18393 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_4BEAT2 register. */
18394 #define ALT_MPFE_HMC_ADP_MPR_4BEAT2_RESET 0x00000000
18395 /* The byte offset of the ALT_MPFE_HMC_ADP_MPR_4BEAT2 register from the beginning of the component. */
18396 #define ALT_MPFE_HMC_ADP_MPR_4BEAT2_OFST 0x44
18397 
18398 /*
18399  * Register : MPR_5BEAT2
18400  *
18401  * MPR register [191:160] for second beat
18402  *
18403  * Register Layout
18404  *
18405  * Bits | Access | Reset | Description
18406  * :-------|:-------|:------|:-----------------------------------
18407  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160
18408  *
18409  */
18410 /*
18411  * Field : MPR160
18412  *
18413  * MPR reg[191:160] for second beat
18414  *
18415  * Field Access Macros:
18416  *
18417  */
18418 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160 register field. */
18419 #define ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160_LSB 0
18420 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160 register field. */
18421 #define ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160_MSB 31
18422 /* The width in bits of the ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160 register field. */
18423 #define ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160_WIDTH 32
18424 /* The mask used to set the ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160 register field value. */
18425 #define ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160_SET_MSK 0xffffffff
18426 /* The mask used to clear the ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160 register field value. */
18427 #define ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160_CLR_MSK 0x00000000
18428 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160 register field. */
18429 #define ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160_RESET 0x0
18430 /* Extracts the ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160 field value from a register. */
18431 #define ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160_GET(value) (((value) & 0xffffffff) >> 0)
18432 /* Produces a ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160 register field value suitable for setting the register. */
18433 #define ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160_SET(value) (((value) << 0) & 0xffffffff)
18434 
18435 #ifndef __ASSEMBLY__
18436 /*
18437  * WARNING: The C register and register group struct declarations are provided for
18438  * convenience and illustrative purposes. They should, however, be used with
18439  * caution as the C language standard provides no guarantees about the alignment or
18440  * atomicity of device memory accesses. The recommended practice for coding device
18441  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18442  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18443  * alt_write_dword() functions for 64 bit registers.
18444  *
18445  * The struct declaration for register ALT_MPFE_HMC_ADP_MPR_5BEAT2.
18446  */
18447 struct ALT_MPFE_HMC_ADP_MPR_5BEAT2_s
18448 {
18449  volatile uint32_t MPR160 : 32; /* ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160 */
18450 };
18451 
18452 /* The typedef declaration for register ALT_MPFE_HMC_ADP_MPR_5BEAT2. */
18453 typedef struct ALT_MPFE_HMC_ADP_MPR_5BEAT2_s ALT_MPFE_HMC_ADP_MPR_5BEAT2_t;
18454 #endif /* __ASSEMBLY__ */
18455 
18456 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_5BEAT2 register. */
18457 #define ALT_MPFE_HMC_ADP_MPR_5BEAT2_RESET 0x00000000
18458 /* The byte offset of the ALT_MPFE_HMC_ADP_MPR_5BEAT2 register from the beginning of the component. */
18459 #define ALT_MPFE_HMC_ADP_MPR_5BEAT2_OFST 0x48
18460 
18461 /*
18462  * Register : MPR_6BEAT2
18463  *
18464  * MPR register [223:192] for second beat
18465  *
18466  * Register Layout
18467  *
18468  * Bits | Access | Reset | Description
18469  * :-------|:-------|:------|:-----------------------------------
18470  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192
18471  *
18472  */
18473 /*
18474  * Field : MPR192
18475  *
18476  * MPR reg[223:192] for second beat
18477  *
18478  * Field Access Macros:
18479  *
18480  */
18481 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192 register field. */
18482 #define ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192_LSB 0
18483 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192 register field. */
18484 #define ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192_MSB 31
18485 /* The width in bits of the ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192 register field. */
18486 #define ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192_WIDTH 32
18487 /* The mask used to set the ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192 register field value. */
18488 #define ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192_SET_MSK 0xffffffff
18489 /* The mask used to clear the ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192 register field value. */
18490 #define ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192_CLR_MSK 0x00000000
18491 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192 register field. */
18492 #define ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192_RESET 0x0
18493 /* Extracts the ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192 field value from a register. */
18494 #define ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192_GET(value) (((value) & 0xffffffff) >> 0)
18495 /* Produces a ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192 register field value suitable for setting the register. */
18496 #define ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192_SET(value) (((value) << 0) & 0xffffffff)
18497 
18498 #ifndef __ASSEMBLY__
18499 /*
18500  * WARNING: The C register and register group struct declarations are provided for
18501  * convenience and illustrative purposes. They should, however, be used with
18502  * caution as the C language standard provides no guarantees about the alignment or
18503  * atomicity of device memory accesses. The recommended practice for coding device
18504  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18505  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18506  * alt_write_dword() functions for 64 bit registers.
18507  *
18508  * The struct declaration for register ALT_MPFE_HMC_ADP_MPR_6BEAT2.
18509  */
18510 struct ALT_MPFE_HMC_ADP_MPR_6BEAT2_s
18511 {
18512  volatile uint32_t MPR192 : 32; /* ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192 */
18513 };
18514 
18515 /* The typedef declaration for register ALT_MPFE_HMC_ADP_MPR_6BEAT2. */
18516 typedef struct ALT_MPFE_HMC_ADP_MPR_6BEAT2_s ALT_MPFE_HMC_ADP_MPR_6BEAT2_t;
18517 #endif /* __ASSEMBLY__ */
18518 
18519 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_6BEAT2 register. */
18520 #define ALT_MPFE_HMC_ADP_MPR_6BEAT2_RESET 0x00000000
18521 /* The byte offset of the ALT_MPFE_HMC_ADP_MPR_6BEAT2 register from the beginning of the component. */
18522 #define ALT_MPFE_HMC_ADP_MPR_6BEAT2_OFST 0x4c
18523 
18524 /*
18525  * Register : MPR_7BEAT2
18526  *
18527  * MPR register [255:224] for second beat
18528  *
18529  * Register Layout
18530  *
18531  * Bits | Access | Reset | Description
18532  * :-------|:-------|:------|:-----------------------------------
18533  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224
18534  *
18535  */
18536 /*
18537  * Field : MPR224
18538  *
18539  * MPR reg[255:224] for second beat
18540  *
18541  * Field Access Macros:
18542  *
18543  */
18544 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224 register field. */
18545 #define ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224_LSB 0
18546 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224 register field. */
18547 #define ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224_MSB 31
18548 /* The width in bits of the ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224 register field. */
18549 #define ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224_WIDTH 32
18550 /* The mask used to set the ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224 register field value. */
18551 #define ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224_SET_MSK 0xffffffff
18552 /* The mask used to clear the ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224 register field value. */
18553 #define ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224_CLR_MSK 0x00000000
18554 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224 register field. */
18555 #define ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224_RESET 0x0
18556 /* Extracts the ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224 field value from a register. */
18557 #define ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224_GET(value) (((value) & 0xffffffff) >> 0)
18558 /* Produces a ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224 register field value suitable for setting the register. */
18559 #define ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224_SET(value) (((value) << 0) & 0xffffffff)
18560 
18561 #ifndef __ASSEMBLY__
18562 /*
18563  * WARNING: The C register and register group struct declarations are provided for
18564  * convenience and illustrative purposes. They should, however, be used with
18565  * caution as the C language standard provides no guarantees about the alignment or
18566  * atomicity of device memory accesses. The recommended practice for coding device
18567  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18568  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18569  * alt_write_dword() functions for 64 bit registers.
18570  *
18571  * The struct declaration for register ALT_MPFE_HMC_ADP_MPR_7BEAT2.
18572  */
18573 struct ALT_MPFE_HMC_ADP_MPR_7BEAT2_s
18574 {
18575  volatile uint32_t MPR224 : 32; /* ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224 */
18576 };
18577 
18578 /* The typedef declaration for register ALT_MPFE_HMC_ADP_MPR_7BEAT2. */
18579 typedef struct ALT_MPFE_HMC_ADP_MPR_7BEAT2_s ALT_MPFE_HMC_ADP_MPR_7BEAT2_t;
18580 #endif /* __ASSEMBLY__ */
18581 
18582 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_7BEAT2 register. */
18583 #define ALT_MPFE_HMC_ADP_MPR_7BEAT2_RESET 0x00000000
18584 /* The byte offset of the ALT_MPFE_HMC_ADP_MPR_7BEAT2 register from the beginning of the component. */
18585 #define ALT_MPFE_HMC_ADP_MPR_7BEAT2_OFST 0x50
18586 
18587 /*
18588  * Register : MPR_8BEAT2
18589  *
18590  * MPR register [287:256] for second beat
18591  *
18592  * Register Layout
18593  *
18594  * Bits | Access | Reset | Description
18595  * :-------|:-------|:------|:-----------------------------------
18596  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256
18597  *
18598  */
18599 /*
18600  * Field : MPR256
18601  *
18602  * MPR reg[287:256] for second beat
18603  *
18604  * Field Access Macros:
18605  *
18606  */
18607 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256 register field. */
18608 #define ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256_LSB 0
18609 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256 register field. */
18610 #define ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256_MSB 31
18611 /* The width in bits of the ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256 register field. */
18612 #define ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256_WIDTH 32
18613 /* The mask used to set the ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256 register field value. */
18614 #define ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256_SET_MSK 0xffffffff
18615 /* The mask used to clear the ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256 register field value. */
18616 #define ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256_CLR_MSK 0x00000000
18617 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256 register field. */
18618 #define ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256_RESET 0x0
18619 /* Extracts the ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256 field value from a register. */
18620 #define ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256_GET(value) (((value) & 0xffffffff) >> 0)
18621 /* Produces a ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256 register field value suitable for setting the register. */
18622 #define ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256_SET(value) (((value) << 0) & 0xffffffff)
18623 
18624 #ifndef __ASSEMBLY__
18625 /*
18626  * WARNING: The C register and register group struct declarations are provided for
18627  * convenience and illustrative purposes. They should, however, be used with
18628  * caution as the C language standard provides no guarantees about the alignment or
18629  * atomicity of device memory accesses. The recommended practice for coding device
18630  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18631  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18632  * alt_write_dword() functions for 64 bit registers.
18633  *
18634  * The struct declaration for register ALT_MPFE_HMC_ADP_MPR_8BEAT2.
18635  */
18636 struct ALT_MPFE_HMC_ADP_MPR_8BEAT2_s
18637 {
18638  volatile uint32_t MPR256 : 32; /* ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256 */
18639 };
18640 
18641 /* The typedef declaration for register ALT_MPFE_HMC_ADP_MPR_8BEAT2. */
18642 typedef struct ALT_MPFE_HMC_ADP_MPR_8BEAT2_s ALT_MPFE_HMC_ADP_MPR_8BEAT2_t;
18643 #endif /* __ASSEMBLY__ */
18644 
18645 /* The reset value of the ALT_MPFE_HMC_ADP_MPR_8BEAT2 register. */
18646 #define ALT_MPFE_HMC_ADP_MPR_8BEAT2_RESET 0x00000000
18647 /* The byte offset of the ALT_MPFE_HMC_ADP_MPR_8BEAT2 register from the beginning of the component. */
18648 #define ALT_MPFE_HMC_ADP_MPR_8BEAT2_OFST 0x54
18649 
18650 /*
18651  * Register : AUTO_PRECHARGE
18652  *
18653  * auto-precharge bit
18654  *
18655  * Register Layout
18656  *
18657  * Bits | Access | Reset | Description
18658  * :-------|:-------|:------|:-------------------------------------
18659  * [0] | RW | 0x0 | ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL
18660  * [31:1] | ??? | 0x0 | *UNDEFINED*
18661  *
18662  */
18663 /*
18664  * Field : CTRL
18665  *
18666  * Drive bit 43 of core2ctl_cmd_data0 bus to HMC.
18667  *
18668  * 1'b0: Default value after reset. Auto-precharge request to HMC is disabled
18669  *
18670  * 1'b1: Every read/write command sent to HMC has the auto-precharge bit enabled
18671  *
18672  * Field Enumeration Values:
18673  *
18674  * Enum | Value | Description
18675  * :-----------------------------------------------|:------|:------------
18676  * ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL_E_DISABLE | 0x0 |
18677  * ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL_E_ENABLE | 0x1 |
18678  *
18679  * Field Access Macros:
18680  *
18681  */
18682 /*
18683  * Enumerated value for register field ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL
18684  *
18685  */
18686 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL_E_DISABLE 0x0
18687 /*
18688  * Enumerated value for register field ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL
18689  *
18690  */
18691 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL_E_ENABLE 0x1
18692 
18693 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL register field. */
18694 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL_LSB 0
18695 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL register field. */
18696 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL_MSB 0
18697 /* The width in bits of the ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL register field. */
18698 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL_WIDTH 1
18699 /* The mask used to set the ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL register field value. */
18700 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL_SET_MSK 0x00000001
18701 /* The mask used to clear the ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL register field value. */
18702 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL_CLR_MSK 0xfffffffe
18703 /* The reset value of the ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL register field. */
18704 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL_RESET 0x0
18705 /* Extracts the ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL field value from a register. */
18706 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL_GET(value) (((value) & 0x00000001) >> 0)
18707 /* Produces a ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL register field value suitable for setting the register. */
18708 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL_SET(value) (((value) << 0) & 0x00000001)
18709 
18710 #ifndef __ASSEMBLY__
18711 /*
18712  * WARNING: The C register and register group struct declarations are provided for
18713  * convenience and illustrative purposes. They should, however, be used with
18714  * caution as the C language standard provides no guarantees about the alignment or
18715  * atomicity of device memory accesses. The recommended practice for coding device
18716  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18717  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18718  * alt_write_dword() functions for 64 bit registers.
18719  *
18720  * The struct declaration for register ALT_MPFE_HMC_ADP_AUTO_PRECHARGE.
18721  */
18722 struct ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_s
18723 {
18724  volatile uint32_t CTRL : 1; /* ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL */
18725  uint32_t : 31; /* *UNDEFINED* */
18726 };
18727 
18728 /* The typedef declaration for register ALT_MPFE_HMC_ADP_AUTO_PRECHARGE. */
18729 typedef struct ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_s ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_t;
18730 #endif /* __ASSEMBLY__ */
18731 
18732 /* The reset value of the ALT_MPFE_HMC_ADP_AUTO_PRECHARGE register. */
18733 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_RESET 0x00000000
18734 /* The byte offset of the ALT_MPFE_HMC_ADP_AUTO_PRECHARGE register from the beginning of the component. */
18735 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_OFST 0x60
18736 
18737 /*
18738  * Register : DRAMADDRWIDTH
18739  *
18740  * DRAM address bit width
18741  *
18742  * Register Layout
18743  *
18744  * Bits | Access | Reset | Description
18745  * :--------|:-------|:------|:---------------------------------------------------------
18746  * [4:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH
18747  * [9:5] | RW | 0x0 | ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH
18748  * [13:10] | RW | 0x0 | ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH
18749  * [15:14] | RW | 0x0 | ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH
18750  * [18:16] | RW | 0x0 | ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH
18751  * [31:19] | ??? | 0x0 | *UNDEFINED*
18752  *
18753  */
18754 /*
18755  * Field : CFG_COL_ADDR_WIDTH
18756  *
18757  * DRAM Column Address Bits
18758  *
18759  * The number of column address bits for the memory devices in your memory
18760  * interface.
18761  *
18762  * Field Access Macros:
18763  *
18764  */
18765 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH register field. */
18766 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH_LSB 0
18767 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH register field. */
18768 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH_MSB 4
18769 /* The width in bits of the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH register field. */
18770 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH_WIDTH 5
18771 /* The mask used to set the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH register field value. */
18772 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH_SET_MSK 0x0000001f
18773 /* The mask used to clear the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH register field value. */
18774 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH_CLR_MSK 0xffffffe0
18775 /* The reset value of the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH register field. */
18776 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH_RESET 0x0
18777 /* Extracts the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH field value from a register. */
18778 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH_GET(value) (((value) & 0x0000001f) >> 0)
18779 /* Produces a ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH register field value suitable for setting the register. */
18780 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH_SET(value) (((value) << 0) & 0x0000001f)
18781 
18782 /*
18783  * Field : CFG_ROW_ADDR_WIDTH
18784  *
18785  * DRAM Row Address Bits
18786  *
18787  * The number of row address bits for the memory devices in your memory interface.
18788  *
18789  * Field Access Macros:
18790  *
18791  */
18792 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH register field. */
18793 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH_LSB 5
18794 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH register field. */
18795 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH_MSB 9
18796 /* The width in bits of the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH register field. */
18797 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH_WIDTH 5
18798 /* The mask used to set the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH register field value. */
18799 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH_SET_MSK 0x000003e0
18800 /* The mask used to clear the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH register field value. */
18801 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH_CLR_MSK 0xfffffc1f
18802 /* The reset value of the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH register field. */
18803 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH_RESET 0x0
18804 /* Extracts the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH field value from a register. */
18805 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH_GET(value) (((value) & 0x000003e0) >> 5)
18806 /* Produces a ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH register field value suitable for setting the register. */
18807 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH_SET(value) (((value) << 5) & 0x000003e0)
18808 
18809 /*
18810  * Field : CFG_BANK_ADDR_WIDTH
18811  *
18812  * DRAM Bank Address Bits
18813  *
18814  * The number of bank address bits for the memory devices in your memory interface.
18815  *
18816  * Field Access Macros:
18817  *
18818  */
18819 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH register field. */
18820 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH_LSB 10
18821 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH register field. */
18822 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH_MSB 13
18823 /* The width in bits of the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH register field. */
18824 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH_WIDTH 4
18825 /* The mask used to set the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH register field value. */
18826 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH_SET_MSK 0x00003c00
18827 /* The mask used to clear the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH register field value. */
18828 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH_CLR_MSK 0xffffc3ff
18829 /* The reset value of the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH register field. */
18830 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH_RESET 0x0
18831 /* Extracts the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH field value from a register. */
18832 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH_GET(value) (((value) & 0x00003c00) >> 10)
18833 /* Produces a ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH register field value suitable for setting the register. */
18834 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH_SET(value) (((value) << 10) & 0x00003c00)
18835 
18836 /*
18837  * Field : CFG_BANK_GROUP_ADDR_WIDTH
18838  *
18839  * DRAM Bank Group Address Bits
18840  *
18841  * The number of bank group address bits for t he memory devices in your memory
18842  * interface.
18843  *
18844  * Field Access Macros:
18845  *
18846  */
18847 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH register field. */
18848 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH_LSB 14
18849 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH register field. */
18850 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH_MSB 15
18851 /* The width in bits of the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH register field. */
18852 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH_WIDTH 2
18853 /* The mask used to set the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH register field value. */
18854 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH_SET_MSK 0x0000c000
18855 /* The mask used to clear the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH register field value. */
18856 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH_CLR_MSK 0xffff3fff
18857 /* The reset value of the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH register field. */
18858 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH_RESET 0x0
18859 /* Extracts the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH field value from a register. */
18860 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH_GET(value) (((value) & 0x0000c000) >> 14)
18861 /* Produces a ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH register field value suitable for setting the register. */
18862 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH_SET(value) (((value) << 14) & 0x0000c000)
18863 
18864 /*
18865  * Field : CFG_CS_ADDR_WIDTH
18866  *
18867  * Chip Address Bits
18868  *
18869  * The number of chip select address bits for the memory devices in your memory
18870  * interface.
18871  *
18872  * Field Access Macros:
18873  *
18874  */
18875 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH register field. */
18876 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH_LSB 16
18877 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH register field. */
18878 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH_MSB 18
18879 /* The width in bits of the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH register field. */
18880 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH_WIDTH 3
18881 /* The mask used to set the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH register field value. */
18882 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH_SET_MSK 0x00070000
18883 /* The mask used to clear the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH register field value. */
18884 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH_CLR_MSK 0xfff8ffff
18885 /* The reset value of the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH register field. */
18886 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH_RESET 0x0
18887 /* Extracts the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH field value from a register. */
18888 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH_GET(value) (((value) & 0x00070000) >> 16)
18889 /* Produces a ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH register field value suitable for setting the register. */
18890 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH_SET(value) (((value) << 16) & 0x00070000)
18891 
18892 #ifndef __ASSEMBLY__
18893 /*
18894  * WARNING: The C register and register group struct declarations are provided for
18895  * convenience and illustrative purposes. They should, however, be used with
18896  * caution as the C language standard provides no guarantees about the alignment or
18897  * atomicity of device memory accesses. The recommended practice for coding device
18898  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18899  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18900  * alt_write_dword() functions for 64 bit registers.
18901  *
18902  * The struct declaration for register ALT_MPFE_HMC_ADP_DRAMADDRWIDTH.
18903  */
18904 struct ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_s
18905 {
18906  volatile uint32_t CFG_COL_ADDR_WIDTH : 5; /* ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH */
18907  volatile uint32_t CFG_ROW_ADDR_WIDTH : 5; /* ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH */
18908  volatile uint32_t CFG_BANK_ADDR_WIDTH : 4; /* ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH */
18909  volatile uint32_t CFG_BANK_GROUP_ADDR_WIDTH : 2; /* ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH */
18910  volatile uint32_t CFG_CS_ADDR_WIDTH : 3; /* ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH */
18911  uint32_t : 13; /* *UNDEFINED* */
18912 };
18913 
18914 /* The typedef declaration for register ALT_MPFE_HMC_ADP_DRAMADDRWIDTH. */
18915 typedef struct ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_s ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_t;
18916 #endif /* __ASSEMBLY__ */
18917 
18918 /* The reset value of the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH register. */
18919 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_RESET 0x00000000
18920 /* The byte offset of the ALT_MPFE_HMC_ADP_DRAMADDRWIDTH register from the beginning of the component. */
18921 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_OFST 0xe0
18922 
18923 /*
18924  * Register : ECCCTRL1
18925  *
18926  * ECC control 1.
18927  *
18928  * This bit is used to set the initialize the memory and ecc to a known value
18929  *
18930  * Register Layout
18931  *
18932  * Bits | Access | Reset | Description
18933  * :--------|:-------|:------|:-----------------------------------------
18934  * [0] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN
18935  * [7:1] | ??? | 0x0 | *UNDEFINED*
18936  * [8] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST
18937  * [15:9] | ??? | 0x0 | *UNDEFINED*
18938  * [16] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST
18939  * [31:17] | ??? | 0x0 | *UNDEFINED*
18940  *
18941  */
18942 /*
18943  * Field : ECC_EN
18944  *
18945  * Enable for the ECC detection and correction logic.
18946  *
18947  * 1'b0:ECC block is disabled. Default value after reset.
18948  *
18949  * 1'b1: ECC block is enabled. Every RAM access will verify the data and generate
18950  * any necessary error requests.
18951  *
18952  * Field Enumeration Values:
18953  *
18954  * Enum | Value | Description
18955  * :-------------------------------------------|:------|:------------
18956  * ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_E_DISABLE | 0x0 |
18957  * ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_E_ENABLE | 0x1 |
18958  *
18959  * Field Access Macros:
18960  *
18961  */
18962 /*
18963  * Enumerated value for register field ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN
18964  *
18965  */
18966 #define ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_E_DISABLE 0x0
18967 /*
18968  * Enumerated value for register field ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN
18969  *
18970  */
18971 #define ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_E_ENABLE 0x1
18972 
18973 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN register field. */
18974 #define ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_LSB 0
18975 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN register field. */
18976 #define ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_MSB 0
18977 /* The width in bits of the ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN register field. */
18978 #define ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_WIDTH 1
18979 /* The mask used to set the ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN register field value. */
18980 #define ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK 0x00000001
18981 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN register field value. */
18982 #define ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_CLR_MSK 0xfffffffe
18983 /* The reset value of the ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN register field. */
18984 #define ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_RESET 0x0
18985 /* Extracts the ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN field value from a register. */
18986 #define ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
18987 /* Produces a ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN register field value suitable for setting the register. */
18988 #define ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
18989 
18990 /*
18991  * Field : CNT_RST
18992  *
18993  * Reset of internal counter.
18994  *
18995  * 1'b0: No effect on internal counter. Dafault value after reset
18996  *
18997  * 1'b1: Reset the internal counter to zero
18998  *
18999  * Field Enumeration Values:
19000  *
19001  * Enum | Value | Description
19002  * :------------------------------------------|:------|:------------
19003  * ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_E_STAY | 0x0 |
19004  * ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_E_RESET | 0x1 |
19005  *
19006  * Field Access Macros:
19007  *
19008  */
19009 /*
19010  * Enumerated value for register field ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST
19011  *
19012  */
19013 #define ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_E_STAY 0x0
19014 /*
19015  * Enumerated value for register field ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST
19016  *
19017  */
19018 #define ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_E_RESET 0x1
19019 
19020 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST register field. */
19021 #define ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_LSB 8
19022 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST register field. */
19023 #define ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_MSB 8
19024 /* The width in bits of the ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST register field. */
19025 #define ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_WIDTH 1
19026 /* The mask used to set the ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST register field value. */
19027 #define ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK 0x00000100
19028 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST register field value. */
19029 #define ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_CLR_MSK 0xfffffeff
19030 /* The reset value of the ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST register field. */
19031 #define ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_RESET 0x0
19032 /* Extracts the ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST field value from a register. */
19033 #define ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_GET(value) (((value) & 0x00000100) >> 8)
19034 /* Produces a ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST register field value suitable for setting the register. */
19035 #define ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET(value) (((value) << 8) & 0x00000100)
19036 
19037 /*
19038  * Field : AUTOWB_CNT_RST
19039  *
19040  * Reset the autoWB internal counter to zero.
19041  *
19042  * 1'b0 : No effect on autoWB internal counter. Default value after reset
19043  *
19044  * 1'b1 : Reset the autoWB internal counter to zero
19045  *
19046  * Field Enumeration Values:
19047  *
19048  * Enum | Value | Description
19049  * :-------------------------------------------------|:------|:------------
19050  * ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_E_STAY | 0x0 |
19051  * ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_E_RESET | 0x1 |
19052  *
19053  * Field Access Macros:
19054  *
19055  */
19056 /*
19057  * Enumerated value for register field ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST
19058  *
19059  */
19060 #define ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_E_STAY 0x0
19061 /*
19062  * Enumerated value for register field ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST
19063  *
19064  */
19065 #define ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_E_RESET 0x1
19066 
19067 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST register field. */
19068 #define ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_LSB 16
19069 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST register field. */
19070 #define ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_MSB 16
19071 /* The width in bits of the ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST register field. */
19072 #define ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_WIDTH 1
19073 /* The mask used to set the ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST register field value. */
19074 #define ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK 0x00010000
19075 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST register field value. */
19076 #define ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_CLR_MSK 0xfffeffff
19077 /* The reset value of the ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST register field. */
19078 #define ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_RESET 0x0
19079 /* Extracts the ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST field value from a register. */
19080 #define ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_GET(value) (((value) & 0x00010000) >> 16)
19081 /* Produces a ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST register field value suitable for setting the register. */
19082 #define ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET(value) (((value) << 16) & 0x00010000)
19083 
19084 #ifndef __ASSEMBLY__
19085 /*
19086  * WARNING: The C register and register group struct declarations are provided for
19087  * convenience and illustrative purposes. They should, however, be used with
19088  * caution as the C language standard provides no guarantees about the alignment or
19089  * atomicity of device memory accesses. The recommended practice for coding device
19090  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
19091  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
19092  * alt_write_dword() functions for 64 bit registers.
19093  *
19094  * The struct declaration for register ALT_MPFE_HMC_ADP_ECCCTRL1.
19095  */
19096 struct ALT_MPFE_HMC_ADP_ECCCTRL1_s
19097 {
19098  volatile uint32_t ECC_EN : 1; /* ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN */
19099  uint32_t : 7; /* *UNDEFINED* */
19100  volatile uint32_t CNT_RST : 1; /* ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST */
19101  uint32_t : 7; /* *UNDEFINED* */
19102  volatile uint32_t AUTOWB_CNT_RST : 1; /* ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST */
19103  uint32_t : 15; /* *UNDEFINED* */
19104 };
19105 
19106 /* The typedef declaration for register ALT_MPFE_HMC_ADP_ECCCTRL1. */
19107 typedef struct ALT_MPFE_HMC_ADP_ECCCTRL1_s ALT_MPFE_HMC_ADP_ECCCTRL1_t;
19108 #endif /* __ASSEMBLY__ */
19109 
19110 /* The reset value of the ALT_MPFE_HMC_ADP_ECCCTRL1 register. */
19111 #define ALT_MPFE_HMC_ADP_ECCCTRL1_RESET 0x00000000
19112 /* The byte offset of the ALT_MPFE_HMC_ADP_ECCCTRL1 register from the beginning of the component. */
19113 #define ALT_MPFE_HMC_ADP_ECCCTRL1_OFST 0x100
19114 
19115 /*
19116  * Register : ECCCTRL2
19117  *
19118  * ECC control 2.
19119  *
19120  * This bit is used to set the initialize the memory and ecc to a known value
19121  *
19122  * Register Layout
19123  *
19124  * Bits | Access | Reset | Description
19125  * :--------|:-------|:------|:-----------------------------------------
19126  * [0] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN
19127  * [7:1] | ??? | 0x0 | *UNDEFINED*
19128  * [8] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN
19129  * [15:9] | ??? | 0x0 | *UNDEFINED*
19130  * [16] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN
19131  * [31:17] | ??? | 0x0 | *UNDEFINED*
19132  *
19133  */
19134 /*
19135  * Field : AUTOWB_EN
19136  *
19137  * Enable auto write back correction feature.
19138  *
19139  * When serr is detected on outgoing reads, HMC adaptor schedules the corrected
19140  * data and ECC to the written to the DDR memory. This bit enables auto correction
19141  * of DDR memory.
19142  *
19143  * 1'b0: disable auto WB drop correction. Default value after reset.
19144  *
19145  * 1'b1: enable auto WB drop correction.
19146  *
19147  * Field Enumeration Values:
19148  *
19149  * Enum | Value | Description
19150  * :----------------------------------------------|:------|:------------
19151  * ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_E_DISABLE | 0x0 |
19152  * ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_E_ENABLE | 0x1 |
19153  *
19154  * Field Access Macros:
19155  *
19156  */
19157 /*
19158  * Enumerated value for register field ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN
19159  *
19160  */
19161 #define ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_E_DISABLE 0x0
19162 /*
19163  * Enumerated value for register field ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN
19164  *
19165  */
19166 #define ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_E_ENABLE 0x1
19167 
19168 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN register field. */
19169 #define ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_LSB 0
19170 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN register field. */
19171 #define ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_MSB 0
19172 /* The width in bits of the ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN register field. */
19173 #define ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_WIDTH 1
19174 /* The mask used to set the ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN register field value. */
19175 #define ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_SET_MSK 0x00000001
19176 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN register field value. */
19177 #define ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_CLR_MSK 0xfffffffe
19178 /* The reset value of the ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN register field. */
19179 #define ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_RESET 0x0
19180 /* Extracts the ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN field value from a register. */
19181 #define ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_GET(value) (((value) & 0x00000001) >> 0)
19182 /* Produces a ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN register field value suitable for setting the register. */
19183 #define ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_SET(value) (((value) << 0) & 0x00000001)
19184 
19185 /*
19186  * Field : RMW_EN
19187  *
19188  * Enable read modify write logic.
19189  *
19190  * When ECC is enabled and sub word accesses require correct ECC to be calculated,
19191  * this bit should be enabled. RMW_EN bit should be disabled when ECC_EN is
19192  * disabled.
19193  *
19194  * 1'b0: disable RMW logic. Default value after reset.
19195  *
19196  * 1'b1: enable RMW logic.
19197  *
19198  * Field Enumeration Values:
19199  *
19200  * Enum | Value | Description
19201  * :-------------------------------------------|:------|:------------
19202  * ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_E_DISABLE | 0x0 |
19203  * ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_E_ENABLE | 0x1 |
19204  *
19205  * Field Access Macros:
19206  *
19207  */
19208 /*
19209  * Enumerated value for register field ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN
19210  *
19211  */
19212 #define ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_E_DISABLE 0x0
19213 /*
19214  * Enumerated value for register field ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN
19215  *
19216  */
19217 #define ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_E_ENABLE 0x1
19218 
19219 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN register field. */
19220 #define ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_LSB 8
19221 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN register field. */
19222 #define ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_MSB 8
19223 /* The width in bits of the ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN register field. */
19224 #define ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_WIDTH 1
19225 /* The mask used to set the ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN register field value. */
19226 #define ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_SET_MSK 0x00000100
19227 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN register field value. */
19228 #define ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_CLR_MSK 0xfffffeff
19229 /* The reset value of the ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN register field. */
19230 #define ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_RESET 0x0
19231 /* Extracts the ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN field value from a register. */
19232 #define ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_GET(value) (((value) & 0x00000100) >> 8)
19233 /* Produces a ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN register field value suitable for setting the register. */
19234 #define ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_SET(value) (((value) << 8) & 0x00000100)
19235 
19236 /*
19237  * Field : OVRW_RB_ECC_EN
19238  *
19239  * Overwrite the read-back ecc code during RMW process if DBE is detected.
19240  *
19241  * 1'b0: write the read-back ECC from RMW process if derr is detected. Default
19242  * value after reset.
19243  *
19244  * 1'b1: write of 1 will overwrite the ECC overwrite feature.
19245  *
19246  * Field Enumeration Values:
19247  *
19248  * Enum | Value | Description
19249  * :---------------------------------------------------|:------|:------------
19250  * ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_E_DISABLE | 0x0 |
19251  * ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_E_ENABLE | 0x1 |
19252  *
19253  * Field Access Macros:
19254  *
19255  */
19256 /*
19257  * Enumerated value for register field ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN
19258  *
19259  */
19260 #define ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_E_DISABLE 0x0
19261 /*
19262  * Enumerated value for register field ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN
19263  *
19264  */
19265 #define ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_E_ENABLE 0x1
19266 
19267 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN register field. */
19268 #define ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_LSB 16
19269 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN register field. */
19270 #define ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_MSB 16
19271 /* The width in bits of the ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN register field. */
19272 #define ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_WIDTH 1
19273 /* The mask used to set the ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN register field value. */
19274 #define ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_SET_MSK 0x00010000
19275 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN register field value. */
19276 #define ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_CLR_MSK 0xfffeffff
19277 /* The reset value of the ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN register field. */
19278 #define ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_RESET 0x0
19279 /* Extracts the ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN field value from a register. */
19280 #define ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_GET(value) (((value) & 0x00010000) >> 16)
19281 /* Produces a ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN register field value suitable for setting the register. */
19282 #define ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_SET(value) (((value) << 16) & 0x00010000)
19283 
19284 #ifndef __ASSEMBLY__
19285 /*
19286  * WARNING: The C register and register group struct declarations are provided for
19287  * convenience and illustrative purposes. They should, however, be used with
19288  * caution as the C language standard provides no guarantees about the alignment or
19289  * atomicity of device memory accesses. The recommended practice for coding device
19290  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
19291  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
19292  * alt_write_dword() functions for 64 bit registers.
19293  *
19294  * The struct declaration for register ALT_MPFE_HMC_ADP_ECCCTRL2.
19295  */
19296 struct ALT_MPFE_HMC_ADP_ECCCTRL2_s
19297 {
19298  volatile uint32_t AUTOWB_EN : 1; /* ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN */
19299  uint32_t : 7; /* *UNDEFINED* */
19300  volatile uint32_t RMW_EN : 1; /* ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN */
19301  uint32_t : 7; /* *UNDEFINED* */
19302  volatile uint32_t OVRW_RB_ECC_EN : 1; /* ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN */
19303  uint32_t : 15; /* *UNDEFINED* */
19304 };
19305 
19306 /* The typedef declaration for register ALT_MPFE_HMC_ADP_ECCCTRL2. */
19307 typedef struct ALT_MPFE_HMC_ADP_ECCCTRL2_s ALT_MPFE_HMC_ADP_ECCCTRL2_t;
19308 #endif /* __ASSEMBLY__ */
19309 
19310 /* The reset value of the ALT_MPFE_HMC_ADP_ECCCTRL2 register. */
19311 #define ALT_MPFE_HMC_ADP_ECCCTRL2_RESET 0x00000000
19312 /* The byte offset of the ALT_MPFE_HMC_ADP_ECCCTRL2 register from the beginning of the component. */
19313 #define ALT_MPFE_HMC_ADP_ECCCTRL2_OFST 0x104
19314 
19315 /*
19316  * Register : ERRINTEN
19317  *
19318  * Error Interrupt enable
19319  *
19320  * Register Layout
19321  *
19322  * Bits | Access | Reset | Description
19323  * :-------|:-------|:------|:------------------------------------------
19324  * [0] | RW | 0x0 | ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN
19325  * [1] | RW | 0x0 | ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN
19326  * [2] | RW | 0x0 | ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN
19327  * [3] | RW | 0x0 | ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN
19328  * [31:4] | ??? | 0x0 | *UNDEFINED*
19329  *
19330  */
19331 /*
19332  * Field : SERRINTEN
19333  *
19334  * This bit is used to enable the single bit error to system manager. It enables
19335  * the interrupt modes (sbe request,compare match)
19336  *
19337  * 1'b0: SBE interrupt generation logic is disabled.
19338  *
19339  * 1'b1: SBE interrupt generation logic is enabled,
19340  *
19341  * Field Enumeration Values:
19342  *
19343  * Enum | Value | Description
19344  * :----------------------------------------------|:------|:------------
19345  * ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN_E_DISABLE | 0x0 |
19346  * ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN_E_ENABLE | 0x1 |
19347  *
19348  * Field Access Macros:
19349  *
19350  */
19351 /*
19352  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN
19353  *
19354  */
19355 #define ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN_E_DISABLE 0x0
19356 /*
19357  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN
19358  *
19359  */
19360 #define ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN_E_ENABLE 0x1
19361 
19362 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN register field. */
19363 #define ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN_LSB 0
19364 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN register field. */
19365 #define ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN_MSB 0
19366 /* The width in bits of the ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN register field. */
19367 #define ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN_WIDTH 1
19368 /* The mask used to set the ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN register field value. */
19369 #define ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN_SET_MSK 0x00000001
19370 /* The mask used to clear the ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN register field value. */
19371 #define ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN_CLR_MSK 0xfffffffe
19372 /* The reset value of the ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN register field. */
19373 #define ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN_RESET 0x0
19374 /* Extracts the ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN field value from a register. */
19375 #define ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN_GET(value) (((value) & 0x00000001) >> 0)
19376 /* Produces a ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN register field value suitable for setting the register. */
19377 #define ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN_SET(value) (((value) << 0) & 0x00000001)
19378 
19379 /*
19380  * Field : DERRINTEN
19381  *
19382  * This bit is used to enable the double bit error interrupt to system
19383  *
19384  * manager.When dbe error occurs, bus error is always generated with the
19385  * transaction.DERR interrupt (derr_req)will be generated when this bit is enabled.
19386  *
19387  * 1'b0: DBE interrupt generation logic is disabled.
19388  *
19389  * 1'b1: DBE interrupt generation logic is enabled,
19390  *
19391  * Field Enumeration Values:
19392  *
19393  * Enum | Value | Description
19394  * :----------------------------------------------|:------|:------------
19395  * ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN_E_DISABLE | 0x0 |
19396  * ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN_E_ENABLE | 0x1 |
19397  *
19398  * Field Access Macros:
19399  *
19400  */
19401 /*
19402  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN
19403  *
19404  */
19405 #define ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN_E_DISABLE 0x0
19406 /*
19407  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN
19408  *
19409  */
19410 #define ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN_E_ENABLE 0x1
19411 
19412 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN register field. */
19413 #define ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN_LSB 1
19414 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN register field. */
19415 #define ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN_MSB 1
19416 /* The width in bits of the ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN register field. */
19417 #define ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN_WIDTH 1
19418 /* The mask used to set the ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN register field value. */
19419 #define ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN_SET_MSK 0x00000002
19420 /* The mask used to clear the ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN register field value. */
19421 #define ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN_CLR_MSK 0xfffffffd
19422 /* The reset value of the ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN register field. */
19423 #define ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN_RESET 0x0
19424 /* Extracts the ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN field value from a register. */
19425 #define ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN_GET(value) (((value) & 0x00000002) >> 1)
19426 /* Produces a ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN register field value suitable for setting the register. */
19427 #define ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN_SET(value) (((value) << 1) & 0x00000002)
19428 
19429 /*
19430  * Field : HMI_INTREN
19431  *
19432  * Enables GP HMI interrupt.
19433  *
19434  * This bit is used to enable the general purpose HMI interrupt error interrupt to
19435  * system manager. When this bit is enabled along with autoWB_drop_en, it compares
19436  * the internal counter with autoWB_drop_cntreg value. If the value is greater than
19437  * or equal to, then the interrupt will be asserted..
19438  *
19439  * 1'b0: hmi interrupt generation logic is disabled.
19440  *
19441  * 1'b1: hmi interrupt generation logic is enabled.
19442  *
19443  * Field Enumeration Values:
19444  *
19445  * Enum | Value | Description
19446  * :-----------------------------------------------|:------|:------------
19447  * ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN_E_DISABLE | 0x0 |
19448  * ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN_E_ENABLE | 0x1 |
19449  *
19450  * Field Access Macros:
19451  *
19452  */
19453 /*
19454  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN
19455  *
19456  */
19457 #define ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN_E_DISABLE 0x0
19458 /*
19459  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN
19460  *
19461  */
19462 #define ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN_E_ENABLE 0x1
19463 
19464 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN register field. */
19465 #define ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN_LSB 2
19466 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN register field. */
19467 #define ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN_MSB 2
19468 /* The width in bits of the ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN register field. */
19469 #define ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN_WIDTH 1
19470 /* The mask used to set the ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN register field value. */
19471 #define ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN_SET_MSK 0x00000004
19472 /* The mask used to clear the ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN register field value. */
19473 #define ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN_CLR_MSK 0xfffffffb
19474 /* The reset value of the ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN register field. */
19475 #define ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN_RESET 0x0
19476 /* Extracts the ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN field value from a register. */
19477 #define ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN_GET(value) (((value) & 0x00000004) >> 2)
19478 /* Produces a ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN register field value suitable for setting the register. */
19479 #define ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN_SET(value) (((value) << 2) & 0x00000004)
19480 
19481 /*
19482  * Field : SEQ2CORE_INTREN
19483  *
19484  * Enables seq2core interrupt.
19485  *
19486  * 1'b0: seq2core interrupt generation logic is disabled.
19487  *
19488  * 1'b1: seq2core interrupt generation logic is enabled.
19489  *
19490  * Field Enumeration Values:
19491  *
19492  * Enum | Value | Description
19493  * :----------------------------------------------------|:------|:------------
19494  * ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN_E_DISABLE | 0x0 |
19495  * ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN_E_ENABLE | 0x1 |
19496  *
19497  * Field Access Macros:
19498  *
19499  */
19500 /*
19501  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN
19502  *
19503  */
19504 #define ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN_E_DISABLE 0x0
19505 /*
19506  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN
19507  *
19508  */
19509 #define ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN_E_ENABLE 0x1
19510 
19511 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN register field. */
19512 #define ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN_LSB 3
19513 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN register field. */
19514 #define ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN_MSB 3
19515 /* The width in bits of the ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN register field. */
19516 #define ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN_WIDTH 1
19517 /* The mask used to set the ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN register field value. */
19518 #define ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN_SET_MSK 0x00000008
19519 /* The mask used to clear the ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN register field value. */
19520 #define ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN_CLR_MSK 0xfffffff7
19521 /* The reset value of the ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN register field. */
19522 #define ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN_RESET 0x0
19523 /* Extracts the ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN field value from a register. */
19524 #define ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN_GET(value) (((value) & 0x00000008) >> 3)
19525 /* Produces a ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN register field value suitable for setting the register. */
19526 #define ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN_SET(value) (((value) << 3) & 0x00000008)
19527 
19528 #ifndef __ASSEMBLY__
19529 /*
19530  * WARNING: The C register and register group struct declarations are provided for
19531  * convenience and illustrative purposes. They should, however, be used with
19532  * caution as the C language standard provides no guarantees about the alignment or
19533  * atomicity of device memory accesses. The recommended practice for coding device
19534  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
19535  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
19536  * alt_write_dword() functions for 64 bit registers.
19537  *
19538  * The struct declaration for register ALT_MPFE_HMC_ADP_ERRINTEN.
19539  */
19540 struct ALT_MPFE_HMC_ADP_ERRINTEN_s
19541 {
19542  volatile uint32_t SERRINTEN : 1; /* ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN */
19543  volatile uint32_t DERRINTEN : 1; /* ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN */
19544  volatile uint32_t HMI_INTREN : 1; /* ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN */
19545  volatile uint32_t SEQ2CORE_INTREN : 1; /* ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN */
19546  uint32_t : 28; /* *UNDEFINED* */
19547 };
19548 
19549 /* The typedef declaration for register ALT_MPFE_HMC_ADP_ERRINTEN. */
19550 typedef struct ALT_MPFE_HMC_ADP_ERRINTEN_s ALT_MPFE_HMC_ADP_ERRINTEN_t;
19551 #endif /* __ASSEMBLY__ */
19552 
19553 /* The reset value of the ALT_MPFE_HMC_ADP_ERRINTEN register. */
19554 #define ALT_MPFE_HMC_ADP_ERRINTEN_RESET 0x00000000
19555 /* The byte offset of the ALT_MPFE_HMC_ADP_ERRINTEN register from the beginning of the component. */
19556 #define ALT_MPFE_HMC_ADP_ERRINTEN_OFST 0x110
19557 
19558 /*
19559  * Register : ERRINTENS
19560  *
19561  * Error Interrupt set
19562  *
19563  * Register Layout
19564  *
19565  * Bits | Access | Reset | Description
19566  * :-------|:-------|:------|:------------------------------------------
19567  * [0] | RW | 0x0 | ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS
19568  * [1] | RW | 0x0 | ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS
19569  * [2] | RW | 0x0 | ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS
19570  * [3] | RW | 0x0 | ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS
19571  * [31:4] | ??? | 0x0 | *UNDEFINED*
19572  *
19573  */
19574 /*
19575  * Field : SERRINTS
19576  *
19577  * This bit is used to set the single-bit error interrupt bit.
19578  *
19579  * Reads reflect SERRINTEN.
19580  *
19581  * 1'b0: writing of zero has no effect
19582  *
19583  * 1'b1: writing one, this bit will set SERRINTEN bit to 1.
19584  *
19585  * This is performing a bitwise writing, not implemented as a FF.
19586  *
19587  * Field Enumeration Values:
19588  *
19589  * Enum | Value | Description
19590  * :-------------------------------------------|:------|:------------
19591  * ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS_E_STAY | 0x0 |
19592  * ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS_E_SET | 0x1 |
19593  *
19594  * Field Access Macros:
19595  *
19596  */
19597 /*
19598  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS
19599  *
19600  */
19601 #define ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS_E_STAY 0x0
19602 /*
19603  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS
19604  *
19605  */
19606 #define ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS_E_SET 0x1
19607 
19608 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS register field. */
19609 #define ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS_LSB 0
19610 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS register field. */
19611 #define ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS_MSB 0
19612 /* The width in bits of the ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS register field. */
19613 #define ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS_WIDTH 1
19614 /* The mask used to set the ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS register field value. */
19615 #define ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS_SET_MSK 0x00000001
19616 /* The mask used to clear the ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS register field value. */
19617 #define ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS_CLR_MSK 0xfffffffe
19618 /* The reset value of the ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS register field. */
19619 #define ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS_RESET 0x0
19620 /* Extracts the ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS field value from a register. */
19621 #define ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS_GET(value) (((value) & 0x00000001) >> 0)
19622 /* Produces a ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS register field value suitable for setting the register. */
19623 #define ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS_SET(value) (((value) << 0) & 0x00000001)
19624 
19625 /*
19626  * Field : DERRINTS
19627  *
19628  * This bit is used to set the double-bit error interrupt bit.
19629  *
19630  * Reads reflect DERRINTEN.
19631  *
19632  * 1'b0: writing of zero has no effect
19633  *
19634  * 1'b1: writing one, DERRINTEN bit to 1.
19635  *
19636  * This is performing a bitwise writing, not implemented as a FF.
19637  *
19638  * Field Enumeration Values:
19639  *
19640  * Enum | Value | Description
19641  * :-------------------------------------------|:------|:------------
19642  * ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS_E_STAY | 0x0 |
19643  * ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS_E_SET | 0x1 |
19644  *
19645  * Field Access Macros:
19646  *
19647  */
19648 /*
19649  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS
19650  *
19651  */
19652 #define ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS_E_STAY 0x0
19653 /*
19654  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS
19655  *
19656  */
19657 #define ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS_E_SET 0x1
19658 
19659 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS register field. */
19660 #define ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS_LSB 1
19661 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS register field. */
19662 #define ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS_MSB 1
19663 /* The width in bits of the ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS register field. */
19664 #define ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS_WIDTH 1
19665 /* The mask used to set the ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS register field value. */
19666 #define ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS_SET_MSK 0x00000002
19667 /* The mask used to clear the ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS register field value. */
19668 #define ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS_CLR_MSK 0xfffffffd
19669 /* The reset value of the ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS register field. */
19670 #define ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS_RESET 0x0
19671 /* Extracts the ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS field value from a register. */
19672 #define ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS_GET(value) (((value) & 0x00000002) >> 1)
19673 /* Produces a ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS register field value suitable for setting the register. */
19674 #define ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS_SET(value) (((value) << 1) & 0x00000002)
19675 
19676 /*
19677  * Field : HMI_INTRS
19678  *
19679  * This bit is used to set the general purposes HMI interrupt error.
19680  *
19681  * 1'b0: writing of zero has no effect
19682  *
19683  * 1'b1: writing one, HMI_INTREN bit to 1.
19684  *
19685  * This is performing a bitwise writing, not implemented as a FF.
19686  *
19687  * Field Enumeration Values:
19688  *
19689  * Enum | Value | Description
19690  * :--------------------------------------------|:------|:------------
19691  * ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS_E_STAY | 0x0 |
19692  * ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS_E_SET | 0x1 |
19693  *
19694  * Field Access Macros:
19695  *
19696  */
19697 /*
19698  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS
19699  *
19700  */
19701 #define ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS_E_STAY 0x0
19702 /*
19703  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS
19704  *
19705  */
19706 #define ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS_E_SET 0x1
19707 
19708 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS register field. */
19709 #define ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS_LSB 2
19710 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS register field. */
19711 #define ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS_MSB 2
19712 /* The width in bits of the ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS register field. */
19713 #define ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS_WIDTH 1
19714 /* The mask used to set the ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS register field value. */
19715 #define ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS_SET_MSK 0x00000004
19716 /* The mask used to clear the ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS register field value. */
19717 #define ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS_CLR_MSK 0xfffffffb
19718 /* The reset value of the ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS register field. */
19719 #define ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS_RESET 0x0
19720 /* Extracts the ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS field value from a register. */
19721 #define ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS_GET(value) (((value) & 0x00000004) >> 2)
19722 /* Produces a ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS register field value suitable for setting the register. */
19723 #define ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS_SET(value) (((value) << 2) & 0x00000004)
19724 
19725 /*
19726  * Field : SEQ2CORE_INTRS
19727  *
19728  * This bit is used to set the seq2core interrupt.
19729  *
19730  * 1'b0: writing of zero has no effect
19731  *
19732  * 1'b1: writing one, SEQ2CORE_INTREN bit to 1
19733  *
19734  * This is performing a bitwise writing, not implemented as a FF.
19735  *
19736  * Field Enumeration Values:
19737  *
19738  * Enum | Value | Description
19739  * :-------------------------------------------------|:------|:------------
19740  * ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS_E_STAY | 0x0 |
19741  * ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS_E_SET | 0x1 |
19742  *
19743  * Field Access Macros:
19744  *
19745  */
19746 /*
19747  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS
19748  *
19749  */
19750 #define ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS_E_STAY 0x0
19751 /*
19752  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS
19753  *
19754  */
19755 #define ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS_E_SET 0x1
19756 
19757 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS register field. */
19758 #define ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS_LSB 3
19759 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS register field. */
19760 #define ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS_MSB 3
19761 /* The width in bits of the ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS register field. */
19762 #define ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS_WIDTH 1
19763 /* The mask used to set the ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS register field value. */
19764 #define ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS_SET_MSK 0x00000008
19765 /* The mask used to clear the ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS register field value. */
19766 #define ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS_CLR_MSK 0xfffffff7
19767 /* The reset value of the ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS register field. */
19768 #define ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS_RESET 0x0
19769 /* Extracts the ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS field value from a register. */
19770 #define ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS_GET(value) (((value) & 0x00000008) >> 3)
19771 /* Produces a ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS register field value suitable for setting the register. */
19772 #define ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS_SET(value) (((value) << 3) & 0x00000008)
19773 
19774 #ifndef __ASSEMBLY__
19775 /*
19776  * WARNING: The C register and register group struct declarations are provided for
19777  * convenience and illustrative purposes. They should, however, be used with
19778  * caution as the C language standard provides no guarantees about the alignment or
19779  * atomicity of device memory accesses. The recommended practice for coding device
19780  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
19781  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
19782  * alt_write_dword() functions for 64 bit registers.
19783  *
19784  * The struct declaration for register ALT_MPFE_HMC_ADP_ERRINTENS.
19785  */
19786 struct ALT_MPFE_HMC_ADP_ERRINTENS_s
19787 {
19788  volatile uint32_t SERRINTS : 1; /* ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS */
19789  volatile uint32_t DERRINTS : 1; /* ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS */
19790  volatile uint32_t HMI_INTRS : 1; /* ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS */
19791  volatile uint32_t SEQ2CORE_INTRS : 1; /* ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS */
19792  uint32_t : 28; /* *UNDEFINED* */
19793 };
19794 
19795 /* The typedef declaration for register ALT_MPFE_HMC_ADP_ERRINTENS. */
19796 typedef struct ALT_MPFE_HMC_ADP_ERRINTENS_s ALT_MPFE_HMC_ADP_ERRINTENS_t;
19797 #endif /* __ASSEMBLY__ */
19798 
19799 /* The reset value of the ALT_MPFE_HMC_ADP_ERRINTENS register. */
19800 #define ALT_MPFE_HMC_ADP_ERRINTENS_RESET 0x00000000
19801 /* The byte offset of the ALT_MPFE_HMC_ADP_ERRINTENS register from the beginning of the component. */
19802 #define ALT_MPFE_HMC_ADP_ERRINTENS_OFST 0x114
19803 
19804 /*
19805  * Register : ERRINTENR
19806  *
19807  * Error Interrupt reset.
19808  *
19809  * Register Layout
19810  *
19811  * Bits | Access | Reset | Description
19812  * :-------|:-------|:------|:------------------------------------------
19813  * [0] | RW | 0x0 | ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR
19814  * [1] | RW | 0x0 | ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR
19815  * [2] | RW | 0x0 | ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR
19816  * [3] | RW | 0x0 | ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR
19817  * [31:4] | ??? | 0x0 | *UNDEFINED*
19818  *
19819  */
19820 /*
19821  * Field : SERRINTR
19822  *
19823  * This bit is used to reset the single-bit error interrupt bit.
19824  *
19825  * Reads reflect SERRINTEN.
19826  *
19827  * 1’b0: Writing of zero has no effect.
19828  *
19829  * 1’b1: By writing one, this bit will reset SERRINTEN bit to 0.
19830  *
19831  * This is performing a bitwise writing of this feature.
19832  *
19833  * Field Enumeration Values:
19834  *
19835  * Enum | Value | Description
19836  * :--------------------------------------------|:------|:------------
19837  * ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR_E_STAY | 0x0 |
19838  * ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR_E_RESET | 0x1 |
19839  *
19840  * Field Access Macros:
19841  *
19842  */
19843 /*
19844  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR
19845  *
19846  */
19847 #define ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR_E_STAY 0x0
19848 /*
19849  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR
19850  *
19851  */
19852 #define ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR_E_RESET 0x1
19853 
19854 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR register field. */
19855 #define ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR_LSB 0
19856 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR register field. */
19857 #define ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR_MSB 0
19858 /* The width in bits of the ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR register field. */
19859 #define ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR_WIDTH 1
19860 /* The mask used to set the ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR register field value. */
19861 #define ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR_SET_MSK 0x00000001
19862 /* The mask used to clear the ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR register field value. */
19863 #define ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR_CLR_MSK 0xfffffffe
19864 /* The reset value of the ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR register field. */
19865 #define ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR_RESET 0x0
19866 /* Extracts the ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR field value from a register. */
19867 #define ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR_GET(value) (((value) & 0x00000001) >> 0)
19868 /* Produces a ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR register field value suitable for setting the register. */
19869 #define ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR_SET(value) (((value) << 0) & 0x00000001)
19870 
19871 /*
19872  * Field : DERRINTR
19873  *
19874  * This bit is used to reset the double-bit error interrupt bit.
19875  *
19876  * Reads reflect DERRINTEN.
19877  *
19878  * 1’b0: Writing of zero has no effect.
19879  *
19880  * 1’b1: By writing one, this bit will reset DERRINTEN bit to 0.
19881  *
19882  * This is performing a bitwise writing of this feature.
19883  *
19884  * Field Enumeration Values:
19885  *
19886  * Enum | Value | Description
19887  * :--------------------------------------------|:------|:------------
19888  * ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR_E_STAY | 0x0 |
19889  * ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR_E_RESET | 0x1 |
19890  *
19891  * Field Access Macros:
19892  *
19893  */
19894 /*
19895  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR
19896  *
19897  */
19898 #define ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR_E_STAY 0x0
19899 /*
19900  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR
19901  *
19902  */
19903 #define ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR_E_RESET 0x1
19904 
19905 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR register field. */
19906 #define ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR_LSB 1
19907 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR register field. */
19908 #define ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR_MSB 1
19909 /* The width in bits of the ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR register field. */
19910 #define ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR_WIDTH 1
19911 /* The mask used to set the ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR register field value. */
19912 #define ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR_SET_MSK 0x00000002
19913 /* The mask used to clear the ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR register field value. */
19914 #define ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR_CLR_MSK 0xfffffffd
19915 /* The reset value of the ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR register field. */
19916 #define ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR_RESET 0x0
19917 /* Extracts the ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR field value from a register. */
19918 #define ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR_GET(value) (((value) & 0x00000002) >> 1)
19919 /* Produces a ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR register field value suitable for setting the register. */
19920 #define ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR_SET(value) (((value) << 1) & 0x00000002)
19921 
19922 /*
19923  * Field : HMI_INTRR
19924  *
19925  * This bit is used to reset the general purpose HMI interrupt error interrupt to
19926  * system manager
19927  *
19928  * 1’b0: Writing of zero has no effect.
19929  *
19930  * 1’b1: By writing one, this bit will reset HMI_INTREN bit to 0.
19931  *
19932  * This is performing a bitwise writing of this feature.
19933  *
19934  * Field Enumeration Values:
19935  *
19936  * Enum | Value | Description
19937  * :---------------------------------------------|:------|:------------
19938  * ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR_E_STAY | 0x0 |
19939  * ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR_E_RESET | 0x1 |
19940  *
19941  * Field Access Macros:
19942  *
19943  */
19944 /*
19945  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR
19946  *
19947  */
19948 #define ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR_E_STAY 0x0
19949 /*
19950  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR
19951  *
19952  */
19953 #define ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR_E_RESET 0x1
19954 
19955 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR register field. */
19956 #define ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR_LSB 2
19957 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR register field. */
19958 #define ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR_MSB 2
19959 /* The width in bits of the ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR register field. */
19960 #define ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR_WIDTH 1
19961 /* The mask used to set the ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR register field value. */
19962 #define ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR_SET_MSK 0x00000004
19963 /* The mask used to clear the ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR register field value. */
19964 #define ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR_CLR_MSK 0xfffffffb
19965 /* The reset value of the ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR register field. */
19966 #define ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR_RESET 0x0
19967 /* Extracts the ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR field value from a register. */
19968 #define ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR_GET(value) (((value) & 0x00000004) >> 2)
19969 /* Produces a ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR register field value suitable for setting the register. */
19970 #define ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR_SET(value) (((value) << 2) & 0x00000004)
19971 
19972 /*
19973  * Field : SEQ2CORE_INTRR
19974  *
19975  * This bit is used to reset the seq2core interrupt bit.
19976  *
19977  * 1’b0: Writing of zero has no effect.
19978  *
19979  * 1’b1: By writing one, this bit will reset SEQ2CORE_INTREN bit to 0.
19980  *
19981  * This is performing a bitwise writing of this feature.
19982  *
19983  * Field Enumeration Values:
19984  *
19985  * Enum | Value | Description
19986  * :--------------------------------------------------|:------|:------------
19987  * ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR_E_STAY | 0x0 |
19988  * ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR_E_RESET | 0x1 |
19989  *
19990  * Field Access Macros:
19991  *
19992  */
19993 /*
19994  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR
19995  *
19996  */
19997 #define ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR_E_STAY 0x0
19998 /*
19999  * Enumerated value for register field ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR
20000  *
20001  */
20002 #define ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR_E_RESET 0x1
20003 
20004 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR register field. */
20005 #define ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR_LSB 3
20006 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR register field. */
20007 #define ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR_MSB 3
20008 /* The width in bits of the ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR register field. */
20009 #define ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR_WIDTH 1
20010 /* The mask used to set the ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR register field value. */
20011 #define ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR_SET_MSK 0x00000008
20012 /* The mask used to clear the ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR register field value. */
20013 #define ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR_CLR_MSK 0xfffffff7
20014 /* The reset value of the ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR register field. */
20015 #define ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR_RESET 0x0
20016 /* Extracts the ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR field value from a register. */
20017 #define ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR_GET(value) (((value) & 0x00000008) >> 3)
20018 /* Produces a ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR register field value suitable for setting the register. */
20019 #define ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR_SET(value) (((value) << 3) & 0x00000008)
20020 
20021 #ifndef __ASSEMBLY__
20022 /*
20023  * WARNING: The C register and register group struct declarations are provided for
20024  * convenience and illustrative purposes. They should, however, be used with
20025  * caution as the C language standard provides no guarantees about the alignment or
20026  * atomicity of device memory accesses. The recommended practice for coding device
20027  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
20028  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
20029  * alt_write_dword() functions for 64 bit registers.
20030  *
20031  * The struct declaration for register ALT_MPFE_HMC_ADP_ERRINTENR.
20032  */
20033 struct ALT_MPFE_HMC_ADP_ERRINTENR_s
20034 {
20035  volatile uint32_t SERRINTR : 1; /* ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR */
20036  volatile uint32_t DERRINTR : 1; /* ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR */
20037  volatile uint32_t HMI_INTRR : 1; /* ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR */
20038  volatile uint32_t SEQ2CORE_INTRR : 1; /* ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR */
20039  uint32_t : 28; /* *UNDEFINED* */
20040 };
20041 
20042 /* The typedef declaration for register ALT_MPFE_HMC_ADP_ERRINTENR. */
20043 typedef struct ALT_MPFE_HMC_ADP_ERRINTENR_s ALT_MPFE_HMC_ADP_ERRINTENR_t;
20044 #endif /* __ASSEMBLY__ */
20045 
20046 /* The reset value of the ALT_MPFE_HMC_ADP_ERRINTENR register. */
20047 #define ALT_MPFE_HMC_ADP_ERRINTENR_RESET 0x00000000
20048 /* The byte offset of the ALT_MPFE_HMC_ADP_ERRINTENR register from the beginning of the component. */
20049 #define ALT_MPFE_HMC_ADP_ERRINTENR_OFST 0x118
20050 
20051 /*
20052  * Register : INTMODE
20053  *
20054  * Interrupt mode
20055  *
20056  * Register Layout
20057  *
20058  * Bits | Access | Reset | Description
20059  * :--------|:-------|:------|:-------------------------------------------
20060  * [0] | RW | 0x0 | ALT_MPFE_HMC_ADP_INTMODE_INTMODE
20061  * [7:1] | ??? | 0x0 | *UNDEFINED*
20062  * [8] | RW | 0x0 | ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN
20063  * [15:9] | ??? | 0x0 | *UNDEFINED*
20064  * [16] | RW | 0x0 | ALT_MPFE_HMC_ADP_INTMODE_INTONCMP
20065  * [23:17] | ??? | 0x0 | *UNDEFINED*
20066  * [24] | RW | 0x0 | ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN
20067  * [31:25] | ??? | 0x0 | *UNDEFINED*
20068  *
20069  */
20070 /*
20071  * Field : INTMODE
20072  *
20073  * Interrupt mode for single-bit error.This is disabled when SERRINTEN is disabled.
20074  *
20075  * 1'b0: interrupt disbaled
20076  *
20077  * 1'b1: generate interrupt on every SERR
20078  *
20079  * Field Enumeration Values:
20080  *
20081  * Enum | Value | Description
20082  * :-------------------------------------------|:------|:------------
20083  * ALT_MPFE_HMC_ADP_INTMODE_INTMODE_E_DISABLE | 0x0 |
20084  * ALT_MPFE_HMC_ADP_INTMODE_INTMODE_E_ENABLE | 0x1 |
20085  *
20086  * Field Access Macros:
20087  *
20088  */
20089 /*
20090  * Enumerated value for register field ALT_MPFE_HMC_ADP_INTMODE_INTMODE
20091  *
20092  */
20093 #define ALT_MPFE_HMC_ADP_INTMODE_INTMODE_E_DISABLE 0x0
20094 /*
20095  * Enumerated value for register field ALT_MPFE_HMC_ADP_INTMODE_INTMODE
20096  *
20097  */
20098 #define ALT_MPFE_HMC_ADP_INTMODE_INTMODE_E_ENABLE 0x1
20099 
20100 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_INTMODE_INTMODE register field. */
20101 #define ALT_MPFE_HMC_ADP_INTMODE_INTMODE_LSB 0
20102 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_INTMODE_INTMODE register field. */
20103 #define ALT_MPFE_HMC_ADP_INTMODE_INTMODE_MSB 0
20104 /* The width in bits of the ALT_MPFE_HMC_ADP_INTMODE_INTMODE register field. */
20105 #define ALT_MPFE_HMC_ADP_INTMODE_INTMODE_WIDTH 1
20106 /* The mask used to set the ALT_MPFE_HMC_ADP_INTMODE_INTMODE register field value. */
20107 #define ALT_MPFE_HMC_ADP_INTMODE_INTMODE_SET_MSK 0x00000001
20108 /* The mask used to clear the ALT_MPFE_HMC_ADP_INTMODE_INTMODE register field value. */
20109 #define ALT_MPFE_HMC_ADP_INTMODE_INTMODE_CLR_MSK 0xfffffffe
20110 /* The reset value of the ALT_MPFE_HMC_ADP_INTMODE_INTMODE register field. */
20111 #define ALT_MPFE_HMC_ADP_INTMODE_INTMODE_RESET 0x0
20112 /* Extracts the ALT_MPFE_HMC_ADP_INTMODE_INTMODE field value from a register. */
20113 #define ALT_MPFE_HMC_ADP_INTMODE_INTMODE_GET(value) (((value) & 0x00000001) >> 0)
20114 /* Produces a ALT_MPFE_HMC_ADP_INTMODE_INTMODE register field value suitable for setting the register. */
20115 #define ALT_MPFE_HMC_ADP_INTMODE_INTMODE_SET(value) (((value) << 0) & 0x00000001)
20116 
20117 /*
20118  * Field : EXT_ADDRPARITY_EN
20119  *
20120  * Enable address parity for DDR4 memories.
20121  *
20122  * This bit is used to enable the interrupt that generate externally when address
20123  * parity is detected. when enabled, this will be generating derr_req signal
20124  *
20125  * 1'b0: disable address parity on DERR interrupt
20126  *
20127  * 1'b1: enable address parity on DERR interrupt
20128  *
20129  * Field Enumeration Values:
20130  *
20131  * Enum | Value | Description
20132  * :-----------------------------------------------------|:------|:------------
20133  * ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN_E_DISABLE | 0x0 |
20134  * ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN_E_ENABLE | 0x1 |
20135  *
20136  * Field Access Macros:
20137  *
20138  */
20139 /*
20140  * Enumerated value for register field ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN
20141  *
20142  */
20143 #define ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN_E_DISABLE 0x0
20144 /*
20145  * Enumerated value for register field ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN
20146  *
20147  */
20148 #define ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN_E_ENABLE 0x1
20149 
20150 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN register field. */
20151 #define ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN_LSB 8
20152 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN register field. */
20153 #define ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN_MSB 8
20154 /* The width in bits of the ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN register field. */
20155 #define ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN_WIDTH 1
20156 /* The mask used to set the ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN register field value. */
20157 #define ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN_SET_MSK 0x00000100
20158 /* The mask used to clear the ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN register field value. */
20159 #define ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN_CLR_MSK 0xfffffeff
20160 /* The reset value of the ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN register field. */
20161 #define ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN_RESET 0x0
20162 /* Extracts the ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN field value from a register. */
20163 #define ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN_GET(value) (((value) & 0x00000100) >> 8)
20164 /* Produces a ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN register field value suitable for setting the register. */
20165 #define ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN_SET(value) (((value) << 8) & 0x00000100)
20166 
20167 /*
20168  * Field : INTONCMP
20169  *
20170  * Enable interrupt on compare match.
20171  *
20172  * This bit is used to enable interrupt when the internal counter and SERRCNTA
20173  * value matches. serr_req signal will be asserted on a match.
20174  *
20175  * 1'b0: SERR interrupt on compare match is disabled
20176  *
20177  * 1'b1: SERR interrupt on compare match is enabled
20178  *
20179  * Field Enumeration Values:
20180  *
20181  * Enum | Value | Description
20182  * :--------------------------------------------|:------|:------------
20183  * ALT_MPFE_HMC_ADP_INTMODE_INTONCMP_E_DISABLE | 0x0 |
20184  * ALT_MPFE_HMC_ADP_INTMODE_INTONCMP_E_ENABLE | 0x1 |
20185  *
20186  * Field Access Macros:
20187  *
20188  */
20189 /*
20190  * Enumerated value for register field ALT_MPFE_HMC_ADP_INTMODE_INTONCMP
20191  *
20192  */
20193 #define ALT_MPFE_HMC_ADP_INTMODE_INTONCMP_E_DISABLE 0x0
20194 /*
20195  * Enumerated value for register field ALT_MPFE_HMC_ADP_INTMODE_INTONCMP
20196  *
20197  */
20198 #define ALT_MPFE_HMC_ADP_INTMODE_INTONCMP_E_ENABLE 0x1
20199 
20200 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_INTMODE_INTONCMP register field. */
20201 #define ALT_MPFE_HMC_ADP_INTMODE_INTONCMP_LSB 16
20202 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_INTMODE_INTONCMP register field. */
20203 #define ALT_MPFE_HMC_ADP_INTMODE_INTONCMP_MSB 16
20204 /* The width in bits of the ALT_MPFE_HMC_ADP_INTMODE_INTONCMP register field. */
20205 #define ALT_MPFE_HMC_ADP_INTMODE_INTONCMP_WIDTH 1
20206 /* The mask used to set the ALT_MPFE_HMC_ADP_INTMODE_INTONCMP register field value. */
20207 #define ALT_MPFE_HMC_ADP_INTMODE_INTONCMP_SET_MSK 0x00010000
20208 /* The mask used to clear the ALT_MPFE_HMC_ADP_INTMODE_INTONCMP register field value. */
20209 #define ALT_MPFE_HMC_ADP_INTMODE_INTONCMP_CLR_MSK 0xfffeffff
20210 /* The reset value of the ALT_MPFE_HMC_ADP_INTMODE_INTONCMP register field. */
20211 #define ALT_MPFE_HMC_ADP_INTMODE_INTONCMP_RESET 0x0
20212 /* Extracts the ALT_MPFE_HMC_ADP_INTMODE_INTONCMP field value from a register. */
20213 #define ALT_MPFE_HMC_ADP_INTMODE_INTONCMP_GET(value) (((value) & 0x00010000) >> 16)
20214 /* Produces a ALT_MPFE_HMC_ADP_INTMODE_INTONCMP register field value suitable for setting the register. */
20215 #define ALT_MPFE_HMC_ADP_INTMODE_INTONCMP_SET(value) (((value) << 16) & 0x00010000)
20216 
20217 /*
20218  * Field : AFICAL_EN
20219  *
20220  * Enable interrupt of AFI Cal success.
20221  *
20222  * This bit is used to enable interrupt of AFI Cal success. hmi_intr signal will be
20223  * asserted on a match.
20224  *
20225  * 1'b0: HMI interrupts on compare match is disabled.
20226  *
20227  * 1'b1: HMI interrupts on compare matched is enabled.
20228  *
20229  * Field Enumeration Values:
20230  *
20231  * Enum | Value | Description
20232  * :---------------------------------------------|:------|:------------
20233  * ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN_E_DISABLE | 0x0 |
20234  * ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN_E_ENABLE | 0x1 |
20235  *
20236  * Field Access Macros:
20237  *
20238  */
20239 /*
20240  * Enumerated value for register field ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN
20241  *
20242  */
20243 #define ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN_E_DISABLE 0x0
20244 /*
20245  * Enumerated value for register field ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN
20246  *
20247  */
20248 #define ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN_E_ENABLE 0x1
20249 
20250 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN register field. */
20251 #define ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN_LSB 24
20252 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN register field. */
20253 #define ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN_MSB 24
20254 /* The width in bits of the ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN register field. */
20255 #define ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN_WIDTH 1
20256 /* The mask used to set the ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN register field value. */
20257 #define ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN_SET_MSK 0x01000000
20258 /* The mask used to clear the ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN register field value. */
20259 #define ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN_CLR_MSK 0xfeffffff
20260 /* The reset value of the ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN register field. */
20261 #define ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN_RESET 0x0
20262 /* Extracts the ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN field value from a register. */
20263 #define ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN_GET(value) (((value) & 0x01000000) >> 24)
20264 /* Produces a ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN register field value suitable for setting the register. */
20265 #define ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN_SET(value) (((value) << 24) & 0x01000000)
20266 
20267 #ifndef __ASSEMBLY__
20268 /*
20269  * WARNING: The C register and register group struct declarations are provided for
20270  * convenience and illustrative purposes. They should, however, be used with
20271  * caution as the C language standard provides no guarantees about the alignment or
20272  * atomicity of device memory accesses. The recommended practice for coding device
20273  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
20274  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
20275  * alt_write_dword() functions for 64 bit registers.
20276  *
20277  * The struct declaration for register ALT_MPFE_HMC_ADP_INTMODE.
20278  */
20279 struct ALT_MPFE_HMC_ADP_INTMODE_s
20280 {
20281  volatile uint32_t INTMODE : 1; /* ALT_MPFE_HMC_ADP_INTMODE_INTMODE */
20282  uint32_t : 7; /* *UNDEFINED* */
20283  volatile uint32_t EXT_ADDRPARITY_EN : 1; /* ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN */
20284  uint32_t : 7; /* *UNDEFINED* */
20285  volatile uint32_t INTONCMP : 1; /* ALT_MPFE_HMC_ADP_INTMODE_INTONCMP */
20286  uint32_t : 7; /* *UNDEFINED* */
20287  volatile uint32_t AFICAL_EN : 1; /* ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN */
20288  uint32_t : 7; /* *UNDEFINED* */
20289 };
20290 
20291 /* The typedef declaration for register ALT_MPFE_HMC_ADP_INTMODE. */
20292 typedef struct ALT_MPFE_HMC_ADP_INTMODE_s ALT_MPFE_HMC_ADP_INTMODE_t;
20293 #endif /* __ASSEMBLY__ */
20294 
20295 /* The reset value of the ALT_MPFE_HMC_ADP_INTMODE register. */
20296 #define ALT_MPFE_HMC_ADP_INTMODE_RESET 0x00000000
20297 /* The byte offset of the ALT_MPFE_HMC_ADP_INTMODE register from the beginning of the component. */
20298 #define ALT_MPFE_HMC_ADP_INTMODE_OFST 0x11c
20299 
20300 /*
20301  * Register : INTSTAT
20302  *
20303  * Interrupt status
20304  *
20305  * Register Layout
20306  *
20307  * Bits | Access | Reset | Description
20308  * :--------|:-------|:------|:---------------------------------------
20309  * [0] | RW | 0x0 | ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA
20310  * [1] | RW | 0x0 | ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA
20311  * [2] | RW | 0x0 | ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA
20312  * [3] | RW | 0x0 | ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA
20313  * [15:4] | ??? | 0x0 | *UNDEFINED*
20314  * [16] | RW | 0x0 | ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG
20315  * [17] | RW | 0x0 | ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG
20316  * [18] | RW | 0x0 | ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG
20317  * [31:19] | ??? | 0x0 | *UNDEFINED*
20318  *
20319  */
20320 /*
20321  * Field : SERRPENA
20322  *
20323  * Single-bit error pending
20324  *
20325  * This bit is used to clear the pending SBE.
20326  *
20327  * 1'b0: No effect.
20328  *
20329  * 1'b1: indicates SBE is pending. Write of one will clear the pending. This will
20330  * de-assert the serr_req signal.
20331  *
20332  * Field Access Macros:
20333  *
20334  */
20335 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA register field. */
20336 #define ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA_LSB 0
20337 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA register field. */
20338 #define ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA_MSB 0
20339 /* The width in bits of the ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA register field. */
20340 #define ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA_WIDTH 1
20341 /* The mask used to set the ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA register field value. */
20342 #define ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA_SET_MSK 0x00000001
20343 /* The mask used to clear the ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA register field value. */
20344 #define ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA_CLR_MSK 0xfffffffe
20345 /* The reset value of the ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA register field. */
20346 #define ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA_RESET 0x0
20347 /* Extracts the ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA field value from a register. */
20348 #define ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA_GET(value) (((value) & 0x00000001) >> 0)
20349 /* Produces a ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA register field value suitable for setting the register. */
20350 #define ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA_SET(value) (((value) << 0) & 0x00000001)
20351 
20352 /*
20353  * Field : DERRPENA
20354  *
20355  * Double bit error pending
20356  *
20357  * This bit is used to clear the pending DBE.
20358  *
20359  * 1'b0: No effect.
20360  *
20361  * 1'b1: indicates DBE is pending. Write of one will clear the pending DBE. This
20362  * will de-assert the derr_req signal.
20363  *
20364  * Field Access Macros:
20365  *
20366  */
20367 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA register field. */
20368 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA_LSB 1
20369 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA register field. */
20370 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA_MSB 1
20371 /* The width in bits of the ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA register field. */
20372 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA_WIDTH 1
20373 /* The mask used to set the ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA register field value. */
20374 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA_SET_MSK 0x00000002
20375 /* The mask used to clear the ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA register field value. */
20376 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA_CLR_MSK 0xfffffffd
20377 /* The reset value of the ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA register field. */
20378 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA_RESET 0x0
20379 /* Extracts the ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA field value from a register. */
20380 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA_GET(value) (((value) & 0x00000002) >> 1)
20381 /* Produces a ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA register field value suitable for setting the register. */
20382 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA_SET(value) (((value) << 1) & 0x00000002)
20383 
20384 /*
20385  * Field : HMI_PENA
20386  *
20387  * HMI interrupt pending
20388  *
20389  * This bit is used to clear the pending hmi interrupt bit.
20390  *
20391  * 1'b0: No effect
20392  *
20393  * 1'b1: indicates hmi interrupt is pending. Write of one will clear the pending
20394  * interrupt. This will de-assert the hmi_intr signal.
20395  *
20396  * Field Access Macros:
20397  *
20398  */
20399 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA register field. */
20400 #define ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA_LSB 2
20401 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA register field. */
20402 #define ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA_MSB 2
20403 /* The width in bits of the ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA register field. */
20404 #define ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA_WIDTH 1
20405 /* The mask used to set the ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA register field value. */
20406 #define ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA_SET_MSK 0x00000004
20407 /* The mask used to clear the ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA register field value. */
20408 #define ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA_CLR_MSK 0xfffffffb
20409 /* The reset value of the ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA register field. */
20410 #define ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA_RESET 0x0
20411 /* Extracts the ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA field value from a register. */
20412 #define ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA_GET(value) (((value) & 0x00000004) >> 2)
20413 /* Produces a ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA register field value suitable for setting the register. */
20414 #define ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA_SET(value) (((value) << 2) & 0x00000004)
20415 
20416 /*
20417  * Field : SEQ2CORE_PENA
20418  *
20419  * SEQ2CORE pending
20420  *
20421  * This bit is used to clear the pending SEQ2CORE.
20422  *
20423  * 1'b0: No effect
20424  *
20425  * 1'b1: indicates seq2core interrupt is pending. Write of one will clear the
20426  * pending interrupt. This will de-assert the seq2core_intr signal.
20427  *
20428  * Field Access Macros:
20429  *
20430  */
20431 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA register field. */
20432 #define ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA_LSB 3
20433 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA register field. */
20434 #define ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA_MSB 3
20435 /* The width in bits of the ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA register field. */
20436 #define ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA_WIDTH 1
20437 /* The mask used to set the ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA register field value. */
20438 #define ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA_SET_MSK 0x00000008
20439 /* The mask used to clear the ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA register field value. */
20440 #define ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA_CLR_MSK 0xfffffff7
20441 /* The reset value of the ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA register field. */
20442 #define ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA_RESET 0x0
20443 /* Extracts the ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA field value from a register. */
20444 #define ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA_GET(value) (((value) & 0x00000008) >> 3)
20445 /* Produces a ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA register field value suitable for setting the register. */
20446 #define ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA_SET(value) (((value) << 3) & 0x00000008)
20447 
20448 /*
20449  * Field : ADDRMTCFLG
20450  *
20451  * Address mismatch error flag.
20452  *
20453  * This bit is used to flag the last transaction was flagged with address mismatch
20454  * error.
20455  *
20456  * 1'b0: No effect.
20457  *
20458  * 1'b1: indicates address mismatch error has occured. This will drive the bus to
20459  * respond the read with bus error. Write of one will clears this register address
20460  * mismatch error.
20461  *
20462  * Bus error occurs as part of the transaction but this indicates the SW the cause
20463  * of the error. This should occur once per transaction.
20464  *
20465  * Field Access Macros:
20466  *
20467  */
20468 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG register field. */
20469 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG_LSB 16
20470 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG register field. */
20471 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG_MSB 16
20472 /* The width in bits of the ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG register field. */
20473 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG_WIDTH 1
20474 /* The mask used to set the ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG register field value. */
20475 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG_SET_MSK 0x00010000
20476 /* The mask used to clear the ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG register field value. */
20477 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG_CLR_MSK 0xfffeffff
20478 /* The reset value of the ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG register field. */
20479 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG_RESET 0x0
20480 /* Extracts the ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG field value from a register. */
20481 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG_GET(value) (((value) & 0x00010000) >> 16)
20482 /* Produces a ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG register field value suitable for setting the register. */
20483 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG_SET(value) (((value) << 16) & 0x00010000)
20484 
20485 /*
20486  * Field : ADDRPARFLG
20487  *
20488  * External address parity flag for DDR4 memory.
20489  *
20490  * This bit is used to flag external address parity flag which is driven with
20491  * derr_req port.
20492  *
20493  * 1'b0: No Effect.
20494  *
20495  * 1'b1: Read of one indicates double-bit interrupt has occurred. Write of one
20496  * will clear this register last address parity flag.
20497  *
20498  * Field Access Macros:
20499  *
20500  */
20501 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG register field. */
20502 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG_LSB 17
20503 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG register field. */
20504 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG_MSB 17
20505 /* The width in bits of the ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG register field. */
20506 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG_WIDTH 1
20507 /* The mask used to set the ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG register field value. */
20508 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG_SET_MSK 0x00020000
20509 /* The mask used to clear the ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG register field value. */
20510 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG_CLR_MSK 0xfffdffff
20511 /* The reset value of the ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG register field. */
20512 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG_RESET 0x0
20513 /* Extracts the ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG field value from a register. */
20514 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG_GET(value) (((value) & 0x00020000) >> 17)
20515 /* Produces a ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG register field value suitable for setting the register. */
20516 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG_SET(value) (((value) << 17) & 0x00020000)
20517 
20518 /*
20519  * Field : DERRBUSFLG
20520  *
20521  * This bit is used to flag the last transaction was flagged with double-bit error.
20522  *
20523  * 1'b0: no effect.
20524  *
20525  * 1'b1: indicates double-bit error has occured. This will drive the bus to respond
20526  * the read with bus error. Write of one will clear this register double-but bus
20527  * error.
20528  *
20529  * Bus error occurs as part of the transaction but this indicates the SW the cause
20530  * of the error. This should only occur once per transaction
20531  *
20532  * Field Access Macros:
20533  *
20534  */
20535 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG register field. */
20536 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG_LSB 18
20537 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG register field. */
20538 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG_MSB 18
20539 /* The width in bits of the ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG register field. */
20540 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG_WIDTH 1
20541 /* The mask used to set the ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG register field value. */
20542 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG_SET_MSK 0x00040000
20543 /* The mask used to clear the ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG register field value. */
20544 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG_CLR_MSK 0xfffbffff
20545 /* The reset value of the ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG register field. */
20546 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG_RESET 0x0
20547 /* Extracts the ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG field value from a register. */
20548 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG_GET(value) (((value) & 0x00040000) >> 18)
20549 /* Produces a ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG register field value suitable for setting the register. */
20550 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG_SET(value) (((value) << 18) & 0x00040000)
20551 
20552 #ifndef __ASSEMBLY__
20553 /*
20554  * WARNING: The C register and register group struct declarations are provided for
20555  * convenience and illustrative purposes. They should, however, be used with
20556  * caution as the C language standard provides no guarantees about the alignment or
20557  * atomicity of device memory accesses. The recommended practice for coding device
20558  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
20559  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
20560  * alt_write_dword() functions for 64 bit registers.
20561  *
20562  * The struct declaration for register ALT_MPFE_HMC_ADP_INTSTAT.
20563  */
20564 struct ALT_MPFE_HMC_ADP_INTSTAT_s
20565 {
20566  volatile uint32_t SERRPENA : 1; /* ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA */
20567  volatile uint32_t DERRPENA : 1; /* ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA */
20568  volatile uint32_t HMI_PENA : 1; /* ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA */
20569  volatile uint32_t SEQ2CORE_PENA : 1; /* ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA */
20570  uint32_t : 12; /* *UNDEFINED* */
20571  volatile uint32_t ADDRMTCFLG : 1; /* ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG */
20572  volatile uint32_t ADDRPARFLG : 1; /* ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG */
20573  volatile uint32_t DERRBUSFLG : 1; /* ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG */
20574  uint32_t : 13; /* *UNDEFINED* */
20575 };
20576 
20577 /* The typedef declaration for register ALT_MPFE_HMC_ADP_INTSTAT. */
20578 typedef struct ALT_MPFE_HMC_ADP_INTSTAT_s ALT_MPFE_HMC_ADP_INTSTAT_t;
20579 #endif /* __ASSEMBLY__ */
20580 
20581 /* The reset value of the ALT_MPFE_HMC_ADP_INTSTAT register. */
20582 #define ALT_MPFE_HMC_ADP_INTSTAT_RESET 0x00000000
20583 /* The byte offset of the ALT_MPFE_HMC_ADP_INTSTAT register from the beginning of the component. */
20584 #define ALT_MPFE_HMC_ADP_INTSTAT_OFST 0x120
20585 
20586 /*
20587  * Register : DIAGINTTEST
20588  *
20589  * Enable diagnostic errors
20590  *
20591  * Register Layout
20592  *
20593  * Bits | Access | Reset | Description
20594  * :--------|:-------|:------|:--------------------------------------
20595  * [0] | RW | 0x0 | ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA
20596  * [7:1] | ??? | 0x0 | *UNDEFINED*
20597  * [8] | RW | 0x0 | ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA
20598  * [15:9] | ??? | 0x0 | *UNDEFINED*
20599  * [16] | RW | 0x0 | ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC
20600  * [23:17] | ??? | 0x0 | *UNDEFINED*
20601  * [24] | RW | 0x0 | ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR
20602  * [31:25] | ??? | 0x0 | *UNDEFINED*
20603  *
20604  */
20605 /*
20606  * Field : TSERRA
20607  *
20608  * This bit is used to test a single-bit error.
20609  *
20610  * 1'b0: Write of zero has no effect.
20611  *
20612  * 1'b1: When this bit is set to 1, serr_req signal is generated to the system
20613  * manager when the ECC decoder detects a single-bit error. By writing to this bit,
20614  * SERRPENA bit will be pending. Write of one to SERRPENA will clear this bit.
20615  *
20616  * Field Enumeration Values:
20617  *
20618  * Enum | Value | Description
20619  * :-------------------------------------------|:------|:------------
20620  * ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA_E_STAY | 0x0 |
20621  * ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA_E_SET | 0x1 |
20622  *
20623  * Field Access Macros:
20624  *
20625  */
20626 /*
20627  * Enumerated value for register field ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA
20628  *
20629  */
20630 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA_E_STAY 0x0
20631 /*
20632  * Enumerated value for register field ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA
20633  *
20634  */
20635 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA_E_SET 0x1
20636 
20637 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA register field. */
20638 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA_LSB 0
20639 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA register field. */
20640 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA_MSB 0
20641 /* The width in bits of the ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA register field. */
20642 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA_WIDTH 1
20643 /* The mask used to set the ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA register field value. */
20644 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA_SET_MSK 0x00000001
20645 /* The mask used to clear the ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA register field value. */
20646 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA_CLR_MSK 0xfffffffe
20647 /* The reset value of the ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA register field. */
20648 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA_RESET 0x0
20649 /* Extracts the ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA field value from a register. */
20650 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA_GET(value) (((value) & 0x00000001) >> 0)
20651 /* Produces a ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA register field value suitable for setting the register. */
20652 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA_SET(value) (((value) << 0) & 0x00000001)
20653 
20654 /*
20655  * Field : TDERRA
20656  *
20657  * Diagnostic enable of Double-bit error.
20658  *
20659  * This bit is used to test double-bit error.
20660  *
20661  * 1'b0: Write of zero has no effect.
20662  *
20663  * 1'b1: When this bit is set to 1, derr_req signal is generated to the system
20664  * manager when the ECC decoder detects a double-bit error. By writing to this bit,
20665  * DERRBUSFLG bit will be pending. Write of one to DERRBUSFLG will clear this bit.
20666  * SW needs to explicitly write to DERRPENA to clear it.
20667  *
20668  * Field Enumeration Values:
20669  *
20670  * Enum | Value | Description
20671  * :-------------------------------------------|:------|:------------
20672  * ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA_E_STAY | 0x0 |
20673  * ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA_E_SET | 0x1 |
20674  *
20675  * Field Access Macros:
20676  *
20677  */
20678 /*
20679  * Enumerated value for register field ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA
20680  *
20681  */
20682 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA_E_STAY 0x0
20683 /*
20684  * Enumerated value for register field ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA
20685  *
20686  */
20687 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA_E_SET 0x1
20688 
20689 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA register field. */
20690 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA_LSB 8
20691 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA register field. */
20692 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA_MSB 8
20693 /* The width in bits of the ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA register field. */
20694 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA_WIDTH 1
20695 /* The mask used to set the ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA register field value. */
20696 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA_SET_MSK 0x00000100
20697 /* The mask used to clear the ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA register field value. */
20698 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA_CLR_MSK 0xfffffeff
20699 /* The reset value of the ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA register field. */
20700 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA_RESET 0x0
20701 /* Extracts the ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA field value from a register. */
20702 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA_GET(value) (((value) & 0x00000100) >> 8)
20703 /* Produces a ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA register field value suitable for setting the register. */
20704 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA_SET(value) (((value) << 8) & 0x00000100)
20705 
20706 /*
20707  * Field : TADDRMTC
20708  *
20709  * Diagnostic enable of Address mismatch error.
20710  *
20711  * This bit is used to flag that the last transaction was flagged with address
20712  * mismatch error.
20713  *
20714  * 1'b0: Disables generating address match bus error as part of the transaction.
20715  *
20716  * 1'b1: When this bit is set to 1, derr_req signal is generated to the system
20717  * manager when the ECC decoder detects a ecc address mismatch. By writing to this
20718  * bit, ADDRMTCFLG bit will be pending. Write of one to ADDRMTCFLG will clear this
20719  * bit. SW needs to explicitly write to DERRPENA to clear it.
20720  *
20721  * Field Enumeration Values:
20722  *
20723  * Enum | Value | Description
20724  * :---------------------------------------------|:------|:------------
20725  * ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC_E_STAY | 0x0 |
20726  * ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC_E_SET | 0x1 |
20727  *
20728  * Field Access Macros:
20729  *
20730  */
20731 /*
20732  * Enumerated value for register field ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC
20733  *
20734  */
20735 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC_E_STAY 0x0
20736 /*
20737  * Enumerated value for register field ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC
20738  *
20739  */
20740 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC_E_SET 0x1
20741 
20742 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC register field. */
20743 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC_LSB 16
20744 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC register field. */
20745 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC_MSB 16
20746 /* The width in bits of the ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC register field. */
20747 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC_WIDTH 1
20748 /* The mask used to set the ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC register field value. */
20749 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC_SET_MSK 0x00010000
20750 /* The mask used to clear the ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC register field value. */
20751 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC_CLR_MSK 0xfffeffff
20752 /* The reset value of the ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC register field. */
20753 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC_RESET 0x0
20754 /* Extracts the ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC field value from a register. */
20755 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC_GET(value) (((value) & 0x00010000) >> 16)
20756 /* Produces a ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC register field value suitable for setting the register. */
20757 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC_SET(value) (((value) << 16) & 0x00010000)
20758 
20759 /*
20760  * Field : TADDRPAR
20761  *
20762  * Diagnostic of address parity of DDR4.
20763  *
20764  * This bit is used to test the address parity error path.
20765  *
20766  * 1'b0: Disables generating address match bus error as part of the transaction.
20767  *
20768  * 1'b1: When this bit is set to 1, derr_req signal is generated to the system
20769  * manager when the ECC decoder detects an ecc address parity error. By writing to
20770  * this bit, ADDRPARFLG bit will be pending. Write of one to ADDRPARFLG will clear
20771  * this bit. SW needs to explicitly write to DERRPENA to clear it.
20772  *
20773  * Field Enumeration Values:
20774  *
20775  * Enum | Value | Description
20776  * :---------------------------------------------|:------|:------------
20777  * ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR_E_STAY | 0x0 |
20778  * ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR_E_SET | 0x1 |
20779  *
20780  * Field Access Macros:
20781  *
20782  */
20783 /*
20784  * Enumerated value for register field ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR
20785  *
20786  */
20787 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR_E_STAY 0x0
20788 /*
20789  * Enumerated value for register field ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR
20790  *
20791  */
20792 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR_E_SET 0x1
20793 
20794 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR register field. */
20795 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR_LSB 24
20796 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR register field. */
20797 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR_MSB 24
20798 /* The width in bits of the ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR register field. */
20799 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR_WIDTH 1
20800 /* The mask used to set the ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR register field value. */
20801 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR_SET_MSK 0x01000000
20802 /* The mask used to clear the ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR register field value. */
20803 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR_CLR_MSK 0xfeffffff
20804 /* The reset value of the ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR register field. */
20805 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR_RESET 0x0
20806 /* Extracts the ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR field value from a register. */
20807 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR_GET(value) (((value) & 0x01000000) >> 24)
20808 /* Produces a ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR register field value suitable for setting the register. */
20809 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR_SET(value) (((value) << 24) & 0x01000000)
20810 
20811 #ifndef __ASSEMBLY__
20812 /*
20813  * WARNING: The C register and register group struct declarations are provided for
20814  * convenience and illustrative purposes. They should, however, be used with
20815  * caution as the C language standard provides no guarantees about the alignment or
20816  * atomicity of device memory accesses. The recommended practice for coding device
20817  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
20818  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
20819  * alt_write_dword() functions for 64 bit registers.
20820  *
20821  * The struct declaration for register ALT_MPFE_HMC_ADP_DIAGINTTEST.
20822  */
20823 struct ALT_MPFE_HMC_ADP_DIAGINTTEST_s
20824 {
20825  volatile uint32_t TSERRA : 1; /* ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA */
20826  uint32_t : 7; /* *UNDEFINED* */
20827  volatile uint32_t TDERRA : 1; /* ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA */
20828  uint32_t : 7; /* *UNDEFINED* */
20829  volatile uint32_t TADDRMTC : 1; /* ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC */
20830  uint32_t : 7; /* *UNDEFINED* */
20831  volatile uint32_t TADDRPAR : 1; /* ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR */
20832  uint32_t : 7; /* *UNDEFINED* */
20833 };
20834 
20835 /* The typedef declaration for register ALT_MPFE_HMC_ADP_DIAGINTTEST. */
20836 typedef struct ALT_MPFE_HMC_ADP_DIAGINTTEST_s ALT_MPFE_HMC_ADP_DIAGINTTEST_t;
20837 #endif /* __ASSEMBLY__ */
20838 
20839 /* The reset value of the ALT_MPFE_HMC_ADP_DIAGINTTEST register. */
20840 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_RESET 0x00000000
20841 /* The byte offset of the ALT_MPFE_HMC_ADP_DIAGINTTEST register from the beginning of the component. */
20842 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_OFST 0x124
20843 
20844 /*
20845  * Register : MODSTAT
20846  *
20847  * Counter feature status flag
20848  *
20849  * Register Layout
20850  *
20851  * Bits | Access | Reset | Description
20852  * :-------|:-------|:------|:-----------------------------------------
20853  * [0] | RW | 0x0 | ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA
20854  * [7:1] | ??? | 0x0 | *UNDEFINED*
20855  * [8] | RW | 0x0 | ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG
20856  * [31:9] | ??? | 0x0 | *UNDEFINED*
20857  *
20858  */
20859 /*
20860  * Field : CMPFLGA
20861  *
20862  * Counter Match occurred flag.
20863  *
20864  * This bit indicates that the internal counter and SERRCNT value matched.
20865  *
20866  * 1'b0: read indicates match check of SERR interrupt on compare match is disabled.
20867  *
20868  * 1'b1: read indicates compare has matched. Write of one will clear the pending
20869  * compare match. This will not de-assert the serr_req signal - software needs to
20870  * write to serrpen bit to clear the interrupt.
20871  *
20872  * When the match occurs, additional errors will not increment count until the
20873  * compare status flag is cleared. If the software does not change the SERRCNT
20874  * register prior to clearing this flag or reset the internal counter, next
20875  * increment of internal counter could set this flag again in the next cycle.
20876  *
20877  * Field Access Macros:
20878  *
20879  */
20880 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA register field. */
20881 #define ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA_LSB 0
20882 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA register field. */
20883 #define ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA_MSB 0
20884 /* The width in bits of the ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA register field. */
20885 #define ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA_WIDTH 1
20886 /* The mask used to set the ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA register field value. */
20887 #define ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA_SET_MSK 0x00000001
20888 /* The mask used to clear the ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA register field value. */
20889 #define ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA_CLR_MSK 0xfffffffe
20890 /* The reset value of the ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA register field. */
20891 #define ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA_RESET 0x0
20892 /* Extracts the ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA field value from a register. */
20893 #define ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA_GET(value) (((value) & 0x00000001) >> 0)
20894 /* Produces a ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA register field value suitable for setting the register. */
20895 #define ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA_SET(value) (((value) << 0) & 0x00000001)
20896 
20897 /*
20898  * Field : AUTOWB_DROP_FLG
20899  *
20900  * Auto writeback counter match flag.
20901  *
20902  * This bit indicates that the internal autoWB counter and autoWB_drop_cnt value
20903  * matched.
20904  *
20905  * 1'b0: read indicates match check of hmi_intr interrupt on compare match is
20906  * disabled.
20907  *
20908  * 1'b1: read indicates compare has matched. Write of one will clear the pending
20909  * compare match. This will not de-assert the hmi_intr signal - software needs to
20910  * write to hmi_intrpen bit to clear the interrupt.
20911  *
20912  * When the match occurs, additional errors will not increment count until the
20913  * compare status flag is cleared. If the software does not change the
20914  * autoWB_drop_cnt register prior to clearing this flag or reset the autoWB
20915  * counter, next increment of internal autoWB counter could set this flag in the
20916  * next cycle.
20917  *
20918  * Field Access Macros:
20919  *
20920  */
20921 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG register field. */
20922 #define ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG_LSB 8
20923 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG register field. */
20924 #define ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG_MSB 8
20925 /* The width in bits of the ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG register field. */
20926 #define ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG_WIDTH 1
20927 /* The mask used to set the ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG register field value. */
20928 #define ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG_SET_MSK 0x00000100
20929 /* The mask used to clear the ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG register field value. */
20930 #define ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG_CLR_MSK 0xfffffeff
20931 /* The reset value of the ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG register field. */
20932 #define ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG_RESET 0x0
20933 /* Extracts the ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG field value from a register. */
20934 #define ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG_GET(value) (((value) & 0x00000100) >> 8)
20935 /* Produces a ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG register field value suitable for setting the register. */
20936 #define ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG_SET(value) (((value) << 8) & 0x00000100)
20937 
20938 #ifndef __ASSEMBLY__
20939 /*
20940  * WARNING: The C register and register group struct declarations are provided for
20941  * convenience and illustrative purposes. They should, however, be used with
20942  * caution as the C language standard provides no guarantees about the alignment or
20943  * atomicity of device memory accesses. The recommended practice for coding device
20944  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
20945  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
20946  * alt_write_dword() functions for 64 bit registers.
20947  *
20948  * The struct declaration for register ALT_MPFE_HMC_ADP_MODSTAT.
20949  */
20950 struct ALT_MPFE_HMC_ADP_MODSTAT_s
20951 {
20952  volatile uint32_t CMPFLGA : 1; /* ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA */
20953  uint32_t : 7; /* *UNDEFINED* */
20954  volatile uint32_t AUTOWB_DROP_FLG : 1; /* ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG */
20955  uint32_t : 23; /* *UNDEFINED* */
20956 };
20957 
20958 /* The typedef declaration for register ALT_MPFE_HMC_ADP_MODSTAT. */
20959 typedef struct ALT_MPFE_HMC_ADP_MODSTAT_s ALT_MPFE_HMC_ADP_MODSTAT_t;
20960 #endif /* __ASSEMBLY__ */
20961 
20962 /* The reset value of the ALT_MPFE_HMC_ADP_MODSTAT register. */
20963 #define ALT_MPFE_HMC_ADP_MODSTAT_RESET 0x00000000
20964 /* The byte offset of the ALT_MPFE_HMC_ADP_MODSTAT register from the beginning of the component. */
20965 #define ALT_MPFE_HMC_ADP_MODSTAT_OFST 0x128
20966 
20967 /*
20968  * Register : DERRADDRA
20969  *
20970  * Double-bit error address
20971  *
20972  * Register Layout
20973  *
20974  * Bits | Access | Reset | Description
20975  * :-------|:-------|:------|:------------------------------------
20976  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS
20977  *
20978  */
20979 /*
20980  * Field : DADDRESS
20981  *
20982  * Recent DBE address.
20983  *
20984  * This register shows the address of the current double-bit error. RAM size will
20985  * determine the maximum number of address bits.
20986  *
20987  * This address is logged when a new derr_req or bus error is generated to the
20988  * system. This is gated by the ecc_en enable bit and derrinten bit.
20989  *
20990  * Field Access Macros:
20991  *
20992  */
20993 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS register field. */
20994 #define ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS_LSB 0
20995 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS register field. */
20996 #define ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS_MSB 31
20997 /* The width in bits of the ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS register field. */
20998 #define ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS_WIDTH 32
20999 /* The mask used to set the ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS register field value. */
21000 #define ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS_SET_MSK 0xffffffff
21001 /* The mask used to clear the ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS register field value. */
21002 #define ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS_CLR_MSK 0x00000000
21003 /* The reset value of the ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS register field. */
21004 #define ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS_RESET 0x0
21005 /* Extracts the ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS field value from a register. */
21006 #define ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS_GET(value) (((value) & 0xffffffff) >> 0)
21007 /* Produces a ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS register field value suitable for setting the register. */
21008 #define ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS_SET(value) (((value) << 0) & 0xffffffff)
21009 
21010 #ifndef __ASSEMBLY__
21011 /*
21012  * WARNING: The C register and register group struct declarations are provided for
21013  * convenience and illustrative purposes. They should, however, be used with
21014  * caution as the C language standard provides no guarantees about the alignment or
21015  * atomicity of device memory accesses. The recommended practice for coding device
21016  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21017  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21018  * alt_write_dword() functions for 64 bit registers.
21019  *
21020  * The struct declaration for register ALT_MPFE_HMC_ADP_DERRADDRA.
21021  */
21022 struct ALT_MPFE_HMC_ADP_DERRADDRA_s
21023 {
21024  volatile uint32_t DADDRESS : 32; /* ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS */
21025 };
21026 
21027 /* The typedef declaration for register ALT_MPFE_HMC_ADP_DERRADDRA. */
21028 typedef struct ALT_MPFE_HMC_ADP_DERRADDRA_s ALT_MPFE_HMC_ADP_DERRADDRA_t;
21029 #endif /* __ASSEMBLY__ */
21030 
21031 /* The reset value of the ALT_MPFE_HMC_ADP_DERRADDRA register. */
21032 #define ALT_MPFE_HMC_ADP_DERRADDRA_RESET 0x00000000
21033 /* The byte offset of the ALT_MPFE_HMC_ADP_DERRADDRA register from the beginning of the component. */
21034 #define ALT_MPFE_HMC_ADP_DERRADDRA_OFST 0x12c
21035 
21036 /*
21037  * Register : SERRADDRA
21038  *
21039  * Single-bit error address
21040  *
21041  * Register Layout
21042  *
21043  * Bits | Access | Reset | Description
21044  * :-------|:-------|:------|:------------------------------------
21045  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS
21046  *
21047  */
21048 /*
21049  * Field : SADDRESS
21050  *
21051  * Recent single-bit error address.
21052  *
21053  * This register shows the address of the current single-bit error. This address is
21054  * logged when a new serr_req is generated to the system. This is gated by the
21055  * single-bit error interrupt enable and ecc_en.
21056  *
21057  * Field Access Macros:
21058  *
21059  */
21060 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS register field. */
21061 #define ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS_LSB 0
21062 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS register field. */
21063 #define ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS_MSB 31
21064 /* The width in bits of the ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS register field. */
21065 #define ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS_WIDTH 32
21066 /* The mask used to set the ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS register field value. */
21067 #define ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS_SET_MSK 0xffffffff
21068 /* The mask used to clear the ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS register field value. */
21069 #define ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS_CLR_MSK 0x00000000
21070 /* The reset value of the ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS register field. */
21071 #define ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS_RESET 0x0
21072 /* Extracts the ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS field value from a register. */
21073 #define ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS_GET(value) (((value) & 0xffffffff) >> 0)
21074 /* Produces a ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS register field value suitable for setting the register. */
21075 #define ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS_SET(value) (((value) << 0) & 0xffffffff)
21076 
21077 #ifndef __ASSEMBLY__
21078 /*
21079  * WARNING: The C register and register group struct declarations are provided for
21080  * convenience and illustrative purposes. They should, however, be used with
21081  * caution as the C language standard provides no guarantees about the alignment or
21082  * atomicity of device memory accesses. The recommended practice for coding device
21083  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21084  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21085  * alt_write_dword() functions for 64 bit registers.
21086  *
21087  * The struct declaration for register ALT_MPFE_HMC_ADP_SERRADDRA.
21088  */
21089 struct ALT_MPFE_HMC_ADP_SERRADDRA_s
21090 {
21091  volatile uint32_t SADDRESS : 32; /* ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS */
21092 };
21093 
21094 /* The typedef declaration for register ALT_MPFE_HMC_ADP_SERRADDRA. */
21095 typedef struct ALT_MPFE_HMC_ADP_SERRADDRA_s ALT_MPFE_HMC_ADP_SERRADDRA_t;
21096 #endif /* __ASSEMBLY__ */
21097 
21098 /* The reset value of the ALT_MPFE_HMC_ADP_SERRADDRA register. */
21099 #define ALT_MPFE_HMC_ADP_SERRADDRA_RESET 0x00000000
21100 /* The byte offset of the ALT_MPFE_HMC_ADP_SERRADDRA register from the beginning of the component. */
21101 #define ALT_MPFE_HMC_ADP_SERRADDRA_OFST 0x130
21102 
21103 /*
21104  * Register : AUTOWB_CORRADDR
21105  *
21106  * This register shows the address of the current autoWB correction SBE.
21107  *
21108  * Register Layout
21109  *
21110  * Bits | Access | Reset | Description
21111  * :-------|:-------|:------|:--------------------------------------------
21112  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS
21113  *
21114  */
21115 /*
21116  * Field : SWBADDRESS
21117  *
21118  * recent autoWB correction address.
21119  *
21120  * This register shows the address of the current autoWB correction single-bit
21121  * error. This address is logged when a new serr_req is generated to the system.
21122  * This is gated by the single-bit error interrupt enable and ecc_en.
21123  *
21124  * Field Access Macros:
21125  *
21126  */
21127 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS register field. */
21128 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS_LSB 0
21129 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS register field. */
21130 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS_MSB 31
21131 /* The width in bits of the ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS register field. */
21132 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS_WIDTH 32
21133 /* The mask used to set the ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS register field value. */
21134 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS_SET_MSK 0xffffffff
21135 /* The mask used to clear the ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS register field value. */
21136 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS_CLR_MSK 0x00000000
21137 /* The reset value of the ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS register field. */
21138 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS_RESET 0x0
21139 /* Extracts the ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS field value from a register. */
21140 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS_GET(value) (((value) & 0xffffffff) >> 0)
21141 /* Produces a ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS register field value suitable for setting the register. */
21142 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS_SET(value) (((value) << 0) & 0xffffffff)
21143 
21144 #ifndef __ASSEMBLY__
21145 /*
21146  * WARNING: The C register and register group struct declarations are provided for
21147  * convenience and illustrative purposes. They should, however, be used with
21148  * caution as the C language standard provides no guarantees about the alignment or
21149  * atomicity of device memory accesses. The recommended practice for coding device
21150  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21151  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21152  * alt_write_dword() functions for 64 bit registers.
21153  *
21154  * The struct declaration for register ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR.
21155  */
21156 struct ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_s
21157 {
21158  volatile uint32_t SWBADDRESS : 32; /* ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS */
21159 };
21160 
21161 /* The typedef declaration for register ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR. */
21162 typedef struct ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_s ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_t;
21163 #endif /* __ASSEMBLY__ */
21164 
21165 /* The reset value of the ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR register. */
21166 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_RESET 0x00000000
21167 /* The byte offset of the ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR register from the beginning of the component. */
21168 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_OFST 0x138
21169 
21170 /*
21171  * Register : SERRCNTREG
21172  *
21173  * Maximum counter value for single-bit error interrupt
21174  *
21175  * Register Layout
21176  *
21177  * Bits | Access | Reset | Description
21178  * :-------|:-------|:------|:------------------------------------
21179  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT
21180  *
21181  */
21182 /*
21183  * Field : SERRCNT
21184  *
21185  * Compare value for the internal single-bit errors.
21186  *
21187  * This register sets the value to compare with the internal counter. Software
21188  * should write to this register before enabling the interrupt on compare.
21189  *
21190  * 0x0: If the serrcnt bits are not modified before enabling the intoncmp, internal
21191  * counter=0 and serrcnt=0, serr compare interrupt will not occur. Default after
21192  * reset.
21193  *
21194  * Nonzero: if internal counter == serrcnt == nonzero will create a serr compare
21195  * interrupt.
21196  *
21197  * When the compare matches, autoWB_drop_cmpflga will be set.
21198  *
21199  * Field Access Macros:
21200  *
21201  */
21202 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT register field. */
21203 #define ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT_LSB 0
21204 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT register field. */
21205 #define ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT_MSB 31
21206 /* The width in bits of the ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT register field. */
21207 #define ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT_WIDTH 32
21208 /* The mask used to set the ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT register field value. */
21209 #define ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT_SET_MSK 0xffffffff
21210 /* The mask used to clear the ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT register field value. */
21211 #define ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT_CLR_MSK 0x00000000
21212 /* The reset value of the ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT register field. */
21213 #define ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT_RESET 0x0
21214 /* Extracts the ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT field value from a register. */
21215 #define ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT_GET(value) (((value) & 0xffffffff) >> 0)
21216 /* Produces a ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT register field value suitable for setting the register. */
21217 #define ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT_SET(value) (((value) << 0) & 0xffffffff)
21218 
21219 #ifndef __ASSEMBLY__
21220 /*
21221  * WARNING: The C register and register group struct declarations are provided for
21222  * convenience and illustrative purposes. They should, however, be used with
21223  * caution as the C language standard provides no guarantees about the alignment or
21224  * atomicity of device memory accesses. The recommended practice for coding device
21225  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21226  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21227  * alt_write_dword() functions for 64 bit registers.
21228  *
21229  * The struct declaration for register ALT_MPFE_HMC_ADP_SERRCNTREG.
21230  */
21231 struct ALT_MPFE_HMC_ADP_SERRCNTREG_s
21232 {
21233  volatile uint32_t SERRCNT : 32; /* ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT */
21234 };
21235 
21236 /* The typedef declaration for register ALT_MPFE_HMC_ADP_SERRCNTREG. */
21237 typedef struct ALT_MPFE_HMC_ADP_SERRCNTREG_s ALT_MPFE_HMC_ADP_SERRCNTREG_t;
21238 #endif /* __ASSEMBLY__ */
21239 
21240 /* The reset value of the ALT_MPFE_HMC_ADP_SERRCNTREG register. */
21241 #define ALT_MPFE_HMC_ADP_SERRCNTREG_RESET 0x00000000
21242 /* The byte offset of the ALT_MPFE_HMC_ADP_SERRCNTREG register from the beginning of the component. */
21243 #define ALT_MPFE_HMC_ADP_SERRCNTREG_OFST 0x13c
21244 
21245 /*
21246  * Register : AUTOWB_DROP_CNTREG
21247  *
21248  * Maximum counter value for AUTOWB correction interrupt
21249  *
21250  * Register Layout
21251  *
21252  * Bits | Access | Reset | Description
21253  * :-------|:-------|:------|:----------------------------------------
21254  * [31:0] | RW | 0x1 | ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT
21255  *
21256  */
21257 /*
21258  * Field : CNT
21259  *
21260  * Compare value for the internal autoWB correction count.
21261  *
21262  * This register sets the value to compare with the autoWB internal counter.
21263  * Software should write to this register before enabling the interrupt on compare.
21264  *
21265  * 0x1: If the autoWB_drop_cntreg bits are not modified before enabling the
21266  * hmi_intr, autoWB internal counter=0 and autoWB_dop_cnt =1, serr compare
21267  * interrupt will not occur. Default after reset.
21268  *
21269  * Nonzero: if autoWB internal counter == autoWB_drop_cnt == nonzero will create a
21270  * serr compare interrupt.
21271  *
21272  * When the compare matches, autoWB_drop_flg will be set.
21273  *
21274  * Field Access Macros:
21275  *
21276  */
21277 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT register field. */
21278 #define ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT_LSB 0
21279 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT register field. */
21280 #define ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT_MSB 31
21281 /* The width in bits of the ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT register field. */
21282 #define ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT_WIDTH 32
21283 /* The mask used to set the ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT register field value. */
21284 #define ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT_SET_MSK 0xffffffff
21285 /* The mask used to clear the ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT register field value. */
21286 #define ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT_CLR_MSK 0x00000000
21287 /* The reset value of the ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT register field. */
21288 #define ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT_RESET 0x1
21289 /* Extracts the ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT field value from a register. */
21290 #define ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21291 /* Produces a ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT register field value suitable for setting the register. */
21292 #define ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT_SET(value) (((value) << 0) & 0xffffffff)
21293 
21294 #ifndef __ASSEMBLY__
21295 /*
21296  * WARNING: The C register and register group struct declarations are provided for
21297  * convenience and illustrative purposes. They should, however, be used with
21298  * caution as the C language standard provides no guarantees about the alignment or
21299  * atomicity of device memory accesses. The recommended practice for coding device
21300  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21301  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21302  * alt_write_dword() functions for 64 bit registers.
21303  *
21304  * The struct declaration for register ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG.
21305  */
21306 struct ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_s
21307 {
21308  volatile uint32_t CNT : 32; /* ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT */
21309 };
21310 
21311 /* The typedef declaration for register ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG. */
21312 typedef struct ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_s ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_t;
21313 #endif /* __ASSEMBLY__ */
21314 
21315 /* The reset value of the ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG register. */
21316 #define ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_RESET 0x00000001
21317 /* The byte offset of the ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG register from the beginning of the component. */
21318 #define ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_OFST 0x140
21319 
21320 /*
21321  * Register : ECC_REG2WRECCDATABUS
21322  *
21323  * ECC from register associated to data which will be written to the RAM
21324  *
21325  * Register Layout
21326  *
21327  * Bits | Access | Reset | Description
21328  * :--------|:-------|:------|:----------------------------------------------
21329  * [7:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS
21330  * [15:8] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS
21331  * [23:16] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS
21332  * [31:24] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS
21333  *
21334  */
21335 /*
21336  * Field : ECC0BUS
21337  *
21338  * ECC from register associated to data [63:0] which will be written to the RAM
21339  *
21340  * Field Access Macros:
21341  *
21342  */
21343 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS register field. */
21344 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS_LSB 0
21345 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS register field. */
21346 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS_MSB 7
21347 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS register field. */
21348 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS_WIDTH 8
21349 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS register field value. */
21350 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS_SET_MSK 0x000000ff
21351 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS register field value. */
21352 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS_CLR_MSK 0xffffff00
21353 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS register field. */
21354 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS_RESET 0x0
21355 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS field value from a register. */
21356 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
21357 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS register field value suitable for setting the register. */
21358 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
21359 
21360 /*
21361  * Field : ECC1BUS
21362  *
21363  * ECC from register associated to data [127:64] which will be written to the RAM
21364  *
21365  * Field Access Macros:
21366  *
21367  */
21368 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS register field. */
21369 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS_LSB 8
21370 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS register field. */
21371 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS_MSB 15
21372 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS register field. */
21373 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS_WIDTH 8
21374 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS register field value. */
21375 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS_SET_MSK 0x0000ff00
21376 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS register field value. */
21377 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS_CLR_MSK 0xffff00ff
21378 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS register field. */
21379 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS_RESET 0x0
21380 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS field value from a register. */
21381 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
21382 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS register field value suitable for setting the register. */
21383 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
21384 
21385 /*
21386  * Field : ECC2BUS
21387  *
21388  * ECC from register associated to data [191:128] which will be written to the RAM
21389  *
21390  * Field Access Macros:
21391  *
21392  */
21393 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS register field. */
21394 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS_LSB 16
21395 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS register field. */
21396 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS_MSB 23
21397 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS register field. */
21398 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS_WIDTH 8
21399 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS register field value. */
21400 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS_SET_MSK 0x00ff0000
21401 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS register field value. */
21402 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS_CLR_MSK 0xff00ffff
21403 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS register field. */
21404 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS_RESET 0x0
21405 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS field value from a register. */
21406 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
21407 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS register field value suitable for setting the register. */
21408 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
21409 
21410 /*
21411  * Field : ECC3BUS
21412  *
21413  * ECC from register associated to data [255:192] which will be written to the RAM
21414  *
21415  * Field Access Macros:
21416  *
21417  */
21418 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS register field. */
21419 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS_LSB 24
21420 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS register field. */
21421 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS_MSB 31
21422 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS register field. */
21423 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS_WIDTH 8
21424 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS register field value. */
21425 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS_SET_MSK 0xff000000
21426 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS register field value. */
21427 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS_CLR_MSK 0x00ffffff
21428 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS register field. */
21429 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS_RESET 0x0
21430 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS field value from a register. */
21431 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
21432 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS register field value suitable for setting the register. */
21433 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
21434 
21435 #ifndef __ASSEMBLY__
21436 /*
21437  * WARNING: The C register and register group struct declarations are provided for
21438  * convenience and illustrative purposes. They should, however, be used with
21439  * caution as the C language standard provides no guarantees about the alignment or
21440  * atomicity of device memory accesses. The recommended practice for coding device
21441  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21442  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21443  * alt_write_dword() functions for 64 bit registers.
21444  *
21445  * The struct declaration for register ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS.
21446  */
21447 struct ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_s
21448 {
21449  volatile uint32_t ECC0BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS */
21450  volatile uint32_t ECC1BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS */
21451  volatile uint32_t ECC2BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS */
21452  volatile uint32_t ECC3BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS */
21453 };
21454 
21455 /* The typedef declaration for register ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS. */
21456 typedef struct ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_s ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_t;
21457 #endif /* __ASSEMBLY__ */
21458 
21459 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS register. */
21460 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_RESET 0x00000000
21461 /* The byte offset of the ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS register from the beginning of the component. */
21462 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_OFST 0x144
21463 
21464 /*
21465  * Register : ECC_RDECCDATA2REGBUS
21466  *
21467  * ECC of data from RAM will be written to register
21468  *
21469  * Register Layout
21470  *
21471  * Bits | Access | Reset | Description
21472  * :--------|:-------|:------|:----------------------------------------------
21473  * [7:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS
21474  * [15:8] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS
21475  * [23:16] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS
21476  * [31:24] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS
21477  *
21478  */
21479 /*
21480  * Field : ECC0BUS
21481  *
21482  * ECC of data [63:0] from RAM which will be written to register.
21483  *
21484  * Based on the DDR IO width, unimplemented bytes of this register will read as
21485  * zero.
21486  *
21487  * Field Access Macros:
21488  *
21489  */
21490 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS register field. */
21491 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS_LSB 0
21492 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS register field. */
21493 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS_MSB 7
21494 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS register field. */
21495 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS_WIDTH 8
21496 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS register field value. */
21497 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS_SET_MSK 0x000000ff
21498 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS register field value. */
21499 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS_CLR_MSK 0xffffff00
21500 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS register field. */
21501 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS_RESET 0x0
21502 /* Extracts the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS field value from a register. */
21503 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
21504 /* Produces a ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS register field value suitable for setting the register. */
21505 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
21506 
21507 /*
21508  * Field : ECC1BUS
21509  *
21510  * ECC of data [127:64] from RAM which will be written to register.
21511  *
21512  * Based on the DDR IO width, unimplemented bytes of this register will read as
21513  * zero.
21514  *
21515  * Field Access Macros:
21516  *
21517  */
21518 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS register field. */
21519 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS_LSB 8
21520 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS register field. */
21521 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS_MSB 15
21522 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS register field. */
21523 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS_WIDTH 8
21524 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS register field value. */
21525 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS_SET_MSK 0x0000ff00
21526 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS register field value. */
21527 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS_CLR_MSK 0xffff00ff
21528 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS register field. */
21529 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS_RESET 0x0
21530 /* Extracts the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS field value from a register. */
21531 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
21532 /* Produces a ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS register field value suitable for setting the register. */
21533 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
21534 
21535 /*
21536  * Field : ECC2BUS
21537  *
21538  * ECC of data [191:128] from RAM which will be written to register.
21539  *
21540  * Based on the DDR IO width, unimplemented bytes of this register will read as
21541  * zero.
21542  *
21543  * Field Access Macros:
21544  *
21545  */
21546 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS register field. */
21547 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS_LSB 16
21548 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS register field. */
21549 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS_MSB 23
21550 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS register field. */
21551 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS_WIDTH 8
21552 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS register field value. */
21553 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS_SET_MSK 0x00ff0000
21554 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS register field value. */
21555 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS_CLR_MSK 0xff00ffff
21556 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS register field. */
21557 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS_RESET 0x0
21558 /* Extracts the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS field value from a register. */
21559 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
21560 /* Produces a ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS register field value suitable for setting the register. */
21561 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
21562 
21563 /*
21564  * Field : ECC3BUS
21565  *
21566  * ECC of data [255:192] from RAM which will be written to register.
21567  *
21568  * Based on the DDR IO width, unimplemented bytes of this register will read as
21569  * zero.
21570  *
21571  * Field Access Macros:
21572  *
21573  */
21574 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS register field. */
21575 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS_LSB 24
21576 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS register field. */
21577 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS_MSB 31
21578 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS register field. */
21579 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS_WIDTH 8
21580 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS register field value. */
21581 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS_SET_MSK 0xff000000
21582 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS register field value. */
21583 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS_CLR_MSK 0x00ffffff
21584 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS register field. */
21585 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS_RESET 0x0
21586 /* Extracts the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS field value from a register. */
21587 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
21588 /* Produces a ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS register field value suitable for setting the register. */
21589 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
21590 
21591 #ifndef __ASSEMBLY__
21592 /*
21593  * WARNING: The C register and register group struct declarations are provided for
21594  * convenience and illustrative purposes. They should, however, be used with
21595  * caution as the C language standard provides no guarantees about the alignment or
21596  * atomicity of device memory accesses. The recommended practice for coding device
21597  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21598  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21599  * alt_write_dword() functions for 64 bit registers.
21600  *
21601  * The struct declaration for register ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS.
21602  */
21603 struct ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_s
21604 {
21605  volatile uint32_t ECC0BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS */
21606  volatile uint32_t ECC1BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS */
21607  volatile uint32_t ECC2BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS */
21608  volatile uint32_t ECC3BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS */
21609 };
21610 
21611 /* The typedef declaration for register ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS. */
21612 typedef struct ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_s ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_t;
21613 #endif /* __ASSEMBLY__ */
21614 
21615 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS register. */
21616 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_RESET 0x00000000
21617 /* The byte offset of the ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS register from the beginning of the component. */
21618 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_OFST 0x148
21619 
21620 /*
21621  * Register : ECC_REG2RDECCDATABUS
21622  *
21623  * ECC from register associated to RD data which will be written to hmc ecc
21624  *
21625  * Register Layout
21626  *
21627  * Bits | Access | Reset | Description
21628  * :--------|:-------|:------|:----------------------------------------------
21629  * [7:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS
21630  * [15:8] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS
21631  * [23:16] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS
21632  * [31:24] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS
21633  *
21634  */
21635 /*
21636  * Field : ECC0BUS
21637  *
21638  * ECC from register associated to RD data [63:0] which will be written to hmc ecc.
21639  *
21640  * Based on the DDR IO width, unimplemented bytes of this register will read as
21641  * zero.
21642  *
21643  * Field Access Macros:
21644  *
21645  */
21646 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS register field. */
21647 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS_LSB 0
21648 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS register field. */
21649 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS_MSB 7
21650 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS register field. */
21651 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS_WIDTH 8
21652 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS register field value. */
21653 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS_SET_MSK 0x000000ff
21654 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS register field value. */
21655 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS_CLR_MSK 0xffffff00
21656 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS register field. */
21657 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS_RESET 0x0
21658 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS field value from a register. */
21659 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
21660 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS register field value suitable for setting the register. */
21661 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
21662 
21663 /*
21664  * Field : ECC1BUS
21665  *
21666  * ECC from register associated to RD data [127:64] which will be written to hmc
21667  * ecc.
21668  *
21669  * Based on the DDR IO width, unimplemented bytes of this register will read as
21670  * zero.
21671  *
21672  * Field Access Macros:
21673  *
21674  */
21675 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS register field. */
21676 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS_LSB 8
21677 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS register field. */
21678 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS_MSB 15
21679 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS register field. */
21680 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS_WIDTH 8
21681 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS register field value. */
21682 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS_SET_MSK 0x0000ff00
21683 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS register field value. */
21684 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS_CLR_MSK 0xffff00ff
21685 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS register field. */
21686 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS_RESET 0x0
21687 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS field value from a register. */
21688 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
21689 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS register field value suitable for setting the register. */
21690 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
21691 
21692 /*
21693  * Field : ECC2BUS
21694  *
21695  * ECC from register associated to RD data [191:128] which will be written to hmc
21696  * ecc.
21697  *
21698  * Based on the DDR IO width, unimplemented bytes of this register will read as
21699  * zero.
21700  *
21701  * Field Access Macros:
21702  *
21703  */
21704 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS register field. */
21705 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS_LSB 16
21706 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS register field. */
21707 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS_MSB 23
21708 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS register field. */
21709 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS_WIDTH 8
21710 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS register field value. */
21711 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS_SET_MSK 0x00ff0000
21712 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS register field value. */
21713 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS_CLR_MSK 0xff00ffff
21714 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS register field. */
21715 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS_RESET 0x0
21716 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS field value from a register. */
21717 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
21718 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS register field value suitable for setting the register. */
21719 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
21720 
21721 /*
21722  * Field : ECC3BUS
21723  *
21724  * ECC from register associated to RD data [255:192] which will be written to hmc
21725  * ecc.
21726  *
21727  * Based on the DDR IO width, unimplemented bytes of this register will read as
21728  * zero.
21729  *
21730  * Field Access Macros:
21731  *
21732  */
21733 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS register field. */
21734 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS_LSB 24
21735 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS register field. */
21736 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS_MSB 31
21737 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS register field. */
21738 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS_WIDTH 8
21739 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS register field value. */
21740 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS_SET_MSK 0xff000000
21741 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS register field value. */
21742 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS_CLR_MSK 0x00ffffff
21743 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS register field. */
21744 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS_RESET 0x0
21745 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS field value from a register. */
21746 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
21747 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS register field value suitable for setting the register. */
21748 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
21749 
21750 #ifndef __ASSEMBLY__
21751 /*
21752  * WARNING: The C register and register group struct declarations are provided for
21753  * convenience and illustrative purposes. They should, however, be used with
21754  * caution as the C language standard provides no guarantees about the alignment or
21755  * atomicity of device memory accesses. The recommended practice for coding device
21756  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21757  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21758  * alt_write_dword() functions for 64 bit registers.
21759  *
21760  * The struct declaration for register ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS.
21761  */
21762 struct ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_s
21763 {
21764  volatile uint32_t ECC0BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS */
21765  volatile uint32_t ECC1BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS */
21766  volatile uint32_t ECC2BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS */
21767  volatile uint32_t ECC3BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS */
21768 };
21769 
21770 /* The typedef declaration for register ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS. */
21771 typedef struct ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_s ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_t;
21772 #endif /* __ASSEMBLY__ */
21773 
21774 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS register. */
21775 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_RESET 0x00000000
21776 /* The byte offset of the ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS register from the beginning of the component. */
21777 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_OFST 0x14c
21778 
21779 /*
21780  * Register : ECC_DIAGON
21781  *
21782  * Enable diagnostics access
21783  *
21784  * Register Layout
21785  *
21786  * Bits | Access | Reset | Description
21787  * :--------|:-------|:------|:--------------------------------------
21788  * [0] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON
21789  * [1] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON
21790  * [15:2] | ??? | 0x0 | *UNDEFINED*
21791  * [16] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON
21792  * [31:17] | ??? | 0x0 | *UNDEFINED*
21793  *
21794  */
21795 /*
21796  * Field : WRDIAGON
21797  *
21798  * Write diagnostics mux enabled.
21799  *
21800  * This overrides the encoder output with the register data ecc.
21801  *
21802  * 1'b0: Write diagnostics path via the ecc_reg2wdatabus is disabled.
21803  *
21804  * 1'b1: Write diagnostics path via the ecc_reg2wdatabus is enabled.
21805  *
21806  * Both Rddiagon and Wrdiagon bits can be enabled.
21807  *
21808  * Field Enumeration Values:
21809  *
21810  * Enum | Value | Description
21811  * :-----------------------------------------------|:------|:------------
21812  * ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON_E_DISABLE | 0x0 |
21813  * ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON_E_ENABLE | 0x1 |
21814  *
21815  * Field Access Macros:
21816  *
21817  */
21818 /*
21819  * Enumerated value for register field ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON
21820  *
21821  */
21822 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON_E_DISABLE 0x0
21823 /*
21824  * Enumerated value for register field ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON
21825  *
21826  */
21827 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON_E_ENABLE 0x1
21828 
21829 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON register field. */
21830 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON_LSB 0
21831 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON register field. */
21832 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON_MSB 0
21833 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON register field. */
21834 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON_WIDTH 1
21835 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON register field value. */
21836 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON_SET_MSK 0x00000001
21837 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON register field value. */
21838 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON_CLR_MSK 0xfffffffe
21839 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON register field. */
21840 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON_RESET 0x0
21841 /* Extracts the ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON field value from a register. */
21842 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON_GET(value) (((value) & 0x00000001) >> 0)
21843 /* Produces a ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON register field value suitable for setting the register. */
21844 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON_SET(value) (((value) << 0) & 0x00000001)
21845 
21846 /*
21847  * Field : RDDIAGON
21848  *
21849  * Read diagnostics mux enabled.
21850  *
21851  * This overrides the data entering the ECC decoder.
21852  *
21853  * 1'b0: Read diagnostics path via the ecc_rdata2regbus or ecc_reg2rdatabus is
21854  * disabled.
21855  *
21856  * 1'b1: Read diagnostics path via the ecc_rdata2regbus or ecc_reg2rdatabus is
21857  * enabled.
21858  *
21859  * Both Rddiagon and Wrdiagon bits can be enabled.
21860  *
21861  * Field Enumeration Values:
21862  *
21863  * Enum | Value | Description
21864  * :-----------------------------------------------|:------|:------------
21865  * ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON_E_DISABLE | 0x0 |
21866  * ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON_E_ENABLE | 0x1 |
21867  *
21868  * Field Access Macros:
21869  *
21870  */
21871 /*
21872  * Enumerated value for register field ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON
21873  *
21874  */
21875 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON_E_DISABLE 0x0
21876 /*
21877  * Enumerated value for register field ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON
21878  *
21879  */
21880 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON_E_ENABLE 0x1
21881 
21882 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON register field. */
21883 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON_LSB 1
21884 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON register field. */
21885 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON_MSB 1
21886 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON register field. */
21887 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON_WIDTH 1
21888 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON register field value. */
21889 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON_SET_MSK 0x00000002
21890 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON register field value. */
21891 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON_CLR_MSK 0xfffffffd
21892 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON register field. */
21893 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON_RESET 0x0
21894 /* Extracts the ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON field value from a register. */
21895 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON_GET(value) (((value) & 0x00000002) >> 1)
21896 /* Produces a ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON register field value suitable for setting the register. */
21897 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON_SET(value) (((value) << 1) & 0x00000002)
21898 
21899 /*
21900  * Field : ECCDIAGON
21901  *
21902  * ECC diagnostics mode.
21903  *
21904  * 1'b0: ECC diagnostics logic is disabled. ECC encoder bypass is disabled.
21905  *
21906  * 1'b1: ECC diagnostics logic is enabled. Direction of ECC data from the register
21907  * to data bus or data bus to ecc register is determined by ECC_rddiagon or
21908  * ECC_wrdiagon.
21909  *
21910  * Field Enumeration Values:
21911  *
21912  * Enum | Value | Description
21913  * :------------------------------------------------|:------|:------------
21914  * ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON_E_DISABLE | 0x0 |
21915  * ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON_E_ENABLE | 0x1 |
21916  *
21917  * Field Access Macros:
21918  *
21919  */
21920 /*
21921  * Enumerated value for register field ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON
21922  *
21923  */
21924 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON_E_DISABLE 0x0
21925 /*
21926  * Enumerated value for register field ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON
21927  *
21928  */
21929 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON_E_ENABLE 0x1
21930 
21931 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON register field. */
21932 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON_LSB 16
21933 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON register field. */
21934 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON_MSB 16
21935 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON register field. */
21936 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON_WIDTH 1
21937 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON register field value. */
21938 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON_SET_MSK 0x00010000
21939 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON register field value. */
21940 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON_CLR_MSK 0xfffeffff
21941 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON register field. */
21942 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON_RESET 0x0
21943 /* Extracts the ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON field value from a register. */
21944 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON_GET(value) (((value) & 0x00010000) >> 16)
21945 /* Produces a ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON register field value suitable for setting the register. */
21946 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON_SET(value) (((value) << 16) & 0x00010000)
21947 
21948 #ifndef __ASSEMBLY__
21949 /*
21950  * WARNING: The C register and register group struct declarations are provided for
21951  * convenience and illustrative purposes. They should, however, be used with
21952  * caution as the C language standard provides no guarantees about the alignment or
21953  * atomicity of device memory accesses. The recommended practice for coding device
21954  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21955  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21956  * alt_write_dword() functions for 64 bit registers.
21957  *
21958  * The struct declaration for register ALT_MPFE_HMC_ADP_ECC_DIAGON.
21959  */
21960 struct ALT_MPFE_HMC_ADP_ECC_DIAGON_s
21961 {
21962  volatile uint32_t WRDIAGON : 1; /* ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON */
21963  volatile uint32_t RDDIAGON : 1; /* ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON */
21964  uint32_t : 14; /* *UNDEFINED* */
21965  volatile uint32_t ECCDIAGON : 1; /* ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON */
21966  uint32_t : 15; /* *UNDEFINED* */
21967 };
21968 
21969 /* The typedef declaration for register ALT_MPFE_HMC_ADP_ECC_DIAGON. */
21970 typedef struct ALT_MPFE_HMC_ADP_ECC_DIAGON_s ALT_MPFE_HMC_ADP_ECC_DIAGON_t;
21971 #endif /* __ASSEMBLY__ */
21972 
21973 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_DIAGON register. */
21974 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_RESET 0x00000000
21975 /* The byte offset of the ALT_MPFE_HMC_ADP_ECC_DIAGON register from the beginning of the component. */
21976 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_OFST 0x150
21977 
21978 /*
21979  * Register : ECC_DECSTAT
21980  *
21981  * Diagnostic decoder status
21982  *
21983  * Register Layout
21984  *
21985  * Bits | Access | Reset | Description
21986  * :--------|:-------|:------|:-----------------------------------------
21987  * [0] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG
21988  * [1] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG
21989  * [2] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG
21990  * [3] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG
21991  * [4] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG
21992  * [5] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG
21993  * [6] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG
21994  * [7] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG
21995  * [8] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG
21996  * [9] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG
21997  * [10] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG
21998  * [11] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG
21999  * [31:12] | ??? | 0x0 | *UNDEFINED*
22000  *
22001  */
22002 /*
22003  * Field : DEC0SERRFLG
22004  *
22005  * indicates decoder for data [63:0] has detected SBE.
22006  *
22007  * 1'b0: No error has been captured with this flag.
22008  *
22009  * 1'b1: Decoder 0 detected a single bit error. This flag will be set by the
22010  * hardware and it will be cleared by the writing 1. This flag will be set till SW
22011  * clears. Additional errors will not change the state of this bit. Error flag is
22012  * set on the first beat of erred data.
22013  *
22014  * This won't be reset by the ecc_en bit.
22015  *
22016  * Field Access Macros:
22017  *
22018  */
22019 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG register field. */
22020 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG_LSB 0
22021 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG register field. */
22022 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG_MSB 0
22023 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG register field. */
22024 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG_WIDTH 1
22025 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG register field value. */
22026 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG_SET_MSK 0x00000001
22027 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG register field value. */
22028 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG_CLR_MSK 0xfffffffe
22029 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG register field. */
22030 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG_RESET 0x0
22031 /* Extracts the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG field value from a register. */
22032 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG_GET(value) (((value) & 0x00000001) >> 0)
22033 /* Produces a ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG register field value suitable for setting the register. */
22034 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG_SET(value) (((value) << 0) & 0x00000001)
22035 
22036 /*
22037  * Field : DEC1SERRFLG
22038  *
22039  * indicates decoder for data [127:64] has detected SBE.
22040  *
22041  * 1'b0: No error has been captured with this flag.
22042  *
22043  * 1'b1: Decoder 0 detected a single bit error. This flag will be set by the
22044  * hardware and it will be cleared by the writing 1. This flag will be set till SW
22045  * clears. Additional errors will not change the state of this bit. Error flag is
22046  * set on the first beat of erred data.
22047  *
22048  * This won't be reset by the ecc_en bit.
22049  *
22050  * Field Access Macros:
22051  *
22052  */
22053 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG register field. */
22054 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG_LSB 1
22055 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG register field. */
22056 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG_MSB 1
22057 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG register field. */
22058 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG_WIDTH 1
22059 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG register field value. */
22060 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG_SET_MSK 0x00000002
22061 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG register field value. */
22062 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG_CLR_MSK 0xfffffffd
22063 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG register field. */
22064 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG_RESET 0x0
22065 /* Extracts the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG field value from a register. */
22066 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG_GET(value) (((value) & 0x00000002) >> 1)
22067 /* Produces a ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG register field value suitable for setting the register. */
22068 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG_SET(value) (((value) << 1) & 0x00000002)
22069 
22070 /*
22071  * Field : DEC2SERRFLG
22072  *
22073  * indicates decoder for data [191:128] has detected SBE.
22074  *
22075  * 1'b0: No error has been captured with this flag.
22076  *
22077  * 1'b1: Decoder 0 detected a single bit error. This flag will be set by the
22078  * hardware and it will be cleared by the writing 1. This flag will be set till SW
22079  * clears. Additional errors will not change the state of this bit.Error flag is
22080  * set on the first beat of erred data.
22081  *
22082  * This won't be reset by the ecc_en bit.
22083  *
22084  * Field Access Macros:
22085  *
22086  */
22087 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG register field. */
22088 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG_LSB 2
22089 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG register field. */
22090 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG_MSB 2
22091 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG register field. */
22092 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG_WIDTH 1
22093 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG register field value. */
22094 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG_SET_MSK 0x00000004
22095 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG register field value. */
22096 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG_CLR_MSK 0xfffffffb
22097 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG register field. */
22098 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG_RESET 0x0
22099 /* Extracts the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG field value from a register. */
22100 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG_GET(value) (((value) & 0x00000004) >> 2)
22101 /* Produces a ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG register field value suitable for setting the register. */
22102 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG_SET(value) (((value) << 2) & 0x00000004)
22103 
22104 /*
22105  * Field : DEC3SERRFLG
22106  *
22107  * indicates decoder for data [255:192] has detected SBE.
22108  *
22109  * 1'b0: No error has been captured with this flag.
22110  *
22111  * 1'b1: Decoder 0 detected a single bit error. This flag will be set by the
22112  * hardware and it will be cleared by the writing 1. This flag will be set till SW
22113  * clears. Additional errors will not change the state of this bit.Error flag is
22114  * set on the first beat of erred data.
22115  *
22116  * This won't be reset by the ecc_en bit.
22117  *
22118  * Field Access Macros:
22119  *
22120  */
22121 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG register field. */
22122 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG_LSB 3
22123 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG register field. */
22124 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG_MSB 3
22125 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG register field. */
22126 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG_WIDTH 1
22127 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG register field value. */
22128 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG_SET_MSK 0x00000008
22129 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG register field value. */
22130 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG_CLR_MSK 0xfffffff7
22131 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG register field. */
22132 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG_RESET 0x0
22133 /* Extracts the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG field value from a register. */
22134 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG_GET(value) (((value) & 0x00000008) >> 3)
22135 /* Produces a ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG register field value suitable for setting the register. */
22136 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG_SET(value) (((value) << 3) & 0x00000008)
22137 
22138 /*
22139  * Field : DEC0ADDRFLG
22140  *
22141  * indicates decoder for data [63:0] has detected address error.
22142  *
22143  * 1'b0: No error has been captured with this flag.
22144  *
22145  * 1'b1: Decoder 0 detected an address mismatch error. This flag will be set by the
22146  * hardware and it will be cleared by the writing 1. This flag will be set till SW
22147  * clears.Additional errors will not change the state of this bit.Error flag is set
22148  * on the first beat of erred data.
22149  *
22150  * This won't be reset by the ecc_en bit.
22151  *
22152  * Field Access Macros:
22153  *
22154  */
22155 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG register field. */
22156 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG_LSB 4
22157 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG register field. */
22158 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG_MSB 4
22159 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG register field. */
22160 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG_WIDTH 1
22161 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG register field value. */
22162 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG_SET_MSK 0x00000010
22163 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG register field value. */
22164 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG_CLR_MSK 0xffffffef
22165 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG register field. */
22166 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG_RESET 0x0
22167 /* Extracts the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG field value from a register. */
22168 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG_GET(value) (((value) & 0x00000010) >> 4)
22169 /* Produces a ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG register field value suitable for setting the register. */
22170 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG_SET(value) (((value) << 4) & 0x00000010)
22171 
22172 /*
22173  * Field : DEC1ADDRFLG
22174  *
22175  * indicates decoder for data [127:64] has detected address error.
22176  *
22177  * 1'b0: No error has been captured with this flag.
22178  *
22179  * 1'b1: Decoder 0 detected an address mismatch error. This flag will be set by the
22180  * hardware and it will be cleared by the writing 1. This flag will be set till SW
22181  * clears.Additional errors will not change the state of this bit.Error flag is set
22182  * on the first beat of erred data.
22183  *
22184  * This won't be reset by the ecc_en bit.
22185  *
22186  * Field Access Macros:
22187  *
22188  */
22189 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG register field. */
22190 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG_LSB 5
22191 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG register field. */
22192 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG_MSB 5
22193 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG register field. */
22194 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG_WIDTH 1
22195 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG register field value. */
22196 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG_SET_MSK 0x00000020
22197 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG register field value. */
22198 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG_CLR_MSK 0xffffffdf
22199 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG register field. */
22200 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG_RESET 0x0
22201 /* Extracts the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG field value from a register. */
22202 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG_GET(value) (((value) & 0x00000020) >> 5)
22203 /* Produces a ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG register field value suitable for setting the register. */
22204 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG_SET(value) (((value) << 5) & 0x00000020)
22205 
22206 /*
22207  * Field : DEC2ADDRFLG
22208  *
22209  * indicates decoder for data [191:128] has detected address error.
22210  *
22211  * 1'b0: No error has been captured with this flag.
22212  *
22213  * 1'b1: Decoder 0 detected an address mismatch error. This flag will be set by the
22214  * hardware and it will be cleared by the writing 1. This flag will be set till SW
22215  * clears.Additional errors will not change the state of this bit.Error flag is set
22216  * on the first beat of erred data.
22217  *
22218  * This won't be reset by the ecc_en bit.
22219  *
22220  * Field Access Macros:
22221  *
22222  */
22223 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG register field. */
22224 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG_LSB 6
22225 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG register field. */
22226 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG_MSB 6
22227 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG register field. */
22228 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG_WIDTH 1
22229 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG register field value. */
22230 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG_SET_MSK 0x00000040
22231 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG register field value. */
22232 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG_CLR_MSK 0xffffffbf
22233 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG register field. */
22234 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG_RESET 0x0
22235 /* Extracts the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG field value from a register. */
22236 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG_GET(value) (((value) & 0x00000040) >> 6)
22237 /* Produces a ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG register field value suitable for setting the register. */
22238 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG_SET(value) (((value) << 6) & 0x00000040)
22239 
22240 /*
22241  * Field : DEC3ADDRFLG
22242  *
22243  * indicates decoder for data [255:192] has detected address error.
22244  *
22245  * 1'b0: No error has been captured with this flag.
22246  *
22247  * 1'b1: Decoder 0 detected an address mismatch error. This flag will be set by the
22248  * hardware and it will be cleared by the writing 1. This flag will be set till SW
22249  * clears.Additional errors will not change the state of this bit.Error flag is set
22250  * on the first beat of erred data.
22251  *
22252  * This won't be reset by the ecc_en bit.
22253  *
22254  * Field Access Macros:
22255  *
22256  */
22257 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG register field. */
22258 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG_LSB 7
22259 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG register field. */
22260 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG_MSB 7
22261 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG register field. */
22262 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG_WIDTH 1
22263 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG register field value. */
22264 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG_SET_MSK 0x00000080
22265 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG register field value. */
22266 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG_CLR_MSK 0xffffff7f
22267 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG register field. */
22268 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG_RESET 0x0
22269 /* Extracts the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG field value from a register. */
22270 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG_GET(value) (((value) & 0x00000080) >> 7)
22271 /* Produces a ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG register field value suitable for setting the register. */
22272 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG_SET(value) (((value) << 7) & 0x00000080)
22273 
22274 /*
22275  * Field : DEC0DERRFLG
22276  *
22277  * indicates decoder for data [63:0] has detected DBE.
22278  *
22279  * 1'b0: No error has been captured with this flag.
22280  *
22281  * 1'b1: Decoder 0 detected a double-bit error. This flag will be set by the
22282  * hardware and it will be cleared by the writing 1. This flag will be set till SW
22283  * clears. Additional errors will not change the state of this bit. Error flag is
22284  * set on the first beat of erred data.
22285  *
22286  * This won't be reset by the ecc_en bit.
22287  *
22288  * Field Access Macros:
22289  *
22290  */
22291 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG register field. */
22292 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG_LSB 8
22293 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG register field. */
22294 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG_MSB 8
22295 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG register field. */
22296 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG_WIDTH 1
22297 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG register field value. */
22298 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG_SET_MSK 0x00000100
22299 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG register field value. */
22300 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG_CLR_MSK 0xfffffeff
22301 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG register field. */
22302 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG_RESET 0x0
22303 /* Extracts the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG field value from a register. */
22304 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG_GET(value) (((value) & 0x00000100) >> 8)
22305 /* Produces a ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG register field value suitable for setting the register. */
22306 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG_SET(value) (((value) << 8) & 0x00000100)
22307 
22308 /*
22309  * Field : DEC1DERRFLG
22310  *
22311  * indicates decoder for data [127:64] has detected DBE.
22312  *
22313  * 1'b0: No error has been captured with this flag.
22314  *
22315  * 1'b1: Decoder 0 detected a double-bit error. This flag will be set by the
22316  * hardware and it will be cleared by the writing 1. This flag will be set till SW
22317  * clears. Additional errors will not change the state of this bit.Error flag is
22318  * set on the first beat of erred data.
22319  *
22320  * This won't be reset by the ecc_en bit.
22321  *
22322  * Field Access Macros:
22323  *
22324  */
22325 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG register field. */
22326 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG_LSB 9
22327 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG register field. */
22328 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG_MSB 9
22329 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG register field. */
22330 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG_WIDTH 1
22331 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG register field value. */
22332 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG_SET_MSK 0x00000200
22333 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG register field value. */
22334 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG_CLR_MSK 0xfffffdff
22335 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG register field. */
22336 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG_RESET 0x0
22337 /* Extracts the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG field value from a register. */
22338 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG_GET(value) (((value) & 0x00000200) >> 9)
22339 /* Produces a ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG register field value suitable for setting the register. */
22340 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG_SET(value) (((value) << 9) & 0x00000200)
22341 
22342 /*
22343  * Field : DEC2DERRFLG
22344  *
22345  * indicates decoder for data [191:128] has detected DBE.
22346  *
22347  * 1'b0: No error has been captured with this flag.
22348  *
22349  * 1'b1: Decoder 0 detected a double-bit error. This flag will be set by the
22350  * hardware and it will be cleared by the writing 1. This flag will be set till SW
22351  * clears. Additional errors will not change the state of this bit.Error flag is
22352  * set on the first beat of erred data.
22353  *
22354  * This won't be reset by the ecc_en bit.
22355  *
22356  * Field Access Macros:
22357  *
22358  */
22359 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG register field. */
22360 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG_LSB 10
22361 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG register field. */
22362 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG_MSB 10
22363 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG register field. */
22364 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG_WIDTH 1
22365 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG register field value. */
22366 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG_SET_MSK 0x00000400
22367 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG register field value. */
22368 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG_CLR_MSK 0xfffffbff
22369 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG register field. */
22370 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG_RESET 0x0
22371 /* Extracts the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG field value from a register. */
22372 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG_GET(value) (((value) & 0x00000400) >> 10)
22373 /* Produces a ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG register field value suitable for setting the register. */
22374 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG_SET(value) (((value) << 10) & 0x00000400)
22375 
22376 /*
22377  * Field : DEC3DERRFLG
22378  *
22379  * indicates decoder for data [255:192] has detected DBE.
22380  *
22381  * 1'b0: No error has been captured with this flag.
22382  *
22383  * 1'b1: Decoder 0 detected a double-bit error. This flag will be set by the
22384  * hardware and it will be cleared by the writing 1. This flag will be set till SW
22385  * clears. Additional errors will not change the state of this bit. Error flag is
22386  * set on the first beat of erred data.
22387  *
22388  * This won't be reset by the ecc_en bit.
22389  *
22390  * Field Access Macros:
22391  *
22392  */
22393 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG register field. */
22394 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG_LSB 11
22395 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG register field. */
22396 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG_MSB 11
22397 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG register field. */
22398 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG_WIDTH 1
22399 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG register field value. */
22400 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG_SET_MSK 0x00000800
22401 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG register field value. */
22402 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG_CLR_MSK 0xfffff7ff
22403 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG register field. */
22404 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG_RESET 0x0
22405 /* Extracts the ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG field value from a register. */
22406 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG_GET(value) (((value) & 0x00000800) >> 11)
22407 /* Produces a ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG register field value suitable for setting the register. */
22408 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG_SET(value) (((value) << 11) & 0x00000800)
22409 
22410 #ifndef __ASSEMBLY__
22411 /*
22412  * WARNING: The C register and register group struct declarations are provided for
22413  * convenience and illustrative purposes. They should, however, be used with
22414  * caution as the C language standard provides no guarantees about the alignment or
22415  * atomicity of device memory accesses. The recommended practice for coding device
22416  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22417  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22418  * alt_write_dword() functions for 64 bit registers.
22419  *
22420  * The struct declaration for register ALT_MPFE_HMC_ADP_ECC_DECSTAT.
22421  */
22422 struct ALT_MPFE_HMC_ADP_ECC_DECSTAT_s
22423 {
22424  volatile uint32_t DEC0SERRFLG : 1; /* ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG */
22425  volatile uint32_t DEC1SERRFLG : 1; /* ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG */
22426  volatile uint32_t DEC2SERRFLG : 1; /* ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG */
22427  volatile uint32_t DEC3SERRFLG : 1; /* ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG */
22428  volatile uint32_t DEC0ADDRFLG : 1; /* ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG */
22429  volatile uint32_t DEC1ADDRFLG : 1; /* ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG */
22430  volatile uint32_t DEC2ADDRFLG : 1; /* ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG */
22431  volatile uint32_t DEC3ADDRFLG : 1; /* ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG */
22432  volatile uint32_t DEC0DERRFLG : 1; /* ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG */
22433  volatile uint32_t DEC1DERRFLG : 1; /* ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG */
22434  volatile uint32_t DEC2DERRFLG : 1; /* ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG */
22435  volatile uint32_t DEC3DERRFLG : 1; /* ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG */
22436  uint32_t : 20; /* *UNDEFINED* */
22437 };
22438 
22439 /* The typedef declaration for register ALT_MPFE_HMC_ADP_ECC_DECSTAT. */
22440 typedef struct ALT_MPFE_HMC_ADP_ECC_DECSTAT_s ALT_MPFE_HMC_ADP_ECC_DECSTAT_t;
22441 #endif /* __ASSEMBLY__ */
22442 
22443 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_DECSTAT register. */
22444 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_RESET 0x00000000
22445 /* The byte offset of the ALT_MPFE_HMC_ADP_ECC_DECSTAT register from the beginning of the component. */
22446 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_OFST 0x154
22447 
22448 /*
22449  * Register : ECC_ERRGENADDR_0
22450  *
22451  * Error address register
22452  *
22453  * Register Layout
22454  *
22455  * Bits | Access | Reset | Description
22456  * :-------|:-------|:------|:---------------------------------------
22457  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR
22458  *
22459  */
22460 /*
22461  * Field : ADDR
22462  *
22463  * For decoder 0.
22464  *
22465  * Address generated with SER or address mismatch logic. Address will be driven by
22466  * the ECC decoder on every read latched by the RAM independent of ECCDiagon is on.
22467  *
22468  * Field Access Macros:
22469  *
22470  */
22471 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR register field. */
22472 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR_LSB 0
22473 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR register field. */
22474 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR_MSB 31
22475 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR register field. */
22476 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR_WIDTH 32
22477 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR register field value. */
22478 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR_SET_MSK 0xffffffff
22479 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR register field value. */
22480 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR_CLR_MSK 0x00000000
22481 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR register field. */
22482 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR_RESET 0x0
22483 /* Extracts the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR field value from a register. */
22484 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
22485 /* Produces a ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR register field value suitable for setting the register. */
22486 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR_SET(value) (((value) << 0) & 0xffffffff)
22487 
22488 #ifndef __ASSEMBLY__
22489 /*
22490  * WARNING: The C register and register group struct declarations are provided for
22491  * convenience and illustrative purposes. They should, however, be used with
22492  * caution as the C language standard provides no guarantees about the alignment or
22493  * atomicity of device memory accesses. The recommended practice for coding device
22494  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22495  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22496  * alt_write_dword() functions for 64 bit registers.
22497  *
22498  * The struct declaration for register ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0.
22499  */
22500 struct ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_s
22501 {
22502  volatile uint32_t ADDR : 32; /* ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR */
22503 };
22504 
22505 /* The typedef declaration for register ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0. */
22506 typedef struct ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_s ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_t;
22507 #endif /* __ASSEMBLY__ */
22508 
22509 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0 register. */
22510 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_RESET 0x00000000
22511 /* The byte offset of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0 register from the beginning of the component. */
22512 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_OFST 0x160
22513 
22514 /*
22515  * Register : ECC_ERRGENADDR_1
22516  *
22517  * Error address register
22518  *
22519  * Register Layout
22520  *
22521  * Bits | Access | Reset | Description
22522  * :-------|:-------|:------|:---------------------------------------
22523  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR
22524  *
22525  */
22526 /*
22527  * Field : ADDR
22528  *
22529  * For decoder 1.
22530  *
22531  * Address generated with SER or address mismatch logic. Address will be driven by
22532  * the ECC decoder on every read latched by the RAM independent of ECCDiagon is on.
22533  *
22534  * Field Access Macros:
22535  *
22536  */
22537 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR register field. */
22538 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR_LSB 0
22539 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR register field. */
22540 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR_MSB 31
22541 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR register field. */
22542 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR_WIDTH 32
22543 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR register field value. */
22544 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR_SET_MSK 0xffffffff
22545 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR register field value. */
22546 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR_CLR_MSK 0x00000000
22547 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR register field. */
22548 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR_RESET 0x0
22549 /* Extracts the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR field value from a register. */
22550 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
22551 /* Produces a ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR register field value suitable for setting the register. */
22552 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR_SET(value) (((value) << 0) & 0xffffffff)
22553 
22554 #ifndef __ASSEMBLY__
22555 /*
22556  * WARNING: The C register and register group struct declarations are provided for
22557  * convenience and illustrative purposes. They should, however, be used with
22558  * caution as the C language standard provides no guarantees about the alignment or
22559  * atomicity of device memory accesses. The recommended practice for coding device
22560  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22561  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22562  * alt_write_dword() functions for 64 bit registers.
22563  *
22564  * The struct declaration for register ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1.
22565  */
22566 struct ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_s
22567 {
22568  volatile uint32_t ADDR : 32; /* ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR */
22569 };
22570 
22571 /* The typedef declaration for register ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1. */
22572 typedef struct ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_s ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_t;
22573 #endif /* __ASSEMBLY__ */
22574 
22575 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1 register. */
22576 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_RESET 0x00000000
22577 /* The byte offset of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1 register from the beginning of the component. */
22578 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_OFST 0x164
22579 
22580 /*
22581  * Register : ECC_ERRGENADDR_2
22582  *
22583  * Error address register
22584  *
22585  * Register Layout
22586  *
22587  * Bits | Access | Reset | Description
22588  * :-------|:-------|:------|:---------------------------------------
22589  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR
22590  *
22591  */
22592 /*
22593  * Field : ADDR
22594  *
22595  * For decoder 2.
22596  *
22597  * Address generated with SER or address mismatch logic. Address will be driven by
22598  * the ECC decoder on every read latched by the RAM independent of ECCDiagon is on.
22599  *
22600  * Field Access Macros:
22601  *
22602  */
22603 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR register field. */
22604 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR_LSB 0
22605 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR register field. */
22606 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR_MSB 31
22607 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR register field. */
22608 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR_WIDTH 32
22609 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR register field value. */
22610 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR_SET_MSK 0xffffffff
22611 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR register field value. */
22612 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR_CLR_MSK 0x00000000
22613 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR register field. */
22614 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR_RESET 0x0
22615 /* Extracts the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR field value from a register. */
22616 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
22617 /* Produces a ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR register field value suitable for setting the register. */
22618 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR_SET(value) (((value) << 0) & 0xffffffff)
22619 
22620 #ifndef __ASSEMBLY__
22621 /*
22622  * WARNING: The C register and register group struct declarations are provided for
22623  * convenience and illustrative purposes. They should, however, be used with
22624  * caution as the C language standard provides no guarantees about the alignment or
22625  * atomicity of device memory accesses. The recommended practice for coding device
22626  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22627  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22628  * alt_write_dword() functions for 64 bit registers.
22629  *
22630  * The struct declaration for register ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2.
22631  */
22632 struct ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_s
22633 {
22634  volatile uint32_t ADDR : 32; /* ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR */
22635 };
22636 
22637 /* The typedef declaration for register ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2. */
22638 typedef struct ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_s ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_t;
22639 #endif /* __ASSEMBLY__ */
22640 
22641 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2 register. */
22642 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_RESET 0x00000000
22643 /* The byte offset of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2 register from the beginning of the component. */
22644 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_OFST 0x168
22645 
22646 /*
22647  * Register : ECC_ERRGENADDR_3
22648  *
22649  * Error address register
22650  *
22651  * Register Layout
22652  *
22653  * Bits | Access | Reset | Description
22654  * :-------|:-------|:------|:---------------------------------------
22655  * [31:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR
22656  *
22657  */
22658 /*
22659  * Field : ADDR
22660  *
22661  * For decoder 3.
22662  *
22663  * Address generated with SER or address mismatch logic. Address will be driven by
22664  * the ECC decoder on every read latched by the RAM independent of ECCDiagon is on.
22665  *
22666  * Field Access Macros:
22667  *
22668  */
22669 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR register field. */
22670 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR_LSB 0
22671 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR register field. */
22672 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR_MSB 31
22673 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR register field. */
22674 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR_WIDTH 32
22675 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR register field value. */
22676 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR_SET_MSK 0xffffffff
22677 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR register field value. */
22678 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR_CLR_MSK 0x00000000
22679 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR register field. */
22680 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR_RESET 0x0
22681 /* Extracts the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR field value from a register. */
22682 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
22683 /* Produces a ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR register field value suitable for setting the register. */
22684 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR_SET(value) (((value) << 0) & 0xffffffff)
22685 
22686 #ifndef __ASSEMBLY__
22687 /*
22688  * WARNING: The C register and register group struct declarations are provided for
22689  * convenience and illustrative purposes. They should, however, be used with
22690  * caution as the C language standard provides no guarantees about the alignment or
22691  * atomicity of device memory accesses. The recommended practice for coding device
22692  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22693  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22694  * alt_write_dword() functions for 64 bit registers.
22695  *
22696  * The struct declaration for register ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3.
22697  */
22698 struct ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_s
22699 {
22700  volatile uint32_t ADDR : 32; /* ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR */
22701 };
22702 
22703 /* The typedef declaration for register ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3. */
22704 typedef struct ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_s ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_t;
22705 #endif /* __ASSEMBLY__ */
22706 
22707 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3 register. */
22708 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_RESET 0x00000000
22709 /* The byte offset of the ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3 register from the beginning of the component. */
22710 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_OFST 0x16c
22711 
22712 /*
22713  * Register : ECC_REG2RDDATABUS_BEAT0
22714  *
22715  * ECC Reg2Rddatabus_beat0
22716  *
22717  * Register Layout
22718  *
22719  * Bits | Access | Reset | Description
22720  * :--------|:-------|:------|:-------------------------------------------------
22721  * [7:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS
22722  * [15:8] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS
22723  * [23:16] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS
22724  * [31:24] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS
22725  *
22726  */
22727 /*
22728  * Field : ECC0BUS
22729  *
22730  * Data ECC from the register will be written to the RAM
22731  *
22732  * Field Access Macros:
22733  *
22734  */
22735 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS register field. */
22736 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_LSB 0
22737 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS register field. */
22738 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_MSB 7
22739 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS register field. */
22740 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_WIDTH 8
22741 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS register field value. */
22742 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_SET_MSK 0x000000ff
22743 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS register field value. */
22744 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_CLR_MSK 0xffffff00
22745 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS register field. */
22746 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_RESET 0x0
22747 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS field value from a register. */
22748 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
22749 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS register field value suitable for setting the register. */
22750 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
22751 
22752 /*
22753  * Field : ECC1BUS
22754  *
22755  * Data ECC from the register will be written to the RAM
22756  *
22757  * Field Access Macros:
22758  *
22759  */
22760 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS register field. */
22761 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_LSB 8
22762 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS register field. */
22763 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_MSB 15
22764 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS register field. */
22765 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_WIDTH 8
22766 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS register field value. */
22767 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_SET_MSK 0x0000ff00
22768 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS register field value. */
22769 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_CLR_MSK 0xffff00ff
22770 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS register field. */
22771 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_RESET 0x0
22772 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS field value from a register. */
22773 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
22774 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS register field value suitable for setting the register. */
22775 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
22776 
22777 /*
22778  * Field : ECC2BUS
22779  *
22780  * Data ECC from the register will be written to the RAM
22781  *
22782  * Field Access Macros:
22783  *
22784  */
22785 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS register field. */
22786 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_LSB 16
22787 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS register field. */
22788 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_MSB 23
22789 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS register field. */
22790 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_WIDTH 8
22791 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS register field value. */
22792 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_SET_MSK 0x00ff0000
22793 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS register field value. */
22794 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_CLR_MSK 0xff00ffff
22795 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS register field. */
22796 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_RESET 0x0
22797 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS field value from a register. */
22798 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
22799 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS register field value suitable for setting the register. */
22800 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
22801 
22802 /*
22803  * Field : ECC3BUS
22804  *
22805  * Data ECC from the register will be written to the RAM
22806  *
22807  * Field Access Macros:
22808  *
22809  */
22810 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS register field. */
22811 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_LSB 24
22812 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS register field. */
22813 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_MSB 31
22814 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS register field. */
22815 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_WIDTH 8
22816 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS register field value. */
22817 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_SET_MSK 0xff000000
22818 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS register field value. */
22819 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_CLR_MSK 0x00ffffff
22820 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS register field. */
22821 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_RESET 0x0
22822 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS field value from a register. */
22823 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
22824 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS register field value suitable for setting the register. */
22825 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
22826 
22827 #ifndef __ASSEMBLY__
22828 /*
22829  * WARNING: The C register and register group struct declarations are provided for
22830  * convenience and illustrative purposes. They should, however, be used with
22831  * caution as the C language standard provides no guarantees about the alignment or
22832  * atomicity of device memory accesses. The recommended practice for coding device
22833  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22834  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22835  * alt_write_dword() functions for 64 bit registers.
22836  *
22837  * The struct declaration for register ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0.
22838  */
22839 struct ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_s
22840 {
22841  volatile uint32_t ECC0BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS */
22842  volatile uint32_t ECC1BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS */
22843  volatile uint32_t ECC2BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS */
22844  volatile uint32_t ECC3BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS */
22845 };
22846 
22847 /* The typedef declaration for register ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0. */
22848 typedef struct ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_s ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_t;
22849 #endif /* __ASSEMBLY__ */
22850 
22851 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0 register. */
22852 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_RESET 0x00000000
22853 /* The byte offset of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0 register from the beginning of the component. */
22854 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_OFST 0x170
22855 
22856 /*
22857  * Register : ECC_REG2RDDATABUS_BEAT1
22858  *
22859  * ECC Reg2Rddatabus_beat1
22860  *
22861  * Register Layout
22862  *
22863  * Bits | Access | Reset | Description
22864  * :--------|:-------|:------|:-------------------------------------------------
22865  * [7:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS
22866  * [15:8] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS
22867  * [23:16] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS
22868  * [31:24] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS
22869  *
22870  */
22871 /*
22872  * Field : ECC0BUS
22873  *
22874  * Data ECC from the register will be written to the RAM
22875  *
22876  * Field Access Macros:
22877  *
22878  */
22879 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS register field. */
22880 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_LSB 0
22881 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS register field. */
22882 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_MSB 7
22883 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS register field. */
22884 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_WIDTH 8
22885 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS register field value. */
22886 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_SET_MSK 0x000000ff
22887 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS register field value. */
22888 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_CLR_MSK 0xffffff00
22889 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS register field. */
22890 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_RESET 0x0
22891 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS field value from a register. */
22892 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
22893 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS register field value suitable for setting the register. */
22894 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
22895 
22896 /*
22897  * Field : ECC1BUS
22898  *
22899  * Data ECC from the register will be written to the RAM
22900  *
22901  * Field Access Macros:
22902  *
22903  */
22904 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS register field. */
22905 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_LSB 8
22906 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS register field. */
22907 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_MSB 15
22908 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS register field. */
22909 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_WIDTH 8
22910 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS register field value. */
22911 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_SET_MSK 0x0000ff00
22912 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS register field value. */
22913 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_CLR_MSK 0xffff00ff
22914 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS register field. */
22915 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_RESET 0x0
22916 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS field value from a register. */
22917 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
22918 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS register field value suitable for setting the register. */
22919 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
22920 
22921 /*
22922  * Field : ECC2BUS
22923  *
22924  * Data ECC from the register will be written to the RAM
22925  *
22926  * Field Access Macros:
22927  *
22928  */
22929 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS register field. */
22930 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_LSB 16
22931 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS register field. */
22932 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_MSB 23
22933 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS register field. */
22934 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_WIDTH 8
22935 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS register field value. */
22936 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_SET_MSK 0x00ff0000
22937 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS register field value. */
22938 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_CLR_MSK 0xff00ffff
22939 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS register field. */
22940 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_RESET 0x0
22941 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS field value from a register. */
22942 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
22943 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS register field value suitable for setting the register. */
22944 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
22945 
22946 /*
22947  * Field : ECC3BUS
22948  *
22949  * Data ECC from the register will be written to the RAM
22950  *
22951  * Field Access Macros:
22952  *
22953  */
22954 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS register field. */
22955 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_LSB 24
22956 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS register field. */
22957 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_MSB 31
22958 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS register field. */
22959 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_WIDTH 8
22960 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS register field value. */
22961 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_SET_MSK 0xff000000
22962 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS register field value. */
22963 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_CLR_MSK 0x00ffffff
22964 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS register field. */
22965 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_RESET 0x0
22966 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS field value from a register. */
22967 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
22968 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS register field value suitable for setting the register. */
22969 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
22970 
22971 #ifndef __ASSEMBLY__
22972 /*
22973  * WARNING: The C register and register group struct declarations are provided for
22974  * convenience and illustrative purposes. They should, however, be used with
22975  * caution as the C language standard provides no guarantees about the alignment or
22976  * atomicity of device memory accesses. The recommended practice for coding device
22977  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22978  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22979  * alt_write_dword() functions for 64 bit registers.
22980  *
22981  * The struct declaration for register ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1.
22982  */
22983 struct ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_s
22984 {
22985  volatile uint32_t ECC0BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS */
22986  volatile uint32_t ECC1BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS */
22987  volatile uint32_t ECC2BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS */
22988  volatile uint32_t ECC3BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS */
22989 };
22990 
22991 /* The typedef declaration for register ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1. */
22992 typedef struct ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_s ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_t;
22993 #endif /* __ASSEMBLY__ */
22994 
22995 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1 register. */
22996 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_RESET 0x00000000
22997 /* The byte offset of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1 register from the beginning of the component. */
22998 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_OFST 0x174
22999 
23000 /*
23001  * Register : ECC_REG2RDDATABUS_BEAT2
23002  *
23003  * ECC Reg2Rddatabus_beat2
23004  *
23005  * Register Layout
23006  *
23007  * Bits | Access | Reset | Description
23008  * :--------|:-------|:------|:-------------------------------------------------
23009  * [7:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS
23010  * [15:8] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS
23011  * [23:16] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS
23012  * [31:24] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS
23013  *
23014  */
23015 /*
23016  * Field : ECC0BUS
23017  *
23018  * Data ECC from the register will be written to the RAM
23019  *
23020  * Field Access Macros:
23021  *
23022  */
23023 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS register field. */
23024 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_LSB 0
23025 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS register field. */
23026 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_MSB 7
23027 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS register field. */
23028 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_WIDTH 8
23029 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS register field value. */
23030 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_SET_MSK 0x000000ff
23031 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS register field value. */
23032 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_CLR_MSK 0xffffff00
23033 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS register field. */
23034 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_RESET 0x0
23035 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS field value from a register. */
23036 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
23037 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS register field value suitable for setting the register. */
23038 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
23039 
23040 /*
23041  * Field : ECC1BUS
23042  *
23043  * Data ECC from the register will be written to the RAM
23044  *
23045  * Field Access Macros:
23046  *
23047  */
23048 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS register field. */
23049 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_LSB 8
23050 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS register field. */
23051 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_MSB 15
23052 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS register field. */
23053 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_WIDTH 8
23054 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS register field value. */
23055 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_SET_MSK 0x0000ff00
23056 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS register field value. */
23057 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_CLR_MSK 0xffff00ff
23058 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS register field. */
23059 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_RESET 0x0
23060 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS field value from a register. */
23061 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
23062 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS register field value suitable for setting the register. */
23063 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
23064 
23065 /*
23066  * Field : ECC2BUS
23067  *
23068  * Data ECC from the register will be written to the RAM
23069  *
23070  * Field Access Macros:
23071  *
23072  */
23073 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS register field. */
23074 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_LSB 16
23075 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS register field. */
23076 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_MSB 23
23077 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS register field. */
23078 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_WIDTH 8
23079 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS register field value. */
23080 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_SET_MSK 0x00ff0000
23081 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS register field value. */
23082 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_CLR_MSK 0xff00ffff
23083 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS register field. */
23084 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_RESET 0x0
23085 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS field value from a register. */
23086 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
23087 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS register field value suitable for setting the register. */
23088 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
23089 
23090 /*
23091  * Field : ECC3BUS
23092  *
23093  * Data ECC from the register will be written to the RAM
23094  *
23095  * Field Access Macros:
23096  *
23097  */
23098 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS register field. */
23099 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_LSB 24
23100 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS register field. */
23101 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_MSB 31
23102 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS register field. */
23103 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_WIDTH 8
23104 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS register field value. */
23105 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_SET_MSK 0xff000000
23106 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS register field value. */
23107 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_CLR_MSK 0x00ffffff
23108 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS register field. */
23109 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_RESET 0x0
23110 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS field value from a register. */
23111 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
23112 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS register field value suitable for setting the register. */
23113 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
23114 
23115 #ifndef __ASSEMBLY__
23116 /*
23117  * WARNING: The C register and register group struct declarations are provided for
23118  * convenience and illustrative purposes. They should, however, be used with
23119  * caution as the C language standard provides no guarantees about the alignment or
23120  * atomicity of device memory accesses. The recommended practice for coding device
23121  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23122  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23123  * alt_write_dword() functions for 64 bit registers.
23124  *
23125  * The struct declaration for register ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2.
23126  */
23127 struct ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_s
23128 {
23129  volatile uint32_t ECC0BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS */
23130  volatile uint32_t ECC1BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS */
23131  volatile uint32_t ECC2BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS */
23132  volatile uint32_t ECC3BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS */
23133 };
23134 
23135 /* The typedef declaration for register ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2. */
23136 typedef struct ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_s ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_t;
23137 #endif /* __ASSEMBLY__ */
23138 
23139 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2 register. */
23140 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_RESET 0x00000000
23141 /* The byte offset of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2 register from the beginning of the component. */
23142 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_OFST 0x178
23143 
23144 /*
23145  * Register : ECC_REG2RDDATABUS_BEAT3
23146  *
23147  * ECC Reg2Rddatabus_beat3
23148  *
23149  * Register Layout
23150  *
23151  * Bits | Access | Reset | Description
23152  * :--------|:-------|:------|:-------------------------------------------------
23153  * [7:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS
23154  * [15:8] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS
23155  * [23:16] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS
23156  * [31:24] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS
23157  *
23158  */
23159 /*
23160  * Field : ECC0BUS
23161  *
23162  * Data ECC from the register will be written to the RAM
23163  *
23164  * Field Access Macros:
23165  *
23166  */
23167 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS register field. */
23168 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_LSB 0
23169 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS register field. */
23170 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_MSB 7
23171 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS register field. */
23172 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_WIDTH 8
23173 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS register field value. */
23174 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_SET_MSK 0x000000ff
23175 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS register field value. */
23176 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_CLR_MSK 0xffffff00
23177 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS register field. */
23178 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_RESET 0x0
23179 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS field value from a register. */
23180 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
23181 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS register field value suitable for setting the register. */
23182 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
23183 
23184 /*
23185  * Field : ECC1BUS
23186  *
23187  * Data ECC from the register will be written to the RAM
23188  *
23189  * Field Access Macros:
23190  *
23191  */
23192 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS register field. */
23193 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_LSB 8
23194 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS register field. */
23195 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_MSB 15
23196 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS register field. */
23197 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_WIDTH 8
23198 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS register field value. */
23199 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_SET_MSK 0x0000ff00
23200 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS register field value. */
23201 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_CLR_MSK 0xffff00ff
23202 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS register field. */
23203 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_RESET 0x0
23204 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS field value from a register. */
23205 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
23206 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS register field value suitable for setting the register. */
23207 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
23208 
23209 /*
23210  * Field : ECC2BUS
23211  *
23212  * Data ECC from the register will be written to the RAM
23213  *
23214  * Field Access Macros:
23215  *
23216  */
23217 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS register field. */
23218 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_LSB 16
23219 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS register field. */
23220 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_MSB 23
23221 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS register field. */
23222 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_WIDTH 8
23223 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS register field value. */
23224 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_SET_MSK 0x00ff0000
23225 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS register field value. */
23226 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_CLR_MSK 0xff00ffff
23227 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS register field. */
23228 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_RESET 0x0
23229 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS field value from a register. */
23230 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
23231 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS register field value suitable for setting the register. */
23232 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
23233 
23234 /*
23235  * Field : ECC3BUS
23236  *
23237  * Data ECC from the register will be written to the RAM
23238  *
23239  * Field Access Macros:
23240  *
23241  */
23242 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS register field. */
23243 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_LSB 24
23244 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS register field. */
23245 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_MSB 31
23246 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS register field. */
23247 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_WIDTH 8
23248 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS register field value. */
23249 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_SET_MSK 0xff000000
23250 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS register field value. */
23251 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_CLR_MSK 0x00ffffff
23252 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS register field. */
23253 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_RESET 0x0
23254 /* Extracts the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS field value from a register. */
23255 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
23256 /* Produces a ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS register field value suitable for setting the register. */
23257 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
23258 
23259 #ifndef __ASSEMBLY__
23260 /*
23261  * WARNING: The C register and register group struct declarations are provided for
23262  * convenience and illustrative purposes. They should, however, be used with
23263  * caution as the C language standard provides no guarantees about the alignment or
23264  * atomicity of device memory accesses. The recommended practice for coding device
23265  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23266  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23267  * alt_write_dword() functions for 64 bit registers.
23268  *
23269  * The struct declaration for register ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3.
23270  */
23271 struct ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_s
23272 {
23273  volatile uint32_t ECC0BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS */
23274  volatile uint32_t ECC1BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS */
23275  volatile uint32_t ECC2BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS */
23276  volatile uint32_t ECC3BUS : 8; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS */
23277 };
23278 
23279 /* The typedef declaration for register ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3. */
23280 typedef struct ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_s ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_t;
23281 #endif /* __ASSEMBLY__ */
23282 
23283 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3 register. */
23284 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_RESET 0x00000000
23285 /* The byte offset of the ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3 register from the beginning of the component. */
23286 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_OFST 0x17c
23287 
23288 /*
23289  * Register : ECC_ERRGENHADDR_0
23290  *
23291  * Error address register
23292  *
23293  * Register Layout
23294  *
23295  * Bits | Access | Reset | Description
23296  * :-------|:-------|:------|:----------------------------------------
23297  * [4:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR
23298  * [31:5] | ??? | 0x0 | *UNDEFINED*
23299  *
23300  */
23301 /*
23302  * Field : ADDR
23303  *
23304  * For decoder 0.
23305  *
23306  * High address generated with SER or address mismatch logic. Address will be
23307  * driven by the ECC decoder on every read latched by the RAM independent of
23308  * ECCDiagon is on.
23309  *
23310  * Field Access Macros:
23311  *
23312  */
23313 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR register field. */
23314 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR_LSB 0
23315 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR register field. */
23316 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR_MSB 4
23317 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR register field. */
23318 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR_WIDTH 5
23319 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR register field value. */
23320 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR_SET_MSK 0x0000001f
23321 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR register field value. */
23322 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR_CLR_MSK 0xffffffe0
23323 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR register field. */
23324 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR_RESET 0x0
23325 /* Extracts the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR field value from a register. */
23326 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR_GET(value) (((value) & 0x0000001f) >> 0)
23327 /* Produces a ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR register field value suitable for setting the register. */
23328 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR_SET(value) (((value) << 0) & 0x0000001f)
23329 
23330 #ifndef __ASSEMBLY__
23331 /*
23332  * WARNING: The C register and register group struct declarations are provided for
23333  * convenience and illustrative purposes. They should, however, be used with
23334  * caution as the C language standard provides no guarantees about the alignment or
23335  * atomicity of device memory accesses. The recommended practice for coding device
23336  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23337  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23338  * alt_write_dword() functions for 64 bit registers.
23339  *
23340  * The struct declaration for register ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0.
23341  */
23342 struct ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_s
23343 {
23344  volatile uint32_t ADDR : 5; /* ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR */
23345  uint32_t : 27; /* *UNDEFINED* */
23346 };
23347 
23348 /* The typedef declaration for register ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0. */
23349 typedef struct ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_s ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_t;
23350 #endif /* __ASSEMBLY__ */
23351 
23352 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0 register. */
23353 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_RESET 0x00000000
23354 /* The byte offset of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0 register from the beginning of the component. */
23355 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_OFST 0x180
23356 
23357 /*
23358  * Register : ECC_ERRGENHADDR_1
23359  *
23360  * Error address register
23361  *
23362  * Register Layout
23363  *
23364  * Bits | Access | Reset | Description
23365  * :-------|:-------|:------|:----------------------------------------
23366  * [4:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR
23367  * [31:5] | ??? | 0x0 | *UNDEFINED*
23368  *
23369  */
23370 /*
23371  * Field : ADDR
23372  *
23373  * For decoder 1.
23374  *
23375  * High address generated with SER or address mismatch logic. Address will be
23376  * driven by the ECC decoder on every read latched by the RAM independent of
23377  * ECCDiagon is on.
23378  *
23379  * Field Access Macros:
23380  *
23381  */
23382 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR register field. */
23383 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR_LSB 0
23384 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR register field. */
23385 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR_MSB 4
23386 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR register field. */
23387 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR_WIDTH 5
23388 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR register field value. */
23389 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR_SET_MSK 0x0000001f
23390 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR register field value. */
23391 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR_CLR_MSK 0xffffffe0
23392 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR register field. */
23393 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR_RESET 0x0
23394 /* Extracts the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR field value from a register. */
23395 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR_GET(value) (((value) & 0x0000001f) >> 0)
23396 /* Produces a ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR register field value suitable for setting the register. */
23397 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR_SET(value) (((value) << 0) & 0x0000001f)
23398 
23399 #ifndef __ASSEMBLY__
23400 /*
23401  * WARNING: The C register and register group struct declarations are provided for
23402  * convenience and illustrative purposes. They should, however, be used with
23403  * caution as the C language standard provides no guarantees about the alignment or
23404  * atomicity of device memory accesses. The recommended practice for coding device
23405  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23406  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23407  * alt_write_dword() functions for 64 bit registers.
23408  *
23409  * The struct declaration for register ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1.
23410  */
23411 struct ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_s
23412 {
23413  volatile uint32_t ADDR : 5; /* ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR */
23414  uint32_t : 27; /* *UNDEFINED* */
23415 };
23416 
23417 /* The typedef declaration for register ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1. */
23418 typedef struct ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_s ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_t;
23419 #endif /* __ASSEMBLY__ */
23420 
23421 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1 register. */
23422 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_RESET 0x00000000
23423 /* The byte offset of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1 register from the beginning of the component. */
23424 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_OFST 0x184
23425 
23426 /*
23427  * Register : ECC_ERRGENHADDR_2
23428  *
23429  * Error address register
23430  *
23431  * Register Layout
23432  *
23433  * Bits | Access | Reset | Description
23434  * :-------|:-------|:------|:----------------------------------------
23435  * [4:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR
23436  * [31:5] | ??? | 0x0 | *UNDEFINED*
23437  *
23438  */
23439 /*
23440  * Field : ADDR
23441  *
23442  * For decoder 2.
23443  *
23444  * High address generated with SER or address mismatch logic. Address will be
23445  * driven by the ECC decoder on every read latched by the RAM independent of
23446  * ECCDiagon is on.
23447  *
23448  * Field Access Macros:
23449  *
23450  */
23451 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR register field. */
23452 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR_LSB 0
23453 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR register field. */
23454 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR_MSB 4
23455 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR register field. */
23456 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR_WIDTH 5
23457 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR register field value. */
23458 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR_SET_MSK 0x0000001f
23459 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR register field value. */
23460 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR_CLR_MSK 0xffffffe0
23461 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR register field. */
23462 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR_RESET 0x0
23463 /* Extracts the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR field value from a register. */
23464 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR_GET(value) (((value) & 0x0000001f) >> 0)
23465 /* Produces a ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR register field value suitable for setting the register. */
23466 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR_SET(value) (((value) << 0) & 0x0000001f)
23467 
23468 #ifndef __ASSEMBLY__
23469 /*
23470  * WARNING: The C register and register group struct declarations are provided for
23471  * convenience and illustrative purposes. They should, however, be used with
23472  * caution as the C language standard provides no guarantees about the alignment or
23473  * atomicity of device memory accesses. The recommended practice for coding device
23474  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23475  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23476  * alt_write_dword() functions for 64 bit registers.
23477  *
23478  * The struct declaration for register ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2.
23479  */
23480 struct ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_s
23481 {
23482  volatile uint32_t ADDR : 5; /* ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR */
23483  uint32_t : 27; /* *UNDEFINED* */
23484 };
23485 
23486 /* The typedef declaration for register ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2. */
23487 typedef struct ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_s ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_t;
23488 #endif /* __ASSEMBLY__ */
23489 
23490 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2 register. */
23491 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_RESET 0x00000000
23492 /* The byte offset of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2 register from the beginning of the component. */
23493 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_OFST 0x188
23494 
23495 /*
23496  * Register : ECC_ERRGENHADDR_3
23497  *
23498  * Error address register
23499  *
23500  * Register Layout
23501  *
23502  * Bits | Access | Reset | Description
23503  * :-------|:-------|:------|:----------------------------------------
23504  * [4:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR
23505  * [31:5] | ??? | 0x0 | *UNDEFINED*
23506  *
23507  */
23508 /*
23509  * Field : ADDR
23510  *
23511  * For decoder 3.
23512  *
23513  * High address generated with SER or address mismatch logic. Address will be
23514  * driven by the ECC decoder on every read latched by the RAM independent of
23515  * ECCDiagon is on.
23516  *
23517  * Field Access Macros:
23518  *
23519  */
23520 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR register field. */
23521 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR_LSB 0
23522 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR register field. */
23523 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR_MSB 4
23524 /* The width in bits of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR register field. */
23525 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR_WIDTH 5
23526 /* The mask used to set the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR register field value. */
23527 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR_SET_MSK 0x0000001f
23528 /* The mask used to clear the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR register field value. */
23529 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR_CLR_MSK 0xffffffe0
23530 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR register field. */
23531 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR_RESET 0x0
23532 /* Extracts the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR field value from a register. */
23533 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR_GET(value) (((value) & 0x0000001f) >> 0)
23534 /* Produces a ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR register field value suitable for setting the register. */
23535 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR_SET(value) (((value) << 0) & 0x0000001f)
23536 
23537 #ifndef __ASSEMBLY__
23538 /*
23539  * WARNING: The C register and register group struct declarations are provided for
23540  * convenience and illustrative purposes. They should, however, be used with
23541  * caution as the C language standard provides no guarantees about the alignment or
23542  * atomicity of device memory accesses. The recommended practice for coding device
23543  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23544  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23545  * alt_write_dword() functions for 64 bit registers.
23546  *
23547  * The struct declaration for register ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3.
23548  */
23549 struct ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_s
23550 {
23551  volatile uint32_t ADDR : 5; /* ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR */
23552  uint32_t : 27; /* *UNDEFINED* */
23553 };
23554 
23555 /* The typedef declaration for register ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3. */
23556 typedef struct ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_s ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_t;
23557 #endif /* __ASSEMBLY__ */
23558 
23559 /* The reset value of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3 register. */
23560 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_RESET 0x00000000
23561 /* The byte offset of the ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3 register from the beginning of the component. */
23562 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_OFST 0x18c
23563 
23564 /*
23565  * Register : DERRHADDR
23566  *
23567  * Double-bit error high address
23568  *
23569  * Register Layout
23570  *
23571  * Bits | Access | Reset | Description
23572  * :-------|:-------|:------|:------------------------------------
23573  * [4:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS
23574  * [31:5] | ??? | 0x0 | *UNDEFINED*
23575  *
23576  */
23577 /*
23578  * Field : DADDRESS
23579  *
23580  * Recent DBE High address.
23581  *
23582  * This register shows the address of the current double-bit error. RAM size will
23583  * determine the maximum number of address bits.
23584  *
23585  * This address is logged when a new derr_req or bus error is generated to the
23586  * system. This is gated by the ecc_en enable bit and derrinten bit.
23587  *
23588  * Field Access Macros:
23589  *
23590  */
23591 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS register field. */
23592 #define ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS_LSB 0
23593 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS register field. */
23594 #define ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS_MSB 4
23595 /* The width in bits of the ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS register field. */
23596 #define ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS_WIDTH 5
23597 /* The mask used to set the ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS register field value. */
23598 #define ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS_SET_MSK 0x0000001f
23599 /* The mask used to clear the ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS register field value. */
23600 #define ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS_CLR_MSK 0xffffffe0
23601 /* The reset value of the ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS register field. */
23602 #define ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS_RESET 0x0
23603 /* Extracts the ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS field value from a register. */
23604 #define ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS_GET(value) (((value) & 0x0000001f) >> 0)
23605 /* Produces a ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS register field value suitable for setting the register. */
23606 #define ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS_SET(value) (((value) << 0) & 0x0000001f)
23607 
23608 #ifndef __ASSEMBLY__
23609 /*
23610  * WARNING: The C register and register group struct declarations are provided for
23611  * convenience and illustrative purposes. They should, however, be used with
23612  * caution as the C language standard provides no guarantees about the alignment or
23613  * atomicity of device memory accesses. The recommended practice for coding device
23614  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23615  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23616  * alt_write_dword() functions for 64 bit registers.
23617  *
23618  * The struct declaration for register ALT_MPFE_HMC_ADP_DERRHADDR.
23619  */
23620 struct ALT_MPFE_HMC_ADP_DERRHADDR_s
23621 {
23622  volatile uint32_t DADDRESS : 5; /* ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS */
23623  uint32_t : 27; /* *UNDEFINED* */
23624 };
23625 
23626 /* The typedef declaration for register ALT_MPFE_HMC_ADP_DERRHADDR. */
23627 typedef struct ALT_MPFE_HMC_ADP_DERRHADDR_s ALT_MPFE_HMC_ADP_DERRHADDR_t;
23628 #endif /* __ASSEMBLY__ */
23629 
23630 /* The reset value of the ALT_MPFE_HMC_ADP_DERRHADDR register. */
23631 #define ALT_MPFE_HMC_ADP_DERRHADDR_RESET 0x00000000
23632 /* The byte offset of the ALT_MPFE_HMC_ADP_DERRHADDR register from the beginning of the component. */
23633 #define ALT_MPFE_HMC_ADP_DERRHADDR_OFST 0x1b0
23634 
23635 /*
23636  * Register : SERRHADDR
23637  *
23638  * Single-bit error address
23639  *
23640  * Register Layout
23641  *
23642  * Bits | Access | Reset | Description
23643  * :-------|:-------|:------|:------------------------------------
23644  * [4:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS
23645  * [31:5] | ??? | 0x0 | *UNDEFINED*
23646  *
23647  */
23648 /*
23649  * Field : SADDRESS
23650  *
23651  * Recent SBE High address.
23652  *
23653  * This register shows the address of the current single-bit error. This address is
23654  * logged when a new serr_req is generated to the system. This is gated by the
23655  * single-bit error interrupt enable and ecc_en.
23656  *
23657  * Field Access Macros:
23658  *
23659  */
23660 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS register field. */
23661 #define ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS_LSB 0
23662 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS register field. */
23663 #define ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS_MSB 4
23664 /* The width in bits of the ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS register field. */
23665 #define ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS_WIDTH 5
23666 /* The mask used to set the ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS register field value. */
23667 #define ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS_SET_MSK 0x0000001f
23668 /* The mask used to clear the ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS register field value. */
23669 #define ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS_CLR_MSK 0xffffffe0
23670 /* The reset value of the ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS register field. */
23671 #define ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS_RESET 0x0
23672 /* Extracts the ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS field value from a register. */
23673 #define ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS_GET(value) (((value) & 0x0000001f) >> 0)
23674 /* Produces a ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS register field value suitable for setting the register. */
23675 #define ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS_SET(value) (((value) << 0) & 0x0000001f)
23676 
23677 #ifndef __ASSEMBLY__
23678 /*
23679  * WARNING: The C register and register group struct declarations are provided for
23680  * convenience and illustrative purposes. They should, however, be used with
23681  * caution as the C language standard provides no guarantees about the alignment or
23682  * atomicity of device memory accesses. The recommended practice for coding device
23683  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23684  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23685  * alt_write_dword() functions for 64 bit registers.
23686  *
23687  * The struct declaration for register ALT_MPFE_HMC_ADP_SERRHADDR.
23688  */
23689 struct ALT_MPFE_HMC_ADP_SERRHADDR_s
23690 {
23691  volatile uint32_t SADDRESS : 5; /* ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS */
23692  uint32_t : 27; /* *UNDEFINED* */
23693 };
23694 
23695 /* The typedef declaration for register ALT_MPFE_HMC_ADP_SERRHADDR. */
23696 typedef struct ALT_MPFE_HMC_ADP_SERRHADDR_s ALT_MPFE_HMC_ADP_SERRHADDR_t;
23697 #endif /* __ASSEMBLY__ */
23698 
23699 /* The reset value of the ALT_MPFE_HMC_ADP_SERRHADDR register. */
23700 #define ALT_MPFE_HMC_ADP_SERRHADDR_RESET 0x00000000
23701 /* The byte offset of the ALT_MPFE_HMC_ADP_SERRHADDR register from the beginning of the component. */
23702 #define ALT_MPFE_HMC_ADP_SERRHADDR_OFST 0x1b4
23703 
23704 /*
23705  * Register : AUTOWB_CORRHADDR
23706  *
23707  * This register shows the high address of the current autoWB correction SBE.
23708  *
23709  * Register Layout
23710  *
23711  * Bits | Access | Reset | Description
23712  * :-------|:-------|:------|:---------------------------------------------
23713  * [4:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS
23714  * [31:5] | ??? | 0x0 | *UNDEFINED*
23715  *
23716  */
23717 /*
23718  * Field : SWBADDRESS
23719  *
23720  * recent autoWB correction high address.
23721  *
23722  * This register shows the address of the current autoWB correction single-bit
23723  * error. This address is logged when a new serr_req is generated to the system.
23724  * This is gated by the single-bit error interrupt enable and ecc_en.
23725  *
23726  * Field Access Macros:
23727  *
23728  */
23729 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS register field. */
23730 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS_LSB 0
23731 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS register field. */
23732 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS_MSB 4
23733 /* The width in bits of the ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS register field. */
23734 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS_WIDTH 5
23735 /* The mask used to set the ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS register field value. */
23736 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS_SET_MSK 0x0000001f
23737 /* The mask used to clear the ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS register field value. */
23738 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS_CLR_MSK 0xffffffe0
23739 /* The reset value of the ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS register field. */
23740 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS_RESET 0x0
23741 /* Extracts the ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS field value from a register. */
23742 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS_GET(value) (((value) & 0x0000001f) >> 0)
23743 /* Produces a ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS register field value suitable for setting the register. */
23744 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS_SET(value) (((value) << 0) & 0x0000001f)
23745 
23746 #ifndef __ASSEMBLY__
23747 /*
23748  * WARNING: The C register and register group struct declarations are provided for
23749  * convenience and illustrative purposes. They should, however, be used with
23750  * caution as the C language standard provides no guarantees about the alignment or
23751  * atomicity of device memory accesses. The recommended practice for coding device
23752  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23753  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23754  * alt_write_dword() functions for 64 bit registers.
23755  *
23756  * The struct declaration for register ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR.
23757  */
23758 struct ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_s
23759 {
23760  volatile uint32_t SWBADDRESS : 5; /* ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS */
23761  uint32_t : 27; /* *UNDEFINED* */
23762 };
23763 
23764 /* The typedef declaration for register ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR. */
23765 typedef struct ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_s ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_t;
23766 #endif /* __ASSEMBLY__ */
23767 
23768 /* The reset value of the ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR register. */
23769 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_RESET 0x00000000
23770 /* The byte offset of the ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR register from the beginning of the component. */
23771 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_OFST 0x1bc
23772 
23773 /*
23774  * Register : HPSINTFCSEL
23775  *
23776  * HPS interface Enable
23777  *
23778  * Register Layout
23779  *
23780  * Bits | Access | Reset | Description
23781  * :--------|:-------|:------|:-----------------------------------------
23782  * [0] | RW | 0x0 | ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0
23783  * [1] | RW | 0x0 | ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1
23784  * [2] | RW | 0x0 | ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2
23785  * [3] | RW | 0x0 | ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3
23786  * [4] | RW | 0x0 | ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC
23787  * [7:5] | ??? | 0x0 | *UNDEFINED*
23788  * [8] | RW | 0x0 | ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0
23789  * [9] | RW | 0x0 | ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1
23790  * [10] | RW | 0x0 | ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2
23791  * [11] | RW | 0x0 | ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3
23792  * [12] | RW | 0x0 | ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC
23793  * [15:13] | ??? | 0x0 | *UNDEFINED*
23794  * [16] | RW | 0x0 | ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0
23795  * [17] | RW | 0x0 | ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1
23796  * [18] | RW | 0x0 | ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2
23797  * [19] | RW | 0x0 | ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3
23798  * [20] | RW | 0x0 | ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC
23799  * [31:21] | ??? | 0x0 | *UNDEFINED*
23800  *
23801  */
23802 /*
23803  * Field : TILEA_LANE0
23804  *
23805  * To select which path of signals connect to Tile A lane 0 (fabric wires stealing)
23806  *
23807  * 1'b0 : Set 0 to choose fabric path (Default value after reset)
23808  *
23809  * 1'b1: Set 1 to choose HMC adaptor path
23810  *
23811  * Field Enumeration Values:
23812  *
23813  * Enum | Value | Description
23814  * :------------------------------------------------|:------|:------------
23815  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0_E_FPGA | 0x0 |
23816  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0_E_HPS | 0x1 |
23817  *
23818  * Field Access Macros:
23819  *
23820  */
23821 /*
23822  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0
23823  *
23824  */
23825 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0_E_FPGA 0x0
23826 /*
23827  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0
23828  *
23829  */
23830 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0_E_HPS 0x1
23831 
23832 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0 register field. */
23833 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0_LSB 0
23834 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0 register field. */
23835 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0_MSB 0
23836 /* The width in bits of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0 register field. */
23837 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0_WIDTH 1
23838 /* The mask used to set the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0 register field value. */
23839 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0_SET_MSK 0x00000001
23840 /* The mask used to clear the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0 register field value. */
23841 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0_CLR_MSK 0xfffffffe
23842 /* The reset value of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0 register field. */
23843 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0_RESET 0x0
23844 /* Extracts the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0 field value from a register. */
23845 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0_GET(value) (((value) & 0x00000001) >> 0)
23846 /* Produces a ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0 register field value suitable for setting the register. */
23847 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0_SET(value) (((value) << 0) & 0x00000001)
23848 
23849 /*
23850  * Field : TILEA_LANE1
23851  *
23852  * To select which path of signals connect to Tile A lane 1 (fabric wires stealing)
23853  *
23854  * 1'b0 : Set 0 to choose fabric path (Default value after reset)
23855  *
23856  * 1'b1: Set 1 to choose HMC adaptor path
23857  *
23858  * Field Enumeration Values:
23859  *
23860  * Enum | Value | Description
23861  * :------------------------------------------------|:------|:------------
23862  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1_E_FPGA | 0x0 |
23863  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1_E_HPS | 0x1 |
23864  *
23865  * Field Access Macros:
23866  *
23867  */
23868 /*
23869  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1
23870  *
23871  */
23872 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1_E_FPGA 0x0
23873 /*
23874  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1
23875  *
23876  */
23877 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1_E_HPS 0x1
23878 
23879 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1 register field. */
23880 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1_LSB 1
23881 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1 register field. */
23882 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1_MSB 1
23883 /* The width in bits of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1 register field. */
23884 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1_WIDTH 1
23885 /* The mask used to set the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1 register field value. */
23886 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1_SET_MSK 0x00000002
23887 /* The mask used to clear the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1 register field value. */
23888 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1_CLR_MSK 0xfffffffd
23889 /* The reset value of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1 register field. */
23890 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1_RESET 0x0
23891 /* Extracts the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1 field value from a register. */
23892 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1_GET(value) (((value) & 0x00000002) >> 1)
23893 /* Produces a ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1 register field value suitable for setting the register. */
23894 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1_SET(value) (((value) << 1) & 0x00000002)
23895 
23896 /*
23897  * Field : TILEA_LANE2
23898  *
23899  * To select which path of signals connect to Tile A lane 2 (fabric wires stealing)
23900  *
23901  * 1'b0 : Set 0 to choose fabric path (Default value after reset)
23902  *
23903  * 1'b1: Set 1 to choose HMC adaptor path
23904  *
23905  * Field Enumeration Values:
23906  *
23907  * Enum | Value | Description
23908  * :------------------------------------------------|:------|:------------
23909  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2_E_FPGA | 0x0 |
23910  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2_E_HPS | 0x1 |
23911  *
23912  * Field Access Macros:
23913  *
23914  */
23915 /*
23916  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2
23917  *
23918  */
23919 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2_E_FPGA 0x0
23920 /*
23921  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2
23922  *
23923  */
23924 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2_E_HPS 0x1
23925 
23926 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2 register field. */
23927 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2_LSB 2
23928 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2 register field. */
23929 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2_MSB 2
23930 /* The width in bits of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2 register field. */
23931 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2_WIDTH 1
23932 /* The mask used to set the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2 register field value. */
23933 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2_SET_MSK 0x00000004
23934 /* The mask used to clear the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2 register field value. */
23935 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2_CLR_MSK 0xfffffffb
23936 /* The reset value of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2 register field. */
23937 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2_RESET 0x0
23938 /* Extracts the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2 field value from a register. */
23939 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2_GET(value) (((value) & 0x00000004) >> 2)
23940 /* Produces a ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2 register field value suitable for setting the register. */
23941 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2_SET(value) (((value) << 2) & 0x00000004)
23942 
23943 /*
23944  * Field : TILEA_LANE3
23945  *
23946  * To select which path of signals connect to Tile A lane 3 (fabric wires stealing)
23947  *
23948  * 1'b0 : Set 0 to choose fabric path (Default value after reset)
23949  *
23950  * 1'b1: Set 1 to choose HMC adaptor path
23951  *
23952  * Field Enumeration Values:
23953  *
23954  * Enum | Value | Description
23955  * :------------------------------------------------|:------|:------------
23956  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3_E_FPGA | 0x0 |
23957  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3_E_HPS | 0x1 |
23958  *
23959  * Field Access Macros:
23960  *
23961  */
23962 /*
23963  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3
23964  *
23965  */
23966 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3_E_FPGA 0x0
23967 /*
23968  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3
23969  *
23970  */
23971 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3_E_HPS 0x1
23972 
23973 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3 register field. */
23974 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3_LSB 3
23975 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3 register field. */
23976 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3_MSB 3
23977 /* The width in bits of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3 register field. */
23978 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3_WIDTH 1
23979 /* The mask used to set the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3 register field value. */
23980 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3_SET_MSK 0x00000008
23981 /* The mask used to clear the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3 register field value. */
23982 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3_CLR_MSK 0xfffffff7
23983 /* The reset value of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3 register field. */
23984 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3_RESET 0x0
23985 /* Extracts the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3 field value from a register. */
23986 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3_GET(value) (((value) & 0x00000008) >> 3)
23987 /* Produces a ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3 register field value suitable for setting the register. */
23988 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3_SET(value) (((value) << 3) & 0x00000008)
23989 
23990 /*
23991  * Field : TILEA_HMC
23992  *
23993  * To select which path of signals connect to Tile A HMC (fabric wires stealing)
23994  *
23995  * 1'b0 : Set 0 to choose fabric path (Default value after reset)
23996  *
23997  * 1'b1: Set 1 to choose HMC adaptor path
23998  *
23999  * Field Enumeration Values:
24000  *
24001  * Enum | Value | Description
24002  * :----------------------------------------------|:------|:------------
24003  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC_E_FPGA | 0x0 |
24004  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC_E_HPS | 0x1 |
24005  *
24006  * Field Access Macros:
24007  *
24008  */
24009 /*
24010  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC
24011  *
24012  */
24013 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC_E_FPGA 0x0
24014 /*
24015  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC
24016  *
24017  */
24018 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC_E_HPS 0x1
24019 
24020 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC register field. */
24021 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC_LSB 4
24022 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC register field. */
24023 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC_MSB 4
24024 /* The width in bits of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC register field. */
24025 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC_WIDTH 1
24026 /* The mask used to set the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC register field value. */
24027 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC_SET_MSK 0x00000010
24028 /* The mask used to clear the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC register field value. */
24029 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC_CLR_MSK 0xffffffef
24030 /* The reset value of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC register field. */
24031 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC_RESET 0x0
24032 /* Extracts the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC field value from a register. */
24033 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC_GET(value) (((value) & 0x00000010) >> 4)
24034 /* Produces a ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC register field value suitable for setting the register. */
24035 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC_SET(value) (((value) << 4) & 0x00000010)
24036 
24037 /*
24038  * Field : TILEB_LANE0
24039  *
24040  * To select which path of signals connect to Tile B lane 0 (fabric wires stealing)
24041  *
24042  * 1'b0 : Set 0 to choose fabric path (Default value after reset)
24043  *
24044  * 1'b1: Set 1 to choose HMC adaptor path
24045  *
24046  * Field Enumeration Values:
24047  *
24048  * Enum | Value | Description
24049  * :------------------------------------------------|:------|:------------
24050  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0_E_FPGA | 0x0 |
24051  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0_E_HPS | 0x1 |
24052  *
24053  * Field Access Macros:
24054  *
24055  */
24056 /*
24057  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0
24058  *
24059  */
24060 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0_E_FPGA 0x0
24061 /*
24062  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0
24063  *
24064  */
24065 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0_E_HPS 0x1
24066 
24067 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0 register field. */
24068 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0_LSB 8
24069 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0 register field. */
24070 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0_MSB 8
24071 /* The width in bits of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0 register field. */
24072 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0_WIDTH 1
24073 /* The mask used to set the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0 register field value. */
24074 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0_SET_MSK 0x00000100
24075 /* The mask used to clear the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0 register field value. */
24076 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0_CLR_MSK 0xfffffeff
24077 /* The reset value of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0 register field. */
24078 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0_RESET 0x0
24079 /* Extracts the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0 field value from a register. */
24080 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0_GET(value) (((value) & 0x00000100) >> 8)
24081 /* Produces a ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0 register field value suitable for setting the register. */
24082 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0_SET(value) (((value) << 8) & 0x00000100)
24083 
24084 /*
24085  * Field : TILEB_LANE1
24086  *
24087  * To select which path of signals connect to Tile B lane 1 (fabric wires stealing)
24088  *
24089  * 1'b0 : Set 0 to choose fabric path (Default value after reset)
24090  *
24091  * 1'b1: Set 1 to choose HMC adaptor path
24092  *
24093  * Field Enumeration Values:
24094  *
24095  * Enum | Value | Description
24096  * :------------------------------------------------|:------|:------------
24097  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1_E_FPGA | 0x0 |
24098  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1_E_HPS | 0x1 |
24099  *
24100  * Field Access Macros:
24101  *
24102  */
24103 /*
24104  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1
24105  *
24106  */
24107 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1_E_FPGA 0x0
24108 /*
24109  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1
24110  *
24111  */
24112 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1_E_HPS 0x1
24113 
24114 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1 register field. */
24115 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1_LSB 9
24116 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1 register field. */
24117 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1_MSB 9
24118 /* The width in bits of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1 register field. */
24119 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1_WIDTH 1
24120 /* The mask used to set the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1 register field value. */
24121 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1_SET_MSK 0x00000200
24122 /* The mask used to clear the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1 register field value. */
24123 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1_CLR_MSK 0xfffffdff
24124 /* The reset value of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1 register field. */
24125 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1_RESET 0x0
24126 /* Extracts the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1 field value from a register. */
24127 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1_GET(value) (((value) & 0x00000200) >> 9)
24128 /* Produces a ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1 register field value suitable for setting the register. */
24129 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1_SET(value) (((value) << 9) & 0x00000200)
24130 
24131 /*
24132  * Field : TILEB_LANE2
24133  *
24134  * To select which path of signals connect to Tile B lane 2 (fabric wires stealing)
24135  *
24136  * 1'b0 : Set 0 to choose fabric path (Default value after reset)
24137  *
24138  * 1'b1: Set 1 to choose HMC adaptor path
24139  *
24140  * Field Enumeration Values:
24141  *
24142  * Enum | Value | Description
24143  * :------------------------------------------------|:------|:------------
24144  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2_E_FPGA | 0x0 |
24145  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2_E_HPS | 0x1 |
24146  *
24147  * Field Access Macros:
24148  *
24149  */
24150 /*
24151  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2
24152  *
24153  */
24154 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2_E_FPGA 0x0
24155 /*
24156  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2
24157  *
24158  */
24159 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2_E_HPS 0x1
24160 
24161 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2 register field. */
24162 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2_LSB 10
24163 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2 register field. */
24164 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2_MSB 10
24165 /* The width in bits of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2 register field. */
24166 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2_WIDTH 1
24167 /* The mask used to set the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2 register field value. */
24168 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2_SET_MSK 0x00000400
24169 /* The mask used to clear the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2 register field value. */
24170 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2_CLR_MSK 0xfffffbff
24171 /* The reset value of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2 register field. */
24172 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2_RESET 0x0
24173 /* Extracts the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2 field value from a register. */
24174 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2_GET(value) (((value) & 0x00000400) >> 10)
24175 /* Produces a ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2 register field value suitable for setting the register. */
24176 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2_SET(value) (((value) << 10) & 0x00000400)
24177 
24178 /*
24179  * Field : TILEB_LANE3
24180  *
24181  * To select which path of signals connect to Tile B lane 3 (fabric wires stealing)
24182  *
24183  * 1'b0 : Set 0 to choose fabric path (Default value after reset)
24184  *
24185  * 1'b1: Set 1 to choose HMC adaptor path
24186  *
24187  * Field Enumeration Values:
24188  *
24189  * Enum | Value | Description
24190  * :------------------------------------------------|:------|:------------
24191  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3_E_FPGA | 0x0 |
24192  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3_E_HPS | 0x1 |
24193  *
24194  * Field Access Macros:
24195  *
24196  */
24197 /*
24198  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3
24199  *
24200  */
24201 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3_E_FPGA 0x0
24202 /*
24203  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3
24204  *
24205  */
24206 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3_E_HPS 0x1
24207 
24208 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3 register field. */
24209 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3_LSB 11
24210 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3 register field. */
24211 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3_MSB 11
24212 /* The width in bits of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3 register field. */
24213 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3_WIDTH 1
24214 /* The mask used to set the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3 register field value. */
24215 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3_SET_MSK 0x00000800
24216 /* The mask used to clear the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3 register field value. */
24217 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3_CLR_MSK 0xfffff7ff
24218 /* The reset value of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3 register field. */
24219 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3_RESET 0x0
24220 /* Extracts the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3 field value from a register. */
24221 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3_GET(value) (((value) & 0x00000800) >> 11)
24222 /* Produces a ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3 register field value suitable for setting the register. */
24223 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3_SET(value) (((value) << 11) & 0x00000800)
24224 
24225 /*
24226  * Field : TILEB_HMC
24227  *
24228  * To select which path of signals connect to Tile B HMC (fabric wires stealing)
24229  *
24230  * 1'b0 : Set 0 to choose fabric path (Default value after reset)
24231  *
24232  * 1'b1: Set 1 to choose HMC adaptor path
24233  *
24234  * Field Enumeration Values:
24235  *
24236  * Enum | Value | Description
24237  * :----------------------------------------------|:------|:------------
24238  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC_E_FPGA | 0x0 |
24239  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC_E_HPS | 0x1 |
24240  *
24241  * Field Access Macros:
24242  *
24243  */
24244 /*
24245  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC
24246  *
24247  */
24248 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC_E_FPGA 0x0
24249 /*
24250  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC
24251  *
24252  */
24253 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC_E_HPS 0x1
24254 
24255 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC register field. */
24256 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC_LSB 12
24257 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC register field. */
24258 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC_MSB 12
24259 /* The width in bits of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC register field. */
24260 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC_WIDTH 1
24261 /* The mask used to set the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC register field value. */
24262 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC_SET_MSK 0x00001000
24263 /* The mask used to clear the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC register field value. */
24264 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC_CLR_MSK 0xffffefff
24265 /* The reset value of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC register field. */
24266 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC_RESET 0x0
24267 /* Extracts the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC field value from a register. */
24268 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC_GET(value) (((value) & 0x00001000) >> 12)
24269 /* Produces a ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC register field value suitable for setting the register. */
24270 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC_SET(value) (((value) << 12) & 0x00001000)
24271 
24272 /*
24273  * Field : TILEC_LANE0
24274  *
24275  * To select which path of signals connect to Tile C lane 0 (fabric wires stealing)
24276  *
24277  * 1'b0 : Set 0 to choose fabric path (Default value after reset)
24278  *
24279  * 1'b1: Set 1 to choose HMC adaptor path
24280  *
24281  * Field Enumeration Values:
24282  *
24283  * Enum | Value | Description
24284  * :------------------------------------------------|:------|:------------
24285  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0_E_FPGA | 0x0 |
24286  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0_E_HPS | 0x1 |
24287  *
24288  * Field Access Macros:
24289  *
24290  */
24291 /*
24292  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0
24293  *
24294  */
24295 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0_E_FPGA 0x0
24296 /*
24297  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0
24298  *
24299  */
24300 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0_E_HPS 0x1
24301 
24302 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0 register field. */
24303 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0_LSB 16
24304 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0 register field. */
24305 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0_MSB 16
24306 /* The width in bits of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0 register field. */
24307 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0_WIDTH 1
24308 /* The mask used to set the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0 register field value. */
24309 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0_SET_MSK 0x00010000
24310 /* The mask used to clear the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0 register field value. */
24311 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0_CLR_MSK 0xfffeffff
24312 /* The reset value of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0 register field. */
24313 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0_RESET 0x0
24314 /* Extracts the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0 field value from a register. */
24315 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0_GET(value) (((value) & 0x00010000) >> 16)
24316 /* Produces a ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0 register field value suitable for setting the register. */
24317 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0_SET(value) (((value) << 16) & 0x00010000)
24318 
24319 /*
24320  * Field : TILEC_LANE1
24321  *
24322  * To select which path of signals connect to Tile C lane 1 (fabric wires stealing)
24323  *
24324  * 1'b0 : Set 0 to choose fabric path (Default value after reset)
24325  *
24326  * 1'b1: Set 1 to choose HMC adaptor path
24327  *
24328  * Field Enumeration Values:
24329  *
24330  * Enum | Value | Description
24331  * :------------------------------------------------|:------|:------------
24332  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1_E_FPGA | 0x0 |
24333  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1_E_HPS | 0x1 |
24334  *
24335  * Field Access Macros:
24336  *
24337  */
24338 /*
24339  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1
24340  *
24341  */
24342 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1_E_FPGA 0x0
24343 /*
24344  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1
24345  *
24346  */
24347 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1_E_HPS 0x1
24348 
24349 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1 register field. */
24350 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1_LSB 17
24351 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1 register field. */
24352 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1_MSB 17
24353 /* The width in bits of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1 register field. */
24354 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1_WIDTH 1
24355 /* The mask used to set the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1 register field value. */
24356 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1_SET_MSK 0x00020000
24357 /* The mask used to clear the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1 register field value. */
24358 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1_CLR_MSK 0xfffdffff
24359 /* The reset value of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1 register field. */
24360 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1_RESET 0x0
24361 /* Extracts the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1 field value from a register. */
24362 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1_GET(value) (((value) & 0x00020000) >> 17)
24363 /* Produces a ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1 register field value suitable for setting the register. */
24364 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1_SET(value) (((value) << 17) & 0x00020000)
24365 
24366 /*
24367  * Field : TILEC_LANE2
24368  *
24369  * To select which path of signals connect to Tile C lane 2 (fabric wires stealing)
24370  *
24371  * 1'b0 : Set 0 to choose fabric path (Default value after reset)
24372  *
24373  * 1'b1: Set 1 to choose HMC adaptor path
24374  *
24375  * Field Enumeration Values:
24376  *
24377  * Enum | Value | Description
24378  * :------------------------------------------------|:------|:------------
24379  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2_E_FPGA | 0x0 |
24380  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2_E_HPS | 0x1 |
24381  *
24382  * Field Access Macros:
24383  *
24384  */
24385 /*
24386  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2
24387  *
24388  */
24389 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2_E_FPGA 0x0
24390 /*
24391  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2
24392  *
24393  */
24394 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2_E_HPS 0x1
24395 
24396 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2 register field. */
24397 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2_LSB 18
24398 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2 register field. */
24399 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2_MSB 18
24400 /* The width in bits of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2 register field. */
24401 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2_WIDTH 1
24402 /* The mask used to set the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2 register field value. */
24403 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2_SET_MSK 0x00040000
24404 /* The mask used to clear the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2 register field value. */
24405 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2_CLR_MSK 0xfffbffff
24406 /* The reset value of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2 register field. */
24407 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2_RESET 0x0
24408 /* Extracts the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2 field value from a register. */
24409 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2_GET(value) (((value) & 0x00040000) >> 18)
24410 /* Produces a ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2 register field value suitable for setting the register. */
24411 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2_SET(value) (((value) << 18) & 0x00040000)
24412 
24413 /*
24414  * Field : TILEC_LANE3
24415  *
24416  * To select which path of signals connect to Tile C lane 3 (fabric wires stealing)
24417  *
24418  * 1'b0 : Set 0 to choose fabric path (Default value after reset)
24419  *
24420  * 1'b1: Set 1 to choose HMC adaptor path
24421  *
24422  * Field Enumeration Values:
24423  *
24424  * Enum | Value | Description
24425  * :------------------------------------------------|:------|:------------
24426  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3_E_FPGA | 0x0 |
24427  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3_E_HPS | 0x1 |
24428  *
24429  * Field Access Macros:
24430  *
24431  */
24432 /*
24433  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3
24434  *
24435  */
24436 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3_E_FPGA 0x0
24437 /*
24438  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3
24439  *
24440  */
24441 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3_E_HPS 0x1
24442 
24443 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3 register field. */
24444 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3_LSB 19
24445 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3 register field. */
24446 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3_MSB 19
24447 /* The width in bits of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3 register field. */
24448 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3_WIDTH 1
24449 /* The mask used to set the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3 register field value. */
24450 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3_SET_MSK 0x00080000
24451 /* The mask used to clear the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3 register field value. */
24452 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3_CLR_MSK 0xfff7ffff
24453 /* The reset value of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3 register field. */
24454 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3_RESET 0x0
24455 /* Extracts the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3 field value from a register. */
24456 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3_GET(value) (((value) & 0x00080000) >> 19)
24457 /* Produces a ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3 register field value suitable for setting the register. */
24458 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3_SET(value) (((value) << 19) & 0x00080000)
24459 
24460 /*
24461  * Field : TILEC_HMC
24462  *
24463  * To select which path of signals connect to Tile C HMC (fabric wires stealing)
24464  *
24465  * 1'b0 : Set 0 to choose fabric path (Default value after reset)
24466  *
24467  * 1'b1: Set 1 to choose HMC adaptor path
24468  *
24469  * Field Enumeration Values:
24470  *
24471  * Enum | Value | Description
24472  * :----------------------------------------------|:------|:------------
24473  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC_E_FPGA | 0x0 |
24474  * ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC_E_HPS | 0x1 |
24475  *
24476  * Field Access Macros:
24477  *
24478  */
24479 /*
24480  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC
24481  *
24482  */
24483 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC_E_FPGA 0x0
24484 /*
24485  * Enumerated value for register field ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC
24486  *
24487  */
24488 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC_E_HPS 0x1
24489 
24490 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC register field. */
24491 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC_LSB 20
24492 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC register field. */
24493 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC_MSB 20
24494 /* The width in bits of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC register field. */
24495 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC_WIDTH 1
24496 /* The mask used to set the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC register field value. */
24497 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC_SET_MSK 0x00100000
24498 /* The mask used to clear the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC register field value. */
24499 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC_CLR_MSK 0xffefffff
24500 /* The reset value of the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC register field. */
24501 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC_RESET 0x0
24502 /* Extracts the ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC field value from a register. */
24503 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC_GET(value) (((value) & 0x00100000) >> 20)
24504 /* Produces a ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC register field value suitable for setting the register. */
24505 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC_SET(value) (((value) << 20) & 0x00100000)
24506 
24507 #ifndef __ASSEMBLY__
24508 /*
24509  * WARNING: The C register and register group struct declarations are provided for
24510  * convenience and illustrative purposes. They should, however, be used with
24511  * caution as the C language standard provides no guarantees about the alignment or
24512  * atomicity of device memory accesses. The recommended practice for coding device
24513  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
24514  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
24515  * alt_write_dword() functions for 64 bit registers.
24516  *
24517  * The struct declaration for register ALT_MPFE_HMC_ADP_HPSINTFCSEL.
24518  */
24519 struct ALT_MPFE_HMC_ADP_HPSINTFCSEL_s
24520 {
24521  volatile uint32_t TILEA_LANE0 : 1; /* ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0 */
24522  volatile uint32_t TILEA_LANE1 : 1; /* ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1 */
24523  volatile uint32_t TILEA_LANE2 : 1; /* ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2 */
24524  volatile uint32_t TILEA_LANE3 : 1; /* ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3 */
24525  volatile uint32_t TILEA_HMC : 1; /* ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC */
24526  uint32_t : 3; /* *UNDEFINED* */
24527  volatile uint32_t TILEB_LANE0 : 1; /* ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0 */
24528  volatile uint32_t TILEB_LANE1 : 1; /* ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1 */
24529  volatile uint32_t TILEB_LANE2 : 1; /* ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2 */
24530  volatile uint32_t TILEB_LANE3 : 1; /* ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3 */
24531  volatile uint32_t TILEB_HMC : 1; /* ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC */
24532  uint32_t : 3; /* *UNDEFINED* */
24533  volatile uint32_t TILEC_LANE0 : 1; /* ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0 */
24534  volatile uint32_t TILEC_LANE1 : 1; /* ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1 */
24535  volatile uint32_t TILEC_LANE2 : 1; /* ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2 */
24536  volatile uint32_t TILEC_LANE3 : 1; /* ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3 */
24537  volatile uint32_t TILEC_HMC : 1; /* ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC */
24538  uint32_t : 11; /* *UNDEFINED* */
24539 };
24540 
24541 /* The typedef declaration for register ALT_MPFE_HMC_ADP_HPSINTFCSEL. */
24542 typedef struct ALT_MPFE_HMC_ADP_HPSINTFCSEL_s ALT_MPFE_HMC_ADP_HPSINTFCSEL_t;
24543 #endif /* __ASSEMBLY__ */
24544 
24545 /* The reset value of the ALT_MPFE_HMC_ADP_HPSINTFCSEL register. */
24546 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_RESET 0x00000000
24547 /* The byte offset of the ALT_MPFE_HMC_ADP_HPSINTFCSEL register from the beginning of the component. */
24548 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_OFST 0x210
24549 
24550 /*
24551  * Register : RSTHANDSHAKECTRL
24552  *
24553  * reset handshaking from MPFE or ARM
24554  *
24555  * Register Layout
24556  *
24557  * Bits | Access | Reset | Description
24558  * :-------|:-------|:------|:-------------------------------------------
24559  * [7:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ
24560  * [31:8] | ??? | 0x0 | *UNDEFINED*
24561  *
24562  */
24563 /*
24564  * Field : CORE2SEQ
24565  *
24566  * core2seq register
24567  *
24568  * Field Access Macros:
24569  *
24570  */
24571 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ register field. */
24572 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ_LSB 0
24573 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ register field. */
24574 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ_MSB 7
24575 /* The width in bits of the ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ register field. */
24576 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ_WIDTH 8
24577 /* The mask used to set the ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ register field value. */
24578 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ_SET_MSK 0x000000ff
24579 /* The mask used to clear the ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ register field value. */
24580 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ_CLR_MSK 0xffffff00
24581 /* The reset value of the ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ register field. */
24582 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ_RESET 0x0
24583 /* Extracts the ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ field value from a register. */
24584 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ_GET(value) (((value) & 0x000000ff) >> 0)
24585 /* Produces a ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ register field value suitable for setting the register. */
24586 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ_SET(value) (((value) << 0) & 0x000000ff)
24587 
24588 #ifndef __ASSEMBLY__
24589 /*
24590  * WARNING: The C register and register group struct declarations are provided for
24591  * convenience and illustrative purposes. They should, however, be used with
24592  * caution as the C language standard provides no guarantees about the alignment or
24593  * atomicity of device memory accesses. The recommended practice for coding device
24594  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
24595  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
24596  * alt_write_dword() functions for 64 bit registers.
24597  *
24598  * The struct declaration for register ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL.
24599  */
24600 struct ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_s
24601 {
24602  volatile uint32_t CORE2SEQ : 8; /* ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ */
24603  uint32_t : 24; /* *UNDEFINED* */
24604 };
24605 
24606 /* The typedef declaration for register ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL. */
24607 typedef struct ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_s ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_t;
24608 #endif /* __ASSEMBLY__ */
24609 
24610 /* The reset value of the ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL register. */
24611 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_RESET 0x00000000
24612 /* The byte offset of the ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL register from the beginning of the component. */
24613 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_OFST 0x214
24614 
24615 /*
24616  * Register : RSTHANDSHAKESTAT
24617  *
24618  * Reset handshaking from IO48 or Nios
24619  *
24620  * Register Layout
24621  *
24622  * Bits | Access | Reset | Description
24623  * :-------|:-------|:------|:-------------------------------------------
24624  * [7:0] | RW | 0x0 | ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE
24625  * [31:8] | ??? | 0x0 | *UNDEFINED*
24626  *
24627  */
24628 /*
24629  * Field : SEQ2CORE
24630  *
24631  * seq2core register
24632  *
24633  * Field Access Macros:
24634  *
24635  */
24636 /* The Least Significant Bit (LSB) position of the ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE register field. */
24637 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE_LSB 0
24638 /* The Most Significant Bit (MSB) position of the ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE register field. */
24639 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE_MSB 7
24640 /* The width in bits of the ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE register field. */
24641 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE_WIDTH 8
24642 /* The mask used to set the ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE register field value. */
24643 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE_SET_MSK 0x000000ff
24644 /* The mask used to clear the ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE register field value. */
24645 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE_CLR_MSK 0xffffff00
24646 /* The reset value of the ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE register field. */
24647 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE_RESET 0x0
24648 /* Extracts the ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE field value from a register. */
24649 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE_GET(value) (((value) & 0x000000ff) >> 0)
24650 /* Produces a ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE register field value suitable for setting the register. */
24651 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE_SET(value) (((value) << 0) & 0x000000ff)
24652 
24653 #ifndef __ASSEMBLY__
24654 /*
24655  * WARNING: The C register and register group struct declarations are provided for
24656  * convenience and illustrative purposes. They should, however, be used with
24657  * caution as the C language standard provides no guarantees about the alignment or
24658  * atomicity of device memory accesses. The recommended practice for coding device
24659  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
24660  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
24661  * alt_write_dword() functions for 64 bit registers.
24662  *
24663  * The struct declaration for register ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT.
24664  */
24665 struct ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_s
24666 {
24667  volatile uint32_t SEQ2CORE : 8; /* ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE */
24668  uint32_t : 24; /* *UNDEFINED* */
24669 };
24670 
24671 /* The typedef declaration for register ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT. */
24672 typedef struct ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_s ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_t;
24673 #endif /* __ASSEMBLY__ */
24674 
24675 /* The reset value of the ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT register. */
24676 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_RESET 0x00000000
24677 /* The byte offset of the ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT register from the beginning of the component. */
24678 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_OFST 0x218
24679 
24680 #ifndef __ASSEMBLY__
24681 /*
24682  * WARNING: The C register and register group struct declarations are provided for
24683  * convenience and illustrative purposes. They should, however, be used with
24684  * caution as the C language standard provides no guarantees about the alignment or
24685  * atomicity of device memory accesses. The recommended practice for coding device
24686  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
24687  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
24688  * alt_write_dword() functions for 64 bit registers.
24689  *
24690  * The struct declaration for register group ALT_MPFE_HMC_ADP.
24691  */
24692 struct ALT_MPFE_HMC_ADP_s
24693 {
24694  volatile ALT_MPFE_HMC_ADP_IP_REV_ID_t IP_REV_ID; /* ALT_MPFE_HMC_ADP_IP_REV_ID */
24695  volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */
24696  volatile ALT_MPFE_HMC_ADP_DDRIOCTRL_t DDRIOCTRL; /* ALT_MPFE_HMC_ADP_DDRIOCTRL */
24697  volatile ALT_MPFE_HMC_ADP_DDRCALSTAT_t DDRCALSTAT; /* ALT_MPFE_HMC_ADP_DDRCALSTAT */
24698  volatile ALT_MPFE_HMC_ADP_MPR_0BEAT1_t MPR_0BEAT1; /* ALT_MPFE_HMC_ADP_MPR_0BEAT1 */
24699  volatile ALT_MPFE_HMC_ADP_MPR_1BEAT1_t MPR_1BEAT1; /* ALT_MPFE_HMC_ADP_MPR_1BEAT1 */
24700  volatile ALT_MPFE_HMC_ADP_MPR_2BEAT1_t MPR_2BEAT1; /* ALT_MPFE_HMC_ADP_MPR_2BEAT1 */
24701  volatile ALT_MPFE_HMC_ADP_MPR_3BEAT1_t MPR_3BEAT1; /* ALT_MPFE_HMC_ADP_MPR_3BEAT1 */
24702  volatile ALT_MPFE_HMC_ADP_MPR_4BEAT1_t MPR_4BEAT1; /* ALT_MPFE_HMC_ADP_MPR_4BEAT1 */
24703  volatile ALT_MPFE_HMC_ADP_MPR_5BEAT1_t MPR_5BEAT1; /* ALT_MPFE_HMC_ADP_MPR_5BEAT1 */
24704  volatile ALT_MPFE_HMC_ADP_MPR_6BEAT1_t MPR_6BEAT1; /* ALT_MPFE_HMC_ADP_MPR_6BEAT1 */
24705  volatile ALT_MPFE_HMC_ADP_MPR_7BEAT1_t MPR_7BEAT1; /* ALT_MPFE_HMC_ADP_MPR_7BEAT1 */
24706  volatile ALT_MPFE_HMC_ADP_MPR_8BEAT1_t MPR_8BEAT1; /* ALT_MPFE_HMC_ADP_MPR_8BEAT1 */
24707  volatile ALT_MPFE_HMC_ADP_MPR_0BEAT2_t MPR_0BEAT2; /* ALT_MPFE_HMC_ADP_MPR_0BEAT2 */
24708  volatile ALT_MPFE_HMC_ADP_MPR_1BEAT2_t MPR_1BEAT2; /* ALT_MPFE_HMC_ADP_MPR_1BEAT2 */
24709  volatile ALT_MPFE_HMC_ADP_MPR_2BEAT2_t MPR_2BEAT2; /* ALT_MPFE_HMC_ADP_MPR_2BEAT2 */
24710  volatile ALT_MPFE_HMC_ADP_MPR_3BEAT2_t MPR_3BEAT2; /* ALT_MPFE_HMC_ADP_MPR_3BEAT2 */
24711  volatile ALT_MPFE_HMC_ADP_MPR_4BEAT2_t MPR_4BEAT2; /* ALT_MPFE_HMC_ADP_MPR_4BEAT2 */
24712  volatile ALT_MPFE_HMC_ADP_MPR_5BEAT2_t MPR_5BEAT2; /* ALT_MPFE_HMC_ADP_MPR_5BEAT2 */
24713  volatile ALT_MPFE_HMC_ADP_MPR_6BEAT2_t MPR_6BEAT2; /* ALT_MPFE_HMC_ADP_MPR_6BEAT2 */
24714  volatile ALT_MPFE_HMC_ADP_MPR_7BEAT2_t MPR_7BEAT2; /* ALT_MPFE_HMC_ADP_MPR_7BEAT2 */
24715  volatile ALT_MPFE_HMC_ADP_MPR_8BEAT2_t MPR_8BEAT2; /* ALT_MPFE_HMC_ADP_MPR_8BEAT2 */
24716  volatile uint32_t _pad_0x58_0x5f[2]; /* *UNDEFINED* */
24717  volatile ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_t AUTO_PRECHARGE; /* ALT_MPFE_HMC_ADP_AUTO_PRECHARGE */
24718  volatile uint32_t _pad_0x64_0xdf[31]; /* *UNDEFINED* */
24719  volatile ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_t DRAMADDRWIDTH; /* ALT_MPFE_HMC_ADP_DRAMADDRWIDTH */
24720  volatile uint32_t _pad_0xe4_0xff[7]; /* *UNDEFINED* */
24721  volatile ALT_MPFE_HMC_ADP_ECCCTRL1_t ECCCTRL1; /* ALT_MPFE_HMC_ADP_ECCCTRL1 */
24722  volatile ALT_MPFE_HMC_ADP_ECCCTRL2_t ECCCTRL2; /* ALT_MPFE_HMC_ADP_ECCCTRL2 */
24723  volatile uint32_t _pad_0x108_0x10f[2]; /* *UNDEFINED* */
24724  volatile ALT_MPFE_HMC_ADP_ERRINTEN_t ERRINTEN; /* ALT_MPFE_HMC_ADP_ERRINTEN */
24725  volatile ALT_MPFE_HMC_ADP_ERRINTENS_t ERRINTENS; /* ALT_MPFE_HMC_ADP_ERRINTENS */
24726  volatile ALT_MPFE_HMC_ADP_ERRINTENR_t ERRINTENR; /* ALT_MPFE_HMC_ADP_ERRINTENR */
24727  volatile ALT_MPFE_HMC_ADP_INTMODE_t INTMODE; /* ALT_MPFE_HMC_ADP_INTMODE */
24728  volatile ALT_MPFE_HMC_ADP_INTSTAT_t INTSTAT; /* ALT_MPFE_HMC_ADP_INTSTAT */
24729  volatile ALT_MPFE_HMC_ADP_DIAGINTTEST_t DIAGINTTEST; /* ALT_MPFE_HMC_ADP_DIAGINTTEST */
24730  volatile ALT_MPFE_HMC_ADP_MODSTAT_t MODSTAT; /* ALT_MPFE_HMC_ADP_MODSTAT */
24731  volatile ALT_MPFE_HMC_ADP_DERRADDRA_t DERRADDRA; /* ALT_MPFE_HMC_ADP_DERRADDRA */
24732  volatile ALT_MPFE_HMC_ADP_SERRADDRA_t SERRADDRA; /* ALT_MPFE_HMC_ADP_SERRADDRA */
24733  volatile uint32_t _pad_0x134_0x137; /* *UNDEFINED* */
24734  volatile ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_t AUTOWB_CORRADDR; /* ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR */
24735  volatile ALT_MPFE_HMC_ADP_SERRCNTREG_t SERRCNTREG; /* ALT_MPFE_HMC_ADP_SERRCNTREG */
24736  volatile ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_t AUTOWB_DROP_CNTREG; /* ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG */
24737  volatile ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_t ECC_REG2WRECCDATABUS; /* ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS */
24738  volatile ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_t ECC_RDECCDATA2REGBUS; /* ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS */
24739  volatile ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_t ECC_REG2RDECCDATABUS; /* ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS */
24740  volatile ALT_MPFE_HMC_ADP_ECC_DIAGON_t ECC_DIAGON; /* ALT_MPFE_HMC_ADP_ECC_DIAGON */
24741  volatile ALT_MPFE_HMC_ADP_ECC_DECSTAT_t ECC_DECSTAT; /* ALT_MPFE_HMC_ADP_ECC_DECSTAT */
24742  volatile uint32_t _pad_0x158_0x15f[2]; /* *UNDEFINED* */
24743  volatile ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_t ECC_ERRGENADDR_0; /* ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0 */
24744  volatile ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_t ECC_ERRGENADDR_1; /* ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1 */
24745  volatile ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_t ECC_ERRGENADDR_2; /* ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2 */
24746  volatile ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_t ECC_ERRGENADDR_3; /* ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3 */
24747  volatile ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_t ECC_REG2RDDATABUS_BEAT0; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0 */
24748  volatile ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_t ECC_REG2RDDATABUS_BEAT1; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1 */
24749  volatile ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_t ECC_REG2RDDATABUS_BEAT2; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2 */
24750  volatile ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_t ECC_REG2RDDATABUS_BEAT3; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3 */
24751  volatile ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_t ECC_ERRGENHADDR_0; /* ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0 */
24752  volatile ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_t ECC_ERRGENHADDR_1; /* ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1 */
24753  volatile ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_t ECC_ERRGENHADDR_2; /* ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2 */
24754  volatile ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_t ECC_ERRGENHADDR_3; /* ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3 */
24755  volatile uint32_t _pad_0x190_0x1af[8]; /* *UNDEFINED* */
24756  volatile ALT_MPFE_HMC_ADP_DERRHADDR_t DERRHADDR; /* ALT_MPFE_HMC_ADP_DERRHADDR */
24757  volatile ALT_MPFE_HMC_ADP_SERRHADDR_t SERRHADDR; /* ALT_MPFE_HMC_ADP_SERRHADDR */
24758  volatile uint32_t _pad_0x1b8_0x1bb; /* *UNDEFINED* */
24759  volatile ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_t AUTOWB_CORRHADDR; /* ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR */
24760  volatile uint32_t _pad_0x1c0_0x20f[20]; /* *UNDEFINED* */
24761  volatile ALT_MPFE_HMC_ADP_HPSINTFCSEL_t HPSINTFCSEL; /* ALT_MPFE_HMC_ADP_HPSINTFCSEL */
24762  volatile ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_t RSTHANDSHAKECTRL; /* ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL */
24763  volatile ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_t RSTHANDSHAKESTAT; /* ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT */
24764  volatile uint32_t _pad_0x21c_0x500[185]; /* *UNDEFINED* */
24765 };
24766 
24767 /* The typedef declaration for register group ALT_MPFE_HMC_ADP. */
24768 typedef struct ALT_MPFE_HMC_ADP_s ALT_MPFE_HMC_ADP_t;
24769 /* The struct declaration for the raw register contents of register group ALT_MPFE_HMC_ADP. */
24770 struct ALT_MPFE_HMC_ADP_raw_s
24771 {
24772  volatile uint32_t IP_REV_ID; /* ALT_MPFE_HMC_ADP_IP_REV_ID */
24773  volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */
24774  volatile uint32_t DDRIOCTRL; /* ALT_MPFE_HMC_ADP_DDRIOCTRL */
24775  volatile uint32_t DDRCALSTAT; /* ALT_MPFE_HMC_ADP_DDRCALSTAT */
24776  volatile uint32_t MPR_0BEAT1; /* ALT_MPFE_HMC_ADP_MPR_0BEAT1 */
24777  volatile uint32_t MPR_1BEAT1; /* ALT_MPFE_HMC_ADP_MPR_1BEAT1 */
24778  volatile uint32_t MPR_2BEAT1; /* ALT_MPFE_HMC_ADP_MPR_2BEAT1 */
24779  volatile uint32_t MPR_3BEAT1; /* ALT_MPFE_HMC_ADP_MPR_3BEAT1 */
24780  volatile uint32_t MPR_4BEAT1; /* ALT_MPFE_HMC_ADP_MPR_4BEAT1 */
24781  volatile uint32_t MPR_5BEAT1; /* ALT_MPFE_HMC_ADP_MPR_5BEAT1 */
24782  volatile uint32_t MPR_6BEAT1; /* ALT_MPFE_HMC_ADP_MPR_6BEAT1 */
24783  volatile uint32_t MPR_7BEAT1; /* ALT_MPFE_HMC_ADP_MPR_7BEAT1 */
24784  volatile uint32_t MPR_8BEAT1; /* ALT_MPFE_HMC_ADP_MPR_8BEAT1 */
24785  volatile uint32_t MPR_0BEAT2; /* ALT_MPFE_HMC_ADP_MPR_0BEAT2 */
24786  volatile uint32_t MPR_1BEAT2; /* ALT_MPFE_HMC_ADP_MPR_1BEAT2 */
24787  volatile uint32_t MPR_2BEAT2; /* ALT_MPFE_HMC_ADP_MPR_2BEAT2 */
24788  volatile uint32_t MPR_3BEAT2; /* ALT_MPFE_HMC_ADP_MPR_3BEAT2 */
24789  volatile uint32_t MPR_4BEAT2; /* ALT_MPFE_HMC_ADP_MPR_4BEAT2 */
24790  volatile uint32_t MPR_5BEAT2; /* ALT_MPFE_HMC_ADP_MPR_5BEAT2 */
24791  volatile uint32_t MPR_6BEAT2; /* ALT_MPFE_HMC_ADP_MPR_6BEAT2 */
24792  volatile uint32_t MPR_7BEAT2; /* ALT_MPFE_HMC_ADP_MPR_7BEAT2 */
24793  volatile uint32_t MPR_8BEAT2; /* ALT_MPFE_HMC_ADP_MPR_8BEAT2 */
24794  volatile uint32_t _pad_0x58_0x5f[2]; /* *UNDEFINED* */
24795  volatile uint32_t AUTO_PRECHARGE; /* ALT_MPFE_HMC_ADP_AUTO_PRECHARGE */
24796  volatile uint32_t _pad_0x64_0xdf[31]; /* *UNDEFINED* */
24797  volatile uint32_t DRAMADDRWIDTH; /* ALT_MPFE_HMC_ADP_DRAMADDRWIDTH */
24798  volatile uint32_t _pad_0xe4_0xff[7]; /* *UNDEFINED* */
24799  volatile uint32_t ECCCTRL1; /* ALT_MPFE_HMC_ADP_ECCCTRL1 */
24800  volatile uint32_t ECCCTRL2; /* ALT_MPFE_HMC_ADP_ECCCTRL2 */
24801  volatile uint32_t _pad_0x108_0x10f[2]; /* *UNDEFINED* */
24802  volatile uint32_t ERRINTEN; /* ALT_MPFE_HMC_ADP_ERRINTEN */
24803  volatile uint32_t ERRINTENS; /* ALT_MPFE_HMC_ADP_ERRINTENS */
24804  volatile uint32_t ERRINTENR; /* ALT_MPFE_HMC_ADP_ERRINTENR */
24805  volatile uint32_t INTMODE; /* ALT_MPFE_HMC_ADP_INTMODE */
24806  volatile uint32_t INTSTAT; /* ALT_MPFE_HMC_ADP_INTSTAT */
24807  volatile uint32_t DIAGINTTEST; /* ALT_MPFE_HMC_ADP_DIAGINTTEST */
24808  volatile uint32_t MODSTAT; /* ALT_MPFE_HMC_ADP_MODSTAT */
24809  volatile uint32_t DERRADDRA; /* ALT_MPFE_HMC_ADP_DERRADDRA */
24810  volatile uint32_t SERRADDRA; /* ALT_MPFE_HMC_ADP_SERRADDRA */
24811  volatile uint32_t _pad_0x134_0x137; /* *UNDEFINED* */
24812  volatile uint32_t AUTOWB_CORRADDR; /* ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR */
24813  volatile uint32_t SERRCNTREG; /* ALT_MPFE_HMC_ADP_SERRCNTREG */
24814  volatile uint32_t AUTOWB_DROP_CNTREG; /* ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG */
24815  volatile uint32_t ECC_REG2WRECCDATABUS; /* ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS */
24816  volatile uint32_t ECC_RDECCDATA2REGBUS; /* ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS */
24817  volatile uint32_t ECC_REG2RDECCDATABUS; /* ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS */
24818  volatile uint32_t ECC_DIAGON; /* ALT_MPFE_HMC_ADP_ECC_DIAGON */
24819  volatile uint32_t ECC_DECSTAT; /* ALT_MPFE_HMC_ADP_ECC_DECSTAT */
24820  volatile uint32_t _pad_0x158_0x15f[2]; /* *UNDEFINED* */
24821  volatile uint32_t ECC_ERRGENADDR_0; /* ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0 */
24822  volatile uint32_t ECC_ERRGENADDR_1; /* ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1 */
24823  volatile uint32_t ECC_ERRGENADDR_2; /* ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2 */
24824  volatile uint32_t ECC_ERRGENADDR_3; /* ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3 */
24825  volatile uint32_t ECC_REG2RDDATABUS_BEAT0; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0 */
24826  volatile uint32_t ECC_REG2RDDATABUS_BEAT1; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1 */
24827  volatile uint32_t ECC_REG2RDDATABUS_BEAT2; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2 */
24828  volatile uint32_t ECC_REG2RDDATABUS_BEAT3; /* ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3 */
24829  volatile uint32_t ECC_ERRGENHADDR_0; /* ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0 */
24830  volatile uint32_t ECC_ERRGENHADDR_1; /* ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1 */
24831  volatile uint32_t ECC_ERRGENHADDR_2; /* ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2 */
24832  volatile uint32_t ECC_ERRGENHADDR_3; /* ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3 */
24833  volatile uint32_t _pad_0x190_0x1af[8]; /* *UNDEFINED* */
24834  volatile uint32_t DERRHADDR; /* ALT_MPFE_HMC_ADP_DERRHADDR */
24835  volatile uint32_t SERRHADDR; /* ALT_MPFE_HMC_ADP_SERRHADDR */
24836  volatile uint32_t _pad_0x1b8_0x1bb; /* *UNDEFINED* */
24837  volatile uint32_t AUTOWB_CORRHADDR; /* ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR */
24838  volatile uint32_t _pad_0x1c0_0x20f[20]; /* *UNDEFINED* */
24839  volatile uint32_t HPSINTFCSEL; /* ALT_MPFE_HMC_ADP_HPSINTFCSEL */
24840  volatile uint32_t RSTHANDSHAKECTRL; /* ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL */
24841  volatile uint32_t RSTHANDSHAKESTAT; /* ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT */
24842  volatile uint32_t _pad_0x21c_0x500[185]; /* *UNDEFINED* */
24843 };
24844 
24845 /* The typedef declaration for the raw register contents of register group ALT_MPFE_HMC_ADP. */
24846 typedef struct ALT_MPFE_HMC_ADP_raw_s ALT_MPFE_HMC_ADP_raw_t;
24847 #endif /* __ASSEMBLY__ */
24848 
24849 
24850 /*
24851  * Component : MPFE_CS_OBS_AT_MAIN_ATBENDPT
24852  *
24853  */
24854 /*
24855  * Register : cs_obs_at_main_AtbEndPoint_Id_CoreId
24856  *
24857  * Register Layout
24858  *
24859  * Bits | Access | Reset | Description
24860  * :-------|:-------|:---------|:-----------------------------------------------------------------------------------
24861  * [7:0] | R | 0x7 | ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID
24862  * [31:8] | R | 0xca7ca6 | ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM
24863  *
24864  */
24865 /*
24866  * Field : CORETYPEID
24867  *
24868  * Field identifying the type of IP.
24869  *
24870  * Field Access Macros:
24871  *
24872  */
24873 /* The Least Significant Bit (LSB) position of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID register field. */
24874 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID_LSB 0
24875 /* The Most Significant Bit (MSB) position of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID register field. */
24876 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID_MSB 7
24877 /* The width in bits of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID register field. */
24878 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID_WIDTH 8
24879 /* The mask used to set the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID register field value. */
24880 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
24881 /* The mask used to clear the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID register field value. */
24882 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
24883 /* The reset value of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID register field. */
24884 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID_RESET 0x7
24885 /* Extracts the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID field value from a register. */
24886 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
24887 /* Produces a ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID register field value suitable for setting the register. */
24888 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
24889 
24890 /*
24891  * Field : CORECHECKSUM
24892  *
24893  * Field containing a checksum of the parameters of the IP.
24894  *
24895  * Field Access Macros:
24896  *
24897  */
24898 /* The Least Significant Bit (LSB) position of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM register field. */
24899 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM_LSB 8
24900 /* The Most Significant Bit (MSB) position of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM register field. */
24901 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM_MSB 31
24902 /* The width in bits of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM register field. */
24903 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM_WIDTH 24
24904 /* The mask used to set the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM register field value. */
24905 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
24906 /* The mask used to clear the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM register field value. */
24907 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
24908 /* The reset value of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM register field. */
24909 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM_RESET 0xca7ca6
24910 /* Extracts the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM field value from a register. */
24911 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
24912 /* Produces a ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM register field value suitable for setting the register. */
24913 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
24914 
24915 #ifndef __ASSEMBLY__
24916 /*
24917  * WARNING: The C register and register group struct declarations are provided for
24918  * convenience and illustrative purposes. They should, however, be used with
24919  * caution as the C language standard provides no guarantees about the alignment or
24920  * atomicity of device memory accesses. The recommended practice for coding device
24921  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
24922  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
24923  * alt_write_dword() functions for 64 bit registers.
24924  *
24925  * The struct declaration for register ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID.
24926  */
24927 struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_s
24928 {
24929  const volatile uint32_t CORETYPEID : 8; /* ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID */
24930  const volatile uint32_t CORECHECKSUM : 24; /* ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM */
24931 };
24932 
24933 /* The typedef declaration for register ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID. */
24934 typedef struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_s ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_t;
24935 #endif /* __ASSEMBLY__ */
24936 
24937 /* The reset value of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID register. */
24938 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_RESET 0xca7ca607
24939 /* The byte offset of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID register from the beginning of the component. */
24940 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_OFST 0x0
24941 
24942 /*
24943  * Register : cs_obs_at_main_AtbEndPoint_Id_RevisionId
24944  *
24945  * Register Layout
24946  *
24947  * Bits | Access | Reset | Description
24948  * :-------|:-------|:------|:------------------------------------------------------------------------------------
24949  * [7:0] | R | 0x0 | ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID
24950  * [31:8] | R | 0x148 | ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID
24951  *
24952  */
24953 /*
24954  * Field : USERID
24955  *
24956  * Field containing a user defined value, not used anywhere inside the IP itself.
24957  *
24958  * Field Access Macros:
24959  *
24960  */
24961 /* The Least Significant Bit (LSB) position of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID register field. */
24962 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID_LSB 0
24963 /* The Most Significant Bit (MSB) position of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID register field. */
24964 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID_MSB 7
24965 /* The width in bits of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID register field. */
24966 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID_WIDTH 8
24967 /* The mask used to set the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID register field value. */
24968 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID_SET_MSK 0x000000ff
24969 /* The mask used to clear the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID register field value. */
24970 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
24971 /* The reset value of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID register field. */
24972 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID_RESET 0x0
24973 /* Extracts the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID field value from a register. */
24974 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
24975 /* Produces a ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID register field value suitable for setting the register. */
24976 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
24977 
24978 /*
24979  * Field : FLEXNOCID
24980  *
24981  * Field containing the build revision of the software used to generate the IP HDL
24982  * code.
24983  *
24984  * Field Access Macros:
24985  *
24986  */
24987 /* The Least Significant Bit (LSB) position of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID register field. */
24988 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID_LSB 8
24989 /* The Most Significant Bit (MSB) position of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID register field. */
24990 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID_MSB 31
24991 /* The width in bits of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID register field. */
24992 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID_WIDTH 24
24993 /* The mask used to set the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID register field value. */
24994 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
24995 /* The mask used to clear the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID register field value. */
24996 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
24997 /* The reset value of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID register field. */
24998 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID_RESET 0x148
24999 /* Extracts the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID field value from a register. */
25000 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
25001 /* Produces a ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID register field value suitable for setting the register. */
25002 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
25003 
25004 #ifndef __ASSEMBLY__
25005 /*
25006  * WARNING: The C register and register group struct declarations are provided for
25007  * convenience and illustrative purposes. They should, however, be used with
25008  * caution as the C language standard provides no guarantees about the alignment or
25009  * atomicity of device memory accesses. The recommended practice for coding device
25010  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25011  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25012  * alt_write_dword() functions for 64 bit registers.
25013  *
25014  * The struct declaration for register ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID.
25015  */
25016 struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_s
25017 {
25018  const volatile uint32_t USERID : 8; /* ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID */
25019  const volatile uint32_t FLEXNOCID : 24; /* ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID */
25020 };
25021 
25022 /* The typedef declaration for register ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID. */
25023 typedef struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_s ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_t;
25024 #endif /* __ASSEMBLY__ */
25025 
25026 /* The reset value of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID register. */
25027 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_RESET 0x00014800
25028 /* The byte offset of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID register from the beginning of the component. */
25029 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_OFST 0x4
25030 
25031 /*
25032  * Register : cs_obs_at_main_AtbEndPoint_AtbId
25033  *
25034  * Register Layout
25035  *
25036  * Bits | Access | Reset | Description
25037  * :-------|:-------|:--------|:------------------------------------------------------------------------
25038  * [6:0] | RW | 0x0 | ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID
25039  * [31:7] | ??? | Unknown | *UNDEFINED*
25040  *
25041  */
25042 /*
25043  * Field : ATBID
25044  *
25045  * ATB AtId
25046  *
25047  * Field Access Macros:
25048  *
25049  */
25050 /* The Least Significant Bit (LSB) position of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID register field. */
25051 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID_LSB 0
25052 /* The Most Significant Bit (MSB) position of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID register field. */
25053 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID_MSB 6
25054 /* The width in bits of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID register field. */
25055 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID_WIDTH 7
25056 /* The mask used to set the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID register field value. */
25057 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID_SET_MSK 0x0000007f
25058 /* The mask used to clear the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID register field value. */
25059 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID_CLR_MSK 0xffffff80
25060 /* The reset value of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID register field. */
25061 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID_RESET 0x0
25062 /* Extracts the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID field value from a register. */
25063 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID_GET(value) (((value) & 0x0000007f) >> 0)
25064 /* Produces a ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID register field value suitable for setting the register. */
25065 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID_SET(value) (((value) << 0) & 0x0000007f)
25066 
25067 #ifndef __ASSEMBLY__
25068 /*
25069  * WARNING: The C register and register group struct declarations are provided for
25070  * convenience and illustrative purposes. They should, however, be used with
25071  * caution as the C language standard provides no guarantees about the alignment or
25072  * atomicity of device memory accesses. The recommended practice for coding device
25073  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25074  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25075  * alt_write_dword() functions for 64 bit registers.
25076  *
25077  * The struct declaration for register ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID.
25078  */
25079 struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_s
25080 {
25081  volatile uint32_t ATBID : 7; /* ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID */
25082  uint32_t : 25; /* *UNDEFINED* */
25083 };
25084 
25085 /* The typedef declaration for register ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID. */
25086 typedef struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_s ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_t;
25087 #endif /* __ASSEMBLY__ */
25088 
25089 /* The reset value of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID register. */
25090 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_RESET 0x00000000
25091 /* The byte offset of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID register from the beginning of the component. */
25092 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_OFST 0x8
25093 
25094 /*
25095  * Register : cs_obs_at_main_AtbEndPoint_AtbEn
25096  *
25097  * Register Layout
25098  *
25099  * Bits | Access | Reset | Description
25100  * :-------|:-------|:--------|:------------------------------------------------------------------------
25101  * [0] | RW | 0x0 | ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN
25102  * [31:1] | ??? | Unknown | *UNDEFINED*
25103  *
25104  */
25105 /*
25106  * Field : ATBEN
25107  *
25108  * ATB Unit Enable
25109  *
25110  * Field Access Macros:
25111  *
25112  */
25113 /* The Least Significant Bit (LSB) position of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN register field. */
25114 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN_LSB 0
25115 /* The Most Significant Bit (MSB) position of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN register field. */
25116 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN_MSB 0
25117 /* The width in bits of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN register field. */
25118 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN_WIDTH 1
25119 /* The mask used to set the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN register field value. */
25120 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN_SET_MSK 0x00000001
25121 /* The mask used to clear the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN register field value. */
25122 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN_CLR_MSK 0xfffffffe
25123 /* The reset value of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN register field. */
25124 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN_RESET 0x0
25125 /* Extracts the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN field value from a register. */
25126 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN_GET(value) (((value) & 0x00000001) >> 0)
25127 /* Produces a ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN register field value suitable for setting the register. */
25128 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN_SET(value) (((value) << 0) & 0x00000001)
25129 
25130 #ifndef __ASSEMBLY__
25131 /*
25132  * WARNING: The C register and register group struct declarations are provided for
25133  * convenience and illustrative purposes. They should, however, be used with
25134  * caution as the C language standard provides no guarantees about the alignment or
25135  * atomicity of device memory accesses. The recommended practice for coding device
25136  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25137  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25138  * alt_write_dword() functions for 64 bit registers.
25139  *
25140  * The struct declaration for register ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN.
25141  */
25142 struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_s
25143 {
25144  volatile uint32_t ATBEN : 1; /* ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN */
25145  uint32_t : 31; /* *UNDEFINED* */
25146 };
25147 
25148 /* The typedef declaration for register ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN. */
25149 typedef struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_s ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_t;
25150 #endif /* __ASSEMBLY__ */
25151 
25152 /* The reset value of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN register. */
25153 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_RESET 0x00000000
25154 /* The byte offset of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN register from the beginning of the component. */
25155 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_OFST 0xc
25156 
25157 /*
25158  * Register : cs_obs_at_main_AtbEndPoint_SyncPeriod
25159  *
25160  * Register Layout
25161  *
25162  * Bits | Access | Reset | Description
25163  * :-------|:-------|:--------|:----------------------------------------------------------------------------------
25164  * [4:0] | RW | 0x0 | ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD
25165  * [31:5] | ??? | Unknown | *UNDEFINED*
25166  *
25167  */
25168 /*
25169  * Field : SYNCPERIOD
25170  *
25171  * ATB Synchro Period
25172  *
25173  * Field Access Macros:
25174  *
25175  */
25176 /* The Least Significant Bit (LSB) position of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD register field. */
25177 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD_LSB 0
25178 /* The Most Significant Bit (MSB) position of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD register field. */
25179 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD_MSB 4
25180 /* The width in bits of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD register field. */
25181 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD_WIDTH 5
25182 /* The mask used to set the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD register field value. */
25183 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD_SET_MSK 0x0000001f
25184 /* The mask used to clear the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD register field value. */
25185 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD_CLR_MSK 0xffffffe0
25186 /* The reset value of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD register field. */
25187 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD_RESET 0x0
25188 /* Extracts the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD field value from a register. */
25189 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD_GET(value) (((value) & 0x0000001f) >> 0)
25190 /* Produces a ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD register field value suitable for setting the register. */
25191 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD_SET(value) (((value) << 0) & 0x0000001f)
25192 
25193 #ifndef __ASSEMBLY__
25194 /*
25195  * WARNING: The C register and register group struct declarations are provided for
25196  * convenience and illustrative purposes. They should, however, be used with
25197  * caution as the C language standard provides no guarantees about the alignment or
25198  * atomicity of device memory accesses. The recommended practice for coding device
25199  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25200  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25201  * alt_write_dword() functions for 64 bit registers.
25202  *
25203  * The struct declaration for register ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD.
25204  */
25205 struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_s
25206 {
25207  volatile uint32_t SYNCPERIOD : 5; /* ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD */
25208  uint32_t : 27; /* *UNDEFINED* */
25209 };
25210 
25211 /* The typedef declaration for register ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD. */
25212 typedef struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_s ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_t;
25213 #endif /* __ASSEMBLY__ */
25214 
25215 /* The reset value of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD register. */
25216 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_RESET 0x00000000
25217 /* The byte offset of the ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD register from the beginning of the component. */
25218 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_OFST 0x10
25219 
25220 #ifndef __ASSEMBLY__
25221 /*
25222  * WARNING: The C register and register group struct declarations are provided for
25223  * convenience and illustrative purposes. They should, however, be used with
25224  * caution as the C language standard provides no guarantees about the alignment or
25225  * atomicity of device memory accesses. The recommended practice for coding device
25226  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25227  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25228  * alt_write_dword() functions for 64 bit registers.
25229  *
25230  * The struct declaration for register group ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT.
25231  */
25232 struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_s
25233 {
25234  volatile ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_t cs_obs_at_main_AtbEndPoint_Id_CoreId; /* ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID */
25235  volatile ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_t cs_obs_at_main_AtbEndPoint_Id_RevisionId; /* ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID */
25236  volatile ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_t cs_obs_at_main_AtbEndPoint_AtbId; /* ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID */
25237  volatile ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_t cs_obs_at_main_AtbEndPoint_AtbEn; /* ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN */
25238  volatile ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_t cs_obs_at_main_AtbEndPoint_SyncPeriod; /* ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD */
25239  volatile uint32_t _pad_0x14_0x80[27]; /* *UNDEFINED* */
25240 };
25241 
25242 /* The typedef declaration for register group ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT. */
25243 typedef struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_s ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_t;
25244 /* The struct declaration for the raw register contents of register group ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT. */
25245 struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_raw_s
25246 {
25247  volatile uint32_t cs_obs_at_main_AtbEndPoint_Id_CoreId; /* ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID */
25248  volatile uint32_t cs_obs_at_main_AtbEndPoint_Id_RevisionId; /* ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID */
25249  volatile uint32_t cs_obs_at_main_AtbEndPoint_AtbId; /* ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID */
25250  volatile uint32_t cs_obs_at_main_AtbEndPoint_AtbEn; /* ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN */
25251  volatile uint32_t cs_obs_at_main_AtbEndPoint_SyncPeriod; /* ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD */
25252  volatile uint32_t _pad_0x14_0x80[27]; /* *UNDEFINED* */
25253 };
25254 
25255 /* The typedef declaration for the raw register contents of register group ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT. */
25256 typedef struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_raw_s ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_raw_t;
25257 #endif /* __ASSEMBLY__ */
25258 
25259 
25260 /*
25261  * Component : MPFE_CCU_MEM0_QOS
25262  *
25263  */
25264 /*
25265  * Register : ccu_mem0_I_main_QosGenerator_Id_CoreId
25266  *
25267  * Register Layout
25268  *
25269  * Bits | Access | Reset | Description
25270  * :-------|:-------|:---------|:--------------------------------------------------------------------------
25271  * [7:0] | R | 0x4 | ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID
25272  * [31:8] | R | 0x89b4d7 | ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM
25273  *
25274  */
25275 /*
25276  * Field : CORETYPEID
25277  *
25278  * Field identifying the type of IP.
25279  *
25280  * Field Access Macros:
25281  *
25282  */
25283 /* The Least Significant Bit (LSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
25284 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_LSB 0
25285 /* The Most Significant Bit (MSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
25286 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_MSB 7
25287 /* The width in bits of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
25288 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_WIDTH 8
25289 /* The mask used to set the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value. */
25290 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
25291 /* The mask used to clear the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value. */
25292 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
25293 /* The reset value of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
25294 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_RESET 0x4
25295 /* Extracts the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID field value from a register. */
25296 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
25297 /* Produces a ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value suitable for setting the register. */
25298 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
25299 
25300 /*
25301  * Field : CORECHECKSUM
25302  *
25303  * Field containing a checksum of the parameters of the IP.
25304  *
25305  * Field Access Macros:
25306  *
25307  */
25308 /* The Least Significant Bit (LSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
25309 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_LSB 8
25310 /* The Most Significant Bit (MSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
25311 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_MSB 31
25312 /* The width in bits of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
25313 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_WIDTH 24
25314 /* The mask used to set the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value. */
25315 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
25316 /* The mask used to clear the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value. */
25317 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
25318 /* The reset value of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
25319 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_RESET 0x89b4d7
25320 /* Extracts the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM field value from a register. */
25321 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
25322 /* Produces a ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value suitable for setting the register. */
25323 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
25324 
25325 #ifndef __ASSEMBLY__
25326 /*
25327  * WARNING: The C register and register group struct declarations are provided for
25328  * convenience and illustrative purposes. They should, however, be used with
25329  * caution as the C language standard provides no guarantees about the alignment or
25330  * atomicity of device memory accesses. The recommended practice for coding device
25331  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25332  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25333  * alt_write_dword() functions for 64 bit registers.
25334  *
25335  * The struct declaration for register ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID.
25336  */
25337 struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_s
25338 {
25339  const volatile uint32_t CORETYPEID : 8; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID */
25340  const volatile uint32_t CORECHECKSUM : 24; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM */
25341 };
25342 
25343 /* The typedef declaration for register ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID. */
25344 typedef struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_s ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_t;
25345 #endif /* __ASSEMBLY__ */
25346 
25347 /* The reset value of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID register. */
25348 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_RESET 0x89b4d704
25349 /* The byte offset of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID register from the beginning of the component. */
25350 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_OFST 0x0
25351 
25352 /*
25353  * Register : ccu_mem0_I_main_QosGenerator_Id_RevisionId
25354  *
25355  * Register Layout
25356  *
25357  * Bits | Access | Reset | Description
25358  * :-------|:-------|:------|:---------------------------------------------------------------------------
25359  * [7:0] | R | 0x0 | ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID
25360  * [31:8] | R | 0x148 | ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID
25361  *
25362  */
25363 /*
25364  * Field : USERID
25365  *
25366  * Field containing a user defined value, not used anywhere inside the IP itself.
25367  *
25368  * Field Access Macros:
25369  *
25370  */
25371 /* The Least Significant Bit (LSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
25372 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_LSB 0
25373 /* The Most Significant Bit (MSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
25374 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_MSB 7
25375 /* The width in bits of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
25376 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_WIDTH 8
25377 /* The mask used to set the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value. */
25378 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET_MSK 0x000000ff
25379 /* The mask used to clear the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value. */
25380 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
25381 /* The reset value of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
25382 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_RESET 0x0
25383 /* Extracts the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID field value from a register. */
25384 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
25385 /* Produces a ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value suitable for setting the register. */
25386 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
25387 
25388 /*
25389  * Field : FLEXNOCID
25390  *
25391  * Field containing the build revision of the software used to generate the IP HDL
25392  * code.
25393  *
25394  * Field Access Macros:
25395  *
25396  */
25397 /* The Least Significant Bit (LSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
25398 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_LSB 8
25399 /* The Most Significant Bit (MSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
25400 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_MSB 31
25401 /* The width in bits of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
25402 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_WIDTH 24
25403 /* The mask used to set the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value. */
25404 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
25405 /* The mask used to clear the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value. */
25406 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
25407 /* The reset value of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
25408 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_RESET 0x148
25409 /* Extracts the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID field value from a register. */
25410 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
25411 /* Produces a ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value suitable for setting the register. */
25412 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
25413 
25414 #ifndef __ASSEMBLY__
25415 /*
25416  * WARNING: The C register and register group struct declarations are provided for
25417  * convenience and illustrative purposes. They should, however, be used with
25418  * caution as the C language standard provides no guarantees about the alignment or
25419  * atomicity of device memory accesses. The recommended practice for coding device
25420  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25421  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25422  * alt_write_dword() functions for 64 bit registers.
25423  *
25424  * The struct declaration for register ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID.
25425  */
25426 struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_s
25427 {
25428  const volatile uint32_t USERID : 8; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID */
25429  const volatile uint32_t FLEXNOCID : 24; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID */
25430 };
25431 
25432 /* The typedef declaration for register ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID. */
25433 typedef struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_s ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_t;
25434 #endif /* __ASSEMBLY__ */
25435 
25436 /* The reset value of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID register. */
25437 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_RESET 0x00014800
25438 /* The byte offset of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID register from the beginning of the component. */
25439 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_OFST 0x4
25440 
25441 /*
25442  * Register : ccu_mem0_I_main_QosGenerator_Priority
25443  *
25444  * Priority register.
25445  *
25446  * Register Layout
25447  *
25448  * Bits | Access | Reset | Description
25449  * :--------|:-------|:--------|:-----------------------------------------------------------------
25450  * [1:0] | RW | 0x0 | ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0
25451  * [7:2] | ??? | Unknown | *UNDEFINED*
25452  * [9:8] | RW | 0x0 | ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1
25453  * [30:10] | ??? | Unknown | *UNDEFINED*
25454  * [31] | R | 0x1 | ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK
25455  *
25456  */
25457 /*
25458  * Field : P0
25459  *
25460  * In Programmable or Bandwidth Limiter mode, the priority level for write
25461  * transactions. In Bandwidth Regulator mode, the priority level when the used
25462  * throughput is above the threshold. In Bandwidth Regulator mode, P0 should have a
25463  * value equal or lower than P1.
25464  *
25465  * Field Access Macros:
25466  *
25467  */
25468 /* The Least Significant Bit (LSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
25469 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0_LSB 0
25470 /* The Most Significant Bit (MSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
25471 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0_MSB 1
25472 /* The width in bits of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
25473 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0_WIDTH 2
25474 /* The mask used to set the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value. */
25475 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET_MSK 0x00000003
25476 /* The mask used to clear the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value. */
25477 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0_CLR_MSK 0xfffffffc
25478 /* The reset value of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
25479 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0_RESET 0x0
25480 /* Extracts the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0 field value from a register. */
25481 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0_GET(value) (((value) & 0x00000003) >> 0)
25482 /* Produces a ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value suitable for setting the register. */
25483 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET(value) (((value) << 0) & 0x00000003)
25484 
25485 /*
25486  * Field : P1
25487  *
25488  * In Programmable or Bandwidth Limiter mode, the priority level for read
25489  * transactions. In Bandwidth regulator mode, the priority level when the used
25490  * throughput is below the threshold. In Bandwidth Regulator mode, P1 should have a
25491  * value equal or greater than P0.
25492  *
25493  * Field Access Macros:
25494  *
25495  */
25496 /* The Least Significant Bit (LSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
25497 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1_LSB 8
25498 /* The Most Significant Bit (MSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
25499 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1_MSB 9
25500 /* The width in bits of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
25501 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1_WIDTH 2
25502 /* The mask used to set the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value. */
25503 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET_MSK 0x00000300
25504 /* The mask used to clear the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value. */
25505 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1_CLR_MSK 0xfffffcff
25506 /* The reset value of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
25507 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1_RESET 0x0
25508 /* Extracts the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1 field value from a register. */
25509 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1_GET(value) (((value) & 0x00000300) >> 8)
25510 /* Produces a ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value suitable for setting the register. */
25511 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET(value) (((value) << 8) & 0x00000300)
25512 
25513 /*
25514  * Field : MARK
25515  *
25516  * Backward compatibility marker when 0.
25517  *
25518  * Field Access Macros:
25519  *
25520  */
25521 /* The Least Significant Bit (LSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
25522 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK_LSB 31
25523 /* The Most Significant Bit (MSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
25524 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK_MSB 31
25525 /* The width in bits of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
25526 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK_WIDTH 1
25527 /* The mask used to set the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value. */
25528 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET_MSK 0x80000000
25529 /* The mask used to clear the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value. */
25530 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK_CLR_MSK 0x7fffffff
25531 /* The reset value of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
25532 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK_RESET 0x1
25533 /* Extracts the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK field value from a register. */
25534 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK_GET(value) (((value) & 0x80000000) >> 31)
25535 /* Produces a ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value suitable for setting the register. */
25536 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET(value) (((value) << 31) & 0x80000000)
25537 
25538 #ifndef __ASSEMBLY__
25539 /*
25540  * WARNING: The C register and register group struct declarations are provided for
25541  * convenience and illustrative purposes. They should, however, be used with
25542  * caution as the C language standard provides no guarantees about the alignment or
25543  * atomicity of device memory accesses. The recommended practice for coding device
25544  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25545  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25546  * alt_write_dword() functions for 64 bit registers.
25547  *
25548  * The struct declaration for register ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY.
25549  */
25550 struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_s
25551 {
25552  volatile uint32_t P0 : 2; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0 */
25553  uint32_t : 6; /* *UNDEFINED* */
25554  volatile uint32_t P1 : 2; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1 */
25555  uint32_t : 21; /* *UNDEFINED* */
25556  const volatile uint32_t MARK : 1; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK */
25557 };
25558 
25559 /* The typedef declaration for register ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY. */
25560 typedef struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_s ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_t;
25561 #endif /* __ASSEMBLY__ */
25562 
25563 /* The reset value of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY register. */
25564 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_RESET 0x80000000
25565 /* The byte offset of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY register from the beginning of the component. */
25566 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_OFST 0x8
25567 
25568 /*
25569  * Register : ccu_mem0_I_main_QosGenerator_Mode
25570  *
25571  * Register Layout
25572  *
25573  * Bits | Access | Reset | Description
25574  * :-------|:-------|:--------|:-------------------------------------------------------------
25575  * [1:0] | RW | 0x1 | ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE
25576  * [31:2] | ??? | Unknown | *UNDEFINED*
25577  *
25578  */
25579 /*
25580  * Field : MODE
25581  *
25582  * 0 = Programmable mode: a programmed priority is assigned to each read or write,
25583  * 1 = Bandwidth Limiter Mode: a hard limit restricts throughput, 2 = Bypass mode:
25584  * (<See SoC-specific QoS generator documentation>), 3 = Bandwidth Regulator mode:
25585  * priority decreases when throughput exceeds a threshold.
25586  *
25587  * Field Access Macros:
25588  *
25589  */
25590 /* The Least Significant Bit (LSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
25591 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE_LSB 0
25592 /* The Most Significant Bit (MSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
25593 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE_MSB 1
25594 /* The width in bits of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
25595 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE_WIDTH 2
25596 /* The mask used to set the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE register field value. */
25597 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE_SET_MSK 0x00000003
25598 /* The mask used to clear the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE register field value. */
25599 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE_CLR_MSK 0xfffffffc
25600 /* The reset value of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
25601 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE_RESET 0x1
25602 /* Extracts the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE field value from a register. */
25603 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE_GET(value) (((value) & 0x00000003) >> 0)
25604 /* Produces a ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE register field value suitable for setting the register. */
25605 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE_SET(value) (((value) << 0) & 0x00000003)
25606 
25607 #ifndef __ASSEMBLY__
25608 /*
25609  * WARNING: The C register and register group struct declarations are provided for
25610  * convenience and illustrative purposes. They should, however, be used with
25611  * caution as the C language standard provides no guarantees about the alignment or
25612  * atomicity of device memory accesses. The recommended practice for coding device
25613  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25614  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25615  * alt_write_dword() functions for 64 bit registers.
25616  *
25617  * The struct declaration for register ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE.
25618  */
25619 struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_s
25620 {
25621  volatile uint32_t MODE : 2; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE */
25622  uint32_t : 30; /* *UNDEFINED* */
25623 };
25624 
25625 /* The typedef declaration for register ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE. */
25626 typedef struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_s ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_t;
25627 #endif /* __ASSEMBLY__ */
25628 
25629 /* The reset value of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE register. */
25630 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_RESET 0x00000001
25631 /* The byte offset of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE register from the beginning of the component. */
25632 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_OFST 0xc
25633 
25634 /*
25635  * Register : ccu_mem0_I_main_QosGenerator_Bandwidth
25636  *
25637  * Register Layout
25638  *
25639  * Bits | Access | Reset | Description
25640  * :--------|:-------|:--------|:-----------------------------------------------------------------------
25641  * [12:0] | RW | 0xbfe | ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH
25642  * [31:13] | ??? | Unknown | *UNDEFINED*
25643  *
25644  */
25645 /*
25646  * Field : BANDWIDTH
25647  *
25648  * In Bandwidth Limiter or Bandwidth Regulator mode, the bandwidth threshold in
25649  * units of 1/256th bytes per cycle. For example, 80 MBps on a 250 MHz interface is
25650  * value 0x0052.
25651  *
25652  * Field Access Macros:
25653  *
25654  */
25655 /* The Least Significant Bit (LSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
25656 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_LSB 0
25657 /* The Most Significant Bit (MSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
25658 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MSB 12
25659 /* The width in bits of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
25660 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_WIDTH 13
25661 /* The mask used to set the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value. */
25662 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET_MSK 0x00001fff
25663 /* The mask used to clear the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value. */
25664 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_CLR_MSK 0xffffe000
25665 /* The reset value of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
25666 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_RESET 0xbfe
25667 /* Extracts the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH field value from a register. */
25668 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_GET(value) (((value) & 0x00001fff) >> 0)
25669 /* Produces a ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value suitable for setting the register. */
25670 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x00001fff)
25671 
25672 #ifndef __ASSEMBLY__
25673 /*
25674  * WARNING: The C register and register group struct declarations are provided for
25675  * convenience and illustrative purposes. They should, however, be used with
25676  * caution as the C language standard provides no guarantees about the alignment or
25677  * atomicity of device memory accesses. The recommended practice for coding device
25678  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25679  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25680  * alt_write_dword() functions for 64 bit registers.
25681  *
25682  * The struct declaration for register ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH.
25683  */
25684 struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_s
25685 {
25686  volatile uint32_t BANDWIDTH : 13; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH */
25687  uint32_t : 19; /* *UNDEFINED* */
25688 };
25689 
25690 /* The typedef declaration for register ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH. */
25691 typedef struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_s ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_t;
25692 #endif /* __ASSEMBLY__ */
25693 
25694 /* The reset value of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH register. */
25695 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_RESET 0x00000bfe
25696 /* The byte offset of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH register from the beginning of the component. */
25697 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_OFST 0x10
25698 
25699 /*
25700  * Register : ccu_mem0_I_main_QosGenerator_Saturation
25701  *
25702  * Register Layout
25703  *
25704  * Bits | Access | Reset | Description
25705  * :--------|:-------|:--------|:-------------------------------------------------------------------------
25706  * [9:0] | RW | 0x8 | ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION
25707  * [31:10] | ??? | Unknown | *UNDEFINED*
25708  *
25709  */
25710 /*
25711  * Field : SATURATION
25712  *
25713  * In Bandwidth Limiter or Bandwidth Regulator mode, the maximum data count value,
25714  * in units of 16 bytes. This determines the window of time over which bandwidth is
25715  * measured. For example, to measure bandwidth within a 1000 cycle window on a
25716  * 64-bit interface is value 0x1F4.
25717  *
25718  * Field Access Macros:
25719  *
25720  */
25721 /* The Least Significant Bit (LSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
25722 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_LSB 0
25723 /* The Most Significant Bit (MSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
25724 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_MSB 9
25725 /* The width in bits of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
25726 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_WIDTH 10
25727 /* The mask used to set the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value. */
25728 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET_MSK 0x000003ff
25729 /* The mask used to clear the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value. */
25730 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_CLR_MSK 0xfffffc00
25731 /* The reset value of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
25732 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_RESET 0x8
25733 /* Extracts the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION field value from a register. */
25734 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
25735 /* Produces a ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value suitable for setting the register. */
25736 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
25737 
25738 #ifndef __ASSEMBLY__
25739 /*
25740  * WARNING: The C register and register group struct declarations are provided for
25741  * convenience and illustrative purposes. They should, however, be used with
25742  * caution as the C language standard provides no guarantees about the alignment or
25743  * atomicity of device memory accesses. The recommended practice for coding device
25744  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25745  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25746  * alt_write_dword() functions for 64 bit registers.
25747  *
25748  * The struct declaration for register ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION.
25749  */
25750 struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_s
25751 {
25752  volatile uint32_t SATURATION : 10; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION */
25753  uint32_t : 22; /* *UNDEFINED* */
25754 };
25755 
25756 /* The typedef declaration for register ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION. */
25757 typedef struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_s ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_t;
25758 #endif /* __ASSEMBLY__ */
25759 
25760 /* The reset value of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION register. */
25761 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_RESET 0x00000008
25762 /* The byte offset of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION register from the beginning of the component. */
25763 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_OFST 0x14
25764 
25765 /*
25766  * Register : ccu_mem0_I_main_QosGenerator_ExtControl
25767  *
25768  * External inputs control.
25769  *
25770  * Register Layout
25771  *
25772  * Bits | Access | Reset | Description
25773  * :-------|:-------|:--------|:--------------------------------------------------------------------------
25774  * [0] | RW | 0x0 | ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN
25775  * [1] | RW | 0x0 | ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN
25776  * [2] | RW | 0x0 | ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN
25777  * [31:3] | ??? | Unknown | *UNDEFINED*
25778  *
25779  */
25780 /*
25781  * Field : SOCKETQOSEN
25782  *
25783  * n/a
25784  *
25785  * Field Access Macros:
25786  *
25787  */
25788 /* The Least Significant Bit (LSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
25789 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_LSB 0
25790 /* The Most Significant Bit (MSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
25791 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MSB 0
25792 /* The width in bits of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
25793 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_WIDTH 1
25794 /* The mask used to set the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value. */
25795 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET_MSK 0x00000001
25796 /* The mask used to clear the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value. */
25797 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_CLR_MSK 0xfffffffe
25798 /* The reset value of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
25799 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_RESET 0x0
25800 /* Extracts the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN field value from a register. */
25801 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
25802 /* Produces a ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value suitable for setting the register. */
25803 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
25804 
25805 /*
25806  * Field : EXTTHREN
25807  *
25808  * n/a
25809  *
25810  * Field Access Macros:
25811  *
25812  */
25813 /* The Least Significant Bit (LSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
25814 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_LSB 1
25815 /* The Most Significant Bit (MSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
25816 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_MSB 1
25817 /* The width in bits of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
25818 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_WIDTH 1
25819 /* The mask used to set the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value. */
25820 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET_MSK 0x00000002
25821 /* The mask used to clear the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value. */
25822 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_CLR_MSK 0xfffffffd
25823 /* The reset value of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
25824 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_RESET 0x0
25825 /* Extracts the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN field value from a register. */
25826 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
25827 /* Produces a ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value suitable for setting the register. */
25828 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
25829 
25830 /*
25831  * Field : INTCLKEN
25832  *
25833  * n/a
25834  *
25835  * Field Access Macros:
25836  *
25837  */
25838 /* The Least Significant Bit (LSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
25839 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_LSB 2
25840 /* The Most Significant Bit (MSB) position of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
25841 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_MSB 2
25842 /* The width in bits of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
25843 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_WIDTH 1
25844 /* The mask used to set the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value. */
25845 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET_MSK 0x00000004
25846 /* The mask used to clear the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value. */
25847 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_CLR_MSK 0xfffffffb
25848 /* The reset value of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
25849 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_RESET 0x0
25850 /* Extracts the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN field value from a register. */
25851 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
25852 /* Produces a ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value suitable for setting the register. */
25853 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
25854 
25855 #ifndef __ASSEMBLY__
25856 /*
25857  * WARNING: The C register and register group struct declarations are provided for
25858  * convenience and illustrative purposes. They should, however, be used with
25859  * caution as the C language standard provides no guarantees about the alignment or
25860  * atomicity of device memory accesses. The recommended practice for coding device
25861  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25862  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25863  * alt_write_dword() functions for 64 bit registers.
25864  *
25865  * The struct declaration for register ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL.
25866  */
25867 struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_s
25868 {
25869  volatile uint32_t SOCKETQOSEN : 1; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN */
25870  volatile uint32_t EXTTHREN : 1; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN */
25871  volatile uint32_t INTCLKEN : 1; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN */
25872  uint32_t : 29; /* *UNDEFINED* */
25873 };
25874 
25875 /* The typedef declaration for register ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL. */
25876 typedef struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_s ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_t;
25877 #endif /* __ASSEMBLY__ */
25878 
25879 /* The reset value of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL register. */
25880 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_RESET 0x00000000
25881 /* The byte offset of the ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL register from the beginning of the component. */
25882 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_OFST 0x18
25883 
25884 #ifndef __ASSEMBLY__
25885 /*
25886  * WARNING: The C register and register group struct declarations are provided for
25887  * convenience and illustrative purposes. They should, however, be used with
25888  * caution as the C language standard provides no guarantees about the alignment or
25889  * atomicity of device memory accesses. The recommended practice for coding device
25890  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25891  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25892  * alt_write_dword() functions for 64 bit registers.
25893  *
25894  * The struct declaration for register group ALT_MPFE_CCU_MEM0_QOS.
25895  */
25896 struct ALT_MPFE_CCU_MEM0_QOS_s
25897 {
25898  volatile ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_t ccu_mem0_I_main_QosGenerator_Id_CoreId; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID */
25899  volatile ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_t ccu_mem0_I_main_QosGenerator_Id_RevisionId; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID */
25900  volatile ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_t ccu_mem0_I_main_QosGenerator_Priority; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY */
25901  volatile ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_t ccu_mem0_I_main_QosGenerator_Mode; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE */
25902  volatile ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_t ccu_mem0_I_main_QosGenerator_Bandwidth; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH */
25903  volatile ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_t ccu_mem0_I_main_QosGenerator_Saturation; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION */
25904  volatile ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_t ccu_mem0_I_main_QosGenerator_ExtControl; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL */
25905  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
25906 };
25907 
25908 /* The typedef declaration for register group ALT_MPFE_CCU_MEM0_QOS. */
25909 typedef struct ALT_MPFE_CCU_MEM0_QOS_s ALT_MPFE_CCU_MEM0_QOS_t;
25910 /* The struct declaration for the raw register contents of register group ALT_MPFE_CCU_MEM0_QOS. */
25911 struct ALT_MPFE_CCU_MEM0_QOS_raw_s
25912 {
25913  volatile uint32_t ccu_mem0_I_main_QosGenerator_Id_CoreId; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID */
25914  volatile uint32_t ccu_mem0_I_main_QosGenerator_Id_RevisionId; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID */
25915  volatile uint32_t ccu_mem0_I_main_QosGenerator_Priority; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY */
25916  volatile uint32_t ccu_mem0_I_main_QosGenerator_Mode; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE */
25917  volatile uint32_t ccu_mem0_I_main_QosGenerator_Bandwidth; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH */
25918  volatile uint32_t ccu_mem0_I_main_QosGenerator_Saturation; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION */
25919  volatile uint32_t ccu_mem0_I_main_QosGenerator_ExtControl; /* ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL */
25920  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
25921 };
25922 
25923 /* The typedef declaration for the raw register contents of register group ALT_MPFE_CCU_MEM0_QOS. */
25924 typedef struct ALT_MPFE_CCU_MEM0_QOS_raw_s ALT_MPFE_CCU_MEM0_QOS_raw_t;
25925 #endif /* __ASSEMBLY__ */
25926 
25927 
25928 /*
25929  * Component : MPFE_F2SDR0_AXI128_QOS
25930  *
25931  */
25932 /*
25933  * Register : fpga2sdram0_axi128_I_main_QosGenerator_Id_CoreId
25934  *
25935  * Register Layout
25936  *
25937  * Bits | Access | Reset | Description
25938  * :-------|:-------|:---------|:-----------------------------------------------------------------------------------------
25939  * [7:0] | R | 0x4 | ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID
25940  * [31:8] | R | 0x38bac5 | ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM
25941  *
25942  */
25943 /*
25944  * Field : CORETYPEID
25945  *
25946  * Field identifying the type of IP.
25947  *
25948  * Field Access Macros:
25949  *
25950  */
25951 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
25952 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_LSB 0
25953 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
25954 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_MSB 7
25955 /* The width in bits of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
25956 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_WIDTH 8
25957 /* The mask used to set the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value. */
25958 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
25959 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value. */
25960 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
25961 /* The reset value of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
25962 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_RESET 0x4
25963 /* Extracts the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID field value from a register. */
25964 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
25965 /* Produces a ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value suitable for setting the register. */
25966 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
25967 
25968 /*
25969  * Field : CORECHECKSUM
25970  *
25971  * Field containing a checksum of the parameters of the IP.
25972  *
25973  * Field Access Macros:
25974  *
25975  */
25976 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
25977 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_LSB 8
25978 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
25979 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_MSB 31
25980 /* The width in bits of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
25981 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_WIDTH 24
25982 /* The mask used to set the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value. */
25983 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
25984 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value. */
25985 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
25986 /* The reset value of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
25987 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_RESET 0x38bac5
25988 /* Extracts the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM field value from a register. */
25989 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
25990 /* Produces a ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value suitable for setting the register. */
25991 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
25992 
25993 #ifndef __ASSEMBLY__
25994 /*
25995  * WARNING: The C register and register group struct declarations are provided for
25996  * convenience and illustrative purposes. They should, however, be used with
25997  * caution as the C language standard provides no guarantees about the alignment or
25998  * atomicity of device memory accesses. The recommended practice for coding device
25999  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26000  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26001  * alt_write_dword() functions for 64 bit registers.
26002  *
26003  * The struct declaration for register ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID.
26004  */
26005 struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_s
26006 {
26007  const volatile uint32_t CORETYPEID : 8; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID */
26008  const volatile uint32_t CORECHECKSUM : 24; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM */
26009 };
26010 
26011 /* The typedef declaration for register ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID. */
26012 typedef struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_s ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_t;
26013 #endif /* __ASSEMBLY__ */
26014 
26015 /* The reset value of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID register. */
26016 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_RESET 0x38bac504
26017 /* The byte offset of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID register from the beginning of the component. */
26018 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_OFST 0x0
26019 
26020 /*
26021  * Register : fpga2sdram0_axi128_I_main_QosGenerator_Id_RevisionId
26022  *
26023  * Register Layout
26024  *
26025  * Bits | Access | Reset | Description
26026  * :-------|:-------|:------|:------------------------------------------------------------------------------------------
26027  * [7:0] | R | 0x0 | ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID
26028  * [31:8] | R | 0x148 | ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID
26029  *
26030  */
26031 /*
26032  * Field : USERID
26033  *
26034  * Field containing a user defined value, not used anywhere inside the IP itself.
26035  *
26036  * Field Access Macros:
26037  *
26038  */
26039 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
26040 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_LSB 0
26041 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
26042 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_MSB 7
26043 /* The width in bits of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
26044 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_WIDTH 8
26045 /* The mask used to set the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value. */
26046 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET_MSK 0x000000ff
26047 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value. */
26048 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
26049 /* The reset value of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
26050 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_RESET 0x0
26051 /* Extracts the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID field value from a register. */
26052 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
26053 /* Produces a ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value suitable for setting the register. */
26054 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
26055 
26056 /*
26057  * Field : FLEXNOCID
26058  *
26059  * Field containing the build revision of the software used to generate the IP HDL
26060  * code.
26061  *
26062  * Field Access Macros:
26063  *
26064  */
26065 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
26066 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_LSB 8
26067 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
26068 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_MSB 31
26069 /* The width in bits of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
26070 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_WIDTH 24
26071 /* The mask used to set the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value. */
26072 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
26073 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value. */
26074 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
26075 /* The reset value of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
26076 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_RESET 0x148
26077 /* Extracts the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID field value from a register. */
26078 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
26079 /* Produces a ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value suitable for setting the register. */
26080 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
26081 
26082 #ifndef __ASSEMBLY__
26083 /*
26084  * WARNING: The C register and register group struct declarations are provided for
26085  * convenience and illustrative purposes. They should, however, be used with
26086  * caution as the C language standard provides no guarantees about the alignment or
26087  * atomicity of device memory accesses. The recommended practice for coding device
26088  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26089  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26090  * alt_write_dword() functions for 64 bit registers.
26091  *
26092  * The struct declaration for register ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID.
26093  */
26094 struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_s
26095 {
26096  const volatile uint32_t USERID : 8; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID */
26097  const volatile uint32_t FLEXNOCID : 24; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID */
26098 };
26099 
26100 /* The typedef declaration for register ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID. */
26101 typedef struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_s ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_t;
26102 #endif /* __ASSEMBLY__ */
26103 
26104 /* The reset value of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID register. */
26105 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_RESET 0x00014800
26106 /* The byte offset of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID register from the beginning of the component. */
26107 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_OFST 0x4
26108 
26109 /*
26110  * Register : fpga2sdram0_axi128_I_main_QosGenerator_Priority
26111  *
26112  * Priority register.
26113  *
26114  * Register Layout
26115  *
26116  * Bits | Access | Reset | Description
26117  * :--------|:-------|:--------|:--------------------------------------------------------------------------------
26118  * [1:0] | RW | 0x0 | ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0
26119  * [7:2] | ??? | Unknown | *UNDEFINED*
26120  * [9:8] | RW | 0x2 | ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1
26121  * [30:10] | ??? | Unknown | *UNDEFINED*
26122  * [31] | R | 0x1 | ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK
26123  *
26124  */
26125 /*
26126  * Field : P0
26127  *
26128  * In Programmable or Bandwidth Limiter mode, the priority level for write
26129  * transactions. In Bandwidth Regulator mode, the priority level when the used
26130  * throughput is above the threshold. In Bandwidth Regulator mode, P0 should have a
26131  * value equal or lower than P1.
26132  *
26133  * Field Access Macros:
26134  *
26135  */
26136 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
26137 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_LSB 0
26138 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
26139 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_MSB 1
26140 /* The width in bits of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
26141 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_WIDTH 2
26142 /* The mask used to set the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value. */
26143 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET_MSK 0x00000003
26144 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value. */
26145 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_CLR_MSK 0xfffffffc
26146 /* The reset value of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
26147 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_RESET 0x0
26148 /* Extracts the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 field value from a register. */
26149 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_GET(value) (((value) & 0x00000003) >> 0)
26150 /* Produces a ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value suitable for setting the register. */
26151 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET(value) (((value) << 0) & 0x00000003)
26152 
26153 /*
26154  * Field : P1
26155  *
26156  * In Programmable or Bandwidth Limiter mode, the priority level for read
26157  * transactions. In Bandwidth regulator mode, the priority level when the used
26158  * throughput is below the threshold. In Bandwidth Regulator mode, P1 should have a
26159  * value equal or greater than P0.
26160  *
26161  * Field Access Macros:
26162  *
26163  */
26164 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
26165 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_LSB 8
26166 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
26167 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_MSB 9
26168 /* The width in bits of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
26169 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_WIDTH 2
26170 /* The mask used to set the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value. */
26171 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET_MSK 0x00000300
26172 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value. */
26173 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_CLR_MSK 0xfffffcff
26174 /* The reset value of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
26175 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_RESET 0x2
26176 /* Extracts the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 field value from a register. */
26177 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_GET(value) (((value) & 0x00000300) >> 8)
26178 /* Produces a ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value suitable for setting the register. */
26179 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET(value) (((value) << 8) & 0x00000300)
26180 
26181 /*
26182  * Field : MARK
26183  *
26184  * Backward compatibility marker when 0.
26185  *
26186  * Field Access Macros:
26187  *
26188  */
26189 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
26190 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_LSB 31
26191 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
26192 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_MSB 31
26193 /* The width in bits of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
26194 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_WIDTH 1
26195 /* The mask used to set the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value. */
26196 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET_MSK 0x80000000
26197 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value. */
26198 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_CLR_MSK 0x7fffffff
26199 /* The reset value of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
26200 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_RESET 0x1
26201 /* Extracts the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK field value from a register. */
26202 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_GET(value) (((value) & 0x80000000) >> 31)
26203 /* Produces a ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value suitable for setting the register. */
26204 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET(value) (((value) << 31) & 0x80000000)
26205 
26206 #ifndef __ASSEMBLY__
26207 /*
26208  * WARNING: The C register and register group struct declarations are provided for
26209  * convenience and illustrative purposes. They should, however, be used with
26210  * caution as the C language standard provides no guarantees about the alignment or
26211  * atomicity of device memory accesses. The recommended practice for coding device
26212  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26213  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26214  * alt_write_dword() functions for 64 bit registers.
26215  *
26216  * The struct declaration for register ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY.
26217  */
26218 struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_s
26219 {
26220  volatile uint32_t P0 : 2; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 */
26221  uint32_t : 6; /* *UNDEFINED* */
26222  volatile uint32_t P1 : 2; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 */
26223  uint32_t : 21; /* *UNDEFINED* */
26224  const volatile uint32_t MARK : 1; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK */
26225 };
26226 
26227 /* The typedef declaration for register ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY. */
26228 typedef struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_s ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_t;
26229 #endif /* __ASSEMBLY__ */
26230 
26231 /* The reset value of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY register. */
26232 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_RESET 0x80000200
26233 /* The byte offset of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY register from the beginning of the component. */
26234 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_OFST 0x8
26235 
26236 /*
26237  * Register : fpga2sdram0_axi128_I_main_QosGenerator_Mode
26238  *
26239  * Register Layout
26240  *
26241  * Bits | Access | Reset | Description
26242  * :-------|:-------|:--------|:----------------------------------------------------------------------------
26243  * [1:0] | RW | 0x3 | ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE
26244  * [31:2] | ??? | Unknown | *UNDEFINED*
26245  *
26246  */
26247 /*
26248  * Field : MODE
26249  *
26250  * 0 = Programmable mode: a programmed priority is assigned to each read or write,
26251  * 1 = Bandwidth Limiter Mode: a hard limit restricts throughput, 2 = Bypass mode:
26252  * (<See SoC-specific QoS generator documentation>), 3 = Bandwidth Regulator mode:
26253  * priority decreases when throughput exceeds a threshold.
26254  *
26255  * Field Access Macros:
26256  *
26257  */
26258 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
26259 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_LSB 0
26260 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
26261 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_MSB 1
26262 /* The width in bits of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
26263 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_WIDTH 2
26264 /* The mask used to set the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE register field value. */
26265 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_SET_MSK 0x00000003
26266 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE register field value. */
26267 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_CLR_MSK 0xfffffffc
26268 /* The reset value of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
26269 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_RESET 0x3
26270 /* Extracts the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE field value from a register. */
26271 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_GET(value) (((value) & 0x00000003) >> 0)
26272 /* Produces a ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE register field value suitable for setting the register. */
26273 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_SET(value) (((value) << 0) & 0x00000003)
26274 
26275 #ifndef __ASSEMBLY__
26276 /*
26277  * WARNING: The C register and register group struct declarations are provided for
26278  * convenience and illustrative purposes. They should, however, be used with
26279  * caution as the C language standard provides no guarantees about the alignment or
26280  * atomicity of device memory accesses. The recommended practice for coding device
26281  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26282  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26283  * alt_write_dword() functions for 64 bit registers.
26284  *
26285  * The struct declaration for register ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE.
26286  */
26287 struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_s
26288 {
26289  volatile uint32_t MODE : 2; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE */
26290  uint32_t : 30; /* *UNDEFINED* */
26291 };
26292 
26293 /* The typedef declaration for register ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE. */
26294 typedef struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_s ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_t;
26295 #endif /* __ASSEMBLY__ */
26296 
26297 /* The reset value of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE register. */
26298 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_RESET 0x00000003
26299 /* The byte offset of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE register from the beginning of the component. */
26300 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_OFST 0xc
26301 
26302 /*
26303  * Register : fpga2sdram0_axi128_I_main_QosGenerator_Bandwidth
26304  *
26305  * Register Layout
26306  *
26307  * Bits | Access | Reset | Description
26308  * :--------|:-------|:--------|:--------------------------------------------------------------------------------------
26309  * [12:0] | RW | 0xc80 | ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH
26310  * [31:13] | ??? | Unknown | *UNDEFINED*
26311  *
26312  */
26313 /*
26314  * Field : BANDWIDTH
26315  *
26316  * In Bandwidth Limiter or Bandwidth Regulator mode, the bandwidth threshold in
26317  * units of 1/256th bytes per cycle. For example, 80 MBps on a 250 MHz interface is
26318  * value 0x0052.
26319  *
26320  * Field Access Macros:
26321  *
26322  */
26323 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
26324 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_LSB 0
26325 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
26326 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MSB 12
26327 /* The width in bits of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
26328 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_WIDTH 13
26329 /* The mask used to set the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value. */
26330 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET_MSK 0x00001fff
26331 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value. */
26332 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_CLR_MSK 0xffffe000
26333 /* The reset value of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
26334 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_RESET 0xc80
26335 /* Extracts the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH field value from a register. */
26336 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_GET(value) (((value) & 0x00001fff) >> 0)
26337 /* Produces a ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value suitable for setting the register. */
26338 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x00001fff)
26339 
26340 #ifndef __ASSEMBLY__
26341 /*
26342  * WARNING: The C register and register group struct declarations are provided for
26343  * convenience and illustrative purposes. They should, however, be used with
26344  * caution as the C language standard provides no guarantees about the alignment or
26345  * atomicity of device memory accesses. The recommended practice for coding device
26346  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26347  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26348  * alt_write_dword() functions for 64 bit registers.
26349  *
26350  * The struct declaration for register ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH.
26351  */
26352 struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_s
26353 {
26354  volatile uint32_t BANDWIDTH : 13; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH */
26355  uint32_t : 19; /* *UNDEFINED* */
26356 };
26357 
26358 /* The typedef declaration for register ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH. */
26359 typedef struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_s ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_t;
26360 #endif /* __ASSEMBLY__ */
26361 
26362 /* The reset value of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH register. */
26363 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_RESET 0x00000c80
26364 /* The byte offset of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH register from the beginning of the component. */
26365 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_OFST 0x10
26366 
26367 /*
26368  * Register : fpga2sdram0_axi128_I_main_QosGenerator_Saturation
26369  *
26370  * Register Layout
26371  *
26372  * Bits | Access | Reset | Description
26373  * :--------|:-------|:--------|:----------------------------------------------------------------------------------------
26374  * [9:0] | RW | 0x8 | ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION
26375  * [31:10] | ??? | Unknown | *UNDEFINED*
26376  *
26377  */
26378 /*
26379  * Field : SATURATION
26380  *
26381  * In Bandwidth Limiter or Bandwidth Regulator mode, the maximum data count value,
26382  * in units of 16 bytes. This determines the window of time over which bandwidth is
26383  * measured. For example, to measure bandwidth within a 1000 cycle window on a
26384  * 64-bit interface is value 0x1F4.
26385  *
26386  * Field Access Macros:
26387  *
26388  */
26389 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
26390 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_LSB 0
26391 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
26392 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_MSB 9
26393 /* The width in bits of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
26394 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_WIDTH 10
26395 /* The mask used to set the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value. */
26396 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET_MSK 0x000003ff
26397 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value. */
26398 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_CLR_MSK 0xfffffc00
26399 /* The reset value of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
26400 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_RESET 0x8
26401 /* Extracts the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION field value from a register. */
26402 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
26403 /* Produces a ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value suitable for setting the register. */
26404 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
26405 
26406 #ifndef __ASSEMBLY__
26407 /*
26408  * WARNING: The C register and register group struct declarations are provided for
26409  * convenience and illustrative purposes. They should, however, be used with
26410  * caution as the C language standard provides no guarantees about the alignment or
26411  * atomicity of device memory accesses. The recommended practice for coding device
26412  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26413  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26414  * alt_write_dword() functions for 64 bit registers.
26415  *
26416  * The struct declaration for register ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION.
26417  */
26418 struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_s
26419 {
26420  volatile uint32_t SATURATION : 10; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION */
26421  uint32_t : 22; /* *UNDEFINED* */
26422 };
26423 
26424 /* The typedef declaration for register ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION. */
26425 typedef struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_s ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_t;
26426 #endif /* __ASSEMBLY__ */
26427 
26428 /* The reset value of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION register. */
26429 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_RESET 0x00000008
26430 /* The byte offset of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION register from the beginning of the component. */
26431 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_OFST 0x14
26432 
26433 /*
26434  * Register : fpga2sdram0_axi128_I_main_QosGenerator_ExtControl
26435  *
26436  * External inputs control.
26437  *
26438  * Register Layout
26439  *
26440  * Bits | Access | Reset | Description
26441  * :-------|:-------|:--------|:-----------------------------------------------------------------------------------------
26442  * [0] | RW | 0x0 | ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN
26443  * [1] | RW | 0x0 | ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN
26444  * [2] | RW | 0x0 | ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN
26445  * [31:3] | ??? | Unknown | *UNDEFINED*
26446  *
26447  */
26448 /*
26449  * Field : SOCKETQOSEN
26450  *
26451  * n/a
26452  *
26453  * Field Access Macros:
26454  *
26455  */
26456 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
26457 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_LSB 0
26458 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
26459 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MSB 0
26460 /* The width in bits of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
26461 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_WIDTH 1
26462 /* The mask used to set the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value. */
26463 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET_MSK 0x00000001
26464 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value. */
26465 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_CLR_MSK 0xfffffffe
26466 /* The reset value of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
26467 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_RESET 0x0
26468 /* Extracts the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN field value from a register. */
26469 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
26470 /* Produces a ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value suitable for setting the register. */
26471 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
26472 
26473 /*
26474  * Field : EXTTHREN
26475  *
26476  * n/a
26477  *
26478  * Field Access Macros:
26479  *
26480  */
26481 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
26482 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_LSB 1
26483 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
26484 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_MSB 1
26485 /* The width in bits of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
26486 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_WIDTH 1
26487 /* The mask used to set the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value. */
26488 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET_MSK 0x00000002
26489 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value. */
26490 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_CLR_MSK 0xfffffffd
26491 /* The reset value of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
26492 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_RESET 0x0
26493 /* Extracts the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN field value from a register. */
26494 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
26495 /* Produces a ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value suitable for setting the register. */
26496 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
26497 
26498 /*
26499  * Field : INTCLKEN
26500  *
26501  * n/a
26502  *
26503  * Field Access Macros:
26504  *
26505  */
26506 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
26507 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_LSB 2
26508 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
26509 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_MSB 2
26510 /* The width in bits of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
26511 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_WIDTH 1
26512 /* The mask used to set the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value. */
26513 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET_MSK 0x00000004
26514 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value. */
26515 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_CLR_MSK 0xfffffffb
26516 /* The reset value of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
26517 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_RESET 0x0
26518 /* Extracts the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN field value from a register. */
26519 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
26520 /* Produces a ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value suitable for setting the register. */
26521 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
26522 
26523 #ifndef __ASSEMBLY__
26524 /*
26525  * WARNING: The C register and register group struct declarations are provided for
26526  * convenience and illustrative purposes. They should, however, be used with
26527  * caution as the C language standard provides no guarantees about the alignment or
26528  * atomicity of device memory accesses. The recommended practice for coding device
26529  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26530  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26531  * alt_write_dword() functions for 64 bit registers.
26532  *
26533  * The struct declaration for register ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL.
26534  */
26535 struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_s
26536 {
26537  volatile uint32_t SOCKETQOSEN : 1; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN */
26538  volatile uint32_t EXTTHREN : 1; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN */
26539  volatile uint32_t INTCLKEN : 1; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN */
26540  uint32_t : 29; /* *UNDEFINED* */
26541 };
26542 
26543 /* The typedef declaration for register ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL. */
26544 typedef struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_s ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_t;
26545 #endif /* __ASSEMBLY__ */
26546 
26547 /* The reset value of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL register. */
26548 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_RESET 0x00000000
26549 /* The byte offset of the ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL register from the beginning of the component. */
26550 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_OFST 0x18
26551 
26552 #ifndef __ASSEMBLY__
26553 /*
26554  * WARNING: The C register and register group struct declarations are provided for
26555  * convenience and illustrative purposes. They should, however, be used with
26556  * caution as the C language standard provides no guarantees about the alignment or
26557  * atomicity of device memory accesses. The recommended practice for coding device
26558  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26559  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26560  * alt_write_dword() functions for 64 bit registers.
26561  *
26562  * The struct declaration for register group ALT_MPFE_F2SDR0_AXI128_QOS.
26563  */
26564 struct ALT_MPFE_F2SDR0_AXI128_QOS_s
26565 {
26566  volatile ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_t fpga2sdram0_axi128_I_main_QosGenerator_Id_CoreId; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID */
26567  volatile ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_t fpga2sdram0_axi128_I_main_QosGenerator_Id_RevisionId; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID */
26568  volatile ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_t fpga2sdram0_axi128_I_main_QosGenerator_Priority; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY */
26569  volatile ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_t fpga2sdram0_axi128_I_main_QosGenerator_Mode; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE */
26570  volatile ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_t fpga2sdram0_axi128_I_main_QosGenerator_Bandwidth; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH */
26571  volatile ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_t fpga2sdram0_axi128_I_main_QosGenerator_Saturation; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION */
26572  volatile ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_t fpga2sdram0_axi128_I_main_QosGenerator_ExtControl; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL */
26573  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
26574 };
26575 
26576 /* The typedef declaration for register group ALT_MPFE_F2SDR0_AXI128_QOS. */
26577 typedef struct ALT_MPFE_F2SDR0_AXI128_QOS_s ALT_MPFE_F2SDR0_AXI128_QOS_t;
26578 /* The struct declaration for the raw register contents of register group ALT_MPFE_F2SDR0_AXI128_QOS. */
26579 struct ALT_MPFE_F2SDR0_AXI128_QOS_raw_s
26580 {
26581  volatile uint32_t fpga2sdram0_axi128_I_main_QosGenerator_Id_CoreId; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID */
26582  volatile uint32_t fpga2sdram0_axi128_I_main_QosGenerator_Id_RevisionId; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID */
26583  volatile uint32_t fpga2sdram0_axi128_I_main_QosGenerator_Priority; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY */
26584  volatile uint32_t fpga2sdram0_axi128_I_main_QosGenerator_Mode; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE */
26585  volatile uint32_t fpga2sdram0_axi128_I_main_QosGenerator_Bandwidth; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH */
26586  volatile uint32_t fpga2sdram0_axi128_I_main_QosGenerator_Saturation; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION */
26587  volatile uint32_t fpga2sdram0_axi128_I_main_QosGenerator_ExtControl; /* ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL */
26588  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
26589 };
26590 
26591 /* The typedef declaration for the raw register contents of register group ALT_MPFE_F2SDR0_AXI128_QOS. */
26592 typedef struct ALT_MPFE_F2SDR0_AXI128_QOS_raw_s ALT_MPFE_F2SDR0_AXI128_QOS_raw_t;
26593 #endif /* __ASSEMBLY__ */
26594 
26595 
26596 /*
26597  * Component : MPFE_F2SDR0_AXI32_QOS
26598  *
26599  */
26600 /*
26601  * Register : fpga2sdram0_axi32_I_main_QosGenerator_Id_CoreId
26602  *
26603  * Register Layout
26604  *
26605  * Bits | Access | Reset | Description
26606  * :-------|:-------|:---------|:---------------------------------------------------------------------------------------
26607  * [7:0] | R | 0x4 | ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID
26608  * [31:8] | R | 0x90f627 | ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM
26609  *
26610  */
26611 /*
26612  * Field : CORETYPEID
26613  *
26614  * Field identifying the type of IP.
26615  *
26616  * Field Access Macros:
26617  *
26618  */
26619 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
26620 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_LSB 0
26621 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
26622 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_MSB 7
26623 /* The width in bits of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
26624 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_WIDTH 8
26625 /* The mask used to set the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value. */
26626 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
26627 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value. */
26628 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
26629 /* The reset value of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
26630 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_RESET 0x4
26631 /* Extracts the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID field value from a register. */
26632 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
26633 /* Produces a ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value suitable for setting the register. */
26634 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
26635 
26636 /*
26637  * Field : CORECHECKSUM
26638  *
26639  * Field containing a checksum of the parameters of the IP.
26640  *
26641  * Field Access Macros:
26642  *
26643  */
26644 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
26645 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_LSB 8
26646 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
26647 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_MSB 31
26648 /* The width in bits of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
26649 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_WIDTH 24
26650 /* The mask used to set the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value. */
26651 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
26652 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value. */
26653 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
26654 /* The reset value of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
26655 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_RESET 0x90f627
26656 /* Extracts the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM field value from a register. */
26657 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
26658 /* Produces a ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value suitable for setting the register. */
26659 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
26660 
26661 #ifndef __ASSEMBLY__
26662 /*
26663  * WARNING: The C register and register group struct declarations are provided for
26664  * convenience and illustrative purposes. They should, however, be used with
26665  * caution as the C language standard provides no guarantees about the alignment or
26666  * atomicity of device memory accesses. The recommended practice for coding device
26667  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26668  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26669  * alt_write_dword() functions for 64 bit registers.
26670  *
26671  * The struct declaration for register ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID.
26672  */
26673 struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_s
26674 {
26675  const volatile uint32_t CORETYPEID : 8; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID */
26676  const volatile uint32_t CORECHECKSUM : 24; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM */
26677 };
26678 
26679 /* The typedef declaration for register ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID. */
26680 typedef struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_s ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_t;
26681 #endif /* __ASSEMBLY__ */
26682 
26683 /* The reset value of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID register. */
26684 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_RESET 0x90f62704
26685 /* The byte offset of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID register from the beginning of the component. */
26686 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_OFST 0x0
26687 
26688 /*
26689  * Register : fpga2sdram0_axi32_I_main_QosGenerator_Id_RevisionId
26690  *
26691  * Register Layout
26692  *
26693  * Bits | Access | Reset | Description
26694  * :-------|:-------|:------|:----------------------------------------------------------------------------------------
26695  * [7:0] | R | 0x0 | ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID
26696  * [31:8] | R | 0x148 | ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID
26697  *
26698  */
26699 /*
26700  * Field : USERID
26701  *
26702  * Field containing a user defined value, not used anywhere inside the IP itself.
26703  *
26704  * Field Access Macros:
26705  *
26706  */
26707 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
26708 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_LSB 0
26709 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
26710 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_MSB 7
26711 /* The width in bits of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
26712 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_WIDTH 8
26713 /* The mask used to set the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value. */
26714 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET_MSK 0x000000ff
26715 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value. */
26716 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
26717 /* The reset value of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
26718 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_RESET 0x0
26719 /* Extracts the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID field value from a register. */
26720 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
26721 /* Produces a ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value suitable for setting the register. */
26722 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
26723 
26724 /*
26725  * Field : FLEXNOCID
26726  *
26727  * Field containing the build revision of the software used to generate the IP HDL
26728  * code.
26729  *
26730  * Field Access Macros:
26731  *
26732  */
26733 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
26734 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_LSB 8
26735 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
26736 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_MSB 31
26737 /* The width in bits of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
26738 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_WIDTH 24
26739 /* The mask used to set the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value. */
26740 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
26741 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value. */
26742 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
26743 /* The reset value of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
26744 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_RESET 0x148
26745 /* Extracts the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID field value from a register. */
26746 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
26747 /* Produces a ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value suitable for setting the register. */
26748 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
26749 
26750 #ifndef __ASSEMBLY__
26751 /*
26752  * WARNING: The C register and register group struct declarations are provided for
26753  * convenience and illustrative purposes. They should, however, be used with
26754  * caution as the C language standard provides no guarantees about the alignment or
26755  * atomicity of device memory accesses. The recommended practice for coding device
26756  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26757  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26758  * alt_write_dword() functions for 64 bit registers.
26759  *
26760  * The struct declaration for register ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID.
26761  */
26762 struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_s
26763 {
26764  const volatile uint32_t USERID : 8; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID */
26765  const volatile uint32_t FLEXNOCID : 24; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID */
26766 };
26767 
26768 /* The typedef declaration for register ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID. */
26769 typedef struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_s ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_t;
26770 #endif /* __ASSEMBLY__ */
26771 
26772 /* The reset value of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID register. */
26773 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_RESET 0x00014800
26774 /* The byte offset of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID register from the beginning of the component. */
26775 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_OFST 0x4
26776 
26777 /*
26778  * Register : fpga2sdram0_axi32_I_main_QosGenerator_Priority
26779  *
26780  * Priority register.
26781  *
26782  * Register Layout
26783  *
26784  * Bits | Access | Reset | Description
26785  * :--------|:-------|:--------|:------------------------------------------------------------------------------
26786  * [1:0] | RW | 0x0 | ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0
26787  * [7:2] | ??? | Unknown | *UNDEFINED*
26788  * [9:8] | RW | 0x2 | ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1
26789  * [30:10] | ??? | Unknown | *UNDEFINED*
26790  * [31] | R | 0x1 | ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK
26791  *
26792  */
26793 /*
26794  * Field : P0
26795  *
26796  * In Programmable or Bandwidth Limiter mode, the priority level for write
26797  * transactions. In Bandwidth Regulator mode, the priority level when the used
26798  * throughput is above the threshold. In Bandwidth Regulator mode, P0 should have a
26799  * value equal or lower than P1.
26800  *
26801  * Field Access Macros:
26802  *
26803  */
26804 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
26805 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_LSB 0
26806 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
26807 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_MSB 1
26808 /* The width in bits of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
26809 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_WIDTH 2
26810 /* The mask used to set the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value. */
26811 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET_MSK 0x00000003
26812 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value. */
26813 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_CLR_MSK 0xfffffffc
26814 /* The reset value of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
26815 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_RESET 0x0
26816 /* Extracts the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 field value from a register. */
26817 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_GET(value) (((value) & 0x00000003) >> 0)
26818 /* Produces a ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value suitable for setting the register. */
26819 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET(value) (((value) << 0) & 0x00000003)
26820 
26821 /*
26822  * Field : P1
26823  *
26824  * In Programmable or Bandwidth Limiter mode, the priority level for read
26825  * transactions. In Bandwidth regulator mode, the priority level when the used
26826  * throughput is below the threshold. In Bandwidth Regulator mode, P1 should have a
26827  * value equal or greater than P0.
26828  *
26829  * Field Access Macros:
26830  *
26831  */
26832 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
26833 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_LSB 8
26834 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
26835 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_MSB 9
26836 /* The width in bits of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
26837 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_WIDTH 2
26838 /* The mask used to set the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value. */
26839 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET_MSK 0x00000300
26840 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value. */
26841 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_CLR_MSK 0xfffffcff
26842 /* The reset value of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
26843 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_RESET 0x2
26844 /* Extracts the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 field value from a register. */
26845 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_GET(value) (((value) & 0x00000300) >> 8)
26846 /* Produces a ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value suitable for setting the register. */
26847 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET(value) (((value) << 8) & 0x00000300)
26848 
26849 /*
26850  * Field : MARK
26851  *
26852  * Backward compatibility marker when 0.
26853  *
26854  * Field Access Macros:
26855  *
26856  */
26857 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
26858 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_LSB 31
26859 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
26860 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_MSB 31
26861 /* The width in bits of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
26862 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_WIDTH 1
26863 /* The mask used to set the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value. */
26864 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET_MSK 0x80000000
26865 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value. */
26866 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_CLR_MSK 0x7fffffff
26867 /* The reset value of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
26868 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_RESET 0x1
26869 /* Extracts the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK field value from a register. */
26870 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_GET(value) (((value) & 0x80000000) >> 31)
26871 /* Produces a ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value suitable for setting the register. */
26872 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET(value) (((value) << 31) & 0x80000000)
26873 
26874 #ifndef __ASSEMBLY__
26875 /*
26876  * WARNING: The C register and register group struct declarations are provided for
26877  * convenience and illustrative purposes. They should, however, be used with
26878  * caution as the C language standard provides no guarantees about the alignment or
26879  * atomicity of device memory accesses. The recommended practice for coding device
26880  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26881  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26882  * alt_write_dword() functions for 64 bit registers.
26883  *
26884  * The struct declaration for register ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY.
26885  */
26886 struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_s
26887 {
26888  volatile uint32_t P0 : 2; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 */
26889  uint32_t : 6; /* *UNDEFINED* */
26890  volatile uint32_t P1 : 2; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 */
26891  uint32_t : 21; /* *UNDEFINED* */
26892  const volatile uint32_t MARK : 1; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK */
26893 };
26894 
26895 /* The typedef declaration for register ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY. */
26896 typedef struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_s ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_t;
26897 #endif /* __ASSEMBLY__ */
26898 
26899 /* The reset value of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY register. */
26900 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_RESET 0x80000200
26901 /* The byte offset of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY register from the beginning of the component. */
26902 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_OFST 0x8
26903 
26904 /*
26905  * Register : fpga2sdram0_axi32_I_main_QosGenerator_Mode
26906  *
26907  * Register Layout
26908  *
26909  * Bits | Access | Reset | Description
26910  * :-------|:-------|:--------|:--------------------------------------------------------------------------
26911  * [1:0] | RW | 0x3 | ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE
26912  * [31:2] | ??? | Unknown | *UNDEFINED*
26913  *
26914  */
26915 /*
26916  * Field : MODE
26917  *
26918  * 0 = Programmable mode: a programmed priority is assigned to each read or write,
26919  * 1 = Bandwidth Limiter Mode: a hard limit restricts throughput, 2 = Bypass mode:
26920  * (<See SoC-specific QoS generator documentation>), 3 = Bandwidth Regulator mode:
26921  * priority decreases when throughput exceeds a threshold.
26922  *
26923  * Field Access Macros:
26924  *
26925  */
26926 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
26927 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_LSB 0
26928 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
26929 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_MSB 1
26930 /* The width in bits of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
26931 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_WIDTH 2
26932 /* The mask used to set the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE register field value. */
26933 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_SET_MSK 0x00000003
26934 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE register field value. */
26935 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_CLR_MSK 0xfffffffc
26936 /* The reset value of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
26937 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_RESET 0x3
26938 /* Extracts the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE field value from a register. */
26939 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_GET(value) (((value) & 0x00000003) >> 0)
26940 /* Produces a ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE register field value suitable for setting the register. */
26941 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_SET(value) (((value) << 0) & 0x00000003)
26942 
26943 #ifndef __ASSEMBLY__
26944 /*
26945  * WARNING: The C register and register group struct declarations are provided for
26946  * convenience and illustrative purposes. They should, however, be used with
26947  * caution as the C language standard provides no guarantees about the alignment or
26948  * atomicity of device memory accesses. The recommended practice for coding device
26949  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26950  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26951  * alt_write_dword() functions for 64 bit registers.
26952  *
26953  * The struct declaration for register ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE.
26954  */
26955 struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_s
26956 {
26957  volatile uint32_t MODE : 2; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE */
26958  uint32_t : 30; /* *UNDEFINED* */
26959 };
26960 
26961 /* The typedef declaration for register ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE. */
26962 typedef struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_s ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_t;
26963 #endif /* __ASSEMBLY__ */
26964 
26965 /* The reset value of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE register. */
26966 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_RESET 0x00000003
26967 /* The byte offset of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE register from the beginning of the component. */
26968 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_OFST 0xc
26969 
26970 /*
26971  * Register : fpga2sdram0_axi32_I_main_QosGenerator_Bandwidth
26972  *
26973  * Register Layout
26974  *
26975  * Bits | Access | Reset | Description
26976  * :--------|:-------|:--------|:------------------------------------------------------------------------------------
26977  * [10:0] | RW | 0x280 | ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH
26978  * [31:11] | ??? | Unknown | *UNDEFINED*
26979  *
26980  */
26981 /*
26982  * Field : BANDWIDTH
26983  *
26984  * In Bandwidth Limiter or Bandwidth Regulator mode, the bandwidth threshold in
26985  * units of 1/256th bytes per cycle. For example, 80 MBps on a 250 MHz interface is
26986  * value 0x0052.
26987  *
26988  * Field Access Macros:
26989  *
26990  */
26991 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
26992 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_LSB 0
26993 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
26994 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MSB 10
26995 /* The width in bits of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
26996 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_WIDTH 11
26997 /* The mask used to set the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value. */
26998 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET_MSK 0x000007ff
26999 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value. */
27000 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_CLR_MSK 0xfffff800
27001 /* The reset value of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
27002 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_RESET 0x280
27003 /* Extracts the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH field value from a register. */
27004 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_GET(value) (((value) & 0x000007ff) >> 0)
27005 /* Produces a ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value suitable for setting the register. */
27006 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x000007ff)
27007 
27008 #ifndef __ASSEMBLY__
27009 /*
27010  * WARNING: The C register and register group struct declarations are provided for
27011  * convenience and illustrative purposes. They should, however, be used with
27012  * caution as the C language standard provides no guarantees about the alignment or
27013  * atomicity of device memory accesses. The recommended practice for coding device
27014  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27015  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27016  * alt_write_dword() functions for 64 bit registers.
27017  *
27018  * The struct declaration for register ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH.
27019  */
27020 struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_s
27021 {
27022  volatile uint32_t BANDWIDTH : 11; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH */
27023  uint32_t : 21; /* *UNDEFINED* */
27024 };
27025 
27026 /* The typedef declaration for register ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH. */
27027 typedef struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_s ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_t;
27028 #endif /* __ASSEMBLY__ */
27029 
27030 /* The reset value of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH register. */
27031 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_RESET 0x00000280
27032 /* The byte offset of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH register from the beginning of the component. */
27033 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_OFST 0x10
27034 
27035 /*
27036  * Register : fpga2sdram0_axi32_I_main_QosGenerator_Saturation
27037  *
27038  * Register Layout
27039  *
27040  * Bits | Access | Reset | Description
27041  * :--------|:-------|:--------|:--------------------------------------------------------------------------------------
27042  * [9:0] | RW | 0x8 | ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION
27043  * [31:10] | ??? | Unknown | *UNDEFINED*
27044  *
27045  */
27046 /*
27047  * Field : SATURATION
27048  *
27049  * In Bandwidth Limiter or Bandwidth Regulator mode, the maximum data count value,
27050  * in units of 16 bytes. This determines the window of time over which bandwidth is
27051  * measured. For example, to measure bandwidth within a 1000 cycle window on a
27052  * 64-bit interface is value 0x1F4.
27053  *
27054  * Field Access Macros:
27055  *
27056  */
27057 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
27058 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_LSB 0
27059 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
27060 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_MSB 9
27061 /* The width in bits of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
27062 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_WIDTH 10
27063 /* The mask used to set the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value. */
27064 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET_MSK 0x000003ff
27065 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value. */
27066 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_CLR_MSK 0xfffffc00
27067 /* The reset value of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
27068 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_RESET 0x8
27069 /* Extracts the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION field value from a register. */
27070 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
27071 /* Produces a ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value suitable for setting the register. */
27072 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
27073 
27074 #ifndef __ASSEMBLY__
27075 /*
27076  * WARNING: The C register and register group struct declarations are provided for
27077  * convenience and illustrative purposes. They should, however, be used with
27078  * caution as the C language standard provides no guarantees about the alignment or
27079  * atomicity of device memory accesses. The recommended practice for coding device
27080  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27081  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27082  * alt_write_dword() functions for 64 bit registers.
27083  *
27084  * The struct declaration for register ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION.
27085  */
27086 struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_s
27087 {
27088  volatile uint32_t SATURATION : 10; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION */
27089  uint32_t : 22; /* *UNDEFINED* */
27090 };
27091 
27092 /* The typedef declaration for register ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION. */
27093 typedef struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_s ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_t;
27094 #endif /* __ASSEMBLY__ */
27095 
27096 /* The reset value of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION register. */
27097 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_RESET 0x00000008
27098 /* The byte offset of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION register from the beginning of the component. */
27099 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_OFST 0x14
27100 
27101 /*
27102  * Register : fpga2sdram0_axi32_I_main_QosGenerator_ExtControl
27103  *
27104  * External inputs control.
27105  *
27106  * Register Layout
27107  *
27108  * Bits | Access | Reset | Description
27109  * :-------|:-------|:--------|:---------------------------------------------------------------------------------------
27110  * [0] | RW | 0x0 | ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN
27111  * [1] | RW | 0x0 | ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN
27112  * [2] | RW | 0x0 | ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN
27113  * [31:3] | ??? | Unknown | *UNDEFINED*
27114  *
27115  */
27116 /*
27117  * Field : SOCKETQOSEN
27118  *
27119  * n/a
27120  *
27121  * Field Access Macros:
27122  *
27123  */
27124 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
27125 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_LSB 0
27126 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
27127 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MSB 0
27128 /* The width in bits of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
27129 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_WIDTH 1
27130 /* The mask used to set the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value. */
27131 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET_MSK 0x00000001
27132 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value. */
27133 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_CLR_MSK 0xfffffffe
27134 /* The reset value of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
27135 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_RESET 0x0
27136 /* Extracts the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN field value from a register. */
27137 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
27138 /* Produces a ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value suitable for setting the register. */
27139 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
27140 
27141 /*
27142  * Field : EXTTHREN
27143  *
27144  * n/a
27145  *
27146  * Field Access Macros:
27147  *
27148  */
27149 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
27150 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_LSB 1
27151 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
27152 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_MSB 1
27153 /* The width in bits of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
27154 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_WIDTH 1
27155 /* The mask used to set the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value. */
27156 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET_MSK 0x00000002
27157 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value. */
27158 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_CLR_MSK 0xfffffffd
27159 /* The reset value of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
27160 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_RESET 0x0
27161 /* Extracts the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN field value from a register. */
27162 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
27163 /* Produces a ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value suitable for setting the register. */
27164 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
27165 
27166 /*
27167  * Field : INTCLKEN
27168  *
27169  * n/a
27170  *
27171  * Field Access Macros:
27172  *
27173  */
27174 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
27175 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_LSB 2
27176 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
27177 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_MSB 2
27178 /* The width in bits of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
27179 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_WIDTH 1
27180 /* The mask used to set the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value. */
27181 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET_MSK 0x00000004
27182 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value. */
27183 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_CLR_MSK 0xfffffffb
27184 /* The reset value of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
27185 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_RESET 0x0
27186 /* Extracts the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN field value from a register. */
27187 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
27188 /* Produces a ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value suitable for setting the register. */
27189 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
27190 
27191 #ifndef __ASSEMBLY__
27192 /*
27193  * WARNING: The C register and register group struct declarations are provided for
27194  * convenience and illustrative purposes. They should, however, be used with
27195  * caution as the C language standard provides no guarantees about the alignment or
27196  * atomicity of device memory accesses. The recommended practice for coding device
27197  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27198  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27199  * alt_write_dword() functions for 64 bit registers.
27200  *
27201  * The struct declaration for register ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL.
27202  */
27203 struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_s
27204 {
27205  volatile uint32_t SOCKETQOSEN : 1; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN */
27206  volatile uint32_t EXTTHREN : 1; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN */
27207  volatile uint32_t INTCLKEN : 1; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN */
27208  uint32_t : 29; /* *UNDEFINED* */
27209 };
27210 
27211 /* The typedef declaration for register ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL. */
27212 typedef struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_s ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_t;
27213 #endif /* __ASSEMBLY__ */
27214 
27215 /* The reset value of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL register. */
27216 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_RESET 0x00000000
27217 /* The byte offset of the ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL register from the beginning of the component. */
27218 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_OFST 0x18
27219 
27220 #ifndef __ASSEMBLY__
27221 /*
27222  * WARNING: The C register and register group struct declarations are provided for
27223  * convenience and illustrative purposes. They should, however, be used with
27224  * caution as the C language standard provides no guarantees about the alignment or
27225  * atomicity of device memory accesses. The recommended practice for coding device
27226  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27227  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27228  * alt_write_dword() functions for 64 bit registers.
27229  *
27230  * The struct declaration for register group ALT_MPFE_F2SDR0_AXI32_QOS.
27231  */
27232 struct ALT_MPFE_F2SDR0_AXI32_QOS_s
27233 {
27234  volatile ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_t fpga2sdram0_axi32_I_main_QosGenerator_Id_CoreId; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID */
27235  volatile ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_t fpga2sdram0_axi32_I_main_QosGenerator_Id_RevisionId; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID */
27236  volatile ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_t fpga2sdram0_axi32_I_main_QosGenerator_Priority; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY */
27237  volatile ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_t fpga2sdram0_axi32_I_main_QosGenerator_Mode; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE */
27238  volatile ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_t fpga2sdram0_axi32_I_main_QosGenerator_Bandwidth; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH */
27239  volatile ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_t fpga2sdram0_axi32_I_main_QosGenerator_Saturation; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION */
27240  volatile ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_t fpga2sdram0_axi32_I_main_QosGenerator_ExtControl; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL */
27241  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
27242 };
27243 
27244 /* The typedef declaration for register group ALT_MPFE_F2SDR0_AXI32_QOS. */
27245 typedef struct ALT_MPFE_F2SDR0_AXI32_QOS_s ALT_MPFE_F2SDR0_AXI32_QOS_t;
27246 /* The struct declaration for the raw register contents of register group ALT_MPFE_F2SDR0_AXI32_QOS. */
27247 struct ALT_MPFE_F2SDR0_AXI32_QOS_raw_s
27248 {
27249  volatile uint32_t fpga2sdram0_axi32_I_main_QosGenerator_Id_CoreId; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID */
27250  volatile uint32_t fpga2sdram0_axi32_I_main_QosGenerator_Id_RevisionId; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID */
27251  volatile uint32_t fpga2sdram0_axi32_I_main_QosGenerator_Priority; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY */
27252  volatile uint32_t fpga2sdram0_axi32_I_main_QosGenerator_Mode; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE */
27253  volatile uint32_t fpga2sdram0_axi32_I_main_QosGenerator_Bandwidth; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH */
27254  volatile uint32_t fpga2sdram0_axi32_I_main_QosGenerator_Saturation; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION */
27255  volatile uint32_t fpga2sdram0_axi32_I_main_QosGenerator_ExtControl; /* ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL */
27256  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
27257 };
27258 
27259 /* The typedef declaration for the raw register contents of register group ALT_MPFE_F2SDR0_AXI32_QOS. */
27260 typedef struct ALT_MPFE_F2SDR0_AXI32_QOS_raw_s ALT_MPFE_F2SDR0_AXI32_QOS_raw_t;
27261 #endif /* __ASSEMBLY__ */
27262 
27263 
27264 /*
27265  * Component : MPFE_F2SDR0_AXI64_QOS
27266  *
27267  */
27268 /*
27269  * Register : fpga2sdram0_axi64_I_main_QosGenerator_Id_CoreId
27270  *
27271  * Register Layout
27272  *
27273  * Bits | Access | Reset | Description
27274  * :-------|:-------|:---------|:---------------------------------------------------------------------------------------
27275  * [7:0] | R | 0x4 | ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID
27276  * [31:8] | R | 0xb31375 | ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM
27277  *
27278  */
27279 /*
27280  * Field : CORETYPEID
27281  *
27282  * Field identifying the type of IP.
27283  *
27284  * Field Access Macros:
27285  *
27286  */
27287 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
27288 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_LSB 0
27289 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
27290 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_MSB 7
27291 /* The width in bits of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
27292 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_WIDTH 8
27293 /* The mask used to set the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value. */
27294 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
27295 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value. */
27296 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
27297 /* The reset value of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
27298 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_RESET 0x4
27299 /* Extracts the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID field value from a register. */
27300 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
27301 /* Produces a ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value suitable for setting the register. */
27302 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
27303 
27304 /*
27305  * Field : CORECHECKSUM
27306  *
27307  * Field containing a checksum of the parameters of the IP.
27308  *
27309  * Field Access Macros:
27310  *
27311  */
27312 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
27313 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_LSB 8
27314 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
27315 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_MSB 31
27316 /* The width in bits of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
27317 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_WIDTH 24
27318 /* The mask used to set the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value. */
27319 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
27320 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value. */
27321 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
27322 /* The reset value of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
27323 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_RESET 0xb31375
27324 /* Extracts the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM field value from a register. */
27325 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
27326 /* Produces a ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value suitable for setting the register. */
27327 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
27328 
27329 #ifndef __ASSEMBLY__
27330 /*
27331  * WARNING: The C register and register group struct declarations are provided for
27332  * convenience and illustrative purposes. They should, however, be used with
27333  * caution as the C language standard provides no guarantees about the alignment or
27334  * atomicity of device memory accesses. The recommended practice for coding device
27335  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27336  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27337  * alt_write_dword() functions for 64 bit registers.
27338  *
27339  * The struct declaration for register ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID.
27340  */
27341 struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_s
27342 {
27343  const volatile uint32_t CORETYPEID : 8; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID */
27344  const volatile uint32_t CORECHECKSUM : 24; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM */
27345 };
27346 
27347 /* The typedef declaration for register ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID. */
27348 typedef struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_s ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_t;
27349 #endif /* __ASSEMBLY__ */
27350 
27351 /* The reset value of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID register. */
27352 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_RESET 0xb3137504
27353 /* The byte offset of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID register from the beginning of the component. */
27354 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_OFST 0x0
27355 
27356 /*
27357  * Register : fpga2sdram0_axi64_I_main_QosGenerator_Id_RevisionId
27358  *
27359  * Register Layout
27360  *
27361  * Bits | Access | Reset | Description
27362  * :-------|:-------|:------|:----------------------------------------------------------------------------------------
27363  * [7:0] | R | 0x0 | ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID
27364  * [31:8] | R | 0x148 | ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID
27365  *
27366  */
27367 /*
27368  * Field : USERID
27369  *
27370  * Field containing a user defined value, not used anywhere inside the IP itself.
27371  *
27372  * Field Access Macros:
27373  *
27374  */
27375 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
27376 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_LSB 0
27377 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
27378 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_MSB 7
27379 /* The width in bits of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
27380 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_WIDTH 8
27381 /* The mask used to set the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value. */
27382 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET_MSK 0x000000ff
27383 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value. */
27384 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
27385 /* The reset value of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
27386 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_RESET 0x0
27387 /* Extracts the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID field value from a register. */
27388 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
27389 /* Produces a ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value suitable for setting the register. */
27390 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
27391 
27392 /*
27393  * Field : FLEXNOCID
27394  *
27395  * Field containing the build revision of the software used to generate the IP HDL
27396  * code.
27397  *
27398  * Field Access Macros:
27399  *
27400  */
27401 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
27402 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_LSB 8
27403 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
27404 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_MSB 31
27405 /* The width in bits of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
27406 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_WIDTH 24
27407 /* The mask used to set the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value. */
27408 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
27409 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value. */
27410 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
27411 /* The reset value of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
27412 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_RESET 0x148
27413 /* Extracts the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID field value from a register. */
27414 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
27415 /* Produces a ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value suitable for setting the register. */
27416 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
27417 
27418 #ifndef __ASSEMBLY__
27419 /*
27420  * WARNING: The C register and register group struct declarations are provided for
27421  * convenience and illustrative purposes. They should, however, be used with
27422  * caution as the C language standard provides no guarantees about the alignment or
27423  * atomicity of device memory accesses. The recommended practice for coding device
27424  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27425  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27426  * alt_write_dword() functions for 64 bit registers.
27427  *
27428  * The struct declaration for register ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID.
27429  */
27430 struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_s
27431 {
27432  const volatile uint32_t USERID : 8; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID */
27433  const volatile uint32_t FLEXNOCID : 24; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID */
27434 };
27435 
27436 /* The typedef declaration for register ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID. */
27437 typedef struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_s ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_t;
27438 #endif /* __ASSEMBLY__ */
27439 
27440 /* The reset value of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID register. */
27441 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_RESET 0x00014800
27442 /* The byte offset of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID register from the beginning of the component. */
27443 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_OFST 0x4
27444 
27445 /*
27446  * Register : fpga2sdram0_axi64_I_main_QosGenerator_Priority
27447  *
27448  * Priority register.
27449  *
27450  * Register Layout
27451  *
27452  * Bits | Access | Reset | Description
27453  * :--------|:-------|:--------|:------------------------------------------------------------------------------
27454  * [1:0] | RW | 0x0 | ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0
27455  * [7:2] | ??? | Unknown | *UNDEFINED*
27456  * [9:8] | RW | 0x2 | ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1
27457  * [30:10] | ??? | Unknown | *UNDEFINED*
27458  * [31] | R | 0x1 | ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK
27459  *
27460  */
27461 /*
27462  * Field : P0
27463  *
27464  * In Programmable or Bandwidth Limiter mode, the priority level for write
27465  * transactions. In Bandwidth Regulator mode, the priority level when the used
27466  * throughput is above the threshold. In Bandwidth Regulator mode, P0 should have a
27467  * value equal or lower than P1.
27468  *
27469  * Field Access Macros:
27470  *
27471  */
27472 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
27473 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_LSB 0
27474 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
27475 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_MSB 1
27476 /* The width in bits of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
27477 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_WIDTH 2
27478 /* The mask used to set the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value. */
27479 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET_MSK 0x00000003
27480 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value. */
27481 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_CLR_MSK 0xfffffffc
27482 /* The reset value of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
27483 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_RESET 0x0
27484 /* Extracts the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 field value from a register. */
27485 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_GET(value) (((value) & 0x00000003) >> 0)
27486 /* Produces a ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value suitable for setting the register. */
27487 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET(value) (((value) << 0) & 0x00000003)
27488 
27489 /*
27490  * Field : P1
27491  *
27492  * In Programmable or Bandwidth Limiter mode, the priority level for read
27493  * transactions. In Bandwidth regulator mode, the priority level when the used
27494  * throughput is below the threshold. In Bandwidth Regulator mode, P1 should have a
27495  * value equal or greater than P0.
27496  *
27497  * Field Access Macros:
27498  *
27499  */
27500 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
27501 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_LSB 8
27502 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
27503 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_MSB 9
27504 /* The width in bits of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
27505 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_WIDTH 2
27506 /* The mask used to set the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value. */
27507 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET_MSK 0x00000300
27508 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value. */
27509 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_CLR_MSK 0xfffffcff
27510 /* The reset value of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
27511 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_RESET 0x2
27512 /* Extracts the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 field value from a register. */
27513 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_GET(value) (((value) & 0x00000300) >> 8)
27514 /* Produces a ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value suitable for setting the register. */
27515 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET(value) (((value) << 8) & 0x00000300)
27516 
27517 /*
27518  * Field : MARK
27519  *
27520  * Backward compatibility marker when 0.
27521  *
27522  * Field Access Macros:
27523  *
27524  */
27525 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
27526 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_LSB 31
27527 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
27528 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_MSB 31
27529 /* The width in bits of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
27530 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_WIDTH 1
27531 /* The mask used to set the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value. */
27532 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET_MSK 0x80000000
27533 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value. */
27534 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_CLR_MSK 0x7fffffff
27535 /* The reset value of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
27536 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_RESET 0x1
27537 /* Extracts the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK field value from a register. */
27538 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_GET(value) (((value) & 0x80000000) >> 31)
27539 /* Produces a ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value suitable for setting the register. */
27540 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET(value) (((value) << 31) & 0x80000000)
27541 
27542 #ifndef __ASSEMBLY__
27543 /*
27544  * WARNING: The C register and register group struct declarations are provided for
27545  * convenience and illustrative purposes. They should, however, be used with
27546  * caution as the C language standard provides no guarantees about the alignment or
27547  * atomicity of device memory accesses. The recommended practice for coding device
27548  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27549  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27550  * alt_write_dword() functions for 64 bit registers.
27551  *
27552  * The struct declaration for register ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY.
27553  */
27554 struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_s
27555 {
27556  volatile uint32_t P0 : 2; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 */
27557  uint32_t : 6; /* *UNDEFINED* */
27558  volatile uint32_t P1 : 2; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 */
27559  uint32_t : 21; /* *UNDEFINED* */
27560  const volatile uint32_t MARK : 1; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK */
27561 };
27562 
27563 /* The typedef declaration for register ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY. */
27564 typedef struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_s ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_t;
27565 #endif /* __ASSEMBLY__ */
27566 
27567 /* The reset value of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY register. */
27568 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_RESET 0x80000200
27569 /* The byte offset of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY register from the beginning of the component. */
27570 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_OFST 0x8
27571 
27572 /*
27573  * Register : fpga2sdram0_axi64_I_main_QosGenerator_Mode
27574  *
27575  * Register Layout
27576  *
27577  * Bits | Access | Reset | Description
27578  * :-------|:-------|:--------|:--------------------------------------------------------------------------
27579  * [1:0] | RW | 0x3 | ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE
27580  * [31:2] | ??? | Unknown | *UNDEFINED*
27581  *
27582  */
27583 /*
27584  * Field : MODE
27585  *
27586  * 0 = Programmable mode: a programmed priority is assigned to each read or write,
27587  * 1 = Bandwidth Limiter Mode: a hard limit restricts throughput, 2 = Bypass mode:
27588  * (<See SoC-specific QoS generator documentation>), 3 = Bandwidth Regulator mode:
27589  * priority decreases when throughput exceeds a threshold.
27590  *
27591  * Field Access Macros:
27592  *
27593  */
27594 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
27595 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_LSB 0
27596 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
27597 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_MSB 1
27598 /* The width in bits of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
27599 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_WIDTH 2
27600 /* The mask used to set the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE register field value. */
27601 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_SET_MSK 0x00000003
27602 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE register field value. */
27603 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_CLR_MSK 0xfffffffc
27604 /* The reset value of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
27605 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_RESET 0x3
27606 /* Extracts the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE field value from a register. */
27607 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_GET(value) (((value) & 0x00000003) >> 0)
27608 /* Produces a ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE register field value suitable for setting the register. */
27609 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_SET(value) (((value) << 0) & 0x00000003)
27610 
27611 #ifndef __ASSEMBLY__
27612 /*
27613  * WARNING: The C register and register group struct declarations are provided for
27614  * convenience and illustrative purposes. They should, however, be used with
27615  * caution as the C language standard provides no guarantees about the alignment or
27616  * atomicity of device memory accesses. The recommended practice for coding device
27617  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27618  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27619  * alt_write_dword() functions for 64 bit registers.
27620  *
27621  * The struct declaration for register ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE.
27622  */
27623 struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_s
27624 {
27625  volatile uint32_t MODE : 2; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE */
27626  uint32_t : 30; /* *UNDEFINED* */
27627 };
27628 
27629 /* The typedef declaration for register ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE. */
27630 typedef struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_s ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_t;
27631 #endif /* __ASSEMBLY__ */
27632 
27633 /* The reset value of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE register. */
27634 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_RESET 0x00000003
27635 /* The byte offset of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE register from the beginning of the component. */
27636 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_OFST 0xc
27637 
27638 /*
27639  * Register : fpga2sdram0_axi64_I_main_QosGenerator_Bandwidth
27640  *
27641  * Register Layout
27642  *
27643  * Bits | Access | Reset | Description
27644  * :--------|:-------|:--------|:------------------------------------------------------------------------------------
27645  * [11:0] | RW | 0x780 | ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH
27646  * [31:12] | ??? | Unknown | *UNDEFINED*
27647  *
27648  */
27649 /*
27650  * Field : BANDWIDTH
27651  *
27652  * In Bandwidth Limiter or Bandwidth Regulator mode, the bandwidth threshold in
27653  * units of 1/256th bytes per cycle. For example, 80 MBps on a 250 MHz interface is
27654  * value 0x0052.
27655  *
27656  * Field Access Macros:
27657  *
27658  */
27659 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
27660 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_LSB 0
27661 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
27662 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MSB 11
27663 /* The width in bits of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
27664 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_WIDTH 12
27665 /* The mask used to set the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value. */
27666 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET_MSK 0x00000fff
27667 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value. */
27668 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_CLR_MSK 0xfffff000
27669 /* The reset value of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
27670 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_RESET 0x780
27671 /* Extracts the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH field value from a register. */
27672 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_GET(value) (((value) & 0x00000fff) >> 0)
27673 /* Produces a ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value suitable for setting the register. */
27674 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x00000fff)
27675 
27676 #ifndef __ASSEMBLY__
27677 /*
27678  * WARNING: The C register and register group struct declarations are provided for
27679  * convenience and illustrative purposes. They should, however, be used with
27680  * caution as the C language standard provides no guarantees about the alignment or
27681  * atomicity of device memory accesses. The recommended practice for coding device
27682  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27683  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27684  * alt_write_dword() functions for 64 bit registers.
27685  *
27686  * The struct declaration for register ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH.
27687  */
27688 struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_s
27689 {
27690  volatile uint32_t BANDWIDTH : 12; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH */
27691  uint32_t : 20; /* *UNDEFINED* */
27692 };
27693 
27694 /* The typedef declaration for register ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH. */
27695 typedef struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_s ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_t;
27696 #endif /* __ASSEMBLY__ */
27697 
27698 /* The reset value of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH register. */
27699 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_RESET 0x00000780
27700 /* The byte offset of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH register from the beginning of the component. */
27701 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_OFST 0x10
27702 
27703 /*
27704  * Register : fpga2sdram0_axi64_I_main_QosGenerator_Saturation
27705  *
27706  * Register Layout
27707  *
27708  * Bits | Access | Reset | Description
27709  * :--------|:-------|:--------|:--------------------------------------------------------------------------------------
27710  * [9:0] | RW | 0x8 | ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION
27711  * [31:10] | ??? | Unknown | *UNDEFINED*
27712  *
27713  */
27714 /*
27715  * Field : SATURATION
27716  *
27717  * In Bandwidth Limiter or Bandwidth Regulator mode, the maximum data count value,
27718  * in units of 16 bytes. This determines the window of time over which bandwidth is
27719  * measured. For example, to measure bandwidth within a 1000 cycle window on a
27720  * 64-bit interface is value 0x1F4.
27721  *
27722  * Field Access Macros:
27723  *
27724  */
27725 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
27726 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_LSB 0
27727 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
27728 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_MSB 9
27729 /* The width in bits of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
27730 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_WIDTH 10
27731 /* The mask used to set the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value. */
27732 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET_MSK 0x000003ff
27733 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value. */
27734 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_CLR_MSK 0xfffffc00
27735 /* The reset value of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
27736 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_RESET 0x8
27737 /* Extracts the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION field value from a register. */
27738 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
27739 /* Produces a ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value suitable for setting the register. */
27740 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
27741 
27742 #ifndef __ASSEMBLY__
27743 /*
27744  * WARNING: The C register and register group struct declarations are provided for
27745  * convenience and illustrative purposes. They should, however, be used with
27746  * caution as the C language standard provides no guarantees about the alignment or
27747  * atomicity of device memory accesses. The recommended practice for coding device
27748  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27749  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27750  * alt_write_dword() functions for 64 bit registers.
27751  *
27752  * The struct declaration for register ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION.
27753  */
27754 struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_s
27755 {
27756  volatile uint32_t SATURATION : 10; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION */
27757  uint32_t : 22; /* *UNDEFINED* */
27758 };
27759 
27760 /* The typedef declaration for register ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION. */
27761 typedef struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_s ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_t;
27762 #endif /* __ASSEMBLY__ */
27763 
27764 /* The reset value of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION register. */
27765 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_RESET 0x00000008
27766 /* The byte offset of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION register from the beginning of the component. */
27767 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_OFST 0x14
27768 
27769 /*
27770  * Register : fpga2sdram0_axi64_I_main_QosGenerator_ExtControl
27771  *
27772  * External inputs control.
27773  *
27774  * Register Layout
27775  *
27776  * Bits | Access | Reset | Description
27777  * :-------|:-------|:--------|:---------------------------------------------------------------------------------------
27778  * [0] | RW | 0x0 | ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN
27779  * [1] | RW | 0x0 | ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN
27780  * [2] | RW | 0x0 | ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN
27781  * [31:3] | ??? | Unknown | *UNDEFINED*
27782  *
27783  */
27784 /*
27785  * Field : SOCKETQOSEN
27786  *
27787  * n/a
27788  *
27789  * Field Access Macros:
27790  *
27791  */
27792 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
27793 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_LSB 0
27794 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
27795 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MSB 0
27796 /* The width in bits of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
27797 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_WIDTH 1
27798 /* The mask used to set the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value. */
27799 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET_MSK 0x00000001
27800 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value. */
27801 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_CLR_MSK 0xfffffffe
27802 /* The reset value of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
27803 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_RESET 0x0
27804 /* Extracts the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN field value from a register. */
27805 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
27806 /* Produces a ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value suitable for setting the register. */
27807 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
27808 
27809 /*
27810  * Field : EXTTHREN
27811  *
27812  * n/a
27813  *
27814  * Field Access Macros:
27815  *
27816  */
27817 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
27818 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_LSB 1
27819 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
27820 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_MSB 1
27821 /* The width in bits of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
27822 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_WIDTH 1
27823 /* The mask used to set the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value. */
27824 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET_MSK 0x00000002
27825 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value. */
27826 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_CLR_MSK 0xfffffffd
27827 /* The reset value of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
27828 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_RESET 0x0
27829 /* Extracts the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN field value from a register. */
27830 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
27831 /* Produces a ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value suitable for setting the register. */
27832 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
27833 
27834 /*
27835  * Field : INTCLKEN
27836  *
27837  * n/a
27838  *
27839  * Field Access Macros:
27840  *
27841  */
27842 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
27843 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_LSB 2
27844 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
27845 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_MSB 2
27846 /* The width in bits of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
27847 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_WIDTH 1
27848 /* The mask used to set the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value. */
27849 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET_MSK 0x00000004
27850 /* The mask used to clear the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value. */
27851 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_CLR_MSK 0xfffffffb
27852 /* The reset value of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
27853 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_RESET 0x0
27854 /* Extracts the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN field value from a register. */
27855 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
27856 /* Produces a ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value suitable for setting the register. */
27857 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
27858 
27859 #ifndef __ASSEMBLY__
27860 /*
27861  * WARNING: The C register and register group struct declarations are provided for
27862  * convenience and illustrative purposes. They should, however, be used with
27863  * caution as the C language standard provides no guarantees about the alignment or
27864  * atomicity of device memory accesses. The recommended practice for coding device
27865  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27866  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27867  * alt_write_dword() functions for 64 bit registers.
27868  *
27869  * The struct declaration for register ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL.
27870  */
27871 struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_s
27872 {
27873  volatile uint32_t SOCKETQOSEN : 1; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN */
27874  volatile uint32_t EXTTHREN : 1; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN */
27875  volatile uint32_t INTCLKEN : 1; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN */
27876  uint32_t : 29; /* *UNDEFINED* */
27877 };
27878 
27879 /* The typedef declaration for register ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL. */
27880 typedef struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_s ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_t;
27881 #endif /* __ASSEMBLY__ */
27882 
27883 /* The reset value of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL register. */
27884 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_RESET 0x00000000
27885 /* The byte offset of the ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL register from the beginning of the component. */
27886 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_OFST 0x18
27887 
27888 #ifndef __ASSEMBLY__
27889 /*
27890  * WARNING: The C register and register group struct declarations are provided for
27891  * convenience and illustrative purposes. They should, however, be used with
27892  * caution as the C language standard provides no guarantees about the alignment or
27893  * atomicity of device memory accesses. The recommended practice for coding device
27894  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27895  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27896  * alt_write_dword() functions for 64 bit registers.
27897  *
27898  * The struct declaration for register group ALT_MPFE_F2SDR0_AXI64_QOS.
27899  */
27900 struct ALT_MPFE_F2SDR0_AXI64_QOS_s
27901 {
27902  volatile ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_t fpga2sdram0_axi64_I_main_QosGenerator_Id_CoreId; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID */
27903  volatile ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_t fpga2sdram0_axi64_I_main_QosGenerator_Id_RevisionId; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID */
27904  volatile ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_t fpga2sdram0_axi64_I_main_QosGenerator_Priority; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY */
27905  volatile ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_t fpga2sdram0_axi64_I_main_QosGenerator_Mode; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE */
27906  volatile ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_t fpga2sdram0_axi64_I_main_QosGenerator_Bandwidth; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH */
27907  volatile ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_t fpga2sdram0_axi64_I_main_QosGenerator_Saturation; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION */
27908  volatile ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_t fpga2sdram0_axi64_I_main_QosGenerator_ExtControl; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL */
27909  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
27910 };
27911 
27912 /* The typedef declaration for register group ALT_MPFE_F2SDR0_AXI64_QOS. */
27913 typedef struct ALT_MPFE_F2SDR0_AXI64_QOS_s ALT_MPFE_F2SDR0_AXI64_QOS_t;
27914 /* The struct declaration for the raw register contents of register group ALT_MPFE_F2SDR0_AXI64_QOS. */
27915 struct ALT_MPFE_F2SDR0_AXI64_QOS_raw_s
27916 {
27917  volatile uint32_t fpga2sdram0_axi64_I_main_QosGenerator_Id_CoreId; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID */
27918  volatile uint32_t fpga2sdram0_axi64_I_main_QosGenerator_Id_RevisionId; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID */
27919  volatile uint32_t fpga2sdram0_axi64_I_main_QosGenerator_Priority; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY */
27920  volatile uint32_t fpga2sdram0_axi64_I_main_QosGenerator_Mode; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE */
27921  volatile uint32_t fpga2sdram0_axi64_I_main_QosGenerator_Bandwidth; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH */
27922  volatile uint32_t fpga2sdram0_axi64_I_main_QosGenerator_Saturation; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION */
27923  volatile uint32_t fpga2sdram0_axi64_I_main_QosGenerator_ExtControl; /* ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL */
27924  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
27925 };
27926 
27927 /* The typedef declaration for the raw register contents of register group ALT_MPFE_F2SDR0_AXI64_QOS. */
27928 typedef struct ALT_MPFE_F2SDR0_AXI64_QOS_raw_s ALT_MPFE_F2SDR0_AXI64_QOS_raw_t;
27929 #endif /* __ASSEMBLY__ */
27930 
27931 
27932 /*
27933  * Component : MPFE_F2SDR1_AXI128_QOS
27934  *
27935  */
27936 /*
27937  * Register : fpga2sdram1_axi128_I_main_QosGenerator_Id_CoreId
27938  *
27939  * Register Layout
27940  *
27941  * Bits | Access | Reset | Description
27942  * :-------|:-------|:---------|:-----------------------------------------------------------------------------------------
27943  * [7:0] | R | 0x4 | ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID
27944  * [31:8] | R | 0x98409b | ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM
27945  *
27946  */
27947 /*
27948  * Field : CORETYPEID
27949  *
27950  * Field identifying the type of IP.
27951  *
27952  * Field Access Macros:
27953  *
27954  */
27955 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
27956 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_LSB 0
27957 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
27958 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_MSB 7
27959 /* The width in bits of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
27960 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_WIDTH 8
27961 /* The mask used to set the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value. */
27962 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
27963 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value. */
27964 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
27965 /* The reset value of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
27966 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_RESET 0x4
27967 /* Extracts the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID field value from a register. */
27968 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
27969 /* Produces a ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value suitable for setting the register. */
27970 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
27971 
27972 /*
27973  * Field : CORECHECKSUM
27974  *
27975  * Field containing a checksum of the parameters of the IP.
27976  *
27977  * Field Access Macros:
27978  *
27979  */
27980 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
27981 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_LSB 8
27982 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
27983 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_MSB 31
27984 /* The width in bits of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
27985 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_WIDTH 24
27986 /* The mask used to set the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value. */
27987 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
27988 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value. */
27989 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
27990 /* The reset value of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
27991 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_RESET 0x98409b
27992 /* Extracts the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM field value from a register. */
27993 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
27994 /* Produces a ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value suitable for setting the register. */
27995 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
27996 
27997 #ifndef __ASSEMBLY__
27998 /*
27999  * WARNING: The C register and register group struct declarations are provided for
28000  * convenience and illustrative purposes. They should, however, be used with
28001  * caution as the C language standard provides no guarantees about the alignment or
28002  * atomicity of device memory accesses. The recommended practice for coding device
28003  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
28004  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
28005  * alt_write_dword() functions for 64 bit registers.
28006  *
28007  * The struct declaration for register ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID.
28008  */
28009 struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_s
28010 {
28011  const volatile uint32_t CORETYPEID : 8; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID */
28012  const volatile uint32_t CORECHECKSUM : 24; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM */
28013 };
28014 
28015 /* The typedef declaration for register ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID. */
28016 typedef struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_s ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_t;
28017 #endif /* __ASSEMBLY__ */
28018 
28019 /* The reset value of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID register. */
28020 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_RESET 0x98409b04
28021 /* The byte offset of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID register from the beginning of the component. */
28022 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_OFST 0x0
28023 
28024 /*
28025  * Register : fpga2sdram1_axi128_I_main_QosGenerator_Id_RevisionId
28026  *
28027  * Register Layout
28028  *
28029  * Bits | Access | Reset | Description
28030  * :-------|:-------|:------|:------------------------------------------------------------------------------------------
28031  * [7:0] | R | 0x0 | ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID
28032  * [31:8] | R | 0x148 | ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID
28033  *
28034  */
28035 /*
28036  * Field : USERID
28037  *
28038  * Field containing a user defined value, not used anywhere inside the IP itself.
28039  *
28040  * Field Access Macros:
28041  *
28042  */
28043 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
28044 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_LSB 0
28045 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
28046 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_MSB 7
28047 /* The width in bits of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
28048 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_WIDTH 8
28049 /* The mask used to set the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value. */
28050 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET_MSK 0x000000ff
28051 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value. */
28052 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
28053 /* The reset value of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
28054 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_RESET 0x0
28055 /* Extracts the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID field value from a register. */
28056 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
28057 /* Produces a ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value suitable for setting the register. */
28058 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
28059 
28060 /*
28061  * Field : FLEXNOCID
28062  *
28063  * Field containing the build revision of the software used to generate the IP HDL
28064  * code.
28065  *
28066  * Field Access Macros:
28067  *
28068  */
28069 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
28070 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_LSB 8
28071 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
28072 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_MSB 31
28073 /* The width in bits of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
28074 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_WIDTH 24
28075 /* The mask used to set the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value. */
28076 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
28077 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value. */
28078 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
28079 /* The reset value of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
28080 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_RESET 0x148
28081 /* Extracts the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID field value from a register. */
28082 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
28083 /* Produces a ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value suitable for setting the register. */
28084 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
28085 
28086 #ifndef __ASSEMBLY__
28087 /*
28088  * WARNING: The C register and register group struct declarations are provided for
28089  * convenience and illustrative purposes. They should, however, be used with
28090  * caution as the C language standard provides no guarantees about the alignment or
28091  * atomicity of device memory accesses. The recommended practice for coding device
28092  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
28093  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
28094  * alt_write_dword() functions for 64 bit registers.
28095  *
28096  * The struct declaration for register ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID.
28097  */
28098 struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_s
28099 {
28100  const volatile uint32_t USERID : 8; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID */
28101  const volatile uint32_t FLEXNOCID : 24; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID */
28102 };
28103 
28104 /* The typedef declaration for register ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID. */
28105 typedef struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_s ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_t;
28106 #endif /* __ASSEMBLY__ */
28107 
28108 /* The reset value of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID register. */
28109 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_RESET 0x00014800
28110 /* The byte offset of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID register from the beginning of the component. */
28111 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_OFST 0x4
28112 
28113 /*
28114  * Register : fpga2sdram1_axi128_I_main_QosGenerator_Priority
28115  *
28116  * Priority register.
28117  *
28118  * Register Layout
28119  *
28120  * Bits | Access | Reset | Description
28121  * :--------|:-------|:--------|:--------------------------------------------------------------------------------
28122  * [1:0] | RW | 0x0 | ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0
28123  * [7:2] | ??? | Unknown | *UNDEFINED*
28124  * [9:8] | RW | 0x2 | ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1
28125  * [30:10] | ??? | Unknown | *UNDEFINED*
28126  * [31] | R | 0x1 | ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK
28127  *
28128  */
28129 /*
28130  * Field : P0
28131  *
28132  * In Programmable or Bandwidth Limiter mode, the priority level for write
28133  * transactions. In Bandwidth Regulator mode, the priority level when the used
28134  * throughput is above the threshold. In Bandwidth Regulator mode, P0 should have a
28135  * value equal or lower than P1.
28136  *
28137  * Field Access Macros:
28138  *
28139  */
28140 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
28141 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_LSB 0
28142 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
28143 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_MSB 1
28144 /* The width in bits of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
28145 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_WIDTH 2
28146 /* The mask used to set the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value. */
28147 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET_MSK 0x00000003
28148 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value. */
28149 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_CLR_MSK 0xfffffffc
28150 /* The reset value of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
28151 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_RESET 0x0
28152 /* Extracts the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 field value from a register. */
28153 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_GET(value) (((value) & 0x00000003) >> 0)
28154 /* Produces a ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value suitable for setting the register. */
28155 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET(value) (((value) << 0) & 0x00000003)
28156 
28157 /*
28158  * Field : P1
28159  *
28160  * In Programmable or Bandwidth Limiter mode, the priority level for read
28161  * transactions. In Bandwidth regulator mode, the priority level when the used
28162  * throughput is below the threshold. In Bandwidth Regulator mode, P1 should have a
28163  * value equal or greater than P0.
28164  *
28165  * Field Access Macros:
28166  *
28167  */
28168 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
28169 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_LSB 8
28170 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
28171 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_MSB 9
28172 /* The width in bits of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
28173 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_WIDTH 2
28174 /* The mask used to set the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value. */
28175 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET_MSK 0x00000300
28176 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value. */
28177 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_CLR_MSK 0xfffffcff
28178 /* The reset value of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
28179 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_RESET 0x2
28180 /* Extracts the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 field value from a register. */
28181 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_GET(value) (((value) & 0x00000300) >> 8)
28182 /* Produces a ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value suitable for setting the register. */
28183 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET(value) (((value) << 8) & 0x00000300)
28184 
28185 /*
28186  * Field : MARK
28187  *
28188  * Backward compatibility marker when 0.
28189  *
28190  * Field Access Macros:
28191  *
28192  */
28193 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
28194 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_LSB 31
28195 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
28196 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_MSB 31
28197 /* The width in bits of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
28198 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_WIDTH 1
28199 /* The mask used to set the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value. */
28200 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET_MSK 0x80000000
28201 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value. */
28202 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_CLR_MSK 0x7fffffff
28203 /* The reset value of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
28204 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_RESET 0x1
28205 /* Extracts the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK field value from a register. */
28206 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_GET(value) (((value) & 0x80000000) >> 31)
28207 /* Produces a ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value suitable for setting the register. */
28208 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET(value) (((value) << 31) & 0x80000000)
28209 
28210 #ifndef __ASSEMBLY__
28211 /*
28212  * WARNING: The C register and register group struct declarations are provided for
28213  * convenience and illustrative purposes. They should, however, be used with
28214  * caution as the C language standard provides no guarantees about the alignment or
28215  * atomicity of device memory accesses. The recommended practice for coding device
28216  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
28217  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
28218  * alt_write_dword() functions for 64 bit registers.
28219  *
28220  * The struct declaration for register ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY.
28221  */
28222 struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_s
28223 {
28224  volatile uint32_t P0 : 2; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 */
28225  uint32_t : 6; /* *UNDEFINED* */
28226  volatile uint32_t P1 : 2; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 */
28227  uint32_t : 21; /* *UNDEFINED* */
28228  const volatile uint32_t MARK : 1; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK */
28229 };
28230 
28231 /* The typedef declaration for register ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY. */
28232 typedef struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_s ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_t;
28233 #endif /* __ASSEMBLY__ */
28234 
28235 /* The reset value of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY register. */
28236 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_RESET 0x80000200
28237 /* The byte offset of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY register from the beginning of the component. */
28238 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_OFST 0x8
28239 
28240 /*
28241  * Register : fpga2sdram1_axi128_I_main_QosGenerator_Mode
28242  *
28243  * Register Layout
28244  *
28245  * Bits | Access | Reset | Description
28246  * :-------|:-------|:--------|:----------------------------------------------------------------------------
28247  * [1:0] | RW | 0x3 | ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE
28248  * [31:2] | ??? | Unknown | *UNDEFINED*
28249  *
28250  */
28251 /*
28252  * Field : MODE
28253  *
28254  * 0 = Programmable mode: a programmed priority is assigned to each read or write,
28255  * 1 = Bandwidth Limiter Mode: a hard limit restricts throughput, 2 = Bypass mode:
28256  * (<See SoC-specific QoS generator documentation>), 3 = Bandwidth Regulator mode:
28257  * priority decreases when throughput exceeds a threshold.
28258  *
28259  * Field Access Macros:
28260  *
28261  */
28262 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
28263 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_LSB 0
28264 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
28265 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_MSB 1
28266 /* The width in bits of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
28267 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_WIDTH 2
28268 /* The mask used to set the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE register field value. */
28269 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_SET_MSK 0x00000003
28270 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE register field value. */
28271 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_CLR_MSK 0xfffffffc
28272 /* The reset value of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
28273 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_RESET 0x3
28274 /* Extracts the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE field value from a register. */
28275 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_GET(value) (((value) & 0x00000003) >> 0)
28276 /* Produces a ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE register field value suitable for setting the register. */
28277 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_SET(value) (((value) << 0) & 0x00000003)
28278 
28279 #ifndef __ASSEMBLY__
28280 /*
28281  * WARNING: The C register and register group struct declarations are provided for
28282  * convenience and illustrative purposes. They should, however, be used with
28283  * caution as the C language standard provides no guarantees about the alignment or
28284  * atomicity of device memory accesses. The recommended practice for coding device
28285  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
28286  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
28287  * alt_write_dword() functions for 64 bit registers.
28288  *
28289  * The struct declaration for register ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE.
28290  */
28291 struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_s
28292 {
28293  volatile uint32_t MODE : 2; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE */
28294  uint32_t : 30; /* *UNDEFINED* */
28295 };
28296 
28297 /* The typedef declaration for register ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE. */
28298 typedef struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_s ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_t;
28299 #endif /* __ASSEMBLY__ */
28300 
28301 /* The reset value of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE register. */
28302 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_RESET 0x00000003
28303 /* The byte offset of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE register from the beginning of the component. */
28304 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_OFST 0xc
28305 
28306 /*
28307  * Register : fpga2sdram1_axi128_I_main_QosGenerator_Bandwidth
28308  *
28309  * Register Layout
28310  *
28311  * Bits | Access | Reset | Description
28312  * :--------|:-------|:--------|:--------------------------------------------------------------------------------------
28313  * [12:0] | RW | 0x780 | ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH
28314  * [31:13] | ??? | Unknown | *UNDEFINED*
28315  *
28316  */
28317 /*
28318  * Field : BANDWIDTH
28319  *
28320  * In Bandwidth Limiter or Bandwidth Regulator mode, the bandwidth threshold in
28321  * units of 1/256th bytes per cycle. For example, 80 MBps on a 250 MHz interface is
28322  * value 0x0052.
28323  *
28324  * Field Access Macros:
28325  *
28326  */
28327 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
28328 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_LSB 0
28329 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
28330 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MSB 12
28331 /* The width in bits of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
28332 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_WIDTH 13
28333 /* The mask used to set the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value. */
28334 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET_MSK 0x00001fff
28335 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value. */
28336 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_CLR_MSK 0xffffe000
28337 /* The reset value of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
28338 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_RESET 0x780
28339 /* Extracts the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH field value from a register. */
28340 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_GET(value) (((value) & 0x00001fff) >> 0)
28341 /* Produces a ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value suitable for setting the register. */
28342 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x00001fff)
28343 
28344 #ifndef __ASSEMBLY__
28345 /*
28346  * WARNING: The C register and register group struct declarations are provided for
28347  * convenience and illustrative purposes. They should, however, be used with
28348  * caution as the C language standard provides no guarantees about the alignment or
28349  * atomicity of device memory accesses. The recommended practice for coding device
28350  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
28351  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
28352  * alt_write_dword() functions for 64 bit registers.
28353  *
28354  * The struct declaration for register ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH.
28355  */
28356 struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_s
28357 {
28358  volatile uint32_t BANDWIDTH : 13; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH */
28359  uint32_t : 19; /* *UNDEFINED* */
28360 };
28361 
28362 /* The typedef declaration for register ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH. */
28363 typedef struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_s ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_t;
28364 #endif /* __ASSEMBLY__ */
28365 
28366 /* The reset value of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH register. */
28367 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_RESET 0x00000780
28368 /* The byte offset of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH register from the beginning of the component. */
28369 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_OFST 0x10
28370 
28371 /*
28372  * Register : fpga2sdram1_axi128_I_main_QosGenerator_Saturation
28373  *
28374  * Register Layout
28375  *
28376  * Bits | Access | Reset | Description
28377  * :--------|:-------|:--------|:----------------------------------------------------------------------------------------
28378  * [9:0] | RW | 0x8 | ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION
28379  * [31:10] | ??? | Unknown | *UNDEFINED*
28380  *
28381  */
28382 /*
28383  * Field : SATURATION
28384  *
28385  * In Bandwidth Limiter or Bandwidth Regulator mode, the maximum data count value,
28386  * in units of 16 bytes. This determines the window of time over which bandwidth is
28387  * measured. For example, to measure bandwidth within a 1000 cycle window on a
28388  * 64-bit interface is value 0x1F4.
28389  *
28390  * Field Access Macros:
28391  *
28392  */
28393 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
28394 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_LSB 0
28395 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
28396 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_MSB 9
28397 /* The width in bits of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
28398 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_WIDTH 10
28399 /* The mask used to set the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value. */
28400 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET_MSK 0x000003ff
28401 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value. */
28402 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_CLR_MSK 0xfffffc00
28403 /* The reset value of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
28404 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_RESET 0x8
28405 /* Extracts the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION field value from a register. */
28406 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
28407 /* Produces a ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value suitable for setting the register. */
28408 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
28409 
28410 #ifndef __ASSEMBLY__
28411 /*
28412  * WARNING: The C register and register group struct declarations are provided for
28413  * convenience and illustrative purposes. They should, however, be used with
28414  * caution as the C language standard provides no guarantees about the alignment or
28415  * atomicity of device memory accesses. The recommended practice for coding device
28416  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
28417  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
28418  * alt_write_dword() functions for 64 bit registers.
28419  *
28420  * The struct declaration for register ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION.
28421  */
28422 struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_s
28423 {
28424  volatile uint32_t SATURATION : 10; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION */
28425  uint32_t : 22; /* *UNDEFINED* */
28426 };
28427 
28428 /* The typedef declaration for register ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION. */
28429 typedef struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_s ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_t;
28430 #endif /* __ASSEMBLY__ */
28431 
28432 /* The reset value of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION register. */
28433 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_RESET 0x00000008
28434 /* The byte offset of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION register from the beginning of the component. */
28435 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_OFST 0x14
28436 
28437 /*
28438  * Register : fpga2sdram1_axi128_I_main_QosGenerator_ExtControl
28439  *
28440  * External inputs control.
28441  *
28442  * Register Layout
28443  *
28444  * Bits | Access | Reset | Description
28445  * :-------|:-------|:--------|:-----------------------------------------------------------------------------------------
28446  * [0] | RW | 0x0 | ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN
28447  * [1] | RW | 0x0 | ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN
28448  * [2] | RW | 0x0 | ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN
28449  * [31:3] | ??? | Unknown | *UNDEFINED*
28450  *
28451  */
28452 /*
28453  * Field : SOCKETQOSEN
28454  *
28455  * n/a
28456  *
28457  * Field Access Macros:
28458  *
28459  */
28460 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
28461 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_LSB 0
28462 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
28463 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MSB 0
28464 /* The width in bits of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
28465 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_WIDTH 1
28466 /* The mask used to set the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value. */
28467 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET_MSK 0x00000001
28468 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value. */
28469 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_CLR_MSK 0xfffffffe
28470 /* The reset value of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
28471 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_RESET 0x0
28472 /* Extracts the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN field value from a register. */
28473 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
28474 /* Produces a ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value suitable for setting the register. */
28475 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
28476 
28477 /*
28478  * Field : EXTTHREN
28479  *
28480  * n/a
28481  *
28482  * Field Access Macros:
28483  *
28484  */
28485 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
28486 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_LSB 1
28487 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
28488 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_MSB 1
28489 /* The width in bits of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
28490 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_WIDTH 1
28491 /* The mask used to set the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value. */
28492 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET_MSK 0x00000002
28493 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value. */
28494 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_CLR_MSK 0xfffffffd
28495 /* The reset value of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
28496 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_RESET 0x0
28497 /* Extracts the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN field value from a register. */
28498 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
28499 /* Produces a ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value suitable for setting the register. */
28500 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
28501 
28502 /*
28503  * Field : INTCLKEN
28504  *
28505  * n/a
28506  *
28507  * Field Access Macros:
28508  *
28509  */
28510 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
28511 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_LSB 2
28512 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
28513 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_MSB 2
28514 /* The width in bits of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
28515 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_WIDTH 1
28516 /* The mask used to set the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value. */
28517 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET_MSK 0x00000004
28518 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value. */
28519 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_CLR_MSK 0xfffffffb
28520 /* The reset value of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
28521 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_RESET 0x0
28522 /* Extracts the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN field value from a register. */
28523 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
28524 /* Produces a ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value suitable for setting the register. */
28525 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
28526 
28527 #ifndef __ASSEMBLY__
28528 /*
28529  * WARNING: The C register and register group struct declarations are provided for
28530  * convenience and illustrative purposes. They should, however, be used with
28531  * caution as the C language standard provides no guarantees about the alignment or
28532  * atomicity of device memory accesses. The recommended practice for coding device
28533  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
28534  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
28535  * alt_write_dword() functions for 64 bit registers.
28536  *
28537  * The struct declaration for register ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL.
28538  */
28539 struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_s
28540 {
28541  volatile uint32_t SOCKETQOSEN : 1; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN */
28542  volatile uint32_t EXTTHREN : 1; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN */
28543  volatile uint32_t INTCLKEN : 1; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN */
28544  uint32_t : 29; /* *UNDEFINED* */
28545 };
28546 
28547 /* The typedef declaration for register ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL. */
28548 typedef struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_s ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_t;
28549 #endif /* __ASSEMBLY__ */
28550 
28551 /* The reset value of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL register. */
28552 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_RESET 0x00000000
28553 /* The byte offset of the ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL register from the beginning of the component. */
28554 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_OFST 0x18
28555 
28556 #ifndef __ASSEMBLY__
28557 /*
28558  * WARNING: The C register and register group struct declarations are provided for
28559  * convenience and illustrative purposes. They should, however, be used with
28560  * caution as the C language standard provides no guarantees about the alignment or
28561  * atomicity of device memory accesses. The recommended practice for coding device
28562  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
28563  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
28564  * alt_write_dword() functions for 64 bit registers.
28565  *
28566  * The struct declaration for register group ALT_MPFE_F2SDR1_AXI128_QOS.
28567  */
28568 struct ALT_MPFE_F2SDR1_AXI128_QOS_s
28569 {
28570  volatile ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_t fpga2sdram1_axi128_I_main_QosGenerator_Id_CoreId; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID */
28571  volatile ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_t fpga2sdram1_axi128_I_main_QosGenerator_Id_RevisionId; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID */
28572  volatile ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_t fpga2sdram1_axi128_I_main_QosGenerator_Priority; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY */
28573  volatile ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_t fpga2sdram1_axi128_I_main_QosGenerator_Mode; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE */
28574  volatile ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_t fpga2sdram1_axi128_I_main_QosGenerator_Bandwidth; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH */
28575  volatile ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_t fpga2sdram1_axi128_I_main_QosGenerator_Saturation; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION */
28576  volatile ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_t fpga2sdram1_axi128_I_main_QosGenerator_ExtControl; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL */
28577  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
28578 };
28579 
28580 /* The typedef declaration for register group ALT_MPFE_F2SDR1_AXI128_QOS. */
28581 typedef struct ALT_MPFE_F2SDR1_AXI128_QOS_s ALT_MPFE_F2SDR1_AXI128_QOS_t;
28582 /* The struct declaration for the raw register contents of register group ALT_MPFE_F2SDR1_AXI128_QOS. */
28583 struct ALT_MPFE_F2SDR1_AXI128_QOS_raw_s
28584 {
28585  volatile uint32_t fpga2sdram1_axi128_I_main_QosGenerator_Id_CoreId; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID */
28586  volatile uint32_t fpga2sdram1_axi128_I_main_QosGenerator_Id_RevisionId; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID */
28587  volatile uint32_t fpga2sdram1_axi128_I_main_QosGenerator_Priority; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY */
28588  volatile uint32_t fpga2sdram1_axi128_I_main_QosGenerator_Mode; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE */
28589  volatile uint32_t fpga2sdram1_axi128_I_main_QosGenerator_Bandwidth; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH */
28590  volatile uint32_t fpga2sdram1_axi128_I_main_QosGenerator_Saturation; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION */
28591  volatile uint32_t fpga2sdram1_axi128_I_main_QosGenerator_ExtControl; /* ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL */
28592  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
28593 };
28594 
28595 /* The typedef declaration for the raw register contents of register group ALT_MPFE_F2SDR1_AXI128_QOS. */
28596 typedef struct ALT_MPFE_F2SDR1_AXI128_QOS_raw_s ALT_MPFE_F2SDR1_AXI128_QOS_raw_t;
28597 #endif /* __ASSEMBLY__ */
28598 
28599 
28600 /*
28601  * Component : MPFE_F2SDR1_AXI32_QOS
28602  *
28603  */
28604 /*
28605  * Register : fpga2sdram1_axi32_I_main_QosGenerator_Id_CoreId
28606  *
28607  * Register Layout
28608  *
28609  * Bits | Access | Reset | Description
28610  * :-------|:-------|:---------|:---------------------------------------------------------------------------------------
28611  * [7:0] | R | 0x4 | ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID
28612  * [31:8] | R | 0x163445 | ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM
28613  *
28614  */
28615 /*
28616  * Field : CORETYPEID
28617  *
28618  * Field identifying the type of IP.
28619  *
28620  * Field Access Macros:
28621  *
28622  */
28623 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
28624 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_LSB 0
28625 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
28626 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_MSB 7
28627 /* The width in bits of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
28628 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_WIDTH 8
28629 /* The mask used to set the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value. */
28630 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
28631 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value. */
28632 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
28633 /* The reset value of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
28634 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_RESET 0x4
28635 /* Extracts the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID field value from a register. */
28636 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
28637 /* Produces a ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value suitable for setting the register. */
28638 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
28639 
28640 /*
28641  * Field : CORECHECKSUM
28642  *
28643  * Field containing a checksum of the parameters of the IP.
28644  *
28645  * Field Access Macros:
28646  *
28647  */
28648 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
28649 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_LSB 8
28650 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
28651 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_MSB 31
28652 /* The width in bits of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
28653 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_WIDTH 24
28654 /* The mask used to set the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value. */
28655 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
28656 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value. */
28657 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
28658 /* The reset value of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
28659 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_RESET 0x163445
28660 /* Extracts the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM field value from a register. */
28661 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
28662 /* Produces a ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value suitable for setting the register. */
28663 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
28664 
28665 #ifndef __ASSEMBLY__
28666 /*
28667  * WARNING: The C register and register group struct declarations are provided for
28668  * convenience and illustrative purposes. They should, however, be used with
28669  * caution as the C language standard provides no guarantees about the alignment or
28670  * atomicity of device memory accesses. The recommended practice for coding device
28671  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
28672  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
28673  * alt_write_dword() functions for 64 bit registers.
28674  *
28675  * The struct declaration for register ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID.
28676  */
28677 struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_s
28678 {
28679  const volatile uint32_t CORETYPEID : 8; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID */
28680  const volatile uint32_t CORECHECKSUM : 24; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM */
28681 };
28682 
28683 /* The typedef declaration for register ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID. */
28684 typedef struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_s ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_t;
28685 #endif /* __ASSEMBLY__ */
28686 
28687 /* The reset value of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID register. */
28688 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_RESET 0x16344504
28689 /* The byte offset of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID register from the beginning of the component. */
28690 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_OFST 0x0
28691 
28692 /*
28693  * Register : fpga2sdram1_axi32_I_main_QosGenerator_Id_RevisionId
28694  *
28695  * Register Layout
28696  *
28697  * Bits | Access | Reset | Description
28698  * :-------|:-------|:------|:----------------------------------------------------------------------------------------
28699  * [7:0] | R | 0x0 | ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID
28700  * [31:8] | R | 0x148 | ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID
28701  *
28702  */
28703 /*
28704  * Field : USERID
28705  *
28706  * Field containing a user defined value, not used anywhere inside the IP itself.
28707  *
28708  * Field Access Macros:
28709  *
28710  */
28711 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
28712 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_LSB 0
28713 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
28714 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_MSB 7
28715 /* The width in bits of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
28716 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_WIDTH 8
28717 /* The mask used to set the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value. */
28718 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET_MSK 0x000000ff
28719 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value. */
28720 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
28721 /* The reset value of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
28722 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_RESET 0x0
28723 /* Extracts the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID field value from a register. */
28724 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
28725 /* Produces a ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value suitable for setting the register. */
28726 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
28727 
28728 /*
28729  * Field : FLEXNOCID
28730  *
28731  * Field containing the build revision of the software used to generate the IP HDL
28732  * code.
28733  *
28734  * Field Access Macros:
28735  *
28736  */
28737 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
28738 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_LSB 8
28739 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
28740 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_MSB 31
28741 /* The width in bits of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
28742 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_WIDTH 24
28743 /* The mask used to set the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value. */
28744 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
28745 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value. */
28746 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
28747 /* The reset value of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
28748 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_RESET 0x148
28749 /* Extracts the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID field value from a register. */
28750 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
28751 /* Produces a ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value suitable for setting the register. */
28752 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
28753 
28754 #ifndef __ASSEMBLY__
28755 /*
28756  * WARNING: The C register and register group struct declarations are provided for
28757  * convenience and illustrative purposes. They should, however, be used with
28758  * caution as the C language standard provides no guarantees about the alignment or
28759  * atomicity of device memory accesses. The recommended practice for coding device
28760  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
28761  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
28762  * alt_write_dword() functions for 64 bit registers.
28763  *
28764  * The struct declaration for register ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID.
28765  */
28766 struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_s
28767 {
28768  const volatile uint32_t USERID : 8; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID */
28769  const volatile uint32_t FLEXNOCID : 24; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID */
28770 };
28771 
28772 /* The typedef declaration for register ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID. */
28773 typedef struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_s ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_t;
28774 #endif /* __ASSEMBLY__ */
28775 
28776 /* The reset value of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID register. */
28777 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_RESET 0x00014800
28778 /* The byte offset of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID register from the beginning of the component. */
28779 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_OFST 0x4
28780 
28781 /*
28782  * Register : fpga2sdram1_axi32_I_main_QosGenerator_Priority
28783  *
28784  * Priority register.
28785  *
28786  * Register Layout
28787  *
28788  * Bits | Access | Reset | Description
28789  * :--------|:-------|:--------|:------------------------------------------------------------------------------
28790  * [1:0] | RW | 0x0 | ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0
28791  * [7:2] | ??? | Unknown | *UNDEFINED*
28792  * [9:8] | RW | 0x2 | ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1
28793  * [30:10] | ??? | Unknown | *UNDEFINED*
28794  * [31] | R | 0x1 | ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK
28795  *
28796  */
28797 /*
28798  * Field : P0
28799  *
28800  * In Programmable or Bandwidth Limiter mode, the priority level for write
28801  * transactions. In Bandwidth Regulator mode, the priority level when the used
28802  * throughput is above the threshold. In Bandwidth Regulator mode, P0 should have a
28803  * value equal or lower than P1.
28804  *
28805  * Field Access Macros:
28806  *
28807  */
28808 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
28809 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_LSB 0
28810 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
28811 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_MSB 1
28812 /* The width in bits of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
28813 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_WIDTH 2
28814 /* The mask used to set the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value. */
28815 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET_MSK 0x00000003
28816 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value. */
28817 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_CLR_MSK 0xfffffffc
28818 /* The reset value of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
28819 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_RESET 0x0
28820 /* Extracts the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 field value from a register. */
28821 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_GET(value) (((value) & 0x00000003) >> 0)
28822 /* Produces a ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value suitable for setting the register. */
28823 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET(value) (((value) << 0) & 0x00000003)
28824 
28825 /*
28826  * Field : P1
28827  *
28828  * In Programmable or Bandwidth Limiter mode, the priority level for read
28829  * transactions. In Bandwidth regulator mode, the priority level when the used
28830  * throughput is below the threshold. In Bandwidth Regulator mode, P1 should have a
28831  * value equal or greater than P0.
28832  *
28833  * Field Access Macros:
28834  *
28835  */
28836 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
28837 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_LSB 8
28838 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
28839 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_MSB 9
28840 /* The width in bits of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
28841 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_WIDTH 2
28842 /* The mask used to set the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value. */
28843 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET_MSK 0x00000300
28844 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value. */
28845 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_CLR_MSK 0xfffffcff
28846 /* The reset value of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
28847 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_RESET 0x2
28848 /* Extracts the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 field value from a register. */
28849 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_GET(value) (((value) & 0x00000300) >> 8)
28850 /* Produces a ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value suitable for setting the register. */
28851 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET(value) (((value) << 8) & 0x00000300)
28852 
28853 /*
28854  * Field : MARK
28855  *
28856  * Backward compatibility marker when 0.
28857  *
28858  * Field Access Macros:
28859  *
28860  */
28861 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
28862 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_LSB 31
28863 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
28864 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_MSB 31
28865 /* The width in bits of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
28866 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_WIDTH 1
28867 /* The mask used to set the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value. */
28868 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET_MSK 0x80000000
28869 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value. */
28870 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_CLR_MSK 0x7fffffff
28871 /* The reset value of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
28872 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_RESET 0x1
28873 /* Extracts the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK field value from a register. */
28874 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_GET(value) (((value) & 0x80000000) >> 31)
28875 /* Produces a ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value suitable for setting the register. */
28876 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET(value) (((value) << 31) & 0x80000000)
28877 
28878 #ifndef __ASSEMBLY__
28879 /*
28880  * WARNING: The C register and register group struct declarations are provided for
28881  * convenience and illustrative purposes. They should, however, be used with
28882  * caution as the C language standard provides no guarantees about the alignment or
28883  * atomicity of device memory accesses. The recommended practice for coding device
28884  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
28885  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
28886  * alt_write_dword() functions for 64 bit registers.
28887  *
28888  * The struct declaration for register ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY.
28889  */
28890 struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_s
28891 {
28892  volatile uint32_t P0 : 2; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 */
28893  uint32_t : 6; /* *UNDEFINED* */
28894  volatile uint32_t P1 : 2; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 */
28895  uint32_t : 21; /* *UNDEFINED* */
28896  const volatile uint32_t MARK : 1; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK */
28897 };
28898 
28899 /* The typedef declaration for register ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY. */
28900 typedef struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_s ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_t;
28901 #endif /* __ASSEMBLY__ */
28902 
28903 /* The reset value of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY register. */
28904 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_RESET 0x80000200
28905 /* The byte offset of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY register from the beginning of the component. */
28906 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_OFST 0x8
28907 
28908 /*
28909  * Register : fpga2sdram1_axi32_I_main_QosGenerator_Mode
28910  *
28911  * Register Layout
28912  *
28913  * Bits | Access | Reset | Description
28914  * :-------|:-------|:--------|:--------------------------------------------------------------------------
28915  * [1:0] | RW | 0x3 | ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE
28916  * [31:2] | ??? | Unknown | *UNDEFINED*
28917  *
28918  */
28919 /*
28920  * Field : MODE
28921  *
28922  * 0 = Programmable mode: a programmed priority is assigned to each read or write,
28923  * 1 = Bandwidth Limiter Mode: a hard limit restricts throughput, 2 = Bypass mode:
28924  * (<See SoC-specific QoS generator documentation>), 3 = Bandwidth Regulator mode:
28925  * priority decreases when throughput exceeds a threshold.
28926  *
28927  * Field Access Macros:
28928  *
28929  */
28930 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
28931 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_LSB 0
28932 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
28933 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_MSB 1
28934 /* The width in bits of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
28935 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_WIDTH 2
28936 /* The mask used to set the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE register field value. */
28937 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_SET_MSK 0x00000003
28938 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE register field value. */
28939 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_CLR_MSK 0xfffffffc
28940 /* The reset value of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
28941 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_RESET 0x3
28942 /* Extracts the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE field value from a register. */
28943 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_GET(value) (((value) & 0x00000003) >> 0)
28944 /* Produces a ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE register field value suitable for setting the register. */
28945 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_SET(value) (((value) << 0) & 0x00000003)
28946 
28947 #ifndef __ASSEMBLY__
28948 /*
28949  * WARNING: The C register and register group struct declarations are provided for
28950  * convenience and illustrative purposes. They should, however, be used with
28951  * caution as the C language standard provides no guarantees about the alignment or
28952  * atomicity of device memory accesses. The recommended practice for coding device
28953  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
28954  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
28955  * alt_write_dword() functions for 64 bit registers.
28956  *
28957  * The struct declaration for register ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE.
28958  */
28959 struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_s
28960 {
28961  volatile uint32_t MODE : 2; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE */
28962  uint32_t : 30; /* *UNDEFINED* */
28963 };
28964 
28965 /* The typedef declaration for register ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE. */
28966 typedef struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_s ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_t;
28967 #endif /* __ASSEMBLY__ */
28968 
28969 /* The reset value of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE register. */
28970 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_RESET 0x00000003
28971 /* The byte offset of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE register from the beginning of the component. */
28972 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_OFST 0xc
28973 
28974 /*
28975  * Register : fpga2sdram1_axi32_I_main_QosGenerator_Bandwidth
28976  *
28977  * Register Layout
28978  *
28979  * Bits | Access | Reset | Description
28980  * :--------|:-------|:--------|:------------------------------------------------------------------------------------
28981  * [10:0] | RW | 0x280 | ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH
28982  * [31:11] | ??? | Unknown | *UNDEFINED*
28983  *
28984  */
28985 /*
28986  * Field : BANDWIDTH
28987  *
28988  * In Bandwidth Limiter or Bandwidth Regulator mode, the bandwidth threshold in
28989  * units of 1/256th bytes per cycle. For example, 80 MBps on a 250 MHz interface is
28990  * value 0x0052.
28991  *
28992  * Field Access Macros:
28993  *
28994  */
28995 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
28996 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_LSB 0
28997 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
28998 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MSB 10
28999 /* The width in bits of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
29000 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_WIDTH 11
29001 /* The mask used to set the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value. */
29002 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET_MSK 0x000007ff
29003 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value. */
29004 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_CLR_MSK 0xfffff800
29005 /* The reset value of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
29006 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_RESET 0x280
29007 /* Extracts the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH field value from a register. */
29008 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_GET(value) (((value) & 0x000007ff) >> 0)
29009 /* Produces a ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value suitable for setting the register. */
29010 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x000007ff)
29011 
29012 #ifndef __ASSEMBLY__
29013 /*
29014  * WARNING: The C register and register group struct declarations are provided for
29015  * convenience and illustrative purposes. They should, however, be used with
29016  * caution as the C language standard provides no guarantees about the alignment or
29017  * atomicity of device memory accesses. The recommended practice for coding device
29018  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29019  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29020  * alt_write_dword() functions for 64 bit registers.
29021  *
29022  * The struct declaration for register ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH.
29023  */
29024 struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_s
29025 {
29026  volatile uint32_t BANDWIDTH : 11; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH */
29027  uint32_t : 21; /* *UNDEFINED* */
29028 };
29029 
29030 /* The typedef declaration for register ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH. */
29031 typedef struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_s ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_t;
29032 #endif /* __ASSEMBLY__ */
29033 
29034 /* The reset value of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH register. */
29035 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_RESET 0x00000280
29036 /* The byte offset of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH register from the beginning of the component. */
29037 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_OFST 0x10
29038 
29039 /*
29040  * Register : fpga2sdram1_axi32_I_main_QosGenerator_Saturation
29041  *
29042  * Register Layout
29043  *
29044  * Bits | Access | Reset | Description
29045  * :--------|:-------|:--------|:--------------------------------------------------------------------------------------
29046  * [9:0] | RW | 0x8 | ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION
29047  * [31:10] | ??? | Unknown | *UNDEFINED*
29048  *
29049  */
29050 /*
29051  * Field : SATURATION
29052  *
29053  * In Bandwidth Limiter or Bandwidth Regulator mode, the maximum data count value,
29054  * in units of 16 bytes. This determines the window of time over which bandwidth is
29055  * measured. For example, to measure bandwidth within a 1000 cycle window on a
29056  * 64-bit interface is value 0x1F4.
29057  *
29058  * Field Access Macros:
29059  *
29060  */
29061 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
29062 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_LSB 0
29063 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
29064 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_MSB 9
29065 /* The width in bits of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
29066 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_WIDTH 10
29067 /* The mask used to set the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value. */
29068 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET_MSK 0x000003ff
29069 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value. */
29070 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_CLR_MSK 0xfffffc00
29071 /* The reset value of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
29072 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_RESET 0x8
29073 /* Extracts the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION field value from a register. */
29074 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
29075 /* Produces a ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value suitable for setting the register. */
29076 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
29077 
29078 #ifndef __ASSEMBLY__
29079 /*
29080  * WARNING: The C register and register group struct declarations are provided for
29081  * convenience and illustrative purposes. They should, however, be used with
29082  * caution as the C language standard provides no guarantees about the alignment or
29083  * atomicity of device memory accesses. The recommended practice for coding device
29084  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29085  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29086  * alt_write_dword() functions for 64 bit registers.
29087  *
29088  * The struct declaration for register ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION.
29089  */
29090 struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_s
29091 {
29092  volatile uint32_t SATURATION : 10; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION */
29093  uint32_t : 22; /* *UNDEFINED* */
29094 };
29095 
29096 /* The typedef declaration for register ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION. */
29097 typedef struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_s ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_t;
29098 #endif /* __ASSEMBLY__ */
29099 
29100 /* The reset value of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION register. */
29101 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_RESET 0x00000008
29102 /* The byte offset of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION register from the beginning of the component. */
29103 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_OFST 0x14
29104 
29105 /*
29106  * Register : fpga2sdram1_axi32_I_main_QosGenerator_ExtControl
29107  *
29108  * External inputs control.
29109  *
29110  * Register Layout
29111  *
29112  * Bits | Access | Reset | Description
29113  * :-------|:-------|:--------|:---------------------------------------------------------------------------------------
29114  * [0] | RW | 0x0 | ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN
29115  * [1] | RW | 0x0 | ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN
29116  * [2] | RW | 0x0 | ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN
29117  * [31:3] | ??? | Unknown | *UNDEFINED*
29118  *
29119  */
29120 /*
29121  * Field : SOCKETQOSEN
29122  *
29123  * n/a
29124  *
29125  * Field Access Macros:
29126  *
29127  */
29128 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
29129 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_LSB 0
29130 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
29131 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MSB 0
29132 /* The width in bits of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
29133 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_WIDTH 1
29134 /* The mask used to set the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value. */
29135 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET_MSK 0x00000001
29136 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value. */
29137 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_CLR_MSK 0xfffffffe
29138 /* The reset value of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
29139 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_RESET 0x0
29140 /* Extracts the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN field value from a register. */
29141 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
29142 /* Produces a ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value suitable for setting the register. */
29143 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
29144 
29145 /*
29146  * Field : EXTTHREN
29147  *
29148  * n/a
29149  *
29150  * Field Access Macros:
29151  *
29152  */
29153 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
29154 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_LSB 1
29155 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
29156 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_MSB 1
29157 /* The width in bits of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
29158 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_WIDTH 1
29159 /* The mask used to set the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value. */
29160 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET_MSK 0x00000002
29161 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value. */
29162 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_CLR_MSK 0xfffffffd
29163 /* The reset value of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
29164 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_RESET 0x0
29165 /* Extracts the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN field value from a register. */
29166 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
29167 /* Produces a ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value suitable for setting the register. */
29168 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
29169 
29170 /*
29171  * Field : INTCLKEN
29172  *
29173  * n/a
29174  *
29175  * Field Access Macros:
29176  *
29177  */
29178 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
29179 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_LSB 2
29180 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
29181 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_MSB 2
29182 /* The width in bits of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
29183 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_WIDTH 1
29184 /* The mask used to set the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value. */
29185 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET_MSK 0x00000004
29186 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value. */
29187 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_CLR_MSK 0xfffffffb
29188 /* The reset value of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
29189 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_RESET 0x0
29190 /* Extracts the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN field value from a register. */
29191 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
29192 /* Produces a ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value suitable for setting the register. */
29193 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
29194 
29195 #ifndef __ASSEMBLY__
29196 /*
29197  * WARNING: The C register and register group struct declarations are provided for
29198  * convenience and illustrative purposes. They should, however, be used with
29199  * caution as the C language standard provides no guarantees about the alignment or
29200  * atomicity of device memory accesses. The recommended practice for coding device
29201  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29202  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29203  * alt_write_dword() functions for 64 bit registers.
29204  *
29205  * The struct declaration for register ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL.
29206  */
29207 struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_s
29208 {
29209  volatile uint32_t SOCKETQOSEN : 1; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN */
29210  volatile uint32_t EXTTHREN : 1; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN */
29211  volatile uint32_t INTCLKEN : 1; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN */
29212  uint32_t : 29; /* *UNDEFINED* */
29213 };
29214 
29215 /* The typedef declaration for register ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL. */
29216 typedef struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_s ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_t;
29217 #endif /* __ASSEMBLY__ */
29218 
29219 /* The reset value of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL register. */
29220 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_RESET 0x00000000
29221 /* The byte offset of the ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL register from the beginning of the component. */
29222 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_OFST 0x18
29223 
29224 #ifndef __ASSEMBLY__
29225 /*
29226  * WARNING: The C register and register group struct declarations are provided for
29227  * convenience and illustrative purposes. They should, however, be used with
29228  * caution as the C language standard provides no guarantees about the alignment or
29229  * atomicity of device memory accesses. The recommended practice for coding device
29230  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29231  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29232  * alt_write_dword() functions for 64 bit registers.
29233  *
29234  * The struct declaration for register group ALT_MPFE_F2SDR1_AXI32_QOS.
29235  */
29236 struct ALT_MPFE_F2SDR1_AXI32_QOS_s
29237 {
29238  volatile ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_t fpga2sdram1_axi32_I_main_QosGenerator_Id_CoreId; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID */
29239  volatile ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_t fpga2sdram1_axi32_I_main_QosGenerator_Id_RevisionId; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID */
29240  volatile ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_t fpga2sdram1_axi32_I_main_QosGenerator_Priority; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY */
29241  volatile ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_t fpga2sdram1_axi32_I_main_QosGenerator_Mode; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE */
29242  volatile ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_t fpga2sdram1_axi32_I_main_QosGenerator_Bandwidth; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH */
29243  volatile ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_t fpga2sdram1_axi32_I_main_QosGenerator_Saturation; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION */
29244  volatile ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_t fpga2sdram1_axi32_I_main_QosGenerator_ExtControl; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL */
29245  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
29246 };
29247 
29248 /* The typedef declaration for register group ALT_MPFE_F2SDR1_AXI32_QOS. */
29249 typedef struct ALT_MPFE_F2SDR1_AXI32_QOS_s ALT_MPFE_F2SDR1_AXI32_QOS_t;
29250 /* The struct declaration for the raw register contents of register group ALT_MPFE_F2SDR1_AXI32_QOS. */
29251 struct ALT_MPFE_F2SDR1_AXI32_QOS_raw_s
29252 {
29253  volatile uint32_t fpga2sdram1_axi32_I_main_QosGenerator_Id_CoreId; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID */
29254  volatile uint32_t fpga2sdram1_axi32_I_main_QosGenerator_Id_RevisionId; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID */
29255  volatile uint32_t fpga2sdram1_axi32_I_main_QosGenerator_Priority; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY */
29256  volatile uint32_t fpga2sdram1_axi32_I_main_QosGenerator_Mode; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE */
29257  volatile uint32_t fpga2sdram1_axi32_I_main_QosGenerator_Bandwidth; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH */
29258  volatile uint32_t fpga2sdram1_axi32_I_main_QosGenerator_Saturation; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION */
29259  volatile uint32_t fpga2sdram1_axi32_I_main_QosGenerator_ExtControl; /* ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL */
29260  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
29261 };
29262 
29263 /* The typedef declaration for the raw register contents of register group ALT_MPFE_F2SDR1_AXI32_QOS. */
29264 typedef struct ALT_MPFE_F2SDR1_AXI32_QOS_raw_s ALT_MPFE_F2SDR1_AXI32_QOS_raw_t;
29265 #endif /* __ASSEMBLY__ */
29266 
29267 
29268 /*
29269  * Component : MPFE_F2SDR1_AXI64_QOS
29270  *
29271  */
29272 /*
29273  * Register : fpga2sdram1_axi64_I_main_QosGenerator_Id_CoreId
29274  *
29275  * Register Layout
29276  *
29277  * Bits | Access | Reset | Description
29278  * :-------|:-------|:---------|:---------------------------------------------------------------------------------------
29279  * [7:0] | R | 0x4 | ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID
29280  * [31:8] | R | 0x41ac8b | ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM
29281  *
29282  */
29283 /*
29284  * Field : CORETYPEID
29285  *
29286  * Field identifying the type of IP.
29287  *
29288  * Field Access Macros:
29289  *
29290  */
29291 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
29292 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_LSB 0
29293 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
29294 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_MSB 7
29295 /* The width in bits of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
29296 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_WIDTH 8
29297 /* The mask used to set the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value. */
29298 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
29299 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value. */
29300 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
29301 /* The reset value of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
29302 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_RESET 0x4
29303 /* Extracts the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID field value from a register. */
29304 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
29305 /* Produces a ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value suitable for setting the register. */
29306 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
29307 
29308 /*
29309  * Field : CORECHECKSUM
29310  *
29311  * Field containing a checksum of the parameters of the IP.
29312  *
29313  * Field Access Macros:
29314  *
29315  */
29316 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
29317 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_LSB 8
29318 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
29319 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_MSB 31
29320 /* The width in bits of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
29321 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_WIDTH 24
29322 /* The mask used to set the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value. */
29323 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
29324 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value. */
29325 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
29326 /* The reset value of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
29327 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_RESET 0x41ac8b
29328 /* Extracts the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM field value from a register. */
29329 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
29330 /* Produces a ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value suitable for setting the register. */
29331 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
29332 
29333 #ifndef __ASSEMBLY__
29334 /*
29335  * WARNING: The C register and register group struct declarations are provided for
29336  * convenience and illustrative purposes. They should, however, be used with
29337  * caution as the C language standard provides no guarantees about the alignment or
29338  * atomicity of device memory accesses. The recommended practice for coding device
29339  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29340  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29341  * alt_write_dword() functions for 64 bit registers.
29342  *
29343  * The struct declaration for register ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID.
29344  */
29345 struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_s
29346 {
29347  const volatile uint32_t CORETYPEID : 8; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID */
29348  const volatile uint32_t CORECHECKSUM : 24; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM */
29349 };
29350 
29351 /* The typedef declaration for register ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID. */
29352 typedef struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_s ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_t;
29353 #endif /* __ASSEMBLY__ */
29354 
29355 /* The reset value of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID register. */
29356 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_RESET 0x41ac8b04
29357 /* The byte offset of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID register from the beginning of the component. */
29358 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_OFST 0x0
29359 
29360 /*
29361  * Register : fpga2sdram1_axi64_I_main_QosGenerator_Id_RevisionId
29362  *
29363  * Register Layout
29364  *
29365  * Bits | Access | Reset | Description
29366  * :-------|:-------|:------|:----------------------------------------------------------------------------------------
29367  * [7:0] | R | 0x0 | ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID
29368  * [31:8] | R | 0x148 | ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID
29369  *
29370  */
29371 /*
29372  * Field : USERID
29373  *
29374  * Field containing a user defined value, not used anywhere inside the IP itself.
29375  *
29376  * Field Access Macros:
29377  *
29378  */
29379 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
29380 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_LSB 0
29381 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
29382 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_MSB 7
29383 /* The width in bits of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
29384 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_WIDTH 8
29385 /* The mask used to set the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value. */
29386 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET_MSK 0x000000ff
29387 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value. */
29388 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
29389 /* The reset value of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
29390 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_RESET 0x0
29391 /* Extracts the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID field value from a register. */
29392 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
29393 /* Produces a ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value suitable for setting the register. */
29394 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
29395 
29396 /*
29397  * Field : FLEXNOCID
29398  *
29399  * Field containing the build revision of the software used to generate the IP HDL
29400  * code.
29401  *
29402  * Field Access Macros:
29403  *
29404  */
29405 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
29406 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_LSB 8
29407 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
29408 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_MSB 31
29409 /* The width in bits of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
29410 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_WIDTH 24
29411 /* The mask used to set the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value. */
29412 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
29413 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value. */
29414 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
29415 /* The reset value of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
29416 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_RESET 0x148
29417 /* Extracts the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID field value from a register. */
29418 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
29419 /* Produces a ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value suitable for setting the register. */
29420 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
29421 
29422 #ifndef __ASSEMBLY__
29423 /*
29424  * WARNING: The C register and register group struct declarations are provided for
29425  * convenience and illustrative purposes. They should, however, be used with
29426  * caution as the C language standard provides no guarantees about the alignment or
29427  * atomicity of device memory accesses. The recommended practice for coding device
29428  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29429  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29430  * alt_write_dword() functions for 64 bit registers.
29431  *
29432  * The struct declaration for register ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID.
29433  */
29434 struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_s
29435 {
29436  const volatile uint32_t USERID : 8; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID */
29437  const volatile uint32_t FLEXNOCID : 24; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID */
29438 };
29439 
29440 /* The typedef declaration for register ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID. */
29441 typedef struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_s ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_t;
29442 #endif /* __ASSEMBLY__ */
29443 
29444 /* The reset value of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID register. */
29445 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_RESET 0x00014800
29446 /* The byte offset of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID register from the beginning of the component. */
29447 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_OFST 0x4
29448 
29449 /*
29450  * Register : fpga2sdram1_axi64_I_main_QosGenerator_Priority
29451  *
29452  * Priority register.
29453  *
29454  * Register Layout
29455  *
29456  * Bits | Access | Reset | Description
29457  * :--------|:-------|:--------|:------------------------------------------------------------------------------
29458  * [1:0] | RW | 0x0 | ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0
29459  * [7:2] | ??? | Unknown | *UNDEFINED*
29460  * [9:8] | RW | 0x2 | ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1
29461  * [30:10] | ??? | Unknown | *UNDEFINED*
29462  * [31] | R | 0x1 | ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK
29463  *
29464  */
29465 /*
29466  * Field : P0
29467  *
29468  * In Programmable or Bandwidth Limiter mode, the priority level for write
29469  * transactions. In Bandwidth Regulator mode, the priority level when the used
29470  * throughput is above the threshold. In Bandwidth Regulator mode, P0 should have a
29471  * value equal or lower than P1.
29472  *
29473  * Field Access Macros:
29474  *
29475  */
29476 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
29477 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_LSB 0
29478 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
29479 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_MSB 1
29480 /* The width in bits of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
29481 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_WIDTH 2
29482 /* The mask used to set the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value. */
29483 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET_MSK 0x00000003
29484 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value. */
29485 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_CLR_MSK 0xfffffffc
29486 /* The reset value of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
29487 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_RESET 0x0
29488 /* Extracts the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 field value from a register. */
29489 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_GET(value) (((value) & 0x00000003) >> 0)
29490 /* Produces a ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value suitable for setting the register. */
29491 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET(value) (((value) << 0) & 0x00000003)
29492 
29493 /*
29494  * Field : P1
29495  *
29496  * In Programmable or Bandwidth Limiter mode, the priority level for read
29497  * transactions. In Bandwidth regulator mode, the priority level when the used
29498  * throughput is below the threshold. In Bandwidth Regulator mode, P1 should have a
29499  * value equal or greater than P0.
29500  *
29501  * Field Access Macros:
29502  *
29503  */
29504 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
29505 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_LSB 8
29506 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
29507 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_MSB 9
29508 /* The width in bits of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
29509 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_WIDTH 2
29510 /* The mask used to set the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value. */
29511 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET_MSK 0x00000300
29512 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value. */
29513 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_CLR_MSK 0xfffffcff
29514 /* The reset value of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
29515 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_RESET 0x2
29516 /* Extracts the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 field value from a register. */
29517 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_GET(value) (((value) & 0x00000300) >> 8)
29518 /* Produces a ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value suitable for setting the register. */
29519 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET(value) (((value) << 8) & 0x00000300)
29520 
29521 /*
29522  * Field : MARK
29523  *
29524  * Backward compatibility marker when 0.
29525  *
29526  * Field Access Macros:
29527  *
29528  */
29529 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
29530 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_LSB 31
29531 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
29532 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_MSB 31
29533 /* The width in bits of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
29534 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_WIDTH 1
29535 /* The mask used to set the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value. */
29536 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET_MSK 0x80000000
29537 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value. */
29538 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_CLR_MSK 0x7fffffff
29539 /* The reset value of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
29540 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_RESET 0x1
29541 /* Extracts the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK field value from a register. */
29542 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_GET(value) (((value) & 0x80000000) >> 31)
29543 /* Produces a ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value suitable for setting the register. */
29544 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET(value) (((value) << 31) & 0x80000000)
29545 
29546 #ifndef __ASSEMBLY__
29547 /*
29548  * WARNING: The C register and register group struct declarations are provided for
29549  * convenience and illustrative purposes. They should, however, be used with
29550  * caution as the C language standard provides no guarantees about the alignment or
29551  * atomicity of device memory accesses. The recommended practice for coding device
29552  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29553  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29554  * alt_write_dword() functions for 64 bit registers.
29555  *
29556  * The struct declaration for register ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY.
29557  */
29558 struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_s
29559 {
29560  volatile uint32_t P0 : 2; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 */
29561  uint32_t : 6; /* *UNDEFINED* */
29562  volatile uint32_t P1 : 2; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 */
29563  uint32_t : 21; /* *UNDEFINED* */
29564  const volatile uint32_t MARK : 1; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK */
29565 };
29566 
29567 /* The typedef declaration for register ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY. */
29568 typedef struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_s ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_t;
29569 #endif /* __ASSEMBLY__ */
29570 
29571 /* The reset value of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY register. */
29572 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_RESET 0x80000200
29573 /* The byte offset of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY register from the beginning of the component. */
29574 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_OFST 0x8
29575 
29576 /*
29577  * Register : fpga2sdram1_axi64_I_main_QosGenerator_Mode
29578  *
29579  * Register Layout
29580  *
29581  * Bits | Access | Reset | Description
29582  * :-------|:-------|:--------|:--------------------------------------------------------------------------
29583  * [1:0] | RW | 0x3 | ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE
29584  * [31:2] | ??? | Unknown | *UNDEFINED*
29585  *
29586  */
29587 /*
29588  * Field : MODE
29589  *
29590  * 0 = Programmable mode: a programmed priority is assigned to each read or write,
29591  * 1 = Bandwidth Limiter Mode: a hard limit restricts throughput, 2 = Bypass mode:
29592  * (<See SoC-specific QoS generator documentation>), 3 = Bandwidth Regulator mode:
29593  * priority decreases when throughput exceeds a threshold.
29594  *
29595  * Field Access Macros:
29596  *
29597  */
29598 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
29599 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_LSB 0
29600 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
29601 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_MSB 1
29602 /* The width in bits of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
29603 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_WIDTH 2
29604 /* The mask used to set the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE register field value. */
29605 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_SET_MSK 0x00000003
29606 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE register field value. */
29607 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_CLR_MSK 0xfffffffc
29608 /* The reset value of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
29609 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_RESET 0x3
29610 /* Extracts the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE field value from a register. */
29611 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_GET(value) (((value) & 0x00000003) >> 0)
29612 /* Produces a ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE register field value suitable for setting the register. */
29613 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_SET(value) (((value) << 0) & 0x00000003)
29614 
29615 #ifndef __ASSEMBLY__
29616 /*
29617  * WARNING: The C register and register group struct declarations are provided for
29618  * convenience and illustrative purposes. They should, however, be used with
29619  * caution as the C language standard provides no guarantees about the alignment or
29620  * atomicity of device memory accesses. The recommended practice for coding device
29621  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29622  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29623  * alt_write_dword() functions for 64 bit registers.
29624  *
29625  * The struct declaration for register ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE.
29626  */
29627 struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_s
29628 {
29629  volatile uint32_t MODE : 2; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE */
29630  uint32_t : 30; /* *UNDEFINED* */
29631 };
29632 
29633 /* The typedef declaration for register ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE. */
29634 typedef struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_s ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_t;
29635 #endif /* __ASSEMBLY__ */
29636 
29637 /* The reset value of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE register. */
29638 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_RESET 0x00000003
29639 /* The byte offset of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE register from the beginning of the component. */
29640 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_OFST 0xc
29641 
29642 /*
29643  * Register : fpga2sdram1_axi64_I_main_QosGenerator_Bandwidth
29644  *
29645  * Register Layout
29646  *
29647  * Bits | Access | Reset | Description
29648  * :--------|:-------|:--------|:------------------------------------------------------------------------------------
29649  * [11:0] | RW | 0x780 | ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH
29650  * [31:12] | ??? | Unknown | *UNDEFINED*
29651  *
29652  */
29653 /*
29654  * Field : BANDWIDTH
29655  *
29656  * In Bandwidth Limiter or Bandwidth Regulator mode, the bandwidth threshold in
29657  * units of 1/256th bytes per cycle. For example, 80 MBps on a 250 MHz interface is
29658  * value 0x0052.
29659  *
29660  * Field Access Macros:
29661  *
29662  */
29663 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
29664 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_LSB 0
29665 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
29666 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MSB 11
29667 /* The width in bits of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
29668 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_WIDTH 12
29669 /* The mask used to set the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value. */
29670 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET_MSK 0x00000fff
29671 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value. */
29672 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_CLR_MSK 0xfffff000
29673 /* The reset value of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
29674 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_RESET 0x780
29675 /* Extracts the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH field value from a register. */
29676 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_GET(value) (((value) & 0x00000fff) >> 0)
29677 /* Produces a ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value suitable for setting the register. */
29678 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x00000fff)
29679 
29680 #ifndef __ASSEMBLY__
29681 /*
29682  * WARNING: The C register and register group struct declarations are provided for
29683  * convenience and illustrative purposes. They should, however, be used with
29684  * caution as the C language standard provides no guarantees about the alignment or
29685  * atomicity of device memory accesses. The recommended practice for coding device
29686  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29687  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29688  * alt_write_dword() functions for 64 bit registers.
29689  *
29690  * The struct declaration for register ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH.
29691  */
29692 struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_s
29693 {
29694  volatile uint32_t BANDWIDTH : 12; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH */
29695  uint32_t : 20; /* *UNDEFINED* */
29696 };
29697 
29698 /* The typedef declaration for register ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH. */
29699 typedef struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_s ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_t;
29700 #endif /* __ASSEMBLY__ */
29701 
29702 /* The reset value of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH register. */
29703 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_RESET 0x00000780
29704 /* The byte offset of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH register from the beginning of the component. */
29705 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_OFST 0x10
29706 
29707 /*
29708  * Register : fpga2sdram1_axi64_I_main_QosGenerator_Saturation
29709  *
29710  * Register Layout
29711  *
29712  * Bits | Access | Reset | Description
29713  * :--------|:-------|:--------|:--------------------------------------------------------------------------------------
29714  * [9:0] | RW | 0x8 | ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION
29715  * [31:10] | ??? | Unknown | *UNDEFINED*
29716  *
29717  */
29718 /*
29719  * Field : SATURATION
29720  *
29721  * In Bandwidth Limiter or Bandwidth Regulator mode, the maximum data count value,
29722  * in units of 16 bytes. This determines the window of time over which bandwidth is
29723  * measured. For example, to measure bandwidth within a 1000 cycle window on a
29724  * 64-bit interface is value 0x1F4.
29725  *
29726  * Field Access Macros:
29727  *
29728  */
29729 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
29730 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_LSB 0
29731 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
29732 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_MSB 9
29733 /* The width in bits of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
29734 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_WIDTH 10
29735 /* The mask used to set the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value. */
29736 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET_MSK 0x000003ff
29737 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value. */
29738 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_CLR_MSK 0xfffffc00
29739 /* The reset value of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
29740 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_RESET 0x8
29741 /* Extracts the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION field value from a register. */
29742 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
29743 /* Produces a ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value suitable for setting the register. */
29744 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
29745 
29746 #ifndef __ASSEMBLY__
29747 /*
29748  * WARNING: The C register and register group struct declarations are provided for
29749  * convenience and illustrative purposes. They should, however, be used with
29750  * caution as the C language standard provides no guarantees about the alignment or
29751  * atomicity of device memory accesses. The recommended practice for coding device
29752  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29753  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29754  * alt_write_dword() functions for 64 bit registers.
29755  *
29756  * The struct declaration for register ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION.
29757  */
29758 struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_s
29759 {
29760  volatile uint32_t SATURATION : 10; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION */
29761  uint32_t : 22; /* *UNDEFINED* */
29762 };
29763 
29764 /* The typedef declaration for register ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION. */
29765 typedef struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_s ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_t;
29766 #endif /* __ASSEMBLY__ */
29767 
29768 /* The reset value of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION register. */
29769 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_RESET 0x00000008
29770 /* The byte offset of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION register from the beginning of the component. */
29771 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_OFST 0x14
29772 
29773 /*
29774  * Register : fpga2sdram1_axi64_I_main_QosGenerator_ExtControl
29775  *
29776  * External inputs control.
29777  *
29778  * Register Layout
29779  *
29780  * Bits | Access | Reset | Description
29781  * :-------|:-------|:--------|:---------------------------------------------------------------------------------------
29782  * [0] | RW | 0x0 | ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN
29783  * [1] | RW | 0x0 | ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN
29784  * [2] | RW | 0x0 | ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN
29785  * [31:3] | ??? | Unknown | *UNDEFINED*
29786  *
29787  */
29788 /*
29789  * Field : SOCKETQOSEN
29790  *
29791  * n/a
29792  *
29793  * Field Access Macros:
29794  *
29795  */
29796 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
29797 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_LSB 0
29798 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
29799 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MSB 0
29800 /* The width in bits of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
29801 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_WIDTH 1
29802 /* The mask used to set the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value. */
29803 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET_MSK 0x00000001
29804 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value. */
29805 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_CLR_MSK 0xfffffffe
29806 /* The reset value of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
29807 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_RESET 0x0
29808 /* Extracts the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN field value from a register. */
29809 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
29810 /* Produces a ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value suitable for setting the register. */
29811 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
29812 
29813 /*
29814  * Field : EXTTHREN
29815  *
29816  * n/a
29817  *
29818  * Field Access Macros:
29819  *
29820  */
29821 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
29822 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_LSB 1
29823 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
29824 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_MSB 1
29825 /* The width in bits of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
29826 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_WIDTH 1
29827 /* The mask used to set the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value. */
29828 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET_MSK 0x00000002
29829 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value. */
29830 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_CLR_MSK 0xfffffffd
29831 /* The reset value of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
29832 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_RESET 0x0
29833 /* Extracts the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN field value from a register. */
29834 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
29835 /* Produces a ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value suitable for setting the register. */
29836 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
29837 
29838 /*
29839  * Field : INTCLKEN
29840  *
29841  * n/a
29842  *
29843  * Field Access Macros:
29844  *
29845  */
29846 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
29847 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_LSB 2
29848 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
29849 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_MSB 2
29850 /* The width in bits of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
29851 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_WIDTH 1
29852 /* The mask used to set the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value. */
29853 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET_MSK 0x00000004
29854 /* The mask used to clear the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value. */
29855 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_CLR_MSK 0xfffffffb
29856 /* The reset value of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
29857 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_RESET 0x0
29858 /* Extracts the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN field value from a register. */
29859 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
29860 /* Produces a ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value suitable for setting the register. */
29861 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
29862 
29863 #ifndef __ASSEMBLY__
29864 /*
29865  * WARNING: The C register and register group struct declarations are provided for
29866  * convenience and illustrative purposes. They should, however, be used with
29867  * caution as the C language standard provides no guarantees about the alignment or
29868  * atomicity of device memory accesses. The recommended practice for coding device
29869  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29870  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29871  * alt_write_dword() functions for 64 bit registers.
29872  *
29873  * The struct declaration for register ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL.
29874  */
29875 struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_s
29876 {
29877  volatile uint32_t SOCKETQOSEN : 1; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN */
29878  volatile uint32_t EXTTHREN : 1; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN */
29879  volatile uint32_t INTCLKEN : 1; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN */
29880  uint32_t : 29; /* *UNDEFINED* */
29881 };
29882 
29883 /* The typedef declaration for register ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL. */
29884 typedef struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_s ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_t;
29885 #endif /* __ASSEMBLY__ */
29886 
29887 /* The reset value of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL register. */
29888 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_RESET 0x00000000
29889 /* The byte offset of the ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL register from the beginning of the component. */
29890 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_OFST 0x18
29891 
29892 #ifndef __ASSEMBLY__
29893 /*
29894  * WARNING: The C register and register group struct declarations are provided for
29895  * convenience and illustrative purposes. They should, however, be used with
29896  * caution as the C language standard provides no guarantees about the alignment or
29897  * atomicity of device memory accesses. The recommended practice for coding device
29898  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29899  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29900  * alt_write_dword() functions for 64 bit registers.
29901  *
29902  * The struct declaration for register group ALT_MPFE_F2SDR1_AXI64_QOS.
29903  */
29904 struct ALT_MPFE_F2SDR1_AXI64_QOS_s
29905 {
29906  volatile ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_t fpga2sdram1_axi64_I_main_QosGenerator_Id_CoreId; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID */
29907  volatile ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_t fpga2sdram1_axi64_I_main_QosGenerator_Id_RevisionId; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID */
29908  volatile ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_t fpga2sdram1_axi64_I_main_QosGenerator_Priority; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY */
29909  volatile ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_t fpga2sdram1_axi64_I_main_QosGenerator_Mode; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE */
29910  volatile ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_t fpga2sdram1_axi64_I_main_QosGenerator_Bandwidth; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH */
29911  volatile ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_t fpga2sdram1_axi64_I_main_QosGenerator_Saturation; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION */
29912  volatile ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_t fpga2sdram1_axi64_I_main_QosGenerator_ExtControl; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL */
29913  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
29914 };
29915 
29916 /* The typedef declaration for register group ALT_MPFE_F2SDR1_AXI64_QOS. */
29917 typedef struct ALT_MPFE_F2SDR1_AXI64_QOS_s ALT_MPFE_F2SDR1_AXI64_QOS_t;
29918 /* The struct declaration for the raw register contents of register group ALT_MPFE_F2SDR1_AXI64_QOS. */
29919 struct ALT_MPFE_F2SDR1_AXI64_QOS_raw_s
29920 {
29921  volatile uint32_t fpga2sdram1_axi64_I_main_QosGenerator_Id_CoreId; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID */
29922  volatile uint32_t fpga2sdram1_axi64_I_main_QosGenerator_Id_RevisionId; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID */
29923  volatile uint32_t fpga2sdram1_axi64_I_main_QosGenerator_Priority; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY */
29924  volatile uint32_t fpga2sdram1_axi64_I_main_QosGenerator_Mode; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE */
29925  volatile uint32_t fpga2sdram1_axi64_I_main_QosGenerator_Bandwidth; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH */
29926  volatile uint32_t fpga2sdram1_axi64_I_main_QosGenerator_Saturation; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION */
29927  volatile uint32_t fpga2sdram1_axi64_I_main_QosGenerator_ExtControl; /* ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL */
29928  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
29929 };
29930 
29931 /* The typedef declaration for the raw register contents of register group ALT_MPFE_F2SDR1_AXI64_QOS. */
29932 typedef struct ALT_MPFE_F2SDR1_AXI64_QOS_raw_s ALT_MPFE_F2SDR1_AXI64_QOS_raw_t;
29933 #endif /* __ASSEMBLY__ */
29934 
29935 
29936 /*
29937  * Component : MPFE_F2SDR2_AXI128_QOS
29938  *
29939  */
29940 /*
29941  * Register : fpga2sdram2_axi128_I_main_QosGenerator_Id_CoreId
29942  *
29943  * Register Layout
29944  *
29945  * Bits | Access | Reset | Description
29946  * :-------|:-------|:---------|:-----------------------------------------------------------------------------------------
29947  * [7:0] | R | 0x4 | ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID
29948  * [31:8] | R | 0x150ab7 | ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM
29949  *
29950  */
29951 /*
29952  * Field : CORETYPEID
29953  *
29954  * Field identifying the type of IP.
29955  *
29956  * Field Access Macros:
29957  *
29958  */
29959 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
29960 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_LSB 0
29961 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
29962 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_MSB 7
29963 /* The width in bits of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
29964 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_WIDTH 8
29965 /* The mask used to set the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value. */
29966 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
29967 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value. */
29968 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
29969 /* The reset value of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
29970 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_RESET 0x4
29971 /* Extracts the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID field value from a register. */
29972 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
29973 /* Produces a ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value suitable for setting the register. */
29974 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
29975 
29976 /*
29977  * Field : CORECHECKSUM
29978  *
29979  * Field containing a checksum of the parameters of the IP.
29980  *
29981  * Field Access Macros:
29982  *
29983  */
29984 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
29985 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_LSB 8
29986 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
29987 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_MSB 31
29988 /* The width in bits of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
29989 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_WIDTH 24
29990 /* The mask used to set the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value. */
29991 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
29992 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value. */
29993 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
29994 /* The reset value of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
29995 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_RESET 0x150ab7
29996 /* Extracts the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM field value from a register. */
29997 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
29998 /* Produces a ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value suitable for setting the register. */
29999 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
30000 
30001 #ifndef __ASSEMBLY__
30002 /*
30003  * WARNING: The C register and register group struct declarations are provided for
30004  * convenience and illustrative purposes. They should, however, be used with
30005  * caution as the C language standard provides no guarantees about the alignment or
30006  * atomicity of device memory accesses. The recommended practice for coding device
30007  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30008  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30009  * alt_write_dword() functions for 64 bit registers.
30010  *
30011  * The struct declaration for register ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID.
30012  */
30013 struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_s
30014 {
30015  const volatile uint32_t CORETYPEID : 8; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID */
30016  const volatile uint32_t CORECHECKSUM : 24; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM */
30017 };
30018 
30019 /* The typedef declaration for register ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID. */
30020 typedef struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_s ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_t;
30021 #endif /* __ASSEMBLY__ */
30022 
30023 /* The reset value of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID register. */
30024 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_RESET 0x150ab704
30025 /* The byte offset of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID register from the beginning of the component. */
30026 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_OFST 0x0
30027 
30028 /*
30029  * Register : fpga2sdram2_axi128_I_main_QosGenerator_Id_RevisionId
30030  *
30031  * Register Layout
30032  *
30033  * Bits | Access | Reset | Description
30034  * :-------|:-------|:------|:------------------------------------------------------------------------------------------
30035  * [7:0] | R | 0x0 | ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID
30036  * [31:8] | R | 0x148 | ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID
30037  *
30038  */
30039 /*
30040  * Field : USERID
30041  *
30042  * Field containing a user defined value, not used anywhere inside the IP itself.
30043  *
30044  * Field Access Macros:
30045  *
30046  */
30047 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
30048 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_LSB 0
30049 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
30050 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_MSB 7
30051 /* The width in bits of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
30052 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_WIDTH 8
30053 /* The mask used to set the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value. */
30054 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET_MSK 0x000000ff
30055 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value. */
30056 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
30057 /* The reset value of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
30058 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_RESET 0x0
30059 /* Extracts the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID field value from a register. */
30060 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
30061 /* Produces a ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value suitable for setting the register. */
30062 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
30063 
30064 /*
30065  * Field : FLEXNOCID
30066  *
30067  * Field containing the build revision of the software used to generate the IP HDL
30068  * code.
30069  *
30070  * Field Access Macros:
30071  *
30072  */
30073 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
30074 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_LSB 8
30075 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
30076 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_MSB 31
30077 /* The width in bits of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
30078 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_WIDTH 24
30079 /* The mask used to set the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value. */
30080 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
30081 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value. */
30082 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
30083 /* The reset value of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
30084 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_RESET 0x148
30085 /* Extracts the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID field value from a register. */
30086 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
30087 /* Produces a ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value suitable for setting the register. */
30088 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
30089 
30090 #ifndef __ASSEMBLY__
30091 /*
30092  * WARNING: The C register and register group struct declarations are provided for
30093  * convenience and illustrative purposes. They should, however, be used with
30094  * caution as the C language standard provides no guarantees about the alignment or
30095  * atomicity of device memory accesses. The recommended practice for coding device
30096  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30097  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30098  * alt_write_dword() functions for 64 bit registers.
30099  *
30100  * The struct declaration for register ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID.
30101  */
30102 struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_s
30103 {
30104  const volatile uint32_t USERID : 8; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID */
30105  const volatile uint32_t FLEXNOCID : 24; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID */
30106 };
30107 
30108 /* The typedef declaration for register ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID. */
30109 typedef struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_s ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_t;
30110 #endif /* __ASSEMBLY__ */
30111 
30112 /* The reset value of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID register. */
30113 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_RESET 0x00014800
30114 /* The byte offset of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID register from the beginning of the component. */
30115 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_OFST 0x4
30116 
30117 /*
30118  * Register : fpga2sdram2_axi128_I_main_QosGenerator_Priority
30119  *
30120  * Priority register.
30121  *
30122  * Register Layout
30123  *
30124  * Bits | Access | Reset | Description
30125  * :--------|:-------|:--------|:--------------------------------------------------------------------------------
30126  * [1:0] | RW | 0x0 | ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0
30127  * [7:2] | ??? | Unknown | *UNDEFINED*
30128  * [9:8] | RW | 0x2 | ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1
30129  * [30:10] | ??? | Unknown | *UNDEFINED*
30130  * [31] | R | 0x1 | ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK
30131  *
30132  */
30133 /*
30134  * Field : P0
30135  *
30136  * In Programmable or Bandwidth Limiter mode, the priority level for write
30137  * transactions. In Bandwidth Regulator mode, the priority level when the used
30138  * throughput is above the threshold. In Bandwidth Regulator mode, P0 should have a
30139  * value equal or lower than P1.
30140  *
30141  * Field Access Macros:
30142  *
30143  */
30144 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
30145 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_LSB 0
30146 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
30147 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_MSB 1
30148 /* The width in bits of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
30149 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_WIDTH 2
30150 /* The mask used to set the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value. */
30151 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET_MSK 0x00000003
30152 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value. */
30153 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_CLR_MSK 0xfffffffc
30154 /* The reset value of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
30155 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_RESET 0x0
30156 /* Extracts the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 field value from a register. */
30157 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_GET(value) (((value) & 0x00000003) >> 0)
30158 /* Produces a ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value suitable for setting the register. */
30159 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET(value) (((value) << 0) & 0x00000003)
30160 
30161 /*
30162  * Field : P1
30163  *
30164  * In Programmable or Bandwidth Limiter mode, the priority level for read
30165  * transactions. In Bandwidth regulator mode, the priority level when the used
30166  * throughput is below the threshold. In Bandwidth Regulator mode, P1 should have a
30167  * value equal or greater than P0.
30168  *
30169  * Field Access Macros:
30170  *
30171  */
30172 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
30173 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_LSB 8
30174 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
30175 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_MSB 9
30176 /* The width in bits of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
30177 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_WIDTH 2
30178 /* The mask used to set the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value. */
30179 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET_MSK 0x00000300
30180 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value. */
30181 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_CLR_MSK 0xfffffcff
30182 /* The reset value of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
30183 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_RESET 0x2
30184 /* Extracts the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 field value from a register. */
30185 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_GET(value) (((value) & 0x00000300) >> 8)
30186 /* Produces a ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value suitable for setting the register. */
30187 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET(value) (((value) << 8) & 0x00000300)
30188 
30189 /*
30190  * Field : MARK
30191  *
30192  * Backward compatibility marker when 0.
30193  *
30194  * Field Access Macros:
30195  *
30196  */
30197 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
30198 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_LSB 31
30199 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
30200 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_MSB 31
30201 /* The width in bits of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
30202 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_WIDTH 1
30203 /* The mask used to set the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value. */
30204 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET_MSK 0x80000000
30205 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value. */
30206 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_CLR_MSK 0x7fffffff
30207 /* The reset value of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
30208 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_RESET 0x1
30209 /* Extracts the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK field value from a register. */
30210 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_GET(value) (((value) & 0x80000000) >> 31)
30211 /* Produces a ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value suitable for setting the register. */
30212 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET(value) (((value) << 31) & 0x80000000)
30213 
30214 #ifndef __ASSEMBLY__
30215 /*
30216  * WARNING: The C register and register group struct declarations are provided for
30217  * convenience and illustrative purposes. They should, however, be used with
30218  * caution as the C language standard provides no guarantees about the alignment or
30219  * atomicity of device memory accesses. The recommended practice for coding device
30220  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30221  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30222  * alt_write_dword() functions for 64 bit registers.
30223  *
30224  * The struct declaration for register ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY.
30225  */
30226 struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_s
30227 {
30228  volatile uint32_t P0 : 2; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0 */
30229  uint32_t : 6; /* *UNDEFINED* */
30230  volatile uint32_t P1 : 2; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1 */
30231  uint32_t : 21; /* *UNDEFINED* */
30232  const volatile uint32_t MARK : 1; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK */
30233 };
30234 
30235 /* The typedef declaration for register ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY. */
30236 typedef struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_s ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_t;
30237 #endif /* __ASSEMBLY__ */
30238 
30239 /* The reset value of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY register. */
30240 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_RESET 0x80000200
30241 /* The byte offset of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY register from the beginning of the component. */
30242 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_OFST 0x8
30243 
30244 /*
30245  * Register : fpga2sdram2_axi128_I_main_QosGenerator_Mode
30246  *
30247  * Register Layout
30248  *
30249  * Bits | Access | Reset | Description
30250  * :-------|:-------|:--------|:----------------------------------------------------------------------------
30251  * [1:0] | RW | 0x3 | ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE
30252  * [31:2] | ??? | Unknown | *UNDEFINED*
30253  *
30254  */
30255 /*
30256  * Field : MODE
30257  *
30258  * 0 = Programmable mode: a programmed priority is assigned to each read or write,
30259  * 1 = Bandwidth Limiter Mode: a hard limit restricts throughput, 2 = Bypass mode:
30260  * (<See SoC-specific QoS generator documentation>), 3 = Bandwidth Regulator mode:
30261  * priority decreases when throughput exceeds a threshold.
30262  *
30263  * Field Access Macros:
30264  *
30265  */
30266 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
30267 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_LSB 0
30268 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
30269 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_MSB 1
30270 /* The width in bits of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
30271 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_WIDTH 2
30272 /* The mask used to set the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE register field value. */
30273 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_SET_MSK 0x00000003
30274 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE register field value. */
30275 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_CLR_MSK 0xfffffffc
30276 /* The reset value of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
30277 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_RESET 0x3
30278 /* Extracts the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE field value from a register. */
30279 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_GET(value) (((value) & 0x00000003) >> 0)
30280 /* Produces a ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE register field value suitable for setting the register. */
30281 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_SET(value) (((value) << 0) & 0x00000003)
30282 
30283 #ifndef __ASSEMBLY__
30284 /*
30285  * WARNING: The C register and register group struct declarations are provided for
30286  * convenience and illustrative purposes. They should, however, be used with
30287  * caution as the C language standard provides no guarantees about the alignment or
30288  * atomicity of device memory accesses. The recommended practice for coding device
30289  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30290  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30291  * alt_write_dword() functions for 64 bit registers.
30292  *
30293  * The struct declaration for register ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE.
30294  */
30295 struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_s
30296 {
30297  volatile uint32_t MODE : 2; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE */
30298  uint32_t : 30; /* *UNDEFINED* */
30299 };
30300 
30301 /* The typedef declaration for register ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE. */
30302 typedef struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_s ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_t;
30303 #endif /* __ASSEMBLY__ */
30304 
30305 /* The reset value of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE register. */
30306 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_RESET 0x00000003
30307 /* The byte offset of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE register from the beginning of the component. */
30308 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_OFST 0xc
30309 
30310 /*
30311  * Register : fpga2sdram2_axi128_I_main_QosGenerator_Bandwidth
30312  *
30313  * Register Layout
30314  *
30315  * Bits | Access | Reset | Description
30316  * :--------|:-------|:--------|:--------------------------------------------------------------------------------------
30317  * [12:0] | RW | 0xc80 | ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH
30318  * [31:13] | ??? | Unknown | *UNDEFINED*
30319  *
30320  */
30321 /*
30322  * Field : BANDWIDTH
30323  *
30324  * In Bandwidth Limiter or Bandwidth Regulator mode, the bandwidth threshold in
30325  * units of 1/256th bytes per cycle. For example, 80 MBps on a 250 MHz interface is
30326  * value 0x0052.
30327  *
30328  * Field Access Macros:
30329  *
30330  */
30331 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
30332 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_LSB 0
30333 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
30334 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MSB 12
30335 /* The width in bits of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
30336 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_WIDTH 13
30337 /* The mask used to set the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value. */
30338 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET_MSK 0x00001fff
30339 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value. */
30340 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_CLR_MSK 0xffffe000
30341 /* The reset value of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
30342 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_RESET 0xc80
30343 /* Extracts the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH field value from a register. */
30344 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_GET(value) (((value) & 0x00001fff) >> 0)
30345 /* Produces a ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value suitable for setting the register. */
30346 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x00001fff)
30347 
30348 #ifndef __ASSEMBLY__
30349 /*
30350  * WARNING: The C register and register group struct declarations are provided for
30351  * convenience and illustrative purposes. They should, however, be used with
30352  * caution as the C language standard provides no guarantees about the alignment or
30353  * atomicity of device memory accesses. The recommended practice for coding device
30354  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30355  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30356  * alt_write_dword() functions for 64 bit registers.
30357  *
30358  * The struct declaration for register ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH.
30359  */
30360 struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_s
30361 {
30362  volatile uint32_t BANDWIDTH : 13; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH */
30363  uint32_t : 19; /* *UNDEFINED* */
30364 };
30365 
30366 /* The typedef declaration for register ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH. */
30367 typedef struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_s ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_t;
30368 #endif /* __ASSEMBLY__ */
30369 
30370 /* The reset value of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH register. */
30371 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_RESET 0x00000c80
30372 /* The byte offset of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH register from the beginning of the component. */
30373 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_OFST 0x10
30374 
30375 /*
30376  * Register : fpga2sdram2_axi128_I_main_QosGenerator_Saturation
30377  *
30378  * Register Layout
30379  *
30380  * Bits | Access | Reset | Description
30381  * :--------|:-------|:--------|:----------------------------------------------------------------------------------------
30382  * [9:0] | RW | 0x8 | ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION
30383  * [31:10] | ??? | Unknown | *UNDEFINED*
30384  *
30385  */
30386 /*
30387  * Field : SATURATION
30388  *
30389  * In Bandwidth Limiter or Bandwidth Regulator mode, the maximum data count value,
30390  * in units of 16 bytes. This determines the window of time over which bandwidth is
30391  * measured. For example, to measure bandwidth within a 1000 cycle window on a
30392  * 64-bit interface is value 0x1F4.
30393  *
30394  * Field Access Macros:
30395  *
30396  */
30397 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
30398 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_LSB 0
30399 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
30400 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_MSB 9
30401 /* The width in bits of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
30402 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_WIDTH 10
30403 /* The mask used to set the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value. */
30404 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET_MSK 0x000003ff
30405 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value. */
30406 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_CLR_MSK 0xfffffc00
30407 /* The reset value of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
30408 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_RESET 0x8
30409 /* Extracts the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION field value from a register. */
30410 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
30411 /* Produces a ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value suitable for setting the register. */
30412 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
30413 
30414 #ifndef __ASSEMBLY__
30415 /*
30416  * WARNING: The C register and register group struct declarations are provided for
30417  * convenience and illustrative purposes. They should, however, be used with
30418  * caution as the C language standard provides no guarantees about the alignment or
30419  * atomicity of device memory accesses. The recommended practice for coding device
30420  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30421  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30422  * alt_write_dword() functions for 64 bit registers.
30423  *
30424  * The struct declaration for register ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION.
30425  */
30426 struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_s
30427 {
30428  volatile uint32_t SATURATION : 10; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION */
30429  uint32_t : 22; /* *UNDEFINED* */
30430 };
30431 
30432 /* The typedef declaration for register ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION. */
30433 typedef struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_s ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_t;
30434 #endif /* __ASSEMBLY__ */
30435 
30436 /* The reset value of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION register. */
30437 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_RESET 0x00000008
30438 /* The byte offset of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION register from the beginning of the component. */
30439 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_OFST 0x14
30440 
30441 /*
30442  * Register : fpga2sdram2_axi128_I_main_QosGenerator_ExtControl
30443  *
30444  * External inputs control.
30445  *
30446  * Register Layout
30447  *
30448  * Bits | Access | Reset | Description
30449  * :-------|:-------|:--------|:-----------------------------------------------------------------------------------------
30450  * [0] | RW | 0x0 | ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN
30451  * [1] | RW | 0x0 | ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN
30452  * [2] | RW | 0x0 | ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN
30453  * [31:3] | ??? | Unknown | *UNDEFINED*
30454  *
30455  */
30456 /*
30457  * Field : SOCKETQOSEN
30458  *
30459  * n/a
30460  *
30461  * Field Access Macros:
30462  *
30463  */
30464 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
30465 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_LSB 0
30466 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
30467 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MSB 0
30468 /* The width in bits of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
30469 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_WIDTH 1
30470 /* The mask used to set the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value. */
30471 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET_MSK 0x00000001
30472 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value. */
30473 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_CLR_MSK 0xfffffffe
30474 /* The reset value of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
30475 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_RESET 0x0
30476 /* Extracts the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN field value from a register. */
30477 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
30478 /* Produces a ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value suitable for setting the register. */
30479 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
30480 
30481 /*
30482  * Field : EXTTHREN
30483  *
30484  * n/a
30485  *
30486  * Field Access Macros:
30487  *
30488  */
30489 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
30490 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_LSB 1
30491 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
30492 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_MSB 1
30493 /* The width in bits of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
30494 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_WIDTH 1
30495 /* The mask used to set the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value. */
30496 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET_MSK 0x00000002
30497 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value. */
30498 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_CLR_MSK 0xfffffffd
30499 /* The reset value of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
30500 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_RESET 0x0
30501 /* Extracts the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN field value from a register. */
30502 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
30503 /* Produces a ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value suitable for setting the register. */
30504 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
30505 
30506 /*
30507  * Field : INTCLKEN
30508  *
30509  * n/a
30510  *
30511  * Field Access Macros:
30512  *
30513  */
30514 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
30515 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_LSB 2
30516 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
30517 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_MSB 2
30518 /* The width in bits of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
30519 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_WIDTH 1
30520 /* The mask used to set the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value. */
30521 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET_MSK 0x00000004
30522 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value. */
30523 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_CLR_MSK 0xfffffffb
30524 /* The reset value of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
30525 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_RESET 0x0
30526 /* Extracts the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN field value from a register. */
30527 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
30528 /* Produces a ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value suitable for setting the register. */
30529 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
30530 
30531 #ifndef __ASSEMBLY__
30532 /*
30533  * WARNING: The C register and register group struct declarations are provided for
30534  * convenience and illustrative purposes. They should, however, be used with
30535  * caution as the C language standard provides no guarantees about the alignment or
30536  * atomicity of device memory accesses. The recommended practice for coding device
30537  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30538  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30539  * alt_write_dword() functions for 64 bit registers.
30540  *
30541  * The struct declaration for register ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL.
30542  */
30543 struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_s
30544 {
30545  volatile uint32_t SOCKETQOSEN : 1; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN */
30546  volatile uint32_t EXTTHREN : 1; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN */
30547  volatile uint32_t INTCLKEN : 1; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN */
30548  uint32_t : 29; /* *UNDEFINED* */
30549 };
30550 
30551 /* The typedef declaration for register ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL. */
30552 typedef struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_s ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_t;
30553 #endif /* __ASSEMBLY__ */
30554 
30555 /* The reset value of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL register. */
30556 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_RESET 0x00000000
30557 /* The byte offset of the ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL register from the beginning of the component. */
30558 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_OFST 0x18
30559 
30560 #ifndef __ASSEMBLY__
30561 /*
30562  * WARNING: The C register and register group struct declarations are provided for
30563  * convenience and illustrative purposes. They should, however, be used with
30564  * caution as the C language standard provides no guarantees about the alignment or
30565  * atomicity of device memory accesses. The recommended practice for coding device
30566  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30567  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30568  * alt_write_dword() functions for 64 bit registers.
30569  *
30570  * The struct declaration for register group ALT_MPFE_F2SDR2_AXI128_QOS.
30571  */
30572 struct ALT_MPFE_F2SDR2_AXI128_QOS_s
30573 {
30574  volatile ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_t fpga2sdram2_axi128_I_main_QosGenerator_Id_CoreId; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID */
30575  volatile ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_t fpga2sdram2_axi128_I_main_QosGenerator_Id_RevisionId; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID */
30576  volatile ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_t fpga2sdram2_axi128_I_main_QosGenerator_Priority; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY */
30577  volatile ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_t fpga2sdram2_axi128_I_main_QosGenerator_Mode; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE */
30578  volatile ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_t fpga2sdram2_axi128_I_main_QosGenerator_Bandwidth; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH */
30579  volatile ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_t fpga2sdram2_axi128_I_main_QosGenerator_Saturation; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION */
30580  volatile ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_t fpga2sdram2_axi128_I_main_QosGenerator_ExtControl; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL */
30581  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
30582 };
30583 
30584 /* The typedef declaration for register group ALT_MPFE_F2SDR2_AXI128_QOS. */
30585 typedef struct ALT_MPFE_F2SDR2_AXI128_QOS_s ALT_MPFE_F2SDR2_AXI128_QOS_t;
30586 /* The struct declaration for the raw register contents of register group ALT_MPFE_F2SDR2_AXI128_QOS. */
30587 struct ALT_MPFE_F2SDR2_AXI128_QOS_raw_s
30588 {
30589  volatile uint32_t fpga2sdram2_axi128_I_main_QosGenerator_Id_CoreId; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID */
30590  volatile uint32_t fpga2sdram2_axi128_I_main_QosGenerator_Id_RevisionId; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID */
30591  volatile uint32_t fpga2sdram2_axi128_I_main_QosGenerator_Priority; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY */
30592  volatile uint32_t fpga2sdram2_axi128_I_main_QosGenerator_Mode; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE */
30593  volatile uint32_t fpga2sdram2_axi128_I_main_QosGenerator_Bandwidth; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH */
30594  volatile uint32_t fpga2sdram2_axi128_I_main_QosGenerator_Saturation; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION */
30595  volatile uint32_t fpga2sdram2_axi128_I_main_QosGenerator_ExtControl; /* ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL */
30596  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
30597 };
30598 
30599 /* The typedef declaration for the raw register contents of register group ALT_MPFE_F2SDR2_AXI128_QOS. */
30600 typedef struct ALT_MPFE_F2SDR2_AXI128_QOS_raw_s ALT_MPFE_F2SDR2_AXI128_QOS_raw_t;
30601 #endif /* __ASSEMBLY__ */
30602 
30603 
30604 /*
30605  * Component : MPFE_F2SDR2_AXI32_QOS
30606  *
30607  */
30608 /*
30609  * Register : fpga2sdram2_axi32_I_main_QosGenerator_Id_CoreId
30610  *
30611  * Register Layout
30612  *
30613  * Bits | Access | Reset | Description
30614  * :-------|:-------|:---------|:---------------------------------------------------------------------------------------
30615  * [7:0] | R | 0x4 | ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID
30616  * [31:8] | R | 0xecc09f | ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM
30617  *
30618  */
30619 /*
30620  * Field : CORETYPEID
30621  *
30622  * Field identifying the type of IP.
30623  *
30624  * Field Access Macros:
30625  *
30626  */
30627 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
30628 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_LSB 0
30629 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
30630 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_MSB 7
30631 /* The width in bits of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
30632 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_WIDTH 8
30633 /* The mask used to set the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value. */
30634 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
30635 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value. */
30636 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
30637 /* The reset value of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
30638 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_RESET 0x4
30639 /* Extracts the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID field value from a register. */
30640 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
30641 /* Produces a ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value suitable for setting the register. */
30642 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
30643 
30644 /*
30645  * Field : CORECHECKSUM
30646  *
30647  * Field containing a checksum of the parameters of the IP.
30648  *
30649  * Field Access Macros:
30650  *
30651  */
30652 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
30653 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_LSB 8
30654 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
30655 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_MSB 31
30656 /* The width in bits of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
30657 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_WIDTH 24
30658 /* The mask used to set the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value. */
30659 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
30660 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value. */
30661 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
30662 /* The reset value of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
30663 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_RESET 0xecc09f
30664 /* Extracts the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM field value from a register. */
30665 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
30666 /* Produces a ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value suitable for setting the register. */
30667 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
30668 
30669 #ifndef __ASSEMBLY__
30670 /*
30671  * WARNING: The C register and register group struct declarations are provided for
30672  * convenience and illustrative purposes. They should, however, be used with
30673  * caution as the C language standard provides no guarantees about the alignment or
30674  * atomicity of device memory accesses. The recommended practice for coding device
30675  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30676  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30677  * alt_write_dword() functions for 64 bit registers.
30678  *
30679  * The struct declaration for register ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID.
30680  */
30681 struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_s
30682 {
30683  const volatile uint32_t CORETYPEID : 8; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID */
30684  const volatile uint32_t CORECHECKSUM : 24; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM */
30685 };
30686 
30687 /* The typedef declaration for register ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID. */
30688 typedef struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_s ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_t;
30689 #endif /* __ASSEMBLY__ */
30690 
30691 /* The reset value of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID register. */
30692 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_RESET 0xecc09f04
30693 /* The byte offset of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID register from the beginning of the component. */
30694 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_OFST 0x0
30695 
30696 /*
30697  * Register : fpga2sdram2_axi32_I_main_QosGenerator_Id_RevisionId
30698  *
30699  * Register Layout
30700  *
30701  * Bits | Access | Reset | Description
30702  * :-------|:-------|:------|:----------------------------------------------------------------------------------------
30703  * [7:0] | R | 0x0 | ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID
30704  * [31:8] | R | 0x148 | ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID
30705  *
30706  */
30707 /*
30708  * Field : USERID
30709  *
30710  * Field containing a user defined value, not used anywhere inside the IP itself.
30711  *
30712  * Field Access Macros:
30713  *
30714  */
30715 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
30716 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_LSB 0
30717 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
30718 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_MSB 7
30719 /* The width in bits of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
30720 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_WIDTH 8
30721 /* The mask used to set the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value. */
30722 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET_MSK 0x000000ff
30723 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value. */
30724 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
30725 /* The reset value of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
30726 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_RESET 0x0
30727 /* Extracts the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID field value from a register. */
30728 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
30729 /* Produces a ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value suitable for setting the register. */
30730 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
30731 
30732 /*
30733  * Field : FLEXNOCID
30734  *
30735  * Field containing the build revision of the software used to generate the IP HDL
30736  * code.
30737  *
30738  * Field Access Macros:
30739  *
30740  */
30741 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
30742 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_LSB 8
30743 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
30744 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_MSB 31
30745 /* The width in bits of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
30746 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_WIDTH 24
30747 /* The mask used to set the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value. */
30748 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
30749 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value. */
30750 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
30751 /* The reset value of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
30752 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_RESET 0x148
30753 /* Extracts the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID field value from a register. */
30754 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
30755 /* Produces a ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value suitable for setting the register. */
30756 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
30757 
30758 #ifndef __ASSEMBLY__
30759 /*
30760  * WARNING: The C register and register group struct declarations are provided for
30761  * convenience and illustrative purposes. They should, however, be used with
30762  * caution as the C language standard provides no guarantees about the alignment or
30763  * atomicity of device memory accesses. The recommended practice for coding device
30764  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30765  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30766  * alt_write_dword() functions for 64 bit registers.
30767  *
30768  * The struct declaration for register ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID.
30769  */
30770 struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_s
30771 {
30772  const volatile uint32_t USERID : 8; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID */
30773  const volatile uint32_t FLEXNOCID : 24; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID */
30774 };
30775 
30776 /* The typedef declaration for register ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID. */
30777 typedef struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_s ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_t;
30778 #endif /* __ASSEMBLY__ */
30779 
30780 /* The reset value of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID register. */
30781 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_RESET 0x00014800
30782 /* The byte offset of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID register from the beginning of the component. */
30783 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_OFST 0x4
30784 
30785 /*
30786  * Register : fpga2sdram2_axi32_I_main_QosGenerator_Priority
30787  *
30788  * Priority register.
30789  *
30790  * Register Layout
30791  *
30792  * Bits | Access | Reset | Description
30793  * :--------|:-------|:--------|:------------------------------------------------------------------------------
30794  * [1:0] | RW | 0x0 | ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0
30795  * [7:2] | ??? | Unknown | *UNDEFINED*
30796  * [9:8] | RW | 0x2 | ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1
30797  * [30:10] | ??? | Unknown | *UNDEFINED*
30798  * [31] | R | 0x1 | ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK
30799  *
30800  */
30801 /*
30802  * Field : P0
30803  *
30804  * In Programmable or Bandwidth Limiter mode, the priority level for write
30805  * transactions. In Bandwidth Regulator mode, the priority level when the used
30806  * throughput is above the threshold. In Bandwidth Regulator mode, P0 should have a
30807  * value equal or lower than P1.
30808  *
30809  * Field Access Macros:
30810  *
30811  */
30812 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
30813 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_LSB 0
30814 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
30815 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_MSB 1
30816 /* The width in bits of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
30817 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_WIDTH 2
30818 /* The mask used to set the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value. */
30819 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET_MSK 0x00000003
30820 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value. */
30821 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_CLR_MSK 0xfffffffc
30822 /* The reset value of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
30823 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_RESET 0x0
30824 /* Extracts the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 field value from a register. */
30825 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_GET(value) (((value) & 0x00000003) >> 0)
30826 /* Produces a ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value suitable for setting the register. */
30827 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET(value) (((value) << 0) & 0x00000003)
30828 
30829 /*
30830  * Field : P1
30831  *
30832  * In Programmable or Bandwidth Limiter mode, the priority level for read
30833  * transactions. In Bandwidth regulator mode, the priority level when the used
30834  * throughput is below the threshold. In Bandwidth Regulator mode, P1 should have a
30835  * value equal or greater than P0.
30836  *
30837  * Field Access Macros:
30838  *
30839  */
30840 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
30841 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_LSB 8
30842 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
30843 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_MSB 9
30844 /* The width in bits of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
30845 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_WIDTH 2
30846 /* The mask used to set the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value. */
30847 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET_MSK 0x00000300
30848 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value. */
30849 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_CLR_MSK 0xfffffcff
30850 /* The reset value of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
30851 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_RESET 0x2
30852 /* Extracts the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 field value from a register. */
30853 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_GET(value) (((value) & 0x00000300) >> 8)
30854 /* Produces a ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value suitable for setting the register. */
30855 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET(value) (((value) << 8) & 0x00000300)
30856 
30857 /*
30858  * Field : MARK
30859  *
30860  * Backward compatibility marker when 0.
30861  *
30862  * Field Access Macros:
30863  *
30864  */
30865 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
30866 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_LSB 31
30867 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
30868 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_MSB 31
30869 /* The width in bits of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
30870 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_WIDTH 1
30871 /* The mask used to set the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value. */
30872 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET_MSK 0x80000000
30873 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value. */
30874 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_CLR_MSK 0x7fffffff
30875 /* The reset value of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
30876 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_RESET 0x1
30877 /* Extracts the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK field value from a register. */
30878 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_GET(value) (((value) & 0x80000000) >> 31)
30879 /* Produces a ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value suitable for setting the register. */
30880 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET(value) (((value) << 31) & 0x80000000)
30881 
30882 #ifndef __ASSEMBLY__
30883 /*
30884  * WARNING: The C register and register group struct declarations are provided for
30885  * convenience and illustrative purposes. They should, however, be used with
30886  * caution as the C language standard provides no guarantees about the alignment or
30887  * atomicity of device memory accesses. The recommended practice for coding device
30888  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30889  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30890  * alt_write_dword() functions for 64 bit registers.
30891  *
30892  * The struct declaration for register ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY.
30893  */
30894 struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_s
30895 {
30896  volatile uint32_t P0 : 2; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0 */
30897  uint32_t : 6; /* *UNDEFINED* */
30898  volatile uint32_t P1 : 2; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1 */
30899  uint32_t : 21; /* *UNDEFINED* */
30900  const volatile uint32_t MARK : 1; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK */
30901 };
30902 
30903 /* The typedef declaration for register ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY. */
30904 typedef struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_s ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_t;
30905 #endif /* __ASSEMBLY__ */
30906 
30907 /* The reset value of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY register. */
30908 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_RESET 0x80000200
30909 /* The byte offset of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY register from the beginning of the component. */
30910 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_OFST 0x8
30911 
30912 /*
30913  * Register : fpga2sdram2_axi32_I_main_QosGenerator_Mode
30914  *
30915  * Register Layout
30916  *
30917  * Bits | Access | Reset | Description
30918  * :-------|:-------|:--------|:--------------------------------------------------------------------------
30919  * [1:0] | RW | 0x3 | ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE
30920  * [31:2] | ??? | Unknown | *UNDEFINED*
30921  *
30922  */
30923 /*
30924  * Field : MODE
30925  *
30926  * 0 = Programmable mode: a programmed priority is assigned to each read or write,
30927  * 1 = Bandwidth Limiter Mode: a hard limit restricts throughput, 2 = Bypass mode:
30928  * (<See SoC-specific QoS generator documentation>), 3 = Bandwidth Regulator mode:
30929  * priority decreases when throughput exceeds a threshold.
30930  *
30931  * Field Access Macros:
30932  *
30933  */
30934 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
30935 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_LSB 0
30936 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
30937 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_MSB 1
30938 /* The width in bits of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
30939 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_WIDTH 2
30940 /* The mask used to set the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE register field value. */
30941 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_SET_MSK 0x00000003
30942 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE register field value. */
30943 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_CLR_MSK 0xfffffffc
30944 /* The reset value of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
30945 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_RESET 0x3
30946 /* Extracts the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE field value from a register. */
30947 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_GET(value) (((value) & 0x00000003) >> 0)
30948 /* Produces a ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE register field value suitable for setting the register. */
30949 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_SET(value) (((value) << 0) & 0x00000003)
30950 
30951 #ifndef __ASSEMBLY__
30952 /*
30953  * WARNING: The C register and register group struct declarations are provided for
30954  * convenience and illustrative purposes. They should, however, be used with
30955  * caution as the C language standard provides no guarantees about the alignment or
30956  * atomicity of device memory accesses. The recommended practice for coding device
30957  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30958  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30959  * alt_write_dword() functions for 64 bit registers.
30960  *
30961  * The struct declaration for register ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE.
30962  */
30963 struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_s
30964 {
30965  volatile uint32_t MODE : 2; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE */
30966  uint32_t : 30; /* *UNDEFINED* */
30967 };
30968 
30969 /* The typedef declaration for register ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE. */
30970 typedef struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_s ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_t;
30971 #endif /* __ASSEMBLY__ */
30972 
30973 /* The reset value of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE register. */
30974 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_RESET 0x00000003
30975 /* The byte offset of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE register from the beginning of the component. */
30976 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_OFST 0xc
30977 
30978 /*
30979  * Register : fpga2sdram2_axi32_I_main_QosGenerator_Bandwidth
30980  *
30981  * Register Layout
30982  *
30983  * Bits | Access | Reset | Description
30984  * :--------|:-------|:--------|:------------------------------------------------------------------------------------
30985  * [10:0] | RW | 0x280 | ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH
30986  * [31:11] | ??? | Unknown | *UNDEFINED*
30987  *
30988  */
30989 /*
30990  * Field : BANDWIDTH
30991  *
30992  * In Bandwidth Limiter or Bandwidth Regulator mode, the bandwidth threshold in
30993  * units of 1/256th bytes per cycle. For example, 80 MBps on a 250 MHz interface is
30994  * value 0x0052.
30995  *
30996  * Field Access Macros:
30997  *
30998  */
30999 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
31000 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_LSB 0
31001 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
31002 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MSB 10
31003 /* The width in bits of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
31004 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_WIDTH 11
31005 /* The mask used to set the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value. */
31006 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET_MSK 0x000007ff
31007 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value. */
31008 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_CLR_MSK 0xfffff800
31009 /* The reset value of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
31010 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_RESET 0x280
31011 /* Extracts the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH field value from a register. */
31012 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_GET(value) (((value) & 0x000007ff) >> 0)
31013 /* Produces a ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value suitable for setting the register. */
31014 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x000007ff)
31015 
31016 #ifndef __ASSEMBLY__
31017 /*
31018  * WARNING: The C register and register group struct declarations are provided for
31019  * convenience and illustrative purposes. They should, however, be used with
31020  * caution as the C language standard provides no guarantees about the alignment or
31021  * atomicity of device memory accesses. The recommended practice for coding device
31022  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
31023  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
31024  * alt_write_dword() functions for 64 bit registers.
31025  *
31026  * The struct declaration for register ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH.
31027  */
31028 struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_s
31029 {
31030  volatile uint32_t BANDWIDTH : 11; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH */
31031  uint32_t : 21; /* *UNDEFINED* */
31032 };
31033 
31034 /* The typedef declaration for register ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH. */
31035 typedef struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_s ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_t;
31036 #endif /* __ASSEMBLY__ */
31037 
31038 /* The reset value of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH register. */
31039 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_RESET 0x00000280
31040 /* The byte offset of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH register from the beginning of the component. */
31041 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_OFST 0x10
31042 
31043 /*
31044  * Register : fpga2sdram2_axi32_I_main_QosGenerator_Saturation
31045  *
31046  * Register Layout
31047  *
31048  * Bits | Access | Reset | Description
31049  * :--------|:-------|:--------|:--------------------------------------------------------------------------------------
31050  * [9:0] | RW | 0x8 | ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION
31051  * [31:10] | ??? | Unknown | *UNDEFINED*
31052  *
31053  */
31054 /*
31055  * Field : SATURATION
31056  *
31057  * In Bandwidth Limiter or Bandwidth Regulator mode, the maximum data count value,
31058  * in units of 16 bytes. This determines the window of time over which bandwidth is
31059  * measured. For example, to measure bandwidth within a 1000 cycle window on a
31060  * 64-bit interface is value 0x1F4.
31061  *
31062  * Field Access Macros:
31063  *
31064  */
31065 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
31066 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_LSB 0
31067 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
31068 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_MSB 9
31069 /* The width in bits of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
31070 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_WIDTH 10
31071 /* The mask used to set the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value. */
31072 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET_MSK 0x000003ff
31073 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value. */
31074 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_CLR_MSK 0xfffffc00
31075 /* The reset value of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
31076 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_RESET 0x8
31077 /* Extracts the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION field value from a register. */
31078 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
31079 /* Produces a ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value suitable for setting the register. */
31080 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
31081 
31082 #ifndef __ASSEMBLY__
31083 /*
31084  * WARNING: The C register and register group struct declarations are provided for
31085  * convenience and illustrative purposes. They should, however, be used with
31086  * caution as the C language standard provides no guarantees about the alignment or
31087  * atomicity of device memory accesses. The recommended practice for coding device
31088  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
31089  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
31090  * alt_write_dword() functions for 64 bit registers.
31091  *
31092  * The struct declaration for register ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION.
31093  */
31094 struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_s
31095 {
31096  volatile uint32_t SATURATION : 10; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION */
31097  uint32_t : 22; /* *UNDEFINED* */
31098 };
31099 
31100 /* The typedef declaration for register ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION. */
31101 typedef struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_s ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_t;
31102 #endif /* __ASSEMBLY__ */
31103 
31104 /* The reset value of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION register. */
31105 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_RESET 0x00000008
31106 /* The byte offset of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION register from the beginning of the component. */
31107 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_OFST 0x14
31108 
31109 /*
31110  * Register : fpga2sdram2_axi32_I_main_QosGenerator_ExtControl
31111  *
31112  * External inputs control.
31113  *
31114  * Register Layout
31115  *
31116  * Bits | Access | Reset | Description
31117  * :-------|:-------|:--------|:---------------------------------------------------------------------------------------
31118  * [0] | RW | 0x0 | ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN
31119  * [1] | RW | 0x0 | ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN
31120  * [2] | RW | 0x0 | ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN
31121  * [31:3] | ??? | Unknown | *UNDEFINED*
31122  *
31123  */
31124 /*
31125  * Field : SOCKETQOSEN
31126  *
31127  * n/a
31128  *
31129  * Field Access Macros:
31130  *
31131  */
31132 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
31133 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_LSB 0
31134 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
31135 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MSB 0
31136 /* The width in bits of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
31137 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_WIDTH 1
31138 /* The mask used to set the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value. */
31139 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET_MSK 0x00000001
31140 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value. */
31141 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_CLR_MSK 0xfffffffe
31142 /* The reset value of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
31143 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_RESET 0x0
31144 /* Extracts the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN field value from a register. */
31145 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
31146 /* Produces a ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value suitable for setting the register. */
31147 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
31148 
31149 /*
31150  * Field : EXTTHREN
31151  *
31152  * n/a
31153  *
31154  * Field Access Macros:
31155  *
31156  */
31157 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
31158 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_LSB 1
31159 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
31160 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_MSB 1
31161 /* The width in bits of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
31162 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_WIDTH 1
31163 /* The mask used to set the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value. */
31164 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET_MSK 0x00000002
31165 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value. */
31166 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_CLR_MSK 0xfffffffd
31167 /* The reset value of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
31168 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_RESET 0x0
31169 /* Extracts the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN field value from a register. */
31170 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
31171 /* Produces a ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value suitable for setting the register. */
31172 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
31173 
31174 /*
31175  * Field : INTCLKEN
31176  *
31177  * n/a
31178  *
31179  * Field Access Macros:
31180  *
31181  */
31182 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
31183 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_LSB 2
31184 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
31185 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_MSB 2
31186 /* The width in bits of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
31187 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_WIDTH 1
31188 /* The mask used to set the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value. */
31189 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET_MSK 0x00000004
31190 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value. */
31191 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_CLR_MSK 0xfffffffb
31192 /* The reset value of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
31193 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_RESET 0x0
31194 /* Extracts the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN field value from a register. */
31195 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
31196 /* Produces a ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value suitable for setting the register. */
31197 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
31198 
31199 #ifndef __ASSEMBLY__
31200 /*
31201  * WARNING: The C register and register group struct declarations are provided for
31202  * convenience and illustrative purposes. They should, however, be used with
31203  * caution as the C language standard provides no guarantees about the alignment or
31204  * atomicity of device memory accesses. The recommended practice for coding device
31205  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
31206  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
31207  * alt_write_dword() functions for 64 bit registers.
31208  *
31209  * The struct declaration for register ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL.
31210  */
31211 struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_s
31212 {
31213  volatile uint32_t SOCKETQOSEN : 1; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN */
31214  volatile uint32_t EXTTHREN : 1; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN */
31215  volatile uint32_t INTCLKEN : 1; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN */
31216  uint32_t : 29; /* *UNDEFINED* */
31217 };
31218 
31219 /* The typedef declaration for register ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL. */
31220 typedef struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_s ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_t;
31221 #endif /* __ASSEMBLY__ */
31222 
31223 /* The reset value of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL register. */
31224 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_RESET 0x00000000
31225 /* The byte offset of the ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL register from the beginning of the component. */
31226 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_OFST 0x18
31227 
31228 #ifndef __ASSEMBLY__
31229 /*
31230  * WARNING: The C register and register group struct declarations are provided for
31231  * convenience and illustrative purposes. They should, however, be used with
31232  * caution as the C language standard provides no guarantees about the alignment or
31233  * atomicity of device memory accesses. The recommended practice for coding device
31234  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
31235  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
31236  * alt_write_dword() functions for 64 bit registers.
31237  *
31238  * The struct declaration for register group ALT_MPFE_F2SDR2_AXI32_QOS.
31239  */
31240 struct ALT_MPFE_F2SDR2_AXI32_QOS_s
31241 {
31242  volatile ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_t fpga2sdram2_axi32_I_main_QosGenerator_Id_CoreId; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID */
31243  volatile ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_t fpga2sdram2_axi32_I_main_QosGenerator_Id_RevisionId; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID */
31244  volatile ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_t fpga2sdram2_axi32_I_main_QosGenerator_Priority; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY */
31245  volatile ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_t fpga2sdram2_axi32_I_main_QosGenerator_Mode; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE */
31246  volatile ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_t fpga2sdram2_axi32_I_main_QosGenerator_Bandwidth; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH */
31247  volatile ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_t fpga2sdram2_axi32_I_main_QosGenerator_Saturation; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION */
31248  volatile ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_t fpga2sdram2_axi32_I_main_QosGenerator_ExtControl; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL */
31249  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
31250 };
31251 
31252 /* The typedef declaration for register group ALT_MPFE_F2SDR2_AXI32_QOS. */
31253 typedef struct ALT_MPFE_F2SDR2_AXI32_QOS_s ALT_MPFE_F2SDR2_AXI32_QOS_t;
31254 /* The struct declaration for the raw register contents of register group ALT_MPFE_F2SDR2_AXI32_QOS. */
31255 struct ALT_MPFE_F2SDR2_AXI32_QOS_raw_s
31256 {
31257  volatile uint32_t fpga2sdram2_axi32_I_main_QosGenerator_Id_CoreId; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID */
31258  volatile uint32_t fpga2sdram2_axi32_I_main_QosGenerator_Id_RevisionId; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID */
31259  volatile uint32_t fpga2sdram2_axi32_I_main_QosGenerator_Priority; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY */
31260  volatile uint32_t fpga2sdram2_axi32_I_main_QosGenerator_Mode; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE */
31261  volatile uint32_t fpga2sdram2_axi32_I_main_QosGenerator_Bandwidth; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH */
31262  volatile uint32_t fpga2sdram2_axi32_I_main_QosGenerator_Saturation; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION */
31263  volatile uint32_t fpga2sdram2_axi32_I_main_QosGenerator_ExtControl; /* ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL */
31264  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
31265 };
31266 
31267 /* The typedef declaration for the raw register contents of register group ALT_MPFE_F2SDR2_AXI32_QOS. */
31268 typedef struct ALT_MPFE_F2SDR2_AXI32_QOS_raw_s ALT_MPFE_F2SDR2_AXI32_QOS_raw_t;
31269 #endif /* __ASSEMBLY__ */
31270 
31271 
31272 /*
31273  * Component : MPFE_F2SDR2_AXI64_QOS
31274  *
31275  */
31276 /*
31277  * Register : fpga2sdram2_axi64_I_main_QosGenerator_Id_CoreId
31278  *
31279  * Register Layout
31280  *
31281  * Bits | Access | Reset | Description
31282  * :-------|:-------|:---------|:---------------------------------------------------------------------------------------
31283  * [7:0] | R | 0x4 | ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID
31284  * [31:8] | R | 0xe58cca | ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM
31285  *
31286  */
31287 /*
31288  * Field : CORETYPEID
31289  *
31290  * Field identifying the type of IP.
31291  *
31292  * Field Access Macros:
31293  *
31294  */
31295 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
31296 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_LSB 0
31297 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
31298 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_MSB 7
31299 /* The width in bits of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
31300 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_WIDTH 8
31301 /* The mask used to set the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value. */
31302 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
31303 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value. */
31304 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
31305 /* The reset value of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field. */
31306 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_RESET 0x4
31307 /* Extracts the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID field value from a register. */
31308 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
31309 /* Produces a ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID register field value suitable for setting the register. */
31310 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
31311 
31312 /*
31313  * Field : CORECHECKSUM
31314  *
31315  * Field containing a checksum of the parameters of the IP.
31316  *
31317  * Field Access Macros:
31318  *
31319  */
31320 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
31321 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_LSB 8
31322 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
31323 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_MSB 31
31324 /* The width in bits of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
31325 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_WIDTH 24
31326 /* The mask used to set the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value. */
31327 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
31328 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value. */
31329 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
31330 /* The reset value of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field. */
31331 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_RESET 0xe58cca
31332 /* Extracts the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM field value from a register. */
31333 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
31334 /* Produces a ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM register field value suitable for setting the register. */
31335 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
31336 
31337 #ifndef __ASSEMBLY__
31338 /*
31339  * WARNING: The C register and register group struct declarations are provided for
31340  * convenience and illustrative purposes. They should, however, be used with
31341  * caution as the C language standard provides no guarantees about the alignment or
31342  * atomicity of device memory accesses. The recommended practice for coding device
31343  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
31344  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
31345  * alt_write_dword() functions for 64 bit registers.
31346  *
31347  * The struct declaration for register ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID.
31348  */
31349 struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_s
31350 {
31351  const volatile uint32_t CORETYPEID : 8; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID */
31352  const volatile uint32_t CORECHECKSUM : 24; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM */
31353 };
31354 
31355 /* The typedef declaration for register ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID. */
31356 typedef struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_s ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_t;
31357 #endif /* __ASSEMBLY__ */
31358 
31359 /* The reset value of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID register. */
31360 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_RESET 0xe58cca04
31361 /* The byte offset of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID register from the beginning of the component. */
31362 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_OFST 0x0
31363 
31364 /*
31365  * Register : fpga2sdram2_axi64_I_main_QosGenerator_Id_RevisionId
31366  *
31367  * Register Layout
31368  *
31369  * Bits | Access | Reset | Description
31370  * :-------|:-------|:------|:----------------------------------------------------------------------------------------
31371  * [7:0] | R | 0x0 | ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID
31372  * [31:8] | R | 0x148 | ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID
31373  *
31374  */
31375 /*
31376  * Field : USERID
31377  *
31378  * Field containing a user defined value, not used anywhere inside the IP itself.
31379  *
31380  * Field Access Macros:
31381  *
31382  */
31383 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
31384 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_LSB 0
31385 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
31386 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_MSB 7
31387 /* The width in bits of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
31388 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_WIDTH 8
31389 /* The mask used to set the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value. */
31390 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET_MSK 0x000000ff
31391 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value. */
31392 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
31393 /* The reset value of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field. */
31394 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_RESET 0x0
31395 /* Extracts the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID field value from a register. */
31396 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
31397 /* Produces a ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID register field value suitable for setting the register. */
31398 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
31399 
31400 /*
31401  * Field : FLEXNOCID
31402  *
31403  * Field containing the build revision of the software used to generate the IP HDL
31404  * code.
31405  *
31406  * Field Access Macros:
31407  *
31408  */
31409 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
31410 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_LSB 8
31411 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
31412 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_MSB 31
31413 /* The width in bits of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
31414 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_WIDTH 24
31415 /* The mask used to set the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value. */
31416 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
31417 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value. */
31418 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
31419 /* The reset value of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field. */
31420 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_RESET 0x148
31421 /* Extracts the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID field value from a register. */
31422 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
31423 /* Produces a ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID register field value suitable for setting the register. */
31424 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
31425 
31426 #ifndef __ASSEMBLY__
31427 /*
31428  * WARNING: The C register and register group struct declarations are provided for
31429  * convenience and illustrative purposes. They should, however, be used with
31430  * caution as the C language standard provides no guarantees about the alignment or
31431  * atomicity of device memory accesses. The recommended practice for coding device
31432  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
31433  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
31434  * alt_write_dword() functions for 64 bit registers.
31435  *
31436  * The struct declaration for register ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID.
31437  */
31438 struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_s
31439 {
31440  const volatile uint32_t USERID : 8; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID */
31441  const volatile uint32_t FLEXNOCID : 24; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID */
31442 };
31443 
31444 /* The typedef declaration for register ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID. */
31445 typedef struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_s ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_t;
31446 #endif /* __ASSEMBLY__ */
31447 
31448 /* The reset value of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID register. */
31449 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_RESET 0x00014800
31450 /* The byte offset of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID register from the beginning of the component. */
31451 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_OFST 0x4
31452 
31453 /*
31454  * Register : fpga2sdram2_axi64_I_main_QosGenerator_Priority
31455  *
31456  * Priority register.
31457  *
31458  * Register Layout
31459  *
31460  * Bits | Access | Reset | Description
31461  * :--------|:-------|:--------|:------------------------------------------------------------------------------
31462  * [1:0] | RW | 0x0 | ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0
31463  * [7:2] | ??? | Unknown | *UNDEFINED*
31464  * [9:8] | RW | 0x2 | ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1
31465  * [30:10] | ??? | Unknown | *UNDEFINED*
31466  * [31] | R | 0x1 | ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK
31467  *
31468  */
31469 /*
31470  * Field : P0
31471  *
31472  * In Programmable or Bandwidth Limiter mode, the priority level for write
31473  * transactions. In Bandwidth Regulator mode, the priority level when the used
31474  * throughput is above the threshold. In Bandwidth Regulator mode, P0 should have a
31475  * value equal or lower than P1.
31476  *
31477  * Field Access Macros:
31478  *
31479  */
31480 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
31481 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_LSB 0
31482 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
31483 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_MSB 1
31484 /* The width in bits of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
31485 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_WIDTH 2
31486 /* The mask used to set the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value. */
31487 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET_MSK 0x00000003
31488 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value. */
31489 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_CLR_MSK 0xfffffffc
31490 /* The reset value of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field. */
31491 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_RESET 0x0
31492 /* Extracts the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 field value from a register. */
31493 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_GET(value) (((value) & 0x00000003) >> 0)
31494 /* Produces a ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 register field value suitable for setting the register. */
31495 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET(value) (((value) << 0) & 0x00000003)
31496 
31497 /*
31498  * Field : P1
31499  *
31500  * In Programmable or Bandwidth Limiter mode, the priority level for read
31501  * transactions. In Bandwidth regulator mode, the priority level when the used
31502  * throughput is below the threshold. In Bandwidth Regulator mode, P1 should have a
31503  * value equal or greater than P0.
31504  *
31505  * Field Access Macros:
31506  *
31507  */
31508 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
31509 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_LSB 8
31510 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
31511 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_MSB 9
31512 /* The width in bits of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
31513 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_WIDTH 2
31514 /* The mask used to set the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value. */
31515 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET_MSK 0x00000300
31516 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value. */
31517 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_CLR_MSK 0xfffffcff
31518 /* The reset value of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field. */
31519 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_RESET 0x2
31520 /* Extracts the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 field value from a register. */
31521 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_GET(value) (((value) & 0x00000300) >> 8)
31522 /* Produces a ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 register field value suitable for setting the register. */
31523 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET(value) (((value) << 8) & 0x00000300)
31524 
31525 /*
31526  * Field : MARK
31527  *
31528  * Backward compatibility marker when 0.
31529  *
31530  * Field Access Macros:
31531  *
31532  */
31533 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
31534 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_LSB 31
31535 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
31536 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_MSB 31
31537 /* The width in bits of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
31538 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_WIDTH 1
31539 /* The mask used to set the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value. */
31540 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET_MSK 0x80000000
31541 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value. */
31542 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_CLR_MSK 0x7fffffff
31543 /* The reset value of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field. */
31544 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_RESET 0x1
31545 /* Extracts the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK field value from a register. */
31546 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_GET(value) (((value) & 0x80000000) >> 31)
31547 /* Produces a ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK register field value suitable for setting the register. */
31548 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET(value) (((value) << 31) & 0x80000000)
31549 
31550 #ifndef __ASSEMBLY__
31551 /*
31552  * WARNING: The C register and register group struct declarations are provided for
31553  * convenience and illustrative purposes. They should, however, be used with
31554  * caution as the C language standard provides no guarantees about the alignment or
31555  * atomicity of device memory accesses. The recommended practice for coding device
31556  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
31557  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
31558  * alt_write_dword() functions for 64 bit registers.
31559  *
31560  * The struct declaration for register ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY.
31561  */
31562 struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_s
31563 {
31564  volatile uint32_t P0 : 2; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0 */
31565  uint32_t : 6; /* *UNDEFINED* */
31566  volatile uint32_t P1 : 2; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1 */
31567  uint32_t : 21; /* *UNDEFINED* */
31568  const volatile uint32_t MARK : 1; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK */
31569 };
31570 
31571 /* The typedef declaration for register ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY. */
31572 typedef struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_s ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_t;
31573 #endif /* __ASSEMBLY__ */
31574 
31575 /* The reset value of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY register. */
31576 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_RESET 0x80000200
31577 /* The byte offset of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY register from the beginning of the component. */
31578 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_OFST 0x8
31579 
31580 /*
31581  * Register : fpga2sdram2_axi64_I_main_QosGenerator_Mode
31582  *
31583  * Register Layout
31584  *
31585  * Bits | Access | Reset | Description
31586  * :-------|:-------|:--------|:--------------------------------------------------------------------------
31587  * [1:0] | RW | 0x3 | ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE
31588  * [31:2] | ??? | Unknown | *UNDEFINED*
31589  *
31590  */
31591 /*
31592  * Field : MODE
31593  *
31594  * 0 = Programmable mode: a programmed priority is assigned to each read or write,
31595  * 1 = Bandwidth Limiter Mode: a hard limit restricts throughput, 2 = Bypass mode:
31596  * (<See SoC-specific QoS generator documentation>), 3 = Bandwidth Regulator mode:
31597  * priority decreases when throughput exceeds a threshold.
31598  *
31599  * Field Access Macros:
31600  *
31601  */
31602 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
31603 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_LSB 0
31604 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
31605 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_MSB 1
31606 /* The width in bits of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
31607 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_WIDTH 2
31608 /* The mask used to set the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE register field value. */
31609 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_SET_MSK 0x00000003
31610 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE register field value. */
31611 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_CLR_MSK 0xfffffffc
31612 /* The reset value of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE register field. */
31613 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_RESET 0x3
31614 /* Extracts the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE field value from a register. */
31615 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_GET(value) (((value) & 0x00000003) >> 0)
31616 /* Produces a ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE register field value suitable for setting the register. */
31617 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_SET(value) (((value) << 0) & 0x00000003)
31618 
31619 #ifndef __ASSEMBLY__
31620 /*
31621  * WARNING: The C register and register group struct declarations are provided for
31622  * convenience and illustrative purposes. They should, however, be used with
31623  * caution as the C language standard provides no guarantees about the alignment or
31624  * atomicity of device memory accesses. The recommended practice for coding device
31625  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
31626  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
31627  * alt_write_dword() functions for 64 bit registers.
31628  *
31629  * The struct declaration for register ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE.
31630  */
31631 struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_s
31632 {
31633  volatile uint32_t MODE : 2; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE */
31634  uint32_t : 30; /* *UNDEFINED* */
31635 };
31636 
31637 /* The typedef declaration for register ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE. */
31638 typedef struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_s ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_t;
31639 #endif /* __ASSEMBLY__ */
31640 
31641 /* The reset value of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE register. */
31642 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_RESET 0x00000003
31643 /* The byte offset of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE register from the beginning of the component. */
31644 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_OFST 0xc
31645 
31646 /*
31647  * Register : fpga2sdram2_axi64_I_main_QosGenerator_Bandwidth
31648  *
31649  * Register Layout
31650  *
31651  * Bits | Access | Reset | Description
31652  * :--------|:-------|:--------|:------------------------------------------------------------------------------------
31653  * [11:0] | RW | 0x780 | ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH
31654  * [31:12] | ??? | Unknown | *UNDEFINED*
31655  *
31656  */
31657 /*
31658  * Field : BANDWIDTH
31659  *
31660  * In Bandwidth Limiter or Bandwidth Regulator mode, the bandwidth threshold in
31661  * units of 1/256th bytes per cycle. For example, 80 MBps on a 250 MHz interface is
31662  * value 0x0052.
31663  *
31664  * Field Access Macros:
31665  *
31666  */
31667 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
31668 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_LSB 0
31669 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
31670 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MSB 11
31671 /* The width in bits of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
31672 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_WIDTH 12
31673 /* The mask used to set the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value. */
31674 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET_MSK 0x00000fff
31675 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value. */
31676 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_CLR_MSK 0xfffff000
31677 /* The reset value of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field. */
31678 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_RESET 0x780
31679 /* Extracts the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH field value from a register. */
31680 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_GET(value) (((value) & 0x00000fff) >> 0)
31681 /* Produces a ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH register field value suitable for setting the register. */
31682 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x00000fff)
31683 
31684 #ifndef __ASSEMBLY__
31685 /*
31686  * WARNING: The C register and register group struct declarations are provided for
31687  * convenience and illustrative purposes. They should, however, be used with
31688  * caution as the C language standard provides no guarantees about the alignment or
31689  * atomicity of device memory accesses. The recommended practice for coding device
31690  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
31691  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
31692  * alt_write_dword() functions for 64 bit registers.
31693  *
31694  * The struct declaration for register ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH.
31695  */
31696 struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_s
31697 {
31698  volatile uint32_t BANDWIDTH : 12; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH */
31699  uint32_t : 20; /* *UNDEFINED* */
31700 };
31701 
31702 /* The typedef declaration for register ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH. */
31703 typedef struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_s ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_t;
31704 #endif /* __ASSEMBLY__ */
31705 
31706 /* The reset value of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH register. */
31707 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_RESET 0x00000780
31708 /* The byte offset of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH register from the beginning of the component. */
31709 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_OFST 0x10
31710 
31711 /*
31712  * Register : fpga2sdram2_axi64_I_main_QosGenerator_Saturation
31713  *
31714  * Register Layout
31715  *
31716  * Bits | Access | Reset | Description
31717  * :--------|:-------|:--------|:--------------------------------------------------------------------------------------
31718  * [9:0] | RW | 0x8 | ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION
31719  * [31:10] | ??? | Unknown | *UNDEFINED*
31720  *
31721  */
31722 /*
31723  * Field : SATURATION
31724  *
31725  * In Bandwidth Limiter or Bandwidth Regulator mode, the maximum data count value,
31726  * in units of 16 bytes. This determines the window of time over which bandwidth is
31727  * measured. For example, to measure bandwidth within a 1000 cycle window on a
31728  * 64-bit interface is value 0x1F4.
31729  *
31730  * Field Access Macros:
31731  *
31732  */
31733 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
31734 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_LSB 0
31735 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
31736 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_MSB 9
31737 /* The width in bits of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
31738 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_WIDTH 10
31739 /* The mask used to set the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value. */
31740 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET_MSK 0x000003ff
31741 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value. */
31742 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_CLR_MSK 0xfffffc00
31743 /* The reset value of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field. */
31744 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_RESET 0x8
31745 /* Extracts the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION field value from a register. */
31746 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
31747 /* Produces a ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION register field value suitable for setting the register. */
31748 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
31749 
31750 #ifndef __ASSEMBLY__
31751 /*
31752  * WARNING: The C register and register group struct declarations are provided for
31753  * convenience and illustrative purposes. They should, however, be used with
31754  * caution as the C language standard provides no guarantees about the alignment or
31755  * atomicity of device memory accesses. The recommended practice for coding device
31756  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
31757  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
31758  * alt_write_dword() functions for 64 bit registers.
31759  *
31760  * The struct declaration for register ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION.
31761  */
31762 struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_s
31763 {
31764  volatile uint32_t SATURATION : 10; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION */
31765  uint32_t : 22; /* *UNDEFINED* */
31766 };
31767 
31768 /* The typedef declaration for register ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION. */
31769 typedef struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_s ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_t;
31770 #endif /* __ASSEMBLY__ */
31771 
31772 /* The reset value of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION register. */
31773 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_RESET 0x00000008
31774 /* The byte offset of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION register from the beginning of the component. */
31775 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_OFST 0x14
31776 
31777 /*
31778  * Register : fpga2sdram2_axi64_I_main_QosGenerator_ExtControl
31779  *
31780  * External inputs control.
31781  *
31782  * Register Layout
31783  *
31784  * Bits | Access | Reset | Description
31785  * :-------|:-------|:--------|:---------------------------------------------------------------------------------------
31786  * [0] | RW | 0x0 | ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN
31787  * [1] | RW | 0x0 | ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN
31788  * [2] | RW | 0x0 | ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN
31789  * [31:3] | ??? | Unknown | *UNDEFINED*
31790  *
31791  */
31792 /*
31793  * Field : SOCKETQOSEN
31794  *
31795  * n/a
31796  *
31797  * Field Access Macros:
31798  *
31799  */
31800 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
31801 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_LSB 0
31802 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
31803 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MSB 0
31804 /* The width in bits of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
31805 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_WIDTH 1
31806 /* The mask used to set the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value. */
31807 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET_MSK 0x00000001
31808 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value. */
31809 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_CLR_MSK 0xfffffffe
31810 /* The reset value of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field. */
31811 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_RESET 0x0
31812 /* Extracts the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN field value from a register. */
31813 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
31814 /* Produces a ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN register field value suitable for setting the register. */
31815 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
31816 
31817 /*
31818  * Field : EXTTHREN
31819  *
31820  * n/a
31821  *
31822  * Field Access Macros:
31823  *
31824  */
31825 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
31826 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_LSB 1
31827 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
31828 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_MSB 1
31829 /* The width in bits of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
31830 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_WIDTH 1
31831 /* The mask used to set the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value. */
31832 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET_MSK 0x00000002
31833 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value. */
31834 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_CLR_MSK 0xfffffffd
31835 /* The reset value of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field. */
31836 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_RESET 0x0
31837 /* Extracts the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN field value from a register. */
31838 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
31839 /* Produces a ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN register field value suitable for setting the register. */
31840 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
31841 
31842 /*
31843  * Field : INTCLKEN
31844  *
31845  * n/a
31846  *
31847  * Field Access Macros:
31848  *
31849  */
31850 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
31851 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_LSB 2
31852 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
31853 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_MSB 2
31854 /* The width in bits of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
31855 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_WIDTH 1
31856 /* The mask used to set the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value. */
31857 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET_MSK 0x00000004
31858 /* The mask used to clear the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value. */
31859 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_CLR_MSK 0xfffffffb
31860 /* The reset value of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field. */
31861 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_RESET 0x0
31862 /* Extracts the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN field value from a register. */
31863 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
31864 /* Produces a ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN register field value suitable for setting the register. */
31865 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
31866 
31867 #ifndef __ASSEMBLY__
31868 /*
31869  * WARNING: The C register and register group struct declarations are provided for
31870  * convenience and illustrative purposes. They should, however, be used with
31871  * caution as the C language standard provides no guarantees about the alignment or
31872  * atomicity of device memory accesses. The recommended practice for coding device
31873  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
31874  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
31875  * alt_write_dword() functions for 64 bit registers.
31876  *
31877  * The struct declaration for register ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL.
31878  */
31879 struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_s
31880 {
31881  volatile uint32_t SOCKETQOSEN : 1; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN */
31882  volatile uint32_t EXTTHREN : 1; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN */
31883  volatile uint32_t INTCLKEN : 1; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN */
31884  uint32_t : 29; /* *UNDEFINED* */
31885 };
31886 
31887 /* The typedef declaration for register ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL. */
31888 typedef struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_s ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_t;
31889 #endif /* __ASSEMBLY__ */
31890 
31891 /* The reset value of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL register. */
31892 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_RESET 0x00000000
31893 /* The byte offset of the ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL register from the beginning of the component. */
31894 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_OFST 0x18
31895 
31896 #ifndef __ASSEMBLY__
31897 /*
31898  * WARNING: The C register and register group struct declarations are provided for
31899  * convenience and illustrative purposes. They should, however, be used with
31900  * caution as the C language standard provides no guarantees about the alignment or
31901  * atomicity of device memory accesses. The recommended practice for coding device
31902  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
31903  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
31904  * alt_write_dword() functions for 64 bit registers.
31905  *
31906  * The struct declaration for register group ALT_MPFE_F2SDR2_AXI64_QOS.
31907  */
31908 struct ALT_MPFE_F2SDR2_AXI64_QOS_s
31909 {
31910  volatile ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_t fpga2sdram2_axi64_I_main_QosGenerator_Id_CoreId; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID */
31911  volatile ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_t fpga2sdram2_axi64_I_main_QosGenerator_Id_RevisionId; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID */
31912  volatile ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_t fpga2sdram2_axi64_I_main_QosGenerator_Priority; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY */
31913  volatile ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_t fpga2sdram2_axi64_I_main_QosGenerator_Mode; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE */
31914  volatile ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_t fpga2sdram2_axi64_I_main_QosGenerator_Bandwidth; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH */
31915  volatile ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_t fpga2sdram2_axi64_I_main_QosGenerator_Saturation; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION */
31916  volatile ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_t fpga2sdram2_axi64_I_main_QosGenerator_ExtControl; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL */
31917  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
31918 };
31919 
31920 /* The typedef declaration for register group ALT_MPFE_F2SDR2_AXI64_QOS. */
31921 typedef struct ALT_MPFE_F2SDR2_AXI64_QOS_s ALT_MPFE_F2SDR2_AXI64_QOS_t;
31922 /* The struct declaration for the raw register contents of register group ALT_MPFE_F2SDR2_AXI64_QOS. */
31923 struct ALT_MPFE_F2SDR2_AXI64_QOS_raw_s
31924 {
31925  volatile uint32_t fpga2sdram2_axi64_I_main_QosGenerator_Id_CoreId; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID */
31926  volatile uint32_t fpga2sdram2_axi64_I_main_QosGenerator_Id_RevisionId; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID */
31927  volatile uint32_t fpga2sdram2_axi64_I_main_QosGenerator_Priority; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY */
31928  volatile uint32_t fpga2sdram2_axi64_I_main_QosGenerator_Mode; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE */
31929  volatile uint32_t fpga2sdram2_axi64_I_main_QosGenerator_Bandwidth; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH */
31930  volatile uint32_t fpga2sdram2_axi64_I_main_QosGenerator_Saturation; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION */
31931  volatile uint32_t fpga2sdram2_axi64_I_main_QosGenerator_ExtControl; /* ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL */
31932  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
31933 };
31934 
31935 /* The typedef declaration for the raw register contents of register group ALT_MPFE_F2SDR2_AXI64_QOS. */
31936 typedef struct ALT_MPFE_F2SDR2_AXI64_QOS_raw_s ALT_MPFE_F2SDR2_AXI64_QOS_raw_t;
31937 #endif /* __ASSEMBLY__ */
31938 
31939 
31940 /*
31941  * Component : MPFE_F2SDR_MGR_MAIN_SBMGR
31942  *
31943  */
31944 /*
31945  * Register : fpga2sdram_manager_main_SidebandManager_Id_CoreId
31946  *
31947  * Register Layout
31948  *
31949  * Bits | Access | Reset | Description
31950  * :-------|:-------|:---------|:---------------------------------------------------------------------------------------------
31951  * [7:0] | R | 0xb | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID
31952  * [31:8] | R | 0x9885cb | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM
31953  *
31954  */
31955 /*
31956  * Field : CORETYPEID
31957  *
31958  * Field identifying the type of IP.
31959  *
31960  * Field Access Macros:
31961  *
31962  */
31963 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID register field. */
31964 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID_LSB 0
31965 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID register field. */
31966 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID_MSB 7
31967 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID register field. */
31968 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID_WIDTH 8
31969 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID register field value. */
31970 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
31971 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID register field value. */
31972 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
31973 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID register field. */
31974 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID_RESET 0xb
31975 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID field value from a register. */
31976 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
31977 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID register field value suitable for setting the register. */
31978 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
31979 
31980 /*
31981  * Field : CORECHECKSUM
31982  *
31983  * Field containing a checksum of the parameters of the IP.
31984  *
31985  * Field Access Macros:
31986  *
31987  */
31988 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM register field. */
31989 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM_LSB 8
31990 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM register field. */
31991 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM_MSB 31
31992 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM register field. */
31993 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM_WIDTH 24
31994 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM register field value. */
31995 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
31996 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM register field value. */
31997 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
31998 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM register field. */
31999 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM_RESET 0x9885cb
32000 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM field value from a register. */
32001 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
32002 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM register field value suitable for setting the register. */
32003 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
32004 
32005 #ifndef __ASSEMBLY__
32006 /*
32007  * WARNING: The C register and register group struct declarations are provided for
32008  * convenience and illustrative purposes. They should, however, be used with
32009  * caution as the C language standard provides no guarantees about the alignment or
32010  * atomicity of device memory accesses. The recommended practice for coding device
32011  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
32012  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
32013  * alt_write_dword() functions for 64 bit registers.
32014  *
32015  * The struct declaration for register ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID.
32016  */
32017 struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_s
32018 {
32019  const volatile uint32_t CORETYPEID : 8; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID */
32020  const volatile uint32_t CORECHECKSUM : 24; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM */
32021 };
32022 
32023 /* The typedef declaration for register ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID. */
32024 typedef struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_s ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_t;
32025 #endif /* __ASSEMBLY__ */
32026 
32027 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID register. */
32028 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_RESET 0x9885cb0b
32029 /* The byte offset of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID register from the beginning of the component. */
32030 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_OFST 0x0
32031 
32032 /*
32033  * Register : fpga2sdram_manager_main_SidebandManager_Id_RevisionId
32034  *
32035  * Register Layout
32036  *
32037  * Bits | Access | Reset | Description
32038  * :-------|:-------|:------|:----------------------------------------------------------------------------------------------
32039  * [7:0] | R | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID
32040  * [31:8] | R | 0x148 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID
32041  *
32042  */
32043 /*
32044  * Field : USERID
32045  *
32046  * Field containing a user defined value, not used anywhere inside the IP itself.
32047  *
32048  * Field Access Macros:
32049  *
32050  */
32051 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID register field. */
32052 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID_LSB 0
32053 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID register field. */
32054 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID_MSB 7
32055 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID register field. */
32056 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID_WIDTH 8
32057 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID register field value. */
32058 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID_SET_MSK 0x000000ff
32059 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID register field value. */
32060 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
32061 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID register field. */
32062 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID_RESET 0x0
32063 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID field value from a register. */
32064 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
32065 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID register field value suitable for setting the register. */
32066 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
32067 
32068 /*
32069  * Field : FLEXNOCID
32070  *
32071  * Field containing the build revision of the software used to generate the IP HDL
32072  * code.
32073  *
32074  * Field Access Macros:
32075  *
32076  */
32077 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID register field. */
32078 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID_LSB 8
32079 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID register field. */
32080 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID_MSB 31
32081 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID register field. */
32082 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID_WIDTH 24
32083 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID register field value. */
32084 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
32085 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID register field value. */
32086 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
32087 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID register field. */
32088 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID_RESET 0x148
32089 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID field value from a register. */
32090 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
32091 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID register field value suitable for setting the register. */
32092 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
32093 
32094 #ifndef __ASSEMBLY__
32095 /*
32096  * WARNING: The C register and register group struct declarations are provided for
32097  * convenience and illustrative purposes. They should, however, be used with
32098  * caution as the C language standard provides no guarantees about the alignment or
32099  * atomicity of device memory accesses. The recommended practice for coding device
32100  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
32101  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
32102  * alt_write_dword() functions for 64 bit registers.
32103  *
32104  * The struct declaration for register ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID.
32105  */
32106 struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_s
32107 {
32108  const volatile uint32_t USERID : 8; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID */
32109  const volatile uint32_t FLEXNOCID : 24; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID */
32110 };
32111 
32112 /* The typedef declaration for register ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID. */
32113 typedef struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_s ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_t;
32114 #endif /* __ASSEMBLY__ */
32115 
32116 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID register. */
32117 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_RESET 0x00014800
32118 /* The byte offset of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID register from the beginning of the component. */
32119 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_OFST 0x4
32120 
32121 /*
32122  * Register : fpga2sdram_manager_main_SidebandManager_FaultEn
32123  *
32124  * Register Layout
32125  *
32126  * Bits | Access | Reset | Description
32127  * :-------|:-------|:--------|:--------------------------------------------------------------------------------------
32128  * [0] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN
32129  * [31:1] | ??? | Unknown | *UNDEFINED*
32130  *
32131  */
32132 /*
32133  * Field : FAULTEN
32134  *
32135  * Global Fault Enable register
32136  *
32137  * Field Access Macros:
32138  *
32139  */
32140 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN register field. */
32141 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN_LSB 0
32142 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN register field. */
32143 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN_MSB 0
32144 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN register field. */
32145 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN_WIDTH 1
32146 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN register field value. */
32147 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN_SET_MSK 0x00000001
32148 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN register field value. */
32149 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN_CLR_MSK 0xfffffffe
32150 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN register field. */
32151 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN_RESET 0x0
32152 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN field value from a register. */
32153 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN_GET(value) (((value) & 0x00000001) >> 0)
32154 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN register field value suitable for setting the register. */
32155 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN_SET(value) (((value) << 0) & 0x00000001)
32156 
32157 #ifndef __ASSEMBLY__
32158 /*
32159  * WARNING: The C register and register group struct declarations are provided for
32160  * convenience and illustrative purposes. They should, however, be used with
32161  * caution as the C language standard provides no guarantees about the alignment or
32162  * atomicity of device memory accesses. The recommended practice for coding device
32163  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
32164  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
32165  * alt_write_dword() functions for 64 bit registers.
32166  *
32167  * The struct declaration for register ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN.
32168  */
32169 struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_s
32170 {
32171  volatile uint32_t FAULTEN : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN */
32172  uint32_t : 31; /* *UNDEFINED* */
32173 };
32174 
32175 /* The typedef declaration for register ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN. */
32176 typedef struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_s ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_t;
32177 #endif /* __ASSEMBLY__ */
32178 
32179 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN register. */
32180 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_RESET 0x00000000
32181 /* The byte offset of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN register from the beginning of the component. */
32182 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_OFST 0x8
32183 
32184 /*
32185  * Register : fpga2sdram_manager_main_SidebandManager_FaultStatus
32186  *
32187  * Register Layout
32188  *
32189  * Bits | Access | Reset | Description
32190  * :-------|:-------|:--------|:----------------------------------------------------------------------------------------------
32191  * [0] | R | Unknown | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS
32192  * [31:1] | ??? | Unknown | *UNDEFINED*
32193  *
32194  */
32195 /*
32196  * Field : FAULTSTATUS
32197  *
32198  * Global Fault Status register
32199  *
32200  * Field Access Macros:
32201  *
32202  */
32203 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS register field. */
32204 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS_LSB 0
32205 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS register field. */
32206 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS_MSB 0
32207 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS register field. */
32208 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS_WIDTH 1
32209 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS register field value. */
32210 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS_SET_MSK 0x00000001
32211 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS register field value. */
32212 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS_CLR_MSK 0xfffffffe
32213 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS register field is UNKNOWN. */
32214 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS_RESET 0x0
32215 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS field value from a register. */
32216 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS_GET(value) (((value) & 0x00000001) >> 0)
32217 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS register field value suitable for setting the register. */
32218 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS_SET(value) (((value) << 0) & 0x00000001)
32219 
32220 #ifndef __ASSEMBLY__
32221 /*
32222  * WARNING: The C register and register group struct declarations are provided for
32223  * convenience and illustrative purposes. They should, however, be used with
32224  * caution as the C language standard provides no guarantees about the alignment or
32225  * atomicity of device memory accesses. The recommended practice for coding device
32226  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
32227  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
32228  * alt_write_dword() functions for 64 bit registers.
32229  *
32230  * The struct declaration for register ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS.
32231  */
32232 struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_s
32233 {
32234  const volatile uint32_t FAULTSTATUS : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS */
32235  uint32_t : 31; /* *UNDEFINED* */
32236 };
32237 
32238 /* The typedef declaration for register ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS. */
32239 typedef struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_s ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_t;
32240 #endif /* __ASSEMBLY__ */
32241 
32242 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS register. */
32243 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_RESET 0x00000000
32244 /* The byte offset of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS register from the beginning of the component. */
32245 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_OFST 0xc
32246 
32247 /*
32248  * Register : fpga2sdram_manager_main_SidebandManager_FlagInEn0
32249  *
32250  * Register Layout
32251  *
32252  * Bits | Access | Reset | Description
32253  * :--------|:-------|:--------|:---------------------------------------------------------------------------------------------------------
32254  * [0] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN
32255  * [1] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN
32256  * [2] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN
32257  * [3] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN
32258  * [4] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN
32259  * [5] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN
32260  * [6] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN
32261  * [7] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN
32262  * [8] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN
32263  * [9] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN
32264  * [10] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN
32265  * [11] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN
32266  * [31:12] | ??? | Unknown | *UNDEFINED*
32267  *
32268  */
32269 /*
32270  * Field : FPGA2SDRAM0_IDLE_EN
32271  *
32272  * FlagIn Enable register #0.FPGA2SDRAM0_IDLE_EN
32273  *
32274  * Field Access Macros:
32275  *
32276  */
32277 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN register field. */
32278 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN_LSB 0
32279 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN register field. */
32280 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN_MSB 0
32281 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN register field. */
32282 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN_WIDTH 1
32283 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN register field value. */
32284 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN_SET_MSK 0x00000001
32285 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN register field value. */
32286 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN_CLR_MSK 0xfffffffe
32287 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN register field. */
32288 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN_RESET 0x0
32289 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN field value from a register. */
32290 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN_GET(value) (((value) & 0x00000001) >> 0)
32291 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN register field value suitable for setting the register. */
32292 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN_SET(value) (((value) << 0) & 0x00000001)
32293 
32294 /*
32295  * Field : FPGA2SDRAM0_IDLEACK_EN
32296  *
32297  * FlagIn Enable register #1.FPGA2SDRAM0_IDLEACK_EN
32298  *
32299  * Field Access Macros:
32300  *
32301  */
32302 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN register field. */
32303 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN_LSB 1
32304 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN register field. */
32305 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN_MSB 1
32306 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN register field. */
32307 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN_WIDTH 1
32308 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN register field value. */
32309 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN_SET_MSK 0x00000002
32310 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN register field value. */
32311 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN_CLR_MSK 0xfffffffd
32312 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN register field. */
32313 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN_RESET 0x0
32314 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN field value from a register. */
32315 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN_GET(value) (((value) & 0x00000002) >> 1)
32316 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN register field value suitable for setting the register. */
32317 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN_SET(value) (((value) << 1) & 0x00000002)
32318 
32319 /*
32320  * Field : FPGA2SDRAM0_CMD_IDLE_EN
32321  *
32322  * FlagIn Enable register #2.FPGA2SDRAM0_CMD_IDLE_EN
32323  *
32324  * Field Access Macros:
32325  *
32326  */
32327 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN register field. */
32328 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN_LSB 2
32329 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN register field. */
32330 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN_MSB 2
32331 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN register field. */
32332 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN_WIDTH 1
32333 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN register field value. */
32334 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN_SET_MSK 0x00000004
32335 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN register field value. */
32336 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN_CLR_MSK 0xfffffffb
32337 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN register field. */
32338 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN_RESET 0x0
32339 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN field value from a register. */
32340 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN_GET(value) (((value) & 0x00000004) >> 2)
32341 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN register field value suitable for setting the register. */
32342 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN_SET(value) (((value) << 2) & 0x00000004)
32343 
32344 /*
32345  * Field : FPGA2SDRAM0_RESP_IDLE_EN
32346  *
32347  * FlagIn Enable register #3.FPGA2SDRAM0_RESP_IDLE_EN
32348  *
32349  * Field Access Macros:
32350  *
32351  */
32352 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN register field. */
32353 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN_LSB 3
32354 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN register field. */
32355 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN_MSB 3
32356 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN register field. */
32357 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN_WIDTH 1
32358 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN register field value. */
32359 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN_SET_MSK 0x00000008
32360 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN register field value. */
32361 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN_CLR_MSK 0xfffffff7
32362 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN register field. */
32363 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN_RESET 0x0
32364 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN field value from a register. */
32365 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN_GET(value) (((value) & 0x00000008) >> 3)
32366 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN register field value suitable for setting the register. */
32367 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN_SET(value) (((value) << 3) & 0x00000008)
32368 
32369 /*
32370  * Field : FPGA2SDRAM1_IDLE_EN
32371  *
32372  * FlagIn Enable register #4.FPGA2SDRAM1_IDLE_EN
32373  *
32374  * Field Access Macros:
32375  *
32376  */
32377 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN register field. */
32378 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN_LSB 4
32379 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN register field. */
32380 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN_MSB 4
32381 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN register field. */
32382 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN_WIDTH 1
32383 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN register field value. */
32384 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN_SET_MSK 0x00000010
32385 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN register field value. */
32386 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN_CLR_MSK 0xffffffef
32387 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN register field. */
32388 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN_RESET 0x0
32389 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN field value from a register. */
32390 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN_GET(value) (((value) & 0x00000010) >> 4)
32391 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN register field value suitable for setting the register. */
32392 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN_SET(value) (((value) << 4) & 0x00000010)
32393 
32394 /*
32395  * Field : FPGA2SDRAM1_IDLEACK_EN
32396  *
32397  * FlagIn Enable register #5.FPGA2SDRAM1_IDLEACK_EN
32398  *
32399  * Field Access Macros:
32400  *
32401  */
32402 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN register field. */
32403 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN_LSB 5
32404 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN register field. */
32405 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN_MSB 5
32406 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN register field. */
32407 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN_WIDTH 1
32408 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN register field value. */
32409 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN_SET_MSK 0x00000020
32410 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN register field value. */
32411 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN_CLR_MSK 0xffffffdf
32412 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN register field. */
32413 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN_RESET 0x0
32414 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN field value from a register. */
32415 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN_GET(value) (((value) & 0x00000020) >> 5)
32416 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN register field value suitable for setting the register. */
32417 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN_SET(value) (((value) << 5) & 0x00000020)
32418 
32419 /*
32420  * Field : FPGA2SDRAM1_CMD_IDLE_EN
32421  *
32422  * FlagIn Enable register #6.FPGA2SDRAM1_CMD_IDLE_EN
32423  *
32424  * Field Access Macros:
32425  *
32426  */
32427 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN register field. */
32428 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN_LSB 6
32429 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN register field. */
32430 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN_MSB 6
32431 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN register field. */
32432 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN_WIDTH 1
32433 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN register field value. */
32434 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN_SET_MSK 0x00000040
32435 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN register field value. */
32436 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN_CLR_MSK 0xffffffbf
32437 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN register field. */
32438 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN_RESET 0x0
32439 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN field value from a register. */
32440 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN_GET(value) (((value) & 0x00000040) >> 6)
32441 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN register field value suitable for setting the register. */
32442 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN_SET(value) (((value) << 6) & 0x00000040)
32443 
32444 /*
32445  * Field : FPGA2SDRAM1_RESP_IDLE_EN
32446  *
32447  * FlagIn Enable register #7.FPGA2SDRAM1_RESP_IDLE_EN
32448  *
32449  * Field Access Macros:
32450  *
32451  */
32452 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN register field. */
32453 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN_LSB 7
32454 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN register field. */
32455 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN_MSB 7
32456 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN register field. */
32457 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN_WIDTH 1
32458 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN register field value. */
32459 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN_SET_MSK 0x00000080
32460 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN register field value. */
32461 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN_CLR_MSK 0xffffff7f
32462 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN register field. */
32463 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN_RESET 0x0
32464 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN field value from a register. */
32465 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN_GET(value) (((value) & 0x00000080) >> 7)
32466 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN register field value suitable for setting the register. */
32467 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN_SET(value) (((value) << 7) & 0x00000080)
32468 
32469 /*
32470  * Field : FPGA2SDRAM2_IDLE_EN
32471  *
32472  * FlagIn Enable register #8.FPGA2SDRAM2_IDLE_EN
32473  *
32474  * Field Access Macros:
32475  *
32476  */
32477 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN register field. */
32478 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN_LSB 8
32479 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN register field. */
32480 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN_MSB 8
32481 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN register field. */
32482 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN_WIDTH 1
32483 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN register field value. */
32484 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN_SET_MSK 0x00000100
32485 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN register field value. */
32486 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN_CLR_MSK 0xfffffeff
32487 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN register field. */
32488 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN_RESET 0x0
32489 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN field value from a register. */
32490 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN_GET(value) (((value) & 0x00000100) >> 8)
32491 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN register field value suitable for setting the register. */
32492 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN_SET(value) (((value) << 8) & 0x00000100)
32493 
32494 /*
32495  * Field : FPGA2SDRAM2_IDLEACK_EN
32496  *
32497  * FlagIn Enable register #9.FPGA2SDRAM2_IDLEACK_EN
32498  *
32499  * Field Access Macros:
32500  *
32501  */
32502 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN register field. */
32503 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN_LSB 9
32504 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN register field. */
32505 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN_MSB 9
32506 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN register field. */
32507 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN_WIDTH 1
32508 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN register field value. */
32509 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN_SET_MSK 0x00000200
32510 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN register field value. */
32511 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN_CLR_MSK 0xfffffdff
32512 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN register field. */
32513 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN_RESET 0x0
32514 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN field value from a register. */
32515 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN_GET(value) (((value) & 0x00000200) >> 9)
32516 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN register field value suitable for setting the register. */
32517 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN_SET(value) (((value) << 9) & 0x00000200)
32518 
32519 /*
32520  * Field : FPGA2SDRAM2_CMD_IDLE_EN
32521  *
32522  * FlagIn Enable register #10.FPGA2SDRAM2_CMD_IDLE_EN
32523  *
32524  * Field Access Macros:
32525  *
32526  */
32527 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN register field. */
32528 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN_LSB 10
32529 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN register field. */
32530 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN_MSB 10
32531 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN register field. */
32532 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN_WIDTH 1
32533 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN register field value. */
32534 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN_SET_MSK 0x00000400
32535 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN register field value. */
32536 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN_CLR_MSK 0xfffffbff
32537 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN register field. */
32538 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN_RESET 0x0
32539 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN field value from a register. */
32540 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN_GET(value) (((value) & 0x00000400) >> 10)
32541 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN register field value suitable for setting the register. */
32542 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN_SET(value) (((value) << 10) & 0x00000400)
32543 
32544 /*
32545  * Field : FPGA2SDRAM2_RESP_IDLE_EN
32546  *
32547  * FlagIn Enable register #11.FPGA2SDRAM2_RESP_IDLE_EN
32548  *
32549  * Field Access Macros:
32550  *
32551  */
32552 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN register field. */
32553 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN_LSB 11
32554 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN register field. */
32555 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN_MSB 11
32556 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN register field. */
32557 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN_WIDTH 1
32558 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN register field value. */
32559 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN_SET_MSK 0x00000800
32560 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN register field value. */
32561 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN_CLR_MSK 0xfffff7ff
32562 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN register field. */
32563 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN_RESET 0x0
32564 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN field value from a register. */
32565 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN_GET(value) (((value) & 0x00000800) >> 11)
32566 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN register field value suitable for setting the register. */
32567 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN_SET(value) (((value) << 11) & 0x00000800)
32568 
32569 #ifndef __ASSEMBLY__
32570 /*
32571  * WARNING: The C register and register group struct declarations are provided for
32572  * convenience and illustrative purposes. They should, however, be used with
32573  * caution as the C language standard provides no guarantees about the alignment or
32574  * atomicity of device memory accesses. The recommended practice for coding device
32575  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
32576  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
32577  * alt_write_dword() functions for 64 bit registers.
32578  *
32579  * The struct declaration for register ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0.
32580  */
32581 struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_s
32582 {
32583  volatile uint32_t FPGA2SDRAM0_IDLE_EN : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN */
32584  volatile uint32_t FPGA2SDRAM0_IDLEACK_EN : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN */
32585  volatile uint32_t FPGA2SDRAM0_CMD_IDLE_EN : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN */
32586  volatile uint32_t FPGA2SDRAM0_RESP_IDLE_EN : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN */
32587  volatile uint32_t FPGA2SDRAM1_IDLE_EN : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN */
32588  volatile uint32_t FPGA2SDRAM1_IDLEACK_EN : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN */
32589  volatile uint32_t FPGA2SDRAM1_CMD_IDLE_EN : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN */
32590  volatile uint32_t FPGA2SDRAM1_RESP_IDLE_EN : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN */
32591  volatile uint32_t FPGA2SDRAM2_IDLE_EN : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN */
32592  volatile uint32_t FPGA2SDRAM2_IDLEACK_EN : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN */
32593  volatile uint32_t FPGA2SDRAM2_CMD_IDLE_EN : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN */
32594  volatile uint32_t FPGA2SDRAM2_RESP_IDLE_EN : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN */
32595  uint32_t : 20; /* *UNDEFINED* */
32596 };
32597 
32598 /* The typedef declaration for register ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0. */
32599 typedef struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_s ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_t;
32600 #endif /* __ASSEMBLY__ */
32601 
32602 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0 register. */
32603 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_RESET 0x00000000
32604 /* The byte offset of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0 register from the beginning of the component. */
32605 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_OFST 0x10
32606 
32607 /*
32608  * Register : fpga2sdram_manager_main_SidebandManager_FlagInStatus0
32609  *
32610  * Register Layout
32611  *
32612  * Bits | Access | Reset | Description
32613  * :--------|:-------|:--------|:-----------------------------------------------------------------------------------------------------------------
32614  * [0] | R | Unknown | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS
32615  * [1] | R | Unknown | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS
32616  * [2] | R | Unknown | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS
32617  * [3] | R | Unknown | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS
32618  * [4] | R | Unknown | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS
32619  * [5] | R | Unknown | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS
32620  * [6] | R | Unknown | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS
32621  * [7] | R | Unknown | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS
32622  * [8] | R | Unknown | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS
32623  * [9] | R | Unknown | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS
32624  * [10] | R | Unknown | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS
32625  * [11] | R | Unknown | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS
32626  * [31:12] | ??? | Unknown | *UNDEFINED*
32627  *
32628  */
32629 /*
32630  * Field : FPGA2SDRAM0_IDLE_STATUS
32631  *
32632  * FlagIn Status register #0.FPGA2SDRAM0_IDLE_STATUS
32633  *
32634  * Field Access Macros:
32635  *
32636  */
32637 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS register field. */
32638 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS_LSB 0
32639 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS register field. */
32640 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS_MSB 0
32641 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS register field. */
32642 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS_WIDTH 1
32643 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS register field value. */
32644 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS_SET_MSK 0x00000001
32645 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS register field value. */
32646 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS_CLR_MSK 0xfffffffe
32647 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS register field is UNKNOWN. */
32648 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS_RESET 0x0
32649 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS field value from a register. */
32650 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS_GET(value) (((value) & 0x00000001) >> 0)
32651 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS register field value suitable for setting the register. */
32652 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS_SET(value) (((value) << 0) & 0x00000001)
32653 
32654 /*
32655  * Field : FPGA2SDRAM0_IDLEACK_STATUS
32656  *
32657  * FlagIn Status register #1.FPGA2SDRAM0_IDLEACK_STATUS
32658  *
32659  * Field Access Macros:
32660  *
32661  */
32662 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS register field. */
32663 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS_LSB 1
32664 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS register field. */
32665 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS_MSB 1
32666 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS register field. */
32667 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS_WIDTH 1
32668 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS register field value. */
32669 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS_SET_MSK 0x00000002
32670 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS register field value. */
32671 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS_CLR_MSK 0xfffffffd
32672 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS register field is UNKNOWN. */
32673 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS_RESET 0x0
32674 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS field value from a register. */
32675 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS_GET(value) (((value) & 0x00000002) >> 1)
32676 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS register field value suitable for setting the register. */
32677 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS_SET(value) (((value) << 1) & 0x00000002)
32678 
32679 /*
32680  * Field : FPGA2SDRAM0_CMD_IDLE_STATUS
32681  *
32682  * FlagIn Status register #2.FPGA2SDRAM0_CMD_IDLE_STATUS
32683  *
32684  * Field Access Macros:
32685  *
32686  */
32687 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS register field. */
32688 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS_LSB 2
32689 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS register field. */
32690 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS_MSB 2
32691 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS register field. */
32692 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS_WIDTH 1
32693 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS register field value. */
32694 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS_SET_MSK 0x00000004
32695 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS register field value. */
32696 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS_CLR_MSK 0xfffffffb
32697 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS register field is UNKNOWN. */
32698 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS_RESET 0x0
32699 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS field value from a register. */
32700 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS_GET(value) (((value) & 0x00000004) >> 2)
32701 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS register field value suitable for setting the register. */
32702 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS_SET(value) (((value) << 2) & 0x00000004)
32703 
32704 /*
32705  * Field : FPGA2SDRAM0_RESP_IDLE_STATUS
32706  *
32707  * FlagIn Status register #3.FPGA2SDRAM0_RESP_IDLE_STATUS
32708  *
32709  * Field Access Macros:
32710  *
32711  */
32712 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS register field. */
32713 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS_LSB 3
32714 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS register field. */
32715 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS_MSB 3
32716 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS register field. */
32717 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS_WIDTH 1
32718 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS register field value. */
32719 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS_SET_MSK 0x00000008
32720 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS register field value. */
32721 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS_CLR_MSK 0xfffffff7
32722 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS register field is UNKNOWN. */
32723 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS_RESET 0x0
32724 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS field value from a register. */
32725 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS_GET(value) (((value) & 0x00000008) >> 3)
32726 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS register field value suitable for setting the register. */
32727 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS_SET(value) (((value) << 3) & 0x00000008)
32728 
32729 /*
32730  * Field : FPGA2SDRAM1_IDLE_STATUS
32731  *
32732  * FlagIn Status register #4.FPGA2SDRAM1_IDLE_STATUS
32733  *
32734  * Field Access Macros:
32735  *
32736  */
32737 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS register field. */
32738 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS_LSB 4
32739 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS register field. */
32740 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS_MSB 4
32741 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS register field. */
32742 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS_WIDTH 1
32743 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS register field value. */
32744 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS_SET_MSK 0x00000010
32745 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS register field value. */
32746 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS_CLR_MSK 0xffffffef
32747 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS register field is UNKNOWN. */
32748 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS_RESET 0x0
32749 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS field value from a register. */
32750 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS_GET(value) (((value) & 0x00000010) >> 4)
32751 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS register field value suitable for setting the register. */
32752 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS_SET(value) (((value) << 4) & 0x00000010)
32753 
32754 /*
32755  * Field : FPGA2SDRAM1_IDLEACK_STATUS
32756  *
32757  * FlagIn Status register #5.FPGA2SDRAM1_IDLEACK_STATUS
32758  *
32759  * Field Access Macros:
32760  *
32761  */
32762 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS register field. */
32763 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS_LSB 5
32764 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS register field. */
32765 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS_MSB 5
32766 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS register field. */
32767 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS_WIDTH 1
32768 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS register field value. */
32769 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS_SET_MSK 0x00000020
32770 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS register field value. */
32771 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS_CLR_MSK 0xffffffdf
32772 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS register field is UNKNOWN. */
32773 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS_RESET 0x0
32774 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS field value from a register. */
32775 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS_GET(value) (((value) & 0x00000020) >> 5)
32776 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS register field value suitable for setting the register. */
32777 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS_SET(value) (((value) << 5) & 0x00000020)
32778 
32779 /*
32780  * Field : FPGA2SDRAM1_CMD_IDLE_STATUS
32781  *
32782  * FlagIn Status register #6.FPGA2SDRAM1_CMD_IDLE_STATUS
32783  *
32784  * Field Access Macros:
32785  *
32786  */
32787 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS register field. */
32788 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS_LSB 6
32789 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS register field. */
32790 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS_MSB 6
32791 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS register field. */
32792 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS_WIDTH 1
32793 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS register field value. */
32794 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS_SET_MSK 0x00000040
32795 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS register field value. */
32796 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS_CLR_MSK 0xffffffbf
32797 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS register field is UNKNOWN. */
32798 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS_RESET 0x0
32799 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS field value from a register. */
32800 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS_GET(value) (((value) & 0x00000040) >> 6)
32801 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS register field value suitable for setting the register. */
32802 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS_SET(value) (((value) << 6) & 0x00000040)
32803 
32804 /*
32805  * Field : FPGA2SDRAM1_RESP_IDLE_STATUS
32806  *
32807  * FlagIn Status register #7.FPGA2SDRAM1_RESP_IDLE_STATUS
32808  *
32809  * Field Access Macros:
32810  *
32811  */
32812 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS register field. */
32813 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS_LSB 7
32814 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS register field. */
32815 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS_MSB 7
32816 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS register field. */
32817 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS_WIDTH 1
32818 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS register field value. */
32819 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS_SET_MSK 0x00000080
32820 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS register field value. */
32821 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS_CLR_MSK 0xffffff7f
32822 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS register field is UNKNOWN. */
32823 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS_RESET 0x0
32824 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS field value from a register. */
32825 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS_GET(value) (((value) & 0x00000080) >> 7)
32826 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS register field value suitable for setting the register. */
32827 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS_SET(value) (((value) << 7) & 0x00000080)
32828 
32829 /*
32830  * Field : FPGA2SDRAM2_IDLE_STATUS
32831  *
32832  * FlagIn Status register #8.FPGA2SDRAM2_IDLE_STATUS
32833  *
32834  * Field Access Macros:
32835  *
32836  */
32837 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS register field. */
32838 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS_LSB 8
32839 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS register field. */
32840 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS_MSB 8
32841 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS register field. */
32842 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS_WIDTH 1
32843 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS register field value. */
32844 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS_SET_MSK 0x00000100
32845 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS register field value. */
32846 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS_CLR_MSK 0xfffffeff
32847 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS register field is UNKNOWN. */
32848 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS_RESET 0x0
32849 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS field value from a register. */
32850 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS_GET(value) (((value) & 0x00000100) >> 8)
32851 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS register field value suitable for setting the register. */
32852 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS_SET(value) (((value) << 8) & 0x00000100)
32853 
32854 /*
32855  * Field : FPGA2SDRAM2_IDLEACK_STATUS
32856  *
32857  * FlagIn Status register #9.FPGA2SDRAM2_IDLEACK_STATUS
32858  *
32859  * Field Access Macros:
32860  *
32861  */
32862 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS register field. */
32863 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS_LSB 9
32864 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS register field. */
32865 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS_MSB 9
32866 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS register field. */
32867 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS_WIDTH 1
32868 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS register field value. */
32869 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS_SET_MSK 0x00000200
32870 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS register field value. */
32871 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS_CLR_MSK 0xfffffdff
32872 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS register field is UNKNOWN. */
32873 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS_RESET 0x0
32874 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS field value from a register. */
32875 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS_GET(value) (((value) & 0x00000200) >> 9)
32876 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS register field value suitable for setting the register. */
32877 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS_SET(value) (((value) << 9) & 0x00000200)
32878 
32879 /*
32880  * Field : FPGA2SDRAM2_CMD_IDLE_STATUS
32881  *
32882  * FlagIn Status register #10.FPGA2SDRAM2_CMD_IDLE_STATUS
32883  *
32884  * Field Access Macros:
32885  *
32886  */
32887 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS register field. */
32888 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS_LSB 10
32889 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS register field. */
32890 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS_MSB 10
32891 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS register field. */
32892 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS_WIDTH 1
32893 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS register field value. */
32894 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS_SET_MSK 0x00000400
32895 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS register field value. */
32896 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS_CLR_MSK 0xfffffbff
32897 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS register field is UNKNOWN. */
32898 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS_RESET 0x0
32899 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS field value from a register. */
32900 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS_GET(value) (((value) & 0x00000400) >> 10)
32901 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS register field value suitable for setting the register. */
32902 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS_SET(value) (((value) << 10) & 0x00000400)
32903 
32904 /*
32905  * Field : FPGA2SDRAM2_RESP_IDLE_STATUS
32906  *
32907  * FlagIn Status register #11.FPGA2SDRAM2_RESP_IDLE_STATUS
32908  *
32909  * Field Access Macros:
32910  *
32911  */
32912 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS register field. */
32913 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS_LSB 11
32914 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS register field. */
32915 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS_MSB 11
32916 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS register field. */
32917 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS_WIDTH 1
32918 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS register field value. */
32919 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS_SET_MSK 0x00000800
32920 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS register field value. */
32921 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS_CLR_MSK 0xfffff7ff
32922 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS register field is UNKNOWN. */
32923 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS_RESET 0x0
32924 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS field value from a register. */
32925 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS_GET(value) (((value) & 0x00000800) >> 11)
32926 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS register field value suitable for setting the register. */
32927 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS_SET(value) (((value) << 11) & 0x00000800)
32928 
32929 #ifndef __ASSEMBLY__
32930 /*
32931  * WARNING: The C register and register group struct declarations are provided for
32932  * convenience and illustrative purposes. They should, however, be used with
32933  * caution as the C language standard provides no guarantees about the alignment or
32934  * atomicity of device memory accesses. The recommended practice for coding device
32935  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
32936  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
32937  * alt_write_dword() functions for 64 bit registers.
32938  *
32939  * The struct declaration for register ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0.
32940  */
32941 struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_s
32942 {
32943  const volatile uint32_t FPGA2SDRAM0_IDLE_STATUS : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS */
32944  const volatile uint32_t FPGA2SDRAM0_IDLEACK_STATUS : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS */
32945  const volatile uint32_t FPGA2SDRAM0_CMD_IDLE_STATUS : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS */
32946  const volatile uint32_t FPGA2SDRAM0_RESP_IDLE_STATUS : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS */
32947  const volatile uint32_t FPGA2SDRAM1_IDLE_STATUS : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS */
32948  const volatile uint32_t FPGA2SDRAM1_IDLEACK_STATUS : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS */
32949  const volatile uint32_t FPGA2SDRAM1_CMD_IDLE_STATUS : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS */
32950  const volatile uint32_t FPGA2SDRAM1_RESP_IDLE_STATUS : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS */
32951  const volatile uint32_t FPGA2SDRAM2_IDLE_STATUS : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS */
32952  const volatile uint32_t FPGA2SDRAM2_IDLEACK_STATUS : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS */
32953  const volatile uint32_t FPGA2SDRAM2_CMD_IDLE_STATUS : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS */
32954  const volatile uint32_t FPGA2SDRAM2_RESP_IDLE_STATUS : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS */
32955  uint32_t : 20; /* *UNDEFINED* */
32956 };
32957 
32958 /* The typedef declaration for register ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0. */
32959 typedef struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_s ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_t;
32960 #endif /* __ASSEMBLY__ */
32961 
32962 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0 register. */
32963 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_RESET 0x00000000
32964 /* The byte offset of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0 register from the beginning of the component. */
32965 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_OFST 0x14
32966 
32967 /*
32968  * Register : fpga2sdram_manager_main_SidebandManager_FlagOutSet0
32969  *
32970  * Register Layout
32971  *
32972  * Bits | Access | Reset | Description
32973  * :-------|:-------|:--------|:--------------------------------------------------------------------------------------------------------------
32974  * [0] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET
32975  * [1] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET
32976  * [2] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET
32977  * [3] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET
32978  * [4] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET
32979  * [5] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET
32980  * [6] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET
32981  * [7] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET
32982  * [8] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET
32983  * [31:9] | ??? | Unknown | *UNDEFINED*
32984  *
32985  */
32986 /*
32987  * Field : FPGA2SDRAM0_IDLEREQ_SET
32988  *
32989  * FlagOut Set register #0.FPGA2SDRAM0_IDLEREQ_SET
32990  *
32991  * Field Access Macros:
32992  *
32993  */
32994 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET register field. */
32995 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET_LSB 0
32996 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET register field. */
32997 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET_MSB 0
32998 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET register field. */
32999 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET_WIDTH 1
33000 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET register field value. */
33001 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET_SET_MSK 0x00000001
33002 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET register field value. */
33003 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET_CLR_MSK 0xfffffffe
33004 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET register field. */
33005 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET_RESET 0x0
33006 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET field value from a register. */
33007 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET_GET(value) (((value) & 0x00000001) >> 0)
33008 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET register field value suitable for setting the register. */
33009 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET_SET(value) (((value) << 0) & 0x00000001)
33010 
33011 /*
33012  * Field : FPGA2SDRAM0_ENABLE_SET
33013  *
33014  * FlagOut Set register #1.FPGA2SDRAM0_ENABLE_SET
33015  *
33016  * Field Access Macros:
33017  *
33018  */
33019 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET register field. */
33020 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET_LSB 1
33021 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET register field. */
33022 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET_MSB 1
33023 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET register field. */
33024 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET_WIDTH 1
33025 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET register field value. */
33026 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET_SET_MSK 0x00000002
33027 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET register field value. */
33028 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET_CLR_MSK 0xfffffffd
33029 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET register field. */
33030 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET_RESET 0x0
33031 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET field value from a register. */
33032 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET_GET(value) (((value) & 0x00000002) >> 1)
33033 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET register field value suitable for setting the register. */
33034 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET_SET(value) (((value) << 1) & 0x00000002)
33035 
33036 /*
33037  * Field : FPGA2SDRAM0_FORCE_DRAIN_SET
33038  *
33039  * FlagOut Set register #2.FPGA2SDRAM0_FORCE_DRAIN_SET
33040  *
33041  * Field Access Macros:
33042  *
33043  */
33044 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET register field. */
33045 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET_LSB 2
33046 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET register field. */
33047 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET_MSB 2
33048 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET register field. */
33049 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET_WIDTH 1
33050 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET register field value. */
33051 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET_SET_MSK 0x00000004
33052 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET register field value. */
33053 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET_CLR_MSK 0xfffffffb
33054 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET register field. */
33055 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET_RESET 0x0
33056 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET field value from a register. */
33057 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET_GET(value) (((value) & 0x00000004) >> 2)
33058 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET register field value suitable for setting the register. */
33059 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET_SET(value) (((value) << 2) & 0x00000004)
33060 
33061 /*
33062  * Field : FPGA2SDRAM1_IDLEREQ_SET
33063  *
33064  * FlagOut Set register #3.FPGA2SDRAM1_IDLEREQ_SET
33065  *
33066  * Field Access Macros:
33067  *
33068  */
33069 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET register field. */
33070 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET_LSB 3
33071 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET register field. */
33072 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET_MSB 3
33073 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET register field. */
33074 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET_WIDTH 1
33075 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET register field value. */
33076 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET_SET_MSK 0x00000008
33077 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET register field value. */
33078 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET_CLR_MSK 0xfffffff7
33079 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET register field. */
33080 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET_RESET 0x0
33081 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET field value from a register. */
33082 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET_GET(value) (((value) & 0x00000008) >> 3)
33083 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET register field value suitable for setting the register. */
33084 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET_SET(value) (((value) << 3) & 0x00000008)
33085 
33086 /*
33087  * Field : FPGA2SDRAM1_ENABLE_SET
33088  *
33089  * FlagOut Set register #4.FPGA2SDRAM1_ENABLE_SET
33090  *
33091  * Field Access Macros:
33092  *
33093  */
33094 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET register field. */
33095 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET_LSB 4
33096 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET register field. */
33097 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET_MSB 4
33098 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET register field. */
33099 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET_WIDTH 1
33100 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET register field value. */
33101 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET_SET_MSK 0x00000010
33102 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET register field value. */
33103 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET_CLR_MSK 0xffffffef
33104 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET register field. */
33105 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET_RESET 0x0
33106 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET field value from a register. */
33107 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET_GET(value) (((value) & 0x00000010) >> 4)
33108 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET register field value suitable for setting the register. */
33109 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET_SET(value) (((value) << 4) & 0x00000010)
33110 
33111 /*
33112  * Field : FPGA2SDRAM1_FORCE_DRAIN_SET
33113  *
33114  * FlagOut Set register #5.FPGA2SDRAM1_FORCE_DRAIN_SET
33115  *
33116  * Field Access Macros:
33117  *
33118  */
33119 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET register field. */
33120 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET_LSB 5
33121 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET register field. */
33122 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET_MSB 5
33123 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET register field. */
33124 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET_WIDTH 1
33125 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET register field value. */
33126 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET_SET_MSK 0x00000020
33127 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET register field value. */
33128 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET_CLR_MSK 0xffffffdf
33129 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET register field. */
33130 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET_RESET 0x0
33131 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET field value from a register. */
33132 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET_GET(value) (((value) & 0x00000020) >> 5)
33133 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET register field value suitable for setting the register. */
33134 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET_SET(value) (((value) << 5) & 0x00000020)
33135 
33136 /*
33137  * Field : FPGA2SDRAM2_IDLEREQ_SET
33138  *
33139  * FlagOut Set register #6.FPGA2SDRAM2_IDLEREQ_SET
33140  *
33141  * Field Access Macros:
33142  *
33143  */
33144 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET register field. */
33145 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET_LSB 6
33146 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET register field. */
33147 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET_MSB 6
33148 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET register field. */
33149 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET_WIDTH 1
33150 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET register field value. */
33151 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET_SET_MSK 0x00000040
33152 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET register field value. */
33153 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET_CLR_MSK 0xffffffbf
33154 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET register field. */
33155 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET_RESET 0x0
33156 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET field value from a register. */
33157 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET_GET(value) (((value) & 0x00000040) >> 6)
33158 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET register field value suitable for setting the register. */
33159 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET_SET(value) (((value) << 6) & 0x00000040)
33160 
33161 /*
33162  * Field : FPGA2SDRAM2_ENABLE_SET
33163  *
33164  * FlagOut Set register #7.FPGA2SDRAM2_ENABLE_SET
33165  *
33166  * Field Access Macros:
33167  *
33168  */
33169 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET register field. */
33170 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET_LSB 7
33171 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET register field. */
33172 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET_MSB 7
33173 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET register field. */
33174 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET_WIDTH 1
33175 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET register field value. */
33176 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET_SET_MSK 0x00000080
33177 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET register field value. */
33178 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET_CLR_MSK 0xffffff7f
33179 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET register field. */
33180 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET_RESET 0x0
33181 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET field value from a register. */
33182 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET_GET(value) (((value) & 0x00000080) >> 7)
33183 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET register field value suitable for setting the register. */
33184 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET_SET(value) (((value) << 7) & 0x00000080)
33185 
33186 /*
33187  * Field : FPGA2SDRAM2_FORCE_DRAIN_SET
33188  *
33189  * FlagOut Set register #8.FPGA2SDRAM2_FORCE_DRAIN_SET
33190  *
33191  * Field Access Macros:
33192  *
33193  */
33194 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET register field. */
33195 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET_LSB 8
33196 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET register field. */
33197 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET_MSB 8
33198 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET register field. */
33199 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET_WIDTH 1
33200 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET register field value. */
33201 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET_SET_MSK 0x00000100
33202 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET register field value. */
33203 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET_CLR_MSK 0xfffffeff
33204 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET register field. */
33205 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET_RESET 0x0
33206 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET field value from a register. */
33207 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET_GET(value) (((value) & 0x00000100) >> 8)
33208 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET register field value suitable for setting the register. */
33209 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET_SET(value) (((value) << 8) & 0x00000100)
33210 
33211 #ifndef __ASSEMBLY__
33212 /*
33213  * WARNING: The C register and register group struct declarations are provided for
33214  * convenience and illustrative purposes. They should, however, be used with
33215  * caution as the C language standard provides no guarantees about the alignment or
33216  * atomicity of device memory accesses. The recommended practice for coding device
33217  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
33218  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
33219  * alt_write_dword() functions for 64 bit registers.
33220  *
33221  * The struct declaration for register ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0.
33222  */
33223 struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_s
33224 {
33225  volatile uint32_t FPGA2SDRAM0_IDLEREQ_SET : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET */
33226  volatile uint32_t FPGA2SDRAM0_ENABLE_SET : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET */
33227  volatile uint32_t FPGA2SDRAM0_FORCE_DRAIN_SET : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET */
33228  volatile uint32_t FPGA2SDRAM1_IDLEREQ_SET : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET */
33229  volatile uint32_t FPGA2SDRAM1_ENABLE_SET : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET */
33230  volatile uint32_t FPGA2SDRAM1_FORCE_DRAIN_SET : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET */
33231  volatile uint32_t FPGA2SDRAM2_IDLEREQ_SET : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET */
33232  volatile uint32_t FPGA2SDRAM2_ENABLE_SET : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET */
33233  volatile uint32_t FPGA2SDRAM2_FORCE_DRAIN_SET : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET */
33234  uint32_t : 23; /* *UNDEFINED* */
33235 };
33236 
33237 /* The typedef declaration for register ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0. */
33238 typedef struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_s ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_t;
33239 #endif /* __ASSEMBLY__ */
33240 
33241 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0 register. */
33242 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_RESET 0x00000000
33243 /* The byte offset of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0 register from the beginning of the component. */
33244 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_OFST 0x50
33245 
33246 /*
33247  * Register : fpga2sdram_manager_main_SidebandManager_FlagOutClr0
33248  *
33249  * Register Layout
33250  *
33251  * Bits | Access | Reset | Description
33252  * :-------|:-------|:--------|:--------------------------------------------------------------------------------------------------------------
33253  * [0] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR
33254  * [1] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR
33255  * [2] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR
33256  * [3] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR
33257  * [4] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR
33258  * [5] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR
33259  * [6] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR
33260  * [7] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR
33261  * [8] | RW | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR
33262  * [31:9] | ??? | Unknown | *UNDEFINED*
33263  *
33264  */
33265 /*
33266  * Field : FPGA2SDRAM0_IDLEREQ_CLR
33267  *
33268  * FlagOut Clr register #0.FPGA2SDRAM0_IDLEREQ_CLR
33269  *
33270  * Field Access Macros:
33271  *
33272  */
33273 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR register field. */
33274 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR_LSB 0
33275 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR register field. */
33276 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR_MSB 0
33277 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR register field. */
33278 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR_WIDTH 1
33279 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR register field value. */
33280 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR_SET_MSK 0x00000001
33281 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR register field value. */
33282 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR_CLR_MSK 0xfffffffe
33283 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR register field. */
33284 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR_RESET 0x0
33285 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR field value from a register. */
33286 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR_GET(value) (((value) & 0x00000001) >> 0)
33287 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR register field value suitable for setting the register. */
33288 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR_SET(value) (((value) << 0) & 0x00000001)
33289 
33290 /*
33291  * Field : FPGA2SDRAM0_ENABLE_CLR
33292  *
33293  * FlagOut Clr register #1.FPGA2SDRAM0_ENABLE_CLR
33294  *
33295  * Field Access Macros:
33296  *
33297  */
33298 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR register field. */
33299 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR_LSB 1
33300 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR register field. */
33301 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR_MSB 1
33302 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR register field. */
33303 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR_WIDTH 1
33304 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR register field value. */
33305 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR_SET_MSK 0x00000002
33306 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR register field value. */
33307 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR_CLR_MSK 0xfffffffd
33308 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR register field. */
33309 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR_RESET 0x0
33310 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR field value from a register. */
33311 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR_GET(value) (((value) & 0x00000002) >> 1)
33312 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR register field value suitable for setting the register. */
33313 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR_SET(value) (((value) << 1) & 0x00000002)
33314 
33315 /*
33316  * Field : FPGA2SDRAM0_FORCE_DRAIN_CLR
33317  *
33318  * FlagOut Clr register #2.FPGA2SDRAM0_FORCE_DRAIN_CLR
33319  *
33320  * Field Access Macros:
33321  *
33322  */
33323 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR register field. */
33324 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR_LSB 2
33325 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR register field. */
33326 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR_MSB 2
33327 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR register field. */
33328 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR_WIDTH 1
33329 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR register field value. */
33330 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR_SET_MSK 0x00000004
33331 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR register field value. */
33332 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR_CLR_MSK 0xfffffffb
33333 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR register field. */
33334 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR_RESET 0x0
33335 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR field value from a register. */
33336 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR_GET(value) (((value) & 0x00000004) >> 2)
33337 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR register field value suitable for setting the register. */
33338 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR_SET(value) (((value) << 2) & 0x00000004)
33339 
33340 /*
33341  * Field : FPGA2SDRAM1_IDLEREQ_CLR
33342  *
33343  * FlagOut Clr register #3.FPGA2SDRAM1_IDLEREQ_CLR
33344  *
33345  * Field Access Macros:
33346  *
33347  */
33348 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR register field. */
33349 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR_LSB 3
33350 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR register field. */
33351 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR_MSB 3
33352 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR register field. */
33353 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR_WIDTH 1
33354 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR register field value. */
33355 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR_SET_MSK 0x00000008
33356 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR register field value. */
33357 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR_CLR_MSK 0xfffffff7
33358 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR register field. */
33359 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR_RESET 0x0
33360 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR field value from a register. */
33361 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR_GET(value) (((value) & 0x00000008) >> 3)
33362 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR register field value suitable for setting the register. */
33363 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR_SET(value) (((value) << 3) & 0x00000008)
33364 
33365 /*
33366  * Field : FPGA2SDRAM1_ENABLE_CLR
33367  *
33368  * FlagOut Clr register #4.FPGA2SDRAM1_ENABLE_CLR
33369  *
33370  * Field Access Macros:
33371  *
33372  */
33373 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR register field. */
33374 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR_LSB 4
33375 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR register field. */
33376 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR_MSB 4
33377 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR register field. */
33378 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR_WIDTH 1
33379 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR register field value. */
33380 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR_SET_MSK 0x00000010
33381 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR register field value. */
33382 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR_CLR_MSK 0xffffffef
33383 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR register field. */
33384 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR_RESET 0x0
33385 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR field value from a register. */
33386 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR_GET(value) (((value) & 0x00000010) >> 4)
33387 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR register field value suitable for setting the register. */
33388 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR_SET(value) (((value) << 4) & 0x00000010)
33389 
33390 /*
33391  * Field : FPGA2SDRAM1_FORCE_DRAIN_CLR
33392  *
33393  * FlagOut Clr register #5.FPGA2SDRAM1_FORCE_DRAIN_CLR
33394  *
33395  * Field Access Macros:
33396  *
33397  */
33398 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR register field. */
33399 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR_LSB 5
33400 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR register field. */
33401 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR_MSB 5
33402 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR register field. */
33403 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR_WIDTH 1
33404 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR register field value. */
33405 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR_SET_MSK 0x00000020
33406 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR register field value. */
33407 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR_CLR_MSK 0xffffffdf
33408 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR register field. */
33409 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR_RESET 0x0
33410 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR field value from a register. */
33411 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR_GET(value) (((value) & 0x00000020) >> 5)
33412 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR register field value suitable for setting the register. */
33413 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR_SET(value) (((value) << 5) & 0x00000020)
33414 
33415 /*
33416  * Field : FPGA2SDRAM2_IDLEREQ_CLR
33417  *
33418  * FlagOut Clr register #6.FPGA2SDRAM2_IDLEREQ_CLR
33419  *
33420  * Field Access Macros:
33421  *
33422  */
33423 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR register field. */
33424 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR_LSB 6
33425 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR register field. */
33426 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR_MSB 6
33427 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR register field. */
33428 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR_WIDTH 1
33429 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR register field value. */
33430 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR_SET_MSK 0x00000040
33431 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR register field value. */
33432 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR_CLR_MSK 0xffffffbf
33433 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR register field. */
33434 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR_RESET 0x0
33435 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR field value from a register. */
33436 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR_GET(value) (((value) & 0x00000040) >> 6)
33437 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR register field value suitable for setting the register. */
33438 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR_SET(value) (((value) << 6) & 0x00000040)
33439 
33440 /*
33441  * Field : FPGA2SDRAM2_ENABLE_CLR
33442  *
33443  * FlagOut Clr register #7.FPGA2SDRAM2_ENABLE_CLR
33444  *
33445  * Field Access Macros:
33446  *
33447  */
33448 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR register field. */
33449 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR_LSB 7
33450 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR register field. */
33451 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR_MSB 7
33452 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR register field. */
33453 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR_WIDTH 1
33454 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR register field value. */
33455 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR_SET_MSK 0x00000080
33456 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR register field value. */
33457 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR_CLR_MSK 0xffffff7f
33458 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR register field. */
33459 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR_RESET 0x0
33460 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR field value from a register. */
33461 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR_GET(value) (((value) & 0x00000080) >> 7)
33462 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR register field value suitable for setting the register. */
33463 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR_SET(value) (((value) << 7) & 0x00000080)
33464 
33465 /*
33466  * Field : FPGA2SDRAM2_FORCE_DRAIN_CLR
33467  *
33468  * FlagOut Clr register #8.FPGA2SDRAM2_FORCE_DRAIN_CLR
33469  *
33470  * Field Access Macros:
33471  *
33472  */
33473 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR register field. */
33474 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR_LSB 8
33475 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR register field. */
33476 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR_MSB 8
33477 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR register field. */
33478 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR_WIDTH 1
33479 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR register field value. */
33480 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR_SET_MSK 0x00000100
33481 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR register field value. */
33482 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR_CLR_MSK 0xfffffeff
33483 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR register field. */
33484 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR_RESET 0x0
33485 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR field value from a register. */
33486 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR_GET(value) (((value) & 0x00000100) >> 8)
33487 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR register field value suitable for setting the register. */
33488 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR_SET(value) (((value) << 8) & 0x00000100)
33489 
33490 #ifndef __ASSEMBLY__
33491 /*
33492  * WARNING: The C register and register group struct declarations are provided for
33493  * convenience and illustrative purposes. They should, however, be used with
33494  * caution as the C language standard provides no guarantees about the alignment or
33495  * atomicity of device memory accesses. The recommended practice for coding device
33496  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
33497  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
33498  * alt_write_dword() functions for 64 bit registers.
33499  *
33500  * The struct declaration for register ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0.
33501  */
33502 struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_s
33503 {
33504  volatile uint32_t FPGA2SDRAM0_IDLEREQ_CLR : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR */
33505  volatile uint32_t FPGA2SDRAM0_ENABLE_CLR : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR */
33506  volatile uint32_t FPGA2SDRAM0_FORCE_DRAIN_CLR : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR */
33507  volatile uint32_t FPGA2SDRAM1_IDLEREQ_CLR : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR */
33508  volatile uint32_t FPGA2SDRAM1_ENABLE_CLR : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR */
33509  volatile uint32_t FPGA2SDRAM1_FORCE_DRAIN_CLR : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR */
33510  volatile uint32_t FPGA2SDRAM2_IDLEREQ_CLR : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR */
33511  volatile uint32_t FPGA2SDRAM2_ENABLE_CLR : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR */
33512  volatile uint32_t FPGA2SDRAM2_FORCE_DRAIN_CLR : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR */
33513  uint32_t : 23; /* *UNDEFINED* */
33514 };
33515 
33516 /* The typedef declaration for register ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0. */
33517 typedef struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_s ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_t;
33518 #endif /* __ASSEMBLY__ */
33519 
33520 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0 register. */
33521 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_RESET 0x00000000
33522 /* The byte offset of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0 register from the beginning of the component. */
33523 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_OFST 0x54
33524 
33525 /*
33526  * Register : fpga2sdram_manager_main_SidebandManager_FlagOutStatus0
33527  *
33528  * Register Layout
33529  *
33530  * Bits | Access | Reset | Description
33531  * :-------|:-------|:--------|:--------------------------------------------------------------------------------------------------------------------
33532  * [0] | R | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS
33533  * [1] | R | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS
33534  * [2] | R | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS
33535  * [3] | R | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS
33536  * [4] | R | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS
33537  * [5] | R | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS
33538  * [6] | R | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS
33539  * [7] | R | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS
33540  * [8] | R | 0x0 | ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS
33541  * [31:9] | ??? | Unknown | *UNDEFINED*
33542  *
33543  */
33544 /*
33545  * Field : FPGA2SDRAM0_IDLEREQ_STATUS
33546  *
33547  * FlagOut Status register #0.FPGA2SDRAM0_IDLEREQ_STATUS
33548  *
33549  * Field Access Macros:
33550  *
33551  */
33552 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS register field. */
33553 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS_LSB 0
33554 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS register field. */
33555 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS_MSB 0
33556 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS register field. */
33557 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS_WIDTH 1
33558 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS register field value. */
33559 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS_SET_MSK 0x00000001
33560 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS register field value. */
33561 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS_CLR_MSK 0xfffffffe
33562 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS register field. */
33563 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS_RESET 0x0
33564 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS field value from a register. */
33565 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS_GET(value) (((value) & 0x00000001) >> 0)
33566 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS register field value suitable for setting the register. */
33567 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS_SET(value) (((value) << 0) & 0x00000001)
33568 
33569 /*
33570  * Field : FPGA2SDRAM0_ENABLE_STATUS
33571  *
33572  * FlagOut Status register #1.FPGA2SDRAM0_ENABLE_STATUS
33573  *
33574  * Field Access Macros:
33575  *
33576  */
33577 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS register field. */
33578 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS_LSB 1
33579 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS register field. */
33580 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS_MSB 1
33581 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS register field. */
33582 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS_WIDTH 1
33583 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS register field value. */
33584 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS_SET_MSK 0x00000002
33585 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS register field value. */
33586 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS_CLR_MSK 0xfffffffd
33587 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS register field. */
33588 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS_RESET 0x0
33589 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS field value from a register. */
33590 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS_GET(value) (((value) & 0x00000002) >> 1)
33591 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS register field value suitable for setting the register. */
33592 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS_SET(value) (((value) << 1) & 0x00000002)
33593 
33594 /*
33595  * Field : FPGA2SDRAM0_FORCE_DRAIN_STATUS
33596  *
33597  * FlagOut Status register #2.FPGA2SDRAM0_FORCE_DRAIN_STATUS
33598  *
33599  * Field Access Macros:
33600  *
33601  */
33602 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS register field. */
33603 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS_LSB 2
33604 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS register field. */
33605 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS_MSB 2
33606 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS register field. */
33607 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS_WIDTH 1
33608 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS register field value. */
33609 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS_SET_MSK 0x00000004
33610 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS register field value. */
33611 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS_CLR_MSK 0xfffffffb
33612 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS register field. */
33613 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS_RESET 0x0
33614 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS field value from a register. */
33615 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS_GET(value) (((value) & 0x00000004) >> 2)
33616 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS register field value suitable for setting the register. */
33617 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS_SET(value) (((value) << 2) & 0x00000004)
33618 
33619 /*
33620  * Field : FPGA2SDRAM1_IDLEREQ_STATUS
33621  *
33622  * FlagOut Status register #3.FPGA2SDRAM1_IDLEREQ_STATUS
33623  *
33624  * Field Access Macros:
33625  *
33626  */
33627 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS register field. */
33628 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS_LSB 3
33629 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS register field. */
33630 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS_MSB 3
33631 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS register field. */
33632 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS_WIDTH 1
33633 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS register field value. */
33634 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS_SET_MSK 0x00000008
33635 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS register field value. */
33636 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS_CLR_MSK 0xfffffff7
33637 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS register field. */
33638 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS_RESET 0x0
33639 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS field value from a register. */
33640 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS_GET(value) (((value) & 0x00000008) >> 3)
33641 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS register field value suitable for setting the register. */
33642 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS_SET(value) (((value) << 3) & 0x00000008)
33643 
33644 /*
33645  * Field : FPGA2SDRAM1_ENABLE_STATUS
33646  *
33647  * FlagOut Status register #4.FPGA2SDRAM1_ENABLE_STATUS
33648  *
33649  * Field Access Macros:
33650  *
33651  */
33652 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS register field. */
33653 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS_LSB 4
33654 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS register field. */
33655 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS_MSB 4
33656 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS register field. */
33657 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS_WIDTH 1
33658 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS register field value. */
33659 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS_SET_MSK 0x00000010
33660 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS register field value. */
33661 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS_CLR_MSK 0xffffffef
33662 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS register field. */
33663 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS_RESET 0x0
33664 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS field value from a register. */
33665 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS_GET(value) (((value) & 0x00000010) >> 4)
33666 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS register field value suitable for setting the register. */
33667 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS_SET(value) (((value) << 4) & 0x00000010)
33668 
33669 /*
33670  * Field : FPGA2SDRAM1_FORCE_DRAIN_STATUS
33671  *
33672  * FlagOut Status register #5.FPGA2SDRAM1_FORCE_DRAIN_STATUS
33673  *
33674  * Field Access Macros:
33675  *
33676  */
33677 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS register field. */
33678 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS_LSB 5
33679 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS register field. */
33680 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS_MSB 5
33681 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS register field. */
33682 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS_WIDTH 1
33683 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS register field value. */
33684 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS_SET_MSK 0x00000020
33685 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS register field value. */
33686 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS_CLR_MSK 0xffffffdf
33687 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS register field. */
33688 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS_RESET 0x0
33689 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS field value from a register. */
33690 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS_GET(value) (((value) & 0x00000020) >> 5)
33691 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS register field value suitable for setting the register. */
33692 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS_SET(value) (((value) << 5) & 0x00000020)
33693 
33694 /*
33695  * Field : FPGA2SDRAM2_IDLEREQ_STATUS
33696  *
33697  * FlagOut Status register #6.FPGA2SDRAM2_IDLEREQ_STATUS
33698  *
33699  * Field Access Macros:
33700  *
33701  */
33702 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS register field. */
33703 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS_LSB 6
33704 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS register field. */
33705 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS_MSB 6
33706 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS register field. */
33707 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS_WIDTH 1
33708 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS register field value. */
33709 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS_SET_MSK 0x00000040
33710 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS register field value. */
33711 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS_CLR_MSK 0xffffffbf
33712 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS register field. */
33713 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS_RESET 0x0
33714 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS field value from a register. */
33715 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS_GET(value) (((value) & 0x00000040) >> 6)
33716 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS register field value suitable for setting the register. */
33717 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS_SET(value) (((value) << 6) & 0x00000040)
33718 
33719 /*
33720  * Field : FPGA2SDRAM2_ENABLE_STATUS
33721  *
33722  * FlagOut Status register #7.FPGA2SDRAM2_ENABLE_STATUS
33723  *
33724  * Field Access Macros:
33725  *
33726  */
33727 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS register field. */
33728 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS_LSB 7
33729 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS register field. */
33730 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS_MSB 7
33731 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS register field. */
33732 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS_WIDTH 1
33733 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS register field value. */
33734 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS_SET_MSK 0x00000080
33735 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS register field value. */
33736 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS_CLR_MSK 0xffffff7f
33737 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS register field. */
33738 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS_RESET 0x0
33739 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS field value from a register. */
33740 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS_GET(value) (((value) & 0x00000080) >> 7)
33741 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS register field value suitable for setting the register. */
33742 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS_SET(value) (((value) << 7) & 0x00000080)
33743 
33744 /*
33745  * Field : FPGA2SDRAM2_FORCE_DRAIN_STATUS
33746  *
33747  * FlagOut Status register #8.FPGA2SDRAM2_FORCE_DRAIN_STATUS
33748  *
33749  * Field Access Macros:
33750  *
33751  */
33752 /* The Least Significant Bit (LSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS register field. */
33753 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS_LSB 8
33754 /* The Most Significant Bit (MSB) position of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS register field. */
33755 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS_MSB 8
33756 /* The width in bits of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS register field. */
33757 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS_WIDTH 1
33758 /* The mask used to set the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS register field value. */
33759 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS_SET_MSK 0x00000100
33760 /* The mask used to clear the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS register field value. */
33761 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS_CLR_MSK 0xfffffeff
33762 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS register field. */
33763 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS_RESET 0x0
33764 /* Extracts the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS field value from a register. */
33765 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS_GET(value) (((value) & 0x00000100) >> 8)
33766 /* Produces a ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS register field value suitable for setting the register. */
33767 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS_SET(value) (((value) << 8) & 0x00000100)
33768 
33769 #ifndef __ASSEMBLY__
33770 /*
33771  * WARNING: The C register and register group struct declarations are provided for
33772  * convenience and illustrative purposes. They should, however, be used with
33773  * caution as the C language standard provides no guarantees about the alignment or
33774  * atomicity of device memory accesses. The recommended practice for coding device
33775  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
33776  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
33777  * alt_write_dword() functions for 64 bit registers.
33778  *
33779  * The struct declaration for register ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0.
33780  */
33781 struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_s
33782 {
33783  const volatile uint32_t FPGA2SDRAM0_IDLEREQ_STATUS : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS */
33784  const volatile uint32_t FPGA2SDRAM0_ENABLE_STATUS : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS */
33785  const volatile uint32_t FPGA2SDRAM0_FORCE_DRAIN_STATUS : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS */
33786  const volatile uint32_t FPGA2SDRAM1_IDLEREQ_STATUS : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS */
33787  const volatile uint32_t FPGA2SDRAM1_ENABLE_STATUS : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS */
33788  const volatile uint32_t FPGA2SDRAM1_FORCE_DRAIN_STATUS : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS */
33789  const volatile uint32_t FPGA2SDRAM2_IDLEREQ_STATUS : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS */
33790  const volatile uint32_t FPGA2SDRAM2_ENABLE_STATUS : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS */
33791  const volatile uint32_t FPGA2SDRAM2_FORCE_DRAIN_STATUS : 1; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS */
33792  uint32_t : 23; /* *UNDEFINED* */
33793 };
33794 
33795 /* The typedef declaration for register ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0. */
33796 typedef struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_s ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_t;
33797 #endif /* __ASSEMBLY__ */
33798 
33799 /* The reset value of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0 register. */
33800 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_RESET 0x00000000
33801 /* The byte offset of the ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0 register from the beginning of the component. */
33802 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_OFST 0x58
33803 
33804 #ifndef __ASSEMBLY__
33805 /*
33806  * WARNING: The C register and register group struct declarations are provided for
33807  * convenience and illustrative purposes. They should, however, be used with
33808  * caution as the C language standard provides no guarantees about the alignment or
33809  * atomicity of device memory accesses. The recommended practice for coding device
33810  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
33811  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
33812  * alt_write_dword() functions for 64 bit registers.
33813  *
33814  * The struct declaration for register group ALT_MPFE_F2SDR_MGR_MAIN_SBMGR.
33815  */
33816 struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_s
33817 {
33818  volatile ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_t fpga2sdram_manager_main_SidebandManager_Id_CoreId; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID */
33819  volatile ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_t fpga2sdram_manager_main_SidebandManager_Id_RevisionId; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID */
33820  volatile ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_t fpga2sdram_manager_main_SidebandManager_FaultEn; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN */
33821  volatile ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_t fpga2sdram_manager_main_SidebandManager_FaultStatus; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS */
33822  volatile ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_t fpga2sdram_manager_main_SidebandManager_FlagInEn0; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0 */
33823  volatile ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_t fpga2sdram_manager_main_SidebandManager_FlagInStatus0; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0 */
33824  volatile uint32_t _pad_0x18_0x4f[14]; /* *UNDEFINED* */
33825  volatile ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_t fpga2sdram_manager_main_SidebandManager_FlagOutSet0; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0 */
33826  volatile ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_t fpga2sdram_manager_main_SidebandManager_FlagOutClr0; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0 */
33827  volatile ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_t fpga2sdram_manager_main_SidebandManager_FlagOutStatus0; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0 */
33828  volatile uint32_t _pad_0x5c_0x100[41]; /* *UNDEFINED* */
33829 };
33830 
33831 /* The typedef declaration for register group ALT_MPFE_F2SDR_MGR_MAIN_SBMGR. */
33832 typedef struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_s ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_t;
33833 /* The struct declaration for the raw register contents of register group ALT_MPFE_F2SDR_MGR_MAIN_SBMGR. */
33834 struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_raw_s
33835 {
33836  volatile uint32_t fpga2sdram_manager_main_SidebandManager_Id_CoreId; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID */
33837  volatile uint32_t fpga2sdram_manager_main_SidebandManager_Id_RevisionId; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID */
33838  volatile uint32_t fpga2sdram_manager_main_SidebandManager_FaultEn; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN */
33839  volatile uint32_t fpga2sdram_manager_main_SidebandManager_FaultStatus; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS */
33840  volatile uint32_t fpga2sdram_manager_main_SidebandManager_FlagInEn0; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0 */
33841  volatile uint32_t fpga2sdram_manager_main_SidebandManager_FlagInStatus0; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0 */
33842  volatile uint32_t _pad_0x18_0x4f[14]; /* *UNDEFINED* */
33843  volatile uint32_t fpga2sdram_manager_main_SidebandManager_FlagOutSet0; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0 */
33844  volatile uint32_t fpga2sdram_manager_main_SidebandManager_FlagOutClr0; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0 */
33845  volatile uint32_t fpga2sdram_manager_main_SidebandManager_FlagOutStatus0; /* ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0 */
33846  volatile uint32_t _pad_0x5c_0x100[41]; /* *UNDEFINED* */
33847 };
33848 
33849 /* The typedef declaration for the raw register contents of register group ALT_MPFE_F2SDR_MGR_MAIN_SBMGR. */
33850 typedef struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_raw_s ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_raw_t;
33851 #endif /* __ASSEMBLY__ */
33852 
33853 
33854 #ifdef __cplusplus
33855 }
33856 #endif /* __cplusplus */
33857 #endif /* __ALT_SOCAL_MPFE_H__ */
33858