Hardware Libraries  20.1
Stratix 10 SoC Hardware Manager
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Groups
alt_noc_ccu_h2f_main_prb.h
1 /***********************************************************************************
2 * *
3 * Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
4 * *
5 * Redistribution and use in source and binary forms, with or without *
6 * modification, are permitted provided that the following conditions are met: *
7 * *
8 * 1. Redistributions of source code must retain the above copyright notice, *
9 * this list of conditions and the following disclaimer. *
10 * *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, *
12 * this list of conditions and the following disclaimer in the documentation *
13 * and/or other materials provided with the distribution. *
14 * *
15 * 3. Neither the name of the copyright holder nor the names of its contributors *
16 * may be used to endorse or promote products derived from this software without *
17 * specific prior written permission. *
18 * *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
29 * POSSIBILITY OF SUCH DAMAGE. *
30 * *
31 ***********************************************************************************/
32 
33 /* Altera - ALT_NOC_CCU_H2F_MAIN_PRB */
34 
35 #ifndef __ALT_SOCAL_NOC_CCU_H2F_MAIN_PRB_H__
36 #define __ALT_SOCAL_NOC_CCU_H2F_MAIN_PRB_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : NOC_CCU_H2F_MAIN_PRB
50  *
51  */
52 /*
53  * Register : probe_soc2fpga_main_Probe_Id_CoreId
54  *
55  * Register Layout
56  *
57  * Bits | Access | Reset | Description
58  * :-------|:-------|:---------|:--------------------------------------------------------------------------
59  * [7:0] | R | 0x6 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORETYPEID
60  * [31:8] | R | 0xbf79da | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORECHECKSUM
61  *
62  */
63 /*
64  * Field : CORETYPEID
65  *
66  * Field identifying the type of IP.
67  *
68  * Field Access Macros:
69  *
70  */
71 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORETYPEID register field. */
72 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORETYPEID_LSB 0
73 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORETYPEID register field. */
74 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORETYPEID_MSB 7
75 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORETYPEID register field. */
76 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORETYPEID_WIDTH 8
77 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORETYPEID register field value. */
78 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
79 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORETYPEID register field value. */
80 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
81 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORETYPEID register field. */
82 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORETYPEID_RESET 0x6
83 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORETYPEID field value from a register. */
84 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
85 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORETYPEID register field value suitable for setting the register. */
86 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
87 
88 /*
89  * Field : CORECHECKSUM
90  *
91  * Field containing a checksum of the parameters of the IP.
92  *
93  * Field Access Macros:
94  *
95  */
96 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORECHECKSUM register field. */
97 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORECHECKSUM_LSB 8
98 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORECHECKSUM register field. */
99 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORECHECKSUM_MSB 31
100 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORECHECKSUM register field. */
101 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORECHECKSUM_WIDTH 24
102 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORECHECKSUM register field value. */
103 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
104 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORECHECKSUM register field value. */
105 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
106 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORECHECKSUM register field. */
107 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORECHECKSUM_RESET 0xbf79da
108 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORECHECKSUM field value from a register. */
109 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
110 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORECHECKSUM register field value suitable for setting the register. */
111 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
112 
113 #ifndef __ASSEMBLY__
114 /*
115  * WARNING: The C register and register group struct declarations are provided for
116  * convenience and illustrative purposes. They should, however, be used with
117  * caution as the C language standard provides no guarantees about the alignment or
118  * atomicity of device memory accesses. The recommended practice for coding device
119  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
120  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
121  * alt_write_dword() functions for 64 bit registers.
122  *
123  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID.
124  */
125 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_s
126 {
127  const volatile uint32_t CORETYPEID : 8; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORETYPEID */
128  const volatile uint32_t CORECHECKSUM : 24; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_CORECHECKSUM */
129 };
130 
131 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID. */
132 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_t;
133 #endif /* __ASSEMBLY__ */
134 
135 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID register. */
136 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_RESET 0xbf79da06
137 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID register from the beginning of the component. */
138 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_OFST 0x0
139 
140 /*
141  * Register : probe_soc2fpga_main_Probe_Id_RevisionId
142  *
143  * Register Layout
144  *
145  * Bits | Access | Reset | Description
146  * :-------|:-------|:------|:---------------------------------------------------------------------------
147  * [7:0] | R | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_USERID
148  * [31:8] | R | 0x148 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_FLEXNOCID
149  *
150  */
151 /*
152  * Field : USERID
153  *
154  * Field containing a user defined value, not used anywhere inside the IP itself.
155  *
156  * Field Access Macros:
157  *
158  */
159 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_USERID register field. */
160 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_USERID_LSB 0
161 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_USERID register field. */
162 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_USERID_MSB 7
163 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_USERID register field. */
164 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_USERID_WIDTH 8
165 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_USERID register field value. */
166 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_USERID_SET_MSK 0x000000ff
167 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_USERID register field value. */
168 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
169 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_USERID register field. */
170 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_USERID_RESET 0x0
171 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_USERID field value from a register. */
172 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
173 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_USERID register field value suitable for setting the register. */
174 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
175 
176 /*
177  * Field : FLEXNOCID
178  *
179  * Field containing the build revision of the software used to generate the IP HDL
180  * code.
181  *
182  * Field Access Macros:
183  *
184  */
185 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_FLEXNOCID register field. */
186 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_LSB 8
187 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_FLEXNOCID register field. */
188 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_MSB 31
189 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_FLEXNOCID register field. */
190 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_WIDTH 24
191 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_FLEXNOCID register field value. */
192 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
193 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_FLEXNOCID register field value. */
194 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
195 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_FLEXNOCID register field. */
196 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_RESET 0x148
197 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_FLEXNOCID field value from a register. */
198 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
199 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_FLEXNOCID register field value suitable for setting the register. */
200 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
201 
202 #ifndef __ASSEMBLY__
203 /*
204  * WARNING: The C register and register group struct declarations are provided for
205  * convenience and illustrative purposes. They should, however, be used with
206  * caution as the C language standard provides no guarantees about the alignment or
207  * atomicity of device memory accesses. The recommended practice for coding device
208  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
209  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
210  * alt_write_dword() functions for 64 bit registers.
211  *
212  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID.
213  */
214 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_s
215 {
216  const volatile uint32_t USERID : 8; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_USERID */
217  const volatile uint32_t FLEXNOCID : 24; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_FLEXNOCID */
218 };
219 
220 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID. */
221 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_t;
222 #endif /* __ASSEMBLY__ */
223 
224 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID register. */
225 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_RESET 0x00014800
226 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID register from the beginning of the component. */
227 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_OFST 0x4
228 
229 /*
230  * Register : probe_soc2fpga_main_Probe_MainCtl
231  *
232  * Register MainCtl contains probe global control bits. The register has seven bit
233  * fields:
234  *
235  * Register Layout
236  *
237  * Bits | Access | Reset | Description
238  * :-------|:-------|:--------|:-------------------------------------------------------------------------------------
239  * [0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ERREN
240  * [1] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_TRACEEN
241  * [2] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_PAYLOADEN
242  * [3] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATEN
243  * [4] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ALARMEN
244  * [5] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATCONDDUMP
245  * [6] | R | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_INTRUSIVEMODE
246  * [7] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN
247  * [31:8] | ??? | Unknown | *UNDEFINED*
248  *
249  */
250 /*
251  * Field : ERREN
252  *
253  * Register field ErrEn enables the probe to send on the ObsTx output any packet
254  * with Error status, independently of filtering mechanisms, thus constituting a
255  * simple supplementary global filter.
256  *
257  * Field Access Macros:
258  *
259  */
260 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ERREN register field. */
261 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ERREN_LSB 0
262 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ERREN register field. */
263 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ERREN_MSB 0
264 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ERREN register field. */
265 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ERREN_WIDTH 1
266 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ERREN register field value. */
267 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ERREN_SET_MSK 0x00000001
268 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ERREN register field value. */
269 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ERREN_CLR_MSK 0xfffffffe
270 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ERREN register field. */
271 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ERREN_RESET 0x0
272 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ERREN field value from a register. */
273 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ERREN_GET(value) (((value) & 0x00000001) >> 0)
274 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ERREN register field value suitable for setting the register. */
275 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ERREN_SET(value) (((value) << 0) & 0x00000001)
276 
277 /*
278  * Field : TRACEEN
279  *
280  * Register field TraceEn enables the probe to send filtered packets (Trace) on the
281  * ObsTx observation output.
282  *
283  * Field Access Macros:
284  *
285  */
286 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_TRACEEN register field. */
287 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_TRACEEN_LSB 1
288 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_TRACEEN register field. */
289 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_TRACEEN_MSB 1
290 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_TRACEEN register field. */
291 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_TRACEEN_WIDTH 1
292 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_TRACEEN register field value. */
293 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_TRACEEN_SET_MSK 0x00000002
294 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_TRACEEN register field value. */
295 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_TRACEEN_CLR_MSK 0xfffffffd
296 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_TRACEEN register field. */
297 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_TRACEEN_RESET 0x0
298 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_TRACEEN field value from a register. */
299 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_TRACEEN_GET(value) (((value) & 0x00000002) >> 1)
300 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_TRACEEN register field value suitable for setting the register. */
301 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_TRACEEN_SET(value) (((value) << 1) & 0x00000002)
302 
303 /*
304  * Field : PAYLOADEN
305  *
306  * Register field PayloadEn, when set to 1, enables traces to contain headers and
307  * payload. When set ot 0, only headers are reported.
308  *
309  * Field Access Macros:
310  *
311  */
312 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_PAYLOADEN register field. */
313 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_PAYLOADEN_LSB 2
314 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_PAYLOADEN register field. */
315 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_PAYLOADEN_MSB 2
316 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_PAYLOADEN register field. */
317 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_PAYLOADEN_WIDTH 1
318 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_PAYLOADEN register field value. */
319 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_PAYLOADEN_SET_MSK 0x00000004
320 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_PAYLOADEN register field value. */
321 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_PAYLOADEN_CLR_MSK 0xfffffffb
322 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_PAYLOADEN register field. */
323 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_PAYLOADEN_RESET 0x0
324 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_PAYLOADEN field value from a register. */
325 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_PAYLOADEN_GET(value) (((value) & 0x00000004) >> 2)
326 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_PAYLOADEN register field value suitable for setting the register. */
327 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_PAYLOADEN_SET(value) (((value) << 2) & 0x00000004)
328 
329 /*
330  * Field : STATEN
331  *
332  * When set to 1, register field StatEn enables statistics profiling. The probe
333  * sendS statistics results to the output for signal ObsTx. All statistics counters
334  * are cleared when the StatEn bit goes from 0 to 1. When set to 0, counters are
335  * disabled.
336  *
337  * Field Access Macros:
338  *
339  */
340 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATEN register field. */
341 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATEN_LSB 3
342 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATEN register field. */
343 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATEN_MSB 3
344 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATEN register field. */
345 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATEN_WIDTH 1
346 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATEN register field value. */
347 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATEN_SET_MSK 0x00000008
348 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATEN register field value. */
349 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATEN_CLR_MSK 0xfffffff7
350 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATEN register field. */
351 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATEN_RESET 0x0
352 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATEN field value from a register. */
353 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATEN_GET(value) (((value) & 0x00000008) >> 3)
354 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATEN register field value suitable for setting the register. */
355 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATEN_SET(value) (((value) << 3) & 0x00000008)
356 
357 /*
358  * Field : ALARMEN
359  *
360  * When set, register field AlarmEn enables the probe to collect alarm-related
361  * information. When the register field bit is null, both TraceAlarm and StatAlarm
362  * outputs are driven to 0.
363  *
364  * Field Access Macros:
365  *
366  */
367 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ALARMEN register field. */
368 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ALARMEN_LSB 4
369 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ALARMEN register field. */
370 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ALARMEN_MSB 4
371 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ALARMEN register field. */
372 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ALARMEN_WIDTH 1
373 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ALARMEN register field value. */
374 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ALARMEN_SET_MSK 0x00000010
375 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ALARMEN register field value. */
376 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ALARMEN_CLR_MSK 0xffffffef
377 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ALARMEN register field. */
378 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ALARMEN_RESET 0x0
379 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ALARMEN field value from a register. */
380 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ALARMEN_GET(value) (((value) & 0x00000010) >> 4)
381 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ALARMEN register field value suitable for setting the register. */
382 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ALARMEN_SET(value) (((value) << 4) & 0x00000010)
383 
384 /*
385  * Field : STATCONDDUMP
386  *
387  * When set, register field StatCondDump enables the dump of a statistics frame to
388  * the range of counter values set for registers StatAlarmMin, StatAlarmMax, and
389  * AlarmMode. This field also renders register StatAlarmStatus inoperative. When
390  * parameter statisticsCounterAlarm is set to False, the StatCondDump register bit
391  * is reserved.
392  *
393  * Field Access Macros:
394  *
395  */
396 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATCONDDUMP register field. */
397 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATCONDDUMP_LSB 5
398 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATCONDDUMP register field. */
399 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATCONDDUMP_MSB 5
400 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATCONDDUMP register field. */
401 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATCONDDUMP_WIDTH 1
402 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATCONDDUMP register field value. */
403 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATCONDDUMP_SET_MSK 0x00000020
404 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATCONDDUMP register field value. */
405 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATCONDDUMP_CLR_MSK 0xffffffdf
406 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATCONDDUMP register field. */
407 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATCONDDUMP_RESET 0x0
408 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATCONDDUMP field value from a register. */
409 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATCONDDUMP_GET(value) (((value) & 0x00000020) >> 5)
410 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATCONDDUMP register field value suitable for setting the register. */
411 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATCONDDUMP_SET(value) (((value) << 5) & 0x00000020)
412 
413 /*
414  * Field : INTRUSIVEMODE
415  *
416  * When set to 1, register field IntrusiveMode enables trace operation in Intrusive
417  * flow-control mode. When set to 0, the register enables trace operation in
418  * Overflow flow-control mode
419  *
420  * Field Access Macros:
421  *
422  */
423 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_INTRUSIVEMODE register field. */
424 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_LSB 6
425 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_INTRUSIVEMODE register field. */
426 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MSB 6
427 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_INTRUSIVEMODE register field. */
428 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_WIDTH 1
429 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_INTRUSIVEMODE register field value. */
430 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SET_MSK 0x00000040
431 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_INTRUSIVEMODE register field value. */
432 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_CLR_MSK 0xffffffbf
433 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_INTRUSIVEMODE register field. */
434 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_RESET 0x0
435 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_INTRUSIVEMODE field value from a register. */
436 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_GET(value) (((value) & 0x00000040) >> 6)
437 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_INTRUSIVEMODE register field value suitable for setting the register. */
438 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SET(value) (((value) << 6) & 0x00000040)
439 
440 /*
441  * Field : FILTBYTEALWAYSCHAINABLEEN
442  *
443  * When set to 0, filters are mapped to all statistic counters when counting bytes
444  * or enabled bytes. Therefore, only filter events mapped to even counters can be
445  * counted using a pair of chained counters.When set to 1, filters are mapped only
446  * to even statistic counters when counting bytes or enabled bytes. Thus events
447  * from any filter can be counted using a pair of chained counters.
448  *
449  * Field Access Macros:
450  *
451  */
452 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
453 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_LSB 7
454 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
455 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MSB 7
456 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
457 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_WIDTH 1
458 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field value. */
459 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET_MSK 0x00000080
460 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field value. */
461 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_CLR_MSK 0xffffff7f
462 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
463 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_RESET 0x0
464 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN field value from a register. */
465 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_GET(value) (((value) & 0x00000080) >> 7)
466 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field value suitable for setting the register. */
467 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET(value) (((value) << 7) & 0x00000080)
468 
469 #ifndef __ASSEMBLY__
470 /*
471  * WARNING: The C register and register group struct declarations are provided for
472  * convenience and illustrative purposes. They should, however, be used with
473  * caution as the C language standard provides no guarantees about the alignment or
474  * atomicity of device memory accesses. The recommended practice for coding device
475  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
476  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
477  * alt_write_dword() functions for 64 bit registers.
478  *
479  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL.
480  */
481 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_s
482 {
483  volatile uint32_t ERREN : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ERREN */
484  volatile uint32_t TRACEEN : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_TRACEEN */
485  volatile uint32_t PAYLOADEN : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_PAYLOADEN */
486  volatile uint32_t STATEN : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATEN */
487  volatile uint32_t ALARMEN : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_ALARMEN */
488  volatile uint32_t STATCONDDUMP : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_STATCONDDUMP */
489  const volatile uint32_t INTRUSIVEMODE : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_INTRUSIVEMODE */
490  volatile uint32_t FILTBYTEALWAYSCHAINABLEEN : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN */
491  uint32_t : 24; /* *UNDEFINED* */
492 };
493 
494 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL. */
495 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_t;
496 #endif /* __ASSEMBLY__ */
497 
498 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL register. */
499 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_RESET 0x00000000
500 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL register from the beginning of the component. */
501 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_OFST 0x8
502 
503 /*
504  * Register : probe_soc2fpga_main_Probe_CfgCtl
505  *
506  * Register Layout
507  *
508  * Bits | Access | Reset | Description
509  * :-------|:-------|:--------|:-------------------------------------------------------------------
510  * [0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_GLOBALEN
511  * [1] | R | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_ACTIVE
512  * [31:2] | ??? | Unknown | *UNDEFINED*
513  *
514  */
515 /*
516  * Field : GLOBALEN
517  *
518  * Field Access Macros:
519  *
520  */
521 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_GLOBALEN register field. */
522 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_GLOBALEN_LSB 0
523 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_GLOBALEN register field. */
524 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_GLOBALEN_MSB 0
525 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_GLOBALEN register field. */
526 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_GLOBALEN_WIDTH 1
527 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_GLOBALEN register field value. */
528 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_GLOBALEN_SET_MSK 0x00000001
529 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_GLOBALEN register field value. */
530 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_GLOBALEN_CLR_MSK 0xfffffffe
531 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_GLOBALEN register field. */
532 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_GLOBALEN_RESET 0x0
533 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_GLOBALEN field value from a register. */
534 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_GLOBALEN_GET(value) (((value) & 0x00000001) >> 0)
535 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_GLOBALEN register field value suitable for setting the register. */
536 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_GLOBALEN_SET(value) (((value) << 0) & 0x00000001)
537 
538 /*
539  * Field : ACTIVE
540  *
541  * Field Access Macros:
542  *
543  */
544 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_ACTIVE register field. */
545 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_ACTIVE_LSB 1
546 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_ACTIVE register field. */
547 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_ACTIVE_MSB 1
548 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_ACTIVE register field. */
549 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_ACTIVE_WIDTH 1
550 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_ACTIVE register field value. */
551 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_ACTIVE_SET_MSK 0x00000002
552 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_ACTIVE register field value. */
553 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_ACTIVE_CLR_MSK 0xfffffffd
554 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_ACTIVE register field. */
555 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_ACTIVE_RESET 0x0
556 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_ACTIVE field value from a register. */
557 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_ACTIVE_GET(value) (((value) & 0x00000002) >> 1)
558 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_ACTIVE register field value suitable for setting the register. */
559 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_ACTIVE_SET(value) (((value) << 1) & 0x00000002)
560 
561 #ifndef __ASSEMBLY__
562 /*
563  * WARNING: The C register and register group struct declarations are provided for
564  * convenience and illustrative purposes. They should, however, be used with
565  * caution as the C language standard provides no guarantees about the alignment or
566  * atomicity of device memory accesses. The recommended practice for coding device
567  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
568  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
569  * alt_write_dword() functions for 64 bit registers.
570  *
571  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL.
572  */
573 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_s
574 {
575  volatile uint32_t GLOBALEN : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_GLOBALEN */
576  const volatile uint32_t ACTIVE : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_ACTIVE */
577  uint32_t : 30; /* *UNDEFINED* */
578 };
579 
580 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL. */
581 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_t;
582 #endif /* __ASSEMBLY__ */
583 
584 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL register. */
585 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_RESET 0x00000000
586 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL register from the beginning of the component. */
587 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_OFST 0xc
588 
589 /*
590  * Register : probe_soc2fpga_main_Probe_TracePortSel
591  *
592  * Register Layout
593  *
594  * Bits | Access | Reset | Description
595  * :-------|:-------|:--------|:-----------------------------------------------------------------------------
596  * [0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL
597  * [31:1] | ??? | Unknown | *UNDEFINED*
598  *
599  */
600 /*
601  * Field : TRACEPORTSEL
602  *
603  * Register TracePortSel indicates which generic protocol link is currently being
604  * observed by trace logic.The number of bits in register TracePortSel is equal to
605  * log2 of the value set for parameter nPort.The register can be updated at any
606  * time, but changes only become effective at packet boundaries.
607  *
608  * Field Access Macros:
609  *
610  */
611 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL register field. */
612 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL_LSB 0
613 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL register field. */
614 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL_MSB 0
615 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL register field. */
616 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL_WIDTH 1
617 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL register field value. */
618 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL_SET_MSK 0x00000001
619 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL register field value. */
620 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL_CLR_MSK 0xfffffffe
621 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL register field. */
622 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL_RESET 0x0
623 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL field value from a register. */
624 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL_GET(value) (((value) & 0x00000001) >> 0)
625 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL register field value suitable for setting the register. */
626 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL_SET(value) (((value) << 0) & 0x00000001)
627 
628 #ifndef __ASSEMBLY__
629 /*
630  * WARNING: The C register and register group struct declarations are provided for
631  * convenience and illustrative purposes. They should, however, be used with
632  * caution as the C language standard provides no guarantees about the alignment or
633  * atomicity of device memory accesses. The recommended practice for coding device
634  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
635  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
636  * alt_write_dword() functions for 64 bit registers.
637  *
638  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL.
639  */
640 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_s
641 {
642  volatile uint32_t TRACEPORTSEL : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL */
643  uint32_t : 31; /* *UNDEFINED* */
644 };
645 
646 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL. */
647 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_t;
648 #endif /* __ASSEMBLY__ */
649 
650 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL register. */
651 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_RESET 0x00000000
652 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL register from the beginning of the component. */
653 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_OFST 0x10
654 
655 /*
656  * Register : probe_soc2fpga_main_Probe_FilterLut
657  *
658  * Register Layout
659  *
660  * Bits | Access | Reset | Description
661  * :-------|:-------|:--------|:-----------------------------------------------------------------------
662  * [3:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_FILTERLUT
663  * [31:4] | ??? | Unknown | *UNDEFINED*
664  *
665  */
666 /*
667  * Field : FILTERLUT
668  *
669  * Register FilterLut contains a look-up table that is used to combine filter
670  * outputs in order to trace packets. Packet tracing is enabled when the FilterLut
671  * bit of index (FNout ... F0out) is equal to 1.The number of bits in register
672  * FilterLut is determined by the setting for parameter nFilter, calculated as
673  * 2**nFilter.When parameter nFilter is set to None, FilterLut is reserved.
674  *
675  * Field Access Macros:
676  *
677  */
678 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_FILTERLUT register field. */
679 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_FILTERLUT_LSB 0
680 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_FILTERLUT register field. */
681 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_FILTERLUT_MSB 3
682 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_FILTERLUT register field. */
683 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_FILTERLUT_WIDTH 4
684 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_FILTERLUT register field value. */
685 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_FILTERLUT_SET_MSK 0x0000000f
686 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_FILTERLUT register field value. */
687 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_FILTERLUT_CLR_MSK 0xfffffff0
688 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_FILTERLUT register field. */
689 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_FILTERLUT_RESET 0x0
690 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_FILTERLUT field value from a register. */
691 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_FILTERLUT_GET(value) (((value) & 0x0000000f) >> 0)
692 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_FILTERLUT register field value suitable for setting the register. */
693 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_FILTERLUT_SET(value) (((value) << 0) & 0x0000000f)
694 
695 #ifndef __ASSEMBLY__
696 /*
697  * WARNING: The C register and register group struct declarations are provided for
698  * convenience and illustrative purposes. They should, however, be used with
699  * caution as the C language standard provides no guarantees about the alignment or
700  * atomicity of device memory accesses. The recommended practice for coding device
701  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
702  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
703  * alt_write_dword() functions for 64 bit registers.
704  *
705  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT.
706  */
707 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_s
708 {
709  volatile uint32_t FILTERLUT : 4; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_FILTERLUT */
710  uint32_t : 28; /* *UNDEFINED* */
711 };
712 
713 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT. */
714 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_t;
715 #endif /* __ASSEMBLY__ */
716 
717 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT register. */
718 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_RESET 0x00000000
719 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT register from the beginning of the component. */
720 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_OFST 0x14
721 
722 /*
723  * Register : probe_soc2fpga_main_Probe_TraceAlarmEn
724  *
725  * Register Layout
726  *
727  * Bits | Access | Reset | Description
728  * :-------|:-------|:--------|:-----------------------------------------------------------------------------
729  * [2:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN
730  * [31:3] | ??? | Unknown | *UNDEFINED*
731  *
732  */
733 /*
734  * Field : TRACEALARMEN
735  *
736  * Register TraceAlarmEn controls which lookup table or filter can set the
737  * TraceAlarm signal output once the trace alarm status is set. The number of bits
738  * in register TraceAlarmEn is determined by the value set for parameter nFilter +
739  * 1.Bit nFilter controls the lookup table output, and bits nFilter:0 control the
740  * corresponding filter output. When parameter nFilter is set to None, TraceAlarmEn
741  * is reserved.
742  *
743  * Field Access Macros:
744  *
745  */
746 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN register field. */
747 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_LSB 0
748 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN register field. */
749 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_MSB 2
750 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN register field. */
751 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_WIDTH 3
752 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN register field value. */
753 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_SET_MSK 0x00000007
754 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN register field value. */
755 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_CLR_MSK 0xfffffff8
756 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN register field. */
757 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_RESET 0x0
758 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN field value from a register. */
759 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_GET(value) (((value) & 0x00000007) >> 0)
760 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN register field value suitable for setting the register. */
761 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_SET(value) (((value) << 0) & 0x00000007)
762 
763 #ifndef __ASSEMBLY__
764 /*
765  * WARNING: The C register and register group struct declarations are provided for
766  * convenience and illustrative purposes. They should, however, be used with
767  * caution as the C language standard provides no guarantees about the alignment or
768  * atomicity of device memory accesses. The recommended practice for coding device
769  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
770  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
771  * alt_write_dword() functions for 64 bit registers.
772  *
773  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN.
774  */
775 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_s
776 {
777  volatile uint32_t TRACEALARMEN : 3; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN */
778  uint32_t : 29; /* *UNDEFINED* */
779 };
780 
781 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN. */
782 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_t;
783 #endif /* __ASSEMBLY__ */
784 
785 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN register. */
786 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_RESET 0x00000000
787 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN register from the beginning of the component. */
788 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_OFST 0x18
789 
790 /*
791  * Register : probe_soc2fpga_main_Probe_TraceAlarmStatus
792  *
793  * Register Layout
794  *
795  * Bits | Access | Reset | Description
796  * :-------|:-------|:--------|:-------------------------------------------------------------------------------------
797  * [2:0] | R | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS
798  * [31:3] | ??? | Unknown | *UNDEFINED*
799  *
800  */
801 /*
802  * Field : TRACEALARMSTATUS
803  *
804  * Register TraceAlarmStatus is a read-only register that indicates which lookup
805  * table or filter has been matched by a packet, independently of register
806  * TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is
807  * determined by the value set for parameter nFilter + 1.When nFilter is set to
808  * None, TraceAlarmStatus is reserved.
809  *
810  * Field Access Macros:
811  *
812  */
813 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS register field. */
814 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_LSB 0
815 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS register field. */
816 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_MSB 2
817 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS register field. */
818 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_WIDTH 3
819 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS register field value. */
820 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_SET_MSK 0x00000007
821 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS register field value. */
822 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_CLR_MSK 0xfffffff8
823 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS register field. */
824 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_RESET 0x0
825 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS field value from a register. */
826 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_GET(value) (((value) & 0x00000007) >> 0)
827 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS register field value suitable for setting the register. */
828 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_SET(value) (((value) << 0) & 0x00000007)
829 
830 #ifndef __ASSEMBLY__
831 /*
832  * WARNING: The C register and register group struct declarations are provided for
833  * convenience and illustrative purposes. They should, however, be used with
834  * caution as the C language standard provides no guarantees about the alignment or
835  * atomicity of device memory accesses. The recommended practice for coding device
836  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
837  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
838  * alt_write_dword() functions for 64 bit registers.
839  *
840  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS.
841  */
842 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_s
843 {
844  const volatile uint32_t TRACEALARMSTATUS : 3; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS */
845  uint32_t : 29; /* *UNDEFINED* */
846 };
847 
848 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS. */
849 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_t;
850 #endif /* __ASSEMBLY__ */
851 
852 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS register. */
853 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_RESET 0x00000000
854 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS register from the beginning of the component. */
855 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_OFST 0x1c
856 
857 /*
858  * Register : probe_soc2fpga_main_Probe_TraceAlarmClr
859  *
860  * Register Layout
861  *
862  * Bits | Access | Reset | Description
863  * :-------|:-------|:--------|:-------------------------------------------------------------------------------
864  * [2:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR
865  * [31:3] | ??? | Unknown | *UNDEFINED*
866  *
867  */
868 /*
869  * Field : TRACEALARMCLR
870  *
871  * Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in
872  * register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal
873  * to (nFilter + 1). When nFilter is set to 0, TraceAlarmClr is reserved.NOTE The
874  * written value is not stored in TraceAlarmClr. A read always returns 0.
875  *
876  * Field Access Macros:
877  *
878  */
879 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR register field. */
880 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_LSB 0
881 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR register field. */
882 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_MSB 2
883 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR register field. */
884 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_WIDTH 3
885 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR register field value. */
886 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_SET_MSK 0x00000007
887 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR register field value. */
888 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_CLR_MSK 0xfffffff8
889 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR register field. */
890 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_RESET 0x0
891 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR field value from a register. */
892 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_GET(value) (((value) & 0x00000007) >> 0)
893 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR register field value suitable for setting the register. */
894 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_SET(value) (((value) << 0) & 0x00000007)
895 
896 #ifndef __ASSEMBLY__
897 /*
898  * WARNING: The C register and register group struct declarations are provided for
899  * convenience and illustrative purposes. They should, however, be used with
900  * caution as the C language standard provides no guarantees about the alignment or
901  * atomicity of device memory accesses. The recommended practice for coding device
902  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
903  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
904  * alt_write_dword() functions for 64 bit registers.
905  *
906  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR.
907  */
908 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_s
909 {
910  volatile uint32_t TRACEALARMCLR : 3; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR */
911  uint32_t : 29; /* *UNDEFINED* */
912 };
913 
914 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR. */
915 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_t;
916 #endif /* __ASSEMBLY__ */
917 
918 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR register. */
919 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_RESET 0x00000000
920 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR register from the beginning of the component. */
921 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_OFST 0x20
922 
923 /*
924  * Register : probe_soc2fpga_main_Probe_StatPeriod
925  *
926  * Register Layout
927  *
928  * Bits | Access | Reset | Description
929  * :-------|:-------|:--------|:-------------------------------------------------------------------------
930  * [4:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_STATPERIOD
931  * [31:5] | ??? | Unknown | *UNDEFINED*
932  *
933  */
934 /*
935  * Field : STATPERIOD
936  *
937  * Register StatPeriod is a 5-bit register that sets a period, within a range of 2
938  * cycles to 2 gigacycles, during which statistics are collected before being
939  * dumped automatically. Setting the register implicitly enables automatic mode
940  * operation for statistics collection. The period is calculated with the formula:
941  * N_Cycle = 2**StatPeriodWhen register StatPeriod is set to its default value 0,
942  * automatic dump mode is disabled, and register StatGo is activated for manual
943  * mode operation. Note: When parameter statisticsCollection is set to False,
944  * StatPeriod is reserved.
945  *
946  * Field Access Macros:
947  *
948  */
949 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_STATPERIOD register field. */
950 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_STATPERIOD_LSB 0
951 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_STATPERIOD register field. */
952 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_STATPERIOD_MSB 4
953 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_STATPERIOD register field. */
954 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_STATPERIOD_WIDTH 5
955 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_STATPERIOD register field value. */
956 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_STATPERIOD_SET_MSK 0x0000001f
957 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_STATPERIOD register field value. */
958 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_STATPERIOD_CLR_MSK 0xffffffe0
959 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_STATPERIOD register field. */
960 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_STATPERIOD_RESET 0x0
961 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_STATPERIOD field value from a register. */
962 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_STATPERIOD_GET(value) (((value) & 0x0000001f) >> 0)
963 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_STATPERIOD register field value suitable for setting the register. */
964 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_STATPERIOD_SET(value) (((value) << 0) & 0x0000001f)
965 
966 #ifndef __ASSEMBLY__
967 /*
968  * WARNING: The C register and register group struct declarations are provided for
969  * convenience and illustrative purposes. They should, however, be used with
970  * caution as the C language standard provides no guarantees about the alignment or
971  * atomicity of device memory accesses. The recommended practice for coding device
972  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
973  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
974  * alt_write_dword() functions for 64 bit registers.
975  *
976  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD.
977  */
978 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_s
979 {
980  volatile uint32_t STATPERIOD : 5; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_STATPERIOD */
981  uint32_t : 27; /* *UNDEFINED* */
982 };
983 
984 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD. */
985 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_t;
986 #endif /* __ASSEMBLY__ */
987 
988 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD register. */
989 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_RESET 0x00000000
990 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD register from the beginning of the component. */
991 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_OFST 0x24
992 
993 /*
994  * Register : probe_soc2fpga_main_Probe_StatGo
995  *
996  * Register Layout
997  *
998  * Bits | Access | Reset | Description
999  * :-------|:-------|:--------|:-----------------------------------------------------------------
1000  * [0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_STATGO
1001  * [31:1] | ??? | Unknown | *UNDEFINED*
1002  *
1003  */
1004 /*
1005  * Field : STATGO
1006  *
1007  * Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The
1008  * register is active when statistics collection operates in manual mode, that is,
1009  * when register StatPeriod is set to 0.NOTE The written value is not stored in
1010  * StatGo. A read always returns 0.
1011  *
1012  * Field Access Macros:
1013  *
1014  */
1015 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_STATGO register field. */
1016 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_STATGO_LSB 0
1017 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_STATGO register field. */
1018 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_STATGO_MSB 0
1019 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_STATGO register field. */
1020 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_STATGO_WIDTH 1
1021 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_STATGO register field value. */
1022 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_STATGO_SET_MSK 0x00000001
1023 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_STATGO register field value. */
1024 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_STATGO_CLR_MSK 0xfffffffe
1025 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_STATGO register field. */
1026 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_STATGO_RESET 0x0
1027 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_STATGO field value from a register. */
1028 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_STATGO_GET(value) (((value) & 0x00000001) >> 0)
1029 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_STATGO register field value suitable for setting the register. */
1030 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_STATGO_SET(value) (((value) << 0) & 0x00000001)
1031 
1032 #ifndef __ASSEMBLY__
1033 /*
1034  * WARNING: The C register and register group struct declarations are provided for
1035  * convenience and illustrative purposes. They should, however, be used with
1036  * caution as the C language standard provides no guarantees about the alignment or
1037  * atomicity of device memory accesses. The recommended practice for coding device
1038  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1039  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1040  * alt_write_dword() functions for 64 bit registers.
1041  *
1042  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO.
1043  */
1044 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_s
1045 {
1046  volatile uint32_t STATGO : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_STATGO */
1047  uint32_t : 31; /* *UNDEFINED* */
1048 };
1049 
1050 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO. */
1051 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_t;
1052 #endif /* __ASSEMBLY__ */
1053 
1054 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO register. */
1055 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_RESET 0x00000000
1056 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO register from the beginning of the component. */
1057 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_OFST 0x28
1058 
1059 /*
1060  * Register : probe_soc2fpga_main_Probe_StatAlarmMin
1061  *
1062  * Register Layout
1063  *
1064  * Bits | Access | Reset | Description
1065  * :-------|:-------|:------|:-----------------------------------------------------------------------------
1066  * [31:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_STATALARMMIN
1067  *
1068  */
1069 /*
1070  * Field : STATALARMMIN
1071  *
1072  * Register StatAlarmMin contains the minimum count value used in statistics alarm
1073  * comparisons. The number of bits is equal to twice the value set forparameter
1074  * wStatisticsCounter. When parameter statisticsCounterAlarm is set to False,
1075  * StatAlarmMin is reserved.
1076  *
1077  * Field Access Macros:
1078  *
1079  */
1080 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_STATALARMMIN register field. */
1081 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_STATALARMMIN_LSB 0
1082 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_STATALARMMIN register field. */
1083 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_STATALARMMIN_MSB 31
1084 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_STATALARMMIN register field. */
1085 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_STATALARMMIN_WIDTH 32
1086 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_STATALARMMIN register field value. */
1087 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_STATALARMMIN_SET_MSK 0xffffffff
1088 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_STATALARMMIN register field value. */
1089 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_STATALARMMIN_CLR_MSK 0x00000000
1090 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_STATALARMMIN register field. */
1091 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_STATALARMMIN_RESET 0x0
1092 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_STATALARMMIN field value from a register. */
1093 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_STATALARMMIN_GET(value) (((value) & 0xffffffff) >> 0)
1094 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_STATALARMMIN register field value suitable for setting the register. */
1095 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_STATALARMMIN_SET(value) (((value) << 0) & 0xffffffff)
1096 
1097 #ifndef __ASSEMBLY__
1098 /*
1099  * WARNING: The C register and register group struct declarations are provided for
1100  * convenience and illustrative purposes. They should, however, be used with
1101  * caution as the C language standard provides no guarantees about the alignment or
1102  * atomicity of device memory accesses. The recommended practice for coding device
1103  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1104  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1105  * alt_write_dword() functions for 64 bit registers.
1106  *
1107  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN.
1108  */
1109 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_s
1110 {
1111  volatile uint32_t STATALARMMIN : 32; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_STATALARMMIN */
1112 };
1113 
1114 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN. */
1115 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_t;
1116 #endif /* __ASSEMBLY__ */
1117 
1118 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN register. */
1119 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_RESET 0x00000000
1120 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN register from the beginning of the component. */
1121 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_OFST 0x2c
1122 
1123 /*
1124  * Register : probe_soc2fpga_main_Probe_StatAlarmMax
1125  *
1126  * Register Layout
1127  *
1128  * Bits | Access | Reset | Description
1129  * :-------|:-------|:------|:-----------------------------------------------------------------------------
1130  * [31:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_STATALARMMAX
1131  *
1132  */
1133 /*
1134  * Field : STATALARMMAX
1135  *
1136  * Register StatAlarmMax contains the maximum count value used in statistics alarm
1137  * comparisons.The number of bits is equal to twice the value set for parameter
1138  * wStatisticsCounter. When parameter statisticsCounterAlarm is set to False,
1139  * StatAlarmMax is reserved.
1140  *
1141  * Field Access Macros:
1142  *
1143  */
1144 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_STATALARMMAX register field. */
1145 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_STATALARMMAX_LSB 0
1146 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_STATALARMMAX register field. */
1147 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_STATALARMMAX_MSB 31
1148 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_STATALARMMAX register field. */
1149 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_STATALARMMAX_WIDTH 32
1150 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_STATALARMMAX register field value. */
1151 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_STATALARMMAX_SET_MSK 0xffffffff
1152 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_STATALARMMAX register field value. */
1153 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_STATALARMMAX_CLR_MSK 0x00000000
1154 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_STATALARMMAX register field. */
1155 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_STATALARMMAX_RESET 0x0
1156 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_STATALARMMAX field value from a register. */
1157 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_STATALARMMAX_GET(value) (((value) & 0xffffffff) >> 0)
1158 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_STATALARMMAX register field value suitable for setting the register. */
1159 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_STATALARMMAX_SET(value) (((value) << 0) & 0xffffffff)
1160 
1161 #ifndef __ASSEMBLY__
1162 /*
1163  * WARNING: The C register and register group struct declarations are provided for
1164  * convenience and illustrative purposes. They should, however, be used with
1165  * caution as the C language standard provides no guarantees about the alignment or
1166  * atomicity of device memory accesses. The recommended practice for coding device
1167  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1168  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1169  * alt_write_dword() functions for 64 bit registers.
1170  *
1171  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX.
1172  */
1173 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_s
1174 {
1175  volatile uint32_t STATALARMMAX : 32; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_STATALARMMAX */
1176 };
1177 
1178 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX. */
1179 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_t;
1180 #endif /* __ASSEMBLY__ */
1181 
1182 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX register. */
1183 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_RESET 0x00000000
1184 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX register from the beginning of the component. */
1185 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_OFST 0x30
1186 
1187 /*
1188  * Register : probe_soc2fpga_main_Probe_StatAlarmStatus
1189  *
1190  * Register Layout
1191  *
1192  * Bits | Access | Reset | Description
1193  * :-------|:-------|:--------|:-----------------------------------------------------------------------------------
1194  * [0] | R | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS
1195  * [31:1] | ??? | Unknown | *UNDEFINED*
1196  *
1197  */
1198 /*
1199  * Field : STATALARMSTATUS
1200  *
1201  * Register StatAlarmStatus is a read-only 1-bit register indicating that at least
1202  * one statistics counter has exceeded the programmed values for registers
1203  * StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values
1204  * stored in register MainCtl fields StatAlarmStatus and AlarmEn. When parameter
1205  * statisticsCounterAlarm is set to False, StatAlarmStatus is reserved.
1206  *
1207  * Field Access Macros:
1208  *
1209  */
1210 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS register field. */
1211 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_LSB 0
1212 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS register field. */
1213 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_MSB 0
1214 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS register field. */
1215 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_WIDTH 1
1216 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS register field value. */
1217 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_SET_MSK 0x00000001
1218 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS register field value. */
1219 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_CLR_MSK 0xfffffffe
1220 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS register field. */
1221 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_RESET 0x0
1222 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS field value from a register. */
1223 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_GET(value) (((value) & 0x00000001) >> 0)
1224 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS register field value suitable for setting the register. */
1225 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_SET(value) (((value) << 0) & 0x00000001)
1226 
1227 #ifndef __ASSEMBLY__
1228 /*
1229  * WARNING: The C register and register group struct declarations are provided for
1230  * convenience and illustrative purposes. They should, however, be used with
1231  * caution as the C language standard provides no guarantees about the alignment or
1232  * atomicity of device memory accesses. The recommended practice for coding device
1233  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1234  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1235  * alt_write_dword() functions for 64 bit registers.
1236  *
1237  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS.
1238  */
1239 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_s
1240 {
1241  const volatile uint32_t STATALARMSTATUS : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS */
1242  uint32_t : 31; /* *UNDEFINED* */
1243 };
1244 
1245 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS. */
1246 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_t;
1247 #endif /* __ASSEMBLY__ */
1248 
1249 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS register. */
1250 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_RESET 0x00000000
1251 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS register from the beginning of the component. */
1252 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_OFST 0x34
1253 
1254 /*
1255  * Register : probe_soc2fpga_main_Probe_StatAlarmClr
1256  *
1257  * Register Layout
1258  *
1259  * Bits | Access | Reset | Description
1260  * :-------|:-------|:--------|:-----------------------------------------------------------------------------
1261  * [0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_STATALARMCLR
1262  * [31:1] | ??? | Unknown | *UNDEFINED*
1263  *
1264  */
1265 /*
1266  * Field : STATALARMCLR
1267  *
1268  * Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears
1269  * the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to
1270  * False, StatAlarmClr is reserved.NOTE The written value is not stored in
1271  * StatAlarmClr. A read always returns 0.
1272  *
1273  * Field Access Macros:
1274  *
1275  */
1276 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_STATALARMCLR register field. */
1277 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_STATALARMCLR_LSB 0
1278 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_STATALARMCLR register field. */
1279 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_STATALARMCLR_MSB 0
1280 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_STATALARMCLR register field. */
1281 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_STATALARMCLR_WIDTH 1
1282 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_STATALARMCLR register field value. */
1283 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_STATALARMCLR_SET_MSK 0x00000001
1284 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_STATALARMCLR register field value. */
1285 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_STATALARMCLR_CLR_MSK 0xfffffffe
1286 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_STATALARMCLR register field. */
1287 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_STATALARMCLR_RESET 0x0
1288 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_STATALARMCLR field value from a register. */
1289 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_STATALARMCLR_GET(value) (((value) & 0x00000001) >> 0)
1290 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_STATALARMCLR register field value suitable for setting the register. */
1291 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_STATALARMCLR_SET(value) (((value) << 0) & 0x00000001)
1292 
1293 #ifndef __ASSEMBLY__
1294 /*
1295  * WARNING: The C register and register group struct declarations are provided for
1296  * convenience and illustrative purposes. They should, however, be used with
1297  * caution as the C language standard provides no guarantees about the alignment or
1298  * atomicity of device memory accesses. The recommended practice for coding device
1299  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1300  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1301  * alt_write_dword() functions for 64 bit registers.
1302  *
1303  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR.
1304  */
1305 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_s
1306 {
1307  volatile uint32_t STATALARMCLR : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_STATALARMCLR */
1308  uint32_t : 31; /* *UNDEFINED* */
1309 };
1310 
1311 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR. */
1312 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_t;
1313 #endif /* __ASSEMBLY__ */
1314 
1315 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR register. */
1316 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_RESET 0x00000000
1317 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR register from the beginning of the component. */
1318 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_OFST 0x38
1319 
1320 /*
1321  * Register : probe_soc2fpga_main_Probe_StatAlarmEn
1322  *
1323  * Register Layout
1324  *
1325  * Bits | Access | Reset | Description
1326  * :-------|:-------|:--------|:---------------------------------------------------------------------------
1327  * [0] | RW | 0x1 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_STATALARMEN
1328  * [31:1] | ??? | Unknown | *UNDEFINED*
1329  *
1330  */
1331 /*
1332  * Field : STATALARMEN
1333  *
1334  * Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and
1335  * CtiTrigOut(1) signal interrupts.
1336  *
1337  * Field Access Macros:
1338  *
1339  */
1340 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_STATALARMEN register field. */
1341 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_STATALARMEN_LSB 0
1342 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_STATALARMEN register field. */
1343 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_STATALARMEN_MSB 0
1344 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_STATALARMEN register field. */
1345 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_STATALARMEN_WIDTH 1
1346 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_STATALARMEN register field value. */
1347 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_STATALARMEN_SET_MSK 0x00000001
1348 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_STATALARMEN register field value. */
1349 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_STATALARMEN_CLR_MSK 0xfffffffe
1350 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_STATALARMEN register field. */
1351 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_STATALARMEN_RESET 0x1
1352 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_STATALARMEN field value from a register. */
1353 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_STATALARMEN_GET(value) (((value) & 0x00000001) >> 0)
1354 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_STATALARMEN register field value suitable for setting the register. */
1355 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_STATALARMEN_SET(value) (((value) << 0) & 0x00000001)
1356 
1357 #ifndef __ASSEMBLY__
1358 /*
1359  * WARNING: The C register and register group struct declarations are provided for
1360  * convenience and illustrative purposes. They should, however, be used with
1361  * caution as the C language standard provides no guarantees about the alignment or
1362  * atomicity of device memory accesses. The recommended practice for coding device
1363  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1364  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1365  * alt_write_dword() functions for 64 bit registers.
1366  *
1367  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN.
1368  */
1369 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_s
1370 {
1371  volatile uint32_t STATALARMEN : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_STATALARMEN */
1372  uint32_t : 31; /* *UNDEFINED* */
1373 };
1374 
1375 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN. */
1376 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_t;
1377 #endif /* __ASSEMBLY__ */
1378 
1379 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN register. */
1380 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_RESET 0x00000001
1381 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN register from the beginning of the component. */
1382 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_OFST 0x3c
1383 
1384 /*
1385  * Register : probe_soc2fpga_main_Probe_Filters_0_RouteIdBase
1386  *
1387  * Register Layout
1388  *
1389  * Bits | Access | Reset | Description
1390  * :--------|:-------|:--------|:-----------------------------------------------------------------------------------------------
1391  * [22:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE
1392  * [31:23] | ??? | Unknown | *UNDEFINED*
1393  *
1394  */
1395 /*
1396  * Field : FILTERS_0_ROUTEIDBASE
1397  *
1398  * Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to
1399  * filter packets.
1400  *
1401  * Field Access Macros:
1402  *
1403  */
1404 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE register field. */
1405 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_LSB 0
1406 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE register field. */
1407 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_MSB 22
1408 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE register field. */
1409 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_WIDTH 23
1410 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE register field value. */
1411 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_SET_MSK 0x007fffff
1412 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE register field value. */
1413 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_CLR_MSK 0xff800000
1414 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE register field. */
1415 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_RESET 0x0
1416 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE field value from a register. */
1417 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_GET(value) (((value) & 0x007fffff) >> 0)
1418 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE register field value suitable for setting the register. */
1419 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_SET(value) (((value) << 0) & 0x007fffff)
1420 
1421 #ifndef __ASSEMBLY__
1422 /*
1423  * WARNING: The C register and register group struct declarations are provided for
1424  * convenience and illustrative purposes. They should, however, be used with
1425  * caution as the C language standard provides no guarantees about the alignment or
1426  * atomicity of device memory accesses. The recommended practice for coding device
1427  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1428  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1429  * alt_write_dword() functions for 64 bit registers.
1430  *
1431  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE.
1432  */
1433 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_s
1434 {
1435  volatile uint32_t FILTERS_0_ROUTEIDBASE : 23; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE */
1436  uint32_t : 9; /* *UNDEFINED* */
1437 };
1438 
1439 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE. */
1440 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_t;
1441 #endif /* __ASSEMBLY__ */
1442 
1443 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE register. */
1444 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_RESET 0x00000000
1445 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE register from the beginning of the component. */
1446 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_OFST 0x44
1447 
1448 /*
1449  * Register : probe_soc2fpga_main_Probe_Filters_0_RouteIdMask
1450  *
1451  * Register Layout
1452  *
1453  * Bits | Access | Reset | Description
1454  * :--------|:-------|:--------|:-----------------------------------------------------------------------------------------------
1455  * [22:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK
1456  * [31:23] | ??? | Unknown | *UNDEFINED*
1457  *
1458  */
1459 /*
1460  * Field : FILTERS_0_ROUTEIDMASK
1461  *
1462  * Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter
1463  * packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &
1464  * RouteIdMask = RouteIdBase & RouteIdMask.
1465  *
1466  * Field Access Macros:
1467  *
1468  */
1469 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK register field. */
1470 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_LSB 0
1471 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK register field. */
1472 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_MSB 22
1473 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK register field. */
1474 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_WIDTH 23
1475 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK register field value. */
1476 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_SET_MSK 0x007fffff
1477 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK register field value. */
1478 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_CLR_MSK 0xff800000
1479 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK register field. */
1480 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_RESET 0x0
1481 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK field value from a register. */
1482 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_GET(value) (((value) & 0x007fffff) >> 0)
1483 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK register field value suitable for setting the register. */
1484 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_SET(value) (((value) << 0) & 0x007fffff)
1485 
1486 #ifndef __ASSEMBLY__
1487 /*
1488  * WARNING: The C register and register group struct declarations are provided for
1489  * convenience and illustrative purposes. They should, however, be used with
1490  * caution as the C language standard provides no guarantees about the alignment or
1491  * atomicity of device memory accesses. The recommended practice for coding device
1492  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1493  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1494  * alt_write_dword() functions for 64 bit registers.
1495  *
1496  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK.
1497  */
1498 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_s
1499 {
1500  volatile uint32_t FILTERS_0_ROUTEIDMASK : 23; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK */
1501  uint32_t : 9; /* *UNDEFINED* */
1502 };
1503 
1504 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK. */
1505 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_t;
1506 #endif /* __ASSEMBLY__ */
1507 
1508 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK register. */
1509 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_RESET 0x00000000
1510 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK register from the beginning of the component. */
1511 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_OFST 0x48
1512 
1513 /*
1514  * Register : probe_soc2fpga_main_Probe_Filters_0_AddrBase_Low
1515  *
1516  * Register Layout
1517  *
1518  * Bits | Access | Reset | Description
1519  * :-------|:-------|:------|:-------------------------------------------------------------------------------------------------
1520  * [31:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW
1521  *
1522  */
1523 /*
1524  * Field : FILTERS_0_ADDRBASE_LOW
1525  *
1526  * Address LSB register.
1527  *
1528  * Field Access Macros:
1529  *
1530  */
1531 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW register field. */
1532 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_LSB 0
1533 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW register field. */
1534 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_MSB 31
1535 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW register field. */
1536 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_WIDTH 32
1537 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW register field value. */
1538 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_SET_MSK 0xffffffff
1539 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW register field value. */
1540 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_CLR_MSK 0x00000000
1541 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW register field. */
1542 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_RESET 0x0
1543 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW field value from a register. */
1544 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
1545 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW register field value suitable for setting the register. */
1546 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
1547 
1548 #ifndef __ASSEMBLY__
1549 /*
1550  * WARNING: The C register and register group struct declarations are provided for
1551  * convenience and illustrative purposes. They should, however, be used with
1552  * caution as the C language standard provides no guarantees about the alignment or
1553  * atomicity of device memory accesses. The recommended practice for coding device
1554  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1555  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1556  * alt_write_dword() functions for 64 bit registers.
1557  *
1558  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW.
1559  */
1560 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_s
1561 {
1562  volatile uint32_t FILTERS_0_ADDRBASE_LOW : 32; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW */
1563 };
1564 
1565 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW. */
1566 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_t;
1567 #endif /* __ASSEMBLY__ */
1568 
1569 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW register. */
1570 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_RESET 0x00000000
1571 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW register from the beginning of the component. */
1572 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_OFST 0x4c
1573 
1574 /*
1575  * Register : probe_soc2fpga_main_Probe_Filters_0_AddrBase_High
1576  *
1577  * Register Layout
1578  *
1579  * Bits | Access | Reset | Description
1580  * :-------|:-------|:--------|:---------------------------------------------------------------------------------------------------
1581  * [7:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH
1582  * [31:8] | ??? | Unknown | *UNDEFINED*
1583  *
1584  */
1585 /*
1586  * Field : FILTERS_0_ADDRBASE_HIGH
1587  *
1588  * Address MSB register.
1589  *
1590  * Field Access Macros:
1591  *
1592  */
1593 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH register field. */
1594 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_LSB 0
1595 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH register field. */
1596 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_MSB 7
1597 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH register field. */
1598 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_WIDTH 8
1599 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH register field value. */
1600 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_SET_MSK 0x000000ff
1601 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH register field value. */
1602 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_CLR_MSK 0xffffff00
1603 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH register field. */
1604 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_RESET 0x0
1605 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH field value from a register. */
1606 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_GET(value) (((value) & 0x000000ff) >> 0)
1607 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH register field value suitable for setting the register. */
1608 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_SET(value) (((value) << 0) & 0x000000ff)
1609 
1610 #ifndef __ASSEMBLY__
1611 /*
1612  * WARNING: The C register and register group struct declarations are provided for
1613  * convenience and illustrative purposes. They should, however, be used with
1614  * caution as the C language standard provides no guarantees about the alignment or
1615  * atomicity of device memory accesses. The recommended practice for coding device
1616  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1617  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1618  * alt_write_dword() functions for 64 bit registers.
1619  *
1620  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH.
1621  */
1622 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_s
1623 {
1624  volatile uint32_t FILTERS_0_ADDRBASE_HIGH : 8; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH */
1625  uint32_t : 24; /* *UNDEFINED* */
1626 };
1627 
1628 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH. */
1629 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_t;
1630 #endif /* __ASSEMBLY__ */
1631 
1632 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH register. */
1633 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_RESET 0x00000000
1634 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH register from the beginning of the component. */
1635 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_OFST 0x50
1636 
1637 /*
1638  * Register : probe_soc2fpga_main_Probe_Filters_0_WindowSize
1639  *
1640  * Register Layout
1641  *
1642  * Bits | Access | Reset | Description
1643  * :-------|:-------|:--------|:---------------------------------------------------------------------------------------------
1644  * [5:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE
1645  * [31:6] | ??? | Unknown | *UNDEFINED*
1646  *
1647  */
1648 /*
1649  * Field : FILTERS_0_WINDOWSIZE
1650  *
1651  * Register WindowSize contains the encoded address mask used to filter packets.
1652  * The effective Mask value is equal to ~(2max(WindowSize, packet.Len) - 1). A
1653  * packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows
1654  * filteringof packets having an intersection with the AddrBase/WindowSize burst
1655  * aligned region, even if the region is smaller than the packet.
1656  *
1657  * Field Access Macros:
1658  *
1659  */
1660 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE register field. */
1661 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_LSB 0
1662 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE register field. */
1663 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_MSB 5
1664 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE register field. */
1665 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_WIDTH 6
1666 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE register field value. */
1667 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_SET_MSK 0x0000003f
1668 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE register field value. */
1669 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_CLR_MSK 0xffffffc0
1670 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE register field. */
1671 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_RESET 0x0
1672 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE field value from a register. */
1673 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
1674 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE register field value suitable for setting the register. */
1675 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
1676 
1677 #ifndef __ASSEMBLY__
1678 /*
1679  * WARNING: The C register and register group struct declarations are provided for
1680  * convenience and illustrative purposes. They should, however, be used with
1681  * caution as the C language standard provides no guarantees about the alignment or
1682  * atomicity of device memory accesses. The recommended practice for coding device
1683  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1684  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1685  * alt_write_dword() functions for 64 bit registers.
1686  *
1687  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE.
1688  */
1689 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_s
1690 {
1691  volatile uint32_t FILTERS_0_WINDOWSIZE : 6; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE */
1692  uint32_t : 26; /* *UNDEFINED* */
1693 };
1694 
1695 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE. */
1696 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_t;
1697 #endif /* __ASSEMBLY__ */
1698 
1699 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE register. */
1700 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_RESET 0x00000000
1701 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE register from the beginning of the component. */
1702 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_OFST 0x54
1703 
1704 /*
1705  * Register : probe_soc2fpga_main_Probe_Filters_0_SecurityBase
1706  *
1707  * Register Layout
1708  *
1709  * Bits | Access | Reset | Description
1710  * :-------|:-------|:--------|:-------------------------------------------------------------------------------------------------
1711  * [1:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE
1712  * [31:2] | ??? | Unknown | *UNDEFINED*
1713  *
1714  */
1715 /*
1716  * Field : FILTERS_0_SECURITYBASE
1717  *
1718  * Register SecurityBase contains the security base used to filter packets.
1719  *
1720  * Field Access Macros:
1721  *
1722  */
1723 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE register field. */
1724 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_LSB 0
1725 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE register field. */
1726 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_MSB 1
1727 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE register field. */
1728 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_WIDTH 2
1729 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE register field value. */
1730 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_SET_MSK 0x00000003
1731 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE register field value. */
1732 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_CLR_MSK 0xfffffffc
1733 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE register field. */
1734 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_RESET 0x0
1735 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE field value from a register. */
1736 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_GET(value) (((value) & 0x00000003) >> 0)
1737 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE register field value suitable for setting the register. */
1738 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_SET(value) (((value) << 0) & 0x00000003)
1739 
1740 #ifndef __ASSEMBLY__
1741 /*
1742  * WARNING: The C register and register group struct declarations are provided for
1743  * convenience and illustrative purposes. They should, however, be used with
1744  * caution as the C language standard provides no guarantees about the alignment or
1745  * atomicity of device memory accesses. The recommended practice for coding device
1746  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1747  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1748  * alt_write_dword() functions for 64 bit registers.
1749  *
1750  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE.
1751  */
1752 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_s
1753 {
1754  volatile uint32_t FILTERS_0_SECURITYBASE : 2; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE */
1755  uint32_t : 30; /* *UNDEFINED* */
1756 };
1757 
1758 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE. */
1759 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_t;
1760 #endif /* __ASSEMBLY__ */
1761 
1762 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE register. */
1763 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_RESET 0x00000000
1764 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE register from the beginning of the component. */
1765 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_OFST 0x58
1766 
1767 /*
1768  * Register : probe_soc2fpga_main_Probe_Filters_0_SecurityMask
1769  *
1770  * Register Layout
1771  *
1772  * Bits | Access | Reset | Description
1773  * :-------|:-------|:--------|:-------------------------------------------------------------------------------------------------
1774  * [1:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK
1775  * [31:2] | ??? | Unknown | *UNDEFINED*
1776  *
1777  */
1778 /*
1779  * Field : FILTERS_0_SECURITYMASK
1780  *
1781  * Register SecurityMask is contains the security mask used to filter packets. A
1782  * packet is a candidate when: packet.Security & SecurityMask = SecurityBase &
1783  * SecurityMasks.
1784  *
1785  * Field Access Macros:
1786  *
1787  */
1788 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK register field. */
1789 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_LSB 0
1790 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK register field. */
1791 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_MSB 1
1792 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK register field. */
1793 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_WIDTH 2
1794 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK register field value. */
1795 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_SET_MSK 0x00000003
1796 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK register field value. */
1797 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_CLR_MSK 0xfffffffc
1798 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK register field. */
1799 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_RESET 0x0
1800 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK field value from a register. */
1801 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_GET(value) (((value) & 0x00000003) >> 0)
1802 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK register field value suitable for setting the register. */
1803 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_SET(value) (((value) << 0) & 0x00000003)
1804 
1805 #ifndef __ASSEMBLY__
1806 /*
1807  * WARNING: The C register and register group struct declarations are provided for
1808  * convenience and illustrative purposes. They should, however, be used with
1809  * caution as the C language standard provides no guarantees about the alignment or
1810  * atomicity of device memory accesses. The recommended practice for coding device
1811  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1812  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1813  * alt_write_dword() functions for 64 bit registers.
1814  *
1815  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK.
1816  */
1817 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_s
1818 {
1819  volatile uint32_t FILTERS_0_SECURITYMASK : 2; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK */
1820  uint32_t : 30; /* *UNDEFINED* */
1821 };
1822 
1823 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK. */
1824 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_t;
1825 #endif /* __ASSEMBLY__ */
1826 
1827 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK register. */
1828 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_RESET 0x00000000
1829 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK register from the beginning of the component. */
1830 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_OFST 0x5c
1831 
1832 /*
1833  * Register : probe_soc2fpga_main_Probe_Filters_0_Opcode
1834  *
1835  * Packet Probe register Opcode is a 4-bit register that selects candidate packets
1836  * based on packet opcodes (0 disables the filter):
1837  *
1838  * Register Layout
1839  *
1840  * Bits | Access | Reset | Description
1841  * :-------|:-------|:--------|:---------------------------------------------------------------------------
1842  * [0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_RDEN
1843  * [1] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_WREN
1844  * [2] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN
1845  * [3] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_URGEN
1846  * [31:4] | ??? | Unknown | *UNDEFINED*
1847  *
1848  */
1849 /*
1850  * Field : RDEN
1851  *
1852  * Selects RD packets.
1853  *
1854  * Field Access Macros:
1855  *
1856  */
1857 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_RDEN register field. */
1858 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_LSB 0
1859 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_RDEN register field. */
1860 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_MSB 0
1861 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_RDEN register field. */
1862 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_WIDTH 1
1863 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_RDEN register field value. */
1864 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_SET_MSK 0x00000001
1865 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_RDEN register field value. */
1866 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_CLR_MSK 0xfffffffe
1867 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_RDEN register field. */
1868 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_RESET 0x0
1869 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_RDEN field value from a register. */
1870 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
1871 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_RDEN register field value suitable for setting the register. */
1872 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
1873 
1874 /*
1875  * Field : WREN
1876  *
1877  * Selects WR packets.
1878  *
1879  * Field Access Macros:
1880  *
1881  */
1882 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_WREN register field. */
1883 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_WREN_LSB 1
1884 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_WREN register field. */
1885 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_WREN_MSB 1
1886 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_WREN register field. */
1887 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_WREN_WIDTH 1
1888 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_WREN register field value. */
1889 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_WREN_SET_MSK 0x00000002
1890 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_WREN register field value. */
1891 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_WREN_CLR_MSK 0xfffffffd
1892 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_WREN register field. */
1893 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_WREN_RESET 0x0
1894 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_WREN field value from a register. */
1895 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
1896 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_WREN register field value suitable for setting the register. */
1897 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
1898 
1899 /*
1900  * Field : LOCKEN
1901  *
1902  * Selects RDX-WR, RDL, WRC and Linked sequence.
1903  *
1904  * Field Access Macros:
1905  *
1906  */
1907 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN register field. */
1908 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_LSB 2
1909 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN register field. */
1910 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_MSB 2
1911 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN register field. */
1912 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_WIDTH 1
1913 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN register field value. */
1914 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_SET_MSK 0x00000004
1915 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN register field value. */
1916 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
1917 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN register field. */
1918 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_RESET 0x0
1919 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN field value from a register. */
1920 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
1921 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN register field value suitable for setting the register. */
1922 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
1923 
1924 /*
1925  * Field : URGEN
1926  *
1927  * Selects URG packets (urgency).
1928  *
1929  * Field Access Macros:
1930  *
1931  */
1932 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_URGEN register field. */
1933 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_LSB 3
1934 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_URGEN register field. */
1935 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_MSB 3
1936 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_URGEN register field. */
1937 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_WIDTH 1
1938 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_URGEN register field value. */
1939 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_SET_MSK 0x00000008
1940 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_URGEN register field value. */
1941 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_CLR_MSK 0xfffffff7
1942 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_URGEN register field. */
1943 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_RESET 0x0
1944 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_URGEN field value from a register. */
1945 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
1946 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_URGEN register field value suitable for setting the register. */
1947 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
1948 
1949 #ifndef __ASSEMBLY__
1950 /*
1951  * WARNING: The C register and register group struct declarations are provided for
1952  * convenience and illustrative purposes. They should, however, be used with
1953  * caution as the C language standard provides no guarantees about the alignment or
1954  * atomicity of device memory accesses. The recommended practice for coding device
1955  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1956  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1957  * alt_write_dword() functions for 64 bit registers.
1958  *
1959  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE.
1960  */
1961 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_s
1962 {
1963  volatile uint32_t RDEN : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_RDEN */
1964  volatile uint32_t WREN : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_WREN */
1965  volatile uint32_t LOCKEN : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN */
1966  volatile uint32_t URGEN : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_URGEN */
1967  uint32_t : 28; /* *UNDEFINED* */
1968 };
1969 
1970 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE. */
1971 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_t;
1972 #endif /* __ASSEMBLY__ */
1973 
1974 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE register. */
1975 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_RESET 0x00000000
1976 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE register from the beginning of the component. */
1977 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_OFST 0x60
1978 
1979 /*
1980  * Register : probe_soc2fpga_main_Probe_Filters_0_Status
1981  *
1982  * Register Status is 2-bit register that selects candidate packets based on packet
1983  * status.
1984  *
1985  * Register Layout
1986  *
1987  * Bits | Access | Reset | Description
1988  * :-------|:-------|:--------|:--------------------------------------------------------------------------
1989  * [0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_REQEN
1990  * [1] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_RSPEN
1991  * [31:2] | ??? | Unknown | *UNDEFINED*
1992  *
1993  */
1994 /*
1995  * Field : REQEN
1996  *
1997  * Selects REQ status packets.
1998  *
1999  * Field Access Macros:
2000  *
2001  */
2002 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_REQEN register field. */
2003 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_REQEN_LSB 0
2004 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_REQEN register field. */
2005 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_REQEN_MSB 0
2006 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_REQEN register field. */
2007 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_REQEN_WIDTH 1
2008 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_REQEN register field value. */
2009 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_REQEN_SET_MSK 0x00000001
2010 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_REQEN register field value. */
2011 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_REQEN_CLR_MSK 0xfffffffe
2012 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_REQEN register field. */
2013 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_REQEN_RESET 0x0
2014 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_REQEN field value from a register. */
2015 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_REQEN_GET(value) (((value) & 0x00000001) >> 0)
2016 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_REQEN register field value suitable for setting the register. */
2017 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_REQEN_SET(value) (((value) << 0) & 0x00000001)
2018 
2019 /*
2020  * Field : RSPEN
2021  *
2022  * Selects RSP and FAIL-CONT status packets.
2023  *
2024  * Field Access Macros:
2025  *
2026  */
2027 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_RSPEN register field. */
2028 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_LSB 1
2029 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_RSPEN register field. */
2030 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_MSB 1
2031 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_RSPEN register field. */
2032 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_WIDTH 1
2033 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_RSPEN register field value. */
2034 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_SET_MSK 0x00000002
2035 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_RSPEN register field value. */
2036 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_CLR_MSK 0xfffffffd
2037 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_RSPEN register field. */
2038 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_RESET 0x0
2039 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_RSPEN field value from a register. */
2040 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
2041 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_RSPEN register field value suitable for setting the register. */
2042 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_SET(value) (((value) << 1) & 0x00000002)
2043 
2044 #ifndef __ASSEMBLY__
2045 /*
2046  * WARNING: The C register and register group struct declarations are provided for
2047  * convenience and illustrative purposes. They should, however, be used with
2048  * caution as the C language standard provides no guarantees about the alignment or
2049  * atomicity of device memory accesses. The recommended practice for coding device
2050  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2051  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2052  * alt_write_dword() functions for 64 bit registers.
2053  *
2054  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS.
2055  */
2056 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_s
2057 {
2058  volatile uint32_t REQEN : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_REQEN */
2059  volatile uint32_t RSPEN : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_RSPEN */
2060  uint32_t : 30; /* *UNDEFINED* */
2061 };
2062 
2063 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS. */
2064 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_t;
2065 #endif /* __ASSEMBLY__ */
2066 
2067 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS register. */
2068 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_RESET 0x00000000
2069 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS register from the beginning of the component. */
2070 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_OFST 0x64
2071 
2072 /*
2073  * Register : probe_soc2fpga_main_Probe_Filters_0_Length
2074  *
2075  * Register Layout
2076  *
2077  * Bits | Access | Reset | Description
2078  * :-------|:-------|:--------|:-------------------------------------------------------------------------------------
2079  * [3:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH
2080  * [31:4] | ??? | Unknown | *UNDEFINED*
2081  *
2082  */
2083 /*
2084  * Field : FILTERS_0_LENGTH
2085  *
2086  * Register Length is 4-bit register that selects candidate packets if their number
2087  * of bytes is less than or equal to 2**Length.
2088  *
2089  * Field Access Macros:
2090  *
2091  */
2092 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH register field. */
2093 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_LSB 0
2094 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH register field. */
2095 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_MSB 3
2096 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH register field. */
2097 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_WIDTH 4
2098 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH register field value. */
2099 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_SET_MSK 0x0000000f
2100 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH register field value. */
2101 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_CLR_MSK 0xfffffff0
2102 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH register field. */
2103 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_RESET 0x0
2104 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH field value from a register. */
2105 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_GET(value) (((value) & 0x0000000f) >> 0)
2106 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH register field value suitable for setting the register. */
2107 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_SET(value) (((value) << 0) & 0x0000000f)
2108 
2109 #ifndef __ASSEMBLY__
2110 /*
2111  * WARNING: The C register and register group struct declarations are provided for
2112  * convenience and illustrative purposes. They should, however, be used with
2113  * caution as the C language standard provides no guarantees about the alignment or
2114  * atomicity of device memory accesses. The recommended practice for coding device
2115  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2116  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2117  * alt_write_dword() functions for 64 bit registers.
2118  *
2119  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH.
2120  */
2121 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_s
2122 {
2123  volatile uint32_t FILTERS_0_LENGTH : 4; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH */
2124  uint32_t : 28; /* *UNDEFINED* */
2125 };
2126 
2127 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH. */
2128 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_t;
2129 #endif /* __ASSEMBLY__ */
2130 
2131 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH register. */
2132 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_RESET 0x00000000
2133 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH register from the beginning of the component. */
2134 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_OFST 0x68
2135 
2136 /*
2137  * Register : probe_soc2fpga_main_Probe_Filters_0_Urgency
2138  *
2139  * Register Layout
2140  *
2141  * Bits | Access | Reset | Description
2142  * :-------|:-------|:--------|:---------------------------------------------------------------------------------------
2143  * [1:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY
2144  * [31:2] | ??? | Unknown | *UNDEFINED*
2145  *
2146  */
2147 /*
2148  * Field : FILTERS_0_URGENCY
2149  *
2150  * Register Urgency contains the minimum urgency level used to filter packets. A
2151  * packet is a candidate when its socket urgency is greater than or equal to the
2152  * urgency specified in the register.
2153  *
2154  * Field Access Macros:
2155  *
2156  */
2157 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY register field. */
2158 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_LSB 0
2159 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY register field. */
2160 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_MSB 1
2161 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY register field. */
2162 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_WIDTH 2
2163 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY register field value. */
2164 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_SET_MSK 0x00000003
2165 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY register field value. */
2166 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_CLR_MSK 0xfffffffc
2167 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY register field. */
2168 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_RESET 0x0
2169 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY field value from a register. */
2170 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
2171 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY register field value suitable for setting the register. */
2172 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_SET(value) (((value) << 0) & 0x00000003)
2173 
2174 #ifndef __ASSEMBLY__
2175 /*
2176  * WARNING: The C register and register group struct declarations are provided for
2177  * convenience and illustrative purposes. They should, however, be used with
2178  * caution as the C language standard provides no guarantees about the alignment or
2179  * atomicity of device memory accesses. The recommended practice for coding device
2180  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2181  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2182  * alt_write_dword() functions for 64 bit registers.
2183  *
2184  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY.
2185  */
2186 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_s
2187 {
2188  volatile uint32_t FILTERS_0_URGENCY : 2; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY */
2189  uint32_t : 30; /* *UNDEFINED* */
2190 };
2191 
2192 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY. */
2193 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_t;
2194 #endif /* __ASSEMBLY__ */
2195 
2196 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY register. */
2197 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_RESET 0x00000000
2198 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY register from the beginning of the component. */
2199 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_OFST 0x6c
2200 
2201 /*
2202  * Register : probe_soc2fpga_main_Probe_Filters_1_RouteIdBase
2203  *
2204  * Register Layout
2205  *
2206  * Bits | Access | Reset | Description
2207  * :--------|:-------|:--------|:-----------------------------------------------------------------------------------------------
2208  * [22:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE
2209  * [31:23] | ??? | Unknown | *UNDEFINED*
2210  *
2211  */
2212 /*
2213  * Field : FILTERS_1_ROUTEIDBASE
2214  *
2215  * Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to
2216  * filter packets.
2217  *
2218  * Field Access Macros:
2219  *
2220  */
2221 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE register field. */
2222 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_LSB 0
2223 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE register field. */
2224 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_MSB 22
2225 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE register field. */
2226 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_WIDTH 23
2227 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE register field value. */
2228 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_SET_MSK 0x007fffff
2229 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE register field value. */
2230 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_CLR_MSK 0xff800000
2231 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE register field. */
2232 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_RESET 0x0
2233 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE field value from a register. */
2234 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_GET(value) (((value) & 0x007fffff) >> 0)
2235 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE register field value suitable for setting the register. */
2236 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_SET(value) (((value) << 0) & 0x007fffff)
2237 
2238 #ifndef __ASSEMBLY__
2239 /*
2240  * WARNING: The C register and register group struct declarations are provided for
2241  * convenience and illustrative purposes. They should, however, be used with
2242  * caution as the C language standard provides no guarantees about the alignment or
2243  * atomicity of device memory accesses. The recommended practice for coding device
2244  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2245  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2246  * alt_write_dword() functions for 64 bit registers.
2247  *
2248  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE.
2249  */
2250 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_s
2251 {
2252  volatile uint32_t FILTERS_1_ROUTEIDBASE : 23; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE */
2253  uint32_t : 9; /* *UNDEFINED* */
2254 };
2255 
2256 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE. */
2257 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_t;
2258 #endif /* __ASSEMBLY__ */
2259 
2260 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE register. */
2261 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_RESET 0x00000000
2262 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE register from the beginning of the component. */
2263 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_OFST 0x80
2264 
2265 /*
2266  * Register : probe_soc2fpga_main_Probe_Filters_1_RouteIdMask
2267  *
2268  * Register Layout
2269  *
2270  * Bits | Access | Reset | Description
2271  * :--------|:-------|:--------|:-----------------------------------------------------------------------------------------------
2272  * [22:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK
2273  * [31:23] | ??? | Unknown | *UNDEFINED*
2274  *
2275  */
2276 /*
2277  * Field : FILTERS_1_ROUTEIDMASK
2278  *
2279  * Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter
2280  * packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &
2281  * RouteIdMask = RouteIdBase & RouteIdMask.
2282  *
2283  * Field Access Macros:
2284  *
2285  */
2286 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK register field. */
2287 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_LSB 0
2288 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK register field. */
2289 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_MSB 22
2290 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK register field. */
2291 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_WIDTH 23
2292 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK register field value. */
2293 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_SET_MSK 0x007fffff
2294 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK register field value. */
2295 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_CLR_MSK 0xff800000
2296 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK register field. */
2297 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_RESET 0x0
2298 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK field value from a register. */
2299 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_GET(value) (((value) & 0x007fffff) >> 0)
2300 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK register field value suitable for setting the register. */
2301 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_SET(value) (((value) << 0) & 0x007fffff)
2302 
2303 #ifndef __ASSEMBLY__
2304 /*
2305  * WARNING: The C register and register group struct declarations are provided for
2306  * convenience and illustrative purposes. They should, however, be used with
2307  * caution as the C language standard provides no guarantees about the alignment or
2308  * atomicity of device memory accesses. The recommended practice for coding device
2309  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2310  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2311  * alt_write_dword() functions for 64 bit registers.
2312  *
2313  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK.
2314  */
2315 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_s
2316 {
2317  volatile uint32_t FILTERS_1_ROUTEIDMASK : 23; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK */
2318  uint32_t : 9; /* *UNDEFINED* */
2319 };
2320 
2321 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK. */
2322 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_t;
2323 #endif /* __ASSEMBLY__ */
2324 
2325 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK register. */
2326 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_RESET 0x00000000
2327 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK register from the beginning of the component. */
2328 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_OFST 0x84
2329 
2330 /*
2331  * Register : probe_soc2fpga_main_Probe_Filters_1_AddrBase_Low
2332  *
2333  * Register Layout
2334  *
2335  * Bits | Access | Reset | Description
2336  * :-------|:-------|:------|:-------------------------------------------------------------------------------------------------
2337  * [31:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW
2338  *
2339  */
2340 /*
2341  * Field : FILTERS_1_ADDRBASE_LOW
2342  *
2343  * Address LSB register.
2344  *
2345  * Field Access Macros:
2346  *
2347  */
2348 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW register field. */
2349 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_LSB 0
2350 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW register field. */
2351 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_MSB 31
2352 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW register field. */
2353 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_WIDTH 32
2354 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW register field value. */
2355 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_SET_MSK 0xffffffff
2356 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW register field value. */
2357 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_CLR_MSK 0x00000000
2358 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW register field. */
2359 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_RESET 0x0
2360 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW field value from a register. */
2361 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
2362 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW register field value suitable for setting the register. */
2363 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
2364 
2365 #ifndef __ASSEMBLY__
2366 /*
2367  * WARNING: The C register and register group struct declarations are provided for
2368  * convenience and illustrative purposes. They should, however, be used with
2369  * caution as the C language standard provides no guarantees about the alignment or
2370  * atomicity of device memory accesses. The recommended practice for coding device
2371  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2372  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2373  * alt_write_dword() functions for 64 bit registers.
2374  *
2375  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW.
2376  */
2377 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_s
2378 {
2379  volatile uint32_t FILTERS_1_ADDRBASE_LOW : 32; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW */
2380 };
2381 
2382 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW. */
2383 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_t;
2384 #endif /* __ASSEMBLY__ */
2385 
2386 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW register. */
2387 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_RESET 0x00000000
2388 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW register from the beginning of the component. */
2389 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_OFST 0x88
2390 
2391 /*
2392  * Register : probe_soc2fpga_main_Probe_Filters_1_AddrBase_High
2393  *
2394  * Register Layout
2395  *
2396  * Bits | Access | Reset | Description
2397  * :-------|:-------|:--------|:---------------------------------------------------------------------------------------------------
2398  * [7:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH
2399  * [31:8] | ??? | Unknown | *UNDEFINED*
2400  *
2401  */
2402 /*
2403  * Field : FILTERS_1_ADDRBASE_HIGH
2404  *
2405  * Address MSB register.
2406  *
2407  * Field Access Macros:
2408  *
2409  */
2410 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH register field. */
2411 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_LSB 0
2412 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH register field. */
2413 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_MSB 7
2414 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH register field. */
2415 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_WIDTH 8
2416 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH register field value. */
2417 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_SET_MSK 0x000000ff
2418 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH register field value. */
2419 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_CLR_MSK 0xffffff00
2420 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH register field. */
2421 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_RESET 0x0
2422 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH field value from a register. */
2423 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_GET(value) (((value) & 0x000000ff) >> 0)
2424 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH register field value suitable for setting the register. */
2425 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_SET(value) (((value) << 0) & 0x000000ff)
2426 
2427 #ifndef __ASSEMBLY__
2428 /*
2429  * WARNING: The C register and register group struct declarations are provided for
2430  * convenience and illustrative purposes. They should, however, be used with
2431  * caution as the C language standard provides no guarantees about the alignment or
2432  * atomicity of device memory accesses. The recommended practice for coding device
2433  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2434  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2435  * alt_write_dword() functions for 64 bit registers.
2436  *
2437  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH.
2438  */
2439 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_s
2440 {
2441  volatile uint32_t FILTERS_1_ADDRBASE_HIGH : 8; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH */
2442  uint32_t : 24; /* *UNDEFINED* */
2443 };
2444 
2445 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH. */
2446 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_t;
2447 #endif /* __ASSEMBLY__ */
2448 
2449 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH register. */
2450 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_RESET 0x00000000
2451 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH register from the beginning of the component. */
2452 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_OFST 0x8c
2453 
2454 /*
2455  * Register : probe_soc2fpga_main_Probe_Filters_1_WindowSize
2456  *
2457  * Register Layout
2458  *
2459  * Bits | Access | Reset | Description
2460  * :-------|:-------|:--------|:---------------------------------------------------------------------------------------------
2461  * [5:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE
2462  * [31:6] | ??? | Unknown | *UNDEFINED*
2463  *
2464  */
2465 /*
2466  * Field : FILTERS_1_WINDOWSIZE
2467  *
2468  * Register WindowSize contains the encoded address mask used to filter packets.
2469  * The effective Mask value is equal to ~(2max(WindowSize, packet.Len) - 1). A
2470  * packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows
2471  * filteringof packets having an intersection with the AddrBase/WindowSize burst
2472  * aligned region, even if the region is smaller than the packet.
2473  *
2474  * Field Access Macros:
2475  *
2476  */
2477 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE register field. */
2478 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_LSB 0
2479 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE register field. */
2480 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_MSB 5
2481 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE register field. */
2482 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_WIDTH 6
2483 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE register field value. */
2484 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_SET_MSK 0x0000003f
2485 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE register field value. */
2486 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_CLR_MSK 0xffffffc0
2487 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE register field. */
2488 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_RESET 0x0
2489 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE field value from a register. */
2490 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
2491 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE register field value suitable for setting the register. */
2492 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
2493 
2494 #ifndef __ASSEMBLY__
2495 /*
2496  * WARNING: The C register and register group struct declarations are provided for
2497  * convenience and illustrative purposes. They should, however, be used with
2498  * caution as the C language standard provides no guarantees about the alignment or
2499  * atomicity of device memory accesses. The recommended practice for coding device
2500  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2501  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2502  * alt_write_dword() functions for 64 bit registers.
2503  *
2504  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE.
2505  */
2506 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_s
2507 {
2508  volatile uint32_t FILTERS_1_WINDOWSIZE : 6; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE */
2509  uint32_t : 26; /* *UNDEFINED* */
2510 };
2511 
2512 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE. */
2513 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_t;
2514 #endif /* __ASSEMBLY__ */
2515 
2516 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE register. */
2517 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_RESET 0x00000000
2518 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE register from the beginning of the component. */
2519 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_OFST 0x90
2520 
2521 /*
2522  * Register : probe_soc2fpga_main_Probe_Filters_1_SecurityBase
2523  *
2524  * Register Layout
2525  *
2526  * Bits | Access | Reset | Description
2527  * :-------|:-------|:--------|:-------------------------------------------------------------------------------------------------
2528  * [1:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE
2529  * [31:2] | ??? | Unknown | *UNDEFINED*
2530  *
2531  */
2532 /*
2533  * Field : FILTERS_1_SECURITYBASE
2534  *
2535  * Register SecurityBase contains the security base used to filter packets.
2536  *
2537  * Field Access Macros:
2538  *
2539  */
2540 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE register field. */
2541 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_LSB 0
2542 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE register field. */
2543 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_MSB 1
2544 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE register field. */
2545 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_WIDTH 2
2546 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE register field value. */
2547 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_SET_MSK 0x00000003
2548 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE register field value. */
2549 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_CLR_MSK 0xfffffffc
2550 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE register field. */
2551 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_RESET 0x0
2552 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE field value from a register. */
2553 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_GET(value) (((value) & 0x00000003) >> 0)
2554 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE register field value suitable for setting the register. */
2555 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_SET(value) (((value) << 0) & 0x00000003)
2556 
2557 #ifndef __ASSEMBLY__
2558 /*
2559  * WARNING: The C register and register group struct declarations are provided for
2560  * convenience and illustrative purposes. They should, however, be used with
2561  * caution as the C language standard provides no guarantees about the alignment or
2562  * atomicity of device memory accesses. The recommended practice for coding device
2563  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2564  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2565  * alt_write_dword() functions for 64 bit registers.
2566  *
2567  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE.
2568  */
2569 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_s
2570 {
2571  volatile uint32_t FILTERS_1_SECURITYBASE : 2; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE */
2572  uint32_t : 30; /* *UNDEFINED* */
2573 };
2574 
2575 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE. */
2576 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_t;
2577 #endif /* __ASSEMBLY__ */
2578 
2579 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE register. */
2580 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_RESET 0x00000000
2581 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE register from the beginning of the component. */
2582 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_OFST 0x94
2583 
2584 /*
2585  * Register : probe_soc2fpga_main_Probe_Filters_1_SecurityMask
2586  *
2587  * Register Layout
2588  *
2589  * Bits | Access | Reset | Description
2590  * :-------|:-------|:--------|:-------------------------------------------------------------------------------------------------
2591  * [1:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK
2592  * [31:2] | ??? | Unknown | *UNDEFINED*
2593  *
2594  */
2595 /*
2596  * Field : FILTERS_1_SECURITYMASK
2597  *
2598  * Register SecurityMask is contains the security mask used to filter packets. A
2599  * packet is a candidate when: packet.Security & SecurityMask = SecurityBase &
2600  * SecurityMasks.
2601  *
2602  * Field Access Macros:
2603  *
2604  */
2605 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK register field. */
2606 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_LSB 0
2607 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK register field. */
2608 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_MSB 1
2609 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK register field. */
2610 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_WIDTH 2
2611 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK register field value. */
2612 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_SET_MSK 0x00000003
2613 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK register field value. */
2614 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_CLR_MSK 0xfffffffc
2615 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK register field. */
2616 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_RESET 0x0
2617 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK field value from a register. */
2618 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_GET(value) (((value) & 0x00000003) >> 0)
2619 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK register field value suitable for setting the register. */
2620 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_SET(value) (((value) << 0) & 0x00000003)
2621 
2622 #ifndef __ASSEMBLY__
2623 /*
2624  * WARNING: The C register and register group struct declarations are provided for
2625  * convenience and illustrative purposes. They should, however, be used with
2626  * caution as the C language standard provides no guarantees about the alignment or
2627  * atomicity of device memory accesses. The recommended practice for coding device
2628  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2629  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2630  * alt_write_dword() functions for 64 bit registers.
2631  *
2632  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK.
2633  */
2634 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_s
2635 {
2636  volatile uint32_t FILTERS_1_SECURITYMASK : 2; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK */
2637  uint32_t : 30; /* *UNDEFINED* */
2638 };
2639 
2640 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK. */
2641 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_t;
2642 #endif /* __ASSEMBLY__ */
2643 
2644 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK register. */
2645 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_RESET 0x00000000
2646 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK register from the beginning of the component. */
2647 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_OFST 0x98
2648 
2649 /*
2650  * Register : probe_soc2fpga_main_Probe_Filters_1_Opcode
2651  *
2652  * Packet Probe register Opcode is a 4-bit register that selects candidate packets
2653  * based on packet opcodes (0 disables the filter):
2654  *
2655  * Register Layout
2656  *
2657  * Bits | Access | Reset | Description
2658  * :-------|:-------|:--------|:---------------------------------------------------------------------------
2659  * [0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_RDEN
2660  * [1] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_WREN
2661  * [2] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN
2662  * [3] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_URGEN
2663  * [31:4] | ??? | Unknown | *UNDEFINED*
2664  *
2665  */
2666 /*
2667  * Field : RDEN
2668  *
2669  * Selects RD packets.
2670  *
2671  * Field Access Macros:
2672  *
2673  */
2674 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_RDEN register field. */
2675 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_LSB 0
2676 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_RDEN register field. */
2677 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_MSB 0
2678 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_RDEN register field. */
2679 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_WIDTH 1
2680 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_RDEN register field value. */
2681 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_SET_MSK 0x00000001
2682 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_RDEN register field value. */
2683 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_CLR_MSK 0xfffffffe
2684 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_RDEN register field. */
2685 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_RESET 0x0
2686 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_RDEN field value from a register. */
2687 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
2688 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_RDEN register field value suitable for setting the register. */
2689 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
2690 
2691 /*
2692  * Field : WREN
2693  *
2694  * Selects WR packets.
2695  *
2696  * Field Access Macros:
2697  *
2698  */
2699 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_WREN register field. */
2700 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_WREN_LSB 1
2701 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_WREN register field. */
2702 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_WREN_MSB 1
2703 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_WREN register field. */
2704 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_WREN_WIDTH 1
2705 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_WREN register field value. */
2706 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_WREN_SET_MSK 0x00000002
2707 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_WREN register field value. */
2708 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_WREN_CLR_MSK 0xfffffffd
2709 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_WREN register field. */
2710 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_WREN_RESET 0x0
2711 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_WREN field value from a register. */
2712 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
2713 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_WREN register field value suitable for setting the register. */
2714 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
2715 
2716 /*
2717  * Field : LOCKEN
2718  *
2719  * Selects RDX-WR, RDL, WRC and Linked sequence.
2720  *
2721  * Field Access Macros:
2722  *
2723  */
2724 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN register field. */
2725 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_LSB 2
2726 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN register field. */
2727 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_MSB 2
2728 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN register field. */
2729 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_WIDTH 1
2730 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN register field value. */
2731 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_SET_MSK 0x00000004
2732 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN register field value. */
2733 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
2734 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN register field. */
2735 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_RESET 0x0
2736 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN field value from a register. */
2737 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
2738 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN register field value suitable for setting the register. */
2739 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
2740 
2741 /*
2742  * Field : URGEN
2743  *
2744  * Selects URG packets (urgency).
2745  *
2746  * Field Access Macros:
2747  *
2748  */
2749 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_URGEN register field. */
2750 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_LSB 3
2751 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_URGEN register field. */
2752 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_MSB 3
2753 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_URGEN register field. */
2754 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_WIDTH 1
2755 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_URGEN register field value. */
2756 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_SET_MSK 0x00000008
2757 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_URGEN register field value. */
2758 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_CLR_MSK 0xfffffff7
2759 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_URGEN register field. */
2760 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_RESET 0x0
2761 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_URGEN field value from a register. */
2762 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
2763 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_URGEN register field value suitable for setting the register. */
2764 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
2765 
2766 #ifndef __ASSEMBLY__
2767 /*
2768  * WARNING: The C register and register group struct declarations are provided for
2769  * convenience and illustrative purposes. They should, however, be used with
2770  * caution as the C language standard provides no guarantees about the alignment or
2771  * atomicity of device memory accesses. The recommended practice for coding device
2772  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2773  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2774  * alt_write_dword() functions for 64 bit registers.
2775  *
2776  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE.
2777  */
2778 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_s
2779 {
2780  volatile uint32_t RDEN : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_RDEN */
2781  volatile uint32_t WREN : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_WREN */
2782  volatile uint32_t LOCKEN : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN */
2783  volatile uint32_t URGEN : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_URGEN */
2784  uint32_t : 28; /* *UNDEFINED* */
2785 };
2786 
2787 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE. */
2788 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_t;
2789 #endif /* __ASSEMBLY__ */
2790 
2791 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE register. */
2792 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_RESET 0x00000000
2793 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE register from the beginning of the component. */
2794 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_OFST 0x9c
2795 
2796 /*
2797  * Register : probe_soc2fpga_main_Probe_Filters_1_Status
2798  *
2799  * Register Status is 2-bit register that selects candidate packets based on packet
2800  * status.
2801  *
2802  * Register Layout
2803  *
2804  * Bits | Access | Reset | Description
2805  * :-------|:-------|:--------|:--------------------------------------------------------------------------
2806  * [0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_REQEN
2807  * [1] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_RSPEN
2808  * [31:2] | ??? | Unknown | *UNDEFINED*
2809  *
2810  */
2811 /*
2812  * Field : REQEN
2813  *
2814  * Selects REQ status packets.
2815  *
2816  * Field Access Macros:
2817  *
2818  */
2819 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_REQEN register field. */
2820 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_REQEN_LSB 0
2821 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_REQEN register field. */
2822 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_REQEN_MSB 0
2823 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_REQEN register field. */
2824 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_REQEN_WIDTH 1
2825 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_REQEN register field value. */
2826 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_REQEN_SET_MSK 0x00000001
2827 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_REQEN register field value. */
2828 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_REQEN_CLR_MSK 0xfffffffe
2829 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_REQEN register field. */
2830 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_REQEN_RESET 0x0
2831 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_REQEN field value from a register. */
2832 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_REQEN_GET(value) (((value) & 0x00000001) >> 0)
2833 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_REQEN register field value suitable for setting the register. */
2834 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_REQEN_SET(value) (((value) << 0) & 0x00000001)
2835 
2836 /*
2837  * Field : RSPEN
2838  *
2839  * Selects RSP and FAIL-CONT status packets.
2840  *
2841  * Field Access Macros:
2842  *
2843  */
2844 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_RSPEN register field. */
2845 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_LSB 1
2846 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_RSPEN register field. */
2847 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_MSB 1
2848 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_RSPEN register field. */
2849 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_WIDTH 1
2850 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_RSPEN register field value. */
2851 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_SET_MSK 0x00000002
2852 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_RSPEN register field value. */
2853 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_CLR_MSK 0xfffffffd
2854 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_RSPEN register field. */
2855 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_RESET 0x0
2856 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_RSPEN field value from a register. */
2857 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
2858 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_RSPEN register field value suitable for setting the register. */
2859 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_SET(value) (((value) << 1) & 0x00000002)
2860 
2861 #ifndef __ASSEMBLY__
2862 /*
2863  * WARNING: The C register and register group struct declarations are provided for
2864  * convenience and illustrative purposes. They should, however, be used with
2865  * caution as the C language standard provides no guarantees about the alignment or
2866  * atomicity of device memory accesses. The recommended practice for coding device
2867  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2868  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2869  * alt_write_dword() functions for 64 bit registers.
2870  *
2871  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS.
2872  */
2873 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_s
2874 {
2875  volatile uint32_t REQEN : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_REQEN */
2876  volatile uint32_t RSPEN : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_RSPEN */
2877  uint32_t : 30; /* *UNDEFINED* */
2878 };
2879 
2880 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS. */
2881 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_t;
2882 #endif /* __ASSEMBLY__ */
2883 
2884 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS register. */
2885 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_RESET 0x00000000
2886 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS register from the beginning of the component. */
2887 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_OFST 0xa0
2888 
2889 /*
2890  * Register : probe_soc2fpga_main_Probe_Filters_1_Length
2891  *
2892  * Register Layout
2893  *
2894  * Bits | Access | Reset | Description
2895  * :-------|:-------|:--------|:-------------------------------------------------------------------------------------
2896  * [3:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH
2897  * [31:4] | ??? | Unknown | *UNDEFINED*
2898  *
2899  */
2900 /*
2901  * Field : FILTERS_1_LENGTH
2902  *
2903  * Register Length is 4-bit register that selects candidate packets if their number
2904  * of bytes is less than or equal to 2**Length.
2905  *
2906  * Field Access Macros:
2907  *
2908  */
2909 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH register field. */
2910 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_LSB 0
2911 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH register field. */
2912 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_MSB 3
2913 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH register field. */
2914 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_WIDTH 4
2915 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH register field value. */
2916 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_SET_MSK 0x0000000f
2917 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH register field value. */
2918 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_CLR_MSK 0xfffffff0
2919 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH register field. */
2920 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_RESET 0x0
2921 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH field value from a register. */
2922 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_GET(value) (((value) & 0x0000000f) >> 0)
2923 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH register field value suitable for setting the register. */
2924 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_SET(value) (((value) << 0) & 0x0000000f)
2925 
2926 #ifndef __ASSEMBLY__
2927 /*
2928  * WARNING: The C register and register group struct declarations are provided for
2929  * convenience and illustrative purposes. They should, however, be used with
2930  * caution as the C language standard provides no guarantees about the alignment or
2931  * atomicity of device memory accesses. The recommended practice for coding device
2932  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2933  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2934  * alt_write_dword() functions for 64 bit registers.
2935  *
2936  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH.
2937  */
2938 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_s
2939 {
2940  volatile uint32_t FILTERS_1_LENGTH : 4; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH */
2941  uint32_t : 28; /* *UNDEFINED* */
2942 };
2943 
2944 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH. */
2945 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_t;
2946 #endif /* __ASSEMBLY__ */
2947 
2948 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH register. */
2949 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_RESET 0x00000000
2950 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH register from the beginning of the component. */
2951 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_OFST 0xa4
2952 
2953 /*
2954  * Register : probe_soc2fpga_main_Probe_Filters_1_Urgency
2955  *
2956  * Register Layout
2957  *
2958  * Bits | Access | Reset | Description
2959  * :-------|:-------|:--------|:---------------------------------------------------------------------------------------
2960  * [1:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY
2961  * [31:2] | ??? | Unknown | *UNDEFINED*
2962  *
2963  */
2964 /*
2965  * Field : FILTERS_1_URGENCY
2966  *
2967  * Register Urgency contains the minimum urgency level used to filter packets. A
2968  * packet is a candidate when its socket urgency is greater than or equal to the
2969  * urgency specified in the register.
2970  *
2971  * Field Access Macros:
2972  *
2973  */
2974 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY register field. */
2975 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_LSB 0
2976 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY register field. */
2977 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_MSB 1
2978 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY register field. */
2979 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_WIDTH 2
2980 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY register field value. */
2981 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_SET_MSK 0x00000003
2982 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY register field value. */
2983 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_CLR_MSK 0xfffffffc
2984 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY register field. */
2985 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_RESET 0x0
2986 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY field value from a register. */
2987 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
2988 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY register field value suitable for setting the register. */
2989 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_SET(value) (((value) << 0) & 0x00000003)
2990 
2991 #ifndef __ASSEMBLY__
2992 /*
2993  * WARNING: The C register and register group struct declarations are provided for
2994  * convenience and illustrative purposes. They should, however, be used with
2995  * caution as the C language standard provides no guarantees about the alignment or
2996  * atomicity of device memory accesses. The recommended practice for coding device
2997  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2998  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2999  * alt_write_dword() functions for 64 bit registers.
3000  *
3001  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY.
3002  */
3003 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_s
3004 {
3005  volatile uint32_t FILTERS_1_URGENCY : 2; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY */
3006  uint32_t : 30; /* *UNDEFINED* */
3007 };
3008 
3009 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY. */
3010 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_t;
3011 #endif /* __ASSEMBLY__ */
3012 
3013 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY register. */
3014 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_RESET 0x00000000
3015 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY register from the beginning of the component. */
3016 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_OFST 0xa8
3017 
3018 /*
3019  * Register : probe_soc2fpga_main_Probe_Counters_0_PortSel
3020  *
3021  * Register Layout
3022  *
3023  * Bits | Access | Reset | Description
3024  * :-------|:-------|:--------|:-----------------------------------------------------------------------------------------
3025  * [0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_COUNTERS_0_PORTSEL
3026  * [31:1] | ??? | Unknown | *UNDEFINED*
3027  *
3028  */
3029 /*
3030  * Field : COUNTERS_0_PORTSEL
3031  *
3032  * Register PortSel indicates which NTTP link is associated with the counter. The
3033  * register can be changed at any time, with the change effective immediately. The
3034  * LUT and FILTx sources do not depend on this NTTP port selection.
3035  *
3036  * Field Access Macros:
3037  *
3038  */
3039 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_COUNTERS_0_PORTSEL register field. */
3040 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_COUNTERS_0_PORTSEL_LSB 0
3041 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_COUNTERS_0_PORTSEL register field. */
3042 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_COUNTERS_0_PORTSEL_MSB 0
3043 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_COUNTERS_0_PORTSEL register field. */
3044 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_COUNTERS_0_PORTSEL_WIDTH 1
3045 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_COUNTERS_0_PORTSEL register field value. */
3046 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_COUNTERS_0_PORTSEL_SET_MSK 0x00000001
3047 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_COUNTERS_0_PORTSEL register field value. */
3048 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_COUNTERS_0_PORTSEL_CLR_MSK 0xfffffffe
3049 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_COUNTERS_0_PORTSEL register field. */
3050 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_COUNTERS_0_PORTSEL_RESET 0x0
3051 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_COUNTERS_0_PORTSEL field value from a register. */
3052 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_COUNTERS_0_PORTSEL_GET(value) (((value) & 0x00000001) >> 0)
3053 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_COUNTERS_0_PORTSEL register field value suitable for setting the register. */
3054 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_COUNTERS_0_PORTSEL_SET(value) (((value) << 0) & 0x00000001)
3055 
3056 #ifndef __ASSEMBLY__
3057 /*
3058  * WARNING: The C register and register group struct declarations are provided for
3059  * convenience and illustrative purposes. They should, however, be used with
3060  * caution as the C language standard provides no guarantees about the alignment or
3061  * atomicity of device memory accesses. The recommended practice for coding device
3062  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3063  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3064  * alt_write_dword() functions for 64 bit registers.
3065  *
3066  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL.
3067  */
3068 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_s
3069 {
3070  volatile uint32_t COUNTERS_0_PORTSEL : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_COUNTERS_0_PORTSEL */
3071  uint32_t : 31; /* *UNDEFINED* */
3072 };
3073 
3074 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL. */
3075 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_t;
3076 #endif /* __ASSEMBLY__ */
3077 
3078 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL register. */
3079 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_RESET 0x00000000
3080 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL register from the beginning of the component. */
3081 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_OFST 0x134
3082 
3083 /*
3084  * Register : probe_soc2fpga_main_Probe_Counters_0_Src
3085  *
3086  * Register CntSrc indicates the event source used to increment the counter.
3087  * Unassigned values (non-existing Press level or ExtEvent index, or unimplemented
3088  * Filter) are equivalent to OFF.
3089  *
3090  * Register Layout
3091  *
3092  * Bits | Access | Reset | Description
3093  * :-------|:-------|:--------|:---------------------------------------------------------------------------
3094  * [4:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT
3095  * [31:5] | ??? | Unknown | *UNDEFINED*
3096  *
3097  */
3098 /*
3099  * Field : INTEVENT
3100  *
3101  * Internal packet event
3102  *
3103  * Field Access Macros:
3104  *
3105  */
3106 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT register field. */
3107 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_LSB 0
3108 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT register field. */
3109 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_MSB 4
3110 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT register field. */
3111 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_WIDTH 5
3112 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT register field value. */
3113 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_SET_MSK 0x0000001f
3114 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT register field value. */
3115 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_CLR_MSK 0xffffffe0
3116 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT register field. */
3117 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_RESET 0x0
3118 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT field value from a register. */
3119 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
3120 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT register field value suitable for setting the register. */
3121 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
3122 
3123 #ifndef __ASSEMBLY__
3124 /*
3125  * WARNING: The C register and register group struct declarations are provided for
3126  * convenience and illustrative purposes. They should, however, be used with
3127  * caution as the C language standard provides no guarantees about the alignment or
3128  * atomicity of device memory accesses. The recommended practice for coding device
3129  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3130  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3131  * alt_write_dword() functions for 64 bit registers.
3132  *
3133  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC.
3134  */
3135 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_s
3136 {
3137  volatile uint32_t INTEVENT : 5; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT */
3138  uint32_t : 27; /* *UNDEFINED* */
3139 };
3140 
3141 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC. */
3142 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_t;
3143 #endif /* __ASSEMBLY__ */
3144 
3145 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC register. */
3146 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_RESET 0x00000000
3147 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC register from the beginning of the component. */
3148 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_OFST 0x138
3149 
3150 /*
3151  * Register : probe_soc2fpga_main_Probe_Counters_0_AlarmMode
3152  *
3153  * Register Layout
3154  *
3155  * Bits | Access | Reset | Description
3156  * :-------|:-------|:--------|:---------------------------------------------------------------------------------------------
3157  * [1:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE
3158  * [31:2] | ??? | Unknown | *UNDEFINED*
3159  *
3160  */
3161 /*
3162  * Field : COUNTERS_0_ALARMMODE
3163  *
3164  * Register AlarmMode is a 2-bit register that is present when parameter
3165  * statisticsCounterAlarm is set to True. The register defines the statistics-alarm
3166  * behavior of the counter.
3167  *
3168  * Field Access Macros:
3169  *
3170  */
3171 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE register field. */
3172 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_LSB 0
3173 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE register field. */
3174 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_MSB 1
3175 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE register field. */
3176 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_WIDTH 2
3177 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE register field value. */
3178 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_SET_MSK 0x00000003
3179 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE register field value. */
3180 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_CLR_MSK 0xfffffffc
3181 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE register field. */
3182 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_RESET 0x0
3183 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE field value from a register. */
3184 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_GET(value) (((value) & 0x00000003) >> 0)
3185 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE register field value suitable for setting the register. */
3186 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_SET(value) (((value) << 0) & 0x00000003)
3187 
3188 #ifndef __ASSEMBLY__
3189 /*
3190  * WARNING: The C register and register group struct declarations are provided for
3191  * convenience and illustrative purposes. They should, however, be used with
3192  * caution as the C language standard provides no guarantees about the alignment or
3193  * atomicity of device memory accesses. The recommended practice for coding device
3194  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3195  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3196  * alt_write_dword() functions for 64 bit registers.
3197  *
3198  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE.
3199  */
3200 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_s
3201 {
3202  volatile uint32_t COUNTERS_0_ALARMMODE : 2; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE */
3203  uint32_t : 30; /* *UNDEFINED* */
3204 };
3205 
3206 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE. */
3207 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_t;
3208 #endif /* __ASSEMBLY__ */
3209 
3210 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE register. */
3211 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_RESET 0x00000000
3212 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE register from the beginning of the component. */
3213 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_OFST 0x13c
3214 
3215 /*
3216  * Register : probe_soc2fpga_main_Probe_Counters_0_Val
3217  *
3218  * Register Layout
3219  *
3220  * Bits | Access | Reset | Description
3221  * :--------|:-------|:--------|:---------------------------------------------------------------------------------
3222  * [15:0] | R | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL
3223  * [31:16] | ??? | Unknown | *UNDEFINED*
3224  *
3225  */
3226 /*
3227  * Field : COUNTERS_0_VAL
3228  *
3229  * Register Val is a read-only register that is always present. The register
3230  * containsthe statistics counter value either pending StatAlarm output, or when
3231  * statisticscollection is suspended subsequent to triggers or signal statSuspend.
3232  *
3233  * Field Access Macros:
3234  *
3235  */
3236 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL register field. */
3237 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_LSB 0
3238 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL register field. */
3239 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_MSB 15
3240 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL register field. */
3241 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_WIDTH 16
3242 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL register field value. */
3243 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_SET_MSK 0x0000ffff
3244 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL register field value. */
3245 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_CLR_MSK 0xffff0000
3246 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL register field. */
3247 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_RESET 0x0
3248 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL field value from a register. */
3249 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
3250 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL register field value suitable for setting the register. */
3251 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_SET(value) (((value) << 0) & 0x0000ffff)
3252 
3253 #ifndef __ASSEMBLY__
3254 /*
3255  * WARNING: The C register and register group struct declarations are provided for
3256  * convenience and illustrative purposes. They should, however, be used with
3257  * caution as the C language standard provides no guarantees about the alignment or
3258  * atomicity of device memory accesses. The recommended practice for coding device
3259  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3260  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3261  * alt_write_dword() functions for 64 bit registers.
3262  *
3263  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL.
3264  */
3265 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_s
3266 {
3267  const volatile uint32_t COUNTERS_0_VAL : 16; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL */
3268  uint32_t : 16; /* *UNDEFINED* */
3269 };
3270 
3271 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL. */
3272 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_t;
3273 #endif /* __ASSEMBLY__ */
3274 
3275 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL register. */
3276 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_RESET 0x00000000
3277 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL register from the beginning of the component. */
3278 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_OFST 0x140
3279 
3280 /*
3281  * Register : probe_soc2fpga_main_Probe_Counters_1_PortSel
3282  *
3283  * Register Layout
3284  *
3285  * Bits | Access | Reset | Description
3286  * :-------|:-------|:--------|:-----------------------------------------------------------------------------------------
3287  * [0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_COUNTERS_1_PORTSEL
3288  * [31:1] | ??? | Unknown | *UNDEFINED*
3289  *
3290  */
3291 /*
3292  * Field : COUNTERS_1_PORTSEL
3293  *
3294  * Register PortSel indicates which NTTP link is associated with the counter. The
3295  * register can be changed at any time, with the change effective immediately. The
3296  * LUT and FILTx sources do not depend on this NTTP port selection.
3297  *
3298  * Field Access Macros:
3299  *
3300  */
3301 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_COUNTERS_1_PORTSEL register field. */
3302 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_COUNTERS_1_PORTSEL_LSB 0
3303 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_COUNTERS_1_PORTSEL register field. */
3304 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_COUNTERS_1_PORTSEL_MSB 0
3305 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_COUNTERS_1_PORTSEL register field. */
3306 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_COUNTERS_1_PORTSEL_WIDTH 1
3307 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_COUNTERS_1_PORTSEL register field value. */
3308 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_COUNTERS_1_PORTSEL_SET_MSK 0x00000001
3309 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_COUNTERS_1_PORTSEL register field value. */
3310 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_COUNTERS_1_PORTSEL_CLR_MSK 0xfffffffe
3311 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_COUNTERS_1_PORTSEL register field. */
3312 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_COUNTERS_1_PORTSEL_RESET 0x0
3313 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_COUNTERS_1_PORTSEL field value from a register. */
3314 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_COUNTERS_1_PORTSEL_GET(value) (((value) & 0x00000001) >> 0)
3315 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_COUNTERS_1_PORTSEL register field value suitable for setting the register. */
3316 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_COUNTERS_1_PORTSEL_SET(value) (((value) << 0) & 0x00000001)
3317 
3318 #ifndef __ASSEMBLY__
3319 /*
3320  * WARNING: The C register and register group struct declarations are provided for
3321  * convenience and illustrative purposes. They should, however, be used with
3322  * caution as the C language standard provides no guarantees about the alignment or
3323  * atomicity of device memory accesses. The recommended practice for coding device
3324  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3325  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3326  * alt_write_dword() functions for 64 bit registers.
3327  *
3328  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL.
3329  */
3330 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_s
3331 {
3332  volatile uint32_t COUNTERS_1_PORTSEL : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_COUNTERS_1_PORTSEL */
3333  uint32_t : 31; /* *UNDEFINED* */
3334 };
3335 
3336 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL. */
3337 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_t;
3338 #endif /* __ASSEMBLY__ */
3339 
3340 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL register. */
3341 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_RESET 0x00000000
3342 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL register from the beginning of the component. */
3343 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_OFST 0x148
3344 
3345 /*
3346  * Register : probe_soc2fpga_main_Probe_Counters_1_Src
3347  *
3348  * Register CntSrc indicates the event source used to increment the counter.
3349  * Unassigned values (non-existing Press level or ExtEvent index, or unimplemented
3350  * Filter) are equivalent to OFF.
3351  *
3352  * Register Layout
3353  *
3354  * Bits | Access | Reset | Description
3355  * :-------|:-------|:--------|:---------------------------------------------------------------------------
3356  * [4:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT
3357  * [31:5] | ??? | Unknown | *UNDEFINED*
3358  *
3359  */
3360 /*
3361  * Field : INTEVENT
3362  *
3363  * Internal packet event
3364  *
3365  * Field Access Macros:
3366  *
3367  */
3368 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT register field. */
3369 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_LSB 0
3370 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT register field. */
3371 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_MSB 4
3372 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT register field. */
3373 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_WIDTH 5
3374 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT register field value. */
3375 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_SET_MSK 0x0000001f
3376 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT register field value. */
3377 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_CLR_MSK 0xffffffe0
3378 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT register field. */
3379 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_RESET 0x0
3380 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT field value from a register. */
3381 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
3382 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT register field value suitable for setting the register. */
3383 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
3384 
3385 #ifndef __ASSEMBLY__
3386 /*
3387  * WARNING: The C register and register group struct declarations are provided for
3388  * convenience and illustrative purposes. They should, however, be used with
3389  * caution as the C language standard provides no guarantees about the alignment or
3390  * atomicity of device memory accesses. The recommended practice for coding device
3391  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3392  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3393  * alt_write_dword() functions for 64 bit registers.
3394  *
3395  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC.
3396  */
3397 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_s
3398 {
3399  volatile uint32_t INTEVENT : 5; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT */
3400  uint32_t : 27; /* *UNDEFINED* */
3401 };
3402 
3403 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC. */
3404 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_t;
3405 #endif /* __ASSEMBLY__ */
3406 
3407 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC register. */
3408 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_RESET 0x00000000
3409 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC register from the beginning of the component. */
3410 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_OFST 0x14c
3411 
3412 /*
3413  * Register : probe_soc2fpga_main_Probe_Counters_1_AlarmMode
3414  *
3415  * Register Layout
3416  *
3417  * Bits | Access | Reset | Description
3418  * :-------|:-------|:--------|:---------------------------------------------------------------------------------------------
3419  * [1:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE
3420  * [31:2] | ??? | Unknown | *UNDEFINED*
3421  *
3422  */
3423 /*
3424  * Field : COUNTERS_1_ALARMMODE
3425  *
3426  * Register AlarmMode is a 2-bit register that is present when parameter
3427  * statisticsCounterAlarm is set to True. The register defines the statistics-alarm
3428  * behavior of the counter.
3429  *
3430  * Field Access Macros:
3431  *
3432  */
3433 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE register field. */
3434 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_LSB 0
3435 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE register field. */
3436 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_MSB 1
3437 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE register field. */
3438 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_WIDTH 2
3439 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE register field value. */
3440 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_SET_MSK 0x00000003
3441 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE register field value. */
3442 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_CLR_MSK 0xfffffffc
3443 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE register field. */
3444 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_RESET 0x0
3445 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE field value from a register. */
3446 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_GET(value) (((value) & 0x00000003) >> 0)
3447 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE register field value suitable for setting the register. */
3448 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_SET(value) (((value) << 0) & 0x00000003)
3449 
3450 #ifndef __ASSEMBLY__
3451 /*
3452  * WARNING: The C register and register group struct declarations are provided for
3453  * convenience and illustrative purposes. They should, however, be used with
3454  * caution as the C language standard provides no guarantees about the alignment or
3455  * atomicity of device memory accesses. The recommended practice for coding device
3456  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3457  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3458  * alt_write_dword() functions for 64 bit registers.
3459  *
3460  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE.
3461  */
3462 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_s
3463 {
3464  volatile uint32_t COUNTERS_1_ALARMMODE : 2; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE */
3465  uint32_t : 30; /* *UNDEFINED* */
3466 };
3467 
3468 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE. */
3469 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_t;
3470 #endif /* __ASSEMBLY__ */
3471 
3472 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE register. */
3473 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_RESET 0x00000000
3474 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE register from the beginning of the component. */
3475 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_OFST 0x150
3476 
3477 /*
3478  * Register : probe_soc2fpga_main_Probe_Counters_1_Val
3479  *
3480  * Register Layout
3481  *
3482  * Bits | Access | Reset | Description
3483  * :--------|:-------|:--------|:---------------------------------------------------------------------------------
3484  * [15:0] | R | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL
3485  * [31:16] | ??? | Unknown | *UNDEFINED*
3486  *
3487  */
3488 /*
3489  * Field : COUNTERS_1_VAL
3490  *
3491  * Register Val is a read-only register that is always present. The register
3492  * containsthe statistics counter value either pending StatAlarm output, or when
3493  * statisticscollection is suspended subsequent to triggers or signal statSuspend.
3494  *
3495  * Field Access Macros:
3496  *
3497  */
3498 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL register field. */
3499 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_LSB 0
3500 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL register field. */
3501 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_MSB 15
3502 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL register field. */
3503 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_WIDTH 16
3504 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL register field value. */
3505 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_SET_MSK 0x0000ffff
3506 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL register field value. */
3507 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_CLR_MSK 0xffff0000
3508 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL register field. */
3509 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_RESET 0x0
3510 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL field value from a register. */
3511 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
3512 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL register field value suitable for setting the register. */
3513 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_SET(value) (((value) << 0) & 0x0000ffff)
3514 
3515 #ifndef __ASSEMBLY__
3516 /*
3517  * WARNING: The C register and register group struct declarations are provided for
3518  * convenience and illustrative purposes. They should, however, be used with
3519  * caution as the C language standard provides no guarantees about the alignment or
3520  * atomicity of device memory accesses. The recommended practice for coding device
3521  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3522  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3523  * alt_write_dword() functions for 64 bit registers.
3524  *
3525  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL.
3526  */
3527 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_s
3528 {
3529  const volatile uint32_t COUNTERS_1_VAL : 16; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL */
3530  uint32_t : 16; /* *UNDEFINED* */
3531 };
3532 
3533 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL. */
3534 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_t;
3535 #endif /* __ASSEMBLY__ */
3536 
3537 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL register. */
3538 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_RESET 0x00000000
3539 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL register from the beginning of the component. */
3540 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_OFST 0x154
3541 
3542 /*
3543  * Register : probe_soc2fpga_main_Probe_Counters_2_PortSel
3544  *
3545  * Register Layout
3546  *
3547  * Bits | Access | Reset | Description
3548  * :-------|:-------|:--------|:-----------------------------------------------------------------------------------------
3549  * [0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_COUNTERS_2_PORTSEL
3550  * [31:1] | ??? | Unknown | *UNDEFINED*
3551  *
3552  */
3553 /*
3554  * Field : COUNTERS_2_PORTSEL
3555  *
3556  * Register PortSel indicates which NTTP link is associated with the counter. The
3557  * register can be changed at any time, with the change effective immediately. The
3558  * LUT and FILTx sources do not depend on this NTTP port selection.
3559  *
3560  * Field Access Macros:
3561  *
3562  */
3563 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_COUNTERS_2_PORTSEL register field. */
3564 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_COUNTERS_2_PORTSEL_LSB 0
3565 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_COUNTERS_2_PORTSEL register field. */
3566 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_COUNTERS_2_PORTSEL_MSB 0
3567 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_COUNTERS_2_PORTSEL register field. */
3568 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_COUNTERS_2_PORTSEL_WIDTH 1
3569 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_COUNTERS_2_PORTSEL register field value. */
3570 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_COUNTERS_2_PORTSEL_SET_MSK 0x00000001
3571 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_COUNTERS_2_PORTSEL register field value. */
3572 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_COUNTERS_2_PORTSEL_CLR_MSK 0xfffffffe
3573 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_COUNTERS_2_PORTSEL register field. */
3574 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_COUNTERS_2_PORTSEL_RESET 0x0
3575 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_COUNTERS_2_PORTSEL field value from a register. */
3576 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_COUNTERS_2_PORTSEL_GET(value) (((value) & 0x00000001) >> 0)
3577 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_COUNTERS_2_PORTSEL register field value suitable for setting the register. */
3578 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_COUNTERS_2_PORTSEL_SET(value) (((value) << 0) & 0x00000001)
3579 
3580 #ifndef __ASSEMBLY__
3581 /*
3582  * WARNING: The C register and register group struct declarations are provided for
3583  * convenience and illustrative purposes. They should, however, be used with
3584  * caution as the C language standard provides no guarantees about the alignment or
3585  * atomicity of device memory accesses. The recommended practice for coding device
3586  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3587  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3588  * alt_write_dword() functions for 64 bit registers.
3589  *
3590  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL.
3591  */
3592 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_s
3593 {
3594  volatile uint32_t COUNTERS_2_PORTSEL : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_COUNTERS_2_PORTSEL */
3595  uint32_t : 31; /* *UNDEFINED* */
3596 };
3597 
3598 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL. */
3599 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_t;
3600 #endif /* __ASSEMBLY__ */
3601 
3602 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL register. */
3603 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_RESET 0x00000000
3604 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL register from the beginning of the component. */
3605 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_OFST 0x15c
3606 
3607 /*
3608  * Register : probe_soc2fpga_main_Probe_Counters_2_Src
3609  *
3610  * Register CntSrc indicates the event source used to increment the counter.
3611  * Unassigned values (non-existing Press level or ExtEvent index, or unimplemented
3612  * Filter) are equivalent to OFF.
3613  *
3614  * Register Layout
3615  *
3616  * Bits | Access | Reset | Description
3617  * :-------|:-------|:--------|:---------------------------------------------------------------------------
3618  * [4:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT
3619  * [31:5] | ??? | Unknown | *UNDEFINED*
3620  *
3621  */
3622 /*
3623  * Field : INTEVENT
3624  *
3625  * Internal packet event
3626  *
3627  * Field Access Macros:
3628  *
3629  */
3630 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT register field. */
3631 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT_LSB 0
3632 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT register field. */
3633 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT_MSB 4
3634 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT register field. */
3635 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT_WIDTH 5
3636 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT register field value. */
3637 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT_SET_MSK 0x0000001f
3638 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT register field value. */
3639 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT_CLR_MSK 0xffffffe0
3640 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT register field. */
3641 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT_RESET 0x0
3642 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT field value from a register. */
3643 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
3644 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT register field value suitable for setting the register. */
3645 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
3646 
3647 #ifndef __ASSEMBLY__
3648 /*
3649  * WARNING: The C register and register group struct declarations are provided for
3650  * convenience and illustrative purposes. They should, however, be used with
3651  * caution as the C language standard provides no guarantees about the alignment or
3652  * atomicity of device memory accesses. The recommended practice for coding device
3653  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3654  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3655  * alt_write_dword() functions for 64 bit registers.
3656  *
3657  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC.
3658  */
3659 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_s
3660 {
3661  volatile uint32_t INTEVENT : 5; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT */
3662  uint32_t : 27; /* *UNDEFINED* */
3663 };
3664 
3665 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC. */
3666 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_t;
3667 #endif /* __ASSEMBLY__ */
3668 
3669 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC register. */
3670 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_RESET 0x00000000
3671 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC register from the beginning of the component. */
3672 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_OFST 0x160
3673 
3674 /*
3675  * Register : probe_soc2fpga_main_Probe_Counters_2_AlarmMode
3676  *
3677  * Register Layout
3678  *
3679  * Bits | Access | Reset | Description
3680  * :-------|:-------|:--------|:---------------------------------------------------------------------------------------------
3681  * [1:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_COUNTERS_2_ALARMMODE
3682  * [31:2] | ??? | Unknown | *UNDEFINED*
3683  *
3684  */
3685 /*
3686  * Field : COUNTERS_2_ALARMMODE
3687  *
3688  * Register AlarmMode is a 2-bit register that is present when parameter
3689  * statisticsCounterAlarm is set to True. The register defines the statistics-alarm
3690  * behavior of the counter.
3691  *
3692  * Field Access Macros:
3693  *
3694  */
3695 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_COUNTERS_2_ALARMMODE register field. */
3696 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_COUNTERS_2_ALARMMODE_LSB 0
3697 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_COUNTERS_2_ALARMMODE register field. */
3698 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_COUNTERS_2_ALARMMODE_MSB 1
3699 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_COUNTERS_2_ALARMMODE register field. */
3700 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_COUNTERS_2_ALARMMODE_WIDTH 2
3701 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_COUNTERS_2_ALARMMODE register field value. */
3702 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_COUNTERS_2_ALARMMODE_SET_MSK 0x00000003
3703 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_COUNTERS_2_ALARMMODE register field value. */
3704 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_COUNTERS_2_ALARMMODE_CLR_MSK 0xfffffffc
3705 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_COUNTERS_2_ALARMMODE register field. */
3706 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_COUNTERS_2_ALARMMODE_RESET 0x0
3707 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_COUNTERS_2_ALARMMODE field value from a register. */
3708 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_COUNTERS_2_ALARMMODE_GET(value) (((value) & 0x00000003) >> 0)
3709 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_COUNTERS_2_ALARMMODE register field value suitable for setting the register. */
3710 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_COUNTERS_2_ALARMMODE_SET(value) (((value) << 0) & 0x00000003)
3711 
3712 #ifndef __ASSEMBLY__
3713 /*
3714  * WARNING: The C register and register group struct declarations are provided for
3715  * convenience and illustrative purposes. They should, however, be used with
3716  * caution as the C language standard provides no guarantees about the alignment or
3717  * atomicity of device memory accesses. The recommended practice for coding device
3718  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3719  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3720  * alt_write_dword() functions for 64 bit registers.
3721  *
3722  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE.
3723  */
3724 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_s
3725 {
3726  volatile uint32_t COUNTERS_2_ALARMMODE : 2; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_COUNTERS_2_ALARMMODE */
3727  uint32_t : 30; /* *UNDEFINED* */
3728 };
3729 
3730 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE. */
3731 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_t;
3732 #endif /* __ASSEMBLY__ */
3733 
3734 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE register. */
3735 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_RESET 0x00000000
3736 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE register from the beginning of the component. */
3737 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_OFST 0x164
3738 
3739 /*
3740  * Register : probe_soc2fpga_main_Probe_Counters_2_Val
3741  *
3742  * Register Layout
3743  *
3744  * Bits | Access | Reset | Description
3745  * :--------|:-------|:--------|:---------------------------------------------------------------------------------
3746  * [15:0] | R | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL
3747  * [31:16] | ??? | Unknown | *UNDEFINED*
3748  *
3749  */
3750 /*
3751  * Field : COUNTERS_2_VAL
3752  *
3753  * Register Val is a read-only register that is always present. The register
3754  * containsthe statistics counter value either pending StatAlarm output, or when
3755  * statisticscollection is suspended subsequent to triggers or signal statSuspend.
3756  *
3757  * Field Access Macros:
3758  *
3759  */
3760 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL register field. */
3761 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL_LSB 0
3762 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL register field. */
3763 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL_MSB 15
3764 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL register field. */
3765 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL_WIDTH 16
3766 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL register field value. */
3767 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL_SET_MSK 0x0000ffff
3768 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL register field value. */
3769 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL_CLR_MSK 0xffff0000
3770 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL register field. */
3771 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL_RESET 0x0
3772 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL field value from a register. */
3773 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
3774 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL register field value suitable for setting the register. */
3775 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL_SET(value) (((value) << 0) & 0x0000ffff)
3776 
3777 #ifndef __ASSEMBLY__
3778 /*
3779  * WARNING: The C register and register group struct declarations are provided for
3780  * convenience and illustrative purposes. They should, however, be used with
3781  * caution as the C language standard provides no guarantees about the alignment or
3782  * atomicity of device memory accesses. The recommended practice for coding device
3783  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3784  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3785  * alt_write_dword() functions for 64 bit registers.
3786  *
3787  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL.
3788  */
3789 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_s
3790 {
3791  const volatile uint32_t COUNTERS_2_VAL : 16; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL */
3792  uint32_t : 16; /* *UNDEFINED* */
3793 };
3794 
3795 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL. */
3796 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_t;
3797 #endif /* __ASSEMBLY__ */
3798 
3799 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL register. */
3800 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_RESET 0x00000000
3801 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL register from the beginning of the component. */
3802 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_OFST 0x168
3803 
3804 /*
3805  * Register : probe_soc2fpga_main_Probe_Counters_3_PortSel
3806  *
3807  * Register Layout
3808  *
3809  * Bits | Access | Reset | Description
3810  * :-------|:-------|:--------|:-----------------------------------------------------------------------------------------
3811  * [0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_COUNTERS_3_PORTSEL
3812  * [31:1] | ??? | Unknown | *UNDEFINED*
3813  *
3814  */
3815 /*
3816  * Field : COUNTERS_3_PORTSEL
3817  *
3818  * Register PortSel indicates which NTTP link is associated with the counter. The
3819  * register can be changed at any time, with the change effective immediately. The
3820  * LUT and FILTx sources do not depend on this NTTP port selection.
3821  *
3822  * Field Access Macros:
3823  *
3824  */
3825 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_COUNTERS_3_PORTSEL register field. */
3826 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_COUNTERS_3_PORTSEL_LSB 0
3827 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_COUNTERS_3_PORTSEL register field. */
3828 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_COUNTERS_3_PORTSEL_MSB 0
3829 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_COUNTERS_3_PORTSEL register field. */
3830 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_COUNTERS_3_PORTSEL_WIDTH 1
3831 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_COUNTERS_3_PORTSEL register field value. */
3832 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_COUNTERS_3_PORTSEL_SET_MSK 0x00000001
3833 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_COUNTERS_3_PORTSEL register field value. */
3834 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_COUNTERS_3_PORTSEL_CLR_MSK 0xfffffffe
3835 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_COUNTERS_3_PORTSEL register field. */
3836 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_COUNTERS_3_PORTSEL_RESET 0x0
3837 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_COUNTERS_3_PORTSEL field value from a register. */
3838 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_COUNTERS_3_PORTSEL_GET(value) (((value) & 0x00000001) >> 0)
3839 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_COUNTERS_3_PORTSEL register field value suitable for setting the register. */
3840 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_COUNTERS_3_PORTSEL_SET(value) (((value) << 0) & 0x00000001)
3841 
3842 #ifndef __ASSEMBLY__
3843 /*
3844  * WARNING: The C register and register group struct declarations are provided for
3845  * convenience and illustrative purposes. They should, however, be used with
3846  * caution as the C language standard provides no guarantees about the alignment or
3847  * atomicity of device memory accesses. The recommended practice for coding device
3848  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3849  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3850  * alt_write_dword() functions for 64 bit registers.
3851  *
3852  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL.
3853  */
3854 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_s
3855 {
3856  volatile uint32_t COUNTERS_3_PORTSEL : 1; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_COUNTERS_3_PORTSEL */
3857  uint32_t : 31; /* *UNDEFINED* */
3858 };
3859 
3860 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL. */
3861 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_t;
3862 #endif /* __ASSEMBLY__ */
3863 
3864 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL register. */
3865 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_RESET 0x00000000
3866 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL register from the beginning of the component. */
3867 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_OFST 0x170
3868 
3869 /*
3870  * Register : probe_soc2fpga_main_Probe_Counters_3_Src
3871  *
3872  * Register CntSrc indicates the event source used to increment the counter.
3873  * Unassigned values (non-existing Press level or ExtEvent index, or unimplemented
3874  * Filter) are equivalent to OFF.
3875  *
3876  * Register Layout
3877  *
3878  * Bits | Access | Reset | Description
3879  * :-------|:-------|:--------|:---------------------------------------------------------------------------
3880  * [4:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT
3881  * [31:5] | ??? | Unknown | *UNDEFINED*
3882  *
3883  */
3884 /*
3885  * Field : INTEVENT
3886  *
3887  * Internal packet event
3888  *
3889  * Field Access Macros:
3890  *
3891  */
3892 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT register field. */
3893 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT_LSB 0
3894 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT register field. */
3895 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT_MSB 4
3896 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT register field. */
3897 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT_WIDTH 5
3898 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT register field value. */
3899 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT_SET_MSK 0x0000001f
3900 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT register field value. */
3901 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT_CLR_MSK 0xffffffe0
3902 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT register field. */
3903 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT_RESET 0x0
3904 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT field value from a register. */
3905 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
3906 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT register field value suitable for setting the register. */
3907 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
3908 
3909 #ifndef __ASSEMBLY__
3910 /*
3911  * WARNING: The C register and register group struct declarations are provided for
3912  * convenience and illustrative purposes. They should, however, be used with
3913  * caution as the C language standard provides no guarantees about the alignment or
3914  * atomicity of device memory accesses. The recommended practice for coding device
3915  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3916  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3917  * alt_write_dword() functions for 64 bit registers.
3918  *
3919  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC.
3920  */
3921 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_s
3922 {
3923  volatile uint32_t INTEVENT : 5; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT */
3924  uint32_t : 27; /* *UNDEFINED* */
3925 };
3926 
3927 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC. */
3928 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_t;
3929 #endif /* __ASSEMBLY__ */
3930 
3931 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC register. */
3932 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_RESET 0x00000000
3933 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC register from the beginning of the component. */
3934 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_OFST 0x174
3935 
3936 /*
3937  * Register : probe_soc2fpga_main_Probe_Counters_3_AlarmMode
3938  *
3939  * Register Layout
3940  *
3941  * Bits | Access | Reset | Description
3942  * :-------|:-------|:--------|:---------------------------------------------------------------------------------------------
3943  * [1:0] | RW | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_COUNTERS_3_ALARMMODE
3944  * [31:2] | ??? | Unknown | *UNDEFINED*
3945  *
3946  */
3947 /*
3948  * Field : COUNTERS_3_ALARMMODE
3949  *
3950  * Register AlarmMode is a 2-bit register that is present when parameter
3951  * statisticsCounterAlarm is set to True. The register defines the statistics-alarm
3952  * behavior of the counter.
3953  *
3954  * Field Access Macros:
3955  *
3956  */
3957 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_COUNTERS_3_ALARMMODE register field. */
3958 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_COUNTERS_3_ALARMMODE_LSB 0
3959 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_COUNTERS_3_ALARMMODE register field. */
3960 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_COUNTERS_3_ALARMMODE_MSB 1
3961 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_COUNTERS_3_ALARMMODE register field. */
3962 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_COUNTERS_3_ALARMMODE_WIDTH 2
3963 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_COUNTERS_3_ALARMMODE register field value. */
3964 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_COUNTERS_3_ALARMMODE_SET_MSK 0x00000003
3965 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_COUNTERS_3_ALARMMODE register field value. */
3966 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_COUNTERS_3_ALARMMODE_CLR_MSK 0xfffffffc
3967 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_COUNTERS_3_ALARMMODE register field. */
3968 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_COUNTERS_3_ALARMMODE_RESET 0x0
3969 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_COUNTERS_3_ALARMMODE field value from a register. */
3970 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_COUNTERS_3_ALARMMODE_GET(value) (((value) & 0x00000003) >> 0)
3971 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_COUNTERS_3_ALARMMODE register field value suitable for setting the register. */
3972 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_COUNTERS_3_ALARMMODE_SET(value) (((value) << 0) & 0x00000003)
3973 
3974 #ifndef __ASSEMBLY__
3975 /*
3976  * WARNING: The C register and register group struct declarations are provided for
3977  * convenience and illustrative purposes. They should, however, be used with
3978  * caution as the C language standard provides no guarantees about the alignment or
3979  * atomicity of device memory accesses. The recommended practice for coding device
3980  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3981  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3982  * alt_write_dword() functions for 64 bit registers.
3983  *
3984  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE.
3985  */
3986 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_s
3987 {
3988  volatile uint32_t COUNTERS_3_ALARMMODE : 2; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_COUNTERS_3_ALARMMODE */
3989  uint32_t : 30; /* *UNDEFINED* */
3990 };
3991 
3992 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE. */
3993 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_t;
3994 #endif /* __ASSEMBLY__ */
3995 
3996 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE register. */
3997 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_RESET 0x00000000
3998 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE register from the beginning of the component. */
3999 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_OFST 0x178
4000 
4001 /*
4002  * Register : probe_soc2fpga_main_Probe_Counters_3_Val
4003  *
4004  * Register Layout
4005  *
4006  * Bits | Access | Reset | Description
4007  * :--------|:-------|:--------|:---------------------------------------------------------------------------------
4008  * [15:0] | R | 0x0 | ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL
4009  * [31:16] | ??? | Unknown | *UNDEFINED*
4010  *
4011  */
4012 /*
4013  * Field : COUNTERS_3_VAL
4014  *
4015  * Register Val is a read-only register that is always present. The register
4016  * containsthe statistics counter value either pending StatAlarm output, or when
4017  * statisticscollection is suspended subsequent to triggers or signal statSuspend.
4018  *
4019  * Field Access Macros:
4020  *
4021  */
4022 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL register field. */
4023 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL_LSB 0
4024 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL register field. */
4025 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL_MSB 15
4026 /* The width in bits of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL register field. */
4027 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL_WIDTH 16
4028 /* The mask used to set the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL register field value. */
4029 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL_SET_MSK 0x0000ffff
4030 /* The mask used to clear the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL register field value. */
4031 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL_CLR_MSK 0xffff0000
4032 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL register field. */
4033 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL_RESET 0x0
4034 /* Extracts the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL field value from a register. */
4035 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
4036 /* Produces a ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL register field value suitable for setting the register. */
4037 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL_SET(value) (((value) << 0) & 0x0000ffff)
4038 
4039 #ifndef __ASSEMBLY__
4040 /*
4041  * WARNING: The C register and register group struct declarations are provided for
4042  * convenience and illustrative purposes. They should, however, be used with
4043  * caution as the C language standard provides no guarantees about the alignment or
4044  * atomicity of device memory accesses. The recommended practice for coding device
4045  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4046  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4047  * alt_write_dword() functions for 64 bit registers.
4048  *
4049  * The struct declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL.
4050  */
4051 struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_s
4052 {
4053  const volatile uint32_t COUNTERS_3_VAL : 16; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL */
4054  uint32_t : 16; /* *UNDEFINED* */
4055 };
4056 
4057 /* The typedef declaration for register ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL. */
4058 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_s ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_t;
4059 #endif /* __ASSEMBLY__ */
4060 
4061 /* The reset value of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL register. */
4062 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_RESET 0x00000000
4063 /* The byte offset of the ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL register from the beginning of the component. */
4064 #define ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_OFST 0x17c
4065 
4066 #ifndef __ASSEMBLY__
4067 /*
4068  * WARNING: The C register and register group struct declarations are provided for
4069  * convenience and illustrative purposes. They should, however, be used with
4070  * caution as the C language standard provides no guarantees about the alignment or
4071  * atomicity of device memory accesses. The recommended practice for coding device
4072  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4073  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4074  * alt_write_dword() functions for 64 bit registers.
4075  *
4076  * The struct declaration for register group ALT_NOC_CCU_H2F_MAIN_PRB.
4077  */
4078 struct ALT_NOC_CCU_H2F_MAIN_PRB_s
4079 {
4080  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID_t probe_soc2fpga_main_Probe_Id_CoreId; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID */
4081  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID_t probe_soc2fpga_main_Probe_Id_RevisionId; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID */
4082  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL_t probe_soc2fpga_main_Probe_MainCtl; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL */
4083  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL_t probe_soc2fpga_main_Probe_CfgCtl; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL */
4084  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL_t probe_soc2fpga_main_Probe_TracePortSel; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL */
4085  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT_t probe_soc2fpga_main_Probe_FilterLut; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT */
4086  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN_t probe_soc2fpga_main_Probe_TraceAlarmEn; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN */
4087  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS_t probe_soc2fpga_main_Probe_TraceAlarmStatus; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS */
4088  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR_t probe_soc2fpga_main_Probe_TraceAlarmClr; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR */
4089  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD_t probe_soc2fpga_main_Probe_StatPeriod; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD */
4090  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO_t probe_soc2fpga_main_Probe_StatGo; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO */
4091  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN_t probe_soc2fpga_main_Probe_StatAlarmMin; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN */
4092  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX_t probe_soc2fpga_main_Probe_StatAlarmMax; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX */
4093  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS_t probe_soc2fpga_main_Probe_StatAlarmStatus; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS */
4094  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR_t probe_soc2fpga_main_Probe_StatAlarmClr; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR */
4095  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN_t probe_soc2fpga_main_Probe_StatAlarmEn; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN */
4096  volatile uint32_t _pad_0x40_0x43; /* *UNDEFINED* */
4097  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_t probe_soc2fpga_main_Probe_Filters_0_RouteIdBase; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE */
4098  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_t probe_soc2fpga_main_Probe_Filters_0_RouteIdMask; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK */
4099  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_t probe_soc2fpga_main_Probe_Filters_0_AddrBase_Low; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW */
4100  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_t probe_soc2fpga_main_Probe_Filters_0_AddrBase_High; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH */
4101  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE_t probe_soc2fpga_main_Probe_Filters_0_WindowSize; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE */
4102  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE_t probe_soc2fpga_main_Probe_Filters_0_SecurityBase; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE */
4103  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK_t probe_soc2fpga_main_Probe_Filters_0_SecurityMask; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK */
4104  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE_t probe_soc2fpga_main_Probe_Filters_0_Opcode; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE */
4105  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS_t probe_soc2fpga_main_Probe_Filters_0_Status; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS */
4106  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH_t probe_soc2fpga_main_Probe_Filters_0_Length; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH */
4107  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY_t probe_soc2fpga_main_Probe_Filters_0_Urgency; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY */
4108  volatile uint32_t _pad_0x70_0x7f[4]; /* *UNDEFINED* */
4109  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_t probe_soc2fpga_main_Probe_Filters_1_RouteIdBase; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE */
4110  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_t probe_soc2fpga_main_Probe_Filters_1_RouteIdMask; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK */
4111  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_t probe_soc2fpga_main_Probe_Filters_1_AddrBase_Low; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW */
4112  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_t probe_soc2fpga_main_Probe_Filters_1_AddrBase_High; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH */
4113  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE_t probe_soc2fpga_main_Probe_Filters_1_WindowSize; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE */
4114  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE_t probe_soc2fpga_main_Probe_Filters_1_SecurityBase; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE */
4115  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK_t probe_soc2fpga_main_Probe_Filters_1_SecurityMask; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK */
4116  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE_t probe_soc2fpga_main_Probe_Filters_1_Opcode; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE */
4117  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS_t probe_soc2fpga_main_Probe_Filters_1_Status; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS */
4118  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH_t probe_soc2fpga_main_Probe_Filters_1_Length; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH */
4119  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY_t probe_soc2fpga_main_Probe_Filters_1_Urgency; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY */
4120  volatile uint32_t _pad_0xac_0x133[34]; /* *UNDEFINED* */
4121  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL_t probe_soc2fpga_main_Probe_Counters_0_PortSel; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL */
4122  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC_t probe_soc2fpga_main_Probe_Counters_0_Src; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC */
4123  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE_t probe_soc2fpga_main_Probe_Counters_0_AlarmMode; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE */
4124  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL_t probe_soc2fpga_main_Probe_Counters_0_Val; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL */
4125  volatile uint32_t _pad_0x144_0x147; /* *UNDEFINED* */
4126  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL_t probe_soc2fpga_main_Probe_Counters_1_PortSel; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL */
4127  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC_t probe_soc2fpga_main_Probe_Counters_1_Src; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC */
4128  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE_t probe_soc2fpga_main_Probe_Counters_1_AlarmMode; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE */
4129  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL_t probe_soc2fpga_main_Probe_Counters_1_Val; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL */
4130  volatile uint32_t _pad_0x158_0x15b; /* *UNDEFINED* */
4131  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL_t probe_soc2fpga_main_Probe_Counters_2_PortSel; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL */
4132  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC_t probe_soc2fpga_main_Probe_Counters_2_Src; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC */
4133  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE_t probe_soc2fpga_main_Probe_Counters_2_AlarmMode; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE */
4134  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL_t probe_soc2fpga_main_Probe_Counters_2_Val; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL */
4135  volatile uint32_t _pad_0x16c_0x16f; /* *UNDEFINED* */
4136  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL_t probe_soc2fpga_main_Probe_Counters_3_PortSel; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL */
4137  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC_t probe_soc2fpga_main_Probe_Counters_3_Src; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC */
4138  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE_t probe_soc2fpga_main_Probe_Counters_3_AlarmMode; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE */
4139  volatile ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL_t probe_soc2fpga_main_Probe_Counters_3_Val; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL */
4140  volatile uint32_t _pad_0x180_0x400[160]; /* *UNDEFINED* */
4141 };
4142 
4143 /* The typedef declaration for register group ALT_NOC_CCU_H2F_MAIN_PRB. */
4144 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_s ALT_NOC_CCU_H2F_MAIN_PRB_t;
4145 /* The struct declaration for the raw register contents of register group ALT_NOC_CCU_H2F_MAIN_PRB. */
4146 struct ALT_NOC_CCU_H2F_MAIN_PRB_raw_s
4147 {
4148  volatile uint32_t probe_soc2fpga_main_Probe_Id_CoreId; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_COREID */
4149  volatile uint32_t probe_soc2fpga_main_Probe_Id_RevisionId; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_ID_REVISIONID */
4150  volatile uint32_t probe_soc2fpga_main_Probe_MainCtl; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_MAINCTL */
4151  volatile uint32_t probe_soc2fpga_main_Probe_CfgCtl; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_CFGCTL */
4152  volatile uint32_t probe_soc2fpga_main_Probe_TracePortSel; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEPORTSEL */
4153  volatile uint32_t probe_soc2fpga_main_Probe_FilterLut; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERLUT */
4154  volatile uint32_t probe_soc2fpga_main_Probe_TraceAlarmEn; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMEN */
4155  volatile uint32_t probe_soc2fpga_main_Probe_TraceAlarmStatus; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMSTATUS */
4156  volatile uint32_t probe_soc2fpga_main_Probe_TraceAlarmClr; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_TRACEALARMCLR */
4157  volatile uint32_t probe_soc2fpga_main_Probe_StatPeriod; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATPERIOD */
4158  volatile uint32_t probe_soc2fpga_main_Probe_StatGo; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATGO */
4159  volatile uint32_t probe_soc2fpga_main_Probe_StatAlarmMin; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMIN */
4160  volatile uint32_t probe_soc2fpga_main_Probe_StatAlarmMax; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMMAX */
4161  volatile uint32_t probe_soc2fpga_main_Probe_StatAlarmStatus; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMSTATUS */
4162  volatile uint32_t probe_soc2fpga_main_Probe_StatAlarmClr; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMCLR */
4163  volatile uint32_t probe_soc2fpga_main_Probe_StatAlarmEn; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_STATALARMEN */
4164  volatile uint32_t _pad_0x40_0x43; /* *UNDEFINED* */
4165  volatile uint32_t probe_soc2fpga_main_Probe_Filters_0_RouteIdBase; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDBASE */
4166  volatile uint32_t probe_soc2fpga_main_Probe_Filters_0_RouteIdMask; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ROUTEIDMASK */
4167  volatile uint32_t probe_soc2fpga_main_Probe_Filters_0_AddrBase_Low; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW */
4168  volatile uint32_t probe_soc2fpga_main_Probe_Filters_0_AddrBase_High; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH */
4169  volatile uint32_t probe_soc2fpga_main_Probe_Filters_0_WindowSize; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_WINDOWSIZE */
4170  volatile uint32_t probe_soc2fpga_main_Probe_Filters_0_SecurityBase; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYBASE */
4171  volatile uint32_t probe_soc2fpga_main_Probe_Filters_0_SecurityMask; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_SECURITYMASK */
4172  volatile uint32_t probe_soc2fpga_main_Probe_Filters_0_Opcode; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_OPCODE */
4173  volatile uint32_t probe_soc2fpga_main_Probe_Filters_0_Status; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_STATUS */
4174  volatile uint32_t probe_soc2fpga_main_Probe_Filters_0_Length; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_LENGTH */
4175  volatile uint32_t probe_soc2fpga_main_Probe_Filters_0_Urgency; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_0_URGENCY */
4176  volatile uint32_t _pad_0x70_0x7f[4]; /* *UNDEFINED* */
4177  volatile uint32_t probe_soc2fpga_main_Probe_Filters_1_RouteIdBase; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDBASE */
4178  volatile uint32_t probe_soc2fpga_main_Probe_Filters_1_RouteIdMask; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ROUTEIDMASK */
4179  volatile uint32_t probe_soc2fpga_main_Probe_Filters_1_AddrBase_Low; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW */
4180  volatile uint32_t probe_soc2fpga_main_Probe_Filters_1_AddrBase_High; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH */
4181  volatile uint32_t probe_soc2fpga_main_Probe_Filters_1_WindowSize; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_WINDOWSIZE */
4182  volatile uint32_t probe_soc2fpga_main_Probe_Filters_1_SecurityBase; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYBASE */
4183  volatile uint32_t probe_soc2fpga_main_Probe_Filters_1_SecurityMask; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_SECURITYMASK */
4184  volatile uint32_t probe_soc2fpga_main_Probe_Filters_1_Opcode; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_OPCODE */
4185  volatile uint32_t probe_soc2fpga_main_Probe_Filters_1_Status; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_STATUS */
4186  volatile uint32_t probe_soc2fpga_main_Probe_Filters_1_Length; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_LENGTH */
4187  volatile uint32_t probe_soc2fpga_main_Probe_Filters_1_Urgency; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_FILTERS_1_URGENCY */
4188  volatile uint32_t _pad_0xac_0x133[34]; /* *UNDEFINED* */
4189  volatile uint32_t probe_soc2fpga_main_Probe_Counters_0_PortSel; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_PORTSEL */
4190  volatile uint32_t probe_soc2fpga_main_Probe_Counters_0_Src; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_SRC */
4191  volatile uint32_t probe_soc2fpga_main_Probe_Counters_0_AlarmMode; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_ALARMMODE */
4192  volatile uint32_t probe_soc2fpga_main_Probe_Counters_0_Val; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_0_VAL */
4193  volatile uint32_t _pad_0x144_0x147; /* *UNDEFINED* */
4194  volatile uint32_t probe_soc2fpga_main_Probe_Counters_1_PortSel; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_PORTSEL */
4195  volatile uint32_t probe_soc2fpga_main_Probe_Counters_1_Src; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_SRC */
4196  volatile uint32_t probe_soc2fpga_main_Probe_Counters_1_AlarmMode; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_ALARMMODE */
4197  volatile uint32_t probe_soc2fpga_main_Probe_Counters_1_Val; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_1_VAL */
4198  volatile uint32_t _pad_0x158_0x15b; /* *UNDEFINED* */
4199  volatile uint32_t probe_soc2fpga_main_Probe_Counters_2_PortSel; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_PORTSEL */
4200  volatile uint32_t probe_soc2fpga_main_Probe_Counters_2_Src; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_SRC */
4201  volatile uint32_t probe_soc2fpga_main_Probe_Counters_2_AlarmMode; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_ALARMMODE */
4202  volatile uint32_t probe_soc2fpga_main_Probe_Counters_2_Val; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_2_VAL */
4203  volatile uint32_t _pad_0x16c_0x16f; /* *UNDEFINED* */
4204  volatile uint32_t probe_soc2fpga_main_Probe_Counters_3_PortSel; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_PORTSEL */
4205  volatile uint32_t probe_soc2fpga_main_Probe_Counters_3_Src; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_SRC */
4206  volatile uint32_t probe_soc2fpga_main_Probe_Counters_3_AlarmMode; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_ALARMMODE */
4207  volatile uint32_t probe_soc2fpga_main_Probe_Counters_3_Val; /* ALT_NOC_CCU_H2F_MAIN_PRB_PROBE_SOC2FPGA_MAIN_PROBE_COUNTERS_3_VAL */
4208  volatile uint32_t _pad_0x180_0x400[160]; /* *UNDEFINED* */
4209 };
4210 
4211 /* The typedef declaration for the raw register contents of register group ALT_NOC_CCU_H2F_MAIN_PRB. */
4212 typedef struct ALT_NOC_CCU_H2F_MAIN_PRB_raw_s ALT_NOC_CCU_H2F_MAIN_PRB_raw_t;
4213 #endif /* __ASSEMBLY__ */
4214 
4215 
4216 #ifdef __cplusplus
4217 }
4218 #endif /* __cplusplus */
4219 #endif /* __ALT_SOCAL_NOC_CCU_H2F_MAIN_PRB_H__ */
4220