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alt_a53_timers.h
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32 
33 /*
34  * $Id: //acds/main/embedded/ip/hps/armv8/hwlib/include/alt_a53_timers.h#1 $
35  */
36 
37 #ifndef ALT_A53_CPU_TIMER_H_
38 #define ALT_A53_CPU_TIMER_H_
39 
40 #include "socal/hps.h"
41 
42 /*
43  *
44  Description:
45  This is the main header file used for access to Cortex A53 Generic Timer Registers
46  for both the AArch 32 and AArch64 State
47  *
48  */
49 
50 /*
51  Timer Access
52 
53  EL1 Physical Timer (Secure/NonSecure)
54  Accesible from EL1 modes, when permitted.
55  CNTkCTL.EL0PTEN determines whether the regs are accessiable from EL0.
56 
57  For Access from EL3 (Monitor Mode) the Value of EL3.NS determines weather to access Secure or Non-Secure Registers
58  *
59  */
60 
61 /********************************************/
62 /******** A53 CPU Timer Defines ***********/
63 /********************************************/
64 
65 /*
66  *
67 #defines for Generic Timer Control Register Bitfields
68  *
69  */
70 
71 
72 #define VALUE_SET (1)
73 #define VALUE_CLEAR (0)
74 
75 /* Hypervisor Control Register */
76 #define CNT_HYPCTL_EL1PCTEN (1<<0) /*Controls Physical Counter Accessability from NonSec EL1 and EL0.*/
77 #define CNT_HYPCTL_EL1PCEN (1<<1) /*Controls whether the Physcial Timer Registers are accessible from NonSec EL1 and EL0*/
78 #define CNT_HYPCTL_ENVTEN (1<<2) /*Enables Event Stream From Corresponding Counter*/
79 #define CNT_HYPCTL_EVNTDIR (1<<3) /*Controls Edge on Evenet*/
80 #define CNT_HYPCTL_EVNTI (0x0000F0) /*Bit Select fo Event Stream Generation*/
81 
82 /*Kernal Control Register*/
83 #define CNT_KNLCTL_EL0PCTEN (1<<0) /*Controls whether the physical counter and freq reg is accessible from EL0 Mode*/
84 #define CNT_KNLCTL_EL0VCTEN (1<<1) /*Controls whether the virutual counter and frequency Count are Available From EL0*/
85 #define CNT_KNLCTL_EVNTEN (1<<2) /*Enable/Disable Event Stream*/
86 #define CNT_KNLCTL_EVETDIR (1<<3) /*Controls Edge On Event Generation*/
87 #define CNT_KNLCTL_EVNTI (0x000000F0) /*Bit Select for Event Stream Generation*/
88 #define CNT_KNLCTL_EL0VTEN (1<<8) /*Contols whether the virutal timer regs are accessible from EL0*/
89 #define CNT_KNLCTL_EL0PTEN (1<<9) /*Control Wether the Physical Timer Regs are accessible from EL0
90 */
91 /*Timer Control Registers*/
92 #define CNT_CTL_ENABLE (1<<0) /*Timer Interrupt Enable*/
93 #define CNT_CTL_IMASK (1<<1) /*Timer Interrupt Mask*/
94 #define CNT_CTL_ISTATUS (1<<2) /*Timer Enable Disable*/
95 
96 /*Conter Timer ID Registers*/
97 #define CNT_FRAME7 (0xF0000000)
98 #define CNT_FRAME6 (0x0F000000)
99 #define CNT_FRAME5 (0x00F00000)
100 #define CNT_FRAME4 (0x000F0000)
101 #define CNT_FRAME3 (0x0000F000)
102 #define CNT_FRAME2 (0x00000F00)
103 #define CNT_FRAME1 (0x000000F0)
104 #define CNT_FRAME0 (0x0000000F)
105 
106 #define CNT_DBGH (1<<1) /*Controls if Counter is Halted or Not in Debug Mode*/
107 
108 /* Non Secure Access Register*/
109 #define CNT_NS0 (1<<0) /*Control Weather Frames CNTBaseN and CNTEL0BaseN are accessible by Non-Sec Accesses*/
110 #define CNT_NS1 (1<<1)
111 #define CNT_NS1 (1<<1)
112 #define CNT_NS2 (1<<2)
113 #define CNT_NS3 (1<<3)
114 #define CNT_NS4 (1<<4)
115 #define CNT_NS5 (1<<5)
116 #define CNT_NS6 (1<<6)
117 #define CNT_NS7 (1<<7)
118 
119 /*Counter Control Register*/
120 #define CNT_HDBG (1<<1) /*Halt On Debug*/
121 
122 
123 /********************************************/
124 /**** A53 CPU Timer Function Prototypes******/
125 /********************************************/
126 uint32_t alt_a53_get_gentimer_nsel1control(void);
127 void alt_a53_set_gentimer_nsel1control(uint32_t val);
128 int32_t alt_a53_get_gentimer_nsel1timervalue(void);
129 void alt_a53_set_gentimer_nsel1timervalue(int32_t val);
130 uint64_t alt_a53_get_gentimer_nsel1comparevalue(void);
131 void alt_a53_set_gentimer_nsel1comparevalue(uint64_t val);
132 
133 uint32_t alt_a53_get_gentimer_sel1control(void);
134 void alt_a53_set_gentimer_sel1control(uint32_t val);
135 int32_t alt_a53_get_gentimer_sel1timervalue(void);
136 void alt_a53_set_gentimer_sel1timervalue(int32_t val);
137 uint64_t alt_a53_get_gentimer_sel1comparevalue(void);
138 void alt_a53_set_gentimer_sel1comparevalue(uint64_t val);
139 
140 
141 uint32_t alt_a53_get_gentimer_nsel2control(void);
142 void alt_a53_set_gentimer_nsel2control(uint32_t val);
143 int32_t alt_a53_get_gentimer_nsel2timervalue(void);
144 void alt_a53_set_gentimer_nsel2timervalue(int32_t val);
145 uint64_t alt_a53_get_gentimer_nsel2comparevalue(void);
146 void alt_a53_set_gentimer_nsel2comparevalue(uint64_t val);
147 
148 
149 uint32_t alt_a53_get_gentimer_virtcontrol(void);
150 void alt_a53_set_gentimer_virtcontrol(uint32_t val);
151 int32_t alt_a53_get_gentimer_virttimervalue(void);
152 void alt_a53_set_gentimer_virttimervalue(int32_t val);
153 uint64_t alt_a53_get_gentimer_virtcomparevalue(void);
154 void alt_a53_set_gentimer_virtcomparevalue(int64_t val);
155 
156 
157 uint32_t alt_a53_get_cntrtimerkernel_control(void);
158 void alt_a53_set_cntrtimerkernel_control(int32_t val);
159 
160 uint32_t alt_a53_get_cntrtimer_freq(void);
161 void alt_a53_set_cntrtimer_freq(int32_t val);
162 
163 uint32_t alt_a53_get_cntrtimer_phycnt(void);
164 uint32_t alt_a53_get_cntrtimer_vircnt(void);
165 
166 void alt_a53_isb(void);
167 
168 #endif /* End of ALT_A53_CPU_TIMER_H_ */