Hardware Libraries  20.1
Arria 10 SoC Abstration Layer
 All Groups
alt_rstmgr.h
1 /***********************************************************************************
2 * *
3 * Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
4 * *
5 * Redistribution and use in source and binary forms, with or without *
6 * modification, are permitted provided that the following conditions are met: *
7 * *
8 * 1. Redistributions of source code must retain the above copyright notice, *
9 * this list of conditions and the following disclaimer. *
10 * *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, *
12 * this list of conditions and the following disclaimer in the documentation *
13 * and/or other materials provided with the distribution. *
14 * *
15 * 3. Neither the name of the copyright holder nor the names of its contributors *
16 * may be used to endorse or promote products derived from this software without *
17 * specific prior written permission. *
18 * *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
29 * POSSIBILITY OF SUCH DAMAGE. *
30 * *
31 ***********************************************************************************/
32 
33 /* Altera - ALT_RSTMGR */
34 
35 #ifndef __ALT_SOCAL_RSTMGR_H__
36 #define __ALT_SOCAL_RSTMGR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_RSTMGR
50  *
51  */
52 /*
53  * Register : Status Register - stat
54  *
55  * The STAT register contains bits that indicate the reset source. For reset
56  * sources, a field is 1 if its associated reset requester caused the reset.
57  *
58  * Software clears bits by writing them with a value of 1. Writes to bits with a
59  * value of 0 are ignored.
60  *
61  * After a cold reset is complete, all bits are reset to their reset value except
62  * for the bit(s) that indicate the source of the cold reset. If multiple cold
63  * reset requests overlap with each other, the source de-asserts the request last
64  * will be logged. The other reset request source(s) de-assert the request in the
65  * same cycle will also be logged, the rest of the fields are reset to default
66  * value of 0.
67  *
68  * After a warm reset is complete, the bit(s) that indicate the source of the warm
69  * reset are set to 1. A warm reset doesn't clear any of the bits in the STAT
70  * register; these bits must be cleared by software writing the STAT register.
71  *
72  * Register Layout
73  *
74  * Bits | Access | Reset | Description
75  * :--------|:-------|:------|:------------------------------------------
76  * [0] | RW | 0x0 | HPS Power-On Voltage Detector Cold Reset
77  * [1] | RW | 0x0 | Power-On FPGA Voltage Detector Cold Reset
78  * [2] | RW | 0x0 | nPOR Pin Cold Reset
79  * [3] | RW | 0x0 | FPGA Core Cold Reset
80  * [4] | RW | 0x0 | CONFIG_IO Cold Reset
81  * [5] | RW | 0x0 | Software Cold Reset
82  * [7:6] | ??? | 0x0 | *UNDEFINED*
83  * [8] | RW | 0x0 | nRST Pin Warm Reset
84  * [9] | RW | 0x0 | FPGA Core Warm Reset
85  * [10] | RW | 0x0 | Software Warm Reset
86  * [11] | RW | 0x0 | MPU Watchdog 0 Warm Reset
87  * [12] | RW | 0x0 | MPU Watchdog 1 Warm Reset
88  * [13] | RW | 0x0 | L4 Watchdog 0 Warm Reset
89  * [14] | RW | 0x0 | L4 Watchdog 1 Warm Reset
90  * [15] | ??? | 0x0 | *UNDEFINED*
91  * [16] | RW | 0x0 | FPGA Core Debug Reset
92  * [17] | RW | 0x0 | DAP Debug Reset
93  * [31:18] | ??? | 0x0 | *UNDEFINED*
94  *
95  */
96 /*
97  * Field : HPS Power-On Voltage Detector Cold Reset - porhpsvoltrst
98  *
99  * Built-in HPS POR voltage detector triggered a cold reset. Security Manager
100  * brought Reset Manager out of POR Reset.
101  *
102  * Field Access Macros:
103  *
104  */
105 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_PORHPSVOLTRST register field. */
106 #define ALT_RSTMGR_STAT_PORHPSVOLTRST_LSB 0
107 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_PORHPSVOLTRST register field. */
108 #define ALT_RSTMGR_STAT_PORHPSVOLTRST_MSB 0
109 /* The width in bits of the ALT_RSTMGR_STAT_PORHPSVOLTRST register field. */
110 #define ALT_RSTMGR_STAT_PORHPSVOLTRST_WIDTH 1
111 /* The mask used to set the ALT_RSTMGR_STAT_PORHPSVOLTRST register field value. */
112 #define ALT_RSTMGR_STAT_PORHPSVOLTRST_SET_MSK 0x00000001
113 /* The mask used to clear the ALT_RSTMGR_STAT_PORHPSVOLTRST register field value. */
114 #define ALT_RSTMGR_STAT_PORHPSVOLTRST_CLR_MSK 0xfffffffe
115 /* The reset value of the ALT_RSTMGR_STAT_PORHPSVOLTRST register field. */
116 #define ALT_RSTMGR_STAT_PORHPSVOLTRST_RESET 0x0
117 /* Extracts the ALT_RSTMGR_STAT_PORHPSVOLTRST field value from a register. */
118 #define ALT_RSTMGR_STAT_PORHPSVOLTRST_GET(value) (((value) & 0x00000001) >> 0)
119 /* Produces a ALT_RSTMGR_STAT_PORHPSVOLTRST register field value suitable for setting the register. */
120 #define ALT_RSTMGR_STAT_PORHPSVOLTRST_SET(value) (((value) << 0) & 0x00000001)
121 
122 /*
123  * Field : Power-On FPGA Voltage Detector Cold Reset - porfpgavoltrst
124  *
125  * Built-in FPGA POR voltage detector triggered a cold reset. Security Manager
126  * brought Reset Manager out of POR Reset.
127  *
128  * Field Access Macros:
129  *
130  */
131 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_PORFPGAVOLTRST register field. */
132 #define ALT_RSTMGR_STAT_PORFPGAVOLTRST_LSB 1
133 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_PORFPGAVOLTRST register field. */
134 #define ALT_RSTMGR_STAT_PORFPGAVOLTRST_MSB 1
135 /* The width in bits of the ALT_RSTMGR_STAT_PORFPGAVOLTRST register field. */
136 #define ALT_RSTMGR_STAT_PORFPGAVOLTRST_WIDTH 1
137 /* The mask used to set the ALT_RSTMGR_STAT_PORFPGAVOLTRST register field value. */
138 #define ALT_RSTMGR_STAT_PORFPGAVOLTRST_SET_MSK 0x00000002
139 /* The mask used to clear the ALT_RSTMGR_STAT_PORFPGAVOLTRST register field value. */
140 #define ALT_RSTMGR_STAT_PORFPGAVOLTRST_CLR_MSK 0xfffffffd
141 /* The reset value of the ALT_RSTMGR_STAT_PORFPGAVOLTRST register field. */
142 #define ALT_RSTMGR_STAT_PORFPGAVOLTRST_RESET 0x0
143 /* Extracts the ALT_RSTMGR_STAT_PORFPGAVOLTRST field value from a register. */
144 #define ALT_RSTMGR_STAT_PORFPGAVOLTRST_GET(value) (((value) & 0x00000002) >> 1)
145 /* Produces a ALT_RSTMGR_STAT_PORFPGAVOLTRST register field value suitable for setting the register. */
146 #define ALT_RSTMGR_STAT_PORFPGAVOLTRST_SET(value) (((value) << 1) & 0x00000002)
147 
148 /*
149  * Field : nPOR Pin Cold Reset - nporpinrst
150  *
151  * nPOR pin triggered a cold reset (por_pin_req = 1)
152  *
153  * Field Access Macros:
154  *
155  */
156 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_NPORPINRST register field. */
157 #define ALT_RSTMGR_STAT_NPORPINRST_LSB 2
158 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_NPORPINRST register field. */
159 #define ALT_RSTMGR_STAT_NPORPINRST_MSB 2
160 /* The width in bits of the ALT_RSTMGR_STAT_NPORPINRST register field. */
161 #define ALT_RSTMGR_STAT_NPORPINRST_WIDTH 1
162 /* The mask used to set the ALT_RSTMGR_STAT_NPORPINRST register field value. */
163 #define ALT_RSTMGR_STAT_NPORPINRST_SET_MSK 0x00000004
164 /* The mask used to clear the ALT_RSTMGR_STAT_NPORPINRST register field value. */
165 #define ALT_RSTMGR_STAT_NPORPINRST_CLR_MSK 0xfffffffb
166 /* The reset value of the ALT_RSTMGR_STAT_NPORPINRST register field. */
167 #define ALT_RSTMGR_STAT_NPORPINRST_RESET 0x0
168 /* Extracts the ALT_RSTMGR_STAT_NPORPINRST field value from a register. */
169 #define ALT_RSTMGR_STAT_NPORPINRST_GET(value) (((value) & 0x00000004) >> 2)
170 /* Produces a ALT_RSTMGR_STAT_NPORPINRST register field value suitable for setting the register. */
171 #define ALT_RSTMGR_STAT_NPORPINRST_SET(value) (((value) << 2) & 0x00000004)
172 
173 /*
174  * Field : FPGA Core Cold Reset - fpgacoldrst
175  *
176  * FPGA core triggered a cold reset (f2s_cold_rst_req = 1)
177  *
178  * Field Access Macros:
179  *
180  */
181 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */
182 #define ALT_RSTMGR_STAT_FPGACOLDRST_LSB 3
183 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */
184 #define ALT_RSTMGR_STAT_FPGACOLDRST_MSB 3
185 /* The width in bits of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */
186 #define ALT_RSTMGR_STAT_FPGACOLDRST_WIDTH 1
187 /* The mask used to set the ALT_RSTMGR_STAT_FPGACOLDRST register field value. */
188 #define ALT_RSTMGR_STAT_FPGACOLDRST_SET_MSK 0x00000008
189 /* The mask used to clear the ALT_RSTMGR_STAT_FPGACOLDRST register field value. */
190 #define ALT_RSTMGR_STAT_FPGACOLDRST_CLR_MSK 0xfffffff7
191 /* The reset value of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */
192 #define ALT_RSTMGR_STAT_FPGACOLDRST_RESET 0x0
193 /* Extracts the ALT_RSTMGR_STAT_FPGACOLDRST field value from a register. */
194 #define ALT_RSTMGR_STAT_FPGACOLDRST_GET(value) (((value) & 0x00000008) >> 3)
195 /* Produces a ALT_RSTMGR_STAT_FPGACOLDRST register field value suitable for setting the register. */
196 #define ALT_RSTMGR_STAT_FPGACOLDRST_SET(value) (((value) << 3) & 0x00000008)
197 
198 /*
199  * Field : CONFIG_IO Cold Reset - configiocoldrst
200  *
201  * FPGA entered CONFIG_IO mode and a triggered a cold reset
202  *
203  * Field Access Macros:
204  *
205  */
206 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */
207 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_LSB 4
208 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */
209 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_MSB 4
210 /* The width in bits of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */
211 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_WIDTH 1
212 /* The mask used to set the ALT_RSTMGR_STAT_CFGIOCOLDRST register field value. */
213 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET_MSK 0x00000010
214 /* The mask used to clear the ALT_RSTMGR_STAT_CFGIOCOLDRST register field value. */
215 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_CLR_MSK 0xffffffef
216 /* The reset value of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */
217 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_RESET 0x0
218 /* Extracts the ALT_RSTMGR_STAT_CFGIOCOLDRST field value from a register. */
219 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_GET(value) (((value) & 0x00000010) >> 4)
220 /* Produces a ALT_RSTMGR_STAT_CFGIOCOLDRST register field value suitable for setting the register. */
221 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET(value) (((value) << 4) & 0x00000010)
222 
223 /*
224  * Field : Software Cold Reset - swcoldrst
225  *
226  * Software wrote CTRL.SWCOLDRSTREQ to 1 and triggered a cold reset.
227  *
228  * Field Access Macros:
229  *
230  */
231 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SWCOLDRST register field. */
232 #define ALT_RSTMGR_STAT_SWCOLDRST_LSB 5
233 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SWCOLDRST register field. */
234 #define ALT_RSTMGR_STAT_SWCOLDRST_MSB 5
235 /* The width in bits of the ALT_RSTMGR_STAT_SWCOLDRST register field. */
236 #define ALT_RSTMGR_STAT_SWCOLDRST_WIDTH 1
237 /* The mask used to set the ALT_RSTMGR_STAT_SWCOLDRST register field value. */
238 #define ALT_RSTMGR_STAT_SWCOLDRST_SET_MSK 0x00000020
239 /* The mask used to clear the ALT_RSTMGR_STAT_SWCOLDRST register field value. */
240 #define ALT_RSTMGR_STAT_SWCOLDRST_CLR_MSK 0xffffffdf
241 /* The reset value of the ALT_RSTMGR_STAT_SWCOLDRST register field. */
242 #define ALT_RSTMGR_STAT_SWCOLDRST_RESET 0x0
243 /* Extracts the ALT_RSTMGR_STAT_SWCOLDRST field value from a register. */
244 #define ALT_RSTMGR_STAT_SWCOLDRST_GET(value) (((value) & 0x00000020) >> 5)
245 /* Produces a ALT_RSTMGR_STAT_SWCOLDRST register field value suitable for setting the register. */
246 #define ALT_RSTMGR_STAT_SWCOLDRST_SET(value) (((value) << 5) & 0x00000020)
247 
248 /*
249  * Field : nRST Pin Warm Reset - nrstpinrst
250  *
251  * nRST pin triggered a hardware sequenced warm reset
252  *
253  * Field Access Macros:
254  *
255  */
256 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_NRSTPINRST register field. */
257 #define ALT_RSTMGR_STAT_NRSTPINRST_LSB 8
258 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_NRSTPINRST register field. */
259 #define ALT_RSTMGR_STAT_NRSTPINRST_MSB 8
260 /* The width in bits of the ALT_RSTMGR_STAT_NRSTPINRST register field. */
261 #define ALT_RSTMGR_STAT_NRSTPINRST_WIDTH 1
262 /* The mask used to set the ALT_RSTMGR_STAT_NRSTPINRST register field value. */
263 #define ALT_RSTMGR_STAT_NRSTPINRST_SET_MSK 0x00000100
264 /* The mask used to clear the ALT_RSTMGR_STAT_NRSTPINRST register field value. */
265 #define ALT_RSTMGR_STAT_NRSTPINRST_CLR_MSK 0xfffffeff
266 /* The reset value of the ALT_RSTMGR_STAT_NRSTPINRST register field. */
267 #define ALT_RSTMGR_STAT_NRSTPINRST_RESET 0x0
268 /* Extracts the ALT_RSTMGR_STAT_NRSTPINRST field value from a register. */
269 #define ALT_RSTMGR_STAT_NRSTPINRST_GET(value) (((value) & 0x00000100) >> 8)
270 /* Produces a ALT_RSTMGR_STAT_NRSTPINRST register field value suitable for setting the register. */
271 #define ALT_RSTMGR_STAT_NRSTPINRST_SET(value) (((value) << 8) & 0x00000100)
272 
273 /*
274  * Field : FPGA Core Warm Reset - fpgawarmrst
275  *
276  * FPGA core triggered a hardware sequenced warm reset
277  *
278  * Field Access Macros:
279  *
280  */
281 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */
282 #define ALT_RSTMGR_STAT_FPGAWARMRST_LSB 9
283 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */
284 #define ALT_RSTMGR_STAT_FPGAWARMRST_MSB 9
285 /* The width in bits of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */
286 #define ALT_RSTMGR_STAT_FPGAWARMRST_WIDTH 1
287 /* The mask used to set the ALT_RSTMGR_STAT_FPGAWARMRST register field value. */
288 #define ALT_RSTMGR_STAT_FPGAWARMRST_SET_MSK 0x00000200
289 /* The mask used to clear the ALT_RSTMGR_STAT_FPGAWARMRST register field value. */
290 #define ALT_RSTMGR_STAT_FPGAWARMRST_CLR_MSK 0xfffffdff
291 /* The reset value of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */
292 #define ALT_RSTMGR_STAT_FPGAWARMRST_RESET 0x0
293 /* Extracts the ALT_RSTMGR_STAT_FPGAWARMRST field value from a register. */
294 #define ALT_RSTMGR_STAT_FPGAWARMRST_GET(value) (((value) & 0x00000200) >> 9)
295 /* Produces a ALT_RSTMGR_STAT_FPGAWARMRST register field value suitable for setting the register. */
296 #define ALT_RSTMGR_STAT_FPGAWARMRST_SET(value) (((value) << 9) & 0x00000200)
297 
298 /*
299  * Field : Software Warm Reset - swwarmrst
300  *
301  * Software wrote CTRL.SWARMRSTREQ to 1 and triggered a hardware sequenced warm
302  * reset.
303  *
304  * Field Access Macros:
305  *
306  */
307 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SWWARMRST register field. */
308 #define ALT_RSTMGR_STAT_SWWARMRST_LSB 10
309 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SWWARMRST register field. */
310 #define ALT_RSTMGR_STAT_SWWARMRST_MSB 10
311 /* The width in bits of the ALT_RSTMGR_STAT_SWWARMRST register field. */
312 #define ALT_RSTMGR_STAT_SWWARMRST_WIDTH 1
313 /* The mask used to set the ALT_RSTMGR_STAT_SWWARMRST register field value. */
314 #define ALT_RSTMGR_STAT_SWWARMRST_SET_MSK 0x00000400
315 /* The mask used to clear the ALT_RSTMGR_STAT_SWWARMRST register field value. */
316 #define ALT_RSTMGR_STAT_SWWARMRST_CLR_MSK 0xfffffbff
317 /* The reset value of the ALT_RSTMGR_STAT_SWWARMRST register field. */
318 #define ALT_RSTMGR_STAT_SWWARMRST_RESET 0x0
319 /* Extracts the ALT_RSTMGR_STAT_SWWARMRST field value from a register. */
320 #define ALT_RSTMGR_STAT_SWWARMRST_GET(value) (((value) & 0x00000400) >> 10)
321 /* Produces a ALT_RSTMGR_STAT_SWWARMRST register field value suitable for setting the register. */
322 #define ALT_RSTMGR_STAT_SWWARMRST_SET(value) (((value) << 10) & 0x00000400)
323 
324 /*
325  * Field : MPU Watchdog 0 Warm Reset - mpuwd0rst
326  *
327  * MPU Watchdog 0 triggered a hardware sequenced warm reset
328  *
329  * Field Access Macros:
330  *
331  */
332 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPUWD0RST register field. */
333 #define ALT_RSTMGR_STAT_MPUWD0RST_LSB 11
334 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPUWD0RST register field. */
335 #define ALT_RSTMGR_STAT_MPUWD0RST_MSB 11
336 /* The width in bits of the ALT_RSTMGR_STAT_MPUWD0RST register field. */
337 #define ALT_RSTMGR_STAT_MPUWD0RST_WIDTH 1
338 /* The mask used to set the ALT_RSTMGR_STAT_MPUWD0RST register field value. */
339 #define ALT_RSTMGR_STAT_MPUWD0RST_SET_MSK 0x00000800
340 /* The mask used to clear the ALT_RSTMGR_STAT_MPUWD0RST register field value. */
341 #define ALT_RSTMGR_STAT_MPUWD0RST_CLR_MSK 0xfffff7ff
342 /* The reset value of the ALT_RSTMGR_STAT_MPUWD0RST register field. */
343 #define ALT_RSTMGR_STAT_MPUWD0RST_RESET 0x0
344 /* Extracts the ALT_RSTMGR_STAT_MPUWD0RST field value from a register. */
345 #define ALT_RSTMGR_STAT_MPUWD0RST_GET(value) (((value) & 0x00000800) >> 11)
346 /* Produces a ALT_RSTMGR_STAT_MPUWD0RST register field value suitable for setting the register. */
347 #define ALT_RSTMGR_STAT_MPUWD0RST_SET(value) (((value) << 11) & 0x00000800)
348 
349 /*
350  * Field : MPU Watchdog 1 Warm Reset - mpuwd1rst
351  *
352  * MPU Watchdog 1 triggered a hardware sequenced warm reset
353  *
354  * Field Access Macros:
355  *
356  */
357 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPUWD1RST register field. */
358 #define ALT_RSTMGR_STAT_MPUWD1RST_LSB 12
359 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPUWD1RST register field. */
360 #define ALT_RSTMGR_STAT_MPUWD1RST_MSB 12
361 /* The width in bits of the ALT_RSTMGR_STAT_MPUWD1RST register field. */
362 #define ALT_RSTMGR_STAT_MPUWD1RST_WIDTH 1
363 /* The mask used to set the ALT_RSTMGR_STAT_MPUWD1RST register field value. */
364 #define ALT_RSTMGR_STAT_MPUWD1RST_SET_MSK 0x00001000
365 /* The mask used to clear the ALT_RSTMGR_STAT_MPUWD1RST register field value. */
366 #define ALT_RSTMGR_STAT_MPUWD1RST_CLR_MSK 0xffffefff
367 /* The reset value of the ALT_RSTMGR_STAT_MPUWD1RST register field. */
368 #define ALT_RSTMGR_STAT_MPUWD1RST_RESET 0x0
369 /* Extracts the ALT_RSTMGR_STAT_MPUWD1RST field value from a register. */
370 #define ALT_RSTMGR_STAT_MPUWD1RST_GET(value) (((value) & 0x00001000) >> 12)
371 /* Produces a ALT_RSTMGR_STAT_MPUWD1RST register field value suitable for setting the register. */
372 #define ALT_RSTMGR_STAT_MPUWD1RST_SET(value) (((value) << 12) & 0x00001000)
373 
374 /*
375  * Field : L4 Watchdog 0 Warm Reset - l4wd0rst
376  *
377  * L4 Watchdog 0 triggered a hardware sequenced warm reset
378  *
379  * Field Access Macros:
380  *
381  */
382 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field. */
383 #define ALT_RSTMGR_STAT_L4WD0RST_LSB 13
384 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field. */
385 #define ALT_RSTMGR_STAT_L4WD0RST_MSB 13
386 /* The width in bits of the ALT_RSTMGR_STAT_L4WD0RST register field. */
387 #define ALT_RSTMGR_STAT_L4WD0RST_WIDTH 1
388 /* The mask used to set the ALT_RSTMGR_STAT_L4WD0RST register field value. */
389 #define ALT_RSTMGR_STAT_L4WD0RST_SET_MSK 0x00002000
390 /* The mask used to clear the ALT_RSTMGR_STAT_L4WD0RST register field value. */
391 #define ALT_RSTMGR_STAT_L4WD0RST_CLR_MSK 0xffffdfff
392 /* The reset value of the ALT_RSTMGR_STAT_L4WD0RST register field. */
393 #define ALT_RSTMGR_STAT_L4WD0RST_RESET 0x0
394 /* Extracts the ALT_RSTMGR_STAT_L4WD0RST field value from a register. */
395 #define ALT_RSTMGR_STAT_L4WD0RST_GET(value) (((value) & 0x00002000) >> 13)
396 /* Produces a ALT_RSTMGR_STAT_L4WD0RST register field value suitable for setting the register. */
397 #define ALT_RSTMGR_STAT_L4WD0RST_SET(value) (((value) << 13) & 0x00002000)
398 
399 /*
400  * Field : L4 Watchdog 1 Warm Reset - l4wd1rst
401  *
402  * L4 Watchdog 1 triggered a hardware sequenced warm reset
403  *
404  * Field Access Macros:
405  *
406  */
407 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field. */
408 #define ALT_RSTMGR_STAT_L4WD1RST_LSB 14
409 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field. */
410 #define ALT_RSTMGR_STAT_L4WD1RST_MSB 14
411 /* The width in bits of the ALT_RSTMGR_STAT_L4WD1RST register field. */
412 #define ALT_RSTMGR_STAT_L4WD1RST_WIDTH 1
413 /* The mask used to set the ALT_RSTMGR_STAT_L4WD1RST register field value. */
414 #define ALT_RSTMGR_STAT_L4WD1RST_SET_MSK 0x00004000
415 /* The mask used to clear the ALT_RSTMGR_STAT_L4WD1RST register field value. */
416 #define ALT_RSTMGR_STAT_L4WD1RST_CLR_MSK 0xffffbfff
417 /* The reset value of the ALT_RSTMGR_STAT_L4WD1RST register field. */
418 #define ALT_RSTMGR_STAT_L4WD1RST_RESET 0x0
419 /* Extracts the ALT_RSTMGR_STAT_L4WD1RST field value from a register. */
420 #define ALT_RSTMGR_STAT_L4WD1RST_GET(value) (((value) & 0x00004000) >> 14)
421 /* Produces a ALT_RSTMGR_STAT_L4WD1RST register field value suitable for setting the register. */
422 #define ALT_RSTMGR_STAT_L4WD1RST_SET(value) (((value) << 14) & 0x00004000)
423 
424 /*
425  * Field : FPGA Core Debug Reset - fpgadbgrst
426  *
427  * FPGA triggered debug reset
428  *
429  * Field Access Macros:
430  *
431  */
432 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGADBGRST register field. */
433 #define ALT_RSTMGR_STAT_FPGADBGRST_LSB 16
434 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGADBGRST register field. */
435 #define ALT_RSTMGR_STAT_FPGADBGRST_MSB 16
436 /* The width in bits of the ALT_RSTMGR_STAT_FPGADBGRST register field. */
437 #define ALT_RSTMGR_STAT_FPGADBGRST_WIDTH 1
438 /* The mask used to set the ALT_RSTMGR_STAT_FPGADBGRST register field value. */
439 #define ALT_RSTMGR_STAT_FPGADBGRST_SET_MSK 0x00010000
440 /* The mask used to clear the ALT_RSTMGR_STAT_FPGADBGRST register field value. */
441 #define ALT_RSTMGR_STAT_FPGADBGRST_CLR_MSK 0xfffeffff
442 /* The reset value of the ALT_RSTMGR_STAT_FPGADBGRST register field. */
443 #define ALT_RSTMGR_STAT_FPGADBGRST_RESET 0x0
444 /* Extracts the ALT_RSTMGR_STAT_FPGADBGRST field value from a register. */
445 #define ALT_RSTMGR_STAT_FPGADBGRST_GET(value) (((value) & 0x00010000) >> 16)
446 /* Produces a ALT_RSTMGR_STAT_FPGADBGRST register field value suitable for setting the register. */
447 #define ALT_RSTMGR_STAT_FPGADBGRST_SET(value) (((value) << 16) & 0x00010000)
448 
449 /*
450  * Field : DAP Debug Reset - cdbgreqrst
451  *
452  * DAP triggered debug reset
453  *
454  * Field Access Macros:
455  *
456  */
457 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CDBGREQRST register field. */
458 #define ALT_RSTMGR_STAT_CDBGREQRST_LSB 17
459 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CDBGREQRST register field. */
460 #define ALT_RSTMGR_STAT_CDBGREQRST_MSB 17
461 /* The width in bits of the ALT_RSTMGR_STAT_CDBGREQRST register field. */
462 #define ALT_RSTMGR_STAT_CDBGREQRST_WIDTH 1
463 /* The mask used to set the ALT_RSTMGR_STAT_CDBGREQRST register field value. */
464 #define ALT_RSTMGR_STAT_CDBGREQRST_SET_MSK 0x00020000
465 /* The mask used to clear the ALT_RSTMGR_STAT_CDBGREQRST register field value. */
466 #define ALT_RSTMGR_STAT_CDBGREQRST_CLR_MSK 0xfffdffff
467 /* The reset value of the ALT_RSTMGR_STAT_CDBGREQRST register field. */
468 #define ALT_RSTMGR_STAT_CDBGREQRST_RESET 0x0
469 /* Extracts the ALT_RSTMGR_STAT_CDBGREQRST field value from a register. */
470 #define ALT_RSTMGR_STAT_CDBGREQRST_GET(value) (((value) & 0x00020000) >> 17)
471 /* Produces a ALT_RSTMGR_STAT_CDBGREQRST register field value suitable for setting the register. */
472 #define ALT_RSTMGR_STAT_CDBGREQRST_SET(value) (((value) << 17) & 0x00020000)
473 
474 #ifndef __ASSEMBLY__
475 /*
476  * WARNING: The C register and register group struct declarations are provided for
477  * convenience and illustrative purposes. They should, however, be used with
478  * caution as the C language standard provides no guarantees about the alignment or
479  * atomicity of device memory accesses. The recommended practice for writing
480  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
481  * alt_write_word() functions.
482  *
483  * The struct declaration for register ALT_RSTMGR_STAT.
484  */
485 struct ALT_RSTMGR_STAT_s
486 {
487  uint32_t porhpsvoltrst : 1; /* HPS Power-On Voltage Detector Cold Reset */
488  uint32_t porfpgavoltrst : 1; /* Power-On FPGA Voltage Detector Cold Reset */
489  uint32_t nporpinrst : 1; /* nPOR Pin Cold Reset */
490  uint32_t fpgacoldrst : 1; /* FPGA Core Cold Reset */
491  uint32_t configiocoldrst : 1; /* CONFIG_IO Cold Reset */
492  uint32_t swcoldrst : 1; /* Software Cold Reset */
493  uint32_t : 2; /* *UNDEFINED* */
494  uint32_t nrstpinrst : 1; /* nRST Pin Warm Reset */
495  uint32_t fpgawarmrst : 1; /* FPGA Core Warm Reset */
496  uint32_t swwarmrst : 1; /* Software Warm Reset */
497  uint32_t mpuwd0rst : 1; /* MPU Watchdog 0 Warm Reset */
498  uint32_t mpuwd1rst : 1; /* MPU Watchdog 1 Warm Reset */
499  uint32_t l4wd0rst : 1; /* L4 Watchdog 0 Warm Reset */
500  uint32_t l4wd1rst : 1; /* L4 Watchdog 1 Warm Reset */
501  uint32_t : 1; /* *UNDEFINED* */
502  uint32_t fpgadbgrst : 1; /* FPGA Core Debug Reset */
503  uint32_t cdbgreqrst : 1; /* DAP Debug Reset */
504  uint32_t : 14; /* *UNDEFINED* */
505 };
506 
507 /* The typedef declaration for register ALT_RSTMGR_STAT. */
508 typedef volatile struct ALT_RSTMGR_STAT_s ALT_RSTMGR_STAT_t;
509 #endif /* __ASSEMBLY__ */
510 
511 /* The reset value of the ALT_RSTMGR_STAT register. */
512 #define ALT_RSTMGR_STAT_RESET 0x00000000
513 /* The byte offset of the ALT_RSTMGR_STAT register from the beginning of the component. */
514 #define ALT_RSTMGR_STAT_OFST 0x0
515 
516 /*
517  * Register : RAM Status Register - ramstat
518  *
519  * The RAMSTAT register contains bits that indicate the security RAM clearing event
520  * during cold or warm reset for each RAM.
521  *
522  * Software clears bits by writing them with a value of 1. Writes to bits with a
523  * value of 0 are ignored.
524  *
525  * For MPU, there are seperate bits for L1 invalidate only or full security
526  * clearing.
527  *
528  * There is another bit for L1 invalidate timeout error only. The security RAM
529  * clearing does not have a timeout.
530  *
531  * Register Layout
532  *
533  * Bits | Access | Reset | Description
534  * :--------|:-------|:------|:---------------------------------------------------------------------
535  * [0] | RW | 0x0 | Onchip RAM RAMSTATUS bit during cold/warm reset
536  * [1] | RW | 0x0 | USB0 RAM RAMSTATUS bit during cold/warm reset
537  * [2] | RW | 0x0 | USB1 RAM RAMSTATUS bit during cold/warm reset
538  * [3] | RW | 0x0 | SDMMC RAM RAMSTATUS bit during cold/warm reset
539  * [4] | RW | 0x0 | DMA RAM RAMSTATUS bit during cold/warm reset
540  * [5] | RW | 0x0 | NAND Write RAM RAMSTATUS bit during cold/warm reset
541  * [6] | RW | 0x0 | NAND Read RAM RAMSTATUS bit during cold/warm reset
542  * [7] | RW | 0x0 | NAND ECC RAM RAMSTATUS bit during cold/warm reset
543  * [8] | RW | 0x0 | EMAC0 RX RAM RAMSTATUS bit during cold/warm reset
544  * [9] | RW | 0x0 | EMAC0 TX RAM RAMSTATUS bit during cold/warm reset
545  * [10] | RW | 0x0 | EMAC1 RX RAM RAMSTATUS bit during cold/warm reset
546  * [11] | RW | 0x0 | EMAC1 TX RAM RAMSTATUS bit during cold/warm reset
547  * [12] | RW | 0x0 | EMAC2 TX RAM RAMSTATUS bit during cold/warm reset
548  * [13] | RW | 0x0 | EMAC2 RX RAM RAMSTATUS bit during cold/warm reset
549  * [14] | RW | 0x0 | QSPI RAM RAMSTATUS bit during cold/warm reset
550  * [15] | RW | 0x0 | MWP RAM RAMSTATUS bit during cold/warm reset
551  * [16] | RW | 0x0 | MPU L1 invalidate clearing only RAMSTATUS bit during cold/warm reset
552  * [17] | RW | 0x0 | MPU l1 RAM clearing timeout during cold/warm reset
553  * [31:18] | ??? | 0x0 | *UNDEFINED*
554  *
555  */
556 /*
557  * Field : Onchip RAM RAMSTATUS bit during cold/warm reset - onchipramclr
558  *
559  * RAMSTATUS bit to indicate Onchip RAM is cleared during cold/warm reset
560  *
561  * Field Access Macros:
562  *
563  */
564 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR register field. */
565 #define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_LSB 0
566 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR register field. */
567 #define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_MSB 0
568 /* The width in bits of the ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR register field. */
569 #define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_WIDTH 1
570 /* The mask used to set the ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR register field value. */
571 #define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_SET_MSK 0x00000001
572 /* The mask used to clear the ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR register field value. */
573 #define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_CLR_MSK 0xfffffffe
574 /* The reset value of the ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR register field. */
575 #define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_RESET 0x0
576 /* Extracts the ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR field value from a register. */
577 #define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_GET(value) (((value) & 0x00000001) >> 0)
578 /* Produces a ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR register field value suitable for setting the register. */
579 #define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_SET(value) (((value) << 0) & 0x00000001)
580 
581 /*
582  * Field : USB0 RAM RAMSTATUS bit during cold/warm reset - otg0ramclr
583  *
584  * RAMSTATUS bit to indicate USB0 RAM is cleared during cold/warm reset
585  *
586  * Field Access Macros:
587  *
588  */
589 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_OTG0RAMCLR register field. */
590 #define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_LSB 1
591 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_OTG0RAMCLR register field. */
592 #define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_MSB 1
593 /* The width in bits of the ALT_RSTMGR_RAMSTAT_OTG0RAMCLR register field. */
594 #define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_WIDTH 1
595 /* The mask used to set the ALT_RSTMGR_RAMSTAT_OTG0RAMCLR register field value. */
596 #define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_SET_MSK 0x00000002
597 /* The mask used to clear the ALT_RSTMGR_RAMSTAT_OTG0RAMCLR register field value. */
598 #define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_CLR_MSK 0xfffffffd
599 /* The reset value of the ALT_RSTMGR_RAMSTAT_OTG0RAMCLR register field. */
600 #define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_RESET 0x0
601 /* Extracts the ALT_RSTMGR_RAMSTAT_OTG0RAMCLR field value from a register. */
602 #define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_GET(value) (((value) & 0x00000002) >> 1)
603 /* Produces a ALT_RSTMGR_RAMSTAT_OTG0RAMCLR register field value suitable for setting the register. */
604 #define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_SET(value) (((value) << 1) & 0x00000002)
605 
606 /*
607  * Field : USB1 RAM RAMSTATUS bit during cold/warm reset - otg1ramclr
608  *
609  * RAMSTATUS bit to indicate USB1 RAM is cleared during cold/warm reset
610  *
611  * Field Access Macros:
612  *
613  */
614 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_OTG1RAMCLR register field. */
615 #define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_LSB 2
616 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_OTG1RAMCLR register field. */
617 #define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_MSB 2
618 /* The width in bits of the ALT_RSTMGR_RAMSTAT_OTG1RAMCLR register field. */
619 #define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_WIDTH 1
620 /* The mask used to set the ALT_RSTMGR_RAMSTAT_OTG1RAMCLR register field value. */
621 #define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_SET_MSK 0x00000004
622 /* The mask used to clear the ALT_RSTMGR_RAMSTAT_OTG1RAMCLR register field value. */
623 #define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_CLR_MSK 0xfffffffb
624 /* The reset value of the ALT_RSTMGR_RAMSTAT_OTG1RAMCLR register field. */
625 #define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_RESET 0x0
626 /* Extracts the ALT_RSTMGR_RAMSTAT_OTG1RAMCLR field value from a register. */
627 #define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_GET(value) (((value) & 0x00000004) >> 2)
628 /* Produces a ALT_RSTMGR_RAMSTAT_OTG1RAMCLR register field value suitable for setting the register. */
629 #define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_SET(value) (((value) << 2) & 0x00000004)
630 
631 /*
632  * Field : SDMMC RAM RAMSTATUS bit during cold/warm reset - sdmmcramclr
633  *
634  * RAMSTATUS bit to indicate SDMMC RAM is cleared during cold/warm reset
635  *
636  * Field Access Macros:
637  *
638  */
639 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR register field. */
640 #define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_LSB 3
641 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR register field. */
642 #define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_MSB 3
643 /* The width in bits of the ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR register field. */
644 #define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_WIDTH 1
645 /* The mask used to set the ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR register field value. */
646 #define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_SET_MSK 0x00000008
647 /* The mask used to clear the ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR register field value. */
648 #define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_CLR_MSK 0xfffffff7
649 /* The reset value of the ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR register field. */
650 #define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_RESET 0x0
651 /* Extracts the ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR field value from a register. */
652 #define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_GET(value) (((value) & 0x00000008) >> 3)
653 /* Produces a ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR register field value suitable for setting the register. */
654 #define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_SET(value) (((value) << 3) & 0x00000008)
655 
656 /*
657  * Field : DMA RAM RAMSTATUS bit during cold/warm reset - dmaramclr
658  *
659  * RAMSTATUS bit to indicate DMA RAM is cleared during cold/warm reset
660  *
661  * Field Access Macros:
662  *
663  */
664 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_DMARAMCLR register field. */
665 #define ALT_RSTMGR_RAMSTAT_DMARAMCLR_LSB 4
666 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_DMARAMCLR register field. */
667 #define ALT_RSTMGR_RAMSTAT_DMARAMCLR_MSB 4
668 /* The width in bits of the ALT_RSTMGR_RAMSTAT_DMARAMCLR register field. */
669 #define ALT_RSTMGR_RAMSTAT_DMARAMCLR_WIDTH 1
670 /* The mask used to set the ALT_RSTMGR_RAMSTAT_DMARAMCLR register field value. */
671 #define ALT_RSTMGR_RAMSTAT_DMARAMCLR_SET_MSK 0x00000010
672 /* The mask used to clear the ALT_RSTMGR_RAMSTAT_DMARAMCLR register field value. */
673 #define ALT_RSTMGR_RAMSTAT_DMARAMCLR_CLR_MSK 0xffffffef
674 /* The reset value of the ALT_RSTMGR_RAMSTAT_DMARAMCLR register field. */
675 #define ALT_RSTMGR_RAMSTAT_DMARAMCLR_RESET 0x0
676 /* Extracts the ALT_RSTMGR_RAMSTAT_DMARAMCLR field value from a register. */
677 #define ALT_RSTMGR_RAMSTAT_DMARAMCLR_GET(value) (((value) & 0x00000010) >> 4)
678 /* Produces a ALT_RSTMGR_RAMSTAT_DMARAMCLR register field value suitable for setting the register. */
679 #define ALT_RSTMGR_RAMSTAT_DMARAMCLR_SET(value) (((value) << 4) & 0x00000010)
680 
681 /*
682  * Field : NAND Write RAM RAMSTATUS bit during cold/warm reset - nandwramclr
683  *
684  * RAMSTATUS bit to indicate NAND Write RAM is cleared during cold/warm reset
685  *
686  * Field Access Macros:
687  *
688  */
689 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_NANDWRAMCLR register field. */
690 #define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_LSB 5
691 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_NANDWRAMCLR register field. */
692 #define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_MSB 5
693 /* The width in bits of the ALT_RSTMGR_RAMSTAT_NANDWRAMCLR register field. */
694 #define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_WIDTH 1
695 /* The mask used to set the ALT_RSTMGR_RAMSTAT_NANDWRAMCLR register field value. */
696 #define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_SET_MSK 0x00000020
697 /* The mask used to clear the ALT_RSTMGR_RAMSTAT_NANDWRAMCLR register field value. */
698 #define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_CLR_MSK 0xffffffdf
699 /* The reset value of the ALT_RSTMGR_RAMSTAT_NANDWRAMCLR register field. */
700 #define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_RESET 0x0
701 /* Extracts the ALT_RSTMGR_RAMSTAT_NANDWRAMCLR field value from a register. */
702 #define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_GET(value) (((value) & 0x00000020) >> 5)
703 /* Produces a ALT_RSTMGR_RAMSTAT_NANDWRAMCLR register field value suitable for setting the register. */
704 #define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_SET(value) (((value) << 5) & 0x00000020)
705 
706 /*
707  * Field : NAND Read RAM RAMSTATUS bit during cold/warm reset - nandrramclr
708  *
709  * RAMSTATUS bit to indicate NAND Read RAM is cleared during cold/warm reset
710  *
711  * Field Access Macros:
712  *
713  */
714 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_NANDRRAMCLR register field. */
715 #define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_LSB 6
716 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_NANDRRAMCLR register field. */
717 #define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_MSB 6
718 /* The width in bits of the ALT_RSTMGR_RAMSTAT_NANDRRAMCLR register field. */
719 #define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_WIDTH 1
720 /* The mask used to set the ALT_RSTMGR_RAMSTAT_NANDRRAMCLR register field value. */
721 #define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_SET_MSK 0x00000040
722 /* The mask used to clear the ALT_RSTMGR_RAMSTAT_NANDRRAMCLR register field value. */
723 #define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_CLR_MSK 0xffffffbf
724 /* The reset value of the ALT_RSTMGR_RAMSTAT_NANDRRAMCLR register field. */
725 #define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_RESET 0x0
726 /* Extracts the ALT_RSTMGR_RAMSTAT_NANDRRAMCLR field value from a register. */
727 #define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_GET(value) (((value) & 0x00000040) >> 6)
728 /* Produces a ALT_RSTMGR_RAMSTAT_NANDRRAMCLR register field value suitable for setting the register. */
729 #define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_SET(value) (((value) << 6) & 0x00000040)
730 
731 /*
732  * Field : NAND ECC RAM RAMSTATUS bit during cold/warm reset - nanderamclr
733  *
734  * RAMSTATUS bit to indicate NAND ECC RAM is cleared during cold/warm reset
735  *
736  * Field Access Macros:
737  *
738  */
739 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_NANDERAMCLR register field. */
740 #define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_LSB 7
741 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_NANDERAMCLR register field. */
742 #define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_MSB 7
743 /* The width in bits of the ALT_RSTMGR_RAMSTAT_NANDERAMCLR register field. */
744 #define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_WIDTH 1
745 /* The mask used to set the ALT_RSTMGR_RAMSTAT_NANDERAMCLR register field value. */
746 #define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_SET_MSK 0x00000080
747 /* The mask used to clear the ALT_RSTMGR_RAMSTAT_NANDERAMCLR register field value. */
748 #define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_CLR_MSK 0xffffff7f
749 /* The reset value of the ALT_RSTMGR_RAMSTAT_NANDERAMCLR register field. */
750 #define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_RESET 0x0
751 /* Extracts the ALT_RSTMGR_RAMSTAT_NANDERAMCLR field value from a register. */
752 #define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_GET(value) (((value) & 0x00000080) >> 7)
753 /* Produces a ALT_RSTMGR_RAMSTAT_NANDERAMCLR register field value suitable for setting the register. */
754 #define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_SET(value) (((value) << 7) & 0x00000080)
755 
756 /*
757  * Field : EMAC0 RX RAM RAMSTATUS bit during cold/warm reset - emac0rxramclr
758  *
759  * RAMSTATUS bit to indicate EMAC0 RX RAM is cleared during cold/warm reset
760  *
761  * Field Access Macros:
762  *
763  */
764 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR register field. */
765 #define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_LSB 8
766 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR register field. */
767 #define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_MSB 8
768 /* The width in bits of the ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR register field. */
769 #define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_WIDTH 1
770 /* The mask used to set the ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR register field value. */
771 #define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_SET_MSK 0x00000100
772 /* The mask used to clear the ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR register field value. */
773 #define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_CLR_MSK 0xfffffeff
774 /* The reset value of the ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR register field. */
775 #define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_RESET 0x0
776 /* Extracts the ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR field value from a register. */
777 #define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_GET(value) (((value) & 0x00000100) >> 8)
778 /* Produces a ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR register field value suitable for setting the register. */
779 #define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_SET(value) (((value) << 8) & 0x00000100)
780 
781 /*
782  * Field : EMAC0 TX RAM RAMSTATUS bit during cold/warm reset - emac0txramclr
783  *
784  * RAMSTATUS bit to indicate EMAC0 TX RAM is cleared during cold/warm reset
785  *
786  * Field Access Macros:
787  *
788  */
789 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR register field. */
790 #define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_LSB 9
791 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR register field. */
792 #define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_MSB 9
793 /* The width in bits of the ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR register field. */
794 #define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_WIDTH 1
795 /* The mask used to set the ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR register field value. */
796 #define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_SET_MSK 0x00000200
797 /* The mask used to clear the ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR register field value. */
798 #define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_CLR_MSK 0xfffffdff
799 /* The reset value of the ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR register field. */
800 #define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_RESET 0x0
801 /* Extracts the ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR field value from a register. */
802 #define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_GET(value) (((value) & 0x00000200) >> 9)
803 /* Produces a ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR register field value suitable for setting the register. */
804 #define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_SET(value) (((value) << 9) & 0x00000200)
805 
806 /*
807  * Field : EMAC1 RX RAM RAMSTATUS bit during cold/warm reset - emac1rxramclr
808  *
809  * RAMSTATUS bit to indicate EMAC1 RX RAM is cleared during cold/warm reset
810  *
811  * Field Access Macros:
812  *
813  */
814 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR register field. */
815 #define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_LSB 10
816 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR register field. */
817 #define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_MSB 10
818 /* The width in bits of the ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR register field. */
819 #define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_WIDTH 1
820 /* The mask used to set the ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR register field value. */
821 #define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_SET_MSK 0x00000400
822 /* The mask used to clear the ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR register field value. */
823 #define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_CLR_MSK 0xfffffbff
824 /* The reset value of the ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR register field. */
825 #define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_RESET 0x0
826 /* Extracts the ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR field value from a register. */
827 #define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_GET(value) (((value) & 0x00000400) >> 10)
828 /* Produces a ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR register field value suitable for setting the register. */
829 #define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_SET(value) (((value) << 10) & 0x00000400)
830 
831 /*
832  * Field : EMAC1 TX RAM RAMSTATUS bit during cold/warm reset - emac1txramclr
833  *
834  * RAMSTATUS bit to indicate EMAC1 TX RAM is cleared during cold/warm reset
835  *
836  * Field Access Macros:
837  *
838  */
839 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR register field. */
840 #define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_LSB 11
841 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR register field. */
842 #define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_MSB 11
843 /* The width in bits of the ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR register field. */
844 #define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_WIDTH 1
845 /* The mask used to set the ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR register field value. */
846 #define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_SET_MSK 0x00000800
847 /* The mask used to clear the ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR register field value. */
848 #define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_CLR_MSK 0xfffff7ff
849 /* The reset value of the ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR register field. */
850 #define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_RESET 0x0
851 /* Extracts the ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR field value from a register. */
852 #define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_GET(value) (((value) & 0x00000800) >> 11)
853 /* Produces a ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR register field value suitable for setting the register. */
854 #define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_SET(value) (((value) << 11) & 0x00000800)
855 
856 /*
857  * Field : EMAC2 TX RAM RAMSTATUS bit during cold/warm reset - emac2txramclr
858  *
859  * RAMSTATUS bit to indicate EMAC2 TX RAM is cleared during cold/warm reset
860  *
861  * Field Access Macros:
862  *
863  */
864 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR register field. */
865 #define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_LSB 12
866 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR register field. */
867 #define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_MSB 12
868 /* The width in bits of the ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR register field. */
869 #define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_WIDTH 1
870 /* The mask used to set the ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR register field value. */
871 #define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_SET_MSK 0x00001000
872 /* The mask used to clear the ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR register field value. */
873 #define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_CLR_MSK 0xffffefff
874 /* The reset value of the ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR register field. */
875 #define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_RESET 0x0
876 /* Extracts the ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR field value from a register. */
877 #define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_GET(value) (((value) & 0x00001000) >> 12)
878 /* Produces a ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR register field value suitable for setting the register. */
879 #define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_SET(value) (((value) << 12) & 0x00001000)
880 
881 /*
882  * Field : EMAC2 RX RAM RAMSTATUS bit during cold/warm reset - emac2rxramclr
883  *
884  * RAMSTATUS bit to indicate EMAC2 RX RAM is cleared during cold/warm reset
885  *
886  * Field Access Macros:
887  *
888  */
889 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR register field. */
890 #define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_LSB 13
891 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR register field. */
892 #define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_MSB 13
893 /* The width in bits of the ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR register field. */
894 #define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_WIDTH 1
895 /* The mask used to set the ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR register field value. */
896 #define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_SET_MSK 0x00002000
897 /* The mask used to clear the ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR register field value. */
898 #define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_CLR_MSK 0xffffdfff
899 /* The reset value of the ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR register field. */
900 #define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_RESET 0x0
901 /* Extracts the ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR field value from a register. */
902 #define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_GET(value) (((value) & 0x00002000) >> 13)
903 /* Produces a ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR register field value suitable for setting the register. */
904 #define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_SET(value) (((value) << 13) & 0x00002000)
905 
906 /*
907  * Field : QSPI RAM RAMSTATUS bit during cold/warm reset - qspiramclr
908  *
909  * RAMSTATUS bit to indicate QSPI RAM is cleared during cold/warm reset
910  *
911  * Field Access Macros:
912  *
913  */
914 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_QSPIRAMCLR register field. */
915 #define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_LSB 14
916 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_QSPIRAMCLR register field. */
917 #define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_MSB 14
918 /* The width in bits of the ALT_RSTMGR_RAMSTAT_QSPIRAMCLR register field. */
919 #define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_WIDTH 1
920 /* The mask used to set the ALT_RSTMGR_RAMSTAT_QSPIRAMCLR register field value. */
921 #define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_SET_MSK 0x00004000
922 /* The mask used to clear the ALT_RSTMGR_RAMSTAT_QSPIRAMCLR register field value. */
923 #define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_CLR_MSK 0xffffbfff
924 /* The reset value of the ALT_RSTMGR_RAMSTAT_QSPIRAMCLR register field. */
925 #define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_RESET 0x0
926 /* Extracts the ALT_RSTMGR_RAMSTAT_QSPIRAMCLR field value from a register. */
927 #define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_GET(value) (((value) & 0x00004000) >> 14)
928 /* Produces a ALT_RSTMGR_RAMSTAT_QSPIRAMCLR register field value suitable for setting the register. */
929 #define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_SET(value) (((value) << 14) & 0x00004000)
930 
931 /*
932  * Field : MWP RAM RAMSTATUS bit during cold/warm reset - mwpramclr
933  *
934  * RAMSTATUS bit to indicate MWP RAM is cleared during cold/warm reset
935  *
936  * Field Access Macros:
937  *
938  */
939 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_MWPRAMCLR register field. */
940 #define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_LSB 15
941 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_MWPRAMCLR register field. */
942 #define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_MSB 15
943 /* The width in bits of the ALT_RSTMGR_RAMSTAT_MWPRAMCLR register field. */
944 #define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_WIDTH 1
945 /* The mask used to set the ALT_RSTMGR_RAMSTAT_MWPRAMCLR register field value. */
946 #define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_SET_MSK 0x00008000
947 /* The mask used to clear the ALT_RSTMGR_RAMSTAT_MWPRAMCLR register field value. */
948 #define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_CLR_MSK 0xffff7fff
949 /* The reset value of the ALT_RSTMGR_RAMSTAT_MWPRAMCLR register field. */
950 #define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_RESET 0x0
951 /* Extracts the ALT_RSTMGR_RAMSTAT_MWPRAMCLR field value from a register. */
952 #define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_GET(value) (((value) & 0x00008000) >> 15)
953 /* Produces a ALT_RSTMGR_RAMSTAT_MWPRAMCLR register field value suitable for setting the register. */
954 #define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_SET(value) (((value) << 15) & 0x00008000)
955 
956 /*
957  * Field : MPU L1 invalidate clearing only RAMSTATUS bit during cold/warm reset - mpul1ramclr
958  *
959  * RAMSTATUS bit to indicate MPU L1 invalidate clearing only or full security
960  * clearing during cold/warm reset
961  *
962  * Field Access Macros:
963  *
964  */
965 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR register field. */
966 #define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_LSB 16
967 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR register field. */
968 #define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_MSB 16
969 /* The width in bits of the ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR register field. */
970 #define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_WIDTH 1
971 /* The mask used to set the ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR register field value. */
972 #define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_SET_MSK 0x00010000
973 /* The mask used to clear the ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR register field value. */
974 #define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_CLR_MSK 0xfffeffff
975 /* The reset value of the ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR register field. */
976 #define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_RESET 0x0
977 /* Extracts the ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR field value from a register. */
978 #define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_GET(value) (((value) & 0x00010000) >> 16)
979 /* Produces a ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR register field value suitable for setting the register. */
980 #define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_SET(value) (((value) << 16) & 0x00010000)
981 
982 /*
983  * Field : MPU l1 RAM clearing timeout during cold/warm reset - mpul1timeout
984  *
985  * RAMSTATUS bit to indicate MPU l1 RAM cleared timeout during cold/warm reset
986  *
987  * Field Access Macros:
988  *
989  */
990 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_MPUL1TMO register field. */
991 #define ALT_RSTMGR_RAMSTAT_MPUL1TMO_LSB 17
992 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_MPUL1TMO register field. */
993 #define ALT_RSTMGR_RAMSTAT_MPUL1TMO_MSB 17
994 /* The width in bits of the ALT_RSTMGR_RAMSTAT_MPUL1TMO register field. */
995 #define ALT_RSTMGR_RAMSTAT_MPUL1TMO_WIDTH 1
996 /* The mask used to set the ALT_RSTMGR_RAMSTAT_MPUL1TMO register field value. */
997 #define ALT_RSTMGR_RAMSTAT_MPUL1TMO_SET_MSK 0x00020000
998 /* The mask used to clear the ALT_RSTMGR_RAMSTAT_MPUL1TMO register field value. */
999 #define ALT_RSTMGR_RAMSTAT_MPUL1TMO_CLR_MSK 0xfffdffff
1000 /* The reset value of the ALT_RSTMGR_RAMSTAT_MPUL1TMO register field. */
1001 #define ALT_RSTMGR_RAMSTAT_MPUL1TMO_RESET 0x0
1002 /* Extracts the ALT_RSTMGR_RAMSTAT_MPUL1TMO field value from a register. */
1003 #define ALT_RSTMGR_RAMSTAT_MPUL1TMO_GET(value) (((value) & 0x00020000) >> 17)
1004 /* Produces a ALT_RSTMGR_RAMSTAT_MPUL1TMO register field value suitable for setting the register. */
1005 #define ALT_RSTMGR_RAMSTAT_MPUL1TMO_SET(value) (((value) << 17) & 0x00020000)
1006 
1007 #ifndef __ASSEMBLY__
1008 /*
1009  * WARNING: The C register and register group struct declarations are provided for
1010  * convenience and illustrative purposes. They should, however, be used with
1011  * caution as the C language standard provides no guarantees about the alignment or
1012  * atomicity of device memory accesses. The recommended practice for writing
1013  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1014  * alt_write_word() functions.
1015  *
1016  * The struct declaration for register ALT_RSTMGR_RAMSTAT.
1017  */
1018 struct ALT_RSTMGR_RAMSTAT_s
1019 {
1020  uint32_t onchipramclr : 1; /* Onchip RAM RAMSTATUS bit during cold/warm reset */
1021  uint32_t otg0ramclr : 1; /* USB0 RAM RAMSTATUS bit during cold/warm reset */
1022  uint32_t otg1ramclr : 1; /* USB1 RAM RAMSTATUS bit during cold/warm reset */
1023  uint32_t sdmmcramclr : 1; /* SDMMC RAM RAMSTATUS bit during cold/warm reset */
1024  uint32_t dmaramclr : 1; /* DMA RAM RAMSTATUS bit during cold/warm reset */
1025  uint32_t nandwramclr : 1; /* NAND Write RAM RAMSTATUS bit during cold/warm reset */
1026  uint32_t nandrramclr : 1; /* NAND Read RAM RAMSTATUS bit during cold/warm reset */
1027  uint32_t nanderamclr : 1; /* NAND ECC RAM RAMSTATUS bit during cold/warm reset */
1028  uint32_t emac0rxramclr : 1; /* EMAC0 RX RAM RAMSTATUS bit during cold/warm reset */
1029  uint32_t emac0txramclr : 1; /* EMAC0 TX RAM RAMSTATUS bit during cold/warm reset */
1030  uint32_t emac1rxramclr : 1; /* EMAC1 RX RAM RAMSTATUS bit during cold/warm reset */
1031  uint32_t emac1txramclr : 1; /* EMAC1 TX RAM RAMSTATUS bit during cold/warm reset */
1032  uint32_t emac2txramclr : 1; /* EMAC2 TX RAM RAMSTATUS bit during cold/warm reset */
1033  uint32_t emac2rxramclr : 1; /* EMAC2 RX RAM RAMSTATUS bit during cold/warm reset */
1034  uint32_t qspiramclr : 1; /* QSPI RAM RAMSTATUS bit during cold/warm reset */
1035  uint32_t mwpramclr : 1; /* MWP RAM RAMSTATUS bit during cold/warm reset */
1036  uint32_t mpul1ramclr : 1; /* MPU L1 invalidate clearing only RAMSTATUS bit during cold/warm reset */
1037  uint32_t mpul1timeout : 1; /* MPU l1 RAM clearing timeout during cold/warm reset */
1038  uint32_t : 14; /* *UNDEFINED* */
1039 };
1040 
1041 /* The typedef declaration for register ALT_RSTMGR_RAMSTAT. */
1042 typedef volatile struct ALT_RSTMGR_RAMSTAT_s ALT_RSTMGR_RAMSTAT_t;
1043 #endif /* __ASSEMBLY__ */
1044 
1045 /* The reset value of the ALT_RSTMGR_RAMSTAT register. */
1046 #define ALT_RSTMGR_RAMSTAT_RESET 0x00000000
1047 /* The byte offset of the ALT_RSTMGR_RAMSTAT register from the beginning of the component. */
1048 #define ALT_RSTMGR_RAMSTAT_OFST 0x4
1049 
1050 /*
1051  * Register : Status Register - miscstat
1052  *
1053  * The MISCSTAT register contains bits that indicate the timeout event. For timeout
1054  * events, a field is 1 if its associated timeout occured as part of a hardware
1055  * sequenced warm/debug reset.
1056  *
1057  * Software clears bits by writing them with a value of 1. Writes to bits with a
1058  * value of 0 are ignored.
1059  *
1060  * After a cold reset is complete, all bits are reset to their reset value except
1061  * for the bit(s) that indicate the source of the cold reset. If multiple cold
1062  * reset requests overlap with each other, the source de-asserts the request last
1063  * will be logged. The other reset request source(s) de-assert the request in the
1064  * same cycle will also be logged, the rest of the fields are reset to default
1065  * value of 0.
1066  *
1067  * After a warm reset is complete, the bit(s) that indicate the source of the warm
1068  * reset are set to 1. A warm reset doesn't clear any of the bits in the MISCSTAT
1069  * register; these bits must be cleared by software writing the STAT register.
1070  *
1071  * Register Layout
1072  *
1073  * Bits | Access | Reset | Description
1074  * :-------|:-------|:------|:-------------------------------
1075  * [0] | RW | 0x0 | SDRAM Self-Refresh Timeout
1076  * [1] | RW | 0x0 | FPGA manager handshake Timeout
1077  * [2] | RW | 0x0 | FPGA handshake Timeout
1078  * [3] | RW | 0x0 | ETR Stall Timeout
1079  * [31:4] | ??? | 0x0 | *UNDEFINED*
1080  *
1081  */
1082 /*
1083  * Field : SDRAM Self-Refresh Timeout - sdrselfreftimeout
1084  *
1085  * A 1 indicates that Reset Manager's request to the SDRAM Controller Subsystem to
1086  * put the SDRAM devices into self-refresh mode before starting a hardware
1087  * sequenced warm reset timed-out and the Reset Manager had to proceed with the
1088  * warm reset anyway.
1089  *
1090  * Field Access Macros:
1091  *
1092  */
1093 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO register field. */
1094 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_LSB 0
1095 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO register field. */
1096 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_MSB 0
1097 /* The width in bits of the ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO register field. */
1098 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_WIDTH 1
1099 /* The mask used to set the ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO register field value. */
1100 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_SET_MSK 0x00000001
1101 /* The mask used to clear the ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO register field value. */
1102 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_CLR_MSK 0xfffffffe
1103 /* The reset value of the ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO register field. */
1104 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_RESET 0x0
1105 /* Extracts the ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO field value from a register. */
1106 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_GET(value) (((value) & 0x00000001) >> 0)
1107 /* Produces a ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO register field value suitable for setting the register. */
1108 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_SET(value) (((value) << 0) & 0x00000001)
1109 
1110 /*
1111  * Field : FPGA manager handshake Timeout - fpgamgrhstimeout
1112  *
1113  * A 1 indicates that Reset Manager's request to the FPGA manager to stop driving
1114  * configuration clock to FPGA CB before starting a hardware sequenced warm reset
1115  * timed-out and the Reset Manager had to proceed with the warm reset anyway.
1116  *
1117  * Field Access Macros:
1118  *
1119  */
1120 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO register field. */
1121 #define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_LSB 1
1122 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO register field. */
1123 #define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_MSB 1
1124 /* The width in bits of the ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO register field. */
1125 #define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_WIDTH 1
1126 /* The mask used to set the ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO register field value. */
1127 #define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_SET_MSK 0x00000002
1128 /* The mask used to clear the ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO register field value. */
1129 #define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_CLR_MSK 0xfffffffd
1130 /* The reset value of the ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO register field. */
1131 #define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_RESET 0x0
1132 /* Extracts the ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO field value from a register. */
1133 #define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_GET(value) (((value) & 0x00000002) >> 1)
1134 /* Produces a ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO register field value suitable for setting the register. */
1135 #define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_SET(value) (((value) << 1) & 0x00000002)
1136 
1137 /*
1138  * Field : FPGA handshake Timeout - fpgahstimeout
1139  *
1140  * A 1 indicates that Reset Manager's handshake request to FPGA before starting a
1141  * hardware sequenced warm reset timed-out and the Reset Manager had to proceed
1142  * with the warm reset anyway.
1143  *
1144  * Field Access Macros:
1145  *
1146  */
1147 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCSTAT_FPGAHSTMO register field. */
1148 #define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_LSB 2
1149 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCSTAT_FPGAHSTMO register field. */
1150 #define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_MSB 2
1151 /* The width in bits of the ALT_RSTMGR_MISCSTAT_FPGAHSTMO register field. */
1152 #define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_WIDTH 1
1153 /* The mask used to set the ALT_RSTMGR_MISCSTAT_FPGAHSTMO register field value. */
1154 #define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_SET_MSK 0x00000004
1155 /* The mask used to clear the ALT_RSTMGR_MISCSTAT_FPGAHSTMO register field value. */
1156 #define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_CLR_MSK 0xfffffffb
1157 /* The reset value of the ALT_RSTMGR_MISCSTAT_FPGAHSTMO register field. */
1158 #define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_RESET 0x0
1159 /* Extracts the ALT_RSTMGR_MISCSTAT_FPGAHSTMO field value from a register. */
1160 #define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_GET(value) (((value) & 0x00000004) >> 2)
1161 /* Produces a ALT_RSTMGR_MISCSTAT_FPGAHSTMO register field value suitable for setting the register. */
1162 #define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_SET(value) (((value) << 2) & 0x00000004)
1163 
1164 /*
1165  * Field : ETR Stall Timeout - etrstalltimeout
1166  *
1167  * A 1 indicates that Reset Manager's request to the ETR (Embedded Trace Router) to
1168  * stall its AXI master port before starting a hardware sequenced warm reset timed-
1169  * out and the Reset Manager had to proceed with the warm reset anyway.
1170  *
1171  * Field Access Macros:
1172  *
1173  */
1174 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCSTAT_ETRSTALLTMO register field. */
1175 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_LSB 3
1176 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCSTAT_ETRSTALLTMO register field. */
1177 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_MSB 3
1178 /* The width in bits of the ALT_RSTMGR_MISCSTAT_ETRSTALLTMO register field. */
1179 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_WIDTH 1
1180 /* The mask used to set the ALT_RSTMGR_MISCSTAT_ETRSTALLTMO register field value. */
1181 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_SET_MSK 0x00000008
1182 /* The mask used to clear the ALT_RSTMGR_MISCSTAT_ETRSTALLTMO register field value. */
1183 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_CLR_MSK 0xfffffff7
1184 /* The reset value of the ALT_RSTMGR_MISCSTAT_ETRSTALLTMO register field. */
1185 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_RESET 0x0
1186 /* Extracts the ALT_RSTMGR_MISCSTAT_ETRSTALLTMO field value from a register. */
1187 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_GET(value) (((value) & 0x00000008) >> 3)
1188 /* Produces a ALT_RSTMGR_MISCSTAT_ETRSTALLTMO register field value suitable for setting the register. */
1189 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_SET(value) (((value) << 3) & 0x00000008)
1190 
1191 #ifndef __ASSEMBLY__
1192 /*
1193  * WARNING: The C register and register group struct declarations are provided for
1194  * convenience and illustrative purposes. They should, however, be used with
1195  * caution as the C language standard provides no guarantees about the alignment or
1196  * atomicity of device memory accesses. The recommended practice for writing
1197  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1198  * alt_write_word() functions.
1199  *
1200  * The struct declaration for register ALT_RSTMGR_MISCSTAT.
1201  */
1202 struct ALT_RSTMGR_MISCSTAT_s
1203 {
1204  uint32_t sdrselfreftimeout : 1; /* SDRAM Self-Refresh Timeout */
1205  uint32_t fpgamgrhstimeout : 1; /* FPGA manager handshake Timeout */
1206  uint32_t fpgahstimeout : 1; /* FPGA handshake Timeout */
1207  uint32_t etrstalltimeout : 1; /* ETR Stall Timeout */
1208  uint32_t : 28; /* *UNDEFINED* */
1209 };
1210 
1211 /* The typedef declaration for register ALT_RSTMGR_MISCSTAT. */
1212 typedef volatile struct ALT_RSTMGR_MISCSTAT_s ALT_RSTMGR_MISCSTAT_t;
1213 #endif /* __ASSEMBLY__ */
1214 
1215 /* The reset value of the ALT_RSTMGR_MISCSTAT register. */
1216 #define ALT_RSTMGR_MISCSTAT_RESET 0x00000000
1217 /* The byte offset of the ALT_RSTMGR_MISCSTAT register from the beginning of the component. */
1218 #define ALT_RSTMGR_MISCSTAT_OFST 0x8
1219 
1220 /*
1221  * Register : Control Register - ctrl
1222  *
1223  * The CTRL register is used by software to control reset behavior.It includes
1224  * fields for software to initiate the cold and warm reset.
1225  *
1226  * Register Layout
1227  *
1228  * Bits | Access | Reset | Description
1229  * :-------|:-------|:--------|:----------------------------
1230  * [0] | RW | 0x0 | Software Cold Reset Request
1231  * [1] | RW | 0x0 | Software Warm Reset Request
1232  * [31:2] | ??? | Unknown | *UNDEFINED*
1233  *
1234  */
1235 /*
1236  * Field : Software Cold Reset Request - swcoldrstreq
1237  *
1238  * This is a one-shot bit written by software to 1 to trigger a cold reset. It
1239  * always reads the value 0.
1240  *
1241  * Field Access Macros:
1242  *
1243  */
1244 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */
1245 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_LSB 0
1246 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */
1247 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_MSB 0
1248 /* The width in bits of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */
1249 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_WIDTH 1
1250 /* The mask used to set the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value. */
1251 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK 0x00000001
1252 /* The mask used to clear the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value. */
1253 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_CLR_MSK 0xfffffffe
1254 /* The reset value of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */
1255 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_RESET 0x0
1256 /* Extracts the ALT_RSTMGR_CTL_SWCOLDRSTREQ field value from a register. */
1257 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_GET(value) (((value) & 0x00000001) >> 0)
1258 /* Produces a ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value suitable for setting the register. */
1259 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET(value) (((value) << 0) & 0x00000001)
1260 
1261 /*
1262  * Field : Software Warm Reset Request - swwarmrstreq
1263  *
1264  * This is a one-shot bit written by software to 1 to trigger a hardware sequenced
1265  * warm reset. It always reads the value 0.
1266  *
1267  * Field Access Macros:
1268  *
1269  */
1270 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */
1271 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_LSB 1
1272 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */
1273 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_MSB 1
1274 /* The width in bits of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */
1275 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_WIDTH 1
1276 /* The mask used to set the ALT_RSTMGR_CTL_SWWARMRSTREQ register field value. */
1277 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK 0x00000002
1278 /* The mask used to clear the ALT_RSTMGR_CTL_SWWARMRSTREQ register field value. */
1279 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_CLR_MSK 0xfffffffd
1280 /* The reset value of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */
1281 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_RESET 0x0
1282 /* Extracts the ALT_RSTMGR_CTL_SWWARMRSTREQ field value from a register. */
1283 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_GET(value) (((value) & 0x00000002) >> 1)
1284 /* Produces a ALT_RSTMGR_CTL_SWWARMRSTREQ register field value suitable for setting the register. */
1285 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET(value) (((value) << 1) & 0x00000002)
1286 
1287 #ifndef __ASSEMBLY__
1288 /*
1289  * WARNING: The C register and register group struct declarations are provided for
1290  * convenience and illustrative purposes. They should, however, be used with
1291  * caution as the C language standard provides no guarantees about the alignment or
1292  * atomicity of device memory accesses. The recommended practice for writing
1293  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1294  * alt_write_word() functions.
1295  *
1296  * The struct declaration for register ALT_RSTMGR_CTL.
1297  */
1298 struct ALT_RSTMGR_CTL_s
1299 {
1300  uint32_t swcoldrstreq : 1; /* Software Cold Reset Request */
1301  uint32_t swwarmrstreq : 1; /* Software Warm Reset Request */
1302  uint32_t : 30; /* *UNDEFINED* */
1303 };
1304 
1305 /* The typedef declaration for register ALT_RSTMGR_CTL. */
1306 typedef volatile struct ALT_RSTMGR_CTL_s ALT_RSTMGR_CTL_t;
1307 #endif /* __ASSEMBLY__ */
1308 
1309 /* The reset value of the ALT_RSTMGR_CTL register. */
1310 #define ALT_RSTMGR_CTL_RESET 0x00100000
1311 /* The byte offset of the ALT_RSTMGR_CTL register from the beginning of the component. */
1312 #define ALT_RSTMGR_CTL_OFST 0xc
1313 
1314 /*
1315  * Register : Control Register - hdsken
1316  *
1317  * The CTRL register is used by software to control reset behavior.It includes
1318  * fields for enable hardware handshake with other modules before warm reset.
1319  *
1320  * Register Layout
1321  *
1322  * Bits | Access | Reset | Description
1323  * :-------|:-------|:--------|:---------------------------------------------
1324  * [0] | RW | 0x0 | SDRAM Self-Refresh Enable
1325  * [1] | RW | 0x0 | FPGA Manager Handshake Enable
1326  * [2] | RW | 0x0 | FPGA Handshake Enable
1327  * [3] | RW | 0x0 | ETR (Embedded Trace Router) Handshake Enable
1328  * [31:4] | ??? | Unknown | *UNDEFINED*
1329  *
1330  */
1331 /*
1332  * Field : SDRAM Self-Refresh Enable - sdrselfrefen
1333  *
1334  * This field controls whether the contents of SDRAM devices survive a hardware
1335  * sequenced warm reset. If set to 1, the Reset Manager makes a request to the
1336  * SDRAM Controller Subsystem to put the SDRAM devices into self-refresh mode
1337  * before asserting warm reset signals. However, if SDRAM is already in warm reset,
1338  * Handshake with SDRAM is not performed.
1339  *
1340  * Field Access Macros:
1341  *
1342  */
1343 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKEN_SDRSELFREFEN register field. */
1344 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_LSB 0
1345 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKEN_SDRSELFREFEN register field. */
1346 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_MSB 0
1347 /* The width in bits of the ALT_RSTMGR_HDSKEN_SDRSELFREFEN register field. */
1348 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_WIDTH 1
1349 /* The mask used to set the ALT_RSTMGR_HDSKEN_SDRSELFREFEN register field value. */
1350 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK 0x00000001
1351 /* The mask used to clear the ALT_RSTMGR_HDSKEN_SDRSELFREFEN register field value. */
1352 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_CLR_MSK 0xfffffffe
1353 /* The reset value of the ALT_RSTMGR_HDSKEN_SDRSELFREFEN register field. */
1354 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_RESET 0x0
1355 /* Extracts the ALT_RSTMGR_HDSKEN_SDRSELFREFEN field value from a register. */
1356 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_GET(value) (((value) & 0x00000001) >> 0)
1357 /* Produces a ALT_RSTMGR_HDSKEN_SDRSELFREFEN register field value suitable for setting the register. */
1358 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET(value) (((value) << 0) & 0x00000001)
1359 
1360 /*
1361  * Field : FPGA Manager Handshake Enable - fpgamgrhsen
1362  *
1363  * Enables a handshake between the Reset Manager and FPGA Manager before a warm
1364  * reset. The handshake is used to warn the FPGA Manager that a warm reset it
1365  * coming so it can prepare for it. When the FPGA Manager receives a warm reset
1366  * handshake, the FPGA Manager drives its output clock to a quiescent state to
1367  * avoid glitches.
1368  *
1369  * If set to 1, the Manager makes a request to the FPGA Managerbefore asserting
1370  * warm reset signals. However if the FPGA Manager is already in warm reset, the
1371  * handshake is skipped.
1372  *
1373  * If set to 0, the handshake is skipped.
1374  *
1375  * Field Access Macros:
1376  *
1377  */
1378 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKEN_FPGAMGRHSEN register field. */
1379 #define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_LSB 1
1380 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKEN_FPGAMGRHSEN register field. */
1381 #define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_MSB 1
1382 /* The width in bits of the ALT_RSTMGR_HDSKEN_FPGAMGRHSEN register field. */
1383 #define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_WIDTH 1
1384 /* The mask used to set the ALT_RSTMGR_HDSKEN_FPGAMGRHSEN register field value. */
1385 #define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET_MSK 0x00000002
1386 /* The mask used to clear the ALT_RSTMGR_HDSKEN_FPGAMGRHSEN register field value. */
1387 #define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_CLR_MSK 0xfffffffd
1388 /* The reset value of the ALT_RSTMGR_HDSKEN_FPGAMGRHSEN register field. */
1389 #define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_RESET 0x0
1390 /* Extracts the ALT_RSTMGR_HDSKEN_FPGAMGRHSEN field value from a register. */
1391 #define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_GET(value) (((value) & 0x00000002) >> 1)
1392 /* Produces a ALT_RSTMGR_HDSKEN_FPGAMGRHSEN register field value suitable for setting the register. */
1393 #define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET(value) (((value) << 1) & 0x00000002)
1394 
1395 /*
1396  * Field : FPGA Handshake Enable - fpgahsen
1397  *
1398  * This field controls whether to perform handshake with FPGA before asserting warm
1399  * reset.
1400  *
1401  * If set to 1, the Reset Manager makes a request to the FPGAbefore asserting warm
1402  * reset signals. However if FPGA is already in warm reset state, the handshake is
1403  * not performed.
1404  *
1405  * If set to 0, the handshake is not performed
1406  *
1407  * Field Access Macros:
1408  *
1409  */
1410 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKEN_FPGAHSEN register field. */
1411 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_LSB 2
1412 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKEN_FPGAHSEN register field. */
1413 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_MSB 2
1414 /* The width in bits of the ALT_RSTMGR_HDSKEN_FPGAHSEN register field. */
1415 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_WIDTH 1
1416 /* The mask used to set the ALT_RSTMGR_HDSKEN_FPGAHSEN register field value. */
1417 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK 0x00000004
1418 /* The mask used to clear the ALT_RSTMGR_HDSKEN_FPGAHSEN register field value. */
1419 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_CLR_MSK 0xfffffffb
1420 /* The reset value of the ALT_RSTMGR_HDSKEN_FPGAHSEN register field. */
1421 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_RESET 0x0
1422 /* Extracts the ALT_RSTMGR_HDSKEN_FPGAHSEN field value from a register. */
1423 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_GET(value) (((value) & 0x00000004) >> 2)
1424 /* Produces a ALT_RSTMGR_HDSKEN_FPGAHSEN register field value suitable for setting the register. */
1425 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET(value) (((value) << 2) & 0x00000004)
1426 
1427 /*
1428  * Field : ETR (Embedded Trace Router) Handshake Enable - etrstallen
1429  *
1430  * Software writes this field 1 to request to the ETR that it stalls its AXI master
1431  * to the L3 Interconnect.
1432  *
1433  * Software waits for the ETRSTALLACK to be 1 and then writes this field to 0.
1434  * Note that it is possible for the ETR to never assert ETRSTALLACK so software
1435  * should timeout if ETRSTALLACK is never asserted.
1436  *
1437  * Field Access Macros:
1438  *
1439  */
1440 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKEN_ETRSTALLEN register field. */
1441 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_LSB 3
1442 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKEN_ETRSTALLEN register field. */
1443 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_MSB 3
1444 /* The width in bits of the ALT_RSTMGR_HDSKEN_ETRSTALLEN register field. */
1445 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_WIDTH 1
1446 /* The mask used to set the ALT_RSTMGR_HDSKEN_ETRSTALLEN register field value. */
1447 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK 0x00000008
1448 /* The mask used to clear the ALT_RSTMGR_HDSKEN_ETRSTALLEN register field value. */
1449 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_CLR_MSK 0xfffffff7
1450 /* The reset value of the ALT_RSTMGR_HDSKEN_ETRSTALLEN register field. */
1451 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_RESET 0x0
1452 /* Extracts the ALT_RSTMGR_HDSKEN_ETRSTALLEN field value from a register. */
1453 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_GET(value) (((value) & 0x00000008) >> 3)
1454 /* Produces a ALT_RSTMGR_HDSKEN_ETRSTALLEN register field value suitable for setting the register. */
1455 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET(value) (((value) << 3) & 0x00000008)
1456 
1457 #ifndef __ASSEMBLY__
1458 /*
1459  * WARNING: The C register and register group struct declarations are provided for
1460  * convenience and illustrative purposes. They should, however, be used with
1461  * caution as the C language standard provides no guarantees about the alignment or
1462  * atomicity of device memory accesses. The recommended practice for writing
1463  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1464  * alt_write_word() functions.
1465  *
1466  * The struct declaration for register ALT_RSTMGR_HDSKEN.
1467  */
1468 struct ALT_RSTMGR_HDSKEN_s
1469 {
1470  uint32_t sdrselfrefen : 1; /* SDRAM Self-Refresh Enable */
1471  uint32_t fpgamgrhsen : 1; /* FPGA Manager Handshake Enable */
1472  uint32_t fpgahsen : 1; /* FPGA Handshake Enable */
1473  uint32_t etrstallen : 1; /* ETR (Embedded Trace Router) Handshake Enable */
1474  uint32_t : 28; /* *UNDEFINED* */
1475 };
1476 
1477 /* The typedef declaration for register ALT_RSTMGR_HDSKEN. */
1478 typedef volatile struct ALT_RSTMGR_HDSKEN_s ALT_RSTMGR_HDSKEN_t;
1479 #endif /* __ASSEMBLY__ */
1480 
1481 /* The reset value of the ALT_RSTMGR_HDSKEN register. */
1482 #define ALT_RSTMGR_HDSKEN_RESET 0x00100000
1483 /* The byte offset of the ALT_RSTMGR_HDSKEN register from the beginning of the component. */
1484 #define ALT_RSTMGR_HDSKEN_OFST 0x10
1485 
1486 /*
1487  * Register : Control Register - hdskreq
1488  *
1489  * The CTRL register is used by software to control reset behavior.It includes
1490  * fields for software to initiate the cold and warm reset, enable hardware
1491  * handshake with other modules before warm reset, and perform software handshake.
1492  * The software handshake sequence must match the hardware sequence. Software
1493  * mustde-assert the handshake request after asserting warm reset and before de-
1494  * assert the warm reset.
1495  *
1496  * Fields are only reset by a cold reset.
1497  *
1498  * Register Layout
1499  *
1500  * Bits | Access | Reset | Description
1501  * :-------|:-------|:--------|:------------------------------------------
1502  * [0] | RW | 0x0 | SDRAM Self-Refresh Request
1503  * [1] | RW | 0x0 | FPGA Manager Handshake Request
1504  * [2] | RW | 0x0 | FPGA Handshake Request
1505  * [3] | RW | 0x0 | ETR (Embedded Trace Router) Stall Request
1506  * [31:4] | ??? | Unknown | *UNDEFINED*
1507  *
1508  */
1509 /*
1510  * Field : SDRAM Self-Refresh Request - sdrselfrefreq
1511  *
1512  * Software writes this field 1 to request to the SDRAM Controller Subsystem that
1513  * it puts the SDRAM devices into self-refresh mode. This is done to preserve SDRAM
1514  * contents across a software warm reset.
1515  *
1516  * Software waits for the SDRSELFREFACK to be 1 and then writes this field to 0.
1517  * Note that it is possible for the SDRAM Controller Subsystem to never assert
1518  * SDRSELFREFACK so software should timeout if SDRSELFREFACK is never asserted.
1519  *
1520  * Field Access Macros:
1521  *
1522  */
1523 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ register field. */
1524 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_LSB 0
1525 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ register field. */
1526 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_MSB 0
1527 /* The width in bits of the ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ register field. */
1528 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_WIDTH 1
1529 /* The mask used to set the ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ register field value. */
1530 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_SET_MSK 0x00000001
1531 /* The mask used to clear the ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ register field value. */
1532 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_CLR_MSK 0xfffffffe
1533 /* The reset value of the ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ register field. */
1534 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_RESET 0x0
1535 /* Extracts the ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ field value from a register. */
1536 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_GET(value) (((value) & 0x00000001) >> 0)
1537 /* Produces a ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ register field value suitable for setting the register. */
1538 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_SET(value) (((value) << 0) & 0x00000001)
1539 
1540 /*
1541  * Field : FPGA Manager Handshake Request - fpgamgrhsreq
1542  *
1543  * Software writes this field 1 to request to the FPGA Manager to idle its output
1544  * clock.
1545  *
1546  * Software waits for the FPGAMGRHSACK to be 1 and then writes this field to 0.
1547  * Note that it is possible for the FPGA Manager to never assert FPGAMGRHSACK so
1548  * software should timeout in this case.
1549  *
1550  * Field Access Macros:
1551  *
1552  */
1553 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ register field. */
1554 #define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_LSB 1
1555 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ register field. */
1556 #define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_MSB 1
1557 /* The width in bits of the ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ register field. */
1558 #define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_WIDTH 1
1559 /* The mask used to set the ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ register field value. */
1560 #define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_SET_MSK 0x00000002
1561 /* The mask used to clear the ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ register field value. */
1562 #define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_CLR_MSK 0xfffffffd
1563 /* The reset value of the ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ register field. */
1564 #define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_RESET 0x0
1565 /* Extracts the ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ field value from a register. */
1566 #define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_GET(value) (((value) & 0x00000002) >> 1)
1567 /* Produces a ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ register field value suitable for setting the register. */
1568 #define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_SET(value) (((value) << 1) & 0x00000002)
1569 
1570 /*
1571  * Field : FPGA Handshake Request - fpgahsreq
1572  *
1573  * Software writes this field 1 to initiate handshake request to FPGA .
1574  *
1575  * Software waits for the FPGAHSACK to be active and then writes this field to 0.
1576  * Note that it is possible for the FPGA to never assert FPGAHSACK so software
1577  * should timeout in this case.
1578  *
1579  * Field Access Macros:
1580  *
1581  */
1582 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKREQ_FPGAHSREQ register field. */
1583 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_LSB 2
1584 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKREQ_FPGAHSREQ register field. */
1585 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_MSB 2
1586 /* The width in bits of the ALT_RSTMGR_HDSKREQ_FPGAHSREQ register field. */
1587 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_WIDTH 1
1588 /* The mask used to set the ALT_RSTMGR_HDSKREQ_FPGAHSREQ register field value. */
1589 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_SET_MSK 0x00000004
1590 /* The mask used to clear the ALT_RSTMGR_HDSKREQ_FPGAHSREQ register field value. */
1591 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_CLR_MSK 0xfffffffb
1592 /* The reset value of the ALT_RSTMGR_HDSKREQ_FPGAHSREQ register field. */
1593 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_RESET 0x0
1594 /* Extracts the ALT_RSTMGR_HDSKREQ_FPGAHSREQ field value from a register. */
1595 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_GET(value) (((value) & 0x00000004) >> 2)
1596 /* Produces a ALT_RSTMGR_HDSKREQ_FPGAHSREQ register field value suitable for setting the register. */
1597 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_SET(value) (((value) << 2) & 0x00000004)
1598 
1599 /*
1600  * Field : ETR (Embedded Trace Router) Stall Request - etrstallreq
1601  *
1602  * Software writes this field 1 to request to the ETR that it stalls its AXI master
1603  * to the L3 Interconnect.
1604  *
1605  * Software waits for the ETRSTALLACK to be 1 and then writes this field to 0.
1606  * Note that it is possible for the ETR to never assert ETRSTALLACK so software
1607  * should timeout if ETRSTALLACK is never asserted.
1608  *
1609  * Field Access Macros:
1610  *
1611  */
1612 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKREQ_ETRSTALLREQ register field. */
1613 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_LSB 3
1614 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKREQ_ETRSTALLREQ register field. */
1615 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_MSB 3
1616 /* The width in bits of the ALT_RSTMGR_HDSKREQ_ETRSTALLREQ register field. */
1617 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_WIDTH 1
1618 /* The mask used to set the ALT_RSTMGR_HDSKREQ_ETRSTALLREQ register field value. */
1619 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_SET_MSK 0x00000008
1620 /* The mask used to clear the ALT_RSTMGR_HDSKREQ_ETRSTALLREQ register field value. */
1621 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_CLR_MSK 0xfffffff7
1622 /* The reset value of the ALT_RSTMGR_HDSKREQ_ETRSTALLREQ register field. */
1623 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_RESET 0x0
1624 /* Extracts the ALT_RSTMGR_HDSKREQ_ETRSTALLREQ field value from a register. */
1625 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_GET(value) (((value) & 0x00000008) >> 3)
1626 /* Produces a ALT_RSTMGR_HDSKREQ_ETRSTALLREQ register field value suitable for setting the register. */
1627 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_SET(value) (((value) << 3) & 0x00000008)
1628 
1629 #ifndef __ASSEMBLY__
1630 /*
1631  * WARNING: The C register and register group struct declarations are provided for
1632  * convenience and illustrative purposes. They should, however, be used with
1633  * caution as the C language standard provides no guarantees about the alignment or
1634  * atomicity of device memory accesses. The recommended practice for writing
1635  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1636  * alt_write_word() functions.
1637  *
1638  * The struct declaration for register ALT_RSTMGR_HDSKREQ.
1639  */
1640 struct ALT_RSTMGR_HDSKREQ_s
1641 {
1642  uint32_t sdrselfrefreq : 1; /* SDRAM Self-Refresh Request */
1643  uint32_t fpgamgrhsreq : 1; /* FPGA Manager Handshake Request */
1644  uint32_t fpgahsreq : 1; /* FPGA Handshake Request */
1645  uint32_t etrstallreq : 1; /* ETR (Embedded Trace Router) Stall Request */
1646  uint32_t : 28; /* *UNDEFINED* */
1647 };
1648 
1649 /* The typedef declaration for register ALT_RSTMGR_HDSKREQ. */
1650 typedef volatile struct ALT_RSTMGR_HDSKREQ_s ALT_RSTMGR_HDSKREQ_t;
1651 #endif /* __ASSEMBLY__ */
1652 
1653 /* The reset value of the ALT_RSTMGR_HDSKREQ register. */
1654 #define ALT_RSTMGR_HDSKREQ_RESET 0x00100000
1655 /* The byte offset of the ALT_RSTMGR_HDSKREQ register from the beginning of the component. */
1656 #define ALT_RSTMGR_HDSKREQ_OFST 0x14
1657 
1658 /*
1659  * Register : Control Register - hdskack
1660  *
1661  * The CTRL register is used by software to control reset behavior.It includes
1662  * fields for software to initiate the cold and warm reset, enable hardware
1663  * handshake with other modules before warm reset, and perform software handshake.
1664  * The software handshake sequence must match the hardware sequence. Software
1665  * mustde-assert the handshake request after asserting warm reset and before de-
1666  * assert the warm reset.
1667  *
1668  * Fields are only reset by a cold reset.
1669  *
1670  * Register Layout
1671  *
1672  * Bits | Access | Reset | Description
1673  * :-------|:-------|:--------|:---------------------------------------------------
1674  * [0] | R | 0x0 | SDRAM Self-Refresh Acknowledge
1675  * [1] | R | 0x0 | FPGA Manager Handshake Acknowledge
1676  * [2] | R | 0x0 | FPGA Handshake Acknowledge
1677  * [3] | R | 0x0 | ETR (Embedded Trace Router) Stall Acknowledge
1678  * [7:4] | ??? | 0x0 | *UNDEFINED*
1679  * [8] | RW | 0x0 | ETR (Embedded Trace Router) Stall After Warm Reset
1680  * [31:9] | ??? | Unknown | *UNDEFINED*
1681  *
1682  */
1683 /*
1684  * Field : SDRAM Self-Refresh Acknowledge - sdrselfreqack
1685  *
1686  * This is the acknowlege for a SDRAM self-refresh mode request initiated by the
1687  * SDRSELFREFREQ field. A 1 indicates that the SDRAM Controller Subsystem has put
1688  * the SDRAM devices into self-refresh mode.
1689  *
1690  * Field Access Macros:
1691  *
1692  */
1693 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKACK_SDRSELFREQACK register field. */
1694 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_LSB 0
1695 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKACK_SDRSELFREQACK register field. */
1696 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_MSB 0
1697 /* The width in bits of the ALT_RSTMGR_HDSKACK_SDRSELFREQACK register field. */
1698 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_WIDTH 1
1699 /* The mask used to set the ALT_RSTMGR_HDSKACK_SDRSELFREQACK register field value. */
1700 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_SET_MSK 0x00000001
1701 /* The mask used to clear the ALT_RSTMGR_HDSKACK_SDRSELFREQACK register field value. */
1702 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_CLR_MSK 0xfffffffe
1703 /* The reset value of the ALT_RSTMGR_HDSKACK_SDRSELFREQACK register field. */
1704 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_RESET 0x0
1705 /* Extracts the ALT_RSTMGR_HDSKACK_SDRSELFREQACK field value from a register. */
1706 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_GET(value) (((value) & 0x00000001) >> 0)
1707 /* Produces a ALT_RSTMGR_HDSKACK_SDRSELFREQACK register field value suitable for setting the register. */
1708 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_SET(value) (((value) << 0) & 0x00000001)
1709 
1710 /*
1711  * Field : FPGA Manager Handshake Acknowledge - fpgamgrhsack
1712  *
1713  * This is the acknowlege (high active) that the FPGA manager has successfully
1714  * idled its output clock.
1715  *
1716  * Field Access Macros:
1717  *
1718  */
1719 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKACK_FPGAMGRHSACK register field. */
1720 #define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_LSB 1
1721 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKACK_FPGAMGRHSACK register field. */
1722 #define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_MSB 1
1723 /* The width in bits of the ALT_RSTMGR_HDSKACK_FPGAMGRHSACK register field. */
1724 #define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_WIDTH 1
1725 /* The mask used to set the ALT_RSTMGR_HDSKACK_FPGAMGRHSACK register field value. */
1726 #define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_SET_MSK 0x00000002
1727 /* The mask used to clear the ALT_RSTMGR_HDSKACK_FPGAMGRHSACK register field value. */
1728 #define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_CLR_MSK 0xfffffffd
1729 /* The reset value of the ALT_RSTMGR_HDSKACK_FPGAMGRHSACK register field. */
1730 #define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_RESET 0x0
1731 /* Extracts the ALT_RSTMGR_HDSKACK_FPGAMGRHSACK field value from a register. */
1732 #define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_GET(value) (((value) & 0x00000002) >> 1)
1733 /* Produces a ALT_RSTMGR_HDSKACK_FPGAMGRHSACK register field value suitable for setting the register. */
1734 #define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_SET(value) (((value) << 1) & 0x00000002)
1735 
1736 /*
1737  * Field : FPGA Handshake Acknowledge - fpgahsack
1738  *
1739  * This is the acknowlege (high active) that the FPGA handshake acknowledge has
1740  * been received by Reset Manager.
1741  *
1742  * Field Access Macros:
1743  *
1744  */
1745 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKACK_FPGAHSACK register field. */
1746 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_LSB 2
1747 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKACK_FPGAHSACK register field. */
1748 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_MSB 2
1749 /* The width in bits of the ALT_RSTMGR_HDSKACK_FPGAHSACK register field. */
1750 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_WIDTH 1
1751 /* The mask used to set the ALT_RSTMGR_HDSKACK_FPGAHSACK register field value. */
1752 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_SET_MSK 0x00000004
1753 /* The mask used to clear the ALT_RSTMGR_HDSKACK_FPGAHSACK register field value. */
1754 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_CLR_MSK 0xfffffffb
1755 /* The reset value of the ALT_RSTMGR_HDSKACK_FPGAHSACK register field. */
1756 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_RESET 0x0
1757 /* Extracts the ALT_RSTMGR_HDSKACK_FPGAHSACK field value from a register. */
1758 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_GET(value) (((value) & 0x00000004) >> 2)
1759 /* Produces a ALT_RSTMGR_HDSKACK_FPGAHSACK register field value suitable for setting the register. */
1760 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_SET(value) (((value) << 2) & 0x00000004)
1761 
1762 /*
1763  * Field : ETR (Embedded Trace Router) Stall Acknowledge - etrstallack
1764  *
1765  * This is the acknowlege for a ETR AXI master stall initiated by the ETRSTALLREQ
1766  * field. A 1 indicates that the ETR has stalled its AXI master
1767  *
1768  * Field Access Macros:
1769  *
1770  */
1771 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKACK_ETRSTALLACK register field. */
1772 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_LSB 3
1773 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKACK_ETRSTALLACK register field. */
1774 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_MSB 3
1775 /* The width in bits of the ALT_RSTMGR_HDSKACK_ETRSTALLACK register field. */
1776 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_WIDTH 1
1777 /* The mask used to set the ALT_RSTMGR_HDSKACK_ETRSTALLACK register field value. */
1778 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_SET_MSK 0x00000008
1779 /* The mask used to clear the ALT_RSTMGR_HDSKACK_ETRSTALLACK register field value. */
1780 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_CLR_MSK 0xfffffff7
1781 /* The reset value of the ALT_RSTMGR_HDSKACK_ETRSTALLACK register field. */
1782 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_RESET 0x0
1783 /* Extracts the ALT_RSTMGR_HDSKACK_ETRSTALLACK field value from a register. */
1784 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_GET(value) (((value) & 0x00000008) >> 3)
1785 /* Produces a ALT_RSTMGR_HDSKACK_ETRSTALLACK register field value suitable for setting the register. */
1786 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_SET(value) (((value) << 3) & 0x00000008)
1787 
1788 /*
1789  * Field : ETR (Embedded Trace Router) Stall After Warm Reset - etrstallwarmrst
1790  *
1791  * If a warm reset occurs and ETRSTALLEN is 1, hardware sets this bit to 1 to
1792  * indicate that the stall of the ETR AXI master is pending. Hardware leaves the
1793  * ETR stalled until software clears this field by writing it with 1. Software must
1794  * only clear this field when it is ready to have the ETR AXI master start making
1795  * AXI requests to write trace data.
1796  *
1797  * Field Access Macros:
1798  *
1799  */
1800 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST register field. */
1801 #define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_LSB 8
1802 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST register field. */
1803 #define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_MSB 8
1804 /* The width in bits of the ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST register field. */
1805 #define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_WIDTH 1
1806 /* The mask used to set the ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST register field value. */
1807 #define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_SET_MSK 0x00000100
1808 /* The mask used to clear the ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST register field value. */
1809 #define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_CLR_MSK 0xfffffeff
1810 /* The reset value of the ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST register field. */
1811 #define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_RESET 0x0
1812 /* Extracts the ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST field value from a register. */
1813 #define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_GET(value) (((value) & 0x00000100) >> 8)
1814 /* Produces a ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST register field value suitable for setting the register. */
1815 #define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_SET(value) (((value) << 8) & 0x00000100)
1816 
1817 #ifndef __ASSEMBLY__
1818 /*
1819  * WARNING: The C register and register group struct declarations are provided for
1820  * convenience and illustrative purposes. They should, however, be used with
1821  * caution as the C language standard provides no guarantees about the alignment or
1822  * atomicity of device memory accesses. The recommended practice for writing
1823  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1824  * alt_write_word() functions.
1825  *
1826  * The struct declaration for register ALT_RSTMGR_HDSKACK.
1827  */
1828 struct ALT_RSTMGR_HDSKACK_s
1829 {
1830  const uint32_t sdrselfreqack : 1; /* SDRAM Self-Refresh Acknowledge */
1831  const uint32_t fpgamgrhsack : 1; /* FPGA Manager Handshake Acknowledge */
1832  const uint32_t fpgahsack : 1; /* FPGA Handshake Acknowledge */
1833  const uint32_t etrstallack : 1; /* ETR (Embedded Trace Router) Stall Acknowledge */
1834  uint32_t : 4; /* *UNDEFINED* */
1835  uint32_t etrstallwarmrst : 1; /* ETR (Embedded Trace Router) Stall After Warm Reset */
1836  uint32_t : 23; /* *UNDEFINED* */
1837 };
1838 
1839 /* The typedef declaration for register ALT_RSTMGR_HDSKACK. */
1840 typedef volatile struct ALT_RSTMGR_HDSKACK_s ALT_RSTMGR_HDSKACK_t;
1841 #endif /* __ASSEMBLY__ */
1842 
1843 /* The reset value of the ALT_RSTMGR_HDSKACK register. */
1844 #define ALT_RSTMGR_HDSKACK_RESET 0x00100000
1845 /* The byte offset of the ALT_RSTMGR_HDSKACK register from the beginning of the component. */
1846 #define ALT_RSTMGR_HDSKACK_OFST 0x18
1847 
1848 /*
1849  * Register : Reset Cycles Count Register - counts
1850  *
1851  * The COUNTS register is used by software to control reset behavior.It includes
1852  * fields for software to control the behavior of the warm reset and nRST pin.
1853  *
1854  * Fields are only reset by a cold reset.
1855  *
1856  * Register Layout
1857  *
1858  * Bits | Access | Reset | Description
1859  * :--------|:-------|:------|:-------------------------------
1860  * [19:0] | RW | 0x800 | nRST Pin Count
1861  * [23:20] | ??? | 0x0 | *UNDEFINED*
1862  * [31:24] | RW | 0x80 | Warm reset release delay count
1863  *
1864  */
1865 /*
1866  * Field : nRST Pin Count - nrstcnt
1867  *
1868  * The Reset Manager pulls down the nRST pin on a warm reset for the number of
1869  * cycles specified in this register. A value of 0x0 prevents the Reset Manager
1870  * from pulling down the nRST pin.
1871  *
1872  * Field Access Macros:
1873  *
1874  */
1875 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */
1876 #define ALT_RSTMGR_COUNTS_NRSTCNT_LSB 0
1877 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */
1878 #define ALT_RSTMGR_COUNTS_NRSTCNT_MSB 19
1879 /* The width in bits of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */
1880 #define ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH 20
1881 /* The mask used to set the ALT_RSTMGR_COUNTS_NRSTCNT register field value. */
1882 #define ALT_RSTMGR_COUNTS_NRSTCNT_SET_MSK 0x000fffff
1883 /* The mask used to clear the ALT_RSTMGR_COUNTS_NRSTCNT register field value. */
1884 #define ALT_RSTMGR_COUNTS_NRSTCNT_CLR_MSK 0xfff00000
1885 /* The reset value of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */
1886 #define ALT_RSTMGR_COUNTS_NRSTCNT_RESET 0x800
1887 /* Extracts the ALT_RSTMGR_COUNTS_NRSTCNT field value from a register. */
1888 #define ALT_RSTMGR_COUNTS_NRSTCNT_GET(value) (((value) & 0x000fffff) >> 0)
1889 /* Produces a ALT_RSTMGR_COUNTS_NRSTCNT register field value suitable for setting the register. */
1890 #define ALT_RSTMGR_COUNTS_NRSTCNT_SET(value) (((value) << 0) & 0x000fffff)
1891 
1892 /*
1893  * Field : Warm reset release delay count - warmrstcycles
1894  *
1895  * On a warm reset, the Reset Manager releases the reset to the Clock Manager, and
1896  * then waits for the number of cycles specified in this register before releasing
1897  * the rest of the hardware controlled resets.
1898  *
1899  * Field Access Macros:
1900  *
1901  */
1902 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */
1903 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_LSB 24
1904 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */
1905 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_MSB 31
1906 /* The width in bits of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */
1907 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH 8
1908 /* The mask used to set the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value. */
1909 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET_MSK 0xff000000
1910 /* The mask used to clear the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value. */
1911 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_CLR_MSK 0x00ffffff
1912 /* The reset value of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */
1913 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_RESET 0x80
1914 /* Extracts the ALT_RSTMGR_COUNTS_WARMRSTCYCLES field value from a register. */
1915 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_GET(value) (((value) & 0xff000000) >> 24)
1916 /* Produces a ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value suitable for setting the register. */
1917 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET(value) (((value) << 24) & 0xff000000)
1918 
1919 #ifndef __ASSEMBLY__
1920 /*
1921  * WARNING: The C register and register group struct declarations are provided for
1922  * convenience and illustrative purposes. They should, however, be used with
1923  * caution as the C language standard provides no guarantees about the alignment or
1924  * atomicity of device memory accesses. The recommended practice for writing
1925  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1926  * alt_write_word() functions.
1927  *
1928  * The struct declaration for register ALT_RSTMGR_COUNTS.
1929  */
1930 struct ALT_RSTMGR_COUNTS_s
1931 {
1932  uint32_t nrstcnt : 20; /* nRST Pin Count */
1933  uint32_t : 4; /* *UNDEFINED* */
1934  uint32_t warmrstcycles : 8; /* Warm reset release delay count */
1935 };
1936 
1937 /* The typedef declaration for register ALT_RSTMGR_COUNTS. */
1938 typedef volatile struct ALT_RSTMGR_COUNTS_s ALT_RSTMGR_COUNTS_t;
1939 #endif /* __ASSEMBLY__ */
1940 
1941 /* The reset value of the ALT_RSTMGR_COUNTS register. */
1942 #define ALT_RSTMGR_COUNTS_RESET 0x80000800
1943 /* The byte offset of the ALT_RSTMGR_COUNTS register from the beginning of the component. */
1944 #define ALT_RSTMGR_COUNTS_OFST 0x1c
1945 
1946 /*
1947  * Register : MPU Module Reset Register - mpumodrst
1948  *
1949  * The MPUMODRST register is used by software to trigger module resets (individual
1950  * module reset signals). Software explicitly asserts and de-asserts module reset
1951  * signals by writing bits in the appropriate *MODRST register. It is up to
1952  * software to ensure module reset signals are asserted for the appropriate length
1953  * of time and are de-asserted in the correct order. It is also up to software to
1954  * not assert a module reset signal that would prevent software from de-asserting
1955  * the module reset signal. For example, software should not assert the module
1956  * reset to the CPU executing the software.
1957  *
1958  * Software writes a bit to 1 to assert the module reset signal and to 0 to de-
1959  * assert the module reset signal.
1960  *
1961  * All fields except CPU1 are only reset by a cold reset. The CPU1 field is reset
1962  * by a cold reset. The CPU1 field is also reset by a warm reset if not masked by
1963  * the corresponding MPUWARMMASK field.
1964  *
1965  * Register Layout
1966  *
1967  * Bits | Access | Reset | Description
1968  * :-------|:-------|:------|:----------------
1969  * [0] | RW | 0x0 | CPU0
1970  * [1] | RW | 0x1 | CPU1
1971  * [2] | RW | 0x0 | Watchdogs
1972  * [3] | RW | 0x0 | SCU/Peripherals
1973  * [31:4] | ??? | 0x0 | *UNDEFINED*
1974  *
1975  */
1976 /*
1977  * Field : CPU0 - cpu0
1978  *
1979  * Resets Cortex-A9 CPU0 in MPU. Whe software changes this field from 0 to 1,
1980  * ittriggers the following sequence: 1. CPU0 reset is asserted. cpu0 clkoff is
1981  * de-asserted 2. after 32 osc1_clk cycles, cpu0 clkoff is asserted.
1982  *
1983  * When software changes this field from 1 to 0, it triggers the following
1984  * sequence: 1.CPU0 reset is de-asserted. 2. after 32 cycles, cpu0 clkoff is de-
1985  * asserted.
1986  *
1987  * Software needs to wait for at least 64 osc1_clk cycles between each change of
1988  * this field to keep the proper reset/clkoff sequence.
1989  *
1990  * Field Access Macros:
1991  *
1992  */
1993 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */
1994 #define ALT_RSTMGR_MPUMODRST_CPU0_LSB 0
1995 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */
1996 #define ALT_RSTMGR_MPUMODRST_CPU0_MSB 0
1997 /* The width in bits of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */
1998 #define ALT_RSTMGR_MPUMODRST_CPU0_WIDTH 1
1999 /* The mask used to set the ALT_RSTMGR_MPUMODRST_CPU0 register field value. */
2000 #define ALT_RSTMGR_MPUMODRST_CPU0_SET_MSK 0x00000001
2001 /* The mask used to clear the ALT_RSTMGR_MPUMODRST_CPU0 register field value. */
2002 #define ALT_RSTMGR_MPUMODRST_CPU0_CLR_MSK 0xfffffffe
2003 /* The reset value of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */
2004 #define ALT_RSTMGR_MPUMODRST_CPU0_RESET 0x0
2005 /* Extracts the ALT_RSTMGR_MPUMODRST_CPU0 field value from a register. */
2006 #define ALT_RSTMGR_MPUMODRST_CPU0_GET(value) (((value) & 0x00000001) >> 0)
2007 /* Produces a ALT_RSTMGR_MPUMODRST_CPU0 register field value suitable for setting the register. */
2008 #define ALT_RSTMGR_MPUMODRST_CPU0_SET(value) (((value) << 0) & 0x00000001)
2009 
2010 /*
2011  * Field : CPU1 - cpu1
2012  *
2013  * Resets Cortex-A9 CPU1 in MPU.
2014  *
2015  * It is reset to 1 on a cold or warm reset. This holds CPU1 in reset until
2016  * software is ready to release CPU1 from reset by writing 0 to this field.
2017  *
2018  * On single-core devices, writes to this field are ignored.On dual-core devices,
2019  * writes to this field trigger the same sequence as writes to the CPU0 field
2020  * (except the sequence is performed on CPU1).
2021  *
2022  * Field Access Macros:
2023  *
2024  */
2025 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */
2026 #define ALT_RSTMGR_MPUMODRST_CPU1_LSB 1
2027 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */
2028 #define ALT_RSTMGR_MPUMODRST_CPU1_MSB 1
2029 /* The width in bits of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */
2030 #define ALT_RSTMGR_MPUMODRST_CPU1_WIDTH 1
2031 /* The mask used to set the ALT_RSTMGR_MPUMODRST_CPU1 register field value. */
2032 #define ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK 0x00000002
2033 /* The mask used to clear the ALT_RSTMGR_MPUMODRST_CPU1 register field value. */
2034 #define ALT_RSTMGR_MPUMODRST_CPU1_CLR_MSK 0xfffffffd
2035 /* The reset value of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */
2036 #define ALT_RSTMGR_MPUMODRST_CPU1_RESET 0x1
2037 /* Extracts the ALT_RSTMGR_MPUMODRST_CPU1 field value from a register. */
2038 #define ALT_RSTMGR_MPUMODRST_CPU1_GET(value) (((value) & 0x00000002) >> 1)
2039 /* Produces a ALT_RSTMGR_MPUMODRST_CPU1 register field value suitable for setting the register. */
2040 #define ALT_RSTMGR_MPUMODRST_CPU1_SET(value) (((value) << 1) & 0x00000002)
2041 
2042 /*
2043  * Field : Watchdogs - wds
2044  *
2045  * Resets both per-CPU Watchdog Reset Status registers in MPU.
2046  *
2047  * Field Access Macros:
2048  *
2049  */
2050 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_WDS register field. */
2051 #define ALT_RSTMGR_MPUMODRST_WDS_LSB 2
2052 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_WDS register field. */
2053 #define ALT_RSTMGR_MPUMODRST_WDS_MSB 2
2054 /* The width in bits of the ALT_RSTMGR_MPUMODRST_WDS register field. */
2055 #define ALT_RSTMGR_MPUMODRST_WDS_WIDTH 1
2056 /* The mask used to set the ALT_RSTMGR_MPUMODRST_WDS register field value. */
2057 #define ALT_RSTMGR_MPUMODRST_WDS_SET_MSK 0x00000004
2058 /* The mask used to clear the ALT_RSTMGR_MPUMODRST_WDS register field value. */
2059 #define ALT_RSTMGR_MPUMODRST_WDS_CLR_MSK 0xfffffffb
2060 /* The reset value of the ALT_RSTMGR_MPUMODRST_WDS register field. */
2061 #define ALT_RSTMGR_MPUMODRST_WDS_RESET 0x0
2062 /* Extracts the ALT_RSTMGR_MPUMODRST_WDS field value from a register. */
2063 #define ALT_RSTMGR_MPUMODRST_WDS_GET(value) (((value) & 0x00000004) >> 2)
2064 /* Produces a ALT_RSTMGR_MPUMODRST_WDS register field value suitable for setting the register. */
2065 #define ALT_RSTMGR_MPUMODRST_WDS_SET(value) (((value) << 2) & 0x00000004)
2066 
2067 /*
2068  * Field : SCU/Peripherals - scuper
2069  *
2070  * Resets SCU and peripherals. Peripherals consist of the interrupt controller,
2071  * global timer, both per-CPU private timers, and both per-CPU watchdogs (except
2072  * for the Watchdog Reset Status registers).
2073  *
2074  * Field Access Macros:
2075  *
2076  */
2077 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */
2078 #define ALT_RSTMGR_MPUMODRST_SCUPER_LSB 3
2079 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */
2080 #define ALT_RSTMGR_MPUMODRST_SCUPER_MSB 3
2081 /* The width in bits of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */
2082 #define ALT_RSTMGR_MPUMODRST_SCUPER_WIDTH 1
2083 /* The mask used to set the ALT_RSTMGR_MPUMODRST_SCUPER register field value. */
2084 #define ALT_RSTMGR_MPUMODRST_SCUPER_SET_MSK 0x00000008
2085 /* The mask used to clear the ALT_RSTMGR_MPUMODRST_SCUPER register field value. */
2086 #define ALT_RSTMGR_MPUMODRST_SCUPER_CLR_MSK 0xfffffff7
2087 /* The reset value of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */
2088 #define ALT_RSTMGR_MPUMODRST_SCUPER_RESET 0x0
2089 /* Extracts the ALT_RSTMGR_MPUMODRST_SCUPER field value from a register. */
2090 #define ALT_RSTMGR_MPUMODRST_SCUPER_GET(value) (((value) & 0x00000008) >> 3)
2091 /* Produces a ALT_RSTMGR_MPUMODRST_SCUPER register field value suitable for setting the register. */
2092 #define ALT_RSTMGR_MPUMODRST_SCUPER_SET(value) (((value) << 3) & 0x00000008)
2093 
2094 #ifndef __ASSEMBLY__
2095 /*
2096  * WARNING: The C register and register group struct declarations are provided for
2097  * convenience and illustrative purposes. They should, however, be used with
2098  * caution as the C language standard provides no guarantees about the alignment or
2099  * atomicity of device memory accesses. The recommended practice for writing
2100  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2101  * alt_write_word() functions.
2102  *
2103  * The struct declaration for register ALT_RSTMGR_MPUMODRST.
2104  */
2105 struct ALT_RSTMGR_MPUMODRST_s
2106 {
2107  uint32_t cpu0 : 1; /* CPU0 */
2108  uint32_t cpu1 : 1; /* CPU1 */
2109  uint32_t wds : 1; /* Watchdogs */
2110  uint32_t scuper : 1; /* SCU/Peripherals */
2111  uint32_t : 28; /* *UNDEFINED* */
2112 };
2113 
2114 /* The typedef declaration for register ALT_RSTMGR_MPUMODRST. */
2115 typedef volatile struct ALT_RSTMGR_MPUMODRST_s ALT_RSTMGR_MPUMODRST_t;
2116 #endif /* __ASSEMBLY__ */
2117 
2118 /* The reset value of the ALT_RSTMGR_MPUMODRST register. */
2119 #define ALT_RSTMGR_MPUMODRST_RESET 0x00000002
2120 /* The byte offset of the ALT_RSTMGR_MPUMODRST register from the beginning of the component. */
2121 #define ALT_RSTMGR_MPUMODRST_OFST 0x20
2122 
2123 /*
2124  * Register : Peripheral 0 Module Reset Register - per0modrst
2125  *
2126  * The PER0MODRST register is used by software to trigger module resets for
2127  * Peripheral Group and Fast Peripheral Group. Regular Peripheral Group resets are
2128  * in the lower 2 bytes, and Fast Pheripheral Group resets are in the upper 2
2129  * bytes. Software explicitly asserts and de-asserts module reset signals by
2130  * writing bits in the appropriate *MODRST register. It is up to software to ensure
2131  * module reset signals are asserted for the appropriate length of time and are de-
2132  * asserted in the correct order. It is also up to software to not assert a module
2133  * reset signal that would prevent software from de-asserting the module reset
2134  * signal. For example, software should not assert the module reset to the CPU
2135  * executing the software.
2136  *
2137  * Software writes a bit to 1 to assert the module reset signal and to 0 to de-
2138  * assert the module reset signal.
2139  *
2140  * All fields are reset by a cold reset.All fields are also reset by a warm reset
2141  * if not masked by the corresponding PERWARMMASK field.
2142  *
2143  * The reset value of all fields is 1. This holds the corresponding module in reset
2144  * until software is ready to release the module from reset by writing 0 to its
2145  * field.
2146  *
2147  * Register Layout
2148  *
2149  * Bits | Access | Reset | Description
2150  * :-----|:-------|:------|:---------------
2151  * [0] | RW | 0x1 | EMAC0
2152  * [1] | RW | 0x1 | EMAC1
2153  * [2] | RW | 0x1 | EMAC2
2154  * [3] | RW | 0x1 | USB0
2155  * [4] | RW | 0x1 | USB1
2156  * [5] | RW | 0x1 | NAND Flash
2157  * [6] | RW | 0x1 | QSPI Flash
2158  * [7] | RW | 0x1 | SD/MMC
2159  * [8] | RW | 0x1 | EMAC0OCP
2160  * [9] | RW | 0x1 | EMAC1OCP
2161  * [10] | RW | 0x1 | EMAC2OCP
2162  * [11] | RW | 0x1 | USB0OCP
2163  * [12] | RW | 0x1 | USB1OCP
2164  * [13] | RW | 0x1 | NANDOCP
2165  * [14] | RW | 0x1 | QSPIOCP
2166  * [15] | RW | 0x1 | SDMMCOCP
2167  * [16] | RW | 0x1 | DMA Controller
2168  * [17] | RW | 0x1 | SPIM0
2169  * [18] | RW | 0x1 | SPIM1
2170  * [19] | RW | 0x1 | SPIS0
2171  * [20] | RW | 0x1 | SPIS1
2172  * [21] | RW | 0x1 | DMAOCP
2173  * [22] | RW | 0x1 | EMAC PTP
2174  * [23] | ??? | 0x0 | *UNDEFINED*
2175  * [24] | RW | 0x1 | FPGA DMA0
2176  * [25] | RW | 0x1 | FPGA DMA1
2177  * [26] | RW | 0x1 | FPGA DMA2
2178  * [27] | RW | 0x1 | FPGA DMA3
2179  * [28] | RW | 0x1 | FPGA DMA4
2180  * [29] | RW | 0x1 | FPGA DMA5
2181  * [30] | RW | 0x1 | FPGA DMA6
2182  * [31] | RW | 0x1 | FPGA DMA7
2183  *
2184  */
2185 /*
2186  * Field : EMAC0 - emac0
2187  *
2188  * Resets EMAC0
2189  *
2190  * Field Access Macros:
2191  *
2192  */
2193 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_EMAC0 register field. */
2194 #define ALT_RSTMGR_PER0MODRST_EMAC0_LSB 0
2195 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_EMAC0 register field. */
2196 #define ALT_RSTMGR_PER0MODRST_EMAC0_MSB 0
2197 /* The width in bits of the ALT_RSTMGR_PER0MODRST_EMAC0 register field. */
2198 #define ALT_RSTMGR_PER0MODRST_EMAC0_WIDTH 1
2199 /* The mask used to set the ALT_RSTMGR_PER0MODRST_EMAC0 register field value. */
2200 #define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK 0x00000001
2201 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_EMAC0 register field value. */
2202 #define ALT_RSTMGR_PER0MODRST_EMAC0_CLR_MSK 0xfffffffe
2203 /* The reset value of the ALT_RSTMGR_PER0MODRST_EMAC0 register field. */
2204 #define ALT_RSTMGR_PER0MODRST_EMAC0_RESET 0x1
2205 /* Extracts the ALT_RSTMGR_PER0MODRST_EMAC0 field value from a register. */
2206 #define ALT_RSTMGR_PER0MODRST_EMAC0_GET(value) (((value) & 0x00000001) >> 0)
2207 /* Produces a ALT_RSTMGR_PER0MODRST_EMAC0 register field value suitable for setting the register. */
2208 #define ALT_RSTMGR_PER0MODRST_EMAC0_SET(value) (((value) << 0) & 0x00000001)
2209 
2210 /*
2211  * Field : EMAC1 - emac1
2212  *
2213  * Resets EMAC1
2214  *
2215  * Field Access Macros:
2216  *
2217  */
2218 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_EMAC1 register field. */
2219 #define ALT_RSTMGR_PER0MODRST_EMAC1_LSB 1
2220 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_EMAC1 register field. */
2221 #define ALT_RSTMGR_PER0MODRST_EMAC1_MSB 1
2222 /* The width in bits of the ALT_RSTMGR_PER0MODRST_EMAC1 register field. */
2223 #define ALT_RSTMGR_PER0MODRST_EMAC1_WIDTH 1
2224 /* The mask used to set the ALT_RSTMGR_PER0MODRST_EMAC1 register field value. */
2225 #define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK 0x00000002
2226 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_EMAC1 register field value. */
2227 #define ALT_RSTMGR_PER0MODRST_EMAC1_CLR_MSK 0xfffffffd
2228 /* The reset value of the ALT_RSTMGR_PER0MODRST_EMAC1 register field. */
2229 #define ALT_RSTMGR_PER0MODRST_EMAC1_RESET 0x1
2230 /* Extracts the ALT_RSTMGR_PER0MODRST_EMAC1 field value from a register. */
2231 #define ALT_RSTMGR_PER0MODRST_EMAC1_GET(value) (((value) & 0x00000002) >> 1)
2232 /* Produces a ALT_RSTMGR_PER0MODRST_EMAC1 register field value suitable for setting the register. */
2233 #define ALT_RSTMGR_PER0MODRST_EMAC1_SET(value) (((value) << 1) & 0x00000002)
2234 
2235 /*
2236  * Field : EMAC2 - emac2
2237  *
2238  * Resets EMAC2
2239  *
2240  * Field Access Macros:
2241  *
2242  */
2243 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_EMAC2 register field. */
2244 #define ALT_RSTMGR_PER0MODRST_EMAC2_LSB 2
2245 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_EMAC2 register field. */
2246 #define ALT_RSTMGR_PER0MODRST_EMAC2_MSB 2
2247 /* The width in bits of the ALT_RSTMGR_PER0MODRST_EMAC2 register field. */
2248 #define ALT_RSTMGR_PER0MODRST_EMAC2_WIDTH 1
2249 /* The mask used to set the ALT_RSTMGR_PER0MODRST_EMAC2 register field value. */
2250 #define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK 0x00000004
2251 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_EMAC2 register field value. */
2252 #define ALT_RSTMGR_PER0MODRST_EMAC2_CLR_MSK 0xfffffffb
2253 /* The reset value of the ALT_RSTMGR_PER0MODRST_EMAC2 register field. */
2254 #define ALT_RSTMGR_PER0MODRST_EMAC2_RESET 0x1
2255 /* Extracts the ALT_RSTMGR_PER0MODRST_EMAC2 field value from a register. */
2256 #define ALT_RSTMGR_PER0MODRST_EMAC2_GET(value) (((value) & 0x00000004) >> 2)
2257 /* Produces a ALT_RSTMGR_PER0MODRST_EMAC2 register field value suitable for setting the register. */
2258 #define ALT_RSTMGR_PER0MODRST_EMAC2_SET(value) (((value) << 2) & 0x00000004)
2259 
2260 /*
2261  * Field : USB0 - usb0
2262  *
2263  * Resets USB0
2264  *
2265  * Field Access Macros:
2266  *
2267  */
2268 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_USB0 register field. */
2269 #define ALT_RSTMGR_PER0MODRST_USB0_LSB 3
2270 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_USB0 register field. */
2271 #define ALT_RSTMGR_PER0MODRST_USB0_MSB 3
2272 /* The width in bits of the ALT_RSTMGR_PER0MODRST_USB0 register field. */
2273 #define ALT_RSTMGR_PER0MODRST_USB0_WIDTH 1
2274 /* The mask used to set the ALT_RSTMGR_PER0MODRST_USB0 register field value. */
2275 #define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK 0x00000008
2276 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_USB0 register field value. */
2277 #define ALT_RSTMGR_PER0MODRST_USB0_CLR_MSK 0xfffffff7
2278 /* The reset value of the ALT_RSTMGR_PER0MODRST_USB0 register field. */
2279 #define ALT_RSTMGR_PER0MODRST_USB0_RESET 0x1
2280 /* Extracts the ALT_RSTMGR_PER0MODRST_USB0 field value from a register. */
2281 #define ALT_RSTMGR_PER0MODRST_USB0_GET(value) (((value) & 0x00000008) >> 3)
2282 /* Produces a ALT_RSTMGR_PER0MODRST_USB0 register field value suitable for setting the register. */
2283 #define ALT_RSTMGR_PER0MODRST_USB0_SET(value) (((value) << 3) & 0x00000008)
2284 
2285 /*
2286  * Field : USB1 - usb1
2287  *
2288  * Resets USB1
2289  *
2290  * Field Access Macros:
2291  *
2292  */
2293 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_USB1 register field. */
2294 #define ALT_RSTMGR_PER0MODRST_USB1_LSB 4
2295 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_USB1 register field. */
2296 #define ALT_RSTMGR_PER0MODRST_USB1_MSB 4
2297 /* The width in bits of the ALT_RSTMGR_PER0MODRST_USB1 register field. */
2298 #define ALT_RSTMGR_PER0MODRST_USB1_WIDTH 1
2299 /* The mask used to set the ALT_RSTMGR_PER0MODRST_USB1 register field value. */
2300 #define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK 0x00000010
2301 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_USB1 register field value. */
2302 #define ALT_RSTMGR_PER0MODRST_USB1_CLR_MSK 0xffffffef
2303 /* The reset value of the ALT_RSTMGR_PER0MODRST_USB1 register field. */
2304 #define ALT_RSTMGR_PER0MODRST_USB1_RESET 0x1
2305 /* Extracts the ALT_RSTMGR_PER0MODRST_USB1 field value from a register. */
2306 #define ALT_RSTMGR_PER0MODRST_USB1_GET(value) (((value) & 0x00000010) >> 4)
2307 /* Produces a ALT_RSTMGR_PER0MODRST_USB1 register field value suitable for setting the register. */
2308 #define ALT_RSTMGR_PER0MODRST_USB1_SET(value) (((value) << 4) & 0x00000010)
2309 
2310 /*
2311  * Field : NAND Flash - nand
2312  *
2313  * Resets NAND flash controller
2314  *
2315  * Field Access Macros:
2316  *
2317  */
2318 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_NAND register field. */
2319 #define ALT_RSTMGR_PER0MODRST_NAND_LSB 5
2320 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_NAND register field. */
2321 #define ALT_RSTMGR_PER0MODRST_NAND_MSB 5
2322 /* The width in bits of the ALT_RSTMGR_PER0MODRST_NAND register field. */
2323 #define ALT_RSTMGR_PER0MODRST_NAND_WIDTH 1
2324 /* The mask used to set the ALT_RSTMGR_PER0MODRST_NAND register field value. */
2325 #define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK 0x00000020
2326 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_NAND register field value. */
2327 #define ALT_RSTMGR_PER0MODRST_NAND_CLR_MSK 0xffffffdf
2328 /* The reset value of the ALT_RSTMGR_PER0MODRST_NAND register field. */
2329 #define ALT_RSTMGR_PER0MODRST_NAND_RESET 0x1
2330 /* Extracts the ALT_RSTMGR_PER0MODRST_NAND field value from a register. */
2331 #define ALT_RSTMGR_PER0MODRST_NAND_GET(value) (((value) & 0x00000020) >> 5)
2332 /* Produces a ALT_RSTMGR_PER0MODRST_NAND register field value suitable for setting the register. */
2333 #define ALT_RSTMGR_PER0MODRST_NAND_SET(value) (((value) << 5) & 0x00000020)
2334 
2335 /*
2336  * Field : QSPI Flash - qspi
2337  *
2338  * Resets QSPI flash controller
2339  *
2340  * Field Access Macros:
2341  *
2342  */
2343 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_QSPI register field. */
2344 #define ALT_RSTMGR_PER0MODRST_QSPI_LSB 6
2345 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_QSPI register field. */
2346 #define ALT_RSTMGR_PER0MODRST_QSPI_MSB 6
2347 /* The width in bits of the ALT_RSTMGR_PER0MODRST_QSPI register field. */
2348 #define ALT_RSTMGR_PER0MODRST_QSPI_WIDTH 1
2349 /* The mask used to set the ALT_RSTMGR_PER0MODRST_QSPI register field value. */
2350 #define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK 0x00000040
2351 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_QSPI register field value. */
2352 #define ALT_RSTMGR_PER0MODRST_QSPI_CLR_MSK 0xffffffbf
2353 /* The reset value of the ALT_RSTMGR_PER0MODRST_QSPI register field. */
2354 #define ALT_RSTMGR_PER0MODRST_QSPI_RESET 0x1
2355 /* Extracts the ALT_RSTMGR_PER0MODRST_QSPI field value from a register. */
2356 #define ALT_RSTMGR_PER0MODRST_QSPI_GET(value) (((value) & 0x00000040) >> 6)
2357 /* Produces a ALT_RSTMGR_PER0MODRST_QSPI register field value suitable for setting the register. */
2358 #define ALT_RSTMGR_PER0MODRST_QSPI_SET(value) (((value) << 6) & 0x00000040)
2359 
2360 /*
2361  * Field : SD/MMC - sdmmc
2362  *
2363  * Resets SD/MMC controller
2364  *
2365  * Field Access Macros:
2366  *
2367  */
2368 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_SDMMC register field. */
2369 #define ALT_RSTMGR_PER0MODRST_SDMMC_LSB 7
2370 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_SDMMC register field. */
2371 #define ALT_RSTMGR_PER0MODRST_SDMMC_MSB 7
2372 /* The width in bits of the ALT_RSTMGR_PER0MODRST_SDMMC register field. */
2373 #define ALT_RSTMGR_PER0MODRST_SDMMC_WIDTH 1
2374 /* The mask used to set the ALT_RSTMGR_PER0MODRST_SDMMC register field value. */
2375 #define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK 0x00000080
2376 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_SDMMC register field value. */
2377 #define ALT_RSTMGR_PER0MODRST_SDMMC_CLR_MSK 0xffffff7f
2378 /* The reset value of the ALT_RSTMGR_PER0MODRST_SDMMC register field. */
2379 #define ALT_RSTMGR_PER0MODRST_SDMMC_RESET 0x1
2380 /* Extracts the ALT_RSTMGR_PER0MODRST_SDMMC field value from a register. */
2381 #define ALT_RSTMGR_PER0MODRST_SDMMC_GET(value) (((value) & 0x00000080) >> 7)
2382 /* Produces a ALT_RSTMGR_PER0MODRST_SDMMC register field value suitable for setting the register. */
2383 #define ALT_RSTMGR_PER0MODRST_SDMMC_SET(value) (((value) << 7) & 0x00000080)
2384 
2385 /*
2386  * Field : EMAC0OCP - emac0ocp
2387  *
2388  * Resets EMAC0 ECC OCP DIagnostics modules.
2389  *
2390  * Field Access Macros:
2391  *
2392  */
2393 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_EMAC0OCP register field. */
2394 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_LSB 8
2395 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_EMAC0OCP register field. */
2396 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_MSB 8
2397 /* The width in bits of the ALT_RSTMGR_PER0MODRST_EMAC0OCP register field. */
2398 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_WIDTH 1
2399 /* The mask used to set the ALT_RSTMGR_PER0MODRST_EMAC0OCP register field value. */
2400 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_SET_MSK 0x00000100
2401 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_EMAC0OCP register field value. */
2402 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_CLR_MSK 0xfffffeff
2403 /* The reset value of the ALT_RSTMGR_PER0MODRST_EMAC0OCP register field. */
2404 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_RESET 0x1
2405 /* Extracts the ALT_RSTMGR_PER0MODRST_EMAC0OCP field value from a register. */
2406 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_GET(value) (((value) & 0x00000100) >> 8)
2407 /* Produces a ALT_RSTMGR_PER0MODRST_EMAC0OCP register field value suitable for setting the register. */
2408 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_SET(value) (((value) << 8) & 0x00000100)
2409 
2410 /*
2411  * Field : EMAC1OCP - emac1ocp
2412  *
2413  * Resets EMAC1 ECC OCP DIagnostics modules.
2414  *
2415  * Field Access Macros:
2416  *
2417  */
2418 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_EMAC1OCP register field. */
2419 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_LSB 9
2420 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_EMAC1OCP register field. */
2421 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_MSB 9
2422 /* The width in bits of the ALT_RSTMGR_PER0MODRST_EMAC1OCP register field. */
2423 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_WIDTH 1
2424 /* The mask used to set the ALT_RSTMGR_PER0MODRST_EMAC1OCP register field value. */
2425 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_SET_MSK 0x00000200
2426 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_EMAC1OCP register field value. */
2427 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_CLR_MSK 0xfffffdff
2428 /* The reset value of the ALT_RSTMGR_PER0MODRST_EMAC1OCP register field. */
2429 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_RESET 0x1
2430 /* Extracts the ALT_RSTMGR_PER0MODRST_EMAC1OCP field value from a register. */
2431 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_GET(value) (((value) & 0x00000200) >> 9)
2432 /* Produces a ALT_RSTMGR_PER0MODRST_EMAC1OCP register field value suitable for setting the register. */
2433 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_SET(value) (((value) << 9) & 0x00000200)
2434 
2435 /*
2436  * Field : EMAC2OCP - emac2ocp
2437  *
2438  * Resets EMAC0 ECC OCP DIagnostics modules.
2439  *
2440  * Field Access Macros:
2441  *
2442  */
2443 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_EMAC2OCP register field. */
2444 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_LSB 10
2445 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_EMAC2OCP register field. */
2446 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_MSB 10
2447 /* The width in bits of the ALT_RSTMGR_PER0MODRST_EMAC2OCP register field. */
2448 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_WIDTH 1
2449 /* The mask used to set the ALT_RSTMGR_PER0MODRST_EMAC2OCP register field value. */
2450 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_SET_MSK 0x00000400
2451 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_EMAC2OCP register field value. */
2452 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_CLR_MSK 0xfffffbff
2453 /* The reset value of the ALT_RSTMGR_PER0MODRST_EMAC2OCP register field. */
2454 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_RESET 0x1
2455 /* Extracts the ALT_RSTMGR_PER0MODRST_EMAC2OCP field value from a register. */
2456 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_GET(value) (((value) & 0x00000400) >> 10)
2457 /* Produces a ALT_RSTMGR_PER0MODRST_EMAC2OCP register field value suitable for setting the register. */
2458 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_SET(value) (((value) << 10) & 0x00000400)
2459 
2460 /*
2461  * Field : USB0OCP - usb0ocp
2462  *
2463  * Resets USB0 ECC OCP DIagnostics modules.
2464  *
2465  * Field Access Macros:
2466  *
2467  */
2468 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_USB0OCP register field. */
2469 #define ALT_RSTMGR_PER0MODRST_USB0OCP_LSB 11
2470 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_USB0OCP register field. */
2471 #define ALT_RSTMGR_PER0MODRST_USB0OCP_MSB 11
2472 /* The width in bits of the ALT_RSTMGR_PER0MODRST_USB0OCP register field. */
2473 #define ALT_RSTMGR_PER0MODRST_USB0OCP_WIDTH 1
2474 /* The mask used to set the ALT_RSTMGR_PER0MODRST_USB0OCP register field value. */
2475 #define ALT_RSTMGR_PER0MODRST_USB0OCP_SET_MSK 0x00000800
2476 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_USB0OCP register field value. */
2477 #define ALT_RSTMGR_PER0MODRST_USB0OCP_CLR_MSK 0xfffff7ff
2478 /* The reset value of the ALT_RSTMGR_PER0MODRST_USB0OCP register field. */
2479 #define ALT_RSTMGR_PER0MODRST_USB0OCP_RESET 0x1
2480 /* Extracts the ALT_RSTMGR_PER0MODRST_USB0OCP field value from a register. */
2481 #define ALT_RSTMGR_PER0MODRST_USB0OCP_GET(value) (((value) & 0x00000800) >> 11)
2482 /* Produces a ALT_RSTMGR_PER0MODRST_USB0OCP register field value suitable for setting the register. */
2483 #define ALT_RSTMGR_PER0MODRST_USB0OCP_SET(value) (((value) << 11) & 0x00000800)
2484 
2485 /*
2486  * Field : USB1OCP - usb1ocp
2487  *
2488  * Resets USB1 ECC OCP DIagnostics modules.
2489  *
2490  * Field Access Macros:
2491  *
2492  */
2493 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_USB1OCP register field. */
2494 #define ALT_RSTMGR_PER0MODRST_USB1OCP_LSB 12
2495 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_USB1OCP register field. */
2496 #define ALT_RSTMGR_PER0MODRST_USB1OCP_MSB 12
2497 /* The width in bits of the ALT_RSTMGR_PER0MODRST_USB1OCP register field. */
2498 #define ALT_RSTMGR_PER0MODRST_USB1OCP_WIDTH 1
2499 /* The mask used to set the ALT_RSTMGR_PER0MODRST_USB1OCP register field value. */
2500 #define ALT_RSTMGR_PER0MODRST_USB1OCP_SET_MSK 0x00001000
2501 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_USB1OCP register field value. */
2502 #define ALT_RSTMGR_PER0MODRST_USB1OCP_CLR_MSK 0xffffefff
2503 /* The reset value of the ALT_RSTMGR_PER0MODRST_USB1OCP register field. */
2504 #define ALT_RSTMGR_PER0MODRST_USB1OCP_RESET 0x1
2505 /* Extracts the ALT_RSTMGR_PER0MODRST_USB1OCP field value from a register. */
2506 #define ALT_RSTMGR_PER0MODRST_USB1OCP_GET(value) (((value) & 0x00001000) >> 12)
2507 /* Produces a ALT_RSTMGR_PER0MODRST_USB1OCP register field value suitable for setting the register. */
2508 #define ALT_RSTMGR_PER0MODRST_USB1OCP_SET(value) (((value) << 12) & 0x00001000)
2509 
2510 /*
2511  * Field : NANDOCP - nandocp
2512  *
2513  * Resets NAND ECC OCP DIagnostics modules.
2514  *
2515  * Field Access Macros:
2516  *
2517  */
2518 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_NANDOCP register field. */
2519 #define ALT_RSTMGR_PER0MODRST_NANDOCP_LSB 13
2520 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_NANDOCP register field. */
2521 #define ALT_RSTMGR_PER0MODRST_NANDOCP_MSB 13
2522 /* The width in bits of the ALT_RSTMGR_PER0MODRST_NANDOCP register field. */
2523 #define ALT_RSTMGR_PER0MODRST_NANDOCP_WIDTH 1
2524 /* The mask used to set the ALT_RSTMGR_PER0MODRST_NANDOCP register field value. */
2525 #define ALT_RSTMGR_PER0MODRST_NANDOCP_SET_MSK 0x00002000
2526 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_NANDOCP register field value. */
2527 #define ALT_RSTMGR_PER0MODRST_NANDOCP_CLR_MSK 0xffffdfff
2528 /* The reset value of the ALT_RSTMGR_PER0MODRST_NANDOCP register field. */
2529 #define ALT_RSTMGR_PER0MODRST_NANDOCP_RESET 0x1
2530 /* Extracts the ALT_RSTMGR_PER0MODRST_NANDOCP field value from a register. */
2531 #define ALT_RSTMGR_PER0MODRST_NANDOCP_GET(value) (((value) & 0x00002000) >> 13)
2532 /* Produces a ALT_RSTMGR_PER0MODRST_NANDOCP register field value suitable for setting the register. */
2533 #define ALT_RSTMGR_PER0MODRST_NANDOCP_SET(value) (((value) << 13) & 0x00002000)
2534 
2535 /*
2536  * Field : QSPIOCP - qspiocp
2537  *
2538  * Resets QSPI ECC OCP DIagnostics modules.
2539  *
2540  * Field Access Macros:
2541  *
2542  */
2543 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_QSPIOCP register field. */
2544 #define ALT_RSTMGR_PER0MODRST_QSPIOCP_LSB 14
2545 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_QSPIOCP register field. */
2546 #define ALT_RSTMGR_PER0MODRST_QSPIOCP_MSB 14
2547 /* The width in bits of the ALT_RSTMGR_PER0MODRST_QSPIOCP register field. */
2548 #define ALT_RSTMGR_PER0MODRST_QSPIOCP_WIDTH 1
2549 /* The mask used to set the ALT_RSTMGR_PER0MODRST_QSPIOCP register field value. */
2550 #define ALT_RSTMGR_PER0MODRST_QSPIOCP_SET_MSK 0x00004000
2551 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_QSPIOCP register field value. */
2552 #define ALT_RSTMGR_PER0MODRST_QSPIOCP_CLR_MSK 0xffffbfff
2553 /* The reset value of the ALT_RSTMGR_PER0MODRST_QSPIOCP register field. */
2554 #define ALT_RSTMGR_PER0MODRST_QSPIOCP_RESET 0x1
2555 /* Extracts the ALT_RSTMGR_PER0MODRST_QSPIOCP field value from a register. */
2556 #define ALT_RSTMGR_PER0MODRST_QSPIOCP_GET(value) (((value) & 0x00004000) >> 14)
2557 /* Produces a ALT_RSTMGR_PER0MODRST_QSPIOCP register field value suitable for setting the register. */
2558 #define ALT_RSTMGR_PER0MODRST_QSPIOCP_SET(value) (((value) << 14) & 0x00004000)
2559 
2560 /*
2561  * Field : SDMMCOCP - sdmmcocp
2562  *
2563  * Resets SDMMC ECC OCP DIagnostics modules.
2564  *
2565  * Field Access Macros:
2566  *
2567  */
2568 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_SDMMCOCP register field. */
2569 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_LSB 15
2570 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_SDMMCOCP register field. */
2571 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_MSB 15
2572 /* The width in bits of the ALT_RSTMGR_PER0MODRST_SDMMCOCP register field. */
2573 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_WIDTH 1
2574 /* The mask used to set the ALT_RSTMGR_PER0MODRST_SDMMCOCP register field value. */
2575 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_SET_MSK 0x00008000
2576 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_SDMMCOCP register field value. */
2577 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_CLR_MSK 0xffff7fff
2578 /* The reset value of the ALT_RSTMGR_PER0MODRST_SDMMCOCP register field. */
2579 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_RESET 0x1
2580 /* Extracts the ALT_RSTMGR_PER0MODRST_SDMMCOCP field value from a register. */
2581 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_GET(value) (((value) & 0x00008000) >> 15)
2582 /* Produces a ALT_RSTMGR_PER0MODRST_SDMMCOCP register field value suitable for setting the register. */
2583 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_SET(value) (((value) << 15) & 0x00008000)
2584 
2585 /*
2586  * Field : DMA Controller - dma
2587  *
2588  * Resets DMA controller
2589  *
2590  * Field Access Macros:
2591  *
2592  */
2593 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMA register field. */
2594 #define ALT_RSTMGR_PER0MODRST_DMA_LSB 16
2595 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMA register field. */
2596 #define ALT_RSTMGR_PER0MODRST_DMA_MSB 16
2597 /* The width in bits of the ALT_RSTMGR_PER0MODRST_DMA register field. */
2598 #define ALT_RSTMGR_PER0MODRST_DMA_WIDTH 1
2599 /* The mask used to set the ALT_RSTMGR_PER0MODRST_DMA register field value. */
2600 #define ALT_RSTMGR_PER0MODRST_DMA_SET_MSK 0x00010000
2601 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_DMA register field value. */
2602 #define ALT_RSTMGR_PER0MODRST_DMA_CLR_MSK 0xfffeffff
2603 /* The reset value of the ALT_RSTMGR_PER0MODRST_DMA register field. */
2604 #define ALT_RSTMGR_PER0MODRST_DMA_RESET 0x1
2605 /* Extracts the ALT_RSTMGR_PER0MODRST_DMA field value from a register. */
2606 #define ALT_RSTMGR_PER0MODRST_DMA_GET(value) (((value) & 0x00010000) >> 16)
2607 /* Produces a ALT_RSTMGR_PER0MODRST_DMA register field value suitable for setting the register. */
2608 #define ALT_RSTMGR_PER0MODRST_DMA_SET(value) (((value) << 16) & 0x00010000)
2609 
2610 /*
2611  * Field : SPIM0 - spim0
2612  *
2613  * Resets SPIM0 controller
2614  *
2615  * Field Access Macros:
2616  *
2617  */
2618 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_SPIM0 register field. */
2619 #define ALT_RSTMGR_PER0MODRST_SPIM0_LSB 17
2620 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_SPIM0 register field. */
2621 #define ALT_RSTMGR_PER0MODRST_SPIM0_MSB 17
2622 /* The width in bits of the ALT_RSTMGR_PER0MODRST_SPIM0 register field. */
2623 #define ALT_RSTMGR_PER0MODRST_SPIM0_WIDTH 1
2624 /* The mask used to set the ALT_RSTMGR_PER0MODRST_SPIM0 register field value. */
2625 #define ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK 0x00020000
2626 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_SPIM0 register field value. */
2627 #define ALT_RSTMGR_PER0MODRST_SPIM0_CLR_MSK 0xfffdffff
2628 /* The reset value of the ALT_RSTMGR_PER0MODRST_SPIM0 register field. */
2629 #define ALT_RSTMGR_PER0MODRST_SPIM0_RESET 0x1
2630 /* Extracts the ALT_RSTMGR_PER0MODRST_SPIM0 field value from a register. */
2631 #define ALT_RSTMGR_PER0MODRST_SPIM0_GET(value) (((value) & 0x00020000) >> 17)
2632 /* Produces a ALT_RSTMGR_PER0MODRST_SPIM0 register field value suitable for setting the register. */
2633 #define ALT_RSTMGR_PER0MODRST_SPIM0_SET(value) (((value) << 17) & 0x00020000)
2634 
2635 /*
2636  * Field : SPIM1 - spim1
2637  *
2638  * Resets SPIM1 controller
2639  *
2640  * Field Access Macros:
2641  *
2642  */
2643 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_SPIM1 register field. */
2644 #define ALT_RSTMGR_PER0MODRST_SPIM1_LSB 18
2645 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_SPIM1 register field. */
2646 #define ALT_RSTMGR_PER0MODRST_SPIM1_MSB 18
2647 /* The width in bits of the ALT_RSTMGR_PER0MODRST_SPIM1 register field. */
2648 #define ALT_RSTMGR_PER0MODRST_SPIM1_WIDTH 1
2649 /* The mask used to set the ALT_RSTMGR_PER0MODRST_SPIM1 register field value. */
2650 #define ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK 0x00040000
2651 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_SPIM1 register field value. */
2652 #define ALT_RSTMGR_PER0MODRST_SPIM1_CLR_MSK 0xfffbffff
2653 /* The reset value of the ALT_RSTMGR_PER0MODRST_SPIM1 register field. */
2654 #define ALT_RSTMGR_PER0MODRST_SPIM1_RESET 0x1
2655 /* Extracts the ALT_RSTMGR_PER0MODRST_SPIM1 field value from a register. */
2656 #define ALT_RSTMGR_PER0MODRST_SPIM1_GET(value) (((value) & 0x00040000) >> 18)
2657 /* Produces a ALT_RSTMGR_PER0MODRST_SPIM1 register field value suitable for setting the register. */
2658 #define ALT_RSTMGR_PER0MODRST_SPIM1_SET(value) (((value) << 18) & 0x00040000)
2659 
2660 /*
2661  * Field : SPIS0 - spis0
2662  *
2663  * Resets SPIS0 controller
2664  *
2665  * Field Access Macros:
2666  *
2667  */
2668 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_SPIS0 register field. */
2669 #define ALT_RSTMGR_PER0MODRST_SPIS0_LSB 19
2670 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_SPIS0 register field. */
2671 #define ALT_RSTMGR_PER0MODRST_SPIS0_MSB 19
2672 /* The width in bits of the ALT_RSTMGR_PER0MODRST_SPIS0 register field. */
2673 #define ALT_RSTMGR_PER0MODRST_SPIS0_WIDTH 1
2674 /* The mask used to set the ALT_RSTMGR_PER0MODRST_SPIS0 register field value. */
2675 #define ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK 0x00080000
2676 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_SPIS0 register field value. */
2677 #define ALT_RSTMGR_PER0MODRST_SPIS0_CLR_MSK 0xfff7ffff
2678 /* The reset value of the ALT_RSTMGR_PER0MODRST_SPIS0 register field. */
2679 #define ALT_RSTMGR_PER0MODRST_SPIS0_RESET 0x1
2680 /* Extracts the ALT_RSTMGR_PER0MODRST_SPIS0 field value from a register. */
2681 #define ALT_RSTMGR_PER0MODRST_SPIS0_GET(value) (((value) & 0x00080000) >> 19)
2682 /* Produces a ALT_RSTMGR_PER0MODRST_SPIS0 register field value suitable for setting the register. */
2683 #define ALT_RSTMGR_PER0MODRST_SPIS0_SET(value) (((value) << 19) & 0x00080000)
2684 
2685 /*
2686  * Field : SPIS1 - spis1
2687  *
2688  * Resets SPIS1 controller
2689  *
2690  * Field Access Macros:
2691  *
2692  */
2693 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_SPIS1 register field. */
2694 #define ALT_RSTMGR_PER0MODRST_SPIS1_LSB 20
2695 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_SPIS1 register field. */
2696 #define ALT_RSTMGR_PER0MODRST_SPIS1_MSB 20
2697 /* The width in bits of the ALT_RSTMGR_PER0MODRST_SPIS1 register field. */
2698 #define ALT_RSTMGR_PER0MODRST_SPIS1_WIDTH 1
2699 /* The mask used to set the ALT_RSTMGR_PER0MODRST_SPIS1 register field value. */
2700 #define ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK 0x00100000
2701 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_SPIS1 register field value. */
2702 #define ALT_RSTMGR_PER0MODRST_SPIS1_CLR_MSK 0xffefffff
2703 /* The reset value of the ALT_RSTMGR_PER0MODRST_SPIS1 register field. */
2704 #define ALT_RSTMGR_PER0MODRST_SPIS1_RESET 0x1
2705 /* Extracts the ALT_RSTMGR_PER0MODRST_SPIS1 field value from a register. */
2706 #define ALT_RSTMGR_PER0MODRST_SPIS1_GET(value) (((value) & 0x00100000) >> 20)
2707 /* Produces a ALT_RSTMGR_PER0MODRST_SPIS1 register field value suitable for setting the register. */
2708 #define ALT_RSTMGR_PER0MODRST_SPIS1_SET(value) (((value) << 20) & 0x00100000)
2709 
2710 /*
2711  * Field : DMAOCP - dmaocp
2712  *
2713  * Resets DMA Controller ECC OCP DIagnostics modules.
2714  *
2715  * Field Access Macros:
2716  *
2717  */
2718 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAOCP register field. */
2719 #define ALT_RSTMGR_PER0MODRST_DMAOCP_LSB 21
2720 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAOCP register field. */
2721 #define ALT_RSTMGR_PER0MODRST_DMAOCP_MSB 21
2722 /* The width in bits of the ALT_RSTMGR_PER0MODRST_DMAOCP register field. */
2723 #define ALT_RSTMGR_PER0MODRST_DMAOCP_WIDTH 1
2724 /* The mask used to set the ALT_RSTMGR_PER0MODRST_DMAOCP register field value. */
2725 #define ALT_RSTMGR_PER0MODRST_DMAOCP_SET_MSK 0x00200000
2726 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAOCP register field value. */
2727 #define ALT_RSTMGR_PER0MODRST_DMAOCP_CLR_MSK 0xffdfffff
2728 /* The reset value of the ALT_RSTMGR_PER0MODRST_DMAOCP register field. */
2729 #define ALT_RSTMGR_PER0MODRST_DMAOCP_RESET 0x1
2730 /* Extracts the ALT_RSTMGR_PER0MODRST_DMAOCP field value from a register. */
2731 #define ALT_RSTMGR_PER0MODRST_DMAOCP_GET(value) (((value) & 0x00200000) >> 21)
2732 /* Produces a ALT_RSTMGR_PER0MODRST_DMAOCP register field value suitable for setting the register. */
2733 #define ALT_RSTMGR_PER0MODRST_DMAOCP_SET(value) (((value) << 21) & 0x00200000)
2734 
2735 /*
2736  * Field : EMAC PTP - emacptp
2737  *
2738  * Resets EMAC PTP
2739  *
2740  * Field Access Macros:
2741  *
2742  */
2743 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_EMACPTP register field. */
2744 #define ALT_RSTMGR_PER0MODRST_EMACPTP_LSB 22
2745 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_EMACPTP register field. */
2746 #define ALT_RSTMGR_PER0MODRST_EMACPTP_MSB 22
2747 /* The width in bits of the ALT_RSTMGR_PER0MODRST_EMACPTP register field. */
2748 #define ALT_RSTMGR_PER0MODRST_EMACPTP_WIDTH 1
2749 /* The mask used to set the ALT_RSTMGR_PER0MODRST_EMACPTP register field value. */
2750 #define ALT_RSTMGR_PER0MODRST_EMACPTP_SET_MSK 0x00400000
2751 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_EMACPTP register field value. */
2752 #define ALT_RSTMGR_PER0MODRST_EMACPTP_CLR_MSK 0xffbfffff
2753 /* The reset value of the ALT_RSTMGR_PER0MODRST_EMACPTP register field. */
2754 #define ALT_RSTMGR_PER0MODRST_EMACPTP_RESET 0x1
2755 /* Extracts the ALT_RSTMGR_PER0MODRST_EMACPTP field value from a register. */
2756 #define ALT_RSTMGR_PER0MODRST_EMACPTP_GET(value) (((value) & 0x00400000) >> 22)
2757 /* Produces a ALT_RSTMGR_PER0MODRST_EMACPTP register field value suitable for setting the register. */
2758 #define ALT_RSTMGR_PER0MODRST_EMACPTP_SET(value) (((value) << 22) & 0x00400000)
2759 
2760 /*
2761  * Field : FPGA DMA0 - dmaif0
2762  *
2763  * Resets DMA channel 0 interface adapter between FPGA Fabric and HPS DMA
2764  * Controller
2765  *
2766  * Field Access Macros:
2767  *
2768  */
2769 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF0 register field. */
2770 #define ALT_RSTMGR_PER0MODRST_DMAIF0_LSB 24
2771 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF0 register field. */
2772 #define ALT_RSTMGR_PER0MODRST_DMAIF0_MSB 24
2773 /* The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF0 register field. */
2774 #define ALT_RSTMGR_PER0MODRST_DMAIF0_WIDTH 1
2775 /* The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF0 register field value. */
2776 #define ALT_RSTMGR_PER0MODRST_DMAIF0_SET_MSK 0x01000000
2777 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF0 register field value. */
2778 #define ALT_RSTMGR_PER0MODRST_DMAIF0_CLR_MSK 0xfeffffff
2779 /* The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF0 register field. */
2780 #define ALT_RSTMGR_PER0MODRST_DMAIF0_RESET 0x1
2781 /* Extracts the ALT_RSTMGR_PER0MODRST_DMAIF0 field value from a register. */
2782 #define ALT_RSTMGR_PER0MODRST_DMAIF0_GET(value) (((value) & 0x01000000) >> 24)
2783 /* Produces a ALT_RSTMGR_PER0MODRST_DMAIF0 register field value suitable for setting the register. */
2784 #define ALT_RSTMGR_PER0MODRST_DMAIF0_SET(value) (((value) << 24) & 0x01000000)
2785 
2786 /*
2787  * Field : FPGA DMA1 - dmaif1
2788  *
2789  * Resets DMA channel 1 interface adapter between FPGA Fabric and HPS DMA
2790  * Controller
2791  *
2792  * Field Access Macros:
2793  *
2794  */
2795 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF1 register field. */
2796 #define ALT_RSTMGR_PER0MODRST_DMAIF1_LSB 25
2797 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF1 register field. */
2798 #define ALT_RSTMGR_PER0MODRST_DMAIF1_MSB 25
2799 /* The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF1 register field. */
2800 #define ALT_RSTMGR_PER0MODRST_DMAIF1_WIDTH 1
2801 /* The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF1 register field value. */
2802 #define ALT_RSTMGR_PER0MODRST_DMAIF1_SET_MSK 0x02000000
2803 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF1 register field value. */
2804 #define ALT_RSTMGR_PER0MODRST_DMAIF1_CLR_MSK 0xfdffffff
2805 /* The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF1 register field. */
2806 #define ALT_RSTMGR_PER0MODRST_DMAIF1_RESET 0x1
2807 /* Extracts the ALT_RSTMGR_PER0MODRST_DMAIF1 field value from a register. */
2808 #define ALT_RSTMGR_PER0MODRST_DMAIF1_GET(value) (((value) & 0x02000000) >> 25)
2809 /* Produces a ALT_RSTMGR_PER0MODRST_DMAIF1 register field value suitable for setting the register. */
2810 #define ALT_RSTMGR_PER0MODRST_DMAIF1_SET(value) (((value) << 25) & 0x02000000)
2811 
2812 /*
2813  * Field : FPGA DMA2 - dmaif2
2814  *
2815  * Resets DMA channel 2 interface adapter between FPGA Fabric and HPS DMA
2816  * Controller
2817  *
2818  * Field Access Macros:
2819  *
2820  */
2821 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF2 register field. */
2822 #define ALT_RSTMGR_PER0MODRST_DMAIF2_LSB 26
2823 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF2 register field. */
2824 #define ALT_RSTMGR_PER0MODRST_DMAIF2_MSB 26
2825 /* The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF2 register field. */
2826 #define ALT_RSTMGR_PER0MODRST_DMAIF2_WIDTH 1
2827 /* The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF2 register field value. */
2828 #define ALT_RSTMGR_PER0MODRST_DMAIF2_SET_MSK 0x04000000
2829 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF2 register field value. */
2830 #define ALT_RSTMGR_PER0MODRST_DMAIF2_CLR_MSK 0xfbffffff
2831 /* The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF2 register field. */
2832 #define ALT_RSTMGR_PER0MODRST_DMAIF2_RESET 0x1
2833 /* Extracts the ALT_RSTMGR_PER0MODRST_DMAIF2 field value from a register. */
2834 #define ALT_RSTMGR_PER0MODRST_DMAIF2_GET(value) (((value) & 0x04000000) >> 26)
2835 /* Produces a ALT_RSTMGR_PER0MODRST_DMAIF2 register field value suitable for setting the register. */
2836 #define ALT_RSTMGR_PER0MODRST_DMAIF2_SET(value) (((value) << 26) & 0x04000000)
2837 
2838 /*
2839  * Field : FPGA DMA3 - dmaif3
2840  *
2841  * Resets DMA channel 3 interface adapter between FPGA Fabric and HPS DMA
2842  * Controller
2843  *
2844  * Field Access Macros:
2845  *
2846  */
2847 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF3 register field. */
2848 #define ALT_RSTMGR_PER0MODRST_DMAIF3_LSB 27
2849 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF3 register field. */
2850 #define ALT_RSTMGR_PER0MODRST_DMAIF3_MSB 27
2851 /* The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF3 register field. */
2852 #define ALT_RSTMGR_PER0MODRST_DMAIF3_WIDTH 1
2853 /* The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF3 register field value. */
2854 #define ALT_RSTMGR_PER0MODRST_DMAIF3_SET_MSK 0x08000000
2855 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF3 register field value. */
2856 #define ALT_RSTMGR_PER0MODRST_DMAIF3_CLR_MSK 0xf7ffffff
2857 /* The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF3 register field. */
2858 #define ALT_RSTMGR_PER0MODRST_DMAIF3_RESET 0x1
2859 /* Extracts the ALT_RSTMGR_PER0MODRST_DMAIF3 field value from a register. */
2860 #define ALT_RSTMGR_PER0MODRST_DMAIF3_GET(value) (((value) & 0x08000000) >> 27)
2861 /* Produces a ALT_RSTMGR_PER0MODRST_DMAIF3 register field value suitable for setting the register. */
2862 #define ALT_RSTMGR_PER0MODRST_DMAIF3_SET(value) (((value) << 27) & 0x08000000)
2863 
2864 /*
2865  * Field : FPGA DMA4 - dmaif4
2866  *
2867  * Resets DMA channel 4 interface adapter between FPGA Fabric and HPS DMA
2868  * Controller
2869  *
2870  * Field Access Macros:
2871  *
2872  */
2873 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF4 register field. */
2874 #define ALT_RSTMGR_PER0MODRST_DMAIF4_LSB 28
2875 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF4 register field. */
2876 #define ALT_RSTMGR_PER0MODRST_DMAIF4_MSB 28
2877 /* The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF4 register field. */
2878 #define ALT_RSTMGR_PER0MODRST_DMAIF4_WIDTH 1
2879 /* The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF4 register field value. */
2880 #define ALT_RSTMGR_PER0MODRST_DMAIF4_SET_MSK 0x10000000
2881 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF4 register field value. */
2882 #define ALT_RSTMGR_PER0MODRST_DMAIF4_CLR_MSK 0xefffffff
2883 /* The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF4 register field. */
2884 #define ALT_RSTMGR_PER0MODRST_DMAIF4_RESET 0x1
2885 /* Extracts the ALT_RSTMGR_PER0MODRST_DMAIF4 field value from a register. */
2886 #define ALT_RSTMGR_PER0MODRST_DMAIF4_GET(value) (((value) & 0x10000000) >> 28)
2887 /* Produces a ALT_RSTMGR_PER0MODRST_DMAIF4 register field value suitable for setting the register. */
2888 #define ALT_RSTMGR_PER0MODRST_DMAIF4_SET(value) (((value) << 28) & 0x10000000)
2889 
2890 /*
2891  * Field : FPGA DMA5 - dmaif5
2892  *
2893  * Resets DMA channel 5 interface adapter between FPGA Fabric and HPS DMA
2894  * Controller
2895  *
2896  * Field Access Macros:
2897  *
2898  */
2899 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF5 register field. */
2900 #define ALT_RSTMGR_PER0MODRST_DMAIF5_LSB 29
2901 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF5 register field. */
2902 #define ALT_RSTMGR_PER0MODRST_DMAIF5_MSB 29
2903 /* The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF5 register field. */
2904 #define ALT_RSTMGR_PER0MODRST_DMAIF5_WIDTH 1
2905 /* The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF5 register field value. */
2906 #define ALT_RSTMGR_PER0MODRST_DMAIF5_SET_MSK 0x20000000
2907 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF5 register field value. */
2908 #define ALT_RSTMGR_PER0MODRST_DMAIF5_CLR_MSK 0xdfffffff
2909 /* The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF5 register field. */
2910 #define ALT_RSTMGR_PER0MODRST_DMAIF5_RESET 0x1
2911 /* Extracts the ALT_RSTMGR_PER0MODRST_DMAIF5 field value from a register. */
2912 #define ALT_RSTMGR_PER0MODRST_DMAIF5_GET(value) (((value) & 0x20000000) >> 29)
2913 /* Produces a ALT_RSTMGR_PER0MODRST_DMAIF5 register field value suitable for setting the register. */
2914 #define ALT_RSTMGR_PER0MODRST_DMAIF5_SET(value) (((value) << 29) & 0x20000000)
2915 
2916 /*
2917  * Field : FPGA DMA6 - dmaif6
2918  *
2919  * Resets DMA channel 6 interface adapter between FPGA Fabric and HPS DMA
2920  * Controller
2921  *
2922  * Field Access Macros:
2923  *
2924  */
2925 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF6 register field. */
2926 #define ALT_RSTMGR_PER0MODRST_DMAIF6_LSB 30
2927 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF6 register field. */
2928 #define ALT_RSTMGR_PER0MODRST_DMAIF6_MSB 30
2929 /* The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF6 register field. */
2930 #define ALT_RSTMGR_PER0MODRST_DMAIF6_WIDTH 1
2931 /* The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF6 register field value. */
2932 #define ALT_RSTMGR_PER0MODRST_DMAIF6_SET_MSK 0x40000000
2933 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF6 register field value. */
2934 #define ALT_RSTMGR_PER0MODRST_DMAIF6_CLR_MSK 0xbfffffff
2935 /* The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF6 register field. */
2936 #define ALT_RSTMGR_PER0MODRST_DMAIF6_RESET 0x1
2937 /* Extracts the ALT_RSTMGR_PER0MODRST_DMAIF6 field value from a register. */
2938 #define ALT_RSTMGR_PER0MODRST_DMAIF6_GET(value) (((value) & 0x40000000) >> 30)
2939 /* Produces a ALT_RSTMGR_PER0MODRST_DMAIF6 register field value suitable for setting the register. */
2940 #define ALT_RSTMGR_PER0MODRST_DMAIF6_SET(value) (((value) << 30) & 0x40000000)
2941 
2942 /*
2943  * Field : FPGA DMA7 - dmaif7
2944  *
2945  * Resets DMA channel 7 interface adapter between FPGA Fabric and HPS DMA
2946  * Controller
2947  *
2948  * Field Access Macros:
2949  *
2950  */
2951 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF7 register field. */
2952 #define ALT_RSTMGR_PER0MODRST_DMAIF7_LSB 31
2953 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF7 register field. */
2954 #define ALT_RSTMGR_PER0MODRST_DMAIF7_MSB 31
2955 /* The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF7 register field. */
2956 #define ALT_RSTMGR_PER0MODRST_DMAIF7_WIDTH 1
2957 /* The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF7 register field value. */
2958 #define ALT_RSTMGR_PER0MODRST_DMAIF7_SET_MSK 0x80000000
2959 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF7 register field value. */
2960 #define ALT_RSTMGR_PER0MODRST_DMAIF7_CLR_MSK 0x7fffffff
2961 /* The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF7 register field. */
2962 #define ALT_RSTMGR_PER0MODRST_DMAIF7_RESET 0x1
2963 /* Extracts the ALT_RSTMGR_PER0MODRST_DMAIF7 field value from a register. */
2964 #define ALT_RSTMGR_PER0MODRST_DMAIF7_GET(value) (((value) & 0x80000000) >> 31)
2965 /* Produces a ALT_RSTMGR_PER0MODRST_DMAIF7 register field value suitable for setting the register. */
2966 #define ALT_RSTMGR_PER0MODRST_DMAIF7_SET(value) (((value) << 31) & 0x80000000)
2967 
2968 #ifndef __ASSEMBLY__
2969 /*
2970  * WARNING: The C register and register group struct declarations are provided for
2971  * convenience and illustrative purposes. They should, however, be used with
2972  * caution as the C language standard provides no guarantees about the alignment or
2973  * atomicity of device memory accesses. The recommended practice for writing
2974  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2975  * alt_write_word() functions.
2976  *
2977  * The struct declaration for register ALT_RSTMGR_PER0MODRST.
2978  */
2979 struct ALT_RSTMGR_PER0MODRST_s
2980 {
2981  uint32_t emac0 : 1; /* EMAC0 */
2982  uint32_t emac1 : 1; /* EMAC1 */
2983  uint32_t emac2 : 1; /* EMAC2 */
2984  uint32_t usb0 : 1; /* USB0 */
2985  uint32_t usb1 : 1; /* USB1 */
2986  uint32_t nand : 1; /* NAND Flash */
2987  uint32_t qspi : 1; /* QSPI Flash */
2988  uint32_t sdmmc : 1; /* SD/MMC */
2989  uint32_t emac0ocp : 1; /* EMAC0OCP */
2990  uint32_t emac1ocp : 1; /* EMAC1OCP */
2991  uint32_t emac2ocp : 1; /* EMAC2OCP */
2992  uint32_t usb0ocp : 1; /* USB0OCP */
2993  uint32_t usb1ocp : 1; /* USB1OCP */
2994  uint32_t nandocp : 1; /* NANDOCP */
2995  uint32_t qspiocp : 1; /* QSPIOCP */
2996  uint32_t sdmmcocp : 1; /* SDMMCOCP */
2997  uint32_t dma : 1; /* DMA Controller */
2998  uint32_t spim0 : 1; /* SPIM0 */
2999  uint32_t spim1 : 1; /* SPIM1 */
3000  uint32_t spis0 : 1; /* SPIS0 */
3001  uint32_t spis1 : 1; /* SPIS1 */
3002  uint32_t dmaocp : 1; /* DMAOCP */
3003  uint32_t emacptp : 1; /* EMAC PTP */
3004  uint32_t : 1; /* *UNDEFINED* */
3005  uint32_t dmaif0 : 1; /* FPGA DMA0 */
3006  uint32_t dmaif1 : 1; /* FPGA DMA1 */
3007  uint32_t dmaif2 : 1; /* FPGA DMA2 */
3008  uint32_t dmaif3 : 1; /* FPGA DMA3 */
3009  uint32_t dmaif4 : 1; /* FPGA DMA4 */
3010  uint32_t dmaif5 : 1; /* FPGA DMA5 */
3011  uint32_t dmaif6 : 1; /* FPGA DMA6 */
3012  uint32_t dmaif7 : 1; /* FPGA DMA7 */
3013 };
3014 
3015 /* The typedef declaration for register ALT_RSTMGR_PER0MODRST. */
3016 typedef volatile struct ALT_RSTMGR_PER0MODRST_s ALT_RSTMGR_PER0MODRST_t;
3017 #endif /* __ASSEMBLY__ */
3018 
3019 /* The reset value of the ALT_RSTMGR_PER0MODRST register. */
3020 #define ALT_RSTMGR_PER0MODRST_RESET 0xff7fffff
3021 /* The byte offset of the ALT_RSTMGR_PER0MODRST register from the beginning of the component. */
3022 #define ALT_RSTMGR_PER0MODRST_OFST 0x24
3023 
3024 /*
3025  * Register : Peripheral Module Reset Register - per1modrst
3026  *
3027  * The PER1MODRST register is used by software to trigger module resets for Slow
3028  * Peripheral Group. Software explicitly asserts and de-asserts module reset
3029  * signals by writing bits in the appropriate *MODRST register. It is up to
3030  * software to ensure module reset signals are asserted for the appropriate length
3031  * of time and are de-asserted in the correct order. It is also up to software to
3032  * not assert a module reset signal that would prevent software from de-asserting
3033  * the module reset signal. For example, software should not assert the module
3034  * reset to the CPU executing the software.
3035  *
3036  * Software writes a bit to 1 to assert the module reset signal and to 0 to de-
3037  * assert the module reset signal.
3038  *
3039  * All fields are reset by a cold reset.All fields are also reset by a warm reset
3040  * if not masked by the corresponding PERWARMMASK field.
3041  *
3042  * The reset value of all fields is 1. This holds the corresponding module in reset
3043  * until software is ready to release the module from reset by writing 0 to its
3044  * field.
3045  *
3046  * Register Layout
3047  *
3048  * Bits | Access | Reset | Description
3049  * :--------|:-------|:------|:-------------
3050  * [0] | RW | 0x1 | Watch Dog0
3051  * [1] | RW | 0x1 | Watch Dog1
3052  * [2] | RW | 0x1 | l4systimer0
3053  * [3] | RW | 0x1 | l4sys_timer1
3054  * [4] | RW | 0x1 | SP Timer 0
3055  * [5] | RW | 0x1 | SP Timer 1
3056  * [7:6] | ??? | 0x0 | *UNDEFINED*
3057  * [8] | RW | 0x1 | I2C0
3058  * [9] | RW | 0x1 | I2C1
3059  * [10] | RW | 0x1 | I2C2
3060  * [11] | RW | 0x1 | I2C3
3061  * [12] | RW | 0x1 | I2C4
3062  * [15:13] | ??? | 0x0 | *UNDEFINED*
3063  * [16] | RW | 0x1 | UART0
3064  * [17] | RW | 0x1 | UART1
3065  * [23:18] | ??? | 0x0 | *UNDEFINED*
3066  * [24] | RW | 0x1 | GPIO0
3067  * [25] | RW | 0x1 | GPIO1
3068  * [26] | RW | 0x1 | GPIO2
3069  * [31:27] | ??? | 0x0 | *UNDEFINED*
3070  *
3071  */
3072 /*
3073  * Field : Watch Dog0 - watchdog0
3074  *
3075  * Resets Watchdog 0
3076  *
3077  * Field Access Macros:
3078  *
3079  */
3080 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_WD0 register field. */
3081 #define ALT_RSTMGR_PER1MODRST_WD0_LSB 0
3082 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_WD0 register field. */
3083 #define ALT_RSTMGR_PER1MODRST_WD0_MSB 0
3084 /* The width in bits of the ALT_RSTMGR_PER1MODRST_WD0 register field. */
3085 #define ALT_RSTMGR_PER1MODRST_WD0_WIDTH 1
3086 /* The mask used to set the ALT_RSTMGR_PER1MODRST_WD0 register field value. */
3087 #define ALT_RSTMGR_PER1MODRST_WD0_SET_MSK 0x00000001
3088 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_WD0 register field value. */
3089 #define ALT_RSTMGR_PER1MODRST_WD0_CLR_MSK 0xfffffffe
3090 /* The reset value of the ALT_RSTMGR_PER1MODRST_WD0 register field. */
3091 #define ALT_RSTMGR_PER1MODRST_WD0_RESET 0x1
3092 /* Extracts the ALT_RSTMGR_PER1MODRST_WD0 field value from a register. */
3093 #define ALT_RSTMGR_PER1MODRST_WD0_GET(value) (((value) & 0x00000001) >> 0)
3094 /* Produces a ALT_RSTMGR_PER1MODRST_WD0 register field value suitable for setting the register. */
3095 #define ALT_RSTMGR_PER1MODRST_WD0_SET(value) (((value) << 0) & 0x00000001)
3096 
3097 /*
3098  * Field : Watch Dog1 - watchdog1
3099  *
3100  * Resets Watchdog 1
3101  *
3102  * Field Access Macros:
3103  *
3104  */
3105 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_WD1 register field. */
3106 #define ALT_RSTMGR_PER1MODRST_WD1_LSB 1
3107 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_WD1 register field. */
3108 #define ALT_RSTMGR_PER1MODRST_WD1_MSB 1
3109 /* The width in bits of the ALT_RSTMGR_PER1MODRST_WD1 register field. */
3110 #define ALT_RSTMGR_PER1MODRST_WD1_WIDTH 1
3111 /* The mask used to set the ALT_RSTMGR_PER1MODRST_WD1 register field value. */
3112 #define ALT_RSTMGR_PER1MODRST_WD1_SET_MSK 0x00000002
3113 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_WD1 register field value. */
3114 #define ALT_RSTMGR_PER1MODRST_WD1_CLR_MSK 0xfffffffd
3115 /* The reset value of the ALT_RSTMGR_PER1MODRST_WD1 register field. */
3116 #define ALT_RSTMGR_PER1MODRST_WD1_RESET 0x1
3117 /* Extracts the ALT_RSTMGR_PER1MODRST_WD1 field value from a register. */
3118 #define ALT_RSTMGR_PER1MODRST_WD1_GET(value) (((value) & 0x00000002) >> 1)
3119 /* Produces a ALT_RSTMGR_PER1MODRST_WD1 register field value suitable for setting the register. */
3120 #define ALT_RSTMGR_PER1MODRST_WD1_SET(value) (((value) << 1) & 0x00000002)
3121 
3122 /*
3123  * Field : l4systimer0 - l4systimer0
3124  *
3125  * Resets l4sys_timer0
3126  *
3127  * Field Access Macros:
3128  *
3129  */
3130 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_L4SYSTMR0 register field. */
3131 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_LSB 2
3132 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_L4SYSTMR0 register field. */
3133 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_MSB 2
3134 /* The width in bits of the ALT_RSTMGR_PER1MODRST_L4SYSTMR0 register field. */
3135 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_WIDTH 1
3136 /* The mask used to set the ALT_RSTMGR_PER1MODRST_L4SYSTMR0 register field value. */
3137 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_SET_MSK 0x00000004
3138 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_L4SYSTMR0 register field value. */
3139 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_CLR_MSK 0xfffffffb
3140 /* The reset value of the ALT_RSTMGR_PER1MODRST_L4SYSTMR0 register field. */
3141 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_RESET 0x1
3142 /* Extracts the ALT_RSTMGR_PER1MODRST_L4SYSTMR0 field value from a register. */
3143 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_GET(value) (((value) & 0x00000004) >> 2)
3144 /* Produces a ALT_RSTMGR_PER1MODRST_L4SYSTMR0 register field value suitable for setting the register. */
3145 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_SET(value) (((value) << 2) & 0x00000004)
3146 
3147 /*
3148  * Field : l4sys_timer1 - l4systimer1
3149  *
3150  * Resets l4sys_timer1
3151  *
3152  * Field Access Macros:
3153  *
3154  */
3155 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_L4SYSTMR1 register field. */
3156 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_LSB 3
3157 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_L4SYSTMR1 register field. */
3158 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_MSB 3
3159 /* The width in bits of the ALT_RSTMGR_PER1MODRST_L4SYSTMR1 register field. */
3160 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_WIDTH 1
3161 /* The mask used to set the ALT_RSTMGR_PER1MODRST_L4SYSTMR1 register field value. */
3162 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_SET_MSK 0x00000008
3163 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_L4SYSTMR1 register field value. */
3164 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_CLR_MSK 0xfffffff7
3165 /* The reset value of the ALT_RSTMGR_PER1MODRST_L4SYSTMR1 register field. */
3166 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_RESET 0x1
3167 /* Extracts the ALT_RSTMGR_PER1MODRST_L4SYSTMR1 field value from a register. */
3168 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_GET(value) (((value) & 0x00000008) >> 3)
3169 /* Produces a ALT_RSTMGR_PER1MODRST_L4SYSTMR1 register field value suitable for setting the register. */
3170 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_SET(value) (((value) << 3) & 0x00000008)
3171 
3172 /*
3173  * Field : SP Timer 0 - sptimer0
3174  *
3175  * Resets SP timer 0 connected to L4
3176  *
3177  * Field Access Macros:
3178  *
3179  */
3180 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_SPTMR0 register field. */
3181 #define ALT_RSTMGR_PER1MODRST_SPTMR0_LSB 4
3182 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_SPTMR0 register field. */
3183 #define ALT_RSTMGR_PER1MODRST_SPTMR0_MSB 4
3184 /* The width in bits of the ALT_RSTMGR_PER1MODRST_SPTMR0 register field. */
3185 #define ALT_RSTMGR_PER1MODRST_SPTMR0_WIDTH 1
3186 /* The mask used to set the ALT_RSTMGR_PER1MODRST_SPTMR0 register field value. */
3187 #define ALT_RSTMGR_PER1MODRST_SPTMR0_SET_MSK 0x00000010
3188 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_SPTMR0 register field value. */
3189 #define ALT_RSTMGR_PER1MODRST_SPTMR0_CLR_MSK 0xffffffef
3190 /* The reset value of the ALT_RSTMGR_PER1MODRST_SPTMR0 register field. */
3191 #define ALT_RSTMGR_PER1MODRST_SPTMR0_RESET 0x1
3192 /* Extracts the ALT_RSTMGR_PER1MODRST_SPTMR0 field value from a register. */
3193 #define ALT_RSTMGR_PER1MODRST_SPTMR0_GET(value) (((value) & 0x00000010) >> 4)
3194 /* Produces a ALT_RSTMGR_PER1MODRST_SPTMR0 register field value suitable for setting the register. */
3195 #define ALT_RSTMGR_PER1MODRST_SPTMR0_SET(value) (((value) << 4) & 0x00000010)
3196 
3197 /*
3198  * Field : SP Timer 1 - sptimer1
3199  *
3200  * Resets SP timer 1 connected to L4
3201  *
3202  * Field Access Macros:
3203  *
3204  */
3205 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_SPTMR1 register field. */
3206 #define ALT_RSTMGR_PER1MODRST_SPTMR1_LSB 5
3207 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_SPTMR1 register field. */
3208 #define ALT_RSTMGR_PER1MODRST_SPTMR1_MSB 5
3209 /* The width in bits of the ALT_RSTMGR_PER1MODRST_SPTMR1 register field. */
3210 #define ALT_RSTMGR_PER1MODRST_SPTMR1_WIDTH 1
3211 /* The mask used to set the ALT_RSTMGR_PER1MODRST_SPTMR1 register field value. */
3212 #define ALT_RSTMGR_PER1MODRST_SPTMR1_SET_MSK 0x00000020
3213 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_SPTMR1 register field value. */
3214 #define ALT_RSTMGR_PER1MODRST_SPTMR1_CLR_MSK 0xffffffdf
3215 /* The reset value of the ALT_RSTMGR_PER1MODRST_SPTMR1 register field. */
3216 #define ALT_RSTMGR_PER1MODRST_SPTMR1_RESET 0x1
3217 /* Extracts the ALT_RSTMGR_PER1MODRST_SPTMR1 field value from a register. */
3218 #define ALT_RSTMGR_PER1MODRST_SPTMR1_GET(value) (((value) & 0x00000020) >> 5)
3219 /* Produces a ALT_RSTMGR_PER1MODRST_SPTMR1 register field value suitable for setting the register. */
3220 #define ALT_RSTMGR_PER1MODRST_SPTMR1_SET(value) (((value) << 5) & 0x00000020)
3221 
3222 /*
3223  * Field : I2C0 - i2c0
3224  *
3225  * Resets I2C0 controller
3226  *
3227  * Field Access Macros:
3228  *
3229  */
3230 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_I2C0 register field. */
3231 #define ALT_RSTMGR_PER1MODRST_I2C0_LSB 8
3232 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_I2C0 register field. */
3233 #define ALT_RSTMGR_PER1MODRST_I2C0_MSB 8
3234 /* The width in bits of the ALT_RSTMGR_PER1MODRST_I2C0 register field. */
3235 #define ALT_RSTMGR_PER1MODRST_I2C0_WIDTH 1
3236 /* The mask used to set the ALT_RSTMGR_PER1MODRST_I2C0 register field value. */
3237 #define ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK 0x00000100
3238 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_I2C0 register field value. */
3239 #define ALT_RSTMGR_PER1MODRST_I2C0_CLR_MSK 0xfffffeff
3240 /* The reset value of the ALT_RSTMGR_PER1MODRST_I2C0 register field. */
3241 #define ALT_RSTMGR_PER1MODRST_I2C0_RESET 0x1
3242 /* Extracts the ALT_RSTMGR_PER1MODRST_I2C0 field value from a register. */
3243 #define ALT_RSTMGR_PER1MODRST_I2C0_GET(value) (((value) & 0x00000100) >> 8)
3244 /* Produces a ALT_RSTMGR_PER1MODRST_I2C0 register field value suitable for setting the register. */
3245 #define ALT_RSTMGR_PER1MODRST_I2C0_SET(value) (((value) << 8) & 0x00000100)
3246 
3247 /*
3248  * Field : I2C1 - i2c1
3249  *
3250  * Resets I2C1 controller
3251  *
3252  * Field Access Macros:
3253  *
3254  */
3255 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_I2C1 register field. */
3256 #define ALT_RSTMGR_PER1MODRST_I2C1_LSB 9
3257 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_I2C1 register field. */
3258 #define ALT_RSTMGR_PER1MODRST_I2C1_MSB 9
3259 /* The width in bits of the ALT_RSTMGR_PER1MODRST_I2C1 register field. */
3260 #define ALT_RSTMGR_PER1MODRST_I2C1_WIDTH 1
3261 /* The mask used to set the ALT_RSTMGR_PER1MODRST_I2C1 register field value. */
3262 #define ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK 0x00000200
3263 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_I2C1 register field value. */
3264 #define ALT_RSTMGR_PER1MODRST_I2C1_CLR_MSK 0xfffffdff
3265 /* The reset value of the ALT_RSTMGR_PER1MODRST_I2C1 register field. */
3266 #define ALT_RSTMGR_PER1MODRST_I2C1_RESET 0x1
3267 /* Extracts the ALT_RSTMGR_PER1MODRST_I2C1 field value from a register. */
3268 #define ALT_RSTMGR_PER1MODRST_I2C1_GET(value) (((value) & 0x00000200) >> 9)
3269 /* Produces a ALT_RSTMGR_PER1MODRST_I2C1 register field value suitable for setting the register. */
3270 #define ALT_RSTMGR_PER1MODRST_I2C1_SET(value) (((value) << 9) & 0x00000200)
3271 
3272 /*
3273  * Field : I2C2 - i2c2
3274  *
3275  * Resets I2C2 controller
3276  *
3277  * Field Access Macros:
3278  *
3279  */
3280 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_I2C2 register field. */
3281 #define ALT_RSTMGR_PER1MODRST_I2C2_LSB 10
3282 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_I2C2 register field. */
3283 #define ALT_RSTMGR_PER1MODRST_I2C2_MSB 10
3284 /* The width in bits of the ALT_RSTMGR_PER1MODRST_I2C2 register field. */
3285 #define ALT_RSTMGR_PER1MODRST_I2C2_WIDTH 1
3286 /* The mask used to set the ALT_RSTMGR_PER1MODRST_I2C2 register field value. */
3287 #define ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK 0x00000400
3288 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_I2C2 register field value. */
3289 #define ALT_RSTMGR_PER1MODRST_I2C2_CLR_MSK 0xfffffbff
3290 /* The reset value of the ALT_RSTMGR_PER1MODRST_I2C2 register field. */
3291 #define ALT_RSTMGR_PER1MODRST_I2C2_RESET 0x1
3292 /* Extracts the ALT_RSTMGR_PER1MODRST_I2C2 field value from a register. */
3293 #define ALT_RSTMGR_PER1MODRST_I2C2_GET(value) (((value) & 0x00000400) >> 10)
3294 /* Produces a ALT_RSTMGR_PER1MODRST_I2C2 register field value suitable for setting the register. */
3295 #define ALT_RSTMGR_PER1MODRST_I2C2_SET(value) (((value) << 10) & 0x00000400)
3296 
3297 /*
3298  * Field : I2C3 - i2c3
3299  *
3300  * Resets I2C3 controller
3301  *
3302  * Field Access Macros:
3303  *
3304  */
3305 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_I2C3 register field. */
3306 #define ALT_RSTMGR_PER1MODRST_I2C3_LSB 11
3307 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_I2C3 register field. */
3308 #define ALT_RSTMGR_PER1MODRST_I2C3_MSB 11
3309 /* The width in bits of the ALT_RSTMGR_PER1MODRST_I2C3 register field. */
3310 #define ALT_RSTMGR_PER1MODRST_I2C3_WIDTH 1
3311 /* The mask used to set the ALT_RSTMGR_PER1MODRST_I2C3 register field value. */
3312 #define ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK 0x00000800
3313 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_I2C3 register field value. */
3314 #define ALT_RSTMGR_PER1MODRST_I2C3_CLR_MSK 0xfffff7ff
3315 /* The reset value of the ALT_RSTMGR_PER1MODRST_I2C3 register field. */
3316 #define ALT_RSTMGR_PER1MODRST_I2C3_RESET 0x1
3317 /* Extracts the ALT_RSTMGR_PER1MODRST_I2C3 field value from a register. */
3318 #define ALT_RSTMGR_PER1MODRST_I2C3_GET(value) (((value) & 0x00000800) >> 11)
3319 /* Produces a ALT_RSTMGR_PER1MODRST_I2C3 register field value suitable for setting the register. */
3320 #define ALT_RSTMGR_PER1MODRST_I2C3_SET(value) (((value) << 11) & 0x00000800)
3321 
3322 /*
3323  * Field : I2C4 - i2c4
3324  *
3325  * Resets I2C4 controller
3326  *
3327  * Field Access Macros:
3328  *
3329  */
3330 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_I2C4 register field. */
3331 #define ALT_RSTMGR_PER1MODRST_I2C4_LSB 12
3332 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_I2C4 register field. */
3333 #define ALT_RSTMGR_PER1MODRST_I2C4_MSB 12
3334 /* The width in bits of the ALT_RSTMGR_PER1MODRST_I2C4 register field. */
3335 #define ALT_RSTMGR_PER1MODRST_I2C4_WIDTH 1
3336 /* The mask used to set the ALT_RSTMGR_PER1MODRST_I2C4 register field value. */
3337 #define ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK 0x00001000
3338 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_I2C4 register field value. */
3339 #define ALT_RSTMGR_PER1MODRST_I2C4_CLR_MSK 0xffffefff
3340 /* The reset value of the ALT_RSTMGR_PER1MODRST_I2C4 register field. */
3341 #define ALT_RSTMGR_PER1MODRST_I2C4_RESET 0x1
3342 /* Extracts the ALT_RSTMGR_PER1MODRST_I2C4 field value from a register. */
3343 #define ALT_RSTMGR_PER1MODRST_I2C4_GET(value) (((value) & 0x00001000) >> 12)
3344 /* Produces a ALT_RSTMGR_PER1MODRST_I2C4 register field value suitable for setting the register. */
3345 #define ALT_RSTMGR_PER1MODRST_I2C4_SET(value) (((value) << 12) & 0x00001000)
3346 
3347 /*
3348  * Field : UART0 - uart0
3349  *
3350  * Resets UART0
3351  *
3352  * Field Access Macros:
3353  *
3354  */
3355 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_UART0 register field. */
3356 #define ALT_RSTMGR_PER1MODRST_UART0_LSB 16
3357 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_UART0 register field. */
3358 #define ALT_RSTMGR_PER1MODRST_UART0_MSB 16
3359 /* The width in bits of the ALT_RSTMGR_PER1MODRST_UART0 register field. */
3360 #define ALT_RSTMGR_PER1MODRST_UART0_WIDTH 1
3361 /* The mask used to set the ALT_RSTMGR_PER1MODRST_UART0 register field value. */
3362 #define ALT_RSTMGR_PER1MODRST_UART0_SET_MSK 0x00010000
3363 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_UART0 register field value. */
3364 #define ALT_RSTMGR_PER1MODRST_UART0_CLR_MSK 0xfffeffff
3365 /* The reset value of the ALT_RSTMGR_PER1MODRST_UART0 register field. */
3366 #define ALT_RSTMGR_PER1MODRST_UART0_RESET 0x1
3367 /* Extracts the ALT_RSTMGR_PER1MODRST_UART0 field value from a register. */
3368 #define ALT_RSTMGR_PER1MODRST_UART0_GET(value) (((value) & 0x00010000) >> 16)
3369 /* Produces a ALT_RSTMGR_PER1MODRST_UART0 register field value suitable for setting the register. */
3370 #define ALT_RSTMGR_PER1MODRST_UART0_SET(value) (((value) << 16) & 0x00010000)
3371 
3372 /*
3373  * Field : UART1 - uart1
3374  *
3375  * Resets UART1
3376  *
3377  * Field Access Macros:
3378  *
3379  */
3380 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_UART1 register field. */
3381 #define ALT_RSTMGR_PER1MODRST_UART1_LSB 17
3382 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_UART1 register field. */
3383 #define ALT_RSTMGR_PER1MODRST_UART1_MSB 17
3384 /* The width in bits of the ALT_RSTMGR_PER1MODRST_UART1 register field. */
3385 #define ALT_RSTMGR_PER1MODRST_UART1_WIDTH 1
3386 /* The mask used to set the ALT_RSTMGR_PER1MODRST_UART1 register field value. */
3387 #define ALT_RSTMGR_PER1MODRST_UART1_SET_MSK 0x00020000
3388 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_UART1 register field value. */
3389 #define ALT_RSTMGR_PER1MODRST_UART1_CLR_MSK 0xfffdffff
3390 /* The reset value of the ALT_RSTMGR_PER1MODRST_UART1 register field. */
3391 #define ALT_RSTMGR_PER1MODRST_UART1_RESET 0x1
3392 /* Extracts the ALT_RSTMGR_PER1MODRST_UART1 field value from a register. */
3393 #define ALT_RSTMGR_PER1MODRST_UART1_GET(value) (((value) & 0x00020000) >> 17)
3394 /* Produces a ALT_RSTMGR_PER1MODRST_UART1 register field value suitable for setting the register. */
3395 #define ALT_RSTMGR_PER1MODRST_UART1_SET(value) (((value) << 17) & 0x00020000)
3396 
3397 /*
3398  * Field : GPIO0 - gpio0
3399  *
3400  * Resets GPIO0
3401  *
3402  * Field Access Macros:
3403  *
3404  */
3405 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_GPIO0 register field. */
3406 #define ALT_RSTMGR_PER1MODRST_GPIO0_LSB 24
3407 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_GPIO0 register field. */
3408 #define ALT_RSTMGR_PER1MODRST_GPIO0_MSB 24
3409 /* The width in bits of the ALT_RSTMGR_PER1MODRST_GPIO0 register field. */
3410 #define ALT_RSTMGR_PER1MODRST_GPIO0_WIDTH 1
3411 /* The mask used to set the ALT_RSTMGR_PER1MODRST_GPIO0 register field value. */
3412 #define ALT_RSTMGR_PER1MODRST_GPIO0_SET_MSK 0x01000000
3413 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_GPIO0 register field value. */
3414 #define ALT_RSTMGR_PER1MODRST_GPIO0_CLR_MSK 0xfeffffff
3415 /* The reset value of the ALT_RSTMGR_PER1MODRST_GPIO0 register field. */
3416 #define ALT_RSTMGR_PER1MODRST_GPIO0_RESET 0x1
3417 /* Extracts the ALT_RSTMGR_PER1MODRST_GPIO0 field value from a register. */
3418 #define ALT_RSTMGR_PER1MODRST_GPIO0_GET(value) (((value) & 0x01000000) >> 24)
3419 /* Produces a ALT_RSTMGR_PER1MODRST_GPIO0 register field value suitable for setting the register. */
3420 #define ALT_RSTMGR_PER1MODRST_GPIO0_SET(value) (((value) << 24) & 0x01000000)
3421 
3422 /*
3423  * Field : GPIO1 - gpio1
3424  *
3425  * Resets GPIO1
3426  *
3427  * Field Access Macros:
3428  *
3429  */
3430 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_GPIO1 register field. */
3431 #define ALT_RSTMGR_PER1MODRST_GPIO1_LSB 25
3432 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_GPIO1 register field. */
3433 #define ALT_RSTMGR_PER1MODRST_GPIO1_MSB 25
3434 /* The width in bits of the ALT_RSTMGR_PER1MODRST_GPIO1 register field. */
3435 #define ALT_RSTMGR_PER1MODRST_GPIO1_WIDTH 1
3436 /* The mask used to set the ALT_RSTMGR_PER1MODRST_GPIO1 register field value. */
3437 #define ALT_RSTMGR_PER1MODRST_GPIO1_SET_MSK 0x02000000
3438 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_GPIO1 register field value. */
3439 #define ALT_RSTMGR_PER1MODRST_GPIO1_CLR_MSK 0xfdffffff
3440 /* The reset value of the ALT_RSTMGR_PER1MODRST_GPIO1 register field. */
3441 #define ALT_RSTMGR_PER1MODRST_GPIO1_RESET 0x1
3442 /* Extracts the ALT_RSTMGR_PER1MODRST_GPIO1 field value from a register. */
3443 #define ALT_RSTMGR_PER1MODRST_GPIO1_GET(value) (((value) & 0x02000000) >> 25)
3444 /* Produces a ALT_RSTMGR_PER1MODRST_GPIO1 register field value suitable for setting the register. */
3445 #define ALT_RSTMGR_PER1MODRST_GPIO1_SET(value) (((value) << 25) & 0x02000000)
3446 
3447 /*
3448  * Field : GPIO2 - gpio2
3449  *
3450  * Resets GPIO2
3451  *
3452  * Field Access Macros:
3453  *
3454  */
3455 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_GPIO2 register field. */
3456 #define ALT_RSTMGR_PER1MODRST_GPIO2_LSB 26
3457 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_GPIO2 register field. */
3458 #define ALT_RSTMGR_PER1MODRST_GPIO2_MSB 26
3459 /* The width in bits of the ALT_RSTMGR_PER1MODRST_GPIO2 register field. */
3460 #define ALT_RSTMGR_PER1MODRST_GPIO2_WIDTH 1
3461 /* The mask used to set the ALT_RSTMGR_PER1MODRST_GPIO2 register field value. */
3462 #define ALT_RSTMGR_PER1MODRST_GPIO2_SET_MSK 0x04000000
3463 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_GPIO2 register field value. */
3464 #define ALT_RSTMGR_PER1MODRST_GPIO2_CLR_MSK 0xfbffffff
3465 /* The reset value of the ALT_RSTMGR_PER1MODRST_GPIO2 register field. */
3466 #define ALT_RSTMGR_PER1MODRST_GPIO2_RESET 0x1
3467 /* Extracts the ALT_RSTMGR_PER1MODRST_GPIO2 field value from a register. */
3468 #define ALT_RSTMGR_PER1MODRST_GPIO2_GET(value) (((value) & 0x04000000) >> 26)
3469 /* Produces a ALT_RSTMGR_PER1MODRST_GPIO2 register field value suitable for setting the register. */
3470 #define ALT_RSTMGR_PER1MODRST_GPIO2_SET(value) (((value) << 26) & 0x04000000)
3471 
3472 #ifndef __ASSEMBLY__
3473 /*
3474  * WARNING: The C register and register group struct declarations are provided for
3475  * convenience and illustrative purposes. They should, however, be used with
3476  * caution as the C language standard provides no guarantees about the alignment or
3477  * atomicity of device memory accesses. The recommended practice for writing
3478  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3479  * alt_write_word() functions.
3480  *
3481  * The struct declaration for register ALT_RSTMGR_PER1MODRST.
3482  */
3483 struct ALT_RSTMGR_PER1MODRST_s
3484 {
3485  uint32_t watchdog0 : 1; /* Watch Dog0 */
3486  uint32_t watchdog1 : 1; /* Watch Dog1 */
3487  uint32_t l4systimer0 : 1; /* l4systimer0 */
3488  uint32_t l4systimer1 : 1; /* l4sys_timer1 */
3489  uint32_t sptimer0 : 1; /* SP Timer 0 */
3490  uint32_t sptimer1 : 1; /* SP Timer 1 */
3491  uint32_t : 2; /* *UNDEFINED* */
3492  uint32_t i2c0 : 1; /* I2C0 */
3493  uint32_t i2c1 : 1; /* I2C1 */
3494  uint32_t i2c2 : 1; /* I2C2 */
3495  uint32_t i2c3 : 1; /* I2C3 */
3496  uint32_t i2c4 : 1; /* I2C4 */
3497  uint32_t : 3; /* *UNDEFINED* */
3498  uint32_t uart0 : 1; /* UART0 */
3499  uint32_t uart1 : 1; /* UART1 */
3500  uint32_t : 6; /* *UNDEFINED* */
3501  uint32_t gpio0 : 1; /* GPIO0 */
3502  uint32_t gpio1 : 1; /* GPIO1 */
3503  uint32_t gpio2 : 1; /* GPIO2 */
3504  uint32_t : 5; /* *UNDEFINED* */
3505 };
3506 
3507 /* The typedef declaration for register ALT_RSTMGR_PER1MODRST. */
3508 typedef volatile struct ALT_RSTMGR_PER1MODRST_s ALT_RSTMGR_PER1MODRST_t;
3509 #endif /* __ASSEMBLY__ */
3510 
3511 /* The reset value of the ALT_RSTMGR_PER1MODRST register. */
3512 #define ALT_RSTMGR_PER1MODRST_RESET 0x07031f3f
3513 /* The byte offset of the ALT_RSTMGR_PER1MODRST register from the beginning of the component. */
3514 #define ALT_RSTMGR_PER1MODRST_OFST 0x28
3515 
3516 /*
3517  * Register : Bridge Module Reset Register - brgmodrst
3518  *
3519  * The BRGMODRST register is used by software to trigger module resets (individual
3520  * module reset signals). Software explicitly asserts and de-asserts module reset
3521  * signals by writing bits in the appropriate *MODRST register. It is up to
3522  * software to ensure module reset signals are asserted for the appropriate length
3523  * of time and are de-asserted in the correct order. It is also up to software to
3524  * not assert a module reset signal that would prevent software from de-asserting
3525  * the module reset signal. For example, software should not assert the module
3526  * reset to the CPU executing the software.
3527  *
3528  * Software writes a bit to 1 to assert the module reset signal and to 0 to de-
3529  * assert the module reset signal.
3530  *
3531  * All fields are reset by a cold reset.All fields are also reset by a warm reset
3532  * if not masked by the corresponding BRGWARMMASK field.
3533  *
3534  * The reset value of all fields is 1. This holds the corresponding module in reset
3535  * until software is ready to release the module from reset by writing 0 to its
3536  * field.
3537  *
3538  * Register Layout
3539  *
3540  * Bits | Access | Reset | Description
3541  * :-------|:-------|:------|:------------------
3542  * [0] | RW | 0x1 | HPS2FPGA Bridge
3543  * [1] | RW | 0x1 | LWHPS2FPGA Bridge
3544  * [2] | RW | 0x1 | FPGA2HPS Bridge
3545  * [3] | RW | 0x1 | F2S SDRAM0 Bridge
3546  * [4] | RW | 0x1 | F2S SDRAM1 Bridge
3547  * [5] | RW | 0x1 | F2S SDRAM2 Bridge
3548  * [6] | RW | 0x1 | DDR Scheduler
3549  * [31:7] | ??? | 0x0 | *UNDEFINED*
3550  *
3551  */
3552 /*
3553  * Field : HPS2FPGA Bridge - hps2fpga
3554  *
3555  * Resets HPS2FPGA Bridge
3556  *
3557  * Field Access Macros:
3558  *
3559  */
3560 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_H2F register field. */
3561 #define ALT_RSTMGR_BRGMODRST_H2F_LSB 0
3562 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_H2F register field. */
3563 #define ALT_RSTMGR_BRGMODRST_H2F_MSB 0
3564 /* The width in bits of the ALT_RSTMGR_BRGMODRST_H2F register field. */
3565 #define ALT_RSTMGR_BRGMODRST_H2F_WIDTH 1
3566 /* The mask used to set the ALT_RSTMGR_BRGMODRST_H2F register field value. */
3567 #define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK 0x00000001
3568 /* The mask used to clear the ALT_RSTMGR_BRGMODRST_H2F register field value. */
3569 #define ALT_RSTMGR_BRGMODRST_H2F_CLR_MSK 0xfffffffe
3570 /* The reset value of the ALT_RSTMGR_BRGMODRST_H2F register field. */
3571 #define ALT_RSTMGR_BRGMODRST_H2F_RESET 0x1
3572 /* Extracts the ALT_RSTMGR_BRGMODRST_H2F field value from a register. */
3573 #define ALT_RSTMGR_BRGMODRST_H2F_GET(value) (((value) & 0x00000001) >> 0)
3574 /* Produces a ALT_RSTMGR_BRGMODRST_H2F register field value suitable for setting the register. */
3575 #define ALT_RSTMGR_BRGMODRST_H2F_SET(value) (((value) << 0) & 0x00000001)
3576 
3577 /*
3578  * Field : LWHPS2FPGA Bridge - lwhps2fpga
3579  *
3580  * Resets LWHPS2FPGA Bridge
3581  *
3582  * Field Access Macros:
3583  *
3584  */
3585 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */
3586 #define ALT_RSTMGR_BRGMODRST_LWH2F_LSB 1
3587 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */
3588 #define ALT_RSTMGR_BRGMODRST_LWH2F_MSB 1
3589 /* The width in bits of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */
3590 #define ALT_RSTMGR_BRGMODRST_LWH2F_WIDTH 1
3591 /* The mask used to set the ALT_RSTMGR_BRGMODRST_LWH2F register field value. */
3592 #define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK 0x00000002
3593 /* The mask used to clear the ALT_RSTMGR_BRGMODRST_LWH2F register field value. */
3594 #define ALT_RSTMGR_BRGMODRST_LWH2F_CLR_MSK 0xfffffffd
3595 /* The reset value of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */
3596 #define ALT_RSTMGR_BRGMODRST_LWH2F_RESET 0x1
3597 /* Extracts the ALT_RSTMGR_BRGMODRST_LWH2F field value from a register. */
3598 #define ALT_RSTMGR_BRGMODRST_LWH2F_GET(value) (((value) & 0x00000002) >> 1)
3599 /* Produces a ALT_RSTMGR_BRGMODRST_LWH2F register field value suitable for setting the register. */
3600 #define ALT_RSTMGR_BRGMODRST_LWH2F_SET(value) (((value) << 1) & 0x00000002)
3601 
3602 /*
3603  * Field : FPGA2HPS Bridge - fpga2hps
3604  *
3605  * Resets FPGA2HPS Bridge
3606  *
3607  * Field Access Macros:
3608  *
3609  */
3610 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_F2H register field. */
3611 #define ALT_RSTMGR_BRGMODRST_F2H_LSB 2
3612 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_F2H register field. */
3613 #define ALT_RSTMGR_BRGMODRST_F2H_MSB 2
3614 /* The width in bits of the ALT_RSTMGR_BRGMODRST_F2H register field. */
3615 #define ALT_RSTMGR_BRGMODRST_F2H_WIDTH 1
3616 /* The mask used to set the ALT_RSTMGR_BRGMODRST_F2H register field value. */
3617 #define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK 0x00000004
3618 /* The mask used to clear the ALT_RSTMGR_BRGMODRST_F2H register field value. */
3619 #define ALT_RSTMGR_BRGMODRST_F2H_CLR_MSK 0xfffffffb
3620 /* The reset value of the ALT_RSTMGR_BRGMODRST_F2H register field. */
3621 #define ALT_RSTMGR_BRGMODRST_F2H_RESET 0x1
3622 /* Extracts the ALT_RSTMGR_BRGMODRST_F2H field value from a register. */
3623 #define ALT_RSTMGR_BRGMODRST_F2H_GET(value) (((value) & 0x00000004) >> 2)
3624 /* Produces a ALT_RSTMGR_BRGMODRST_F2H register field value suitable for setting the register. */
3625 #define ALT_RSTMGR_BRGMODRST_F2H_SET(value) (((value) << 2) & 0x00000004)
3626 
3627 /*
3628  * Field : F2S SDRAM0 Bridge - f2ssdram0
3629  *
3630  * Resets F2S_SDRAM0 Bridge
3631  *
3632  * Field Access Macros:
3633  *
3634  */
3635 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_F2SSDRAM0 register field. */
3636 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_LSB 3
3637 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_F2SSDRAM0 register field. */
3638 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_MSB 3
3639 /* The width in bits of the ALT_RSTMGR_BRGMODRST_F2SSDRAM0 register field. */
3640 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_WIDTH 1
3641 /* The mask used to set the ALT_RSTMGR_BRGMODRST_F2SSDRAM0 register field value. */
3642 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK 0x00000008
3643 /* The mask used to clear the ALT_RSTMGR_BRGMODRST_F2SSDRAM0 register field value. */
3644 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_CLR_MSK 0xfffffff7
3645 /* The reset value of the ALT_RSTMGR_BRGMODRST_F2SSDRAM0 register field. */
3646 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_RESET 0x1
3647 /* Extracts the ALT_RSTMGR_BRGMODRST_F2SSDRAM0 field value from a register. */
3648 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_GET(value) (((value) & 0x00000008) >> 3)
3649 /* Produces a ALT_RSTMGR_BRGMODRST_F2SSDRAM0 register field value suitable for setting the register. */
3650 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET(value) (((value) << 3) & 0x00000008)
3651 
3652 /*
3653  * Field : F2S SDRAM1 Bridge - f2ssdram1
3654  *
3655  * Resets F2S_SDRAM1 Bridge
3656  *
3657  * Field Access Macros:
3658  *
3659  */
3660 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_F2SSDRAM1 register field. */
3661 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_LSB 4
3662 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_F2SSDRAM1 register field. */
3663 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_MSB 4
3664 /* The width in bits of the ALT_RSTMGR_BRGMODRST_F2SSDRAM1 register field. */
3665 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_WIDTH 1
3666 /* The mask used to set the ALT_RSTMGR_BRGMODRST_F2SSDRAM1 register field value. */
3667 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK 0x00000010
3668 /* The mask used to clear the ALT_RSTMGR_BRGMODRST_F2SSDRAM1 register field value. */
3669 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_CLR_MSK 0xffffffef
3670 /* The reset value of the ALT_RSTMGR_BRGMODRST_F2SSDRAM1 register field. */
3671 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_RESET 0x1
3672 /* Extracts the ALT_RSTMGR_BRGMODRST_F2SSDRAM1 field value from a register. */
3673 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_GET(value) (((value) & 0x00000010) >> 4)
3674 /* Produces a ALT_RSTMGR_BRGMODRST_F2SSDRAM1 register field value suitable for setting the register. */
3675 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET(value) (((value) << 4) & 0x00000010)
3676 
3677 /*
3678  * Field : F2S SDRAM2 Bridge - f2ssdram2
3679  *
3680  * Resets F2S_SDRAM2 Bridge
3681  *
3682  * Field Access Macros:
3683  *
3684  */
3685 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_F2SSDRAM2 register field. */
3686 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_LSB 5
3687 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_F2SSDRAM2 register field. */
3688 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_MSB 5
3689 /* The width in bits of the ALT_RSTMGR_BRGMODRST_F2SSDRAM2 register field. */
3690 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_WIDTH 1
3691 /* The mask used to set the ALT_RSTMGR_BRGMODRST_F2SSDRAM2 register field value. */
3692 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK 0x00000020
3693 /* The mask used to clear the ALT_RSTMGR_BRGMODRST_F2SSDRAM2 register field value. */
3694 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_CLR_MSK 0xffffffdf
3695 /* The reset value of the ALT_RSTMGR_BRGMODRST_F2SSDRAM2 register field. */
3696 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_RESET 0x1
3697 /* Extracts the ALT_RSTMGR_BRGMODRST_F2SSDRAM2 field value from a register. */
3698 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_GET(value) (((value) & 0x00000020) >> 5)
3699 /* Produces a ALT_RSTMGR_BRGMODRST_F2SSDRAM2 register field value suitable for setting the register. */
3700 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET(value) (((value) << 5) & 0x00000020)
3701 
3702 /*
3703  * Field : DDR Scheduler - ddrsch
3704  *
3705  * Resets logic in the DDR Scheduler in the NOC.
3706  *
3707  * Field Access Macros:
3708  *
3709  */
3710 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_DDRSCH register field. */
3711 #define ALT_RSTMGR_BRGMODRST_DDRSCH_LSB 6
3712 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_DDRSCH register field. */
3713 #define ALT_RSTMGR_BRGMODRST_DDRSCH_MSB 6
3714 /* The width in bits of the ALT_RSTMGR_BRGMODRST_DDRSCH register field. */
3715 #define ALT_RSTMGR_BRGMODRST_DDRSCH_WIDTH 1
3716 /* The mask used to set the ALT_RSTMGR_BRGMODRST_DDRSCH register field value. */
3717 #define ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK 0x00000040
3718 /* The mask used to clear the ALT_RSTMGR_BRGMODRST_DDRSCH register field value. */
3719 #define ALT_RSTMGR_BRGMODRST_DDRSCH_CLR_MSK 0xffffffbf
3720 /* The reset value of the ALT_RSTMGR_BRGMODRST_DDRSCH register field. */
3721 #define ALT_RSTMGR_BRGMODRST_DDRSCH_RESET 0x1
3722 /* Extracts the ALT_RSTMGR_BRGMODRST_DDRSCH field value from a register. */
3723 #define ALT_RSTMGR_BRGMODRST_DDRSCH_GET(value) (((value) & 0x00000040) >> 6)
3724 /* Produces a ALT_RSTMGR_BRGMODRST_DDRSCH register field value suitable for setting the register. */
3725 #define ALT_RSTMGR_BRGMODRST_DDRSCH_SET(value) (((value) << 6) & 0x00000040)
3726 
3727 #ifndef __ASSEMBLY__
3728 /*
3729  * WARNING: The C register and register group struct declarations are provided for
3730  * convenience and illustrative purposes. They should, however, be used with
3731  * caution as the C language standard provides no guarantees about the alignment or
3732  * atomicity of device memory accesses. The recommended practice for writing
3733  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3734  * alt_write_word() functions.
3735  *
3736  * The struct declaration for register ALT_RSTMGR_BRGMODRST.
3737  */
3738 struct ALT_RSTMGR_BRGMODRST_s
3739 {
3740  uint32_t hps2fpga : 1; /* HPS2FPGA Bridge */
3741  uint32_t lwhps2fpga : 1; /* LWHPS2FPGA Bridge */
3742  uint32_t fpga2hps : 1; /* FPGA2HPS Bridge */
3743  uint32_t f2ssdram0 : 1; /* F2S SDRAM0 Bridge */
3744  uint32_t f2ssdram1 : 1; /* F2S SDRAM1 Bridge */
3745  uint32_t f2ssdram2 : 1; /* F2S SDRAM2 Bridge */
3746  uint32_t ddrsch : 1; /* DDR Scheduler */
3747  uint32_t : 25; /* *UNDEFINED* */
3748 };
3749 
3750 /* The typedef declaration for register ALT_RSTMGR_BRGMODRST. */
3751 typedef volatile struct ALT_RSTMGR_BRGMODRST_s ALT_RSTMGR_BRGMODRST_t;
3752 #endif /* __ASSEMBLY__ */
3753 
3754 /* The reset value of the ALT_RSTMGR_BRGMODRST register. */
3755 #define ALT_RSTMGR_BRGMODRST_RESET 0x0000007f
3756 /* The byte offset of the ALT_RSTMGR_BRGMODRST register from the beginning of the component. */
3757 #define ALT_RSTMGR_BRGMODRST_OFST 0x2c
3758 
3759 /*
3760  * Register : SYSTEM Module Reset Register - sysmodrst
3761  *
3762  * The SYSMODRST register is used by software to trigger module resets (individual
3763  * module reset signals). Software explicitly asserts and de-asserts module reset
3764  * signals by writing bits in the appropriate *MODRST register. It is up to
3765  * software to ensure module reset signals are asserted for the appropriate length
3766  * of time and are de-asserted in the correct order. It is also up to software to
3767  * not assert a module reset signal that would prevent software from de-asserting
3768  * the module reset signal. For example, software should not assert the module
3769  * reset to the CPU executing the software.
3770  *
3771  * Software writes a bit to 1 to assert the module reset signal and to 0 to de-
3772  * assert the module reset signal.
3773  *
3774  * All fields are only reset by a cold reset
3775  *
3776  * Register Layout
3777  *
3778  * Bits | Access | Reset | Description
3779  * :-------|:-------|:------|:--------------------------------
3780  * [0] | RW | 0x0 | Boot ROM
3781  * [1] | RW | 0x0 | On-chip RAM
3782  * [2] | ??? | 0x0 | *UNDEFINED*
3783  * [3] | RW | 0x0 | FPGA Manager
3784  * [4] | RW | 0x0 | HPS to FPGA Core (Cold or Warm)
3785  * [5] | RW | 0x0 | System/Debug
3786  * [6] | RW | 0x0 | On-chip RAM ECC OCP Diagnostic
3787  * [31:7] | ??? | 0x0 | *UNDEFINED*
3788  *
3789  */
3790 /*
3791  * Field : Boot ROM - rom
3792  *
3793  * Resets Boot ROM
3794  *
3795  * Field Access Macros:
3796  *
3797  */
3798 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_SYSMODRST_ROM register field. */
3799 #define ALT_RSTMGR_SYSMODRST_ROM_LSB 0
3800 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_SYSMODRST_ROM register field. */
3801 #define ALT_RSTMGR_SYSMODRST_ROM_MSB 0
3802 /* The width in bits of the ALT_RSTMGR_SYSMODRST_ROM register field. */
3803 #define ALT_RSTMGR_SYSMODRST_ROM_WIDTH 1
3804 /* The mask used to set the ALT_RSTMGR_SYSMODRST_ROM register field value. */
3805 #define ALT_RSTMGR_SYSMODRST_ROM_SET_MSK 0x00000001
3806 /* The mask used to clear the ALT_RSTMGR_SYSMODRST_ROM register field value. */
3807 #define ALT_RSTMGR_SYSMODRST_ROM_CLR_MSK 0xfffffffe
3808 /* The reset value of the ALT_RSTMGR_SYSMODRST_ROM register field. */
3809 #define ALT_RSTMGR_SYSMODRST_ROM_RESET 0x0
3810 /* Extracts the ALT_RSTMGR_SYSMODRST_ROM field value from a register. */
3811 #define ALT_RSTMGR_SYSMODRST_ROM_GET(value) (((value) & 0x00000001) >> 0)
3812 /* Produces a ALT_RSTMGR_SYSMODRST_ROM register field value suitable for setting the register. */
3813 #define ALT_RSTMGR_SYSMODRST_ROM_SET(value) (((value) << 0) & 0x00000001)
3814 
3815 /*
3816  * Field : On-chip RAM - ocram
3817  *
3818  * Resets On-chip RAM
3819  *
3820  * Field Access Macros:
3821  *
3822  */
3823 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_SYSMODRST_OCRAM register field. */
3824 #define ALT_RSTMGR_SYSMODRST_OCRAM_LSB 1
3825 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_SYSMODRST_OCRAM register field. */
3826 #define ALT_RSTMGR_SYSMODRST_OCRAM_MSB 1
3827 /* The width in bits of the ALT_RSTMGR_SYSMODRST_OCRAM register field. */
3828 #define ALT_RSTMGR_SYSMODRST_OCRAM_WIDTH 1
3829 /* The mask used to set the ALT_RSTMGR_SYSMODRST_OCRAM register field value. */
3830 #define ALT_RSTMGR_SYSMODRST_OCRAM_SET_MSK 0x00000002
3831 /* The mask used to clear the ALT_RSTMGR_SYSMODRST_OCRAM register field value. */
3832 #define ALT_RSTMGR_SYSMODRST_OCRAM_CLR_MSK 0xfffffffd
3833 /* The reset value of the ALT_RSTMGR_SYSMODRST_OCRAM register field. */
3834 #define ALT_RSTMGR_SYSMODRST_OCRAM_RESET 0x0
3835 /* Extracts the ALT_RSTMGR_SYSMODRST_OCRAM field value from a register. */
3836 #define ALT_RSTMGR_SYSMODRST_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
3837 /* Produces a ALT_RSTMGR_SYSMODRST_OCRAM register field value suitable for setting the register. */
3838 #define ALT_RSTMGR_SYSMODRST_OCRAM_SET(value) (((value) << 1) & 0x00000002)
3839 
3840 /*
3841  * Field : FPGA Manager - fpgamgr
3842  *
3843  * Resets FPGA Manager
3844  *
3845  * Field Access Macros:
3846  *
3847  */
3848 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_SYSMODRST_FPGAMGR register field. */
3849 #define ALT_RSTMGR_SYSMODRST_FPGAMGR_LSB 3
3850 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_SYSMODRST_FPGAMGR register field. */
3851 #define ALT_RSTMGR_SYSMODRST_FPGAMGR_MSB 3
3852 /* The width in bits of the ALT_RSTMGR_SYSMODRST_FPGAMGR register field. */
3853 #define ALT_RSTMGR_SYSMODRST_FPGAMGR_WIDTH 1
3854 /* The mask used to set the ALT_RSTMGR_SYSMODRST_FPGAMGR register field value. */
3855 #define ALT_RSTMGR_SYSMODRST_FPGAMGR_SET_MSK 0x00000008
3856 /* The mask used to clear the ALT_RSTMGR_SYSMODRST_FPGAMGR register field value. */
3857 #define ALT_RSTMGR_SYSMODRST_FPGAMGR_CLR_MSK 0xfffffff7
3858 /* The reset value of the ALT_RSTMGR_SYSMODRST_FPGAMGR register field. */
3859 #define ALT_RSTMGR_SYSMODRST_FPGAMGR_RESET 0x0
3860 /* Extracts the ALT_RSTMGR_SYSMODRST_FPGAMGR field value from a register. */
3861 #define ALT_RSTMGR_SYSMODRST_FPGAMGR_GET(value) (((value) & 0x00000008) >> 3)
3862 /* Produces a ALT_RSTMGR_SYSMODRST_FPGAMGR register field value suitable for setting the register. */
3863 #define ALT_RSTMGR_SYSMODRST_FPGAMGR_SET(value) (((value) << 3) & 0x00000008)
3864 
3865 /*
3866  * Field : HPS to FPGA Core (Cold or Warm) - s2f
3867  *
3868  * Resets logic in FPGA core that doesn't differentiate between HPS cold and warm
3869  * resets
3870  *
3871  * Field Access Macros:
3872  *
3873  */
3874 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_SYSMODRST_S2F register field. */
3875 #define ALT_RSTMGR_SYSMODRST_S2F_LSB 4
3876 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_SYSMODRST_S2F register field. */
3877 #define ALT_RSTMGR_SYSMODRST_S2F_MSB 4
3878 /* The width in bits of the ALT_RSTMGR_SYSMODRST_S2F register field. */
3879 #define ALT_RSTMGR_SYSMODRST_S2F_WIDTH 1
3880 /* The mask used to set the ALT_RSTMGR_SYSMODRST_S2F register field value. */
3881 #define ALT_RSTMGR_SYSMODRST_S2F_SET_MSK 0x00000010
3882 /* The mask used to clear the ALT_RSTMGR_SYSMODRST_S2F register field value. */
3883 #define ALT_RSTMGR_SYSMODRST_S2F_CLR_MSK 0xffffffef
3884 /* The reset value of the ALT_RSTMGR_SYSMODRST_S2F register field. */
3885 #define ALT_RSTMGR_SYSMODRST_S2F_RESET 0x0
3886 /* Extracts the ALT_RSTMGR_SYSMODRST_S2F field value from a register. */
3887 #define ALT_RSTMGR_SYSMODRST_S2F_GET(value) (((value) & 0x00000010) >> 4)
3888 /* Produces a ALT_RSTMGR_SYSMODRST_S2F register field value suitable for setting the register. */
3889 #define ALT_RSTMGR_SYSMODRST_S2F_SET(value) (((value) << 4) & 0x00000010)
3890 
3891 /*
3892  * Field : System/Debug - sysdbg
3893  *
3894  * Resets logic that spans the system and debug domains.
3895  *
3896  * Field Access Macros:
3897  *
3898  */
3899 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_SYSMODRST_SYSDBG register field. */
3900 #define ALT_RSTMGR_SYSMODRST_SYSDBG_LSB 5
3901 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_SYSMODRST_SYSDBG register field. */
3902 #define ALT_RSTMGR_SYSMODRST_SYSDBG_MSB 5
3903 /* The width in bits of the ALT_RSTMGR_SYSMODRST_SYSDBG register field. */
3904 #define ALT_RSTMGR_SYSMODRST_SYSDBG_WIDTH 1
3905 /* The mask used to set the ALT_RSTMGR_SYSMODRST_SYSDBG register field value. */
3906 #define ALT_RSTMGR_SYSMODRST_SYSDBG_SET_MSK 0x00000020
3907 /* The mask used to clear the ALT_RSTMGR_SYSMODRST_SYSDBG register field value. */
3908 #define ALT_RSTMGR_SYSMODRST_SYSDBG_CLR_MSK 0xffffffdf
3909 /* The reset value of the ALT_RSTMGR_SYSMODRST_SYSDBG register field. */
3910 #define ALT_RSTMGR_SYSMODRST_SYSDBG_RESET 0x0
3911 /* Extracts the ALT_RSTMGR_SYSMODRST_SYSDBG field value from a register. */
3912 #define ALT_RSTMGR_SYSMODRST_SYSDBG_GET(value) (((value) & 0x00000020) >> 5)
3913 /* Produces a ALT_RSTMGR_SYSMODRST_SYSDBG register field value suitable for setting the register. */
3914 #define ALT_RSTMGR_SYSMODRST_SYSDBG_SET(value) (((value) << 5) & 0x00000020)
3915 
3916 /*
3917  * Field : On-chip RAM ECC OCP Diagnostic - ocramocp
3918  *
3919  * Resets On-chip RAM ECC OCP Diagnostic module
3920  *
3921  * Field Access Macros:
3922  *
3923  */
3924 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_SYSMODRST_OCRAMOCP register field. */
3925 #define ALT_RSTMGR_SYSMODRST_OCRAMOCP_LSB 6
3926 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_SYSMODRST_OCRAMOCP register field. */
3927 #define ALT_RSTMGR_SYSMODRST_OCRAMOCP_MSB 6
3928 /* The width in bits of the ALT_RSTMGR_SYSMODRST_OCRAMOCP register field. */
3929 #define ALT_RSTMGR_SYSMODRST_OCRAMOCP_WIDTH 1
3930 /* The mask used to set the ALT_RSTMGR_SYSMODRST_OCRAMOCP register field value. */
3931 #define ALT_RSTMGR_SYSMODRST_OCRAMOCP_SET_MSK 0x00000040
3932 /* The mask used to clear the ALT_RSTMGR_SYSMODRST_OCRAMOCP register field value. */
3933 #define ALT_RSTMGR_SYSMODRST_OCRAMOCP_CLR_MSK 0xffffffbf
3934 /* The reset value of the ALT_RSTMGR_SYSMODRST_OCRAMOCP register field. */
3935 #define ALT_RSTMGR_SYSMODRST_OCRAMOCP_RESET 0x0
3936 /* Extracts the ALT_RSTMGR_SYSMODRST_OCRAMOCP field value from a register. */
3937 #define ALT_RSTMGR_SYSMODRST_OCRAMOCP_GET(value) (((value) & 0x00000040) >> 6)
3938 /* Produces a ALT_RSTMGR_SYSMODRST_OCRAMOCP register field value suitable for setting the register. */
3939 #define ALT_RSTMGR_SYSMODRST_OCRAMOCP_SET(value) (((value) << 6) & 0x00000040)
3940 
3941 #ifndef __ASSEMBLY__
3942 /*
3943  * WARNING: The C register and register group struct declarations are provided for
3944  * convenience and illustrative purposes. They should, however, be used with
3945  * caution as the C language standard provides no guarantees about the alignment or
3946  * atomicity of device memory accesses. The recommended practice for writing
3947  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3948  * alt_write_word() functions.
3949  *
3950  * The struct declaration for register ALT_RSTMGR_SYSMODRST.
3951  */
3952 struct ALT_RSTMGR_SYSMODRST_s
3953 {
3954  uint32_t rom : 1; /* Boot ROM */
3955  uint32_t ocram : 1; /* On-chip RAM */
3956  uint32_t : 1; /* *UNDEFINED* */
3957  uint32_t fpgamgr : 1; /* FPGA Manager */
3958  uint32_t s2f : 1; /* HPS to FPGA Core (Cold or Warm) */
3959  uint32_t sysdbg : 1; /* System/Debug */
3960  uint32_t ocramocp : 1; /* On-chip RAM ECC OCP Diagnostic */
3961  uint32_t : 25; /* *UNDEFINED* */
3962 };
3963 
3964 /* The typedef declaration for register ALT_RSTMGR_SYSMODRST. */
3965 typedef volatile struct ALT_RSTMGR_SYSMODRST_s ALT_RSTMGR_SYSMODRST_t;
3966 #endif /* __ASSEMBLY__ */
3967 
3968 /* The reset value of the ALT_RSTMGR_SYSMODRST register. */
3969 #define ALT_RSTMGR_SYSMODRST_RESET 0x00000000
3970 /* The byte offset of the ALT_RSTMGR_SYSMODRST register from the beginning of the component. */
3971 #define ALT_RSTMGR_SYSMODRST_OFST 0x30
3972 
3973 /*
3974  * Register : COLD Module Reset Register - coldmodrst
3975  *
3976  * The COLDMODRST register is used by software to trigger module resets (individual
3977  * module reset signals). Software explicitly asserts and de-asserts module reset
3978  * signals by writing bits in the appropriate *MODRST register. It is up to
3979  * software to ensure module reset signals are asserted for the appropriate length
3980  * of time and are de-asserted in the correct order. It is also up to software to
3981  * not assert a module reset signal that would prevent software from de-asserting
3982  * the module reset signal. For example, software should not assert the module
3983  * reset to the CPU executing the software.
3984  *
3985  * Software writes a bit to 1 to assert the module reset signal and to 0 to de-
3986  * assert the module reset signal.
3987  *
3988  * All fields are only reset by a cold reset
3989  *
3990  * Register Layout
3991  *
3992  * Bits | Access | Reset | Description
3993  * :-------|:-------|:------|:-----------------------------
3994  * [0] | RW | 0x0 | Clock Manager
3995  * [2:1] | ??? | 0x0 | *UNDEFINED*
3996  * [3] | RW | 0x0 | HPS to FPGA Core (Cold-only)
3997  * [4] | RW | 0x0 | Timestamp
3998  * [5] | RW | 0x0 | TAP Controller
3999  * [6] | RW | 0x0 | HMC Cold Reset
4000  * [7] | RW | 0x0 | IO Manager (Cold-only)
4001  * [31:8] | ??? | 0x0 | *UNDEFINED*
4002  *
4003  */
4004 /*
4005  * Field : Clock Manager - clkmgrcold
4006  *
4007  * Resets Clock Manager (cold reset only)
4008  *
4009  * Field Access Macros:
4010  *
4011  */
4012 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COLDMODRST_CLKMGRCOLD register field. */
4013 #define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_LSB 0
4014 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COLDMODRST_CLKMGRCOLD register field. */
4015 #define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_MSB 0
4016 /* The width in bits of the ALT_RSTMGR_COLDMODRST_CLKMGRCOLD register field. */
4017 #define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_WIDTH 1
4018 /* The mask used to set the ALT_RSTMGR_COLDMODRST_CLKMGRCOLD register field value. */
4019 #define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_SET_MSK 0x00000001
4020 /* The mask used to clear the ALT_RSTMGR_COLDMODRST_CLKMGRCOLD register field value. */
4021 #define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_CLR_MSK 0xfffffffe
4022 /* The reset value of the ALT_RSTMGR_COLDMODRST_CLKMGRCOLD register field. */
4023 #define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_RESET 0x0
4024 /* Extracts the ALT_RSTMGR_COLDMODRST_CLKMGRCOLD field value from a register. */
4025 #define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_GET(value) (((value) & 0x00000001) >> 0)
4026 /* Produces a ALT_RSTMGR_COLDMODRST_CLKMGRCOLD register field value suitable for setting the register. */
4027 #define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_SET(value) (((value) << 0) & 0x00000001)
4028 
4029 /*
4030  * Field : HPS to FPGA Core (Cold-only) - s2fcold
4031  *
4032  * Resets logic in FPGA core that is only reset by a cold reset (ignores warm
4033  * reset)
4034  *
4035  * Field Access Macros:
4036  *
4037  */
4038 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COLDMODRST_S2FCOLD register field. */
4039 #define ALT_RSTMGR_COLDMODRST_S2FCOLD_LSB 3
4040 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COLDMODRST_S2FCOLD register field. */
4041 #define ALT_RSTMGR_COLDMODRST_S2FCOLD_MSB 3
4042 /* The width in bits of the ALT_RSTMGR_COLDMODRST_S2FCOLD register field. */
4043 #define ALT_RSTMGR_COLDMODRST_S2FCOLD_WIDTH 1
4044 /* The mask used to set the ALT_RSTMGR_COLDMODRST_S2FCOLD register field value. */
4045 #define ALT_RSTMGR_COLDMODRST_S2FCOLD_SET_MSK 0x00000008
4046 /* The mask used to clear the ALT_RSTMGR_COLDMODRST_S2FCOLD register field value. */
4047 #define ALT_RSTMGR_COLDMODRST_S2FCOLD_CLR_MSK 0xfffffff7
4048 /* The reset value of the ALT_RSTMGR_COLDMODRST_S2FCOLD register field. */
4049 #define ALT_RSTMGR_COLDMODRST_S2FCOLD_RESET 0x0
4050 /* Extracts the ALT_RSTMGR_COLDMODRST_S2FCOLD field value from a register. */
4051 #define ALT_RSTMGR_COLDMODRST_S2FCOLD_GET(value) (((value) & 0x00000008) >> 3)
4052 /* Produces a ALT_RSTMGR_COLDMODRST_S2FCOLD register field value suitable for setting the register. */
4053 #define ALT_RSTMGR_COLDMODRST_S2FCOLD_SET(value) (((value) << 3) & 0x00000008)
4054 
4055 /*
4056  * Field : Timestamp - timestampcold
4057  *
4058  * Resets debug timestamp to 0 (cold reset only)
4059  *
4060  * Field Access Macros:
4061  *
4062  */
4063 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COLDMODRST_TSCOLD register field. */
4064 #define ALT_RSTMGR_COLDMODRST_TSCOLD_LSB 4
4065 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COLDMODRST_TSCOLD register field. */
4066 #define ALT_RSTMGR_COLDMODRST_TSCOLD_MSB 4
4067 /* The width in bits of the ALT_RSTMGR_COLDMODRST_TSCOLD register field. */
4068 #define ALT_RSTMGR_COLDMODRST_TSCOLD_WIDTH 1
4069 /* The mask used to set the ALT_RSTMGR_COLDMODRST_TSCOLD register field value. */
4070 #define ALT_RSTMGR_COLDMODRST_TSCOLD_SET_MSK 0x00000010
4071 /* The mask used to clear the ALT_RSTMGR_COLDMODRST_TSCOLD register field value. */
4072 #define ALT_RSTMGR_COLDMODRST_TSCOLD_CLR_MSK 0xffffffef
4073 /* The reset value of the ALT_RSTMGR_COLDMODRST_TSCOLD register field. */
4074 #define ALT_RSTMGR_COLDMODRST_TSCOLD_RESET 0x0
4075 /* Extracts the ALT_RSTMGR_COLDMODRST_TSCOLD field value from a register. */
4076 #define ALT_RSTMGR_COLDMODRST_TSCOLD_GET(value) (((value) & 0x00000010) >> 4)
4077 /* Produces a ALT_RSTMGR_COLDMODRST_TSCOLD register field value suitable for setting the register. */
4078 #define ALT_RSTMGR_COLDMODRST_TSCOLD_SET(value) (((value) << 4) & 0x00000010)
4079 
4080 /*
4081  * Field : TAP Controller - tapcold
4082  *
4083  * Resets portion of DAP JTAG TAP controller no reset by a debug probe reset (i.e.
4084  * nTRST pin). Cold reset only.
4085  *
4086  * Field Access Macros:
4087  *
4088  */
4089 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COLDMODRST_TAPCOLD register field. */
4090 #define ALT_RSTMGR_COLDMODRST_TAPCOLD_LSB 5
4091 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COLDMODRST_TAPCOLD register field. */
4092 #define ALT_RSTMGR_COLDMODRST_TAPCOLD_MSB 5
4093 /* The width in bits of the ALT_RSTMGR_COLDMODRST_TAPCOLD register field. */
4094 #define ALT_RSTMGR_COLDMODRST_TAPCOLD_WIDTH 1
4095 /* The mask used to set the ALT_RSTMGR_COLDMODRST_TAPCOLD register field value. */
4096 #define ALT_RSTMGR_COLDMODRST_TAPCOLD_SET_MSK 0x00000020
4097 /* The mask used to clear the ALT_RSTMGR_COLDMODRST_TAPCOLD register field value. */
4098 #define ALT_RSTMGR_COLDMODRST_TAPCOLD_CLR_MSK 0xffffffdf
4099 /* The reset value of the ALT_RSTMGR_COLDMODRST_TAPCOLD register field. */
4100 #define ALT_RSTMGR_COLDMODRST_TAPCOLD_RESET 0x0
4101 /* Extracts the ALT_RSTMGR_COLDMODRST_TAPCOLD field value from a register. */
4102 #define ALT_RSTMGR_COLDMODRST_TAPCOLD_GET(value) (((value) & 0x00000020) >> 5)
4103 /* Produces a ALT_RSTMGR_COLDMODRST_TAPCOLD register field value suitable for setting the register. */
4104 #define ALT_RSTMGR_COLDMODRST_TAPCOLD_SET(value) (((value) << 5) & 0x00000020)
4105 
4106 /*
4107  * Field : HMC Cold Reset - hmccold
4108  *
4109  * Resets logic in HMC affected only by a cold reset.
4110  *
4111  * Field Access Macros:
4112  *
4113  */
4114 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COLDMODRST_HMCCOLD register field. */
4115 #define ALT_RSTMGR_COLDMODRST_HMCCOLD_LSB 6
4116 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COLDMODRST_HMCCOLD register field. */
4117 #define ALT_RSTMGR_COLDMODRST_HMCCOLD_MSB 6
4118 /* The width in bits of the ALT_RSTMGR_COLDMODRST_HMCCOLD register field. */
4119 #define ALT_RSTMGR_COLDMODRST_HMCCOLD_WIDTH 1
4120 /* The mask used to set the ALT_RSTMGR_COLDMODRST_HMCCOLD register field value. */
4121 #define ALT_RSTMGR_COLDMODRST_HMCCOLD_SET_MSK 0x00000040
4122 /* The mask used to clear the ALT_RSTMGR_COLDMODRST_HMCCOLD register field value. */
4123 #define ALT_RSTMGR_COLDMODRST_HMCCOLD_CLR_MSK 0xffffffbf
4124 /* The reset value of the ALT_RSTMGR_COLDMODRST_HMCCOLD register field. */
4125 #define ALT_RSTMGR_COLDMODRST_HMCCOLD_RESET 0x0
4126 /* Extracts the ALT_RSTMGR_COLDMODRST_HMCCOLD field value from a register. */
4127 #define ALT_RSTMGR_COLDMODRST_HMCCOLD_GET(value) (((value) & 0x00000040) >> 6)
4128 /* Produces a ALT_RSTMGR_COLDMODRST_HMCCOLD register field value suitable for setting the register. */
4129 #define ALT_RSTMGR_COLDMODRST_HMCCOLD_SET(value) (((value) << 6) & 0x00000040)
4130 
4131 /*
4132  * Field : IO Manager (Cold-only) - iomgrcold
4133  *
4134  * Resets logic in IO Manager that is only reset by a cold reset (ignores warm
4135  * reset)
4136  *
4137  * Field Access Macros:
4138  *
4139  */
4140 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COLDMODRST_IOMGRCOLD register field. */
4141 #define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_LSB 7
4142 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COLDMODRST_IOMGRCOLD register field. */
4143 #define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_MSB 7
4144 /* The width in bits of the ALT_RSTMGR_COLDMODRST_IOMGRCOLD register field. */
4145 #define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_WIDTH 1
4146 /* The mask used to set the ALT_RSTMGR_COLDMODRST_IOMGRCOLD register field value. */
4147 #define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_SET_MSK 0x00000080
4148 /* The mask used to clear the ALT_RSTMGR_COLDMODRST_IOMGRCOLD register field value. */
4149 #define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_CLR_MSK 0xffffff7f
4150 /* The reset value of the ALT_RSTMGR_COLDMODRST_IOMGRCOLD register field. */
4151 #define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_RESET 0x0
4152 /* Extracts the ALT_RSTMGR_COLDMODRST_IOMGRCOLD field value from a register. */
4153 #define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_GET(value) (((value) & 0x00000080) >> 7)
4154 /* Produces a ALT_RSTMGR_COLDMODRST_IOMGRCOLD register field value suitable for setting the register. */
4155 #define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_SET(value) (((value) << 7) & 0x00000080)
4156 
4157 #ifndef __ASSEMBLY__
4158 /*
4159  * WARNING: The C register and register group struct declarations are provided for
4160  * convenience and illustrative purposes. They should, however, be used with
4161  * caution as the C language standard provides no guarantees about the alignment or
4162  * atomicity of device memory accesses. The recommended practice for writing
4163  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4164  * alt_write_word() functions.
4165  *
4166  * The struct declaration for register ALT_RSTMGR_COLDMODRST.
4167  */
4168 struct ALT_RSTMGR_COLDMODRST_s
4169 {
4170  uint32_t clkmgrcold : 1; /* Clock Manager */
4171  uint32_t : 2; /* *UNDEFINED* */
4172  uint32_t s2fcold : 1; /* HPS to FPGA Core (Cold-only) */
4173  uint32_t timestampcold : 1; /* Timestamp */
4174  uint32_t tapcold : 1; /* TAP Controller */
4175  uint32_t hmccold : 1; /* HMC Cold Reset */
4176  uint32_t iomgrcold : 1; /* IO Manager (Cold-only) */
4177  uint32_t : 24; /* *UNDEFINED* */
4178 };
4179 
4180 /* The typedef declaration for register ALT_RSTMGR_COLDMODRST. */
4181 typedef volatile struct ALT_RSTMGR_COLDMODRST_s ALT_RSTMGR_COLDMODRST_t;
4182 #endif /* __ASSEMBLY__ */
4183 
4184 /* The reset value of the ALT_RSTMGR_COLDMODRST register. */
4185 #define ALT_RSTMGR_COLDMODRST_RESET 0x00000000
4186 /* The byte offset of the ALT_RSTMGR_COLDMODRST register from the beginning of the component. */
4187 #define ALT_RSTMGR_COLDMODRST_OFST 0x34
4188 
4189 /*
4190  * Register : NRST Module Reset Register - nrstmodrst
4191  *
4192  * The NRSTMODRST register is used by software to trigger module resets (individual
4193  * module reset signals). Software explicitly asserts and de-asserts module reset
4194  * signals by writing bits in the appropriate *MODRST register. It is up to
4195  * software to ensure module reset signals are asserted for the appropriate length
4196  * of time and are de-asserted in the correct order. It is also up to software to
4197  * not assert a module reset signal that would prevent software from de-asserting
4198  * the module reset signal. For example, software should not assert the module
4199  * reset to the CPU executing the software.
4200  *
4201  * Software writes a bit to 1 to assert the module reset signal and to 0 to de-
4202  * assert the module reset signal.
4203  *
4204  * All fields are only reset by a cold reset
4205  *
4206  * Register Layout
4207  *
4208  * Bits | Access | Reset | Description
4209  * :-------|:-------|:------|:------------
4210  * [0] | RW | 0x0 | nRST Pin OE
4211  * [31:1] | ??? | 0x0 | *UNDEFINED*
4212  *
4213  */
4214 /*
4215  * Field : nRST Pin OE - nrstpinoe
4216  *
4217  * Drives NRST output enable with data tied low to extend cold and warm reset
4218  *
4219  * Field Access Macros:
4220  *
4221  */
4222 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_NRSTMODRST_NRSTPINOE register field. */
4223 #define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_LSB 0
4224 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_NRSTMODRST_NRSTPINOE register field. */
4225 #define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_MSB 0
4226 /* The width in bits of the ALT_RSTMGR_NRSTMODRST_NRSTPINOE register field. */
4227 #define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_WIDTH 1
4228 /* The mask used to set the ALT_RSTMGR_NRSTMODRST_NRSTPINOE register field value. */
4229 #define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_SET_MSK 0x00000001
4230 /* The mask used to clear the ALT_RSTMGR_NRSTMODRST_NRSTPINOE register field value. */
4231 #define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_CLR_MSK 0xfffffffe
4232 /* The reset value of the ALT_RSTMGR_NRSTMODRST_NRSTPINOE register field. */
4233 #define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_RESET 0x0
4234 /* Extracts the ALT_RSTMGR_NRSTMODRST_NRSTPINOE field value from a register. */
4235 #define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_GET(value) (((value) & 0x00000001) >> 0)
4236 /* Produces a ALT_RSTMGR_NRSTMODRST_NRSTPINOE register field value suitable for setting the register. */
4237 #define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_SET(value) (((value) << 0) & 0x00000001)
4238 
4239 #ifndef __ASSEMBLY__
4240 /*
4241  * WARNING: The C register and register group struct declarations are provided for
4242  * convenience and illustrative purposes. They should, however, be used with
4243  * caution as the C language standard provides no guarantees about the alignment or
4244  * atomicity of device memory accesses. The recommended practice for writing
4245  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4246  * alt_write_word() functions.
4247  *
4248  * The struct declaration for register ALT_RSTMGR_NRSTMODRST.
4249  */
4250 struct ALT_RSTMGR_NRSTMODRST_s
4251 {
4252  uint32_t nrstpinoe : 1; /* nRST Pin OE */
4253  uint32_t : 31; /* *UNDEFINED* */
4254 };
4255 
4256 /* The typedef declaration for register ALT_RSTMGR_NRSTMODRST. */
4257 typedef volatile struct ALT_RSTMGR_NRSTMODRST_s ALT_RSTMGR_NRSTMODRST_t;
4258 #endif /* __ASSEMBLY__ */
4259 
4260 /* The reset value of the ALT_RSTMGR_NRSTMODRST register. */
4261 #define ALT_RSTMGR_NRSTMODRST_RESET 0x00000000
4262 /* The byte offset of the ALT_RSTMGR_NRSTMODRST register from the beginning of the component. */
4263 #define ALT_RSTMGR_NRSTMODRST_OFST 0x38
4264 
4265 /*
4266  * Register : Debug Module Reset Register - dbgmodrst
4267  *
4268  * The DBGMODRST register is used by software to trigger module resets (individual
4269  * module reset signals). Software explicitly asserts and de-asserts module reset
4270  * signals by writing bits in the appropriate *MODRST register. It is up to
4271  * software to ensure module reset signals are asserted for the appropriate length
4272  * of time and are de-asserted in the correct order. It is also up to software to
4273  * not assert a module reset signal that would prevent software from de-asserting
4274  * the module reset signal. For example, software should not assert the module
4275  * reset to the CPU executing the software.
4276  *
4277  * Software writes a bit to 1 to assert the module reset signal and to 0 to de-
4278  * assert the module reset signal.
4279  *
4280  * All fields are only reset by a cold reset
4281  *
4282  * Register Layout
4283  *
4284  * Bits | Access | Reset | Description
4285  * :-------|:-------|:------|:------------
4286  * [0] | RW | 0x0 | Debug
4287  * [31:1] | ??? | 0x0 | *UNDEFINED*
4288  *
4289  */
4290 /*
4291  * Field : Debug - dbg
4292  *
4293  * Resets logic located only in the debug domain.
4294  *
4295  * Field Access Macros:
4296  *
4297  */
4298 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_DBGMODRST_DBG register field. */
4299 #define ALT_RSTMGR_DBGMODRST_DBG_LSB 0
4300 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_DBGMODRST_DBG register field. */
4301 #define ALT_RSTMGR_DBGMODRST_DBG_MSB 0
4302 /* The width in bits of the ALT_RSTMGR_DBGMODRST_DBG register field. */
4303 #define ALT_RSTMGR_DBGMODRST_DBG_WIDTH 1
4304 /* The mask used to set the ALT_RSTMGR_DBGMODRST_DBG register field value. */
4305 #define ALT_RSTMGR_DBGMODRST_DBG_SET_MSK 0x00000001
4306 /* The mask used to clear the ALT_RSTMGR_DBGMODRST_DBG register field value. */
4307 #define ALT_RSTMGR_DBGMODRST_DBG_CLR_MSK 0xfffffffe
4308 /* The reset value of the ALT_RSTMGR_DBGMODRST_DBG register field. */
4309 #define ALT_RSTMGR_DBGMODRST_DBG_RESET 0x0
4310 /* Extracts the ALT_RSTMGR_DBGMODRST_DBG field value from a register. */
4311 #define ALT_RSTMGR_DBGMODRST_DBG_GET(value) (((value) & 0x00000001) >> 0)
4312 /* Produces a ALT_RSTMGR_DBGMODRST_DBG register field value suitable for setting the register. */
4313 #define ALT_RSTMGR_DBGMODRST_DBG_SET(value) (((value) << 0) & 0x00000001)
4314 
4315 #ifndef __ASSEMBLY__
4316 /*
4317  * WARNING: The C register and register group struct declarations are provided for
4318  * convenience and illustrative purposes. They should, however, be used with
4319  * caution as the C language standard provides no guarantees about the alignment or
4320  * atomicity of device memory accesses. The recommended practice for writing
4321  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4322  * alt_write_word() functions.
4323  *
4324  * The struct declaration for register ALT_RSTMGR_DBGMODRST.
4325  */
4326 struct ALT_RSTMGR_DBGMODRST_s
4327 {
4328  uint32_t dbg : 1; /* Debug */
4329  uint32_t : 31; /* *UNDEFINED* */
4330 };
4331 
4332 /* The typedef declaration for register ALT_RSTMGR_DBGMODRST. */
4333 typedef volatile struct ALT_RSTMGR_DBGMODRST_s ALT_RSTMGR_DBGMODRST_t;
4334 #endif /* __ASSEMBLY__ */
4335 
4336 /* The reset value of the ALT_RSTMGR_DBGMODRST register. */
4337 #define ALT_RSTMGR_DBGMODRST_RESET 0x00000000
4338 /* The byte offset of the ALT_RSTMGR_DBGMODRST register from the beginning of the component. */
4339 #define ALT_RSTMGR_DBGMODRST_OFST 0x3c
4340 
4341 /*
4342  * Register : MPU Warm Mask Register - mpuwarmmask
4343  *
4344  * The MPUWARMMASK register is used by software to mask the assertion of module
4345  * reset signals for hardware sequenced warm resets. There is a writeable bit for
4346  * each module reset signal that is asserted by default on a hardware sequenced
4347  * warm reset. If the bit is 1, the module reset signal is asserted by a hardware
4348  * sequenced warm reset. If the bit is 0, the module reset signal is not changed by
4349  * a hardware sequenced warm reset. The bit assignments of the *WARMMASK registers
4350  * match the corresponding *MODRST registers. Any module reset signals that are
4351  * never asserted by a warm reset have reserved bit offsets and are tied to 0 (read
4352  * as 0, writes are ignored).
4353  *
4354  * All fields are only reset by a cold reset.
4355  *
4356  * Register Layout
4357  *
4358  * Bits | Access | Reset | Description
4359  * :-------|:-------|:------|:------------
4360  * [0] | RW | 0x1 | Watchdogs
4361  * [31:1] | ??? | 0xf | *UNDEFINED*
4362  *
4363  */
4364 /*
4365  * Field : Watchdogs - wds
4366  *
4367  * Masks hardware sequenced warm reset for both per-CPU Watchdog Reset Status
4368  * registers in MPU
4369  *
4370  * Field Access Macros:
4371  *
4372  */
4373 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUWARMMSK_WDS register field. */
4374 #define ALT_RSTMGR_MPUWARMMSK_WDS_LSB 0
4375 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUWARMMSK_WDS register field. */
4376 #define ALT_RSTMGR_MPUWARMMSK_WDS_MSB 0
4377 /* The width in bits of the ALT_RSTMGR_MPUWARMMSK_WDS register field. */
4378 #define ALT_RSTMGR_MPUWARMMSK_WDS_WIDTH 1
4379 /* The mask used to set the ALT_RSTMGR_MPUWARMMSK_WDS register field value. */
4380 #define ALT_RSTMGR_MPUWARMMSK_WDS_SET_MSK 0x00000001
4381 /* The mask used to clear the ALT_RSTMGR_MPUWARMMSK_WDS register field value. */
4382 #define ALT_RSTMGR_MPUWARMMSK_WDS_CLR_MSK 0xfffffffe
4383 /* The reset value of the ALT_RSTMGR_MPUWARMMSK_WDS register field. */
4384 #define ALT_RSTMGR_MPUWARMMSK_WDS_RESET 0x1
4385 /* Extracts the ALT_RSTMGR_MPUWARMMSK_WDS field value from a register. */
4386 #define ALT_RSTMGR_MPUWARMMSK_WDS_GET(value) (((value) & 0x00000001) >> 0)
4387 /* Produces a ALT_RSTMGR_MPUWARMMSK_WDS register field value suitable for setting the register. */
4388 #define ALT_RSTMGR_MPUWARMMSK_WDS_SET(value) (((value) << 0) & 0x00000001)
4389 
4390 #ifndef __ASSEMBLY__
4391 /*
4392  * WARNING: The C register and register group struct declarations are provided for
4393  * convenience and illustrative purposes. They should, however, be used with
4394  * caution as the C language standard provides no guarantees about the alignment or
4395  * atomicity of device memory accesses. The recommended practice for writing
4396  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4397  * alt_write_word() functions.
4398  *
4399  * The struct declaration for register ALT_RSTMGR_MPUWARMMSK.
4400  */
4401 struct ALT_RSTMGR_MPUWARMMSK_s
4402 {
4403  uint32_t wds : 1; /* Watchdogs */
4404  uint32_t : 31; /* *UNDEFINED* */
4405 };
4406 
4407 /* The typedef declaration for register ALT_RSTMGR_MPUWARMMSK. */
4408 typedef volatile struct ALT_RSTMGR_MPUWARMMSK_s ALT_RSTMGR_MPUWARMMSK_t;
4409 #endif /* __ASSEMBLY__ */
4410 
4411 /* The reset value of the ALT_RSTMGR_MPUWARMMSK register. */
4412 #define ALT_RSTMGR_MPUWARMMSK_RESET 0x0000001f
4413 /* The byte offset of the ALT_RSTMGR_MPUWARMMSK register from the beginning of the component. */
4414 #define ALT_RSTMGR_MPUWARMMSK_OFST 0x40
4415 
4416 /*
4417  * Register : Peripheral 0 Warm Mask Register - per0warmmask
4418  *
4419  * The PER0WARMMASK register is used by software to mask the assertion of
4420  * Peripheral and Fast Peripheral reset signals for hardware sequenced warm resets.
4421  * There is a writeable bit for each module reset signal that is asserted by
4422  * default on a hardware sequenced warm reset. If the bit is 1, the module reset
4423  * signal is asserted by a hardware sequenced warm reset. If the bit is 0, the
4424  * module reset signal is not changed by a hardware sequenced warm reset. The bit
4425  * assignments of the *WARMMASK registers match the corresponding *MODRST
4426  * registers. Any module reset signals that are never asserted by a warm reset have
4427  * reserved bit offsets and are tied to 0 (read as 0, writes are ignored).
4428  *
4429  * All fields are only reset by a cold reset.
4430  *
4431  * Register Layout
4432  *
4433  * Bits | Access | Reset | Description
4434  * :-----|:-------|:------|:-----------------------
4435  * [0] | RW | 0x1 | EMAC0
4436  * [1] | RW | 0x1 | EMAC1
4437  * [2] | RW | 0x1 | EMAC2
4438  * [3] | RW | 0x1 | USB0
4439  * [4] | RW | 0x1 | USB1
4440  * [5] | RW | 0x1 | NAND Flash
4441  * [6] | RW | 0x1 | QSPI Flash
4442  * [7] | RW | 0x1 | SD/MMC
4443  * [8] | RW | 0x1 | EMAC0OCP
4444  * [9] | RW | 0x1 | EMAC1OCP
4445  * [10] | RW | 0x1 | EMAC2OCP
4446  * [11] | RW | 0x1 | USB0OCP
4447  * [12] | RW | 0x1 | USB1OCP
4448  * [13] | RW | 0x1 | NANDOCP
4449  * [14] | RW | 0x1 | QSPIOCP
4450  * [15] | RW | 0x1 | SDMMCOCP
4451  * [16] | RW | 0x1 | DMA Controller
4452  * [17] | RW | 0x1 | SPIM0
4453  * [18] | RW | 0x1 | SPIM1
4454  * [19] | RW | 0x1 | SPIS0
4455  * [20] | RW | 0x1 | SPIS1
4456  * [21] | RW | 0x1 | DMA Controller ECC OCP
4457  * [22] | RW | 0x1 | EMAC PTP
4458  * [23] | ??? | 0x0 | *UNDEFINED*
4459  * [24] | RW | 0x1 | FPGA DMA0
4460  * [25] | RW | 0x1 | FPGA DMA1
4461  * [26] | RW | 0x1 | FPGA DMA2
4462  * [27] | RW | 0x1 | FPGA DMA3
4463  * [28] | RW | 0x1 | FPGA DMA4
4464  * [29] | RW | 0x1 | FPGA DMA5
4465  * [30] | RW | 0x1 | FPGA DMA6
4466  * [31] | RW | 0x1 | FPGA DMA7
4467  *
4468  */
4469 /*
4470  * Field : EMAC0 - emac0
4471  *
4472  * Masks hardware sequenced warm reset for EMAC0
4473  *
4474  * Field Access Macros:
4475  *
4476  */
4477 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_EMAC0 register field. */
4478 #define ALT_RSTMGR_PER0WARMMSK_EMAC0_LSB 0
4479 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_EMAC0 register field. */
4480 #define ALT_RSTMGR_PER0WARMMSK_EMAC0_MSB 0
4481 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_EMAC0 register field. */
4482 #define ALT_RSTMGR_PER0WARMMSK_EMAC0_WIDTH 1
4483 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_EMAC0 register field value. */
4484 #define ALT_RSTMGR_PER0WARMMSK_EMAC0_SET_MSK 0x00000001
4485 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_EMAC0 register field value. */
4486 #define ALT_RSTMGR_PER0WARMMSK_EMAC0_CLR_MSK 0xfffffffe
4487 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_EMAC0 register field. */
4488 #define ALT_RSTMGR_PER0WARMMSK_EMAC0_RESET 0x1
4489 /* Extracts the ALT_RSTMGR_PER0WARMMSK_EMAC0 field value from a register. */
4490 #define ALT_RSTMGR_PER0WARMMSK_EMAC0_GET(value) (((value) & 0x00000001) >> 0)
4491 /* Produces a ALT_RSTMGR_PER0WARMMSK_EMAC0 register field value suitable for setting the register. */
4492 #define ALT_RSTMGR_PER0WARMMSK_EMAC0_SET(value) (((value) << 0) & 0x00000001)
4493 
4494 /*
4495  * Field : EMAC1 - emac1
4496  *
4497  * Masks hardware sequenced warm reset for EMAC1
4498  *
4499  * Field Access Macros:
4500  *
4501  */
4502 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_EMAC1 register field. */
4503 #define ALT_RSTMGR_PER0WARMMSK_EMAC1_LSB 1
4504 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_EMAC1 register field. */
4505 #define ALT_RSTMGR_PER0WARMMSK_EMAC1_MSB 1
4506 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_EMAC1 register field. */
4507 #define ALT_RSTMGR_PER0WARMMSK_EMAC1_WIDTH 1
4508 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_EMAC1 register field value. */
4509 #define ALT_RSTMGR_PER0WARMMSK_EMAC1_SET_MSK 0x00000002
4510 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_EMAC1 register field value. */
4511 #define ALT_RSTMGR_PER0WARMMSK_EMAC1_CLR_MSK 0xfffffffd
4512 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_EMAC1 register field. */
4513 #define ALT_RSTMGR_PER0WARMMSK_EMAC1_RESET 0x1
4514 /* Extracts the ALT_RSTMGR_PER0WARMMSK_EMAC1 field value from a register. */
4515 #define ALT_RSTMGR_PER0WARMMSK_EMAC1_GET(value) (((value) & 0x00000002) >> 1)
4516 /* Produces a ALT_RSTMGR_PER0WARMMSK_EMAC1 register field value suitable for setting the register. */
4517 #define ALT_RSTMGR_PER0WARMMSK_EMAC1_SET(value) (((value) << 1) & 0x00000002)
4518 
4519 /*
4520  * Field : EMAC2 - emac2
4521  *
4522  * Masks hardware sequenced warm reset for EMAC2
4523  *
4524  * Field Access Macros:
4525  *
4526  */
4527 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_EMAC2 register field. */
4528 #define ALT_RSTMGR_PER0WARMMSK_EMAC2_LSB 2
4529 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_EMAC2 register field. */
4530 #define ALT_RSTMGR_PER0WARMMSK_EMAC2_MSB 2
4531 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_EMAC2 register field. */
4532 #define ALT_RSTMGR_PER0WARMMSK_EMAC2_WIDTH 1
4533 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_EMAC2 register field value. */
4534 #define ALT_RSTMGR_PER0WARMMSK_EMAC2_SET_MSK 0x00000004
4535 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_EMAC2 register field value. */
4536 #define ALT_RSTMGR_PER0WARMMSK_EMAC2_CLR_MSK 0xfffffffb
4537 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_EMAC2 register field. */
4538 #define ALT_RSTMGR_PER0WARMMSK_EMAC2_RESET 0x1
4539 /* Extracts the ALT_RSTMGR_PER0WARMMSK_EMAC2 field value from a register. */
4540 #define ALT_RSTMGR_PER0WARMMSK_EMAC2_GET(value) (((value) & 0x00000004) >> 2)
4541 /* Produces a ALT_RSTMGR_PER0WARMMSK_EMAC2 register field value suitable for setting the register. */
4542 #define ALT_RSTMGR_PER0WARMMSK_EMAC2_SET(value) (((value) << 2) & 0x00000004)
4543 
4544 /*
4545  * Field : USB0 - usb0
4546  *
4547  * Masks hardware sequenced warm reset for USB0
4548  *
4549  * Field Access Macros:
4550  *
4551  */
4552 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_USB0 register field. */
4553 #define ALT_RSTMGR_PER0WARMMSK_USB0_LSB 3
4554 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_USB0 register field. */
4555 #define ALT_RSTMGR_PER0WARMMSK_USB0_MSB 3
4556 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_USB0 register field. */
4557 #define ALT_RSTMGR_PER0WARMMSK_USB0_WIDTH 1
4558 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_USB0 register field value. */
4559 #define ALT_RSTMGR_PER0WARMMSK_USB0_SET_MSK 0x00000008
4560 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_USB0 register field value. */
4561 #define ALT_RSTMGR_PER0WARMMSK_USB0_CLR_MSK 0xfffffff7
4562 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_USB0 register field. */
4563 #define ALT_RSTMGR_PER0WARMMSK_USB0_RESET 0x1
4564 /* Extracts the ALT_RSTMGR_PER0WARMMSK_USB0 field value from a register. */
4565 #define ALT_RSTMGR_PER0WARMMSK_USB0_GET(value) (((value) & 0x00000008) >> 3)
4566 /* Produces a ALT_RSTMGR_PER0WARMMSK_USB0 register field value suitable for setting the register. */
4567 #define ALT_RSTMGR_PER0WARMMSK_USB0_SET(value) (((value) << 3) & 0x00000008)
4568 
4569 /*
4570  * Field : USB1 - usb1
4571  *
4572  * Masks hardware sequenced warm reset for USB1USB1
4573  *
4574  * Field Access Macros:
4575  *
4576  */
4577 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_USB1 register field. */
4578 #define ALT_RSTMGR_PER0WARMMSK_USB1_LSB 4
4579 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_USB1 register field. */
4580 #define ALT_RSTMGR_PER0WARMMSK_USB1_MSB 4
4581 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_USB1 register field. */
4582 #define ALT_RSTMGR_PER0WARMMSK_USB1_WIDTH 1
4583 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_USB1 register field value. */
4584 #define ALT_RSTMGR_PER0WARMMSK_USB1_SET_MSK 0x00000010
4585 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_USB1 register field value. */
4586 #define ALT_RSTMGR_PER0WARMMSK_USB1_CLR_MSK 0xffffffef
4587 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_USB1 register field. */
4588 #define ALT_RSTMGR_PER0WARMMSK_USB1_RESET 0x1
4589 /* Extracts the ALT_RSTMGR_PER0WARMMSK_USB1 field value from a register. */
4590 #define ALT_RSTMGR_PER0WARMMSK_USB1_GET(value) (((value) & 0x00000010) >> 4)
4591 /* Produces a ALT_RSTMGR_PER0WARMMSK_USB1 register field value suitable for setting the register. */
4592 #define ALT_RSTMGR_PER0WARMMSK_USB1_SET(value) (((value) << 4) & 0x00000010)
4593 
4594 /*
4595  * Field : NAND Flash - nand
4596  *
4597  * Masks hardware sequenced warm reset for NAND flash controller
4598  *
4599  * Field Access Macros:
4600  *
4601  */
4602 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_NAND register field. */
4603 #define ALT_RSTMGR_PER0WARMMSK_NAND_LSB 5
4604 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_NAND register field. */
4605 #define ALT_RSTMGR_PER0WARMMSK_NAND_MSB 5
4606 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_NAND register field. */
4607 #define ALT_RSTMGR_PER0WARMMSK_NAND_WIDTH 1
4608 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_NAND register field value. */
4609 #define ALT_RSTMGR_PER0WARMMSK_NAND_SET_MSK 0x00000020
4610 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_NAND register field value. */
4611 #define ALT_RSTMGR_PER0WARMMSK_NAND_CLR_MSK 0xffffffdf
4612 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_NAND register field. */
4613 #define ALT_RSTMGR_PER0WARMMSK_NAND_RESET 0x1
4614 /* Extracts the ALT_RSTMGR_PER0WARMMSK_NAND field value from a register. */
4615 #define ALT_RSTMGR_PER0WARMMSK_NAND_GET(value) (((value) & 0x00000020) >> 5)
4616 /* Produces a ALT_RSTMGR_PER0WARMMSK_NAND register field value suitable for setting the register. */
4617 #define ALT_RSTMGR_PER0WARMMSK_NAND_SET(value) (((value) << 5) & 0x00000020)
4618 
4619 /*
4620  * Field : QSPI Flash - qspi
4621  *
4622  * Masks hardware sequenced warm reset for QSPI flash controller
4623  *
4624  * Field Access Macros:
4625  *
4626  */
4627 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_QSPI register field. */
4628 #define ALT_RSTMGR_PER0WARMMSK_QSPI_LSB 6
4629 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_QSPI register field. */
4630 #define ALT_RSTMGR_PER0WARMMSK_QSPI_MSB 6
4631 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_QSPI register field. */
4632 #define ALT_RSTMGR_PER0WARMMSK_QSPI_WIDTH 1
4633 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_QSPI register field value. */
4634 #define ALT_RSTMGR_PER0WARMMSK_QSPI_SET_MSK 0x00000040
4635 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_QSPI register field value. */
4636 #define ALT_RSTMGR_PER0WARMMSK_QSPI_CLR_MSK 0xffffffbf
4637 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_QSPI register field. */
4638 #define ALT_RSTMGR_PER0WARMMSK_QSPI_RESET 0x1
4639 /* Extracts the ALT_RSTMGR_PER0WARMMSK_QSPI field value from a register. */
4640 #define ALT_RSTMGR_PER0WARMMSK_QSPI_GET(value) (((value) & 0x00000040) >> 6)
4641 /* Produces a ALT_RSTMGR_PER0WARMMSK_QSPI register field value suitable for setting the register. */
4642 #define ALT_RSTMGR_PER0WARMMSK_QSPI_SET(value) (((value) << 6) & 0x00000040)
4643 
4644 /*
4645  * Field : SD/MMC - sdmmc
4646  *
4647  * Masks hardware sequenced warm reset for SD/MMC controller
4648  *
4649  * Field Access Macros:
4650  *
4651  */
4652 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_SDMMC register field. */
4653 #define ALT_RSTMGR_PER0WARMMSK_SDMMC_LSB 7
4654 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_SDMMC register field. */
4655 #define ALT_RSTMGR_PER0WARMMSK_SDMMC_MSB 7
4656 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_SDMMC register field. */
4657 #define ALT_RSTMGR_PER0WARMMSK_SDMMC_WIDTH 1
4658 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_SDMMC register field value. */
4659 #define ALT_RSTMGR_PER0WARMMSK_SDMMC_SET_MSK 0x00000080
4660 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_SDMMC register field value. */
4661 #define ALT_RSTMGR_PER0WARMMSK_SDMMC_CLR_MSK 0xffffff7f
4662 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_SDMMC register field. */
4663 #define ALT_RSTMGR_PER0WARMMSK_SDMMC_RESET 0x1
4664 /* Extracts the ALT_RSTMGR_PER0WARMMSK_SDMMC field value from a register. */
4665 #define ALT_RSTMGR_PER0WARMMSK_SDMMC_GET(value) (((value) & 0x00000080) >> 7)
4666 /* Produces a ALT_RSTMGR_PER0WARMMSK_SDMMC register field value suitable for setting the register. */
4667 #define ALT_RSTMGR_PER0WARMMSK_SDMMC_SET(value) (((value) << 7) & 0x00000080)
4668 
4669 /*
4670  * Field : EMAC0OCP - emac0ocp
4671  *
4672  * Masks hardware sequenced warm reset for EMAC0 ECC OCP DIagnostics modules.
4673  *
4674  * Field Access Macros:
4675  *
4676  */
4677 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_EMAC0OCP register field. */
4678 #define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_LSB 8
4679 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_EMAC0OCP register field. */
4680 #define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_MSB 8
4681 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_EMAC0OCP register field. */
4682 #define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_WIDTH 1
4683 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_EMAC0OCP register field value. */
4684 #define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_SET_MSK 0x00000100
4685 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_EMAC0OCP register field value. */
4686 #define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_CLR_MSK 0xfffffeff
4687 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_EMAC0OCP register field. */
4688 #define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_RESET 0x1
4689 /* Extracts the ALT_RSTMGR_PER0WARMMSK_EMAC0OCP field value from a register. */
4690 #define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_GET(value) (((value) & 0x00000100) >> 8)
4691 /* Produces a ALT_RSTMGR_PER0WARMMSK_EMAC0OCP register field value suitable for setting the register. */
4692 #define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_SET(value) (((value) << 8) & 0x00000100)
4693 
4694 /*
4695  * Field : EMAC1OCP - emac1ocp
4696  *
4697  * Masks hardware sequenced warm reset for EMAC1 ECC OCP DIagnostics modules.
4698  *
4699  * Field Access Macros:
4700  *
4701  */
4702 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_EMAC1OCP register field. */
4703 #define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_LSB 9
4704 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_EMAC1OCP register field. */
4705 #define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_MSB 9
4706 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_EMAC1OCP register field. */
4707 #define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_WIDTH 1
4708 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_EMAC1OCP register field value. */
4709 #define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_SET_MSK 0x00000200
4710 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_EMAC1OCP register field value. */
4711 #define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_CLR_MSK 0xfffffdff
4712 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_EMAC1OCP register field. */
4713 #define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_RESET 0x1
4714 /* Extracts the ALT_RSTMGR_PER0WARMMSK_EMAC1OCP field value from a register. */
4715 #define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_GET(value) (((value) & 0x00000200) >> 9)
4716 /* Produces a ALT_RSTMGR_PER0WARMMSK_EMAC1OCP register field value suitable for setting the register. */
4717 #define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_SET(value) (((value) << 9) & 0x00000200)
4718 
4719 /*
4720  * Field : EMAC2OCP - emac2ocp
4721  *
4722  * Masks hardware sequenced warm reset for EMAC2 ECC OCP DIagnostics modules.
4723  *
4724  * Field Access Macros:
4725  *
4726  */
4727 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_EMAC2OCP register field. */
4728 #define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_LSB 10
4729 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_EMAC2OCP register field. */
4730 #define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_MSB 10
4731 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_EMAC2OCP register field. */
4732 #define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_WIDTH 1
4733 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_EMAC2OCP register field value. */
4734 #define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_SET_MSK 0x00000400
4735 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_EMAC2OCP register field value. */
4736 #define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_CLR_MSK 0xfffffbff
4737 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_EMAC2OCP register field. */
4738 #define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_RESET 0x1
4739 /* Extracts the ALT_RSTMGR_PER0WARMMSK_EMAC2OCP field value from a register. */
4740 #define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_GET(value) (((value) & 0x00000400) >> 10)
4741 /* Produces a ALT_RSTMGR_PER0WARMMSK_EMAC2OCP register field value suitable for setting the register. */
4742 #define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_SET(value) (((value) << 10) & 0x00000400)
4743 
4744 /*
4745  * Field : USB0OCP - usb0ocp
4746  *
4747  * Masks hardware sequenced warm reset for USB0 ECC OCP DIagnostics module.
4748  *
4749  * Field Access Macros:
4750  *
4751  */
4752 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_USB0OCP register field. */
4753 #define ALT_RSTMGR_PER0WARMMSK_USB0OCP_LSB 11
4754 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_USB0OCP register field. */
4755 #define ALT_RSTMGR_PER0WARMMSK_USB0OCP_MSB 11
4756 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_USB0OCP register field. */
4757 #define ALT_RSTMGR_PER0WARMMSK_USB0OCP_WIDTH 1
4758 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_USB0OCP register field value. */
4759 #define ALT_RSTMGR_PER0WARMMSK_USB0OCP_SET_MSK 0x00000800
4760 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_USB0OCP register field value. */
4761 #define ALT_RSTMGR_PER0WARMMSK_USB0OCP_CLR_MSK 0xfffff7ff
4762 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_USB0OCP register field. */
4763 #define ALT_RSTMGR_PER0WARMMSK_USB0OCP_RESET 0x1
4764 /* Extracts the ALT_RSTMGR_PER0WARMMSK_USB0OCP field value from a register. */
4765 #define ALT_RSTMGR_PER0WARMMSK_USB0OCP_GET(value) (((value) & 0x00000800) >> 11)
4766 /* Produces a ALT_RSTMGR_PER0WARMMSK_USB0OCP register field value suitable for setting the register. */
4767 #define ALT_RSTMGR_PER0WARMMSK_USB0OCP_SET(value) (((value) << 11) & 0x00000800)
4768 
4769 /*
4770  * Field : USB1OCP - usb1ocp
4771  *
4772  * Masks hardware sequenced warm reset for USB1 ECC OCP DIagnostics module.
4773  *
4774  * Field Access Macros:
4775  *
4776  */
4777 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_USB1OCP register field. */
4778 #define ALT_RSTMGR_PER0WARMMSK_USB1OCP_LSB 12
4779 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_USB1OCP register field. */
4780 #define ALT_RSTMGR_PER0WARMMSK_USB1OCP_MSB 12
4781 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_USB1OCP register field. */
4782 #define ALT_RSTMGR_PER0WARMMSK_USB1OCP_WIDTH 1
4783 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_USB1OCP register field value. */
4784 #define ALT_RSTMGR_PER0WARMMSK_USB1OCP_SET_MSK 0x00001000
4785 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_USB1OCP register field value. */
4786 #define ALT_RSTMGR_PER0WARMMSK_USB1OCP_CLR_MSK 0xffffefff
4787 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_USB1OCP register field. */
4788 #define ALT_RSTMGR_PER0WARMMSK_USB1OCP_RESET 0x1
4789 /* Extracts the ALT_RSTMGR_PER0WARMMSK_USB1OCP field value from a register. */
4790 #define ALT_RSTMGR_PER0WARMMSK_USB1OCP_GET(value) (((value) & 0x00001000) >> 12)
4791 /* Produces a ALT_RSTMGR_PER0WARMMSK_USB1OCP register field value suitable for setting the register. */
4792 #define ALT_RSTMGR_PER0WARMMSK_USB1OCP_SET(value) (((value) << 12) & 0x00001000)
4793 
4794 /*
4795  * Field : NANDOCP - nandocp
4796  *
4797  * Masks hardware sequenced warm reset for NAND ECC OCP DIagnostics modules.
4798  *
4799  * Field Access Macros:
4800  *
4801  */
4802 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_NANDOCP register field. */
4803 #define ALT_RSTMGR_PER0WARMMSK_NANDOCP_LSB 13
4804 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_NANDOCP register field. */
4805 #define ALT_RSTMGR_PER0WARMMSK_NANDOCP_MSB 13
4806 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_NANDOCP register field. */
4807 #define ALT_RSTMGR_PER0WARMMSK_NANDOCP_WIDTH 1
4808 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_NANDOCP register field value. */
4809 #define ALT_RSTMGR_PER0WARMMSK_NANDOCP_SET_MSK 0x00002000
4810 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_NANDOCP register field value. */
4811 #define ALT_RSTMGR_PER0WARMMSK_NANDOCP_CLR_MSK 0xffffdfff
4812 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_NANDOCP register field. */
4813 #define ALT_RSTMGR_PER0WARMMSK_NANDOCP_RESET 0x1
4814 /* Extracts the ALT_RSTMGR_PER0WARMMSK_NANDOCP field value from a register. */
4815 #define ALT_RSTMGR_PER0WARMMSK_NANDOCP_GET(value) (((value) & 0x00002000) >> 13)
4816 /* Produces a ALT_RSTMGR_PER0WARMMSK_NANDOCP register field value suitable for setting the register. */
4817 #define ALT_RSTMGR_PER0WARMMSK_NANDOCP_SET(value) (((value) << 13) & 0x00002000)
4818 
4819 /*
4820  * Field : QSPIOCP - qspiocp
4821  *
4822  * Masks hardware sequenced warm reset for QSPI ECC OCP DIagnostics module.
4823  *
4824  * Field Access Macros:
4825  *
4826  */
4827 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_QSPIOCP register field. */
4828 #define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_LSB 14
4829 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_QSPIOCP register field. */
4830 #define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_MSB 14
4831 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_QSPIOCP register field. */
4832 #define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_WIDTH 1
4833 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_QSPIOCP register field value. */
4834 #define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_SET_MSK 0x00004000
4835 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_QSPIOCP register field value. */
4836 #define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_CLR_MSK 0xffffbfff
4837 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_QSPIOCP register field. */
4838 #define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_RESET 0x1
4839 /* Extracts the ALT_RSTMGR_PER0WARMMSK_QSPIOCP field value from a register. */
4840 #define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_GET(value) (((value) & 0x00004000) >> 14)
4841 /* Produces a ALT_RSTMGR_PER0WARMMSK_QSPIOCP register field value suitable for setting the register. */
4842 #define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_SET(value) (((value) << 14) & 0x00004000)
4843 
4844 /*
4845  * Field : SDMMCOCP - sdmmcocp
4846  *
4847  * Masks hardware sequenced warm reset for SDMMC ECC OCP DIagnostics module.
4848  *
4849  * Field Access Macros:
4850  *
4851  */
4852 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_SDMMCOCP register field. */
4853 #define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_LSB 15
4854 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_SDMMCOCP register field. */
4855 #define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_MSB 15
4856 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_SDMMCOCP register field. */
4857 #define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_WIDTH 1
4858 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_SDMMCOCP register field value. */
4859 #define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_SET_MSK 0x00008000
4860 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_SDMMCOCP register field value. */
4861 #define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_CLR_MSK 0xffff7fff
4862 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_SDMMCOCP register field. */
4863 #define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_RESET 0x1
4864 /* Extracts the ALT_RSTMGR_PER0WARMMSK_SDMMCOCP field value from a register. */
4865 #define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_GET(value) (((value) & 0x00008000) >> 15)
4866 /* Produces a ALT_RSTMGR_PER0WARMMSK_SDMMCOCP register field value suitable for setting the register. */
4867 #define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_SET(value) (((value) << 15) & 0x00008000)
4868 
4869 /*
4870  * Field : DMA Controller - dma
4871  *
4872  * Masks hardware sequenced warm reset for DMA controller
4873  *
4874  * Field Access Macros:
4875  *
4876  */
4877 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_DMA register field. */
4878 #define ALT_RSTMGR_PER0WARMMSK_DMA_LSB 16
4879 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_DMA register field. */
4880 #define ALT_RSTMGR_PER0WARMMSK_DMA_MSB 16
4881 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_DMA register field. */
4882 #define ALT_RSTMGR_PER0WARMMSK_DMA_WIDTH 1
4883 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_DMA register field value. */
4884 #define ALT_RSTMGR_PER0WARMMSK_DMA_SET_MSK 0x00010000
4885 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_DMA register field value. */
4886 #define ALT_RSTMGR_PER0WARMMSK_DMA_CLR_MSK 0xfffeffff
4887 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_DMA register field. */
4888 #define ALT_RSTMGR_PER0WARMMSK_DMA_RESET 0x1
4889 /* Extracts the ALT_RSTMGR_PER0WARMMSK_DMA field value from a register. */
4890 #define ALT_RSTMGR_PER0WARMMSK_DMA_GET(value) (((value) & 0x00010000) >> 16)
4891 /* Produces a ALT_RSTMGR_PER0WARMMSK_DMA register field value suitable for setting the register. */
4892 #define ALT_RSTMGR_PER0WARMMSK_DMA_SET(value) (((value) << 16) & 0x00010000)
4893 
4894 /*
4895  * Field : SPIM0 - spim0
4896  *
4897  * Masks hardware sequenced warm reset for SPIM0 controller
4898  *
4899  * Field Access Macros:
4900  *
4901  */
4902 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_SPIM0 register field. */
4903 #define ALT_RSTMGR_PER0WARMMSK_SPIM0_LSB 17
4904 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_SPIM0 register field. */
4905 #define ALT_RSTMGR_PER0WARMMSK_SPIM0_MSB 17
4906 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_SPIM0 register field. */
4907 #define ALT_RSTMGR_PER0WARMMSK_SPIM0_WIDTH 1
4908 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_SPIM0 register field value. */
4909 #define ALT_RSTMGR_PER0WARMMSK_SPIM0_SET_MSK 0x00020000
4910 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_SPIM0 register field value. */
4911 #define ALT_RSTMGR_PER0WARMMSK_SPIM0_CLR_MSK 0xfffdffff
4912 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_SPIM0 register field. */
4913 #define ALT_RSTMGR_PER0WARMMSK_SPIM0_RESET 0x1
4914 /* Extracts the ALT_RSTMGR_PER0WARMMSK_SPIM0 field value from a register. */
4915 #define ALT_RSTMGR_PER0WARMMSK_SPIM0_GET(value) (((value) & 0x00020000) >> 17)
4916 /* Produces a ALT_RSTMGR_PER0WARMMSK_SPIM0 register field value suitable for setting the register. */
4917 #define ALT_RSTMGR_PER0WARMMSK_SPIM0_SET(value) (((value) << 17) & 0x00020000)
4918 
4919 /*
4920  * Field : SPIM1 - spim1
4921  *
4922  * Masks hardware sequenced warm reset for SPIM1 controller
4923  *
4924  * Field Access Macros:
4925  *
4926  */
4927 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_SPIM1 register field. */
4928 #define ALT_RSTMGR_PER0WARMMSK_SPIM1_LSB 18
4929 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_SPIM1 register field. */
4930 #define ALT_RSTMGR_PER0WARMMSK_SPIM1_MSB 18
4931 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_SPIM1 register field. */
4932 #define ALT_RSTMGR_PER0WARMMSK_SPIM1_WIDTH 1
4933 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_SPIM1 register field value. */
4934 #define ALT_RSTMGR_PER0WARMMSK_SPIM1_SET_MSK 0x00040000
4935 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_SPIM1 register field value. */
4936 #define ALT_RSTMGR_PER0WARMMSK_SPIM1_CLR_MSK 0xfffbffff
4937 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_SPIM1 register field. */
4938 #define ALT_RSTMGR_PER0WARMMSK_SPIM1_RESET 0x1
4939 /* Extracts the ALT_RSTMGR_PER0WARMMSK_SPIM1 field value from a register. */
4940 #define ALT_RSTMGR_PER0WARMMSK_SPIM1_GET(value) (((value) & 0x00040000) >> 18)
4941 /* Produces a ALT_RSTMGR_PER0WARMMSK_SPIM1 register field value suitable for setting the register. */
4942 #define ALT_RSTMGR_PER0WARMMSK_SPIM1_SET(value) (((value) << 18) & 0x00040000)
4943 
4944 /*
4945  * Field : SPIS0 - spis0
4946  *
4947  * Masks hardware sequenced warm reset for SPIS0 controller
4948  *
4949  * Field Access Macros:
4950  *
4951  */
4952 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_SPIS0 register field. */
4953 #define ALT_RSTMGR_PER0WARMMSK_SPIS0_LSB 19
4954 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_SPIS0 register field. */
4955 #define ALT_RSTMGR_PER0WARMMSK_SPIS0_MSB 19
4956 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_SPIS0 register field. */
4957 #define ALT_RSTMGR_PER0WARMMSK_SPIS0_WIDTH 1
4958 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_SPIS0 register field value. */
4959 #define ALT_RSTMGR_PER0WARMMSK_SPIS0_SET_MSK 0x00080000
4960 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_SPIS0 register field value. */
4961 #define ALT_RSTMGR_PER0WARMMSK_SPIS0_CLR_MSK 0xfff7ffff
4962 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_SPIS0 register field. */
4963 #define ALT_RSTMGR_PER0WARMMSK_SPIS0_RESET 0x1
4964 /* Extracts the ALT_RSTMGR_PER0WARMMSK_SPIS0 field value from a register. */
4965 #define ALT_RSTMGR_PER0WARMMSK_SPIS0_GET(value) (((value) & 0x00080000) >> 19)
4966 /* Produces a ALT_RSTMGR_PER0WARMMSK_SPIS0 register field value suitable for setting the register. */
4967 #define ALT_RSTMGR_PER0WARMMSK_SPIS0_SET(value) (((value) << 19) & 0x00080000)
4968 
4969 /*
4970  * Field : SPIS1 - spis1
4971  *
4972  * Masks hardware sequenced warm reset for SPIS1 controller
4973  *
4974  * Field Access Macros:
4975  *
4976  */
4977 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_SPIS1 register field. */
4978 #define ALT_RSTMGR_PER0WARMMSK_SPIS1_LSB 20
4979 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_SPIS1 register field. */
4980 #define ALT_RSTMGR_PER0WARMMSK_SPIS1_MSB 20
4981 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_SPIS1 register field. */
4982 #define ALT_RSTMGR_PER0WARMMSK_SPIS1_WIDTH 1
4983 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_SPIS1 register field value. */
4984 #define ALT_RSTMGR_PER0WARMMSK_SPIS1_SET_MSK 0x00100000
4985 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_SPIS1 register field value. */
4986 #define ALT_RSTMGR_PER0WARMMSK_SPIS1_CLR_MSK 0xffefffff
4987 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_SPIS1 register field. */
4988 #define ALT_RSTMGR_PER0WARMMSK_SPIS1_RESET 0x1
4989 /* Extracts the ALT_RSTMGR_PER0WARMMSK_SPIS1 field value from a register. */
4990 #define ALT_RSTMGR_PER0WARMMSK_SPIS1_GET(value) (((value) & 0x00100000) >> 20)
4991 /* Produces a ALT_RSTMGR_PER0WARMMSK_SPIS1 register field value suitable for setting the register. */
4992 #define ALT_RSTMGR_PER0WARMMSK_SPIS1_SET(value) (((value) << 20) & 0x00100000)
4993 
4994 /*
4995  * Field : DMA Controller ECC OCP - dmaocp
4996  *
4997  * Masks hardware sequenced warm reset for DMA Controller ECC OCP DIagnostics
4998  * module.
4999  *
5000  * Field Access Macros:
5001  *
5002  */
5003 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_DMAOCP register field. */
5004 #define ALT_RSTMGR_PER0WARMMSK_DMAOCP_LSB 21
5005 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_DMAOCP register field. */
5006 #define ALT_RSTMGR_PER0WARMMSK_DMAOCP_MSB 21
5007 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_DMAOCP register field. */
5008 #define ALT_RSTMGR_PER0WARMMSK_DMAOCP_WIDTH 1
5009 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_DMAOCP register field value. */
5010 #define ALT_RSTMGR_PER0WARMMSK_DMAOCP_SET_MSK 0x00200000
5011 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_DMAOCP register field value. */
5012 #define ALT_RSTMGR_PER0WARMMSK_DMAOCP_CLR_MSK 0xffdfffff
5013 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_DMAOCP register field. */
5014 #define ALT_RSTMGR_PER0WARMMSK_DMAOCP_RESET 0x1
5015 /* Extracts the ALT_RSTMGR_PER0WARMMSK_DMAOCP field value from a register. */
5016 #define ALT_RSTMGR_PER0WARMMSK_DMAOCP_GET(value) (((value) & 0x00200000) >> 21)
5017 /* Produces a ALT_RSTMGR_PER0WARMMSK_DMAOCP register field value suitable for setting the register. */
5018 #define ALT_RSTMGR_PER0WARMMSK_DMAOCP_SET(value) (((value) << 21) & 0x00200000)
5019 
5020 /*
5021  * Field : EMAC PTP - emacptp
5022  *
5023  * Masks hardware sequenced warm reset for EMAC PTP
5024  *
5025  * Field Access Macros:
5026  *
5027  */
5028 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_EMACPTP register field. */
5029 #define ALT_RSTMGR_PER0WARMMSK_EMACPTP_LSB 22
5030 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_EMACPTP register field. */
5031 #define ALT_RSTMGR_PER0WARMMSK_EMACPTP_MSB 22
5032 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_EMACPTP register field. */
5033 #define ALT_RSTMGR_PER0WARMMSK_EMACPTP_WIDTH 1
5034 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_EMACPTP register field value. */
5035 #define ALT_RSTMGR_PER0WARMMSK_EMACPTP_SET_MSK 0x00400000
5036 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_EMACPTP register field value. */
5037 #define ALT_RSTMGR_PER0WARMMSK_EMACPTP_CLR_MSK 0xffbfffff
5038 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_EMACPTP register field. */
5039 #define ALT_RSTMGR_PER0WARMMSK_EMACPTP_RESET 0x1
5040 /* Extracts the ALT_RSTMGR_PER0WARMMSK_EMACPTP field value from a register. */
5041 #define ALT_RSTMGR_PER0WARMMSK_EMACPTP_GET(value) (((value) & 0x00400000) >> 22)
5042 /* Produces a ALT_RSTMGR_PER0WARMMSK_EMACPTP register field value suitable for setting the register. */
5043 #define ALT_RSTMGR_PER0WARMMSK_EMACPTP_SET(value) (((value) << 22) & 0x00400000)
5044 
5045 /*
5046  * Field : FPGA DMA0 - dmaif0
5047  *
5048  * Masks hardware sequenced warm reset for DMA channel 0 interface adapter between
5049  * FPGA Fabric and HPS DMA Controller
5050  *
5051  * Field Access Macros:
5052  *
5053  */
5054 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_DMAIF0 register field. */
5055 #define ALT_RSTMGR_PER0WARMMSK_DMAIF0_LSB 24
5056 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_DMAIF0 register field. */
5057 #define ALT_RSTMGR_PER0WARMMSK_DMAIF0_MSB 24
5058 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_DMAIF0 register field. */
5059 #define ALT_RSTMGR_PER0WARMMSK_DMAIF0_WIDTH 1
5060 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_DMAIF0 register field value. */
5061 #define ALT_RSTMGR_PER0WARMMSK_DMAIF0_SET_MSK 0x01000000
5062 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_DMAIF0 register field value. */
5063 #define ALT_RSTMGR_PER0WARMMSK_DMAIF0_CLR_MSK 0xfeffffff
5064 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_DMAIF0 register field. */
5065 #define ALT_RSTMGR_PER0WARMMSK_DMAIF0_RESET 0x1
5066 /* Extracts the ALT_RSTMGR_PER0WARMMSK_DMAIF0 field value from a register. */
5067 #define ALT_RSTMGR_PER0WARMMSK_DMAIF0_GET(value) (((value) & 0x01000000) >> 24)
5068 /* Produces a ALT_RSTMGR_PER0WARMMSK_DMAIF0 register field value suitable for setting the register. */
5069 #define ALT_RSTMGR_PER0WARMMSK_DMAIF0_SET(value) (((value) << 24) & 0x01000000)
5070 
5071 /*
5072  * Field : FPGA DMA1 - dmaif1
5073  *
5074  * Masks hardware sequenced warm reset for DMA channel 1 interface adapter between
5075  * FPGA Fabric and HPS DMA Controller
5076  *
5077  * Field Access Macros:
5078  *
5079  */
5080 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_DMAIF1 register field. */
5081 #define ALT_RSTMGR_PER0WARMMSK_DMAIF1_LSB 25
5082 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_DMAIF1 register field. */
5083 #define ALT_RSTMGR_PER0WARMMSK_DMAIF1_MSB 25
5084 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_DMAIF1 register field. */
5085 #define ALT_RSTMGR_PER0WARMMSK_DMAIF1_WIDTH 1
5086 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_DMAIF1 register field value. */
5087 #define ALT_RSTMGR_PER0WARMMSK_DMAIF1_SET_MSK 0x02000000
5088 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_DMAIF1 register field value. */
5089 #define ALT_RSTMGR_PER0WARMMSK_DMAIF1_CLR_MSK 0xfdffffff
5090 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_DMAIF1 register field. */
5091 #define ALT_RSTMGR_PER0WARMMSK_DMAIF1_RESET 0x1
5092 /* Extracts the ALT_RSTMGR_PER0WARMMSK_DMAIF1 field value from a register. */
5093 #define ALT_RSTMGR_PER0WARMMSK_DMAIF1_GET(value) (((value) & 0x02000000) >> 25)
5094 /* Produces a ALT_RSTMGR_PER0WARMMSK_DMAIF1 register field value suitable for setting the register. */
5095 #define ALT_RSTMGR_PER0WARMMSK_DMAIF1_SET(value) (((value) << 25) & 0x02000000)
5096 
5097 /*
5098  * Field : FPGA DMA2 - dmaif2
5099  *
5100  * Masks hardware sequenced warm reset for DMA channel 2 interface adapter between
5101  * FPGA Fabric and HPS DMA Controller
5102  *
5103  * Field Access Macros:
5104  *
5105  */
5106 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_DMAIF2 register field. */
5107 #define ALT_RSTMGR_PER0WARMMSK_DMAIF2_LSB 26
5108 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_DMAIF2 register field. */
5109 #define ALT_RSTMGR_PER0WARMMSK_DMAIF2_MSB 26
5110 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_DMAIF2 register field. */
5111 #define ALT_RSTMGR_PER0WARMMSK_DMAIF2_WIDTH 1
5112 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_DMAIF2 register field value. */
5113 #define ALT_RSTMGR_PER0WARMMSK_DMAIF2_SET_MSK 0x04000000
5114 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_DMAIF2 register field value. */
5115 #define ALT_RSTMGR_PER0WARMMSK_DMAIF2_CLR_MSK 0xfbffffff
5116 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_DMAIF2 register field. */
5117 #define ALT_RSTMGR_PER0WARMMSK_DMAIF2_RESET 0x1
5118 /* Extracts the ALT_RSTMGR_PER0WARMMSK_DMAIF2 field value from a register. */
5119 #define ALT_RSTMGR_PER0WARMMSK_DMAIF2_GET(value) (((value) & 0x04000000) >> 26)
5120 /* Produces a ALT_RSTMGR_PER0WARMMSK_DMAIF2 register field value suitable for setting the register. */
5121 #define ALT_RSTMGR_PER0WARMMSK_DMAIF2_SET(value) (((value) << 26) & 0x04000000)
5122 
5123 /*
5124  * Field : FPGA DMA3 - dmaif3
5125  *
5126  * Masks hardware sequenced warm reset for DMA channel 3 interface adapter between
5127  * FPGA Fabric and HPS DMA Controller
5128  *
5129  * Field Access Macros:
5130  *
5131  */
5132 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_DMAIF3 register field. */
5133 #define ALT_RSTMGR_PER0WARMMSK_DMAIF3_LSB 27
5134 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_DMAIF3 register field. */
5135 #define ALT_RSTMGR_PER0WARMMSK_DMAIF3_MSB 27
5136 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_DMAIF3 register field. */
5137 #define ALT_RSTMGR_PER0WARMMSK_DMAIF3_WIDTH 1
5138 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_DMAIF3 register field value. */
5139 #define ALT_RSTMGR_PER0WARMMSK_DMAIF3_SET_MSK 0x08000000
5140 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_DMAIF3 register field value. */
5141 #define ALT_RSTMGR_PER0WARMMSK_DMAIF3_CLR_MSK 0xf7ffffff
5142 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_DMAIF3 register field. */
5143 #define ALT_RSTMGR_PER0WARMMSK_DMAIF3_RESET 0x1
5144 /* Extracts the ALT_RSTMGR_PER0WARMMSK_DMAIF3 field value from a register. */
5145 #define ALT_RSTMGR_PER0WARMMSK_DMAIF3_GET(value) (((value) & 0x08000000) >> 27)
5146 /* Produces a ALT_RSTMGR_PER0WARMMSK_DMAIF3 register field value suitable for setting the register. */
5147 #define ALT_RSTMGR_PER0WARMMSK_DMAIF3_SET(value) (((value) << 27) & 0x08000000)
5148 
5149 /*
5150  * Field : FPGA DMA4 - dmaif4
5151  *
5152  * Masks hardware sequenced warm reset for DMA channel 4 interface adapter between
5153  * FPGA Fabric and HPS DMA Controller
5154  *
5155  * Field Access Macros:
5156  *
5157  */
5158 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_DMAIF4 register field. */
5159 #define ALT_RSTMGR_PER0WARMMSK_DMAIF4_LSB 28
5160 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_DMAIF4 register field. */
5161 #define ALT_RSTMGR_PER0WARMMSK_DMAIF4_MSB 28
5162 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_DMAIF4 register field. */
5163 #define ALT_RSTMGR_PER0WARMMSK_DMAIF4_WIDTH 1
5164 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_DMAIF4 register field value. */
5165 #define ALT_RSTMGR_PER0WARMMSK_DMAIF4_SET_MSK 0x10000000
5166 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_DMAIF4 register field value. */
5167 #define ALT_RSTMGR_PER0WARMMSK_DMAIF4_CLR_MSK 0xefffffff
5168 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_DMAIF4 register field. */
5169 #define ALT_RSTMGR_PER0WARMMSK_DMAIF4_RESET 0x1
5170 /* Extracts the ALT_RSTMGR_PER0WARMMSK_DMAIF4 field value from a register. */
5171 #define ALT_RSTMGR_PER0WARMMSK_DMAIF4_GET(value) (((value) & 0x10000000) >> 28)
5172 /* Produces a ALT_RSTMGR_PER0WARMMSK_DMAIF4 register field value suitable for setting the register. */
5173 #define ALT_RSTMGR_PER0WARMMSK_DMAIF4_SET(value) (((value) << 28) & 0x10000000)
5174 
5175 /*
5176  * Field : FPGA DMA5 - dmaif5
5177  *
5178  * Masks hardware sequenced warm reset for DMA channel 5 interface adapter between
5179  * FPGA Fabric and HPS DMA Controller
5180  *
5181  * Field Access Macros:
5182  *
5183  */
5184 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_DMAIF5 register field. */
5185 #define ALT_RSTMGR_PER0WARMMSK_DMAIF5_LSB 29
5186 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_DMAIF5 register field. */
5187 #define ALT_RSTMGR_PER0WARMMSK_DMAIF5_MSB 29
5188 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_DMAIF5 register field. */
5189 #define ALT_RSTMGR_PER0WARMMSK_DMAIF5_WIDTH 1
5190 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_DMAIF5 register field value. */
5191 #define ALT_RSTMGR_PER0WARMMSK_DMAIF5_SET_MSK 0x20000000
5192 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_DMAIF5 register field value. */
5193 #define ALT_RSTMGR_PER0WARMMSK_DMAIF5_CLR_MSK 0xdfffffff
5194 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_DMAIF5 register field. */
5195 #define ALT_RSTMGR_PER0WARMMSK_DMAIF5_RESET 0x1
5196 /* Extracts the ALT_RSTMGR_PER0WARMMSK_DMAIF5 field value from a register. */
5197 #define ALT_RSTMGR_PER0WARMMSK_DMAIF5_GET(value) (((value) & 0x20000000) >> 29)
5198 /* Produces a ALT_RSTMGR_PER0WARMMSK_DMAIF5 register field value suitable for setting the register. */
5199 #define ALT_RSTMGR_PER0WARMMSK_DMAIF5_SET(value) (((value) << 29) & 0x20000000)
5200 
5201 /*
5202  * Field : FPGA DMA6 - dmaif6
5203  *
5204  * Masks hardware sequenced warm reset for DMA channel 6 interface adapter between
5205  * FPGA Fabric and HPS DMA Controller
5206  *
5207  * Field Access Macros:
5208  *
5209  */
5210 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_DMAIF6 register field. */
5211 #define ALT_RSTMGR_PER0WARMMSK_DMAIF6_LSB 30
5212 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_DMAIF6 register field. */
5213 #define ALT_RSTMGR_PER0WARMMSK_DMAIF6_MSB 30
5214 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_DMAIF6 register field. */
5215 #define ALT_RSTMGR_PER0WARMMSK_DMAIF6_WIDTH 1
5216 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_DMAIF6 register field value. */
5217 #define ALT_RSTMGR_PER0WARMMSK_DMAIF6_SET_MSK 0x40000000
5218 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_DMAIF6 register field value. */
5219 #define ALT_RSTMGR_PER0WARMMSK_DMAIF6_CLR_MSK 0xbfffffff
5220 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_DMAIF6 register field. */
5221 #define ALT_RSTMGR_PER0WARMMSK_DMAIF6_RESET 0x1
5222 /* Extracts the ALT_RSTMGR_PER0WARMMSK_DMAIF6 field value from a register. */
5223 #define ALT_RSTMGR_PER0WARMMSK_DMAIF6_GET(value) (((value) & 0x40000000) >> 30)
5224 /* Produces a ALT_RSTMGR_PER0WARMMSK_DMAIF6 register field value suitable for setting the register. */
5225 #define ALT_RSTMGR_PER0WARMMSK_DMAIF6_SET(value) (((value) << 30) & 0x40000000)
5226 
5227 /*
5228  * Field : FPGA DMA7 - dmaif7
5229  *
5230  * Masks hardware sequenced warm reset for DMA channel 7 interface adapter between
5231  * FPGA Fabric and HPS DMA Controller
5232  *
5233  * Field Access Macros:
5234  *
5235  */
5236 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0WARMMSK_DMAIF7 register field. */
5237 #define ALT_RSTMGR_PER0WARMMSK_DMAIF7_LSB 31
5238 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0WARMMSK_DMAIF7 register field. */
5239 #define ALT_RSTMGR_PER0WARMMSK_DMAIF7_MSB 31
5240 /* The width in bits of the ALT_RSTMGR_PER0WARMMSK_DMAIF7 register field. */
5241 #define ALT_RSTMGR_PER0WARMMSK_DMAIF7_WIDTH 1
5242 /* The mask used to set the ALT_RSTMGR_PER0WARMMSK_DMAIF7 register field value. */
5243 #define ALT_RSTMGR_PER0WARMMSK_DMAIF7_SET_MSK 0x80000000
5244 /* The mask used to clear the ALT_RSTMGR_PER0WARMMSK_DMAIF7 register field value. */
5245 #define ALT_RSTMGR_PER0WARMMSK_DMAIF7_CLR_MSK 0x7fffffff
5246 /* The reset value of the ALT_RSTMGR_PER0WARMMSK_DMAIF7 register field. */
5247 #define ALT_RSTMGR_PER0WARMMSK_DMAIF7_RESET 0x1
5248 /* Extracts the ALT_RSTMGR_PER0WARMMSK_DMAIF7 field value from a register. */
5249 #define ALT_RSTMGR_PER0WARMMSK_DMAIF7_GET(value) (((value) & 0x80000000) >> 31)
5250 /* Produces a ALT_RSTMGR_PER0WARMMSK_DMAIF7 register field value suitable for setting the register. */
5251 #define ALT_RSTMGR_PER0WARMMSK_DMAIF7_SET(value) (((value) << 31) & 0x80000000)
5252 
5253 #ifndef __ASSEMBLY__
5254 /*
5255  * WARNING: The C register and register group struct declarations are provided for
5256  * convenience and illustrative purposes. They should, however, be used with
5257  * caution as the C language standard provides no guarantees about the alignment or
5258  * atomicity of device memory accesses. The recommended practice for writing
5259  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5260  * alt_write_word() functions.
5261  *
5262  * The struct declaration for register ALT_RSTMGR_PER0WARMMSK.
5263  */
5264 struct ALT_RSTMGR_PER0WARMMSK_s
5265 {
5266  uint32_t emac0 : 1; /* EMAC0 */
5267  uint32_t emac1 : 1; /* EMAC1 */
5268  uint32_t emac2 : 1; /* EMAC2 */
5269  uint32_t usb0 : 1; /* USB0 */
5270  uint32_t usb1 : 1; /* USB1 */
5271  uint32_t nand : 1; /* NAND Flash */
5272  uint32_t qspi : 1; /* QSPI Flash */
5273  uint32_t sdmmc : 1; /* SD/MMC */
5274  uint32_t emac0ocp : 1; /* EMAC0OCP */
5275  uint32_t emac1ocp : 1; /* EMAC1OCP */
5276  uint32_t emac2ocp : 1; /* EMAC2OCP */
5277  uint32_t usb0ocp : 1; /* USB0OCP */
5278  uint32_t usb1ocp : 1; /* USB1OCP */
5279  uint32_t nandocp : 1; /* NANDOCP */
5280  uint32_t qspiocp : 1; /* QSPIOCP */
5281  uint32_t sdmmcocp : 1; /* SDMMCOCP */
5282  uint32_t dma : 1; /* DMA Controller */
5283  uint32_t spim0 : 1; /* SPIM0 */
5284  uint32_t spim1 : 1; /* SPIM1 */
5285  uint32_t spis0 : 1; /* SPIS0 */
5286  uint32_t spis1 : 1; /* SPIS1 */
5287  uint32_t dmaocp : 1; /* DMA Controller ECC OCP */
5288  uint32_t emacptp : 1; /* EMAC PTP */
5289  uint32_t : 1; /* *UNDEFINED* */
5290  uint32_t dmaif0 : 1; /* FPGA DMA0 */
5291  uint32_t dmaif1 : 1; /* FPGA DMA1 */
5292  uint32_t dmaif2 : 1; /* FPGA DMA2 */
5293  uint32_t dmaif3 : 1; /* FPGA DMA3 */
5294  uint32_t dmaif4 : 1; /* FPGA DMA4 */
5295  uint32_t dmaif5 : 1; /* FPGA DMA5 */
5296  uint32_t dmaif6 : 1; /* FPGA DMA6 */
5297  uint32_t dmaif7 : 1; /* FPGA DMA7 */
5298 };
5299 
5300 /* The typedef declaration for register ALT_RSTMGR_PER0WARMMSK. */
5301 typedef volatile struct ALT_RSTMGR_PER0WARMMSK_s ALT_RSTMGR_PER0WARMMSK_t;
5302 #endif /* __ASSEMBLY__ */
5303 
5304 /* The reset value of the ALT_RSTMGR_PER0WARMMSK register. */
5305 #define ALT_RSTMGR_PER0WARMMSK_RESET 0xff7fffff
5306 /* The byte offset of the ALT_RSTMGR_PER0WARMMSK register from the beginning of the component. */
5307 #define ALT_RSTMGR_PER0WARMMSK_OFST 0x44
5308 
5309 /*
5310  * Register : Peripheral 1 Warm Mask Register - per1warmmask
5311  *
5312  * The PER1WARMMASK register is used by software to mask the assertion of module
5313  * reset signals for hardware sequenced warm resets. There is a writeable bit for
5314  * each module reset signal that is asserted by default on a hardware sequenced
5315  * warm reset. If the bit is 1, the module reset signal is asserted by a hardware
5316  * sequenced warm reset. If the bit is 0, the module reset signal is not changed by
5317  * a hardware sequenced warm reset. The bit assignments of the *WARMMASK registers
5318  * match the corresponding *MODRST registers. Any module reset signals that are
5319  * never asserted by a warm reset have reserved bit offsets and are tied to 0 (read
5320  * as 0, writes are ignored).
5321  *
5322  * All fields are only reset by a cold reset.
5323  *
5324  * Register Layout
5325  *
5326  * Bits | Access | Reset | Description
5327  * :--------|:-------|:------|:------------
5328  * [0] | RW | 0x1 | Watch Dog0
5329  * [1] | RW | 0x1 | Watch Dog1
5330  * [2] | RW | 0x1 | l4systimer0
5331  * [3] | RW | 0x1 | l4systimer1
5332  * [4] | RW | 0x1 | SP Timer 0
5333  * [5] | RW | 0x1 | SP Timer 1
5334  * [7:6] | ??? | 0x0 | *UNDEFINED*
5335  * [8] | RW | 0x1 | I2C0
5336  * [9] | RW | 0x1 | I2C1
5337  * [10] | RW | 0x1 | I2C2
5338  * [11] | RW | 0x1 | I2C3
5339  * [12] | RW | 0x1 | I2C4
5340  * [15:13] | ??? | 0x0 | *UNDEFINED*
5341  * [16] | RW | 0x1 | UART0
5342  * [17] | RW | 0x1 | UART1
5343  * [23:18] | ??? | 0x0 | *UNDEFINED*
5344  * [24] | RW | 0x1 | GPIO0
5345  * [25] | RW | 0x1 | GPIO1
5346  * [26] | RW | 0x1 | GPIO2
5347  * [31:27] | ??? | 0x0 | *UNDEFINED*
5348  *
5349  */
5350 /*
5351  * Field : Watch Dog0 - watchdog0
5352  *
5353  * Masks hardware sequenced warm reset for Watchdog 0
5354  *
5355  * Field Access Macros:
5356  *
5357  */
5358 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1WARMMSK_WD0 register field. */
5359 #define ALT_RSTMGR_PER1WARMMSK_WD0_LSB 0
5360 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1WARMMSK_WD0 register field. */
5361 #define ALT_RSTMGR_PER1WARMMSK_WD0_MSB 0
5362 /* The width in bits of the ALT_RSTMGR_PER1WARMMSK_WD0 register field. */
5363 #define ALT_RSTMGR_PER1WARMMSK_WD0_WIDTH 1
5364 /* The mask used to set the ALT_RSTMGR_PER1WARMMSK_WD0 register field value. */
5365 #define ALT_RSTMGR_PER1WARMMSK_WD0_SET_MSK 0x00000001
5366 /* The mask used to clear the ALT_RSTMGR_PER1WARMMSK_WD0 register field value. */
5367 #define ALT_RSTMGR_PER1WARMMSK_WD0_CLR_MSK 0xfffffffe
5368 /* The reset value of the ALT_RSTMGR_PER1WARMMSK_WD0 register field. */
5369 #define ALT_RSTMGR_PER1WARMMSK_WD0_RESET 0x1
5370 /* Extracts the ALT_RSTMGR_PER1WARMMSK_WD0 field value from a register. */
5371 #define ALT_RSTMGR_PER1WARMMSK_WD0_GET(value) (((value) & 0x00000001) >> 0)
5372 /* Produces a ALT_RSTMGR_PER1WARMMSK_WD0 register field value suitable for setting the register. */
5373 #define ALT_RSTMGR_PER1WARMMSK_WD0_SET(value) (((value) << 0) & 0x00000001)
5374 
5375 /*
5376  * Field : Watch Dog1 - watchdog1
5377  *
5378  * Masks hardware sequenced warm reset for Watchdog 1
5379  *
5380  * Field Access Macros:
5381  *
5382  */
5383 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1WARMMSK_WD1 register field. */
5384 #define ALT_RSTMGR_PER1WARMMSK_WD1_LSB 1
5385 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1WARMMSK_WD1 register field. */
5386 #define ALT_RSTMGR_PER1WARMMSK_WD1_MSB 1
5387 /* The width in bits of the ALT_RSTMGR_PER1WARMMSK_WD1 register field. */
5388 #define ALT_RSTMGR_PER1WARMMSK_WD1_WIDTH 1
5389 /* The mask used to set the ALT_RSTMGR_PER1WARMMSK_WD1 register field value. */
5390 #define ALT_RSTMGR_PER1WARMMSK_WD1_SET_MSK 0x00000002
5391 /* The mask used to clear the ALT_RSTMGR_PER1WARMMSK_WD1 register field value. */
5392 #define ALT_RSTMGR_PER1WARMMSK_WD1_CLR_MSK 0xfffffffd
5393 /* The reset value of the ALT_RSTMGR_PER1WARMMSK_WD1 register field. */
5394 #define ALT_RSTMGR_PER1WARMMSK_WD1_RESET 0x1
5395 /* Extracts the ALT_RSTMGR_PER1WARMMSK_WD1 field value from a register. */
5396 #define ALT_RSTMGR_PER1WARMMSK_WD1_GET(value) (((value) & 0x00000002) >> 1)
5397 /* Produces a ALT_RSTMGR_PER1WARMMSK_WD1 register field value suitable for setting the register. */
5398 #define ALT_RSTMGR_PER1WARMMSK_WD1_SET(value) (((value) << 1) & 0x00000002)
5399 
5400 /*
5401  * Field : l4systimer0 - l4systimer0
5402  *
5403  * Masks hardware sequenced warm reset for l4sys_timer0
5404  *
5405  * Field Access Macros:
5406  *
5407  */
5408 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0 register field. */
5409 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_LSB 2
5410 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0 register field. */
5411 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_MSB 2
5412 /* The width in bits of the ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0 register field. */
5413 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_WIDTH 1
5414 /* The mask used to set the ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0 register field value. */
5415 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_SET_MSK 0x00000004
5416 /* The mask used to clear the ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0 register field value. */
5417 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_CLR_MSK 0xfffffffb
5418 /* The reset value of the ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0 register field. */
5419 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_RESET 0x1
5420 /* Extracts the ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0 field value from a register. */
5421 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_GET(value) (((value) & 0x00000004) >> 2)
5422 /* Produces a ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0 register field value suitable for setting the register. */
5423 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_SET(value) (((value) << 2) & 0x00000004)
5424 
5425 /*
5426  * Field : l4systimer1 - l4systimer1
5427  *
5428  * Masks hardware sequenced warm reset for l4sys_timer1
5429  *
5430  * Field Access Macros:
5431  *
5432  */
5433 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1 register field. */
5434 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_LSB 3
5435 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1 register field. */
5436 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_MSB 3
5437 /* The width in bits of the ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1 register field. */
5438 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_WIDTH 1
5439 /* The mask used to set the ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1 register field value. */
5440 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_SET_MSK 0x00000008
5441 /* The mask used to clear the ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1 register field value. */
5442 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_CLR_MSK 0xfffffff7
5443 /* The reset value of the ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1 register field. */
5444 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_RESET 0x1
5445 /* Extracts the ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1 field value from a register. */
5446 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_GET(value) (((value) & 0x00000008) >> 3)
5447 /* Produces a ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1 register field value suitable for setting the register. */
5448 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_SET(value) (((value) << 3) & 0x00000008)
5449 
5450 /*
5451  * Field : SP Timer 0 - sptimer0
5452  *
5453  * Masks hardware sequenced warm reset for SP timer 0 connected to L4
5454  *
5455  * Field Access Macros:
5456  *
5457  */
5458 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1WARMMSK_SPTMR0 register field. */
5459 #define ALT_RSTMGR_PER1WARMMSK_SPTMR0_LSB 4
5460 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1WARMMSK_SPTMR0 register field. */
5461 #define ALT_RSTMGR_PER1WARMMSK_SPTMR0_MSB 4
5462 /* The width in bits of the ALT_RSTMGR_PER1WARMMSK_SPTMR0 register field. */
5463 #define ALT_RSTMGR_PER1WARMMSK_SPTMR0_WIDTH 1
5464 /* The mask used to set the ALT_RSTMGR_PER1WARMMSK_SPTMR0 register field value. */
5465 #define ALT_RSTMGR_PER1WARMMSK_SPTMR0_SET_MSK 0x00000010
5466 /* The mask used to clear the ALT_RSTMGR_PER1WARMMSK_SPTMR0 register field value. */
5467 #define ALT_RSTMGR_PER1WARMMSK_SPTMR0_CLR_MSK 0xffffffef
5468 /* The reset value of the ALT_RSTMGR_PER1WARMMSK_SPTMR0 register field. */
5469 #define ALT_RSTMGR_PER1WARMMSK_SPTMR0_RESET 0x1
5470 /* Extracts the ALT_RSTMGR_PER1WARMMSK_SPTMR0 field value from a register. */
5471 #define ALT_RSTMGR_PER1WARMMSK_SPTMR0_GET(value) (((value) & 0x00000010) >> 4)
5472 /* Produces a ALT_RSTMGR_PER1WARMMSK_SPTMR0 register field value suitable for setting the register. */
5473 #define ALT_RSTMGR_PER1WARMMSK_SPTMR0_SET(value) (((value) << 4) & 0x00000010)
5474 
5475 /*
5476  * Field : SP Timer 1 - sptimer1
5477  *
5478  * Masks hardware sequenced warm reset for SP timer 1 connected to L4
5479  *
5480  * Field Access Macros:
5481  *
5482  */
5483 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1WARMMSK_SPTMR1 register field. */
5484 #define ALT_RSTMGR_PER1WARMMSK_SPTMR1_LSB 5
5485 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1WARMMSK_SPTMR1 register field. */
5486 #define ALT_RSTMGR_PER1WARMMSK_SPTMR1_MSB 5
5487 /* The width in bits of the ALT_RSTMGR_PER1WARMMSK_SPTMR1 register field. */
5488 #define ALT_RSTMGR_PER1WARMMSK_SPTMR1_WIDTH 1
5489 /* The mask used to set the ALT_RSTMGR_PER1WARMMSK_SPTMR1 register field value. */
5490 #define ALT_RSTMGR_PER1WARMMSK_SPTMR1_SET_MSK 0x00000020
5491 /* The mask used to clear the ALT_RSTMGR_PER1WARMMSK_SPTMR1 register field value. */
5492 #define ALT_RSTMGR_PER1WARMMSK_SPTMR1_CLR_MSK 0xffffffdf
5493 /* The reset value of the ALT_RSTMGR_PER1WARMMSK_SPTMR1 register field. */
5494 #define ALT_RSTMGR_PER1WARMMSK_SPTMR1_RESET 0x1
5495 /* Extracts the ALT_RSTMGR_PER1WARMMSK_SPTMR1 field value from a register. */
5496 #define ALT_RSTMGR_PER1WARMMSK_SPTMR1_GET(value) (((value) & 0x00000020) >> 5)
5497 /* Produces a ALT_RSTMGR_PER1WARMMSK_SPTMR1 register field value suitable for setting the register. */
5498 #define ALT_RSTMGR_PER1WARMMSK_SPTMR1_SET(value) (((value) << 5) & 0x00000020)
5499 
5500 /*
5501  * Field : I2C0 - i2c0
5502  *
5503  * Masks hardware sequenced warm reset for 2C0 controller
5504  *
5505  * Field Access Macros:
5506  *
5507  */
5508 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1WARMMSK_I2C0 register field. */
5509 #define ALT_RSTMGR_PER1WARMMSK_I2C0_LSB 8
5510 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1WARMMSK_I2C0 register field. */
5511 #define ALT_RSTMGR_PER1WARMMSK_I2C0_MSB 8
5512 /* The width in bits of the ALT_RSTMGR_PER1WARMMSK_I2C0 register field. */
5513 #define ALT_RSTMGR_PER1WARMMSK_I2C0_WIDTH 1
5514 /* The mask used to set the ALT_RSTMGR_PER1WARMMSK_I2C0 register field value. */
5515 #define ALT_RSTMGR_PER1WARMMSK_I2C0_SET_MSK 0x00000100
5516 /* The mask used to clear the ALT_RSTMGR_PER1WARMMSK_I2C0 register field value. */
5517 #define ALT_RSTMGR_PER1WARMMSK_I2C0_CLR_MSK 0xfffffeff
5518 /* The reset value of the ALT_RSTMGR_PER1WARMMSK_I2C0 register field. */
5519 #define ALT_RSTMGR_PER1WARMMSK_I2C0_RESET 0x1
5520 /* Extracts the ALT_RSTMGR_PER1WARMMSK_I2C0 field value from a register. */
5521 #define ALT_RSTMGR_PER1WARMMSK_I2C0_GET(value) (((value) & 0x00000100) >> 8)
5522 /* Produces a ALT_RSTMGR_PER1WARMMSK_I2C0 register field value suitable for setting the register. */
5523 #define ALT_RSTMGR_PER1WARMMSK_I2C0_SET(value) (((value) << 8) & 0x00000100)
5524 
5525 /*
5526  * Field : I2C1 - i2c1
5527  *
5528  * Masks hardware sequenced warm reset for 2C1 controller
5529  *
5530  * Field Access Macros:
5531  *
5532  */
5533 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1WARMMSK_I2C1 register field. */
5534 #define ALT_RSTMGR_PER1WARMMSK_I2C1_LSB 9
5535 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1WARMMSK_I2C1 register field. */
5536 #define ALT_RSTMGR_PER1WARMMSK_I2C1_MSB 9
5537 /* The width in bits of the ALT_RSTMGR_PER1WARMMSK_I2C1 register field. */
5538 #define ALT_RSTMGR_PER1WARMMSK_I2C1_WIDTH 1
5539 /* The mask used to set the ALT_RSTMGR_PER1WARMMSK_I2C1 register field value. */
5540 #define ALT_RSTMGR_PER1WARMMSK_I2C1_SET_MSK 0x00000200
5541 /* The mask used to clear the ALT_RSTMGR_PER1WARMMSK_I2C1 register field value. */
5542 #define ALT_RSTMGR_PER1WARMMSK_I2C1_CLR_MSK 0xfffffdff
5543 /* The reset value of the ALT_RSTMGR_PER1WARMMSK_I2C1 register field. */
5544 #define ALT_RSTMGR_PER1WARMMSK_I2C1_RESET 0x1
5545 /* Extracts the ALT_RSTMGR_PER1WARMMSK_I2C1 field value from a register. */
5546 #define ALT_RSTMGR_PER1WARMMSK_I2C1_GET(value) (((value) & 0x00000200) >> 9)
5547 /* Produces a ALT_RSTMGR_PER1WARMMSK_I2C1 register field value suitable for setting the register. */
5548 #define ALT_RSTMGR_PER1WARMMSK_I2C1_SET(value) (((value) << 9) & 0x00000200)
5549 
5550 /*
5551  * Field : I2C2 - i2c2
5552  *
5553  * Masks hardware sequenced warm reset for I2C2 controller
5554  *
5555  * Field Access Macros:
5556  *
5557  */
5558 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1WARMMSK_I2C2 register field. */
5559 #define ALT_RSTMGR_PER1WARMMSK_I2C2_LSB 10
5560 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1WARMMSK_I2C2 register field. */
5561 #define ALT_RSTMGR_PER1WARMMSK_I2C2_MSB 10
5562 /* The width in bits of the ALT_RSTMGR_PER1WARMMSK_I2C2 register field. */
5563 #define ALT_RSTMGR_PER1WARMMSK_I2C2_WIDTH 1
5564 /* The mask used to set the ALT_RSTMGR_PER1WARMMSK_I2C2 register field value. */
5565 #define ALT_RSTMGR_PER1WARMMSK_I2C2_SET_MSK 0x00000400
5566 /* The mask used to clear the ALT_RSTMGR_PER1WARMMSK_I2C2 register field value. */
5567 #define ALT_RSTMGR_PER1WARMMSK_I2C2_CLR_MSK 0xfffffbff
5568 /* The reset value of the ALT_RSTMGR_PER1WARMMSK_I2C2 register field. */
5569 #define ALT_RSTMGR_PER1WARMMSK_I2C2_RESET 0x1
5570 /* Extracts the ALT_RSTMGR_PER1WARMMSK_I2C2 field value from a register. */
5571 #define ALT_RSTMGR_PER1WARMMSK_I2C2_GET(value) (((value) & 0x00000400) >> 10)
5572 /* Produces a ALT_RSTMGR_PER1WARMMSK_I2C2 register field value suitable for setting the register. */
5573 #define ALT_RSTMGR_PER1WARMMSK_I2C2_SET(value) (((value) << 10) & 0x00000400)
5574 
5575 /*
5576  * Field : I2C3 - i2c3
5577  *
5578  * Masks hardware sequenced warm reset for I2C3 controller
5579  *
5580  * Field Access Macros:
5581  *
5582  */
5583 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1WARMMSK_I2C3 register field. */
5584 #define ALT_RSTMGR_PER1WARMMSK_I2C3_LSB 11
5585 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1WARMMSK_I2C3 register field. */
5586 #define ALT_RSTMGR_PER1WARMMSK_I2C3_MSB 11
5587 /* The width in bits of the ALT_RSTMGR_PER1WARMMSK_I2C3 register field. */
5588 #define ALT_RSTMGR_PER1WARMMSK_I2C3_WIDTH 1
5589 /* The mask used to set the ALT_RSTMGR_PER1WARMMSK_I2C3 register field value. */
5590 #define ALT_RSTMGR_PER1WARMMSK_I2C3_SET_MSK 0x00000800
5591 /* The mask used to clear the ALT_RSTMGR_PER1WARMMSK_I2C3 register field value. */
5592 #define ALT_RSTMGR_PER1WARMMSK_I2C3_CLR_MSK 0xfffff7ff
5593 /* The reset value of the ALT_RSTMGR_PER1WARMMSK_I2C3 register field. */
5594 #define ALT_RSTMGR_PER1WARMMSK_I2C3_RESET 0x1
5595 /* Extracts the ALT_RSTMGR_PER1WARMMSK_I2C3 field value from a register. */
5596 #define ALT_RSTMGR_PER1WARMMSK_I2C3_GET(value) (((value) & 0x00000800) >> 11)
5597 /* Produces a ALT_RSTMGR_PER1WARMMSK_I2C3 register field value suitable for setting the register. */
5598 #define ALT_RSTMGR_PER1WARMMSK_I2C3_SET(value) (((value) << 11) & 0x00000800)
5599 
5600 /*
5601  * Field : I2C4 - i2c4
5602  *
5603  * Masks hardware sequenced warm reset for I2C4 controller
5604  *
5605  * Field Access Macros:
5606  *
5607  */
5608 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1WARMMSK_I2C4 register field. */
5609 #define ALT_RSTMGR_PER1WARMMSK_I2C4_LSB 12
5610 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1WARMMSK_I2C4 register field. */
5611 #define ALT_RSTMGR_PER1WARMMSK_I2C4_MSB 12
5612 /* The width in bits of the ALT_RSTMGR_PER1WARMMSK_I2C4 register field. */
5613 #define ALT_RSTMGR_PER1WARMMSK_I2C4_WIDTH 1
5614 /* The mask used to set the ALT_RSTMGR_PER1WARMMSK_I2C4 register field value. */
5615 #define ALT_RSTMGR_PER1WARMMSK_I2C4_SET_MSK 0x00001000
5616 /* The mask used to clear the ALT_RSTMGR_PER1WARMMSK_I2C4 register field value. */
5617 #define ALT_RSTMGR_PER1WARMMSK_I2C4_CLR_MSK 0xffffefff
5618 /* The reset value of the ALT_RSTMGR_PER1WARMMSK_I2C4 register field. */
5619 #define ALT_RSTMGR_PER1WARMMSK_I2C4_RESET 0x1
5620 /* Extracts the ALT_RSTMGR_PER1WARMMSK_I2C4 field value from a register. */
5621 #define ALT_RSTMGR_PER1WARMMSK_I2C4_GET(value) (((value) & 0x00001000) >> 12)
5622 /* Produces a ALT_RSTMGR_PER1WARMMSK_I2C4 register field value suitable for setting the register. */
5623 #define ALT_RSTMGR_PER1WARMMSK_I2C4_SET(value) (((value) << 12) & 0x00001000)
5624 
5625 /*
5626  * Field : UART0 - uart0
5627  *
5628  * Masks hardware sequenced warm reset forUART0
5629  *
5630  * Field Access Macros:
5631  *
5632  */
5633 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1WARMMSK_UART0 register field. */
5634 #define ALT_RSTMGR_PER1WARMMSK_UART0_LSB 16
5635 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1WARMMSK_UART0 register field. */
5636 #define ALT_RSTMGR_PER1WARMMSK_UART0_MSB 16
5637 /* The width in bits of the ALT_RSTMGR_PER1WARMMSK_UART0 register field. */
5638 #define ALT_RSTMGR_PER1WARMMSK_UART0_WIDTH 1
5639 /* The mask used to set the ALT_RSTMGR_PER1WARMMSK_UART0 register field value. */
5640 #define ALT_RSTMGR_PER1WARMMSK_UART0_SET_MSK 0x00010000
5641 /* The mask used to clear the ALT_RSTMGR_PER1WARMMSK_UART0 register field value. */
5642 #define ALT_RSTMGR_PER1WARMMSK_UART0_CLR_MSK 0xfffeffff
5643 /* The reset value of the ALT_RSTMGR_PER1WARMMSK_UART0 register field. */
5644 #define ALT_RSTMGR_PER1WARMMSK_UART0_RESET 0x1
5645 /* Extracts the ALT_RSTMGR_PER1WARMMSK_UART0 field value from a register. */
5646 #define ALT_RSTMGR_PER1WARMMSK_UART0_GET(value) (((value) & 0x00010000) >> 16)
5647 /* Produces a ALT_RSTMGR_PER1WARMMSK_UART0 register field value suitable for setting the register. */
5648 #define ALT_RSTMGR_PER1WARMMSK_UART0_SET(value) (((value) << 16) & 0x00010000)
5649 
5650 /*
5651  * Field : UART1 - uart1
5652  *
5653  * Masks hardware sequenced warm reset for UART1
5654  *
5655  * Field Access Macros:
5656  *
5657  */
5658 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1WARMMSK_UART1 register field. */
5659 #define ALT_RSTMGR_PER1WARMMSK_UART1_LSB 17
5660 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1WARMMSK_UART1 register field. */
5661 #define ALT_RSTMGR_PER1WARMMSK_UART1_MSB 17
5662 /* The width in bits of the ALT_RSTMGR_PER1WARMMSK_UART1 register field. */
5663 #define ALT_RSTMGR_PER1WARMMSK_UART1_WIDTH 1
5664 /* The mask used to set the ALT_RSTMGR_PER1WARMMSK_UART1 register field value. */
5665 #define ALT_RSTMGR_PER1WARMMSK_UART1_SET_MSK 0x00020000
5666 /* The mask used to clear the ALT_RSTMGR_PER1WARMMSK_UART1 register field value. */
5667 #define ALT_RSTMGR_PER1WARMMSK_UART1_CLR_MSK 0xfffdffff
5668 /* The reset value of the ALT_RSTMGR_PER1WARMMSK_UART1 register field. */
5669 #define ALT_RSTMGR_PER1WARMMSK_UART1_RESET 0x1
5670 /* Extracts the ALT_RSTMGR_PER1WARMMSK_UART1 field value from a register. */
5671 #define ALT_RSTMGR_PER1WARMMSK_UART1_GET(value) (((value) & 0x00020000) >> 17)
5672 /* Produces a ALT_RSTMGR_PER1WARMMSK_UART1 register field value suitable for setting the register. */
5673 #define ALT_RSTMGR_PER1WARMMSK_UART1_SET(value) (((value) << 17) & 0x00020000)
5674 
5675 /*
5676  * Field : GPIO0 - gpio0
5677  *
5678  * Masks hardware sequenced warm reset for GPIO0
5679  *
5680  * Field Access Macros:
5681  *
5682  */
5683 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1WARMMSK_GPIO0 register field. */
5684 #define ALT_RSTMGR_PER1WARMMSK_GPIO0_LSB 24
5685 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1WARMMSK_GPIO0 register field. */
5686 #define ALT_RSTMGR_PER1WARMMSK_GPIO0_MSB 24
5687 /* The width in bits of the ALT_RSTMGR_PER1WARMMSK_GPIO0 register field. */
5688 #define ALT_RSTMGR_PER1WARMMSK_GPIO0_WIDTH 1
5689 /* The mask used to set the ALT_RSTMGR_PER1WARMMSK_GPIO0 register field value. */
5690 #define ALT_RSTMGR_PER1WARMMSK_GPIO0_SET_MSK 0x01000000
5691 /* The mask used to clear the ALT_RSTMGR_PER1WARMMSK_GPIO0 register field value. */
5692 #define ALT_RSTMGR_PER1WARMMSK_GPIO0_CLR_MSK 0xfeffffff
5693 /* The reset value of the ALT_RSTMGR_PER1WARMMSK_GPIO0 register field. */
5694 #define ALT_RSTMGR_PER1WARMMSK_GPIO0_RESET 0x1
5695 /* Extracts the ALT_RSTMGR_PER1WARMMSK_GPIO0 field value from a register. */
5696 #define ALT_RSTMGR_PER1WARMMSK_GPIO0_GET(value) (((value) & 0x01000000) >> 24)
5697 /* Produces a ALT_RSTMGR_PER1WARMMSK_GPIO0 register field value suitable for setting the register. */
5698 #define ALT_RSTMGR_PER1WARMMSK_GPIO0_SET(value) (((value) << 24) & 0x01000000)
5699 
5700 /*
5701  * Field : GPIO1 - gpio1
5702  *
5703  * Masks hardware sequenced warm reset for GPIO1
5704  *
5705  * Field Access Macros:
5706  *
5707  */
5708 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1WARMMSK_GPIO1 register field. */
5709 #define ALT_RSTMGR_PER1WARMMSK_GPIO1_LSB 25
5710 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1WARMMSK_GPIO1 register field. */
5711 #define ALT_RSTMGR_PER1WARMMSK_GPIO1_MSB 25
5712 /* The width in bits of the ALT_RSTMGR_PER1WARMMSK_GPIO1 register field. */
5713 #define ALT_RSTMGR_PER1WARMMSK_GPIO1_WIDTH 1
5714 /* The mask used to set the ALT_RSTMGR_PER1WARMMSK_GPIO1 register field value. */
5715 #define ALT_RSTMGR_PER1WARMMSK_GPIO1_SET_MSK 0x02000000
5716 /* The mask used to clear the ALT_RSTMGR_PER1WARMMSK_GPIO1 register field value. */
5717 #define ALT_RSTMGR_PER1WARMMSK_GPIO1_CLR_MSK 0xfdffffff
5718 /* The reset value of the ALT_RSTMGR_PER1WARMMSK_GPIO1 register field. */
5719 #define ALT_RSTMGR_PER1WARMMSK_GPIO1_RESET 0x1
5720 /* Extracts the ALT_RSTMGR_PER1WARMMSK_GPIO1 field value from a register. */
5721 #define ALT_RSTMGR_PER1WARMMSK_GPIO1_GET(value) (((value) & 0x02000000) >> 25)
5722 /* Produces a ALT_RSTMGR_PER1WARMMSK_GPIO1 register field value suitable for setting the register. */
5723 #define ALT_RSTMGR_PER1WARMMSK_GPIO1_SET(value) (((value) << 25) & 0x02000000)
5724 
5725 /*
5726  * Field : GPIO2 - gpio2
5727  *
5728  * Masks hardware sequenced warm reset for GPIO2
5729  *
5730  * Field Access Macros:
5731  *
5732  */
5733 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1WARMMSK_GPIO2 register field. */
5734 #define ALT_RSTMGR_PER1WARMMSK_GPIO2_LSB 26
5735 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1WARMMSK_GPIO2 register field. */
5736 #define ALT_RSTMGR_PER1WARMMSK_GPIO2_MSB 26
5737 /* The width in bits of the ALT_RSTMGR_PER1WARMMSK_GPIO2 register field. */
5738 #define ALT_RSTMGR_PER1WARMMSK_GPIO2_WIDTH 1
5739 /* The mask used to set the ALT_RSTMGR_PER1WARMMSK_GPIO2 register field value. */
5740 #define ALT_RSTMGR_PER1WARMMSK_GPIO2_SET_MSK 0x04000000
5741 /* The mask used to clear the ALT_RSTMGR_PER1WARMMSK_GPIO2 register field value. */
5742 #define ALT_RSTMGR_PER1WARMMSK_GPIO2_CLR_MSK 0xfbffffff
5743 /* The reset value of the ALT_RSTMGR_PER1WARMMSK_GPIO2 register field. */
5744 #define ALT_RSTMGR_PER1WARMMSK_GPIO2_RESET 0x1
5745 /* Extracts the ALT_RSTMGR_PER1WARMMSK_GPIO2 field value from a register. */
5746 #define ALT_RSTMGR_PER1WARMMSK_GPIO2_GET(value) (((value) & 0x04000000) >> 26)
5747 /* Produces a ALT_RSTMGR_PER1WARMMSK_GPIO2 register field value suitable for setting the register. */
5748 #define ALT_RSTMGR_PER1WARMMSK_GPIO2_SET(value) (((value) << 26) & 0x04000000)
5749 
5750 #ifndef __ASSEMBLY__
5751 /*
5752  * WARNING: The C register and register group struct declarations are provided for
5753  * convenience and illustrative purposes. They should, however, be used with
5754  * caution as the C language standard provides no guarantees about the alignment or
5755  * atomicity of device memory accesses. The recommended practice for writing
5756  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5757  * alt_write_word() functions.
5758  *
5759  * The struct declaration for register ALT_RSTMGR_PER1WARMMSK.
5760  */
5761 struct ALT_RSTMGR_PER1WARMMSK_s
5762 {
5763  uint32_t watchdog0 : 1; /* Watch Dog0 */
5764  uint32_t watchdog1 : 1; /* Watch Dog1 */
5765  uint32_t l4systimer0 : 1; /* l4systimer0 */
5766  uint32_t l4systimer1 : 1; /* l4systimer1 */
5767  uint32_t sptimer0 : 1; /* SP Timer 0 */
5768  uint32_t sptimer1 : 1; /* SP Timer 1 */
5769  uint32_t : 2; /* *UNDEFINED* */
5770  uint32_t i2c0 : 1; /* I2C0 */
5771  uint32_t i2c1 : 1; /* I2C1 */
5772  uint32_t i2c2 : 1; /* I2C2 */
5773  uint32_t i2c3 : 1; /* I2C3 */
5774  uint32_t i2c4 : 1; /* I2C4 */
5775  uint32_t : 3; /* *UNDEFINED* */
5776  uint32_t uart0 : 1; /* UART0 */
5777  uint32_t uart1 : 1; /* UART1 */
5778  uint32_t : 6; /* *UNDEFINED* */
5779  uint32_t gpio0 : 1; /* GPIO0 */
5780  uint32_t gpio1 : 1; /* GPIO1 */
5781  uint32_t gpio2 : 1; /* GPIO2 */
5782  uint32_t : 5; /* *UNDEFINED* */
5783 };
5784 
5785 /* The typedef declaration for register ALT_RSTMGR_PER1WARMMSK. */
5786 typedef volatile struct ALT_RSTMGR_PER1WARMMSK_s ALT_RSTMGR_PER1WARMMSK_t;
5787 #endif /* __ASSEMBLY__ */
5788 
5789 /* The reset value of the ALT_RSTMGR_PER1WARMMSK register. */
5790 #define ALT_RSTMGR_PER1WARMMSK_RESET 0x07031f3f
5791 /* The byte offset of the ALT_RSTMGR_PER1WARMMSK register from the beginning of the component. */
5792 #define ALT_RSTMGR_PER1WARMMSK_OFST 0x48
5793 
5794 /*
5795  * Register : Bridge Warm Mask Register - brgwarmmask
5796  *
5797  * The Bridge_WARM_MASK register is used by software to mask the assertion of
5798  * module reset signals for hardware sequenced warm resets. There is a writeable
5799  * bit for each module reset signal that is asserted by default on a hardware
5800  * sequenced warm reset. If the bit is 1, the module reset signal is asserted by a
5801  * hardware sequenced warm reset. If the bit is 0, the module reset signal is not
5802  * changed by a hardware sequenced warm reset. The bit assignments of the *WARMMASK
5803  * registers match the corresponding *MODRST registers. Any module reset signals
5804  * that are never asserted by a warm reset have reserved bit offsets and are tied
5805  * to 0 (read as 0, writes are ignored).
5806  *
5807  * All fields are only reset by a cold reset.
5808  *
5809  * Register Layout
5810  *
5811  * Bits | Access | Reset | Description
5812  * :-------|:-------|:------|:------------------
5813  * [0] | RW | 0x1 | HPS2FPGA Bridge
5814  * [1] | RW | 0x1 | LWHPS2FPGA Bridge
5815  * [2] | RW | 0x1 | FPGA2HPS Bridge
5816  * [3] | RW | 0x1 | F2S SDRAM0 Bridge
5817  * [4] | RW | 0x1 | F2S SDRAM1 Bridge
5818  * [5] | RW | 0x1 | F2S SDRAM2 Bridge
5819  * [6] | RW | 0x1 | DDR Scheduler
5820  * [31:7] | ??? | 0x0 | *UNDEFINED*
5821  *
5822  */
5823 /*
5824  * Field : HPS2FPGA Bridge - hps2fpga
5825  *
5826  * Masks hardware sequenced warm reset for HPS2FPGA Bridge
5827  *
5828  * Field Access Macros:
5829  *
5830  */
5831 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGWARMMSK_H2F register field. */
5832 #define ALT_RSTMGR_BRGWARMMSK_H2F_LSB 0
5833 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGWARMMSK_H2F register field. */
5834 #define ALT_RSTMGR_BRGWARMMSK_H2F_MSB 0
5835 /* The width in bits of the ALT_RSTMGR_BRGWARMMSK_H2F register field. */
5836 #define ALT_RSTMGR_BRGWARMMSK_H2F_WIDTH 1
5837 /* The mask used to set the ALT_RSTMGR_BRGWARMMSK_H2F register field value. */
5838 #define ALT_RSTMGR_BRGWARMMSK_H2F_SET_MSK 0x00000001
5839 /* The mask used to clear the ALT_RSTMGR_BRGWARMMSK_H2F register field value. */
5840 #define ALT_RSTMGR_BRGWARMMSK_H2F_CLR_MSK 0xfffffffe
5841 /* The reset value of the ALT_RSTMGR_BRGWARMMSK_H2F register field. */
5842 #define ALT_RSTMGR_BRGWARMMSK_H2F_RESET 0x1
5843 /* Extracts the ALT_RSTMGR_BRGWARMMSK_H2F field value from a register. */
5844 #define ALT_RSTMGR_BRGWARMMSK_H2F_GET(value) (((value) & 0x00000001) >> 0)
5845 /* Produces a ALT_RSTMGR_BRGWARMMSK_H2F register field value suitable for setting the register. */
5846 #define ALT_RSTMGR_BRGWARMMSK_H2F_SET(value) (((value) << 0) & 0x00000001)
5847 
5848 /*
5849  * Field : LWHPS2FPGA Bridge - lwhps2fpga
5850  *
5851  * Masks hardware sequenced warm reset for LWHPS2FPGA Bridge
5852  *
5853  * Field Access Macros:
5854  *
5855  */
5856 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGWARMMSK_LWH2F register field. */
5857 #define ALT_RSTMGR_BRGWARMMSK_LWH2F_LSB 1
5858 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGWARMMSK_LWH2F register field. */
5859 #define ALT_RSTMGR_BRGWARMMSK_LWH2F_MSB 1
5860 /* The width in bits of the ALT_RSTMGR_BRGWARMMSK_LWH2F register field. */
5861 #define ALT_RSTMGR_BRGWARMMSK_LWH2F_WIDTH 1
5862 /* The mask used to set the ALT_RSTMGR_BRGWARMMSK_LWH2F register field value. */
5863 #define ALT_RSTMGR_BRGWARMMSK_LWH2F_SET_MSK 0x00000002
5864 /* The mask used to clear the ALT_RSTMGR_BRGWARMMSK_LWH2F register field value. */
5865 #define ALT_RSTMGR_BRGWARMMSK_LWH2F_CLR_MSK 0xfffffffd
5866 /* The reset value of the ALT_RSTMGR_BRGWARMMSK_LWH2F register field. */
5867 #define ALT_RSTMGR_BRGWARMMSK_LWH2F_RESET 0x1
5868 /* Extracts the ALT_RSTMGR_BRGWARMMSK_LWH2F field value from a register. */
5869 #define ALT_RSTMGR_BRGWARMMSK_LWH2F_GET(value) (((value) & 0x00000002) >> 1)
5870 /* Produces a ALT_RSTMGR_BRGWARMMSK_LWH2F register field value suitable for setting the register. */
5871 #define ALT_RSTMGR_BRGWARMMSK_LWH2F_SET(value) (((value) << 1) & 0x00000002)
5872 
5873 /*
5874  * Field : FPGA2HPS Bridge - fpga2hps
5875  *
5876  * Masks hardware sequenced warm reset for FPGA2HPS Bridge
5877  *
5878  * Field Access Macros:
5879  *
5880  */
5881 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGWARMMSK_F2H register field. */
5882 #define ALT_RSTMGR_BRGWARMMSK_F2H_LSB 2
5883 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGWARMMSK_F2H register field. */
5884 #define ALT_RSTMGR_BRGWARMMSK_F2H_MSB 2
5885 /* The width in bits of the ALT_RSTMGR_BRGWARMMSK_F2H register field. */
5886 #define ALT_RSTMGR_BRGWARMMSK_F2H_WIDTH 1
5887 /* The mask used to set the ALT_RSTMGR_BRGWARMMSK_F2H register field value. */
5888 #define ALT_RSTMGR_BRGWARMMSK_F2H_SET_MSK 0x00000004
5889 /* The mask used to clear the ALT_RSTMGR_BRGWARMMSK_F2H register field value. */
5890 #define ALT_RSTMGR_BRGWARMMSK_F2H_CLR_MSK 0xfffffffb
5891 /* The reset value of the ALT_RSTMGR_BRGWARMMSK_F2H register field. */
5892 #define ALT_RSTMGR_BRGWARMMSK_F2H_RESET 0x1
5893 /* Extracts the ALT_RSTMGR_BRGWARMMSK_F2H field value from a register. */
5894 #define ALT_RSTMGR_BRGWARMMSK_F2H_GET(value) (((value) & 0x00000004) >> 2)
5895 /* Produces a ALT_RSTMGR_BRGWARMMSK_F2H register field value suitable for setting the register. */
5896 #define ALT_RSTMGR_BRGWARMMSK_F2H_SET(value) (((value) << 2) & 0x00000004)
5897 
5898 /*
5899  * Field : F2S SDRAM0 Bridge - f2ssdram0
5900  *
5901  * Masks hardware sequenced warm reset for F2S_SDRAM0 Bridge
5902  *
5903  * Field Access Macros:
5904  *
5905  */
5906 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0 register field. */
5907 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_LSB 3
5908 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0 register field. */
5909 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_MSB 3
5910 /* The width in bits of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0 register field. */
5911 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_WIDTH 1
5912 /* The mask used to set the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0 register field value. */
5913 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_SET_MSK 0x00000008
5914 /* The mask used to clear the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0 register field value. */
5915 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_CLR_MSK 0xfffffff7
5916 /* The reset value of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0 register field. */
5917 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_RESET 0x1
5918 /* Extracts the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0 field value from a register. */
5919 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_GET(value) (((value) & 0x00000008) >> 3)
5920 /* Produces a ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0 register field value suitable for setting the register. */
5921 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_SET(value) (((value) << 3) & 0x00000008)
5922 
5923 /*
5924  * Field : F2S SDRAM1 Bridge - f2ssdram1
5925  *
5926  * Masks hardware sequenced warm reset for F2S_SDRAM1 Bridge
5927  *
5928  * Field Access Macros:
5929  *
5930  */
5931 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1 register field. */
5932 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_LSB 4
5933 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1 register field. */
5934 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_MSB 4
5935 /* The width in bits of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1 register field. */
5936 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_WIDTH 1
5937 /* The mask used to set the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1 register field value. */
5938 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_SET_MSK 0x00000010
5939 /* The mask used to clear the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1 register field value. */
5940 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_CLR_MSK 0xffffffef
5941 /* The reset value of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1 register field. */
5942 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_RESET 0x1
5943 /* Extracts the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1 field value from a register. */
5944 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_GET(value) (((value) & 0x00000010) >> 4)
5945 /* Produces a ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1 register field value suitable for setting the register. */
5946 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_SET(value) (((value) << 4) & 0x00000010)
5947 
5948 /*
5949  * Field : F2S SDRAM2 Bridge - f2ssdram2
5950  *
5951  * Masks hardware sequenced warm reset for F2S_SDRAM2 Bridge
5952  *
5953  * Field Access Macros:
5954  *
5955  */
5956 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2 register field. */
5957 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_LSB 5
5958 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2 register field. */
5959 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_MSB 5
5960 /* The width in bits of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2 register field. */
5961 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_WIDTH 1
5962 /* The mask used to set the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2 register field value. */
5963 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_SET_MSK 0x00000020
5964 /* The mask used to clear the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2 register field value. */
5965 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_CLR_MSK 0xffffffdf
5966 /* The reset value of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2 register field. */
5967 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_RESET 0x1
5968 /* Extracts the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2 field value from a register. */
5969 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_GET(value) (((value) & 0x00000020) >> 5)
5970 /* Produces a ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2 register field value suitable for setting the register. */
5971 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_SET(value) (((value) << 5) & 0x00000020)
5972 
5973 /*
5974  * Field : DDR Scheduler - ddrsch
5975  *
5976  * Masks hardware sequenced warm reset for the DDR Scheduler in the NOC.
5977  *
5978  * Field Access Macros:
5979  *
5980  */
5981 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGWARMMSK_DDRSCH register field. */
5982 #define ALT_RSTMGR_BRGWARMMSK_DDRSCH_LSB 6
5983 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGWARMMSK_DDRSCH register field. */
5984 #define ALT_RSTMGR_BRGWARMMSK_DDRSCH_MSB 6
5985 /* The width in bits of the ALT_RSTMGR_BRGWARMMSK_DDRSCH register field. */
5986 #define ALT_RSTMGR_BRGWARMMSK_DDRSCH_WIDTH 1
5987 /* The mask used to set the ALT_RSTMGR_BRGWARMMSK_DDRSCH register field value. */
5988 #define ALT_RSTMGR_BRGWARMMSK_DDRSCH_SET_MSK 0x00000040
5989 /* The mask used to clear the ALT_RSTMGR_BRGWARMMSK_DDRSCH register field value. */
5990 #define ALT_RSTMGR_BRGWARMMSK_DDRSCH_CLR_MSK 0xffffffbf
5991 /* The reset value of the ALT_RSTMGR_BRGWARMMSK_DDRSCH register field. */
5992 #define ALT_RSTMGR_BRGWARMMSK_DDRSCH_RESET 0x1
5993 /* Extracts the ALT_RSTMGR_BRGWARMMSK_DDRSCH field value from a register. */
5994 #define ALT_RSTMGR_BRGWARMMSK_DDRSCH_GET(value) (((value) & 0x00000040) >> 6)
5995 /* Produces a ALT_RSTMGR_BRGWARMMSK_DDRSCH register field value suitable for setting the register. */
5996 #define ALT_RSTMGR_BRGWARMMSK_DDRSCH_SET(value) (((value) << 6) & 0x00000040)
5997 
5998 #ifndef __ASSEMBLY__
5999 /*
6000  * WARNING: The C register and register group struct declarations are provided for
6001  * convenience and illustrative purposes. They should, however, be used with
6002  * caution as the C language standard provides no guarantees about the alignment or
6003  * atomicity of device memory accesses. The recommended practice for writing
6004  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6005  * alt_write_word() functions.
6006  *
6007  * The struct declaration for register ALT_RSTMGR_BRGWARMMSK.
6008  */
6009 struct ALT_RSTMGR_BRGWARMMSK_s
6010 {
6011  uint32_t hps2fpga : 1; /* HPS2FPGA Bridge */
6012  uint32_t lwhps2fpga : 1; /* LWHPS2FPGA Bridge */
6013  uint32_t fpga2hps : 1; /* FPGA2HPS Bridge */
6014  uint32_t f2ssdram0 : 1; /* F2S SDRAM0 Bridge */
6015  uint32_t f2ssdram1 : 1; /* F2S SDRAM1 Bridge */
6016  uint32_t f2ssdram2 : 1; /* F2S SDRAM2 Bridge */
6017  uint32_t ddrsch : 1; /* DDR Scheduler */
6018  uint32_t : 25; /* *UNDEFINED* */
6019 };
6020 
6021 /* The typedef declaration for register ALT_RSTMGR_BRGWARMMSK. */
6022 typedef volatile struct ALT_RSTMGR_BRGWARMMSK_s ALT_RSTMGR_BRGWARMMSK_t;
6023 #endif /* __ASSEMBLY__ */
6024 
6025 /* The reset value of the ALT_RSTMGR_BRGWARMMSK register. */
6026 #define ALT_RSTMGR_BRGWARMMSK_RESET 0x0000007f
6027 /* The byte offset of the ALT_RSTMGR_BRGWARMMSK register from the beginning of the component. */
6028 #define ALT_RSTMGR_BRGWARMMSK_OFST 0x4c
6029 
6030 /*
6031  * Register : SYSTEM Warm Mask Register - syswarmmask
6032  *
6033  * The SYSWARMMASK register is used by software to mask the assertion of module
6034  * reset signals for hardware sequenced warm resets. There is a writeable bit for
6035  * each module reset signal that is asserted by default on a hardware sequenced
6036  * warm reset. If the bit is 1, the module reset signal is asserted by a hardware
6037  * sequenced warm reset. If the bit is 0, the module reset signal is not changed by
6038  * a hardware sequenced warm reset. The bit assignments of the *WARMMASK registers
6039  * match the corresponding *MODRST registers. Any module reset signals that are
6040  * never asserted by a warm reset have reserved bit offsets and are tied to 0 (read
6041  * as 0, writes are ignored).
6042  *
6043  * All fields are only reset by a cold reset.
6044  *
6045  * Fields in the SYSMODRST register associated with cold reset or debug domain
6046  * reset aren't present in the MISCWARMMASK register and are reserved.
6047  *
6048  * Register Layout
6049  *
6050  * Bits | Access | Reset | Description
6051  * :-------|:-------|:------|:--------------------------------
6052  * [0] | RW | 0x1 | Boot ROM
6053  * [1] | RW | 0x1 | On-chip RAM
6054  * [2] | ??? | 0x1 | *UNDEFINED*
6055  * [3] | RW | 0x1 | FPGA Manager
6056  * [4] | RW | 0x1 | HPS to FPGA Core (Cold or Warm)
6057  * [5] | RW | 0x1 | System/Debug
6058  * [6] | RW | 0x1 | On-chip RAM ECC OCP Diagnostic
6059  * [31:7] | ??? | 0x3 | *UNDEFINED*
6060  *
6061  */
6062 /*
6063  * Field : Boot ROM - rom
6064  *
6065  * Masks hardware sequenced warm reset for Boot ROM
6066  *
6067  * Field Access Macros:
6068  *
6069  */
6070 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_SYSWARMMSK_ROM register field. */
6071 #define ALT_RSTMGR_SYSWARMMSK_ROM_LSB 0
6072 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_SYSWARMMSK_ROM register field. */
6073 #define ALT_RSTMGR_SYSWARMMSK_ROM_MSB 0
6074 /* The width in bits of the ALT_RSTMGR_SYSWARMMSK_ROM register field. */
6075 #define ALT_RSTMGR_SYSWARMMSK_ROM_WIDTH 1
6076 /* The mask used to set the ALT_RSTMGR_SYSWARMMSK_ROM register field value. */
6077 #define ALT_RSTMGR_SYSWARMMSK_ROM_SET_MSK 0x00000001
6078 /* The mask used to clear the ALT_RSTMGR_SYSWARMMSK_ROM register field value. */
6079 #define ALT_RSTMGR_SYSWARMMSK_ROM_CLR_MSK 0xfffffffe
6080 /* The reset value of the ALT_RSTMGR_SYSWARMMSK_ROM register field. */
6081 #define ALT_RSTMGR_SYSWARMMSK_ROM_RESET 0x1
6082 /* Extracts the ALT_RSTMGR_SYSWARMMSK_ROM field value from a register. */
6083 #define ALT_RSTMGR_SYSWARMMSK_ROM_GET(value) (((value) & 0x00000001) >> 0)
6084 /* Produces a ALT_RSTMGR_SYSWARMMSK_ROM register field value suitable for setting the register. */
6085 #define ALT_RSTMGR_SYSWARMMSK_ROM_SET(value) (((value) << 0) & 0x00000001)
6086 
6087 /*
6088  * Field : On-chip RAM - ocram
6089  *
6090  * Masks hardware sequenced warm reset for On-chip RAM
6091  *
6092  * Field Access Macros:
6093  *
6094  */
6095 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_SYSWARMMSK_OCRAM register field. */
6096 #define ALT_RSTMGR_SYSWARMMSK_OCRAM_LSB 1
6097 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_SYSWARMMSK_OCRAM register field. */
6098 #define ALT_RSTMGR_SYSWARMMSK_OCRAM_MSB 1
6099 /* The width in bits of the ALT_RSTMGR_SYSWARMMSK_OCRAM register field. */
6100 #define ALT_RSTMGR_SYSWARMMSK_OCRAM_WIDTH 1
6101 /* The mask used to set the ALT_RSTMGR_SYSWARMMSK_OCRAM register field value. */
6102 #define ALT_RSTMGR_SYSWARMMSK_OCRAM_SET_MSK 0x00000002
6103 /* The mask used to clear the ALT_RSTMGR_SYSWARMMSK_OCRAM register field value. */
6104 #define ALT_RSTMGR_SYSWARMMSK_OCRAM_CLR_MSK 0xfffffffd
6105 /* The reset value of the ALT_RSTMGR_SYSWARMMSK_OCRAM register field. */
6106 #define ALT_RSTMGR_SYSWARMMSK_OCRAM_RESET 0x1
6107 /* Extracts the ALT_RSTMGR_SYSWARMMSK_OCRAM field value from a register. */
6108 #define ALT_RSTMGR_SYSWARMMSK_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
6109 /* Produces a ALT_RSTMGR_SYSWARMMSK_OCRAM register field value suitable for setting the register. */
6110 #define ALT_RSTMGR_SYSWARMMSK_OCRAM_SET(value) (((value) << 1) & 0x00000002)
6111 
6112 /*
6113  * Field : FPGA Manager - fpgamgr
6114  *
6115  * Masks hardware sequenced warm reset for FPGA Manager
6116  *
6117  * Field Access Macros:
6118  *
6119  */
6120 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_SYSWARMMSK_FPGAMGR register field. */
6121 #define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_LSB 3
6122 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_SYSWARMMSK_FPGAMGR register field. */
6123 #define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_MSB 3
6124 /* The width in bits of the ALT_RSTMGR_SYSWARMMSK_FPGAMGR register field. */
6125 #define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_WIDTH 1
6126 /* The mask used to set the ALT_RSTMGR_SYSWARMMSK_FPGAMGR register field value. */
6127 #define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_SET_MSK 0x00000008
6128 /* The mask used to clear the ALT_RSTMGR_SYSWARMMSK_FPGAMGR register field value. */
6129 #define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_CLR_MSK 0xfffffff7
6130 /* The reset value of the ALT_RSTMGR_SYSWARMMSK_FPGAMGR register field. */
6131 #define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_RESET 0x1
6132 /* Extracts the ALT_RSTMGR_SYSWARMMSK_FPGAMGR field value from a register. */
6133 #define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_GET(value) (((value) & 0x00000008) >> 3)
6134 /* Produces a ALT_RSTMGR_SYSWARMMSK_FPGAMGR register field value suitable for setting the register. */
6135 #define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_SET(value) (((value) << 3) & 0x00000008)
6136 
6137 /*
6138  * Field : HPS to FPGA Core (Cold or Warm) - s2f
6139  *
6140  * Masks hardware sequenced warm reset for logic in FPGA core that doesn't
6141  * differentiate between HPS cold and warm resets
6142  *
6143  * Field Access Macros:
6144  *
6145  */
6146 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_SYSWARMMSK_S2F register field. */
6147 #define ALT_RSTMGR_SYSWARMMSK_S2F_LSB 4
6148 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_SYSWARMMSK_S2F register field. */
6149 #define ALT_RSTMGR_SYSWARMMSK_S2F_MSB 4
6150 /* The width in bits of the ALT_RSTMGR_SYSWARMMSK_S2F register field. */
6151 #define ALT_RSTMGR_SYSWARMMSK_S2F_WIDTH 1
6152 /* The mask used to set the ALT_RSTMGR_SYSWARMMSK_S2F register field value. */
6153 #define ALT_RSTMGR_SYSWARMMSK_S2F_SET_MSK 0x00000010
6154 /* The mask used to clear the ALT_RSTMGR_SYSWARMMSK_S2F register field value. */
6155 #define ALT_RSTMGR_SYSWARMMSK_S2F_CLR_MSK 0xffffffef
6156 /* The reset value of the ALT_RSTMGR_SYSWARMMSK_S2F register field. */
6157 #define ALT_RSTMGR_SYSWARMMSK_S2F_RESET 0x1
6158 /* Extracts the ALT_RSTMGR_SYSWARMMSK_S2F field value from a register. */
6159 #define ALT_RSTMGR_SYSWARMMSK_S2F_GET(value) (((value) & 0x00000010) >> 4)
6160 /* Produces a ALT_RSTMGR_SYSWARMMSK_S2F register field value suitable for setting the register. */
6161 #define ALT_RSTMGR_SYSWARMMSK_S2F_SET(value) (((value) << 4) & 0x00000010)
6162 
6163 /*
6164  * Field : System/Debug - sysdbg
6165  *
6166  * Masks hardware sequenced warm reset for logic that spans the system and debug
6167  * domains.
6168  *
6169  * Field Access Macros:
6170  *
6171  */
6172 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_SYSWARMMSK_SYSDBG register field. */
6173 #define ALT_RSTMGR_SYSWARMMSK_SYSDBG_LSB 5
6174 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_SYSWARMMSK_SYSDBG register field. */
6175 #define ALT_RSTMGR_SYSWARMMSK_SYSDBG_MSB 5
6176 /* The width in bits of the ALT_RSTMGR_SYSWARMMSK_SYSDBG register field. */
6177 #define ALT_RSTMGR_SYSWARMMSK_SYSDBG_WIDTH 1
6178 /* The mask used to set the ALT_RSTMGR_SYSWARMMSK_SYSDBG register field value. */
6179 #define ALT_RSTMGR_SYSWARMMSK_SYSDBG_SET_MSK 0x00000020
6180 /* The mask used to clear the ALT_RSTMGR_SYSWARMMSK_SYSDBG register field value. */
6181 #define ALT_RSTMGR_SYSWARMMSK_SYSDBG_CLR_MSK 0xffffffdf
6182 /* The reset value of the ALT_RSTMGR_SYSWARMMSK_SYSDBG register field. */
6183 #define ALT_RSTMGR_SYSWARMMSK_SYSDBG_RESET 0x1
6184 /* Extracts the ALT_RSTMGR_SYSWARMMSK_SYSDBG field value from a register. */
6185 #define ALT_RSTMGR_SYSWARMMSK_SYSDBG_GET(value) (((value) & 0x00000020) >> 5)
6186 /* Produces a ALT_RSTMGR_SYSWARMMSK_SYSDBG register field value suitable for setting the register. */
6187 #define ALT_RSTMGR_SYSWARMMSK_SYSDBG_SET(value) (((value) << 5) & 0x00000020)
6188 
6189 /*
6190  * Field : On-chip RAM ECC OCP Diagnostic - ocramocp
6191  *
6192  * Masks hardware sequenced warm reset for On-chip RAM ECC OCP Diagnostic module
6193  *
6194  * Field Access Macros:
6195  *
6196  */
6197 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_SYSWARMMSK_OCRAMOCP register field. */
6198 #define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_LSB 6
6199 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_SYSWARMMSK_OCRAMOCP register field. */
6200 #define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_MSB 6
6201 /* The width in bits of the ALT_RSTMGR_SYSWARMMSK_OCRAMOCP register field. */
6202 #define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_WIDTH 1
6203 /* The mask used to set the ALT_RSTMGR_SYSWARMMSK_OCRAMOCP register field value. */
6204 #define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_SET_MSK 0x00000040
6205 /* The mask used to clear the ALT_RSTMGR_SYSWARMMSK_OCRAMOCP register field value. */
6206 #define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_CLR_MSK 0xffffffbf
6207 /* The reset value of the ALT_RSTMGR_SYSWARMMSK_OCRAMOCP register field. */
6208 #define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_RESET 0x1
6209 /* Extracts the ALT_RSTMGR_SYSWARMMSK_OCRAMOCP field value from a register. */
6210 #define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_GET(value) (((value) & 0x00000040) >> 6)
6211 /* Produces a ALT_RSTMGR_SYSWARMMSK_OCRAMOCP register field value suitable for setting the register. */
6212 #define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_SET(value) (((value) << 6) & 0x00000040)
6213 
6214 #ifndef __ASSEMBLY__
6215 /*
6216  * WARNING: The C register and register group struct declarations are provided for
6217  * convenience and illustrative purposes. They should, however, be used with
6218  * caution as the C language standard provides no guarantees about the alignment or
6219  * atomicity of device memory accesses. The recommended practice for writing
6220  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6221  * alt_write_word() functions.
6222  *
6223  * The struct declaration for register ALT_RSTMGR_SYSWARMMSK.
6224  */
6225 struct ALT_RSTMGR_SYSWARMMSK_s
6226 {
6227  uint32_t rom : 1; /* Boot ROM */
6228  uint32_t ocram : 1; /* On-chip RAM */
6229  uint32_t : 1; /* *UNDEFINED* */
6230  uint32_t fpgamgr : 1; /* FPGA Manager */
6231  uint32_t s2f : 1; /* HPS to FPGA Core (Cold or Warm) */
6232  uint32_t sysdbg : 1; /* System/Debug */
6233  uint32_t ocramocp : 1; /* On-chip RAM ECC OCP Diagnostic */
6234  uint32_t : 25; /* *UNDEFINED* */
6235 };
6236 
6237 /* The typedef declaration for register ALT_RSTMGR_SYSWARMMSK. */
6238 typedef volatile struct ALT_RSTMGR_SYSWARMMSK_s ALT_RSTMGR_SYSWARMMSK_t;
6239 #endif /* __ASSEMBLY__ */
6240 
6241 /* The reset value of the ALT_RSTMGR_SYSWARMMSK register. */
6242 #define ALT_RSTMGR_SYSWARMMSK_RESET 0x000001ff
6243 /* The byte offset of the ALT_RSTMGR_SYSWARMMSK register from the beginning of the component. */
6244 #define ALT_RSTMGR_SYSWARMMSK_OFST 0x50
6245 
6246 /*
6247  * Register : NRST Warm Mask Register - nrstwarmmask
6248  *
6249  * The NRSTWARMMASK register is used by software to mask the assertion of module
6250  * reset signals for hardware sequenced warm resets. There is a writeable bit for
6251  * each module reset signal that is asserted by default on a hardware sequenced
6252  * warm reset. If the bit is 1, the module reset signal is asserted by a hardware
6253  * sequenced warm reset. If the bit is 0, the module reset signal is not changed by
6254  * a hardware sequenced warm reset. The bit assignments of the *WARMMASK registers
6255  * match the corresponding *MODRST registers. Any module reset signals that are
6256  * never asserted by a warm reset have reserved bit offsets and are tied to 0 (read
6257  * as 0, writes are ignored).
6258  *
6259  * All fields are only reset by a cold reset.
6260  *
6261  * Fields in the MISCMODRST register associated with cold reset or debug domain
6262  * reset aren't present in the MISCWARMMASK register and are reserved.
6263  *
6264  * Register Layout
6265  *
6266  * Bits | Access | Reset | Description
6267  * :-------|:-------|:------|:------------
6268  * [0] | RW | 0x1 | nRST Pin OE
6269  * [31:1] | ??? | 0x0 | *UNDEFINED*
6270  *
6271  */
6272 /*
6273  * Field : nRST Pin OE - nrstpinoe
6274  *
6275  * Masks hardware sequenced warm reset for nrst_pin_oe
6276  *
6277  * Field Access Macros:
6278  *
6279  */
6280 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE register field. */
6281 #define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_LSB 0
6282 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE register field. */
6283 #define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_MSB 0
6284 /* The width in bits of the ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE register field. */
6285 #define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_WIDTH 1
6286 /* The mask used to set the ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE register field value. */
6287 #define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_SET_MSK 0x00000001
6288 /* The mask used to clear the ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE register field value. */
6289 #define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_CLR_MSK 0xfffffffe
6290 /* The reset value of the ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE register field. */
6291 #define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_RESET 0x1
6292 /* Extracts the ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE field value from a register. */
6293 #define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_GET(value) (((value) & 0x00000001) >> 0)
6294 /* Produces a ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE register field value suitable for setting the register. */
6295 #define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_SET(value) (((value) << 0) & 0x00000001)
6296 
6297 #ifndef __ASSEMBLY__
6298 /*
6299  * WARNING: The C register and register group struct declarations are provided for
6300  * convenience and illustrative purposes. They should, however, be used with
6301  * caution as the C language standard provides no guarantees about the alignment or
6302  * atomicity of device memory accesses. The recommended practice for writing
6303  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6304  * alt_write_word() functions.
6305  *
6306  * The struct declaration for register ALT_RSTMGR_NRSTWARMMSK.
6307  */
6308 struct ALT_RSTMGR_NRSTWARMMSK_s
6309 {
6310  uint32_t nrstpinoe : 1; /* nRST Pin OE */
6311  uint32_t : 31; /* *UNDEFINED* */
6312 };
6313 
6314 /* The typedef declaration for register ALT_RSTMGR_NRSTWARMMSK. */
6315 typedef volatile struct ALT_RSTMGR_NRSTWARMMSK_s ALT_RSTMGR_NRSTWARMMSK_t;
6316 #endif /* __ASSEMBLY__ */
6317 
6318 /* The reset value of the ALT_RSTMGR_NRSTWARMMSK register. */
6319 #define ALT_RSTMGR_NRSTWARMMSK_RESET 0x00000001
6320 /* The byte offset of the ALT_RSTMGR_NRSTWARMMSK register from the beginning of the component. */
6321 #define ALT_RSTMGR_NRSTWARMMSK_OFST 0x54
6322 
6323 /*
6324  * Register : Mask L3 Register - l3warmmask
6325  *
6326  * The L3WARMMASK register is used by software to mask the assertion of module
6327  * reset signals for hardware sequenced warm resets. There is a writeable bit for
6328  * each module reset signal that is asserted by default on a hardware sequenced
6329  * warm reset. If the bit is 1, the module reset signal is asserted by a hardware
6330  * sequenced warm reset. If the bit is 0, the module reset signal is not changed by
6331  * a hardware sequenced warm reset. The bit assignments of the *WARMMASK registers
6332  * match the corresponding *MODRST registers. Any module reset signals that are
6333  * never asserted by a warm reset have reserved bit offsets and are tied to 0 (read
6334  * as 0, writes are ignored).
6335  *
6336  * All fields are only reset by a cold reset.
6337  *
6338  * Note that there is no module reset for the L3 interconnect in any *MODRST
6339  * register because there would be no way for a master to remove the module reset
6340  * to the L3 once asserted.
6341  *
6342  * Register Layout
6343  *
6344  * Bits | Access | Reset | Description
6345  * :-------|:-------|:------|:----------------
6346  * [0] | RW | 0x1 | L3 Interconnect
6347  * [31:1] | ??? | 0x0 | *UNDEFINED*
6348  *
6349  */
6350 /*
6351  * Field : L3 Interconnect - l3
6352  *
6353  * Masks hardware sequenced warm reset to L3 Interconnect
6354  *
6355  * Field Access Macros:
6356  *
6357  */
6358 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_L3WARMMSK_L3 register field. */
6359 #define ALT_RSTMGR_L3WARMMSK_L3_LSB 0
6360 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_L3WARMMSK_L3 register field. */
6361 #define ALT_RSTMGR_L3WARMMSK_L3_MSB 0
6362 /* The width in bits of the ALT_RSTMGR_L3WARMMSK_L3 register field. */
6363 #define ALT_RSTMGR_L3WARMMSK_L3_WIDTH 1
6364 /* The mask used to set the ALT_RSTMGR_L3WARMMSK_L3 register field value. */
6365 #define ALT_RSTMGR_L3WARMMSK_L3_SET_MSK 0x00000001
6366 /* The mask used to clear the ALT_RSTMGR_L3WARMMSK_L3 register field value. */
6367 #define ALT_RSTMGR_L3WARMMSK_L3_CLR_MSK 0xfffffffe
6368 /* The reset value of the ALT_RSTMGR_L3WARMMSK_L3 register field. */
6369 #define ALT_RSTMGR_L3WARMMSK_L3_RESET 0x1
6370 /* Extracts the ALT_RSTMGR_L3WARMMSK_L3 field value from a register. */
6371 #define ALT_RSTMGR_L3WARMMSK_L3_GET(value) (((value) & 0x00000001) >> 0)
6372 /* Produces a ALT_RSTMGR_L3WARMMSK_L3 register field value suitable for setting the register. */
6373 #define ALT_RSTMGR_L3WARMMSK_L3_SET(value) (((value) << 0) & 0x00000001)
6374 
6375 #ifndef __ASSEMBLY__
6376 /*
6377  * WARNING: The C register and register group struct declarations are provided for
6378  * convenience and illustrative purposes. They should, however, be used with
6379  * caution as the C language standard provides no guarantees about the alignment or
6380  * atomicity of device memory accesses. The recommended practice for writing
6381  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6382  * alt_write_word() functions.
6383  *
6384  * The struct declaration for register ALT_RSTMGR_L3WARMMSK.
6385  */
6386 struct ALT_RSTMGR_L3WARMMSK_s
6387 {
6388  uint32_t l3 : 1; /* L3 Interconnect */
6389  uint32_t : 31; /* *UNDEFINED* */
6390 };
6391 
6392 /* The typedef declaration for register ALT_RSTMGR_L3WARMMSK. */
6393 typedef volatile struct ALT_RSTMGR_L3WARMMSK_s ALT_RSTMGR_L3WARMMSK_t;
6394 #endif /* __ASSEMBLY__ */
6395 
6396 /* The reset value of the ALT_RSTMGR_L3WARMMSK register. */
6397 #define ALT_RSTMGR_L3WARMMSK_RESET 0x00000001
6398 /* The byte offset of the ALT_RSTMGR_L3WARMMSK register from the beginning of the component. */
6399 #define ALT_RSTMGR_L3WARMMSK_OFST 0x58
6400 
6401 /*
6402  * Register : Test Status - tststa
6403  *
6404  * status fields used for testing the Reset Manager.
6405  *
6406  * Register Layout
6407  *
6408  * Bits | Access | Reset | Description
6409  * :-------|:-------|:--------|:------------------
6410  * [3:0] | R | Unknown | warm reset state
6411  * [6:4] | R | Unknown | debug reset state
6412  * [31:7] | ??? | 0x0 | *UNDEFINED*
6413  *
6414  */
6415 /*
6416  * Field : warm reset state - warmrstst
6417  *
6418  * warm reset control FSM state
6419  *
6420  * Field Access Macros:
6421  *
6422  */
6423 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_TSTSTA_WARMRSTST register field. */
6424 #define ALT_RSTMGR_TSTSTA_WARMRSTST_LSB 0
6425 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_TSTSTA_WARMRSTST register field. */
6426 #define ALT_RSTMGR_TSTSTA_WARMRSTST_MSB 3
6427 /* The width in bits of the ALT_RSTMGR_TSTSTA_WARMRSTST register field. */
6428 #define ALT_RSTMGR_TSTSTA_WARMRSTST_WIDTH 4
6429 /* The mask used to set the ALT_RSTMGR_TSTSTA_WARMRSTST register field value. */
6430 #define ALT_RSTMGR_TSTSTA_WARMRSTST_SET_MSK 0x0000000f
6431 /* The mask used to clear the ALT_RSTMGR_TSTSTA_WARMRSTST register field value. */
6432 #define ALT_RSTMGR_TSTSTA_WARMRSTST_CLR_MSK 0xfffffff0
6433 /* The reset value of the ALT_RSTMGR_TSTSTA_WARMRSTST register field is UNKNOWN. */
6434 #define ALT_RSTMGR_TSTSTA_WARMRSTST_RESET 0x0
6435 /* Extracts the ALT_RSTMGR_TSTSTA_WARMRSTST field value from a register. */
6436 #define ALT_RSTMGR_TSTSTA_WARMRSTST_GET(value) (((value) & 0x0000000f) >> 0)
6437 /* Produces a ALT_RSTMGR_TSTSTA_WARMRSTST register field value suitable for setting the register. */
6438 #define ALT_RSTMGR_TSTSTA_WARMRSTST_SET(value) (((value) << 0) & 0x0000000f)
6439 
6440 /*
6441  * Field : debug reset state - dbgrstst
6442  *
6443  * debug reset control FSM state
6444  *
6445  * Field Access Macros:
6446  *
6447  */
6448 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_TSTSTA_DBGRSTST register field. */
6449 #define ALT_RSTMGR_TSTSTA_DBGRSTST_LSB 4
6450 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_TSTSTA_DBGRSTST register field. */
6451 #define ALT_RSTMGR_TSTSTA_DBGRSTST_MSB 6
6452 /* The width in bits of the ALT_RSTMGR_TSTSTA_DBGRSTST register field. */
6453 #define ALT_RSTMGR_TSTSTA_DBGRSTST_WIDTH 3
6454 /* The mask used to set the ALT_RSTMGR_TSTSTA_DBGRSTST register field value. */
6455 #define ALT_RSTMGR_TSTSTA_DBGRSTST_SET_MSK 0x00000070
6456 /* The mask used to clear the ALT_RSTMGR_TSTSTA_DBGRSTST register field value. */
6457 #define ALT_RSTMGR_TSTSTA_DBGRSTST_CLR_MSK 0xffffff8f
6458 /* The reset value of the ALT_RSTMGR_TSTSTA_DBGRSTST register field is UNKNOWN. */
6459 #define ALT_RSTMGR_TSTSTA_DBGRSTST_RESET 0x0
6460 /* Extracts the ALT_RSTMGR_TSTSTA_DBGRSTST field value from a register. */
6461 #define ALT_RSTMGR_TSTSTA_DBGRSTST_GET(value) (((value) & 0x00000070) >> 4)
6462 /* Produces a ALT_RSTMGR_TSTSTA_DBGRSTST register field value suitable for setting the register. */
6463 #define ALT_RSTMGR_TSTSTA_DBGRSTST_SET(value) (((value) << 4) & 0x00000070)
6464 
6465 #ifndef __ASSEMBLY__
6466 /*
6467  * WARNING: The C register and register group struct declarations are provided for
6468  * convenience and illustrative purposes. They should, however, be used with
6469  * caution as the C language standard provides no guarantees about the alignment or
6470  * atomicity of device memory accesses. The recommended practice for writing
6471  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6472  * alt_write_word() functions.
6473  *
6474  * The struct declaration for register ALT_RSTMGR_TSTSTA.
6475  */
6476 struct ALT_RSTMGR_TSTSTA_s
6477 {
6478  const uint32_t warmrstst : 4; /* warm reset state */
6479  const uint32_t dbgrstst : 3; /* debug reset state */
6480  uint32_t : 25; /* *UNDEFINED* */
6481 };
6482 
6483 /* The typedef declaration for register ALT_RSTMGR_TSTSTA. */
6484 typedef volatile struct ALT_RSTMGR_TSTSTA_s ALT_RSTMGR_TSTSTA_t;
6485 #endif /* __ASSEMBLY__ */
6486 
6487 /* The reset value of the ALT_RSTMGR_TSTSTA register. */
6488 #define ALT_RSTMGR_TSTSTA_RESET 0x00000000
6489 /* The byte offset of the ALT_RSTMGR_TSTSTA register from the beginning of the component. */
6490 #define ALT_RSTMGR_TSTSTA_OFST 0x5c
6491 
6492 /*
6493  * Register : Test Scratch - tstscratch
6494  *
6495  * SW can write/read this register without side effect to reset manager function.
6496  *
6497  * Register Layout
6498  *
6499  * Bits | Access | Reset | Description
6500  * :-------|:-------|:------|:------------
6501  * [31:0] | RW | 0x0 | field0
6502  *
6503  */
6504 /*
6505  * Field : field0 - fld0
6506  *
6507  * field for SW write/read
6508  *
6509  * Field Access Macros:
6510  *
6511  */
6512 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_TSTSCRATCH_FLD0 register field. */
6513 #define ALT_RSTMGR_TSTSCRATCH_FLD0_LSB 0
6514 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_TSTSCRATCH_FLD0 register field. */
6515 #define ALT_RSTMGR_TSTSCRATCH_FLD0_MSB 31
6516 /* The width in bits of the ALT_RSTMGR_TSTSCRATCH_FLD0 register field. */
6517 #define ALT_RSTMGR_TSTSCRATCH_FLD0_WIDTH 32
6518 /* The mask used to set the ALT_RSTMGR_TSTSCRATCH_FLD0 register field value. */
6519 #define ALT_RSTMGR_TSTSCRATCH_FLD0_SET_MSK 0xffffffff
6520 /* The mask used to clear the ALT_RSTMGR_TSTSCRATCH_FLD0 register field value. */
6521 #define ALT_RSTMGR_TSTSCRATCH_FLD0_CLR_MSK 0x00000000
6522 /* The reset value of the ALT_RSTMGR_TSTSCRATCH_FLD0 register field. */
6523 #define ALT_RSTMGR_TSTSCRATCH_FLD0_RESET 0x0
6524 /* Extracts the ALT_RSTMGR_TSTSCRATCH_FLD0 field value from a register. */
6525 #define ALT_RSTMGR_TSTSCRATCH_FLD0_GET(value) (((value) & 0xffffffff) >> 0)
6526 /* Produces a ALT_RSTMGR_TSTSCRATCH_FLD0 register field value suitable for setting the register. */
6527 #define ALT_RSTMGR_TSTSCRATCH_FLD0_SET(value) (((value) << 0) & 0xffffffff)
6528 
6529 #ifndef __ASSEMBLY__
6530 /*
6531  * WARNING: The C register and register group struct declarations are provided for
6532  * convenience and illustrative purposes. They should, however, be used with
6533  * caution as the C language standard provides no guarantees about the alignment or
6534  * atomicity of device memory accesses. The recommended practice for writing
6535  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6536  * alt_write_word() functions.
6537  *
6538  * The struct declaration for register ALT_RSTMGR_TSTSCRATCH.
6539  */
6540 struct ALT_RSTMGR_TSTSCRATCH_s
6541 {
6542  uint32_t fld0 : 32; /* field0 */
6543 };
6544 
6545 /* The typedef declaration for register ALT_RSTMGR_TSTSCRATCH. */
6546 typedef volatile struct ALT_RSTMGR_TSTSCRATCH_s ALT_RSTMGR_TSTSCRATCH_t;
6547 #endif /* __ASSEMBLY__ */
6548 
6549 /* The reset value of the ALT_RSTMGR_TSTSCRATCH register. */
6550 #define ALT_RSTMGR_TSTSCRATCH_RESET 0x00000000
6551 /* The byte offset of the ALT_RSTMGR_TSTSCRATCH register from the beginning of the component. */
6552 #define ALT_RSTMGR_TSTSCRATCH_OFST 0x60
6553 
6554 /*
6555  * Register : Hand Shake Time Out - hdsktimeout
6556  *
6557  * The Warm Reset handshake timeout will default to 10,240 which at 100 MHz for
6558  * l4_sys_free_clk will 102.4 micro-seconds. This value will be a 25 bit
6559  * programmable value in SW. The reason for this is the HMC adaptor may need a
6560  * longer time to clear all outstanding SDRAM transactions. The maximum
6561  * programmable value would be 20.97 msec
6562  *
6563  * Register Layout
6564  *
6565  * Bits | Access | Reset | Description
6566  * :--------|:-------|:-------|:------------------
6567  * [24:0] | RW | 0x2800 | handshake timeout
6568  * [31:25] | ??? | 0x0 | *UNDEFINED*
6569  *
6570  */
6571 /*
6572  * Field : handshake timeout - val
6573  *
6574  * hand shake timeout
6575  *
6576  * Field Access Macros:
6577  *
6578  */
6579 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKTMO_VAL register field. */
6580 #define ALT_RSTMGR_HDSKTMO_VAL_LSB 0
6581 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKTMO_VAL register field. */
6582 #define ALT_RSTMGR_HDSKTMO_VAL_MSB 24
6583 /* The width in bits of the ALT_RSTMGR_HDSKTMO_VAL register field. */
6584 #define ALT_RSTMGR_HDSKTMO_VAL_WIDTH 25
6585 /* The mask used to set the ALT_RSTMGR_HDSKTMO_VAL register field value. */
6586 #define ALT_RSTMGR_HDSKTMO_VAL_SET_MSK 0x01ffffff
6587 /* The mask used to clear the ALT_RSTMGR_HDSKTMO_VAL register field value. */
6588 #define ALT_RSTMGR_HDSKTMO_VAL_CLR_MSK 0xfe000000
6589 /* The reset value of the ALT_RSTMGR_HDSKTMO_VAL register field. */
6590 #define ALT_RSTMGR_HDSKTMO_VAL_RESET 0x2800
6591 /* Extracts the ALT_RSTMGR_HDSKTMO_VAL field value from a register. */
6592 #define ALT_RSTMGR_HDSKTMO_VAL_GET(value) (((value) & 0x01ffffff) >> 0)
6593 /* Produces a ALT_RSTMGR_HDSKTMO_VAL register field value suitable for setting the register. */
6594 #define ALT_RSTMGR_HDSKTMO_VAL_SET(value) (((value) << 0) & 0x01ffffff)
6595 
6596 #ifndef __ASSEMBLY__
6597 /*
6598  * WARNING: The C register and register group struct declarations are provided for
6599  * convenience and illustrative purposes. They should, however, be used with
6600  * caution as the C language standard provides no guarantees about the alignment or
6601  * atomicity of device memory accesses. The recommended practice for writing
6602  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6603  * alt_write_word() functions.
6604  *
6605  * The struct declaration for register ALT_RSTMGR_HDSKTMO.
6606  */
6607 struct ALT_RSTMGR_HDSKTMO_s
6608 {
6609  uint32_t val : 25; /* handshake timeout */
6610  uint32_t : 7; /* *UNDEFINED* */
6611 };
6612 
6613 /* The typedef declaration for register ALT_RSTMGR_HDSKTMO. */
6614 typedef volatile struct ALT_RSTMGR_HDSKTMO_s ALT_RSTMGR_HDSKTMO_t;
6615 #endif /* __ASSEMBLY__ */
6616 
6617 /* The reset value of the ALT_RSTMGR_HDSKTMO register. */
6618 #define ALT_RSTMGR_HDSKTMO_RESET 0x00002800
6619 /* The byte offset of the ALT_RSTMGR_HDSKTMO register from the beginning of the component. */
6620 #define ALT_RSTMGR_HDSKTMO_OFST 0x64
6621 
6622 /*
6623  * Register : HMC Interrupt - hmcintr
6624  *
6625  * HMC GPIO Interrupt
6626  *
6627  * Register Layout
6628  *
6629  * Bits | Access | Reset | Description
6630  * :-------|:-------|:------|:------------
6631  * [0] | RW | 0x0 | intr
6632  * [31:1] | ??? | 0x0 | *UNDEFINED*
6633  *
6634  */
6635 /*
6636  * Field : intr - intr
6637  *
6638  * Interrupt
6639  *
6640  * Field Access Macros:
6641  *
6642  */
6643 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HMCINTR_INTR register field. */
6644 #define ALT_RSTMGR_HMCINTR_INTR_LSB 0
6645 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HMCINTR_INTR register field. */
6646 #define ALT_RSTMGR_HMCINTR_INTR_MSB 0
6647 /* The width in bits of the ALT_RSTMGR_HMCINTR_INTR register field. */
6648 #define ALT_RSTMGR_HMCINTR_INTR_WIDTH 1
6649 /* The mask used to set the ALT_RSTMGR_HMCINTR_INTR register field value. */
6650 #define ALT_RSTMGR_HMCINTR_INTR_SET_MSK 0x00000001
6651 /* The mask used to clear the ALT_RSTMGR_HMCINTR_INTR register field value. */
6652 #define ALT_RSTMGR_HMCINTR_INTR_CLR_MSK 0xfffffffe
6653 /* The reset value of the ALT_RSTMGR_HMCINTR_INTR register field. */
6654 #define ALT_RSTMGR_HMCINTR_INTR_RESET 0x0
6655 /* Extracts the ALT_RSTMGR_HMCINTR_INTR field value from a register. */
6656 #define ALT_RSTMGR_HMCINTR_INTR_GET(value) (((value) & 0x00000001) >> 0)
6657 /* Produces a ALT_RSTMGR_HMCINTR_INTR register field value suitable for setting the register. */
6658 #define ALT_RSTMGR_HMCINTR_INTR_SET(value) (((value) << 0) & 0x00000001)
6659 
6660 #ifndef __ASSEMBLY__
6661 /*
6662  * WARNING: The C register and register group struct declarations are provided for
6663  * convenience and illustrative purposes. They should, however, be used with
6664  * caution as the C language standard provides no guarantees about the alignment or
6665  * atomicity of device memory accesses. The recommended practice for writing
6666  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6667  * alt_write_word() functions.
6668  *
6669  * The struct declaration for register ALT_RSTMGR_HMCINTR.
6670  */
6671 struct ALT_RSTMGR_HMCINTR_s
6672 {
6673  uint32_t intr : 1; /* intr */
6674  uint32_t : 31; /* *UNDEFINED* */
6675 };
6676 
6677 /* The typedef declaration for register ALT_RSTMGR_HMCINTR. */
6678 typedef volatile struct ALT_RSTMGR_HMCINTR_s ALT_RSTMGR_HMCINTR_t;
6679 #endif /* __ASSEMBLY__ */
6680 
6681 /* The reset value of the ALT_RSTMGR_HMCINTR register. */
6682 #define ALT_RSTMGR_HMCINTR_RESET 0x00000000
6683 /* The byte offset of the ALT_RSTMGR_HMCINTR register from the beginning of the component. */
6684 #define ALT_RSTMGR_HMCINTR_OFST 0x68
6685 
6686 /*
6687  * Register : HMC Interrupt enable - hmcintren
6688  *
6689  * HMC Interrupt Enable
6690  *
6691  * Register Layout
6692  *
6693  * Bits | Access | Reset | Description
6694  * :-------|:-------|:------|:---------------------
6695  * [0] | RW | 0x0 | HMC Interrupt Enable
6696  * [31:1] | ??? | 0x0 | *UNDEFINED*
6697  *
6698  */
6699 /*
6700  * Field : HMC Interrupt Enable - en
6701  *
6702  * HMC Interrupt Enable Signal for hmcintr
6703  *
6704  * Field Access Macros:
6705  *
6706  */
6707 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HMCINTREN_EN register field. */
6708 #define ALT_RSTMGR_HMCINTREN_EN_LSB 0
6709 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HMCINTREN_EN register field. */
6710 #define ALT_RSTMGR_HMCINTREN_EN_MSB 0
6711 /* The width in bits of the ALT_RSTMGR_HMCINTREN_EN register field. */
6712 #define ALT_RSTMGR_HMCINTREN_EN_WIDTH 1
6713 /* The mask used to set the ALT_RSTMGR_HMCINTREN_EN register field value. */
6714 #define ALT_RSTMGR_HMCINTREN_EN_SET_MSK 0x00000001
6715 /* The mask used to clear the ALT_RSTMGR_HMCINTREN_EN register field value. */
6716 #define ALT_RSTMGR_HMCINTREN_EN_CLR_MSK 0xfffffffe
6717 /* The reset value of the ALT_RSTMGR_HMCINTREN_EN register field. */
6718 #define ALT_RSTMGR_HMCINTREN_EN_RESET 0x0
6719 /* Extracts the ALT_RSTMGR_HMCINTREN_EN field value from a register. */
6720 #define ALT_RSTMGR_HMCINTREN_EN_GET(value) (((value) & 0x00000001) >> 0)
6721 /* Produces a ALT_RSTMGR_HMCINTREN_EN register field value suitable for setting the register. */
6722 #define ALT_RSTMGR_HMCINTREN_EN_SET(value) (((value) << 0) & 0x00000001)
6723 
6724 #ifndef __ASSEMBLY__
6725 /*
6726  * WARNING: The C register and register group struct declarations are provided for
6727  * convenience and illustrative purposes. They should, however, be used with
6728  * caution as the C language standard provides no guarantees about the alignment or
6729  * atomicity of device memory accesses. The recommended practice for writing
6730  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6731  * alt_write_word() functions.
6732  *
6733  * The struct declaration for register ALT_RSTMGR_HMCINTREN.
6734  */
6735 struct ALT_RSTMGR_HMCINTREN_s
6736 {
6737  uint32_t en : 1; /* HMC Interrupt Enable */
6738  uint32_t : 31; /* *UNDEFINED* */
6739 };
6740 
6741 /* The typedef declaration for register ALT_RSTMGR_HMCINTREN. */
6742 typedef volatile struct ALT_RSTMGR_HMCINTREN_s ALT_RSTMGR_HMCINTREN_t;
6743 #endif /* __ASSEMBLY__ */
6744 
6745 /* The reset value of the ALT_RSTMGR_HMCINTREN register. */
6746 #define ALT_RSTMGR_HMCINTREN_RESET 0x00000000
6747 /* The byte offset of the ALT_RSTMGR_HMCINTREN register from the beginning of the component. */
6748 #define ALT_RSTMGR_HMCINTREN_OFST 0x6c
6749 
6750 /*
6751  * Register : HMC Interrupt enable set - hmcintrens
6752  *
6753  * HMC Interrupt Enable Set
6754  *
6755  * Register Layout
6756  *
6757  * Bits | Access | Reset | Description
6758  * :-------|:-------|:------|:----------------------------
6759  * [0] | RW | 0x0 | Interrupt Enable Set Signal
6760  * [31:1] | ??? | 0x0 | *UNDEFINED*
6761  *
6762  */
6763 /*
6764  * Field : Interrupt Enable Set Signal - en
6765  *
6766  * Interrupt Enable Set Signal
6767  *
6768  * Field Access Macros:
6769  *
6770  */
6771 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HMCINTRENS_EN register field. */
6772 #define ALT_RSTMGR_HMCINTRENS_EN_LSB 0
6773 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HMCINTRENS_EN register field. */
6774 #define ALT_RSTMGR_HMCINTRENS_EN_MSB 0
6775 /* The width in bits of the ALT_RSTMGR_HMCINTRENS_EN register field. */
6776 #define ALT_RSTMGR_HMCINTRENS_EN_WIDTH 1
6777 /* The mask used to set the ALT_RSTMGR_HMCINTRENS_EN register field value. */
6778 #define ALT_RSTMGR_HMCINTRENS_EN_SET_MSK 0x00000001
6779 /* The mask used to clear the ALT_RSTMGR_HMCINTRENS_EN register field value. */
6780 #define ALT_RSTMGR_HMCINTRENS_EN_CLR_MSK 0xfffffffe
6781 /* The reset value of the ALT_RSTMGR_HMCINTRENS_EN register field. */
6782 #define ALT_RSTMGR_HMCINTRENS_EN_RESET 0x0
6783 /* Extracts the ALT_RSTMGR_HMCINTRENS_EN field value from a register. */
6784 #define ALT_RSTMGR_HMCINTRENS_EN_GET(value) (((value) & 0x00000001) >> 0)
6785 /* Produces a ALT_RSTMGR_HMCINTRENS_EN register field value suitable for setting the register. */
6786 #define ALT_RSTMGR_HMCINTRENS_EN_SET(value) (((value) << 0) & 0x00000001)
6787 
6788 #ifndef __ASSEMBLY__
6789 /*
6790  * WARNING: The C register and register group struct declarations are provided for
6791  * convenience and illustrative purposes. They should, however, be used with
6792  * caution as the C language standard provides no guarantees about the alignment or
6793  * atomicity of device memory accesses. The recommended practice for writing
6794  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6795  * alt_write_word() functions.
6796  *
6797  * The struct declaration for register ALT_RSTMGR_HMCINTRENS.
6798  */
6799 struct ALT_RSTMGR_HMCINTRENS_s
6800 {
6801  uint32_t en : 1; /* Interrupt Enable Set Signal */
6802  uint32_t : 31; /* *UNDEFINED* */
6803 };
6804 
6805 /* The typedef declaration for register ALT_RSTMGR_HMCINTRENS. */
6806 typedef volatile struct ALT_RSTMGR_HMCINTRENS_s ALT_RSTMGR_HMCINTRENS_t;
6807 #endif /* __ASSEMBLY__ */
6808 
6809 /* The reset value of the ALT_RSTMGR_HMCINTRENS register. */
6810 #define ALT_RSTMGR_HMCINTRENS_RESET 0x00000000
6811 /* The byte offset of the ALT_RSTMGR_HMCINTRENS register from the beginning of the component. */
6812 #define ALT_RSTMGR_HMCINTRENS_OFST 0x70
6813 
6814 /*
6815  * Register : HMC Interrupt Enable Clear - hmcintrenr
6816  *
6817  * HMC Interrupt Enable Clear
6818  *
6819  * Register Layout
6820  *
6821  * Bits | Access | Reset | Description
6822  * :-------|:-------|:------|:---------------------------
6823  * [0] | RW | 0x0 | HMC Interrupt Enable Clear
6824  * [31:1] | ??? | 0x0 | *UNDEFINED*
6825  *
6826  */
6827 /*
6828  * Field : HMC Interrupt Enable Clear - en
6829  *
6830  * HMC Interrupt Enable Clear Signal
6831  *
6832  * Field Access Macros:
6833  *
6834  */
6835 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HMCINTRENR_EN register field. */
6836 #define ALT_RSTMGR_HMCINTRENR_EN_LSB 0
6837 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HMCINTRENR_EN register field. */
6838 #define ALT_RSTMGR_HMCINTRENR_EN_MSB 0
6839 /* The width in bits of the ALT_RSTMGR_HMCINTRENR_EN register field. */
6840 #define ALT_RSTMGR_HMCINTRENR_EN_WIDTH 1
6841 /* The mask used to set the ALT_RSTMGR_HMCINTRENR_EN register field value. */
6842 #define ALT_RSTMGR_HMCINTRENR_EN_SET_MSK 0x00000001
6843 /* The mask used to clear the ALT_RSTMGR_HMCINTRENR_EN register field value. */
6844 #define ALT_RSTMGR_HMCINTRENR_EN_CLR_MSK 0xfffffffe
6845 /* The reset value of the ALT_RSTMGR_HMCINTRENR_EN register field. */
6846 #define ALT_RSTMGR_HMCINTRENR_EN_RESET 0x0
6847 /* Extracts the ALT_RSTMGR_HMCINTRENR_EN field value from a register. */
6848 #define ALT_RSTMGR_HMCINTRENR_EN_GET(value) (((value) & 0x00000001) >> 0)
6849 /* Produces a ALT_RSTMGR_HMCINTRENR_EN register field value suitable for setting the register. */
6850 #define ALT_RSTMGR_HMCINTRENR_EN_SET(value) (((value) << 0) & 0x00000001)
6851 
6852 #ifndef __ASSEMBLY__
6853 /*
6854  * WARNING: The C register and register group struct declarations are provided for
6855  * convenience and illustrative purposes. They should, however, be used with
6856  * caution as the C language standard provides no guarantees about the alignment or
6857  * atomicity of device memory accesses. The recommended practice for writing
6858  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6859  * alt_write_word() functions.
6860  *
6861  * The struct declaration for register ALT_RSTMGR_HMCINTRENR.
6862  */
6863 struct ALT_RSTMGR_HMCINTRENR_s
6864 {
6865  uint32_t en : 1; /* HMC Interrupt Enable Clear */
6866  uint32_t : 31; /* *UNDEFINED* */
6867 };
6868 
6869 /* The typedef declaration for register ALT_RSTMGR_HMCINTRENR. */
6870 typedef volatile struct ALT_RSTMGR_HMCINTRENR_s ALT_RSTMGR_HMCINTRENR_t;
6871 #endif /* __ASSEMBLY__ */
6872 
6873 /* The reset value of the ALT_RSTMGR_HMCINTRENR register. */
6874 #define ALT_RSTMGR_HMCINTRENR_RESET 0x00000000
6875 /* The byte offset of the ALT_RSTMGR_HMCINTRENR register from the beginning of the component. */
6876 #define ALT_RSTMGR_HMCINTRENR_OFST 0x74
6877 
6878 /*
6879  * Register : HMC GPIO Output - hmcgpout
6880  *
6881  * GPIO output for HMC and corresponding interrupt
6882  *
6883  * Register Layout
6884  *
6885  * Bits | Access | Reset | Description
6886  * :-------|:-------|:------|:------------
6887  * [7:0] | RW | 0x0 | out
6888  * [31:8] | ??? | 0x0 | *UNDEFINED*
6889  *
6890  */
6891 /*
6892  * Field : out - out
6893  *
6894  * hmc gpio out
6895  *
6896  * Field Access Macros:
6897  *
6898  */
6899 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HMCGPOUT_OUT register field. */
6900 #define ALT_RSTMGR_HMCGPOUT_OUT_LSB 0
6901 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HMCGPOUT_OUT register field. */
6902 #define ALT_RSTMGR_HMCGPOUT_OUT_MSB 7
6903 /* The width in bits of the ALT_RSTMGR_HMCGPOUT_OUT register field. */
6904 #define ALT_RSTMGR_HMCGPOUT_OUT_WIDTH 8
6905 /* The mask used to set the ALT_RSTMGR_HMCGPOUT_OUT register field value. */
6906 #define ALT_RSTMGR_HMCGPOUT_OUT_SET_MSK 0x000000ff
6907 /* The mask used to clear the ALT_RSTMGR_HMCGPOUT_OUT register field value. */
6908 #define ALT_RSTMGR_HMCGPOUT_OUT_CLR_MSK 0xffffff00
6909 /* The reset value of the ALT_RSTMGR_HMCGPOUT_OUT register field. */
6910 #define ALT_RSTMGR_HMCGPOUT_OUT_RESET 0x0
6911 /* Extracts the ALT_RSTMGR_HMCGPOUT_OUT field value from a register. */
6912 #define ALT_RSTMGR_HMCGPOUT_OUT_GET(value) (((value) & 0x000000ff) >> 0)
6913 /* Produces a ALT_RSTMGR_HMCGPOUT_OUT register field value suitable for setting the register. */
6914 #define ALT_RSTMGR_HMCGPOUT_OUT_SET(value) (((value) << 0) & 0x000000ff)
6915 
6916 #ifndef __ASSEMBLY__
6917 /*
6918  * WARNING: The C register and register group struct declarations are provided for
6919  * convenience and illustrative purposes. They should, however, be used with
6920  * caution as the C language standard provides no guarantees about the alignment or
6921  * atomicity of device memory accesses. The recommended practice for writing
6922  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6923  * alt_write_word() functions.
6924  *
6925  * The struct declaration for register ALT_RSTMGR_HMCGPOUT.
6926  */
6927 struct ALT_RSTMGR_HMCGPOUT_s
6928 {
6929  uint32_t out : 8; /* out */
6930  uint32_t : 24; /* *UNDEFINED* */
6931 };
6932 
6933 /* The typedef declaration for register ALT_RSTMGR_HMCGPOUT. */
6934 typedef volatile struct ALT_RSTMGR_HMCGPOUT_s ALT_RSTMGR_HMCGPOUT_t;
6935 #endif /* __ASSEMBLY__ */
6936 
6937 /* The reset value of the ALT_RSTMGR_HMCGPOUT register. */
6938 #define ALT_RSTMGR_HMCGPOUT_RESET 0x00000000
6939 /* The byte offset of the ALT_RSTMGR_HMCGPOUT register from the beginning of the component. */
6940 #define ALT_RSTMGR_HMCGPOUT_OFST 0x78
6941 
6942 /*
6943  * Register : HMC GPIO Input - hmcgpin
6944  *
6945  * GPIO input for HMC and corresponding interrupt
6946  *
6947  * Register Layout
6948  *
6949  * Bits | Access | Reset | Description
6950  * :-------|:-------|:------|:------------
6951  * [7:0] | R | 0x0 | in
6952  * [31:8] | ??? | 0x0 | *UNDEFINED*
6953  *
6954  */
6955 /*
6956  * Field : in - in
6957  *
6958  * hmc gpio in
6959  *
6960  * Field Access Macros:
6961  *
6962  */
6963 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HMCGPIN_IN register field. */
6964 #define ALT_RSTMGR_HMCGPIN_IN_LSB 0
6965 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HMCGPIN_IN register field. */
6966 #define ALT_RSTMGR_HMCGPIN_IN_MSB 7
6967 /* The width in bits of the ALT_RSTMGR_HMCGPIN_IN register field. */
6968 #define ALT_RSTMGR_HMCGPIN_IN_WIDTH 8
6969 /* The mask used to set the ALT_RSTMGR_HMCGPIN_IN register field value. */
6970 #define ALT_RSTMGR_HMCGPIN_IN_SET_MSK 0x000000ff
6971 /* The mask used to clear the ALT_RSTMGR_HMCGPIN_IN register field value. */
6972 #define ALT_RSTMGR_HMCGPIN_IN_CLR_MSK 0xffffff00
6973 /* The reset value of the ALT_RSTMGR_HMCGPIN_IN register field. */
6974 #define ALT_RSTMGR_HMCGPIN_IN_RESET 0x0
6975 /* Extracts the ALT_RSTMGR_HMCGPIN_IN field value from a register. */
6976 #define ALT_RSTMGR_HMCGPIN_IN_GET(value) (((value) & 0x000000ff) >> 0)
6977 /* Produces a ALT_RSTMGR_HMCGPIN_IN register field value suitable for setting the register. */
6978 #define ALT_RSTMGR_HMCGPIN_IN_SET(value) (((value) << 0) & 0x000000ff)
6979 
6980 #ifndef __ASSEMBLY__
6981 /*
6982  * WARNING: The C register and register group struct declarations are provided for
6983  * convenience and illustrative purposes. They should, however, be used with
6984  * caution as the C language standard provides no guarantees about the alignment or
6985  * atomicity of device memory accesses. The recommended practice for writing
6986  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6987  * alt_write_word() functions.
6988  *
6989  * The struct declaration for register ALT_RSTMGR_HMCGPIN.
6990  */
6991 struct ALT_RSTMGR_HMCGPIN_s
6992 {
6993  const uint32_t in : 8; /* in */
6994  uint32_t : 24; /* *UNDEFINED* */
6995 };
6996 
6997 /* The typedef declaration for register ALT_RSTMGR_HMCGPIN. */
6998 typedef volatile struct ALT_RSTMGR_HMCGPIN_s ALT_RSTMGR_HMCGPIN_t;
6999 #endif /* __ASSEMBLY__ */
7000 
7001 /* The reset value of the ALT_RSTMGR_HMCGPIN register. */
7002 #define ALT_RSTMGR_HMCGPIN_RESET 0x00000000
7003 /* The byte offset of the ALT_RSTMGR_HMCGPIN register from the beginning of the component. */
7004 #define ALT_RSTMGR_HMCGPIN_OFST 0x7c
7005 
7006 #ifndef __ASSEMBLY__
7007 /*
7008  * WARNING: The C register and register group struct declarations are provided for
7009  * convenience and illustrative purposes. They should, however, be used with
7010  * caution as the C language standard provides no guarantees about the alignment or
7011  * atomicity of device memory accesses. The recommended practice for writing
7012  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7013  * alt_write_word() functions.
7014  *
7015  * The struct declaration for register group ALT_RSTMGR.
7016  */
7017 struct ALT_RSTMGR_s
7018 {
7019  ALT_RSTMGR_STAT_t stat; /* ALT_RSTMGR_STAT */
7020  ALT_RSTMGR_RAMSTAT_t ramstat; /* ALT_RSTMGR_RAMSTAT */
7021  ALT_RSTMGR_MISCSTAT_t miscstat; /* ALT_RSTMGR_MISCSTAT */
7022  ALT_RSTMGR_CTL_t ctrl; /* ALT_RSTMGR_CTL */
7023  ALT_RSTMGR_HDSKEN_t hdsken; /* ALT_RSTMGR_HDSKEN */
7024  ALT_RSTMGR_HDSKREQ_t hdskreq; /* ALT_RSTMGR_HDSKREQ */
7025  ALT_RSTMGR_HDSKACK_t hdskack; /* ALT_RSTMGR_HDSKACK */
7026  ALT_RSTMGR_COUNTS_t counts; /* ALT_RSTMGR_COUNTS */
7027  ALT_RSTMGR_MPUMODRST_t mpumodrst; /* ALT_RSTMGR_MPUMODRST */
7028  ALT_RSTMGR_PER0MODRST_t per0modrst; /* ALT_RSTMGR_PER0MODRST */
7029  ALT_RSTMGR_PER1MODRST_t per1modrst; /* ALT_RSTMGR_PER1MODRST */
7030  ALT_RSTMGR_BRGMODRST_t brgmodrst; /* ALT_RSTMGR_BRGMODRST */
7031  ALT_RSTMGR_SYSMODRST_t sysmodrst; /* ALT_RSTMGR_SYSMODRST */
7032  ALT_RSTMGR_COLDMODRST_t coldmodrst; /* ALT_RSTMGR_COLDMODRST */
7033  ALT_RSTMGR_NRSTMODRST_t nrstmodrst; /* ALT_RSTMGR_NRSTMODRST */
7034  ALT_RSTMGR_DBGMODRST_t dbgmodrst; /* ALT_RSTMGR_DBGMODRST */
7035  ALT_RSTMGR_MPUWARMMSK_t mpuwarmmask; /* ALT_RSTMGR_MPUWARMMSK */
7036  ALT_RSTMGR_PER0WARMMSK_t per0warmmask; /* ALT_RSTMGR_PER0WARMMSK */
7037  ALT_RSTMGR_PER1WARMMSK_t per1warmmask; /* ALT_RSTMGR_PER1WARMMSK */
7038  ALT_RSTMGR_BRGWARMMSK_t brgwarmmask; /* ALT_RSTMGR_BRGWARMMSK */
7039  ALT_RSTMGR_SYSWARMMSK_t syswarmmask; /* ALT_RSTMGR_SYSWARMMSK */
7040  ALT_RSTMGR_NRSTWARMMSK_t nrstwarmmask; /* ALT_RSTMGR_NRSTWARMMSK */
7041  ALT_RSTMGR_L3WARMMSK_t l3warmmask; /* ALT_RSTMGR_L3WARMMSK */
7042  ALT_RSTMGR_TSTSTA_t tststa; /* ALT_RSTMGR_TSTSTA */
7043  ALT_RSTMGR_TSTSCRATCH_t tstscratch; /* ALT_RSTMGR_TSTSCRATCH */
7044  ALT_RSTMGR_HDSKTMO_t hdsktimeout; /* ALT_RSTMGR_HDSKTMO */
7045  ALT_RSTMGR_HMCINTR_t hmcintr; /* ALT_RSTMGR_HMCINTR */
7046  ALT_RSTMGR_HMCINTREN_t hmcintren; /* ALT_RSTMGR_HMCINTREN */
7047  ALT_RSTMGR_HMCINTRENS_t hmcintrens; /* ALT_RSTMGR_HMCINTRENS */
7048  ALT_RSTMGR_HMCINTRENR_t hmcintrenr; /* ALT_RSTMGR_HMCINTRENR */
7049  ALT_RSTMGR_HMCGPOUT_t hmcgpout; /* ALT_RSTMGR_HMCGPOUT */
7050  ALT_RSTMGR_HMCGPIN_t hmcgpin; /* ALT_RSTMGR_HMCGPIN */
7051  volatile uint32_t _pad_0x80_0x100[32]; /* *UNDEFINED* */
7052 };
7053 
7054 /* The typedef declaration for register group ALT_RSTMGR. */
7055 typedef volatile struct ALT_RSTMGR_s ALT_RSTMGR_t;
7056 /* The struct declaration for the raw register contents of register group ALT_RSTMGR. */
7057 struct ALT_RSTMGR_raw_s
7058 {
7059  volatile uint32_t stat; /* ALT_RSTMGR_STAT */
7060  volatile uint32_t ramstat; /* ALT_RSTMGR_RAMSTAT */
7061  volatile uint32_t miscstat; /* ALT_RSTMGR_MISCSTAT */
7062  volatile uint32_t ctrl; /* ALT_RSTMGR_CTL */
7063  volatile uint32_t hdsken; /* ALT_RSTMGR_HDSKEN */
7064  volatile uint32_t hdskreq; /* ALT_RSTMGR_HDSKREQ */
7065  volatile uint32_t hdskack; /* ALT_RSTMGR_HDSKACK */
7066  volatile uint32_t counts; /* ALT_RSTMGR_COUNTS */
7067  volatile uint32_t mpumodrst; /* ALT_RSTMGR_MPUMODRST */
7068  volatile uint32_t per0modrst; /* ALT_RSTMGR_PER0MODRST */
7069  volatile uint32_t per1modrst; /* ALT_RSTMGR_PER1MODRST */
7070  volatile uint32_t brgmodrst; /* ALT_RSTMGR_BRGMODRST */
7071  volatile uint32_t sysmodrst; /* ALT_RSTMGR_SYSMODRST */
7072  volatile uint32_t coldmodrst; /* ALT_RSTMGR_COLDMODRST */
7073  volatile uint32_t nrstmodrst; /* ALT_RSTMGR_NRSTMODRST */
7074  volatile uint32_t dbgmodrst; /* ALT_RSTMGR_DBGMODRST */
7075  volatile uint32_t mpuwarmmask; /* ALT_RSTMGR_MPUWARMMSK */
7076  volatile uint32_t per0warmmask; /* ALT_RSTMGR_PER0WARMMSK */
7077  volatile uint32_t per1warmmask; /* ALT_RSTMGR_PER1WARMMSK */
7078  volatile uint32_t brgwarmmask; /* ALT_RSTMGR_BRGWARMMSK */
7079  volatile uint32_t syswarmmask; /* ALT_RSTMGR_SYSWARMMSK */
7080  volatile uint32_t nrstwarmmask; /* ALT_RSTMGR_NRSTWARMMSK */
7081  volatile uint32_t l3warmmask; /* ALT_RSTMGR_L3WARMMSK */
7082  volatile uint32_t tststa; /* ALT_RSTMGR_TSTSTA */
7083  volatile uint32_t tstscratch; /* ALT_RSTMGR_TSTSCRATCH */
7084  volatile uint32_t hdsktimeout; /* ALT_RSTMGR_HDSKTMO */
7085  volatile uint32_t hmcintr; /* ALT_RSTMGR_HMCINTR */
7086  volatile uint32_t hmcintren; /* ALT_RSTMGR_HMCINTREN */
7087  volatile uint32_t hmcintrens; /* ALT_RSTMGR_HMCINTRENS */
7088  volatile uint32_t hmcintrenr; /* ALT_RSTMGR_HMCINTRENR */
7089  volatile uint32_t hmcgpout; /* ALT_RSTMGR_HMCGPOUT */
7090  volatile uint32_t hmcgpin; /* ALT_RSTMGR_HMCGPIN */
7091  uint32_t _pad_0x80_0x100[32]; /* *UNDEFINED* */
7092 };
7093 
7094 /* The typedef declaration for the raw register contents of register group ALT_RSTMGR. */
7095 typedef volatile struct ALT_RSTMGR_raw_s ALT_RSTMGR_raw_t;
7096 #endif /* __ASSEMBLY__ */
7097 
7098 
7099 #ifdef __cplusplus
7100 }
7101 #endif /* __cplusplus */
7102 #endif /* __ALT_SOCAL_RSTMGR_H__ */
7103