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alt_noc_fw_tcu_scr.h
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32 
33 /* Altera - ALT_NOC_FW_TCU_SCR */
34 
35 #ifndef __ALT_SOCAL_NOC_FW_TCU_SCR_H__
36 #define __ALT_SOCAL_NOC_FW_TCU_SCR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : NOC_FW_TCU_SCR
50  * L4_SYS Security Control Registers (SCR)
51  *
52  */
53 /*
54  * Register : tcu
55  *
56  * Per-Master Security bit for dma_ecc
57  *
58  * Register Layout
59  *
60  * Bits | Access | Reset | Description
61  * :--------|:-------|:--------|:--------------------------------
62  * [0] | RW | 0x0 | ALT_NOC_FW_TCU_SCR_TCU_MPU
63  * [15:1] | ??? | Unknown | *UNDEFINED*
64  * [16] | RW | 0x0 | ALT_NOC_FW_TCU_SCR_TCU_FPGA2SOC
65  * [23:17] | ??? | Unknown | *UNDEFINED*
66  * [24] | RW | 0x0 | ALT_NOC_FW_TCU_SCR_TCU_AXI_AP
67  * [31:25] | ??? | Unknown | *UNDEFINED*
68  *
69  */
70 /*
71  * Field : mpu
72  *
73  * Security bit configuration for transactions from mpu to dma_ecc. When cleared
74  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
75  * Secure transactions are allowed.
76  *
77  * Field Access Macros:
78  *
79  */
80 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_TCU_SCR_TCU_MPU register field. */
81 #define ALT_NOC_FW_TCU_SCR_TCU_MPU_LSB 0
82 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_TCU_SCR_TCU_MPU register field. */
83 #define ALT_NOC_FW_TCU_SCR_TCU_MPU_MSB 0
84 /* The width in bits of the ALT_NOC_FW_TCU_SCR_TCU_MPU register field. */
85 #define ALT_NOC_FW_TCU_SCR_TCU_MPU_WIDTH 1
86 /* The mask used to set the ALT_NOC_FW_TCU_SCR_TCU_MPU register field value. */
87 #define ALT_NOC_FW_TCU_SCR_TCU_MPU_SET_MSK 0x00000001
88 /* The mask used to clear the ALT_NOC_FW_TCU_SCR_TCU_MPU register field value. */
89 #define ALT_NOC_FW_TCU_SCR_TCU_MPU_CLR_MSK 0xfffffffe
90 /* The reset value of the ALT_NOC_FW_TCU_SCR_TCU_MPU register field. */
91 #define ALT_NOC_FW_TCU_SCR_TCU_MPU_RESET 0x0
92 /* Extracts the ALT_NOC_FW_TCU_SCR_TCU_MPU field value from a register. */
93 #define ALT_NOC_FW_TCU_SCR_TCU_MPU_GET(value) (((value) & 0x00000001) >> 0)
94 /* Produces a ALT_NOC_FW_TCU_SCR_TCU_MPU register field value suitable for setting the register. */
95 #define ALT_NOC_FW_TCU_SCR_TCU_MPU_SET(value) (((value) << 0) & 0x00000001)
96 
97 /*
98  * Field : fpga2soc
99  *
100  * Security bit configuration for transactions from fpga2soc to dma_ecc. When
101  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
102  * Non-Secure transactions are allowed.
103  *
104  * Field Access Macros:
105  *
106  */
107 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_TCU_SCR_TCU_FPGA2SOC register field. */
108 #define ALT_NOC_FW_TCU_SCR_TCU_FPGA2SOC_LSB 16
109 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_TCU_SCR_TCU_FPGA2SOC register field. */
110 #define ALT_NOC_FW_TCU_SCR_TCU_FPGA2SOC_MSB 16
111 /* The width in bits of the ALT_NOC_FW_TCU_SCR_TCU_FPGA2SOC register field. */
112 #define ALT_NOC_FW_TCU_SCR_TCU_FPGA2SOC_WIDTH 1
113 /* The mask used to set the ALT_NOC_FW_TCU_SCR_TCU_FPGA2SOC register field value. */
114 #define ALT_NOC_FW_TCU_SCR_TCU_FPGA2SOC_SET_MSK 0x00010000
115 /* The mask used to clear the ALT_NOC_FW_TCU_SCR_TCU_FPGA2SOC register field value. */
116 #define ALT_NOC_FW_TCU_SCR_TCU_FPGA2SOC_CLR_MSK 0xfffeffff
117 /* The reset value of the ALT_NOC_FW_TCU_SCR_TCU_FPGA2SOC register field. */
118 #define ALT_NOC_FW_TCU_SCR_TCU_FPGA2SOC_RESET 0x0
119 /* Extracts the ALT_NOC_FW_TCU_SCR_TCU_FPGA2SOC field value from a register. */
120 #define ALT_NOC_FW_TCU_SCR_TCU_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
121 /* Produces a ALT_NOC_FW_TCU_SCR_TCU_FPGA2SOC register field value suitable for setting the register. */
122 #define ALT_NOC_FW_TCU_SCR_TCU_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
123 
124 /*
125  * Field : axi_ap
126  *
127  * Security bit configuration for transactions from axi_ap to dma_ecc. When cleared
128  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
129  * Secure transactions are allowed.
130  *
131  * Field Access Macros:
132  *
133  */
134 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_TCU_SCR_TCU_AXI_AP register field. */
135 #define ALT_NOC_FW_TCU_SCR_TCU_AXI_AP_LSB 24
136 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_TCU_SCR_TCU_AXI_AP register field. */
137 #define ALT_NOC_FW_TCU_SCR_TCU_AXI_AP_MSB 24
138 /* The width in bits of the ALT_NOC_FW_TCU_SCR_TCU_AXI_AP register field. */
139 #define ALT_NOC_FW_TCU_SCR_TCU_AXI_AP_WIDTH 1
140 /* The mask used to set the ALT_NOC_FW_TCU_SCR_TCU_AXI_AP register field value. */
141 #define ALT_NOC_FW_TCU_SCR_TCU_AXI_AP_SET_MSK 0x01000000
142 /* The mask used to clear the ALT_NOC_FW_TCU_SCR_TCU_AXI_AP register field value. */
143 #define ALT_NOC_FW_TCU_SCR_TCU_AXI_AP_CLR_MSK 0xfeffffff
144 /* The reset value of the ALT_NOC_FW_TCU_SCR_TCU_AXI_AP register field. */
145 #define ALT_NOC_FW_TCU_SCR_TCU_AXI_AP_RESET 0x0
146 /* Extracts the ALT_NOC_FW_TCU_SCR_TCU_AXI_AP field value from a register. */
147 #define ALT_NOC_FW_TCU_SCR_TCU_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
148 /* Produces a ALT_NOC_FW_TCU_SCR_TCU_AXI_AP register field value suitable for setting the register. */
149 #define ALT_NOC_FW_TCU_SCR_TCU_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
150 
151 #ifndef __ASSEMBLY__
152 /*
153  * WARNING: The C register and register group struct declarations are provided for
154  * convenience and illustrative purposes. They should, however, be used with
155  * caution as the C language standard provides no guarantees about the alignment or
156  * atomicity of device memory accesses. The recommended practice for coding device
157  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
158  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
159  * alt_write_dword() functions for 64 bit registers.
160  *
161  * The struct declaration for register ALT_NOC_FW_TCU_SCR_TCU.
162  */
163 struct ALT_NOC_FW_TCU_SCR_TCU_s
164 {
165  volatile uint32_t mpu : 1; /* ALT_NOC_FW_TCU_SCR_TCU_MPU */
166  uint32_t : 15; /* *UNDEFINED* */
167  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_TCU_SCR_TCU_FPGA2SOC */
168  uint32_t : 7; /* *UNDEFINED* */
169  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_TCU_SCR_TCU_AXI_AP */
170  uint32_t : 7; /* *UNDEFINED* */
171 };
172 
173 /* The typedef declaration for register ALT_NOC_FW_TCU_SCR_TCU. */
174 typedef struct ALT_NOC_FW_TCU_SCR_TCU_s ALT_NOC_FW_TCU_SCR_TCU_t;
175 #endif /* __ASSEMBLY__ */
176 
177 /* The reset value of the ALT_NOC_FW_TCU_SCR_TCU register. */
178 #define ALT_NOC_FW_TCU_SCR_TCU_RESET 0x00000000
179 /* The byte offset of the ALT_NOC_FW_TCU_SCR_TCU register from the beginning of the component. */
180 #define ALT_NOC_FW_TCU_SCR_TCU_OFST 0x0
181 
182 #ifndef __ASSEMBLY__
183 /*
184  * WARNING: The C register and register group struct declarations are provided for
185  * convenience and illustrative purposes. They should, however, be used with
186  * caution as the C language standard provides no guarantees about the alignment or
187  * atomicity of device memory accesses. The recommended practice for coding device
188  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
189  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
190  * alt_write_dword() functions for 64 bit registers.
191  *
192  * The struct declaration for register group ALT_NOC_FW_TCU_SCR.
193  */
194 struct ALT_NOC_FW_TCU_SCR_s
195 {
196  volatile ALT_NOC_FW_TCU_SCR_TCU_t tcu; /* ALT_NOC_FW_TCU_SCR_TCU */
197  volatile uint32_t _pad_0x4_0x100[63]; /* *UNDEFINED* */
198 };
199 
200 /* The typedef declaration for register group ALT_NOC_FW_TCU_SCR. */
201 typedef struct ALT_NOC_FW_TCU_SCR_s ALT_NOC_FW_TCU_SCR_t;
202 /* The struct declaration for the raw register contents of register group ALT_NOC_FW_TCU_SCR. */
203 struct ALT_NOC_FW_TCU_SCR_raw_s
204 {
205  volatile uint32_t tcu; /* ALT_NOC_FW_TCU_SCR_TCU */
206  volatile uint32_t _pad_0x4_0x100[63]; /* *UNDEFINED* */
207 };
208 
209 /* The typedef declaration for the raw register contents of register group ALT_NOC_FW_TCU_SCR. */
210 typedef struct ALT_NOC_FW_TCU_SCR_raw_s ALT_NOC_FW_TCU_SCR_raw_t;
211 #endif /* __ASSEMBLY__ */
212 
213 
214 #ifdef __cplusplus
215 }
216 #endif /* __cplusplus */
217 #endif /* __ALT_SOCAL_NOC_FW_TCU_SCR_H__ */
218