Altera SoCAL  20.1
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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alt_gpio.h
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32 
33 /* Altera - ALT_GPIO */
34 
35 #ifndef __ALTERA_ALT_GPIO_H__
36 #define __ALTERA_ALT_GPIO_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
43 /*
44  * Component : GPIO Module - ALT_GPIO
45  * GPIO Module
46  *
47  * Registers in the GPIO module
48  *
49  */
50 /*
51  * Register : Port A Data Register - gpio_swporta_dr
52  *
53  * This GPIO Data register is used to input or output data
54  *
55  * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented.
56  *
57  * Register Layout
58  *
59  * Bits | Access | Reset | Description
60  * :--------|:-------|:------|:------------
61  * [28:0] | RW | 0x0 | Port A Data
62  * [31:29] | ??? | 0x0 | *UNDEFINED*
63  *
64  */
65 /*
66  * Field : Port A Data - gpio_swporta_dr
67  *
68  * Values written to this register are output on the I/O signals of the GPIO Data
69  * Register, if the corresponding data direction bits for GPIO Data Direction Field
70  * are set to Output mode. The value read back is equal to the last value written
71  * to this register.
72  *
73  * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented.
74  *
75  * Field Access Macros:
76  *
77  */
78 /* The Least Significant Bit (LSB) position of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
79 #define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_LSB 0
80 /* The Most Significant Bit (MSB) position of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
81 #define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_MSB 28
82 /* The width in bits of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
83 #define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_WIDTH 29
84 /* The mask used to set the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value. */
85 #define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_SET_MSK 0x1fffffff
86 /* The mask used to clear the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value. */
87 #define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_CLR_MSK 0xe0000000
88 /* The reset value of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
89 #define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_RESET 0x0
90 /* Extracts the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR field value from a register. */
91 #define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_GET(value) (((value) & 0x1fffffff) >> 0)
92 /* Produces a ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value suitable for setting the register. */
93 #define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_SET(value) (((value) << 0) & 0x1fffffff)
94 
95 #ifndef __ASSEMBLY__
96 /*
97  * WARNING: The C register and register group struct declarations are provided for
98  * convenience and illustrative purposes. They should, however, be used with
99  * caution as the C language standard provides no guarantees about the alignment or
100  * atomicity of device memory accesses. The recommended practice for writing
101  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
102  * alt_write_word() functions.
103  *
104  * The struct declaration for register ALT_GPIO_SWPORTA_DR.
105  */
106 struct ALT_GPIO_SWPORTA_DR_s
107 {
108  uint32_t gpio_swporta_dr : 29; /* Port A Data */
109  uint32_t : 3; /* *UNDEFINED* */
110 };
111 
112 /* The typedef declaration for register ALT_GPIO_SWPORTA_DR. */
113 typedef volatile struct ALT_GPIO_SWPORTA_DR_s ALT_GPIO_SWPORTA_DR_t;
114 #endif /* __ASSEMBLY__ */
115 
116 /* The byte offset of the ALT_GPIO_SWPORTA_DR register from the beginning of the component. */
117 #define ALT_GPIO_SWPORTA_DR_OFST 0x0
118 /* The address of the ALT_GPIO_SWPORTA_DR register. */
119 #define ALT_GPIO_SWPORTA_DR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_SWPORTA_DR_OFST))
120 
121 /*
122  * Register : Port A Data Direction Register - gpio_swporta_ddr
123  *
124  * This register establishes the direction of each corresponding GPIO Data Field
125  * Bit.
126  *
127  * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented.
128  *
129  * Register Layout
130  *
131  * Bits | Access | Reset | Description
132  * :--------|:-------|:------|:----------------------------
133  * [28:0] | RW | 0x0 | Port A Data Direction Field
134  * [31:29] | ??? | 0x0 | *UNDEFINED*
135  *
136  */
137 /*
138  * Field : Port A Data Direction Field - gpio_swporta_ddr
139  *
140  * Values written to this register independently control the direction of the
141  * corresponding data bit in the Port A Data Register.
142  *
143  * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented.
144  *
145  * Field Enumeration Values:
146  *
147  * Enum | Value | Description
148  * :--------------------------------------------|:------|:-----------------
149  * ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_IN | 0x0 | Input Direction
150  * ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_OUT | 0x1 | Output Direction
151  *
152  * Field Access Macros:
153  *
154  */
155 /*
156  * Enumerated value for register field ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR
157  *
158  * Input Direction
159  */
160 #define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_IN 0x0
161 /*
162  * Enumerated value for register field ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR
163  *
164  * Output Direction
165  */
166 #define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_OUT 0x1
167 
168 /* The Least Significant Bit (LSB) position of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */
169 #define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_LSB 0
170 /* The Most Significant Bit (MSB) position of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */
171 #define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_MSB 28
172 /* The width in bits of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */
173 #define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_WIDTH 29
174 /* The mask used to set the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value. */
175 #define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_SET_MSK 0x1fffffff
176 /* The mask used to clear the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value. */
177 #define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_CLR_MSK 0xe0000000
178 /* The reset value of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */
179 #define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_RESET 0x0
180 /* Extracts the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR field value from a register. */
181 #define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_GET(value) (((value) & 0x1fffffff) >> 0)
182 /* Produces a ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value suitable for setting the register. */
183 #define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_SET(value) (((value) << 0) & 0x1fffffff)
184 
185 #ifndef __ASSEMBLY__
186 /*
187  * WARNING: The C register and register group struct declarations are provided for
188  * convenience and illustrative purposes. They should, however, be used with
189  * caution as the C language standard provides no guarantees about the alignment or
190  * atomicity of device memory accesses. The recommended practice for writing
191  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
192  * alt_write_word() functions.
193  *
194  * The struct declaration for register ALT_GPIO_SWPORTA_DDR.
195  */
196 struct ALT_GPIO_SWPORTA_DDR_s
197 {
198  uint32_t gpio_swporta_ddr : 29; /* Port A Data Direction Field */
199  uint32_t : 3; /* *UNDEFINED* */
200 };
201 
202 /* The typedef declaration for register ALT_GPIO_SWPORTA_DDR. */
203 typedef volatile struct ALT_GPIO_SWPORTA_DDR_s ALT_GPIO_SWPORTA_DDR_t;
204 #endif /* __ASSEMBLY__ */
205 
206 /* The byte offset of the ALT_GPIO_SWPORTA_DDR register from the beginning of the component. */
207 #define ALT_GPIO_SWPORTA_DDR_OFST 0x4
208 /* The address of the ALT_GPIO_SWPORTA_DDR register. */
209 #define ALT_GPIO_SWPORTA_DDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_SWPORTA_DDR_OFST))
210 
211 /*
212  * Register : Interrupt Enable Register - gpio_inten
213  *
214  * The Interrupt enable register allows interrupts for each bit of the Port A data
215  * register.
216  *
217  * Register Layout
218  *
219  * Bits | Access | Reset | Description
220  * :--------|:-------|:------|:-----------------------
221  * [28:0] | RW | 0x0 | Interrupt Enable Field
222  * [31:29] | ??? | 0x0 | *UNDEFINED*
223  *
224  */
225 /*
226  * Field : Interrupt Enable Field - gpio_inten
227  *
228  * Allows each bit of Port A Data Register to be configured for interrupt
229  * capability. Interrupts are disabled on the corresponding bits of Port A Data
230  * Register if the corresponding data direction register is set to Output.
231  *
232  * Field Enumeration Values:
233  *
234  * Enum | Value | Description
235  * :--------------------------------|:------|:----------------------------
236  * ALT_GPIO_INTEN_GPIO_INTEN_E_DIS | 0x0 | Disable Interrupt on Port A
237  * ALT_GPIO_INTEN_GPIO_INTEN_E_EN | 0x1 | Enable Interrupt on Port A
238  *
239  * Field Access Macros:
240  *
241  */
242 /*
243  * Enumerated value for register field ALT_GPIO_INTEN_GPIO_INTEN
244  *
245  * Disable Interrupt on Port A
246  */
247 #define ALT_GPIO_INTEN_GPIO_INTEN_E_DIS 0x0
248 /*
249  * Enumerated value for register field ALT_GPIO_INTEN_GPIO_INTEN
250  *
251  * Enable Interrupt on Port A
252  */
253 #define ALT_GPIO_INTEN_GPIO_INTEN_E_EN 0x1
254 
255 /* The Least Significant Bit (LSB) position of the ALT_GPIO_INTEN_GPIO_INTEN register field. */
256 #define ALT_GPIO_INTEN_GPIO_INTEN_LSB 0
257 /* The Most Significant Bit (MSB) position of the ALT_GPIO_INTEN_GPIO_INTEN register field. */
258 #define ALT_GPIO_INTEN_GPIO_INTEN_MSB 28
259 /* The width in bits of the ALT_GPIO_INTEN_GPIO_INTEN register field. */
260 #define ALT_GPIO_INTEN_GPIO_INTEN_WIDTH 29
261 /* The mask used to set the ALT_GPIO_INTEN_GPIO_INTEN register field value. */
262 #define ALT_GPIO_INTEN_GPIO_INTEN_SET_MSK 0x1fffffff
263 /* The mask used to clear the ALT_GPIO_INTEN_GPIO_INTEN register field value. */
264 #define ALT_GPIO_INTEN_GPIO_INTEN_CLR_MSK 0xe0000000
265 /* The reset value of the ALT_GPIO_INTEN_GPIO_INTEN register field. */
266 #define ALT_GPIO_INTEN_GPIO_INTEN_RESET 0x0
267 /* Extracts the ALT_GPIO_INTEN_GPIO_INTEN field value from a register. */
268 #define ALT_GPIO_INTEN_GPIO_INTEN_GET(value) (((value) & 0x1fffffff) >> 0)
269 /* Produces a ALT_GPIO_INTEN_GPIO_INTEN register field value suitable for setting the register. */
270 #define ALT_GPIO_INTEN_GPIO_INTEN_SET(value) (((value) << 0) & 0x1fffffff)
271 
272 #ifndef __ASSEMBLY__
273 /*
274  * WARNING: The C register and register group struct declarations are provided for
275  * convenience and illustrative purposes. They should, however, be used with
276  * caution as the C language standard provides no guarantees about the alignment or
277  * atomicity of device memory accesses. The recommended practice for writing
278  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
279  * alt_write_word() functions.
280  *
281  * The struct declaration for register ALT_GPIO_INTEN.
282  */
283 struct ALT_GPIO_INTEN_s
284 {
285  uint32_t gpio_inten : 29; /* Interrupt Enable Field */
286  uint32_t : 3; /* *UNDEFINED* */
287 };
288 
289 /* The typedef declaration for register ALT_GPIO_INTEN. */
290 typedef volatile struct ALT_GPIO_INTEN_s ALT_GPIO_INTEN_t;
291 #endif /* __ASSEMBLY__ */
292 
293 /* The byte offset of the ALT_GPIO_INTEN register from the beginning of the component. */
294 #define ALT_GPIO_INTEN_OFST 0x30
295 /* The address of the ALT_GPIO_INTEN register. */
296 #define ALT_GPIO_INTEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTEN_OFST))
297 
298 /*
299  * Register : Interrupt Mask Register - gpio_intmask
300  *
301  * Controls which pins cause interrupts on Port A Data Register inputs.
302  *
303  * Register Layout
304  *
305  * Bits | Access | Reset | Description
306  * :--------|:-------|:------|:---------------------
307  * [28:0] | RW | 0x0 | Interrupt Mask Field
308  * [31:29] | ??? | 0x0 | *UNDEFINED*
309  *
310  */
311 /*
312  * Field : Interrupt Mask Field - gpio_intmask
313  *
314  * Controls whether an interrupt on Port A Data Register can generate an interrupt
315  * to the interrupt controller by not masking it. The unmasked status can be read
316  * as well as the resultant status after masking.
317  *
318  * Field Enumeration Values:
319  *
320  * Enum | Value | Description
321  * :----------------------------------|:------|:----------------------------
322  * ALT_GPIO_INTMSK_GPIO_INTMSK_E_DIS | 0x0 | Interrupt bits are unmasked
323  * ALT_GPIO_INTMSK_GPIO_INTMSK_E_EN | 0x1 | Mask Interrupt
324  *
325  * Field Access Macros:
326  *
327  */
328 /*
329  * Enumerated value for register field ALT_GPIO_INTMSK_GPIO_INTMSK
330  *
331  * Interrupt bits are unmasked
332  */
333 #define ALT_GPIO_INTMSK_GPIO_INTMSK_E_DIS 0x0
334 /*
335  * Enumerated value for register field ALT_GPIO_INTMSK_GPIO_INTMSK
336  *
337  * Mask Interrupt
338  */
339 #define ALT_GPIO_INTMSK_GPIO_INTMSK_E_EN 0x1
340 
341 /* The Least Significant Bit (LSB) position of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */
342 #define ALT_GPIO_INTMSK_GPIO_INTMSK_LSB 0
343 /* The Most Significant Bit (MSB) position of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */
344 #define ALT_GPIO_INTMSK_GPIO_INTMSK_MSB 28
345 /* The width in bits of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */
346 #define ALT_GPIO_INTMSK_GPIO_INTMSK_WIDTH 29
347 /* The mask used to set the ALT_GPIO_INTMSK_GPIO_INTMSK register field value. */
348 #define ALT_GPIO_INTMSK_GPIO_INTMSK_SET_MSK 0x1fffffff
349 /* The mask used to clear the ALT_GPIO_INTMSK_GPIO_INTMSK register field value. */
350 #define ALT_GPIO_INTMSK_GPIO_INTMSK_CLR_MSK 0xe0000000
351 /* The reset value of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */
352 #define ALT_GPIO_INTMSK_GPIO_INTMSK_RESET 0x0
353 /* Extracts the ALT_GPIO_INTMSK_GPIO_INTMSK field value from a register. */
354 #define ALT_GPIO_INTMSK_GPIO_INTMSK_GET(value) (((value) & 0x1fffffff) >> 0)
355 /* Produces a ALT_GPIO_INTMSK_GPIO_INTMSK register field value suitable for setting the register. */
356 #define ALT_GPIO_INTMSK_GPIO_INTMSK_SET(value) (((value) << 0) & 0x1fffffff)
357 
358 #ifndef __ASSEMBLY__
359 /*
360  * WARNING: The C register and register group struct declarations are provided for
361  * convenience and illustrative purposes. They should, however, be used with
362  * caution as the C language standard provides no guarantees about the alignment or
363  * atomicity of device memory accesses. The recommended practice for writing
364  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
365  * alt_write_word() functions.
366  *
367  * The struct declaration for register ALT_GPIO_INTMSK.
368  */
369 struct ALT_GPIO_INTMSK_s
370 {
371  uint32_t gpio_intmask : 29; /* Interrupt Mask Field */
372  uint32_t : 3; /* *UNDEFINED* */
373 };
374 
375 /* The typedef declaration for register ALT_GPIO_INTMSK. */
376 typedef volatile struct ALT_GPIO_INTMSK_s ALT_GPIO_INTMSK_t;
377 #endif /* __ASSEMBLY__ */
378 
379 /* The byte offset of the ALT_GPIO_INTMSK register from the beginning of the component. */
380 #define ALT_GPIO_INTMSK_OFST 0x34
381 /* The address of the ALT_GPIO_INTMSK register. */
382 #define ALT_GPIO_INTMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTMSK_OFST))
383 
384 /*
385  * Register : Interrupt Level Register - gpio_inttype_level
386  *
387  * The interrupt level register defines the type of interrupt (edge or level).
388  *
389  * Register Layout
390  *
391  * Bits | Access | Reset | Description
392  * :--------|:-------|:------|:----------------------
393  * [28:0] | RW | 0x0 | Interrupt Level Field
394  * [31:29] | ??? | 0x0 | *UNDEFINED*
395  *
396  */
397 /*
398  * Field : Interrupt Level Field - gpio_inttype_level
399  *
400  * This field controls the type of interrupt that can occur on the Port A Data
401  * Register.
402  *
403  * Field Enumeration Values:
404  *
405  * Enum | Value | Description
406  * :--------------------------------------------------|:------|:----------------
407  * ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_LEVEL | 0x0 | Level-sensitive
408  * ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_EDGE | 0x1 | Edge-sensitive
409  *
410  * Field Access Macros:
411  *
412  */
413 /*
414  * Enumerated value for register field ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL
415  *
416  * Level-sensitive
417  */
418 #define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_LEVEL 0x0
419 /*
420  * Enumerated value for register field ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL
421  *
422  * Edge-sensitive
423  */
424 #define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_EDGE 0x1
425 
426 /* The Least Significant Bit (LSB) position of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
427 #define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_LSB 0
428 /* The Most Significant Bit (MSB) position of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
429 #define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_MSB 28
430 /* The width in bits of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
431 #define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_WIDTH 29
432 /* The mask used to set the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value. */
433 #define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_SET_MSK 0x1fffffff
434 /* The mask used to clear the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value. */
435 #define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_CLR_MSK 0xe0000000
436 /* The reset value of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
437 #define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_RESET 0x0
438 /* Extracts the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL field value from a register. */
439 #define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_GET(value) (((value) & 0x1fffffff) >> 0)
440 /* Produces a ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value suitable for setting the register. */
441 #define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_SET(value) (((value) << 0) & 0x1fffffff)
442 
443 #ifndef __ASSEMBLY__
444 /*
445  * WARNING: The C register and register group struct declarations are provided for
446  * convenience and illustrative purposes. They should, however, be used with
447  * caution as the C language standard provides no guarantees about the alignment or
448  * atomicity of device memory accesses. The recommended practice for writing
449  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
450  * alt_write_word() functions.
451  *
452  * The struct declaration for register ALT_GPIO_INTTYPE_LEVEL.
453  */
454 struct ALT_GPIO_INTTYPE_LEVEL_s
455 {
456  uint32_t gpio_inttype_level : 29; /* Interrupt Level Field */
457  uint32_t : 3; /* *UNDEFINED* */
458 };
459 
460 /* The typedef declaration for register ALT_GPIO_INTTYPE_LEVEL. */
461 typedef volatile struct ALT_GPIO_INTTYPE_LEVEL_s ALT_GPIO_INTTYPE_LEVEL_t;
462 #endif /* __ASSEMBLY__ */
463 
464 /* The byte offset of the ALT_GPIO_INTTYPE_LEVEL register from the beginning of the component. */
465 #define ALT_GPIO_INTTYPE_LEVEL_OFST 0x38
466 /* The address of the ALT_GPIO_INTTYPE_LEVEL register. */
467 #define ALT_GPIO_INTTYPE_LEVEL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTTYPE_LEVEL_OFST))
468 
469 /*
470  * Register : Interrupt Polarity Register - gpio_int_polarity
471  *
472  * Controls the Polarity of Interrupts that can occur on inputs of Port A Data
473  * Register
474  *
475  * Register Layout
476  *
477  * Bits | Access | Reset | Description
478  * :--------|:-------|:------|:-----------------------
479  * [28:0] | RW | 0x0 | Polarity Control Field
480  * [31:29] | ??? | 0x0 | *UNDEFINED*
481  *
482  */
483 /*
484  * Field : Polarity Control Field - gpio_int_polarity
485  *
486  * Controls the polarity of edge or level sensitivity that can occur on input of
487  * Port A Data Register.
488  *
489  * Field Enumeration Values:
490  *
491  * Enum | Value | Description
492  * :----------------------------------------|:------|:------------
493  * ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTLOW | 0x0 | Active low
494  * ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTHIGH | 0x1 | Active high
495  *
496  * Field Access Macros:
497  *
498  */
499 /*
500  * Enumerated value for register field ALT_GPIO_INT_POL_GPIO_INT_POL
501  *
502  * Active low
503  */
504 #define ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTLOW 0x0
505 /*
506  * Enumerated value for register field ALT_GPIO_INT_POL_GPIO_INT_POL
507  *
508  * Active high
509  */
510 #define ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTHIGH 0x1
511 
512 /* The Least Significant Bit (LSB) position of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */
513 #define ALT_GPIO_INT_POL_GPIO_INT_POL_LSB 0
514 /* The Most Significant Bit (MSB) position of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */
515 #define ALT_GPIO_INT_POL_GPIO_INT_POL_MSB 28
516 /* The width in bits of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */
517 #define ALT_GPIO_INT_POL_GPIO_INT_POL_WIDTH 29
518 /* The mask used to set the ALT_GPIO_INT_POL_GPIO_INT_POL register field value. */
519 #define ALT_GPIO_INT_POL_GPIO_INT_POL_SET_MSK 0x1fffffff
520 /* The mask used to clear the ALT_GPIO_INT_POL_GPIO_INT_POL register field value. */
521 #define ALT_GPIO_INT_POL_GPIO_INT_POL_CLR_MSK 0xe0000000
522 /* The reset value of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */
523 #define ALT_GPIO_INT_POL_GPIO_INT_POL_RESET 0x0
524 /* Extracts the ALT_GPIO_INT_POL_GPIO_INT_POL field value from a register. */
525 #define ALT_GPIO_INT_POL_GPIO_INT_POL_GET(value) (((value) & 0x1fffffff) >> 0)
526 /* Produces a ALT_GPIO_INT_POL_GPIO_INT_POL register field value suitable for setting the register. */
527 #define ALT_GPIO_INT_POL_GPIO_INT_POL_SET(value) (((value) << 0) & 0x1fffffff)
528 
529 #ifndef __ASSEMBLY__
530 /*
531  * WARNING: The C register and register group struct declarations are provided for
532  * convenience and illustrative purposes. They should, however, be used with
533  * caution as the C language standard provides no guarantees about the alignment or
534  * atomicity of device memory accesses. The recommended practice for writing
535  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
536  * alt_write_word() functions.
537  *
538  * The struct declaration for register ALT_GPIO_INT_POL.
539  */
540 struct ALT_GPIO_INT_POL_s
541 {
542  uint32_t gpio_int_polarity : 29; /* Polarity Control Field */
543  uint32_t : 3; /* *UNDEFINED* */
544 };
545 
546 /* The typedef declaration for register ALT_GPIO_INT_POL. */
547 typedef volatile struct ALT_GPIO_INT_POL_s ALT_GPIO_INT_POL_t;
548 #endif /* __ASSEMBLY__ */
549 
550 /* The byte offset of the ALT_GPIO_INT_POL register from the beginning of the component. */
551 #define ALT_GPIO_INT_POL_OFST 0x3c
552 /* The address of the ALT_GPIO_INT_POL register. */
553 #define ALT_GPIO_INT_POL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INT_POL_OFST))
554 
555 /*
556  * Register : Interrupt Status Register - gpio_intstatus
557  *
558  * The Interrupt status is reported for all Port A Data Register Bits.
559  *
560  * Register Layout
561  *
562  * Bits | Access | Reset | Description
563  * :--------|:-------|:------|:-----------------------
564  * [28:0] | RW | 0x0 | Interrupt Status Field
565  * [31:29] | ??? | 0x0 | *UNDEFINED*
566  *
567  */
568 /*
569  * Field : Interrupt Status Field - gpio_intstatus
570  *
571  * Interrupt status of Port A Data Register.
572  *
573  * Field Enumeration Values:
574  *
575  * Enum | Value | Description
576  * :--------------------------------------|:------|:------------
577  * ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_INACT | 0x0 | Inactive
578  * ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_ACT | 0x1 | Active
579  *
580  * Field Access Macros:
581  *
582  */
583 /*
584  * Enumerated value for register field ALT_GPIO_INTSTAT_GPIO_INTSTAT
585  *
586  * Inactive
587  */
588 #define ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_INACT 0x0
589 /*
590  * Enumerated value for register field ALT_GPIO_INTSTAT_GPIO_INTSTAT
591  *
592  * Active
593  */
594 #define ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_ACT 0x1
595 
596 /* The Least Significant Bit (LSB) position of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */
597 #define ALT_GPIO_INTSTAT_GPIO_INTSTAT_LSB 0
598 /* The Most Significant Bit (MSB) position of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */
599 #define ALT_GPIO_INTSTAT_GPIO_INTSTAT_MSB 28
600 /* The width in bits of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */
601 #define ALT_GPIO_INTSTAT_GPIO_INTSTAT_WIDTH 29
602 /* The mask used to set the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value. */
603 #define ALT_GPIO_INTSTAT_GPIO_INTSTAT_SET_MSK 0x1fffffff
604 /* The mask used to clear the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value. */
605 #define ALT_GPIO_INTSTAT_GPIO_INTSTAT_CLR_MSK 0xe0000000
606 /* The reset value of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */
607 #define ALT_GPIO_INTSTAT_GPIO_INTSTAT_RESET 0x0
608 /* Extracts the ALT_GPIO_INTSTAT_GPIO_INTSTAT field value from a register. */
609 #define ALT_GPIO_INTSTAT_GPIO_INTSTAT_GET(value) (((value) & 0x1fffffff) >> 0)
610 /* Produces a ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value suitable for setting the register. */
611 #define ALT_GPIO_INTSTAT_GPIO_INTSTAT_SET(value) (((value) << 0) & 0x1fffffff)
612 
613 #ifndef __ASSEMBLY__
614 /*
615  * WARNING: The C register and register group struct declarations are provided for
616  * convenience and illustrative purposes. They should, however, be used with
617  * caution as the C language standard provides no guarantees about the alignment or
618  * atomicity of device memory accesses. The recommended practice for writing
619  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
620  * alt_write_word() functions.
621  *
622  * The struct declaration for register ALT_GPIO_INTSTAT.
623  */
624 struct ALT_GPIO_INTSTAT_s
625 {
626  uint32_t gpio_intstatus : 29; /* Interrupt Status Field */
627  uint32_t : 3; /* *UNDEFINED* */
628 };
629 
630 /* The typedef declaration for register ALT_GPIO_INTSTAT. */
631 typedef volatile struct ALT_GPIO_INTSTAT_s ALT_GPIO_INTSTAT_t;
632 #endif /* __ASSEMBLY__ */
633 
634 /* The byte offset of the ALT_GPIO_INTSTAT register from the beginning of the component. */
635 #define ALT_GPIO_INTSTAT_OFST 0x40
636 /* The address of the ALT_GPIO_INTSTAT register. */
637 #define ALT_GPIO_INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTSTAT_OFST))
638 
639 /*
640  * Register : Raw Interrupt Status Register - gpio_raw_intstatus
641  *
642  * This is the Raw Interrupt Status Register for Port A Data Register. It is used
643  * with the Interrupt Mask Register to allow interrupts from the Port A Data
644  * Register.
645  *
646  * Register Layout
647  *
648  * Bits | Access | Reset | Description
649  * :--------|:-------|:------|:---------------------------
650  * [28:0] | RW | 0x0 | Raw Interrupt Status Field
651  * [31:29] | ??? | 0x0 | *UNDEFINED*
652  *
653  */
654 /*
655  * Field : Raw Interrupt Status Field - gpio_raw_intstatus
656  *
657  * Raw interrupt of status of Port A Data Register (premasking bits)
658  *
659  * Field Enumeration Values:
660  *
661  * Enum | Value | Description
662  * :----------------------------------------------|:------|:------------
663  * ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_INACT | 0x0 | Inactive
664  * ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_ACT | 0x1 | Active
665  *
666  * Field Access Macros:
667  *
668  */
669 /*
670  * Enumerated value for register field ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT
671  *
672  * Inactive
673  */
674 #define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_INACT 0x0
675 /*
676  * Enumerated value for register field ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT
677  *
678  * Active
679  */
680 #define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_ACT 0x1
681 
682 /* The Least Significant Bit (LSB) position of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */
683 #define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_LSB 0
684 /* The Most Significant Bit (MSB) position of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */
685 #define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_MSB 28
686 /* The width in bits of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */
687 #define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_WIDTH 29
688 /* The mask used to set the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value. */
689 #define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_SET_MSK 0x1fffffff
690 /* The mask used to clear the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value. */
691 #define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_CLR_MSK 0xe0000000
692 /* The reset value of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */
693 #define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_RESET 0x0
694 /* Extracts the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT field value from a register. */
695 #define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_GET(value) (((value) & 0x1fffffff) >> 0)
696 /* Produces a ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value suitable for setting the register. */
697 #define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_SET(value) (((value) << 0) & 0x1fffffff)
698 
699 #ifndef __ASSEMBLY__
700 /*
701  * WARNING: The C register and register group struct declarations are provided for
702  * convenience and illustrative purposes. They should, however, be used with
703  * caution as the C language standard provides no guarantees about the alignment or
704  * atomicity of device memory accesses. The recommended practice for writing
705  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
706  * alt_write_word() functions.
707  *
708  * The struct declaration for register ALT_GPIO_RAW_INTSTAT.
709  */
710 struct ALT_GPIO_RAW_INTSTAT_s
711 {
712  uint32_t gpio_raw_intstatus : 29; /* Raw Interrupt Status Field */
713  uint32_t : 3; /* *UNDEFINED* */
714 };
715 
716 /* The typedef declaration for register ALT_GPIO_RAW_INTSTAT. */
717 typedef volatile struct ALT_GPIO_RAW_INTSTAT_s ALT_GPIO_RAW_INTSTAT_t;
718 #endif /* __ASSEMBLY__ */
719 
720 /* The byte offset of the ALT_GPIO_RAW_INTSTAT register from the beginning of the component. */
721 #define ALT_GPIO_RAW_INTSTAT_OFST 0x44
722 /* The address of the ALT_GPIO_RAW_INTSTAT register. */
723 #define ALT_GPIO_RAW_INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_RAW_INTSTAT_OFST))
724 
725 /*
726  * Register : Debounce Enable Register - gpio_debounce
727  *
728  * Debounces each IO Pin
729  *
730  * Register Layout
731  *
732  * Bits | Access | Reset | Description
733  * :--------|:-------|:------|:--------------------------------
734  * [28:0] | RW | 0x0 | ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE
735  * [31:29] | ??? | 0x0 | *UNDEFINED*
736  *
737  */
738 /*
739  * Field : gpio_debounce
740  *
741  * Controls whether an external signal that is the source of an interrupt needs to
742  * be debounced to remove any spurious glitches. A signal must be valid for two
743  * periods of an external clock (gpio_db_clk) before it is internally processed.
744  *
745  * Field Enumeration Values:
746  *
747  * Enum | Value | Description
748  * :--------------------------------------|:------|:----------------
749  * ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_DIS | 0x0 | No debounce
750  * ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_EN | 0x1 | Enable debounce
751  *
752  * Field Access Macros:
753  *
754  */
755 /*
756  * Enumerated value for register field ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE
757  *
758  * No debounce
759  */
760 #define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_DIS 0x0
761 /*
762  * Enumerated value for register field ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE
763  *
764  * Enable debounce
765  */
766 #define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_EN 0x1
767 
768 /* The Least Significant Bit (LSB) position of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
769 #define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_LSB 0
770 /* The Most Significant Bit (MSB) position of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
771 #define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_MSB 28
772 /* The width in bits of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
773 #define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_WIDTH 29
774 /* The mask used to set the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value. */
775 #define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_SET_MSK 0x1fffffff
776 /* The mask used to clear the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value. */
777 #define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_CLR_MSK 0xe0000000
778 /* The reset value of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
779 #define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_RESET 0x0
780 /* Extracts the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE field value from a register. */
781 #define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_GET(value) (((value) & 0x1fffffff) >> 0)
782 /* Produces a ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value suitable for setting the register. */
783 #define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_SET(value) (((value) << 0) & 0x1fffffff)
784 
785 #ifndef __ASSEMBLY__
786 /*
787  * WARNING: The C register and register group struct declarations are provided for
788  * convenience and illustrative purposes. They should, however, be used with
789  * caution as the C language standard provides no guarantees about the alignment or
790  * atomicity of device memory accesses. The recommended practice for writing
791  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
792  * alt_write_word() functions.
793  *
794  * The struct declaration for register ALT_GPIO_DEBOUNCE.
795  */
796 struct ALT_GPIO_DEBOUNCE_s
797 {
798  uint32_t gpio_debounce : 29; /* ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE */
799  uint32_t : 3; /* *UNDEFINED* */
800 };
801 
802 /* The typedef declaration for register ALT_GPIO_DEBOUNCE. */
803 typedef volatile struct ALT_GPIO_DEBOUNCE_s ALT_GPIO_DEBOUNCE_t;
804 #endif /* __ASSEMBLY__ */
805 
806 /* The byte offset of the ALT_GPIO_DEBOUNCE register from the beginning of the component. */
807 #define ALT_GPIO_DEBOUNCE_OFST 0x48
808 /* The address of the ALT_GPIO_DEBOUNCE register. */
809 #define ALT_GPIO_DEBOUNCE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_DEBOUNCE_OFST))
810 
811 /*
812  * Register : Clear Interrupt Register - gpio_porta_eoi
813  *
814  * Port A Data Register interrupt handling.
815  *
816  * Register Layout
817  *
818  * Bits | Access | Reset | Description
819  * :--------|:-------|:------|:-----------------------------
820  * [28:0] | W | 0x0 | Clears Edge Interrupts Field
821  * [31:29] | ??? | 0x0 | *UNDEFINED*
822  *
823  */
824 /*
825  * Field : Clears Edge Interrupts Field - gpio_porta_eoi
826  *
827  * Controls the clearing of edge type interrupts from the Port A Data Register.
828  *
829  * Field Enumeration Values:
830  *
831  * Enum | Value | Description
832  * :------------------------------------------|:------|:-------------------
833  * ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_NOCLR | 0x0 | No interrupt clear
834  * ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_CLR | 0x1 | Clear interrupt
835  *
836  * Field Access Macros:
837  *
838  */
839 /*
840  * Enumerated value for register field ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI
841  *
842  * No interrupt clear
843  */
844 #define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_NOCLR 0x0
845 /*
846  * Enumerated value for register field ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI
847  *
848  * Clear interrupt
849  */
850 #define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_CLR 0x1
851 
852 /* The Least Significant Bit (LSB) position of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
853 #define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_LSB 0
854 /* The Most Significant Bit (MSB) position of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
855 #define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_MSB 28
856 /* The width in bits of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
857 #define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_WIDTH 29
858 /* The mask used to set the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value. */
859 #define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_SET_MSK 0x1fffffff
860 /* The mask used to clear the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value. */
861 #define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_CLR_MSK 0xe0000000
862 /* The reset value of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
863 #define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_RESET 0x0
864 /* Extracts the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI field value from a register. */
865 #define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_GET(value) (((value) & 0x1fffffff) >> 0)
866 /* Produces a ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value suitable for setting the register. */
867 #define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_SET(value) (((value) << 0) & 0x1fffffff)
868 
869 #ifndef __ASSEMBLY__
870 /*
871  * WARNING: The C register and register group struct declarations are provided for
872  * convenience and illustrative purposes. They should, however, be used with
873  * caution as the C language standard provides no guarantees about the alignment or
874  * atomicity of device memory accesses. The recommended practice for writing
875  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
876  * alt_write_word() functions.
877  *
878  * The struct declaration for register ALT_GPIO_PORTA_EOI.
879  */
880 struct ALT_GPIO_PORTA_EOI_s
881 {
882  uint32_t gpio_porta_eoi : 29; /* Clears Edge Interrupts Field */
883  uint32_t : 3; /* *UNDEFINED* */
884 };
885 
886 /* The typedef declaration for register ALT_GPIO_PORTA_EOI. */
887 typedef volatile struct ALT_GPIO_PORTA_EOI_s ALT_GPIO_PORTA_EOI_t;
888 #endif /* __ASSEMBLY__ */
889 
890 /* The byte offset of the ALT_GPIO_PORTA_EOI register from the beginning of the component. */
891 #define ALT_GPIO_PORTA_EOI_OFST 0x4c
892 /* The address of the ALT_GPIO_PORTA_EOI register. */
893 #define ALT_GPIO_PORTA_EOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_PORTA_EOI_OFST))
894 
895 /*
896  * Register : External Port A Register - gpio_ext_porta
897  *
898  * The external port register is used to input data to the metastability flops.
899  *
900  * Register Layout
901  *
902  * Bits | Access | Reset | Description
903  * :--------|:-------|:------|:--------------------
904  * [28:0] | R | 0x0 | External Port Field
905  * [31:29] | ??? | 0x0 | *UNDEFINED*
906  *
907  */
908 /*
909  * Field : External Port Field - gpio_ext_porta
910  *
911  * When Port A Data Register is configured as Input, then reading this location
912  * reads the values on the signals. When the data direction of Port A Data Register
913  * is set as Output, reading this location reads Port A Data Register
914  *
915  * Field Access Macros:
916  *
917  */
918 /* The Least Significant Bit (LSB) position of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
919 #define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_LSB 0
920 /* The Most Significant Bit (MSB) position of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
921 #define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_MSB 28
922 /* The width in bits of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
923 #define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_WIDTH 29
924 /* The mask used to set the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value. */
925 #define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_SET_MSK 0x1fffffff
926 /* The mask used to clear the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value. */
927 #define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_CLR_MSK 0xe0000000
928 /* The reset value of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
929 #define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_RESET 0x0
930 /* Extracts the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA field value from a register. */
931 #define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_GET(value) (((value) & 0x1fffffff) >> 0)
932 /* Produces a ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value suitable for setting the register. */
933 #define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_SET(value) (((value) << 0) & 0x1fffffff)
934 
935 #ifndef __ASSEMBLY__
936 /*
937  * WARNING: The C register and register group struct declarations are provided for
938  * convenience and illustrative purposes. They should, however, be used with
939  * caution as the C language standard provides no guarantees about the alignment or
940  * atomicity of device memory accesses. The recommended practice for writing
941  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
942  * alt_write_word() functions.
943  *
944  * The struct declaration for register ALT_GPIO_EXT_PORTA.
945  */
946 struct ALT_GPIO_EXT_PORTA_s
947 {
948  const uint32_t gpio_ext_porta : 29; /* External Port Field */
949  uint32_t : 3; /* *UNDEFINED* */
950 };
951 
952 /* The typedef declaration for register ALT_GPIO_EXT_PORTA. */
953 typedef volatile struct ALT_GPIO_EXT_PORTA_s ALT_GPIO_EXT_PORTA_t;
954 #endif /* __ASSEMBLY__ */
955 
956 /* The byte offset of the ALT_GPIO_EXT_PORTA register from the beginning of the component. */
957 #define ALT_GPIO_EXT_PORTA_OFST 0x50
958 /* The address of the ALT_GPIO_EXT_PORTA register. */
959 #define ALT_GPIO_EXT_PORTA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_EXT_PORTA_OFST))
960 
961 /*
962  * Register : Synchronization Level Register - gpio_ls_sync
963  *
964  * The Synchronization level register is used to synchronize input with l4_mp_clk
965  *
966  * Register Layout
967  *
968  * Bits | Access | Reset | Description
969  * :-------|:-------|:------|:----------------------------
970  * [0] | RW | 0x0 | Synchronization Level Field
971  * [31:1] | ??? | 0x0 | *UNDEFINED*
972  *
973  */
974 /*
975  * Field : Synchronization Level Field - gpio_ls_sync
976  *
977  * The level-sensitive interrupts is synchronized to l4_mp_clk.
978  *
979  * Field Enumeration Values:
980  *
981  * Enum | Value | Description
982  * :---------------------------------------|:------|:--------------------------------
983  * ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_NOSYNC | 0x0 | No synchronization to l4_mp_clk
984  * ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_SYNC | 0x1 | Synchronize to l4_mp_clk
985  *
986  * Field Access Macros:
987  *
988  */
989 /*
990  * Enumerated value for register field ALT_GPIO_LS_SYNC_GPIO_LS_SYNC
991  *
992  * No synchronization to l4_mp_clk
993  */
994 #define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_NOSYNC 0x0
995 /*
996  * Enumerated value for register field ALT_GPIO_LS_SYNC_GPIO_LS_SYNC
997  *
998  * Synchronize to l4_mp_clk
999  */
1000 #define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_SYNC 0x1
1001 
1002 /* The Least Significant Bit (LSB) position of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
1003 #define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_LSB 0
1004 /* The Most Significant Bit (MSB) position of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
1005 #define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_MSB 0
1006 /* The width in bits of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
1007 #define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_WIDTH 1
1008 /* The mask used to set the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */
1009 #define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_SET_MSK 0x00000001
1010 /* The mask used to clear the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */
1011 #define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_CLR_MSK 0xfffffffe
1012 /* The reset value of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
1013 #define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_RESET 0x0
1014 /* Extracts the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC field value from a register. */
1015 #define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_GET(value) (((value) & 0x00000001) >> 0)
1016 /* Produces a ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value suitable for setting the register. */
1017 #define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_SET(value) (((value) << 0) & 0x00000001)
1018 
1019 #ifndef __ASSEMBLY__
1020 /*
1021  * WARNING: The C register and register group struct declarations are provided for
1022  * convenience and illustrative purposes. They should, however, be used with
1023  * caution as the C language standard provides no guarantees about the alignment or
1024  * atomicity of device memory accesses. The recommended practice for writing
1025  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1026  * alt_write_word() functions.
1027  *
1028  * The struct declaration for register ALT_GPIO_LS_SYNC.
1029  */
1030 struct ALT_GPIO_LS_SYNC_s
1031 {
1032  uint32_t gpio_ls_sync : 1; /* Synchronization Level Field */
1033  uint32_t : 31; /* *UNDEFINED* */
1034 };
1035 
1036 /* The typedef declaration for register ALT_GPIO_LS_SYNC. */
1037 typedef volatile struct ALT_GPIO_LS_SYNC_s ALT_GPIO_LS_SYNC_t;
1038 #endif /* __ASSEMBLY__ */
1039 
1040 /* The byte offset of the ALT_GPIO_LS_SYNC register from the beginning of the component. */
1041 #define ALT_GPIO_LS_SYNC_OFST 0x60
1042 /* The address of the ALT_GPIO_LS_SYNC register. */
1043 #define ALT_GPIO_LS_SYNC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_LS_SYNC_OFST))
1044 
1045 /*
1046  * Register : ID Code Register - gpio_id_code
1047  *
1048  * GPIO ID code.
1049  *
1050  * Register Layout
1051  *
1052  * Bits | Access | Reset | Description
1053  * :-------|:-------|:------|:--------------
1054  * [31:0] | R | 0x0 | ID Code Field
1055  *
1056  */
1057 /*
1058  * Field : ID Code Field - gpio_id_code
1059  *
1060  * Chip identification
1061  *
1062  * Field Access Macros:
1063  *
1064  */
1065 /* The Least Significant Bit (LSB) position of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */
1066 #define ALT_GPIO_ID_CODE_GPIO_ID_CODE_LSB 0
1067 /* The Most Significant Bit (MSB) position of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */
1068 #define ALT_GPIO_ID_CODE_GPIO_ID_CODE_MSB 31
1069 /* The width in bits of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */
1070 #define ALT_GPIO_ID_CODE_GPIO_ID_CODE_WIDTH 32
1071 /* The mask used to set the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value. */
1072 #define ALT_GPIO_ID_CODE_GPIO_ID_CODE_SET_MSK 0xffffffff
1073 /* The mask used to clear the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value. */
1074 #define ALT_GPIO_ID_CODE_GPIO_ID_CODE_CLR_MSK 0x00000000
1075 /* The reset value of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */
1076 #define ALT_GPIO_ID_CODE_GPIO_ID_CODE_RESET 0x0
1077 /* Extracts the ALT_GPIO_ID_CODE_GPIO_ID_CODE field value from a register. */
1078 #define ALT_GPIO_ID_CODE_GPIO_ID_CODE_GET(value) (((value) & 0xffffffff) >> 0)
1079 /* Produces a ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value suitable for setting the register. */
1080 #define ALT_GPIO_ID_CODE_GPIO_ID_CODE_SET(value) (((value) << 0) & 0xffffffff)
1081 
1082 #ifndef __ASSEMBLY__
1083 /*
1084  * WARNING: The C register and register group struct declarations are provided for
1085  * convenience and illustrative purposes. They should, however, be used with
1086  * caution as the C language standard provides no guarantees about the alignment or
1087  * atomicity of device memory accesses. The recommended practice for writing
1088  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1089  * alt_write_word() functions.
1090  *
1091  * The struct declaration for register ALT_GPIO_ID_CODE.
1092  */
1093 struct ALT_GPIO_ID_CODE_s
1094 {
1095  const uint32_t gpio_id_code : 32; /* ID Code Field */
1096 };
1097 
1098 /* The typedef declaration for register ALT_GPIO_ID_CODE. */
1099 typedef volatile struct ALT_GPIO_ID_CODE_s ALT_GPIO_ID_CODE_t;
1100 #endif /* __ASSEMBLY__ */
1101 
1102 /* The byte offset of the ALT_GPIO_ID_CODE register from the beginning of the component. */
1103 #define ALT_GPIO_ID_CODE_OFST 0x64
1104 /* The address of the ALT_GPIO_ID_CODE register. */
1105 #define ALT_GPIO_ID_CODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_ID_CODE_OFST))
1106 
1107 /*
1108  * Register : GPIO Version Register - gpio_ver_id_code
1109  *
1110  * GPIO Component Version
1111  *
1112  * Register Layout
1113  *
1114  * Bits | Access | Reset | Description
1115  * :-------|:-------|:-----------|:------------------------------
1116  * [31:0] | R | 0x3230382a | ASCII Component Version Field
1117  *
1118  */
1119 /*
1120  * Field : ASCII Component Version Field - gpio_ver_id_code
1121  *
1122  * ASCII value for each number in the version, followed by *. For example.
1123  * 32_30_31_2A represents the version 2.01
1124  *
1125  * Field Access Macros:
1126  *
1127  */
1128 /* The Least Significant Bit (LSB) position of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
1129 #define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_LSB 0
1130 /* The Most Significant Bit (MSB) position of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
1131 #define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_MSB 31
1132 /* The width in bits of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
1133 #define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_WIDTH 32
1134 /* The mask used to set the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */
1135 #define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET_MSK 0xffffffff
1136 /* The mask used to clear the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */
1137 #define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_CLR_MSK 0x00000000
1138 /* The reset value of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
1139 #define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_RESET 0x3230382a
1140 /* Extracts the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE field value from a register. */
1141 #define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_GET(value) (((value) & 0xffffffff) >> 0)
1142 /* Produces a ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value suitable for setting the register. */
1143 #define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET(value) (((value) << 0) & 0xffffffff)
1144 
1145 #ifndef __ASSEMBLY__
1146 /*
1147  * WARNING: The C register and register group struct declarations are provided for
1148  * convenience and illustrative purposes. They should, however, be used with
1149  * caution as the C language standard provides no guarantees about the alignment or
1150  * atomicity of device memory accesses. The recommended practice for writing
1151  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1152  * alt_write_word() functions.
1153  *
1154  * The struct declaration for register ALT_GPIO_VER_ID_CODE.
1155  */
1156 struct ALT_GPIO_VER_ID_CODE_s
1157 {
1158  const uint32_t gpio_ver_id_code : 32; /* ASCII Component Version Field */
1159 };
1160 
1161 /* The typedef declaration for register ALT_GPIO_VER_ID_CODE. */
1162 typedef volatile struct ALT_GPIO_VER_ID_CODE_s ALT_GPIO_VER_ID_CODE_t;
1163 #endif /* __ASSEMBLY__ */
1164 
1165 /* The byte offset of the ALT_GPIO_VER_ID_CODE register from the beginning of the component. */
1166 #define ALT_GPIO_VER_ID_CODE_OFST 0x6c
1167 /* The address of the ALT_GPIO_VER_ID_CODE register. */
1168 #define ALT_GPIO_VER_ID_CODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_VER_ID_CODE_OFST))
1169 
1170 /*
1171  * Register : Configuration Register 2 - gpio_config_reg2
1172  *
1173  * Specifies the bit width of port A.
1174  *
1175  * Register Layout
1176  *
1177  * Bits | Access | Reset | Description
1178  * :--------|:-------|:------|:----------------------
1179  * [4:0] | R | 0x1c | Port A Width (less 1)
1180  * [9:5] | R | 0x7 | Port B Width (less 1)
1181  * [14:10] | R | 0x7 | Port C Width (less 1)
1182  * [19:15] | R | 0x7 | Port D Width (less 1)
1183  * [31:20] | ??? | 0x0 | *UNDEFINED*
1184  *
1185  */
1186 /*
1187  * Field : Port A Width (less 1) - encoded_id_pwidth_a
1188  *
1189  * Specifies the width of GPIO Port A. The value 28 represents the 29-bit width
1190  * less one.
1191  *
1192  * Field Enumeration Values:
1193  *
1194  * Enum | Value | Description
1195  * :-------------------------------------------------------|:------|:--------------------------
1196  * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits
1197  * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits
1198  *
1199  * Field Access Macros:
1200  *
1201  */
1202 /*
1203  * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A
1204  *
1205  * Width (less 1) of 8 bits
1206  */
1207 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS 0x7
1208 /*
1209  * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A
1210  *
1211  * Width (less 1) of 29 bits
1212  */
1213 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE29BITS 0x1c
1214 
1215 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
1216 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_LSB 0
1217 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
1218 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_MSB 4
1219 /* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
1220 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_WIDTH 5
1221 /* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value. */
1222 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET_MSK 0x0000001f
1223 /* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value. */
1224 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_CLR_MSK 0xffffffe0
1225 /* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
1226 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_RESET 0x1c
1227 /* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A field value from a register. */
1228 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_GET(value) (((value) & 0x0000001f) >> 0)
1229 /* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value suitable for setting the register. */
1230 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET(value) (((value) << 0) & 0x0000001f)
1231 
1232 /*
1233  * Field : Port B Width (less 1) - encoded_id_pwidth_b
1234  *
1235  * Specifies the width of GPIO Port B. Ignored because there is no Port B in the
1236  * GPIO.
1237  *
1238  * Field Enumeration Values:
1239  *
1240  * Enum | Value | Description
1241  * :-------------------------------------------------------|:------|:--------------------------
1242  * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits
1243  * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits
1244  *
1245  * Field Access Macros:
1246  *
1247  */
1248 /*
1249  * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B
1250  *
1251  * Width (less 1) of 8 bits
1252  */
1253 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS 0x7
1254 /*
1255  * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B
1256  *
1257  * Width (less 1) of 29 bits
1258  */
1259 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE29BITS 0x1c
1260 
1261 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
1262 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_LSB 5
1263 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
1264 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_MSB 9
1265 /* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
1266 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_WIDTH 5
1267 /* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value. */
1268 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET_MSK 0x000003e0
1269 /* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value. */
1270 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_CLR_MSK 0xfffffc1f
1271 /* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
1272 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_RESET 0x7
1273 /* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B field value from a register. */
1274 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_GET(value) (((value) & 0x000003e0) >> 5)
1275 /* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value suitable for setting the register. */
1276 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET(value) (((value) << 5) & 0x000003e0)
1277 
1278 /*
1279  * Field : Port C Width (less 1) - encoded_id_pwidth_c
1280  *
1281  * Specifies the width of GPIO Port C. Ignored because there is no Port C in the
1282  * GPIO.
1283  *
1284  * Field Enumeration Values:
1285  *
1286  * Enum | Value | Description
1287  * :-------------------------------------------------------|:------|:--------------------------
1288  * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits
1289  * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits
1290  *
1291  * Field Access Macros:
1292  *
1293  */
1294 /*
1295  * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C
1296  *
1297  * Width (less 1) of 8 bits
1298  */
1299 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS 0x7
1300 /*
1301  * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C
1302  *
1303  * Width (less 1) of 29 bits
1304  */
1305 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE29BITS 0x1c
1306 
1307 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
1308 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_LSB 10
1309 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
1310 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_MSB 14
1311 /* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
1312 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_WIDTH 5
1313 /* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value. */
1314 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET_MSK 0x00007c00
1315 /* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value. */
1316 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_CLR_MSK 0xffff83ff
1317 /* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
1318 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_RESET 0x7
1319 /* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C field value from a register. */
1320 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_GET(value) (((value) & 0x00007c00) >> 10)
1321 /* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value suitable for setting the register. */
1322 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET(value) (((value) << 10) & 0x00007c00)
1323 
1324 /*
1325  * Field : Port D Width (less 1) - encoded_id_pwidth_d
1326  *
1327  * Specifies the width of GPIO Port D. Ignored because there is no Port D in the
1328  * GPIO.
1329  *
1330  * Field Enumeration Values:
1331  *
1332  * Enum | Value | Description
1333  * :-------------------------------------------------------|:------|:--------------------------
1334  * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits
1335  * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits
1336  *
1337  * Field Access Macros:
1338  *
1339  */
1340 /*
1341  * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D
1342  *
1343  * Width (less 1) of 8 bits
1344  */
1345 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS 0x7
1346 /*
1347  * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D
1348  *
1349  * Width (less 1) of 29 bits
1350  */
1351 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE29BITS 0x1c
1352 
1353 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
1354 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_LSB 15
1355 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
1356 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_MSB 19
1357 /* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
1358 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_WIDTH 5
1359 /* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value. */
1360 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET_MSK 0x000f8000
1361 /* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value. */
1362 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_CLR_MSK 0xfff07fff
1363 /* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
1364 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_RESET 0x7
1365 /* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D field value from a register. */
1366 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_GET(value) (((value) & 0x000f8000) >> 15)
1367 /* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value suitable for setting the register. */
1368 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET(value) (((value) << 15) & 0x000f8000)
1369 
1370 #ifndef __ASSEMBLY__
1371 /*
1372  * WARNING: The C register and register group struct declarations are provided for
1373  * convenience and illustrative purposes. They should, however, be used with
1374  * caution as the C language standard provides no guarantees about the alignment or
1375  * atomicity of device memory accesses. The recommended practice for writing
1376  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1377  * alt_write_word() functions.
1378  *
1379  * The struct declaration for register ALT_GPIO_CFG_REG2.
1380  */
1381 struct ALT_GPIO_CFG_REG2_s
1382 {
1383  const uint32_t encoded_id_pwidth_a : 5; /* Port A Width (less 1) */
1384  const uint32_t encoded_id_pwidth_b : 5; /* Port B Width (less 1) */
1385  const uint32_t encoded_id_pwidth_c : 5; /* Port C Width (less 1) */
1386  const uint32_t encoded_id_pwidth_d : 5; /* Port D Width (less 1) */
1387  uint32_t : 12; /* *UNDEFINED* */
1388 };
1389 
1390 /* The typedef declaration for register ALT_GPIO_CFG_REG2. */
1391 typedef volatile struct ALT_GPIO_CFG_REG2_s ALT_GPIO_CFG_REG2_t;
1392 #endif /* __ASSEMBLY__ */
1393 
1394 /* The byte offset of the ALT_GPIO_CFG_REG2 register from the beginning of the component. */
1395 #define ALT_GPIO_CFG_REG2_OFST 0x70
1396 /* The address of the ALT_GPIO_CFG_REG2 register. */
1397 #define ALT_GPIO_CFG_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_CFG_REG2_OFST))
1398 
1399 /*
1400  * Register : Configuration Register 1 - gpio_config_reg1
1401  *
1402  * Reports settings of various GPIO configuration parameters
1403  *
1404  * Register Layout
1405  *
1406  * Bits | Access | Reset | Description
1407  * :--------|:-------|:------|:----------------------------------
1408  * [1:0] | R | 0x2 | APB DATA WIDTH
1409  * [3:2] | R | 0x0 | NUM PORTS
1410  * [4] | R | 0x1 | PORT A SINGLE CTL
1411  * [5] | R | 0x1 | PORT B SINGLE CTL
1412  * [6] | R | 0x1 | PORT C SINGLE CTL
1413  * [7] | R | 0x1 | PORT D SINGLE CTL
1414  * [8] | R | 0x0 | HW PORTA
1415  * [11:9] | ??? | 0x0 | *UNDEFINED*
1416  * [12] | R | 0x1 | Port A Interrupt Field
1417  * [13] | R | 0x1 | Debounce Field
1418  * [14] | R | 0x1 | Encoded GPIO Parameters Available
1419  * [15] | R | 0x1 | ID Field
1420  * [20:16] | R | 0x1f | Encoded ID Width Field
1421  * [31:21] | ??? | 0x0 | *UNDEFINED*
1422  *
1423  */
1424 /*
1425  * Field : APB DATA WIDTH - apb_data_width
1426  *
1427  * Fixed to support an ABP data bus width of 32-bits.
1428  *
1429  * Field Enumeration Values:
1430  *
1431  * Enum | Value | Description
1432  * :-----------------------------------------------|:------|:-------------------------
1433  * ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS | 0x2 | APB Data Width = 32-bits
1434  *
1435  * Field Access Macros:
1436  *
1437  */
1438 /*
1439  * Enumerated value for register field ALT_GPIO_CFG_REG1_APB_DATA_WIDTH
1440  *
1441  * APB Data Width = 32-bits
1442  */
1443 #define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2
1444 
1445 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
1446 #define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_LSB 0
1447 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
1448 #define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_MSB 1
1449 /* The width in bits of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
1450 #define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_WIDTH 2
1451 /* The mask used to set the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value. */
1452 #define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_SET_MSK 0x00000003
1453 /* The mask used to clear the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value. */
1454 #define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc
1455 /* The reset value of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
1456 #define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_RESET 0x2
1457 /* Extracts the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH field value from a register. */
1458 #define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0)
1459 /* Produces a ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value suitable for setting the register. */
1460 #define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003)
1461 
1462 /*
1463  * Field : NUM PORTS - num_ports
1464  *
1465  * The value of this register is fixed at one port (Port A).
1466  *
1467  * Field Enumeration Values:
1468  *
1469  * Enum | Value | Description
1470  * :---------------------------------------|:------|:-------------------------
1471  * ALT_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA | 0x0 | Number of GPIO Ports = 1
1472  *
1473  * Field Access Macros:
1474  *
1475  */
1476 /*
1477  * Enumerated value for register field ALT_GPIO_CFG_REG1_NUM_PORTS
1478  *
1479  * Number of GPIO Ports = 1
1480  */
1481 #define ALT_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA 0x0
1482 
1483 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */
1484 #define ALT_GPIO_CFG_REG1_NUM_PORTS_LSB 2
1485 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */
1486 #define ALT_GPIO_CFG_REG1_NUM_PORTS_MSB 3
1487 /* The width in bits of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */
1488 #define ALT_GPIO_CFG_REG1_NUM_PORTS_WIDTH 2
1489 /* The mask used to set the ALT_GPIO_CFG_REG1_NUM_PORTS register field value. */
1490 #define ALT_GPIO_CFG_REG1_NUM_PORTS_SET_MSK 0x0000000c
1491 /* The mask used to clear the ALT_GPIO_CFG_REG1_NUM_PORTS register field value. */
1492 #define ALT_GPIO_CFG_REG1_NUM_PORTS_CLR_MSK 0xfffffff3
1493 /* The reset value of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */
1494 #define ALT_GPIO_CFG_REG1_NUM_PORTS_RESET 0x0
1495 /* Extracts the ALT_GPIO_CFG_REG1_NUM_PORTS field value from a register. */
1496 #define ALT_GPIO_CFG_REG1_NUM_PORTS_GET(value) (((value) & 0x0000000c) >> 2)
1497 /* Produces a ALT_GPIO_CFG_REG1_NUM_PORTS register field value suitable for setting the register. */
1498 #define ALT_GPIO_CFG_REG1_NUM_PORTS_SET(value) (((value) << 2) & 0x0000000c)
1499 
1500 /*
1501  * Field : PORT A SINGLE CTL - porta_single_ctl
1502  *
1503  * Indicates the mode of operation of Port A to be software controlled only.
1504  *
1505  * Field Enumeration Values:
1506  *
1507  * Enum | Value | Description
1508  * :-------------------------------------------------|:------|:-----------------------------------------
1509  * ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control
1510  *
1511  * Field Access Macros:
1512  *
1513  */
1514 /*
1515  * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL
1516  *
1517  * Software Enabled Individual Port Control
1518  */
1519 #define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY 0x1
1520 
1521 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
1522 #define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_LSB 4
1523 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
1524 #define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_MSB 4
1525 /* The width in bits of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
1526 #define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_WIDTH 1
1527 /* The mask used to set the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value. */
1528 #define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET_MSK 0x00000010
1529 /* The mask used to clear the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value. */
1530 #define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_CLR_MSK 0xffffffef
1531 /* The reset value of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
1532 #define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_RESET 0x1
1533 /* Extracts the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL field value from a register. */
1534 #define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_GET(value) (((value) & 0x00000010) >> 4)
1535 /* Produces a ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value suitable for setting the register. */
1536 #define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET(value) (((value) << 4) & 0x00000010)
1537 
1538 /*
1539  * Field : PORT B SINGLE CTL - portb_single_ctl
1540  *
1541  * Indicates the mode of operation of Port B to be software controlled only.
1542  * Ignored because there is no Port B in the GPIO.
1543  *
1544  * Field Enumeration Values:
1545  *
1546  * Enum | Value | Description
1547  * :-------------------------------------------------|:------|:-----------------------------------------
1548  * ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control
1549  *
1550  * Field Access Macros:
1551  *
1552  */
1553 /*
1554  * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL
1555  *
1556  * Software Enabled Individual Port Control
1557  */
1558 #define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY 0x1
1559 
1560 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
1561 #define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_LSB 5
1562 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
1563 #define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_MSB 5
1564 /* The width in bits of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
1565 #define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_WIDTH 1
1566 /* The mask used to set the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value. */
1567 #define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET_MSK 0x00000020
1568 /* The mask used to clear the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value. */
1569 #define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_CLR_MSK 0xffffffdf
1570 /* The reset value of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
1571 #define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_RESET 0x1
1572 /* Extracts the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL field value from a register. */
1573 #define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_GET(value) (((value) & 0x00000020) >> 5)
1574 /* Produces a ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value suitable for setting the register. */
1575 #define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET(value) (((value) << 5) & 0x00000020)
1576 
1577 /*
1578  * Field : PORT C SINGLE CTL - portc_single_ctl
1579  *
1580  * Indicates the mode of operation of Port C to be software controlled only.
1581  * Ignored because there is no Port C in the GPIO.
1582  *
1583  * Field Enumeration Values:
1584  *
1585  * Enum | Value | Description
1586  * :-------------------------------------------------|:------|:-----------------------------------------
1587  * ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control
1588  *
1589  * Field Access Macros:
1590  *
1591  */
1592 /*
1593  * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL
1594  *
1595  * Software Enabled Individual Port Control
1596  */
1597 #define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY 0x1
1598 
1599 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
1600 #define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_LSB 6
1601 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
1602 #define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_MSB 6
1603 /* The width in bits of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
1604 #define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_WIDTH 1
1605 /* The mask used to set the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value. */
1606 #define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET_MSK 0x00000040
1607 /* The mask used to clear the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value. */
1608 #define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_CLR_MSK 0xffffffbf
1609 /* The reset value of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
1610 #define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_RESET 0x1
1611 /* Extracts the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL field value from a register. */
1612 #define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_GET(value) (((value) & 0x00000040) >> 6)
1613 /* Produces a ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value suitable for setting the register. */
1614 #define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET(value) (((value) << 6) & 0x00000040)
1615 
1616 /*
1617  * Field : PORT D SINGLE CTL - portd_single_ctl
1618  *
1619  * Indicates the mode of operation of Port D to be software controlled only.
1620  * Ignored because there is no Port D in the GPIO.
1621  *
1622  * Field Enumeration Values:
1623  *
1624  * Enum | Value | Description
1625  * :-------------------------------------------------|:------|:-----------------------------------------
1626  * ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control
1627  *
1628  * Field Access Macros:
1629  *
1630  */
1631 /*
1632  * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL
1633  *
1634  * Software Enabled Individual Port Control
1635  */
1636 #define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY 0x1
1637 
1638 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
1639 #define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_LSB 7
1640 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
1641 #define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_MSB 7
1642 /* The width in bits of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
1643 #define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_WIDTH 1
1644 /* The mask used to set the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value. */
1645 #define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET_MSK 0x00000080
1646 /* The mask used to clear the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value. */
1647 #define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_CLR_MSK 0xffffff7f
1648 /* The reset value of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
1649 #define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_RESET 0x1
1650 /* Extracts the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL field value from a register. */
1651 #define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_GET(value) (((value) & 0x00000080) >> 7)
1652 /* Produces a ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value suitable for setting the register. */
1653 #define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET(value) (((value) << 7) & 0x00000080)
1654 
1655 /*
1656  * Field : HW PORTA - hw_porta
1657  *
1658  * The value is fixed to enable Port A configuration to be controlled by software
1659  * only.
1660  *
1661  * Field Enumeration Values:
1662  *
1663  * Enum | Value | Description
1664  * :-----------------------------------------|:------|:---------------------------------------
1665  * ALT_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD | 0x0 | Software Configuration Control Enabled
1666  *
1667  * Field Access Macros:
1668  *
1669  */
1670 /*
1671  * Enumerated value for register field ALT_GPIO_CFG_REG1_HW_PORTA
1672  *
1673  * Software Configuration Control Enabled
1674  */
1675 #define ALT_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD 0x0
1676 
1677 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */
1678 #define ALT_GPIO_CFG_REG1_HW_PORTA_LSB 8
1679 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */
1680 #define ALT_GPIO_CFG_REG1_HW_PORTA_MSB 8
1681 /* The width in bits of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */
1682 #define ALT_GPIO_CFG_REG1_HW_PORTA_WIDTH 1
1683 /* The mask used to set the ALT_GPIO_CFG_REG1_HW_PORTA register field value. */
1684 #define ALT_GPIO_CFG_REG1_HW_PORTA_SET_MSK 0x00000100
1685 /* The mask used to clear the ALT_GPIO_CFG_REG1_HW_PORTA register field value. */
1686 #define ALT_GPIO_CFG_REG1_HW_PORTA_CLR_MSK 0xfffffeff
1687 /* The reset value of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */
1688 #define ALT_GPIO_CFG_REG1_HW_PORTA_RESET 0x0
1689 /* Extracts the ALT_GPIO_CFG_REG1_HW_PORTA field value from a register. */
1690 #define ALT_GPIO_CFG_REG1_HW_PORTA_GET(value) (((value) & 0x00000100) >> 8)
1691 /* Produces a ALT_GPIO_CFG_REG1_HW_PORTA register field value suitable for setting the register. */
1692 #define ALT_GPIO_CFG_REG1_HW_PORTA_SET(value) (((value) << 8) & 0x00000100)
1693 
1694 /*
1695  * Field : Port A Interrupt Field - porta_intr
1696  *
1697  * The value of this field is fixed to allow interrupts on Port A.
1698  *
1699  * Field Enumeration Values:
1700  *
1701  * Enum | Value | Description
1702  * :-------------------------------------------|:------|:--------------------------
1703  * ALT_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR | 0x1 | Port A Interrupts Enabled
1704  *
1705  * Field Access Macros:
1706  *
1707  */
1708 /*
1709  * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTA_INTR
1710  *
1711  * Port A Interrupts Enabled
1712  */
1713 #define ALT_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR 0x1
1714 
1715 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */
1716 #define ALT_GPIO_CFG_REG1_PORTA_INTR_LSB 12
1717 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */
1718 #define ALT_GPIO_CFG_REG1_PORTA_INTR_MSB 12
1719 /* The width in bits of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */
1720 #define ALT_GPIO_CFG_REG1_PORTA_INTR_WIDTH 1
1721 /* The mask used to set the ALT_GPIO_CFG_REG1_PORTA_INTR register field value. */
1722 #define ALT_GPIO_CFG_REG1_PORTA_INTR_SET_MSK 0x00001000
1723 /* The mask used to clear the ALT_GPIO_CFG_REG1_PORTA_INTR register field value. */
1724 #define ALT_GPIO_CFG_REG1_PORTA_INTR_CLR_MSK 0xffffefff
1725 /* The reset value of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */
1726 #define ALT_GPIO_CFG_REG1_PORTA_INTR_RESET 0x1
1727 /* Extracts the ALT_GPIO_CFG_REG1_PORTA_INTR field value from a register. */
1728 #define ALT_GPIO_CFG_REG1_PORTA_INTR_GET(value) (((value) & 0x00001000) >> 12)
1729 /* Produces a ALT_GPIO_CFG_REG1_PORTA_INTR register field value suitable for setting the register. */
1730 #define ALT_GPIO_CFG_REG1_PORTA_INTR_SET(value) (((value) << 12) & 0x00001000)
1731 
1732 /*
1733  * Field : Debounce Field - debounce
1734  *
1735  * The value of this field is fixed to allow debouncing of the Port A signals.
1736  *
1737  * Field Enumeration Values:
1738  *
1739  * Enum | Value | Description
1740  * :---------------------------------------|:------|:--------------------
1741  * ALT_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA | 0x1 | Debounce is Enabled
1742  *
1743  * Field Access Macros:
1744  *
1745  */
1746 /*
1747  * Enumerated value for register field ALT_GPIO_CFG_REG1_DEBOUNCE
1748  *
1749  * Debounce is Enabled
1750  */
1751 #define ALT_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA 0x1
1752 
1753 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */
1754 #define ALT_GPIO_CFG_REG1_DEBOUNCE_LSB 13
1755 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */
1756 #define ALT_GPIO_CFG_REG1_DEBOUNCE_MSB 13
1757 /* The width in bits of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */
1758 #define ALT_GPIO_CFG_REG1_DEBOUNCE_WIDTH 1
1759 /* The mask used to set the ALT_GPIO_CFG_REG1_DEBOUNCE register field value. */
1760 #define ALT_GPIO_CFG_REG1_DEBOUNCE_SET_MSK 0x00002000
1761 /* The mask used to clear the ALT_GPIO_CFG_REG1_DEBOUNCE register field value. */
1762 #define ALT_GPIO_CFG_REG1_DEBOUNCE_CLR_MSK 0xffffdfff
1763 /* The reset value of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */
1764 #define ALT_GPIO_CFG_REG1_DEBOUNCE_RESET 0x1
1765 /* Extracts the ALT_GPIO_CFG_REG1_DEBOUNCE field value from a register. */
1766 #define ALT_GPIO_CFG_REG1_DEBOUNCE_GET(value) (((value) & 0x00002000) >> 13)
1767 /* Produces a ALT_GPIO_CFG_REG1_DEBOUNCE register field value suitable for setting the register. */
1768 #define ALT_GPIO_CFG_REG1_DEBOUNCE_SET(value) (((value) << 13) & 0x00002000)
1769 
1770 /*
1771  * Field : Encoded GPIO Parameters Available - add_encoded_params
1772  *
1773  * Fixed to allow the indentification of the Designware IP component.
1774  *
1775  * Field Enumeration Values:
1776  *
1777  * Enum | Value | Description
1778  * :------------------------------------------------|:------|:--------------------------
1779  * ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS | 0x1 | Enable IP indentification
1780  *
1781  * Field Access Macros:
1782  *
1783  */
1784 /*
1785  * Enumerated value for register field ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS
1786  *
1787  * Enable IP indentification
1788  */
1789 #define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1
1790 
1791 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
1792 #define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_LSB 14
1793 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
1794 #define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_MSB 14
1795 /* The width in bits of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
1796 #define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_WIDTH 1
1797 /* The mask used to set the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value. */
1798 #define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET_MSK 0x00004000
1799 /* The mask used to clear the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value. */
1800 #define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_CLR_MSK 0xffffbfff
1801 /* The reset value of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
1802 #define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_RESET 0x1
1803 /* Extracts the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS field value from a register. */
1804 #define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00004000) >> 14)
1805 /* Produces a ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value suitable for setting the register. */
1806 #define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET(value) (((value) << 14) & 0x00004000)
1807 
1808 /*
1809  * Field : ID Field - gpio_id
1810  *
1811  * Provides an ID code value
1812  *
1813  * Field Enumeration Values:
1814  *
1815  * Enum | Value | Description
1816  * :-----------------------------------|:------|:-------------
1817  * ALT_GPIO_CFG_REG1_GPIO_ID_E_IDCODE | 0x1 | GPIO ID Code
1818  *
1819  * Field Access Macros:
1820  *
1821  */
1822 /*
1823  * Enumerated value for register field ALT_GPIO_CFG_REG1_GPIO_ID
1824  *
1825  * GPIO ID Code
1826  */
1827 #define ALT_GPIO_CFG_REG1_GPIO_ID_E_IDCODE 0x1
1828 
1829 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */
1830 #define ALT_GPIO_CFG_REG1_GPIO_ID_LSB 15
1831 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */
1832 #define ALT_GPIO_CFG_REG1_GPIO_ID_MSB 15
1833 /* The width in bits of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */
1834 #define ALT_GPIO_CFG_REG1_GPIO_ID_WIDTH 1
1835 /* The mask used to set the ALT_GPIO_CFG_REG1_GPIO_ID register field value. */
1836 #define ALT_GPIO_CFG_REG1_GPIO_ID_SET_MSK 0x00008000
1837 /* The mask used to clear the ALT_GPIO_CFG_REG1_GPIO_ID register field value. */
1838 #define ALT_GPIO_CFG_REG1_GPIO_ID_CLR_MSK 0xffff7fff
1839 /* The reset value of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */
1840 #define ALT_GPIO_CFG_REG1_GPIO_ID_RESET 0x1
1841 /* Extracts the ALT_GPIO_CFG_REG1_GPIO_ID field value from a register. */
1842 #define ALT_GPIO_CFG_REG1_GPIO_ID_GET(value) (((value) & 0x00008000) >> 15)
1843 /* Produces a ALT_GPIO_CFG_REG1_GPIO_ID register field value suitable for setting the register. */
1844 #define ALT_GPIO_CFG_REG1_GPIO_ID_SET(value) (((value) << 15) & 0x00008000)
1845 
1846 /*
1847  * Field : Encoded ID Width Field - encoded_id_width
1848  *
1849  * This value is fixed at 32 bits.
1850  *
1851  * Field Enumeration Values:
1852  *
1853  * Enum | Value | Description
1854  * :--------------------------------------------|:------|:------------------
1855  * ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH | 0x1f | Width of ID Field
1856  *
1857  * Field Access Macros:
1858  *
1859  */
1860 /*
1861  * Enumerated value for register field ALT_GPIO_CFG_REG1_ENC_ID_WIDTH
1862  *
1863  * Width of ID Field
1864  */
1865 #define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH 0x1f
1866 
1867 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
1868 #define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_LSB 16
1869 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
1870 #define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_MSB 20
1871 /* The width in bits of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
1872 #define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_WIDTH 5
1873 /* The mask used to set the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value. */
1874 #define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_SET_MSK 0x001f0000
1875 /* The mask used to clear the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value. */
1876 #define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_CLR_MSK 0xffe0ffff
1877 /* The reset value of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
1878 #define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_RESET 0x1f
1879 /* Extracts the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH field value from a register. */
1880 #define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_GET(value) (((value) & 0x001f0000) >> 16)
1881 /* Produces a ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value suitable for setting the register. */
1882 #define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_SET(value) (((value) << 16) & 0x001f0000)
1883 
1884 #ifndef __ASSEMBLY__
1885 /*
1886  * WARNING: The C register and register group struct declarations are provided for
1887  * convenience and illustrative purposes. They should, however, be used with
1888  * caution as the C language standard provides no guarantees about the alignment or
1889  * atomicity of device memory accesses. The recommended practice for writing
1890  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1891  * alt_write_word() functions.
1892  *
1893  * The struct declaration for register ALT_GPIO_CFG_REG1.
1894  */
1895 struct ALT_GPIO_CFG_REG1_s
1896 {
1897  const uint32_t apb_data_width : 2; /* APB DATA WIDTH */
1898  const uint32_t num_ports : 2; /* NUM PORTS */
1899  const uint32_t porta_single_ctl : 1; /* PORT A SINGLE CTL */
1900  const uint32_t portb_single_ctl : 1; /* PORT B SINGLE CTL */
1901  const uint32_t portc_single_ctl : 1; /* PORT C SINGLE CTL */
1902  const uint32_t portd_single_ctl : 1; /* PORT D SINGLE CTL */
1903  const uint32_t hw_porta : 1; /* HW PORTA */
1904  uint32_t : 3; /* *UNDEFINED* */
1905  const uint32_t porta_intr : 1; /* Port A Interrupt Field */
1906  const uint32_t debounce : 1; /* Debounce Field */
1907  const uint32_t add_encoded_params : 1; /* Encoded GPIO Parameters Available */
1908  const uint32_t gpio_id : 1; /* ID Field */
1909  const uint32_t encoded_id_width : 5; /* Encoded ID Width Field */
1910  uint32_t : 11; /* *UNDEFINED* */
1911 };
1912 
1913 /* The typedef declaration for register ALT_GPIO_CFG_REG1. */
1914 typedef volatile struct ALT_GPIO_CFG_REG1_s ALT_GPIO_CFG_REG1_t;
1915 #endif /* __ASSEMBLY__ */
1916 
1917 /* The byte offset of the ALT_GPIO_CFG_REG1 register from the beginning of the component. */
1918 #define ALT_GPIO_CFG_REG1_OFST 0x74
1919 /* The address of the ALT_GPIO_CFG_REG1 register. */
1920 #define ALT_GPIO_CFG_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_CFG_REG1_OFST))
1921 
1922 #ifndef __ASSEMBLY__
1923 /*
1924  * WARNING: The C register and register group struct declarations are provided for
1925  * convenience and illustrative purposes. They should, however, be used with
1926  * caution as the C language standard provides no guarantees about the alignment or
1927  * atomicity of device memory accesses. The recommended practice for writing
1928  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1929  * alt_write_word() functions.
1930  *
1931  * The struct declaration for register group ALT_GPIO.
1932  */
1933 struct ALT_GPIO_s
1934 {
1935  ALT_GPIO_SWPORTA_DR_t gpio_swporta_dr; /* ALT_GPIO_SWPORTA_DR */
1936  ALT_GPIO_SWPORTA_DDR_t gpio_swporta_ddr; /* ALT_GPIO_SWPORTA_DDR */
1937  volatile uint32_t _pad_0x8_0x2f[10]; /* *UNDEFINED* */
1938  ALT_GPIO_INTEN_t gpio_inten; /* ALT_GPIO_INTEN */
1939  ALT_GPIO_INTMSK_t gpio_intmask; /* ALT_GPIO_INTMSK */
1940  ALT_GPIO_INTTYPE_LEVEL_t gpio_inttype_level; /* ALT_GPIO_INTTYPE_LEVEL */
1941  ALT_GPIO_INT_POL_t gpio_int_polarity; /* ALT_GPIO_INT_POL */
1942  ALT_GPIO_INTSTAT_t gpio_intstatus; /* ALT_GPIO_INTSTAT */
1943  ALT_GPIO_RAW_INTSTAT_t gpio_raw_intstatus; /* ALT_GPIO_RAW_INTSTAT */
1944  ALT_GPIO_DEBOUNCE_t gpio_debounce; /* ALT_GPIO_DEBOUNCE */
1945  ALT_GPIO_PORTA_EOI_t gpio_porta_eoi; /* ALT_GPIO_PORTA_EOI */
1946  ALT_GPIO_EXT_PORTA_t gpio_ext_porta; /* ALT_GPIO_EXT_PORTA */
1947  volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
1948  ALT_GPIO_LS_SYNC_t gpio_ls_sync; /* ALT_GPIO_LS_SYNC */
1949  ALT_GPIO_ID_CODE_t gpio_id_code; /* ALT_GPIO_ID_CODE */
1950  volatile uint32_t _pad_0x68_0x6b; /* *UNDEFINED* */
1951  ALT_GPIO_VER_ID_CODE_t gpio_ver_id_code; /* ALT_GPIO_VER_ID_CODE */
1952  ALT_GPIO_CFG_REG2_t gpio_config_reg2; /* ALT_GPIO_CFG_REG2 */
1953  ALT_GPIO_CFG_REG1_t gpio_config_reg1; /* ALT_GPIO_CFG_REG1 */
1954  volatile uint32_t _pad_0x78_0x80[2]; /* *UNDEFINED* */
1955 };
1956 
1957 /* The typedef declaration for register group ALT_GPIO. */
1958 typedef volatile struct ALT_GPIO_s ALT_GPIO_t;
1959 /* The struct declaration for the raw register contents of register group ALT_GPIO. */
1960 struct ALT_GPIO_raw_s
1961 {
1962  volatile uint32_t gpio_swporta_dr; /* ALT_GPIO_SWPORTA_DR */
1963  volatile uint32_t gpio_swporta_ddr; /* ALT_GPIO_SWPORTA_DDR */
1964  uint32_t _pad_0x8_0x2f[10]; /* *UNDEFINED* */
1965  volatile uint32_t gpio_inten; /* ALT_GPIO_INTEN */
1966  volatile uint32_t gpio_intmask; /* ALT_GPIO_INTMSK */
1967  volatile uint32_t gpio_inttype_level; /* ALT_GPIO_INTTYPE_LEVEL */
1968  volatile uint32_t gpio_int_polarity; /* ALT_GPIO_INT_POL */
1969  volatile uint32_t gpio_intstatus; /* ALT_GPIO_INTSTAT */
1970  volatile uint32_t gpio_raw_intstatus; /* ALT_GPIO_RAW_INTSTAT */
1971  volatile uint32_t gpio_debounce; /* ALT_GPIO_DEBOUNCE */
1972  volatile uint32_t gpio_porta_eoi; /* ALT_GPIO_PORTA_EOI */
1973  volatile uint32_t gpio_ext_porta; /* ALT_GPIO_EXT_PORTA */
1974  uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
1975  volatile uint32_t gpio_ls_sync; /* ALT_GPIO_LS_SYNC */
1976  volatile uint32_t gpio_id_code; /* ALT_GPIO_ID_CODE */
1977  uint32_t _pad_0x68_0x6b; /* *UNDEFINED* */
1978  volatile uint32_t gpio_ver_id_code; /* ALT_GPIO_VER_ID_CODE */
1979  volatile uint32_t gpio_config_reg2; /* ALT_GPIO_CFG_REG2 */
1980  volatile uint32_t gpio_config_reg1; /* ALT_GPIO_CFG_REG1 */
1981  uint32_t _pad_0x78_0x80[2]; /* *UNDEFINED* */
1982 };
1983 
1984 /* The typedef declaration for the raw register contents of register group ALT_GPIO. */
1985 typedef volatile struct ALT_GPIO_raw_s ALT_GPIO_raw_t;
1986 #endif /* __ASSEMBLY__ */
1987 
1988 
1989 #ifdef __cplusplus
1990 }
1991 #endif /* __cplusplus */
1992 #endif /* __ALTERA_ALT_GPIO_H__ */
1993