Hardware Libraries  20.1
Arria 10 SoC Hardware Manager
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Groups
alt_fpgamgr.h
1 /***********************************************************************************
2 * *
3 * Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
4 * *
5 * Redistribution and use in source and binary forms, with or without *
6 * modification, are permitted provided that the following conditions are met: *
7 * *
8 * 1. Redistributions of source code must retain the above copyright notice, *
9 * this list of conditions and the following disclaimer. *
10 * *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, *
12 * this list of conditions and the following disclaimer in the documentation *
13 * and/or other materials provided with the distribution. *
14 * *
15 * 3. Neither the name of the copyright holder nor the names of its contributors *
16 * may be used to endorse or promote products derived from this software without *
17 * specific prior written permission. *
18 * *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
29 * POSSIBILITY OF SUCH DAMAGE. *
30 * *
31 ***********************************************************************************/
32 
33 /* Altera - ALT_FPGAMGR */
34 
35 #ifndef __ALT_SOCAL_FPGAMGR_H__
36 #define __ALT_SOCAL_FPGAMGR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_FPGAMGR
50  *
51  */
52 /*
53  * Register : DCLK Count Register - dclkcnt
54  *
55  * Used to give software control in enabling DCLK at any time.
56  *
57  * SW will need control of the DCLK in specific configuration and partial
58  * reconfiguration initialization steps to send spurious DCLKs required by the CB.
59  * SW takes ownership for DCLK during normal configuration, partial
60  * reconfiguration, error scenerio handshakes including SEU CRC error during
61  * partial reconfiguration, SW early abort of partial reconfiguration, and
62  * initializatin phase DCLK driving.
63  *
64  * During initialization phase, a configuration image loaded into the FPGA can
65  * request that DCLK be used as the initialization phase clock instead of the
66  * default internal oscillator or optionally the CLKUSR pin. In the case that DCLK
67  * is requested, the DCLKCNT register is used by software to control DCLK during
68  * the initialization phase.
69  *
70  * Software should poll the DCLKSTAT.DCNTDONE write one to clear register to be set
71  * when the correct number of DCLKs have completed. Software should clear
72  * DCLKSTAT.DCNTDONE before writing to the DCLKCNT register again.
73  *
74  * This field only affects the FPGA if CTRL.EN is 1.
75  *
76  * Register Layout
77  *
78  * Bits | Access | Reset | Description
79  * :-------|:-------|:------|:------------
80  * [31:0] | RW | 0x0 | Count
81  *
82  */
83 /*
84  * Field : Count - cnt
85  *
86  * Controls DCLK counter.
87  *
88  * Software writes a non-zero value into CNT and the FPGA Manager generates the
89  * specified number of DCLK pulses and decrements COUNT. This register will read
90  * back the original value written by software.
91  *
92  * Software can write CNT at any time.
93  *
94  * Field Access Macros:
95  *
96  */
97 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_DCLKCNT_CNT register field. */
98 #define ALT_FPGAMGR_DCLKCNT_CNT_LSB 0
99 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_DCLKCNT_CNT register field. */
100 #define ALT_FPGAMGR_DCLKCNT_CNT_MSB 31
101 /* The width in bits of the ALT_FPGAMGR_DCLKCNT_CNT register field. */
102 #define ALT_FPGAMGR_DCLKCNT_CNT_WIDTH 32
103 /* The mask used to set the ALT_FPGAMGR_DCLKCNT_CNT register field value. */
104 #define ALT_FPGAMGR_DCLKCNT_CNT_SET_MSK 0xffffffff
105 /* The mask used to clear the ALT_FPGAMGR_DCLKCNT_CNT register field value. */
106 #define ALT_FPGAMGR_DCLKCNT_CNT_CLR_MSK 0x00000000
107 /* The reset value of the ALT_FPGAMGR_DCLKCNT_CNT register field. */
108 #define ALT_FPGAMGR_DCLKCNT_CNT_RESET 0x0
109 /* Extracts the ALT_FPGAMGR_DCLKCNT_CNT field value from a register. */
110 #define ALT_FPGAMGR_DCLKCNT_CNT_GET(value) (((value) & 0xffffffff) >> 0)
111 /* Produces a ALT_FPGAMGR_DCLKCNT_CNT register field value suitable for setting the register. */
112 #define ALT_FPGAMGR_DCLKCNT_CNT_SET(value) (((value) << 0) & 0xffffffff)
113 
114 #ifndef __ASSEMBLY__
115 /*
116  * WARNING: The C register and register group struct declarations are provided for
117  * convenience and illustrative purposes. They should, however, be used with
118  * caution as the C language standard provides no guarantees about the alignment or
119  * atomicity of device memory accesses. The recommended practice for writing
120  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
121  * alt_write_word() functions.
122  *
123  * The struct declaration for register ALT_FPGAMGR_DCLKCNT.
124  */
125 struct ALT_FPGAMGR_DCLKCNT_s
126 {
127  uint32_t cnt : 32; /* Count */
128 };
129 
130 /* The typedef declaration for register ALT_FPGAMGR_DCLKCNT. */
131 typedef volatile struct ALT_FPGAMGR_DCLKCNT_s ALT_FPGAMGR_DCLKCNT_t;
132 #endif /* __ASSEMBLY__ */
133 
134 /* The reset value of the ALT_FPGAMGR_DCLKCNT register. */
135 #define ALT_FPGAMGR_DCLKCNT_RESET 0x00000000
136 /* The byte offset of the ALT_FPGAMGR_DCLKCNT register from the beginning of the component. */
137 #define ALT_FPGAMGR_DCLKCNT_OFST 0x8
138 
139 /*
140  * Register : DCLK Status Register - dclkstat
141  *
142  * This write one to clear register indicates that the DCLKCNT has counted down to
143  * zero. The DCLKCNT is used by software to drive spurious DCLKs to the FPGA.
144  * Software will poll this bit after writing DCLKCNT to know when all of the DCLKs
145  * have been sent.
146  *
147  * Register Layout
148  *
149  * Bits | Access | Reset | Description
150  * :-------|:-------|:------|:----------------
151  * [0] | RW | 0x0 | DCLK Count Done
152  * [31:1] | ??? | 0x0 | *UNDEFINED*
153  *
154  */
155 /*
156  * Field : DCLK Count Done - dcntdone
157  *
158  * This bit is write one to clear. This bit gets set after the DCLKCNT has
159  * counted down to zero (transition from 1 to 0).
160  *
161  * Field Enumeration Values:
162  *
163  * Enum | Value | Description
164  * :----------------------------------------|:------|:--------------------------------
165  * ALT_FPGAMGR_DCLKSTAT_DCNTDONE_E_NOTDONE | 0x0 | DCLKCNT is still counting down.
166  * ALT_FPGAMGR_DCLKSTAT_DCNTDONE_E_DONE | 0x1 | DCLKCNT is done counting down.
167  *
168  * Field Access Macros:
169  *
170  */
171 /*
172  * Enumerated value for register field ALT_FPGAMGR_DCLKSTAT_DCNTDONE
173  *
174  * DCLKCNT is still counting down.
175  */
176 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_E_NOTDONE 0x0
177 /*
178  * Enumerated value for register field ALT_FPGAMGR_DCLKSTAT_DCNTDONE
179  *
180  * DCLKCNT is done counting down.
181  */
182 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_E_DONE 0x1
183 
184 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_DCLKSTAT_DCNTDONE register field. */
185 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_LSB 0
186 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_DCLKSTAT_DCNTDONE register field. */
187 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_MSB 0
188 /* The width in bits of the ALT_FPGAMGR_DCLKSTAT_DCNTDONE register field. */
189 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_WIDTH 1
190 /* The mask used to set the ALT_FPGAMGR_DCLKSTAT_DCNTDONE register field value. */
191 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_SET_MSK 0x00000001
192 /* The mask used to clear the ALT_FPGAMGR_DCLKSTAT_DCNTDONE register field value. */
193 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_CLR_MSK 0xfffffffe
194 /* The reset value of the ALT_FPGAMGR_DCLKSTAT_DCNTDONE register field. */
195 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_RESET 0x0
196 /* Extracts the ALT_FPGAMGR_DCLKSTAT_DCNTDONE field value from a register. */
197 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_GET(value) (((value) & 0x00000001) >> 0)
198 /* Produces a ALT_FPGAMGR_DCLKSTAT_DCNTDONE register field value suitable for setting the register. */
199 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_SET(value) (((value) << 0) & 0x00000001)
200 
201 #ifndef __ASSEMBLY__
202 /*
203  * WARNING: The C register and register group struct declarations are provided for
204  * convenience and illustrative purposes. They should, however, be used with
205  * caution as the C language standard provides no guarantees about the alignment or
206  * atomicity of device memory accesses. The recommended practice for writing
207  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
208  * alt_write_word() functions.
209  *
210  * The struct declaration for register ALT_FPGAMGR_DCLKSTAT.
211  */
212 struct ALT_FPGAMGR_DCLKSTAT_s
213 {
214  uint32_t dcntdone : 1; /* DCLK Count Done */
215  uint32_t : 31; /* *UNDEFINED* */
216 };
217 
218 /* The typedef declaration for register ALT_FPGAMGR_DCLKSTAT. */
219 typedef volatile struct ALT_FPGAMGR_DCLKSTAT_s ALT_FPGAMGR_DCLKSTAT_t;
220 #endif /* __ASSEMBLY__ */
221 
222 /* The reset value of the ALT_FPGAMGR_DCLKSTAT register. */
223 #define ALT_FPGAMGR_DCLKSTAT_RESET 0x00000000
224 /* The byte offset of the ALT_FPGAMGR_DCLKSTAT register from the beginning of the component. */
225 #define ALT_FPGAMGR_DCLKSTAT_OFST 0xc
226 
227 /*
228  * Register : General-Purpose Output Register - gpo
229  *
230  * Provides a low-latency, low-performance, and simple way to drive general-purpose
231  * signals to the FPGA fabric.
232  *
233  * Register Layout
234  *
235  * Bits | Access | Reset | Description
236  * :-------|:-------|:------|:------------
237  * [31:0] | RW | 0x0 | Value
238  *
239  */
240 /*
241  * Field : Value - value
242  *
243  * Drives s2f_gp[31:0] with specified value. When read, returns the current value
244  * being driven to the FPGA fabric.
245  *
246  * Field Access Macros:
247  *
248  */
249 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_GPO_VALUE register field. */
250 #define ALT_FPGAMGR_GPO_VALUE_LSB 0
251 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_GPO_VALUE register field. */
252 #define ALT_FPGAMGR_GPO_VALUE_MSB 31
253 /* The width in bits of the ALT_FPGAMGR_GPO_VALUE register field. */
254 #define ALT_FPGAMGR_GPO_VALUE_WIDTH 32
255 /* The mask used to set the ALT_FPGAMGR_GPO_VALUE register field value. */
256 #define ALT_FPGAMGR_GPO_VALUE_SET_MSK 0xffffffff
257 /* The mask used to clear the ALT_FPGAMGR_GPO_VALUE register field value. */
258 #define ALT_FPGAMGR_GPO_VALUE_CLR_MSK 0x00000000
259 /* The reset value of the ALT_FPGAMGR_GPO_VALUE register field. */
260 #define ALT_FPGAMGR_GPO_VALUE_RESET 0x0
261 /* Extracts the ALT_FPGAMGR_GPO_VALUE field value from a register. */
262 #define ALT_FPGAMGR_GPO_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
263 /* Produces a ALT_FPGAMGR_GPO_VALUE register field value suitable for setting the register. */
264 #define ALT_FPGAMGR_GPO_VALUE_SET(value) (((value) << 0) & 0xffffffff)
265 
266 #ifndef __ASSEMBLY__
267 /*
268  * WARNING: The C register and register group struct declarations are provided for
269  * convenience and illustrative purposes. They should, however, be used with
270  * caution as the C language standard provides no guarantees about the alignment or
271  * atomicity of device memory accesses. The recommended practice for writing
272  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
273  * alt_write_word() functions.
274  *
275  * The struct declaration for register ALT_FPGAMGR_GPO.
276  */
277 struct ALT_FPGAMGR_GPO_s
278 {
279  uint32_t value : 32; /* Value */
280 };
281 
282 /* The typedef declaration for register ALT_FPGAMGR_GPO. */
283 typedef volatile struct ALT_FPGAMGR_GPO_s ALT_FPGAMGR_GPO_t;
284 #endif /* __ASSEMBLY__ */
285 
286 /* The reset value of the ALT_FPGAMGR_GPO register. */
287 #define ALT_FPGAMGR_GPO_RESET 0x00000000
288 /* The byte offset of the ALT_FPGAMGR_GPO register from the beginning of the component. */
289 #define ALT_FPGAMGR_GPO_OFST 0x10
290 
291 /*
292  * Register : General-Purpose Input Register - gpi
293  *
294  * Provides a low-latency, low-performance, and simple way to read general-purpose
295  * signals driven from the FPGA fabric.
296  *
297  * Register Layout
298  *
299  * Bits | Access | Reset | Description
300  * :-------|:-------|:------|:------------
301  * [31:0] | R | 0x0 | Value
302  *
303  */
304 /*
305  * Field : Value - value
306  *
307  * The value being driven from the FPGA fabric on f2s_gp[31:0]. If the FPGA is not
308  * in User Mode, the value of this field is undefined.
309  *
310  * Field Access Macros:
311  *
312  */
313 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_GPI_VALUE register field. */
314 #define ALT_FPGAMGR_GPI_VALUE_LSB 0
315 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_GPI_VALUE register field. */
316 #define ALT_FPGAMGR_GPI_VALUE_MSB 31
317 /* The width in bits of the ALT_FPGAMGR_GPI_VALUE register field. */
318 #define ALT_FPGAMGR_GPI_VALUE_WIDTH 32
319 /* The mask used to set the ALT_FPGAMGR_GPI_VALUE register field value. */
320 #define ALT_FPGAMGR_GPI_VALUE_SET_MSK 0xffffffff
321 /* The mask used to clear the ALT_FPGAMGR_GPI_VALUE register field value. */
322 #define ALT_FPGAMGR_GPI_VALUE_CLR_MSK 0x00000000
323 /* The reset value of the ALT_FPGAMGR_GPI_VALUE register field. */
324 #define ALT_FPGAMGR_GPI_VALUE_RESET 0x0
325 /* Extracts the ALT_FPGAMGR_GPI_VALUE field value from a register. */
326 #define ALT_FPGAMGR_GPI_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
327 /* Produces a ALT_FPGAMGR_GPI_VALUE register field value suitable for setting the register. */
328 #define ALT_FPGAMGR_GPI_VALUE_SET(value) (((value) << 0) & 0xffffffff)
329 
330 #ifndef __ASSEMBLY__
331 /*
332  * WARNING: The C register and register group struct declarations are provided for
333  * convenience and illustrative purposes. They should, however, be used with
334  * caution as the C language standard provides no guarantees about the alignment or
335  * atomicity of device memory accesses. The recommended practice for writing
336  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
337  * alt_write_word() functions.
338  *
339  * The struct declaration for register ALT_FPGAMGR_GPI.
340  */
341 struct ALT_FPGAMGR_GPI_s
342 {
343  const uint32_t value : 32; /* Value */
344 };
345 
346 /* The typedef declaration for register ALT_FPGAMGR_GPI. */
347 typedef volatile struct ALT_FPGAMGR_GPI_s ALT_FPGAMGR_GPI_t;
348 #endif /* __ASSEMBLY__ */
349 
350 /* The reset value of the ALT_FPGAMGR_GPI register. */
351 #define ALT_FPGAMGR_GPI_RESET 0x00000000
352 /* The byte offset of the ALT_FPGAMGR_GPI register from the beginning of the component. */
353 #define ALT_FPGAMGR_GPI_OFST 0x14
354 
355 /*
356  * Register : Miscellaneous Input Register - misci
357  *
358  * Provides a low-latency, low-performance, and simple way to read specific
359  * handshaking signals driven from the FPGA fabric.
360  *
361  * Register Layout
362  *
363  * Bits | Access | Reset | Description
364  * :-------|:-------|:--------|:--------------------------
365  * [0] | R | Unknown | Boot From FPGA on Failure
366  * [1] | R | Unknown | Boot From FPGA Ready
367  * [31:2] | ??? | 0x0 | *UNDEFINED*
368  *
369  */
370 /*
371  * Field : Boot From FPGA on Failure - bootFPGAfail
372  *
373  * The value of the f2s_boot_from_fpga_on_failure signal from the FPGA fabric. If
374  * the FPGA is not in User Mode, the value of this field is undefined.
375  *
376  * 1 = Boot ROM will boot from FPGA if boot from normal boot device fails.
377  *
378  * 0 = Boot ROM will not boot from FPGA if boot from normal boot device fails.
379  *
380  * Field Access Macros:
381  *
382  */
383 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_MISCI_BOOTFPGAFAIL register field. */
384 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_LSB 0
385 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_MISCI_BOOTFPGAFAIL register field. */
386 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_MSB 0
387 /* The width in bits of the ALT_FPGAMGR_MISCI_BOOTFPGAFAIL register field. */
388 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_WIDTH 1
389 /* The mask used to set the ALT_FPGAMGR_MISCI_BOOTFPGAFAIL register field value. */
390 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_SET_MSK 0x00000001
391 /* The mask used to clear the ALT_FPGAMGR_MISCI_BOOTFPGAFAIL register field value. */
392 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_CLR_MSK 0xfffffffe
393 /* The reset value of the ALT_FPGAMGR_MISCI_BOOTFPGAFAIL register field is UNKNOWN. */
394 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_RESET 0x0
395 /* Extracts the ALT_FPGAMGR_MISCI_BOOTFPGAFAIL field value from a register. */
396 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_GET(value) (((value) & 0x00000001) >> 0)
397 /* Produces a ALT_FPGAMGR_MISCI_BOOTFPGAFAIL register field value suitable for setting the register. */
398 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_SET(value) (((value) << 0) & 0x00000001)
399 
400 /*
401  * Field : Boot From FPGA Ready - bootFPGArdy
402  *
403  * The value of the f2s_boot_from_fpga_ready signal from the FPGA fabric. If the
404  * FPGA is not in User Mode, the value of this field is undefined.
405  *
406  * 1 = FPGA fabric is ready to accept AXI master requests from the HPS2FPGA bridge.
407  *
408  * 0 = FPGA fabric is not ready (probably still processing a reset).
409  *
410  * Field Access Macros:
411  *
412  */
413 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_MISCI_BOOTFPGARDY register field. */
414 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_LSB 1
415 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_MISCI_BOOTFPGARDY register field. */
416 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_MSB 1
417 /* The width in bits of the ALT_FPGAMGR_MISCI_BOOTFPGARDY register field. */
418 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_WIDTH 1
419 /* The mask used to set the ALT_FPGAMGR_MISCI_BOOTFPGARDY register field value. */
420 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_SET_MSK 0x00000002
421 /* The mask used to clear the ALT_FPGAMGR_MISCI_BOOTFPGARDY register field value. */
422 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_CLR_MSK 0xfffffffd
423 /* The reset value of the ALT_FPGAMGR_MISCI_BOOTFPGARDY register field is UNKNOWN. */
424 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_RESET 0x0
425 /* Extracts the ALT_FPGAMGR_MISCI_BOOTFPGARDY field value from a register. */
426 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_GET(value) (((value) & 0x00000002) >> 1)
427 /* Produces a ALT_FPGAMGR_MISCI_BOOTFPGARDY register field value suitable for setting the register. */
428 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_SET(value) (((value) << 1) & 0x00000002)
429 
430 #ifndef __ASSEMBLY__
431 /*
432  * WARNING: The C register and register group struct declarations are provided for
433  * convenience and illustrative purposes. They should, however, be used with
434  * caution as the C language standard provides no guarantees about the alignment or
435  * atomicity of device memory accesses. The recommended practice for writing
436  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
437  * alt_write_word() functions.
438  *
439  * The struct declaration for register ALT_FPGAMGR_MISCI.
440  */
441 struct ALT_FPGAMGR_MISCI_s
442 {
443  const uint32_t bootFPGAfail : 1; /* Boot From FPGA on Failure */
444  const uint32_t bootFPGArdy : 1; /* Boot From FPGA Ready */
445  uint32_t : 30; /* *UNDEFINED* */
446 };
447 
448 /* The typedef declaration for register ALT_FPGAMGR_MISCI. */
449 typedef volatile struct ALT_FPGAMGR_MISCI_s ALT_FPGAMGR_MISCI_t;
450 #endif /* __ASSEMBLY__ */
451 
452 /* The reset value of the ALT_FPGAMGR_MISCI register. */
453 #define ALT_FPGAMGR_MISCI_RESET 0x00000000
454 /* The byte offset of the ALT_FPGAMGR_MISCI register from the beginning of the component. */
455 #define ALT_FPGAMGR_MISCI_OFST 0x18
456 
457 /*
458  * Register : Extracted EMR register content - emr_data0
459  *
460  * bits [31:0] of EMR register
461  *
462  * Register Layout
463  *
464  * Bits | Access | Reset | Description
465  * :-------|:-------|:------|:------------
466  * [31:0] | R | 0x0 | Value
467  *
468  */
469 /*
470  * Field : Value - value
471  *
472  * EMR register bits
473  *
474  * Field Access Macros:
475  *
476  */
477 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_EMR_DATA0_VALUE register field. */
478 #define ALT_FPGAMGR_EMR_DATA0_VALUE_LSB 0
479 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_EMR_DATA0_VALUE register field. */
480 #define ALT_FPGAMGR_EMR_DATA0_VALUE_MSB 31
481 /* The width in bits of the ALT_FPGAMGR_EMR_DATA0_VALUE register field. */
482 #define ALT_FPGAMGR_EMR_DATA0_VALUE_WIDTH 32
483 /* The mask used to set the ALT_FPGAMGR_EMR_DATA0_VALUE register field value. */
484 #define ALT_FPGAMGR_EMR_DATA0_VALUE_SET_MSK 0xffffffff
485 /* The mask used to clear the ALT_FPGAMGR_EMR_DATA0_VALUE register field value. */
486 #define ALT_FPGAMGR_EMR_DATA0_VALUE_CLR_MSK 0x00000000
487 /* The reset value of the ALT_FPGAMGR_EMR_DATA0_VALUE register field. */
488 #define ALT_FPGAMGR_EMR_DATA0_VALUE_RESET 0x0
489 /* Extracts the ALT_FPGAMGR_EMR_DATA0_VALUE field value from a register. */
490 #define ALT_FPGAMGR_EMR_DATA0_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
491 /* Produces a ALT_FPGAMGR_EMR_DATA0_VALUE register field value suitable for setting the register. */
492 #define ALT_FPGAMGR_EMR_DATA0_VALUE_SET(value) (((value) << 0) & 0xffffffff)
493 
494 #ifndef __ASSEMBLY__
495 /*
496  * WARNING: The C register and register group struct declarations are provided for
497  * convenience and illustrative purposes. They should, however, be used with
498  * caution as the C language standard provides no guarantees about the alignment or
499  * atomicity of device memory accesses. The recommended practice for writing
500  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
501  * alt_write_word() functions.
502  *
503  * The struct declaration for register ALT_FPGAMGR_EMR_DATA0.
504  */
505 struct ALT_FPGAMGR_EMR_DATA0_s
506 {
507  const uint32_t value : 32; /* Value */
508 };
509 
510 /* The typedef declaration for register ALT_FPGAMGR_EMR_DATA0. */
511 typedef volatile struct ALT_FPGAMGR_EMR_DATA0_s ALT_FPGAMGR_EMR_DATA0_t;
512 #endif /* __ASSEMBLY__ */
513 
514 /* The reset value of the ALT_FPGAMGR_EMR_DATA0 register. */
515 #define ALT_FPGAMGR_EMR_DATA0_RESET 0x00000000
516 /* The byte offset of the ALT_FPGAMGR_EMR_DATA0 register from the beginning of the component. */
517 #define ALT_FPGAMGR_EMR_DATA0_OFST 0x30
518 
519 /*
520  * Register : Extracted EMR register content - emr_data1
521  *
522  * bits [63:32] of EMR register
523  *
524  * Register Layout
525  *
526  * Bits | Access | Reset | Description
527  * :-------|:-------|:------|:------------
528  * [31:0] | R | 0x0 | Value
529  *
530  */
531 /*
532  * Field : Value - value
533  *
534  * EMR register bits
535  *
536  * Field Access Macros:
537  *
538  */
539 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_EMR_DATA1_VALUE register field. */
540 #define ALT_FPGAMGR_EMR_DATA1_VALUE_LSB 0
541 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_EMR_DATA1_VALUE register field. */
542 #define ALT_FPGAMGR_EMR_DATA1_VALUE_MSB 31
543 /* The width in bits of the ALT_FPGAMGR_EMR_DATA1_VALUE register field. */
544 #define ALT_FPGAMGR_EMR_DATA1_VALUE_WIDTH 32
545 /* The mask used to set the ALT_FPGAMGR_EMR_DATA1_VALUE register field value. */
546 #define ALT_FPGAMGR_EMR_DATA1_VALUE_SET_MSK 0xffffffff
547 /* The mask used to clear the ALT_FPGAMGR_EMR_DATA1_VALUE register field value. */
548 #define ALT_FPGAMGR_EMR_DATA1_VALUE_CLR_MSK 0x00000000
549 /* The reset value of the ALT_FPGAMGR_EMR_DATA1_VALUE register field. */
550 #define ALT_FPGAMGR_EMR_DATA1_VALUE_RESET 0x0
551 /* Extracts the ALT_FPGAMGR_EMR_DATA1_VALUE field value from a register. */
552 #define ALT_FPGAMGR_EMR_DATA1_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
553 /* Produces a ALT_FPGAMGR_EMR_DATA1_VALUE register field value suitable for setting the register. */
554 #define ALT_FPGAMGR_EMR_DATA1_VALUE_SET(value) (((value) << 0) & 0xffffffff)
555 
556 #ifndef __ASSEMBLY__
557 /*
558  * WARNING: The C register and register group struct declarations are provided for
559  * convenience and illustrative purposes. They should, however, be used with
560  * caution as the C language standard provides no guarantees about the alignment or
561  * atomicity of device memory accesses. The recommended practice for writing
562  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
563  * alt_write_word() functions.
564  *
565  * The struct declaration for register ALT_FPGAMGR_EMR_DATA1.
566  */
567 struct ALT_FPGAMGR_EMR_DATA1_s
568 {
569  const uint32_t value : 32; /* Value */
570 };
571 
572 /* The typedef declaration for register ALT_FPGAMGR_EMR_DATA1. */
573 typedef volatile struct ALT_FPGAMGR_EMR_DATA1_s ALT_FPGAMGR_EMR_DATA1_t;
574 #endif /* __ASSEMBLY__ */
575 
576 /* The reset value of the ALT_FPGAMGR_EMR_DATA1 register. */
577 #define ALT_FPGAMGR_EMR_DATA1_RESET 0x00000000
578 /* The byte offset of the ALT_FPGAMGR_EMR_DATA1 register from the beginning of the component. */
579 #define ALT_FPGAMGR_EMR_DATA1_OFST 0x34
580 
581 /*
582  * Register : emr_data2
583  *
584  * bits [95:64] of EMR register
585  *
586  * Register Layout
587  *
588  * Bits | Access | Reset | Description
589  * :-------|:-------|:--------|:------------
590  * [31:0] | R | Unknown | Value
591  *
592  */
593 /*
594  * Field : Value - value
595  *
596  * EMR register bits
597  *
598  * Field Access Macros:
599  *
600  */
601 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_EMR_DATA2_VALUE register field. */
602 #define ALT_FPGAMGR_EMR_DATA2_VALUE_LSB 0
603 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_EMR_DATA2_VALUE register field. */
604 #define ALT_FPGAMGR_EMR_DATA2_VALUE_MSB 31
605 /* The width in bits of the ALT_FPGAMGR_EMR_DATA2_VALUE register field. */
606 #define ALT_FPGAMGR_EMR_DATA2_VALUE_WIDTH 32
607 /* The mask used to set the ALT_FPGAMGR_EMR_DATA2_VALUE register field value. */
608 #define ALT_FPGAMGR_EMR_DATA2_VALUE_SET_MSK 0xffffffff
609 /* The mask used to clear the ALT_FPGAMGR_EMR_DATA2_VALUE register field value. */
610 #define ALT_FPGAMGR_EMR_DATA2_VALUE_CLR_MSK 0x00000000
611 /* The reset value of the ALT_FPGAMGR_EMR_DATA2_VALUE register field is UNKNOWN. */
612 #define ALT_FPGAMGR_EMR_DATA2_VALUE_RESET 0x0
613 /* Extracts the ALT_FPGAMGR_EMR_DATA2_VALUE field value from a register. */
614 #define ALT_FPGAMGR_EMR_DATA2_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
615 /* Produces a ALT_FPGAMGR_EMR_DATA2_VALUE register field value suitable for setting the register. */
616 #define ALT_FPGAMGR_EMR_DATA2_VALUE_SET(value) (((value) << 0) & 0xffffffff)
617 
618 #ifndef __ASSEMBLY__
619 /*
620  * WARNING: The C register and register group struct declarations are provided for
621  * convenience and illustrative purposes. They should, however, be used with
622  * caution as the C language standard provides no guarantees about the alignment or
623  * atomicity of device memory accesses. The recommended practice for writing
624  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
625  * alt_write_word() functions.
626  *
627  * The struct declaration for register ALT_FPGAMGR_EMR_DATA2.
628  */
629 struct ALT_FPGAMGR_EMR_DATA2_s
630 {
631  const uint32_t value : 32; /* Value */
632 };
633 
634 /* The typedef declaration for register ALT_FPGAMGR_EMR_DATA2. */
635 typedef volatile struct ALT_FPGAMGR_EMR_DATA2_s ALT_FPGAMGR_EMR_DATA2_t;
636 #endif /* __ASSEMBLY__ */
637 
638 /* The reset value of the ALT_FPGAMGR_EMR_DATA2 register. */
639 #define ALT_FPGAMGR_EMR_DATA2_RESET 0x00000000
640 /* The byte offset of the ALT_FPGAMGR_EMR_DATA2 register from the beginning of the component. */
641 #define ALT_FPGAMGR_EMR_DATA2_OFST 0x38
642 
643 /*
644  * Register : emr_data3
645  *
646  * bits [119:96] of EMR register
647  *
648  * Register Layout
649  *
650  * Bits | Access | Reset | Description
651  * :-------|:-------|:--------|:------------
652  * [31:0] | R | Unknown | Value
653  *
654  */
655 /*
656  * Field : Value - value
657  *
658  * EMR register bits
659  *
660  * Field Access Macros:
661  *
662  */
663 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_EMR_DATA3_VALUE register field. */
664 #define ALT_FPGAMGR_EMR_DATA3_VALUE_LSB 0
665 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_EMR_DATA3_VALUE register field. */
666 #define ALT_FPGAMGR_EMR_DATA3_VALUE_MSB 31
667 /* The width in bits of the ALT_FPGAMGR_EMR_DATA3_VALUE register field. */
668 #define ALT_FPGAMGR_EMR_DATA3_VALUE_WIDTH 32
669 /* The mask used to set the ALT_FPGAMGR_EMR_DATA3_VALUE register field value. */
670 #define ALT_FPGAMGR_EMR_DATA3_VALUE_SET_MSK 0xffffffff
671 /* The mask used to clear the ALT_FPGAMGR_EMR_DATA3_VALUE register field value. */
672 #define ALT_FPGAMGR_EMR_DATA3_VALUE_CLR_MSK 0x00000000
673 /* The reset value of the ALT_FPGAMGR_EMR_DATA3_VALUE register field is UNKNOWN. */
674 #define ALT_FPGAMGR_EMR_DATA3_VALUE_RESET 0x0
675 /* Extracts the ALT_FPGAMGR_EMR_DATA3_VALUE field value from a register. */
676 #define ALT_FPGAMGR_EMR_DATA3_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
677 /* Produces a ALT_FPGAMGR_EMR_DATA3_VALUE register field value suitable for setting the register. */
678 #define ALT_FPGAMGR_EMR_DATA3_VALUE_SET(value) (((value) << 0) & 0xffffffff)
679 
680 #ifndef __ASSEMBLY__
681 /*
682  * WARNING: The C register and register group struct declarations are provided for
683  * convenience and illustrative purposes. They should, however, be used with
684  * caution as the C language standard provides no guarantees about the alignment or
685  * atomicity of device memory accesses. The recommended practice for writing
686  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
687  * alt_write_word() functions.
688  *
689  * The struct declaration for register ALT_FPGAMGR_EMR_DATA3.
690  */
691 struct ALT_FPGAMGR_EMR_DATA3_s
692 {
693  const uint32_t value : 32; /* Value */
694 };
695 
696 /* The typedef declaration for register ALT_FPGAMGR_EMR_DATA3. */
697 typedef volatile struct ALT_FPGAMGR_EMR_DATA3_s ALT_FPGAMGR_EMR_DATA3_t;
698 #endif /* __ASSEMBLY__ */
699 
700 /* The reset value of the ALT_FPGAMGR_EMR_DATA3 register. */
701 #define ALT_FPGAMGR_EMR_DATA3_RESET 0x00000000
702 /* The byte offset of the ALT_FPGAMGR_EMR_DATA3 register from the beginning of the component. */
703 #define ALT_FPGAMGR_EMR_DATA3_OFST 0x3c
704 
705 /*
706  * Register : emr_data4
707  *
708  * bits [159:128] of EMR register
709  *
710  * Register Layout
711  *
712  * Bits | Access | Reset | Description
713  * :-------|:-------|:--------|:------------
714  * [31:0] | R | Unknown | Value
715  *
716  */
717 /*
718  * Field : Value - value
719  *
720  * EMR register bits
721  *
722  * Field Access Macros:
723  *
724  */
725 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_EMR_DATA4_VALUE register field. */
726 #define ALT_FPGAMGR_EMR_DATA4_VALUE_LSB 0
727 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_EMR_DATA4_VALUE register field. */
728 #define ALT_FPGAMGR_EMR_DATA4_VALUE_MSB 31
729 /* The width in bits of the ALT_FPGAMGR_EMR_DATA4_VALUE register field. */
730 #define ALT_FPGAMGR_EMR_DATA4_VALUE_WIDTH 32
731 /* The mask used to set the ALT_FPGAMGR_EMR_DATA4_VALUE register field value. */
732 #define ALT_FPGAMGR_EMR_DATA4_VALUE_SET_MSK 0xffffffff
733 /* The mask used to clear the ALT_FPGAMGR_EMR_DATA4_VALUE register field value. */
734 #define ALT_FPGAMGR_EMR_DATA4_VALUE_CLR_MSK 0x00000000
735 /* The reset value of the ALT_FPGAMGR_EMR_DATA4_VALUE register field is UNKNOWN. */
736 #define ALT_FPGAMGR_EMR_DATA4_VALUE_RESET 0x0
737 /* Extracts the ALT_FPGAMGR_EMR_DATA4_VALUE field value from a register. */
738 #define ALT_FPGAMGR_EMR_DATA4_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
739 /* Produces a ALT_FPGAMGR_EMR_DATA4_VALUE register field value suitable for setting the register. */
740 #define ALT_FPGAMGR_EMR_DATA4_VALUE_SET(value) (((value) << 0) & 0xffffffff)
741 
742 #ifndef __ASSEMBLY__
743 /*
744  * WARNING: The C register and register group struct declarations are provided for
745  * convenience and illustrative purposes. They should, however, be used with
746  * caution as the C language standard provides no guarantees about the alignment or
747  * atomicity of device memory accesses. The recommended practice for writing
748  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
749  * alt_write_word() functions.
750  *
751  * The struct declaration for register ALT_FPGAMGR_EMR_DATA4.
752  */
753 struct ALT_FPGAMGR_EMR_DATA4_s
754 {
755  const uint32_t value : 32; /* Value */
756 };
757 
758 /* The typedef declaration for register ALT_FPGAMGR_EMR_DATA4. */
759 typedef volatile struct ALT_FPGAMGR_EMR_DATA4_s ALT_FPGAMGR_EMR_DATA4_t;
760 #endif /* __ASSEMBLY__ */
761 
762 /* The reset value of the ALT_FPGAMGR_EMR_DATA4 register. */
763 #define ALT_FPGAMGR_EMR_DATA4_RESET 0x00000000
764 /* The byte offset of the ALT_FPGAMGR_EMR_DATA4 register from the beginning of the component. */
765 #define ALT_FPGAMGR_EMR_DATA4_OFST 0x40
766 
767 /*
768  * Register : emr_data5
769  *
770  * bits [171:160] of EMR register
771  *
772  * Register Layout
773  *
774  * Bits | Access | Reset | Description
775  * :-------|:-------|:--------|:------------
776  * [31:0] | R | Unknown | Value
777  *
778  */
779 /*
780  * Field : Value - value
781  *
782  * EMR register bits
783  *
784  * Field Access Macros:
785  *
786  */
787 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_EMR_DATA5_VALUE register field. */
788 #define ALT_FPGAMGR_EMR_DATA5_VALUE_LSB 0
789 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_EMR_DATA5_VALUE register field. */
790 #define ALT_FPGAMGR_EMR_DATA5_VALUE_MSB 31
791 /* The width in bits of the ALT_FPGAMGR_EMR_DATA5_VALUE register field. */
792 #define ALT_FPGAMGR_EMR_DATA5_VALUE_WIDTH 32
793 /* The mask used to set the ALT_FPGAMGR_EMR_DATA5_VALUE register field value. */
794 #define ALT_FPGAMGR_EMR_DATA5_VALUE_SET_MSK 0xffffffff
795 /* The mask used to clear the ALT_FPGAMGR_EMR_DATA5_VALUE register field value. */
796 #define ALT_FPGAMGR_EMR_DATA5_VALUE_CLR_MSK 0x00000000
797 /* The reset value of the ALT_FPGAMGR_EMR_DATA5_VALUE register field is UNKNOWN. */
798 #define ALT_FPGAMGR_EMR_DATA5_VALUE_RESET 0x0
799 /* Extracts the ALT_FPGAMGR_EMR_DATA5_VALUE field value from a register. */
800 #define ALT_FPGAMGR_EMR_DATA5_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
801 /* Produces a ALT_FPGAMGR_EMR_DATA5_VALUE register field value suitable for setting the register. */
802 #define ALT_FPGAMGR_EMR_DATA5_VALUE_SET(value) (((value) << 0) & 0xffffffff)
803 
804 #ifndef __ASSEMBLY__
805 /*
806  * WARNING: The C register and register group struct declarations are provided for
807  * convenience and illustrative purposes. They should, however, be used with
808  * caution as the C language standard provides no guarantees about the alignment or
809  * atomicity of device memory accesses. The recommended practice for writing
810  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
811  * alt_write_word() functions.
812  *
813  * The struct declaration for register ALT_FPGAMGR_EMR_DATA5.
814  */
815 struct ALT_FPGAMGR_EMR_DATA5_s
816 {
817  const uint32_t value : 32; /* Value */
818 };
819 
820 /* The typedef declaration for register ALT_FPGAMGR_EMR_DATA5. */
821 typedef volatile struct ALT_FPGAMGR_EMR_DATA5_s ALT_FPGAMGR_EMR_DATA5_t;
822 #endif /* __ASSEMBLY__ */
823 
824 /* The reset value of the ALT_FPGAMGR_EMR_DATA5 register. */
825 #define ALT_FPGAMGR_EMR_DATA5_RESET 0x00000000
826 /* The byte offset of the ALT_FPGAMGR_EMR_DATA5 register from the beginning of the component. */
827 #define ALT_FPGAMGR_EMR_DATA5_OFST 0x44
828 
829 /*
830  * Register : emr_valid
831  *
832  * Register Layout
833  *
834  * Bits | Access | Reset | Description
835  * :-------|:-------|:------|:--------------------------
836  * [0] | RW | 0x0 | ALT_FPGAMGR_EMR_VALID_VLD
837  * [31:1] | ??? | 0x0 | *UNDEFINED*
838  *
839  */
840 /*
841  * Field : vld
842  *
843  * Field Access Macros:
844  *
845  */
846 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_EMR_VALID_VLD register field. */
847 #define ALT_FPGAMGR_EMR_VALID_VLD_LSB 0
848 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_EMR_VALID_VLD register field. */
849 #define ALT_FPGAMGR_EMR_VALID_VLD_MSB 0
850 /* The width in bits of the ALT_FPGAMGR_EMR_VALID_VLD register field. */
851 #define ALT_FPGAMGR_EMR_VALID_VLD_WIDTH 1
852 /* The mask used to set the ALT_FPGAMGR_EMR_VALID_VLD register field value. */
853 #define ALT_FPGAMGR_EMR_VALID_VLD_SET_MSK 0x00000001
854 /* The mask used to clear the ALT_FPGAMGR_EMR_VALID_VLD register field value. */
855 #define ALT_FPGAMGR_EMR_VALID_VLD_CLR_MSK 0xfffffffe
856 /* The reset value of the ALT_FPGAMGR_EMR_VALID_VLD register field. */
857 #define ALT_FPGAMGR_EMR_VALID_VLD_RESET 0x0
858 /* Extracts the ALT_FPGAMGR_EMR_VALID_VLD field value from a register. */
859 #define ALT_FPGAMGR_EMR_VALID_VLD_GET(value) (((value) & 0x00000001) >> 0)
860 /* Produces a ALT_FPGAMGR_EMR_VALID_VLD register field value suitable for setting the register. */
861 #define ALT_FPGAMGR_EMR_VALID_VLD_SET(value) (((value) << 0) & 0x00000001)
862 
863 #ifndef __ASSEMBLY__
864 /*
865  * WARNING: The C register and register group struct declarations are provided for
866  * convenience and illustrative purposes. They should, however, be used with
867  * caution as the C language standard provides no guarantees about the alignment or
868  * atomicity of device memory accesses. The recommended practice for writing
869  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
870  * alt_write_word() functions.
871  *
872  * The struct declaration for register ALT_FPGAMGR_EMR_VALID.
873  */
874 struct ALT_FPGAMGR_EMR_VALID_s
875 {
876  uint32_t vld : 1; /* ALT_FPGAMGR_EMR_VALID_VLD */
877  uint32_t : 31; /* *UNDEFINED* */
878 };
879 
880 /* The typedef declaration for register ALT_FPGAMGR_EMR_VALID. */
881 typedef volatile struct ALT_FPGAMGR_EMR_VALID_s ALT_FPGAMGR_EMR_VALID_t;
882 #endif /* __ASSEMBLY__ */
883 
884 /* The reset value of the ALT_FPGAMGR_EMR_VALID register. */
885 #define ALT_FPGAMGR_EMR_VALID_RESET 0x00000000
886 /* The byte offset of the ALT_FPGAMGR_EMR_VALID register from the beginning of the component. */
887 #define ALT_FPGAMGR_EMR_VALID_OFST 0x48
888 
889 /*
890  * Register : emr_en
891  *
892  * Register Layout
893  *
894  * Bits | Access | Reset | Description
895  * :-------|:-------|:-----------|:------------
896  * [0] | RW | 0x0 | EMR_EN
897  * [31:1] | ??? | 0x3b800000 | *UNDEFINED*
898  *
899  */
900 /*
901  * Field : EMR_EN - en
902  *
903  * Enable HPS EMR extraction from CSS.
904  *
905  * Field Access Macros:
906  *
907  */
908 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_EMR_EN_EN register field. */
909 #define ALT_FPGAMGR_EMR_EN_EN_LSB 0
910 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_EMR_EN_EN register field. */
911 #define ALT_FPGAMGR_EMR_EN_EN_MSB 0
912 /* The width in bits of the ALT_FPGAMGR_EMR_EN_EN register field. */
913 #define ALT_FPGAMGR_EMR_EN_EN_WIDTH 1
914 /* The mask used to set the ALT_FPGAMGR_EMR_EN_EN register field value. */
915 #define ALT_FPGAMGR_EMR_EN_EN_SET_MSK 0x00000001
916 /* The mask used to clear the ALT_FPGAMGR_EMR_EN_EN register field value. */
917 #define ALT_FPGAMGR_EMR_EN_EN_CLR_MSK 0xfffffffe
918 /* The reset value of the ALT_FPGAMGR_EMR_EN_EN register field. */
919 #define ALT_FPGAMGR_EMR_EN_EN_RESET 0x0
920 /* Extracts the ALT_FPGAMGR_EMR_EN_EN field value from a register. */
921 #define ALT_FPGAMGR_EMR_EN_EN_GET(value) (((value) & 0x00000001) >> 0)
922 /* Produces a ALT_FPGAMGR_EMR_EN_EN register field value suitable for setting the register. */
923 #define ALT_FPGAMGR_EMR_EN_EN_SET(value) (((value) << 0) & 0x00000001)
924 
925 #ifndef __ASSEMBLY__
926 /*
927  * WARNING: The C register and register group struct declarations are provided for
928  * convenience and illustrative purposes. They should, however, be used with
929  * caution as the C language standard provides no guarantees about the alignment or
930  * atomicity of device memory accesses. The recommended practice for writing
931  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
932  * alt_write_word() functions.
933  *
934  * The struct declaration for register ALT_FPGAMGR_EMR_EN.
935  */
936 struct ALT_FPGAMGR_EMR_EN_s
937 {
938  uint32_t en : 1; /* EMR_EN */
939  uint32_t : 31; /* *UNDEFINED* */
940 };
941 
942 /* The typedef declaration for register ALT_FPGAMGR_EMR_EN. */
943 typedef volatile struct ALT_FPGAMGR_EMR_EN_s ALT_FPGAMGR_EMR_EN_t;
944 #endif /* __ASSEMBLY__ */
945 
946 /* The reset value of the ALT_FPGAMGR_EMR_EN register. */
947 #define ALT_FPGAMGR_EMR_EN_RESET 0x77000000
948 /* The byte offset of the ALT_FPGAMGR_EMR_EN register from the beginning of the component. */
949 #define ALT_FPGAMGR_EMR_EN_OFST 0x4c
950 
951 /*
952  * Register : Scan-Chain Enable Register - jtag_config
953  *
954  * This register is used to configure the JTAG master interface.
955  *
956  * It is recommended that software write this register before initiating a
957  * transfer.
958  *
959  * If the software writes to this register while an active session is in progress
960  * (as indicated by jtag_status.SessionStatus), the expected behavior is
961  * "undefined".
962  *
963  * Register Layout
964  *
965  * Bits | Access | Reset | Description
966  * :--------|:-------|:------|:----------------------------
967  * [0] | RW | 0x0 | Jtag Host Enable
968  * [1] | RW | 0x0 | Jtag Port Enable
969  * [2] | RW | 0x0 | Loop Back Enable
970  * [3] | ??? | 0x0 | *UNDEFINED*
971  * [4] | RW | 0x0 | ALT_FPGAMGR_JTAG_CFG_TRSTEN
972  * [7:5] | ??? | 0x0 | *UNDEFINED*
973  * [15:8] | RW | 0x14 | TCK Divide Ratio
974  * [31:16] | RW | 0x0 | Number of TX bits
975  *
976  */
977 /*
978  * Field : Jtag Host Enable - JtagHostEn
979  *
980  * This bit field drives the enable signal to the FPGA CSS. Please note that this
981  * enable should be driven long before you start any JTAG transactions.
982  *
983  * Field Enumeration Values:
984  *
985  * Enum | Value | Description
986  * :--------------------------------------|:------|:-------------------
987  * ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_E_DIS | 0x0 | Disable scan-chain
988  * ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_E_EN | 0x1 | Enable scan-chain
989  *
990  * Field Access Macros:
991  *
992  */
993 /*
994  * Enumerated value for register field ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN
995  *
996  * Disable scan-chain
997  */
998 #define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_E_DIS 0x0
999 /*
1000  * Enumerated value for register field ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN
1001  *
1002  * Enable scan-chain
1003  */
1004 #define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_E_EN 0x1
1005 
1006 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN register field. */
1007 #define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_LSB 0
1008 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN register field. */
1009 #define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_MSB 0
1010 /* The width in bits of the ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN register field. */
1011 #define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_WIDTH 1
1012 /* The mask used to set the ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN register field value. */
1013 #define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_SET_MSK 0x00000001
1014 /* The mask used to clear the ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN register field value. */
1015 #define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_CLR_MSK 0xfffffffe
1016 /* The reset value of the ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN register field. */
1017 #define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_RESET 0x0
1018 /* Extracts the ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN field value from a register. */
1019 #define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_GET(value) (((value) & 0x00000001) >> 0)
1020 /* Produces a ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN register field value suitable for setting the register. */
1021 #define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_SET(value) (((value) << 0) & 0x00000001)
1022 
1023 /*
1024  * Field : Jtag Port Enable - jtagPortEn
1025  *
1026  * This bit field gates off TDI/TMS/TCK driven to the FPGA CSS interface. This
1027  * allows the software to take over JTAG but keep them tied low. If this bit is 0
1028  * the internal core logic will still be active and all the status will be updated
1029  * as in regular operation.
1030  *
1031  * Field Enumeration Values:
1032  *
1033  * Enum | Value | Description
1034  * :--------------------------------------|:------|:-------------------
1035  * ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_E_DIS | 0x0 | Disable scan-chain
1036  * ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_E_EN | 0x1 | Enable scan-chain
1037  *
1038  * Field Access Macros:
1039  *
1040  */
1041 /*
1042  * Enumerated value for register field ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN
1043  *
1044  * Disable scan-chain
1045  */
1046 #define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_E_DIS 0x0
1047 /*
1048  * Enumerated value for register field ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN
1049  *
1050  * Enable scan-chain
1051  */
1052 #define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_E_EN 0x1
1053 
1054 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN register field. */
1055 #define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_LSB 1
1056 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN register field. */
1057 #define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_MSB 1
1058 /* The width in bits of the ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN register field. */
1059 #define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_WIDTH 1
1060 /* The mask used to set the ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN register field value. */
1061 #define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_SET_MSK 0x00000002
1062 /* The mask used to clear the ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN register field value. */
1063 #define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_CLR_MSK 0xfffffffd
1064 /* The reset value of the ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN register field. */
1065 #define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_RESET 0x0
1066 /* Extracts the ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN field value from a register. */
1067 #define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_GET(value) (((value) & 0x00000002) >> 1)
1068 /* Produces a ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN register field value suitable for setting the register. */
1069 #define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_SET(value) (((value) << 1) & 0x00000002)
1070 
1071 /*
1072  * Field : Loop Back Enable - loopBackEn
1073  *
1074  * Enables the internal loopback mode. A typical scenario will be to set
1075  * JtagHostEn=0, JtagPortEn=0, and then initiate transmits by software writes to
1076  * TXFifo. All transfers should receive back on RxFifo. Also this should not affect
1077  * anything external, since the Jtag ports will be gated off.
1078  *
1079  * Field Enumeration Values:
1080  *
1081  * Enum | Value | Description
1082  * :--------------------------------------|:------|:-------------------
1083  * ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_E_DIS | 0x0 | Disable scan-chain
1084  * ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_E_EN | 0x1 | Enable scan-chain
1085  *
1086  * Field Access Macros:
1087  *
1088  */
1089 /*
1090  * Enumerated value for register field ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN
1091  *
1092  * Disable scan-chain
1093  */
1094 #define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_E_DIS 0x0
1095 /*
1096  * Enumerated value for register field ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN
1097  *
1098  * Enable scan-chain
1099  */
1100 #define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_E_EN 0x1
1101 
1102 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN register field. */
1103 #define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_LSB 2
1104 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN register field. */
1105 #define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_MSB 2
1106 /* The width in bits of the ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN register field. */
1107 #define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_WIDTH 1
1108 /* The mask used to set the ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN register field value. */
1109 #define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_SET_MSK 0x00000004
1110 /* The mask used to clear the ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN register field value. */
1111 #define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_CLR_MSK 0xfffffffb
1112 /* The reset value of the ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN register field. */
1113 #define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_RESET 0x0
1114 /* Extracts the ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN field value from a register. */
1115 #define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_GET(value) (((value) & 0x00000004) >> 2)
1116 /* Produces a ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN register field value suitable for setting the register. */
1117 #define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_SET(value) (((value) << 2) & 0x00000004)
1118 
1119 /*
1120  * Field : trstEn
1121  *
1122  * Set this bit and then writing at least 1 data in jtag_data_w will cause a JTAG
1123  * reset to happen. Please note that writing TRSTEN while a data transmission is
1124  * undergoing could cause undesired effects, so it is recommended that software
1125  * poll the SESSIONSTATUS bit to make sure there is no existing transfers before
1126  * writing TRSTEN. Software should manually write 0 to this bit after the
1127  * completion of the reset and after the SESSIONSTATUS is inactive.
1128  *
1129  * Field Access Macros:
1130  *
1131  */
1132 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_CFG_TRSTEN register field. */
1133 #define ALT_FPGAMGR_JTAG_CFG_TRSTEN_LSB 4
1134 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_CFG_TRSTEN register field. */
1135 #define ALT_FPGAMGR_JTAG_CFG_TRSTEN_MSB 4
1136 /* The width in bits of the ALT_FPGAMGR_JTAG_CFG_TRSTEN register field. */
1137 #define ALT_FPGAMGR_JTAG_CFG_TRSTEN_WIDTH 1
1138 /* The mask used to set the ALT_FPGAMGR_JTAG_CFG_TRSTEN register field value. */
1139 #define ALT_FPGAMGR_JTAG_CFG_TRSTEN_SET_MSK 0x00000010
1140 /* The mask used to clear the ALT_FPGAMGR_JTAG_CFG_TRSTEN register field value. */
1141 #define ALT_FPGAMGR_JTAG_CFG_TRSTEN_CLR_MSK 0xffffffef
1142 /* The reset value of the ALT_FPGAMGR_JTAG_CFG_TRSTEN register field. */
1143 #define ALT_FPGAMGR_JTAG_CFG_TRSTEN_RESET 0x0
1144 /* Extracts the ALT_FPGAMGR_JTAG_CFG_TRSTEN field value from a register. */
1145 #define ALT_FPGAMGR_JTAG_CFG_TRSTEN_GET(value) (((value) & 0x00000010) >> 4)
1146 /* Produces a ALT_FPGAMGR_JTAG_CFG_TRSTEN register field value suitable for setting the register. */
1147 #define ALT_FPGAMGR_JTAG_CFG_TRSTEN_SET(value) (((value) << 4) & 0x00000010)
1148 
1149 /*
1150  * Field : TCK Divide Ratio - tckRatio
1151  *
1152  * Ratio of TCK division. The FPGA manager clock is 100MHz.
1153  *
1154  * value of 4 provides a 25MHz TCK
1155  *
1156  * value of 20 (0x14) provides a 5MHz TCK.
1157  *
1158  * Maximum supported TCK frequency is 25MHz.
1159  *
1160  * So writing a value less than 4 to this field will cause unexpected behavior.
1161  *
1162  * Field Access Macros:
1163  *
1164  */
1165 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_CFG_TCKRATIO register field. */
1166 #define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_LSB 8
1167 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_CFG_TCKRATIO register field. */
1168 #define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_MSB 15
1169 /* The width in bits of the ALT_FPGAMGR_JTAG_CFG_TCKRATIO register field. */
1170 #define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_WIDTH 8
1171 /* The mask used to set the ALT_FPGAMGR_JTAG_CFG_TCKRATIO register field value. */
1172 #define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_SET_MSK 0x0000ff00
1173 /* The mask used to clear the ALT_FPGAMGR_JTAG_CFG_TCKRATIO register field value. */
1174 #define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_CLR_MSK 0xffff00ff
1175 /* The reset value of the ALT_FPGAMGR_JTAG_CFG_TCKRATIO register field. */
1176 #define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_RESET 0x14
1177 /* Extracts the ALT_FPGAMGR_JTAG_CFG_TCKRATIO field value from a register. */
1178 #define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_GET(value) (((value) & 0x0000ff00) >> 8)
1179 /* Produces a ALT_FPGAMGR_JTAG_CFG_TCKRATIO register field value suitable for setting the register. */
1180 #define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_SET(value) (((value) << 8) & 0x0000ff00)
1181 
1182 /*
1183  * Field : Number of TX bits - txSize
1184  *
1185  * Defines the number of bits to be transmitted. Once the software kicks of the
1186  * transfer via Start_Transfer bits, the hardware will stop the transfer, when
1187  * either of the below conditions are reached.
1188  *
1189  * a) Completed a transfer of programmed Number of TX Bits +1.
1190  *
1191  * b) TxFifo became empty (under-run of TxFifo).
1192  *
1193  * c) A Stop Transfer request received from software.
1194  *
1195  * So for a successful transfer of fixed number of bits, software has to make sure
1196  * continuous flow of data.
1197  *
1198  * The exact number of bits to be transferred in the current session is 1+ the
1199  * value in this register field.
1200  *
1201  * For example
1202  *
1203  * 0 -> 1 bit to be transmitted once start session is triggered.
1204  *
1205  * 1-> 2 bits to be transmitted.once start session is triggered.
1206  *
1207  * Field Access Macros:
1208  *
1209  */
1210 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_CFG_TXSIZE register field. */
1211 #define ALT_FPGAMGR_JTAG_CFG_TXSIZE_LSB 16
1212 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_CFG_TXSIZE register field. */
1213 #define ALT_FPGAMGR_JTAG_CFG_TXSIZE_MSB 31
1214 /* The width in bits of the ALT_FPGAMGR_JTAG_CFG_TXSIZE register field. */
1215 #define ALT_FPGAMGR_JTAG_CFG_TXSIZE_WIDTH 16
1216 /* The mask used to set the ALT_FPGAMGR_JTAG_CFG_TXSIZE register field value. */
1217 #define ALT_FPGAMGR_JTAG_CFG_TXSIZE_SET_MSK 0xffff0000
1218 /* The mask used to clear the ALT_FPGAMGR_JTAG_CFG_TXSIZE register field value. */
1219 #define ALT_FPGAMGR_JTAG_CFG_TXSIZE_CLR_MSK 0x0000ffff
1220 /* The reset value of the ALT_FPGAMGR_JTAG_CFG_TXSIZE register field. */
1221 #define ALT_FPGAMGR_JTAG_CFG_TXSIZE_RESET 0x0
1222 /* Extracts the ALT_FPGAMGR_JTAG_CFG_TXSIZE field value from a register. */
1223 #define ALT_FPGAMGR_JTAG_CFG_TXSIZE_GET(value) (((value) & 0xffff0000) >> 16)
1224 /* Produces a ALT_FPGAMGR_JTAG_CFG_TXSIZE register field value suitable for setting the register. */
1225 #define ALT_FPGAMGR_JTAG_CFG_TXSIZE_SET(value) (((value) << 16) & 0xffff0000)
1226 
1227 #ifndef __ASSEMBLY__
1228 /*
1229  * WARNING: The C register and register group struct declarations are provided for
1230  * convenience and illustrative purposes. They should, however, be used with
1231  * caution as the C language standard provides no guarantees about the alignment or
1232  * atomicity of device memory accesses. The recommended practice for writing
1233  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1234  * alt_write_word() functions.
1235  *
1236  * The struct declaration for register ALT_FPGAMGR_JTAG_CFG.
1237  */
1238 struct ALT_FPGAMGR_JTAG_CFG_s
1239 {
1240  uint32_t JtagHostEn : 1; /* Jtag Host Enable */
1241  uint32_t jtagPortEn : 1; /* Jtag Port Enable */
1242  uint32_t loopBackEn : 1; /* Loop Back Enable */
1243  uint32_t : 1; /* *UNDEFINED* */
1244  uint32_t trstEn : 1; /* ALT_FPGAMGR_JTAG_CFG_TRSTEN */
1245  uint32_t : 3; /* *UNDEFINED* */
1246  uint32_t tckRatio : 8; /* TCK Divide Ratio */
1247  uint32_t txSize : 16; /* Number of TX bits */
1248 };
1249 
1250 /* The typedef declaration for register ALT_FPGAMGR_JTAG_CFG. */
1251 typedef volatile struct ALT_FPGAMGR_JTAG_CFG_s ALT_FPGAMGR_JTAG_CFG_t;
1252 #endif /* __ASSEMBLY__ */
1253 
1254 /* The reset value of the ALT_FPGAMGR_JTAG_CFG register. */
1255 #define ALT_FPGAMGR_JTAG_CFG_RESET 0x00001400
1256 /* The byte offset of the ALT_FPGAMGR_JTAG_CFG register from the beginning of the component. */
1257 #define ALT_FPGAMGR_JTAG_CFG_OFST 0x50
1258 
1259 /*
1260  * Register : Control/Status Word Register - jtag_status
1261  *
1262  * status of the currently ongoing JTAG transmit or receive
1263  *
1264  * Register Layout
1265  *
1266  * Bits | Access | Reset | Description
1267  * :--------|:-------|:--------|:-------------------------------
1268  * [3:0] | RW | 0x0 | Current Tx Fifo level
1269  * [7:4] | RW | 0x0 | Current RX FIFO Level
1270  * [8] | RW | 0x1 | Tx Fifo Empty Status
1271  * [9] | RW | 0x0 | Tx Fifo Full Status
1272  * [10] | RW | 0x1 | Rx Fifo Empty Status
1273  * [11] | RW | 0x0 | Rx Fifo Full Status
1274  * [14:12] | ??? | 0x0 | *UNDEFINED*
1275  * [15] | RW | 0x0 | Valid Ongoing Transfer Session
1276  * [31:16] | RW | Unknown | Number of bits Transmitted
1277  *
1278  */
1279 /*
1280  * Field : Current Tx Fifo level - txFifoLevel
1281  *
1282  * Number of words remaining in Tx Fifo.
1283  *
1284  * Maximum value is 0x8
1285  *
1286  * Field Access Macros:
1287  *
1288  */
1289 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL register field. */
1290 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_LSB 0
1291 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL register field. */
1292 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_MSB 3
1293 /* The width in bits of the ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL register field. */
1294 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_WIDTH 4
1295 /* The mask used to set the ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL register field value. */
1296 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_SET_MSK 0x0000000f
1297 /* The mask used to clear the ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL register field value. */
1298 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_CLR_MSK 0xfffffff0
1299 /* The reset value of the ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL register field. */
1300 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_RESET 0x0
1301 /* Extracts the ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL field value from a register. */
1302 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_GET(value) (((value) & 0x0000000f) >> 0)
1303 /* Produces a ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL register field value suitable for setting the register. */
1304 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_SET(value) (((value) << 0) & 0x0000000f)
1305 
1306 /*
1307  * Field : Current RX FIFO Level - rxFifoLevel
1308  *
1309  * Number of Words remaining in the Rx Fifo.
1310  *
1311  * Maximum value is 0x8
1312  *
1313  * Field Access Macros:
1314  *
1315  */
1316 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL register field. */
1317 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_LSB 4
1318 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL register field. */
1319 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_MSB 7
1320 /* The width in bits of the ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL register field. */
1321 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_WIDTH 4
1322 /* The mask used to set the ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL register field value. */
1323 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_SET_MSK 0x000000f0
1324 /* The mask used to clear the ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL register field value. */
1325 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_CLR_MSK 0xffffff0f
1326 /* The reset value of the ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL register field. */
1327 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_RESET 0x0
1328 /* Extracts the ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL field value from a register. */
1329 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_GET(value) (((value) & 0x000000f0) >> 4)
1330 /* Produces a ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL register field value suitable for setting the register. */
1331 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_SET(value) (((value) << 4) & 0x000000f0)
1332 
1333 /*
1334  * Field : Tx Fifo Empty Status - txFifoEmpty
1335  *
1336  * Read
1337  *
1338  * 1 -> Tx Fifo Empty
1339  *
1340  * 0 -> Tx Fifo NOT Empty
1341  *
1342  * Field Access Macros:
1343  *
1344  */
1345 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY register field. */
1346 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_LSB 8
1347 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY register field. */
1348 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_MSB 8
1349 /* The width in bits of the ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY register field. */
1350 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_WIDTH 1
1351 /* The mask used to set the ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY register field value. */
1352 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_SET_MSK 0x00000100
1353 /* The mask used to clear the ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY register field value. */
1354 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_CLR_MSK 0xfffffeff
1355 /* The reset value of the ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY register field. */
1356 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_RESET 0x1
1357 /* Extracts the ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY field value from a register. */
1358 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_GET(value) (((value) & 0x00000100) >> 8)
1359 /* Produces a ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY register field value suitable for setting the register. */
1360 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_SET(value) (((value) << 8) & 0x00000100)
1361 
1362 /*
1363  * Field : Tx Fifo Full Status - txFifoFull
1364  *
1365  * Read
1366  *
1367  * 1 -> Tx Fifo Full
1368  *
1369  * 0 -> Tx Fifo NOT full
1370  *
1371  * Field Access Macros:
1372  *
1373  */
1374 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL register field. */
1375 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_LSB 9
1376 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL register field. */
1377 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_MSB 9
1378 /* The width in bits of the ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL register field. */
1379 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_WIDTH 1
1380 /* The mask used to set the ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL register field value. */
1381 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_SET_MSK 0x00000200
1382 /* The mask used to clear the ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL register field value. */
1383 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_CLR_MSK 0xfffffdff
1384 /* The reset value of the ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL register field. */
1385 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_RESET 0x0
1386 /* Extracts the ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL field value from a register. */
1387 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_GET(value) (((value) & 0x00000200) >> 9)
1388 /* Produces a ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL register field value suitable for setting the register. */
1389 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_SET(value) (((value) << 9) & 0x00000200)
1390 
1391 /*
1392  * Field : Rx Fifo Empty Status - rxFifoEmpty
1393  *
1394  * Read
1395  *
1396  * 1 -> Rx Fifo Empty
1397  *
1398  * 0 -> Rx Fifo NOT Empty
1399  *
1400  * Field Access Macros:
1401  *
1402  */
1403 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY register field. */
1404 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_LSB 10
1405 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY register field. */
1406 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_MSB 10
1407 /* The width in bits of the ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY register field. */
1408 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_WIDTH 1
1409 /* The mask used to set the ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY register field value. */
1410 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_SET_MSK 0x00000400
1411 /* The mask used to clear the ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY register field value. */
1412 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_CLR_MSK 0xfffffbff
1413 /* The reset value of the ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY register field. */
1414 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_RESET 0x1
1415 /* Extracts the ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY field value from a register. */
1416 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_GET(value) (((value) & 0x00000400) >> 10)
1417 /* Produces a ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY register field value suitable for setting the register. */
1418 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_SET(value) (((value) << 10) & 0x00000400)
1419 
1420 /*
1421  * Field : Rx Fifo Full Status - rxFifoFull
1422  *
1423  * Read
1424  *
1425  * 1 -> Rx Fifo Full
1426  *
1427  * 0 -> Rx Fifo NOT full
1428  *
1429  * Field Access Macros:
1430  *
1431  */
1432 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL register field. */
1433 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_LSB 11
1434 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL register field. */
1435 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_MSB 11
1436 /* The width in bits of the ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL register field. */
1437 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_WIDTH 1
1438 /* The mask used to set the ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL register field value. */
1439 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_SET_MSK 0x00000800
1440 /* The mask used to clear the ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL register field value. */
1441 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_CLR_MSK 0xfffff7ff
1442 /* The reset value of the ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL register field. */
1443 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_RESET 0x0
1444 /* Extracts the ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL field value from a register. */
1445 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_GET(value) (((value) & 0x00000800) >> 11)
1446 /* Produces a ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL register field value suitable for setting the register. */
1447 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_SET(value) (((value) << 11) & 0x00000800)
1448 
1449 /*
1450  * Field : Valid Ongoing Transfer Session - SessionStatus
1451  *
1452  * A read of 1 indicates that there is an ongoing transfer session.
1453  *
1454  * A read of 0 indicates that there is no ongoing transfer session.
1455  *
1456  * Field Enumeration Values:
1457  *
1458  * Enum | Value | Description
1459  * :----------------------------------------|:------|:-------------------
1460  * ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_E_DIS | 0x0 | Disable scan-chain
1461  * ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_E_EN | 0x1 | Enable scan-chain
1462  *
1463  * Field Access Macros:
1464  *
1465  */
1466 /*
1467  * Enumerated value for register field ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT
1468  *
1469  * Disable scan-chain
1470  */
1471 #define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_E_DIS 0x0
1472 /*
1473  * Enumerated value for register field ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT
1474  *
1475  * Enable scan-chain
1476  */
1477 #define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_E_EN 0x1
1478 
1479 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT register field. */
1480 #define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_LSB 15
1481 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT register field. */
1482 #define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_MSB 15
1483 /* The width in bits of the ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT register field. */
1484 #define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_WIDTH 1
1485 /* The mask used to set the ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT register field value. */
1486 #define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_SET_MSK 0x00008000
1487 /* The mask used to clear the ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT register field value. */
1488 #define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_CLR_MSK 0xffff7fff
1489 /* The reset value of the ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT register field. */
1490 #define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_RESET 0x0
1491 /* Extracts the ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT field value from a register. */
1492 #define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_GET(value) (((value) & 0x00008000) >> 15)
1493 /* Produces a ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT register field value suitable for setting the register. */
1494 #define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_SET(value) (((value) << 15) & 0x00008000)
1495 
1496 /*
1497  * Field : Number of bits Transmitted - txDoneSize
1498  *
1499  * Total Number of Successful bits transferred in the current session.
1500  *
1501  * The exact number of bits transferred in the current session is 1+ the value in
1502  * this register.
1503  *
1504  * For example
1505  *
1506  * 0 -> 1 bit completed transmit or in the process of transmitting.
1507  *
1508  * 1-> 2 bits completed transmit or in the process of transmitting.
1509  *
1510  * Field Access Macros:
1511  *
1512  */
1513 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_STAT_TXDONESIZE register field. */
1514 #define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_LSB 16
1515 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_STAT_TXDONESIZE register field. */
1516 #define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_MSB 31
1517 /* The width in bits of the ALT_FPGAMGR_JTAG_STAT_TXDONESIZE register field. */
1518 #define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_WIDTH 16
1519 /* The mask used to set the ALT_FPGAMGR_JTAG_STAT_TXDONESIZE register field value. */
1520 #define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_SET_MSK 0xffff0000
1521 /* The mask used to clear the ALT_FPGAMGR_JTAG_STAT_TXDONESIZE register field value. */
1522 #define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_CLR_MSK 0x0000ffff
1523 /* The reset value of the ALT_FPGAMGR_JTAG_STAT_TXDONESIZE register field is UNKNOWN. */
1524 #define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_RESET 0x0
1525 /* Extracts the ALT_FPGAMGR_JTAG_STAT_TXDONESIZE field value from a register. */
1526 #define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_GET(value) (((value) & 0xffff0000) >> 16)
1527 /* Produces a ALT_FPGAMGR_JTAG_STAT_TXDONESIZE register field value suitable for setting the register. */
1528 #define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_SET(value) (((value) << 16) & 0xffff0000)
1529 
1530 #ifndef __ASSEMBLY__
1531 /*
1532  * WARNING: The C register and register group struct declarations are provided for
1533  * convenience and illustrative purposes. They should, however, be used with
1534  * caution as the C language standard provides no guarantees about the alignment or
1535  * atomicity of device memory accesses. The recommended practice for writing
1536  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1537  * alt_write_word() functions.
1538  *
1539  * The struct declaration for register ALT_FPGAMGR_JTAG_STAT.
1540  */
1541 struct ALT_FPGAMGR_JTAG_STAT_s
1542 {
1543  uint32_t txFifoLevel : 4; /* Current Tx Fifo level */
1544  uint32_t rxFifoLevel : 4; /* Current RX FIFO Level */
1545  uint32_t txFifoEmpty : 1; /* Tx Fifo Empty Status */
1546  uint32_t txFifoFull : 1; /* Tx Fifo Full Status */
1547  uint32_t rxFifoEmpty : 1; /* Rx Fifo Empty Status */
1548  uint32_t rxFifoFull : 1; /* Rx Fifo Full Status */
1549  uint32_t : 3; /* *UNDEFINED* */
1550  uint32_t SessionStatus : 1; /* Valid Ongoing Transfer Session */
1551  uint32_t txDoneSize : 16; /* Number of bits Transmitted */
1552 };
1553 
1554 /* The typedef declaration for register ALT_FPGAMGR_JTAG_STAT. */
1555 typedef volatile struct ALT_FPGAMGR_JTAG_STAT_s ALT_FPGAMGR_JTAG_STAT_t;
1556 #endif /* __ASSEMBLY__ */
1557 
1558 /* The reset value of the ALT_FPGAMGR_JTAG_STAT register. */
1559 #define ALT_FPGAMGR_JTAG_STAT_RESET 0x00000500
1560 /* The byte offset of the ALT_FPGAMGR_JTAG_STAT register from the beginning of the component. */
1561 #define ALT_FPGAMGR_JTAG_STAT_OFST 0x54
1562 
1563 /*
1564  * Register : TCK Divide ratio - jtag_kick
1565  *
1566  * Jtag Master Control Triggers. Each of this bit field triggers a specific
1567  * hardware operation.
1568  *
1569  * Register Layout
1570  *
1571  * Bits | Access | Reset | Description
1572  * :-------|:-------|:--------|:-------------------------------
1573  * [0] | RW | 0x0 | Kick off a new Session
1574  * [1] | RW | 0x0 | force stop an ongoing session.
1575  * [2] | RW | 0x0 | Clear TX FIFO
1576  * [3] | RW | 0x0 | Clear RX FIFO
1577  * [31:4] | ??? | Unknown | *UNDEFINED*
1578  *
1579  */
1580 /*
1581  * Field : Kick off a new Session - startSession
1582  *
1583  * A write 1 to this bit field will kick off a session of TX and RX. Please note
1584  * that there should be alteast 1 word available in the Tx Fifo for this kick off
1585  * to be successful. The status of this kick off can be read from status register
1586  * SessionStatus field.
1587  *
1588  * stopSession has priority over startSession.
1589  *
1590  * Field Access Macros:
1591  *
1592  */
1593 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_KICK_STARTSESSION register field. */
1594 #define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_LSB 0
1595 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_KICK_STARTSESSION register field. */
1596 #define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_MSB 0
1597 /* The width in bits of the ALT_FPGAMGR_JTAG_KICK_STARTSESSION register field. */
1598 #define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_WIDTH 1
1599 /* The mask used to set the ALT_FPGAMGR_JTAG_KICK_STARTSESSION register field value. */
1600 #define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_SET_MSK 0x00000001
1601 /* The mask used to clear the ALT_FPGAMGR_JTAG_KICK_STARTSESSION register field value. */
1602 #define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_CLR_MSK 0xfffffffe
1603 /* The reset value of the ALT_FPGAMGR_JTAG_KICK_STARTSESSION register field. */
1604 #define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_RESET 0x0
1605 /* Extracts the ALT_FPGAMGR_JTAG_KICK_STARTSESSION field value from a register. */
1606 #define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_GET(value) (((value) & 0x00000001) >> 0)
1607 /* Produces a ALT_FPGAMGR_JTAG_KICK_STARTSESSION register field value suitable for setting the register. */
1608 #define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_SET(value) (((value) << 0) & 0x00000001)
1609 
1610 /*
1611  * Field : force stop an ongoing session. - stopSession
1612  *
1613  * A write 1 to this bit field will kick off stop of an ongoing session of TX and
1614  * RX. Please note that there should be alteast 1 word available in the Tx Fifo for
1615  * this kick off to be successful. The status of this kick off can be read from
1616  * status register SessionStatus field.
1617  *
1618  * stopSession has priority over startSession.
1619  *
1620  * Field Access Macros:
1621  *
1622  */
1623 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_KICK_STOPSESSION register field. */
1624 #define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_LSB 1
1625 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_KICK_STOPSESSION register field. */
1626 #define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_MSB 1
1627 /* The width in bits of the ALT_FPGAMGR_JTAG_KICK_STOPSESSION register field. */
1628 #define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_WIDTH 1
1629 /* The mask used to set the ALT_FPGAMGR_JTAG_KICK_STOPSESSION register field value. */
1630 #define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_SET_MSK 0x00000002
1631 /* The mask used to clear the ALT_FPGAMGR_JTAG_KICK_STOPSESSION register field value. */
1632 #define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_CLR_MSK 0xfffffffd
1633 /* The reset value of the ALT_FPGAMGR_JTAG_KICK_STOPSESSION register field. */
1634 #define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_RESET 0x0
1635 /* Extracts the ALT_FPGAMGR_JTAG_KICK_STOPSESSION field value from a register. */
1636 #define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_GET(value) (((value) & 0x00000002) >> 1)
1637 /* Produces a ALT_FPGAMGR_JTAG_KICK_STOPSESSION register field value suitable for setting the register. */
1638 #define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_SET(value) (((value) << 1) & 0x00000002)
1639 
1640 /*
1641  * Field : Clear TX FIFO - clearTxFifo
1642  *
1643  * A write 1 to this bit field will empty the TxFifo. A read will always return 0.
1644  *
1645  * Field Access Macros:
1646  *
1647  */
1648 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO register field. */
1649 #define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_LSB 2
1650 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO register field. */
1651 #define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_MSB 2
1652 /* The width in bits of the ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO register field. */
1653 #define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_WIDTH 1
1654 /* The mask used to set the ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO register field value. */
1655 #define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_SET_MSK 0x00000004
1656 /* The mask used to clear the ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO register field value. */
1657 #define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_CLR_MSK 0xfffffffb
1658 /* The reset value of the ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO register field. */
1659 #define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_RESET 0x0
1660 /* Extracts the ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO field value from a register. */
1661 #define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_GET(value) (((value) & 0x00000004) >> 2)
1662 /* Produces a ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO register field value suitable for setting the register. */
1663 #define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_SET(value) (((value) << 2) & 0x00000004)
1664 
1665 /*
1666  * Field : Clear RX FIFO - clearRxFifo
1667  *
1668  * A write 1 to this bit field will empty the RxFifo. A read will always return 0.
1669  *
1670  * Field Access Macros:
1671  *
1672  */
1673 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO register field. */
1674 #define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_LSB 3
1675 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO register field. */
1676 #define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_MSB 3
1677 /* The width in bits of the ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO register field. */
1678 #define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_WIDTH 1
1679 /* The mask used to set the ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO register field value. */
1680 #define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_SET_MSK 0x00000008
1681 /* The mask used to clear the ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO register field value. */
1682 #define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_CLR_MSK 0xfffffff7
1683 /* The reset value of the ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO register field. */
1684 #define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_RESET 0x0
1685 /* Extracts the ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO field value from a register. */
1686 #define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_GET(value) (((value) & 0x00000008) >> 3)
1687 /* Produces a ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO register field value suitable for setting the register. */
1688 #define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_SET(value) (((value) << 3) & 0x00000008)
1689 
1690 #ifndef __ASSEMBLY__
1691 /*
1692  * WARNING: The C register and register group struct declarations are provided for
1693  * convenience and illustrative purposes. They should, however, be used with
1694  * caution as the C language standard provides no guarantees about the alignment or
1695  * atomicity of device memory accesses. The recommended practice for writing
1696  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1697  * alt_write_word() functions.
1698  *
1699  * The struct declaration for register ALT_FPGAMGR_JTAG_KICK.
1700  */
1701 struct ALT_FPGAMGR_JTAG_KICK_s
1702 {
1703  uint32_t startSession : 1; /* Kick off a new Session */
1704  uint32_t stopSession : 1; /* force stop an ongoing session. */
1705  uint32_t clearTxFifo : 1; /* Clear TX FIFO */
1706  uint32_t clearRxFifo : 1; /* Clear RX FIFO */
1707  uint32_t : 28; /* *UNDEFINED* */
1708 };
1709 
1710 /* The typedef declaration for register ALT_FPGAMGR_JTAG_KICK. */
1711 typedef volatile struct ALT_FPGAMGR_JTAG_KICK_s ALT_FPGAMGR_JTAG_KICK_t;
1712 #endif /* __ASSEMBLY__ */
1713 
1714 /* The reset value of the ALT_FPGAMGR_JTAG_KICK register. */
1715 #define ALT_FPGAMGR_JTAG_KICK_RESET 0x00000000
1716 /* The byte offset of the ALT_FPGAMGR_JTAG_KICK register from the beginning of the component. */
1717 #define ALT_FPGAMGR_JTAG_KICK_OFST 0x58
1718 
1719 /*
1720  * Register : TX FIFO Write - jtag_data_w
1721  *
1722  * A write to this field initiates a write to the TxFifo with the value provided.
1723  * Please note that this is always a 32bit write, and lower 16 of these bits will
1724  * be transferred over TDI and upper 16 of these bits will be transferred over TMS
1725  * once the transfer is initiated. A write to this fifo when full will just be
1726  * ignored. Also it is allowed to keep writing this fifo without actually intiating
1727  * a transfer. A typical scenario where this is applicable is if the software want
1728  * to keep a fixed number of bits ready for JTAG interface before kicking it off.
1729  *
1730  * Both the fifos are 8 words deep. So you can have up to 128 bits buffered in the
1731  * FIFOs. If you have more than 128 bits to be transferred, and want continuous
1732  * transfer software should make sure proper data flow to avoid a Tx-Fifo under-run
1733  * or Rx-Fifo over-run. A Rx-Fifo over-run will cause silent data loss, and a Tx-
1734  * Fifo under-run will stop the transfer, and will stop the TCK toggles, till
1735  * another transfer is initiated by software.
1736  *
1737  * At 5MHz jtag clock 16x100/5 = 320 cycles of FPGA manager clock to transfer 1
1738  * word of data
1739  *
1740  * At 25Mhz jtag clock 16x100/25 = 64 cycles of FPGA manager clock to transfer 1
1741  * word of data.
1742  *
1743  * Register Layout
1744  *
1745  * Bits | Access | Reset | Description
1746  * :--------|:-------|:------|:------------
1747  * [15:0] | RW | 0x0 | TDI Data
1748  * [31:16] | RW | 0x0 | TMS Data
1749  *
1750  */
1751 /*
1752  * Field : TDI Data - tdiData
1753  *
1754  * Field Access Macros:
1755  *
1756  */
1757 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_DATA_W_TDIDATA register field. */
1758 #define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_LSB 0
1759 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_DATA_W_TDIDATA register field. */
1760 #define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_MSB 15
1761 /* The width in bits of the ALT_FPGAMGR_JTAG_DATA_W_TDIDATA register field. */
1762 #define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_WIDTH 16
1763 /* The mask used to set the ALT_FPGAMGR_JTAG_DATA_W_TDIDATA register field value. */
1764 #define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_SET_MSK 0x0000ffff
1765 /* The mask used to clear the ALT_FPGAMGR_JTAG_DATA_W_TDIDATA register field value. */
1766 #define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_CLR_MSK 0xffff0000
1767 /* The reset value of the ALT_FPGAMGR_JTAG_DATA_W_TDIDATA register field. */
1768 #define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_RESET 0x0
1769 /* Extracts the ALT_FPGAMGR_JTAG_DATA_W_TDIDATA field value from a register. */
1770 #define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_GET(value) (((value) & 0x0000ffff) >> 0)
1771 /* Produces a ALT_FPGAMGR_JTAG_DATA_W_TDIDATA register field value suitable for setting the register. */
1772 #define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_SET(value) (((value) << 0) & 0x0000ffff)
1773 
1774 /*
1775  * Field : TMS Data - tmsData
1776  *
1777  * Data to be transferred over TMS.
1778  *
1779  * Field Access Macros:
1780  *
1781  */
1782 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_DATA_W_TMSDATA register field. */
1783 #define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_LSB 16
1784 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_DATA_W_TMSDATA register field. */
1785 #define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_MSB 31
1786 /* The width in bits of the ALT_FPGAMGR_JTAG_DATA_W_TMSDATA register field. */
1787 #define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_WIDTH 16
1788 /* The mask used to set the ALT_FPGAMGR_JTAG_DATA_W_TMSDATA register field value. */
1789 #define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_SET_MSK 0xffff0000
1790 /* The mask used to clear the ALT_FPGAMGR_JTAG_DATA_W_TMSDATA register field value. */
1791 #define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_CLR_MSK 0x0000ffff
1792 /* The reset value of the ALT_FPGAMGR_JTAG_DATA_W_TMSDATA register field. */
1793 #define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_RESET 0x0
1794 /* Extracts the ALT_FPGAMGR_JTAG_DATA_W_TMSDATA field value from a register. */
1795 #define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_GET(value) (((value) & 0xffff0000) >> 16)
1796 /* Produces a ALT_FPGAMGR_JTAG_DATA_W_TMSDATA register field value suitable for setting the register. */
1797 #define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_SET(value) (((value) << 16) & 0xffff0000)
1798 
1799 #ifndef __ASSEMBLY__
1800 /*
1801  * WARNING: The C register and register group struct declarations are provided for
1802  * convenience and illustrative purposes. They should, however, be used with
1803  * caution as the C language standard provides no guarantees about the alignment or
1804  * atomicity of device memory accesses. The recommended practice for writing
1805  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1806  * alt_write_word() functions.
1807  *
1808  * The struct declaration for register ALT_FPGAMGR_JTAG_DATA_W.
1809  */
1810 struct ALT_FPGAMGR_JTAG_DATA_W_s
1811 {
1812  uint32_t tdiData : 16; /* TDI Data */
1813  uint32_t tmsData : 16; /* TMS Data */
1814 };
1815 
1816 /* The typedef declaration for register ALT_FPGAMGR_JTAG_DATA_W. */
1817 typedef volatile struct ALT_FPGAMGR_JTAG_DATA_W_s ALT_FPGAMGR_JTAG_DATA_W_t;
1818 #endif /* __ASSEMBLY__ */
1819 
1820 /* The reset value of the ALT_FPGAMGR_JTAG_DATA_W register. */
1821 #define ALT_FPGAMGR_JTAG_DATA_W_RESET 0x00000000
1822 /* The byte offset of the ALT_FPGAMGR_JTAG_DATA_W register from the beginning of the component. */
1823 #define ALT_FPGAMGR_JTAG_DATA_W_OFST 0x60
1824 
1825 /*
1826  * Register : RX FIFO Read - jtag_data_r
1827  *
1828  * A read to this field initiates a read to the RxFifo. Please note that the read
1829  * always returns a 16 bit value. If the received number of bits are not aligned
1830  * with 16, lower most n bits should be ignored by software. For example in the
1831  * case of 6 bits received, rdata[15:10] will contain received bits and rdata[9:0]
1832  * should be ignored. A read of the fifo while empty is not defined.
1833  *
1834  * Both the fifos are 8 words deep. So you can have up to 128 bits buffered in the
1835  * FIFOs. If you have more than 128 bits to be transferred, and want continuous
1836  * transfer software should make sure proper data flow to avoid a Tx-Fifo under-run
1837  * or Rx-Fifo over-run. A Rx-Fifo over-run will cause silent data loss, and a Tx-
1838  * Fifo under-run will stop the transfer, and will stop the TCK toggles, till
1839  * another transfer is initiated by software.
1840  *
1841  * At 5MHz jtag clock 16x100/5 = 320 cycles of FPGA manager clock to transfer 1
1842  * word of data
1843  *
1844  * At 25Mhz jtag clock 16x100/25 = 64 cycles of FPGA manager clock to transfer 1
1845  * word of data.
1846  *
1847  * Register Layout
1848  *
1849  * Bits | Access | Reset | Description
1850  * :--------|:-------|:------|:-----------------------------
1851  * [15:0] | RW | 0x0 | TDI Data
1852  * [31:16] | RW | 0x0 | ALT_FPGAMGR_JTAG_DATA_R_RSVD
1853  *
1854  */
1855 /*
1856  * Field : TDI Data - tdiData
1857  *
1858  * Field Access Macros:
1859  *
1860  */
1861 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_DATA_R_TDIDATA register field. */
1862 #define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_LSB 0
1863 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_DATA_R_TDIDATA register field. */
1864 #define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_MSB 15
1865 /* The width in bits of the ALT_FPGAMGR_JTAG_DATA_R_TDIDATA register field. */
1866 #define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_WIDTH 16
1867 /* The mask used to set the ALT_FPGAMGR_JTAG_DATA_R_TDIDATA register field value. */
1868 #define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_SET_MSK 0x0000ffff
1869 /* The mask used to clear the ALT_FPGAMGR_JTAG_DATA_R_TDIDATA register field value. */
1870 #define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_CLR_MSK 0xffff0000
1871 /* The reset value of the ALT_FPGAMGR_JTAG_DATA_R_TDIDATA register field. */
1872 #define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_RESET 0x0
1873 /* Extracts the ALT_FPGAMGR_JTAG_DATA_R_TDIDATA field value from a register. */
1874 #define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_GET(value) (((value) & 0x0000ffff) >> 0)
1875 /* Produces a ALT_FPGAMGR_JTAG_DATA_R_TDIDATA register field value suitable for setting the register. */
1876 #define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_SET(value) (((value) << 0) & 0x0000ffff)
1877 
1878 /*
1879  * Field : Reserved
1880  *
1881  * Field Access Macros:
1882  *
1883  */
1884 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_DATA_R_RSVD register field. */
1885 #define ALT_FPGAMGR_JTAG_DATA_R_RSVD_LSB 16
1886 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_DATA_R_RSVD register field. */
1887 #define ALT_FPGAMGR_JTAG_DATA_R_RSVD_MSB 31
1888 /* The width in bits of the ALT_FPGAMGR_JTAG_DATA_R_RSVD register field. */
1889 #define ALT_FPGAMGR_JTAG_DATA_R_RSVD_WIDTH 16
1890 /* The mask used to set the ALT_FPGAMGR_JTAG_DATA_R_RSVD register field value. */
1891 #define ALT_FPGAMGR_JTAG_DATA_R_RSVD_SET_MSK 0xffff0000
1892 /* The mask used to clear the ALT_FPGAMGR_JTAG_DATA_R_RSVD register field value. */
1893 #define ALT_FPGAMGR_JTAG_DATA_R_RSVD_CLR_MSK 0x0000ffff
1894 /* The reset value of the ALT_FPGAMGR_JTAG_DATA_R_RSVD register field. */
1895 #define ALT_FPGAMGR_JTAG_DATA_R_RSVD_RESET 0x0
1896 /* Extracts the ALT_FPGAMGR_JTAG_DATA_R_RSVD field value from a register. */
1897 #define ALT_FPGAMGR_JTAG_DATA_R_RSVD_GET(value) (((value) & 0xffff0000) >> 16)
1898 /* Produces a ALT_FPGAMGR_JTAG_DATA_R_RSVD register field value suitable for setting the register. */
1899 #define ALT_FPGAMGR_JTAG_DATA_R_RSVD_SET(value) (((value) << 16) & 0xffff0000)
1900 
1901 #ifndef __ASSEMBLY__
1902 /*
1903  * WARNING: The C register and register group struct declarations are provided for
1904  * convenience and illustrative purposes. They should, however, be used with
1905  * caution as the C language standard provides no guarantees about the alignment or
1906  * atomicity of device memory accesses. The recommended practice for writing
1907  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1908  * alt_write_word() functions.
1909  *
1910  * The struct declaration for register ALT_FPGAMGR_JTAG_DATA_R.
1911  */
1912 struct ALT_FPGAMGR_JTAG_DATA_R_s
1913 {
1914  uint32_t tdiData : 16; /* TDI Data */
1915  uint32_t Reserved : 16; /* ALT_FPGAMGR_JTAG_DATA_R_RSVD */
1916 };
1917 
1918 /* The typedef declaration for register ALT_FPGAMGR_JTAG_DATA_R. */
1919 typedef volatile struct ALT_FPGAMGR_JTAG_DATA_R_s ALT_FPGAMGR_JTAG_DATA_R_t;
1920 #endif /* __ASSEMBLY__ */
1921 
1922 /* The reset value of the ALT_FPGAMGR_JTAG_DATA_R register. */
1923 #define ALT_FPGAMGR_JTAG_DATA_R_RESET 0x00000000
1924 /* The byte offset of the ALT_FPGAMGR_JTAG_DATA_R register from the beginning of the component. */
1925 #define ALT_FPGAMGR_JTAG_DATA_R_OFST 0x64
1926 
1927 /*
1928  * Register : imgcfg_ctrl_00
1929  *
1930  * Register Layout
1931  *
1932  * Bits | Access | Reset | Description
1933  * :--------|:-------|:------|:------------------------------------------
1934  * [0] | RW | 0x1 | ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG
1935  * [1] | RW | 0x1 | ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT
1936  * [2] | RW | 0x1 | ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE
1937  * [7:3] | ??? | 0x0 | *UNDEFINED*
1938  * [8] | RW | 0x1 | ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG
1939  * [15:9] | ??? | 0x0 | *UNDEFINED*
1940  * [16] | RW | 0x0 | ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE
1941  * [23:17] | ??? | 0x0 | *UNDEFINED*
1942  * [24] | RW | 0x0 | ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE
1943  * [31:25] | ??? | 0x0 | *UNDEFINED*
1944  *
1945  */
1946 /*
1947  * Field : s2f_nenable_nconfig
1948  *
1949  * HPS override Enable for nCONFIG to CSS
1950  *
1951  * 1: override is disabled
1952  *
1953  * 0: override is enabled
1954  *
1955  * Field Access Macros:
1956  *
1957  */
1958 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG register field. */
1959 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_LSB 0
1960 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG register field. */
1961 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_MSB 0
1962 /* The width in bits of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG register field. */
1963 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_WIDTH 1
1964 /* The mask used to set the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG register field value. */
1965 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_SET_MSK 0x00000001
1966 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG register field value. */
1967 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_CLR_MSK 0xfffffffe
1968 /* The reset value of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG register field. */
1969 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_RESET 0x1
1970 /* Extracts the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG field value from a register. */
1971 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_GET(value) (((value) & 0x00000001) >> 0)
1972 /* Produces a ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG register field value suitable for setting the register. */
1973 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_SET(value) (((value) << 0) & 0x00000001)
1974 
1975 /*
1976  * Field : s2f_nenable_nstatus
1977  *
1978  * HPS override Enable for nSTATUS to PIN
1979  *
1980  * 1: override is disabled
1981  *
1982  * 0: override is enabled
1983  *
1984  * Field Access Macros:
1985  *
1986  */
1987 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT register field. */
1988 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_LSB 1
1989 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT register field. */
1990 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_MSB 1
1991 /* The width in bits of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT register field. */
1992 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_WIDTH 1
1993 /* The mask used to set the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT register field value. */
1994 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_SET_MSK 0x00000002
1995 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT register field value. */
1996 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_CLR_MSK 0xfffffffd
1997 /* The reset value of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT register field. */
1998 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_RESET 0x1
1999 /* Extracts the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT field value from a register. */
2000 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_GET(value) (((value) & 0x00000002) >> 1)
2001 /* Produces a ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT register field value suitable for setting the register. */
2002 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_SET(value) (((value) << 1) & 0x00000002)
2003 
2004 /*
2005  * Field : s2f_nenable_condone
2006  *
2007  * HPS override Enable for CONF_DONE to PIN
2008  *
2009  * 1: override is disabled
2010  *
2011  * 0: override is enabled
2012  *
2013  * Field Access Macros:
2014  *
2015  */
2016 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE register field. */
2017 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_LSB 2
2018 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE register field. */
2019 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_MSB 2
2020 /* The width in bits of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE register field. */
2021 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_WIDTH 1
2022 /* The mask used to set the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE register field value. */
2023 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_SET_MSK 0x00000004
2024 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE register field value. */
2025 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_CLR_MSK 0xfffffffb
2026 /* The reset value of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE register field. */
2027 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_RESET 0x1
2028 /* Extracts the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE field value from a register. */
2029 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_GET(value) (((value) & 0x00000004) >> 2)
2030 /* Produces a ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE register field value suitable for setting the register. */
2031 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_SET(value) (((value) << 2) & 0x00000004)
2032 
2033 /*
2034  * Field : s2f_nconfig
2035  *
2036  * This bit has an effect on CSS only if curresponding override is enabled.
2037  *
2038  * 1: Drive nCONFIG input to CSS 1.
2039  *
2040  * 0: Drive nCONFIG input to CSS 0
2041  *
2042  * The nCONFIG input is used to put the FPGA into its reset phase. If the FPGA was
2043  * configured, its operation stops and it will have to be configured again to start
2044  * operation.
2045  *
2046  * Field Access Macros:
2047  *
2048  */
2049 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG register field. */
2050 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_LSB 8
2051 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG register field. */
2052 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_MSB 8
2053 /* The width in bits of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG register field. */
2054 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_WIDTH 1
2055 /* The mask used to set the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG register field value. */
2056 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_SET_MSK 0x00000100
2057 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG register field value. */
2058 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_CLR_MSK 0xfffffeff
2059 /* The reset value of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG register field. */
2060 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_RESET 0x1
2061 /* Extracts the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG field value from a register. */
2062 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_GET(value) (((value) & 0x00000100) >> 8)
2063 /* Produces a ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG register field value suitable for setting the register. */
2064 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_SET(value) (((value) << 8) & 0x00000100)
2065 
2066 /*
2067  * Field : s2f_nstatus_oe
2068  *
2069  * This bit has an effect on CSS only if curresponding override is enabled.
2070  *
2071  * 1: Drive nSTATUS pin to 0.
2072  *
2073  * 0: Disable nSTATUS pin drive from HPS, and allow default pull-up to take over.
2074  *
2075  * Driving this pin has no effect on CSS once the FPGA is in user mode.
2076  *
2077  * HPS can drive this pin 0 to delay the initialization phase of CSS.
2078  *
2079  * During configuation phase, HPS can drive this pin 0 to end the current
2080  * configuration and initialize a reconfiguration.
2081  *
2082  * Field Access Macros:
2083  *
2084  */
2085 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE register field. */
2086 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_LSB 16
2087 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE register field. */
2088 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_MSB 16
2089 /* The width in bits of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE register field. */
2090 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_WIDTH 1
2091 /* The mask used to set the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE register field value. */
2092 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_SET_MSK 0x00010000
2093 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE register field value. */
2094 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_CLR_MSK 0xfffeffff
2095 /* The reset value of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE register field. */
2096 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_RESET 0x0
2097 /* Extracts the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE field value from a register. */
2098 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_GET(value) (((value) & 0x00010000) >> 16)
2099 /* Produces a ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE register field value suitable for setting the register. */
2100 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_SET(value) (((value) << 16) & 0x00010000)
2101 
2102 /*
2103  * Field : s2f_condone_oe
2104  *
2105  * This bit has an effect on CSS/PIN only if curresponding override is enabled.
2106  *
2107  * 1: Drive CONF_DONE pin to 0.
2108  *
2109  * 0: Disable CONF_DONE pin drive from HPS, and allow default pull-up to take over.
2110  *
2111  * HPS can drive CONF_DONE pin 0 to delay the FPGA from entering user mode.
2112  *
2113  * Field Access Macros:
2114  *
2115  */
2116 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE register field. */
2117 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_LSB 24
2118 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE register field. */
2119 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_MSB 24
2120 /* The width in bits of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE register field. */
2121 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_WIDTH 1
2122 /* The mask used to set the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE register field value. */
2123 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK 0x01000000
2124 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE register field value. */
2125 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_CLR_MSK 0xfeffffff
2126 /* The reset value of the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE register field. */
2127 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_RESET 0x0
2128 /* Extracts the ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE field value from a register. */
2129 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_GET(value) (((value) & 0x01000000) >> 24)
2130 /* Produces a ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE register field value suitable for setting the register. */
2131 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET(value) (((value) << 24) & 0x01000000)
2132 
2133 #ifndef __ASSEMBLY__
2134 /*
2135  * WARNING: The C register and register group struct declarations are provided for
2136  * convenience and illustrative purposes. They should, however, be used with
2137  * caution as the C language standard provides no guarantees about the alignment or
2138  * atomicity of device memory accesses. The recommended practice for writing
2139  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2140  * alt_write_word() functions.
2141  *
2142  * The struct declaration for register ALT_FPGAMGR_IMGCFG_CTL_00.
2143  */
2144 struct ALT_FPGAMGR_IMGCFG_CTL_00_s
2145 {
2146  uint32_t s2f_nenable_nconfig : 1; /* ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG */
2147  uint32_t s2f_nenable_nstatus : 1; /* ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT */
2148  uint32_t s2f_nenable_condone : 1; /* ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE */
2149  uint32_t : 5; /* *UNDEFINED* */
2150  uint32_t s2f_nconfig : 1; /* ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG */
2151  uint32_t : 7; /* *UNDEFINED* */
2152  uint32_t s2f_nstatus_oe : 1; /* ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE */
2153  uint32_t : 7; /* *UNDEFINED* */
2154  uint32_t s2f_condone_oe : 1; /* ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE */
2155  uint32_t : 7; /* *UNDEFINED* */
2156 };
2157 
2158 /* The typedef declaration for register ALT_FPGAMGR_IMGCFG_CTL_00. */
2159 typedef volatile struct ALT_FPGAMGR_IMGCFG_CTL_00_s ALT_FPGAMGR_IMGCFG_CTL_00_t;
2160 #endif /* __ASSEMBLY__ */
2161 
2162 /* The reset value of the ALT_FPGAMGR_IMGCFG_CTL_00 register. */
2163 #define ALT_FPGAMGR_IMGCFG_CTL_00_RESET 0x00000107
2164 /* The byte offset of the ALT_FPGAMGR_IMGCFG_CTL_00 register from the beginning of the component. */
2165 #define ALT_FPGAMGR_IMGCFG_CTL_00_OFST 0x70
2166 
2167 /*
2168  * Register : imgcfg_ctrl_01
2169  *
2170  * Register Layout
2171  *
2172  * Bits | Access | Reset | Description
2173  * :--------|:-------|:------|:-----------------------------------------
2174  * [0] | RW | 0x1 | ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG
2175  * [15:1] | ??? | 0x0 | *UNDEFINED*
2176  * [16] | RW | 0x0 | ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST
2177  * [23:17] | ??? | 0x0 | *UNDEFINED*
2178  * [24] | RW | 0x1 | ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE
2179  * [31:25] | ??? | 0x0 | *UNDEFINED*
2180  *
2181  */
2182 /*
2183  * Field : s2f_nenable_config
2184  *
2185  * HPS override Enable for DATA, DCLK, NCE and PR_REQUEST to CSS
2186  *
2187  * 1: override is disabled
2188  *
2189  * 0: override is enabled
2190  *
2191  * Field Access Macros:
2192  *
2193  */
2194 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG register field. */
2195 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_LSB 0
2196 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG register field. */
2197 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_MSB 0
2198 /* The width in bits of the ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG register field. */
2199 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_WIDTH 1
2200 /* The mask used to set the ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG register field value. */
2201 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_SET_MSK 0x00000001
2202 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG register field value. */
2203 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_CLR_MSK 0xfffffffe
2204 /* The reset value of the ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG register field. */
2205 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_RESET 0x1
2206 /* Extracts the ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG field value from a register. */
2207 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_GET(value) (((value) & 0x00000001) >> 0)
2208 /* Produces a ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG register field value suitable for setting the register. */
2209 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_SET(value) (((value) << 0) & 0x00000001)
2210 
2211 /*
2212  * Field : s2f_pr_request
2213  *
2214  * This bit carries the override value of PR_REQUEST to CSS.
2215  *
2216  * Field Access Macros:
2217  *
2218  */
2219 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST register field. */
2220 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_LSB 16
2221 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST register field. */
2222 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_MSB 16
2223 /* The width in bits of the ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST register field. */
2224 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_WIDTH 1
2225 /* The mask used to set the ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST register field value. */
2226 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK 0x00010000
2227 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST register field value. */
2228 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_CLR_MSK 0xfffeffff
2229 /* The reset value of the ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST register field. */
2230 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_RESET 0x0
2231 /* Extracts the ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST field value from a register. */
2232 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_GET(value) (((value) & 0x00010000) >> 16)
2233 /* Produces a ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST register field value suitable for setting the register. */
2234 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET(value) (((value) << 16) & 0x00010000)
2235 
2236 /*
2237  * Field : s2f_nce
2238  *
2239  * This bit carries the override value of nCE to CSS.
2240  *
2241  * Field Access Macros:
2242  *
2243  */
2244 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE register field. */
2245 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_LSB 24
2246 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE register field. */
2247 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_MSB 24
2248 /* The width in bits of the ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE register field. */
2249 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_WIDTH 1
2250 /* The mask used to set the ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE register field value. */
2251 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK 0x01000000
2252 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE register field value. */
2253 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_CLR_MSK 0xfeffffff
2254 /* The reset value of the ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE register field. */
2255 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_RESET 0x1
2256 /* Extracts the ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE field value from a register. */
2257 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_GET(value) (((value) & 0x01000000) >> 24)
2258 /* Produces a ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE register field value suitable for setting the register. */
2259 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET(value) (((value) << 24) & 0x01000000)
2260 
2261 #ifndef __ASSEMBLY__
2262 /*
2263  * WARNING: The C register and register group struct declarations are provided for
2264  * convenience and illustrative purposes. They should, however, be used with
2265  * caution as the C language standard provides no guarantees about the alignment or
2266  * atomicity of device memory accesses. The recommended practice for writing
2267  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2268  * alt_write_word() functions.
2269  *
2270  * The struct declaration for register ALT_FPGAMGR_IMGCFG_CTL_01.
2271  */
2272 struct ALT_FPGAMGR_IMGCFG_CTL_01_s
2273 {
2274  uint32_t s2f_nenable_config : 1; /* ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG */
2275  uint32_t : 15; /* *UNDEFINED* */
2276  uint32_t s2f_pr_request : 1; /* ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST */
2277  uint32_t : 7; /* *UNDEFINED* */
2278  uint32_t s2f_nce : 1; /* ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE */
2279  uint32_t : 7; /* *UNDEFINED* */
2280 };
2281 
2282 /* The typedef declaration for register ALT_FPGAMGR_IMGCFG_CTL_01. */
2283 typedef volatile struct ALT_FPGAMGR_IMGCFG_CTL_01_s ALT_FPGAMGR_IMGCFG_CTL_01_t;
2284 #endif /* __ASSEMBLY__ */
2285 
2286 /* The reset value of the ALT_FPGAMGR_IMGCFG_CTL_01 register. */
2287 #define ALT_FPGAMGR_IMGCFG_CTL_01_RESET 0x01000001
2288 /* The byte offset of the ALT_FPGAMGR_IMGCFG_CTL_01 register from the beginning of the component. */
2289 #define ALT_FPGAMGR_IMGCFG_CTL_01_OFST 0x74
2290 
2291 /*
2292  * Register : Control Register - imgcfg_ctrl_02
2293  *
2294  * Allows HPS to control FPGA configuration.
2295  *
2296  * The NCONFIGPULL, NSTATUSPULL, and CONFDONEPULL fields drive signals to the FPGA
2297  * Control Block that are logically ORed into their respective pins. These signals
2298  * are always driven independent of the value of EN. The polarity of the
2299  * NCONFIGPULL, NSTATUSPULL, and CONFDONEPULL fields is inverted relative to their
2300  * associated pins.
2301  *
2302  * The MSEL (external pins), CDRATIO and CFGWDTH signals determine the mode of
2303  * operation for Normal Configuration. For Partial Reconfiguration, CDRATIO is used
2304  * to set the appropriate clock to data ratio, and CFGWDTH should always be set to
2305  * 16-bit Passive Parallel.
2306  *
2307  * AXICFGEN is used to enable transfer of configuration data by enabling or
2308  * disabling DCLK during data transfers.
2309  *
2310  * Register Layout
2311  *
2312  * Bits | Access | Reset | Description
2313  * :--------|:-------|:------|:--------------------------------------
2314  * [0] | RW | 0x0 | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL
2315  * [7:1] | ??? | 0x0 | *UNDEFINED*
2316  * [8] | RW | 0x0 | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA
2317  * [15:9] | ??? | 0x1 | *UNDEFINED*
2318  * [17:16] | RW | 0x0 | CD Ratio
2319  * [23:18] | ??? | 0x0 | *UNDEFINED*
2320  * [24] | RW | 0x0 | Configuration Data Width
2321  * [31:25] | ??? | 0x0 | *UNDEFINED*
2322  *
2323  */
2324 /*
2325  * Field : en_cfg_ctrl
2326  *
2327  * If this bit is not enabled, the s2f_dclk as well as s2f_data will be always
2328  * driven 0.
2329  *
2330  * This is to provide a mechanism by which HPS can take over the DCLK/DATA by first
2331  * setting the nenable_dclk even while s2f_dclk and s2f_data from HPS is silent.
2332  *
2333  * Field Access Macros:
2334  *
2335  */
2336 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL register field. */
2337 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_LSB 0
2338 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL register field. */
2339 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_MSB 0
2340 /* The width in bits of the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL register field. */
2341 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_WIDTH 1
2342 /* The mask used to set the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL register field value. */
2343 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_SET_MSK 0x00000001
2344 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL register field value. */
2345 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_CLR_MSK 0xfffffffe
2346 /* The reset value of the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL register field. */
2347 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_RESET 0x0
2348 /* Extracts the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL field value from a register. */
2349 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_GET(value) (((value) & 0x00000001) >> 0)
2350 /* Produces a ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL register field value suitable for setting the register. */
2351 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_SET(value) (((value) << 0) & 0x00000001)
2352 
2353 /*
2354  * Field : en_cfg_data
2355  *
2356  * this is an unused software bit
2357  *
2358  * Field Access Macros:
2359  *
2360  */
2361 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA register field. */
2362 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_LSB 8
2363 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA register field. */
2364 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_MSB 8
2365 /* The width in bits of the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA register field. */
2366 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_WIDTH 1
2367 /* The mask used to set the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA register field value. */
2368 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK 0x00000100
2369 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA register field value. */
2370 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_CLR_MSK 0xfffffeff
2371 /* The reset value of the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA register field. */
2372 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_RESET 0x0
2373 /* Extracts the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA field value from a register. */
2374 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_GET(value) (((value) & 0x00000100) >> 8)
2375 /* Produces a ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA register field value suitable for setting the register. */
2376 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET(value) (((value) << 8) & 0x00000100)
2377 
2378 /*
2379  * Field : CD Ratio - cdratio
2380  *
2381  * This field controls the Clock to Data Ratio (CDRATIO) for Normal Configuration
2382  * and Partial Reconfiguration data transfer from the AXI Slave to the FPGA.
2383  *
2384  * For Normal Configuration, the value in this field must be set to be consistent
2385  * to the implied CD ratio of the MSEL setting.
2386  *
2387  * For Partial Reconfiguration, the value in this field must be set to the same
2388  * clock to data ratio in the options bits in the Normal Configuration file.
2389  *
2390  * Field Enumeration Values:
2391  *
2392  * Enum | Value | Description
2393  * :---------------------------------------|:------|:-------------
2394  * ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X1 | 0x0 | CDRATIO of 1
2395  * ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X2 | 0x1 | CDRATIO of 2
2396  * ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X4 | 0x2 | CDRATIO of 4
2397  * ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X8 | 0x3 | CDRATIO of 8
2398  *
2399  * Field Access Macros:
2400  *
2401  */
2402 /*
2403  * Enumerated value for register field ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO
2404  *
2405  * CDRATIO of 1
2406  */
2407 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X1 0x0
2408 /*
2409  * Enumerated value for register field ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO
2410  *
2411  * CDRATIO of 2
2412  */
2413 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X2 0x1
2414 /*
2415  * Enumerated value for register field ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO
2416  *
2417  * CDRATIO of 4
2418  */
2419 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X4 0x2
2420 /*
2421  * Enumerated value for register field ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO
2422  *
2423  * CDRATIO of 8
2424  */
2425 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X8 0x3
2426 
2427 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO register field. */
2428 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
2429 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO register field. */
2430 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_MSB 17
2431 /* The width in bits of the ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO register field. */
2432 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_WIDTH 2
2433 /* The mask used to set the ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO register field value. */
2434 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000
2435 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO register field value. */
2436 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_CLR_MSK 0xfffcffff
2437 /* The reset value of the ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO register field. */
2438 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_RESET 0x0
2439 /* Extracts the ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO field value from a register. */
2440 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_GET(value) (((value) & 0x00030000) >> 16)
2441 /* Produces a ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO register field value suitable for setting the register. */
2442 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET(value) (((value) << 16) & 0x00030000)
2443 
2444 /*
2445  * Field : Configuration Data Width - cfgwidth
2446  *
2447  * This field determines the Configuration Passive Parallel data bus width when HPS
2448  * configures the FPGA. Only 32-bit Passive Parallel or 16-bit Passive Parallel
2449  * are supported.
2450  *
2451  * When HPS does Normal Configuration, configuration should use 32-bit Passive
2452  * Parallel Mode. The external pins MSEL must be set appropriately for the
2453  * configuration selected.
2454  *
2455  * For Partial Reconfiguration, 16-bit Passive Parallel must be used.
2456  *
2457  * Field Enumeration Values:
2458  *
2459  * Enum | Value | Description
2460  * :-------------------------------------------|:------|:------------------------
2461  * ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_E_PPX16 | 0x0 | 16-bit Passive Parallel
2462  * ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_E_PPX32 | 0x1 | 32-bit Passive Parallel
2463  *
2464  * Field Access Macros:
2465  *
2466  */
2467 /*
2468  * Enumerated value for register field ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH
2469  *
2470  * 16-bit Passive Parallel
2471  */
2472 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_E_PPX16 0x0
2473 /*
2474  * Enumerated value for register field ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH
2475  *
2476  * 32-bit Passive Parallel
2477  */
2478 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_E_PPX32 0x1
2479 
2480 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH register field. */
2481 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_LSB 24
2482 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH register field. */
2483 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_MSB 24
2484 /* The width in bits of the ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH register field. */
2485 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_WIDTH 1
2486 /* The mask used to set the ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH register field value. */
2487 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK 0x01000000
2488 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH register field value. */
2489 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_CLR_MSK 0xfeffffff
2490 /* The reset value of the ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH register field. */
2491 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_RESET 0x0
2492 /* Extracts the ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH field value from a register. */
2493 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_GET(value) (((value) & 0x01000000) >> 24)
2494 /* Produces a ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH register field value suitable for setting the register. */
2495 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET(value) (((value) << 24) & 0x01000000)
2496 
2497 #ifndef __ASSEMBLY__
2498 /*
2499  * WARNING: The C register and register group struct declarations are provided for
2500  * convenience and illustrative purposes. They should, however, be used with
2501  * caution as the C language standard provides no guarantees about the alignment or
2502  * atomicity of device memory accesses. The recommended practice for writing
2503  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2504  * alt_write_word() functions.
2505  *
2506  * The struct declaration for register ALT_FPGAMGR_IMGCFG_CTL_02.
2507  */
2508 struct ALT_FPGAMGR_IMGCFG_CTL_02_s
2509 {
2510  uint32_t en_cfg_ctrl : 1; /* ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL */
2511  uint32_t : 7; /* *UNDEFINED* */
2512  uint32_t en_cfg_data : 1; /* ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA */
2513  uint32_t : 7; /* *UNDEFINED* */
2514  uint32_t cdratio : 2; /* CD Ratio */
2515  uint32_t : 6; /* *UNDEFINED* */
2516  uint32_t cfgwidth : 1; /* Configuration Data Width */
2517  uint32_t : 7; /* *UNDEFINED* */
2518 };
2519 
2520 /* The typedef declaration for register ALT_FPGAMGR_IMGCFG_CTL_02. */
2521 typedef volatile struct ALT_FPGAMGR_IMGCFG_CTL_02_s ALT_FPGAMGR_IMGCFG_CTL_02_t;
2522 #endif /* __ASSEMBLY__ */
2523 
2524 /* The reset value of the ALT_FPGAMGR_IMGCFG_CTL_02 register. */
2525 #define ALT_FPGAMGR_IMGCFG_CTL_02_RESET 0x00000200
2526 /* The byte offset of the ALT_FPGAMGR_IMGCFG_CTL_02 register from the beginning of the component. */
2527 #define ALT_FPGAMGR_IMGCFG_CTL_02_OFST 0x78
2528 
2529 /*
2530  * Register : imgcfg_stat
2531  *
2532  * This is the unmasked status.
2533  *
2534  * Value of corresponding inputs from CSS or PINs, without considering the
2535  * intr_mask or intr_polarity.
2536  *
2537  * Register Layout
2538  *
2539  * Bits | Access | Reset | Description
2540  * :--------|:-------|:------|:------------------------------------------
2541  * [0] | R | 0x0 | ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR
2542  * [1] | R | 0x0 | ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD
2543  * [2] | R | 0x0 | ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD
2544  * [3] | R | 0x0 | ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE
2545  * [4] | R | 0x0 | ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN
2546  * [5] | R | 0x0 | ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE
2547  * [6] | R | 0x0 | ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN
2548  * [7] | R | 0x0 | ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE
2549  * [8] | R | 0x0 | ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE
2550  * [9] | R | 0x0 | ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY
2551  * [10] | R | 0x0 | ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE
2552  * [11] | R | 0x0 | ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR
2553  * [12] | R | 0x0 | ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN
2554  * [13] | R | 0x0 | ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE
2555  * [15:14] | ??? | 0x0 | *UNDEFINED*
2556  * [16] | R | 0x0 | ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0
2557  * [17] | R | 0x0 | ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1
2558  * [18] | R | 0x0 | ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2
2559  * [23:19] | ??? | 0x0 | *UNDEFINED*
2560  * [24] | R | 0x1 | ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY
2561  * [25] | R | 0x0 | ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL
2562  * [27:26] | ??? | 0x0 | *UNDEFINED*
2563  * [28] | R | 0x0 | ALT_FPGAMGR_IMGCFG_STAT_JTAGM
2564  * [29] | R | 0x0 | ALT_FPGAMGR_IMGCFG_STAT_EMR
2565  * [31:30] | ??? | 0x0 | *UNDEFINED*
2566  *
2567  */
2568 /*
2569  * Field : f2s_crc_error
2570  *
2571  * Field Access Macros:
2572  *
2573  */
2574 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR register field. */
2575 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_LSB 0
2576 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR register field. */
2577 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_MSB 0
2578 /* The width in bits of the ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR register field. */
2579 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_WIDTH 1
2580 /* The mask used to set the ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR register field value. */
2581 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK 0x00000001
2582 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR register field value. */
2583 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_CLR_MSK 0xfffffffe
2584 /* The reset value of the ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR register field. */
2585 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_RESET 0x0
2586 /* Extracts the ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR field value from a register. */
2587 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_GET(value) (((value) & 0x00000001) >> 0)
2588 /* Produces a ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR register field value suitable for setting the register. */
2589 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET(value) (((value) << 0) & 0x00000001)
2590 
2591 /*
2592  * Field : f2s_early_usermode
2593  *
2594  * Field Access Macros:
2595  *
2596  */
2597 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD register field. */
2598 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_LSB 1
2599 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD register field. */
2600 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_MSB 1
2601 /* The width in bits of the ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD register field. */
2602 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_WIDTH 1
2603 /* The mask used to set the ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD register field value. */
2604 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_SET_MSK 0x00000002
2605 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD register field value. */
2606 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_CLR_MSK 0xfffffffd
2607 /* The reset value of the ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD register field. */
2608 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_RESET 0x0
2609 /* Extracts the ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD field value from a register. */
2610 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_GET(value) (((value) & 0x00000002) >> 1)
2611 /* Produces a ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD register field value suitable for setting the register. */
2612 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_SET(value) (((value) << 1) & 0x00000002)
2613 
2614 /*
2615  * Field : f2s_usermode
2616  *
2617  * Field Access Macros:
2618  *
2619  */
2620 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD register field. */
2621 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_LSB 2
2622 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD register field. */
2623 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_MSB 2
2624 /* The width in bits of the ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD register field. */
2625 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_WIDTH 1
2626 /* The mask used to set the ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD register field value. */
2627 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_SET_MSK 0x00000004
2628 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD register field value. */
2629 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_CLR_MSK 0xfffffffb
2630 /* The reset value of the ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD register field. */
2631 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_RESET 0x0
2632 /* Extracts the ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD field value from a register. */
2633 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_GET(value) (((value) & 0x00000004) >> 2)
2634 /* Produces a ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD register field value suitable for setting the register. */
2635 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_SET(value) (((value) << 2) & 0x00000004)
2636 
2637 /*
2638  * Field : f2s_initdone_oe
2639  *
2640  * Field Access Macros:
2641  *
2642  */
2643 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE register field. */
2644 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_LSB 3
2645 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE register field. */
2646 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_MSB 3
2647 /* The width in bits of the ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE register field. */
2648 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_WIDTH 1
2649 /* The mask used to set the ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE register field value. */
2650 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK 0x00000008
2651 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE register field value. */
2652 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_CLR_MSK 0xfffffff7
2653 /* The reset value of the ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE register field. */
2654 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_RESET 0x0
2655 /* Extracts the ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE field value from a register. */
2656 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_GET(value) (((value) & 0x00000008) >> 3)
2657 /* Produces a ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE register field value suitable for setting the register. */
2658 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET(value) (((value) << 3) & 0x00000008)
2659 
2660 /*
2661  * Field : f2s_nstatus_pin
2662  *
2663  * Field Access Macros:
2664  *
2665  */
2666 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN register field. */
2667 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_LSB 4
2668 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN register field. */
2669 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_MSB 4
2670 /* The width in bits of the ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN register field. */
2671 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_WIDTH 1
2672 /* The mask used to set the ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN register field value. */
2673 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_SET_MSK 0x00000010
2674 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN register field value. */
2675 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_CLR_MSK 0xffffffef
2676 /* The reset value of the ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN register field. */
2677 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_RESET 0x0
2678 /* Extracts the ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN field value from a register. */
2679 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_GET(value) (((value) & 0x00000010) >> 4)
2680 /* Produces a ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN register field value suitable for setting the register. */
2681 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_SET(value) (((value) << 4) & 0x00000010)
2682 
2683 /*
2684  * Field : f2s_nstatus_oe
2685  *
2686  * Field Access Macros:
2687  *
2688  */
2689 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE register field. */
2690 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_LSB 5
2691 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE register field. */
2692 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_MSB 5
2693 /* The width in bits of the ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE register field. */
2694 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_WIDTH 1
2695 /* The mask used to set the ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE register field value. */
2696 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_SET_MSK 0x00000020
2697 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE register field value. */
2698 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_CLR_MSK 0xffffffdf
2699 /* The reset value of the ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE register field. */
2700 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_RESET 0x0
2701 /* Extracts the ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE field value from a register. */
2702 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_GET(value) (((value) & 0x00000020) >> 5)
2703 /* Produces a ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE register field value suitable for setting the register. */
2704 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_SET(value) (((value) << 5) & 0x00000020)
2705 
2706 /*
2707  * Field : f2s_condone_pin
2708  *
2709  * Field Access Macros:
2710  *
2711  */
2712 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN register field. */
2713 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_LSB 6
2714 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN register field. */
2715 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_MSB 6
2716 /* The width in bits of the ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN register field. */
2717 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_WIDTH 1
2718 /* The mask used to set the ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN register field value. */
2719 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK 0x00000040
2720 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN register field value. */
2721 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_CLR_MSK 0xffffffbf
2722 /* The reset value of the ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN register field. */
2723 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_RESET 0x0
2724 /* Extracts the ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN field value from a register. */
2725 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_GET(value) (((value) & 0x00000040) >> 6)
2726 /* Produces a ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN register field value suitable for setting the register. */
2727 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET(value) (((value) << 6) & 0x00000040)
2728 
2729 /*
2730  * Field : f2s_condone_oe
2731  *
2732  * Field Access Macros:
2733  *
2734  */
2735 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE register field. */
2736 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_LSB 7
2737 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE register field. */
2738 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_MSB 7
2739 /* The width in bits of the ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE register field. */
2740 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_WIDTH 1
2741 /* The mask used to set the ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE register field value. */
2742 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK 0x00000080
2743 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE register field value. */
2744 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_CLR_MSK 0xffffff7f
2745 /* The reset value of the ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE register field. */
2746 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_RESET 0x0
2747 /* Extracts the ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE field value from a register. */
2748 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_GET(value) (((value) & 0x00000080) >> 7)
2749 /* Produces a ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE register field value suitable for setting the register. */
2750 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET(value) (((value) << 7) & 0x00000080)
2751 
2752 /*
2753  * Field : f2s_cvp_conf_done
2754  *
2755  * Field Access Macros:
2756  *
2757  */
2758 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE register field. */
2759 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_LSB 8
2760 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE register field. */
2761 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_MSB 8
2762 /* The width in bits of the ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE register field. */
2763 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_WIDTH 1
2764 /* The mask used to set the ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE register field value. */
2765 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK 0x00000100
2766 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE register field value. */
2767 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_CLR_MSK 0xfffffeff
2768 /* The reset value of the ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE register field. */
2769 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_RESET 0x0
2770 /* Extracts the ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE field value from a register. */
2771 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_GET(value) (((value) & 0x00000100) >> 8)
2772 /* Produces a ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE register field value suitable for setting the register. */
2773 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET(value) (((value) << 8) & 0x00000100)
2774 
2775 /*
2776  * Field : f2s_pr_ready
2777  *
2778  * Field Access Macros:
2779  *
2780  */
2781 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY register field. */
2782 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_LSB 9
2783 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY register field. */
2784 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_MSB 9
2785 /* The width in bits of the ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY register field. */
2786 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_WIDTH 1
2787 /* The mask used to set the ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY register field value. */
2788 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_SET_MSK 0x00000200
2789 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY register field value. */
2790 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_CLR_MSK 0xfffffdff
2791 /* The reset value of the ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY register field. */
2792 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_RESET 0x0
2793 /* Extracts the ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY field value from a register. */
2794 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_GET(value) (((value) & 0x00000200) >> 9)
2795 /* Produces a ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY register field value suitable for setting the register. */
2796 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_SET(value) (((value) << 9) & 0x00000200)
2797 
2798 /*
2799  * Field : f2s_pr_done
2800  *
2801  * Field Access Macros:
2802  *
2803  */
2804 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE register field. */
2805 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_LSB 10
2806 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE register field. */
2807 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_MSB 10
2808 /* The width in bits of the ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE register field. */
2809 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_WIDTH 1
2810 /* The mask used to set the ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE register field value. */
2811 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK 0x00000400
2812 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE register field value. */
2813 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_CLR_MSK 0xfffffbff
2814 /* The reset value of the ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE register field. */
2815 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_RESET 0x0
2816 /* Extracts the ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE field value from a register. */
2817 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_GET(value) (((value) & 0x00000400) >> 10)
2818 /* Produces a ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE register field value suitable for setting the register. */
2819 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET(value) (((value) << 10) & 0x00000400)
2820 
2821 /*
2822  * Field : f2s_pr_error
2823  *
2824  * Field Access Macros:
2825  *
2826  */
2827 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR register field. */
2828 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_LSB 11
2829 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR register field. */
2830 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_MSB 11
2831 /* The width in bits of the ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR register field. */
2832 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_WIDTH 1
2833 /* The mask used to set the ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR register field value. */
2834 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK 0x00000800
2835 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR register field value. */
2836 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_CLR_MSK 0xfffff7ff
2837 /* The reset value of the ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR register field. */
2838 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_RESET 0x0
2839 /* Extracts the ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR field value from a register. */
2840 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_GET(value) (((value) & 0x00000800) >> 11)
2841 /* Produces a ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR register field value suitable for setting the register. */
2842 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET(value) (((value) << 11) & 0x00000800)
2843 
2844 /*
2845  * Field : f2s_nconfig_pin
2846  *
2847  * Field Access Macros:
2848  *
2849  */
2850 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN register field. */
2851 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_LSB 12
2852 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN register field. */
2853 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_MSB 12
2854 /* The width in bits of the ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN register field. */
2855 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_WIDTH 1
2856 /* The mask used to set the ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN register field value. */
2857 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_SET_MSK 0x00001000
2858 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN register field value. */
2859 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_CLR_MSK 0xffffefff
2860 /* The reset value of the ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN register field. */
2861 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_RESET 0x0
2862 /* Extracts the ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN field value from a register. */
2863 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_GET(value) (((value) & 0x00001000) >> 12)
2864 /* Produces a ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN register field value suitable for setting the register. */
2865 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_SET(value) (((value) << 12) & 0x00001000)
2866 
2867 /*
2868  * Field : f2s_nceo_oe
2869  *
2870  * Field Access Macros:
2871  *
2872  */
2873 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE register field. */
2874 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_LSB 13
2875 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE register field. */
2876 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_MSB 13
2877 /* The width in bits of the ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE register field. */
2878 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_WIDTH 1
2879 /* The mask used to set the ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE register field value. */
2880 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK 0x00002000
2881 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE register field value. */
2882 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_CLR_MSK 0xffffdfff
2883 /* The reset value of the ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE register field. */
2884 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_RESET 0x0
2885 /* Extracts the ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE field value from a register. */
2886 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_GET(value) (((value) & 0x00002000) >> 13)
2887 /* Produces a ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE register field value suitable for setting the register. */
2888 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET(value) (((value) << 13) & 0x00002000)
2889 
2890 /*
2891  * Field : f2s_msel0
2892  *
2893  * This read-only field allows software to observe the MSEL inputs from the device
2894  * pins. The MSEL pins define the FPGA configuration mode.
2895  *
2896  * Please refer to CSS functional specifications for the exact definisions of MSEL
2897  * encoding.
2898  *
2899  * In Baum only 3 of these are used. Other bits will always read 0.
2900  *
2901  * Field Access Macros:
2902  *
2903  */
2904 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0 register field. */
2905 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16
2906 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0 register field. */
2907 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_MSB 16
2908 /* The width in bits of the ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0 register field. */
2909 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_WIDTH 1
2910 /* The mask used to set the ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0 register field value. */
2911 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK 0x00010000
2912 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0 register field value. */
2913 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_CLR_MSK 0xfffeffff
2914 /* The reset value of the ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0 register field. */
2915 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_RESET 0x0
2916 /* Extracts the ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0 field value from a register. */
2917 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_GET(value) (((value) & 0x00010000) >> 16)
2918 /* Produces a ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0 register field value suitable for setting the register. */
2919 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET(value) (((value) << 16) & 0x00010000)
2920 
2921 /*
2922  * Field : f2s_msel1
2923  *
2924  * This read-only field allows software to observe the MSEL inputs from the device
2925  * pins. The MSEL pins define the FPGA configuration mode.
2926  *
2927  * Please refer to CSS functional specifications for the exact definisions of MSEL
2928  * encoding.
2929  *
2930  * In Baum only 3 of these are used. Other bits will always read 0.
2931  *
2932  * Field Access Macros:
2933  *
2934  */
2935 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1 register field. */
2936 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_LSB 17
2937 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1 register field. */
2938 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_MSB 17
2939 /* The width in bits of the ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1 register field. */
2940 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_WIDTH 1
2941 /* The mask used to set the ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1 register field value. */
2942 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK 0x00020000
2943 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1 register field value. */
2944 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_CLR_MSK 0xfffdffff
2945 /* The reset value of the ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1 register field. */
2946 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_RESET 0x0
2947 /* Extracts the ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1 field value from a register. */
2948 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_GET(value) (((value) & 0x00020000) >> 17)
2949 /* Produces a ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1 register field value suitable for setting the register. */
2950 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET(value) (((value) << 17) & 0x00020000)
2951 
2952 /*
2953  * Field : f2s_msel2
2954  *
2955  * This read-only field allows software to observe the MSEL inputs from the device
2956  * pins. The MSEL pins define the FPGA configuration mode.
2957  *
2958  * Please refer to CSS functional specifications for the exact definisions of MSEL
2959  * encoding.
2960  *
2961  * In Baum only 3 of these are used. Other bits will always read 0.
2962  *
2963  * Field Access Macros:
2964  *
2965  */
2966 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2 register field. */
2967 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_LSB 18
2968 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2 register field. */
2969 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_MSB 18
2970 /* The width in bits of the ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2 register field. */
2971 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_WIDTH 1
2972 /* The mask used to set the ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2 register field value. */
2973 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK 0x00040000
2974 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2 register field value. */
2975 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_CLR_MSK 0xfffbffff
2976 /* The reset value of the ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2 register field. */
2977 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_RESET 0x0
2978 /* Extracts the ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2 field value from a register. */
2979 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_GET(value) (((value) & 0x00040000) >> 18)
2980 /* Produces a ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2 register field value suitable for setting the register. */
2981 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET(value) (((value) << 18) & 0x00040000)
2982 
2983 /*
2984  * Field : imgcfg_FifoEmpty
2985  *
2986  * FIfoEmpty Status of FPGA image configuration FIFO
2987  *
2988  * Field Access Macros:
2989  *
2990  */
2991 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY register field. */
2992 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_LSB 24
2993 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY register field. */
2994 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_MSB 24
2995 /* The width in bits of the ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY register field. */
2996 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_WIDTH 1
2997 /* The mask used to set the ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY register field value. */
2998 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_SET_MSK 0x01000000
2999 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY register field value. */
3000 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_CLR_MSK 0xfeffffff
3001 /* The reset value of the ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY register field. */
3002 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_RESET 0x1
3003 /* Extracts the ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY field value from a register. */
3004 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_GET(value) (((value) & 0x01000000) >> 24)
3005 /* Produces a ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY register field value suitable for setting the register. */
3006 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_SET(value) (((value) << 24) & 0x01000000)
3007 
3008 /*
3009  * Field : imgcfg_FifoFull
3010  *
3011  * FIfoFull Status of FPGA image configuration FIFO
3012  *
3013  * Field Access Macros:
3014  *
3015  */
3016 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL register field. */
3017 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_LSB 25
3018 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL register field. */
3019 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_MSB 25
3020 /* The width in bits of the ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL register field. */
3021 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_WIDTH 1
3022 /* The mask used to set the ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL register field value. */
3023 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_SET_MSK 0x02000000
3024 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL register field value. */
3025 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_CLR_MSK 0xfdffffff
3026 /* The reset value of the ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL register field. */
3027 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_RESET 0x0
3028 /* Extracts the ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL field value from a register. */
3029 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_GET(value) (((value) & 0x02000000) >> 25)
3030 /* Produces a ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL register field value suitable for setting the register. */
3031 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_SET(value) (((value) << 25) & 0x02000000)
3032 
3033 /*
3034  * Field : jtagm
3035  *
3036  * JTAG Master Session Status
3037  *
3038  * Field Access Macros:
3039  *
3040  */
3041 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_STAT_JTAGM register field. */
3042 #define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_LSB 28
3043 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_STAT_JTAGM register field. */
3044 #define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_MSB 28
3045 /* The width in bits of the ALT_FPGAMGR_IMGCFG_STAT_JTAGM register field. */
3046 #define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_WIDTH 1
3047 /* The mask used to set the ALT_FPGAMGR_IMGCFG_STAT_JTAGM register field value. */
3048 #define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_SET_MSK 0x10000000
3049 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_STAT_JTAGM register field value. */
3050 #define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_CLR_MSK 0xefffffff
3051 /* The reset value of the ALT_FPGAMGR_IMGCFG_STAT_JTAGM register field. */
3052 #define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_RESET 0x0
3053 /* Extracts the ALT_FPGAMGR_IMGCFG_STAT_JTAGM field value from a register. */
3054 #define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_GET(value) (((value) & 0x10000000) >> 28)
3055 /* Produces a ALT_FPGAMGR_IMGCFG_STAT_JTAGM register field value suitable for setting the register. */
3056 #define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_SET(value) (((value) << 28) & 0x10000000)
3057 
3058 /*
3059  * Field : emr
3060  *
3061  * EMR valid bit
3062  *
3063  * Field Access Macros:
3064  *
3065  */
3066 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_STAT_EMR register field. */
3067 #define ALT_FPGAMGR_IMGCFG_STAT_EMR_LSB 29
3068 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_STAT_EMR register field. */
3069 #define ALT_FPGAMGR_IMGCFG_STAT_EMR_MSB 29
3070 /* The width in bits of the ALT_FPGAMGR_IMGCFG_STAT_EMR register field. */
3071 #define ALT_FPGAMGR_IMGCFG_STAT_EMR_WIDTH 1
3072 /* The mask used to set the ALT_FPGAMGR_IMGCFG_STAT_EMR register field value. */
3073 #define ALT_FPGAMGR_IMGCFG_STAT_EMR_SET_MSK 0x20000000
3074 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_STAT_EMR register field value. */
3075 #define ALT_FPGAMGR_IMGCFG_STAT_EMR_CLR_MSK 0xdfffffff
3076 /* The reset value of the ALT_FPGAMGR_IMGCFG_STAT_EMR register field. */
3077 #define ALT_FPGAMGR_IMGCFG_STAT_EMR_RESET 0x0
3078 /* Extracts the ALT_FPGAMGR_IMGCFG_STAT_EMR field value from a register. */
3079 #define ALT_FPGAMGR_IMGCFG_STAT_EMR_GET(value) (((value) & 0x20000000) >> 29)
3080 /* Produces a ALT_FPGAMGR_IMGCFG_STAT_EMR register field value suitable for setting the register. */
3081 #define ALT_FPGAMGR_IMGCFG_STAT_EMR_SET(value) (((value) << 29) & 0x20000000)
3082 
3083 #ifndef __ASSEMBLY__
3084 /*
3085  * WARNING: The C register and register group struct declarations are provided for
3086  * convenience and illustrative purposes. They should, however, be used with
3087  * caution as the C language standard provides no guarantees about the alignment or
3088  * atomicity of device memory accesses. The recommended practice for writing
3089  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3090  * alt_write_word() functions.
3091  *
3092  * The struct declaration for register ALT_FPGAMGR_IMGCFG_STAT.
3093  */
3094 struct ALT_FPGAMGR_IMGCFG_STAT_s
3095 {
3096  const uint32_t f2s_crc_error : 1; /* ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR */
3097  const uint32_t f2s_early_usermode : 1; /* ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD */
3098  const uint32_t f2s_usermode : 1; /* ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD */
3099  const uint32_t f2s_initdone_oe : 1; /* ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE */
3100  const uint32_t f2s_nstatus_pin : 1; /* ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN */
3101  const uint32_t f2s_nstatus_oe : 1; /* ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE */
3102  const uint32_t f2s_condone_pin : 1; /* ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN */
3103  const uint32_t f2s_condone_oe : 1; /* ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE */
3104  const uint32_t f2s_cvp_conf_done : 1; /* ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE */
3105  const uint32_t f2s_pr_ready : 1; /* ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY */
3106  const uint32_t f2s_pr_done : 1; /* ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE */
3107  const uint32_t f2s_pr_error : 1; /* ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR */
3108  const uint32_t f2s_nconfig_pin : 1; /* ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN */
3109  const uint32_t f2s_nceo_oe : 1; /* ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE */
3110  uint32_t : 2; /* *UNDEFINED* */
3111  const uint32_t f2s_msel0 : 1; /* ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0 */
3112  const uint32_t f2s_msel1 : 1; /* ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1 */
3113  const uint32_t f2s_msel2 : 1; /* ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2 */
3114  uint32_t : 5; /* *UNDEFINED* */
3115  const uint32_t imgcfg_FifoEmpty : 1; /* ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY */
3116  const uint32_t imgcfg_FifoFull : 1; /* ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL */
3117  uint32_t : 2; /* *UNDEFINED* */
3118  const uint32_t jtagm : 1; /* ALT_FPGAMGR_IMGCFG_STAT_JTAGM */
3119  const uint32_t emr : 1; /* ALT_FPGAMGR_IMGCFG_STAT_EMR */
3120  uint32_t : 2; /* *UNDEFINED* */
3121 };
3122 
3123 /* The typedef declaration for register ALT_FPGAMGR_IMGCFG_STAT. */
3124 typedef volatile struct ALT_FPGAMGR_IMGCFG_STAT_s ALT_FPGAMGR_IMGCFG_STAT_t;
3125 #endif /* __ASSEMBLY__ */
3126 
3127 /* The reset value of the ALT_FPGAMGR_IMGCFG_STAT register. */
3128 #define ALT_FPGAMGR_IMGCFG_STAT_RESET 0x01000000
3129 /* The byte offset of the ALT_FPGAMGR_IMGCFG_STAT register from the beginning of the component. */
3130 #define ALT_FPGAMGR_IMGCFG_STAT_OFST 0x80
3131 
3132 /*
3133  * Register : intr_masked_status
3134  *
3135  * When you read this register you read the active high pending interrupt status of
3136  * corresponding bit.
3137  *
3138  * This value is after the masking specified by intr_mask and after the polarity
3139  * conversion as specified in intr_polarity
3140  *
3141  * Register Layout
3142  *
3143  * Bits | Access | Reset | Description
3144  * :--------|:-------|:------|:----------------------------------------------
3145  * [0] | RW | 0x0 | ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR
3146  * [1] | RW | 0x0 | ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD
3147  * [2] | RW | 0x0 | ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD
3148  * [3] | RW | 0x0 | ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE
3149  * [4] | RW | 0x0 | ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN
3150  * [5] | RW | 0x0 | ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE
3151  * [6] | RW | 0x0 | ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN
3152  * [7] | RW | 0x0 | ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE
3153  * [8] | RW | 0x0 | ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE
3154  * [9] | RW | 0x0 | ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY
3155  * [10] | RW | 0x0 | ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE
3156  * [11] | RW | 0x0 | ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR
3157  * [12] | RW | 0x0 | ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN
3158  * [13] | RW | 0x0 | ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE
3159  * [15:14] | ??? | 0x0 | *UNDEFINED*
3160  * [16] | RW | 0x0 | ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0
3161  * [17] | RW | 0x0 | ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1
3162  * [18] | RW | 0x0 | ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2
3163  * [23:19] | ??? | 0x0 | *UNDEFINED*
3164  * [24] | RW | 0x0 | ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY
3165  * [25] | RW | 0x0 | ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL
3166  * [27:26] | ??? | 0x0 | *UNDEFINED*
3167  * [28] | RW | 0x0 | ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM
3168  * [29] | RW | 0x0 | ALT_FPGAMGR_INTR_MSKED_STAT_EMR
3169  * [31:30] | ??? | 0x0 | *UNDEFINED*
3170  *
3171  */
3172 /*
3173  * Field : f2s_crc_error
3174  *
3175  * Field Access Macros:
3176  *
3177  */
3178 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR register field. */
3179 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_LSB 0
3180 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR register field. */
3181 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_MSB 0
3182 /* The width in bits of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR register field. */
3183 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_WIDTH 1
3184 /* The mask used to set the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR register field value. */
3185 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_SET_MSK 0x00000001
3186 /* The mask used to clear the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR register field value. */
3187 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_CLR_MSK 0xfffffffe
3188 /* The reset value of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR register field. */
3189 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_RESET 0x0
3190 /* Extracts the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR field value from a register. */
3191 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_GET(value) (((value) & 0x00000001) >> 0)
3192 /* Produces a ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR register field value suitable for setting the register. */
3193 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_SET(value) (((value) << 0) & 0x00000001)
3194 
3195 /*
3196  * Field : f2s_early_usermode
3197  *
3198  * Field Access Macros:
3199  *
3200  */
3201 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD register field. */
3202 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_LSB 1
3203 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD register field. */
3204 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_MSB 1
3205 /* The width in bits of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD register field. */
3206 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_WIDTH 1
3207 /* The mask used to set the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD register field value. */
3208 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_SET_MSK 0x00000002
3209 /* The mask used to clear the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD register field value. */
3210 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_CLR_MSK 0xfffffffd
3211 /* The reset value of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD register field. */
3212 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_RESET 0x0
3213 /* Extracts the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD field value from a register. */
3214 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_GET(value) (((value) & 0x00000002) >> 1)
3215 /* Produces a ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD register field value suitable for setting the register. */
3216 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_SET(value) (((value) << 1) & 0x00000002)
3217 
3218 /*
3219  * Field : f2s_usermode
3220  *
3221  * Field Access Macros:
3222  *
3223  */
3224 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD register field. */
3225 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_LSB 2
3226 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD register field. */
3227 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_MSB 2
3228 /* The width in bits of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD register field. */
3229 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_WIDTH 1
3230 /* The mask used to set the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD register field value. */
3231 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_SET_MSK 0x00000004
3232 /* The mask used to clear the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD register field value. */
3233 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_CLR_MSK 0xfffffffb
3234 /* The reset value of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD register field. */
3235 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_RESET 0x0
3236 /* Extracts the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD field value from a register. */
3237 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_GET(value) (((value) & 0x00000004) >> 2)
3238 /* Produces a ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD register field value suitable for setting the register. */
3239 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_SET(value) (((value) << 2) & 0x00000004)
3240 
3241 /*
3242  * Field : f2s_initdone_oe
3243  *
3244  * Field Access Macros:
3245  *
3246  */
3247 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE register field. */
3248 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_LSB 3
3249 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE register field. */
3250 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_MSB 3
3251 /* The width in bits of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE register field. */
3252 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_WIDTH 1
3253 /* The mask used to set the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE register field value. */
3254 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_SET_MSK 0x00000008
3255 /* The mask used to clear the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE register field value. */
3256 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_CLR_MSK 0xfffffff7
3257 /* The reset value of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE register field. */
3258 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_RESET 0x0
3259 /* Extracts the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE field value from a register. */
3260 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_GET(value) (((value) & 0x00000008) >> 3)
3261 /* Produces a ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE register field value suitable for setting the register. */
3262 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_SET(value) (((value) << 3) & 0x00000008)
3263 
3264 /*
3265  * Field : f2s_nstatus_pin
3266  *
3267  * Field Access Macros:
3268  *
3269  */
3270 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN register field. */
3271 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_LSB 4
3272 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN register field. */
3273 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_MSB 4
3274 /* The width in bits of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN register field. */
3275 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_WIDTH 1
3276 /* The mask used to set the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN register field value. */
3277 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_SET_MSK 0x00000010
3278 /* The mask used to clear the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN register field value. */
3279 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_CLR_MSK 0xffffffef
3280 /* The reset value of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN register field. */
3281 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_RESET 0x0
3282 /* Extracts the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN field value from a register. */
3283 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_GET(value) (((value) & 0x00000010) >> 4)
3284 /* Produces a ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN register field value suitable for setting the register. */
3285 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_SET(value) (((value) << 4) & 0x00000010)
3286 
3287 /*
3288  * Field : f2s_nstatus_oe
3289  *
3290  * Field Access Macros:
3291  *
3292  */
3293 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE register field. */
3294 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_LSB 5
3295 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE register field. */
3296 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_MSB 5
3297 /* The width in bits of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE register field. */
3298 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_WIDTH 1
3299 /* The mask used to set the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE register field value. */
3300 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_SET_MSK 0x00000020
3301 /* The mask used to clear the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE register field value. */
3302 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_CLR_MSK 0xffffffdf
3303 /* The reset value of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE register field. */
3304 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_RESET 0x0
3305 /* Extracts the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE field value from a register. */
3306 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_GET(value) (((value) & 0x00000020) >> 5)
3307 /* Produces a ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE register field value suitable for setting the register. */
3308 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_SET(value) (((value) << 5) & 0x00000020)
3309 
3310 /*
3311  * Field : f2s_condone_pin
3312  *
3313  * Field Access Macros:
3314  *
3315  */
3316 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN register field. */
3317 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_LSB 6
3318 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN register field. */
3319 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_MSB 6
3320 /* The width in bits of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN register field. */
3321 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_WIDTH 1
3322 /* The mask used to set the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN register field value. */
3323 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_SET_MSK 0x00000040
3324 /* The mask used to clear the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN register field value. */
3325 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_CLR_MSK 0xffffffbf
3326 /* The reset value of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN register field. */
3327 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_RESET 0x0
3328 /* Extracts the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN field value from a register. */
3329 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_GET(value) (((value) & 0x00000040) >> 6)
3330 /* Produces a ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN register field value suitable for setting the register. */
3331 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_SET(value) (((value) << 6) & 0x00000040)
3332 
3333 /*
3334  * Field : f2s_condone_oe
3335  *
3336  * Field Access Macros:
3337  *
3338  */
3339 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE register field. */
3340 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_LSB 7
3341 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE register field. */
3342 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_MSB 7
3343 /* The width in bits of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE register field. */
3344 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_WIDTH 1
3345 /* The mask used to set the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE register field value. */
3346 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_SET_MSK 0x00000080
3347 /* The mask used to clear the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE register field value. */
3348 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_CLR_MSK 0xffffff7f
3349 /* The reset value of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE register field. */
3350 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_RESET 0x0
3351 /* Extracts the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE field value from a register. */
3352 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_GET(value) (((value) & 0x00000080) >> 7)
3353 /* Produces a ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE register field value suitable for setting the register. */
3354 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_SET(value) (((value) << 7) & 0x00000080)
3355 
3356 /*
3357  * Field : f2s_cvp_conf_done
3358  *
3359  * Field Access Macros:
3360  *
3361  */
3362 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE register field. */
3363 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_LSB 8
3364 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE register field. */
3365 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_MSB 8
3366 /* The width in bits of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE register field. */
3367 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_WIDTH 1
3368 /* The mask used to set the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE register field value. */
3369 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_SET_MSK 0x00000100
3370 /* The mask used to clear the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE register field value. */
3371 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_CLR_MSK 0xfffffeff
3372 /* The reset value of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE register field. */
3373 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_RESET 0x0
3374 /* Extracts the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE field value from a register. */
3375 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_GET(value) (((value) & 0x00000100) >> 8)
3376 /* Produces a ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE register field value suitable for setting the register. */
3377 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_SET(value) (((value) << 8) & 0x00000100)
3378 
3379 /*
3380  * Field : f2s_pr_ready
3381  *
3382  * Field Access Macros:
3383  *
3384  */
3385 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY register field. */
3386 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_LSB 9
3387 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY register field. */
3388 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_MSB 9
3389 /* The width in bits of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY register field. */
3390 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_WIDTH 1
3391 /* The mask used to set the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY register field value. */
3392 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_SET_MSK 0x00000200
3393 /* The mask used to clear the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY register field value. */
3394 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_CLR_MSK 0xfffffdff
3395 /* The reset value of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY register field. */
3396 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_RESET 0x0
3397 /* Extracts the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY field value from a register. */
3398 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_GET(value) (((value) & 0x00000200) >> 9)
3399 /* Produces a ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY register field value suitable for setting the register. */
3400 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_SET(value) (((value) << 9) & 0x00000200)
3401 
3402 /*
3403  * Field : f2s_pr_done
3404  *
3405  * Field Access Macros:
3406  *
3407  */
3408 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE register field. */
3409 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_LSB 10
3410 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE register field. */
3411 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_MSB 10
3412 /* The width in bits of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE register field. */
3413 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_WIDTH 1
3414 /* The mask used to set the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE register field value. */
3415 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_SET_MSK 0x00000400
3416 /* The mask used to clear the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE register field value. */
3417 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_CLR_MSK 0xfffffbff
3418 /* The reset value of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE register field. */
3419 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_RESET 0x0
3420 /* Extracts the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE field value from a register. */
3421 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_GET(value) (((value) & 0x00000400) >> 10)
3422 /* Produces a ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE register field value suitable for setting the register. */
3423 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_SET(value) (((value) << 10) & 0x00000400)
3424 
3425 /*
3426  * Field : f2s_pr_error
3427  *
3428  * Field Access Macros:
3429  *
3430  */
3431 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR register field. */
3432 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_LSB 11
3433 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR register field. */
3434 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_MSB 11
3435 /* The width in bits of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR register field. */
3436 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_WIDTH 1
3437 /* The mask used to set the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR register field value. */
3438 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_SET_MSK 0x00000800
3439 /* The mask used to clear the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR register field value. */
3440 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_CLR_MSK 0xfffff7ff
3441 /* The reset value of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR register field. */
3442 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_RESET 0x0
3443 /* Extracts the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR field value from a register. */
3444 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_GET(value) (((value) & 0x00000800) >> 11)
3445 /* Produces a ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR register field value suitable for setting the register. */
3446 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_SET(value) (((value) << 11) & 0x00000800)
3447 
3448 /*
3449  * Field : f2s_nconfig_pin
3450  *
3451  * Field Access Macros:
3452  *
3453  */
3454 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN register field. */
3455 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_LSB 12
3456 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN register field. */
3457 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_MSB 12
3458 /* The width in bits of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN register field. */
3459 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_WIDTH 1
3460 /* The mask used to set the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN register field value. */
3461 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_SET_MSK 0x00001000
3462 /* The mask used to clear the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN register field value. */
3463 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_CLR_MSK 0xffffefff
3464 /* The reset value of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN register field. */
3465 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_RESET 0x0
3466 /* Extracts the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN field value from a register. */
3467 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_GET(value) (((value) & 0x00001000) >> 12)
3468 /* Produces a ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN register field value suitable for setting the register. */
3469 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_SET(value) (((value) << 12) & 0x00001000)
3470 
3471 /*
3472  * Field : f2s_nceo_oe
3473  *
3474  * Field Access Macros:
3475  *
3476  */
3477 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE register field. */
3478 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_LSB 13
3479 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE register field. */
3480 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_MSB 13
3481 /* The width in bits of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE register field. */
3482 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_WIDTH 1
3483 /* The mask used to set the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE register field value. */
3484 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_SET_MSK 0x00002000
3485 /* The mask used to clear the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE register field value. */
3486 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_CLR_MSK 0xffffdfff
3487 /* The reset value of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE register field. */
3488 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_RESET 0x0
3489 /* Extracts the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE field value from a register. */
3490 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_GET(value) (((value) & 0x00002000) >> 13)
3491 /* Produces a ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE register field value suitable for setting the register. */
3492 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_SET(value) (((value) << 13) & 0x00002000)
3493 
3494 /*
3495  * Field : f2s_msel0
3496  *
3497  * Field Access Macros:
3498  *
3499  */
3500 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0 register field. */
3501 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_LSB 16
3502 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0 register field. */
3503 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_MSB 16
3504 /* The width in bits of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0 register field. */
3505 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_WIDTH 1
3506 /* The mask used to set the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0 register field value. */
3507 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_SET_MSK 0x00010000
3508 /* The mask used to clear the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0 register field value. */
3509 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_CLR_MSK 0xfffeffff
3510 /* The reset value of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0 register field. */
3511 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_RESET 0x0
3512 /* Extracts the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0 field value from a register. */
3513 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_GET(value) (((value) & 0x00010000) >> 16)
3514 /* Produces a ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0 register field value suitable for setting the register. */
3515 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_SET(value) (((value) << 16) & 0x00010000)
3516 
3517 /*
3518  * Field : f2s_msel1
3519  *
3520  * Field Access Macros:
3521  *
3522  */
3523 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1 register field. */
3524 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_LSB 17
3525 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1 register field. */
3526 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_MSB 17
3527 /* The width in bits of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1 register field. */
3528 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_WIDTH 1
3529 /* The mask used to set the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1 register field value. */
3530 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_SET_MSK 0x00020000
3531 /* The mask used to clear the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1 register field value. */
3532 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_CLR_MSK 0xfffdffff
3533 /* The reset value of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1 register field. */
3534 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_RESET 0x0
3535 /* Extracts the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1 field value from a register. */
3536 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_GET(value) (((value) & 0x00020000) >> 17)
3537 /* Produces a ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1 register field value suitable for setting the register. */
3538 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_SET(value) (((value) << 17) & 0x00020000)
3539 
3540 /*
3541  * Field : f2s_msel2
3542  *
3543  * Field Access Macros:
3544  *
3545  */
3546 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2 register field. */
3547 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_LSB 18
3548 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2 register field. */
3549 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_MSB 18
3550 /* The width in bits of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2 register field. */
3551 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_WIDTH 1
3552 /* The mask used to set the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2 register field value. */
3553 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_SET_MSK 0x00040000
3554 /* The mask used to clear the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2 register field value. */
3555 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_CLR_MSK 0xfffbffff
3556 /* The reset value of the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2 register field. */
3557 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_RESET 0x0
3558 /* Extracts the ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2 field value from a register. */
3559 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_GET(value) (((value) & 0x00040000) >> 18)
3560 /* Produces a ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2 register field value suitable for setting the register. */
3561 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_SET(value) (((value) << 18) & 0x00040000)
3562 
3563 /*
3564  * Field : imgcfg_FifoEmpty
3565  *
3566  * FIfoEmpty Status of FPGA image configuration FIFO
3567  *
3568  * Field Access Macros:
3569  *
3570  */
3571 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY register field. */
3572 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_LSB 24
3573 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY register field. */
3574 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_MSB 24
3575 /* The width in bits of the ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY register field. */
3576 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_WIDTH 1
3577 /* The mask used to set the ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY register field value. */
3578 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_SET_MSK 0x01000000
3579 /* The mask used to clear the ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY register field value. */
3580 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_CLR_MSK 0xfeffffff
3581 /* The reset value of the ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY register field. */
3582 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_RESET 0x0
3583 /* Extracts the ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY field value from a register. */
3584 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_GET(value) (((value) & 0x01000000) >> 24)
3585 /* Produces a ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY register field value suitable for setting the register. */
3586 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_SET(value) (((value) << 24) & 0x01000000)
3587 
3588 /*
3589  * Field : imgcfg_FifoFull
3590  *
3591  * FIfoFull Status of FPGA image configuration FIFO
3592  *
3593  * Field Access Macros:
3594  *
3595  */
3596 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL register field. */
3597 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_LSB 25
3598 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL register field. */
3599 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_MSB 25
3600 /* The width in bits of the ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL register field. */
3601 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_WIDTH 1
3602 /* The mask used to set the ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL register field value. */
3603 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_SET_MSK 0x02000000
3604 /* The mask used to clear the ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL register field value. */
3605 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_CLR_MSK 0xfdffffff
3606 /* The reset value of the ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL register field. */
3607 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_RESET 0x0
3608 /* Extracts the ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL field value from a register. */
3609 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_GET(value) (((value) & 0x02000000) >> 25)
3610 /* Produces a ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL register field value suitable for setting the register. */
3611 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_SET(value) (((value) << 25) & 0x02000000)
3612 
3613 /*
3614  * Field : jtagm
3615  *
3616  * JTAG Master Session Status
3617  *
3618  * Field Access Macros:
3619  *
3620  */
3621 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM register field. */
3622 #define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_LSB 28
3623 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM register field. */
3624 #define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_MSB 28
3625 /* The width in bits of the ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM register field. */
3626 #define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_WIDTH 1
3627 /* The mask used to set the ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM register field value. */
3628 #define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_SET_MSK 0x10000000
3629 /* The mask used to clear the ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM register field value. */
3630 #define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_CLR_MSK 0xefffffff
3631 /* The reset value of the ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM register field. */
3632 #define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_RESET 0x0
3633 /* Extracts the ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM field value from a register. */
3634 #define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_GET(value) (((value) & 0x10000000) >> 28)
3635 /* Produces a ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM register field value suitable for setting the register. */
3636 #define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_SET(value) (((value) << 28) & 0x10000000)
3637 
3638 /*
3639  * Field : emr
3640  *
3641  * EMR valid bit
3642  *
3643  * Field Access Macros:
3644  *
3645  */
3646 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_EMR register field. */
3647 #define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_LSB 29
3648 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSKED_STAT_EMR register field. */
3649 #define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_MSB 29
3650 /* The width in bits of the ALT_FPGAMGR_INTR_MSKED_STAT_EMR register field. */
3651 #define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_WIDTH 1
3652 /* The mask used to set the ALT_FPGAMGR_INTR_MSKED_STAT_EMR register field value. */
3653 #define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_SET_MSK 0x20000000
3654 /* The mask used to clear the ALT_FPGAMGR_INTR_MSKED_STAT_EMR register field value. */
3655 #define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_CLR_MSK 0xdfffffff
3656 /* The reset value of the ALT_FPGAMGR_INTR_MSKED_STAT_EMR register field. */
3657 #define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_RESET 0x0
3658 /* Extracts the ALT_FPGAMGR_INTR_MSKED_STAT_EMR field value from a register. */
3659 #define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_GET(value) (((value) & 0x20000000) >> 29)
3660 /* Produces a ALT_FPGAMGR_INTR_MSKED_STAT_EMR register field value suitable for setting the register. */
3661 #define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_SET(value) (((value) << 29) & 0x20000000)
3662 
3663 #ifndef __ASSEMBLY__
3664 /*
3665  * WARNING: The C register and register group struct declarations are provided for
3666  * convenience and illustrative purposes. They should, however, be used with
3667  * caution as the C language standard provides no guarantees about the alignment or
3668  * atomicity of device memory accesses. The recommended practice for writing
3669  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3670  * alt_write_word() functions.
3671  *
3672  * The struct declaration for register ALT_FPGAMGR_INTR_MSKED_STAT.
3673  */
3674 struct ALT_FPGAMGR_INTR_MSKED_STAT_s
3675 {
3676  uint32_t f2s_crc_error : 1; /* ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR */
3677  uint32_t f2s_early_usermode : 1; /* ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD */
3678  uint32_t f2s_usermode : 1; /* ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD */
3679  uint32_t f2s_initdone_oe : 1; /* ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE */
3680  uint32_t f2s_nstatus_pin : 1; /* ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN */
3681  uint32_t f2s_nstatus_oe : 1; /* ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE */
3682  uint32_t f2s_condone_pin : 1; /* ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN */
3683  uint32_t f2s_condone_oe : 1; /* ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE */
3684  uint32_t f2s_cvp_conf_done : 1; /* ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE */
3685  uint32_t f2s_pr_ready : 1; /* ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY */
3686  uint32_t f2s_pr_done : 1; /* ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE */
3687  uint32_t f2s_pr_error : 1; /* ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR */
3688  uint32_t f2s_nconfig_pin : 1; /* ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN */
3689  uint32_t f2s_nceo_oe : 1; /* ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE */
3690  uint32_t : 2; /* *UNDEFINED* */
3691  uint32_t f2s_msel0 : 1; /* ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0 */
3692  uint32_t f2s_msel1 : 1; /* ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1 */
3693  uint32_t f2s_msel2 : 1; /* ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2 */
3694  uint32_t : 5; /* *UNDEFINED* */
3695  uint32_t imgcfg_FifoEmpty : 1; /* ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY */
3696  uint32_t imgcfg_FifoFull : 1; /* ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL */
3697  uint32_t : 2; /* *UNDEFINED* */
3698  uint32_t jtagm : 1; /* ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM */
3699  uint32_t emr : 1; /* ALT_FPGAMGR_INTR_MSKED_STAT_EMR */
3700  uint32_t : 2; /* *UNDEFINED* */
3701 };
3702 
3703 /* The typedef declaration for register ALT_FPGAMGR_INTR_MSKED_STAT. */
3704 typedef volatile struct ALT_FPGAMGR_INTR_MSKED_STAT_s ALT_FPGAMGR_INTR_MSKED_STAT_t;
3705 #endif /* __ASSEMBLY__ */
3706 
3707 /* The reset value of the ALT_FPGAMGR_INTR_MSKED_STAT register. */
3708 #define ALT_FPGAMGR_INTR_MSKED_STAT_RESET 0x00000000
3709 /* The byte offset of the ALT_FPGAMGR_INTR_MSKED_STAT register from the beginning of the component. */
3710 #define ALT_FPGAMGR_INTR_MSKED_STAT_OFST 0x84
3711 
3712 /*
3713  * Register : intr_mask
3714  *
3715  * Mask for interrupts. A value of 1 in a particular bit will cause the specific
3716  * interrupt to be masked.
3717  *
3718  * Register Layout
3719  *
3720  * Bits | Access | Reset | Description
3721  * :--------|:-------|:------|:---------------------------------------
3722  * [0] | RW | 0x1 | ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR
3723  * [1] | RW | 0x1 | ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD
3724  * [2] | RW | 0x1 | ALT_FPGAMGR_INTR_MSK_F2S_USERMOD
3725  * [3] | RW | 0x1 | ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE
3726  * [4] | RW | 0x1 | ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN
3727  * [5] | RW | 0x1 | ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE
3728  * [6] | RW | 0x1 | ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN
3729  * [7] | RW | 0x1 | ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE
3730  * [8] | RW | 0x1 | ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE
3731  * [9] | RW | 0x1 | ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY
3732  * [10] | RW | 0x1 | ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE
3733  * [11] | RW | 0x1 | ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR
3734  * [12] | RW | 0x1 | ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN
3735  * [13] | RW | 0x1 | ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE
3736  * [15:14] | ??? | 0x0 | *UNDEFINED*
3737  * [16] | RW | 0x1 | ALT_FPGAMGR_INTR_MSK_F2S_MSEL0
3738  * [17] | RW | 0x1 | ALT_FPGAMGR_INTR_MSK_F2S_MSEL1
3739  * [18] | RW | 0x1 | ALT_FPGAMGR_INTR_MSK_F2S_MSEL2
3740  * [23:19] | ??? | 0x0 | *UNDEFINED*
3741  * [24] | RW | 0x1 | ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY
3742  * [25] | RW | 0x1 | ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL
3743  * [27:26] | ??? | 0x0 | *UNDEFINED*
3744  * [28] | RW | 0x1 | ALT_FPGAMGR_INTR_MSK_JTAGM
3745  * [29] | RW | 0x1 | ALT_FPGAMGR_INTR_MSK_EMR
3746  * [31:30] | ??? | 0x0 | *UNDEFINED*
3747  *
3748  */
3749 /*
3750  * Field : f2s_crc_error
3751  *
3752  * Field Access Macros:
3753  *
3754  */
3755 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR register field. */
3756 #define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_LSB 0
3757 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR register field. */
3758 #define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_MSB 0
3759 /* The width in bits of the ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR register field. */
3760 #define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_WIDTH 1
3761 /* The mask used to set the ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR register field value. */
3762 #define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_SET_MSK 0x00000001
3763 /* The mask used to clear the ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR register field value. */
3764 #define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_CLR_MSK 0xfffffffe
3765 /* The reset value of the ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR register field. */
3766 #define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_RESET 0x1
3767 /* Extracts the ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR field value from a register. */
3768 #define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_GET(value) (((value) & 0x00000001) >> 0)
3769 /* Produces a ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR register field value suitable for setting the register. */
3770 #define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_SET(value) (((value) << 0) & 0x00000001)
3771 
3772 /*
3773  * Field : f2s_early_usermode
3774  *
3775  * Field Access Macros:
3776  *
3777  */
3778 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD register field. */
3779 #define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_LSB 1
3780 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD register field. */
3781 #define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_MSB 1
3782 /* The width in bits of the ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD register field. */
3783 #define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_WIDTH 1
3784 /* The mask used to set the ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD register field value. */
3785 #define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_SET_MSK 0x00000002
3786 /* The mask used to clear the ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD register field value. */
3787 #define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_CLR_MSK 0xfffffffd
3788 /* The reset value of the ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD register field. */
3789 #define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_RESET 0x1
3790 /* Extracts the ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD field value from a register. */
3791 #define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_GET(value) (((value) & 0x00000002) >> 1)
3792 /* Produces a ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD register field value suitable for setting the register. */
3793 #define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_SET(value) (((value) << 1) & 0x00000002)
3794 
3795 /*
3796  * Field : f2s_usermode
3797  *
3798  * Field Access Macros:
3799  *
3800  */
3801 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_USERMOD register field. */
3802 #define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_LSB 2
3803 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_USERMOD register field. */
3804 #define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_MSB 2
3805 /* The width in bits of the ALT_FPGAMGR_INTR_MSK_F2S_USERMOD register field. */
3806 #define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_WIDTH 1
3807 /* The mask used to set the ALT_FPGAMGR_INTR_MSK_F2S_USERMOD register field value. */
3808 #define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_SET_MSK 0x00000004
3809 /* The mask used to clear the ALT_FPGAMGR_INTR_MSK_F2S_USERMOD register field value. */
3810 #define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_CLR_MSK 0xfffffffb
3811 /* The reset value of the ALT_FPGAMGR_INTR_MSK_F2S_USERMOD register field. */
3812 #define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_RESET 0x1
3813 /* Extracts the ALT_FPGAMGR_INTR_MSK_F2S_USERMOD field value from a register. */
3814 #define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_GET(value) (((value) & 0x00000004) >> 2)
3815 /* Produces a ALT_FPGAMGR_INTR_MSK_F2S_USERMOD register field value suitable for setting the register. */
3816 #define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_SET(value) (((value) << 2) & 0x00000004)
3817 
3818 /*
3819  * Field : f2s_initdone_oe
3820  *
3821  * Field Access Macros:
3822  *
3823  */
3824 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE register field. */
3825 #define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_LSB 3
3826 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE register field. */
3827 #define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_MSB 3
3828 /* The width in bits of the ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE register field. */
3829 #define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_WIDTH 1
3830 /* The mask used to set the ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE register field value. */
3831 #define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_SET_MSK 0x00000008
3832 /* The mask used to clear the ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE register field value. */
3833 #define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_CLR_MSK 0xfffffff7
3834 /* The reset value of the ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE register field. */
3835 #define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_RESET 0x1
3836 /* Extracts the ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE field value from a register. */
3837 #define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_GET(value) (((value) & 0x00000008) >> 3)
3838 /* Produces a ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE register field value suitable for setting the register. */
3839 #define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_SET(value) (((value) << 3) & 0x00000008)
3840 
3841 /*
3842  * Field : f2s_nstatus_pin
3843  *
3844  * Field Access Macros:
3845  *
3846  */
3847 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN register field. */
3848 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_LSB 4
3849 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN register field. */
3850 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_MSB 4
3851 /* The width in bits of the ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN register field. */
3852 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_WIDTH 1
3853 /* The mask used to set the ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN register field value. */
3854 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_SET_MSK 0x00000010
3855 /* The mask used to clear the ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN register field value. */
3856 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_CLR_MSK 0xffffffef
3857 /* The reset value of the ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN register field. */
3858 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_RESET 0x1
3859 /* Extracts the ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN field value from a register. */
3860 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_GET(value) (((value) & 0x00000010) >> 4)
3861 /* Produces a ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN register field value suitable for setting the register. */
3862 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_SET(value) (((value) << 4) & 0x00000010)
3863 
3864 /*
3865  * Field : f2s_nstatus_oe
3866  *
3867  * Field Access Macros:
3868  *
3869  */
3870 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE register field. */
3871 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_LSB 5
3872 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE register field. */
3873 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_MSB 5
3874 /* The width in bits of the ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE register field. */
3875 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_WIDTH 1
3876 /* The mask used to set the ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE register field value. */
3877 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_SET_MSK 0x00000020
3878 /* The mask used to clear the ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE register field value. */
3879 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_CLR_MSK 0xffffffdf
3880 /* The reset value of the ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE register field. */
3881 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_RESET 0x1
3882 /* Extracts the ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE field value from a register. */
3883 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_GET(value) (((value) & 0x00000020) >> 5)
3884 /* Produces a ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE register field value suitable for setting the register. */
3885 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_SET(value) (((value) << 5) & 0x00000020)
3886 
3887 /*
3888  * Field : f2s_condone_pin
3889  *
3890  * Field Access Macros:
3891  *
3892  */
3893 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN register field. */
3894 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_LSB 6
3895 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN register field. */
3896 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_MSB 6
3897 /* The width in bits of the ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN register field. */
3898 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_WIDTH 1
3899 /* The mask used to set the ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN register field value. */
3900 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_SET_MSK 0x00000040
3901 /* The mask used to clear the ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN register field value. */
3902 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_CLR_MSK 0xffffffbf
3903 /* The reset value of the ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN register field. */
3904 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_RESET 0x1
3905 /* Extracts the ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN field value from a register. */
3906 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_GET(value) (((value) & 0x00000040) >> 6)
3907 /* Produces a ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN register field value suitable for setting the register. */
3908 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_SET(value) (((value) << 6) & 0x00000040)
3909 
3910 /*
3911  * Field : f2s_condone_oe
3912  *
3913  * Field Access Macros:
3914  *
3915  */
3916 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE register field. */
3917 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_LSB 7
3918 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE register field. */
3919 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_MSB 7
3920 /* The width in bits of the ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE register field. */
3921 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_WIDTH 1
3922 /* The mask used to set the ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE register field value. */
3923 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_SET_MSK 0x00000080
3924 /* The mask used to clear the ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE register field value. */
3925 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_CLR_MSK 0xffffff7f
3926 /* The reset value of the ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE register field. */
3927 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_RESET 0x1
3928 /* Extracts the ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE field value from a register. */
3929 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_GET(value) (((value) & 0x00000080) >> 7)
3930 /* Produces a ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE register field value suitable for setting the register. */
3931 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_SET(value) (((value) << 7) & 0x00000080)
3932 
3933 /*
3934  * Field : f2s_cvp_conf_done
3935  *
3936  * Field Access Macros:
3937  *
3938  */
3939 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE register field. */
3940 #define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_LSB 8
3941 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE register field. */
3942 #define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_MSB 8
3943 /* The width in bits of the ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE register field. */
3944 #define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_WIDTH 1
3945 /* The mask used to set the ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE register field value. */
3946 #define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_SET_MSK 0x00000100
3947 /* The mask used to clear the ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE register field value. */
3948 #define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_CLR_MSK 0xfffffeff
3949 /* The reset value of the ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE register field. */
3950 #define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_RESET 0x1
3951 /* Extracts the ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE field value from a register. */
3952 #define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_GET(value) (((value) & 0x00000100) >> 8)
3953 /* Produces a ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE register field value suitable for setting the register. */
3954 #define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_SET(value) (((value) << 8) & 0x00000100)
3955 
3956 /*
3957  * Field : f2s_pr_ready
3958  *
3959  * Field Access Macros:
3960  *
3961  */
3962 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY register field. */
3963 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_LSB 9
3964 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY register field. */
3965 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_MSB 9
3966 /* The width in bits of the ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY register field. */
3967 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_WIDTH 1
3968 /* The mask used to set the ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY register field value. */
3969 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_SET_MSK 0x00000200
3970 /* The mask used to clear the ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY register field value. */
3971 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_CLR_MSK 0xfffffdff
3972 /* The reset value of the ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY register field. */
3973 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_RESET 0x1
3974 /* Extracts the ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY field value from a register. */
3975 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_GET(value) (((value) & 0x00000200) >> 9)
3976 /* Produces a ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY register field value suitable for setting the register. */
3977 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_SET(value) (((value) << 9) & 0x00000200)
3978 
3979 /*
3980  * Field : f2s_pr_done
3981  *
3982  * Field Access Macros:
3983  *
3984  */
3985 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE register field. */
3986 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_LSB 10
3987 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE register field. */
3988 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_MSB 10
3989 /* The width in bits of the ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE register field. */
3990 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_WIDTH 1
3991 /* The mask used to set the ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE register field value. */
3992 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_SET_MSK 0x00000400
3993 /* The mask used to clear the ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE register field value. */
3994 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_CLR_MSK 0xfffffbff
3995 /* The reset value of the ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE register field. */
3996 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_RESET 0x1
3997 /* Extracts the ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE field value from a register. */
3998 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_GET(value) (((value) & 0x00000400) >> 10)
3999 /* Produces a ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE register field value suitable for setting the register. */
4000 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_SET(value) (((value) << 10) & 0x00000400)
4001 
4002 /*
4003  * Field : f2s_pr_error
4004  *
4005  * Field Access Macros:
4006  *
4007  */
4008 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR register field. */
4009 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_LSB 11
4010 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR register field. */
4011 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_MSB 11
4012 /* The width in bits of the ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR register field. */
4013 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_WIDTH 1
4014 /* The mask used to set the ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR register field value. */
4015 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_SET_MSK 0x00000800
4016 /* The mask used to clear the ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR register field value. */
4017 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_CLR_MSK 0xfffff7ff
4018 /* The reset value of the ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR register field. */
4019 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_RESET 0x1
4020 /* Extracts the ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR field value from a register. */
4021 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_GET(value) (((value) & 0x00000800) >> 11)
4022 /* Produces a ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR register field value suitable for setting the register. */
4023 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_SET(value) (((value) << 11) & 0x00000800)
4024 
4025 /*
4026  * Field : f2s_nconfig_pin
4027  *
4028  * Field Access Macros:
4029  *
4030  */
4031 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN register field. */
4032 #define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_LSB 12
4033 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN register field. */
4034 #define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_MSB 12
4035 /* The width in bits of the ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN register field. */
4036 #define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_WIDTH 1
4037 /* The mask used to set the ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN register field value. */
4038 #define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_SET_MSK 0x00001000
4039 /* The mask used to clear the ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN register field value. */
4040 #define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_CLR_MSK 0xffffefff
4041 /* The reset value of the ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN register field. */
4042 #define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_RESET 0x1
4043 /* Extracts the ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN field value from a register. */
4044 #define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_GET(value) (((value) & 0x00001000) >> 12)
4045 /* Produces a ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN register field value suitable for setting the register. */
4046 #define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_SET(value) (((value) << 12) & 0x00001000)
4047 
4048 /*
4049  * Field : f2s_nceo_oe
4050  *
4051  * Field Access Macros:
4052  *
4053  */
4054 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE register field. */
4055 #define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_LSB 13
4056 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE register field. */
4057 #define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_MSB 13
4058 /* The width in bits of the ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE register field. */
4059 #define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_WIDTH 1
4060 /* The mask used to set the ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE register field value. */
4061 #define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_SET_MSK 0x00002000
4062 /* The mask used to clear the ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE register field value. */
4063 #define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_CLR_MSK 0xffffdfff
4064 /* The reset value of the ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE register field. */
4065 #define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_RESET 0x1
4066 /* Extracts the ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE field value from a register. */
4067 #define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_GET(value) (((value) & 0x00002000) >> 13)
4068 /* Produces a ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE register field value suitable for setting the register. */
4069 #define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_SET(value) (((value) << 13) & 0x00002000)
4070 
4071 /*
4072  * Field : f2s_msel0
4073  *
4074  * Field Access Macros:
4075  *
4076  */
4077 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_MSEL0 register field. */
4078 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_LSB 16
4079 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_MSEL0 register field. */
4080 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_MSB 16
4081 /* The width in bits of the ALT_FPGAMGR_INTR_MSK_F2S_MSEL0 register field. */
4082 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_WIDTH 1
4083 /* The mask used to set the ALT_FPGAMGR_INTR_MSK_F2S_MSEL0 register field value. */
4084 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_SET_MSK 0x00010000
4085 /* The mask used to clear the ALT_FPGAMGR_INTR_MSK_F2S_MSEL0 register field value. */
4086 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_CLR_MSK 0xfffeffff
4087 /* The reset value of the ALT_FPGAMGR_INTR_MSK_F2S_MSEL0 register field. */
4088 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_RESET 0x1
4089 /* Extracts the ALT_FPGAMGR_INTR_MSK_F2S_MSEL0 field value from a register. */
4090 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_GET(value) (((value) & 0x00010000) >> 16)
4091 /* Produces a ALT_FPGAMGR_INTR_MSK_F2S_MSEL0 register field value suitable for setting the register. */
4092 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_SET(value) (((value) << 16) & 0x00010000)
4093 
4094 /*
4095  * Field : f2s_msel1
4096  *
4097  * Field Access Macros:
4098  *
4099  */
4100 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_MSEL1 register field. */
4101 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_LSB 17
4102 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_MSEL1 register field. */
4103 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_MSB 17
4104 /* The width in bits of the ALT_FPGAMGR_INTR_MSK_F2S_MSEL1 register field. */
4105 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_WIDTH 1
4106 /* The mask used to set the ALT_FPGAMGR_INTR_MSK_F2S_MSEL1 register field value. */
4107 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_SET_MSK 0x00020000
4108 /* The mask used to clear the ALT_FPGAMGR_INTR_MSK_F2S_MSEL1 register field value. */
4109 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_CLR_MSK 0xfffdffff
4110 /* The reset value of the ALT_FPGAMGR_INTR_MSK_F2S_MSEL1 register field. */
4111 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_RESET 0x1
4112 /* Extracts the ALT_FPGAMGR_INTR_MSK_F2S_MSEL1 field value from a register. */
4113 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_GET(value) (((value) & 0x00020000) >> 17)
4114 /* Produces a ALT_FPGAMGR_INTR_MSK_F2S_MSEL1 register field value suitable for setting the register. */
4115 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_SET(value) (((value) << 17) & 0x00020000)
4116 
4117 /*
4118  * Field : f2s_msel2
4119  *
4120  * Field Access Macros:
4121  *
4122  */
4123 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_MSEL2 register field. */
4124 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_LSB 18
4125 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSK_F2S_MSEL2 register field. */
4126 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_MSB 18
4127 /* The width in bits of the ALT_FPGAMGR_INTR_MSK_F2S_MSEL2 register field. */
4128 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_WIDTH 1
4129 /* The mask used to set the ALT_FPGAMGR_INTR_MSK_F2S_MSEL2 register field value. */
4130 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_SET_MSK 0x00040000
4131 /* The mask used to clear the ALT_FPGAMGR_INTR_MSK_F2S_MSEL2 register field value. */
4132 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_CLR_MSK 0xfffbffff
4133 /* The reset value of the ALT_FPGAMGR_INTR_MSK_F2S_MSEL2 register field. */
4134 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_RESET 0x1
4135 /* Extracts the ALT_FPGAMGR_INTR_MSK_F2S_MSEL2 field value from a register. */
4136 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_GET(value) (((value) & 0x00040000) >> 18)
4137 /* Produces a ALT_FPGAMGR_INTR_MSK_F2S_MSEL2 register field value suitable for setting the register. */
4138 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_SET(value) (((value) << 18) & 0x00040000)
4139 
4140 /*
4141  * Field : imgcfg_FifoEmpty
4142  *
4143  * FIfoEmpty Status of FPGA image configuration FIFO
4144  *
4145  * Field Access Macros:
4146  *
4147  */
4148 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY register field. */
4149 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_LSB 24
4150 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY register field. */
4151 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_MSB 24
4152 /* The width in bits of the ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY register field. */
4153 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_WIDTH 1
4154 /* The mask used to set the ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY register field value. */
4155 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_SET_MSK 0x01000000
4156 /* The mask used to clear the ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY register field value. */
4157 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_CLR_MSK 0xfeffffff
4158 /* The reset value of the ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY register field. */
4159 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_RESET 0x1
4160 /* Extracts the ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY field value from a register. */
4161 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_GET(value) (((value) & 0x01000000) >> 24)
4162 /* Produces a ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY register field value suitable for setting the register. */
4163 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_SET(value) (((value) << 24) & 0x01000000)
4164 
4165 /*
4166  * Field : imgcfg_FifoFull
4167  *
4168  * FIfoFull Status of FPGA image configuration FIFO
4169  *
4170  * Field Access Macros:
4171  *
4172  */
4173 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL register field. */
4174 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_LSB 25
4175 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL register field. */
4176 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_MSB 25
4177 /* The width in bits of the ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL register field. */
4178 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_WIDTH 1
4179 /* The mask used to set the ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL register field value. */
4180 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_SET_MSK 0x02000000
4181 /* The mask used to clear the ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL register field value. */
4182 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_CLR_MSK 0xfdffffff
4183 /* The reset value of the ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL register field. */
4184 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_RESET 0x1
4185 /* Extracts the ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL field value from a register. */
4186 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_GET(value) (((value) & 0x02000000) >> 25)
4187 /* Produces a ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL register field value suitable for setting the register. */
4188 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_SET(value) (((value) << 25) & 0x02000000)
4189 
4190 /*
4191  * Field : jtagm
4192  *
4193  * JTAG Master Session Status
4194  *
4195  * Field Access Macros:
4196  *
4197  */
4198 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSK_JTAGM register field. */
4199 #define ALT_FPGAMGR_INTR_MSK_JTAGM_LSB 28
4200 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSK_JTAGM register field. */
4201 #define ALT_FPGAMGR_INTR_MSK_JTAGM_MSB 28
4202 /* The width in bits of the ALT_FPGAMGR_INTR_MSK_JTAGM register field. */
4203 #define ALT_FPGAMGR_INTR_MSK_JTAGM_WIDTH 1
4204 /* The mask used to set the ALT_FPGAMGR_INTR_MSK_JTAGM register field value. */
4205 #define ALT_FPGAMGR_INTR_MSK_JTAGM_SET_MSK 0x10000000
4206 /* The mask used to clear the ALT_FPGAMGR_INTR_MSK_JTAGM register field value. */
4207 #define ALT_FPGAMGR_INTR_MSK_JTAGM_CLR_MSK 0xefffffff
4208 /* The reset value of the ALT_FPGAMGR_INTR_MSK_JTAGM register field. */
4209 #define ALT_FPGAMGR_INTR_MSK_JTAGM_RESET 0x1
4210 /* Extracts the ALT_FPGAMGR_INTR_MSK_JTAGM field value from a register. */
4211 #define ALT_FPGAMGR_INTR_MSK_JTAGM_GET(value) (((value) & 0x10000000) >> 28)
4212 /* Produces a ALT_FPGAMGR_INTR_MSK_JTAGM register field value suitable for setting the register. */
4213 #define ALT_FPGAMGR_INTR_MSK_JTAGM_SET(value) (((value) << 28) & 0x10000000)
4214 
4215 /*
4216  * Field : emr
4217  *
4218  * EMR valid bit
4219  *
4220  * Field Access Macros:
4221  *
4222  */
4223 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_MSK_EMR register field. */
4224 #define ALT_FPGAMGR_INTR_MSK_EMR_LSB 29
4225 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_MSK_EMR register field. */
4226 #define ALT_FPGAMGR_INTR_MSK_EMR_MSB 29
4227 /* The width in bits of the ALT_FPGAMGR_INTR_MSK_EMR register field. */
4228 #define ALT_FPGAMGR_INTR_MSK_EMR_WIDTH 1
4229 /* The mask used to set the ALT_FPGAMGR_INTR_MSK_EMR register field value. */
4230 #define ALT_FPGAMGR_INTR_MSK_EMR_SET_MSK 0x20000000
4231 /* The mask used to clear the ALT_FPGAMGR_INTR_MSK_EMR register field value. */
4232 #define ALT_FPGAMGR_INTR_MSK_EMR_CLR_MSK 0xdfffffff
4233 /* The reset value of the ALT_FPGAMGR_INTR_MSK_EMR register field. */
4234 #define ALT_FPGAMGR_INTR_MSK_EMR_RESET 0x1
4235 /* Extracts the ALT_FPGAMGR_INTR_MSK_EMR field value from a register. */
4236 #define ALT_FPGAMGR_INTR_MSK_EMR_GET(value) (((value) & 0x20000000) >> 29)
4237 /* Produces a ALT_FPGAMGR_INTR_MSK_EMR register field value suitable for setting the register. */
4238 #define ALT_FPGAMGR_INTR_MSK_EMR_SET(value) (((value) << 29) & 0x20000000)
4239 
4240 #ifndef __ASSEMBLY__
4241 /*
4242  * WARNING: The C register and register group struct declarations are provided for
4243  * convenience and illustrative purposes. They should, however, be used with
4244  * caution as the C language standard provides no guarantees about the alignment or
4245  * atomicity of device memory accesses. The recommended practice for writing
4246  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4247  * alt_write_word() functions.
4248  *
4249  * The struct declaration for register ALT_FPGAMGR_INTR_MSK.
4250  */
4251 struct ALT_FPGAMGR_INTR_MSK_s
4252 {
4253  uint32_t f2s_crc_error : 1; /* ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR */
4254  uint32_t f2s_early_usermode : 1; /* ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD */
4255  uint32_t f2s_usermode : 1; /* ALT_FPGAMGR_INTR_MSK_F2S_USERMOD */
4256  uint32_t f2s_initdone_oe : 1; /* ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE */
4257  uint32_t f2s_nstatus_pin : 1; /* ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN */
4258  uint32_t f2s_nstatus_oe : 1; /* ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE */
4259  uint32_t f2s_condone_pin : 1; /* ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN */
4260  uint32_t f2s_condone_oe : 1; /* ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE */
4261  uint32_t f2s_cvp_conf_done : 1; /* ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE */
4262  uint32_t f2s_pr_ready : 1; /* ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY */
4263  uint32_t f2s_pr_done : 1; /* ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE */
4264  uint32_t f2s_pr_error : 1; /* ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR */
4265  uint32_t f2s_nconfig_pin : 1; /* ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN */
4266  uint32_t f2s_nceo_oe : 1; /* ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE */
4267  uint32_t : 2; /* *UNDEFINED* */
4268  uint32_t f2s_msel0 : 1; /* ALT_FPGAMGR_INTR_MSK_F2S_MSEL0 */
4269  uint32_t f2s_msel1 : 1; /* ALT_FPGAMGR_INTR_MSK_F2S_MSEL1 */
4270  uint32_t f2s_msel2 : 1; /* ALT_FPGAMGR_INTR_MSK_F2S_MSEL2 */
4271  uint32_t : 5; /* *UNDEFINED* */
4272  uint32_t imgcfg_FifoEmpty : 1; /* ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY */
4273  uint32_t imgcfg_FifoFull : 1; /* ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL */
4274  uint32_t : 2; /* *UNDEFINED* */
4275  uint32_t jtagm : 1; /* ALT_FPGAMGR_INTR_MSK_JTAGM */
4276  uint32_t emr : 1; /* ALT_FPGAMGR_INTR_MSK_EMR */
4277  uint32_t : 2; /* *UNDEFINED* */
4278 };
4279 
4280 /* The typedef declaration for register ALT_FPGAMGR_INTR_MSK. */
4281 typedef volatile struct ALT_FPGAMGR_INTR_MSK_s ALT_FPGAMGR_INTR_MSK_t;
4282 #endif /* __ASSEMBLY__ */
4283 
4284 /* The reset value of the ALT_FPGAMGR_INTR_MSK register. */
4285 #define ALT_FPGAMGR_INTR_MSK_RESET 0x33073fff
4286 /* The byte offset of the ALT_FPGAMGR_INTR_MSK register from the beginning of the component. */
4287 #define ALT_FPGAMGR_INTR_MSK_OFST 0x88
4288 
4289 /*
4290  * Register : intr_polarity
4291  *
4292  * Active Level of the signal to generate interrupt.
4293  *
4294  * 0 :Active LOW. An interrupt will be generated when that particular bit/signal is
4295  * LOW
4296  *
4297  * 1: Active HIGH. An interrupt will be generated when that particular bit/signal
4298  * is HIGH
4299  *
4300  * Register Layout
4301  *
4302  * Bits | Access | Reset | Description
4303  * :--------|:-------|:------|:---------------------------------------
4304  * [0] | RW | 0x1 | ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR
4305  * [1] | RW | 0x1 | ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD
4306  * [2] | RW | 0x1 | ALT_FPGAMGR_INTR_POL_F2S_USERMOD
4307  * [3] | RW | 0x1 | ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE
4308  * [4] | RW | 0x1 | ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN
4309  * [5] | RW | 0x1 | ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE
4310  * [6] | RW | 0x1 | ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN
4311  * [7] | RW | 0x1 | ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE
4312  * [8] | RW | 0x1 | ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE
4313  * [9] | RW | 0x1 | ALT_FPGAMGR_INTR_POL_F2S_PR_RDY
4314  * [10] | RW | 0x1 | ALT_FPGAMGR_INTR_POL_F2S_PR_DONE
4315  * [11] | RW | 0x1 | ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR
4316  * [12] | RW | 0x1 | ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN
4317  * [13] | RW | 0x1 | ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE
4318  * [15:14] | ??? | 0x0 | *UNDEFINED*
4319  * [16] | RW | 0x1 | ALT_FPGAMGR_INTR_POL_F2S_MSEL0
4320  * [17] | RW | 0x1 | ALT_FPGAMGR_INTR_POL_F2S_MSEL1
4321  * [18] | RW | 0x1 | ALT_FPGAMGR_INTR_POL_F2S_MSEL2
4322  * [23:19] | ??? | 0x0 | *UNDEFINED*
4323  * [24] | RW | 0x1 | ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY
4324  * [25] | RW | 0x1 | ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL
4325  * [27:26] | ??? | 0x0 | *UNDEFINED*
4326  * [28] | RW | 0x1 | ALT_FPGAMGR_INTR_POL_JTAGM
4327  * [29] | RW | 0x1 | ALT_FPGAMGR_INTR_POL_EMR
4328  * [31:30] | ??? | 0x0 | *UNDEFINED*
4329  *
4330  */
4331 /*
4332  * Field : f2s_crc_error
4333  *
4334  * Field Access Macros:
4335  *
4336  */
4337 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR register field. */
4338 #define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_LSB 0
4339 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR register field. */
4340 #define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_MSB 0
4341 /* The width in bits of the ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR register field. */
4342 #define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_WIDTH 1
4343 /* The mask used to set the ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR register field value. */
4344 #define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_SET_MSK 0x00000001
4345 /* The mask used to clear the ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR register field value. */
4346 #define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_CLR_MSK 0xfffffffe
4347 /* The reset value of the ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR register field. */
4348 #define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_RESET 0x1
4349 /* Extracts the ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR field value from a register. */
4350 #define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_GET(value) (((value) & 0x00000001) >> 0)
4351 /* Produces a ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR register field value suitable for setting the register. */
4352 #define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_SET(value) (((value) << 0) & 0x00000001)
4353 
4354 /*
4355  * Field : f2s_early_usermode
4356  *
4357  * Field Access Macros:
4358  *
4359  */
4360 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD register field. */
4361 #define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_LSB 1
4362 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD register field. */
4363 #define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_MSB 1
4364 /* The width in bits of the ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD register field. */
4365 #define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_WIDTH 1
4366 /* The mask used to set the ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD register field value. */
4367 #define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_SET_MSK 0x00000002
4368 /* The mask used to clear the ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD register field value. */
4369 #define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_CLR_MSK 0xfffffffd
4370 /* The reset value of the ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD register field. */
4371 #define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_RESET 0x1
4372 /* Extracts the ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD field value from a register. */
4373 #define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_GET(value) (((value) & 0x00000002) >> 1)
4374 /* Produces a ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD register field value suitable for setting the register. */
4375 #define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_SET(value) (((value) << 1) & 0x00000002)
4376 
4377 /*
4378  * Field : f2s_usermode
4379  *
4380  * Field Access Macros:
4381  *
4382  */
4383 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_POL_F2S_USERMOD register field. */
4384 #define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_LSB 2
4385 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_POL_F2S_USERMOD register field. */
4386 #define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_MSB 2
4387 /* The width in bits of the ALT_FPGAMGR_INTR_POL_F2S_USERMOD register field. */
4388 #define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_WIDTH 1
4389 /* The mask used to set the ALT_FPGAMGR_INTR_POL_F2S_USERMOD register field value. */
4390 #define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_SET_MSK 0x00000004
4391 /* The mask used to clear the ALT_FPGAMGR_INTR_POL_F2S_USERMOD register field value. */
4392 #define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_CLR_MSK 0xfffffffb
4393 /* The reset value of the ALT_FPGAMGR_INTR_POL_F2S_USERMOD register field. */
4394 #define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_RESET 0x1
4395 /* Extracts the ALT_FPGAMGR_INTR_POL_F2S_USERMOD field value from a register. */
4396 #define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_GET(value) (((value) & 0x00000004) >> 2)
4397 /* Produces a ALT_FPGAMGR_INTR_POL_F2S_USERMOD register field value suitable for setting the register. */
4398 #define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_SET(value) (((value) << 2) & 0x00000004)
4399 
4400 /*
4401  * Field : f2s_initdone_oe
4402  *
4403  * Field Access Macros:
4404  *
4405  */
4406 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE register field. */
4407 #define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_LSB 3
4408 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE register field. */
4409 #define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_MSB 3
4410 /* The width in bits of the ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE register field. */
4411 #define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_WIDTH 1
4412 /* The mask used to set the ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE register field value. */
4413 #define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_SET_MSK 0x00000008
4414 /* The mask used to clear the ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE register field value. */
4415 #define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_CLR_MSK 0xfffffff7
4416 /* The reset value of the ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE register field. */
4417 #define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_RESET 0x1
4418 /* Extracts the ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE field value from a register. */
4419 #define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_GET(value) (((value) & 0x00000008) >> 3)
4420 /* Produces a ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE register field value suitable for setting the register. */
4421 #define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_SET(value) (((value) << 3) & 0x00000008)
4422 
4423 /*
4424  * Field : f2s_nstatus_pin
4425  *
4426  * Field Access Macros:
4427  *
4428  */
4429 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN register field. */
4430 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_LSB 4
4431 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN register field. */
4432 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_MSB 4
4433 /* The width in bits of the ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN register field. */
4434 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_WIDTH 1
4435 /* The mask used to set the ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN register field value. */
4436 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_SET_MSK 0x00000010
4437 /* The mask used to clear the ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN register field value. */
4438 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_CLR_MSK 0xffffffef
4439 /* The reset value of the ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN register field. */
4440 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_RESET 0x1
4441 /* Extracts the ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN field value from a register. */
4442 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_GET(value) (((value) & 0x00000010) >> 4)
4443 /* Produces a ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN register field value suitable for setting the register. */
4444 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_SET(value) (((value) << 4) & 0x00000010)
4445 
4446 /*
4447  * Field : f2s_nstatus_oe
4448  *
4449  * Field Access Macros:
4450  *
4451  */
4452 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE register field. */
4453 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_LSB 5
4454 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE register field. */
4455 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_MSB 5
4456 /* The width in bits of the ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE register field. */
4457 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_WIDTH 1
4458 /* The mask used to set the ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE register field value. */
4459 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_SET_MSK 0x00000020
4460 /* The mask used to clear the ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE register field value. */
4461 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_CLR_MSK 0xffffffdf
4462 /* The reset value of the ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE register field. */
4463 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_RESET 0x1
4464 /* Extracts the ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE field value from a register. */
4465 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_GET(value) (((value) & 0x00000020) >> 5)
4466 /* Produces a ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE register field value suitable for setting the register. */
4467 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_SET(value) (((value) << 5) & 0x00000020)
4468 
4469 /*
4470  * Field : f2s_condone_pin
4471  *
4472  * Field Access Macros:
4473  *
4474  */
4475 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN register field. */
4476 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_LSB 6
4477 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN register field. */
4478 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_MSB 6
4479 /* The width in bits of the ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN register field. */
4480 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_WIDTH 1
4481 /* The mask used to set the ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN register field value. */
4482 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_SET_MSK 0x00000040
4483 /* The mask used to clear the ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN register field value. */
4484 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_CLR_MSK 0xffffffbf
4485 /* The reset value of the ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN register field. */
4486 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_RESET 0x1
4487 /* Extracts the ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN field value from a register. */
4488 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_GET(value) (((value) & 0x00000040) >> 6)
4489 /* Produces a ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN register field value suitable for setting the register. */
4490 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_SET(value) (((value) << 6) & 0x00000040)
4491 
4492 /*
4493  * Field : f2s_condone_oe
4494  *
4495  * Field Access Macros:
4496  *
4497  */
4498 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE register field. */
4499 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_LSB 7
4500 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE register field. */
4501 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_MSB 7
4502 /* The width in bits of the ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE register field. */
4503 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_WIDTH 1
4504 /* The mask used to set the ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE register field value. */
4505 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_SET_MSK 0x00000080
4506 /* The mask used to clear the ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE register field value. */
4507 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_CLR_MSK 0xffffff7f
4508 /* The reset value of the ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE register field. */
4509 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_RESET 0x1
4510 /* Extracts the ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE field value from a register. */
4511 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_GET(value) (((value) & 0x00000080) >> 7)
4512 /* Produces a ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE register field value suitable for setting the register. */
4513 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_SET(value) (((value) << 7) & 0x00000080)
4514 
4515 /*
4516  * Field : f2s_cvp_conf_done
4517  *
4518  * Field Access Macros:
4519  *
4520  */
4521 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE register field. */
4522 #define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_LSB 8
4523 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE register field. */
4524 #define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_MSB 8
4525 /* The width in bits of the ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE register field. */
4526 #define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_WIDTH 1
4527 /* The mask used to set the ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE register field value. */
4528 #define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_SET_MSK 0x00000100
4529 /* The mask used to clear the ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE register field value. */
4530 #define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_CLR_MSK 0xfffffeff
4531 /* The reset value of the ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE register field. */
4532 #define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_RESET 0x1
4533 /* Extracts the ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE field value from a register. */
4534 #define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_GET(value) (((value) & 0x00000100) >> 8)
4535 /* Produces a ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE register field value suitable for setting the register. */
4536 #define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_SET(value) (((value) << 8) & 0x00000100)
4537 
4538 /*
4539  * Field : f2s_pr_ready
4540  *
4541  * Field Access Macros:
4542  *
4543  */
4544 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_POL_F2S_PR_RDY register field. */
4545 #define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_LSB 9
4546 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_POL_F2S_PR_RDY register field. */
4547 #define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_MSB 9
4548 /* The width in bits of the ALT_FPGAMGR_INTR_POL_F2S_PR_RDY register field. */
4549 #define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_WIDTH 1
4550 /* The mask used to set the ALT_FPGAMGR_INTR_POL_F2S_PR_RDY register field value. */
4551 #define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_SET_MSK 0x00000200
4552 /* The mask used to clear the ALT_FPGAMGR_INTR_POL_F2S_PR_RDY register field value. */
4553 #define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_CLR_MSK 0xfffffdff
4554 /* The reset value of the ALT_FPGAMGR_INTR_POL_F2S_PR_RDY register field. */
4555 #define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_RESET 0x1
4556 /* Extracts the ALT_FPGAMGR_INTR_POL_F2S_PR_RDY field value from a register. */
4557 #define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_GET(value) (((value) & 0x00000200) >> 9)
4558 /* Produces a ALT_FPGAMGR_INTR_POL_F2S_PR_RDY register field value suitable for setting the register. */
4559 #define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_SET(value) (((value) << 9) & 0x00000200)
4560 
4561 /*
4562  * Field : f2s_pr_done
4563  *
4564  * Field Access Macros:
4565  *
4566  */
4567 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_POL_F2S_PR_DONE register field. */
4568 #define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_LSB 10
4569 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_POL_F2S_PR_DONE register field. */
4570 #define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_MSB 10
4571 /* The width in bits of the ALT_FPGAMGR_INTR_POL_F2S_PR_DONE register field. */
4572 #define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_WIDTH 1
4573 /* The mask used to set the ALT_FPGAMGR_INTR_POL_F2S_PR_DONE register field value. */
4574 #define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_SET_MSK 0x00000400
4575 /* The mask used to clear the ALT_FPGAMGR_INTR_POL_F2S_PR_DONE register field value. */
4576 #define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_CLR_MSK 0xfffffbff
4577 /* The reset value of the ALT_FPGAMGR_INTR_POL_F2S_PR_DONE register field. */
4578 #define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_RESET 0x1
4579 /* Extracts the ALT_FPGAMGR_INTR_POL_F2S_PR_DONE field value from a register. */
4580 #define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_GET(value) (((value) & 0x00000400) >> 10)
4581 /* Produces a ALT_FPGAMGR_INTR_POL_F2S_PR_DONE register field value suitable for setting the register. */
4582 #define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_SET(value) (((value) << 10) & 0x00000400)
4583 
4584 /*
4585  * Field : f2s_pr_error
4586  *
4587  * Field Access Macros:
4588  *
4589  */
4590 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR register field. */
4591 #define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_LSB 11
4592 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR register field. */
4593 #define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_MSB 11
4594 /* The width in bits of the ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR register field. */
4595 #define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_WIDTH 1
4596 /* The mask used to set the ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR register field value. */
4597 #define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_SET_MSK 0x00000800
4598 /* The mask used to clear the ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR register field value. */
4599 #define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_CLR_MSK 0xfffff7ff
4600 /* The reset value of the ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR register field. */
4601 #define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_RESET 0x1
4602 /* Extracts the ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR field value from a register. */
4603 #define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_GET(value) (((value) & 0x00000800) >> 11)
4604 /* Produces a ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR register field value suitable for setting the register. */
4605 #define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_SET(value) (((value) << 11) & 0x00000800)
4606 
4607 /*
4608  * Field : f2s_nconfig_pin
4609  *
4610  * Field Access Macros:
4611  *
4612  */
4613 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN register field. */
4614 #define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_LSB 12
4615 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN register field. */
4616 #define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_MSB 12
4617 /* The width in bits of the ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN register field. */
4618 #define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_WIDTH 1
4619 /* The mask used to set the ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN register field value. */
4620 #define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_SET_MSK 0x00001000
4621 /* The mask used to clear the ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN register field value. */
4622 #define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_CLR_MSK 0xffffefff
4623 /* The reset value of the ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN register field. */
4624 #define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_RESET 0x1
4625 /* Extracts the ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN field value from a register. */
4626 #define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_GET(value) (((value) & 0x00001000) >> 12)
4627 /* Produces a ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN register field value suitable for setting the register. */
4628 #define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_SET(value) (((value) << 12) & 0x00001000)
4629 
4630 /*
4631  * Field : f2s_nceo_oe
4632  *
4633  * Field Access Macros:
4634  *
4635  */
4636 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE register field. */
4637 #define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_LSB 13
4638 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE register field. */
4639 #define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_MSB 13
4640 /* The width in bits of the ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE register field. */
4641 #define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_WIDTH 1
4642 /* The mask used to set the ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE register field value. */
4643 #define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_SET_MSK 0x00002000
4644 /* The mask used to clear the ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE register field value. */
4645 #define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_CLR_MSK 0xffffdfff
4646 /* The reset value of the ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE register field. */
4647 #define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_RESET 0x1
4648 /* Extracts the ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE field value from a register. */
4649 #define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_GET(value) (((value) & 0x00002000) >> 13)
4650 /* Produces a ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE register field value suitable for setting the register. */
4651 #define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_SET(value) (((value) << 13) & 0x00002000)
4652 
4653 /*
4654  * Field : f2s_msel0
4655  *
4656  * Field Access Macros:
4657  *
4658  */
4659 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_POL_F2S_MSEL0 register field. */
4660 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_LSB 16
4661 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_POL_F2S_MSEL0 register field. */
4662 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_MSB 16
4663 /* The width in bits of the ALT_FPGAMGR_INTR_POL_F2S_MSEL0 register field. */
4664 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_WIDTH 1
4665 /* The mask used to set the ALT_FPGAMGR_INTR_POL_F2S_MSEL0 register field value. */
4666 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_SET_MSK 0x00010000
4667 /* The mask used to clear the ALT_FPGAMGR_INTR_POL_F2S_MSEL0 register field value. */
4668 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_CLR_MSK 0xfffeffff
4669 /* The reset value of the ALT_FPGAMGR_INTR_POL_F2S_MSEL0 register field. */
4670 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_RESET 0x1
4671 /* Extracts the ALT_FPGAMGR_INTR_POL_F2S_MSEL0 field value from a register. */
4672 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_GET(value) (((value) & 0x00010000) >> 16)
4673 /* Produces a ALT_FPGAMGR_INTR_POL_F2S_MSEL0 register field value suitable for setting the register. */
4674 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_SET(value) (((value) << 16) & 0x00010000)
4675 
4676 /*
4677  * Field : f2s_msel1
4678  *
4679  * Field Access Macros:
4680  *
4681  */
4682 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_POL_F2S_MSEL1 register field. */
4683 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_LSB 17
4684 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_POL_F2S_MSEL1 register field. */
4685 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_MSB 17
4686 /* The width in bits of the ALT_FPGAMGR_INTR_POL_F2S_MSEL1 register field. */
4687 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_WIDTH 1
4688 /* The mask used to set the ALT_FPGAMGR_INTR_POL_F2S_MSEL1 register field value. */
4689 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_SET_MSK 0x00020000
4690 /* The mask used to clear the ALT_FPGAMGR_INTR_POL_F2S_MSEL1 register field value. */
4691 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_CLR_MSK 0xfffdffff
4692 /* The reset value of the ALT_FPGAMGR_INTR_POL_F2S_MSEL1 register field. */
4693 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_RESET 0x1
4694 /* Extracts the ALT_FPGAMGR_INTR_POL_F2S_MSEL1 field value from a register. */
4695 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_GET(value) (((value) & 0x00020000) >> 17)
4696 /* Produces a ALT_FPGAMGR_INTR_POL_F2S_MSEL1 register field value suitable for setting the register. */
4697 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_SET(value) (((value) << 17) & 0x00020000)
4698 
4699 /*
4700  * Field : f2s_msel2
4701  *
4702  * Field Access Macros:
4703  *
4704  */
4705 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_POL_F2S_MSEL2 register field. */
4706 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_LSB 18
4707 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_POL_F2S_MSEL2 register field. */
4708 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_MSB 18
4709 /* The width in bits of the ALT_FPGAMGR_INTR_POL_F2S_MSEL2 register field. */
4710 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_WIDTH 1
4711 /* The mask used to set the ALT_FPGAMGR_INTR_POL_F2S_MSEL2 register field value. */
4712 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_SET_MSK 0x00040000
4713 /* The mask used to clear the ALT_FPGAMGR_INTR_POL_F2S_MSEL2 register field value. */
4714 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_CLR_MSK 0xfffbffff
4715 /* The reset value of the ALT_FPGAMGR_INTR_POL_F2S_MSEL2 register field. */
4716 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_RESET 0x1
4717 /* Extracts the ALT_FPGAMGR_INTR_POL_F2S_MSEL2 field value from a register. */
4718 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_GET(value) (((value) & 0x00040000) >> 18)
4719 /* Produces a ALT_FPGAMGR_INTR_POL_F2S_MSEL2 register field value suitable for setting the register. */
4720 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_SET(value) (((value) << 18) & 0x00040000)
4721 
4722 /*
4723  * Field : imgcfg_FifoEmpty
4724  *
4725  * FIfoEmpty Status of FPGA image configuration FIFO
4726  *
4727  * Field Access Macros:
4728  *
4729  */
4730 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY register field. */
4731 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_LSB 24
4732 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY register field. */
4733 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_MSB 24
4734 /* The width in bits of the ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY register field. */
4735 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_WIDTH 1
4736 /* The mask used to set the ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY register field value. */
4737 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_SET_MSK 0x01000000
4738 /* The mask used to clear the ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY register field value. */
4739 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_CLR_MSK 0xfeffffff
4740 /* The reset value of the ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY register field. */
4741 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_RESET 0x1
4742 /* Extracts the ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY field value from a register. */
4743 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_GET(value) (((value) & 0x01000000) >> 24)
4744 /* Produces a ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY register field value suitable for setting the register. */
4745 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_SET(value) (((value) << 24) & 0x01000000)
4746 
4747 /*
4748  * Field : imgcfg_FifoFull
4749  *
4750  * FIfoFull Status of FPGA image configuration FIFO
4751  *
4752  * Field Access Macros:
4753  *
4754  */
4755 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL register field. */
4756 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_LSB 25
4757 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL register field. */
4758 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_MSB 25
4759 /* The width in bits of the ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL register field. */
4760 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_WIDTH 1
4761 /* The mask used to set the ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL register field value. */
4762 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_SET_MSK 0x02000000
4763 /* The mask used to clear the ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL register field value. */
4764 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_CLR_MSK 0xfdffffff
4765 /* The reset value of the ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL register field. */
4766 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_RESET 0x1
4767 /* Extracts the ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL field value from a register. */
4768 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_GET(value) (((value) & 0x02000000) >> 25)
4769 /* Produces a ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL register field value suitable for setting the register. */
4770 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_SET(value) (((value) << 25) & 0x02000000)
4771 
4772 /*
4773  * Field : jtagm
4774  *
4775  * JTAG Master Session Status
4776  *
4777  * Field Access Macros:
4778  *
4779  */
4780 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_POL_JTAGM register field. */
4781 #define ALT_FPGAMGR_INTR_POL_JTAGM_LSB 28
4782 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_POL_JTAGM register field. */
4783 #define ALT_FPGAMGR_INTR_POL_JTAGM_MSB 28
4784 /* The width in bits of the ALT_FPGAMGR_INTR_POL_JTAGM register field. */
4785 #define ALT_FPGAMGR_INTR_POL_JTAGM_WIDTH 1
4786 /* The mask used to set the ALT_FPGAMGR_INTR_POL_JTAGM register field value. */
4787 #define ALT_FPGAMGR_INTR_POL_JTAGM_SET_MSK 0x10000000
4788 /* The mask used to clear the ALT_FPGAMGR_INTR_POL_JTAGM register field value. */
4789 #define ALT_FPGAMGR_INTR_POL_JTAGM_CLR_MSK 0xefffffff
4790 /* The reset value of the ALT_FPGAMGR_INTR_POL_JTAGM register field. */
4791 #define ALT_FPGAMGR_INTR_POL_JTAGM_RESET 0x1
4792 /* Extracts the ALT_FPGAMGR_INTR_POL_JTAGM field value from a register. */
4793 #define ALT_FPGAMGR_INTR_POL_JTAGM_GET(value) (((value) & 0x10000000) >> 28)
4794 /* Produces a ALT_FPGAMGR_INTR_POL_JTAGM register field value suitable for setting the register. */
4795 #define ALT_FPGAMGR_INTR_POL_JTAGM_SET(value) (((value) << 28) & 0x10000000)
4796 
4797 /*
4798  * Field : emr
4799  *
4800  * EMR valid bit
4801  *
4802  * Field Access Macros:
4803  *
4804  */
4805 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_INTR_POL_EMR register field. */
4806 #define ALT_FPGAMGR_INTR_POL_EMR_LSB 29
4807 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_INTR_POL_EMR register field. */
4808 #define ALT_FPGAMGR_INTR_POL_EMR_MSB 29
4809 /* The width in bits of the ALT_FPGAMGR_INTR_POL_EMR register field. */
4810 #define ALT_FPGAMGR_INTR_POL_EMR_WIDTH 1
4811 /* The mask used to set the ALT_FPGAMGR_INTR_POL_EMR register field value. */
4812 #define ALT_FPGAMGR_INTR_POL_EMR_SET_MSK 0x20000000
4813 /* The mask used to clear the ALT_FPGAMGR_INTR_POL_EMR register field value. */
4814 #define ALT_FPGAMGR_INTR_POL_EMR_CLR_MSK 0xdfffffff
4815 /* The reset value of the ALT_FPGAMGR_INTR_POL_EMR register field. */
4816 #define ALT_FPGAMGR_INTR_POL_EMR_RESET 0x1
4817 /* Extracts the ALT_FPGAMGR_INTR_POL_EMR field value from a register. */
4818 #define ALT_FPGAMGR_INTR_POL_EMR_GET(value) (((value) & 0x20000000) >> 29)
4819 /* Produces a ALT_FPGAMGR_INTR_POL_EMR register field value suitable for setting the register. */
4820 #define ALT_FPGAMGR_INTR_POL_EMR_SET(value) (((value) << 29) & 0x20000000)
4821 
4822 #ifndef __ASSEMBLY__
4823 /*
4824  * WARNING: The C register and register group struct declarations are provided for
4825  * convenience and illustrative purposes. They should, however, be used with
4826  * caution as the C language standard provides no guarantees about the alignment or
4827  * atomicity of device memory accesses. The recommended practice for writing
4828  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4829  * alt_write_word() functions.
4830  *
4831  * The struct declaration for register ALT_FPGAMGR_INTR_POL.
4832  */
4833 struct ALT_FPGAMGR_INTR_POL_s
4834 {
4835  uint32_t f2s_crc_error : 1; /* ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR */
4836  uint32_t f2s_early_usermode : 1; /* ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD */
4837  uint32_t f2s_usermode : 1; /* ALT_FPGAMGR_INTR_POL_F2S_USERMOD */
4838  uint32_t f2s_initdone_oe : 1; /* ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE */
4839  uint32_t f2s_nstatus_pin : 1; /* ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN */
4840  uint32_t f2s_nstatus_oe : 1; /* ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE */
4841  uint32_t f2s_condone_pin : 1; /* ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN */
4842  uint32_t f2s_condone_oe : 1; /* ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE */
4843  uint32_t f2s_cvp_conf_done : 1; /* ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE */
4844  uint32_t f2s_pr_ready : 1; /* ALT_FPGAMGR_INTR_POL_F2S_PR_RDY */
4845  uint32_t f2s_pr_done : 1; /* ALT_FPGAMGR_INTR_POL_F2S_PR_DONE */
4846  uint32_t f2s_pr_error : 1; /* ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR */
4847  uint32_t f2s_nconfig_pin : 1; /* ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN */
4848  uint32_t f2s_nceo_oe : 1; /* ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE */
4849  uint32_t : 2; /* *UNDEFINED* */
4850  uint32_t f2s_msel0 : 1; /* ALT_FPGAMGR_INTR_POL_F2S_MSEL0 */
4851  uint32_t f2s_msel1 : 1; /* ALT_FPGAMGR_INTR_POL_F2S_MSEL1 */
4852  uint32_t f2s_msel2 : 1; /* ALT_FPGAMGR_INTR_POL_F2S_MSEL2 */
4853  uint32_t : 5; /* *UNDEFINED* */
4854  uint32_t imgcfg_FifoEmpty : 1; /* ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY */
4855  uint32_t imgcfg_FifoFull : 1; /* ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL */
4856  uint32_t : 2; /* *UNDEFINED* */
4857  uint32_t jtagm : 1; /* ALT_FPGAMGR_INTR_POL_JTAGM */
4858  uint32_t emr : 1; /* ALT_FPGAMGR_INTR_POL_EMR */
4859  uint32_t : 2; /* *UNDEFINED* */
4860 };
4861 
4862 /* The typedef declaration for register ALT_FPGAMGR_INTR_POL. */
4863 typedef volatile struct ALT_FPGAMGR_INTR_POL_s ALT_FPGAMGR_INTR_POL_t;
4864 #endif /* __ASSEMBLY__ */
4865 
4866 /* The reset value of the ALT_FPGAMGR_INTR_POL register. */
4867 #define ALT_FPGAMGR_INTR_POL_RESET 0x33073fff
4868 /* The byte offset of the ALT_FPGAMGR_INTR_POL register from the beginning of the component. */
4869 #define ALT_FPGAMGR_INTR_POL_OFST 0x8c
4870 
4871 /*
4872  * Register : Control/Status Word Register - dma_config
4873  *
4874  * Consist of control bit and status information.
4875  *
4876  * Register Layout
4877  *
4878  * Bits | Access | Reset | Description
4879  * :--------|:-------|:--------|:---------------------------------
4880  * [7:0] | RW | 0x0 | ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL
4881  * [8] | RW | 0x0 | ALT_FPGAMGR_DMA_CFG_DMAREQ_EN
4882  * [15:9] | ??? | 0x0 | *UNDEFINED*
4883  * [16] | RW | 0x0 | ALT_FPGAMGR_DMA_CFG_CLRFIFO
4884  * [31:17] | ??? | Unknown | *UNDEFINED*
4885  *
4886  */
4887 /*
4888  * Field : dmareq_level
4889  *
4890  * DMA request threshold level
4891  *
4892  * Field Access Macros:
4893  *
4894  */
4895 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL register field. */
4896 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_LSB 0
4897 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL register field. */
4898 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_MSB 7
4899 /* The width in bits of the ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL register field. */
4900 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_WIDTH 8
4901 /* The mask used to set the ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL register field value. */
4902 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_SET_MSK 0x000000ff
4903 /* The mask used to clear the ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL register field value. */
4904 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_CLR_MSK 0xffffff00
4905 /* The reset value of the ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL register field. */
4906 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_RESET 0x0
4907 /* Extracts the ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL field value from a register. */
4908 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_GET(value) (((value) & 0x000000ff) >> 0)
4909 /* Produces a ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL register field value suitable for setting the register. */
4910 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_SET(value) (((value) << 0) & 0x000000ff)
4911 
4912 /*
4913  * Field : dmareq_enable
4914  *
4915  * Writing 1 will enable DMA request handshake from FPGA manager.
4916  *
4917  * Writing 0 will disable DMA request handshake from FPGA manager.
4918  *
4919  * Field Enumeration Values:
4920  *
4921  * Enum | Value | Description
4922  * :------------------------------------|:------|:------------
4923  * ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_E_DIS | 0x0 |
4924  * ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_E_EN | 0x1 |
4925  *
4926  * Field Access Macros:
4927  *
4928  */
4929 /*
4930  * Enumerated value for register field ALT_FPGAMGR_DMA_CFG_DMAREQ_EN
4931  *
4932  * DMA request handshake disable.
4933  */
4934 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_E_DIS 0x0
4935 /*
4936  * Enumerated value for register field ALT_FPGAMGR_DMA_CFG_DMAREQ_EN
4937  *
4938  * DMA request handshake enable
4939  */
4940 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_E_EN 0x1
4941 
4942 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_DMA_CFG_DMAREQ_EN register field. */
4943 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_LSB 8
4944 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_DMA_CFG_DMAREQ_EN register field. */
4945 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_MSB 8
4946 /* The width in bits of the ALT_FPGAMGR_DMA_CFG_DMAREQ_EN register field. */
4947 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_WIDTH 1
4948 /* The mask used to set the ALT_FPGAMGR_DMA_CFG_DMAREQ_EN register field value. */
4949 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_SET_MSK 0x00000100
4950 /* The mask used to clear the ALT_FPGAMGR_DMA_CFG_DMAREQ_EN register field value. */
4951 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_CLR_MSK 0xfffffeff
4952 /* The reset value of the ALT_FPGAMGR_DMA_CFG_DMAREQ_EN register field. */
4953 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_RESET 0x0
4954 /* Extracts the ALT_FPGAMGR_DMA_CFG_DMAREQ_EN field value from a register. */
4955 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_GET(value) (((value) & 0x00000100) >> 8)
4956 /* Produces a ALT_FPGAMGR_DMA_CFG_DMAREQ_EN register field value suitable for setting the register. */
4957 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_SET(value) (((value) << 8) & 0x00000100)
4958 
4959 /*
4960  * Field : clearFifo
4961  *
4962  * A write 1 to this bit field will empty the TxFifo. A read will always return 0.
4963  *
4964  * Field Access Macros:
4965  *
4966  */
4967 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_DMA_CFG_CLRFIFO register field. */
4968 #define ALT_FPGAMGR_DMA_CFG_CLRFIFO_LSB 16
4969 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_DMA_CFG_CLRFIFO register field. */
4970 #define ALT_FPGAMGR_DMA_CFG_CLRFIFO_MSB 16
4971 /* The width in bits of the ALT_FPGAMGR_DMA_CFG_CLRFIFO register field. */
4972 #define ALT_FPGAMGR_DMA_CFG_CLRFIFO_WIDTH 1
4973 /* The mask used to set the ALT_FPGAMGR_DMA_CFG_CLRFIFO register field value. */
4974 #define ALT_FPGAMGR_DMA_CFG_CLRFIFO_SET_MSK 0x00010000
4975 /* The mask used to clear the ALT_FPGAMGR_DMA_CFG_CLRFIFO register field value. */
4976 #define ALT_FPGAMGR_DMA_CFG_CLRFIFO_CLR_MSK 0xfffeffff
4977 /* The reset value of the ALT_FPGAMGR_DMA_CFG_CLRFIFO register field. */
4978 #define ALT_FPGAMGR_DMA_CFG_CLRFIFO_RESET 0x0
4979 /* Extracts the ALT_FPGAMGR_DMA_CFG_CLRFIFO field value from a register. */
4980 #define ALT_FPGAMGR_DMA_CFG_CLRFIFO_GET(value) (((value) & 0x00010000) >> 16)
4981 /* Produces a ALT_FPGAMGR_DMA_CFG_CLRFIFO register field value suitable for setting the register. */
4982 #define ALT_FPGAMGR_DMA_CFG_CLRFIFO_SET(value) (((value) << 16) & 0x00010000)
4983 
4984 #ifndef __ASSEMBLY__
4985 /*
4986  * WARNING: The C register and register group struct declarations are provided for
4987  * convenience and illustrative purposes. They should, however, be used with
4988  * caution as the C language standard provides no guarantees about the alignment or
4989  * atomicity of device memory accesses. The recommended practice for writing
4990  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4991  * alt_write_word() functions.
4992  *
4993  * The struct declaration for register ALT_FPGAMGR_DMA_CFG.
4994  */
4995 struct ALT_FPGAMGR_DMA_CFG_s
4996 {
4997  uint32_t dmareq_level : 8; /* ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL */
4998  uint32_t dmareq_enable : 1; /* ALT_FPGAMGR_DMA_CFG_DMAREQ_EN */
4999  uint32_t : 7; /* *UNDEFINED* */
5000  uint32_t clearFifo : 1; /* ALT_FPGAMGR_DMA_CFG_CLRFIFO */
5001  uint32_t : 15; /* *UNDEFINED* */
5002 };
5003 
5004 /* The typedef declaration for register ALT_FPGAMGR_DMA_CFG. */
5005 typedef volatile struct ALT_FPGAMGR_DMA_CFG_s ALT_FPGAMGR_DMA_CFG_t;
5006 #endif /* __ASSEMBLY__ */
5007 
5008 /* The reset value of the ALT_FPGAMGR_DMA_CFG register. */
5009 #define ALT_FPGAMGR_DMA_CFG_RESET 0x00000000
5010 /* The byte offset of the ALT_FPGAMGR_DMA_CFG register from the beginning of the component. */
5011 #define ALT_FPGAMGR_DMA_CFG_OFST 0x90
5012 
5013 /*
5014  * Register : Control/Status Word Register - imgcfg_fifo_status
5015  *
5016  * Consist of control bit and status information.
5017  *
5018  * Register Layout
5019  *
5020  * Bits | Access | Reset | Description
5021  * :--------|:-------|:--------|:---------------------------------------
5022  * [7:0] | RW | 0x0 | ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL
5023  * [8] | RW | 0x0 | ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL
5024  * [9] | RW | 0x1 | ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY
5025  * [31:10] | ??? | Unknown | *UNDEFINED*
5026  *
5027  */
5028 /*
5029  * Field : FifoLevel
5030  *
5031  * Number of words remaining in FPGA Image Configuration Fifo.
5032  *
5033  * Maximum value is 0x64
5034  *
5035  * Field Access Macros:
5036  *
5037  */
5038 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL register field. */
5039 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_LSB 0
5040 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL register field. */
5041 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_MSB 7
5042 /* The width in bits of the ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL register field. */
5043 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_WIDTH 8
5044 /* The mask used to set the ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL register field value. */
5045 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_SET_MSK 0x000000ff
5046 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL register field value. */
5047 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_CLR_MSK 0xffffff00
5048 /* The reset value of the ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL register field. */
5049 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_RESET 0x0
5050 /* Extracts the ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL field value from a register. */
5051 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_GET(value) (((value) & 0x000000ff) >> 0)
5052 /* Produces a ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL register field value suitable for setting the register. */
5053 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_SET(value) (((value) << 0) & 0x000000ff)
5054 
5055 /*
5056  * Field : FifoFull
5057  *
5058  * Read
5059  *
5060  * 1 -> Fifo Full
5061  *
5062  * 0 -> Fifo NOT full
5063  *
5064  * Field Access Macros:
5065  *
5066  */
5067 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL register field. */
5068 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_LSB 8
5069 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL register field. */
5070 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_MSB 8
5071 /* The width in bits of the ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL register field. */
5072 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_WIDTH 1
5073 /* The mask used to set the ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL register field value. */
5074 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_SET_MSK 0x00000100
5075 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL register field value. */
5076 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_CLR_MSK 0xfffffeff
5077 /* The reset value of the ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL register field. */
5078 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_RESET 0x0
5079 /* Extracts the ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL field value from a register. */
5080 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_GET(value) (((value) & 0x00000100) >> 8)
5081 /* Produces a ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL register field value suitable for setting the register. */
5082 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_SET(value) (((value) << 8) & 0x00000100)
5083 
5084 /*
5085  * Field : FifoEmpty
5086  *
5087  * Read
5088  *
5089  * 1 -> Fifo Empty
5090  *
5091  * 0 -> Fifo NOT Empty
5092  *
5093  * Field Access Macros:
5094  *
5095  */
5096 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY register field. */
5097 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_LSB 9
5098 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY register field. */
5099 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_MSB 9
5100 /* The width in bits of the ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY register field. */
5101 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_WIDTH 1
5102 /* The mask used to set the ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY register field value. */
5103 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_SET_MSK 0x00000200
5104 /* The mask used to clear the ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY register field value. */
5105 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_CLR_MSK 0xfffffdff
5106 /* The reset value of the ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY register field. */
5107 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_RESET 0x1
5108 /* Extracts the ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY field value from a register. */
5109 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_GET(value) (((value) & 0x00000200) >> 9)
5110 /* Produces a ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY register field value suitable for setting the register. */
5111 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_SET(value) (((value) << 9) & 0x00000200)
5112 
5113 #ifndef __ASSEMBLY__
5114 /*
5115  * WARNING: The C register and register group struct declarations are provided for
5116  * convenience and illustrative purposes. They should, however, be used with
5117  * caution as the C language standard provides no guarantees about the alignment or
5118  * atomicity of device memory accesses. The recommended practice for writing
5119  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5120  * alt_write_word() functions.
5121  *
5122  * The struct declaration for register ALT_FPGAMGR_IMGCFG_FIFO_STAT.
5123  */
5124 struct ALT_FPGAMGR_IMGCFG_FIFO_STAT_s
5125 {
5126  uint32_t FifoLevel : 8; /* ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL */
5127  uint32_t FifoFull : 1; /* ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL */
5128  uint32_t FifoEmpty : 1; /* ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY */
5129  uint32_t : 22; /* *UNDEFINED* */
5130 };
5131 
5132 /* The typedef declaration for register ALT_FPGAMGR_IMGCFG_FIFO_STAT. */
5133 typedef volatile struct ALT_FPGAMGR_IMGCFG_FIFO_STAT_s ALT_FPGAMGR_IMGCFG_FIFO_STAT_t;
5134 #endif /* __ASSEMBLY__ */
5135 
5136 /* The reset value of the ALT_FPGAMGR_IMGCFG_FIFO_STAT register. */
5137 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_RESET 0x00000200
5138 /* The byte offset of the ALT_FPGAMGR_IMGCFG_FIFO_STAT register from the beginning of the component. */
5139 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_OFST 0x94
5140 
5141 #ifndef __ASSEMBLY__
5142 /*
5143  * WARNING: The C register and register group struct declarations are provided for
5144  * convenience and illustrative purposes. They should, however, be used with
5145  * caution as the C language standard provides no guarantees about the alignment or
5146  * atomicity of device memory accesses. The recommended practice for writing
5147  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5148  * alt_write_word() functions.
5149  *
5150  * The struct declaration for register group ALT_FPGAMGR.
5151  */
5152 struct ALT_FPGAMGR_s
5153 {
5154  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
5155  ALT_FPGAMGR_DCLKCNT_t dclkcnt; /* ALT_FPGAMGR_DCLKCNT */
5156  ALT_FPGAMGR_DCLKSTAT_t dclkstat; /* ALT_FPGAMGR_DCLKSTAT */
5157  ALT_FPGAMGR_GPO_t gpo; /* ALT_FPGAMGR_GPO */
5158  ALT_FPGAMGR_GPI_t gpi; /* ALT_FPGAMGR_GPI */
5159  ALT_FPGAMGR_MISCI_t misci; /* ALT_FPGAMGR_MISCI */
5160  volatile uint32_t _pad_0x1c_0x2f[5]; /* *UNDEFINED* */
5161  ALT_FPGAMGR_EMR_DATA0_t emr_data0; /* ALT_FPGAMGR_EMR_DATA0 */
5162  ALT_FPGAMGR_EMR_DATA1_t emr_data1; /* ALT_FPGAMGR_EMR_DATA1 */
5163  ALT_FPGAMGR_EMR_DATA2_t emr_data2; /* ALT_FPGAMGR_EMR_DATA2 */
5164  ALT_FPGAMGR_EMR_DATA3_t emr_data3; /* ALT_FPGAMGR_EMR_DATA3 */
5165  ALT_FPGAMGR_EMR_DATA4_t emr_data4; /* ALT_FPGAMGR_EMR_DATA4 */
5166  ALT_FPGAMGR_EMR_DATA5_t emr_data5; /* ALT_FPGAMGR_EMR_DATA5 */
5167  ALT_FPGAMGR_EMR_VALID_t emr_valid; /* ALT_FPGAMGR_EMR_VALID */
5168  ALT_FPGAMGR_EMR_EN_t emr_en; /* ALT_FPGAMGR_EMR_EN */
5169  ALT_FPGAMGR_JTAG_CFG_t jtag_config; /* ALT_FPGAMGR_JTAG_CFG */
5170  ALT_FPGAMGR_JTAG_STAT_t jtag_status; /* ALT_FPGAMGR_JTAG_STAT */
5171  ALT_FPGAMGR_JTAG_KICK_t jtag_kick; /* ALT_FPGAMGR_JTAG_KICK */
5172  volatile uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */
5173  ALT_FPGAMGR_JTAG_DATA_W_t jtag_data_w; /* ALT_FPGAMGR_JTAG_DATA_W */
5174  ALT_FPGAMGR_JTAG_DATA_R_t jtag_data_r; /* ALT_FPGAMGR_JTAG_DATA_R */
5175  volatile uint32_t _pad_0x68_0x6f[2]; /* *UNDEFINED* */
5176  ALT_FPGAMGR_IMGCFG_CTL_00_t imgcfg_ctrl_00; /* ALT_FPGAMGR_IMGCFG_CTL_00 */
5177  ALT_FPGAMGR_IMGCFG_CTL_01_t imgcfg_ctrl_01; /* ALT_FPGAMGR_IMGCFG_CTL_01 */
5178  ALT_FPGAMGR_IMGCFG_CTL_02_t imgcfg_ctrl_02; /* ALT_FPGAMGR_IMGCFG_CTL_02 */
5179  volatile uint32_t _pad_0x7c_0x7f; /* *UNDEFINED* */
5180  ALT_FPGAMGR_IMGCFG_STAT_t imgcfg_stat; /* ALT_FPGAMGR_IMGCFG_STAT */
5181  ALT_FPGAMGR_INTR_MSKED_STAT_t intr_masked_status; /* ALT_FPGAMGR_INTR_MSKED_STAT */
5182  ALT_FPGAMGR_INTR_MSK_t intr_mask; /* ALT_FPGAMGR_INTR_MSK */
5183  ALT_FPGAMGR_INTR_POL_t intr_polarity; /* ALT_FPGAMGR_INTR_POL */
5184  ALT_FPGAMGR_DMA_CFG_t dma_config; /* ALT_FPGAMGR_DMA_CFG */
5185  ALT_FPGAMGR_IMGCFG_FIFO_STAT_t imgcfg_fifo_status; /* ALT_FPGAMGR_IMGCFG_FIFO_STAT */
5186  volatile uint32_t _pad_0x98_0x1000[986]; /* *UNDEFINED* */
5187 };
5188 
5189 /* The typedef declaration for register group ALT_FPGAMGR. */
5190 typedef volatile struct ALT_FPGAMGR_s ALT_FPGAMGR_t;
5191 /* The struct declaration for the raw register contents of register group ALT_FPGAMGR. */
5192 struct ALT_FPGAMGR_raw_s
5193 {
5194  uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
5195  volatile uint32_t dclkcnt; /* ALT_FPGAMGR_DCLKCNT */
5196  volatile uint32_t dclkstat; /* ALT_FPGAMGR_DCLKSTAT */
5197  volatile uint32_t gpo; /* ALT_FPGAMGR_GPO */
5198  volatile uint32_t gpi; /* ALT_FPGAMGR_GPI */
5199  volatile uint32_t misci; /* ALT_FPGAMGR_MISCI */
5200  uint32_t _pad_0x1c_0x2f[5]; /* *UNDEFINED* */
5201  volatile uint32_t emr_data0; /* ALT_FPGAMGR_EMR_DATA0 */
5202  volatile uint32_t emr_data1; /* ALT_FPGAMGR_EMR_DATA1 */
5203  volatile uint32_t emr_data2; /* ALT_FPGAMGR_EMR_DATA2 */
5204  volatile uint32_t emr_data3; /* ALT_FPGAMGR_EMR_DATA3 */
5205  volatile uint32_t emr_data4; /* ALT_FPGAMGR_EMR_DATA4 */
5206  volatile uint32_t emr_data5; /* ALT_FPGAMGR_EMR_DATA5 */
5207  volatile uint32_t emr_valid; /* ALT_FPGAMGR_EMR_VALID */
5208  volatile uint32_t emr_en; /* ALT_FPGAMGR_EMR_EN */
5209  volatile uint32_t jtag_config; /* ALT_FPGAMGR_JTAG_CFG */
5210  volatile uint32_t jtag_status; /* ALT_FPGAMGR_JTAG_STAT */
5211  volatile uint32_t jtag_kick; /* ALT_FPGAMGR_JTAG_KICK */
5212  uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */
5213  volatile uint32_t jtag_data_w; /* ALT_FPGAMGR_JTAG_DATA_W */
5214  volatile uint32_t jtag_data_r; /* ALT_FPGAMGR_JTAG_DATA_R */
5215  uint32_t _pad_0x68_0x6f[2]; /* *UNDEFINED* */
5216  volatile uint32_t imgcfg_ctrl_00; /* ALT_FPGAMGR_IMGCFG_CTL_00 */
5217  volatile uint32_t imgcfg_ctrl_01; /* ALT_FPGAMGR_IMGCFG_CTL_01 */
5218  volatile uint32_t imgcfg_ctrl_02; /* ALT_FPGAMGR_IMGCFG_CTL_02 */
5219  uint32_t _pad_0x7c_0x7f; /* *UNDEFINED* */
5220  volatile uint32_t imgcfg_stat; /* ALT_FPGAMGR_IMGCFG_STAT */
5221  volatile uint32_t intr_masked_status; /* ALT_FPGAMGR_INTR_MSKED_STAT */
5222  volatile uint32_t intr_mask; /* ALT_FPGAMGR_INTR_MSK */
5223  volatile uint32_t intr_polarity; /* ALT_FPGAMGR_INTR_POL */
5224  volatile uint32_t dma_config; /* ALT_FPGAMGR_DMA_CFG */
5225  volatile uint32_t imgcfg_fifo_status; /* ALT_FPGAMGR_IMGCFG_FIFO_STAT */
5226  uint32_t _pad_0x98_0x1000[986]; /* *UNDEFINED* */
5227 };
5228 
5229 /* The typedef declaration for the raw register contents of register group ALT_FPGAMGR. */
5230 typedef volatile struct ALT_FPGAMGR_raw_s ALT_FPGAMGR_raw_t;
5231 #endif /* __ASSEMBLY__ */
5232 
5233 
5234 #ifdef __cplusplus
5235 }
5236 #endif /* __cplusplus */
5237 #endif /* __ALT_SOCAL_FPGAMGR_H__ */
5238