35 #ifndef __ALT_SOCAL_SYSMGR_H__
36 #define __ALT_SOCAL_SYSMGR_H__
88 #define ALT_SYSMGR_CORE_SILICONID1_REV_E_REV1 0x1
91 #define ALT_SYSMGR_CORE_SILICONID1_REV_LSB 0
93 #define ALT_SYSMGR_CORE_SILICONID1_REV_MSB 15
95 #define ALT_SYSMGR_CORE_SILICONID1_REV_WIDTH 16
97 #define ALT_SYSMGR_CORE_SILICONID1_REV_SET_MSK 0x0000ffff
99 #define ALT_SYSMGR_CORE_SILICONID1_REV_CLR_MSK 0xffff0000
101 #define ALT_SYSMGR_CORE_SILICONID1_REV_RESET 0x1
103 #define ALT_SYSMGR_CORE_SILICONID1_REV_GET(value) (((value) & 0x0000ffff) >> 0)
105 #define ALT_SYSMGR_CORE_SILICONID1_REV_SET(value) (((value) << 0) & 0x0000ffff)
125 #define ALT_SYSMGR_CORE_SILICONID1_ID_E_HPS_STRATIX10 0x2
128 #define ALT_SYSMGR_CORE_SILICONID1_ID_LSB 16
130 #define ALT_SYSMGR_CORE_SILICONID1_ID_MSB 31
132 #define ALT_SYSMGR_CORE_SILICONID1_ID_WIDTH 16
134 #define ALT_SYSMGR_CORE_SILICONID1_ID_SET_MSK 0xffff0000
136 #define ALT_SYSMGR_CORE_SILICONID1_ID_CLR_MSK 0x0000ffff
138 #define ALT_SYSMGR_CORE_SILICONID1_ID_RESET 0x2
140 #define ALT_SYSMGR_CORE_SILICONID1_ID_GET(value) (((value) & 0xffff0000) >> 16)
142 #define ALT_SYSMGR_CORE_SILICONID1_ID_SET(value) (((value) << 16) & 0xffff0000)
156 struct ALT_SYSMGR_CORE_SILICONID1_s
158 const volatile uint32_t rev : 16;
159 const volatile uint32_t
id : 16;
163 typedef struct ALT_SYSMGR_CORE_SILICONID1_s ALT_SYSMGR_CORE_SILICONID1_t;
167 #define ALT_SYSMGR_CORE_SILICONID1_RESET 0x00020001
169 #define ALT_SYSMGR_CORE_SILICONID1_OFST 0x0
197 #define ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION_LSB 0
199 #define ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION_MSB 3
201 #define ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION_WIDTH 4
203 #define ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION_SET_MSK 0x0000000f
205 #define ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION_CLR_MSK 0xfffffff0
207 #define ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION_RESET 0x0
209 #define ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION_GET(value) (((value) & 0x0000000f) >> 0)
211 #define ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION_SET(value) (((value) << 0) & 0x0000000f)
222 #define ALT_SYSMGR_CORE_SILICONID2_RSV_LSB 4
224 #define ALT_SYSMGR_CORE_SILICONID2_RSV_MSB 31
226 #define ALT_SYSMGR_CORE_SILICONID2_RSV_WIDTH 28
228 #define ALT_SYSMGR_CORE_SILICONID2_RSV_SET_MSK 0xfffffff0
230 #define ALT_SYSMGR_CORE_SILICONID2_RSV_CLR_MSK 0x0000000f
232 #define ALT_SYSMGR_CORE_SILICONID2_RSV_RESET 0x0
234 #define ALT_SYSMGR_CORE_SILICONID2_RSV_GET(value) (((value) & 0xfffffff0) >> 4)
236 #define ALT_SYSMGR_CORE_SILICONID2_RSV_SET(value) (((value) << 4) & 0xfffffff0)
250 struct ALT_SYSMGR_CORE_SILICONID2_s
252 const volatile uint32_t device_revision : 4;
253 const volatile uint32_t rsv : 28;
257 typedef struct ALT_SYSMGR_CORE_SILICONID2_s ALT_SYSMGR_CORE_SILICONID2_t;
261 #define ALT_SYSMGR_CORE_SILICONID2_RESET 0x00000000
263 #define ALT_SYSMGR_CORE_SILICONID2_OFST 0x4
311 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_E_MODE_0_DONT_PAUSE 0x0
316 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_E_MODE_0_PAUSE_FOR_CPU0 0x1
321 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_E_MODE_0_PAUSE_FOR_CPU1 0x2
326 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_E_MODE_0_PAUSE_FOR_CPU2 0x4
331 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_E_MODE_0_PAUSE_FOR_CPU3 0x8
336 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_E_MODE_0_PAUSE_FOR_ANY_CPU 0xf
339 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_LSB 0
341 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_MSB 3
343 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_WIDTH 4
345 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_SET_MSK 0x0000000f
347 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_CLR_MSK 0xfffffff0
349 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_RESET 0x8
351 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_GET(value) (((value) & 0x0000000f) >> 0)
353 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_SET(value) (((value) << 0) & 0x0000000f)
379 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_E_MODE_1_DONT_PAUSE 0x0
384 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_E_MODE_1_PAUSE_FOR_CPU0 0x1
389 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_E_MODE_1_PAUSE_FOR_CPU1 0x2
394 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_E_MODE_1_PAUSE_FOR_CPU2 0x4
399 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_E_MODE_1_PAUSE_FOR_CPU3 0x8
404 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_E_MODE_1_PAUSE_FOR_ANY_CPU 0xf
407 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_LSB 8
409 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_MSB 11
411 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_WIDTH 4
413 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_SET_MSK 0x00000f00
415 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_CLR_MSK 0xfffff0ff
417 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_RESET 0x8
419 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_GET(value) (((value) & 0x00000f00) >> 8)
421 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_SET(value) (((value) << 8) & 0x00000f00)
447 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_E_MODE_2_DONT_PAUSE 0x0
452 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_E_MODE_2_PAUSE_FOR_CPU0 0x1
457 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_E_MODE_2_PAUSE_FOR_CPU1 0x2
462 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_E_MODE_2_PAUSE_FOR_CPU2 0x4
467 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_E_MODE_2_PAUSE_FOR_CPU3 0x8
472 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_E_MODE_2_PAUSE_FOR_ANY_CPU 0xf
475 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_LSB 16
477 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_MSB 19
479 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_WIDTH 4
481 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_SET_MSK 0x000f0000
483 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_CLR_MSK 0xfff0ffff
485 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_RESET 0x8
487 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_GET(value) (((value) & 0x000f0000) >> 16)
489 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_SET(value) (((value) << 16) & 0x000f0000)
515 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_E_MODE_3_DONT_PAUSE 0x0
520 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_E_MODE_3_PAUSE_FOR_CPU0 0x1
525 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_E_MODE_3_PAUSE_FOR_CPU1 0x2
530 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_E_MODE_3_PAUSE_FOR_CPU2 0x4
535 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_E_MODE_3_PAUSE_FOR_CPU3 0x8
540 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_E_MODE_3_PAUSE_FOR_ANY_CPU 0xf
543 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_LSB 24
545 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_MSB 27
547 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_WIDTH 4
549 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_SET_MSK 0x0f000000
551 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_CLR_MSK 0xf0ffffff
553 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_RESET 0x8
555 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_GET(value) (((value) & 0x0f000000) >> 24)
557 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_SET(value) (((value) << 24) & 0x0f000000)
571 struct ALT_SYSMGR_CORE_WDDBG_s
573 volatile uint32_t mode_0 : 4;
575 volatile uint32_t mode_1 : 4;
577 volatile uint32_t mode_2 : 4;
579 volatile uint32_t mode_3 : 4;
584 typedef struct ALT_SYSMGR_CORE_WDDBG_s ALT_SYSMGR_CORE_WDDBG_t;
588 #define ALT_SYSMGR_CORE_WDDBG_RESET 0x08080808
590 #define ALT_SYSMGR_CORE_WDDBG_OFST 0x8
617 #define ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR_LSB 0
619 #define ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR_MSB 0
621 #define ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR_WIDTH 1
623 #define ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR_SET_MSK 0x00000001
625 #define ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR_CLR_MSK 0xfffffffe
627 #define ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR_RESET 0x0
629 #define ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR_GET(value) (((value) & 0x00000001) >> 0)
631 #define ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR_SET(value) (((value) << 0) & 0x00000001)
645 struct ALT_SYSMGR_CORE_MPU_STATUS_s
647 const volatile uint32_t uncorrerr : 1;
652 typedef struct ALT_SYSMGR_CORE_MPU_STATUS_s ALT_SYSMGR_CORE_MPU_STATUS_t;
656 #define ALT_SYSMGR_CORE_MPU_STATUS_RESET 0x00000000
658 #define ALT_SYSMGR_CORE_MPU_STATUS_OFST 0x10
697 #define ALT_SYSMGR_CORE_MPU_ACE_AWQOS_E_LOW 0x0
702 #define ALT_SYSMGR_CORE_MPU_ACE_AWQOS_E_MED 0x1
707 #define ALT_SYSMGR_CORE_MPU_ACE_AWQOS_E_HIGH 0x2
710 #define ALT_SYSMGR_CORE_MPU_ACE_AWQOS_LSB 0
712 #define ALT_SYSMGR_CORE_MPU_ACE_AWQOS_MSB 3
714 #define ALT_SYSMGR_CORE_MPU_ACE_AWQOS_WIDTH 4
716 #define ALT_SYSMGR_CORE_MPU_ACE_AWQOS_SET_MSK 0x0000000f
718 #define ALT_SYSMGR_CORE_MPU_ACE_AWQOS_CLR_MSK 0xfffffff0
720 #define ALT_SYSMGR_CORE_MPU_ACE_AWQOS_RESET 0x2
722 #define ALT_SYSMGR_CORE_MPU_ACE_AWQOS_GET(value) (((value) & 0x0000000f) >> 0)
724 #define ALT_SYSMGR_CORE_MPU_ACE_AWQOS_SET(value) (((value) << 0) & 0x0000000f)
748 #define ALT_SYSMGR_CORE_MPU_ACE_ARQOS_E_LOW 0x0
753 #define ALT_SYSMGR_CORE_MPU_ACE_ARQOS_E_MED 0x1
758 #define ALT_SYSMGR_CORE_MPU_ACE_ARQOS_E_HIGH 0x2
761 #define ALT_SYSMGR_CORE_MPU_ACE_ARQOS_LSB 8
763 #define ALT_SYSMGR_CORE_MPU_ACE_ARQOS_MSB 12
765 #define ALT_SYSMGR_CORE_MPU_ACE_ARQOS_WIDTH 5
767 #define ALT_SYSMGR_CORE_MPU_ACE_ARQOS_SET_MSK 0x00001f00
769 #define ALT_SYSMGR_CORE_MPU_ACE_ARQOS_CLR_MSK 0xffffe0ff
771 #define ALT_SYSMGR_CORE_MPU_ACE_ARQOS_RESET 0x2
773 #define ALT_SYSMGR_CORE_MPU_ACE_ARQOS_GET(value) (((value) & 0x00001f00) >> 8)
775 #define ALT_SYSMGR_CORE_MPU_ACE_ARQOS_SET(value) (((value) << 8) & 0x00001f00)
789 struct ALT_SYSMGR_CORE_MPU_ACE_s
791 volatile uint32_t awqos : 4;
793 volatile uint32_t arqos : 5;
798 typedef struct ALT_SYSMGR_CORE_MPU_ACE_s ALT_SYSMGR_CORE_MPU_ACE_t;
802 #define ALT_SYSMGR_CORE_MPU_ACE_RESET 0x00000202
804 #define ALT_SYSMGR_CORE_MPU_ACE_OFST 0x14
848 #define ALT_SYSMGR_CORE_DMA_CHANSEL_0_E_FPGA 0x0
853 #define ALT_SYSMGR_CORE_DMA_CHANSEL_0_E_I2C4_TX 0x1
856 #define ALT_SYSMGR_CORE_DMA_CHANSEL_0_LSB 0
858 #define ALT_SYSMGR_CORE_DMA_CHANSEL_0_MSB 0
860 #define ALT_SYSMGR_CORE_DMA_CHANSEL_0_WIDTH 1
862 #define ALT_SYSMGR_CORE_DMA_CHANSEL_0_SET_MSK 0x00000001
864 #define ALT_SYSMGR_CORE_DMA_CHANSEL_0_CLR_MSK 0xfffffffe
866 #define ALT_SYSMGR_CORE_DMA_CHANSEL_0_RESET 0x0
868 #define ALT_SYSMGR_CORE_DMA_CHANSEL_0_GET(value) (((value) & 0x00000001) >> 0)
870 #define ALT_SYSMGR_CORE_DMA_CHANSEL_0_SET(value) (((value) << 0) & 0x00000001)
891 #define ALT_SYSMGR_CORE_DMA_CHANSEL_1_E_FPGA 0x0
896 #define ALT_SYSMGR_CORE_DMA_CHANSEL_1_E_I2C4_RX 0x1
899 #define ALT_SYSMGR_CORE_DMA_CHANSEL_1_LSB 4
901 #define ALT_SYSMGR_CORE_DMA_CHANSEL_1_MSB 4
903 #define ALT_SYSMGR_CORE_DMA_CHANSEL_1_WIDTH 1
905 #define ALT_SYSMGR_CORE_DMA_CHANSEL_1_SET_MSK 0x00000010
907 #define ALT_SYSMGR_CORE_DMA_CHANSEL_1_CLR_MSK 0xffffffef
909 #define ALT_SYSMGR_CORE_DMA_CHANSEL_1_RESET 0x0
911 #define ALT_SYSMGR_CORE_DMA_CHANSEL_1_GET(value) (((value) & 0x00000010) >> 4)
913 #define ALT_SYSMGR_CORE_DMA_CHANSEL_1_SET(value) (((value) << 4) & 0x00000010)
930 #define ALT_SYSMGR_CORE_DMA_MGR_NS_LSB 16
932 #define ALT_SYSMGR_CORE_DMA_MGR_NS_MSB 16
934 #define ALT_SYSMGR_CORE_DMA_MGR_NS_WIDTH 1
936 #define ALT_SYSMGR_CORE_DMA_MGR_NS_SET_MSK 0x00010000
938 #define ALT_SYSMGR_CORE_DMA_MGR_NS_CLR_MSK 0xfffeffff
940 #define ALT_SYSMGR_CORE_DMA_MGR_NS_RESET 0x0
942 #define ALT_SYSMGR_CORE_DMA_MGR_NS_GET(value) (((value) & 0x00010000) >> 16)
944 #define ALT_SYSMGR_CORE_DMA_MGR_NS_SET(value) (((value) << 16) & 0x00010000)
960 #define ALT_SYSMGR_CORE_DMA_IRQ_NS_LSB 24
962 #define ALT_SYSMGR_CORE_DMA_IRQ_NS_MSB 31
964 #define ALT_SYSMGR_CORE_DMA_IRQ_NS_WIDTH 8
966 #define ALT_SYSMGR_CORE_DMA_IRQ_NS_SET_MSK 0xff000000
968 #define ALT_SYSMGR_CORE_DMA_IRQ_NS_CLR_MSK 0x00ffffff
970 #define ALT_SYSMGR_CORE_DMA_IRQ_NS_RESET 0x0
972 #define ALT_SYSMGR_CORE_DMA_IRQ_NS_GET(value) (((value) & 0xff000000) >> 24)
974 #define ALT_SYSMGR_CORE_DMA_IRQ_NS_SET(value) (((value) << 24) & 0xff000000)
988 struct ALT_SYSMGR_CORE_DMA_s
990 volatile uint32_t chansel_0 : 1;
992 volatile uint32_t chansel_1 : 1;
994 volatile uint32_t mgr_ns : 1;
996 volatile uint32_t irq_ns : 8;
1000 typedef struct ALT_SYSMGR_CORE_DMA_s ALT_SYSMGR_CORE_DMA_t;
1004 #define ALT_SYSMGR_CORE_DMA_RESET 0x00000000
1006 #define ALT_SYSMGR_CORE_DMA_OFST 0x20
1040 #define ALT_SYSMGR_CORE_DMA_PERIPH_NS_LSB 0
1042 #define ALT_SYSMGR_CORE_DMA_PERIPH_NS_MSB 31
1044 #define ALT_SYSMGR_CORE_DMA_PERIPH_NS_WIDTH 32
1046 #define ALT_SYSMGR_CORE_DMA_PERIPH_NS_SET_MSK 0xffffffff
1048 #define ALT_SYSMGR_CORE_DMA_PERIPH_NS_CLR_MSK 0x00000000
1050 #define ALT_SYSMGR_CORE_DMA_PERIPH_NS_RESET 0x0
1052 #define ALT_SYSMGR_CORE_DMA_PERIPH_NS_GET(value) (((value) & 0xffffffff) >> 0)
1054 #define ALT_SYSMGR_CORE_DMA_PERIPH_NS_SET(value) (((value) << 0) & 0xffffffff)
1056 #ifndef __ASSEMBLY__
1068 struct ALT_SYSMGR_CORE_DMA_PERIPH_s
1070 volatile uint32_t ns : 32;
1074 typedef struct ALT_SYSMGR_CORE_DMA_PERIPH_s ALT_SYSMGR_CORE_DMA_PERIPH_t;
1078 #define ALT_SYSMGR_CORE_DMA_PERIPH_RESET 0x00000000
1080 #define ALT_SYSMGR_CORE_DMA_PERIPH_OFST 0x24
1123 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES0 0x0
1128 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES45 0x1
1133 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES90 0x2
1138 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES135 0x3
1143 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES180 0x4
1148 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES225 0x5
1153 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES270 0x6
1158 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES315 0x7
1161 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_LSB 0
1163 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_MSB 2
1165 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_WIDTH 3
1167 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_SET_MSK 0x00000007
1169 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_CLR_MSK 0xfffffff8
1171 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_RESET 0x0
1173 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_GET(value) (((value) & 0x00000007) >> 0)
1175 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_SET(value) (((value) << 0) & 0x00000007)
1202 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES0 0x0
1207 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES45 0x1
1212 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES90 0x2
1217 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES135 0x3
1222 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES180 0x4
1227 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES225 0x5
1232 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES270 0x6
1237 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES315 0x7
1240 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_LSB 4
1242 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_MSB 6
1244 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_WIDTH 3
1246 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_SET_MSK 0x00000070
1248 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_CLR_MSK 0xffffff8f
1250 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_RESET 0x0
1252 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_GET(value) (((value) & 0x00000070) >> 4)
1254 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_SET(value) (((value) << 4) & 0x00000070)
1256 #ifndef __ASSEMBLY__
1268 struct ALT_SYSMGR_CORE_SDMMC_s
1270 volatile uint32_t drvsel : 3;
1272 volatile uint32_t smplsel : 3;
1277 typedef struct ALT_SYSMGR_CORE_SDMMC_s ALT_SYSMGR_CORE_SDMMC_t;
1281 #define ALT_SYSMGR_CORE_SDMMC_RESET 0x00000000
1283 #define ALT_SYSMGR_CORE_SDMMC_OFST 0x28
1346 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT_LSB 0
1348 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT_MSB 3
1350 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT_WIDTH 4
1352 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT_SET_MSK 0x0000000f
1354 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT_CLR_MSK 0xfffffff0
1356 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT_RESET 0x1
1358 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT_GET(value) (((value) & 0x0000000f) >> 0)
1360 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT_SET(value) (((value) << 0) & 0x0000000f)
1371 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1_LSB 4
1373 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1_MSB 5
1375 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1_WIDTH 2
1377 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1_SET_MSK 0x00000030
1379 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1_CLR_MSK 0xffffffcf
1381 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1_RESET 0x0
1383 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1_GET(value) (((value) & 0x00000030) >> 4)
1385 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1_SET(value) (((value) << 4) & 0x00000030)
1396 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6_LSB 8
1398 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6_MSB 9
1400 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6_WIDTH 2
1402 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6_SET_MSK 0x00000300
1404 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6_CLR_MSK 0xfffffcff
1406 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6_RESET 0x3
1408 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6_GET(value) (((value) & 0x00000300) >> 8)
1410 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6_SET(value) (((value) << 8) & 0x00000300)
1421 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13_LSB 16
1423 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13_MSB 25
1425 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13_WIDTH 10
1427 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13_SET_MSK 0x03ff0000
1429 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13_CLR_MSK 0xfc00ffff
1431 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13_RESET 0x0
1433 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13_GET(value) (((value) & 0x03ff0000) >> 16)
1435 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13_SET(value) (((value) << 16) & 0x03ff0000)
1437 #ifndef __ASSEMBLY__
1449 struct ALT_SYSMGR_CORE_SDMMC_L3MASTER_s
1451 volatile uint32_t hprot : 4;
1452 volatile uint32_t hauser0_1 : 2;
1454 volatile uint32_t hauser7_6 : 2;
1456 volatile uint32_t hauser22_13 : 10;
1461 typedef struct ALT_SYSMGR_CORE_SDMMC_L3MASTER_s ALT_SYSMGR_CORE_SDMMC_L3MASTER_t;
1465 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_RESET 0x00000301
1467 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_OFST 0x2c
1503 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT_LSB 0
1505 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT_MSB 0
1507 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT_WIDTH 1
1509 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT_SET_MSK 0x00000001
1511 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT_CLR_MSK 0xfffffffe
1513 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT_RESET 0x0
1515 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT_GET(value) (((value) & 0x00000001) >> 0)
1517 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT_SET(value) (((value) << 0) & 0x00000001)
1529 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0_LSB 8
1531 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0_MSB 8
1533 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0_WIDTH 1
1535 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0_SET_MSK 0x00000100
1537 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0_CLR_MSK 0xfffffeff
1539 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0_RESET 0x0
1541 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0_GET(value) (((value) & 0x00000100) >> 8)
1543 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0_SET(value) (((value) << 8) & 0x00000100)
1555 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR_LSB 16
1557 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR_MSB 16
1559 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR_WIDTH 1
1561 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR_SET_MSK 0x00010000
1563 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR_CLR_MSK 0xfffeffff
1565 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR_RESET 0x0
1567 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR_GET(value) (((value) & 0x00010000) >> 16)
1569 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR_SET(value) (((value) << 16) & 0x00010000)
1580 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_LSB 24
1582 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_MSB 24
1584 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_WIDTH 1
1586 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_SET_MSK 0x01000000
1588 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_CLR_MSK 0xfeffffff
1590 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_RESET 0x0
1592 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_GET(value) (((value) & 0x01000000) >> 24)
1594 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_SET(value) (((value) << 24) & 0x01000000)
1611 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16_LSB 28
1613 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16_MSB 28
1615 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16_WIDTH 1
1617 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16_SET_MSK 0x10000000
1619 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16_CLR_MSK 0xefffffff
1621 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16_RESET 0x0
1623 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16_GET(value) (((value) & 0x10000000) >> 28)
1625 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16_SET(value) (((value) << 28) & 0x10000000)
1627 #ifndef __ASSEMBLY__
1639 struct ALT_SYSMGR_CORE_NAND_BOOTSTRAP_s
1641 volatile uint32_t noinit : 1;
1643 volatile uint32_t noloadb0p0 : 1;
1645 volatile uint32_t tworowaddr : 1;
1647 volatile uint32_t page512 : 1;
1649 volatile uint32_t page512_x16 : 1;
1654 typedef struct ALT_SYSMGR_CORE_NAND_BOOTSTRAP_s ALT_SYSMGR_CORE_NAND_BOOTSTRAP_t;
1658 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_RESET 0x00000000
1660 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_OFST 0x30
1722 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_NONCACHE_NONBUFF 0x0
1727 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_BUFF 0x1
1732 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_NONALLOC 0x2
1737 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
1742 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_RESERVED1 0x4
1747 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_RESERVED2 0x5
1752 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
1757 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
1762 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_RESERVED3 0x8
1767 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_RESERVED4 0x9
1772 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
1777 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
1782 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_RESERVED5 0xc
1787 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_RESERVED6 0xd
1792 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
1797 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
1800 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_LSB 0
1802 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_MSB 3
1804 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_WIDTH 4
1806 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_SET_MSK 0x0000000f
1808 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_CLR_MSK 0xfffffff0
1810 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_RESET 0x0
1812 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_GET(value) (((value) & 0x0000000f) >> 0)
1814 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_SET(value) (((value) << 0) & 0x0000000f)
1849 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_NONCACHE_NONBUFF 0x0
1854 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_BUFF 0x1
1859 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_NONALLOC 0x2
1864 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
1869 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_RESERVED1 0x4
1874 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_RESERVED2 0x5
1879 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
1884 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
1889 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_RESERVED3 0x8
1894 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_RESERVED4 0x9
1899 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
1904 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
1909 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_RESERVED5 0xc
1914 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_RESERVED6 0xd
1919 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
1924 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
1927 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_LSB 4
1929 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_MSB 7
1931 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_WIDTH 4
1933 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_SET_MSK 0x000000f0
1935 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_CLR_MSK 0xffffff0f
1937 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_RESET 0x0
1939 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_GET(value) (((value) & 0x000000f0) >> 4)
1941 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_SET(value) (((value) << 4) & 0x000000f0)
1952 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN_LSB 8
1954 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN_MSB 9
1956 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN_WIDTH 2
1958 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN_SET_MSK 0x00000300
1960 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN_CLR_MSK 0xfffffcff
1962 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN_RESET 0x3
1964 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN_GET(value) (((value) & 0x00000300) >> 8)
1966 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN_SET(value) (((value) << 8) & 0x00000300)
1977 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN_LSB 12
1979 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN_MSB 13
1981 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN_WIDTH 2
1983 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN_SET_MSK 0x00003000
1985 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN_CLR_MSK 0xffffcfff
1987 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN_RESET 0x3
1989 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN_GET(value) (((value) & 0x00003000) >> 12)
1991 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN_SET(value) (((value) << 12) & 0x00003000)
2002 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT_LSB 16
2004 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT_MSB 18
2006 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT_WIDTH 3
2008 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT_SET_MSK 0x00070000
2010 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT_CLR_MSK 0xfff8ffff
2012 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT_RESET 0x0
2014 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT_GET(value) (((value) & 0x00070000) >> 16)
2016 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT_SET(value) (((value) << 16) & 0x00070000)
2027 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT_LSB 20
2029 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT_MSB 22
2031 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT_WIDTH 3
2033 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT_SET_MSK 0x00700000
2035 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT_CLR_MSK 0xff8fffff
2037 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT_RESET 0x0
2039 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT_GET(value) (((value) & 0x00700000) >> 20)
2041 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT_SET(value) (((value) << 20) & 0x00700000)
2043 #ifndef __ASSEMBLY__
2055 struct ALT_SYSMGR_CORE_NAND_L3MASTER_s
2057 volatile uint32_t arcache_0 : 4;
2058 volatile uint32_t awcache_0 : 4;
2059 volatile uint32_t awdomain : 2;
2061 volatile uint32_t ardomain : 2;
2063 volatile uint32_t awprot : 3;
2065 volatile uint32_t arprot : 3;
2070 typedef struct ALT_SYSMGR_CORE_NAND_L3MASTER_s ALT_SYSMGR_CORE_NAND_L3MASTER_t;
2074 #define ALT_SYSMGR_CORE_NAND_L3MASTER_RESET 0x00003300
2076 #define ALT_SYSMGR_CORE_NAND_L3MASTER_OFST 0x34
2119 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT_LSB 0
2121 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT_MSB 3
2123 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT_WIDTH 4
2125 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT_SET_MSK 0x0000000f
2127 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT_CLR_MSK 0xfffffff0
2129 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT_RESET 0x1
2131 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT_GET(value) (((value) & 0x0000000f) >> 0)
2133 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT_SET(value) (((value) << 0) & 0x0000000f)
2144 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0_LSB 8
2146 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0_MSB 8
2148 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0_WIDTH 1
2150 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0_SET_MSK 0x00000100
2152 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0_CLR_MSK 0xfffffeff
2154 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0_RESET 0x0
2156 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0_GET(value) (((value) & 0x00000100) >> 8)
2158 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0_SET(value) (((value) << 8) & 0x00000100)
2169 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1_LSB 9
2171 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1_MSB 9
2173 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1_WIDTH 1
2175 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1_SET_MSK 0x00000200
2177 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1_CLR_MSK 0xfffffdff
2179 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1_RESET 0x0
2181 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1_GET(value) (((value) & 0x00000200) >> 9)
2183 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1_SET(value) (((value) << 9) & 0x00000200)
2194 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6_LSB 12
2196 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6_MSB 13
2198 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6_WIDTH 2
2200 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6_SET_MSK 0x00003000
2202 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6_CLR_MSK 0xffffcfff
2204 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6_RESET 0x3
2206 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6_GET(value) (((value) & 0x00003000) >> 12)
2208 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6_SET(value) (((value) << 12) & 0x00003000)
2219 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13_LSB 16
2221 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13_MSB 25
2223 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13_WIDTH 10
2225 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13_SET_MSK 0x03ff0000
2227 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13_CLR_MSK 0xfc00ffff
2229 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13_RESET 0x0
2231 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13_GET(value) (((value) & 0x03ff0000) >> 16)
2233 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13_SET(value) (((value) << 16) & 0x03ff0000)
2235 #ifndef __ASSEMBLY__
2247 struct ALT_SYSMGR_CORE_USB0_L3MASTER_s
2249 volatile uint32_t hprot : 4;
2251 volatile uint32_t hauser_0 : 1;
2252 volatile uint32_t hauser_1 : 1;
2254 volatile uint32_t hauser7_6 : 2;
2256 volatile uint32_t hauser22_13 : 10;
2261 typedef struct ALT_SYSMGR_CORE_USB0_L3MASTER_s ALT_SYSMGR_CORE_USB0_L3MASTER_t;
2265 #define ALT_SYSMGR_CORE_USB0_L3MASTER_RESET 0x00003001
2267 #define ALT_SYSMGR_CORE_USB0_L3MASTER_OFST 0x38
2310 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT_LSB 0
2312 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT_MSB 3
2314 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT_WIDTH 4
2316 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT_SET_MSK 0x0000000f
2318 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT_CLR_MSK 0xfffffff0
2320 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT_RESET 0x1
2322 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT_GET(value) (((value) & 0x0000000f) >> 0)
2324 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT_SET(value) (((value) << 0) & 0x0000000f)
2335 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0_LSB 8
2337 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0_MSB 8
2339 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0_WIDTH 1
2341 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0_SET_MSK 0x00000100
2343 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0_CLR_MSK 0xfffffeff
2345 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0_RESET 0x0
2347 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0_GET(value) (((value) & 0x00000100) >> 8)
2349 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0_SET(value) (((value) << 8) & 0x00000100)
2360 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1_LSB 9
2362 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1_MSB 9
2364 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1_WIDTH 1
2366 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1_SET_MSK 0x00000200
2368 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1_CLR_MSK 0xfffffdff
2370 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1_RESET 0x0
2372 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1_GET(value) (((value) & 0x00000200) >> 9)
2374 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1_SET(value) (((value) << 9) & 0x00000200)
2385 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6_LSB 12
2387 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6_MSB 13
2389 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6_WIDTH 2
2391 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6_SET_MSK 0x00003000
2393 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6_CLR_MSK 0xffffcfff
2395 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6_RESET 0x3
2397 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6_GET(value) (((value) & 0x00003000) >> 12)
2399 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6_SET(value) (((value) << 12) & 0x00003000)
2410 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13_LSB 16
2412 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13_MSB 25
2414 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13_WIDTH 10
2416 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13_SET_MSK 0x03ff0000
2418 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13_CLR_MSK 0xfc00ffff
2420 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13_RESET 0x0
2422 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13_GET(value) (((value) & 0x03ff0000) >> 16)
2424 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13_SET(value) (((value) << 16) & 0x03ff0000)
2426 #ifndef __ASSEMBLY__
2438 struct ALT_SYSMGR_CORE_USB1_L3MASTER_s
2440 volatile uint32_t hprot : 4;
2442 volatile uint32_t hauser_0 : 1;
2443 volatile uint32_t hauser_1 : 1;
2445 volatile uint32_t hauser7_6 : 2;
2447 volatile uint32_t hauser22_13 : 10;
2452 typedef struct ALT_SYSMGR_CORE_USB1_L3MASTER_s ALT_SYSMGR_CORE_USB1_L3MASTER_t;
2456 #define ALT_SYSMGR_CORE_USB1_L3MASTER_RESET 0x00003001
2458 #define ALT_SYSMGR_CORE_USB1_L3MASTER_OFST 0x3c
2499 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL_E_EMAC_PTP_CLK 0x0
2504 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL_E_F2S_PTP_REF_CLK 0x1
2507 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL_LSB 0
2509 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL_MSB 0
2511 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL_WIDTH 1
2513 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL_SET_MSK 0x00000001
2515 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL_CLR_MSK 0xfffffffe
2517 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL_RESET 0x0
2519 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL_GET(value) (((value) & 0x00000001) >> 0)
2521 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL_SET(value) (((value) << 0) & 0x00000001)
2523 #ifndef __ASSEMBLY__
2535 struct ALT_SYSMGR_CORE_EMAC_GLOBAL_s
2537 volatile uint32_t ptp_clk_sel : 1;
2542 typedef struct ALT_SYSMGR_CORE_EMAC_GLOBAL_s ALT_SYSMGR_CORE_EMAC_GLOBAL_t;
2546 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_RESET 0x00000000
2548 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_OFST 0x40
2601 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_E_GMII_MII 0x0
2606 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_E_RGMII 0x1
2611 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_E_RMII 0x2
2616 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_E_RESET 0x3
2619 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_LSB 0
2621 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_MSB 1
2623 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_WIDTH 2
2625 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_SET_MSK 0x00000003
2627 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_CLR_MSK 0xfffffffc
2629 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_RESET 0x3
2631 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_GET(value) (((value) & 0x00000003) >> 0)
2633 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_SET(value) (((value) << 0) & 0x00000003)
2657 #define ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL_E_INTERNAL 0x0
2662 #define ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL_E_EXTERNAL 0x1
2665 #define ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL_LSB 8
2667 #define ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL_MSB 8
2669 #define ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL_WIDTH 1
2671 #define ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL_SET_MSK 0x00000100
2673 #define ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL_CLR_MSK 0xfffffeff
2675 #define ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL_RESET 0x0
2677 #define ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL_GET(value) (((value) & 0x00000100) >> 8)
2679 #define ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL_SET(value) (((value) << 8) & 0x00000100)
2702 #define ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL_E_L4_MP_CLK 0x0
2707 #define ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL_E_F2S_AP_CLK 0x1
2710 #define ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL_LSB 12
2712 #define ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL_MSB 12
2714 #define ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL_WIDTH 1
2716 #define ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL_SET_MSK 0x00001000
2718 #define ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL_CLR_MSK 0xffffefff
2720 #define ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL_RESET 0x0
2722 #define ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL_GET(value) (((value) & 0x00001000) >> 12)
2724 #define ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL_SET(value) (((value) << 12) & 0x00001000)
2761 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_NONCACHE_NONBUFF 0x0
2766 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_BUFF 0x1
2771 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_NONALLOC 0x2
2776 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_BUFF_NONALLOC 0x3
2781 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_RESERVED1 0x4
2786 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_RESERVED2 0x5
2791 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
2796 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_WRBACK_RDALLOC 0x7
2801 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_RESERVED3 0x8
2806 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_RESERVED4 0x9
2811 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
2816 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_WRBACK_WRALLOC 0xb
2821 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_RESERVED5 0xc
2826 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_RESERVED6 0xd
2831 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_WRTHRU_ALLOC 0xe
2836 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_WRBACK_ALLOC 0xf
2839 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_LSB 16
2841 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_MSB 19
2843 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_WIDTH 4
2845 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_SET_MSK 0x000f0000
2847 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_CLR_MSK 0xfff0ffff
2849 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_RESET 0x0
2851 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_GET(value) (((value) & 0x000f0000) >> 16)
2853 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_SET(value) (((value) << 16) & 0x000f0000)
2890 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_NONCACHE_NONBUFF 0x0
2895 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_BUFF 0x1
2900 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_NONALLOC 0x2
2905 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_BUFF_NONALLOC 0x3
2910 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_RESERVED1 0x4
2915 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_RESERVED2 0x5
2920 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
2925 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_WRBACK_RDALLOC 0x7
2930 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_RESERVED3 0x8
2935 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_RESERVED4 0x9
2940 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
2945 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_WRBACK_WRALLOC 0xb
2950 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_RESERVED5 0xc
2955 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_RESERVED6 0xd
2960 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_WRTHRU_ALLOC 0xe
2965 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_WRBACK_ALLOC 0xf
2968 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_LSB 20
2970 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_MSB 23
2972 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_WIDTH 4
2974 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_SET_MSK 0x00f00000
2976 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_CLR_MSK 0xff0fffff
2978 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_RESET 0x0
2980 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_GET(value) (((value) & 0x00f00000) >> 20)
2982 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_SET(value) (((value) << 20) & 0x00f00000)
3024 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_E_SECURE_NORMAL 0x0
3030 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_E_SECURE_PRIVILEGED 0x1
3036 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_E_NONSECURE_NORMAL 0x2
3042 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_E_NONSECURE_PRIVILEGED 0x3
3045 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_LSB 24
3047 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_MSB 26
3049 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_WIDTH 3
3051 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_SET_MSK 0x07000000
3053 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_CLR_MSK 0xf8ffffff
3055 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_RESET 0x2
3057 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_GET(value) (((value) & 0x07000000) >> 24)
3059 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_SET(value) (((value) << 24) & 0x07000000)
3101 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_E_SECURE_NORMAL 0x0
3107 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_E_SECURE_PRIVILEGED 0x1
3113 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_E_NONSECURE_NORMAL 0x2
3119 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_E_NONSECURE_PRIVILEGED 0x3
3122 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_LSB 27
3124 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_MSB 29
3126 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_WIDTH 3
3128 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_SET_MSK 0x38000000
3130 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_CLR_MSK 0xc7ffffff
3132 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_RESET 0x2
3134 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_GET(value) (((value) & 0x38000000) >> 27)
3136 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_SET(value) (((value) << 27) & 0x38000000)
3159 #define ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN 0x0
3164 #define ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN 0x1
3167 #define ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS_LSB 30
3169 #define ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS_MSB 30
3171 #define ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS_WIDTH 1
3173 #define ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS_SET_MSK 0x40000000
3175 #define ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS_CLR_MSK 0xbfffffff
3177 #define ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS_RESET 0x0
3179 #define ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS_GET(value) (((value) & 0x40000000) >> 30)
3181 #define ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS_SET(value) (((value) << 30) & 0x40000000)
3192 #define ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE_LSB 31
3194 #define ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE_MSB 31
3196 #define ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE_WIDTH 1
3198 #define ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE_SET_MSK 0x80000000
3200 #define ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE_CLR_MSK 0x7fffffff
3202 #define ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE_RESET 0x0
3204 #define ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE_GET(value) (((value) & 0x80000000) >> 31)
3206 #define ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE_SET(value) (((value) << 31) & 0x80000000)
3208 #ifndef __ASSEMBLY__
3220 struct ALT_SYSMGR_CORE_EMAC0_s
3222 volatile uint32_t phy_intf_sel : 2;
3224 volatile uint32_t ptp_ref_sel : 1;
3226 volatile uint32_t app_clk_sel : 1;
3228 volatile uint32_t arcache : 4;
3229 volatile uint32_t awcache : 4;
3230 volatile uint32_t arprot : 3;
3231 volatile uint32_t awprot : 3;
3232 volatile uint32_t sbd_data_endianness : 1;
3233 volatile uint32_t axi_disable : 1;
3237 typedef struct ALT_SYSMGR_CORE_EMAC0_s ALT_SYSMGR_CORE_EMAC0_t;
3241 #define ALT_SYSMGR_CORE_EMAC0_RESET 0x12000003
3243 #define ALT_SYSMGR_CORE_EMAC0_OFST 0x44
3296 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_E_GMII_MII 0x0
3301 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_E_RGMII 0x1
3306 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_E_RMII 0x2
3311 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_E_RESET 0x3
3314 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_LSB 0
3316 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_MSB 1
3318 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_WIDTH 2
3320 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_SET_MSK 0x00000003
3322 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_CLR_MSK 0xfffffffc
3324 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_RESET 0x3
3326 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_GET(value) (((value) & 0x00000003) >> 0)
3328 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_SET(value) (((value) << 0) & 0x00000003)
3352 #define ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL_E_INTERNAL 0x0
3357 #define ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL_E_EXTERNAL 0x1
3360 #define ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL_LSB 8
3362 #define ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL_MSB 8
3364 #define ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL_WIDTH 1
3366 #define ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL_SET_MSK 0x00000100
3368 #define ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL_CLR_MSK 0xfffffeff
3370 #define ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL_RESET 0x0
3372 #define ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL_GET(value) (((value) & 0x00000100) >> 8)
3374 #define ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL_SET(value) (((value) << 8) & 0x00000100)
3397 #define ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL_E_L4_MP_CLK 0x0
3402 #define ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL_E_F2S_AP_CLK 0x1
3405 #define ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL_LSB 12
3407 #define ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL_MSB 12
3409 #define ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL_WIDTH 1
3411 #define ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL_SET_MSK 0x00001000
3413 #define ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL_CLR_MSK 0xffffefff
3415 #define ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL_RESET 0x0
3417 #define ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL_GET(value) (((value) & 0x00001000) >> 12)
3419 #define ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL_SET(value) (((value) << 12) & 0x00001000)
3456 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_F2S_AP_CLK 0x0
3461 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_BUFF 0x1
3466 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_NONALLOC 0x2
3471 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_BUFF_NONALLOC 0x3
3476 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_RESERVED1 0x4
3481 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_RESERVED2 0x5
3486 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
3491 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_WRBACK_RDALLOC 0x7
3496 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_RESERVED3 0x8
3501 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_RESERVED4 0x9
3506 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
3511 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_WRBACK_WRALLOC 0xb
3516 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_RESERVED5 0xc
3521 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_RESERVED6 0xd
3526 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_WRTHRU_ALLOC 0xe
3531 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_WRBACK_ALLOC 0xf
3534 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_LSB 16
3536 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_MSB 19
3538 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_WIDTH 4
3540 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_SET_MSK 0x000f0000
3542 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_CLR_MSK 0xfff0ffff
3544 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_RESET 0x0
3546 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_GET(value) (((value) & 0x000f0000) >> 16)
3548 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_SET(value) (((value) << 16) & 0x000f0000)
3585 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_NONCACHE_NONBUFF 0x0
3590 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_BUFF 0x1
3595 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_NONALLOC 0x2
3600 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_BUFF_NONALLOC 0x3
3605 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_RESERVED1 0x4
3610 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_RESERVED2 0x5
3615 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
3620 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_WRBACK_RDALLOC 0x7
3625 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_RESERVED3 0x8
3630 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_RESERVED4 0x9
3635 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
3640 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_WRBACK_WRALLOC 0xb
3645 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_RESERVED5 0xc
3650 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_RESERVED6 0xd
3655 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_WRTHRU_ALLOC 0xe
3660 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_WRBACK_ALLOC 0xf
3663 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_LSB 20
3665 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_MSB 23
3667 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_WIDTH 4
3669 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_SET_MSK 0x00f00000
3671 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_CLR_MSK 0xff0fffff
3673 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_RESET 0x0
3675 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_GET(value) (((value) & 0x00f00000) >> 20)
3677 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_SET(value) (((value) << 20) & 0x00f00000)
3719 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_E_SECURE_NORMAL 0x0
3725 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_E_SECURE_PRIVILEGED 0x1
3731 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_E_NONSECURE_NORMAL 0x2
3737 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_E_NONSECURE_PRIVILEGED 0x3
3740 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_LSB 24
3742 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_MSB 26
3744 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_WIDTH 3
3746 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_SET_MSK 0x07000000
3748 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_CLR_MSK 0xf8ffffff
3750 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_RESET 0x2
3752 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_GET(value) (((value) & 0x07000000) >> 24)
3754 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_SET(value) (((value) << 24) & 0x07000000)
3796 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_E_SECURE_NORMAL 0x0
3802 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_E_SECURE_PRIVILEGED 0x1
3808 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_E_NONSECURE_NORMAL 0x2
3814 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_E_NONSECURE_PRIVILEGED 0x3
3817 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_LSB 27
3819 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_MSB 29
3821 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_WIDTH 3
3823 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_SET_MSK 0x38000000
3825 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_CLR_MSK 0xc7ffffff
3827 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_RESET 0x2
3829 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_GET(value) (((value) & 0x38000000) >> 27)
3831 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_SET(value) (((value) << 27) & 0x38000000)
3854 #define ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN 0x0
3859 #define ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN 0x1
3862 #define ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS_LSB 30
3864 #define ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS_MSB 30
3866 #define ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS_WIDTH 1
3868 #define ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS_SET_MSK 0x40000000
3870 #define ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS_CLR_MSK 0xbfffffff
3872 #define ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS_RESET 0x0
3874 #define ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS_GET(value) (((value) & 0x40000000) >> 30)
3876 #define ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS_SET(value) (((value) << 30) & 0x40000000)
3887 #define ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE_LSB 31
3889 #define ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE_MSB 31
3891 #define ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE_WIDTH 1
3893 #define ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE_SET_MSK 0x80000000
3895 #define ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE_CLR_MSK 0x7fffffff
3897 #define ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE_RESET 0x0
3899 #define ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE_GET(value) (((value) & 0x80000000) >> 31)
3901 #define ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE_SET(value) (((value) << 31) & 0x80000000)
3903 #ifndef __ASSEMBLY__
3915 struct ALT_SYSMGR_CORE_EMAC1_s
3917 volatile uint32_t phy_intf_sel : 2;
3919 volatile uint32_t ptp_ref_sel : 1;
3921 volatile uint32_t app_clk_sel : 1;
3923 volatile uint32_t arcache : 4;
3924 volatile uint32_t awcache : 4;
3925 volatile uint32_t arprot : 3;
3926 volatile uint32_t awprot : 3;
3927 volatile uint32_t sbd_data_endianness : 1;
3928 volatile uint32_t axi_disable : 1;
3932 typedef struct ALT_SYSMGR_CORE_EMAC1_s ALT_SYSMGR_CORE_EMAC1_t;
3936 #define ALT_SYSMGR_CORE_EMAC1_RESET 0x12000003
3938 #define ALT_SYSMGR_CORE_EMAC1_OFST 0x48
3991 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_E_GMII_MII 0x0
3996 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_E_RGMII 0x1
4001 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_E_RMII 0x2
4006 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_E_RESET 0x3
4009 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_LSB 0
4011 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_MSB 1
4013 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_WIDTH 2
4015 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_SET_MSK 0x00000003
4017 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_CLR_MSK 0xfffffffc
4019 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_RESET 0x3
4021 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_GET(value) (((value) & 0x00000003) >> 0)
4023 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_SET(value) (((value) << 0) & 0x00000003)
4047 #define ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL_E_INTERNAL 0x0
4052 #define ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL_E_EXTERNAL 0x1
4055 #define ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL_LSB 8
4057 #define ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL_MSB 8
4059 #define ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL_WIDTH 1
4061 #define ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL_SET_MSK 0x00000100
4063 #define ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL_CLR_MSK 0xfffffeff
4065 #define ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL_RESET 0x0
4067 #define ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL_GET(value) (((value) & 0x00000100) >> 8)
4069 #define ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL_SET(value) (((value) << 8) & 0x00000100)
4092 #define ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL_E_L4_MP_CLK 0x0
4097 #define ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL_E_F2S_AP_CLK 0x1
4100 #define ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL_LSB 12
4102 #define ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL_MSB 12
4104 #define ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL_WIDTH 1
4106 #define ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL_SET_MSK 0x00001000
4108 #define ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL_CLR_MSK 0xffffefff
4110 #define ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL_RESET 0x0
4112 #define ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL_GET(value) (((value) & 0x00001000) >> 12)
4114 #define ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL_SET(value) (((value) << 12) & 0x00001000)
4151 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_NONCACHE_NONBUFF 0x0
4156 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_BUFF 0x1
4161 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_NONALLOC 0x2
4166 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_BUFF_NONALLOC 0x3
4171 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_RESERVED1 0x4
4176 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_RESERVED2 0x5
4181 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
4186 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_WRBACK_RDALLOC 0x7
4191 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_RESERVED3 0x8
4196 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_RESERVED4 0x9
4201 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
4206 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_WRBACK_WRALLOC 0xb
4211 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_RESERVED5 0xc
4216 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_RESERVED6 0xd
4221 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_WRTHRU_ALLOC 0xe
4226 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_WRBACK_ALLOC 0xf
4229 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_LSB 16
4231 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_MSB 19
4233 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_WIDTH 4
4235 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_SET_MSK 0x000f0000
4237 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_CLR_MSK 0xfff0ffff
4239 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_RESET 0x0
4241 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_GET(value) (((value) & 0x000f0000) >> 16)
4243 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_SET(value) (((value) << 16) & 0x000f0000)
4280 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_NONCACHE_NONBUFF 0x0
4285 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_BUFF 0x1
4290 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_NONALLOC 0x2
4295 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_BUFF_NONALLOC 0x3
4300 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_RESERVED1 0x4
4305 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_RESERVED2 0x5
4310 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
4315 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_WRBACK_RDALLOC 0x7
4320 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_RESERVED3 0x8
4325 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_RESERVED4 0x9
4330 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
4335 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_WRBACK_WRALLOC 0xb
4340 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_RESERVED5 0xc
4345 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_RESERVED6 0xd
4350 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_WRTHRU_ALLOC 0xe
4355 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_WRBACK_ALLOC 0xf
4358 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_LSB 20
4360 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_MSB 23
4362 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_WIDTH 4
4364 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_SET_MSK 0x00f00000
4366 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_CLR_MSK 0xff0fffff
4368 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_RESET 0x0
4370 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_GET(value) (((value) & 0x00f00000) >> 20)
4372 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_SET(value) (((value) << 20) & 0x00f00000)
4414 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_E_SECURE_NORMAL 0x0
4420 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_E_SECURE_PRIVILEGED 0x1
4426 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_E_NONSECURE_NORMAL 0x2
4432 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_E_NONSECURE_PRIVILEGED 0x3
4435 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_LSB 24
4437 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_MSB 26
4439 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_WIDTH 3
4441 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_SET_MSK 0x07000000
4443 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_CLR_MSK 0xf8ffffff
4445 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_RESET 0x2
4447 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_GET(value) (((value) & 0x07000000) >> 24)
4449 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_SET(value) (((value) << 24) & 0x07000000)
4491 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_E_SECURE_NORMAL 0x0
4497 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_E_SECURE_PRIVILEGED 0x1
4503 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_E_NONSECURE_NORMAL 0x2
4509 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_E_NONSECURE_PRIVILEGED 0x3
4512 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_LSB 27
4514 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_MSB 29
4516 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_WIDTH 3
4518 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_SET_MSK 0x38000000
4520 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_CLR_MSK 0xc7ffffff
4522 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_RESET 0x2
4524 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_GET(value) (((value) & 0x38000000) >> 27)
4526 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_SET(value) (((value) << 27) & 0x38000000)
4549 #define ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN 0x0
4554 #define ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN 0x1
4557 #define ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS_LSB 30
4559 #define ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS_MSB 30
4561 #define ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS_WIDTH 1
4563 #define ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS_SET_MSK 0x40000000
4565 #define ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS_CLR_MSK 0xbfffffff
4567 #define ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS_RESET 0x0
4569 #define ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS_GET(value) (((value) & 0x40000000) >> 30)
4571 #define ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS_SET(value) (((value) << 30) & 0x40000000)
4582 #define ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE_LSB 31
4584 #define ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE_MSB 31
4586 #define ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE_WIDTH 1
4588 #define ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE_SET_MSK 0x80000000
4590 #define ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE_CLR_MSK 0x7fffffff
4592 #define ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE_RESET 0x0
4594 #define ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE_GET(value) (((value) & 0x80000000) >> 31)
4596 #define ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE_SET(value) (((value) << 31) & 0x80000000)
4598 #ifndef __ASSEMBLY__
4610 struct ALT_SYSMGR_CORE_EMAC2_s
4612 volatile uint32_t phy_intf_sel : 2;
4614 volatile uint32_t ptp_ref_sel : 1;
4616 volatile uint32_t app_clk_sel : 1;
4618 volatile uint32_t arcache : 4;
4619 volatile uint32_t awcache : 4;
4620 volatile uint32_t arprot : 3;
4621 volatile uint32_t awprot : 3;
4622 volatile uint32_t sbd_data_endianness : 1;
4623 volatile uint32_t axi_disable : 1;
4627 typedef struct ALT_SYSMGR_CORE_EMAC2_s ALT_SYSMGR_CORE_EMAC2_t;
4631 #define ALT_SYSMGR_CORE_EMAC2_RESET 0x12000003
4633 #define ALT_SYSMGR_CORE_EMAC2_OFST 0x4c
4663 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN_LSB 0
4665 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN_MSB 1
4667 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN_WIDTH 2
4669 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN_SET_MSK 0x00000003
4671 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN_CLR_MSK 0xfffffffc
4673 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN_RESET 0x3
4675 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN_GET(value) (((value) & 0x00000003) >> 0)
4677 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN_SET(value) (((value) << 0) & 0x00000003)
4688 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN_LSB 4
4690 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN_MSB 5
4692 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN_WIDTH 2
4694 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN_SET_MSK 0x00000030
4696 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN_CLR_MSK 0xffffffcf
4698 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN_RESET 0x3
4700 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN_GET(value) (((value) & 0x00000030) >> 4)
4702 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN_SET(value) (((value) << 4) & 0x00000030)
4713 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARSID_LSB 8
4715 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARSID_MSB 17
4717 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARSID_WIDTH 10
4719 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARSID_SET_MSK 0x0003ff00
4721 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARSID_CLR_MSK 0xfffc00ff
4723 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARSID_RESET 0x0
4725 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARSID_GET(value) (((value) & 0x0003ff00) >> 8)
4727 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARSID_SET(value) (((value) << 8) & 0x0003ff00)
4738 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWSID_LSB 20
4740 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWSID_MSB 29
4742 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWSID_WIDTH 10
4744 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWSID_SET_MSK 0x3ff00000
4746 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWSID_CLR_MSK 0xc00fffff
4748 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWSID_RESET 0x0
4750 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWSID_GET(value) (((value) & 0x3ff00000) >> 20)
4752 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWSID_SET(value) (((value) << 20) & 0x3ff00000)
4754 #ifndef __ASSEMBLY__
4766 struct ALT_SYSMGR_CORE_EMAC0_ACE_s
4768 volatile uint32_t ardomain : 2;
4770 volatile uint32_t awdomain : 2;
4772 volatile uint32_t arsid : 10;
4774 volatile uint32_t awsid : 10;
4779 typedef struct ALT_SYSMGR_CORE_EMAC0_ACE_s ALT_SYSMGR_CORE_EMAC0_ACE_t;
4783 #define ALT_SYSMGR_CORE_EMAC0_ACE_RESET 0x00000033
4785 #define ALT_SYSMGR_CORE_EMAC0_ACE_OFST 0x50
4815 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN_LSB 0
4817 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN_MSB 1
4819 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN_WIDTH 2
4821 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN_SET_MSK 0x00000003
4823 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN_CLR_MSK 0xfffffffc
4825 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN_RESET 0x3
4827 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN_GET(value) (((value) & 0x00000003) >> 0)
4829 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN_SET(value) (((value) << 0) & 0x00000003)
4840 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN_LSB 4
4842 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN_MSB 5
4844 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN_WIDTH 2
4846 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN_SET_MSK 0x00000030
4848 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN_CLR_MSK 0xffffffcf
4850 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN_RESET 0x3
4852 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN_GET(value) (((value) & 0x00000030) >> 4)
4854 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN_SET(value) (((value) << 4) & 0x00000030)
4865 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARSID_LSB 8
4867 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARSID_MSB 17
4869 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARSID_WIDTH 10
4871 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARSID_SET_MSK 0x0003ff00
4873 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARSID_CLR_MSK 0xfffc00ff
4875 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARSID_RESET 0x0
4877 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARSID_GET(value) (((value) & 0x0003ff00) >> 8)
4879 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARSID_SET(value) (((value) << 8) & 0x0003ff00)
4890 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWSID_LSB 20
4892 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWSID_MSB 29
4894 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWSID_WIDTH 10
4896 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWSID_SET_MSK 0x3ff00000
4898 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWSID_CLR_MSK 0xc00fffff
4900 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWSID_RESET 0x0
4902 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWSID_GET(value) (((value) & 0x3ff00000) >> 20)
4904 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWSID_SET(value) (((value) << 20) & 0x3ff00000)
4906 #ifndef __ASSEMBLY__
4918 struct ALT_SYSMGR_CORE_EMAC1_ACE_s
4920 volatile uint32_t ardomain : 2;
4922 volatile uint32_t awdomain : 2;
4924 volatile uint32_t arsid : 10;
4926 volatile uint32_t awsid : 10;
4931 typedef struct ALT_SYSMGR_CORE_EMAC1_ACE_s ALT_SYSMGR_CORE_EMAC1_ACE_t;
4935 #define ALT_SYSMGR_CORE_EMAC1_ACE_RESET 0x00000033
4937 #define ALT_SYSMGR_CORE_EMAC1_ACE_OFST 0x54
4967 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN_LSB 0
4969 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN_MSB 1
4971 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN_WIDTH 2
4973 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN_SET_MSK 0x00000003
4975 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN_CLR_MSK 0xfffffffc
4977 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN_RESET 0x3
4979 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN_GET(value) (((value) & 0x00000003) >> 0)
4981 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN_SET(value) (((value) << 0) & 0x00000003)
4992 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN_LSB 4
4994 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN_MSB 5
4996 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN_WIDTH 2
4998 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN_SET_MSK 0x00000030
5000 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN_CLR_MSK 0xffffffcf
5002 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN_RESET 0x3
5004 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN_GET(value) (((value) & 0x00000030) >> 4)
5006 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN_SET(value) (((value) << 4) & 0x00000030)
5017 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARSID_LSB 8
5019 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARSID_MSB 17
5021 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARSID_WIDTH 10
5023 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARSID_SET_MSK 0x0003ff00
5025 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARSID_CLR_MSK 0xfffc00ff
5027 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARSID_RESET 0x0
5029 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARSID_GET(value) (((value) & 0x0003ff00) >> 8)
5031 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARSID_SET(value) (((value) << 8) & 0x0003ff00)
5042 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWSID_LSB 20
5044 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWSID_MSB 29
5046 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWSID_WIDTH 10
5048 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWSID_SET_MSK 0x3ff00000
5050 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWSID_CLR_MSK 0xc00fffff
5052 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWSID_RESET 0x0
5054 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWSID_GET(value) (((value) & 0x3ff00000) >> 20)
5056 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWSID_SET(value) (((value) << 20) & 0x3ff00000)
5058 #ifndef __ASSEMBLY__
5070 struct ALT_SYSMGR_CORE_EMAC2_ACE_s
5072 volatile uint32_t ardomain : 2;
5074 volatile uint32_t awdomain : 2;
5076 volatile uint32_t arsid : 10;
5078 volatile uint32_t awsid : 10;
5083 typedef struct ALT_SYSMGR_CORE_EMAC2_ACE_s ALT_SYSMGR_CORE_EMAC2_ACE_t;
5087 #define ALT_SYSMGR_CORE_EMAC2_ACE_RESET 0x00000033
5089 #define ALT_SYSMGR_CORE_EMAC2_ACE_OFST 0x58
5115 #define ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER_LSB 0
5117 #define ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER_MSB 9
5119 #define ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER_WIDTH 10
5121 #define ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER_SET_MSK 0x000003ff
5123 #define ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER_CLR_MSK 0xfffffc00
5125 #define ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER_RESET 0x0
5127 #define ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER_GET(value) (((value) & 0x000003ff) >> 0)
5129 #define ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER_SET(value) (((value) << 0) & 0x000003ff)
5140 #define ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER_LSB 16
5142 #define ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER_MSB 25
5144 #define ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER_WIDTH 10
5146 #define ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER_SET_MSK 0x03ff0000
5148 #define ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER_CLR_MSK 0xfc00ffff
5150 #define ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER_RESET 0x0
5152 #define ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER_GET(value) (((value) & 0x03ff0000) >> 16)
5154 #define ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER_SET(value) (((value) << 16) & 0x03ff0000)
5156 #ifndef __ASSEMBLY__
5168 struct ALT_SYSMGR_CORE_NAND_AXUSER_s
5170 volatile uint32_t awuser : 10;
5172 volatile uint32_t aruser : 10;
5177 typedef struct ALT_SYSMGR_CORE_NAND_AXUSER_s ALT_SYSMGR_CORE_NAND_AXUSER_t;
5181 #define ALT_SYSMGR_CORE_NAND_AXUSER_RESET 0x00000000
5183 #define ALT_SYSMGR_CORE_NAND_AXUSER_OFST 0x5c
5227 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN_E_DISABLE 0x0
5232 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN_E_ENABLE 0x1
5235 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN_LSB 0
5237 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN_MSB 0
5239 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN_WIDTH 1
5241 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN_SET_MSK 0x00000001
5243 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN_CLR_MSK 0xfffffffe
5245 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN_RESET 0x0
5247 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN_GET(value) (((value) & 0x00000001) >> 0)
5249 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN_SET(value) (((value) << 0) & 0x00000001)
5270 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT_E_DISABLE 0x0
5275 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT_E_ENABLE 0x1
5278 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT_LSB 4
5280 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT_MSB 4
5282 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT_WIDTH 1
5284 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT_SET_MSK 0x00000010
5286 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT_CLR_MSK 0xffffffef
5288 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT_RESET 0x1
5290 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT_GET(value) (((value) & 0x00000010) >> 4)
5292 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT_SET(value) (((value) << 4) & 0x00000010)
5314 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB_E_DISABLE 0x0
5319 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB_E_ENABLE 0x1
5322 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB_LSB 8
5324 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB_MSB 8
5326 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB_WIDTH 1
5328 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB_SET_MSK 0x00000100
5330 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB_CLR_MSK 0xfffffeff
5332 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB_RESET 0x1
5334 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB_GET(value) (((value) & 0x00000100) >> 8)
5336 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB_SET(value) (((value) << 8) & 0x00000100)
5358 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT_E_DISABLE 0x0
5363 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT_E_ENABLE 0x1
5366 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT_LSB 16
5368 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT_MSB 16
5370 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT_WIDTH 1
5372 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT_SET_MSK 0x00010000
5374 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT_CLR_MSK 0xfffeffff
5376 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT_RESET 0x1
5378 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT_GET(value) (((value) & 0x00010000) >> 16)
5380 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT_SET(value) (((value) << 16) & 0x00010000)
5403 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER_E_DISABLE 0x0
5408 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER_E_ENABLE 0x1
5411 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER_LSB 24
5413 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER_MSB 24
5415 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER_WIDTH 1
5417 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER_SET_MSK 0x01000000
5419 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER_CLR_MSK 0xfeffffff
5421 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER_RESET 0x1
5423 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER_GET(value) (((value) & 0x01000000) >> 24)
5425 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER_SET(value) (((value) << 24) & 0x01000000)
5427 #ifndef __ASSEMBLY__
5439 struct ALT_SYSMGR_CORE_FPGAINTF_EN_1_s
5441 volatile uint32_t tracein : 1;
5443 volatile uint32_t traceout : 1;
5445 volatile uint32_t dbgapb : 1;
5447 volatile uint32_t stmevent : 1;
5449 volatile uint32_t ctmtrigger : 1;
5454 typedef struct ALT_SYSMGR_CORE_FPGAINTF_EN_1_s ALT_SYSMGR_CORE_FPGAINTF_EN_1_t;
5458 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_RESET 0x01010110
5460 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_OFST 0x68
5504 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND_E_DISABLE 0x0
5509 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND_E_ENABLE 0x1
5512 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND_LSB 4
5514 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND_MSB 4
5516 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND_WIDTH 1
5518 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND_SET_MSK 0x00000010
5520 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND_CLR_MSK 0xffffffef
5522 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND_RESET 0x0
5524 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND_GET(value) (((value) & 0x00000010) >> 4)
5526 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND_SET(value) (((value) << 4) & 0x00000010)
5548 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC_E_DISABLE 0x0
5553 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC_E_ENABLE 0x1
5556 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC_LSB 8
5558 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC_MSB 8
5560 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC_WIDTH 1
5562 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC_SET_MSK 0x00000100
5564 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC_CLR_MSK 0xfffffeff
5566 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC_RESET 0x0
5568 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC_GET(value) (((value) & 0x00000100) >> 8)
5570 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC_SET(value) (((value) << 8) & 0x00000100)
5594 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0_E_DISABLE 0x0
5599 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0_E_ENABLE 0x1
5602 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0_LSB 16
5604 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0_MSB 16
5606 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0_WIDTH 1
5608 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0_SET_MSK 0x00010000
5610 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0_CLR_MSK 0xfffeffff
5612 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0_RESET 0x0
5614 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0_GET(value) (((value) & 0x00010000) >> 16)
5616 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0_SET(value) (((value) << 16) & 0x00010000)
5640 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1_E_DISABLE 0x0
5645 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1_E_ENABLE 0x1
5648 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1_LSB 24
5650 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1_MSB 24
5652 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1_WIDTH 1
5654 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1_SET_MSK 0x01000000
5656 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1_CLR_MSK 0xfeffffff
5658 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1_RESET 0x0
5660 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1_GET(value) (((value) & 0x01000000) >> 24)
5662 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1_SET(value) (((value) << 24) & 0x01000000)
5664 #ifndef __ASSEMBLY__
5676 struct ALT_SYSMGR_CORE_FPGAINTF_EN_2_s
5679 volatile uint32_t nand : 1;
5681 volatile uint32_t sdmmc : 1;
5683 volatile uint32_t spim_0 : 1;
5685 volatile uint32_t spim_1 : 1;
5690 typedef struct ALT_SYSMGR_CORE_FPGAINTF_EN_2_s ALT_SYSMGR_CORE_FPGAINTF_EN_2_t;
5694 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_RESET 0x00000000
5696 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_OFST 0x6c
5745 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_E_DISABLE 0x0
5750 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_E_ENABLE 0x1
5753 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_LSB 0
5755 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_MSB 0
5757 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_WIDTH 1
5759 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SET_MSK 0x00000001
5761 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_CLR_MSK 0xfffffffe
5763 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_RESET 0x0
5765 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_GET(value) (((value) & 0x00000001) >> 0)
5767 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SET(value) (((value) << 0) & 0x00000001)
5788 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH_E_DISABLE 0x0
5793 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH_E_ENABLE 0x1
5796 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH_LSB 4
5798 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH_MSB 4
5800 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH_WIDTH 1
5802 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH_SET_MSK 0x00000010
5804 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH_CLR_MSK 0xffffffef
5806 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH_RESET 0x0
5808 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH_GET(value) (((value) & 0x00000010) >> 4)
5810 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH_SET(value) (((value) << 4) & 0x00000010)
5834 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_E_DISABLE 0x0
5839 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_E_ENABLE 0x1
5842 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_LSB 8
5844 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_MSB 8
5846 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_WIDTH 1
5848 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SET_MSK 0x00000100
5850 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_CLR_MSK 0xfffffeff
5852 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_RESET 0x0
5854 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_GET(value) (((value) & 0x00000100) >> 8)
5856 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SET(value) (((value) << 8) & 0x00000100)
5877 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH_E_DISABLE 0x0
5882 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH_E_ENABLE 0x1
5885 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH_LSB 12
5887 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH_MSB 12
5889 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH_WIDTH 1
5891 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH_SET_MSK 0x00001000
5893 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH_CLR_MSK 0xffffefff
5895 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH_RESET 0x0
5897 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH_GET(value) (((value) & 0x00001000) >> 12)
5899 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH_SET(value) (((value) << 12) & 0x00001000)
5923 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_E_DISABLE 0x0
5928 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_E_ENABLE 0x1
5931 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_LSB 16
5933 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_MSB 16
5935 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_WIDTH 1
5937 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SET_MSK 0x00010000
5939 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_CLR_MSK 0xfffeffff
5941 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_RESET 0x0
5943 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_GET(value) (((value) & 0x00010000) >> 16)
5945 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SET(value) (((value) << 16) & 0x00010000)
5966 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH_E_DISABLE 0x0
5971 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH_E_ENABLE 0x1
5974 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH_LSB 20
5976 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH_MSB 20
5978 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH_WIDTH 1
5980 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH_SET_MSK 0x00100000
5982 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH_CLR_MSK 0xffefffff
5984 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH_RESET 0x0
5986 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH_GET(value) (((value) & 0x00100000) >> 20)
5988 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH_SET(value) (((value) << 20) & 0x00100000)
5990 #ifndef __ASSEMBLY__
6002 struct ALT_SYSMGR_CORE_FPGAINTF_EN_3_s
6004 volatile uint32_t emac_0 : 1;
6006 volatile uint32_t emac_0_switch : 1;
6008 volatile uint32_t emac_1 : 1;
6010 volatile uint32_t emac_1_switch : 1;
6012 volatile uint32_t emac_2 : 1;
6014 volatile uint32_t emac_2_switch : 1;
6019 typedef struct ALT_SYSMGR_CORE_FPGAINTF_EN_3_s ALT_SYSMGR_CORE_FPGAINTF_EN_3_t;
6023 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_RESET 0x00000000
6025 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_OFST 0x70
6053 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER_LSB 0
6055 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER_MSB 9
6057 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER_WIDTH 10
6059 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER_SET_MSK 0x000003ff
6061 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER_CLR_MSK 0xfffffc00
6063 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER_RESET 0x0
6065 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER_GET(value) (((value) & 0x000003ff) >> 0)
6067 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER_SET(value) (((value) << 0) & 0x000003ff)
6078 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN_LSB 12
6080 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN_MSB 13
6082 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN_WIDTH 2
6084 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN_SET_MSK 0x00003000
6086 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN_CLR_MSK 0xffffcfff
6088 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN_RESET 0x3
6090 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN_GET(value) (((value) & 0x00003000) >> 12)
6092 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN_SET(value) (((value) << 12) & 0x00003000)
6103 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN_LSB 14
6105 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN_MSB 15
6107 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN_WIDTH 2
6109 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN_SET_MSK 0x0000c000
6111 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN_CLR_MSK 0xffff3fff
6113 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN_RESET 0x3
6115 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN_GET(value) (((value) & 0x0000c000) >> 14)
6117 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN_SET(value) (((value) << 14) & 0x0000c000)
6128 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER_LSB 16
6130 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER_MSB 25
6132 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER_WIDTH 10
6134 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER_SET_MSK 0x03ff0000
6136 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER_CLR_MSK 0xfc00ffff
6138 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER_RESET 0x0
6140 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER_GET(value) (((value) & 0x03ff0000) >> 16)
6142 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER_SET(value) (((value) << 16) & 0x03ff0000)
6144 #ifndef __ASSEMBLY__
6156 struct ALT_SYSMGR_CORE_DMA_L3MASTER_s
6158 volatile uint32_t awuser : 10;
6160 volatile uint32_t awdomain : 2;
6161 volatile uint32_t ardomain : 2;
6162 volatile uint32_t aruser : 10;
6167 typedef struct ALT_SYSMGR_CORE_DMA_L3MASTER_s ALT_SYSMGR_CORE_DMA_L3MASTER_t;
6171 #define ALT_SYSMGR_CORE_DMA_L3MASTER_RESET 0x0000f000
6173 #define ALT_SYSMGR_CORE_DMA_L3MASTER_OFST 0x74
6201 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER_LSB 0
6203 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER_MSB 9
6205 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER_WIDTH 10
6207 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER_SET_MSK 0x000003ff
6209 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER_CLR_MSK 0xfffffc00
6211 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER_RESET 0x0
6213 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER_GET(value) (((value) & 0x000003ff) >> 0)
6215 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER_SET(value) (((value) << 0) & 0x000003ff)
6226 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN_LSB 12
6228 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN_MSB 13
6230 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN_WIDTH 2
6232 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN_SET_MSK 0x00003000
6234 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN_CLR_MSK 0xffffcfff
6236 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN_RESET 0x3
6238 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN_GET(value) (((value) & 0x00003000) >> 12)
6240 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN_SET(value) (((value) << 12) & 0x00003000)
6251 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN_LSB 14
6253 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN_MSB 15
6255 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN_WIDTH 2
6257 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN_SET_MSK 0x0000c000
6259 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN_CLR_MSK 0xffff3fff
6261 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN_RESET 0x3
6263 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN_GET(value) (((value) & 0x0000c000) >> 14)
6265 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN_SET(value) (((value) << 14) & 0x0000c000)
6276 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER_LSB 16
6278 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER_MSB 25
6280 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER_WIDTH 10
6282 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER_SET_MSK 0x03ff0000
6284 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER_CLR_MSK 0xfc00ffff
6286 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER_RESET 0x0
6288 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER_GET(value) (((value) & 0x03ff0000) >> 16)
6290 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER_SET(value) (((value) << 16) & 0x03ff0000)
6292 #ifndef __ASSEMBLY__
6304 struct ALT_SYSMGR_CORE_ETR_L3MASTER_s
6306 volatile uint32_t awuser : 10;
6308 volatile uint32_t awdomain : 2;
6309 volatile uint32_t ardomain : 2;
6310 volatile uint32_t aruser : 10;
6315 typedef struct ALT_SYSMGR_CORE_ETR_L3MASTER_s ALT_SYSMGR_CORE_ETR_L3MASTER_t;
6319 #define ALT_SYSMGR_CORE_ETR_L3MASTER_RESET 0x0000f000
6321 #define ALT_SYSMGR_CORE_ETR_L3MASTER_OFST 0x78
6347 #define ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL_LSB 0
6349 #define ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL_MSB 0
6351 #define ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL_WIDTH 1
6353 #define ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL_SET_MSK 0x00000001
6355 #define ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL_CLR_MSK 0xfffffffe
6357 #define ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL_RESET 0x1
6359 #define ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL_GET(value) (((value) & 0x00000001) >> 0)
6361 #define ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL_SET(value) (((value) << 0) & 0x00000001)
6363 #ifndef __ASSEMBLY__
6375 struct ALT_SYSMGR_CORE_SEC_CTRL_SLT_s
6377 const volatile uint32_t val : 1;
6382 typedef struct ALT_SYSMGR_CORE_SEC_CTRL_SLT_s ALT_SYSMGR_CORE_SEC_CTRL_SLT_t;
6386 #define ALT_SYSMGR_CORE_SEC_CTRL_SLT_RESET 0x00000001
6388 #define ALT_SYSMGR_CORE_SEC_CTRL_SLT_OFST 0x80
6412 #define ALT_SYSMGR_CORE_OSC_TRIM_VAL_LSB 0
6414 #define ALT_SYSMGR_CORE_OSC_TRIM_VAL_MSB 7
6416 #define ALT_SYSMGR_CORE_OSC_TRIM_VAL_WIDTH 8
6418 #define ALT_SYSMGR_CORE_OSC_TRIM_VAL_SET_MSK 0x000000ff
6420 #define ALT_SYSMGR_CORE_OSC_TRIM_VAL_CLR_MSK 0xffffff00
6422 #define ALT_SYSMGR_CORE_OSC_TRIM_VAL_RESET 0x0
6424 #define ALT_SYSMGR_CORE_OSC_TRIM_VAL_GET(value) (((value) & 0x000000ff) >> 0)
6426 #define ALT_SYSMGR_CORE_OSC_TRIM_VAL_SET(value) (((value) << 0) & 0x000000ff)
6428 #ifndef __ASSEMBLY__
6440 struct ALT_SYSMGR_CORE_OSC_TRIM_s
6442 const volatile uint32_t val : 8;
6447 typedef struct ALT_SYSMGR_CORE_OSC_TRIM_s ALT_SYSMGR_CORE_OSC_TRIM_t;
6451 #define ALT_SYSMGR_CORE_OSC_TRIM_RESET 0x00000000
6453 #define ALT_SYSMGR_CORE_OSC_TRIM_OFST 0x84
6494 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM_LSB 1
6496 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM_MSB 1
6498 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM_WIDTH 1
6500 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM_SET_MSK 0x00000002
6502 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM_CLR_MSK 0xfffffffd
6504 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM_RESET 0x0
6506 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
6508 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM_SET(value) (((value) << 1) & 0x00000002)
6517 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0_LSB 2
6519 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0_MSB 2
6521 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0_WIDTH 1
6523 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0_SET_MSK 0x00000004
6525 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0_CLR_MSK 0xfffffffb
6527 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0_RESET 0x0
6529 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0_GET(value) (((value) & 0x00000004) >> 2)
6531 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0_SET(value) (((value) << 2) & 0x00000004)
6540 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1_LSB 3
6542 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1_MSB 3
6544 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1_WIDTH 1
6546 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1_SET_MSK 0x00000008
6548 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1_CLR_MSK 0xfffffff7
6550 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1_RESET 0x0
6552 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1_GET(value) (((value) & 0x00000008) >> 3)
6554 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1_SET(value) (((value) << 3) & 0x00000008)
6563 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX_LSB 4
6565 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX_MSB 4
6567 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX_WIDTH 1
6569 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX_SET_MSK 0x00000010
6571 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX_CLR_MSK 0xffffffef
6573 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX_RESET 0x0
6575 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
6577 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
6586 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX_LSB 5
6588 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX_MSB 5
6590 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX_WIDTH 1
6592 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX_SET_MSK 0x00000020
6594 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX_CLR_MSK 0xffffffdf
6596 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX_RESET 0x0
6598 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
6600 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
6609 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX_LSB 6
6611 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX_MSB 6
6613 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX_WIDTH 1
6615 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX_SET_MSK 0x00000040
6617 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX_CLR_MSK 0xffffffbf
6619 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX_RESET 0x0
6621 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
6623 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
6632 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX_LSB 7
6634 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX_MSB 7
6636 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX_WIDTH 1
6638 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX_SET_MSK 0x00000080
6640 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX_CLR_MSK 0xffffff7f
6642 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX_RESET 0x0
6644 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
6646 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
6655 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX_LSB 8
6657 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX_MSB 8
6659 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX_WIDTH 1
6661 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX_SET_MSK 0x00000100
6663 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX_CLR_MSK 0xfffffeff
6665 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX_RESET 0x0
6667 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
6669 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
6678 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX_LSB 9
6680 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX_MSB 9
6682 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX_WIDTH 1
6684 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX_SET_MSK 0x00000200
6686 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX_CLR_MSK 0xfffffdff
6688 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX_RESET 0x0
6690 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
6692 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
6701 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA_LSB 10
6703 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA_MSB 10
6705 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA_WIDTH 1
6707 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA_SET_MSK 0x00000400
6709 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA_CLR_MSK 0xfffffbff
6711 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA_RESET 0x0
6713 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA_GET(value) (((value) & 0x00000400) >> 10)
6715 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA_SET(value) (((value) << 10) & 0x00000400)
6724 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF_LSB 11
6726 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF_MSB 11
6728 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF_WIDTH 1
6730 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF_SET_MSK 0x00000800
6732 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF_CLR_MSK 0xfffff7ff
6734 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF_RESET 0x0
6736 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
6738 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
6747 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR_LSB 12
6749 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR_MSB 12
6751 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR_WIDTH 1
6753 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR_SET_MSK 0x00001000
6755 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR_CLR_MSK 0xffffefff
6757 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR_RESET 0x0
6759 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
6761 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
6770 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD_LSB 13
6772 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD_MSB 13
6774 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD_WIDTH 1
6776 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD_SET_MSK 0x00002000
6778 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD_CLR_MSK 0xffffdfff
6780 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD_RESET 0x0
6782 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
6784 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
6793 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA_LSB 14
6795 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA_MSB 14
6797 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA_WIDTH 1
6799 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA_SET_MSK 0x00004000
6801 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA_CLR_MSK 0xffffbfff
6803 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA_RESET 0x0
6805 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA_GET(value) (((value) & 0x00004000) >> 14)
6807 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA_SET(value) (((value) << 14) & 0x00004000)
6816 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB_LSB 15
6818 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB_MSB 15
6820 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB_WIDTH 1
6822 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB_SET_MSK 0x00008000
6824 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB_CLR_MSK 0xffff7fff
6826 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB_RESET 0x0
6828 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB_GET(value) (((value) & 0x00008000) >> 15)
6830 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB_SET(value) (((value) << 15) & 0x00008000)
6839 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0_LSB 16
6841 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0_MSB 16
6843 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0_WIDTH 1
6845 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0_SET_MSK 0x00010000
6847 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0_CLR_MSK 0xfffeffff
6849 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0_RESET 0x0
6851 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0_GET(value) (((value) & 0x00010000) >> 16)
6853 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0_SET(value) (((value) << 16) & 0x00010000)
6862 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1_LSB 17
6864 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1_MSB 17
6866 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1_WIDTH 1
6868 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1_SET_MSK 0x00020000
6870 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1_CLR_MSK 0xfffdffff
6872 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1_RESET 0x0
6874 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1_GET(value) (((value) & 0x00020000) >> 17)
6876 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1_SET(value) (((value) << 17) & 0x00020000)
6878 #ifndef __ASSEMBLY__
6890 struct ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_s
6893 volatile uint32_t ocram : 1;
6894 volatile uint32_t usb0 : 1;
6895 volatile uint32_t usb1 : 1;
6896 volatile uint32_t emac0_rx : 1;
6897 volatile uint32_t emac0_tx : 1;
6898 volatile uint32_t emac1_rx : 1;
6899 volatile uint32_t emac1_tx : 1;
6900 volatile uint32_t emac2_rx : 1;
6901 volatile uint32_t emac2_tx : 1;
6902 volatile uint32_t dma : 1;
6903 volatile uint32_t nand_buf : 1;
6904 volatile uint32_t nand_wr : 1;
6905 volatile uint32_t nand_rd : 1;
6906 volatile uint32_t sdmmca : 1;
6907 volatile uint32_t sdmmcb : 1;
6908 volatile uint32_t ddr0 : 1;
6909 volatile uint32_t ddr1 : 1;
6914 typedef struct ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_s ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_t;
6918 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_RESET 0x00000000
6920 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OFST 0x90
6961 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM_LSB 1
6963 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM_MSB 1
6965 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM_WIDTH 1
6967 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM_SET_MSK 0x00000002
6969 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM_CLR_MSK 0xfffffffd
6971 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM_RESET 0x0
6973 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
6975 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM_SET(value) (((value) << 1) & 0x00000002)
6984 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0_LSB 2
6986 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0_MSB 2
6988 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0_WIDTH 1
6990 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0_SET_MSK 0x00000004
6992 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0_CLR_MSK 0xfffffffb
6994 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0_RESET 0x0
6996 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0_GET(value) (((value) & 0x00000004) >> 2)
6998 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0_SET(value) (((value) << 2) & 0x00000004)
7007 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1_LSB 3
7009 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1_MSB 3
7011 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1_WIDTH 1
7013 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1_SET_MSK 0x00000008
7015 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1_CLR_MSK 0xfffffff7
7017 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1_RESET 0x0
7019 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1_GET(value) (((value) & 0x00000008) >> 3)
7021 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1_SET(value) (((value) << 3) & 0x00000008)
7030 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX_LSB 4
7032 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX_MSB 4
7034 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX_WIDTH 1
7036 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX_SET_MSK 0x00000010
7038 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX_CLR_MSK 0xffffffef
7040 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX_RESET 0x0
7042 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
7044 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
7053 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX_LSB 5
7055 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX_MSB 5
7057 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX_WIDTH 1
7059 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX_SET_MSK 0x00000020
7061 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX_CLR_MSK 0xffffffdf
7063 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX_RESET 0x0
7065 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
7067 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
7076 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX_LSB 6
7078 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX_MSB 6
7080 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX_WIDTH 1
7082 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX_SET_MSK 0x00000040
7084 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX_CLR_MSK 0xffffffbf
7086 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX_RESET 0x0
7088 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
7090 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
7099 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX_LSB 7
7101 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX_MSB 7
7103 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX_WIDTH 1
7105 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX_SET_MSK 0x00000080
7107 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX_CLR_MSK 0xffffff7f
7109 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX_RESET 0x0
7111 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
7113 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
7122 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX_LSB 8
7124 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX_MSB 8
7126 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX_WIDTH 1
7128 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX_SET_MSK 0x00000100
7130 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX_CLR_MSK 0xfffffeff
7132 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX_RESET 0x0
7134 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
7136 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
7145 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX_LSB 9
7147 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX_MSB 9
7149 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX_WIDTH 1
7151 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX_SET_MSK 0x00000200
7153 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX_CLR_MSK 0xfffffdff
7155 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX_RESET 0x0
7157 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
7159 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
7168 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA_LSB 10
7170 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA_MSB 10
7172 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA_WIDTH 1
7174 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA_SET_MSK 0x00000400
7176 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA_CLR_MSK 0xfffffbff
7178 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA_RESET 0x0
7180 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA_GET(value) (((value) & 0x00000400) >> 10)
7182 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA_SET(value) (((value) << 10) & 0x00000400)
7191 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF_LSB 11
7193 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF_MSB 11
7195 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF_WIDTH 1
7197 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF_SET_MSK 0x00000800
7199 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF_CLR_MSK 0xfffff7ff
7201 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF_RESET 0x0
7203 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
7205 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
7214 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR_LSB 12
7216 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR_MSB 12
7218 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR_WIDTH 1
7220 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR_SET_MSK 0x00001000
7222 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR_CLR_MSK 0xffffefff
7224 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR_RESET 0x0
7226 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
7228 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
7237 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD_LSB 13
7239 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD_MSB 13
7241 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD_WIDTH 1
7243 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD_SET_MSK 0x00002000
7245 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD_CLR_MSK 0xffffdfff
7247 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD_RESET 0x0
7249 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
7251 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
7260 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA_LSB 14
7262 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA_MSB 14
7264 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA_WIDTH 1
7266 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA_SET_MSK 0x00004000
7268 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA_CLR_MSK 0xffffbfff
7270 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA_RESET 0x0
7272 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA_GET(value) (((value) & 0x00004000) >> 14)
7274 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA_SET(value) (((value) << 14) & 0x00004000)
7283 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB_LSB 15
7285 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB_MSB 15
7287 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB_WIDTH 1
7289 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB_SET_MSK 0x00008000
7291 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB_CLR_MSK 0xffff7fff
7293 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB_RESET 0x0
7295 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB_GET(value) (((value) & 0x00008000) >> 15)
7297 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB_SET(value) (((value) << 15) & 0x00008000)
7306 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0_LSB 16
7308 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0_MSB 16
7310 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0_WIDTH 1
7312 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0_SET_MSK 0x00010000
7314 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0_CLR_MSK 0xfffeffff
7316 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0_RESET 0x0
7318 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0_GET(value) (((value) & 0x00010000) >> 16)
7320 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0_SET(value) (((value) << 16) & 0x00010000)
7329 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1_LSB 17
7331 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1_MSB 17
7333 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1_WIDTH 1
7335 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1_SET_MSK 0x00020000
7337 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1_CLR_MSK 0xfffdffff
7339 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1_RESET 0x0
7341 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1_GET(value) (((value) & 0x00020000) >> 17)
7343 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1_SET(value) (((value) << 17) & 0x00020000)
7345 #ifndef __ASSEMBLY__
7357 struct ALT_SYSMGR_CORE_ECC_INTMASK_SET_s
7360 volatile uint32_t ocram : 1;
7361 volatile uint32_t usb0 : 1;
7362 volatile uint32_t usb1 : 1;
7363 volatile uint32_t emac0_rx : 1;
7364 volatile uint32_t emac0_tx : 1;
7365 volatile uint32_t emac1_rx : 1;
7366 volatile uint32_t emac1_tx : 1;
7367 volatile uint32_t emac2_rx : 1;
7368 volatile uint32_t emac2_tx : 1;
7369 volatile uint32_t dma : 1;
7370 volatile uint32_t nand_buf : 1;
7371 volatile uint32_t nand_wr : 1;
7372 volatile uint32_t nand_rd : 1;
7373 volatile uint32_t sdmmca : 1;
7374 volatile uint32_t sdmmcb : 1;
7375 volatile uint32_t ddr0 : 1;
7376 volatile uint32_t ddr1 : 1;
7381 typedef struct ALT_SYSMGR_CORE_ECC_INTMASK_SET_s ALT_SYSMGR_CORE_ECC_INTMASK_SET_t;
7385 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_RESET 0x00000000
7387 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_OFST 0x94
7428 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM_LSB 1
7430 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM_MSB 1
7432 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM_WIDTH 1
7434 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM_SET_MSK 0x00000002
7436 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM_CLR_MSK 0xfffffffd
7438 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM_RESET 0x0
7440 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
7442 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM_SET(value) (((value) << 1) & 0x00000002)
7451 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0_LSB 2
7453 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0_MSB 2
7455 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0_WIDTH 1
7457 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0_SET_MSK 0x00000004
7459 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0_CLR_MSK 0xfffffffb
7461 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0_RESET 0x0
7463 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0_GET(value) (((value) & 0x00000004) >> 2)
7465 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0_SET(value) (((value) << 2) & 0x00000004)
7474 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1_LSB 3
7476 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1_MSB 3
7478 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1_WIDTH 1
7480 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1_SET_MSK 0x00000008
7482 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1_CLR_MSK 0xfffffff7
7484 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1_RESET 0x0
7486 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1_GET(value) (((value) & 0x00000008) >> 3)
7488 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1_SET(value) (((value) << 3) & 0x00000008)
7497 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX_LSB 4
7499 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX_MSB 4
7501 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX_WIDTH 1
7503 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX_SET_MSK 0x00000010
7505 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX_CLR_MSK 0xffffffef
7507 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX_RESET 0x0
7509 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
7511 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
7520 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX_LSB 5
7522 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX_MSB 5
7524 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX_WIDTH 1
7526 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX_SET_MSK 0x00000020
7528 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX_CLR_MSK 0xffffffdf
7530 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX_RESET 0x0
7532 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
7534 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
7543 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX_LSB 6
7545 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX_MSB 6
7547 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX_WIDTH 1
7549 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX_SET_MSK 0x00000040
7551 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX_CLR_MSK 0xffffffbf
7553 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX_RESET 0x0
7555 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
7557 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
7566 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX_LSB 7
7568 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX_MSB 7
7570 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX_WIDTH 1
7572 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX_SET_MSK 0x00000080
7574 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX_CLR_MSK 0xffffff7f
7576 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX_RESET 0x0
7578 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
7580 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
7589 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX_LSB 8
7591 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX_MSB 8
7593 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX_WIDTH 1
7595 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX_SET_MSK 0x00000100
7597 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX_CLR_MSK 0xfffffeff
7599 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX_RESET 0x0
7601 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
7603 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
7612 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX_LSB 9
7614 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX_MSB 9
7616 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX_WIDTH 1
7618 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX_SET_MSK 0x00000200
7620 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX_CLR_MSK 0xfffffdff
7622 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX_RESET 0x0
7624 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
7626 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
7635 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA_LSB 10
7637 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA_MSB 10
7639 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA_WIDTH 1
7641 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA_SET_MSK 0x00000400
7643 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA_CLR_MSK 0xfffffbff
7645 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA_RESET 0x0
7647 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA_GET(value) (((value) & 0x00000400) >> 10)
7649 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA_SET(value) (((value) << 10) & 0x00000400)
7658 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF_LSB 11
7660 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF_MSB 11
7662 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF_WIDTH 1
7664 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF_SET_MSK 0x00000800
7666 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF_CLR_MSK 0xfffff7ff
7668 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF_RESET 0x0
7670 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
7672 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
7681 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR_LSB 12
7683 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR_MSB 12
7685 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR_WIDTH 1
7687 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR_SET_MSK 0x00001000
7689 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR_CLR_MSK 0xffffefff
7691 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR_RESET 0x0
7693 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
7695 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
7704 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD_LSB 13
7706 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD_MSB 13
7708 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD_WIDTH 1
7710 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD_SET_MSK 0x00002000
7712 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD_CLR_MSK 0xffffdfff
7714 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD_RESET 0x0
7716 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
7718 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
7727 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA_LSB 14
7729 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA_MSB 14
7731 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA_WIDTH 1
7733 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA_SET_MSK 0x00004000
7735 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA_CLR_MSK 0xffffbfff
7737 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA_RESET 0x0
7739 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA_GET(value) (((value) & 0x00004000) >> 14)
7741 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA_SET(value) (((value) << 14) & 0x00004000)
7750 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB_LSB 15
7752 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB_MSB 15
7754 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB_WIDTH 1
7756 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB_SET_MSK 0x00008000
7758 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB_CLR_MSK 0xffff7fff
7760 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB_RESET 0x0
7762 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB_GET(value) (((value) & 0x00008000) >> 15)
7764 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB_SET(value) (((value) << 15) & 0x00008000)
7773 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0_LSB 16
7775 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0_MSB 16
7777 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0_WIDTH 1
7779 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0_SET_MSK 0x00010000
7781 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0_CLR_MSK 0xfffeffff
7783 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0_RESET 0x0
7785 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0_GET(value) (((value) & 0x00010000) >> 16)
7787 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0_SET(value) (((value) << 16) & 0x00010000)
7796 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1_LSB 17
7798 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1_MSB 17
7800 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1_WIDTH 1
7802 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1_SET_MSK 0x00020000
7804 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1_CLR_MSK 0xfffdffff
7806 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1_RESET 0x0
7808 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1_GET(value) (((value) & 0x00020000) >> 17)
7810 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1_SET(value) (((value) << 17) & 0x00020000)
7812 #ifndef __ASSEMBLY__
7824 struct ALT_SYSMGR_CORE_ECC_INTMASK_CLR_s
7827 volatile uint32_t ocram : 1;
7828 volatile uint32_t usb0 : 1;
7829 volatile uint32_t usb1 : 1;
7830 volatile uint32_t emac0_rx : 1;
7831 volatile uint32_t emac0_tx : 1;
7832 volatile uint32_t emac1_rx : 1;
7833 volatile uint32_t emac1_tx : 1;
7834 volatile uint32_t emac2_rx : 1;
7835 volatile uint32_t emac2_tx : 1;
7836 volatile uint32_t dma : 1;
7837 volatile uint32_t nand_buf : 1;
7838 volatile uint32_t nand_wr : 1;
7839 volatile uint32_t nand_rd : 1;
7840 volatile uint32_t sdmmca : 1;
7841 volatile uint32_t sdmmcb : 1;
7842 volatile uint32_t ddr0 : 1;
7843 volatile uint32_t ddr1 : 1;
7848 typedef struct ALT_SYSMGR_CORE_ECC_INTMASK_CLR_s ALT_SYSMGR_CORE_ECC_INTMASK_CLR_t;
7852 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_RESET 0x00000000
7854 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OFST 0x98
7895 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM_LSB 1
7897 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM_MSB 1
7899 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM_WIDTH 1
7901 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM_SET_MSK 0x00000002
7903 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM_CLR_MSK 0xfffffffd
7905 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM_RESET 0x0
7907 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
7909 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM_SET(value) (((value) << 1) & 0x00000002)
7918 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0_LSB 2
7920 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0_MSB 2
7922 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0_WIDTH 1
7924 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0_SET_MSK 0x00000004
7926 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0_CLR_MSK 0xfffffffb
7928 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0_RESET 0x0
7930 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0_GET(value) (((value) & 0x00000004) >> 2)
7932 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0_SET(value) (((value) << 2) & 0x00000004)
7941 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1_LSB 3
7943 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1_MSB 3
7945 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1_WIDTH 1
7947 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1_SET_MSK 0x00000008
7949 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1_CLR_MSK 0xfffffff7
7951 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1_RESET 0x0
7953 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1_GET(value) (((value) & 0x00000008) >> 3)
7955 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1_SET(value) (((value) << 3) & 0x00000008)
7964 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX_LSB 4
7966 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX_MSB 4
7968 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX_WIDTH 1
7970 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX_SET_MSK 0x00000010
7972 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX_CLR_MSK 0xffffffef
7974 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX_RESET 0x0
7976 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
7978 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
7987 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX_LSB 5
7989 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX_MSB 5
7991 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX_WIDTH 1
7993 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX_SET_MSK 0x00000020
7995 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX_CLR_MSK 0xffffffdf
7997 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX_RESET 0x0
7999 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
8001 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
8010 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX_LSB 6
8012 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX_MSB 6
8014 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX_WIDTH 1
8016 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX_SET_MSK 0x00000040
8018 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX_CLR_MSK 0xffffffbf
8020 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX_RESET 0x0
8022 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
8024 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
8033 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX_LSB 7
8035 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX_MSB 7
8037 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX_WIDTH 1
8039 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX_SET_MSK 0x00000080
8041 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX_CLR_MSK 0xffffff7f
8043 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX_RESET 0x0
8045 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
8047 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
8056 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX_LSB 8
8058 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX_MSB 8
8060 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX_WIDTH 1
8062 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX_SET_MSK 0x00000100
8064 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX_CLR_MSK 0xfffffeff
8066 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX_RESET 0x0
8068 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
8070 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
8079 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX_LSB 9
8081 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX_MSB 9
8083 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX_WIDTH 1
8085 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX_SET_MSK 0x00000200
8087 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX_CLR_MSK 0xfffffdff
8089 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX_RESET 0x0
8091 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
8093 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
8102 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA_LSB 10
8104 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA_MSB 10
8106 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA_WIDTH 1
8108 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA_SET_MSK 0x00000400
8110 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA_CLR_MSK 0xfffffbff
8112 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA_RESET 0x0
8114 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA_GET(value) (((value) & 0x00000400) >> 10)
8116 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA_SET(value) (((value) << 10) & 0x00000400)
8125 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF_LSB 11
8127 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF_MSB 11
8129 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF_WIDTH 1
8131 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF_SET_MSK 0x00000800
8133 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF_CLR_MSK 0xfffff7ff
8135 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF_RESET 0x0
8137 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
8139 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
8148 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR_LSB 12
8150 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR_MSB 12
8152 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR_WIDTH 1
8154 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR_SET_MSK 0x00001000
8156 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR_CLR_MSK 0xffffefff
8158 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR_RESET 0x0
8160 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
8162 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
8171 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD_LSB 13
8173 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD_MSB 13
8175 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD_WIDTH 1
8177 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD_SET_MSK 0x00002000
8179 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD_CLR_MSK 0xffffdfff
8181 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD_RESET 0x0
8183 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
8185 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
8194 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA_LSB 14
8196 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA_MSB 14
8198 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA_WIDTH 1
8200 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA_SET_MSK 0x00004000
8202 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA_CLR_MSK 0xffffbfff
8204 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA_RESET 0x0
8206 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA_GET(value) (((value) & 0x00004000) >> 14)
8208 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA_SET(value) (((value) << 14) & 0x00004000)
8217 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB_LSB 15
8219 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB_MSB 15
8221 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB_WIDTH 1
8223 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB_SET_MSK 0x00008000
8225 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB_CLR_MSK 0xffff7fff
8227 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB_RESET 0x0
8229 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB_GET(value) (((value) & 0x00008000) >> 15)
8231 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB_SET(value) (((value) << 15) & 0x00008000)
8240 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0_LSB 16
8242 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0_MSB 16
8244 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0_WIDTH 1
8246 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0_SET_MSK 0x00010000
8248 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0_CLR_MSK 0xfffeffff
8250 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0_RESET 0x0
8252 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0_GET(value) (((value) & 0x00010000) >> 16)
8254 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0_SET(value) (((value) << 16) & 0x00010000)
8263 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1_LSB 17
8265 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1_MSB 17
8267 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1_WIDTH 1
8269 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1_SET_MSK 0x00020000
8271 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1_CLR_MSK 0xfffdffff
8273 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1_RESET 0x0
8275 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1_GET(value) (((value) & 0x00020000) >> 17)
8277 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1_SET(value) (((value) << 17) & 0x00020000)
8279 #ifndef __ASSEMBLY__
8291 struct ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_s
8294 const volatile uint32_t ocram : 1;
8295 const volatile uint32_t usb0 : 1;
8296 const volatile uint32_t usb1 : 1;
8297 const volatile uint32_t emac0_rx : 1;
8298 const volatile uint32_t emac0_tx : 1;
8299 const volatile uint32_t emac1_rx : 1;
8300 const volatile uint32_t emac1_tx : 1;
8301 const volatile uint32_t emac2_rx : 1;
8302 const volatile uint32_t emac2_tx : 1;
8303 const volatile uint32_t dma : 1;
8304 const volatile uint32_t nand_buf : 1;
8305 const volatile uint32_t nand_wr : 1;
8306 const volatile uint32_t nand_rd : 1;
8307 const volatile uint32_t sdmmca : 1;
8308 const volatile uint32_t sdmmcb : 1;
8309 const volatile uint32_t ddr0 : 1;
8310 const volatile uint32_t ddr1 : 1;
8315 typedef struct ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_s ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_t;
8319 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_RESET 0x00000000
8321 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OFST 0x9c
8362 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM_LSB 1
8364 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM_MSB 1
8366 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM_WIDTH 1
8368 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM_SET_MSK 0x00000002
8370 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM_CLR_MSK 0xfffffffd
8372 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM_RESET 0x0
8374 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
8376 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM_SET(value) (((value) << 1) & 0x00000002)
8385 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0_LSB 2
8387 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0_MSB 2
8389 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0_WIDTH 1
8391 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0_SET_MSK 0x00000004
8393 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0_CLR_MSK 0xfffffffb
8395 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0_RESET 0x0
8397 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0_GET(value) (((value) & 0x00000004) >> 2)
8399 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0_SET(value) (((value) << 2) & 0x00000004)
8408 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1_LSB 3
8410 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1_MSB 3
8412 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1_WIDTH 1
8414 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1_SET_MSK 0x00000008
8416 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1_CLR_MSK 0xfffffff7
8418 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1_RESET 0x0
8420 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1_GET(value) (((value) & 0x00000008) >> 3)
8422 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1_SET(value) (((value) << 3) & 0x00000008)
8431 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX_LSB 4
8433 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX_MSB 4
8435 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX_WIDTH 1
8437 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX_SET_MSK 0x00000010
8439 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX_CLR_MSK 0xffffffef
8441 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX_RESET 0x0
8443 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
8445 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
8454 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX_LSB 5
8456 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX_MSB 5
8458 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX_WIDTH 1
8460 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX_SET_MSK 0x00000020
8462 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX_CLR_MSK 0xffffffdf
8464 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX_RESET 0x0
8466 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
8468 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
8477 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX_LSB 6
8479 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX_MSB 6
8481 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX_WIDTH 1
8483 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX_SET_MSK 0x00000040
8485 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX_CLR_MSK 0xffffffbf
8487 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX_RESET 0x0
8489 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
8491 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
8500 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX_LSB 7
8502 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX_MSB 7
8504 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX_WIDTH 1
8506 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX_SET_MSK 0x00000080
8508 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX_CLR_MSK 0xffffff7f
8510 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX_RESET 0x0
8512 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
8514 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
8523 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX_LSB 8
8525 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX_MSB 8
8527 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX_WIDTH 1
8529 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX_SET_MSK 0x00000100
8531 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX_CLR_MSK 0xfffffeff
8533 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX_RESET 0x0
8535 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
8537 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
8546 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX_LSB 9
8548 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX_MSB 9
8550 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX_WIDTH 1
8552 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX_SET_MSK 0x00000200
8554 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX_CLR_MSK 0xfffffdff
8556 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX_RESET 0x0
8558 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
8560 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
8569 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA_LSB 10
8571 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA_MSB 10
8573 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA_WIDTH 1
8575 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA_SET_MSK 0x00000400
8577 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA_CLR_MSK 0xfffffbff
8579 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA_RESET 0x0
8581 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA_GET(value) (((value) & 0x00000400) >> 10)
8583 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA_SET(value) (((value) << 10) & 0x00000400)
8592 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF_LSB 11
8594 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF_MSB 11
8596 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF_WIDTH 1
8598 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF_SET_MSK 0x00000800
8600 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF_CLR_MSK 0xfffff7ff
8602 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF_RESET 0x0
8604 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
8606 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
8615 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR_LSB 12
8617 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR_MSB 12
8619 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR_WIDTH 1
8621 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR_SET_MSK 0x00001000
8623 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR_CLR_MSK 0xffffefff
8625 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR_RESET 0x0
8627 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
8629 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
8638 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD_LSB 13
8640 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD_MSB 13
8642 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD_WIDTH 1
8644 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD_SET_MSK 0x00002000
8646 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD_CLR_MSK 0xffffdfff
8648 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD_RESET 0x0
8650 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
8652 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
8661 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA_LSB 14
8663 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA_MSB 14
8665 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA_WIDTH 1
8667 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA_SET_MSK 0x00004000
8669 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA_CLR_MSK 0xffffbfff
8671 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA_RESET 0x0
8673 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA_GET(value) (((value) & 0x00004000) >> 14)
8675 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA_SET(value) (((value) << 14) & 0x00004000)
8684 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB_LSB 15
8686 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB_MSB 15
8688 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB_WIDTH 1
8690 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB_SET_MSK 0x00008000
8692 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB_CLR_MSK 0xffff7fff
8694 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB_RESET 0x0
8696 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB_GET(value) (((value) & 0x00008000) >> 15)
8698 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB_SET(value) (((value) << 15) & 0x00008000)
8707 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0_LSB 16
8709 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0_MSB 16
8711 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0_WIDTH 1
8713 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0_SET_MSK 0x00010000
8715 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0_CLR_MSK 0xfffeffff
8717 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0_RESET 0x0
8719 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0_GET(value) (((value) & 0x00010000) >> 16)
8721 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0_SET(value) (((value) << 16) & 0x00010000)
8730 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1_LSB 17
8732 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1_MSB 17
8734 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1_WIDTH 1
8736 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1_SET_MSK 0x00020000
8738 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1_CLR_MSK 0xfffdffff
8740 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1_RESET 0x0
8742 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1_GET(value) (((value) & 0x00020000) >> 17)
8744 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1_SET(value) (((value) << 17) & 0x00020000)
8746 #ifndef __ASSEMBLY__
8758 struct ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_s
8761 const volatile uint32_t ocram : 1;
8762 const volatile uint32_t usb0 : 1;
8763 const volatile uint32_t usb1 : 1;
8764 const volatile uint32_t emac0_rx : 1;
8765 const volatile uint32_t emac0_tx : 1;
8766 const volatile uint32_t emac1_rx : 1;
8767 const volatile uint32_t emac1_tx : 1;
8768 const volatile uint32_t emac2_rx : 1;
8769 const volatile uint32_t emac2_tx : 1;
8770 const volatile uint32_t dma : 1;
8771 const volatile uint32_t nand_buf : 1;
8772 const volatile uint32_t nand_wr : 1;
8773 const volatile uint32_t nand_rd : 1;
8774 const volatile uint32_t sdmmca : 1;
8775 const volatile uint32_t sdmmcb : 1;
8776 const volatile uint32_t ddr0 : 1;
8777 const volatile uint32_t ddr1 : 1;
8782 typedef struct ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_s ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_t;
8786 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_RESET 0x00000000
8788 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OFST 0xa0
8816 #define ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE_LSB 0
8818 #define ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE_MSB 0
8820 #define ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE_WIDTH 1
8822 #define ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE_SET_MSK 0x00000001
8824 #define ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE_CLR_MSK 0xfffffffe
8826 #define ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE_RESET 0x0
8828 #define ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE_GET(value) (((value) & 0x00000001) >> 0)
8830 #define ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE_SET(value) (((value) << 0) & 0x00000001)
8832 #ifndef __ASSEMBLY__
8844 struct ALT_SYSMGR_CORE_NOC_ADDR_REMAP_s
8846 volatile uint32_t sdm2hps_be : 1;
8851 typedef struct ALT_SYSMGR_CORE_NOC_ADDR_REMAP_s ALT_SYSMGR_CORE_NOC_ADDR_REMAP_t;
8855 #define ALT_SYSMGR_CORE_NOC_ADDR_REMAP_RESET 0x00000000
8857 #define ALT_SYSMGR_CORE_NOC_ADDR_REMAP_OFST 0xb0
8889 #define ALT_SYSMGR_CORE_HMC_CLK_STATUS_LSB 0
8891 #define ALT_SYSMGR_CORE_HMC_CLK_STATUS_MSB 0
8893 #define ALT_SYSMGR_CORE_HMC_CLK_STATUS_WIDTH 1
8895 #define ALT_SYSMGR_CORE_HMC_CLK_STATUS_SET_MSK 0x00000001
8897 #define ALT_SYSMGR_CORE_HMC_CLK_STATUS_CLR_MSK 0xfffffffe
8899 #define ALT_SYSMGR_CORE_HMC_CLK_STATUS_RESET 0x0
8901 #define ALT_SYSMGR_CORE_HMC_CLK_STATUS_GET(value) (((value) & 0x00000001) >> 0)
8903 #define ALT_SYSMGR_CORE_HMC_CLK_STATUS_SET(value) (((value) << 0) & 0x00000001)
8914 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A_LSB 8
8916 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A_MSB 8
8918 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A_WIDTH 1
8920 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A_SET_MSK 0x00000100
8922 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A_CLR_MSK 0xfffffeff
8924 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A_RESET 0x0
8926 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A_GET(value) (((value) & 0x00000100) >> 8)
8928 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A_SET(value) (((value) << 8) & 0x00000100)
8939 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B_LSB 9
8941 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B_MSB 9
8943 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B_WIDTH 1
8945 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B_SET_MSK 0x00000200
8947 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B_CLR_MSK 0xfffffdff
8949 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B_RESET 0x0
8951 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B_GET(value) (((value) & 0x00000200) >> 9)
8953 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B_SET(value) (((value) << 9) & 0x00000200)
8964 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C_LSB 10
8966 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C_MSB 10
8968 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C_WIDTH 1
8970 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C_SET_MSK 0x00000400
8972 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C_CLR_MSK 0xfffffbff
8974 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C_RESET 0x0
8976 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C_GET(value) (((value) & 0x00000400) >> 10)
8978 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C_SET(value) (((value) << 10) & 0x00000400)
8989 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A_LSB 16
8991 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A_MSB 16
8993 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A_WIDTH 1
8995 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A_SET_MSK 0x00010000
8997 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A_CLR_MSK 0xfffeffff
8999 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A_RESET 0x0
9001 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A_GET(value) (((value) & 0x00010000) >> 16)
9003 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A_SET(value) (((value) << 16) & 0x00010000)
9014 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B_LSB 17
9016 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B_MSB 17
9018 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B_WIDTH 1
9020 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B_SET_MSK 0x00020000
9022 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B_CLR_MSK 0xfffdffff
9024 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B_RESET 0x0
9026 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B_GET(value) (((value) & 0x00020000) >> 17)
9028 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B_SET(value) (((value) << 17) & 0x00020000)
9039 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C_LSB 18
9041 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C_MSB 18
9043 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C_WIDTH 1
9045 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C_SET_MSK 0x00040000
9047 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C_CLR_MSK 0xfffbffff
9049 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C_RESET 0x0
9051 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C_GET(value) (((value) & 0x00040000) >> 18)
9053 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C_SET(value) (((value) << 18) & 0x00040000)
9055 #ifndef __ASSEMBLY__
9067 struct ALT_SYSMGR_CORE_HMC_CLK_s
9069 const volatile uint32_t status : 1;
9071 const volatile uint32_t io_pll_lock_a : 1;
9072 const volatile uint32_t io_pll_lock_b : 1;
9073 const volatile uint32_t io_pll_lock_c : 1;
9075 const volatile uint32_t io_cpa_lock_a : 1;
9076 const volatile uint32_t io_cpa_lock_b : 1;
9077 const volatile uint32_t io_cpa_lock_c : 1;
9082 typedef struct ALT_SYSMGR_CORE_HMC_CLK_s ALT_SYSMGR_CORE_HMC_CLK_t;
9086 #define ALT_SYSMGR_CORE_HMC_CLK_RESET 0x00000000
9088 #define ALT_SYSMGR_CORE_HMC_CLK_OFST 0xb4
9115 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A_LSB 0
9117 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A_MSB 0
9119 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A_WIDTH 1
9121 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A_SET_MSK 0x00000001
9123 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A_CLR_MSK 0xfffffffe
9125 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A_RESET 0x1
9127 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A_GET(value) (((value) & 0x00000001) >> 0)
9129 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A_SET(value) (((value) << 0) & 0x00000001)
9141 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B_LSB 1
9143 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B_MSB 1
9145 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B_WIDTH 1
9147 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B_SET_MSK 0x00000002
9149 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B_CLR_MSK 0xfffffffd
9151 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B_RESET 0x1
9153 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B_GET(value) (((value) & 0x00000002) >> 1)
9155 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B_SET(value) (((value) << 1) & 0x00000002)
9167 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C_LSB 2
9169 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C_MSB 2
9171 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C_WIDTH 1
9173 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C_SET_MSK 0x00000004
9175 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C_CLR_MSK 0xfffffffb
9177 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C_RESET 0x1
9179 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C_GET(value) (((value) & 0x00000004) >> 2)
9181 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C_SET(value) (((value) << 2) & 0x00000004)
9183 #ifndef __ASSEMBLY__
9195 struct ALT_SYSMGR_CORE_IO_PA_CTRL_s
9197 volatile uint32_t io_pa_reset_n_a : 1;
9198 volatile uint32_t io_pa_reset_n_b : 1;
9199 volatile uint32_t io_pa_reset_n_c : 1;
9204 typedef struct ALT_SYSMGR_CORE_IO_PA_CTRL_s ALT_SYSMGR_CORE_IO_PA_CTRL_t;
9208 #define ALT_SYSMGR_CORE_IO_PA_CTRL_RESET 0x00000007
9210 #define ALT_SYSMGR_CORE_IO_PA_CTRL_OFST 0xb8
9232 #define ALT_SYSMGR_CORE_NOC_TIMEOUT_EN_LSB 0
9234 #define ALT_SYSMGR_CORE_NOC_TIMEOUT_EN_MSB 0
9236 #define ALT_SYSMGR_CORE_NOC_TIMEOUT_EN_WIDTH 1
9238 #define ALT_SYSMGR_CORE_NOC_TIMEOUT_EN_SET_MSK 0x00000001
9240 #define ALT_SYSMGR_CORE_NOC_TIMEOUT_EN_CLR_MSK 0xfffffffe
9242 #define ALT_SYSMGR_CORE_NOC_TIMEOUT_EN_RESET 0x0
9244 #define ALT_SYSMGR_CORE_NOC_TIMEOUT_EN_GET(value) (((value) & 0x00000001) >> 0)
9246 #define ALT_SYSMGR_CORE_NOC_TIMEOUT_EN_SET(value) (((value) << 0) & 0x00000001)
9248 #ifndef __ASSEMBLY__
9260 struct ALT_SYSMGR_CORE_NOC_TIMEOUT_s
9262 volatile uint32_t en : 1;
9267 typedef struct ALT_SYSMGR_CORE_NOC_TIMEOUT_s ALT_SYSMGR_CORE_NOC_TIMEOUT_t;
9271 #define ALT_SYSMGR_CORE_NOC_TIMEOUT_RESET 0x00000000
9273 #define ALT_SYSMGR_CORE_NOC_TIMEOUT_OFST 0xc0
9297 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA_LSB 0
9299 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA_MSB 0
9301 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA_WIDTH 1
9303 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA_SET_MSK 0x00000001
9305 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA_CLR_MSK 0xfffffffe
9307 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA_RESET 0x0
9309 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA_GET(value) (((value) & 0x00000001) >> 0)
9311 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA_SET(value) (((value) << 0) & 0x00000001)
9320 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA_LSB 4
9322 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA_MSB 4
9324 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA_WIDTH 1
9326 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA_SET_MSK 0x00000010
9328 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA_CLR_MSK 0xffffffef
9330 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA_RESET 0x0
9332 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA_GET(value) (((value) & 0x00000010) >> 4)
9334 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA_SET(value) (((value) << 4) & 0x00000010)
9336 #ifndef __ASSEMBLY__
9348 struct ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_s
9350 volatile uint32_t soc2fpga : 1;
9352 volatile uint32_t lwsoc2fpga : 1;
9357 typedef struct ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_s ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_t;
9361 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_RESET 0x00000000
9363 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_OFST 0xc4
9387 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA_LSB 0
9389 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA_MSB 0
9391 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA_WIDTH 1
9393 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA_SET_MSK 0x00000001
9395 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA_CLR_MSK 0xfffffffe
9397 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA_RESET 0x0
9399 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA_GET(value) (((value) & 0x00000001) >> 0)
9401 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA_SET(value) (((value) << 0) & 0x00000001)
9410 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA_LSB 4
9412 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA_MSB 4
9414 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA_WIDTH 1
9416 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA_SET_MSK 0x00000010
9418 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA_CLR_MSK 0xffffffef
9420 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA_RESET 0x0
9422 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA_GET(value) (((value) & 0x00000010) >> 4)
9424 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA_SET(value) (((value) << 4) & 0x00000010)
9426 #ifndef __ASSEMBLY__
9438 struct ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_s
9440 volatile uint32_t soc2fpga : 1;
9442 volatile uint32_t lwsoc2fpga : 1;
9447 typedef struct ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_s ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_t;
9451 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_RESET 0x00000000
9453 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_OFST 0xc8
9483 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA_LSB 0
9485 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA_MSB 0
9487 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA_WIDTH 1
9489 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA_SET_MSK 0x00000001
9491 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA_CLR_MSK 0xfffffffe
9493 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA_RESET 0x0
9495 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA_GET(value) (((value) & 0x00000001) >> 0)
9497 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA_SET(value) (((value) << 0) & 0x00000001)
9506 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA_LSB 4
9508 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA_MSB 4
9510 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA_WIDTH 1
9512 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA_SET_MSK 0x00000010
9514 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA_CLR_MSK 0xffffffef
9516 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA_RESET 0x0
9518 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA_GET(value) (((value) & 0x00000010) >> 4)
9520 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA_SET(value) (((value) << 4) & 0x00000010)
9522 #ifndef __ASSEMBLY__
9534 struct ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_s
9536 volatile uint32_t soc2fpga : 1;
9538 volatile uint32_t lwsoc2fpga : 1;
9543 typedef struct ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_s ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_t;
9547 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_RESET 0x00000000
9549 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_OFST 0xcc
9574 #define ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA_LSB 0
9576 #define ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA_MSB 0
9578 #define ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA_WIDTH 1
9580 #define ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA_SET_MSK 0x00000001
9582 #define ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA_CLR_MSK 0xfffffffe
9584 #define ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA_RESET 0x1
9586 #define ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA_GET(value) (((value) & 0x00000001) >> 0)
9588 #define ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA_SET(value) (((value) << 0) & 0x00000001)
9597 #define ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA_LSB 4
9599 #define ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA_MSB 4
9601 #define ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA_WIDTH 1
9603 #define ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA_SET_MSK 0x00000010
9605 #define ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA_CLR_MSK 0xffffffef
9607 #define ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA_RESET 0x1
9609 #define ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA_GET(value) (((value) & 0x00000010) >> 4)
9611 #define ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA_SET(value) (((value) << 4) & 0x00000010)
9613 #ifndef __ASSEMBLY__
9625 struct ALT_SYSMGR_CORE_NOC_IDLEACK_s
9627 const volatile uint32_t soc2fpga : 1;
9629 const volatile uint32_t lwsoc2fpga : 1;
9634 typedef struct ALT_SYSMGR_CORE_NOC_IDLEACK_s ALT_SYSMGR_CORE_NOC_IDLEACK_t;
9638 #define ALT_SYSMGR_CORE_NOC_IDLEACK_RESET 0x00000011
9640 #define ALT_SYSMGR_CORE_NOC_IDLEACK_OFST 0xd0
9665 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA_LSB 0
9667 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA_MSB 0
9669 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA_WIDTH 1
9671 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA_SET_MSK 0x00000001
9673 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA_CLR_MSK 0xfffffffe
9675 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA_RESET 0x1
9677 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA_GET(value) (((value) & 0x00000001) >> 0)
9679 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA_SET(value) (((value) << 0) & 0x00000001)
9688 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA_LSB 4
9690 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA_MSB 4
9692 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA_WIDTH 1
9694 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA_SET_MSK 0x00000010
9696 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA_CLR_MSK 0xffffffef
9698 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA_RESET 0x1
9700 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA_GET(value) (((value) & 0x00000010) >> 4)
9702 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA_SET(value) (((value) << 4) & 0x00000010)
9704 #ifndef __ASSEMBLY__
9716 struct ALT_SYSMGR_CORE_NOC_IDLESTATUS_s
9718 const volatile uint32_t soc2fpga : 1;
9720 const volatile uint32_t lwsoc2fpga : 1;
9725 typedef struct ALT_SYSMGR_CORE_NOC_IDLESTATUS_s ALT_SYSMGR_CORE_NOC_IDLESTATUS_t;
9729 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_RESET 0x00000011
9731 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_OFST 0xd4
9755 #define ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE_LSB 0
9757 #define ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE_MSB 0
9759 #define ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE_WIDTH 1
9761 #define ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE_SET_MSK 0x00000001
9763 #define ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE_CLR_MSK 0xfffffffe
9765 #define ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE_RESET 0x1
9767 #define ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE_GET(value) (((value) & 0x00000001) >> 0)
9769 #define ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE_SET(value) (((value) << 0) & 0x00000001)
9771 #ifndef __ASSEMBLY__
9783 struct ALT_SYSMGR_CORE_FPGA2SOC_CTRL_s
9785 volatile uint32_t allow_secure : 1;
9790 typedef struct ALT_SYSMGR_CORE_FPGA2SOC_CTRL_s ALT_SYSMGR_CORE_FPGA2SOC_CTRL_t;
9794 #define ALT_SYSMGR_CORE_FPGA2SOC_CTRL_RESET 0x00000001
9796 #define ALT_SYSMGR_CORE_FPGA2SOC_CTRL_OFST 0xd8
9821 #define ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE_LSB 0
9823 #define ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE_MSB 0
9825 #define ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE_WIDTH 1
9827 #define ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE_SET_MSK 0x00000001
9829 #define ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE_CLR_MSK 0xfffffffe
9831 #define ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE_RESET 0x0
9833 #define ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE_GET(value) (((value) & 0x00000001) >> 0)
9835 #define ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE_SET(value) (((value) << 0) & 0x00000001)
9846 #define ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE_LSB 1
9848 #define ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE_MSB 1
9850 #define ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE_WIDTH 1
9852 #define ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE_SET_MSK 0x00000002
9854 #define ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE_CLR_MSK 0xfffffffd
9856 #define ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE_RESET 0x0
9858 #define ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE_GET(value) (((value) & 0x00000002) >> 1)
9860 #define ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE_SET(value) (((value) << 1) & 0x00000002)
9862 #ifndef __ASSEMBLY__
9874 struct ALT_SYSMGR_CORE_FPGA_CONFIG_s
9876 const volatile uint32_t fpga_complete : 1;
9877 const volatile uint32_t early_usermode : 1;
9882 typedef struct ALT_SYSMGR_CORE_FPGA_CONFIG_s ALT_SYSMGR_CORE_FPGA_CONFIG_t;
9886 #define ALT_SYSMGR_CORE_FPGA_CONFIG_RESET 0x00000000
9888 #define ALT_SYSMGR_CORE_FPGA_CONFIG_OFST 0xdc
9916 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA_LSB 0
9918 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA_MSB 0
9920 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA_WIDTH 1
9922 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA_SET_MSK 0x00000001
9924 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA_CLR_MSK 0xfffffffe
9926 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA_RESET 0x0
9928 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA_GET(value) (((value) & 0x00000001) >> 0)
9930 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA_SET(value) (((value) << 0) & 0x00000001)
9941 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB_LSB 8
9943 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB_MSB 8
9945 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB_WIDTH 1
9947 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB_SET_MSK 0x00000100
9949 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB_CLR_MSK 0xfffffeff
9951 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB_RESET 0x0
9953 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB_GET(value) (((value) & 0x00000100) >> 8)
9955 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB_SET(value) (((value) << 8) & 0x00000100)
9966 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC_LSB 16
9968 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC_MSB 16
9970 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC_WIDTH 1
9972 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC_SET_MSK 0x00010000
9974 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC_CLR_MSK 0xfffeffff
9976 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC_RESET 0x0
9978 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC_GET(value) (((value) & 0x00010000) >> 16)
9980 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC_SET(value) (((value) << 16) & 0x00010000)
9982 #ifndef __ASSEMBLY__
9994 struct ALT_SYSMGR_CORE_IOCSRCLK_GATE_s
9996 volatile uint32_t tilea : 1;
9998 volatile uint32_t tileb : 1;
10000 volatile uint32_t tilec : 1;
10005 typedef struct ALT_SYSMGR_CORE_IOCSRCLK_GATE_s ALT_SYSMGR_CORE_IOCSRCLK_GATE_t;
10009 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_RESET 0x00000000
10011 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_OFST 0xe0
10036 #define ALT_SYSMGR_CORE_GPO_VAL_LSB 0
10038 #define ALT_SYSMGR_CORE_GPO_VAL_MSB 31
10040 #define ALT_SYSMGR_CORE_GPO_VAL_WIDTH 32
10042 #define ALT_SYSMGR_CORE_GPO_VAL_SET_MSK 0xffffffff
10044 #define ALT_SYSMGR_CORE_GPO_VAL_CLR_MSK 0x00000000
10046 #define ALT_SYSMGR_CORE_GPO_VAL_RESET 0x0
10048 #define ALT_SYSMGR_CORE_GPO_VAL_GET(value) (((value) & 0xffffffff) >> 0)
10050 #define ALT_SYSMGR_CORE_GPO_VAL_SET(value) (((value) << 0) & 0xffffffff)
10052 #ifndef __ASSEMBLY__
10064 struct ALT_SYSMGR_CORE_GPO_s
10066 volatile uint32_t val : 32;
10070 typedef struct ALT_SYSMGR_CORE_GPO_s ALT_SYSMGR_CORE_GPO_t;
10074 #define ALT_SYSMGR_CORE_GPO_RESET 0x00000000
10076 #define ALT_SYSMGR_CORE_GPO_OFST 0xe4
10101 #define ALT_SYSMGR_CORE_GPI_VAL_LSB 0
10103 #define ALT_SYSMGR_CORE_GPI_VAL_MSB 31
10105 #define ALT_SYSMGR_CORE_GPI_VAL_WIDTH 32
10107 #define ALT_SYSMGR_CORE_GPI_VAL_SET_MSK 0xffffffff
10109 #define ALT_SYSMGR_CORE_GPI_VAL_CLR_MSK 0x00000000
10111 #define ALT_SYSMGR_CORE_GPI_VAL_RESET 0x0
10113 #define ALT_SYSMGR_CORE_GPI_VAL_GET(value) (((value) & 0xffffffff) >> 0)
10115 #define ALT_SYSMGR_CORE_GPI_VAL_SET(value) (((value) << 0) & 0xffffffff)
10117 #ifndef __ASSEMBLY__
10129 struct ALT_SYSMGR_CORE_GPI_s
10131 const volatile uint32_t val : 32;
10135 typedef struct ALT_SYSMGR_CORE_GPI_s ALT_SYSMGR_CORE_GPI_t;
10139 #define ALT_SYSMGR_CORE_GPI_RESET 0x00000000
10141 #define ALT_SYSMGR_CORE_GPI_OFST 0xe8
10168 #define ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE_LSB 0
10170 #define ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE_MSB 0
10172 #define ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE_WIDTH 1
10174 #define ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE_SET_MSK 0x00000001
10176 #define ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE_CLR_MSK 0xfffffffe
10178 #define ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE_RESET 0x0
10180 #define ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE_GET(value) (((value) & 0x00000001) >> 0)
10182 #define ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE_SET(value) (((value) << 0) & 0x00000001)
10184 #ifndef __ASSEMBLY__
10196 struct ALT_SYSMGR_CORE_MPU_s
10198 volatile uint32_t mpu_cfgsdisable : 1;
10203 typedef struct ALT_SYSMGR_CORE_MPU_s ALT_SYSMGR_CORE_MPU_t;
10207 #define ALT_SYSMGR_CORE_MPU_RESET 0x00000000
10209 #define ALT_SYSMGR_CORE_MPU_OFST 0xf0
10243 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0_LSB 0
10245 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0_MSB 0
10247 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0_WIDTH 1
10249 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0_SET_MSK 0x00000001
10251 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0_CLR_MSK 0xfffffffe
10253 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0_RESET 0x0
10255 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0_GET(value) (((value) & 0x00000001) >> 0)
10257 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0_SET(value) (((value) << 0) & 0x00000001)
10266 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1_LSB 1
10268 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1_MSB 1
10270 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1_WIDTH 1
10272 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1_SET_MSK 0x00000002
10274 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1_CLR_MSK 0xfffffffd
10276 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1_RESET 0x0
10278 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1_GET(value) (((value) & 0x00000002) >> 1)
10280 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1_SET(value) (((value) << 1) & 0x00000002)
10289 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2_LSB 2
10291 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2_MSB 2
10293 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2_WIDTH 1
10295 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2_SET_MSK 0x00000004
10297 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2_CLR_MSK 0xfffffffb
10299 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2_RESET 0x0
10301 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2_GET(value) (((value) & 0x00000004) >> 2)
10303 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2_SET(value) (((value) << 2) & 0x00000004)
10312 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3_LSB 3
10314 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3_MSB 3
10316 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3_WIDTH 1
10318 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3_SET_MSK 0x00000008
10320 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3_CLR_MSK 0xfffffff7
10322 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3_RESET 0x0
10324 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3_GET(value) (((value) & 0x00000008) >> 3)
10326 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3_SET(value) (((value) << 3) & 0x00000008)
10335 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4_LSB 4
10337 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4_MSB 4
10339 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4_WIDTH 1
10341 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4_SET_MSK 0x00000010
10343 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4_CLR_MSK 0xffffffef
10345 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4_RESET 0x0
10347 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4_GET(value) (((value) & 0x00000010) >> 4)
10349 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4_SET(value) (((value) << 4) & 0x00000010)
10358 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5_LSB 5
10360 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5_MSB 5
10362 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5_WIDTH 1
10364 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5_SET_MSK 0x00000020
10366 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5_CLR_MSK 0xffffffdf
10368 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5_RESET 0x0
10370 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5_GET(value) (((value) & 0x00000020) >> 5)
10372 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5_SET(value) (((value) << 5) & 0x00000020)
10381 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6_LSB 6
10383 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6_MSB 6
10385 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6_WIDTH 1
10387 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6_SET_MSK 0x00000040
10389 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6_CLR_MSK 0xffffffbf
10391 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6_RESET 0x0
10393 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6_GET(value) (((value) & 0x00000040) >> 6)
10395 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6_SET(value) (((value) << 6) & 0x00000040)
10404 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7_LSB 7
10406 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7_MSB 7
10408 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7_WIDTH 1
10410 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7_SET_MSK 0x00000080
10412 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7_CLR_MSK 0xffffff7f
10414 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7_RESET 0x0
10416 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7_GET(value) (((value) & 0x00000080) >> 7)
10418 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7_SET(value) (((value) << 7) & 0x00000080)
10427 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8_LSB 8
10429 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8_MSB 8
10431 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8_WIDTH 1
10433 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8_SET_MSK 0x00000100
10435 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8_CLR_MSK 0xfffffeff
10437 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8_RESET 0x0
10439 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8_GET(value) (((value) & 0x00000100) >> 8)
10441 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8_SET(value) (((value) << 8) & 0x00000100)
10450 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9_LSB 9
10452 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9_MSB 9
10454 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9_WIDTH 1
10456 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9_SET_MSK 0x00000200
10458 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9_CLR_MSK 0xfffffdff
10460 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9_RESET 0x0
10462 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9_GET(value) (((value) & 0x00000200) >> 9)
10464 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9_SET(value) (((value) << 9) & 0x00000200)
10473 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10_LSB 10
10475 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10_MSB 10
10477 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10_WIDTH 1
10479 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10_SET_MSK 0x00000400
10481 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10_CLR_MSK 0xfffffbff
10483 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10_RESET 0x0
10485 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10_GET(value) (((value) & 0x00000400) >> 10)
10487 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10_SET(value) (((value) << 10) & 0x00000400)
10496 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11_LSB 11
10498 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11_MSB 11
10500 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11_WIDTH 1
10502 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11_SET_MSK 0x00000800
10504 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11_CLR_MSK 0xfffff7ff
10506 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11_RESET 0x0
10508 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11_GET(value) (((value) & 0x00000800) >> 11)
10510 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11_SET(value) (((value) << 11) & 0x00000800)
10512 #ifndef __ASSEMBLY__
10524 struct ALT_SYSMGR_CORE_SDM_HPS_SPARE_s
10526 volatile uint32_t bit_0 : 1;
10527 volatile uint32_t bit_1 : 1;
10528 volatile uint32_t bit_2 : 1;
10529 volatile uint32_t bit_3 : 1;
10530 volatile uint32_t bit_4 : 1;
10531 volatile uint32_t bit_5 : 1;
10532 volatile uint32_t bit_6 : 1;
10533 volatile uint32_t bit_7 : 1;
10534 volatile uint32_t bit_8 : 1;
10535 volatile uint32_t bit_9 : 1;
10536 volatile uint32_t bit_10 : 1;
10537 volatile uint32_t bit_11 : 1;
10542 typedef struct ALT_SYSMGR_CORE_SDM_HPS_SPARE_s ALT_SYSMGR_CORE_SDM_HPS_SPARE_t;
10546 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_RESET 0x00000000
10548 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_OFST 0xf4
10572 #define ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL_LSB 0
10574 #define ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL_MSB 18
10576 #define ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL_WIDTH 19
10578 #define ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL_SET_MSK 0x0007ffff
10580 #define ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL_CLR_MSK 0xfff80000
10582 #define ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL_RESET 0x0
10584 #define ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL_GET(value) (((value) & 0x0007ffff) >> 0)
10586 #define ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL_SET(value) (((value) << 0) & 0x0007ffff)
10588 #ifndef __ASSEMBLY__
10600 struct ALT_SYSMGR_CORE_HPS_SDM_SPARE_s
10602 volatile uint32_t val : 19;
10607 typedef struct ALT_SYSMGR_CORE_HPS_SDM_SPARE_s ALT_SYSMGR_CORE_HPS_SDM_SPARE_t;
10611 #define ALT_SYSMGR_CORE_HPS_SDM_SPARE_RESET 0x00000000
10613 #define ALT_SYSMGR_CORE_HPS_SDM_SPARE_OFST 0xf8
10636 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL_LSB 0
10638 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL_MSB 31
10640 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL_WIDTH 32
10642 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL_SET_MSK 0xffffffff
10644 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL_CLR_MSK 0x00000000
10646 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL_RESET 0x0
10648 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL_GET(value) (((value) & 0xffffffff) >> 0)
10650 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL_SET(value) (((value) << 0) & 0xffffffff)
10652 #ifndef __ASSEMBLY__
10664 struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_s
10666 volatile uint32_t val : 32;
10670 typedef struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_s ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_t;
10674 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_RESET 0x00000000
10676 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_OFST 0x200
10699 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL_LSB 0
10701 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL_MSB 31
10703 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL_WIDTH 32
10705 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL_SET_MSK 0xffffffff
10707 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL_CLR_MSK 0x00000000
10709 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL_RESET 0x0
10711 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL_GET(value) (((value) & 0xffffffff) >> 0)
10713 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL_SET(value) (((value) << 0) & 0xffffffff)
10715 #ifndef __ASSEMBLY__
10727 struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_s
10729 volatile uint32_t val : 32;
10733 typedef struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_s ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_t;
10737 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_RESET 0x00000000
10739 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_OFST 0x204
10762 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL_LSB 0
10764 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL_MSB 31
10766 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL_WIDTH 32
10768 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL_SET_MSK 0xffffffff
10770 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL_CLR_MSK 0x00000000
10772 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL_RESET 0x0
10774 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL_GET(value) (((value) & 0xffffffff) >> 0)
10776 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL_SET(value) (((value) << 0) & 0xffffffff)
10778 #ifndef __ASSEMBLY__
10790 struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_s
10792 volatile uint32_t val : 32;
10796 typedef struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_s ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_t;
10800 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_RESET 0x00000000
10802 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_OFST 0x208
10825 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL_LSB 0
10827 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL_MSB 31
10829 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL_WIDTH 32
10831 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL_SET_MSK 0xffffffff
10833 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL_CLR_MSK 0x00000000
10835 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL_RESET 0x0
10837 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL_GET(value) (((value) & 0xffffffff) >> 0)
10839 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL_SET(value) (((value) << 0) & 0xffffffff)
10841 #ifndef __ASSEMBLY__
10853 struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_s
10855 volatile uint32_t val : 32;
10859 typedef struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_s ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_t;
10863 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_RESET 0x00000000
10865 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_OFST 0x20c
10888 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL_LSB 0
10890 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL_MSB 31
10892 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL_WIDTH 32
10894 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL_SET_MSK 0xffffffff
10896 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL_CLR_MSK 0x00000000
10898 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL_RESET 0x0
10900 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL_GET(value) (((value) & 0xffffffff) >> 0)
10902 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL_SET(value) (((value) << 0) & 0xffffffff)
10904 #ifndef __ASSEMBLY__
10916 struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_s
10918 volatile uint32_t val : 32;
10922 typedef struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_s ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_t;
10926 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_RESET 0x00000000
10928 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_OFST 0x210
10951 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL_LSB 0
10953 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL_MSB 31
10955 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL_WIDTH 32
10957 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL_SET_MSK 0xffffffff
10959 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL_CLR_MSK 0x00000000
10961 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL_RESET 0x0
10963 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL_GET(value) (((value) & 0xffffffff) >> 0)
10965 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL_SET(value) (((value) << 0) & 0xffffffff)
10967 #ifndef __ASSEMBLY__
10979 struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_s
10981 volatile uint32_t val : 32;
10985 typedef struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_s ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_t;
10989 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_RESET 0x00000000
10991 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_OFST 0x214
11014 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL_LSB 0
11016 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL_MSB 31
11018 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL_WIDTH 32
11020 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL_SET_MSK 0xffffffff
11022 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL_CLR_MSK 0x00000000
11024 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL_RESET 0x0
11026 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL_GET(value) (((value) & 0xffffffff) >> 0)
11028 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL_SET(value) (((value) << 0) & 0xffffffff)
11030 #ifndef __ASSEMBLY__
11042 struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_s
11044 volatile uint32_t val : 32;
11048 typedef struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_s ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_t;
11052 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_RESET 0x00000000
11054 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_OFST 0x218
11077 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL_LSB 0
11079 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL_MSB 31
11081 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL_WIDTH 32
11083 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL_SET_MSK 0xffffffff
11085 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL_CLR_MSK 0x00000000
11087 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL_RESET 0x0
11089 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL_GET(value) (((value) & 0xffffffff) >> 0)
11091 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL_SET(value) (((value) << 0) & 0xffffffff)
11093 #ifndef __ASSEMBLY__
11105 struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_s
11107 volatile uint32_t val : 32;
11111 typedef struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_s ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_t;
11115 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_RESET 0x00000000
11117 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_OFST 0x21c
11140 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL_LSB 0
11142 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL_MSB 31
11144 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL_WIDTH 32
11146 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL_SET_MSK 0xffffffff
11148 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL_CLR_MSK 0x00000000
11150 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL_RESET 0x0
11152 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL_GET(value) (((value) & 0xffffffff) >> 0)
11154 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL_SET(value) (((value) << 0) & 0xffffffff)
11156 #ifndef __ASSEMBLY__
11168 struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_s
11170 volatile uint32_t val : 32;
11174 typedef struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_s ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_t;
11178 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_RESET 0x00000000
11180 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_OFST 0x220
11203 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL_LSB 0
11205 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL_MSB 31
11207 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL_WIDTH 32
11209 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL_SET_MSK 0xffffffff
11211 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL_CLR_MSK 0x00000000
11213 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL_RESET 0x0
11215 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL_GET(value) (((value) & 0xffffffff) >> 0)
11217 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL_SET(value) (((value) << 0) & 0xffffffff)
11219 #ifndef __ASSEMBLY__
11231 struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_s
11233 volatile uint32_t val : 32;
11237 typedef struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_s ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_t;
11241 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_RESET 0x00000000
11243 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_OFST 0x224
11245 #ifndef __ASSEMBLY__
11257 struct ALT_SYSMGR_CORE_s
11259 volatile ALT_SYSMGR_CORE_SILICONID1_t siliconid1;
11260 volatile ALT_SYSMGR_CORE_SILICONID2_t siliconid2;
11261 volatile ALT_SYSMGR_CORE_WDDBG_t wddbg;
11262 volatile uint32_t _pad_0xc_0xf;
11263 volatile ALT_SYSMGR_CORE_MPU_STATUS_t mpu_status;
11264 volatile ALT_SYSMGR_CORE_MPU_ACE_t mpu_ace;
11265 volatile uint32_t _pad_0x18_0x1f[2];
11266 volatile ALT_SYSMGR_CORE_DMA_t dma;
11267 volatile ALT_SYSMGR_CORE_DMA_PERIPH_t dma_periph;
11268 volatile ALT_SYSMGR_CORE_SDMMC_t sdmmc;
11269 volatile ALT_SYSMGR_CORE_SDMMC_L3MASTER_t sdmmc_l3master;
11270 volatile ALT_SYSMGR_CORE_NAND_BOOTSTRAP_t nand_bootstrap;
11271 volatile ALT_SYSMGR_CORE_NAND_L3MASTER_t nand_l3master;
11272 volatile ALT_SYSMGR_CORE_USB0_L3MASTER_t usb0_l3master;
11273 volatile ALT_SYSMGR_CORE_USB1_L3MASTER_t usb1_l3master;
11274 volatile ALT_SYSMGR_CORE_EMAC_GLOBAL_t emac_global;
11275 volatile ALT_SYSMGR_CORE_EMAC0_t emac0;
11276 volatile ALT_SYSMGR_CORE_EMAC1_t emac1;
11277 volatile ALT_SYSMGR_CORE_EMAC2_t emac2;
11278 volatile ALT_SYSMGR_CORE_EMAC0_ACE_t emac0_ace;
11279 volatile ALT_SYSMGR_CORE_EMAC1_ACE_t emac1_ace;
11280 volatile ALT_SYSMGR_CORE_EMAC2_ACE_t emac2_ace;
11281 volatile ALT_SYSMGR_CORE_NAND_AXUSER_t nand_axuser;
11282 volatile uint32_t _pad_0x60_0x67[2];
11283 volatile ALT_SYSMGR_CORE_FPGAINTF_EN_1_t fpgaintf_en_1;
11284 volatile ALT_SYSMGR_CORE_FPGAINTF_EN_2_t fpgaintf_en_2;
11285 volatile ALT_SYSMGR_CORE_FPGAINTF_EN_3_t fpgaintf_en_3;
11286 volatile ALT_SYSMGR_CORE_DMA_L3MASTER_t dma_l3master;
11287 volatile ALT_SYSMGR_CORE_ETR_L3MASTER_t etr_l3master;
11288 volatile uint32_t _pad_0x7c_0x7f;
11289 volatile ALT_SYSMGR_CORE_SEC_CTRL_SLT_t sec_ctrl_slt;
11290 volatile ALT_SYSMGR_CORE_OSC_TRIM_t osc_trim;
11291 volatile uint32_t _pad_0x88_0x8f[2];
11292 volatile ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_t ecc_intmask_value;
11293 volatile ALT_SYSMGR_CORE_ECC_INTMASK_SET_t ecc_intmask_set;
11294 volatile ALT_SYSMGR_CORE_ECC_INTMASK_CLR_t ecc_intmask_clr;
11295 volatile ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_t ecc_intstatus_serr;
11296 volatile ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_t ecc_intstatus_derr;
11297 volatile uint32_t _pad_0xa4_0xaf[3];
11298 volatile ALT_SYSMGR_CORE_NOC_ADDR_REMAP_t noc_addr_remap;
11299 volatile ALT_SYSMGR_CORE_HMC_CLK_t hmc_clk;
11300 volatile ALT_SYSMGR_CORE_IO_PA_CTRL_t io_pa_ctrl;
11301 volatile uint32_t _pad_0xbc_0xbf;
11302 volatile ALT_SYSMGR_CORE_NOC_TIMEOUT_t noc_timeout;
11303 volatile ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_t noc_idlereq_set;
11304 volatile ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_t noc_idlereq_clr;
11305 volatile ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_t noc_idlereq_value;
11306 volatile ALT_SYSMGR_CORE_NOC_IDLEACK_t noc_idleack;
11307 volatile ALT_SYSMGR_CORE_NOC_IDLESTATUS_t noc_idlestatus;
11308 volatile ALT_SYSMGR_CORE_FPGA2SOC_CTRL_t fpga2soc_ctrl;
11309 volatile ALT_SYSMGR_CORE_FPGA_CONFIG_t fpga_config;
11310 volatile ALT_SYSMGR_CORE_IOCSRCLK_GATE_t iocsrclk_gate;
11311 volatile ALT_SYSMGR_CORE_GPO_t gpo;
11312 volatile ALT_SYSMGR_CORE_GPI_t gpi;
11313 volatile uint32_t _pad_0xec_0xef;
11314 volatile ALT_SYSMGR_CORE_MPU_t mpu;
11315 volatile ALT_SYSMGR_CORE_SDM_HPS_SPARE_t sdm_hps_spare;
11316 volatile ALT_SYSMGR_CORE_HPS_SDM_SPARE_t hps_sdm_spare;
11317 volatile uint32_t _pad_0xfc_0x1ff[65];
11318 volatile ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_t boot_scratch_cold0;
11319 volatile ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_t boot_scratch_cold1;
11320 volatile ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_t boot_scratch_cold2;
11321 volatile ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_t boot_scratch_cold3;
11322 volatile ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_t boot_scratch_cold4;
11323 volatile ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_t boot_scratch_cold5;
11324 volatile ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_t boot_scratch_cold6;
11325 volatile ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_t boot_scratch_cold7;
11326 volatile ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_t boot_scratch_cold8;
11327 volatile ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_t boot_scratch_cold9;
11328 volatile uint32_t _pad_0x228_0x500[182];
11332 typedef struct ALT_SYSMGR_CORE_s ALT_SYSMGR_CORE_t;
11334 struct ALT_SYSMGR_CORE_raw_s
11336 volatile uint32_t siliconid1;
11337 volatile uint32_t siliconid2;
11338 volatile uint32_t wddbg;
11339 volatile uint32_t _pad_0xc_0xf;
11340 volatile uint32_t mpu_status;
11341 volatile uint32_t mpu_ace;
11342 volatile uint32_t _pad_0x18_0x1f[2];
11343 volatile uint32_t dma;
11344 volatile uint32_t dma_periph;
11345 volatile uint32_t sdmmc;
11346 volatile uint32_t sdmmc_l3master;
11347 volatile uint32_t nand_bootstrap;
11348 volatile uint32_t nand_l3master;
11349 volatile uint32_t usb0_l3master;
11350 volatile uint32_t usb1_l3master;
11351 volatile uint32_t emac_global;
11352 volatile uint32_t emac0;
11353 volatile uint32_t emac1;
11354 volatile uint32_t emac2;
11355 volatile uint32_t emac0_ace;
11356 volatile uint32_t emac1_ace;
11357 volatile uint32_t emac2_ace;
11358 volatile uint32_t nand_axuser;
11359 volatile uint32_t _pad_0x60_0x67[2];
11360 volatile uint32_t fpgaintf_en_1;
11361 volatile uint32_t fpgaintf_en_2;
11362 volatile uint32_t fpgaintf_en_3;
11363 volatile uint32_t dma_l3master;
11364 volatile uint32_t etr_l3master;
11365 volatile uint32_t _pad_0x7c_0x7f;
11366 volatile uint32_t sec_ctrl_slt;
11367 volatile uint32_t osc_trim;
11368 volatile uint32_t _pad_0x88_0x8f[2];
11369 volatile uint32_t ecc_intmask_value;
11370 volatile uint32_t ecc_intmask_set;
11371 volatile uint32_t ecc_intmask_clr;
11372 volatile uint32_t ecc_intstatus_serr;
11373 volatile uint32_t ecc_intstatus_derr;
11374 volatile uint32_t _pad_0xa4_0xaf[3];
11375 volatile uint32_t noc_addr_remap;
11376 volatile uint32_t hmc_clk;
11377 volatile uint32_t io_pa_ctrl;
11378 volatile uint32_t _pad_0xbc_0xbf;
11379 volatile uint32_t noc_timeout;
11380 volatile uint32_t noc_idlereq_set;
11381 volatile uint32_t noc_idlereq_clr;
11382 volatile uint32_t noc_idlereq_value;
11383 volatile uint32_t noc_idleack;
11384 volatile uint32_t noc_idlestatus;
11385 volatile uint32_t fpga2soc_ctrl;
11386 volatile uint32_t fpga_config;
11387 volatile uint32_t iocsrclk_gate;
11388 volatile uint32_t gpo;
11389 volatile uint32_t gpi;
11390 volatile uint32_t _pad_0xec_0xef;
11391 volatile uint32_t mpu;
11392 volatile uint32_t sdm_hps_spare;
11393 volatile uint32_t hps_sdm_spare;
11394 volatile uint32_t _pad_0xfc_0x1ff[65];
11395 volatile uint32_t boot_scratch_cold0;
11396 volatile uint32_t boot_scratch_cold1;
11397 volatile uint32_t boot_scratch_cold2;
11398 volatile uint32_t boot_scratch_cold3;
11399 volatile uint32_t boot_scratch_cold4;
11400 volatile uint32_t boot_scratch_cold5;
11401 volatile uint32_t boot_scratch_cold6;
11402 volatile uint32_t boot_scratch_cold7;
11403 volatile uint32_t boot_scratch_cold8;
11404 volatile uint32_t boot_scratch_cold9;
11405 volatile uint32_t _pad_0x228_0x500[182];
11409 typedef struct ALT_SYSMGR_CORE_raw_s ALT_SYSMGR_CORE_raw_t;