35 #ifndef __ALT_SOCAL_CLKMGR_PERPLL_H__
36 #define __ALT_SOCAL_CLKMGR_PERPLL_H__
92 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_LSB 0
94 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_MSB 0
96 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_WIDTH 1
98 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_SET_MSK 0x00000001
100 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_CLR_MSK 0xfffffffe
102 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_RESET 0x1
104 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_GET(value) (((value) & 0x00000001) >> 0)
106 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_SET(value) (((value) << 0) & 0x00000001)
117 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_LSB 1
119 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_MSB 1
121 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_WIDTH 1
123 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_SET_MSK 0x00000002
125 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_CLR_MSK 0xfffffffd
127 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_RESET 0x1
129 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_GET(value) (((value) & 0x00000002) >> 1)
131 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_SET(value) (((value) << 1) & 0x00000002)
142 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_LSB 2
144 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_MSB 2
146 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_WIDTH 1
148 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_SET_MSK 0x00000004
150 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_CLR_MSK 0xfffffffb
152 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_RESET 0x1
154 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_GET(value) (((value) & 0x00000004) >> 2)
156 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_SET(value) (((value) << 2) & 0x00000004)
167 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_LSB 3
169 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_MSB 3
171 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_WIDTH 1
173 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_SET_MSK 0x00000008
175 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_CLR_MSK 0xfffffff7
177 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_RESET 0x1
179 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_GET(value) (((value) & 0x00000008) >> 3)
181 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_SET(value) (((value) << 3) & 0x00000008)
192 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_LSB 4
194 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_MSB 4
196 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_WIDTH 1
198 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_SET_MSK 0x00000010
200 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_CLR_MSK 0xffffffef
202 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_RESET 0x1
204 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_GET(value) (((value) & 0x00000010) >> 4)
206 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_SET(value) (((value) << 4) & 0x00000010)
218 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_LSB 5
220 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_MSB 5
222 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_WIDTH 1
224 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_SET_MSK 0x00000020
226 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_CLR_MSK 0xffffffdf
228 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_RESET 0x1
230 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_GET(value) (((value) & 0x00000020) >> 5)
232 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_SET(value) (((value) << 5) & 0x00000020)
243 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_LSB 6
245 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_MSB 6
247 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_WIDTH 1
249 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_SET_MSK 0x00000040
251 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_CLR_MSK 0xffffffbf
253 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_RESET 0x1
255 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_GET(value) (((value) & 0x00000040) >> 6)
257 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_SET(value) (((value) << 6) & 0x00000040)
268 #define ALT_CLKMGR_PERPLL_EN_PSICLKEN_LSB 7
270 #define ALT_CLKMGR_PERPLL_EN_PSICLKEN_MSB 7
272 #define ALT_CLKMGR_PERPLL_EN_PSICLKEN_WIDTH 1
274 #define ALT_CLKMGR_PERPLL_EN_PSICLKEN_SET_MSK 0x00000080
276 #define ALT_CLKMGR_PERPLL_EN_PSICLKEN_CLR_MSK 0xffffff7f
278 #define ALT_CLKMGR_PERPLL_EN_PSICLKEN_RESET 0x1
280 #define ALT_CLKMGR_PERPLL_EN_PSICLKEN_GET(value) (((value) & 0x00000080) >> 7)
282 #define ALT_CLKMGR_PERPLL_EN_PSICLKEN_SET(value) (((value) << 7) & 0x00000080)
294 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_LSB 8
296 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_MSB 8
298 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_WIDTH 1
300 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_SET_MSK 0x00000100
302 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_CLR_MSK 0xfffffeff
304 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_RESET 0x1
306 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_GET(value) (((value) & 0x00000100) >> 8)
308 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_SET(value) (((value) << 8) & 0x00000100)
320 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_LSB 9
322 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_MSB 9
324 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_WIDTH 1
326 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_SET_MSK 0x00000200
328 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_CLR_MSK 0xfffffdff
330 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_RESET 0x1
332 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_GET(value) (((value) & 0x00000200) >> 9)
334 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_SET(value) (((value) << 9) & 0x00000200)
346 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_LSB 10
348 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_MSB 10
350 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_WIDTH 1
352 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_SET_MSK 0x00000400
354 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_CLR_MSK 0xfffffbff
356 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_RESET 0x1
358 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_GET(value) (((value) & 0x00000400) >> 10)
360 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_SET(value) (((value) << 10) & 0x00000400)
374 struct ALT_CLKMGR_PERPLL_EN_s
376 volatile uint32_t emac0en : 1;
377 volatile uint32_t emac1en : 1;
378 volatile uint32_t emac2en : 1;
379 volatile uint32_t emacptpen : 1;
380 volatile uint32_t gpiodben : 1;
381 volatile uint32_t sdmmcclken : 1;
382 volatile uint32_t s2fuser1clken : 1;
383 volatile uint32_t psiclken : 1;
384 volatile uint32_t usbclken : 1;
385 volatile uint32_t spimclken : 1;
386 volatile uint32_t nandclken : 1;
391 typedef struct ALT_CLKMGR_PERPLL_EN_s ALT_CLKMGR_PERPLL_EN_t;
395 #define ALT_CLKMGR_PERPLL_EN_RESET 0x00000fff
397 #define ALT_CLKMGR_PERPLL_EN_OFST 0x0
431 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_LSB 0
433 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_MSB 0
435 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_WIDTH 1
437 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_SET_MSK 0x00000001
439 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_CLR_MSK 0xfffffffe
441 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_RESET 0x1
443 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_GET(value) (((value) & 0x00000001) >> 0)
445 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_SET(value) (((value) << 0) & 0x00000001)
456 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_LSB 1
458 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_MSB 1
460 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_WIDTH 1
462 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_SET_MSK 0x00000002
464 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_CLR_MSK 0xfffffffd
466 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_RESET 0x1
468 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_GET(value) (((value) & 0x00000002) >> 1)
470 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_SET(value) (((value) << 1) & 0x00000002)
481 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_LSB 2
483 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_MSB 2
485 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_WIDTH 1
487 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_SET_MSK 0x00000004
489 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_CLR_MSK 0xfffffffb
491 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_RESET 0x1
493 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_GET(value) (((value) & 0x00000004) >> 2)
495 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_SET(value) (((value) << 2) & 0x00000004)
506 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_LSB 3
508 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_MSB 3
510 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_WIDTH 1
512 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_SET_MSK 0x00000008
514 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_CLR_MSK 0xfffffff7
516 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_RESET 0x1
518 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_GET(value) (((value) & 0x00000008) >> 3)
520 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_SET(value) (((value) << 3) & 0x00000008)
531 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_LSB 4
533 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_MSB 4
535 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_WIDTH 1
537 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_SET_MSK 0x00000010
539 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_CLR_MSK 0xffffffef
541 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_RESET 0x1
543 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_GET(value) (((value) & 0x00000010) >> 4)
545 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_SET(value) (((value) << 4) & 0x00000010)
557 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_LSB 5
559 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_MSB 5
561 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_WIDTH 1
563 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_SET_MSK 0x00000020
565 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_CLR_MSK 0xffffffdf
567 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_RESET 0x1
569 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_GET(value) (((value) & 0x00000020) >> 5)
571 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_SET(value) (((value) << 5) & 0x00000020)
582 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_LSB 6
584 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_MSB 6
586 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_WIDTH 1
588 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_SET_MSK 0x00000040
590 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_CLR_MSK 0xffffffbf
592 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_RESET 0x1
594 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_GET(value) (((value) & 0x00000040) >> 6)
596 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_SET(value) (((value) << 6) & 0x00000040)
607 #define ALT_CLKMGR_PERPLL_ENS_PSICLKEN_LSB 7
609 #define ALT_CLKMGR_PERPLL_ENS_PSICLKEN_MSB 7
611 #define ALT_CLKMGR_PERPLL_ENS_PSICLKEN_WIDTH 1
613 #define ALT_CLKMGR_PERPLL_ENS_PSICLKEN_SET_MSK 0x00000080
615 #define ALT_CLKMGR_PERPLL_ENS_PSICLKEN_CLR_MSK 0xffffff7f
617 #define ALT_CLKMGR_PERPLL_ENS_PSICLKEN_RESET 0x1
619 #define ALT_CLKMGR_PERPLL_ENS_PSICLKEN_GET(value) (((value) & 0x00000080) >> 7)
621 #define ALT_CLKMGR_PERPLL_ENS_PSICLKEN_SET(value) (((value) << 7) & 0x00000080)
633 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_LSB 8
635 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_MSB 8
637 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_WIDTH 1
639 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_SET_MSK 0x00000100
641 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_CLR_MSK 0xfffffeff
643 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_RESET 0x1
645 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_GET(value) (((value) & 0x00000100) >> 8)
647 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_SET(value) (((value) << 8) & 0x00000100)
659 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_LSB 9
661 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_MSB 9
663 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_WIDTH 1
665 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_SET_MSK 0x00000200
667 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_CLR_MSK 0xfffffdff
669 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_RESET 0x1
671 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_GET(value) (((value) & 0x00000200) >> 9)
673 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_SET(value) (((value) << 9) & 0x00000200)
685 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_LSB 10
687 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_MSB 10
689 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_WIDTH 1
691 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_SET_MSK 0x00000400
693 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_CLR_MSK 0xfffffbff
695 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_RESET 0x1
697 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_GET(value) (((value) & 0x00000400) >> 10)
699 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_SET(value) (((value) << 10) & 0x00000400)
713 struct ALT_CLKMGR_PERPLL_ENS_s
715 volatile uint32_t emac0en : 1;
716 volatile uint32_t emac1en : 1;
717 volatile uint32_t emac2en : 1;
718 volatile uint32_t emacptpen : 1;
719 volatile uint32_t gpiodben : 1;
720 volatile uint32_t sdmmcclken : 1;
721 volatile uint32_t s2fuser1clken : 1;
722 volatile uint32_t psiclken : 1;
723 volatile uint32_t usbclken : 1;
724 volatile uint32_t spimclken : 1;
725 volatile uint32_t nandclken : 1;
730 typedef struct ALT_CLKMGR_PERPLL_ENS_s ALT_CLKMGR_PERPLL_ENS_t;
734 #define ALT_CLKMGR_PERPLL_ENS_RESET 0x00000fff
736 #define ALT_CLKMGR_PERPLL_ENS_OFST 0x4
770 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_LSB 0
772 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_MSB 0
774 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_WIDTH 1
776 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_SET_MSK 0x00000001
778 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_CLR_MSK 0xfffffffe
780 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_RESET 0x1
782 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_GET(value) (((value) & 0x00000001) >> 0)
784 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_SET(value) (((value) << 0) & 0x00000001)
795 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_LSB 1
797 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_MSB 1
799 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_WIDTH 1
801 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_SET_MSK 0x00000002
803 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_CLR_MSK 0xfffffffd
805 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_RESET 0x1
807 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_GET(value) (((value) & 0x00000002) >> 1)
809 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_SET(value) (((value) << 1) & 0x00000002)
820 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_LSB 2
822 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_MSB 2
824 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_WIDTH 1
826 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_SET_MSK 0x00000004
828 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_CLR_MSK 0xfffffffb
830 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_RESET 0x1
832 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_GET(value) (((value) & 0x00000004) >> 2)
834 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_SET(value) (((value) << 2) & 0x00000004)
845 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_LSB 3
847 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_MSB 3
849 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_WIDTH 1
851 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_SET_MSK 0x00000008
853 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_CLR_MSK 0xfffffff7
855 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_RESET 0x1
857 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_GET(value) (((value) & 0x00000008) >> 3)
859 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_SET(value) (((value) << 3) & 0x00000008)
870 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_LSB 4
872 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_MSB 4
874 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_WIDTH 1
876 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_SET_MSK 0x00000010
878 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_CLR_MSK 0xffffffef
880 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_RESET 0x1
882 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_GET(value) (((value) & 0x00000010) >> 4)
884 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_SET(value) (((value) << 4) & 0x00000010)
896 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_LSB 5
898 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_MSB 5
900 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_WIDTH 1
902 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_SET_MSK 0x00000020
904 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_CLR_MSK 0xffffffdf
906 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_RESET 0x1
908 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_GET(value) (((value) & 0x00000020) >> 5)
910 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_SET(value) (((value) << 5) & 0x00000020)
921 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_LSB 6
923 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_MSB 6
925 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_WIDTH 1
927 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_SET_MSK 0x00000040
929 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_CLR_MSK 0xffffffbf
931 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_RESET 0x1
933 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_GET(value) (((value) & 0x00000040) >> 6)
935 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_SET(value) (((value) << 6) & 0x00000040)
946 #define ALT_CLKMGR_PERPLL_ENR_PSICLKEN_LSB 7
948 #define ALT_CLKMGR_PERPLL_ENR_PSICLKEN_MSB 7
950 #define ALT_CLKMGR_PERPLL_ENR_PSICLKEN_WIDTH 1
952 #define ALT_CLKMGR_PERPLL_ENR_PSICLKEN_SET_MSK 0x00000080
954 #define ALT_CLKMGR_PERPLL_ENR_PSICLKEN_CLR_MSK 0xffffff7f
956 #define ALT_CLKMGR_PERPLL_ENR_PSICLKEN_RESET 0x1
958 #define ALT_CLKMGR_PERPLL_ENR_PSICLKEN_GET(value) (((value) & 0x00000080) >> 7)
960 #define ALT_CLKMGR_PERPLL_ENR_PSICLKEN_SET(value) (((value) << 7) & 0x00000080)
972 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_LSB 8
974 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_MSB 8
976 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_WIDTH 1
978 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_SET_MSK 0x00000100
980 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_CLR_MSK 0xfffffeff
982 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_RESET 0x1
984 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_GET(value) (((value) & 0x00000100) >> 8)
986 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_SET(value) (((value) << 8) & 0x00000100)
998 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_LSB 9
1000 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_MSB 9
1002 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_WIDTH 1
1004 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_SET_MSK 0x00000200
1006 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_CLR_MSK 0xfffffdff
1008 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_RESET 0x1
1010 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_GET(value) (((value) & 0x00000200) >> 9)
1012 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_SET(value) (((value) << 9) & 0x00000200)
1024 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_LSB 10
1026 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_MSB 10
1028 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_WIDTH 1
1030 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_SET_MSK 0x00000400
1032 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_CLR_MSK 0xfffffbff
1034 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_RESET 0x1
1036 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_GET(value) (((value) & 0x00000400) >> 10)
1038 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_SET(value) (((value) << 10) & 0x00000400)
1040 #ifndef __ASSEMBLY__
1052 struct ALT_CLKMGR_PERPLL_ENR_s
1054 volatile uint32_t emac0en : 1;
1055 volatile uint32_t emac1en : 1;
1056 volatile uint32_t emac2en : 1;
1057 volatile uint32_t emacptpen : 1;
1058 volatile uint32_t gpiodben : 1;
1059 volatile uint32_t sdmmcclken : 1;
1060 volatile uint32_t s2fuser1clken : 1;
1061 volatile uint32_t psiclken : 1;
1062 volatile uint32_t usbclken : 1;
1063 volatile uint32_t spimclken : 1;
1064 volatile uint32_t nandclken : 1;
1069 typedef struct ALT_CLKMGR_PERPLL_ENR_s ALT_CLKMGR_PERPLL_ENR_t;
1073 #define ALT_CLKMGR_PERPLL_ENR_RESET 0x00000fff
1075 #define ALT_CLKMGR_PERPLL_ENR_OFST 0x8
1110 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_LSB 0
1112 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_MSB 0
1114 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_WIDTH 1
1116 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_SET_MSK 0x00000001
1118 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_CLR_MSK 0xfffffffe
1120 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_RESET 0x1
1122 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_GET(value) (((value) & 0x00000001) >> 0)
1124 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_SET(value) (((value) << 0) & 0x00000001)
1136 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_LSB 1
1138 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_MSB 1
1140 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_WIDTH 1
1142 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_SET_MSK 0x00000002
1144 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_CLR_MSK 0xfffffffd
1146 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_RESET 0x1
1148 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_GET(value) (((value) & 0x00000002) >> 1)
1150 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_SET(value) (((value) << 1) & 0x00000002)
1162 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_LSB 2
1164 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_MSB 2
1166 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_WIDTH 1
1168 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_SET_MSK 0x00000004
1170 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_CLR_MSK 0xfffffffb
1172 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_RESET 0x1
1174 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_GET(value) (((value) & 0x00000004) >> 2)
1176 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_SET(value) (((value) << 2) & 0x00000004)
1188 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_LSB 3
1190 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_MSB 3
1192 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_WIDTH 1
1194 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_SET_MSK 0x00000008
1196 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_CLR_MSK 0xfffffff7
1198 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_RESET 0x1
1200 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_GET(value) (((value) & 0x00000008) >> 3)
1202 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_SET(value) (((value) << 3) & 0x00000008)
1214 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_LSB 4
1216 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_MSB 4
1218 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_WIDTH 1
1220 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_SET_MSK 0x00000010
1222 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_CLR_MSK 0xffffffef
1224 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_RESET 0x1
1226 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_GET(value) (((value) & 0x00000010) >> 4)
1228 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_SET(value) (((value) << 4) & 0x00000010)
1240 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_LSB 5
1242 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_MSB 5
1244 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_WIDTH 1
1246 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_SET_MSK 0x00000020
1248 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_CLR_MSK 0xffffffdf
1250 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_RESET 0x1
1252 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_GET(value) (((value) & 0x00000020) >> 5)
1254 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_SET(value) (((value) << 5) & 0x00000020)
1266 #define ALT_CLKMGR_PERPLL_BYPASS_PSIREF_LSB 6
1268 #define ALT_CLKMGR_PERPLL_BYPASS_PSIREF_MSB 6
1270 #define ALT_CLKMGR_PERPLL_BYPASS_PSIREF_WIDTH 1
1272 #define ALT_CLKMGR_PERPLL_BYPASS_PSIREF_SET_MSK 0x00000040
1274 #define ALT_CLKMGR_PERPLL_BYPASS_PSIREF_CLR_MSK 0xffffffbf
1276 #define ALT_CLKMGR_PERPLL_BYPASS_PSIREF_RESET 0x1
1278 #define ALT_CLKMGR_PERPLL_BYPASS_PSIREF_GET(value) (((value) & 0x00000040) >> 6)
1280 #define ALT_CLKMGR_PERPLL_BYPASS_PSIREF_SET(value) (((value) << 6) & 0x00000040)
1282 #ifndef __ASSEMBLY__
1294 struct ALT_CLKMGR_PERPLL_BYPASS_s
1296 volatile uint32_t emaca : 1;
1297 volatile uint32_t emacb : 1;
1298 volatile uint32_t emacptp : 1;
1299 volatile uint32_t gpiodb : 1;
1300 volatile uint32_t sdmmc : 1;
1301 volatile uint32_t s2fuser1 : 1;
1302 volatile uint32_t psiref : 1;
1307 typedef struct ALT_CLKMGR_PERPLL_BYPASS_s ALT_CLKMGR_PERPLL_BYPASS_t;
1311 #define ALT_CLKMGR_PERPLL_BYPASS_RESET 0x000000ff
1313 #define ALT_CLKMGR_PERPLL_BYPASS_OFST 0xc
1344 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_LSB 0
1346 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_MSB 0
1348 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_WIDTH 1
1350 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_SET_MSK 0x00000001
1352 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_CLR_MSK 0xfffffffe
1354 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_RESET 0x1
1356 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_GET(value) (((value) & 0x00000001) >> 0)
1358 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_SET(value) (((value) << 0) & 0x00000001)
1370 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_LSB 1
1372 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_MSB 1
1374 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_WIDTH 1
1376 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_SET_MSK 0x00000002
1378 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_CLR_MSK 0xfffffffd
1380 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_RESET 0x1
1382 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_GET(value) (((value) & 0x00000002) >> 1)
1384 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_SET(value) (((value) << 1) & 0x00000002)
1396 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_LSB 2
1398 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_MSB 2
1400 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_WIDTH 1
1402 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_SET_MSK 0x00000004
1404 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_CLR_MSK 0xfffffffb
1406 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_RESET 0x1
1408 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_GET(value) (((value) & 0x00000004) >> 2)
1410 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_SET(value) (((value) << 2) & 0x00000004)
1422 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_LSB 3
1424 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_MSB 3
1426 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_WIDTH 1
1428 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_SET_MSK 0x00000008
1430 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_CLR_MSK 0xfffffff7
1432 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_RESET 0x1
1434 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_GET(value) (((value) & 0x00000008) >> 3)
1436 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_SET(value) (((value) << 3) & 0x00000008)
1448 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_LSB 4
1450 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_MSB 4
1452 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_WIDTH 1
1454 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_SET_MSK 0x00000010
1456 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_CLR_MSK 0xffffffef
1458 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_RESET 0x1
1460 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_GET(value) (((value) & 0x00000010) >> 4)
1462 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_SET(value) (((value) << 4) & 0x00000010)
1474 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_LSB 5
1476 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_MSB 5
1478 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_WIDTH 1
1480 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_SET_MSK 0x00000020
1482 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_CLR_MSK 0xffffffdf
1484 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_RESET 0x1
1486 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_GET(value) (((value) & 0x00000020) >> 5)
1488 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_SET(value) (((value) << 5) & 0x00000020)
1500 #define ALT_CLKMGR_PERPLL_BYPASSS_PSIREF_LSB 6
1502 #define ALT_CLKMGR_PERPLL_BYPASSS_PSIREF_MSB 6
1504 #define ALT_CLKMGR_PERPLL_BYPASSS_PSIREF_WIDTH 1
1506 #define ALT_CLKMGR_PERPLL_BYPASSS_PSIREF_SET_MSK 0x00000040
1508 #define ALT_CLKMGR_PERPLL_BYPASSS_PSIREF_CLR_MSK 0xffffffbf
1510 #define ALT_CLKMGR_PERPLL_BYPASSS_PSIREF_RESET 0x1
1512 #define ALT_CLKMGR_PERPLL_BYPASSS_PSIREF_GET(value) (((value) & 0x00000040) >> 6)
1514 #define ALT_CLKMGR_PERPLL_BYPASSS_PSIREF_SET(value) (((value) << 6) & 0x00000040)
1516 #ifndef __ASSEMBLY__
1528 struct ALT_CLKMGR_PERPLL_BYPASSS_s
1530 volatile uint32_t emaca : 1;
1531 volatile uint32_t emacb : 1;
1532 volatile uint32_t emacptp : 1;
1533 volatile uint32_t gpiodb : 1;
1534 volatile uint32_t sdmmc : 1;
1535 volatile uint32_t s2fuser1 : 1;
1536 volatile uint32_t psiref : 1;
1541 typedef struct ALT_CLKMGR_PERPLL_BYPASSS_s ALT_CLKMGR_PERPLL_BYPASSS_t;
1545 #define ALT_CLKMGR_PERPLL_BYPASSS_RESET 0x000000ff
1547 #define ALT_CLKMGR_PERPLL_BYPASSS_OFST 0x10
1578 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_LSB 0
1580 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_MSB 0
1582 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_WIDTH 1
1584 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_SET_MSK 0x00000001
1586 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_CLR_MSK 0xfffffffe
1588 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_RESET 0x1
1590 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_GET(value) (((value) & 0x00000001) >> 0)
1592 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_SET(value) (((value) << 0) & 0x00000001)
1604 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_LSB 1
1606 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_MSB 1
1608 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_WIDTH 1
1610 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_SET_MSK 0x00000002
1612 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_CLR_MSK 0xfffffffd
1614 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_RESET 0x1
1616 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_GET(value) (((value) & 0x00000002) >> 1)
1618 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_SET(value) (((value) << 1) & 0x00000002)
1630 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_LSB 2
1632 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_MSB 2
1634 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_WIDTH 1
1636 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_SET_MSK 0x00000004
1638 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_CLR_MSK 0xfffffffb
1640 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_RESET 0x1
1642 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_GET(value) (((value) & 0x00000004) >> 2)
1644 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_SET(value) (((value) << 2) & 0x00000004)
1656 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_LSB 3
1658 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_MSB 3
1660 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_WIDTH 1
1662 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_SET_MSK 0x00000008
1664 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_CLR_MSK 0xfffffff7
1666 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_RESET 0x1
1668 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_GET(value) (((value) & 0x00000008) >> 3)
1670 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_SET(value) (((value) << 3) & 0x00000008)
1682 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_LSB 4
1684 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_MSB 4
1686 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_WIDTH 1
1688 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_SET_MSK 0x00000010
1690 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_CLR_MSK 0xffffffef
1692 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_RESET 0x1
1694 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_GET(value) (((value) & 0x00000010) >> 4)
1696 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_SET(value) (((value) << 4) & 0x00000010)
1708 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_LSB 5
1710 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_MSB 5
1712 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_WIDTH 1
1714 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_SET_MSK 0x00000020
1716 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_CLR_MSK 0xffffffdf
1718 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_RESET 0x1
1720 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_GET(value) (((value) & 0x00000020) >> 5)
1722 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_SET(value) (((value) << 5) & 0x00000020)
1734 #define ALT_CLKMGR_PERPLL_BYPASSR_PSIREF_LSB 6
1736 #define ALT_CLKMGR_PERPLL_BYPASSR_PSIREF_MSB 6
1738 #define ALT_CLKMGR_PERPLL_BYPASSR_PSIREF_WIDTH 1
1740 #define ALT_CLKMGR_PERPLL_BYPASSR_PSIREF_SET_MSK 0x00000040
1742 #define ALT_CLKMGR_PERPLL_BYPASSR_PSIREF_CLR_MSK 0xffffffbf
1744 #define ALT_CLKMGR_PERPLL_BYPASSR_PSIREF_RESET 0x1
1746 #define ALT_CLKMGR_PERPLL_BYPASSR_PSIREF_GET(value) (((value) & 0x00000040) >> 6)
1748 #define ALT_CLKMGR_PERPLL_BYPASSR_PSIREF_SET(value) (((value) << 6) & 0x00000040)
1750 #ifndef __ASSEMBLY__
1762 struct ALT_CLKMGR_PERPLL_BYPASSR_s
1764 volatile uint32_t emaca : 1;
1765 volatile uint32_t emacb : 1;
1766 volatile uint32_t emacptp : 1;
1767 volatile uint32_t gpiodb : 1;
1768 volatile uint32_t sdmmc : 1;
1769 volatile uint32_t s2fuser1 : 1;
1770 volatile uint32_t psiref : 1;
1775 typedef struct ALT_CLKMGR_PERPLL_BYPASSR_s ALT_CLKMGR_PERPLL_BYPASSR_t;
1779 #define ALT_CLKMGR_PERPLL_BYPASSR_RESET 0x000000ff
1781 #define ALT_CLKMGR_PERPLL_BYPASSR_OFST 0x14
1808 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_LSB 0
1810 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_MSB 10
1812 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_WIDTH 11
1814 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_SET_MSK 0x000007ff
1816 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_CLR_MSK 0xfffff800
1818 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_RESET 0x1
1820 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
1822 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
1847 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_MAIN 0x0
1852 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_PERI 0x1
1857 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_OSC1 0x2
1862 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_INTOSC 0x3
1867 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_FPGA 0x4
1870 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_LSB 16
1872 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_MSB 18
1874 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_WIDTH 3
1876 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_SET_MSK 0x00070000
1878 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_CLR_MSK 0xfff8ffff
1880 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_RESET 0x1
1882 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
1884 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
1886 #ifndef __ASSEMBLY__
1898 struct ALT_CLKMGR_PERPLL_CNTR2CLK_s
1900 volatile uint32_t cnt : 11;
1902 volatile uint32_t src : 3;
1907 typedef struct ALT_CLKMGR_PERPLL_CNTR2CLK_s ALT_CLKMGR_PERPLL_CNTR2CLK_t;
1911 #define ALT_CLKMGR_PERPLL_CNTR2CLK_RESET 0x00010001
1913 #define ALT_CLKMGR_PERPLL_CNTR2CLK_OFST 0x18
1940 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_LSB 0
1942 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_MSB 10
1944 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_WIDTH 11
1946 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_SET_MSK 0x000007ff
1948 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_CLR_MSK 0xfffff800
1950 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_RESET 0x1
1952 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
1954 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
1979 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_MAIN 0x0
1984 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_PERI 0x1
1989 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_OSC1 0x2
1994 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_INTOSC 0x3
1999 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_FPGA 0x4
2002 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_LSB 16
2004 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_MSB 18
2006 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_WIDTH 3
2008 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_SET_MSK 0x00070000
2010 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_CLR_MSK 0xfff8ffff
2012 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_RESET 0x1
2014 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
2016 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
2018 #ifndef __ASSEMBLY__
2030 struct ALT_CLKMGR_PERPLL_CNTR3CLK_s
2032 volatile uint32_t cnt : 11;
2034 volatile uint32_t src : 3;
2039 typedef struct ALT_CLKMGR_PERPLL_CNTR3CLK_s ALT_CLKMGR_PERPLL_CNTR3CLK_t;
2043 #define ALT_CLKMGR_PERPLL_CNTR3CLK_RESET 0x00010001
2045 #define ALT_CLKMGR_PERPLL_CNTR3CLK_OFST 0x1c
2072 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_LSB 0
2074 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_MSB 10
2076 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_WIDTH 11
2078 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_SET_MSK 0x000007ff
2080 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_CLR_MSK 0xfffff800
2082 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_RESET 0x4
2084 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
2086 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
2111 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_MAIN 0x0
2116 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_PERI 0x1
2121 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_OSC1 0x2
2126 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_INTOSC 0x3
2131 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_FPGA 0x4
2134 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_LSB 16
2136 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_MSB 18
2138 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_WIDTH 3
2140 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_SET_MSK 0x00070000
2142 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_CLR_MSK 0xfff8ffff
2144 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_RESET 0x1
2146 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
2148 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
2150 #ifndef __ASSEMBLY__
2162 struct ALT_CLKMGR_PERPLL_CNTR4CLK_s
2164 volatile uint32_t cnt : 11;
2166 volatile uint32_t src : 3;
2171 typedef struct ALT_CLKMGR_PERPLL_CNTR4CLK_s ALT_CLKMGR_PERPLL_CNTR4CLK_t;
2175 #define ALT_CLKMGR_PERPLL_CNTR4CLK_RESET 0x00010004
2177 #define ALT_CLKMGR_PERPLL_CNTR4CLK_OFST 0x20
2204 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_LSB 0
2206 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_MSB 10
2208 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_WIDTH 11
2210 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_SET_MSK 0x000007ff
2212 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_CLR_MSK 0xfffff800
2214 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_RESET 0x1
2216 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
2218 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
2243 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_MAIN 0x0
2248 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_PERI 0x1
2253 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_OSC1 0x2
2258 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_INTOSC 0x3
2263 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_FPGA 0x4
2266 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_LSB 16
2268 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_MSB 18
2270 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_WIDTH 3
2272 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_SET_MSK 0x00070000
2274 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_CLR_MSK 0xfff8ffff
2276 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_RESET 0x0
2278 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
2280 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
2282 #ifndef __ASSEMBLY__
2294 struct ALT_CLKMGR_PERPLL_CNTR5CLK_s
2296 volatile uint32_t cnt : 11;
2298 volatile uint32_t src : 3;
2303 typedef struct ALT_CLKMGR_PERPLL_CNTR5CLK_s ALT_CLKMGR_PERPLL_CNTR5CLK_t;
2307 #define ALT_CLKMGR_PERPLL_CNTR5CLK_RESET 0x00000001
2309 #define ALT_CLKMGR_PERPLL_CNTR5CLK_OFST 0x24
2336 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_LSB 0
2338 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_MSB 10
2340 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_WIDTH 11
2342 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_SET_MSK 0x000007ff
2344 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_CLR_MSK 0xfffff800
2346 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_RESET 0x1
2348 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
2350 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
2375 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_MAIN 0x0
2380 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_PERI 0x1
2385 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_OSC1 0x2
2390 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_INTOSC 0x3
2395 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_FPGA 0x4
2398 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_LSB 16
2400 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_MSB 18
2402 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_WIDTH 3
2404 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_SET_MSK 0x00070000
2406 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_CLR_MSK 0xfff8ffff
2408 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_RESET 0x0
2410 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
2412 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
2414 #ifndef __ASSEMBLY__
2426 struct ALT_CLKMGR_PERPLL_CNTR6CLK_s
2428 volatile uint32_t cnt : 11;
2430 volatile uint32_t src : 3;
2435 typedef struct ALT_CLKMGR_PERPLL_CNTR6CLK_s ALT_CLKMGR_PERPLL_CNTR6CLK_t;
2439 #define ALT_CLKMGR_PERPLL_CNTR6CLK_RESET 0x00000001
2441 #define ALT_CLKMGR_PERPLL_CNTR6CLK_OFST 0x28
2466 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_LSB 0
2468 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_MSB 10
2470 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_WIDTH 11
2472 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_SET_MSK 0x000007ff
2474 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_CLR_MSK 0xfffff800
2476 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_RESET 0x0
2478 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
2480 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
2482 #ifndef __ASSEMBLY__
2494 struct ALT_CLKMGR_PERPLL_CNTR7CLK_s
2496 volatile uint32_t cnt : 11;
2501 typedef struct ALT_CLKMGR_PERPLL_CNTR7CLK_s ALT_CLKMGR_PERPLL_CNTR7CLK_t;
2505 #define ALT_CLKMGR_PERPLL_CNTR7CLK_RESET 0x00000000
2507 #define ALT_CLKMGR_PERPLL_CNTR7CLK_OFST 0x2c
2534 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_LSB 0
2536 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_MSB 10
2538 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_WIDTH 11
2540 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_SET_MSK 0x000007ff
2542 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_CLR_MSK 0xfffff800
2544 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_RESET 0x0
2546 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
2548 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
2573 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_MAIN 0x0
2578 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_PERI 0x1
2583 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_OSC1 0x2
2588 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_INTOSC 0x3
2593 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_FPGA 0x4
2596 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_LSB 16
2598 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_MSB 18
2600 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_WIDTH 3
2602 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_SET_MSK 0x00070000
2604 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_CLR_MSK 0xfff8ffff
2606 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_RESET 0x1
2608 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
2610 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
2612 #ifndef __ASSEMBLY__
2624 struct ALT_CLKMGR_PERPLL_CNTR8CLK_s
2626 volatile uint32_t cnt : 11;
2628 volatile uint32_t src : 3;
2633 typedef struct ALT_CLKMGR_PERPLL_CNTR8CLK_s ALT_CLKMGR_PERPLL_CNTR8CLK_t;
2637 #define ALT_CLKMGR_PERPLL_CNTR8CLK_RESET 0x00010000
2639 #define ALT_CLKMGR_PERPLL_CNTR8CLK_OFST 0x30
2666 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_LSB 0
2668 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_MSB 10
2670 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_WIDTH 11
2672 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_SET_MSK 0x000007ff
2674 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_CLR_MSK 0xfffff800
2676 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_RESET 0x0
2678 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
2680 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
2705 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_E_MAIN 0x0
2710 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_E_PERI 0x1
2715 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_E_OSC1 0x2
2720 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_E_INTOSC 0x3
2725 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_E_FPGA 0x4
2728 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_LSB 16
2730 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_MSB 18
2732 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_WIDTH 3
2734 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_SET_MSK 0x00070000
2736 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_CLR_MSK 0xfff8ffff
2738 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_RESET 0x1
2740 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
2742 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
2744 #ifndef __ASSEMBLY__
2756 struct ALT_CLKMGR_PERPLL_CNTR9CLK_s
2758 volatile uint32_t cnt : 11;
2760 volatile uint32_t src : 3;
2765 typedef struct ALT_CLKMGR_PERPLL_CNTR9CLK_s ALT_CLKMGR_PERPLL_CNTR9CLK_t;
2769 #define ALT_CLKMGR_PERPLL_CNTR9CLK_RESET 0x00010000
2771 #define ALT_CLKMGR_PERPLL_CNTR9CLK_OFST 0x34
2810 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_E_EMACA 0x0
2816 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_E_EMACB 0x1
2819 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB 26
2821 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_MSB 26
2823 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_WIDTH 1
2825 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_SET_MSK 0x04000000
2827 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_CLR_MSK 0xfbffffff
2829 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_RESET 0x0
2831 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_GET(value) (((value) & 0x04000000) >> 26)
2833 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_SET(value) (((value) << 26) & 0x04000000)
2855 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_E_EMACA 0x0
2861 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_E_EMACB 0x1
2864 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB 27
2866 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_MSB 27
2868 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_WIDTH 1
2870 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_SET_MSK 0x08000000
2872 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_CLR_MSK 0xf7ffffff
2874 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_RESET 0x0
2876 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_GET(value) (((value) & 0x08000000) >> 27)
2878 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_SET(value) (((value) << 27) & 0x08000000)
2900 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_E_EMACA 0x0
2906 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_E_EMACB 0x1
2909 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB 28
2911 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_MSB 28
2913 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_WIDTH 1
2915 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_SET_MSK 0x10000000
2917 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_CLR_MSK 0xefffffff
2919 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_RESET 0x0
2921 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_GET(value) (((value) & 0x10000000) >> 28)
2923 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_SET(value) (((value) << 28) & 0x10000000)
2925 #ifndef __ASSEMBLY__
2937 struct ALT_CLKMGR_PERPLL_EMACCTL_s
2940 volatile uint32_t emac0sel : 1;
2941 volatile uint32_t emac1sel : 1;
2942 volatile uint32_t emac2sel : 1;
2947 typedef struct ALT_CLKMGR_PERPLL_EMACCTL_s ALT_CLKMGR_PERPLL_EMACCTL_t;
2951 #define ALT_CLKMGR_PERPLL_EMACCTL_RESET 0x00000000
2953 #define ALT_CLKMGR_PERPLL_EMACCTL_OFST 0x38
2979 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB 0
2981 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_MSB 15
2983 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_WIDTH 16
2985 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK 0x0000ffff
2987 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_CLR_MSK 0xffff0000
2989 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_RESET 0x1
2991 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET(value) (((value) & 0x0000ffff) >> 0)
2993 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(value) (((value) << 0) & 0x0000ffff)
2995 #ifndef __ASSEMBLY__
3007 struct ALT_CLKMGR_PERPLL_GPIODIV_s
3009 volatile uint32_t gpiodbclk : 16;
3014 typedef struct ALT_CLKMGR_PERPLL_GPIODIV_s ALT_CLKMGR_PERPLL_GPIODIV_t;
3018 #define ALT_CLKMGR_PERPLL_GPIODIV_RESET 0x00000001
3020 #define ALT_CLKMGR_PERPLL_GPIODIV_OFST 0x3c
3069 #define ALT_CLKMGR_PERPLL_PLLGLOB_PD_E_POWERDOWN 0x0
3074 #define ALT_CLKMGR_PERPLL_PLLGLOB_PD_E_POWERUP 0x1
3077 #define ALT_CLKMGR_PERPLL_PLLGLOB_PD_LSB 0
3079 #define ALT_CLKMGR_PERPLL_PLLGLOB_PD_MSB 0
3081 #define ALT_CLKMGR_PERPLL_PLLGLOB_PD_WIDTH 1
3083 #define ALT_CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK 0x00000001
3085 #define ALT_CLKMGR_PERPLL_PLLGLOB_PD_CLR_MSK 0xfffffffe
3087 #define ALT_CLKMGR_PERPLL_PLLGLOB_PD_RESET 0x0
3089 #define ALT_CLKMGR_PERPLL_PLLGLOB_PD_GET(value) (((value) & 0x00000001) >> 0)
3091 #define ALT_CLKMGR_PERPLL_PLLGLOB_PD_SET(value) (((value) << 0) & 0x00000001)
3110 #define ALT_CLKMGR_PERPLL_PLLGLOB_RST_LSB 1
3112 #define ALT_CLKMGR_PERPLL_PLLGLOB_RST_MSB 1
3114 #define ALT_CLKMGR_PERPLL_PLLGLOB_RST_WIDTH 1
3116 #define ALT_CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK 0x00000002
3118 #define ALT_CLKMGR_PERPLL_PLLGLOB_RST_CLR_MSK 0xfffffffd
3120 #define ALT_CLKMGR_PERPLL_PLLGLOB_RST_RESET 0x0
3122 #define ALT_CLKMGR_PERPLL_PLLGLOB_RST_GET(value) (((value) & 0x00000002) >> 1)
3124 #define ALT_CLKMGR_PERPLL_PLLGLOB_RST_SET(value) (((value) << 1) & 0x00000002)
3149 #define ALT_CLKMGR_PERPLL_PLLGLOB_MUTE_E_UNMUTE 0x0
3154 #define ALT_CLKMGR_PERPLL_PLLGLOB_MUTE_E_MUTE 0x1
3157 #define ALT_CLKMGR_PERPLL_PLLGLOB_MUTE_LSB 2
3159 #define ALT_CLKMGR_PERPLL_PLLGLOB_MUTE_MSB 2
3161 #define ALT_CLKMGR_PERPLL_PLLGLOB_MUTE_WIDTH 1
3163 #define ALT_CLKMGR_PERPLL_PLLGLOB_MUTE_SET_MSK 0x00000004
3165 #define ALT_CLKMGR_PERPLL_PLLGLOB_MUTE_CLR_MSK 0xfffffffb
3167 #define ALT_CLKMGR_PERPLL_PLLGLOB_MUTE_RESET 0x0
3169 #define ALT_CLKMGR_PERPLL_PLLGLOB_MUTE_GET(value) (((value) & 0x00000004) >> 2)
3171 #define ALT_CLKMGR_PERPLL_PLLGLOB_MUTE_SET(value) (((value) << 2) & 0x00000004)
3198 #define ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL_E_INT 0x0
3203 #define ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL_E_FLOAT 0x1
3206 #define ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL_LSB 3
3208 #define ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL_MSB 3
3210 #define ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL_WIDTH 1
3212 #define ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL_SET_MSK 0x00000008
3214 #define ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL_CLR_MSK 0xfffffff7
3216 #define ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL_RESET 0x0
3218 #define ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL_GET(value) (((value) & 0x00000008) >> 3)
3220 #define ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL_SET(value) (((value) << 3) & 0x00000008)
3236 #define ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL_LSB 4
3238 #define ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL_MSB 4
3240 #define ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL_WIDTH 1
3242 #define ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL_SET_MSK 0x00000010
3244 #define ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL_CLR_MSK 0xffffffef
3246 #define ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL_RESET 0x0
3248 #define ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL_GET(value) (((value) & 0x00000010) >> 4)
3250 #define ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL_SET(value) (((value) << 4) & 0x00000010)
3271 #define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV_LSB 8
3273 #define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV_MSB 13
3275 #define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV_WIDTH 6
3277 #define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV_SET_MSK 0x00003f00
3279 #define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV_CLR_MSK 0xffffc0ff
3281 #define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV_RESET 0x1
3283 #define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV_GET(value) (((value) & 0x00003f00) >> 8)
3285 #define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV_SET(value) (((value) << 8) & 0x00003f00)
3308 #define ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_E_EOSC1 0x0
3314 #define ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_E_INTOSC 0x1
3320 #define ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_E_F2S 0x2
3323 #define ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_LSB 16
3325 #define ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_MSB 17
3327 #define ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_WIDTH 2
3329 #define ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_SET_MSK 0x00030000
3331 #define ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_CLR_MSK 0xfffcffff
3333 #define ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_RESET 0x0
3335 #define ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_GET(value) (((value) & 0x00030000) >> 16)
3337 #define ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_SET(value) (((value) << 16) & 0x00030000)
3339 #ifndef __ASSEMBLY__
3351 struct ALT_CLKMGR_PERPLL_PLLGLOB_s
3353 volatile uint32_t pd : 1;
3354 volatile uint32_t rst : 1;
3355 volatile uint32_t mute : 1;
3356 volatile uint32_t modsel : 1;
3357 volatile uint32_t bysctl : 1;
3359 volatile uint32_t refclkdiv : 6;
3361 volatile uint32_t psrc : 2;
3366 typedef struct ALT_CLKMGR_PERPLL_PLLGLOB_s ALT_CLKMGR_PERPLL_PLLGLOB_t;
3370 #define ALT_CLKMGR_PERPLL_PLLGLOB_RESET 0x00000100
3372 #define ALT_CLKMGR_PERPLL_PLLGLOB_OFST 0x40
3408 #define ALT_CLKMGR_PERPLL_FDBCK_FDIV_LSB 0
3410 #define ALT_CLKMGR_PERPLL_FDBCK_FDIV_MSB 23
3412 #define ALT_CLKMGR_PERPLL_FDBCK_FDIV_WIDTH 24
3414 #define ALT_CLKMGR_PERPLL_FDBCK_FDIV_SET_MSK 0x00ffffff
3416 #define ALT_CLKMGR_PERPLL_FDBCK_FDIV_CLR_MSK 0xff000000
3418 #define ALT_CLKMGR_PERPLL_FDBCK_FDIV_RESET 0x0
3420 #define ALT_CLKMGR_PERPLL_FDBCK_FDIV_GET(value) (((value) & 0x00ffffff) >> 0)
3422 #define ALT_CLKMGR_PERPLL_FDBCK_FDIV_SET(value) (((value) << 0) & 0x00ffffff)
3446 #define ALT_CLKMGR_PERPLL_FDBCK_MDIV_LSB 24
3448 #define ALT_CLKMGR_PERPLL_FDBCK_MDIV_MSB 31
3450 #define ALT_CLKMGR_PERPLL_FDBCK_MDIV_WIDTH 8
3452 #define ALT_CLKMGR_PERPLL_FDBCK_MDIV_SET_MSK 0xff000000
3454 #define ALT_CLKMGR_PERPLL_FDBCK_MDIV_CLR_MSK 0x00ffffff
3456 #define ALT_CLKMGR_PERPLL_FDBCK_MDIV_RESET 0x22
3458 #define ALT_CLKMGR_PERPLL_FDBCK_MDIV_GET(value) (((value) & 0xff000000) >> 24)
3460 #define ALT_CLKMGR_PERPLL_FDBCK_MDIV_SET(value) (((value) << 24) & 0xff000000)
3462 #ifndef __ASSEMBLY__
3474 struct ALT_CLKMGR_PERPLL_FDBCK_s
3476 volatile uint32_t fdiv : 24;
3477 volatile uint32_t mdiv : 8;
3481 typedef struct ALT_CLKMGR_PERPLL_FDBCK_s ALT_CLKMGR_PERPLL_FDBCK_t;
3485 #define ALT_CLKMGR_PERPLL_FDBCK_RESET 0x22000000
3487 #define ALT_CLKMGR_PERPLL_FDBCK_OFST 0x44
3515 #define ALT_CLKMGR_PERPLL_MEM_ADDR_LSB 0
3517 #define ALT_CLKMGR_PERPLL_MEM_ADDR_MSB 9
3519 #define ALT_CLKMGR_PERPLL_MEM_ADDR_WIDTH 10
3521 #define ALT_CLKMGR_PERPLL_MEM_ADDR_SET_MSK 0x000003ff
3523 #define ALT_CLKMGR_PERPLL_MEM_ADDR_CLR_MSK 0xfffffc00
3525 #define ALT_CLKMGR_PERPLL_MEM_ADDR_RESET 0x0
3527 #define ALT_CLKMGR_PERPLL_MEM_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
3529 #define ALT_CLKMGR_PERPLL_MEM_ADDR_SET(value) (((value) << 0) & 0x000003ff)
3540 #define ALT_CLKMGR_PERPLL_MEM_WDAT_LSB 16
3542 #define ALT_CLKMGR_PERPLL_MEM_WDAT_MSB 23
3544 #define ALT_CLKMGR_PERPLL_MEM_WDAT_WIDTH 8
3546 #define ALT_CLKMGR_PERPLL_MEM_WDAT_SET_MSK 0x00ff0000
3548 #define ALT_CLKMGR_PERPLL_MEM_WDAT_CLR_MSK 0xff00ffff
3550 #define ALT_CLKMGR_PERPLL_MEM_WDAT_RESET 0x0
3552 #define ALT_CLKMGR_PERPLL_MEM_WDAT_GET(value) (((value) & 0x00ff0000) >> 16)
3554 #define ALT_CLKMGR_PERPLL_MEM_WDAT_SET(value) (((value) << 16) & 0x00ff0000)
3565 #define ALT_CLKMGR_PERPLL_MEM_REQ_LSB 24
3567 #define ALT_CLKMGR_PERPLL_MEM_REQ_MSB 24
3569 #define ALT_CLKMGR_PERPLL_MEM_REQ_WIDTH 1
3571 #define ALT_CLKMGR_PERPLL_MEM_REQ_SET_MSK 0x01000000
3573 #define ALT_CLKMGR_PERPLL_MEM_REQ_CLR_MSK 0xfeffffff
3575 #define ALT_CLKMGR_PERPLL_MEM_REQ_RESET 0x0
3577 #define ALT_CLKMGR_PERPLL_MEM_REQ_GET(value) (((value) & 0x01000000) >> 24)
3579 #define ALT_CLKMGR_PERPLL_MEM_REQ_SET(value) (((value) << 24) & 0x01000000)
3601 #define ALT_CLKMGR_PERPLL_MEM_WR_E_READ 0x0
3606 #define ALT_CLKMGR_PERPLL_MEM_WR_E_WRITE 0x1
3609 #define ALT_CLKMGR_PERPLL_MEM_WR_LSB 25
3611 #define ALT_CLKMGR_PERPLL_MEM_WR_MSB 25
3613 #define ALT_CLKMGR_PERPLL_MEM_WR_WIDTH 1
3615 #define ALT_CLKMGR_PERPLL_MEM_WR_SET_MSK 0x02000000
3617 #define ALT_CLKMGR_PERPLL_MEM_WR_CLR_MSK 0xfdffffff
3619 #define ALT_CLKMGR_PERPLL_MEM_WR_RESET 0x0
3621 #define ALT_CLKMGR_PERPLL_MEM_WR_GET(value) (((value) & 0x02000000) >> 25)
3623 #define ALT_CLKMGR_PERPLL_MEM_WR_SET(value) (((value) << 25) & 0x02000000)
3625 #ifndef __ASSEMBLY__
3637 struct ALT_CLKMGR_PERPLL_MEM_s
3639 volatile uint32_t addr : 10;
3641 volatile uint32_t wdat : 8;
3642 volatile uint32_t req : 1;
3643 volatile uint32_t wr : 1;
3648 typedef struct ALT_CLKMGR_PERPLL_MEM_s ALT_CLKMGR_PERPLL_MEM_t;
3652 #define ALT_CLKMGR_PERPLL_MEM_RESET 0x00000000
3654 #define ALT_CLKMGR_PERPLL_MEM_OFST 0x48
3678 #define ALT_CLKMGR_PERPLL_MEMSTAT_RDATA_LSB 0
3680 #define ALT_CLKMGR_PERPLL_MEMSTAT_RDATA_MSB 7
3682 #define ALT_CLKMGR_PERPLL_MEMSTAT_RDATA_WIDTH 8
3684 #define ALT_CLKMGR_PERPLL_MEMSTAT_RDATA_SET_MSK 0x000000ff
3686 #define ALT_CLKMGR_PERPLL_MEMSTAT_RDATA_CLR_MSK 0xffffff00
3688 #define ALT_CLKMGR_PERPLL_MEMSTAT_RDATA_RESET 0x0
3690 #define ALT_CLKMGR_PERPLL_MEMSTAT_RDATA_GET(value) (((value) & 0x000000ff) >> 0)
3692 #define ALT_CLKMGR_PERPLL_MEMSTAT_RDATA_SET(value) (((value) << 0) & 0x000000ff)
3694 #ifndef __ASSEMBLY__
3706 struct ALT_CLKMGR_PERPLL_MEMSTAT_s
3708 const volatile uint32_t rdata : 8;
3713 typedef struct ALT_CLKMGR_PERPLL_MEMSTAT_s ALT_CLKMGR_PERPLL_MEMSTAT_t;
3717 #define ALT_CLKMGR_PERPLL_MEMSTAT_RESET 0x00000000
3719 #define ALT_CLKMGR_PERPLL_MEMSTAT_OFST 0x4c
3750 #define ALT_CLKMGR_PERPLL_PLLC0_DIV_LSB 0
3752 #define ALT_CLKMGR_PERPLL_PLLC0_DIV_MSB 7
3754 #define ALT_CLKMGR_PERPLL_PLLC0_DIV_WIDTH 8
3756 #define ALT_CLKMGR_PERPLL_PLLC0_DIV_SET_MSK 0x000000ff
3758 #define ALT_CLKMGR_PERPLL_PLLC0_DIV_CLR_MSK 0xffffff00
3760 #define ALT_CLKMGR_PERPLL_PLLC0_DIV_RESET 0x2
3762 #define ALT_CLKMGR_PERPLL_PLLC0_DIV_GET(value) (((value) & 0x000000ff) >> 0)
3764 #define ALT_CLKMGR_PERPLL_PLLC0_DIV_SET(value) (((value) << 0) & 0x000000ff)
3786 #define ALT_CLKMGR_PERPLL_PLLC0_PHINC_E_UNPUSH 0x0
3791 #define ALT_CLKMGR_PERPLL_PLLC0_PHINC_E_PUSH 0x1
3794 #define ALT_CLKMGR_PERPLL_PLLC0_PHINC_LSB 24
3796 #define ALT_CLKMGR_PERPLL_PLLC0_PHINC_MSB 24
3798 #define ALT_CLKMGR_PERPLL_PLLC0_PHINC_WIDTH 1
3800 #define ALT_CLKMGR_PERPLL_PLLC0_PHINC_SET_MSK 0x01000000
3802 #define ALT_CLKMGR_PERPLL_PLLC0_PHINC_CLR_MSK 0xfeffffff
3804 #define ALT_CLKMGR_PERPLL_PLLC0_PHINC_RESET 0x0
3806 #define ALT_CLKMGR_PERPLL_PLLC0_PHINC_GET(value) (((value) & 0x01000000) >> 24)
3808 #define ALT_CLKMGR_PERPLL_PLLC0_PHINC_SET(value) (((value) << 24) & 0x01000000)
3830 #define ALT_CLKMGR_PERPLL_PLLC0_PHRST_E_RSTDEASSERT 0x0
3835 #define ALT_CLKMGR_PERPLL_PLLC0_PHRST_E_RSTASSERT 0x1
3838 #define ALT_CLKMGR_PERPLL_PLLC0_PHRST_LSB 25
3840 #define ALT_CLKMGR_PERPLL_PLLC0_PHRST_MSB 25
3842 #define ALT_CLKMGR_PERPLL_PLLC0_PHRST_WIDTH 1
3844 #define ALT_CLKMGR_PERPLL_PLLC0_PHRST_SET_MSK 0x02000000
3846 #define ALT_CLKMGR_PERPLL_PLLC0_PHRST_CLR_MSK 0xfdffffff
3848 #define ALT_CLKMGR_PERPLL_PLLC0_PHRST_RESET 0x0
3850 #define ALT_CLKMGR_PERPLL_PLLC0_PHRST_GET(value) (((value) & 0x02000000) >> 25)
3852 #define ALT_CLKMGR_PERPLL_PLLC0_PHRST_SET(value) (((value) << 25) & 0x02000000)
3874 #define ALT_CLKMGR_PERPLL_PLLC0_BYPAS_E_UNBYPASS 0x0
3879 #define ALT_CLKMGR_PERPLL_PLLC0_BYPAS_E_BYPASS 0x1
3882 #define ALT_CLKMGR_PERPLL_PLLC0_BYPAS_LSB 26
3884 #define ALT_CLKMGR_PERPLL_PLLC0_BYPAS_MSB 26
3886 #define ALT_CLKMGR_PERPLL_PLLC0_BYPAS_WIDTH 1
3888 #define ALT_CLKMGR_PERPLL_PLLC0_BYPAS_SET_MSK 0x04000000
3890 #define ALT_CLKMGR_PERPLL_PLLC0_BYPAS_CLR_MSK 0xfbffffff
3892 #define ALT_CLKMGR_PERPLL_PLLC0_BYPAS_RESET 0x0
3894 #define ALT_CLKMGR_PERPLL_PLLC0_BYPAS_GET(value) (((value) & 0x04000000) >> 26)
3896 #define ALT_CLKMGR_PERPLL_PLLC0_BYPAS_SET(value) (((value) << 26) & 0x04000000)
3919 #define ALT_CLKMGR_PERPLL_PLLC0_EN_E_DISABLE 0x0
3924 #define ALT_CLKMGR_PERPLL_PLLC0_EN_E_ENABLE 0x1
3927 #define ALT_CLKMGR_PERPLL_PLLC0_EN_LSB 27
3929 #define ALT_CLKMGR_PERPLL_PLLC0_EN_MSB 27
3931 #define ALT_CLKMGR_PERPLL_PLLC0_EN_WIDTH 1
3933 #define ALT_CLKMGR_PERPLL_PLLC0_EN_SET_MSK 0x08000000
3935 #define ALT_CLKMGR_PERPLL_PLLC0_EN_CLR_MSK 0xf7ffffff
3937 #define ALT_CLKMGR_PERPLL_PLLC0_EN_RESET 0x1
3939 #define ALT_CLKMGR_PERPLL_PLLC0_EN_GET(value) (((value) & 0x08000000) >> 27)
3941 #define ALT_CLKMGR_PERPLL_PLLC0_EN_SET(value) (((value) << 27) & 0x08000000)
3943 #ifndef __ASSEMBLY__
3955 struct ALT_CLKMGR_PERPLL_PLLC0_s
3957 volatile uint32_t div : 8;
3959 volatile uint32_t phinc : 1;
3960 volatile uint32_t phrst : 1;
3961 volatile uint32_t bypas : 1;
3962 volatile uint32_t en : 1;
3967 typedef struct ALT_CLKMGR_PERPLL_PLLC0_s ALT_CLKMGR_PERPLL_PLLC0_t;
3971 #define ALT_CLKMGR_PERPLL_PLLC0_RESET 0x08000002
3973 #define ALT_CLKMGR_PERPLL_PLLC0_OFST 0x50
4004 #define ALT_CLKMGR_PERPLL_PLLC1_DIV_LSB 0
4006 #define ALT_CLKMGR_PERPLL_PLLC1_DIV_MSB 7
4008 #define ALT_CLKMGR_PERPLL_PLLC1_DIV_WIDTH 8
4010 #define ALT_CLKMGR_PERPLL_PLLC1_DIV_SET_MSK 0x000000ff
4012 #define ALT_CLKMGR_PERPLL_PLLC1_DIV_CLR_MSK 0xffffff00
4014 #define ALT_CLKMGR_PERPLL_PLLC1_DIV_RESET 0x4
4016 #define ALT_CLKMGR_PERPLL_PLLC1_DIV_GET(value) (((value) & 0x000000ff) >> 0)
4018 #define ALT_CLKMGR_PERPLL_PLLC1_DIV_SET(value) (((value) << 0) & 0x000000ff)
4041 #define ALT_CLKMGR_PERPLL_PLLC1_EN_E_DISABLE 0x0
4046 #define ALT_CLKMGR_PERPLL_PLLC1_EN_E_ENABLE 0x1
4049 #define ALT_CLKMGR_PERPLL_PLLC1_EN_LSB 24
4051 #define ALT_CLKMGR_PERPLL_PLLC1_EN_MSB 24
4053 #define ALT_CLKMGR_PERPLL_PLLC1_EN_WIDTH 1
4055 #define ALT_CLKMGR_PERPLL_PLLC1_EN_SET_MSK 0x01000000
4057 #define ALT_CLKMGR_PERPLL_PLLC1_EN_CLR_MSK 0xfeffffff
4059 #define ALT_CLKMGR_PERPLL_PLLC1_EN_RESET 0x1
4061 #define ALT_CLKMGR_PERPLL_PLLC1_EN_GET(value) (((value) & 0x01000000) >> 24)
4063 #define ALT_CLKMGR_PERPLL_PLLC1_EN_SET(value) (((value) << 24) & 0x01000000)
4085 #define ALT_CLKMGR_PERPLL_PLLC1_BYPAS_E_UNBYPASS 0x0
4090 #define ALT_CLKMGR_PERPLL_PLLC1_BYPAS_E_BYPASS 0x1
4093 #define ALT_CLKMGR_PERPLL_PLLC1_BYPAS_LSB 25
4095 #define ALT_CLKMGR_PERPLL_PLLC1_BYPAS_MSB 25
4097 #define ALT_CLKMGR_PERPLL_PLLC1_BYPAS_WIDTH 1
4099 #define ALT_CLKMGR_PERPLL_PLLC1_BYPAS_SET_MSK 0x02000000
4101 #define ALT_CLKMGR_PERPLL_PLLC1_BYPAS_CLR_MSK 0xfdffffff
4103 #define ALT_CLKMGR_PERPLL_PLLC1_BYPAS_RESET 0x0
4105 #define ALT_CLKMGR_PERPLL_PLLC1_BYPAS_GET(value) (((value) & 0x02000000) >> 25)
4107 #define ALT_CLKMGR_PERPLL_PLLC1_BYPAS_SET(value) (((value) << 25) & 0x02000000)
4129 #define ALT_CLKMGR_PERPLL_PLLC1_PHINC_E_UNPUSH 0x0
4134 #define ALT_CLKMGR_PERPLL_PLLC1_PHINC_E_PUSH 0x1
4137 #define ALT_CLKMGR_PERPLL_PLLC1_PHINC_LSB 26
4139 #define ALT_CLKMGR_PERPLL_PLLC1_PHINC_MSB 26
4141 #define ALT_CLKMGR_PERPLL_PLLC1_PHINC_WIDTH 1
4143 #define ALT_CLKMGR_PERPLL_PLLC1_PHINC_SET_MSK 0x04000000
4145 #define ALT_CLKMGR_PERPLL_PLLC1_PHINC_CLR_MSK 0xfbffffff
4147 #define ALT_CLKMGR_PERPLL_PLLC1_PHINC_RESET 0x0
4149 #define ALT_CLKMGR_PERPLL_PLLC1_PHINC_GET(value) (((value) & 0x04000000) >> 26)
4151 #define ALT_CLKMGR_PERPLL_PLLC1_PHINC_SET(value) (((value) << 26) & 0x04000000)
4173 #define ALT_CLKMGR_PERPLL_PLLC1_PHRST_E_RSTDEASSERT 0x0
4178 #define ALT_CLKMGR_PERPLL_PLLC1_PHRST_E_RSTASSERT 0x1
4181 #define ALT_CLKMGR_PERPLL_PLLC1_PHRST_LSB 27
4183 #define ALT_CLKMGR_PERPLL_PLLC1_PHRST_MSB 27
4185 #define ALT_CLKMGR_PERPLL_PLLC1_PHRST_WIDTH 1
4187 #define ALT_CLKMGR_PERPLL_PLLC1_PHRST_SET_MSK 0x08000000
4189 #define ALT_CLKMGR_PERPLL_PLLC1_PHRST_CLR_MSK 0xf7ffffff
4191 #define ALT_CLKMGR_PERPLL_PLLC1_PHRST_RESET 0x0
4193 #define ALT_CLKMGR_PERPLL_PLLC1_PHRST_GET(value) (((value) & 0x08000000) >> 27)
4195 #define ALT_CLKMGR_PERPLL_PLLC1_PHRST_SET(value) (((value) << 27) & 0x08000000)
4197 #ifndef __ASSEMBLY__
4209 struct ALT_CLKMGR_PERPLL_PLLC1_s
4211 volatile uint32_t div : 8;
4213 volatile uint32_t en : 1;
4214 volatile uint32_t bypas : 1;
4215 volatile uint32_t phinc : 1;
4216 volatile uint32_t phrst : 1;
4221 typedef struct ALT_CLKMGR_PERPLL_PLLC1_s ALT_CLKMGR_PERPLL_PLLC1_t;
4225 #define ALT_CLKMGR_PERPLL_PLLC1_RESET 0x01000004
4227 #define ALT_CLKMGR_PERPLL_PLLC1_OFST 0x54
4261 #define ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_LSB 0
4263 #define ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_MSB 7
4265 #define ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_WIDTH 8
4267 #define ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_SET_MSK 0x000000ff
4269 #define ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_CLR_MSK 0xffffff00
4271 #define ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_RESET 0xbf
4273 #define ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_GET(value) (((value) & 0x000000ff) >> 0)
4275 #define ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_SET(value) (((value) << 0) & 0x000000ff)
4290 #define ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_LSB 9
4292 #define ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_MSB 16
4294 #define ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_WIDTH 8
4296 #define ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_SET_MSK 0x0001fe00
4298 #define ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_CLR_MSK 0xfffe01ff
4300 #define ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_RESET 0x5
4302 #define ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_GET(value) (((value) & 0x0001fe00) >> 9)
4304 #define ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_SET(value) (((value) << 9) & 0x0001fe00)
4315 #define ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN_LSB 23
4317 #define ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN_MSB 24
4319 #define ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN_WIDTH 2
4321 #define ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN_SET_MSK 0x01800000
4323 #define ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN_CLR_MSK 0xfe7fffff
4325 #define ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN_RESET 0x0
4327 #define ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN_GET(value) (((value) & 0x01800000) >> 23)
4329 #define ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN_SET(value) (((value) << 23) & 0x01800000)
4331 #ifndef __ASSEMBLY__
4343 struct ALT_CLKMGR_PERPLL_VCOCALIB_s
4345 volatile uint32_t hscnt : 8;
4347 volatile uint32_t mscnt : 8;
4349 volatile uint32_t termin : 2;
4354 typedef struct ALT_CLKMGR_PERPLL_VCOCALIB_s ALT_CLKMGR_PERPLL_VCOCALIB_t;
4358 #define ALT_CLKMGR_PERPLL_VCOCALIB_RESET 0x00000abf
4360 #define ALT_CLKMGR_PERPLL_VCOCALIB_OFST 0x58
4362 #ifndef __ASSEMBLY__
4374 struct ALT_CLKMGR_PERPLL_s
4376 volatile ALT_CLKMGR_PERPLL_EN_t en;
4377 volatile ALT_CLKMGR_PERPLL_ENS_t ens;
4378 volatile ALT_CLKMGR_PERPLL_ENR_t enr;
4379 volatile ALT_CLKMGR_PERPLL_BYPASS_t bypass;
4380 volatile ALT_CLKMGR_PERPLL_BYPASSS_t bypasss;
4381 volatile ALT_CLKMGR_PERPLL_BYPASSR_t bypassr;
4382 volatile ALT_CLKMGR_PERPLL_CNTR2CLK_t cntr2clk;
4383 volatile ALT_CLKMGR_PERPLL_CNTR3CLK_t cntr3clk;
4384 volatile ALT_CLKMGR_PERPLL_CNTR4CLK_t cntr4clk;
4385 volatile ALT_CLKMGR_PERPLL_CNTR5CLK_t cntr5clk;
4386 volatile ALT_CLKMGR_PERPLL_CNTR6CLK_t cntr6clk;
4387 volatile ALT_CLKMGR_PERPLL_CNTR7CLK_t cntr7clk;
4388 volatile ALT_CLKMGR_PERPLL_CNTR8CLK_t cntr8clk;
4389 volatile ALT_CLKMGR_PERPLL_CNTR9CLK_t cntr9clk;
4390 volatile ALT_CLKMGR_PERPLL_EMACCTL_t emacctl;
4391 volatile ALT_CLKMGR_PERPLL_GPIODIV_t gpiodiv;
4392 volatile ALT_CLKMGR_PERPLL_PLLGLOB_t pllglob;
4393 volatile ALT_CLKMGR_PERPLL_FDBCK_t fdbck;
4394 volatile ALT_CLKMGR_PERPLL_MEM_t mem;
4395 volatile ALT_CLKMGR_PERPLL_MEMSTAT_t memstat;
4396 volatile ALT_CLKMGR_PERPLL_PLLC0_t pllc0;
4397 volatile ALT_CLKMGR_PERPLL_PLLC1_t pllc1;
4398 volatile ALT_CLKMGR_PERPLL_VCOCALIB_t vcocalib;
4399 volatile uint32_t _pad_0x5c_0x80[9];
4403 typedef struct ALT_CLKMGR_PERPLL_s ALT_CLKMGR_PERPLL_t;
4405 struct ALT_CLKMGR_PERPLL_raw_s
4407 volatile uint32_t en;
4408 volatile uint32_t ens;
4409 volatile uint32_t enr;
4410 volatile uint32_t bypass;
4411 volatile uint32_t bypasss;
4412 volatile uint32_t bypassr;
4413 volatile uint32_t cntr2clk;
4414 volatile uint32_t cntr3clk;
4415 volatile uint32_t cntr4clk;
4416 volatile uint32_t cntr5clk;
4417 volatile uint32_t cntr6clk;
4418 volatile uint32_t cntr7clk;
4419 volatile uint32_t cntr8clk;
4420 volatile uint32_t cntr9clk;
4421 volatile uint32_t emacctl;
4422 volatile uint32_t gpiodiv;
4423 volatile uint32_t pllglob;
4424 volatile uint32_t fdbck;
4425 volatile uint32_t mem;
4426 volatile uint32_t memstat;
4427 volatile uint32_t pllc0;
4428 volatile uint32_t pllc1;
4429 volatile uint32_t vcocalib;
4430 volatile uint32_t _pad_0x5c_0x80[9];
4434 typedef struct ALT_CLKMGR_PERPLL_raw_s ALT_CLKMGR_PERPLL_raw_t;