Hardware Libraries  20.1
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alt_sdram.h
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32 
33 /*
34  * $Id: //acds/rel/20.1/embedded/ip/hps/altera_hps/hwlib/include/soc_a10/alt_sdram.h#1 $
35  */
36 
41 #ifndef __ALT_SDRAM_PRIORITY_H__
42 #define __ALT_SDRAM_PRIORITY_H__
43 
44 #include <stdint.h>
45 #include "alt_interrupt.h"
46 #include "socal/hps.h"
47 
48 
49 /*****************************************************************************/
62 typedef enum ALT_SDR_MODE_e
63 {
64  ALT_SDR_MODE_PROGRAMMABLE = 0,
65  ALT_SDR_MODE_BANDWIDTH_LIMITER = 1,
66  ALT_SDR_MODE_BYPASS = 2,
67  ALT_SDR_MODE_BANDWIDTH_REGULATOR = 3
69 
74 typedef enum ALT_SDR_PORT_e
75 {
76  ALT_SDR_PORT_MPU_M0 = 0,
77  ALT_SDR_PORT_MPU_M1 = 1,
78  ALT_SDR_PORT_FPGA2SOC32 = 2,
79  ALT_SDR_PORT_FPGA2SOC64 = 3,
80  ALT_SDR_PORT_FPGA2SOC128 = 4,
81  ALT_SDR_PORT_DMA = 5,
82  ALT_SDR_PORT_EMAC0 = 6,
83  ALT_SDR_PORT_EMAC1 = 7,
84  ALT_SDR_PORT_EMAC2 = 8,
85  ALT_SDR_PORT_USB0 = 9,
86  ALT_SDR_PORT_USB1 = 10,
87  ALT_SDR_PORT_NAND = 11,
88  ALT_SDR_PORT_SDMMC = 12,
89  ALT_SDR_PORT_FPGA2SDRAM0_32 = 13,
90  ALT_SDR_PORT_FPGA2SDRAM0_64 = 14,
91  ALT_SDR_PORT_FPGA2SDRAM0_128 = 15,
92  ALT_SDR_PORT_FPGA2SDRAM1_32 = 16,
93  ALT_SDR_PORT_FPGA2SDRAM1_64 = 17,
94  ALT_SDR_PORT_FPGA2SDRAM2_32 = 18,
95  ALT_SDR_PORT_FPGA2SDRAM2_64 = 19,
96  ALT_SDR_PORT_FPGA2SDRAM2_128 = 20
98 
104 typedef struct ALT_SDR_QOS_INFO_s
105 {
106  ALT_SDR_MODE_t Mode;
107  uint16_t Bandwidth;
108  uint16_t Saturation;
109  uint8_t ReadPriority; /* 0 (Lowest) to 3 (Highest). However, disabling the QOS gives highest priority */
110  uint8_t WritePriority; /* 0 (Lowest) to 3 (Highest). However, disabling the QOS gives highest priority */
111  bool Enabled;
112  bool ClkEn;
113  bool ExThrEn;
114 } __attribute__((aligned(4))) ALT_SDR_QOS_INFO_t;
115 
133 ALT_STATUS_CODE alt_sdr_port_qos_set(ALT_SDR_PORT_t port, ALT_SDR_QOS_INFO_t *qos);
134 
152 ALT_STATUS_CODE alt_sdr_port_qos_get(ALT_SDR_PORT_t port, ALT_SDR_QOS_INFO_t *qos);
153 
154 /******************************************************************************
155  Firewall API
156 ******************************************************************************/
157 
166 {
167  bool AHB_AP_Allow_NS_Access; /* 0- Secure Only, 1 N/S Allowed */
168  bool FPGA2SOC_Allow_NS_Access; /* 0- Secure Only, 1 N/S Allowed */
169  bool DMA_Allow_NS_Access; /* 0- Secure Only, 1 N/S Allowed */
170  bool MPU_M0_Allow_NS_Access; /* 0- Secure Only, 1 N/S Allowed */
172 
179 {
180  ALT_SDR_MEM_NAND_REGISTERS = 0,
181  ALT_SDR_MEM_NAND_DATA = 1,
182  ALT_SDR_MEM_QSPI_DATA = 2,
183  ALT_SDR_MEM_USB0_REGISTERS = 3,
184  ALT_SDR_MEM_USB1_REGISTERS = 4,
185  ALT_SDR_MEM_SPI_MASTER0 = 7,
186  ALT_SDR_MEM_SPI_MASTER1 = 8,
187  ALT_SDR_MEM_SPI_SLAVE0 = 9,
188  ALT_SDR_MEM_SPI_SLAVE1 = 10,
189  ALT_SDR_MEM_EMAC0 = 11,
190  ALT_SDR_MEM_EMAC1 = 12,
191  ALT_SDR_MEM_EMAC2 = 13,
192  ALT_SDR_MEM_QSPI = 15,
193  ALT_SDR_MEM_SDMMC = 16,
194  ALT_SDR_MEM_GPIO0 = 17,
195  ALT_SDR_MEM_GPIO1 = 18,
196  ALT_SDR_MEM_GPIO2 = 19,
197  ALT_SDR_MEM_I2C0 = 20,
198  ALT_SDR_MEM_I2C1 = 21,
199  ALT_SDR_MEM_I2C2 = 22,
200  ALT_SDR_MEM_I2C3 = 23,
201  ALT_SDR_MEM_I2C4 = 24,
202  ALT_SDR_MEM_SP_TIMER0 = 25,
203  ALT_SDR_MEM_SP_TIMER1 = 26,
204  ALT_SDR_MEM_UART0 = 27,
205  ALT_SDR_MEM_UART1 = 28,
206 
207  ALT_SDR_MEM_CAN0_ECC = 64,
208  ALT_SDR_MEM_CAN1_ECC = 65,
209  ALT_SDR_MEM_DMA_ECC = 66,
210  ALT_SDR_MEM_EMAC0RX_ECC = 67,
211  ALT_SDR_MEM_EMAC0TX_ECC = 68,
212  ALT_SDR_MEM_EMAC1RX_ECC = 69,
213  ALT_SDR_MEM_EMAC1TX_ECC = 70,
214  ALT_SDR_MEM_EMAC2RX_ECC = 71,
215  ALT_SDR_MEM_EMAC2TX_ECC = 72,
216  ALT_SDR_MEM_EMAC3RX_ECC = 73,
217  ALT_SDR_MEM_EMAC3TX_ECC = 74,
218  ALT_SDR_MEM_NAND_ECC = 75,
219  ALT_SDR_MEM_NAND_READ_ECC = 76,
220  ALT_SDR_MEM_NAND_WRITE_ECC = 77,
221  ALT_SDR_MEM_ONCHIPRAM_ECC = 78,
222  ALT_SDR_MEM_QSPI_ECC = 79,
223  ALT_SDR_MEM_SDMMC_ECC = 80,
224  ALT_SDR_MEM_USB0_ECC = 81,
225  ALT_SDR_MEM_USB1_ECC = 82,
226  ALT_SDR_MEM_CLOCK_MGR = 83,
227  ALT_SDR_MEM_FPGA_MGR = 84,
228  ALT_SDR_MEM_PIN_MUX = 85,
229  ALT_SDR_MEM_RESET_MGR = 86,
230  ALT_SDR_MEM_SYSTEM_MGR = 87,
231  ALT_SDR_MEM_OSC0 = 88,
232  ALT_SDR_MEM_OSC1 = 89,
233  ALT_SDR_MEM_WATCHDOG0 = 90,
234  ALT_SDR_MEM_WATCHDOG1 = 91,
235  ALT_SDR_MEM_DAP = 92,
236  ALT_SDR_MEM_FPGA_MGR_STREAM= 93,
237  ALT_SDR_MEM_SEC_MGR_STREAM = 94,
238  ALT_SDR_MEM_HMC = 95,
239  ALT_SDR_MEM_HMC_ADAPTOR = 96,
240  ALT_SDR_MEM_L3_INTCON = 97,
241  ALT_SDR_MEM_DDR_SCHEDULER = 98,
242  ALT_SDR_MEM_L4_INTCON_FW = 99,
243  ALT_SDR_MEM_L4_INTCON_PROBES= 100,
244  ALT_SDR_MEM_L4_QOS_CSR = 101
246 
264 
282 
285 #endif