Hardware Libraries  20.1
Arria 10 SoC Abstration Layer
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alt_noc_fw_ddr_l3_scr.h
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32 
33 /* Altera - ALT_NOC_FW_DDR_L3_SCR */
34 
35 #ifndef __ALT_SOCAL_NOC_FW_DDR_L3_SCR_H__
36 #define __ALT_SOCAL_NOC_FW_DDR_L3_SCR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_NOC_FW_DDR_L3_SCR
50  *
51  */
52 /*
53  * Register : enable
54  *
55  * Enable
56  *
57  * Register Layout
58  *
59  * Bits | Access | Reset | Description
60  * :-------|:-------|:------|:-----------------------------------
61  * [0] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN
62  * [1] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN
63  * [2] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN
64  * [3] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN
65  * [4] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN
66  * [5] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN
67  * [6] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN
68  * [7] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN
69  * [31:8] | ??? | 0x0 | *UNDEFINED*
70  *
71  */
72 /*
73  * Field : hpsregion0enable
74  *
75  * HPS Region 0 Enable. Value of 1 means region is enabled, Value of 0 means region
76  * is disabled.
77  *
78  * Field Access Macros:
79  *
80  */
81 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN register field. */
82 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_LSB 0
83 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN register field. */
84 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_MSB 0
85 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN register field. */
86 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_WIDTH 1
87 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN register field value. */
88 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_SET_MSK 0x00000001
89 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN register field value. */
90 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_CLR_MSK 0xfffffffe
91 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN register field. */
92 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_RESET 0x0
93 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN field value from a register. */
94 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_GET(value) (((value) & 0x00000001) >> 0)
95 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN register field value suitable for setting the register. */
96 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_SET(value) (((value) << 0) & 0x00000001)
97 
98 /*
99  * Field : hpsregion1enable
100  *
101  * HPS Region 1 Enable. Value of 1 means region is enabled, Value of 0 means region
102  * is disabled
103  *
104  * Field Access Macros:
105  *
106  */
107 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN register field. */
108 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_LSB 1
109 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN register field. */
110 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_MSB 1
111 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN register field. */
112 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_WIDTH 1
113 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN register field value. */
114 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_SET_MSK 0x00000002
115 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN register field value. */
116 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_CLR_MSK 0xfffffffd
117 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN register field. */
118 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_RESET 0x0
119 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN field value from a register. */
120 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_GET(value) (((value) & 0x00000002) >> 1)
121 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN register field value suitable for setting the register. */
122 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_SET(value) (((value) << 1) & 0x00000002)
123 
124 /*
125  * Field : hpsregion2enable
126  *
127  * HPS Region 2 Enable. Value of 1 means region is enabled, Value of 0 means region
128  * is disabled
129  *
130  * Field Access Macros:
131  *
132  */
133 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN register field. */
134 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_LSB 2
135 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN register field. */
136 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_MSB 2
137 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN register field. */
138 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_WIDTH 1
139 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN register field value. */
140 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_SET_MSK 0x00000004
141 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN register field value. */
142 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_CLR_MSK 0xfffffffb
143 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN register field. */
144 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_RESET 0x0
145 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN field value from a register. */
146 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_GET(value) (((value) & 0x00000004) >> 2)
147 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN register field value suitable for setting the register. */
148 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_SET(value) (((value) << 2) & 0x00000004)
149 
150 /*
151  * Field : hpsregion3enable
152  *
153  * HPS Region 3 Enable. Value of 1 means region is enabled, Value of 0 means region
154  * is disabled
155  *
156  * Field Access Macros:
157  *
158  */
159 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN register field. */
160 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_LSB 3
161 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN register field. */
162 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_MSB 3
163 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN register field. */
164 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_WIDTH 1
165 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN register field value. */
166 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_SET_MSK 0x00000008
167 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN register field value. */
168 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_CLR_MSK 0xfffffff7
169 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN register field. */
170 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_RESET 0x0
171 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN field value from a register. */
172 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_GET(value) (((value) & 0x00000008) >> 3)
173 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN register field value suitable for setting the register. */
174 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_SET(value) (((value) << 3) & 0x00000008)
175 
176 /*
177  * Field : hpsregion4enable
178  *
179  * HPS Region 4 Enable. Value of 1 means region is enabled, Value of 0 means region
180  * is disabled
181  *
182  * Field Access Macros:
183  *
184  */
185 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN register field. */
186 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_LSB 4
187 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN register field. */
188 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_MSB 4
189 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN register field. */
190 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_WIDTH 1
191 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN register field value. */
192 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_SET_MSK 0x00000010
193 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN register field value. */
194 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_CLR_MSK 0xffffffef
195 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN register field. */
196 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_RESET 0x0
197 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN field value from a register. */
198 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_GET(value) (((value) & 0x00000010) >> 4)
199 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN register field value suitable for setting the register. */
200 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_SET(value) (((value) << 4) & 0x00000010)
201 
202 /*
203  * Field : hpsregion5enable
204  *
205  * HPS Region 5 Enable. Value of 1 means region is enabled, Value of 0 means region
206  * is disabled
207  *
208  * Field Access Macros:
209  *
210  */
211 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN register field. */
212 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_LSB 5
213 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN register field. */
214 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_MSB 5
215 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN register field. */
216 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_WIDTH 1
217 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN register field value. */
218 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_SET_MSK 0x00000020
219 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN register field value. */
220 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_CLR_MSK 0xffffffdf
221 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN register field. */
222 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_RESET 0x0
223 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN field value from a register. */
224 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_GET(value) (((value) & 0x00000020) >> 5)
225 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN register field value suitable for setting the register. */
226 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_SET(value) (((value) << 5) & 0x00000020)
227 
228 /*
229  * Field : hpsregion6enable
230  *
231  * HPS Region 6 Enable. Value of 1 means region is enabled, Value of 0 means region
232  * is disabled
233  *
234  * Field Access Macros:
235  *
236  */
237 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN register field. */
238 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_LSB 6
239 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN register field. */
240 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_MSB 6
241 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN register field. */
242 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_WIDTH 1
243 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN register field value. */
244 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_SET_MSK 0x00000040
245 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN register field value. */
246 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_CLR_MSK 0xffffffbf
247 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN register field. */
248 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_RESET 0x0
249 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN field value from a register. */
250 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_GET(value) (((value) & 0x00000040) >> 6)
251 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN register field value suitable for setting the register. */
252 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_SET(value) (((value) << 6) & 0x00000040)
253 
254 /*
255  * Field : hpsregion7enable
256  *
257  * HPS Region 7 Enable. Value of 1 means region is enabled, Value of 0 means region
258  * is disabled
259  *
260  * Field Access Macros:
261  *
262  */
263 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN register field. */
264 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_LSB 7
265 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN register field. */
266 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_MSB 7
267 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN register field. */
268 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_WIDTH 1
269 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN register field value. */
270 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_SET_MSK 0x00000080
271 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN register field value. */
272 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_CLR_MSK 0xffffff7f
273 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN register field. */
274 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_RESET 0x0
275 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN field value from a register. */
276 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_GET(value) (((value) & 0x00000080) >> 7)
277 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN register field value suitable for setting the register. */
278 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_SET(value) (((value) << 7) & 0x00000080)
279 
280 #ifndef __ASSEMBLY__
281 /*
282  * WARNING: The C register and register group struct declarations are provided for
283  * convenience and illustrative purposes. They should, however, be used with
284  * caution as the C language standard provides no guarantees about the alignment or
285  * atomicity of device memory accesses. The recommended practice for writing
286  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
287  * alt_write_word() functions.
288  *
289  * The struct declaration for register ALT_NOC_FW_DDR_L3_SCR_EN.
290  */
291 struct ALT_NOC_FW_DDR_L3_SCR_EN_s
292 {
293  uint32_t hpsregion0enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN */
294  uint32_t hpsregion1enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN */
295  uint32_t hpsregion2enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN */
296  uint32_t hpsregion3enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN */
297  uint32_t hpsregion4enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN */
298  uint32_t hpsregion5enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN */
299  uint32_t hpsregion6enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN */
300  uint32_t hpsregion7enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN */
301  uint32_t : 24; /* *UNDEFINED* */
302 };
303 
304 /* The typedef declaration for register ALT_NOC_FW_DDR_L3_SCR_EN. */
305 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_EN_s ALT_NOC_FW_DDR_L3_SCR_EN_t;
306 #endif /* __ASSEMBLY__ */
307 
308 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN register. */
309 #define ALT_NOC_FW_DDR_L3_SCR_EN_RESET 0x00000000
310 /* The byte offset of the ALT_NOC_FW_DDR_L3_SCR_EN register from the beginning of the component. */
311 #define ALT_NOC_FW_DDR_L3_SCR_EN_OFST 0x0
312 
313 /*
314  * Register : enable_set
315  *
316  * Sets Master Region Enable field when written with 1
317  *
318  * Register Layout
319  *
320  * Bits | Access | Reset | Description
321  * :-------|:-------|:------|:---------------------------------------
322  * [0] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN
323  * [1] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN
324  * [2] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN
325  * [3] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN
326  * [4] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN
327  * [5] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN
328  * [6] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN
329  * [7] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN
330  * [31:8] | ??? | 0x0 | *UNDEFINED*
331  *
332  */
333 /*
334  * Field : hpsregion0enable
335  *
336  * HPS Region 0 Enable Set.
337  *
338  * Writing zero has no effect
339  *
340  * Writing one will set the hpsregion0enable bit to one
341  *
342  * Field Access Macros:
343  *
344  */
345 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN register field. */
346 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_LSB 0
347 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN register field. */
348 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_MSB 0
349 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN register field. */
350 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_WIDTH 1
351 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN register field value. */
352 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_SET_MSK 0x00000001
353 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN register field value. */
354 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_CLR_MSK 0xfffffffe
355 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN register field. */
356 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_RESET 0x0
357 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN field value from a register. */
358 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_GET(value) (((value) & 0x00000001) >> 0)
359 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN register field value suitable for setting the register. */
360 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_SET(value) (((value) << 0) & 0x00000001)
361 
362 /*
363  * Field : hpsregion1enable
364  *
365  * HPS Region 0 Enable Set.
366  *
367  * Writing zero has no effect
368  *
369  * Writing one will set the hpsregion1enable bit to one
370  *
371  * Field Access Macros:
372  *
373  */
374 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN register field. */
375 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_LSB 1
376 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN register field. */
377 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_MSB 1
378 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN register field. */
379 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_WIDTH 1
380 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN register field value. */
381 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_SET_MSK 0x00000002
382 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN register field value. */
383 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_CLR_MSK 0xfffffffd
384 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN register field. */
385 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_RESET 0x0
386 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN field value from a register. */
387 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_GET(value) (((value) & 0x00000002) >> 1)
388 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN register field value suitable for setting the register. */
389 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_SET(value) (((value) << 1) & 0x00000002)
390 
391 /*
392  * Field : hpsregion2enable
393  *
394  * HPS Region 0 Enable Set.
395  *
396  * Writing zero has no effect
397  *
398  * Writing one will set the hpsregion2enable bit to one
399  *
400  * Field Access Macros:
401  *
402  */
403 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN register field. */
404 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_LSB 2
405 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN register field. */
406 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_MSB 2
407 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN register field. */
408 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_WIDTH 1
409 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN register field value. */
410 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_SET_MSK 0x00000004
411 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN register field value. */
412 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_CLR_MSK 0xfffffffb
413 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN register field. */
414 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_RESET 0x0
415 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN field value from a register. */
416 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_GET(value) (((value) & 0x00000004) >> 2)
417 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN register field value suitable for setting the register. */
418 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_SET(value) (((value) << 2) & 0x00000004)
419 
420 /*
421  * Field : hpsregion3enable
422  *
423  * HPS Region 0 Enable Set.
424  *
425  * Writing zero has no effect
426  *
427  * Writing one will set the hpsregion3enable bit to one
428  *
429  * Field Access Macros:
430  *
431  */
432 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN register field. */
433 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_LSB 3
434 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN register field. */
435 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_MSB 3
436 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN register field. */
437 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_WIDTH 1
438 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN register field value. */
439 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_SET_MSK 0x00000008
440 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN register field value. */
441 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_CLR_MSK 0xfffffff7
442 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN register field. */
443 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_RESET 0x0
444 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN field value from a register. */
445 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_GET(value) (((value) & 0x00000008) >> 3)
446 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN register field value suitable for setting the register. */
447 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_SET(value) (((value) << 3) & 0x00000008)
448 
449 /*
450  * Field : hpsregion4enable
451  *
452  * HPS Region 0 Enable Set.
453  *
454  * Writing zero has no effect
455  *
456  * Writing one will set the hpsregion4enable bit to one
457  *
458  * Field Access Macros:
459  *
460  */
461 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN register field. */
462 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_LSB 4
463 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN register field. */
464 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_MSB 4
465 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN register field. */
466 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_WIDTH 1
467 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN register field value. */
468 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_SET_MSK 0x00000010
469 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN register field value. */
470 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_CLR_MSK 0xffffffef
471 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN register field. */
472 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_RESET 0x0
473 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN field value from a register. */
474 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_GET(value) (((value) & 0x00000010) >> 4)
475 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN register field value suitable for setting the register. */
476 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_SET(value) (((value) << 4) & 0x00000010)
477 
478 /*
479  * Field : hpsregion5enable
480  *
481  * HPS Region 0 Enable Set.
482  *
483  * Writing zero has no effect
484  *
485  * Writing one will set the hpsregion5enable bit to one
486  *
487  * Field Access Macros:
488  *
489  */
490 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN register field. */
491 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_LSB 5
492 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN register field. */
493 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_MSB 5
494 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN register field. */
495 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_WIDTH 1
496 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN register field value. */
497 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_SET_MSK 0x00000020
498 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN register field value. */
499 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_CLR_MSK 0xffffffdf
500 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN register field. */
501 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_RESET 0x0
502 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN field value from a register. */
503 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_GET(value) (((value) & 0x00000020) >> 5)
504 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN register field value suitable for setting the register. */
505 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_SET(value) (((value) << 5) & 0x00000020)
506 
507 /*
508  * Field : hpsregion6enable
509  *
510  * HPS Region 0 Enable Set.
511  *
512  * Writing zero has no effect
513  *
514  * Writing one will set the hpsregion6enable bit to one
515  *
516  * Field Access Macros:
517  *
518  */
519 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN register field. */
520 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_LSB 6
521 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN register field. */
522 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_MSB 6
523 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN register field. */
524 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_WIDTH 1
525 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN register field value. */
526 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_SET_MSK 0x00000040
527 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN register field value. */
528 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_CLR_MSK 0xffffffbf
529 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN register field. */
530 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_RESET 0x0
531 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN field value from a register. */
532 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_GET(value) (((value) & 0x00000040) >> 6)
533 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN register field value suitable for setting the register. */
534 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_SET(value) (((value) << 6) & 0x00000040)
535 
536 /*
537  * Field : hpsregion7enable
538  *
539  * HPS Region 0 Enable Set.
540  *
541  * Writing zero has no effect
542  *
543  * Writing one will set the hpsregion7enable bit to one
544  *
545  * Field Access Macros:
546  *
547  */
548 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN register field. */
549 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_LSB 7
550 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN register field. */
551 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_MSB 7
552 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN register field. */
553 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_WIDTH 1
554 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN register field value. */
555 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_SET_MSK 0x00000080
556 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN register field value. */
557 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_CLR_MSK 0xffffff7f
558 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN register field. */
559 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_RESET 0x0
560 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN field value from a register. */
561 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_GET(value) (((value) & 0x00000080) >> 7)
562 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN register field value suitable for setting the register. */
563 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_SET(value) (((value) << 7) & 0x00000080)
564 
565 #ifndef __ASSEMBLY__
566 /*
567  * WARNING: The C register and register group struct declarations are provided for
568  * convenience and illustrative purposes. They should, however, be used with
569  * caution as the C language standard provides no guarantees about the alignment or
570  * atomicity of device memory accesses. The recommended practice for writing
571  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
572  * alt_write_word() functions.
573  *
574  * The struct declaration for register ALT_NOC_FW_DDR_L3_SCR_EN_SET.
575  */
576 struct ALT_NOC_FW_DDR_L3_SCR_EN_SET_s
577 {
578  uint32_t hpsregion0enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN */
579  uint32_t hpsregion1enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN */
580  uint32_t hpsregion2enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN */
581  uint32_t hpsregion3enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN */
582  uint32_t hpsregion4enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN */
583  uint32_t hpsregion5enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN */
584  uint32_t hpsregion6enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN */
585  uint32_t hpsregion7enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN */
586  uint32_t : 24; /* *UNDEFINED* */
587 };
588 
589 /* The typedef declaration for register ALT_NOC_FW_DDR_L3_SCR_EN_SET. */
590 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_EN_SET_s ALT_NOC_FW_DDR_L3_SCR_EN_SET_t;
591 #endif /* __ASSEMBLY__ */
592 
593 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_SET register. */
594 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_RESET 0x00000000
595 /* The byte offset of the ALT_NOC_FW_DDR_L3_SCR_EN_SET register from the beginning of the component. */
596 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_OFST 0x4
597 
598 /*
599  * Register : enable_clear
600  *
601  * Clears Master Region Enable field when written with 1
602  *
603  * Register Layout
604  *
605  * Bits | Access | Reset | Description
606  * :-------|:-------|:------|:---------------------------------------
607  * [0] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN
608  * [1] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN
609  * [2] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN
610  * [3] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN
611  * [4] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN
612  * [5] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN
613  * [6] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN
614  * [7] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN
615  * [31:8] | ??? | 0x0 | *UNDEFINED*
616  *
617  */
618 /*
619  * Field : hpsregion0enable
620  *
621  * HPS Region 0 Enable Clear.
622  *
623  * Writing zero has no effect
624  *
625  * Writing one will clear the hpsregion0enable bit to zero
626  *
627  * Field Access Macros:
628  *
629  */
630 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN register field. */
631 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_LSB 0
632 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN register field. */
633 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_MSB 0
634 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN register field. */
635 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_WIDTH 1
636 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN register field value. */
637 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_SET_MSK 0x00000001
638 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN register field value. */
639 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_CLR_MSK 0xfffffffe
640 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN register field. */
641 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_RESET 0x0
642 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN field value from a register. */
643 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_GET(value) (((value) & 0x00000001) >> 0)
644 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN register field value suitable for setting the register. */
645 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_SET(value) (((value) << 0) & 0x00000001)
646 
647 /*
648  * Field : hpsregion1enable
649  *
650  * HPS Region 0 Enable Clear.
651  *
652  * Writing zero has no effect
653  *
654  * Writing one will clear the hpsregion1enable bit to zero
655  *
656  * Field Access Macros:
657  *
658  */
659 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN register field. */
660 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_LSB 1
661 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN register field. */
662 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_MSB 1
663 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN register field. */
664 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_WIDTH 1
665 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN register field value. */
666 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_SET_MSK 0x00000002
667 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN register field value. */
668 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_CLR_MSK 0xfffffffd
669 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN register field. */
670 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_RESET 0x0
671 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN field value from a register. */
672 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_GET(value) (((value) & 0x00000002) >> 1)
673 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN register field value suitable for setting the register. */
674 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_SET(value) (((value) << 1) & 0x00000002)
675 
676 /*
677  * Field : hpsregion2enable
678  *
679  * HPS Region 0 Enable Clear.
680  *
681  * Writing zero has no effect
682  *
683  * Writing one will clear the hpsregion2enable bit to zero
684  *
685  * Field Access Macros:
686  *
687  */
688 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN register field. */
689 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_LSB 2
690 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN register field. */
691 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_MSB 2
692 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN register field. */
693 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_WIDTH 1
694 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN register field value. */
695 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_SET_MSK 0x00000004
696 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN register field value. */
697 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_CLR_MSK 0xfffffffb
698 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN register field. */
699 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_RESET 0x0
700 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN field value from a register. */
701 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_GET(value) (((value) & 0x00000004) >> 2)
702 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN register field value suitable for setting the register. */
703 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_SET(value) (((value) << 2) & 0x00000004)
704 
705 /*
706  * Field : hpsregion3enable
707  *
708  * HPS Region 0 Enable Clear.
709  *
710  * Writing zero has no effect
711  *
712  * Writing one will clear the hpsregion3enable bit to zero
713  *
714  * Field Access Macros:
715  *
716  */
717 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN register field. */
718 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_LSB 3
719 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN register field. */
720 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_MSB 3
721 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN register field. */
722 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_WIDTH 1
723 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN register field value. */
724 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_SET_MSK 0x00000008
725 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN register field value. */
726 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_CLR_MSK 0xfffffff7
727 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN register field. */
728 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_RESET 0x0
729 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN field value from a register. */
730 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_GET(value) (((value) & 0x00000008) >> 3)
731 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN register field value suitable for setting the register. */
732 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_SET(value) (((value) << 3) & 0x00000008)
733 
734 /*
735  * Field : hpsregion4enable
736  *
737  * HPS Region 0 Enable Clear.
738  *
739  * Writing zero has no effect
740  *
741  * Writing one will clear the hpsregion4enable bit to zero
742  *
743  * Field Access Macros:
744  *
745  */
746 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN register field. */
747 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_LSB 4
748 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN register field. */
749 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_MSB 4
750 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN register field. */
751 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_WIDTH 1
752 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN register field value. */
753 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_SET_MSK 0x00000010
754 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN register field value. */
755 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_CLR_MSK 0xffffffef
756 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN register field. */
757 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_RESET 0x0
758 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN field value from a register. */
759 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_GET(value) (((value) & 0x00000010) >> 4)
760 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN register field value suitable for setting the register. */
761 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_SET(value) (((value) << 4) & 0x00000010)
762 
763 /*
764  * Field : hpsregion5enable
765  *
766  * HPS Region 0 Enable Clear.
767  *
768  * Writing zero has no effect
769  *
770  * Writing one will clear the hpsregion5enable bit to zero
771  *
772  * Field Access Macros:
773  *
774  */
775 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN register field. */
776 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_LSB 5
777 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN register field. */
778 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_MSB 5
779 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN register field. */
780 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_WIDTH 1
781 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN register field value. */
782 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_SET_MSK 0x00000020
783 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN register field value. */
784 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_CLR_MSK 0xffffffdf
785 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN register field. */
786 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_RESET 0x0
787 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN field value from a register. */
788 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_GET(value) (((value) & 0x00000020) >> 5)
789 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN register field value suitable for setting the register. */
790 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_SET(value) (((value) << 5) & 0x00000020)
791 
792 /*
793  * Field : hpsregion6enable
794  *
795  * HPS Region 0 Enable Clear.
796  *
797  * Writing zero has no effect
798  *
799  * Writing one will clear the hpsregion6enable bit to zero
800  *
801  * Field Access Macros:
802  *
803  */
804 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN register field. */
805 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_LSB 6
806 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN register field. */
807 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_MSB 6
808 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN register field. */
809 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_WIDTH 1
810 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN register field value. */
811 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_SET_MSK 0x00000040
812 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN register field value. */
813 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_CLR_MSK 0xffffffbf
814 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN register field. */
815 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_RESET 0x0
816 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN field value from a register. */
817 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_GET(value) (((value) & 0x00000040) >> 6)
818 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN register field value suitable for setting the register. */
819 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_SET(value) (((value) << 6) & 0x00000040)
820 
821 /*
822  * Field : hpsregion7enable
823  *
824  * HPS Region 0 Enable Clear.
825  *
826  * Writing zero has no effect
827  *
828  * Writing one will clear the hpsregion7enable bit to zero
829  *
830  * Field Access Macros:
831  *
832  */
833 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN register field. */
834 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_LSB 7
835 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN register field. */
836 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_MSB 7
837 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN register field. */
838 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_WIDTH 1
839 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN register field value. */
840 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_SET_MSK 0x00000080
841 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN register field value. */
842 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_CLR_MSK 0xffffff7f
843 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN register field. */
844 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_RESET 0x0
845 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN field value from a register. */
846 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_GET(value) (((value) & 0x00000080) >> 7)
847 /* Produces a ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN register field value suitable for setting the register. */
848 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_SET(value) (((value) << 7) & 0x00000080)
849 
850 #ifndef __ASSEMBLY__
851 /*
852  * WARNING: The C register and register group struct declarations are provided for
853  * convenience and illustrative purposes. They should, however, be used with
854  * caution as the C language standard provides no guarantees about the alignment or
855  * atomicity of device memory accesses. The recommended practice for writing
856  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
857  * alt_write_word() functions.
858  *
859  * The struct declaration for register ALT_NOC_FW_DDR_L3_SCR_EN_CLR.
860  */
861 struct ALT_NOC_FW_DDR_L3_SCR_EN_CLR_s
862 {
863  uint32_t hpsregion0enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN */
864  uint32_t hpsregion1enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN */
865  uint32_t hpsregion2enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN */
866  uint32_t hpsregion3enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN */
867  uint32_t hpsregion4enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN */
868  uint32_t hpsregion5enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN */
869  uint32_t hpsregion6enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN */
870  uint32_t hpsregion7enable : 1; /* ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN */
871  uint32_t : 24; /* *UNDEFINED* */
872 };
873 
874 /* The typedef declaration for register ALT_NOC_FW_DDR_L3_SCR_EN_CLR. */
875 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_EN_CLR_s ALT_NOC_FW_DDR_L3_SCR_EN_CLR_t;
876 #endif /* __ASSEMBLY__ */
877 
878 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR register. */
879 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_RESET 0x00000000
880 /* The byte offset of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR register from the beginning of the component. */
881 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_OFST 0x8
882 
883 /*
884  * Register : hpsregion0addr
885  *
886  * Base and Limit definition for HPS Region 0
887  *
888  * Register Layout
889  *
890  * Bits | Access | Reset | Description
891  * :--------|:-------|:------|:----------------------------------------
892  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE
893  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT
894  *
895  */
896 /*
897  * Field : base
898  *
899  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
900  * zeros. Region start address is {base, 16'h000}
901  *
902  * Field Access Macros:
903  *
904  */
905 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE register field. */
906 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_LSB 0
907 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE register field. */
908 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_MSB 15
909 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE register field. */
910 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_WIDTH 16
911 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE register field value. */
912 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_SET_MSK 0x0000ffff
913 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE register field value. */
914 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_CLR_MSK 0xffff0000
915 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE register field. */
916 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_RESET 0x0
917 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE field value from a register. */
918 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
919 /* Produces a ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE register field value suitable for setting the register. */
920 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
921 
922 /*
923  * Field : limit
924  *
925  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
926  * ones. Region end address is {limit, 16'hFFF}
927  *
928  * Field Access Macros:
929  *
930  */
931 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT register field. */
932 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_LSB 16
933 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT register field. */
934 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_MSB 31
935 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT register field. */
936 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_WIDTH 16
937 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT register field value. */
938 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_SET_MSK 0xffff0000
939 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT register field value. */
940 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_CLR_MSK 0x0000ffff
941 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT register field. */
942 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_RESET 0x0
943 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT field value from a register. */
944 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
945 /* Produces a ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT register field value suitable for setting the register. */
946 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
947 
948 #ifndef __ASSEMBLY__
949 /*
950  * WARNING: The C register and register group struct declarations are provided for
951  * convenience and illustrative purposes. They should, however, be used with
952  * caution as the C language standard provides no guarantees about the alignment or
953  * atomicity of device memory accesses. The recommended practice for writing
954  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
955  * alt_write_word() functions.
956  *
957  * The struct declaration for register ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR.
958  */
959 struct ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_s
960 {
961  uint32_t base : 16; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE */
962  uint32_t limit : 16; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT */
963 };
964 
965 /* The typedef declaration for register ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR. */
966 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_s ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_t;
967 #endif /* __ASSEMBLY__ */
968 
969 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR register. */
970 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_RESET 0x00000000
971 /* The byte offset of the ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR register from the beginning of the component. */
972 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_OFST 0xc
973 
974 /*
975  * Register : hpsregion1addr
976  *
977  * Base and Limit definition for HPS Region 1
978  *
979  * Register Layout
980  *
981  * Bits | Access | Reset | Description
982  * :--------|:-------|:------|:----------------------------------------
983  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE
984  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT
985  *
986  */
987 /*
988  * Field : base
989  *
990  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
991  * zeros. Region start address is {base, 16'h000}
992  *
993  * Field Access Macros:
994  *
995  */
996 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE register field. */
997 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_LSB 0
998 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE register field. */
999 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_MSB 15
1000 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE register field. */
1001 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_WIDTH 16
1002 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE register field value. */
1003 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_SET_MSK 0x0000ffff
1004 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE register field value. */
1005 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_CLR_MSK 0xffff0000
1006 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE register field. */
1007 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_RESET 0x0
1008 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE field value from a register. */
1009 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1010 /* Produces a ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE register field value suitable for setting the register. */
1011 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1012 
1013 /*
1014  * Field : limit
1015  *
1016  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
1017  * ones. Region end address is {limit, 16'hFFF}
1018  *
1019  * Field Access Macros:
1020  *
1021  */
1022 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT register field. */
1023 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_LSB 16
1024 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT register field. */
1025 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_MSB 31
1026 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT register field. */
1027 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_WIDTH 16
1028 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT register field value. */
1029 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_SET_MSK 0xffff0000
1030 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT register field value. */
1031 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_CLR_MSK 0x0000ffff
1032 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT register field. */
1033 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_RESET 0x0
1034 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT field value from a register. */
1035 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1036 /* Produces a ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT register field value suitable for setting the register. */
1037 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1038 
1039 #ifndef __ASSEMBLY__
1040 /*
1041  * WARNING: The C register and register group struct declarations are provided for
1042  * convenience and illustrative purposes. They should, however, be used with
1043  * caution as the C language standard provides no guarantees about the alignment or
1044  * atomicity of device memory accesses. The recommended practice for writing
1045  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1046  * alt_write_word() functions.
1047  *
1048  * The struct declaration for register ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR.
1049  */
1050 struct ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_s
1051 {
1052  uint32_t base : 16; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE */
1053  uint32_t limit : 16; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT */
1054 };
1055 
1056 /* The typedef declaration for register ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR. */
1057 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_s ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_t;
1058 #endif /* __ASSEMBLY__ */
1059 
1060 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR register. */
1061 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_RESET 0x00000000
1062 /* The byte offset of the ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR register from the beginning of the component. */
1063 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_OFST 0x10
1064 
1065 /*
1066  * Register : hpsregion2addr
1067  *
1068  * Base and Limit definition for HPS Region 2
1069  *
1070  * Register Layout
1071  *
1072  * Bits | Access | Reset | Description
1073  * :--------|:-------|:------|:----------------------------------------
1074  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE
1075  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT
1076  *
1077  */
1078 /*
1079  * Field : base
1080  *
1081  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
1082  * zeros. Region start address is {base, 16'h000}
1083  *
1084  * Field Access Macros:
1085  *
1086  */
1087 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE register field. */
1088 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_LSB 0
1089 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE register field. */
1090 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_MSB 15
1091 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE register field. */
1092 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_WIDTH 16
1093 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE register field value. */
1094 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_SET_MSK 0x0000ffff
1095 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE register field value. */
1096 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_CLR_MSK 0xffff0000
1097 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE register field. */
1098 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_RESET 0x0
1099 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE field value from a register. */
1100 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1101 /* Produces a ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE register field value suitable for setting the register. */
1102 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1103 
1104 /*
1105  * Field : limit
1106  *
1107  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
1108  * ones. Region end address is {limit, 16'hFFF}
1109  *
1110  * Field Access Macros:
1111  *
1112  */
1113 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT register field. */
1114 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_LSB 16
1115 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT register field. */
1116 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_MSB 31
1117 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT register field. */
1118 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_WIDTH 16
1119 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT register field value. */
1120 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_SET_MSK 0xffff0000
1121 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT register field value. */
1122 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_CLR_MSK 0x0000ffff
1123 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT register field. */
1124 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_RESET 0x0
1125 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT field value from a register. */
1126 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1127 /* Produces a ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT register field value suitable for setting the register. */
1128 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1129 
1130 #ifndef __ASSEMBLY__
1131 /*
1132  * WARNING: The C register and register group struct declarations are provided for
1133  * convenience and illustrative purposes. They should, however, be used with
1134  * caution as the C language standard provides no guarantees about the alignment or
1135  * atomicity of device memory accesses. The recommended practice for writing
1136  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1137  * alt_write_word() functions.
1138  *
1139  * The struct declaration for register ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR.
1140  */
1141 struct ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_s
1142 {
1143  uint32_t base : 16; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE */
1144  uint32_t limit : 16; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT */
1145 };
1146 
1147 /* The typedef declaration for register ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR. */
1148 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_s ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_t;
1149 #endif /* __ASSEMBLY__ */
1150 
1151 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR register. */
1152 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_RESET 0x00000000
1153 /* The byte offset of the ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR register from the beginning of the component. */
1154 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_OFST 0x14
1155 
1156 /*
1157  * Register : hpsregion3addr
1158  *
1159  * Base and Limit definition for HPS Region 3
1160  *
1161  * Register Layout
1162  *
1163  * Bits | Access | Reset | Description
1164  * :--------|:-------|:------|:----------------------------------------
1165  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE
1166  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT
1167  *
1168  */
1169 /*
1170  * Field : base
1171  *
1172  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
1173  * zeros. Region start address is {base, 16'h000}
1174  *
1175  * Field Access Macros:
1176  *
1177  */
1178 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE register field. */
1179 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_LSB 0
1180 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE register field. */
1181 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_MSB 15
1182 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE register field. */
1183 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_WIDTH 16
1184 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE register field value. */
1185 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_SET_MSK 0x0000ffff
1186 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE register field value. */
1187 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_CLR_MSK 0xffff0000
1188 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE register field. */
1189 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_RESET 0x0
1190 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE field value from a register. */
1191 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1192 /* Produces a ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE register field value suitable for setting the register. */
1193 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1194 
1195 /*
1196  * Field : limit
1197  *
1198  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
1199  * ones. Region end address is {limit, 16'hFFF}
1200  *
1201  * Field Access Macros:
1202  *
1203  */
1204 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT register field. */
1205 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_LSB 16
1206 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT register field. */
1207 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_MSB 31
1208 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT register field. */
1209 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_WIDTH 16
1210 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT register field value. */
1211 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_SET_MSK 0xffff0000
1212 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT register field value. */
1213 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_CLR_MSK 0x0000ffff
1214 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT register field. */
1215 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_RESET 0x0
1216 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT field value from a register. */
1217 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1218 /* Produces a ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT register field value suitable for setting the register. */
1219 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1220 
1221 #ifndef __ASSEMBLY__
1222 /*
1223  * WARNING: The C register and register group struct declarations are provided for
1224  * convenience and illustrative purposes. They should, however, be used with
1225  * caution as the C language standard provides no guarantees about the alignment or
1226  * atomicity of device memory accesses. The recommended practice for writing
1227  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1228  * alt_write_word() functions.
1229  *
1230  * The struct declaration for register ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR.
1231  */
1232 struct ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_s
1233 {
1234  uint32_t base : 16; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE */
1235  uint32_t limit : 16; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT */
1236 };
1237 
1238 /* The typedef declaration for register ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR. */
1239 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_s ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_t;
1240 #endif /* __ASSEMBLY__ */
1241 
1242 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR register. */
1243 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_RESET 0x00000000
1244 /* The byte offset of the ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR register from the beginning of the component. */
1245 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_OFST 0x18
1246 
1247 /*
1248  * Register : hpsregion4addr
1249  *
1250  * Base and Limit definition for HPS Region 4
1251  *
1252  * Register Layout
1253  *
1254  * Bits | Access | Reset | Description
1255  * :--------|:-------|:------|:----------------------------------------
1256  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE
1257  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT
1258  *
1259  */
1260 /*
1261  * Field : base
1262  *
1263  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
1264  * zeros. Region start address is {base, 16'h000}
1265  *
1266  * Field Access Macros:
1267  *
1268  */
1269 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE register field. */
1270 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_LSB 0
1271 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE register field. */
1272 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_MSB 15
1273 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE register field. */
1274 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_WIDTH 16
1275 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE register field value. */
1276 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_SET_MSK 0x0000ffff
1277 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE register field value. */
1278 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_CLR_MSK 0xffff0000
1279 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE register field. */
1280 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_RESET 0x0
1281 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE field value from a register. */
1282 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1283 /* Produces a ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE register field value suitable for setting the register. */
1284 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1285 
1286 /*
1287  * Field : limit
1288  *
1289  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
1290  * ones. Region end address is {limit, 16'hFFF}
1291  *
1292  * Field Access Macros:
1293  *
1294  */
1295 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT register field. */
1296 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_LSB 16
1297 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT register field. */
1298 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_MSB 31
1299 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT register field. */
1300 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_WIDTH 16
1301 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT register field value. */
1302 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_SET_MSK 0xffff0000
1303 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT register field value. */
1304 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_CLR_MSK 0x0000ffff
1305 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT register field. */
1306 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_RESET 0x0
1307 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT field value from a register. */
1308 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1309 /* Produces a ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT register field value suitable for setting the register. */
1310 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1311 
1312 #ifndef __ASSEMBLY__
1313 /*
1314  * WARNING: The C register and register group struct declarations are provided for
1315  * convenience and illustrative purposes. They should, however, be used with
1316  * caution as the C language standard provides no guarantees about the alignment or
1317  * atomicity of device memory accesses. The recommended practice for writing
1318  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1319  * alt_write_word() functions.
1320  *
1321  * The struct declaration for register ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR.
1322  */
1323 struct ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_s
1324 {
1325  uint32_t base : 16; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE */
1326  uint32_t limit : 16; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT */
1327 };
1328 
1329 /* The typedef declaration for register ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR. */
1330 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_s ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_t;
1331 #endif /* __ASSEMBLY__ */
1332 
1333 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR register. */
1334 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_RESET 0x00000000
1335 /* The byte offset of the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR register from the beginning of the component. */
1336 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_OFST 0x1c
1337 
1338 /*
1339  * Register : hpsregion5addr
1340  *
1341  * Base and Limit definition for HPS Region 5
1342  *
1343  * Register Layout
1344  *
1345  * Bits | Access | Reset | Description
1346  * :--------|:-------|:------|:----------------------------------------
1347  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE
1348  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT
1349  *
1350  */
1351 /*
1352  * Field : base
1353  *
1354  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
1355  * zeros. Region start address is {base, 16'h000}
1356  *
1357  * Field Access Macros:
1358  *
1359  */
1360 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE register field. */
1361 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_LSB 0
1362 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE register field. */
1363 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_MSB 15
1364 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE register field. */
1365 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_WIDTH 16
1366 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE register field value. */
1367 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_SET_MSK 0x0000ffff
1368 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE register field value. */
1369 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_CLR_MSK 0xffff0000
1370 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE register field. */
1371 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_RESET 0x0
1372 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE field value from a register. */
1373 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1374 /* Produces a ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE register field value suitable for setting the register. */
1375 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1376 
1377 /*
1378  * Field : limit
1379  *
1380  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
1381  * ones. Region end address is {limit, 16'hFFF}
1382  *
1383  * Field Access Macros:
1384  *
1385  */
1386 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT register field. */
1387 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_LSB 16
1388 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT register field. */
1389 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_MSB 31
1390 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT register field. */
1391 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_WIDTH 16
1392 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT register field value. */
1393 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_SET_MSK 0xffff0000
1394 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT register field value. */
1395 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_CLR_MSK 0x0000ffff
1396 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT register field. */
1397 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_RESET 0x0
1398 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT field value from a register. */
1399 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1400 /* Produces a ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT register field value suitable for setting the register. */
1401 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1402 
1403 #ifndef __ASSEMBLY__
1404 /*
1405  * WARNING: The C register and register group struct declarations are provided for
1406  * convenience and illustrative purposes. They should, however, be used with
1407  * caution as the C language standard provides no guarantees about the alignment or
1408  * atomicity of device memory accesses. The recommended practice for writing
1409  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1410  * alt_write_word() functions.
1411  *
1412  * The struct declaration for register ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR.
1413  */
1414 struct ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_s
1415 {
1416  uint32_t base : 16; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE */
1417  uint32_t limit : 16; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT */
1418 };
1419 
1420 /* The typedef declaration for register ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR. */
1421 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_s ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_t;
1422 #endif /* __ASSEMBLY__ */
1423 
1424 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR register. */
1425 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_RESET 0x00000000
1426 /* The byte offset of the ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR register from the beginning of the component. */
1427 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_OFST 0x20
1428 
1429 /*
1430  * Register : hpsregion6addr
1431  *
1432  * Base and Limit definition for HPS Region 6
1433  *
1434  * Register Layout
1435  *
1436  * Bits | Access | Reset | Description
1437  * :--------|:-------|:------|:----------------------------------------
1438  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE
1439  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT
1440  *
1441  */
1442 /*
1443  * Field : base
1444  *
1445  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
1446  * zeros. Region start address is {base, 16'h000}
1447  *
1448  * Field Access Macros:
1449  *
1450  */
1451 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE register field. */
1452 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_LSB 0
1453 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE register field. */
1454 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_MSB 15
1455 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE register field. */
1456 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_WIDTH 16
1457 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE register field value. */
1458 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_SET_MSK 0x0000ffff
1459 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE register field value. */
1460 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_CLR_MSK 0xffff0000
1461 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE register field. */
1462 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_RESET 0x0
1463 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE field value from a register. */
1464 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1465 /* Produces a ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE register field value suitable for setting the register. */
1466 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1467 
1468 /*
1469  * Field : limit
1470  *
1471  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
1472  * ones. Region end address is {limit, 16'hFFF}
1473  *
1474  * Field Access Macros:
1475  *
1476  */
1477 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT register field. */
1478 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_LSB 16
1479 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT register field. */
1480 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_MSB 31
1481 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT register field. */
1482 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_WIDTH 16
1483 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT register field value. */
1484 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_SET_MSK 0xffff0000
1485 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT register field value. */
1486 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_CLR_MSK 0x0000ffff
1487 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT register field. */
1488 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_RESET 0x0
1489 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT field value from a register. */
1490 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1491 /* Produces a ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT register field value suitable for setting the register. */
1492 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1493 
1494 #ifndef __ASSEMBLY__
1495 /*
1496  * WARNING: The C register and register group struct declarations are provided for
1497  * convenience and illustrative purposes. They should, however, be used with
1498  * caution as the C language standard provides no guarantees about the alignment or
1499  * atomicity of device memory accesses. The recommended practice for writing
1500  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1501  * alt_write_word() functions.
1502  *
1503  * The struct declaration for register ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR.
1504  */
1505 struct ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_s
1506 {
1507  uint32_t base : 16; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE */
1508  uint32_t limit : 16; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT */
1509 };
1510 
1511 /* The typedef declaration for register ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR. */
1512 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_s ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_t;
1513 #endif /* __ASSEMBLY__ */
1514 
1515 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR register. */
1516 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_RESET 0x00000000
1517 /* The byte offset of the ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR register from the beginning of the component. */
1518 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_OFST 0x24
1519 
1520 /*
1521  * Register : hpsregion7addr
1522  *
1523  * Base and Limit definition for HPS Region 7
1524  *
1525  * Register Layout
1526  *
1527  * Bits | Access | Reset | Description
1528  * :--------|:-------|:------|:----------------------------------------
1529  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE
1530  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT
1531  *
1532  */
1533 /*
1534  * Field : base
1535  *
1536  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
1537  * zeros. Region start address is {base, 16'h000}
1538  *
1539  * Field Access Macros:
1540  *
1541  */
1542 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE register field. */
1543 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_LSB 0
1544 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE register field. */
1545 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_MSB 15
1546 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE register field. */
1547 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_WIDTH 16
1548 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE register field value. */
1549 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_SET_MSK 0x0000ffff
1550 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE register field value. */
1551 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_CLR_MSK 0xffff0000
1552 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE register field. */
1553 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_RESET 0x0
1554 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE field value from a register. */
1555 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1556 /* Produces a ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE register field value suitable for setting the register. */
1557 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1558 
1559 /*
1560  * Field : limit
1561  *
1562  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
1563  * ones. Region end address is {limit, 16'hFFF}
1564  *
1565  * Field Access Macros:
1566  *
1567  */
1568 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT register field. */
1569 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_LSB 16
1570 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT register field. */
1571 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_MSB 31
1572 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT register field. */
1573 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_WIDTH 16
1574 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT register field value. */
1575 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_SET_MSK 0xffff0000
1576 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT register field value. */
1577 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_CLR_MSK 0x0000ffff
1578 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT register field. */
1579 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_RESET 0x0
1580 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT field value from a register. */
1581 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1582 /* Produces a ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT register field value suitable for setting the register. */
1583 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1584 
1585 #ifndef __ASSEMBLY__
1586 /*
1587  * WARNING: The C register and register group struct declarations are provided for
1588  * convenience and illustrative purposes. They should, however, be used with
1589  * caution as the C language standard provides no guarantees about the alignment or
1590  * atomicity of device memory accesses. The recommended practice for writing
1591  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1592  * alt_write_word() functions.
1593  *
1594  * The struct declaration for register ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR.
1595  */
1596 struct ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_s
1597 {
1598  uint32_t base : 16; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE */
1599  uint32_t limit : 16; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT */
1600 };
1601 
1602 /* The typedef declaration for register ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR. */
1603 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_s ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_t;
1604 #endif /* __ASSEMBLY__ */
1605 
1606 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR register. */
1607 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_RESET 0x00000000
1608 /* The byte offset of the ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR register from the beginning of the component. */
1609 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_OFST 0x28
1610 
1611 /*
1612  * Register : global
1613  *
1614  * Global Firewall Control Register. This register will store various overrides
1615  * that change default firewall behavior on the entire interconnect.
1616  *
1617  * Register Layout
1618  *
1619  * Bits | Access | Reset | Description
1620  * :-------|:-------|:------|:------------------------------------------
1621  * [0] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE
1622  * [31:1] | ??? | 0x0 | *UNDEFINED*
1623  *
1624  */
1625 /*
1626  * Field : error_response
1627  *
1628  * When 0, transactions blocked by the firewall will silently fail (i.e successful
1629  * completion with random data). When 1, transactions blocked by the firewall will
1630  * return error
1631  *
1632  * Field Access Macros:
1633  *
1634  */
1635 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE register field. */
1636 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_LSB 0
1637 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE register field. */
1638 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_MSB 0
1639 /* The width in bits of the ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE register field. */
1640 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_WIDTH 1
1641 /* The mask used to set the ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE register field value. */
1642 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_SET_MSK 0x00000001
1643 /* The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE register field value. */
1644 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_CLR_MSK 0xfffffffe
1645 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE register field. */
1646 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_RESET 0x0
1647 /* Extracts the ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE field value from a register. */
1648 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_GET(value) (((value) & 0x00000001) >> 0)
1649 /* Produces a ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE register field value suitable for setting the register. */
1650 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_SET(value) (((value) << 0) & 0x00000001)
1651 
1652 #ifndef __ASSEMBLY__
1653 /*
1654  * WARNING: The C register and register group struct declarations are provided for
1655  * convenience and illustrative purposes. They should, however, be used with
1656  * caution as the C language standard provides no guarantees about the alignment or
1657  * atomicity of device memory accesses. The recommended practice for writing
1658  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1659  * alt_write_word() functions.
1660  *
1661  * The struct declaration for register ALT_NOC_FW_DDR_L3_SCR_GLOB.
1662  */
1663 struct ALT_NOC_FW_DDR_L3_SCR_GLOB_s
1664 {
1665  uint32_t error_response : 1; /* ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE */
1666  uint32_t : 31; /* *UNDEFINED* */
1667 };
1668 
1669 /* The typedef declaration for register ALT_NOC_FW_DDR_L3_SCR_GLOB. */
1670 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_GLOB_s ALT_NOC_FW_DDR_L3_SCR_GLOB_t;
1671 #endif /* __ASSEMBLY__ */
1672 
1673 /* The reset value of the ALT_NOC_FW_DDR_L3_SCR_GLOB register. */
1674 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_RESET 0x00000000
1675 /* The byte offset of the ALT_NOC_FW_DDR_L3_SCR_GLOB register from the beginning of the component. */
1676 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_OFST 0x2c
1677 
1678 #ifndef __ASSEMBLY__
1679 /*
1680  * WARNING: The C register and register group struct declarations are provided for
1681  * convenience and illustrative purposes. They should, however, be used with
1682  * caution as the C language standard provides no guarantees about the alignment or
1683  * atomicity of device memory accesses. The recommended practice for writing
1684  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1685  * alt_write_word() functions.
1686  *
1687  * The struct declaration for register group ALT_NOC_FW_DDR_L3_SCR.
1688  */
1689 struct ALT_NOC_FW_DDR_L3_SCR_s
1690 {
1691  ALT_NOC_FW_DDR_L3_SCR_EN_t enable; /* ALT_NOC_FW_DDR_L3_SCR_EN */
1692  ALT_NOC_FW_DDR_L3_SCR_EN_SET_t enable_set; /* ALT_NOC_FW_DDR_L3_SCR_EN_SET */
1693  ALT_NOC_FW_DDR_L3_SCR_EN_CLR_t enable_clear; /* ALT_NOC_FW_DDR_L3_SCR_EN_CLR */
1694  ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_t hpsregion0addr; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR */
1695  ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_t hpsregion1addr; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR */
1696  ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_t hpsregion2addr; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR */
1697  ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_t hpsregion3addr; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR */
1698  ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_t hpsregion4addr; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR */
1699  ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_t hpsregion5addr; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR */
1700  ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_t hpsregion6addr; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR */
1701  ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_t hpsregion7addr; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR */
1702  ALT_NOC_FW_DDR_L3_SCR_GLOB_t global; /* ALT_NOC_FW_DDR_L3_SCR_GLOB */
1703  volatile uint32_t _pad_0x30_0x100[52]; /* *UNDEFINED* */
1704 };
1705 
1706 /* The typedef declaration for register group ALT_NOC_FW_DDR_L3_SCR. */
1707 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_s ALT_NOC_FW_DDR_L3_SCR_t;
1708 /* The struct declaration for the raw register contents of register group ALT_NOC_FW_DDR_L3_SCR. */
1709 struct ALT_NOC_FW_DDR_L3_SCR_raw_s
1710 {
1711  volatile uint32_t enable; /* ALT_NOC_FW_DDR_L3_SCR_EN */
1712  volatile uint32_t enable_set; /* ALT_NOC_FW_DDR_L3_SCR_EN_SET */
1713  volatile uint32_t enable_clear; /* ALT_NOC_FW_DDR_L3_SCR_EN_CLR */
1714  volatile uint32_t hpsregion0addr; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR */
1715  volatile uint32_t hpsregion1addr; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR */
1716  volatile uint32_t hpsregion2addr; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR */
1717  volatile uint32_t hpsregion3addr; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR */
1718  volatile uint32_t hpsregion4addr; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR */
1719  volatile uint32_t hpsregion5addr; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR */
1720  volatile uint32_t hpsregion6addr; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR */
1721  volatile uint32_t hpsregion7addr; /* ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR */
1722  volatile uint32_t global; /* ALT_NOC_FW_DDR_L3_SCR_GLOB */
1723  uint32_t _pad_0x30_0x100[52]; /* *UNDEFINED* */
1724 };
1725 
1726 /* The typedef declaration for the raw register contents of register group ALT_NOC_FW_DDR_L3_SCR. */
1727 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_raw_s ALT_NOC_FW_DDR_L3_SCR_raw_t;
1728 #endif /* __ASSEMBLY__ */
1729 
1730 
1731 #ifdef __cplusplus
1732 }
1733 #endif /* __cplusplus */
1734 #endif /* __ALT_SOCAL_NOC_FW_DDR_L3_SCR_H__ */
1735