Hardware Libraries  20.1
Arria 10 SoC Abstration Layer
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alt_noc_fw_l4_per_scr.h
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32 
33 /* Altera - ALT_NOC_FW_L4_PER_SCR */
34 
35 #ifndef __ALT_SOCAL_NOC_FW_L4_PER_SCR_H__
36 #define __ALT_SOCAL_NOC_FW_L4_PER_SCR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_NOC_FW_L4_PER_SCR
50  *
51  */
52 /*
53  * Register : nand_register
54  *
55  * Per-Master Security bit for nand register
56  *
57  * Register Layout
58  *
59  * Bits | Access | Reset | Description
60  * :--------|:-------|:--------|:--------------------------------------
61  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0
62  * [7:1] | ??? | Unknown | *UNDEFINED*
63  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA
64  * [15:9] | ??? | Unknown | *UNDEFINED*
65  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H
66  * [23:17] | ??? | Unknown | *UNDEFINED*
67  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP
68  * [31:25] | ??? | Unknown | *UNDEFINED*
69  *
70  */
71 /*
72  * Field : mpu_m0
73  *
74  * Security bit configuration for transactions from mpu_m0 to nand_register. When
75  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
76  * Non-Secure transactions are allowed.
77  *
78  * Field Access Macros:
79  *
80  */
81 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0 register field. */
82 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_LSB 0
83 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0 register field. */
84 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_MSB 0
85 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0 register field. */
86 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_WIDTH 1
87 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0 register field value. */
88 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_SET_MSK 0x00000001
89 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0 register field value. */
90 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_CLR_MSK 0xfffffffe
91 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0 register field. */
92 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_RESET 0x0
93 /* Extracts the ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0 field value from a register. */
94 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
95 /* Produces a ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0 register field value suitable for setting the register. */
96 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
97 
98 /*
99  * Field : dma
100  *
101  * Security bit configuration for transactions from dma to nand_register. When
102  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
103  * Non-Secure transactions are allowed.
104  *
105  * Field Access Macros:
106  *
107  */
108 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA register field. */
109 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_LSB 8
110 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA register field. */
111 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_MSB 8
112 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA register field. */
113 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_WIDTH 1
114 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA register field value. */
115 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_SET_MSK 0x00000100
116 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA register field value. */
117 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_CLR_MSK 0xfffffeff
118 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA register field. */
119 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_RESET 0x0
120 /* Extracts the ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA field value from a register. */
121 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_GET(value) (((value) & 0x00000100) >> 8)
122 /* Produces a ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA register field value suitable for setting the register. */
123 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_SET(value) (((value) << 8) & 0x00000100)
124 
125 /*
126  * Field : fpga2soc
127  *
128  * Security bit configuration for transactions from fpga2soc to nand_register. When
129  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
130  * Non-Secure transactions are allowed.
131  *
132  * Field Access Macros:
133  *
134  */
135 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H register field. */
136 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_LSB 16
137 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H register field. */
138 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_MSB 16
139 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H register field. */
140 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_WIDTH 1
141 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H register field value. */
142 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_SET_MSK 0x00010000
143 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H register field value. */
144 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_CLR_MSK 0xfffeffff
145 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H register field. */
146 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_RESET 0x0
147 /* Extracts the ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H field value from a register. */
148 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
149 /* Produces a ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H register field value suitable for setting the register. */
150 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
151 
152 /*
153  * Field : ahb_ap
154  *
155  * Security bit configuration for transactions from ahb_ap to nand_register. When
156  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
157  * Non-Secure transactions are allowed.
158  *
159  * Field Access Macros:
160  *
161  */
162 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP register field. */
163 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_LSB 24
164 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP register field. */
165 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_MSB 24
166 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP register field. */
167 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_WIDTH 1
168 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP register field value. */
169 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_SET_MSK 0x01000000
170 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP register field value. */
171 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_CLR_MSK 0xfeffffff
172 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP register field. */
173 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_RESET 0x0
174 /* Extracts the ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP field value from a register. */
175 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
176 /* Produces a ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP register field value suitable for setting the register. */
177 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
178 
179 #ifndef __ASSEMBLY__
180 /*
181  * WARNING: The C register and register group struct declarations are provided for
182  * convenience and illustrative purposes. They should, however, be used with
183  * caution as the C language standard provides no guarantees about the alignment or
184  * atomicity of device memory accesses. The recommended practice for writing
185  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
186  * alt_write_word() functions.
187  *
188  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_NAND_REG.
189  */
190 struct ALT_NOC_FW_L4_PER_SCR_NAND_REG_s
191 {
192  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0 */
193  uint32_t : 7; /* *UNDEFINED* */
194  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA */
195  uint32_t : 7; /* *UNDEFINED* */
196  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H */
197  uint32_t : 7; /* *UNDEFINED* */
198  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP */
199  uint32_t : 7; /* *UNDEFINED* */
200 };
201 
202 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_NAND_REG. */
203 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_NAND_REG_s ALT_NOC_FW_L4_PER_SCR_NAND_REG_t;
204 #endif /* __ASSEMBLY__ */
205 
206 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_NAND_REG register. */
207 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_RESET 0x00000000
208 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_NAND_REG register from the beginning of the component. */
209 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_OFST 0x0
210 
211 /*
212  * Register : nand_data
213  *
214  * Per-Master Security bit for nand_data
215  *
216  * Register Layout
217  *
218  * Bits | Access | Reset | Description
219  * :--------|:-------|:--------|:---------------------------------------
220  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0
221  * [7:1] | ??? | Unknown | *UNDEFINED*
222  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA
223  * [15:9] | ??? | Unknown | *UNDEFINED*
224  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H
225  * [23:17] | ??? | Unknown | *UNDEFINED*
226  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP
227  * [31:25] | ??? | Unknown | *UNDEFINED*
228  *
229  */
230 /*
231  * Field : mpu_m0
232  *
233  * Security bit configuration for transactions from mpu_m0 to nand_data. When
234  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
235  * Non-Secure transactions are allowed.
236  *
237  * Field Access Macros:
238  *
239  */
240 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0 register field. */
241 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_LSB 0
242 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0 register field. */
243 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_MSB 0
244 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0 register field. */
245 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_WIDTH 1
246 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0 register field value. */
247 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_SET_MSK 0x00000001
248 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0 register field value. */
249 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_CLR_MSK 0xfffffffe
250 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0 register field. */
251 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_RESET 0x0
252 /* Extracts the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0 field value from a register. */
253 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
254 /* Produces a ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0 register field value suitable for setting the register. */
255 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
256 
257 /*
258  * Field : dma
259  *
260  * Security bit configuration for transactions from dma to nand_data. When cleared
261  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
262  * Secure transactions are allowed.
263  *
264  * Field Access Macros:
265  *
266  */
267 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA register field. */
268 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_LSB 8
269 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA register field. */
270 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_MSB 8
271 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA register field. */
272 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_WIDTH 1
273 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA register field value. */
274 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_SET_MSK 0x00000100
275 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA register field value. */
276 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_CLR_MSK 0xfffffeff
277 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA register field. */
278 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_RESET 0x0
279 /* Extracts the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA field value from a register. */
280 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_GET(value) (((value) & 0x00000100) >> 8)
281 /* Produces a ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA register field value suitable for setting the register. */
282 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_SET(value) (((value) << 8) & 0x00000100)
283 
284 /*
285  * Field : fpga2soc
286  *
287  * Security bit configuration for transactions from fpga2soc to nand_data. When
288  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
289  * Non-Secure transactions are allowed.
290  *
291  * Field Access Macros:
292  *
293  */
294 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H register field. */
295 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_LSB 16
296 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H register field. */
297 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_MSB 16
298 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H register field. */
299 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_WIDTH 1
300 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H register field value. */
301 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_SET_MSK 0x00010000
302 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H register field value. */
303 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_CLR_MSK 0xfffeffff
304 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H register field. */
305 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_RESET 0x0
306 /* Extracts the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H field value from a register. */
307 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_GET(value) (((value) & 0x00010000) >> 16)
308 /* Produces a ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H register field value suitable for setting the register. */
309 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_SET(value) (((value) << 16) & 0x00010000)
310 
311 /*
312  * Field : ahb_ap
313  *
314  * Security bit configuration for transactions from ahb_ap to nand_data. When
315  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
316  * Non-Secure transactions are allowed.
317  *
318  * Field Access Macros:
319  *
320  */
321 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP register field. */
322 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_LSB 24
323 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP register field. */
324 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_MSB 24
325 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP register field. */
326 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_WIDTH 1
327 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP register field value. */
328 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_SET_MSK 0x01000000
329 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP register field value. */
330 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_CLR_MSK 0xfeffffff
331 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP register field. */
332 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_RESET 0x0
333 /* Extracts the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP field value from a register. */
334 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
335 /* Produces a ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP register field value suitable for setting the register. */
336 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
337 
338 #ifndef __ASSEMBLY__
339 /*
340  * WARNING: The C register and register group struct declarations are provided for
341  * convenience and illustrative purposes. They should, however, be used with
342  * caution as the C language standard provides no guarantees about the alignment or
343  * atomicity of device memory accesses. The recommended practice for writing
344  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
345  * alt_write_word() functions.
346  *
347  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_NAND_DATA.
348  */
349 struct ALT_NOC_FW_L4_PER_SCR_NAND_DATA_s
350 {
351  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0 */
352  uint32_t : 7; /* *UNDEFINED* */
353  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA */
354  uint32_t : 7; /* *UNDEFINED* */
355  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H */
356  uint32_t : 7; /* *UNDEFINED* */
357  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP */
358  uint32_t : 7; /* *UNDEFINED* */
359 };
360 
361 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_NAND_DATA. */
362 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_NAND_DATA_s ALT_NOC_FW_L4_PER_SCR_NAND_DATA_t;
363 #endif /* __ASSEMBLY__ */
364 
365 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA register. */
366 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_RESET 0x00000000
367 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA register from the beginning of the component. */
368 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_OFST 0x4
369 
370 /*
371  * Register : qspi_data
372  *
373  * Per-Master Security bit for qspi_data
374  *
375  * Register Layout
376  *
377  * Bits | Access | Reset | Description
378  * :--------|:-------|:--------|:---------------------------------------
379  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0
380  * [7:1] | ??? | Unknown | *UNDEFINED*
381  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA
382  * [15:9] | ??? | Unknown | *UNDEFINED*
383  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H
384  * [23:17] | ??? | Unknown | *UNDEFINED*
385  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP
386  * [31:25] | ??? | Unknown | *UNDEFINED*
387  *
388  */
389 /*
390  * Field : mpu_m0
391  *
392  * Security bit configuration for transactions from mpu_m0 to qspi_data. When
393  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
394  * Non-Secure transactions are allowed.
395  *
396  * Field Access Macros:
397  *
398  */
399 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0 register field. */
400 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_LSB 0
401 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0 register field. */
402 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_MSB 0
403 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0 register field. */
404 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_WIDTH 1
405 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0 register field value. */
406 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_SET_MSK 0x00000001
407 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0 register field value. */
408 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_CLR_MSK 0xfffffffe
409 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0 register field. */
410 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_RESET 0x0
411 /* Extracts the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0 field value from a register. */
412 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
413 /* Produces a ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0 register field value suitable for setting the register. */
414 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
415 
416 /*
417  * Field : dma
418  *
419  * Security bit configuration for transactions from dma to qspi_data. When cleared
420  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
421  * Secure transactions are allowed.
422  *
423  * Field Access Macros:
424  *
425  */
426 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA register field. */
427 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_LSB 8
428 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA register field. */
429 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_MSB 8
430 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA register field. */
431 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_WIDTH 1
432 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA register field value. */
433 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_SET_MSK 0x00000100
434 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA register field value. */
435 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_CLR_MSK 0xfffffeff
436 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA register field. */
437 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_RESET 0x0
438 /* Extracts the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA field value from a register. */
439 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_GET(value) (((value) & 0x00000100) >> 8)
440 /* Produces a ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA register field value suitable for setting the register. */
441 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_SET(value) (((value) << 8) & 0x00000100)
442 
443 /*
444  * Field : fpga2soc
445  *
446  * Security bit configuration for transactions from fpga2soc to qspi_data. When
447  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
448  * Non-Secure transactions are allowed.
449  *
450  * Field Access Macros:
451  *
452  */
453 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H register field. */
454 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_LSB 16
455 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H register field. */
456 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_MSB 16
457 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H register field. */
458 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_WIDTH 1
459 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H register field value. */
460 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_SET_MSK 0x00010000
461 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H register field value. */
462 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_CLR_MSK 0xfffeffff
463 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H register field. */
464 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_RESET 0x0
465 /* Extracts the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H field value from a register. */
466 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_GET(value) (((value) & 0x00010000) >> 16)
467 /* Produces a ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H register field value suitable for setting the register. */
468 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_SET(value) (((value) << 16) & 0x00010000)
469 
470 /*
471  * Field : ahb_ap
472  *
473  * Security bit configuration for transactions from ahb_ap to qspi_data. When
474  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
475  * Non-Secure transactions are allowed.
476  *
477  * Field Access Macros:
478  *
479  */
480 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP register field. */
481 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_LSB 24
482 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP register field. */
483 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_MSB 24
484 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP register field. */
485 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_WIDTH 1
486 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP register field value. */
487 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_SET_MSK 0x01000000
488 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP register field value. */
489 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_CLR_MSK 0xfeffffff
490 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP register field. */
491 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_RESET 0x0
492 /* Extracts the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP field value from a register. */
493 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
494 /* Produces a ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP register field value suitable for setting the register. */
495 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
496 
497 #ifndef __ASSEMBLY__
498 /*
499  * WARNING: The C register and register group struct declarations are provided for
500  * convenience and illustrative purposes. They should, however, be used with
501  * caution as the C language standard provides no guarantees about the alignment or
502  * atomicity of device memory accesses. The recommended practice for writing
503  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
504  * alt_write_word() functions.
505  *
506  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_QSPI_DATA.
507  */
508 struct ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_s
509 {
510  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0 */
511  uint32_t : 7; /* *UNDEFINED* */
512  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA */
513  uint32_t : 7; /* *UNDEFINED* */
514  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H */
515  uint32_t : 7; /* *UNDEFINED* */
516  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP */
517  uint32_t : 7; /* *UNDEFINED* */
518 };
519 
520 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_QSPI_DATA. */
521 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_s ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_t;
522 #endif /* __ASSEMBLY__ */
523 
524 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA register. */
525 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_RESET 0x00000000
526 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_QSPI_DATA register from the beginning of the component. */
527 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_OFST 0x8
528 
529 /*
530  * Register : usb0_register
531  *
532  * Per-Master Security bit for usb0_register
533  *
534  * Register Layout
535  *
536  * Bits | Access | Reset | Description
537  * :--------|:-------|:--------|:--------------------------------------
538  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0
539  * [7:1] | ??? | Unknown | *UNDEFINED*
540  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA
541  * [15:9] | ??? | Unknown | *UNDEFINED*
542  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H
543  * [23:17] | ??? | Unknown | *UNDEFINED*
544  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP
545  * [31:25] | ??? | Unknown | *UNDEFINED*
546  *
547  */
548 /*
549  * Field : mpu_m0
550  *
551  * Security bit configuration for transactions from mpu_m0 to usb0_register. When
552  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
553  * Non-Secure transactions are allowed.
554  *
555  * Field Access Macros:
556  *
557  */
558 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0 register field. */
559 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_LSB 0
560 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0 register field. */
561 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_MSB 0
562 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0 register field. */
563 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_WIDTH 1
564 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0 register field value. */
565 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_SET_MSK 0x00000001
566 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0 register field value. */
567 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_CLR_MSK 0xfffffffe
568 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0 register field. */
569 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_RESET 0x0
570 /* Extracts the ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0 field value from a register. */
571 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
572 /* Produces a ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0 register field value suitable for setting the register. */
573 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
574 
575 /*
576  * Field : dma
577  *
578  * Security bit configuration for transactions from dma to usb0_register. When
579  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
580  * Non-Secure transactions are allowed.
581  *
582  * Field Access Macros:
583  *
584  */
585 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA register field. */
586 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_LSB 8
587 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA register field. */
588 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_MSB 8
589 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA register field. */
590 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_WIDTH 1
591 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA register field value. */
592 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_SET_MSK 0x00000100
593 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA register field value. */
594 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_CLR_MSK 0xfffffeff
595 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA register field. */
596 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_RESET 0x0
597 /* Extracts the ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA field value from a register. */
598 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_GET(value) (((value) & 0x00000100) >> 8)
599 /* Produces a ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA register field value suitable for setting the register. */
600 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_SET(value) (((value) << 8) & 0x00000100)
601 
602 /*
603  * Field : fpga2soc
604  *
605  * Security bit configuration for transactions from fpga2soc to usb0_register. When
606  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
607  * Non-Secure transactions are allowed.
608  *
609  * Field Access Macros:
610  *
611  */
612 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H register field. */
613 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_LSB 16
614 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H register field. */
615 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_MSB 16
616 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H register field. */
617 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_WIDTH 1
618 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H register field value. */
619 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_SET_MSK 0x00010000
620 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H register field value. */
621 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_CLR_MSK 0xfffeffff
622 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H register field. */
623 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_RESET 0x0
624 /* Extracts the ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H field value from a register. */
625 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
626 /* Produces a ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H register field value suitable for setting the register. */
627 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
628 
629 /*
630  * Field : ahb_ap
631  *
632  * Security bit configuration for transactions from ahb_ap to usb0_register. When
633  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
634  * Non-Secure transactions are allowed.
635  *
636  * Field Access Macros:
637  *
638  */
639 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP register field. */
640 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_LSB 24
641 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP register field. */
642 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_MSB 24
643 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP register field. */
644 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_WIDTH 1
645 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP register field value. */
646 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_SET_MSK 0x01000000
647 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP register field value. */
648 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_CLR_MSK 0xfeffffff
649 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP register field. */
650 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_RESET 0x0
651 /* Extracts the ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP field value from a register. */
652 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
653 /* Produces a ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP register field value suitable for setting the register. */
654 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
655 
656 #ifndef __ASSEMBLY__
657 /*
658  * WARNING: The C register and register group struct declarations are provided for
659  * convenience and illustrative purposes. They should, however, be used with
660  * caution as the C language standard provides no guarantees about the alignment or
661  * atomicity of device memory accesses. The recommended practice for writing
662  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
663  * alt_write_word() functions.
664  *
665  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_USB0_REG.
666  */
667 struct ALT_NOC_FW_L4_PER_SCR_USB0_REG_s
668 {
669  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0 */
670  uint32_t : 7; /* *UNDEFINED* */
671  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA */
672  uint32_t : 7; /* *UNDEFINED* */
673  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H */
674  uint32_t : 7; /* *UNDEFINED* */
675  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP */
676  uint32_t : 7; /* *UNDEFINED* */
677 };
678 
679 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_USB0_REG. */
680 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_USB0_REG_s ALT_NOC_FW_L4_PER_SCR_USB0_REG_t;
681 #endif /* __ASSEMBLY__ */
682 
683 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_USB0_REG register. */
684 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_RESET 0x00000000
685 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_USB0_REG register from the beginning of the component. */
686 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_OFST 0xc
687 
688 /*
689  * Register : usb1_register
690  *
691  * Per-Master Security bit for usb1_register
692  *
693  * Register Layout
694  *
695  * Bits | Access | Reset | Description
696  * :--------|:-------|:--------|:--------------------------------------
697  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0
698  * [7:1] | ??? | Unknown | *UNDEFINED*
699  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA
700  * [15:9] | ??? | Unknown | *UNDEFINED*
701  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H
702  * [23:17] | ??? | Unknown | *UNDEFINED*
703  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP
704  * [31:25] | ??? | Unknown | *UNDEFINED*
705  *
706  */
707 /*
708  * Field : mpu_m0
709  *
710  * Security bit configuration for transactions from mpu_m0 to usb1_register. When
711  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
712  * Non-Secure transactions are allowed.
713  *
714  * Field Access Macros:
715  *
716  */
717 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0 register field. */
718 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_LSB 0
719 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0 register field. */
720 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_MSB 0
721 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0 register field. */
722 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_WIDTH 1
723 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0 register field value. */
724 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_SET_MSK 0x00000001
725 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0 register field value. */
726 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_CLR_MSK 0xfffffffe
727 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0 register field. */
728 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_RESET 0x0
729 /* Extracts the ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0 field value from a register. */
730 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
731 /* Produces a ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0 register field value suitable for setting the register. */
732 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
733 
734 /*
735  * Field : dma
736  *
737  * Security bit configuration for transactions from dma to usb1_register. When
738  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
739  * Non-Secure transactions are allowed.
740  *
741  * Field Access Macros:
742  *
743  */
744 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA register field. */
745 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_LSB 8
746 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA register field. */
747 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_MSB 8
748 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA register field. */
749 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_WIDTH 1
750 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA register field value. */
751 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_SET_MSK 0x00000100
752 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA register field value. */
753 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_CLR_MSK 0xfffffeff
754 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA register field. */
755 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_RESET 0x0
756 /* Extracts the ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA field value from a register. */
757 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_GET(value) (((value) & 0x00000100) >> 8)
758 /* Produces a ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA register field value suitable for setting the register. */
759 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_SET(value) (((value) << 8) & 0x00000100)
760 
761 /*
762  * Field : fpga2soc
763  *
764  * Security bit configuration for transactions from fpga2soc to usb1_register. When
765  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
766  * Non-Secure transactions are allowed.
767  *
768  * Field Access Macros:
769  *
770  */
771 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H register field. */
772 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_LSB 16
773 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H register field. */
774 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_MSB 16
775 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H register field. */
776 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_WIDTH 1
777 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H register field value. */
778 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_SET_MSK 0x00010000
779 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H register field value. */
780 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_CLR_MSK 0xfffeffff
781 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H register field. */
782 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_RESET 0x0
783 /* Extracts the ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H field value from a register. */
784 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
785 /* Produces a ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H register field value suitable for setting the register. */
786 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
787 
788 /*
789  * Field : ahb_ap
790  *
791  * Security bit configuration for transactions from ahb_ap to usb1_register. When
792  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
793  * Non-Secure transactions are allowed.
794  *
795  * Field Access Macros:
796  *
797  */
798 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP register field. */
799 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_LSB 24
800 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP register field. */
801 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_MSB 24
802 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP register field. */
803 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_WIDTH 1
804 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP register field value. */
805 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_SET_MSK 0x01000000
806 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP register field value. */
807 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_CLR_MSK 0xfeffffff
808 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP register field. */
809 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_RESET 0x0
810 /* Extracts the ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP field value from a register. */
811 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
812 /* Produces a ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP register field value suitable for setting the register. */
813 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
814 
815 #ifndef __ASSEMBLY__
816 /*
817  * WARNING: The C register and register group struct declarations are provided for
818  * convenience and illustrative purposes. They should, however, be used with
819  * caution as the C language standard provides no guarantees about the alignment or
820  * atomicity of device memory accesses. The recommended practice for writing
821  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
822  * alt_write_word() functions.
823  *
824  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_USB1_REG.
825  */
826 struct ALT_NOC_FW_L4_PER_SCR_USB1_REG_s
827 {
828  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0 */
829  uint32_t : 7; /* *UNDEFINED* */
830  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA */
831  uint32_t : 7; /* *UNDEFINED* */
832  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H */
833  uint32_t : 7; /* *UNDEFINED* */
834  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP */
835  uint32_t : 7; /* *UNDEFINED* */
836 };
837 
838 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_USB1_REG. */
839 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_USB1_REG_s ALT_NOC_FW_L4_PER_SCR_USB1_REG_t;
840 #endif /* __ASSEMBLY__ */
841 
842 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_USB1_REG register. */
843 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_RESET 0x00000000
844 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_USB1_REG register from the beginning of the component. */
845 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_OFST 0x10
846 
847 /*
848  * Register : dma_nonsecure
849  *
850  * Per-Master Security bit for dma_nonsecure
851  *
852  * Register Layout
853  *
854  * Bits | Access | Reset | Description
855  * :-------|:-------|:------|:-----------------------------------------
856  * [31:0] | RW | 0x1 | ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD
857  *
858  */
859 /*
860  * Field : Reserved
861  *
862  * Field Access Macros:
863  *
864  */
865 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD register field. */
866 #define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_LSB 0
867 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD register field. */
868 #define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_MSB 31
869 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD register field. */
870 #define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_WIDTH 32
871 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD register field value. */
872 #define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_SET_MSK 0xffffffff
873 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD register field value. */
874 #define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_CLR_MSK 0x00000000
875 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD register field. */
876 #define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_RESET 0x1
877 /* Extracts the ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD field value from a register. */
878 #define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
879 /* Produces a ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD register field value suitable for setting the register. */
880 #define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_SET(value) (((value) << 0) & 0xffffffff)
881 
882 #ifndef __ASSEMBLY__
883 /*
884  * WARNING: The C register and register group struct declarations are provided for
885  * convenience and illustrative purposes. They should, however, be used with
886  * caution as the C language standard provides no guarantees about the alignment or
887  * atomicity of device memory accesses. The recommended practice for writing
888  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
889  * alt_write_word() functions.
890  *
891  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE.
892  */
893 struct ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_s
894 {
895  uint32_t Reserved : 32; /* ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD */
896 };
897 
898 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE. */
899 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_s ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_t;
900 #endif /* __ASSEMBLY__ */
901 
902 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE register. */
903 #define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RESET 0x00000001
904 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE register from the beginning of the component. */
905 #define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_OFST 0x14
906 
907 /*
908  * Register : dma_secure
909  *
910  * Per-Master Security bit for dma_secure
911  *
912  * Register Layout
913  *
914  * Bits | Access | Reset | Description
915  * :-------|:-------|:------|:--------------------------------------
916  * [31:0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD
917  *
918  */
919 /*
920  * Field : Reserved
921  *
922  * Field Access Macros:
923  *
924  */
925 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD register field. */
926 #define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_LSB 0
927 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD register field. */
928 #define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_MSB 31
929 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD register field. */
930 #define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_WIDTH 32
931 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD register field value. */
932 #define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_SET_MSK 0xffffffff
933 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD register field value. */
934 #define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_CLR_MSK 0x00000000
935 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD register field. */
936 #define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_RESET 0x0
937 /* Extracts the ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD field value from a register. */
938 #define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
939 /* Produces a ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD register field value suitable for setting the register. */
940 #define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_SET(value) (((value) << 0) & 0xffffffff)
941 
942 #ifndef __ASSEMBLY__
943 /*
944  * WARNING: The C register and register group struct declarations are provided for
945  * convenience and illustrative purposes. They should, however, be used with
946  * caution as the C language standard provides no guarantees about the alignment or
947  * atomicity of device memory accesses. The recommended practice for writing
948  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
949  * alt_write_word() functions.
950  *
951  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_DMA_SECURE.
952  */
953 struct ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_s
954 {
955  uint32_t Reserved : 32; /* ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD */
956 };
957 
958 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_DMA_SECURE. */
959 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_s ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_t;
960 #endif /* __ASSEMBLY__ */
961 
962 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_DMA_SECURE register. */
963 #define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RESET 0x00000000
964 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_DMA_SECURE register from the beginning of the component. */
965 #define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_OFST 0x18
966 
967 /*
968  * Register : spi_master0
969  *
970  * Per-Master Security bit for spi_master0
971  *
972  * Register Layout
973  *
974  * Bits | Access | Reset | Description
975  * :--------|:-------|:--------|:--------------------------------------
976  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0
977  * [7:1] | ??? | Unknown | *UNDEFINED*
978  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA
979  * [15:9] | ??? | Unknown | *UNDEFINED*
980  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H
981  * [23:17] | ??? | Unknown | *UNDEFINED*
982  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP
983  * [31:25] | ??? | Unknown | *UNDEFINED*
984  *
985  */
986 /*
987  * Field : mpu_m0
988  *
989  * Security bit configuration for transactions from mpu_m0 to spi_master0. When
990  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
991  * Non-Secure transactions are allowed.
992  *
993  * Field Access Macros:
994  *
995  */
996 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0 register field. */
997 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_LSB 0
998 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0 register field. */
999 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_MSB 0
1000 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0 register field. */
1001 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_WIDTH 1
1002 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0 register field value. */
1003 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_SET_MSK 0x00000001
1004 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0 register field value. */
1005 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_CLR_MSK 0xfffffffe
1006 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0 register field. */
1007 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_RESET 0x0
1008 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0 field value from a register. */
1009 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1010 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0 register field value suitable for setting the register. */
1011 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1012 
1013 /*
1014  * Field : dma
1015  *
1016  * Security bit configuration for transactions from dma to spi_master0. When
1017  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1018  * Non-Secure transactions are allowed.
1019  *
1020  * Field Access Macros:
1021  *
1022  */
1023 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA register field. */
1024 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_LSB 8
1025 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA register field. */
1026 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_MSB 8
1027 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA register field. */
1028 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_WIDTH 1
1029 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA register field value. */
1030 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_SET_MSK 0x00000100
1031 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA register field value. */
1032 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_CLR_MSK 0xfffffeff
1033 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA register field. */
1034 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_RESET 0x0
1035 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA field value from a register. */
1036 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_GET(value) (((value) & 0x00000100) >> 8)
1037 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA register field value suitable for setting the register. */
1038 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_SET(value) (((value) << 8) & 0x00000100)
1039 
1040 /*
1041  * Field : fpga2soc
1042  *
1043  * Security bit configuration for transactions from fpga2soc to spi_master0. When
1044  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1045  * Non-Secure transactions are allowed.
1046  *
1047  * Field Access Macros:
1048  *
1049  */
1050 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H register field. */
1051 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_LSB 16
1052 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H register field. */
1053 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_MSB 16
1054 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H register field. */
1055 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_WIDTH 1
1056 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H register field value. */
1057 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_SET_MSK 0x00010000
1058 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H register field value. */
1059 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_CLR_MSK 0xfffeffff
1060 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H register field. */
1061 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_RESET 0x0
1062 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H field value from a register. */
1063 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_GET(value) (((value) & 0x00010000) >> 16)
1064 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H register field value suitable for setting the register. */
1065 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_SET(value) (((value) << 16) & 0x00010000)
1066 
1067 /*
1068  * Field : ahb_ap
1069  *
1070  * Security bit configuration for transactions from ahb_ap to spi_master0. When
1071  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1072  * Non-Secure transactions are allowed.
1073  *
1074  * Field Access Macros:
1075  *
1076  */
1077 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP register field. */
1078 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_LSB 24
1079 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP register field. */
1080 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_MSB 24
1081 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP register field. */
1082 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_WIDTH 1
1083 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP register field value. */
1084 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_SET_MSK 0x01000000
1085 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP register field value. */
1086 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_CLR_MSK 0xfeffffff
1087 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP register field. */
1088 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_RESET 0x0
1089 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP field value from a register. */
1090 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1091 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP register field value suitable for setting the register. */
1092 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1093 
1094 #ifndef __ASSEMBLY__
1095 /*
1096  * WARNING: The C register and register group struct declarations are provided for
1097  * convenience and illustrative purposes. They should, however, be used with
1098  * caution as the C language standard provides no guarantees about the alignment or
1099  * atomicity of device memory accesses. The recommended practice for writing
1100  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1101  * alt_write_word() functions.
1102  *
1103  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_SPI_MST0.
1104  */
1105 struct ALT_NOC_FW_L4_PER_SCR_SPI_MST0_s
1106 {
1107  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0 */
1108  uint32_t : 7; /* *UNDEFINED* */
1109  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA */
1110  uint32_t : 7; /* *UNDEFINED* */
1111  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H */
1112  uint32_t : 7; /* *UNDEFINED* */
1113  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP */
1114  uint32_t : 7; /* *UNDEFINED* */
1115 };
1116 
1117 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_SPI_MST0. */
1118 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_SPI_MST0_s ALT_NOC_FW_L4_PER_SCR_SPI_MST0_t;
1119 #endif /* __ASSEMBLY__ */
1120 
1121 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_MST0 register. */
1122 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_RESET 0x00000000
1123 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_SPI_MST0 register from the beginning of the component. */
1124 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_OFST 0x1c
1125 
1126 /*
1127  * Register : spi_master1
1128  *
1129  * Per-Master Security bit for spi_master1
1130  *
1131  * Register Layout
1132  *
1133  * Bits | Access | Reset | Description
1134  * :--------|:-------|:--------|:--------------------------------------
1135  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0
1136  * [7:1] | ??? | Unknown | *UNDEFINED*
1137  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA
1138  * [15:9] | ??? | Unknown | *UNDEFINED*
1139  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H
1140  * [23:17] | ??? | Unknown | *UNDEFINED*
1141  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP
1142  * [31:25] | ??? | Unknown | *UNDEFINED*
1143  *
1144  */
1145 /*
1146  * Field : mpu_m0
1147  *
1148  * Security bit configuration for transactions from mpu_m0 to spi_master1. When
1149  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1150  * Non-Secure transactions are allowed.
1151  *
1152  * Field Access Macros:
1153  *
1154  */
1155 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0 register field. */
1156 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_LSB 0
1157 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0 register field. */
1158 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_MSB 0
1159 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0 register field. */
1160 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_WIDTH 1
1161 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0 register field value. */
1162 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_SET_MSK 0x00000001
1163 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0 register field value. */
1164 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_CLR_MSK 0xfffffffe
1165 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0 register field. */
1166 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_RESET 0x0
1167 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0 field value from a register. */
1168 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1169 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0 register field value suitable for setting the register. */
1170 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1171 
1172 /*
1173  * Field : dma
1174  *
1175  * Security bit configuration for transactions from dma to spi_master1. When
1176  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1177  * Non-Secure transactions are allowed.
1178  *
1179  * Field Access Macros:
1180  *
1181  */
1182 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA register field. */
1183 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_LSB 8
1184 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA register field. */
1185 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_MSB 8
1186 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA register field. */
1187 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_WIDTH 1
1188 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA register field value. */
1189 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_SET_MSK 0x00000100
1190 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA register field value. */
1191 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_CLR_MSK 0xfffffeff
1192 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA register field. */
1193 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_RESET 0x0
1194 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA field value from a register. */
1195 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_GET(value) (((value) & 0x00000100) >> 8)
1196 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA register field value suitable for setting the register. */
1197 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_SET(value) (((value) << 8) & 0x00000100)
1198 
1199 /*
1200  * Field : fpga2soc
1201  *
1202  * Security bit configuration for transactions from fpga2soc to spi_master1. When
1203  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1204  * Non-Secure transactions are allowed.
1205  *
1206  * Field Access Macros:
1207  *
1208  */
1209 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H register field. */
1210 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_LSB 16
1211 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H register field. */
1212 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_MSB 16
1213 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H register field. */
1214 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_WIDTH 1
1215 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H register field value. */
1216 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_SET_MSK 0x00010000
1217 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H register field value. */
1218 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_CLR_MSK 0xfffeffff
1219 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H register field. */
1220 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_RESET 0x0
1221 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H field value from a register. */
1222 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_GET(value) (((value) & 0x00010000) >> 16)
1223 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H register field value suitable for setting the register. */
1224 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_SET(value) (((value) << 16) & 0x00010000)
1225 
1226 /*
1227  * Field : ahb_ap
1228  *
1229  * Security bit configuration for transactions from ahb_ap to spi_master1. When
1230  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1231  * Non-Secure transactions are allowed.
1232  *
1233  * Field Access Macros:
1234  *
1235  */
1236 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP register field. */
1237 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_LSB 24
1238 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP register field. */
1239 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_MSB 24
1240 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP register field. */
1241 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_WIDTH 1
1242 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP register field value. */
1243 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_SET_MSK 0x01000000
1244 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP register field value. */
1245 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_CLR_MSK 0xfeffffff
1246 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP register field. */
1247 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_RESET 0x0
1248 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP field value from a register. */
1249 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1250 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP register field value suitable for setting the register. */
1251 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1252 
1253 #ifndef __ASSEMBLY__
1254 /*
1255  * WARNING: The C register and register group struct declarations are provided for
1256  * convenience and illustrative purposes. They should, however, be used with
1257  * caution as the C language standard provides no guarantees about the alignment or
1258  * atomicity of device memory accesses. The recommended practice for writing
1259  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1260  * alt_write_word() functions.
1261  *
1262  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_SPI_MST1.
1263  */
1264 struct ALT_NOC_FW_L4_PER_SCR_SPI_MST1_s
1265 {
1266  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0 */
1267  uint32_t : 7; /* *UNDEFINED* */
1268  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA */
1269  uint32_t : 7; /* *UNDEFINED* */
1270  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H */
1271  uint32_t : 7; /* *UNDEFINED* */
1272  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP */
1273  uint32_t : 7; /* *UNDEFINED* */
1274 };
1275 
1276 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_SPI_MST1. */
1277 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_SPI_MST1_s ALT_NOC_FW_L4_PER_SCR_SPI_MST1_t;
1278 #endif /* __ASSEMBLY__ */
1279 
1280 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_MST1 register. */
1281 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_RESET 0x00000000
1282 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_SPI_MST1 register from the beginning of the component. */
1283 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_OFST 0x20
1284 
1285 /*
1286  * Register : spi_slave0
1287  *
1288  * Per-Master Security bit for spi_slave0
1289  *
1290  * Register Layout
1291  *
1292  * Bits | Access | Reset | Description
1293  * :--------|:-------|:--------|:--------------------------------------
1294  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0
1295  * [7:1] | ??? | Unknown | *UNDEFINED*
1296  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA
1297  * [15:9] | ??? | Unknown | *UNDEFINED*
1298  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H
1299  * [23:17] | ??? | Unknown | *UNDEFINED*
1300  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP
1301  * [31:25] | ??? | Unknown | *UNDEFINED*
1302  *
1303  */
1304 /*
1305  * Field : mpu_m0
1306  *
1307  * Security bit configuration for transactions from mpu_m0 to spi_slave0. When
1308  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1309  * Non-Secure transactions are allowed.
1310  *
1311  * Field Access Macros:
1312  *
1313  */
1314 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0 register field. */
1315 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_LSB 0
1316 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0 register field. */
1317 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_MSB 0
1318 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0 register field. */
1319 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_WIDTH 1
1320 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0 register field value. */
1321 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_SET_MSK 0x00000001
1322 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0 register field value. */
1323 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_CLR_MSK 0xfffffffe
1324 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0 register field. */
1325 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_RESET 0x0
1326 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0 field value from a register. */
1327 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1328 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0 register field value suitable for setting the register. */
1329 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1330 
1331 /*
1332  * Field : dma
1333  *
1334  * Security bit configuration for transactions from dma to spi_slave0. When cleared
1335  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1336  * Secure transactions are allowed.
1337  *
1338  * Field Access Macros:
1339  *
1340  */
1341 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA register field. */
1342 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_LSB 8
1343 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA register field. */
1344 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_MSB 8
1345 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA register field. */
1346 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_WIDTH 1
1347 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA register field value. */
1348 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_SET_MSK 0x00000100
1349 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA register field value. */
1350 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_CLR_MSK 0xfffffeff
1351 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA register field. */
1352 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_RESET 0x0
1353 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA field value from a register. */
1354 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_GET(value) (((value) & 0x00000100) >> 8)
1355 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA register field value suitable for setting the register. */
1356 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_SET(value) (((value) << 8) & 0x00000100)
1357 
1358 /*
1359  * Field : fpga2soc
1360  *
1361  * Security bit configuration for transactions from fpga2soc to spi_slave0. When
1362  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1363  * Non-Secure transactions are allowed.
1364  *
1365  * Field Access Macros:
1366  *
1367  */
1368 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H register field. */
1369 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_LSB 16
1370 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H register field. */
1371 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_MSB 16
1372 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H register field. */
1373 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_WIDTH 1
1374 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H register field value. */
1375 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_SET_MSK 0x00010000
1376 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H register field value. */
1377 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_CLR_MSK 0xfffeffff
1378 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H register field. */
1379 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_RESET 0x0
1380 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H field value from a register. */
1381 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_GET(value) (((value) & 0x00010000) >> 16)
1382 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H register field value suitable for setting the register. */
1383 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_SET(value) (((value) << 16) & 0x00010000)
1384 
1385 /*
1386  * Field : ahb_ap
1387  *
1388  * Security bit configuration for transactions from ahb_ap to spi_slave0. When
1389  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1390  * Non-Secure transactions are allowed.
1391  *
1392  * Field Access Macros:
1393  *
1394  */
1395 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP register field. */
1396 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_LSB 24
1397 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP register field. */
1398 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_MSB 24
1399 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP register field. */
1400 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_WIDTH 1
1401 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP register field value. */
1402 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_SET_MSK 0x01000000
1403 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP register field value. */
1404 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_CLR_MSK 0xfeffffff
1405 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP register field. */
1406 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_RESET 0x0
1407 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP field value from a register. */
1408 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1409 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP register field value suitable for setting the register. */
1410 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1411 
1412 #ifndef __ASSEMBLY__
1413 /*
1414  * WARNING: The C register and register group struct declarations are provided for
1415  * convenience and illustrative purposes. They should, however, be used with
1416  * caution as the C language standard provides no guarantees about the alignment or
1417  * atomicity of device memory accesses. The recommended practice for writing
1418  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1419  * alt_write_word() functions.
1420  *
1421  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_SPI_SLV0.
1422  */
1423 struct ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_s
1424 {
1425  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0 */
1426  uint32_t : 7; /* *UNDEFINED* */
1427  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA */
1428  uint32_t : 7; /* *UNDEFINED* */
1429  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H */
1430  uint32_t : 7; /* *UNDEFINED* */
1431  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP */
1432  uint32_t : 7; /* *UNDEFINED* */
1433 };
1434 
1435 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_SPI_SLV0. */
1436 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_s ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_t;
1437 #endif /* __ASSEMBLY__ */
1438 
1439 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0 register. */
1440 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_RESET 0x00000000
1441 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV0 register from the beginning of the component. */
1442 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_OFST 0x24
1443 
1444 /*
1445  * Register : spi_slave1
1446  *
1447  * Per-Master Security bit for spi_slave1
1448  *
1449  * Register Layout
1450  *
1451  * Bits | Access | Reset | Description
1452  * :--------|:-------|:--------|:--------------------------------------
1453  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0
1454  * [7:1] | ??? | Unknown | *UNDEFINED*
1455  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA
1456  * [15:9] | ??? | Unknown | *UNDEFINED*
1457  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H
1458  * [23:17] | ??? | Unknown | *UNDEFINED*
1459  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP
1460  * [31:25] | ??? | Unknown | *UNDEFINED*
1461  *
1462  */
1463 /*
1464  * Field : mpu_m0
1465  *
1466  * Security bit configuration for transactions from mpu_m0 to spi_slave1. When
1467  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1468  * Non-Secure transactions are allowed.
1469  *
1470  * Field Access Macros:
1471  *
1472  */
1473 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0 register field. */
1474 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_LSB 0
1475 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0 register field. */
1476 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_MSB 0
1477 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0 register field. */
1478 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_WIDTH 1
1479 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0 register field value. */
1480 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_SET_MSK 0x00000001
1481 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0 register field value. */
1482 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_CLR_MSK 0xfffffffe
1483 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0 register field. */
1484 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_RESET 0x0
1485 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0 field value from a register. */
1486 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1487 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0 register field value suitable for setting the register. */
1488 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1489 
1490 /*
1491  * Field : dma
1492  *
1493  * Security bit configuration for transactions from dma to spi_slave1. When cleared
1494  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1495  * Secure transactions are allowed.
1496  *
1497  * Field Access Macros:
1498  *
1499  */
1500 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA register field. */
1501 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_LSB 8
1502 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA register field. */
1503 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_MSB 8
1504 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA register field. */
1505 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_WIDTH 1
1506 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA register field value. */
1507 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_SET_MSK 0x00000100
1508 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA register field value. */
1509 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_CLR_MSK 0xfffffeff
1510 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA register field. */
1511 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_RESET 0x0
1512 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA field value from a register. */
1513 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_GET(value) (((value) & 0x00000100) >> 8)
1514 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA register field value suitable for setting the register. */
1515 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_SET(value) (((value) << 8) & 0x00000100)
1516 
1517 /*
1518  * Field : fpga2soc
1519  *
1520  * Security bit configuration for transactions from fpga2soc to spi_slave1. When
1521  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1522  * Non-Secure transactions are allowed.
1523  *
1524  * Field Access Macros:
1525  *
1526  */
1527 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H register field. */
1528 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_LSB 16
1529 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H register field. */
1530 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_MSB 16
1531 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H register field. */
1532 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_WIDTH 1
1533 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H register field value. */
1534 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_SET_MSK 0x00010000
1535 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H register field value. */
1536 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_CLR_MSK 0xfffeffff
1537 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H register field. */
1538 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_RESET 0x0
1539 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H field value from a register. */
1540 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_GET(value) (((value) & 0x00010000) >> 16)
1541 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H register field value suitable for setting the register. */
1542 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_SET(value) (((value) << 16) & 0x00010000)
1543 
1544 /*
1545  * Field : ahb_ap
1546  *
1547  * Security bit configuration for transactions from ahb_ap to spi_slave1. When
1548  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1549  * Non-Secure transactions are allowed.
1550  *
1551  * Field Access Macros:
1552  *
1553  */
1554 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP register field. */
1555 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_LSB 24
1556 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP register field. */
1557 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_MSB 24
1558 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP register field. */
1559 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_WIDTH 1
1560 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP register field value. */
1561 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_SET_MSK 0x01000000
1562 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP register field value. */
1563 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_CLR_MSK 0xfeffffff
1564 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP register field. */
1565 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_RESET 0x0
1566 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP field value from a register. */
1567 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1568 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP register field value suitable for setting the register. */
1569 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1570 
1571 #ifndef __ASSEMBLY__
1572 /*
1573  * WARNING: The C register and register group struct declarations are provided for
1574  * convenience and illustrative purposes. They should, however, be used with
1575  * caution as the C language standard provides no guarantees about the alignment or
1576  * atomicity of device memory accesses. The recommended practice for writing
1577  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1578  * alt_write_word() functions.
1579  *
1580  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_SPI_SLV1.
1581  */
1582 struct ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_s
1583 {
1584  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0 */
1585  uint32_t : 7; /* *UNDEFINED* */
1586  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA */
1587  uint32_t : 7; /* *UNDEFINED* */
1588  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H */
1589  uint32_t : 7; /* *UNDEFINED* */
1590  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP */
1591  uint32_t : 7; /* *UNDEFINED* */
1592 };
1593 
1594 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_SPI_SLV1. */
1595 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_s ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_t;
1596 #endif /* __ASSEMBLY__ */
1597 
1598 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1 register. */
1599 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_RESET 0x00000000
1600 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_SPI_SLV1 register from the beginning of the component. */
1601 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_OFST 0x28
1602 
1603 /*
1604  * Register : emac0
1605  *
1606  * Per-Master Security bit for emac0
1607  *
1608  * Register Layout
1609  *
1610  * Bits | Access | Reset | Description
1611  * :--------|:-------|:--------|:-----------------------------------
1612  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0
1613  * [7:1] | ??? | Unknown | *UNDEFINED*
1614  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA
1615  * [15:9] | ??? | Unknown | *UNDEFINED*
1616  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H
1617  * [23:17] | ??? | Unknown | *UNDEFINED*
1618  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP
1619  * [31:25] | ??? | Unknown | *UNDEFINED*
1620  *
1621  */
1622 /*
1623  * Field : mpu_m0
1624  *
1625  * Security bit configuration for transactions from mpu_m0 to emac0. When cleared
1626  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1627  * Secure transactions are allowed.
1628  *
1629  * Field Access Macros:
1630  *
1631  */
1632 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0 register field. */
1633 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_LSB 0
1634 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0 register field. */
1635 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_MSB 0
1636 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0 register field. */
1637 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_WIDTH 1
1638 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0 register field value. */
1639 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_SET_MSK 0x00000001
1640 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0 register field value. */
1641 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_CLR_MSK 0xfffffffe
1642 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0 register field. */
1643 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_RESET 0x0
1644 /* Extracts the ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0 field value from a register. */
1645 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1646 /* Produces a ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0 register field value suitable for setting the register. */
1647 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1648 
1649 /*
1650  * Field : dma
1651  *
1652  * Security bit configuration for transactions from dma to emac0. When cleared (0),
1653  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
1654  * transactions are allowed.
1655  *
1656  * Field Access Macros:
1657  *
1658  */
1659 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA register field. */
1660 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_LSB 8
1661 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA register field. */
1662 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_MSB 8
1663 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA register field. */
1664 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_WIDTH 1
1665 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA register field value. */
1666 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_SET_MSK 0x00000100
1667 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA register field value. */
1668 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_CLR_MSK 0xfffffeff
1669 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA register field. */
1670 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_RESET 0x0
1671 /* Extracts the ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA field value from a register. */
1672 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_GET(value) (((value) & 0x00000100) >> 8)
1673 /* Produces a ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA register field value suitable for setting the register. */
1674 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_SET(value) (((value) << 8) & 0x00000100)
1675 
1676 /*
1677  * Field : fpga2soc
1678  *
1679  * Security bit configuration for transactions from fpga2soc to emac0. When cleared
1680  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1681  * Secure transactions are allowed.
1682  *
1683  * Field Access Macros:
1684  *
1685  */
1686 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H register field. */
1687 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_LSB 16
1688 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H register field. */
1689 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_MSB 16
1690 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H register field. */
1691 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_WIDTH 1
1692 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H register field value. */
1693 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_SET_MSK 0x00010000
1694 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H register field value. */
1695 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_CLR_MSK 0xfffeffff
1696 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H register field. */
1697 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_RESET 0x0
1698 /* Extracts the ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H field value from a register. */
1699 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_GET(value) (((value) & 0x00010000) >> 16)
1700 /* Produces a ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H register field value suitable for setting the register. */
1701 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_SET(value) (((value) << 16) & 0x00010000)
1702 
1703 /*
1704  * Field : ahb_ap
1705  *
1706  * Security bit configuration for transactions from ahb_ap to emac0. When cleared
1707  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1708  * Secure transactions are allowed.
1709  *
1710  * Field Access Macros:
1711  *
1712  */
1713 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP register field. */
1714 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_LSB 24
1715 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP register field. */
1716 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_MSB 24
1717 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP register field. */
1718 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_WIDTH 1
1719 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP register field value. */
1720 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_SET_MSK 0x01000000
1721 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP register field value. */
1722 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_CLR_MSK 0xfeffffff
1723 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP register field. */
1724 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_RESET 0x0
1725 /* Extracts the ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP field value from a register. */
1726 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1727 /* Produces a ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP register field value suitable for setting the register. */
1728 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1729 
1730 #ifndef __ASSEMBLY__
1731 /*
1732  * WARNING: The C register and register group struct declarations are provided for
1733  * convenience and illustrative purposes. They should, however, be used with
1734  * caution as the C language standard provides no guarantees about the alignment or
1735  * atomicity of device memory accesses. The recommended practice for writing
1736  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1737  * alt_write_word() functions.
1738  *
1739  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_EMAC0.
1740  */
1741 struct ALT_NOC_FW_L4_PER_SCR_EMAC0_s
1742 {
1743  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0 */
1744  uint32_t : 7; /* *UNDEFINED* */
1745  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA */
1746  uint32_t : 7; /* *UNDEFINED* */
1747  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H */
1748  uint32_t : 7; /* *UNDEFINED* */
1749  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP */
1750  uint32_t : 7; /* *UNDEFINED* */
1751 };
1752 
1753 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_EMAC0. */
1754 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_EMAC0_s ALT_NOC_FW_L4_PER_SCR_EMAC0_t;
1755 #endif /* __ASSEMBLY__ */
1756 
1757 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC0 register. */
1758 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_RESET 0x00000000
1759 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_EMAC0 register from the beginning of the component. */
1760 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_OFST 0x2c
1761 
1762 /*
1763  * Register : emac1
1764  *
1765  * Per-Master Security bit for emac1
1766  *
1767  * Register Layout
1768  *
1769  * Bits | Access | Reset | Description
1770  * :--------|:-------|:--------|:-----------------------------------
1771  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0
1772  * [7:1] | ??? | Unknown | *UNDEFINED*
1773  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA
1774  * [15:9] | ??? | Unknown | *UNDEFINED*
1775  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H
1776  * [23:17] | ??? | Unknown | *UNDEFINED*
1777  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP
1778  * [31:25] | ??? | Unknown | *UNDEFINED*
1779  *
1780  */
1781 /*
1782  * Field : mpu_m0
1783  *
1784  * Security bit configuration for transactions from mpu_m0 to emac1. When cleared
1785  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1786  * Secure transactions are allowed.
1787  *
1788  * Field Access Macros:
1789  *
1790  */
1791 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0 register field. */
1792 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_LSB 0
1793 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0 register field. */
1794 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_MSB 0
1795 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0 register field. */
1796 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_WIDTH 1
1797 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0 register field value. */
1798 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_SET_MSK 0x00000001
1799 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0 register field value. */
1800 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_CLR_MSK 0xfffffffe
1801 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0 register field. */
1802 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_RESET 0x0
1803 /* Extracts the ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0 field value from a register. */
1804 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1805 /* Produces a ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0 register field value suitable for setting the register. */
1806 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1807 
1808 /*
1809  * Field : dma
1810  *
1811  * Security bit configuration for transactions from dma to emac1. When cleared (0),
1812  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
1813  * transactions are allowed.
1814  *
1815  * Field Access Macros:
1816  *
1817  */
1818 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA register field. */
1819 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_LSB 8
1820 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA register field. */
1821 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_MSB 8
1822 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA register field. */
1823 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_WIDTH 1
1824 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA register field value. */
1825 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_SET_MSK 0x00000100
1826 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA register field value. */
1827 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_CLR_MSK 0xfffffeff
1828 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA register field. */
1829 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_RESET 0x0
1830 /* Extracts the ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA field value from a register. */
1831 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_GET(value) (((value) & 0x00000100) >> 8)
1832 /* Produces a ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA register field value suitable for setting the register. */
1833 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_SET(value) (((value) << 8) & 0x00000100)
1834 
1835 /*
1836  * Field : fpga2soc
1837  *
1838  * Security bit configuration for transactions from fpga2soc to emac1. When cleared
1839  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1840  * Secure transactions are allowed.
1841  *
1842  * Field Access Macros:
1843  *
1844  */
1845 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H register field. */
1846 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_LSB 16
1847 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H register field. */
1848 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_MSB 16
1849 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H register field. */
1850 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_WIDTH 1
1851 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H register field value. */
1852 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_SET_MSK 0x00010000
1853 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H register field value. */
1854 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_CLR_MSK 0xfffeffff
1855 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H register field. */
1856 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_RESET 0x0
1857 /* Extracts the ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H field value from a register. */
1858 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_GET(value) (((value) & 0x00010000) >> 16)
1859 /* Produces a ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H register field value suitable for setting the register. */
1860 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_SET(value) (((value) << 16) & 0x00010000)
1861 
1862 /*
1863  * Field : ahb_ap
1864  *
1865  * Security bit configuration for transactions from ahb_ap to emac1. When cleared
1866  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1867  * Secure transactions are allowed.
1868  *
1869  * Field Access Macros:
1870  *
1871  */
1872 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP register field. */
1873 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_LSB 24
1874 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP register field. */
1875 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_MSB 24
1876 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP register field. */
1877 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_WIDTH 1
1878 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP register field value. */
1879 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_SET_MSK 0x01000000
1880 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP register field value. */
1881 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_CLR_MSK 0xfeffffff
1882 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP register field. */
1883 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_RESET 0x0
1884 /* Extracts the ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP field value from a register. */
1885 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1886 /* Produces a ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP register field value suitable for setting the register. */
1887 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1888 
1889 #ifndef __ASSEMBLY__
1890 /*
1891  * WARNING: The C register and register group struct declarations are provided for
1892  * convenience and illustrative purposes. They should, however, be used with
1893  * caution as the C language standard provides no guarantees about the alignment or
1894  * atomicity of device memory accesses. The recommended practice for writing
1895  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1896  * alt_write_word() functions.
1897  *
1898  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_EMAC1.
1899  */
1900 struct ALT_NOC_FW_L4_PER_SCR_EMAC1_s
1901 {
1902  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0 */
1903  uint32_t : 7; /* *UNDEFINED* */
1904  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA */
1905  uint32_t : 7; /* *UNDEFINED* */
1906  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H */
1907  uint32_t : 7; /* *UNDEFINED* */
1908  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP */
1909  uint32_t : 7; /* *UNDEFINED* */
1910 };
1911 
1912 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_EMAC1. */
1913 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_EMAC1_s ALT_NOC_FW_L4_PER_SCR_EMAC1_t;
1914 #endif /* __ASSEMBLY__ */
1915 
1916 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC1 register. */
1917 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_RESET 0x00000000
1918 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_EMAC1 register from the beginning of the component. */
1919 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_OFST 0x30
1920 
1921 /*
1922  * Register : emac2
1923  *
1924  * Per-Master Security bit for emac2
1925  *
1926  * Register Layout
1927  *
1928  * Bits | Access | Reset | Description
1929  * :--------|:-------|:--------|:-----------------------------------
1930  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0
1931  * [7:1] | ??? | Unknown | *UNDEFINED*
1932  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA
1933  * [15:9] | ??? | Unknown | *UNDEFINED*
1934  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H
1935  * [23:17] | ??? | Unknown | *UNDEFINED*
1936  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP
1937  * [31:25] | ??? | Unknown | *UNDEFINED*
1938  *
1939  */
1940 /*
1941  * Field : mpu_m0
1942  *
1943  * Security bit configuration for transactions from mpu_m0 to emac2. When cleared
1944  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1945  * Secure transactions are allowed.
1946  *
1947  * Field Access Macros:
1948  *
1949  */
1950 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0 register field. */
1951 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_LSB 0
1952 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0 register field. */
1953 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_MSB 0
1954 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0 register field. */
1955 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_WIDTH 1
1956 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0 register field value. */
1957 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_SET_MSK 0x00000001
1958 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0 register field value. */
1959 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_CLR_MSK 0xfffffffe
1960 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0 register field. */
1961 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_RESET 0x0
1962 /* Extracts the ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0 field value from a register. */
1963 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1964 /* Produces a ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0 register field value suitable for setting the register. */
1965 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1966 
1967 /*
1968  * Field : dma
1969  *
1970  * Security bit configuration for transactions from dma to emac2. When cleared (0),
1971  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
1972  * transactions are allowed.
1973  *
1974  * Field Access Macros:
1975  *
1976  */
1977 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA register field. */
1978 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_LSB 8
1979 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA register field. */
1980 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_MSB 8
1981 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA register field. */
1982 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_WIDTH 1
1983 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA register field value. */
1984 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_SET_MSK 0x00000100
1985 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA register field value. */
1986 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_CLR_MSK 0xfffffeff
1987 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA register field. */
1988 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_RESET 0x0
1989 /* Extracts the ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA field value from a register. */
1990 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_GET(value) (((value) & 0x00000100) >> 8)
1991 /* Produces a ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA register field value suitable for setting the register. */
1992 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_SET(value) (((value) << 8) & 0x00000100)
1993 
1994 /*
1995  * Field : fpga2soc
1996  *
1997  * Security bit configuration for transactions from fpga2soc to emac2. When cleared
1998  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1999  * Secure transactions are allowed.
2000  *
2001  * Field Access Macros:
2002  *
2003  */
2004 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H register field. */
2005 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_LSB 16
2006 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H register field. */
2007 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_MSB 16
2008 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H register field. */
2009 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_WIDTH 1
2010 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H register field value. */
2011 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_SET_MSK 0x00010000
2012 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H register field value. */
2013 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_CLR_MSK 0xfffeffff
2014 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H register field. */
2015 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_RESET 0x0
2016 /* Extracts the ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H field value from a register. */
2017 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_GET(value) (((value) & 0x00010000) >> 16)
2018 /* Produces a ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H register field value suitable for setting the register. */
2019 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_SET(value) (((value) << 16) & 0x00010000)
2020 
2021 /*
2022  * Field : ahb_ap
2023  *
2024  * Security bit configuration for transactions from ahb_ap to emac2. When cleared
2025  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2026  * Secure transactions are allowed.
2027  *
2028  * Field Access Macros:
2029  *
2030  */
2031 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP register field. */
2032 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_LSB 24
2033 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP register field. */
2034 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_MSB 24
2035 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP register field. */
2036 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_WIDTH 1
2037 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP register field value. */
2038 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_SET_MSK 0x01000000
2039 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP register field value. */
2040 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_CLR_MSK 0xfeffffff
2041 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP register field. */
2042 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_RESET 0x0
2043 /* Extracts the ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP field value from a register. */
2044 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2045 /* Produces a ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP register field value suitable for setting the register. */
2046 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2047 
2048 #ifndef __ASSEMBLY__
2049 /*
2050  * WARNING: The C register and register group struct declarations are provided for
2051  * convenience and illustrative purposes. They should, however, be used with
2052  * caution as the C language standard provides no guarantees about the alignment or
2053  * atomicity of device memory accesses. The recommended practice for writing
2054  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2055  * alt_write_word() functions.
2056  *
2057  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_EMAC2.
2058  */
2059 struct ALT_NOC_FW_L4_PER_SCR_EMAC2_s
2060 {
2061  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0 */
2062  uint32_t : 7; /* *UNDEFINED* */
2063  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA */
2064  uint32_t : 7; /* *UNDEFINED* */
2065  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H */
2066  uint32_t : 7; /* *UNDEFINED* */
2067  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP */
2068  uint32_t : 7; /* *UNDEFINED* */
2069 };
2070 
2071 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_EMAC2. */
2072 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_EMAC2_s ALT_NOC_FW_L4_PER_SCR_EMAC2_t;
2073 #endif /* __ASSEMBLY__ */
2074 
2075 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC2 register. */
2076 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_RESET 0x00000000
2077 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_EMAC2 register from the beginning of the component. */
2078 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_OFST 0x34
2079 
2080 /*
2081  * Register : emac3
2082  *
2083  * Per-Master Security bit for emac3
2084  *
2085  * Register Layout
2086  *
2087  * Bits | Access | Reset | Description
2088  * :-------|:-------|:------|:---------------------------------
2089  * [31:0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD
2090  *
2091  */
2092 /*
2093  * Field : Reserved
2094  *
2095  * Field Access Macros:
2096  *
2097  */
2098 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD register field. */
2099 #define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_LSB 0
2100 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD register field. */
2101 #define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_MSB 31
2102 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD register field. */
2103 #define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_WIDTH 32
2104 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD register field value. */
2105 #define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_SET_MSK 0xffffffff
2106 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD register field value. */
2107 #define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_CLR_MSK 0x00000000
2108 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD register field. */
2109 #define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_RESET 0x0
2110 /* Extracts the ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD field value from a register. */
2111 #define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
2112 /* Produces a ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD register field value suitable for setting the register. */
2113 #define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_SET(value) (((value) << 0) & 0xffffffff)
2114 
2115 #ifndef __ASSEMBLY__
2116 /*
2117  * WARNING: The C register and register group struct declarations are provided for
2118  * convenience and illustrative purposes. They should, however, be used with
2119  * caution as the C language standard provides no guarantees about the alignment or
2120  * atomicity of device memory accesses. The recommended practice for writing
2121  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2122  * alt_write_word() functions.
2123  *
2124  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_EMAC3.
2125  */
2126 struct ALT_NOC_FW_L4_PER_SCR_EMAC3_s
2127 {
2128  uint32_t Reserved : 32; /* ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD */
2129 };
2130 
2131 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_EMAC3. */
2132 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_EMAC3_s ALT_NOC_FW_L4_PER_SCR_EMAC3_t;
2133 #endif /* __ASSEMBLY__ */
2134 
2135 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC3 register. */
2136 #define ALT_NOC_FW_L4_PER_SCR_EMAC3_RESET 0x00000000
2137 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_EMAC3 register from the beginning of the component. */
2138 #define ALT_NOC_FW_L4_PER_SCR_EMAC3_OFST 0x38
2139 
2140 /*
2141  * Register : qspi
2142  *
2143  * Per-Master Security bit for qspi
2144  *
2145  * Register Layout
2146  *
2147  * Bits | Access | Reset | Description
2148  * :--------|:-------|:--------|:----------------------------------
2149  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0
2150  * [7:1] | ??? | Unknown | *UNDEFINED*
2151  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_QSPI_DMA
2152  * [15:9] | ??? | Unknown | *UNDEFINED*
2153  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_QSPI_F2H
2154  * [23:17] | ??? | Unknown | *UNDEFINED*
2155  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP
2156  * [31:25] | ??? | Unknown | *UNDEFINED*
2157  *
2158  */
2159 /*
2160  * Field : mpu_m0
2161  *
2162  * Security bit configuration for transactions from mpu_m0 to qspi. When cleared
2163  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2164  * Secure transactions are allowed.
2165  *
2166  * Field Access Macros:
2167  *
2168  */
2169 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0 register field. */
2170 #define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_LSB 0
2171 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0 register field. */
2172 #define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_MSB 0
2173 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0 register field. */
2174 #define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_WIDTH 1
2175 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0 register field value. */
2176 #define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_SET_MSK 0x00000001
2177 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0 register field value. */
2178 #define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_CLR_MSK 0xfffffffe
2179 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0 register field. */
2180 #define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_RESET 0x0
2181 /* Extracts the ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0 field value from a register. */
2182 #define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2183 /* Produces a ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0 register field value suitable for setting the register. */
2184 #define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2185 
2186 /*
2187  * Field : dma
2188  *
2189  * Security bit configuration for transactions from dma to qspi. When cleared (0),
2190  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
2191  * transactions are allowed.
2192  *
2193  * Field Access Macros:
2194  *
2195  */
2196 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_QSPI_DMA register field. */
2197 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_LSB 8
2198 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_QSPI_DMA register field. */
2199 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_MSB 8
2200 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_QSPI_DMA register field. */
2201 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_WIDTH 1
2202 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_QSPI_DMA register field value. */
2203 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_SET_MSK 0x00000100
2204 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_QSPI_DMA register field value. */
2205 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_CLR_MSK 0xfffffeff
2206 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_QSPI_DMA register field. */
2207 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_RESET 0x0
2208 /* Extracts the ALT_NOC_FW_L4_PER_SCR_QSPI_DMA field value from a register. */
2209 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_GET(value) (((value) & 0x00000100) >> 8)
2210 /* Produces a ALT_NOC_FW_L4_PER_SCR_QSPI_DMA register field value suitable for setting the register. */
2211 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_SET(value) (((value) << 8) & 0x00000100)
2212 
2213 /*
2214  * Field : fpga2soc
2215  *
2216  * Security bit configuration for transactions from fpga2soc to qspi. When cleared
2217  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2218  * Secure transactions are allowed.
2219  *
2220  * Field Access Macros:
2221  *
2222  */
2223 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_QSPI_F2H register field. */
2224 #define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_LSB 16
2225 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_QSPI_F2H register field. */
2226 #define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_MSB 16
2227 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_QSPI_F2H register field. */
2228 #define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_WIDTH 1
2229 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_QSPI_F2H register field value. */
2230 #define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_SET_MSK 0x00010000
2231 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_QSPI_F2H register field value. */
2232 #define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_CLR_MSK 0xfffeffff
2233 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_QSPI_F2H register field. */
2234 #define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_RESET 0x0
2235 /* Extracts the ALT_NOC_FW_L4_PER_SCR_QSPI_F2H field value from a register. */
2236 #define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_GET(value) (((value) & 0x00010000) >> 16)
2237 /* Produces a ALT_NOC_FW_L4_PER_SCR_QSPI_F2H register field value suitable for setting the register. */
2238 #define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_SET(value) (((value) << 16) & 0x00010000)
2239 
2240 /*
2241  * Field : ahb_ap
2242  *
2243  * Security bit configuration for transactions from ahb_ap to qspi. When cleared
2244  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2245  * Secure transactions are allowed.
2246  *
2247  * Field Access Macros:
2248  *
2249  */
2250 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP register field. */
2251 #define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_LSB 24
2252 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP register field. */
2253 #define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_MSB 24
2254 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP register field. */
2255 #define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_WIDTH 1
2256 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP register field value. */
2257 #define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_SET_MSK 0x01000000
2258 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP register field value. */
2259 #define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_CLR_MSK 0xfeffffff
2260 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP register field. */
2261 #define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_RESET 0x0
2262 /* Extracts the ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP field value from a register. */
2263 #define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2264 /* Produces a ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP register field value suitable for setting the register. */
2265 #define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2266 
2267 #ifndef __ASSEMBLY__
2268 /*
2269  * WARNING: The C register and register group struct declarations are provided for
2270  * convenience and illustrative purposes. They should, however, be used with
2271  * caution as the C language standard provides no guarantees about the alignment or
2272  * atomicity of device memory accesses. The recommended practice for writing
2273  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2274  * alt_write_word() functions.
2275  *
2276  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_QSPI.
2277  */
2278 struct ALT_NOC_FW_L4_PER_SCR_QSPI_s
2279 {
2280  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0 */
2281  uint32_t : 7; /* *UNDEFINED* */
2282  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_QSPI_DMA */
2283  uint32_t : 7; /* *UNDEFINED* */
2284  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_QSPI_F2H */
2285  uint32_t : 7; /* *UNDEFINED* */
2286  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP */
2287  uint32_t : 7; /* *UNDEFINED* */
2288 };
2289 
2290 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_QSPI. */
2291 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_QSPI_s ALT_NOC_FW_L4_PER_SCR_QSPI_t;
2292 #endif /* __ASSEMBLY__ */
2293 
2294 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_QSPI register. */
2295 #define ALT_NOC_FW_L4_PER_SCR_QSPI_RESET 0x00000000
2296 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_QSPI register from the beginning of the component. */
2297 #define ALT_NOC_FW_L4_PER_SCR_QSPI_OFST 0x3c
2298 
2299 /*
2300  * Register : sdmmc
2301  *
2302  * Per-Master Security bit for sdmmc
2303  *
2304  * Register Layout
2305  *
2306  * Bits | Access | Reset | Description
2307  * :--------|:-------|:--------|:-----------------------------------
2308  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0
2309  * [7:1] | ??? | Unknown | *UNDEFINED*
2310  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA
2311  * [15:9] | ??? | Unknown | *UNDEFINED*
2312  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H
2313  * [23:17] | ??? | Unknown | *UNDEFINED*
2314  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP
2315  * [31:25] | ??? | Unknown | *UNDEFINED*
2316  *
2317  */
2318 /*
2319  * Field : mpu_m0
2320  *
2321  * Security bit configuration for transactions from mpu_m0 to sdmmc. When cleared
2322  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2323  * Secure transactions are allowed.
2324  *
2325  * Field Access Macros:
2326  *
2327  */
2328 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0 register field. */
2329 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_LSB 0
2330 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0 register field. */
2331 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_MSB 0
2332 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0 register field. */
2333 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_WIDTH 1
2334 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0 register field value. */
2335 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_SET_MSK 0x00000001
2336 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0 register field value. */
2337 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_CLR_MSK 0xfffffffe
2338 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0 register field. */
2339 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_RESET 0x0
2340 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0 field value from a register. */
2341 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2342 /* Produces a ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0 register field value suitable for setting the register. */
2343 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2344 
2345 /*
2346  * Field : dma
2347  *
2348  * Security bit configuration for transactions from dma to sdmmc. When cleared (0),
2349  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
2350  * transactions are allowed.
2351  *
2352  * Field Access Macros:
2353  *
2354  */
2355 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA register field. */
2356 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_LSB 8
2357 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA register field. */
2358 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_MSB 8
2359 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA register field. */
2360 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_WIDTH 1
2361 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA register field value. */
2362 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_SET_MSK 0x00000100
2363 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA register field value. */
2364 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_CLR_MSK 0xfffffeff
2365 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA register field. */
2366 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_RESET 0x0
2367 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA field value from a register. */
2368 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_GET(value) (((value) & 0x00000100) >> 8)
2369 /* Produces a ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA register field value suitable for setting the register. */
2370 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_SET(value) (((value) << 8) & 0x00000100)
2371 
2372 /*
2373  * Field : fpga2soc
2374  *
2375  * Security bit configuration for transactions from fpga2soc to sdmmc. When cleared
2376  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2377  * Secure transactions are allowed.
2378  *
2379  * Field Access Macros:
2380  *
2381  */
2382 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H register field. */
2383 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_LSB 16
2384 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H register field. */
2385 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_MSB 16
2386 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H register field. */
2387 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_WIDTH 1
2388 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H register field value. */
2389 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_SET_MSK 0x00010000
2390 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H register field value. */
2391 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_CLR_MSK 0xfffeffff
2392 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H register field. */
2393 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_RESET 0x0
2394 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H field value from a register. */
2395 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_GET(value) (((value) & 0x00010000) >> 16)
2396 /* Produces a ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H register field value suitable for setting the register. */
2397 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_SET(value) (((value) << 16) & 0x00010000)
2398 
2399 /*
2400  * Field : ahb_ap
2401  *
2402  * Security bit configuration for transactions from ahb_ap to sdmmc. When cleared
2403  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2404  * Secure transactions are allowed.
2405  *
2406  * Field Access Macros:
2407  *
2408  */
2409 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP register field. */
2410 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_LSB 24
2411 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP register field. */
2412 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_MSB 24
2413 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP register field. */
2414 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_WIDTH 1
2415 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP register field value. */
2416 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_SET_MSK 0x01000000
2417 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP register field value. */
2418 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_CLR_MSK 0xfeffffff
2419 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP register field. */
2420 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_RESET 0x0
2421 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP field value from a register. */
2422 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2423 /* Produces a ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP register field value suitable for setting the register. */
2424 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2425 
2426 #ifndef __ASSEMBLY__
2427 /*
2428  * WARNING: The C register and register group struct declarations are provided for
2429  * convenience and illustrative purposes. They should, however, be used with
2430  * caution as the C language standard provides no guarantees about the alignment or
2431  * atomicity of device memory accesses. The recommended practice for writing
2432  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2433  * alt_write_word() functions.
2434  *
2435  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_SDMMC.
2436  */
2437 struct ALT_NOC_FW_L4_PER_SCR_SDMMC_s
2438 {
2439  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0 */
2440  uint32_t : 7; /* *UNDEFINED* */
2441  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA */
2442  uint32_t : 7; /* *UNDEFINED* */
2443  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H */
2444  uint32_t : 7; /* *UNDEFINED* */
2445  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP */
2446  uint32_t : 7; /* *UNDEFINED* */
2447 };
2448 
2449 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_SDMMC. */
2450 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_SDMMC_s ALT_NOC_FW_L4_PER_SCR_SDMMC_t;
2451 #endif /* __ASSEMBLY__ */
2452 
2453 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SDMMC register. */
2454 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_RESET 0x00000000
2455 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_SDMMC register from the beginning of the component. */
2456 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_OFST 0x40
2457 
2458 /*
2459  * Register : gpio0
2460  *
2461  * Per-Master Security bit for gpio0
2462  *
2463  * Register Layout
2464  *
2465  * Bits | Access | Reset | Description
2466  * :--------|:-------|:--------|:-----------------------------------
2467  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0
2468  * [7:1] | ??? | Unknown | *UNDEFINED*
2469  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA
2470  * [15:9] | ??? | Unknown | *UNDEFINED*
2471  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H
2472  * [23:17] | ??? | Unknown | *UNDEFINED*
2473  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP
2474  * [31:25] | ??? | Unknown | *UNDEFINED*
2475  *
2476  */
2477 /*
2478  * Field : mpu_m0
2479  *
2480  * Security bit configuration for transactions from mpu_m0 to gpio0. When cleared
2481  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2482  * Secure transactions are allowed.
2483  *
2484  * Field Access Macros:
2485  *
2486  */
2487 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0 register field. */
2488 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_LSB 0
2489 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0 register field. */
2490 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_MSB 0
2491 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0 register field. */
2492 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_WIDTH 1
2493 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0 register field value. */
2494 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_SET_MSK 0x00000001
2495 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0 register field value. */
2496 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_CLR_MSK 0xfffffffe
2497 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0 register field. */
2498 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_RESET 0x0
2499 /* Extracts the ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0 field value from a register. */
2500 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2501 /* Produces a ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0 register field value suitable for setting the register. */
2502 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2503 
2504 /*
2505  * Field : dma
2506  *
2507  * Security bit configuration for transactions from dma to gpio0. When cleared (0),
2508  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
2509  * transactions are allowed.
2510  *
2511  * Field Access Macros:
2512  *
2513  */
2514 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA register field. */
2515 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_LSB 8
2516 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA register field. */
2517 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_MSB 8
2518 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA register field. */
2519 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_WIDTH 1
2520 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA register field value. */
2521 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_SET_MSK 0x00000100
2522 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA register field value. */
2523 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_CLR_MSK 0xfffffeff
2524 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA register field. */
2525 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_RESET 0x0
2526 /* Extracts the ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA field value from a register. */
2527 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_GET(value) (((value) & 0x00000100) >> 8)
2528 /* Produces a ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA register field value suitable for setting the register. */
2529 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_SET(value) (((value) << 8) & 0x00000100)
2530 
2531 /*
2532  * Field : fpga2soc
2533  *
2534  * Security bit configuration for transactions from fpga2soc to gpio0. When cleared
2535  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2536  * Secure transactions are allowed.
2537  *
2538  * Field Access Macros:
2539  *
2540  */
2541 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H register field. */
2542 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_LSB 16
2543 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H register field. */
2544 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_MSB 16
2545 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H register field. */
2546 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_WIDTH 1
2547 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H register field value. */
2548 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_SET_MSK 0x00010000
2549 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H register field value. */
2550 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_CLR_MSK 0xfffeffff
2551 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H register field. */
2552 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_RESET 0x0
2553 /* Extracts the ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H field value from a register. */
2554 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_GET(value) (((value) & 0x00010000) >> 16)
2555 /* Produces a ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H register field value suitable for setting the register. */
2556 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_SET(value) (((value) << 16) & 0x00010000)
2557 
2558 /*
2559  * Field : ahb_ap
2560  *
2561  * Security bit configuration for transactions from ahb_ap to gpio0. When cleared
2562  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2563  * Secure transactions are allowed.
2564  *
2565  * Field Access Macros:
2566  *
2567  */
2568 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP register field. */
2569 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_LSB 24
2570 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP register field. */
2571 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_MSB 24
2572 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP register field. */
2573 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_WIDTH 1
2574 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP register field value. */
2575 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_SET_MSK 0x01000000
2576 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP register field value. */
2577 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_CLR_MSK 0xfeffffff
2578 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP register field. */
2579 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_RESET 0x0
2580 /* Extracts the ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP field value from a register. */
2581 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2582 /* Produces a ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP register field value suitable for setting the register. */
2583 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2584 
2585 #ifndef __ASSEMBLY__
2586 /*
2587  * WARNING: The C register and register group struct declarations are provided for
2588  * convenience and illustrative purposes. They should, however, be used with
2589  * caution as the C language standard provides no guarantees about the alignment or
2590  * atomicity of device memory accesses. The recommended practice for writing
2591  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2592  * alt_write_word() functions.
2593  *
2594  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_GPIO0.
2595  */
2596 struct ALT_NOC_FW_L4_PER_SCR_GPIO0_s
2597 {
2598  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0 */
2599  uint32_t : 7; /* *UNDEFINED* */
2600  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA */
2601  uint32_t : 7; /* *UNDEFINED* */
2602  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H */
2603  uint32_t : 7; /* *UNDEFINED* */
2604  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP */
2605  uint32_t : 7; /* *UNDEFINED* */
2606 };
2607 
2608 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_GPIO0. */
2609 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_GPIO0_s ALT_NOC_FW_L4_PER_SCR_GPIO0_t;
2610 #endif /* __ASSEMBLY__ */
2611 
2612 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO0 register. */
2613 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_RESET 0x00000000
2614 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_GPIO0 register from the beginning of the component. */
2615 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_OFST 0x44
2616 
2617 /*
2618  * Register : gpio1
2619  *
2620  * Per-Master Security bit for gpio1
2621  *
2622  * Register Layout
2623  *
2624  * Bits | Access | Reset | Description
2625  * :--------|:-------|:--------|:-----------------------------------
2626  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0
2627  * [7:1] | ??? | Unknown | *UNDEFINED*
2628  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA
2629  * [15:9] | ??? | Unknown | *UNDEFINED*
2630  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H
2631  * [23:17] | ??? | Unknown | *UNDEFINED*
2632  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP
2633  * [31:25] | ??? | Unknown | *UNDEFINED*
2634  *
2635  */
2636 /*
2637  * Field : mpu_m0
2638  *
2639  * Security bit configuration for transactions from mpu_m0 to gpio1. When cleared
2640  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2641  * Secure transactions are allowed.
2642  *
2643  * Field Access Macros:
2644  *
2645  */
2646 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0 register field. */
2647 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_LSB 0
2648 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0 register field. */
2649 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_MSB 0
2650 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0 register field. */
2651 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_WIDTH 1
2652 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0 register field value. */
2653 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_SET_MSK 0x00000001
2654 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0 register field value. */
2655 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_CLR_MSK 0xfffffffe
2656 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0 register field. */
2657 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_RESET 0x0
2658 /* Extracts the ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0 field value from a register. */
2659 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2660 /* Produces a ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0 register field value suitable for setting the register. */
2661 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2662 
2663 /*
2664  * Field : dma
2665  *
2666  * Security bit configuration for transactions from dma to gpio1. When cleared (0),
2667  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
2668  * transactions are allowed.
2669  *
2670  * Field Access Macros:
2671  *
2672  */
2673 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA register field. */
2674 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_LSB 8
2675 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA register field. */
2676 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_MSB 8
2677 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA register field. */
2678 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_WIDTH 1
2679 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA register field value. */
2680 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_SET_MSK 0x00000100
2681 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA register field value. */
2682 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_CLR_MSK 0xfffffeff
2683 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA register field. */
2684 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_RESET 0x0
2685 /* Extracts the ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA field value from a register. */
2686 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_GET(value) (((value) & 0x00000100) >> 8)
2687 /* Produces a ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA register field value suitable for setting the register. */
2688 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_SET(value) (((value) << 8) & 0x00000100)
2689 
2690 /*
2691  * Field : fpga2soc
2692  *
2693  * Security bit configuration for transactions from fpga2soc to gpio1. When cleared
2694  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2695  * Secure transactions are allowed.
2696  *
2697  * Field Access Macros:
2698  *
2699  */
2700 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H register field. */
2701 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_LSB 16
2702 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H register field. */
2703 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_MSB 16
2704 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H register field. */
2705 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_WIDTH 1
2706 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H register field value. */
2707 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_SET_MSK 0x00010000
2708 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H register field value. */
2709 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_CLR_MSK 0xfffeffff
2710 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H register field. */
2711 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_RESET 0x0
2712 /* Extracts the ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H field value from a register. */
2713 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_GET(value) (((value) & 0x00010000) >> 16)
2714 /* Produces a ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H register field value suitable for setting the register. */
2715 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_SET(value) (((value) << 16) & 0x00010000)
2716 
2717 /*
2718  * Field : ahb_ap
2719  *
2720  * Security bit configuration for transactions from ahb_ap to gpio1. When cleared
2721  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2722  * Secure transactions are allowed.
2723  *
2724  * Field Access Macros:
2725  *
2726  */
2727 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP register field. */
2728 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_LSB 24
2729 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP register field. */
2730 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_MSB 24
2731 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP register field. */
2732 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_WIDTH 1
2733 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP register field value. */
2734 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_SET_MSK 0x01000000
2735 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP register field value. */
2736 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_CLR_MSK 0xfeffffff
2737 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP register field. */
2738 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_RESET 0x0
2739 /* Extracts the ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP field value from a register. */
2740 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2741 /* Produces a ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP register field value suitable for setting the register. */
2742 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2743 
2744 #ifndef __ASSEMBLY__
2745 /*
2746  * WARNING: The C register and register group struct declarations are provided for
2747  * convenience and illustrative purposes. They should, however, be used with
2748  * caution as the C language standard provides no guarantees about the alignment or
2749  * atomicity of device memory accesses. The recommended practice for writing
2750  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2751  * alt_write_word() functions.
2752  *
2753  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_GPIO1.
2754  */
2755 struct ALT_NOC_FW_L4_PER_SCR_GPIO1_s
2756 {
2757  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0 */
2758  uint32_t : 7; /* *UNDEFINED* */
2759  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA */
2760  uint32_t : 7; /* *UNDEFINED* */
2761  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H */
2762  uint32_t : 7; /* *UNDEFINED* */
2763  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP */
2764  uint32_t : 7; /* *UNDEFINED* */
2765 };
2766 
2767 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_GPIO1. */
2768 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_GPIO1_s ALT_NOC_FW_L4_PER_SCR_GPIO1_t;
2769 #endif /* __ASSEMBLY__ */
2770 
2771 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO1 register. */
2772 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_RESET 0x00000000
2773 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_GPIO1 register from the beginning of the component. */
2774 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_OFST 0x48
2775 
2776 /*
2777  * Register : gpio2
2778  *
2779  * Per-Master Security bit for gpio2
2780  *
2781  * Register Layout
2782  *
2783  * Bits | Access | Reset | Description
2784  * :--------|:-------|:--------|:-----------------------------------
2785  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0
2786  * [7:1] | ??? | Unknown | *UNDEFINED*
2787  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA
2788  * [15:9] | ??? | Unknown | *UNDEFINED*
2789  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H
2790  * [23:17] | ??? | Unknown | *UNDEFINED*
2791  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP
2792  * [31:25] | ??? | Unknown | *UNDEFINED*
2793  *
2794  */
2795 /*
2796  * Field : mpu_m0
2797  *
2798  * Security bit configuration for transactions from mpu_m0 to gpio2. When cleared
2799  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2800  * Secure transactions are allowed.
2801  *
2802  * Field Access Macros:
2803  *
2804  */
2805 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0 register field. */
2806 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_LSB 0
2807 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0 register field. */
2808 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_MSB 0
2809 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0 register field. */
2810 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_WIDTH 1
2811 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0 register field value. */
2812 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_SET_MSK 0x00000001
2813 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0 register field value. */
2814 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_CLR_MSK 0xfffffffe
2815 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0 register field. */
2816 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_RESET 0x0
2817 /* Extracts the ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0 field value from a register. */
2818 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2819 /* Produces a ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0 register field value suitable for setting the register. */
2820 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2821 
2822 /*
2823  * Field : dma
2824  *
2825  * Security bit configuration for transactions from dma to gpio2. When cleared (0),
2826  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
2827  * transactions are allowed.
2828  *
2829  * Field Access Macros:
2830  *
2831  */
2832 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA register field. */
2833 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_LSB 8
2834 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA register field. */
2835 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_MSB 8
2836 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA register field. */
2837 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_WIDTH 1
2838 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA register field value. */
2839 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_SET_MSK 0x00000100
2840 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA register field value. */
2841 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_CLR_MSK 0xfffffeff
2842 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA register field. */
2843 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_RESET 0x0
2844 /* Extracts the ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA field value from a register. */
2845 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_GET(value) (((value) & 0x00000100) >> 8)
2846 /* Produces a ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA register field value suitable for setting the register. */
2847 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_SET(value) (((value) << 8) & 0x00000100)
2848 
2849 /*
2850  * Field : fpga2soc
2851  *
2852  * Security bit configuration for transactions from fpga2soc to gpio2. When cleared
2853  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2854  * Secure transactions are allowed.
2855  *
2856  * Field Access Macros:
2857  *
2858  */
2859 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H register field. */
2860 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_LSB 16
2861 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H register field. */
2862 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_MSB 16
2863 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H register field. */
2864 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_WIDTH 1
2865 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H register field value. */
2866 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_SET_MSK 0x00010000
2867 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H register field value. */
2868 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_CLR_MSK 0xfffeffff
2869 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H register field. */
2870 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_RESET 0x0
2871 /* Extracts the ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H field value from a register. */
2872 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_GET(value) (((value) & 0x00010000) >> 16)
2873 /* Produces a ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H register field value suitable for setting the register. */
2874 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_SET(value) (((value) << 16) & 0x00010000)
2875 
2876 /*
2877  * Field : ahb_ap
2878  *
2879  * Security bit configuration for transactions from ahb_ap to gpio2. When cleared
2880  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2881  * Secure transactions are allowed.
2882  *
2883  * Field Access Macros:
2884  *
2885  */
2886 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP register field. */
2887 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_LSB 24
2888 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP register field. */
2889 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_MSB 24
2890 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP register field. */
2891 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_WIDTH 1
2892 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP register field value. */
2893 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_SET_MSK 0x01000000
2894 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP register field value. */
2895 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_CLR_MSK 0xfeffffff
2896 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP register field. */
2897 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_RESET 0x0
2898 /* Extracts the ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP field value from a register. */
2899 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2900 /* Produces a ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP register field value suitable for setting the register. */
2901 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2902 
2903 #ifndef __ASSEMBLY__
2904 /*
2905  * WARNING: The C register and register group struct declarations are provided for
2906  * convenience and illustrative purposes. They should, however, be used with
2907  * caution as the C language standard provides no guarantees about the alignment or
2908  * atomicity of device memory accesses. The recommended practice for writing
2909  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2910  * alt_write_word() functions.
2911  *
2912  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_GPIO2.
2913  */
2914 struct ALT_NOC_FW_L4_PER_SCR_GPIO2_s
2915 {
2916  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0 */
2917  uint32_t : 7; /* *UNDEFINED* */
2918  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA */
2919  uint32_t : 7; /* *UNDEFINED* */
2920  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H */
2921  uint32_t : 7; /* *UNDEFINED* */
2922  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP */
2923  uint32_t : 7; /* *UNDEFINED* */
2924 };
2925 
2926 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_GPIO2. */
2927 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_GPIO2_s ALT_NOC_FW_L4_PER_SCR_GPIO2_t;
2928 #endif /* __ASSEMBLY__ */
2929 
2930 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO2 register. */
2931 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_RESET 0x00000000
2932 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_GPIO2 register from the beginning of the component. */
2933 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_OFST 0x4c
2934 
2935 /*
2936  * Register : i2c0
2937  *
2938  * Per-Master Security bit for i2c0
2939  *
2940  * Register Layout
2941  *
2942  * Bits | Access | Reset | Description
2943  * :--------|:-------|:--------|:----------------------------------
2944  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0
2945  * [7:1] | ??? | Unknown | *UNDEFINED*
2946  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C0_DMA
2947  * [15:9] | ??? | Unknown | *UNDEFINED*
2948  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C0_F2H
2949  * [23:17] | ??? | Unknown | *UNDEFINED*
2950  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP
2951  * [31:25] | ??? | Unknown | *UNDEFINED*
2952  *
2953  */
2954 /*
2955  * Field : mpu_m0
2956  *
2957  * Security bit configuration for transactions from mpu_m0 to i2c0. When cleared
2958  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2959  * Secure transactions are allowed.
2960  *
2961  * Field Access Macros:
2962  *
2963  */
2964 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0 register field. */
2965 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_LSB 0
2966 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0 register field. */
2967 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_MSB 0
2968 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0 register field. */
2969 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_WIDTH 1
2970 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0 register field value. */
2971 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_SET_MSK 0x00000001
2972 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0 register field value. */
2973 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_CLR_MSK 0xfffffffe
2974 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0 register field. */
2975 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_RESET 0x0
2976 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0 field value from a register. */
2977 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2978 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0 register field value suitable for setting the register. */
2979 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2980 
2981 /*
2982  * Field : dma
2983  *
2984  * Security bit configuration for transactions from dma to i2c0. When cleared (0),
2985  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
2986  * transactions are allowed.
2987  *
2988  * Field Access Macros:
2989  *
2990  */
2991 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C0_DMA register field. */
2992 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_LSB 8
2993 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C0_DMA register field. */
2994 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_MSB 8
2995 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C0_DMA register field. */
2996 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_WIDTH 1
2997 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C0_DMA register field value. */
2998 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_SET_MSK 0x00000100
2999 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C0_DMA register field value. */
3000 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_CLR_MSK 0xfffffeff
3001 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C0_DMA register field. */
3002 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_RESET 0x0
3003 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C0_DMA field value from a register. */
3004 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_GET(value) (((value) & 0x00000100) >> 8)
3005 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C0_DMA register field value suitable for setting the register. */
3006 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_SET(value) (((value) << 8) & 0x00000100)
3007 
3008 /*
3009  * Field : fpga2soc
3010  *
3011  * Security bit configuration for transactions from fpga2soc to i2c0. When cleared
3012  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3013  * Secure transactions are allowed.
3014  *
3015  * Field Access Macros:
3016  *
3017  */
3018 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C0_F2H register field. */
3019 #define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_LSB 16
3020 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C0_F2H register field. */
3021 #define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_MSB 16
3022 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C0_F2H register field. */
3023 #define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_WIDTH 1
3024 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C0_F2H register field value. */
3025 #define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_SET_MSK 0x00010000
3026 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C0_F2H register field value. */
3027 #define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_CLR_MSK 0xfffeffff
3028 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C0_F2H register field. */
3029 #define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_RESET 0x0
3030 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C0_F2H field value from a register. */
3031 #define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_GET(value) (((value) & 0x00010000) >> 16)
3032 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C0_F2H register field value suitable for setting the register. */
3033 #define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_SET(value) (((value) << 16) & 0x00010000)
3034 
3035 /*
3036  * Field : ahb_ap
3037  *
3038  * Security bit configuration for transactions from ahb_ap to i2c0. When cleared
3039  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3040  * Secure transactions are allowed.
3041  *
3042  * Field Access Macros:
3043  *
3044  */
3045 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP register field. */
3046 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_LSB 24
3047 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP register field. */
3048 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_MSB 24
3049 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP register field. */
3050 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_WIDTH 1
3051 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP register field value. */
3052 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_SET_MSK 0x01000000
3053 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP register field value. */
3054 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_CLR_MSK 0xfeffffff
3055 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP register field. */
3056 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_RESET 0x0
3057 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP field value from a register. */
3058 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3059 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP register field value suitable for setting the register. */
3060 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3061 
3062 #ifndef __ASSEMBLY__
3063 /*
3064  * WARNING: The C register and register group struct declarations are provided for
3065  * convenience and illustrative purposes. They should, however, be used with
3066  * caution as the C language standard provides no guarantees about the alignment or
3067  * atomicity of device memory accesses. The recommended practice for writing
3068  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3069  * alt_write_word() functions.
3070  *
3071  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_I2C0.
3072  */
3073 struct ALT_NOC_FW_L4_PER_SCR_I2C0_s
3074 {
3075  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0 */
3076  uint32_t : 7; /* *UNDEFINED* */
3077  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C0_DMA */
3078  uint32_t : 7; /* *UNDEFINED* */
3079  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C0_F2H */
3080  uint32_t : 7; /* *UNDEFINED* */
3081  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP */
3082  uint32_t : 7; /* *UNDEFINED* */
3083 };
3084 
3085 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_I2C0. */
3086 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_I2C0_s ALT_NOC_FW_L4_PER_SCR_I2C0_t;
3087 #endif /* __ASSEMBLY__ */
3088 
3089 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C0 register. */
3090 #define ALT_NOC_FW_L4_PER_SCR_I2C0_RESET 0x00000000
3091 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_I2C0 register from the beginning of the component. */
3092 #define ALT_NOC_FW_L4_PER_SCR_I2C0_OFST 0x50
3093 
3094 /*
3095  * Register : i2c1
3096  *
3097  * Per-Master Security bit for i2c1
3098  *
3099  * Register Layout
3100  *
3101  * Bits | Access | Reset | Description
3102  * :--------|:-------|:--------|:----------------------------------
3103  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0
3104  * [7:1] | ??? | Unknown | *UNDEFINED*
3105  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C1_DMA
3106  * [15:9] | ??? | Unknown | *UNDEFINED*
3107  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C1_F2H
3108  * [23:17] | ??? | Unknown | *UNDEFINED*
3109  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP
3110  * [31:25] | ??? | Unknown | *UNDEFINED*
3111  *
3112  */
3113 /*
3114  * Field : mpu_m0
3115  *
3116  * Security bit configuration for transactions from mpu_m0 to i2c1. When cleared
3117  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3118  * Secure transactions are allowed.
3119  *
3120  * Field Access Macros:
3121  *
3122  */
3123 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0 register field. */
3124 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_LSB 0
3125 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0 register field. */
3126 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_MSB 0
3127 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0 register field. */
3128 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_WIDTH 1
3129 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0 register field value. */
3130 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_SET_MSK 0x00000001
3131 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0 register field value. */
3132 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_CLR_MSK 0xfffffffe
3133 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0 register field. */
3134 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_RESET 0x0
3135 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0 field value from a register. */
3136 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3137 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0 register field value suitable for setting the register. */
3138 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3139 
3140 /*
3141  * Field : dma
3142  *
3143  * Security bit configuration for transactions from dma to i2c1. When cleared (0),
3144  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
3145  * transactions are allowed.
3146  *
3147  * Field Access Macros:
3148  *
3149  */
3150 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C1_DMA register field. */
3151 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_LSB 8
3152 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C1_DMA register field. */
3153 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_MSB 8
3154 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C1_DMA register field. */
3155 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_WIDTH 1
3156 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C1_DMA register field value. */
3157 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_SET_MSK 0x00000100
3158 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C1_DMA register field value. */
3159 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_CLR_MSK 0xfffffeff
3160 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C1_DMA register field. */
3161 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_RESET 0x0
3162 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C1_DMA field value from a register. */
3163 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_GET(value) (((value) & 0x00000100) >> 8)
3164 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C1_DMA register field value suitable for setting the register. */
3165 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_SET(value) (((value) << 8) & 0x00000100)
3166 
3167 /*
3168  * Field : fpga2soc
3169  *
3170  * Security bit configuration for transactions from fpga2soc to i2c1. When cleared
3171  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3172  * Secure transactions are allowed.
3173  *
3174  * Field Access Macros:
3175  *
3176  */
3177 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C1_F2H register field. */
3178 #define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_LSB 16
3179 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C1_F2H register field. */
3180 #define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_MSB 16
3181 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C1_F2H register field. */
3182 #define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_WIDTH 1
3183 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C1_F2H register field value. */
3184 #define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_SET_MSK 0x00010000
3185 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C1_F2H register field value. */
3186 #define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_CLR_MSK 0xfffeffff
3187 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C1_F2H register field. */
3188 #define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_RESET 0x0
3189 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C1_F2H field value from a register. */
3190 #define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_GET(value) (((value) & 0x00010000) >> 16)
3191 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C1_F2H register field value suitable for setting the register. */
3192 #define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_SET(value) (((value) << 16) & 0x00010000)
3193 
3194 /*
3195  * Field : ahb_ap
3196  *
3197  * Security bit configuration for transactions from ahb_ap to i2c1. When cleared
3198  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3199  * Secure transactions are allowed.
3200  *
3201  * Field Access Macros:
3202  *
3203  */
3204 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP register field. */
3205 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_LSB 24
3206 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP register field. */
3207 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_MSB 24
3208 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP register field. */
3209 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_WIDTH 1
3210 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP register field value. */
3211 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_SET_MSK 0x01000000
3212 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP register field value. */
3213 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_CLR_MSK 0xfeffffff
3214 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP register field. */
3215 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_RESET 0x0
3216 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP field value from a register. */
3217 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3218 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP register field value suitable for setting the register. */
3219 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3220 
3221 #ifndef __ASSEMBLY__
3222 /*
3223  * WARNING: The C register and register group struct declarations are provided for
3224  * convenience and illustrative purposes. They should, however, be used with
3225  * caution as the C language standard provides no guarantees about the alignment or
3226  * atomicity of device memory accesses. The recommended practice for writing
3227  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3228  * alt_write_word() functions.
3229  *
3230  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_I2C1.
3231  */
3232 struct ALT_NOC_FW_L4_PER_SCR_I2C1_s
3233 {
3234  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0 */
3235  uint32_t : 7; /* *UNDEFINED* */
3236  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C1_DMA */
3237  uint32_t : 7; /* *UNDEFINED* */
3238  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C1_F2H */
3239  uint32_t : 7; /* *UNDEFINED* */
3240  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP */
3241  uint32_t : 7; /* *UNDEFINED* */
3242 };
3243 
3244 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_I2C1. */
3245 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_I2C1_s ALT_NOC_FW_L4_PER_SCR_I2C1_t;
3246 #endif /* __ASSEMBLY__ */
3247 
3248 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C1 register. */
3249 #define ALT_NOC_FW_L4_PER_SCR_I2C1_RESET 0x00000000
3250 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_I2C1 register from the beginning of the component. */
3251 #define ALT_NOC_FW_L4_PER_SCR_I2C1_OFST 0x54
3252 
3253 /*
3254  * Register : i2c2
3255  *
3256  * Per-Master Security bit for i2c2
3257  *
3258  * Register Layout
3259  *
3260  * Bits | Access | Reset | Description
3261  * :--------|:-------|:--------|:----------------------------------
3262  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0
3263  * [7:1] | ??? | Unknown | *UNDEFINED*
3264  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C2_DMA
3265  * [15:9] | ??? | Unknown | *UNDEFINED*
3266  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C2_F2H
3267  * [23:17] | ??? | Unknown | *UNDEFINED*
3268  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP
3269  * [31:25] | ??? | Unknown | *UNDEFINED*
3270  *
3271  */
3272 /*
3273  * Field : mpu_m0
3274  *
3275  * Security bit configuration for transactions from mpu_m0 to i2c2. When cleared
3276  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3277  * Secure transactions are allowed.
3278  *
3279  * Field Access Macros:
3280  *
3281  */
3282 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0 register field. */
3283 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_LSB 0
3284 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0 register field. */
3285 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_MSB 0
3286 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0 register field. */
3287 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_WIDTH 1
3288 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0 register field value. */
3289 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_SET_MSK 0x00000001
3290 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0 register field value. */
3291 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_CLR_MSK 0xfffffffe
3292 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0 register field. */
3293 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_RESET 0x0
3294 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0 field value from a register. */
3295 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3296 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0 register field value suitable for setting the register. */
3297 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3298 
3299 /*
3300  * Field : dma
3301  *
3302  * Security bit configuration for transactions from dma to i2c2. When cleared (0),
3303  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
3304  * transactions are allowed.
3305  *
3306  * Field Access Macros:
3307  *
3308  */
3309 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C2_DMA register field. */
3310 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_LSB 8
3311 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C2_DMA register field. */
3312 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_MSB 8
3313 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C2_DMA register field. */
3314 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_WIDTH 1
3315 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C2_DMA register field value. */
3316 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_SET_MSK 0x00000100
3317 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C2_DMA register field value. */
3318 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_CLR_MSK 0xfffffeff
3319 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C2_DMA register field. */
3320 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_RESET 0x0
3321 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C2_DMA field value from a register. */
3322 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_GET(value) (((value) & 0x00000100) >> 8)
3323 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C2_DMA register field value suitable for setting the register. */
3324 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_SET(value) (((value) << 8) & 0x00000100)
3325 
3326 /*
3327  * Field : fpga2soc
3328  *
3329  * Security bit configuration for transactions from fpga2soc to i2c2. When cleared
3330  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3331  * Secure transactions are allowed.
3332  *
3333  * Field Access Macros:
3334  *
3335  */
3336 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C2_F2H register field. */
3337 #define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_LSB 16
3338 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C2_F2H register field. */
3339 #define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_MSB 16
3340 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C2_F2H register field. */
3341 #define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_WIDTH 1
3342 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C2_F2H register field value. */
3343 #define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_SET_MSK 0x00010000
3344 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C2_F2H register field value. */
3345 #define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_CLR_MSK 0xfffeffff
3346 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C2_F2H register field. */
3347 #define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_RESET 0x0
3348 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C2_F2H field value from a register. */
3349 #define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_GET(value) (((value) & 0x00010000) >> 16)
3350 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C2_F2H register field value suitable for setting the register. */
3351 #define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_SET(value) (((value) << 16) & 0x00010000)
3352 
3353 /*
3354  * Field : ahb_ap
3355  *
3356  * Security bit configuration for transactions from ahb_ap to i2c2. When cleared
3357  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3358  * Secure transactions are allowed.
3359  *
3360  * Field Access Macros:
3361  *
3362  */
3363 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP register field. */
3364 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_LSB 24
3365 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP register field. */
3366 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_MSB 24
3367 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP register field. */
3368 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_WIDTH 1
3369 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP register field value. */
3370 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_SET_MSK 0x01000000
3371 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP register field value. */
3372 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_CLR_MSK 0xfeffffff
3373 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP register field. */
3374 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_RESET 0x0
3375 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP field value from a register. */
3376 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3377 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP register field value suitable for setting the register. */
3378 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3379 
3380 #ifndef __ASSEMBLY__
3381 /*
3382  * WARNING: The C register and register group struct declarations are provided for
3383  * convenience and illustrative purposes. They should, however, be used with
3384  * caution as the C language standard provides no guarantees about the alignment or
3385  * atomicity of device memory accesses. The recommended practice for writing
3386  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3387  * alt_write_word() functions.
3388  *
3389  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_I2C2.
3390  */
3391 struct ALT_NOC_FW_L4_PER_SCR_I2C2_s
3392 {
3393  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0 */
3394  uint32_t : 7; /* *UNDEFINED* */
3395  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C2_DMA */
3396  uint32_t : 7; /* *UNDEFINED* */
3397  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C2_F2H */
3398  uint32_t : 7; /* *UNDEFINED* */
3399  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP */
3400  uint32_t : 7; /* *UNDEFINED* */
3401 };
3402 
3403 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_I2C2. */
3404 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_I2C2_s ALT_NOC_FW_L4_PER_SCR_I2C2_t;
3405 #endif /* __ASSEMBLY__ */
3406 
3407 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C2 register. */
3408 #define ALT_NOC_FW_L4_PER_SCR_I2C2_RESET 0x00000000
3409 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_I2C2 register from the beginning of the component. */
3410 #define ALT_NOC_FW_L4_PER_SCR_I2C2_OFST 0x58
3411 
3412 /*
3413  * Register : i2c3
3414  *
3415  * Per-Master Security bit for i2c3
3416  *
3417  * Register Layout
3418  *
3419  * Bits | Access | Reset | Description
3420  * :--------|:-------|:--------|:----------------------------------
3421  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0
3422  * [7:1] | ??? | Unknown | *UNDEFINED*
3423  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C3_DMA
3424  * [15:9] | ??? | Unknown | *UNDEFINED*
3425  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C3_F2H
3426  * [23:17] | ??? | Unknown | *UNDEFINED*
3427  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP
3428  * [31:25] | ??? | Unknown | *UNDEFINED*
3429  *
3430  */
3431 /*
3432  * Field : mpu_m0
3433  *
3434  * Security bit configuration for transactions from mpu_m0 to i2c3. When cleared
3435  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3436  * Secure transactions are allowed.
3437  *
3438  * Field Access Macros:
3439  *
3440  */
3441 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0 register field. */
3442 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_LSB 0
3443 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0 register field. */
3444 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_MSB 0
3445 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0 register field. */
3446 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_WIDTH 1
3447 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0 register field value. */
3448 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_SET_MSK 0x00000001
3449 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0 register field value. */
3450 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_CLR_MSK 0xfffffffe
3451 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0 register field. */
3452 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_RESET 0x0
3453 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0 field value from a register. */
3454 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3455 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0 register field value suitable for setting the register. */
3456 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3457 
3458 /*
3459  * Field : dma
3460  *
3461  * Security bit configuration for transactions from dma to i2c3. When cleared (0),
3462  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
3463  * transactions are allowed.
3464  *
3465  * Field Access Macros:
3466  *
3467  */
3468 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C3_DMA register field. */
3469 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_LSB 8
3470 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C3_DMA register field. */
3471 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_MSB 8
3472 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C3_DMA register field. */
3473 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_WIDTH 1
3474 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C3_DMA register field value. */
3475 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_SET_MSK 0x00000100
3476 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C3_DMA register field value. */
3477 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_CLR_MSK 0xfffffeff
3478 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C3_DMA register field. */
3479 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_RESET 0x0
3480 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C3_DMA field value from a register. */
3481 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_GET(value) (((value) & 0x00000100) >> 8)
3482 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C3_DMA register field value suitable for setting the register. */
3483 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_SET(value) (((value) << 8) & 0x00000100)
3484 
3485 /*
3486  * Field : fpga2soc
3487  *
3488  * Security bit configuration for transactions from fpga2soc to i2c3. When cleared
3489  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3490  * Secure transactions are allowed.
3491  *
3492  * Field Access Macros:
3493  *
3494  */
3495 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C3_F2H register field. */
3496 #define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_LSB 16
3497 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C3_F2H register field. */
3498 #define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_MSB 16
3499 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C3_F2H register field. */
3500 #define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_WIDTH 1
3501 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C3_F2H register field value. */
3502 #define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_SET_MSK 0x00010000
3503 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C3_F2H register field value. */
3504 #define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_CLR_MSK 0xfffeffff
3505 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C3_F2H register field. */
3506 #define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_RESET 0x0
3507 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C3_F2H field value from a register. */
3508 #define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_GET(value) (((value) & 0x00010000) >> 16)
3509 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C3_F2H register field value suitable for setting the register. */
3510 #define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_SET(value) (((value) << 16) & 0x00010000)
3511 
3512 /*
3513  * Field : ahb_ap
3514  *
3515  * Security bit configuration for transactions from ahb_ap to i2c3. When cleared
3516  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3517  * Secure transactions are allowed.
3518  *
3519  * Field Access Macros:
3520  *
3521  */
3522 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP register field. */
3523 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_LSB 24
3524 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP register field. */
3525 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_MSB 24
3526 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP register field. */
3527 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_WIDTH 1
3528 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP register field value. */
3529 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_SET_MSK 0x01000000
3530 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP register field value. */
3531 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_CLR_MSK 0xfeffffff
3532 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP register field. */
3533 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_RESET 0x0
3534 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP field value from a register. */
3535 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3536 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP register field value suitable for setting the register. */
3537 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3538 
3539 #ifndef __ASSEMBLY__
3540 /*
3541  * WARNING: The C register and register group struct declarations are provided for
3542  * convenience and illustrative purposes. They should, however, be used with
3543  * caution as the C language standard provides no guarantees about the alignment or
3544  * atomicity of device memory accesses. The recommended practice for writing
3545  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3546  * alt_write_word() functions.
3547  *
3548  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_I2C3.
3549  */
3550 struct ALT_NOC_FW_L4_PER_SCR_I2C3_s
3551 {
3552  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0 */
3553  uint32_t : 7; /* *UNDEFINED* */
3554  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C3_DMA */
3555  uint32_t : 7; /* *UNDEFINED* */
3556  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C3_F2H */
3557  uint32_t : 7; /* *UNDEFINED* */
3558  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP */
3559  uint32_t : 7; /* *UNDEFINED* */
3560 };
3561 
3562 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_I2C3. */
3563 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_I2C3_s ALT_NOC_FW_L4_PER_SCR_I2C3_t;
3564 #endif /* __ASSEMBLY__ */
3565 
3566 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C3 register. */
3567 #define ALT_NOC_FW_L4_PER_SCR_I2C3_RESET 0x00000000
3568 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_I2C3 register from the beginning of the component. */
3569 #define ALT_NOC_FW_L4_PER_SCR_I2C3_OFST 0x5c
3570 
3571 /*
3572  * Register : i2c4
3573  *
3574  * Per-Master Security bit for i2c4
3575  *
3576  * Register Layout
3577  *
3578  * Bits | Access | Reset | Description
3579  * :--------|:-------|:--------|:----------------------------------
3580  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0
3581  * [7:1] | ??? | Unknown | *UNDEFINED*
3582  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C4_DMA
3583  * [15:9] | ??? | Unknown | *UNDEFINED*
3584  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C4_F2H
3585  * [23:17] | ??? | Unknown | *UNDEFINED*
3586  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP
3587  * [31:25] | ??? | Unknown | *UNDEFINED*
3588  *
3589  */
3590 /*
3591  * Field : mpu_m0
3592  *
3593  * Security bit configuration for transactions from mpu_m0 to i2c4. When cleared
3594  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3595  * Secure transactions are allowed.
3596  *
3597  * Field Access Macros:
3598  *
3599  */
3600 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0 register field. */
3601 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_LSB 0
3602 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0 register field. */
3603 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_MSB 0
3604 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0 register field. */
3605 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_WIDTH 1
3606 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0 register field value. */
3607 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_SET_MSK 0x00000001
3608 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0 register field value. */
3609 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_CLR_MSK 0xfffffffe
3610 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0 register field. */
3611 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_RESET 0x0
3612 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0 field value from a register. */
3613 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3614 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0 register field value suitable for setting the register. */
3615 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3616 
3617 /*
3618  * Field : dma
3619  *
3620  * Security bit configuration for transactions from dma to i2c4. When cleared (0),
3621  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
3622  * transactions are allowed.
3623  *
3624  * Field Access Macros:
3625  *
3626  */
3627 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C4_DMA register field. */
3628 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_LSB 8
3629 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C4_DMA register field. */
3630 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_MSB 8
3631 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C4_DMA register field. */
3632 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_WIDTH 1
3633 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C4_DMA register field value. */
3634 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_SET_MSK 0x00000100
3635 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C4_DMA register field value. */
3636 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_CLR_MSK 0xfffffeff
3637 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C4_DMA register field. */
3638 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_RESET 0x0
3639 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C4_DMA field value from a register. */
3640 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_GET(value) (((value) & 0x00000100) >> 8)
3641 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C4_DMA register field value suitable for setting the register. */
3642 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_SET(value) (((value) << 8) & 0x00000100)
3643 
3644 /*
3645  * Field : fpga2soc
3646  *
3647  * Security bit configuration for transactions from fpga2soc to i2c4. When cleared
3648  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3649  * Secure transactions are allowed.
3650  *
3651  * Field Access Macros:
3652  *
3653  */
3654 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C4_F2H register field. */
3655 #define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_LSB 16
3656 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C4_F2H register field. */
3657 #define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_MSB 16
3658 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C4_F2H register field. */
3659 #define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_WIDTH 1
3660 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C4_F2H register field value. */
3661 #define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_SET_MSK 0x00010000
3662 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C4_F2H register field value. */
3663 #define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_CLR_MSK 0xfffeffff
3664 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C4_F2H register field. */
3665 #define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_RESET 0x0
3666 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C4_F2H field value from a register. */
3667 #define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_GET(value) (((value) & 0x00010000) >> 16)
3668 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C4_F2H register field value suitable for setting the register. */
3669 #define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_SET(value) (((value) << 16) & 0x00010000)
3670 
3671 /*
3672  * Field : ahb_ap
3673  *
3674  * Security bit configuration for transactions from ahb_ap to. When cleared (0),
3675  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
3676  * transactions are allowed.
3677  *
3678  * Field Access Macros:
3679  *
3680  */
3681 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP register field. */
3682 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_LSB 24
3683 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP register field. */
3684 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_MSB 24
3685 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP register field. */
3686 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_WIDTH 1
3687 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP register field value. */
3688 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_SET_MSK 0x01000000
3689 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP register field value. */
3690 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_CLR_MSK 0xfeffffff
3691 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP register field. */
3692 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_RESET 0x0
3693 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP field value from a register. */
3694 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3695 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP register field value suitable for setting the register. */
3696 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3697 
3698 #ifndef __ASSEMBLY__
3699 /*
3700  * WARNING: The C register and register group struct declarations are provided for
3701  * convenience and illustrative purposes. They should, however, be used with
3702  * caution as the C language standard provides no guarantees about the alignment or
3703  * atomicity of device memory accesses. The recommended practice for writing
3704  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3705  * alt_write_word() functions.
3706  *
3707  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_I2C4.
3708  */
3709 struct ALT_NOC_FW_L4_PER_SCR_I2C4_s
3710 {
3711  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0 */
3712  uint32_t : 7; /* *UNDEFINED* */
3713  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C4_DMA */
3714  uint32_t : 7; /* *UNDEFINED* */
3715  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C4_F2H */
3716  uint32_t : 7; /* *UNDEFINED* */
3717  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP */
3718  uint32_t : 7; /* *UNDEFINED* */
3719 };
3720 
3721 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_I2C4. */
3722 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_I2C4_s ALT_NOC_FW_L4_PER_SCR_I2C4_t;
3723 #endif /* __ASSEMBLY__ */
3724 
3725 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C4 register. */
3726 #define ALT_NOC_FW_L4_PER_SCR_I2C4_RESET 0x00000000
3727 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_I2C4 register from the beginning of the component. */
3728 #define ALT_NOC_FW_L4_PER_SCR_I2C4_OFST 0x60
3729 
3730 /*
3731  * Register : sp_timer0
3732  *
3733  * Per-Master Security bit for sp_timer0
3734  *
3735  * Register Layout
3736  *
3737  * Bits | Access | Reset | Description
3738  * :--------|:-------|:--------|:-------------------------------------
3739  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0
3740  * [7:1] | ??? | Unknown | *UNDEFINED*
3741  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA
3742  * [15:9] | ??? | Unknown | *UNDEFINED*
3743  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H
3744  * [23:17] | ??? | Unknown | *UNDEFINED*
3745  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP
3746  * [31:25] | ??? | Unknown | *UNDEFINED*
3747  *
3748  */
3749 /*
3750  * Field : mpu_m0
3751  *
3752  * Security bit configuration for transactions from mpu_m0 to sp_timer0. When
3753  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3754  * Non-Secure transactions are allowed.
3755  *
3756  * Field Access Macros:
3757  *
3758  */
3759 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0 register field. */
3760 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_LSB 0
3761 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0 register field. */
3762 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_MSB 0
3763 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0 register field. */
3764 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_WIDTH 1
3765 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0 register field value. */
3766 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_SET_MSK 0x00000001
3767 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0 register field value. */
3768 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_CLR_MSK 0xfffffffe
3769 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0 register field. */
3770 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_RESET 0x0
3771 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0 field value from a register. */
3772 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3773 /* Produces a ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0 register field value suitable for setting the register. */
3774 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3775 
3776 /*
3777  * Field : dma
3778  *
3779  * Security bit configuration for transactions from dma to sp_timer0. When cleared
3780  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3781  * Secure transactions are allowed.
3782  *
3783  * Field Access Macros:
3784  *
3785  */
3786 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA register field. */
3787 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_LSB 8
3788 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA register field. */
3789 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_MSB 8
3790 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA register field. */
3791 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_WIDTH 1
3792 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA register field value. */
3793 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_SET_MSK 0x00000100
3794 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA register field value. */
3795 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_CLR_MSK 0xfffffeff
3796 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA register field. */
3797 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_RESET 0x0
3798 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA field value from a register. */
3799 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_GET(value) (((value) & 0x00000100) >> 8)
3800 /* Produces a ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA register field value suitable for setting the register. */
3801 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_SET(value) (((value) << 8) & 0x00000100)
3802 
3803 /*
3804  * Field : fpga2soc
3805  *
3806  * Security bit configuration for transactions from fpga2soc to sp_timer0. When
3807  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3808  * Non-Secure transactions are allowed.
3809  *
3810  * Field Access Macros:
3811  *
3812  */
3813 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H register field. */
3814 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_LSB 16
3815 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H register field. */
3816 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_MSB 16
3817 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H register field. */
3818 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_WIDTH 1
3819 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H register field value. */
3820 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_SET_MSK 0x00010000
3821 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H register field value. */
3822 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_CLR_MSK 0xfffeffff
3823 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H register field. */
3824 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_RESET 0x0
3825 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H field value from a register. */
3826 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_GET(value) (((value) & 0x00010000) >> 16)
3827 /* Produces a ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H register field value suitable for setting the register. */
3828 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_SET(value) (((value) << 16) & 0x00010000)
3829 
3830 /*
3831  * Field : ahb_ap
3832  *
3833  * Security bit configuration for transactions from ahb_ap to sp_timer0. When
3834  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3835  * Non-Secure transactions are allowed.
3836  *
3837  * Field Access Macros:
3838  *
3839  */
3840 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP register field. */
3841 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_LSB 24
3842 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP register field. */
3843 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_MSB 24
3844 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP register field. */
3845 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_WIDTH 1
3846 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP register field value. */
3847 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_SET_MSK 0x01000000
3848 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP register field value. */
3849 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_CLR_MSK 0xfeffffff
3850 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP register field. */
3851 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_RESET 0x0
3852 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP field value from a register. */
3853 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3854 /* Produces a ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP register field value suitable for setting the register. */
3855 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3856 
3857 #ifndef __ASSEMBLY__
3858 /*
3859  * WARNING: The C register and register group struct declarations are provided for
3860  * convenience and illustrative purposes. They should, however, be used with
3861  * caution as the C language standard provides no guarantees about the alignment or
3862  * atomicity of device memory accesses. The recommended practice for writing
3863  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3864  * alt_write_word() functions.
3865  *
3866  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_SP_TMR0.
3867  */
3868 struct ALT_NOC_FW_L4_PER_SCR_SP_TMR0_s
3869 {
3870  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0 */
3871  uint32_t : 7; /* *UNDEFINED* */
3872  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA */
3873  uint32_t : 7; /* *UNDEFINED* */
3874  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H */
3875  uint32_t : 7; /* *UNDEFINED* */
3876  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP */
3877  uint32_t : 7; /* *UNDEFINED* */
3878 };
3879 
3880 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_SP_TMR0. */
3881 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_SP_TMR0_s ALT_NOC_FW_L4_PER_SCR_SP_TMR0_t;
3882 #endif /* __ASSEMBLY__ */
3883 
3884 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SP_TMR0 register. */
3885 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_RESET 0x00000000
3886 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_SP_TMR0 register from the beginning of the component. */
3887 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_OFST 0x64
3888 
3889 /*
3890  * Register : sp_timer1
3891  *
3892  * Per-Master Security bit for sp_timer1
3893  *
3894  * Register Layout
3895  *
3896  * Bits | Access | Reset | Description
3897  * :--------|:-------|:--------|:-------------------------------------
3898  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0
3899  * [7:1] | ??? | Unknown | *UNDEFINED*
3900  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA
3901  * [15:9] | ??? | Unknown | *UNDEFINED*
3902  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H
3903  * [23:17] | ??? | Unknown | *UNDEFINED*
3904  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP
3905  * [31:25] | ??? | Unknown | *UNDEFINED*
3906  *
3907  */
3908 /*
3909  * Field : mpu_m0
3910  *
3911  * Security bit configuration for transactions from mpu_m0 to sp_timer1. When
3912  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3913  * Non-Secure transactions are allowed.
3914  *
3915  * Field Access Macros:
3916  *
3917  */
3918 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0 register field. */
3919 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_LSB 0
3920 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0 register field. */
3921 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_MSB 0
3922 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0 register field. */
3923 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_WIDTH 1
3924 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0 register field value. */
3925 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_SET_MSK 0x00000001
3926 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0 register field value. */
3927 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_CLR_MSK 0xfffffffe
3928 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0 register field. */
3929 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_RESET 0x0
3930 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0 field value from a register. */
3931 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3932 /* Produces a ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0 register field value suitable for setting the register. */
3933 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3934 
3935 /*
3936  * Field : dma
3937  *
3938  * Security bit configuration for transactions from dma to sp_timer1. When cleared
3939  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3940  * Secure transactions are allowed.
3941  *
3942  * Field Access Macros:
3943  *
3944  */
3945 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA register field. */
3946 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_LSB 8
3947 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA register field. */
3948 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_MSB 8
3949 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA register field. */
3950 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_WIDTH 1
3951 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA register field value. */
3952 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_SET_MSK 0x00000100
3953 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA register field value. */
3954 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_CLR_MSK 0xfffffeff
3955 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA register field. */
3956 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_RESET 0x0
3957 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA field value from a register. */
3958 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_GET(value) (((value) & 0x00000100) >> 8)
3959 /* Produces a ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA register field value suitable for setting the register. */
3960 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_SET(value) (((value) << 8) & 0x00000100)
3961 
3962 /*
3963  * Field : fpga2soc
3964  *
3965  * Security bit configuration for transactions from fpga2soc to sp_timer1. When
3966  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3967  * Non-Secure transactions are allowed.
3968  *
3969  * Field Access Macros:
3970  *
3971  */
3972 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H register field. */
3973 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_LSB 16
3974 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H register field. */
3975 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_MSB 16
3976 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H register field. */
3977 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_WIDTH 1
3978 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H register field value. */
3979 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_SET_MSK 0x00010000
3980 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H register field value. */
3981 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_CLR_MSK 0xfffeffff
3982 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H register field. */
3983 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_RESET 0x0
3984 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H field value from a register. */
3985 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_GET(value) (((value) & 0x00010000) >> 16)
3986 /* Produces a ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H register field value suitable for setting the register. */
3987 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_SET(value) (((value) << 16) & 0x00010000)
3988 
3989 /*
3990  * Field : ahb_ap
3991  *
3992  * Security bit configuration for transactions from ahb_ap to sp_timer1. When
3993  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3994  * Non-Secure transactions are allowed.
3995  *
3996  * Field Access Macros:
3997  *
3998  */
3999 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP register field. */
4000 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_LSB 24
4001 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP register field. */
4002 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_MSB 24
4003 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP register field. */
4004 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_WIDTH 1
4005 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP register field value. */
4006 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_SET_MSK 0x01000000
4007 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP register field value. */
4008 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_CLR_MSK 0xfeffffff
4009 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP register field. */
4010 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_RESET 0x0
4011 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP field value from a register. */
4012 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4013 /* Produces a ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP register field value suitable for setting the register. */
4014 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4015 
4016 #ifndef __ASSEMBLY__
4017 /*
4018  * WARNING: The C register and register group struct declarations are provided for
4019  * convenience and illustrative purposes. They should, however, be used with
4020  * caution as the C language standard provides no guarantees about the alignment or
4021  * atomicity of device memory accesses. The recommended practice for writing
4022  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4023  * alt_write_word() functions.
4024  *
4025  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_SP_TMR1.
4026  */
4027 struct ALT_NOC_FW_L4_PER_SCR_SP_TMR1_s
4028 {
4029  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0 */
4030  uint32_t : 7; /* *UNDEFINED* */
4031  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA */
4032  uint32_t : 7; /* *UNDEFINED* */
4033  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H */
4034  uint32_t : 7; /* *UNDEFINED* */
4035  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP */
4036  uint32_t : 7; /* *UNDEFINED* */
4037 };
4038 
4039 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_SP_TMR1. */
4040 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_SP_TMR1_s ALT_NOC_FW_L4_PER_SCR_SP_TMR1_t;
4041 #endif /* __ASSEMBLY__ */
4042 
4043 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SP_TMR1 register. */
4044 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_RESET 0x00000000
4045 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_SP_TMR1 register from the beginning of the component. */
4046 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_OFST 0x68
4047 
4048 /*
4049  * Register : uart0
4050  *
4051  * Per-Master Security bit for uart0
4052  *
4053  * Register Layout
4054  *
4055  * Bits | Access | Reset | Description
4056  * :--------|:-------|:--------|:-----------------------------------
4057  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0
4058  * [7:1] | ??? | Unknown | *UNDEFINED*
4059  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_UART0_DMA
4060  * [15:9] | ??? | Unknown | *UNDEFINED*
4061  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_UART0_F2H
4062  * [23:17] | ??? | Unknown | *UNDEFINED*
4063  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP
4064  * [31:25] | ??? | Unknown | *UNDEFINED*
4065  *
4066  */
4067 /*
4068  * Field : mpu_m0
4069  *
4070  * Security bit configuration for transactions from mpu_m0 to uart0. When cleared
4071  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
4072  * Secure transactions are allowed.
4073  *
4074  * Field Access Macros:
4075  *
4076  */
4077 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0 register field. */
4078 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_LSB 0
4079 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0 register field. */
4080 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_MSB 0
4081 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0 register field. */
4082 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_WIDTH 1
4083 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0 register field value. */
4084 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_SET_MSK 0x00000001
4085 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0 register field value. */
4086 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_CLR_MSK 0xfffffffe
4087 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0 register field. */
4088 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_RESET 0x0
4089 /* Extracts the ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0 field value from a register. */
4090 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4091 /* Produces a ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0 register field value suitable for setting the register. */
4092 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4093 
4094 /*
4095  * Field : dma
4096  *
4097  * Security bit configuration for transactions from dma to uart0. When cleared (0),
4098  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
4099  * transactions are allowed.
4100  *
4101  * Field Access Macros:
4102  *
4103  */
4104 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_UART0_DMA register field. */
4105 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_LSB 8
4106 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_UART0_DMA register field. */
4107 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_MSB 8
4108 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_UART0_DMA register field. */
4109 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_WIDTH 1
4110 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_UART0_DMA register field value. */
4111 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_SET_MSK 0x00000100
4112 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_UART0_DMA register field value. */
4113 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_CLR_MSK 0xfffffeff
4114 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_UART0_DMA register field. */
4115 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_RESET 0x0
4116 /* Extracts the ALT_NOC_FW_L4_PER_SCR_UART0_DMA field value from a register. */
4117 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_GET(value) (((value) & 0x00000100) >> 8)
4118 /* Produces a ALT_NOC_FW_L4_PER_SCR_UART0_DMA register field value suitable for setting the register. */
4119 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_SET(value) (((value) << 8) & 0x00000100)
4120 
4121 /*
4122  * Field : fpga2soc
4123  *
4124  * Security bit configuration for transactions from fpga2soc to uart0. When cleared
4125  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
4126  * Secure transactions are allowed.
4127  *
4128  * Field Access Macros:
4129  *
4130  */
4131 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_UART0_F2H register field. */
4132 #define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_LSB 16
4133 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_UART0_F2H register field. */
4134 #define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_MSB 16
4135 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_UART0_F2H register field. */
4136 #define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_WIDTH 1
4137 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_UART0_F2H register field value. */
4138 #define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_SET_MSK 0x00010000
4139 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_UART0_F2H register field value. */
4140 #define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_CLR_MSK 0xfffeffff
4141 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_UART0_F2H register field. */
4142 #define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_RESET 0x0
4143 /* Extracts the ALT_NOC_FW_L4_PER_SCR_UART0_F2H field value from a register. */
4144 #define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_GET(value) (((value) & 0x00010000) >> 16)
4145 /* Produces a ALT_NOC_FW_L4_PER_SCR_UART0_F2H register field value suitable for setting the register. */
4146 #define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_SET(value) (((value) << 16) & 0x00010000)
4147 
4148 /*
4149  * Field : ahb_ap
4150  *
4151  * Security bit configuration for transactions from ahb_ap to uart0. When cleared
4152  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
4153  * Secure transactions are allowed.
4154  *
4155  * Field Access Macros:
4156  *
4157  */
4158 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP register field. */
4159 #define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_LSB 24
4160 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP register field. */
4161 #define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_MSB 24
4162 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP register field. */
4163 #define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_WIDTH 1
4164 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP register field value. */
4165 #define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_SET_MSK 0x01000000
4166 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP register field value. */
4167 #define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_CLR_MSK 0xfeffffff
4168 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP register field. */
4169 #define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_RESET 0x0
4170 /* Extracts the ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP field value from a register. */
4171 #define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4172 /* Produces a ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP register field value suitable for setting the register. */
4173 #define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4174 
4175 #ifndef __ASSEMBLY__
4176 /*
4177  * WARNING: The C register and register group struct declarations are provided for
4178  * convenience and illustrative purposes. They should, however, be used with
4179  * caution as the C language standard provides no guarantees about the alignment or
4180  * atomicity of device memory accesses. The recommended practice for writing
4181  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4182  * alt_write_word() functions.
4183  *
4184  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_UART0.
4185  */
4186 struct ALT_NOC_FW_L4_PER_SCR_UART0_s
4187 {
4188  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0 */
4189  uint32_t : 7; /* *UNDEFINED* */
4190  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_UART0_DMA */
4191  uint32_t : 7; /* *UNDEFINED* */
4192  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_UART0_F2H */
4193  uint32_t : 7; /* *UNDEFINED* */
4194  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP */
4195  uint32_t : 7; /* *UNDEFINED* */
4196 };
4197 
4198 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_UART0. */
4199 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_UART0_s ALT_NOC_FW_L4_PER_SCR_UART0_t;
4200 #endif /* __ASSEMBLY__ */
4201 
4202 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_UART0 register. */
4203 #define ALT_NOC_FW_L4_PER_SCR_UART0_RESET 0x00000000
4204 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_UART0 register from the beginning of the component. */
4205 #define ALT_NOC_FW_L4_PER_SCR_UART0_OFST 0x6c
4206 
4207 /*
4208  * Register : uart1
4209  *
4210  * Per-Master Security bit for uart1
4211  *
4212  * Register Layout
4213  *
4214  * Bits | Access | Reset | Description
4215  * :--------|:-------|:--------|:-----------------------------------
4216  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0
4217  * [7:1] | ??? | Unknown | *UNDEFINED*
4218  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_UART1_DMA
4219  * [15:9] | ??? | Unknown | *UNDEFINED*
4220  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_UART1_F2H
4221  * [23:17] | ??? | Unknown | *UNDEFINED*
4222  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP
4223  * [31:25] | ??? | Unknown | *UNDEFINED*
4224  *
4225  */
4226 /*
4227  * Field : mpu_m0
4228  *
4229  * Security bit configuration for transactions from mpu_m0 to uart1. When cleared
4230  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
4231  * Secure transactions are allowed.
4232  *
4233  * Field Access Macros:
4234  *
4235  */
4236 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0 register field. */
4237 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_LSB 0
4238 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0 register field. */
4239 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_MSB 0
4240 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0 register field. */
4241 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_WIDTH 1
4242 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0 register field value. */
4243 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_SET_MSK 0x00000001
4244 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0 register field value. */
4245 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_CLR_MSK 0xfffffffe
4246 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0 register field. */
4247 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_RESET 0x0
4248 /* Extracts the ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0 field value from a register. */
4249 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4250 /* Produces a ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0 register field value suitable for setting the register. */
4251 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4252 
4253 /*
4254  * Field : dma
4255  *
4256  * Security bit configuration for transactions from dma to uart1. When cleared (0),
4257  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
4258  * transactions are allowed.
4259  *
4260  * Field Access Macros:
4261  *
4262  */
4263 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_UART1_DMA register field. */
4264 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_LSB 8
4265 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_UART1_DMA register field. */
4266 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_MSB 8
4267 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_UART1_DMA register field. */
4268 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_WIDTH 1
4269 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_UART1_DMA register field value. */
4270 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_SET_MSK 0x00000100
4271 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_UART1_DMA register field value. */
4272 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_CLR_MSK 0xfffffeff
4273 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_UART1_DMA register field. */
4274 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_RESET 0x0
4275 /* Extracts the ALT_NOC_FW_L4_PER_SCR_UART1_DMA field value from a register. */
4276 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_GET(value) (((value) & 0x00000100) >> 8)
4277 /* Produces a ALT_NOC_FW_L4_PER_SCR_UART1_DMA register field value suitable for setting the register. */
4278 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_SET(value) (((value) << 8) & 0x00000100)
4279 
4280 /*
4281  * Field : fpga2soc
4282  *
4283  * Security bit configuration for transactions from fpga2soc to uart1. When cleared
4284  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
4285  * Secure transactions are allowed.
4286  *
4287  * Field Access Macros:
4288  *
4289  */
4290 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_UART1_F2H register field. */
4291 #define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_LSB 16
4292 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_UART1_F2H register field. */
4293 #define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_MSB 16
4294 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_UART1_F2H register field. */
4295 #define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_WIDTH 1
4296 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_UART1_F2H register field value. */
4297 #define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_SET_MSK 0x00010000
4298 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_UART1_F2H register field value. */
4299 #define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_CLR_MSK 0xfffeffff
4300 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_UART1_F2H register field. */
4301 #define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_RESET 0x0
4302 /* Extracts the ALT_NOC_FW_L4_PER_SCR_UART1_F2H field value from a register. */
4303 #define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_GET(value) (((value) & 0x00010000) >> 16)
4304 /* Produces a ALT_NOC_FW_L4_PER_SCR_UART1_F2H register field value suitable for setting the register. */
4305 #define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_SET(value) (((value) << 16) & 0x00010000)
4306 
4307 /*
4308  * Field : ahb_ap
4309  *
4310  * Security bit configuration for transactions from ahb_ap to uart1. When cleared
4311  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
4312  * Secure transactions are allowed.
4313  *
4314  * Field Access Macros:
4315  *
4316  */
4317 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP register field. */
4318 #define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_LSB 24
4319 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP register field. */
4320 #define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_MSB 24
4321 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP register field. */
4322 #define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_WIDTH 1
4323 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP register field value. */
4324 #define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_SET_MSK 0x01000000
4325 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP register field value. */
4326 #define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_CLR_MSK 0xfeffffff
4327 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP register field. */
4328 #define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_RESET 0x0
4329 /* Extracts the ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP field value from a register. */
4330 #define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4331 /* Produces a ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP register field value suitable for setting the register. */
4332 #define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4333 
4334 #ifndef __ASSEMBLY__
4335 /*
4336  * WARNING: The C register and register group struct declarations are provided for
4337  * convenience and illustrative purposes. They should, however, be used with
4338  * caution as the C language standard provides no guarantees about the alignment or
4339  * atomicity of device memory accesses. The recommended practice for writing
4340  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4341  * alt_write_word() functions.
4342  *
4343  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_UART1.
4344  */
4345 struct ALT_NOC_FW_L4_PER_SCR_UART1_s
4346 {
4347  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0 */
4348  uint32_t : 7; /* *UNDEFINED* */
4349  uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_UART1_DMA */
4350  uint32_t : 7; /* *UNDEFINED* */
4351  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_UART1_F2H */
4352  uint32_t : 7; /* *UNDEFINED* */
4353  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP */
4354  uint32_t : 7; /* *UNDEFINED* */
4355 };
4356 
4357 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_UART1. */
4358 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_UART1_s ALT_NOC_FW_L4_PER_SCR_UART1_t;
4359 #endif /* __ASSEMBLY__ */
4360 
4361 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_UART1 register. */
4362 #define ALT_NOC_FW_L4_PER_SCR_UART1_RESET 0x00000000
4363 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_UART1 register from the beginning of the component. */
4364 #define ALT_NOC_FW_L4_PER_SCR_UART1_OFST 0x70
4365 
4366 #ifndef __ASSEMBLY__
4367 /*
4368  * WARNING: The C register and register group struct declarations are provided for
4369  * convenience and illustrative purposes. They should, however, be used with
4370  * caution as the C language standard provides no guarantees about the alignment or
4371  * atomicity of device memory accesses. The recommended practice for writing
4372  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4373  * alt_write_word() functions.
4374  *
4375  * The struct declaration for register group ALT_NOC_FW_L4_PER_SCR.
4376  */
4377 struct ALT_NOC_FW_L4_PER_SCR_s
4378 {
4379  ALT_NOC_FW_L4_PER_SCR_NAND_REG_t nand_register; /* ALT_NOC_FW_L4_PER_SCR_NAND_REG */
4380  ALT_NOC_FW_L4_PER_SCR_NAND_DATA_t nand_data; /* ALT_NOC_FW_L4_PER_SCR_NAND_DATA */
4381  ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_t qspi_data; /* ALT_NOC_FW_L4_PER_SCR_QSPI_DATA */
4382  ALT_NOC_FW_L4_PER_SCR_USB0_REG_t usb0_register; /* ALT_NOC_FW_L4_PER_SCR_USB0_REG */
4383  ALT_NOC_FW_L4_PER_SCR_USB1_REG_t usb1_register; /* ALT_NOC_FW_L4_PER_SCR_USB1_REG */
4384  ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_t dma_nonsecure; /* ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE */
4385  ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_t dma_secure; /* ALT_NOC_FW_L4_PER_SCR_DMA_SECURE */
4386  ALT_NOC_FW_L4_PER_SCR_SPI_MST0_t spi_master0; /* ALT_NOC_FW_L4_PER_SCR_SPI_MST0 */
4387  ALT_NOC_FW_L4_PER_SCR_SPI_MST1_t spi_master1; /* ALT_NOC_FW_L4_PER_SCR_SPI_MST1 */
4388  ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_t spi_slave0; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLV0 */
4389  ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_t spi_slave1; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLV1 */
4390  ALT_NOC_FW_L4_PER_SCR_EMAC0_t emac0; /* ALT_NOC_FW_L4_PER_SCR_EMAC0 */
4391  ALT_NOC_FW_L4_PER_SCR_EMAC1_t emac1; /* ALT_NOC_FW_L4_PER_SCR_EMAC1 */
4392  ALT_NOC_FW_L4_PER_SCR_EMAC2_t emac2; /* ALT_NOC_FW_L4_PER_SCR_EMAC2 */
4393  ALT_NOC_FW_L4_PER_SCR_EMAC3_t emac3; /* ALT_NOC_FW_L4_PER_SCR_EMAC3 */
4394  ALT_NOC_FW_L4_PER_SCR_QSPI_t qspi; /* ALT_NOC_FW_L4_PER_SCR_QSPI */
4395  ALT_NOC_FW_L4_PER_SCR_SDMMC_t sdmmc; /* ALT_NOC_FW_L4_PER_SCR_SDMMC */
4396  ALT_NOC_FW_L4_PER_SCR_GPIO0_t gpio0; /* ALT_NOC_FW_L4_PER_SCR_GPIO0 */
4397  ALT_NOC_FW_L4_PER_SCR_GPIO1_t gpio1; /* ALT_NOC_FW_L4_PER_SCR_GPIO1 */
4398  ALT_NOC_FW_L4_PER_SCR_GPIO2_t gpio2; /* ALT_NOC_FW_L4_PER_SCR_GPIO2 */
4399  ALT_NOC_FW_L4_PER_SCR_I2C0_t i2c0; /* ALT_NOC_FW_L4_PER_SCR_I2C0 */
4400  ALT_NOC_FW_L4_PER_SCR_I2C1_t i2c1; /* ALT_NOC_FW_L4_PER_SCR_I2C1 */
4401  ALT_NOC_FW_L4_PER_SCR_I2C2_t i2c2; /* ALT_NOC_FW_L4_PER_SCR_I2C2 */
4402  ALT_NOC_FW_L4_PER_SCR_I2C3_t i2c3; /* ALT_NOC_FW_L4_PER_SCR_I2C3 */
4403  ALT_NOC_FW_L4_PER_SCR_I2C4_t i2c4; /* ALT_NOC_FW_L4_PER_SCR_I2C4 */
4404  ALT_NOC_FW_L4_PER_SCR_SP_TMR0_t sp_timer0; /* ALT_NOC_FW_L4_PER_SCR_SP_TMR0 */
4405  ALT_NOC_FW_L4_PER_SCR_SP_TMR1_t sp_timer1; /* ALT_NOC_FW_L4_PER_SCR_SP_TMR1 */
4406  ALT_NOC_FW_L4_PER_SCR_UART0_t uart0; /* ALT_NOC_FW_L4_PER_SCR_UART0 */
4407  ALT_NOC_FW_L4_PER_SCR_UART1_t uart1; /* ALT_NOC_FW_L4_PER_SCR_UART1 */
4408  volatile uint32_t _pad_0x74_0x100[35]; /* *UNDEFINED* */
4409 };
4410 
4411 /* The typedef declaration for register group ALT_NOC_FW_L4_PER_SCR. */
4412 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_s ALT_NOC_FW_L4_PER_SCR_t;
4413 /* The struct declaration for the raw register contents of register group ALT_NOC_FW_L4_PER_SCR. */
4414 struct ALT_NOC_FW_L4_PER_SCR_raw_s
4415 {
4416  volatile uint32_t nand_register; /* ALT_NOC_FW_L4_PER_SCR_NAND_REG */
4417  volatile uint32_t nand_data; /* ALT_NOC_FW_L4_PER_SCR_NAND_DATA */
4418  volatile uint32_t qspi_data; /* ALT_NOC_FW_L4_PER_SCR_QSPI_DATA */
4419  volatile uint32_t usb0_register; /* ALT_NOC_FW_L4_PER_SCR_USB0_REG */
4420  volatile uint32_t usb1_register; /* ALT_NOC_FW_L4_PER_SCR_USB1_REG */
4421  volatile uint32_t dma_nonsecure; /* ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE */
4422  volatile uint32_t dma_secure; /* ALT_NOC_FW_L4_PER_SCR_DMA_SECURE */
4423  volatile uint32_t spi_master0; /* ALT_NOC_FW_L4_PER_SCR_SPI_MST0 */
4424  volatile uint32_t spi_master1; /* ALT_NOC_FW_L4_PER_SCR_SPI_MST1 */
4425  volatile uint32_t spi_slave0; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLV0 */
4426  volatile uint32_t spi_slave1; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLV1 */
4427  volatile uint32_t emac0; /* ALT_NOC_FW_L4_PER_SCR_EMAC0 */
4428  volatile uint32_t emac1; /* ALT_NOC_FW_L4_PER_SCR_EMAC1 */
4429  volatile uint32_t emac2; /* ALT_NOC_FW_L4_PER_SCR_EMAC2 */
4430  volatile uint32_t emac3; /* ALT_NOC_FW_L4_PER_SCR_EMAC3 */
4431  volatile uint32_t qspi; /* ALT_NOC_FW_L4_PER_SCR_QSPI */
4432  volatile uint32_t sdmmc; /* ALT_NOC_FW_L4_PER_SCR_SDMMC */
4433  volatile uint32_t gpio0; /* ALT_NOC_FW_L4_PER_SCR_GPIO0 */
4434  volatile uint32_t gpio1; /* ALT_NOC_FW_L4_PER_SCR_GPIO1 */
4435  volatile uint32_t gpio2; /* ALT_NOC_FW_L4_PER_SCR_GPIO2 */
4436  volatile uint32_t i2c0; /* ALT_NOC_FW_L4_PER_SCR_I2C0 */
4437  volatile uint32_t i2c1; /* ALT_NOC_FW_L4_PER_SCR_I2C1 */
4438  volatile uint32_t i2c2; /* ALT_NOC_FW_L4_PER_SCR_I2C2 */
4439  volatile uint32_t i2c3; /* ALT_NOC_FW_L4_PER_SCR_I2C3 */
4440  volatile uint32_t i2c4; /* ALT_NOC_FW_L4_PER_SCR_I2C4 */
4441  volatile uint32_t sp_timer0; /* ALT_NOC_FW_L4_PER_SCR_SP_TMR0 */
4442  volatile uint32_t sp_timer1; /* ALT_NOC_FW_L4_PER_SCR_SP_TMR1 */
4443  volatile uint32_t uart0; /* ALT_NOC_FW_L4_PER_SCR_UART0 */
4444  volatile uint32_t uart1; /* ALT_NOC_FW_L4_PER_SCR_UART1 */
4445  uint32_t _pad_0x74_0x100[35]; /* *UNDEFINED* */
4446 };
4447 
4448 /* The typedef declaration for the raw register contents of register group ALT_NOC_FW_L4_PER_SCR. */
4449 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_raw_s ALT_NOC_FW_L4_PER_SCR_raw_t;
4450 #endif /* __ASSEMBLY__ */
4451 
4452 
4453 #ifdef __cplusplus
4454 }
4455 #endif /* __cplusplus */
4456 #endif /* __ALT_SOCAL_NOC_FW_L4_PER_SCR_H__ */
4457