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alt_l4wd.h
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32 
33 /* Altera - ALT_L4WD */
34 
35 #ifndef __ALTERA_ALT_L4WD_H__
36 #define __ALTERA_ALT_L4WD_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
43 /*
44  * Component : L4 Watchdog Module - ALT_L4WD
45  * L4 Watchdog Module
46  *
47  * Registers in the L4 Watchdog module
48  *
49  */
50 /*
51  * Register : Control Register - wdt_cr
52  *
53  * Contains fields that control operating functions.
54  *
55  * Register Layout
56  *
57  * Bits | Access | Reset | Description
58  * :-------|:-------|:------|:--------------
59  * [0] | RW | 0x0 | Enable
60  * [1] | RW | 0x1 | Response Mode
61  * [31:2] | ??? | 0x0 | *UNDEFINED*
62  *
63  */
64 /*
65  * Field : Enable - wdt_en
66  *
67  * This bit is used to enable and disable the watchdog. When disabled, the counter
68  * does not decrement. Thus, no interrupts or warm reset requests are generated.
69  * Once this bit has been enabled, it can only be cleared only by resetting the
70  * watchdog.
71  *
72  * Field Enumeration Values:
73  *
74  * Enum | Value | Description
75  * :--------------------------|:------|:------------------
76  * ALT_L4WD_CR_WDT_EN_E_DISD | 0x0 | Watchdog disabled
77  * ALT_L4WD_CR_WDT_EN_E_END | 0x1 | Watchdog enabled
78  *
79  * Field Access Macros:
80  *
81  */
82 /*
83  * Enumerated value for register field ALT_L4WD_CR_WDT_EN
84  *
85  * Watchdog disabled
86  */
87 #define ALT_L4WD_CR_WDT_EN_E_DISD 0x0
88 /*
89  * Enumerated value for register field ALT_L4WD_CR_WDT_EN
90  *
91  * Watchdog enabled
92  */
93 #define ALT_L4WD_CR_WDT_EN_E_END 0x1
94 
95 /* The Least Significant Bit (LSB) position of the ALT_L4WD_CR_WDT_EN register field. */
96 #define ALT_L4WD_CR_WDT_EN_LSB 0
97 /* The Most Significant Bit (MSB) position of the ALT_L4WD_CR_WDT_EN register field. */
98 #define ALT_L4WD_CR_WDT_EN_MSB 0
99 /* The width in bits of the ALT_L4WD_CR_WDT_EN register field. */
100 #define ALT_L4WD_CR_WDT_EN_WIDTH 1
101 /* The mask used to set the ALT_L4WD_CR_WDT_EN register field value. */
102 #define ALT_L4WD_CR_WDT_EN_SET_MSK 0x00000001
103 /* The mask used to clear the ALT_L4WD_CR_WDT_EN register field value. */
104 #define ALT_L4WD_CR_WDT_EN_CLR_MSK 0xfffffffe
105 /* The reset value of the ALT_L4WD_CR_WDT_EN register field. */
106 #define ALT_L4WD_CR_WDT_EN_RESET 0x0
107 /* Extracts the ALT_L4WD_CR_WDT_EN field value from a register. */
108 #define ALT_L4WD_CR_WDT_EN_GET(value) (((value) & 0x00000001) >> 0)
109 /* Produces a ALT_L4WD_CR_WDT_EN register field value suitable for setting the register. */
110 #define ALT_L4WD_CR_WDT_EN_SET(value) (((value) << 0) & 0x00000001)
111 
112 /*
113  * Field : Response Mode - rmod
114  *
115  * Selects the output response generated to a timeout.
116  *
117  * Field Enumeration Values:
118  *
119  * Enum | Value | Description
120  * :--------------------------|:------|:----------------------------------------------
121  * ALT_L4WD_CR_RMOD_E_RST | 0x0 | Generate a warm reset request
122  * ALT_L4WD_CR_RMOD_E_IRQRST | 0x1 | First generate an interrupt, and if it is not
123  * : | | cleared by the time a second timeout occurs,
124  * : | | then generate a warm reset request.
125  *
126  * Field Access Macros:
127  *
128  */
129 /*
130  * Enumerated value for register field ALT_L4WD_CR_RMOD
131  *
132  * Generate a warm reset request
133  */
134 #define ALT_L4WD_CR_RMOD_E_RST 0x0
135 /*
136  * Enumerated value for register field ALT_L4WD_CR_RMOD
137  *
138  * First generate an interrupt, and if it is not cleared by the time a second
139  * timeout occurs, then generate a warm reset request.
140  */
141 #define ALT_L4WD_CR_RMOD_E_IRQRST 0x1
142 
143 /* The Least Significant Bit (LSB) position of the ALT_L4WD_CR_RMOD register field. */
144 #define ALT_L4WD_CR_RMOD_LSB 1
145 /* The Most Significant Bit (MSB) position of the ALT_L4WD_CR_RMOD register field. */
146 #define ALT_L4WD_CR_RMOD_MSB 1
147 /* The width in bits of the ALT_L4WD_CR_RMOD register field. */
148 #define ALT_L4WD_CR_RMOD_WIDTH 1
149 /* The mask used to set the ALT_L4WD_CR_RMOD register field value. */
150 #define ALT_L4WD_CR_RMOD_SET_MSK 0x00000002
151 /* The mask used to clear the ALT_L4WD_CR_RMOD register field value. */
152 #define ALT_L4WD_CR_RMOD_CLR_MSK 0xfffffffd
153 /* The reset value of the ALT_L4WD_CR_RMOD register field. */
154 #define ALT_L4WD_CR_RMOD_RESET 0x1
155 /* Extracts the ALT_L4WD_CR_RMOD field value from a register. */
156 #define ALT_L4WD_CR_RMOD_GET(value) (((value) & 0x00000002) >> 1)
157 /* Produces a ALT_L4WD_CR_RMOD register field value suitable for setting the register. */
158 #define ALT_L4WD_CR_RMOD_SET(value) (((value) << 1) & 0x00000002)
159 
160 #ifndef __ASSEMBLY__
161 /*
162  * WARNING: The C register and register group struct declarations are provided for
163  * convenience and illustrative purposes. They should, however, be used with
164  * caution as the C language standard provides no guarantees about the alignment or
165  * atomicity of device memory accesses. The recommended practice for writing
166  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
167  * alt_write_word() functions.
168  *
169  * The struct declaration for register ALT_L4WD_CR.
170  */
171 struct ALT_L4WD_CR_s
172 {
173  uint32_t wdt_en : 1; /* Enable */
174  uint32_t rmod : 1; /* Response Mode */
175  uint32_t : 30; /* *UNDEFINED* */
176 };
177 
178 /* The typedef declaration for register ALT_L4WD_CR. */
179 typedef volatile struct ALT_L4WD_CR_s ALT_L4WD_CR_t;
180 #endif /* __ASSEMBLY__ */
181 
182 /* The byte offset of the ALT_L4WD_CR register from the beginning of the component. */
183 #define ALT_L4WD_CR_OFST 0x0
184 /* The address of the ALT_L4WD_CR register. */
185 #define ALT_L4WD_CR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CR_OFST))
186 
187 /*
188  * Register : Timeout Range Register - wdt_torr
189  *
190  * Contains fields that determine the watchdog timeout.
191  *
192  * Register Layout
193  *
194  * Bits | Access | Reset | Description
195  * :-------|:-------|:------|:----------------------------------
196  * [3:0] | RW | 0xf | Timeout Period
197  * [7:4] | RW | 0xf | Timeout Period for Initialization
198  * [31:8] | ??? | 0x0 | *UNDEFINED*
199  *
200  */
201 /*
202  * Field : Timeout Period - top
203  *
204  * This field is used to select the timeout period from which the watchdog counter
205  * restarts. A change of the timeout period takes effect only after the next
206  * counter restart (kick). The timeout period (in clocks) is:
207  *
208  * t = 2**(16 + top)
209  *
210  * Field Enumeration Values:
211  *
212  * Enum | Value | Description
213  * :----------------------------|:------|:------------------------------
214  * ALT_L4WD_TORR_TOP_E_TMO64K | 0x0 | Timeout = 65536 osc1_clk
215  * ALT_L4WD_TORR_TOP_E_TMO128K | 0x1 | Timeout = 131072 osc1_clk
216  * ALT_L4WD_TORR_TOP_E_TMO256K | 0x2 | Timeout = 262144 osc1_clk
217  * ALT_L4WD_TORR_TOP_E_TMO512K | 0x3 | Timeout = 524288 osc1_clk
218  * ALT_L4WD_TORR_TOP_E_TMO1M | 0x4 | Timeout = 1048576 osc1_clk
219  * ALT_L4WD_TORR_TOP_E_TMO2M | 0x5 | Timeout = 2097152 osc1_clk
220  * ALT_L4WD_TORR_TOP_E_TMO4M | 0x6 | Timeout = 4194304 osc1_clk
221  * ALT_L4WD_TORR_TOP_E_TMO8M | 0x7 | Timeout = 8388608 osc1_clk
222  * ALT_L4WD_TORR_TOP_E_TMO16M | 0x8 | Timeout = 16777216 osc1_clk
223  * ALT_L4WD_TORR_TOP_E_TMO32M | 0x9 | Timeout = 33554432 osc1_clk
224  * ALT_L4WD_TORR_TOP_E_TMO64M | 0xa | Timeout = 67108864 osc1_clk
225  * ALT_L4WD_TORR_TOP_E_TMO128M | 0xb | Timeout = 134217728 osc1_clk
226  * ALT_L4WD_TORR_TOP_E_TMO256M | 0xc | Timeout = 268435456 osc1_clk
227  * ALT_L4WD_TORR_TOP_E_TMO512M | 0xd | Timeout = 536870912 osc1_clk
228  * ALT_L4WD_TORR_TOP_E_TMO1G | 0xe | Timeout = 1073741824 osc1_clk
229  * ALT_L4WD_TORR_TOP_E_TMO2G | 0xf | Timeout = 2147483648 osc1_clk
230  *
231  * Field Access Macros:
232  *
233  */
234 /*
235  * Enumerated value for register field ALT_L4WD_TORR_TOP
236  *
237  * Timeout = 65536 osc1_clk
238  */
239 #define ALT_L4WD_TORR_TOP_E_TMO64K 0x0
240 /*
241  * Enumerated value for register field ALT_L4WD_TORR_TOP
242  *
243  * Timeout = 131072 osc1_clk
244  */
245 #define ALT_L4WD_TORR_TOP_E_TMO128K 0x1
246 /*
247  * Enumerated value for register field ALT_L4WD_TORR_TOP
248  *
249  * Timeout = 262144 osc1_clk
250  */
251 #define ALT_L4WD_TORR_TOP_E_TMO256K 0x2
252 /*
253  * Enumerated value for register field ALT_L4WD_TORR_TOP
254  *
255  * Timeout = 524288 osc1_clk
256  */
257 #define ALT_L4WD_TORR_TOP_E_TMO512K 0x3
258 /*
259  * Enumerated value for register field ALT_L4WD_TORR_TOP
260  *
261  * Timeout = 1048576 osc1_clk
262  */
263 #define ALT_L4WD_TORR_TOP_E_TMO1M 0x4
264 /*
265  * Enumerated value for register field ALT_L4WD_TORR_TOP
266  *
267  * Timeout = 2097152 osc1_clk
268  */
269 #define ALT_L4WD_TORR_TOP_E_TMO2M 0x5
270 /*
271  * Enumerated value for register field ALT_L4WD_TORR_TOP
272  *
273  * Timeout = 4194304 osc1_clk
274  */
275 #define ALT_L4WD_TORR_TOP_E_TMO4M 0x6
276 /*
277  * Enumerated value for register field ALT_L4WD_TORR_TOP
278  *
279  * Timeout = 8388608 osc1_clk
280  */
281 #define ALT_L4WD_TORR_TOP_E_TMO8M 0x7
282 /*
283  * Enumerated value for register field ALT_L4WD_TORR_TOP
284  *
285  * Timeout = 16777216 osc1_clk
286  */
287 #define ALT_L4WD_TORR_TOP_E_TMO16M 0x8
288 /*
289  * Enumerated value for register field ALT_L4WD_TORR_TOP
290  *
291  * Timeout = 33554432 osc1_clk
292  */
293 #define ALT_L4WD_TORR_TOP_E_TMO32M 0x9
294 /*
295  * Enumerated value for register field ALT_L4WD_TORR_TOP
296  *
297  * Timeout = 67108864 osc1_clk
298  */
299 #define ALT_L4WD_TORR_TOP_E_TMO64M 0xa
300 /*
301  * Enumerated value for register field ALT_L4WD_TORR_TOP
302  *
303  * Timeout = 134217728 osc1_clk
304  */
305 #define ALT_L4WD_TORR_TOP_E_TMO128M 0xb
306 /*
307  * Enumerated value for register field ALT_L4WD_TORR_TOP
308  *
309  * Timeout = 268435456 osc1_clk
310  */
311 #define ALT_L4WD_TORR_TOP_E_TMO256M 0xc
312 /*
313  * Enumerated value for register field ALT_L4WD_TORR_TOP
314  *
315  * Timeout = 536870912 osc1_clk
316  */
317 #define ALT_L4WD_TORR_TOP_E_TMO512M 0xd
318 /*
319  * Enumerated value for register field ALT_L4WD_TORR_TOP
320  *
321  * Timeout = 1073741824 osc1_clk
322  */
323 #define ALT_L4WD_TORR_TOP_E_TMO1G 0xe
324 /*
325  * Enumerated value for register field ALT_L4WD_TORR_TOP
326  *
327  * Timeout = 2147483648 osc1_clk
328  */
329 #define ALT_L4WD_TORR_TOP_E_TMO2G 0xf
330 
331 /* The Least Significant Bit (LSB) position of the ALT_L4WD_TORR_TOP register field. */
332 #define ALT_L4WD_TORR_TOP_LSB 0
333 /* The Most Significant Bit (MSB) position of the ALT_L4WD_TORR_TOP register field. */
334 #define ALT_L4WD_TORR_TOP_MSB 3
335 /* The width in bits of the ALT_L4WD_TORR_TOP register field. */
336 #define ALT_L4WD_TORR_TOP_WIDTH 4
337 /* The mask used to set the ALT_L4WD_TORR_TOP register field value. */
338 #define ALT_L4WD_TORR_TOP_SET_MSK 0x0000000f
339 /* The mask used to clear the ALT_L4WD_TORR_TOP register field value. */
340 #define ALT_L4WD_TORR_TOP_CLR_MSK 0xfffffff0
341 /* The reset value of the ALT_L4WD_TORR_TOP register field. */
342 #define ALT_L4WD_TORR_TOP_RESET 0xf
343 /* Extracts the ALT_L4WD_TORR_TOP field value from a register. */
344 #define ALT_L4WD_TORR_TOP_GET(value) (((value) & 0x0000000f) >> 0)
345 /* Produces a ALT_L4WD_TORR_TOP register field value suitable for setting the register. */
346 #define ALT_L4WD_TORR_TOP_SET(value) (((value) << 0) & 0x0000000f)
347 
348 /*
349  * Field : Timeout Period for Initialization - top_init
350  *
351  * Used to select the timeout period that the watchdog counter restarts from for
352  * the first counter restart (kick). This register should be written after reset
353  * and before the watchdog is enabled. A change of the TOP_INIT is seen only once
354  * the watchdog has been enabled, and any change after the first kick is not seen
355  * as subsequent kicks use the period specified by the TOP bits. The timeout period
356  * (in clocks) is:
357  *
358  * t = 2**(16 + top_init)
359  *
360  * Field Enumeration Values:
361  *
362  * Enum | Value | Description
363  * :---------------------------------|:------|:------------------------------
364  * ALT_L4WD_TORR_TOP_INIT_E_TMO64K | 0x0 | Timeout = 65536 osc1_clk
365  * ALT_L4WD_TORR_TOP_INIT_E_TMO128K | 0x1 | Timeout = 131072 osc1_clk
366  * ALT_L4WD_TORR_TOP_INIT_E_TMO256K | 0x2 | Timeout = 262144 osc1_clk
367  * ALT_L4WD_TORR_TOP_INIT_E_TMO512K | 0x3 | Timeout = 524288 osc1_clk
368  * ALT_L4WD_TORR_TOP_INIT_E_TMO1M | 0x4 | Timeout = 1048576 osc1_clk
369  * ALT_L4WD_TORR_TOP_INIT_E_TMO2M | 0x5 | Timeout = 2097152 osc1_clk
370  * ALT_L4WD_TORR_TOP_INIT_E_TMO4M | 0x6 | Timeout = 4194304 osc1_clk
371  * ALT_L4WD_TORR_TOP_INIT_E_TMO8M | 0x7 | Timeout = 8388608 osc1_clk
372  * ALT_L4WD_TORR_TOP_INIT_E_TMO16M | 0x8 | Timeout = 16777216 osc1_clk
373  * ALT_L4WD_TORR_TOP_INIT_E_TMO32M | 0x9 | Timeout = 33554432 osc1_clk
374  * ALT_L4WD_TORR_TOP_INIT_E_TMO64M | 0xa | Timeout = 67108864 osc1_clk
375  * ALT_L4WD_TORR_TOP_INIT_E_TMO128M | 0xb | Timeout = 134217728 osc1_clk
376  * ALT_L4WD_TORR_TOP_INIT_E_TMO256M | 0xc | Timeout = 268435456 osc1_clk
377  * ALT_L4WD_TORR_TOP_INIT_E_TMO512M | 0xd | Timeout = 536870912 osc1_clk
378  * ALT_L4WD_TORR_TOP_INIT_E_TMO1G | 0xe | Timeout = 1073741824 osc1_clk
379  * ALT_L4WD_TORR_TOP_INIT_E_TMO2G | 0xf | Timeout = 2147483648 osc1_clk
380  *
381  * Field Access Macros:
382  *
383  */
384 /*
385  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
386  *
387  * Timeout = 65536 osc1_clk
388  */
389 #define ALT_L4WD_TORR_TOP_INIT_E_TMO64K 0x0
390 /*
391  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
392  *
393  * Timeout = 131072 osc1_clk
394  */
395 #define ALT_L4WD_TORR_TOP_INIT_E_TMO128K 0x1
396 /*
397  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
398  *
399  * Timeout = 262144 osc1_clk
400  */
401 #define ALT_L4WD_TORR_TOP_INIT_E_TMO256K 0x2
402 /*
403  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
404  *
405  * Timeout = 524288 osc1_clk
406  */
407 #define ALT_L4WD_TORR_TOP_INIT_E_TMO512K 0x3
408 /*
409  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
410  *
411  * Timeout = 1048576 osc1_clk
412  */
413 #define ALT_L4WD_TORR_TOP_INIT_E_TMO1M 0x4
414 /*
415  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
416  *
417  * Timeout = 2097152 osc1_clk
418  */
419 #define ALT_L4WD_TORR_TOP_INIT_E_TMO2M 0x5
420 /*
421  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
422  *
423  * Timeout = 4194304 osc1_clk
424  */
425 #define ALT_L4WD_TORR_TOP_INIT_E_TMO4M 0x6
426 /*
427  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
428  *
429  * Timeout = 8388608 osc1_clk
430  */
431 #define ALT_L4WD_TORR_TOP_INIT_E_TMO8M 0x7
432 /*
433  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
434  *
435  * Timeout = 16777216 osc1_clk
436  */
437 #define ALT_L4WD_TORR_TOP_INIT_E_TMO16M 0x8
438 /*
439  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
440  *
441  * Timeout = 33554432 osc1_clk
442  */
443 #define ALT_L4WD_TORR_TOP_INIT_E_TMO32M 0x9
444 /*
445  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
446  *
447  * Timeout = 67108864 osc1_clk
448  */
449 #define ALT_L4WD_TORR_TOP_INIT_E_TMO64M 0xa
450 /*
451  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
452  *
453  * Timeout = 134217728 osc1_clk
454  */
455 #define ALT_L4WD_TORR_TOP_INIT_E_TMO128M 0xb
456 /*
457  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
458  *
459  * Timeout = 268435456 osc1_clk
460  */
461 #define ALT_L4WD_TORR_TOP_INIT_E_TMO256M 0xc
462 /*
463  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
464  *
465  * Timeout = 536870912 osc1_clk
466  */
467 #define ALT_L4WD_TORR_TOP_INIT_E_TMO512M 0xd
468 /*
469  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
470  *
471  * Timeout = 1073741824 osc1_clk
472  */
473 #define ALT_L4WD_TORR_TOP_INIT_E_TMO1G 0xe
474 /*
475  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
476  *
477  * Timeout = 2147483648 osc1_clk
478  */
479 #define ALT_L4WD_TORR_TOP_INIT_E_TMO2G 0xf
480 
481 /* The Least Significant Bit (LSB) position of the ALT_L4WD_TORR_TOP_INIT register field. */
482 #define ALT_L4WD_TORR_TOP_INIT_LSB 4
483 /* The Most Significant Bit (MSB) position of the ALT_L4WD_TORR_TOP_INIT register field. */
484 #define ALT_L4WD_TORR_TOP_INIT_MSB 7
485 /* The width in bits of the ALT_L4WD_TORR_TOP_INIT register field. */
486 #define ALT_L4WD_TORR_TOP_INIT_WIDTH 4
487 /* The mask used to set the ALT_L4WD_TORR_TOP_INIT register field value. */
488 #define ALT_L4WD_TORR_TOP_INIT_SET_MSK 0x000000f0
489 /* The mask used to clear the ALT_L4WD_TORR_TOP_INIT register field value. */
490 #define ALT_L4WD_TORR_TOP_INIT_CLR_MSK 0xffffff0f
491 /* The reset value of the ALT_L4WD_TORR_TOP_INIT register field. */
492 #define ALT_L4WD_TORR_TOP_INIT_RESET 0xf
493 /* Extracts the ALT_L4WD_TORR_TOP_INIT field value from a register. */
494 #define ALT_L4WD_TORR_TOP_INIT_GET(value) (((value) & 0x000000f0) >> 4)
495 /* Produces a ALT_L4WD_TORR_TOP_INIT register field value suitable for setting the register. */
496 #define ALT_L4WD_TORR_TOP_INIT_SET(value) (((value) << 4) & 0x000000f0)
497 
498 #ifndef __ASSEMBLY__
499 /*
500  * WARNING: The C register and register group struct declarations are provided for
501  * convenience and illustrative purposes. They should, however, be used with
502  * caution as the C language standard provides no guarantees about the alignment or
503  * atomicity of device memory accesses. The recommended practice for writing
504  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
505  * alt_write_word() functions.
506  *
507  * The struct declaration for register ALT_L4WD_TORR.
508  */
509 struct ALT_L4WD_TORR_s
510 {
511  uint32_t top : 4; /* Timeout Period */
512  uint32_t top_init : 4; /* Timeout Period for Initialization */
513  uint32_t : 24; /* *UNDEFINED* */
514 };
515 
516 /* The typedef declaration for register ALT_L4WD_TORR. */
517 typedef volatile struct ALT_L4WD_TORR_s ALT_L4WD_TORR_t;
518 #endif /* __ASSEMBLY__ */
519 
520 /* The byte offset of the ALT_L4WD_TORR register from the beginning of the component. */
521 #define ALT_L4WD_TORR_OFST 0x4
522 /* The address of the ALT_L4WD_TORR register. */
523 #define ALT_L4WD_TORR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_TORR_OFST))
524 
525 /*
526  * Register : Current Counter Value Register - wdt_ccvr
527  *
528  * See Field Description
529  *
530  * Register Layout
531  *
532  * Bits | Access | Reset | Description
533  * :-------|:-------|:-----------|:----------------------
534  * [31:0] | R | 0x7fffffff | Current Counter Value
535  *
536  */
537 /*
538  * Field : Current Counter Value - wdt_ccvr
539  *
540  * This register provides the current value of the internal counter.
541  *
542  * Field Access Macros:
543  *
544  */
545 /* The Least Significant Bit (LSB) position of the ALT_L4WD_CCVR_WDT_CCVR register field. */
546 #define ALT_L4WD_CCVR_WDT_CCVR_LSB 0
547 /* The Most Significant Bit (MSB) position of the ALT_L4WD_CCVR_WDT_CCVR register field. */
548 #define ALT_L4WD_CCVR_WDT_CCVR_MSB 31
549 /* The width in bits of the ALT_L4WD_CCVR_WDT_CCVR register field. */
550 #define ALT_L4WD_CCVR_WDT_CCVR_WIDTH 32
551 /* The mask used to set the ALT_L4WD_CCVR_WDT_CCVR register field value. */
552 #define ALT_L4WD_CCVR_WDT_CCVR_SET_MSK 0xffffffff
553 /* The mask used to clear the ALT_L4WD_CCVR_WDT_CCVR register field value. */
554 #define ALT_L4WD_CCVR_WDT_CCVR_CLR_MSK 0x00000000
555 /* The reset value of the ALT_L4WD_CCVR_WDT_CCVR register field. */
556 #define ALT_L4WD_CCVR_WDT_CCVR_RESET 0x7fffffff
557 /* Extracts the ALT_L4WD_CCVR_WDT_CCVR field value from a register. */
558 #define ALT_L4WD_CCVR_WDT_CCVR_GET(value) (((value) & 0xffffffff) >> 0)
559 /* Produces a ALT_L4WD_CCVR_WDT_CCVR register field value suitable for setting the register. */
560 #define ALT_L4WD_CCVR_WDT_CCVR_SET(value) (((value) << 0) & 0xffffffff)
561 
562 #ifndef __ASSEMBLY__
563 /*
564  * WARNING: The C register and register group struct declarations are provided for
565  * convenience and illustrative purposes. They should, however, be used with
566  * caution as the C language standard provides no guarantees about the alignment or
567  * atomicity of device memory accesses. The recommended practice for writing
568  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
569  * alt_write_word() functions.
570  *
571  * The struct declaration for register ALT_L4WD_CCVR.
572  */
573 struct ALT_L4WD_CCVR_s
574 {
575  const uint32_t wdt_ccvr : 32; /* Current Counter Value */
576 };
577 
578 /* The typedef declaration for register ALT_L4WD_CCVR. */
579 typedef volatile struct ALT_L4WD_CCVR_s ALT_L4WD_CCVR_t;
580 #endif /* __ASSEMBLY__ */
581 
582 /* The byte offset of the ALT_L4WD_CCVR register from the beginning of the component. */
583 #define ALT_L4WD_CCVR_OFST 0x8
584 /* The address of the ALT_L4WD_CCVR register. */
585 #define ALT_L4WD_CCVR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CCVR_OFST))
586 
587 /*
588  * Register : Counter Restart Register - wdt_crr
589  *
590  * Restarts the watchdog.
591  *
592  * Register Layout
593  *
594  * Bits | Access | Reset | Description
595  * :-------|:-------|:------|:-------------------------
596  * [7:0] | W | 0x0 | Counter Restart Register
597  * [31:8] | ??? | 0x0 | *UNDEFINED*
598  *
599  */
600 /*
601  * Field : Counter Restart Register - wdt_crr
602  *
603  * This register is used to restart the watchdog counter. As a safety feature to
604  * prevent accidental restarts, the kick value of 0x76 must be written. A restart
605  * also clears the watchdog interrupt.
606  *
607  * Field Enumeration Values:
608  *
609  * Enum | Value | Description
610  * :----------------------------|:------|:-----------------------------------------
611  * ALT_L4WD_CRR_WDT_CRR_E_KICK | 0x76 | Value to write to restart watchdog timer
612  *
613  * Field Access Macros:
614  *
615  */
616 /*
617  * Enumerated value for register field ALT_L4WD_CRR_WDT_CRR
618  *
619  * Value to write to restart watchdog timer
620  */
621 #define ALT_L4WD_CRR_WDT_CRR_E_KICK 0x76
622 
623 /* The Least Significant Bit (LSB) position of the ALT_L4WD_CRR_WDT_CRR register field. */
624 #define ALT_L4WD_CRR_WDT_CRR_LSB 0
625 /* The Most Significant Bit (MSB) position of the ALT_L4WD_CRR_WDT_CRR register field. */
626 #define ALT_L4WD_CRR_WDT_CRR_MSB 7
627 /* The width in bits of the ALT_L4WD_CRR_WDT_CRR register field. */
628 #define ALT_L4WD_CRR_WDT_CRR_WIDTH 8
629 /* The mask used to set the ALT_L4WD_CRR_WDT_CRR register field value. */
630 #define ALT_L4WD_CRR_WDT_CRR_SET_MSK 0x000000ff
631 /* The mask used to clear the ALT_L4WD_CRR_WDT_CRR register field value. */
632 #define ALT_L4WD_CRR_WDT_CRR_CLR_MSK 0xffffff00
633 /* The reset value of the ALT_L4WD_CRR_WDT_CRR register field. */
634 #define ALT_L4WD_CRR_WDT_CRR_RESET 0x0
635 /* Extracts the ALT_L4WD_CRR_WDT_CRR field value from a register. */
636 #define ALT_L4WD_CRR_WDT_CRR_GET(value) (((value) & 0x000000ff) >> 0)
637 /* Produces a ALT_L4WD_CRR_WDT_CRR register field value suitable for setting the register. */
638 #define ALT_L4WD_CRR_WDT_CRR_SET(value) (((value) << 0) & 0x000000ff)
639 
640 #ifndef __ASSEMBLY__
641 /*
642  * WARNING: The C register and register group struct declarations are provided for
643  * convenience and illustrative purposes. They should, however, be used with
644  * caution as the C language standard provides no guarantees about the alignment or
645  * atomicity of device memory accesses. The recommended practice for writing
646  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
647  * alt_write_word() functions.
648  *
649  * The struct declaration for register ALT_L4WD_CRR.
650  */
651 struct ALT_L4WD_CRR_s
652 {
653  uint32_t wdt_crr : 8; /* Counter Restart Register */
654  uint32_t : 24; /* *UNDEFINED* */
655 };
656 
657 /* The typedef declaration for register ALT_L4WD_CRR. */
658 typedef volatile struct ALT_L4WD_CRR_s ALT_L4WD_CRR_t;
659 #endif /* __ASSEMBLY__ */
660 
661 /* The byte offset of the ALT_L4WD_CRR register from the beginning of the component. */
662 #define ALT_L4WD_CRR_OFST 0xc
663 /* The address of the ALT_L4WD_CRR register. */
664 #define ALT_L4WD_CRR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CRR_OFST))
665 
666 /*
667  * Register : Interrupt Status Register. - wdt_stat
668  *
669  * Provides interrupt status
670  *
671  * Register Layout
672  *
673  * Bits | Access | Reset | Description
674  * :-------|:-------|:------|:-----------------
675  * [0] | R | 0x0 | Interrupt Status
676  * [31:1] | ??? | 0x0 | *UNDEFINED*
677  *
678  */
679 /*
680  * Field : Interrupt Status - wdt_stat
681  *
682  * Provides the interrupt status of the watchdog.
683  *
684  * Field Enumeration Values:
685  *
686  * Enum | Value | Description
687  * :-------------------------------|:------|:----------------------
688  * ALT_L4WD_STAT_WDT_STAT_E_ACT | 0x1 | Interrupt is active
689  * ALT_L4WD_STAT_WDT_STAT_E_INACT | 0x0 | Interrupt is inactive
690  *
691  * Field Access Macros:
692  *
693  */
694 /*
695  * Enumerated value for register field ALT_L4WD_STAT_WDT_STAT
696  *
697  * Interrupt is active
698  */
699 #define ALT_L4WD_STAT_WDT_STAT_E_ACT 0x1
700 /*
701  * Enumerated value for register field ALT_L4WD_STAT_WDT_STAT
702  *
703  * Interrupt is inactive
704  */
705 #define ALT_L4WD_STAT_WDT_STAT_E_INACT 0x0
706 
707 /* The Least Significant Bit (LSB) position of the ALT_L4WD_STAT_WDT_STAT register field. */
708 #define ALT_L4WD_STAT_WDT_STAT_LSB 0
709 /* The Most Significant Bit (MSB) position of the ALT_L4WD_STAT_WDT_STAT register field. */
710 #define ALT_L4WD_STAT_WDT_STAT_MSB 0
711 /* The width in bits of the ALT_L4WD_STAT_WDT_STAT register field. */
712 #define ALT_L4WD_STAT_WDT_STAT_WIDTH 1
713 /* The mask used to set the ALT_L4WD_STAT_WDT_STAT register field value. */
714 #define ALT_L4WD_STAT_WDT_STAT_SET_MSK 0x00000001
715 /* The mask used to clear the ALT_L4WD_STAT_WDT_STAT register field value. */
716 #define ALT_L4WD_STAT_WDT_STAT_CLR_MSK 0xfffffffe
717 /* The reset value of the ALT_L4WD_STAT_WDT_STAT register field. */
718 #define ALT_L4WD_STAT_WDT_STAT_RESET 0x0
719 /* Extracts the ALT_L4WD_STAT_WDT_STAT field value from a register. */
720 #define ALT_L4WD_STAT_WDT_STAT_GET(value) (((value) & 0x00000001) >> 0)
721 /* Produces a ALT_L4WD_STAT_WDT_STAT register field value suitable for setting the register. */
722 #define ALT_L4WD_STAT_WDT_STAT_SET(value) (((value) << 0) & 0x00000001)
723 
724 #ifndef __ASSEMBLY__
725 /*
726  * WARNING: The C register and register group struct declarations are provided for
727  * convenience and illustrative purposes. They should, however, be used with
728  * caution as the C language standard provides no guarantees about the alignment or
729  * atomicity of device memory accesses. The recommended practice for writing
730  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
731  * alt_write_word() functions.
732  *
733  * The struct declaration for register ALT_L4WD_STAT.
734  */
735 struct ALT_L4WD_STAT_s
736 {
737  const uint32_t wdt_stat : 1; /* Interrupt Status */
738  uint32_t : 31; /* *UNDEFINED* */
739 };
740 
741 /* The typedef declaration for register ALT_L4WD_STAT. */
742 typedef volatile struct ALT_L4WD_STAT_s ALT_L4WD_STAT_t;
743 #endif /* __ASSEMBLY__ */
744 
745 /* The byte offset of the ALT_L4WD_STAT register from the beginning of the component. */
746 #define ALT_L4WD_STAT_OFST 0x10
747 /* The address of the ALT_L4WD_STAT register. */
748 #define ALT_L4WD_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_STAT_OFST))
749 
750 /*
751  * Register : Interrupt Clear Register - wdt_eoi
752  *
753  * Clears the watchdog interrupt when read.
754  *
755  * Register Layout
756  *
757  * Bits | Access | Reset | Description
758  * :-------|:-------|:------|:----------------
759  * [0] | R | 0x0 | Interrupt Clear
760  * [31:1] | ??? | 0x0 | *UNDEFINED*
761  *
762  */
763 /*
764  * Field : Interrupt Clear - wdt_eoi
765  *
766  * Clears the watchdog interrupt. This can be used to clear the interrupt without
767  * restarting the watchdog counter.
768  *
769  * Field Access Macros:
770  *
771  */
772 /* The Least Significant Bit (LSB) position of the ALT_L4WD_EOI_WDT_EOI register field. */
773 #define ALT_L4WD_EOI_WDT_EOI_LSB 0
774 /* The Most Significant Bit (MSB) position of the ALT_L4WD_EOI_WDT_EOI register field. */
775 #define ALT_L4WD_EOI_WDT_EOI_MSB 0
776 /* The width in bits of the ALT_L4WD_EOI_WDT_EOI register field. */
777 #define ALT_L4WD_EOI_WDT_EOI_WIDTH 1
778 /* The mask used to set the ALT_L4WD_EOI_WDT_EOI register field value. */
779 #define ALT_L4WD_EOI_WDT_EOI_SET_MSK 0x00000001
780 /* The mask used to clear the ALT_L4WD_EOI_WDT_EOI register field value. */
781 #define ALT_L4WD_EOI_WDT_EOI_CLR_MSK 0xfffffffe
782 /* The reset value of the ALT_L4WD_EOI_WDT_EOI register field. */
783 #define ALT_L4WD_EOI_WDT_EOI_RESET 0x0
784 /* Extracts the ALT_L4WD_EOI_WDT_EOI field value from a register. */
785 #define ALT_L4WD_EOI_WDT_EOI_GET(value) (((value) & 0x00000001) >> 0)
786 /* Produces a ALT_L4WD_EOI_WDT_EOI register field value suitable for setting the register. */
787 #define ALT_L4WD_EOI_WDT_EOI_SET(value) (((value) << 0) & 0x00000001)
788 
789 #ifndef __ASSEMBLY__
790 /*
791  * WARNING: The C register and register group struct declarations are provided for
792  * convenience and illustrative purposes. They should, however, be used with
793  * caution as the C language standard provides no guarantees about the alignment or
794  * atomicity of device memory accesses. The recommended practice for writing
795  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
796  * alt_write_word() functions.
797  *
798  * The struct declaration for register ALT_L4WD_EOI.
799  */
800 struct ALT_L4WD_EOI_s
801 {
802  const uint32_t wdt_eoi : 1; /* Interrupt Clear */
803  uint32_t : 31; /* *UNDEFINED* */
804 };
805 
806 /* The typedef declaration for register ALT_L4WD_EOI. */
807 typedef volatile struct ALT_L4WD_EOI_s ALT_L4WD_EOI_t;
808 #endif /* __ASSEMBLY__ */
809 
810 /* The byte offset of the ALT_L4WD_EOI register from the beginning of the component. */
811 #define ALT_L4WD_EOI_OFST 0x14
812 /* The address of the ALT_L4WD_EOI register. */
813 #define ALT_L4WD_EOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_EOI_OFST))
814 
815 /*
816  * Register : Component Parameters Register 5 - cp_wdt_user_top_max
817  *
818  * This is a constant read-only register that contains encoded information about
819  * the component's parameter settings.
820  *
821  * Register Layout
822  *
823  * Bits | Access | Reset | Description
824  * :-------|:-------|:------|:-----------------------
825  * [31:0] | R | 0x0 | Component Parameters 5
826  *
827  */
828 /*
829  * Field : Component Parameters 5 - cp_wdt_user_top_max
830  *
831  * Upper limit of Timeout Period parameters.
832  *
833  * Field Access Macros:
834  *
835  */
836 /* The Least Significant Bit (LSB) position of the ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL register field. */
837 #define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_LSB 0
838 /* The Most Significant Bit (MSB) position of the ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL register field. */
839 #define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_MSB 31
840 /* The width in bits of the ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL register field. */
841 #define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_WIDTH 32
842 /* The mask used to set the ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL register field value. */
843 #define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_SET_MSK 0xffffffff
844 /* The mask used to clear the ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL register field value. */
845 #define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_CLR_MSK 0x00000000
846 /* The reset value of the ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL register field. */
847 #define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_RESET 0x0
848 /* Extracts the ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL field value from a register. */
849 #define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_GET(value) (((value) & 0xffffffff) >> 0)
850 /* Produces a ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL register field value suitable for setting the register. */
851 #define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_SET(value) (((value) << 0) & 0xffffffff)
852 
853 #ifndef __ASSEMBLY__
854 /*
855  * WARNING: The C register and register group struct declarations are provided for
856  * convenience and illustrative purposes. They should, however, be used with
857  * caution as the C language standard provides no guarantees about the alignment or
858  * atomicity of device memory accesses. The recommended practice for writing
859  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
860  * alt_write_word() functions.
861  *
862  * The struct declaration for register ALT_L4WD_CP_WDT_USER_TOP_MAX.
863  */
864 struct ALT_L4WD_CP_WDT_USER_TOP_MAX_s
865 {
866  const uint32_t cp_wdt_user_top_max : 32; /* Component Parameters 5 */
867 };
868 
869 /* The typedef declaration for register ALT_L4WD_CP_WDT_USER_TOP_MAX. */
870 typedef volatile struct ALT_L4WD_CP_WDT_USER_TOP_MAX_s ALT_L4WD_CP_WDT_USER_TOP_MAX_t;
871 #endif /* __ASSEMBLY__ */
872 
873 /* The byte offset of the ALT_L4WD_CP_WDT_USER_TOP_MAX register from the beginning of the component. */
874 #define ALT_L4WD_CP_WDT_USER_TOP_MAX_OFST 0xe4
875 /* The address of the ALT_L4WD_CP_WDT_USER_TOP_MAX register. */
876 #define ALT_L4WD_CP_WDT_USER_TOP_MAX_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CP_WDT_USER_TOP_MAX_OFST))
877 
878 /*
879  * Register : Component Parameters Register 4 - cp_wdt_user_top_init_max
880  *
881  * This is a constant read-only register that contains encoded information about
882  * the component's parameter settings
883  *
884  * Register Layout
885  *
886  * Bits | Access | Reset | Description
887  * :-------|:-------|:------|:-----------------------
888  * [31:0] | R | 0x0 | Component Parameters 4
889  *
890  */
891 /*
892  * Field : Component Parameters 4 - cp_wdt_user_top_init_max
893  *
894  * Upper limit of Initial Timeout Period parameters.
895  *
896  * Field Access Macros:
897  *
898  */
899 /* The Least Significant Bit (LSB) position of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL register field. */
900 #define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_LSB 0
901 /* The Most Significant Bit (MSB) position of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL register field. */
902 #define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_MSB 31
903 /* The width in bits of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL register field. */
904 #define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_WIDTH 32
905 /* The mask used to set the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL register field value. */
906 #define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_SET_MSK 0xffffffff
907 /* The mask used to clear the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL register field value. */
908 #define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_CLR_MSK 0x00000000
909 /* The reset value of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL register field. */
910 #define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_RESET 0x0
911 /* Extracts the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL field value from a register. */
912 #define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_GET(value) (((value) & 0xffffffff) >> 0)
913 /* Produces a ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL register field value suitable for setting the register. */
914 #define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_SET(value) (((value) << 0) & 0xffffffff)
915 
916 #ifndef __ASSEMBLY__
917 /*
918  * WARNING: The C register and register group struct declarations are provided for
919  * convenience and illustrative purposes. They should, however, be used with
920  * caution as the C language standard provides no guarantees about the alignment or
921  * atomicity of device memory accesses. The recommended practice for writing
922  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
923  * alt_write_word() functions.
924  *
925  * The struct declaration for register ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX.
926  */
927 struct ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_s
928 {
929  const uint32_t cp_wdt_user_top_init_max : 32; /* Component Parameters 4 */
930 };
931 
932 /* The typedef declaration for register ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX. */
933 typedef volatile struct ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_s ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_t;
934 #endif /* __ASSEMBLY__ */
935 
936 /* The byte offset of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX register from the beginning of the component. */
937 #define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_OFST 0xe8
938 /* The address of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX register. */
939 #define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_OFST))
940 
941 /*
942  * Register : Component Parameters Register 3 - cd_wdt_top_rst
943  *
944  * This is a constant read-only register that contains encoded information about
945  * the component's parameter settings.
946  *
947  * Register Layout
948  *
949  * Bits | Access | Reset | Description
950  * :-------|:-------|:------|:------------------------
951  * [31:0] | R | 0xff | Component Parameters 3
952  *
953  */
954 /*
955  * Field : Component Parameters 3 - cd_wdt_top_rst
956  *
957  * Contains the reset value of the WDT_TORR register.
958  *
959  * Field Access Macros:
960  *
961  */
962 /* The Least Significant Bit (LSB) position of the ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST register field. */
963 #define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_LSB 0
964 /* The Most Significant Bit (MSB) position of the ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST register field. */
965 #define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_MSB 31
966 /* The width in bits of the ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST register field. */
967 #define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_WIDTH 32
968 /* The mask used to set the ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST register field value. */
969 #define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_SET_MSK 0xffffffff
970 /* The mask used to clear the ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST register field value. */
971 #define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_CLR_MSK 0x00000000
972 /* The reset value of the ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST register field. */
973 #define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_RESET 0xff
974 /* Extracts the ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST field value from a register. */
975 #define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_GET(value) (((value) & 0xffffffff) >> 0)
976 /* Produces a ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST register field value suitable for setting the register. */
977 #define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_SET(value) (((value) << 0) & 0xffffffff)
978 
979 #ifndef __ASSEMBLY__
980 /*
981  * WARNING: The C register and register group struct declarations are provided for
982  * convenience and illustrative purposes. They should, however, be used with
983  * caution as the C language standard provides no guarantees about the alignment or
984  * atomicity of device memory accesses. The recommended practice for writing
985  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
986  * alt_write_word() functions.
987  *
988  * The struct declaration for register ALT_L4WD_CD_WDT_TOP_RST.
989  */
990 struct ALT_L4WD_CD_WDT_TOP_RST_s
991 {
992  const uint32_t cd_wdt_top_rst : 32; /* Component Parameters 3 */
993 };
994 
995 /* The typedef declaration for register ALT_L4WD_CD_WDT_TOP_RST. */
996 typedef volatile struct ALT_L4WD_CD_WDT_TOP_RST_s ALT_L4WD_CD_WDT_TOP_RST_t;
997 #endif /* __ASSEMBLY__ */
998 
999 /* The byte offset of the ALT_L4WD_CD_WDT_TOP_RST register from the beginning of the component. */
1000 #define ALT_L4WD_CD_WDT_TOP_RST_OFST 0xec
1001 /* The address of the ALT_L4WD_CD_WDT_TOP_RST register. */
1002 #define ALT_L4WD_CD_WDT_TOP_RST_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CD_WDT_TOP_RST_OFST))
1003 
1004 /*
1005  * Register : Component Parameters Register 2 - cp_wdt_cnt_rst
1006  *
1007  * This is a constant read-only register that contains encoded information about
1008  * the component's parameter settings.
1009  *
1010  * Register Layout
1011  *
1012  * Bits | Access | Reset | Description
1013  * :-------|:-------|:-----------|:------------------------
1014  * [31:0] | R | 0x7fffffff | Component Parameters 2
1015  *
1016  */
1017 /*
1018  * Field : Component Parameters 2 - cp_wdt_cnt_rst
1019  *
1020  * The timeout period range is fixed. The range increments by the power of 2 from 2
1021  * to the 16 to 2 to the 31.
1022  *
1023  * Field Access Macros:
1024  *
1025  */
1026 /* The Least Significant Bit (LSB) position of the ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST register field. */
1027 #define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_LSB 0
1028 /* The Most Significant Bit (MSB) position of the ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST register field. */
1029 #define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_MSB 31
1030 /* The width in bits of the ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST register field. */
1031 #define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_WIDTH 32
1032 /* The mask used to set the ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST register field value. */
1033 #define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_SET_MSK 0xffffffff
1034 /* The mask used to clear the ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST register field value. */
1035 #define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_CLR_MSK 0x00000000
1036 /* The reset value of the ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST register field. */
1037 #define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_RESET 0x7fffffff
1038 /* Extracts the ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST field value from a register. */
1039 #define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_GET(value) (((value) & 0xffffffff) >> 0)
1040 /* Produces a ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST register field value suitable for setting the register. */
1041 #define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_SET(value) (((value) << 0) & 0xffffffff)
1042 
1043 #ifndef __ASSEMBLY__
1044 /*
1045  * WARNING: The C register and register group struct declarations are provided for
1046  * convenience and illustrative purposes. They should, however, be used with
1047  * caution as the C language standard provides no guarantees about the alignment or
1048  * atomicity of device memory accesses. The recommended practice for writing
1049  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1050  * alt_write_word() functions.
1051  *
1052  * The struct declaration for register ALT_L4WD_CP_WDT_CNT_RST.
1053  */
1054 struct ALT_L4WD_CP_WDT_CNT_RST_s
1055 {
1056  const uint32_t cp_wdt_cnt_rst : 32; /* Component Parameters 2 */
1057 };
1058 
1059 /* The typedef declaration for register ALT_L4WD_CP_WDT_CNT_RST. */
1060 typedef volatile struct ALT_L4WD_CP_WDT_CNT_RST_s ALT_L4WD_CP_WDT_CNT_RST_t;
1061 #endif /* __ASSEMBLY__ */
1062 
1063 /* The byte offset of the ALT_L4WD_CP_WDT_CNT_RST register from the beginning of the component. */
1064 #define ALT_L4WD_CP_WDT_CNT_RST_OFST 0xf0
1065 /* The address of the ALT_L4WD_CP_WDT_CNT_RST register. */
1066 #define ALT_L4WD_CP_WDT_CNT_RST_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CP_WDT_CNT_RST_OFST))
1067 
1068 /*
1069  * Register : Component Parameters Register 1 - wdt_comp_param_1
1070  *
1071  * This is a constant read-only register that contains encoded information about
1072  * the component's parameter settings.
1073  *
1074  * Register Layout
1075  *
1076  * Bits | Access | Reset | Description
1077  * :--------|:-------|:------|:---------------------------------------
1078  * [0] | R | 0x0 | Always Enable
1079  * [1] | R | 0x0 | Default Mode
1080  * [2] | R | 0x1 | Dual Timeout Period
1081  * [3] | R | 0x0 | Hardcode Response Mode
1082  * [4] | R | 0x1 | Hardcode Reset Pulse Length
1083  * [5] | R | 0x0 | Hardcode Timeout Period
1084  * [6] | R | 0x1 | Use Pre-defined (Fixed) Timeout Values
1085  * [7] | R | 0x0 | Include Pause Input
1086  * [9:8] | R | 0x2 | APB Data Width
1087  * [12:10] | R | 0x0 | Default Reset Pulse Length
1088  * [15:13] | ??? | 0x0 | *UNDEFINED*
1089  * [19:16] | R | 0xf | Default Timeout Period
1090  * [23:20] | R | 0xf | Default Initial Timeout Period
1091  * [28:24] | R | 0x10 | Counter Width in Bits
1092  * [31:29] | ??? | 0x0 | *UNDEFINED*
1093  *
1094  */
1095 /*
1096  * Field : Always Enable - cp_wdt_always_en
1097  *
1098  * Specifies whether watchdog starts after reset or not.
1099  *
1100  * Field Enumeration Values:
1101  *
1102  * Enum | Value | Description
1103  * :----------------------------------------------|:------|:---------------------------
1104  * ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_E_DISD | 0x0 | Watchdog disabled on reset
1105  *
1106  * Field Access Macros:
1107  *
1108  */
1109 /*
1110  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN
1111  *
1112  * Watchdog disabled on reset
1113  */
1114 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_E_DISD 0x0
1115 
1116 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field. */
1117 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_LSB 0
1118 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field. */
1119 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_MSB 0
1120 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field. */
1121 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_WIDTH 1
1122 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field value. */
1123 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_SET_MSK 0x00000001
1124 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field value. */
1125 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_CLR_MSK 0xfffffffe
1126 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field. */
1127 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_RESET 0x0
1128 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN field value from a register. */
1129 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_GET(value) (((value) & 0x00000001) >> 0)
1130 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field value suitable for setting the register. */
1131 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_SET(value) (((value) << 0) & 0x00000001)
1132 
1133 /*
1134  * Field : Default Mode - cp_wdt_dflt_rmod
1135  *
1136  * Specifies default output response mode after reset.
1137  *
1138  * Field Enumeration Values:
1139  *
1140  * Enum | Value | Description
1141  * :------------------------------------------------|:------|:-------------------------------------------------
1142  * ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_E_RSTREQ | 0x0 | Generate a warm reset request (don't generate an
1143  * : | | interrupt first)
1144  *
1145  * Field Access Macros:
1146  *
1147  */
1148 /*
1149  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD
1150  *
1151  * Generate a warm reset request (don't generate an interrupt first)
1152  */
1153 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_E_RSTREQ 0x0
1154 
1155 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field. */
1156 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_LSB 1
1157 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field. */
1158 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_MSB 1
1159 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field. */
1160 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_WIDTH 1
1161 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field value. */
1162 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_SET_MSK 0x00000002
1163 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field value. */
1164 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_CLR_MSK 0xfffffffd
1165 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field. */
1166 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_RESET 0x0
1167 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD field value from a register. */
1168 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_GET(value) (((value) & 0x00000002) >> 1)
1169 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field value suitable for setting the register. */
1170 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_SET(value) (((value) << 1) & 0x00000002)
1171 
1172 /*
1173  * Field : Dual Timeout Period - cp_wdt_dual_top
1174  *
1175  * Specifies whether a second timeout period that is used for initialization prior
1176  * to the first kick is present or not.
1177  *
1178  * Field Enumeration Values:
1179  *
1180  * Enum | Value | Description
1181  * :------------------------------------------------|:------|:---------------------------------
1182  * ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_E_DUALTOP | 0x1 | Second timeout period is present
1183  *
1184  * Field Access Macros:
1185  *
1186  */
1187 /*
1188  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP
1189  *
1190  * Second timeout period is present
1191  */
1192 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_E_DUALTOP 0x1
1193 
1194 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field. */
1195 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_LSB 2
1196 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field. */
1197 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_MSB 2
1198 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field. */
1199 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_WIDTH 1
1200 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field value. */
1201 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_SET_MSK 0x00000004
1202 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field value. */
1203 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_CLR_MSK 0xfffffffb
1204 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field. */
1205 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_RESET 0x1
1206 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP field value from a register. */
1207 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_GET(value) (((value) & 0x00000004) >> 2)
1208 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field value suitable for setting the register. */
1209 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_SET(value) (((value) << 2) & 0x00000004)
1210 
1211 /*
1212  * Field : Hardcode Response Mode - cp_wdt_hc_rmod
1213  *
1214  * Specifies if response mode (when counter reaches 0) is programmable or
1215  * hardcoded.
1216  *
1217  * Field Enumeration Values:
1218  *
1219  * Enum | Value | Description
1220  * :--------------------------------------------|:------|:--------------------------------------
1221  * ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_E_PGML | 0x0 | Output response mode is programmable.
1222  *
1223  * Field Access Macros:
1224  *
1225  */
1226 /*
1227  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD
1228  *
1229  * Output response mode is programmable.
1230  */
1231 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_E_PGML 0x0
1232 
1233 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field. */
1234 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_LSB 3
1235 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field. */
1236 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_MSB 3
1237 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field. */
1238 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_WIDTH 1
1239 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field value. */
1240 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_SET_MSK 0x00000008
1241 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field value. */
1242 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_CLR_MSK 0xfffffff7
1243 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field. */
1244 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_RESET 0x0
1245 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD field value from a register. */
1246 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_GET(value) (((value) & 0x00000008) >> 3)
1247 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field value suitable for setting the register. */
1248 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_SET(value) (((value) << 3) & 0x00000008)
1249 
1250 /*
1251  * Field : Hardcode Reset Pulse Length - cp_wdt_hc_rpl
1252  *
1253  * Specifies if the reset pulse length is programmable or hardcoded.
1254  *
1255  * Field Enumeration Values:
1256  *
1257  * Enum | Value | Description
1258  * :------------------------------------------------|:------|:---------------------------------
1259  * ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_E_HARDCODED | 0x1 | Reset pulse length is hardcoded.
1260  *
1261  * Field Access Macros:
1262  *
1263  */
1264 /*
1265  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL
1266  *
1267  * Reset pulse length is hardcoded.
1268  */
1269 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_E_HARDCODED 0x1
1270 
1271 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field. */
1272 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_LSB 4
1273 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field. */
1274 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_MSB 4
1275 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field. */
1276 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_WIDTH 1
1277 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field value. */
1278 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_SET_MSK 0x00000010
1279 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field value. */
1280 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_CLR_MSK 0xffffffef
1281 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field. */
1282 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_RESET 0x1
1283 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL field value from a register. */
1284 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_GET(value) (((value) & 0x00000010) >> 4)
1285 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field value suitable for setting the register. */
1286 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_SET(value) (((value) << 4) & 0x00000010)
1287 
1288 /*
1289  * Field : Hardcode Timeout Period - cp_wdt_hc_top
1290  *
1291  * Specifies if the timeout period is programmable or hardcoded.
1292  *
1293  * Field Enumeration Values:
1294  *
1295  * Enum | Value | Description
1296  * :-------------------------------------------|:------|:--------------------------------
1297  * ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_E_PGML | 0x0 | Timeout period is programmable.
1298  *
1299  * Field Access Macros:
1300  *
1301  */
1302 /*
1303  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP
1304  *
1305  * Timeout period is programmable.
1306  */
1307 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_E_PGML 0x0
1308 
1309 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field. */
1310 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_LSB 5
1311 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field. */
1312 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_MSB 5
1313 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field. */
1314 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_WIDTH 1
1315 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field value. */
1316 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_SET_MSK 0x00000020
1317 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field value. */
1318 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_CLR_MSK 0xffffffdf
1319 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field. */
1320 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_RESET 0x0
1321 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP field value from a register. */
1322 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_GET(value) (((value) & 0x00000020) >> 5)
1323 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field value suitable for setting the register. */
1324 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_SET(value) (((value) << 5) & 0x00000020)
1325 
1326 /*
1327  * Field : Use Pre-defined (Fixed) Timeout Values - cp_wdt_use_fix_top
1328  *
1329  * Specifies if the watchdog uses the pre-defined timeout values or if these were
1330  * overriden with customer values when the watchdog was configured.
1331  *
1332  * Field Enumeration Values:
1333  *
1334  * Enum | Value | Description
1335  * :------------------------------------------------------|:------|:----------------------------------------------
1336  * ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_E_PREDEFINED | 0x1 | Use pre-defined (fixed) timeout values (range
1337  * : | | from 2**16 to 2**31)
1338  *
1339  * Field Access Macros:
1340  *
1341  */
1342 /*
1343  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP
1344  *
1345  * Use pre-defined (fixed) timeout values (range from 2**16 to 2**31)
1346  */
1347 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_E_PREDEFINED 0x1
1348 
1349 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field. */
1350 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_LSB 6
1351 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field. */
1352 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_MSB 6
1353 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field. */
1354 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_WIDTH 1
1355 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field value. */
1356 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_SET_MSK 0x00000040
1357 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field value. */
1358 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_CLR_MSK 0xffffffbf
1359 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field. */
1360 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_RESET 0x1
1361 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP field value from a register. */
1362 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_GET(value) (((value) & 0x00000040) >> 6)
1363 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field value suitable for setting the register. */
1364 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_SET(value) (((value) << 6) & 0x00000040)
1365 
1366 /*
1367  * Field : Include Pause Input - cp_wdt_pause
1368  *
1369  * Should specify if the pause input is included or not. However, this field is
1370  * always hardwired to 0 so you can't figure this out by reading this field. The
1371  * pause input is included and can be used to pause the watchdog when the MPU is in
1372  * debug mode.
1373  *
1374  * Field Access Macros:
1375  *
1376  */
1377 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field. */
1378 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_LSB 7
1379 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field. */
1380 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_MSB 7
1381 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field. */
1382 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_WIDTH 1
1383 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field value. */
1384 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_SET_MSK 0x00000080
1385 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field value. */
1386 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_CLR_MSK 0xffffff7f
1387 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field. */
1388 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_RESET 0x0
1389 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE field value from a register. */
1390 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_GET(value) (((value) & 0x00000080) >> 7)
1391 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field value suitable for setting the register. */
1392 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_SET(value) (((value) << 7) & 0x00000080)
1393 
1394 /*
1395  * Field : APB Data Width - cp_wdt_apb_data_width
1396  *
1397  * APB Bus Width
1398  *
1399  * Field Enumeration Values:
1400  *
1401  * Enum | Value | Description
1402  * :----------------------------------------------------------|:------|:--------------------------
1403  * ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_E_WIDTH32BITS | 0x2 | APB Data Width is 32 Bits
1404  *
1405  * Field Access Macros:
1406  *
1407  */
1408 /*
1409  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH
1410  *
1411  * APB Data Width is 32 Bits
1412  */
1413 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_E_WIDTH32BITS 0x2
1414 
1415 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field. */
1416 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_LSB 8
1417 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field. */
1418 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_MSB 9
1419 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field. */
1420 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_WIDTH 2
1421 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field value. */
1422 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_SET_MSK 0x00000300
1423 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field value. */
1424 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_CLR_MSK 0xfffffcff
1425 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field. */
1426 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_RESET 0x2
1427 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH field value from a register. */
1428 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_GET(value) (((value) & 0x00000300) >> 8)
1429 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field value suitable for setting the register. */
1430 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_SET(value) (((value) << 8) & 0x00000300)
1431 
1432 /*
1433  * Field : Default Reset Pulse Length - cp_wdt_dflt_rpl
1434  *
1435  * Specifies the reset pulse length in cycles.
1436  *
1437  * Field Enumeration Values:
1438  *
1439  * Enum | Value | Description
1440  * :-----------------------------------------------------|:------|:--------------------------------
1441  * ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_E_PULSE2CYCLES | 0x0 | Reset pulse length of 2 cycles.
1442  *
1443  * Field Access Macros:
1444  *
1445  */
1446 /*
1447  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL
1448  *
1449  * Reset pulse length of 2 cycles.
1450  */
1451 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_E_PULSE2CYCLES 0x0
1452 
1453 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field. */
1454 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_LSB 10
1455 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field. */
1456 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_MSB 12
1457 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field. */
1458 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_WIDTH 3
1459 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field value. */
1460 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_SET_MSK 0x00001c00
1461 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field value. */
1462 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_CLR_MSK 0xffffe3ff
1463 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field. */
1464 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_RESET 0x0
1465 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL field value from a register. */
1466 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_GET(value) (((value) & 0x00001c00) >> 10)
1467 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field value suitable for setting the register. */
1468 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_SET(value) (((value) << 10) & 0x00001c00)
1469 
1470 /*
1471  * Field : Default Timeout Period - cp_wdt_dflt_top
1472  *
1473  * Specifies the timeout period that is available directly after reset.
1474  *
1475  * Field Enumeration Values:
1476  *
1477  * Enum | Value | Description
1478  * :----------------------------------------------|:------|:-------------------------------------
1479  * ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_E_TMO15 | 0xf | Timeout period is 15 (2**31 cycles).
1480  *
1481  * Field Access Macros:
1482  *
1483  */
1484 /*
1485  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP
1486  *
1487  * Timeout period is 15 (2**31 cycles).
1488  */
1489 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_E_TMO15 0xf
1490 
1491 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field. */
1492 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_LSB 16
1493 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field. */
1494 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_MSB 19
1495 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field. */
1496 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_WIDTH 4
1497 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field value. */
1498 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_SET_MSK 0x000f0000
1499 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field value. */
1500 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_CLR_MSK 0xfff0ffff
1501 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field. */
1502 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_RESET 0xf
1503 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP field value from a register. */
1504 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_GET(value) (((value) & 0x000f0000) >> 16)
1505 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field value suitable for setting the register. */
1506 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_SET(value) (((value) << 16) & 0x000f0000)
1507 
1508 /*
1509  * Field : Default Initial Timeout Period - cp_wdt_dflt_top_init
1510  *
1511  * Specifies the initial timeout period that is available directly after reset.
1512  *
1513  * Field Enumeration Values:
1514  *
1515  * Enum | Value | Description
1516  * :---------------------------------------------------|:------|:---------------------------------------------
1517  * ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_E_TMO15 | 0xf | Initial timeout period is 15 (2**31 cycles).
1518  *
1519  * Field Access Macros:
1520  *
1521  */
1522 /*
1523  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT
1524  *
1525  * Initial timeout period is 15 (2**31 cycles).
1526  */
1527 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_E_TMO15 0xf
1528 
1529 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field. */
1530 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_LSB 20
1531 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field. */
1532 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_MSB 23
1533 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field. */
1534 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_WIDTH 4
1535 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field value. */
1536 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_SET_MSK 0x00f00000
1537 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field value. */
1538 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_CLR_MSK 0xff0fffff
1539 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field. */
1540 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_RESET 0xf
1541 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT field value from a register. */
1542 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_GET(value) (((value) & 0x00f00000) >> 20)
1543 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field value suitable for setting the register. */
1544 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_SET(value) (((value) << 20) & 0x00f00000)
1545 
1546 /*
1547  * Field : Counter Width in Bits - cp_wdt_cnt_width
1548  *
1549  * Width of counter in bits less 16.
1550  *
1551  * Field Enumeration Values:
1552  *
1553  * Enum | Value | Description
1554  * :-----------------------------------------------------|:------|:-------------------------
1555  * ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_E_WIDTH32BITS | 0x10 | Counter width is 32 bits
1556  *
1557  * Field Access Macros:
1558  *
1559  */
1560 /*
1561  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH
1562  *
1563  * Counter width is 32 bits
1564  */
1565 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_E_WIDTH32BITS 0x10
1566 
1567 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field. */
1568 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_LSB 24
1569 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field. */
1570 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_MSB 28
1571 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field. */
1572 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_WIDTH 5
1573 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field value. */
1574 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_SET_MSK 0x1f000000
1575 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field value. */
1576 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_CLR_MSK 0xe0ffffff
1577 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field. */
1578 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_RESET 0x10
1579 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH field value from a register. */
1580 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_GET(value) (((value) & 0x1f000000) >> 24)
1581 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field value suitable for setting the register. */
1582 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_SET(value) (((value) << 24) & 0x1f000000)
1583 
1584 #ifndef __ASSEMBLY__
1585 /*
1586  * WARNING: The C register and register group struct declarations are provided for
1587  * convenience and illustrative purposes. They should, however, be used with
1588  * caution as the C language standard provides no guarantees about the alignment or
1589  * atomicity of device memory accesses. The recommended practice for writing
1590  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1591  * alt_write_word() functions.
1592  *
1593  * The struct declaration for register ALT_L4WD_COMP_PARAM_1.
1594  */
1595 struct ALT_L4WD_COMP_PARAM_1_s
1596 {
1597  const uint32_t cp_wdt_always_en : 1; /* Always Enable */
1598  const uint32_t cp_wdt_dflt_rmod : 1; /* Default Mode */
1599  const uint32_t cp_wdt_dual_top : 1; /* Dual Timeout Period */
1600  const uint32_t cp_wdt_hc_rmod : 1; /* Hardcode Response Mode */
1601  const uint32_t cp_wdt_hc_rpl : 1; /* Hardcode Reset Pulse Length */
1602  const uint32_t cp_wdt_hc_top : 1; /* Hardcode Timeout Period */
1603  const uint32_t cp_wdt_use_fix_top : 1; /* Use Pre-defined (Fixed) Timeout Values */
1604  const uint32_t cp_wdt_pause : 1; /* Include Pause Input */
1605  const uint32_t cp_wdt_apb_data_width : 2; /* APB Data Width */
1606  const uint32_t cp_wdt_dflt_rpl : 3; /* Default Reset Pulse Length */
1607  uint32_t : 3; /* *UNDEFINED* */
1608  const uint32_t cp_wdt_dflt_top : 4; /* Default Timeout Period */
1609  const uint32_t cp_wdt_dflt_top_init : 4; /* Default Initial Timeout Period */
1610  const uint32_t cp_wdt_cnt_width : 5; /* Counter Width in Bits */
1611  uint32_t : 3; /* *UNDEFINED* */
1612 };
1613 
1614 /* The typedef declaration for register ALT_L4WD_COMP_PARAM_1. */
1615 typedef volatile struct ALT_L4WD_COMP_PARAM_1_s ALT_L4WD_COMP_PARAM_1_t;
1616 #endif /* __ASSEMBLY__ */
1617 
1618 /* The byte offset of the ALT_L4WD_COMP_PARAM_1 register from the beginning of the component. */
1619 #define ALT_L4WD_COMP_PARAM_1_OFST 0xf4
1620 /* The address of the ALT_L4WD_COMP_PARAM_1 register. */
1621 #define ALT_L4WD_COMP_PARAM_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_COMP_PARAM_1_OFST))
1622 
1623 /*
1624  * Register : Component Version Register - wdt_comp_version
1625  *
1626  * Register Layout
1627  *
1628  * Bits | Access | Reset | Description
1629  * :-------|:-------|:-----------|:------------------
1630  * [31:0] | R | 0x3130362a | Component Version
1631  *
1632  */
1633 /*
1634  * Field : Component Version - wdt_comp_version
1635  *
1636  * ASCII value for each number in the version, followed by *. For example,
1637  * 32_30_31_2A represents the version 2.01*.
1638  *
1639  * Field Access Macros:
1640  *
1641  */
1642 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_VER_WDT_COMP_VER register field. */
1643 #define ALT_L4WD_COMP_VER_WDT_COMP_VER_LSB 0
1644 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_VER_WDT_COMP_VER register field. */
1645 #define ALT_L4WD_COMP_VER_WDT_COMP_VER_MSB 31
1646 /* The width in bits of the ALT_L4WD_COMP_VER_WDT_COMP_VER register field. */
1647 #define ALT_L4WD_COMP_VER_WDT_COMP_VER_WIDTH 32
1648 /* The mask used to set the ALT_L4WD_COMP_VER_WDT_COMP_VER register field value. */
1649 #define ALT_L4WD_COMP_VER_WDT_COMP_VER_SET_MSK 0xffffffff
1650 /* The mask used to clear the ALT_L4WD_COMP_VER_WDT_COMP_VER register field value. */
1651 #define ALT_L4WD_COMP_VER_WDT_COMP_VER_CLR_MSK 0x00000000
1652 /* The reset value of the ALT_L4WD_COMP_VER_WDT_COMP_VER register field. */
1653 #define ALT_L4WD_COMP_VER_WDT_COMP_VER_RESET 0x3130362a
1654 /* Extracts the ALT_L4WD_COMP_VER_WDT_COMP_VER field value from a register. */
1655 #define ALT_L4WD_COMP_VER_WDT_COMP_VER_GET(value) (((value) & 0xffffffff) >> 0)
1656 /* Produces a ALT_L4WD_COMP_VER_WDT_COMP_VER register field value suitable for setting the register. */
1657 #define ALT_L4WD_COMP_VER_WDT_COMP_VER_SET(value) (((value) << 0) & 0xffffffff)
1658 
1659 #ifndef __ASSEMBLY__
1660 /*
1661  * WARNING: The C register and register group struct declarations are provided for
1662  * convenience and illustrative purposes. They should, however, be used with
1663  * caution as the C language standard provides no guarantees about the alignment or
1664  * atomicity of device memory accesses. The recommended practice for writing
1665  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1666  * alt_write_word() functions.
1667  *
1668  * The struct declaration for register ALT_L4WD_COMP_VER.
1669  */
1670 struct ALT_L4WD_COMP_VER_s
1671 {
1672  const uint32_t wdt_comp_version : 32; /* Component Version */
1673 };
1674 
1675 /* The typedef declaration for register ALT_L4WD_COMP_VER. */
1676 typedef volatile struct ALT_L4WD_COMP_VER_s ALT_L4WD_COMP_VER_t;
1677 #endif /* __ASSEMBLY__ */
1678 
1679 /* The byte offset of the ALT_L4WD_COMP_VER register from the beginning of the component. */
1680 #define ALT_L4WD_COMP_VER_OFST 0xf8
1681 /* The address of the ALT_L4WD_COMP_VER register. */
1682 #define ALT_L4WD_COMP_VER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_COMP_VER_OFST))
1683 
1684 /*
1685  * Register : Component Type Register - wdt_comp_type
1686  *
1687  * Register Layout
1688  *
1689  * Bits | Access | Reset | Description
1690  * :-------|:-------|:-----------|:---------------
1691  * [31:0] | R | 0x44570120 | Component Type
1692  *
1693  */
1694 /*
1695  * Field : Component Type - wdt_comp_type
1696  *
1697  * Designware Component Type number = 0x44_57_01_20.
1698  *
1699  * Field Access Macros:
1700  *
1701  */
1702 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE register field. */
1703 #define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_LSB 0
1704 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE register field. */
1705 #define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_MSB 31
1706 /* The width in bits of the ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE register field. */
1707 #define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_WIDTH 32
1708 /* The mask used to set the ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE register field value. */
1709 #define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_SET_MSK 0xffffffff
1710 /* The mask used to clear the ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE register field value. */
1711 #define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_CLR_MSK 0x00000000
1712 /* The reset value of the ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE register field. */
1713 #define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_RESET 0x44570120
1714 /* Extracts the ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE field value from a register. */
1715 #define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_GET(value) (((value) & 0xffffffff) >> 0)
1716 /* Produces a ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE register field value suitable for setting the register. */
1717 #define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_SET(value) (((value) << 0) & 0xffffffff)
1718 
1719 #ifndef __ASSEMBLY__
1720 /*
1721  * WARNING: The C register and register group struct declarations are provided for
1722  * convenience and illustrative purposes. They should, however, be used with
1723  * caution as the C language standard provides no guarantees about the alignment or
1724  * atomicity of device memory accesses. The recommended practice for writing
1725  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1726  * alt_write_word() functions.
1727  *
1728  * The struct declaration for register ALT_L4WD_COMP_TYPE.
1729  */
1730 struct ALT_L4WD_COMP_TYPE_s
1731 {
1732  const uint32_t wdt_comp_type : 32; /* Component Type */
1733 };
1734 
1735 /* The typedef declaration for register ALT_L4WD_COMP_TYPE. */
1736 typedef volatile struct ALT_L4WD_COMP_TYPE_s ALT_L4WD_COMP_TYPE_t;
1737 #endif /* __ASSEMBLY__ */
1738 
1739 /* The byte offset of the ALT_L4WD_COMP_TYPE register from the beginning of the component. */
1740 #define ALT_L4WD_COMP_TYPE_OFST 0xfc
1741 /* The address of the ALT_L4WD_COMP_TYPE register. */
1742 #define ALT_L4WD_COMP_TYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_COMP_TYPE_OFST))
1743 
1744 #ifndef __ASSEMBLY__
1745 /*
1746  * WARNING: The C register and register group struct declarations are provided for
1747  * convenience and illustrative purposes. They should, however, be used with
1748  * caution as the C language standard provides no guarantees about the alignment or
1749  * atomicity of device memory accesses. The recommended practice for writing
1750  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1751  * alt_write_word() functions.
1752  *
1753  * The struct declaration for register group ALT_L4WD.
1754  */
1755 struct ALT_L4WD_s
1756 {
1757  ALT_L4WD_CR_t wdt_cr; /* ALT_L4WD_CR */
1758  ALT_L4WD_TORR_t wdt_torr; /* ALT_L4WD_TORR */
1759  ALT_L4WD_CCVR_t wdt_ccvr; /* ALT_L4WD_CCVR */
1760  ALT_L4WD_CRR_t wdt_crr; /* ALT_L4WD_CRR */
1761  ALT_L4WD_STAT_t wdt_stat; /* ALT_L4WD_STAT */
1762  ALT_L4WD_EOI_t wdt_eoi; /* ALT_L4WD_EOI */
1763  volatile uint32_t _pad_0x18_0xe3[51]; /* *UNDEFINED* */
1764  ALT_L4WD_CP_WDT_USER_TOP_MAX_t cp_wdt_user_top_max; /* ALT_L4WD_CP_WDT_USER_TOP_MAX */
1765  ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_t cp_wdt_user_top_init_max; /* ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX */
1766  ALT_L4WD_CD_WDT_TOP_RST_t cd_wdt_top_rst; /* ALT_L4WD_CD_WDT_TOP_RST */
1767  ALT_L4WD_CP_WDT_CNT_RST_t cp_wdt_cnt_rst; /* ALT_L4WD_CP_WDT_CNT_RST */
1768  ALT_L4WD_COMP_PARAM_1_t wdt_comp_param_1; /* ALT_L4WD_COMP_PARAM_1 */
1769  ALT_L4WD_COMP_VER_t wdt_comp_version; /* ALT_L4WD_COMP_VER */
1770  ALT_L4WD_COMP_TYPE_t wdt_comp_type; /* ALT_L4WD_COMP_TYPE */
1771 };
1772 
1773 /* The typedef declaration for register group ALT_L4WD. */
1774 typedef volatile struct ALT_L4WD_s ALT_L4WD_t;
1775 /* The struct declaration for the raw register contents of register group ALT_L4WD. */
1776 struct ALT_L4WD_raw_s
1777 {
1778  volatile uint32_t wdt_cr; /* ALT_L4WD_CR */
1779  volatile uint32_t wdt_torr; /* ALT_L4WD_TORR */
1780  volatile uint32_t wdt_ccvr; /* ALT_L4WD_CCVR */
1781  volatile uint32_t wdt_crr; /* ALT_L4WD_CRR */
1782  volatile uint32_t wdt_stat; /* ALT_L4WD_STAT */
1783  volatile uint32_t wdt_eoi; /* ALT_L4WD_EOI */
1784  uint32_t _pad_0x18_0xe3[51]; /* *UNDEFINED* */
1785  volatile uint32_t cp_wdt_user_top_max; /* ALT_L4WD_CP_WDT_USER_TOP_MAX */
1786  volatile uint32_t cp_wdt_user_top_init_max; /* ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX */
1787  volatile uint32_t cd_wdt_top_rst; /* ALT_L4WD_CD_WDT_TOP_RST */
1788  volatile uint32_t cp_wdt_cnt_rst; /* ALT_L4WD_CP_WDT_CNT_RST */
1789  volatile uint32_t wdt_comp_param_1; /* ALT_L4WD_COMP_PARAM_1 */
1790  volatile uint32_t wdt_comp_version; /* ALT_L4WD_COMP_VER */
1791  volatile uint32_t wdt_comp_type; /* ALT_L4WD_COMP_TYPE */
1792 };
1793 
1794 /* The typedef declaration for the raw register contents of register group ALT_L4WD. */
1795 typedef volatile struct ALT_L4WD_raw_s ALT_L4WD_raw_t;
1796 #endif /* __ASSEMBLY__ */
1797 
1798 
1799 #ifdef __cplusplus
1800 }
1801 #endif /* __cplusplus */
1802 #endif /* __ALTERA_ALT_L4WD_H__ */
1803