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alt_gic.h
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32 
33 /* Altera - ALT_GIC_DIST */
34 
35 #ifndef __ALT_SOCAL_GIC_H__
36 #define __ALT_SOCAL_GIC_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : Distributor memory map - GIC_DIST
50  * Distributor memory map
51  *
52  * Memory map for the GIC Distributor block. Contains all registers with the GICD
53  * prefix. Note: Some registers are security-banked or banked per-CPU.
54  *
55  */
56 /*
57  * Register : GICD_CTLR
58  *
59  * Distributor Control Register
60  *
61  * Register Layout
62  *
63  * Bits | Access | Reset | Description
64  * :-------|:-------|:------|:------------
65  * [31:0] | RW | 0x0 | Empty
66  *
67  */
68 /*
69  * Field : Empty - fld
70  *
71  * Placeholder
72  *
73  * Field Access Macros:
74  *
75  */
76 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_CTLR_FLD register field. */
77 #define ALT_GIC_DIST_GICD_CTLR_FLD_LSB 0
78 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_CTLR_FLD register field. */
79 #define ALT_GIC_DIST_GICD_CTLR_FLD_MSB 31
80 /* The width in bits of the ALT_GIC_DIST_GICD_CTLR_FLD register field. */
81 #define ALT_GIC_DIST_GICD_CTLR_FLD_WIDTH 32
82 /* The mask used to set the ALT_GIC_DIST_GICD_CTLR_FLD register field value. */
83 #define ALT_GIC_DIST_GICD_CTLR_FLD_SET_MSK 0xffffffff
84 /* The mask used to clear the ALT_GIC_DIST_GICD_CTLR_FLD register field value. */
85 #define ALT_GIC_DIST_GICD_CTLR_FLD_CLR_MSK 0x00000000
86 /* The reset value of the ALT_GIC_DIST_GICD_CTLR_FLD register field. */
87 #define ALT_GIC_DIST_GICD_CTLR_FLD_RESET 0x0
88 /* Extracts the ALT_GIC_DIST_GICD_CTLR_FLD field value from a register. */
89 #define ALT_GIC_DIST_GICD_CTLR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
90 /* Produces a ALT_GIC_DIST_GICD_CTLR_FLD register field value suitable for setting the register. */
91 #define ALT_GIC_DIST_GICD_CTLR_FLD_SET(value) (((value) << 0) & 0xffffffff)
92 
93 #ifndef __ASSEMBLY__
94 /*
95  * WARNING: The C register and register group struct declarations are provided for
96  * convenience and illustrative purposes. They should, however, be used with
97  * caution as the C language standard provides no guarantees about the alignment or
98  * atomicity of device memory accesses. The recommended practice for coding device
99  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
100  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
101  * alt_write_dword() functions for 64 bit registers.
102  *
103  * The struct declaration for register ALT_GIC_DIST_GICD_CTLR.
104  */
105 struct ALT_GIC_DIST_GICD_CTLR_s
106 {
107  volatile uint32_t fld : 32; /* Empty */
108 };
109 
110 /* The typedef declaration for register ALT_GIC_DIST_GICD_CTLR. */
111 typedef struct ALT_GIC_DIST_GICD_CTLR_s ALT_GIC_DIST_GICD_CTLR_t;
112 #endif /* __ASSEMBLY__ */
113 
114 /* The reset value of the ALT_GIC_DIST_GICD_CTLR register. */
115 #define ALT_GIC_DIST_GICD_CTLR_RESET 0x00000000
116 /* The byte offset of the ALT_GIC_DIST_GICD_CTLR register from the beginning of the component. */
117 #define ALT_GIC_DIST_GICD_CTLR_OFST 0x0
118 
119 /*
120  * Register : GICD_TYPER
121  *
122  * Interrupt Controller Type Register
123  *
124  * Register Layout
125  *
126  * Bits | Access | Reset | Description
127  * :-------|:-------|:--------|:------------
128  * [31:0] | RW | Unknown | Empty
129  *
130  */
131 /*
132  * Field : Empty - fld
133  *
134  * Placeholder
135  *
136  * Field Access Macros:
137  *
138  */
139 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_TYPER_FLD register field. */
140 #define ALT_GIC_DIST_GICD_TYPER_FLD_LSB 0
141 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_TYPER_FLD register field. */
142 #define ALT_GIC_DIST_GICD_TYPER_FLD_MSB 31
143 /* The width in bits of the ALT_GIC_DIST_GICD_TYPER_FLD register field. */
144 #define ALT_GIC_DIST_GICD_TYPER_FLD_WIDTH 32
145 /* The mask used to set the ALT_GIC_DIST_GICD_TYPER_FLD register field value. */
146 #define ALT_GIC_DIST_GICD_TYPER_FLD_SET_MSK 0xffffffff
147 /* The mask used to clear the ALT_GIC_DIST_GICD_TYPER_FLD register field value. */
148 #define ALT_GIC_DIST_GICD_TYPER_FLD_CLR_MSK 0x00000000
149 /* The reset value of the ALT_GIC_DIST_GICD_TYPER_FLD register field is UNKNOWN. */
150 #define ALT_GIC_DIST_GICD_TYPER_FLD_RESET 0x0
151 /* Extracts the ALT_GIC_DIST_GICD_TYPER_FLD field value from a register. */
152 #define ALT_GIC_DIST_GICD_TYPER_FLD_GET(value) (((value) & 0xffffffff) >> 0)
153 /* Produces a ALT_GIC_DIST_GICD_TYPER_FLD register field value suitable for setting the register. */
154 #define ALT_GIC_DIST_GICD_TYPER_FLD_SET(value) (((value) << 0) & 0xffffffff)
155 
156 #ifndef __ASSEMBLY__
157 /*
158  * WARNING: The C register and register group struct declarations are provided for
159  * convenience and illustrative purposes. They should, however, be used with
160  * caution as the C language standard provides no guarantees about the alignment or
161  * atomicity of device memory accesses. The recommended practice for coding device
162  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
163  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
164  * alt_write_dword() functions for 64 bit registers.
165  *
166  * The struct declaration for register ALT_GIC_DIST_GICD_TYPER.
167  */
168 struct ALT_GIC_DIST_GICD_TYPER_s
169 {
170  volatile uint32_t fld : 32; /* Empty */
171 };
172 
173 /* The typedef declaration for register ALT_GIC_DIST_GICD_TYPER. */
174 typedef struct ALT_GIC_DIST_GICD_TYPER_s ALT_GIC_DIST_GICD_TYPER_t;
175 #endif /* __ASSEMBLY__ */
176 
177 /* The reset value of the ALT_GIC_DIST_GICD_TYPER register. */
178 #define ALT_GIC_DIST_GICD_TYPER_RESET 0x00000000
179 /* The byte offset of the ALT_GIC_DIST_GICD_TYPER register from the beginning of the component. */
180 #define ALT_GIC_DIST_GICD_TYPER_OFST 0x4
181 
182 /*
183  * Register : GICD_IIDR
184  *
185  * Distributor Implementer Identification Register
186  *
187  * Register Layout
188  *
189  * Bits | Access | Reset | Description
190  * :-------|:-------|:----------|:------------
191  * [31:0] | RW | 0x200143b | Empty
192  *
193  */
194 /*
195  * Field : Empty - fld
196  *
197  * Placeholder
198  *
199  * Field Access Macros:
200  *
201  */
202 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IIDR_FLD register field. */
203 #define ALT_GIC_DIST_GICD_IIDR_FLD_LSB 0
204 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IIDR_FLD register field. */
205 #define ALT_GIC_DIST_GICD_IIDR_FLD_MSB 31
206 /* The width in bits of the ALT_GIC_DIST_GICD_IIDR_FLD register field. */
207 #define ALT_GIC_DIST_GICD_IIDR_FLD_WIDTH 32
208 /* The mask used to set the ALT_GIC_DIST_GICD_IIDR_FLD register field value. */
209 #define ALT_GIC_DIST_GICD_IIDR_FLD_SET_MSK 0xffffffff
210 /* The mask used to clear the ALT_GIC_DIST_GICD_IIDR_FLD register field value. */
211 #define ALT_GIC_DIST_GICD_IIDR_FLD_CLR_MSK 0x00000000
212 /* The reset value of the ALT_GIC_DIST_GICD_IIDR_FLD register field. */
213 #define ALT_GIC_DIST_GICD_IIDR_FLD_RESET 0x200143b
214 /* Extracts the ALT_GIC_DIST_GICD_IIDR_FLD field value from a register. */
215 #define ALT_GIC_DIST_GICD_IIDR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
216 /* Produces a ALT_GIC_DIST_GICD_IIDR_FLD register field value suitable for setting the register. */
217 #define ALT_GIC_DIST_GICD_IIDR_FLD_SET(value) (((value) << 0) & 0xffffffff)
218 
219 #ifndef __ASSEMBLY__
220 /*
221  * WARNING: The C register and register group struct declarations are provided for
222  * convenience and illustrative purposes. They should, however, be used with
223  * caution as the C language standard provides no guarantees about the alignment or
224  * atomicity of device memory accesses. The recommended practice for coding device
225  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
226  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
227  * alt_write_dword() functions for 64 bit registers.
228  *
229  * The struct declaration for register ALT_GIC_DIST_GICD_IIDR.
230  */
231 struct ALT_GIC_DIST_GICD_IIDR_s
232 {
233  volatile uint32_t fld : 32; /* Empty */
234 };
235 
236 /* The typedef declaration for register ALT_GIC_DIST_GICD_IIDR. */
237 typedef struct ALT_GIC_DIST_GICD_IIDR_s ALT_GIC_DIST_GICD_IIDR_t;
238 #endif /* __ASSEMBLY__ */
239 
240 /* The reset value of the ALT_GIC_DIST_GICD_IIDR register. */
241 #define ALT_GIC_DIST_GICD_IIDR_RESET 0x0200143b
242 /* The byte offset of the ALT_GIC_DIST_GICD_IIDR register from the beginning of the component. */
243 #define ALT_GIC_DIST_GICD_IIDR_OFST 0x8
244 
245 /*
246  * Register : GICD_IGROUPR0
247  *
248  * Interrupt Group Registers
249  *
250  * Register Layout
251  *
252  * Bits | Access | Reset | Description
253  * :-------|:-------|:------|:------------
254  * [31:0] | RW | 0x0 | Empty
255  *
256  */
257 /*
258  * Field : Empty - fld
259  *
260  * Placeholder
261  *
262  * Field Access Macros:
263  *
264  */
265 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IGROUPR0_FLD register field. */
266 #define ALT_GIC_DIST_GICD_IGROUPR0_FLD_LSB 0
267 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IGROUPR0_FLD register field. */
268 #define ALT_GIC_DIST_GICD_IGROUPR0_FLD_MSB 31
269 /* The width in bits of the ALT_GIC_DIST_GICD_IGROUPR0_FLD register field. */
270 #define ALT_GIC_DIST_GICD_IGROUPR0_FLD_WIDTH 32
271 /* The mask used to set the ALT_GIC_DIST_GICD_IGROUPR0_FLD register field value. */
272 #define ALT_GIC_DIST_GICD_IGROUPR0_FLD_SET_MSK 0xffffffff
273 /* The mask used to clear the ALT_GIC_DIST_GICD_IGROUPR0_FLD register field value. */
274 #define ALT_GIC_DIST_GICD_IGROUPR0_FLD_CLR_MSK 0x00000000
275 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR0_FLD register field. */
276 #define ALT_GIC_DIST_GICD_IGROUPR0_FLD_RESET 0x0
277 /* Extracts the ALT_GIC_DIST_GICD_IGROUPR0_FLD field value from a register. */
278 #define ALT_GIC_DIST_GICD_IGROUPR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
279 /* Produces a ALT_GIC_DIST_GICD_IGROUPR0_FLD register field value suitable for setting the register. */
280 #define ALT_GIC_DIST_GICD_IGROUPR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
281 
282 #ifndef __ASSEMBLY__
283 /*
284  * WARNING: The C register and register group struct declarations are provided for
285  * convenience and illustrative purposes. They should, however, be used with
286  * caution as the C language standard provides no guarantees about the alignment or
287  * atomicity of device memory accesses. The recommended practice for coding device
288  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
289  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
290  * alt_write_dword() functions for 64 bit registers.
291  *
292  * The struct declaration for register ALT_GIC_DIST_GICD_IGROUPR0.
293  */
294 struct ALT_GIC_DIST_GICD_IGROUPR0_s
295 {
296  volatile uint32_t fld : 32; /* Empty */
297 };
298 
299 /* The typedef declaration for register ALT_GIC_DIST_GICD_IGROUPR0. */
300 typedef struct ALT_GIC_DIST_GICD_IGROUPR0_s ALT_GIC_DIST_GICD_IGROUPR0_t;
301 #endif /* __ASSEMBLY__ */
302 
303 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR0 register. */
304 #define ALT_GIC_DIST_GICD_IGROUPR0_RESET 0x00000000
305 /* The byte offset of the ALT_GIC_DIST_GICD_IGROUPR0 register from the beginning of the component. */
306 #define ALT_GIC_DIST_GICD_IGROUPR0_OFST 0x80
307 
308 /*
309  * Register : GICD_IGROUPR1
310  *
311  * Interrupt Group Registers
312  *
313  * Register Layout
314  *
315  * Bits | Access | Reset | Description
316  * :-------|:-------|:------|:------------
317  * [31:0] | RW | 0x0 | Empty
318  *
319  */
320 /*
321  * Field : Empty - fld
322  *
323  * Placeholder
324  *
325  * Field Access Macros:
326  *
327  */
328 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IGROUPR1_FLD register field. */
329 #define ALT_GIC_DIST_GICD_IGROUPR1_FLD_LSB 0
330 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IGROUPR1_FLD register field. */
331 #define ALT_GIC_DIST_GICD_IGROUPR1_FLD_MSB 31
332 /* The width in bits of the ALT_GIC_DIST_GICD_IGROUPR1_FLD register field. */
333 #define ALT_GIC_DIST_GICD_IGROUPR1_FLD_WIDTH 32
334 /* The mask used to set the ALT_GIC_DIST_GICD_IGROUPR1_FLD register field value. */
335 #define ALT_GIC_DIST_GICD_IGROUPR1_FLD_SET_MSK 0xffffffff
336 /* The mask used to clear the ALT_GIC_DIST_GICD_IGROUPR1_FLD register field value. */
337 #define ALT_GIC_DIST_GICD_IGROUPR1_FLD_CLR_MSK 0x00000000
338 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR1_FLD register field. */
339 #define ALT_GIC_DIST_GICD_IGROUPR1_FLD_RESET 0x0
340 /* Extracts the ALT_GIC_DIST_GICD_IGROUPR1_FLD field value from a register. */
341 #define ALT_GIC_DIST_GICD_IGROUPR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
342 /* Produces a ALT_GIC_DIST_GICD_IGROUPR1_FLD register field value suitable for setting the register. */
343 #define ALT_GIC_DIST_GICD_IGROUPR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
344 
345 #ifndef __ASSEMBLY__
346 /*
347  * WARNING: The C register and register group struct declarations are provided for
348  * convenience and illustrative purposes. They should, however, be used with
349  * caution as the C language standard provides no guarantees about the alignment or
350  * atomicity of device memory accesses. The recommended practice for coding device
351  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
352  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
353  * alt_write_dword() functions for 64 bit registers.
354  *
355  * The struct declaration for register ALT_GIC_DIST_GICD_IGROUPR1.
356  */
357 struct ALT_GIC_DIST_GICD_IGROUPR1_s
358 {
359  volatile uint32_t fld : 32; /* Empty */
360 };
361 
362 /* The typedef declaration for register ALT_GIC_DIST_GICD_IGROUPR1. */
363 typedef struct ALT_GIC_DIST_GICD_IGROUPR1_s ALT_GIC_DIST_GICD_IGROUPR1_t;
364 #endif /* __ASSEMBLY__ */
365 
366 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR1 register. */
367 #define ALT_GIC_DIST_GICD_IGROUPR1_RESET 0x00000000
368 /* The byte offset of the ALT_GIC_DIST_GICD_IGROUPR1 register from the beginning of the component. */
369 #define ALT_GIC_DIST_GICD_IGROUPR1_OFST 0x84
370 
371 /*
372  * Register : GICD_IGROUPR2
373  *
374  * Interrupt Group Registers
375  *
376  * Register Layout
377  *
378  * Bits | Access | Reset | Description
379  * :-------|:-------|:------|:------------
380  * [31:0] | RW | 0x0 | Empty
381  *
382  */
383 /*
384  * Field : Empty - fld
385  *
386  * Placeholder
387  *
388  * Field Access Macros:
389  *
390  */
391 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IGROUPR2_FLD register field. */
392 #define ALT_GIC_DIST_GICD_IGROUPR2_FLD_LSB 0
393 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IGROUPR2_FLD register field. */
394 #define ALT_GIC_DIST_GICD_IGROUPR2_FLD_MSB 31
395 /* The width in bits of the ALT_GIC_DIST_GICD_IGROUPR2_FLD register field. */
396 #define ALT_GIC_DIST_GICD_IGROUPR2_FLD_WIDTH 32
397 /* The mask used to set the ALT_GIC_DIST_GICD_IGROUPR2_FLD register field value. */
398 #define ALT_GIC_DIST_GICD_IGROUPR2_FLD_SET_MSK 0xffffffff
399 /* The mask used to clear the ALT_GIC_DIST_GICD_IGROUPR2_FLD register field value. */
400 #define ALT_GIC_DIST_GICD_IGROUPR2_FLD_CLR_MSK 0x00000000
401 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR2_FLD register field. */
402 #define ALT_GIC_DIST_GICD_IGROUPR2_FLD_RESET 0x0
403 /* Extracts the ALT_GIC_DIST_GICD_IGROUPR2_FLD field value from a register. */
404 #define ALT_GIC_DIST_GICD_IGROUPR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
405 /* Produces a ALT_GIC_DIST_GICD_IGROUPR2_FLD register field value suitable for setting the register. */
406 #define ALT_GIC_DIST_GICD_IGROUPR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
407 
408 #ifndef __ASSEMBLY__
409 /*
410  * WARNING: The C register and register group struct declarations are provided for
411  * convenience and illustrative purposes. They should, however, be used with
412  * caution as the C language standard provides no guarantees about the alignment or
413  * atomicity of device memory accesses. The recommended practice for coding device
414  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
415  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
416  * alt_write_dword() functions for 64 bit registers.
417  *
418  * The struct declaration for register ALT_GIC_DIST_GICD_IGROUPR2.
419  */
420 struct ALT_GIC_DIST_GICD_IGROUPR2_s
421 {
422  volatile uint32_t fld : 32; /* Empty */
423 };
424 
425 /* The typedef declaration for register ALT_GIC_DIST_GICD_IGROUPR2. */
426 typedef struct ALT_GIC_DIST_GICD_IGROUPR2_s ALT_GIC_DIST_GICD_IGROUPR2_t;
427 #endif /* __ASSEMBLY__ */
428 
429 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR2 register. */
430 #define ALT_GIC_DIST_GICD_IGROUPR2_RESET 0x00000000
431 /* The byte offset of the ALT_GIC_DIST_GICD_IGROUPR2 register from the beginning of the component. */
432 #define ALT_GIC_DIST_GICD_IGROUPR2_OFST 0x88
433 
434 /*
435  * Register : GICD_IGROUPR3
436  *
437  * Interrupt Group Registers
438  *
439  * Register Layout
440  *
441  * Bits | Access | Reset | Description
442  * :-------|:-------|:------|:------------
443  * [31:0] | RW | 0x0 | Empty
444  *
445  */
446 /*
447  * Field : Empty - fld
448  *
449  * Placeholder
450  *
451  * Field Access Macros:
452  *
453  */
454 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IGROUPR3_FLD register field. */
455 #define ALT_GIC_DIST_GICD_IGROUPR3_FLD_LSB 0
456 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IGROUPR3_FLD register field. */
457 #define ALT_GIC_DIST_GICD_IGROUPR3_FLD_MSB 31
458 /* The width in bits of the ALT_GIC_DIST_GICD_IGROUPR3_FLD register field. */
459 #define ALT_GIC_DIST_GICD_IGROUPR3_FLD_WIDTH 32
460 /* The mask used to set the ALT_GIC_DIST_GICD_IGROUPR3_FLD register field value. */
461 #define ALT_GIC_DIST_GICD_IGROUPR3_FLD_SET_MSK 0xffffffff
462 /* The mask used to clear the ALT_GIC_DIST_GICD_IGROUPR3_FLD register field value. */
463 #define ALT_GIC_DIST_GICD_IGROUPR3_FLD_CLR_MSK 0x00000000
464 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR3_FLD register field. */
465 #define ALT_GIC_DIST_GICD_IGROUPR3_FLD_RESET 0x0
466 /* Extracts the ALT_GIC_DIST_GICD_IGROUPR3_FLD field value from a register. */
467 #define ALT_GIC_DIST_GICD_IGROUPR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
468 /* Produces a ALT_GIC_DIST_GICD_IGROUPR3_FLD register field value suitable for setting the register. */
469 #define ALT_GIC_DIST_GICD_IGROUPR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
470 
471 #ifndef __ASSEMBLY__
472 /*
473  * WARNING: The C register and register group struct declarations are provided for
474  * convenience and illustrative purposes. They should, however, be used with
475  * caution as the C language standard provides no guarantees about the alignment or
476  * atomicity of device memory accesses. The recommended practice for coding device
477  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
478  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
479  * alt_write_dword() functions for 64 bit registers.
480  *
481  * The struct declaration for register ALT_GIC_DIST_GICD_IGROUPR3.
482  */
483 struct ALT_GIC_DIST_GICD_IGROUPR3_s
484 {
485  volatile uint32_t fld : 32; /* Empty */
486 };
487 
488 /* The typedef declaration for register ALT_GIC_DIST_GICD_IGROUPR3. */
489 typedef struct ALT_GIC_DIST_GICD_IGROUPR3_s ALT_GIC_DIST_GICD_IGROUPR3_t;
490 #endif /* __ASSEMBLY__ */
491 
492 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR3 register. */
493 #define ALT_GIC_DIST_GICD_IGROUPR3_RESET 0x00000000
494 /* The byte offset of the ALT_GIC_DIST_GICD_IGROUPR3 register from the beginning of the component. */
495 #define ALT_GIC_DIST_GICD_IGROUPR3_OFST 0x8c
496 
497 /*
498  * Register : GICD_IGROUPR4
499  *
500  * Interrupt Group Registers
501  *
502  * Register Layout
503  *
504  * Bits | Access | Reset | Description
505  * :-------|:-------|:------|:------------
506  * [31:0] | RW | 0x0 | Empty
507  *
508  */
509 /*
510  * Field : Empty - fld
511  *
512  * Placeholder
513  *
514  * Field Access Macros:
515  *
516  */
517 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IGROUPR4_FLD register field. */
518 #define ALT_GIC_DIST_GICD_IGROUPR4_FLD_LSB 0
519 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IGROUPR4_FLD register field. */
520 #define ALT_GIC_DIST_GICD_IGROUPR4_FLD_MSB 31
521 /* The width in bits of the ALT_GIC_DIST_GICD_IGROUPR4_FLD register field. */
522 #define ALT_GIC_DIST_GICD_IGROUPR4_FLD_WIDTH 32
523 /* The mask used to set the ALT_GIC_DIST_GICD_IGROUPR4_FLD register field value. */
524 #define ALT_GIC_DIST_GICD_IGROUPR4_FLD_SET_MSK 0xffffffff
525 /* The mask used to clear the ALT_GIC_DIST_GICD_IGROUPR4_FLD register field value. */
526 #define ALT_GIC_DIST_GICD_IGROUPR4_FLD_CLR_MSK 0x00000000
527 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR4_FLD register field. */
528 #define ALT_GIC_DIST_GICD_IGROUPR4_FLD_RESET 0x0
529 /* Extracts the ALT_GIC_DIST_GICD_IGROUPR4_FLD field value from a register. */
530 #define ALT_GIC_DIST_GICD_IGROUPR4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
531 /* Produces a ALT_GIC_DIST_GICD_IGROUPR4_FLD register field value suitable for setting the register. */
532 #define ALT_GIC_DIST_GICD_IGROUPR4_FLD_SET(value) (((value) << 0) & 0xffffffff)
533 
534 #ifndef __ASSEMBLY__
535 /*
536  * WARNING: The C register and register group struct declarations are provided for
537  * convenience and illustrative purposes. They should, however, be used with
538  * caution as the C language standard provides no guarantees about the alignment or
539  * atomicity of device memory accesses. The recommended practice for coding device
540  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
541  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
542  * alt_write_dword() functions for 64 bit registers.
543  *
544  * The struct declaration for register ALT_GIC_DIST_GICD_IGROUPR4.
545  */
546 struct ALT_GIC_DIST_GICD_IGROUPR4_s
547 {
548  volatile uint32_t fld : 32; /* Empty */
549 };
550 
551 /* The typedef declaration for register ALT_GIC_DIST_GICD_IGROUPR4. */
552 typedef struct ALT_GIC_DIST_GICD_IGROUPR4_s ALT_GIC_DIST_GICD_IGROUPR4_t;
553 #endif /* __ASSEMBLY__ */
554 
555 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR4 register. */
556 #define ALT_GIC_DIST_GICD_IGROUPR4_RESET 0x00000000
557 /* The byte offset of the ALT_GIC_DIST_GICD_IGROUPR4 register from the beginning of the component. */
558 #define ALT_GIC_DIST_GICD_IGROUPR4_OFST 0x90
559 
560 /*
561  * Register : GICD_IGROUPR5
562  *
563  * Interrupt Group Registers
564  *
565  * Register Layout
566  *
567  * Bits | Access | Reset | Description
568  * :-------|:-------|:------|:------------
569  * [31:0] | RW | 0x0 | Empty
570  *
571  */
572 /*
573  * Field : Empty - fld
574  *
575  * Placeholder
576  *
577  * Field Access Macros:
578  *
579  */
580 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IGROUPR5_FLD register field. */
581 #define ALT_GIC_DIST_GICD_IGROUPR5_FLD_LSB 0
582 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IGROUPR5_FLD register field. */
583 #define ALT_GIC_DIST_GICD_IGROUPR5_FLD_MSB 31
584 /* The width in bits of the ALT_GIC_DIST_GICD_IGROUPR5_FLD register field. */
585 #define ALT_GIC_DIST_GICD_IGROUPR5_FLD_WIDTH 32
586 /* The mask used to set the ALT_GIC_DIST_GICD_IGROUPR5_FLD register field value. */
587 #define ALT_GIC_DIST_GICD_IGROUPR5_FLD_SET_MSK 0xffffffff
588 /* The mask used to clear the ALT_GIC_DIST_GICD_IGROUPR5_FLD register field value. */
589 #define ALT_GIC_DIST_GICD_IGROUPR5_FLD_CLR_MSK 0x00000000
590 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR5_FLD register field. */
591 #define ALT_GIC_DIST_GICD_IGROUPR5_FLD_RESET 0x0
592 /* Extracts the ALT_GIC_DIST_GICD_IGROUPR5_FLD field value from a register. */
593 #define ALT_GIC_DIST_GICD_IGROUPR5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
594 /* Produces a ALT_GIC_DIST_GICD_IGROUPR5_FLD register field value suitable for setting the register. */
595 #define ALT_GIC_DIST_GICD_IGROUPR5_FLD_SET(value) (((value) << 0) & 0xffffffff)
596 
597 #ifndef __ASSEMBLY__
598 /*
599  * WARNING: The C register and register group struct declarations are provided for
600  * convenience and illustrative purposes. They should, however, be used with
601  * caution as the C language standard provides no guarantees about the alignment or
602  * atomicity of device memory accesses. The recommended practice for coding device
603  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
604  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
605  * alt_write_dword() functions for 64 bit registers.
606  *
607  * The struct declaration for register ALT_GIC_DIST_GICD_IGROUPR5.
608  */
609 struct ALT_GIC_DIST_GICD_IGROUPR5_s
610 {
611  volatile uint32_t fld : 32; /* Empty */
612 };
613 
614 /* The typedef declaration for register ALT_GIC_DIST_GICD_IGROUPR5. */
615 typedef struct ALT_GIC_DIST_GICD_IGROUPR5_s ALT_GIC_DIST_GICD_IGROUPR5_t;
616 #endif /* __ASSEMBLY__ */
617 
618 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR5 register. */
619 #define ALT_GIC_DIST_GICD_IGROUPR5_RESET 0x00000000
620 /* The byte offset of the ALT_GIC_DIST_GICD_IGROUPR5 register from the beginning of the component. */
621 #define ALT_GIC_DIST_GICD_IGROUPR5_OFST 0x94
622 
623 /*
624  * Register : GICD_IGROUPR6
625  *
626  * Interrupt Group Registers
627  *
628  * Register Layout
629  *
630  * Bits | Access | Reset | Description
631  * :-------|:-------|:------|:------------
632  * [31:0] | RW | 0x0 | Empty
633  *
634  */
635 /*
636  * Field : Empty - fld
637  *
638  * Placeholder
639  *
640  * Field Access Macros:
641  *
642  */
643 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IGROUPR6_FLD register field. */
644 #define ALT_GIC_DIST_GICD_IGROUPR6_FLD_LSB 0
645 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IGROUPR6_FLD register field. */
646 #define ALT_GIC_DIST_GICD_IGROUPR6_FLD_MSB 31
647 /* The width in bits of the ALT_GIC_DIST_GICD_IGROUPR6_FLD register field. */
648 #define ALT_GIC_DIST_GICD_IGROUPR6_FLD_WIDTH 32
649 /* The mask used to set the ALT_GIC_DIST_GICD_IGROUPR6_FLD register field value. */
650 #define ALT_GIC_DIST_GICD_IGROUPR6_FLD_SET_MSK 0xffffffff
651 /* The mask used to clear the ALT_GIC_DIST_GICD_IGROUPR6_FLD register field value. */
652 #define ALT_GIC_DIST_GICD_IGROUPR6_FLD_CLR_MSK 0x00000000
653 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR6_FLD register field. */
654 #define ALT_GIC_DIST_GICD_IGROUPR6_FLD_RESET 0x0
655 /* Extracts the ALT_GIC_DIST_GICD_IGROUPR6_FLD field value from a register. */
656 #define ALT_GIC_DIST_GICD_IGROUPR6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
657 /* Produces a ALT_GIC_DIST_GICD_IGROUPR6_FLD register field value suitable for setting the register. */
658 #define ALT_GIC_DIST_GICD_IGROUPR6_FLD_SET(value) (((value) << 0) & 0xffffffff)
659 
660 #ifndef __ASSEMBLY__
661 /*
662  * WARNING: The C register and register group struct declarations are provided for
663  * convenience and illustrative purposes. They should, however, be used with
664  * caution as the C language standard provides no guarantees about the alignment or
665  * atomicity of device memory accesses. The recommended practice for coding device
666  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
667  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
668  * alt_write_dword() functions for 64 bit registers.
669  *
670  * The struct declaration for register ALT_GIC_DIST_GICD_IGROUPR6.
671  */
672 struct ALT_GIC_DIST_GICD_IGROUPR6_s
673 {
674  volatile uint32_t fld : 32; /* Empty */
675 };
676 
677 /* The typedef declaration for register ALT_GIC_DIST_GICD_IGROUPR6. */
678 typedef struct ALT_GIC_DIST_GICD_IGROUPR6_s ALT_GIC_DIST_GICD_IGROUPR6_t;
679 #endif /* __ASSEMBLY__ */
680 
681 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR6 register. */
682 #define ALT_GIC_DIST_GICD_IGROUPR6_RESET 0x00000000
683 /* The byte offset of the ALT_GIC_DIST_GICD_IGROUPR6 register from the beginning of the component. */
684 #define ALT_GIC_DIST_GICD_IGROUPR6_OFST 0x98
685 
686 /*
687  * Register : GICD_IGROUPR7
688  *
689  * Interrupt Group Registers
690  *
691  * Register Layout
692  *
693  * Bits | Access | Reset | Description
694  * :-------|:-------|:------|:------------
695  * [31:0] | RW | 0x0 | Empty
696  *
697  */
698 /*
699  * Field : Empty - fld
700  *
701  * Placeholder
702  *
703  * Field Access Macros:
704  *
705  */
706 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IGROUPR7_FLD register field. */
707 #define ALT_GIC_DIST_GICD_IGROUPR7_FLD_LSB 0
708 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IGROUPR7_FLD register field. */
709 #define ALT_GIC_DIST_GICD_IGROUPR7_FLD_MSB 31
710 /* The width in bits of the ALT_GIC_DIST_GICD_IGROUPR7_FLD register field. */
711 #define ALT_GIC_DIST_GICD_IGROUPR7_FLD_WIDTH 32
712 /* The mask used to set the ALT_GIC_DIST_GICD_IGROUPR7_FLD register field value. */
713 #define ALT_GIC_DIST_GICD_IGROUPR7_FLD_SET_MSK 0xffffffff
714 /* The mask used to clear the ALT_GIC_DIST_GICD_IGROUPR7_FLD register field value. */
715 #define ALT_GIC_DIST_GICD_IGROUPR7_FLD_CLR_MSK 0x00000000
716 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR7_FLD register field. */
717 #define ALT_GIC_DIST_GICD_IGROUPR7_FLD_RESET 0x0
718 /* Extracts the ALT_GIC_DIST_GICD_IGROUPR7_FLD field value from a register. */
719 #define ALT_GIC_DIST_GICD_IGROUPR7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
720 /* Produces a ALT_GIC_DIST_GICD_IGROUPR7_FLD register field value suitable for setting the register. */
721 #define ALT_GIC_DIST_GICD_IGROUPR7_FLD_SET(value) (((value) << 0) & 0xffffffff)
722 
723 #ifndef __ASSEMBLY__
724 /*
725  * WARNING: The C register and register group struct declarations are provided for
726  * convenience and illustrative purposes. They should, however, be used with
727  * caution as the C language standard provides no guarantees about the alignment or
728  * atomicity of device memory accesses. The recommended practice for coding device
729  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
730  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
731  * alt_write_dword() functions for 64 bit registers.
732  *
733  * The struct declaration for register ALT_GIC_DIST_GICD_IGROUPR7.
734  */
735 struct ALT_GIC_DIST_GICD_IGROUPR7_s
736 {
737  volatile uint32_t fld : 32; /* Empty */
738 };
739 
740 /* The typedef declaration for register ALT_GIC_DIST_GICD_IGROUPR7. */
741 typedef struct ALT_GIC_DIST_GICD_IGROUPR7_s ALT_GIC_DIST_GICD_IGROUPR7_t;
742 #endif /* __ASSEMBLY__ */
743 
744 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR7 register. */
745 #define ALT_GIC_DIST_GICD_IGROUPR7_RESET 0x00000000
746 /* The byte offset of the ALT_GIC_DIST_GICD_IGROUPR7 register from the beginning of the component. */
747 #define ALT_GIC_DIST_GICD_IGROUPR7_OFST 0x9c
748 
749 /*
750  * Register : GICD_IGROUPR8
751  *
752  * Interrupt Group Registers
753  *
754  * Register Layout
755  *
756  * Bits | Access | Reset | Description
757  * :-------|:-------|:------|:------------
758  * [31:0] | RW | 0x0 | Empty
759  *
760  */
761 /*
762  * Field : Empty - fld
763  *
764  * Placeholder
765  *
766  * Field Access Macros:
767  *
768  */
769 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IGROUPR8_FLD register field. */
770 #define ALT_GIC_DIST_GICD_IGROUPR8_FLD_LSB 0
771 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IGROUPR8_FLD register field. */
772 #define ALT_GIC_DIST_GICD_IGROUPR8_FLD_MSB 31
773 /* The width in bits of the ALT_GIC_DIST_GICD_IGROUPR8_FLD register field. */
774 #define ALT_GIC_DIST_GICD_IGROUPR8_FLD_WIDTH 32
775 /* The mask used to set the ALT_GIC_DIST_GICD_IGROUPR8_FLD register field value. */
776 #define ALT_GIC_DIST_GICD_IGROUPR8_FLD_SET_MSK 0xffffffff
777 /* The mask used to clear the ALT_GIC_DIST_GICD_IGROUPR8_FLD register field value. */
778 #define ALT_GIC_DIST_GICD_IGROUPR8_FLD_CLR_MSK 0x00000000
779 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR8_FLD register field. */
780 #define ALT_GIC_DIST_GICD_IGROUPR8_FLD_RESET 0x0
781 /* Extracts the ALT_GIC_DIST_GICD_IGROUPR8_FLD field value from a register. */
782 #define ALT_GIC_DIST_GICD_IGROUPR8_FLD_GET(value) (((value) & 0xffffffff) >> 0)
783 /* Produces a ALT_GIC_DIST_GICD_IGROUPR8_FLD register field value suitable for setting the register. */
784 #define ALT_GIC_DIST_GICD_IGROUPR8_FLD_SET(value) (((value) << 0) & 0xffffffff)
785 
786 #ifndef __ASSEMBLY__
787 /*
788  * WARNING: The C register and register group struct declarations are provided for
789  * convenience and illustrative purposes. They should, however, be used with
790  * caution as the C language standard provides no guarantees about the alignment or
791  * atomicity of device memory accesses. The recommended practice for coding device
792  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
793  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
794  * alt_write_dword() functions for 64 bit registers.
795  *
796  * The struct declaration for register ALT_GIC_DIST_GICD_IGROUPR8.
797  */
798 struct ALT_GIC_DIST_GICD_IGROUPR8_s
799 {
800  volatile uint32_t fld : 32; /* Empty */
801 };
802 
803 /* The typedef declaration for register ALT_GIC_DIST_GICD_IGROUPR8. */
804 typedef struct ALT_GIC_DIST_GICD_IGROUPR8_s ALT_GIC_DIST_GICD_IGROUPR8_t;
805 #endif /* __ASSEMBLY__ */
806 
807 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR8 register. */
808 #define ALT_GIC_DIST_GICD_IGROUPR8_RESET 0x00000000
809 /* The byte offset of the ALT_GIC_DIST_GICD_IGROUPR8 register from the beginning of the component. */
810 #define ALT_GIC_DIST_GICD_IGROUPR8_OFST 0xa0
811 
812 /*
813  * Register : GICD_IGROUPR9
814  *
815  * Interrupt Group Registers
816  *
817  * Register Layout
818  *
819  * Bits | Access | Reset | Description
820  * :-------|:-------|:------|:------------
821  * [31:0] | RW | 0x0 | Empty
822  *
823  */
824 /*
825  * Field : Empty - fld
826  *
827  * Placeholder
828  *
829  * Field Access Macros:
830  *
831  */
832 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IGROUPR9_FLD register field. */
833 #define ALT_GIC_DIST_GICD_IGROUPR9_FLD_LSB 0
834 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IGROUPR9_FLD register field. */
835 #define ALT_GIC_DIST_GICD_IGROUPR9_FLD_MSB 31
836 /* The width in bits of the ALT_GIC_DIST_GICD_IGROUPR9_FLD register field. */
837 #define ALT_GIC_DIST_GICD_IGROUPR9_FLD_WIDTH 32
838 /* The mask used to set the ALT_GIC_DIST_GICD_IGROUPR9_FLD register field value. */
839 #define ALT_GIC_DIST_GICD_IGROUPR9_FLD_SET_MSK 0xffffffff
840 /* The mask used to clear the ALT_GIC_DIST_GICD_IGROUPR9_FLD register field value. */
841 #define ALT_GIC_DIST_GICD_IGROUPR9_FLD_CLR_MSK 0x00000000
842 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR9_FLD register field. */
843 #define ALT_GIC_DIST_GICD_IGROUPR9_FLD_RESET 0x0
844 /* Extracts the ALT_GIC_DIST_GICD_IGROUPR9_FLD field value from a register. */
845 #define ALT_GIC_DIST_GICD_IGROUPR9_FLD_GET(value) (((value) & 0xffffffff) >> 0)
846 /* Produces a ALT_GIC_DIST_GICD_IGROUPR9_FLD register field value suitable for setting the register. */
847 #define ALT_GIC_DIST_GICD_IGROUPR9_FLD_SET(value) (((value) << 0) & 0xffffffff)
848 
849 #ifndef __ASSEMBLY__
850 /*
851  * WARNING: The C register and register group struct declarations are provided for
852  * convenience and illustrative purposes. They should, however, be used with
853  * caution as the C language standard provides no guarantees about the alignment or
854  * atomicity of device memory accesses. The recommended practice for coding device
855  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
856  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
857  * alt_write_dword() functions for 64 bit registers.
858  *
859  * The struct declaration for register ALT_GIC_DIST_GICD_IGROUPR9.
860  */
861 struct ALT_GIC_DIST_GICD_IGROUPR9_s
862 {
863  volatile uint32_t fld : 32; /* Empty */
864 };
865 
866 /* The typedef declaration for register ALT_GIC_DIST_GICD_IGROUPR9. */
867 typedef struct ALT_GIC_DIST_GICD_IGROUPR9_s ALT_GIC_DIST_GICD_IGROUPR9_t;
868 #endif /* __ASSEMBLY__ */
869 
870 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR9 register. */
871 #define ALT_GIC_DIST_GICD_IGROUPR9_RESET 0x00000000
872 /* The byte offset of the ALT_GIC_DIST_GICD_IGROUPR9 register from the beginning of the component. */
873 #define ALT_GIC_DIST_GICD_IGROUPR9_OFST 0xa4
874 
875 /*
876  * Register : GICD_IGROUPR10
877  *
878  * Interrupt Group Registers
879  *
880  * Register Layout
881  *
882  * Bits | Access | Reset | Description
883  * :-------|:-------|:------|:------------
884  * [31:0] | RW | 0x0 | Empty
885  *
886  */
887 /*
888  * Field : Empty - fld
889  *
890  * Placeholder
891  *
892  * Field Access Macros:
893  *
894  */
895 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IGROUPR10_FLD register field. */
896 #define ALT_GIC_DIST_GICD_IGROUPR10_FLD_LSB 0
897 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IGROUPR10_FLD register field. */
898 #define ALT_GIC_DIST_GICD_IGROUPR10_FLD_MSB 31
899 /* The width in bits of the ALT_GIC_DIST_GICD_IGROUPR10_FLD register field. */
900 #define ALT_GIC_DIST_GICD_IGROUPR10_FLD_WIDTH 32
901 /* The mask used to set the ALT_GIC_DIST_GICD_IGROUPR10_FLD register field value. */
902 #define ALT_GIC_DIST_GICD_IGROUPR10_FLD_SET_MSK 0xffffffff
903 /* The mask used to clear the ALT_GIC_DIST_GICD_IGROUPR10_FLD register field value. */
904 #define ALT_GIC_DIST_GICD_IGROUPR10_FLD_CLR_MSK 0x00000000
905 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR10_FLD register field. */
906 #define ALT_GIC_DIST_GICD_IGROUPR10_FLD_RESET 0x0
907 /* Extracts the ALT_GIC_DIST_GICD_IGROUPR10_FLD field value from a register. */
908 #define ALT_GIC_DIST_GICD_IGROUPR10_FLD_GET(value) (((value) & 0xffffffff) >> 0)
909 /* Produces a ALT_GIC_DIST_GICD_IGROUPR10_FLD register field value suitable for setting the register. */
910 #define ALT_GIC_DIST_GICD_IGROUPR10_FLD_SET(value) (((value) << 0) & 0xffffffff)
911 
912 #ifndef __ASSEMBLY__
913 /*
914  * WARNING: The C register and register group struct declarations are provided for
915  * convenience and illustrative purposes. They should, however, be used with
916  * caution as the C language standard provides no guarantees about the alignment or
917  * atomicity of device memory accesses. The recommended practice for coding device
918  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
919  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
920  * alt_write_dword() functions for 64 bit registers.
921  *
922  * The struct declaration for register ALT_GIC_DIST_GICD_IGROUPR10.
923  */
924 struct ALT_GIC_DIST_GICD_IGROUPR10_s
925 {
926  volatile uint32_t fld : 32; /* Empty */
927 };
928 
929 /* The typedef declaration for register ALT_GIC_DIST_GICD_IGROUPR10. */
930 typedef struct ALT_GIC_DIST_GICD_IGROUPR10_s ALT_GIC_DIST_GICD_IGROUPR10_t;
931 #endif /* __ASSEMBLY__ */
932 
933 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR10 register. */
934 #define ALT_GIC_DIST_GICD_IGROUPR10_RESET 0x00000000
935 /* The byte offset of the ALT_GIC_DIST_GICD_IGROUPR10 register from the beginning of the component. */
936 #define ALT_GIC_DIST_GICD_IGROUPR10_OFST 0xa8
937 
938 /*
939  * Register : GICD_IGROUPR11
940  *
941  * Interrupt Group Registers
942  *
943  * Register Layout
944  *
945  * Bits | Access | Reset | Description
946  * :-------|:-------|:------|:------------
947  * [31:0] | RW | 0x0 | Empty
948  *
949  */
950 /*
951  * Field : Empty - fld
952  *
953  * Placeholder
954  *
955  * Field Access Macros:
956  *
957  */
958 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IGROUPR11_FLD register field. */
959 #define ALT_GIC_DIST_GICD_IGROUPR11_FLD_LSB 0
960 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IGROUPR11_FLD register field. */
961 #define ALT_GIC_DIST_GICD_IGROUPR11_FLD_MSB 31
962 /* The width in bits of the ALT_GIC_DIST_GICD_IGROUPR11_FLD register field. */
963 #define ALT_GIC_DIST_GICD_IGROUPR11_FLD_WIDTH 32
964 /* The mask used to set the ALT_GIC_DIST_GICD_IGROUPR11_FLD register field value. */
965 #define ALT_GIC_DIST_GICD_IGROUPR11_FLD_SET_MSK 0xffffffff
966 /* The mask used to clear the ALT_GIC_DIST_GICD_IGROUPR11_FLD register field value. */
967 #define ALT_GIC_DIST_GICD_IGROUPR11_FLD_CLR_MSK 0x00000000
968 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR11_FLD register field. */
969 #define ALT_GIC_DIST_GICD_IGROUPR11_FLD_RESET 0x0
970 /* Extracts the ALT_GIC_DIST_GICD_IGROUPR11_FLD field value from a register. */
971 #define ALT_GIC_DIST_GICD_IGROUPR11_FLD_GET(value) (((value) & 0xffffffff) >> 0)
972 /* Produces a ALT_GIC_DIST_GICD_IGROUPR11_FLD register field value suitable for setting the register. */
973 #define ALT_GIC_DIST_GICD_IGROUPR11_FLD_SET(value) (((value) << 0) & 0xffffffff)
974 
975 #ifndef __ASSEMBLY__
976 /*
977  * WARNING: The C register and register group struct declarations are provided for
978  * convenience and illustrative purposes. They should, however, be used with
979  * caution as the C language standard provides no guarantees about the alignment or
980  * atomicity of device memory accesses. The recommended practice for coding device
981  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
982  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
983  * alt_write_dword() functions for 64 bit registers.
984  *
985  * The struct declaration for register ALT_GIC_DIST_GICD_IGROUPR11.
986  */
987 struct ALT_GIC_DIST_GICD_IGROUPR11_s
988 {
989  volatile uint32_t fld : 32; /* Empty */
990 };
991 
992 /* The typedef declaration for register ALT_GIC_DIST_GICD_IGROUPR11. */
993 typedef struct ALT_GIC_DIST_GICD_IGROUPR11_s ALT_GIC_DIST_GICD_IGROUPR11_t;
994 #endif /* __ASSEMBLY__ */
995 
996 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR11 register. */
997 #define ALT_GIC_DIST_GICD_IGROUPR11_RESET 0x00000000
998 /* The byte offset of the ALT_GIC_DIST_GICD_IGROUPR11 register from the beginning of the component. */
999 #define ALT_GIC_DIST_GICD_IGROUPR11_OFST 0xac
1000 
1001 /*
1002  * Register : GICD_IGROUPR12
1003  *
1004  * Interrupt Group Registers
1005  *
1006  * Register Layout
1007  *
1008  * Bits | Access | Reset | Description
1009  * :-------|:-------|:------|:------------
1010  * [31:0] | RW | 0x0 | Empty
1011  *
1012  */
1013 /*
1014  * Field : Empty - fld
1015  *
1016  * Placeholder
1017  *
1018  * Field Access Macros:
1019  *
1020  */
1021 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IGROUPR12_FLD register field. */
1022 #define ALT_GIC_DIST_GICD_IGROUPR12_FLD_LSB 0
1023 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IGROUPR12_FLD register field. */
1024 #define ALT_GIC_DIST_GICD_IGROUPR12_FLD_MSB 31
1025 /* The width in bits of the ALT_GIC_DIST_GICD_IGROUPR12_FLD register field. */
1026 #define ALT_GIC_DIST_GICD_IGROUPR12_FLD_WIDTH 32
1027 /* The mask used to set the ALT_GIC_DIST_GICD_IGROUPR12_FLD register field value. */
1028 #define ALT_GIC_DIST_GICD_IGROUPR12_FLD_SET_MSK 0xffffffff
1029 /* The mask used to clear the ALT_GIC_DIST_GICD_IGROUPR12_FLD register field value. */
1030 #define ALT_GIC_DIST_GICD_IGROUPR12_FLD_CLR_MSK 0x00000000
1031 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR12_FLD register field. */
1032 #define ALT_GIC_DIST_GICD_IGROUPR12_FLD_RESET 0x0
1033 /* Extracts the ALT_GIC_DIST_GICD_IGROUPR12_FLD field value from a register. */
1034 #define ALT_GIC_DIST_GICD_IGROUPR12_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1035 /* Produces a ALT_GIC_DIST_GICD_IGROUPR12_FLD register field value suitable for setting the register. */
1036 #define ALT_GIC_DIST_GICD_IGROUPR12_FLD_SET(value) (((value) << 0) & 0xffffffff)
1037 
1038 #ifndef __ASSEMBLY__
1039 /*
1040  * WARNING: The C register and register group struct declarations are provided for
1041  * convenience and illustrative purposes. They should, however, be used with
1042  * caution as the C language standard provides no guarantees about the alignment or
1043  * atomicity of device memory accesses. The recommended practice for coding device
1044  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1045  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1046  * alt_write_dword() functions for 64 bit registers.
1047  *
1048  * The struct declaration for register ALT_GIC_DIST_GICD_IGROUPR12.
1049  */
1050 struct ALT_GIC_DIST_GICD_IGROUPR12_s
1051 {
1052  volatile uint32_t fld : 32; /* Empty */
1053 };
1054 
1055 /* The typedef declaration for register ALT_GIC_DIST_GICD_IGROUPR12. */
1056 typedef struct ALT_GIC_DIST_GICD_IGROUPR12_s ALT_GIC_DIST_GICD_IGROUPR12_t;
1057 #endif /* __ASSEMBLY__ */
1058 
1059 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR12 register. */
1060 #define ALT_GIC_DIST_GICD_IGROUPR12_RESET 0x00000000
1061 /* The byte offset of the ALT_GIC_DIST_GICD_IGROUPR12 register from the beginning of the component. */
1062 #define ALT_GIC_DIST_GICD_IGROUPR12_OFST 0xb0
1063 
1064 /*
1065  * Register : GICD_IGROUPR13
1066  *
1067  * Interrupt Group Registers
1068  *
1069  * Register Layout
1070  *
1071  * Bits | Access | Reset | Description
1072  * :-------|:-------|:------|:------------
1073  * [31:0] | RW | 0x0 | Empty
1074  *
1075  */
1076 /*
1077  * Field : Empty - fld
1078  *
1079  * Placeholder
1080  *
1081  * Field Access Macros:
1082  *
1083  */
1084 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IGROUPR13_FLD register field. */
1085 #define ALT_GIC_DIST_GICD_IGROUPR13_FLD_LSB 0
1086 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IGROUPR13_FLD register field. */
1087 #define ALT_GIC_DIST_GICD_IGROUPR13_FLD_MSB 31
1088 /* The width in bits of the ALT_GIC_DIST_GICD_IGROUPR13_FLD register field. */
1089 #define ALT_GIC_DIST_GICD_IGROUPR13_FLD_WIDTH 32
1090 /* The mask used to set the ALT_GIC_DIST_GICD_IGROUPR13_FLD register field value. */
1091 #define ALT_GIC_DIST_GICD_IGROUPR13_FLD_SET_MSK 0xffffffff
1092 /* The mask used to clear the ALT_GIC_DIST_GICD_IGROUPR13_FLD register field value. */
1093 #define ALT_GIC_DIST_GICD_IGROUPR13_FLD_CLR_MSK 0x00000000
1094 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR13_FLD register field. */
1095 #define ALT_GIC_DIST_GICD_IGROUPR13_FLD_RESET 0x0
1096 /* Extracts the ALT_GIC_DIST_GICD_IGROUPR13_FLD field value from a register. */
1097 #define ALT_GIC_DIST_GICD_IGROUPR13_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1098 /* Produces a ALT_GIC_DIST_GICD_IGROUPR13_FLD register field value suitable for setting the register. */
1099 #define ALT_GIC_DIST_GICD_IGROUPR13_FLD_SET(value) (((value) << 0) & 0xffffffff)
1100 
1101 #ifndef __ASSEMBLY__
1102 /*
1103  * WARNING: The C register and register group struct declarations are provided for
1104  * convenience and illustrative purposes. They should, however, be used with
1105  * caution as the C language standard provides no guarantees about the alignment or
1106  * atomicity of device memory accesses. The recommended practice for coding device
1107  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1108  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1109  * alt_write_dword() functions for 64 bit registers.
1110  *
1111  * The struct declaration for register ALT_GIC_DIST_GICD_IGROUPR13.
1112  */
1113 struct ALT_GIC_DIST_GICD_IGROUPR13_s
1114 {
1115  volatile uint32_t fld : 32; /* Empty */
1116 };
1117 
1118 /* The typedef declaration for register ALT_GIC_DIST_GICD_IGROUPR13. */
1119 typedef struct ALT_GIC_DIST_GICD_IGROUPR13_s ALT_GIC_DIST_GICD_IGROUPR13_t;
1120 #endif /* __ASSEMBLY__ */
1121 
1122 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR13 register. */
1123 #define ALT_GIC_DIST_GICD_IGROUPR13_RESET 0x00000000
1124 /* The byte offset of the ALT_GIC_DIST_GICD_IGROUPR13 register from the beginning of the component. */
1125 #define ALT_GIC_DIST_GICD_IGROUPR13_OFST 0xb4
1126 
1127 /*
1128  * Register : GICD_IGROUPR14
1129  *
1130  * Interrupt Group Registers
1131  *
1132  * Register Layout
1133  *
1134  * Bits | Access | Reset | Description
1135  * :-------|:-------|:------|:------------
1136  * [31:0] | RW | 0x0 | Empty
1137  *
1138  */
1139 /*
1140  * Field : Empty - fld
1141  *
1142  * Placeholder
1143  *
1144  * Field Access Macros:
1145  *
1146  */
1147 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IGROUPR14_FLD register field. */
1148 #define ALT_GIC_DIST_GICD_IGROUPR14_FLD_LSB 0
1149 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IGROUPR14_FLD register field. */
1150 #define ALT_GIC_DIST_GICD_IGROUPR14_FLD_MSB 31
1151 /* The width in bits of the ALT_GIC_DIST_GICD_IGROUPR14_FLD register field. */
1152 #define ALT_GIC_DIST_GICD_IGROUPR14_FLD_WIDTH 32
1153 /* The mask used to set the ALT_GIC_DIST_GICD_IGROUPR14_FLD register field value. */
1154 #define ALT_GIC_DIST_GICD_IGROUPR14_FLD_SET_MSK 0xffffffff
1155 /* The mask used to clear the ALT_GIC_DIST_GICD_IGROUPR14_FLD register field value. */
1156 #define ALT_GIC_DIST_GICD_IGROUPR14_FLD_CLR_MSK 0x00000000
1157 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR14_FLD register field. */
1158 #define ALT_GIC_DIST_GICD_IGROUPR14_FLD_RESET 0x0
1159 /* Extracts the ALT_GIC_DIST_GICD_IGROUPR14_FLD field value from a register. */
1160 #define ALT_GIC_DIST_GICD_IGROUPR14_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1161 /* Produces a ALT_GIC_DIST_GICD_IGROUPR14_FLD register field value suitable for setting the register. */
1162 #define ALT_GIC_DIST_GICD_IGROUPR14_FLD_SET(value) (((value) << 0) & 0xffffffff)
1163 
1164 #ifndef __ASSEMBLY__
1165 /*
1166  * WARNING: The C register and register group struct declarations are provided for
1167  * convenience and illustrative purposes. They should, however, be used with
1168  * caution as the C language standard provides no guarantees about the alignment or
1169  * atomicity of device memory accesses. The recommended practice for coding device
1170  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1171  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1172  * alt_write_dword() functions for 64 bit registers.
1173  *
1174  * The struct declaration for register ALT_GIC_DIST_GICD_IGROUPR14.
1175  */
1176 struct ALT_GIC_DIST_GICD_IGROUPR14_s
1177 {
1178  volatile uint32_t fld : 32; /* Empty */
1179 };
1180 
1181 /* The typedef declaration for register ALT_GIC_DIST_GICD_IGROUPR14. */
1182 typedef struct ALT_GIC_DIST_GICD_IGROUPR14_s ALT_GIC_DIST_GICD_IGROUPR14_t;
1183 #endif /* __ASSEMBLY__ */
1184 
1185 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR14 register. */
1186 #define ALT_GIC_DIST_GICD_IGROUPR14_RESET 0x00000000
1187 /* The byte offset of the ALT_GIC_DIST_GICD_IGROUPR14 register from the beginning of the component. */
1188 #define ALT_GIC_DIST_GICD_IGROUPR14_OFST 0xb8
1189 
1190 /*
1191  * Register : GICD_IGROUPR15
1192  *
1193  * Interrupt Group Registers
1194  *
1195  * Register Layout
1196  *
1197  * Bits | Access | Reset | Description
1198  * :-------|:-------|:------|:------------
1199  * [31:0] | RW | 0x0 | Empty
1200  *
1201  */
1202 /*
1203  * Field : Empty - fld
1204  *
1205  * Placeholder
1206  *
1207  * Field Access Macros:
1208  *
1209  */
1210 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IGROUPR15_FLD register field. */
1211 #define ALT_GIC_DIST_GICD_IGROUPR15_FLD_LSB 0
1212 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IGROUPR15_FLD register field. */
1213 #define ALT_GIC_DIST_GICD_IGROUPR15_FLD_MSB 31
1214 /* The width in bits of the ALT_GIC_DIST_GICD_IGROUPR15_FLD register field. */
1215 #define ALT_GIC_DIST_GICD_IGROUPR15_FLD_WIDTH 32
1216 /* The mask used to set the ALT_GIC_DIST_GICD_IGROUPR15_FLD register field value. */
1217 #define ALT_GIC_DIST_GICD_IGROUPR15_FLD_SET_MSK 0xffffffff
1218 /* The mask used to clear the ALT_GIC_DIST_GICD_IGROUPR15_FLD register field value. */
1219 #define ALT_GIC_DIST_GICD_IGROUPR15_FLD_CLR_MSK 0x00000000
1220 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR15_FLD register field. */
1221 #define ALT_GIC_DIST_GICD_IGROUPR15_FLD_RESET 0x0
1222 /* Extracts the ALT_GIC_DIST_GICD_IGROUPR15_FLD field value from a register. */
1223 #define ALT_GIC_DIST_GICD_IGROUPR15_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1224 /* Produces a ALT_GIC_DIST_GICD_IGROUPR15_FLD register field value suitable for setting the register. */
1225 #define ALT_GIC_DIST_GICD_IGROUPR15_FLD_SET(value) (((value) << 0) & 0xffffffff)
1226 
1227 #ifndef __ASSEMBLY__
1228 /*
1229  * WARNING: The C register and register group struct declarations are provided for
1230  * convenience and illustrative purposes. They should, however, be used with
1231  * caution as the C language standard provides no guarantees about the alignment or
1232  * atomicity of device memory accesses. The recommended practice for coding device
1233  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1234  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1235  * alt_write_dword() functions for 64 bit registers.
1236  *
1237  * The struct declaration for register ALT_GIC_DIST_GICD_IGROUPR15.
1238  */
1239 struct ALT_GIC_DIST_GICD_IGROUPR15_s
1240 {
1241  volatile uint32_t fld : 32; /* Empty */
1242 };
1243 
1244 /* The typedef declaration for register ALT_GIC_DIST_GICD_IGROUPR15. */
1245 typedef struct ALT_GIC_DIST_GICD_IGROUPR15_s ALT_GIC_DIST_GICD_IGROUPR15_t;
1246 #endif /* __ASSEMBLY__ */
1247 
1248 /* The reset value of the ALT_GIC_DIST_GICD_IGROUPR15 register. */
1249 #define ALT_GIC_DIST_GICD_IGROUPR15_RESET 0x00000000
1250 /* The byte offset of the ALT_GIC_DIST_GICD_IGROUPR15 register from the beginning of the component. */
1251 #define ALT_GIC_DIST_GICD_IGROUPR15_OFST 0xbc
1252 
1253 /*
1254  * Register : GICD_ISENABLER0
1255  *
1256  * Interrupt Set-Enable Registers
1257  *
1258  * Register Layout
1259  *
1260  * Bits | Access | Reset | Description
1261  * :-------|:-------|:--------|:------------
1262  * [31:0] | RW | Unknown | Empty
1263  *
1264  */
1265 /*
1266  * Field : Empty - fld
1267  *
1268  * Placeholder
1269  *
1270  * Field Access Macros:
1271  *
1272  */
1273 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISENABLER0_FLD register field. */
1274 #define ALT_GIC_DIST_GICD_ISENABLER0_FLD_LSB 0
1275 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISENABLER0_FLD register field. */
1276 #define ALT_GIC_DIST_GICD_ISENABLER0_FLD_MSB 31
1277 /* The width in bits of the ALT_GIC_DIST_GICD_ISENABLER0_FLD register field. */
1278 #define ALT_GIC_DIST_GICD_ISENABLER0_FLD_WIDTH 32
1279 /* The mask used to set the ALT_GIC_DIST_GICD_ISENABLER0_FLD register field value. */
1280 #define ALT_GIC_DIST_GICD_ISENABLER0_FLD_SET_MSK 0xffffffff
1281 /* The mask used to clear the ALT_GIC_DIST_GICD_ISENABLER0_FLD register field value. */
1282 #define ALT_GIC_DIST_GICD_ISENABLER0_FLD_CLR_MSK 0x00000000
1283 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER0_FLD register field is UNKNOWN. */
1284 #define ALT_GIC_DIST_GICD_ISENABLER0_FLD_RESET 0x0
1285 /* Extracts the ALT_GIC_DIST_GICD_ISENABLER0_FLD field value from a register. */
1286 #define ALT_GIC_DIST_GICD_ISENABLER0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1287 /* Produces a ALT_GIC_DIST_GICD_ISENABLER0_FLD register field value suitable for setting the register. */
1288 #define ALT_GIC_DIST_GICD_ISENABLER0_FLD_SET(value) (((value) << 0) & 0xffffffff)
1289 
1290 #ifndef __ASSEMBLY__
1291 /*
1292  * WARNING: The C register and register group struct declarations are provided for
1293  * convenience and illustrative purposes. They should, however, be used with
1294  * caution as the C language standard provides no guarantees about the alignment or
1295  * atomicity of device memory accesses. The recommended practice for coding device
1296  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1297  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1298  * alt_write_dword() functions for 64 bit registers.
1299  *
1300  * The struct declaration for register ALT_GIC_DIST_GICD_ISENABLER0.
1301  */
1302 struct ALT_GIC_DIST_GICD_ISENABLER0_s
1303 {
1304  volatile uint32_t fld : 32; /* Empty */
1305 };
1306 
1307 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISENABLER0. */
1308 typedef struct ALT_GIC_DIST_GICD_ISENABLER0_s ALT_GIC_DIST_GICD_ISENABLER0_t;
1309 #endif /* __ASSEMBLY__ */
1310 
1311 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER0 register. */
1312 #define ALT_GIC_DIST_GICD_ISENABLER0_RESET 0x0000ffff
1313 /* The byte offset of the ALT_GIC_DIST_GICD_ISENABLER0 register from the beginning of the component. */
1314 #define ALT_GIC_DIST_GICD_ISENABLER0_OFST 0x100
1315 
1316 /*
1317  * Register : GICD_ISENABLER1
1318  *
1319  * Interrupt Set-Enable Registers
1320  *
1321  * Register Layout
1322  *
1323  * Bits | Access | Reset | Description
1324  * :-------|:-------|:------|:------------
1325  * [31:0] | RW | 0x0 | Empty
1326  *
1327  */
1328 /*
1329  * Field : Empty - fld
1330  *
1331  * Placeholder
1332  *
1333  * Field Access Macros:
1334  *
1335  */
1336 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISENABLER1_FLD register field. */
1337 #define ALT_GIC_DIST_GICD_ISENABLER1_FLD_LSB 0
1338 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISENABLER1_FLD register field. */
1339 #define ALT_GIC_DIST_GICD_ISENABLER1_FLD_MSB 31
1340 /* The width in bits of the ALT_GIC_DIST_GICD_ISENABLER1_FLD register field. */
1341 #define ALT_GIC_DIST_GICD_ISENABLER1_FLD_WIDTH 32
1342 /* The mask used to set the ALT_GIC_DIST_GICD_ISENABLER1_FLD register field value. */
1343 #define ALT_GIC_DIST_GICD_ISENABLER1_FLD_SET_MSK 0xffffffff
1344 /* The mask used to clear the ALT_GIC_DIST_GICD_ISENABLER1_FLD register field value. */
1345 #define ALT_GIC_DIST_GICD_ISENABLER1_FLD_CLR_MSK 0x00000000
1346 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER1_FLD register field. */
1347 #define ALT_GIC_DIST_GICD_ISENABLER1_FLD_RESET 0x0
1348 /* Extracts the ALT_GIC_DIST_GICD_ISENABLER1_FLD field value from a register. */
1349 #define ALT_GIC_DIST_GICD_ISENABLER1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1350 /* Produces a ALT_GIC_DIST_GICD_ISENABLER1_FLD register field value suitable for setting the register. */
1351 #define ALT_GIC_DIST_GICD_ISENABLER1_FLD_SET(value) (((value) << 0) & 0xffffffff)
1352 
1353 #ifndef __ASSEMBLY__
1354 /*
1355  * WARNING: The C register and register group struct declarations are provided for
1356  * convenience and illustrative purposes. They should, however, be used with
1357  * caution as the C language standard provides no guarantees about the alignment or
1358  * atomicity of device memory accesses. The recommended practice for coding device
1359  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1360  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1361  * alt_write_dword() functions for 64 bit registers.
1362  *
1363  * The struct declaration for register ALT_GIC_DIST_GICD_ISENABLER1.
1364  */
1365 struct ALT_GIC_DIST_GICD_ISENABLER1_s
1366 {
1367  volatile uint32_t fld : 32; /* Empty */
1368 };
1369 
1370 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISENABLER1. */
1371 typedef struct ALT_GIC_DIST_GICD_ISENABLER1_s ALT_GIC_DIST_GICD_ISENABLER1_t;
1372 #endif /* __ASSEMBLY__ */
1373 
1374 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER1 register. */
1375 #define ALT_GIC_DIST_GICD_ISENABLER1_RESET 0x00000000
1376 /* The byte offset of the ALT_GIC_DIST_GICD_ISENABLER1 register from the beginning of the component. */
1377 #define ALT_GIC_DIST_GICD_ISENABLER1_OFST 0x104
1378 
1379 /*
1380  * Register : GICD_ISENABLER2
1381  *
1382  * Interrupt Set-Enable Registers
1383  *
1384  * Register Layout
1385  *
1386  * Bits | Access | Reset | Description
1387  * :-------|:-------|:------|:------------
1388  * [31:0] | RW | 0x0 | Empty
1389  *
1390  */
1391 /*
1392  * Field : Empty - fld
1393  *
1394  * Placeholder
1395  *
1396  * Field Access Macros:
1397  *
1398  */
1399 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISENABLER2_FLD register field. */
1400 #define ALT_GIC_DIST_GICD_ISENABLER2_FLD_LSB 0
1401 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISENABLER2_FLD register field. */
1402 #define ALT_GIC_DIST_GICD_ISENABLER2_FLD_MSB 31
1403 /* The width in bits of the ALT_GIC_DIST_GICD_ISENABLER2_FLD register field. */
1404 #define ALT_GIC_DIST_GICD_ISENABLER2_FLD_WIDTH 32
1405 /* The mask used to set the ALT_GIC_DIST_GICD_ISENABLER2_FLD register field value. */
1406 #define ALT_GIC_DIST_GICD_ISENABLER2_FLD_SET_MSK 0xffffffff
1407 /* The mask used to clear the ALT_GIC_DIST_GICD_ISENABLER2_FLD register field value. */
1408 #define ALT_GIC_DIST_GICD_ISENABLER2_FLD_CLR_MSK 0x00000000
1409 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER2_FLD register field. */
1410 #define ALT_GIC_DIST_GICD_ISENABLER2_FLD_RESET 0x0
1411 /* Extracts the ALT_GIC_DIST_GICD_ISENABLER2_FLD field value from a register. */
1412 #define ALT_GIC_DIST_GICD_ISENABLER2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1413 /* Produces a ALT_GIC_DIST_GICD_ISENABLER2_FLD register field value suitable for setting the register. */
1414 #define ALT_GIC_DIST_GICD_ISENABLER2_FLD_SET(value) (((value) << 0) & 0xffffffff)
1415 
1416 #ifndef __ASSEMBLY__
1417 /*
1418  * WARNING: The C register and register group struct declarations are provided for
1419  * convenience and illustrative purposes. They should, however, be used with
1420  * caution as the C language standard provides no guarantees about the alignment or
1421  * atomicity of device memory accesses. The recommended practice for coding device
1422  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1423  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1424  * alt_write_dword() functions for 64 bit registers.
1425  *
1426  * The struct declaration for register ALT_GIC_DIST_GICD_ISENABLER2.
1427  */
1428 struct ALT_GIC_DIST_GICD_ISENABLER2_s
1429 {
1430  volatile uint32_t fld : 32; /* Empty */
1431 };
1432 
1433 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISENABLER2. */
1434 typedef struct ALT_GIC_DIST_GICD_ISENABLER2_s ALT_GIC_DIST_GICD_ISENABLER2_t;
1435 #endif /* __ASSEMBLY__ */
1436 
1437 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER2 register. */
1438 #define ALT_GIC_DIST_GICD_ISENABLER2_RESET 0x00000000
1439 /* The byte offset of the ALT_GIC_DIST_GICD_ISENABLER2 register from the beginning of the component. */
1440 #define ALT_GIC_DIST_GICD_ISENABLER2_OFST 0x108
1441 
1442 /*
1443  * Register : GICD_ISENABLER3
1444  *
1445  * Interrupt Set-Enable Registers
1446  *
1447  * Register Layout
1448  *
1449  * Bits | Access | Reset | Description
1450  * :-------|:-------|:------|:------------
1451  * [31:0] | RW | 0x0 | Empty
1452  *
1453  */
1454 /*
1455  * Field : Empty - fld
1456  *
1457  * Placeholder
1458  *
1459  * Field Access Macros:
1460  *
1461  */
1462 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISENABLER3_FLD register field. */
1463 #define ALT_GIC_DIST_GICD_ISENABLER3_FLD_LSB 0
1464 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISENABLER3_FLD register field. */
1465 #define ALT_GIC_DIST_GICD_ISENABLER3_FLD_MSB 31
1466 /* The width in bits of the ALT_GIC_DIST_GICD_ISENABLER3_FLD register field. */
1467 #define ALT_GIC_DIST_GICD_ISENABLER3_FLD_WIDTH 32
1468 /* The mask used to set the ALT_GIC_DIST_GICD_ISENABLER3_FLD register field value. */
1469 #define ALT_GIC_DIST_GICD_ISENABLER3_FLD_SET_MSK 0xffffffff
1470 /* The mask used to clear the ALT_GIC_DIST_GICD_ISENABLER3_FLD register field value. */
1471 #define ALT_GIC_DIST_GICD_ISENABLER3_FLD_CLR_MSK 0x00000000
1472 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER3_FLD register field. */
1473 #define ALT_GIC_DIST_GICD_ISENABLER3_FLD_RESET 0x0
1474 /* Extracts the ALT_GIC_DIST_GICD_ISENABLER3_FLD field value from a register. */
1475 #define ALT_GIC_DIST_GICD_ISENABLER3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1476 /* Produces a ALT_GIC_DIST_GICD_ISENABLER3_FLD register field value suitable for setting the register. */
1477 #define ALT_GIC_DIST_GICD_ISENABLER3_FLD_SET(value) (((value) << 0) & 0xffffffff)
1478 
1479 #ifndef __ASSEMBLY__
1480 /*
1481  * WARNING: The C register and register group struct declarations are provided for
1482  * convenience and illustrative purposes. They should, however, be used with
1483  * caution as the C language standard provides no guarantees about the alignment or
1484  * atomicity of device memory accesses. The recommended practice for coding device
1485  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1486  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1487  * alt_write_dword() functions for 64 bit registers.
1488  *
1489  * The struct declaration for register ALT_GIC_DIST_GICD_ISENABLER3.
1490  */
1491 struct ALT_GIC_DIST_GICD_ISENABLER3_s
1492 {
1493  volatile uint32_t fld : 32; /* Empty */
1494 };
1495 
1496 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISENABLER3. */
1497 typedef struct ALT_GIC_DIST_GICD_ISENABLER3_s ALT_GIC_DIST_GICD_ISENABLER3_t;
1498 #endif /* __ASSEMBLY__ */
1499 
1500 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER3 register. */
1501 #define ALT_GIC_DIST_GICD_ISENABLER3_RESET 0x00000000
1502 /* The byte offset of the ALT_GIC_DIST_GICD_ISENABLER3 register from the beginning of the component. */
1503 #define ALT_GIC_DIST_GICD_ISENABLER3_OFST 0x10c
1504 
1505 /*
1506  * Register : GICD_ISENABLER4
1507  *
1508  * Interrupt Set-Enable Registers
1509  *
1510  * Register Layout
1511  *
1512  * Bits | Access | Reset | Description
1513  * :-------|:-------|:------|:------------
1514  * [31:0] | RW | 0x0 | Empty
1515  *
1516  */
1517 /*
1518  * Field : Empty - fld
1519  *
1520  * Placeholder
1521  *
1522  * Field Access Macros:
1523  *
1524  */
1525 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISENABLER4_FLD register field. */
1526 #define ALT_GIC_DIST_GICD_ISENABLER4_FLD_LSB 0
1527 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISENABLER4_FLD register field. */
1528 #define ALT_GIC_DIST_GICD_ISENABLER4_FLD_MSB 31
1529 /* The width in bits of the ALT_GIC_DIST_GICD_ISENABLER4_FLD register field. */
1530 #define ALT_GIC_DIST_GICD_ISENABLER4_FLD_WIDTH 32
1531 /* The mask used to set the ALT_GIC_DIST_GICD_ISENABLER4_FLD register field value. */
1532 #define ALT_GIC_DIST_GICD_ISENABLER4_FLD_SET_MSK 0xffffffff
1533 /* The mask used to clear the ALT_GIC_DIST_GICD_ISENABLER4_FLD register field value. */
1534 #define ALT_GIC_DIST_GICD_ISENABLER4_FLD_CLR_MSK 0x00000000
1535 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER4_FLD register field. */
1536 #define ALT_GIC_DIST_GICD_ISENABLER4_FLD_RESET 0x0
1537 /* Extracts the ALT_GIC_DIST_GICD_ISENABLER4_FLD field value from a register. */
1538 #define ALT_GIC_DIST_GICD_ISENABLER4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1539 /* Produces a ALT_GIC_DIST_GICD_ISENABLER4_FLD register field value suitable for setting the register. */
1540 #define ALT_GIC_DIST_GICD_ISENABLER4_FLD_SET(value) (((value) << 0) & 0xffffffff)
1541 
1542 #ifndef __ASSEMBLY__
1543 /*
1544  * WARNING: The C register and register group struct declarations are provided for
1545  * convenience and illustrative purposes. They should, however, be used with
1546  * caution as the C language standard provides no guarantees about the alignment or
1547  * atomicity of device memory accesses. The recommended practice for coding device
1548  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1549  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1550  * alt_write_dword() functions for 64 bit registers.
1551  *
1552  * The struct declaration for register ALT_GIC_DIST_GICD_ISENABLER4.
1553  */
1554 struct ALT_GIC_DIST_GICD_ISENABLER4_s
1555 {
1556  volatile uint32_t fld : 32; /* Empty */
1557 };
1558 
1559 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISENABLER4. */
1560 typedef struct ALT_GIC_DIST_GICD_ISENABLER4_s ALT_GIC_DIST_GICD_ISENABLER4_t;
1561 #endif /* __ASSEMBLY__ */
1562 
1563 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER4 register. */
1564 #define ALT_GIC_DIST_GICD_ISENABLER4_RESET 0x00000000
1565 /* The byte offset of the ALT_GIC_DIST_GICD_ISENABLER4 register from the beginning of the component. */
1566 #define ALT_GIC_DIST_GICD_ISENABLER4_OFST 0x110
1567 
1568 /*
1569  * Register : GICD_ISENABLER5
1570  *
1571  * Interrupt Set-Enable Registers
1572  *
1573  * Register Layout
1574  *
1575  * Bits | Access | Reset | Description
1576  * :-------|:-------|:------|:------------
1577  * [31:0] | RW | 0x0 | Empty
1578  *
1579  */
1580 /*
1581  * Field : Empty - fld
1582  *
1583  * Placeholder
1584  *
1585  * Field Access Macros:
1586  *
1587  */
1588 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISENABLER5_FLD register field. */
1589 #define ALT_GIC_DIST_GICD_ISENABLER5_FLD_LSB 0
1590 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISENABLER5_FLD register field. */
1591 #define ALT_GIC_DIST_GICD_ISENABLER5_FLD_MSB 31
1592 /* The width in bits of the ALT_GIC_DIST_GICD_ISENABLER5_FLD register field. */
1593 #define ALT_GIC_DIST_GICD_ISENABLER5_FLD_WIDTH 32
1594 /* The mask used to set the ALT_GIC_DIST_GICD_ISENABLER5_FLD register field value. */
1595 #define ALT_GIC_DIST_GICD_ISENABLER5_FLD_SET_MSK 0xffffffff
1596 /* The mask used to clear the ALT_GIC_DIST_GICD_ISENABLER5_FLD register field value. */
1597 #define ALT_GIC_DIST_GICD_ISENABLER5_FLD_CLR_MSK 0x00000000
1598 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER5_FLD register field. */
1599 #define ALT_GIC_DIST_GICD_ISENABLER5_FLD_RESET 0x0
1600 /* Extracts the ALT_GIC_DIST_GICD_ISENABLER5_FLD field value from a register. */
1601 #define ALT_GIC_DIST_GICD_ISENABLER5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1602 /* Produces a ALT_GIC_DIST_GICD_ISENABLER5_FLD register field value suitable for setting the register. */
1603 #define ALT_GIC_DIST_GICD_ISENABLER5_FLD_SET(value) (((value) << 0) & 0xffffffff)
1604 
1605 #ifndef __ASSEMBLY__
1606 /*
1607  * WARNING: The C register and register group struct declarations are provided for
1608  * convenience and illustrative purposes. They should, however, be used with
1609  * caution as the C language standard provides no guarantees about the alignment or
1610  * atomicity of device memory accesses. The recommended practice for coding device
1611  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1612  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1613  * alt_write_dword() functions for 64 bit registers.
1614  *
1615  * The struct declaration for register ALT_GIC_DIST_GICD_ISENABLER5.
1616  */
1617 struct ALT_GIC_DIST_GICD_ISENABLER5_s
1618 {
1619  volatile uint32_t fld : 32; /* Empty */
1620 };
1621 
1622 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISENABLER5. */
1623 typedef struct ALT_GIC_DIST_GICD_ISENABLER5_s ALT_GIC_DIST_GICD_ISENABLER5_t;
1624 #endif /* __ASSEMBLY__ */
1625 
1626 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER5 register. */
1627 #define ALT_GIC_DIST_GICD_ISENABLER5_RESET 0x00000000
1628 /* The byte offset of the ALT_GIC_DIST_GICD_ISENABLER5 register from the beginning of the component. */
1629 #define ALT_GIC_DIST_GICD_ISENABLER5_OFST 0x114
1630 
1631 /*
1632  * Register : GICD_ISENABLER6
1633  *
1634  * Interrupt Set-Enable Registers
1635  *
1636  * Register Layout
1637  *
1638  * Bits | Access | Reset | Description
1639  * :-------|:-------|:------|:------------
1640  * [31:0] | RW | 0x0 | Empty
1641  *
1642  */
1643 /*
1644  * Field : Empty - fld
1645  *
1646  * Placeholder
1647  *
1648  * Field Access Macros:
1649  *
1650  */
1651 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISENABLER6_FLD register field. */
1652 #define ALT_GIC_DIST_GICD_ISENABLER6_FLD_LSB 0
1653 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISENABLER6_FLD register field. */
1654 #define ALT_GIC_DIST_GICD_ISENABLER6_FLD_MSB 31
1655 /* The width in bits of the ALT_GIC_DIST_GICD_ISENABLER6_FLD register field. */
1656 #define ALT_GIC_DIST_GICD_ISENABLER6_FLD_WIDTH 32
1657 /* The mask used to set the ALT_GIC_DIST_GICD_ISENABLER6_FLD register field value. */
1658 #define ALT_GIC_DIST_GICD_ISENABLER6_FLD_SET_MSK 0xffffffff
1659 /* The mask used to clear the ALT_GIC_DIST_GICD_ISENABLER6_FLD register field value. */
1660 #define ALT_GIC_DIST_GICD_ISENABLER6_FLD_CLR_MSK 0x00000000
1661 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER6_FLD register field. */
1662 #define ALT_GIC_DIST_GICD_ISENABLER6_FLD_RESET 0x0
1663 /* Extracts the ALT_GIC_DIST_GICD_ISENABLER6_FLD field value from a register. */
1664 #define ALT_GIC_DIST_GICD_ISENABLER6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1665 /* Produces a ALT_GIC_DIST_GICD_ISENABLER6_FLD register field value suitable for setting the register. */
1666 #define ALT_GIC_DIST_GICD_ISENABLER6_FLD_SET(value) (((value) << 0) & 0xffffffff)
1667 
1668 #ifndef __ASSEMBLY__
1669 /*
1670  * WARNING: The C register and register group struct declarations are provided for
1671  * convenience and illustrative purposes. They should, however, be used with
1672  * caution as the C language standard provides no guarantees about the alignment or
1673  * atomicity of device memory accesses. The recommended practice for coding device
1674  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1675  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1676  * alt_write_dword() functions for 64 bit registers.
1677  *
1678  * The struct declaration for register ALT_GIC_DIST_GICD_ISENABLER6.
1679  */
1680 struct ALT_GIC_DIST_GICD_ISENABLER6_s
1681 {
1682  volatile uint32_t fld : 32; /* Empty */
1683 };
1684 
1685 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISENABLER6. */
1686 typedef struct ALT_GIC_DIST_GICD_ISENABLER6_s ALT_GIC_DIST_GICD_ISENABLER6_t;
1687 #endif /* __ASSEMBLY__ */
1688 
1689 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER6 register. */
1690 #define ALT_GIC_DIST_GICD_ISENABLER6_RESET 0x00000000
1691 /* The byte offset of the ALT_GIC_DIST_GICD_ISENABLER6 register from the beginning of the component. */
1692 #define ALT_GIC_DIST_GICD_ISENABLER6_OFST 0x118
1693 
1694 /*
1695  * Register : GICD_ISENABLER7
1696  *
1697  * Interrupt Set-Enable Registers
1698  *
1699  * Register Layout
1700  *
1701  * Bits | Access | Reset | Description
1702  * :-------|:-------|:------|:------------
1703  * [31:0] | RW | 0x0 | Empty
1704  *
1705  */
1706 /*
1707  * Field : Empty - fld
1708  *
1709  * Placeholder
1710  *
1711  * Field Access Macros:
1712  *
1713  */
1714 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISENABLER7_FLD register field. */
1715 #define ALT_GIC_DIST_GICD_ISENABLER7_FLD_LSB 0
1716 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISENABLER7_FLD register field. */
1717 #define ALT_GIC_DIST_GICD_ISENABLER7_FLD_MSB 31
1718 /* The width in bits of the ALT_GIC_DIST_GICD_ISENABLER7_FLD register field. */
1719 #define ALT_GIC_DIST_GICD_ISENABLER7_FLD_WIDTH 32
1720 /* The mask used to set the ALT_GIC_DIST_GICD_ISENABLER7_FLD register field value. */
1721 #define ALT_GIC_DIST_GICD_ISENABLER7_FLD_SET_MSK 0xffffffff
1722 /* The mask used to clear the ALT_GIC_DIST_GICD_ISENABLER7_FLD register field value. */
1723 #define ALT_GIC_DIST_GICD_ISENABLER7_FLD_CLR_MSK 0x00000000
1724 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER7_FLD register field. */
1725 #define ALT_GIC_DIST_GICD_ISENABLER7_FLD_RESET 0x0
1726 /* Extracts the ALT_GIC_DIST_GICD_ISENABLER7_FLD field value from a register. */
1727 #define ALT_GIC_DIST_GICD_ISENABLER7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1728 /* Produces a ALT_GIC_DIST_GICD_ISENABLER7_FLD register field value suitable for setting the register. */
1729 #define ALT_GIC_DIST_GICD_ISENABLER7_FLD_SET(value) (((value) << 0) & 0xffffffff)
1730 
1731 #ifndef __ASSEMBLY__
1732 /*
1733  * WARNING: The C register and register group struct declarations are provided for
1734  * convenience and illustrative purposes. They should, however, be used with
1735  * caution as the C language standard provides no guarantees about the alignment or
1736  * atomicity of device memory accesses. The recommended practice for coding device
1737  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1738  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1739  * alt_write_dword() functions for 64 bit registers.
1740  *
1741  * The struct declaration for register ALT_GIC_DIST_GICD_ISENABLER7.
1742  */
1743 struct ALT_GIC_DIST_GICD_ISENABLER7_s
1744 {
1745  volatile uint32_t fld : 32; /* Empty */
1746 };
1747 
1748 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISENABLER7. */
1749 typedef struct ALT_GIC_DIST_GICD_ISENABLER7_s ALT_GIC_DIST_GICD_ISENABLER7_t;
1750 #endif /* __ASSEMBLY__ */
1751 
1752 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER7 register. */
1753 #define ALT_GIC_DIST_GICD_ISENABLER7_RESET 0x00000000
1754 /* The byte offset of the ALT_GIC_DIST_GICD_ISENABLER7 register from the beginning of the component. */
1755 #define ALT_GIC_DIST_GICD_ISENABLER7_OFST 0x11c
1756 
1757 /*
1758  * Register : GICD_ISENABLER8
1759  *
1760  * Interrupt Set-Enable Registers
1761  *
1762  * Register Layout
1763  *
1764  * Bits | Access | Reset | Description
1765  * :-------|:-------|:------|:------------
1766  * [31:0] | RW | 0x0 | Empty
1767  *
1768  */
1769 /*
1770  * Field : Empty - fld
1771  *
1772  * Placeholder
1773  *
1774  * Field Access Macros:
1775  *
1776  */
1777 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISENABLER8_FLD register field. */
1778 #define ALT_GIC_DIST_GICD_ISENABLER8_FLD_LSB 0
1779 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISENABLER8_FLD register field. */
1780 #define ALT_GIC_DIST_GICD_ISENABLER8_FLD_MSB 31
1781 /* The width in bits of the ALT_GIC_DIST_GICD_ISENABLER8_FLD register field. */
1782 #define ALT_GIC_DIST_GICD_ISENABLER8_FLD_WIDTH 32
1783 /* The mask used to set the ALT_GIC_DIST_GICD_ISENABLER8_FLD register field value. */
1784 #define ALT_GIC_DIST_GICD_ISENABLER8_FLD_SET_MSK 0xffffffff
1785 /* The mask used to clear the ALT_GIC_DIST_GICD_ISENABLER8_FLD register field value. */
1786 #define ALT_GIC_DIST_GICD_ISENABLER8_FLD_CLR_MSK 0x00000000
1787 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER8_FLD register field. */
1788 #define ALT_GIC_DIST_GICD_ISENABLER8_FLD_RESET 0x0
1789 /* Extracts the ALT_GIC_DIST_GICD_ISENABLER8_FLD field value from a register. */
1790 #define ALT_GIC_DIST_GICD_ISENABLER8_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1791 /* Produces a ALT_GIC_DIST_GICD_ISENABLER8_FLD register field value suitable for setting the register. */
1792 #define ALT_GIC_DIST_GICD_ISENABLER8_FLD_SET(value) (((value) << 0) & 0xffffffff)
1793 
1794 #ifndef __ASSEMBLY__
1795 /*
1796  * WARNING: The C register and register group struct declarations are provided for
1797  * convenience and illustrative purposes. They should, however, be used with
1798  * caution as the C language standard provides no guarantees about the alignment or
1799  * atomicity of device memory accesses. The recommended practice for coding device
1800  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1801  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1802  * alt_write_dword() functions for 64 bit registers.
1803  *
1804  * The struct declaration for register ALT_GIC_DIST_GICD_ISENABLER8.
1805  */
1806 struct ALT_GIC_DIST_GICD_ISENABLER8_s
1807 {
1808  volatile uint32_t fld : 32; /* Empty */
1809 };
1810 
1811 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISENABLER8. */
1812 typedef struct ALT_GIC_DIST_GICD_ISENABLER8_s ALT_GIC_DIST_GICD_ISENABLER8_t;
1813 #endif /* __ASSEMBLY__ */
1814 
1815 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER8 register. */
1816 #define ALT_GIC_DIST_GICD_ISENABLER8_RESET 0x00000000
1817 /* The byte offset of the ALT_GIC_DIST_GICD_ISENABLER8 register from the beginning of the component. */
1818 #define ALT_GIC_DIST_GICD_ISENABLER8_OFST 0x120
1819 
1820 /*
1821  * Register : GICD_ISENABLER9
1822  *
1823  * Interrupt Set-Enable Registers
1824  *
1825  * Register Layout
1826  *
1827  * Bits | Access | Reset | Description
1828  * :-------|:-------|:------|:------------
1829  * [31:0] | RW | 0x0 | Empty
1830  *
1831  */
1832 /*
1833  * Field : Empty - fld
1834  *
1835  * Placeholder
1836  *
1837  * Field Access Macros:
1838  *
1839  */
1840 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISENABLER9_FLD register field. */
1841 #define ALT_GIC_DIST_GICD_ISENABLER9_FLD_LSB 0
1842 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISENABLER9_FLD register field. */
1843 #define ALT_GIC_DIST_GICD_ISENABLER9_FLD_MSB 31
1844 /* The width in bits of the ALT_GIC_DIST_GICD_ISENABLER9_FLD register field. */
1845 #define ALT_GIC_DIST_GICD_ISENABLER9_FLD_WIDTH 32
1846 /* The mask used to set the ALT_GIC_DIST_GICD_ISENABLER9_FLD register field value. */
1847 #define ALT_GIC_DIST_GICD_ISENABLER9_FLD_SET_MSK 0xffffffff
1848 /* The mask used to clear the ALT_GIC_DIST_GICD_ISENABLER9_FLD register field value. */
1849 #define ALT_GIC_DIST_GICD_ISENABLER9_FLD_CLR_MSK 0x00000000
1850 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER9_FLD register field. */
1851 #define ALT_GIC_DIST_GICD_ISENABLER9_FLD_RESET 0x0
1852 /* Extracts the ALT_GIC_DIST_GICD_ISENABLER9_FLD field value from a register. */
1853 #define ALT_GIC_DIST_GICD_ISENABLER9_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1854 /* Produces a ALT_GIC_DIST_GICD_ISENABLER9_FLD register field value suitable for setting the register. */
1855 #define ALT_GIC_DIST_GICD_ISENABLER9_FLD_SET(value) (((value) << 0) & 0xffffffff)
1856 
1857 #ifndef __ASSEMBLY__
1858 /*
1859  * WARNING: The C register and register group struct declarations are provided for
1860  * convenience and illustrative purposes. They should, however, be used with
1861  * caution as the C language standard provides no guarantees about the alignment or
1862  * atomicity of device memory accesses. The recommended practice for coding device
1863  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1864  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1865  * alt_write_dword() functions for 64 bit registers.
1866  *
1867  * The struct declaration for register ALT_GIC_DIST_GICD_ISENABLER9.
1868  */
1869 struct ALT_GIC_DIST_GICD_ISENABLER9_s
1870 {
1871  volatile uint32_t fld : 32; /* Empty */
1872 };
1873 
1874 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISENABLER9. */
1875 typedef struct ALT_GIC_DIST_GICD_ISENABLER9_s ALT_GIC_DIST_GICD_ISENABLER9_t;
1876 #endif /* __ASSEMBLY__ */
1877 
1878 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER9 register. */
1879 #define ALT_GIC_DIST_GICD_ISENABLER9_RESET 0x00000000
1880 /* The byte offset of the ALT_GIC_DIST_GICD_ISENABLER9 register from the beginning of the component. */
1881 #define ALT_GIC_DIST_GICD_ISENABLER9_OFST 0x124
1882 
1883 /*
1884  * Register : GICD_ISENABLER10
1885  *
1886  * Interrupt Set-Enable Registers
1887  *
1888  * Register Layout
1889  *
1890  * Bits | Access | Reset | Description
1891  * :-------|:-------|:------|:------------
1892  * [31:0] | RW | 0x0 | Empty
1893  *
1894  */
1895 /*
1896  * Field : Empty - fld
1897  *
1898  * Placeholder
1899  *
1900  * Field Access Macros:
1901  *
1902  */
1903 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISENABLER10_FLD register field. */
1904 #define ALT_GIC_DIST_GICD_ISENABLER10_FLD_LSB 0
1905 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISENABLER10_FLD register field. */
1906 #define ALT_GIC_DIST_GICD_ISENABLER10_FLD_MSB 31
1907 /* The width in bits of the ALT_GIC_DIST_GICD_ISENABLER10_FLD register field. */
1908 #define ALT_GIC_DIST_GICD_ISENABLER10_FLD_WIDTH 32
1909 /* The mask used to set the ALT_GIC_DIST_GICD_ISENABLER10_FLD register field value. */
1910 #define ALT_GIC_DIST_GICD_ISENABLER10_FLD_SET_MSK 0xffffffff
1911 /* The mask used to clear the ALT_GIC_DIST_GICD_ISENABLER10_FLD register field value. */
1912 #define ALT_GIC_DIST_GICD_ISENABLER10_FLD_CLR_MSK 0x00000000
1913 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER10_FLD register field. */
1914 #define ALT_GIC_DIST_GICD_ISENABLER10_FLD_RESET 0x0
1915 /* Extracts the ALT_GIC_DIST_GICD_ISENABLER10_FLD field value from a register. */
1916 #define ALT_GIC_DIST_GICD_ISENABLER10_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1917 /* Produces a ALT_GIC_DIST_GICD_ISENABLER10_FLD register field value suitable for setting the register. */
1918 #define ALT_GIC_DIST_GICD_ISENABLER10_FLD_SET(value) (((value) << 0) & 0xffffffff)
1919 
1920 #ifndef __ASSEMBLY__
1921 /*
1922  * WARNING: The C register and register group struct declarations are provided for
1923  * convenience and illustrative purposes. They should, however, be used with
1924  * caution as the C language standard provides no guarantees about the alignment or
1925  * atomicity of device memory accesses. The recommended practice for coding device
1926  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1927  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1928  * alt_write_dword() functions for 64 bit registers.
1929  *
1930  * The struct declaration for register ALT_GIC_DIST_GICD_ISENABLER10.
1931  */
1932 struct ALT_GIC_DIST_GICD_ISENABLER10_s
1933 {
1934  volatile uint32_t fld : 32; /* Empty */
1935 };
1936 
1937 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISENABLER10. */
1938 typedef struct ALT_GIC_DIST_GICD_ISENABLER10_s ALT_GIC_DIST_GICD_ISENABLER10_t;
1939 #endif /* __ASSEMBLY__ */
1940 
1941 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER10 register. */
1942 #define ALT_GIC_DIST_GICD_ISENABLER10_RESET 0x00000000
1943 /* The byte offset of the ALT_GIC_DIST_GICD_ISENABLER10 register from the beginning of the component. */
1944 #define ALT_GIC_DIST_GICD_ISENABLER10_OFST 0x128
1945 
1946 /*
1947  * Register : GICD_ISENABLER11
1948  *
1949  * Interrupt Set-Enable Registers
1950  *
1951  * Register Layout
1952  *
1953  * Bits | Access | Reset | Description
1954  * :-------|:-------|:------|:------------
1955  * [31:0] | RW | 0x0 | Empty
1956  *
1957  */
1958 /*
1959  * Field : Empty - fld
1960  *
1961  * Placeholder
1962  *
1963  * Field Access Macros:
1964  *
1965  */
1966 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISENABLER11_FLD register field. */
1967 #define ALT_GIC_DIST_GICD_ISENABLER11_FLD_LSB 0
1968 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISENABLER11_FLD register field. */
1969 #define ALT_GIC_DIST_GICD_ISENABLER11_FLD_MSB 31
1970 /* The width in bits of the ALT_GIC_DIST_GICD_ISENABLER11_FLD register field. */
1971 #define ALT_GIC_DIST_GICD_ISENABLER11_FLD_WIDTH 32
1972 /* The mask used to set the ALT_GIC_DIST_GICD_ISENABLER11_FLD register field value. */
1973 #define ALT_GIC_DIST_GICD_ISENABLER11_FLD_SET_MSK 0xffffffff
1974 /* The mask used to clear the ALT_GIC_DIST_GICD_ISENABLER11_FLD register field value. */
1975 #define ALT_GIC_DIST_GICD_ISENABLER11_FLD_CLR_MSK 0x00000000
1976 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER11_FLD register field. */
1977 #define ALT_GIC_DIST_GICD_ISENABLER11_FLD_RESET 0x0
1978 /* Extracts the ALT_GIC_DIST_GICD_ISENABLER11_FLD field value from a register. */
1979 #define ALT_GIC_DIST_GICD_ISENABLER11_FLD_GET(value) (((value) & 0xffffffff) >> 0)
1980 /* Produces a ALT_GIC_DIST_GICD_ISENABLER11_FLD register field value suitable for setting the register. */
1981 #define ALT_GIC_DIST_GICD_ISENABLER11_FLD_SET(value) (((value) << 0) & 0xffffffff)
1982 
1983 #ifndef __ASSEMBLY__
1984 /*
1985  * WARNING: The C register and register group struct declarations are provided for
1986  * convenience and illustrative purposes. They should, however, be used with
1987  * caution as the C language standard provides no guarantees about the alignment or
1988  * atomicity of device memory accesses. The recommended practice for coding device
1989  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1990  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1991  * alt_write_dword() functions for 64 bit registers.
1992  *
1993  * The struct declaration for register ALT_GIC_DIST_GICD_ISENABLER11.
1994  */
1995 struct ALT_GIC_DIST_GICD_ISENABLER11_s
1996 {
1997  volatile uint32_t fld : 32; /* Empty */
1998 };
1999 
2000 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISENABLER11. */
2001 typedef struct ALT_GIC_DIST_GICD_ISENABLER11_s ALT_GIC_DIST_GICD_ISENABLER11_t;
2002 #endif /* __ASSEMBLY__ */
2003 
2004 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER11 register. */
2005 #define ALT_GIC_DIST_GICD_ISENABLER11_RESET 0x00000000
2006 /* The byte offset of the ALT_GIC_DIST_GICD_ISENABLER11 register from the beginning of the component. */
2007 #define ALT_GIC_DIST_GICD_ISENABLER11_OFST 0x12c
2008 
2009 /*
2010  * Register : GICD_ISENABLER12
2011  *
2012  * Interrupt Set-Enable Registers
2013  *
2014  * Register Layout
2015  *
2016  * Bits | Access | Reset | Description
2017  * :-------|:-------|:------|:------------
2018  * [31:0] | RW | 0x0 | Empty
2019  *
2020  */
2021 /*
2022  * Field : Empty - fld
2023  *
2024  * Placeholder
2025  *
2026  * Field Access Macros:
2027  *
2028  */
2029 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISENABLER12_FLD register field. */
2030 #define ALT_GIC_DIST_GICD_ISENABLER12_FLD_LSB 0
2031 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISENABLER12_FLD register field. */
2032 #define ALT_GIC_DIST_GICD_ISENABLER12_FLD_MSB 31
2033 /* The width in bits of the ALT_GIC_DIST_GICD_ISENABLER12_FLD register field. */
2034 #define ALT_GIC_DIST_GICD_ISENABLER12_FLD_WIDTH 32
2035 /* The mask used to set the ALT_GIC_DIST_GICD_ISENABLER12_FLD register field value. */
2036 #define ALT_GIC_DIST_GICD_ISENABLER12_FLD_SET_MSK 0xffffffff
2037 /* The mask used to clear the ALT_GIC_DIST_GICD_ISENABLER12_FLD register field value. */
2038 #define ALT_GIC_DIST_GICD_ISENABLER12_FLD_CLR_MSK 0x00000000
2039 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER12_FLD register field. */
2040 #define ALT_GIC_DIST_GICD_ISENABLER12_FLD_RESET 0x0
2041 /* Extracts the ALT_GIC_DIST_GICD_ISENABLER12_FLD field value from a register. */
2042 #define ALT_GIC_DIST_GICD_ISENABLER12_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2043 /* Produces a ALT_GIC_DIST_GICD_ISENABLER12_FLD register field value suitable for setting the register. */
2044 #define ALT_GIC_DIST_GICD_ISENABLER12_FLD_SET(value) (((value) << 0) & 0xffffffff)
2045 
2046 #ifndef __ASSEMBLY__
2047 /*
2048  * WARNING: The C register and register group struct declarations are provided for
2049  * convenience and illustrative purposes. They should, however, be used with
2050  * caution as the C language standard provides no guarantees about the alignment or
2051  * atomicity of device memory accesses. The recommended practice for coding device
2052  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2053  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2054  * alt_write_dword() functions for 64 bit registers.
2055  *
2056  * The struct declaration for register ALT_GIC_DIST_GICD_ISENABLER12.
2057  */
2058 struct ALT_GIC_DIST_GICD_ISENABLER12_s
2059 {
2060  volatile uint32_t fld : 32; /* Empty */
2061 };
2062 
2063 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISENABLER12. */
2064 typedef struct ALT_GIC_DIST_GICD_ISENABLER12_s ALT_GIC_DIST_GICD_ISENABLER12_t;
2065 #endif /* __ASSEMBLY__ */
2066 
2067 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER12 register. */
2068 #define ALT_GIC_DIST_GICD_ISENABLER12_RESET 0x00000000
2069 /* The byte offset of the ALT_GIC_DIST_GICD_ISENABLER12 register from the beginning of the component. */
2070 #define ALT_GIC_DIST_GICD_ISENABLER12_OFST 0x130
2071 
2072 /*
2073  * Register : GICD_ISENABLER13
2074  *
2075  * Interrupt Set-Enable Registers
2076  *
2077  * Register Layout
2078  *
2079  * Bits | Access | Reset | Description
2080  * :-------|:-------|:------|:------------
2081  * [31:0] | RW | 0x0 | Empty
2082  *
2083  */
2084 /*
2085  * Field : Empty - fld
2086  *
2087  * Placeholder
2088  *
2089  * Field Access Macros:
2090  *
2091  */
2092 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISENABLER13_FLD register field. */
2093 #define ALT_GIC_DIST_GICD_ISENABLER13_FLD_LSB 0
2094 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISENABLER13_FLD register field. */
2095 #define ALT_GIC_DIST_GICD_ISENABLER13_FLD_MSB 31
2096 /* The width in bits of the ALT_GIC_DIST_GICD_ISENABLER13_FLD register field. */
2097 #define ALT_GIC_DIST_GICD_ISENABLER13_FLD_WIDTH 32
2098 /* The mask used to set the ALT_GIC_DIST_GICD_ISENABLER13_FLD register field value. */
2099 #define ALT_GIC_DIST_GICD_ISENABLER13_FLD_SET_MSK 0xffffffff
2100 /* The mask used to clear the ALT_GIC_DIST_GICD_ISENABLER13_FLD register field value. */
2101 #define ALT_GIC_DIST_GICD_ISENABLER13_FLD_CLR_MSK 0x00000000
2102 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER13_FLD register field. */
2103 #define ALT_GIC_DIST_GICD_ISENABLER13_FLD_RESET 0x0
2104 /* Extracts the ALT_GIC_DIST_GICD_ISENABLER13_FLD field value from a register. */
2105 #define ALT_GIC_DIST_GICD_ISENABLER13_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2106 /* Produces a ALT_GIC_DIST_GICD_ISENABLER13_FLD register field value suitable for setting the register. */
2107 #define ALT_GIC_DIST_GICD_ISENABLER13_FLD_SET(value) (((value) << 0) & 0xffffffff)
2108 
2109 #ifndef __ASSEMBLY__
2110 /*
2111  * WARNING: The C register and register group struct declarations are provided for
2112  * convenience and illustrative purposes. They should, however, be used with
2113  * caution as the C language standard provides no guarantees about the alignment or
2114  * atomicity of device memory accesses. The recommended practice for coding device
2115  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2116  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2117  * alt_write_dword() functions for 64 bit registers.
2118  *
2119  * The struct declaration for register ALT_GIC_DIST_GICD_ISENABLER13.
2120  */
2121 struct ALT_GIC_DIST_GICD_ISENABLER13_s
2122 {
2123  volatile uint32_t fld : 32; /* Empty */
2124 };
2125 
2126 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISENABLER13. */
2127 typedef struct ALT_GIC_DIST_GICD_ISENABLER13_s ALT_GIC_DIST_GICD_ISENABLER13_t;
2128 #endif /* __ASSEMBLY__ */
2129 
2130 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER13 register. */
2131 #define ALT_GIC_DIST_GICD_ISENABLER13_RESET 0x00000000
2132 /* The byte offset of the ALT_GIC_DIST_GICD_ISENABLER13 register from the beginning of the component. */
2133 #define ALT_GIC_DIST_GICD_ISENABLER13_OFST 0x134
2134 
2135 /*
2136  * Register : GICD_ISENABLER14
2137  *
2138  * Interrupt Set-Enable Registers
2139  *
2140  * Register Layout
2141  *
2142  * Bits | Access | Reset | Description
2143  * :-------|:-------|:------|:------------
2144  * [31:0] | RW | 0x0 | Empty
2145  *
2146  */
2147 /*
2148  * Field : Empty - fld
2149  *
2150  * Placeholder
2151  *
2152  * Field Access Macros:
2153  *
2154  */
2155 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISENABLER14_FLD register field. */
2156 #define ALT_GIC_DIST_GICD_ISENABLER14_FLD_LSB 0
2157 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISENABLER14_FLD register field. */
2158 #define ALT_GIC_DIST_GICD_ISENABLER14_FLD_MSB 31
2159 /* The width in bits of the ALT_GIC_DIST_GICD_ISENABLER14_FLD register field. */
2160 #define ALT_GIC_DIST_GICD_ISENABLER14_FLD_WIDTH 32
2161 /* The mask used to set the ALT_GIC_DIST_GICD_ISENABLER14_FLD register field value. */
2162 #define ALT_GIC_DIST_GICD_ISENABLER14_FLD_SET_MSK 0xffffffff
2163 /* The mask used to clear the ALT_GIC_DIST_GICD_ISENABLER14_FLD register field value. */
2164 #define ALT_GIC_DIST_GICD_ISENABLER14_FLD_CLR_MSK 0x00000000
2165 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER14_FLD register field. */
2166 #define ALT_GIC_DIST_GICD_ISENABLER14_FLD_RESET 0x0
2167 /* Extracts the ALT_GIC_DIST_GICD_ISENABLER14_FLD field value from a register. */
2168 #define ALT_GIC_DIST_GICD_ISENABLER14_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2169 /* Produces a ALT_GIC_DIST_GICD_ISENABLER14_FLD register field value suitable for setting the register. */
2170 #define ALT_GIC_DIST_GICD_ISENABLER14_FLD_SET(value) (((value) << 0) & 0xffffffff)
2171 
2172 #ifndef __ASSEMBLY__
2173 /*
2174  * WARNING: The C register and register group struct declarations are provided for
2175  * convenience and illustrative purposes. They should, however, be used with
2176  * caution as the C language standard provides no guarantees about the alignment or
2177  * atomicity of device memory accesses. The recommended practice for coding device
2178  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2179  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2180  * alt_write_dword() functions for 64 bit registers.
2181  *
2182  * The struct declaration for register ALT_GIC_DIST_GICD_ISENABLER14.
2183  */
2184 struct ALT_GIC_DIST_GICD_ISENABLER14_s
2185 {
2186  volatile uint32_t fld : 32; /* Empty */
2187 };
2188 
2189 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISENABLER14. */
2190 typedef struct ALT_GIC_DIST_GICD_ISENABLER14_s ALT_GIC_DIST_GICD_ISENABLER14_t;
2191 #endif /* __ASSEMBLY__ */
2192 
2193 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER14 register. */
2194 #define ALT_GIC_DIST_GICD_ISENABLER14_RESET 0x00000000
2195 /* The byte offset of the ALT_GIC_DIST_GICD_ISENABLER14 register from the beginning of the component. */
2196 #define ALT_GIC_DIST_GICD_ISENABLER14_OFST 0x138
2197 
2198 /*
2199  * Register : GICD_ISENABLER15
2200  *
2201  * Interrupt Set-Enable Registers
2202  *
2203  * Register Layout
2204  *
2205  * Bits | Access | Reset | Description
2206  * :-------|:-------|:------|:------------
2207  * [31:0] | RW | 0x0 | Empty
2208  *
2209  */
2210 /*
2211  * Field : Empty - fld
2212  *
2213  * Placeholder
2214  *
2215  * Field Access Macros:
2216  *
2217  */
2218 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISENABLER15_FLD register field. */
2219 #define ALT_GIC_DIST_GICD_ISENABLER15_FLD_LSB 0
2220 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISENABLER15_FLD register field. */
2221 #define ALT_GIC_DIST_GICD_ISENABLER15_FLD_MSB 31
2222 /* The width in bits of the ALT_GIC_DIST_GICD_ISENABLER15_FLD register field. */
2223 #define ALT_GIC_DIST_GICD_ISENABLER15_FLD_WIDTH 32
2224 /* The mask used to set the ALT_GIC_DIST_GICD_ISENABLER15_FLD register field value. */
2225 #define ALT_GIC_DIST_GICD_ISENABLER15_FLD_SET_MSK 0xffffffff
2226 /* The mask used to clear the ALT_GIC_DIST_GICD_ISENABLER15_FLD register field value. */
2227 #define ALT_GIC_DIST_GICD_ISENABLER15_FLD_CLR_MSK 0x00000000
2228 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER15_FLD register field. */
2229 #define ALT_GIC_DIST_GICD_ISENABLER15_FLD_RESET 0x0
2230 /* Extracts the ALT_GIC_DIST_GICD_ISENABLER15_FLD field value from a register. */
2231 #define ALT_GIC_DIST_GICD_ISENABLER15_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2232 /* Produces a ALT_GIC_DIST_GICD_ISENABLER15_FLD register field value suitable for setting the register. */
2233 #define ALT_GIC_DIST_GICD_ISENABLER15_FLD_SET(value) (((value) << 0) & 0xffffffff)
2234 
2235 #ifndef __ASSEMBLY__
2236 /*
2237  * WARNING: The C register and register group struct declarations are provided for
2238  * convenience and illustrative purposes. They should, however, be used with
2239  * caution as the C language standard provides no guarantees about the alignment or
2240  * atomicity of device memory accesses. The recommended practice for coding device
2241  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2242  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2243  * alt_write_dword() functions for 64 bit registers.
2244  *
2245  * The struct declaration for register ALT_GIC_DIST_GICD_ISENABLER15.
2246  */
2247 struct ALT_GIC_DIST_GICD_ISENABLER15_s
2248 {
2249  volatile uint32_t fld : 32; /* Empty */
2250 };
2251 
2252 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISENABLER15. */
2253 typedef struct ALT_GIC_DIST_GICD_ISENABLER15_s ALT_GIC_DIST_GICD_ISENABLER15_t;
2254 #endif /* __ASSEMBLY__ */
2255 
2256 /* The reset value of the ALT_GIC_DIST_GICD_ISENABLER15 register. */
2257 #define ALT_GIC_DIST_GICD_ISENABLER15_RESET 0x00000000
2258 /* The byte offset of the ALT_GIC_DIST_GICD_ISENABLER15 register from the beginning of the component. */
2259 #define ALT_GIC_DIST_GICD_ISENABLER15_OFST 0x13c
2260 
2261 /*
2262  * Register : GICD_ICENABLER0
2263  *
2264  * Interrupt Clear-Enable Registers
2265  *
2266  * Register Layout
2267  *
2268  * Bits | Access | Reset | Description
2269  * :-------|:-------|:--------|:------------
2270  * [31:0] | RW | Unknown | Empty
2271  *
2272  */
2273 /*
2274  * Field : Empty - fld
2275  *
2276  * Placeholder
2277  *
2278  * Field Access Macros:
2279  *
2280  */
2281 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICENABLER0_FLD register field. */
2282 #define ALT_GIC_DIST_GICD_ICENABLER0_FLD_LSB 0
2283 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICENABLER0_FLD register field. */
2284 #define ALT_GIC_DIST_GICD_ICENABLER0_FLD_MSB 31
2285 /* The width in bits of the ALT_GIC_DIST_GICD_ICENABLER0_FLD register field. */
2286 #define ALT_GIC_DIST_GICD_ICENABLER0_FLD_WIDTH 32
2287 /* The mask used to set the ALT_GIC_DIST_GICD_ICENABLER0_FLD register field value. */
2288 #define ALT_GIC_DIST_GICD_ICENABLER0_FLD_SET_MSK 0xffffffff
2289 /* The mask used to clear the ALT_GIC_DIST_GICD_ICENABLER0_FLD register field value. */
2290 #define ALT_GIC_DIST_GICD_ICENABLER0_FLD_CLR_MSK 0x00000000
2291 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER0_FLD register field is UNKNOWN. */
2292 #define ALT_GIC_DIST_GICD_ICENABLER0_FLD_RESET 0x0
2293 /* Extracts the ALT_GIC_DIST_GICD_ICENABLER0_FLD field value from a register. */
2294 #define ALT_GIC_DIST_GICD_ICENABLER0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2295 /* Produces a ALT_GIC_DIST_GICD_ICENABLER0_FLD register field value suitable for setting the register. */
2296 #define ALT_GIC_DIST_GICD_ICENABLER0_FLD_SET(value) (((value) << 0) & 0xffffffff)
2297 
2298 #ifndef __ASSEMBLY__
2299 /*
2300  * WARNING: The C register and register group struct declarations are provided for
2301  * convenience and illustrative purposes. They should, however, be used with
2302  * caution as the C language standard provides no guarantees about the alignment or
2303  * atomicity of device memory accesses. The recommended practice for coding device
2304  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2305  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2306  * alt_write_dword() functions for 64 bit registers.
2307  *
2308  * The struct declaration for register ALT_GIC_DIST_GICD_ICENABLER0.
2309  */
2310 struct ALT_GIC_DIST_GICD_ICENABLER0_s
2311 {
2312  volatile uint32_t fld : 32; /* Empty */
2313 };
2314 
2315 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICENABLER0. */
2316 typedef struct ALT_GIC_DIST_GICD_ICENABLER0_s ALT_GIC_DIST_GICD_ICENABLER0_t;
2317 #endif /* __ASSEMBLY__ */
2318 
2319 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER0 register. */
2320 #define ALT_GIC_DIST_GICD_ICENABLER0_RESET 0x0000ffff
2321 /* The byte offset of the ALT_GIC_DIST_GICD_ICENABLER0 register from the beginning of the component. */
2322 #define ALT_GIC_DIST_GICD_ICENABLER0_OFST 0x180
2323 
2324 /*
2325  * Register : GICD_ICENABLER1
2326  *
2327  * Interrupt Clear-Enable Registers
2328  *
2329  * Register Layout
2330  *
2331  * Bits | Access | Reset | Description
2332  * :-------|:-------|:------|:------------
2333  * [31:0] | RW | 0x0 | Empty
2334  *
2335  */
2336 /*
2337  * Field : Empty - fld
2338  *
2339  * Placeholder
2340  *
2341  * Field Access Macros:
2342  *
2343  */
2344 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICENABLER1_FLD register field. */
2345 #define ALT_GIC_DIST_GICD_ICENABLER1_FLD_LSB 0
2346 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICENABLER1_FLD register field. */
2347 #define ALT_GIC_DIST_GICD_ICENABLER1_FLD_MSB 31
2348 /* The width in bits of the ALT_GIC_DIST_GICD_ICENABLER1_FLD register field. */
2349 #define ALT_GIC_DIST_GICD_ICENABLER1_FLD_WIDTH 32
2350 /* The mask used to set the ALT_GIC_DIST_GICD_ICENABLER1_FLD register field value. */
2351 #define ALT_GIC_DIST_GICD_ICENABLER1_FLD_SET_MSK 0xffffffff
2352 /* The mask used to clear the ALT_GIC_DIST_GICD_ICENABLER1_FLD register field value. */
2353 #define ALT_GIC_DIST_GICD_ICENABLER1_FLD_CLR_MSK 0x00000000
2354 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER1_FLD register field. */
2355 #define ALT_GIC_DIST_GICD_ICENABLER1_FLD_RESET 0x0
2356 /* Extracts the ALT_GIC_DIST_GICD_ICENABLER1_FLD field value from a register. */
2357 #define ALT_GIC_DIST_GICD_ICENABLER1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2358 /* Produces a ALT_GIC_DIST_GICD_ICENABLER1_FLD register field value suitable for setting the register. */
2359 #define ALT_GIC_DIST_GICD_ICENABLER1_FLD_SET(value) (((value) << 0) & 0xffffffff)
2360 
2361 #ifndef __ASSEMBLY__
2362 /*
2363  * WARNING: The C register and register group struct declarations are provided for
2364  * convenience and illustrative purposes. They should, however, be used with
2365  * caution as the C language standard provides no guarantees about the alignment or
2366  * atomicity of device memory accesses. The recommended practice for coding device
2367  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2368  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2369  * alt_write_dword() functions for 64 bit registers.
2370  *
2371  * The struct declaration for register ALT_GIC_DIST_GICD_ICENABLER1.
2372  */
2373 struct ALT_GIC_DIST_GICD_ICENABLER1_s
2374 {
2375  volatile uint32_t fld : 32; /* Empty */
2376 };
2377 
2378 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICENABLER1. */
2379 typedef struct ALT_GIC_DIST_GICD_ICENABLER1_s ALT_GIC_DIST_GICD_ICENABLER1_t;
2380 #endif /* __ASSEMBLY__ */
2381 
2382 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER1 register. */
2383 #define ALT_GIC_DIST_GICD_ICENABLER1_RESET 0x00000000
2384 /* The byte offset of the ALT_GIC_DIST_GICD_ICENABLER1 register from the beginning of the component. */
2385 #define ALT_GIC_DIST_GICD_ICENABLER1_OFST 0x184
2386 
2387 /*
2388  * Register : GICD_ICENABLER2
2389  *
2390  * Interrupt Clear-Enable Registers
2391  *
2392  * Register Layout
2393  *
2394  * Bits | Access | Reset | Description
2395  * :-------|:-------|:------|:------------
2396  * [31:0] | RW | 0x0 | Empty
2397  *
2398  */
2399 /*
2400  * Field : Empty - fld
2401  *
2402  * Placeholder
2403  *
2404  * Field Access Macros:
2405  *
2406  */
2407 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICENABLER2_FLD register field. */
2408 #define ALT_GIC_DIST_GICD_ICENABLER2_FLD_LSB 0
2409 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICENABLER2_FLD register field. */
2410 #define ALT_GIC_DIST_GICD_ICENABLER2_FLD_MSB 31
2411 /* The width in bits of the ALT_GIC_DIST_GICD_ICENABLER2_FLD register field. */
2412 #define ALT_GIC_DIST_GICD_ICENABLER2_FLD_WIDTH 32
2413 /* The mask used to set the ALT_GIC_DIST_GICD_ICENABLER2_FLD register field value. */
2414 #define ALT_GIC_DIST_GICD_ICENABLER2_FLD_SET_MSK 0xffffffff
2415 /* The mask used to clear the ALT_GIC_DIST_GICD_ICENABLER2_FLD register field value. */
2416 #define ALT_GIC_DIST_GICD_ICENABLER2_FLD_CLR_MSK 0x00000000
2417 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER2_FLD register field. */
2418 #define ALT_GIC_DIST_GICD_ICENABLER2_FLD_RESET 0x0
2419 /* Extracts the ALT_GIC_DIST_GICD_ICENABLER2_FLD field value from a register. */
2420 #define ALT_GIC_DIST_GICD_ICENABLER2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2421 /* Produces a ALT_GIC_DIST_GICD_ICENABLER2_FLD register field value suitable for setting the register. */
2422 #define ALT_GIC_DIST_GICD_ICENABLER2_FLD_SET(value) (((value) << 0) & 0xffffffff)
2423 
2424 #ifndef __ASSEMBLY__
2425 /*
2426  * WARNING: The C register and register group struct declarations are provided for
2427  * convenience and illustrative purposes. They should, however, be used with
2428  * caution as the C language standard provides no guarantees about the alignment or
2429  * atomicity of device memory accesses. The recommended practice for coding device
2430  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2431  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2432  * alt_write_dword() functions for 64 bit registers.
2433  *
2434  * The struct declaration for register ALT_GIC_DIST_GICD_ICENABLER2.
2435  */
2436 struct ALT_GIC_DIST_GICD_ICENABLER2_s
2437 {
2438  volatile uint32_t fld : 32; /* Empty */
2439 };
2440 
2441 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICENABLER2. */
2442 typedef struct ALT_GIC_DIST_GICD_ICENABLER2_s ALT_GIC_DIST_GICD_ICENABLER2_t;
2443 #endif /* __ASSEMBLY__ */
2444 
2445 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER2 register. */
2446 #define ALT_GIC_DIST_GICD_ICENABLER2_RESET 0x00000000
2447 /* The byte offset of the ALT_GIC_DIST_GICD_ICENABLER2 register from the beginning of the component. */
2448 #define ALT_GIC_DIST_GICD_ICENABLER2_OFST 0x188
2449 
2450 /*
2451  * Register : GICD_ICENABLER3
2452  *
2453  * Interrupt Clear-Enable Registers
2454  *
2455  * Register Layout
2456  *
2457  * Bits | Access | Reset | Description
2458  * :-------|:-------|:------|:------------
2459  * [31:0] | RW | 0x0 | Empty
2460  *
2461  */
2462 /*
2463  * Field : Empty - fld
2464  *
2465  * Placeholder
2466  *
2467  * Field Access Macros:
2468  *
2469  */
2470 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICENABLER3_FLD register field. */
2471 #define ALT_GIC_DIST_GICD_ICENABLER3_FLD_LSB 0
2472 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICENABLER3_FLD register field. */
2473 #define ALT_GIC_DIST_GICD_ICENABLER3_FLD_MSB 31
2474 /* The width in bits of the ALT_GIC_DIST_GICD_ICENABLER3_FLD register field. */
2475 #define ALT_GIC_DIST_GICD_ICENABLER3_FLD_WIDTH 32
2476 /* The mask used to set the ALT_GIC_DIST_GICD_ICENABLER3_FLD register field value. */
2477 #define ALT_GIC_DIST_GICD_ICENABLER3_FLD_SET_MSK 0xffffffff
2478 /* The mask used to clear the ALT_GIC_DIST_GICD_ICENABLER3_FLD register field value. */
2479 #define ALT_GIC_DIST_GICD_ICENABLER3_FLD_CLR_MSK 0x00000000
2480 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER3_FLD register field. */
2481 #define ALT_GIC_DIST_GICD_ICENABLER3_FLD_RESET 0x0
2482 /* Extracts the ALT_GIC_DIST_GICD_ICENABLER3_FLD field value from a register. */
2483 #define ALT_GIC_DIST_GICD_ICENABLER3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2484 /* Produces a ALT_GIC_DIST_GICD_ICENABLER3_FLD register field value suitable for setting the register. */
2485 #define ALT_GIC_DIST_GICD_ICENABLER3_FLD_SET(value) (((value) << 0) & 0xffffffff)
2486 
2487 #ifndef __ASSEMBLY__
2488 /*
2489  * WARNING: The C register and register group struct declarations are provided for
2490  * convenience and illustrative purposes. They should, however, be used with
2491  * caution as the C language standard provides no guarantees about the alignment or
2492  * atomicity of device memory accesses. The recommended practice for coding device
2493  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2494  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2495  * alt_write_dword() functions for 64 bit registers.
2496  *
2497  * The struct declaration for register ALT_GIC_DIST_GICD_ICENABLER3.
2498  */
2499 struct ALT_GIC_DIST_GICD_ICENABLER3_s
2500 {
2501  volatile uint32_t fld : 32; /* Empty */
2502 };
2503 
2504 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICENABLER3. */
2505 typedef struct ALT_GIC_DIST_GICD_ICENABLER3_s ALT_GIC_DIST_GICD_ICENABLER3_t;
2506 #endif /* __ASSEMBLY__ */
2507 
2508 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER3 register. */
2509 #define ALT_GIC_DIST_GICD_ICENABLER3_RESET 0x00000000
2510 /* The byte offset of the ALT_GIC_DIST_GICD_ICENABLER3 register from the beginning of the component. */
2511 #define ALT_GIC_DIST_GICD_ICENABLER3_OFST 0x18c
2512 
2513 /*
2514  * Register : GICD_ICENABLER4
2515  *
2516  * Interrupt Clear-Enable Registers
2517  *
2518  * Register Layout
2519  *
2520  * Bits | Access | Reset | Description
2521  * :-------|:-------|:------|:------------
2522  * [31:0] | RW | 0x0 | Empty
2523  *
2524  */
2525 /*
2526  * Field : Empty - fld
2527  *
2528  * Placeholder
2529  *
2530  * Field Access Macros:
2531  *
2532  */
2533 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICENABLER4_FLD register field. */
2534 #define ALT_GIC_DIST_GICD_ICENABLER4_FLD_LSB 0
2535 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICENABLER4_FLD register field. */
2536 #define ALT_GIC_DIST_GICD_ICENABLER4_FLD_MSB 31
2537 /* The width in bits of the ALT_GIC_DIST_GICD_ICENABLER4_FLD register field. */
2538 #define ALT_GIC_DIST_GICD_ICENABLER4_FLD_WIDTH 32
2539 /* The mask used to set the ALT_GIC_DIST_GICD_ICENABLER4_FLD register field value. */
2540 #define ALT_GIC_DIST_GICD_ICENABLER4_FLD_SET_MSK 0xffffffff
2541 /* The mask used to clear the ALT_GIC_DIST_GICD_ICENABLER4_FLD register field value. */
2542 #define ALT_GIC_DIST_GICD_ICENABLER4_FLD_CLR_MSK 0x00000000
2543 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER4_FLD register field. */
2544 #define ALT_GIC_DIST_GICD_ICENABLER4_FLD_RESET 0x0
2545 /* Extracts the ALT_GIC_DIST_GICD_ICENABLER4_FLD field value from a register. */
2546 #define ALT_GIC_DIST_GICD_ICENABLER4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2547 /* Produces a ALT_GIC_DIST_GICD_ICENABLER4_FLD register field value suitable for setting the register. */
2548 #define ALT_GIC_DIST_GICD_ICENABLER4_FLD_SET(value) (((value) << 0) & 0xffffffff)
2549 
2550 #ifndef __ASSEMBLY__
2551 /*
2552  * WARNING: The C register and register group struct declarations are provided for
2553  * convenience and illustrative purposes. They should, however, be used with
2554  * caution as the C language standard provides no guarantees about the alignment or
2555  * atomicity of device memory accesses. The recommended practice for coding device
2556  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2557  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2558  * alt_write_dword() functions for 64 bit registers.
2559  *
2560  * The struct declaration for register ALT_GIC_DIST_GICD_ICENABLER4.
2561  */
2562 struct ALT_GIC_DIST_GICD_ICENABLER4_s
2563 {
2564  volatile uint32_t fld : 32; /* Empty */
2565 };
2566 
2567 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICENABLER4. */
2568 typedef struct ALT_GIC_DIST_GICD_ICENABLER4_s ALT_GIC_DIST_GICD_ICENABLER4_t;
2569 #endif /* __ASSEMBLY__ */
2570 
2571 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER4 register. */
2572 #define ALT_GIC_DIST_GICD_ICENABLER4_RESET 0x00000000
2573 /* The byte offset of the ALT_GIC_DIST_GICD_ICENABLER4 register from the beginning of the component. */
2574 #define ALT_GIC_DIST_GICD_ICENABLER4_OFST 0x190
2575 
2576 /*
2577  * Register : GICD_ICENABLER5
2578  *
2579  * Interrupt Clear-Enable Registers
2580  *
2581  * Register Layout
2582  *
2583  * Bits | Access | Reset | Description
2584  * :-------|:-------|:------|:------------
2585  * [31:0] | RW | 0x0 | Empty
2586  *
2587  */
2588 /*
2589  * Field : Empty - fld
2590  *
2591  * Placeholder
2592  *
2593  * Field Access Macros:
2594  *
2595  */
2596 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICENABLER5_FLD register field. */
2597 #define ALT_GIC_DIST_GICD_ICENABLER5_FLD_LSB 0
2598 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICENABLER5_FLD register field. */
2599 #define ALT_GIC_DIST_GICD_ICENABLER5_FLD_MSB 31
2600 /* The width in bits of the ALT_GIC_DIST_GICD_ICENABLER5_FLD register field. */
2601 #define ALT_GIC_DIST_GICD_ICENABLER5_FLD_WIDTH 32
2602 /* The mask used to set the ALT_GIC_DIST_GICD_ICENABLER5_FLD register field value. */
2603 #define ALT_GIC_DIST_GICD_ICENABLER5_FLD_SET_MSK 0xffffffff
2604 /* The mask used to clear the ALT_GIC_DIST_GICD_ICENABLER5_FLD register field value. */
2605 #define ALT_GIC_DIST_GICD_ICENABLER5_FLD_CLR_MSK 0x00000000
2606 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER5_FLD register field. */
2607 #define ALT_GIC_DIST_GICD_ICENABLER5_FLD_RESET 0x0
2608 /* Extracts the ALT_GIC_DIST_GICD_ICENABLER5_FLD field value from a register. */
2609 #define ALT_GIC_DIST_GICD_ICENABLER5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2610 /* Produces a ALT_GIC_DIST_GICD_ICENABLER5_FLD register field value suitable for setting the register. */
2611 #define ALT_GIC_DIST_GICD_ICENABLER5_FLD_SET(value) (((value) << 0) & 0xffffffff)
2612 
2613 #ifndef __ASSEMBLY__
2614 /*
2615  * WARNING: The C register and register group struct declarations are provided for
2616  * convenience and illustrative purposes. They should, however, be used with
2617  * caution as the C language standard provides no guarantees about the alignment or
2618  * atomicity of device memory accesses. The recommended practice for coding device
2619  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2620  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2621  * alt_write_dword() functions for 64 bit registers.
2622  *
2623  * The struct declaration for register ALT_GIC_DIST_GICD_ICENABLER5.
2624  */
2625 struct ALT_GIC_DIST_GICD_ICENABLER5_s
2626 {
2627  volatile uint32_t fld : 32; /* Empty */
2628 };
2629 
2630 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICENABLER5. */
2631 typedef struct ALT_GIC_DIST_GICD_ICENABLER5_s ALT_GIC_DIST_GICD_ICENABLER5_t;
2632 #endif /* __ASSEMBLY__ */
2633 
2634 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER5 register. */
2635 #define ALT_GIC_DIST_GICD_ICENABLER5_RESET 0x00000000
2636 /* The byte offset of the ALT_GIC_DIST_GICD_ICENABLER5 register from the beginning of the component. */
2637 #define ALT_GIC_DIST_GICD_ICENABLER5_OFST 0x194
2638 
2639 /*
2640  * Register : GICD_ICENABLER6
2641  *
2642  * Interrupt Clear-Enable Registers
2643  *
2644  * Register Layout
2645  *
2646  * Bits | Access | Reset | Description
2647  * :-------|:-------|:------|:------------
2648  * [31:0] | RW | 0x0 | Empty
2649  *
2650  */
2651 /*
2652  * Field : Empty - fld
2653  *
2654  * Placeholder
2655  *
2656  * Field Access Macros:
2657  *
2658  */
2659 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICENABLER6_FLD register field. */
2660 #define ALT_GIC_DIST_GICD_ICENABLER6_FLD_LSB 0
2661 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICENABLER6_FLD register field. */
2662 #define ALT_GIC_DIST_GICD_ICENABLER6_FLD_MSB 31
2663 /* The width in bits of the ALT_GIC_DIST_GICD_ICENABLER6_FLD register field. */
2664 #define ALT_GIC_DIST_GICD_ICENABLER6_FLD_WIDTH 32
2665 /* The mask used to set the ALT_GIC_DIST_GICD_ICENABLER6_FLD register field value. */
2666 #define ALT_GIC_DIST_GICD_ICENABLER6_FLD_SET_MSK 0xffffffff
2667 /* The mask used to clear the ALT_GIC_DIST_GICD_ICENABLER6_FLD register field value. */
2668 #define ALT_GIC_DIST_GICD_ICENABLER6_FLD_CLR_MSK 0x00000000
2669 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER6_FLD register field. */
2670 #define ALT_GIC_DIST_GICD_ICENABLER6_FLD_RESET 0x0
2671 /* Extracts the ALT_GIC_DIST_GICD_ICENABLER6_FLD field value from a register. */
2672 #define ALT_GIC_DIST_GICD_ICENABLER6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2673 /* Produces a ALT_GIC_DIST_GICD_ICENABLER6_FLD register field value suitable for setting the register. */
2674 #define ALT_GIC_DIST_GICD_ICENABLER6_FLD_SET(value) (((value) << 0) & 0xffffffff)
2675 
2676 #ifndef __ASSEMBLY__
2677 /*
2678  * WARNING: The C register and register group struct declarations are provided for
2679  * convenience and illustrative purposes. They should, however, be used with
2680  * caution as the C language standard provides no guarantees about the alignment or
2681  * atomicity of device memory accesses. The recommended practice for coding device
2682  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2683  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2684  * alt_write_dword() functions for 64 bit registers.
2685  *
2686  * The struct declaration for register ALT_GIC_DIST_GICD_ICENABLER6.
2687  */
2688 struct ALT_GIC_DIST_GICD_ICENABLER6_s
2689 {
2690  volatile uint32_t fld : 32; /* Empty */
2691 };
2692 
2693 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICENABLER6. */
2694 typedef struct ALT_GIC_DIST_GICD_ICENABLER6_s ALT_GIC_DIST_GICD_ICENABLER6_t;
2695 #endif /* __ASSEMBLY__ */
2696 
2697 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER6 register. */
2698 #define ALT_GIC_DIST_GICD_ICENABLER6_RESET 0x00000000
2699 /* The byte offset of the ALT_GIC_DIST_GICD_ICENABLER6 register from the beginning of the component. */
2700 #define ALT_GIC_DIST_GICD_ICENABLER6_OFST 0x198
2701 
2702 /*
2703  * Register : GICD_ICENABLER7
2704  *
2705  * Interrupt Clear-Enable Registers
2706  *
2707  * Register Layout
2708  *
2709  * Bits | Access | Reset | Description
2710  * :-------|:-------|:------|:------------
2711  * [31:0] | RW | 0x0 | Empty
2712  *
2713  */
2714 /*
2715  * Field : Empty - fld
2716  *
2717  * Placeholder
2718  *
2719  * Field Access Macros:
2720  *
2721  */
2722 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICENABLER7_FLD register field. */
2723 #define ALT_GIC_DIST_GICD_ICENABLER7_FLD_LSB 0
2724 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICENABLER7_FLD register field. */
2725 #define ALT_GIC_DIST_GICD_ICENABLER7_FLD_MSB 31
2726 /* The width in bits of the ALT_GIC_DIST_GICD_ICENABLER7_FLD register field. */
2727 #define ALT_GIC_DIST_GICD_ICENABLER7_FLD_WIDTH 32
2728 /* The mask used to set the ALT_GIC_DIST_GICD_ICENABLER7_FLD register field value. */
2729 #define ALT_GIC_DIST_GICD_ICENABLER7_FLD_SET_MSK 0xffffffff
2730 /* The mask used to clear the ALT_GIC_DIST_GICD_ICENABLER7_FLD register field value. */
2731 #define ALT_GIC_DIST_GICD_ICENABLER7_FLD_CLR_MSK 0x00000000
2732 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER7_FLD register field. */
2733 #define ALT_GIC_DIST_GICD_ICENABLER7_FLD_RESET 0x0
2734 /* Extracts the ALT_GIC_DIST_GICD_ICENABLER7_FLD field value from a register. */
2735 #define ALT_GIC_DIST_GICD_ICENABLER7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2736 /* Produces a ALT_GIC_DIST_GICD_ICENABLER7_FLD register field value suitable for setting the register. */
2737 #define ALT_GIC_DIST_GICD_ICENABLER7_FLD_SET(value) (((value) << 0) & 0xffffffff)
2738 
2739 #ifndef __ASSEMBLY__
2740 /*
2741  * WARNING: The C register and register group struct declarations are provided for
2742  * convenience and illustrative purposes. They should, however, be used with
2743  * caution as the C language standard provides no guarantees about the alignment or
2744  * atomicity of device memory accesses. The recommended practice for coding device
2745  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2746  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2747  * alt_write_dword() functions for 64 bit registers.
2748  *
2749  * The struct declaration for register ALT_GIC_DIST_GICD_ICENABLER7.
2750  */
2751 struct ALT_GIC_DIST_GICD_ICENABLER7_s
2752 {
2753  volatile uint32_t fld : 32; /* Empty */
2754 };
2755 
2756 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICENABLER7. */
2757 typedef struct ALT_GIC_DIST_GICD_ICENABLER7_s ALT_GIC_DIST_GICD_ICENABLER7_t;
2758 #endif /* __ASSEMBLY__ */
2759 
2760 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER7 register. */
2761 #define ALT_GIC_DIST_GICD_ICENABLER7_RESET 0x00000000
2762 /* The byte offset of the ALT_GIC_DIST_GICD_ICENABLER7 register from the beginning of the component. */
2763 #define ALT_GIC_DIST_GICD_ICENABLER7_OFST 0x19c
2764 
2765 /*
2766  * Register : GICD_ICENABLER8
2767  *
2768  * Interrupt Clear-Enable Registers
2769  *
2770  * Register Layout
2771  *
2772  * Bits | Access | Reset | Description
2773  * :-------|:-------|:------|:------------
2774  * [31:0] | RW | 0x0 | Empty
2775  *
2776  */
2777 /*
2778  * Field : Empty - fld
2779  *
2780  * Placeholder
2781  *
2782  * Field Access Macros:
2783  *
2784  */
2785 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICENABLER8_FLD register field. */
2786 #define ALT_GIC_DIST_GICD_ICENABLER8_FLD_LSB 0
2787 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICENABLER8_FLD register field. */
2788 #define ALT_GIC_DIST_GICD_ICENABLER8_FLD_MSB 31
2789 /* The width in bits of the ALT_GIC_DIST_GICD_ICENABLER8_FLD register field. */
2790 #define ALT_GIC_DIST_GICD_ICENABLER8_FLD_WIDTH 32
2791 /* The mask used to set the ALT_GIC_DIST_GICD_ICENABLER8_FLD register field value. */
2792 #define ALT_GIC_DIST_GICD_ICENABLER8_FLD_SET_MSK 0xffffffff
2793 /* The mask used to clear the ALT_GIC_DIST_GICD_ICENABLER8_FLD register field value. */
2794 #define ALT_GIC_DIST_GICD_ICENABLER8_FLD_CLR_MSK 0x00000000
2795 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER8_FLD register field. */
2796 #define ALT_GIC_DIST_GICD_ICENABLER8_FLD_RESET 0x0
2797 /* Extracts the ALT_GIC_DIST_GICD_ICENABLER8_FLD field value from a register. */
2798 #define ALT_GIC_DIST_GICD_ICENABLER8_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2799 /* Produces a ALT_GIC_DIST_GICD_ICENABLER8_FLD register field value suitable for setting the register. */
2800 #define ALT_GIC_DIST_GICD_ICENABLER8_FLD_SET(value) (((value) << 0) & 0xffffffff)
2801 
2802 #ifndef __ASSEMBLY__
2803 /*
2804  * WARNING: The C register and register group struct declarations are provided for
2805  * convenience and illustrative purposes. They should, however, be used with
2806  * caution as the C language standard provides no guarantees about the alignment or
2807  * atomicity of device memory accesses. The recommended practice for coding device
2808  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2809  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2810  * alt_write_dword() functions for 64 bit registers.
2811  *
2812  * The struct declaration for register ALT_GIC_DIST_GICD_ICENABLER8.
2813  */
2814 struct ALT_GIC_DIST_GICD_ICENABLER8_s
2815 {
2816  volatile uint32_t fld : 32; /* Empty */
2817 };
2818 
2819 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICENABLER8. */
2820 typedef struct ALT_GIC_DIST_GICD_ICENABLER8_s ALT_GIC_DIST_GICD_ICENABLER8_t;
2821 #endif /* __ASSEMBLY__ */
2822 
2823 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER8 register. */
2824 #define ALT_GIC_DIST_GICD_ICENABLER8_RESET 0x00000000
2825 /* The byte offset of the ALT_GIC_DIST_GICD_ICENABLER8 register from the beginning of the component. */
2826 #define ALT_GIC_DIST_GICD_ICENABLER8_OFST 0x1a0
2827 
2828 /*
2829  * Register : GICD_ICENABLER9
2830  *
2831  * Interrupt Clear-Enable Registers
2832  *
2833  * Register Layout
2834  *
2835  * Bits | Access | Reset | Description
2836  * :-------|:-------|:------|:------------
2837  * [31:0] | RW | 0x0 | Empty
2838  *
2839  */
2840 /*
2841  * Field : Empty - fld
2842  *
2843  * Placeholder
2844  *
2845  * Field Access Macros:
2846  *
2847  */
2848 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICENABLER9_FLD register field. */
2849 #define ALT_GIC_DIST_GICD_ICENABLER9_FLD_LSB 0
2850 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICENABLER9_FLD register field. */
2851 #define ALT_GIC_DIST_GICD_ICENABLER9_FLD_MSB 31
2852 /* The width in bits of the ALT_GIC_DIST_GICD_ICENABLER9_FLD register field. */
2853 #define ALT_GIC_DIST_GICD_ICENABLER9_FLD_WIDTH 32
2854 /* The mask used to set the ALT_GIC_DIST_GICD_ICENABLER9_FLD register field value. */
2855 #define ALT_GIC_DIST_GICD_ICENABLER9_FLD_SET_MSK 0xffffffff
2856 /* The mask used to clear the ALT_GIC_DIST_GICD_ICENABLER9_FLD register field value. */
2857 #define ALT_GIC_DIST_GICD_ICENABLER9_FLD_CLR_MSK 0x00000000
2858 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER9_FLD register field. */
2859 #define ALT_GIC_DIST_GICD_ICENABLER9_FLD_RESET 0x0
2860 /* Extracts the ALT_GIC_DIST_GICD_ICENABLER9_FLD field value from a register. */
2861 #define ALT_GIC_DIST_GICD_ICENABLER9_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2862 /* Produces a ALT_GIC_DIST_GICD_ICENABLER9_FLD register field value suitable for setting the register. */
2863 #define ALT_GIC_DIST_GICD_ICENABLER9_FLD_SET(value) (((value) << 0) & 0xffffffff)
2864 
2865 #ifndef __ASSEMBLY__
2866 /*
2867  * WARNING: The C register and register group struct declarations are provided for
2868  * convenience and illustrative purposes. They should, however, be used with
2869  * caution as the C language standard provides no guarantees about the alignment or
2870  * atomicity of device memory accesses. The recommended practice for coding device
2871  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2872  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2873  * alt_write_dword() functions for 64 bit registers.
2874  *
2875  * The struct declaration for register ALT_GIC_DIST_GICD_ICENABLER9.
2876  */
2877 struct ALT_GIC_DIST_GICD_ICENABLER9_s
2878 {
2879  volatile uint32_t fld : 32; /* Empty */
2880 };
2881 
2882 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICENABLER9. */
2883 typedef struct ALT_GIC_DIST_GICD_ICENABLER9_s ALT_GIC_DIST_GICD_ICENABLER9_t;
2884 #endif /* __ASSEMBLY__ */
2885 
2886 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER9 register. */
2887 #define ALT_GIC_DIST_GICD_ICENABLER9_RESET 0x00000000
2888 /* The byte offset of the ALT_GIC_DIST_GICD_ICENABLER9 register from the beginning of the component. */
2889 #define ALT_GIC_DIST_GICD_ICENABLER9_OFST 0x1a4
2890 
2891 /*
2892  * Register : GICD_ICENABLER10
2893  *
2894  * Interrupt Clear-Enable Registers
2895  *
2896  * Register Layout
2897  *
2898  * Bits | Access | Reset | Description
2899  * :-------|:-------|:------|:------------
2900  * [31:0] | RW | 0x0 | Empty
2901  *
2902  */
2903 /*
2904  * Field : Empty - fld
2905  *
2906  * Placeholder
2907  *
2908  * Field Access Macros:
2909  *
2910  */
2911 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICENABLER10_FLD register field. */
2912 #define ALT_GIC_DIST_GICD_ICENABLER10_FLD_LSB 0
2913 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICENABLER10_FLD register field. */
2914 #define ALT_GIC_DIST_GICD_ICENABLER10_FLD_MSB 31
2915 /* The width in bits of the ALT_GIC_DIST_GICD_ICENABLER10_FLD register field. */
2916 #define ALT_GIC_DIST_GICD_ICENABLER10_FLD_WIDTH 32
2917 /* The mask used to set the ALT_GIC_DIST_GICD_ICENABLER10_FLD register field value. */
2918 #define ALT_GIC_DIST_GICD_ICENABLER10_FLD_SET_MSK 0xffffffff
2919 /* The mask used to clear the ALT_GIC_DIST_GICD_ICENABLER10_FLD register field value. */
2920 #define ALT_GIC_DIST_GICD_ICENABLER10_FLD_CLR_MSK 0x00000000
2921 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER10_FLD register field. */
2922 #define ALT_GIC_DIST_GICD_ICENABLER10_FLD_RESET 0x0
2923 /* Extracts the ALT_GIC_DIST_GICD_ICENABLER10_FLD field value from a register. */
2924 #define ALT_GIC_DIST_GICD_ICENABLER10_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2925 /* Produces a ALT_GIC_DIST_GICD_ICENABLER10_FLD register field value suitable for setting the register. */
2926 #define ALT_GIC_DIST_GICD_ICENABLER10_FLD_SET(value) (((value) << 0) & 0xffffffff)
2927 
2928 #ifndef __ASSEMBLY__
2929 /*
2930  * WARNING: The C register and register group struct declarations are provided for
2931  * convenience and illustrative purposes. They should, however, be used with
2932  * caution as the C language standard provides no guarantees about the alignment or
2933  * atomicity of device memory accesses. The recommended practice for coding device
2934  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2935  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2936  * alt_write_dword() functions for 64 bit registers.
2937  *
2938  * The struct declaration for register ALT_GIC_DIST_GICD_ICENABLER10.
2939  */
2940 struct ALT_GIC_DIST_GICD_ICENABLER10_s
2941 {
2942  volatile uint32_t fld : 32; /* Empty */
2943 };
2944 
2945 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICENABLER10. */
2946 typedef struct ALT_GIC_DIST_GICD_ICENABLER10_s ALT_GIC_DIST_GICD_ICENABLER10_t;
2947 #endif /* __ASSEMBLY__ */
2948 
2949 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER10 register. */
2950 #define ALT_GIC_DIST_GICD_ICENABLER10_RESET 0x00000000
2951 /* The byte offset of the ALT_GIC_DIST_GICD_ICENABLER10 register from the beginning of the component. */
2952 #define ALT_GIC_DIST_GICD_ICENABLER10_OFST 0x1a8
2953 
2954 /*
2955  * Register : GICD_ICENABLER11
2956  *
2957  * Interrupt Clear-Enable Registers
2958  *
2959  * Register Layout
2960  *
2961  * Bits | Access | Reset | Description
2962  * :-------|:-------|:------|:------------
2963  * [31:0] | RW | 0x0 | Empty
2964  *
2965  */
2966 /*
2967  * Field : Empty - fld
2968  *
2969  * Placeholder
2970  *
2971  * Field Access Macros:
2972  *
2973  */
2974 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICENABLER11_FLD register field. */
2975 #define ALT_GIC_DIST_GICD_ICENABLER11_FLD_LSB 0
2976 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICENABLER11_FLD register field. */
2977 #define ALT_GIC_DIST_GICD_ICENABLER11_FLD_MSB 31
2978 /* The width in bits of the ALT_GIC_DIST_GICD_ICENABLER11_FLD register field. */
2979 #define ALT_GIC_DIST_GICD_ICENABLER11_FLD_WIDTH 32
2980 /* The mask used to set the ALT_GIC_DIST_GICD_ICENABLER11_FLD register field value. */
2981 #define ALT_GIC_DIST_GICD_ICENABLER11_FLD_SET_MSK 0xffffffff
2982 /* The mask used to clear the ALT_GIC_DIST_GICD_ICENABLER11_FLD register field value. */
2983 #define ALT_GIC_DIST_GICD_ICENABLER11_FLD_CLR_MSK 0x00000000
2984 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER11_FLD register field. */
2985 #define ALT_GIC_DIST_GICD_ICENABLER11_FLD_RESET 0x0
2986 /* Extracts the ALT_GIC_DIST_GICD_ICENABLER11_FLD field value from a register. */
2987 #define ALT_GIC_DIST_GICD_ICENABLER11_FLD_GET(value) (((value) & 0xffffffff) >> 0)
2988 /* Produces a ALT_GIC_DIST_GICD_ICENABLER11_FLD register field value suitable for setting the register. */
2989 #define ALT_GIC_DIST_GICD_ICENABLER11_FLD_SET(value) (((value) << 0) & 0xffffffff)
2990 
2991 #ifndef __ASSEMBLY__
2992 /*
2993  * WARNING: The C register and register group struct declarations are provided for
2994  * convenience and illustrative purposes. They should, however, be used with
2995  * caution as the C language standard provides no guarantees about the alignment or
2996  * atomicity of device memory accesses. The recommended practice for coding device
2997  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2998  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2999  * alt_write_dword() functions for 64 bit registers.
3000  *
3001  * The struct declaration for register ALT_GIC_DIST_GICD_ICENABLER11.
3002  */
3003 struct ALT_GIC_DIST_GICD_ICENABLER11_s
3004 {
3005  volatile uint32_t fld : 32; /* Empty */
3006 };
3007 
3008 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICENABLER11. */
3009 typedef struct ALT_GIC_DIST_GICD_ICENABLER11_s ALT_GIC_DIST_GICD_ICENABLER11_t;
3010 #endif /* __ASSEMBLY__ */
3011 
3012 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER11 register. */
3013 #define ALT_GIC_DIST_GICD_ICENABLER11_RESET 0x00000000
3014 /* The byte offset of the ALT_GIC_DIST_GICD_ICENABLER11 register from the beginning of the component. */
3015 #define ALT_GIC_DIST_GICD_ICENABLER11_OFST 0x1ac
3016 
3017 /*
3018  * Register : GICD_ICENABLER12
3019  *
3020  * Interrupt Clear-Enable Registers
3021  *
3022  * Register Layout
3023  *
3024  * Bits | Access | Reset | Description
3025  * :-------|:-------|:------|:------------
3026  * [31:0] | RW | 0x0 | Empty
3027  *
3028  */
3029 /*
3030  * Field : Empty - fld
3031  *
3032  * Placeholder
3033  *
3034  * Field Access Macros:
3035  *
3036  */
3037 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICENABLER12_FLD register field. */
3038 #define ALT_GIC_DIST_GICD_ICENABLER12_FLD_LSB 0
3039 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICENABLER12_FLD register field. */
3040 #define ALT_GIC_DIST_GICD_ICENABLER12_FLD_MSB 31
3041 /* The width in bits of the ALT_GIC_DIST_GICD_ICENABLER12_FLD register field. */
3042 #define ALT_GIC_DIST_GICD_ICENABLER12_FLD_WIDTH 32
3043 /* The mask used to set the ALT_GIC_DIST_GICD_ICENABLER12_FLD register field value. */
3044 #define ALT_GIC_DIST_GICD_ICENABLER12_FLD_SET_MSK 0xffffffff
3045 /* The mask used to clear the ALT_GIC_DIST_GICD_ICENABLER12_FLD register field value. */
3046 #define ALT_GIC_DIST_GICD_ICENABLER12_FLD_CLR_MSK 0x00000000
3047 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER12_FLD register field. */
3048 #define ALT_GIC_DIST_GICD_ICENABLER12_FLD_RESET 0x0
3049 /* Extracts the ALT_GIC_DIST_GICD_ICENABLER12_FLD field value from a register. */
3050 #define ALT_GIC_DIST_GICD_ICENABLER12_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3051 /* Produces a ALT_GIC_DIST_GICD_ICENABLER12_FLD register field value suitable for setting the register. */
3052 #define ALT_GIC_DIST_GICD_ICENABLER12_FLD_SET(value) (((value) << 0) & 0xffffffff)
3053 
3054 #ifndef __ASSEMBLY__
3055 /*
3056  * WARNING: The C register and register group struct declarations are provided for
3057  * convenience and illustrative purposes. They should, however, be used with
3058  * caution as the C language standard provides no guarantees about the alignment or
3059  * atomicity of device memory accesses. The recommended practice for coding device
3060  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3061  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3062  * alt_write_dword() functions for 64 bit registers.
3063  *
3064  * The struct declaration for register ALT_GIC_DIST_GICD_ICENABLER12.
3065  */
3066 struct ALT_GIC_DIST_GICD_ICENABLER12_s
3067 {
3068  volatile uint32_t fld : 32; /* Empty */
3069 };
3070 
3071 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICENABLER12. */
3072 typedef struct ALT_GIC_DIST_GICD_ICENABLER12_s ALT_GIC_DIST_GICD_ICENABLER12_t;
3073 #endif /* __ASSEMBLY__ */
3074 
3075 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER12 register. */
3076 #define ALT_GIC_DIST_GICD_ICENABLER12_RESET 0x00000000
3077 /* The byte offset of the ALT_GIC_DIST_GICD_ICENABLER12 register from the beginning of the component. */
3078 #define ALT_GIC_DIST_GICD_ICENABLER12_OFST 0x1b0
3079 
3080 /*
3081  * Register : GICD_ICENABLER13
3082  *
3083  * Interrupt Clear-Enable Registers
3084  *
3085  * Register Layout
3086  *
3087  * Bits | Access | Reset | Description
3088  * :-------|:-------|:------|:------------
3089  * [31:0] | RW | 0x0 | Empty
3090  *
3091  */
3092 /*
3093  * Field : Empty - fld
3094  *
3095  * Placeholder
3096  *
3097  * Field Access Macros:
3098  *
3099  */
3100 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICENABLER13_FLD register field. */
3101 #define ALT_GIC_DIST_GICD_ICENABLER13_FLD_LSB 0
3102 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICENABLER13_FLD register field. */
3103 #define ALT_GIC_DIST_GICD_ICENABLER13_FLD_MSB 31
3104 /* The width in bits of the ALT_GIC_DIST_GICD_ICENABLER13_FLD register field. */
3105 #define ALT_GIC_DIST_GICD_ICENABLER13_FLD_WIDTH 32
3106 /* The mask used to set the ALT_GIC_DIST_GICD_ICENABLER13_FLD register field value. */
3107 #define ALT_GIC_DIST_GICD_ICENABLER13_FLD_SET_MSK 0xffffffff
3108 /* The mask used to clear the ALT_GIC_DIST_GICD_ICENABLER13_FLD register field value. */
3109 #define ALT_GIC_DIST_GICD_ICENABLER13_FLD_CLR_MSK 0x00000000
3110 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER13_FLD register field. */
3111 #define ALT_GIC_DIST_GICD_ICENABLER13_FLD_RESET 0x0
3112 /* Extracts the ALT_GIC_DIST_GICD_ICENABLER13_FLD field value from a register. */
3113 #define ALT_GIC_DIST_GICD_ICENABLER13_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3114 /* Produces a ALT_GIC_DIST_GICD_ICENABLER13_FLD register field value suitable for setting the register. */
3115 #define ALT_GIC_DIST_GICD_ICENABLER13_FLD_SET(value) (((value) << 0) & 0xffffffff)
3116 
3117 #ifndef __ASSEMBLY__
3118 /*
3119  * WARNING: The C register and register group struct declarations are provided for
3120  * convenience and illustrative purposes. They should, however, be used with
3121  * caution as the C language standard provides no guarantees about the alignment or
3122  * atomicity of device memory accesses. The recommended practice for coding device
3123  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3124  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3125  * alt_write_dword() functions for 64 bit registers.
3126  *
3127  * The struct declaration for register ALT_GIC_DIST_GICD_ICENABLER13.
3128  */
3129 struct ALT_GIC_DIST_GICD_ICENABLER13_s
3130 {
3131  volatile uint32_t fld : 32; /* Empty */
3132 };
3133 
3134 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICENABLER13. */
3135 typedef struct ALT_GIC_DIST_GICD_ICENABLER13_s ALT_GIC_DIST_GICD_ICENABLER13_t;
3136 #endif /* __ASSEMBLY__ */
3137 
3138 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER13 register. */
3139 #define ALT_GIC_DIST_GICD_ICENABLER13_RESET 0x00000000
3140 /* The byte offset of the ALT_GIC_DIST_GICD_ICENABLER13 register from the beginning of the component. */
3141 #define ALT_GIC_DIST_GICD_ICENABLER13_OFST 0x1b4
3142 
3143 /*
3144  * Register : GICD_ICENABLER14
3145  *
3146  * Interrupt Clear-Enable Registers
3147  *
3148  * Register Layout
3149  *
3150  * Bits | Access | Reset | Description
3151  * :-------|:-------|:------|:------------
3152  * [31:0] | RW | 0x0 | Empty
3153  *
3154  */
3155 /*
3156  * Field : Empty - fld
3157  *
3158  * Placeholder
3159  *
3160  * Field Access Macros:
3161  *
3162  */
3163 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICENABLER14_FLD register field. */
3164 #define ALT_GIC_DIST_GICD_ICENABLER14_FLD_LSB 0
3165 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICENABLER14_FLD register field. */
3166 #define ALT_GIC_DIST_GICD_ICENABLER14_FLD_MSB 31
3167 /* The width in bits of the ALT_GIC_DIST_GICD_ICENABLER14_FLD register field. */
3168 #define ALT_GIC_DIST_GICD_ICENABLER14_FLD_WIDTH 32
3169 /* The mask used to set the ALT_GIC_DIST_GICD_ICENABLER14_FLD register field value. */
3170 #define ALT_GIC_DIST_GICD_ICENABLER14_FLD_SET_MSK 0xffffffff
3171 /* The mask used to clear the ALT_GIC_DIST_GICD_ICENABLER14_FLD register field value. */
3172 #define ALT_GIC_DIST_GICD_ICENABLER14_FLD_CLR_MSK 0x00000000
3173 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER14_FLD register field. */
3174 #define ALT_GIC_DIST_GICD_ICENABLER14_FLD_RESET 0x0
3175 /* Extracts the ALT_GIC_DIST_GICD_ICENABLER14_FLD field value from a register. */
3176 #define ALT_GIC_DIST_GICD_ICENABLER14_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3177 /* Produces a ALT_GIC_DIST_GICD_ICENABLER14_FLD register field value suitable for setting the register. */
3178 #define ALT_GIC_DIST_GICD_ICENABLER14_FLD_SET(value) (((value) << 0) & 0xffffffff)
3179 
3180 #ifndef __ASSEMBLY__
3181 /*
3182  * WARNING: The C register and register group struct declarations are provided for
3183  * convenience and illustrative purposes. They should, however, be used with
3184  * caution as the C language standard provides no guarantees about the alignment or
3185  * atomicity of device memory accesses. The recommended practice for coding device
3186  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3187  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3188  * alt_write_dword() functions for 64 bit registers.
3189  *
3190  * The struct declaration for register ALT_GIC_DIST_GICD_ICENABLER14.
3191  */
3192 struct ALT_GIC_DIST_GICD_ICENABLER14_s
3193 {
3194  volatile uint32_t fld : 32; /* Empty */
3195 };
3196 
3197 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICENABLER14. */
3198 typedef struct ALT_GIC_DIST_GICD_ICENABLER14_s ALT_GIC_DIST_GICD_ICENABLER14_t;
3199 #endif /* __ASSEMBLY__ */
3200 
3201 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER14 register. */
3202 #define ALT_GIC_DIST_GICD_ICENABLER14_RESET 0x00000000
3203 /* The byte offset of the ALT_GIC_DIST_GICD_ICENABLER14 register from the beginning of the component. */
3204 #define ALT_GIC_DIST_GICD_ICENABLER14_OFST 0x1b8
3205 
3206 /*
3207  * Register : GICD_ICENABLER15
3208  *
3209  * Interrupt Clear-Enable Registers
3210  *
3211  * Register Layout
3212  *
3213  * Bits | Access | Reset | Description
3214  * :-------|:-------|:------|:------------
3215  * [31:0] | RW | 0x0 | Empty
3216  *
3217  */
3218 /*
3219  * Field : Empty - fld
3220  *
3221  * Placeholder
3222  *
3223  * Field Access Macros:
3224  *
3225  */
3226 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICENABLER15_FLD register field. */
3227 #define ALT_GIC_DIST_GICD_ICENABLER15_FLD_LSB 0
3228 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICENABLER15_FLD register field. */
3229 #define ALT_GIC_DIST_GICD_ICENABLER15_FLD_MSB 31
3230 /* The width in bits of the ALT_GIC_DIST_GICD_ICENABLER15_FLD register field. */
3231 #define ALT_GIC_DIST_GICD_ICENABLER15_FLD_WIDTH 32
3232 /* The mask used to set the ALT_GIC_DIST_GICD_ICENABLER15_FLD register field value. */
3233 #define ALT_GIC_DIST_GICD_ICENABLER15_FLD_SET_MSK 0xffffffff
3234 /* The mask used to clear the ALT_GIC_DIST_GICD_ICENABLER15_FLD register field value. */
3235 #define ALT_GIC_DIST_GICD_ICENABLER15_FLD_CLR_MSK 0x00000000
3236 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER15_FLD register field. */
3237 #define ALT_GIC_DIST_GICD_ICENABLER15_FLD_RESET 0x0
3238 /* Extracts the ALT_GIC_DIST_GICD_ICENABLER15_FLD field value from a register. */
3239 #define ALT_GIC_DIST_GICD_ICENABLER15_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3240 /* Produces a ALT_GIC_DIST_GICD_ICENABLER15_FLD register field value suitable for setting the register. */
3241 #define ALT_GIC_DIST_GICD_ICENABLER15_FLD_SET(value) (((value) << 0) & 0xffffffff)
3242 
3243 #ifndef __ASSEMBLY__
3244 /*
3245  * WARNING: The C register and register group struct declarations are provided for
3246  * convenience and illustrative purposes. They should, however, be used with
3247  * caution as the C language standard provides no guarantees about the alignment or
3248  * atomicity of device memory accesses. The recommended practice for coding device
3249  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3250  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3251  * alt_write_dword() functions for 64 bit registers.
3252  *
3253  * The struct declaration for register ALT_GIC_DIST_GICD_ICENABLER15.
3254  */
3255 struct ALT_GIC_DIST_GICD_ICENABLER15_s
3256 {
3257  volatile uint32_t fld : 32; /* Empty */
3258 };
3259 
3260 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICENABLER15. */
3261 typedef struct ALT_GIC_DIST_GICD_ICENABLER15_s ALT_GIC_DIST_GICD_ICENABLER15_t;
3262 #endif /* __ASSEMBLY__ */
3263 
3264 /* The reset value of the ALT_GIC_DIST_GICD_ICENABLER15 register. */
3265 #define ALT_GIC_DIST_GICD_ICENABLER15_RESET 0x00000000
3266 /* The byte offset of the ALT_GIC_DIST_GICD_ICENABLER15 register from the beginning of the component. */
3267 #define ALT_GIC_DIST_GICD_ICENABLER15_OFST 0x1bc
3268 
3269 /*
3270  * Register : GICD_ISPENDR0
3271  *
3272  * Interrupt Set-Pending Registers
3273  *
3274  * Register Layout
3275  *
3276  * Bits | Access | Reset | Description
3277  * :-------|:-------|:------|:------------
3278  * [31:0] | RW | 0x0 | Empty
3279  *
3280  */
3281 /*
3282  * Field : Empty - fld
3283  *
3284  * Placeholder
3285  *
3286  * Field Access Macros:
3287  *
3288  */
3289 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISPENDR0_FLD register field. */
3290 #define ALT_GIC_DIST_GICD_ISPENDR0_FLD_LSB 0
3291 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISPENDR0_FLD register field. */
3292 #define ALT_GIC_DIST_GICD_ISPENDR0_FLD_MSB 31
3293 /* The width in bits of the ALT_GIC_DIST_GICD_ISPENDR0_FLD register field. */
3294 #define ALT_GIC_DIST_GICD_ISPENDR0_FLD_WIDTH 32
3295 /* The mask used to set the ALT_GIC_DIST_GICD_ISPENDR0_FLD register field value. */
3296 #define ALT_GIC_DIST_GICD_ISPENDR0_FLD_SET_MSK 0xffffffff
3297 /* The mask used to clear the ALT_GIC_DIST_GICD_ISPENDR0_FLD register field value. */
3298 #define ALT_GIC_DIST_GICD_ISPENDR0_FLD_CLR_MSK 0x00000000
3299 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR0_FLD register field. */
3300 #define ALT_GIC_DIST_GICD_ISPENDR0_FLD_RESET 0x0
3301 /* Extracts the ALT_GIC_DIST_GICD_ISPENDR0_FLD field value from a register. */
3302 #define ALT_GIC_DIST_GICD_ISPENDR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3303 /* Produces a ALT_GIC_DIST_GICD_ISPENDR0_FLD register field value suitable for setting the register. */
3304 #define ALT_GIC_DIST_GICD_ISPENDR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
3305 
3306 #ifndef __ASSEMBLY__
3307 /*
3308  * WARNING: The C register and register group struct declarations are provided for
3309  * convenience and illustrative purposes. They should, however, be used with
3310  * caution as the C language standard provides no guarantees about the alignment or
3311  * atomicity of device memory accesses. The recommended practice for coding device
3312  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3313  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3314  * alt_write_dword() functions for 64 bit registers.
3315  *
3316  * The struct declaration for register ALT_GIC_DIST_GICD_ISPENDR0.
3317  */
3318 struct ALT_GIC_DIST_GICD_ISPENDR0_s
3319 {
3320  volatile uint32_t fld : 32; /* Empty */
3321 };
3322 
3323 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISPENDR0. */
3324 typedef struct ALT_GIC_DIST_GICD_ISPENDR0_s ALT_GIC_DIST_GICD_ISPENDR0_t;
3325 #endif /* __ASSEMBLY__ */
3326 
3327 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR0 register. */
3328 #define ALT_GIC_DIST_GICD_ISPENDR0_RESET 0x00000000
3329 /* The byte offset of the ALT_GIC_DIST_GICD_ISPENDR0 register from the beginning of the component. */
3330 #define ALT_GIC_DIST_GICD_ISPENDR0_OFST 0x200
3331 
3332 /*
3333  * Register : GICD_ISPENDR1
3334  *
3335  * Interrupt Set-Pending Registers
3336  *
3337  * Register Layout
3338  *
3339  * Bits | Access | Reset | Description
3340  * :-------|:-------|:------|:------------
3341  * [31:0] | RW | 0x0 | Empty
3342  *
3343  */
3344 /*
3345  * Field : Empty - fld
3346  *
3347  * Placeholder
3348  *
3349  * Field Access Macros:
3350  *
3351  */
3352 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISPENDR1_FLD register field. */
3353 #define ALT_GIC_DIST_GICD_ISPENDR1_FLD_LSB 0
3354 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISPENDR1_FLD register field. */
3355 #define ALT_GIC_DIST_GICD_ISPENDR1_FLD_MSB 31
3356 /* The width in bits of the ALT_GIC_DIST_GICD_ISPENDR1_FLD register field. */
3357 #define ALT_GIC_DIST_GICD_ISPENDR1_FLD_WIDTH 32
3358 /* The mask used to set the ALT_GIC_DIST_GICD_ISPENDR1_FLD register field value. */
3359 #define ALT_GIC_DIST_GICD_ISPENDR1_FLD_SET_MSK 0xffffffff
3360 /* The mask used to clear the ALT_GIC_DIST_GICD_ISPENDR1_FLD register field value. */
3361 #define ALT_GIC_DIST_GICD_ISPENDR1_FLD_CLR_MSK 0x00000000
3362 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR1_FLD register field. */
3363 #define ALT_GIC_DIST_GICD_ISPENDR1_FLD_RESET 0x0
3364 /* Extracts the ALT_GIC_DIST_GICD_ISPENDR1_FLD field value from a register. */
3365 #define ALT_GIC_DIST_GICD_ISPENDR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3366 /* Produces a ALT_GIC_DIST_GICD_ISPENDR1_FLD register field value suitable for setting the register. */
3367 #define ALT_GIC_DIST_GICD_ISPENDR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
3368 
3369 #ifndef __ASSEMBLY__
3370 /*
3371  * WARNING: The C register and register group struct declarations are provided for
3372  * convenience and illustrative purposes. They should, however, be used with
3373  * caution as the C language standard provides no guarantees about the alignment or
3374  * atomicity of device memory accesses. The recommended practice for coding device
3375  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3376  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3377  * alt_write_dword() functions for 64 bit registers.
3378  *
3379  * The struct declaration for register ALT_GIC_DIST_GICD_ISPENDR1.
3380  */
3381 struct ALT_GIC_DIST_GICD_ISPENDR1_s
3382 {
3383  volatile uint32_t fld : 32; /* Empty */
3384 };
3385 
3386 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISPENDR1. */
3387 typedef struct ALT_GIC_DIST_GICD_ISPENDR1_s ALT_GIC_DIST_GICD_ISPENDR1_t;
3388 #endif /* __ASSEMBLY__ */
3389 
3390 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR1 register. */
3391 #define ALT_GIC_DIST_GICD_ISPENDR1_RESET 0x00000000
3392 /* The byte offset of the ALT_GIC_DIST_GICD_ISPENDR1 register from the beginning of the component. */
3393 #define ALT_GIC_DIST_GICD_ISPENDR1_OFST 0x204
3394 
3395 /*
3396  * Register : GICD_ISPENDR2
3397  *
3398  * Interrupt Set-Pending Registers
3399  *
3400  * Register Layout
3401  *
3402  * Bits | Access | Reset | Description
3403  * :-------|:-------|:------|:------------
3404  * [31:0] | RW | 0x0 | Empty
3405  *
3406  */
3407 /*
3408  * Field : Empty - fld
3409  *
3410  * Placeholder
3411  *
3412  * Field Access Macros:
3413  *
3414  */
3415 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISPENDR2_FLD register field. */
3416 #define ALT_GIC_DIST_GICD_ISPENDR2_FLD_LSB 0
3417 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISPENDR2_FLD register field. */
3418 #define ALT_GIC_DIST_GICD_ISPENDR2_FLD_MSB 31
3419 /* The width in bits of the ALT_GIC_DIST_GICD_ISPENDR2_FLD register field. */
3420 #define ALT_GIC_DIST_GICD_ISPENDR2_FLD_WIDTH 32
3421 /* The mask used to set the ALT_GIC_DIST_GICD_ISPENDR2_FLD register field value. */
3422 #define ALT_GIC_DIST_GICD_ISPENDR2_FLD_SET_MSK 0xffffffff
3423 /* The mask used to clear the ALT_GIC_DIST_GICD_ISPENDR2_FLD register field value. */
3424 #define ALT_GIC_DIST_GICD_ISPENDR2_FLD_CLR_MSK 0x00000000
3425 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR2_FLD register field. */
3426 #define ALT_GIC_DIST_GICD_ISPENDR2_FLD_RESET 0x0
3427 /* Extracts the ALT_GIC_DIST_GICD_ISPENDR2_FLD field value from a register. */
3428 #define ALT_GIC_DIST_GICD_ISPENDR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3429 /* Produces a ALT_GIC_DIST_GICD_ISPENDR2_FLD register field value suitable for setting the register. */
3430 #define ALT_GIC_DIST_GICD_ISPENDR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
3431 
3432 #ifndef __ASSEMBLY__
3433 /*
3434  * WARNING: The C register and register group struct declarations are provided for
3435  * convenience and illustrative purposes. They should, however, be used with
3436  * caution as the C language standard provides no guarantees about the alignment or
3437  * atomicity of device memory accesses. The recommended practice for coding device
3438  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3439  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3440  * alt_write_dword() functions for 64 bit registers.
3441  *
3442  * The struct declaration for register ALT_GIC_DIST_GICD_ISPENDR2.
3443  */
3444 struct ALT_GIC_DIST_GICD_ISPENDR2_s
3445 {
3446  volatile uint32_t fld : 32; /* Empty */
3447 };
3448 
3449 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISPENDR2. */
3450 typedef struct ALT_GIC_DIST_GICD_ISPENDR2_s ALT_GIC_DIST_GICD_ISPENDR2_t;
3451 #endif /* __ASSEMBLY__ */
3452 
3453 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR2 register. */
3454 #define ALT_GIC_DIST_GICD_ISPENDR2_RESET 0x00000000
3455 /* The byte offset of the ALT_GIC_DIST_GICD_ISPENDR2 register from the beginning of the component. */
3456 #define ALT_GIC_DIST_GICD_ISPENDR2_OFST 0x208
3457 
3458 /*
3459  * Register : GICD_ISPENDR3
3460  *
3461  * Interrupt Set-Pending Registers
3462  *
3463  * Register Layout
3464  *
3465  * Bits | Access | Reset | Description
3466  * :-------|:-------|:------|:------------
3467  * [31:0] | RW | 0x0 | Empty
3468  *
3469  */
3470 /*
3471  * Field : Empty - fld
3472  *
3473  * Placeholder
3474  *
3475  * Field Access Macros:
3476  *
3477  */
3478 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISPENDR3_FLD register field. */
3479 #define ALT_GIC_DIST_GICD_ISPENDR3_FLD_LSB 0
3480 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISPENDR3_FLD register field. */
3481 #define ALT_GIC_DIST_GICD_ISPENDR3_FLD_MSB 31
3482 /* The width in bits of the ALT_GIC_DIST_GICD_ISPENDR3_FLD register field. */
3483 #define ALT_GIC_DIST_GICD_ISPENDR3_FLD_WIDTH 32
3484 /* The mask used to set the ALT_GIC_DIST_GICD_ISPENDR3_FLD register field value. */
3485 #define ALT_GIC_DIST_GICD_ISPENDR3_FLD_SET_MSK 0xffffffff
3486 /* The mask used to clear the ALT_GIC_DIST_GICD_ISPENDR3_FLD register field value. */
3487 #define ALT_GIC_DIST_GICD_ISPENDR3_FLD_CLR_MSK 0x00000000
3488 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR3_FLD register field. */
3489 #define ALT_GIC_DIST_GICD_ISPENDR3_FLD_RESET 0x0
3490 /* Extracts the ALT_GIC_DIST_GICD_ISPENDR3_FLD field value from a register. */
3491 #define ALT_GIC_DIST_GICD_ISPENDR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3492 /* Produces a ALT_GIC_DIST_GICD_ISPENDR3_FLD register field value suitable for setting the register. */
3493 #define ALT_GIC_DIST_GICD_ISPENDR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
3494 
3495 #ifndef __ASSEMBLY__
3496 /*
3497  * WARNING: The C register and register group struct declarations are provided for
3498  * convenience and illustrative purposes. They should, however, be used with
3499  * caution as the C language standard provides no guarantees about the alignment or
3500  * atomicity of device memory accesses. The recommended practice for coding device
3501  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3502  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3503  * alt_write_dword() functions for 64 bit registers.
3504  *
3505  * The struct declaration for register ALT_GIC_DIST_GICD_ISPENDR3.
3506  */
3507 struct ALT_GIC_DIST_GICD_ISPENDR3_s
3508 {
3509  volatile uint32_t fld : 32; /* Empty */
3510 };
3511 
3512 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISPENDR3. */
3513 typedef struct ALT_GIC_DIST_GICD_ISPENDR3_s ALT_GIC_DIST_GICD_ISPENDR3_t;
3514 #endif /* __ASSEMBLY__ */
3515 
3516 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR3 register. */
3517 #define ALT_GIC_DIST_GICD_ISPENDR3_RESET 0x00000000
3518 /* The byte offset of the ALT_GIC_DIST_GICD_ISPENDR3 register from the beginning of the component. */
3519 #define ALT_GIC_DIST_GICD_ISPENDR3_OFST 0x20c
3520 
3521 /*
3522  * Register : GICD_ISPENDR4
3523  *
3524  * Interrupt Set-Pending Registers
3525  *
3526  * Register Layout
3527  *
3528  * Bits | Access | Reset | Description
3529  * :-------|:-------|:------|:------------
3530  * [31:0] | RW | 0x0 | Empty
3531  *
3532  */
3533 /*
3534  * Field : Empty - fld
3535  *
3536  * Placeholder
3537  *
3538  * Field Access Macros:
3539  *
3540  */
3541 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISPENDR4_FLD register field. */
3542 #define ALT_GIC_DIST_GICD_ISPENDR4_FLD_LSB 0
3543 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISPENDR4_FLD register field. */
3544 #define ALT_GIC_DIST_GICD_ISPENDR4_FLD_MSB 31
3545 /* The width in bits of the ALT_GIC_DIST_GICD_ISPENDR4_FLD register field. */
3546 #define ALT_GIC_DIST_GICD_ISPENDR4_FLD_WIDTH 32
3547 /* The mask used to set the ALT_GIC_DIST_GICD_ISPENDR4_FLD register field value. */
3548 #define ALT_GIC_DIST_GICD_ISPENDR4_FLD_SET_MSK 0xffffffff
3549 /* The mask used to clear the ALT_GIC_DIST_GICD_ISPENDR4_FLD register field value. */
3550 #define ALT_GIC_DIST_GICD_ISPENDR4_FLD_CLR_MSK 0x00000000
3551 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR4_FLD register field. */
3552 #define ALT_GIC_DIST_GICD_ISPENDR4_FLD_RESET 0x0
3553 /* Extracts the ALT_GIC_DIST_GICD_ISPENDR4_FLD field value from a register. */
3554 #define ALT_GIC_DIST_GICD_ISPENDR4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3555 /* Produces a ALT_GIC_DIST_GICD_ISPENDR4_FLD register field value suitable for setting the register. */
3556 #define ALT_GIC_DIST_GICD_ISPENDR4_FLD_SET(value) (((value) << 0) & 0xffffffff)
3557 
3558 #ifndef __ASSEMBLY__
3559 /*
3560  * WARNING: The C register and register group struct declarations are provided for
3561  * convenience and illustrative purposes. They should, however, be used with
3562  * caution as the C language standard provides no guarantees about the alignment or
3563  * atomicity of device memory accesses. The recommended practice for coding device
3564  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3565  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3566  * alt_write_dword() functions for 64 bit registers.
3567  *
3568  * The struct declaration for register ALT_GIC_DIST_GICD_ISPENDR4.
3569  */
3570 struct ALT_GIC_DIST_GICD_ISPENDR4_s
3571 {
3572  volatile uint32_t fld : 32; /* Empty */
3573 };
3574 
3575 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISPENDR4. */
3576 typedef struct ALT_GIC_DIST_GICD_ISPENDR4_s ALT_GIC_DIST_GICD_ISPENDR4_t;
3577 #endif /* __ASSEMBLY__ */
3578 
3579 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR4 register. */
3580 #define ALT_GIC_DIST_GICD_ISPENDR4_RESET 0x00000000
3581 /* The byte offset of the ALT_GIC_DIST_GICD_ISPENDR4 register from the beginning of the component. */
3582 #define ALT_GIC_DIST_GICD_ISPENDR4_OFST 0x210
3583 
3584 /*
3585  * Register : GICD_ISPENDR5
3586  *
3587  * Interrupt Set-Pending Registers
3588  *
3589  * Register Layout
3590  *
3591  * Bits | Access | Reset | Description
3592  * :-------|:-------|:------|:------------
3593  * [31:0] | RW | 0x0 | Empty
3594  *
3595  */
3596 /*
3597  * Field : Empty - fld
3598  *
3599  * Placeholder
3600  *
3601  * Field Access Macros:
3602  *
3603  */
3604 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISPENDR5_FLD register field. */
3605 #define ALT_GIC_DIST_GICD_ISPENDR5_FLD_LSB 0
3606 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISPENDR5_FLD register field. */
3607 #define ALT_GIC_DIST_GICD_ISPENDR5_FLD_MSB 31
3608 /* The width in bits of the ALT_GIC_DIST_GICD_ISPENDR5_FLD register field. */
3609 #define ALT_GIC_DIST_GICD_ISPENDR5_FLD_WIDTH 32
3610 /* The mask used to set the ALT_GIC_DIST_GICD_ISPENDR5_FLD register field value. */
3611 #define ALT_GIC_DIST_GICD_ISPENDR5_FLD_SET_MSK 0xffffffff
3612 /* The mask used to clear the ALT_GIC_DIST_GICD_ISPENDR5_FLD register field value. */
3613 #define ALT_GIC_DIST_GICD_ISPENDR5_FLD_CLR_MSK 0x00000000
3614 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR5_FLD register field. */
3615 #define ALT_GIC_DIST_GICD_ISPENDR5_FLD_RESET 0x0
3616 /* Extracts the ALT_GIC_DIST_GICD_ISPENDR5_FLD field value from a register. */
3617 #define ALT_GIC_DIST_GICD_ISPENDR5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3618 /* Produces a ALT_GIC_DIST_GICD_ISPENDR5_FLD register field value suitable for setting the register. */
3619 #define ALT_GIC_DIST_GICD_ISPENDR5_FLD_SET(value) (((value) << 0) & 0xffffffff)
3620 
3621 #ifndef __ASSEMBLY__
3622 /*
3623  * WARNING: The C register and register group struct declarations are provided for
3624  * convenience and illustrative purposes. They should, however, be used with
3625  * caution as the C language standard provides no guarantees about the alignment or
3626  * atomicity of device memory accesses. The recommended practice for coding device
3627  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3628  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3629  * alt_write_dword() functions for 64 bit registers.
3630  *
3631  * The struct declaration for register ALT_GIC_DIST_GICD_ISPENDR5.
3632  */
3633 struct ALT_GIC_DIST_GICD_ISPENDR5_s
3634 {
3635  volatile uint32_t fld : 32; /* Empty */
3636 };
3637 
3638 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISPENDR5. */
3639 typedef struct ALT_GIC_DIST_GICD_ISPENDR5_s ALT_GIC_DIST_GICD_ISPENDR5_t;
3640 #endif /* __ASSEMBLY__ */
3641 
3642 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR5 register. */
3643 #define ALT_GIC_DIST_GICD_ISPENDR5_RESET 0x00000000
3644 /* The byte offset of the ALT_GIC_DIST_GICD_ISPENDR5 register from the beginning of the component. */
3645 #define ALT_GIC_DIST_GICD_ISPENDR5_OFST 0x214
3646 
3647 /*
3648  * Register : GICD_ISPENDR6
3649  *
3650  * Interrupt Set-Pending Registers
3651  *
3652  * Register Layout
3653  *
3654  * Bits | Access | Reset | Description
3655  * :-------|:-------|:------|:------------
3656  * [31:0] | RW | 0x0 | Empty
3657  *
3658  */
3659 /*
3660  * Field : Empty - fld
3661  *
3662  * Placeholder
3663  *
3664  * Field Access Macros:
3665  *
3666  */
3667 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISPENDR6_FLD register field. */
3668 #define ALT_GIC_DIST_GICD_ISPENDR6_FLD_LSB 0
3669 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISPENDR6_FLD register field. */
3670 #define ALT_GIC_DIST_GICD_ISPENDR6_FLD_MSB 31
3671 /* The width in bits of the ALT_GIC_DIST_GICD_ISPENDR6_FLD register field. */
3672 #define ALT_GIC_DIST_GICD_ISPENDR6_FLD_WIDTH 32
3673 /* The mask used to set the ALT_GIC_DIST_GICD_ISPENDR6_FLD register field value. */
3674 #define ALT_GIC_DIST_GICD_ISPENDR6_FLD_SET_MSK 0xffffffff
3675 /* The mask used to clear the ALT_GIC_DIST_GICD_ISPENDR6_FLD register field value. */
3676 #define ALT_GIC_DIST_GICD_ISPENDR6_FLD_CLR_MSK 0x00000000
3677 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR6_FLD register field. */
3678 #define ALT_GIC_DIST_GICD_ISPENDR6_FLD_RESET 0x0
3679 /* Extracts the ALT_GIC_DIST_GICD_ISPENDR6_FLD field value from a register. */
3680 #define ALT_GIC_DIST_GICD_ISPENDR6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3681 /* Produces a ALT_GIC_DIST_GICD_ISPENDR6_FLD register field value suitable for setting the register. */
3682 #define ALT_GIC_DIST_GICD_ISPENDR6_FLD_SET(value) (((value) << 0) & 0xffffffff)
3683 
3684 #ifndef __ASSEMBLY__
3685 /*
3686  * WARNING: The C register and register group struct declarations are provided for
3687  * convenience and illustrative purposes. They should, however, be used with
3688  * caution as the C language standard provides no guarantees about the alignment or
3689  * atomicity of device memory accesses. The recommended practice for coding device
3690  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3691  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3692  * alt_write_dword() functions for 64 bit registers.
3693  *
3694  * The struct declaration for register ALT_GIC_DIST_GICD_ISPENDR6.
3695  */
3696 struct ALT_GIC_DIST_GICD_ISPENDR6_s
3697 {
3698  volatile uint32_t fld : 32; /* Empty */
3699 };
3700 
3701 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISPENDR6. */
3702 typedef struct ALT_GIC_DIST_GICD_ISPENDR6_s ALT_GIC_DIST_GICD_ISPENDR6_t;
3703 #endif /* __ASSEMBLY__ */
3704 
3705 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR6 register. */
3706 #define ALT_GIC_DIST_GICD_ISPENDR6_RESET 0x00000000
3707 /* The byte offset of the ALT_GIC_DIST_GICD_ISPENDR6 register from the beginning of the component. */
3708 #define ALT_GIC_DIST_GICD_ISPENDR6_OFST 0x218
3709 
3710 /*
3711  * Register : GICD_ISPENDR7
3712  *
3713  * Interrupt Set-Pending Registers
3714  *
3715  * Register Layout
3716  *
3717  * Bits | Access | Reset | Description
3718  * :-------|:-------|:------|:------------
3719  * [31:0] | RW | 0x0 | Empty
3720  *
3721  */
3722 /*
3723  * Field : Empty - fld
3724  *
3725  * Placeholder
3726  *
3727  * Field Access Macros:
3728  *
3729  */
3730 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISPENDR7_FLD register field. */
3731 #define ALT_GIC_DIST_GICD_ISPENDR7_FLD_LSB 0
3732 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISPENDR7_FLD register field. */
3733 #define ALT_GIC_DIST_GICD_ISPENDR7_FLD_MSB 31
3734 /* The width in bits of the ALT_GIC_DIST_GICD_ISPENDR7_FLD register field. */
3735 #define ALT_GIC_DIST_GICD_ISPENDR7_FLD_WIDTH 32
3736 /* The mask used to set the ALT_GIC_DIST_GICD_ISPENDR7_FLD register field value. */
3737 #define ALT_GIC_DIST_GICD_ISPENDR7_FLD_SET_MSK 0xffffffff
3738 /* The mask used to clear the ALT_GIC_DIST_GICD_ISPENDR7_FLD register field value. */
3739 #define ALT_GIC_DIST_GICD_ISPENDR7_FLD_CLR_MSK 0x00000000
3740 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR7_FLD register field. */
3741 #define ALT_GIC_DIST_GICD_ISPENDR7_FLD_RESET 0x0
3742 /* Extracts the ALT_GIC_DIST_GICD_ISPENDR7_FLD field value from a register. */
3743 #define ALT_GIC_DIST_GICD_ISPENDR7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3744 /* Produces a ALT_GIC_DIST_GICD_ISPENDR7_FLD register field value suitable for setting the register. */
3745 #define ALT_GIC_DIST_GICD_ISPENDR7_FLD_SET(value) (((value) << 0) & 0xffffffff)
3746 
3747 #ifndef __ASSEMBLY__
3748 /*
3749  * WARNING: The C register and register group struct declarations are provided for
3750  * convenience and illustrative purposes. They should, however, be used with
3751  * caution as the C language standard provides no guarantees about the alignment or
3752  * atomicity of device memory accesses. The recommended practice for coding device
3753  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3754  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3755  * alt_write_dword() functions for 64 bit registers.
3756  *
3757  * The struct declaration for register ALT_GIC_DIST_GICD_ISPENDR7.
3758  */
3759 struct ALT_GIC_DIST_GICD_ISPENDR7_s
3760 {
3761  volatile uint32_t fld : 32; /* Empty */
3762 };
3763 
3764 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISPENDR7. */
3765 typedef struct ALT_GIC_DIST_GICD_ISPENDR7_s ALT_GIC_DIST_GICD_ISPENDR7_t;
3766 #endif /* __ASSEMBLY__ */
3767 
3768 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR7 register. */
3769 #define ALT_GIC_DIST_GICD_ISPENDR7_RESET 0x00000000
3770 /* The byte offset of the ALT_GIC_DIST_GICD_ISPENDR7 register from the beginning of the component. */
3771 #define ALT_GIC_DIST_GICD_ISPENDR7_OFST 0x21c
3772 
3773 /*
3774  * Register : GICD_ISPENDR8
3775  *
3776  * Interrupt Set-Pending Registers
3777  *
3778  * Register Layout
3779  *
3780  * Bits | Access | Reset | Description
3781  * :-------|:-------|:------|:------------
3782  * [31:0] | RW | 0x0 | Empty
3783  *
3784  */
3785 /*
3786  * Field : Empty - fld
3787  *
3788  * Placeholder
3789  *
3790  * Field Access Macros:
3791  *
3792  */
3793 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISPENDR8_FLD register field. */
3794 #define ALT_GIC_DIST_GICD_ISPENDR8_FLD_LSB 0
3795 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISPENDR8_FLD register field. */
3796 #define ALT_GIC_DIST_GICD_ISPENDR8_FLD_MSB 31
3797 /* The width in bits of the ALT_GIC_DIST_GICD_ISPENDR8_FLD register field. */
3798 #define ALT_GIC_DIST_GICD_ISPENDR8_FLD_WIDTH 32
3799 /* The mask used to set the ALT_GIC_DIST_GICD_ISPENDR8_FLD register field value. */
3800 #define ALT_GIC_DIST_GICD_ISPENDR8_FLD_SET_MSK 0xffffffff
3801 /* The mask used to clear the ALT_GIC_DIST_GICD_ISPENDR8_FLD register field value. */
3802 #define ALT_GIC_DIST_GICD_ISPENDR8_FLD_CLR_MSK 0x00000000
3803 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR8_FLD register field. */
3804 #define ALT_GIC_DIST_GICD_ISPENDR8_FLD_RESET 0x0
3805 /* Extracts the ALT_GIC_DIST_GICD_ISPENDR8_FLD field value from a register. */
3806 #define ALT_GIC_DIST_GICD_ISPENDR8_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3807 /* Produces a ALT_GIC_DIST_GICD_ISPENDR8_FLD register field value suitable for setting the register. */
3808 #define ALT_GIC_DIST_GICD_ISPENDR8_FLD_SET(value) (((value) << 0) & 0xffffffff)
3809 
3810 #ifndef __ASSEMBLY__
3811 /*
3812  * WARNING: The C register and register group struct declarations are provided for
3813  * convenience and illustrative purposes. They should, however, be used with
3814  * caution as the C language standard provides no guarantees about the alignment or
3815  * atomicity of device memory accesses. The recommended practice for coding device
3816  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3817  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3818  * alt_write_dword() functions for 64 bit registers.
3819  *
3820  * The struct declaration for register ALT_GIC_DIST_GICD_ISPENDR8.
3821  */
3822 struct ALT_GIC_DIST_GICD_ISPENDR8_s
3823 {
3824  volatile uint32_t fld : 32; /* Empty */
3825 };
3826 
3827 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISPENDR8. */
3828 typedef struct ALT_GIC_DIST_GICD_ISPENDR8_s ALT_GIC_DIST_GICD_ISPENDR8_t;
3829 #endif /* __ASSEMBLY__ */
3830 
3831 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR8 register. */
3832 #define ALT_GIC_DIST_GICD_ISPENDR8_RESET 0x00000000
3833 /* The byte offset of the ALT_GIC_DIST_GICD_ISPENDR8 register from the beginning of the component. */
3834 #define ALT_GIC_DIST_GICD_ISPENDR8_OFST 0x220
3835 
3836 /*
3837  * Register : GICD_ISPENDR9
3838  *
3839  * Interrupt Set-Pending Registers
3840  *
3841  * Register Layout
3842  *
3843  * Bits | Access | Reset | Description
3844  * :-------|:-------|:------|:------------
3845  * [31:0] | RW | 0x0 | Empty
3846  *
3847  */
3848 /*
3849  * Field : Empty - fld
3850  *
3851  * Placeholder
3852  *
3853  * Field Access Macros:
3854  *
3855  */
3856 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISPENDR9_FLD register field. */
3857 #define ALT_GIC_DIST_GICD_ISPENDR9_FLD_LSB 0
3858 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISPENDR9_FLD register field. */
3859 #define ALT_GIC_DIST_GICD_ISPENDR9_FLD_MSB 31
3860 /* The width in bits of the ALT_GIC_DIST_GICD_ISPENDR9_FLD register field. */
3861 #define ALT_GIC_DIST_GICD_ISPENDR9_FLD_WIDTH 32
3862 /* The mask used to set the ALT_GIC_DIST_GICD_ISPENDR9_FLD register field value. */
3863 #define ALT_GIC_DIST_GICD_ISPENDR9_FLD_SET_MSK 0xffffffff
3864 /* The mask used to clear the ALT_GIC_DIST_GICD_ISPENDR9_FLD register field value. */
3865 #define ALT_GIC_DIST_GICD_ISPENDR9_FLD_CLR_MSK 0x00000000
3866 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR9_FLD register field. */
3867 #define ALT_GIC_DIST_GICD_ISPENDR9_FLD_RESET 0x0
3868 /* Extracts the ALT_GIC_DIST_GICD_ISPENDR9_FLD field value from a register. */
3869 #define ALT_GIC_DIST_GICD_ISPENDR9_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3870 /* Produces a ALT_GIC_DIST_GICD_ISPENDR9_FLD register field value suitable for setting the register. */
3871 #define ALT_GIC_DIST_GICD_ISPENDR9_FLD_SET(value) (((value) << 0) & 0xffffffff)
3872 
3873 #ifndef __ASSEMBLY__
3874 /*
3875  * WARNING: The C register and register group struct declarations are provided for
3876  * convenience and illustrative purposes. They should, however, be used with
3877  * caution as the C language standard provides no guarantees about the alignment or
3878  * atomicity of device memory accesses. The recommended practice for coding device
3879  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3880  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3881  * alt_write_dword() functions for 64 bit registers.
3882  *
3883  * The struct declaration for register ALT_GIC_DIST_GICD_ISPENDR9.
3884  */
3885 struct ALT_GIC_DIST_GICD_ISPENDR9_s
3886 {
3887  volatile uint32_t fld : 32; /* Empty */
3888 };
3889 
3890 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISPENDR9. */
3891 typedef struct ALT_GIC_DIST_GICD_ISPENDR9_s ALT_GIC_DIST_GICD_ISPENDR9_t;
3892 #endif /* __ASSEMBLY__ */
3893 
3894 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR9 register. */
3895 #define ALT_GIC_DIST_GICD_ISPENDR9_RESET 0x00000000
3896 /* The byte offset of the ALT_GIC_DIST_GICD_ISPENDR9 register from the beginning of the component. */
3897 #define ALT_GIC_DIST_GICD_ISPENDR9_OFST 0x224
3898 
3899 /*
3900  * Register : GICD_ISPENDR10
3901  *
3902  * Interrupt Set-Pending Registers
3903  *
3904  * Register Layout
3905  *
3906  * Bits | Access | Reset | Description
3907  * :-------|:-------|:------|:------------
3908  * [31:0] | RW | 0x0 | Empty
3909  *
3910  */
3911 /*
3912  * Field : Empty - fld
3913  *
3914  * Placeholder
3915  *
3916  * Field Access Macros:
3917  *
3918  */
3919 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISPENDR10_FLD register field. */
3920 #define ALT_GIC_DIST_GICD_ISPENDR10_FLD_LSB 0
3921 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISPENDR10_FLD register field. */
3922 #define ALT_GIC_DIST_GICD_ISPENDR10_FLD_MSB 31
3923 /* The width in bits of the ALT_GIC_DIST_GICD_ISPENDR10_FLD register field. */
3924 #define ALT_GIC_DIST_GICD_ISPENDR10_FLD_WIDTH 32
3925 /* The mask used to set the ALT_GIC_DIST_GICD_ISPENDR10_FLD register field value. */
3926 #define ALT_GIC_DIST_GICD_ISPENDR10_FLD_SET_MSK 0xffffffff
3927 /* The mask used to clear the ALT_GIC_DIST_GICD_ISPENDR10_FLD register field value. */
3928 #define ALT_GIC_DIST_GICD_ISPENDR10_FLD_CLR_MSK 0x00000000
3929 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR10_FLD register field. */
3930 #define ALT_GIC_DIST_GICD_ISPENDR10_FLD_RESET 0x0
3931 /* Extracts the ALT_GIC_DIST_GICD_ISPENDR10_FLD field value from a register. */
3932 #define ALT_GIC_DIST_GICD_ISPENDR10_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3933 /* Produces a ALT_GIC_DIST_GICD_ISPENDR10_FLD register field value suitable for setting the register. */
3934 #define ALT_GIC_DIST_GICD_ISPENDR10_FLD_SET(value) (((value) << 0) & 0xffffffff)
3935 
3936 #ifndef __ASSEMBLY__
3937 /*
3938  * WARNING: The C register and register group struct declarations are provided for
3939  * convenience and illustrative purposes. They should, however, be used with
3940  * caution as the C language standard provides no guarantees about the alignment or
3941  * atomicity of device memory accesses. The recommended practice for coding device
3942  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3943  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3944  * alt_write_dword() functions for 64 bit registers.
3945  *
3946  * The struct declaration for register ALT_GIC_DIST_GICD_ISPENDR10.
3947  */
3948 struct ALT_GIC_DIST_GICD_ISPENDR10_s
3949 {
3950  volatile uint32_t fld : 32; /* Empty */
3951 };
3952 
3953 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISPENDR10. */
3954 typedef struct ALT_GIC_DIST_GICD_ISPENDR10_s ALT_GIC_DIST_GICD_ISPENDR10_t;
3955 #endif /* __ASSEMBLY__ */
3956 
3957 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR10 register. */
3958 #define ALT_GIC_DIST_GICD_ISPENDR10_RESET 0x00000000
3959 /* The byte offset of the ALT_GIC_DIST_GICD_ISPENDR10 register from the beginning of the component. */
3960 #define ALT_GIC_DIST_GICD_ISPENDR10_OFST 0x228
3961 
3962 /*
3963  * Register : GICD_ISPENDR11
3964  *
3965  * Interrupt Set-Pending Registers
3966  *
3967  * Register Layout
3968  *
3969  * Bits | Access | Reset | Description
3970  * :-------|:-------|:------|:------------
3971  * [31:0] | RW | 0x0 | Empty
3972  *
3973  */
3974 /*
3975  * Field : Empty - fld
3976  *
3977  * Placeholder
3978  *
3979  * Field Access Macros:
3980  *
3981  */
3982 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISPENDR11_FLD register field. */
3983 #define ALT_GIC_DIST_GICD_ISPENDR11_FLD_LSB 0
3984 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISPENDR11_FLD register field. */
3985 #define ALT_GIC_DIST_GICD_ISPENDR11_FLD_MSB 31
3986 /* The width in bits of the ALT_GIC_DIST_GICD_ISPENDR11_FLD register field. */
3987 #define ALT_GIC_DIST_GICD_ISPENDR11_FLD_WIDTH 32
3988 /* The mask used to set the ALT_GIC_DIST_GICD_ISPENDR11_FLD register field value. */
3989 #define ALT_GIC_DIST_GICD_ISPENDR11_FLD_SET_MSK 0xffffffff
3990 /* The mask used to clear the ALT_GIC_DIST_GICD_ISPENDR11_FLD register field value. */
3991 #define ALT_GIC_DIST_GICD_ISPENDR11_FLD_CLR_MSK 0x00000000
3992 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR11_FLD register field. */
3993 #define ALT_GIC_DIST_GICD_ISPENDR11_FLD_RESET 0x0
3994 /* Extracts the ALT_GIC_DIST_GICD_ISPENDR11_FLD field value from a register. */
3995 #define ALT_GIC_DIST_GICD_ISPENDR11_FLD_GET(value) (((value) & 0xffffffff) >> 0)
3996 /* Produces a ALT_GIC_DIST_GICD_ISPENDR11_FLD register field value suitable for setting the register. */
3997 #define ALT_GIC_DIST_GICD_ISPENDR11_FLD_SET(value) (((value) << 0) & 0xffffffff)
3998 
3999 #ifndef __ASSEMBLY__
4000 /*
4001  * WARNING: The C register and register group struct declarations are provided for
4002  * convenience and illustrative purposes. They should, however, be used with
4003  * caution as the C language standard provides no guarantees about the alignment or
4004  * atomicity of device memory accesses. The recommended practice for coding device
4005  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4006  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4007  * alt_write_dword() functions for 64 bit registers.
4008  *
4009  * The struct declaration for register ALT_GIC_DIST_GICD_ISPENDR11.
4010  */
4011 struct ALT_GIC_DIST_GICD_ISPENDR11_s
4012 {
4013  volatile uint32_t fld : 32; /* Empty */
4014 };
4015 
4016 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISPENDR11. */
4017 typedef struct ALT_GIC_DIST_GICD_ISPENDR11_s ALT_GIC_DIST_GICD_ISPENDR11_t;
4018 #endif /* __ASSEMBLY__ */
4019 
4020 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR11 register. */
4021 #define ALT_GIC_DIST_GICD_ISPENDR11_RESET 0x00000000
4022 /* The byte offset of the ALT_GIC_DIST_GICD_ISPENDR11 register from the beginning of the component. */
4023 #define ALT_GIC_DIST_GICD_ISPENDR11_OFST 0x22c
4024 
4025 /*
4026  * Register : GICD_ISPENDR12
4027  *
4028  * Interrupt Set-Pending Registers
4029  *
4030  * Register Layout
4031  *
4032  * Bits | Access | Reset | Description
4033  * :-------|:-------|:------|:------------
4034  * [31:0] | RW | 0x0 | Empty
4035  *
4036  */
4037 /*
4038  * Field : Empty - fld
4039  *
4040  * Placeholder
4041  *
4042  * Field Access Macros:
4043  *
4044  */
4045 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISPENDR12_FLD register field. */
4046 #define ALT_GIC_DIST_GICD_ISPENDR12_FLD_LSB 0
4047 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISPENDR12_FLD register field. */
4048 #define ALT_GIC_DIST_GICD_ISPENDR12_FLD_MSB 31
4049 /* The width in bits of the ALT_GIC_DIST_GICD_ISPENDR12_FLD register field. */
4050 #define ALT_GIC_DIST_GICD_ISPENDR12_FLD_WIDTH 32
4051 /* The mask used to set the ALT_GIC_DIST_GICD_ISPENDR12_FLD register field value. */
4052 #define ALT_GIC_DIST_GICD_ISPENDR12_FLD_SET_MSK 0xffffffff
4053 /* The mask used to clear the ALT_GIC_DIST_GICD_ISPENDR12_FLD register field value. */
4054 #define ALT_GIC_DIST_GICD_ISPENDR12_FLD_CLR_MSK 0x00000000
4055 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR12_FLD register field. */
4056 #define ALT_GIC_DIST_GICD_ISPENDR12_FLD_RESET 0x0
4057 /* Extracts the ALT_GIC_DIST_GICD_ISPENDR12_FLD field value from a register. */
4058 #define ALT_GIC_DIST_GICD_ISPENDR12_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4059 /* Produces a ALT_GIC_DIST_GICD_ISPENDR12_FLD register field value suitable for setting the register. */
4060 #define ALT_GIC_DIST_GICD_ISPENDR12_FLD_SET(value) (((value) << 0) & 0xffffffff)
4061 
4062 #ifndef __ASSEMBLY__
4063 /*
4064  * WARNING: The C register and register group struct declarations are provided for
4065  * convenience and illustrative purposes. They should, however, be used with
4066  * caution as the C language standard provides no guarantees about the alignment or
4067  * atomicity of device memory accesses. The recommended practice for coding device
4068  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4069  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4070  * alt_write_dword() functions for 64 bit registers.
4071  *
4072  * The struct declaration for register ALT_GIC_DIST_GICD_ISPENDR12.
4073  */
4074 struct ALT_GIC_DIST_GICD_ISPENDR12_s
4075 {
4076  volatile uint32_t fld : 32; /* Empty */
4077 };
4078 
4079 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISPENDR12. */
4080 typedef struct ALT_GIC_DIST_GICD_ISPENDR12_s ALT_GIC_DIST_GICD_ISPENDR12_t;
4081 #endif /* __ASSEMBLY__ */
4082 
4083 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR12 register. */
4084 #define ALT_GIC_DIST_GICD_ISPENDR12_RESET 0x00000000
4085 /* The byte offset of the ALT_GIC_DIST_GICD_ISPENDR12 register from the beginning of the component. */
4086 #define ALT_GIC_DIST_GICD_ISPENDR12_OFST 0x230
4087 
4088 /*
4089  * Register : GICD_ISPENDR13
4090  *
4091  * Interrupt Set-Pending Registers
4092  *
4093  * Register Layout
4094  *
4095  * Bits | Access | Reset | Description
4096  * :-------|:-------|:------|:------------
4097  * [31:0] | RW | 0x0 | Empty
4098  *
4099  */
4100 /*
4101  * Field : Empty - fld
4102  *
4103  * Placeholder
4104  *
4105  * Field Access Macros:
4106  *
4107  */
4108 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISPENDR13_FLD register field. */
4109 #define ALT_GIC_DIST_GICD_ISPENDR13_FLD_LSB 0
4110 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISPENDR13_FLD register field. */
4111 #define ALT_GIC_DIST_GICD_ISPENDR13_FLD_MSB 31
4112 /* The width in bits of the ALT_GIC_DIST_GICD_ISPENDR13_FLD register field. */
4113 #define ALT_GIC_DIST_GICD_ISPENDR13_FLD_WIDTH 32
4114 /* The mask used to set the ALT_GIC_DIST_GICD_ISPENDR13_FLD register field value. */
4115 #define ALT_GIC_DIST_GICD_ISPENDR13_FLD_SET_MSK 0xffffffff
4116 /* The mask used to clear the ALT_GIC_DIST_GICD_ISPENDR13_FLD register field value. */
4117 #define ALT_GIC_DIST_GICD_ISPENDR13_FLD_CLR_MSK 0x00000000
4118 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR13_FLD register field. */
4119 #define ALT_GIC_DIST_GICD_ISPENDR13_FLD_RESET 0x0
4120 /* Extracts the ALT_GIC_DIST_GICD_ISPENDR13_FLD field value from a register. */
4121 #define ALT_GIC_DIST_GICD_ISPENDR13_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4122 /* Produces a ALT_GIC_DIST_GICD_ISPENDR13_FLD register field value suitable for setting the register. */
4123 #define ALT_GIC_DIST_GICD_ISPENDR13_FLD_SET(value) (((value) << 0) & 0xffffffff)
4124 
4125 #ifndef __ASSEMBLY__
4126 /*
4127  * WARNING: The C register and register group struct declarations are provided for
4128  * convenience and illustrative purposes. They should, however, be used with
4129  * caution as the C language standard provides no guarantees about the alignment or
4130  * atomicity of device memory accesses. The recommended practice for coding device
4131  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4132  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4133  * alt_write_dword() functions for 64 bit registers.
4134  *
4135  * The struct declaration for register ALT_GIC_DIST_GICD_ISPENDR13.
4136  */
4137 struct ALT_GIC_DIST_GICD_ISPENDR13_s
4138 {
4139  volatile uint32_t fld : 32; /* Empty */
4140 };
4141 
4142 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISPENDR13. */
4143 typedef struct ALT_GIC_DIST_GICD_ISPENDR13_s ALT_GIC_DIST_GICD_ISPENDR13_t;
4144 #endif /* __ASSEMBLY__ */
4145 
4146 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR13 register. */
4147 #define ALT_GIC_DIST_GICD_ISPENDR13_RESET 0x00000000
4148 /* The byte offset of the ALT_GIC_DIST_GICD_ISPENDR13 register from the beginning of the component. */
4149 #define ALT_GIC_DIST_GICD_ISPENDR13_OFST 0x234
4150 
4151 /*
4152  * Register : GICD_ISPENDR14
4153  *
4154  * Interrupt Set-Pending Registers
4155  *
4156  * Register Layout
4157  *
4158  * Bits | Access | Reset | Description
4159  * :-------|:-------|:------|:------------
4160  * [31:0] | RW | 0x0 | Empty
4161  *
4162  */
4163 /*
4164  * Field : Empty - fld
4165  *
4166  * Placeholder
4167  *
4168  * Field Access Macros:
4169  *
4170  */
4171 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISPENDR14_FLD register field. */
4172 #define ALT_GIC_DIST_GICD_ISPENDR14_FLD_LSB 0
4173 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISPENDR14_FLD register field. */
4174 #define ALT_GIC_DIST_GICD_ISPENDR14_FLD_MSB 31
4175 /* The width in bits of the ALT_GIC_DIST_GICD_ISPENDR14_FLD register field. */
4176 #define ALT_GIC_DIST_GICD_ISPENDR14_FLD_WIDTH 32
4177 /* The mask used to set the ALT_GIC_DIST_GICD_ISPENDR14_FLD register field value. */
4178 #define ALT_GIC_DIST_GICD_ISPENDR14_FLD_SET_MSK 0xffffffff
4179 /* The mask used to clear the ALT_GIC_DIST_GICD_ISPENDR14_FLD register field value. */
4180 #define ALT_GIC_DIST_GICD_ISPENDR14_FLD_CLR_MSK 0x00000000
4181 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR14_FLD register field. */
4182 #define ALT_GIC_DIST_GICD_ISPENDR14_FLD_RESET 0x0
4183 /* Extracts the ALT_GIC_DIST_GICD_ISPENDR14_FLD field value from a register. */
4184 #define ALT_GIC_DIST_GICD_ISPENDR14_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4185 /* Produces a ALT_GIC_DIST_GICD_ISPENDR14_FLD register field value suitable for setting the register. */
4186 #define ALT_GIC_DIST_GICD_ISPENDR14_FLD_SET(value) (((value) << 0) & 0xffffffff)
4187 
4188 #ifndef __ASSEMBLY__
4189 /*
4190  * WARNING: The C register and register group struct declarations are provided for
4191  * convenience and illustrative purposes. They should, however, be used with
4192  * caution as the C language standard provides no guarantees about the alignment or
4193  * atomicity of device memory accesses. The recommended practice for coding device
4194  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4195  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4196  * alt_write_dword() functions for 64 bit registers.
4197  *
4198  * The struct declaration for register ALT_GIC_DIST_GICD_ISPENDR14.
4199  */
4200 struct ALT_GIC_DIST_GICD_ISPENDR14_s
4201 {
4202  volatile uint32_t fld : 32; /* Empty */
4203 };
4204 
4205 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISPENDR14. */
4206 typedef struct ALT_GIC_DIST_GICD_ISPENDR14_s ALT_GIC_DIST_GICD_ISPENDR14_t;
4207 #endif /* __ASSEMBLY__ */
4208 
4209 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR14 register. */
4210 #define ALT_GIC_DIST_GICD_ISPENDR14_RESET 0x00000000
4211 /* The byte offset of the ALT_GIC_DIST_GICD_ISPENDR14 register from the beginning of the component. */
4212 #define ALT_GIC_DIST_GICD_ISPENDR14_OFST 0x238
4213 
4214 /*
4215  * Register : GICD_ISPENDR15
4216  *
4217  * Interrupt Set-Pending Registers
4218  *
4219  * Register Layout
4220  *
4221  * Bits | Access | Reset | Description
4222  * :-------|:-------|:------|:------------
4223  * [31:0] | RW | 0x0 | Empty
4224  *
4225  */
4226 /*
4227  * Field : Empty - fld
4228  *
4229  * Placeholder
4230  *
4231  * Field Access Macros:
4232  *
4233  */
4234 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISPENDR15_FLD register field. */
4235 #define ALT_GIC_DIST_GICD_ISPENDR15_FLD_LSB 0
4236 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISPENDR15_FLD register field. */
4237 #define ALT_GIC_DIST_GICD_ISPENDR15_FLD_MSB 31
4238 /* The width in bits of the ALT_GIC_DIST_GICD_ISPENDR15_FLD register field. */
4239 #define ALT_GIC_DIST_GICD_ISPENDR15_FLD_WIDTH 32
4240 /* The mask used to set the ALT_GIC_DIST_GICD_ISPENDR15_FLD register field value. */
4241 #define ALT_GIC_DIST_GICD_ISPENDR15_FLD_SET_MSK 0xffffffff
4242 /* The mask used to clear the ALT_GIC_DIST_GICD_ISPENDR15_FLD register field value. */
4243 #define ALT_GIC_DIST_GICD_ISPENDR15_FLD_CLR_MSK 0x00000000
4244 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR15_FLD register field. */
4245 #define ALT_GIC_DIST_GICD_ISPENDR15_FLD_RESET 0x0
4246 /* Extracts the ALT_GIC_DIST_GICD_ISPENDR15_FLD field value from a register. */
4247 #define ALT_GIC_DIST_GICD_ISPENDR15_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4248 /* Produces a ALT_GIC_DIST_GICD_ISPENDR15_FLD register field value suitable for setting the register. */
4249 #define ALT_GIC_DIST_GICD_ISPENDR15_FLD_SET(value) (((value) << 0) & 0xffffffff)
4250 
4251 #ifndef __ASSEMBLY__
4252 /*
4253  * WARNING: The C register and register group struct declarations are provided for
4254  * convenience and illustrative purposes. They should, however, be used with
4255  * caution as the C language standard provides no guarantees about the alignment or
4256  * atomicity of device memory accesses. The recommended practice for coding device
4257  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4258  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4259  * alt_write_dword() functions for 64 bit registers.
4260  *
4261  * The struct declaration for register ALT_GIC_DIST_GICD_ISPENDR15.
4262  */
4263 struct ALT_GIC_DIST_GICD_ISPENDR15_s
4264 {
4265  volatile uint32_t fld : 32; /* Empty */
4266 };
4267 
4268 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISPENDR15. */
4269 typedef struct ALT_GIC_DIST_GICD_ISPENDR15_s ALT_GIC_DIST_GICD_ISPENDR15_t;
4270 #endif /* __ASSEMBLY__ */
4271 
4272 /* The reset value of the ALT_GIC_DIST_GICD_ISPENDR15 register. */
4273 #define ALT_GIC_DIST_GICD_ISPENDR15_RESET 0x00000000
4274 /* The byte offset of the ALT_GIC_DIST_GICD_ISPENDR15 register from the beginning of the component. */
4275 #define ALT_GIC_DIST_GICD_ISPENDR15_OFST 0x23c
4276 
4277 /*
4278  * Register : GICD_ICPENDR0
4279  *
4280  * Interrupt Clear-Pending Registers
4281  *
4282  * Register Layout
4283  *
4284  * Bits | Access | Reset | Description
4285  * :-------|:-------|:------|:------------
4286  * [31:0] | RW | 0x0 | Empty
4287  *
4288  */
4289 /*
4290  * Field : Empty - fld
4291  *
4292  * Placeholder
4293  *
4294  * Field Access Macros:
4295  *
4296  */
4297 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICPENDR0_FLD register field. */
4298 #define ALT_GIC_DIST_GICD_ICPENDR0_FLD_LSB 0
4299 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICPENDR0_FLD register field. */
4300 #define ALT_GIC_DIST_GICD_ICPENDR0_FLD_MSB 31
4301 /* The width in bits of the ALT_GIC_DIST_GICD_ICPENDR0_FLD register field. */
4302 #define ALT_GIC_DIST_GICD_ICPENDR0_FLD_WIDTH 32
4303 /* The mask used to set the ALT_GIC_DIST_GICD_ICPENDR0_FLD register field value. */
4304 #define ALT_GIC_DIST_GICD_ICPENDR0_FLD_SET_MSK 0xffffffff
4305 /* The mask used to clear the ALT_GIC_DIST_GICD_ICPENDR0_FLD register field value. */
4306 #define ALT_GIC_DIST_GICD_ICPENDR0_FLD_CLR_MSK 0x00000000
4307 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR0_FLD register field. */
4308 #define ALT_GIC_DIST_GICD_ICPENDR0_FLD_RESET 0x0
4309 /* Extracts the ALT_GIC_DIST_GICD_ICPENDR0_FLD field value from a register. */
4310 #define ALT_GIC_DIST_GICD_ICPENDR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4311 /* Produces a ALT_GIC_DIST_GICD_ICPENDR0_FLD register field value suitable for setting the register. */
4312 #define ALT_GIC_DIST_GICD_ICPENDR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
4313 
4314 #ifndef __ASSEMBLY__
4315 /*
4316  * WARNING: The C register and register group struct declarations are provided for
4317  * convenience and illustrative purposes. They should, however, be used with
4318  * caution as the C language standard provides no guarantees about the alignment or
4319  * atomicity of device memory accesses. The recommended practice for coding device
4320  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4321  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4322  * alt_write_dword() functions for 64 bit registers.
4323  *
4324  * The struct declaration for register ALT_GIC_DIST_GICD_ICPENDR0.
4325  */
4326 struct ALT_GIC_DIST_GICD_ICPENDR0_s
4327 {
4328  volatile uint32_t fld : 32; /* Empty */
4329 };
4330 
4331 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICPENDR0. */
4332 typedef struct ALT_GIC_DIST_GICD_ICPENDR0_s ALT_GIC_DIST_GICD_ICPENDR0_t;
4333 #endif /* __ASSEMBLY__ */
4334 
4335 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR0 register. */
4336 #define ALT_GIC_DIST_GICD_ICPENDR0_RESET 0x00000000
4337 /* The byte offset of the ALT_GIC_DIST_GICD_ICPENDR0 register from the beginning of the component. */
4338 #define ALT_GIC_DIST_GICD_ICPENDR0_OFST 0x280
4339 
4340 /*
4341  * Register : GICD_ICPENDR1
4342  *
4343  * Interrupt Clear-Pending Registers
4344  *
4345  * Register Layout
4346  *
4347  * Bits | Access | Reset | Description
4348  * :-------|:-------|:------|:------------
4349  * [31:0] | RW | 0x0 | Empty
4350  *
4351  */
4352 /*
4353  * Field : Empty - fld
4354  *
4355  * Placeholder
4356  *
4357  * Field Access Macros:
4358  *
4359  */
4360 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICPENDR1_FLD register field. */
4361 #define ALT_GIC_DIST_GICD_ICPENDR1_FLD_LSB 0
4362 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICPENDR1_FLD register field. */
4363 #define ALT_GIC_DIST_GICD_ICPENDR1_FLD_MSB 31
4364 /* The width in bits of the ALT_GIC_DIST_GICD_ICPENDR1_FLD register field. */
4365 #define ALT_GIC_DIST_GICD_ICPENDR1_FLD_WIDTH 32
4366 /* The mask used to set the ALT_GIC_DIST_GICD_ICPENDR1_FLD register field value. */
4367 #define ALT_GIC_DIST_GICD_ICPENDR1_FLD_SET_MSK 0xffffffff
4368 /* The mask used to clear the ALT_GIC_DIST_GICD_ICPENDR1_FLD register field value. */
4369 #define ALT_GIC_DIST_GICD_ICPENDR1_FLD_CLR_MSK 0x00000000
4370 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR1_FLD register field. */
4371 #define ALT_GIC_DIST_GICD_ICPENDR1_FLD_RESET 0x0
4372 /* Extracts the ALT_GIC_DIST_GICD_ICPENDR1_FLD field value from a register. */
4373 #define ALT_GIC_DIST_GICD_ICPENDR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4374 /* Produces a ALT_GIC_DIST_GICD_ICPENDR1_FLD register field value suitable for setting the register. */
4375 #define ALT_GIC_DIST_GICD_ICPENDR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
4376 
4377 #ifndef __ASSEMBLY__
4378 /*
4379  * WARNING: The C register and register group struct declarations are provided for
4380  * convenience and illustrative purposes. They should, however, be used with
4381  * caution as the C language standard provides no guarantees about the alignment or
4382  * atomicity of device memory accesses. The recommended practice for coding device
4383  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4384  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4385  * alt_write_dword() functions for 64 bit registers.
4386  *
4387  * The struct declaration for register ALT_GIC_DIST_GICD_ICPENDR1.
4388  */
4389 struct ALT_GIC_DIST_GICD_ICPENDR1_s
4390 {
4391  volatile uint32_t fld : 32; /* Empty */
4392 };
4393 
4394 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICPENDR1. */
4395 typedef struct ALT_GIC_DIST_GICD_ICPENDR1_s ALT_GIC_DIST_GICD_ICPENDR1_t;
4396 #endif /* __ASSEMBLY__ */
4397 
4398 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR1 register. */
4399 #define ALT_GIC_DIST_GICD_ICPENDR1_RESET 0x00000000
4400 /* The byte offset of the ALT_GIC_DIST_GICD_ICPENDR1 register from the beginning of the component. */
4401 #define ALT_GIC_DIST_GICD_ICPENDR1_OFST 0x284
4402 
4403 /*
4404  * Register : GICD_ICPENDR2
4405  *
4406  * Interrupt Clear-Pending Registers
4407  *
4408  * Register Layout
4409  *
4410  * Bits | Access | Reset | Description
4411  * :-------|:-------|:------|:------------
4412  * [31:0] | RW | 0x0 | Empty
4413  *
4414  */
4415 /*
4416  * Field : Empty - fld
4417  *
4418  * Placeholder
4419  *
4420  * Field Access Macros:
4421  *
4422  */
4423 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICPENDR2_FLD register field. */
4424 #define ALT_GIC_DIST_GICD_ICPENDR2_FLD_LSB 0
4425 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICPENDR2_FLD register field. */
4426 #define ALT_GIC_DIST_GICD_ICPENDR2_FLD_MSB 31
4427 /* The width in bits of the ALT_GIC_DIST_GICD_ICPENDR2_FLD register field. */
4428 #define ALT_GIC_DIST_GICD_ICPENDR2_FLD_WIDTH 32
4429 /* The mask used to set the ALT_GIC_DIST_GICD_ICPENDR2_FLD register field value. */
4430 #define ALT_GIC_DIST_GICD_ICPENDR2_FLD_SET_MSK 0xffffffff
4431 /* The mask used to clear the ALT_GIC_DIST_GICD_ICPENDR2_FLD register field value. */
4432 #define ALT_GIC_DIST_GICD_ICPENDR2_FLD_CLR_MSK 0x00000000
4433 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR2_FLD register field. */
4434 #define ALT_GIC_DIST_GICD_ICPENDR2_FLD_RESET 0x0
4435 /* Extracts the ALT_GIC_DIST_GICD_ICPENDR2_FLD field value from a register. */
4436 #define ALT_GIC_DIST_GICD_ICPENDR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4437 /* Produces a ALT_GIC_DIST_GICD_ICPENDR2_FLD register field value suitable for setting the register. */
4438 #define ALT_GIC_DIST_GICD_ICPENDR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
4439 
4440 #ifndef __ASSEMBLY__
4441 /*
4442  * WARNING: The C register and register group struct declarations are provided for
4443  * convenience and illustrative purposes. They should, however, be used with
4444  * caution as the C language standard provides no guarantees about the alignment or
4445  * atomicity of device memory accesses. The recommended practice for coding device
4446  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4447  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4448  * alt_write_dword() functions for 64 bit registers.
4449  *
4450  * The struct declaration for register ALT_GIC_DIST_GICD_ICPENDR2.
4451  */
4452 struct ALT_GIC_DIST_GICD_ICPENDR2_s
4453 {
4454  volatile uint32_t fld : 32; /* Empty */
4455 };
4456 
4457 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICPENDR2. */
4458 typedef struct ALT_GIC_DIST_GICD_ICPENDR2_s ALT_GIC_DIST_GICD_ICPENDR2_t;
4459 #endif /* __ASSEMBLY__ */
4460 
4461 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR2 register. */
4462 #define ALT_GIC_DIST_GICD_ICPENDR2_RESET 0x00000000
4463 /* The byte offset of the ALT_GIC_DIST_GICD_ICPENDR2 register from the beginning of the component. */
4464 #define ALT_GIC_DIST_GICD_ICPENDR2_OFST 0x288
4465 
4466 /*
4467  * Register : GICD_ICPENDR3
4468  *
4469  * Interrupt Clear-Pending Registers
4470  *
4471  * Register Layout
4472  *
4473  * Bits | Access | Reset | Description
4474  * :-------|:-------|:------|:------------
4475  * [31:0] | RW | 0x0 | Empty
4476  *
4477  */
4478 /*
4479  * Field : Empty - fld
4480  *
4481  * Placeholder
4482  *
4483  * Field Access Macros:
4484  *
4485  */
4486 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICPENDR3_FLD register field. */
4487 #define ALT_GIC_DIST_GICD_ICPENDR3_FLD_LSB 0
4488 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICPENDR3_FLD register field. */
4489 #define ALT_GIC_DIST_GICD_ICPENDR3_FLD_MSB 31
4490 /* The width in bits of the ALT_GIC_DIST_GICD_ICPENDR3_FLD register field. */
4491 #define ALT_GIC_DIST_GICD_ICPENDR3_FLD_WIDTH 32
4492 /* The mask used to set the ALT_GIC_DIST_GICD_ICPENDR3_FLD register field value. */
4493 #define ALT_GIC_DIST_GICD_ICPENDR3_FLD_SET_MSK 0xffffffff
4494 /* The mask used to clear the ALT_GIC_DIST_GICD_ICPENDR3_FLD register field value. */
4495 #define ALT_GIC_DIST_GICD_ICPENDR3_FLD_CLR_MSK 0x00000000
4496 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR3_FLD register field. */
4497 #define ALT_GIC_DIST_GICD_ICPENDR3_FLD_RESET 0x0
4498 /* Extracts the ALT_GIC_DIST_GICD_ICPENDR3_FLD field value from a register. */
4499 #define ALT_GIC_DIST_GICD_ICPENDR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4500 /* Produces a ALT_GIC_DIST_GICD_ICPENDR3_FLD register field value suitable for setting the register. */
4501 #define ALT_GIC_DIST_GICD_ICPENDR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
4502 
4503 #ifndef __ASSEMBLY__
4504 /*
4505  * WARNING: The C register and register group struct declarations are provided for
4506  * convenience and illustrative purposes. They should, however, be used with
4507  * caution as the C language standard provides no guarantees about the alignment or
4508  * atomicity of device memory accesses. The recommended practice for coding device
4509  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4510  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4511  * alt_write_dword() functions for 64 bit registers.
4512  *
4513  * The struct declaration for register ALT_GIC_DIST_GICD_ICPENDR3.
4514  */
4515 struct ALT_GIC_DIST_GICD_ICPENDR3_s
4516 {
4517  volatile uint32_t fld : 32; /* Empty */
4518 };
4519 
4520 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICPENDR3. */
4521 typedef struct ALT_GIC_DIST_GICD_ICPENDR3_s ALT_GIC_DIST_GICD_ICPENDR3_t;
4522 #endif /* __ASSEMBLY__ */
4523 
4524 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR3 register. */
4525 #define ALT_GIC_DIST_GICD_ICPENDR3_RESET 0x00000000
4526 /* The byte offset of the ALT_GIC_DIST_GICD_ICPENDR3 register from the beginning of the component. */
4527 #define ALT_GIC_DIST_GICD_ICPENDR3_OFST 0x28c
4528 
4529 /*
4530  * Register : GICD_ICPENDR4
4531  *
4532  * Interrupt Clear-Pending Registers
4533  *
4534  * Register Layout
4535  *
4536  * Bits | Access | Reset | Description
4537  * :-------|:-------|:------|:------------
4538  * [31:0] | RW | 0x0 | Empty
4539  *
4540  */
4541 /*
4542  * Field : Empty - fld
4543  *
4544  * Placeholder
4545  *
4546  * Field Access Macros:
4547  *
4548  */
4549 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICPENDR4_FLD register field. */
4550 #define ALT_GIC_DIST_GICD_ICPENDR4_FLD_LSB 0
4551 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICPENDR4_FLD register field. */
4552 #define ALT_GIC_DIST_GICD_ICPENDR4_FLD_MSB 31
4553 /* The width in bits of the ALT_GIC_DIST_GICD_ICPENDR4_FLD register field. */
4554 #define ALT_GIC_DIST_GICD_ICPENDR4_FLD_WIDTH 32
4555 /* The mask used to set the ALT_GIC_DIST_GICD_ICPENDR4_FLD register field value. */
4556 #define ALT_GIC_DIST_GICD_ICPENDR4_FLD_SET_MSK 0xffffffff
4557 /* The mask used to clear the ALT_GIC_DIST_GICD_ICPENDR4_FLD register field value. */
4558 #define ALT_GIC_DIST_GICD_ICPENDR4_FLD_CLR_MSK 0x00000000
4559 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR4_FLD register field. */
4560 #define ALT_GIC_DIST_GICD_ICPENDR4_FLD_RESET 0x0
4561 /* Extracts the ALT_GIC_DIST_GICD_ICPENDR4_FLD field value from a register. */
4562 #define ALT_GIC_DIST_GICD_ICPENDR4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4563 /* Produces a ALT_GIC_DIST_GICD_ICPENDR4_FLD register field value suitable for setting the register. */
4564 #define ALT_GIC_DIST_GICD_ICPENDR4_FLD_SET(value) (((value) << 0) & 0xffffffff)
4565 
4566 #ifndef __ASSEMBLY__
4567 /*
4568  * WARNING: The C register and register group struct declarations are provided for
4569  * convenience and illustrative purposes. They should, however, be used with
4570  * caution as the C language standard provides no guarantees about the alignment or
4571  * atomicity of device memory accesses. The recommended practice for coding device
4572  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4573  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4574  * alt_write_dword() functions for 64 bit registers.
4575  *
4576  * The struct declaration for register ALT_GIC_DIST_GICD_ICPENDR4.
4577  */
4578 struct ALT_GIC_DIST_GICD_ICPENDR4_s
4579 {
4580  volatile uint32_t fld : 32; /* Empty */
4581 };
4582 
4583 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICPENDR4. */
4584 typedef struct ALT_GIC_DIST_GICD_ICPENDR4_s ALT_GIC_DIST_GICD_ICPENDR4_t;
4585 #endif /* __ASSEMBLY__ */
4586 
4587 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR4 register. */
4588 #define ALT_GIC_DIST_GICD_ICPENDR4_RESET 0x00000000
4589 /* The byte offset of the ALT_GIC_DIST_GICD_ICPENDR4 register from the beginning of the component. */
4590 #define ALT_GIC_DIST_GICD_ICPENDR4_OFST 0x290
4591 
4592 /*
4593  * Register : GICD_ICPENDR5
4594  *
4595  * Interrupt Clear-Pending Registers
4596  *
4597  * Register Layout
4598  *
4599  * Bits | Access | Reset | Description
4600  * :-------|:-------|:------|:------------
4601  * [31:0] | RW | 0x0 | Empty
4602  *
4603  */
4604 /*
4605  * Field : Empty - fld
4606  *
4607  * Placeholder
4608  *
4609  * Field Access Macros:
4610  *
4611  */
4612 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICPENDR5_FLD register field. */
4613 #define ALT_GIC_DIST_GICD_ICPENDR5_FLD_LSB 0
4614 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICPENDR5_FLD register field. */
4615 #define ALT_GIC_DIST_GICD_ICPENDR5_FLD_MSB 31
4616 /* The width in bits of the ALT_GIC_DIST_GICD_ICPENDR5_FLD register field. */
4617 #define ALT_GIC_DIST_GICD_ICPENDR5_FLD_WIDTH 32
4618 /* The mask used to set the ALT_GIC_DIST_GICD_ICPENDR5_FLD register field value. */
4619 #define ALT_GIC_DIST_GICD_ICPENDR5_FLD_SET_MSK 0xffffffff
4620 /* The mask used to clear the ALT_GIC_DIST_GICD_ICPENDR5_FLD register field value. */
4621 #define ALT_GIC_DIST_GICD_ICPENDR5_FLD_CLR_MSK 0x00000000
4622 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR5_FLD register field. */
4623 #define ALT_GIC_DIST_GICD_ICPENDR5_FLD_RESET 0x0
4624 /* Extracts the ALT_GIC_DIST_GICD_ICPENDR5_FLD field value from a register. */
4625 #define ALT_GIC_DIST_GICD_ICPENDR5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4626 /* Produces a ALT_GIC_DIST_GICD_ICPENDR5_FLD register field value suitable for setting the register. */
4627 #define ALT_GIC_DIST_GICD_ICPENDR5_FLD_SET(value) (((value) << 0) & 0xffffffff)
4628 
4629 #ifndef __ASSEMBLY__
4630 /*
4631  * WARNING: The C register and register group struct declarations are provided for
4632  * convenience and illustrative purposes. They should, however, be used with
4633  * caution as the C language standard provides no guarantees about the alignment or
4634  * atomicity of device memory accesses. The recommended practice for coding device
4635  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4636  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4637  * alt_write_dword() functions for 64 bit registers.
4638  *
4639  * The struct declaration for register ALT_GIC_DIST_GICD_ICPENDR5.
4640  */
4641 struct ALT_GIC_DIST_GICD_ICPENDR5_s
4642 {
4643  volatile uint32_t fld : 32; /* Empty */
4644 };
4645 
4646 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICPENDR5. */
4647 typedef struct ALT_GIC_DIST_GICD_ICPENDR5_s ALT_GIC_DIST_GICD_ICPENDR5_t;
4648 #endif /* __ASSEMBLY__ */
4649 
4650 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR5 register. */
4651 #define ALT_GIC_DIST_GICD_ICPENDR5_RESET 0x00000000
4652 /* The byte offset of the ALT_GIC_DIST_GICD_ICPENDR5 register from the beginning of the component. */
4653 #define ALT_GIC_DIST_GICD_ICPENDR5_OFST 0x294
4654 
4655 /*
4656  * Register : GICD_ICPENDR6
4657  *
4658  * Interrupt Clear-Pending Registers
4659  *
4660  * Register Layout
4661  *
4662  * Bits | Access | Reset | Description
4663  * :-------|:-------|:------|:------------
4664  * [31:0] | RW | 0x0 | Empty
4665  *
4666  */
4667 /*
4668  * Field : Empty - fld
4669  *
4670  * Placeholder
4671  *
4672  * Field Access Macros:
4673  *
4674  */
4675 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICPENDR6_FLD register field. */
4676 #define ALT_GIC_DIST_GICD_ICPENDR6_FLD_LSB 0
4677 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICPENDR6_FLD register field. */
4678 #define ALT_GIC_DIST_GICD_ICPENDR6_FLD_MSB 31
4679 /* The width in bits of the ALT_GIC_DIST_GICD_ICPENDR6_FLD register field. */
4680 #define ALT_GIC_DIST_GICD_ICPENDR6_FLD_WIDTH 32
4681 /* The mask used to set the ALT_GIC_DIST_GICD_ICPENDR6_FLD register field value. */
4682 #define ALT_GIC_DIST_GICD_ICPENDR6_FLD_SET_MSK 0xffffffff
4683 /* The mask used to clear the ALT_GIC_DIST_GICD_ICPENDR6_FLD register field value. */
4684 #define ALT_GIC_DIST_GICD_ICPENDR6_FLD_CLR_MSK 0x00000000
4685 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR6_FLD register field. */
4686 #define ALT_GIC_DIST_GICD_ICPENDR6_FLD_RESET 0x0
4687 /* Extracts the ALT_GIC_DIST_GICD_ICPENDR6_FLD field value from a register. */
4688 #define ALT_GIC_DIST_GICD_ICPENDR6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4689 /* Produces a ALT_GIC_DIST_GICD_ICPENDR6_FLD register field value suitable for setting the register. */
4690 #define ALT_GIC_DIST_GICD_ICPENDR6_FLD_SET(value) (((value) << 0) & 0xffffffff)
4691 
4692 #ifndef __ASSEMBLY__
4693 /*
4694  * WARNING: The C register and register group struct declarations are provided for
4695  * convenience and illustrative purposes. They should, however, be used with
4696  * caution as the C language standard provides no guarantees about the alignment or
4697  * atomicity of device memory accesses. The recommended practice for coding device
4698  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4699  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4700  * alt_write_dword() functions for 64 bit registers.
4701  *
4702  * The struct declaration for register ALT_GIC_DIST_GICD_ICPENDR6.
4703  */
4704 struct ALT_GIC_DIST_GICD_ICPENDR6_s
4705 {
4706  volatile uint32_t fld : 32; /* Empty */
4707 };
4708 
4709 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICPENDR6. */
4710 typedef struct ALT_GIC_DIST_GICD_ICPENDR6_s ALT_GIC_DIST_GICD_ICPENDR6_t;
4711 #endif /* __ASSEMBLY__ */
4712 
4713 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR6 register. */
4714 #define ALT_GIC_DIST_GICD_ICPENDR6_RESET 0x00000000
4715 /* The byte offset of the ALT_GIC_DIST_GICD_ICPENDR6 register from the beginning of the component. */
4716 #define ALT_GIC_DIST_GICD_ICPENDR6_OFST 0x298
4717 
4718 /*
4719  * Register : GICD_ICPENDR7
4720  *
4721  * Interrupt Clear-Pending Registers
4722  *
4723  * Register Layout
4724  *
4725  * Bits | Access | Reset | Description
4726  * :-------|:-------|:------|:------------
4727  * [31:0] | RW | 0x0 | Empty
4728  *
4729  */
4730 /*
4731  * Field : Empty - fld
4732  *
4733  * Placeholder
4734  *
4735  * Field Access Macros:
4736  *
4737  */
4738 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICPENDR7_FLD register field. */
4739 #define ALT_GIC_DIST_GICD_ICPENDR7_FLD_LSB 0
4740 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICPENDR7_FLD register field. */
4741 #define ALT_GIC_DIST_GICD_ICPENDR7_FLD_MSB 31
4742 /* The width in bits of the ALT_GIC_DIST_GICD_ICPENDR7_FLD register field. */
4743 #define ALT_GIC_DIST_GICD_ICPENDR7_FLD_WIDTH 32
4744 /* The mask used to set the ALT_GIC_DIST_GICD_ICPENDR7_FLD register field value. */
4745 #define ALT_GIC_DIST_GICD_ICPENDR7_FLD_SET_MSK 0xffffffff
4746 /* The mask used to clear the ALT_GIC_DIST_GICD_ICPENDR7_FLD register field value. */
4747 #define ALT_GIC_DIST_GICD_ICPENDR7_FLD_CLR_MSK 0x00000000
4748 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR7_FLD register field. */
4749 #define ALT_GIC_DIST_GICD_ICPENDR7_FLD_RESET 0x0
4750 /* Extracts the ALT_GIC_DIST_GICD_ICPENDR7_FLD field value from a register. */
4751 #define ALT_GIC_DIST_GICD_ICPENDR7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4752 /* Produces a ALT_GIC_DIST_GICD_ICPENDR7_FLD register field value suitable for setting the register. */
4753 #define ALT_GIC_DIST_GICD_ICPENDR7_FLD_SET(value) (((value) << 0) & 0xffffffff)
4754 
4755 #ifndef __ASSEMBLY__
4756 /*
4757  * WARNING: The C register and register group struct declarations are provided for
4758  * convenience and illustrative purposes. They should, however, be used with
4759  * caution as the C language standard provides no guarantees about the alignment or
4760  * atomicity of device memory accesses. The recommended practice for coding device
4761  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4762  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4763  * alt_write_dword() functions for 64 bit registers.
4764  *
4765  * The struct declaration for register ALT_GIC_DIST_GICD_ICPENDR7.
4766  */
4767 struct ALT_GIC_DIST_GICD_ICPENDR7_s
4768 {
4769  volatile uint32_t fld : 32; /* Empty */
4770 };
4771 
4772 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICPENDR7. */
4773 typedef struct ALT_GIC_DIST_GICD_ICPENDR7_s ALT_GIC_DIST_GICD_ICPENDR7_t;
4774 #endif /* __ASSEMBLY__ */
4775 
4776 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR7 register. */
4777 #define ALT_GIC_DIST_GICD_ICPENDR7_RESET 0x00000000
4778 /* The byte offset of the ALT_GIC_DIST_GICD_ICPENDR7 register from the beginning of the component. */
4779 #define ALT_GIC_DIST_GICD_ICPENDR7_OFST 0x29c
4780 
4781 /*
4782  * Register : GICD_ICPENDR8
4783  *
4784  * Interrupt Clear-Pending Registers
4785  *
4786  * Register Layout
4787  *
4788  * Bits | Access | Reset | Description
4789  * :-------|:-------|:------|:------------
4790  * [31:0] | RW | 0x0 | Empty
4791  *
4792  */
4793 /*
4794  * Field : Empty - fld
4795  *
4796  * Placeholder
4797  *
4798  * Field Access Macros:
4799  *
4800  */
4801 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICPENDR8_FLD register field. */
4802 #define ALT_GIC_DIST_GICD_ICPENDR8_FLD_LSB 0
4803 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICPENDR8_FLD register field. */
4804 #define ALT_GIC_DIST_GICD_ICPENDR8_FLD_MSB 31
4805 /* The width in bits of the ALT_GIC_DIST_GICD_ICPENDR8_FLD register field. */
4806 #define ALT_GIC_DIST_GICD_ICPENDR8_FLD_WIDTH 32
4807 /* The mask used to set the ALT_GIC_DIST_GICD_ICPENDR8_FLD register field value. */
4808 #define ALT_GIC_DIST_GICD_ICPENDR8_FLD_SET_MSK 0xffffffff
4809 /* The mask used to clear the ALT_GIC_DIST_GICD_ICPENDR8_FLD register field value. */
4810 #define ALT_GIC_DIST_GICD_ICPENDR8_FLD_CLR_MSK 0x00000000
4811 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR8_FLD register field. */
4812 #define ALT_GIC_DIST_GICD_ICPENDR8_FLD_RESET 0x0
4813 /* Extracts the ALT_GIC_DIST_GICD_ICPENDR8_FLD field value from a register. */
4814 #define ALT_GIC_DIST_GICD_ICPENDR8_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4815 /* Produces a ALT_GIC_DIST_GICD_ICPENDR8_FLD register field value suitable for setting the register. */
4816 #define ALT_GIC_DIST_GICD_ICPENDR8_FLD_SET(value) (((value) << 0) & 0xffffffff)
4817 
4818 #ifndef __ASSEMBLY__
4819 /*
4820  * WARNING: The C register and register group struct declarations are provided for
4821  * convenience and illustrative purposes. They should, however, be used with
4822  * caution as the C language standard provides no guarantees about the alignment or
4823  * atomicity of device memory accesses. The recommended practice for coding device
4824  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4825  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4826  * alt_write_dword() functions for 64 bit registers.
4827  *
4828  * The struct declaration for register ALT_GIC_DIST_GICD_ICPENDR8.
4829  */
4830 struct ALT_GIC_DIST_GICD_ICPENDR8_s
4831 {
4832  volatile uint32_t fld : 32; /* Empty */
4833 };
4834 
4835 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICPENDR8. */
4836 typedef struct ALT_GIC_DIST_GICD_ICPENDR8_s ALT_GIC_DIST_GICD_ICPENDR8_t;
4837 #endif /* __ASSEMBLY__ */
4838 
4839 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR8 register. */
4840 #define ALT_GIC_DIST_GICD_ICPENDR8_RESET 0x00000000
4841 /* The byte offset of the ALT_GIC_DIST_GICD_ICPENDR8 register from the beginning of the component. */
4842 #define ALT_GIC_DIST_GICD_ICPENDR8_OFST 0x2a0
4843 
4844 /*
4845  * Register : GICD_ICPENDR9
4846  *
4847  * Interrupt Clear-Pending Registers
4848  *
4849  * Register Layout
4850  *
4851  * Bits | Access | Reset | Description
4852  * :-------|:-------|:------|:------------
4853  * [31:0] | RW | 0x0 | Empty
4854  *
4855  */
4856 /*
4857  * Field : Empty - fld
4858  *
4859  * Placeholder
4860  *
4861  * Field Access Macros:
4862  *
4863  */
4864 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICPENDR9_FLD register field. */
4865 #define ALT_GIC_DIST_GICD_ICPENDR9_FLD_LSB 0
4866 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICPENDR9_FLD register field. */
4867 #define ALT_GIC_DIST_GICD_ICPENDR9_FLD_MSB 31
4868 /* The width in bits of the ALT_GIC_DIST_GICD_ICPENDR9_FLD register field. */
4869 #define ALT_GIC_DIST_GICD_ICPENDR9_FLD_WIDTH 32
4870 /* The mask used to set the ALT_GIC_DIST_GICD_ICPENDR9_FLD register field value. */
4871 #define ALT_GIC_DIST_GICD_ICPENDR9_FLD_SET_MSK 0xffffffff
4872 /* The mask used to clear the ALT_GIC_DIST_GICD_ICPENDR9_FLD register field value. */
4873 #define ALT_GIC_DIST_GICD_ICPENDR9_FLD_CLR_MSK 0x00000000
4874 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR9_FLD register field. */
4875 #define ALT_GIC_DIST_GICD_ICPENDR9_FLD_RESET 0x0
4876 /* Extracts the ALT_GIC_DIST_GICD_ICPENDR9_FLD field value from a register. */
4877 #define ALT_GIC_DIST_GICD_ICPENDR9_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4878 /* Produces a ALT_GIC_DIST_GICD_ICPENDR9_FLD register field value suitable for setting the register. */
4879 #define ALT_GIC_DIST_GICD_ICPENDR9_FLD_SET(value) (((value) << 0) & 0xffffffff)
4880 
4881 #ifndef __ASSEMBLY__
4882 /*
4883  * WARNING: The C register and register group struct declarations are provided for
4884  * convenience and illustrative purposes. They should, however, be used with
4885  * caution as the C language standard provides no guarantees about the alignment or
4886  * atomicity of device memory accesses. The recommended practice for coding device
4887  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4888  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4889  * alt_write_dword() functions for 64 bit registers.
4890  *
4891  * The struct declaration for register ALT_GIC_DIST_GICD_ICPENDR9.
4892  */
4893 struct ALT_GIC_DIST_GICD_ICPENDR9_s
4894 {
4895  volatile uint32_t fld : 32; /* Empty */
4896 };
4897 
4898 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICPENDR9. */
4899 typedef struct ALT_GIC_DIST_GICD_ICPENDR9_s ALT_GIC_DIST_GICD_ICPENDR9_t;
4900 #endif /* __ASSEMBLY__ */
4901 
4902 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR9 register. */
4903 #define ALT_GIC_DIST_GICD_ICPENDR9_RESET 0x00000000
4904 /* The byte offset of the ALT_GIC_DIST_GICD_ICPENDR9 register from the beginning of the component. */
4905 #define ALT_GIC_DIST_GICD_ICPENDR9_OFST 0x2a4
4906 
4907 /*
4908  * Register : GICD_ICPENDR10
4909  *
4910  * Interrupt Clear-Pending Registers
4911  *
4912  * Register Layout
4913  *
4914  * Bits | Access | Reset | Description
4915  * :-------|:-------|:------|:------------
4916  * [31:0] | RW | 0x0 | Empty
4917  *
4918  */
4919 /*
4920  * Field : Empty - fld
4921  *
4922  * Placeholder
4923  *
4924  * Field Access Macros:
4925  *
4926  */
4927 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICPENDR10_FLD register field. */
4928 #define ALT_GIC_DIST_GICD_ICPENDR10_FLD_LSB 0
4929 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICPENDR10_FLD register field. */
4930 #define ALT_GIC_DIST_GICD_ICPENDR10_FLD_MSB 31
4931 /* The width in bits of the ALT_GIC_DIST_GICD_ICPENDR10_FLD register field. */
4932 #define ALT_GIC_DIST_GICD_ICPENDR10_FLD_WIDTH 32
4933 /* The mask used to set the ALT_GIC_DIST_GICD_ICPENDR10_FLD register field value. */
4934 #define ALT_GIC_DIST_GICD_ICPENDR10_FLD_SET_MSK 0xffffffff
4935 /* The mask used to clear the ALT_GIC_DIST_GICD_ICPENDR10_FLD register field value. */
4936 #define ALT_GIC_DIST_GICD_ICPENDR10_FLD_CLR_MSK 0x00000000
4937 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR10_FLD register field. */
4938 #define ALT_GIC_DIST_GICD_ICPENDR10_FLD_RESET 0x0
4939 /* Extracts the ALT_GIC_DIST_GICD_ICPENDR10_FLD field value from a register. */
4940 #define ALT_GIC_DIST_GICD_ICPENDR10_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4941 /* Produces a ALT_GIC_DIST_GICD_ICPENDR10_FLD register field value suitable for setting the register. */
4942 #define ALT_GIC_DIST_GICD_ICPENDR10_FLD_SET(value) (((value) << 0) & 0xffffffff)
4943 
4944 #ifndef __ASSEMBLY__
4945 /*
4946  * WARNING: The C register and register group struct declarations are provided for
4947  * convenience and illustrative purposes. They should, however, be used with
4948  * caution as the C language standard provides no guarantees about the alignment or
4949  * atomicity of device memory accesses. The recommended practice for coding device
4950  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4951  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4952  * alt_write_dword() functions for 64 bit registers.
4953  *
4954  * The struct declaration for register ALT_GIC_DIST_GICD_ICPENDR10.
4955  */
4956 struct ALT_GIC_DIST_GICD_ICPENDR10_s
4957 {
4958  volatile uint32_t fld : 32; /* Empty */
4959 };
4960 
4961 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICPENDR10. */
4962 typedef struct ALT_GIC_DIST_GICD_ICPENDR10_s ALT_GIC_DIST_GICD_ICPENDR10_t;
4963 #endif /* __ASSEMBLY__ */
4964 
4965 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR10 register. */
4966 #define ALT_GIC_DIST_GICD_ICPENDR10_RESET 0x00000000
4967 /* The byte offset of the ALT_GIC_DIST_GICD_ICPENDR10 register from the beginning of the component. */
4968 #define ALT_GIC_DIST_GICD_ICPENDR10_OFST 0x2a8
4969 
4970 /*
4971  * Register : GICD_ICPENDR11
4972  *
4973  * Interrupt Clear-Pending Registers
4974  *
4975  * Register Layout
4976  *
4977  * Bits | Access | Reset | Description
4978  * :-------|:-------|:------|:------------
4979  * [31:0] | RW | 0x0 | Empty
4980  *
4981  */
4982 /*
4983  * Field : Empty - fld
4984  *
4985  * Placeholder
4986  *
4987  * Field Access Macros:
4988  *
4989  */
4990 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICPENDR11_FLD register field. */
4991 #define ALT_GIC_DIST_GICD_ICPENDR11_FLD_LSB 0
4992 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICPENDR11_FLD register field. */
4993 #define ALT_GIC_DIST_GICD_ICPENDR11_FLD_MSB 31
4994 /* The width in bits of the ALT_GIC_DIST_GICD_ICPENDR11_FLD register field. */
4995 #define ALT_GIC_DIST_GICD_ICPENDR11_FLD_WIDTH 32
4996 /* The mask used to set the ALT_GIC_DIST_GICD_ICPENDR11_FLD register field value. */
4997 #define ALT_GIC_DIST_GICD_ICPENDR11_FLD_SET_MSK 0xffffffff
4998 /* The mask used to clear the ALT_GIC_DIST_GICD_ICPENDR11_FLD register field value. */
4999 #define ALT_GIC_DIST_GICD_ICPENDR11_FLD_CLR_MSK 0x00000000
5000 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR11_FLD register field. */
5001 #define ALT_GIC_DIST_GICD_ICPENDR11_FLD_RESET 0x0
5002 /* Extracts the ALT_GIC_DIST_GICD_ICPENDR11_FLD field value from a register. */
5003 #define ALT_GIC_DIST_GICD_ICPENDR11_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5004 /* Produces a ALT_GIC_DIST_GICD_ICPENDR11_FLD register field value suitable for setting the register. */
5005 #define ALT_GIC_DIST_GICD_ICPENDR11_FLD_SET(value) (((value) << 0) & 0xffffffff)
5006 
5007 #ifndef __ASSEMBLY__
5008 /*
5009  * WARNING: The C register and register group struct declarations are provided for
5010  * convenience and illustrative purposes. They should, however, be used with
5011  * caution as the C language standard provides no guarantees about the alignment or
5012  * atomicity of device memory accesses. The recommended practice for coding device
5013  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5014  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5015  * alt_write_dword() functions for 64 bit registers.
5016  *
5017  * The struct declaration for register ALT_GIC_DIST_GICD_ICPENDR11.
5018  */
5019 struct ALT_GIC_DIST_GICD_ICPENDR11_s
5020 {
5021  volatile uint32_t fld : 32; /* Empty */
5022 };
5023 
5024 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICPENDR11. */
5025 typedef struct ALT_GIC_DIST_GICD_ICPENDR11_s ALT_GIC_DIST_GICD_ICPENDR11_t;
5026 #endif /* __ASSEMBLY__ */
5027 
5028 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR11 register. */
5029 #define ALT_GIC_DIST_GICD_ICPENDR11_RESET 0x00000000
5030 /* The byte offset of the ALT_GIC_DIST_GICD_ICPENDR11 register from the beginning of the component. */
5031 #define ALT_GIC_DIST_GICD_ICPENDR11_OFST 0x2ac
5032 
5033 /*
5034  * Register : GICD_ICPENDR12
5035  *
5036  * Interrupt Clear-Pending Registers
5037  *
5038  * Register Layout
5039  *
5040  * Bits | Access | Reset | Description
5041  * :-------|:-------|:------|:------------
5042  * [31:0] | RW | 0x0 | Empty
5043  *
5044  */
5045 /*
5046  * Field : Empty - fld
5047  *
5048  * Placeholder
5049  *
5050  * Field Access Macros:
5051  *
5052  */
5053 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICPENDR12_FLD register field. */
5054 #define ALT_GIC_DIST_GICD_ICPENDR12_FLD_LSB 0
5055 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICPENDR12_FLD register field. */
5056 #define ALT_GIC_DIST_GICD_ICPENDR12_FLD_MSB 31
5057 /* The width in bits of the ALT_GIC_DIST_GICD_ICPENDR12_FLD register field. */
5058 #define ALT_GIC_DIST_GICD_ICPENDR12_FLD_WIDTH 32
5059 /* The mask used to set the ALT_GIC_DIST_GICD_ICPENDR12_FLD register field value. */
5060 #define ALT_GIC_DIST_GICD_ICPENDR12_FLD_SET_MSK 0xffffffff
5061 /* The mask used to clear the ALT_GIC_DIST_GICD_ICPENDR12_FLD register field value. */
5062 #define ALT_GIC_DIST_GICD_ICPENDR12_FLD_CLR_MSK 0x00000000
5063 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR12_FLD register field. */
5064 #define ALT_GIC_DIST_GICD_ICPENDR12_FLD_RESET 0x0
5065 /* Extracts the ALT_GIC_DIST_GICD_ICPENDR12_FLD field value from a register. */
5066 #define ALT_GIC_DIST_GICD_ICPENDR12_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5067 /* Produces a ALT_GIC_DIST_GICD_ICPENDR12_FLD register field value suitable for setting the register. */
5068 #define ALT_GIC_DIST_GICD_ICPENDR12_FLD_SET(value) (((value) << 0) & 0xffffffff)
5069 
5070 #ifndef __ASSEMBLY__
5071 /*
5072  * WARNING: The C register and register group struct declarations are provided for
5073  * convenience and illustrative purposes. They should, however, be used with
5074  * caution as the C language standard provides no guarantees about the alignment or
5075  * atomicity of device memory accesses. The recommended practice for coding device
5076  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5077  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5078  * alt_write_dword() functions for 64 bit registers.
5079  *
5080  * The struct declaration for register ALT_GIC_DIST_GICD_ICPENDR12.
5081  */
5082 struct ALT_GIC_DIST_GICD_ICPENDR12_s
5083 {
5084  volatile uint32_t fld : 32; /* Empty */
5085 };
5086 
5087 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICPENDR12. */
5088 typedef struct ALT_GIC_DIST_GICD_ICPENDR12_s ALT_GIC_DIST_GICD_ICPENDR12_t;
5089 #endif /* __ASSEMBLY__ */
5090 
5091 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR12 register. */
5092 #define ALT_GIC_DIST_GICD_ICPENDR12_RESET 0x00000000
5093 /* The byte offset of the ALT_GIC_DIST_GICD_ICPENDR12 register from the beginning of the component. */
5094 #define ALT_GIC_DIST_GICD_ICPENDR12_OFST 0x2b0
5095 
5096 /*
5097  * Register : GICD_ICPENDR13
5098  *
5099  * Interrupt Clear-Pending Registers
5100  *
5101  * Register Layout
5102  *
5103  * Bits | Access | Reset | Description
5104  * :-------|:-------|:------|:------------
5105  * [31:0] | RW | 0x0 | Empty
5106  *
5107  */
5108 /*
5109  * Field : Empty - fld
5110  *
5111  * Placeholder
5112  *
5113  * Field Access Macros:
5114  *
5115  */
5116 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICPENDR13_FLD register field. */
5117 #define ALT_GIC_DIST_GICD_ICPENDR13_FLD_LSB 0
5118 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICPENDR13_FLD register field. */
5119 #define ALT_GIC_DIST_GICD_ICPENDR13_FLD_MSB 31
5120 /* The width in bits of the ALT_GIC_DIST_GICD_ICPENDR13_FLD register field. */
5121 #define ALT_GIC_DIST_GICD_ICPENDR13_FLD_WIDTH 32
5122 /* The mask used to set the ALT_GIC_DIST_GICD_ICPENDR13_FLD register field value. */
5123 #define ALT_GIC_DIST_GICD_ICPENDR13_FLD_SET_MSK 0xffffffff
5124 /* The mask used to clear the ALT_GIC_DIST_GICD_ICPENDR13_FLD register field value. */
5125 #define ALT_GIC_DIST_GICD_ICPENDR13_FLD_CLR_MSK 0x00000000
5126 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR13_FLD register field. */
5127 #define ALT_GIC_DIST_GICD_ICPENDR13_FLD_RESET 0x0
5128 /* Extracts the ALT_GIC_DIST_GICD_ICPENDR13_FLD field value from a register. */
5129 #define ALT_GIC_DIST_GICD_ICPENDR13_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5130 /* Produces a ALT_GIC_DIST_GICD_ICPENDR13_FLD register field value suitable for setting the register. */
5131 #define ALT_GIC_DIST_GICD_ICPENDR13_FLD_SET(value) (((value) << 0) & 0xffffffff)
5132 
5133 #ifndef __ASSEMBLY__
5134 /*
5135  * WARNING: The C register and register group struct declarations are provided for
5136  * convenience and illustrative purposes. They should, however, be used with
5137  * caution as the C language standard provides no guarantees about the alignment or
5138  * atomicity of device memory accesses. The recommended practice for coding device
5139  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5140  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5141  * alt_write_dword() functions for 64 bit registers.
5142  *
5143  * The struct declaration for register ALT_GIC_DIST_GICD_ICPENDR13.
5144  */
5145 struct ALT_GIC_DIST_GICD_ICPENDR13_s
5146 {
5147  volatile uint32_t fld : 32; /* Empty */
5148 };
5149 
5150 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICPENDR13. */
5151 typedef struct ALT_GIC_DIST_GICD_ICPENDR13_s ALT_GIC_DIST_GICD_ICPENDR13_t;
5152 #endif /* __ASSEMBLY__ */
5153 
5154 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR13 register. */
5155 #define ALT_GIC_DIST_GICD_ICPENDR13_RESET 0x00000000
5156 /* The byte offset of the ALT_GIC_DIST_GICD_ICPENDR13 register from the beginning of the component. */
5157 #define ALT_GIC_DIST_GICD_ICPENDR13_OFST 0x2b4
5158 
5159 /*
5160  * Register : GICD_ICPENDR14
5161  *
5162  * Interrupt Clear-Pending Registers
5163  *
5164  * Register Layout
5165  *
5166  * Bits | Access | Reset | Description
5167  * :-------|:-------|:------|:------------
5168  * [31:0] | RW | 0x0 | Empty
5169  *
5170  */
5171 /*
5172  * Field : Empty - fld
5173  *
5174  * Placeholder
5175  *
5176  * Field Access Macros:
5177  *
5178  */
5179 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICPENDR14_FLD register field. */
5180 #define ALT_GIC_DIST_GICD_ICPENDR14_FLD_LSB 0
5181 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICPENDR14_FLD register field. */
5182 #define ALT_GIC_DIST_GICD_ICPENDR14_FLD_MSB 31
5183 /* The width in bits of the ALT_GIC_DIST_GICD_ICPENDR14_FLD register field. */
5184 #define ALT_GIC_DIST_GICD_ICPENDR14_FLD_WIDTH 32
5185 /* The mask used to set the ALT_GIC_DIST_GICD_ICPENDR14_FLD register field value. */
5186 #define ALT_GIC_DIST_GICD_ICPENDR14_FLD_SET_MSK 0xffffffff
5187 /* The mask used to clear the ALT_GIC_DIST_GICD_ICPENDR14_FLD register field value. */
5188 #define ALT_GIC_DIST_GICD_ICPENDR14_FLD_CLR_MSK 0x00000000
5189 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR14_FLD register field. */
5190 #define ALT_GIC_DIST_GICD_ICPENDR14_FLD_RESET 0x0
5191 /* Extracts the ALT_GIC_DIST_GICD_ICPENDR14_FLD field value from a register. */
5192 #define ALT_GIC_DIST_GICD_ICPENDR14_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5193 /* Produces a ALT_GIC_DIST_GICD_ICPENDR14_FLD register field value suitable for setting the register. */
5194 #define ALT_GIC_DIST_GICD_ICPENDR14_FLD_SET(value) (((value) << 0) & 0xffffffff)
5195 
5196 #ifndef __ASSEMBLY__
5197 /*
5198  * WARNING: The C register and register group struct declarations are provided for
5199  * convenience and illustrative purposes. They should, however, be used with
5200  * caution as the C language standard provides no guarantees about the alignment or
5201  * atomicity of device memory accesses. The recommended practice for coding device
5202  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5203  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5204  * alt_write_dword() functions for 64 bit registers.
5205  *
5206  * The struct declaration for register ALT_GIC_DIST_GICD_ICPENDR14.
5207  */
5208 struct ALT_GIC_DIST_GICD_ICPENDR14_s
5209 {
5210  volatile uint32_t fld : 32; /* Empty */
5211 };
5212 
5213 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICPENDR14. */
5214 typedef struct ALT_GIC_DIST_GICD_ICPENDR14_s ALT_GIC_DIST_GICD_ICPENDR14_t;
5215 #endif /* __ASSEMBLY__ */
5216 
5217 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR14 register. */
5218 #define ALT_GIC_DIST_GICD_ICPENDR14_RESET 0x00000000
5219 /* The byte offset of the ALT_GIC_DIST_GICD_ICPENDR14 register from the beginning of the component. */
5220 #define ALT_GIC_DIST_GICD_ICPENDR14_OFST 0x2b8
5221 
5222 /*
5223  * Register : GICD_ICPENDR15
5224  *
5225  * Interrupt Clear-Pending Registers
5226  *
5227  * Register Layout
5228  *
5229  * Bits | Access | Reset | Description
5230  * :-------|:-------|:------|:------------
5231  * [31:0] | RW | 0x0 | Empty
5232  *
5233  */
5234 /*
5235  * Field : Empty - fld
5236  *
5237  * Placeholder
5238  *
5239  * Field Access Macros:
5240  *
5241  */
5242 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICPENDR15_FLD register field. */
5243 #define ALT_GIC_DIST_GICD_ICPENDR15_FLD_LSB 0
5244 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICPENDR15_FLD register field. */
5245 #define ALT_GIC_DIST_GICD_ICPENDR15_FLD_MSB 31
5246 /* The width in bits of the ALT_GIC_DIST_GICD_ICPENDR15_FLD register field. */
5247 #define ALT_GIC_DIST_GICD_ICPENDR15_FLD_WIDTH 32
5248 /* The mask used to set the ALT_GIC_DIST_GICD_ICPENDR15_FLD register field value. */
5249 #define ALT_GIC_DIST_GICD_ICPENDR15_FLD_SET_MSK 0xffffffff
5250 /* The mask used to clear the ALT_GIC_DIST_GICD_ICPENDR15_FLD register field value. */
5251 #define ALT_GIC_DIST_GICD_ICPENDR15_FLD_CLR_MSK 0x00000000
5252 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR15_FLD register field. */
5253 #define ALT_GIC_DIST_GICD_ICPENDR15_FLD_RESET 0x0
5254 /* Extracts the ALT_GIC_DIST_GICD_ICPENDR15_FLD field value from a register. */
5255 #define ALT_GIC_DIST_GICD_ICPENDR15_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5256 /* Produces a ALT_GIC_DIST_GICD_ICPENDR15_FLD register field value suitable for setting the register. */
5257 #define ALT_GIC_DIST_GICD_ICPENDR15_FLD_SET(value) (((value) << 0) & 0xffffffff)
5258 
5259 #ifndef __ASSEMBLY__
5260 /*
5261  * WARNING: The C register and register group struct declarations are provided for
5262  * convenience and illustrative purposes. They should, however, be used with
5263  * caution as the C language standard provides no guarantees about the alignment or
5264  * atomicity of device memory accesses. The recommended practice for coding device
5265  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5266  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5267  * alt_write_dword() functions for 64 bit registers.
5268  *
5269  * The struct declaration for register ALT_GIC_DIST_GICD_ICPENDR15.
5270  */
5271 struct ALT_GIC_DIST_GICD_ICPENDR15_s
5272 {
5273  volatile uint32_t fld : 32; /* Empty */
5274 };
5275 
5276 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICPENDR15. */
5277 typedef struct ALT_GIC_DIST_GICD_ICPENDR15_s ALT_GIC_DIST_GICD_ICPENDR15_t;
5278 #endif /* __ASSEMBLY__ */
5279 
5280 /* The reset value of the ALT_GIC_DIST_GICD_ICPENDR15 register. */
5281 #define ALT_GIC_DIST_GICD_ICPENDR15_RESET 0x00000000
5282 /* The byte offset of the ALT_GIC_DIST_GICD_ICPENDR15 register from the beginning of the component. */
5283 #define ALT_GIC_DIST_GICD_ICPENDR15_OFST 0x2bc
5284 
5285 /*
5286  * Register : GICD_ISACTIVER0
5287  *
5288  * Interrupt Set-Active Registers
5289  *
5290  * Register Layout
5291  *
5292  * Bits | Access | Reset | Description
5293  * :-------|:-------|:------|:------------
5294  * [31:0] | RW | 0x0 | Empty
5295  *
5296  */
5297 /*
5298  * Field : Empty - fld
5299  *
5300  * Placeholder
5301  *
5302  * Field Access Macros:
5303  *
5304  */
5305 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISACTIVER0_FLD register field. */
5306 #define ALT_GIC_DIST_GICD_ISACTIVER0_FLD_LSB 0
5307 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISACTIVER0_FLD register field. */
5308 #define ALT_GIC_DIST_GICD_ISACTIVER0_FLD_MSB 31
5309 /* The width in bits of the ALT_GIC_DIST_GICD_ISACTIVER0_FLD register field. */
5310 #define ALT_GIC_DIST_GICD_ISACTIVER0_FLD_WIDTH 32
5311 /* The mask used to set the ALT_GIC_DIST_GICD_ISACTIVER0_FLD register field value. */
5312 #define ALT_GIC_DIST_GICD_ISACTIVER0_FLD_SET_MSK 0xffffffff
5313 /* The mask used to clear the ALT_GIC_DIST_GICD_ISACTIVER0_FLD register field value. */
5314 #define ALT_GIC_DIST_GICD_ISACTIVER0_FLD_CLR_MSK 0x00000000
5315 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER0_FLD register field. */
5316 #define ALT_GIC_DIST_GICD_ISACTIVER0_FLD_RESET 0x0
5317 /* Extracts the ALT_GIC_DIST_GICD_ISACTIVER0_FLD field value from a register. */
5318 #define ALT_GIC_DIST_GICD_ISACTIVER0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5319 /* Produces a ALT_GIC_DIST_GICD_ISACTIVER0_FLD register field value suitable for setting the register. */
5320 #define ALT_GIC_DIST_GICD_ISACTIVER0_FLD_SET(value) (((value) << 0) & 0xffffffff)
5321 
5322 #ifndef __ASSEMBLY__
5323 /*
5324  * WARNING: The C register and register group struct declarations are provided for
5325  * convenience and illustrative purposes. They should, however, be used with
5326  * caution as the C language standard provides no guarantees about the alignment or
5327  * atomicity of device memory accesses. The recommended practice for coding device
5328  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5329  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5330  * alt_write_dword() functions for 64 bit registers.
5331  *
5332  * The struct declaration for register ALT_GIC_DIST_GICD_ISACTIVER0.
5333  */
5334 struct ALT_GIC_DIST_GICD_ISACTIVER0_s
5335 {
5336  volatile uint32_t fld : 32; /* Empty */
5337 };
5338 
5339 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISACTIVER0. */
5340 typedef struct ALT_GIC_DIST_GICD_ISACTIVER0_s ALT_GIC_DIST_GICD_ISACTIVER0_t;
5341 #endif /* __ASSEMBLY__ */
5342 
5343 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER0 register. */
5344 #define ALT_GIC_DIST_GICD_ISACTIVER0_RESET 0x00000000
5345 /* The byte offset of the ALT_GIC_DIST_GICD_ISACTIVER0 register from the beginning of the component. */
5346 #define ALT_GIC_DIST_GICD_ISACTIVER0_OFST 0x300
5347 
5348 /*
5349  * Register : GICD_ISACTIVER1
5350  *
5351  * Interrupt Set-Active Registers
5352  *
5353  * Register Layout
5354  *
5355  * Bits | Access | Reset | Description
5356  * :-------|:-------|:------|:------------
5357  * [31:0] | RW | 0x0 | Empty
5358  *
5359  */
5360 /*
5361  * Field : Empty - fld
5362  *
5363  * Placeholder
5364  *
5365  * Field Access Macros:
5366  *
5367  */
5368 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISACTIVER1_FLD register field. */
5369 #define ALT_GIC_DIST_GICD_ISACTIVER1_FLD_LSB 0
5370 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISACTIVER1_FLD register field. */
5371 #define ALT_GIC_DIST_GICD_ISACTIVER1_FLD_MSB 31
5372 /* The width in bits of the ALT_GIC_DIST_GICD_ISACTIVER1_FLD register field. */
5373 #define ALT_GIC_DIST_GICD_ISACTIVER1_FLD_WIDTH 32
5374 /* The mask used to set the ALT_GIC_DIST_GICD_ISACTIVER1_FLD register field value. */
5375 #define ALT_GIC_DIST_GICD_ISACTIVER1_FLD_SET_MSK 0xffffffff
5376 /* The mask used to clear the ALT_GIC_DIST_GICD_ISACTIVER1_FLD register field value. */
5377 #define ALT_GIC_DIST_GICD_ISACTIVER1_FLD_CLR_MSK 0x00000000
5378 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER1_FLD register field. */
5379 #define ALT_GIC_DIST_GICD_ISACTIVER1_FLD_RESET 0x0
5380 /* Extracts the ALT_GIC_DIST_GICD_ISACTIVER1_FLD field value from a register. */
5381 #define ALT_GIC_DIST_GICD_ISACTIVER1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5382 /* Produces a ALT_GIC_DIST_GICD_ISACTIVER1_FLD register field value suitable for setting the register. */
5383 #define ALT_GIC_DIST_GICD_ISACTIVER1_FLD_SET(value) (((value) << 0) & 0xffffffff)
5384 
5385 #ifndef __ASSEMBLY__
5386 /*
5387  * WARNING: The C register and register group struct declarations are provided for
5388  * convenience and illustrative purposes. They should, however, be used with
5389  * caution as the C language standard provides no guarantees about the alignment or
5390  * atomicity of device memory accesses. The recommended practice for coding device
5391  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5392  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5393  * alt_write_dword() functions for 64 bit registers.
5394  *
5395  * The struct declaration for register ALT_GIC_DIST_GICD_ISACTIVER1.
5396  */
5397 struct ALT_GIC_DIST_GICD_ISACTIVER1_s
5398 {
5399  volatile uint32_t fld : 32; /* Empty */
5400 };
5401 
5402 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISACTIVER1. */
5403 typedef struct ALT_GIC_DIST_GICD_ISACTIVER1_s ALT_GIC_DIST_GICD_ISACTIVER1_t;
5404 #endif /* __ASSEMBLY__ */
5405 
5406 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER1 register. */
5407 #define ALT_GIC_DIST_GICD_ISACTIVER1_RESET 0x00000000
5408 /* The byte offset of the ALT_GIC_DIST_GICD_ISACTIVER1 register from the beginning of the component. */
5409 #define ALT_GIC_DIST_GICD_ISACTIVER1_OFST 0x304
5410 
5411 /*
5412  * Register : GICD_ISACTIVER2
5413  *
5414  * Interrupt Set-Active Registers
5415  *
5416  * Register Layout
5417  *
5418  * Bits | Access | Reset | Description
5419  * :-------|:-------|:------|:------------
5420  * [31:0] | RW | 0x0 | Empty
5421  *
5422  */
5423 /*
5424  * Field : Empty - fld
5425  *
5426  * Placeholder
5427  *
5428  * Field Access Macros:
5429  *
5430  */
5431 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISACTIVER2_FLD register field. */
5432 #define ALT_GIC_DIST_GICD_ISACTIVER2_FLD_LSB 0
5433 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISACTIVER2_FLD register field. */
5434 #define ALT_GIC_DIST_GICD_ISACTIVER2_FLD_MSB 31
5435 /* The width in bits of the ALT_GIC_DIST_GICD_ISACTIVER2_FLD register field. */
5436 #define ALT_GIC_DIST_GICD_ISACTIVER2_FLD_WIDTH 32
5437 /* The mask used to set the ALT_GIC_DIST_GICD_ISACTIVER2_FLD register field value. */
5438 #define ALT_GIC_DIST_GICD_ISACTIVER2_FLD_SET_MSK 0xffffffff
5439 /* The mask used to clear the ALT_GIC_DIST_GICD_ISACTIVER2_FLD register field value. */
5440 #define ALT_GIC_DIST_GICD_ISACTIVER2_FLD_CLR_MSK 0x00000000
5441 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER2_FLD register field. */
5442 #define ALT_GIC_DIST_GICD_ISACTIVER2_FLD_RESET 0x0
5443 /* Extracts the ALT_GIC_DIST_GICD_ISACTIVER2_FLD field value from a register. */
5444 #define ALT_GIC_DIST_GICD_ISACTIVER2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5445 /* Produces a ALT_GIC_DIST_GICD_ISACTIVER2_FLD register field value suitable for setting the register. */
5446 #define ALT_GIC_DIST_GICD_ISACTIVER2_FLD_SET(value) (((value) << 0) & 0xffffffff)
5447 
5448 #ifndef __ASSEMBLY__
5449 /*
5450  * WARNING: The C register and register group struct declarations are provided for
5451  * convenience and illustrative purposes. They should, however, be used with
5452  * caution as the C language standard provides no guarantees about the alignment or
5453  * atomicity of device memory accesses. The recommended practice for coding device
5454  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5455  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5456  * alt_write_dword() functions for 64 bit registers.
5457  *
5458  * The struct declaration for register ALT_GIC_DIST_GICD_ISACTIVER2.
5459  */
5460 struct ALT_GIC_DIST_GICD_ISACTIVER2_s
5461 {
5462  volatile uint32_t fld : 32; /* Empty */
5463 };
5464 
5465 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISACTIVER2. */
5466 typedef struct ALT_GIC_DIST_GICD_ISACTIVER2_s ALT_GIC_DIST_GICD_ISACTIVER2_t;
5467 #endif /* __ASSEMBLY__ */
5468 
5469 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER2 register. */
5470 #define ALT_GIC_DIST_GICD_ISACTIVER2_RESET 0x00000000
5471 /* The byte offset of the ALT_GIC_DIST_GICD_ISACTIVER2 register from the beginning of the component. */
5472 #define ALT_GIC_DIST_GICD_ISACTIVER2_OFST 0x308
5473 
5474 /*
5475  * Register : GICD_ISACTIVER3
5476  *
5477  * Interrupt Set-Active Registers
5478  *
5479  * Register Layout
5480  *
5481  * Bits | Access | Reset | Description
5482  * :-------|:-------|:------|:------------
5483  * [31:0] | RW | 0x0 | Empty
5484  *
5485  */
5486 /*
5487  * Field : Empty - fld
5488  *
5489  * Placeholder
5490  *
5491  * Field Access Macros:
5492  *
5493  */
5494 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISACTIVER3_FLD register field. */
5495 #define ALT_GIC_DIST_GICD_ISACTIVER3_FLD_LSB 0
5496 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISACTIVER3_FLD register field. */
5497 #define ALT_GIC_DIST_GICD_ISACTIVER3_FLD_MSB 31
5498 /* The width in bits of the ALT_GIC_DIST_GICD_ISACTIVER3_FLD register field. */
5499 #define ALT_GIC_DIST_GICD_ISACTIVER3_FLD_WIDTH 32
5500 /* The mask used to set the ALT_GIC_DIST_GICD_ISACTIVER3_FLD register field value. */
5501 #define ALT_GIC_DIST_GICD_ISACTIVER3_FLD_SET_MSK 0xffffffff
5502 /* The mask used to clear the ALT_GIC_DIST_GICD_ISACTIVER3_FLD register field value. */
5503 #define ALT_GIC_DIST_GICD_ISACTIVER3_FLD_CLR_MSK 0x00000000
5504 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER3_FLD register field. */
5505 #define ALT_GIC_DIST_GICD_ISACTIVER3_FLD_RESET 0x0
5506 /* Extracts the ALT_GIC_DIST_GICD_ISACTIVER3_FLD field value from a register. */
5507 #define ALT_GIC_DIST_GICD_ISACTIVER3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5508 /* Produces a ALT_GIC_DIST_GICD_ISACTIVER3_FLD register field value suitable for setting the register. */
5509 #define ALT_GIC_DIST_GICD_ISACTIVER3_FLD_SET(value) (((value) << 0) & 0xffffffff)
5510 
5511 #ifndef __ASSEMBLY__
5512 /*
5513  * WARNING: The C register and register group struct declarations are provided for
5514  * convenience and illustrative purposes. They should, however, be used with
5515  * caution as the C language standard provides no guarantees about the alignment or
5516  * atomicity of device memory accesses. The recommended practice for coding device
5517  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5518  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5519  * alt_write_dword() functions for 64 bit registers.
5520  *
5521  * The struct declaration for register ALT_GIC_DIST_GICD_ISACTIVER3.
5522  */
5523 struct ALT_GIC_DIST_GICD_ISACTIVER3_s
5524 {
5525  volatile uint32_t fld : 32; /* Empty */
5526 };
5527 
5528 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISACTIVER3. */
5529 typedef struct ALT_GIC_DIST_GICD_ISACTIVER3_s ALT_GIC_DIST_GICD_ISACTIVER3_t;
5530 #endif /* __ASSEMBLY__ */
5531 
5532 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER3 register. */
5533 #define ALT_GIC_DIST_GICD_ISACTIVER3_RESET 0x00000000
5534 /* The byte offset of the ALT_GIC_DIST_GICD_ISACTIVER3 register from the beginning of the component. */
5535 #define ALT_GIC_DIST_GICD_ISACTIVER3_OFST 0x30c
5536 
5537 /*
5538  * Register : GICD_ISACTIVER4
5539  *
5540  * Interrupt Set-Active Registers
5541  *
5542  * Register Layout
5543  *
5544  * Bits | Access | Reset | Description
5545  * :-------|:-------|:------|:------------
5546  * [31:0] | RW | 0x0 | Empty
5547  *
5548  */
5549 /*
5550  * Field : Empty - fld
5551  *
5552  * Placeholder
5553  *
5554  * Field Access Macros:
5555  *
5556  */
5557 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISACTIVER4_FLD register field. */
5558 #define ALT_GIC_DIST_GICD_ISACTIVER4_FLD_LSB 0
5559 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISACTIVER4_FLD register field. */
5560 #define ALT_GIC_DIST_GICD_ISACTIVER4_FLD_MSB 31
5561 /* The width in bits of the ALT_GIC_DIST_GICD_ISACTIVER4_FLD register field. */
5562 #define ALT_GIC_DIST_GICD_ISACTIVER4_FLD_WIDTH 32
5563 /* The mask used to set the ALT_GIC_DIST_GICD_ISACTIVER4_FLD register field value. */
5564 #define ALT_GIC_DIST_GICD_ISACTIVER4_FLD_SET_MSK 0xffffffff
5565 /* The mask used to clear the ALT_GIC_DIST_GICD_ISACTIVER4_FLD register field value. */
5566 #define ALT_GIC_DIST_GICD_ISACTIVER4_FLD_CLR_MSK 0x00000000
5567 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER4_FLD register field. */
5568 #define ALT_GIC_DIST_GICD_ISACTIVER4_FLD_RESET 0x0
5569 /* Extracts the ALT_GIC_DIST_GICD_ISACTIVER4_FLD field value from a register. */
5570 #define ALT_GIC_DIST_GICD_ISACTIVER4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5571 /* Produces a ALT_GIC_DIST_GICD_ISACTIVER4_FLD register field value suitable for setting the register. */
5572 #define ALT_GIC_DIST_GICD_ISACTIVER4_FLD_SET(value) (((value) << 0) & 0xffffffff)
5573 
5574 #ifndef __ASSEMBLY__
5575 /*
5576  * WARNING: The C register and register group struct declarations are provided for
5577  * convenience and illustrative purposes. They should, however, be used with
5578  * caution as the C language standard provides no guarantees about the alignment or
5579  * atomicity of device memory accesses. The recommended practice for coding device
5580  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5581  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5582  * alt_write_dword() functions for 64 bit registers.
5583  *
5584  * The struct declaration for register ALT_GIC_DIST_GICD_ISACTIVER4.
5585  */
5586 struct ALT_GIC_DIST_GICD_ISACTIVER4_s
5587 {
5588  volatile uint32_t fld : 32; /* Empty */
5589 };
5590 
5591 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISACTIVER4. */
5592 typedef struct ALT_GIC_DIST_GICD_ISACTIVER4_s ALT_GIC_DIST_GICD_ISACTIVER4_t;
5593 #endif /* __ASSEMBLY__ */
5594 
5595 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER4 register. */
5596 #define ALT_GIC_DIST_GICD_ISACTIVER4_RESET 0x00000000
5597 /* The byte offset of the ALT_GIC_DIST_GICD_ISACTIVER4 register from the beginning of the component. */
5598 #define ALT_GIC_DIST_GICD_ISACTIVER4_OFST 0x310
5599 
5600 /*
5601  * Register : GICD_ISACTIVER5
5602  *
5603  * Interrupt Set-Active Registers
5604  *
5605  * Register Layout
5606  *
5607  * Bits | Access | Reset | Description
5608  * :-------|:-------|:------|:------------
5609  * [31:0] | RW | 0x0 | Empty
5610  *
5611  */
5612 /*
5613  * Field : Empty - fld
5614  *
5615  * Placeholder
5616  *
5617  * Field Access Macros:
5618  *
5619  */
5620 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISACTIVER5_FLD register field. */
5621 #define ALT_GIC_DIST_GICD_ISACTIVER5_FLD_LSB 0
5622 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISACTIVER5_FLD register field. */
5623 #define ALT_GIC_DIST_GICD_ISACTIVER5_FLD_MSB 31
5624 /* The width in bits of the ALT_GIC_DIST_GICD_ISACTIVER5_FLD register field. */
5625 #define ALT_GIC_DIST_GICD_ISACTIVER5_FLD_WIDTH 32
5626 /* The mask used to set the ALT_GIC_DIST_GICD_ISACTIVER5_FLD register field value. */
5627 #define ALT_GIC_DIST_GICD_ISACTIVER5_FLD_SET_MSK 0xffffffff
5628 /* The mask used to clear the ALT_GIC_DIST_GICD_ISACTIVER5_FLD register field value. */
5629 #define ALT_GIC_DIST_GICD_ISACTIVER5_FLD_CLR_MSK 0x00000000
5630 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER5_FLD register field. */
5631 #define ALT_GIC_DIST_GICD_ISACTIVER5_FLD_RESET 0x0
5632 /* Extracts the ALT_GIC_DIST_GICD_ISACTIVER5_FLD field value from a register. */
5633 #define ALT_GIC_DIST_GICD_ISACTIVER5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5634 /* Produces a ALT_GIC_DIST_GICD_ISACTIVER5_FLD register field value suitable for setting the register. */
5635 #define ALT_GIC_DIST_GICD_ISACTIVER5_FLD_SET(value) (((value) << 0) & 0xffffffff)
5636 
5637 #ifndef __ASSEMBLY__
5638 /*
5639  * WARNING: The C register and register group struct declarations are provided for
5640  * convenience and illustrative purposes. They should, however, be used with
5641  * caution as the C language standard provides no guarantees about the alignment or
5642  * atomicity of device memory accesses. The recommended practice for coding device
5643  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5644  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5645  * alt_write_dword() functions for 64 bit registers.
5646  *
5647  * The struct declaration for register ALT_GIC_DIST_GICD_ISACTIVER5.
5648  */
5649 struct ALT_GIC_DIST_GICD_ISACTIVER5_s
5650 {
5651  volatile uint32_t fld : 32; /* Empty */
5652 };
5653 
5654 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISACTIVER5. */
5655 typedef struct ALT_GIC_DIST_GICD_ISACTIVER5_s ALT_GIC_DIST_GICD_ISACTIVER5_t;
5656 #endif /* __ASSEMBLY__ */
5657 
5658 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER5 register. */
5659 #define ALT_GIC_DIST_GICD_ISACTIVER5_RESET 0x00000000
5660 /* The byte offset of the ALT_GIC_DIST_GICD_ISACTIVER5 register from the beginning of the component. */
5661 #define ALT_GIC_DIST_GICD_ISACTIVER5_OFST 0x314
5662 
5663 /*
5664  * Register : GICD_ISACTIVER6
5665  *
5666  * Interrupt Set-Active Registers
5667  *
5668  * Register Layout
5669  *
5670  * Bits | Access | Reset | Description
5671  * :-------|:-------|:------|:------------
5672  * [31:0] | RW | 0x0 | Empty
5673  *
5674  */
5675 /*
5676  * Field : Empty - fld
5677  *
5678  * Placeholder
5679  *
5680  * Field Access Macros:
5681  *
5682  */
5683 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISACTIVER6_FLD register field. */
5684 #define ALT_GIC_DIST_GICD_ISACTIVER6_FLD_LSB 0
5685 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISACTIVER6_FLD register field. */
5686 #define ALT_GIC_DIST_GICD_ISACTIVER6_FLD_MSB 31
5687 /* The width in bits of the ALT_GIC_DIST_GICD_ISACTIVER6_FLD register field. */
5688 #define ALT_GIC_DIST_GICD_ISACTIVER6_FLD_WIDTH 32
5689 /* The mask used to set the ALT_GIC_DIST_GICD_ISACTIVER6_FLD register field value. */
5690 #define ALT_GIC_DIST_GICD_ISACTIVER6_FLD_SET_MSK 0xffffffff
5691 /* The mask used to clear the ALT_GIC_DIST_GICD_ISACTIVER6_FLD register field value. */
5692 #define ALT_GIC_DIST_GICD_ISACTIVER6_FLD_CLR_MSK 0x00000000
5693 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER6_FLD register field. */
5694 #define ALT_GIC_DIST_GICD_ISACTIVER6_FLD_RESET 0x0
5695 /* Extracts the ALT_GIC_DIST_GICD_ISACTIVER6_FLD field value from a register. */
5696 #define ALT_GIC_DIST_GICD_ISACTIVER6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5697 /* Produces a ALT_GIC_DIST_GICD_ISACTIVER6_FLD register field value suitable for setting the register. */
5698 #define ALT_GIC_DIST_GICD_ISACTIVER6_FLD_SET(value) (((value) << 0) & 0xffffffff)
5699 
5700 #ifndef __ASSEMBLY__
5701 /*
5702  * WARNING: The C register and register group struct declarations are provided for
5703  * convenience and illustrative purposes. They should, however, be used with
5704  * caution as the C language standard provides no guarantees about the alignment or
5705  * atomicity of device memory accesses. The recommended practice for coding device
5706  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5707  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5708  * alt_write_dword() functions for 64 bit registers.
5709  *
5710  * The struct declaration for register ALT_GIC_DIST_GICD_ISACTIVER6.
5711  */
5712 struct ALT_GIC_DIST_GICD_ISACTIVER6_s
5713 {
5714  volatile uint32_t fld : 32; /* Empty */
5715 };
5716 
5717 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISACTIVER6. */
5718 typedef struct ALT_GIC_DIST_GICD_ISACTIVER6_s ALT_GIC_DIST_GICD_ISACTIVER6_t;
5719 #endif /* __ASSEMBLY__ */
5720 
5721 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER6 register. */
5722 #define ALT_GIC_DIST_GICD_ISACTIVER6_RESET 0x00000000
5723 /* The byte offset of the ALT_GIC_DIST_GICD_ISACTIVER6 register from the beginning of the component. */
5724 #define ALT_GIC_DIST_GICD_ISACTIVER6_OFST 0x318
5725 
5726 /*
5727  * Register : GICD_ISACTIVER7
5728  *
5729  * Interrupt Set-Active Registers
5730  *
5731  * Register Layout
5732  *
5733  * Bits | Access | Reset | Description
5734  * :-------|:-------|:------|:------------
5735  * [31:0] | RW | 0x0 | Empty
5736  *
5737  */
5738 /*
5739  * Field : Empty - fld
5740  *
5741  * Placeholder
5742  *
5743  * Field Access Macros:
5744  *
5745  */
5746 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISACTIVER7_FLD register field. */
5747 #define ALT_GIC_DIST_GICD_ISACTIVER7_FLD_LSB 0
5748 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISACTIVER7_FLD register field. */
5749 #define ALT_GIC_DIST_GICD_ISACTIVER7_FLD_MSB 31
5750 /* The width in bits of the ALT_GIC_DIST_GICD_ISACTIVER7_FLD register field. */
5751 #define ALT_GIC_DIST_GICD_ISACTIVER7_FLD_WIDTH 32
5752 /* The mask used to set the ALT_GIC_DIST_GICD_ISACTIVER7_FLD register field value. */
5753 #define ALT_GIC_DIST_GICD_ISACTIVER7_FLD_SET_MSK 0xffffffff
5754 /* The mask used to clear the ALT_GIC_DIST_GICD_ISACTIVER7_FLD register field value. */
5755 #define ALT_GIC_DIST_GICD_ISACTIVER7_FLD_CLR_MSK 0x00000000
5756 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER7_FLD register field. */
5757 #define ALT_GIC_DIST_GICD_ISACTIVER7_FLD_RESET 0x0
5758 /* Extracts the ALT_GIC_DIST_GICD_ISACTIVER7_FLD field value from a register. */
5759 #define ALT_GIC_DIST_GICD_ISACTIVER7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5760 /* Produces a ALT_GIC_DIST_GICD_ISACTIVER7_FLD register field value suitable for setting the register. */
5761 #define ALT_GIC_DIST_GICD_ISACTIVER7_FLD_SET(value) (((value) << 0) & 0xffffffff)
5762 
5763 #ifndef __ASSEMBLY__
5764 /*
5765  * WARNING: The C register and register group struct declarations are provided for
5766  * convenience and illustrative purposes. They should, however, be used with
5767  * caution as the C language standard provides no guarantees about the alignment or
5768  * atomicity of device memory accesses. The recommended practice for coding device
5769  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5770  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5771  * alt_write_dword() functions for 64 bit registers.
5772  *
5773  * The struct declaration for register ALT_GIC_DIST_GICD_ISACTIVER7.
5774  */
5775 struct ALT_GIC_DIST_GICD_ISACTIVER7_s
5776 {
5777  volatile uint32_t fld : 32; /* Empty */
5778 };
5779 
5780 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISACTIVER7. */
5781 typedef struct ALT_GIC_DIST_GICD_ISACTIVER7_s ALT_GIC_DIST_GICD_ISACTIVER7_t;
5782 #endif /* __ASSEMBLY__ */
5783 
5784 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER7 register. */
5785 #define ALT_GIC_DIST_GICD_ISACTIVER7_RESET 0x00000000
5786 /* The byte offset of the ALT_GIC_DIST_GICD_ISACTIVER7 register from the beginning of the component. */
5787 #define ALT_GIC_DIST_GICD_ISACTIVER7_OFST 0x31c
5788 
5789 /*
5790  * Register : GICD_ISACTIVER8
5791  *
5792  * Interrupt Set-Active Registers
5793  *
5794  * Register Layout
5795  *
5796  * Bits | Access | Reset | Description
5797  * :-------|:-------|:------|:------------
5798  * [31:0] | RW | 0x0 | Empty
5799  *
5800  */
5801 /*
5802  * Field : Empty - fld
5803  *
5804  * Placeholder
5805  *
5806  * Field Access Macros:
5807  *
5808  */
5809 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISACTIVER8_FLD register field. */
5810 #define ALT_GIC_DIST_GICD_ISACTIVER8_FLD_LSB 0
5811 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISACTIVER8_FLD register field. */
5812 #define ALT_GIC_DIST_GICD_ISACTIVER8_FLD_MSB 31
5813 /* The width in bits of the ALT_GIC_DIST_GICD_ISACTIVER8_FLD register field. */
5814 #define ALT_GIC_DIST_GICD_ISACTIVER8_FLD_WIDTH 32
5815 /* The mask used to set the ALT_GIC_DIST_GICD_ISACTIVER8_FLD register field value. */
5816 #define ALT_GIC_DIST_GICD_ISACTIVER8_FLD_SET_MSK 0xffffffff
5817 /* The mask used to clear the ALT_GIC_DIST_GICD_ISACTIVER8_FLD register field value. */
5818 #define ALT_GIC_DIST_GICD_ISACTIVER8_FLD_CLR_MSK 0x00000000
5819 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER8_FLD register field. */
5820 #define ALT_GIC_DIST_GICD_ISACTIVER8_FLD_RESET 0x0
5821 /* Extracts the ALT_GIC_DIST_GICD_ISACTIVER8_FLD field value from a register. */
5822 #define ALT_GIC_DIST_GICD_ISACTIVER8_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5823 /* Produces a ALT_GIC_DIST_GICD_ISACTIVER8_FLD register field value suitable for setting the register. */
5824 #define ALT_GIC_DIST_GICD_ISACTIVER8_FLD_SET(value) (((value) << 0) & 0xffffffff)
5825 
5826 #ifndef __ASSEMBLY__
5827 /*
5828  * WARNING: The C register and register group struct declarations are provided for
5829  * convenience and illustrative purposes. They should, however, be used with
5830  * caution as the C language standard provides no guarantees about the alignment or
5831  * atomicity of device memory accesses. The recommended practice for coding device
5832  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5833  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5834  * alt_write_dword() functions for 64 bit registers.
5835  *
5836  * The struct declaration for register ALT_GIC_DIST_GICD_ISACTIVER8.
5837  */
5838 struct ALT_GIC_DIST_GICD_ISACTIVER8_s
5839 {
5840  volatile uint32_t fld : 32; /* Empty */
5841 };
5842 
5843 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISACTIVER8. */
5844 typedef struct ALT_GIC_DIST_GICD_ISACTIVER8_s ALT_GIC_DIST_GICD_ISACTIVER8_t;
5845 #endif /* __ASSEMBLY__ */
5846 
5847 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER8 register. */
5848 #define ALT_GIC_DIST_GICD_ISACTIVER8_RESET 0x00000000
5849 /* The byte offset of the ALT_GIC_DIST_GICD_ISACTIVER8 register from the beginning of the component. */
5850 #define ALT_GIC_DIST_GICD_ISACTIVER8_OFST 0x320
5851 
5852 /*
5853  * Register : GICD_ISACTIVER9
5854  *
5855  * Interrupt Set-Active Registers
5856  *
5857  * Register Layout
5858  *
5859  * Bits | Access | Reset | Description
5860  * :-------|:-------|:------|:------------
5861  * [31:0] | RW | 0x0 | Empty
5862  *
5863  */
5864 /*
5865  * Field : Empty - fld
5866  *
5867  * Placeholder
5868  *
5869  * Field Access Macros:
5870  *
5871  */
5872 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISACTIVER9_FLD register field. */
5873 #define ALT_GIC_DIST_GICD_ISACTIVER9_FLD_LSB 0
5874 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISACTIVER9_FLD register field. */
5875 #define ALT_GIC_DIST_GICD_ISACTIVER9_FLD_MSB 31
5876 /* The width in bits of the ALT_GIC_DIST_GICD_ISACTIVER9_FLD register field. */
5877 #define ALT_GIC_DIST_GICD_ISACTIVER9_FLD_WIDTH 32
5878 /* The mask used to set the ALT_GIC_DIST_GICD_ISACTIVER9_FLD register field value. */
5879 #define ALT_GIC_DIST_GICD_ISACTIVER9_FLD_SET_MSK 0xffffffff
5880 /* The mask used to clear the ALT_GIC_DIST_GICD_ISACTIVER9_FLD register field value. */
5881 #define ALT_GIC_DIST_GICD_ISACTIVER9_FLD_CLR_MSK 0x00000000
5882 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER9_FLD register field. */
5883 #define ALT_GIC_DIST_GICD_ISACTIVER9_FLD_RESET 0x0
5884 /* Extracts the ALT_GIC_DIST_GICD_ISACTIVER9_FLD field value from a register. */
5885 #define ALT_GIC_DIST_GICD_ISACTIVER9_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5886 /* Produces a ALT_GIC_DIST_GICD_ISACTIVER9_FLD register field value suitable for setting the register. */
5887 #define ALT_GIC_DIST_GICD_ISACTIVER9_FLD_SET(value) (((value) << 0) & 0xffffffff)
5888 
5889 #ifndef __ASSEMBLY__
5890 /*
5891  * WARNING: The C register and register group struct declarations are provided for
5892  * convenience and illustrative purposes. They should, however, be used with
5893  * caution as the C language standard provides no guarantees about the alignment or
5894  * atomicity of device memory accesses. The recommended practice for coding device
5895  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5896  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5897  * alt_write_dword() functions for 64 bit registers.
5898  *
5899  * The struct declaration for register ALT_GIC_DIST_GICD_ISACTIVER9.
5900  */
5901 struct ALT_GIC_DIST_GICD_ISACTIVER9_s
5902 {
5903  volatile uint32_t fld : 32; /* Empty */
5904 };
5905 
5906 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISACTIVER9. */
5907 typedef struct ALT_GIC_DIST_GICD_ISACTIVER9_s ALT_GIC_DIST_GICD_ISACTIVER9_t;
5908 #endif /* __ASSEMBLY__ */
5909 
5910 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER9 register. */
5911 #define ALT_GIC_DIST_GICD_ISACTIVER9_RESET 0x00000000
5912 /* The byte offset of the ALT_GIC_DIST_GICD_ISACTIVER9 register from the beginning of the component. */
5913 #define ALT_GIC_DIST_GICD_ISACTIVER9_OFST 0x324
5914 
5915 /*
5916  * Register : GICD_ISACTIVER10
5917  *
5918  * Interrupt Set-Active Registers
5919  *
5920  * Register Layout
5921  *
5922  * Bits | Access | Reset | Description
5923  * :-------|:-------|:------|:------------
5924  * [31:0] | RW | 0x0 | Empty
5925  *
5926  */
5927 /*
5928  * Field : Empty - fld
5929  *
5930  * Placeholder
5931  *
5932  * Field Access Macros:
5933  *
5934  */
5935 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISACTIVER10_FLD register field. */
5936 #define ALT_GIC_DIST_GICD_ISACTIVER10_FLD_LSB 0
5937 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISACTIVER10_FLD register field. */
5938 #define ALT_GIC_DIST_GICD_ISACTIVER10_FLD_MSB 31
5939 /* The width in bits of the ALT_GIC_DIST_GICD_ISACTIVER10_FLD register field. */
5940 #define ALT_GIC_DIST_GICD_ISACTIVER10_FLD_WIDTH 32
5941 /* The mask used to set the ALT_GIC_DIST_GICD_ISACTIVER10_FLD register field value. */
5942 #define ALT_GIC_DIST_GICD_ISACTIVER10_FLD_SET_MSK 0xffffffff
5943 /* The mask used to clear the ALT_GIC_DIST_GICD_ISACTIVER10_FLD register field value. */
5944 #define ALT_GIC_DIST_GICD_ISACTIVER10_FLD_CLR_MSK 0x00000000
5945 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER10_FLD register field. */
5946 #define ALT_GIC_DIST_GICD_ISACTIVER10_FLD_RESET 0x0
5947 /* Extracts the ALT_GIC_DIST_GICD_ISACTIVER10_FLD field value from a register. */
5948 #define ALT_GIC_DIST_GICD_ISACTIVER10_FLD_GET(value) (((value) & 0xffffffff) >> 0)
5949 /* Produces a ALT_GIC_DIST_GICD_ISACTIVER10_FLD register field value suitable for setting the register. */
5950 #define ALT_GIC_DIST_GICD_ISACTIVER10_FLD_SET(value) (((value) << 0) & 0xffffffff)
5951 
5952 #ifndef __ASSEMBLY__
5953 /*
5954  * WARNING: The C register and register group struct declarations are provided for
5955  * convenience and illustrative purposes. They should, however, be used with
5956  * caution as the C language standard provides no guarantees about the alignment or
5957  * atomicity of device memory accesses. The recommended practice for coding device
5958  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5959  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5960  * alt_write_dword() functions for 64 bit registers.
5961  *
5962  * The struct declaration for register ALT_GIC_DIST_GICD_ISACTIVER10.
5963  */
5964 struct ALT_GIC_DIST_GICD_ISACTIVER10_s
5965 {
5966  volatile uint32_t fld : 32; /* Empty */
5967 };
5968 
5969 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISACTIVER10. */
5970 typedef struct ALT_GIC_DIST_GICD_ISACTIVER10_s ALT_GIC_DIST_GICD_ISACTIVER10_t;
5971 #endif /* __ASSEMBLY__ */
5972 
5973 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER10 register. */
5974 #define ALT_GIC_DIST_GICD_ISACTIVER10_RESET 0x00000000
5975 /* The byte offset of the ALT_GIC_DIST_GICD_ISACTIVER10 register from the beginning of the component. */
5976 #define ALT_GIC_DIST_GICD_ISACTIVER10_OFST 0x328
5977 
5978 /*
5979  * Register : GICD_ISACTIVER11
5980  *
5981  * Interrupt Set-Active Registers
5982  *
5983  * Register Layout
5984  *
5985  * Bits | Access | Reset | Description
5986  * :-------|:-------|:------|:------------
5987  * [31:0] | RW | 0x0 | Empty
5988  *
5989  */
5990 /*
5991  * Field : Empty - fld
5992  *
5993  * Placeholder
5994  *
5995  * Field Access Macros:
5996  *
5997  */
5998 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISACTIVER11_FLD register field. */
5999 #define ALT_GIC_DIST_GICD_ISACTIVER11_FLD_LSB 0
6000 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISACTIVER11_FLD register field. */
6001 #define ALT_GIC_DIST_GICD_ISACTIVER11_FLD_MSB 31
6002 /* The width in bits of the ALT_GIC_DIST_GICD_ISACTIVER11_FLD register field. */
6003 #define ALT_GIC_DIST_GICD_ISACTIVER11_FLD_WIDTH 32
6004 /* The mask used to set the ALT_GIC_DIST_GICD_ISACTIVER11_FLD register field value. */
6005 #define ALT_GIC_DIST_GICD_ISACTIVER11_FLD_SET_MSK 0xffffffff
6006 /* The mask used to clear the ALT_GIC_DIST_GICD_ISACTIVER11_FLD register field value. */
6007 #define ALT_GIC_DIST_GICD_ISACTIVER11_FLD_CLR_MSK 0x00000000
6008 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER11_FLD register field. */
6009 #define ALT_GIC_DIST_GICD_ISACTIVER11_FLD_RESET 0x0
6010 /* Extracts the ALT_GIC_DIST_GICD_ISACTIVER11_FLD field value from a register. */
6011 #define ALT_GIC_DIST_GICD_ISACTIVER11_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6012 /* Produces a ALT_GIC_DIST_GICD_ISACTIVER11_FLD register field value suitable for setting the register. */
6013 #define ALT_GIC_DIST_GICD_ISACTIVER11_FLD_SET(value) (((value) << 0) & 0xffffffff)
6014 
6015 #ifndef __ASSEMBLY__
6016 /*
6017  * WARNING: The C register and register group struct declarations are provided for
6018  * convenience and illustrative purposes. They should, however, be used with
6019  * caution as the C language standard provides no guarantees about the alignment or
6020  * atomicity of device memory accesses. The recommended practice for coding device
6021  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6022  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6023  * alt_write_dword() functions for 64 bit registers.
6024  *
6025  * The struct declaration for register ALT_GIC_DIST_GICD_ISACTIVER11.
6026  */
6027 struct ALT_GIC_DIST_GICD_ISACTIVER11_s
6028 {
6029  volatile uint32_t fld : 32; /* Empty */
6030 };
6031 
6032 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISACTIVER11. */
6033 typedef struct ALT_GIC_DIST_GICD_ISACTIVER11_s ALT_GIC_DIST_GICD_ISACTIVER11_t;
6034 #endif /* __ASSEMBLY__ */
6035 
6036 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER11 register. */
6037 #define ALT_GIC_DIST_GICD_ISACTIVER11_RESET 0x00000000
6038 /* The byte offset of the ALT_GIC_DIST_GICD_ISACTIVER11 register from the beginning of the component. */
6039 #define ALT_GIC_DIST_GICD_ISACTIVER11_OFST 0x32c
6040 
6041 /*
6042  * Register : GICD_ISACTIVER12
6043  *
6044  * Interrupt Set-Active Registers
6045  *
6046  * Register Layout
6047  *
6048  * Bits | Access | Reset | Description
6049  * :-------|:-------|:------|:------------
6050  * [31:0] | RW | 0x0 | Empty
6051  *
6052  */
6053 /*
6054  * Field : Empty - fld
6055  *
6056  * Placeholder
6057  *
6058  * Field Access Macros:
6059  *
6060  */
6061 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISACTIVER12_FLD register field. */
6062 #define ALT_GIC_DIST_GICD_ISACTIVER12_FLD_LSB 0
6063 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISACTIVER12_FLD register field. */
6064 #define ALT_GIC_DIST_GICD_ISACTIVER12_FLD_MSB 31
6065 /* The width in bits of the ALT_GIC_DIST_GICD_ISACTIVER12_FLD register field. */
6066 #define ALT_GIC_DIST_GICD_ISACTIVER12_FLD_WIDTH 32
6067 /* The mask used to set the ALT_GIC_DIST_GICD_ISACTIVER12_FLD register field value. */
6068 #define ALT_GIC_DIST_GICD_ISACTIVER12_FLD_SET_MSK 0xffffffff
6069 /* The mask used to clear the ALT_GIC_DIST_GICD_ISACTIVER12_FLD register field value. */
6070 #define ALT_GIC_DIST_GICD_ISACTIVER12_FLD_CLR_MSK 0x00000000
6071 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER12_FLD register field. */
6072 #define ALT_GIC_DIST_GICD_ISACTIVER12_FLD_RESET 0x0
6073 /* Extracts the ALT_GIC_DIST_GICD_ISACTIVER12_FLD field value from a register. */
6074 #define ALT_GIC_DIST_GICD_ISACTIVER12_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6075 /* Produces a ALT_GIC_DIST_GICD_ISACTIVER12_FLD register field value suitable for setting the register. */
6076 #define ALT_GIC_DIST_GICD_ISACTIVER12_FLD_SET(value) (((value) << 0) & 0xffffffff)
6077 
6078 #ifndef __ASSEMBLY__
6079 /*
6080  * WARNING: The C register and register group struct declarations are provided for
6081  * convenience and illustrative purposes. They should, however, be used with
6082  * caution as the C language standard provides no guarantees about the alignment or
6083  * atomicity of device memory accesses. The recommended practice for coding device
6084  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6085  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6086  * alt_write_dword() functions for 64 bit registers.
6087  *
6088  * The struct declaration for register ALT_GIC_DIST_GICD_ISACTIVER12.
6089  */
6090 struct ALT_GIC_DIST_GICD_ISACTIVER12_s
6091 {
6092  volatile uint32_t fld : 32; /* Empty */
6093 };
6094 
6095 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISACTIVER12. */
6096 typedef struct ALT_GIC_DIST_GICD_ISACTIVER12_s ALT_GIC_DIST_GICD_ISACTIVER12_t;
6097 #endif /* __ASSEMBLY__ */
6098 
6099 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER12 register. */
6100 #define ALT_GIC_DIST_GICD_ISACTIVER12_RESET 0x00000000
6101 /* The byte offset of the ALT_GIC_DIST_GICD_ISACTIVER12 register from the beginning of the component. */
6102 #define ALT_GIC_DIST_GICD_ISACTIVER12_OFST 0x330
6103 
6104 /*
6105  * Register : GICD_ISACTIVER13
6106  *
6107  * Interrupt Set-Active Registers
6108  *
6109  * Register Layout
6110  *
6111  * Bits | Access | Reset | Description
6112  * :-------|:-------|:------|:------------
6113  * [31:0] | RW | 0x0 | Empty
6114  *
6115  */
6116 /*
6117  * Field : Empty - fld
6118  *
6119  * Placeholder
6120  *
6121  * Field Access Macros:
6122  *
6123  */
6124 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISACTIVER13_FLD register field. */
6125 #define ALT_GIC_DIST_GICD_ISACTIVER13_FLD_LSB 0
6126 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISACTIVER13_FLD register field. */
6127 #define ALT_GIC_DIST_GICD_ISACTIVER13_FLD_MSB 31
6128 /* The width in bits of the ALT_GIC_DIST_GICD_ISACTIVER13_FLD register field. */
6129 #define ALT_GIC_DIST_GICD_ISACTIVER13_FLD_WIDTH 32
6130 /* The mask used to set the ALT_GIC_DIST_GICD_ISACTIVER13_FLD register field value. */
6131 #define ALT_GIC_DIST_GICD_ISACTIVER13_FLD_SET_MSK 0xffffffff
6132 /* The mask used to clear the ALT_GIC_DIST_GICD_ISACTIVER13_FLD register field value. */
6133 #define ALT_GIC_DIST_GICD_ISACTIVER13_FLD_CLR_MSK 0x00000000
6134 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER13_FLD register field. */
6135 #define ALT_GIC_DIST_GICD_ISACTIVER13_FLD_RESET 0x0
6136 /* Extracts the ALT_GIC_DIST_GICD_ISACTIVER13_FLD field value from a register. */
6137 #define ALT_GIC_DIST_GICD_ISACTIVER13_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6138 /* Produces a ALT_GIC_DIST_GICD_ISACTIVER13_FLD register field value suitable for setting the register. */
6139 #define ALT_GIC_DIST_GICD_ISACTIVER13_FLD_SET(value) (((value) << 0) & 0xffffffff)
6140 
6141 #ifndef __ASSEMBLY__
6142 /*
6143  * WARNING: The C register and register group struct declarations are provided for
6144  * convenience and illustrative purposes. They should, however, be used with
6145  * caution as the C language standard provides no guarantees about the alignment or
6146  * atomicity of device memory accesses. The recommended practice for coding device
6147  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6148  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6149  * alt_write_dword() functions for 64 bit registers.
6150  *
6151  * The struct declaration for register ALT_GIC_DIST_GICD_ISACTIVER13.
6152  */
6153 struct ALT_GIC_DIST_GICD_ISACTIVER13_s
6154 {
6155  volatile uint32_t fld : 32; /* Empty */
6156 };
6157 
6158 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISACTIVER13. */
6159 typedef struct ALT_GIC_DIST_GICD_ISACTIVER13_s ALT_GIC_DIST_GICD_ISACTIVER13_t;
6160 #endif /* __ASSEMBLY__ */
6161 
6162 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER13 register. */
6163 #define ALT_GIC_DIST_GICD_ISACTIVER13_RESET 0x00000000
6164 /* The byte offset of the ALT_GIC_DIST_GICD_ISACTIVER13 register from the beginning of the component. */
6165 #define ALT_GIC_DIST_GICD_ISACTIVER13_OFST 0x334
6166 
6167 /*
6168  * Register : GICD_ISACTIVER14
6169  *
6170  * Interrupt Set-Active Registers
6171  *
6172  * Register Layout
6173  *
6174  * Bits | Access | Reset | Description
6175  * :-------|:-------|:------|:------------
6176  * [31:0] | RW | 0x0 | Empty
6177  *
6178  */
6179 /*
6180  * Field : Empty - fld
6181  *
6182  * Placeholder
6183  *
6184  * Field Access Macros:
6185  *
6186  */
6187 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISACTIVER14_FLD register field. */
6188 #define ALT_GIC_DIST_GICD_ISACTIVER14_FLD_LSB 0
6189 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISACTIVER14_FLD register field. */
6190 #define ALT_GIC_DIST_GICD_ISACTIVER14_FLD_MSB 31
6191 /* The width in bits of the ALT_GIC_DIST_GICD_ISACTIVER14_FLD register field. */
6192 #define ALT_GIC_DIST_GICD_ISACTIVER14_FLD_WIDTH 32
6193 /* The mask used to set the ALT_GIC_DIST_GICD_ISACTIVER14_FLD register field value. */
6194 #define ALT_GIC_DIST_GICD_ISACTIVER14_FLD_SET_MSK 0xffffffff
6195 /* The mask used to clear the ALT_GIC_DIST_GICD_ISACTIVER14_FLD register field value. */
6196 #define ALT_GIC_DIST_GICD_ISACTIVER14_FLD_CLR_MSK 0x00000000
6197 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER14_FLD register field. */
6198 #define ALT_GIC_DIST_GICD_ISACTIVER14_FLD_RESET 0x0
6199 /* Extracts the ALT_GIC_DIST_GICD_ISACTIVER14_FLD field value from a register. */
6200 #define ALT_GIC_DIST_GICD_ISACTIVER14_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6201 /* Produces a ALT_GIC_DIST_GICD_ISACTIVER14_FLD register field value suitable for setting the register. */
6202 #define ALT_GIC_DIST_GICD_ISACTIVER14_FLD_SET(value) (((value) << 0) & 0xffffffff)
6203 
6204 #ifndef __ASSEMBLY__
6205 /*
6206  * WARNING: The C register and register group struct declarations are provided for
6207  * convenience and illustrative purposes. They should, however, be used with
6208  * caution as the C language standard provides no guarantees about the alignment or
6209  * atomicity of device memory accesses. The recommended practice for coding device
6210  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6211  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6212  * alt_write_dword() functions for 64 bit registers.
6213  *
6214  * The struct declaration for register ALT_GIC_DIST_GICD_ISACTIVER14.
6215  */
6216 struct ALT_GIC_DIST_GICD_ISACTIVER14_s
6217 {
6218  volatile uint32_t fld : 32; /* Empty */
6219 };
6220 
6221 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISACTIVER14. */
6222 typedef struct ALT_GIC_DIST_GICD_ISACTIVER14_s ALT_GIC_DIST_GICD_ISACTIVER14_t;
6223 #endif /* __ASSEMBLY__ */
6224 
6225 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER14 register. */
6226 #define ALT_GIC_DIST_GICD_ISACTIVER14_RESET 0x00000000
6227 /* The byte offset of the ALT_GIC_DIST_GICD_ISACTIVER14 register from the beginning of the component. */
6228 #define ALT_GIC_DIST_GICD_ISACTIVER14_OFST 0x338
6229 
6230 /*
6231  * Register : GICD_ISACTIVER15
6232  *
6233  * Interrupt Set-Active Registers
6234  *
6235  * Register Layout
6236  *
6237  * Bits | Access | Reset | Description
6238  * :-------|:-------|:------|:------------
6239  * [31:0] | RW | 0x0 | Empty
6240  *
6241  */
6242 /*
6243  * Field : Empty - fld
6244  *
6245  * Placeholder
6246  *
6247  * Field Access Macros:
6248  *
6249  */
6250 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ISACTIVER15_FLD register field. */
6251 #define ALT_GIC_DIST_GICD_ISACTIVER15_FLD_LSB 0
6252 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ISACTIVER15_FLD register field. */
6253 #define ALT_GIC_DIST_GICD_ISACTIVER15_FLD_MSB 31
6254 /* The width in bits of the ALT_GIC_DIST_GICD_ISACTIVER15_FLD register field. */
6255 #define ALT_GIC_DIST_GICD_ISACTIVER15_FLD_WIDTH 32
6256 /* The mask used to set the ALT_GIC_DIST_GICD_ISACTIVER15_FLD register field value. */
6257 #define ALT_GIC_DIST_GICD_ISACTIVER15_FLD_SET_MSK 0xffffffff
6258 /* The mask used to clear the ALT_GIC_DIST_GICD_ISACTIVER15_FLD register field value. */
6259 #define ALT_GIC_DIST_GICD_ISACTIVER15_FLD_CLR_MSK 0x00000000
6260 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER15_FLD register field. */
6261 #define ALT_GIC_DIST_GICD_ISACTIVER15_FLD_RESET 0x0
6262 /* Extracts the ALT_GIC_DIST_GICD_ISACTIVER15_FLD field value from a register. */
6263 #define ALT_GIC_DIST_GICD_ISACTIVER15_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6264 /* Produces a ALT_GIC_DIST_GICD_ISACTIVER15_FLD register field value suitable for setting the register. */
6265 #define ALT_GIC_DIST_GICD_ISACTIVER15_FLD_SET(value) (((value) << 0) & 0xffffffff)
6266 
6267 #ifndef __ASSEMBLY__
6268 /*
6269  * WARNING: The C register and register group struct declarations are provided for
6270  * convenience and illustrative purposes. They should, however, be used with
6271  * caution as the C language standard provides no guarantees about the alignment or
6272  * atomicity of device memory accesses. The recommended practice for coding device
6273  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6274  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6275  * alt_write_dword() functions for 64 bit registers.
6276  *
6277  * The struct declaration for register ALT_GIC_DIST_GICD_ISACTIVER15.
6278  */
6279 struct ALT_GIC_DIST_GICD_ISACTIVER15_s
6280 {
6281  volatile uint32_t fld : 32; /* Empty */
6282 };
6283 
6284 /* The typedef declaration for register ALT_GIC_DIST_GICD_ISACTIVER15. */
6285 typedef struct ALT_GIC_DIST_GICD_ISACTIVER15_s ALT_GIC_DIST_GICD_ISACTIVER15_t;
6286 #endif /* __ASSEMBLY__ */
6287 
6288 /* The reset value of the ALT_GIC_DIST_GICD_ISACTIVER15 register. */
6289 #define ALT_GIC_DIST_GICD_ISACTIVER15_RESET 0x00000000
6290 /* The byte offset of the ALT_GIC_DIST_GICD_ISACTIVER15 register from the beginning of the component. */
6291 #define ALT_GIC_DIST_GICD_ISACTIVER15_OFST 0x33c
6292 
6293 /*
6294  * Register : GICD_ICACTIVER0
6295  *
6296  * Interrupt Clear-Active Registers
6297  *
6298  * Register Layout
6299  *
6300  * Bits | Access | Reset | Description
6301  * :-------|:-------|:------|:------------
6302  * [31:0] | RW | 0x0 | Empty
6303  *
6304  */
6305 /*
6306  * Field : Empty - fld
6307  *
6308  * Placeholder
6309  *
6310  * Field Access Macros:
6311  *
6312  */
6313 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICACTIVER0_FLD register field. */
6314 #define ALT_GIC_DIST_GICD_ICACTIVER0_FLD_LSB 0
6315 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICACTIVER0_FLD register field. */
6316 #define ALT_GIC_DIST_GICD_ICACTIVER0_FLD_MSB 31
6317 /* The width in bits of the ALT_GIC_DIST_GICD_ICACTIVER0_FLD register field. */
6318 #define ALT_GIC_DIST_GICD_ICACTIVER0_FLD_WIDTH 32
6319 /* The mask used to set the ALT_GIC_DIST_GICD_ICACTIVER0_FLD register field value. */
6320 #define ALT_GIC_DIST_GICD_ICACTIVER0_FLD_SET_MSK 0xffffffff
6321 /* The mask used to clear the ALT_GIC_DIST_GICD_ICACTIVER0_FLD register field value. */
6322 #define ALT_GIC_DIST_GICD_ICACTIVER0_FLD_CLR_MSK 0x00000000
6323 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER0_FLD register field. */
6324 #define ALT_GIC_DIST_GICD_ICACTIVER0_FLD_RESET 0x0
6325 /* Extracts the ALT_GIC_DIST_GICD_ICACTIVER0_FLD field value from a register. */
6326 #define ALT_GIC_DIST_GICD_ICACTIVER0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6327 /* Produces a ALT_GIC_DIST_GICD_ICACTIVER0_FLD register field value suitable for setting the register. */
6328 #define ALT_GIC_DIST_GICD_ICACTIVER0_FLD_SET(value) (((value) << 0) & 0xffffffff)
6329 
6330 #ifndef __ASSEMBLY__
6331 /*
6332  * WARNING: The C register and register group struct declarations are provided for
6333  * convenience and illustrative purposes. They should, however, be used with
6334  * caution as the C language standard provides no guarantees about the alignment or
6335  * atomicity of device memory accesses. The recommended practice for coding device
6336  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6337  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6338  * alt_write_dword() functions for 64 bit registers.
6339  *
6340  * The struct declaration for register ALT_GIC_DIST_GICD_ICACTIVER0.
6341  */
6342 struct ALT_GIC_DIST_GICD_ICACTIVER0_s
6343 {
6344  volatile uint32_t fld : 32; /* Empty */
6345 };
6346 
6347 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICACTIVER0. */
6348 typedef struct ALT_GIC_DIST_GICD_ICACTIVER0_s ALT_GIC_DIST_GICD_ICACTIVER0_t;
6349 #endif /* __ASSEMBLY__ */
6350 
6351 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER0 register. */
6352 #define ALT_GIC_DIST_GICD_ICACTIVER0_RESET 0x00000000
6353 /* The byte offset of the ALT_GIC_DIST_GICD_ICACTIVER0 register from the beginning of the component. */
6354 #define ALT_GIC_DIST_GICD_ICACTIVER0_OFST 0x380
6355 
6356 /*
6357  * Register : GICD_ICACTIVER1
6358  *
6359  * Interrupt Clear-Active Registers
6360  *
6361  * Register Layout
6362  *
6363  * Bits | Access | Reset | Description
6364  * :-------|:-------|:------|:------------
6365  * [31:0] | RW | 0x0 | Empty
6366  *
6367  */
6368 /*
6369  * Field : Empty - fld
6370  *
6371  * Placeholder
6372  *
6373  * Field Access Macros:
6374  *
6375  */
6376 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICACTIVER1_FLD register field. */
6377 #define ALT_GIC_DIST_GICD_ICACTIVER1_FLD_LSB 0
6378 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICACTIVER1_FLD register field. */
6379 #define ALT_GIC_DIST_GICD_ICACTIVER1_FLD_MSB 31
6380 /* The width in bits of the ALT_GIC_DIST_GICD_ICACTIVER1_FLD register field. */
6381 #define ALT_GIC_DIST_GICD_ICACTIVER1_FLD_WIDTH 32
6382 /* The mask used to set the ALT_GIC_DIST_GICD_ICACTIVER1_FLD register field value. */
6383 #define ALT_GIC_DIST_GICD_ICACTIVER1_FLD_SET_MSK 0xffffffff
6384 /* The mask used to clear the ALT_GIC_DIST_GICD_ICACTIVER1_FLD register field value. */
6385 #define ALT_GIC_DIST_GICD_ICACTIVER1_FLD_CLR_MSK 0x00000000
6386 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER1_FLD register field. */
6387 #define ALT_GIC_DIST_GICD_ICACTIVER1_FLD_RESET 0x0
6388 /* Extracts the ALT_GIC_DIST_GICD_ICACTIVER1_FLD field value from a register. */
6389 #define ALT_GIC_DIST_GICD_ICACTIVER1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6390 /* Produces a ALT_GIC_DIST_GICD_ICACTIVER1_FLD register field value suitable for setting the register. */
6391 #define ALT_GIC_DIST_GICD_ICACTIVER1_FLD_SET(value) (((value) << 0) & 0xffffffff)
6392 
6393 #ifndef __ASSEMBLY__
6394 /*
6395  * WARNING: The C register and register group struct declarations are provided for
6396  * convenience and illustrative purposes. They should, however, be used with
6397  * caution as the C language standard provides no guarantees about the alignment or
6398  * atomicity of device memory accesses. The recommended practice for coding device
6399  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6400  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6401  * alt_write_dword() functions for 64 bit registers.
6402  *
6403  * The struct declaration for register ALT_GIC_DIST_GICD_ICACTIVER1.
6404  */
6405 struct ALT_GIC_DIST_GICD_ICACTIVER1_s
6406 {
6407  volatile uint32_t fld : 32; /* Empty */
6408 };
6409 
6410 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICACTIVER1. */
6411 typedef struct ALT_GIC_DIST_GICD_ICACTIVER1_s ALT_GIC_DIST_GICD_ICACTIVER1_t;
6412 #endif /* __ASSEMBLY__ */
6413 
6414 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER1 register. */
6415 #define ALT_GIC_DIST_GICD_ICACTIVER1_RESET 0x00000000
6416 /* The byte offset of the ALT_GIC_DIST_GICD_ICACTIVER1 register from the beginning of the component. */
6417 #define ALT_GIC_DIST_GICD_ICACTIVER1_OFST 0x384
6418 
6419 /*
6420  * Register : GICD_ICACTIVER2
6421  *
6422  * Interrupt Clear-Active Registers
6423  *
6424  * Register Layout
6425  *
6426  * Bits | Access | Reset | Description
6427  * :-------|:-------|:------|:------------
6428  * [31:0] | RW | 0x0 | Empty
6429  *
6430  */
6431 /*
6432  * Field : Empty - fld
6433  *
6434  * Placeholder
6435  *
6436  * Field Access Macros:
6437  *
6438  */
6439 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICACTIVER2_FLD register field. */
6440 #define ALT_GIC_DIST_GICD_ICACTIVER2_FLD_LSB 0
6441 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICACTIVER2_FLD register field. */
6442 #define ALT_GIC_DIST_GICD_ICACTIVER2_FLD_MSB 31
6443 /* The width in bits of the ALT_GIC_DIST_GICD_ICACTIVER2_FLD register field. */
6444 #define ALT_GIC_DIST_GICD_ICACTIVER2_FLD_WIDTH 32
6445 /* The mask used to set the ALT_GIC_DIST_GICD_ICACTIVER2_FLD register field value. */
6446 #define ALT_GIC_DIST_GICD_ICACTIVER2_FLD_SET_MSK 0xffffffff
6447 /* The mask used to clear the ALT_GIC_DIST_GICD_ICACTIVER2_FLD register field value. */
6448 #define ALT_GIC_DIST_GICD_ICACTIVER2_FLD_CLR_MSK 0x00000000
6449 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER2_FLD register field. */
6450 #define ALT_GIC_DIST_GICD_ICACTIVER2_FLD_RESET 0x0
6451 /* Extracts the ALT_GIC_DIST_GICD_ICACTIVER2_FLD field value from a register. */
6452 #define ALT_GIC_DIST_GICD_ICACTIVER2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6453 /* Produces a ALT_GIC_DIST_GICD_ICACTIVER2_FLD register field value suitable for setting the register. */
6454 #define ALT_GIC_DIST_GICD_ICACTIVER2_FLD_SET(value) (((value) << 0) & 0xffffffff)
6455 
6456 #ifndef __ASSEMBLY__
6457 /*
6458  * WARNING: The C register and register group struct declarations are provided for
6459  * convenience and illustrative purposes. They should, however, be used with
6460  * caution as the C language standard provides no guarantees about the alignment or
6461  * atomicity of device memory accesses. The recommended practice for coding device
6462  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6463  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6464  * alt_write_dword() functions for 64 bit registers.
6465  *
6466  * The struct declaration for register ALT_GIC_DIST_GICD_ICACTIVER2.
6467  */
6468 struct ALT_GIC_DIST_GICD_ICACTIVER2_s
6469 {
6470  volatile uint32_t fld : 32; /* Empty */
6471 };
6472 
6473 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICACTIVER2. */
6474 typedef struct ALT_GIC_DIST_GICD_ICACTIVER2_s ALT_GIC_DIST_GICD_ICACTIVER2_t;
6475 #endif /* __ASSEMBLY__ */
6476 
6477 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER2 register. */
6478 #define ALT_GIC_DIST_GICD_ICACTIVER2_RESET 0x00000000
6479 /* The byte offset of the ALT_GIC_DIST_GICD_ICACTIVER2 register from the beginning of the component. */
6480 #define ALT_GIC_DIST_GICD_ICACTIVER2_OFST 0x388
6481 
6482 /*
6483  * Register : GICD_ICACTIVER3
6484  *
6485  * Interrupt Clear-Active Registers
6486  *
6487  * Register Layout
6488  *
6489  * Bits | Access | Reset | Description
6490  * :-------|:-------|:------|:------------
6491  * [31:0] | RW | 0x0 | Empty
6492  *
6493  */
6494 /*
6495  * Field : Empty - fld
6496  *
6497  * Placeholder
6498  *
6499  * Field Access Macros:
6500  *
6501  */
6502 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICACTIVER3_FLD register field. */
6503 #define ALT_GIC_DIST_GICD_ICACTIVER3_FLD_LSB 0
6504 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICACTIVER3_FLD register field. */
6505 #define ALT_GIC_DIST_GICD_ICACTIVER3_FLD_MSB 31
6506 /* The width in bits of the ALT_GIC_DIST_GICD_ICACTIVER3_FLD register field. */
6507 #define ALT_GIC_DIST_GICD_ICACTIVER3_FLD_WIDTH 32
6508 /* The mask used to set the ALT_GIC_DIST_GICD_ICACTIVER3_FLD register field value. */
6509 #define ALT_GIC_DIST_GICD_ICACTIVER3_FLD_SET_MSK 0xffffffff
6510 /* The mask used to clear the ALT_GIC_DIST_GICD_ICACTIVER3_FLD register field value. */
6511 #define ALT_GIC_DIST_GICD_ICACTIVER3_FLD_CLR_MSK 0x00000000
6512 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER3_FLD register field. */
6513 #define ALT_GIC_DIST_GICD_ICACTIVER3_FLD_RESET 0x0
6514 /* Extracts the ALT_GIC_DIST_GICD_ICACTIVER3_FLD field value from a register. */
6515 #define ALT_GIC_DIST_GICD_ICACTIVER3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6516 /* Produces a ALT_GIC_DIST_GICD_ICACTIVER3_FLD register field value suitable for setting the register. */
6517 #define ALT_GIC_DIST_GICD_ICACTIVER3_FLD_SET(value) (((value) << 0) & 0xffffffff)
6518 
6519 #ifndef __ASSEMBLY__
6520 /*
6521  * WARNING: The C register and register group struct declarations are provided for
6522  * convenience and illustrative purposes. They should, however, be used with
6523  * caution as the C language standard provides no guarantees about the alignment or
6524  * atomicity of device memory accesses. The recommended practice for coding device
6525  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6526  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6527  * alt_write_dword() functions for 64 bit registers.
6528  *
6529  * The struct declaration for register ALT_GIC_DIST_GICD_ICACTIVER3.
6530  */
6531 struct ALT_GIC_DIST_GICD_ICACTIVER3_s
6532 {
6533  volatile uint32_t fld : 32; /* Empty */
6534 };
6535 
6536 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICACTIVER3. */
6537 typedef struct ALT_GIC_DIST_GICD_ICACTIVER3_s ALT_GIC_DIST_GICD_ICACTIVER3_t;
6538 #endif /* __ASSEMBLY__ */
6539 
6540 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER3 register. */
6541 #define ALT_GIC_DIST_GICD_ICACTIVER3_RESET 0x00000000
6542 /* The byte offset of the ALT_GIC_DIST_GICD_ICACTIVER3 register from the beginning of the component. */
6543 #define ALT_GIC_DIST_GICD_ICACTIVER3_OFST 0x38c
6544 
6545 /*
6546  * Register : GICD_ICACTIVER4
6547  *
6548  * Interrupt Clear-Active Registers
6549  *
6550  * Register Layout
6551  *
6552  * Bits | Access | Reset | Description
6553  * :-------|:-------|:------|:------------
6554  * [31:0] | RW | 0x0 | Empty
6555  *
6556  */
6557 /*
6558  * Field : Empty - fld
6559  *
6560  * Placeholder
6561  *
6562  * Field Access Macros:
6563  *
6564  */
6565 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICACTIVER4_FLD register field. */
6566 #define ALT_GIC_DIST_GICD_ICACTIVER4_FLD_LSB 0
6567 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICACTIVER4_FLD register field. */
6568 #define ALT_GIC_DIST_GICD_ICACTIVER4_FLD_MSB 31
6569 /* The width in bits of the ALT_GIC_DIST_GICD_ICACTIVER4_FLD register field. */
6570 #define ALT_GIC_DIST_GICD_ICACTIVER4_FLD_WIDTH 32
6571 /* The mask used to set the ALT_GIC_DIST_GICD_ICACTIVER4_FLD register field value. */
6572 #define ALT_GIC_DIST_GICD_ICACTIVER4_FLD_SET_MSK 0xffffffff
6573 /* The mask used to clear the ALT_GIC_DIST_GICD_ICACTIVER4_FLD register field value. */
6574 #define ALT_GIC_DIST_GICD_ICACTIVER4_FLD_CLR_MSK 0x00000000
6575 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER4_FLD register field. */
6576 #define ALT_GIC_DIST_GICD_ICACTIVER4_FLD_RESET 0x0
6577 /* Extracts the ALT_GIC_DIST_GICD_ICACTIVER4_FLD field value from a register. */
6578 #define ALT_GIC_DIST_GICD_ICACTIVER4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6579 /* Produces a ALT_GIC_DIST_GICD_ICACTIVER4_FLD register field value suitable for setting the register. */
6580 #define ALT_GIC_DIST_GICD_ICACTIVER4_FLD_SET(value) (((value) << 0) & 0xffffffff)
6581 
6582 #ifndef __ASSEMBLY__
6583 /*
6584  * WARNING: The C register and register group struct declarations are provided for
6585  * convenience and illustrative purposes. They should, however, be used with
6586  * caution as the C language standard provides no guarantees about the alignment or
6587  * atomicity of device memory accesses. The recommended practice for coding device
6588  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6589  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6590  * alt_write_dword() functions for 64 bit registers.
6591  *
6592  * The struct declaration for register ALT_GIC_DIST_GICD_ICACTIVER4.
6593  */
6594 struct ALT_GIC_DIST_GICD_ICACTIVER4_s
6595 {
6596  volatile uint32_t fld : 32; /* Empty */
6597 };
6598 
6599 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICACTIVER4. */
6600 typedef struct ALT_GIC_DIST_GICD_ICACTIVER4_s ALT_GIC_DIST_GICD_ICACTIVER4_t;
6601 #endif /* __ASSEMBLY__ */
6602 
6603 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER4 register. */
6604 #define ALT_GIC_DIST_GICD_ICACTIVER4_RESET 0x00000000
6605 /* The byte offset of the ALT_GIC_DIST_GICD_ICACTIVER4 register from the beginning of the component. */
6606 #define ALT_GIC_DIST_GICD_ICACTIVER4_OFST 0x390
6607 
6608 /*
6609  * Register : GICD_ICACTIVER5
6610  *
6611  * Interrupt Clear-Active Registers
6612  *
6613  * Register Layout
6614  *
6615  * Bits | Access | Reset | Description
6616  * :-------|:-------|:------|:------------
6617  * [31:0] | RW | 0x0 | Empty
6618  *
6619  */
6620 /*
6621  * Field : Empty - fld
6622  *
6623  * Placeholder
6624  *
6625  * Field Access Macros:
6626  *
6627  */
6628 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICACTIVER5_FLD register field. */
6629 #define ALT_GIC_DIST_GICD_ICACTIVER5_FLD_LSB 0
6630 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICACTIVER5_FLD register field. */
6631 #define ALT_GIC_DIST_GICD_ICACTIVER5_FLD_MSB 31
6632 /* The width in bits of the ALT_GIC_DIST_GICD_ICACTIVER5_FLD register field. */
6633 #define ALT_GIC_DIST_GICD_ICACTIVER5_FLD_WIDTH 32
6634 /* The mask used to set the ALT_GIC_DIST_GICD_ICACTIVER5_FLD register field value. */
6635 #define ALT_GIC_DIST_GICD_ICACTIVER5_FLD_SET_MSK 0xffffffff
6636 /* The mask used to clear the ALT_GIC_DIST_GICD_ICACTIVER5_FLD register field value. */
6637 #define ALT_GIC_DIST_GICD_ICACTIVER5_FLD_CLR_MSK 0x00000000
6638 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER5_FLD register field. */
6639 #define ALT_GIC_DIST_GICD_ICACTIVER5_FLD_RESET 0x0
6640 /* Extracts the ALT_GIC_DIST_GICD_ICACTIVER5_FLD field value from a register. */
6641 #define ALT_GIC_DIST_GICD_ICACTIVER5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6642 /* Produces a ALT_GIC_DIST_GICD_ICACTIVER5_FLD register field value suitable for setting the register. */
6643 #define ALT_GIC_DIST_GICD_ICACTIVER5_FLD_SET(value) (((value) << 0) & 0xffffffff)
6644 
6645 #ifndef __ASSEMBLY__
6646 /*
6647  * WARNING: The C register and register group struct declarations are provided for
6648  * convenience and illustrative purposes. They should, however, be used with
6649  * caution as the C language standard provides no guarantees about the alignment or
6650  * atomicity of device memory accesses. The recommended practice for coding device
6651  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6652  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6653  * alt_write_dword() functions for 64 bit registers.
6654  *
6655  * The struct declaration for register ALT_GIC_DIST_GICD_ICACTIVER5.
6656  */
6657 struct ALT_GIC_DIST_GICD_ICACTIVER5_s
6658 {
6659  volatile uint32_t fld : 32; /* Empty */
6660 };
6661 
6662 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICACTIVER5. */
6663 typedef struct ALT_GIC_DIST_GICD_ICACTIVER5_s ALT_GIC_DIST_GICD_ICACTIVER5_t;
6664 #endif /* __ASSEMBLY__ */
6665 
6666 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER5 register. */
6667 #define ALT_GIC_DIST_GICD_ICACTIVER5_RESET 0x00000000
6668 /* The byte offset of the ALT_GIC_DIST_GICD_ICACTIVER5 register from the beginning of the component. */
6669 #define ALT_GIC_DIST_GICD_ICACTIVER5_OFST 0x394
6670 
6671 /*
6672  * Register : GICD_ICACTIVER6
6673  *
6674  * Interrupt Clear-Active Registers
6675  *
6676  * Register Layout
6677  *
6678  * Bits | Access | Reset | Description
6679  * :-------|:-------|:------|:------------
6680  * [31:0] | RW | 0x0 | Empty
6681  *
6682  */
6683 /*
6684  * Field : Empty - fld
6685  *
6686  * Placeholder
6687  *
6688  * Field Access Macros:
6689  *
6690  */
6691 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICACTIVER6_FLD register field. */
6692 #define ALT_GIC_DIST_GICD_ICACTIVER6_FLD_LSB 0
6693 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICACTIVER6_FLD register field. */
6694 #define ALT_GIC_DIST_GICD_ICACTIVER6_FLD_MSB 31
6695 /* The width in bits of the ALT_GIC_DIST_GICD_ICACTIVER6_FLD register field. */
6696 #define ALT_GIC_DIST_GICD_ICACTIVER6_FLD_WIDTH 32
6697 /* The mask used to set the ALT_GIC_DIST_GICD_ICACTIVER6_FLD register field value. */
6698 #define ALT_GIC_DIST_GICD_ICACTIVER6_FLD_SET_MSK 0xffffffff
6699 /* The mask used to clear the ALT_GIC_DIST_GICD_ICACTIVER6_FLD register field value. */
6700 #define ALT_GIC_DIST_GICD_ICACTIVER6_FLD_CLR_MSK 0x00000000
6701 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER6_FLD register field. */
6702 #define ALT_GIC_DIST_GICD_ICACTIVER6_FLD_RESET 0x0
6703 /* Extracts the ALT_GIC_DIST_GICD_ICACTIVER6_FLD field value from a register. */
6704 #define ALT_GIC_DIST_GICD_ICACTIVER6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6705 /* Produces a ALT_GIC_DIST_GICD_ICACTIVER6_FLD register field value suitable for setting the register. */
6706 #define ALT_GIC_DIST_GICD_ICACTIVER6_FLD_SET(value) (((value) << 0) & 0xffffffff)
6707 
6708 #ifndef __ASSEMBLY__
6709 /*
6710  * WARNING: The C register and register group struct declarations are provided for
6711  * convenience and illustrative purposes. They should, however, be used with
6712  * caution as the C language standard provides no guarantees about the alignment or
6713  * atomicity of device memory accesses. The recommended practice for coding device
6714  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6715  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6716  * alt_write_dword() functions for 64 bit registers.
6717  *
6718  * The struct declaration for register ALT_GIC_DIST_GICD_ICACTIVER6.
6719  */
6720 struct ALT_GIC_DIST_GICD_ICACTIVER6_s
6721 {
6722  volatile uint32_t fld : 32; /* Empty */
6723 };
6724 
6725 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICACTIVER6. */
6726 typedef struct ALT_GIC_DIST_GICD_ICACTIVER6_s ALT_GIC_DIST_GICD_ICACTIVER6_t;
6727 #endif /* __ASSEMBLY__ */
6728 
6729 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER6 register. */
6730 #define ALT_GIC_DIST_GICD_ICACTIVER6_RESET 0x00000000
6731 /* The byte offset of the ALT_GIC_DIST_GICD_ICACTIVER6 register from the beginning of the component. */
6732 #define ALT_GIC_DIST_GICD_ICACTIVER6_OFST 0x398
6733 
6734 /*
6735  * Register : GICD_ICACTIVER7
6736  *
6737  * Interrupt Clear-Active Registers
6738  *
6739  * Register Layout
6740  *
6741  * Bits | Access | Reset | Description
6742  * :-------|:-------|:------|:------------
6743  * [31:0] | RW | 0x0 | Empty
6744  *
6745  */
6746 /*
6747  * Field : Empty - fld
6748  *
6749  * Placeholder
6750  *
6751  * Field Access Macros:
6752  *
6753  */
6754 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICACTIVER7_FLD register field. */
6755 #define ALT_GIC_DIST_GICD_ICACTIVER7_FLD_LSB 0
6756 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICACTIVER7_FLD register field. */
6757 #define ALT_GIC_DIST_GICD_ICACTIVER7_FLD_MSB 31
6758 /* The width in bits of the ALT_GIC_DIST_GICD_ICACTIVER7_FLD register field. */
6759 #define ALT_GIC_DIST_GICD_ICACTIVER7_FLD_WIDTH 32
6760 /* The mask used to set the ALT_GIC_DIST_GICD_ICACTIVER7_FLD register field value. */
6761 #define ALT_GIC_DIST_GICD_ICACTIVER7_FLD_SET_MSK 0xffffffff
6762 /* The mask used to clear the ALT_GIC_DIST_GICD_ICACTIVER7_FLD register field value. */
6763 #define ALT_GIC_DIST_GICD_ICACTIVER7_FLD_CLR_MSK 0x00000000
6764 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER7_FLD register field. */
6765 #define ALT_GIC_DIST_GICD_ICACTIVER7_FLD_RESET 0x0
6766 /* Extracts the ALT_GIC_DIST_GICD_ICACTIVER7_FLD field value from a register. */
6767 #define ALT_GIC_DIST_GICD_ICACTIVER7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6768 /* Produces a ALT_GIC_DIST_GICD_ICACTIVER7_FLD register field value suitable for setting the register. */
6769 #define ALT_GIC_DIST_GICD_ICACTIVER7_FLD_SET(value) (((value) << 0) & 0xffffffff)
6770 
6771 #ifndef __ASSEMBLY__
6772 /*
6773  * WARNING: The C register and register group struct declarations are provided for
6774  * convenience and illustrative purposes. They should, however, be used with
6775  * caution as the C language standard provides no guarantees about the alignment or
6776  * atomicity of device memory accesses. The recommended practice for coding device
6777  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6778  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6779  * alt_write_dword() functions for 64 bit registers.
6780  *
6781  * The struct declaration for register ALT_GIC_DIST_GICD_ICACTIVER7.
6782  */
6783 struct ALT_GIC_DIST_GICD_ICACTIVER7_s
6784 {
6785  volatile uint32_t fld : 32; /* Empty */
6786 };
6787 
6788 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICACTIVER7. */
6789 typedef struct ALT_GIC_DIST_GICD_ICACTIVER7_s ALT_GIC_DIST_GICD_ICACTIVER7_t;
6790 #endif /* __ASSEMBLY__ */
6791 
6792 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER7 register. */
6793 #define ALT_GIC_DIST_GICD_ICACTIVER7_RESET 0x00000000
6794 /* The byte offset of the ALT_GIC_DIST_GICD_ICACTIVER7 register from the beginning of the component. */
6795 #define ALT_GIC_DIST_GICD_ICACTIVER7_OFST 0x39c
6796 
6797 /*
6798  * Register : GICD_ICACTIVER8
6799  *
6800  * Interrupt Clear-Active Registers
6801  *
6802  * Register Layout
6803  *
6804  * Bits | Access | Reset | Description
6805  * :-------|:-------|:------|:------------
6806  * [31:0] | RW | 0x0 | Empty
6807  *
6808  */
6809 /*
6810  * Field : Empty - fld
6811  *
6812  * Placeholder
6813  *
6814  * Field Access Macros:
6815  *
6816  */
6817 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICACTIVER8_FLD register field. */
6818 #define ALT_GIC_DIST_GICD_ICACTIVER8_FLD_LSB 0
6819 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICACTIVER8_FLD register field. */
6820 #define ALT_GIC_DIST_GICD_ICACTIVER8_FLD_MSB 31
6821 /* The width in bits of the ALT_GIC_DIST_GICD_ICACTIVER8_FLD register field. */
6822 #define ALT_GIC_DIST_GICD_ICACTIVER8_FLD_WIDTH 32
6823 /* The mask used to set the ALT_GIC_DIST_GICD_ICACTIVER8_FLD register field value. */
6824 #define ALT_GIC_DIST_GICD_ICACTIVER8_FLD_SET_MSK 0xffffffff
6825 /* The mask used to clear the ALT_GIC_DIST_GICD_ICACTIVER8_FLD register field value. */
6826 #define ALT_GIC_DIST_GICD_ICACTIVER8_FLD_CLR_MSK 0x00000000
6827 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER8_FLD register field. */
6828 #define ALT_GIC_DIST_GICD_ICACTIVER8_FLD_RESET 0x0
6829 /* Extracts the ALT_GIC_DIST_GICD_ICACTIVER8_FLD field value from a register. */
6830 #define ALT_GIC_DIST_GICD_ICACTIVER8_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6831 /* Produces a ALT_GIC_DIST_GICD_ICACTIVER8_FLD register field value suitable for setting the register. */
6832 #define ALT_GIC_DIST_GICD_ICACTIVER8_FLD_SET(value) (((value) << 0) & 0xffffffff)
6833 
6834 #ifndef __ASSEMBLY__
6835 /*
6836  * WARNING: The C register and register group struct declarations are provided for
6837  * convenience and illustrative purposes. They should, however, be used with
6838  * caution as the C language standard provides no guarantees about the alignment or
6839  * atomicity of device memory accesses. The recommended practice for coding device
6840  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6841  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6842  * alt_write_dword() functions for 64 bit registers.
6843  *
6844  * The struct declaration for register ALT_GIC_DIST_GICD_ICACTIVER8.
6845  */
6846 struct ALT_GIC_DIST_GICD_ICACTIVER8_s
6847 {
6848  volatile uint32_t fld : 32; /* Empty */
6849 };
6850 
6851 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICACTIVER8. */
6852 typedef struct ALT_GIC_DIST_GICD_ICACTIVER8_s ALT_GIC_DIST_GICD_ICACTIVER8_t;
6853 #endif /* __ASSEMBLY__ */
6854 
6855 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER8 register. */
6856 #define ALT_GIC_DIST_GICD_ICACTIVER8_RESET 0x00000000
6857 /* The byte offset of the ALT_GIC_DIST_GICD_ICACTIVER8 register from the beginning of the component. */
6858 #define ALT_GIC_DIST_GICD_ICACTIVER8_OFST 0x3a0
6859 
6860 /*
6861  * Register : GICD_ICACTIVER9
6862  *
6863  * Interrupt Clear-Active Registers
6864  *
6865  * Register Layout
6866  *
6867  * Bits | Access | Reset | Description
6868  * :-------|:-------|:------|:------------
6869  * [31:0] | RW | 0x0 | Empty
6870  *
6871  */
6872 /*
6873  * Field : Empty - fld
6874  *
6875  * Placeholder
6876  *
6877  * Field Access Macros:
6878  *
6879  */
6880 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICACTIVER9_FLD register field. */
6881 #define ALT_GIC_DIST_GICD_ICACTIVER9_FLD_LSB 0
6882 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICACTIVER9_FLD register field. */
6883 #define ALT_GIC_DIST_GICD_ICACTIVER9_FLD_MSB 31
6884 /* The width in bits of the ALT_GIC_DIST_GICD_ICACTIVER9_FLD register field. */
6885 #define ALT_GIC_DIST_GICD_ICACTIVER9_FLD_WIDTH 32
6886 /* The mask used to set the ALT_GIC_DIST_GICD_ICACTIVER9_FLD register field value. */
6887 #define ALT_GIC_DIST_GICD_ICACTIVER9_FLD_SET_MSK 0xffffffff
6888 /* The mask used to clear the ALT_GIC_DIST_GICD_ICACTIVER9_FLD register field value. */
6889 #define ALT_GIC_DIST_GICD_ICACTIVER9_FLD_CLR_MSK 0x00000000
6890 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER9_FLD register field. */
6891 #define ALT_GIC_DIST_GICD_ICACTIVER9_FLD_RESET 0x0
6892 /* Extracts the ALT_GIC_DIST_GICD_ICACTIVER9_FLD field value from a register. */
6893 #define ALT_GIC_DIST_GICD_ICACTIVER9_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6894 /* Produces a ALT_GIC_DIST_GICD_ICACTIVER9_FLD register field value suitable for setting the register. */
6895 #define ALT_GIC_DIST_GICD_ICACTIVER9_FLD_SET(value) (((value) << 0) & 0xffffffff)
6896 
6897 #ifndef __ASSEMBLY__
6898 /*
6899  * WARNING: The C register and register group struct declarations are provided for
6900  * convenience and illustrative purposes. They should, however, be used with
6901  * caution as the C language standard provides no guarantees about the alignment or
6902  * atomicity of device memory accesses. The recommended practice for coding device
6903  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6904  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6905  * alt_write_dword() functions for 64 bit registers.
6906  *
6907  * The struct declaration for register ALT_GIC_DIST_GICD_ICACTIVER9.
6908  */
6909 struct ALT_GIC_DIST_GICD_ICACTIVER9_s
6910 {
6911  volatile uint32_t fld : 32; /* Empty */
6912 };
6913 
6914 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICACTIVER9. */
6915 typedef struct ALT_GIC_DIST_GICD_ICACTIVER9_s ALT_GIC_DIST_GICD_ICACTIVER9_t;
6916 #endif /* __ASSEMBLY__ */
6917 
6918 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER9 register. */
6919 #define ALT_GIC_DIST_GICD_ICACTIVER9_RESET 0x00000000
6920 /* The byte offset of the ALT_GIC_DIST_GICD_ICACTIVER9 register from the beginning of the component. */
6921 #define ALT_GIC_DIST_GICD_ICACTIVER9_OFST 0x3a4
6922 
6923 /*
6924  * Register : GICD_ICACTIVER10
6925  *
6926  * Interrupt Clear-Active Registers
6927  *
6928  * Register Layout
6929  *
6930  * Bits | Access | Reset | Description
6931  * :-------|:-------|:------|:------------
6932  * [31:0] | RW | 0x0 | Empty
6933  *
6934  */
6935 /*
6936  * Field : Empty - fld
6937  *
6938  * Placeholder
6939  *
6940  * Field Access Macros:
6941  *
6942  */
6943 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICACTIVER10_FLD register field. */
6944 #define ALT_GIC_DIST_GICD_ICACTIVER10_FLD_LSB 0
6945 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICACTIVER10_FLD register field. */
6946 #define ALT_GIC_DIST_GICD_ICACTIVER10_FLD_MSB 31
6947 /* The width in bits of the ALT_GIC_DIST_GICD_ICACTIVER10_FLD register field. */
6948 #define ALT_GIC_DIST_GICD_ICACTIVER10_FLD_WIDTH 32
6949 /* The mask used to set the ALT_GIC_DIST_GICD_ICACTIVER10_FLD register field value. */
6950 #define ALT_GIC_DIST_GICD_ICACTIVER10_FLD_SET_MSK 0xffffffff
6951 /* The mask used to clear the ALT_GIC_DIST_GICD_ICACTIVER10_FLD register field value. */
6952 #define ALT_GIC_DIST_GICD_ICACTIVER10_FLD_CLR_MSK 0x00000000
6953 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER10_FLD register field. */
6954 #define ALT_GIC_DIST_GICD_ICACTIVER10_FLD_RESET 0x0
6955 /* Extracts the ALT_GIC_DIST_GICD_ICACTIVER10_FLD field value from a register. */
6956 #define ALT_GIC_DIST_GICD_ICACTIVER10_FLD_GET(value) (((value) & 0xffffffff) >> 0)
6957 /* Produces a ALT_GIC_DIST_GICD_ICACTIVER10_FLD register field value suitable for setting the register. */
6958 #define ALT_GIC_DIST_GICD_ICACTIVER10_FLD_SET(value) (((value) << 0) & 0xffffffff)
6959 
6960 #ifndef __ASSEMBLY__
6961 /*
6962  * WARNING: The C register and register group struct declarations are provided for
6963  * convenience and illustrative purposes. They should, however, be used with
6964  * caution as the C language standard provides no guarantees about the alignment or
6965  * atomicity of device memory accesses. The recommended practice for coding device
6966  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6967  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6968  * alt_write_dword() functions for 64 bit registers.
6969  *
6970  * The struct declaration for register ALT_GIC_DIST_GICD_ICACTIVER10.
6971  */
6972 struct ALT_GIC_DIST_GICD_ICACTIVER10_s
6973 {
6974  volatile uint32_t fld : 32; /* Empty */
6975 };
6976 
6977 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICACTIVER10. */
6978 typedef struct ALT_GIC_DIST_GICD_ICACTIVER10_s ALT_GIC_DIST_GICD_ICACTIVER10_t;
6979 #endif /* __ASSEMBLY__ */
6980 
6981 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER10 register. */
6982 #define ALT_GIC_DIST_GICD_ICACTIVER10_RESET 0x00000000
6983 /* The byte offset of the ALT_GIC_DIST_GICD_ICACTIVER10 register from the beginning of the component. */
6984 #define ALT_GIC_DIST_GICD_ICACTIVER10_OFST 0x3a8
6985 
6986 /*
6987  * Register : GICD_ICACTIVER11
6988  *
6989  * Interrupt Clear-Active Registers
6990  *
6991  * Register Layout
6992  *
6993  * Bits | Access | Reset | Description
6994  * :-------|:-------|:------|:------------
6995  * [31:0] | RW | 0x0 | Empty
6996  *
6997  */
6998 /*
6999  * Field : Empty - fld
7000  *
7001  * Placeholder
7002  *
7003  * Field Access Macros:
7004  *
7005  */
7006 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICACTIVER11_FLD register field. */
7007 #define ALT_GIC_DIST_GICD_ICACTIVER11_FLD_LSB 0
7008 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICACTIVER11_FLD register field. */
7009 #define ALT_GIC_DIST_GICD_ICACTIVER11_FLD_MSB 31
7010 /* The width in bits of the ALT_GIC_DIST_GICD_ICACTIVER11_FLD register field. */
7011 #define ALT_GIC_DIST_GICD_ICACTIVER11_FLD_WIDTH 32
7012 /* The mask used to set the ALT_GIC_DIST_GICD_ICACTIVER11_FLD register field value. */
7013 #define ALT_GIC_DIST_GICD_ICACTIVER11_FLD_SET_MSK 0xffffffff
7014 /* The mask used to clear the ALT_GIC_DIST_GICD_ICACTIVER11_FLD register field value. */
7015 #define ALT_GIC_DIST_GICD_ICACTIVER11_FLD_CLR_MSK 0x00000000
7016 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER11_FLD register field. */
7017 #define ALT_GIC_DIST_GICD_ICACTIVER11_FLD_RESET 0x0
7018 /* Extracts the ALT_GIC_DIST_GICD_ICACTIVER11_FLD field value from a register. */
7019 #define ALT_GIC_DIST_GICD_ICACTIVER11_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7020 /* Produces a ALT_GIC_DIST_GICD_ICACTIVER11_FLD register field value suitable for setting the register. */
7021 #define ALT_GIC_DIST_GICD_ICACTIVER11_FLD_SET(value) (((value) << 0) & 0xffffffff)
7022 
7023 #ifndef __ASSEMBLY__
7024 /*
7025  * WARNING: The C register and register group struct declarations are provided for
7026  * convenience and illustrative purposes. They should, however, be used with
7027  * caution as the C language standard provides no guarantees about the alignment or
7028  * atomicity of device memory accesses. The recommended practice for coding device
7029  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7030  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7031  * alt_write_dword() functions for 64 bit registers.
7032  *
7033  * The struct declaration for register ALT_GIC_DIST_GICD_ICACTIVER11.
7034  */
7035 struct ALT_GIC_DIST_GICD_ICACTIVER11_s
7036 {
7037  volatile uint32_t fld : 32; /* Empty */
7038 };
7039 
7040 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICACTIVER11. */
7041 typedef struct ALT_GIC_DIST_GICD_ICACTIVER11_s ALT_GIC_DIST_GICD_ICACTIVER11_t;
7042 #endif /* __ASSEMBLY__ */
7043 
7044 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER11 register. */
7045 #define ALT_GIC_DIST_GICD_ICACTIVER11_RESET 0x00000000
7046 /* The byte offset of the ALT_GIC_DIST_GICD_ICACTIVER11 register from the beginning of the component. */
7047 #define ALT_GIC_DIST_GICD_ICACTIVER11_OFST 0x3ac
7048 
7049 /*
7050  * Register : GICD_ICACTIVER12
7051  *
7052  * Interrupt Clear-Active Registers
7053  *
7054  * Register Layout
7055  *
7056  * Bits | Access | Reset | Description
7057  * :-------|:-------|:------|:------------
7058  * [31:0] | RW | 0x0 | Empty
7059  *
7060  */
7061 /*
7062  * Field : Empty - fld
7063  *
7064  * Placeholder
7065  *
7066  * Field Access Macros:
7067  *
7068  */
7069 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICACTIVER12_FLD register field. */
7070 #define ALT_GIC_DIST_GICD_ICACTIVER12_FLD_LSB 0
7071 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICACTIVER12_FLD register field. */
7072 #define ALT_GIC_DIST_GICD_ICACTIVER12_FLD_MSB 31
7073 /* The width in bits of the ALT_GIC_DIST_GICD_ICACTIVER12_FLD register field. */
7074 #define ALT_GIC_DIST_GICD_ICACTIVER12_FLD_WIDTH 32
7075 /* The mask used to set the ALT_GIC_DIST_GICD_ICACTIVER12_FLD register field value. */
7076 #define ALT_GIC_DIST_GICD_ICACTIVER12_FLD_SET_MSK 0xffffffff
7077 /* The mask used to clear the ALT_GIC_DIST_GICD_ICACTIVER12_FLD register field value. */
7078 #define ALT_GIC_DIST_GICD_ICACTIVER12_FLD_CLR_MSK 0x00000000
7079 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER12_FLD register field. */
7080 #define ALT_GIC_DIST_GICD_ICACTIVER12_FLD_RESET 0x0
7081 /* Extracts the ALT_GIC_DIST_GICD_ICACTIVER12_FLD field value from a register. */
7082 #define ALT_GIC_DIST_GICD_ICACTIVER12_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7083 /* Produces a ALT_GIC_DIST_GICD_ICACTIVER12_FLD register field value suitable for setting the register. */
7084 #define ALT_GIC_DIST_GICD_ICACTIVER12_FLD_SET(value) (((value) << 0) & 0xffffffff)
7085 
7086 #ifndef __ASSEMBLY__
7087 /*
7088  * WARNING: The C register and register group struct declarations are provided for
7089  * convenience and illustrative purposes. They should, however, be used with
7090  * caution as the C language standard provides no guarantees about the alignment or
7091  * atomicity of device memory accesses. The recommended practice for coding device
7092  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7093  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7094  * alt_write_dword() functions for 64 bit registers.
7095  *
7096  * The struct declaration for register ALT_GIC_DIST_GICD_ICACTIVER12.
7097  */
7098 struct ALT_GIC_DIST_GICD_ICACTIVER12_s
7099 {
7100  volatile uint32_t fld : 32; /* Empty */
7101 };
7102 
7103 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICACTIVER12. */
7104 typedef struct ALT_GIC_DIST_GICD_ICACTIVER12_s ALT_GIC_DIST_GICD_ICACTIVER12_t;
7105 #endif /* __ASSEMBLY__ */
7106 
7107 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER12 register. */
7108 #define ALT_GIC_DIST_GICD_ICACTIVER12_RESET 0x00000000
7109 /* The byte offset of the ALT_GIC_DIST_GICD_ICACTIVER12 register from the beginning of the component. */
7110 #define ALT_GIC_DIST_GICD_ICACTIVER12_OFST 0x3b0
7111 
7112 /*
7113  * Register : GICD_ICACTIVER13
7114  *
7115  * Interrupt Clear-Active Registers
7116  *
7117  * Register Layout
7118  *
7119  * Bits | Access | Reset | Description
7120  * :-------|:-------|:------|:------------
7121  * [31:0] | RW | 0x0 | Empty
7122  *
7123  */
7124 /*
7125  * Field : Empty - fld
7126  *
7127  * Placeholder
7128  *
7129  * Field Access Macros:
7130  *
7131  */
7132 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICACTIVER13_FLD register field. */
7133 #define ALT_GIC_DIST_GICD_ICACTIVER13_FLD_LSB 0
7134 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICACTIVER13_FLD register field. */
7135 #define ALT_GIC_DIST_GICD_ICACTIVER13_FLD_MSB 31
7136 /* The width in bits of the ALT_GIC_DIST_GICD_ICACTIVER13_FLD register field. */
7137 #define ALT_GIC_DIST_GICD_ICACTIVER13_FLD_WIDTH 32
7138 /* The mask used to set the ALT_GIC_DIST_GICD_ICACTIVER13_FLD register field value. */
7139 #define ALT_GIC_DIST_GICD_ICACTIVER13_FLD_SET_MSK 0xffffffff
7140 /* The mask used to clear the ALT_GIC_DIST_GICD_ICACTIVER13_FLD register field value. */
7141 #define ALT_GIC_DIST_GICD_ICACTIVER13_FLD_CLR_MSK 0x00000000
7142 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER13_FLD register field. */
7143 #define ALT_GIC_DIST_GICD_ICACTIVER13_FLD_RESET 0x0
7144 /* Extracts the ALT_GIC_DIST_GICD_ICACTIVER13_FLD field value from a register. */
7145 #define ALT_GIC_DIST_GICD_ICACTIVER13_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7146 /* Produces a ALT_GIC_DIST_GICD_ICACTIVER13_FLD register field value suitable for setting the register. */
7147 #define ALT_GIC_DIST_GICD_ICACTIVER13_FLD_SET(value) (((value) << 0) & 0xffffffff)
7148 
7149 #ifndef __ASSEMBLY__
7150 /*
7151  * WARNING: The C register and register group struct declarations are provided for
7152  * convenience and illustrative purposes. They should, however, be used with
7153  * caution as the C language standard provides no guarantees about the alignment or
7154  * atomicity of device memory accesses. The recommended practice for coding device
7155  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7156  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7157  * alt_write_dword() functions for 64 bit registers.
7158  *
7159  * The struct declaration for register ALT_GIC_DIST_GICD_ICACTIVER13.
7160  */
7161 struct ALT_GIC_DIST_GICD_ICACTIVER13_s
7162 {
7163  volatile uint32_t fld : 32; /* Empty */
7164 };
7165 
7166 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICACTIVER13. */
7167 typedef struct ALT_GIC_DIST_GICD_ICACTIVER13_s ALT_GIC_DIST_GICD_ICACTIVER13_t;
7168 #endif /* __ASSEMBLY__ */
7169 
7170 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER13 register. */
7171 #define ALT_GIC_DIST_GICD_ICACTIVER13_RESET 0x00000000
7172 /* The byte offset of the ALT_GIC_DIST_GICD_ICACTIVER13 register from the beginning of the component. */
7173 #define ALT_GIC_DIST_GICD_ICACTIVER13_OFST 0x3b4
7174 
7175 /*
7176  * Register : GICD_ICACTIVER14
7177  *
7178  * Interrupt Clear-Active Registers
7179  *
7180  * Register Layout
7181  *
7182  * Bits | Access | Reset | Description
7183  * :-------|:-------|:------|:------------
7184  * [31:0] | RW | 0x0 | Empty
7185  *
7186  */
7187 /*
7188  * Field : Empty - fld
7189  *
7190  * Placeholder
7191  *
7192  * Field Access Macros:
7193  *
7194  */
7195 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICACTIVER14_FLD register field. */
7196 #define ALT_GIC_DIST_GICD_ICACTIVER14_FLD_LSB 0
7197 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICACTIVER14_FLD register field. */
7198 #define ALT_GIC_DIST_GICD_ICACTIVER14_FLD_MSB 31
7199 /* The width in bits of the ALT_GIC_DIST_GICD_ICACTIVER14_FLD register field. */
7200 #define ALT_GIC_DIST_GICD_ICACTIVER14_FLD_WIDTH 32
7201 /* The mask used to set the ALT_GIC_DIST_GICD_ICACTIVER14_FLD register field value. */
7202 #define ALT_GIC_DIST_GICD_ICACTIVER14_FLD_SET_MSK 0xffffffff
7203 /* The mask used to clear the ALT_GIC_DIST_GICD_ICACTIVER14_FLD register field value. */
7204 #define ALT_GIC_DIST_GICD_ICACTIVER14_FLD_CLR_MSK 0x00000000
7205 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER14_FLD register field. */
7206 #define ALT_GIC_DIST_GICD_ICACTIVER14_FLD_RESET 0x0
7207 /* Extracts the ALT_GIC_DIST_GICD_ICACTIVER14_FLD field value from a register. */
7208 #define ALT_GIC_DIST_GICD_ICACTIVER14_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7209 /* Produces a ALT_GIC_DIST_GICD_ICACTIVER14_FLD register field value suitable for setting the register. */
7210 #define ALT_GIC_DIST_GICD_ICACTIVER14_FLD_SET(value) (((value) << 0) & 0xffffffff)
7211 
7212 #ifndef __ASSEMBLY__
7213 /*
7214  * WARNING: The C register and register group struct declarations are provided for
7215  * convenience and illustrative purposes. They should, however, be used with
7216  * caution as the C language standard provides no guarantees about the alignment or
7217  * atomicity of device memory accesses. The recommended practice for coding device
7218  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7219  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7220  * alt_write_dword() functions for 64 bit registers.
7221  *
7222  * The struct declaration for register ALT_GIC_DIST_GICD_ICACTIVER14.
7223  */
7224 struct ALT_GIC_DIST_GICD_ICACTIVER14_s
7225 {
7226  volatile uint32_t fld : 32; /* Empty */
7227 };
7228 
7229 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICACTIVER14. */
7230 typedef struct ALT_GIC_DIST_GICD_ICACTIVER14_s ALT_GIC_DIST_GICD_ICACTIVER14_t;
7231 #endif /* __ASSEMBLY__ */
7232 
7233 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER14 register. */
7234 #define ALT_GIC_DIST_GICD_ICACTIVER14_RESET 0x00000000
7235 /* The byte offset of the ALT_GIC_DIST_GICD_ICACTIVER14 register from the beginning of the component. */
7236 #define ALT_GIC_DIST_GICD_ICACTIVER14_OFST 0x3b8
7237 
7238 /*
7239  * Register : GICD_ICACTIVER15
7240  *
7241  * Interrupt Clear-Active Registers
7242  *
7243  * Register Layout
7244  *
7245  * Bits | Access | Reset | Description
7246  * :-------|:-------|:------|:------------
7247  * [31:0] | RW | 0x0 | Empty
7248  *
7249  */
7250 /*
7251  * Field : Empty - fld
7252  *
7253  * Placeholder
7254  *
7255  * Field Access Macros:
7256  *
7257  */
7258 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICACTIVER15_FLD register field. */
7259 #define ALT_GIC_DIST_GICD_ICACTIVER15_FLD_LSB 0
7260 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICACTIVER15_FLD register field. */
7261 #define ALT_GIC_DIST_GICD_ICACTIVER15_FLD_MSB 31
7262 /* The width in bits of the ALT_GIC_DIST_GICD_ICACTIVER15_FLD register field. */
7263 #define ALT_GIC_DIST_GICD_ICACTIVER15_FLD_WIDTH 32
7264 /* The mask used to set the ALT_GIC_DIST_GICD_ICACTIVER15_FLD register field value. */
7265 #define ALT_GIC_DIST_GICD_ICACTIVER15_FLD_SET_MSK 0xffffffff
7266 /* The mask used to clear the ALT_GIC_DIST_GICD_ICACTIVER15_FLD register field value. */
7267 #define ALT_GIC_DIST_GICD_ICACTIVER15_FLD_CLR_MSK 0x00000000
7268 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER15_FLD register field. */
7269 #define ALT_GIC_DIST_GICD_ICACTIVER15_FLD_RESET 0x0
7270 /* Extracts the ALT_GIC_DIST_GICD_ICACTIVER15_FLD field value from a register. */
7271 #define ALT_GIC_DIST_GICD_ICACTIVER15_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7272 /* Produces a ALT_GIC_DIST_GICD_ICACTIVER15_FLD register field value suitable for setting the register. */
7273 #define ALT_GIC_DIST_GICD_ICACTIVER15_FLD_SET(value) (((value) << 0) & 0xffffffff)
7274 
7275 #ifndef __ASSEMBLY__
7276 /*
7277  * WARNING: The C register and register group struct declarations are provided for
7278  * convenience and illustrative purposes. They should, however, be used with
7279  * caution as the C language standard provides no guarantees about the alignment or
7280  * atomicity of device memory accesses. The recommended practice for coding device
7281  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7282  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7283  * alt_write_dword() functions for 64 bit registers.
7284  *
7285  * The struct declaration for register ALT_GIC_DIST_GICD_ICACTIVER15.
7286  */
7287 struct ALT_GIC_DIST_GICD_ICACTIVER15_s
7288 {
7289  volatile uint32_t fld : 32; /* Empty */
7290 };
7291 
7292 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICACTIVER15. */
7293 typedef struct ALT_GIC_DIST_GICD_ICACTIVER15_s ALT_GIC_DIST_GICD_ICACTIVER15_t;
7294 #endif /* __ASSEMBLY__ */
7295 
7296 /* The reset value of the ALT_GIC_DIST_GICD_ICACTIVER15 register. */
7297 #define ALT_GIC_DIST_GICD_ICACTIVER15_RESET 0x00000000
7298 /* The byte offset of the ALT_GIC_DIST_GICD_ICACTIVER15 register from the beginning of the component. */
7299 #define ALT_GIC_DIST_GICD_ICACTIVER15_OFST 0x3bc
7300 
7301 /*
7302  * Register : GICD_IPRIORITYR0
7303  *
7304  * Interrupt Priority Registers
7305  *
7306  * Register Layout
7307  *
7308  * Bits | Access | Reset | Description
7309  * :-------|:-------|:------|:------------
7310  * [31:0] | RW | 0x0 | Empty
7311  *
7312  */
7313 /*
7314  * Field : Empty - fld
7315  *
7316  * Placeholder
7317  *
7318  * Field Access Macros:
7319  *
7320  */
7321 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR0_FLD register field. */
7322 #define ALT_GIC_DIST_GICD_IPRIORITYR0_FLD_LSB 0
7323 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR0_FLD register field. */
7324 #define ALT_GIC_DIST_GICD_IPRIORITYR0_FLD_MSB 31
7325 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR0_FLD register field. */
7326 #define ALT_GIC_DIST_GICD_IPRIORITYR0_FLD_WIDTH 32
7327 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR0_FLD register field value. */
7328 #define ALT_GIC_DIST_GICD_IPRIORITYR0_FLD_SET_MSK 0xffffffff
7329 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR0_FLD register field value. */
7330 #define ALT_GIC_DIST_GICD_IPRIORITYR0_FLD_CLR_MSK 0x00000000
7331 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR0_FLD register field. */
7332 #define ALT_GIC_DIST_GICD_IPRIORITYR0_FLD_RESET 0x0
7333 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR0_FLD field value from a register. */
7334 #define ALT_GIC_DIST_GICD_IPRIORITYR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7335 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR0_FLD register field value suitable for setting the register. */
7336 #define ALT_GIC_DIST_GICD_IPRIORITYR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
7337 
7338 #ifndef __ASSEMBLY__
7339 /*
7340  * WARNING: The C register and register group struct declarations are provided for
7341  * convenience and illustrative purposes. They should, however, be used with
7342  * caution as the C language standard provides no guarantees about the alignment or
7343  * atomicity of device memory accesses. The recommended practice for coding device
7344  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7345  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7346  * alt_write_dword() functions for 64 bit registers.
7347  *
7348  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR0.
7349  */
7350 struct ALT_GIC_DIST_GICD_IPRIORITYR0_s
7351 {
7352  volatile uint32_t fld : 32; /* Empty */
7353 };
7354 
7355 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR0. */
7356 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR0_s ALT_GIC_DIST_GICD_IPRIORITYR0_t;
7357 #endif /* __ASSEMBLY__ */
7358 
7359 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR0 register. */
7360 #define ALT_GIC_DIST_GICD_IPRIORITYR0_RESET 0x00000000
7361 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR0 register from the beginning of the component. */
7362 #define ALT_GIC_DIST_GICD_IPRIORITYR0_OFST 0x400
7363 
7364 /*
7365  * Register : GICD_IPRIORITYR1
7366  *
7367  * Interrupt Priority Registers
7368  *
7369  * Register Layout
7370  *
7371  * Bits | Access | Reset | Description
7372  * :-------|:-------|:------|:------------
7373  * [31:0] | RW | 0x0 | Empty
7374  *
7375  */
7376 /*
7377  * Field : Empty - fld
7378  *
7379  * Placeholder
7380  *
7381  * Field Access Macros:
7382  *
7383  */
7384 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR1_FLD register field. */
7385 #define ALT_GIC_DIST_GICD_IPRIORITYR1_FLD_LSB 0
7386 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR1_FLD register field. */
7387 #define ALT_GIC_DIST_GICD_IPRIORITYR1_FLD_MSB 31
7388 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR1_FLD register field. */
7389 #define ALT_GIC_DIST_GICD_IPRIORITYR1_FLD_WIDTH 32
7390 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR1_FLD register field value. */
7391 #define ALT_GIC_DIST_GICD_IPRIORITYR1_FLD_SET_MSK 0xffffffff
7392 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR1_FLD register field value. */
7393 #define ALT_GIC_DIST_GICD_IPRIORITYR1_FLD_CLR_MSK 0x00000000
7394 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR1_FLD register field. */
7395 #define ALT_GIC_DIST_GICD_IPRIORITYR1_FLD_RESET 0x0
7396 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR1_FLD field value from a register. */
7397 #define ALT_GIC_DIST_GICD_IPRIORITYR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7398 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR1_FLD register field value suitable for setting the register. */
7399 #define ALT_GIC_DIST_GICD_IPRIORITYR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
7400 
7401 #ifndef __ASSEMBLY__
7402 /*
7403  * WARNING: The C register and register group struct declarations are provided for
7404  * convenience and illustrative purposes. They should, however, be used with
7405  * caution as the C language standard provides no guarantees about the alignment or
7406  * atomicity of device memory accesses. The recommended practice for coding device
7407  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7408  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7409  * alt_write_dword() functions for 64 bit registers.
7410  *
7411  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR1.
7412  */
7413 struct ALT_GIC_DIST_GICD_IPRIORITYR1_s
7414 {
7415  volatile uint32_t fld : 32; /* Empty */
7416 };
7417 
7418 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR1. */
7419 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR1_s ALT_GIC_DIST_GICD_IPRIORITYR1_t;
7420 #endif /* __ASSEMBLY__ */
7421 
7422 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR1 register. */
7423 #define ALT_GIC_DIST_GICD_IPRIORITYR1_RESET 0x00000000
7424 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR1 register from the beginning of the component. */
7425 #define ALT_GIC_DIST_GICD_IPRIORITYR1_OFST 0x404
7426 
7427 /*
7428  * Register : GICD_IPRIORITYR2
7429  *
7430  * Interrupt Priority Registers
7431  *
7432  * Register Layout
7433  *
7434  * Bits | Access | Reset | Description
7435  * :-------|:-------|:------|:------------
7436  * [31:0] | RW | 0x0 | Empty
7437  *
7438  */
7439 /*
7440  * Field : Empty - fld
7441  *
7442  * Placeholder
7443  *
7444  * Field Access Macros:
7445  *
7446  */
7447 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR2_FLD register field. */
7448 #define ALT_GIC_DIST_GICD_IPRIORITYR2_FLD_LSB 0
7449 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR2_FLD register field. */
7450 #define ALT_GIC_DIST_GICD_IPRIORITYR2_FLD_MSB 31
7451 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR2_FLD register field. */
7452 #define ALT_GIC_DIST_GICD_IPRIORITYR2_FLD_WIDTH 32
7453 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR2_FLD register field value. */
7454 #define ALT_GIC_DIST_GICD_IPRIORITYR2_FLD_SET_MSK 0xffffffff
7455 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR2_FLD register field value. */
7456 #define ALT_GIC_DIST_GICD_IPRIORITYR2_FLD_CLR_MSK 0x00000000
7457 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR2_FLD register field. */
7458 #define ALT_GIC_DIST_GICD_IPRIORITYR2_FLD_RESET 0x0
7459 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR2_FLD field value from a register. */
7460 #define ALT_GIC_DIST_GICD_IPRIORITYR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7461 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR2_FLD register field value suitable for setting the register. */
7462 #define ALT_GIC_DIST_GICD_IPRIORITYR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
7463 
7464 #ifndef __ASSEMBLY__
7465 /*
7466  * WARNING: The C register and register group struct declarations are provided for
7467  * convenience and illustrative purposes. They should, however, be used with
7468  * caution as the C language standard provides no guarantees about the alignment or
7469  * atomicity of device memory accesses. The recommended practice for coding device
7470  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7471  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7472  * alt_write_dword() functions for 64 bit registers.
7473  *
7474  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR2.
7475  */
7476 struct ALT_GIC_DIST_GICD_IPRIORITYR2_s
7477 {
7478  volatile uint32_t fld : 32; /* Empty */
7479 };
7480 
7481 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR2. */
7482 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR2_s ALT_GIC_DIST_GICD_IPRIORITYR2_t;
7483 #endif /* __ASSEMBLY__ */
7484 
7485 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR2 register. */
7486 #define ALT_GIC_DIST_GICD_IPRIORITYR2_RESET 0x00000000
7487 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR2 register from the beginning of the component. */
7488 #define ALT_GIC_DIST_GICD_IPRIORITYR2_OFST 0x408
7489 
7490 /*
7491  * Register : GICD_IPRIORITYR3
7492  *
7493  * Interrupt Priority Registers
7494  *
7495  * Register Layout
7496  *
7497  * Bits | Access | Reset | Description
7498  * :-------|:-------|:------|:------------
7499  * [31:0] | RW | 0x0 | Empty
7500  *
7501  */
7502 /*
7503  * Field : Empty - fld
7504  *
7505  * Placeholder
7506  *
7507  * Field Access Macros:
7508  *
7509  */
7510 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR3_FLD register field. */
7511 #define ALT_GIC_DIST_GICD_IPRIORITYR3_FLD_LSB 0
7512 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR3_FLD register field. */
7513 #define ALT_GIC_DIST_GICD_IPRIORITYR3_FLD_MSB 31
7514 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR3_FLD register field. */
7515 #define ALT_GIC_DIST_GICD_IPRIORITYR3_FLD_WIDTH 32
7516 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR3_FLD register field value. */
7517 #define ALT_GIC_DIST_GICD_IPRIORITYR3_FLD_SET_MSK 0xffffffff
7518 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR3_FLD register field value. */
7519 #define ALT_GIC_DIST_GICD_IPRIORITYR3_FLD_CLR_MSK 0x00000000
7520 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR3_FLD register field. */
7521 #define ALT_GIC_DIST_GICD_IPRIORITYR3_FLD_RESET 0x0
7522 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR3_FLD field value from a register. */
7523 #define ALT_GIC_DIST_GICD_IPRIORITYR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7524 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR3_FLD register field value suitable for setting the register. */
7525 #define ALT_GIC_DIST_GICD_IPRIORITYR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
7526 
7527 #ifndef __ASSEMBLY__
7528 /*
7529  * WARNING: The C register and register group struct declarations are provided for
7530  * convenience and illustrative purposes. They should, however, be used with
7531  * caution as the C language standard provides no guarantees about the alignment or
7532  * atomicity of device memory accesses. The recommended practice for coding device
7533  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7534  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7535  * alt_write_dword() functions for 64 bit registers.
7536  *
7537  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR3.
7538  */
7539 struct ALT_GIC_DIST_GICD_IPRIORITYR3_s
7540 {
7541  volatile uint32_t fld : 32; /* Empty */
7542 };
7543 
7544 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR3. */
7545 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR3_s ALT_GIC_DIST_GICD_IPRIORITYR3_t;
7546 #endif /* __ASSEMBLY__ */
7547 
7548 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR3 register. */
7549 #define ALT_GIC_DIST_GICD_IPRIORITYR3_RESET 0x00000000
7550 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR3 register from the beginning of the component. */
7551 #define ALT_GIC_DIST_GICD_IPRIORITYR3_OFST 0x40c
7552 
7553 /*
7554  * Register : GICD_IPRIORITYR4
7555  *
7556  * Interrupt Priority Registers
7557  *
7558  * Register Layout
7559  *
7560  * Bits | Access | Reset | Description
7561  * :-------|:-------|:------|:------------
7562  * [31:0] | RW | 0x0 | Empty
7563  *
7564  */
7565 /*
7566  * Field : Empty - fld
7567  *
7568  * Placeholder
7569  *
7570  * Field Access Macros:
7571  *
7572  */
7573 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR4_FLD register field. */
7574 #define ALT_GIC_DIST_GICD_IPRIORITYR4_FLD_LSB 0
7575 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR4_FLD register field. */
7576 #define ALT_GIC_DIST_GICD_IPRIORITYR4_FLD_MSB 31
7577 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR4_FLD register field. */
7578 #define ALT_GIC_DIST_GICD_IPRIORITYR4_FLD_WIDTH 32
7579 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR4_FLD register field value. */
7580 #define ALT_GIC_DIST_GICD_IPRIORITYR4_FLD_SET_MSK 0xffffffff
7581 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR4_FLD register field value. */
7582 #define ALT_GIC_DIST_GICD_IPRIORITYR4_FLD_CLR_MSK 0x00000000
7583 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR4_FLD register field. */
7584 #define ALT_GIC_DIST_GICD_IPRIORITYR4_FLD_RESET 0x0
7585 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR4_FLD field value from a register. */
7586 #define ALT_GIC_DIST_GICD_IPRIORITYR4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7587 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR4_FLD register field value suitable for setting the register. */
7588 #define ALT_GIC_DIST_GICD_IPRIORITYR4_FLD_SET(value) (((value) << 0) & 0xffffffff)
7589 
7590 #ifndef __ASSEMBLY__
7591 /*
7592  * WARNING: The C register and register group struct declarations are provided for
7593  * convenience and illustrative purposes. They should, however, be used with
7594  * caution as the C language standard provides no guarantees about the alignment or
7595  * atomicity of device memory accesses. The recommended practice for coding device
7596  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7597  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7598  * alt_write_dword() functions for 64 bit registers.
7599  *
7600  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR4.
7601  */
7602 struct ALT_GIC_DIST_GICD_IPRIORITYR4_s
7603 {
7604  volatile uint32_t fld : 32; /* Empty */
7605 };
7606 
7607 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR4. */
7608 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR4_s ALT_GIC_DIST_GICD_IPRIORITYR4_t;
7609 #endif /* __ASSEMBLY__ */
7610 
7611 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR4 register. */
7612 #define ALT_GIC_DIST_GICD_IPRIORITYR4_RESET 0x00000000
7613 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR4 register from the beginning of the component. */
7614 #define ALT_GIC_DIST_GICD_IPRIORITYR4_OFST 0x410
7615 
7616 /*
7617  * Register : GICD_IPRIORITYR5
7618  *
7619  * Interrupt Priority Registers
7620  *
7621  * Register Layout
7622  *
7623  * Bits | Access | Reset | Description
7624  * :-------|:-------|:------|:------------
7625  * [31:0] | RW | 0x0 | Empty
7626  *
7627  */
7628 /*
7629  * Field : Empty - fld
7630  *
7631  * Placeholder
7632  *
7633  * Field Access Macros:
7634  *
7635  */
7636 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR5_FLD register field. */
7637 #define ALT_GIC_DIST_GICD_IPRIORITYR5_FLD_LSB 0
7638 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR5_FLD register field. */
7639 #define ALT_GIC_DIST_GICD_IPRIORITYR5_FLD_MSB 31
7640 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR5_FLD register field. */
7641 #define ALT_GIC_DIST_GICD_IPRIORITYR5_FLD_WIDTH 32
7642 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR5_FLD register field value. */
7643 #define ALT_GIC_DIST_GICD_IPRIORITYR5_FLD_SET_MSK 0xffffffff
7644 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR5_FLD register field value. */
7645 #define ALT_GIC_DIST_GICD_IPRIORITYR5_FLD_CLR_MSK 0x00000000
7646 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR5_FLD register field. */
7647 #define ALT_GIC_DIST_GICD_IPRIORITYR5_FLD_RESET 0x0
7648 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR5_FLD field value from a register. */
7649 #define ALT_GIC_DIST_GICD_IPRIORITYR5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7650 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR5_FLD register field value suitable for setting the register. */
7651 #define ALT_GIC_DIST_GICD_IPRIORITYR5_FLD_SET(value) (((value) << 0) & 0xffffffff)
7652 
7653 #ifndef __ASSEMBLY__
7654 /*
7655  * WARNING: The C register and register group struct declarations are provided for
7656  * convenience and illustrative purposes. They should, however, be used with
7657  * caution as the C language standard provides no guarantees about the alignment or
7658  * atomicity of device memory accesses. The recommended practice for coding device
7659  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7660  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7661  * alt_write_dword() functions for 64 bit registers.
7662  *
7663  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR5.
7664  */
7665 struct ALT_GIC_DIST_GICD_IPRIORITYR5_s
7666 {
7667  volatile uint32_t fld : 32; /* Empty */
7668 };
7669 
7670 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR5. */
7671 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR5_s ALT_GIC_DIST_GICD_IPRIORITYR5_t;
7672 #endif /* __ASSEMBLY__ */
7673 
7674 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR5 register. */
7675 #define ALT_GIC_DIST_GICD_IPRIORITYR5_RESET 0x00000000
7676 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR5 register from the beginning of the component. */
7677 #define ALT_GIC_DIST_GICD_IPRIORITYR5_OFST 0x414
7678 
7679 /*
7680  * Register : GICD_IPRIORITYR6
7681  *
7682  * Interrupt Priority Registers
7683  *
7684  * Register Layout
7685  *
7686  * Bits | Access | Reset | Description
7687  * :-------|:-------|:------|:------------
7688  * [31:0] | RW | 0x0 | Empty
7689  *
7690  */
7691 /*
7692  * Field : Empty - fld
7693  *
7694  * Placeholder
7695  *
7696  * Field Access Macros:
7697  *
7698  */
7699 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR6_FLD register field. */
7700 #define ALT_GIC_DIST_GICD_IPRIORITYR6_FLD_LSB 0
7701 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR6_FLD register field. */
7702 #define ALT_GIC_DIST_GICD_IPRIORITYR6_FLD_MSB 31
7703 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR6_FLD register field. */
7704 #define ALT_GIC_DIST_GICD_IPRIORITYR6_FLD_WIDTH 32
7705 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR6_FLD register field value. */
7706 #define ALT_GIC_DIST_GICD_IPRIORITYR6_FLD_SET_MSK 0xffffffff
7707 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR6_FLD register field value. */
7708 #define ALT_GIC_DIST_GICD_IPRIORITYR6_FLD_CLR_MSK 0x00000000
7709 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR6_FLD register field. */
7710 #define ALT_GIC_DIST_GICD_IPRIORITYR6_FLD_RESET 0x0
7711 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR6_FLD field value from a register. */
7712 #define ALT_GIC_DIST_GICD_IPRIORITYR6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7713 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR6_FLD register field value suitable for setting the register. */
7714 #define ALT_GIC_DIST_GICD_IPRIORITYR6_FLD_SET(value) (((value) << 0) & 0xffffffff)
7715 
7716 #ifndef __ASSEMBLY__
7717 /*
7718  * WARNING: The C register and register group struct declarations are provided for
7719  * convenience and illustrative purposes. They should, however, be used with
7720  * caution as the C language standard provides no guarantees about the alignment or
7721  * atomicity of device memory accesses. The recommended practice for coding device
7722  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7723  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7724  * alt_write_dword() functions for 64 bit registers.
7725  *
7726  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR6.
7727  */
7728 struct ALT_GIC_DIST_GICD_IPRIORITYR6_s
7729 {
7730  volatile uint32_t fld : 32; /* Empty */
7731 };
7732 
7733 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR6. */
7734 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR6_s ALT_GIC_DIST_GICD_IPRIORITYR6_t;
7735 #endif /* __ASSEMBLY__ */
7736 
7737 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR6 register. */
7738 #define ALT_GIC_DIST_GICD_IPRIORITYR6_RESET 0x00000000
7739 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR6 register from the beginning of the component. */
7740 #define ALT_GIC_DIST_GICD_IPRIORITYR6_OFST 0x418
7741 
7742 /*
7743  * Register : GICD_IPRIORITYR7
7744  *
7745  * Interrupt Priority Registers
7746  *
7747  * Register Layout
7748  *
7749  * Bits | Access | Reset | Description
7750  * :-------|:-------|:------|:------------
7751  * [31:0] | RW | 0x0 | Empty
7752  *
7753  */
7754 /*
7755  * Field : Empty - fld
7756  *
7757  * Placeholder
7758  *
7759  * Field Access Macros:
7760  *
7761  */
7762 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR7_FLD register field. */
7763 #define ALT_GIC_DIST_GICD_IPRIORITYR7_FLD_LSB 0
7764 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR7_FLD register field. */
7765 #define ALT_GIC_DIST_GICD_IPRIORITYR7_FLD_MSB 31
7766 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR7_FLD register field. */
7767 #define ALT_GIC_DIST_GICD_IPRIORITYR7_FLD_WIDTH 32
7768 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR7_FLD register field value. */
7769 #define ALT_GIC_DIST_GICD_IPRIORITYR7_FLD_SET_MSK 0xffffffff
7770 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR7_FLD register field value. */
7771 #define ALT_GIC_DIST_GICD_IPRIORITYR7_FLD_CLR_MSK 0x00000000
7772 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR7_FLD register field. */
7773 #define ALT_GIC_DIST_GICD_IPRIORITYR7_FLD_RESET 0x0
7774 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR7_FLD field value from a register. */
7775 #define ALT_GIC_DIST_GICD_IPRIORITYR7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7776 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR7_FLD register field value suitable for setting the register. */
7777 #define ALT_GIC_DIST_GICD_IPRIORITYR7_FLD_SET(value) (((value) << 0) & 0xffffffff)
7778 
7779 #ifndef __ASSEMBLY__
7780 /*
7781  * WARNING: The C register and register group struct declarations are provided for
7782  * convenience and illustrative purposes. They should, however, be used with
7783  * caution as the C language standard provides no guarantees about the alignment or
7784  * atomicity of device memory accesses. The recommended practice for coding device
7785  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7786  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7787  * alt_write_dword() functions for 64 bit registers.
7788  *
7789  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR7.
7790  */
7791 struct ALT_GIC_DIST_GICD_IPRIORITYR7_s
7792 {
7793  volatile uint32_t fld : 32; /* Empty */
7794 };
7795 
7796 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR7. */
7797 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR7_s ALT_GIC_DIST_GICD_IPRIORITYR7_t;
7798 #endif /* __ASSEMBLY__ */
7799 
7800 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR7 register. */
7801 #define ALT_GIC_DIST_GICD_IPRIORITYR7_RESET 0x00000000
7802 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR7 register from the beginning of the component. */
7803 #define ALT_GIC_DIST_GICD_IPRIORITYR7_OFST 0x41c
7804 
7805 /*
7806  * Register : GICD_IPRIORITYR8
7807  *
7808  * Interrupt Priority Registers
7809  *
7810  * Register Layout
7811  *
7812  * Bits | Access | Reset | Description
7813  * :-------|:-------|:------|:------------
7814  * [31:0] | RW | 0x0 | Empty
7815  *
7816  */
7817 /*
7818  * Field : Empty - fld
7819  *
7820  * Placeholder
7821  *
7822  * Field Access Macros:
7823  *
7824  */
7825 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR8_FLD register field. */
7826 #define ALT_GIC_DIST_GICD_IPRIORITYR8_FLD_LSB 0
7827 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR8_FLD register field. */
7828 #define ALT_GIC_DIST_GICD_IPRIORITYR8_FLD_MSB 31
7829 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR8_FLD register field. */
7830 #define ALT_GIC_DIST_GICD_IPRIORITYR8_FLD_WIDTH 32
7831 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR8_FLD register field value. */
7832 #define ALT_GIC_DIST_GICD_IPRIORITYR8_FLD_SET_MSK 0xffffffff
7833 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR8_FLD register field value. */
7834 #define ALT_GIC_DIST_GICD_IPRIORITYR8_FLD_CLR_MSK 0x00000000
7835 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR8_FLD register field. */
7836 #define ALT_GIC_DIST_GICD_IPRIORITYR8_FLD_RESET 0x0
7837 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR8_FLD field value from a register. */
7838 #define ALT_GIC_DIST_GICD_IPRIORITYR8_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7839 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR8_FLD register field value suitable for setting the register. */
7840 #define ALT_GIC_DIST_GICD_IPRIORITYR8_FLD_SET(value) (((value) << 0) & 0xffffffff)
7841 
7842 #ifndef __ASSEMBLY__
7843 /*
7844  * WARNING: The C register and register group struct declarations are provided for
7845  * convenience and illustrative purposes. They should, however, be used with
7846  * caution as the C language standard provides no guarantees about the alignment or
7847  * atomicity of device memory accesses. The recommended practice for coding device
7848  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7849  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7850  * alt_write_dword() functions for 64 bit registers.
7851  *
7852  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR8.
7853  */
7854 struct ALT_GIC_DIST_GICD_IPRIORITYR8_s
7855 {
7856  volatile uint32_t fld : 32; /* Empty */
7857 };
7858 
7859 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR8. */
7860 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR8_s ALT_GIC_DIST_GICD_IPRIORITYR8_t;
7861 #endif /* __ASSEMBLY__ */
7862 
7863 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR8 register. */
7864 #define ALT_GIC_DIST_GICD_IPRIORITYR8_RESET 0x00000000
7865 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR8 register from the beginning of the component. */
7866 #define ALT_GIC_DIST_GICD_IPRIORITYR8_OFST 0x420
7867 
7868 /*
7869  * Register : GICD_IPRIORITYR9
7870  *
7871  * Interrupt Priority Registers
7872  *
7873  * Register Layout
7874  *
7875  * Bits | Access | Reset | Description
7876  * :-------|:-------|:------|:------------
7877  * [31:0] | RW | 0x0 | Empty
7878  *
7879  */
7880 /*
7881  * Field : Empty - fld
7882  *
7883  * Placeholder
7884  *
7885  * Field Access Macros:
7886  *
7887  */
7888 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR9_FLD register field. */
7889 #define ALT_GIC_DIST_GICD_IPRIORITYR9_FLD_LSB 0
7890 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR9_FLD register field. */
7891 #define ALT_GIC_DIST_GICD_IPRIORITYR9_FLD_MSB 31
7892 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR9_FLD register field. */
7893 #define ALT_GIC_DIST_GICD_IPRIORITYR9_FLD_WIDTH 32
7894 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR9_FLD register field value. */
7895 #define ALT_GIC_DIST_GICD_IPRIORITYR9_FLD_SET_MSK 0xffffffff
7896 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR9_FLD register field value. */
7897 #define ALT_GIC_DIST_GICD_IPRIORITYR9_FLD_CLR_MSK 0x00000000
7898 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR9_FLD register field. */
7899 #define ALT_GIC_DIST_GICD_IPRIORITYR9_FLD_RESET 0x0
7900 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR9_FLD field value from a register. */
7901 #define ALT_GIC_DIST_GICD_IPRIORITYR9_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7902 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR9_FLD register field value suitable for setting the register. */
7903 #define ALT_GIC_DIST_GICD_IPRIORITYR9_FLD_SET(value) (((value) << 0) & 0xffffffff)
7904 
7905 #ifndef __ASSEMBLY__
7906 /*
7907  * WARNING: The C register and register group struct declarations are provided for
7908  * convenience and illustrative purposes. They should, however, be used with
7909  * caution as the C language standard provides no guarantees about the alignment or
7910  * atomicity of device memory accesses. The recommended practice for coding device
7911  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7912  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7913  * alt_write_dword() functions for 64 bit registers.
7914  *
7915  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR9.
7916  */
7917 struct ALT_GIC_DIST_GICD_IPRIORITYR9_s
7918 {
7919  volatile uint32_t fld : 32; /* Empty */
7920 };
7921 
7922 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR9. */
7923 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR9_s ALT_GIC_DIST_GICD_IPRIORITYR9_t;
7924 #endif /* __ASSEMBLY__ */
7925 
7926 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR9 register. */
7927 #define ALT_GIC_DIST_GICD_IPRIORITYR9_RESET 0x00000000
7928 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR9 register from the beginning of the component. */
7929 #define ALT_GIC_DIST_GICD_IPRIORITYR9_OFST 0x424
7930 
7931 /*
7932  * Register : GICD_IPRIORITYR10
7933  *
7934  * Interrupt Priority Registers
7935  *
7936  * Register Layout
7937  *
7938  * Bits | Access | Reset | Description
7939  * :-------|:-------|:------|:------------
7940  * [31:0] | RW | 0x0 | Empty
7941  *
7942  */
7943 /*
7944  * Field : Empty - fld
7945  *
7946  * Placeholder
7947  *
7948  * Field Access Macros:
7949  *
7950  */
7951 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR10_FLD register field. */
7952 #define ALT_GIC_DIST_GICD_IPRIORITYR10_FLD_LSB 0
7953 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR10_FLD register field. */
7954 #define ALT_GIC_DIST_GICD_IPRIORITYR10_FLD_MSB 31
7955 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR10_FLD register field. */
7956 #define ALT_GIC_DIST_GICD_IPRIORITYR10_FLD_WIDTH 32
7957 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR10_FLD register field value. */
7958 #define ALT_GIC_DIST_GICD_IPRIORITYR10_FLD_SET_MSK 0xffffffff
7959 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR10_FLD register field value. */
7960 #define ALT_GIC_DIST_GICD_IPRIORITYR10_FLD_CLR_MSK 0x00000000
7961 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR10_FLD register field. */
7962 #define ALT_GIC_DIST_GICD_IPRIORITYR10_FLD_RESET 0x0
7963 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR10_FLD field value from a register. */
7964 #define ALT_GIC_DIST_GICD_IPRIORITYR10_FLD_GET(value) (((value) & 0xffffffff) >> 0)
7965 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR10_FLD register field value suitable for setting the register. */
7966 #define ALT_GIC_DIST_GICD_IPRIORITYR10_FLD_SET(value) (((value) << 0) & 0xffffffff)
7967 
7968 #ifndef __ASSEMBLY__
7969 /*
7970  * WARNING: The C register and register group struct declarations are provided for
7971  * convenience and illustrative purposes. They should, however, be used with
7972  * caution as the C language standard provides no guarantees about the alignment or
7973  * atomicity of device memory accesses. The recommended practice for coding device
7974  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7975  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7976  * alt_write_dword() functions for 64 bit registers.
7977  *
7978  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR10.
7979  */
7980 struct ALT_GIC_DIST_GICD_IPRIORITYR10_s
7981 {
7982  volatile uint32_t fld : 32; /* Empty */
7983 };
7984 
7985 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR10. */
7986 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR10_s ALT_GIC_DIST_GICD_IPRIORITYR10_t;
7987 #endif /* __ASSEMBLY__ */
7988 
7989 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR10 register. */
7990 #define ALT_GIC_DIST_GICD_IPRIORITYR10_RESET 0x00000000
7991 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR10 register from the beginning of the component. */
7992 #define ALT_GIC_DIST_GICD_IPRIORITYR10_OFST 0x428
7993 
7994 /*
7995  * Register : GICD_IPRIORITYR11
7996  *
7997  * Interrupt Priority Registers
7998  *
7999  * Register Layout
8000  *
8001  * Bits | Access | Reset | Description
8002  * :-------|:-------|:------|:------------
8003  * [31:0] | RW | 0x0 | Empty
8004  *
8005  */
8006 /*
8007  * Field : Empty - fld
8008  *
8009  * Placeholder
8010  *
8011  * Field Access Macros:
8012  *
8013  */
8014 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR11_FLD register field. */
8015 #define ALT_GIC_DIST_GICD_IPRIORITYR11_FLD_LSB 0
8016 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR11_FLD register field. */
8017 #define ALT_GIC_DIST_GICD_IPRIORITYR11_FLD_MSB 31
8018 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR11_FLD register field. */
8019 #define ALT_GIC_DIST_GICD_IPRIORITYR11_FLD_WIDTH 32
8020 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR11_FLD register field value. */
8021 #define ALT_GIC_DIST_GICD_IPRIORITYR11_FLD_SET_MSK 0xffffffff
8022 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR11_FLD register field value. */
8023 #define ALT_GIC_DIST_GICD_IPRIORITYR11_FLD_CLR_MSK 0x00000000
8024 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR11_FLD register field. */
8025 #define ALT_GIC_DIST_GICD_IPRIORITYR11_FLD_RESET 0x0
8026 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR11_FLD field value from a register. */
8027 #define ALT_GIC_DIST_GICD_IPRIORITYR11_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8028 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR11_FLD register field value suitable for setting the register. */
8029 #define ALT_GIC_DIST_GICD_IPRIORITYR11_FLD_SET(value) (((value) << 0) & 0xffffffff)
8030 
8031 #ifndef __ASSEMBLY__
8032 /*
8033  * WARNING: The C register and register group struct declarations are provided for
8034  * convenience and illustrative purposes. They should, however, be used with
8035  * caution as the C language standard provides no guarantees about the alignment or
8036  * atomicity of device memory accesses. The recommended practice for coding device
8037  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8038  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8039  * alt_write_dword() functions for 64 bit registers.
8040  *
8041  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR11.
8042  */
8043 struct ALT_GIC_DIST_GICD_IPRIORITYR11_s
8044 {
8045  volatile uint32_t fld : 32; /* Empty */
8046 };
8047 
8048 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR11. */
8049 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR11_s ALT_GIC_DIST_GICD_IPRIORITYR11_t;
8050 #endif /* __ASSEMBLY__ */
8051 
8052 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR11 register. */
8053 #define ALT_GIC_DIST_GICD_IPRIORITYR11_RESET 0x00000000
8054 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR11 register from the beginning of the component. */
8055 #define ALT_GIC_DIST_GICD_IPRIORITYR11_OFST 0x42c
8056 
8057 /*
8058  * Register : GICD_IPRIORITYR12
8059  *
8060  * Interrupt Priority Registers
8061  *
8062  * Register Layout
8063  *
8064  * Bits | Access | Reset | Description
8065  * :-------|:-------|:------|:------------
8066  * [31:0] | RW | 0x0 | Empty
8067  *
8068  */
8069 /*
8070  * Field : Empty - fld
8071  *
8072  * Placeholder
8073  *
8074  * Field Access Macros:
8075  *
8076  */
8077 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR12_FLD register field. */
8078 #define ALT_GIC_DIST_GICD_IPRIORITYR12_FLD_LSB 0
8079 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR12_FLD register field. */
8080 #define ALT_GIC_DIST_GICD_IPRIORITYR12_FLD_MSB 31
8081 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR12_FLD register field. */
8082 #define ALT_GIC_DIST_GICD_IPRIORITYR12_FLD_WIDTH 32
8083 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR12_FLD register field value. */
8084 #define ALT_GIC_DIST_GICD_IPRIORITYR12_FLD_SET_MSK 0xffffffff
8085 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR12_FLD register field value. */
8086 #define ALT_GIC_DIST_GICD_IPRIORITYR12_FLD_CLR_MSK 0x00000000
8087 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR12_FLD register field. */
8088 #define ALT_GIC_DIST_GICD_IPRIORITYR12_FLD_RESET 0x0
8089 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR12_FLD field value from a register. */
8090 #define ALT_GIC_DIST_GICD_IPRIORITYR12_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8091 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR12_FLD register field value suitable for setting the register. */
8092 #define ALT_GIC_DIST_GICD_IPRIORITYR12_FLD_SET(value) (((value) << 0) & 0xffffffff)
8093 
8094 #ifndef __ASSEMBLY__
8095 /*
8096  * WARNING: The C register and register group struct declarations are provided for
8097  * convenience and illustrative purposes. They should, however, be used with
8098  * caution as the C language standard provides no guarantees about the alignment or
8099  * atomicity of device memory accesses. The recommended practice for coding device
8100  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8101  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8102  * alt_write_dword() functions for 64 bit registers.
8103  *
8104  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR12.
8105  */
8106 struct ALT_GIC_DIST_GICD_IPRIORITYR12_s
8107 {
8108  volatile uint32_t fld : 32; /* Empty */
8109 };
8110 
8111 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR12. */
8112 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR12_s ALT_GIC_DIST_GICD_IPRIORITYR12_t;
8113 #endif /* __ASSEMBLY__ */
8114 
8115 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR12 register. */
8116 #define ALT_GIC_DIST_GICD_IPRIORITYR12_RESET 0x00000000
8117 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR12 register from the beginning of the component. */
8118 #define ALT_GIC_DIST_GICD_IPRIORITYR12_OFST 0x430
8119 
8120 /*
8121  * Register : GICD_IPRIORITYR13
8122  *
8123  * Interrupt Priority Registers
8124  *
8125  * Register Layout
8126  *
8127  * Bits | Access | Reset | Description
8128  * :-------|:-------|:------|:------------
8129  * [31:0] | RW | 0x0 | Empty
8130  *
8131  */
8132 /*
8133  * Field : Empty - fld
8134  *
8135  * Placeholder
8136  *
8137  * Field Access Macros:
8138  *
8139  */
8140 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR13_FLD register field. */
8141 #define ALT_GIC_DIST_GICD_IPRIORITYR13_FLD_LSB 0
8142 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR13_FLD register field. */
8143 #define ALT_GIC_DIST_GICD_IPRIORITYR13_FLD_MSB 31
8144 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR13_FLD register field. */
8145 #define ALT_GIC_DIST_GICD_IPRIORITYR13_FLD_WIDTH 32
8146 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR13_FLD register field value. */
8147 #define ALT_GIC_DIST_GICD_IPRIORITYR13_FLD_SET_MSK 0xffffffff
8148 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR13_FLD register field value. */
8149 #define ALT_GIC_DIST_GICD_IPRIORITYR13_FLD_CLR_MSK 0x00000000
8150 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR13_FLD register field. */
8151 #define ALT_GIC_DIST_GICD_IPRIORITYR13_FLD_RESET 0x0
8152 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR13_FLD field value from a register. */
8153 #define ALT_GIC_DIST_GICD_IPRIORITYR13_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8154 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR13_FLD register field value suitable for setting the register. */
8155 #define ALT_GIC_DIST_GICD_IPRIORITYR13_FLD_SET(value) (((value) << 0) & 0xffffffff)
8156 
8157 #ifndef __ASSEMBLY__
8158 /*
8159  * WARNING: The C register and register group struct declarations are provided for
8160  * convenience and illustrative purposes. They should, however, be used with
8161  * caution as the C language standard provides no guarantees about the alignment or
8162  * atomicity of device memory accesses. The recommended practice for coding device
8163  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8164  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8165  * alt_write_dword() functions for 64 bit registers.
8166  *
8167  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR13.
8168  */
8169 struct ALT_GIC_DIST_GICD_IPRIORITYR13_s
8170 {
8171  volatile uint32_t fld : 32; /* Empty */
8172 };
8173 
8174 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR13. */
8175 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR13_s ALT_GIC_DIST_GICD_IPRIORITYR13_t;
8176 #endif /* __ASSEMBLY__ */
8177 
8178 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR13 register. */
8179 #define ALT_GIC_DIST_GICD_IPRIORITYR13_RESET 0x00000000
8180 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR13 register from the beginning of the component. */
8181 #define ALT_GIC_DIST_GICD_IPRIORITYR13_OFST 0x434
8182 
8183 /*
8184  * Register : GICD_IPRIORITYR14
8185  *
8186  * Interrupt Priority Registers
8187  *
8188  * Register Layout
8189  *
8190  * Bits | Access | Reset | Description
8191  * :-------|:-------|:------|:------------
8192  * [31:0] | RW | 0x0 | Empty
8193  *
8194  */
8195 /*
8196  * Field : Empty - fld
8197  *
8198  * Placeholder
8199  *
8200  * Field Access Macros:
8201  *
8202  */
8203 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR14_FLD register field. */
8204 #define ALT_GIC_DIST_GICD_IPRIORITYR14_FLD_LSB 0
8205 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR14_FLD register field. */
8206 #define ALT_GIC_DIST_GICD_IPRIORITYR14_FLD_MSB 31
8207 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR14_FLD register field. */
8208 #define ALT_GIC_DIST_GICD_IPRIORITYR14_FLD_WIDTH 32
8209 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR14_FLD register field value. */
8210 #define ALT_GIC_DIST_GICD_IPRIORITYR14_FLD_SET_MSK 0xffffffff
8211 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR14_FLD register field value. */
8212 #define ALT_GIC_DIST_GICD_IPRIORITYR14_FLD_CLR_MSK 0x00000000
8213 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR14_FLD register field. */
8214 #define ALT_GIC_DIST_GICD_IPRIORITYR14_FLD_RESET 0x0
8215 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR14_FLD field value from a register. */
8216 #define ALT_GIC_DIST_GICD_IPRIORITYR14_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8217 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR14_FLD register field value suitable for setting the register. */
8218 #define ALT_GIC_DIST_GICD_IPRIORITYR14_FLD_SET(value) (((value) << 0) & 0xffffffff)
8219 
8220 #ifndef __ASSEMBLY__
8221 /*
8222  * WARNING: The C register and register group struct declarations are provided for
8223  * convenience and illustrative purposes. They should, however, be used with
8224  * caution as the C language standard provides no guarantees about the alignment or
8225  * atomicity of device memory accesses. The recommended practice for coding device
8226  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8227  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8228  * alt_write_dword() functions for 64 bit registers.
8229  *
8230  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR14.
8231  */
8232 struct ALT_GIC_DIST_GICD_IPRIORITYR14_s
8233 {
8234  volatile uint32_t fld : 32; /* Empty */
8235 };
8236 
8237 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR14. */
8238 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR14_s ALT_GIC_DIST_GICD_IPRIORITYR14_t;
8239 #endif /* __ASSEMBLY__ */
8240 
8241 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR14 register. */
8242 #define ALT_GIC_DIST_GICD_IPRIORITYR14_RESET 0x00000000
8243 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR14 register from the beginning of the component. */
8244 #define ALT_GIC_DIST_GICD_IPRIORITYR14_OFST 0x438
8245 
8246 /*
8247  * Register : GICD_IPRIORITYR15
8248  *
8249  * Interrupt Priority Registers
8250  *
8251  * Register Layout
8252  *
8253  * Bits | Access | Reset | Description
8254  * :-------|:-------|:------|:------------
8255  * [31:0] | RW | 0x0 | Empty
8256  *
8257  */
8258 /*
8259  * Field : Empty - fld
8260  *
8261  * Placeholder
8262  *
8263  * Field Access Macros:
8264  *
8265  */
8266 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR15_FLD register field. */
8267 #define ALT_GIC_DIST_GICD_IPRIORITYR15_FLD_LSB 0
8268 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR15_FLD register field. */
8269 #define ALT_GIC_DIST_GICD_IPRIORITYR15_FLD_MSB 31
8270 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR15_FLD register field. */
8271 #define ALT_GIC_DIST_GICD_IPRIORITYR15_FLD_WIDTH 32
8272 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR15_FLD register field value. */
8273 #define ALT_GIC_DIST_GICD_IPRIORITYR15_FLD_SET_MSK 0xffffffff
8274 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR15_FLD register field value. */
8275 #define ALT_GIC_DIST_GICD_IPRIORITYR15_FLD_CLR_MSK 0x00000000
8276 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR15_FLD register field. */
8277 #define ALT_GIC_DIST_GICD_IPRIORITYR15_FLD_RESET 0x0
8278 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR15_FLD field value from a register. */
8279 #define ALT_GIC_DIST_GICD_IPRIORITYR15_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8280 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR15_FLD register field value suitable for setting the register. */
8281 #define ALT_GIC_DIST_GICD_IPRIORITYR15_FLD_SET(value) (((value) << 0) & 0xffffffff)
8282 
8283 #ifndef __ASSEMBLY__
8284 /*
8285  * WARNING: The C register and register group struct declarations are provided for
8286  * convenience and illustrative purposes. They should, however, be used with
8287  * caution as the C language standard provides no guarantees about the alignment or
8288  * atomicity of device memory accesses. The recommended practice for coding device
8289  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8290  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8291  * alt_write_dword() functions for 64 bit registers.
8292  *
8293  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR15.
8294  */
8295 struct ALT_GIC_DIST_GICD_IPRIORITYR15_s
8296 {
8297  volatile uint32_t fld : 32; /* Empty */
8298 };
8299 
8300 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR15. */
8301 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR15_s ALT_GIC_DIST_GICD_IPRIORITYR15_t;
8302 #endif /* __ASSEMBLY__ */
8303 
8304 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR15 register. */
8305 #define ALT_GIC_DIST_GICD_IPRIORITYR15_RESET 0x00000000
8306 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR15 register from the beginning of the component. */
8307 #define ALT_GIC_DIST_GICD_IPRIORITYR15_OFST 0x43c
8308 
8309 /*
8310  * Register : GICD_IPRIORITYR16
8311  *
8312  * Interrupt Priority Registers
8313  *
8314  * Register Layout
8315  *
8316  * Bits | Access | Reset | Description
8317  * :-------|:-------|:------|:------------
8318  * [31:0] | RW | 0x0 | Empty
8319  *
8320  */
8321 /*
8322  * Field : Empty - fld
8323  *
8324  * Placeholder
8325  *
8326  * Field Access Macros:
8327  *
8328  */
8329 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR16_FLD register field. */
8330 #define ALT_GIC_DIST_GICD_IPRIORITYR16_FLD_LSB 0
8331 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR16_FLD register field. */
8332 #define ALT_GIC_DIST_GICD_IPRIORITYR16_FLD_MSB 31
8333 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR16_FLD register field. */
8334 #define ALT_GIC_DIST_GICD_IPRIORITYR16_FLD_WIDTH 32
8335 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR16_FLD register field value. */
8336 #define ALT_GIC_DIST_GICD_IPRIORITYR16_FLD_SET_MSK 0xffffffff
8337 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR16_FLD register field value. */
8338 #define ALT_GIC_DIST_GICD_IPRIORITYR16_FLD_CLR_MSK 0x00000000
8339 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR16_FLD register field. */
8340 #define ALT_GIC_DIST_GICD_IPRIORITYR16_FLD_RESET 0x0
8341 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR16_FLD field value from a register. */
8342 #define ALT_GIC_DIST_GICD_IPRIORITYR16_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8343 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR16_FLD register field value suitable for setting the register. */
8344 #define ALT_GIC_DIST_GICD_IPRIORITYR16_FLD_SET(value) (((value) << 0) & 0xffffffff)
8345 
8346 #ifndef __ASSEMBLY__
8347 /*
8348  * WARNING: The C register and register group struct declarations are provided for
8349  * convenience and illustrative purposes. They should, however, be used with
8350  * caution as the C language standard provides no guarantees about the alignment or
8351  * atomicity of device memory accesses. The recommended practice for coding device
8352  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8353  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8354  * alt_write_dword() functions for 64 bit registers.
8355  *
8356  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR16.
8357  */
8358 struct ALT_GIC_DIST_GICD_IPRIORITYR16_s
8359 {
8360  volatile uint32_t fld : 32; /* Empty */
8361 };
8362 
8363 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR16. */
8364 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR16_s ALT_GIC_DIST_GICD_IPRIORITYR16_t;
8365 #endif /* __ASSEMBLY__ */
8366 
8367 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR16 register. */
8368 #define ALT_GIC_DIST_GICD_IPRIORITYR16_RESET 0x00000000
8369 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR16 register from the beginning of the component. */
8370 #define ALT_GIC_DIST_GICD_IPRIORITYR16_OFST 0x440
8371 
8372 /*
8373  * Register : GICD_IPRIORITYR17
8374  *
8375  * Interrupt Priority Registers
8376  *
8377  * Register Layout
8378  *
8379  * Bits | Access | Reset | Description
8380  * :-------|:-------|:------|:------------
8381  * [31:0] | RW | 0x0 | Empty
8382  *
8383  */
8384 /*
8385  * Field : Empty - fld
8386  *
8387  * Placeholder
8388  *
8389  * Field Access Macros:
8390  *
8391  */
8392 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR17_FLD register field. */
8393 #define ALT_GIC_DIST_GICD_IPRIORITYR17_FLD_LSB 0
8394 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR17_FLD register field. */
8395 #define ALT_GIC_DIST_GICD_IPRIORITYR17_FLD_MSB 31
8396 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR17_FLD register field. */
8397 #define ALT_GIC_DIST_GICD_IPRIORITYR17_FLD_WIDTH 32
8398 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR17_FLD register field value. */
8399 #define ALT_GIC_DIST_GICD_IPRIORITYR17_FLD_SET_MSK 0xffffffff
8400 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR17_FLD register field value. */
8401 #define ALT_GIC_DIST_GICD_IPRIORITYR17_FLD_CLR_MSK 0x00000000
8402 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR17_FLD register field. */
8403 #define ALT_GIC_DIST_GICD_IPRIORITYR17_FLD_RESET 0x0
8404 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR17_FLD field value from a register. */
8405 #define ALT_GIC_DIST_GICD_IPRIORITYR17_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8406 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR17_FLD register field value suitable for setting the register. */
8407 #define ALT_GIC_DIST_GICD_IPRIORITYR17_FLD_SET(value) (((value) << 0) & 0xffffffff)
8408 
8409 #ifndef __ASSEMBLY__
8410 /*
8411  * WARNING: The C register and register group struct declarations are provided for
8412  * convenience and illustrative purposes. They should, however, be used with
8413  * caution as the C language standard provides no guarantees about the alignment or
8414  * atomicity of device memory accesses. The recommended practice for coding device
8415  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8416  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8417  * alt_write_dword() functions for 64 bit registers.
8418  *
8419  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR17.
8420  */
8421 struct ALT_GIC_DIST_GICD_IPRIORITYR17_s
8422 {
8423  volatile uint32_t fld : 32; /* Empty */
8424 };
8425 
8426 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR17. */
8427 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR17_s ALT_GIC_DIST_GICD_IPRIORITYR17_t;
8428 #endif /* __ASSEMBLY__ */
8429 
8430 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR17 register. */
8431 #define ALT_GIC_DIST_GICD_IPRIORITYR17_RESET 0x00000000
8432 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR17 register from the beginning of the component. */
8433 #define ALT_GIC_DIST_GICD_IPRIORITYR17_OFST 0x444
8434 
8435 /*
8436  * Register : GICD_IPRIORITYR18
8437  *
8438  * Interrupt Priority Registers
8439  *
8440  * Register Layout
8441  *
8442  * Bits | Access | Reset | Description
8443  * :-------|:-------|:------|:------------
8444  * [31:0] | RW | 0x0 | Empty
8445  *
8446  */
8447 /*
8448  * Field : Empty - fld
8449  *
8450  * Placeholder
8451  *
8452  * Field Access Macros:
8453  *
8454  */
8455 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR18_FLD register field. */
8456 #define ALT_GIC_DIST_GICD_IPRIORITYR18_FLD_LSB 0
8457 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR18_FLD register field. */
8458 #define ALT_GIC_DIST_GICD_IPRIORITYR18_FLD_MSB 31
8459 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR18_FLD register field. */
8460 #define ALT_GIC_DIST_GICD_IPRIORITYR18_FLD_WIDTH 32
8461 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR18_FLD register field value. */
8462 #define ALT_GIC_DIST_GICD_IPRIORITYR18_FLD_SET_MSK 0xffffffff
8463 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR18_FLD register field value. */
8464 #define ALT_GIC_DIST_GICD_IPRIORITYR18_FLD_CLR_MSK 0x00000000
8465 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR18_FLD register field. */
8466 #define ALT_GIC_DIST_GICD_IPRIORITYR18_FLD_RESET 0x0
8467 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR18_FLD field value from a register. */
8468 #define ALT_GIC_DIST_GICD_IPRIORITYR18_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8469 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR18_FLD register field value suitable for setting the register. */
8470 #define ALT_GIC_DIST_GICD_IPRIORITYR18_FLD_SET(value) (((value) << 0) & 0xffffffff)
8471 
8472 #ifndef __ASSEMBLY__
8473 /*
8474  * WARNING: The C register and register group struct declarations are provided for
8475  * convenience and illustrative purposes. They should, however, be used with
8476  * caution as the C language standard provides no guarantees about the alignment or
8477  * atomicity of device memory accesses. The recommended practice for coding device
8478  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8479  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8480  * alt_write_dword() functions for 64 bit registers.
8481  *
8482  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR18.
8483  */
8484 struct ALT_GIC_DIST_GICD_IPRIORITYR18_s
8485 {
8486  volatile uint32_t fld : 32; /* Empty */
8487 };
8488 
8489 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR18. */
8490 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR18_s ALT_GIC_DIST_GICD_IPRIORITYR18_t;
8491 #endif /* __ASSEMBLY__ */
8492 
8493 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR18 register. */
8494 #define ALT_GIC_DIST_GICD_IPRIORITYR18_RESET 0x00000000
8495 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR18 register from the beginning of the component. */
8496 #define ALT_GIC_DIST_GICD_IPRIORITYR18_OFST 0x448
8497 
8498 /*
8499  * Register : GICD_IPRIORITYR19
8500  *
8501  * Interrupt Priority Registers
8502  *
8503  * Register Layout
8504  *
8505  * Bits | Access | Reset | Description
8506  * :-------|:-------|:------|:------------
8507  * [31:0] | RW | 0x0 | Empty
8508  *
8509  */
8510 /*
8511  * Field : Empty - fld
8512  *
8513  * Placeholder
8514  *
8515  * Field Access Macros:
8516  *
8517  */
8518 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR19_FLD register field. */
8519 #define ALT_GIC_DIST_GICD_IPRIORITYR19_FLD_LSB 0
8520 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR19_FLD register field. */
8521 #define ALT_GIC_DIST_GICD_IPRIORITYR19_FLD_MSB 31
8522 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR19_FLD register field. */
8523 #define ALT_GIC_DIST_GICD_IPRIORITYR19_FLD_WIDTH 32
8524 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR19_FLD register field value. */
8525 #define ALT_GIC_DIST_GICD_IPRIORITYR19_FLD_SET_MSK 0xffffffff
8526 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR19_FLD register field value. */
8527 #define ALT_GIC_DIST_GICD_IPRIORITYR19_FLD_CLR_MSK 0x00000000
8528 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR19_FLD register field. */
8529 #define ALT_GIC_DIST_GICD_IPRIORITYR19_FLD_RESET 0x0
8530 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR19_FLD field value from a register. */
8531 #define ALT_GIC_DIST_GICD_IPRIORITYR19_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8532 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR19_FLD register field value suitable for setting the register. */
8533 #define ALT_GIC_DIST_GICD_IPRIORITYR19_FLD_SET(value) (((value) << 0) & 0xffffffff)
8534 
8535 #ifndef __ASSEMBLY__
8536 /*
8537  * WARNING: The C register and register group struct declarations are provided for
8538  * convenience and illustrative purposes. They should, however, be used with
8539  * caution as the C language standard provides no guarantees about the alignment or
8540  * atomicity of device memory accesses. The recommended practice for coding device
8541  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8542  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8543  * alt_write_dword() functions for 64 bit registers.
8544  *
8545  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR19.
8546  */
8547 struct ALT_GIC_DIST_GICD_IPRIORITYR19_s
8548 {
8549  volatile uint32_t fld : 32; /* Empty */
8550 };
8551 
8552 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR19. */
8553 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR19_s ALT_GIC_DIST_GICD_IPRIORITYR19_t;
8554 #endif /* __ASSEMBLY__ */
8555 
8556 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR19 register. */
8557 #define ALT_GIC_DIST_GICD_IPRIORITYR19_RESET 0x00000000
8558 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR19 register from the beginning of the component. */
8559 #define ALT_GIC_DIST_GICD_IPRIORITYR19_OFST 0x44c
8560 
8561 /*
8562  * Register : GICD_IPRIORITYR20
8563  *
8564  * Interrupt Priority Registers
8565  *
8566  * Register Layout
8567  *
8568  * Bits | Access | Reset | Description
8569  * :-------|:-------|:------|:------------
8570  * [31:0] | RW | 0x0 | Empty
8571  *
8572  */
8573 /*
8574  * Field : Empty - fld
8575  *
8576  * Placeholder
8577  *
8578  * Field Access Macros:
8579  *
8580  */
8581 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR20_FLD register field. */
8582 #define ALT_GIC_DIST_GICD_IPRIORITYR20_FLD_LSB 0
8583 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR20_FLD register field. */
8584 #define ALT_GIC_DIST_GICD_IPRIORITYR20_FLD_MSB 31
8585 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR20_FLD register field. */
8586 #define ALT_GIC_DIST_GICD_IPRIORITYR20_FLD_WIDTH 32
8587 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR20_FLD register field value. */
8588 #define ALT_GIC_DIST_GICD_IPRIORITYR20_FLD_SET_MSK 0xffffffff
8589 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR20_FLD register field value. */
8590 #define ALT_GIC_DIST_GICD_IPRIORITYR20_FLD_CLR_MSK 0x00000000
8591 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR20_FLD register field. */
8592 #define ALT_GIC_DIST_GICD_IPRIORITYR20_FLD_RESET 0x0
8593 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR20_FLD field value from a register. */
8594 #define ALT_GIC_DIST_GICD_IPRIORITYR20_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8595 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR20_FLD register field value suitable for setting the register. */
8596 #define ALT_GIC_DIST_GICD_IPRIORITYR20_FLD_SET(value) (((value) << 0) & 0xffffffff)
8597 
8598 #ifndef __ASSEMBLY__
8599 /*
8600  * WARNING: The C register and register group struct declarations are provided for
8601  * convenience and illustrative purposes. They should, however, be used with
8602  * caution as the C language standard provides no guarantees about the alignment or
8603  * atomicity of device memory accesses. The recommended practice for coding device
8604  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8605  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8606  * alt_write_dword() functions for 64 bit registers.
8607  *
8608  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR20.
8609  */
8610 struct ALT_GIC_DIST_GICD_IPRIORITYR20_s
8611 {
8612  volatile uint32_t fld : 32; /* Empty */
8613 };
8614 
8615 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR20. */
8616 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR20_s ALT_GIC_DIST_GICD_IPRIORITYR20_t;
8617 #endif /* __ASSEMBLY__ */
8618 
8619 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR20 register. */
8620 #define ALT_GIC_DIST_GICD_IPRIORITYR20_RESET 0x00000000
8621 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR20 register from the beginning of the component. */
8622 #define ALT_GIC_DIST_GICD_IPRIORITYR20_OFST 0x450
8623 
8624 /*
8625  * Register : GICD_IPRIORITYR21
8626  *
8627  * Interrupt Priority Registers
8628  *
8629  * Register Layout
8630  *
8631  * Bits | Access | Reset | Description
8632  * :-------|:-------|:------|:------------
8633  * [31:0] | RW | 0x0 | Empty
8634  *
8635  */
8636 /*
8637  * Field : Empty - fld
8638  *
8639  * Placeholder
8640  *
8641  * Field Access Macros:
8642  *
8643  */
8644 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR21_FLD register field. */
8645 #define ALT_GIC_DIST_GICD_IPRIORITYR21_FLD_LSB 0
8646 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR21_FLD register field. */
8647 #define ALT_GIC_DIST_GICD_IPRIORITYR21_FLD_MSB 31
8648 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR21_FLD register field. */
8649 #define ALT_GIC_DIST_GICD_IPRIORITYR21_FLD_WIDTH 32
8650 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR21_FLD register field value. */
8651 #define ALT_GIC_DIST_GICD_IPRIORITYR21_FLD_SET_MSK 0xffffffff
8652 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR21_FLD register field value. */
8653 #define ALT_GIC_DIST_GICD_IPRIORITYR21_FLD_CLR_MSK 0x00000000
8654 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR21_FLD register field. */
8655 #define ALT_GIC_DIST_GICD_IPRIORITYR21_FLD_RESET 0x0
8656 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR21_FLD field value from a register. */
8657 #define ALT_GIC_DIST_GICD_IPRIORITYR21_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8658 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR21_FLD register field value suitable for setting the register. */
8659 #define ALT_GIC_DIST_GICD_IPRIORITYR21_FLD_SET(value) (((value) << 0) & 0xffffffff)
8660 
8661 #ifndef __ASSEMBLY__
8662 /*
8663  * WARNING: The C register and register group struct declarations are provided for
8664  * convenience and illustrative purposes. They should, however, be used with
8665  * caution as the C language standard provides no guarantees about the alignment or
8666  * atomicity of device memory accesses. The recommended practice for coding device
8667  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8668  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8669  * alt_write_dword() functions for 64 bit registers.
8670  *
8671  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR21.
8672  */
8673 struct ALT_GIC_DIST_GICD_IPRIORITYR21_s
8674 {
8675  volatile uint32_t fld : 32; /* Empty */
8676 };
8677 
8678 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR21. */
8679 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR21_s ALT_GIC_DIST_GICD_IPRIORITYR21_t;
8680 #endif /* __ASSEMBLY__ */
8681 
8682 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR21 register. */
8683 #define ALT_GIC_DIST_GICD_IPRIORITYR21_RESET 0x00000000
8684 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR21 register from the beginning of the component. */
8685 #define ALT_GIC_DIST_GICD_IPRIORITYR21_OFST 0x454
8686 
8687 /*
8688  * Register : GICD_IPRIORITYR22
8689  *
8690  * Interrupt Priority Registers
8691  *
8692  * Register Layout
8693  *
8694  * Bits | Access | Reset | Description
8695  * :-------|:-------|:------|:------------
8696  * [31:0] | RW | 0x0 | Empty
8697  *
8698  */
8699 /*
8700  * Field : Empty - fld
8701  *
8702  * Placeholder
8703  *
8704  * Field Access Macros:
8705  *
8706  */
8707 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR22_FLD register field. */
8708 #define ALT_GIC_DIST_GICD_IPRIORITYR22_FLD_LSB 0
8709 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR22_FLD register field. */
8710 #define ALT_GIC_DIST_GICD_IPRIORITYR22_FLD_MSB 31
8711 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR22_FLD register field. */
8712 #define ALT_GIC_DIST_GICD_IPRIORITYR22_FLD_WIDTH 32
8713 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR22_FLD register field value. */
8714 #define ALT_GIC_DIST_GICD_IPRIORITYR22_FLD_SET_MSK 0xffffffff
8715 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR22_FLD register field value. */
8716 #define ALT_GIC_DIST_GICD_IPRIORITYR22_FLD_CLR_MSK 0x00000000
8717 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR22_FLD register field. */
8718 #define ALT_GIC_DIST_GICD_IPRIORITYR22_FLD_RESET 0x0
8719 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR22_FLD field value from a register. */
8720 #define ALT_GIC_DIST_GICD_IPRIORITYR22_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8721 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR22_FLD register field value suitable for setting the register. */
8722 #define ALT_GIC_DIST_GICD_IPRIORITYR22_FLD_SET(value) (((value) << 0) & 0xffffffff)
8723 
8724 #ifndef __ASSEMBLY__
8725 /*
8726  * WARNING: The C register and register group struct declarations are provided for
8727  * convenience and illustrative purposes. They should, however, be used with
8728  * caution as the C language standard provides no guarantees about the alignment or
8729  * atomicity of device memory accesses. The recommended practice for coding device
8730  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8731  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8732  * alt_write_dword() functions for 64 bit registers.
8733  *
8734  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR22.
8735  */
8736 struct ALT_GIC_DIST_GICD_IPRIORITYR22_s
8737 {
8738  volatile uint32_t fld : 32; /* Empty */
8739 };
8740 
8741 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR22. */
8742 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR22_s ALT_GIC_DIST_GICD_IPRIORITYR22_t;
8743 #endif /* __ASSEMBLY__ */
8744 
8745 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR22 register. */
8746 #define ALT_GIC_DIST_GICD_IPRIORITYR22_RESET 0x00000000
8747 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR22 register from the beginning of the component. */
8748 #define ALT_GIC_DIST_GICD_IPRIORITYR22_OFST 0x458
8749 
8750 /*
8751  * Register : GICD_IPRIORITYR23
8752  *
8753  * Interrupt Priority Registers
8754  *
8755  * Register Layout
8756  *
8757  * Bits | Access | Reset | Description
8758  * :-------|:-------|:------|:------------
8759  * [31:0] | RW | 0x0 | Empty
8760  *
8761  */
8762 /*
8763  * Field : Empty - fld
8764  *
8765  * Placeholder
8766  *
8767  * Field Access Macros:
8768  *
8769  */
8770 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR23_FLD register field. */
8771 #define ALT_GIC_DIST_GICD_IPRIORITYR23_FLD_LSB 0
8772 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR23_FLD register field. */
8773 #define ALT_GIC_DIST_GICD_IPRIORITYR23_FLD_MSB 31
8774 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR23_FLD register field. */
8775 #define ALT_GIC_DIST_GICD_IPRIORITYR23_FLD_WIDTH 32
8776 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR23_FLD register field value. */
8777 #define ALT_GIC_DIST_GICD_IPRIORITYR23_FLD_SET_MSK 0xffffffff
8778 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR23_FLD register field value. */
8779 #define ALT_GIC_DIST_GICD_IPRIORITYR23_FLD_CLR_MSK 0x00000000
8780 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR23_FLD register field. */
8781 #define ALT_GIC_DIST_GICD_IPRIORITYR23_FLD_RESET 0x0
8782 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR23_FLD field value from a register. */
8783 #define ALT_GIC_DIST_GICD_IPRIORITYR23_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8784 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR23_FLD register field value suitable for setting the register. */
8785 #define ALT_GIC_DIST_GICD_IPRIORITYR23_FLD_SET(value) (((value) << 0) & 0xffffffff)
8786 
8787 #ifndef __ASSEMBLY__
8788 /*
8789  * WARNING: The C register and register group struct declarations are provided for
8790  * convenience and illustrative purposes. They should, however, be used with
8791  * caution as the C language standard provides no guarantees about the alignment or
8792  * atomicity of device memory accesses. The recommended practice for coding device
8793  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8794  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8795  * alt_write_dword() functions for 64 bit registers.
8796  *
8797  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR23.
8798  */
8799 struct ALT_GIC_DIST_GICD_IPRIORITYR23_s
8800 {
8801  volatile uint32_t fld : 32; /* Empty */
8802 };
8803 
8804 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR23. */
8805 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR23_s ALT_GIC_DIST_GICD_IPRIORITYR23_t;
8806 #endif /* __ASSEMBLY__ */
8807 
8808 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR23 register. */
8809 #define ALT_GIC_DIST_GICD_IPRIORITYR23_RESET 0x00000000
8810 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR23 register from the beginning of the component. */
8811 #define ALT_GIC_DIST_GICD_IPRIORITYR23_OFST 0x45c
8812 
8813 /*
8814  * Register : GICD_IPRIORITYR24
8815  *
8816  * Interrupt Priority Registers
8817  *
8818  * Register Layout
8819  *
8820  * Bits | Access | Reset | Description
8821  * :-------|:-------|:------|:------------
8822  * [31:0] | RW | 0x0 | Empty
8823  *
8824  */
8825 /*
8826  * Field : Empty - fld
8827  *
8828  * Placeholder
8829  *
8830  * Field Access Macros:
8831  *
8832  */
8833 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR24_FLD register field. */
8834 #define ALT_GIC_DIST_GICD_IPRIORITYR24_FLD_LSB 0
8835 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR24_FLD register field. */
8836 #define ALT_GIC_DIST_GICD_IPRIORITYR24_FLD_MSB 31
8837 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR24_FLD register field. */
8838 #define ALT_GIC_DIST_GICD_IPRIORITYR24_FLD_WIDTH 32
8839 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR24_FLD register field value. */
8840 #define ALT_GIC_DIST_GICD_IPRIORITYR24_FLD_SET_MSK 0xffffffff
8841 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR24_FLD register field value. */
8842 #define ALT_GIC_DIST_GICD_IPRIORITYR24_FLD_CLR_MSK 0x00000000
8843 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR24_FLD register field. */
8844 #define ALT_GIC_DIST_GICD_IPRIORITYR24_FLD_RESET 0x0
8845 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR24_FLD field value from a register. */
8846 #define ALT_GIC_DIST_GICD_IPRIORITYR24_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8847 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR24_FLD register field value suitable for setting the register. */
8848 #define ALT_GIC_DIST_GICD_IPRIORITYR24_FLD_SET(value) (((value) << 0) & 0xffffffff)
8849 
8850 #ifndef __ASSEMBLY__
8851 /*
8852  * WARNING: The C register and register group struct declarations are provided for
8853  * convenience and illustrative purposes. They should, however, be used with
8854  * caution as the C language standard provides no guarantees about the alignment or
8855  * atomicity of device memory accesses. The recommended practice for coding device
8856  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8857  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8858  * alt_write_dword() functions for 64 bit registers.
8859  *
8860  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR24.
8861  */
8862 struct ALT_GIC_DIST_GICD_IPRIORITYR24_s
8863 {
8864  volatile uint32_t fld : 32; /* Empty */
8865 };
8866 
8867 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR24. */
8868 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR24_s ALT_GIC_DIST_GICD_IPRIORITYR24_t;
8869 #endif /* __ASSEMBLY__ */
8870 
8871 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR24 register. */
8872 #define ALT_GIC_DIST_GICD_IPRIORITYR24_RESET 0x00000000
8873 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR24 register from the beginning of the component. */
8874 #define ALT_GIC_DIST_GICD_IPRIORITYR24_OFST 0x460
8875 
8876 /*
8877  * Register : GICD_IPRIORITYR25
8878  *
8879  * Interrupt Priority Registers
8880  *
8881  * Register Layout
8882  *
8883  * Bits | Access | Reset | Description
8884  * :-------|:-------|:------|:------------
8885  * [31:0] | RW | 0x0 | Empty
8886  *
8887  */
8888 /*
8889  * Field : Empty - fld
8890  *
8891  * Placeholder
8892  *
8893  * Field Access Macros:
8894  *
8895  */
8896 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR25_FLD register field. */
8897 #define ALT_GIC_DIST_GICD_IPRIORITYR25_FLD_LSB 0
8898 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR25_FLD register field. */
8899 #define ALT_GIC_DIST_GICD_IPRIORITYR25_FLD_MSB 31
8900 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR25_FLD register field. */
8901 #define ALT_GIC_DIST_GICD_IPRIORITYR25_FLD_WIDTH 32
8902 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR25_FLD register field value. */
8903 #define ALT_GIC_DIST_GICD_IPRIORITYR25_FLD_SET_MSK 0xffffffff
8904 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR25_FLD register field value. */
8905 #define ALT_GIC_DIST_GICD_IPRIORITYR25_FLD_CLR_MSK 0x00000000
8906 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR25_FLD register field. */
8907 #define ALT_GIC_DIST_GICD_IPRIORITYR25_FLD_RESET 0x0
8908 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR25_FLD field value from a register. */
8909 #define ALT_GIC_DIST_GICD_IPRIORITYR25_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8910 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR25_FLD register field value suitable for setting the register. */
8911 #define ALT_GIC_DIST_GICD_IPRIORITYR25_FLD_SET(value) (((value) << 0) & 0xffffffff)
8912 
8913 #ifndef __ASSEMBLY__
8914 /*
8915  * WARNING: The C register and register group struct declarations are provided for
8916  * convenience and illustrative purposes. They should, however, be used with
8917  * caution as the C language standard provides no guarantees about the alignment or
8918  * atomicity of device memory accesses. The recommended practice for coding device
8919  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8920  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8921  * alt_write_dword() functions for 64 bit registers.
8922  *
8923  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR25.
8924  */
8925 struct ALT_GIC_DIST_GICD_IPRIORITYR25_s
8926 {
8927  volatile uint32_t fld : 32; /* Empty */
8928 };
8929 
8930 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR25. */
8931 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR25_s ALT_GIC_DIST_GICD_IPRIORITYR25_t;
8932 #endif /* __ASSEMBLY__ */
8933 
8934 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR25 register. */
8935 #define ALT_GIC_DIST_GICD_IPRIORITYR25_RESET 0x00000000
8936 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR25 register from the beginning of the component. */
8937 #define ALT_GIC_DIST_GICD_IPRIORITYR25_OFST 0x464
8938 
8939 /*
8940  * Register : GICD_IPRIORITYR26
8941  *
8942  * Interrupt Priority Registers
8943  *
8944  * Register Layout
8945  *
8946  * Bits | Access | Reset | Description
8947  * :-------|:-------|:------|:------------
8948  * [31:0] | RW | 0x0 | Empty
8949  *
8950  */
8951 /*
8952  * Field : Empty - fld
8953  *
8954  * Placeholder
8955  *
8956  * Field Access Macros:
8957  *
8958  */
8959 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR26_FLD register field. */
8960 #define ALT_GIC_DIST_GICD_IPRIORITYR26_FLD_LSB 0
8961 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR26_FLD register field. */
8962 #define ALT_GIC_DIST_GICD_IPRIORITYR26_FLD_MSB 31
8963 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR26_FLD register field. */
8964 #define ALT_GIC_DIST_GICD_IPRIORITYR26_FLD_WIDTH 32
8965 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR26_FLD register field value. */
8966 #define ALT_GIC_DIST_GICD_IPRIORITYR26_FLD_SET_MSK 0xffffffff
8967 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR26_FLD register field value. */
8968 #define ALT_GIC_DIST_GICD_IPRIORITYR26_FLD_CLR_MSK 0x00000000
8969 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR26_FLD register field. */
8970 #define ALT_GIC_DIST_GICD_IPRIORITYR26_FLD_RESET 0x0
8971 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR26_FLD field value from a register. */
8972 #define ALT_GIC_DIST_GICD_IPRIORITYR26_FLD_GET(value) (((value) & 0xffffffff) >> 0)
8973 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR26_FLD register field value suitable for setting the register. */
8974 #define ALT_GIC_DIST_GICD_IPRIORITYR26_FLD_SET(value) (((value) << 0) & 0xffffffff)
8975 
8976 #ifndef __ASSEMBLY__
8977 /*
8978  * WARNING: The C register and register group struct declarations are provided for
8979  * convenience and illustrative purposes. They should, however, be used with
8980  * caution as the C language standard provides no guarantees about the alignment or
8981  * atomicity of device memory accesses. The recommended practice for coding device
8982  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8983  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8984  * alt_write_dword() functions for 64 bit registers.
8985  *
8986  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR26.
8987  */
8988 struct ALT_GIC_DIST_GICD_IPRIORITYR26_s
8989 {
8990  volatile uint32_t fld : 32; /* Empty */
8991 };
8992 
8993 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR26. */
8994 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR26_s ALT_GIC_DIST_GICD_IPRIORITYR26_t;
8995 #endif /* __ASSEMBLY__ */
8996 
8997 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR26 register. */
8998 #define ALT_GIC_DIST_GICD_IPRIORITYR26_RESET 0x00000000
8999 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR26 register from the beginning of the component. */
9000 #define ALT_GIC_DIST_GICD_IPRIORITYR26_OFST 0x468
9001 
9002 /*
9003  * Register : GICD_IPRIORITYR27
9004  *
9005  * Interrupt Priority Registers
9006  *
9007  * Register Layout
9008  *
9009  * Bits | Access | Reset | Description
9010  * :-------|:-------|:------|:------------
9011  * [31:0] | RW | 0x0 | Empty
9012  *
9013  */
9014 /*
9015  * Field : Empty - fld
9016  *
9017  * Placeholder
9018  *
9019  * Field Access Macros:
9020  *
9021  */
9022 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR27_FLD register field. */
9023 #define ALT_GIC_DIST_GICD_IPRIORITYR27_FLD_LSB 0
9024 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR27_FLD register field. */
9025 #define ALT_GIC_DIST_GICD_IPRIORITYR27_FLD_MSB 31
9026 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR27_FLD register field. */
9027 #define ALT_GIC_DIST_GICD_IPRIORITYR27_FLD_WIDTH 32
9028 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR27_FLD register field value. */
9029 #define ALT_GIC_DIST_GICD_IPRIORITYR27_FLD_SET_MSK 0xffffffff
9030 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR27_FLD register field value. */
9031 #define ALT_GIC_DIST_GICD_IPRIORITYR27_FLD_CLR_MSK 0x00000000
9032 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR27_FLD register field. */
9033 #define ALT_GIC_DIST_GICD_IPRIORITYR27_FLD_RESET 0x0
9034 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR27_FLD field value from a register. */
9035 #define ALT_GIC_DIST_GICD_IPRIORITYR27_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9036 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR27_FLD register field value suitable for setting the register. */
9037 #define ALT_GIC_DIST_GICD_IPRIORITYR27_FLD_SET(value) (((value) << 0) & 0xffffffff)
9038 
9039 #ifndef __ASSEMBLY__
9040 /*
9041  * WARNING: The C register and register group struct declarations are provided for
9042  * convenience and illustrative purposes. They should, however, be used with
9043  * caution as the C language standard provides no guarantees about the alignment or
9044  * atomicity of device memory accesses. The recommended practice for coding device
9045  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9046  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9047  * alt_write_dword() functions for 64 bit registers.
9048  *
9049  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR27.
9050  */
9051 struct ALT_GIC_DIST_GICD_IPRIORITYR27_s
9052 {
9053  volatile uint32_t fld : 32; /* Empty */
9054 };
9055 
9056 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR27. */
9057 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR27_s ALT_GIC_DIST_GICD_IPRIORITYR27_t;
9058 #endif /* __ASSEMBLY__ */
9059 
9060 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR27 register. */
9061 #define ALT_GIC_DIST_GICD_IPRIORITYR27_RESET 0x00000000
9062 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR27 register from the beginning of the component. */
9063 #define ALT_GIC_DIST_GICD_IPRIORITYR27_OFST 0x46c
9064 
9065 /*
9066  * Register : GICD_IPRIORITYR28
9067  *
9068  * Interrupt Priority Registers
9069  *
9070  * Register Layout
9071  *
9072  * Bits | Access | Reset | Description
9073  * :-------|:-------|:------|:------------
9074  * [31:0] | RW | 0x0 | Empty
9075  *
9076  */
9077 /*
9078  * Field : Empty - fld
9079  *
9080  * Placeholder
9081  *
9082  * Field Access Macros:
9083  *
9084  */
9085 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR28_FLD register field. */
9086 #define ALT_GIC_DIST_GICD_IPRIORITYR28_FLD_LSB 0
9087 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR28_FLD register field. */
9088 #define ALT_GIC_DIST_GICD_IPRIORITYR28_FLD_MSB 31
9089 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR28_FLD register field. */
9090 #define ALT_GIC_DIST_GICD_IPRIORITYR28_FLD_WIDTH 32
9091 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR28_FLD register field value. */
9092 #define ALT_GIC_DIST_GICD_IPRIORITYR28_FLD_SET_MSK 0xffffffff
9093 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR28_FLD register field value. */
9094 #define ALT_GIC_DIST_GICD_IPRIORITYR28_FLD_CLR_MSK 0x00000000
9095 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR28_FLD register field. */
9096 #define ALT_GIC_DIST_GICD_IPRIORITYR28_FLD_RESET 0x0
9097 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR28_FLD field value from a register. */
9098 #define ALT_GIC_DIST_GICD_IPRIORITYR28_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9099 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR28_FLD register field value suitable for setting the register. */
9100 #define ALT_GIC_DIST_GICD_IPRIORITYR28_FLD_SET(value) (((value) << 0) & 0xffffffff)
9101 
9102 #ifndef __ASSEMBLY__
9103 /*
9104  * WARNING: The C register and register group struct declarations are provided for
9105  * convenience and illustrative purposes. They should, however, be used with
9106  * caution as the C language standard provides no guarantees about the alignment or
9107  * atomicity of device memory accesses. The recommended practice for coding device
9108  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9109  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9110  * alt_write_dword() functions for 64 bit registers.
9111  *
9112  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR28.
9113  */
9114 struct ALT_GIC_DIST_GICD_IPRIORITYR28_s
9115 {
9116  volatile uint32_t fld : 32; /* Empty */
9117 };
9118 
9119 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR28. */
9120 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR28_s ALT_GIC_DIST_GICD_IPRIORITYR28_t;
9121 #endif /* __ASSEMBLY__ */
9122 
9123 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR28 register. */
9124 #define ALT_GIC_DIST_GICD_IPRIORITYR28_RESET 0x00000000
9125 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR28 register from the beginning of the component. */
9126 #define ALT_GIC_DIST_GICD_IPRIORITYR28_OFST 0x470
9127 
9128 /*
9129  * Register : GICD_IPRIORITYR29
9130  *
9131  * Interrupt Priority Registers
9132  *
9133  * Register Layout
9134  *
9135  * Bits | Access | Reset | Description
9136  * :-------|:-------|:------|:------------
9137  * [31:0] | RW | 0x0 | Empty
9138  *
9139  */
9140 /*
9141  * Field : Empty - fld
9142  *
9143  * Placeholder
9144  *
9145  * Field Access Macros:
9146  *
9147  */
9148 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR29_FLD register field. */
9149 #define ALT_GIC_DIST_GICD_IPRIORITYR29_FLD_LSB 0
9150 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR29_FLD register field. */
9151 #define ALT_GIC_DIST_GICD_IPRIORITYR29_FLD_MSB 31
9152 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR29_FLD register field. */
9153 #define ALT_GIC_DIST_GICD_IPRIORITYR29_FLD_WIDTH 32
9154 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR29_FLD register field value. */
9155 #define ALT_GIC_DIST_GICD_IPRIORITYR29_FLD_SET_MSK 0xffffffff
9156 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR29_FLD register field value. */
9157 #define ALT_GIC_DIST_GICD_IPRIORITYR29_FLD_CLR_MSK 0x00000000
9158 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR29_FLD register field. */
9159 #define ALT_GIC_DIST_GICD_IPRIORITYR29_FLD_RESET 0x0
9160 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR29_FLD field value from a register. */
9161 #define ALT_GIC_DIST_GICD_IPRIORITYR29_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9162 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR29_FLD register field value suitable for setting the register. */
9163 #define ALT_GIC_DIST_GICD_IPRIORITYR29_FLD_SET(value) (((value) << 0) & 0xffffffff)
9164 
9165 #ifndef __ASSEMBLY__
9166 /*
9167  * WARNING: The C register and register group struct declarations are provided for
9168  * convenience and illustrative purposes. They should, however, be used with
9169  * caution as the C language standard provides no guarantees about the alignment or
9170  * atomicity of device memory accesses. The recommended practice for coding device
9171  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9172  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9173  * alt_write_dword() functions for 64 bit registers.
9174  *
9175  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR29.
9176  */
9177 struct ALT_GIC_DIST_GICD_IPRIORITYR29_s
9178 {
9179  volatile uint32_t fld : 32; /* Empty */
9180 };
9181 
9182 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR29. */
9183 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR29_s ALT_GIC_DIST_GICD_IPRIORITYR29_t;
9184 #endif /* __ASSEMBLY__ */
9185 
9186 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR29 register. */
9187 #define ALT_GIC_DIST_GICD_IPRIORITYR29_RESET 0x00000000
9188 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR29 register from the beginning of the component. */
9189 #define ALT_GIC_DIST_GICD_IPRIORITYR29_OFST 0x474
9190 
9191 /*
9192  * Register : GICD_IPRIORITYR30
9193  *
9194  * Interrupt Priority Registers
9195  *
9196  * Register Layout
9197  *
9198  * Bits | Access | Reset | Description
9199  * :-------|:-------|:------|:------------
9200  * [31:0] | RW | 0x0 | Empty
9201  *
9202  */
9203 /*
9204  * Field : Empty - fld
9205  *
9206  * Placeholder
9207  *
9208  * Field Access Macros:
9209  *
9210  */
9211 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR30_FLD register field. */
9212 #define ALT_GIC_DIST_GICD_IPRIORITYR30_FLD_LSB 0
9213 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR30_FLD register field. */
9214 #define ALT_GIC_DIST_GICD_IPRIORITYR30_FLD_MSB 31
9215 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR30_FLD register field. */
9216 #define ALT_GIC_DIST_GICD_IPRIORITYR30_FLD_WIDTH 32
9217 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR30_FLD register field value. */
9218 #define ALT_GIC_DIST_GICD_IPRIORITYR30_FLD_SET_MSK 0xffffffff
9219 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR30_FLD register field value. */
9220 #define ALT_GIC_DIST_GICD_IPRIORITYR30_FLD_CLR_MSK 0x00000000
9221 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR30_FLD register field. */
9222 #define ALT_GIC_DIST_GICD_IPRIORITYR30_FLD_RESET 0x0
9223 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR30_FLD field value from a register. */
9224 #define ALT_GIC_DIST_GICD_IPRIORITYR30_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9225 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR30_FLD register field value suitable for setting the register. */
9226 #define ALT_GIC_DIST_GICD_IPRIORITYR30_FLD_SET(value) (((value) << 0) & 0xffffffff)
9227 
9228 #ifndef __ASSEMBLY__
9229 /*
9230  * WARNING: The C register and register group struct declarations are provided for
9231  * convenience and illustrative purposes. They should, however, be used with
9232  * caution as the C language standard provides no guarantees about the alignment or
9233  * atomicity of device memory accesses. The recommended practice for coding device
9234  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9235  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9236  * alt_write_dword() functions for 64 bit registers.
9237  *
9238  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR30.
9239  */
9240 struct ALT_GIC_DIST_GICD_IPRIORITYR30_s
9241 {
9242  volatile uint32_t fld : 32; /* Empty */
9243 };
9244 
9245 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR30. */
9246 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR30_s ALT_GIC_DIST_GICD_IPRIORITYR30_t;
9247 #endif /* __ASSEMBLY__ */
9248 
9249 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR30 register. */
9250 #define ALT_GIC_DIST_GICD_IPRIORITYR30_RESET 0x00000000
9251 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR30 register from the beginning of the component. */
9252 #define ALT_GIC_DIST_GICD_IPRIORITYR30_OFST 0x478
9253 
9254 /*
9255  * Register : GICD_IPRIORITYR31
9256  *
9257  * Interrupt Priority Registers
9258  *
9259  * Register Layout
9260  *
9261  * Bits | Access | Reset | Description
9262  * :-------|:-------|:------|:------------
9263  * [31:0] | RW | 0x0 | Empty
9264  *
9265  */
9266 /*
9267  * Field : Empty - fld
9268  *
9269  * Placeholder
9270  *
9271  * Field Access Macros:
9272  *
9273  */
9274 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR31_FLD register field. */
9275 #define ALT_GIC_DIST_GICD_IPRIORITYR31_FLD_LSB 0
9276 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR31_FLD register field. */
9277 #define ALT_GIC_DIST_GICD_IPRIORITYR31_FLD_MSB 31
9278 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR31_FLD register field. */
9279 #define ALT_GIC_DIST_GICD_IPRIORITYR31_FLD_WIDTH 32
9280 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR31_FLD register field value. */
9281 #define ALT_GIC_DIST_GICD_IPRIORITYR31_FLD_SET_MSK 0xffffffff
9282 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR31_FLD register field value. */
9283 #define ALT_GIC_DIST_GICD_IPRIORITYR31_FLD_CLR_MSK 0x00000000
9284 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR31_FLD register field. */
9285 #define ALT_GIC_DIST_GICD_IPRIORITYR31_FLD_RESET 0x0
9286 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR31_FLD field value from a register. */
9287 #define ALT_GIC_DIST_GICD_IPRIORITYR31_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9288 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR31_FLD register field value suitable for setting the register. */
9289 #define ALT_GIC_DIST_GICD_IPRIORITYR31_FLD_SET(value) (((value) << 0) & 0xffffffff)
9290 
9291 #ifndef __ASSEMBLY__
9292 /*
9293  * WARNING: The C register and register group struct declarations are provided for
9294  * convenience and illustrative purposes. They should, however, be used with
9295  * caution as the C language standard provides no guarantees about the alignment or
9296  * atomicity of device memory accesses. The recommended practice for coding device
9297  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9298  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9299  * alt_write_dword() functions for 64 bit registers.
9300  *
9301  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR31.
9302  */
9303 struct ALT_GIC_DIST_GICD_IPRIORITYR31_s
9304 {
9305  volatile uint32_t fld : 32; /* Empty */
9306 };
9307 
9308 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR31. */
9309 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR31_s ALT_GIC_DIST_GICD_IPRIORITYR31_t;
9310 #endif /* __ASSEMBLY__ */
9311 
9312 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR31 register. */
9313 #define ALT_GIC_DIST_GICD_IPRIORITYR31_RESET 0x00000000
9314 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR31 register from the beginning of the component. */
9315 #define ALT_GIC_DIST_GICD_IPRIORITYR31_OFST 0x47c
9316 
9317 /*
9318  * Register : GICD_IPRIORITYR32
9319  *
9320  * Interrupt Priority Registers
9321  *
9322  * Register Layout
9323  *
9324  * Bits | Access | Reset | Description
9325  * :-------|:-------|:------|:------------
9326  * [31:0] | RW | 0x0 | Empty
9327  *
9328  */
9329 /*
9330  * Field : Empty - fld
9331  *
9332  * Placeholder
9333  *
9334  * Field Access Macros:
9335  *
9336  */
9337 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR32_FLD register field. */
9338 #define ALT_GIC_DIST_GICD_IPRIORITYR32_FLD_LSB 0
9339 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR32_FLD register field. */
9340 #define ALT_GIC_DIST_GICD_IPRIORITYR32_FLD_MSB 31
9341 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR32_FLD register field. */
9342 #define ALT_GIC_DIST_GICD_IPRIORITYR32_FLD_WIDTH 32
9343 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR32_FLD register field value. */
9344 #define ALT_GIC_DIST_GICD_IPRIORITYR32_FLD_SET_MSK 0xffffffff
9345 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR32_FLD register field value. */
9346 #define ALT_GIC_DIST_GICD_IPRIORITYR32_FLD_CLR_MSK 0x00000000
9347 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR32_FLD register field. */
9348 #define ALT_GIC_DIST_GICD_IPRIORITYR32_FLD_RESET 0x0
9349 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR32_FLD field value from a register. */
9350 #define ALT_GIC_DIST_GICD_IPRIORITYR32_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9351 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR32_FLD register field value suitable for setting the register. */
9352 #define ALT_GIC_DIST_GICD_IPRIORITYR32_FLD_SET(value) (((value) << 0) & 0xffffffff)
9353 
9354 #ifndef __ASSEMBLY__
9355 /*
9356  * WARNING: The C register and register group struct declarations are provided for
9357  * convenience and illustrative purposes. They should, however, be used with
9358  * caution as the C language standard provides no guarantees about the alignment or
9359  * atomicity of device memory accesses. The recommended practice for coding device
9360  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9361  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9362  * alt_write_dword() functions for 64 bit registers.
9363  *
9364  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR32.
9365  */
9366 struct ALT_GIC_DIST_GICD_IPRIORITYR32_s
9367 {
9368  volatile uint32_t fld : 32; /* Empty */
9369 };
9370 
9371 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR32. */
9372 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR32_s ALT_GIC_DIST_GICD_IPRIORITYR32_t;
9373 #endif /* __ASSEMBLY__ */
9374 
9375 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR32 register. */
9376 #define ALT_GIC_DIST_GICD_IPRIORITYR32_RESET 0x00000000
9377 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR32 register from the beginning of the component. */
9378 #define ALT_GIC_DIST_GICD_IPRIORITYR32_OFST 0x480
9379 
9380 /*
9381  * Register : GICD_IPRIORITYR33
9382  *
9383  * Interrupt Priority Registers
9384  *
9385  * Register Layout
9386  *
9387  * Bits | Access | Reset | Description
9388  * :-------|:-------|:------|:------------
9389  * [31:0] | RW | 0x0 | Empty
9390  *
9391  */
9392 /*
9393  * Field : Empty - fld
9394  *
9395  * Placeholder
9396  *
9397  * Field Access Macros:
9398  *
9399  */
9400 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR33_FLD register field. */
9401 #define ALT_GIC_DIST_GICD_IPRIORITYR33_FLD_LSB 0
9402 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR33_FLD register field. */
9403 #define ALT_GIC_DIST_GICD_IPRIORITYR33_FLD_MSB 31
9404 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR33_FLD register field. */
9405 #define ALT_GIC_DIST_GICD_IPRIORITYR33_FLD_WIDTH 32
9406 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR33_FLD register field value. */
9407 #define ALT_GIC_DIST_GICD_IPRIORITYR33_FLD_SET_MSK 0xffffffff
9408 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR33_FLD register field value. */
9409 #define ALT_GIC_DIST_GICD_IPRIORITYR33_FLD_CLR_MSK 0x00000000
9410 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR33_FLD register field. */
9411 #define ALT_GIC_DIST_GICD_IPRIORITYR33_FLD_RESET 0x0
9412 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR33_FLD field value from a register. */
9413 #define ALT_GIC_DIST_GICD_IPRIORITYR33_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9414 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR33_FLD register field value suitable for setting the register. */
9415 #define ALT_GIC_DIST_GICD_IPRIORITYR33_FLD_SET(value) (((value) << 0) & 0xffffffff)
9416 
9417 #ifndef __ASSEMBLY__
9418 /*
9419  * WARNING: The C register and register group struct declarations are provided for
9420  * convenience and illustrative purposes. They should, however, be used with
9421  * caution as the C language standard provides no guarantees about the alignment or
9422  * atomicity of device memory accesses. The recommended practice for coding device
9423  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9424  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9425  * alt_write_dword() functions for 64 bit registers.
9426  *
9427  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR33.
9428  */
9429 struct ALT_GIC_DIST_GICD_IPRIORITYR33_s
9430 {
9431  volatile uint32_t fld : 32; /* Empty */
9432 };
9433 
9434 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR33. */
9435 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR33_s ALT_GIC_DIST_GICD_IPRIORITYR33_t;
9436 #endif /* __ASSEMBLY__ */
9437 
9438 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR33 register. */
9439 #define ALT_GIC_DIST_GICD_IPRIORITYR33_RESET 0x00000000
9440 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR33 register from the beginning of the component. */
9441 #define ALT_GIC_DIST_GICD_IPRIORITYR33_OFST 0x484
9442 
9443 /*
9444  * Register : GICD_IPRIORITYR34
9445  *
9446  * Interrupt Priority Registers
9447  *
9448  * Register Layout
9449  *
9450  * Bits | Access | Reset | Description
9451  * :-------|:-------|:------|:------------
9452  * [31:0] | RW | 0x0 | Empty
9453  *
9454  */
9455 /*
9456  * Field : Empty - fld
9457  *
9458  * Placeholder
9459  *
9460  * Field Access Macros:
9461  *
9462  */
9463 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR34_FLD register field. */
9464 #define ALT_GIC_DIST_GICD_IPRIORITYR34_FLD_LSB 0
9465 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR34_FLD register field. */
9466 #define ALT_GIC_DIST_GICD_IPRIORITYR34_FLD_MSB 31
9467 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR34_FLD register field. */
9468 #define ALT_GIC_DIST_GICD_IPRIORITYR34_FLD_WIDTH 32
9469 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR34_FLD register field value. */
9470 #define ALT_GIC_DIST_GICD_IPRIORITYR34_FLD_SET_MSK 0xffffffff
9471 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR34_FLD register field value. */
9472 #define ALT_GIC_DIST_GICD_IPRIORITYR34_FLD_CLR_MSK 0x00000000
9473 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR34_FLD register field. */
9474 #define ALT_GIC_DIST_GICD_IPRIORITYR34_FLD_RESET 0x0
9475 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR34_FLD field value from a register. */
9476 #define ALT_GIC_DIST_GICD_IPRIORITYR34_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9477 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR34_FLD register field value suitable for setting the register. */
9478 #define ALT_GIC_DIST_GICD_IPRIORITYR34_FLD_SET(value) (((value) << 0) & 0xffffffff)
9479 
9480 #ifndef __ASSEMBLY__
9481 /*
9482  * WARNING: The C register and register group struct declarations are provided for
9483  * convenience and illustrative purposes. They should, however, be used with
9484  * caution as the C language standard provides no guarantees about the alignment or
9485  * atomicity of device memory accesses. The recommended practice for coding device
9486  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9487  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9488  * alt_write_dword() functions for 64 bit registers.
9489  *
9490  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR34.
9491  */
9492 struct ALT_GIC_DIST_GICD_IPRIORITYR34_s
9493 {
9494  volatile uint32_t fld : 32; /* Empty */
9495 };
9496 
9497 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR34. */
9498 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR34_s ALT_GIC_DIST_GICD_IPRIORITYR34_t;
9499 #endif /* __ASSEMBLY__ */
9500 
9501 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR34 register. */
9502 #define ALT_GIC_DIST_GICD_IPRIORITYR34_RESET 0x00000000
9503 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR34 register from the beginning of the component. */
9504 #define ALT_GIC_DIST_GICD_IPRIORITYR34_OFST 0x488
9505 
9506 /*
9507  * Register : GICD_IPRIORITYR35
9508  *
9509  * Interrupt Priority Registers
9510  *
9511  * Register Layout
9512  *
9513  * Bits | Access | Reset | Description
9514  * :-------|:-------|:------|:------------
9515  * [31:0] | RW | 0x0 | Empty
9516  *
9517  */
9518 /*
9519  * Field : Empty - fld
9520  *
9521  * Placeholder
9522  *
9523  * Field Access Macros:
9524  *
9525  */
9526 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR35_FLD register field. */
9527 #define ALT_GIC_DIST_GICD_IPRIORITYR35_FLD_LSB 0
9528 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR35_FLD register field. */
9529 #define ALT_GIC_DIST_GICD_IPRIORITYR35_FLD_MSB 31
9530 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR35_FLD register field. */
9531 #define ALT_GIC_DIST_GICD_IPRIORITYR35_FLD_WIDTH 32
9532 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR35_FLD register field value. */
9533 #define ALT_GIC_DIST_GICD_IPRIORITYR35_FLD_SET_MSK 0xffffffff
9534 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR35_FLD register field value. */
9535 #define ALT_GIC_DIST_GICD_IPRIORITYR35_FLD_CLR_MSK 0x00000000
9536 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR35_FLD register field. */
9537 #define ALT_GIC_DIST_GICD_IPRIORITYR35_FLD_RESET 0x0
9538 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR35_FLD field value from a register. */
9539 #define ALT_GIC_DIST_GICD_IPRIORITYR35_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9540 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR35_FLD register field value suitable for setting the register. */
9541 #define ALT_GIC_DIST_GICD_IPRIORITYR35_FLD_SET(value) (((value) << 0) & 0xffffffff)
9542 
9543 #ifndef __ASSEMBLY__
9544 /*
9545  * WARNING: The C register and register group struct declarations are provided for
9546  * convenience and illustrative purposes. They should, however, be used with
9547  * caution as the C language standard provides no guarantees about the alignment or
9548  * atomicity of device memory accesses. The recommended practice for coding device
9549  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9550  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9551  * alt_write_dword() functions for 64 bit registers.
9552  *
9553  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR35.
9554  */
9555 struct ALT_GIC_DIST_GICD_IPRIORITYR35_s
9556 {
9557  volatile uint32_t fld : 32; /* Empty */
9558 };
9559 
9560 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR35. */
9561 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR35_s ALT_GIC_DIST_GICD_IPRIORITYR35_t;
9562 #endif /* __ASSEMBLY__ */
9563 
9564 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR35 register. */
9565 #define ALT_GIC_DIST_GICD_IPRIORITYR35_RESET 0x00000000
9566 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR35 register from the beginning of the component. */
9567 #define ALT_GIC_DIST_GICD_IPRIORITYR35_OFST 0x48c
9568 
9569 /*
9570  * Register : GICD_IPRIORITYR36
9571  *
9572  * Interrupt Priority Registers
9573  *
9574  * Register Layout
9575  *
9576  * Bits | Access | Reset | Description
9577  * :-------|:-------|:------|:------------
9578  * [31:0] | RW | 0x0 | Empty
9579  *
9580  */
9581 /*
9582  * Field : Empty - fld
9583  *
9584  * Placeholder
9585  *
9586  * Field Access Macros:
9587  *
9588  */
9589 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR36_FLD register field. */
9590 #define ALT_GIC_DIST_GICD_IPRIORITYR36_FLD_LSB 0
9591 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR36_FLD register field. */
9592 #define ALT_GIC_DIST_GICD_IPRIORITYR36_FLD_MSB 31
9593 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR36_FLD register field. */
9594 #define ALT_GIC_DIST_GICD_IPRIORITYR36_FLD_WIDTH 32
9595 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR36_FLD register field value. */
9596 #define ALT_GIC_DIST_GICD_IPRIORITYR36_FLD_SET_MSK 0xffffffff
9597 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR36_FLD register field value. */
9598 #define ALT_GIC_DIST_GICD_IPRIORITYR36_FLD_CLR_MSK 0x00000000
9599 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR36_FLD register field. */
9600 #define ALT_GIC_DIST_GICD_IPRIORITYR36_FLD_RESET 0x0
9601 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR36_FLD field value from a register. */
9602 #define ALT_GIC_DIST_GICD_IPRIORITYR36_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9603 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR36_FLD register field value suitable for setting the register. */
9604 #define ALT_GIC_DIST_GICD_IPRIORITYR36_FLD_SET(value) (((value) << 0) & 0xffffffff)
9605 
9606 #ifndef __ASSEMBLY__
9607 /*
9608  * WARNING: The C register and register group struct declarations are provided for
9609  * convenience and illustrative purposes. They should, however, be used with
9610  * caution as the C language standard provides no guarantees about the alignment or
9611  * atomicity of device memory accesses. The recommended practice for coding device
9612  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9613  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9614  * alt_write_dword() functions for 64 bit registers.
9615  *
9616  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR36.
9617  */
9618 struct ALT_GIC_DIST_GICD_IPRIORITYR36_s
9619 {
9620  volatile uint32_t fld : 32; /* Empty */
9621 };
9622 
9623 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR36. */
9624 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR36_s ALT_GIC_DIST_GICD_IPRIORITYR36_t;
9625 #endif /* __ASSEMBLY__ */
9626 
9627 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR36 register. */
9628 #define ALT_GIC_DIST_GICD_IPRIORITYR36_RESET 0x00000000
9629 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR36 register from the beginning of the component. */
9630 #define ALT_GIC_DIST_GICD_IPRIORITYR36_OFST 0x490
9631 
9632 /*
9633  * Register : GICD_IPRIORITYR37
9634  *
9635  * Interrupt Priority Registers
9636  *
9637  * Register Layout
9638  *
9639  * Bits | Access | Reset | Description
9640  * :-------|:-------|:------|:------------
9641  * [31:0] | RW | 0x0 | Empty
9642  *
9643  */
9644 /*
9645  * Field : Empty - fld
9646  *
9647  * Placeholder
9648  *
9649  * Field Access Macros:
9650  *
9651  */
9652 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR37_FLD register field. */
9653 #define ALT_GIC_DIST_GICD_IPRIORITYR37_FLD_LSB 0
9654 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR37_FLD register field. */
9655 #define ALT_GIC_DIST_GICD_IPRIORITYR37_FLD_MSB 31
9656 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR37_FLD register field. */
9657 #define ALT_GIC_DIST_GICD_IPRIORITYR37_FLD_WIDTH 32
9658 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR37_FLD register field value. */
9659 #define ALT_GIC_DIST_GICD_IPRIORITYR37_FLD_SET_MSK 0xffffffff
9660 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR37_FLD register field value. */
9661 #define ALT_GIC_DIST_GICD_IPRIORITYR37_FLD_CLR_MSK 0x00000000
9662 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR37_FLD register field. */
9663 #define ALT_GIC_DIST_GICD_IPRIORITYR37_FLD_RESET 0x0
9664 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR37_FLD field value from a register. */
9665 #define ALT_GIC_DIST_GICD_IPRIORITYR37_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9666 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR37_FLD register field value suitable for setting the register. */
9667 #define ALT_GIC_DIST_GICD_IPRIORITYR37_FLD_SET(value) (((value) << 0) & 0xffffffff)
9668 
9669 #ifndef __ASSEMBLY__
9670 /*
9671  * WARNING: The C register and register group struct declarations are provided for
9672  * convenience and illustrative purposes. They should, however, be used with
9673  * caution as the C language standard provides no guarantees about the alignment or
9674  * atomicity of device memory accesses. The recommended practice for coding device
9675  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9676  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9677  * alt_write_dword() functions for 64 bit registers.
9678  *
9679  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR37.
9680  */
9681 struct ALT_GIC_DIST_GICD_IPRIORITYR37_s
9682 {
9683  volatile uint32_t fld : 32; /* Empty */
9684 };
9685 
9686 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR37. */
9687 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR37_s ALT_GIC_DIST_GICD_IPRIORITYR37_t;
9688 #endif /* __ASSEMBLY__ */
9689 
9690 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR37 register. */
9691 #define ALT_GIC_DIST_GICD_IPRIORITYR37_RESET 0x00000000
9692 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR37 register from the beginning of the component. */
9693 #define ALT_GIC_DIST_GICD_IPRIORITYR37_OFST 0x494
9694 
9695 /*
9696  * Register : GICD_IPRIORITYR38
9697  *
9698  * Interrupt Priority Registers
9699  *
9700  * Register Layout
9701  *
9702  * Bits | Access | Reset | Description
9703  * :-------|:-------|:------|:------------
9704  * [31:0] | RW | 0x0 | Empty
9705  *
9706  */
9707 /*
9708  * Field : Empty - fld
9709  *
9710  * Placeholder
9711  *
9712  * Field Access Macros:
9713  *
9714  */
9715 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR38_FLD register field. */
9716 #define ALT_GIC_DIST_GICD_IPRIORITYR38_FLD_LSB 0
9717 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR38_FLD register field. */
9718 #define ALT_GIC_DIST_GICD_IPRIORITYR38_FLD_MSB 31
9719 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR38_FLD register field. */
9720 #define ALT_GIC_DIST_GICD_IPRIORITYR38_FLD_WIDTH 32
9721 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR38_FLD register field value. */
9722 #define ALT_GIC_DIST_GICD_IPRIORITYR38_FLD_SET_MSK 0xffffffff
9723 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR38_FLD register field value. */
9724 #define ALT_GIC_DIST_GICD_IPRIORITYR38_FLD_CLR_MSK 0x00000000
9725 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR38_FLD register field. */
9726 #define ALT_GIC_DIST_GICD_IPRIORITYR38_FLD_RESET 0x0
9727 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR38_FLD field value from a register. */
9728 #define ALT_GIC_DIST_GICD_IPRIORITYR38_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9729 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR38_FLD register field value suitable for setting the register. */
9730 #define ALT_GIC_DIST_GICD_IPRIORITYR38_FLD_SET(value) (((value) << 0) & 0xffffffff)
9731 
9732 #ifndef __ASSEMBLY__
9733 /*
9734  * WARNING: The C register and register group struct declarations are provided for
9735  * convenience and illustrative purposes. They should, however, be used with
9736  * caution as the C language standard provides no guarantees about the alignment or
9737  * atomicity of device memory accesses. The recommended practice for coding device
9738  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9739  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9740  * alt_write_dword() functions for 64 bit registers.
9741  *
9742  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR38.
9743  */
9744 struct ALT_GIC_DIST_GICD_IPRIORITYR38_s
9745 {
9746  volatile uint32_t fld : 32; /* Empty */
9747 };
9748 
9749 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR38. */
9750 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR38_s ALT_GIC_DIST_GICD_IPRIORITYR38_t;
9751 #endif /* __ASSEMBLY__ */
9752 
9753 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR38 register. */
9754 #define ALT_GIC_DIST_GICD_IPRIORITYR38_RESET 0x00000000
9755 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR38 register from the beginning of the component. */
9756 #define ALT_GIC_DIST_GICD_IPRIORITYR38_OFST 0x498
9757 
9758 /*
9759  * Register : GICD_IPRIORITYR39
9760  *
9761  * Interrupt Priority Registers
9762  *
9763  * Register Layout
9764  *
9765  * Bits | Access | Reset | Description
9766  * :-------|:-------|:------|:------------
9767  * [31:0] | RW | 0x0 | Empty
9768  *
9769  */
9770 /*
9771  * Field : Empty - fld
9772  *
9773  * Placeholder
9774  *
9775  * Field Access Macros:
9776  *
9777  */
9778 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR39_FLD register field. */
9779 #define ALT_GIC_DIST_GICD_IPRIORITYR39_FLD_LSB 0
9780 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR39_FLD register field. */
9781 #define ALT_GIC_DIST_GICD_IPRIORITYR39_FLD_MSB 31
9782 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR39_FLD register field. */
9783 #define ALT_GIC_DIST_GICD_IPRIORITYR39_FLD_WIDTH 32
9784 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR39_FLD register field value. */
9785 #define ALT_GIC_DIST_GICD_IPRIORITYR39_FLD_SET_MSK 0xffffffff
9786 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR39_FLD register field value. */
9787 #define ALT_GIC_DIST_GICD_IPRIORITYR39_FLD_CLR_MSK 0x00000000
9788 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR39_FLD register field. */
9789 #define ALT_GIC_DIST_GICD_IPRIORITYR39_FLD_RESET 0x0
9790 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR39_FLD field value from a register. */
9791 #define ALT_GIC_DIST_GICD_IPRIORITYR39_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9792 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR39_FLD register field value suitable for setting the register. */
9793 #define ALT_GIC_DIST_GICD_IPRIORITYR39_FLD_SET(value) (((value) << 0) & 0xffffffff)
9794 
9795 #ifndef __ASSEMBLY__
9796 /*
9797  * WARNING: The C register and register group struct declarations are provided for
9798  * convenience and illustrative purposes. They should, however, be used with
9799  * caution as the C language standard provides no guarantees about the alignment or
9800  * atomicity of device memory accesses. The recommended practice for coding device
9801  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9802  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9803  * alt_write_dword() functions for 64 bit registers.
9804  *
9805  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR39.
9806  */
9807 struct ALT_GIC_DIST_GICD_IPRIORITYR39_s
9808 {
9809  volatile uint32_t fld : 32; /* Empty */
9810 };
9811 
9812 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR39. */
9813 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR39_s ALT_GIC_DIST_GICD_IPRIORITYR39_t;
9814 #endif /* __ASSEMBLY__ */
9815 
9816 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR39 register. */
9817 #define ALT_GIC_DIST_GICD_IPRIORITYR39_RESET 0x00000000
9818 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR39 register from the beginning of the component. */
9819 #define ALT_GIC_DIST_GICD_IPRIORITYR39_OFST 0x49c
9820 
9821 /*
9822  * Register : GICD_IPRIORITYR40
9823  *
9824  * Interrupt Priority Registers
9825  *
9826  * Register Layout
9827  *
9828  * Bits | Access | Reset | Description
9829  * :-------|:-------|:------|:------------
9830  * [31:0] | RW | 0x0 | Empty
9831  *
9832  */
9833 /*
9834  * Field : Empty - fld
9835  *
9836  * Placeholder
9837  *
9838  * Field Access Macros:
9839  *
9840  */
9841 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR40_FLD register field. */
9842 #define ALT_GIC_DIST_GICD_IPRIORITYR40_FLD_LSB 0
9843 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR40_FLD register field. */
9844 #define ALT_GIC_DIST_GICD_IPRIORITYR40_FLD_MSB 31
9845 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR40_FLD register field. */
9846 #define ALT_GIC_DIST_GICD_IPRIORITYR40_FLD_WIDTH 32
9847 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR40_FLD register field value. */
9848 #define ALT_GIC_DIST_GICD_IPRIORITYR40_FLD_SET_MSK 0xffffffff
9849 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR40_FLD register field value. */
9850 #define ALT_GIC_DIST_GICD_IPRIORITYR40_FLD_CLR_MSK 0x00000000
9851 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR40_FLD register field. */
9852 #define ALT_GIC_DIST_GICD_IPRIORITYR40_FLD_RESET 0x0
9853 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR40_FLD field value from a register. */
9854 #define ALT_GIC_DIST_GICD_IPRIORITYR40_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9855 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR40_FLD register field value suitable for setting the register. */
9856 #define ALT_GIC_DIST_GICD_IPRIORITYR40_FLD_SET(value) (((value) << 0) & 0xffffffff)
9857 
9858 #ifndef __ASSEMBLY__
9859 /*
9860  * WARNING: The C register and register group struct declarations are provided for
9861  * convenience and illustrative purposes. They should, however, be used with
9862  * caution as the C language standard provides no guarantees about the alignment or
9863  * atomicity of device memory accesses. The recommended practice for coding device
9864  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9865  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9866  * alt_write_dword() functions for 64 bit registers.
9867  *
9868  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR40.
9869  */
9870 struct ALT_GIC_DIST_GICD_IPRIORITYR40_s
9871 {
9872  volatile uint32_t fld : 32; /* Empty */
9873 };
9874 
9875 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR40. */
9876 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR40_s ALT_GIC_DIST_GICD_IPRIORITYR40_t;
9877 #endif /* __ASSEMBLY__ */
9878 
9879 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR40 register. */
9880 #define ALT_GIC_DIST_GICD_IPRIORITYR40_RESET 0x00000000
9881 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR40 register from the beginning of the component. */
9882 #define ALT_GIC_DIST_GICD_IPRIORITYR40_OFST 0x4a0
9883 
9884 /*
9885  * Register : GICD_IPRIORITYR41
9886  *
9887  * Interrupt Priority Registers
9888  *
9889  * Register Layout
9890  *
9891  * Bits | Access | Reset | Description
9892  * :-------|:-------|:------|:------------
9893  * [31:0] | RW | 0x0 | Empty
9894  *
9895  */
9896 /*
9897  * Field : Empty - fld
9898  *
9899  * Placeholder
9900  *
9901  * Field Access Macros:
9902  *
9903  */
9904 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR41_FLD register field. */
9905 #define ALT_GIC_DIST_GICD_IPRIORITYR41_FLD_LSB 0
9906 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR41_FLD register field. */
9907 #define ALT_GIC_DIST_GICD_IPRIORITYR41_FLD_MSB 31
9908 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR41_FLD register field. */
9909 #define ALT_GIC_DIST_GICD_IPRIORITYR41_FLD_WIDTH 32
9910 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR41_FLD register field value. */
9911 #define ALT_GIC_DIST_GICD_IPRIORITYR41_FLD_SET_MSK 0xffffffff
9912 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR41_FLD register field value. */
9913 #define ALT_GIC_DIST_GICD_IPRIORITYR41_FLD_CLR_MSK 0x00000000
9914 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR41_FLD register field. */
9915 #define ALT_GIC_DIST_GICD_IPRIORITYR41_FLD_RESET 0x0
9916 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR41_FLD field value from a register. */
9917 #define ALT_GIC_DIST_GICD_IPRIORITYR41_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9918 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR41_FLD register field value suitable for setting the register. */
9919 #define ALT_GIC_DIST_GICD_IPRIORITYR41_FLD_SET(value) (((value) << 0) & 0xffffffff)
9920 
9921 #ifndef __ASSEMBLY__
9922 /*
9923  * WARNING: The C register and register group struct declarations are provided for
9924  * convenience and illustrative purposes. They should, however, be used with
9925  * caution as the C language standard provides no guarantees about the alignment or
9926  * atomicity of device memory accesses. The recommended practice for coding device
9927  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9928  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9929  * alt_write_dword() functions for 64 bit registers.
9930  *
9931  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR41.
9932  */
9933 struct ALT_GIC_DIST_GICD_IPRIORITYR41_s
9934 {
9935  volatile uint32_t fld : 32; /* Empty */
9936 };
9937 
9938 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR41. */
9939 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR41_s ALT_GIC_DIST_GICD_IPRIORITYR41_t;
9940 #endif /* __ASSEMBLY__ */
9941 
9942 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR41 register. */
9943 #define ALT_GIC_DIST_GICD_IPRIORITYR41_RESET 0x00000000
9944 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR41 register from the beginning of the component. */
9945 #define ALT_GIC_DIST_GICD_IPRIORITYR41_OFST 0x4a4
9946 
9947 /*
9948  * Register : GICD_IPRIORITYR42
9949  *
9950  * Interrupt Priority Registers
9951  *
9952  * Register Layout
9953  *
9954  * Bits | Access | Reset | Description
9955  * :-------|:-------|:------|:------------
9956  * [31:0] | RW | 0x0 | Empty
9957  *
9958  */
9959 /*
9960  * Field : Empty - fld
9961  *
9962  * Placeholder
9963  *
9964  * Field Access Macros:
9965  *
9966  */
9967 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR42_FLD register field. */
9968 #define ALT_GIC_DIST_GICD_IPRIORITYR42_FLD_LSB 0
9969 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR42_FLD register field. */
9970 #define ALT_GIC_DIST_GICD_IPRIORITYR42_FLD_MSB 31
9971 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR42_FLD register field. */
9972 #define ALT_GIC_DIST_GICD_IPRIORITYR42_FLD_WIDTH 32
9973 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR42_FLD register field value. */
9974 #define ALT_GIC_DIST_GICD_IPRIORITYR42_FLD_SET_MSK 0xffffffff
9975 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR42_FLD register field value. */
9976 #define ALT_GIC_DIST_GICD_IPRIORITYR42_FLD_CLR_MSK 0x00000000
9977 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR42_FLD register field. */
9978 #define ALT_GIC_DIST_GICD_IPRIORITYR42_FLD_RESET 0x0
9979 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR42_FLD field value from a register. */
9980 #define ALT_GIC_DIST_GICD_IPRIORITYR42_FLD_GET(value) (((value) & 0xffffffff) >> 0)
9981 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR42_FLD register field value suitable for setting the register. */
9982 #define ALT_GIC_DIST_GICD_IPRIORITYR42_FLD_SET(value) (((value) << 0) & 0xffffffff)
9983 
9984 #ifndef __ASSEMBLY__
9985 /*
9986  * WARNING: The C register and register group struct declarations are provided for
9987  * convenience and illustrative purposes. They should, however, be used with
9988  * caution as the C language standard provides no guarantees about the alignment or
9989  * atomicity of device memory accesses. The recommended practice for coding device
9990  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9991  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9992  * alt_write_dword() functions for 64 bit registers.
9993  *
9994  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR42.
9995  */
9996 struct ALT_GIC_DIST_GICD_IPRIORITYR42_s
9997 {
9998  volatile uint32_t fld : 32; /* Empty */
9999 };
10000 
10001 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR42. */
10002 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR42_s ALT_GIC_DIST_GICD_IPRIORITYR42_t;
10003 #endif /* __ASSEMBLY__ */
10004 
10005 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR42 register. */
10006 #define ALT_GIC_DIST_GICD_IPRIORITYR42_RESET 0x00000000
10007 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR42 register from the beginning of the component. */
10008 #define ALT_GIC_DIST_GICD_IPRIORITYR42_OFST 0x4a8
10009 
10010 /*
10011  * Register : GICD_IPRIORITYR43
10012  *
10013  * Interrupt Priority Registers
10014  *
10015  * Register Layout
10016  *
10017  * Bits | Access | Reset | Description
10018  * :-------|:-------|:------|:------------
10019  * [31:0] | RW | 0x0 | Empty
10020  *
10021  */
10022 /*
10023  * Field : Empty - fld
10024  *
10025  * Placeholder
10026  *
10027  * Field Access Macros:
10028  *
10029  */
10030 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR43_FLD register field. */
10031 #define ALT_GIC_DIST_GICD_IPRIORITYR43_FLD_LSB 0
10032 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR43_FLD register field. */
10033 #define ALT_GIC_DIST_GICD_IPRIORITYR43_FLD_MSB 31
10034 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR43_FLD register field. */
10035 #define ALT_GIC_DIST_GICD_IPRIORITYR43_FLD_WIDTH 32
10036 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR43_FLD register field value. */
10037 #define ALT_GIC_DIST_GICD_IPRIORITYR43_FLD_SET_MSK 0xffffffff
10038 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR43_FLD register field value. */
10039 #define ALT_GIC_DIST_GICD_IPRIORITYR43_FLD_CLR_MSK 0x00000000
10040 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR43_FLD register field. */
10041 #define ALT_GIC_DIST_GICD_IPRIORITYR43_FLD_RESET 0x0
10042 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR43_FLD field value from a register. */
10043 #define ALT_GIC_DIST_GICD_IPRIORITYR43_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10044 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR43_FLD register field value suitable for setting the register. */
10045 #define ALT_GIC_DIST_GICD_IPRIORITYR43_FLD_SET(value) (((value) << 0) & 0xffffffff)
10046 
10047 #ifndef __ASSEMBLY__
10048 /*
10049  * WARNING: The C register and register group struct declarations are provided for
10050  * convenience and illustrative purposes. They should, however, be used with
10051  * caution as the C language standard provides no guarantees about the alignment or
10052  * atomicity of device memory accesses. The recommended practice for coding device
10053  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10054  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10055  * alt_write_dword() functions for 64 bit registers.
10056  *
10057  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR43.
10058  */
10059 struct ALT_GIC_DIST_GICD_IPRIORITYR43_s
10060 {
10061  volatile uint32_t fld : 32; /* Empty */
10062 };
10063 
10064 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR43. */
10065 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR43_s ALT_GIC_DIST_GICD_IPRIORITYR43_t;
10066 #endif /* __ASSEMBLY__ */
10067 
10068 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR43 register. */
10069 #define ALT_GIC_DIST_GICD_IPRIORITYR43_RESET 0x00000000
10070 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR43 register from the beginning of the component. */
10071 #define ALT_GIC_DIST_GICD_IPRIORITYR43_OFST 0x4ac
10072 
10073 /*
10074  * Register : GICD_IPRIORITYR44
10075  *
10076  * Interrupt Priority Registers
10077  *
10078  * Register Layout
10079  *
10080  * Bits | Access | Reset | Description
10081  * :-------|:-------|:------|:------------
10082  * [31:0] | RW | 0x0 | Empty
10083  *
10084  */
10085 /*
10086  * Field : Empty - fld
10087  *
10088  * Placeholder
10089  *
10090  * Field Access Macros:
10091  *
10092  */
10093 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR44_FLD register field. */
10094 #define ALT_GIC_DIST_GICD_IPRIORITYR44_FLD_LSB 0
10095 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR44_FLD register field. */
10096 #define ALT_GIC_DIST_GICD_IPRIORITYR44_FLD_MSB 31
10097 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR44_FLD register field. */
10098 #define ALT_GIC_DIST_GICD_IPRIORITYR44_FLD_WIDTH 32
10099 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR44_FLD register field value. */
10100 #define ALT_GIC_DIST_GICD_IPRIORITYR44_FLD_SET_MSK 0xffffffff
10101 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR44_FLD register field value. */
10102 #define ALT_GIC_DIST_GICD_IPRIORITYR44_FLD_CLR_MSK 0x00000000
10103 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR44_FLD register field. */
10104 #define ALT_GIC_DIST_GICD_IPRIORITYR44_FLD_RESET 0x0
10105 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR44_FLD field value from a register. */
10106 #define ALT_GIC_DIST_GICD_IPRIORITYR44_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10107 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR44_FLD register field value suitable for setting the register. */
10108 #define ALT_GIC_DIST_GICD_IPRIORITYR44_FLD_SET(value) (((value) << 0) & 0xffffffff)
10109 
10110 #ifndef __ASSEMBLY__
10111 /*
10112  * WARNING: The C register and register group struct declarations are provided for
10113  * convenience and illustrative purposes. They should, however, be used with
10114  * caution as the C language standard provides no guarantees about the alignment or
10115  * atomicity of device memory accesses. The recommended practice for coding device
10116  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10117  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10118  * alt_write_dword() functions for 64 bit registers.
10119  *
10120  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR44.
10121  */
10122 struct ALT_GIC_DIST_GICD_IPRIORITYR44_s
10123 {
10124  volatile uint32_t fld : 32; /* Empty */
10125 };
10126 
10127 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR44. */
10128 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR44_s ALT_GIC_DIST_GICD_IPRIORITYR44_t;
10129 #endif /* __ASSEMBLY__ */
10130 
10131 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR44 register. */
10132 #define ALT_GIC_DIST_GICD_IPRIORITYR44_RESET 0x00000000
10133 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR44 register from the beginning of the component. */
10134 #define ALT_GIC_DIST_GICD_IPRIORITYR44_OFST 0x4b0
10135 
10136 /*
10137  * Register : GICD_IPRIORITYR45
10138  *
10139  * Interrupt Priority Registers
10140  *
10141  * Register Layout
10142  *
10143  * Bits | Access | Reset | Description
10144  * :-------|:-------|:------|:------------
10145  * [31:0] | RW | 0x0 | Empty
10146  *
10147  */
10148 /*
10149  * Field : Empty - fld
10150  *
10151  * Placeholder
10152  *
10153  * Field Access Macros:
10154  *
10155  */
10156 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR45_FLD register field. */
10157 #define ALT_GIC_DIST_GICD_IPRIORITYR45_FLD_LSB 0
10158 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR45_FLD register field. */
10159 #define ALT_GIC_DIST_GICD_IPRIORITYR45_FLD_MSB 31
10160 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR45_FLD register field. */
10161 #define ALT_GIC_DIST_GICD_IPRIORITYR45_FLD_WIDTH 32
10162 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR45_FLD register field value. */
10163 #define ALT_GIC_DIST_GICD_IPRIORITYR45_FLD_SET_MSK 0xffffffff
10164 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR45_FLD register field value. */
10165 #define ALT_GIC_DIST_GICD_IPRIORITYR45_FLD_CLR_MSK 0x00000000
10166 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR45_FLD register field. */
10167 #define ALT_GIC_DIST_GICD_IPRIORITYR45_FLD_RESET 0x0
10168 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR45_FLD field value from a register. */
10169 #define ALT_GIC_DIST_GICD_IPRIORITYR45_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10170 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR45_FLD register field value suitable for setting the register. */
10171 #define ALT_GIC_DIST_GICD_IPRIORITYR45_FLD_SET(value) (((value) << 0) & 0xffffffff)
10172 
10173 #ifndef __ASSEMBLY__
10174 /*
10175  * WARNING: The C register and register group struct declarations are provided for
10176  * convenience and illustrative purposes. They should, however, be used with
10177  * caution as the C language standard provides no guarantees about the alignment or
10178  * atomicity of device memory accesses. The recommended practice for coding device
10179  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10180  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10181  * alt_write_dword() functions for 64 bit registers.
10182  *
10183  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR45.
10184  */
10185 struct ALT_GIC_DIST_GICD_IPRIORITYR45_s
10186 {
10187  volatile uint32_t fld : 32; /* Empty */
10188 };
10189 
10190 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR45. */
10191 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR45_s ALT_GIC_DIST_GICD_IPRIORITYR45_t;
10192 #endif /* __ASSEMBLY__ */
10193 
10194 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR45 register. */
10195 #define ALT_GIC_DIST_GICD_IPRIORITYR45_RESET 0x00000000
10196 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR45 register from the beginning of the component. */
10197 #define ALT_GIC_DIST_GICD_IPRIORITYR45_OFST 0x4b4
10198 
10199 /*
10200  * Register : GICD_IPRIORITYR46
10201  *
10202  * Interrupt Priority Registers
10203  *
10204  * Register Layout
10205  *
10206  * Bits | Access | Reset | Description
10207  * :-------|:-------|:------|:------------
10208  * [31:0] | RW | 0x0 | Empty
10209  *
10210  */
10211 /*
10212  * Field : Empty - fld
10213  *
10214  * Placeholder
10215  *
10216  * Field Access Macros:
10217  *
10218  */
10219 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR46_FLD register field. */
10220 #define ALT_GIC_DIST_GICD_IPRIORITYR46_FLD_LSB 0
10221 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR46_FLD register field. */
10222 #define ALT_GIC_DIST_GICD_IPRIORITYR46_FLD_MSB 31
10223 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR46_FLD register field. */
10224 #define ALT_GIC_DIST_GICD_IPRIORITYR46_FLD_WIDTH 32
10225 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR46_FLD register field value. */
10226 #define ALT_GIC_DIST_GICD_IPRIORITYR46_FLD_SET_MSK 0xffffffff
10227 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR46_FLD register field value. */
10228 #define ALT_GIC_DIST_GICD_IPRIORITYR46_FLD_CLR_MSK 0x00000000
10229 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR46_FLD register field. */
10230 #define ALT_GIC_DIST_GICD_IPRIORITYR46_FLD_RESET 0x0
10231 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR46_FLD field value from a register. */
10232 #define ALT_GIC_DIST_GICD_IPRIORITYR46_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10233 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR46_FLD register field value suitable for setting the register. */
10234 #define ALT_GIC_DIST_GICD_IPRIORITYR46_FLD_SET(value) (((value) << 0) & 0xffffffff)
10235 
10236 #ifndef __ASSEMBLY__
10237 /*
10238  * WARNING: The C register and register group struct declarations are provided for
10239  * convenience and illustrative purposes. They should, however, be used with
10240  * caution as the C language standard provides no guarantees about the alignment or
10241  * atomicity of device memory accesses. The recommended practice for coding device
10242  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10243  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10244  * alt_write_dword() functions for 64 bit registers.
10245  *
10246  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR46.
10247  */
10248 struct ALT_GIC_DIST_GICD_IPRIORITYR46_s
10249 {
10250  volatile uint32_t fld : 32; /* Empty */
10251 };
10252 
10253 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR46. */
10254 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR46_s ALT_GIC_DIST_GICD_IPRIORITYR46_t;
10255 #endif /* __ASSEMBLY__ */
10256 
10257 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR46 register. */
10258 #define ALT_GIC_DIST_GICD_IPRIORITYR46_RESET 0x00000000
10259 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR46 register from the beginning of the component. */
10260 #define ALT_GIC_DIST_GICD_IPRIORITYR46_OFST 0x4b8
10261 
10262 /*
10263  * Register : GICD_IPRIORITYR47
10264  *
10265  * Interrupt Priority Registers
10266  *
10267  * Register Layout
10268  *
10269  * Bits | Access | Reset | Description
10270  * :-------|:-------|:------|:------------
10271  * [31:0] | RW | 0x0 | Empty
10272  *
10273  */
10274 /*
10275  * Field : Empty - fld
10276  *
10277  * Placeholder
10278  *
10279  * Field Access Macros:
10280  *
10281  */
10282 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR47_FLD register field. */
10283 #define ALT_GIC_DIST_GICD_IPRIORITYR47_FLD_LSB 0
10284 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR47_FLD register field. */
10285 #define ALT_GIC_DIST_GICD_IPRIORITYR47_FLD_MSB 31
10286 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR47_FLD register field. */
10287 #define ALT_GIC_DIST_GICD_IPRIORITYR47_FLD_WIDTH 32
10288 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR47_FLD register field value. */
10289 #define ALT_GIC_DIST_GICD_IPRIORITYR47_FLD_SET_MSK 0xffffffff
10290 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR47_FLD register field value. */
10291 #define ALT_GIC_DIST_GICD_IPRIORITYR47_FLD_CLR_MSK 0x00000000
10292 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR47_FLD register field. */
10293 #define ALT_GIC_DIST_GICD_IPRIORITYR47_FLD_RESET 0x0
10294 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR47_FLD field value from a register. */
10295 #define ALT_GIC_DIST_GICD_IPRIORITYR47_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10296 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR47_FLD register field value suitable for setting the register. */
10297 #define ALT_GIC_DIST_GICD_IPRIORITYR47_FLD_SET(value) (((value) << 0) & 0xffffffff)
10298 
10299 #ifndef __ASSEMBLY__
10300 /*
10301  * WARNING: The C register and register group struct declarations are provided for
10302  * convenience and illustrative purposes. They should, however, be used with
10303  * caution as the C language standard provides no guarantees about the alignment or
10304  * atomicity of device memory accesses. The recommended practice for coding device
10305  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10306  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10307  * alt_write_dword() functions for 64 bit registers.
10308  *
10309  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR47.
10310  */
10311 struct ALT_GIC_DIST_GICD_IPRIORITYR47_s
10312 {
10313  volatile uint32_t fld : 32; /* Empty */
10314 };
10315 
10316 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR47. */
10317 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR47_s ALT_GIC_DIST_GICD_IPRIORITYR47_t;
10318 #endif /* __ASSEMBLY__ */
10319 
10320 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR47 register. */
10321 #define ALT_GIC_DIST_GICD_IPRIORITYR47_RESET 0x00000000
10322 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR47 register from the beginning of the component. */
10323 #define ALT_GIC_DIST_GICD_IPRIORITYR47_OFST 0x4bc
10324 
10325 /*
10326  * Register : GICD_IPRIORITYR48
10327  *
10328  * Interrupt Priority Registers
10329  *
10330  * Register Layout
10331  *
10332  * Bits | Access | Reset | Description
10333  * :-------|:-------|:------|:------------
10334  * [31:0] | RW | 0x0 | Empty
10335  *
10336  */
10337 /*
10338  * Field : Empty - fld
10339  *
10340  * Placeholder
10341  *
10342  * Field Access Macros:
10343  *
10344  */
10345 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR48_FLD register field. */
10346 #define ALT_GIC_DIST_GICD_IPRIORITYR48_FLD_LSB 0
10347 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR48_FLD register field. */
10348 #define ALT_GIC_DIST_GICD_IPRIORITYR48_FLD_MSB 31
10349 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR48_FLD register field. */
10350 #define ALT_GIC_DIST_GICD_IPRIORITYR48_FLD_WIDTH 32
10351 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR48_FLD register field value. */
10352 #define ALT_GIC_DIST_GICD_IPRIORITYR48_FLD_SET_MSK 0xffffffff
10353 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR48_FLD register field value. */
10354 #define ALT_GIC_DIST_GICD_IPRIORITYR48_FLD_CLR_MSK 0x00000000
10355 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR48_FLD register field. */
10356 #define ALT_GIC_DIST_GICD_IPRIORITYR48_FLD_RESET 0x0
10357 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR48_FLD field value from a register. */
10358 #define ALT_GIC_DIST_GICD_IPRIORITYR48_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10359 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR48_FLD register field value suitable for setting the register. */
10360 #define ALT_GIC_DIST_GICD_IPRIORITYR48_FLD_SET(value) (((value) << 0) & 0xffffffff)
10361 
10362 #ifndef __ASSEMBLY__
10363 /*
10364  * WARNING: The C register and register group struct declarations are provided for
10365  * convenience and illustrative purposes. They should, however, be used with
10366  * caution as the C language standard provides no guarantees about the alignment or
10367  * atomicity of device memory accesses. The recommended practice for coding device
10368  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10369  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10370  * alt_write_dword() functions for 64 bit registers.
10371  *
10372  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR48.
10373  */
10374 struct ALT_GIC_DIST_GICD_IPRIORITYR48_s
10375 {
10376  volatile uint32_t fld : 32; /* Empty */
10377 };
10378 
10379 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR48. */
10380 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR48_s ALT_GIC_DIST_GICD_IPRIORITYR48_t;
10381 #endif /* __ASSEMBLY__ */
10382 
10383 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR48 register. */
10384 #define ALT_GIC_DIST_GICD_IPRIORITYR48_RESET 0x00000000
10385 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR48 register from the beginning of the component. */
10386 #define ALT_GIC_DIST_GICD_IPRIORITYR48_OFST 0x4c0
10387 
10388 /*
10389  * Register : GICD_IPRIORITYR49
10390  *
10391  * Interrupt Priority Registers
10392  *
10393  * Register Layout
10394  *
10395  * Bits | Access | Reset | Description
10396  * :-------|:-------|:------|:------------
10397  * [31:0] | RW | 0x0 | Empty
10398  *
10399  */
10400 /*
10401  * Field : Empty - fld
10402  *
10403  * Placeholder
10404  *
10405  * Field Access Macros:
10406  *
10407  */
10408 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR49_FLD register field. */
10409 #define ALT_GIC_DIST_GICD_IPRIORITYR49_FLD_LSB 0
10410 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR49_FLD register field. */
10411 #define ALT_GIC_DIST_GICD_IPRIORITYR49_FLD_MSB 31
10412 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR49_FLD register field. */
10413 #define ALT_GIC_DIST_GICD_IPRIORITYR49_FLD_WIDTH 32
10414 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR49_FLD register field value. */
10415 #define ALT_GIC_DIST_GICD_IPRIORITYR49_FLD_SET_MSK 0xffffffff
10416 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR49_FLD register field value. */
10417 #define ALT_GIC_DIST_GICD_IPRIORITYR49_FLD_CLR_MSK 0x00000000
10418 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR49_FLD register field. */
10419 #define ALT_GIC_DIST_GICD_IPRIORITYR49_FLD_RESET 0x0
10420 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR49_FLD field value from a register. */
10421 #define ALT_GIC_DIST_GICD_IPRIORITYR49_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10422 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR49_FLD register field value suitable for setting the register. */
10423 #define ALT_GIC_DIST_GICD_IPRIORITYR49_FLD_SET(value) (((value) << 0) & 0xffffffff)
10424 
10425 #ifndef __ASSEMBLY__
10426 /*
10427  * WARNING: The C register and register group struct declarations are provided for
10428  * convenience and illustrative purposes. They should, however, be used with
10429  * caution as the C language standard provides no guarantees about the alignment or
10430  * atomicity of device memory accesses. The recommended practice for coding device
10431  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10432  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10433  * alt_write_dword() functions for 64 bit registers.
10434  *
10435  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR49.
10436  */
10437 struct ALT_GIC_DIST_GICD_IPRIORITYR49_s
10438 {
10439  volatile uint32_t fld : 32; /* Empty */
10440 };
10441 
10442 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR49. */
10443 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR49_s ALT_GIC_DIST_GICD_IPRIORITYR49_t;
10444 #endif /* __ASSEMBLY__ */
10445 
10446 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR49 register. */
10447 #define ALT_GIC_DIST_GICD_IPRIORITYR49_RESET 0x00000000
10448 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR49 register from the beginning of the component. */
10449 #define ALT_GIC_DIST_GICD_IPRIORITYR49_OFST 0x4c4
10450 
10451 /*
10452  * Register : GICD_IPRIORITYR50
10453  *
10454  * Interrupt Priority Registers
10455  *
10456  * Register Layout
10457  *
10458  * Bits | Access | Reset | Description
10459  * :-------|:-------|:------|:------------
10460  * [31:0] | RW | 0x0 | Empty
10461  *
10462  */
10463 /*
10464  * Field : Empty - fld
10465  *
10466  * Placeholder
10467  *
10468  * Field Access Macros:
10469  *
10470  */
10471 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR50_FLD register field. */
10472 #define ALT_GIC_DIST_GICD_IPRIORITYR50_FLD_LSB 0
10473 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR50_FLD register field. */
10474 #define ALT_GIC_DIST_GICD_IPRIORITYR50_FLD_MSB 31
10475 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR50_FLD register field. */
10476 #define ALT_GIC_DIST_GICD_IPRIORITYR50_FLD_WIDTH 32
10477 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR50_FLD register field value. */
10478 #define ALT_GIC_DIST_GICD_IPRIORITYR50_FLD_SET_MSK 0xffffffff
10479 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR50_FLD register field value. */
10480 #define ALT_GIC_DIST_GICD_IPRIORITYR50_FLD_CLR_MSK 0x00000000
10481 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR50_FLD register field. */
10482 #define ALT_GIC_DIST_GICD_IPRIORITYR50_FLD_RESET 0x0
10483 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR50_FLD field value from a register. */
10484 #define ALT_GIC_DIST_GICD_IPRIORITYR50_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10485 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR50_FLD register field value suitable for setting the register. */
10486 #define ALT_GIC_DIST_GICD_IPRIORITYR50_FLD_SET(value) (((value) << 0) & 0xffffffff)
10487 
10488 #ifndef __ASSEMBLY__
10489 /*
10490  * WARNING: The C register and register group struct declarations are provided for
10491  * convenience and illustrative purposes. They should, however, be used with
10492  * caution as the C language standard provides no guarantees about the alignment or
10493  * atomicity of device memory accesses. The recommended practice for coding device
10494  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10495  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10496  * alt_write_dword() functions for 64 bit registers.
10497  *
10498  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR50.
10499  */
10500 struct ALT_GIC_DIST_GICD_IPRIORITYR50_s
10501 {
10502  volatile uint32_t fld : 32; /* Empty */
10503 };
10504 
10505 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR50. */
10506 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR50_s ALT_GIC_DIST_GICD_IPRIORITYR50_t;
10507 #endif /* __ASSEMBLY__ */
10508 
10509 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR50 register. */
10510 #define ALT_GIC_DIST_GICD_IPRIORITYR50_RESET 0x00000000
10511 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR50 register from the beginning of the component. */
10512 #define ALT_GIC_DIST_GICD_IPRIORITYR50_OFST 0x4c8
10513 
10514 /*
10515  * Register : GICD_IPRIORITYR51
10516  *
10517  * Interrupt Priority Registers
10518  *
10519  * Register Layout
10520  *
10521  * Bits | Access | Reset | Description
10522  * :-------|:-------|:------|:------------
10523  * [31:0] | RW | 0x0 | Empty
10524  *
10525  */
10526 /*
10527  * Field : Empty - fld
10528  *
10529  * Placeholder
10530  *
10531  * Field Access Macros:
10532  *
10533  */
10534 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR51_FLD register field. */
10535 #define ALT_GIC_DIST_GICD_IPRIORITYR51_FLD_LSB 0
10536 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR51_FLD register field. */
10537 #define ALT_GIC_DIST_GICD_IPRIORITYR51_FLD_MSB 31
10538 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR51_FLD register field. */
10539 #define ALT_GIC_DIST_GICD_IPRIORITYR51_FLD_WIDTH 32
10540 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR51_FLD register field value. */
10541 #define ALT_GIC_DIST_GICD_IPRIORITYR51_FLD_SET_MSK 0xffffffff
10542 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR51_FLD register field value. */
10543 #define ALT_GIC_DIST_GICD_IPRIORITYR51_FLD_CLR_MSK 0x00000000
10544 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR51_FLD register field. */
10545 #define ALT_GIC_DIST_GICD_IPRIORITYR51_FLD_RESET 0x0
10546 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR51_FLD field value from a register. */
10547 #define ALT_GIC_DIST_GICD_IPRIORITYR51_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10548 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR51_FLD register field value suitable for setting the register. */
10549 #define ALT_GIC_DIST_GICD_IPRIORITYR51_FLD_SET(value) (((value) << 0) & 0xffffffff)
10550 
10551 #ifndef __ASSEMBLY__
10552 /*
10553  * WARNING: The C register and register group struct declarations are provided for
10554  * convenience and illustrative purposes. They should, however, be used with
10555  * caution as the C language standard provides no guarantees about the alignment or
10556  * atomicity of device memory accesses. The recommended practice for coding device
10557  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10558  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10559  * alt_write_dword() functions for 64 bit registers.
10560  *
10561  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR51.
10562  */
10563 struct ALT_GIC_DIST_GICD_IPRIORITYR51_s
10564 {
10565  volatile uint32_t fld : 32; /* Empty */
10566 };
10567 
10568 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR51. */
10569 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR51_s ALT_GIC_DIST_GICD_IPRIORITYR51_t;
10570 #endif /* __ASSEMBLY__ */
10571 
10572 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR51 register. */
10573 #define ALT_GIC_DIST_GICD_IPRIORITYR51_RESET 0x00000000
10574 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR51 register from the beginning of the component. */
10575 #define ALT_GIC_DIST_GICD_IPRIORITYR51_OFST 0x4cc
10576 
10577 /*
10578  * Register : GICD_IPRIORITYR52
10579  *
10580  * Interrupt Priority Registers
10581  *
10582  * Register Layout
10583  *
10584  * Bits | Access | Reset | Description
10585  * :-------|:-------|:------|:------------
10586  * [31:0] | RW | 0x0 | Empty
10587  *
10588  */
10589 /*
10590  * Field : Empty - fld
10591  *
10592  * Placeholder
10593  *
10594  * Field Access Macros:
10595  *
10596  */
10597 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR52_FLD register field. */
10598 #define ALT_GIC_DIST_GICD_IPRIORITYR52_FLD_LSB 0
10599 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR52_FLD register field. */
10600 #define ALT_GIC_DIST_GICD_IPRIORITYR52_FLD_MSB 31
10601 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR52_FLD register field. */
10602 #define ALT_GIC_DIST_GICD_IPRIORITYR52_FLD_WIDTH 32
10603 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR52_FLD register field value. */
10604 #define ALT_GIC_DIST_GICD_IPRIORITYR52_FLD_SET_MSK 0xffffffff
10605 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR52_FLD register field value. */
10606 #define ALT_GIC_DIST_GICD_IPRIORITYR52_FLD_CLR_MSK 0x00000000
10607 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR52_FLD register field. */
10608 #define ALT_GIC_DIST_GICD_IPRIORITYR52_FLD_RESET 0x0
10609 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR52_FLD field value from a register. */
10610 #define ALT_GIC_DIST_GICD_IPRIORITYR52_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10611 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR52_FLD register field value suitable for setting the register. */
10612 #define ALT_GIC_DIST_GICD_IPRIORITYR52_FLD_SET(value) (((value) << 0) & 0xffffffff)
10613 
10614 #ifndef __ASSEMBLY__
10615 /*
10616  * WARNING: The C register and register group struct declarations are provided for
10617  * convenience and illustrative purposes. They should, however, be used with
10618  * caution as the C language standard provides no guarantees about the alignment or
10619  * atomicity of device memory accesses. The recommended practice for coding device
10620  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10621  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10622  * alt_write_dword() functions for 64 bit registers.
10623  *
10624  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR52.
10625  */
10626 struct ALT_GIC_DIST_GICD_IPRIORITYR52_s
10627 {
10628  volatile uint32_t fld : 32; /* Empty */
10629 };
10630 
10631 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR52. */
10632 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR52_s ALT_GIC_DIST_GICD_IPRIORITYR52_t;
10633 #endif /* __ASSEMBLY__ */
10634 
10635 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR52 register. */
10636 #define ALT_GIC_DIST_GICD_IPRIORITYR52_RESET 0x00000000
10637 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR52 register from the beginning of the component. */
10638 #define ALT_GIC_DIST_GICD_IPRIORITYR52_OFST 0x4d0
10639 
10640 /*
10641  * Register : GICD_IPRIORITYR53
10642  *
10643  * Interrupt Priority Registers
10644  *
10645  * Register Layout
10646  *
10647  * Bits | Access | Reset | Description
10648  * :-------|:-------|:------|:------------
10649  * [31:0] | RW | 0x0 | Empty
10650  *
10651  */
10652 /*
10653  * Field : Empty - fld
10654  *
10655  * Placeholder
10656  *
10657  * Field Access Macros:
10658  *
10659  */
10660 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR53_FLD register field. */
10661 #define ALT_GIC_DIST_GICD_IPRIORITYR53_FLD_LSB 0
10662 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR53_FLD register field. */
10663 #define ALT_GIC_DIST_GICD_IPRIORITYR53_FLD_MSB 31
10664 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR53_FLD register field. */
10665 #define ALT_GIC_DIST_GICD_IPRIORITYR53_FLD_WIDTH 32
10666 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR53_FLD register field value. */
10667 #define ALT_GIC_DIST_GICD_IPRIORITYR53_FLD_SET_MSK 0xffffffff
10668 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR53_FLD register field value. */
10669 #define ALT_GIC_DIST_GICD_IPRIORITYR53_FLD_CLR_MSK 0x00000000
10670 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR53_FLD register field. */
10671 #define ALT_GIC_DIST_GICD_IPRIORITYR53_FLD_RESET 0x0
10672 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR53_FLD field value from a register. */
10673 #define ALT_GIC_DIST_GICD_IPRIORITYR53_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10674 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR53_FLD register field value suitable for setting the register. */
10675 #define ALT_GIC_DIST_GICD_IPRIORITYR53_FLD_SET(value) (((value) << 0) & 0xffffffff)
10676 
10677 #ifndef __ASSEMBLY__
10678 /*
10679  * WARNING: The C register and register group struct declarations are provided for
10680  * convenience and illustrative purposes. They should, however, be used with
10681  * caution as the C language standard provides no guarantees about the alignment or
10682  * atomicity of device memory accesses. The recommended practice for coding device
10683  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10684  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10685  * alt_write_dword() functions for 64 bit registers.
10686  *
10687  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR53.
10688  */
10689 struct ALT_GIC_DIST_GICD_IPRIORITYR53_s
10690 {
10691  volatile uint32_t fld : 32; /* Empty */
10692 };
10693 
10694 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR53. */
10695 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR53_s ALT_GIC_DIST_GICD_IPRIORITYR53_t;
10696 #endif /* __ASSEMBLY__ */
10697 
10698 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR53 register. */
10699 #define ALT_GIC_DIST_GICD_IPRIORITYR53_RESET 0x00000000
10700 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR53 register from the beginning of the component. */
10701 #define ALT_GIC_DIST_GICD_IPRIORITYR53_OFST 0x4d4
10702 
10703 /*
10704  * Register : GICD_IPRIORITYR54
10705  *
10706  * Interrupt Priority Registers
10707  *
10708  * Register Layout
10709  *
10710  * Bits | Access | Reset | Description
10711  * :-------|:-------|:------|:------------
10712  * [31:0] | RW | 0x0 | Empty
10713  *
10714  */
10715 /*
10716  * Field : Empty - fld
10717  *
10718  * Placeholder
10719  *
10720  * Field Access Macros:
10721  *
10722  */
10723 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR54_FLD register field. */
10724 #define ALT_GIC_DIST_GICD_IPRIORITYR54_FLD_LSB 0
10725 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR54_FLD register field. */
10726 #define ALT_GIC_DIST_GICD_IPRIORITYR54_FLD_MSB 31
10727 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR54_FLD register field. */
10728 #define ALT_GIC_DIST_GICD_IPRIORITYR54_FLD_WIDTH 32
10729 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR54_FLD register field value. */
10730 #define ALT_GIC_DIST_GICD_IPRIORITYR54_FLD_SET_MSK 0xffffffff
10731 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR54_FLD register field value. */
10732 #define ALT_GIC_DIST_GICD_IPRIORITYR54_FLD_CLR_MSK 0x00000000
10733 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR54_FLD register field. */
10734 #define ALT_GIC_DIST_GICD_IPRIORITYR54_FLD_RESET 0x0
10735 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR54_FLD field value from a register. */
10736 #define ALT_GIC_DIST_GICD_IPRIORITYR54_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10737 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR54_FLD register field value suitable for setting the register. */
10738 #define ALT_GIC_DIST_GICD_IPRIORITYR54_FLD_SET(value) (((value) << 0) & 0xffffffff)
10739 
10740 #ifndef __ASSEMBLY__
10741 /*
10742  * WARNING: The C register and register group struct declarations are provided for
10743  * convenience and illustrative purposes. They should, however, be used with
10744  * caution as the C language standard provides no guarantees about the alignment or
10745  * atomicity of device memory accesses. The recommended practice for coding device
10746  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10747  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10748  * alt_write_dword() functions for 64 bit registers.
10749  *
10750  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR54.
10751  */
10752 struct ALT_GIC_DIST_GICD_IPRIORITYR54_s
10753 {
10754  volatile uint32_t fld : 32; /* Empty */
10755 };
10756 
10757 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR54. */
10758 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR54_s ALT_GIC_DIST_GICD_IPRIORITYR54_t;
10759 #endif /* __ASSEMBLY__ */
10760 
10761 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR54 register. */
10762 #define ALT_GIC_DIST_GICD_IPRIORITYR54_RESET 0x00000000
10763 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR54 register from the beginning of the component. */
10764 #define ALT_GIC_DIST_GICD_IPRIORITYR54_OFST 0x4d8
10765 
10766 /*
10767  * Register : GICD_IPRIORITYR55
10768  *
10769  * Interrupt Priority Registers
10770  *
10771  * Register Layout
10772  *
10773  * Bits | Access | Reset | Description
10774  * :-------|:-------|:------|:------------
10775  * [31:0] | RW | 0x0 | Empty
10776  *
10777  */
10778 /*
10779  * Field : Empty - fld
10780  *
10781  * Placeholder
10782  *
10783  * Field Access Macros:
10784  *
10785  */
10786 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR55_FLD register field. */
10787 #define ALT_GIC_DIST_GICD_IPRIORITYR55_FLD_LSB 0
10788 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR55_FLD register field. */
10789 #define ALT_GIC_DIST_GICD_IPRIORITYR55_FLD_MSB 31
10790 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR55_FLD register field. */
10791 #define ALT_GIC_DIST_GICD_IPRIORITYR55_FLD_WIDTH 32
10792 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR55_FLD register field value. */
10793 #define ALT_GIC_DIST_GICD_IPRIORITYR55_FLD_SET_MSK 0xffffffff
10794 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR55_FLD register field value. */
10795 #define ALT_GIC_DIST_GICD_IPRIORITYR55_FLD_CLR_MSK 0x00000000
10796 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR55_FLD register field. */
10797 #define ALT_GIC_DIST_GICD_IPRIORITYR55_FLD_RESET 0x0
10798 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR55_FLD field value from a register. */
10799 #define ALT_GIC_DIST_GICD_IPRIORITYR55_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10800 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR55_FLD register field value suitable for setting the register. */
10801 #define ALT_GIC_DIST_GICD_IPRIORITYR55_FLD_SET(value) (((value) << 0) & 0xffffffff)
10802 
10803 #ifndef __ASSEMBLY__
10804 /*
10805  * WARNING: The C register and register group struct declarations are provided for
10806  * convenience and illustrative purposes. They should, however, be used with
10807  * caution as the C language standard provides no guarantees about the alignment or
10808  * atomicity of device memory accesses. The recommended practice for coding device
10809  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10810  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10811  * alt_write_dword() functions for 64 bit registers.
10812  *
10813  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR55.
10814  */
10815 struct ALT_GIC_DIST_GICD_IPRIORITYR55_s
10816 {
10817  volatile uint32_t fld : 32; /* Empty */
10818 };
10819 
10820 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR55. */
10821 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR55_s ALT_GIC_DIST_GICD_IPRIORITYR55_t;
10822 #endif /* __ASSEMBLY__ */
10823 
10824 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR55 register. */
10825 #define ALT_GIC_DIST_GICD_IPRIORITYR55_RESET 0x00000000
10826 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR55 register from the beginning of the component. */
10827 #define ALT_GIC_DIST_GICD_IPRIORITYR55_OFST 0x4dc
10828 
10829 /*
10830  * Register : GICD_IPRIORITYR56
10831  *
10832  * Interrupt Priority Registers
10833  *
10834  * Register Layout
10835  *
10836  * Bits | Access | Reset | Description
10837  * :-------|:-------|:------|:------------
10838  * [31:0] | RW | 0x0 | Empty
10839  *
10840  */
10841 /*
10842  * Field : Empty - fld
10843  *
10844  * Placeholder
10845  *
10846  * Field Access Macros:
10847  *
10848  */
10849 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR56_FLD register field. */
10850 #define ALT_GIC_DIST_GICD_IPRIORITYR56_FLD_LSB 0
10851 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR56_FLD register field. */
10852 #define ALT_GIC_DIST_GICD_IPRIORITYR56_FLD_MSB 31
10853 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR56_FLD register field. */
10854 #define ALT_GIC_DIST_GICD_IPRIORITYR56_FLD_WIDTH 32
10855 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR56_FLD register field value. */
10856 #define ALT_GIC_DIST_GICD_IPRIORITYR56_FLD_SET_MSK 0xffffffff
10857 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR56_FLD register field value. */
10858 #define ALT_GIC_DIST_GICD_IPRIORITYR56_FLD_CLR_MSK 0x00000000
10859 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR56_FLD register field. */
10860 #define ALT_GIC_DIST_GICD_IPRIORITYR56_FLD_RESET 0x0
10861 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR56_FLD field value from a register. */
10862 #define ALT_GIC_DIST_GICD_IPRIORITYR56_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10863 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR56_FLD register field value suitable for setting the register. */
10864 #define ALT_GIC_DIST_GICD_IPRIORITYR56_FLD_SET(value) (((value) << 0) & 0xffffffff)
10865 
10866 #ifndef __ASSEMBLY__
10867 /*
10868  * WARNING: The C register and register group struct declarations are provided for
10869  * convenience and illustrative purposes. They should, however, be used with
10870  * caution as the C language standard provides no guarantees about the alignment or
10871  * atomicity of device memory accesses. The recommended practice for coding device
10872  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10873  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10874  * alt_write_dword() functions for 64 bit registers.
10875  *
10876  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR56.
10877  */
10878 struct ALT_GIC_DIST_GICD_IPRIORITYR56_s
10879 {
10880  volatile uint32_t fld : 32; /* Empty */
10881 };
10882 
10883 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR56. */
10884 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR56_s ALT_GIC_DIST_GICD_IPRIORITYR56_t;
10885 #endif /* __ASSEMBLY__ */
10886 
10887 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR56 register. */
10888 #define ALT_GIC_DIST_GICD_IPRIORITYR56_RESET 0x00000000
10889 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR56 register from the beginning of the component. */
10890 #define ALT_GIC_DIST_GICD_IPRIORITYR56_OFST 0x4e0
10891 
10892 /*
10893  * Register : GICD_IPRIORITYR57
10894  *
10895  * Interrupt Priority Registers
10896  *
10897  * Register Layout
10898  *
10899  * Bits | Access | Reset | Description
10900  * :-------|:-------|:------|:------------
10901  * [31:0] | RW | 0x0 | Empty
10902  *
10903  */
10904 /*
10905  * Field : Empty - fld
10906  *
10907  * Placeholder
10908  *
10909  * Field Access Macros:
10910  *
10911  */
10912 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR57_FLD register field. */
10913 #define ALT_GIC_DIST_GICD_IPRIORITYR57_FLD_LSB 0
10914 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR57_FLD register field. */
10915 #define ALT_GIC_DIST_GICD_IPRIORITYR57_FLD_MSB 31
10916 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR57_FLD register field. */
10917 #define ALT_GIC_DIST_GICD_IPRIORITYR57_FLD_WIDTH 32
10918 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR57_FLD register field value. */
10919 #define ALT_GIC_DIST_GICD_IPRIORITYR57_FLD_SET_MSK 0xffffffff
10920 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR57_FLD register field value. */
10921 #define ALT_GIC_DIST_GICD_IPRIORITYR57_FLD_CLR_MSK 0x00000000
10922 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR57_FLD register field. */
10923 #define ALT_GIC_DIST_GICD_IPRIORITYR57_FLD_RESET 0x0
10924 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR57_FLD field value from a register. */
10925 #define ALT_GIC_DIST_GICD_IPRIORITYR57_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10926 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR57_FLD register field value suitable for setting the register. */
10927 #define ALT_GIC_DIST_GICD_IPRIORITYR57_FLD_SET(value) (((value) << 0) & 0xffffffff)
10928 
10929 #ifndef __ASSEMBLY__
10930 /*
10931  * WARNING: The C register and register group struct declarations are provided for
10932  * convenience and illustrative purposes. They should, however, be used with
10933  * caution as the C language standard provides no guarantees about the alignment or
10934  * atomicity of device memory accesses. The recommended practice for coding device
10935  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10936  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10937  * alt_write_dword() functions for 64 bit registers.
10938  *
10939  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR57.
10940  */
10941 struct ALT_GIC_DIST_GICD_IPRIORITYR57_s
10942 {
10943  volatile uint32_t fld : 32; /* Empty */
10944 };
10945 
10946 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR57. */
10947 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR57_s ALT_GIC_DIST_GICD_IPRIORITYR57_t;
10948 #endif /* __ASSEMBLY__ */
10949 
10950 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR57 register. */
10951 #define ALT_GIC_DIST_GICD_IPRIORITYR57_RESET 0x00000000
10952 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR57 register from the beginning of the component. */
10953 #define ALT_GIC_DIST_GICD_IPRIORITYR57_OFST 0x4e4
10954 
10955 /*
10956  * Register : GICD_IPRIORITYR58
10957  *
10958  * Interrupt Priority Registers
10959  *
10960  * Register Layout
10961  *
10962  * Bits | Access | Reset | Description
10963  * :-------|:-------|:------|:------------
10964  * [31:0] | RW | 0x0 | Empty
10965  *
10966  */
10967 /*
10968  * Field : Empty - fld
10969  *
10970  * Placeholder
10971  *
10972  * Field Access Macros:
10973  *
10974  */
10975 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR58_FLD register field. */
10976 #define ALT_GIC_DIST_GICD_IPRIORITYR58_FLD_LSB 0
10977 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR58_FLD register field. */
10978 #define ALT_GIC_DIST_GICD_IPRIORITYR58_FLD_MSB 31
10979 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR58_FLD register field. */
10980 #define ALT_GIC_DIST_GICD_IPRIORITYR58_FLD_WIDTH 32
10981 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR58_FLD register field value. */
10982 #define ALT_GIC_DIST_GICD_IPRIORITYR58_FLD_SET_MSK 0xffffffff
10983 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR58_FLD register field value. */
10984 #define ALT_GIC_DIST_GICD_IPRIORITYR58_FLD_CLR_MSK 0x00000000
10985 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR58_FLD register field. */
10986 #define ALT_GIC_DIST_GICD_IPRIORITYR58_FLD_RESET 0x0
10987 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR58_FLD field value from a register. */
10988 #define ALT_GIC_DIST_GICD_IPRIORITYR58_FLD_GET(value) (((value) & 0xffffffff) >> 0)
10989 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR58_FLD register field value suitable for setting the register. */
10990 #define ALT_GIC_DIST_GICD_IPRIORITYR58_FLD_SET(value) (((value) << 0) & 0xffffffff)
10991 
10992 #ifndef __ASSEMBLY__
10993 /*
10994  * WARNING: The C register and register group struct declarations are provided for
10995  * convenience and illustrative purposes. They should, however, be used with
10996  * caution as the C language standard provides no guarantees about the alignment or
10997  * atomicity of device memory accesses. The recommended practice for coding device
10998  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10999  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11000  * alt_write_dword() functions for 64 bit registers.
11001  *
11002  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR58.
11003  */
11004 struct ALT_GIC_DIST_GICD_IPRIORITYR58_s
11005 {
11006  volatile uint32_t fld : 32; /* Empty */
11007 };
11008 
11009 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR58. */
11010 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR58_s ALT_GIC_DIST_GICD_IPRIORITYR58_t;
11011 #endif /* __ASSEMBLY__ */
11012 
11013 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR58 register. */
11014 #define ALT_GIC_DIST_GICD_IPRIORITYR58_RESET 0x00000000
11015 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR58 register from the beginning of the component. */
11016 #define ALT_GIC_DIST_GICD_IPRIORITYR58_OFST 0x4e8
11017 
11018 /*
11019  * Register : GICD_IPRIORITYR59
11020  *
11021  * Interrupt Priority Registers
11022  *
11023  * Register Layout
11024  *
11025  * Bits | Access | Reset | Description
11026  * :-------|:-------|:------|:------------
11027  * [31:0] | RW | 0x0 | Empty
11028  *
11029  */
11030 /*
11031  * Field : Empty - fld
11032  *
11033  * Placeholder
11034  *
11035  * Field Access Macros:
11036  *
11037  */
11038 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR59_FLD register field. */
11039 #define ALT_GIC_DIST_GICD_IPRIORITYR59_FLD_LSB 0
11040 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR59_FLD register field. */
11041 #define ALT_GIC_DIST_GICD_IPRIORITYR59_FLD_MSB 31
11042 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR59_FLD register field. */
11043 #define ALT_GIC_DIST_GICD_IPRIORITYR59_FLD_WIDTH 32
11044 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR59_FLD register field value. */
11045 #define ALT_GIC_DIST_GICD_IPRIORITYR59_FLD_SET_MSK 0xffffffff
11046 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR59_FLD register field value. */
11047 #define ALT_GIC_DIST_GICD_IPRIORITYR59_FLD_CLR_MSK 0x00000000
11048 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR59_FLD register field. */
11049 #define ALT_GIC_DIST_GICD_IPRIORITYR59_FLD_RESET 0x0
11050 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR59_FLD field value from a register. */
11051 #define ALT_GIC_DIST_GICD_IPRIORITYR59_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11052 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR59_FLD register field value suitable for setting the register. */
11053 #define ALT_GIC_DIST_GICD_IPRIORITYR59_FLD_SET(value) (((value) << 0) & 0xffffffff)
11054 
11055 #ifndef __ASSEMBLY__
11056 /*
11057  * WARNING: The C register and register group struct declarations are provided for
11058  * convenience and illustrative purposes. They should, however, be used with
11059  * caution as the C language standard provides no guarantees about the alignment or
11060  * atomicity of device memory accesses. The recommended practice for coding device
11061  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11062  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11063  * alt_write_dword() functions for 64 bit registers.
11064  *
11065  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR59.
11066  */
11067 struct ALT_GIC_DIST_GICD_IPRIORITYR59_s
11068 {
11069  volatile uint32_t fld : 32; /* Empty */
11070 };
11071 
11072 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR59. */
11073 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR59_s ALT_GIC_DIST_GICD_IPRIORITYR59_t;
11074 #endif /* __ASSEMBLY__ */
11075 
11076 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR59 register. */
11077 #define ALT_GIC_DIST_GICD_IPRIORITYR59_RESET 0x00000000
11078 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR59 register from the beginning of the component. */
11079 #define ALT_GIC_DIST_GICD_IPRIORITYR59_OFST 0x4ec
11080 
11081 /*
11082  * Register : GICD_IPRIORITYR60
11083  *
11084  * Interrupt Priority Registers
11085  *
11086  * Register Layout
11087  *
11088  * Bits | Access | Reset | Description
11089  * :-------|:-------|:------|:------------
11090  * [31:0] | RW | 0x0 | Empty
11091  *
11092  */
11093 /*
11094  * Field : Empty - fld
11095  *
11096  * Placeholder
11097  *
11098  * Field Access Macros:
11099  *
11100  */
11101 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR60_FLD register field. */
11102 #define ALT_GIC_DIST_GICD_IPRIORITYR60_FLD_LSB 0
11103 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR60_FLD register field. */
11104 #define ALT_GIC_DIST_GICD_IPRIORITYR60_FLD_MSB 31
11105 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR60_FLD register field. */
11106 #define ALT_GIC_DIST_GICD_IPRIORITYR60_FLD_WIDTH 32
11107 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR60_FLD register field value. */
11108 #define ALT_GIC_DIST_GICD_IPRIORITYR60_FLD_SET_MSK 0xffffffff
11109 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR60_FLD register field value. */
11110 #define ALT_GIC_DIST_GICD_IPRIORITYR60_FLD_CLR_MSK 0x00000000
11111 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR60_FLD register field. */
11112 #define ALT_GIC_DIST_GICD_IPRIORITYR60_FLD_RESET 0x0
11113 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR60_FLD field value from a register. */
11114 #define ALT_GIC_DIST_GICD_IPRIORITYR60_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11115 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR60_FLD register field value suitable for setting the register. */
11116 #define ALT_GIC_DIST_GICD_IPRIORITYR60_FLD_SET(value) (((value) << 0) & 0xffffffff)
11117 
11118 #ifndef __ASSEMBLY__
11119 /*
11120  * WARNING: The C register and register group struct declarations are provided for
11121  * convenience and illustrative purposes. They should, however, be used with
11122  * caution as the C language standard provides no guarantees about the alignment or
11123  * atomicity of device memory accesses. The recommended practice for coding device
11124  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11125  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11126  * alt_write_dword() functions for 64 bit registers.
11127  *
11128  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR60.
11129  */
11130 struct ALT_GIC_DIST_GICD_IPRIORITYR60_s
11131 {
11132  volatile uint32_t fld : 32; /* Empty */
11133 };
11134 
11135 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR60. */
11136 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR60_s ALT_GIC_DIST_GICD_IPRIORITYR60_t;
11137 #endif /* __ASSEMBLY__ */
11138 
11139 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR60 register. */
11140 #define ALT_GIC_DIST_GICD_IPRIORITYR60_RESET 0x00000000
11141 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR60 register from the beginning of the component. */
11142 #define ALT_GIC_DIST_GICD_IPRIORITYR60_OFST 0x4f0
11143 
11144 /*
11145  * Register : GICD_IPRIORITYR61
11146  *
11147  * Interrupt Priority Registers
11148  *
11149  * Register Layout
11150  *
11151  * Bits | Access | Reset | Description
11152  * :-------|:-------|:------|:------------
11153  * [31:0] | RW | 0x0 | Empty
11154  *
11155  */
11156 /*
11157  * Field : Empty - fld
11158  *
11159  * Placeholder
11160  *
11161  * Field Access Macros:
11162  *
11163  */
11164 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR61_FLD register field. */
11165 #define ALT_GIC_DIST_GICD_IPRIORITYR61_FLD_LSB 0
11166 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR61_FLD register field. */
11167 #define ALT_GIC_DIST_GICD_IPRIORITYR61_FLD_MSB 31
11168 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR61_FLD register field. */
11169 #define ALT_GIC_DIST_GICD_IPRIORITYR61_FLD_WIDTH 32
11170 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR61_FLD register field value. */
11171 #define ALT_GIC_DIST_GICD_IPRIORITYR61_FLD_SET_MSK 0xffffffff
11172 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR61_FLD register field value. */
11173 #define ALT_GIC_DIST_GICD_IPRIORITYR61_FLD_CLR_MSK 0x00000000
11174 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR61_FLD register field. */
11175 #define ALT_GIC_DIST_GICD_IPRIORITYR61_FLD_RESET 0x0
11176 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR61_FLD field value from a register. */
11177 #define ALT_GIC_DIST_GICD_IPRIORITYR61_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11178 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR61_FLD register field value suitable for setting the register. */
11179 #define ALT_GIC_DIST_GICD_IPRIORITYR61_FLD_SET(value) (((value) << 0) & 0xffffffff)
11180 
11181 #ifndef __ASSEMBLY__
11182 /*
11183  * WARNING: The C register and register group struct declarations are provided for
11184  * convenience and illustrative purposes. They should, however, be used with
11185  * caution as the C language standard provides no guarantees about the alignment or
11186  * atomicity of device memory accesses. The recommended practice for coding device
11187  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11188  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11189  * alt_write_dword() functions for 64 bit registers.
11190  *
11191  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR61.
11192  */
11193 struct ALT_GIC_DIST_GICD_IPRIORITYR61_s
11194 {
11195  volatile uint32_t fld : 32; /* Empty */
11196 };
11197 
11198 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR61. */
11199 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR61_s ALT_GIC_DIST_GICD_IPRIORITYR61_t;
11200 #endif /* __ASSEMBLY__ */
11201 
11202 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR61 register. */
11203 #define ALT_GIC_DIST_GICD_IPRIORITYR61_RESET 0x00000000
11204 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR61 register from the beginning of the component. */
11205 #define ALT_GIC_DIST_GICD_IPRIORITYR61_OFST 0x4f4
11206 
11207 /*
11208  * Register : GICD_IPRIORITYR62
11209  *
11210  * Interrupt Priority Registers
11211  *
11212  * Register Layout
11213  *
11214  * Bits | Access | Reset | Description
11215  * :-------|:-------|:------|:------------
11216  * [31:0] | RW | 0x0 | Empty
11217  *
11218  */
11219 /*
11220  * Field : Empty - fld
11221  *
11222  * Placeholder
11223  *
11224  * Field Access Macros:
11225  *
11226  */
11227 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR62_FLD register field. */
11228 #define ALT_GIC_DIST_GICD_IPRIORITYR62_FLD_LSB 0
11229 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR62_FLD register field. */
11230 #define ALT_GIC_DIST_GICD_IPRIORITYR62_FLD_MSB 31
11231 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR62_FLD register field. */
11232 #define ALT_GIC_DIST_GICD_IPRIORITYR62_FLD_WIDTH 32
11233 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR62_FLD register field value. */
11234 #define ALT_GIC_DIST_GICD_IPRIORITYR62_FLD_SET_MSK 0xffffffff
11235 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR62_FLD register field value. */
11236 #define ALT_GIC_DIST_GICD_IPRIORITYR62_FLD_CLR_MSK 0x00000000
11237 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR62_FLD register field. */
11238 #define ALT_GIC_DIST_GICD_IPRIORITYR62_FLD_RESET 0x0
11239 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR62_FLD field value from a register. */
11240 #define ALT_GIC_DIST_GICD_IPRIORITYR62_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11241 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR62_FLD register field value suitable for setting the register. */
11242 #define ALT_GIC_DIST_GICD_IPRIORITYR62_FLD_SET(value) (((value) << 0) & 0xffffffff)
11243 
11244 #ifndef __ASSEMBLY__
11245 /*
11246  * WARNING: The C register and register group struct declarations are provided for
11247  * convenience and illustrative purposes. They should, however, be used with
11248  * caution as the C language standard provides no guarantees about the alignment or
11249  * atomicity of device memory accesses. The recommended practice for coding device
11250  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11251  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11252  * alt_write_dword() functions for 64 bit registers.
11253  *
11254  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR62.
11255  */
11256 struct ALT_GIC_DIST_GICD_IPRIORITYR62_s
11257 {
11258  volatile uint32_t fld : 32; /* Empty */
11259 };
11260 
11261 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR62. */
11262 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR62_s ALT_GIC_DIST_GICD_IPRIORITYR62_t;
11263 #endif /* __ASSEMBLY__ */
11264 
11265 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR62 register. */
11266 #define ALT_GIC_DIST_GICD_IPRIORITYR62_RESET 0x00000000
11267 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR62 register from the beginning of the component. */
11268 #define ALT_GIC_DIST_GICD_IPRIORITYR62_OFST 0x4f8
11269 
11270 /*
11271  * Register : GICD_IPRIORITYR63
11272  *
11273  * Interrupt Priority Registers
11274  *
11275  * Register Layout
11276  *
11277  * Bits | Access | Reset | Description
11278  * :-------|:-------|:------|:------------
11279  * [31:0] | RW | 0x0 | Empty
11280  *
11281  */
11282 /*
11283  * Field : Empty - fld
11284  *
11285  * Placeholder
11286  *
11287  * Field Access Macros:
11288  *
11289  */
11290 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR63_FLD register field. */
11291 #define ALT_GIC_DIST_GICD_IPRIORITYR63_FLD_LSB 0
11292 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR63_FLD register field. */
11293 #define ALT_GIC_DIST_GICD_IPRIORITYR63_FLD_MSB 31
11294 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR63_FLD register field. */
11295 #define ALT_GIC_DIST_GICD_IPRIORITYR63_FLD_WIDTH 32
11296 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR63_FLD register field value. */
11297 #define ALT_GIC_DIST_GICD_IPRIORITYR63_FLD_SET_MSK 0xffffffff
11298 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR63_FLD register field value. */
11299 #define ALT_GIC_DIST_GICD_IPRIORITYR63_FLD_CLR_MSK 0x00000000
11300 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR63_FLD register field. */
11301 #define ALT_GIC_DIST_GICD_IPRIORITYR63_FLD_RESET 0x0
11302 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR63_FLD field value from a register. */
11303 #define ALT_GIC_DIST_GICD_IPRIORITYR63_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11304 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR63_FLD register field value suitable for setting the register. */
11305 #define ALT_GIC_DIST_GICD_IPRIORITYR63_FLD_SET(value) (((value) << 0) & 0xffffffff)
11306 
11307 #ifndef __ASSEMBLY__
11308 /*
11309  * WARNING: The C register and register group struct declarations are provided for
11310  * convenience and illustrative purposes. They should, however, be used with
11311  * caution as the C language standard provides no guarantees about the alignment or
11312  * atomicity of device memory accesses. The recommended practice for coding device
11313  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11314  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11315  * alt_write_dword() functions for 64 bit registers.
11316  *
11317  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR63.
11318  */
11319 struct ALT_GIC_DIST_GICD_IPRIORITYR63_s
11320 {
11321  volatile uint32_t fld : 32; /* Empty */
11322 };
11323 
11324 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR63. */
11325 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR63_s ALT_GIC_DIST_GICD_IPRIORITYR63_t;
11326 #endif /* __ASSEMBLY__ */
11327 
11328 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR63 register. */
11329 #define ALT_GIC_DIST_GICD_IPRIORITYR63_RESET 0x00000000
11330 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR63 register from the beginning of the component. */
11331 #define ALT_GIC_DIST_GICD_IPRIORITYR63_OFST 0x4fc
11332 
11333 /*
11334  * Register : GICD_IPRIORITYR64
11335  *
11336  * Interrupt Priority Registers
11337  *
11338  * Register Layout
11339  *
11340  * Bits | Access | Reset | Description
11341  * :-------|:-------|:------|:------------
11342  * [31:0] | RW | 0x0 | Empty
11343  *
11344  */
11345 /*
11346  * Field : Empty - fld
11347  *
11348  * Placeholder
11349  *
11350  * Field Access Macros:
11351  *
11352  */
11353 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR64_FLD register field. */
11354 #define ALT_GIC_DIST_GICD_IPRIORITYR64_FLD_LSB 0
11355 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR64_FLD register field. */
11356 #define ALT_GIC_DIST_GICD_IPRIORITYR64_FLD_MSB 31
11357 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR64_FLD register field. */
11358 #define ALT_GIC_DIST_GICD_IPRIORITYR64_FLD_WIDTH 32
11359 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR64_FLD register field value. */
11360 #define ALT_GIC_DIST_GICD_IPRIORITYR64_FLD_SET_MSK 0xffffffff
11361 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR64_FLD register field value. */
11362 #define ALT_GIC_DIST_GICD_IPRIORITYR64_FLD_CLR_MSK 0x00000000
11363 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR64_FLD register field. */
11364 #define ALT_GIC_DIST_GICD_IPRIORITYR64_FLD_RESET 0x0
11365 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR64_FLD field value from a register. */
11366 #define ALT_GIC_DIST_GICD_IPRIORITYR64_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11367 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR64_FLD register field value suitable for setting the register. */
11368 #define ALT_GIC_DIST_GICD_IPRIORITYR64_FLD_SET(value) (((value) << 0) & 0xffffffff)
11369 
11370 #ifndef __ASSEMBLY__
11371 /*
11372  * WARNING: The C register and register group struct declarations are provided for
11373  * convenience and illustrative purposes. They should, however, be used with
11374  * caution as the C language standard provides no guarantees about the alignment or
11375  * atomicity of device memory accesses. The recommended practice for coding device
11376  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11377  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11378  * alt_write_dword() functions for 64 bit registers.
11379  *
11380  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR64.
11381  */
11382 struct ALT_GIC_DIST_GICD_IPRIORITYR64_s
11383 {
11384  volatile uint32_t fld : 32; /* Empty */
11385 };
11386 
11387 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR64. */
11388 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR64_s ALT_GIC_DIST_GICD_IPRIORITYR64_t;
11389 #endif /* __ASSEMBLY__ */
11390 
11391 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR64 register. */
11392 #define ALT_GIC_DIST_GICD_IPRIORITYR64_RESET 0x00000000
11393 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR64 register from the beginning of the component. */
11394 #define ALT_GIC_DIST_GICD_IPRIORITYR64_OFST 0x500
11395 
11396 /*
11397  * Register : GICD_IPRIORITYR65
11398  *
11399  * Interrupt Priority Registers
11400  *
11401  * Register Layout
11402  *
11403  * Bits | Access | Reset | Description
11404  * :-------|:-------|:------|:------------
11405  * [31:0] | RW | 0x0 | Empty
11406  *
11407  */
11408 /*
11409  * Field : Empty - fld
11410  *
11411  * Placeholder
11412  *
11413  * Field Access Macros:
11414  *
11415  */
11416 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR65_FLD register field. */
11417 #define ALT_GIC_DIST_GICD_IPRIORITYR65_FLD_LSB 0
11418 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR65_FLD register field. */
11419 #define ALT_GIC_DIST_GICD_IPRIORITYR65_FLD_MSB 31
11420 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR65_FLD register field. */
11421 #define ALT_GIC_DIST_GICD_IPRIORITYR65_FLD_WIDTH 32
11422 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR65_FLD register field value. */
11423 #define ALT_GIC_DIST_GICD_IPRIORITYR65_FLD_SET_MSK 0xffffffff
11424 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR65_FLD register field value. */
11425 #define ALT_GIC_DIST_GICD_IPRIORITYR65_FLD_CLR_MSK 0x00000000
11426 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR65_FLD register field. */
11427 #define ALT_GIC_DIST_GICD_IPRIORITYR65_FLD_RESET 0x0
11428 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR65_FLD field value from a register. */
11429 #define ALT_GIC_DIST_GICD_IPRIORITYR65_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11430 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR65_FLD register field value suitable for setting the register. */
11431 #define ALT_GIC_DIST_GICD_IPRIORITYR65_FLD_SET(value) (((value) << 0) & 0xffffffff)
11432 
11433 #ifndef __ASSEMBLY__
11434 /*
11435  * WARNING: The C register and register group struct declarations are provided for
11436  * convenience and illustrative purposes. They should, however, be used with
11437  * caution as the C language standard provides no guarantees about the alignment or
11438  * atomicity of device memory accesses. The recommended practice for coding device
11439  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11440  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11441  * alt_write_dword() functions for 64 bit registers.
11442  *
11443  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR65.
11444  */
11445 struct ALT_GIC_DIST_GICD_IPRIORITYR65_s
11446 {
11447  volatile uint32_t fld : 32; /* Empty */
11448 };
11449 
11450 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR65. */
11451 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR65_s ALT_GIC_DIST_GICD_IPRIORITYR65_t;
11452 #endif /* __ASSEMBLY__ */
11453 
11454 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR65 register. */
11455 #define ALT_GIC_DIST_GICD_IPRIORITYR65_RESET 0x00000000
11456 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR65 register from the beginning of the component. */
11457 #define ALT_GIC_DIST_GICD_IPRIORITYR65_OFST 0x504
11458 
11459 /*
11460  * Register : GICD_IPRIORITYR66
11461  *
11462  * Interrupt Priority Registers
11463  *
11464  * Register Layout
11465  *
11466  * Bits | Access | Reset | Description
11467  * :-------|:-------|:------|:------------
11468  * [31:0] | RW | 0x0 | Empty
11469  *
11470  */
11471 /*
11472  * Field : Empty - fld
11473  *
11474  * Placeholder
11475  *
11476  * Field Access Macros:
11477  *
11478  */
11479 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR66_FLD register field. */
11480 #define ALT_GIC_DIST_GICD_IPRIORITYR66_FLD_LSB 0
11481 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR66_FLD register field. */
11482 #define ALT_GIC_DIST_GICD_IPRIORITYR66_FLD_MSB 31
11483 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR66_FLD register field. */
11484 #define ALT_GIC_DIST_GICD_IPRIORITYR66_FLD_WIDTH 32
11485 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR66_FLD register field value. */
11486 #define ALT_GIC_DIST_GICD_IPRIORITYR66_FLD_SET_MSK 0xffffffff
11487 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR66_FLD register field value. */
11488 #define ALT_GIC_DIST_GICD_IPRIORITYR66_FLD_CLR_MSK 0x00000000
11489 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR66_FLD register field. */
11490 #define ALT_GIC_DIST_GICD_IPRIORITYR66_FLD_RESET 0x0
11491 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR66_FLD field value from a register. */
11492 #define ALT_GIC_DIST_GICD_IPRIORITYR66_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11493 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR66_FLD register field value suitable for setting the register. */
11494 #define ALT_GIC_DIST_GICD_IPRIORITYR66_FLD_SET(value) (((value) << 0) & 0xffffffff)
11495 
11496 #ifndef __ASSEMBLY__
11497 /*
11498  * WARNING: The C register and register group struct declarations are provided for
11499  * convenience and illustrative purposes. They should, however, be used with
11500  * caution as the C language standard provides no guarantees about the alignment or
11501  * atomicity of device memory accesses. The recommended practice for coding device
11502  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11503  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11504  * alt_write_dword() functions for 64 bit registers.
11505  *
11506  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR66.
11507  */
11508 struct ALT_GIC_DIST_GICD_IPRIORITYR66_s
11509 {
11510  volatile uint32_t fld : 32; /* Empty */
11511 };
11512 
11513 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR66. */
11514 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR66_s ALT_GIC_DIST_GICD_IPRIORITYR66_t;
11515 #endif /* __ASSEMBLY__ */
11516 
11517 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR66 register. */
11518 #define ALT_GIC_DIST_GICD_IPRIORITYR66_RESET 0x00000000
11519 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR66 register from the beginning of the component. */
11520 #define ALT_GIC_DIST_GICD_IPRIORITYR66_OFST 0x508
11521 
11522 /*
11523  * Register : GICD_IPRIORITYR67
11524  *
11525  * Interrupt Priority Registers
11526  *
11527  * Register Layout
11528  *
11529  * Bits | Access | Reset | Description
11530  * :-------|:-------|:------|:------------
11531  * [31:0] | RW | 0x0 | Empty
11532  *
11533  */
11534 /*
11535  * Field : Empty - fld
11536  *
11537  * Placeholder
11538  *
11539  * Field Access Macros:
11540  *
11541  */
11542 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR67_FLD register field. */
11543 #define ALT_GIC_DIST_GICD_IPRIORITYR67_FLD_LSB 0
11544 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR67_FLD register field. */
11545 #define ALT_GIC_DIST_GICD_IPRIORITYR67_FLD_MSB 31
11546 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR67_FLD register field. */
11547 #define ALT_GIC_DIST_GICD_IPRIORITYR67_FLD_WIDTH 32
11548 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR67_FLD register field value. */
11549 #define ALT_GIC_DIST_GICD_IPRIORITYR67_FLD_SET_MSK 0xffffffff
11550 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR67_FLD register field value. */
11551 #define ALT_GIC_DIST_GICD_IPRIORITYR67_FLD_CLR_MSK 0x00000000
11552 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR67_FLD register field. */
11553 #define ALT_GIC_DIST_GICD_IPRIORITYR67_FLD_RESET 0x0
11554 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR67_FLD field value from a register. */
11555 #define ALT_GIC_DIST_GICD_IPRIORITYR67_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11556 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR67_FLD register field value suitable for setting the register. */
11557 #define ALT_GIC_DIST_GICD_IPRIORITYR67_FLD_SET(value) (((value) << 0) & 0xffffffff)
11558 
11559 #ifndef __ASSEMBLY__
11560 /*
11561  * WARNING: The C register and register group struct declarations are provided for
11562  * convenience and illustrative purposes. They should, however, be used with
11563  * caution as the C language standard provides no guarantees about the alignment or
11564  * atomicity of device memory accesses. The recommended practice for coding device
11565  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11566  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11567  * alt_write_dword() functions for 64 bit registers.
11568  *
11569  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR67.
11570  */
11571 struct ALT_GIC_DIST_GICD_IPRIORITYR67_s
11572 {
11573  volatile uint32_t fld : 32; /* Empty */
11574 };
11575 
11576 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR67. */
11577 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR67_s ALT_GIC_DIST_GICD_IPRIORITYR67_t;
11578 #endif /* __ASSEMBLY__ */
11579 
11580 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR67 register. */
11581 #define ALT_GIC_DIST_GICD_IPRIORITYR67_RESET 0x00000000
11582 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR67 register from the beginning of the component. */
11583 #define ALT_GIC_DIST_GICD_IPRIORITYR67_OFST 0x50c
11584 
11585 /*
11586  * Register : GICD_IPRIORITYR68
11587  *
11588  * Interrupt Priority Registers
11589  *
11590  * Register Layout
11591  *
11592  * Bits | Access | Reset | Description
11593  * :-------|:-------|:------|:------------
11594  * [31:0] | RW | 0x0 | Empty
11595  *
11596  */
11597 /*
11598  * Field : Empty - fld
11599  *
11600  * Placeholder
11601  *
11602  * Field Access Macros:
11603  *
11604  */
11605 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR68_FLD register field. */
11606 #define ALT_GIC_DIST_GICD_IPRIORITYR68_FLD_LSB 0
11607 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR68_FLD register field. */
11608 #define ALT_GIC_DIST_GICD_IPRIORITYR68_FLD_MSB 31
11609 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR68_FLD register field. */
11610 #define ALT_GIC_DIST_GICD_IPRIORITYR68_FLD_WIDTH 32
11611 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR68_FLD register field value. */
11612 #define ALT_GIC_DIST_GICD_IPRIORITYR68_FLD_SET_MSK 0xffffffff
11613 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR68_FLD register field value. */
11614 #define ALT_GIC_DIST_GICD_IPRIORITYR68_FLD_CLR_MSK 0x00000000
11615 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR68_FLD register field. */
11616 #define ALT_GIC_DIST_GICD_IPRIORITYR68_FLD_RESET 0x0
11617 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR68_FLD field value from a register. */
11618 #define ALT_GIC_DIST_GICD_IPRIORITYR68_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11619 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR68_FLD register field value suitable for setting the register. */
11620 #define ALT_GIC_DIST_GICD_IPRIORITYR68_FLD_SET(value) (((value) << 0) & 0xffffffff)
11621 
11622 #ifndef __ASSEMBLY__
11623 /*
11624  * WARNING: The C register and register group struct declarations are provided for
11625  * convenience and illustrative purposes. They should, however, be used with
11626  * caution as the C language standard provides no guarantees about the alignment or
11627  * atomicity of device memory accesses. The recommended practice for coding device
11628  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11629  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11630  * alt_write_dword() functions for 64 bit registers.
11631  *
11632  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR68.
11633  */
11634 struct ALT_GIC_DIST_GICD_IPRIORITYR68_s
11635 {
11636  volatile uint32_t fld : 32; /* Empty */
11637 };
11638 
11639 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR68. */
11640 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR68_s ALT_GIC_DIST_GICD_IPRIORITYR68_t;
11641 #endif /* __ASSEMBLY__ */
11642 
11643 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR68 register. */
11644 #define ALT_GIC_DIST_GICD_IPRIORITYR68_RESET 0x00000000
11645 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR68 register from the beginning of the component. */
11646 #define ALT_GIC_DIST_GICD_IPRIORITYR68_OFST 0x510
11647 
11648 /*
11649  * Register : GICD_IPRIORITYR69
11650  *
11651  * Interrupt Priority Registers
11652  *
11653  * Register Layout
11654  *
11655  * Bits | Access | Reset | Description
11656  * :-------|:-------|:------|:------------
11657  * [31:0] | RW | 0x0 | Empty
11658  *
11659  */
11660 /*
11661  * Field : Empty - fld
11662  *
11663  * Placeholder
11664  *
11665  * Field Access Macros:
11666  *
11667  */
11668 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR69_FLD register field. */
11669 #define ALT_GIC_DIST_GICD_IPRIORITYR69_FLD_LSB 0
11670 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR69_FLD register field. */
11671 #define ALT_GIC_DIST_GICD_IPRIORITYR69_FLD_MSB 31
11672 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR69_FLD register field. */
11673 #define ALT_GIC_DIST_GICD_IPRIORITYR69_FLD_WIDTH 32
11674 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR69_FLD register field value. */
11675 #define ALT_GIC_DIST_GICD_IPRIORITYR69_FLD_SET_MSK 0xffffffff
11676 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR69_FLD register field value. */
11677 #define ALT_GIC_DIST_GICD_IPRIORITYR69_FLD_CLR_MSK 0x00000000
11678 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR69_FLD register field. */
11679 #define ALT_GIC_DIST_GICD_IPRIORITYR69_FLD_RESET 0x0
11680 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR69_FLD field value from a register. */
11681 #define ALT_GIC_DIST_GICD_IPRIORITYR69_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11682 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR69_FLD register field value suitable for setting the register. */
11683 #define ALT_GIC_DIST_GICD_IPRIORITYR69_FLD_SET(value) (((value) << 0) & 0xffffffff)
11684 
11685 #ifndef __ASSEMBLY__
11686 /*
11687  * WARNING: The C register and register group struct declarations are provided for
11688  * convenience and illustrative purposes. They should, however, be used with
11689  * caution as the C language standard provides no guarantees about the alignment or
11690  * atomicity of device memory accesses. The recommended practice for coding device
11691  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11692  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11693  * alt_write_dword() functions for 64 bit registers.
11694  *
11695  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR69.
11696  */
11697 struct ALT_GIC_DIST_GICD_IPRIORITYR69_s
11698 {
11699  volatile uint32_t fld : 32; /* Empty */
11700 };
11701 
11702 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR69. */
11703 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR69_s ALT_GIC_DIST_GICD_IPRIORITYR69_t;
11704 #endif /* __ASSEMBLY__ */
11705 
11706 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR69 register. */
11707 #define ALT_GIC_DIST_GICD_IPRIORITYR69_RESET 0x00000000
11708 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR69 register from the beginning of the component. */
11709 #define ALT_GIC_DIST_GICD_IPRIORITYR69_OFST 0x514
11710 
11711 /*
11712  * Register : GICD_IPRIORITYR70
11713  *
11714  * Interrupt Priority Registers
11715  *
11716  * Register Layout
11717  *
11718  * Bits | Access | Reset | Description
11719  * :-------|:-------|:------|:------------
11720  * [31:0] | RW | 0x0 | Empty
11721  *
11722  */
11723 /*
11724  * Field : Empty - fld
11725  *
11726  * Placeholder
11727  *
11728  * Field Access Macros:
11729  *
11730  */
11731 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR70_FLD register field. */
11732 #define ALT_GIC_DIST_GICD_IPRIORITYR70_FLD_LSB 0
11733 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR70_FLD register field. */
11734 #define ALT_GIC_DIST_GICD_IPRIORITYR70_FLD_MSB 31
11735 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR70_FLD register field. */
11736 #define ALT_GIC_DIST_GICD_IPRIORITYR70_FLD_WIDTH 32
11737 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR70_FLD register field value. */
11738 #define ALT_GIC_DIST_GICD_IPRIORITYR70_FLD_SET_MSK 0xffffffff
11739 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR70_FLD register field value. */
11740 #define ALT_GIC_DIST_GICD_IPRIORITYR70_FLD_CLR_MSK 0x00000000
11741 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR70_FLD register field. */
11742 #define ALT_GIC_DIST_GICD_IPRIORITYR70_FLD_RESET 0x0
11743 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR70_FLD field value from a register. */
11744 #define ALT_GIC_DIST_GICD_IPRIORITYR70_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11745 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR70_FLD register field value suitable for setting the register. */
11746 #define ALT_GIC_DIST_GICD_IPRIORITYR70_FLD_SET(value) (((value) << 0) & 0xffffffff)
11747 
11748 #ifndef __ASSEMBLY__
11749 /*
11750  * WARNING: The C register and register group struct declarations are provided for
11751  * convenience and illustrative purposes. They should, however, be used with
11752  * caution as the C language standard provides no guarantees about the alignment or
11753  * atomicity of device memory accesses. The recommended practice for coding device
11754  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11755  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11756  * alt_write_dword() functions for 64 bit registers.
11757  *
11758  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR70.
11759  */
11760 struct ALT_GIC_DIST_GICD_IPRIORITYR70_s
11761 {
11762  volatile uint32_t fld : 32; /* Empty */
11763 };
11764 
11765 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR70. */
11766 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR70_s ALT_GIC_DIST_GICD_IPRIORITYR70_t;
11767 #endif /* __ASSEMBLY__ */
11768 
11769 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR70 register. */
11770 #define ALT_GIC_DIST_GICD_IPRIORITYR70_RESET 0x00000000
11771 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR70 register from the beginning of the component. */
11772 #define ALT_GIC_DIST_GICD_IPRIORITYR70_OFST 0x518
11773 
11774 /*
11775  * Register : GICD_IPRIORITYR71
11776  *
11777  * Interrupt Priority Registers
11778  *
11779  * Register Layout
11780  *
11781  * Bits | Access | Reset | Description
11782  * :-------|:-------|:------|:------------
11783  * [31:0] | RW | 0x0 | Empty
11784  *
11785  */
11786 /*
11787  * Field : Empty - fld
11788  *
11789  * Placeholder
11790  *
11791  * Field Access Macros:
11792  *
11793  */
11794 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR71_FLD register field. */
11795 #define ALT_GIC_DIST_GICD_IPRIORITYR71_FLD_LSB 0
11796 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR71_FLD register field. */
11797 #define ALT_GIC_DIST_GICD_IPRIORITYR71_FLD_MSB 31
11798 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR71_FLD register field. */
11799 #define ALT_GIC_DIST_GICD_IPRIORITYR71_FLD_WIDTH 32
11800 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR71_FLD register field value. */
11801 #define ALT_GIC_DIST_GICD_IPRIORITYR71_FLD_SET_MSK 0xffffffff
11802 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR71_FLD register field value. */
11803 #define ALT_GIC_DIST_GICD_IPRIORITYR71_FLD_CLR_MSK 0x00000000
11804 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR71_FLD register field. */
11805 #define ALT_GIC_DIST_GICD_IPRIORITYR71_FLD_RESET 0x0
11806 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR71_FLD field value from a register. */
11807 #define ALT_GIC_DIST_GICD_IPRIORITYR71_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11808 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR71_FLD register field value suitable for setting the register. */
11809 #define ALT_GIC_DIST_GICD_IPRIORITYR71_FLD_SET(value) (((value) << 0) & 0xffffffff)
11810 
11811 #ifndef __ASSEMBLY__
11812 /*
11813  * WARNING: The C register and register group struct declarations are provided for
11814  * convenience and illustrative purposes. They should, however, be used with
11815  * caution as the C language standard provides no guarantees about the alignment or
11816  * atomicity of device memory accesses. The recommended practice for coding device
11817  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11818  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11819  * alt_write_dword() functions for 64 bit registers.
11820  *
11821  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR71.
11822  */
11823 struct ALT_GIC_DIST_GICD_IPRIORITYR71_s
11824 {
11825  volatile uint32_t fld : 32; /* Empty */
11826 };
11827 
11828 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR71. */
11829 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR71_s ALT_GIC_DIST_GICD_IPRIORITYR71_t;
11830 #endif /* __ASSEMBLY__ */
11831 
11832 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR71 register. */
11833 #define ALT_GIC_DIST_GICD_IPRIORITYR71_RESET 0x00000000
11834 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR71 register from the beginning of the component. */
11835 #define ALT_GIC_DIST_GICD_IPRIORITYR71_OFST 0x51c
11836 
11837 /*
11838  * Register : GICD_IPRIORITYR72
11839  *
11840  * Interrupt Priority Registers
11841  *
11842  * Register Layout
11843  *
11844  * Bits | Access | Reset | Description
11845  * :-------|:-------|:------|:------------
11846  * [31:0] | RW | 0x0 | Empty
11847  *
11848  */
11849 /*
11850  * Field : Empty - fld
11851  *
11852  * Placeholder
11853  *
11854  * Field Access Macros:
11855  *
11856  */
11857 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR72_FLD register field. */
11858 #define ALT_GIC_DIST_GICD_IPRIORITYR72_FLD_LSB 0
11859 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR72_FLD register field. */
11860 #define ALT_GIC_DIST_GICD_IPRIORITYR72_FLD_MSB 31
11861 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR72_FLD register field. */
11862 #define ALT_GIC_DIST_GICD_IPRIORITYR72_FLD_WIDTH 32
11863 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR72_FLD register field value. */
11864 #define ALT_GIC_DIST_GICD_IPRIORITYR72_FLD_SET_MSK 0xffffffff
11865 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR72_FLD register field value. */
11866 #define ALT_GIC_DIST_GICD_IPRIORITYR72_FLD_CLR_MSK 0x00000000
11867 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR72_FLD register field. */
11868 #define ALT_GIC_DIST_GICD_IPRIORITYR72_FLD_RESET 0x0
11869 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR72_FLD field value from a register. */
11870 #define ALT_GIC_DIST_GICD_IPRIORITYR72_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11871 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR72_FLD register field value suitable for setting the register. */
11872 #define ALT_GIC_DIST_GICD_IPRIORITYR72_FLD_SET(value) (((value) << 0) & 0xffffffff)
11873 
11874 #ifndef __ASSEMBLY__
11875 /*
11876  * WARNING: The C register and register group struct declarations are provided for
11877  * convenience and illustrative purposes. They should, however, be used with
11878  * caution as the C language standard provides no guarantees about the alignment or
11879  * atomicity of device memory accesses. The recommended practice for coding device
11880  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11881  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11882  * alt_write_dword() functions for 64 bit registers.
11883  *
11884  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR72.
11885  */
11886 struct ALT_GIC_DIST_GICD_IPRIORITYR72_s
11887 {
11888  volatile uint32_t fld : 32; /* Empty */
11889 };
11890 
11891 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR72. */
11892 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR72_s ALT_GIC_DIST_GICD_IPRIORITYR72_t;
11893 #endif /* __ASSEMBLY__ */
11894 
11895 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR72 register. */
11896 #define ALT_GIC_DIST_GICD_IPRIORITYR72_RESET 0x00000000
11897 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR72 register from the beginning of the component. */
11898 #define ALT_GIC_DIST_GICD_IPRIORITYR72_OFST 0x520
11899 
11900 /*
11901  * Register : GICD_IPRIORITYR73
11902  *
11903  * Interrupt Priority Registers
11904  *
11905  * Register Layout
11906  *
11907  * Bits | Access | Reset | Description
11908  * :-------|:-------|:------|:------------
11909  * [31:0] | RW | 0x0 | Empty
11910  *
11911  */
11912 /*
11913  * Field : Empty - fld
11914  *
11915  * Placeholder
11916  *
11917  * Field Access Macros:
11918  *
11919  */
11920 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR73_FLD register field. */
11921 #define ALT_GIC_DIST_GICD_IPRIORITYR73_FLD_LSB 0
11922 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR73_FLD register field. */
11923 #define ALT_GIC_DIST_GICD_IPRIORITYR73_FLD_MSB 31
11924 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR73_FLD register field. */
11925 #define ALT_GIC_DIST_GICD_IPRIORITYR73_FLD_WIDTH 32
11926 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR73_FLD register field value. */
11927 #define ALT_GIC_DIST_GICD_IPRIORITYR73_FLD_SET_MSK 0xffffffff
11928 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR73_FLD register field value. */
11929 #define ALT_GIC_DIST_GICD_IPRIORITYR73_FLD_CLR_MSK 0x00000000
11930 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR73_FLD register field. */
11931 #define ALT_GIC_DIST_GICD_IPRIORITYR73_FLD_RESET 0x0
11932 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR73_FLD field value from a register. */
11933 #define ALT_GIC_DIST_GICD_IPRIORITYR73_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11934 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR73_FLD register field value suitable for setting the register. */
11935 #define ALT_GIC_DIST_GICD_IPRIORITYR73_FLD_SET(value) (((value) << 0) & 0xffffffff)
11936 
11937 #ifndef __ASSEMBLY__
11938 /*
11939  * WARNING: The C register and register group struct declarations are provided for
11940  * convenience and illustrative purposes. They should, however, be used with
11941  * caution as the C language standard provides no guarantees about the alignment or
11942  * atomicity of device memory accesses. The recommended practice for coding device
11943  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11944  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11945  * alt_write_dword() functions for 64 bit registers.
11946  *
11947  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR73.
11948  */
11949 struct ALT_GIC_DIST_GICD_IPRIORITYR73_s
11950 {
11951  volatile uint32_t fld : 32; /* Empty */
11952 };
11953 
11954 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR73. */
11955 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR73_s ALT_GIC_DIST_GICD_IPRIORITYR73_t;
11956 #endif /* __ASSEMBLY__ */
11957 
11958 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR73 register. */
11959 #define ALT_GIC_DIST_GICD_IPRIORITYR73_RESET 0x00000000
11960 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR73 register from the beginning of the component. */
11961 #define ALT_GIC_DIST_GICD_IPRIORITYR73_OFST 0x524
11962 
11963 /*
11964  * Register : GICD_IPRIORITYR74
11965  *
11966  * Interrupt Priority Registers
11967  *
11968  * Register Layout
11969  *
11970  * Bits | Access | Reset | Description
11971  * :-------|:-------|:------|:------------
11972  * [31:0] | RW | 0x0 | Empty
11973  *
11974  */
11975 /*
11976  * Field : Empty - fld
11977  *
11978  * Placeholder
11979  *
11980  * Field Access Macros:
11981  *
11982  */
11983 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR74_FLD register field. */
11984 #define ALT_GIC_DIST_GICD_IPRIORITYR74_FLD_LSB 0
11985 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR74_FLD register field. */
11986 #define ALT_GIC_DIST_GICD_IPRIORITYR74_FLD_MSB 31
11987 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR74_FLD register field. */
11988 #define ALT_GIC_DIST_GICD_IPRIORITYR74_FLD_WIDTH 32
11989 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR74_FLD register field value. */
11990 #define ALT_GIC_DIST_GICD_IPRIORITYR74_FLD_SET_MSK 0xffffffff
11991 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR74_FLD register field value. */
11992 #define ALT_GIC_DIST_GICD_IPRIORITYR74_FLD_CLR_MSK 0x00000000
11993 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR74_FLD register field. */
11994 #define ALT_GIC_DIST_GICD_IPRIORITYR74_FLD_RESET 0x0
11995 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR74_FLD field value from a register. */
11996 #define ALT_GIC_DIST_GICD_IPRIORITYR74_FLD_GET(value) (((value) & 0xffffffff) >> 0)
11997 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR74_FLD register field value suitable for setting the register. */
11998 #define ALT_GIC_DIST_GICD_IPRIORITYR74_FLD_SET(value) (((value) << 0) & 0xffffffff)
11999 
12000 #ifndef __ASSEMBLY__
12001 /*
12002  * WARNING: The C register and register group struct declarations are provided for
12003  * convenience and illustrative purposes. They should, however, be used with
12004  * caution as the C language standard provides no guarantees about the alignment or
12005  * atomicity of device memory accesses. The recommended practice for coding device
12006  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12007  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12008  * alt_write_dword() functions for 64 bit registers.
12009  *
12010  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR74.
12011  */
12012 struct ALT_GIC_DIST_GICD_IPRIORITYR74_s
12013 {
12014  volatile uint32_t fld : 32; /* Empty */
12015 };
12016 
12017 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR74. */
12018 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR74_s ALT_GIC_DIST_GICD_IPRIORITYR74_t;
12019 #endif /* __ASSEMBLY__ */
12020 
12021 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR74 register. */
12022 #define ALT_GIC_DIST_GICD_IPRIORITYR74_RESET 0x00000000
12023 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR74 register from the beginning of the component. */
12024 #define ALT_GIC_DIST_GICD_IPRIORITYR74_OFST 0x528
12025 
12026 /*
12027  * Register : GICD_IPRIORITYR75
12028  *
12029  * Interrupt Priority Registers
12030  *
12031  * Register Layout
12032  *
12033  * Bits | Access | Reset | Description
12034  * :-------|:-------|:------|:------------
12035  * [31:0] | RW | 0x0 | Empty
12036  *
12037  */
12038 /*
12039  * Field : Empty - fld
12040  *
12041  * Placeholder
12042  *
12043  * Field Access Macros:
12044  *
12045  */
12046 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR75_FLD register field. */
12047 #define ALT_GIC_DIST_GICD_IPRIORITYR75_FLD_LSB 0
12048 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR75_FLD register field. */
12049 #define ALT_GIC_DIST_GICD_IPRIORITYR75_FLD_MSB 31
12050 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR75_FLD register field. */
12051 #define ALT_GIC_DIST_GICD_IPRIORITYR75_FLD_WIDTH 32
12052 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR75_FLD register field value. */
12053 #define ALT_GIC_DIST_GICD_IPRIORITYR75_FLD_SET_MSK 0xffffffff
12054 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR75_FLD register field value. */
12055 #define ALT_GIC_DIST_GICD_IPRIORITYR75_FLD_CLR_MSK 0x00000000
12056 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR75_FLD register field. */
12057 #define ALT_GIC_DIST_GICD_IPRIORITYR75_FLD_RESET 0x0
12058 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR75_FLD field value from a register. */
12059 #define ALT_GIC_DIST_GICD_IPRIORITYR75_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12060 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR75_FLD register field value suitable for setting the register. */
12061 #define ALT_GIC_DIST_GICD_IPRIORITYR75_FLD_SET(value) (((value) << 0) & 0xffffffff)
12062 
12063 #ifndef __ASSEMBLY__
12064 /*
12065  * WARNING: The C register and register group struct declarations are provided for
12066  * convenience and illustrative purposes. They should, however, be used with
12067  * caution as the C language standard provides no guarantees about the alignment or
12068  * atomicity of device memory accesses. The recommended practice for coding device
12069  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12070  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12071  * alt_write_dword() functions for 64 bit registers.
12072  *
12073  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR75.
12074  */
12075 struct ALT_GIC_DIST_GICD_IPRIORITYR75_s
12076 {
12077  volatile uint32_t fld : 32; /* Empty */
12078 };
12079 
12080 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR75. */
12081 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR75_s ALT_GIC_DIST_GICD_IPRIORITYR75_t;
12082 #endif /* __ASSEMBLY__ */
12083 
12084 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR75 register. */
12085 #define ALT_GIC_DIST_GICD_IPRIORITYR75_RESET 0x00000000
12086 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR75 register from the beginning of the component. */
12087 #define ALT_GIC_DIST_GICD_IPRIORITYR75_OFST 0x52c
12088 
12089 /*
12090  * Register : GICD_IPRIORITYR76
12091  *
12092  * Interrupt Priority Registers
12093  *
12094  * Register Layout
12095  *
12096  * Bits | Access | Reset | Description
12097  * :-------|:-------|:------|:------------
12098  * [31:0] | RW | 0x0 | Empty
12099  *
12100  */
12101 /*
12102  * Field : Empty - fld
12103  *
12104  * Placeholder
12105  *
12106  * Field Access Macros:
12107  *
12108  */
12109 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR76_FLD register field. */
12110 #define ALT_GIC_DIST_GICD_IPRIORITYR76_FLD_LSB 0
12111 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR76_FLD register field. */
12112 #define ALT_GIC_DIST_GICD_IPRIORITYR76_FLD_MSB 31
12113 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR76_FLD register field. */
12114 #define ALT_GIC_DIST_GICD_IPRIORITYR76_FLD_WIDTH 32
12115 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR76_FLD register field value. */
12116 #define ALT_GIC_DIST_GICD_IPRIORITYR76_FLD_SET_MSK 0xffffffff
12117 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR76_FLD register field value. */
12118 #define ALT_GIC_DIST_GICD_IPRIORITYR76_FLD_CLR_MSK 0x00000000
12119 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR76_FLD register field. */
12120 #define ALT_GIC_DIST_GICD_IPRIORITYR76_FLD_RESET 0x0
12121 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR76_FLD field value from a register. */
12122 #define ALT_GIC_DIST_GICD_IPRIORITYR76_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12123 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR76_FLD register field value suitable for setting the register. */
12124 #define ALT_GIC_DIST_GICD_IPRIORITYR76_FLD_SET(value) (((value) << 0) & 0xffffffff)
12125 
12126 #ifndef __ASSEMBLY__
12127 /*
12128  * WARNING: The C register and register group struct declarations are provided for
12129  * convenience and illustrative purposes. They should, however, be used with
12130  * caution as the C language standard provides no guarantees about the alignment or
12131  * atomicity of device memory accesses. The recommended practice for coding device
12132  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12133  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12134  * alt_write_dword() functions for 64 bit registers.
12135  *
12136  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR76.
12137  */
12138 struct ALT_GIC_DIST_GICD_IPRIORITYR76_s
12139 {
12140  volatile uint32_t fld : 32; /* Empty */
12141 };
12142 
12143 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR76. */
12144 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR76_s ALT_GIC_DIST_GICD_IPRIORITYR76_t;
12145 #endif /* __ASSEMBLY__ */
12146 
12147 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR76 register. */
12148 #define ALT_GIC_DIST_GICD_IPRIORITYR76_RESET 0x00000000
12149 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR76 register from the beginning of the component. */
12150 #define ALT_GIC_DIST_GICD_IPRIORITYR76_OFST 0x530
12151 
12152 /*
12153  * Register : GICD_IPRIORITYR77
12154  *
12155  * Interrupt Priority Registers
12156  *
12157  * Register Layout
12158  *
12159  * Bits | Access | Reset | Description
12160  * :-------|:-------|:------|:------------
12161  * [31:0] | RW | 0x0 | Empty
12162  *
12163  */
12164 /*
12165  * Field : Empty - fld
12166  *
12167  * Placeholder
12168  *
12169  * Field Access Macros:
12170  *
12171  */
12172 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR77_FLD register field. */
12173 #define ALT_GIC_DIST_GICD_IPRIORITYR77_FLD_LSB 0
12174 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR77_FLD register field. */
12175 #define ALT_GIC_DIST_GICD_IPRIORITYR77_FLD_MSB 31
12176 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR77_FLD register field. */
12177 #define ALT_GIC_DIST_GICD_IPRIORITYR77_FLD_WIDTH 32
12178 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR77_FLD register field value. */
12179 #define ALT_GIC_DIST_GICD_IPRIORITYR77_FLD_SET_MSK 0xffffffff
12180 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR77_FLD register field value. */
12181 #define ALT_GIC_DIST_GICD_IPRIORITYR77_FLD_CLR_MSK 0x00000000
12182 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR77_FLD register field. */
12183 #define ALT_GIC_DIST_GICD_IPRIORITYR77_FLD_RESET 0x0
12184 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR77_FLD field value from a register. */
12185 #define ALT_GIC_DIST_GICD_IPRIORITYR77_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12186 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR77_FLD register field value suitable for setting the register. */
12187 #define ALT_GIC_DIST_GICD_IPRIORITYR77_FLD_SET(value) (((value) << 0) & 0xffffffff)
12188 
12189 #ifndef __ASSEMBLY__
12190 /*
12191  * WARNING: The C register and register group struct declarations are provided for
12192  * convenience and illustrative purposes. They should, however, be used with
12193  * caution as the C language standard provides no guarantees about the alignment or
12194  * atomicity of device memory accesses. The recommended practice for coding device
12195  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12196  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12197  * alt_write_dword() functions for 64 bit registers.
12198  *
12199  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR77.
12200  */
12201 struct ALT_GIC_DIST_GICD_IPRIORITYR77_s
12202 {
12203  volatile uint32_t fld : 32; /* Empty */
12204 };
12205 
12206 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR77. */
12207 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR77_s ALT_GIC_DIST_GICD_IPRIORITYR77_t;
12208 #endif /* __ASSEMBLY__ */
12209 
12210 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR77 register. */
12211 #define ALT_GIC_DIST_GICD_IPRIORITYR77_RESET 0x00000000
12212 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR77 register from the beginning of the component. */
12213 #define ALT_GIC_DIST_GICD_IPRIORITYR77_OFST 0x534
12214 
12215 /*
12216  * Register : GICD_IPRIORITYR78
12217  *
12218  * Interrupt Priority Registers
12219  *
12220  * Register Layout
12221  *
12222  * Bits | Access | Reset | Description
12223  * :-------|:-------|:------|:------------
12224  * [31:0] | RW | 0x0 | Empty
12225  *
12226  */
12227 /*
12228  * Field : Empty - fld
12229  *
12230  * Placeholder
12231  *
12232  * Field Access Macros:
12233  *
12234  */
12235 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR78_FLD register field. */
12236 #define ALT_GIC_DIST_GICD_IPRIORITYR78_FLD_LSB 0
12237 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR78_FLD register field. */
12238 #define ALT_GIC_DIST_GICD_IPRIORITYR78_FLD_MSB 31
12239 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR78_FLD register field. */
12240 #define ALT_GIC_DIST_GICD_IPRIORITYR78_FLD_WIDTH 32
12241 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR78_FLD register field value. */
12242 #define ALT_GIC_DIST_GICD_IPRIORITYR78_FLD_SET_MSK 0xffffffff
12243 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR78_FLD register field value. */
12244 #define ALT_GIC_DIST_GICD_IPRIORITYR78_FLD_CLR_MSK 0x00000000
12245 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR78_FLD register field. */
12246 #define ALT_GIC_DIST_GICD_IPRIORITYR78_FLD_RESET 0x0
12247 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR78_FLD field value from a register. */
12248 #define ALT_GIC_DIST_GICD_IPRIORITYR78_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12249 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR78_FLD register field value suitable for setting the register. */
12250 #define ALT_GIC_DIST_GICD_IPRIORITYR78_FLD_SET(value) (((value) << 0) & 0xffffffff)
12251 
12252 #ifndef __ASSEMBLY__
12253 /*
12254  * WARNING: The C register and register group struct declarations are provided for
12255  * convenience and illustrative purposes. They should, however, be used with
12256  * caution as the C language standard provides no guarantees about the alignment or
12257  * atomicity of device memory accesses. The recommended practice for coding device
12258  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12259  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12260  * alt_write_dword() functions for 64 bit registers.
12261  *
12262  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR78.
12263  */
12264 struct ALT_GIC_DIST_GICD_IPRIORITYR78_s
12265 {
12266  volatile uint32_t fld : 32; /* Empty */
12267 };
12268 
12269 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR78. */
12270 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR78_s ALT_GIC_DIST_GICD_IPRIORITYR78_t;
12271 #endif /* __ASSEMBLY__ */
12272 
12273 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR78 register. */
12274 #define ALT_GIC_DIST_GICD_IPRIORITYR78_RESET 0x00000000
12275 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR78 register from the beginning of the component. */
12276 #define ALT_GIC_DIST_GICD_IPRIORITYR78_OFST 0x538
12277 
12278 /*
12279  * Register : GICD_IPRIORITYR79
12280  *
12281  * Interrupt Priority Registers
12282  *
12283  * Register Layout
12284  *
12285  * Bits | Access | Reset | Description
12286  * :-------|:-------|:------|:------------
12287  * [31:0] | RW | 0x0 | Empty
12288  *
12289  */
12290 /*
12291  * Field : Empty - fld
12292  *
12293  * Placeholder
12294  *
12295  * Field Access Macros:
12296  *
12297  */
12298 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR79_FLD register field. */
12299 #define ALT_GIC_DIST_GICD_IPRIORITYR79_FLD_LSB 0
12300 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR79_FLD register field. */
12301 #define ALT_GIC_DIST_GICD_IPRIORITYR79_FLD_MSB 31
12302 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR79_FLD register field. */
12303 #define ALT_GIC_DIST_GICD_IPRIORITYR79_FLD_WIDTH 32
12304 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR79_FLD register field value. */
12305 #define ALT_GIC_DIST_GICD_IPRIORITYR79_FLD_SET_MSK 0xffffffff
12306 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR79_FLD register field value. */
12307 #define ALT_GIC_DIST_GICD_IPRIORITYR79_FLD_CLR_MSK 0x00000000
12308 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR79_FLD register field. */
12309 #define ALT_GIC_DIST_GICD_IPRIORITYR79_FLD_RESET 0x0
12310 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR79_FLD field value from a register. */
12311 #define ALT_GIC_DIST_GICD_IPRIORITYR79_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12312 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR79_FLD register field value suitable for setting the register. */
12313 #define ALT_GIC_DIST_GICD_IPRIORITYR79_FLD_SET(value) (((value) << 0) & 0xffffffff)
12314 
12315 #ifndef __ASSEMBLY__
12316 /*
12317  * WARNING: The C register and register group struct declarations are provided for
12318  * convenience and illustrative purposes. They should, however, be used with
12319  * caution as the C language standard provides no guarantees about the alignment or
12320  * atomicity of device memory accesses. The recommended practice for coding device
12321  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12322  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12323  * alt_write_dword() functions for 64 bit registers.
12324  *
12325  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR79.
12326  */
12327 struct ALT_GIC_DIST_GICD_IPRIORITYR79_s
12328 {
12329  volatile uint32_t fld : 32; /* Empty */
12330 };
12331 
12332 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR79. */
12333 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR79_s ALT_GIC_DIST_GICD_IPRIORITYR79_t;
12334 #endif /* __ASSEMBLY__ */
12335 
12336 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR79 register. */
12337 #define ALT_GIC_DIST_GICD_IPRIORITYR79_RESET 0x00000000
12338 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR79 register from the beginning of the component. */
12339 #define ALT_GIC_DIST_GICD_IPRIORITYR79_OFST 0x53c
12340 
12341 /*
12342  * Register : GICD_IPRIORITYR80
12343  *
12344  * Interrupt Priority Registers
12345  *
12346  * Register Layout
12347  *
12348  * Bits | Access | Reset | Description
12349  * :-------|:-------|:------|:------------
12350  * [31:0] | RW | 0x0 | Empty
12351  *
12352  */
12353 /*
12354  * Field : Empty - fld
12355  *
12356  * Placeholder
12357  *
12358  * Field Access Macros:
12359  *
12360  */
12361 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR80_FLD register field. */
12362 #define ALT_GIC_DIST_GICD_IPRIORITYR80_FLD_LSB 0
12363 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR80_FLD register field. */
12364 #define ALT_GIC_DIST_GICD_IPRIORITYR80_FLD_MSB 31
12365 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR80_FLD register field. */
12366 #define ALT_GIC_DIST_GICD_IPRIORITYR80_FLD_WIDTH 32
12367 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR80_FLD register field value. */
12368 #define ALT_GIC_DIST_GICD_IPRIORITYR80_FLD_SET_MSK 0xffffffff
12369 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR80_FLD register field value. */
12370 #define ALT_GIC_DIST_GICD_IPRIORITYR80_FLD_CLR_MSK 0x00000000
12371 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR80_FLD register field. */
12372 #define ALT_GIC_DIST_GICD_IPRIORITYR80_FLD_RESET 0x0
12373 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR80_FLD field value from a register. */
12374 #define ALT_GIC_DIST_GICD_IPRIORITYR80_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12375 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR80_FLD register field value suitable for setting the register. */
12376 #define ALT_GIC_DIST_GICD_IPRIORITYR80_FLD_SET(value) (((value) << 0) & 0xffffffff)
12377 
12378 #ifndef __ASSEMBLY__
12379 /*
12380  * WARNING: The C register and register group struct declarations are provided for
12381  * convenience and illustrative purposes. They should, however, be used with
12382  * caution as the C language standard provides no guarantees about the alignment or
12383  * atomicity of device memory accesses. The recommended practice for coding device
12384  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12385  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12386  * alt_write_dword() functions for 64 bit registers.
12387  *
12388  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR80.
12389  */
12390 struct ALT_GIC_DIST_GICD_IPRIORITYR80_s
12391 {
12392  volatile uint32_t fld : 32; /* Empty */
12393 };
12394 
12395 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR80. */
12396 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR80_s ALT_GIC_DIST_GICD_IPRIORITYR80_t;
12397 #endif /* __ASSEMBLY__ */
12398 
12399 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR80 register. */
12400 #define ALT_GIC_DIST_GICD_IPRIORITYR80_RESET 0x00000000
12401 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR80 register from the beginning of the component. */
12402 #define ALT_GIC_DIST_GICD_IPRIORITYR80_OFST 0x540
12403 
12404 /*
12405  * Register : GICD_IPRIORITYR81
12406  *
12407  * Interrupt Priority Registers
12408  *
12409  * Register Layout
12410  *
12411  * Bits | Access | Reset | Description
12412  * :-------|:-------|:------|:------------
12413  * [31:0] | RW | 0x0 | Empty
12414  *
12415  */
12416 /*
12417  * Field : Empty - fld
12418  *
12419  * Placeholder
12420  *
12421  * Field Access Macros:
12422  *
12423  */
12424 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR81_FLD register field. */
12425 #define ALT_GIC_DIST_GICD_IPRIORITYR81_FLD_LSB 0
12426 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR81_FLD register field. */
12427 #define ALT_GIC_DIST_GICD_IPRIORITYR81_FLD_MSB 31
12428 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR81_FLD register field. */
12429 #define ALT_GIC_DIST_GICD_IPRIORITYR81_FLD_WIDTH 32
12430 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR81_FLD register field value. */
12431 #define ALT_GIC_DIST_GICD_IPRIORITYR81_FLD_SET_MSK 0xffffffff
12432 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR81_FLD register field value. */
12433 #define ALT_GIC_DIST_GICD_IPRIORITYR81_FLD_CLR_MSK 0x00000000
12434 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR81_FLD register field. */
12435 #define ALT_GIC_DIST_GICD_IPRIORITYR81_FLD_RESET 0x0
12436 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR81_FLD field value from a register. */
12437 #define ALT_GIC_DIST_GICD_IPRIORITYR81_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12438 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR81_FLD register field value suitable for setting the register. */
12439 #define ALT_GIC_DIST_GICD_IPRIORITYR81_FLD_SET(value) (((value) << 0) & 0xffffffff)
12440 
12441 #ifndef __ASSEMBLY__
12442 /*
12443  * WARNING: The C register and register group struct declarations are provided for
12444  * convenience and illustrative purposes. They should, however, be used with
12445  * caution as the C language standard provides no guarantees about the alignment or
12446  * atomicity of device memory accesses. The recommended practice for coding device
12447  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12448  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12449  * alt_write_dword() functions for 64 bit registers.
12450  *
12451  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR81.
12452  */
12453 struct ALT_GIC_DIST_GICD_IPRIORITYR81_s
12454 {
12455  volatile uint32_t fld : 32; /* Empty */
12456 };
12457 
12458 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR81. */
12459 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR81_s ALT_GIC_DIST_GICD_IPRIORITYR81_t;
12460 #endif /* __ASSEMBLY__ */
12461 
12462 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR81 register. */
12463 #define ALT_GIC_DIST_GICD_IPRIORITYR81_RESET 0x00000000
12464 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR81 register from the beginning of the component. */
12465 #define ALT_GIC_DIST_GICD_IPRIORITYR81_OFST 0x544
12466 
12467 /*
12468  * Register : GICD_IPRIORITYR82
12469  *
12470  * Interrupt Priority Registers
12471  *
12472  * Register Layout
12473  *
12474  * Bits | Access | Reset | Description
12475  * :-------|:-------|:------|:------------
12476  * [31:0] | RW | 0x0 | Empty
12477  *
12478  */
12479 /*
12480  * Field : Empty - fld
12481  *
12482  * Placeholder
12483  *
12484  * Field Access Macros:
12485  *
12486  */
12487 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR82_FLD register field. */
12488 #define ALT_GIC_DIST_GICD_IPRIORITYR82_FLD_LSB 0
12489 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR82_FLD register field. */
12490 #define ALT_GIC_DIST_GICD_IPRIORITYR82_FLD_MSB 31
12491 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR82_FLD register field. */
12492 #define ALT_GIC_DIST_GICD_IPRIORITYR82_FLD_WIDTH 32
12493 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR82_FLD register field value. */
12494 #define ALT_GIC_DIST_GICD_IPRIORITYR82_FLD_SET_MSK 0xffffffff
12495 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR82_FLD register field value. */
12496 #define ALT_GIC_DIST_GICD_IPRIORITYR82_FLD_CLR_MSK 0x00000000
12497 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR82_FLD register field. */
12498 #define ALT_GIC_DIST_GICD_IPRIORITYR82_FLD_RESET 0x0
12499 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR82_FLD field value from a register. */
12500 #define ALT_GIC_DIST_GICD_IPRIORITYR82_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12501 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR82_FLD register field value suitable for setting the register. */
12502 #define ALT_GIC_DIST_GICD_IPRIORITYR82_FLD_SET(value) (((value) << 0) & 0xffffffff)
12503 
12504 #ifndef __ASSEMBLY__
12505 /*
12506  * WARNING: The C register and register group struct declarations are provided for
12507  * convenience and illustrative purposes. They should, however, be used with
12508  * caution as the C language standard provides no guarantees about the alignment or
12509  * atomicity of device memory accesses. The recommended practice for coding device
12510  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12511  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12512  * alt_write_dword() functions for 64 bit registers.
12513  *
12514  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR82.
12515  */
12516 struct ALT_GIC_DIST_GICD_IPRIORITYR82_s
12517 {
12518  volatile uint32_t fld : 32; /* Empty */
12519 };
12520 
12521 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR82. */
12522 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR82_s ALT_GIC_DIST_GICD_IPRIORITYR82_t;
12523 #endif /* __ASSEMBLY__ */
12524 
12525 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR82 register. */
12526 #define ALT_GIC_DIST_GICD_IPRIORITYR82_RESET 0x00000000
12527 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR82 register from the beginning of the component. */
12528 #define ALT_GIC_DIST_GICD_IPRIORITYR82_OFST 0x548
12529 
12530 /*
12531  * Register : GICD_IPRIORITYR83
12532  *
12533  * Interrupt Priority Registers
12534  *
12535  * Register Layout
12536  *
12537  * Bits | Access | Reset | Description
12538  * :-------|:-------|:------|:------------
12539  * [31:0] | RW | 0x0 | Empty
12540  *
12541  */
12542 /*
12543  * Field : Empty - fld
12544  *
12545  * Placeholder
12546  *
12547  * Field Access Macros:
12548  *
12549  */
12550 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR83_FLD register field. */
12551 #define ALT_GIC_DIST_GICD_IPRIORITYR83_FLD_LSB 0
12552 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR83_FLD register field. */
12553 #define ALT_GIC_DIST_GICD_IPRIORITYR83_FLD_MSB 31
12554 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR83_FLD register field. */
12555 #define ALT_GIC_DIST_GICD_IPRIORITYR83_FLD_WIDTH 32
12556 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR83_FLD register field value. */
12557 #define ALT_GIC_DIST_GICD_IPRIORITYR83_FLD_SET_MSK 0xffffffff
12558 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR83_FLD register field value. */
12559 #define ALT_GIC_DIST_GICD_IPRIORITYR83_FLD_CLR_MSK 0x00000000
12560 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR83_FLD register field. */
12561 #define ALT_GIC_DIST_GICD_IPRIORITYR83_FLD_RESET 0x0
12562 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR83_FLD field value from a register. */
12563 #define ALT_GIC_DIST_GICD_IPRIORITYR83_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12564 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR83_FLD register field value suitable for setting the register. */
12565 #define ALT_GIC_DIST_GICD_IPRIORITYR83_FLD_SET(value) (((value) << 0) & 0xffffffff)
12566 
12567 #ifndef __ASSEMBLY__
12568 /*
12569  * WARNING: The C register and register group struct declarations are provided for
12570  * convenience and illustrative purposes. They should, however, be used with
12571  * caution as the C language standard provides no guarantees about the alignment or
12572  * atomicity of device memory accesses. The recommended practice for coding device
12573  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12574  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12575  * alt_write_dword() functions for 64 bit registers.
12576  *
12577  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR83.
12578  */
12579 struct ALT_GIC_DIST_GICD_IPRIORITYR83_s
12580 {
12581  volatile uint32_t fld : 32; /* Empty */
12582 };
12583 
12584 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR83. */
12585 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR83_s ALT_GIC_DIST_GICD_IPRIORITYR83_t;
12586 #endif /* __ASSEMBLY__ */
12587 
12588 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR83 register. */
12589 #define ALT_GIC_DIST_GICD_IPRIORITYR83_RESET 0x00000000
12590 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR83 register from the beginning of the component. */
12591 #define ALT_GIC_DIST_GICD_IPRIORITYR83_OFST 0x54c
12592 
12593 /*
12594  * Register : GICD_IPRIORITYR84
12595  *
12596  * Interrupt Priority Registers
12597  *
12598  * Register Layout
12599  *
12600  * Bits | Access | Reset | Description
12601  * :-------|:-------|:------|:------------
12602  * [31:0] | RW | 0x0 | Empty
12603  *
12604  */
12605 /*
12606  * Field : Empty - fld
12607  *
12608  * Placeholder
12609  *
12610  * Field Access Macros:
12611  *
12612  */
12613 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR84_FLD register field. */
12614 #define ALT_GIC_DIST_GICD_IPRIORITYR84_FLD_LSB 0
12615 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR84_FLD register field. */
12616 #define ALT_GIC_DIST_GICD_IPRIORITYR84_FLD_MSB 31
12617 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR84_FLD register field. */
12618 #define ALT_GIC_DIST_GICD_IPRIORITYR84_FLD_WIDTH 32
12619 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR84_FLD register field value. */
12620 #define ALT_GIC_DIST_GICD_IPRIORITYR84_FLD_SET_MSK 0xffffffff
12621 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR84_FLD register field value. */
12622 #define ALT_GIC_DIST_GICD_IPRIORITYR84_FLD_CLR_MSK 0x00000000
12623 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR84_FLD register field. */
12624 #define ALT_GIC_DIST_GICD_IPRIORITYR84_FLD_RESET 0x0
12625 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR84_FLD field value from a register. */
12626 #define ALT_GIC_DIST_GICD_IPRIORITYR84_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12627 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR84_FLD register field value suitable for setting the register. */
12628 #define ALT_GIC_DIST_GICD_IPRIORITYR84_FLD_SET(value) (((value) << 0) & 0xffffffff)
12629 
12630 #ifndef __ASSEMBLY__
12631 /*
12632  * WARNING: The C register and register group struct declarations are provided for
12633  * convenience and illustrative purposes. They should, however, be used with
12634  * caution as the C language standard provides no guarantees about the alignment or
12635  * atomicity of device memory accesses. The recommended practice for coding device
12636  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12637  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12638  * alt_write_dword() functions for 64 bit registers.
12639  *
12640  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR84.
12641  */
12642 struct ALT_GIC_DIST_GICD_IPRIORITYR84_s
12643 {
12644  volatile uint32_t fld : 32; /* Empty */
12645 };
12646 
12647 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR84. */
12648 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR84_s ALT_GIC_DIST_GICD_IPRIORITYR84_t;
12649 #endif /* __ASSEMBLY__ */
12650 
12651 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR84 register. */
12652 #define ALT_GIC_DIST_GICD_IPRIORITYR84_RESET 0x00000000
12653 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR84 register from the beginning of the component. */
12654 #define ALT_GIC_DIST_GICD_IPRIORITYR84_OFST 0x550
12655 
12656 /*
12657  * Register : GICD_IPRIORITYR85
12658  *
12659  * Interrupt Priority Registers
12660  *
12661  * Register Layout
12662  *
12663  * Bits | Access | Reset | Description
12664  * :-------|:-------|:------|:------------
12665  * [31:0] | RW | 0x0 | Empty
12666  *
12667  */
12668 /*
12669  * Field : Empty - fld
12670  *
12671  * Placeholder
12672  *
12673  * Field Access Macros:
12674  *
12675  */
12676 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR85_FLD register field. */
12677 #define ALT_GIC_DIST_GICD_IPRIORITYR85_FLD_LSB 0
12678 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR85_FLD register field. */
12679 #define ALT_GIC_DIST_GICD_IPRIORITYR85_FLD_MSB 31
12680 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR85_FLD register field. */
12681 #define ALT_GIC_DIST_GICD_IPRIORITYR85_FLD_WIDTH 32
12682 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR85_FLD register field value. */
12683 #define ALT_GIC_DIST_GICD_IPRIORITYR85_FLD_SET_MSK 0xffffffff
12684 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR85_FLD register field value. */
12685 #define ALT_GIC_DIST_GICD_IPRIORITYR85_FLD_CLR_MSK 0x00000000
12686 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR85_FLD register field. */
12687 #define ALT_GIC_DIST_GICD_IPRIORITYR85_FLD_RESET 0x0
12688 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR85_FLD field value from a register. */
12689 #define ALT_GIC_DIST_GICD_IPRIORITYR85_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12690 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR85_FLD register field value suitable for setting the register. */
12691 #define ALT_GIC_DIST_GICD_IPRIORITYR85_FLD_SET(value) (((value) << 0) & 0xffffffff)
12692 
12693 #ifndef __ASSEMBLY__
12694 /*
12695  * WARNING: The C register and register group struct declarations are provided for
12696  * convenience and illustrative purposes. They should, however, be used with
12697  * caution as the C language standard provides no guarantees about the alignment or
12698  * atomicity of device memory accesses. The recommended practice for coding device
12699  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12700  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12701  * alt_write_dword() functions for 64 bit registers.
12702  *
12703  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR85.
12704  */
12705 struct ALT_GIC_DIST_GICD_IPRIORITYR85_s
12706 {
12707  volatile uint32_t fld : 32; /* Empty */
12708 };
12709 
12710 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR85. */
12711 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR85_s ALT_GIC_DIST_GICD_IPRIORITYR85_t;
12712 #endif /* __ASSEMBLY__ */
12713 
12714 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR85 register. */
12715 #define ALT_GIC_DIST_GICD_IPRIORITYR85_RESET 0x00000000
12716 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR85 register from the beginning of the component. */
12717 #define ALT_GIC_DIST_GICD_IPRIORITYR85_OFST 0x554
12718 
12719 /*
12720  * Register : GICD_IPRIORITYR86
12721  *
12722  * Interrupt Priority Registers
12723  *
12724  * Register Layout
12725  *
12726  * Bits | Access | Reset | Description
12727  * :-------|:-------|:------|:------------
12728  * [31:0] | RW | 0x0 | Empty
12729  *
12730  */
12731 /*
12732  * Field : Empty - fld
12733  *
12734  * Placeholder
12735  *
12736  * Field Access Macros:
12737  *
12738  */
12739 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR86_FLD register field. */
12740 #define ALT_GIC_DIST_GICD_IPRIORITYR86_FLD_LSB 0
12741 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR86_FLD register field. */
12742 #define ALT_GIC_DIST_GICD_IPRIORITYR86_FLD_MSB 31
12743 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR86_FLD register field. */
12744 #define ALT_GIC_DIST_GICD_IPRIORITYR86_FLD_WIDTH 32
12745 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR86_FLD register field value. */
12746 #define ALT_GIC_DIST_GICD_IPRIORITYR86_FLD_SET_MSK 0xffffffff
12747 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR86_FLD register field value. */
12748 #define ALT_GIC_DIST_GICD_IPRIORITYR86_FLD_CLR_MSK 0x00000000
12749 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR86_FLD register field. */
12750 #define ALT_GIC_DIST_GICD_IPRIORITYR86_FLD_RESET 0x0
12751 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR86_FLD field value from a register. */
12752 #define ALT_GIC_DIST_GICD_IPRIORITYR86_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12753 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR86_FLD register field value suitable for setting the register. */
12754 #define ALT_GIC_DIST_GICD_IPRIORITYR86_FLD_SET(value) (((value) << 0) & 0xffffffff)
12755 
12756 #ifndef __ASSEMBLY__
12757 /*
12758  * WARNING: The C register and register group struct declarations are provided for
12759  * convenience and illustrative purposes. They should, however, be used with
12760  * caution as the C language standard provides no guarantees about the alignment or
12761  * atomicity of device memory accesses. The recommended practice for coding device
12762  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12763  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12764  * alt_write_dword() functions for 64 bit registers.
12765  *
12766  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR86.
12767  */
12768 struct ALT_GIC_DIST_GICD_IPRIORITYR86_s
12769 {
12770  volatile uint32_t fld : 32; /* Empty */
12771 };
12772 
12773 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR86. */
12774 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR86_s ALT_GIC_DIST_GICD_IPRIORITYR86_t;
12775 #endif /* __ASSEMBLY__ */
12776 
12777 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR86 register. */
12778 #define ALT_GIC_DIST_GICD_IPRIORITYR86_RESET 0x00000000
12779 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR86 register from the beginning of the component. */
12780 #define ALT_GIC_DIST_GICD_IPRIORITYR86_OFST 0x558
12781 
12782 /*
12783  * Register : GICD_IPRIORITYR87
12784  *
12785  * Interrupt Priority Registers
12786  *
12787  * Register Layout
12788  *
12789  * Bits | Access | Reset | Description
12790  * :-------|:-------|:------|:------------
12791  * [31:0] | RW | 0x0 | Empty
12792  *
12793  */
12794 /*
12795  * Field : Empty - fld
12796  *
12797  * Placeholder
12798  *
12799  * Field Access Macros:
12800  *
12801  */
12802 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR87_FLD register field. */
12803 #define ALT_GIC_DIST_GICD_IPRIORITYR87_FLD_LSB 0
12804 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR87_FLD register field. */
12805 #define ALT_GIC_DIST_GICD_IPRIORITYR87_FLD_MSB 31
12806 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR87_FLD register field. */
12807 #define ALT_GIC_DIST_GICD_IPRIORITYR87_FLD_WIDTH 32
12808 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR87_FLD register field value. */
12809 #define ALT_GIC_DIST_GICD_IPRIORITYR87_FLD_SET_MSK 0xffffffff
12810 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR87_FLD register field value. */
12811 #define ALT_GIC_DIST_GICD_IPRIORITYR87_FLD_CLR_MSK 0x00000000
12812 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR87_FLD register field. */
12813 #define ALT_GIC_DIST_GICD_IPRIORITYR87_FLD_RESET 0x0
12814 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR87_FLD field value from a register. */
12815 #define ALT_GIC_DIST_GICD_IPRIORITYR87_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12816 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR87_FLD register field value suitable for setting the register. */
12817 #define ALT_GIC_DIST_GICD_IPRIORITYR87_FLD_SET(value) (((value) << 0) & 0xffffffff)
12818 
12819 #ifndef __ASSEMBLY__
12820 /*
12821  * WARNING: The C register and register group struct declarations are provided for
12822  * convenience and illustrative purposes. They should, however, be used with
12823  * caution as the C language standard provides no guarantees about the alignment or
12824  * atomicity of device memory accesses. The recommended practice for coding device
12825  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12826  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12827  * alt_write_dword() functions for 64 bit registers.
12828  *
12829  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR87.
12830  */
12831 struct ALT_GIC_DIST_GICD_IPRIORITYR87_s
12832 {
12833  volatile uint32_t fld : 32; /* Empty */
12834 };
12835 
12836 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR87. */
12837 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR87_s ALT_GIC_DIST_GICD_IPRIORITYR87_t;
12838 #endif /* __ASSEMBLY__ */
12839 
12840 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR87 register. */
12841 #define ALT_GIC_DIST_GICD_IPRIORITYR87_RESET 0x00000000
12842 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR87 register from the beginning of the component. */
12843 #define ALT_GIC_DIST_GICD_IPRIORITYR87_OFST 0x55c
12844 
12845 /*
12846  * Register : GICD_IPRIORITYR88
12847  *
12848  * Interrupt Priority Registers
12849  *
12850  * Register Layout
12851  *
12852  * Bits | Access | Reset | Description
12853  * :-------|:-------|:------|:------------
12854  * [31:0] | RW | 0x0 | Empty
12855  *
12856  */
12857 /*
12858  * Field : Empty - fld
12859  *
12860  * Placeholder
12861  *
12862  * Field Access Macros:
12863  *
12864  */
12865 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR88_FLD register field. */
12866 #define ALT_GIC_DIST_GICD_IPRIORITYR88_FLD_LSB 0
12867 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR88_FLD register field. */
12868 #define ALT_GIC_DIST_GICD_IPRIORITYR88_FLD_MSB 31
12869 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR88_FLD register field. */
12870 #define ALT_GIC_DIST_GICD_IPRIORITYR88_FLD_WIDTH 32
12871 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR88_FLD register field value. */
12872 #define ALT_GIC_DIST_GICD_IPRIORITYR88_FLD_SET_MSK 0xffffffff
12873 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR88_FLD register field value. */
12874 #define ALT_GIC_DIST_GICD_IPRIORITYR88_FLD_CLR_MSK 0x00000000
12875 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR88_FLD register field. */
12876 #define ALT_GIC_DIST_GICD_IPRIORITYR88_FLD_RESET 0x0
12877 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR88_FLD field value from a register. */
12878 #define ALT_GIC_DIST_GICD_IPRIORITYR88_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12879 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR88_FLD register field value suitable for setting the register. */
12880 #define ALT_GIC_DIST_GICD_IPRIORITYR88_FLD_SET(value) (((value) << 0) & 0xffffffff)
12881 
12882 #ifndef __ASSEMBLY__
12883 /*
12884  * WARNING: The C register and register group struct declarations are provided for
12885  * convenience and illustrative purposes. They should, however, be used with
12886  * caution as the C language standard provides no guarantees about the alignment or
12887  * atomicity of device memory accesses. The recommended practice for coding device
12888  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12889  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12890  * alt_write_dword() functions for 64 bit registers.
12891  *
12892  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR88.
12893  */
12894 struct ALT_GIC_DIST_GICD_IPRIORITYR88_s
12895 {
12896  volatile uint32_t fld : 32; /* Empty */
12897 };
12898 
12899 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR88. */
12900 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR88_s ALT_GIC_DIST_GICD_IPRIORITYR88_t;
12901 #endif /* __ASSEMBLY__ */
12902 
12903 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR88 register. */
12904 #define ALT_GIC_DIST_GICD_IPRIORITYR88_RESET 0x00000000
12905 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR88 register from the beginning of the component. */
12906 #define ALT_GIC_DIST_GICD_IPRIORITYR88_OFST 0x560
12907 
12908 /*
12909  * Register : GICD_IPRIORITYR89
12910  *
12911  * Interrupt Priority Registers
12912  *
12913  * Register Layout
12914  *
12915  * Bits | Access | Reset | Description
12916  * :-------|:-------|:------|:------------
12917  * [31:0] | RW | 0x0 | Empty
12918  *
12919  */
12920 /*
12921  * Field : Empty - fld
12922  *
12923  * Placeholder
12924  *
12925  * Field Access Macros:
12926  *
12927  */
12928 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR89_FLD register field. */
12929 #define ALT_GIC_DIST_GICD_IPRIORITYR89_FLD_LSB 0
12930 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR89_FLD register field. */
12931 #define ALT_GIC_DIST_GICD_IPRIORITYR89_FLD_MSB 31
12932 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR89_FLD register field. */
12933 #define ALT_GIC_DIST_GICD_IPRIORITYR89_FLD_WIDTH 32
12934 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR89_FLD register field value. */
12935 #define ALT_GIC_DIST_GICD_IPRIORITYR89_FLD_SET_MSK 0xffffffff
12936 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR89_FLD register field value. */
12937 #define ALT_GIC_DIST_GICD_IPRIORITYR89_FLD_CLR_MSK 0x00000000
12938 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR89_FLD register field. */
12939 #define ALT_GIC_DIST_GICD_IPRIORITYR89_FLD_RESET 0x0
12940 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR89_FLD field value from a register. */
12941 #define ALT_GIC_DIST_GICD_IPRIORITYR89_FLD_GET(value) (((value) & 0xffffffff) >> 0)
12942 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR89_FLD register field value suitable for setting the register. */
12943 #define ALT_GIC_DIST_GICD_IPRIORITYR89_FLD_SET(value) (((value) << 0) & 0xffffffff)
12944 
12945 #ifndef __ASSEMBLY__
12946 /*
12947  * WARNING: The C register and register group struct declarations are provided for
12948  * convenience and illustrative purposes. They should, however, be used with
12949  * caution as the C language standard provides no guarantees about the alignment or
12950  * atomicity of device memory accesses. The recommended practice for coding device
12951  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12952  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12953  * alt_write_dword() functions for 64 bit registers.
12954  *
12955  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR89.
12956  */
12957 struct ALT_GIC_DIST_GICD_IPRIORITYR89_s
12958 {
12959  volatile uint32_t fld : 32; /* Empty */
12960 };
12961 
12962 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR89. */
12963 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR89_s ALT_GIC_DIST_GICD_IPRIORITYR89_t;
12964 #endif /* __ASSEMBLY__ */
12965 
12966 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR89 register. */
12967 #define ALT_GIC_DIST_GICD_IPRIORITYR89_RESET 0x00000000
12968 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR89 register from the beginning of the component. */
12969 #define ALT_GIC_DIST_GICD_IPRIORITYR89_OFST 0x564
12970 
12971 /*
12972  * Register : GICD_IPRIORITYR90
12973  *
12974  * Interrupt Priority Registers
12975  *
12976  * Register Layout
12977  *
12978  * Bits | Access | Reset | Description
12979  * :-------|:-------|:------|:------------
12980  * [31:0] | RW | 0x0 | Empty
12981  *
12982  */
12983 /*
12984  * Field : Empty - fld
12985  *
12986  * Placeholder
12987  *
12988  * Field Access Macros:
12989  *
12990  */
12991 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR90_FLD register field. */
12992 #define ALT_GIC_DIST_GICD_IPRIORITYR90_FLD_LSB 0
12993 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR90_FLD register field. */
12994 #define ALT_GIC_DIST_GICD_IPRIORITYR90_FLD_MSB 31
12995 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR90_FLD register field. */
12996 #define ALT_GIC_DIST_GICD_IPRIORITYR90_FLD_WIDTH 32
12997 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR90_FLD register field value. */
12998 #define ALT_GIC_DIST_GICD_IPRIORITYR90_FLD_SET_MSK 0xffffffff
12999 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR90_FLD register field value. */
13000 #define ALT_GIC_DIST_GICD_IPRIORITYR90_FLD_CLR_MSK 0x00000000
13001 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR90_FLD register field. */
13002 #define ALT_GIC_DIST_GICD_IPRIORITYR90_FLD_RESET 0x0
13003 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR90_FLD field value from a register. */
13004 #define ALT_GIC_DIST_GICD_IPRIORITYR90_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13005 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR90_FLD register field value suitable for setting the register. */
13006 #define ALT_GIC_DIST_GICD_IPRIORITYR90_FLD_SET(value) (((value) << 0) & 0xffffffff)
13007 
13008 #ifndef __ASSEMBLY__
13009 /*
13010  * WARNING: The C register and register group struct declarations are provided for
13011  * convenience and illustrative purposes. They should, however, be used with
13012  * caution as the C language standard provides no guarantees about the alignment or
13013  * atomicity of device memory accesses. The recommended practice for coding device
13014  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13015  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13016  * alt_write_dword() functions for 64 bit registers.
13017  *
13018  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR90.
13019  */
13020 struct ALT_GIC_DIST_GICD_IPRIORITYR90_s
13021 {
13022  volatile uint32_t fld : 32; /* Empty */
13023 };
13024 
13025 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR90. */
13026 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR90_s ALT_GIC_DIST_GICD_IPRIORITYR90_t;
13027 #endif /* __ASSEMBLY__ */
13028 
13029 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR90 register. */
13030 #define ALT_GIC_DIST_GICD_IPRIORITYR90_RESET 0x00000000
13031 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR90 register from the beginning of the component. */
13032 #define ALT_GIC_DIST_GICD_IPRIORITYR90_OFST 0x568
13033 
13034 /*
13035  * Register : GICD_IPRIORITYR91
13036  *
13037  * Interrupt Priority Registers
13038  *
13039  * Register Layout
13040  *
13041  * Bits | Access | Reset | Description
13042  * :-------|:-------|:------|:------------
13043  * [31:0] | RW | 0x0 | Empty
13044  *
13045  */
13046 /*
13047  * Field : Empty - fld
13048  *
13049  * Placeholder
13050  *
13051  * Field Access Macros:
13052  *
13053  */
13054 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR91_FLD register field. */
13055 #define ALT_GIC_DIST_GICD_IPRIORITYR91_FLD_LSB 0
13056 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR91_FLD register field. */
13057 #define ALT_GIC_DIST_GICD_IPRIORITYR91_FLD_MSB 31
13058 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR91_FLD register field. */
13059 #define ALT_GIC_DIST_GICD_IPRIORITYR91_FLD_WIDTH 32
13060 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR91_FLD register field value. */
13061 #define ALT_GIC_DIST_GICD_IPRIORITYR91_FLD_SET_MSK 0xffffffff
13062 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR91_FLD register field value. */
13063 #define ALT_GIC_DIST_GICD_IPRIORITYR91_FLD_CLR_MSK 0x00000000
13064 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR91_FLD register field. */
13065 #define ALT_GIC_DIST_GICD_IPRIORITYR91_FLD_RESET 0x0
13066 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR91_FLD field value from a register. */
13067 #define ALT_GIC_DIST_GICD_IPRIORITYR91_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13068 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR91_FLD register field value suitable for setting the register. */
13069 #define ALT_GIC_DIST_GICD_IPRIORITYR91_FLD_SET(value) (((value) << 0) & 0xffffffff)
13070 
13071 #ifndef __ASSEMBLY__
13072 /*
13073  * WARNING: The C register and register group struct declarations are provided for
13074  * convenience and illustrative purposes. They should, however, be used with
13075  * caution as the C language standard provides no guarantees about the alignment or
13076  * atomicity of device memory accesses. The recommended practice for coding device
13077  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13078  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13079  * alt_write_dword() functions for 64 bit registers.
13080  *
13081  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR91.
13082  */
13083 struct ALT_GIC_DIST_GICD_IPRIORITYR91_s
13084 {
13085  volatile uint32_t fld : 32; /* Empty */
13086 };
13087 
13088 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR91. */
13089 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR91_s ALT_GIC_DIST_GICD_IPRIORITYR91_t;
13090 #endif /* __ASSEMBLY__ */
13091 
13092 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR91 register. */
13093 #define ALT_GIC_DIST_GICD_IPRIORITYR91_RESET 0x00000000
13094 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR91 register from the beginning of the component. */
13095 #define ALT_GIC_DIST_GICD_IPRIORITYR91_OFST 0x56c
13096 
13097 /*
13098  * Register : GICD_IPRIORITYR92
13099  *
13100  * Interrupt Priority Registers
13101  *
13102  * Register Layout
13103  *
13104  * Bits | Access | Reset | Description
13105  * :-------|:-------|:------|:------------
13106  * [31:0] | RW | 0x0 | Empty
13107  *
13108  */
13109 /*
13110  * Field : Empty - fld
13111  *
13112  * Placeholder
13113  *
13114  * Field Access Macros:
13115  *
13116  */
13117 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR92_FLD register field. */
13118 #define ALT_GIC_DIST_GICD_IPRIORITYR92_FLD_LSB 0
13119 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR92_FLD register field. */
13120 #define ALT_GIC_DIST_GICD_IPRIORITYR92_FLD_MSB 31
13121 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR92_FLD register field. */
13122 #define ALT_GIC_DIST_GICD_IPRIORITYR92_FLD_WIDTH 32
13123 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR92_FLD register field value. */
13124 #define ALT_GIC_DIST_GICD_IPRIORITYR92_FLD_SET_MSK 0xffffffff
13125 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR92_FLD register field value. */
13126 #define ALT_GIC_DIST_GICD_IPRIORITYR92_FLD_CLR_MSK 0x00000000
13127 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR92_FLD register field. */
13128 #define ALT_GIC_DIST_GICD_IPRIORITYR92_FLD_RESET 0x0
13129 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR92_FLD field value from a register. */
13130 #define ALT_GIC_DIST_GICD_IPRIORITYR92_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13131 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR92_FLD register field value suitable for setting the register. */
13132 #define ALT_GIC_DIST_GICD_IPRIORITYR92_FLD_SET(value) (((value) << 0) & 0xffffffff)
13133 
13134 #ifndef __ASSEMBLY__
13135 /*
13136  * WARNING: The C register and register group struct declarations are provided for
13137  * convenience and illustrative purposes. They should, however, be used with
13138  * caution as the C language standard provides no guarantees about the alignment or
13139  * atomicity of device memory accesses. The recommended practice for coding device
13140  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13141  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13142  * alt_write_dword() functions for 64 bit registers.
13143  *
13144  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR92.
13145  */
13146 struct ALT_GIC_DIST_GICD_IPRIORITYR92_s
13147 {
13148  volatile uint32_t fld : 32; /* Empty */
13149 };
13150 
13151 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR92. */
13152 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR92_s ALT_GIC_DIST_GICD_IPRIORITYR92_t;
13153 #endif /* __ASSEMBLY__ */
13154 
13155 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR92 register. */
13156 #define ALT_GIC_DIST_GICD_IPRIORITYR92_RESET 0x00000000
13157 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR92 register from the beginning of the component. */
13158 #define ALT_GIC_DIST_GICD_IPRIORITYR92_OFST 0x570
13159 
13160 /*
13161  * Register : GICD_IPRIORITYR93
13162  *
13163  * Interrupt Priority Registers
13164  *
13165  * Register Layout
13166  *
13167  * Bits | Access | Reset | Description
13168  * :-------|:-------|:------|:------------
13169  * [31:0] | RW | 0x0 | Empty
13170  *
13171  */
13172 /*
13173  * Field : Empty - fld
13174  *
13175  * Placeholder
13176  *
13177  * Field Access Macros:
13178  *
13179  */
13180 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR93_FLD register field. */
13181 #define ALT_GIC_DIST_GICD_IPRIORITYR93_FLD_LSB 0
13182 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR93_FLD register field. */
13183 #define ALT_GIC_DIST_GICD_IPRIORITYR93_FLD_MSB 31
13184 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR93_FLD register field. */
13185 #define ALT_GIC_DIST_GICD_IPRIORITYR93_FLD_WIDTH 32
13186 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR93_FLD register field value. */
13187 #define ALT_GIC_DIST_GICD_IPRIORITYR93_FLD_SET_MSK 0xffffffff
13188 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR93_FLD register field value. */
13189 #define ALT_GIC_DIST_GICD_IPRIORITYR93_FLD_CLR_MSK 0x00000000
13190 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR93_FLD register field. */
13191 #define ALT_GIC_DIST_GICD_IPRIORITYR93_FLD_RESET 0x0
13192 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR93_FLD field value from a register. */
13193 #define ALT_GIC_DIST_GICD_IPRIORITYR93_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13194 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR93_FLD register field value suitable for setting the register. */
13195 #define ALT_GIC_DIST_GICD_IPRIORITYR93_FLD_SET(value) (((value) << 0) & 0xffffffff)
13196 
13197 #ifndef __ASSEMBLY__
13198 /*
13199  * WARNING: The C register and register group struct declarations are provided for
13200  * convenience and illustrative purposes. They should, however, be used with
13201  * caution as the C language standard provides no guarantees about the alignment or
13202  * atomicity of device memory accesses. The recommended practice for coding device
13203  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13204  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13205  * alt_write_dword() functions for 64 bit registers.
13206  *
13207  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR93.
13208  */
13209 struct ALT_GIC_DIST_GICD_IPRIORITYR93_s
13210 {
13211  volatile uint32_t fld : 32; /* Empty */
13212 };
13213 
13214 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR93. */
13215 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR93_s ALT_GIC_DIST_GICD_IPRIORITYR93_t;
13216 #endif /* __ASSEMBLY__ */
13217 
13218 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR93 register. */
13219 #define ALT_GIC_DIST_GICD_IPRIORITYR93_RESET 0x00000000
13220 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR93 register from the beginning of the component. */
13221 #define ALT_GIC_DIST_GICD_IPRIORITYR93_OFST 0x574
13222 
13223 /*
13224  * Register : GICD_IPRIORITYR94
13225  *
13226  * Interrupt Priority Registers
13227  *
13228  * Register Layout
13229  *
13230  * Bits | Access | Reset | Description
13231  * :-------|:-------|:------|:------------
13232  * [31:0] | RW | 0x0 | Empty
13233  *
13234  */
13235 /*
13236  * Field : Empty - fld
13237  *
13238  * Placeholder
13239  *
13240  * Field Access Macros:
13241  *
13242  */
13243 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR94_FLD register field. */
13244 #define ALT_GIC_DIST_GICD_IPRIORITYR94_FLD_LSB 0
13245 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR94_FLD register field. */
13246 #define ALT_GIC_DIST_GICD_IPRIORITYR94_FLD_MSB 31
13247 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR94_FLD register field. */
13248 #define ALT_GIC_DIST_GICD_IPRIORITYR94_FLD_WIDTH 32
13249 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR94_FLD register field value. */
13250 #define ALT_GIC_DIST_GICD_IPRIORITYR94_FLD_SET_MSK 0xffffffff
13251 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR94_FLD register field value. */
13252 #define ALT_GIC_DIST_GICD_IPRIORITYR94_FLD_CLR_MSK 0x00000000
13253 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR94_FLD register field. */
13254 #define ALT_GIC_DIST_GICD_IPRIORITYR94_FLD_RESET 0x0
13255 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR94_FLD field value from a register. */
13256 #define ALT_GIC_DIST_GICD_IPRIORITYR94_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13257 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR94_FLD register field value suitable for setting the register. */
13258 #define ALT_GIC_DIST_GICD_IPRIORITYR94_FLD_SET(value) (((value) << 0) & 0xffffffff)
13259 
13260 #ifndef __ASSEMBLY__
13261 /*
13262  * WARNING: The C register and register group struct declarations are provided for
13263  * convenience and illustrative purposes. They should, however, be used with
13264  * caution as the C language standard provides no guarantees about the alignment or
13265  * atomicity of device memory accesses. The recommended practice for coding device
13266  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13267  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13268  * alt_write_dword() functions for 64 bit registers.
13269  *
13270  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR94.
13271  */
13272 struct ALT_GIC_DIST_GICD_IPRIORITYR94_s
13273 {
13274  volatile uint32_t fld : 32; /* Empty */
13275 };
13276 
13277 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR94. */
13278 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR94_s ALT_GIC_DIST_GICD_IPRIORITYR94_t;
13279 #endif /* __ASSEMBLY__ */
13280 
13281 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR94 register. */
13282 #define ALT_GIC_DIST_GICD_IPRIORITYR94_RESET 0x00000000
13283 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR94 register from the beginning of the component. */
13284 #define ALT_GIC_DIST_GICD_IPRIORITYR94_OFST 0x578
13285 
13286 /*
13287  * Register : GICD_IPRIORITYR95
13288  *
13289  * Interrupt Priority Registers
13290  *
13291  * Register Layout
13292  *
13293  * Bits | Access | Reset | Description
13294  * :-------|:-------|:------|:------------
13295  * [31:0] | RW | 0x0 | Empty
13296  *
13297  */
13298 /*
13299  * Field : Empty - fld
13300  *
13301  * Placeholder
13302  *
13303  * Field Access Macros:
13304  *
13305  */
13306 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR95_FLD register field. */
13307 #define ALT_GIC_DIST_GICD_IPRIORITYR95_FLD_LSB 0
13308 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR95_FLD register field. */
13309 #define ALT_GIC_DIST_GICD_IPRIORITYR95_FLD_MSB 31
13310 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR95_FLD register field. */
13311 #define ALT_GIC_DIST_GICD_IPRIORITYR95_FLD_WIDTH 32
13312 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR95_FLD register field value. */
13313 #define ALT_GIC_DIST_GICD_IPRIORITYR95_FLD_SET_MSK 0xffffffff
13314 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR95_FLD register field value. */
13315 #define ALT_GIC_DIST_GICD_IPRIORITYR95_FLD_CLR_MSK 0x00000000
13316 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR95_FLD register field. */
13317 #define ALT_GIC_DIST_GICD_IPRIORITYR95_FLD_RESET 0x0
13318 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR95_FLD field value from a register. */
13319 #define ALT_GIC_DIST_GICD_IPRIORITYR95_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13320 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR95_FLD register field value suitable for setting the register. */
13321 #define ALT_GIC_DIST_GICD_IPRIORITYR95_FLD_SET(value) (((value) << 0) & 0xffffffff)
13322 
13323 #ifndef __ASSEMBLY__
13324 /*
13325  * WARNING: The C register and register group struct declarations are provided for
13326  * convenience and illustrative purposes. They should, however, be used with
13327  * caution as the C language standard provides no guarantees about the alignment or
13328  * atomicity of device memory accesses. The recommended practice for coding device
13329  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13330  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13331  * alt_write_dword() functions for 64 bit registers.
13332  *
13333  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR95.
13334  */
13335 struct ALT_GIC_DIST_GICD_IPRIORITYR95_s
13336 {
13337  volatile uint32_t fld : 32; /* Empty */
13338 };
13339 
13340 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR95. */
13341 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR95_s ALT_GIC_DIST_GICD_IPRIORITYR95_t;
13342 #endif /* __ASSEMBLY__ */
13343 
13344 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR95 register. */
13345 #define ALT_GIC_DIST_GICD_IPRIORITYR95_RESET 0x00000000
13346 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR95 register from the beginning of the component. */
13347 #define ALT_GIC_DIST_GICD_IPRIORITYR95_OFST 0x57c
13348 
13349 /*
13350  * Register : GICD_IPRIORITYR96
13351  *
13352  * Interrupt Priority Registers
13353  *
13354  * Register Layout
13355  *
13356  * Bits | Access | Reset | Description
13357  * :-------|:-------|:------|:------------
13358  * [31:0] | RW | 0x0 | Empty
13359  *
13360  */
13361 /*
13362  * Field : Empty - fld
13363  *
13364  * Placeholder
13365  *
13366  * Field Access Macros:
13367  *
13368  */
13369 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR96_FLD register field. */
13370 #define ALT_GIC_DIST_GICD_IPRIORITYR96_FLD_LSB 0
13371 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR96_FLD register field. */
13372 #define ALT_GIC_DIST_GICD_IPRIORITYR96_FLD_MSB 31
13373 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR96_FLD register field. */
13374 #define ALT_GIC_DIST_GICD_IPRIORITYR96_FLD_WIDTH 32
13375 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR96_FLD register field value. */
13376 #define ALT_GIC_DIST_GICD_IPRIORITYR96_FLD_SET_MSK 0xffffffff
13377 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR96_FLD register field value. */
13378 #define ALT_GIC_DIST_GICD_IPRIORITYR96_FLD_CLR_MSK 0x00000000
13379 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR96_FLD register field. */
13380 #define ALT_GIC_DIST_GICD_IPRIORITYR96_FLD_RESET 0x0
13381 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR96_FLD field value from a register. */
13382 #define ALT_GIC_DIST_GICD_IPRIORITYR96_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13383 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR96_FLD register field value suitable for setting the register. */
13384 #define ALT_GIC_DIST_GICD_IPRIORITYR96_FLD_SET(value) (((value) << 0) & 0xffffffff)
13385 
13386 #ifndef __ASSEMBLY__
13387 /*
13388  * WARNING: The C register and register group struct declarations are provided for
13389  * convenience and illustrative purposes. They should, however, be used with
13390  * caution as the C language standard provides no guarantees about the alignment or
13391  * atomicity of device memory accesses. The recommended practice for coding device
13392  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13393  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13394  * alt_write_dword() functions for 64 bit registers.
13395  *
13396  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR96.
13397  */
13398 struct ALT_GIC_DIST_GICD_IPRIORITYR96_s
13399 {
13400  volatile uint32_t fld : 32; /* Empty */
13401 };
13402 
13403 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR96. */
13404 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR96_s ALT_GIC_DIST_GICD_IPRIORITYR96_t;
13405 #endif /* __ASSEMBLY__ */
13406 
13407 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR96 register. */
13408 #define ALT_GIC_DIST_GICD_IPRIORITYR96_RESET 0x00000000
13409 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR96 register from the beginning of the component. */
13410 #define ALT_GIC_DIST_GICD_IPRIORITYR96_OFST 0x580
13411 
13412 /*
13413  * Register : GICD_IPRIORITYR97
13414  *
13415  * Interrupt Priority Registers
13416  *
13417  * Register Layout
13418  *
13419  * Bits | Access | Reset | Description
13420  * :-------|:-------|:------|:------------
13421  * [31:0] | RW | 0x0 | Empty
13422  *
13423  */
13424 /*
13425  * Field : Empty - fld
13426  *
13427  * Placeholder
13428  *
13429  * Field Access Macros:
13430  *
13431  */
13432 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR97_FLD register field. */
13433 #define ALT_GIC_DIST_GICD_IPRIORITYR97_FLD_LSB 0
13434 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR97_FLD register field. */
13435 #define ALT_GIC_DIST_GICD_IPRIORITYR97_FLD_MSB 31
13436 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR97_FLD register field. */
13437 #define ALT_GIC_DIST_GICD_IPRIORITYR97_FLD_WIDTH 32
13438 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR97_FLD register field value. */
13439 #define ALT_GIC_DIST_GICD_IPRIORITYR97_FLD_SET_MSK 0xffffffff
13440 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR97_FLD register field value. */
13441 #define ALT_GIC_DIST_GICD_IPRIORITYR97_FLD_CLR_MSK 0x00000000
13442 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR97_FLD register field. */
13443 #define ALT_GIC_DIST_GICD_IPRIORITYR97_FLD_RESET 0x0
13444 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR97_FLD field value from a register. */
13445 #define ALT_GIC_DIST_GICD_IPRIORITYR97_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13446 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR97_FLD register field value suitable for setting the register. */
13447 #define ALT_GIC_DIST_GICD_IPRIORITYR97_FLD_SET(value) (((value) << 0) & 0xffffffff)
13448 
13449 #ifndef __ASSEMBLY__
13450 /*
13451  * WARNING: The C register and register group struct declarations are provided for
13452  * convenience and illustrative purposes. They should, however, be used with
13453  * caution as the C language standard provides no guarantees about the alignment or
13454  * atomicity of device memory accesses. The recommended practice for coding device
13455  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13456  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13457  * alt_write_dword() functions for 64 bit registers.
13458  *
13459  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR97.
13460  */
13461 struct ALT_GIC_DIST_GICD_IPRIORITYR97_s
13462 {
13463  volatile uint32_t fld : 32; /* Empty */
13464 };
13465 
13466 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR97. */
13467 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR97_s ALT_GIC_DIST_GICD_IPRIORITYR97_t;
13468 #endif /* __ASSEMBLY__ */
13469 
13470 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR97 register. */
13471 #define ALT_GIC_DIST_GICD_IPRIORITYR97_RESET 0x00000000
13472 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR97 register from the beginning of the component. */
13473 #define ALT_GIC_DIST_GICD_IPRIORITYR97_OFST 0x584
13474 
13475 /*
13476  * Register : GICD_IPRIORITYR98
13477  *
13478  * Interrupt Priority Registers
13479  *
13480  * Register Layout
13481  *
13482  * Bits | Access | Reset | Description
13483  * :-------|:-------|:------|:------------
13484  * [31:0] | RW | 0x0 | Empty
13485  *
13486  */
13487 /*
13488  * Field : Empty - fld
13489  *
13490  * Placeholder
13491  *
13492  * Field Access Macros:
13493  *
13494  */
13495 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR98_FLD register field. */
13496 #define ALT_GIC_DIST_GICD_IPRIORITYR98_FLD_LSB 0
13497 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR98_FLD register field. */
13498 #define ALT_GIC_DIST_GICD_IPRIORITYR98_FLD_MSB 31
13499 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR98_FLD register field. */
13500 #define ALT_GIC_DIST_GICD_IPRIORITYR98_FLD_WIDTH 32
13501 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR98_FLD register field value. */
13502 #define ALT_GIC_DIST_GICD_IPRIORITYR98_FLD_SET_MSK 0xffffffff
13503 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR98_FLD register field value. */
13504 #define ALT_GIC_DIST_GICD_IPRIORITYR98_FLD_CLR_MSK 0x00000000
13505 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR98_FLD register field. */
13506 #define ALT_GIC_DIST_GICD_IPRIORITYR98_FLD_RESET 0x0
13507 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR98_FLD field value from a register. */
13508 #define ALT_GIC_DIST_GICD_IPRIORITYR98_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13509 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR98_FLD register field value suitable for setting the register. */
13510 #define ALT_GIC_DIST_GICD_IPRIORITYR98_FLD_SET(value) (((value) << 0) & 0xffffffff)
13511 
13512 #ifndef __ASSEMBLY__
13513 /*
13514  * WARNING: The C register and register group struct declarations are provided for
13515  * convenience and illustrative purposes. They should, however, be used with
13516  * caution as the C language standard provides no guarantees about the alignment or
13517  * atomicity of device memory accesses. The recommended practice for coding device
13518  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13519  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13520  * alt_write_dword() functions for 64 bit registers.
13521  *
13522  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR98.
13523  */
13524 struct ALT_GIC_DIST_GICD_IPRIORITYR98_s
13525 {
13526  volatile uint32_t fld : 32; /* Empty */
13527 };
13528 
13529 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR98. */
13530 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR98_s ALT_GIC_DIST_GICD_IPRIORITYR98_t;
13531 #endif /* __ASSEMBLY__ */
13532 
13533 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR98 register. */
13534 #define ALT_GIC_DIST_GICD_IPRIORITYR98_RESET 0x00000000
13535 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR98 register from the beginning of the component. */
13536 #define ALT_GIC_DIST_GICD_IPRIORITYR98_OFST 0x588
13537 
13538 /*
13539  * Register : GICD_IPRIORITYR99
13540  *
13541  * Interrupt Priority Registers
13542  *
13543  * Register Layout
13544  *
13545  * Bits | Access | Reset | Description
13546  * :-------|:-------|:------|:------------
13547  * [31:0] | RW | 0x0 | Empty
13548  *
13549  */
13550 /*
13551  * Field : Empty - fld
13552  *
13553  * Placeholder
13554  *
13555  * Field Access Macros:
13556  *
13557  */
13558 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR99_FLD register field. */
13559 #define ALT_GIC_DIST_GICD_IPRIORITYR99_FLD_LSB 0
13560 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR99_FLD register field. */
13561 #define ALT_GIC_DIST_GICD_IPRIORITYR99_FLD_MSB 31
13562 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR99_FLD register field. */
13563 #define ALT_GIC_DIST_GICD_IPRIORITYR99_FLD_WIDTH 32
13564 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR99_FLD register field value. */
13565 #define ALT_GIC_DIST_GICD_IPRIORITYR99_FLD_SET_MSK 0xffffffff
13566 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR99_FLD register field value. */
13567 #define ALT_GIC_DIST_GICD_IPRIORITYR99_FLD_CLR_MSK 0x00000000
13568 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR99_FLD register field. */
13569 #define ALT_GIC_DIST_GICD_IPRIORITYR99_FLD_RESET 0x0
13570 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR99_FLD field value from a register. */
13571 #define ALT_GIC_DIST_GICD_IPRIORITYR99_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13572 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR99_FLD register field value suitable for setting the register. */
13573 #define ALT_GIC_DIST_GICD_IPRIORITYR99_FLD_SET(value) (((value) << 0) & 0xffffffff)
13574 
13575 #ifndef __ASSEMBLY__
13576 /*
13577  * WARNING: The C register and register group struct declarations are provided for
13578  * convenience and illustrative purposes. They should, however, be used with
13579  * caution as the C language standard provides no guarantees about the alignment or
13580  * atomicity of device memory accesses. The recommended practice for coding device
13581  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13582  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13583  * alt_write_dword() functions for 64 bit registers.
13584  *
13585  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR99.
13586  */
13587 struct ALT_GIC_DIST_GICD_IPRIORITYR99_s
13588 {
13589  volatile uint32_t fld : 32; /* Empty */
13590 };
13591 
13592 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR99. */
13593 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR99_s ALT_GIC_DIST_GICD_IPRIORITYR99_t;
13594 #endif /* __ASSEMBLY__ */
13595 
13596 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR99 register. */
13597 #define ALT_GIC_DIST_GICD_IPRIORITYR99_RESET 0x00000000
13598 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR99 register from the beginning of the component. */
13599 #define ALT_GIC_DIST_GICD_IPRIORITYR99_OFST 0x58c
13600 
13601 /*
13602  * Register : GICD_IPRIORITYR100
13603  *
13604  * Interrupt Priority Registers
13605  *
13606  * Register Layout
13607  *
13608  * Bits | Access | Reset | Description
13609  * :-------|:-------|:------|:------------
13610  * [31:0] | RW | 0x0 | Empty
13611  *
13612  */
13613 /*
13614  * Field : Empty - fld
13615  *
13616  * Placeholder
13617  *
13618  * Field Access Macros:
13619  *
13620  */
13621 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR100_FLD register field. */
13622 #define ALT_GIC_DIST_GICD_IPRIORITYR100_FLD_LSB 0
13623 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR100_FLD register field. */
13624 #define ALT_GIC_DIST_GICD_IPRIORITYR100_FLD_MSB 31
13625 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR100_FLD register field. */
13626 #define ALT_GIC_DIST_GICD_IPRIORITYR100_FLD_WIDTH 32
13627 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR100_FLD register field value. */
13628 #define ALT_GIC_DIST_GICD_IPRIORITYR100_FLD_SET_MSK 0xffffffff
13629 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR100_FLD register field value. */
13630 #define ALT_GIC_DIST_GICD_IPRIORITYR100_FLD_CLR_MSK 0x00000000
13631 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR100_FLD register field. */
13632 #define ALT_GIC_DIST_GICD_IPRIORITYR100_FLD_RESET 0x0
13633 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR100_FLD field value from a register. */
13634 #define ALT_GIC_DIST_GICD_IPRIORITYR100_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13635 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR100_FLD register field value suitable for setting the register. */
13636 #define ALT_GIC_DIST_GICD_IPRIORITYR100_FLD_SET(value) (((value) << 0) & 0xffffffff)
13637 
13638 #ifndef __ASSEMBLY__
13639 /*
13640  * WARNING: The C register and register group struct declarations are provided for
13641  * convenience and illustrative purposes. They should, however, be used with
13642  * caution as the C language standard provides no guarantees about the alignment or
13643  * atomicity of device memory accesses. The recommended practice for coding device
13644  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13645  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13646  * alt_write_dword() functions for 64 bit registers.
13647  *
13648  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR100.
13649  */
13650 struct ALT_GIC_DIST_GICD_IPRIORITYR100_s
13651 {
13652  volatile uint32_t fld : 32; /* Empty */
13653 };
13654 
13655 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR100. */
13656 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR100_s ALT_GIC_DIST_GICD_IPRIORITYR100_t;
13657 #endif /* __ASSEMBLY__ */
13658 
13659 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR100 register. */
13660 #define ALT_GIC_DIST_GICD_IPRIORITYR100_RESET 0x00000000
13661 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR100 register from the beginning of the component. */
13662 #define ALT_GIC_DIST_GICD_IPRIORITYR100_OFST 0x590
13663 
13664 /*
13665  * Register : GICD_IPRIORITYR101
13666  *
13667  * Interrupt Priority Registers
13668  *
13669  * Register Layout
13670  *
13671  * Bits | Access | Reset | Description
13672  * :-------|:-------|:------|:------------
13673  * [31:0] | RW | 0x0 | Empty
13674  *
13675  */
13676 /*
13677  * Field : Empty - fld
13678  *
13679  * Placeholder
13680  *
13681  * Field Access Macros:
13682  *
13683  */
13684 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR101_FLD register field. */
13685 #define ALT_GIC_DIST_GICD_IPRIORITYR101_FLD_LSB 0
13686 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR101_FLD register field. */
13687 #define ALT_GIC_DIST_GICD_IPRIORITYR101_FLD_MSB 31
13688 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR101_FLD register field. */
13689 #define ALT_GIC_DIST_GICD_IPRIORITYR101_FLD_WIDTH 32
13690 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR101_FLD register field value. */
13691 #define ALT_GIC_DIST_GICD_IPRIORITYR101_FLD_SET_MSK 0xffffffff
13692 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR101_FLD register field value. */
13693 #define ALT_GIC_DIST_GICD_IPRIORITYR101_FLD_CLR_MSK 0x00000000
13694 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR101_FLD register field. */
13695 #define ALT_GIC_DIST_GICD_IPRIORITYR101_FLD_RESET 0x0
13696 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR101_FLD field value from a register. */
13697 #define ALT_GIC_DIST_GICD_IPRIORITYR101_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13698 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR101_FLD register field value suitable for setting the register. */
13699 #define ALT_GIC_DIST_GICD_IPRIORITYR101_FLD_SET(value) (((value) << 0) & 0xffffffff)
13700 
13701 #ifndef __ASSEMBLY__
13702 /*
13703  * WARNING: The C register and register group struct declarations are provided for
13704  * convenience and illustrative purposes. They should, however, be used with
13705  * caution as the C language standard provides no guarantees about the alignment or
13706  * atomicity of device memory accesses. The recommended practice for coding device
13707  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13708  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13709  * alt_write_dword() functions for 64 bit registers.
13710  *
13711  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR101.
13712  */
13713 struct ALT_GIC_DIST_GICD_IPRIORITYR101_s
13714 {
13715  volatile uint32_t fld : 32; /* Empty */
13716 };
13717 
13718 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR101. */
13719 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR101_s ALT_GIC_DIST_GICD_IPRIORITYR101_t;
13720 #endif /* __ASSEMBLY__ */
13721 
13722 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR101 register. */
13723 #define ALT_GIC_DIST_GICD_IPRIORITYR101_RESET 0x00000000
13724 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR101 register from the beginning of the component. */
13725 #define ALT_GIC_DIST_GICD_IPRIORITYR101_OFST 0x594
13726 
13727 /*
13728  * Register : GICD_IPRIORITYR102
13729  *
13730  * Interrupt Priority Registers
13731  *
13732  * Register Layout
13733  *
13734  * Bits | Access | Reset | Description
13735  * :-------|:-------|:------|:------------
13736  * [31:0] | RW | 0x0 | Empty
13737  *
13738  */
13739 /*
13740  * Field : Empty - fld
13741  *
13742  * Placeholder
13743  *
13744  * Field Access Macros:
13745  *
13746  */
13747 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR102_FLD register field. */
13748 #define ALT_GIC_DIST_GICD_IPRIORITYR102_FLD_LSB 0
13749 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR102_FLD register field. */
13750 #define ALT_GIC_DIST_GICD_IPRIORITYR102_FLD_MSB 31
13751 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR102_FLD register field. */
13752 #define ALT_GIC_DIST_GICD_IPRIORITYR102_FLD_WIDTH 32
13753 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR102_FLD register field value. */
13754 #define ALT_GIC_DIST_GICD_IPRIORITYR102_FLD_SET_MSK 0xffffffff
13755 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR102_FLD register field value. */
13756 #define ALT_GIC_DIST_GICD_IPRIORITYR102_FLD_CLR_MSK 0x00000000
13757 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR102_FLD register field. */
13758 #define ALT_GIC_DIST_GICD_IPRIORITYR102_FLD_RESET 0x0
13759 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR102_FLD field value from a register. */
13760 #define ALT_GIC_DIST_GICD_IPRIORITYR102_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13761 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR102_FLD register field value suitable for setting the register. */
13762 #define ALT_GIC_DIST_GICD_IPRIORITYR102_FLD_SET(value) (((value) << 0) & 0xffffffff)
13763 
13764 #ifndef __ASSEMBLY__
13765 /*
13766  * WARNING: The C register and register group struct declarations are provided for
13767  * convenience and illustrative purposes. They should, however, be used with
13768  * caution as the C language standard provides no guarantees about the alignment or
13769  * atomicity of device memory accesses. The recommended practice for coding device
13770  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13771  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13772  * alt_write_dword() functions for 64 bit registers.
13773  *
13774  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR102.
13775  */
13776 struct ALT_GIC_DIST_GICD_IPRIORITYR102_s
13777 {
13778  volatile uint32_t fld : 32; /* Empty */
13779 };
13780 
13781 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR102. */
13782 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR102_s ALT_GIC_DIST_GICD_IPRIORITYR102_t;
13783 #endif /* __ASSEMBLY__ */
13784 
13785 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR102 register. */
13786 #define ALT_GIC_DIST_GICD_IPRIORITYR102_RESET 0x00000000
13787 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR102 register from the beginning of the component. */
13788 #define ALT_GIC_DIST_GICD_IPRIORITYR102_OFST 0x598
13789 
13790 /*
13791  * Register : GICD_IPRIORITYR103
13792  *
13793  * Interrupt Priority Registers
13794  *
13795  * Register Layout
13796  *
13797  * Bits | Access | Reset | Description
13798  * :-------|:-------|:------|:------------
13799  * [31:0] | RW | 0x0 | Empty
13800  *
13801  */
13802 /*
13803  * Field : Empty - fld
13804  *
13805  * Placeholder
13806  *
13807  * Field Access Macros:
13808  *
13809  */
13810 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR103_FLD register field. */
13811 #define ALT_GIC_DIST_GICD_IPRIORITYR103_FLD_LSB 0
13812 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR103_FLD register field. */
13813 #define ALT_GIC_DIST_GICD_IPRIORITYR103_FLD_MSB 31
13814 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR103_FLD register field. */
13815 #define ALT_GIC_DIST_GICD_IPRIORITYR103_FLD_WIDTH 32
13816 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR103_FLD register field value. */
13817 #define ALT_GIC_DIST_GICD_IPRIORITYR103_FLD_SET_MSK 0xffffffff
13818 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR103_FLD register field value. */
13819 #define ALT_GIC_DIST_GICD_IPRIORITYR103_FLD_CLR_MSK 0x00000000
13820 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR103_FLD register field. */
13821 #define ALT_GIC_DIST_GICD_IPRIORITYR103_FLD_RESET 0x0
13822 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR103_FLD field value from a register. */
13823 #define ALT_GIC_DIST_GICD_IPRIORITYR103_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13824 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR103_FLD register field value suitable for setting the register. */
13825 #define ALT_GIC_DIST_GICD_IPRIORITYR103_FLD_SET(value) (((value) << 0) & 0xffffffff)
13826 
13827 #ifndef __ASSEMBLY__
13828 /*
13829  * WARNING: The C register and register group struct declarations are provided for
13830  * convenience and illustrative purposes. They should, however, be used with
13831  * caution as the C language standard provides no guarantees about the alignment or
13832  * atomicity of device memory accesses. The recommended practice for coding device
13833  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13834  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13835  * alt_write_dword() functions for 64 bit registers.
13836  *
13837  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR103.
13838  */
13839 struct ALT_GIC_DIST_GICD_IPRIORITYR103_s
13840 {
13841  volatile uint32_t fld : 32; /* Empty */
13842 };
13843 
13844 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR103. */
13845 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR103_s ALT_GIC_DIST_GICD_IPRIORITYR103_t;
13846 #endif /* __ASSEMBLY__ */
13847 
13848 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR103 register. */
13849 #define ALT_GIC_DIST_GICD_IPRIORITYR103_RESET 0x00000000
13850 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR103 register from the beginning of the component. */
13851 #define ALT_GIC_DIST_GICD_IPRIORITYR103_OFST 0x59c
13852 
13853 /*
13854  * Register : GICD_IPRIORITYR104
13855  *
13856  * Interrupt Priority Registers
13857  *
13858  * Register Layout
13859  *
13860  * Bits | Access | Reset | Description
13861  * :-------|:-------|:------|:------------
13862  * [31:0] | RW | 0x0 | Empty
13863  *
13864  */
13865 /*
13866  * Field : Empty - fld
13867  *
13868  * Placeholder
13869  *
13870  * Field Access Macros:
13871  *
13872  */
13873 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR104_FLD register field. */
13874 #define ALT_GIC_DIST_GICD_IPRIORITYR104_FLD_LSB 0
13875 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR104_FLD register field. */
13876 #define ALT_GIC_DIST_GICD_IPRIORITYR104_FLD_MSB 31
13877 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR104_FLD register field. */
13878 #define ALT_GIC_DIST_GICD_IPRIORITYR104_FLD_WIDTH 32
13879 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR104_FLD register field value. */
13880 #define ALT_GIC_DIST_GICD_IPRIORITYR104_FLD_SET_MSK 0xffffffff
13881 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR104_FLD register field value. */
13882 #define ALT_GIC_DIST_GICD_IPRIORITYR104_FLD_CLR_MSK 0x00000000
13883 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR104_FLD register field. */
13884 #define ALT_GIC_DIST_GICD_IPRIORITYR104_FLD_RESET 0x0
13885 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR104_FLD field value from a register. */
13886 #define ALT_GIC_DIST_GICD_IPRIORITYR104_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13887 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR104_FLD register field value suitable for setting the register. */
13888 #define ALT_GIC_DIST_GICD_IPRIORITYR104_FLD_SET(value) (((value) << 0) & 0xffffffff)
13889 
13890 #ifndef __ASSEMBLY__
13891 /*
13892  * WARNING: The C register and register group struct declarations are provided for
13893  * convenience and illustrative purposes. They should, however, be used with
13894  * caution as the C language standard provides no guarantees about the alignment or
13895  * atomicity of device memory accesses. The recommended practice for coding device
13896  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13897  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13898  * alt_write_dword() functions for 64 bit registers.
13899  *
13900  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR104.
13901  */
13902 struct ALT_GIC_DIST_GICD_IPRIORITYR104_s
13903 {
13904  volatile uint32_t fld : 32; /* Empty */
13905 };
13906 
13907 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR104. */
13908 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR104_s ALT_GIC_DIST_GICD_IPRIORITYR104_t;
13909 #endif /* __ASSEMBLY__ */
13910 
13911 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR104 register. */
13912 #define ALT_GIC_DIST_GICD_IPRIORITYR104_RESET 0x00000000
13913 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR104 register from the beginning of the component. */
13914 #define ALT_GIC_DIST_GICD_IPRIORITYR104_OFST 0x5a0
13915 
13916 /*
13917  * Register : GICD_IPRIORITYR105
13918  *
13919  * Interrupt Priority Registers
13920  *
13921  * Register Layout
13922  *
13923  * Bits | Access | Reset | Description
13924  * :-------|:-------|:------|:------------
13925  * [31:0] | RW | 0x0 | Empty
13926  *
13927  */
13928 /*
13929  * Field : Empty - fld
13930  *
13931  * Placeholder
13932  *
13933  * Field Access Macros:
13934  *
13935  */
13936 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR105_FLD register field. */
13937 #define ALT_GIC_DIST_GICD_IPRIORITYR105_FLD_LSB 0
13938 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR105_FLD register field. */
13939 #define ALT_GIC_DIST_GICD_IPRIORITYR105_FLD_MSB 31
13940 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR105_FLD register field. */
13941 #define ALT_GIC_DIST_GICD_IPRIORITYR105_FLD_WIDTH 32
13942 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR105_FLD register field value. */
13943 #define ALT_GIC_DIST_GICD_IPRIORITYR105_FLD_SET_MSK 0xffffffff
13944 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR105_FLD register field value. */
13945 #define ALT_GIC_DIST_GICD_IPRIORITYR105_FLD_CLR_MSK 0x00000000
13946 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR105_FLD register field. */
13947 #define ALT_GIC_DIST_GICD_IPRIORITYR105_FLD_RESET 0x0
13948 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR105_FLD field value from a register. */
13949 #define ALT_GIC_DIST_GICD_IPRIORITYR105_FLD_GET(value) (((value) & 0xffffffff) >> 0)
13950 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR105_FLD register field value suitable for setting the register. */
13951 #define ALT_GIC_DIST_GICD_IPRIORITYR105_FLD_SET(value) (((value) << 0) & 0xffffffff)
13952 
13953 #ifndef __ASSEMBLY__
13954 /*
13955  * WARNING: The C register and register group struct declarations are provided for
13956  * convenience and illustrative purposes. They should, however, be used with
13957  * caution as the C language standard provides no guarantees about the alignment or
13958  * atomicity of device memory accesses. The recommended practice for coding device
13959  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13960  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13961  * alt_write_dword() functions for 64 bit registers.
13962  *
13963  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR105.
13964  */
13965 struct ALT_GIC_DIST_GICD_IPRIORITYR105_s
13966 {
13967  volatile uint32_t fld : 32; /* Empty */
13968 };
13969 
13970 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR105. */
13971 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR105_s ALT_GIC_DIST_GICD_IPRIORITYR105_t;
13972 #endif /* __ASSEMBLY__ */
13973 
13974 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR105 register. */
13975 #define ALT_GIC_DIST_GICD_IPRIORITYR105_RESET 0x00000000
13976 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR105 register from the beginning of the component. */
13977 #define ALT_GIC_DIST_GICD_IPRIORITYR105_OFST 0x5a4
13978 
13979 /*
13980  * Register : GICD_IPRIORITYR106
13981  *
13982  * Interrupt Priority Registers
13983  *
13984  * Register Layout
13985  *
13986  * Bits | Access | Reset | Description
13987  * :-------|:-------|:------|:------------
13988  * [31:0] | RW | 0x0 | Empty
13989  *
13990  */
13991 /*
13992  * Field : Empty - fld
13993  *
13994  * Placeholder
13995  *
13996  * Field Access Macros:
13997  *
13998  */
13999 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR106_FLD register field. */
14000 #define ALT_GIC_DIST_GICD_IPRIORITYR106_FLD_LSB 0
14001 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR106_FLD register field. */
14002 #define ALT_GIC_DIST_GICD_IPRIORITYR106_FLD_MSB 31
14003 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR106_FLD register field. */
14004 #define ALT_GIC_DIST_GICD_IPRIORITYR106_FLD_WIDTH 32
14005 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR106_FLD register field value. */
14006 #define ALT_GIC_DIST_GICD_IPRIORITYR106_FLD_SET_MSK 0xffffffff
14007 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR106_FLD register field value. */
14008 #define ALT_GIC_DIST_GICD_IPRIORITYR106_FLD_CLR_MSK 0x00000000
14009 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR106_FLD register field. */
14010 #define ALT_GIC_DIST_GICD_IPRIORITYR106_FLD_RESET 0x0
14011 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR106_FLD field value from a register. */
14012 #define ALT_GIC_DIST_GICD_IPRIORITYR106_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14013 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR106_FLD register field value suitable for setting the register. */
14014 #define ALT_GIC_DIST_GICD_IPRIORITYR106_FLD_SET(value) (((value) << 0) & 0xffffffff)
14015 
14016 #ifndef __ASSEMBLY__
14017 /*
14018  * WARNING: The C register and register group struct declarations are provided for
14019  * convenience and illustrative purposes. They should, however, be used with
14020  * caution as the C language standard provides no guarantees about the alignment or
14021  * atomicity of device memory accesses. The recommended practice for coding device
14022  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14023  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14024  * alt_write_dword() functions for 64 bit registers.
14025  *
14026  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR106.
14027  */
14028 struct ALT_GIC_DIST_GICD_IPRIORITYR106_s
14029 {
14030  volatile uint32_t fld : 32; /* Empty */
14031 };
14032 
14033 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR106. */
14034 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR106_s ALT_GIC_DIST_GICD_IPRIORITYR106_t;
14035 #endif /* __ASSEMBLY__ */
14036 
14037 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR106 register. */
14038 #define ALT_GIC_DIST_GICD_IPRIORITYR106_RESET 0x00000000
14039 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR106 register from the beginning of the component. */
14040 #define ALT_GIC_DIST_GICD_IPRIORITYR106_OFST 0x5a8
14041 
14042 /*
14043  * Register : GICD_IPRIORITYR107
14044  *
14045  * Interrupt Priority Registers
14046  *
14047  * Register Layout
14048  *
14049  * Bits | Access | Reset | Description
14050  * :-------|:-------|:------|:------------
14051  * [31:0] | RW | 0x0 | Empty
14052  *
14053  */
14054 /*
14055  * Field : Empty - fld
14056  *
14057  * Placeholder
14058  *
14059  * Field Access Macros:
14060  *
14061  */
14062 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR107_FLD register field. */
14063 #define ALT_GIC_DIST_GICD_IPRIORITYR107_FLD_LSB 0
14064 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR107_FLD register field. */
14065 #define ALT_GIC_DIST_GICD_IPRIORITYR107_FLD_MSB 31
14066 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR107_FLD register field. */
14067 #define ALT_GIC_DIST_GICD_IPRIORITYR107_FLD_WIDTH 32
14068 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR107_FLD register field value. */
14069 #define ALT_GIC_DIST_GICD_IPRIORITYR107_FLD_SET_MSK 0xffffffff
14070 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR107_FLD register field value. */
14071 #define ALT_GIC_DIST_GICD_IPRIORITYR107_FLD_CLR_MSK 0x00000000
14072 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR107_FLD register field. */
14073 #define ALT_GIC_DIST_GICD_IPRIORITYR107_FLD_RESET 0x0
14074 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR107_FLD field value from a register. */
14075 #define ALT_GIC_DIST_GICD_IPRIORITYR107_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14076 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR107_FLD register field value suitable for setting the register. */
14077 #define ALT_GIC_DIST_GICD_IPRIORITYR107_FLD_SET(value) (((value) << 0) & 0xffffffff)
14078 
14079 #ifndef __ASSEMBLY__
14080 /*
14081  * WARNING: The C register and register group struct declarations are provided for
14082  * convenience and illustrative purposes. They should, however, be used with
14083  * caution as the C language standard provides no guarantees about the alignment or
14084  * atomicity of device memory accesses. The recommended practice for coding device
14085  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14086  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14087  * alt_write_dword() functions for 64 bit registers.
14088  *
14089  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR107.
14090  */
14091 struct ALT_GIC_DIST_GICD_IPRIORITYR107_s
14092 {
14093  volatile uint32_t fld : 32; /* Empty */
14094 };
14095 
14096 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR107. */
14097 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR107_s ALT_GIC_DIST_GICD_IPRIORITYR107_t;
14098 #endif /* __ASSEMBLY__ */
14099 
14100 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR107 register. */
14101 #define ALT_GIC_DIST_GICD_IPRIORITYR107_RESET 0x00000000
14102 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR107 register from the beginning of the component. */
14103 #define ALT_GIC_DIST_GICD_IPRIORITYR107_OFST 0x5ac
14104 
14105 /*
14106  * Register : GICD_IPRIORITYR108
14107  *
14108  * Interrupt Priority Registers
14109  *
14110  * Register Layout
14111  *
14112  * Bits | Access | Reset | Description
14113  * :-------|:-------|:------|:------------
14114  * [31:0] | RW | 0x0 | Empty
14115  *
14116  */
14117 /*
14118  * Field : Empty - fld
14119  *
14120  * Placeholder
14121  *
14122  * Field Access Macros:
14123  *
14124  */
14125 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR108_FLD register field. */
14126 #define ALT_GIC_DIST_GICD_IPRIORITYR108_FLD_LSB 0
14127 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR108_FLD register field. */
14128 #define ALT_GIC_DIST_GICD_IPRIORITYR108_FLD_MSB 31
14129 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR108_FLD register field. */
14130 #define ALT_GIC_DIST_GICD_IPRIORITYR108_FLD_WIDTH 32
14131 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR108_FLD register field value. */
14132 #define ALT_GIC_DIST_GICD_IPRIORITYR108_FLD_SET_MSK 0xffffffff
14133 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR108_FLD register field value. */
14134 #define ALT_GIC_DIST_GICD_IPRIORITYR108_FLD_CLR_MSK 0x00000000
14135 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR108_FLD register field. */
14136 #define ALT_GIC_DIST_GICD_IPRIORITYR108_FLD_RESET 0x0
14137 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR108_FLD field value from a register. */
14138 #define ALT_GIC_DIST_GICD_IPRIORITYR108_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14139 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR108_FLD register field value suitable for setting the register. */
14140 #define ALT_GIC_DIST_GICD_IPRIORITYR108_FLD_SET(value) (((value) << 0) & 0xffffffff)
14141 
14142 #ifndef __ASSEMBLY__
14143 /*
14144  * WARNING: The C register and register group struct declarations are provided for
14145  * convenience and illustrative purposes. They should, however, be used with
14146  * caution as the C language standard provides no guarantees about the alignment or
14147  * atomicity of device memory accesses. The recommended practice for coding device
14148  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14149  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14150  * alt_write_dword() functions for 64 bit registers.
14151  *
14152  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR108.
14153  */
14154 struct ALT_GIC_DIST_GICD_IPRIORITYR108_s
14155 {
14156  volatile uint32_t fld : 32; /* Empty */
14157 };
14158 
14159 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR108. */
14160 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR108_s ALT_GIC_DIST_GICD_IPRIORITYR108_t;
14161 #endif /* __ASSEMBLY__ */
14162 
14163 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR108 register. */
14164 #define ALT_GIC_DIST_GICD_IPRIORITYR108_RESET 0x00000000
14165 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR108 register from the beginning of the component. */
14166 #define ALT_GIC_DIST_GICD_IPRIORITYR108_OFST 0x5b0
14167 
14168 /*
14169  * Register : GICD_IPRIORITYR109
14170  *
14171  * Interrupt Priority Registers
14172  *
14173  * Register Layout
14174  *
14175  * Bits | Access | Reset | Description
14176  * :-------|:-------|:------|:------------
14177  * [31:0] | RW | 0x0 | Empty
14178  *
14179  */
14180 /*
14181  * Field : Empty - fld
14182  *
14183  * Placeholder
14184  *
14185  * Field Access Macros:
14186  *
14187  */
14188 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR109_FLD register field. */
14189 #define ALT_GIC_DIST_GICD_IPRIORITYR109_FLD_LSB 0
14190 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR109_FLD register field. */
14191 #define ALT_GIC_DIST_GICD_IPRIORITYR109_FLD_MSB 31
14192 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR109_FLD register field. */
14193 #define ALT_GIC_DIST_GICD_IPRIORITYR109_FLD_WIDTH 32
14194 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR109_FLD register field value. */
14195 #define ALT_GIC_DIST_GICD_IPRIORITYR109_FLD_SET_MSK 0xffffffff
14196 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR109_FLD register field value. */
14197 #define ALT_GIC_DIST_GICD_IPRIORITYR109_FLD_CLR_MSK 0x00000000
14198 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR109_FLD register field. */
14199 #define ALT_GIC_DIST_GICD_IPRIORITYR109_FLD_RESET 0x0
14200 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR109_FLD field value from a register. */
14201 #define ALT_GIC_DIST_GICD_IPRIORITYR109_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14202 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR109_FLD register field value suitable for setting the register. */
14203 #define ALT_GIC_DIST_GICD_IPRIORITYR109_FLD_SET(value) (((value) << 0) & 0xffffffff)
14204 
14205 #ifndef __ASSEMBLY__
14206 /*
14207  * WARNING: The C register and register group struct declarations are provided for
14208  * convenience and illustrative purposes. They should, however, be used with
14209  * caution as the C language standard provides no guarantees about the alignment or
14210  * atomicity of device memory accesses. The recommended practice for coding device
14211  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14212  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14213  * alt_write_dword() functions for 64 bit registers.
14214  *
14215  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR109.
14216  */
14217 struct ALT_GIC_DIST_GICD_IPRIORITYR109_s
14218 {
14219  volatile uint32_t fld : 32; /* Empty */
14220 };
14221 
14222 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR109. */
14223 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR109_s ALT_GIC_DIST_GICD_IPRIORITYR109_t;
14224 #endif /* __ASSEMBLY__ */
14225 
14226 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR109 register. */
14227 #define ALT_GIC_DIST_GICD_IPRIORITYR109_RESET 0x00000000
14228 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR109 register from the beginning of the component. */
14229 #define ALT_GIC_DIST_GICD_IPRIORITYR109_OFST 0x5b4
14230 
14231 /*
14232  * Register : GICD_IPRIORITYR110
14233  *
14234  * Interrupt Priority Registers
14235  *
14236  * Register Layout
14237  *
14238  * Bits | Access | Reset | Description
14239  * :-------|:-------|:------|:------------
14240  * [31:0] | RW | 0x0 | Empty
14241  *
14242  */
14243 /*
14244  * Field : Empty - fld
14245  *
14246  * Placeholder
14247  *
14248  * Field Access Macros:
14249  *
14250  */
14251 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR110_FLD register field. */
14252 #define ALT_GIC_DIST_GICD_IPRIORITYR110_FLD_LSB 0
14253 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR110_FLD register field. */
14254 #define ALT_GIC_DIST_GICD_IPRIORITYR110_FLD_MSB 31
14255 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR110_FLD register field. */
14256 #define ALT_GIC_DIST_GICD_IPRIORITYR110_FLD_WIDTH 32
14257 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR110_FLD register field value. */
14258 #define ALT_GIC_DIST_GICD_IPRIORITYR110_FLD_SET_MSK 0xffffffff
14259 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR110_FLD register field value. */
14260 #define ALT_GIC_DIST_GICD_IPRIORITYR110_FLD_CLR_MSK 0x00000000
14261 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR110_FLD register field. */
14262 #define ALT_GIC_DIST_GICD_IPRIORITYR110_FLD_RESET 0x0
14263 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR110_FLD field value from a register. */
14264 #define ALT_GIC_DIST_GICD_IPRIORITYR110_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14265 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR110_FLD register field value suitable for setting the register. */
14266 #define ALT_GIC_DIST_GICD_IPRIORITYR110_FLD_SET(value) (((value) << 0) & 0xffffffff)
14267 
14268 #ifndef __ASSEMBLY__
14269 /*
14270  * WARNING: The C register and register group struct declarations are provided for
14271  * convenience and illustrative purposes. They should, however, be used with
14272  * caution as the C language standard provides no guarantees about the alignment or
14273  * atomicity of device memory accesses. The recommended practice for coding device
14274  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14275  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14276  * alt_write_dword() functions for 64 bit registers.
14277  *
14278  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR110.
14279  */
14280 struct ALT_GIC_DIST_GICD_IPRIORITYR110_s
14281 {
14282  volatile uint32_t fld : 32; /* Empty */
14283 };
14284 
14285 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR110. */
14286 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR110_s ALT_GIC_DIST_GICD_IPRIORITYR110_t;
14287 #endif /* __ASSEMBLY__ */
14288 
14289 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR110 register. */
14290 #define ALT_GIC_DIST_GICD_IPRIORITYR110_RESET 0x00000000
14291 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR110 register from the beginning of the component. */
14292 #define ALT_GIC_DIST_GICD_IPRIORITYR110_OFST 0x5b8
14293 
14294 /*
14295  * Register : GICD_IPRIORITYR111
14296  *
14297  * Interrupt Priority Registers
14298  *
14299  * Register Layout
14300  *
14301  * Bits | Access | Reset | Description
14302  * :-------|:-------|:------|:------------
14303  * [31:0] | RW | 0x0 | Empty
14304  *
14305  */
14306 /*
14307  * Field : Empty - fld
14308  *
14309  * Placeholder
14310  *
14311  * Field Access Macros:
14312  *
14313  */
14314 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR111_FLD register field. */
14315 #define ALT_GIC_DIST_GICD_IPRIORITYR111_FLD_LSB 0
14316 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR111_FLD register field. */
14317 #define ALT_GIC_DIST_GICD_IPRIORITYR111_FLD_MSB 31
14318 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR111_FLD register field. */
14319 #define ALT_GIC_DIST_GICD_IPRIORITYR111_FLD_WIDTH 32
14320 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR111_FLD register field value. */
14321 #define ALT_GIC_DIST_GICD_IPRIORITYR111_FLD_SET_MSK 0xffffffff
14322 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR111_FLD register field value. */
14323 #define ALT_GIC_DIST_GICD_IPRIORITYR111_FLD_CLR_MSK 0x00000000
14324 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR111_FLD register field. */
14325 #define ALT_GIC_DIST_GICD_IPRIORITYR111_FLD_RESET 0x0
14326 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR111_FLD field value from a register. */
14327 #define ALT_GIC_DIST_GICD_IPRIORITYR111_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14328 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR111_FLD register field value suitable for setting the register. */
14329 #define ALT_GIC_DIST_GICD_IPRIORITYR111_FLD_SET(value) (((value) << 0) & 0xffffffff)
14330 
14331 #ifndef __ASSEMBLY__
14332 /*
14333  * WARNING: The C register and register group struct declarations are provided for
14334  * convenience and illustrative purposes. They should, however, be used with
14335  * caution as the C language standard provides no guarantees about the alignment or
14336  * atomicity of device memory accesses. The recommended practice for coding device
14337  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14338  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14339  * alt_write_dword() functions for 64 bit registers.
14340  *
14341  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR111.
14342  */
14343 struct ALT_GIC_DIST_GICD_IPRIORITYR111_s
14344 {
14345  volatile uint32_t fld : 32; /* Empty */
14346 };
14347 
14348 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR111. */
14349 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR111_s ALT_GIC_DIST_GICD_IPRIORITYR111_t;
14350 #endif /* __ASSEMBLY__ */
14351 
14352 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR111 register. */
14353 #define ALT_GIC_DIST_GICD_IPRIORITYR111_RESET 0x00000000
14354 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR111 register from the beginning of the component. */
14355 #define ALT_GIC_DIST_GICD_IPRIORITYR111_OFST 0x5bc
14356 
14357 /*
14358  * Register : GICD_IPRIORITYR112
14359  *
14360  * Interrupt Priority Registers
14361  *
14362  * Register Layout
14363  *
14364  * Bits | Access | Reset | Description
14365  * :-------|:-------|:------|:------------
14366  * [31:0] | RW | 0x0 | Empty
14367  *
14368  */
14369 /*
14370  * Field : Empty - fld
14371  *
14372  * Placeholder
14373  *
14374  * Field Access Macros:
14375  *
14376  */
14377 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR112_FLD register field. */
14378 #define ALT_GIC_DIST_GICD_IPRIORITYR112_FLD_LSB 0
14379 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR112_FLD register field. */
14380 #define ALT_GIC_DIST_GICD_IPRIORITYR112_FLD_MSB 31
14381 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR112_FLD register field. */
14382 #define ALT_GIC_DIST_GICD_IPRIORITYR112_FLD_WIDTH 32
14383 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR112_FLD register field value. */
14384 #define ALT_GIC_DIST_GICD_IPRIORITYR112_FLD_SET_MSK 0xffffffff
14385 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR112_FLD register field value. */
14386 #define ALT_GIC_DIST_GICD_IPRIORITYR112_FLD_CLR_MSK 0x00000000
14387 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR112_FLD register field. */
14388 #define ALT_GIC_DIST_GICD_IPRIORITYR112_FLD_RESET 0x0
14389 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR112_FLD field value from a register. */
14390 #define ALT_GIC_DIST_GICD_IPRIORITYR112_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14391 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR112_FLD register field value suitable for setting the register. */
14392 #define ALT_GIC_DIST_GICD_IPRIORITYR112_FLD_SET(value) (((value) << 0) & 0xffffffff)
14393 
14394 #ifndef __ASSEMBLY__
14395 /*
14396  * WARNING: The C register and register group struct declarations are provided for
14397  * convenience and illustrative purposes. They should, however, be used with
14398  * caution as the C language standard provides no guarantees about the alignment or
14399  * atomicity of device memory accesses. The recommended practice for coding device
14400  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14401  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14402  * alt_write_dword() functions for 64 bit registers.
14403  *
14404  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR112.
14405  */
14406 struct ALT_GIC_DIST_GICD_IPRIORITYR112_s
14407 {
14408  volatile uint32_t fld : 32; /* Empty */
14409 };
14410 
14411 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR112. */
14412 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR112_s ALT_GIC_DIST_GICD_IPRIORITYR112_t;
14413 #endif /* __ASSEMBLY__ */
14414 
14415 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR112 register. */
14416 #define ALT_GIC_DIST_GICD_IPRIORITYR112_RESET 0x00000000
14417 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR112 register from the beginning of the component. */
14418 #define ALT_GIC_DIST_GICD_IPRIORITYR112_OFST 0x5c0
14419 
14420 /*
14421  * Register : GICD_IPRIORITYR113
14422  *
14423  * Interrupt Priority Registers
14424  *
14425  * Register Layout
14426  *
14427  * Bits | Access | Reset | Description
14428  * :-------|:-------|:------|:------------
14429  * [31:0] | RW | 0x0 | Empty
14430  *
14431  */
14432 /*
14433  * Field : Empty - fld
14434  *
14435  * Placeholder
14436  *
14437  * Field Access Macros:
14438  *
14439  */
14440 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR113_FLD register field. */
14441 #define ALT_GIC_DIST_GICD_IPRIORITYR113_FLD_LSB 0
14442 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR113_FLD register field. */
14443 #define ALT_GIC_DIST_GICD_IPRIORITYR113_FLD_MSB 31
14444 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR113_FLD register field. */
14445 #define ALT_GIC_DIST_GICD_IPRIORITYR113_FLD_WIDTH 32
14446 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR113_FLD register field value. */
14447 #define ALT_GIC_DIST_GICD_IPRIORITYR113_FLD_SET_MSK 0xffffffff
14448 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR113_FLD register field value. */
14449 #define ALT_GIC_DIST_GICD_IPRIORITYR113_FLD_CLR_MSK 0x00000000
14450 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR113_FLD register field. */
14451 #define ALT_GIC_DIST_GICD_IPRIORITYR113_FLD_RESET 0x0
14452 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR113_FLD field value from a register. */
14453 #define ALT_GIC_DIST_GICD_IPRIORITYR113_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14454 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR113_FLD register field value suitable for setting the register. */
14455 #define ALT_GIC_DIST_GICD_IPRIORITYR113_FLD_SET(value) (((value) << 0) & 0xffffffff)
14456 
14457 #ifndef __ASSEMBLY__
14458 /*
14459  * WARNING: The C register and register group struct declarations are provided for
14460  * convenience and illustrative purposes. They should, however, be used with
14461  * caution as the C language standard provides no guarantees about the alignment or
14462  * atomicity of device memory accesses. The recommended practice for coding device
14463  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14464  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14465  * alt_write_dword() functions for 64 bit registers.
14466  *
14467  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR113.
14468  */
14469 struct ALT_GIC_DIST_GICD_IPRIORITYR113_s
14470 {
14471  volatile uint32_t fld : 32; /* Empty */
14472 };
14473 
14474 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR113. */
14475 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR113_s ALT_GIC_DIST_GICD_IPRIORITYR113_t;
14476 #endif /* __ASSEMBLY__ */
14477 
14478 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR113 register. */
14479 #define ALT_GIC_DIST_GICD_IPRIORITYR113_RESET 0x00000000
14480 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR113 register from the beginning of the component. */
14481 #define ALT_GIC_DIST_GICD_IPRIORITYR113_OFST 0x5c4
14482 
14483 /*
14484  * Register : GICD_IPRIORITYR114
14485  *
14486  * Interrupt Priority Registers
14487  *
14488  * Register Layout
14489  *
14490  * Bits | Access | Reset | Description
14491  * :-------|:-------|:------|:------------
14492  * [31:0] | RW | 0x0 | Empty
14493  *
14494  */
14495 /*
14496  * Field : Empty - fld
14497  *
14498  * Placeholder
14499  *
14500  * Field Access Macros:
14501  *
14502  */
14503 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR114_FLD register field. */
14504 #define ALT_GIC_DIST_GICD_IPRIORITYR114_FLD_LSB 0
14505 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR114_FLD register field. */
14506 #define ALT_GIC_DIST_GICD_IPRIORITYR114_FLD_MSB 31
14507 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR114_FLD register field. */
14508 #define ALT_GIC_DIST_GICD_IPRIORITYR114_FLD_WIDTH 32
14509 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR114_FLD register field value. */
14510 #define ALT_GIC_DIST_GICD_IPRIORITYR114_FLD_SET_MSK 0xffffffff
14511 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR114_FLD register field value. */
14512 #define ALT_GIC_DIST_GICD_IPRIORITYR114_FLD_CLR_MSK 0x00000000
14513 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR114_FLD register field. */
14514 #define ALT_GIC_DIST_GICD_IPRIORITYR114_FLD_RESET 0x0
14515 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR114_FLD field value from a register. */
14516 #define ALT_GIC_DIST_GICD_IPRIORITYR114_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14517 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR114_FLD register field value suitable for setting the register. */
14518 #define ALT_GIC_DIST_GICD_IPRIORITYR114_FLD_SET(value) (((value) << 0) & 0xffffffff)
14519 
14520 #ifndef __ASSEMBLY__
14521 /*
14522  * WARNING: The C register and register group struct declarations are provided for
14523  * convenience and illustrative purposes. They should, however, be used with
14524  * caution as the C language standard provides no guarantees about the alignment or
14525  * atomicity of device memory accesses. The recommended practice for coding device
14526  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14527  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14528  * alt_write_dword() functions for 64 bit registers.
14529  *
14530  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR114.
14531  */
14532 struct ALT_GIC_DIST_GICD_IPRIORITYR114_s
14533 {
14534  volatile uint32_t fld : 32; /* Empty */
14535 };
14536 
14537 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR114. */
14538 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR114_s ALT_GIC_DIST_GICD_IPRIORITYR114_t;
14539 #endif /* __ASSEMBLY__ */
14540 
14541 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR114 register. */
14542 #define ALT_GIC_DIST_GICD_IPRIORITYR114_RESET 0x00000000
14543 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR114 register from the beginning of the component. */
14544 #define ALT_GIC_DIST_GICD_IPRIORITYR114_OFST 0x5c8
14545 
14546 /*
14547  * Register : GICD_IPRIORITYR115
14548  *
14549  * Interrupt Priority Registers
14550  *
14551  * Register Layout
14552  *
14553  * Bits | Access | Reset | Description
14554  * :-------|:-------|:------|:------------
14555  * [31:0] | RW | 0x0 | Empty
14556  *
14557  */
14558 /*
14559  * Field : Empty - fld
14560  *
14561  * Placeholder
14562  *
14563  * Field Access Macros:
14564  *
14565  */
14566 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR115_FLD register field. */
14567 #define ALT_GIC_DIST_GICD_IPRIORITYR115_FLD_LSB 0
14568 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR115_FLD register field. */
14569 #define ALT_GIC_DIST_GICD_IPRIORITYR115_FLD_MSB 31
14570 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR115_FLD register field. */
14571 #define ALT_GIC_DIST_GICD_IPRIORITYR115_FLD_WIDTH 32
14572 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR115_FLD register field value. */
14573 #define ALT_GIC_DIST_GICD_IPRIORITYR115_FLD_SET_MSK 0xffffffff
14574 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR115_FLD register field value. */
14575 #define ALT_GIC_DIST_GICD_IPRIORITYR115_FLD_CLR_MSK 0x00000000
14576 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR115_FLD register field. */
14577 #define ALT_GIC_DIST_GICD_IPRIORITYR115_FLD_RESET 0x0
14578 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR115_FLD field value from a register. */
14579 #define ALT_GIC_DIST_GICD_IPRIORITYR115_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14580 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR115_FLD register field value suitable for setting the register. */
14581 #define ALT_GIC_DIST_GICD_IPRIORITYR115_FLD_SET(value) (((value) << 0) & 0xffffffff)
14582 
14583 #ifndef __ASSEMBLY__
14584 /*
14585  * WARNING: The C register and register group struct declarations are provided for
14586  * convenience and illustrative purposes. They should, however, be used with
14587  * caution as the C language standard provides no guarantees about the alignment or
14588  * atomicity of device memory accesses. The recommended practice for coding device
14589  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14590  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14591  * alt_write_dword() functions for 64 bit registers.
14592  *
14593  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR115.
14594  */
14595 struct ALT_GIC_DIST_GICD_IPRIORITYR115_s
14596 {
14597  volatile uint32_t fld : 32; /* Empty */
14598 };
14599 
14600 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR115. */
14601 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR115_s ALT_GIC_DIST_GICD_IPRIORITYR115_t;
14602 #endif /* __ASSEMBLY__ */
14603 
14604 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR115 register. */
14605 #define ALT_GIC_DIST_GICD_IPRIORITYR115_RESET 0x00000000
14606 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR115 register from the beginning of the component. */
14607 #define ALT_GIC_DIST_GICD_IPRIORITYR115_OFST 0x5cc
14608 
14609 /*
14610  * Register : GICD_IPRIORITYR116
14611  *
14612  * Interrupt Priority Registers
14613  *
14614  * Register Layout
14615  *
14616  * Bits | Access | Reset | Description
14617  * :-------|:-------|:------|:------------
14618  * [31:0] | RW | 0x0 | Empty
14619  *
14620  */
14621 /*
14622  * Field : Empty - fld
14623  *
14624  * Placeholder
14625  *
14626  * Field Access Macros:
14627  *
14628  */
14629 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR116_FLD register field. */
14630 #define ALT_GIC_DIST_GICD_IPRIORITYR116_FLD_LSB 0
14631 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR116_FLD register field. */
14632 #define ALT_GIC_DIST_GICD_IPRIORITYR116_FLD_MSB 31
14633 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR116_FLD register field. */
14634 #define ALT_GIC_DIST_GICD_IPRIORITYR116_FLD_WIDTH 32
14635 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR116_FLD register field value. */
14636 #define ALT_GIC_DIST_GICD_IPRIORITYR116_FLD_SET_MSK 0xffffffff
14637 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR116_FLD register field value. */
14638 #define ALT_GIC_DIST_GICD_IPRIORITYR116_FLD_CLR_MSK 0x00000000
14639 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR116_FLD register field. */
14640 #define ALT_GIC_DIST_GICD_IPRIORITYR116_FLD_RESET 0x0
14641 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR116_FLD field value from a register. */
14642 #define ALT_GIC_DIST_GICD_IPRIORITYR116_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14643 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR116_FLD register field value suitable for setting the register. */
14644 #define ALT_GIC_DIST_GICD_IPRIORITYR116_FLD_SET(value) (((value) << 0) & 0xffffffff)
14645 
14646 #ifndef __ASSEMBLY__
14647 /*
14648  * WARNING: The C register and register group struct declarations are provided for
14649  * convenience and illustrative purposes. They should, however, be used with
14650  * caution as the C language standard provides no guarantees about the alignment or
14651  * atomicity of device memory accesses. The recommended practice for coding device
14652  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14653  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14654  * alt_write_dword() functions for 64 bit registers.
14655  *
14656  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR116.
14657  */
14658 struct ALT_GIC_DIST_GICD_IPRIORITYR116_s
14659 {
14660  volatile uint32_t fld : 32; /* Empty */
14661 };
14662 
14663 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR116. */
14664 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR116_s ALT_GIC_DIST_GICD_IPRIORITYR116_t;
14665 #endif /* __ASSEMBLY__ */
14666 
14667 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR116 register. */
14668 #define ALT_GIC_DIST_GICD_IPRIORITYR116_RESET 0x00000000
14669 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR116 register from the beginning of the component. */
14670 #define ALT_GIC_DIST_GICD_IPRIORITYR116_OFST 0x5d0
14671 
14672 /*
14673  * Register : GICD_IPRIORITYR117
14674  *
14675  * Interrupt Priority Registers
14676  *
14677  * Register Layout
14678  *
14679  * Bits | Access | Reset | Description
14680  * :-------|:-------|:------|:------------
14681  * [31:0] | RW | 0x0 | Empty
14682  *
14683  */
14684 /*
14685  * Field : Empty - fld
14686  *
14687  * Placeholder
14688  *
14689  * Field Access Macros:
14690  *
14691  */
14692 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR117_FLD register field. */
14693 #define ALT_GIC_DIST_GICD_IPRIORITYR117_FLD_LSB 0
14694 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR117_FLD register field. */
14695 #define ALT_GIC_DIST_GICD_IPRIORITYR117_FLD_MSB 31
14696 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR117_FLD register field. */
14697 #define ALT_GIC_DIST_GICD_IPRIORITYR117_FLD_WIDTH 32
14698 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR117_FLD register field value. */
14699 #define ALT_GIC_DIST_GICD_IPRIORITYR117_FLD_SET_MSK 0xffffffff
14700 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR117_FLD register field value. */
14701 #define ALT_GIC_DIST_GICD_IPRIORITYR117_FLD_CLR_MSK 0x00000000
14702 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR117_FLD register field. */
14703 #define ALT_GIC_DIST_GICD_IPRIORITYR117_FLD_RESET 0x0
14704 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR117_FLD field value from a register. */
14705 #define ALT_GIC_DIST_GICD_IPRIORITYR117_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14706 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR117_FLD register field value suitable for setting the register. */
14707 #define ALT_GIC_DIST_GICD_IPRIORITYR117_FLD_SET(value) (((value) << 0) & 0xffffffff)
14708 
14709 #ifndef __ASSEMBLY__
14710 /*
14711  * WARNING: The C register and register group struct declarations are provided for
14712  * convenience and illustrative purposes. They should, however, be used with
14713  * caution as the C language standard provides no guarantees about the alignment or
14714  * atomicity of device memory accesses. The recommended practice for coding device
14715  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14716  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14717  * alt_write_dword() functions for 64 bit registers.
14718  *
14719  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR117.
14720  */
14721 struct ALT_GIC_DIST_GICD_IPRIORITYR117_s
14722 {
14723  volatile uint32_t fld : 32; /* Empty */
14724 };
14725 
14726 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR117. */
14727 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR117_s ALT_GIC_DIST_GICD_IPRIORITYR117_t;
14728 #endif /* __ASSEMBLY__ */
14729 
14730 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR117 register. */
14731 #define ALT_GIC_DIST_GICD_IPRIORITYR117_RESET 0x00000000
14732 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR117 register from the beginning of the component. */
14733 #define ALT_GIC_DIST_GICD_IPRIORITYR117_OFST 0x5d4
14734 
14735 /*
14736  * Register : GICD_IPRIORITYR118
14737  *
14738  * Interrupt Priority Registers
14739  *
14740  * Register Layout
14741  *
14742  * Bits | Access | Reset | Description
14743  * :-------|:-------|:------|:------------
14744  * [31:0] | RW | 0x0 | Empty
14745  *
14746  */
14747 /*
14748  * Field : Empty - fld
14749  *
14750  * Placeholder
14751  *
14752  * Field Access Macros:
14753  *
14754  */
14755 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR118_FLD register field. */
14756 #define ALT_GIC_DIST_GICD_IPRIORITYR118_FLD_LSB 0
14757 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR118_FLD register field. */
14758 #define ALT_GIC_DIST_GICD_IPRIORITYR118_FLD_MSB 31
14759 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR118_FLD register field. */
14760 #define ALT_GIC_DIST_GICD_IPRIORITYR118_FLD_WIDTH 32
14761 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR118_FLD register field value. */
14762 #define ALT_GIC_DIST_GICD_IPRIORITYR118_FLD_SET_MSK 0xffffffff
14763 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR118_FLD register field value. */
14764 #define ALT_GIC_DIST_GICD_IPRIORITYR118_FLD_CLR_MSK 0x00000000
14765 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR118_FLD register field. */
14766 #define ALT_GIC_DIST_GICD_IPRIORITYR118_FLD_RESET 0x0
14767 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR118_FLD field value from a register. */
14768 #define ALT_GIC_DIST_GICD_IPRIORITYR118_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14769 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR118_FLD register field value suitable for setting the register. */
14770 #define ALT_GIC_DIST_GICD_IPRIORITYR118_FLD_SET(value) (((value) << 0) & 0xffffffff)
14771 
14772 #ifndef __ASSEMBLY__
14773 /*
14774  * WARNING: The C register and register group struct declarations are provided for
14775  * convenience and illustrative purposes. They should, however, be used with
14776  * caution as the C language standard provides no guarantees about the alignment or
14777  * atomicity of device memory accesses. The recommended practice for coding device
14778  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14779  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14780  * alt_write_dword() functions for 64 bit registers.
14781  *
14782  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR118.
14783  */
14784 struct ALT_GIC_DIST_GICD_IPRIORITYR118_s
14785 {
14786  volatile uint32_t fld : 32; /* Empty */
14787 };
14788 
14789 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR118. */
14790 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR118_s ALT_GIC_DIST_GICD_IPRIORITYR118_t;
14791 #endif /* __ASSEMBLY__ */
14792 
14793 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR118 register. */
14794 #define ALT_GIC_DIST_GICD_IPRIORITYR118_RESET 0x00000000
14795 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR118 register from the beginning of the component. */
14796 #define ALT_GIC_DIST_GICD_IPRIORITYR118_OFST 0x5d8
14797 
14798 /*
14799  * Register : GICD_IPRIORITYR119
14800  *
14801  * Interrupt Priority Registers
14802  *
14803  * Register Layout
14804  *
14805  * Bits | Access | Reset | Description
14806  * :-------|:-------|:------|:------------
14807  * [31:0] | RW | 0x0 | Empty
14808  *
14809  */
14810 /*
14811  * Field : Empty - fld
14812  *
14813  * Placeholder
14814  *
14815  * Field Access Macros:
14816  *
14817  */
14818 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR119_FLD register field. */
14819 #define ALT_GIC_DIST_GICD_IPRIORITYR119_FLD_LSB 0
14820 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR119_FLD register field. */
14821 #define ALT_GIC_DIST_GICD_IPRIORITYR119_FLD_MSB 31
14822 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR119_FLD register field. */
14823 #define ALT_GIC_DIST_GICD_IPRIORITYR119_FLD_WIDTH 32
14824 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR119_FLD register field value. */
14825 #define ALT_GIC_DIST_GICD_IPRIORITYR119_FLD_SET_MSK 0xffffffff
14826 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR119_FLD register field value. */
14827 #define ALT_GIC_DIST_GICD_IPRIORITYR119_FLD_CLR_MSK 0x00000000
14828 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR119_FLD register field. */
14829 #define ALT_GIC_DIST_GICD_IPRIORITYR119_FLD_RESET 0x0
14830 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR119_FLD field value from a register. */
14831 #define ALT_GIC_DIST_GICD_IPRIORITYR119_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14832 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR119_FLD register field value suitable for setting the register. */
14833 #define ALT_GIC_DIST_GICD_IPRIORITYR119_FLD_SET(value) (((value) << 0) & 0xffffffff)
14834 
14835 #ifndef __ASSEMBLY__
14836 /*
14837  * WARNING: The C register and register group struct declarations are provided for
14838  * convenience and illustrative purposes. They should, however, be used with
14839  * caution as the C language standard provides no guarantees about the alignment or
14840  * atomicity of device memory accesses. The recommended practice for coding device
14841  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14842  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14843  * alt_write_dword() functions for 64 bit registers.
14844  *
14845  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR119.
14846  */
14847 struct ALT_GIC_DIST_GICD_IPRIORITYR119_s
14848 {
14849  volatile uint32_t fld : 32; /* Empty */
14850 };
14851 
14852 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR119. */
14853 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR119_s ALT_GIC_DIST_GICD_IPRIORITYR119_t;
14854 #endif /* __ASSEMBLY__ */
14855 
14856 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR119 register. */
14857 #define ALT_GIC_DIST_GICD_IPRIORITYR119_RESET 0x00000000
14858 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR119 register from the beginning of the component. */
14859 #define ALT_GIC_DIST_GICD_IPRIORITYR119_OFST 0x5dc
14860 
14861 /*
14862  * Register : GICD_IPRIORITYR120
14863  *
14864  * Interrupt Priority Registers
14865  *
14866  * Register Layout
14867  *
14868  * Bits | Access | Reset | Description
14869  * :-------|:-------|:------|:------------
14870  * [31:0] | RW | 0x0 | Empty
14871  *
14872  */
14873 /*
14874  * Field : Empty - fld
14875  *
14876  * Placeholder
14877  *
14878  * Field Access Macros:
14879  *
14880  */
14881 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR120_FLD register field. */
14882 #define ALT_GIC_DIST_GICD_IPRIORITYR120_FLD_LSB 0
14883 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR120_FLD register field. */
14884 #define ALT_GIC_DIST_GICD_IPRIORITYR120_FLD_MSB 31
14885 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR120_FLD register field. */
14886 #define ALT_GIC_DIST_GICD_IPRIORITYR120_FLD_WIDTH 32
14887 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR120_FLD register field value. */
14888 #define ALT_GIC_DIST_GICD_IPRIORITYR120_FLD_SET_MSK 0xffffffff
14889 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR120_FLD register field value. */
14890 #define ALT_GIC_DIST_GICD_IPRIORITYR120_FLD_CLR_MSK 0x00000000
14891 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR120_FLD register field. */
14892 #define ALT_GIC_DIST_GICD_IPRIORITYR120_FLD_RESET 0x0
14893 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR120_FLD field value from a register. */
14894 #define ALT_GIC_DIST_GICD_IPRIORITYR120_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14895 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR120_FLD register field value suitable for setting the register. */
14896 #define ALT_GIC_DIST_GICD_IPRIORITYR120_FLD_SET(value) (((value) << 0) & 0xffffffff)
14897 
14898 #ifndef __ASSEMBLY__
14899 /*
14900  * WARNING: The C register and register group struct declarations are provided for
14901  * convenience and illustrative purposes. They should, however, be used with
14902  * caution as the C language standard provides no guarantees about the alignment or
14903  * atomicity of device memory accesses. The recommended practice for coding device
14904  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14905  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14906  * alt_write_dword() functions for 64 bit registers.
14907  *
14908  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR120.
14909  */
14910 struct ALT_GIC_DIST_GICD_IPRIORITYR120_s
14911 {
14912  volatile uint32_t fld : 32; /* Empty */
14913 };
14914 
14915 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR120. */
14916 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR120_s ALT_GIC_DIST_GICD_IPRIORITYR120_t;
14917 #endif /* __ASSEMBLY__ */
14918 
14919 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR120 register. */
14920 #define ALT_GIC_DIST_GICD_IPRIORITYR120_RESET 0x00000000
14921 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR120 register from the beginning of the component. */
14922 #define ALT_GIC_DIST_GICD_IPRIORITYR120_OFST 0x5e0
14923 
14924 /*
14925  * Register : GICD_IPRIORITYR121
14926  *
14927  * Interrupt Priority Registers
14928  *
14929  * Register Layout
14930  *
14931  * Bits | Access | Reset | Description
14932  * :-------|:-------|:------|:------------
14933  * [31:0] | RW | 0x0 | Empty
14934  *
14935  */
14936 /*
14937  * Field : Empty - fld
14938  *
14939  * Placeholder
14940  *
14941  * Field Access Macros:
14942  *
14943  */
14944 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR121_FLD register field. */
14945 #define ALT_GIC_DIST_GICD_IPRIORITYR121_FLD_LSB 0
14946 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR121_FLD register field. */
14947 #define ALT_GIC_DIST_GICD_IPRIORITYR121_FLD_MSB 31
14948 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR121_FLD register field. */
14949 #define ALT_GIC_DIST_GICD_IPRIORITYR121_FLD_WIDTH 32
14950 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR121_FLD register field value. */
14951 #define ALT_GIC_DIST_GICD_IPRIORITYR121_FLD_SET_MSK 0xffffffff
14952 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR121_FLD register field value. */
14953 #define ALT_GIC_DIST_GICD_IPRIORITYR121_FLD_CLR_MSK 0x00000000
14954 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR121_FLD register field. */
14955 #define ALT_GIC_DIST_GICD_IPRIORITYR121_FLD_RESET 0x0
14956 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR121_FLD field value from a register. */
14957 #define ALT_GIC_DIST_GICD_IPRIORITYR121_FLD_GET(value) (((value) & 0xffffffff) >> 0)
14958 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR121_FLD register field value suitable for setting the register. */
14959 #define ALT_GIC_DIST_GICD_IPRIORITYR121_FLD_SET(value) (((value) << 0) & 0xffffffff)
14960 
14961 #ifndef __ASSEMBLY__
14962 /*
14963  * WARNING: The C register and register group struct declarations are provided for
14964  * convenience and illustrative purposes. They should, however, be used with
14965  * caution as the C language standard provides no guarantees about the alignment or
14966  * atomicity of device memory accesses. The recommended practice for coding device
14967  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14968  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14969  * alt_write_dword() functions for 64 bit registers.
14970  *
14971  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR121.
14972  */
14973 struct ALT_GIC_DIST_GICD_IPRIORITYR121_s
14974 {
14975  volatile uint32_t fld : 32; /* Empty */
14976 };
14977 
14978 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR121. */
14979 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR121_s ALT_GIC_DIST_GICD_IPRIORITYR121_t;
14980 #endif /* __ASSEMBLY__ */
14981 
14982 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR121 register. */
14983 #define ALT_GIC_DIST_GICD_IPRIORITYR121_RESET 0x00000000
14984 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR121 register from the beginning of the component. */
14985 #define ALT_GIC_DIST_GICD_IPRIORITYR121_OFST 0x5e4
14986 
14987 /*
14988  * Register : GICD_IPRIORITYR122
14989  *
14990  * Interrupt Priority Registers
14991  *
14992  * Register Layout
14993  *
14994  * Bits | Access | Reset | Description
14995  * :-------|:-------|:------|:------------
14996  * [31:0] | RW | 0x0 | Empty
14997  *
14998  */
14999 /*
15000  * Field : Empty - fld
15001  *
15002  * Placeholder
15003  *
15004  * Field Access Macros:
15005  *
15006  */
15007 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR122_FLD register field. */
15008 #define ALT_GIC_DIST_GICD_IPRIORITYR122_FLD_LSB 0
15009 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR122_FLD register field. */
15010 #define ALT_GIC_DIST_GICD_IPRIORITYR122_FLD_MSB 31
15011 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR122_FLD register field. */
15012 #define ALT_GIC_DIST_GICD_IPRIORITYR122_FLD_WIDTH 32
15013 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR122_FLD register field value. */
15014 #define ALT_GIC_DIST_GICD_IPRIORITYR122_FLD_SET_MSK 0xffffffff
15015 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR122_FLD register field value. */
15016 #define ALT_GIC_DIST_GICD_IPRIORITYR122_FLD_CLR_MSK 0x00000000
15017 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR122_FLD register field. */
15018 #define ALT_GIC_DIST_GICD_IPRIORITYR122_FLD_RESET 0x0
15019 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR122_FLD field value from a register. */
15020 #define ALT_GIC_DIST_GICD_IPRIORITYR122_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15021 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR122_FLD register field value suitable for setting the register. */
15022 #define ALT_GIC_DIST_GICD_IPRIORITYR122_FLD_SET(value) (((value) << 0) & 0xffffffff)
15023 
15024 #ifndef __ASSEMBLY__
15025 /*
15026  * WARNING: The C register and register group struct declarations are provided for
15027  * convenience and illustrative purposes. They should, however, be used with
15028  * caution as the C language standard provides no guarantees about the alignment or
15029  * atomicity of device memory accesses. The recommended practice for coding device
15030  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15031  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15032  * alt_write_dword() functions for 64 bit registers.
15033  *
15034  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR122.
15035  */
15036 struct ALT_GIC_DIST_GICD_IPRIORITYR122_s
15037 {
15038  volatile uint32_t fld : 32; /* Empty */
15039 };
15040 
15041 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR122. */
15042 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR122_s ALT_GIC_DIST_GICD_IPRIORITYR122_t;
15043 #endif /* __ASSEMBLY__ */
15044 
15045 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR122 register. */
15046 #define ALT_GIC_DIST_GICD_IPRIORITYR122_RESET 0x00000000
15047 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR122 register from the beginning of the component. */
15048 #define ALT_GIC_DIST_GICD_IPRIORITYR122_OFST 0x5e8
15049 
15050 /*
15051  * Register : GICD_IPRIORITYR123
15052  *
15053  * Interrupt Priority Registers
15054  *
15055  * Register Layout
15056  *
15057  * Bits | Access | Reset | Description
15058  * :-------|:-------|:------|:------------
15059  * [31:0] | RW | 0x0 | Empty
15060  *
15061  */
15062 /*
15063  * Field : Empty - fld
15064  *
15065  * Placeholder
15066  *
15067  * Field Access Macros:
15068  *
15069  */
15070 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR123_FLD register field. */
15071 #define ALT_GIC_DIST_GICD_IPRIORITYR123_FLD_LSB 0
15072 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR123_FLD register field. */
15073 #define ALT_GIC_DIST_GICD_IPRIORITYR123_FLD_MSB 31
15074 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR123_FLD register field. */
15075 #define ALT_GIC_DIST_GICD_IPRIORITYR123_FLD_WIDTH 32
15076 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR123_FLD register field value. */
15077 #define ALT_GIC_DIST_GICD_IPRIORITYR123_FLD_SET_MSK 0xffffffff
15078 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR123_FLD register field value. */
15079 #define ALT_GIC_DIST_GICD_IPRIORITYR123_FLD_CLR_MSK 0x00000000
15080 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR123_FLD register field. */
15081 #define ALT_GIC_DIST_GICD_IPRIORITYR123_FLD_RESET 0x0
15082 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR123_FLD field value from a register. */
15083 #define ALT_GIC_DIST_GICD_IPRIORITYR123_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15084 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR123_FLD register field value suitable for setting the register. */
15085 #define ALT_GIC_DIST_GICD_IPRIORITYR123_FLD_SET(value) (((value) << 0) & 0xffffffff)
15086 
15087 #ifndef __ASSEMBLY__
15088 /*
15089  * WARNING: The C register and register group struct declarations are provided for
15090  * convenience and illustrative purposes. They should, however, be used with
15091  * caution as the C language standard provides no guarantees about the alignment or
15092  * atomicity of device memory accesses. The recommended practice for coding device
15093  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15094  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15095  * alt_write_dword() functions for 64 bit registers.
15096  *
15097  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR123.
15098  */
15099 struct ALT_GIC_DIST_GICD_IPRIORITYR123_s
15100 {
15101  volatile uint32_t fld : 32; /* Empty */
15102 };
15103 
15104 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR123. */
15105 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR123_s ALT_GIC_DIST_GICD_IPRIORITYR123_t;
15106 #endif /* __ASSEMBLY__ */
15107 
15108 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR123 register. */
15109 #define ALT_GIC_DIST_GICD_IPRIORITYR123_RESET 0x00000000
15110 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR123 register from the beginning of the component. */
15111 #define ALT_GIC_DIST_GICD_IPRIORITYR123_OFST 0x5ec
15112 
15113 /*
15114  * Register : GICD_IPRIORITYR124
15115  *
15116  * Interrupt Priority Registers
15117  *
15118  * Register Layout
15119  *
15120  * Bits | Access | Reset | Description
15121  * :-------|:-------|:------|:------------
15122  * [31:0] | RW | 0x0 | Empty
15123  *
15124  */
15125 /*
15126  * Field : Empty - fld
15127  *
15128  * Placeholder
15129  *
15130  * Field Access Macros:
15131  *
15132  */
15133 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR124_FLD register field. */
15134 #define ALT_GIC_DIST_GICD_IPRIORITYR124_FLD_LSB 0
15135 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR124_FLD register field. */
15136 #define ALT_GIC_DIST_GICD_IPRIORITYR124_FLD_MSB 31
15137 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR124_FLD register field. */
15138 #define ALT_GIC_DIST_GICD_IPRIORITYR124_FLD_WIDTH 32
15139 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR124_FLD register field value. */
15140 #define ALT_GIC_DIST_GICD_IPRIORITYR124_FLD_SET_MSK 0xffffffff
15141 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR124_FLD register field value. */
15142 #define ALT_GIC_DIST_GICD_IPRIORITYR124_FLD_CLR_MSK 0x00000000
15143 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR124_FLD register field. */
15144 #define ALT_GIC_DIST_GICD_IPRIORITYR124_FLD_RESET 0x0
15145 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR124_FLD field value from a register. */
15146 #define ALT_GIC_DIST_GICD_IPRIORITYR124_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15147 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR124_FLD register field value suitable for setting the register. */
15148 #define ALT_GIC_DIST_GICD_IPRIORITYR124_FLD_SET(value) (((value) << 0) & 0xffffffff)
15149 
15150 #ifndef __ASSEMBLY__
15151 /*
15152  * WARNING: The C register and register group struct declarations are provided for
15153  * convenience and illustrative purposes. They should, however, be used with
15154  * caution as the C language standard provides no guarantees about the alignment or
15155  * atomicity of device memory accesses. The recommended practice for coding device
15156  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15157  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15158  * alt_write_dword() functions for 64 bit registers.
15159  *
15160  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR124.
15161  */
15162 struct ALT_GIC_DIST_GICD_IPRIORITYR124_s
15163 {
15164  volatile uint32_t fld : 32; /* Empty */
15165 };
15166 
15167 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR124. */
15168 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR124_s ALT_GIC_DIST_GICD_IPRIORITYR124_t;
15169 #endif /* __ASSEMBLY__ */
15170 
15171 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR124 register. */
15172 #define ALT_GIC_DIST_GICD_IPRIORITYR124_RESET 0x00000000
15173 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR124 register from the beginning of the component. */
15174 #define ALT_GIC_DIST_GICD_IPRIORITYR124_OFST 0x5f0
15175 
15176 /*
15177  * Register : GICD_IPRIORITYR125
15178  *
15179  * Interrupt Priority Registers
15180  *
15181  * Register Layout
15182  *
15183  * Bits | Access | Reset | Description
15184  * :-------|:-------|:------|:------------
15185  * [31:0] | RW | 0x0 | Empty
15186  *
15187  */
15188 /*
15189  * Field : Empty - fld
15190  *
15191  * Placeholder
15192  *
15193  * Field Access Macros:
15194  *
15195  */
15196 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR125_FLD register field. */
15197 #define ALT_GIC_DIST_GICD_IPRIORITYR125_FLD_LSB 0
15198 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR125_FLD register field. */
15199 #define ALT_GIC_DIST_GICD_IPRIORITYR125_FLD_MSB 31
15200 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR125_FLD register field. */
15201 #define ALT_GIC_DIST_GICD_IPRIORITYR125_FLD_WIDTH 32
15202 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR125_FLD register field value. */
15203 #define ALT_GIC_DIST_GICD_IPRIORITYR125_FLD_SET_MSK 0xffffffff
15204 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR125_FLD register field value. */
15205 #define ALT_GIC_DIST_GICD_IPRIORITYR125_FLD_CLR_MSK 0x00000000
15206 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR125_FLD register field. */
15207 #define ALT_GIC_DIST_GICD_IPRIORITYR125_FLD_RESET 0x0
15208 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR125_FLD field value from a register. */
15209 #define ALT_GIC_DIST_GICD_IPRIORITYR125_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15210 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR125_FLD register field value suitable for setting the register. */
15211 #define ALT_GIC_DIST_GICD_IPRIORITYR125_FLD_SET(value) (((value) << 0) & 0xffffffff)
15212 
15213 #ifndef __ASSEMBLY__
15214 /*
15215  * WARNING: The C register and register group struct declarations are provided for
15216  * convenience and illustrative purposes. They should, however, be used with
15217  * caution as the C language standard provides no guarantees about the alignment or
15218  * atomicity of device memory accesses. The recommended practice for coding device
15219  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15220  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15221  * alt_write_dword() functions for 64 bit registers.
15222  *
15223  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR125.
15224  */
15225 struct ALT_GIC_DIST_GICD_IPRIORITYR125_s
15226 {
15227  volatile uint32_t fld : 32; /* Empty */
15228 };
15229 
15230 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR125. */
15231 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR125_s ALT_GIC_DIST_GICD_IPRIORITYR125_t;
15232 #endif /* __ASSEMBLY__ */
15233 
15234 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR125 register. */
15235 #define ALT_GIC_DIST_GICD_IPRIORITYR125_RESET 0x00000000
15236 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR125 register from the beginning of the component. */
15237 #define ALT_GIC_DIST_GICD_IPRIORITYR125_OFST 0x5f4
15238 
15239 /*
15240  * Register : GICD_IPRIORITYR126
15241  *
15242  * Interrupt Priority Registers
15243  *
15244  * Register Layout
15245  *
15246  * Bits | Access | Reset | Description
15247  * :-------|:-------|:------|:------------
15248  * [31:0] | RW | 0x0 | Empty
15249  *
15250  */
15251 /*
15252  * Field : Empty - fld
15253  *
15254  * Placeholder
15255  *
15256  * Field Access Macros:
15257  *
15258  */
15259 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR126_FLD register field. */
15260 #define ALT_GIC_DIST_GICD_IPRIORITYR126_FLD_LSB 0
15261 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR126_FLD register field. */
15262 #define ALT_GIC_DIST_GICD_IPRIORITYR126_FLD_MSB 31
15263 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR126_FLD register field. */
15264 #define ALT_GIC_DIST_GICD_IPRIORITYR126_FLD_WIDTH 32
15265 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR126_FLD register field value. */
15266 #define ALT_GIC_DIST_GICD_IPRIORITYR126_FLD_SET_MSK 0xffffffff
15267 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR126_FLD register field value. */
15268 #define ALT_GIC_DIST_GICD_IPRIORITYR126_FLD_CLR_MSK 0x00000000
15269 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR126_FLD register field. */
15270 #define ALT_GIC_DIST_GICD_IPRIORITYR126_FLD_RESET 0x0
15271 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR126_FLD field value from a register. */
15272 #define ALT_GIC_DIST_GICD_IPRIORITYR126_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15273 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR126_FLD register field value suitable for setting the register. */
15274 #define ALT_GIC_DIST_GICD_IPRIORITYR126_FLD_SET(value) (((value) << 0) & 0xffffffff)
15275 
15276 #ifndef __ASSEMBLY__
15277 /*
15278  * WARNING: The C register and register group struct declarations are provided for
15279  * convenience and illustrative purposes. They should, however, be used with
15280  * caution as the C language standard provides no guarantees about the alignment or
15281  * atomicity of device memory accesses. The recommended practice for coding device
15282  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15283  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15284  * alt_write_dword() functions for 64 bit registers.
15285  *
15286  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR126.
15287  */
15288 struct ALT_GIC_DIST_GICD_IPRIORITYR126_s
15289 {
15290  volatile uint32_t fld : 32; /* Empty */
15291 };
15292 
15293 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR126. */
15294 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR126_s ALT_GIC_DIST_GICD_IPRIORITYR126_t;
15295 #endif /* __ASSEMBLY__ */
15296 
15297 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR126 register. */
15298 #define ALT_GIC_DIST_GICD_IPRIORITYR126_RESET 0x00000000
15299 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR126 register from the beginning of the component. */
15300 #define ALT_GIC_DIST_GICD_IPRIORITYR126_OFST 0x5f8
15301 
15302 /*
15303  * Register : GICD_IPRIORITYR127
15304  *
15305  * Interrupt Priority Registers
15306  *
15307  * Register Layout
15308  *
15309  * Bits | Access | Reset | Description
15310  * :-------|:-------|:------|:------------
15311  * [31:0] | RW | 0x0 | Empty
15312  *
15313  */
15314 /*
15315  * Field : Empty - fld
15316  *
15317  * Placeholder
15318  *
15319  * Field Access Macros:
15320  *
15321  */
15322 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR127_FLD register field. */
15323 #define ALT_GIC_DIST_GICD_IPRIORITYR127_FLD_LSB 0
15324 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_IPRIORITYR127_FLD register field. */
15325 #define ALT_GIC_DIST_GICD_IPRIORITYR127_FLD_MSB 31
15326 /* The width in bits of the ALT_GIC_DIST_GICD_IPRIORITYR127_FLD register field. */
15327 #define ALT_GIC_DIST_GICD_IPRIORITYR127_FLD_WIDTH 32
15328 /* The mask used to set the ALT_GIC_DIST_GICD_IPRIORITYR127_FLD register field value. */
15329 #define ALT_GIC_DIST_GICD_IPRIORITYR127_FLD_SET_MSK 0xffffffff
15330 /* The mask used to clear the ALT_GIC_DIST_GICD_IPRIORITYR127_FLD register field value. */
15331 #define ALT_GIC_DIST_GICD_IPRIORITYR127_FLD_CLR_MSK 0x00000000
15332 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR127_FLD register field. */
15333 #define ALT_GIC_DIST_GICD_IPRIORITYR127_FLD_RESET 0x0
15334 /* Extracts the ALT_GIC_DIST_GICD_IPRIORITYR127_FLD field value from a register. */
15335 #define ALT_GIC_DIST_GICD_IPRIORITYR127_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15336 /* Produces a ALT_GIC_DIST_GICD_IPRIORITYR127_FLD register field value suitable for setting the register. */
15337 #define ALT_GIC_DIST_GICD_IPRIORITYR127_FLD_SET(value) (((value) << 0) & 0xffffffff)
15338 
15339 #ifndef __ASSEMBLY__
15340 /*
15341  * WARNING: The C register and register group struct declarations are provided for
15342  * convenience and illustrative purposes. They should, however, be used with
15343  * caution as the C language standard provides no guarantees about the alignment or
15344  * atomicity of device memory accesses. The recommended practice for coding device
15345  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15346  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15347  * alt_write_dword() functions for 64 bit registers.
15348  *
15349  * The struct declaration for register ALT_GIC_DIST_GICD_IPRIORITYR127.
15350  */
15351 struct ALT_GIC_DIST_GICD_IPRIORITYR127_s
15352 {
15353  volatile uint32_t fld : 32; /* Empty */
15354 };
15355 
15356 /* The typedef declaration for register ALT_GIC_DIST_GICD_IPRIORITYR127. */
15357 typedef struct ALT_GIC_DIST_GICD_IPRIORITYR127_s ALT_GIC_DIST_GICD_IPRIORITYR127_t;
15358 #endif /* __ASSEMBLY__ */
15359 
15360 /* The reset value of the ALT_GIC_DIST_GICD_IPRIORITYR127 register. */
15361 #define ALT_GIC_DIST_GICD_IPRIORITYR127_RESET 0x00000000
15362 /* The byte offset of the ALT_GIC_DIST_GICD_IPRIORITYR127 register from the beginning of the component. */
15363 #define ALT_GIC_DIST_GICD_IPRIORITYR127_OFST 0x5fc
15364 
15365 /*
15366  * Register : GICD_ITARGETSR0
15367  *
15368  * Interrupt Processor Targets Registers
15369  *
15370  * Register Layout
15371  *
15372  * Bits | Access | Reset | Description
15373  * :-------|:-------|:--------|:------------
15374  * [31:0] | RW | Unknown | Empty
15375  *
15376  */
15377 /*
15378  * Field : Empty - fld
15379  *
15380  * Placeholder
15381  *
15382  * Field Access Macros:
15383  *
15384  */
15385 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR0_FLD register field. */
15386 #define ALT_GIC_DIST_GICD_ITARGETSR0_FLD_LSB 0
15387 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR0_FLD register field. */
15388 #define ALT_GIC_DIST_GICD_ITARGETSR0_FLD_MSB 31
15389 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR0_FLD register field. */
15390 #define ALT_GIC_DIST_GICD_ITARGETSR0_FLD_WIDTH 32
15391 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR0_FLD register field value. */
15392 #define ALT_GIC_DIST_GICD_ITARGETSR0_FLD_SET_MSK 0xffffffff
15393 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR0_FLD register field value. */
15394 #define ALT_GIC_DIST_GICD_ITARGETSR0_FLD_CLR_MSK 0x00000000
15395 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR0_FLD register field is UNKNOWN. */
15396 #define ALT_GIC_DIST_GICD_ITARGETSR0_FLD_RESET 0x0
15397 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR0_FLD field value from a register. */
15398 #define ALT_GIC_DIST_GICD_ITARGETSR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15399 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR0_FLD register field value suitable for setting the register. */
15400 #define ALT_GIC_DIST_GICD_ITARGETSR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
15401 
15402 #ifndef __ASSEMBLY__
15403 /*
15404  * WARNING: The C register and register group struct declarations are provided for
15405  * convenience and illustrative purposes. They should, however, be used with
15406  * caution as the C language standard provides no guarantees about the alignment or
15407  * atomicity of device memory accesses. The recommended practice for coding device
15408  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15409  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15410  * alt_write_dword() functions for 64 bit registers.
15411  *
15412  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR0.
15413  */
15414 struct ALT_GIC_DIST_GICD_ITARGETSR0_s
15415 {
15416  volatile uint32_t fld : 32; /* Empty */
15417 };
15418 
15419 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR0. */
15420 typedef struct ALT_GIC_DIST_GICD_ITARGETSR0_s ALT_GIC_DIST_GICD_ITARGETSR0_t;
15421 #endif /* __ASSEMBLY__ */
15422 
15423 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR0 register. */
15424 #define ALT_GIC_DIST_GICD_ITARGETSR0_RESET 0x00000000
15425 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR0 register from the beginning of the component. */
15426 #define ALT_GIC_DIST_GICD_ITARGETSR0_OFST 0x800
15427 
15428 /*
15429  * Register : GICD_ITARGETSR1
15430  *
15431  * Interrupt Processor Targets Registers
15432  *
15433  * Register Layout
15434  *
15435  * Bits | Access | Reset | Description
15436  * :-------|:-------|:--------|:------------
15437  * [31:0] | RW | Unknown | Empty
15438  *
15439  */
15440 /*
15441  * Field : Empty - fld
15442  *
15443  * Placeholder
15444  *
15445  * Field Access Macros:
15446  *
15447  */
15448 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR1_FLD register field. */
15449 #define ALT_GIC_DIST_GICD_ITARGETSR1_FLD_LSB 0
15450 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR1_FLD register field. */
15451 #define ALT_GIC_DIST_GICD_ITARGETSR1_FLD_MSB 31
15452 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR1_FLD register field. */
15453 #define ALT_GIC_DIST_GICD_ITARGETSR1_FLD_WIDTH 32
15454 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR1_FLD register field value. */
15455 #define ALT_GIC_DIST_GICD_ITARGETSR1_FLD_SET_MSK 0xffffffff
15456 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR1_FLD register field value. */
15457 #define ALT_GIC_DIST_GICD_ITARGETSR1_FLD_CLR_MSK 0x00000000
15458 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR1_FLD register field is UNKNOWN. */
15459 #define ALT_GIC_DIST_GICD_ITARGETSR1_FLD_RESET 0x0
15460 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR1_FLD field value from a register. */
15461 #define ALT_GIC_DIST_GICD_ITARGETSR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15462 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR1_FLD register field value suitable for setting the register. */
15463 #define ALT_GIC_DIST_GICD_ITARGETSR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
15464 
15465 #ifndef __ASSEMBLY__
15466 /*
15467  * WARNING: The C register and register group struct declarations are provided for
15468  * convenience and illustrative purposes. They should, however, be used with
15469  * caution as the C language standard provides no guarantees about the alignment or
15470  * atomicity of device memory accesses. The recommended practice for coding device
15471  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15472  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15473  * alt_write_dword() functions for 64 bit registers.
15474  *
15475  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR1.
15476  */
15477 struct ALT_GIC_DIST_GICD_ITARGETSR1_s
15478 {
15479  volatile uint32_t fld : 32; /* Empty */
15480 };
15481 
15482 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR1. */
15483 typedef struct ALT_GIC_DIST_GICD_ITARGETSR1_s ALT_GIC_DIST_GICD_ITARGETSR1_t;
15484 #endif /* __ASSEMBLY__ */
15485 
15486 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR1 register. */
15487 #define ALT_GIC_DIST_GICD_ITARGETSR1_RESET 0x00000000
15488 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR1 register from the beginning of the component. */
15489 #define ALT_GIC_DIST_GICD_ITARGETSR1_OFST 0x804
15490 
15491 /*
15492  * Register : GICD_ITARGETSR2
15493  *
15494  * Interrupt Processor Targets Registers
15495  *
15496  * Register Layout
15497  *
15498  * Bits | Access | Reset | Description
15499  * :-------|:-------|:--------|:------------
15500  * [31:0] | RW | Unknown | Empty
15501  *
15502  */
15503 /*
15504  * Field : Empty - fld
15505  *
15506  * Placeholder
15507  *
15508  * Field Access Macros:
15509  *
15510  */
15511 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR2_FLD register field. */
15512 #define ALT_GIC_DIST_GICD_ITARGETSR2_FLD_LSB 0
15513 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR2_FLD register field. */
15514 #define ALT_GIC_DIST_GICD_ITARGETSR2_FLD_MSB 31
15515 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR2_FLD register field. */
15516 #define ALT_GIC_DIST_GICD_ITARGETSR2_FLD_WIDTH 32
15517 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR2_FLD register field value. */
15518 #define ALT_GIC_DIST_GICD_ITARGETSR2_FLD_SET_MSK 0xffffffff
15519 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR2_FLD register field value. */
15520 #define ALT_GIC_DIST_GICD_ITARGETSR2_FLD_CLR_MSK 0x00000000
15521 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR2_FLD register field is UNKNOWN. */
15522 #define ALT_GIC_DIST_GICD_ITARGETSR2_FLD_RESET 0x0
15523 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR2_FLD field value from a register. */
15524 #define ALT_GIC_DIST_GICD_ITARGETSR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15525 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR2_FLD register field value suitable for setting the register. */
15526 #define ALT_GIC_DIST_GICD_ITARGETSR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
15527 
15528 #ifndef __ASSEMBLY__
15529 /*
15530  * WARNING: The C register and register group struct declarations are provided for
15531  * convenience and illustrative purposes. They should, however, be used with
15532  * caution as the C language standard provides no guarantees about the alignment or
15533  * atomicity of device memory accesses. The recommended practice for coding device
15534  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15535  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15536  * alt_write_dword() functions for 64 bit registers.
15537  *
15538  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR2.
15539  */
15540 struct ALT_GIC_DIST_GICD_ITARGETSR2_s
15541 {
15542  volatile uint32_t fld : 32; /* Empty */
15543 };
15544 
15545 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR2. */
15546 typedef struct ALT_GIC_DIST_GICD_ITARGETSR2_s ALT_GIC_DIST_GICD_ITARGETSR2_t;
15547 #endif /* __ASSEMBLY__ */
15548 
15549 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR2 register. */
15550 #define ALT_GIC_DIST_GICD_ITARGETSR2_RESET 0x00000000
15551 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR2 register from the beginning of the component. */
15552 #define ALT_GIC_DIST_GICD_ITARGETSR2_OFST 0x808
15553 
15554 /*
15555  * Register : GICD_ITARGETSR3
15556  *
15557  * Interrupt Processor Targets Registers
15558  *
15559  * Register Layout
15560  *
15561  * Bits | Access | Reset | Description
15562  * :-------|:-------|:--------|:------------
15563  * [31:0] | RW | Unknown | Empty
15564  *
15565  */
15566 /*
15567  * Field : Empty - fld
15568  *
15569  * Placeholder
15570  *
15571  * Field Access Macros:
15572  *
15573  */
15574 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR3_FLD register field. */
15575 #define ALT_GIC_DIST_GICD_ITARGETSR3_FLD_LSB 0
15576 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR3_FLD register field. */
15577 #define ALT_GIC_DIST_GICD_ITARGETSR3_FLD_MSB 31
15578 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR3_FLD register field. */
15579 #define ALT_GIC_DIST_GICD_ITARGETSR3_FLD_WIDTH 32
15580 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR3_FLD register field value. */
15581 #define ALT_GIC_DIST_GICD_ITARGETSR3_FLD_SET_MSK 0xffffffff
15582 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR3_FLD register field value. */
15583 #define ALT_GIC_DIST_GICD_ITARGETSR3_FLD_CLR_MSK 0x00000000
15584 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR3_FLD register field is UNKNOWN. */
15585 #define ALT_GIC_DIST_GICD_ITARGETSR3_FLD_RESET 0x0
15586 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR3_FLD field value from a register. */
15587 #define ALT_GIC_DIST_GICD_ITARGETSR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15588 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR3_FLD register field value suitable for setting the register. */
15589 #define ALT_GIC_DIST_GICD_ITARGETSR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
15590 
15591 #ifndef __ASSEMBLY__
15592 /*
15593  * WARNING: The C register and register group struct declarations are provided for
15594  * convenience and illustrative purposes. They should, however, be used with
15595  * caution as the C language standard provides no guarantees about the alignment or
15596  * atomicity of device memory accesses. The recommended practice for coding device
15597  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15598  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15599  * alt_write_dword() functions for 64 bit registers.
15600  *
15601  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR3.
15602  */
15603 struct ALT_GIC_DIST_GICD_ITARGETSR3_s
15604 {
15605  volatile uint32_t fld : 32; /* Empty */
15606 };
15607 
15608 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR3. */
15609 typedef struct ALT_GIC_DIST_GICD_ITARGETSR3_s ALT_GIC_DIST_GICD_ITARGETSR3_t;
15610 #endif /* __ASSEMBLY__ */
15611 
15612 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR3 register. */
15613 #define ALT_GIC_DIST_GICD_ITARGETSR3_RESET 0x00000000
15614 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR3 register from the beginning of the component. */
15615 #define ALT_GIC_DIST_GICD_ITARGETSR3_OFST 0x80c
15616 
15617 /*
15618  * Register : GICD_ITARGETSR4
15619  *
15620  * Interrupt Processor Targets Registers
15621  *
15622  * Register Layout
15623  *
15624  * Bits | Access | Reset | Description
15625  * :-------|:-------|:--------|:------------
15626  * [31:0] | RW | Unknown | Empty
15627  *
15628  */
15629 /*
15630  * Field : Empty - fld
15631  *
15632  * Placeholder
15633  *
15634  * Field Access Macros:
15635  *
15636  */
15637 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR4_FLD register field. */
15638 #define ALT_GIC_DIST_GICD_ITARGETSR4_FLD_LSB 0
15639 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR4_FLD register field. */
15640 #define ALT_GIC_DIST_GICD_ITARGETSR4_FLD_MSB 31
15641 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR4_FLD register field. */
15642 #define ALT_GIC_DIST_GICD_ITARGETSR4_FLD_WIDTH 32
15643 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR4_FLD register field value. */
15644 #define ALT_GIC_DIST_GICD_ITARGETSR4_FLD_SET_MSK 0xffffffff
15645 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR4_FLD register field value. */
15646 #define ALT_GIC_DIST_GICD_ITARGETSR4_FLD_CLR_MSK 0x00000000
15647 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR4_FLD register field is UNKNOWN. */
15648 #define ALT_GIC_DIST_GICD_ITARGETSR4_FLD_RESET 0x0
15649 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR4_FLD field value from a register. */
15650 #define ALT_GIC_DIST_GICD_ITARGETSR4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15651 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR4_FLD register field value suitable for setting the register. */
15652 #define ALT_GIC_DIST_GICD_ITARGETSR4_FLD_SET(value) (((value) << 0) & 0xffffffff)
15653 
15654 #ifndef __ASSEMBLY__
15655 /*
15656  * WARNING: The C register and register group struct declarations are provided for
15657  * convenience and illustrative purposes. They should, however, be used with
15658  * caution as the C language standard provides no guarantees about the alignment or
15659  * atomicity of device memory accesses. The recommended practice for coding device
15660  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15661  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15662  * alt_write_dword() functions for 64 bit registers.
15663  *
15664  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR4.
15665  */
15666 struct ALT_GIC_DIST_GICD_ITARGETSR4_s
15667 {
15668  volatile uint32_t fld : 32; /* Empty */
15669 };
15670 
15671 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR4. */
15672 typedef struct ALT_GIC_DIST_GICD_ITARGETSR4_s ALT_GIC_DIST_GICD_ITARGETSR4_t;
15673 #endif /* __ASSEMBLY__ */
15674 
15675 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR4 register. */
15676 #define ALT_GIC_DIST_GICD_ITARGETSR4_RESET 0x00000000
15677 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR4 register from the beginning of the component. */
15678 #define ALT_GIC_DIST_GICD_ITARGETSR4_OFST 0x810
15679 
15680 /*
15681  * Register : GICD_ITARGETSR5
15682  *
15683  * Interrupt Processor Targets Registers
15684  *
15685  * Register Layout
15686  *
15687  * Bits | Access | Reset | Description
15688  * :-------|:-------|:--------|:------------
15689  * [31:0] | RW | Unknown | Empty
15690  *
15691  */
15692 /*
15693  * Field : Empty - fld
15694  *
15695  * Placeholder
15696  *
15697  * Field Access Macros:
15698  *
15699  */
15700 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR5_FLD register field. */
15701 #define ALT_GIC_DIST_GICD_ITARGETSR5_FLD_LSB 0
15702 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR5_FLD register field. */
15703 #define ALT_GIC_DIST_GICD_ITARGETSR5_FLD_MSB 31
15704 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR5_FLD register field. */
15705 #define ALT_GIC_DIST_GICD_ITARGETSR5_FLD_WIDTH 32
15706 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR5_FLD register field value. */
15707 #define ALT_GIC_DIST_GICD_ITARGETSR5_FLD_SET_MSK 0xffffffff
15708 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR5_FLD register field value. */
15709 #define ALT_GIC_DIST_GICD_ITARGETSR5_FLD_CLR_MSK 0x00000000
15710 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR5_FLD register field is UNKNOWN. */
15711 #define ALT_GIC_DIST_GICD_ITARGETSR5_FLD_RESET 0x0
15712 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR5_FLD field value from a register. */
15713 #define ALT_GIC_DIST_GICD_ITARGETSR5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15714 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR5_FLD register field value suitable for setting the register. */
15715 #define ALT_GIC_DIST_GICD_ITARGETSR5_FLD_SET(value) (((value) << 0) & 0xffffffff)
15716 
15717 #ifndef __ASSEMBLY__
15718 /*
15719  * WARNING: The C register and register group struct declarations are provided for
15720  * convenience and illustrative purposes. They should, however, be used with
15721  * caution as the C language standard provides no guarantees about the alignment or
15722  * atomicity of device memory accesses. The recommended practice for coding device
15723  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15724  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15725  * alt_write_dword() functions for 64 bit registers.
15726  *
15727  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR5.
15728  */
15729 struct ALT_GIC_DIST_GICD_ITARGETSR5_s
15730 {
15731  volatile uint32_t fld : 32; /* Empty */
15732 };
15733 
15734 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR5. */
15735 typedef struct ALT_GIC_DIST_GICD_ITARGETSR5_s ALT_GIC_DIST_GICD_ITARGETSR5_t;
15736 #endif /* __ASSEMBLY__ */
15737 
15738 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR5 register. */
15739 #define ALT_GIC_DIST_GICD_ITARGETSR5_RESET 0x00000000
15740 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR5 register from the beginning of the component. */
15741 #define ALT_GIC_DIST_GICD_ITARGETSR5_OFST 0x814
15742 
15743 /*
15744  * Register : GICD_ITARGETSR6
15745  *
15746  * Interrupt Processor Targets Registers
15747  *
15748  * Register Layout
15749  *
15750  * Bits | Access | Reset | Description
15751  * :-------|:-------|:--------|:------------
15752  * [31:0] | RW | Unknown | Empty
15753  *
15754  */
15755 /*
15756  * Field : Empty - fld
15757  *
15758  * Placeholder
15759  *
15760  * Field Access Macros:
15761  *
15762  */
15763 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR6_FLD register field. */
15764 #define ALT_GIC_DIST_GICD_ITARGETSR6_FLD_LSB 0
15765 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR6_FLD register field. */
15766 #define ALT_GIC_DIST_GICD_ITARGETSR6_FLD_MSB 31
15767 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR6_FLD register field. */
15768 #define ALT_GIC_DIST_GICD_ITARGETSR6_FLD_WIDTH 32
15769 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR6_FLD register field value. */
15770 #define ALT_GIC_DIST_GICD_ITARGETSR6_FLD_SET_MSK 0xffffffff
15771 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR6_FLD register field value. */
15772 #define ALT_GIC_DIST_GICD_ITARGETSR6_FLD_CLR_MSK 0x00000000
15773 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR6_FLD register field is UNKNOWN. */
15774 #define ALT_GIC_DIST_GICD_ITARGETSR6_FLD_RESET 0x0
15775 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR6_FLD field value from a register. */
15776 #define ALT_GIC_DIST_GICD_ITARGETSR6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15777 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR6_FLD register field value suitable for setting the register. */
15778 #define ALT_GIC_DIST_GICD_ITARGETSR6_FLD_SET(value) (((value) << 0) & 0xffffffff)
15779 
15780 #ifndef __ASSEMBLY__
15781 /*
15782  * WARNING: The C register and register group struct declarations are provided for
15783  * convenience and illustrative purposes. They should, however, be used with
15784  * caution as the C language standard provides no guarantees about the alignment or
15785  * atomicity of device memory accesses. The recommended practice for coding device
15786  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15787  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15788  * alt_write_dword() functions for 64 bit registers.
15789  *
15790  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR6.
15791  */
15792 struct ALT_GIC_DIST_GICD_ITARGETSR6_s
15793 {
15794  volatile uint32_t fld : 32; /* Empty */
15795 };
15796 
15797 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR6. */
15798 typedef struct ALT_GIC_DIST_GICD_ITARGETSR6_s ALT_GIC_DIST_GICD_ITARGETSR6_t;
15799 #endif /* __ASSEMBLY__ */
15800 
15801 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR6 register. */
15802 #define ALT_GIC_DIST_GICD_ITARGETSR6_RESET 0x00000000
15803 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR6 register from the beginning of the component. */
15804 #define ALT_GIC_DIST_GICD_ITARGETSR6_OFST 0x818
15805 
15806 /*
15807  * Register : GICD_ITARGETSR7
15808  *
15809  * Interrupt Processor Targets Registers
15810  *
15811  * Register Layout
15812  *
15813  * Bits | Access | Reset | Description
15814  * :-------|:-------|:--------|:------------
15815  * [31:0] | RW | Unknown | Empty
15816  *
15817  */
15818 /*
15819  * Field : Empty - fld
15820  *
15821  * Placeholder
15822  *
15823  * Field Access Macros:
15824  *
15825  */
15826 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR7_FLD register field. */
15827 #define ALT_GIC_DIST_GICD_ITARGETSR7_FLD_LSB 0
15828 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR7_FLD register field. */
15829 #define ALT_GIC_DIST_GICD_ITARGETSR7_FLD_MSB 31
15830 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR7_FLD register field. */
15831 #define ALT_GIC_DIST_GICD_ITARGETSR7_FLD_WIDTH 32
15832 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR7_FLD register field value. */
15833 #define ALT_GIC_DIST_GICD_ITARGETSR7_FLD_SET_MSK 0xffffffff
15834 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR7_FLD register field value. */
15835 #define ALT_GIC_DIST_GICD_ITARGETSR7_FLD_CLR_MSK 0x00000000
15836 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR7_FLD register field is UNKNOWN. */
15837 #define ALT_GIC_DIST_GICD_ITARGETSR7_FLD_RESET 0x0
15838 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR7_FLD field value from a register. */
15839 #define ALT_GIC_DIST_GICD_ITARGETSR7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15840 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR7_FLD register field value suitable for setting the register. */
15841 #define ALT_GIC_DIST_GICD_ITARGETSR7_FLD_SET(value) (((value) << 0) & 0xffffffff)
15842 
15843 #ifndef __ASSEMBLY__
15844 /*
15845  * WARNING: The C register and register group struct declarations are provided for
15846  * convenience and illustrative purposes. They should, however, be used with
15847  * caution as the C language standard provides no guarantees about the alignment or
15848  * atomicity of device memory accesses. The recommended practice for coding device
15849  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15850  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15851  * alt_write_dword() functions for 64 bit registers.
15852  *
15853  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR7.
15854  */
15855 struct ALT_GIC_DIST_GICD_ITARGETSR7_s
15856 {
15857  volatile uint32_t fld : 32; /* Empty */
15858 };
15859 
15860 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR7. */
15861 typedef struct ALT_GIC_DIST_GICD_ITARGETSR7_s ALT_GIC_DIST_GICD_ITARGETSR7_t;
15862 #endif /* __ASSEMBLY__ */
15863 
15864 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR7 register. */
15865 #define ALT_GIC_DIST_GICD_ITARGETSR7_RESET 0x00000000
15866 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR7 register from the beginning of the component. */
15867 #define ALT_GIC_DIST_GICD_ITARGETSR7_OFST 0x81c
15868 
15869 /*
15870  * Register : GICD_ITARGETSR8
15871  *
15872  * Interrupt Processor Targets Registers
15873  *
15874  * Register Layout
15875  *
15876  * Bits | Access | Reset | Description
15877  * :-------|:-------|:------|:------------
15878  * [31:0] | RW | 0x0 | Empty
15879  *
15880  */
15881 /*
15882  * Field : Empty - fld
15883  *
15884  * Placeholder
15885  *
15886  * Field Access Macros:
15887  *
15888  */
15889 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR8_FLD register field. */
15890 #define ALT_GIC_DIST_GICD_ITARGETSR8_FLD_LSB 0
15891 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR8_FLD register field. */
15892 #define ALT_GIC_DIST_GICD_ITARGETSR8_FLD_MSB 31
15893 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR8_FLD register field. */
15894 #define ALT_GIC_DIST_GICD_ITARGETSR8_FLD_WIDTH 32
15895 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR8_FLD register field value. */
15896 #define ALT_GIC_DIST_GICD_ITARGETSR8_FLD_SET_MSK 0xffffffff
15897 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR8_FLD register field value. */
15898 #define ALT_GIC_DIST_GICD_ITARGETSR8_FLD_CLR_MSK 0x00000000
15899 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR8_FLD register field. */
15900 #define ALT_GIC_DIST_GICD_ITARGETSR8_FLD_RESET 0x0
15901 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR8_FLD field value from a register. */
15902 #define ALT_GIC_DIST_GICD_ITARGETSR8_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15903 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR8_FLD register field value suitable for setting the register. */
15904 #define ALT_GIC_DIST_GICD_ITARGETSR8_FLD_SET(value) (((value) << 0) & 0xffffffff)
15905 
15906 #ifndef __ASSEMBLY__
15907 /*
15908  * WARNING: The C register and register group struct declarations are provided for
15909  * convenience and illustrative purposes. They should, however, be used with
15910  * caution as the C language standard provides no guarantees about the alignment or
15911  * atomicity of device memory accesses. The recommended practice for coding device
15912  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15913  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15914  * alt_write_dword() functions for 64 bit registers.
15915  *
15916  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR8.
15917  */
15918 struct ALT_GIC_DIST_GICD_ITARGETSR8_s
15919 {
15920  volatile uint32_t fld : 32; /* Empty */
15921 };
15922 
15923 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR8. */
15924 typedef struct ALT_GIC_DIST_GICD_ITARGETSR8_s ALT_GIC_DIST_GICD_ITARGETSR8_t;
15925 #endif /* __ASSEMBLY__ */
15926 
15927 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR8 register. */
15928 #define ALT_GIC_DIST_GICD_ITARGETSR8_RESET 0x00000000
15929 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR8 register from the beginning of the component. */
15930 #define ALT_GIC_DIST_GICD_ITARGETSR8_OFST 0x820
15931 
15932 /*
15933  * Register : GICD_ITARGETSR9
15934  *
15935  * Interrupt Processor Targets Registers
15936  *
15937  * Register Layout
15938  *
15939  * Bits | Access | Reset | Description
15940  * :-------|:-------|:------|:------------
15941  * [31:0] | RW | 0x0 | Empty
15942  *
15943  */
15944 /*
15945  * Field : Empty - fld
15946  *
15947  * Placeholder
15948  *
15949  * Field Access Macros:
15950  *
15951  */
15952 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR9_FLD register field. */
15953 #define ALT_GIC_DIST_GICD_ITARGETSR9_FLD_LSB 0
15954 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR9_FLD register field. */
15955 #define ALT_GIC_DIST_GICD_ITARGETSR9_FLD_MSB 31
15956 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR9_FLD register field. */
15957 #define ALT_GIC_DIST_GICD_ITARGETSR9_FLD_WIDTH 32
15958 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR9_FLD register field value. */
15959 #define ALT_GIC_DIST_GICD_ITARGETSR9_FLD_SET_MSK 0xffffffff
15960 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR9_FLD register field value. */
15961 #define ALT_GIC_DIST_GICD_ITARGETSR9_FLD_CLR_MSK 0x00000000
15962 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR9_FLD register field. */
15963 #define ALT_GIC_DIST_GICD_ITARGETSR9_FLD_RESET 0x0
15964 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR9_FLD field value from a register. */
15965 #define ALT_GIC_DIST_GICD_ITARGETSR9_FLD_GET(value) (((value) & 0xffffffff) >> 0)
15966 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR9_FLD register field value suitable for setting the register. */
15967 #define ALT_GIC_DIST_GICD_ITARGETSR9_FLD_SET(value) (((value) << 0) & 0xffffffff)
15968 
15969 #ifndef __ASSEMBLY__
15970 /*
15971  * WARNING: The C register and register group struct declarations are provided for
15972  * convenience and illustrative purposes. They should, however, be used with
15973  * caution as the C language standard provides no guarantees about the alignment or
15974  * atomicity of device memory accesses. The recommended practice for coding device
15975  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15976  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15977  * alt_write_dword() functions for 64 bit registers.
15978  *
15979  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR9.
15980  */
15981 struct ALT_GIC_DIST_GICD_ITARGETSR9_s
15982 {
15983  volatile uint32_t fld : 32; /* Empty */
15984 };
15985 
15986 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR9. */
15987 typedef struct ALT_GIC_DIST_GICD_ITARGETSR9_s ALT_GIC_DIST_GICD_ITARGETSR9_t;
15988 #endif /* __ASSEMBLY__ */
15989 
15990 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR9 register. */
15991 #define ALT_GIC_DIST_GICD_ITARGETSR9_RESET 0x00000000
15992 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR9 register from the beginning of the component. */
15993 #define ALT_GIC_DIST_GICD_ITARGETSR9_OFST 0x824
15994 
15995 /*
15996  * Register : GICD_ITARGETSR10
15997  *
15998  * Interrupt Processor Targets Registers
15999  *
16000  * Register Layout
16001  *
16002  * Bits | Access | Reset | Description
16003  * :-------|:-------|:------|:------------
16004  * [31:0] | RW | 0x0 | Empty
16005  *
16006  */
16007 /*
16008  * Field : Empty - fld
16009  *
16010  * Placeholder
16011  *
16012  * Field Access Macros:
16013  *
16014  */
16015 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR10_FLD register field. */
16016 #define ALT_GIC_DIST_GICD_ITARGETSR10_FLD_LSB 0
16017 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR10_FLD register field. */
16018 #define ALT_GIC_DIST_GICD_ITARGETSR10_FLD_MSB 31
16019 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR10_FLD register field. */
16020 #define ALT_GIC_DIST_GICD_ITARGETSR10_FLD_WIDTH 32
16021 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR10_FLD register field value. */
16022 #define ALT_GIC_DIST_GICD_ITARGETSR10_FLD_SET_MSK 0xffffffff
16023 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR10_FLD register field value. */
16024 #define ALT_GIC_DIST_GICD_ITARGETSR10_FLD_CLR_MSK 0x00000000
16025 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR10_FLD register field. */
16026 #define ALT_GIC_DIST_GICD_ITARGETSR10_FLD_RESET 0x0
16027 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR10_FLD field value from a register. */
16028 #define ALT_GIC_DIST_GICD_ITARGETSR10_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16029 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR10_FLD register field value suitable for setting the register. */
16030 #define ALT_GIC_DIST_GICD_ITARGETSR10_FLD_SET(value) (((value) << 0) & 0xffffffff)
16031 
16032 #ifndef __ASSEMBLY__
16033 /*
16034  * WARNING: The C register and register group struct declarations are provided for
16035  * convenience and illustrative purposes. They should, however, be used with
16036  * caution as the C language standard provides no guarantees about the alignment or
16037  * atomicity of device memory accesses. The recommended practice for coding device
16038  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16039  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16040  * alt_write_dword() functions for 64 bit registers.
16041  *
16042  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR10.
16043  */
16044 struct ALT_GIC_DIST_GICD_ITARGETSR10_s
16045 {
16046  volatile uint32_t fld : 32; /* Empty */
16047 };
16048 
16049 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR10. */
16050 typedef struct ALT_GIC_DIST_GICD_ITARGETSR10_s ALT_GIC_DIST_GICD_ITARGETSR10_t;
16051 #endif /* __ASSEMBLY__ */
16052 
16053 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR10 register. */
16054 #define ALT_GIC_DIST_GICD_ITARGETSR10_RESET 0x00000000
16055 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR10 register from the beginning of the component. */
16056 #define ALT_GIC_DIST_GICD_ITARGETSR10_OFST 0x828
16057 
16058 /*
16059  * Register : GICD_ITARGETSR11
16060  *
16061  * Interrupt Processor Targets Registers
16062  *
16063  * Register Layout
16064  *
16065  * Bits | Access | Reset | Description
16066  * :-------|:-------|:------|:------------
16067  * [31:0] | RW | 0x0 | Empty
16068  *
16069  */
16070 /*
16071  * Field : Empty - fld
16072  *
16073  * Placeholder
16074  *
16075  * Field Access Macros:
16076  *
16077  */
16078 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR11_FLD register field. */
16079 #define ALT_GIC_DIST_GICD_ITARGETSR11_FLD_LSB 0
16080 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR11_FLD register field. */
16081 #define ALT_GIC_DIST_GICD_ITARGETSR11_FLD_MSB 31
16082 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR11_FLD register field. */
16083 #define ALT_GIC_DIST_GICD_ITARGETSR11_FLD_WIDTH 32
16084 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR11_FLD register field value. */
16085 #define ALT_GIC_DIST_GICD_ITARGETSR11_FLD_SET_MSK 0xffffffff
16086 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR11_FLD register field value. */
16087 #define ALT_GIC_DIST_GICD_ITARGETSR11_FLD_CLR_MSK 0x00000000
16088 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR11_FLD register field. */
16089 #define ALT_GIC_DIST_GICD_ITARGETSR11_FLD_RESET 0x0
16090 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR11_FLD field value from a register. */
16091 #define ALT_GIC_DIST_GICD_ITARGETSR11_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16092 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR11_FLD register field value suitable for setting the register. */
16093 #define ALT_GIC_DIST_GICD_ITARGETSR11_FLD_SET(value) (((value) << 0) & 0xffffffff)
16094 
16095 #ifndef __ASSEMBLY__
16096 /*
16097  * WARNING: The C register and register group struct declarations are provided for
16098  * convenience and illustrative purposes. They should, however, be used with
16099  * caution as the C language standard provides no guarantees about the alignment or
16100  * atomicity of device memory accesses. The recommended practice for coding device
16101  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16102  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16103  * alt_write_dword() functions for 64 bit registers.
16104  *
16105  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR11.
16106  */
16107 struct ALT_GIC_DIST_GICD_ITARGETSR11_s
16108 {
16109  volatile uint32_t fld : 32; /* Empty */
16110 };
16111 
16112 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR11. */
16113 typedef struct ALT_GIC_DIST_GICD_ITARGETSR11_s ALT_GIC_DIST_GICD_ITARGETSR11_t;
16114 #endif /* __ASSEMBLY__ */
16115 
16116 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR11 register. */
16117 #define ALT_GIC_DIST_GICD_ITARGETSR11_RESET 0x00000000
16118 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR11 register from the beginning of the component. */
16119 #define ALT_GIC_DIST_GICD_ITARGETSR11_OFST 0x82c
16120 
16121 /*
16122  * Register : GICD_ITARGETSR12
16123  *
16124  * Interrupt Processor Targets Registers
16125  *
16126  * Register Layout
16127  *
16128  * Bits | Access | Reset | Description
16129  * :-------|:-------|:------|:------------
16130  * [31:0] | RW | 0x0 | Empty
16131  *
16132  */
16133 /*
16134  * Field : Empty - fld
16135  *
16136  * Placeholder
16137  *
16138  * Field Access Macros:
16139  *
16140  */
16141 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR12_FLD register field. */
16142 #define ALT_GIC_DIST_GICD_ITARGETSR12_FLD_LSB 0
16143 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR12_FLD register field. */
16144 #define ALT_GIC_DIST_GICD_ITARGETSR12_FLD_MSB 31
16145 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR12_FLD register field. */
16146 #define ALT_GIC_DIST_GICD_ITARGETSR12_FLD_WIDTH 32
16147 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR12_FLD register field value. */
16148 #define ALT_GIC_DIST_GICD_ITARGETSR12_FLD_SET_MSK 0xffffffff
16149 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR12_FLD register field value. */
16150 #define ALT_GIC_DIST_GICD_ITARGETSR12_FLD_CLR_MSK 0x00000000
16151 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR12_FLD register field. */
16152 #define ALT_GIC_DIST_GICD_ITARGETSR12_FLD_RESET 0x0
16153 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR12_FLD field value from a register. */
16154 #define ALT_GIC_DIST_GICD_ITARGETSR12_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16155 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR12_FLD register field value suitable for setting the register. */
16156 #define ALT_GIC_DIST_GICD_ITARGETSR12_FLD_SET(value) (((value) << 0) & 0xffffffff)
16157 
16158 #ifndef __ASSEMBLY__
16159 /*
16160  * WARNING: The C register and register group struct declarations are provided for
16161  * convenience and illustrative purposes. They should, however, be used with
16162  * caution as the C language standard provides no guarantees about the alignment or
16163  * atomicity of device memory accesses. The recommended practice for coding device
16164  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16165  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16166  * alt_write_dword() functions for 64 bit registers.
16167  *
16168  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR12.
16169  */
16170 struct ALT_GIC_DIST_GICD_ITARGETSR12_s
16171 {
16172  volatile uint32_t fld : 32; /* Empty */
16173 };
16174 
16175 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR12. */
16176 typedef struct ALT_GIC_DIST_GICD_ITARGETSR12_s ALT_GIC_DIST_GICD_ITARGETSR12_t;
16177 #endif /* __ASSEMBLY__ */
16178 
16179 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR12 register. */
16180 #define ALT_GIC_DIST_GICD_ITARGETSR12_RESET 0x00000000
16181 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR12 register from the beginning of the component. */
16182 #define ALT_GIC_DIST_GICD_ITARGETSR12_OFST 0x830
16183 
16184 /*
16185  * Register : GICD_ITARGETSR13
16186  *
16187  * Interrupt Processor Targets Registers
16188  *
16189  * Register Layout
16190  *
16191  * Bits | Access | Reset | Description
16192  * :-------|:-------|:------|:------------
16193  * [31:0] | RW | 0x0 | Empty
16194  *
16195  */
16196 /*
16197  * Field : Empty - fld
16198  *
16199  * Placeholder
16200  *
16201  * Field Access Macros:
16202  *
16203  */
16204 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR13_FLD register field. */
16205 #define ALT_GIC_DIST_GICD_ITARGETSR13_FLD_LSB 0
16206 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR13_FLD register field. */
16207 #define ALT_GIC_DIST_GICD_ITARGETSR13_FLD_MSB 31
16208 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR13_FLD register field. */
16209 #define ALT_GIC_DIST_GICD_ITARGETSR13_FLD_WIDTH 32
16210 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR13_FLD register field value. */
16211 #define ALT_GIC_DIST_GICD_ITARGETSR13_FLD_SET_MSK 0xffffffff
16212 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR13_FLD register field value. */
16213 #define ALT_GIC_DIST_GICD_ITARGETSR13_FLD_CLR_MSK 0x00000000
16214 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR13_FLD register field. */
16215 #define ALT_GIC_DIST_GICD_ITARGETSR13_FLD_RESET 0x0
16216 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR13_FLD field value from a register. */
16217 #define ALT_GIC_DIST_GICD_ITARGETSR13_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16218 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR13_FLD register field value suitable for setting the register. */
16219 #define ALT_GIC_DIST_GICD_ITARGETSR13_FLD_SET(value) (((value) << 0) & 0xffffffff)
16220 
16221 #ifndef __ASSEMBLY__
16222 /*
16223  * WARNING: The C register and register group struct declarations are provided for
16224  * convenience and illustrative purposes. They should, however, be used with
16225  * caution as the C language standard provides no guarantees about the alignment or
16226  * atomicity of device memory accesses. The recommended practice for coding device
16227  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16228  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16229  * alt_write_dword() functions for 64 bit registers.
16230  *
16231  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR13.
16232  */
16233 struct ALT_GIC_DIST_GICD_ITARGETSR13_s
16234 {
16235  volatile uint32_t fld : 32; /* Empty */
16236 };
16237 
16238 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR13. */
16239 typedef struct ALT_GIC_DIST_GICD_ITARGETSR13_s ALT_GIC_DIST_GICD_ITARGETSR13_t;
16240 #endif /* __ASSEMBLY__ */
16241 
16242 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR13 register. */
16243 #define ALT_GIC_DIST_GICD_ITARGETSR13_RESET 0x00000000
16244 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR13 register from the beginning of the component. */
16245 #define ALT_GIC_DIST_GICD_ITARGETSR13_OFST 0x834
16246 
16247 /*
16248  * Register : GICD_ITARGETSR14
16249  *
16250  * Interrupt Processor Targets Registers
16251  *
16252  * Register Layout
16253  *
16254  * Bits | Access | Reset | Description
16255  * :-------|:-------|:------|:------------
16256  * [31:0] | RW | 0x0 | Empty
16257  *
16258  */
16259 /*
16260  * Field : Empty - fld
16261  *
16262  * Placeholder
16263  *
16264  * Field Access Macros:
16265  *
16266  */
16267 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR14_FLD register field. */
16268 #define ALT_GIC_DIST_GICD_ITARGETSR14_FLD_LSB 0
16269 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR14_FLD register field. */
16270 #define ALT_GIC_DIST_GICD_ITARGETSR14_FLD_MSB 31
16271 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR14_FLD register field. */
16272 #define ALT_GIC_DIST_GICD_ITARGETSR14_FLD_WIDTH 32
16273 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR14_FLD register field value. */
16274 #define ALT_GIC_DIST_GICD_ITARGETSR14_FLD_SET_MSK 0xffffffff
16275 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR14_FLD register field value. */
16276 #define ALT_GIC_DIST_GICD_ITARGETSR14_FLD_CLR_MSK 0x00000000
16277 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR14_FLD register field. */
16278 #define ALT_GIC_DIST_GICD_ITARGETSR14_FLD_RESET 0x0
16279 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR14_FLD field value from a register. */
16280 #define ALT_GIC_DIST_GICD_ITARGETSR14_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16281 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR14_FLD register field value suitable for setting the register. */
16282 #define ALT_GIC_DIST_GICD_ITARGETSR14_FLD_SET(value) (((value) << 0) & 0xffffffff)
16283 
16284 #ifndef __ASSEMBLY__
16285 /*
16286  * WARNING: The C register and register group struct declarations are provided for
16287  * convenience and illustrative purposes. They should, however, be used with
16288  * caution as the C language standard provides no guarantees about the alignment or
16289  * atomicity of device memory accesses. The recommended practice for coding device
16290  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16291  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16292  * alt_write_dword() functions for 64 bit registers.
16293  *
16294  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR14.
16295  */
16296 struct ALT_GIC_DIST_GICD_ITARGETSR14_s
16297 {
16298  volatile uint32_t fld : 32; /* Empty */
16299 };
16300 
16301 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR14. */
16302 typedef struct ALT_GIC_DIST_GICD_ITARGETSR14_s ALT_GIC_DIST_GICD_ITARGETSR14_t;
16303 #endif /* __ASSEMBLY__ */
16304 
16305 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR14 register. */
16306 #define ALT_GIC_DIST_GICD_ITARGETSR14_RESET 0x00000000
16307 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR14 register from the beginning of the component. */
16308 #define ALT_GIC_DIST_GICD_ITARGETSR14_OFST 0x838
16309 
16310 /*
16311  * Register : GICD_ITARGETSR15
16312  *
16313  * Interrupt Processor Targets Registers
16314  *
16315  * Register Layout
16316  *
16317  * Bits | Access | Reset | Description
16318  * :-------|:-------|:------|:------------
16319  * [31:0] | RW | 0x0 | Empty
16320  *
16321  */
16322 /*
16323  * Field : Empty - fld
16324  *
16325  * Placeholder
16326  *
16327  * Field Access Macros:
16328  *
16329  */
16330 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR15_FLD register field. */
16331 #define ALT_GIC_DIST_GICD_ITARGETSR15_FLD_LSB 0
16332 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR15_FLD register field. */
16333 #define ALT_GIC_DIST_GICD_ITARGETSR15_FLD_MSB 31
16334 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR15_FLD register field. */
16335 #define ALT_GIC_DIST_GICD_ITARGETSR15_FLD_WIDTH 32
16336 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR15_FLD register field value. */
16337 #define ALT_GIC_DIST_GICD_ITARGETSR15_FLD_SET_MSK 0xffffffff
16338 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR15_FLD register field value. */
16339 #define ALT_GIC_DIST_GICD_ITARGETSR15_FLD_CLR_MSK 0x00000000
16340 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR15_FLD register field. */
16341 #define ALT_GIC_DIST_GICD_ITARGETSR15_FLD_RESET 0x0
16342 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR15_FLD field value from a register. */
16343 #define ALT_GIC_DIST_GICD_ITARGETSR15_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16344 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR15_FLD register field value suitable for setting the register. */
16345 #define ALT_GIC_DIST_GICD_ITARGETSR15_FLD_SET(value) (((value) << 0) & 0xffffffff)
16346 
16347 #ifndef __ASSEMBLY__
16348 /*
16349  * WARNING: The C register and register group struct declarations are provided for
16350  * convenience and illustrative purposes. They should, however, be used with
16351  * caution as the C language standard provides no guarantees about the alignment or
16352  * atomicity of device memory accesses. The recommended practice for coding device
16353  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16354  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16355  * alt_write_dword() functions for 64 bit registers.
16356  *
16357  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR15.
16358  */
16359 struct ALT_GIC_DIST_GICD_ITARGETSR15_s
16360 {
16361  volatile uint32_t fld : 32; /* Empty */
16362 };
16363 
16364 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR15. */
16365 typedef struct ALT_GIC_DIST_GICD_ITARGETSR15_s ALT_GIC_DIST_GICD_ITARGETSR15_t;
16366 #endif /* __ASSEMBLY__ */
16367 
16368 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR15 register. */
16369 #define ALT_GIC_DIST_GICD_ITARGETSR15_RESET 0x00000000
16370 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR15 register from the beginning of the component. */
16371 #define ALT_GIC_DIST_GICD_ITARGETSR15_OFST 0x83c
16372 
16373 /*
16374  * Register : GICD_ITARGETSR16
16375  *
16376  * Interrupt Processor Targets Registers
16377  *
16378  * Register Layout
16379  *
16380  * Bits | Access | Reset | Description
16381  * :-------|:-------|:------|:------------
16382  * [31:0] | RW | 0x0 | Empty
16383  *
16384  */
16385 /*
16386  * Field : Empty - fld
16387  *
16388  * Placeholder
16389  *
16390  * Field Access Macros:
16391  *
16392  */
16393 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR16_FLD register field. */
16394 #define ALT_GIC_DIST_GICD_ITARGETSR16_FLD_LSB 0
16395 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR16_FLD register field. */
16396 #define ALT_GIC_DIST_GICD_ITARGETSR16_FLD_MSB 31
16397 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR16_FLD register field. */
16398 #define ALT_GIC_DIST_GICD_ITARGETSR16_FLD_WIDTH 32
16399 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR16_FLD register field value. */
16400 #define ALT_GIC_DIST_GICD_ITARGETSR16_FLD_SET_MSK 0xffffffff
16401 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR16_FLD register field value. */
16402 #define ALT_GIC_DIST_GICD_ITARGETSR16_FLD_CLR_MSK 0x00000000
16403 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR16_FLD register field. */
16404 #define ALT_GIC_DIST_GICD_ITARGETSR16_FLD_RESET 0x0
16405 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR16_FLD field value from a register. */
16406 #define ALT_GIC_DIST_GICD_ITARGETSR16_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16407 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR16_FLD register field value suitable for setting the register. */
16408 #define ALT_GIC_DIST_GICD_ITARGETSR16_FLD_SET(value) (((value) << 0) & 0xffffffff)
16409 
16410 #ifndef __ASSEMBLY__
16411 /*
16412  * WARNING: The C register and register group struct declarations are provided for
16413  * convenience and illustrative purposes. They should, however, be used with
16414  * caution as the C language standard provides no guarantees about the alignment or
16415  * atomicity of device memory accesses. The recommended practice for coding device
16416  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16417  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16418  * alt_write_dword() functions for 64 bit registers.
16419  *
16420  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR16.
16421  */
16422 struct ALT_GIC_DIST_GICD_ITARGETSR16_s
16423 {
16424  volatile uint32_t fld : 32; /* Empty */
16425 };
16426 
16427 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR16. */
16428 typedef struct ALT_GIC_DIST_GICD_ITARGETSR16_s ALT_GIC_DIST_GICD_ITARGETSR16_t;
16429 #endif /* __ASSEMBLY__ */
16430 
16431 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR16 register. */
16432 #define ALT_GIC_DIST_GICD_ITARGETSR16_RESET 0x00000000
16433 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR16 register from the beginning of the component. */
16434 #define ALT_GIC_DIST_GICD_ITARGETSR16_OFST 0x840
16435 
16436 /*
16437  * Register : GICD_ITARGETSR17
16438  *
16439  * Interrupt Processor Targets Registers
16440  *
16441  * Register Layout
16442  *
16443  * Bits | Access | Reset | Description
16444  * :-------|:-------|:------|:------------
16445  * [31:0] | RW | 0x0 | Empty
16446  *
16447  */
16448 /*
16449  * Field : Empty - fld
16450  *
16451  * Placeholder
16452  *
16453  * Field Access Macros:
16454  *
16455  */
16456 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR17_FLD register field. */
16457 #define ALT_GIC_DIST_GICD_ITARGETSR17_FLD_LSB 0
16458 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR17_FLD register field. */
16459 #define ALT_GIC_DIST_GICD_ITARGETSR17_FLD_MSB 31
16460 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR17_FLD register field. */
16461 #define ALT_GIC_DIST_GICD_ITARGETSR17_FLD_WIDTH 32
16462 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR17_FLD register field value. */
16463 #define ALT_GIC_DIST_GICD_ITARGETSR17_FLD_SET_MSK 0xffffffff
16464 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR17_FLD register field value. */
16465 #define ALT_GIC_DIST_GICD_ITARGETSR17_FLD_CLR_MSK 0x00000000
16466 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR17_FLD register field. */
16467 #define ALT_GIC_DIST_GICD_ITARGETSR17_FLD_RESET 0x0
16468 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR17_FLD field value from a register. */
16469 #define ALT_GIC_DIST_GICD_ITARGETSR17_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16470 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR17_FLD register field value suitable for setting the register. */
16471 #define ALT_GIC_DIST_GICD_ITARGETSR17_FLD_SET(value) (((value) << 0) & 0xffffffff)
16472 
16473 #ifndef __ASSEMBLY__
16474 /*
16475  * WARNING: The C register and register group struct declarations are provided for
16476  * convenience and illustrative purposes. They should, however, be used with
16477  * caution as the C language standard provides no guarantees about the alignment or
16478  * atomicity of device memory accesses. The recommended practice for coding device
16479  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16480  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16481  * alt_write_dword() functions for 64 bit registers.
16482  *
16483  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR17.
16484  */
16485 struct ALT_GIC_DIST_GICD_ITARGETSR17_s
16486 {
16487  volatile uint32_t fld : 32; /* Empty */
16488 };
16489 
16490 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR17. */
16491 typedef struct ALT_GIC_DIST_GICD_ITARGETSR17_s ALT_GIC_DIST_GICD_ITARGETSR17_t;
16492 #endif /* __ASSEMBLY__ */
16493 
16494 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR17 register. */
16495 #define ALT_GIC_DIST_GICD_ITARGETSR17_RESET 0x00000000
16496 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR17 register from the beginning of the component. */
16497 #define ALT_GIC_DIST_GICD_ITARGETSR17_OFST 0x844
16498 
16499 /*
16500  * Register : GICD_ITARGETSR18
16501  *
16502  * Interrupt Processor Targets Registers
16503  *
16504  * Register Layout
16505  *
16506  * Bits | Access | Reset | Description
16507  * :-------|:-------|:------|:------------
16508  * [31:0] | RW | 0x0 | Empty
16509  *
16510  */
16511 /*
16512  * Field : Empty - fld
16513  *
16514  * Placeholder
16515  *
16516  * Field Access Macros:
16517  *
16518  */
16519 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR18_FLD register field. */
16520 #define ALT_GIC_DIST_GICD_ITARGETSR18_FLD_LSB 0
16521 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR18_FLD register field. */
16522 #define ALT_GIC_DIST_GICD_ITARGETSR18_FLD_MSB 31
16523 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR18_FLD register field. */
16524 #define ALT_GIC_DIST_GICD_ITARGETSR18_FLD_WIDTH 32
16525 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR18_FLD register field value. */
16526 #define ALT_GIC_DIST_GICD_ITARGETSR18_FLD_SET_MSK 0xffffffff
16527 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR18_FLD register field value. */
16528 #define ALT_GIC_DIST_GICD_ITARGETSR18_FLD_CLR_MSK 0x00000000
16529 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR18_FLD register field. */
16530 #define ALT_GIC_DIST_GICD_ITARGETSR18_FLD_RESET 0x0
16531 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR18_FLD field value from a register. */
16532 #define ALT_GIC_DIST_GICD_ITARGETSR18_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16533 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR18_FLD register field value suitable for setting the register. */
16534 #define ALT_GIC_DIST_GICD_ITARGETSR18_FLD_SET(value) (((value) << 0) & 0xffffffff)
16535 
16536 #ifndef __ASSEMBLY__
16537 /*
16538  * WARNING: The C register and register group struct declarations are provided for
16539  * convenience and illustrative purposes. They should, however, be used with
16540  * caution as the C language standard provides no guarantees about the alignment or
16541  * atomicity of device memory accesses. The recommended practice for coding device
16542  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16543  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16544  * alt_write_dword() functions for 64 bit registers.
16545  *
16546  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR18.
16547  */
16548 struct ALT_GIC_DIST_GICD_ITARGETSR18_s
16549 {
16550  volatile uint32_t fld : 32; /* Empty */
16551 };
16552 
16553 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR18. */
16554 typedef struct ALT_GIC_DIST_GICD_ITARGETSR18_s ALT_GIC_DIST_GICD_ITARGETSR18_t;
16555 #endif /* __ASSEMBLY__ */
16556 
16557 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR18 register. */
16558 #define ALT_GIC_DIST_GICD_ITARGETSR18_RESET 0x00000000
16559 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR18 register from the beginning of the component. */
16560 #define ALT_GIC_DIST_GICD_ITARGETSR18_OFST 0x848
16561 
16562 /*
16563  * Register : GICD_ITARGETSR19
16564  *
16565  * Interrupt Processor Targets Registers
16566  *
16567  * Register Layout
16568  *
16569  * Bits | Access | Reset | Description
16570  * :-------|:-------|:------|:------------
16571  * [31:0] | RW | 0x0 | Empty
16572  *
16573  */
16574 /*
16575  * Field : Empty - fld
16576  *
16577  * Placeholder
16578  *
16579  * Field Access Macros:
16580  *
16581  */
16582 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR19_FLD register field. */
16583 #define ALT_GIC_DIST_GICD_ITARGETSR19_FLD_LSB 0
16584 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR19_FLD register field. */
16585 #define ALT_GIC_DIST_GICD_ITARGETSR19_FLD_MSB 31
16586 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR19_FLD register field. */
16587 #define ALT_GIC_DIST_GICD_ITARGETSR19_FLD_WIDTH 32
16588 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR19_FLD register field value. */
16589 #define ALT_GIC_DIST_GICD_ITARGETSR19_FLD_SET_MSK 0xffffffff
16590 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR19_FLD register field value. */
16591 #define ALT_GIC_DIST_GICD_ITARGETSR19_FLD_CLR_MSK 0x00000000
16592 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR19_FLD register field. */
16593 #define ALT_GIC_DIST_GICD_ITARGETSR19_FLD_RESET 0x0
16594 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR19_FLD field value from a register. */
16595 #define ALT_GIC_DIST_GICD_ITARGETSR19_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16596 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR19_FLD register field value suitable for setting the register. */
16597 #define ALT_GIC_DIST_GICD_ITARGETSR19_FLD_SET(value) (((value) << 0) & 0xffffffff)
16598 
16599 #ifndef __ASSEMBLY__
16600 /*
16601  * WARNING: The C register and register group struct declarations are provided for
16602  * convenience and illustrative purposes. They should, however, be used with
16603  * caution as the C language standard provides no guarantees about the alignment or
16604  * atomicity of device memory accesses. The recommended practice for coding device
16605  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16606  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16607  * alt_write_dword() functions for 64 bit registers.
16608  *
16609  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR19.
16610  */
16611 struct ALT_GIC_DIST_GICD_ITARGETSR19_s
16612 {
16613  volatile uint32_t fld : 32; /* Empty */
16614 };
16615 
16616 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR19. */
16617 typedef struct ALT_GIC_DIST_GICD_ITARGETSR19_s ALT_GIC_DIST_GICD_ITARGETSR19_t;
16618 #endif /* __ASSEMBLY__ */
16619 
16620 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR19 register. */
16621 #define ALT_GIC_DIST_GICD_ITARGETSR19_RESET 0x00000000
16622 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR19 register from the beginning of the component. */
16623 #define ALT_GIC_DIST_GICD_ITARGETSR19_OFST 0x84c
16624 
16625 /*
16626  * Register : GICD_ITARGETSR20
16627  *
16628  * Interrupt Processor Targets Registers
16629  *
16630  * Register Layout
16631  *
16632  * Bits | Access | Reset | Description
16633  * :-------|:-------|:------|:------------
16634  * [31:0] | RW | 0x0 | Empty
16635  *
16636  */
16637 /*
16638  * Field : Empty - fld
16639  *
16640  * Placeholder
16641  *
16642  * Field Access Macros:
16643  *
16644  */
16645 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR20_FLD register field. */
16646 #define ALT_GIC_DIST_GICD_ITARGETSR20_FLD_LSB 0
16647 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR20_FLD register field. */
16648 #define ALT_GIC_DIST_GICD_ITARGETSR20_FLD_MSB 31
16649 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR20_FLD register field. */
16650 #define ALT_GIC_DIST_GICD_ITARGETSR20_FLD_WIDTH 32
16651 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR20_FLD register field value. */
16652 #define ALT_GIC_DIST_GICD_ITARGETSR20_FLD_SET_MSK 0xffffffff
16653 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR20_FLD register field value. */
16654 #define ALT_GIC_DIST_GICD_ITARGETSR20_FLD_CLR_MSK 0x00000000
16655 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR20_FLD register field. */
16656 #define ALT_GIC_DIST_GICD_ITARGETSR20_FLD_RESET 0x0
16657 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR20_FLD field value from a register. */
16658 #define ALT_GIC_DIST_GICD_ITARGETSR20_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16659 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR20_FLD register field value suitable for setting the register. */
16660 #define ALT_GIC_DIST_GICD_ITARGETSR20_FLD_SET(value) (((value) << 0) & 0xffffffff)
16661 
16662 #ifndef __ASSEMBLY__
16663 /*
16664  * WARNING: The C register and register group struct declarations are provided for
16665  * convenience and illustrative purposes. They should, however, be used with
16666  * caution as the C language standard provides no guarantees about the alignment or
16667  * atomicity of device memory accesses. The recommended practice for coding device
16668  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16669  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16670  * alt_write_dword() functions for 64 bit registers.
16671  *
16672  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR20.
16673  */
16674 struct ALT_GIC_DIST_GICD_ITARGETSR20_s
16675 {
16676  volatile uint32_t fld : 32; /* Empty */
16677 };
16678 
16679 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR20. */
16680 typedef struct ALT_GIC_DIST_GICD_ITARGETSR20_s ALT_GIC_DIST_GICD_ITARGETSR20_t;
16681 #endif /* __ASSEMBLY__ */
16682 
16683 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR20 register. */
16684 #define ALT_GIC_DIST_GICD_ITARGETSR20_RESET 0x00000000
16685 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR20 register from the beginning of the component. */
16686 #define ALT_GIC_DIST_GICD_ITARGETSR20_OFST 0x850
16687 
16688 /*
16689  * Register : GICD_ITARGETSR21
16690  *
16691  * Interrupt Processor Targets Registers
16692  *
16693  * Register Layout
16694  *
16695  * Bits | Access | Reset | Description
16696  * :-------|:-------|:------|:------------
16697  * [31:0] | RW | 0x0 | Empty
16698  *
16699  */
16700 /*
16701  * Field : Empty - fld
16702  *
16703  * Placeholder
16704  *
16705  * Field Access Macros:
16706  *
16707  */
16708 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR21_FLD register field. */
16709 #define ALT_GIC_DIST_GICD_ITARGETSR21_FLD_LSB 0
16710 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR21_FLD register field. */
16711 #define ALT_GIC_DIST_GICD_ITARGETSR21_FLD_MSB 31
16712 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR21_FLD register field. */
16713 #define ALT_GIC_DIST_GICD_ITARGETSR21_FLD_WIDTH 32
16714 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR21_FLD register field value. */
16715 #define ALT_GIC_DIST_GICD_ITARGETSR21_FLD_SET_MSK 0xffffffff
16716 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR21_FLD register field value. */
16717 #define ALT_GIC_DIST_GICD_ITARGETSR21_FLD_CLR_MSK 0x00000000
16718 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR21_FLD register field. */
16719 #define ALT_GIC_DIST_GICD_ITARGETSR21_FLD_RESET 0x0
16720 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR21_FLD field value from a register. */
16721 #define ALT_GIC_DIST_GICD_ITARGETSR21_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16722 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR21_FLD register field value suitable for setting the register. */
16723 #define ALT_GIC_DIST_GICD_ITARGETSR21_FLD_SET(value) (((value) << 0) & 0xffffffff)
16724 
16725 #ifndef __ASSEMBLY__
16726 /*
16727  * WARNING: The C register and register group struct declarations are provided for
16728  * convenience and illustrative purposes. They should, however, be used with
16729  * caution as the C language standard provides no guarantees about the alignment or
16730  * atomicity of device memory accesses. The recommended practice for coding device
16731  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16732  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16733  * alt_write_dword() functions for 64 bit registers.
16734  *
16735  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR21.
16736  */
16737 struct ALT_GIC_DIST_GICD_ITARGETSR21_s
16738 {
16739  volatile uint32_t fld : 32; /* Empty */
16740 };
16741 
16742 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR21. */
16743 typedef struct ALT_GIC_DIST_GICD_ITARGETSR21_s ALT_GIC_DIST_GICD_ITARGETSR21_t;
16744 #endif /* __ASSEMBLY__ */
16745 
16746 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR21 register. */
16747 #define ALT_GIC_DIST_GICD_ITARGETSR21_RESET 0x00000000
16748 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR21 register from the beginning of the component. */
16749 #define ALT_GIC_DIST_GICD_ITARGETSR21_OFST 0x854
16750 
16751 /*
16752  * Register : GICD_ITARGETSR22
16753  *
16754  * Interrupt Processor Targets Registers
16755  *
16756  * Register Layout
16757  *
16758  * Bits | Access | Reset | Description
16759  * :-------|:-------|:------|:------------
16760  * [31:0] | RW | 0x0 | Empty
16761  *
16762  */
16763 /*
16764  * Field : Empty - fld
16765  *
16766  * Placeholder
16767  *
16768  * Field Access Macros:
16769  *
16770  */
16771 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR22_FLD register field. */
16772 #define ALT_GIC_DIST_GICD_ITARGETSR22_FLD_LSB 0
16773 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR22_FLD register field. */
16774 #define ALT_GIC_DIST_GICD_ITARGETSR22_FLD_MSB 31
16775 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR22_FLD register field. */
16776 #define ALT_GIC_DIST_GICD_ITARGETSR22_FLD_WIDTH 32
16777 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR22_FLD register field value. */
16778 #define ALT_GIC_DIST_GICD_ITARGETSR22_FLD_SET_MSK 0xffffffff
16779 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR22_FLD register field value. */
16780 #define ALT_GIC_DIST_GICD_ITARGETSR22_FLD_CLR_MSK 0x00000000
16781 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR22_FLD register field. */
16782 #define ALT_GIC_DIST_GICD_ITARGETSR22_FLD_RESET 0x0
16783 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR22_FLD field value from a register. */
16784 #define ALT_GIC_DIST_GICD_ITARGETSR22_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16785 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR22_FLD register field value suitable for setting the register. */
16786 #define ALT_GIC_DIST_GICD_ITARGETSR22_FLD_SET(value) (((value) << 0) & 0xffffffff)
16787 
16788 #ifndef __ASSEMBLY__
16789 /*
16790  * WARNING: The C register and register group struct declarations are provided for
16791  * convenience and illustrative purposes. They should, however, be used with
16792  * caution as the C language standard provides no guarantees about the alignment or
16793  * atomicity of device memory accesses. The recommended practice for coding device
16794  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16795  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16796  * alt_write_dword() functions for 64 bit registers.
16797  *
16798  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR22.
16799  */
16800 struct ALT_GIC_DIST_GICD_ITARGETSR22_s
16801 {
16802  volatile uint32_t fld : 32; /* Empty */
16803 };
16804 
16805 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR22. */
16806 typedef struct ALT_GIC_DIST_GICD_ITARGETSR22_s ALT_GIC_DIST_GICD_ITARGETSR22_t;
16807 #endif /* __ASSEMBLY__ */
16808 
16809 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR22 register. */
16810 #define ALT_GIC_DIST_GICD_ITARGETSR22_RESET 0x00000000
16811 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR22 register from the beginning of the component. */
16812 #define ALT_GIC_DIST_GICD_ITARGETSR22_OFST 0x858
16813 
16814 /*
16815  * Register : GICD_ITARGETSR23
16816  *
16817  * Interrupt Processor Targets Registers
16818  *
16819  * Register Layout
16820  *
16821  * Bits | Access | Reset | Description
16822  * :-------|:-------|:------|:------------
16823  * [31:0] | RW | 0x0 | Empty
16824  *
16825  */
16826 /*
16827  * Field : Empty - fld
16828  *
16829  * Placeholder
16830  *
16831  * Field Access Macros:
16832  *
16833  */
16834 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR23_FLD register field. */
16835 #define ALT_GIC_DIST_GICD_ITARGETSR23_FLD_LSB 0
16836 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR23_FLD register field. */
16837 #define ALT_GIC_DIST_GICD_ITARGETSR23_FLD_MSB 31
16838 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR23_FLD register field. */
16839 #define ALT_GIC_DIST_GICD_ITARGETSR23_FLD_WIDTH 32
16840 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR23_FLD register field value. */
16841 #define ALT_GIC_DIST_GICD_ITARGETSR23_FLD_SET_MSK 0xffffffff
16842 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR23_FLD register field value. */
16843 #define ALT_GIC_DIST_GICD_ITARGETSR23_FLD_CLR_MSK 0x00000000
16844 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR23_FLD register field. */
16845 #define ALT_GIC_DIST_GICD_ITARGETSR23_FLD_RESET 0x0
16846 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR23_FLD field value from a register. */
16847 #define ALT_GIC_DIST_GICD_ITARGETSR23_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16848 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR23_FLD register field value suitable for setting the register. */
16849 #define ALT_GIC_DIST_GICD_ITARGETSR23_FLD_SET(value) (((value) << 0) & 0xffffffff)
16850 
16851 #ifndef __ASSEMBLY__
16852 /*
16853  * WARNING: The C register and register group struct declarations are provided for
16854  * convenience and illustrative purposes. They should, however, be used with
16855  * caution as the C language standard provides no guarantees about the alignment or
16856  * atomicity of device memory accesses. The recommended practice for coding device
16857  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16858  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16859  * alt_write_dword() functions for 64 bit registers.
16860  *
16861  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR23.
16862  */
16863 struct ALT_GIC_DIST_GICD_ITARGETSR23_s
16864 {
16865  volatile uint32_t fld : 32; /* Empty */
16866 };
16867 
16868 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR23. */
16869 typedef struct ALT_GIC_DIST_GICD_ITARGETSR23_s ALT_GIC_DIST_GICD_ITARGETSR23_t;
16870 #endif /* __ASSEMBLY__ */
16871 
16872 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR23 register. */
16873 #define ALT_GIC_DIST_GICD_ITARGETSR23_RESET 0x00000000
16874 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR23 register from the beginning of the component. */
16875 #define ALT_GIC_DIST_GICD_ITARGETSR23_OFST 0x85c
16876 
16877 /*
16878  * Register : GICD_ITARGETSR24
16879  *
16880  * Interrupt Processor Targets Registers
16881  *
16882  * Register Layout
16883  *
16884  * Bits | Access | Reset | Description
16885  * :-------|:-------|:------|:------------
16886  * [31:0] | RW | 0x0 | Empty
16887  *
16888  */
16889 /*
16890  * Field : Empty - fld
16891  *
16892  * Placeholder
16893  *
16894  * Field Access Macros:
16895  *
16896  */
16897 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR24_FLD register field. */
16898 #define ALT_GIC_DIST_GICD_ITARGETSR24_FLD_LSB 0
16899 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR24_FLD register field. */
16900 #define ALT_GIC_DIST_GICD_ITARGETSR24_FLD_MSB 31
16901 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR24_FLD register field. */
16902 #define ALT_GIC_DIST_GICD_ITARGETSR24_FLD_WIDTH 32
16903 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR24_FLD register field value. */
16904 #define ALT_GIC_DIST_GICD_ITARGETSR24_FLD_SET_MSK 0xffffffff
16905 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR24_FLD register field value. */
16906 #define ALT_GIC_DIST_GICD_ITARGETSR24_FLD_CLR_MSK 0x00000000
16907 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR24_FLD register field. */
16908 #define ALT_GIC_DIST_GICD_ITARGETSR24_FLD_RESET 0x0
16909 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR24_FLD field value from a register. */
16910 #define ALT_GIC_DIST_GICD_ITARGETSR24_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16911 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR24_FLD register field value suitable for setting the register. */
16912 #define ALT_GIC_DIST_GICD_ITARGETSR24_FLD_SET(value) (((value) << 0) & 0xffffffff)
16913 
16914 #ifndef __ASSEMBLY__
16915 /*
16916  * WARNING: The C register and register group struct declarations are provided for
16917  * convenience and illustrative purposes. They should, however, be used with
16918  * caution as the C language standard provides no guarantees about the alignment or
16919  * atomicity of device memory accesses. The recommended practice for coding device
16920  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16921  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16922  * alt_write_dword() functions for 64 bit registers.
16923  *
16924  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR24.
16925  */
16926 struct ALT_GIC_DIST_GICD_ITARGETSR24_s
16927 {
16928  volatile uint32_t fld : 32; /* Empty */
16929 };
16930 
16931 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR24. */
16932 typedef struct ALT_GIC_DIST_GICD_ITARGETSR24_s ALT_GIC_DIST_GICD_ITARGETSR24_t;
16933 #endif /* __ASSEMBLY__ */
16934 
16935 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR24 register. */
16936 #define ALT_GIC_DIST_GICD_ITARGETSR24_RESET 0x00000000
16937 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR24 register from the beginning of the component. */
16938 #define ALT_GIC_DIST_GICD_ITARGETSR24_OFST 0x860
16939 
16940 /*
16941  * Register : GICD_ITARGETSR25
16942  *
16943  * Interrupt Processor Targets Registers
16944  *
16945  * Register Layout
16946  *
16947  * Bits | Access | Reset | Description
16948  * :-------|:-------|:------|:------------
16949  * [31:0] | RW | 0x0 | Empty
16950  *
16951  */
16952 /*
16953  * Field : Empty - fld
16954  *
16955  * Placeholder
16956  *
16957  * Field Access Macros:
16958  *
16959  */
16960 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR25_FLD register field. */
16961 #define ALT_GIC_DIST_GICD_ITARGETSR25_FLD_LSB 0
16962 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR25_FLD register field. */
16963 #define ALT_GIC_DIST_GICD_ITARGETSR25_FLD_MSB 31
16964 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR25_FLD register field. */
16965 #define ALT_GIC_DIST_GICD_ITARGETSR25_FLD_WIDTH 32
16966 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR25_FLD register field value. */
16967 #define ALT_GIC_DIST_GICD_ITARGETSR25_FLD_SET_MSK 0xffffffff
16968 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR25_FLD register field value. */
16969 #define ALT_GIC_DIST_GICD_ITARGETSR25_FLD_CLR_MSK 0x00000000
16970 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR25_FLD register field. */
16971 #define ALT_GIC_DIST_GICD_ITARGETSR25_FLD_RESET 0x0
16972 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR25_FLD field value from a register. */
16973 #define ALT_GIC_DIST_GICD_ITARGETSR25_FLD_GET(value) (((value) & 0xffffffff) >> 0)
16974 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR25_FLD register field value suitable for setting the register. */
16975 #define ALT_GIC_DIST_GICD_ITARGETSR25_FLD_SET(value) (((value) << 0) & 0xffffffff)
16976 
16977 #ifndef __ASSEMBLY__
16978 /*
16979  * WARNING: The C register and register group struct declarations are provided for
16980  * convenience and illustrative purposes. They should, however, be used with
16981  * caution as the C language standard provides no guarantees about the alignment or
16982  * atomicity of device memory accesses. The recommended practice for coding device
16983  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16984  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16985  * alt_write_dword() functions for 64 bit registers.
16986  *
16987  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR25.
16988  */
16989 struct ALT_GIC_DIST_GICD_ITARGETSR25_s
16990 {
16991  volatile uint32_t fld : 32; /* Empty */
16992 };
16993 
16994 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR25. */
16995 typedef struct ALT_GIC_DIST_GICD_ITARGETSR25_s ALT_GIC_DIST_GICD_ITARGETSR25_t;
16996 #endif /* __ASSEMBLY__ */
16997 
16998 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR25 register. */
16999 #define ALT_GIC_DIST_GICD_ITARGETSR25_RESET 0x00000000
17000 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR25 register from the beginning of the component. */
17001 #define ALT_GIC_DIST_GICD_ITARGETSR25_OFST 0x864
17002 
17003 /*
17004  * Register : GICD_ITARGETSR26
17005  *
17006  * Interrupt Processor Targets Registers
17007  *
17008  * Register Layout
17009  *
17010  * Bits | Access | Reset | Description
17011  * :-------|:-------|:------|:------------
17012  * [31:0] | RW | 0x0 | Empty
17013  *
17014  */
17015 /*
17016  * Field : Empty - fld
17017  *
17018  * Placeholder
17019  *
17020  * Field Access Macros:
17021  *
17022  */
17023 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR26_FLD register field. */
17024 #define ALT_GIC_DIST_GICD_ITARGETSR26_FLD_LSB 0
17025 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR26_FLD register field. */
17026 #define ALT_GIC_DIST_GICD_ITARGETSR26_FLD_MSB 31
17027 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR26_FLD register field. */
17028 #define ALT_GIC_DIST_GICD_ITARGETSR26_FLD_WIDTH 32
17029 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR26_FLD register field value. */
17030 #define ALT_GIC_DIST_GICD_ITARGETSR26_FLD_SET_MSK 0xffffffff
17031 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR26_FLD register field value. */
17032 #define ALT_GIC_DIST_GICD_ITARGETSR26_FLD_CLR_MSK 0x00000000
17033 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR26_FLD register field. */
17034 #define ALT_GIC_DIST_GICD_ITARGETSR26_FLD_RESET 0x0
17035 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR26_FLD field value from a register. */
17036 #define ALT_GIC_DIST_GICD_ITARGETSR26_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17037 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR26_FLD register field value suitable for setting the register. */
17038 #define ALT_GIC_DIST_GICD_ITARGETSR26_FLD_SET(value) (((value) << 0) & 0xffffffff)
17039 
17040 #ifndef __ASSEMBLY__
17041 /*
17042  * WARNING: The C register and register group struct declarations are provided for
17043  * convenience and illustrative purposes. They should, however, be used with
17044  * caution as the C language standard provides no guarantees about the alignment or
17045  * atomicity of device memory accesses. The recommended practice for coding device
17046  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17047  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17048  * alt_write_dword() functions for 64 bit registers.
17049  *
17050  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR26.
17051  */
17052 struct ALT_GIC_DIST_GICD_ITARGETSR26_s
17053 {
17054  volatile uint32_t fld : 32; /* Empty */
17055 };
17056 
17057 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR26. */
17058 typedef struct ALT_GIC_DIST_GICD_ITARGETSR26_s ALT_GIC_DIST_GICD_ITARGETSR26_t;
17059 #endif /* __ASSEMBLY__ */
17060 
17061 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR26 register. */
17062 #define ALT_GIC_DIST_GICD_ITARGETSR26_RESET 0x00000000
17063 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR26 register from the beginning of the component. */
17064 #define ALT_GIC_DIST_GICD_ITARGETSR26_OFST 0x868
17065 
17066 /*
17067  * Register : GICD_ITARGETSR27
17068  *
17069  * Interrupt Processor Targets Registers
17070  *
17071  * Register Layout
17072  *
17073  * Bits | Access | Reset | Description
17074  * :-------|:-------|:------|:------------
17075  * [31:0] | RW | 0x0 | Empty
17076  *
17077  */
17078 /*
17079  * Field : Empty - fld
17080  *
17081  * Placeholder
17082  *
17083  * Field Access Macros:
17084  *
17085  */
17086 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR27_FLD register field. */
17087 #define ALT_GIC_DIST_GICD_ITARGETSR27_FLD_LSB 0
17088 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR27_FLD register field. */
17089 #define ALT_GIC_DIST_GICD_ITARGETSR27_FLD_MSB 31
17090 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR27_FLD register field. */
17091 #define ALT_GIC_DIST_GICD_ITARGETSR27_FLD_WIDTH 32
17092 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR27_FLD register field value. */
17093 #define ALT_GIC_DIST_GICD_ITARGETSR27_FLD_SET_MSK 0xffffffff
17094 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR27_FLD register field value. */
17095 #define ALT_GIC_DIST_GICD_ITARGETSR27_FLD_CLR_MSK 0x00000000
17096 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR27_FLD register field. */
17097 #define ALT_GIC_DIST_GICD_ITARGETSR27_FLD_RESET 0x0
17098 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR27_FLD field value from a register. */
17099 #define ALT_GIC_DIST_GICD_ITARGETSR27_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17100 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR27_FLD register field value suitable for setting the register. */
17101 #define ALT_GIC_DIST_GICD_ITARGETSR27_FLD_SET(value) (((value) << 0) & 0xffffffff)
17102 
17103 #ifndef __ASSEMBLY__
17104 /*
17105  * WARNING: The C register and register group struct declarations are provided for
17106  * convenience and illustrative purposes. They should, however, be used with
17107  * caution as the C language standard provides no guarantees about the alignment or
17108  * atomicity of device memory accesses. The recommended practice for coding device
17109  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17110  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17111  * alt_write_dword() functions for 64 bit registers.
17112  *
17113  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR27.
17114  */
17115 struct ALT_GIC_DIST_GICD_ITARGETSR27_s
17116 {
17117  volatile uint32_t fld : 32; /* Empty */
17118 };
17119 
17120 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR27. */
17121 typedef struct ALT_GIC_DIST_GICD_ITARGETSR27_s ALT_GIC_DIST_GICD_ITARGETSR27_t;
17122 #endif /* __ASSEMBLY__ */
17123 
17124 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR27 register. */
17125 #define ALT_GIC_DIST_GICD_ITARGETSR27_RESET 0x00000000
17126 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR27 register from the beginning of the component. */
17127 #define ALT_GIC_DIST_GICD_ITARGETSR27_OFST 0x86c
17128 
17129 /*
17130  * Register : GICD_ITARGETSR28
17131  *
17132  * Interrupt Processor Targets Registers
17133  *
17134  * Register Layout
17135  *
17136  * Bits | Access | Reset | Description
17137  * :-------|:-------|:------|:------------
17138  * [31:0] | RW | 0x0 | Empty
17139  *
17140  */
17141 /*
17142  * Field : Empty - fld
17143  *
17144  * Placeholder
17145  *
17146  * Field Access Macros:
17147  *
17148  */
17149 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR28_FLD register field. */
17150 #define ALT_GIC_DIST_GICD_ITARGETSR28_FLD_LSB 0
17151 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR28_FLD register field. */
17152 #define ALT_GIC_DIST_GICD_ITARGETSR28_FLD_MSB 31
17153 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR28_FLD register field. */
17154 #define ALT_GIC_DIST_GICD_ITARGETSR28_FLD_WIDTH 32
17155 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR28_FLD register field value. */
17156 #define ALT_GIC_DIST_GICD_ITARGETSR28_FLD_SET_MSK 0xffffffff
17157 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR28_FLD register field value. */
17158 #define ALT_GIC_DIST_GICD_ITARGETSR28_FLD_CLR_MSK 0x00000000
17159 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR28_FLD register field. */
17160 #define ALT_GIC_DIST_GICD_ITARGETSR28_FLD_RESET 0x0
17161 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR28_FLD field value from a register. */
17162 #define ALT_GIC_DIST_GICD_ITARGETSR28_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17163 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR28_FLD register field value suitable for setting the register. */
17164 #define ALT_GIC_DIST_GICD_ITARGETSR28_FLD_SET(value) (((value) << 0) & 0xffffffff)
17165 
17166 #ifndef __ASSEMBLY__
17167 /*
17168  * WARNING: The C register and register group struct declarations are provided for
17169  * convenience and illustrative purposes. They should, however, be used with
17170  * caution as the C language standard provides no guarantees about the alignment or
17171  * atomicity of device memory accesses. The recommended practice for coding device
17172  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17173  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17174  * alt_write_dword() functions for 64 bit registers.
17175  *
17176  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR28.
17177  */
17178 struct ALT_GIC_DIST_GICD_ITARGETSR28_s
17179 {
17180  volatile uint32_t fld : 32; /* Empty */
17181 };
17182 
17183 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR28. */
17184 typedef struct ALT_GIC_DIST_GICD_ITARGETSR28_s ALT_GIC_DIST_GICD_ITARGETSR28_t;
17185 #endif /* __ASSEMBLY__ */
17186 
17187 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR28 register. */
17188 #define ALT_GIC_DIST_GICD_ITARGETSR28_RESET 0x00000000
17189 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR28 register from the beginning of the component. */
17190 #define ALT_GIC_DIST_GICD_ITARGETSR28_OFST 0x870
17191 
17192 /*
17193  * Register : GICD_ITARGETSR29
17194  *
17195  * Interrupt Processor Targets Registers
17196  *
17197  * Register Layout
17198  *
17199  * Bits | Access | Reset | Description
17200  * :-------|:-------|:------|:------------
17201  * [31:0] | RW | 0x0 | Empty
17202  *
17203  */
17204 /*
17205  * Field : Empty - fld
17206  *
17207  * Placeholder
17208  *
17209  * Field Access Macros:
17210  *
17211  */
17212 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR29_FLD register field. */
17213 #define ALT_GIC_DIST_GICD_ITARGETSR29_FLD_LSB 0
17214 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR29_FLD register field. */
17215 #define ALT_GIC_DIST_GICD_ITARGETSR29_FLD_MSB 31
17216 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR29_FLD register field. */
17217 #define ALT_GIC_DIST_GICD_ITARGETSR29_FLD_WIDTH 32
17218 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR29_FLD register field value. */
17219 #define ALT_GIC_DIST_GICD_ITARGETSR29_FLD_SET_MSK 0xffffffff
17220 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR29_FLD register field value. */
17221 #define ALT_GIC_DIST_GICD_ITARGETSR29_FLD_CLR_MSK 0x00000000
17222 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR29_FLD register field. */
17223 #define ALT_GIC_DIST_GICD_ITARGETSR29_FLD_RESET 0x0
17224 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR29_FLD field value from a register. */
17225 #define ALT_GIC_DIST_GICD_ITARGETSR29_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17226 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR29_FLD register field value suitable for setting the register. */
17227 #define ALT_GIC_DIST_GICD_ITARGETSR29_FLD_SET(value) (((value) << 0) & 0xffffffff)
17228 
17229 #ifndef __ASSEMBLY__
17230 /*
17231  * WARNING: The C register and register group struct declarations are provided for
17232  * convenience and illustrative purposes. They should, however, be used with
17233  * caution as the C language standard provides no guarantees about the alignment or
17234  * atomicity of device memory accesses. The recommended practice for coding device
17235  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17236  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17237  * alt_write_dword() functions for 64 bit registers.
17238  *
17239  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR29.
17240  */
17241 struct ALT_GIC_DIST_GICD_ITARGETSR29_s
17242 {
17243  volatile uint32_t fld : 32; /* Empty */
17244 };
17245 
17246 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR29. */
17247 typedef struct ALT_GIC_DIST_GICD_ITARGETSR29_s ALT_GIC_DIST_GICD_ITARGETSR29_t;
17248 #endif /* __ASSEMBLY__ */
17249 
17250 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR29 register. */
17251 #define ALT_GIC_DIST_GICD_ITARGETSR29_RESET 0x00000000
17252 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR29 register from the beginning of the component. */
17253 #define ALT_GIC_DIST_GICD_ITARGETSR29_OFST 0x874
17254 
17255 /*
17256  * Register : GICD_ITARGETSR30
17257  *
17258  * Interrupt Processor Targets Registers
17259  *
17260  * Register Layout
17261  *
17262  * Bits | Access | Reset | Description
17263  * :-------|:-------|:------|:------------
17264  * [31:0] | RW | 0x0 | Empty
17265  *
17266  */
17267 /*
17268  * Field : Empty - fld
17269  *
17270  * Placeholder
17271  *
17272  * Field Access Macros:
17273  *
17274  */
17275 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR30_FLD register field. */
17276 #define ALT_GIC_DIST_GICD_ITARGETSR30_FLD_LSB 0
17277 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR30_FLD register field. */
17278 #define ALT_GIC_DIST_GICD_ITARGETSR30_FLD_MSB 31
17279 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR30_FLD register field. */
17280 #define ALT_GIC_DIST_GICD_ITARGETSR30_FLD_WIDTH 32
17281 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR30_FLD register field value. */
17282 #define ALT_GIC_DIST_GICD_ITARGETSR30_FLD_SET_MSK 0xffffffff
17283 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR30_FLD register field value. */
17284 #define ALT_GIC_DIST_GICD_ITARGETSR30_FLD_CLR_MSK 0x00000000
17285 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR30_FLD register field. */
17286 #define ALT_GIC_DIST_GICD_ITARGETSR30_FLD_RESET 0x0
17287 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR30_FLD field value from a register. */
17288 #define ALT_GIC_DIST_GICD_ITARGETSR30_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17289 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR30_FLD register field value suitable for setting the register. */
17290 #define ALT_GIC_DIST_GICD_ITARGETSR30_FLD_SET(value) (((value) << 0) & 0xffffffff)
17291 
17292 #ifndef __ASSEMBLY__
17293 /*
17294  * WARNING: The C register and register group struct declarations are provided for
17295  * convenience and illustrative purposes. They should, however, be used with
17296  * caution as the C language standard provides no guarantees about the alignment or
17297  * atomicity of device memory accesses. The recommended practice for coding device
17298  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17299  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17300  * alt_write_dword() functions for 64 bit registers.
17301  *
17302  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR30.
17303  */
17304 struct ALT_GIC_DIST_GICD_ITARGETSR30_s
17305 {
17306  volatile uint32_t fld : 32; /* Empty */
17307 };
17308 
17309 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR30. */
17310 typedef struct ALT_GIC_DIST_GICD_ITARGETSR30_s ALT_GIC_DIST_GICD_ITARGETSR30_t;
17311 #endif /* __ASSEMBLY__ */
17312 
17313 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR30 register. */
17314 #define ALT_GIC_DIST_GICD_ITARGETSR30_RESET 0x00000000
17315 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR30 register from the beginning of the component. */
17316 #define ALT_GIC_DIST_GICD_ITARGETSR30_OFST 0x878
17317 
17318 /*
17319  * Register : GICD_ITARGETSR31
17320  *
17321  * Interrupt Processor Targets Registers
17322  *
17323  * Register Layout
17324  *
17325  * Bits | Access | Reset | Description
17326  * :-------|:-------|:------|:------------
17327  * [31:0] | RW | 0x0 | Empty
17328  *
17329  */
17330 /*
17331  * Field : Empty - fld
17332  *
17333  * Placeholder
17334  *
17335  * Field Access Macros:
17336  *
17337  */
17338 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR31_FLD register field. */
17339 #define ALT_GIC_DIST_GICD_ITARGETSR31_FLD_LSB 0
17340 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR31_FLD register field. */
17341 #define ALT_GIC_DIST_GICD_ITARGETSR31_FLD_MSB 31
17342 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR31_FLD register field. */
17343 #define ALT_GIC_DIST_GICD_ITARGETSR31_FLD_WIDTH 32
17344 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR31_FLD register field value. */
17345 #define ALT_GIC_DIST_GICD_ITARGETSR31_FLD_SET_MSK 0xffffffff
17346 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR31_FLD register field value. */
17347 #define ALT_GIC_DIST_GICD_ITARGETSR31_FLD_CLR_MSK 0x00000000
17348 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR31_FLD register field. */
17349 #define ALT_GIC_DIST_GICD_ITARGETSR31_FLD_RESET 0x0
17350 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR31_FLD field value from a register. */
17351 #define ALT_GIC_DIST_GICD_ITARGETSR31_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17352 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR31_FLD register field value suitable for setting the register. */
17353 #define ALT_GIC_DIST_GICD_ITARGETSR31_FLD_SET(value) (((value) << 0) & 0xffffffff)
17354 
17355 #ifndef __ASSEMBLY__
17356 /*
17357  * WARNING: The C register and register group struct declarations are provided for
17358  * convenience and illustrative purposes. They should, however, be used with
17359  * caution as the C language standard provides no guarantees about the alignment or
17360  * atomicity of device memory accesses. The recommended practice for coding device
17361  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17362  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17363  * alt_write_dword() functions for 64 bit registers.
17364  *
17365  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR31.
17366  */
17367 struct ALT_GIC_DIST_GICD_ITARGETSR31_s
17368 {
17369  volatile uint32_t fld : 32; /* Empty */
17370 };
17371 
17372 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR31. */
17373 typedef struct ALT_GIC_DIST_GICD_ITARGETSR31_s ALT_GIC_DIST_GICD_ITARGETSR31_t;
17374 #endif /* __ASSEMBLY__ */
17375 
17376 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR31 register. */
17377 #define ALT_GIC_DIST_GICD_ITARGETSR31_RESET 0x00000000
17378 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR31 register from the beginning of the component. */
17379 #define ALT_GIC_DIST_GICD_ITARGETSR31_OFST 0x87c
17380 
17381 /*
17382  * Register : GICD_ITARGETSR32
17383  *
17384  * Interrupt Processor Targets Registers
17385  *
17386  * Register Layout
17387  *
17388  * Bits | Access | Reset | Description
17389  * :-------|:-------|:------|:------------
17390  * [31:0] | RW | 0x0 | Empty
17391  *
17392  */
17393 /*
17394  * Field : Empty - fld
17395  *
17396  * Placeholder
17397  *
17398  * Field Access Macros:
17399  *
17400  */
17401 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR32_FLD register field. */
17402 #define ALT_GIC_DIST_GICD_ITARGETSR32_FLD_LSB 0
17403 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR32_FLD register field. */
17404 #define ALT_GIC_DIST_GICD_ITARGETSR32_FLD_MSB 31
17405 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR32_FLD register field. */
17406 #define ALT_GIC_DIST_GICD_ITARGETSR32_FLD_WIDTH 32
17407 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR32_FLD register field value. */
17408 #define ALT_GIC_DIST_GICD_ITARGETSR32_FLD_SET_MSK 0xffffffff
17409 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR32_FLD register field value. */
17410 #define ALT_GIC_DIST_GICD_ITARGETSR32_FLD_CLR_MSK 0x00000000
17411 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR32_FLD register field. */
17412 #define ALT_GIC_DIST_GICD_ITARGETSR32_FLD_RESET 0x0
17413 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR32_FLD field value from a register. */
17414 #define ALT_GIC_DIST_GICD_ITARGETSR32_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17415 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR32_FLD register field value suitable for setting the register. */
17416 #define ALT_GIC_DIST_GICD_ITARGETSR32_FLD_SET(value) (((value) << 0) & 0xffffffff)
17417 
17418 #ifndef __ASSEMBLY__
17419 /*
17420  * WARNING: The C register and register group struct declarations are provided for
17421  * convenience and illustrative purposes. They should, however, be used with
17422  * caution as the C language standard provides no guarantees about the alignment or
17423  * atomicity of device memory accesses. The recommended practice for coding device
17424  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17425  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17426  * alt_write_dword() functions for 64 bit registers.
17427  *
17428  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR32.
17429  */
17430 struct ALT_GIC_DIST_GICD_ITARGETSR32_s
17431 {
17432  volatile uint32_t fld : 32; /* Empty */
17433 };
17434 
17435 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR32. */
17436 typedef struct ALT_GIC_DIST_GICD_ITARGETSR32_s ALT_GIC_DIST_GICD_ITARGETSR32_t;
17437 #endif /* __ASSEMBLY__ */
17438 
17439 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR32 register. */
17440 #define ALT_GIC_DIST_GICD_ITARGETSR32_RESET 0x00000000
17441 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR32 register from the beginning of the component. */
17442 #define ALT_GIC_DIST_GICD_ITARGETSR32_OFST 0x880
17443 
17444 /*
17445  * Register : GICD_ITARGETSR33
17446  *
17447  * Interrupt Processor Targets Registers
17448  *
17449  * Register Layout
17450  *
17451  * Bits | Access | Reset | Description
17452  * :-------|:-------|:------|:------------
17453  * [31:0] | RW | 0x0 | Empty
17454  *
17455  */
17456 /*
17457  * Field : Empty - fld
17458  *
17459  * Placeholder
17460  *
17461  * Field Access Macros:
17462  *
17463  */
17464 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR33_FLD register field. */
17465 #define ALT_GIC_DIST_GICD_ITARGETSR33_FLD_LSB 0
17466 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR33_FLD register field. */
17467 #define ALT_GIC_DIST_GICD_ITARGETSR33_FLD_MSB 31
17468 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR33_FLD register field. */
17469 #define ALT_GIC_DIST_GICD_ITARGETSR33_FLD_WIDTH 32
17470 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR33_FLD register field value. */
17471 #define ALT_GIC_DIST_GICD_ITARGETSR33_FLD_SET_MSK 0xffffffff
17472 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR33_FLD register field value. */
17473 #define ALT_GIC_DIST_GICD_ITARGETSR33_FLD_CLR_MSK 0x00000000
17474 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR33_FLD register field. */
17475 #define ALT_GIC_DIST_GICD_ITARGETSR33_FLD_RESET 0x0
17476 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR33_FLD field value from a register. */
17477 #define ALT_GIC_DIST_GICD_ITARGETSR33_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17478 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR33_FLD register field value suitable for setting the register. */
17479 #define ALT_GIC_DIST_GICD_ITARGETSR33_FLD_SET(value) (((value) << 0) & 0xffffffff)
17480 
17481 #ifndef __ASSEMBLY__
17482 /*
17483  * WARNING: The C register and register group struct declarations are provided for
17484  * convenience and illustrative purposes. They should, however, be used with
17485  * caution as the C language standard provides no guarantees about the alignment or
17486  * atomicity of device memory accesses. The recommended practice for coding device
17487  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17488  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17489  * alt_write_dword() functions for 64 bit registers.
17490  *
17491  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR33.
17492  */
17493 struct ALT_GIC_DIST_GICD_ITARGETSR33_s
17494 {
17495  volatile uint32_t fld : 32; /* Empty */
17496 };
17497 
17498 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR33. */
17499 typedef struct ALT_GIC_DIST_GICD_ITARGETSR33_s ALT_GIC_DIST_GICD_ITARGETSR33_t;
17500 #endif /* __ASSEMBLY__ */
17501 
17502 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR33 register. */
17503 #define ALT_GIC_DIST_GICD_ITARGETSR33_RESET 0x00000000
17504 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR33 register from the beginning of the component. */
17505 #define ALT_GIC_DIST_GICD_ITARGETSR33_OFST 0x884
17506 
17507 /*
17508  * Register : GICD_ITARGETSR34
17509  *
17510  * Interrupt Processor Targets Registers
17511  *
17512  * Register Layout
17513  *
17514  * Bits | Access | Reset | Description
17515  * :-------|:-------|:------|:------------
17516  * [31:0] | RW | 0x0 | Empty
17517  *
17518  */
17519 /*
17520  * Field : Empty - fld
17521  *
17522  * Placeholder
17523  *
17524  * Field Access Macros:
17525  *
17526  */
17527 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR34_FLD register field. */
17528 #define ALT_GIC_DIST_GICD_ITARGETSR34_FLD_LSB 0
17529 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR34_FLD register field. */
17530 #define ALT_GIC_DIST_GICD_ITARGETSR34_FLD_MSB 31
17531 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR34_FLD register field. */
17532 #define ALT_GIC_DIST_GICD_ITARGETSR34_FLD_WIDTH 32
17533 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR34_FLD register field value. */
17534 #define ALT_GIC_DIST_GICD_ITARGETSR34_FLD_SET_MSK 0xffffffff
17535 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR34_FLD register field value. */
17536 #define ALT_GIC_DIST_GICD_ITARGETSR34_FLD_CLR_MSK 0x00000000
17537 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR34_FLD register field. */
17538 #define ALT_GIC_DIST_GICD_ITARGETSR34_FLD_RESET 0x0
17539 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR34_FLD field value from a register. */
17540 #define ALT_GIC_DIST_GICD_ITARGETSR34_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17541 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR34_FLD register field value suitable for setting the register. */
17542 #define ALT_GIC_DIST_GICD_ITARGETSR34_FLD_SET(value) (((value) << 0) & 0xffffffff)
17543 
17544 #ifndef __ASSEMBLY__
17545 /*
17546  * WARNING: The C register and register group struct declarations are provided for
17547  * convenience and illustrative purposes. They should, however, be used with
17548  * caution as the C language standard provides no guarantees about the alignment or
17549  * atomicity of device memory accesses. The recommended practice for coding device
17550  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17551  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17552  * alt_write_dword() functions for 64 bit registers.
17553  *
17554  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR34.
17555  */
17556 struct ALT_GIC_DIST_GICD_ITARGETSR34_s
17557 {
17558  volatile uint32_t fld : 32; /* Empty */
17559 };
17560 
17561 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR34. */
17562 typedef struct ALT_GIC_DIST_GICD_ITARGETSR34_s ALT_GIC_DIST_GICD_ITARGETSR34_t;
17563 #endif /* __ASSEMBLY__ */
17564 
17565 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR34 register. */
17566 #define ALT_GIC_DIST_GICD_ITARGETSR34_RESET 0x00000000
17567 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR34 register from the beginning of the component. */
17568 #define ALT_GIC_DIST_GICD_ITARGETSR34_OFST 0x888
17569 
17570 /*
17571  * Register : GICD_ITARGETSR35
17572  *
17573  * Interrupt Processor Targets Registers
17574  *
17575  * Register Layout
17576  *
17577  * Bits | Access | Reset | Description
17578  * :-------|:-------|:------|:------------
17579  * [31:0] | RW | 0x0 | Empty
17580  *
17581  */
17582 /*
17583  * Field : Empty - fld
17584  *
17585  * Placeholder
17586  *
17587  * Field Access Macros:
17588  *
17589  */
17590 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR35_FLD register field. */
17591 #define ALT_GIC_DIST_GICD_ITARGETSR35_FLD_LSB 0
17592 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR35_FLD register field. */
17593 #define ALT_GIC_DIST_GICD_ITARGETSR35_FLD_MSB 31
17594 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR35_FLD register field. */
17595 #define ALT_GIC_DIST_GICD_ITARGETSR35_FLD_WIDTH 32
17596 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR35_FLD register field value. */
17597 #define ALT_GIC_DIST_GICD_ITARGETSR35_FLD_SET_MSK 0xffffffff
17598 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR35_FLD register field value. */
17599 #define ALT_GIC_DIST_GICD_ITARGETSR35_FLD_CLR_MSK 0x00000000
17600 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR35_FLD register field. */
17601 #define ALT_GIC_DIST_GICD_ITARGETSR35_FLD_RESET 0x0
17602 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR35_FLD field value from a register. */
17603 #define ALT_GIC_DIST_GICD_ITARGETSR35_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17604 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR35_FLD register field value suitable for setting the register. */
17605 #define ALT_GIC_DIST_GICD_ITARGETSR35_FLD_SET(value) (((value) << 0) & 0xffffffff)
17606 
17607 #ifndef __ASSEMBLY__
17608 /*
17609  * WARNING: The C register and register group struct declarations are provided for
17610  * convenience and illustrative purposes. They should, however, be used with
17611  * caution as the C language standard provides no guarantees about the alignment or
17612  * atomicity of device memory accesses. The recommended practice for coding device
17613  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17614  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17615  * alt_write_dword() functions for 64 bit registers.
17616  *
17617  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR35.
17618  */
17619 struct ALT_GIC_DIST_GICD_ITARGETSR35_s
17620 {
17621  volatile uint32_t fld : 32; /* Empty */
17622 };
17623 
17624 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR35. */
17625 typedef struct ALT_GIC_DIST_GICD_ITARGETSR35_s ALT_GIC_DIST_GICD_ITARGETSR35_t;
17626 #endif /* __ASSEMBLY__ */
17627 
17628 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR35 register. */
17629 #define ALT_GIC_DIST_GICD_ITARGETSR35_RESET 0x00000000
17630 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR35 register from the beginning of the component. */
17631 #define ALT_GIC_DIST_GICD_ITARGETSR35_OFST 0x88c
17632 
17633 /*
17634  * Register : GICD_ITARGETSR36
17635  *
17636  * Interrupt Processor Targets Registers
17637  *
17638  * Register Layout
17639  *
17640  * Bits | Access | Reset | Description
17641  * :-------|:-------|:------|:------------
17642  * [31:0] | RW | 0x0 | Empty
17643  *
17644  */
17645 /*
17646  * Field : Empty - fld
17647  *
17648  * Placeholder
17649  *
17650  * Field Access Macros:
17651  *
17652  */
17653 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR36_FLD register field. */
17654 #define ALT_GIC_DIST_GICD_ITARGETSR36_FLD_LSB 0
17655 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR36_FLD register field. */
17656 #define ALT_GIC_DIST_GICD_ITARGETSR36_FLD_MSB 31
17657 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR36_FLD register field. */
17658 #define ALT_GIC_DIST_GICD_ITARGETSR36_FLD_WIDTH 32
17659 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR36_FLD register field value. */
17660 #define ALT_GIC_DIST_GICD_ITARGETSR36_FLD_SET_MSK 0xffffffff
17661 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR36_FLD register field value. */
17662 #define ALT_GIC_DIST_GICD_ITARGETSR36_FLD_CLR_MSK 0x00000000
17663 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR36_FLD register field. */
17664 #define ALT_GIC_DIST_GICD_ITARGETSR36_FLD_RESET 0x0
17665 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR36_FLD field value from a register. */
17666 #define ALT_GIC_DIST_GICD_ITARGETSR36_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17667 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR36_FLD register field value suitable for setting the register. */
17668 #define ALT_GIC_DIST_GICD_ITARGETSR36_FLD_SET(value) (((value) << 0) & 0xffffffff)
17669 
17670 #ifndef __ASSEMBLY__
17671 /*
17672  * WARNING: The C register and register group struct declarations are provided for
17673  * convenience and illustrative purposes. They should, however, be used with
17674  * caution as the C language standard provides no guarantees about the alignment or
17675  * atomicity of device memory accesses. The recommended practice for coding device
17676  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17677  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17678  * alt_write_dword() functions for 64 bit registers.
17679  *
17680  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR36.
17681  */
17682 struct ALT_GIC_DIST_GICD_ITARGETSR36_s
17683 {
17684  volatile uint32_t fld : 32; /* Empty */
17685 };
17686 
17687 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR36. */
17688 typedef struct ALT_GIC_DIST_GICD_ITARGETSR36_s ALT_GIC_DIST_GICD_ITARGETSR36_t;
17689 #endif /* __ASSEMBLY__ */
17690 
17691 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR36 register. */
17692 #define ALT_GIC_DIST_GICD_ITARGETSR36_RESET 0x00000000
17693 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR36 register from the beginning of the component. */
17694 #define ALT_GIC_DIST_GICD_ITARGETSR36_OFST 0x890
17695 
17696 /*
17697  * Register : GICD_ITARGETSR37
17698  *
17699  * Interrupt Processor Targets Registers
17700  *
17701  * Register Layout
17702  *
17703  * Bits | Access | Reset | Description
17704  * :-------|:-------|:------|:------------
17705  * [31:0] | RW | 0x0 | Empty
17706  *
17707  */
17708 /*
17709  * Field : Empty - fld
17710  *
17711  * Placeholder
17712  *
17713  * Field Access Macros:
17714  *
17715  */
17716 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR37_FLD register field. */
17717 #define ALT_GIC_DIST_GICD_ITARGETSR37_FLD_LSB 0
17718 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR37_FLD register field. */
17719 #define ALT_GIC_DIST_GICD_ITARGETSR37_FLD_MSB 31
17720 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR37_FLD register field. */
17721 #define ALT_GIC_DIST_GICD_ITARGETSR37_FLD_WIDTH 32
17722 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR37_FLD register field value. */
17723 #define ALT_GIC_DIST_GICD_ITARGETSR37_FLD_SET_MSK 0xffffffff
17724 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR37_FLD register field value. */
17725 #define ALT_GIC_DIST_GICD_ITARGETSR37_FLD_CLR_MSK 0x00000000
17726 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR37_FLD register field. */
17727 #define ALT_GIC_DIST_GICD_ITARGETSR37_FLD_RESET 0x0
17728 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR37_FLD field value from a register. */
17729 #define ALT_GIC_DIST_GICD_ITARGETSR37_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17730 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR37_FLD register field value suitable for setting the register. */
17731 #define ALT_GIC_DIST_GICD_ITARGETSR37_FLD_SET(value) (((value) << 0) & 0xffffffff)
17732 
17733 #ifndef __ASSEMBLY__
17734 /*
17735  * WARNING: The C register and register group struct declarations are provided for
17736  * convenience and illustrative purposes. They should, however, be used with
17737  * caution as the C language standard provides no guarantees about the alignment or
17738  * atomicity of device memory accesses. The recommended practice for coding device
17739  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17740  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17741  * alt_write_dword() functions for 64 bit registers.
17742  *
17743  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR37.
17744  */
17745 struct ALT_GIC_DIST_GICD_ITARGETSR37_s
17746 {
17747  volatile uint32_t fld : 32; /* Empty */
17748 };
17749 
17750 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR37. */
17751 typedef struct ALT_GIC_DIST_GICD_ITARGETSR37_s ALT_GIC_DIST_GICD_ITARGETSR37_t;
17752 #endif /* __ASSEMBLY__ */
17753 
17754 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR37 register. */
17755 #define ALT_GIC_DIST_GICD_ITARGETSR37_RESET 0x00000000
17756 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR37 register from the beginning of the component. */
17757 #define ALT_GIC_DIST_GICD_ITARGETSR37_OFST 0x894
17758 
17759 /*
17760  * Register : GICD_ITARGETSR38
17761  *
17762  * Interrupt Processor Targets Registers
17763  *
17764  * Register Layout
17765  *
17766  * Bits | Access | Reset | Description
17767  * :-------|:-------|:------|:------------
17768  * [31:0] | RW | 0x0 | Empty
17769  *
17770  */
17771 /*
17772  * Field : Empty - fld
17773  *
17774  * Placeholder
17775  *
17776  * Field Access Macros:
17777  *
17778  */
17779 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR38_FLD register field. */
17780 #define ALT_GIC_DIST_GICD_ITARGETSR38_FLD_LSB 0
17781 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR38_FLD register field. */
17782 #define ALT_GIC_DIST_GICD_ITARGETSR38_FLD_MSB 31
17783 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR38_FLD register field. */
17784 #define ALT_GIC_DIST_GICD_ITARGETSR38_FLD_WIDTH 32
17785 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR38_FLD register field value. */
17786 #define ALT_GIC_DIST_GICD_ITARGETSR38_FLD_SET_MSK 0xffffffff
17787 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR38_FLD register field value. */
17788 #define ALT_GIC_DIST_GICD_ITARGETSR38_FLD_CLR_MSK 0x00000000
17789 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR38_FLD register field. */
17790 #define ALT_GIC_DIST_GICD_ITARGETSR38_FLD_RESET 0x0
17791 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR38_FLD field value from a register. */
17792 #define ALT_GIC_DIST_GICD_ITARGETSR38_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17793 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR38_FLD register field value suitable for setting the register. */
17794 #define ALT_GIC_DIST_GICD_ITARGETSR38_FLD_SET(value) (((value) << 0) & 0xffffffff)
17795 
17796 #ifndef __ASSEMBLY__
17797 /*
17798  * WARNING: The C register and register group struct declarations are provided for
17799  * convenience and illustrative purposes. They should, however, be used with
17800  * caution as the C language standard provides no guarantees about the alignment or
17801  * atomicity of device memory accesses. The recommended practice for coding device
17802  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17803  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17804  * alt_write_dword() functions for 64 bit registers.
17805  *
17806  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR38.
17807  */
17808 struct ALT_GIC_DIST_GICD_ITARGETSR38_s
17809 {
17810  volatile uint32_t fld : 32; /* Empty */
17811 };
17812 
17813 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR38. */
17814 typedef struct ALT_GIC_DIST_GICD_ITARGETSR38_s ALT_GIC_DIST_GICD_ITARGETSR38_t;
17815 #endif /* __ASSEMBLY__ */
17816 
17817 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR38 register. */
17818 #define ALT_GIC_DIST_GICD_ITARGETSR38_RESET 0x00000000
17819 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR38 register from the beginning of the component. */
17820 #define ALT_GIC_DIST_GICD_ITARGETSR38_OFST 0x898
17821 
17822 /*
17823  * Register : GICD_ITARGETSR39
17824  *
17825  * Interrupt Processor Targets Registers
17826  *
17827  * Register Layout
17828  *
17829  * Bits | Access | Reset | Description
17830  * :-------|:-------|:------|:------------
17831  * [31:0] | RW | 0x0 | Empty
17832  *
17833  */
17834 /*
17835  * Field : Empty - fld
17836  *
17837  * Placeholder
17838  *
17839  * Field Access Macros:
17840  *
17841  */
17842 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR39_FLD register field. */
17843 #define ALT_GIC_DIST_GICD_ITARGETSR39_FLD_LSB 0
17844 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR39_FLD register field. */
17845 #define ALT_GIC_DIST_GICD_ITARGETSR39_FLD_MSB 31
17846 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR39_FLD register field. */
17847 #define ALT_GIC_DIST_GICD_ITARGETSR39_FLD_WIDTH 32
17848 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR39_FLD register field value. */
17849 #define ALT_GIC_DIST_GICD_ITARGETSR39_FLD_SET_MSK 0xffffffff
17850 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR39_FLD register field value. */
17851 #define ALT_GIC_DIST_GICD_ITARGETSR39_FLD_CLR_MSK 0x00000000
17852 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR39_FLD register field. */
17853 #define ALT_GIC_DIST_GICD_ITARGETSR39_FLD_RESET 0x0
17854 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR39_FLD field value from a register. */
17855 #define ALT_GIC_DIST_GICD_ITARGETSR39_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17856 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR39_FLD register field value suitable for setting the register. */
17857 #define ALT_GIC_DIST_GICD_ITARGETSR39_FLD_SET(value) (((value) << 0) & 0xffffffff)
17858 
17859 #ifndef __ASSEMBLY__
17860 /*
17861  * WARNING: The C register and register group struct declarations are provided for
17862  * convenience and illustrative purposes. They should, however, be used with
17863  * caution as the C language standard provides no guarantees about the alignment or
17864  * atomicity of device memory accesses. The recommended practice for coding device
17865  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17866  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17867  * alt_write_dword() functions for 64 bit registers.
17868  *
17869  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR39.
17870  */
17871 struct ALT_GIC_DIST_GICD_ITARGETSR39_s
17872 {
17873  volatile uint32_t fld : 32; /* Empty */
17874 };
17875 
17876 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR39. */
17877 typedef struct ALT_GIC_DIST_GICD_ITARGETSR39_s ALT_GIC_DIST_GICD_ITARGETSR39_t;
17878 #endif /* __ASSEMBLY__ */
17879 
17880 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR39 register. */
17881 #define ALT_GIC_DIST_GICD_ITARGETSR39_RESET 0x00000000
17882 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR39 register from the beginning of the component. */
17883 #define ALT_GIC_DIST_GICD_ITARGETSR39_OFST 0x89c
17884 
17885 /*
17886  * Register : GICD_ITARGETSR40
17887  *
17888  * Interrupt Processor Targets Registers
17889  *
17890  * Register Layout
17891  *
17892  * Bits | Access | Reset | Description
17893  * :-------|:-------|:------|:------------
17894  * [31:0] | RW | 0x0 | Empty
17895  *
17896  */
17897 /*
17898  * Field : Empty - fld
17899  *
17900  * Placeholder
17901  *
17902  * Field Access Macros:
17903  *
17904  */
17905 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR40_FLD register field. */
17906 #define ALT_GIC_DIST_GICD_ITARGETSR40_FLD_LSB 0
17907 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR40_FLD register field. */
17908 #define ALT_GIC_DIST_GICD_ITARGETSR40_FLD_MSB 31
17909 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR40_FLD register field. */
17910 #define ALT_GIC_DIST_GICD_ITARGETSR40_FLD_WIDTH 32
17911 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR40_FLD register field value. */
17912 #define ALT_GIC_DIST_GICD_ITARGETSR40_FLD_SET_MSK 0xffffffff
17913 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR40_FLD register field value. */
17914 #define ALT_GIC_DIST_GICD_ITARGETSR40_FLD_CLR_MSK 0x00000000
17915 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR40_FLD register field. */
17916 #define ALT_GIC_DIST_GICD_ITARGETSR40_FLD_RESET 0x0
17917 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR40_FLD field value from a register. */
17918 #define ALT_GIC_DIST_GICD_ITARGETSR40_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17919 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR40_FLD register field value suitable for setting the register. */
17920 #define ALT_GIC_DIST_GICD_ITARGETSR40_FLD_SET(value) (((value) << 0) & 0xffffffff)
17921 
17922 #ifndef __ASSEMBLY__
17923 /*
17924  * WARNING: The C register and register group struct declarations are provided for
17925  * convenience and illustrative purposes. They should, however, be used with
17926  * caution as the C language standard provides no guarantees about the alignment or
17927  * atomicity of device memory accesses. The recommended practice for coding device
17928  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17929  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17930  * alt_write_dword() functions for 64 bit registers.
17931  *
17932  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR40.
17933  */
17934 struct ALT_GIC_DIST_GICD_ITARGETSR40_s
17935 {
17936  volatile uint32_t fld : 32; /* Empty */
17937 };
17938 
17939 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR40. */
17940 typedef struct ALT_GIC_DIST_GICD_ITARGETSR40_s ALT_GIC_DIST_GICD_ITARGETSR40_t;
17941 #endif /* __ASSEMBLY__ */
17942 
17943 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR40 register. */
17944 #define ALT_GIC_DIST_GICD_ITARGETSR40_RESET 0x00000000
17945 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR40 register from the beginning of the component. */
17946 #define ALT_GIC_DIST_GICD_ITARGETSR40_OFST 0x8a0
17947 
17948 /*
17949  * Register : GICD_ITARGETSR41
17950  *
17951  * Interrupt Processor Targets Registers
17952  *
17953  * Register Layout
17954  *
17955  * Bits | Access | Reset | Description
17956  * :-------|:-------|:------|:------------
17957  * [31:0] | RW | 0x0 | Empty
17958  *
17959  */
17960 /*
17961  * Field : Empty - fld
17962  *
17963  * Placeholder
17964  *
17965  * Field Access Macros:
17966  *
17967  */
17968 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR41_FLD register field. */
17969 #define ALT_GIC_DIST_GICD_ITARGETSR41_FLD_LSB 0
17970 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR41_FLD register field. */
17971 #define ALT_GIC_DIST_GICD_ITARGETSR41_FLD_MSB 31
17972 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR41_FLD register field. */
17973 #define ALT_GIC_DIST_GICD_ITARGETSR41_FLD_WIDTH 32
17974 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR41_FLD register field value. */
17975 #define ALT_GIC_DIST_GICD_ITARGETSR41_FLD_SET_MSK 0xffffffff
17976 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR41_FLD register field value. */
17977 #define ALT_GIC_DIST_GICD_ITARGETSR41_FLD_CLR_MSK 0x00000000
17978 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR41_FLD register field. */
17979 #define ALT_GIC_DIST_GICD_ITARGETSR41_FLD_RESET 0x0
17980 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR41_FLD field value from a register. */
17981 #define ALT_GIC_DIST_GICD_ITARGETSR41_FLD_GET(value) (((value) & 0xffffffff) >> 0)
17982 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR41_FLD register field value suitable for setting the register. */
17983 #define ALT_GIC_DIST_GICD_ITARGETSR41_FLD_SET(value) (((value) << 0) & 0xffffffff)
17984 
17985 #ifndef __ASSEMBLY__
17986 /*
17987  * WARNING: The C register and register group struct declarations are provided for
17988  * convenience and illustrative purposes. They should, however, be used with
17989  * caution as the C language standard provides no guarantees about the alignment or
17990  * atomicity of device memory accesses. The recommended practice for coding device
17991  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17992  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17993  * alt_write_dword() functions for 64 bit registers.
17994  *
17995  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR41.
17996  */
17997 struct ALT_GIC_DIST_GICD_ITARGETSR41_s
17998 {
17999  volatile uint32_t fld : 32; /* Empty */
18000 };
18001 
18002 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR41. */
18003 typedef struct ALT_GIC_DIST_GICD_ITARGETSR41_s ALT_GIC_DIST_GICD_ITARGETSR41_t;
18004 #endif /* __ASSEMBLY__ */
18005 
18006 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR41 register. */
18007 #define ALT_GIC_DIST_GICD_ITARGETSR41_RESET 0x00000000
18008 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR41 register from the beginning of the component. */
18009 #define ALT_GIC_DIST_GICD_ITARGETSR41_OFST 0x8a4
18010 
18011 /*
18012  * Register : GICD_ITARGETSR42
18013  *
18014  * Interrupt Processor Targets Registers
18015  *
18016  * Register Layout
18017  *
18018  * Bits | Access | Reset | Description
18019  * :-------|:-------|:------|:------------
18020  * [31:0] | RW | 0x0 | Empty
18021  *
18022  */
18023 /*
18024  * Field : Empty - fld
18025  *
18026  * Placeholder
18027  *
18028  * Field Access Macros:
18029  *
18030  */
18031 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR42_FLD register field. */
18032 #define ALT_GIC_DIST_GICD_ITARGETSR42_FLD_LSB 0
18033 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR42_FLD register field. */
18034 #define ALT_GIC_DIST_GICD_ITARGETSR42_FLD_MSB 31
18035 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR42_FLD register field. */
18036 #define ALT_GIC_DIST_GICD_ITARGETSR42_FLD_WIDTH 32
18037 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR42_FLD register field value. */
18038 #define ALT_GIC_DIST_GICD_ITARGETSR42_FLD_SET_MSK 0xffffffff
18039 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR42_FLD register field value. */
18040 #define ALT_GIC_DIST_GICD_ITARGETSR42_FLD_CLR_MSK 0x00000000
18041 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR42_FLD register field. */
18042 #define ALT_GIC_DIST_GICD_ITARGETSR42_FLD_RESET 0x0
18043 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR42_FLD field value from a register. */
18044 #define ALT_GIC_DIST_GICD_ITARGETSR42_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18045 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR42_FLD register field value suitable for setting the register. */
18046 #define ALT_GIC_DIST_GICD_ITARGETSR42_FLD_SET(value) (((value) << 0) & 0xffffffff)
18047 
18048 #ifndef __ASSEMBLY__
18049 /*
18050  * WARNING: The C register and register group struct declarations are provided for
18051  * convenience and illustrative purposes. They should, however, be used with
18052  * caution as the C language standard provides no guarantees about the alignment or
18053  * atomicity of device memory accesses. The recommended practice for coding device
18054  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18055  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18056  * alt_write_dword() functions for 64 bit registers.
18057  *
18058  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR42.
18059  */
18060 struct ALT_GIC_DIST_GICD_ITARGETSR42_s
18061 {
18062  volatile uint32_t fld : 32; /* Empty */
18063 };
18064 
18065 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR42. */
18066 typedef struct ALT_GIC_DIST_GICD_ITARGETSR42_s ALT_GIC_DIST_GICD_ITARGETSR42_t;
18067 #endif /* __ASSEMBLY__ */
18068 
18069 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR42 register. */
18070 #define ALT_GIC_DIST_GICD_ITARGETSR42_RESET 0x00000000
18071 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR42 register from the beginning of the component. */
18072 #define ALT_GIC_DIST_GICD_ITARGETSR42_OFST 0x8a8
18073 
18074 /*
18075  * Register : GICD_ITARGETSR43
18076  *
18077  * Interrupt Processor Targets Registers
18078  *
18079  * Register Layout
18080  *
18081  * Bits | Access | Reset | Description
18082  * :-------|:-------|:------|:------------
18083  * [31:0] | RW | 0x0 | Empty
18084  *
18085  */
18086 /*
18087  * Field : Empty - fld
18088  *
18089  * Placeholder
18090  *
18091  * Field Access Macros:
18092  *
18093  */
18094 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR43_FLD register field. */
18095 #define ALT_GIC_DIST_GICD_ITARGETSR43_FLD_LSB 0
18096 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR43_FLD register field. */
18097 #define ALT_GIC_DIST_GICD_ITARGETSR43_FLD_MSB 31
18098 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR43_FLD register field. */
18099 #define ALT_GIC_DIST_GICD_ITARGETSR43_FLD_WIDTH 32
18100 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR43_FLD register field value. */
18101 #define ALT_GIC_DIST_GICD_ITARGETSR43_FLD_SET_MSK 0xffffffff
18102 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR43_FLD register field value. */
18103 #define ALT_GIC_DIST_GICD_ITARGETSR43_FLD_CLR_MSK 0x00000000
18104 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR43_FLD register field. */
18105 #define ALT_GIC_DIST_GICD_ITARGETSR43_FLD_RESET 0x0
18106 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR43_FLD field value from a register. */
18107 #define ALT_GIC_DIST_GICD_ITARGETSR43_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18108 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR43_FLD register field value suitable for setting the register. */
18109 #define ALT_GIC_DIST_GICD_ITARGETSR43_FLD_SET(value) (((value) << 0) & 0xffffffff)
18110 
18111 #ifndef __ASSEMBLY__
18112 /*
18113  * WARNING: The C register and register group struct declarations are provided for
18114  * convenience and illustrative purposes. They should, however, be used with
18115  * caution as the C language standard provides no guarantees about the alignment or
18116  * atomicity of device memory accesses. The recommended practice for coding device
18117  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18118  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18119  * alt_write_dword() functions for 64 bit registers.
18120  *
18121  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR43.
18122  */
18123 struct ALT_GIC_DIST_GICD_ITARGETSR43_s
18124 {
18125  volatile uint32_t fld : 32; /* Empty */
18126 };
18127 
18128 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR43. */
18129 typedef struct ALT_GIC_DIST_GICD_ITARGETSR43_s ALT_GIC_DIST_GICD_ITARGETSR43_t;
18130 #endif /* __ASSEMBLY__ */
18131 
18132 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR43 register. */
18133 #define ALT_GIC_DIST_GICD_ITARGETSR43_RESET 0x00000000
18134 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR43 register from the beginning of the component. */
18135 #define ALT_GIC_DIST_GICD_ITARGETSR43_OFST 0x8ac
18136 
18137 /*
18138  * Register : GICD_ITARGETSR44
18139  *
18140  * Interrupt Processor Targets Registers
18141  *
18142  * Register Layout
18143  *
18144  * Bits | Access | Reset | Description
18145  * :-------|:-------|:------|:------------
18146  * [31:0] | RW | 0x0 | Empty
18147  *
18148  */
18149 /*
18150  * Field : Empty - fld
18151  *
18152  * Placeholder
18153  *
18154  * Field Access Macros:
18155  *
18156  */
18157 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR44_FLD register field. */
18158 #define ALT_GIC_DIST_GICD_ITARGETSR44_FLD_LSB 0
18159 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR44_FLD register field. */
18160 #define ALT_GIC_DIST_GICD_ITARGETSR44_FLD_MSB 31
18161 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR44_FLD register field. */
18162 #define ALT_GIC_DIST_GICD_ITARGETSR44_FLD_WIDTH 32
18163 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR44_FLD register field value. */
18164 #define ALT_GIC_DIST_GICD_ITARGETSR44_FLD_SET_MSK 0xffffffff
18165 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR44_FLD register field value. */
18166 #define ALT_GIC_DIST_GICD_ITARGETSR44_FLD_CLR_MSK 0x00000000
18167 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR44_FLD register field. */
18168 #define ALT_GIC_DIST_GICD_ITARGETSR44_FLD_RESET 0x0
18169 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR44_FLD field value from a register. */
18170 #define ALT_GIC_DIST_GICD_ITARGETSR44_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18171 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR44_FLD register field value suitable for setting the register. */
18172 #define ALT_GIC_DIST_GICD_ITARGETSR44_FLD_SET(value) (((value) << 0) & 0xffffffff)
18173 
18174 #ifndef __ASSEMBLY__
18175 /*
18176  * WARNING: The C register and register group struct declarations are provided for
18177  * convenience and illustrative purposes. They should, however, be used with
18178  * caution as the C language standard provides no guarantees about the alignment or
18179  * atomicity of device memory accesses. The recommended practice for coding device
18180  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18181  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18182  * alt_write_dword() functions for 64 bit registers.
18183  *
18184  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR44.
18185  */
18186 struct ALT_GIC_DIST_GICD_ITARGETSR44_s
18187 {
18188  volatile uint32_t fld : 32; /* Empty */
18189 };
18190 
18191 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR44. */
18192 typedef struct ALT_GIC_DIST_GICD_ITARGETSR44_s ALT_GIC_DIST_GICD_ITARGETSR44_t;
18193 #endif /* __ASSEMBLY__ */
18194 
18195 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR44 register. */
18196 #define ALT_GIC_DIST_GICD_ITARGETSR44_RESET 0x00000000
18197 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR44 register from the beginning of the component. */
18198 #define ALT_GIC_DIST_GICD_ITARGETSR44_OFST 0x8b0
18199 
18200 /*
18201  * Register : GICD_ITARGETSR45
18202  *
18203  * Interrupt Processor Targets Registers
18204  *
18205  * Register Layout
18206  *
18207  * Bits | Access | Reset | Description
18208  * :-------|:-------|:------|:------------
18209  * [31:0] | RW | 0x0 | Empty
18210  *
18211  */
18212 /*
18213  * Field : Empty - fld
18214  *
18215  * Placeholder
18216  *
18217  * Field Access Macros:
18218  *
18219  */
18220 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR45_FLD register field. */
18221 #define ALT_GIC_DIST_GICD_ITARGETSR45_FLD_LSB 0
18222 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR45_FLD register field. */
18223 #define ALT_GIC_DIST_GICD_ITARGETSR45_FLD_MSB 31
18224 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR45_FLD register field. */
18225 #define ALT_GIC_DIST_GICD_ITARGETSR45_FLD_WIDTH 32
18226 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR45_FLD register field value. */
18227 #define ALT_GIC_DIST_GICD_ITARGETSR45_FLD_SET_MSK 0xffffffff
18228 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR45_FLD register field value. */
18229 #define ALT_GIC_DIST_GICD_ITARGETSR45_FLD_CLR_MSK 0x00000000
18230 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR45_FLD register field. */
18231 #define ALT_GIC_DIST_GICD_ITARGETSR45_FLD_RESET 0x0
18232 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR45_FLD field value from a register. */
18233 #define ALT_GIC_DIST_GICD_ITARGETSR45_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18234 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR45_FLD register field value suitable for setting the register. */
18235 #define ALT_GIC_DIST_GICD_ITARGETSR45_FLD_SET(value) (((value) << 0) & 0xffffffff)
18236 
18237 #ifndef __ASSEMBLY__
18238 /*
18239  * WARNING: The C register and register group struct declarations are provided for
18240  * convenience and illustrative purposes. They should, however, be used with
18241  * caution as the C language standard provides no guarantees about the alignment or
18242  * atomicity of device memory accesses. The recommended practice for coding device
18243  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18244  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18245  * alt_write_dword() functions for 64 bit registers.
18246  *
18247  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR45.
18248  */
18249 struct ALT_GIC_DIST_GICD_ITARGETSR45_s
18250 {
18251  volatile uint32_t fld : 32; /* Empty */
18252 };
18253 
18254 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR45. */
18255 typedef struct ALT_GIC_DIST_GICD_ITARGETSR45_s ALT_GIC_DIST_GICD_ITARGETSR45_t;
18256 #endif /* __ASSEMBLY__ */
18257 
18258 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR45 register. */
18259 #define ALT_GIC_DIST_GICD_ITARGETSR45_RESET 0x00000000
18260 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR45 register from the beginning of the component. */
18261 #define ALT_GIC_DIST_GICD_ITARGETSR45_OFST 0x8b4
18262 
18263 /*
18264  * Register : GICD_ITARGETSR46
18265  *
18266  * Interrupt Processor Targets Registers
18267  *
18268  * Register Layout
18269  *
18270  * Bits | Access | Reset | Description
18271  * :-------|:-------|:------|:------------
18272  * [31:0] | RW | 0x0 | Empty
18273  *
18274  */
18275 /*
18276  * Field : Empty - fld
18277  *
18278  * Placeholder
18279  *
18280  * Field Access Macros:
18281  *
18282  */
18283 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR46_FLD register field. */
18284 #define ALT_GIC_DIST_GICD_ITARGETSR46_FLD_LSB 0
18285 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR46_FLD register field. */
18286 #define ALT_GIC_DIST_GICD_ITARGETSR46_FLD_MSB 31
18287 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR46_FLD register field. */
18288 #define ALT_GIC_DIST_GICD_ITARGETSR46_FLD_WIDTH 32
18289 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR46_FLD register field value. */
18290 #define ALT_GIC_DIST_GICD_ITARGETSR46_FLD_SET_MSK 0xffffffff
18291 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR46_FLD register field value. */
18292 #define ALT_GIC_DIST_GICD_ITARGETSR46_FLD_CLR_MSK 0x00000000
18293 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR46_FLD register field. */
18294 #define ALT_GIC_DIST_GICD_ITARGETSR46_FLD_RESET 0x0
18295 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR46_FLD field value from a register. */
18296 #define ALT_GIC_DIST_GICD_ITARGETSR46_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18297 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR46_FLD register field value suitable for setting the register. */
18298 #define ALT_GIC_DIST_GICD_ITARGETSR46_FLD_SET(value) (((value) << 0) & 0xffffffff)
18299 
18300 #ifndef __ASSEMBLY__
18301 /*
18302  * WARNING: The C register and register group struct declarations are provided for
18303  * convenience and illustrative purposes. They should, however, be used with
18304  * caution as the C language standard provides no guarantees about the alignment or
18305  * atomicity of device memory accesses. The recommended practice for coding device
18306  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18307  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18308  * alt_write_dword() functions for 64 bit registers.
18309  *
18310  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR46.
18311  */
18312 struct ALT_GIC_DIST_GICD_ITARGETSR46_s
18313 {
18314  volatile uint32_t fld : 32; /* Empty */
18315 };
18316 
18317 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR46. */
18318 typedef struct ALT_GIC_DIST_GICD_ITARGETSR46_s ALT_GIC_DIST_GICD_ITARGETSR46_t;
18319 #endif /* __ASSEMBLY__ */
18320 
18321 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR46 register. */
18322 #define ALT_GIC_DIST_GICD_ITARGETSR46_RESET 0x00000000
18323 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR46 register from the beginning of the component. */
18324 #define ALT_GIC_DIST_GICD_ITARGETSR46_OFST 0x8b8
18325 
18326 /*
18327  * Register : GICD_ITARGETSR47
18328  *
18329  * Interrupt Processor Targets Registers
18330  *
18331  * Register Layout
18332  *
18333  * Bits | Access | Reset | Description
18334  * :-------|:-------|:------|:------------
18335  * [31:0] | RW | 0x0 | Empty
18336  *
18337  */
18338 /*
18339  * Field : Empty - fld
18340  *
18341  * Placeholder
18342  *
18343  * Field Access Macros:
18344  *
18345  */
18346 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR47_FLD register field. */
18347 #define ALT_GIC_DIST_GICD_ITARGETSR47_FLD_LSB 0
18348 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR47_FLD register field. */
18349 #define ALT_GIC_DIST_GICD_ITARGETSR47_FLD_MSB 31
18350 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR47_FLD register field. */
18351 #define ALT_GIC_DIST_GICD_ITARGETSR47_FLD_WIDTH 32
18352 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR47_FLD register field value. */
18353 #define ALT_GIC_DIST_GICD_ITARGETSR47_FLD_SET_MSK 0xffffffff
18354 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR47_FLD register field value. */
18355 #define ALT_GIC_DIST_GICD_ITARGETSR47_FLD_CLR_MSK 0x00000000
18356 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR47_FLD register field. */
18357 #define ALT_GIC_DIST_GICD_ITARGETSR47_FLD_RESET 0x0
18358 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR47_FLD field value from a register. */
18359 #define ALT_GIC_DIST_GICD_ITARGETSR47_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18360 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR47_FLD register field value suitable for setting the register. */
18361 #define ALT_GIC_DIST_GICD_ITARGETSR47_FLD_SET(value) (((value) << 0) & 0xffffffff)
18362 
18363 #ifndef __ASSEMBLY__
18364 /*
18365  * WARNING: The C register and register group struct declarations are provided for
18366  * convenience and illustrative purposes. They should, however, be used with
18367  * caution as the C language standard provides no guarantees about the alignment or
18368  * atomicity of device memory accesses. The recommended practice for coding device
18369  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18370  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18371  * alt_write_dword() functions for 64 bit registers.
18372  *
18373  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR47.
18374  */
18375 struct ALT_GIC_DIST_GICD_ITARGETSR47_s
18376 {
18377  volatile uint32_t fld : 32; /* Empty */
18378 };
18379 
18380 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR47. */
18381 typedef struct ALT_GIC_DIST_GICD_ITARGETSR47_s ALT_GIC_DIST_GICD_ITARGETSR47_t;
18382 #endif /* __ASSEMBLY__ */
18383 
18384 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR47 register. */
18385 #define ALT_GIC_DIST_GICD_ITARGETSR47_RESET 0x00000000
18386 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR47 register from the beginning of the component. */
18387 #define ALT_GIC_DIST_GICD_ITARGETSR47_OFST 0x8bc
18388 
18389 /*
18390  * Register : GICD_ITARGETSR48
18391  *
18392  * Interrupt Processor Targets Registers
18393  *
18394  * Register Layout
18395  *
18396  * Bits | Access | Reset | Description
18397  * :-------|:-------|:------|:------------
18398  * [31:0] | RW | 0x0 | Empty
18399  *
18400  */
18401 /*
18402  * Field : Empty - fld
18403  *
18404  * Placeholder
18405  *
18406  * Field Access Macros:
18407  *
18408  */
18409 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR48_FLD register field. */
18410 #define ALT_GIC_DIST_GICD_ITARGETSR48_FLD_LSB 0
18411 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR48_FLD register field. */
18412 #define ALT_GIC_DIST_GICD_ITARGETSR48_FLD_MSB 31
18413 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR48_FLD register field. */
18414 #define ALT_GIC_DIST_GICD_ITARGETSR48_FLD_WIDTH 32
18415 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR48_FLD register field value. */
18416 #define ALT_GIC_DIST_GICD_ITARGETSR48_FLD_SET_MSK 0xffffffff
18417 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR48_FLD register field value. */
18418 #define ALT_GIC_DIST_GICD_ITARGETSR48_FLD_CLR_MSK 0x00000000
18419 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR48_FLD register field. */
18420 #define ALT_GIC_DIST_GICD_ITARGETSR48_FLD_RESET 0x0
18421 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR48_FLD field value from a register. */
18422 #define ALT_GIC_DIST_GICD_ITARGETSR48_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18423 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR48_FLD register field value suitable for setting the register. */
18424 #define ALT_GIC_DIST_GICD_ITARGETSR48_FLD_SET(value) (((value) << 0) & 0xffffffff)
18425 
18426 #ifndef __ASSEMBLY__
18427 /*
18428  * WARNING: The C register and register group struct declarations are provided for
18429  * convenience and illustrative purposes. They should, however, be used with
18430  * caution as the C language standard provides no guarantees about the alignment or
18431  * atomicity of device memory accesses. The recommended practice for coding device
18432  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18433  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18434  * alt_write_dword() functions for 64 bit registers.
18435  *
18436  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR48.
18437  */
18438 struct ALT_GIC_DIST_GICD_ITARGETSR48_s
18439 {
18440  volatile uint32_t fld : 32; /* Empty */
18441 };
18442 
18443 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR48. */
18444 typedef struct ALT_GIC_DIST_GICD_ITARGETSR48_s ALT_GIC_DIST_GICD_ITARGETSR48_t;
18445 #endif /* __ASSEMBLY__ */
18446 
18447 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR48 register. */
18448 #define ALT_GIC_DIST_GICD_ITARGETSR48_RESET 0x00000000
18449 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR48 register from the beginning of the component. */
18450 #define ALT_GIC_DIST_GICD_ITARGETSR48_OFST 0x8c0
18451 
18452 /*
18453  * Register : GICD_ITARGETSR49
18454  *
18455  * Interrupt Processor Targets Registers
18456  *
18457  * Register Layout
18458  *
18459  * Bits | Access | Reset | Description
18460  * :-------|:-------|:------|:------------
18461  * [31:0] | RW | 0x0 | Empty
18462  *
18463  */
18464 /*
18465  * Field : Empty - fld
18466  *
18467  * Placeholder
18468  *
18469  * Field Access Macros:
18470  *
18471  */
18472 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR49_FLD register field. */
18473 #define ALT_GIC_DIST_GICD_ITARGETSR49_FLD_LSB 0
18474 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR49_FLD register field. */
18475 #define ALT_GIC_DIST_GICD_ITARGETSR49_FLD_MSB 31
18476 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR49_FLD register field. */
18477 #define ALT_GIC_DIST_GICD_ITARGETSR49_FLD_WIDTH 32
18478 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR49_FLD register field value. */
18479 #define ALT_GIC_DIST_GICD_ITARGETSR49_FLD_SET_MSK 0xffffffff
18480 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR49_FLD register field value. */
18481 #define ALT_GIC_DIST_GICD_ITARGETSR49_FLD_CLR_MSK 0x00000000
18482 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR49_FLD register field. */
18483 #define ALT_GIC_DIST_GICD_ITARGETSR49_FLD_RESET 0x0
18484 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR49_FLD field value from a register. */
18485 #define ALT_GIC_DIST_GICD_ITARGETSR49_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18486 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR49_FLD register field value suitable for setting the register. */
18487 #define ALT_GIC_DIST_GICD_ITARGETSR49_FLD_SET(value) (((value) << 0) & 0xffffffff)
18488 
18489 #ifndef __ASSEMBLY__
18490 /*
18491  * WARNING: The C register and register group struct declarations are provided for
18492  * convenience and illustrative purposes. They should, however, be used with
18493  * caution as the C language standard provides no guarantees about the alignment or
18494  * atomicity of device memory accesses. The recommended practice for coding device
18495  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18496  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18497  * alt_write_dword() functions for 64 bit registers.
18498  *
18499  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR49.
18500  */
18501 struct ALT_GIC_DIST_GICD_ITARGETSR49_s
18502 {
18503  volatile uint32_t fld : 32; /* Empty */
18504 };
18505 
18506 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR49. */
18507 typedef struct ALT_GIC_DIST_GICD_ITARGETSR49_s ALT_GIC_DIST_GICD_ITARGETSR49_t;
18508 #endif /* __ASSEMBLY__ */
18509 
18510 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR49 register. */
18511 #define ALT_GIC_DIST_GICD_ITARGETSR49_RESET 0x00000000
18512 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR49 register from the beginning of the component. */
18513 #define ALT_GIC_DIST_GICD_ITARGETSR49_OFST 0x8c4
18514 
18515 /*
18516  * Register : GICD_ITARGETSR50
18517  *
18518  * Interrupt Processor Targets Registers
18519  *
18520  * Register Layout
18521  *
18522  * Bits | Access | Reset | Description
18523  * :-------|:-------|:------|:------------
18524  * [31:0] | RW | 0x0 | Empty
18525  *
18526  */
18527 /*
18528  * Field : Empty - fld
18529  *
18530  * Placeholder
18531  *
18532  * Field Access Macros:
18533  *
18534  */
18535 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR50_FLD register field. */
18536 #define ALT_GIC_DIST_GICD_ITARGETSR50_FLD_LSB 0
18537 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR50_FLD register field. */
18538 #define ALT_GIC_DIST_GICD_ITARGETSR50_FLD_MSB 31
18539 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR50_FLD register field. */
18540 #define ALT_GIC_DIST_GICD_ITARGETSR50_FLD_WIDTH 32
18541 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR50_FLD register field value. */
18542 #define ALT_GIC_DIST_GICD_ITARGETSR50_FLD_SET_MSK 0xffffffff
18543 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR50_FLD register field value. */
18544 #define ALT_GIC_DIST_GICD_ITARGETSR50_FLD_CLR_MSK 0x00000000
18545 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR50_FLD register field. */
18546 #define ALT_GIC_DIST_GICD_ITARGETSR50_FLD_RESET 0x0
18547 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR50_FLD field value from a register. */
18548 #define ALT_GIC_DIST_GICD_ITARGETSR50_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18549 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR50_FLD register field value suitable for setting the register. */
18550 #define ALT_GIC_DIST_GICD_ITARGETSR50_FLD_SET(value) (((value) << 0) & 0xffffffff)
18551 
18552 #ifndef __ASSEMBLY__
18553 /*
18554  * WARNING: The C register and register group struct declarations are provided for
18555  * convenience and illustrative purposes. They should, however, be used with
18556  * caution as the C language standard provides no guarantees about the alignment or
18557  * atomicity of device memory accesses. The recommended practice for coding device
18558  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18559  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18560  * alt_write_dword() functions for 64 bit registers.
18561  *
18562  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR50.
18563  */
18564 struct ALT_GIC_DIST_GICD_ITARGETSR50_s
18565 {
18566  volatile uint32_t fld : 32; /* Empty */
18567 };
18568 
18569 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR50. */
18570 typedef struct ALT_GIC_DIST_GICD_ITARGETSR50_s ALT_GIC_DIST_GICD_ITARGETSR50_t;
18571 #endif /* __ASSEMBLY__ */
18572 
18573 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR50 register. */
18574 #define ALT_GIC_DIST_GICD_ITARGETSR50_RESET 0x00000000
18575 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR50 register from the beginning of the component. */
18576 #define ALT_GIC_DIST_GICD_ITARGETSR50_OFST 0x8c8
18577 
18578 /*
18579  * Register : GICD_ITARGETSR51
18580  *
18581  * Interrupt Processor Targets Registers
18582  *
18583  * Register Layout
18584  *
18585  * Bits | Access | Reset | Description
18586  * :-------|:-------|:------|:------------
18587  * [31:0] | RW | 0x0 | Empty
18588  *
18589  */
18590 /*
18591  * Field : Empty - fld
18592  *
18593  * Placeholder
18594  *
18595  * Field Access Macros:
18596  *
18597  */
18598 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR51_FLD register field. */
18599 #define ALT_GIC_DIST_GICD_ITARGETSR51_FLD_LSB 0
18600 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR51_FLD register field. */
18601 #define ALT_GIC_DIST_GICD_ITARGETSR51_FLD_MSB 31
18602 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR51_FLD register field. */
18603 #define ALT_GIC_DIST_GICD_ITARGETSR51_FLD_WIDTH 32
18604 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR51_FLD register field value. */
18605 #define ALT_GIC_DIST_GICD_ITARGETSR51_FLD_SET_MSK 0xffffffff
18606 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR51_FLD register field value. */
18607 #define ALT_GIC_DIST_GICD_ITARGETSR51_FLD_CLR_MSK 0x00000000
18608 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR51_FLD register field. */
18609 #define ALT_GIC_DIST_GICD_ITARGETSR51_FLD_RESET 0x0
18610 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR51_FLD field value from a register. */
18611 #define ALT_GIC_DIST_GICD_ITARGETSR51_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18612 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR51_FLD register field value suitable for setting the register. */
18613 #define ALT_GIC_DIST_GICD_ITARGETSR51_FLD_SET(value) (((value) << 0) & 0xffffffff)
18614 
18615 #ifndef __ASSEMBLY__
18616 /*
18617  * WARNING: The C register and register group struct declarations are provided for
18618  * convenience and illustrative purposes. They should, however, be used with
18619  * caution as the C language standard provides no guarantees about the alignment or
18620  * atomicity of device memory accesses. The recommended practice for coding device
18621  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18622  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18623  * alt_write_dword() functions for 64 bit registers.
18624  *
18625  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR51.
18626  */
18627 struct ALT_GIC_DIST_GICD_ITARGETSR51_s
18628 {
18629  volatile uint32_t fld : 32; /* Empty */
18630 };
18631 
18632 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR51. */
18633 typedef struct ALT_GIC_DIST_GICD_ITARGETSR51_s ALT_GIC_DIST_GICD_ITARGETSR51_t;
18634 #endif /* __ASSEMBLY__ */
18635 
18636 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR51 register. */
18637 #define ALT_GIC_DIST_GICD_ITARGETSR51_RESET 0x00000000
18638 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR51 register from the beginning of the component. */
18639 #define ALT_GIC_DIST_GICD_ITARGETSR51_OFST 0x8cc
18640 
18641 /*
18642  * Register : GICD_ITARGETSR52
18643  *
18644  * Interrupt Processor Targets Registers
18645  *
18646  * Register Layout
18647  *
18648  * Bits | Access | Reset | Description
18649  * :-------|:-------|:------|:------------
18650  * [31:0] | RW | 0x0 | Empty
18651  *
18652  */
18653 /*
18654  * Field : Empty - fld
18655  *
18656  * Placeholder
18657  *
18658  * Field Access Macros:
18659  *
18660  */
18661 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR52_FLD register field. */
18662 #define ALT_GIC_DIST_GICD_ITARGETSR52_FLD_LSB 0
18663 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR52_FLD register field. */
18664 #define ALT_GIC_DIST_GICD_ITARGETSR52_FLD_MSB 31
18665 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR52_FLD register field. */
18666 #define ALT_GIC_DIST_GICD_ITARGETSR52_FLD_WIDTH 32
18667 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR52_FLD register field value. */
18668 #define ALT_GIC_DIST_GICD_ITARGETSR52_FLD_SET_MSK 0xffffffff
18669 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR52_FLD register field value. */
18670 #define ALT_GIC_DIST_GICD_ITARGETSR52_FLD_CLR_MSK 0x00000000
18671 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR52_FLD register field. */
18672 #define ALT_GIC_DIST_GICD_ITARGETSR52_FLD_RESET 0x0
18673 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR52_FLD field value from a register. */
18674 #define ALT_GIC_DIST_GICD_ITARGETSR52_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18675 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR52_FLD register field value suitable for setting the register. */
18676 #define ALT_GIC_DIST_GICD_ITARGETSR52_FLD_SET(value) (((value) << 0) & 0xffffffff)
18677 
18678 #ifndef __ASSEMBLY__
18679 /*
18680  * WARNING: The C register and register group struct declarations are provided for
18681  * convenience and illustrative purposes. They should, however, be used with
18682  * caution as the C language standard provides no guarantees about the alignment or
18683  * atomicity of device memory accesses. The recommended practice for coding device
18684  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18685  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18686  * alt_write_dword() functions for 64 bit registers.
18687  *
18688  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR52.
18689  */
18690 struct ALT_GIC_DIST_GICD_ITARGETSR52_s
18691 {
18692  volatile uint32_t fld : 32; /* Empty */
18693 };
18694 
18695 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR52. */
18696 typedef struct ALT_GIC_DIST_GICD_ITARGETSR52_s ALT_GIC_DIST_GICD_ITARGETSR52_t;
18697 #endif /* __ASSEMBLY__ */
18698 
18699 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR52 register. */
18700 #define ALT_GIC_DIST_GICD_ITARGETSR52_RESET 0x00000000
18701 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR52 register from the beginning of the component. */
18702 #define ALT_GIC_DIST_GICD_ITARGETSR52_OFST 0x8d0
18703 
18704 /*
18705  * Register : GICD_ITARGETSR53
18706  *
18707  * Interrupt Processor Targets Registers
18708  *
18709  * Register Layout
18710  *
18711  * Bits | Access | Reset | Description
18712  * :-------|:-------|:------|:------------
18713  * [31:0] | RW | 0x0 | Empty
18714  *
18715  */
18716 /*
18717  * Field : Empty - fld
18718  *
18719  * Placeholder
18720  *
18721  * Field Access Macros:
18722  *
18723  */
18724 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR53_FLD register field. */
18725 #define ALT_GIC_DIST_GICD_ITARGETSR53_FLD_LSB 0
18726 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR53_FLD register field. */
18727 #define ALT_GIC_DIST_GICD_ITARGETSR53_FLD_MSB 31
18728 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR53_FLD register field. */
18729 #define ALT_GIC_DIST_GICD_ITARGETSR53_FLD_WIDTH 32
18730 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR53_FLD register field value. */
18731 #define ALT_GIC_DIST_GICD_ITARGETSR53_FLD_SET_MSK 0xffffffff
18732 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR53_FLD register field value. */
18733 #define ALT_GIC_DIST_GICD_ITARGETSR53_FLD_CLR_MSK 0x00000000
18734 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR53_FLD register field. */
18735 #define ALT_GIC_DIST_GICD_ITARGETSR53_FLD_RESET 0x0
18736 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR53_FLD field value from a register. */
18737 #define ALT_GIC_DIST_GICD_ITARGETSR53_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18738 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR53_FLD register field value suitable for setting the register. */
18739 #define ALT_GIC_DIST_GICD_ITARGETSR53_FLD_SET(value) (((value) << 0) & 0xffffffff)
18740 
18741 #ifndef __ASSEMBLY__
18742 /*
18743  * WARNING: The C register and register group struct declarations are provided for
18744  * convenience and illustrative purposes. They should, however, be used with
18745  * caution as the C language standard provides no guarantees about the alignment or
18746  * atomicity of device memory accesses. The recommended practice for coding device
18747  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18748  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18749  * alt_write_dword() functions for 64 bit registers.
18750  *
18751  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR53.
18752  */
18753 struct ALT_GIC_DIST_GICD_ITARGETSR53_s
18754 {
18755  volatile uint32_t fld : 32; /* Empty */
18756 };
18757 
18758 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR53. */
18759 typedef struct ALT_GIC_DIST_GICD_ITARGETSR53_s ALT_GIC_DIST_GICD_ITARGETSR53_t;
18760 #endif /* __ASSEMBLY__ */
18761 
18762 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR53 register. */
18763 #define ALT_GIC_DIST_GICD_ITARGETSR53_RESET 0x00000000
18764 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR53 register from the beginning of the component. */
18765 #define ALT_GIC_DIST_GICD_ITARGETSR53_OFST 0x8d4
18766 
18767 /*
18768  * Register : GICD_ITARGETSR54
18769  *
18770  * Interrupt Processor Targets Registers
18771  *
18772  * Register Layout
18773  *
18774  * Bits | Access | Reset | Description
18775  * :-------|:-------|:------|:------------
18776  * [31:0] | RW | 0x0 | Empty
18777  *
18778  */
18779 /*
18780  * Field : Empty - fld
18781  *
18782  * Placeholder
18783  *
18784  * Field Access Macros:
18785  *
18786  */
18787 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR54_FLD register field. */
18788 #define ALT_GIC_DIST_GICD_ITARGETSR54_FLD_LSB 0
18789 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR54_FLD register field. */
18790 #define ALT_GIC_DIST_GICD_ITARGETSR54_FLD_MSB 31
18791 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR54_FLD register field. */
18792 #define ALT_GIC_DIST_GICD_ITARGETSR54_FLD_WIDTH 32
18793 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR54_FLD register field value. */
18794 #define ALT_GIC_DIST_GICD_ITARGETSR54_FLD_SET_MSK 0xffffffff
18795 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR54_FLD register field value. */
18796 #define ALT_GIC_DIST_GICD_ITARGETSR54_FLD_CLR_MSK 0x00000000
18797 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR54_FLD register field. */
18798 #define ALT_GIC_DIST_GICD_ITARGETSR54_FLD_RESET 0x0
18799 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR54_FLD field value from a register. */
18800 #define ALT_GIC_DIST_GICD_ITARGETSR54_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18801 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR54_FLD register field value suitable for setting the register. */
18802 #define ALT_GIC_DIST_GICD_ITARGETSR54_FLD_SET(value) (((value) << 0) & 0xffffffff)
18803 
18804 #ifndef __ASSEMBLY__
18805 /*
18806  * WARNING: The C register and register group struct declarations are provided for
18807  * convenience and illustrative purposes. They should, however, be used with
18808  * caution as the C language standard provides no guarantees about the alignment or
18809  * atomicity of device memory accesses. The recommended practice for coding device
18810  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18811  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18812  * alt_write_dword() functions for 64 bit registers.
18813  *
18814  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR54.
18815  */
18816 struct ALT_GIC_DIST_GICD_ITARGETSR54_s
18817 {
18818  volatile uint32_t fld : 32; /* Empty */
18819 };
18820 
18821 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR54. */
18822 typedef struct ALT_GIC_DIST_GICD_ITARGETSR54_s ALT_GIC_DIST_GICD_ITARGETSR54_t;
18823 #endif /* __ASSEMBLY__ */
18824 
18825 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR54 register. */
18826 #define ALT_GIC_DIST_GICD_ITARGETSR54_RESET 0x00000000
18827 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR54 register from the beginning of the component. */
18828 #define ALT_GIC_DIST_GICD_ITARGETSR54_OFST 0x8d8
18829 
18830 /*
18831  * Register : GICD_ITARGETSR55
18832  *
18833  * Interrupt Processor Targets Registers
18834  *
18835  * Register Layout
18836  *
18837  * Bits | Access | Reset | Description
18838  * :-------|:-------|:------|:------------
18839  * [31:0] | RW | 0x0 | Empty
18840  *
18841  */
18842 /*
18843  * Field : Empty - fld
18844  *
18845  * Placeholder
18846  *
18847  * Field Access Macros:
18848  *
18849  */
18850 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR55_FLD register field. */
18851 #define ALT_GIC_DIST_GICD_ITARGETSR55_FLD_LSB 0
18852 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR55_FLD register field. */
18853 #define ALT_GIC_DIST_GICD_ITARGETSR55_FLD_MSB 31
18854 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR55_FLD register field. */
18855 #define ALT_GIC_DIST_GICD_ITARGETSR55_FLD_WIDTH 32
18856 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR55_FLD register field value. */
18857 #define ALT_GIC_DIST_GICD_ITARGETSR55_FLD_SET_MSK 0xffffffff
18858 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR55_FLD register field value. */
18859 #define ALT_GIC_DIST_GICD_ITARGETSR55_FLD_CLR_MSK 0x00000000
18860 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR55_FLD register field. */
18861 #define ALT_GIC_DIST_GICD_ITARGETSR55_FLD_RESET 0x0
18862 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR55_FLD field value from a register. */
18863 #define ALT_GIC_DIST_GICD_ITARGETSR55_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18864 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR55_FLD register field value suitable for setting the register. */
18865 #define ALT_GIC_DIST_GICD_ITARGETSR55_FLD_SET(value) (((value) << 0) & 0xffffffff)
18866 
18867 #ifndef __ASSEMBLY__
18868 /*
18869  * WARNING: The C register and register group struct declarations are provided for
18870  * convenience and illustrative purposes. They should, however, be used with
18871  * caution as the C language standard provides no guarantees about the alignment or
18872  * atomicity of device memory accesses. The recommended practice for coding device
18873  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18874  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18875  * alt_write_dword() functions for 64 bit registers.
18876  *
18877  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR55.
18878  */
18879 struct ALT_GIC_DIST_GICD_ITARGETSR55_s
18880 {
18881  volatile uint32_t fld : 32; /* Empty */
18882 };
18883 
18884 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR55. */
18885 typedef struct ALT_GIC_DIST_GICD_ITARGETSR55_s ALT_GIC_DIST_GICD_ITARGETSR55_t;
18886 #endif /* __ASSEMBLY__ */
18887 
18888 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR55 register. */
18889 #define ALT_GIC_DIST_GICD_ITARGETSR55_RESET 0x00000000
18890 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR55 register from the beginning of the component. */
18891 #define ALT_GIC_DIST_GICD_ITARGETSR55_OFST 0x8dc
18892 
18893 /*
18894  * Register : GICD_ITARGETSR56
18895  *
18896  * Interrupt Processor Targets Registers
18897  *
18898  * Register Layout
18899  *
18900  * Bits | Access | Reset | Description
18901  * :-------|:-------|:------|:------------
18902  * [31:0] | RW | 0x0 | Empty
18903  *
18904  */
18905 /*
18906  * Field : Empty - fld
18907  *
18908  * Placeholder
18909  *
18910  * Field Access Macros:
18911  *
18912  */
18913 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR56_FLD register field. */
18914 #define ALT_GIC_DIST_GICD_ITARGETSR56_FLD_LSB 0
18915 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR56_FLD register field. */
18916 #define ALT_GIC_DIST_GICD_ITARGETSR56_FLD_MSB 31
18917 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR56_FLD register field. */
18918 #define ALT_GIC_DIST_GICD_ITARGETSR56_FLD_WIDTH 32
18919 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR56_FLD register field value. */
18920 #define ALT_GIC_DIST_GICD_ITARGETSR56_FLD_SET_MSK 0xffffffff
18921 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR56_FLD register field value. */
18922 #define ALT_GIC_DIST_GICD_ITARGETSR56_FLD_CLR_MSK 0x00000000
18923 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR56_FLD register field. */
18924 #define ALT_GIC_DIST_GICD_ITARGETSR56_FLD_RESET 0x0
18925 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR56_FLD field value from a register. */
18926 #define ALT_GIC_DIST_GICD_ITARGETSR56_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18927 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR56_FLD register field value suitable for setting the register. */
18928 #define ALT_GIC_DIST_GICD_ITARGETSR56_FLD_SET(value) (((value) << 0) & 0xffffffff)
18929 
18930 #ifndef __ASSEMBLY__
18931 /*
18932  * WARNING: The C register and register group struct declarations are provided for
18933  * convenience and illustrative purposes. They should, however, be used with
18934  * caution as the C language standard provides no guarantees about the alignment or
18935  * atomicity of device memory accesses. The recommended practice for coding device
18936  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
18937  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
18938  * alt_write_dword() functions for 64 bit registers.
18939  *
18940  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR56.
18941  */
18942 struct ALT_GIC_DIST_GICD_ITARGETSR56_s
18943 {
18944  volatile uint32_t fld : 32; /* Empty */
18945 };
18946 
18947 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR56. */
18948 typedef struct ALT_GIC_DIST_GICD_ITARGETSR56_s ALT_GIC_DIST_GICD_ITARGETSR56_t;
18949 #endif /* __ASSEMBLY__ */
18950 
18951 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR56 register. */
18952 #define ALT_GIC_DIST_GICD_ITARGETSR56_RESET 0x00000000
18953 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR56 register from the beginning of the component. */
18954 #define ALT_GIC_DIST_GICD_ITARGETSR56_OFST 0x8e0
18955 
18956 /*
18957  * Register : GICD_ITARGETSR57
18958  *
18959  * Interrupt Processor Targets Registers
18960  *
18961  * Register Layout
18962  *
18963  * Bits | Access | Reset | Description
18964  * :-------|:-------|:------|:------------
18965  * [31:0] | RW | 0x0 | Empty
18966  *
18967  */
18968 /*
18969  * Field : Empty - fld
18970  *
18971  * Placeholder
18972  *
18973  * Field Access Macros:
18974  *
18975  */
18976 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR57_FLD register field. */
18977 #define ALT_GIC_DIST_GICD_ITARGETSR57_FLD_LSB 0
18978 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR57_FLD register field. */
18979 #define ALT_GIC_DIST_GICD_ITARGETSR57_FLD_MSB 31
18980 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR57_FLD register field. */
18981 #define ALT_GIC_DIST_GICD_ITARGETSR57_FLD_WIDTH 32
18982 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR57_FLD register field value. */
18983 #define ALT_GIC_DIST_GICD_ITARGETSR57_FLD_SET_MSK 0xffffffff
18984 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR57_FLD register field value. */
18985 #define ALT_GIC_DIST_GICD_ITARGETSR57_FLD_CLR_MSK 0x00000000
18986 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR57_FLD register field. */
18987 #define ALT_GIC_DIST_GICD_ITARGETSR57_FLD_RESET 0x0
18988 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR57_FLD field value from a register. */
18989 #define ALT_GIC_DIST_GICD_ITARGETSR57_FLD_GET(value) (((value) & 0xffffffff) >> 0)
18990 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR57_FLD register field value suitable for setting the register. */
18991 #define ALT_GIC_DIST_GICD_ITARGETSR57_FLD_SET(value) (((value) << 0) & 0xffffffff)
18992 
18993 #ifndef __ASSEMBLY__
18994 /*
18995  * WARNING: The C register and register group struct declarations are provided for
18996  * convenience and illustrative purposes. They should, however, be used with
18997  * caution as the C language standard provides no guarantees about the alignment or
18998  * atomicity of device memory accesses. The recommended practice for coding device
18999  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
19000  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
19001  * alt_write_dword() functions for 64 bit registers.
19002  *
19003  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR57.
19004  */
19005 struct ALT_GIC_DIST_GICD_ITARGETSR57_s
19006 {
19007  volatile uint32_t fld : 32; /* Empty */
19008 };
19009 
19010 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR57. */
19011 typedef struct ALT_GIC_DIST_GICD_ITARGETSR57_s ALT_GIC_DIST_GICD_ITARGETSR57_t;
19012 #endif /* __ASSEMBLY__ */
19013 
19014 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR57 register. */
19015 #define ALT_GIC_DIST_GICD_ITARGETSR57_RESET 0x00000000
19016 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR57 register from the beginning of the component. */
19017 #define ALT_GIC_DIST_GICD_ITARGETSR57_OFST 0x8e4
19018 
19019 /*
19020  * Register : GICD_ITARGETSR58
19021  *
19022  * Interrupt Processor Targets Registers
19023  *
19024  * Register Layout
19025  *
19026  * Bits | Access | Reset | Description
19027  * :-------|:-------|:------|:------------
19028  * [31:0] | RW | 0x0 | Empty
19029  *
19030  */
19031 /*
19032  * Field : Empty - fld
19033  *
19034  * Placeholder
19035  *
19036  * Field Access Macros:
19037  *
19038  */
19039 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR58_FLD register field. */
19040 #define ALT_GIC_DIST_GICD_ITARGETSR58_FLD_LSB 0
19041 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR58_FLD register field. */
19042 #define ALT_GIC_DIST_GICD_ITARGETSR58_FLD_MSB 31
19043 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR58_FLD register field. */
19044 #define ALT_GIC_DIST_GICD_ITARGETSR58_FLD_WIDTH 32
19045 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR58_FLD register field value. */
19046 #define ALT_GIC_DIST_GICD_ITARGETSR58_FLD_SET_MSK 0xffffffff
19047 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR58_FLD register field value. */
19048 #define ALT_GIC_DIST_GICD_ITARGETSR58_FLD_CLR_MSK 0x00000000
19049 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR58_FLD register field. */
19050 #define ALT_GIC_DIST_GICD_ITARGETSR58_FLD_RESET 0x0
19051 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR58_FLD field value from a register. */
19052 #define ALT_GIC_DIST_GICD_ITARGETSR58_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19053 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR58_FLD register field value suitable for setting the register. */
19054 #define ALT_GIC_DIST_GICD_ITARGETSR58_FLD_SET(value) (((value) << 0) & 0xffffffff)
19055 
19056 #ifndef __ASSEMBLY__
19057 /*
19058  * WARNING: The C register and register group struct declarations are provided for
19059  * convenience and illustrative purposes. They should, however, be used with
19060  * caution as the C language standard provides no guarantees about the alignment or
19061  * atomicity of device memory accesses. The recommended practice for coding device
19062  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
19063  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
19064  * alt_write_dword() functions for 64 bit registers.
19065  *
19066  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR58.
19067  */
19068 struct ALT_GIC_DIST_GICD_ITARGETSR58_s
19069 {
19070  volatile uint32_t fld : 32; /* Empty */
19071 };
19072 
19073 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR58. */
19074 typedef struct ALT_GIC_DIST_GICD_ITARGETSR58_s ALT_GIC_DIST_GICD_ITARGETSR58_t;
19075 #endif /* __ASSEMBLY__ */
19076 
19077 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR58 register. */
19078 #define ALT_GIC_DIST_GICD_ITARGETSR58_RESET 0x00000000
19079 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR58 register from the beginning of the component. */
19080 #define ALT_GIC_DIST_GICD_ITARGETSR58_OFST 0x8e8
19081 
19082 /*
19083  * Register : GICD_ITARGETSR59
19084  *
19085  * Interrupt Processor Targets Registers
19086  *
19087  * Register Layout
19088  *
19089  * Bits | Access | Reset | Description
19090  * :-------|:-------|:------|:------------
19091  * [31:0] | RW | 0x0 | Empty
19092  *
19093  */
19094 /*
19095  * Field : Empty - fld
19096  *
19097  * Placeholder
19098  *
19099  * Field Access Macros:
19100  *
19101  */
19102 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR59_FLD register field. */
19103 #define ALT_GIC_DIST_GICD_ITARGETSR59_FLD_LSB 0
19104 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR59_FLD register field. */
19105 #define ALT_GIC_DIST_GICD_ITARGETSR59_FLD_MSB 31
19106 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR59_FLD register field. */
19107 #define ALT_GIC_DIST_GICD_ITARGETSR59_FLD_WIDTH 32
19108 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR59_FLD register field value. */
19109 #define ALT_GIC_DIST_GICD_ITARGETSR59_FLD_SET_MSK 0xffffffff
19110 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR59_FLD register field value. */
19111 #define ALT_GIC_DIST_GICD_ITARGETSR59_FLD_CLR_MSK 0x00000000
19112 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR59_FLD register field. */
19113 #define ALT_GIC_DIST_GICD_ITARGETSR59_FLD_RESET 0x0
19114 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR59_FLD field value from a register. */
19115 #define ALT_GIC_DIST_GICD_ITARGETSR59_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19116 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR59_FLD register field value suitable for setting the register. */
19117 #define ALT_GIC_DIST_GICD_ITARGETSR59_FLD_SET(value) (((value) << 0) & 0xffffffff)
19118 
19119 #ifndef __ASSEMBLY__
19120 /*
19121  * WARNING: The C register and register group struct declarations are provided for
19122  * convenience and illustrative purposes. They should, however, be used with
19123  * caution as the C language standard provides no guarantees about the alignment or
19124  * atomicity of device memory accesses. The recommended practice for coding device
19125  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
19126  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
19127  * alt_write_dword() functions for 64 bit registers.
19128  *
19129  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR59.
19130  */
19131 struct ALT_GIC_DIST_GICD_ITARGETSR59_s
19132 {
19133  volatile uint32_t fld : 32; /* Empty */
19134 };
19135 
19136 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR59. */
19137 typedef struct ALT_GIC_DIST_GICD_ITARGETSR59_s ALT_GIC_DIST_GICD_ITARGETSR59_t;
19138 #endif /* __ASSEMBLY__ */
19139 
19140 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR59 register. */
19141 #define ALT_GIC_DIST_GICD_ITARGETSR59_RESET 0x00000000
19142 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR59 register from the beginning of the component. */
19143 #define ALT_GIC_DIST_GICD_ITARGETSR59_OFST 0x8ec
19144 
19145 /*
19146  * Register : GICD_ITARGETSR60
19147  *
19148  * Interrupt Processor Targets Registers
19149  *
19150  * Register Layout
19151  *
19152  * Bits | Access | Reset | Description
19153  * :-------|:-------|:------|:------------
19154  * [31:0] | RW | 0x0 | Empty
19155  *
19156  */
19157 /*
19158  * Field : Empty - fld
19159  *
19160  * Placeholder
19161  *
19162  * Field Access Macros:
19163  *
19164  */
19165 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR60_FLD register field. */
19166 #define ALT_GIC_DIST_GICD_ITARGETSR60_FLD_LSB 0
19167 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR60_FLD register field. */
19168 #define ALT_GIC_DIST_GICD_ITARGETSR60_FLD_MSB 31
19169 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR60_FLD register field. */
19170 #define ALT_GIC_DIST_GICD_ITARGETSR60_FLD_WIDTH 32
19171 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR60_FLD register field value. */
19172 #define ALT_GIC_DIST_GICD_ITARGETSR60_FLD_SET_MSK 0xffffffff
19173 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR60_FLD register field value. */
19174 #define ALT_GIC_DIST_GICD_ITARGETSR60_FLD_CLR_MSK 0x00000000
19175 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR60_FLD register field. */
19176 #define ALT_GIC_DIST_GICD_ITARGETSR60_FLD_RESET 0x0
19177 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR60_FLD field value from a register. */
19178 #define ALT_GIC_DIST_GICD_ITARGETSR60_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19179 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR60_FLD register field value suitable for setting the register. */
19180 #define ALT_GIC_DIST_GICD_ITARGETSR60_FLD_SET(value) (((value) << 0) & 0xffffffff)
19181 
19182 #ifndef __ASSEMBLY__
19183 /*
19184  * WARNING: The C register and register group struct declarations are provided for
19185  * convenience and illustrative purposes. They should, however, be used with
19186  * caution as the C language standard provides no guarantees about the alignment or
19187  * atomicity of device memory accesses. The recommended practice for coding device
19188  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
19189  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
19190  * alt_write_dword() functions for 64 bit registers.
19191  *
19192  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR60.
19193  */
19194 struct ALT_GIC_DIST_GICD_ITARGETSR60_s
19195 {
19196  volatile uint32_t fld : 32; /* Empty */
19197 };
19198 
19199 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR60. */
19200 typedef struct ALT_GIC_DIST_GICD_ITARGETSR60_s ALT_GIC_DIST_GICD_ITARGETSR60_t;
19201 #endif /* __ASSEMBLY__ */
19202 
19203 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR60 register. */
19204 #define ALT_GIC_DIST_GICD_ITARGETSR60_RESET 0x00000000
19205 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR60 register from the beginning of the component. */
19206 #define ALT_GIC_DIST_GICD_ITARGETSR60_OFST 0x8f0
19207 
19208 /*
19209  * Register : GICD_ITARGETSR61
19210  *
19211  * Interrupt Processor Targets Registers
19212  *
19213  * Register Layout
19214  *
19215  * Bits | Access | Reset | Description
19216  * :-------|:-------|:------|:------------
19217  * [31:0] | RW | 0x0 | Empty
19218  *
19219  */
19220 /*
19221  * Field : Empty - fld
19222  *
19223  * Placeholder
19224  *
19225  * Field Access Macros:
19226  *
19227  */
19228 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR61_FLD register field. */
19229 #define ALT_GIC_DIST_GICD_ITARGETSR61_FLD_LSB 0
19230 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR61_FLD register field. */
19231 #define ALT_GIC_DIST_GICD_ITARGETSR61_FLD_MSB 31
19232 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR61_FLD register field. */
19233 #define ALT_GIC_DIST_GICD_ITARGETSR61_FLD_WIDTH 32
19234 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR61_FLD register field value. */
19235 #define ALT_GIC_DIST_GICD_ITARGETSR61_FLD_SET_MSK 0xffffffff
19236 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR61_FLD register field value. */
19237 #define ALT_GIC_DIST_GICD_ITARGETSR61_FLD_CLR_MSK 0x00000000
19238 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR61_FLD register field. */
19239 #define ALT_GIC_DIST_GICD_ITARGETSR61_FLD_RESET 0x0
19240 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR61_FLD field value from a register. */
19241 #define ALT_GIC_DIST_GICD_ITARGETSR61_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19242 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR61_FLD register field value suitable for setting the register. */
19243 #define ALT_GIC_DIST_GICD_ITARGETSR61_FLD_SET(value) (((value) << 0) & 0xffffffff)
19244 
19245 #ifndef __ASSEMBLY__
19246 /*
19247  * WARNING: The C register and register group struct declarations are provided for
19248  * convenience and illustrative purposes. They should, however, be used with
19249  * caution as the C language standard provides no guarantees about the alignment or
19250  * atomicity of device memory accesses. The recommended practice for coding device
19251  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
19252  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
19253  * alt_write_dword() functions for 64 bit registers.
19254  *
19255  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR61.
19256  */
19257 struct ALT_GIC_DIST_GICD_ITARGETSR61_s
19258 {
19259  volatile uint32_t fld : 32; /* Empty */
19260 };
19261 
19262 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR61. */
19263 typedef struct ALT_GIC_DIST_GICD_ITARGETSR61_s ALT_GIC_DIST_GICD_ITARGETSR61_t;
19264 #endif /* __ASSEMBLY__ */
19265 
19266 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR61 register. */
19267 #define ALT_GIC_DIST_GICD_ITARGETSR61_RESET 0x00000000
19268 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR61 register from the beginning of the component. */
19269 #define ALT_GIC_DIST_GICD_ITARGETSR61_OFST 0x8f4
19270 
19271 /*
19272  * Register : GICD_ITARGETSR62
19273  *
19274  * Interrupt Processor Targets Registers
19275  *
19276  * Register Layout
19277  *
19278  * Bits | Access | Reset | Description
19279  * :-------|:-------|:------|:------------
19280  * [31:0] | RW | 0x0 | Empty
19281  *
19282  */
19283 /*
19284  * Field : Empty - fld
19285  *
19286  * Placeholder
19287  *
19288  * Field Access Macros:
19289  *
19290  */
19291 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR62_FLD register field. */
19292 #define ALT_GIC_DIST_GICD_ITARGETSR62_FLD_LSB 0
19293 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR62_FLD register field. */
19294 #define ALT_GIC_DIST_GICD_ITARGETSR62_FLD_MSB 31
19295 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR62_FLD register field. */
19296 #define ALT_GIC_DIST_GICD_ITARGETSR62_FLD_WIDTH 32
19297 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR62_FLD register field value. */
19298 #define ALT_GIC_DIST_GICD_ITARGETSR62_FLD_SET_MSK 0xffffffff
19299 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR62_FLD register field value. */
19300 #define ALT_GIC_DIST_GICD_ITARGETSR62_FLD_CLR_MSK 0x00000000
19301 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR62_FLD register field. */
19302 #define ALT_GIC_DIST_GICD_ITARGETSR62_FLD_RESET 0x0
19303 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR62_FLD field value from a register. */
19304 #define ALT_GIC_DIST_GICD_ITARGETSR62_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19305 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR62_FLD register field value suitable for setting the register. */
19306 #define ALT_GIC_DIST_GICD_ITARGETSR62_FLD_SET(value) (((value) << 0) & 0xffffffff)
19307 
19308 #ifndef __ASSEMBLY__
19309 /*
19310  * WARNING: The C register and register group struct declarations are provided for
19311  * convenience and illustrative purposes. They should, however, be used with
19312  * caution as the C language standard provides no guarantees about the alignment or
19313  * atomicity of device memory accesses. The recommended practice for coding device
19314  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
19315  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
19316  * alt_write_dword() functions for 64 bit registers.
19317  *
19318  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR62.
19319  */
19320 struct ALT_GIC_DIST_GICD_ITARGETSR62_s
19321 {
19322  volatile uint32_t fld : 32; /* Empty */
19323 };
19324 
19325 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR62. */
19326 typedef struct ALT_GIC_DIST_GICD_ITARGETSR62_s ALT_GIC_DIST_GICD_ITARGETSR62_t;
19327 #endif /* __ASSEMBLY__ */
19328 
19329 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR62 register. */
19330 #define ALT_GIC_DIST_GICD_ITARGETSR62_RESET 0x00000000
19331 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR62 register from the beginning of the component. */
19332 #define ALT_GIC_DIST_GICD_ITARGETSR62_OFST 0x8f8
19333 
19334 /*
19335  * Register : GICD_ITARGETSR63
19336  *
19337  * Interrupt Processor Targets Registers
19338  *
19339  * Register Layout
19340  *
19341  * Bits | Access | Reset | Description
19342  * :-------|:-------|:------|:------------
19343  * [31:0] | RW | 0x0 | Empty
19344  *
19345  */
19346 /*
19347  * Field : Empty - fld
19348  *
19349  * Placeholder
19350  *
19351  * Field Access Macros:
19352  *
19353  */
19354 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR63_FLD register field. */
19355 #define ALT_GIC_DIST_GICD_ITARGETSR63_FLD_LSB 0
19356 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR63_FLD register field. */
19357 #define ALT_GIC_DIST_GICD_ITARGETSR63_FLD_MSB 31
19358 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR63_FLD register field. */
19359 #define ALT_GIC_DIST_GICD_ITARGETSR63_FLD_WIDTH 32
19360 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR63_FLD register field value. */
19361 #define ALT_GIC_DIST_GICD_ITARGETSR63_FLD_SET_MSK 0xffffffff
19362 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR63_FLD register field value. */
19363 #define ALT_GIC_DIST_GICD_ITARGETSR63_FLD_CLR_MSK 0x00000000
19364 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR63_FLD register field. */
19365 #define ALT_GIC_DIST_GICD_ITARGETSR63_FLD_RESET 0x0
19366 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR63_FLD field value from a register. */
19367 #define ALT_GIC_DIST_GICD_ITARGETSR63_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19368 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR63_FLD register field value suitable for setting the register. */
19369 #define ALT_GIC_DIST_GICD_ITARGETSR63_FLD_SET(value) (((value) << 0) & 0xffffffff)
19370 
19371 #ifndef __ASSEMBLY__
19372 /*
19373  * WARNING: The C register and register group struct declarations are provided for
19374  * convenience and illustrative purposes. They should, however, be used with
19375  * caution as the C language standard provides no guarantees about the alignment or
19376  * atomicity of device memory accesses. The recommended practice for coding device
19377  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
19378  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
19379  * alt_write_dword() functions for 64 bit registers.
19380  *
19381  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR63.
19382  */
19383 struct ALT_GIC_DIST_GICD_ITARGETSR63_s
19384 {
19385  volatile uint32_t fld : 32; /* Empty */
19386 };
19387 
19388 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR63. */
19389 typedef struct ALT_GIC_DIST_GICD_ITARGETSR63_s ALT_GIC_DIST_GICD_ITARGETSR63_t;
19390 #endif /* __ASSEMBLY__ */
19391 
19392 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR63 register. */
19393 #define ALT_GIC_DIST_GICD_ITARGETSR63_RESET 0x00000000
19394 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR63 register from the beginning of the component. */
19395 #define ALT_GIC_DIST_GICD_ITARGETSR63_OFST 0x8fc
19396 
19397 /*
19398  * Register : GICD_ITARGETSR64
19399  *
19400  * Interrupt Processor Targets Registers
19401  *
19402  * Register Layout
19403  *
19404  * Bits | Access | Reset | Description
19405  * :-------|:-------|:------|:------------
19406  * [31:0] | RW | 0x0 | Empty
19407  *
19408  */
19409 /*
19410  * Field : Empty - fld
19411  *
19412  * Placeholder
19413  *
19414  * Field Access Macros:
19415  *
19416  */
19417 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR64_FLD register field. */
19418 #define ALT_GIC_DIST_GICD_ITARGETSR64_FLD_LSB 0
19419 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR64_FLD register field. */
19420 #define ALT_GIC_DIST_GICD_ITARGETSR64_FLD_MSB 31
19421 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR64_FLD register field. */
19422 #define ALT_GIC_DIST_GICD_ITARGETSR64_FLD_WIDTH 32
19423 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR64_FLD register field value. */
19424 #define ALT_GIC_DIST_GICD_ITARGETSR64_FLD_SET_MSK 0xffffffff
19425 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR64_FLD register field value. */
19426 #define ALT_GIC_DIST_GICD_ITARGETSR64_FLD_CLR_MSK 0x00000000
19427 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR64_FLD register field. */
19428 #define ALT_GIC_DIST_GICD_ITARGETSR64_FLD_RESET 0x0
19429 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR64_FLD field value from a register. */
19430 #define ALT_GIC_DIST_GICD_ITARGETSR64_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19431 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR64_FLD register field value suitable for setting the register. */
19432 #define ALT_GIC_DIST_GICD_ITARGETSR64_FLD_SET(value) (((value) << 0) & 0xffffffff)
19433 
19434 #ifndef __ASSEMBLY__
19435 /*
19436  * WARNING: The C register and register group struct declarations are provided for
19437  * convenience and illustrative purposes. They should, however, be used with
19438  * caution as the C language standard provides no guarantees about the alignment or
19439  * atomicity of device memory accesses. The recommended practice for coding device
19440  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
19441  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
19442  * alt_write_dword() functions for 64 bit registers.
19443  *
19444  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR64.
19445  */
19446 struct ALT_GIC_DIST_GICD_ITARGETSR64_s
19447 {
19448  volatile uint32_t fld : 32; /* Empty */
19449 };
19450 
19451 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR64. */
19452 typedef struct ALT_GIC_DIST_GICD_ITARGETSR64_s ALT_GIC_DIST_GICD_ITARGETSR64_t;
19453 #endif /* __ASSEMBLY__ */
19454 
19455 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR64 register. */
19456 #define ALT_GIC_DIST_GICD_ITARGETSR64_RESET 0x00000000
19457 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR64 register from the beginning of the component. */
19458 #define ALT_GIC_DIST_GICD_ITARGETSR64_OFST 0x900
19459 
19460 /*
19461  * Register : GICD_ITARGETSR65
19462  *
19463  * Interrupt Processor Targets Registers
19464  *
19465  * Register Layout
19466  *
19467  * Bits | Access | Reset | Description
19468  * :-------|:-------|:------|:------------
19469  * [31:0] | RW | 0x0 | Empty
19470  *
19471  */
19472 /*
19473  * Field : Empty - fld
19474  *
19475  * Placeholder
19476  *
19477  * Field Access Macros:
19478  *
19479  */
19480 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR65_FLD register field. */
19481 #define ALT_GIC_DIST_GICD_ITARGETSR65_FLD_LSB 0
19482 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR65_FLD register field. */
19483 #define ALT_GIC_DIST_GICD_ITARGETSR65_FLD_MSB 31
19484 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR65_FLD register field. */
19485 #define ALT_GIC_DIST_GICD_ITARGETSR65_FLD_WIDTH 32
19486 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR65_FLD register field value. */
19487 #define ALT_GIC_DIST_GICD_ITARGETSR65_FLD_SET_MSK 0xffffffff
19488 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR65_FLD register field value. */
19489 #define ALT_GIC_DIST_GICD_ITARGETSR65_FLD_CLR_MSK 0x00000000
19490 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR65_FLD register field. */
19491 #define ALT_GIC_DIST_GICD_ITARGETSR65_FLD_RESET 0x0
19492 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR65_FLD field value from a register. */
19493 #define ALT_GIC_DIST_GICD_ITARGETSR65_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19494 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR65_FLD register field value suitable for setting the register. */
19495 #define ALT_GIC_DIST_GICD_ITARGETSR65_FLD_SET(value) (((value) << 0) & 0xffffffff)
19496 
19497 #ifndef __ASSEMBLY__
19498 /*
19499  * WARNING: The C register and register group struct declarations are provided for
19500  * convenience and illustrative purposes. They should, however, be used with
19501  * caution as the C language standard provides no guarantees about the alignment or
19502  * atomicity of device memory accesses. The recommended practice for coding device
19503  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
19504  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
19505  * alt_write_dword() functions for 64 bit registers.
19506  *
19507  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR65.
19508  */
19509 struct ALT_GIC_DIST_GICD_ITARGETSR65_s
19510 {
19511  volatile uint32_t fld : 32; /* Empty */
19512 };
19513 
19514 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR65. */
19515 typedef struct ALT_GIC_DIST_GICD_ITARGETSR65_s ALT_GIC_DIST_GICD_ITARGETSR65_t;
19516 #endif /* __ASSEMBLY__ */
19517 
19518 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR65 register. */
19519 #define ALT_GIC_DIST_GICD_ITARGETSR65_RESET 0x00000000
19520 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR65 register from the beginning of the component. */
19521 #define ALT_GIC_DIST_GICD_ITARGETSR65_OFST 0x904
19522 
19523 /*
19524  * Register : GICD_ITARGETSR66
19525  *
19526  * Interrupt Processor Targets Registers
19527  *
19528  * Register Layout
19529  *
19530  * Bits | Access | Reset | Description
19531  * :-------|:-------|:------|:------------
19532  * [31:0] | RW | 0x0 | Empty
19533  *
19534  */
19535 /*
19536  * Field : Empty - fld
19537  *
19538  * Placeholder
19539  *
19540  * Field Access Macros:
19541  *
19542  */
19543 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR66_FLD register field. */
19544 #define ALT_GIC_DIST_GICD_ITARGETSR66_FLD_LSB 0
19545 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR66_FLD register field. */
19546 #define ALT_GIC_DIST_GICD_ITARGETSR66_FLD_MSB 31
19547 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR66_FLD register field. */
19548 #define ALT_GIC_DIST_GICD_ITARGETSR66_FLD_WIDTH 32
19549 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR66_FLD register field value. */
19550 #define ALT_GIC_DIST_GICD_ITARGETSR66_FLD_SET_MSK 0xffffffff
19551 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR66_FLD register field value. */
19552 #define ALT_GIC_DIST_GICD_ITARGETSR66_FLD_CLR_MSK 0x00000000
19553 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR66_FLD register field. */
19554 #define ALT_GIC_DIST_GICD_ITARGETSR66_FLD_RESET 0x0
19555 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR66_FLD field value from a register. */
19556 #define ALT_GIC_DIST_GICD_ITARGETSR66_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19557 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR66_FLD register field value suitable for setting the register. */
19558 #define ALT_GIC_DIST_GICD_ITARGETSR66_FLD_SET(value) (((value) << 0) & 0xffffffff)
19559 
19560 #ifndef __ASSEMBLY__
19561 /*
19562  * WARNING: The C register and register group struct declarations are provided for
19563  * convenience and illustrative purposes. They should, however, be used with
19564  * caution as the C language standard provides no guarantees about the alignment or
19565  * atomicity of device memory accesses. The recommended practice for coding device
19566  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
19567  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
19568  * alt_write_dword() functions for 64 bit registers.
19569  *
19570  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR66.
19571  */
19572 struct ALT_GIC_DIST_GICD_ITARGETSR66_s
19573 {
19574  volatile uint32_t fld : 32; /* Empty */
19575 };
19576 
19577 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR66. */
19578 typedef struct ALT_GIC_DIST_GICD_ITARGETSR66_s ALT_GIC_DIST_GICD_ITARGETSR66_t;
19579 #endif /* __ASSEMBLY__ */
19580 
19581 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR66 register. */
19582 #define ALT_GIC_DIST_GICD_ITARGETSR66_RESET 0x00000000
19583 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR66 register from the beginning of the component. */
19584 #define ALT_GIC_DIST_GICD_ITARGETSR66_OFST 0x908
19585 
19586 /*
19587  * Register : GICD_ITARGETSR67
19588  *
19589  * Interrupt Processor Targets Registers
19590  *
19591  * Register Layout
19592  *
19593  * Bits | Access | Reset | Description
19594  * :-------|:-------|:------|:------------
19595  * [31:0] | RW | 0x0 | Empty
19596  *
19597  */
19598 /*
19599  * Field : Empty - fld
19600  *
19601  * Placeholder
19602  *
19603  * Field Access Macros:
19604  *
19605  */
19606 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR67_FLD register field. */
19607 #define ALT_GIC_DIST_GICD_ITARGETSR67_FLD_LSB 0
19608 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR67_FLD register field. */
19609 #define ALT_GIC_DIST_GICD_ITARGETSR67_FLD_MSB 31
19610 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR67_FLD register field. */
19611 #define ALT_GIC_DIST_GICD_ITARGETSR67_FLD_WIDTH 32
19612 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR67_FLD register field value. */
19613 #define ALT_GIC_DIST_GICD_ITARGETSR67_FLD_SET_MSK 0xffffffff
19614 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR67_FLD register field value. */
19615 #define ALT_GIC_DIST_GICD_ITARGETSR67_FLD_CLR_MSK 0x00000000
19616 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR67_FLD register field. */
19617 #define ALT_GIC_DIST_GICD_ITARGETSR67_FLD_RESET 0x0
19618 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR67_FLD field value from a register. */
19619 #define ALT_GIC_DIST_GICD_ITARGETSR67_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19620 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR67_FLD register field value suitable for setting the register. */
19621 #define ALT_GIC_DIST_GICD_ITARGETSR67_FLD_SET(value) (((value) << 0) & 0xffffffff)
19622 
19623 #ifndef __ASSEMBLY__
19624 /*
19625  * WARNING: The C register and register group struct declarations are provided for
19626  * convenience and illustrative purposes. They should, however, be used with
19627  * caution as the C language standard provides no guarantees about the alignment or
19628  * atomicity of device memory accesses. The recommended practice for coding device
19629  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
19630  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
19631  * alt_write_dword() functions for 64 bit registers.
19632  *
19633  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR67.
19634  */
19635 struct ALT_GIC_DIST_GICD_ITARGETSR67_s
19636 {
19637  volatile uint32_t fld : 32; /* Empty */
19638 };
19639 
19640 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR67. */
19641 typedef struct ALT_GIC_DIST_GICD_ITARGETSR67_s ALT_GIC_DIST_GICD_ITARGETSR67_t;
19642 #endif /* __ASSEMBLY__ */
19643 
19644 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR67 register. */
19645 #define ALT_GIC_DIST_GICD_ITARGETSR67_RESET 0x00000000
19646 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR67 register from the beginning of the component. */
19647 #define ALT_GIC_DIST_GICD_ITARGETSR67_OFST 0x90c
19648 
19649 /*
19650  * Register : GICD_ITARGETSR68
19651  *
19652  * Interrupt Processor Targets Registers
19653  *
19654  * Register Layout
19655  *
19656  * Bits | Access | Reset | Description
19657  * :-------|:-------|:------|:------------
19658  * [31:0] | RW | 0x0 | Empty
19659  *
19660  */
19661 /*
19662  * Field : Empty - fld
19663  *
19664  * Placeholder
19665  *
19666  * Field Access Macros:
19667  *
19668  */
19669 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR68_FLD register field. */
19670 #define ALT_GIC_DIST_GICD_ITARGETSR68_FLD_LSB 0
19671 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR68_FLD register field. */
19672 #define ALT_GIC_DIST_GICD_ITARGETSR68_FLD_MSB 31
19673 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR68_FLD register field. */
19674 #define ALT_GIC_DIST_GICD_ITARGETSR68_FLD_WIDTH 32
19675 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR68_FLD register field value. */
19676 #define ALT_GIC_DIST_GICD_ITARGETSR68_FLD_SET_MSK 0xffffffff
19677 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR68_FLD register field value. */
19678 #define ALT_GIC_DIST_GICD_ITARGETSR68_FLD_CLR_MSK 0x00000000
19679 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR68_FLD register field. */
19680 #define ALT_GIC_DIST_GICD_ITARGETSR68_FLD_RESET 0x0
19681 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR68_FLD field value from a register. */
19682 #define ALT_GIC_DIST_GICD_ITARGETSR68_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19683 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR68_FLD register field value suitable for setting the register. */
19684 #define ALT_GIC_DIST_GICD_ITARGETSR68_FLD_SET(value) (((value) << 0) & 0xffffffff)
19685 
19686 #ifndef __ASSEMBLY__
19687 /*
19688  * WARNING: The C register and register group struct declarations are provided for
19689  * convenience and illustrative purposes. They should, however, be used with
19690  * caution as the C language standard provides no guarantees about the alignment or
19691  * atomicity of device memory accesses. The recommended practice for coding device
19692  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
19693  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
19694  * alt_write_dword() functions for 64 bit registers.
19695  *
19696  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR68.
19697  */
19698 struct ALT_GIC_DIST_GICD_ITARGETSR68_s
19699 {
19700  volatile uint32_t fld : 32; /* Empty */
19701 };
19702 
19703 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR68. */
19704 typedef struct ALT_GIC_DIST_GICD_ITARGETSR68_s ALT_GIC_DIST_GICD_ITARGETSR68_t;
19705 #endif /* __ASSEMBLY__ */
19706 
19707 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR68 register. */
19708 #define ALT_GIC_DIST_GICD_ITARGETSR68_RESET 0x00000000
19709 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR68 register from the beginning of the component. */
19710 #define ALT_GIC_DIST_GICD_ITARGETSR68_OFST 0x910
19711 
19712 /*
19713  * Register : GICD_ITARGETSR69
19714  *
19715  * Interrupt Processor Targets Registers
19716  *
19717  * Register Layout
19718  *
19719  * Bits | Access | Reset | Description
19720  * :-------|:-------|:------|:------------
19721  * [31:0] | RW | 0x0 | Empty
19722  *
19723  */
19724 /*
19725  * Field : Empty - fld
19726  *
19727  * Placeholder
19728  *
19729  * Field Access Macros:
19730  *
19731  */
19732 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR69_FLD register field. */
19733 #define ALT_GIC_DIST_GICD_ITARGETSR69_FLD_LSB 0
19734 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR69_FLD register field. */
19735 #define ALT_GIC_DIST_GICD_ITARGETSR69_FLD_MSB 31
19736 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR69_FLD register field. */
19737 #define ALT_GIC_DIST_GICD_ITARGETSR69_FLD_WIDTH 32
19738 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR69_FLD register field value. */
19739 #define ALT_GIC_DIST_GICD_ITARGETSR69_FLD_SET_MSK 0xffffffff
19740 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR69_FLD register field value. */
19741 #define ALT_GIC_DIST_GICD_ITARGETSR69_FLD_CLR_MSK 0x00000000
19742 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR69_FLD register field. */
19743 #define ALT_GIC_DIST_GICD_ITARGETSR69_FLD_RESET 0x0
19744 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR69_FLD field value from a register. */
19745 #define ALT_GIC_DIST_GICD_ITARGETSR69_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19746 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR69_FLD register field value suitable for setting the register. */
19747 #define ALT_GIC_DIST_GICD_ITARGETSR69_FLD_SET(value) (((value) << 0) & 0xffffffff)
19748 
19749 #ifndef __ASSEMBLY__
19750 /*
19751  * WARNING: The C register and register group struct declarations are provided for
19752  * convenience and illustrative purposes. They should, however, be used with
19753  * caution as the C language standard provides no guarantees about the alignment or
19754  * atomicity of device memory accesses. The recommended practice for coding device
19755  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
19756  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
19757  * alt_write_dword() functions for 64 bit registers.
19758  *
19759  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR69.
19760  */
19761 struct ALT_GIC_DIST_GICD_ITARGETSR69_s
19762 {
19763  volatile uint32_t fld : 32; /* Empty */
19764 };
19765 
19766 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR69. */
19767 typedef struct ALT_GIC_DIST_GICD_ITARGETSR69_s ALT_GIC_DIST_GICD_ITARGETSR69_t;
19768 #endif /* __ASSEMBLY__ */
19769 
19770 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR69 register. */
19771 #define ALT_GIC_DIST_GICD_ITARGETSR69_RESET 0x00000000
19772 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR69 register from the beginning of the component. */
19773 #define ALT_GIC_DIST_GICD_ITARGETSR69_OFST 0x914
19774 
19775 /*
19776  * Register : GICD_ITARGETSR70
19777  *
19778  * Interrupt Processor Targets Registers
19779  *
19780  * Register Layout
19781  *
19782  * Bits | Access | Reset | Description
19783  * :-------|:-------|:------|:------------
19784  * [31:0] | RW | 0x0 | Empty
19785  *
19786  */
19787 /*
19788  * Field : Empty - fld
19789  *
19790  * Placeholder
19791  *
19792  * Field Access Macros:
19793  *
19794  */
19795 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR70_FLD register field. */
19796 #define ALT_GIC_DIST_GICD_ITARGETSR70_FLD_LSB 0
19797 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR70_FLD register field. */
19798 #define ALT_GIC_DIST_GICD_ITARGETSR70_FLD_MSB 31
19799 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR70_FLD register field. */
19800 #define ALT_GIC_DIST_GICD_ITARGETSR70_FLD_WIDTH 32
19801 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR70_FLD register field value. */
19802 #define ALT_GIC_DIST_GICD_ITARGETSR70_FLD_SET_MSK 0xffffffff
19803 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR70_FLD register field value. */
19804 #define ALT_GIC_DIST_GICD_ITARGETSR70_FLD_CLR_MSK 0x00000000
19805 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR70_FLD register field. */
19806 #define ALT_GIC_DIST_GICD_ITARGETSR70_FLD_RESET 0x0
19807 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR70_FLD field value from a register. */
19808 #define ALT_GIC_DIST_GICD_ITARGETSR70_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19809 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR70_FLD register field value suitable for setting the register. */
19810 #define ALT_GIC_DIST_GICD_ITARGETSR70_FLD_SET(value) (((value) << 0) & 0xffffffff)
19811 
19812 #ifndef __ASSEMBLY__
19813 /*
19814  * WARNING: The C register and register group struct declarations are provided for
19815  * convenience and illustrative purposes. They should, however, be used with
19816  * caution as the C language standard provides no guarantees about the alignment or
19817  * atomicity of device memory accesses. The recommended practice for coding device
19818  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
19819  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
19820  * alt_write_dword() functions for 64 bit registers.
19821  *
19822  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR70.
19823  */
19824 struct ALT_GIC_DIST_GICD_ITARGETSR70_s
19825 {
19826  volatile uint32_t fld : 32; /* Empty */
19827 };
19828 
19829 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR70. */
19830 typedef struct ALT_GIC_DIST_GICD_ITARGETSR70_s ALT_GIC_DIST_GICD_ITARGETSR70_t;
19831 #endif /* __ASSEMBLY__ */
19832 
19833 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR70 register. */
19834 #define ALT_GIC_DIST_GICD_ITARGETSR70_RESET 0x00000000
19835 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR70 register from the beginning of the component. */
19836 #define ALT_GIC_DIST_GICD_ITARGETSR70_OFST 0x918
19837 
19838 /*
19839  * Register : GICD_ITARGETSR71
19840  *
19841  * Interrupt Processor Targets Registers
19842  *
19843  * Register Layout
19844  *
19845  * Bits | Access | Reset | Description
19846  * :-------|:-------|:------|:------------
19847  * [31:0] | RW | 0x0 | Empty
19848  *
19849  */
19850 /*
19851  * Field : Empty - fld
19852  *
19853  * Placeholder
19854  *
19855  * Field Access Macros:
19856  *
19857  */
19858 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR71_FLD register field. */
19859 #define ALT_GIC_DIST_GICD_ITARGETSR71_FLD_LSB 0
19860 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR71_FLD register field. */
19861 #define ALT_GIC_DIST_GICD_ITARGETSR71_FLD_MSB 31
19862 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR71_FLD register field. */
19863 #define ALT_GIC_DIST_GICD_ITARGETSR71_FLD_WIDTH 32
19864 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR71_FLD register field value. */
19865 #define ALT_GIC_DIST_GICD_ITARGETSR71_FLD_SET_MSK 0xffffffff
19866 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR71_FLD register field value. */
19867 #define ALT_GIC_DIST_GICD_ITARGETSR71_FLD_CLR_MSK 0x00000000
19868 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR71_FLD register field. */
19869 #define ALT_GIC_DIST_GICD_ITARGETSR71_FLD_RESET 0x0
19870 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR71_FLD field value from a register. */
19871 #define ALT_GIC_DIST_GICD_ITARGETSR71_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19872 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR71_FLD register field value suitable for setting the register. */
19873 #define ALT_GIC_DIST_GICD_ITARGETSR71_FLD_SET(value) (((value) << 0) & 0xffffffff)
19874 
19875 #ifndef __ASSEMBLY__
19876 /*
19877  * WARNING: The C register and register group struct declarations are provided for
19878  * convenience and illustrative purposes. They should, however, be used with
19879  * caution as the C language standard provides no guarantees about the alignment or
19880  * atomicity of device memory accesses. The recommended practice for coding device
19881  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
19882  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
19883  * alt_write_dword() functions for 64 bit registers.
19884  *
19885  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR71.
19886  */
19887 struct ALT_GIC_DIST_GICD_ITARGETSR71_s
19888 {
19889  volatile uint32_t fld : 32; /* Empty */
19890 };
19891 
19892 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR71. */
19893 typedef struct ALT_GIC_DIST_GICD_ITARGETSR71_s ALT_GIC_DIST_GICD_ITARGETSR71_t;
19894 #endif /* __ASSEMBLY__ */
19895 
19896 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR71 register. */
19897 #define ALT_GIC_DIST_GICD_ITARGETSR71_RESET 0x00000000
19898 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR71 register from the beginning of the component. */
19899 #define ALT_GIC_DIST_GICD_ITARGETSR71_OFST 0x91c
19900 
19901 /*
19902  * Register : GICD_ITARGETSR72
19903  *
19904  * Interrupt Processor Targets Registers
19905  *
19906  * Register Layout
19907  *
19908  * Bits | Access | Reset | Description
19909  * :-------|:-------|:------|:------------
19910  * [31:0] | RW | 0x0 | Empty
19911  *
19912  */
19913 /*
19914  * Field : Empty - fld
19915  *
19916  * Placeholder
19917  *
19918  * Field Access Macros:
19919  *
19920  */
19921 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR72_FLD register field. */
19922 #define ALT_GIC_DIST_GICD_ITARGETSR72_FLD_LSB 0
19923 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR72_FLD register field. */
19924 #define ALT_GIC_DIST_GICD_ITARGETSR72_FLD_MSB 31
19925 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR72_FLD register field. */
19926 #define ALT_GIC_DIST_GICD_ITARGETSR72_FLD_WIDTH 32
19927 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR72_FLD register field value. */
19928 #define ALT_GIC_DIST_GICD_ITARGETSR72_FLD_SET_MSK 0xffffffff
19929 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR72_FLD register field value. */
19930 #define ALT_GIC_DIST_GICD_ITARGETSR72_FLD_CLR_MSK 0x00000000
19931 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR72_FLD register field. */
19932 #define ALT_GIC_DIST_GICD_ITARGETSR72_FLD_RESET 0x0
19933 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR72_FLD field value from a register. */
19934 #define ALT_GIC_DIST_GICD_ITARGETSR72_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19935 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR72_FLD register field value suitable for setting the register. */
19936 #define ALT_GIC_DIST_GICD_ITARGETSR72_FLD_SET(value) (((value) << 0) & 0xffffffff)
19937 
19938 #ifndef __ASSEMBLY__
19939 /*
19940  * WARNING: The C register and register group struct declarations are provided for
19941  * convenience and illustrative purposes. They should, however, be used with
19942  * caution as the C language standard provides no guarantees about the alignment or
19943  * atomicity of device memory accesses. The recommended practice for coding device
19944  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
19945  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
19946  * alt_write_dword() functions for 64 bit registers.
19947  *
19948  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR72.
19949  */
19950 struct ALT_GIC_DIST_GICD_ITARGETSR72_s
19951 {
19952  volatile uint32_t fld : 32; /* Empty */
19953 };
19954 
19955 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR72. */
19956 typedef struct ALT_GIC_DIST_GICD_ITARGETSR72_s ALT_GIC_DIST_GICD_ITARGETSR72_t;
19957 #endif /* __ASSEMBLY__ */
19958 
19959 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR72 register. */
19960 #define ALT_GIC_DIST_GICD_ITARGETSR72_RESET 0x00000000
19961 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR72 register from the beginning of the component. */
19962 #define ALT_GIC_DIST_GICD_ITARGETSR72_OFST 0x920
19963 
19964 /*
19965  * Register : GICD_ITARGETSR73
19966  *
19967  * Interrupt Processor Targets Registers
19968  *
19969  * Register Layout
19970  *
19971  * Bits | Access | Reset | Description
19972  * :-------|:-------|:------|:------------
19973  * [31:0] | RW | 0x0 | Empty
19974  *
19975  */
19976 /*
19977  * Field : Empty - fld
19978  *
19979  * Placeholder
19980  *
19981  * Field Access Macros:
19982  *
19983  */
19984 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR73_FLD register field. */
19985 #define ALT_GIC_DIST_GICD_ITARGETSR73_FLD_LSB 0
19986 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR73_FLD register field. */
19987 #define ALT_GIC_DIST_GICD_ITARGETSR73_FLD_MSB 31
19988 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR73_FLD register field. */
19989 #define ALT_GIC_DIST_GICD_ITARGETSR73_FLD_WIDTH 32
19990 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR73_FLD register field value. */
19991 #define ALT_GIC_DIST_GICD_ITARGETSR73_FLD_SET_MSK 0xffffffff
19992 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR73_FLD register field value. */
19993 #define ALT_GIC_DIST_GICD_ITARGETSR73_FLD_CLR_MSK 0x00000000
19994 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR73_FLD register field. */
19995 #define ALT_GIC_DIST_GICD_ITARGETSR73_FLD_RESET 0x0
19996 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR73_FLD field value from a register. */
19997 #define ALT_GIC_DIST_GICD_ITARGETSR73_FLD_GET(value) (((value) & 0xffffffff) >> 0)
19998 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR73_FLD register field value suitable for setting the register. */
19999 #define ALT_GIC_DIST_GICD_ITARGETSR73_FLD_SET(value) (((value) << 0) & 0xffffffff)
20000 
20001 #ifndef __ASSEMBLY__
20002 /*
20003  * WARNING: The C register and register group struct declarations are provided for
20004  * convenience and illustrative purposes. They should, however, be used with
20005  * caution as the C language standard provides no guarantees about the alignment or
20006  * atomicity of device memory accesses. The recommended practice for coding device
20007  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
20008  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
20009  * alt_write_dword() functions for 64 bit registers.
20010  *
20011  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR73.
20012  */
20013 struct ALT_GIC_DIST_GICD_ITARGETSR73_s
20014 {
20015  volatile uint32_t fld : 32; /* Empty */
20016 };
20017 
20018 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR73. */
20019 typedef struct ALT_GIC_DIST_GICD_ITARGETSR73_s ALT_GIC_DIST_GICD_ITARGETSR73_t;
20020 #endif /* __ASSEMBLY__ */
20021 
20022 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR73 register. */
20023 #define ALT_GIC_DIST_GICD_ITARGETSR73_RESET 0x00000000
20024 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR73 register from the beginning of the component. */
20025 #define ALT_GIC_DIST_GICD_ITARGETSR73_OFST 0x924
20026 
20027 /*
20028  * Register : GICD_ITARGETSR74
20029  *
20030  * Interrupt Processor Targets Registers
20031  *
20032  * Register Layout
20033  *
20034  * Bits | Access | Reset | Description
20035  * :-------|:-------|:------|:------------
20036  * [31:0] | RW | 0x0 | Empty
20037  *
20038  */
20039 /*
20040  * Field : Empty - fld
20041  *
20042  * Placeholder
20043  *
20044  * Field Access Macros:
20045  *
20046  */
20047 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR74_FLD register field. */
20048 #define ALT_GIC_DIST_GICD_ITARGETSR74_FLD_LSB 0
20049 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR74_FLD register field. */
20050 #define ALT_GIC_DIST_GICD_ITARGETSR74_FLD_MSB 31
20051 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR74_FLD register field. */
20052 #define ALT_GIC_DIST_GICD_ITARGETSR74_FLD_WIDTH 32
20053 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR74_FLD register field value. */
20054 #define ALT_GIC_DIST_GICD_ITARGETSR74_FLD_SET_MSK 0xffffffff
20055 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR74_FLD register field value. */
20056 #define ALT_GIC_DIST_GICD_ITARGETSR74_FLD_CLR_MSK 0x00000000
20057 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR74_FLD register field. */
20058 #define ALT_GIC_DIST_GICD_ITARGETSR74_FLD_RESET 0x0
20059 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR74_FLD field value from a register. */
20060 #define ALT_GIC_DIST_GICD_ITARGETSR74_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20061 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR74_FLD register field value suitable for setting the register. */
20062 #define ALT_GIC_DIST_GICD_ITARGETSR74_FLD_SET(value) (((value) << 0) & 0xffffffff)
20063 
20064 #ifndef __ASSEMBLY__
20065 /*
20066  * WARNING: The C register and register group struct declarations are provided for
20067  * convenience and illustrative purposes. They should, however, be used with
20068  * caution as the C language standard provides no guarantees about the alignment or
20069  * atomicity of device memory accesses. The recommended practice for coding device
20070  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
20071  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
20072  * alt_write_dword() functions for 64 bit registers.
20073  *
20074  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR74.
20075  */
20076 struct ALT_GIC_DIST_GICD_ITARGETSR74_s
20077 {
20078  volatile uint32_t fld : 32; /* Empty */
20079 };
20080 
20081 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR74. */
20082 typedef struct ALT_GIC_DIST_GICD_ITARGETSR74_s ALT_GIC_DIST_GICD_ITARGETSR74_t;
20083 #endif /* __ASSEMBLY__ */
20084 
20085 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR74 register. */
20086 #define ALT_GIC_DIST_GICD_ITARGETSR74_RESET 0x00000000
20087 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR74 register from the beginning of the component. */
20088 #define ALT_GIC_DIST_GICD_ITARGETSR74_OFST 0x928
20089 
20090 /*
20091  * Register : GICD_ITARGETSR75
20092  *
20093  * Interrupt Processor Targets Registers
20094  *
20095  * Register Layout
20096  *
20097  * Bits | Access | Reset | Description
20098  * :-------|:-------|:------|:------------
20099  * [31:0] | RW | 0x0 | Empty
20100  *
20101  */
20102 /*
20103  * Field : Empty - fld
20104  *
20105  * Placeholder
20106  *
20107  * Field Access Macros:
20108  *
20109  */
20110 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR75_FLD register field. */
20111 #define ALT_GIC_DIST_GICD_ITARGETSR75_FLD_LSB 0
20112 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR75_FLD register field. */
20113 #define ALT_GIC_DIST_GICD_ITARGETSR75_FLD_MSB 31
20114 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR75_FLD register field. */
20115 #define ALT_GIC_DIST_GICD_ITARGETSR75_FLD_WIDTH 32
20116 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR75_FLD register field value. */
20117 #define ALT_GIC_DIST_GICD_ITARGETSR75_FLD_SET_MSK 0xffffffff
20118 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR75_FLD register field value. */
20119 #define ALT_GIC_DIST_GICD_ITARGETSR75_FLD_CLR_MSK 0x00000000
20120 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR75_FLD register field. */
20121 #define ALT_GIC_DIST_GICD_ITARGETSR75_FLD_RESET 0x0
20122 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR75_FLD field value from a register. */
20123 #define ALT_GIC_DIST_GICD_ITARGETSR75_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20124 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR75_FLD register field value suitable for setting the register. */
20125 #define ALT_GIC_DIST_GICD_ITARGETSR75_FLD_SET(value) (((value) << 0) & 0xffffffff)
20126 
20127 #ifndef __ASSEMBLY__
20128 /*
20129  * WARNING: The C register and register group struct declarations are provided for
20130  * convenience and illustrative purposes. They should, however, be used with
20131  * caution as the C language standard provides no guarantees about the alignment or
20132  * atomicity of device memory accesses. The recommended practice for coding device
20133  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
20134  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
20135  * alt_write_dword() functions for 64 bit registers.
20136  *
20137  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR75.
20138  */
20139 struct ALT_GIC_DIST_GICD_ITARGETSR75_s
20140 {
20141  volatile uint32_t fld : 32; /* Empty */
20142 };
20143 
20144 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR75. */
20145 typedef struct ALT_GIC_DIST_GICD_ITARGETSR75_s ALT_GIC_DIST_GICD_ITARGETSR75_t;
20146 #endif /* __ASSEMBLY__ */
20147 
20148 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR75 register. */
20149 #define ALT_GIC_DIST_GICD_ITARGETSR75_RESET 0x00000000
20150 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR75 register from the beginning of the component. */
20151 #define ALT_GIC_DIST_GICD_ITARGETSR75_OFST 0x92c
20152 
20153 /*
20154  * Register : GICD_ITARGETSR76
20155  *
20156  * Interrupt Processor Targets Registers
20157  *
20158  * Register Layout
20159  *
20160  * Bits | Access | Reset | Description
20161  * :-------|:-------|:------|:------------
20162  * [31:0] | RW | 0x0 | Empty
20163  *
20164  */
20165 /*
20166  * Field : Empty - fld
20167  *
20168  * Placeholder
20169  *
20170  * Field Access Macros:
20171  *
20172  */
20173 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR76_FLD register field. */
20174 #define ALT_GIC_DIST_GICD_ITARGETSR76_FLD_LSB 0
20175 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR76_FLD register field. */
20176 #define ALT_GIC_DIST_GICD_ITARGETSR76_FLD_MSB 31
20177 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR76_FLD register field. */
20178 #define ALT_GIC_DIST_GICD_ITARGETSR76_FLD_WIDTH 32
20179 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR76_FLD register field value. */
20180 #define ALT_GIC_DIST_GICD_ITARGETSR76_FLD_SET_MSK 0xffffffff
20181 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR76_FLD register field value. */
20182 #define ALT_GIC_DIST_GICD_ITARGETSR76_FLD_CLR_MSK 0x00000000
20183 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR76_FLD register field. */
20184 #define ALT_GIC_DIST_GICD_ITARGETSR76_FLD_RESET 0x0
20185 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR76_FLD field value from a register. */
20186 #define ALT_GIC_DIST_GICD_ITARGETSR76_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20187 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR76_FLD register field value suitable for setting the register. */
20188 #define ALT_GIC_DIST_GICD_ITARGETSR76_FLD_SET(value) (((value) << 0) & 0xffffffff)
20189 
20190 #ifndef __ASSEMBLY__
20191 /*
20192  * WARNING: The C register and register group struct declarations are provided for
20193  * convenience and illustrative purposes. They should, however, be used with
20194  * caution as the C language standard provides no guarantees about the alignment or
20195  * atomicity of device memory accesses. The recommended practice for coding device
20196  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
20197  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
20198  * alt_write_dword() functions for 64 bit registers.
20199  *
20200  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR76.
20201  */
20202 struct ALT_GIC_DIST_GICD_ITARGETSR76_s
20203 {
20204  volatile uint32_t fld : 32; /* Empty */
20205 };
20206 
20207 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR76. */
20208 typedef struct ALT_GIC_DIST_GICD_ITARGETSR76_s ALT_GIC_DIST_GICD_ITARGETSR76_t;
20209 #endif /* __ASSEMBLY__ */
20210 
20211 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR76 register. */
20212 #define ALT_GIC_DIST_GICD_ITARGETSR76_RESET 0x00000000
20213 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR76 register from the beginning of the component. */
20214 #define ALT_GIC_DIST_GICD_ITARGETSR76_OFST 0x930
20215 
20216 /*
20217  * Register : GICD_ITARGETSR77
20218  *
20219  * Interrupt Processor Targets Registers
20220  *
20221  * Register Layout
20222  *
20223  * Bits | Access | Reset | Description
20224  * :-------|:-------|:------|:------------
20225  * [31:0] | RW | 0x0 | Empty
20226  *
20227  */
20228 /*
20229  * Field : Empty - fld
20230  *
20231  * Placeholder
20232  *
20233  * Field Access Macros:
20234  *
20235  */
20236 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR77_FLD register field. */
20237 #define ALT_GIC_DIST_GICD_ITARGETSR77_FLD_LSB 0
20238 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR77_FLD register field. */
20239 #define ALT_GIC_DIST_GICD_ITARGETSR77_FLD_MSB 31
20240 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR77_FLD register field. */
20241 #define ALT_GIC_DIST_GICD_ITARGETSR77_FLD_WIDTH 32
20242 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR77_FLD register field value. */
20243 #define ALT_GIC_DIST_GICD_ITARGETSR77_FLD_SET_MSK 0xffffffff
20244 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR77_FLD register field value. */
20245 #define ALT_GIC_DIST_GICD_ITARGETSR77_FLD_CLR_MSK 0x00000000
20246 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR77_FLD register field. */
20247 #define ALT_GIC_DIST_GICD_ITARGETSR77_FLD_RESET 0x0
20248 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR77_FLD field value from a register. */
20249 #define ALT_GIC_DIST_GICD_ITARGETSR77_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20250 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR77_FLD register field value suitable for setting the register. */
20251 #define ALT_GIC_DIST_GICD_ITARGETSR77_FLD_SET(value) (((value) << 0) & 0xffffffff)
20252 
20253 #ifndef __ASSEMBLY__
20254 /*
20255  * WARNING: The C register and register group struct declarations are provided for
20256  * convenience and illustrative purposes. They should, however, be used with
20257  * caution as the C language standard provides no guarantees about the alignment or
20258  * atomicity of device memory accesses. The recommended practice for coding device
20259  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
20260  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
20261  * alt_write_dword() functions for 64 bit registers.
20262  *
20263  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR77.
20264  */
20265 struct ALT_GIC_DIST_GICD_ITARGETSR77_s
20266 {
20267  volatile uint32_t fld : 32; /* Empty */
20268 };
20269 
20270 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR77. */
20271 typedef struct ALT_GIC_DIST_GICD_ITARGETSR77_s ALT_GIC_DIST_GICD_ITARGETSR77_t;
20272 #endif /* __ASSEMBLY__ */
20273 
20274 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR77 register. */
20275 #define ALT_GIC_DIST_GICD_ITARGETSR77_RESET 0x00000000
20276 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR77 register from the beginning of the component. */
20277 #define ALT_GIC_DIST_GICD_ITARGETSR77_OFST 0x934
20278 
20279 /*
20280  * Register : GICD_ITARGETSR78
20281  *
20282  * Interrupt Processor Targets Registers
20283  *
20284  * Register Layout
20285  *
20286  * Bits | Access | Reset | Description
20287  * :-------|:-------|:------|:------------
20288  * [31:0] | RW | 0x0 | Empty
20289  *
20290  */
20291 /*
20292  * Field : Empty - fld
20293  *
20294  * Placeholder
20295  *
20296  * Field Access Macros:
20297  *
20298  */
20299 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR78_FLD register field. */
20300 #define ALT_GIC_DIST_GICD_ITARGETSR78_FLD_LSB 0
20301 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR78_FLD register field. */
20302 #define ALT_GIC_DIST_GICD_ITARGETSR78_FLD_MSB 31
20303 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR78_FLD register field. */
20304 #define ALT_GIC_DIST_GICD_ITARGETSR78_FLD_WIDTH 32
20305 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR78_FLD register field value. */
20306 #define ALT_GIC_DIST_GICD_ITARGETSR78_FLD_SET_MSK 0xffffffff
20307 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR78_FLD register field value. */
20308 #define ALT_GIC_DIST_GICD_ITARGETSR78_FLD_CLR_MSK 0x00000000
20309 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR78_FLD register field. */
20310 #define ALT_GIC_DIST_GICD_ITARGETSR78_FLD_RESET 0x0
20311 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR78_FLD field value from a register. */
20312 #define ALT_GIC_DIST_GICD_ITARGETSR78_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20313 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR78_FLD register field value suitable for setting the register. */
20314 #define ALT_GIC_DIST_GICD_ITARGETSR78_FLD_SET(value) (((value) << 0) & 0xffffffff)
20315 
20316 #ifndef __ASSEMBLY__
20317 /*
20318  * WARNING: The C register and register group struct declarations are provided for
20319  * convenience and illustrative purposes. They should, however, be used with
20320  * caution as the C language standard provides no guarantees about the alignment or
20321  * atomicity of device memory accesses. The recommended practice for coding device
20322  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
20323  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
20324  * alt_write_dword() functions for 64 bit registers.
20325  *
20326  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR78.
20327  */
20328 struct ALT_GIC_DIST_GICD_ITARGETSR78_s
20329 {
20330  volatile uint32_t fld : 32; /* Empty */
20331 };
20332 
20333 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR78. */
20334 typedef struct ALT_GIC_DIST_GICD_ITARGETSR78_s ALT_GIC_DIST_GICD_ITARGETSR78_t;
20335 #endif /* __ASSEMBLY__ */
20336 
20337 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR78 register. */
20338 #define ALT_GIC_DIST_GICD_ITARGETSR78_RESET 0x00000000
20339 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR78 register from the beginning of the component. */
20340 #define ALT_GIC_DIST_GICD_ITARGETSR78_OFST 0x938
20341 
20342 /*
20343  * Register : GICD_ITARGETSR79
20344  *
20345  * Interrupt Processor Targets Registers
20346  *
20347  * Register Layout
20348  *
20349  * Bits | Access | Reset | Description
20350  * :-------|:-------|:------|:------------
20351  * [31:0] | RW | 0x0 | Empty
20352  *
20353  */
20354 /*
20355  * Field : Empty - fld
20356  *
20357  * Placeholder
20358  *
20359  * Field Access Macros:
20360  *
20361  */
20362 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR79_FLD register field. */
20363 #define ALT_GIC_DIST_GICD_ITARGETSR79_FLD_LSB 0
20364 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR79_FLD register field. */
20365 #define ALT_GIC_DIST_GICD_ITARGETSR79_FLD_MSB 31
20366 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR79_FLD register field. */
20367 #define ALT_GIC_DIST_GICD_ITARGETSR79_FLD_WIDTH 32
20368 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR79_FLD register field value. */
20369 #define ALT_GIC_DIST_GICD_ITARGETSR79_FLD_SET_MSK 0xffffffff
20370 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR79_FLD register field value. */
20371 #define ALT_GIC_DIST_GICD_ITARGETSR79_FLD_CLR_MSK 0x00000000
20372 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR79_FLD register field. */
20373 #define ALT_GIC_DIST_GICD_ITARGETSR79_FLD_RESET 0x0
20374 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR79_FLD field value from a register. */
20375 #define ALT_GIC_DIST_GICD_ITARGETSR79_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20376 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR79_FLD register field value suitable for setting the register. */
20377 #define ALT_GIC_DIST_GICD_ITARGETSR79_FLD_SET(value) (((value) << 0) & 0xffffffff)
20378 
20379 #ifndef __ASSEMBLY__
20380 /*
20381  * WARNING: The C register and register group struct declarations are provided for
20382  * convenience and illustrative purposes. They should, however, be used with
20383  * caution as the C language standard provides no guarantees about the alignment or
20384  * atomicity of device memory accesses. The recommended practice for coding device
20385  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
20386  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
20387  * alt_write_dword() functions for 64 bit registers.
20388  *
20389  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR79.
20390  */
20391 struct ALT_GIC_DIST_GICD_ITARGETSR79_s
20392 {
20393  volatile uint32_t fld : 32; /* Empty */
20394 };
20395 
20396 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR79. */
20397 typedef struct ALT_GIC_DIST_GICD_ITARGETSR79_s ALT_GIC_DIST_GICD_ITARGETSR79_t;
20398 #endif /* __ASSEMBLY__ */
20399 
20400 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR79 register. */
20401 #define ALT_GIC_DIST_GICD_ITARGETSR79_RESET 0x00000000
20402 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR79 register from the beginning of the component. */
20403 #define ALT_GIC_DIST_GICD_ITARGETSR79_OFST 0x93c
20404 
20405 /*
20406  * Register : GICD_ITARGETSR80
20407  *
20408  * Interrupt Processor Targets Registers
20409  *
20410  * Register Layout
20411  *
20412  * Bits | Access | Reset | Description
20413  * :-------|:-------|:------|:------------
20414  * [31:0] | RW | 0x0 | Empty
20415  *
20416  */
20417 /*
20418  * Field : Empty - fld
20419  *
20420  * Placeholder
20421  *
20422  * Field Access Macros:
20423  *
20424  */
20425 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR80_FLD register field. */
20426 #define ALT_GIC_DIST_GICD_ITARGETSR80_FLD_LSB 0
20427 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR80_FLD register field. */
20428 #define ALT_GIC_DIST_GICD_ITARGETSR80_FLD_MSB 31
20429 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR80_FLD register field. */
20430 #define ALT_GIC_DIST_GICD_ITARGETSR80_FLD_WIDTH 32
20431 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR80_FLD register field value. */
20432 #define ALT_GIC_DIST_GICD_ITARGETSR80_FLD_SET_MSK 0xffffffff
20433 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR80_FLD register field value. */
20434 #define ALT_GIC_DIST_GICD_ITARGETSR80_FLD_CLR_MSK 0x00000000
20435 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR80_FLD register field. */
20436 #define ALT_GIC_DIST_GICD_ITARGETSR80_FLD_RESET 0x0
20437 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR80_FLD field value from a register. */
20438 #define ALT_GIC_DIST_GICD_ITARGETSR80_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20439 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR80_FLD register field value suitable for setting the register. */
20440 #define ALT_GIC_DIST_GICD_ITARGETSR80_FLD_SET(value) (((value) << 0) & 0xffffffff)
20441 
20442 #ifndef __ASSEMBLY__
20443 /*
20444  * WARNING: The C register and register group struct declarations are provided for
20445  * convenience and illustrative purposes. They should, however, be used with
20446  * caution as the C language standard provides no guarantees about the alignment or
20447  * atomicity of device memory accesses. The recommended practice for coding device
20448  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
20449  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
20450  * alt_write_dword() functions for 64 bit registers.
20451  *
20452  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR80.
20453  */
20454 struct ALT_GIC_DIST_GICD_ITARGETSR80_s
20455 {
20456  volatile uint32_t fld : 32; /* Empty */
20457 };
20458 
20459 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR80. */
20460 typedef struct ALT_GIC_DIST_GICD_ITARGETSR80_s ALT_GIC_DIST_GICD_ITARGETSR80_t;
20461 #endif /* __ASSEMBLY__ */
20462 
20463 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR80 register. */
20464 #define ALT_GIC_DIST_GICD_ITARGETSR80_RESET 0x00000000
20465 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR80 register from the beginning of the component. */
20466 #define ALT_GIC_DIST_GICD_ITARGETSR80_OFST 0x940
20467 
20468 /*
20469  * Register : GICD_ITARGETSR81
20470  *
20471  * Interrupt Processor Targets Registers
20472  *
20473  * Register Layout
20474  *
20475  * Bits | Access | Reset | Description
20476  * :-------|:-------|:------|:------------
20477  * [31:0] | RW | 0x0 | Empty
20478  *
20479  */
20480 /*
20481  * Field : Empty - fld
20482  *
20483  * Placeholder
20484  *
20485  * Field Access Macros:
20486  *
20487  */
20488 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR81_FLD register field. */
20489 #define ALT_GIC_DIST_GICD_ITARGETSR81_FLD_LSB 0
20490 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR81_FLD register field. */
20491 #define ALT_GIC_DIST_GICD_ITARGETSR81_FLD_MSB 31
20492 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR81_FLD register field. */
20493 #define ALT_GIC_DIST_GICD_ITARGETSR81_FLD_WIDTH 32
20494 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR81_FLD register field value. */
20495 #define ALT_GIC_DIST_GICD_ITARGETSR81_FLD_SET_MSK 0xffffffff
20496 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR81_FLD register field value. */
20497 #define ALT_GIC_DIST_GICD_ITARGETSR81_FLD_CLR_MSK 0x00000000
20498 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR81_FLD register field. */
20499 #define ALT_GIC_DIST_GICD_ITARGETSR81_FLD_RESET 0x0
20500 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR81_FLD field value from a register. */
20501 #define ALT_GIC_DIST_GICD_ITARGETSR81_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20502 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR81_FLD register field value suitable for setting the register. */
20503 #define ALT_GIC_DIST_GICD_ITARGETSR81_FLD_SET(value) (((value) << 0) & 0xffffffff)
20504 
20505 #ifndef __ASSEMBLY__
20506 /*
20507  * WARNING: The C register and register group struct declarations are provided for
20508  * convenience and illustrative purposes. They should, however, be used with
20509  * caution as the C language standard provides no guarantees about the alignment or
20510  * atomicity of device memory accesses. The recommended practice for coding device
20511  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
20512  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
20513  * alt_write_dword() functions for 64 bit registers.
20514  *
20515  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR81.
20516  */
20517 struct ALT_GIC_DIST_GICD_ITARGETSR81_s
20518 {
20519  volatile uint32_t fld : 32; /* Empty */
20520 };
20521 
20522 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR81. */
20523 typedef struct ALT_GIC_DIST_GICD_ITARGETSR81_s ALT_GIC_DIST_GICD_ITARGETSR81_t;
20524 #endif /* __ASSEMBLY__ */
20525 
20526 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR81 register. */
20527 #define ALT_GIC_DIST_GICD_ITARGETSR81_RESET 0x00000000
20528 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR81 register from the beginning of the component. */
20529 #define ALT_GIC_DIST_GICD_ITARGETSR81_OFST 0x944
20530 
20531 /*
20532  * Register : GICD_ITARGETSR82
20533  *
20534  * Interrupt Processor Targets Registers
20535  *
20536  * Register Layout
20537  *
20538  * Bits | Access | Reset | Description
20539  * :-------|:-------|:------|:------------
20540  * [31:0] | RW | 0x0 | Empty
20541  *
20542  */
20543 /*
20544  * Field : Empty - fld
20545  *
20546  * Placeholder
20547  *
20548  * Field Access Macros:
20549  *
20550  */
20551 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR82_FLD register field. */
20552 #define ALT_GIC_DIST_GICD_ITARGETSR82_FLD_LSB 0
20553 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR82_FLD register field. */
20554 #define ALT_GIC_DIST_GICD_ITARGETSR82_FLD_MSB 31
20555 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR82_FLD register field. */
20556 #define ALT_GIC_DIST_GICD_ITARGETSR82_FLD_WIDTH 32
20557 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR82_FLD register field value. */
20558 #define ALT_GIC_DIST_GICD_ITARGETSR82_FLD_SET_MSK 0xffffffff
20559 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR82_FLD register field value. */
20560 #define ALT_GIC_DIST_GICD_ITARGETSR82_FLD_CLR_MSK 0x00000000
20561 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR82_FLD register field. */
20562 #define ALT_GIC_DIST_GICD_ITARGETSR82_FLD_RESET 0x0
20563 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR82_FLD field value from a register. */
20564 #define ALT_GIC_DIST_GICD_ITARGETSR82_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20565 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR82_FLD register field value suitable for setting the register. */
20566 #define ALT_GIC_DIST_GICD_ITARGETSR82_FLD_SET(value) (((value) << 0) & 0xffffffff)
20567 
20568 #ifndef __ASSEMBLY__
20569 /*
20570  * WARNING: The C register and register group struct declarations are provided for
20571  * convenience and illustrative purposes. They should, however, be used with
20572  * caution as the C language standard provides no guarantees about the alignment or
20573  * atomicity of device memory accesses. The recommended practice for coding device
20574  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
20575  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
20576  * alt_write_dword() functions for 64 bit registers.
20577  *
20578  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR82.
20579  */
20580 struct ALT_GIC_DIST_GICD_ITARGETSR82_s
20581 {
20582  volatile uint32_t fld : 32; /* Empty */
20583 };
20584 
20585 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR82. */
20586 typedef struct ALT_GIC_DIST_GICD_ITARGETSR82_s ALT_GIC_DIST_GICD_ITARGETSR82_t;
20587 #endif /* __ASSEMBLY__ */
20588 
20589 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR82 register. */
20590 #define ALT_GIC_DIST_GICD_ITARGETSR82_RESET 0x00000000
20591 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR82 register from the beginning of the component. */
20592 #define ALT_GIC_DIST_GICD_ITARGETSR82_OFST 0x948
20593 
20594 /*
20595  * Register : GICD_ITARGETSR83
20596  *
20597  * Interrupt Processor Targets Registers
20598  *
20599  * Register Layout
20600  *
20601  * Bits | Access | Reset | Description
20602  * :-------|:-------|:------|:------------
20603  * [31:0] | RW | 0x0 | Empty
20604  *
20605  */
20606 /*
20607  * Field : Empty - fld
20608  *
20609  * Placeholder
20610  *
20611  * Field Access Macros:
20612  *
20613  */
20614 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR83_FLD register field. */
20615 #define ALT_GIC_DIST_GICD_ITARGETSR83_FLD_LSB 0
20616 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR83_FLD register field. */
20617 #define ALT_GIC_DIST_GICD_ITARGETSR83_FLD_MSB 31
20618 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR83_FLD register field. */
20619 #define ALT_GIC_DIST_GICD_ITARGETSR83_FLD_WIDTH 32
20620 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR83_FLD register field value. */
20621 #define ALT_GIC_DIST_GICD_ITARGETSR83_FLD_SET_MSK 0xffffffff
20622 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR83_FLD register field value. */
20623 #define ALT_GIC_DIST_GICD_ITARGETSR83_FLD_CLR_MSK 0x00000000
20624 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR83_FLD register field. */
20625 #define ALT_GIC_DIST_GICD_ITARGETSR83_FLD_RESET 0x0
20626 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR83_FLD field value from a register. */
20627 #define ALT_GIC_DIST_GICD_ITARGETSR83_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20628 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR83_FLD register field value suitable for setting the register. */
20629 #define ALT_GIC_DIST_GICD_ITARGETSR83_FLD_SET(value) (((value) << 0) & 0xffffffff)
20630 
20631 #ifndef __ASSEMBLY__
20632 /*
20633  * WARNING: The C register and register group struct declarations are provided for
20634  * convenience and illustrative purposes. They should, however, be used with
20635  * caution as the C language standard provides no guarantees about the alignment or
20636  * atomicity of device memory accesses. The recommended practice for coding device
20637  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
20638  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
20639  * alt_write_dword() functions for 64 bit registers.
20640  *
20641  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR83.
20642  */
20643 struct ALT_GIC_DIST_GICD_ITARGETSR83_s
20644 {
20645  volatile uint32_t fld : 32; /* Empty */
20646 };
20647 
20648 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR83. */
20649 typedef struct ALT_GIC_DIST_GICD_ITARGETSR83_s ALT_GIC_DIST_GICD_ITARGETSR83_t;
20650 #endif /* __ASSEMBLY__ */
20651 
20652 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR83 register. */
20653 #define ALT_GIC_DIST_GICD_ITARGETSR83_RESET 0x00000000
20654 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR83 register from the beginning of the component. */
20655 #define ALT_GIC_DIST_GICD_ITARGETSR83_OFST 0x94c
20656 
20657 /*
20658  * Register : GICD_ITARGETSR84
20659  *
20660  * Interrupt Processor Targets Registers
20661  *
20662  * Register Layout
20663  *
20664  * Bits | Access | Reset | Description
20665  * :-------|:-------|:------|:------------
20666  * [31:0] | RW | 0x0 | Empty
20667  *
20668  */
20669 /*
20670  * Field : Empty - fld
20671  *
20672  * Placeholder
20673  *
20674  * Field Access Macros:
20675  *
20676  */
20677 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR84_FLD register field. */
20678 #define ALT_GIC_DIST_GICD_ITARGETSR84_FLD_LSB 0
20679 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR84_FLD register field. */
20680 #define ALT_GIC_DIST_GICD_ITARGETSR84_FLD_MSB 31
20681 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR84_FLD register field. */
20682 #define ALT_GIC_DIST_GICD_ITARGETSR84_FLD_WIDTH 32
20683 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR84_FLD register field value. */
20684 #define ALT_GIC_DIST_GICD_ITARGETSR84_FLD_SET_MSK 0xffffffff
20685 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR84_FLD register field value. */
20686 #define ALT_GIC_DIST_GICD_ITARGETSR84_FLD_CLR_MSK 0x00000000
20687 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR84_FLD register field. */
20688 #define ALT_GIC_DIST_GICD_ITARGETSR84_FLD_RESET 0x0
20689 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR84_FLD field value from a register. */
20690 #define ALT_GIC_DIST_GICD_ITARGETSR84_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20691 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR84_FLD register field value suitable for setting the register. */
20692 #define ALT_GIC_DIST_GICD_ITARGETSR84_FLD_SET(value) (((value) << 0) & 0xffffffff)
20693 
20694 #ifndef __ASSEMBLY__
20695 /*
20696  * WARNING: The C register and register group struct declarations are provided for
20697  * convenience and illustrative purposes. They should, however, be used with
20698  * caution as the C language standard provides no guarantees about the alignment or
20699  * atomicity of device memory accesses. The recommended practice for coding device
20700  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
20701  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
20702  * alt_write_dword() functions for 64 bit registers.
20703  *
20704  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR84.
20705  */
20706 struct ALT_GIC_DIST_GICD_ITARGETSR84_s
20707 {
20708  volatile uint32_t fld : 32; /* Empty */
20709 };
20710 
20711 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR84. */
20712 typedef struct ALT_GIC_DIST_GICD_ITARGETSR84_s ALT_GIC_DIST_GICD_ITARGETSR84_t;
20713 #endif /* __ASSEMBLY__ */
20714 
20715 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR84 register. */
20716 #define ALT_GIC_DIST_GICD_ITARGETSR84_RESET 0x00000000
20717 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR84 register from the beginning of the component. */
20718 #define ALT_GIC_DIST_GICD_ITARGETSR84_OFST 0x950
20719 
20720 /*
20721  * Register : GICD_ITARGETSR85
20722  *
20723  * Interrupt Processor Targets Registers
20724  *
20725  * Register Layout
20726  *
20727  * Bits | Access | Reset | Description
20728  * :-------|:-------|:------|:------------
20729  * [31:0] | RW | 0x0 | Empty
20730  *
20731  */
20732 /*
20733  * Field : Empty - fld
20734  *
20735  * Placeholder
20736  *
20737  * Field Access Macros:
20738  *
20739  */
20740 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR85_FLD register field. */
20741 #define ALT_GIC_DIST_GICD_ITARGETSR85_FLD_LSB 0
20742 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR85_FLD register field. */
20743 #define ALT_GIC_DIST_GICD_ITARGETSR85_FLD_MSB 31
20744 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR85_FLD register field. */
20745 #define ALT_GIC_DIST_GICD_ITARGETSR85_FLD_WIDTH 32
20746 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR85_FLD register field value. */
20747 #define ALT_GIC_DIST_GICD_ITARGETSR85_FLD_SET_MSK 0xffffffff
20748 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR85_FLD register field value. */
20749 #define ALT_GIC_DIST_GICD_ITARGETSR85_FLD_CLR_MSK 0x00000000
20750 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR85_FLD register field. */
20751 #define ALT_GIC_DIST_GICD_ITARGETSR85_FLD_RESET 0x0
20752 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR85_FLD field value from a register. */
20753 #define ALT_GIC_DIST_GICD_ITARGETSR85_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20754 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR85_FLD register field value suitable for setting the register. */
20755 #define ALT_GIC_DIST_GICD_ITARGETSR85_FLD_SET(value) (((value) << 0) & 0xffffffff)
20756 
20757 #ifndef __ASSEMBLY__
20758 /*
20759  * WARNING: The C register and register group struct declarations are provided for
20760  * convenience and illustrative purposes. They should, however, be used with
20761  * caution as the C language standard provides no guarantees about the alignment or
20762  * atomicity of device memory accesses. The recommended practice for coding device
20763  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
20764  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
20765  * alt_write_dword() functions for 64 bit registers.
20766  *
20767  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR85.
20768  */
20769 struct ALT_GIC_DIST_GICD_ITARGETSR85_s
20770 {
20771  volatile uint32_t fld : 32; /* Empty */
20772 };
20773 
20774 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR85. */
20775 typedef struct ALT_GIC_DIST_GICD_ITARGETSR85_s ALT_GIC_DIST_GICD_ITARGETSR85_t;
20776 #endif /* __ASSEMBLY__ */
20777 
20778 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR85 register. */
20779 #define ALT_GIC_DIST_GICD_ITARGETSR85_RESET 0x00000000
20780 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR85 register from the beginning of the component. */
20781 #define ALT_GIC_DIST_GICD_ITARGETSR85_OFST 0x954
20782 
20783 /*
20784  * Register : GICD_ITARGETSR86
20785  *
20786  * Interrupt Processor Targets Registers
20787  *
20788  * Register Layout
20789  *
20790  * Bits | Access | Reset | Description
20791  * :-------|:-------|:------|:------------
20792  * [31:0] | RW | 0x0 | Empty
20793  *
20794  */
20795 /*
20796  * Field : Empty - fld
20797  *
20798  * Placeholder
20799  *
20800  * Field Access Macros:
20801  *
20802  */
20803 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR86_FLD register field. */
20804 #define ALT_GIC_DIST_GICD_ITARGETSR86_FLD_LSB 0
20805 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR86_FLD register field. */
20806 #define ALT_GIC_DIST_GICD_ITARGETSR86_FLD_MSB 31
20807 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR86_FLD register field. */
20808 #define ALT_GIC_DIST_GICD_ITARGETSR86_FLD_WIDTH 32
20809 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR86_FLD register field value. */
20810 #define ALT_GIC_DIST_GICD_ITARGETSR86_FLD_SET_MSK 0xffffffff
20811 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR86_FLD register field value. */
20812 #define ALT_GIC_DIST_GICD_ITARGETSR86_FLD_CLR_MSK 0x00000000
20813 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR86_FLD register field. */
20814 #define ALT_GIC_DIST_GICD_ITARGETSR86_FLD_RESET 0x0
20815 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR86_FLD field value from a register. */
20816 #define ALT_GIC_DIST_GICD_ITARGETSR86_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20817 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR86_FLD register field value suitable for setting the register. */
20818 #define ALT_GIC_DIST_GICD_ITARGETSR86_FLD_SET(value) (((value) << 0) & 0xffffffff)
20819 
20820 #ifndef __ASSEMBLY__
20821 /*
20822  * WARNING: The C register and register group struct declarations are provided for
20823  * convenience and illustrative purposes. They should, however, be used with
20824  * caution as the C language standard provides no guarantees about the alignment or
20825  * atomicity of device memory accesses. The recommended practice for coding device
20826  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
20827  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
20828  * alt_write_dword() functions for 64 bit registers.
20829  *
20830  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR86.
20831  */
20832 struct ALT_GIC_DIST_GICD_ITARGETSR86_s
20833 {
20834  volatile uint32_t fld : 32; /* Empty */
20835 };
20836 
20837 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR86. */
20838 typedef struct ALT_GIC_DIST_GICD_ITARGETSR86_s ALT_GIC_DIST_GICD_ITARGETSR86_t;
20839 #endif /* __ASSEMBLY__ */
20840 
20841 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR86 register. */
20842 #define ALT_GIC_DIST_GICD_ITARGETSR86_RESET 0x00000000
20843 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR86 register from the beginning of the component. */
20844 #define ALT_GIC_DIST_GICD_ITARGETSR86_OFST 0x958
20845 
20846 /*
20847  * Register : GICD_ITARGETSR87
20848  *
20849  * Interrupt Processor Targets Registers
20850  *
20851  * Register Layout
20852  *
20853  * Bits | Access | Reset | Description
20854  * :-------|:-------|:------|:------------
20855  * [31:0] | RW | 0x0 | Empty
20856  *
20857  */
20858 /*
20859  * Field : Empty - fld
20860  *
20861  * Placeholder
20862  *
20863  * Field Access Macros:
20864  *
20865  */
20866 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR87_FLD register field. */
20867 #define ALT_GIC_DIST_GICD_ITARGETSR87_FLD_LSB 0
20868 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR87_FLD register field. */
20869 #define ALT_GIC_DIST_GICD_ITARGETSR87_FLD_MSB 31
20870 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR87_FLD register field. */
20871 #define ALT_GIC_DIST_GICD_ITARGETSR87_FLD_WIDTH 32
20872 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR87_FLD register field value. */
20873 #define ALT_GIC_DIST_GICD_ITARGETSR87_FLD_SET_MSK 0xffffffff
20874 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR87_FLD register field value. */
20875 #define ALT_GIC_DIST_GICD_ITARGETSR87_FLD_CLR_MSK 0x00000000
20876 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR87_FLD register field. */
20877 #define ALT_GIC_DIST_GICD_ITARGETSR87_FLD_RESET 0x0
20878 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR87_FLD field value from a register. */
20879 #define ALT_GIC_DIST_GICD_ITARGETSR87_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20880 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR87_FLD register field value suitable for setting the register. */
20881 #define ALT_GIC_DIST_GICD_ITARGETSR87_FLD_SET(value) (((value) << 0) & 0xffffffff)
20882 
20883 #ifndef __ASSEMBLY__
20884 /*
20885  * WARNING: The C register and register group struct declarations are provided for
20886  * convenience and illustrative purposes. They should, however, be used with
20887  * caution as the C language standard provides no guarantees about the alignment or
20888  * atomicity of device memory accesses. The recommended practice for coding device
20889  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
20890  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
20891  * alt_write_dword() functions for 64 bit registers.
20892  *
20893  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR87.
20894  */
20895 struct ALT_GIC_DIST_GICD_ITARGETSR87_s
20896 {
20897  volatile uint32_t fld : 32; /* Empty */
20898 };
20899 
20900 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR87. */
20901 typedef struct ALT_GIC_DIST_GICD_ITARGETSR87_s ALT_GIC_DIST_GICD_ITARGETSR87_t;
20902 #endif /* __ASSEMBLY__ */
20903 
20904 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR87 register. */
20905 #define ALT_GIC_DIST_GICD_ITARGETSR87_RESET 0x00000000
20906 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR87 register from the beginning of the component. */
20907 #define ALT_GIC_DIST_GICD_ITARGETSR87_OFST 0x95c
20908 
20909 /*
20910  * Register : GICD_ITARGETSR88
20911  *
20912  * Interrupt Processor Targets Registers
20913  *
20914  * Register Layout
20915  *
20916  * Bits | Access | Reset | Description
20917  * :-------|:-------|:------|:------------
20918  * [31:0] | RW | 0x0 | Empty
20919  *
20920  */
20921 /*
20922  * Field : Empty - fld
20923  *
20924  * Placeholder
20925  *
20926  * Field Access Macros:
20927  *
20928  */
20929 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR88_FLD register field. */
20930 #define ALT_GIC_DIST_GICD_ITARGETSR88_FLD_LSB 0
20931 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR88_FLD register field. */
20932 #define ALT_GIC_DIST_GICD_ITARGETSR88_FLD_MSB 31
20933 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR88_FLD register field. */
20934 #define ALT_GIC_DIST_GICD_ITARGETSR88_FLD_WIDTH 32
20935 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR88_FLD register field value. */
20936 #define ALT_GIC_DIST_GICD_ITARGETSR88_FLD_SET_MSK 0xffffffff
20937 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR88_FLD register field value. */
20938 #define ALT_GIC_DIST_GICD_ITARGETSR88_FLD_CLR_MSK 0x00000000
20939 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR88_FLD register field. */
20940 #define ALT_GIC_DIST_GICD_ITARGETSR88_FLD_RESET 0x0
20941 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR88_FLD field value from a register. */
20942 #define ALT_GIC_DIST_GICD_ITARGETSR88_FLD_GET(value) (((value) & 0xffffffff) >> 0)
20943 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR88_FLD register field value suitable for setting the register. */
20944 #define ALT_GIC_DIST_GICD_ITARGETSR88_FLD_SET(value) (((value) << 0) & 0xffffffff)
20945 
20946 #ifndef __ASSEMBLY__
20947 /*
20948  * WARNING: The C register and register group struct declarations are provided for
20949  * convenience and illustrative purposes. They should, however, be used with
20950  * caution as the C language standard provides no guarantees about the alignment or
20951  * atomicity of device memory accesses. The recommended practice for coding device
20952  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
20953  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
20954  * alt_write_dword() functions for 64 bit registers.
20955  *
20956  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR88.
20957  */
20958 struct ALT_GIC_DIST_GICD_ITARGETSR88_s
20959 {
20960  volatile uint32_t fld : 32; /* Empty */
20961 };
20962 
20963 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR88. */
20964 typedef struct ALT_GIC_DIST_GICD_ITARGETSR88_s ALT_GIC_DIST_GICD_ITARGETSR88_t;
20965 #endif /* __ASSEMBLY__ */
20966 
20967 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR88 register. */
20968 #define ALT_GIC_DIST_GICD_ITARGETSR88_RESET 0x00000000
20969 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR88 register from the beginning of the component. */
20970 #define ALT_GIC_DIST_GICD_ITARGETSR88_OFST 0x960
20971 
20972 /*
20973  * Register : GICD_ITARGETSR89
20974  *
20975  * Interrupt Processor Targets Registers
20976  *
20977  * Register Layout
20978  *
20979  * Bits | Access | Reset | Description
20980  * :-------|:-------|:------|:------------
20981  * [31:0] | RW | 0x0 | Empty
20982  *
20983  */
20984 /*
20985  * Field : Empty - fld
20986  *
20987  * Placeholder
20988  *
20989  * Field Access Macros:
20990  *
20991  */
20992 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR89_FLD register field. */
20993 #define ALT_GIC_DIST_GICD_ITARGETSR89_FLD_LSB 0
20994 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR89_FLD register field. */
20995 #define ALT_GIC_DIST_GICD_ITARGETSR89_FLD_MSB 31
20996 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR89_FLD register field. */
20997 #define ALT_GIC_DIST_GICD_ITARGETSR89_FLD_WIDTH 32
20998 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR89_FLD register field value. */
20999 #define ALT_GIC_DIST_GICD_ITARGETSR89_FLD_SET_MSK 0xffffffff
21000 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR89_FLD register field value. */
21001 #define ALT_GIC_DIST_GICD_ITARGETSR89_FLD_CLR_MSK 0x00000000
21002 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR89_FLD register field. */
21003 #define ALT_GIC_DIST_GICD_ITARGETSR89_FLD_RESET 0x0
21004 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR89_FLD field value from a register. */
21005 #define ALT_GIC_DIST_GICD_ITARGETSR89_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21006 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR89_FLD register field value suitable for setting the register. */
21007 #define ALT_GIC_DIST_GICD_ITARGETSR89_FLD_SET(value) (((value) << 0) & 0xffffffff)
21008 
21009 #ifndef __ASSEMBLY__
21010 /*
21011  * WARNING: The C register and register group struct declarations are provided for
21012  * convenience and illustrative purposes. They should, however, be used with
21013  * caution as the C language standard provides no guarantees about the alignment or
21014  * atomicity of device memory accesses. The recommended practice for coding device
21015  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21016  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21017  * alt_write_dword() functions for 64 bit registers.
21018  *
21019  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR89.
21020  */
21021 struct ALT_GIC_DIST_GICD_ITARGETSR89_s
21022 {
21023  volatile uint32_t fld : 32; /* Empty */
21024 };
21025 
21026 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR89. */
21027 typedef struct ALT_GIC_DIST_GICD_ITARGETSR89_s ALT_GIC_DIST_GICD_ITARGETSR89_t;
21028 #endif /* __ASSEMBLY__ */
21029 
21030 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR89 register. */
21031 #define ALT_GIC_DIST_GICD_ITARGETSR89_RESET 0x00000000
21032 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR89 register from the beginning of the component. */
21033 #define ALT_GIC_DIST_GICD_ITARGETSR89_OFST 0x964
21034 
21035 /*
21036  * Register : GICD_ITARGETSR90
21037  *
21038  * Interrupt Processor Targets Registers
21039  *
21040  * Register Layout
21041  *
21042  * Bits | Access | Reset | Description
21043  * :-------|:-------|:------|:------------
21044  * [31:0] | RW | 0x0 | Empty
21045  *
21046  */
21047 /*
21048  * Field : Empty - fld
21049  *
21050  * Placeholder
21051  *
21052  * Field Access Macros:
21053  *
21054  */
21055 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR90_FLD register field. */
21056 #define ALT_GIC_DIST_GICD_ITARGETSR90_FLD_LSB 0
21057 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR90_FLD register field. */
21058 #define ALT_GIC_DIST_GICD_ITARGETSR90_FLD_MSB 31
21059 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR90_FLD register field. */
21060 #define ALT_GIC_DIST_GICD_ITARGETSR90_FLD_WIDTH 32
21061 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR90_FLD register field value. */
21062 #define ALT_GIC_DIST_GICD_ITARGETSR90_FLD_SET_MSK 0xffffffff
21063 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR90_FLD register field value. */
21064 #define ALT_GIC_DIST_GICD_ITARGETSR90_FLD_CLR_MSK 0x00000000
21065 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR90_FLD register field. */
21066 #define ALT_GIC_DIST_GICD_ITARGETSR90_FLD_RESET 0x0
21067 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR90_FLD field value from a register. */
21068 #define ALT_GIC_DIST_GICD_ITARGETSR90_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21069 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR90_FLD register field value suitable for setting the register. */
21070 #define ALT_GIC_DIST_GICD_ITARGETSR90_FLD_SET(value) (((value) << 0) & 0xffffffff)
21071 
21072 #ifndef __ASSEMBLY__
21073 /*
21074  * WARNING: The C register and register group struct declarations are provided for
21075  * convenience and illustrative purposes. They should, however, be used with
21076  * caution as the C language standard provides no guarantees about the alignment or
21077  * atomicity of device memory accesses. The recommended practice for coding device
21078  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21079  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21080  * alt_write_dword() functions for 64 bit registers.
21081  *
21082  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR90.
21083  */
21084 struct ALT_GIC_DIST_GICD_ITARGETSR90_s
21085 {
21086  volatile uint32_t fld : 32; /* Empty */
21087 };
21088 
21089 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR90. */
21090 typedef struct ALT_GIC_DIST_GICD_ITARGETSR90_s ALT_GIC_DIST_GICD_ITARGETSR90_t;
21091 #endif /* __ASSEMBLY__ */
21092 
21093 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR90 register. */
21094 #define ALT_GIC_DIST_GICD_ITARGETSR90_RESET 0x00000000
21095 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR90 register from the beginning of the component. */
21096 #define ALT_GIC_DIST_GICD_ITARGETSR90_OFST 0x968
21097 
21098 /*
21099  * Register : GICD_ITARGETSR91
21100  *
21101  * Interrupt Processor Targets Registers
21102  *
21103  * Register Layout
21104  *
21105  * Bits | Access | Reset | Description
21106  * :-------|:-------|:------|:------------
21107  * [31:0] | RW | 0x0 | Empty
21108  *
21109  */
21110 /*
21111  * Field : Empty - fld
21112  *
21113  * Placeholder
21114  *
21115  * Field Access Macros:
21116  *
21117  */
21118 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR91_FLD register field. */
21119 #define ALT_GIC_DIST_GICD_ITARGETSR91_FLD_LSB 0
21120 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR91_FLD register field. */
21121 #define ALT_GIC_DIST_GICD_ITARGETSR91_FLD_MSB 31
21122 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR91_FLD register field. */
21123 #define ALT_GIC_DIST_GICD_ITARGETSR91_FLD_WIDTH 32
21124 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR91_FLD register field value. */
21125 #define ALT_GIC_DIST_GICD_ITARGETSR91_FLD_SET_MSK 0xffffffff
21126 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR91_FLD register field value. */
21127 #define ALT_GIC_DIST_GICD_ITARGETSR91_FLD_CLR_MSK 0x00000000
21128 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR91_FLD register field. */
21129 #define ALT_GIC_DIST_GICD_ITARGETSR91_FLD_RESET 0x0
21130 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR91_FLD field value from a register. */
21131 #define ALT_GIC_DIST_GICD_ITARGETSR91_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21132 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR91_FLD register field value suitable for setting the register. */
21133 #define ALT_GIC_DIST_GICD_ITARGETSR91_FLD_SET(value) (((value) << 0) & 0xffffffff)
21134 
21135 #ifndef __ASSEMBLY__
21136 /*
21137  * WARNING: The C register and register group struct declarations are provided for
21138  * convenience and illustrative purposes. They should, however, be used with
21139  * caution as the C language standard provides no guarantees about the alignment or
21140  * atomicity of device memory accesses. The recommended practice for coding device
21141  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21142  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21143  * alt_write_dword() functions for 64 bit registers.
21144  *
21145  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR91.
21146  */
21147 struct ALT_GIC_DIST_GICD_ITARGETSR91_s
21148 {
21149  volatile uint32_t fld : 32; /* Empty */
21150 };
21151 
21152 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR91. */
21153 typedef struct ALT_GIC_DIST_GICD_ITARGETSR91_s ALT_GIC_DIST_GICD_ITARGETSR91_t;
21154 #endif /* __ASSEMBLY__ */
21155 
21156 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR91 register. */
21157 #define ALT_GIC_DIST_GICD_ITARGETSR91_RESET 0x00000000
21158 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR91 register from the beginning of the component. */
21159 #define ALT_GIC_DIST_GICD_ITARGETSR91_OFST 0x96c
21160 
21161 /*
21162  * Register : GICD_ITARGETSR92
21163  *
21164  * Interrupt Processor Targets Registers
21165  *
21166  * Register Layout
21167  *
21168  * Bits | Access | Reset | Description
21169  * :-------|:-------|:------|:------------
21170  * [31:0] | RW | 0x0 | Empty
21171  *
21172  */
21173 /*
21174  * Field : Empty - fld
21175  *
21176  * Placeholder
21177  *
21178  * Field Access Macros:
21179  *
21180  */
21181 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR92_FLD register field. */
21182 #define ALT_GIC_DIST_GICD_ITARGETSR92_FLD_LSB 0
21183 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR92_FLD register field. */
21184 #define ALT_GIC_DIST_GICD_ITARGETSR92_FLD_MSB 31
21185 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR92_FLD register field. */
21186 #define ALT_GIC_DIST_GICD_ITARGETSR92_FLD_WIDTH 32
21187 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR92_FLD register field value. */
21188 #define ALT_GIC_DIST_GICD_ITARGETSR92_FLD_SET_MSK 0xffffffff
21189 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR92_FLD register field value. */
21190 #define ALT_GIC_DIST_GICD_ITARGETSR92_FLD_CLR_MSK 0x00000000
21191 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR92_FLD register field. */
21192 #define ALT_GIC_DIST_GICD_ITARGETSR92_FLD_RESET 0x0
21193 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR92_FLD field value from a register. */
21194 #define ALT_GIC_DIST_GICD_ITARGETSR92_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21195 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR92_FLD register field value suitable for setting the register. */
21196 #define ALT_GIC_DIST_GICD_ITARGETSR92_FLD_SET(value) (((value) << 0) & 0xffffffff)
21197 
21198 #ifndef __ASSEMBLY__
21199 /*
21200  * WARNING: The C register and register group struct declarations are provided for
21201  * convenience and illustrative purposes. They should, however, be used with
21202  * caution as the C language standard provides no guarantees about the alignment or
21203  * atomicity of device memory accesses. The recommended practice for coding device
21204  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21205  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21206  * alt_write_dword() functions for 64 bit registers.
21207  *
21208  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR92.
21209  */
21210 struct ALT_GIC_DIST_GICD_ITARGETSR92_s
21211 {
21212  volatile uint32_t fld : 32; /* Empty */
21213 };
21214 
21215 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR92. */
21216 typedef struct ALT_GIC_DIST_GICD_ITARGETSR92_s ALT_GIC_DIST_GICD_ITARGETSR92_t;
21217 #endif /* __ASSEMBLY__ */
21218 
21219 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR92 register. */
21220 #define ALT_GIC_DIST_GICD_ITARGETSR92_RESET 0x00000000
21221 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR92 register from the beginning of the component. */
21222 #define ALT_GIC_DIST_GICD_ITARGETSR92_OFST 0x970
21223 
21224 /*
21225  * Register : GICD_ITARGETSR93
21226  *
21227  * Interrupt Processor Targets Registers
21228  *
21229  * Register Layout
21230  *
21231  * Bits | Access | Reset | Description
21232  * :-------|:-------|:------|:------------
21233  * [31:0] | RW | 0x0 | Empty
21234  *
21235  */
21236 /*
21237  * Field : Empty - fld
21238  *
21239  * Placeholder
21240  *
21241  * Field Access Macros:
21242  *
21243  */
21244 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR93_FLD register field. */
21245 #define ALT_GIC_DIST_GICD_ITARGETSR93_FLD_LSB 0
21246 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR93_FLD register field. */
21247 #define ALT_GIC_DIST_GICD_ITARGETSR93_FLD_MSB 31
21248 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR93_FLD register field. */
21249 #define ALT_GIC_DIST_GICD_ITARGETSR93_FLD_WIDTH 32
21250 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR93_FLD register field value. */
21251 #define ALT_GIC_DIST_GICD_ITARGETSR93_FLD_SET_MSK 0xffffffff
21252 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR93_FLD register field value. */
21253 #define ALT_GIC_DIST_GICD_ITARGETSR93_FLD_CLR_MSK 0x00000000
21254 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR93_FLD register field. */
21255 #define ALT_GIC_DIST_GICD_ITARGETSR93_FLD_RESET 0x0
21256 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR93_FLD field value from a register. */
21257 #define ALT_GIC_DIST_GICD_ITARGETSR93_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21258 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR93_FLD register field value suitable for setting the register. */
21259 #define ALT_GIC_DIST_GICD_ITARGETSR93_FLD_SET(value) (((value) << 0) & 0xffffffff)
21260 
21261 #ifndef __ASSEMBLY__
21262 /*
21263  * WARNING: The C register and register group struct declarations are provided for
21264  * convenience and illustrative purposes. They should, however, be used with
21265  * caution as the C language standard provides no guarantees about the alignment or
21266  * atomicity of device memory accesses. The recommended practice for coding device
21267  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21268  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21269  * alt_write_dword() functions for 64 bit registers.
21270  *
21271  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR93.
21272  */
21273 struct ALT_GIC_DIST_GICD_ITARGETSR93_s
21274 {
21275  volatile uint32_t fld : 32; /* Empty */
21276 };
21277 
21278 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR93. */
21279 typedef struct ALT_GIC_DIST_GICD_ITARGETSR93_s ALT_GIC_DIST_GICD_ITARGETSR93_t;
21280 #endif /* __ASSEMBLY__ */
21281 
21282 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR93 register. */
21283 #define ALT_GIC_DIST_GICD_ITARGETSR93_RESET 0x00000000
21284 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR93 register from the beginning of the component. */
21285 #define ALT_GIC_DIST_GICD_ITARGETSR93_OFST 0x974
21286 
21287 /*
21288  * Register : GICD_ITARGETSR94
21289  *
21290  * Interrupt Processor Targets Registers
21291  *
21292  * Register Layout
21293  *
21294  * Bits | Access | Reset | Description
21295  * :-------|:-------|:------|:------------
21296  * [31:0] | RW | 0x0 | Empty
21297  *
21298  */
21299 /*
21300  * Field : Empty - fld
21301  *
21302  * Placeholder
21303  *
21304  * Field Access Macros:
21305  *
21306  */
21307 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR94_FLD register field. */
21308 #define ALT_GIC_DIST_GICD_ITARGETSR94_FLD_LSB 0
21309 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR94_FLD register field. */
21310 #define ALT_GIC_DIST_GICD_ITARGETSR94_FLD_MSB 31
21311 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR94_FLD register field. */
21312 #define ALT_GIC_DIST_GICD_ITARGETSR94_FLD_WIDTH 32
21313 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR94_FLD register field value. */
21314 #define ALT_GIC_DIST_GICD_ITARGETSR94_FLD_SET_MSK 0xffffffff
21315 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR94_FLD register field value. */
21316 #define ALT_GIC_DIST_GICD_ITARGETSR94_FLD_CLR_MSK 0x00000000
21317 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR94_FLD register field. */
21318 #define ALT_GIC_DIST_GICD_ITARGETSR94_FLD_RESET 0x0
21319 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR94_FLD field value from a register. */
21320 #define ALT_GIC_DIST_GICD_ITARGETSR94_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21321 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR94_FLD register field value suitable for setting the register. */
21322 #define ALT_GIC_DIST_GICD_ITARGETSR94_FLD_SET(value) (((value) << 0) & 0xffffffff)
21323 
21324 #ifndef __ASSEMBLY__
21325 /*
21326  * WARNING: The C register and register group struct declarations are provided for
21327  * convenience and illustrative purposes. They should, however, be used with
21328  * caution as the C language standard provides no guarantees about the alignment or
21329  * atomicity of device memory accesses. The recommended practice for coding device
21330  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21331  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21332  * alt_write_dword() functions for 64 bit registers.
21333  *
21334  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR94.
21335  */
21336 struct ALT_GIC_DIST_GICD_ITARGETSR94_s
21337 {
21338  volatile uint32_t fld : 32; /* Empty */
21339 };
21340 
21341 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR94. */
21342 typedef struct ALT_GIC_DIST_GICD_ITARGETSR94_s ALT_GIC_DIST_GICD_ITARGETSR94_t;
21343 #endif /* __ASSEMBLY__ */
21344 
21345 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR94 register. */
21346 #define ALT_GIC_DIST_GICD_ITARGETSR94_RESET 0x00000000
21347 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR94 register from the beginning of the component. */
21348 #define ALT_GIC_DIST_GICD_ITARGETSR94_OFST 0x978
21349 
21350 /*
21351  * Register : GICD_ITARGETSR95
21352  *
21353  * Interrupt Processor Targets Registers
21354  *
21355  * Register Layout
21356  *
21357  * Bits | Access | Reset | Description
21358  * :-------|:-------|:------|:------------
21359  * [31:0] | RW | 0x0 | Empty
21360  *
21361  */
21362 /*
21363  * Field : Empty - fld
21364  *
21365  * Placeholder
21366  *
21367  * Field Access Macros:
21368  *
21369  */
21370 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR95_FLD register field. */
21371 #define ALT_GIC_DIST_GICD_ITARGETSR95_FLD_LSB 0
21372 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR95_FLD register field. */
21373 #define ALT_GIC_DIST_GICD_ITARGETSR95_FLD_MSB 31
21374 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR95_FLD register field. */
21375 #define ALT_GIC_DIST_GICD_ITARGETSR95_FLD_WIDTH 32
21376 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR95_FLD register field value. */
21377 #define ALT_GIC_DIST_GICD_ITARGETSR95_FLD_SET_MSK 0xffffffff
21378 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR95_FLD register field value. */
21379 #define ALT_GIC_DIST_GICD_ITARGETSR95_FLD_CLR_MSK 0x00000000
21380 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR95_FLD register field. */
21381 #define ALT_GIC_DIST_GICD_ITARGETSR95_FLD_RESET 0x0
21382 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR95_FLD field value from a register. */
21383 #define ALT_GIC_DIST_GICD_ITARGETSR95_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21384 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR95_FLD register field value suitable for setting the register. */
21385 #define ALT_GIC_DIST_GICD_ITARGETSR95_FLD_SET(value) (((value) << 0) & 0xffffffff)
21386 
21387 #ifndef __ASSEMBLY__
21388 /*
21389  * WARNING: The C register and register group struct declarations are provided for
21390  * convenience and illustrative purposes. They should, however, be used with
21391  * caution as the C language standard provides no guarantees about the alignment or
21392  * atomicity of device memory accesses. The recommended practice for coding device
21393  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21394  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21395  * alt_write_dword() functions for 64 bit registers.
21396  *
21397  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR95.
21398  */
21399 struct ALT_GIC_DIST_GICD_ITARGETSR95_s
21400 {
21401  volatile uint32_t fld : 32; /* Empty */
21402 };
21403 
21404 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR95. */
21405 typedef struct ALT_GIC_DIST_GICD_ITARGETSR95_s ALT_GIC_DIST_GICD_ITARGETSR95_t;
21406 #endif /* __ASSEMBLY__ */
21407 
21408 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR95 register. */
21409 #define ALT_GIC_DIST_GICD_ITARGETSR95_RESET 0x00000000
21410 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR95 register from the beginning of the component. */
21411 #define ALT_GIC_DIST_GICD_ITARGETSR95_OFST 0x97c
21412 
21413 /*
21414  * Register : GICD_ITARGETSR96
21415  *
21416  * Interrupt Processor Targets Registers
21417  *
21418  * Register Layout
21419  *
21420  * Bits | Access | Reset | Description
21421  * :-------|:-------|:------|:------------
21422  * [31:0] | RW | 0x0 | Empty
21423  *
21424  */
21425 /*
21426  * Field : Empty - fld
21427  *
21428  * Placeholder
21429  *
21430  * Field Access Macros:
21431  *
21432  */
21433 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR96_FLD register field. */
21434 #define ALT_GIC_DIST_GICD_ITARGETSR96_FLD_LSB 0
21435 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR96_FLD register field. */
21436 #define ALT_GIC_DIST_GICD_ITARGETSR96_FLD_MSB 31
21437 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR96_FLD register field. */
21438 #define ALT_GIC_DIST_GICD_ITARGETSR96_FLD_WIDTH 32
21439 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR96_FLD register field value. */
21440 #define ALT_GIC_DIST_GICD_ITARGETSR96_FLD_SET_MSK 0xffffffff
21441 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR96_FLD register field value. */
21442 #define ALT_GIC_DIST_GICD_ITARGETSR96_FLD_CLR_MSK 0x00000000
21443 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR96_FLD register field. */
21444 #define ALT_GIC_DIST_GICD_ITARGETSR96_FLD_RESET 0x0
21445 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR96_FLD field value from a register. */
21446 #define ALT_GIC_DIST_GICD_ITARGETSR96_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21447 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR96_FLD register field value suitable for setting the register. */
21448 #define ALT_GIC_DIST_GICD_ITARGETSR96_FLD_SET(value) (((value) << 0) & 0xffffffff)
21449 
21450 #ifndef __ASSEMBLY__
21451 /*
21452  * WARNING: The C register and register group struct declarations are provided for
21453  * convenience and illustrative purposes. They should, however, be used with
21454  * caution as the C language standard provides no guarantees about the alignment or
21455  * atomicity of device memory accesses. The recommended practice for coding device
21456  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21457  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21458  * alt_write_dword() functions for 64 bit registers.
21459  *
21460  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR96.
21461  */
21462 struct ALT_GIC_DIST_GICD_ITARGETSR96_s
21463 {
21464  volatile uint32_t fld : 32; /* Empty */
21465 };
21466 
21467 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR96. */
21468 typedef struct ALT_GIC_DIST_GICD_ITARGETSR96_s ALT_GIC_DIST_GICD_ITARGETSR96_t;
21469 #endif /* __ASSEMBLY__ */
21470 
21471 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR96 register. */
21472 #define ALT_GIC_DIST_GICD_ITARGETSR96_RESET 0x00000000
21473 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR96 register from the beginning of the component. */
21474 #define ALT_GIC_DIST_GICD_ITARGETSR96_OFST 0x980
21475 
21476 /*
21477  * Register : GICD_ITARGETSR97
21478  *
21479  * Interrupt Processor Targets Registers
21480  *
21481  * Register Layout
21482  *
21483  * Bits | Access | Reset | Description
21484  * :-------|:-------|:------|:------------
21485  * [31:0] | RW | 0x0 | Empty
21486  *
21487  */
21488 /*
21489  * Field : Empty - fld
21490  *
21491  * Placeholder
21492  *
21493  * Field Access Macros:
21494  *
21495  */
21496 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR97_FLD register field. */
21497 #define ALT_GIC_DIST_GICD_ITARGETSR97_FLD_LSB 0
21498 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR97_FLD register field. */
21499 #define ALT_GIC_DIST_GICD_ITARGETSR97_FLD_MSB 31
21500 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR97_FLD register field. */
21501 #define ALT_GIC_DIST_GICD_ITARGETSR97_FLD_WIDTH 32
21502 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR97_FLD register field value. */
21503 #define ALT_GIC_DIST_GICD_ITARGETSR97_FLD_SET_MSK 0xffffffff
21504 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR97_FLD register field value. */
21505 #define ALT_GIC_DIST_GICD_ITARGETSR97_FLD_CLR_MSK 0x00000000
21506 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR97_FLD register field. */
21507 #define ALT_GIC_DIST_GICD_ITARGETSR97_FLD_RESET 0x0
21508 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR97_FLD field value from a register. */
21509 #define ALT_GIC_DIST_GICD_ITARGETSR97_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21510 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR97_FLD register field value suitable for setting the register. */
21511 #define ALT_GIC_DIST_GICD_ITARGETSR97_FLD_SET(value) (((value) << 0) & 0xffffffff)
21512 
21513 #ifndef __ASSEMBLY__
21514 /*
21515  * WARNING: The C register and register group struct declarations are provided for
21516  * convenience and illustrative purposes. They should, however, be used with
21517  * caution as the C language standard provides no guarantees about the alignment or
21518  * atomicity of device memory accesses. The recommended practice for coding device
21519  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21520  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21521  * alt_write_dword() functions for 64 bit registers.
21522  *
21523  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR97.
21524  */
21525 struct ALT_GIC_DIST_GICD_ITARGETSR97_s
21526 {
21527  volatile uint32_t fld : 32; /* Empty */
21528 };
21529 
21530 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR97. */
21531 typedef struct ALT_GIC_DIST_GICD_ITARGETSR97_s ALT_GIC_DIST_GICD_ITARGETSR97_t;
21532 #endif /* __ASSEMBLY__ */
21533 
21534 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR97 register. */
21535 #define ALT_GIC_DIST_GICD_ITARGETSR97_RESET 0x00000000
21536 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR97 register from the beginning of the component. */
21537 #define ALT_GIC_DIST_GICD_ITARGETSR97_OFST 0x984
21538 
21539 /*
21540  * Register : GICD_ITARGETSR98
21541  *
21542  * Interrupt Processor Targets Registers
21543  *
21544  * Register Layout
21545  *
21546  * Bits | Access | Reset | Description
21547  * :-------|:-------|:------|:------------
21548  * [31:0] | RW | 0x0 | Empty
21549  *
21550  */
21551 /*
21552  * Field : Empty - fld
21553  *
21554  * Placeholder
21555  *
21556  * Field Access Macros:
21557  *
21558  */
21559 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR98_FLD register field. */
21560 #define ALT_GIC_DIST_GICD_ITARGETSR98_FLD_LSB 0
21561 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR98_FLD register field. */
21562 #define ALT_GIC_DIST_GICD_ITARGETSR98_FLD_MSB 31
21563 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR98_FLD register field. */
21564 #define ALT_GIC_DIST_GICD_ITARGETSR98_FLD_WIDTH 32
21565 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR98_FLD register field value. */
21566 #define ALT_GIC_DIST_GICD_ITARGETSR98_FLD_SET_MSK 0xffffffff
21567 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR98_FLD register field value. */
21568 #define ALT_GIC_DIST_GICD_ITARGETSR98_FLD_CLR_MSK 0x00000000
21569 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR98_FLD register field. */
21570 #define ALT_GIC_DIST_GICD_ITARGETSR98_FLD_RESET 0x0
21571 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR98_FLD field value from a register. */
21572 #define ALT_GIC_DIST_GICD_ITARGETSR98_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21573 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR98_FLD register field value suitable for setting the register. */
21574 #define ALT_GIC_DIST_GICD_ITARGETSR98_FLD_SET(value) (((value) << 0) & 0xffffffff)
21575 
21576 #ifndef __ASSEMBLY__
21577 /*
21578  * WARNING: The C register and register group struct declarations are provided for
21579  * convenience and illustrative purposes. They should, however, be used with
21580  * caution as the C language standard provides no guarantees about the alignment or
21581  * atomicity of device memory accesses. The recommended practice for coding device
21582  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21583  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21584  * alt_write_dword() functions for 64 bit registers.
21585  *
21586  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR98.
21587  */
21588 struct ALT_GIC_DIST_GICD_ITARGETSR98_s
21589 {
21590  volatile uint32_t fld : 32; /* Empty */
21591 };
21592 
21593 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR98. */
21594 typedef struct ALT_GIC_DIST_GICD_ITARGETSR98_s ALT_GIC_DIST_GICD_ITARGETSR98_t;
21595 #endif /* __ASSEMBLY__ */
21596 
21597 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR98 register. */
21598 #define ALT_GIC_DIST_GICD_ITARGETSR98_RESET 0x00000000
21599 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR98 register from the beginning of the component. */
21600 #define ALT_GIC_DIST_GICD_ITARGETSR98_OFST 0x988
21601 
21602 /*
21603  * Register : GICD_ITARGETSR99
21604  *
21605  * Interrupt Processor Targets Registers
21606  *
21607  * Register Layout
21608  *
21609  * Bits | Access | Reset | Description
21610  * :-------|:-------|:------|:------------
21611  * [31:0] | RW | 0x0 | Empty
21612  *
21613  */
21614 /*
21615  * Field : Empty - fld
21616  *
21617  * Placeholder
21618  *
21619  * Field Access Macros:
21620  *
21621  */
21622 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR99_FLD register field. */
21623 #define ALT_GIC_DIST_GICD_ITARGETSR99_FLD_LSB 0
21624 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR99_FLD register field. */
21625 #define ALT_GIC_DIST_GICD_ITARGETSR99_FLD_MSB 31
21626 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR99_FLD register field. */
21627 #define ALT_GIC_DIST_GICD_ITARGETSR99_FLD_WIDTH 32
21628 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR99_FLD register field value. */
21629 #define ALT_GIC_DIST_GICD_ITARGETSR99_FLD_SET_MSK 0xffffffff
21630 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR99_FLD register field value. */
21631 #define ALT_GIC_DIST_GICD_ITARGETSR99_FLD_CLR_MSK 0x00000000
21632 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR99_FLD register field. */
21633 #define ALT_GIC_DIST_GICD_ITARGETSR99_FLD_RESET 0x0
21634 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR99_FLD field value from a register. */
21635 #define ALT_GIC_DIST_GICD_ITARGETSR99_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21636 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR99_FLD register field value suitable for setting the register. */
21637 #define ALT_GIC_DIST_GICD_ITARGETSR99_FLD_SET(value) (((value) << 0) & 0xffffffff)
21638 
21639 #ifndef __ASSEMBLY__
21640 /*
21641  * WARNING: The C register and register group struct declarations are provided for
21642  * convenience and illustrative purposes. They should, however, be used with
21643  * caution as the C language standard provides no guarantees about the alignment or
21644  * atomicity of device memory accesses. The recommended practice for coding device
21645  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21646  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21647  * alt_write_dword() functions for 64 bit registers.
21648  *
21649  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR99.
21650  */
21651 struct ALT_GIC_DIST_GICD_ITARGETSR99_s
21652 {
21653  volatile uint32_t fld : 32; /* Empty */
21654 };
21655 
21656 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR99. */
21657 typedef struct ALT_GIC_DIST_GICD_ITARGETSR99_s ALT_GIC_DIST_GICD_ITARGETSR99_t;
21658 #endif /* __ASSEMBLY__ */
21659 
21660 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR99 register. */
21661 #define ALT_GIC_DIST_GICD_ITARGETSR99_RESET 0x00000000
21662 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR99 register from the beginning of the component. */
21663 #define ALT_GIC_DIST_GICD_ITARGETSR99_OFST 0x98c
21664 
21665 /*
21666  * Register : GICD_ITARGETSR100
21667  *
21668  * Interrupt Processor Targets Registers
21669  *
21670  * Register Layout
21671  *
21672  * Bits | Access | Reset | Description
21673  * :-------|:-------|:------|:------------
21674  * [31:0] | RW | 0x0 | Empty
21675  *
21676  */
21677 /*
21678  * Field : Empty - fld
21679  *
21680  * Placeholder
21681  *
21682  * Field Access Macros:
21683  *
21684  */
21685 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR100_FLD register field. */
21686 #define ALT_GIC_DIST_GICD_ITARGETSR100_FLD_LSB 0
21687 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR100_FLD register field. */
21688 #define ALT_GIC_DIST_GICD_ITARGETSR100_FLD_MSB 31
21689 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR100_FLD register field. */
21690 #define ALT_GIC_DIST_GICD_ITARGETSR100_FLD_WIDTH 32
21691 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR100_FLD register field value. */
21692 #define ALT_GIC_DIST_GICD_ITARGETSR100_FLD_SET_MSK 0xffffffff
21693 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR100_FLD register field value. */
21694 #define ALT_GIC_DIST_GICD_ITARGETSR100_FLD_CLR_MSK 0x00000000
21695 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR100_FLD register field. */
21696 #define ALT_GIC_DIST_GICD_ITARGETSR100_FLD_RESET 0x0
21697 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR100_FLD field value from a register. */
21698 #define ALT_GIC_DIST_GICD_ITARGETSR100_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21699 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR100_FLD register field value suitable for setting the register. */
21700 #define ALT_GIC_DIST_GICD_ITARGETSR100_FLD_SET(value) (((value) << 0) & 0xffffffff)
21701 
21702 #ifndef __ASSEMBLY__
21703 /*
21704  * WARNING: The C register and register group struct declarations are provided for
21705  * convenience and illustrative purposes. They should, however, be used with
21706  * caution as the C language standard provides no guarantees about the alignment or
21707  * atomicity of device memory accesses. The recommended practice for coding device
21708  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21709  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21710  * alt_write_dword() functions for 64 bit registers.
21711  *
21712  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR100.
21713  */
21714 struct ALT_GIC_DIST_GICD_ITARGETSR100_s
21715 {
21716  volatile uint32_t fld : 32; /* Empty */
21717 };
21718 
21719 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR100. */
21720 typedef struct ALT_GIC_DIST_GICD_ITARGETSR100_s ALT_GIC_DIST_GICD_ITARGETSR100_t;
21721 #endif /* __ASSEMBLY__ */
21722 
21723 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR100 register. */
21724 #define ALT_GIC_DIST_GICD_ITARGETSR100_RESET 0x00000000
21725 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR100 register from the beginning of the component. */
21726 #define ALT_GIC_DIST_GICD_ITARGETSR100_OFST 0x990
21727 
21728 /*
21729  * Register : GICD_ITARGETSR101
21730  *
21731  * Interrupt Processor Targets Registers
21732  *
21733  * Register Layout
21734  *
21735  * Bits | Access | Reset | Description
21736  * :-------|:-------|:------|:------------
21737  * [31:0] | RW | 0x0 | Empty
21738  *
21739  */
21740 /*
21741  * Field : Empty - fld
21742  *
21743  * Placeholder
21744  *
21745  * Field Access Macros:
21746  *
21747  */
21748 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR101_FLD register field. */
21749 #define ALT_GIC_DIST_GICD_ITARGETSR101_FLD_LSB 0
21750 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR101_FLD register field. */
21751 #define ALT_GIC_DIST_GICD_ITARGETSR101_FLD_MSB 31
21752 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR101_FLD register field. */
21753 #define ALT_GIC_DIST_GICD_ITARGETSR101_FLD_WIDTH 32
21754 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR101_FLD register field value. */
21755 #define ALT_GIC_DIST_GICD_ITARGETSR101_FLD_SET_MSK 0xffffffff
21756 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR101_FLD register field value. */
21757 #define ALT_GIC_DIST_GICD_ITARGETSR101_FLD_CLR_MSK 0x00000000
21758 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR101_FLD register field. */
21759 #define ALT_GIC_DIST_GICD_ITARGETSR101_FLD_RESET 0x0
21760 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR101_FLD field value from a register. */
21761 #define ALT_GIC_DIST_GICD_ITARGETSR101_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21762 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR101_FLD register field value suitable for setting the register. */
21763 #define ALT_GIC_DIST_GICD_ITARGETSR101_FLD_SET(value) (((value) << 0) & 0xffffffff)
21764 
21765 #ifndef __ASSEMBLY__
21766 /*
21767  * WARNING: The C register and register group struct declarations are provided for
21768  * convenience and illustrative purposes. They should, however, be used with
21769  * caution as the C language standard provides no guarantees about the alignment or
21770  * atomicity of device memory accesses. The recommended practice for coding device
21771  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21772  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21773  * alt_write_dword() functions for 64 bit registers.
21774  *
21775  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR101.
21776  */
21777 struct ALT_GIC_DIST_GICD_ITARGETSR101_s
21778 {
21779  volatile uint32_t fld : 32; /* Empty */
21780 };
21781 
21782 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR101. */
21783 typedef struct ALT_GIC_DIST_GICD_ITARGETSR101_s ALT_GIC_DIST_GICD_ITARGETSR101_t;
21784 #endif /* __ASSEMBLY__ */
21785 
21786 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR101 register. */
21787 #define ALT_GIC_DIST_GICD_ITARGETSR101_RESET 0x00000000
21788 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR101 register from the beginning of the component. */
21789 #define ALT_GIC_DIST_GICD_ITARGETSR101_OFST 0x994
21790 
21791 /*
21792  * Register : GICD_ITARGETSR102
21793  *
21794  * Interrupt Processor Targets Registers
21795  *
21796  * Register Layout
21797  *
21798  * Bits | Access | Reset | Description
21799  * :-------|:-------|:------|:------------
21800  * [31:0] | RW | 0x0 | Empty
21801  *
21802  */
21803 /*
21804  * Field : Empty - fld
21805  *
21806  * Placeholder
21807  *
21808  * Field Access Macros:
21809  *
21810  */
21811 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR102_FLD register field. */
21812 #define ALT_GIC_DIST_GICD_ITARGETSR102_FLD_LSB 0
21813 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR102_FLD register field. */
21814 #define ALT_GIC_DIST_GICD_ITARGETSR102_FLD_MSB 31
21815 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR102_FLD register field. */
21816 #define ALT_GIC_DIST_GICD_ITARGETSR102_FLD_WIDTH 32
21817 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR102_FLD register field value. */
21818 #define ALT_GIC_DIST_GICD_ITARGETSR102_FLD_SET_MSK 0xffffffff
21819 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR102_FLD register field value. */
21820 #define ALT_GIC_DIST_GICD_ITARGETSR102_FLD_CLR_MSK 0x00000000
21821 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR102_FLD register field. */
21822 #define ALT_GIC_DIST_GICD_ITARGETSR102_FLD_RESET 0x0
21823 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR102_FLD field value from a register. */
21824 #define ALT_GIC_DIST_GICD_ITARGETSR102_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21825 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR102_FLD register field value suitable for setting the register. */
21826 #define ALT_GIC_DIST_GICD_ITARGETSR102_FLD_SET(value) (((value) << 0) & 0xffffffff)
21827 
21828 #ifndef __ASSEMBLY__
21829 /*
21830  * WARNING: The C register and register group struct declarations are provided for
21831  * convenience and illustrative purposes. They should, however, be used with
21832  * caution as the C language standard provides no guarantees about the alignment or
21833  * atomicity of device memory accesses. The recommended practice for coding device
21834  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21835  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21836  * alt_write_dword() functions for 64 bit registers.
21837  *
21838  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR102.
21839  */
21840 struct ALT_GIC_DIST_GICD_ITARGETSR102_s
21841 {
21842  volatile uint32_t fld : 32; /* Empty */
21843 };
21844 
21845 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR102. */
21846 typedef struct ALT_GIC_DIST_GICD_ITARGETSR102_s ALT_GIC_DIST_GICD_ITARGETSR102_t;
21847 #endif /* __ASSEMBLY__ */
21848 
21849 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR102 register. */
21850 #define ALT_GIC_DIST_GICD_ITARGETSR102_RESET 0x00000000
21851 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR102 register from the beginning of the component. */
21852 #define ALT_GIC_DIST_GICD_ITARGETSR102_OFST 0x998
21853 
21854 /*
21855  * Register : GICD_ITARGETSR103
21856  *
21857  * Interrupt Processor Targets Registers
21858  *
21859  * Register Layout
21860  *
21861  * Bits | Access | Reset | Description
21862  * :-------|:-------|:------|:------------
21863  * [31:0] | RW | 0x0 | Empty
21864  *
21865  */
21866 /*
21867  * Field : Empty - fld
21868  *
21869  * Placeholder
21870  *
21871  * Field Access Macros:
21872  *
21873  */
21874 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR103_FLD register field. */
21875 #define ALT_GIC_DIST_GICD_ITARGETSR103_FLD_LSB 0
21876 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR103_FLD register field. */
21877 #define ALT_GIC_DIST_GICD_ITARGETSR103_FLD_MSB 31
21878 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR103_FLD register field. */
21879 #define ALT_GIC_DIST_GICD_ITARGETSR103_FLD_WIDTH 32
21880 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR103_FLD register field value. */
21881 #define ALT_GIC_DIST_GICD_ITARGETSR103_FLD_SET_MSK 0xffffffff
21882 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR103_FLD register field value. */
21883 #define ALT_GIC_DIST_GICD_ITARGETSR103_FLD_CLR_MSK 0x00000000
21884 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR103_FLD register field. */
21885 #define ALT_GIC_DIST_GICD_ITARGETSR103_FLD_RESET 0x0
21886 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR103_FLD field value from a register. */
21887 #define ALT_GIC_DIST_GICD_ITARGETSR103_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21888 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR103_FLD register field value suitable for setting the register. */
21889 #define ALT_GIC_DIST_GICD_ITARGETSR103_FLD_SET(value) (((value) << 0) & 0xffffffff)
21890 
21891 #ifndef __ASSEMBLY__
21892 /*
21893  * WARNING: The C register and register group struct declarations are provided for
21894  * convenience and illustrative purposes. They should, however, be used with
21895  * caution as the C language standard provides no guarantees about the alignment or
21896  * atomicity of device memory accesses. The recommended practice for coding device
21897  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21898  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21899  * alt_write_dword() functions for 64 bit registers.
21900  *
21901  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR103.
21902  */
21903 struct ALT_GIC_DIST_GICD_ITARGETSR103_s
21904 {
21905  volatile uint32_t fld : 32; /* Empty */
21906 };
21907 
21908 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR103. */
21909 typedef struct ALT_GIC_DIST_GICD_ITARGETSR103_s ALT_GIC_DIST_GICD_ITARGETSR103_t;
21910 #endif /* __ASSEMBLY__ */
21911 
21912 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR103 register. */
21913 #define ALT_GIC_DIST_GICD_ITARGETSR103_RESET 0x00000000
21914 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR103 register from the beginning of the component. */
21915 #define ALT_GIC_DIST_GICD_ITARGETSR103_OFST 0x99c
21916 
21917 /*
21918  * Register : GICD_ITARGETSR104
21919  *
21920  * Interrupt Processor Targets Registers
21921  *
21922  * Register Layout
21923  *
21924  * Bits | Access | Reset | Description
21925  * :-------|:-------|:------|:------------
21926  * [31:0] | RW | 0x0 | Empty
21927  *
21928  */
21929 /*
21930  * Field : Empty - fld
21931  *
21932  * Placeholder
21933  *
21934  * Field Access Macros:
21935  *
21936  */
21937 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR104_FLD register field. */
21938 #define ALT_GIC_DIST_GICD_ITARGETSR104_FLD_LSB 0
21939 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR104_FLD register field. */
21940 #define ALT_GIC_DIST_GICD_ITARGETSR104_FLD_MSB 31
21941 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR104_FLD register field. */
21942 #define ALT_GIC_DIST_GICD_ITARGETSR104_FLD_WIDTH 32
21943 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR104_FLD register field value. */
21944 #define ALT_GIC_DIST_GICD_ITARGETSR104_FLD_SET_MSK 0xffffffff
21945 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR104_FLD register field value. */
21946 #define ALT_GIC_DIST_GICD_ITARGETSR104_FLD_CLR_MSK 0x00000000
21947 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR104_FLD register field. */
21948 #define ALT_GIC_DIST_GICD_ITARGETSR104_FLD_RESET 0x0
21949 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR104_FLD field value from a register. */
21950 #define ALT_GIC_DIST_GICD_ITARGETSR104_FLD_GET(value) (((value) & 0xffffffff) >> 0)
21951 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR104_FLD register field value suitable for setting the register. */
21952 #define ALT_GIC_DIST_GICD_ITARGETSR104_FLD_SET(value) (((value) << 0) & 0xffffffff)
21953 
21954 #ifndef __ASSEMBLY__
21955 /*
21956  * WARNING: The C register and register group struct declarations are provided for
21957  * convenience and illustrative purposes. They should, however, be used with
21958  * caution as the C language standard provides no guarantees about the alignment or
21959  * atomicity of device memory accesses. The recommended practice for coding device
21960  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
21961  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
21962  * alt_write_dword() functions for 64 bit registers.
21963  *
21964  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR104.
21965  */
21966 struct ALT_GIC_DIST_GICD_ITARGETSR104_s
21967 {
21968  volatile uint32_t fld : 32; /* Empty */
21969 };
21970 
21971 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR104. */
21972 typedef struct ALT_GIC_DIST_GICD_ITARGETSR104_s ALT_GIC_DIST_GICD_ITARGETSR104_t;
21973 #endif /* __ASSEMBLY__ */
21974 
21975 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR104 register. */
21976 #define ALT_GIC_DIST_GICD_ITARGETSR104_RESET 0x00000000
21977 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR104 register from the beginning of the component. */
21978 #define ALT_GIC_DIST_GICD_ITARGETSR104_OFST 0x9a0
21979 
21980 /*
21981  * Register : GICD_ITARGETSR105
21982  *
21983  * Interrupt Processor Targets Registers
21984  *
21985  * Register Layout
21986  *
21987  * Bits | Access | Reset | Description
21988  * :-------|:-------|:------|:------------
21989  * [31:0] | RW | 0x0 | Empty
21990  *
21991  */
21992 /*
21993  * Field : Empty - fld
21994  *
21995  * Placeholder
21996  *
21997  * Field Access Macros:
21998  *
21999  */
22000 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR105_FLD register field. */
22001 #define ALT_GIC_DIST_GICD_ITARGETSR105_FLD_LSB 0
22002 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR105_FLD register field. */
22003 #define ALT_GIC_DIST_GICD_ITARGETSR105_FLD_MSB 31
22004 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR105_FLD register field. */
22005 #define ALT_GIC_DIST_GICD_ITARGETSR105_FLD_WIDTH 32
22006 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR105_FLD register field value. */
22007 #define ALT_GIC_DIST_GICD_ITARGETSR105_FLD_SET_MSK 0xffffffff
22008 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR105_FLD register field value. */
22009 #define ALT_GIC_DIST_GICD_ITARGETSR105_FLD_CLR_MSK 0x00000000
22010 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR105_FLD register field. */
22011 #define ALT_GIC_DIST_GICD_ITARGETSR105_FLD_RESET 0x0
22012 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR105_FLD field value from a register. */
22013 #define ALT_GIC_DIST_GICD_ITARGETSR105_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22014 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR105_FLD register field value suitable for setting the register. */
22015 #define ALT_GIC_DIST_GICD_ITARGETSR105_FLD_SET(value) (((value) << 0) & 0xffffffff)
22016 
22017 #ifndef __ASSEMBLY__
22018 /*
22019  * WARNING: The C register and register group struct declarations are provided for
22020  * convenience and illustrative purposes. They should, however, be used with
22021  * caution as the C language standard provides no guarantees about the alignment or
22022  * atomicity of device memory accesses. The recommended practice for coding device
22023  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22024  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22025  * alt_write_dword() functions for 64 bit registers.
22026  *
22027  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR105.
22028  */
22029 struct ALT_GIC_DIST_GICD_ITARGETSR105_s
22030 {
22031  volatile uint32_t fld : 32; /* Empty */
22032 };
22033 
22034 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR105. */
22035 typedef struct ALT_GIC_DIST_GICD_ITARGETSR105_s ALT_GIC_DIST_GICD_ITARGETSR105_t;
22036 #endif /* __ASSEMBLY__ */
22037 
22038 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR105 register. */
22039 #define ALT_GIC_DIST_GICD_ITARGETSR105_RESET 0x00000000
22040 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR105 register from the beginning of the component. */
22041 #define ALT_GIC_DIST_GICD_ITARGETSR105_OFST 0x9a4
22042 
22043 /*
22044  * Register : GICD_ITARGETSR106
22045  *
22046  * Interrupt Processor Targets Registers
22047  *
22048  * Register Layout
22049  *
22050  * Bits | Access | Reset | Description
22051  * :-------|:-------|:------|:------------
22052  * [31:0] | RW | 0x0 | Empty
22053  *
22054  */
22055 /*
22056  * Field : Empty - fld
22057  *
22058  * Placeholder
22059  *
22060  * Field Access Macros:
22061  *
22062  */
22063 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR106_FLD register field. */
22064 #define ALT_GIC_DIST_GICD_ITARGETSR106_FLD_LSB 0
22065 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR106_FLD register field. */
22066 #define ALT_GIC_DIST_GICD_ITARGETSR106_FLD_MSB 31
22067 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR106_FLD register field. */
22068 #define ALT_GIC_DIST_GICD_ITARGETSR106_FLD_WIDTH 32
22069 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR106_FLD register field value. */
22070 #define ALT_GIC_DIST_GICD_ITARGETSR106_FLD_SET_MSK 0xffffffff
22071 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR106_FLD register field value. */
22072 #define ALT_GIC_DIST_GICD_ITARGETSR106_FLD_CLR_MSK 0x00000000
22073 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR106_FLD register field. */
22074 #define ALT_GIC_DIST_GICD_ITARGETSR106_FLD_RESET 0x0
22075 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR106_FLD field value from a register. */
22076 #define ALT_GIC_DIST_GICD_ITARGETSR106_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22077 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR106_FLD register field value suitable for setting the register. */
22078 #define ALT_GIC_DIST_GICD_ITARGETSR106_FLD_SET(value) (((value) << 0) & 0xffffffff)
22079 
22080 #ifndef __ASSEMBLY__
22081 /*
22082  * WARNING: The C register and register group struct declarations are provided for
22083  * convenience and illustrative purposes. They should, however, be used with
22084  * caution as the C language standard provides no guarantees about the alignment or
22085  * atomicity of device memory accesses. The recommended practice for coding device
22086  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22087  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22088  * alt_write_dword() functions for 64 bit registers.
22089  *
22090  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR106.
22091  */
22092 struct ALT_GIC_DIST_GICD_ITARGETSR106_s
22093 {
22094  volatile uint32_t fld : 32; /* Empty */
22095 };
22096 
22097 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR106. */
22098 typedef struct ALT_GIC_DIST_GICD_ITARGETSR106_s ALT_GIC_DIST_GICD_ITARGETSR106_t;
22099 #endif /* __ASSEMBLY__ */
22100 
22101 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR106 register. */
22102 #define ALT_GIC_DIST_GICD_ITARGETSR106_RESET 0x00000000
22103 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR106 register from the beginning of the component. */
22104 #define ALT_GIC_DIST_GICD_ITARGETSR106_OFST 0x9a8
22105 
22106 /*
22107  * Register : GICD_ITARGETSR107
22108  *
22109  * Interrupt Processor Targets Registers
22110  *
22111  * Register Layout
22112  *
22113  * Bits | Access | Reset | Description
22114  * :-------|:-------|:------|:------------
22115  * [31:0] | RW | 0x0 | Empty
22116  *
22117  */
22118 /*
22119  * Field : Empty - fld
22120  *
22121  * Placeholder
22122  *
22123  * Field Access Macros:
22124  *
22125  */
22126 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR107_FLD register field. */
22127 #define ALT_GIC_DIST_GICD_ITARGETSR107_FLD_LSB 0
22128 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR107_FLD register field. */
22129 #define ALT_GIC_DIST_GICD_ITARGETSR107_FLD_MSB 31
22130 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR107_FLD register field. */
22131 #define ALT_GIC_DIST_GICD_ITARGETSR107_FLD_WIDTH 32
22132 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR107_FLD register field value. */
22133 #define ALT_GIC_DIST_GICD_ITARGETSR107_FLD_SET_MSK 0xffffffff
22134 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR107_FLD register field value. */
22135 #define ALT_GIC_DIST_GICD_ITARGETSR107_FLD_CLR_MSK 0x00000000
22136 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR107_FLD register field. */
22137 #define ALT_GIC_DIST_GICD_ITARGETSR107_FLD_RESET 0x0
22138 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR107_FLD field value from a register. */
22139 #define ALT_GIC_DIST_GICD_ITARGETSR107_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22140 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR107_FLD register field value suitable for setting the register. */
22141 #define ALT_GIC_DIST_GICD_ITARGETSR107_FLD_SET(value) (((value) << 0) & 0xffffffff)
22142 
22143 #ifndef __ASSEMBLY__
22144 /*
22145  * WARNING: The C register and register group struct declarations are provided for
22146  * convenience and illustrative purposes. They should, however, be used with
22147  * caution as the C language standard provides no guarantees about the alignment or
22148  * atomicity of device memory accesses. The recommended practice for coding device
22149  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22150  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22151  * alt_write_dword() functions for 64 bit registers.
22152  *
22153  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR107.
22154  */
22155 struct ALT_GIC_DIST_GICD_ITARGETSR107_s
22156 {
22157  volatile uint32_t fld : 32; /* Empty */
22158 };
22159 
22160 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR107. */
22161 typedef struct ALT_GIC_DIST_GICD_ITARGETSR107_s ALT_GIC_DIST_GICD_ITARGETSR107_t;
22162 #endif /* __ASSEMBLY__ */
22163 
22164 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR107 register. */
22165 #define ALT_GIC_DIST_GICD_ITARGETSR107_RESET 0x00000000
22166 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR107 register from the beginning of the component. */
22167 #define ALT_GIC_DIST_GICD_ITARGETSR107_OFST 0x9ac
22168 
22169 /*
22170  * Register : GICD_ITARGETSR108
22171  *
22172  * Interrupt Processor Targets Registers
22173  *
22174  * Register Layout
22175  *
22176  * Bits | Access | Reset | Description
22177  * :-------|:-------|:------|:------------
22178  * [31:0] | RW | 0x0 | Empty
22179  *
22180  */
22181 /*
22182  * Field : Empty - fld
22183  *
22184  * Placeholder
22185  *
22186  * Field Access Macros:
22187  *
22188  */
22189 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR108_FLD register field. */
22190 #define ALT_GIC_DIST_GICD_ITARGETSR108_FLD_LSB 0
22191 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR108_FLD register field. */
22192 #define ALT_GIC_DIST_GICD_ITARGETSR108_FLD_MSB 31
22193 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR108_FLD register field. */
22194 #define ALT_GIC_DIST_GICD_ITARGETSR108_FLD_WIDTH 32
22195 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR108_FLD register field value. */
22196 #define ALT_GIC_DIST_GICD_ITARGETSR108_FLD_SET_MSK 0xffffffff
22197 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR108_FLD register field value. */
22198 #define ALT_GIC_DIST_GICD_ITARGETSR108_FLD_CLR_MSK 0x00000000
22199 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR108_FLD register field. */
22200 #define ALT_GIC_DIST_GICD_ITARGETSR108_FLD_RESET 0x0
22201 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR108_FLD field value from a register. */
22202 #define ALT_GIC_DIST_GICD_ITARGETSR108_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22203 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR108_FLD register field value suitable for setting the register. */
22204 #define ALT_GIC_DIST_GICD_ITARGETSR108_FLD_SET(value) (((value) << 0) & 0xffffffff)
22205 
22206 #ifndef __ASSEMBLY__
22207 /*
22208  * WARNING: The C register and register group struct declarations are provided for
22209  * convenience and illustrative purposes. They should, however, be used with
22210  * caution as the C language standard provides no guarantees about the alignment or
22211  * atomicity of device memory accesses. The recommended practice for coding device
22212  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22213  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22214  * alt_write_dword() functions for 64 bit registers.
22215  *
22216  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR108.
22217  */
22218 struct ALT_GIC_DIST_GICD_ITARGETSR108_s
22219 {
22220  volatile uint32_t fld : 32; /* Empty */
22221 };
22222 
22223 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR108. */
22224 typedef struct ALT_GIC_DIST_GICD_ITARGETSR108_s ALT_GIC_DIST_GICD_ITARGETSR108_t;
22225 #endif /* __ASSEMBLY__ */
22226 
22227 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR108 register. */
22228 #define ALT_GIC_DIST_GICD_ITARGETSR108_RESET 0x00000000
22229 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR108 register from the beginning of the component. */
22230 #define ALT_GIC_DIST_GICD_ITARGETSR108_OFST 0x9b0
22231 
22232 /*
22233  * Register : GICD_ITARGETSR109
22234  *
22235  * Interrupt Processor Targets Registers
22236  *
22237  * Register Layout
22238  *
22239  * Bits | Access | Reset | Description
22240  * :-------|:-------|:------|:------------
22241  * [31:0] | RW | 0x0 | Empty
22242  *
22243  */
22244 /*
22245  * Field : Empty - fld
22246  *
22247  * Placeholder
22248  *
22249  * Field Access Macros:
22250  *
22251  */
22252 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR109_FLD register field. */
22253 #define ALT_GIC_DIST_GICD_ITARGETSR109_FLD_LSB 0
22254 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR109_FLD register field. */
22255 #define ALT_GIC_DIST_GICD_ITARGETSR109_FLD_MSB 31
22256 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR109_FLD register field. */
22257 #define ALT_GIC_DIST_GICD_ITARGETSR109_FLD_WIDTH 32
22258 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR109_FLD register field value. */
22259 #define ALT_GIC_DIST_GICD_ITARGETSR109_FLD_SET_MSK 0xffffffff
22260 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR109_FLD register field value. */
22261 #define ALT_GIC_DIST_GICD_ITARGETSR109_FLD_CLR_MSK 0x00000000
22262 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR109_FLD register field. */
22263 #define ALT_GIC_DIST_GICD_ITARGETSR109_FLD_RESET 0x0
22264 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR109_FLD field value from a register. */
22265 #define ALT_GIC_DIST_GICD_ITARGETSR109_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22266 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR109_FLD register field value suitable for setting the register. */
22267 #define ALT_GIC_DIST_GICD_ITARGETSR109_FLD_SET(value) (((value) << 0) & 0xffffffff)
22268 
22269 #ifndef __ASSEMBLY__
22270 /*
22271  * WARNING: The C register and register group struct declarations are provided for
22272  * convenience and illustrative purposes. They should, however, be used with
22273  * caution as the C language standard provides no guarantees about the alignment or
22274  * atomicity of device memory accesses. The recommended practice for coding device
22275  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22276  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22277  * alt_write_dword() functions for 64 bit registers.
22278  *
22279  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR109.
22280  */
22281 struct ALT_GIC_DIST_GICD_ITARGETSR109_s
22282 {
22283  volatile uint32_t fld : 32; /* Empty */
22284 };
22285 
22286 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR109. */
22287 typedef struct ALT_GIC_DIST_GICD_ITARGETSR109_s ALT_GIC_DIST_GICD_ITARGETSR109_t;
22288 #endif /* __ASSEMBLY__ */
22289 
22290 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR109 register. */
22291 #define ALT_GIC_DIST_GICD_ITARGETSR109_RESET 0x00000000
22292 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR109 register from the beginning of the component. */
22293 #define ALT_GIC_DIST_GICD_ITARGETSR109_OFST 0x9b4
22294 
22295 /*
22296  * Register : GICD_ITARGETSR110
22297  *
22298  * Interrupt Processor Targets Registers
22299  *
22300  * Register Layout
22301  *
22302  * Bits | Access | Reset | Description
22303  * :-------|:-------|:------|:------------
22304  * [31:0] | RW | 0x0 | Empty
22305  *
22306  */
22307 /*
22308  * Field : Empty - fld
22309  *
22310  * Placeholder
22311  *
22312  * Field Access Macros:
22313  *
22314  */
22315 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR110_FLD register field. */
22316 #define ALT_GIC_DIST_GICD_ITARGETSR110_FLD_LSB 0
22317 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR110_FLD register field. */
22318 #define ALT_GIC_DIST_GICD_ITARGETSR110_FLD_MSB 31
22319 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR110_FLD register field. */
22320 #define ALT_GIC_DIST_GICD_ITARGETSR110_FLD_WIDTH 32
22321 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR110_FLD register field value. */
22322 #define ALT_GIC_DIST_GICD_ITARGETSR110_FLD_SET_MSK 0xffffffff
22323 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR110_FLD register field value. */
22324 #define ALT_GIC_DIST_GICD_ITARGETSR110_FLD_CLR_MSK 0x00000000
22325 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR110_FLD register field. */
22326 #define ALT_GIC_DIST_GICD_ITARGETSR110_FLD_RESET 0x0
22327 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR110_FLD field value from a register. */
22328 #define ALT_GIC_DIST_GICD_ITARGETSR110_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22329 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR110_FLD register field value suitable for setting the register. */
22330 #define ALT_GIC_DIST_GICD_ITARGETSR110_FLD_SET(value) (((value) << 0) & 0xffffffff)
22331 
22332 #ifndef __ASSEMBLY__
22333 /*
22334  * WARNING: The C register and register group struct declarations are provided for
22335  * convenience and illustrative purposes. They should, however, be used with
22336  * caution as the C language standard provides no guarantees about the alignment or
22337  * atomicity of device memory accesses. The recommended practice for coding device
22338  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22339  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22340  * alt_write_dword() functions for 64 bit registers.
22341  *
22342  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR110.
22343  */
22344 struct ALT_GIC_DIST_GICD_ITARGETSR110_s
22345 {
22346  volatile uint32_t fld : 32; /* Empty */
22347 };
22348 
22349 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR110. */
22350 typedef struct ALT_GIC_DIST_GICD_ITARGETSR110_s ALT_GIC_DIST_GICD_ITARGETSR110_t;
22351 #endif /* __ASSEMBLY__ */
22352 
22353 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR110 register. */
22354 #define ALT_GIC_DIST_GICD_ITARGETSR110_RESET 0x00000000
22355 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR110 register from the beginning of the component. */
22356 #define ALT_GIC_DIST_GICD_ITARGETSR110_OFST 0x9b8
22357 
22358 /*
22359  * Register : GICD_ITARGETSR111
22360  *
22361  * Interrupt Processor Targets Registers
22362  *
22363  * Register Layout
22364  *
22365  * Bits | Access | Reset | Description
22366  * :-------|:-------|:------|:------------
22367  * [31:0] | RW | 0x0 | Empty
22368  *
22369  */
22370 /*
22371  * Field : Empty - fld
22372  *
22373  * Placeholder
22374  *
22375  * Field Access Macros:
22376  *
22377  */
22378 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR111_FLD register field. */
22379 #define ALT_GIC_DIST_GICD_ITARGETSR111_FLD_LSB 0
22380 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR111_FLD register field. */
22381 #define ALT_GIC_DIST_GICD_ITARGETSR111_FLD_MSB 31
22382 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR111_FLD register field. */
22383 #define ALT_GIC_DIST_GICD_ITARGETSR111_FLD_WIDTH 32
22384 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR111_FLD register field value. */
22385 #define ALT_GIC_DIST_GICD_ITARGETSR111_FLD_SET_MSK 0xffffffff
22386 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR111_FLD register field value. */
22387 #define ALT_GIC_DIST_GICD_ITARGETSR111_FLD_CLR_MSK 0x00000000
22388 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR111_FLD register field. */
22389 #define ALT_GIC_DIST_GICD_ITARGETSR111_FLD_RESET 0x0
22390 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR111_FLD field value from a register. */
22391 #define ALT_GIC_DIST_GICD_ITARGETSR111_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22392 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR111_FLD register field value suitable for setting the register. */
22393 #define ALT_GIC_DIST_GICD_ITARGETSR111_FLD_SET(value) (((value) << 0) & 0xffffffff)
22394 
22395 #ifndef __ASSEMBLY__
22396 /*
22397  * WARNING: The C register and register group struct declarations are provided for
22398  * convenience and illustrative purposes. They should, however, be used with
22399  * caution as the C language standard provides no guarantees about the alignment or
22400  * atomicity of device memory accesses. The recommended practice for coding device
22401  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22402  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22403  * alt_write_dword() functions for 64 bit registers.
22404  *
22405  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR111.
22406  */
22407 struct ALT_GIC_DIST_GICD_ITARGETSR111_s
22408 {
22409  volatile uint32_t fld : 32; /* Empty */
22410 };
22411 
22412 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR111. */
22413 typedef struct ALT_GIC_DIST_GICD_ITARGETSR111_s ALT_GIC_DIST_GICD_ITARGETSR111_t;
22414 #endif /* __ASSEMBLY__ */
22415 
22416 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR111 register. */
22417 #define ALT_GIC_DIST_GICD_ITARGETSR111_RESET 0x00000000
22418 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR111 register from the beginning of the component. */
22419 #define ALT_GIC_DIST_GICD_ITARGETSR111_OFST 0x9bc
22420 
22421 /*
22422  * Register : GICD_ITARGETSR112
22423  *
22424  * Interrupt Processor Targets Registers
22425  *
22426  * Register Layout
22427  *
22428  * Bits | Access | Reset | Description
22429  * :-------|:-------|:------|:------------
22430  * [31:0] | RW | 0x0 | Empty
22431  *
22432  */
22433 /*
22434  * Field : Empty - fld
22435  *
22436  * Placeholder
22437  *
22438  * Field Access Macros:
22439  *
22440  */
22441 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR112_FLD register field. */
22442 #define ALT_GIC_DIST_GICD_ITARGETSR112_FLD_LSB 0
22443 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR112_FLD register field. */
22444 #define ALT_GIC_DIST_GICD_ITARGETSR112_FLD_MSB 31
22445 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR112_FLD register field. */
22446 #define ALT_GIC_DIST_GICD_ITARGETSR112_FLD_WIDTH 32
22447 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR112_FLD register field value. */
22448 #define ALT_GIC_DIST_GICD_ITARGETSR112_FLD_SET_MSK 0xffffffff
22449 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR112_FLD register field value. */
22450 #define ALT_GIC_DIST_GICD_ITARGETSR112_FLD_CLR_MSK 0x00000000
22451 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR112_FLD register field. */
22452 #define ALT_GIC_DIST_GICD_ITARGETSR112_FLD_RESET 0x0
22453 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR112_FLD field value from a register. */
22454 #define ALT_GIC_DIST_GICD_ITARGETSR112_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22455 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR112_FLD register field value suitable for setting the register. */
22456 #define ALT_GIC_DIST_GICD_ITARGETSR112_FLD_SET(value) (((value) << 0) & 0xffffffff)
22457 
22458 #ifndef __ASSEMBLY__
22459 /*
22460  * WARNING: The C register and register group struct declarations are provided for
22461  * convenience and illustrative purposes. They should, however, be used with
22462  * caution as the C language standard provides no guarantees about the alignment or
22463  * atomicity of device memory accesses. The recommended practice for coding device
22464  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22465  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22466  * alt_write_dword() functions for 64 bit registers.
22467  *
22468  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR112.
22469  */
22470 struct ALT_GIC_DIST_GICD_ITARGETSR112_s
22471 {
22472  volatile uint32_t fld : 32; /* Empty */
22473 };
22474 
22475 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR112. */
22476 typedef struct ALT_GIC_DIST_GICD_ITARGETSR112_s ALT_GIC_DIST_GICD_ITARGETSR112_t;
22477 #endif /* __ASSEMBLY__ */
22478 
22479 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR112 register. */
22480 #define ALT_GIC_DIST_GICD_ITARGETSR112_RESET 0x00000000
22481 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR112 register from the beginning of the component. */
22482 #define ALT_GIC_DIST_GICD_ITARGETSR112_OFST 0x9c0
22483 
22484 /*
22485  * Register : GICD_ITARGETSR113
22486  *
22487  * Interrupt Processor Targets Registers
22488  *
22489  * Register Layout
22490  *
22491  * Bits | Access | Reset | Description
22492  * :-------|:-------|:------|:------------
22493  * [31:0] | RW | 0x0 | Empty
22494  *
22495  */
22496 /*
22497  * Field : Empty - fld
22498  *
22499  * Placeholder
22500  *
22501  * Field Access Macros:
22502  *
22503  */
22504 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR113_FLD register field. */
22505 #define ALT_GIC_DIST_GICD_ITARGETSR113_FLD_LSB 0
22506 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR113_FLD register field. */
22507 #define ALT_GIC_DIST_GICD_ITARGETSR113_FLD_MSB 31
22508 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR113_FLD register field. */
22509 #define ALT_GIC_DIST_GICD_ITARGETSR113_FLD_WIDTH 32
22510 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR113_FLD register field value. */
22511 #define ALT_GIC_DIST_GICD_ITARGETSR113_FLD_SET_MSK 0xffffffff
22512 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR113_FLD register field value. */
22513 #define ALT_GIC_DIST_GICD_ITARGETSR113_FLD_CLR_MSK 0x00000000
22514 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR113_FLD register field. */
22515 #define ALT_GIC_DIST_GICD_ITARGETSR113_FLD_RESET 0x0
22516 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR113_FLD field value from a register. */
22517 #define ALT_GIC_DIST_GICD_ITARGETSR113_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22518 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR113_FLD register field value suitable for setting the register. */
22519 #define ALT_GIC_DIST_GICD_ITARGETSR113_FLD_SET(value) (((value) << 0) & 0xffffffff)
22520 
22521 #ifndef __ASSEMBLY__
22522 /*
22523  * WARNING: The C register and register group struct declarations are provided for
22524  * convenience and illustrative purposes. They should, however, be used with
22525  * caution as the C language standard provides no guarantees about the alignment or
22526  * atomicity of device memory accesses. The recommended practice for coding device
22527  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22528  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22529  * alt_write_dword() functions for 64 bit registers.
22530  *
22531  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR113.
22532  */
22533 struct ALT_GIC_DIST_GICD_ITARGETSR113_s
22534 {
22535  volatile uint32_t fld : 32; /* Empty */
22536 };
22537 
22538 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR113. */
22539 typedef struct ALT_GIC_DIST_GICD_ITARGETSR113_s ALT_GIC_DIST_GICD_ITARGETSR113_t;
22540 #endif /* __ASSEMBLY__ */
22541 
22542 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR113 register. */
22543 #define ALT_GIC_DIST_GICD_ITARGETSR113_RESET 0x00000000
22544 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR113 register from the beginning of the component. */
22545 #define ALT_GIC_DIST_GICD_ITARGETSR113_OFST 0x9c4
22546 
22547 /*
22548  * Register : GICD_ITARGETSR114
22549  *
22550  * Interrupt Processor Targets Registers
22551  *
22552  * Register Layout
22553  *
22554  * Bits | Access | Reset | Description
22555  * :-------|:-------|:------|:------------
22556  * [31:0] | RW | 0x0 | Empty
22557  *
22558  */
22559 /*
22560  * Field : Empty - fld
22561  *
22562  * Placeholder
22563  *
22564  * Field Access Macros:
22565  *
22566  */
22567 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR114_FLD register field. */
22568 #define ALT_GIC_DIST_GICD_ITARGETSR114_FLD_LSB 0
22569 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR114_FLD register field. */
22570 #define ALT_GIC_DIST_GICD_ITARGETSR114_FLD_MSB 31
22571 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR114_FLD register field. */
22572 #define ALT_GIC_DIST_GICD_ITARGETSR114_FLD_WIDTH 32
22573 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR114_FLD register field value. */
22574 #define ALT_GIC_DIST_GICD_ITARGETSR114_FLD_SET_MSK 0xffffffff
22575 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR114_FLD register field value. */
22576 #define ALT_GIC_DIST_GICD_ITARGETSR114_FLD_CLR_MSK 0x00000000
22577 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR114_FLD register field. */
22578 #define ALT_GIC_DIST_GICD_ITARGETSR114_FLD_RESET 0x0
22579 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR114_FLD field value from a register. */
22580 #define ALT_GIC_DIST_GICD_ITARGETSR114_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22581 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR114_FLD register field value suitable for setting the register. */
22582 #define ALT_GIC_DIST_GICD_ITARGETSR114_FLD_SET(value) (((value) << 0) & 0xffffffff)
22583 
22584 #ifndef __ASSEMBLY__
22585 /*
22586  * WARNING: The C register and register group struct declarations are provided for
22587  * convenience and illustrative purposes. They should, however, be used with
22588  * caution as the C language standard provides no guarantees about the alignment or
22589  * atomicity of device memory accesses. The recommended practice for coding device
22590  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22591  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22592  * alt_write_dword() functions for 64 bit registers.
22593  *
22594  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR114.
22595  */
22596 struct ALT_GIC_DIST_GICD_ITARGETSR114_s
22597 {
22598  volatile uint32_t fld : 32; /* Empty */
22599 };
22600 
22601 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR114. */
22602 typedef struct ALT_GIC_DIST_GICD_ITARGETSR114_s ALT_GIC_DIST_GICD_ITARGETSR114_t;
22603 #endif /* __ASSEMBLY__ */
22604 
22605 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR114 register. */
22606 #define ALT_GIC_DIST_GICD_ITARGETSR114_RESET 0x00000000
22607 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR114 register from the beginning of the component. */
22608 #define ALT_GIC_DIST_GICD_ITARGETSR114_OFST 0x9c8
22609 
22610 /*
22611  * Register : GICD_ITARGETSR115
22612  *
22613  * Interrupt Processor Targets Registers
22614  *
22615  * Register Layout
22616  *
22617  * Bits | Access | Reset | Description
22618  * :-------|:-------|:------|:------------
22619  * [31:0] | RW | 0x0 | Empty
22620  *
22621  */
22622 /*
22623  * Field : Empty - fld
22624  *
22625  * Placeholder
22626  *
22627  * Field Access Macros:
22628  *
22629  */
22630 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR115_FLD register field. */
22631 #define ALT_GIC_DIST_GICD_ITARGETSR115_FLD_LSB 0
22632 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR115_FLD register field. */
22633 #define ALT_GIC_DIST_GICD_ITARGETSR115_FLD_MSB 31
22634 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR115_FLD register field. */
22635 #define ALT_GIC_DIST_GICD_ITARGETSR115_FLD_WIDTH 32
22636 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR115_FLD register field value. */
22637 #define ALT_GIC_DIST_GICD_ITARGETSR115_FLD_SET_MSK 0xffffffff
22638 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR115_FLD register field value. */
22639 #define ALT_GIC_DIST_GICD_ITARGETSR115_FLD_CLR_MSK 0x00000000
22640 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR115_FLD register field. */
22641 #define ALT_GIC_DIST_GICD_ITARGETSR115_FLD_RESET 0x0
22642 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR115_FLD field value from a register. */
22643 #define ALT_GIC_DIST_GICD_ITARGETSR115_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22644 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR115_FLD register field value suitable for setting the register. */
22645 #define ALT_GIC_DIST_GICD_ITARGETSR115_FLD_SET(value) (((value) << 0) & 0xffffffff)
22646 
22647 #ifndef __ASSEMBLY__
22648 /*
22649  * WARNING: The C register and register group struct declarations are provided for
22650  * convenience and illustrative purposes. They should, however, be used with
22651  * caution as the C language standard provides no guarantees about the alignment or
22652  * atomicity of device memory accesses. The recommended practice for coding device
22653  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22654  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22655  * alt_write_dword() functions for 64 bit registers.
22656  *
22657  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR115.
22658  */
22659 struct ALT_GIC_DIST_GICD_ITARGETSR115_s
22660 {
22661  volatile uint32_t fld : 32; /* Empty */
22662 };
22663 
22664 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR115. */
22665 typedef struct ALT_GIC_DIST_GICD_ITARGETSR115_s ALT_GIC_DIST_GICD_ITARGETSR115_t;
22666 #endif /* __ASSEMBLY__ */
22667 
22668 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR115 register. */
22669 #define ALT_GIC_DIST_GICD_ITARGETSR115_RESET 0x00000000
22670 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR115 register from the beginning of the component. */
22671 #define ALT_GIC_DIST_GICD_ITARGETSR115_OFST 0x9cc
22672 
22673 /*
22674  * Register : GICD_ITARGETSR116
22675  *
22676  * Interrupt Processor Targets Registers
22677  *
22678  * Register Layout
22679  *
22680  * Bits | Access | Reset | Description
22681  * :-------|:-------|:------|:------------
22682  * [31:0] | RW | 0x0 | Empty
22683  *
22684  */
22685 /*
22686  * Field : Empty - fld
22687  *
22688  * Placeholder
22689  *
22690  * Field Access Macros:
22691  *
22692  */
22693 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR116_FLD register field. */
22694 #define ALT_GIC_DIST_GICD_ITARGETSR116_FLD_LSB 0
22695 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR116_FLD register field. */
22696 #define ALT_GIC_DIST_GICD_ITARGETSR116_FLD_MSB 31
22697 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR116_FLD register field. */
22698 #define ALT_GIC_DIST_GICD_ITARGETSR116_FLD_WIDTH 32
22699 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR116_FLD register field value. */
22700 #define ALT_GIC_DIST_GICD_ITARGETSR116_FLD_SET_MSK 0xffffffff
22701 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR116_FLD register field value. */
22702 #define ALT_GIC_DIST_GICD_ITARGETSR116_FLD_CLR_MSK 0x00000000
22703 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR116_FLD register field. */
22704 #define ALT_GIC_DIST_GICD_ITARGETSR116_FLD_RESET 0x0
22705 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR116_FLD field value from a register. */
22706 #define ALT_GIC_DIST_GICD_ITARGETSR116_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22707 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR116_FLD register field value suitable for setting the register. */
22708 #define ALT_GIC_DIST_GICD_ITARGETSR116_FLD_SET(value) (((value) << 0) & 0xffffffff)
22709 
22710 #ifndef __ASSEMBLY__
22711 /*
22712  * WARNING: The C register and register group struct declarations are provided for
22713  * convenience and illustrative purposes. They should, however, be used with
22714  * caution as the C language standard provides no guarantees about the alignment or
22715  * atomicity of device memory accesses. The recommended practice for coding device
22716  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22717  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22718  * alt_write_dword() functions for 64 bit registers.
22719  *
22720  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR116.
22721  */
22722 struct ALT_GIC_DIST_GICD_ITARGETSR116_s
22723 {
22724  volatile uint32_t fld : 32; /* Empty */
22725 };
22726 
22727 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR116. */
22728 typedef struct ALT_GIC_DIST_GICD_ITARGETSR116_s ALT_GIC_DIST_GICD_ITARGETSR116_t;
22729 #endif /* __ASSEMBLY__ */
22730 
22731 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR116 register. */
22732 #define ALT_GIC_DIST_GICD_ITARGETSR116_RESET 0x00000000
22733 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR116 register from the beginning of the component. */
22734 #define ALT_GIC_DIST_GICD_ITARGETSR116_OFST 0x9d0
22735 
22736 /*
22737  * Register : GICD_ITARGETSR117
22738  *
22739  * Interrupt Processor Targets Registers
22740  *
22741  * Register Layout
22742  *
22743  * Bits | Access | Reset | Description
22744  * :-------|:-------|:------|:------------
22745  * [31:0] | RW | 0x0 | Empty
22746  *
22747  */
22748 /*
22749  * Field : Empty - fld
22750  *
22751  * Placeholder
22752  *
22753  * Field Access Macros:
22754  *
22755  */
22756 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR117_FLD register field. */
22757 #define ALT_GIC_DIST_GICD_ITARGETSR117_FLD_LSB 0
22758 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR117_FLD register field. */
22759 #define ALT_GIC_DIST_GICD_ITARGETSR117_FLD_MSB 31
22760 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR117_FLD register field. */
22761 #define ALT_GIC_DIST_GICD_ITARGETSR117_FLD_WIDTH 32
22762 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR117_FLD register field value. */
22763 #define ALT_GIC_DIST_GICD_ITARGETSR117_FLD_SET_MSK 0xffffffff
22764 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR117_FLD register field value. */
22765 #define ALT_GIC_DIST_GICD_ITARGETSR117_FLD_CLR_MSK 0x00000000
22766 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR117_FLD register field. */
22767 #define ALT_GIC_DIST_GICD_ITARGETSR117_FLD_RESET 0x0
22768 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR117_FLD field value from a register. */
22769 #define ALT_GIC_DIST_GICD_ITARGETSR117_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22770 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR117_FLD register field value suitable for setting the register. */
22771 #define ALT_GIC_DIST_GICD_ITARGETSR117_FLD_SET(value) (((value) << 0) & 0xffffffff)
22772 
22773 #ifndef __ASSEMBLY__
22774 /*
22775  * WARNING: The C register and register group struct declarations are provided for
22776  * convenience and illustrative purposes. They should, however, be used with
22777  * caution as the C language standard provides no guarantees about the alignment or
22778  * atomicity of device memory accesses. The recommended practice for coding device
22779  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22780  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22781  * alt_write_dword() functions for 64 bit registers.
22782  *
22783  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR117.
22784  */
22785 struct ALT_GIC_DIST_GICD_ITARGETSR117_s
22786 {
22787  volatile uint32_t fld : 32; /* Empty */
22788 };
22789 
22790 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR117. */
22791 typedef struct ALT_GIC_DIST_GICD_ITARGETSR117_s ALT_GIC_DIST_GICD_ITARGETSR117_t;
22792 #endif /* __ASSEMBLY__ */
22793 
22794 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR117 register. */
22795 #define ALT_GIC_DIST_GICD_ITARGETSR117_RESET 0x00000000
22796 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR117 register from the beginning of the component. */
22797 #define ALT_GIC_DIST_GICD_ITARGETSR117_OFST 0x9d4
22798 
22799 /*
22800  * Register : GICD_ITARGETSR118
22801  *
22802  * Interrupt Processor Targets Registers
22803  *
22804  * Register Layout
22805  *
22806  * Bits | Access | Reset | Description
22807  * :-------|:-------|:------|:------------
22808  * [31:0] | RW | 0x0 | Empty
22809  *
22810  */
22811 /*
22812  * Field : Empty - fld
22813  *
22814  * Placeholder
22815  *
22816  * Field Access Macros:
22817  *
22818  */
22819 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR118_FLD register field. */
22820 #define ALT_GIC_DIST_GICD_ITARGETSR118_FLD_LSB 0
22821 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR118_FLD register field. */
22822 #define ALT_GIC_DIST_GICD_ITARGETSR118_FLD_MSB 31
22823 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR118_FLD register field. */
22824 #define ALT_GIC_DIST_GICD_ITARGETSR118_FLD_WIDTH 32
22825 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR118_FLD register field value. */
22826 #define ALT_GIC_DIST_GICD_ITARGETSR118_FLD_SET_MSK 0xffffffff
22827 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR118_FLD register field value. */
22828 #define ALT_GIC_DIST_GICD_ITARGETSR118_FLD_CLR_MSK 0x00000000
22829 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR118_FLD register field. */
22830 #define ALT_GIC_DIST_GICD_ITARGETSR118_FLD_RESET 0x0
22831 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR118_FLD field value from a register. */
22832 #define ALT_GIC_DIST_GICD_ITARGETSR118_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22833 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR118_FLD register field value suitable for setting the register. */
22834 #define ALT_GIC_DIST_GICD_ITARGETSR118_FLD_SET(value) (((value) << 0) & 0xffffffff)
22835 
22836 #ifndef __ASSEMBLY__
22837 /*
22838  * WARNING: The C register and register group struct declarations are provided for
22839  * convenience and illustrative purposes. They should, however, be used with
22840  * caution as the C language standard provides no guarantees about the alignment or
22841  * atomicity of device memory accesses. The recommended practice for coding device
22842  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22843  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22844  * alt_write_dword() functions for 64 bit registers.
22845  *
22846  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR118.
22847  */
22848 struct ALT_GIC_DIST_GICD_ITARGETSR118_s
22849 {
22850  volatile uint32_t fld : 32; /* Empty */
22851 };
22852 
22853 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR118. */
22854 typedef struct ALT_GIC_DIST_GICD_ITARGETSR118_s ALT_GIC_DIST_GICD_ITARGETSR118_t;
22855 #endif /* __ASSEMBLY__ */
22856 
22857 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR118 register. */
22858 #define ALT_GIC_DIST_GICD_ITARGETSR118_RESET 0x00000000
22859 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR118 register from the beginning of the component. */
22860 #define ALT_GIC_DIST_GICD_ITARGETSR118_OFST 0x9d8
22861 
22862 /*
22863  * Register : GICD_ITARGETSR119
22864  *
22865  * Interrupt Processor Targets Registers
22866  *
22867  * Register Layout
22868  *
22869  * Bits | Access | Reset | Description
22870  * :-------|:-------|:------|:------------
22871  * [31:0] | RW | 0x0 | Empty
22872  *
22873  */
22874 /*
22875  * Field : Empty - fld
22876  *
22877  * Placeholder
22878  *
22879  * Field Access Macros:
22880  *
22881  */
22882 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR119_FLD register field. */
22883 #define ALT_GIC_DIST_GICD_ITARGETSR119_FLD_LSB 0
22884 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR119_FLD register field. */
22885 #define ALT_GIC_DIST_GICD_ITARGETSR119_FLD_MSB 31
22886 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR119_FLD register field. */
22887 #define ALT_GIC_DIST_GICD_ITARGETSR119_FLD_WIDTH 32
22888 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR119_FLD register field value. */
22889 #define ALT_GIC_DIST_GICD_ITARGETSR119_FLD_SET_MSK 0xffffffff
22890 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR119_FLD register field value. */
22891 #define ALT_GIC_DIST_GICD_ITARGETSR119_FLD_CLR_MSK 0x00000000
22892 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR119_FLD register field. */
22893 #define ALT_GIC_DIST_GICD_ITARGETSR119_FLD_RESET 0x0
22894 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR119_FLD field value from a register. */
22895 #define ALT_GIC_DIST_GICD_ITARGETSR119_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22896 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR119_FLD register field value suitable for setting the register. */
22897 #define ALT_GIC_DIST_GICD_ITARGETSR119_FLD_SET(value) (((value) << 0) & 0xffffffff)
22898 
22899 #ifndef __ASSEMBLY__
22900 /*
22901  * WARNING: The C register and register group struct declarations are provided for
22902  * convenience and illustrative purposes. They should, however, be used with
22903  * caution as the C language standard provides no guarantees about the alignment or
22904  * atomicity of device memory accesses. The recommended practice for coding device
22905  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22906  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22907  * alt_write_dword() functions for 64 bit registers.
22908  *
22909  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR119.
22910  */
22911 struct ALT_GIC_DIST_GICD_ITARGETSR119_s
22912 {
22913  volatile uint32_t fld : 32; /* Empty */
22914 };
22915 
22916 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR119. */
22917 typedef struct ALT_GIC_DIST_GICD_ITARGETSR119_s ALT_GIC_DIST_GICD_ITARGETSR119_t;
22918 #endif /* __ASSEMBLY__ */
22919 
22920 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR119 register. */
22921 #define ALT_GIC_DIST_GICD_ITARGETSR119_RESET 0x00000000
22922 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR119 register from the beginning of the component. */
22923 #define ALT_GIC_DIST_GICD_ITARGETSR119_OFST 0x9dc
22924 
22925 /*
22926  * Register : GICD_ITARGETSR120
22927  *
22928  * Interrupt Processor Targets Registers
22929  *
22930  * Register Layout
22931  *
22932  * Bits | Access | Reset | Description
22933  * :-------|:-------|:------|:------------
22934  * [31:0] | RW | 0x0 | Empty
22935  *
22936  */
22937 /*
22938  * Field : Empty - fld
22939  *
22940  * Placeholder
22941  *
22942  * Field Access Macros:
22943  *
22944  */
22945 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR120_FLD register field. */
22946 #define ALT_GIC_DIST_GICD_ITARGETSR120_FLD_LSB 0
22947 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR120_FLD register field. */
22948 #define ALT_GIC_DIST_GICD_ITARGETSR120_FLD_MSB 31
22949 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR120_FLD register field. */
22950 #define ALT_GIC_DIST_GICD_ITARGETSR120_FLD_WIDTH 32
22951 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR120_FLD register field value. */
22952 #define ALT_GIC_DIST_GICD_ITARGETSR120_FLD_SET_MSK 0xffffffff
22953 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR120_FLD register field value. */
22954 #define ALT_GIC_DIST_GICD_ITARGETSR120_FLD_CLR_MSK 0x00000000
22955 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR120_FLD register field. */
22956 #define ALT_GIC_DIST_GICD_ITARGETSR120_FLD_RESET 0x0
22957 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR120_FLD field value from a register. */
22958 #define ALT_GIC_DIST_GICD_ITARGETSR120_FLD_GET(value) (((value) & 0xffffffff) >> 0)
22959 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR120_FLD register field value suitable for setting the register. */
22960 #define ALT_GIC_DIST_GICD_ITARGETSR120_FLD_SET(value) (((value) << 0) & 0xffffffff)
22961 
22962 #ifndef __ASSEMBLY__
22963 /*
22964  * WARNING: The C register and register group struct declarations are provided for
22965  * convenience and illustrative purposes. They should, however, be used with
22966  * caution as the C language standard provides no guarantees about the alignment or
22967  * atomicity of device memory accesses. The recommended practice for coding device
22968  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
22969  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
22970  * alt_write_dword() functions for 64 bit registers.
22971  *
22972  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR120.
22973  */
22974 struct ALT_GIC_DIST_GICD_ITARGETSR120_s
22975 {
22976  volatile uint32_t fld : 32; /* Empty */
22977 };
22978 
22979 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR120. */
22980 typedef struct ALT_GIC_DIST_GICD_ITARGETSR120_s ALT_GIC_DIST_GICD_ITARGETSR120_t;
22981 #endif /* __ASSEMBLY__ */
22982 
22983 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR120 register. */
22984 #define ALT_GIC_DIST_GICD_ITARGETSR120_RESET 0x00000000
22985 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR120 register from the beginning of the component. */
22986 #define ALT_GIC_DIST_GICD_ITARGETSR120_OFST 0x9e0
22987 
22988 /*
22989  * Register : GICD_ITARGETSR121
22990  *
22991  * Interrupt Processor Targets Registers
22992  *
22993  * Register Layout
22994  *
22995  * Bits | Access | Reset | Description
22996  * :-------|:-------|:------|:------------
22997  * [31:0] | RW | 0x0 | Empty
22998  *
22999  */
23000 /*
23001  * Field : Empty - fld
23002  *
23003  * Placeholder
23004  *
23005  * Field Access Macros:
23006  *
23007  */
23008 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR121_FLD register field. */
23009 #define ALT_GIC_DIST_GICD_ITARGETSR121_FLD_LSB 0
23010 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR121_FLD register field. */
23011 #define ALT_GIC_DIST_GICD_ITARGETSR121_FLD_MSB 31
23012 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR121_FLD register field. */
23013 #define ALT_GIC_DIST_GICD_ITARGETSR121_FLD_WIDTH 32
23014 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR121_FLD register field value. */
23015 #define ALT_GIC_DIST_GICD_ITARGETSR121_FLD_SET_MSK 0xffffffff
23016 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR121_FLD register field value. */
23017 #define ALT_GIC_DIST_GICD_ITARGETSR121_FLD_CLR_MSK 0x00000000
23018 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR121_FLD register field. */
23019 #define ALT_GIC_DIST_GICD_ITARGETSR121_FLD_RESET 0x0
23020 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR121_FLD field value from a register. */
23021 #define ALT_GIC_DIST_GICD_ITARGETSR121_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23022 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR121_FLD register field value suitable for setting the register. */
23023 #define ALT_GIC_DIST_GICD_ITARGETSR121_FLD_SET(value) (((value) << 0) & 0xffffffff)
23024 
23025 #ifndef __ASSEMBLY__
23026 /*
23027  * WARNING: The C register and register group struct declarations are provided for
23028  * convenience and illustrative purposes. They should, however, be used with
23029  * caution as the C language standard provides no guarantees about the alignment or
23030  * atomicity of device memory accesses. The recommended practice for coding device
23031  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23032  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23033  * alt_write_dword() functions for 64 bit registers.
23034  *
23035  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR121.
23036  */
23037 struct ALT_GIC_DIST_GICD_ITARGETSR121_s
23038 {
23039  volatile uint32_t fld : 32; /* Empty */
23040 };
23041 
23042 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR121. */
23043 typedef struct ALT_GIC_DIST_GICD_ITARGETSR121_s ALT_GIC_DIST_GICD_ITARGETSR121_t;
23044 #endif /* __ASSEMBLY__ */
23045 
23046 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR121 register. */
23047 #define ALT_GIC_DIST_GICD_ITARGETSR121_RESET 0x00000000
23048 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR121 register from the beginning of the component. */
23049 #define ALT_GIC_DIST_GICD_ITARGETSR121_OFST 0x9e4
23050 
23051 /*
23052  * Register : GICD_ITARGETSR122
23053  *
23054  * Interrupt Processor Targets Registers
23055  *
23056  * Register Layout
23057  *
23058  * Bits | Access | Reset | Description
23059  * :-------|:-------|:------|:------------
23060  * [31:0] | RW | 0x0 | Empty
23061  *
23062  */
23063 /*
23064  * Field : Empty - fld
23065  *
23066  * Placeholder
23067  *
23068  * Field Access Macros:
23069  *
23070  */
23071 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR122_FLD register field. */
23072 #define ALT_GIC_DIST_GICD_ITARGETSR122_FLD_LSB 0
23073 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR122_FLD register field. */
23074 #define ALT_GIC_DIST_GICD_ITARGETSR122_FLD_MSB 31
23075 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR122_FLD register field. */
23076 #define ALT_GIC_DIST_GICD_ITARGETSR122_FLD_WIDTH 32
23077 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR122_FLD register field value. */
23078 #define ALT_GIC_DIST_GICD_ITARGETSR122_FLD_SET_MSK 0xffffffff
23079 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR122_FLD register field value. */
23080 #define ALT_GIC_DIST_GICD_ITARGETSR122_FLD_CLR_MSK 0x00000000
23081 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR122_FLD register field. */
23082 #define ALT_GIC_DIST_GICD_ITARGETSR122_FLD_RESET 0x0
23083 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR122_FLD field value from a register. */
23084 #define ALT_GIC_DIST_GICD_ITARGETSR122_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23085 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR122_FLD register field value suitable for setting the register. */
23086 #define ALT_GIC_DIST_GICD_ITARGETSR122_FLD_SET(value) (((value) << 0) & 0xffffffff)
23087 
23088 #ifndef __ASSEMBLY__
23089 /*
23090  * WARNING: The C register and register group struct declarations are provided for
23091  * convenience and illustrative purposes. They should, however, be used with
23092  * caution as the C language standard provides no guarantees about the alignment or
23093  * atomicity of device memory accesses. The recommended practice for coding device
23094  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23095  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23096  * alt_write_dword() functions for 64 bit registers.
23097  *
23098  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR122.
23099  */
23100 struct ALT_GIC_DIST_GICD_ITARGETSR122_s
23101 {
23102  volatile uint32_t fld : 32; /* Empty */
23103 };
23104 
23105 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR122. */
23106 typedef struct ALT_GIC_DIST_GICD_ITARGETSR122_s ALT_GIC_DIST_GICD_ITARGETSR122_t;
23107 #endif /* __ASSEMBLY__ */
23108 
23109 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR122 register. */
23110 #define ALT_GIC_DIST_GICD_ITARGETSR122_RESET 0x00000000
23111 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR122 register from the beginning of the component. */
23112 #define ALT_GIC_DIST_GICD_ITARGETSR122_OFST 0x9e8
23113 
23114 /*
23115  * Register : GICD_ITARGETSR123
23116  *
23117  * Interrupt Processor Targets Registers
23118  *
23119  * Register Layout
23120  *
23121  * Bits | Access | Reset | Description
23122  * :-------|:-------|:------|:------------
23123  * [31:0] | RW | 0x0 | Empty
23124  *
23125  */
23126 /*
23127  * Field : Empty - fld
23128  *
23129  * Placeholder
23130  *
23131  * Field Access Macros:
23132  *
23133  */
23134 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR123_FLD register field. */
23135 #define ALT_GIC_DIST_GICD_ITARGETSR123_FLD_LSB 0
23136 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR123_FLD register field. */
23137 #define ALT_GIC_DIST_GICD_ITARGETSR123_FLD_MSB 31
23138 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR123_FLD register field. */
23139 #define ALT_GIC_DIST_GICD_ITARGETSR123_FLD_WIDTH 32
23140 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR123_FLD register field value. */
23141 #define ALT_GIC_DIST_GICD_ITARGETSR123_FLD_SET_MSK 0xffffffff
23142 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR123_FLD register field value. */
23143 #define ALT_GIC_DIST_GICD_ITARGETSR123_FLD_CLR_MSK 0x00000000
23144 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR123_FLD register field. */
23145 #define ALT_GIC_DIST_GICD_ITARGETSR123_FLD_RESET 0x0
23146 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR123_FLD field value from a register. */
23147 #define ALT_GIC_DIST_GICD_ITARGETSR123_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23148 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR123_FLD register field value suitable for setting the register. */
23149 #define ALT_GIC_DIST_GICD_ITARGETSR123_FLD_SET(value) (((value) << 0) & 0xffffffff)
23150 
23151 #ifndef __ASSEMBLY__
23152 /*
23153  * WARNING: The C register and register group struct declarations are provided for
23154  * convenience and illustrative purposes. They should, however, be used with
23155  * caution as the C language standard provides no guarantees about the alignment or
23156  * atomicity of device memory accesses. The recommended practice for coding device
23157  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23158  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23159  * alt_write_dword() functions for 64 bit registers.
23160  *
23161  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR123.
23162  */
23163 struct ALT_GIC_DIST_GICD_ITARGETSR123_s
23164 {
23165  volatile uint32_t fld : 32; /* Empty */
23166 };
23167 
23168 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR123. */
23169 typedef struct ALT_GIC_DIST_GICD_ITARGETSR123_s ALT_GIC_DIST_GICD_ITARGETSR123_t;
23170 #endif /* __ASSEMBLY__ */
23171 
23172 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR123 register. */
23173 #define ALT_GIC_DIST_GICD_ITARGETSR123_RESET 0x00000000
23174 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR123 register from the beginning of the component. */
23175 #define ALT_GIC_DIST_GICD_ITARGETSR123_OFST 0x9ec
23176 
23177 /*
23178  * Register : GICD_ITARGETSR124
23179  *
23180  * Interrupt Processor Targets Registers
23181  *
23182  * Register Layout
23183  *
23184  * Bits | Access | Reset | Description
23185  * :-------|:-------|:------|:------------
23186  * [31:0] | RW | 0x0 | Empty
23187  *
23188  */
23189 /*
23190  * Field : Empty - fld
23191  *
23192  * Placeholder
23193  *
23194  * Field Access Macros:
23195  *
23196  */
23197 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR124_FLD register field. */
23198 #define ALT_GIC_DIST_GICD_ITARGETSR124_FLD_LSB 0
23199 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR124_FLD register field. */
23200 #define ALT_GIC_DIST_GICD_ITARGETSR124_FLD_MSB 31
23201 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR124_FLD register field. */
23202 #define ALT_GIC_DIST_GICD_ITARGETSR124_FLD_WIDTH 32
23203 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR124_FLD register field value. */
23204 #define ALT_GIC_DIST_GICD_ITARGETSR124_FLD_SET_MSK 0xffffffff
23205 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR124_FLD register field value. */
23206 #define ALT_GIC_DIST_GICD_ITARGETSR124_FLD_CLR_MSK 0x00000000
23207 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR124_FLD register field. */
23208 #define ALT_GIC_DIST_GICD_ITARGETSR124_FLD_RESET 0x0
23209 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR124_FLD field value from a register. */
23210 #define ALT_GIC_DIST_GICD_ITARGETSR124_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23211 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR124_FLD register field value suitable for setting the register. */
23212 #define ALT_GIC_DIST_GICD_ITARGETSR124_FLD_SET(value) (((value) << 0) & 0xffffffff)
23213 
23214 #ifndef __ASSEMBLY__
23215 /*
23216  * WARNING: The C register and register group struct declarations are provided for
23217  * convenience and illustrative purposes. They should, however, be used with
23218  * caution as the C language standard provides no guarantees about the alignment or
23219  * atomicity of device memory accesses. The recommended practice for coding device
23220  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23221  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23222  * alt_write_dword() functions for 64 bit registers.
23223  *
23224  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR124.
23225  */
23226 struct ALT_GIC_DIST_GICD_ITARGETSR124_s
23227 {
23228  volatile uint32_t fld : 32; /* Empty */
23229 };
23230 
23231 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR124. */
23232 typedef struct ALT_GIC_DIST_GICD_ITARGETSR124_s ALT_GIC_DIST_GICD_ITARGETSR124_t;
23233 #endif /* __ASSEMBLY__ */
23234 
23235 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR124 register. */
23236 #define ALT_GIC_DIST_GICD_ITARGETSR124_RESET 0x00000000
23237 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR124 register from the beginning of the component. */
23238 #define ALT_GIC_DIST_GICD_ITARGETSR124_OFST 0x9f0
23239 
23240 /*
23241  * Register : GICD_ITARGETSR125
23242  *
23243  * Interrupt Processor Targets Registers
23244  *
23245  * Register Layout
23246  *
23247  * Bits | Access | Reset | Description
23248  * :-------|:-------|:------|:------------
23249  * [31:0] | RW | 0x0 | Empty
23250  *
23251  */
23252 /*
23253  * Field : Empty - fld
23254  *
23255  * Placeholder
23256  *
23257  * Field Access Macros:
23258  *
23259  */
23260 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR125_FLD register field. */
23261 #define ALT_GIC_DIST_GICD_ITARGETSR125_FLD_LSB 0
23262 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR125_FLD register field. */
23263 #define ALT_GIC_DIST_GICD_ITARGETSR125_FLD_MSB 31
23264 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR125_FLD register field. */
23265 #define ALT_GIC_DIST_GICD_ITARGETSR125_FLD_WIDTH 32
23266 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR125_FLD register field value. */
23267 #define ALT_GIC_DIST_GICD_ITARGETSR125_FLD_SET_MSK 0xffffffff
23268 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR125_FLD register field value. */
23269 #define ALT_GIC_DIST_GICD_ITARGETSR125_FLD_CLR_MSK 0x00000000
23270 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR125_FLD register field. */
23271 #define ALT_GIC_DIST_GICD_ITARGETSR125_FLD_RESET 0x0
23272 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR125_FLD field value from a register. */
23273 #define ALT_GIC_DIST_GICD_ITARGETSR125_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23274 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR125_FLD register field value suitable for setting the register. */
23275 #define ALT_GIC_DIST_GICD_ITARGETSR125_FLD_SET(value) (((value) << 0) & 0xffffffff)
23276 
23277 #ifndef __ASSEMBLY__
23278 /*
23279  * WARNING: The C register and register group struct declarations are provided for
23280  * convenience and illustrative purposes. They should, however, be used with
23281  * caution as the C language standard provides no guarantees about the alignment or
23282  * atomicity of device memory accesses. The recommended practice for coding device
23283  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23284  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23285  * alt_write_dword() functions for 64 bit registers.
23286  *
23287  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR125.
23288  */
23289 struct ALT_GIC_DIST_GICD_ITARGETSR125_s
23290 {
23291  volatile uint32_t fld : 32; /* Empty */
23292 };
23293 
23294 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR125. */
23295 typedef struct ALT_GIC_DIST_GICD_ITARGETSR125_s ALT_GIC_DIST_GICD_ITARGETSR125_t;
23296 #endif /* __ASSEMBLY__ */
23297 
23298 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR125 register. */
23299 #define ALT_GIC_DIST_GICD_ITARGETSR125_RESET 0x00000000
23300 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR125 register from the beginning of the component. */
23301 #define ALT_GIC_DIST_GICD_ITARGETSR125_OFST 0x9f4
23302 
23303 /*
23304  * Register : GICD_ITARGETSR126
23305  *
23306  * Interrupt Processor Targets Registers
23307  *
23308  * Register Layout
23309  *
23310  * Bits | Access | Reset | Description
23311  * :-------|:-------|:------|:------------
23312  * [31:0] | RW | 0x0 | Empty
23313  *
23314  */
23315 /*
23316  * Field : Empty - fld
23317  *
23318  * Placeholder
23319  *
23320  * Field Access Macros:
23321  *
23322  */
23323 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR126_FLD register field. */
23324 #define ALT_GIC_DIST_GICD_ITARGETSR126_FLD_LSB 0
23325 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR126_FLD register field. */
23326 #define ALT_GIC_DIST_GICD_ITARGETSR126_FLD_MSB 31
23327 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR126_FLD register field. */
23328 #define ALT_GIC_DIST_GICD_ITARGETSR126_FLD_WIDTH 32
23329 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR126_FLD register field value. */
23330 #define ALT_GIC_DIST_GICD_ITARGETSR126_FLD_SET_MSK 0xffffffff
23331 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR126_FLD register field value. */
23332 #define ALT_GIC_DIST_GICD_ITARGETSR126_FLD_CLR_MSK 0x00000000
23333 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR126_FLD register field. */
23334 #define ALT_GIC_DIST_GICD_ITARGETSR126_FLD_RESET 0x0
23335 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR126_FLD field value from a register. */
23336 #define ALT_GIC_DIST_GICD_ITARGETSR126_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23337 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR126_FLD register field value suitable for setting the register. */
23338 #define ALT_GIC_DIST_GICD_ITARGETSR126_FLD_SET(value) (((value) << 0) & 0xffffffff)
23339 
23340 #ifndef __ASSEMBLY__
23341 /*
23342  * WARNING: The C register and register group struct declarations are provided for
23343  * convenience and illustrative purposes. They should, however, be used with
23344  * caution as the C language standard provides no guarantees about the alignment or
23345  * atomicity of device memory accesses. The recommended practice for coding device
23346  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23347  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23348  * alt_write_dword() functions for 64 bit registers.
23349  *
23350  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR126.
23351  */
23352 struct ALT_GIC_DIST_GICD_ITARGETSR126_s
23353 {
23354  volatile uint32_t fld : 32; /* Empty */
23355 };
23356 
23357 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR126. */
23358 typedef struct ALT_GIC_DIST_GICD_ITARGETSR126_s ALT_GIC_DIST_GICD_ITARGETSR126_t;
23359 #endif /* __ASSEMBLY__ */
23360 
23361 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR126 register. */
23362 #define ALT_GIC_DIST_GICD_ITARGETSR126_RESET 0x00000000
23363 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR126 register from the beginning of the component. */
23364 #define ALT_GIC_DIST_GICD_ITARGETSR126_OFST 0x9f8
23365 
23366 /*
23367  * Register : GICD_ITARGETSR127
23368  *
23369  * Interrupt Processor Targets Registers
23370  *
23371  * Register Layout
23372  *
23373  * Bits | Access | Reset | Description
23374  * :-------|:-------|:------|:------------
23375  * [31:0] | RW | 0x0 | Empty
23376  *
23377  */
23378 /*
23379  * Field : Empty - fld
23380  *
23381  * Placeholder
23382  *
23383  * Field Access Macros:
23384  *
23385  */
23386 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ITARGETSR127_FLD register field. */
23387 #define ALT_GIC_DIST_GICD_ITARGETSR127_FLD_LSB 0
23388 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ITARGETSR127_FLD register field. */
23389 #define ALT_GIC_DIST_GICD_ITARGETSR127_FLD_MSB 31
23390 /* The width in bits of the ALT_GIC_DIST_GICD_ITARGETSR127_FLD register field. */
23391 #define ALT_GIC_DIST_GICD_ITARGETSR127_FLD_WIDTH 32
23392 /* The mask used to set the ALT_GIC_DIST_GICD_ITARGETSR127_FLD register field value. */
23393 #define ALT_GIC_DIST_GICD_ITARGETSR127_FLD_SET_MSK 0xffffffff
23394 /* The mask used to clear the ALT_GIC_DIST_GICD_ITARGETSR127_FLD register field value. */
23395 #define ALT_GIC_DIST_GICD_ITARGETSR127_FLD_CLR_MSK 0x00000000
23396 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR127_FLD register field. */
23397 #define ALT_GIC_DIST_GICD_ITARGETSR127_FLD_RESET 0x0
23398 /* Extracts the ALT_GIC_DIST_GICD_ITARGETSR127_FLD field value from a register. */
23399 #define ALT_GIC_DIST_GICD_ITARGETSR127_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23400 /* Produces a ALT_GIC_DIST_GICD_ITARGETSR127_FLD register field value suitable for setting the register. */
23401 #define ALT_GIC_DIST_GICD_ITARGETSR127_FLD_SET(value) (((value) << 0) & 0xffffffff)
23402 
23403 #ifndef __ASSEMBLY__
23404 /*
23405  * WARNING: The C register and register group struct declarations are provided for
23406  * convenience and illustrative purposes. They should, however, be used with
23407  * caution as the C language standard provides no guarantees about the alignment or
23408  * atomicity of device memory accesses. The recommended practice for coding device
23409  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23410  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23411  * alt_write_dword() functions for 64 bit registers.
23412  *
23413  * The struct declaration for register ALT_GIC_DIST_GICD_ITARGETSR127.
23414  */
23415 struct ALT_GIC_DIST_GICD_ITARGETSR127_s
23416 {
23417  volatile uint32_t fld : 32; /* Empty */
23418 };
23419 
23420 /* The typedef declaration for register ALT_GIC_DIST_GICD_ITARGETSR127. */
23421 typedef struct ALT_GIC_DIST_GICD_ITARGETSR127_s ALT_GIC_DIST_GICD_ITARGETSR127_t;
23422 #endif /* __ASSEMBLY__ */
23423 
23424 /* The reset value of the ALT_GIC_DIST_GICD_ITARGETSR127 register. */
23425 #define ALT_GIC_DIST_GICD_ITARGETSR127_RESET 0x00000000
23426 /* The byte offset of the ALT_GIC_DIST_GICD_ITARGETSR127 register from the beginning of the component. */
23427 #define ALT_GIC_DIST_GICD_ITARGETSR127_OFST 0x9fc
23428 
23429 /*
23430  * Register : GICD_ICFGR0
23431  *
23432  * Interrupt Configuration Registers
23433  *
23434  * Register Layout
23435  *
23436  * Bits | Access | Reset | Description
23437  * :-------|:-------|:-----------|:------------
23438  * [31:0] | RW | 0xaaaaaaaa | Empty
23439  *
23440  */
23441 /*
23442  * Field : Empty - fld
23443  *
23444  * Placeholder
23445  *
23446  * Field Access Macros:
23447  *
23448  */
23449 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR0_FLD register field. */
23450 #define ALT_GIC_DIST_GICD_ICFGR0_FLD_LSB 0
23451 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR0_FLD register field. */
23452 #define ALT_GIC_DIST_GICD_ICFGR0_FLD_MSB 31
23453 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR0_FLD register field. */
23454 #define ALT_GIC_DIST_GICD_ICFGR0_FLD_WIDTH 32
23455 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR0_FLD register field value. */
23456 #define ALT_GIC_DIST_GICD_ICFGR0_FLD_SET_MSK 0xffffffff
23457 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR0_FLD register field value. */
23458 #define ALT_GIC_DIST_GICD_ICFGR0_FLD_CLR_MSK 0x00000000
23459 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR0_FLD register field. */
23460 #define ALT_GIC_DIST_GICD_ICFGR0_FLD_RESET 0xaaaaaaaa
23461 /* Extracts the ALT_GIC_DIST_GICD_ICFGR0_FLD field value from a register. */
23462 #define ALT_GIC_DIST_GICD_ICFGR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23463 /* Produces a ALT_GIC_DIST_GICD_ICFGR0_FLD register field value suitable for setting the register. */
23464 #define ALT_GIC_DIST_GICD_ICFGR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
23465 
23466 #ifndef __ASSEMBLY__
23467 /*
23468  * WARNING: The C register and register group struct declarations are provided for
23469  * convenience and illustrative purposes. They should, however, be used with
23470  * caution as the C language standard provides no guarantees about the alignment or
23471  * atomicity of device memory accesses. The recommended practice for coding device
23472  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23473  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23474  * alt_write_dword() functions for 64 bit registers.
23475  *
23476  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR0.
23477  */
23478 struct ALT_GIC_DIST_GICD_ICFGR0_s
23479 {
23480  volatile uint32_t fld : 32; /* Empty */
23481 };
23482 
23483 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR0. */
23484 typedef struct ALT_GIC_DIST_GICD_ICFGR0_s ALT_GIC_DIST_GICD_ICFGR0_t;
23485 #endif /* __ASSEMBLY__ */
23486 
23487 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR0 register. */
23488 #define ALT_GIC_DIST_GICD_ICFGR0_RESET 0xaaaaaaaa
23489 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR0 register from the beginning of the component. */
23490 #define ALT_GIC_DIST_GICD_ICFGR0_OFST 0xc00
23491 
23492 /*
23493  * Register : GICD_ICFGR1
23494  *
23495  * Interrupt Configuration Registers
23496  *
23497  * Register Layout
23498  *
23499  * Bits | Access | Reset | Description
23500  * :-------|:-------|:--------|:------------
23501  * [31:0] | RW | Unknown | Empty
23502  *
23503  */
23504 /*
23505  * Field : Empty - fld
23506  *
23507  * Placeholder
23508  *
23509  * Field Access Macros:
23510  *
23511  */
23512 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR1_FLD register field. */
23513 #define ALT_GIC_DIST_GICD_ICFGR1_FLD_LSB 0
23514 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR1_FLD register field. */
23515 #define ALT_GIC_DIST_GICD_ICFGR1_FLD_MSB 31
23516 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR1_FLD register field. */
23517 #define ALT_GIC_DIST_GICD_ICFGR1_FLD_WIDTH 32
23518 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR1_FLD register field value. */
23519 #define ALT_GIC_DIST_GICD_ICFGR1_FLD_SET_MSK 0xffffffff
23520 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR1_FLD register field value. */
23521 #define ALT_GIC_DIST_GICD_ICFGR1_FLD_CLR_MSK 0x00000000
23522 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR1_FLD register field is UNKNOWN. */
23523 #define ALT_GIC_DIST_GICD_ICFGR1_FLD_RESET 0x0
23524 /* Extracts the ALT_GIC_DIST_GICD_ICFGR1_FLD field value from a register. */
23525 #define ALT_GIC_DIST_GICD_ICFGR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23526 /* Produces a ALT_GIC_DIST_GICD_ICFGR1_FLD register field value suitable for setting the register. */
23527 #define ALT_GIC_DIST_GICD_ICFGR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
23528 
23529 #ifndef __ASSEMBLY__
23530 /*
23531  * WARNING: The C register and register group struct declarations are provided for
23532  * convenience and illustrative purposes. They should, however, be used with
23533  * caution as the C language standard provides no guarantees about the alignment or
23534  * atomicity of device memory accesses. The recommended practice for coding device
23535  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23536  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23537  * alt_write_dword() functions for 64 bit registers.
23538  *
23539  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR1.
23540  */
23541 struct ALT_GIC_DIST_GICD_ICFGR1_s
23542 {
23543  volatile uint32_t fld : 32; /* Empty */
23544 };
23545 
23546 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR1. */
23547 typedef struct ALT_GIC_DIST_GICD_ICFGR1_s ALT_GIC_DIST_GICD_ICFGR1_t;
23548 #endif /* __ASSEMBLY__ */
23549 
23550 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR1 register. */
23551 #define ALT_GIC_DIST_GICD_ICFGR1_RESET 0x55540000
23552 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR1 register from the beginning of the component. */
23553 #define ALT_GIC_DIST_GICD_ICFGR1_OFST 0xc04
23554 
23555 /*
23556  * Register : GICD_ICFGR2
23557  *
23558  * Interrupt Configuration Registers
23559  *
23560  * Register Layout
23561  *
23562  * Bits | Access | Reset | Description
23563  * :-------|:-------|:-----------|:------------
23564  * [31:0] | RW | 0x55555555 | Empty
23565  *
23566  */
23567 /*
23568  * Field : Empty - fld
23569  *
23570  * Placeholder
23571  *
23572  * Field Access Macros:
23573  *
23574  */
23575 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR2_FLD register field. */
23576 #define ALT_GIC_DIST_GICD_ICFGR2_FLD_LSB 0
23577 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR2_FLD register field. */
23578 #define ALT_GIC_DIST_GICD_ICFGR2_FLD_MSB 31
23579 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR2_FLD register field. */
23580 #define ALT_GIC_DIST_GICD_ICFGR2_FLD_WIDTH 32
23581 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR2_FLD register field value. */
23582 #define ALT_GIC_DIST_GICD_ICFGR2_FLD_SET_MSK 0xffffffff
23583 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR2_FLD register field value. */
23584 #define ALT_GIC_DIST_GICD_ICFGR2_FLD_CLR_MSK 0x00000000
23585 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR2_FLD register field. */
23586 #define ALT_GIC_DIST_GICD_ICFGR2_FLD_RESET 0x55555555
23587 /* Extracts the ALT_GIC_DIST_GICD_ICFGR2_FLD field value from a register. */
23588 #define ALT_GIC_DIST_GICD_ICFGR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23589 /* Produces a ALT_GIC_DIST_GICD_ICFGR2_FLD register field value suitable for setting the register. */
23590 #define ALT_GIC_DIST_GICD_ICFGR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
23591 
23592 #ifndef __ASSEMBLY__
23593 /*
23594  * WARNING: The C register and register group struct declarations are provided for
23595  * convenience and illustrative purposes. They should, however, be used with
23596  * caution as the C language standard provides no guarantees about the alignment or
23597  * atomicity of device memory accesses. The recommended practice for coding device
23598  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23599  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23600  * alt_write_dword() functions for 64 bit registers.
23601  *
23602  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR2.
23603  */
23604 struct ALT_GIC_DIST_GICD_ICFGR2_s
23605 {
23606  volatile uint32_t fld : 32; /* Empty */
23607 };
23608 
23609 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR2. */
23610 typedef struct ALT_GIC_DIST_GICD_ICFGR2_s ALT_GIC_DIST_GICD_ICFGR2_t;
23611 #endif /* __ASSEMBLY__ */
23612 
23613 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR2 register. */
23614 #define ALT_GIC_DIST_GICD_ICFGR2_RESET 0x55555555
23615 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR2 register from the beginning of the component. */
23616 #define ALT_GIC_DIST_GICD_ICFGR2_OFST 0xc08
23617 
23618 /*
23619  * Register : GICD_ICFGR3
23620  *
23621  * Interrupt Configuration Registers
23622  *
23623  * Register Layout
23624  *
23625  * Bits | Access | Reset | Description
23626  * :-------|:-------|:-----------|:------------
23627  * [31:0] | RW | 0x55555555 | Empty
23628  *
23629  */
23630 /*
23631  * Field : Empty - fld
23632  *
23633  * Placeholder
23634  *
23635  * Field Access Macros:
23636  *
23637  */
23638 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR3_FLD register field. */
23639 #define ALT_GIC_DIST_GICD_ICFGR3_FLD_LSB 0
23640 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR3_FLD register field. */
23641 #define ALT_GIC_DIST_GICD_ICFGR3_FLD_MSB 31
23642 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR3_FLD register field. */
23643 #define ALT_GIC_DIST_GICD_ICFGR3_FLD_WIDTH 32
23644 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR3_FLD register field value. */
23645 #define ALT_GIC_DIST_GICD_ICFGR3_FLD_SET_MSK 0xffffffff
23646 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR3_FLD register field value. */
23647 #define ALT_GIC_DIST_GICD_ICFGR3_FLD_CLR_MSK 0x00000000
23648 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR3_FLD register field. */
23649 #define ALT_GIC_DIST_GICD_ICFGR3_FLD_RESET 0x55555555
23650 /* Extracts the ALT_GIC_DIST_GICD_ICFGR3_FLD field value from a register. */
23651 #define ALT_GIC_DIST_GICD_ICFGR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23652 /* Produces a ALT_GIC_DIST_GICD_ICFGR3_FLD register field value suitable for setting the register. */
23653 #define ALT_GIC_DIST_GICD_ICFGR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
23654 
23655 #ifndef __ASSEMBLY__
23656 /*
23657  * WARNING: The C register and register group struct declarations are provided for
23658  * convenience and illustrative purposes. They should, however, be used with
23659  * caution as the C language standard provides no guarantees about the alignment or
23660  * atomicity of device memory accesses. The recommended practice for coding device
23661  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23662  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23663  * alt_write_dword() functions for 64 bit registers.
23664  *
23665  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR3.
23666  */
23667 struct ALT_GIC_DIST_GICD_ICFGR3_s
23668 {
23669  volatile uint32_t fld : 32; /* Empty */
23670 };
23671 
23672 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR3. */
23673 typedef struct ALT_GIC_DIST_GICD_ICFGR3_s ALT_GIC_DIST_GICD_ICFGR3_t;
23674 #endif /* __ASSEMBLY__ */
23675 
23676 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR3 register. */
23677 #define ALT_GIC_DIST_GICD_ICFGR3_RESET 0x55555555
23678 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR3 register from the beginning of the component. */
23679 #define ALT_GIC_DIST_GICD_ICFGR3_OFST 0xc0c
23680 
23681 /*
23682  * Register : GICD_ICFGR4
23683  *
23684  * Interrupt Configuration Registers
23685  *
23686  * Register Layout
23687  *
23688  * Bits | Access | Reset | Description
23689  * :-------|:-------|:-----------|:------------
23690  * [31:0] | RW | 0x55555555 | Empty
23691  *
23692  */
23693 /*
23694  * Field : Empty - fld
23695  *
23696  * Placeholder
23697  *
23698  * Field Access Macros:
23699  *
23700  */
23701 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR4_FLD register field. */
23702 #define ALT_GIC_DIST_GICD_ICFGR4_FLD_LSB 0
23703 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR4_FLD register field. */
23704 #define ALT_GIC_DIST_GICD_ICFGR4_FLD_MSB 31
23705 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR4_FLD register field. */
23706 #define ALT_GIC_DIST_GICD_ICFGR4_FLD_WIDTH 32
23707 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR4_FLD register field value. */
23708 #define ALT_GIC_DIST_GICD_ICFGR4_FLD_SET_MSK 0xffffffff
23709 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR4_FLD register field value. */
23710 #define ALT_GIC_DIST_GICD_ICFGR4_FLD_CLR_MSK 0x00000000
23711 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR4_FLD register field. */
23712 #define ALT_GIC_DIST_GICD_ICFGR4_FLD_RESET 0x55555555
23713 /* Extracts the ALT_GIC_DIST_GICD_ICFGR4_FLD field value from a register. */
23714 #define ALT_GIC_DIST_GICD_ICFGR4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23715 /* Produces a ALT_GIC_DIST_GICD_ICFGR4_FLD register field value suitable for setting the register. */
23716 #define ALT_GIC_DIST_GICD_ICFGR4_FLD_SET(value) (((value) << 0) & 0xffffffff)
23717 
23718 #ifndef __ASSEMBLY__
23719 /*
23720  * WARNING: The C register and register group struct declarations are provided for
23721  * convenience and illustrative purposes. They should, however, be used with
23722  * caution as the C language standard provides no guarantees about the alignment or
23723  * atomicity of device memory accesses. The recommended practice for coding device
23724  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23725  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23726  * alt_write_dword() functions for 64 bit registers.
23727  *
23728  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR4.
23729  */
23730 struct ALT_GIC_DIST_GICD_ICFGR4_s
23731 {
23732  volatile uint32_t fld : 32; /* Empty */
23733 };
23734 
23735 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR4. */
23736 typedef struct ALT_GIC_DIST_GICD_ICFGR4_s ALT_GIC_DIST_GICD_ICFGR4_t;
23737 #endif /* __ASSEMBLY__ */
23738 
23739 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR4 register. */
23740 #define ALT_GIC_DIST_GICD_ICFGR4_RESET 0x55555555
23741 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR4 register from the beginning of the component. */
23742 #define ALT_GIC_DIST_GICD_ICFGR4_OFST 0xc10
23743 
23744 /*
23745  * Register : GICD_ICFGR5
23746  *
23747  * Interrupt Configuration Registers
23748  *
23749  * Register Layout
23750  *
23751  * Bits | Access | Reset | Description
23752  * :-------|:-------|:-----------|:------------
23753  * [31:0] | RW | 0x55555555 | Empty
23754  *
23755  */
23756 /*
23757  * Field : Empty - fld
23758  *
23759  * Placeholder
23760  *
23761  * Field Access Macros:
23762  *
23763  */
23764 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR5_FLD register field. */
23765 #define ALT_GIC_DIST_GICD_ICFGR5_FLD_LSB 0
23766 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR5_FLD register field. */
23767 #define ALT_GIC_DIST_GICD_ICFGR5_FLD_MSB 31
23768 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR5_FLD register field. */
23769 #define ALT_GIC_DIST_GICD_ICFGR5_FLD_WIDTH 32
23770 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR5_FLD register field value. */
23771 #define ALT_GIC_DIST_GICD_ICFGR5_FLD_SET_MSK 0xffffffff
23772 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR5_FLD register field value. */
23773 #define ALT_GIC_DIST_GICD_ICFGR5_FLD_CLR_MSK 0x00000000
23774 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR5_FLD register field. */
23775 #define ALT_GIC_DIST_GICD_ICFGR5_FLD_RESET 0x55555555
23776 /* Extracts the ALT_GIC_DIST_GICD_ICFGR5_FLD field value from a register. */
23777 #define ALT_GIC_DIST_GICD_ICFGR5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23778 /* Produces a ALT_GIC_DIST_GICD_ICFGR5_FLD register field value suitable for setting the register. */
23779 #define ALT_GIC_DIST_GICD_ICFGR5_FLD_SET(value) (((value) << 0) & 0xffffffff)
23780 
23781 #ifndef __ASSEMBLY__
23782 /*
23783  * WARNING: The C register and register group struct declarations are provided for
23784  * convenience and illustrative purposes. They should, however, be used with
23785  * caution as the C language standard provides no guarantees about the alignment or
23786  * atomicity of device memory accesses. The recommended practice for coding device
23787  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23788  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23789  * alt_write_dword() functions for 64 bit registers.
23790  *
23791  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR5.
23792  */
23793 struct ALT_GIC_DIST_GICD_ICFGR5_s
23794 {
23795  volatile uint32_t fld : 32; /* Empty */
23796 };
23797 
23798 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR5. */
23799 typedef struct ALT_GIC_DIST_GICD_ICFGR5_s ALT_GIC_DIST_GICD_ICFGR5_t;
23800 #endif /* __ASSEMBLY__ */
23801 
23802 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR5 register. */
23803 #define ALT_GIC_DIST_GICD_ICFGR5_RESET 0x55555555
23804 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR5 register from the beginning of the component. */
23805 #define ALT_GIC_DIST_GICD_ICFGR5_OFST 0xc14
23806 
23807 /*
23808  * Register : GICD_ICFGR6
23809  *
23810  * Interrupt Configuration Registers
23811  *
23812  * Register Layout
23813  *
23814  * Bits | Access | Reset | Description
23815  * :-------|:-------|:-----------|:------------
23816  * [31:0] | RW | 0x55555555 | Empty
23817  *
23818  */
23819 /*
23820  * Field : Empty - fld
23821  *
23822  * Placeholder
23823  *
23824  * Field Access Macros:
23825  *
23826  */
23827 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR6_FLD register field. */
23828 #define ALT_GIC_DIST_GICD_ICFGR6_FLD_LSB 0
23829 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR6_FLD register field. */
23830 #define ALT_GIC_DIST_GICD_ICFGR6_FLD_MSB 31
23831 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR6_FLD register field. */
23832 #define ALT_GIC_DIST_GICD_ICFGR6_FLD_WIDTH 32
23833 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR6_FLD register field value. */
23834 #define ALT_GIC_DIST_GICD_ICFGR6_FLD_SET_MSK 0xffffffff
23835 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR6_FLD register field value. */
23836 #define ALT_GIC_DIST_GICD_ICFGR6_FLD_CLR_MSK 0x00000000
23837 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR6_FLD register field. */
23838 #define ALT_GIC_DIST_GICD_ICFGR6_FLD_RESET 0x55555555
23839 /* Extracts the ALT_GIC_DIST_GICD_ICFGR6_FLD field value from a register. */
23840 #define ALT_GIC_DIST_GICD_ICFGR6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23841 /* Produces a ALT_GIC_DIST_GICD_ICFGR6_FLD register field value suitable for setting the register. */
23842 #define ALT_GIC_DIST_GICD_ICFGR6_FLD_SET(value) (((value) << 0) & 0xffffffff)
23843 
23844 #ifndef __ASSEMBLY__
23845 /*
23846  * WARNING: The C register and register group struct declarations are provided for
23847  * convenience and illustrative purposes. They should, however, be used with
23848  * caution as the C language standard provides no guarantees about the alignment or
23849  * atomicity of device memory accesses. The recommended practice for coding device
23850  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23851  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23852  * alt_write_dword() functions for 64 bit registers.
23853  *
23854  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR6.
23855  */
23856 struct ALT_GIC_DIST_GICD_ICFGR6_s
23857 {
23858  volatile uint32_t fld : 32; /* Empty */
23859 };
23860 
23861 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR6. */
23862 typedef struct ALT_GIC_DIST_GICD_ICFGR6_s ALT_GIC_DIST_GICD_ICFGR6_t;
23863 #endif /* __ASSEMBLY__ */
23864 
23865 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR6 register. */
23866 #define ALT_GIC_DIST_GICD_ICFGR6_RESET 0x55555555
23867 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR6 register from the beginning of the component. */
23868 #define ALT_GIC_DIST_GICD_ICFGR6_OFST 0xc18
23869 
23870 /*
23871  * Register : GICD_ICFGR7
23872  *
23873  * Interrupt Configuration Registers
23874  *
23875  * Register Layout
23876  *
23877  * Bits | Access | Reset | Description
23878  * :-------|:-------|:-----------|:------------
23879  * [31:0] | RW | 0x55555555 | Empty
23880  *
23881  */
23882 /*
23883  * Field : Empty - fld
23884  *
23885  * Placeholder
23886  *
23887  * Field Access Macros:
23888  *
23889  */
23890 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR7_FLD register field. */
23891 #define ALT_GIC_DIST_GICD_ICFGR7_FLD_LSB 0
23892 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR7_FLD register field. */
23893 #define ALT_GIC_DIST_GICD_ICFGR7_FLD_MSB 31
23894 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR7_FLD register field. */
23895 #define ALT_GIC_DIST_GICD_ICFGR7_FLD_WIDTH 32
23896 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR7_FLD register field value. */
23897 #define ALT_GIC_DIST_GICD_ICFGR7_FLD_SET_MSK 0xffffffff
23898 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR7_FLD register field value. */
23899 #define ALT_GIC_DIST_GICD_ICFGR7_FLD_CLR_MSK 0x00000000
23900 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR7_FLD register field. */
23901 #define ALT_GIC_DIST_GICD_ICFGR7_FLD_RESET 0x55555555
23902 /* Extracts the ALT_GIC_DIST_GICD_ICFGR7_FLD field value from a register. */
23903 #define ALT_GIC_DIST_GICD_ICFGR7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23904 /* Produces a ALT_GIC_DIST_GICD_ICFGR7_FLD register field value suitable for setting the register. */
23905 #define ALT_GIC_DIST_GICD_ICFGR7_FLD_SET(value) (((value) << 0) & 0xffffffff)
23906 
23907 #ifndef __ASSEMBLY__
23908 /*
23909  * WARNING: The C register and register group struct declarations are provided for
23910  * convenience and illustrative purposes. They should, however, be used with
23911  * caution as the C language standard provides no guarantees about the alignment or
23912  * atomicity of device memory accesses. The recommended practice for coding device
23913  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23914  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23915  * alt_write_dword() functions for 64 bit registers.
23916  *
23917  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR7.
23918  */
23919 struct ALT_GIC_DIST_GICD_ICFGR7_s
23920 {
23921  volatile uint32_t fld : 32; /* Empty */
23922 };
23923 
23924 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR7. */
23925 typedef struct ALT_GIC_DIST_GICD_ICFGR7_s ALT_GIC_DIST_GICD_ICFGR7_t;
23926 #endif /* __ASSEMBLY__ */
23927 
23928 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR7 register. */
23929 #define ALT_GIC_DIST_GICD_ICFGR7_RESET 0x55555555
23930 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR7 register from the beginning of the component. */
23931 #define ALT_GIC_DIST_GICD_ICFGR7_OFST 0xc1c
23932 
23933 /*
23934  * Register : GICD_ICFGR8
23935  *
23936  * Interrupt Configuration Registers
23937  *
23938  * Register Layout
23939  *
23940  * Bits | Access | Reset | Description
23941  * :-------|:-------|:-----------|:------------
23942  * [31:0] | RW | 0x55555555 | Empty
23943  *
23944  */
23945 /*
23946  * Field : Empty - fld
23947  *
23948  * Placeholder
23949  *
23950  * Field Access Macros:
23951  *
23952  */
23953 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR8_FLD register field. */
23954 #define ALT_GIC_DIST_GICD_ICFGR8_FLD_LSB 0
23955 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR8_FLD register field. */
23956 #define ALT_GIC_DIST_GICD_ICFGR8_FLD_MSB 31
23957 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR8_FLD register field. */
23958 #define ALT_GIC_DIST_GICD_ICFGR8_FLD_WIDTH 32
23959 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR8_FLD register field value. */
23960 #define ALT_GIC_DIST_GICD_ICFGR8_FLD_SET_MSK 0xffffffff
23961 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR8_FLD register field value. */
23962 #define ALT_GIC_DIST_GICD_ICFGR8_FLD_CLR_MSK 0x00000000
23963 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR8_FLD register field. */
23964 #define ALT_GIC_DIST_GICD_ICFGR8_FLD_RESET 0x55555555
23965 /* Extracts the ALT_GIC_DIST_GICD_ICFGR8_FLD field value from a register. */
23966 #define ALT_GIC_DIST_GICD_ICFGR8_FLD_GET(value) (((value) & 0xffffffff) >> 0)
23967 /* Produces a ALT_GIC_DIST_GICD_ICFGR8_FLD register field value suitable for setting the register. */
23968 #define ALT_GIC_DIST_GICD_ICFGR8_FLD_SET(value) (((value) << 0) & 0xffffffff)
23969 
23970 #ifndef __ASSEMBLY__
23971 /*
23972  * WARNING: The C register and register group struct declarations are provided for
23973  * convenience and illustrative purposes. They should, however, be used with
23974  * caution as the C language standard provides no guarantees about the alignment or
23975  * atomicity of device memory accesses. The recommended practice for coding device
23976  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
23977  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
23978  * alt_write_dword() functions for 64 bit registers.
23979  *
23980  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR8.
23981  */
23982 struct ALT_GIC_DIST_GICD_ICFGR8_s
23983 {
23984  volatile uint32_t fld : 32; /* Empty */
23985 };
23986 
23987 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR8. */
23988 typedef struct ALT_GIC_DIST_GICD_ICFGR8_s ALT_GIC_DIST_GICD_ICFGR8_t;
23989 #endif /* __ASSEMBLY__ */
23990 
23991 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR8 register. */
23992 #define ALT_GIC_DIST_GICD_ICFGR8_RESET 0x55555555
23993 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR8 register from the beginning of the component. */
23994 #define ALT_GIC_DIST_GICD_ICFGR8_OFST 0xc20
23995 
23996 /*
23997  * Register : GICD_ICFGR9
23998  *
23999  * Interrupt Configuration Registers
24000  *
24001  * Register Layout
24002  *
24003  * Bits | Access | Reset | Description
24004  * :-------|:-------|:-----------|:------------
24005  * [31:0] | RW | 0x55555555 | Empty
24006  *
24007  */
24008 /*
24009  * Field : Empty - fld
24010  *
24011  * Placeholder
24012  *
24013  * Field Access Macros:
24014  *
24015  */
24016 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR9_FLD register field. */
24017 #define ALT_GIC_DIST_GICD_ICFGR9_FLD_LSB 0
24018 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR9_FLD register field. */
24019 #define ALT_GIC_DIST_GICD_ICFGR9_FLD_MSB 31
24020 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR9_FLD register field. */
24021 #define ALT_GIC_DIST_GICD_ICFGR9_FLD_WIDTH 32
24022 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR9_FLD register field value. */
24023 #define ALT_GIC_DIST_GICD_ICFGR9_FLD_SET_MSK 0xffffffff
24024 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR9_FLD register field value. */
24025 #define ALT_GIC_DIST_GICD_ICFGR9_FLD_CLR_MSK 0x00000000
24026 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR9_FLD register field. */
24027 #define ALT_GIC_DIST_GICD_ICFGR9_FLD_RESET 0x55555555
24028 /* Extracts the ALT_GIC_DIST_GICD_ICFGR9_FLD field value from a register. */
24029 #define ALT_GIC_DIST_GICD_ICFGR9_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24030 /* Produces a ALT_GIC_DIST_GICD_ICFGR9_FLD register field value suitable for setting the register. */
24031 #define ALT_GIC_DIST_GICD_ICFGR9_FLD_SET(value) (((value) << 0) & 0xffffffff)
24032 
24033 #ifndef __ASSEMBLY__
24034 /*
24035  * WARNING: The C register and register group struct declarations are provided for
24036  * convenience and illustrative purposes. They should, however, be used with
24037  * caution as the C language standard provides no guarantees about the alignment or
24038  * atomicity of device memory accesses. The recommended practice for coding device
24039  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
24040  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
24041  * alt_write_dword() functions for 64 bit registers.
24042  *
24043  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR9.
24044  */
24045 struct ALT_GIC_DIST_GICD_ICFGR9_s
24046 {
24047  volatile uint32_t fld : 32; /* Empty */
24048 };
24049 
24050 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR9. */
24051 typedef struct ALT_GIC_DIST_GICD_ICFGR9_s ALT_GIC_DIST_GICD_ICFGR9_t;
24052 #endif /* __ASSEMBLY__ */
24053 
24054 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR9 register. */
24055 #define ALT_GIC_DIST_GICD_ICFGR9_RESET 0x55555555
24056 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR9 register from the beginning of the component. */
24057 #define ALT_GIC_DIST_GICD_ICFGR9_OFST 0xc24
24058 
24059 /*
24060  * Register : GICD_ICFGR10
24061  *
24062  * Interrupt Configuration Registers
24063  *
24064  * Register Layout
24065  *
24066  * Bits | Access | Reset | Description
24067  * :-------|:-------|:-----------|:------------
24068  * [31:0] | RW | 0x55555555 | Empty
24069  *
24070  */
24071 /*
24072  * Field : Empty - fld
24073  *
24074  * Placeholder
24075  *
24076  * Field Access Macros:
24077  *
24078  */
24079 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR10_FLD register field. */
24080 #define ALT_GIC_DIST_GICD_ICFGR10_FLD_LSB 0
24081 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR10_FLD register field. */
24082 #define ALT_GIC_DIST_GICD_ICFGR10_FLD_MSB 31
24083 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR10_FLD register field. */
24084 #define ALT_GIC_DIST_GICD_ICFGR10_FLD_WIDTH 32
24085 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR10_FLD register field value. */
24086 #define ALT_GIC_DIST_GICD_ICFGR10_FLD_SET_MSK 0xffffffff
24087 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR10_FLD register field value. */
24088 #define ALT_GIC_DIST_GICD_ICFGR10_FLD_CLR_MSK 0x00000000
24089 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR10_FLD register field. */
24090 #define ALT_GIC_DIST_GICD_ICFGR10_FLD_RESET 0x55555555
24091 /* Extracts the ALT_GIC_DIST_GICD_ICFGR10_FLD field value from a register. */
24092 #define ALT_GIC_DIST_GICD_ICFGR10_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24093 /* Produces a ALT_GIC_DIST_GICD_ICFGR10_FLD register field value suitable for setting the register. */
24094 #define ALT_GIC_DIST_GICD_ICFGR10_FLD_SET(value) (((value) << 0) & 0xffffffff)
24095 
24096 #ifndef __ASSEMBLY__
24097 /*
24098  * WARNING: The C register and register group struct declarations are provided for
24099  * convenience and illustrative purposes. They should, however, be used with
24100  * caution as the C language standard provides no guarantees about the alignment or
24101  * atomicity of device memory accesses. The recommended practice for coding device
24102  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
24103  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
24104  * alt_write_dword() functions for 64 bit registers.
24105  *
24106  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR10.
24107  */
24108 struct ALT_GIC_DIST_GICD_ICFGR10_s
24109 {
24110  volatile uint32_t fld : 32; /* Empty */
24111 };
24112 
24113 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR10. */
24114 typedef struct ALT_GIC_DIST_GICD_ICFGR10_s ALT_GIC_DIST_GICD_ICFGR10_t;
24115 #endif /* __ASSEMBLY__ */
24116 
24117 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR10 register. */
24118 #define ALT_GIC_DIST_GICD_ICFGR10_RESET 0x55555555
24119 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR10 register from the beginning of the component. */
24120 #define ALT_GIC_DIST_GICD_ICFGR10_OFST 0xc28
24121 
24122 /*
24123  * Register : GICD_ICFGR11
24124  *
24125  * Interrupt Configuration Registers
24126  *
24127  * Register Layout
24128  *
24129  * Bits | Access | Reset | Description
24130  * :-------|:-------|:-----------|:------------
24131  * [31:0] | RW | 0x55555555 | Empty
24132  *
24133  */
24134 /*
24135  * Field : Empty - fld
24136  *
24137  * Placeholder
24138  *
24139  * Field Access Macros:
24140  *
24141  */
24142 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR11_FLD register field. */
24143 #define ALT_GIC_DIST_GICD_ICFGR11_FLD_LSB 0
24144 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR11_FLD register field. */
24145 #define ALT_GIC_DIST_GICD_ICFGR11_FLD_MSB 31
24146 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR11_FLD register field. */
24147 #define ALT_GIC_DIST_GICD_ICFGR11_FLD_WIDTH 32
24148 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR11_FLD register field value. */
24149 #define ALT_GIC_DIST_GICD_ICFGR11_FLD_SET_MSK 0xffffffff
24150 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR11_FLD register field value. */
24151 #define ALT_GIC_DIST_GICD_ICFGR11_FLD_CLR_MSK 0x00000000
24152 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR11_FLD register field. */
24153 #define ALT_GIC_DIST_GICD_ICFGR11_FLD_RESET 0x55555555
24154 /* Extracts the ALT_GIC_DIST_GICD_ICFGR11_FLD field value from a register. */
24155 #define ALT_GIC_DIST_GICD_ICFGR11_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24156 /* Produces a ALT_GIC_DIST_GICD_ICFGR11_FLD register field value suitable for setting the register. */
24157 #define ALT_GIC_DIST_GICD_ICFGR11_FLD_SET(value) (((value) << 0) & 0xffffffff)
24158 
24159 #ifndef __ASSEMBLY__
24160 /*
24161  * WARNING: The C register and register group struct declarations are provided for
24162  * convenience and illustrative purposes. They should, however, be used with
24163  * caution as the C language standard provides no guarantees about the alignment or
24164  * atomicity of device memory accesses. The recommended practice for coding device
24165  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
24166  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
24167  * alt_write_dword() functions for 64 bit registers.
24168  *
24169  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR11.
24170  */
24171 struct ALT_GIC_DIST_GICD_ICFGR11_s
24172 {
24173  volatile uint32_t fld : 32; /* Empty */
24174 };
24175 
24176 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR11. */
24177 typedef struct ALT_GIC_DIST_GICD_ICFGR11_s ALT_GIC_DIST_GICD_ICFGR11_t;
24178 #endif /* __ASSEMBLY__ */
24179 
24180 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR11 register. */
24181 #define ALT_GIC_DIST_GICD_ICFGR11_RESET 0x55555555
24182 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR11 register from the beginning of the component. */
24183 #define ALT_GIC_DIST_GICD_ICFGR11_OFST 0xc2c
24184 
24185 /*
24186  * Register : GICD_ICFGR12
24187  *
24188  * Interrupt Configuration Registers
24189  *
24190  * Register Layout
24191  *
24192  * Bits | Access | Reset | Description
24193  * :-------|:-------|:-----------|:------------
24194  * [31:0] | RW | 0x55555555 | Empty
24195  *
24196  */
24197 /*
24198  * Field : Empty - fld
24199  *
24200  * Placeholder
24201  *
24202  * Field Access Macros:
24203  *
24204  */
24205 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR12_FLD register field. */
24206 #define ALT_GIC_DIST_GICD_ICFGR12_FLD_LSB 0
24207 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR12_FLD register field. */
24208 #define ALT_GIC_DIST_GICD_ICFGR12_FLD_MSB 31
24209 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR12_FLD register field. */
24210 #define ALT_GIC_DIST_GICD_ICFGR12_FLD_WIDTH 32
24211 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR12_FLD register field value. */
24212 #define ALT_GIC_DIST_GICD_ICFGR12_FLD_SET_MSK 0xffffffff
24213 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR12_FLD register field value. */
24214 #define ALT_GIC_DIST_GICD_ICFGR12_FLD_CLR_MSK 0x00000000
24215 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR12_FLD register field. */
24216 #define ALT_GIC_DIST_GICD_ICFGR12_FLD_RESET 0x55555555
24217 /* Extracts the ALT_GIC_DIST_GICD_ICFGR12_FLD field value from a register. */
24218 #define ALT_GIC_DIST_GICD_ICFGR12_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24219 /* Produces a ALT_GIC_DIST_GICD_ICFGR12_FLD register field value suitable for setting the register. */
24220 #define ALT_GIC_DIST_GICD_ICFGR12_FLD_SET(value) (((value) << 0) & 0xffffffff)
24221 
24222 #ifndef __ASSEMBLY__
24223 /*
24224  * WARNING: The C register and register group struct declarations are provided for
24225  * convenience and illustrative purposes. They should, however, be used with
24226  * caution as the C language standard provides no guarantees about the alignment or
24227  * atomicity of device memory accesses. The recommended practice for coding device
24228  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
24229  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
24230  * alt_write_dword() functions for 64 bit registers.
24231  *
24232  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR12.
24233  */
24234 struct ALT_GIC_DIST_GICD_ICFGR12_s
24235 {
24236  volatile uint32_t fld : 32; /* Empty */
24237 };
24238 
24239 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR12. */
24240 typedef struct ALT_GIC_DIST_GICD_ICFGR12_s ALT_GIC_DIST_GICD_ICFGR12_t;
24241 #endif /* __ASSEMBLY__ */
24242 
24243 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR12 register. */
24244 #define ALT_GIC_DIST_GICD_ICFGR12_RESET 0x55555555
24245 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR12 register from the beginning of the component. */
24246 #define ALT_GIC_DIST_GICD_ICFGR12_OFST 0xc30
24247 
24248 /*
24249  * Register : GICD_ICFGR13
24250  *
24251  * Interrupt Configuration Registers
24252  *
24253  * Register Layout
24254  *
24255  * Bits | Access | Reset | Description
24256  * :-------|:-------|:-----------|:------------
24257  * [31:0] | RW | 0x55555555 | Empty
24258  *
24259  */
24260 /*
24261  * Field : Empty - fld
24262  *
24263  * Placeholder
24264  *
24265  * Field Access Macros:
24266  *
24267  */
24268 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR13_FLD register field. */
24269 #define ALT_GIC_DIST_GICD_ICFGR13_FLD_LSB 0
24270 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR13_FLD register field. */
24271 #define ALT_GIC_DIST_GICD_ICFGR13_FLD_MSB 31
24272 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR13_FLD register field. */
24273 #define ALT_GIC_DIST_GICD_ICFGR13_FLD_WIDTH 32
24274 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR13_FLD register field value. */
24275 #define ALT_GIC_DIST_GICD_ICFGR13_FLD_SET_MSK 0xffffffff
24276 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR13_FLD register field value. */
24277 #define ALT_GIC_DIST_GICD_ICFGR13_FLD_CLR_MSK 0x00000000
24278 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR13_FLD register field. */
24279 #define ALT_GIC_DIST_GICD_ICFGR13_FLD_RESET 0x55555555
24280 /* Extracts the ALT_GIC_DIST_GICD_ICFGR13_FLD field value from a register. */
24281 #define ALT_GIC_DIST_GICD_ICFGR13_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24282 /* Produces a ALT_GIC_DIST_GICD_ICFGR13_FLD register field value suitable for setting the register. */
24283 #define ALT_GIC_DIST_GICD_ICFGR13_FLD_SET(value) (((value) << 0) & 0xffffffff)
24284 
24285 #ifndef __ASSEMBLY__
24286 /*
24287  * WARNING: The C register and register group struct declarations are provided for
24288  * convenience and illustrative purposes. They should, however, be used with
24289  * caution as the C language standard provides no guarantees about the alignment or
24290  * atomicity of device memory accesses. The recommended practice for coding device
24291  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
24292  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
24293  * alt_write_dword() functions for 64 bit registers.
24294  *
24295  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR13.
24296  */
24297 struct ALT_GIC_DIST_GICD_ICFGR13_s
24298 {
24299  volatile uint32_t fld : 32; /* Empty */
24300 };
24301 
24302 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR13. */
24303 typedef struct ALT_GIC_DIST_GICD_ICFGR13_s ALT_GIC_DIST_GICD_ICFGR13_t;
24304 #endif /* __ASSEMBLY__ */
24305 
24306 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR13 register. */
24307 #define ALT_GIC_DIST_GICD_ICFGR13_RESET 0x55555555
24308 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR13 register from the beginning of the component. */
24309 #define ALT_GIC_DIST_GICD_ICFGR13_OFST 0xc34
24310 
24311 /*
24312  * Register : GICD_ICFGR14
24313  *
24314  * Interrupt Configuration Registers
24315  *
24316  * Register Layout
24317  *
24318  * Bits | Access | Reset | Description
24319  * :-------|:-------|:-----------|:------------
24320  * [31:0] | RW | 0x55555555 | Empty
24321  *
24322  */
24323 /*
24324  * Field : Empty - fld
24325  *
24326  * Placeholder
24327  *
24328  * Field Access Macros:
24329  *
24330  */
24331 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR14_FLD register field. */
24332 #define ALT_GIC_DIST_GICD_ICFGR14_FLD_LSB 0
24333 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR14_FLD register field. */
24334 #define ALT_GIC_DIST_GICD_ICFGR14_FLD_MSB 31
24335 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR14_FLD register field. */
24336 #define ALT_GIC_DIST_GICD_ICFGR14_FLD_WIDTH 32
24337 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR14_FLD register field value. */
24338 #define ALT_GIC_DIST_GICD_ICFGR14_FLD_SET_MSK 0xffffffff
24339 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR14_FLD register field value. */
24340 #define ALT_GIC_DIST_GICD_ICFGR14_FLD_CLR_MSK 0x00000000
24341 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR14_FLD register field. */
24342 #define ALT_GIC_DIST_GICD_ICFGR14_FLD_RESET 0x55555555
24343 /* Extracts the ALT_GIC_DIST_GICD_ICFGR14_FLD field value from a register. */
24344 #define ALT_GIC_DIST_GICD_ICFGR14_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24345 /* Produces a ALT_GIC_DIST_GICD_ICFGR14_FLD register field value suitable for setting the register. */
24346 #define ALT_GIC_DIST_GICD_ICFGR14_FLD_SET(value) (((value) << 0) & 0xffffffff)
24347 
24348 #ifndef __ASSEMBLY__
24349 /*
24350  * WARNING: The C register and register group struct declarations are provided for
24351  * convenience and illustrative purposes. They should, however, be used with
24352  * caution as the C language standard provides no guarantees about the alignment or
24353  * atomicity of device memory accesses. The recommended practice for coding device
24354  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
24355  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
24356  * alt_write_dword() functions for 64 bit registers.
24357  *
24358  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR14.
24359  */
24360 struct ALT_GIC_DIST_GICD_ICFGR14_s
24361 {
24362  volatile uint32_t fld : 32; /* Empty */
24363 };
24364 
24365 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR14. */
24366 typedef struct ALT_GIC_DIST_GICD_ICFGR14_s ALT_GIC_DIST_GICD_ICFGR14_t;
24367 #endif /* __ASSEMBLY__ */
24368 
24369 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR14 register. */
24370 #define ALT_GIC_DIST_GICD_ICFGR14_RESET 0x55555555
24371 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR14 register from the beginning of the component. */
24372 #define ALT_GIC_DIST_GICD_ICFGR14_OFST 0xc38
24373 
24374 /*
24375  * Register : GICD_ICFGR15
24376  *
24377  * Interrupt Configuration Registers
24378  *
24379  * Register Layout
24380  *
24381  * Bits | Access | Reset | Description
24382  * :-------|:-------|:-----------|:------------
24383  * [31:0] | RW | 0x55555555 | Empty
24384  *
24385  */
24386 /*
24387  * Field : Empty - fld
24388  *
24389  * Placeholder
24390  *
24391  * Field Access Macros:
24392  *
24393  */
24394 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR15_FLD register field. */
24395 #define ALT_GIC_DIST_GICD_ICFGR15_FLD_LSB 0
24396 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR15_FLD register field. */
24397 #define ALT_GIC_DIST_GICD_ICFGR15_FLD_MSB 31
24398 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR15_FLD register field. */
24399 #define ALT_GIC_DIST_GICD_ICFGR15_FLD_WIDTH 32
24400 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR15_FLD register field value. */
24401 #define ALT_GIC_DIST_GICD_ICFGR15_FLD_SET_MSK 0xffffffff
24402 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR15_FLD register field value. */
24403 #define ALT_GIC_DIST_GICD_ICFGR15_FLD_CLR_MSK 0x00000000
24404 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR15_FLD register field. */
24405 #define ALT_GIC_DIST_GICD_ICFGR15_FLD_RESET 0x55555555
24406 /* Extracts the ALT_GIC_DIST_GICD_ICFGR15_FLD field value from a register. */
24407 #define ALT_GIC_DIST_GICD_ICFGR15_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24408 /* Produces a ALT_GIC_DIST_GICD_ICFGR15_FLD register field value suitable for setting the register. */
24409 #define ALT_GIC_DIST_GICD_ICFGR15_FLD_SET(value) (((value) << 0) & 0xffffffff)
24410 
24411 #ifndef __ASSEMBLY__
24412 /*
24413  * WARNING: The C register and register group struct declarations are provided for
24414  * convenience and illustrative purposes. They should, however, be used with
24415  * caution as the C language standard provides no guarantees about the alignment or
24416  * atomicity of device memory accesses. The recommended practice for coding device
24417  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
24418  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
24419  * alt_write_dword() functions for 64 bit registers.
24420  *
24421  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR15.
24422  */
24423 struct ALT_GIC_DIST_GICD_ICFGR15_s
24424 {
24425  volatile uint32_t fld : 32; /* Empty */
24426 };
24427 
24428 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR15. */
24429 typedef struct ALT_GIC_DIST_GICD_ICFGR15_s ALT_GIC_DIST_GICD_ICFGR15_t;
24430 #endif /* __ASSEMBLY__ */
24431 
24432 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR15 register. */
24433 #define ALT_GIC_DIST_GICD_ICFGR15_RESET 0x55555555
24434 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR15 register from the beginning of the component. */
24435 #define ALT_GIC_DIST_GICD_ICFGR15_OFST 0xc3c
24436 
24437 /*
24438  * Register : GICD_ICFGR16
24439  *
24440  * Interrupt Configuration Registers
24441  *
24442  * Register Layout
24443  *
24444  * Bits | Access | Reset | Description
24445  * :-------|:-------|:-----------|:------------
24446  * [31:0] | RW | 0x55555555 | Empty
24447  *
24448  */
24449 /*
24450  * Field : Empty - fld
24451  *
24452  * Placeholder
24453  *
24454  * Field Access Macros:
24455  *
24456  */
24457 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR16_FLD register field. */
24458 #define ALT_GIC_DIST_GICD_ICFGR16_FLD_LSB 0
24459 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR16_FLD register field. */
24460 #define ALT_GIC_DIST_GICD_ICFGR16_FLD_MSB 31
24461 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR16_FLD register field. */
24462 #define ALT_GIC_DIST_GICD_ICFGR16_FLD_WIDTH 32
24463 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR16_FLD register field value. */
24464 #define ALT_GIC_DIST_GICD_ICFGR16_FLD_SET_MSK 0xffffffff
24465 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR16_FLD register field value. */
24466 #define ALT_GIC_DIST_GICD_ICFGR16_FLD_CLR_MSK 0x00000000
24467 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR16_FLD register field. */
24468 #define ALT_GIC_DIST_GICD_ICFGR16_FLD_RESET 0x55555555
24469 /* Extracts the ALT_GIC_DIST_GICD_ICFGR16_FLD field value from a register. */
24470 #define ALT_GIC_DIST_GICD_ICFGR16_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24471 /* Produces a ALT_GIC_DIST_GICD_ICFGR16_FLD register field value suitable for setting the register. */
24472 #define ALT_GIC_DIST_GICD_ICFGR16_FLD_SET(value) (((value) << 0) & 0xffffffff)
24473 
24474 #ifndef __ASSEMBLY__
24475 /*
24476  * WARNING: The C register and register group struct declarations are provided for
24477  * convenience and illustrative purposes. They should, however, be used with
24478  * caution as the C language standard provides no guarantees about the alignment or
24479  * atomicity of device memory accesses. The recommended practice for coding device
24480  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
24481  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
24482  * alt_write_dword() functions for 64 bit registers.
24483  *
24484  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR16.
24485  */
24486 struct ALT_GIC_DIST_GICD_ICFGR16_s
24487 {
24488  volatile uint32_t fld : 32; /* Empty */
24489 };
24490 
24491 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR16. */
24492 typedef struct ALT_GIC_DIST_GICD_ICFGR16_s ALT_GIC_DIST_GICD_ICFGR16_t;
24493 #endif /* __ASSEMBLY__ */
24494 
24495 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR16 register. */
24496 #define ALT_GIC_DIST_GICD_ICFGR16_RESET 0x55555555
24497 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR16 register from the beginning of the component. */
24498 #define ALT_GIC_DIST_GICD_ICFGR16_OFST 0xc40
24499 
24500 /*
24501  * Register : GICD_ICFGR17
24502  *
24503  * Interrupt Configuration Registers
24504  *
24505  * Register Layout
24506  *
24507  * Bits | Access | Reset | Description
24508  * :-------|:-------|:-----------|:------------
24509  * [31:0] | RW | 0x55555555 | Empty
24510  *
24511  */
24512 /*
24513  * Field : Empty - fld
24514  *
24515  * Placeholder
24516  *
24517  * Field Access Macros:
24518  *
24519  */
24520 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR17_FLD register field. */
24521 #define ALT_GIC_DIST_GICD_ICFGR17_FLD_LSB 0
24522 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR17_FLD register field. */
24523 #define ALT_GIC_DIST_GICD_ICFGR17_FLD_MSB 31
24524 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR17_FLD register field. */
24525 #define ALT_GIC_DIST_GICD_ICFGR17_FLD_WIDTH 32
24526 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR17_FLD register field value. */
24527 #define ALT_GIC_DIST_GICD_ICFGR17_FLD_SET_MSK 0xffffffff
24528 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR17_FLD register field value. */
24529 #define ALT_GIC_DIST_GICD_ICFGR17_FLD_CLR_MSK 0x00000000
24530 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR17_FLD register field. */
24531 #define ALT_GIC_DIST_GICD_ICFGR17_FLD_RESET 0x55555555
24532 /* Extracts the ALT_GIC_DIST_GICD_ICFGR17_FLD field value from a register. */
24533 #define ALT_GIC_DIST_GICD_ICFGR17_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24534 /* Produces a ALT_GIC_DIST_GICD_ICFGR17_FLD register field value suitable for setting the register. */
24535 #define ALT_GIC_DIST_GICD_ICFGR17_FLD_SET(value) (((value) << 0) & 0xffffffff)
24536 
24537 #ifndef __ASSEMBLY__
24538 /*
24539  * WARNING: The C register and register group struct declarations are provided for
24540  * convenience and illustrative purposes. They should, however, be used with
24541  * caution as the C language standard provides no guarantees about the alignment or
24542  * atomicity of device memory accesses. The recommended practice for coding device
24543  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
24544  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
24545  * alt_write_dword() functions for 64 bit registers.
24546  *
24547  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR17.
24548  */
24549 struct ALT_GIC_DIST_GICD_ICFGR17_s
24550 {
24551  volatile uint32_t fld : 32; /* Empty */
24552 };
24553 
24554 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR17. */
24555 typedef struct ALT_GIC_DIST_GICD_ICFGR17_s ALT_GIC_DIST_GICD_ICFGR17_t;
24556 #endif /* __ASSEMBLY__ */
24557 
24558 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR17 register. */
24559 #define ALT_GIC_DIST_GICD_ICFGR17_RESET 0x55555555
24560 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR17 register from the beginning of the component. */
24561 #define ALT_GIC_DIST_GICD_ICFGR17_OFST 0xc44
24562 
24563 /*
24564  * Register : GICD_ICFGR18
24565  *
24566  * Interrupt Configuration Registers
24567  *
24568  * Register Layout
24569  *
24570  * Bits | Access | Reset | Description
24571  * :-------|:-------|:-----------|:------------
24572  * [31:0] | RW | 0x55555555 | Empty
24573  *
24574  */
24575 /*
24576  * Field : Empty - fld
24577  *
24578  * Placeholder
24579  *
24580  * Field Access Macros:
24581  *
24582  */
24583 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR18_FLD register field. */
24584 #define ALT_GIC_DIST_GICD_ICFGR18_FLD_LSB 0
24585 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR18_FLD register field. */
24586 #define ALT_GIC_DIST_GICD_ICFGR18_FLD_MSB 31
24587 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR18_FLD register field. */
24588 #define ALT_GIC_DIST_GICD_ICFGR18_FLD_WIDTH 32
24589 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR18_FLD register field value. */
24590 #define ALT_GIC_DIST_GICD_ICFGR18_FLD_SET_MSK 0xffffffff
24591 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR18_FLD register field value. */
24592 #define ALT_GIC_DIST_GICD_ICFGR18_FLD_CLR_MSK 0x00000000
24593 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR18_FLD register field. */
24594 #define ALT_GIC_DIST_GICD_ICFGR18_FLD_RESET 0x55555555
24595 /* Extracts the ALT_GIC_DIST_GICD_ICFGR18_FLD field value from a register. */
24596 #define ALT_GIC_DIST_GICD_ICFGR18_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24597 /* Produces a ALT_GIC_DIST_GICD_ICFGR18_FLD register field value suitable for setting the register. */
24598 #define ALT_GIC_DIST_GICD_ICFGR18_FLD_SET(value) (((value) << 0) & 0xffffffff)
24599 
24600 #ifndef __ASSEMBLY__
24601 /*
24602  * WARNING: The C register and register group struct declarations are provided for
24603  * convenience and illustrative purposes. They should, however, be used with
24604  * caution as the C language standard provides no guarantees about the alignment or
24605  * atomicity of device memory accesses. The recommended practice for coding device
24606  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
24607  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
24608  * alt_write_dword() functions for 64 bit registers.
24609  *
24610  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR18.
24611  */
24612 struct ALT_GIC_DIST_GICD_ICFGR18_s
24613 {
24614  volatile uint32_t fld : 32; /* Empty */
24615 };
24616 
24617 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR18. */
24618 typedef struct ALT_GIC_DIST_GICD_ICFGR18_s ALT_GIC_DIST_GICD_ICFGR18_t;
24619 #endif /* __ASSEMBLY__ */
24620 
24621 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR18 register. */
24622 #define ALT_GIC_DIST_GICD_ICFGR18_RESET 0x55555555
24623 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR18 register from the beginning of the component. */
24624 #define ALT_GIC_DIST_GICD_ICFGR18_OFST 0xc48
24625 
24626 /*
24627  * Register : GICD_ICFGR19
24628  *
24629  * Interrupt Configuration Registers
24630  *
24631  * Register Layout
24632  *
24633  * Bits | Access | Reset | Description
24634  * :-------|:-------|:-----------|:------------
24635  * [31:0] | RW | 0x55555555 | Empty
24636  *
24637  */
24638 /*
24639  * Field : Empty - fld
24640  *
24641  * Placeholder
24642  *
24643  * Field Access Macros:
24644  *
24645  */
24646 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR19_FLD register field. */
24647 #define ALT_GIC_DIST_GICD_ICFGR19_FLD_LSB 0
24648 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR19_FLD register field. */
24649 #define ALT_GIC_DIST_GICD_ICFGR19_FLD_MSB 31
24650 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR19_FLD register field. */
24651 #define ALT_GIC_DIST_GICD_ICFGR19_FLD_WIDTH 32
24652 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR19_FLD register field value. */
24653 #define ALT_GIC_DIST_GICD_ICFGR19_FLD_SET_MSK 0xffffffff
24654 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR19_FLD register field value. */
24655 #define ALT_GIC_DIST_GICD_ICFGR19_FLD_CLR_MSK 0x00000000
24656 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR19_FLD register field. */
24657 #define ALT_GIC_DIST_GICD_ICFGR19_FLD_RESET 0x55555555
24658 /* Extracts the ALT_GIC_DIST_GICD_ICFGR19_FLD field value from a register. */
24659 #define ALT_GIC_DIST_GICD_ICFGR19_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24660 /* Produces a ALT_GIC_DIST_GICD_ICFGR19_FLD register field value suitable for setting the register. */
24661 #define ALT_GIC_DIST_GICD_ICFGR19_FLD_SET(value) (((value) << 0) & 0xffffffff)
24662 
24663 #ifndef __ASSEMBLY__
24664 /*
24665  * WARNING: The C register and register group struct declarations are provided for
24666  * convenience and illustrative purposes. They should, however, be used with
24667  * caution as the C language standard provides no guarantees about the alignment or
24668  * atomicity of device memory accesses. The recommended practice for coding device
24669  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
24670  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
24671  * alt_write_dword() functions for 64 bit registers.
24672  *
24673  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR19.
24674  */
24675 struct ALT_GIC_DIST_GICD_ICFGR19_s
24676 {
24677  volatile uint32_t fld : 32; /* Empty */
24678 };
24679 
24680 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR19. */
24681 typedef struct ALT_GIC_DIST_GICD_ICFGR19_s ALT_GIC_DIST_GICD_ICFGR19_t;
24682 #endif /* __ASSEMBLY__ */
24683 
24684 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR19 register. */
24685 #define ALT_GIC_DIST_GICD_ICFGR19_RESET 0x55555555
24686 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR19 register from the beginning of the component. */
24687 #define ALT_GIC_DIST_GICD_ICFGR19_OFST 0xc4c
24688 
24689 /*
24690  * Register : GICD_ICFGR20
24691  *
24692  * Interrupt Configuration Registers
24693  *
24694  * Register Layout
24695  *
24696  * Bits | Access | Reset | Description
24697  * :-------|:-------|:-----------|:------------
24698  * [31:0] | RW | 0x55555555 | Empty
24699  *
24700  */
24701 /*
24702  * Field : Empty - fld
24703  *
24704  * Placeholder
24705  *
24706  * Field Access Macros:
24707  *
24708  */
24709 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR20_FLD register field. */
24710 #define ALT_GIC_DIST_GICD_ICFGR20_FLD_LSB 0
24711 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR20_FLD register field. */
24712 #define ALT_GIC_DIST_GICD_ICFGR20_FLD_MSB 31
24713 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR20_FLD register field. */
24714 #define ALT_GIC_DIST_GICD_ICFGR20_FLD_WIDTH 32
24715 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR20_FLD register field value. */
24716 #define ALT_GIC_DIST_GICD_ICFGR20_FLD_SET_MSK 0xffffffff
24717 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR20_FLD register field value. */
24718 #define ALT_GIC_DIST_GICD_ICFGR20_FLD_CLR_MSK 0x00000000
24719 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR20_FLD register field. */
24720 #define ALT_GIC_DIST_GICD_ICFGR20_FLD_RESET 0x55555555
24721 /* Extracts the ALT_GIC_DIST_GICD_ICFGR20_FLD field value from a register. */
24722 #define ALT_GIC_DIST_GICD_ICFGR20_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24723 /* Produces a ALT_GIC_DIST_GICD_ICFGR20_FLD register field value suitable for setting the register. */
24724 #define ALT_GIC_DIST_GICD_ICFGR20_FLD_SET(value) (((value) << 0) & 0xffffffff)
24725 
24726 #ifndef __ASSEMBLY__
24727 /*
24728  * WARNING: The C register and register group struct declarations are provided for
24729  * convenience and illustrative purposes. They should, however, be used with
24730  * caution as the C language standard provides no guarantees about the alignment or
24731  * atomicity of device memory accesses. The recommended practice for coding device
24732  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
24733  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
24734  * alt_write_dword() functions for 64 bit registers.
24735  *
24736  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR20.
24737  */
24738 struct ALT_GIC_DIST_GICD_ICFGR20_s
24739 {
24740  volatile uint32_t fld : 32; /* Empty */
24741 };
24742 
24743 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR20. */
24744 typedef struct ALT_GIC_DIST_GICD_ICFGR20_s ALT_GIC_DIST_GICD_ICFGR20_t;
24745 #endif /* __ASSEMBLY__ */
24746 
24747 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR20 register. */
24748 #define ALT_GIC_DIST_GICD_ICFGR20_RESET 0x55555555
24749 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR20 register from the beginning of the component. */
24750 #define ALT_GIC_DIST_GICD_ICFGR20_OFST 0xc50
24751 
24752 /*
24753  * Register : GICD_ICFGR21
24754  *
24755  * Interrupt Configuration Registers
24756  *
24757  * Register Layout
24758  *
24759  * Bits | Access | Reset | Description
24760  * :-------|:-------|:-----------|:------------
24761  * [31:0] | RW | 0x55555555 | Empty
24762  *
24763  */
24764 /*
24765  * Field : Empty - fld
24766  *
24767  * Placeholder
24768  *
24769  * Field Access Macros:
24770  *
24771  */
24772 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR21_FLD register field. */
24773 #define ALT_GIC_DIST_GICD_ICFGR21_FLD_LSB 0
24774 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR21_FLD register field. */
24775 #define ALT_GIC_DIST_GICD_ICFGR21_FLD_MSB 31
24776 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR21_FLD register field. */
24777 #define ALT_GIC_DIST_GICD_ICFGR21_FLD_WIDTH 32
24778 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR21_FLD register field value. */
24779 #define ALT_GIC_DIST_GICD_ICFGR21_FLD_SET_MSK 0xffffffff
24780 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR21_FLD register field value. */
24781 #define ALT_GIC_DIST_GICD_ICFGR21_FLD_CLR_MSK 0x00000000
24782 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR21_FLD register field. */
24783 #define ALT_GIC_DIST_GICD_ICFGR21_FLD_RESET 0x55555555
24784 /* Extracts the ALT_GIC_DIST_GICD_ICFGR21_FLD field value from a register. */
24785 #define ALT_GIC_DIST_GICD_ICFGR21_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24786 /* Produces a ALT_GIC_DIST_GICD_ICFGR21_FLD register field value suitable for setting the register. */
24787 #define ALT_GIC_DIST_GICD_ICFGR21_FLD_SET(value) (((value) << 0) & 0xffffffff)
24788 
24789 #ifndef __ASSEMBLY__
24790 /*
24791  * WARNING: The C register and register group struct declarations are provided for
24792  * convenience and illustrative purposes. They should, however, be used with
24793  * caution as the C language standard provides no guarantees about the alignment or
24794  * atomicity of device memory accesses. The recommended practice for coding device
24795  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
24796  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
24797  * alt_write_dword() functions for 64 bit registers.
24798  *
24799  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR21.
24800  */
24801 struct ALT_GIC_DIST_GICD_ICFGR21_s
24802 {
24803  volatile uint32_t fld : 32; /* Empty */
24804 };
24805 
24806 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR21. */
24807 typedef struct ALT_GIC_DIST_GICD_ICFGR21_s ALT_GIC_DIST_GICD_ICFGR21_t;
24808 #endif /* __ASSEMBLY__ */
24809 
24810 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR21 register. */
24811 #define ALT_GIC_DIST_GICD_ICFGR21_RESET 0x55555555
24812 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR21 register from the beginning of the component. */
24813 #define ALT_GIC_DIST_GICD_ICFGR21_OFST 0xc54
24814 
24815 /*
24816  * Register : GICD_ICFGR22
24817  *
24818  * Interrupt Configuration Registers
24819  *
24820  * Register Layout
24821  *
24822  * Bits | Access | Reset | Description
24823  * :-------|:-------|:-----------|:------------
24824  * [31:0] | RW | 0x55555555 | Empty
24825  *
24826  */
24827 /*
24828  * Field : Empty - fld
24829  *
24830  * Placeholder
24831  *
24832  * Field Access Macros:
24833  *
24834  */
24835 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR22_FLD register field. */
24836 #define ALT_GIC_DIST_GICD_ICFGR22_FLD_LSB 0
24837 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR22_FLD register field. */
24838 #define ALT_GIC_DIST_GICD_ICFGR22_FLD_MSB 31
24839 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR22_FLD register field. */
24840 #define ALT_GIC_DIST_GICD_ICFGR22_FLD_WIDTH 32
24841 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR22_FLD register field value. */
24842 #define ALT_GIC_DIST_GICD_ICFGR22_FLD_SET_MSK 0xffffffff
24843 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR22_FLD register field value. */
24844 #define ALT_GIC_DIST_GICD_ICFGR22_FLD_CLR_MSK 0x00000000
24845 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR22_FLD register field. */
24846 #define ALT_GIC_DIST_GICD_ICFGR22_FLD_RESET 0x55555555
24847 /* Extracts the ALT_GIC_DIST_GICD_ICFGR22_FLD field value from a register. */
24848 #define ALT_GIC_DIST_GICD_ICFGR22_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24849 /* Produces a ALT_GIC_DIST_GICD_ICFGR22_FLD register field value suitable for setting the register. */
24850 #define ALT_GIC_DIST_GICD_ICFGR22_FLD_SET(value) (((value) << 0) & 0xffffffff)
24851 
24852 #ifndef __ASSEMBLY__
24853 /*
24854  * WARNING: The C register and register group struct declarations are provided for
24855  * convenience and illustrative purposes. They should, however, be used with
24856  * caution as the C language standard provides no guarantees about the alignment or
24857  * atomicity of device memory accesses. The recommended practice for coding device
24858  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
24859  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
24860  * alt_write_dword() functions for 64 bit registers.
24861  *
24862  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR22.
24863  */
24864 struct ALT_GIC_DIST_GICD_ICFGR22_s
24865 {
24866  volatile uint32_t fld : 32; /* Empty */
24867 };
24868 
24869 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR22. */
24870 typedef struct ALT_GIC_DIST_GICD_ICFGR22_s ALT_GIC_DIST_GICD_ICFGR22_t;
24871 #endif /* __ASSEMBLY__ */
24872 
24873 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR22 register. */
24874 #define ALT_GIC_DIST_GICD_ICFGR22_RESET 0x55555555
24875 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR22 register from the beginning of the component. */
24876 #define ALT_GIC_DIST_GICD_ICFGR22_OFST 0xc58
24877 
24878 /*
24879  * Register : GICD_ICFGR23
24880  *
24881  * Interrupt Configuration Registers
24882  *
24883  * Register Layout
24884  *
24885  * Bits | Access | Reset | Description
24886  * :-------|:-------|:-----------|:------------
24887  * [31:0] | RW | 0x55555555 | Empty
24888  *
24889  */
24890 /*
24891  * Field : Empty - fld
24892  *
24893  * Placeholder
24894  *
24895  * Field Access Macros:
24896  *
24897  */
24898 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR23_FLD register field. */
24899 #define ALT_GIC_DIST_GICD_ICFGR23_FLD_LSB 0
24900 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR23_FLD register field. */
24901 #define ALT_GIC_DIST_GICD_ICFGR23_FLD_MSB 31
24902 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR23_FLD register field. */
24903 #define ALT_GIC_DIST_GICD_ICFGR23_FLD_WIDTH 32
24904 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR23_FLD register field value. */
24905 #define ALT_GIC_DIST_GICD_ICFGR23_FLD_SET_MSK 0xffffffff
24906 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR23_FLD register field value. */
24907 #define ALT_GIC_DIST_GICD_ICFGR23_FLD_CLR_MSK 0x00000000
24908 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR23_FLD register field. */
24909 #define ALT_GIC_DIST_GICD_ICFGR23_FLD_RESET 0x55555555
24910 /* Extracts the ALT_GIC_DIST_GICD_ICFGR23_FLD field value from a register. */
24911 #define ALT_GIC_DIST_GICD_ICFGR23_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24912 /* Produces a ALT_GIC_DIST_GICD_ICFGR23_FLD register field value suitable for setting the register. */
24913 #define ALT_GIC_DIST_GICD_ICFGR23_FLD_SET(value) (((value) << 0) & 0xffffffff)
24914 
24915 #ifndef __ASSEMBLY__
24916 /*
24917  * WARNING: The C register and register group struct declarations are provided for
24918  * convenience and illustrative purposes. They should, however, be used with
24919  * caution as the C language standard provides no guarantees about the alignment or
24920  * atomicity of device memory accesses. The recommended practice for coding device
24921  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
24922  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
24923  * alt_write_dword() functions for 64 bit registers.
24924  *
24925  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR23.
24926  */
24927 struct ALT_GIC_DIST_GICD_ICFGR23_s
24928 {
24929  volatile uint32_t fld : 32; /* Empty */
24930 };
24931 
24932 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR23. */
24933 typedef struct ALT_GIC_DIST_GICD_ICFGR23_s ALT_GIC_DIST_GICD_ICFGR23_t;
24934 #endif /* __ASSEMBLY__ */
24935 
24936 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR23 register. */
24937 #define ALT_GIC_DIST_GICD_ICFGR23_RESET 0x55555555
24938 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR23 register from the beginning of the component. */
24939 #define ALT_GIC_DIST_GICD_ICFGR23_OFST 0xc5c
24940 
24941 /*
24942  * Register : GICD_ICFGR24
24943  *
24944  * Interrupt Configuration Registers
24945  *
24946  * Register Layout
24947  *
24948  * Bits | Access | Reset | Description
24949  * :-------|:-------|:-----------|:------------
24950  * [31:0] | RW | 0x55555555 | Empty
24951  *
24952  */
24953 /*
24954  * Field : Empty - fld
24955  *
24956  * Placeholder
24957  *
24958  * Field Access Macros:
24959  *
24960  */
24961 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR24_FLD register field. */
24962 #define ALT_GIC_DIST_GICD_ICFGR24_FLD_LSB 0
24963 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR24_FLD register field. */
24964 #define ALT_GIC_DIST_GICD_ICFGR24_FLD_MSB 31
24965 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR24_FLD register field. */
24966 #define ALT_GIC_DIST_GICD_ICFGR24_FLD_WIDTH 32
24967 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR24_FLD register field value. */
24968 #define ALT_GIC_DIST_GICD_ICFGR24_FLD_SET_MSK 0xffffffff
24969 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR24_FLD register field value. */
24970 #define ALT_GIC_DIST_GICD_ICFGR24_FLD_CLR_MSK 0x00000000
24971 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR24_FLD register field. */
24972 #define ALT_GIC_DIST_GICD_ICFGR24_FLD_RESET 0x55555555
24973 /* Extracts the ALT_GIC_DIST_GICD_ICFGR24_FLD field value from a register. */
24974 #define ALT_GIC_DIST_GICD_ICFGR24_FLD_GET(value) (((value) & 0xffffffff) >> 0)
24975 /* Produces a ALT_GIC_DIST_GICD_ICFGR24_FLD register field value suitable for setting the register. */
24976 #define ALT_GIC_DIST_GICD_ICFGR24_FLD_SET(value) (((value) << 0) & 0xffffffff)
24977 
24978 #ifndef __ASSEMBLY__
24979 /*
24980  * WARNING: The C register and register group struct declarations are provided for
24981  * convenience and illustrative purposes. They should, however, be used with
24982  * caution as the C language standard provides no guarantees about the alignment or
24983  * atomicity of device memory accesses. The recommended practice for coding device
24984  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
24985  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
24986  * alt_write_dword() functions for 64 bit registers.
24987  *
24988  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR24.
24989  */
24990 struct ALT_GIC_DIST_GICD_ICFGR24_s
24991 {
24992  volatile uint32_t fld : 32; /* Empty */
24993 };
24994 
24995 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR24. */
24996 typedef struct ALT_GIC_DIST_GICD_ICFGR24_s ALT_GIC_DIST_GICD_ICFGR24_t;
24997 #endif /* __ASSEMBLY__ */
24998 
24999 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR24 register. */
25000 #define ALT_GIC_DIST_GICD_ICFGR24_RESET 0x55555555
25001 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR24 register from the beginning of the component. */
25002 #define ALT_GIC_DIST_GICD_ICFGR24_OFST 0xc60
25003 
25004 /*
25005  * Register : GICD_ICFGR25
25006  *
25007  * Interrupt Configuration Registers
25008  *
25009  * Register Layout
25010  *
25011  * Bits | Access | Reset | Description
25012  * :-------|:-------|:-----------|:------------
25013  * [31:0] | RW | 0x55555555 | Empty
25014  *
25015  */
25016 /*
25017  * Field : Empty - fld
25018  *
25019  * Placeholder
25020  *
25021  * Field Access Macros:
25022  *
25023  */
25024 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR25_FLD register field. */
25025 #define ALT_GIC_DIST_GICD_ICFGR25_FLD_LSB 0
25026 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR25_FLD register field. */
25027 #define ALT_GIC_DIST_GICD_ICFGR25_FLD_MSB 31
25028 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR25_FLD register field. */
25029 #define ALT_GIC_DIST_GICD_ICFGR25_FLD_WIDTH 32
25030 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR25_FLD register field value. */
25031 #define ALT_GIC_DIST_GICD_ICFGR25_FLD_SET_MSK 0xffffffff
25032 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR25_FLD register field value. */
25033 #define ALT_GIC_DIST_GICD_ICFGR25_FLD_CLR_MSK 0x00000000
25034 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR25_FLD register field. */
25035 #define ALT_GIC_DIST_GICD_ICFGR25_FLD_RESET 0x55555555
25036 /* Extracts the ALT_GIC_DIST_GICD_ICFGR25_FLD field value from a register. */
25037 #define ALT_GIC_DIST_GICD_ICFGR25_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25038 /* Produces a ALT_GIC_DIST_GICD_ICFGR25_FLD register field value suitable for setting the register. */
25039 #define ALT_GIC_DIST_GICD_ICFGR25_FLD_SET(value) (((value) << 0) & 0xffffffff)
25040 
25041 #ifndef __ASSEMBLY__
25042 /*
25043  * WARNING: The C register and register group struct declarations are provided for
25044  * convenience and illustrative purposes. They should, however, be used with
25045  * caution as the C language standard provides no guarantees about the alignment or
25046  * atomicity of device memory accesses. The recommended practice for coding device
25047  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25048  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25049  * alt_write_dword() functions for 64 bit registers.
25050  *
25051  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR25.
25052  */
25053 struct ALT_GIC_DIST_GICD_ICFGR25_s
25054 {
25055  volatile uint32_t fld : 32; /* Empty */
25056 };
25057 
25058 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR25. */
25059 typedef struct ALT_GIC_DIST_GICD_ICFGR25_s ALT_GIC_DIST_GICD_ICFGR25_t;
25060 #endif /* __ASSEMBLY__ */
25061 
25062 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR25 register. */
25063 #define ALT_GIC_DIST_GICD_ICFGR25_RESET 0x55555555
25064 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR25 register from the beginning of the component. */
25065 #define ALT_GIC_DIST_GICD_ICFGR25_OFST 0xc64
25066 
25067 /*
25068  * Register : GICD_ICFGR26
25069  *
25070  * Interrupt Configuration Registers
25071  *
25072  * Register Layout
25073  *
25074  * Bits | Access | Reset | Description
25075  * :-------|:-------|:-----------|:------------
25076  * [31:0] | RW | 0x55555555 | Empty
25077  *
25078  */
25079 /*
25080  * Field : Empty - fld
25081  *
25082  * Placeholder
25083  *
25084  * Field Access Macros:
25085  *
25086  */
25087 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR26_FLD register field. */
25088 #define ALT_GIC_DIST_GICD_ICFGR26_FLD_LSB 0
25089 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR26_FLD register field. */
25090 #define ALT_GIC_DIST_GICD_ICFGR26_FLD_MSB 31
25091 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR26_FLD register field. */
25092 #define ALT_GIC_DIST_GICD_ICFGR26_FLD_WIDTH 32
25093 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR26_FLD register field value. */
25094 #define ALT_GIC_DIST_GICD_ICFGR26_FLD_SET_MSK 0xffffffff
25095 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR26_FLD register field value. */
25096 #define ALT_GIC_DIST_GICD_ICFGR26_FLD_CLR_MSK 0x00000000
25097 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR26_FLD register field. */
25098 #define ALT_GIC_DIST_GICD_ICFGR26_FLD_RESET 0x55555555
25099 /* Extracts the ALT_GIC_DIST_GICD_ICFGR26_FLD field value from a register. */
25100 #define ALT_GIC_DIST_GICD_ICFGR26_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25101 /* Produces a ALT_GIC_DIST_GICD_ICFGR26_FLD register field value suitable for setting the register. */
25102 #define ALT_GIC_DIST_GICD_ICFGR26_FLD_SET(value) (((value) << 0) & 0xffffffff)
25103 
25104 #ifndef __ASSEMBLY__
25105 /*
25106  * WARNING: The C register and register group struct declarations are provided for
25107  * convenience and illustrative purposes. They should, however, be used with
25108  * caution as the C language standard provides no guarantees about the alignment or
25109  * atomicity of device memory accesses. The recommended practice for coding device
25110  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25111  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25112  * alt_write_dword() functions for 64 bit registers.
25113  *
25114  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR26.
25115  */
25116 struct ALT_GIC_DIST_GICD_ICFGR26_s
25117 {
25118  volatile uint32_t fld : 32; /* Empty */
25119 };
25120 
25121 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR26. */
25122 typedef struct ALT_GIC_DIST_GICD_ICFGR26_s ALT_GIC_DIST_GICD_ICFGR26_t;
25123 #endif /* __ASSEMBLY__ */
25124 
25125 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR26 register. */
25126 #define ALT_GIC_DIST_GICD_ICFGR26_RESET 0x55555555
25127 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR26 register from the beginning of the component. */
25128 #define ALT_GIC_DIST_GICD_ICFGR26_OFST 0xc68
25129 
25130 /*
25131  * Register : GICD_ICFGR27
25132  *
25133  * Interrupt Configuration Registers
25134  *
25135  * Register Layout
25136  *
25137  * Bits | Access | Reset | Description
25138  * :-------|:-------|:-----------|:------------
25139  * [31:0] | RW | 0x55555555 | Empty
25140  *
25141  */
25142 /*
25143  * Field : Empty - fld
25144  *
25145  * Placeholder
25146  *
25147  * Field Access Macros:
25148  *
25149  */
25150 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR27_FLD register field. */
25151 #define ALT_GIC_DIST_GICD_ICFGR27_FLD_LSB 0
25152 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR27_FLD register field. */
25153 #define ALT_GIC_DIST_GICD_ICFGR27_FLD_MSB 31
25154 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR27_FLD register field. */
25155 #define ALT_GIC_DIST_GICD_ICFGR27_FLD_WIDTH 32
25156 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR27_FLD register field value. */
25157 #define ALT_GIC_DIST_GICD_ICFGR27_FLD_SET_MSK 0xffffffff
25158 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR27_FLD register field value. */
25159 #define ALT_GIC_DIST_GICD_ICFGR27_FLD_CLR_MSK 0x00000000
25160 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR27_FLD register field. */
25161 #define ALT_GIC_DIST_GICD_ICFGR27_FLD_RESET 0x55555555
25162 /* Extracts the ALT_GIC_DIST_GICD_ICFGR27_FLD field value from a register. */
25163 #define ALT_GIC_DIST_GICD_ICFGR27_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25164 /* Produces a ALT_GIC_DIST_GICD_ICFGR27_FLD register field value suitable for setting the register. */
25165 #define ALT_GIC_DIST_GICD_ICFGR27_FLD_SET(value) (((value) << 0) & 0xffffffff)
25166 
25167 #ifndef __ASSEMBLY__
25168 /*
25169  * WARNING: The C register and register group struct declarations are provided for
25170  * convenience and illustrative purposes. They should, however, be used with
25171  * caution as the C language standard provides no guarantees about the alignment or
25172  * atomicity of device memory accesses. The recommended practice for coding device
25173  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25174  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25175  * alt_write_dword() functions for 64 bit registers.
25176  *
25177  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR27.
25178  */
25179 struct ALT_GIC_DIST_GICD_ICFGR27_s
25180 {
25181  volatile uint32_t fld : 32; /* Empty */
25182 };
25183 
25184 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR27. */
25185 typedef struct ALT_GIC_DIST_GICD_ICFGR27_s ALT_GIC_DIST_GICD_ICFGR27_t;
25186 #endif /* __ASSEMBLY__ */
25187 
25188 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR27 register. */
25189 #define ALT_GIC_DIST_GICD_ICFGR27_RESET 0x55555555
25190 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR27 register from the beginning of the component. */
25191 #define ALT_GIC_DIST_GICD_ICFGR27_OFST 0xc6c
25192 
25193 /*
25194  * Register : GICD_ICFGR28
25195  *
25196  * Interrupt Configuration Registers
25197  *
25198  * Register Layout
25199  *
25200  * Bits | Access | Reset | Description
25201  * :-------|:-------|:-----------|:------------
25202  * [31:0] | RW | 0x55555555 | Empty
25203  *
25204  */
25205 /*
25206  * Field : Empty - fld
25207  *
25208  * Placeholder
25209  *
25210  * Field Access Macros:
25211  *
25212  */
25213 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR28_FLD register field. */
25214 #define ALT_GIC_DIST_GICD_ICFGR28_FLD_LSB 0
25215 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR28_FLD register field. */
25216 #define ALT_GIC_DIST_GICD_ICFGR28_FLD_MSB 31
25217 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR28_FLD register field. */
25218 #define ALT_GIC_DIST_GICD_ICFGR28_FLD_WIDTH 32
25219 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR28_FLD register field value. */
25220 #define ALT_GIC_DIST_GICD_ICFGR28_FLD_SET_MSK 0xffffffff
25221 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR28_FLD register field value. */
25222 #define ALT_GIC_DIST_GICD_ICFGR28_FLD_CLR_MSK 0x00000000
25223 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR28_FLD register field. */
25224 #define ALT_GIC_DIST_GICD_ICFGR28_FLD_RESET 0x55555555
25225 /* Extracts the ALT_GIC_DIST_GICD_ICFGR28_FLD field value from a register. */
25226 #define ALT_GIC_DIST_GICD_ICFGR28_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25227 /* Produces a ALT_GIC_DIST_GICD_ICFGR28_FLD register field value suitable for setting the register. */
25228 #define ALT_GIC_DIST_GICD_ICFGR28_FLD_SET(value) (((value) << 0) & 0xffffffff)
25229 
25230 #ifndef __ASSEMBLY__
25231 /*
25232  * WARNING: The C register and register group struct declarations are provided for
25233  * convenience and illustrative purposes. They should, however, be used with
25234  * caution as the C language standard provides no guarantees about the alignment or
25235  * atomicity of device memory accesses. The recommended practice for coding device
25236  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25237  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25238  * alt_write_dword() functions for 64 bit registers.
25239  *
25240  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR28.
25241  */
25242 struct ALT_GIC_DIST_GICD_ICFGR28_s
25243 {
25244  volatile uint32_t fld : 32; /* Empty */
25245 };
25246 
25247 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR28. */
25248 typedef struct ALT_GIC_DIST_GICD_ICFGR28_s ALT_GIC_DIST_GICD_ICFGR28_t;
25249 #endif /* __ASSEMBLY__ */
25250 
25251 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR28 register. */
25252 #define ALT_GIC_DIST_GICD_ICFGR28_RESET 0x55555555
25253 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR28 register from the beginning of the component. */
25254 #define ALT_GIC_DIST_GICD_ICFGR28_OFST 0xc70
25255 
25256 /*
25257  * Register : GICD_ICFGR29
25258  *
25259  * Interrupt Configuration Registers
25260  *
25261  * Register Layout
25262  *
25263  * Bits | Access | Reset | Description
25264  * :-------|:-------|:-----------|:------------
25265  * [31:0] | RW | 0x55555555 | Empty
25266  *
25267  */
25268 /*
25269  * Field : Empty - fld
25270  *
25271  * Placeholder
25272  *
25273  * Field Access Macros:
25274  *
25275  */
25276 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR29_FLD register field. */
25277 #define ALT_GIC_DIST_GICD_ICFGR29_FLD_LSB 0
25278 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR29_FLD register field. */
25279 #define ALT_GIC_DIST_GICD_ICFGR29_FLD_MSB 31
25280 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR29_FLD register field. */
25281 #define ALT_GIC_DIST_GICD_ICFGR29_FLD_WIDTH 32
25282 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR29_FLD register field value. */
25283 #define ALT_GIC_DIST_GICD_ICFGR29_FLD_SET_MSK 0xffffffff
25284 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR29_FLD register field value. */
25285 #define ALT_GIC_DIST_GICD_ICFGR29_FLD_CLR_MSK 0x00000000
25286 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR29_FLD register field. */
25287 #define ALT_GIC_DIST_GICD_ICFGR29_FLD_RESET 0x55555555
25288 /* Extracts the ALT_GIC_DIST_GICD_ICFGR29_FLD field value from a register. */
25289 #define ALT_GIC_DIST_GICD_ICFGR29_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25290 /* Produces a ALT_GIC_DIST_GICD_ICFGR29_FLD register field value suitable for setting the register. */
25291 #define ALT_GIC_DIST_GICD_ICFGR29_FLD_SET(value) (((value) << 0) & 0xffffffff)
25292 
25293 #ifndef __ASSEMBLY__
25294 /*
25295  * WARNING: The C register and register group struct declarations are provided for
25296  * convenience and illustrative purposes. They should, however, be used with
25297  * caution as the C language standard provides no guarantees about the alignment or
25298  * atomicity of device memory accesses. The recommended practice for coding device
25299  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25300  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25301  * alt_write_dword() functions for 64 bit registers.
25302  *
25303  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR29.
25304  */
25305 struct ALT_GIC_DIST_GICD_ICFGR29_s
25306 {
25307  volatile uint32_t fld : 32; /* Empty */
25308 };
25309 
25310 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR29. */
25311 typedef struct ALT_GIC_DIST_GICD_ICFGR29_s ALT_GIC_DIST_GICD_ICFGR29_t;
25312 #endif /* __ASSEMBLY__ */
25313 
25314 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR29 register. */
25315 #define ALT_GIC_DIST_GICD_ICFGR29_RESET 0x55555555
25316 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR29 register from the beginning of the component. */
25317 #define ALT_GIC_DIST_GICD_ICFGR29_OFST 0xc74
25318 
25319 /*
25320  * Register : GICD_ICFGR30
25321  *
25322  * Interrupt Configuration Registers
25323  *
25324  * Register Layout
25325  *
25326  * Bits | Access | Reset | Description
25327  * :-------|:-------|:-----------|:------------
25328  * [31:0] | RW | 0x55555555 | Empty
25329  *
25330  */
25331 /*
25332  * Field : Empty - fld
25333  *
25334  * Placeholder
25335  *
25336  * Field Access Macros:
25337  *
25338  */
25339 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR30_FLD register field. */
25340 #define ALT_GIC_DIST_GICD_ICFGR30_FLD_LSB 0
25341 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR30_FLD register field. */
25342 #define ALT_GIC_DIST_GICD_ICFGR30_FLD_MSB 31
25343 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR30_FLD register field. */
25344 #define ALT_GIC_DIST_GICD_ICFGR30_FLD_WIDTH 32
25345 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR30_FLD register field value. */
25346 #define ALT_GIC_DIST_GICD_ICFGR30_FLD_SET_MSK 0xffffffff
25347 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR30_FLD register field value. */
25348 #define ALT_GIC_DIST_GICD_ICFGR30_FLD_CLR_MSK 0x00000000
25349 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR30_FLD register field. */
25350 #define ALT_GIC_DIST_GICD_ICFGR30_FLD_RESET 0x55555555
25351 /* Extracts the ALT_GIC_DIST_GICD_ICFGR30_FLD field value from a register. */
25352 #define ALT_GIC_DIST_GICD_ICFGR30_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25353 /* Produces a ALT_GIC_DIST_GICD_ICFGR30_FLD register field value suitable for setting the register. */
25354 #define ALT_GIC_DIST_GICD_ICFGR30_FLD_SET(value) (((value) << 0) & 0xffffffff)
25355 
25356 #ifndef __ASSEMBLY__
25357 /*
25358  * WARNING: The C register and register group struct declarations are provided for
25359  * convenience and illustrative purposes. They should, however, be used with
25360  * caution as the C language standard provides no guarantees about the alignment or
25361  * atomicity of device memory accesses. The recommended practice for coding device
25362  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25363  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25364  * alt_write_dword() functions for 64 bit registers.
25365  *
25366  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR30.
25367  */
25368 struct ALT_GIC_DIST_GICD_ICFGR30_s
25369 {
25370  volatile uint32_t fld : 32; /* Empty */
25371 };
25372 
25373 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR30. */
25374 typedef struct ALT_GIC_DIST_GICD_ICFGR30_s ALT_GIC_DIST_GICD_ICFGR30_t;
25375 #endif /* __ASSEMBLY__ */
25376 
25377 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR30 register. */
25378 #define ALT_GIC_DIST_GICD_ICFGR30_RESET 0x55555555
25379 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR30 register from the beginning of the component. */
25380 #define ALT_GIC_DIST_GICD_ICFGR30_OFST 0xc78
25381 
25382 /*
25383  * Register : GICD_ICFGR31
25384  *
25385  * Interrupt Configuration Registers
25386  *
25387  * Register Layout
25388  *
25389  * Bits | Access | Reset | Description
25390  * :-------|:-------|:-----------|:------------
25391  * [31:0] | RW | 0x55555555 | Empty
25392  *
25393  */
25394 /*
25395  * Field : Empty - fld
25396  *
25397  * Placeholder
25398  *
25399  * Field Access Macros:
25400  *
25401  */
25402 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_ICFGR31_FLD register field. */
25403 #define ALT_GIC_DIST_GICD_ICFGR31_FLD_LSB 0
25404 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_ICFGR31_FLD register field. */
25405 #define ALT_GIC_DIST_GICD_ICFGR31_FLD_MSB 31
25406 /* The width in bits of the ALT_GIC_DIST_GICD_ICFGR31_FLD register field. */
25407 #define ALT_GIC_DIST_GICD_ICFGR31_FLD_WIDTH 32
25408 /* The mask used to set the ALT_GIC_DIST_GICD_ICFGR31_FLD register field value. */
25409 #define ALT_GIC_DIST_GICD_ICFGR31_FLD_SET_MSK 0xffffffff
25410 /* The mask used to clear the ALT_GIC_DIST_GICD_ICFGR31_FLD register field value. */
25411 #define ALT_GIC_DIST_GICD_ICFGR31_FLD_CLR_MSK 0x00000000
25412 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR31_FLD register field. */
25413 #define ALT_GIC_DIST_GICD_ICFGR31_FLD_RESET 0x55555555
25414 /* Extracts the ALT_GIC_DIST_GICD_ICFGR31_FLD field value from a register. */
25415 #define ALT_GIC_DIST_GICD_ICFGR31_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25416 /* Produces a ALT_GIC_DIST_GICD_ICFGR31_FLD register field value suitable for setting the register. */
25417 #define ALT_GIC_DIST_GICD_ICFGR31_FLD_SET(value) (((value) << 0) & 0xffffffff)
25418 
25419 #ifndef __ASSEMBLY__
25420 /*
25421  * WARNING: The C register and register group struct declarations are provided for
25422  * convenience and illustrative purposes. They should, however, be used with
25423  * caution as the C language standard provides no guarantees about the alignment or
25424  * atomicity of device memory accesses. The recommended practice for coding device
25425  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25426  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25427  * alt_write_dword() functions for 64 bit registers.
25428  *
25429  * The struct declaration for register ALT_GIC_DIST_GICD_ICFGR31.
25430  */
25431 struct ALT_GIC_DIST_GICD_ICFGR31_s
25432 {
25433  volatile uint32_t fld : 32; /* Empty */
25434 };
25435 
25436 /* The typedef declaration for register ALT_GIC_DIST_GICD_ICFGR31. */
25437 typedef struct ALT_GIC_DIST_GICD_ICFGR31_s ALT_GIC_DIST_GICD_ICFGR31_t;
25438 #endif /* __ASSEMBLY__ */
25439 
25440 /* The reset value of the ALT_GIC_DIST_GICD_ICFGR31 register. */
25441 #define ALT_GIC_DIST_GICD_ICFGR31_RESET 0x55555555
25442 /* The byte offset of the ALT_GIC_DIST_GICD_ICFGR31 register from the beginning of the component. */
25443 #define ALT_GIC_DIST_GICD_ICFGR31_OFST 0xc7c
25444 
25445 /*
25446  * Register : GICD_PPISR
25447  *
25448  * Private Peripheral Interrupt Status Register
25449  *
25450  * Register Layout
25451  *
25452  * Bits | Access | Reset | Description
25453  * :-------|:-------|:------|:------------
25454  * [31:0] | RW | 0x0 | Empty
25455  *
25456  */
25457 /*
25458  * Field : Empty - fld
25459  *
25460  * Placeholder
25461  *
25462  * Field Access Macros:
25463  *
25464  */
25465 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_PPISR_FLD register field. */
25466 #define ALT_GIC_DIST_GICD_PPISR_FLD_LSB 0
25467 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_PPISR_FLD register field. */
25468 #define ALT_GIC_DIST_GICD_PPISR_FLD_MSB 31
25469 /* The width in bits of the ALT_GIC_DIST_GICD_PPISR_FLD register field. */
25470 #define ALT_GIC_DIST_GICD_PPISR_FLD_WIDTH 32
25471 /* The mask used to set the ALT_GIC_DIST_GICD_PPISR_FLD register field value. */
25472 #define ALT_GIC_DIST_GICD_PPISR_FLD_SET_MSK 0xffffffff
25473 /* The mask used to clear the ALT_GIC_DIST_GICD_PPISR_FLD register field value. */
25474 #define ALT_GIC_DIST_GICD_PPISR_FLD_CLR_MSK 0x00000000
25475 /* The reset value of the ALT_GIC_DIST_GICD_PPISR_FLD register field. */
25476 #define ALT_GIC_DIST_GICD_PPISR_FLD_RESET 0x0
25477 /* Extracts the ALT_GIC_DIST_GICD_PPISR_FLD field value from a register. */
25478 #define ALT_GIC_DIST_GICD_PPISR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25479 /* Produces a ALT_GIC_DIST_GICD_PPISR_FLD register field value suitable for setting the register. */
25480 #define ALT_GIC_DIST_GICD_PPISR_FLD_SET(value) (((value) << 0) & 0xffffffff)
25481 
25482 #ifndef __ASSEMBLY__
25483 /*
25484  * WARNING: The C register and register group struct declarations are provided for
25485  * convenience and illustrative purposes. They should, however, be used with
25486  * caution as the C language standard provides no guarantees about the alignment or
25487  * atomicity of device memory accesses. The recommended practice for coding device
25488  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25489  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25490  * alt_write_dword() functions for 64 bit registers.
25491  *
25492  * The struct declaration for register ALT_GIC_DIST_GICD_PPISR.
25493  */
25494 struct ALT_GIC_DIST_GICD_PPISR_s
25495 {
25496  volatile uint32_t fld : 32; /* Empty */
25497 };
25498 
25499 /* The typedef declaration for register ALT_GIC_DIST_GICD_PPISR. */
25500 typedef struct ALT_GIC_DIST_GICD_PPISR_s ALT_GIC_DIST_GICD_PPISR_t;
25501 #endif /* __ASSEMBLY__ */
25502 
25503 /* The reset value of the ALT_GIC_DIST_GICD_PPISR register. */
25504 #define ALT_GIC_DIST_GICD_PPISR_RESET 0x00000000
25505 /* The byte offset of the ALT_GIC_DIST_GICD_PPISR register from the beginning of the component. */
25506 #define ALT_GIC_DIST_GICD_PPISR_OFST 0xd00
25507 
25508 /*
25509  * Register : GICD_SPISR0
25510  *
25511  * Shared Peripheral Interrupt Status Registers
25512  *
25513  * Register Layout
25514  *
25515  * Bits | Access | Reset | Description
25516  * :-------|:-------|:------|:------------
25517  * [31:0] | RW | 0x0 | Empty
25518  *
25519  */
25520 /*
25521  * Field : Empty - fld
25522  *
25523  * Placeholder
25524  *
25525  * Field Access Macros:
25526  *
25527  */
25528 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_SPISR0_FLD register field. */
25529 #define ALT_GIC_DIST_GICD_SPISR0_FLD_LSB 0
25530 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_SPISR0_FLD register field. */
25531 #define ALT_GIC_DIST_GICD_SPISR0_FLD_MSB 31
25532 /* The width in bits of the ALT_GIC_DIST_GICD_SPISR0_FLD register field. */
25533 #define ALT_GIC_DIST_GICD_SPISR0_FLD_WIDTH 32
25534 /* The mask used to set the ALT_GIC_DIST_GICD_SPISR0_FLD register field value. */
25535 #define ALT_GIC_DIST_GICD_SPISR0_FLD_SET_MSK 0xffffffff
25536 /* The mask used to clear the ALT_GIC_DIST_GICD_SPISR0_FLD register field value. */
25537 #define ALT_GIC_DIST_GICD_SPISR0_FLD_CLR_MSK 0x00000000
25538 /* The reset value of the ALT_GIC_DIST_GICD_SPISR0_FLD register field. */
25539 #define ALT_GIC_DIST_GICD_SPISR0_FLD_RESET 0x0
25540 /* Extracts the ALT_GIC_DIST_GICD_SPISR0_FLD field value from a register. */
25541 #define ALT_GIC_DIST_GICD_SPISR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25542 /* Produces a ALT_GIC_DIST_GICD_SPISR0_FLD register field value suitable for setting the register. */
25543 #define ALT_GIC_DIST_GICD_SPISR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
25544 
25545 #ifndef __ASSEMBLY__
25546 /*
25547  * WARNING: The C register and register group struct declarations are provided for
25548  * convenience and illustrative purposes. They should, however, be used with
25549  * caution as the C language standard provides no guarantees about the alignment or
25550  * atomicity of device memory accesses. The recommended practice for coding device
25551  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25552  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25553  * alt_write_dword() functions for 64 bit registers.
25554  *
25555  * The struct declaration for register ALT_GIC_DIST_GICD_SPISR0.
25556  */
25557 struct ALT_GIC_DIST_GICD_SPISR0_s
25558 {
25559  volatile uint32_t fld : 32; /* Empty */
25560 };
25561 
25562 /* The typedef declaration for register ALT_GIC_DIST_GICD_SPISR0. */
25563 typedef struct ALT_GIC_DIST_GICD_SPISR0_s ALT_GIC_DIST_GICD_SPISR0_t;
25564 #endif /* __ASSEMBLY__ */
25565 
25566 /* The reset value of the ALT_GIC_DIST_GICD_SPISR0 register. */
25567 #define ALT_GIC_DIST_GICD_SPISR0_RESET 0x00000000
25568 /* The byte offset of the ALT_GIC_DIST_GICD_SPISR0 register from the beginning of the component. */
25569 #define ALT_GIC_DIST_GICD_SPISR0_OFST 0xd04
25570 
25571 /*
25572  * Register : GICD_SPISR1
25573  *
25574  * Shared Peripheral Interrupt Status Registers
25575  *
25576  * Register Layout
25577  *
25578  * Bits | Access | Reset | Description
25579  * :-------|:-------|:------|:------------
25580  * [31:0] | RW | 0x0 | Empty
25581  *
25582  */
25583 /*
25584  * Field : Empty - fld
25585  *
25586  * Placeholder
25587  *
25588  * Field Access Macros:
25589  *
25590  */
25591 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_SPISR1_FLD register field. */
25592 #define ALT_GIC_DIST_GICD_SPISR1_FLD_LSB 0
25593 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_SPISR1_FLD register field. */
25594 #define ALT_GIC_DIST_GICD_SPISR1_FLD_MSB 31
25595 /* The width in bits of the ALT_GIC_DIST_GICD_SPISR1_FLD register field. */
25596 #define ALT_GIC_DIST_GICD_SPISR1_FLD_WIDTH 32
25597 /* The mask used to set the ALT_GIC_DIST_GICD_SPISR1_FLD register field value. */
25598 #define ALT_GIC_DIST_GICD_SPISR1_FLD_SET_MSK 0xffffffff
25599 /* The mask used to clear the ALT_GIC_DIST_GICD_SPISR1_FLD register field value. */
25600 #define ALT_GIC_DIST_GICD_SPISR1_FLD_CLR_MSK 0x00000000
25601 /* The reset value of the ALT_GIC_DIST_GICD_SPISR1_FLD register field. */
25602 #define ALT_GIC_DIST_GICD_SPISR1_FLD_RESET 0x0
25603 /* Extracts the ALT_GIC_DIST_GICD_SPISR1_FLD field value from a register. */
25604 #define ALT_GIC_DIST_GICD_SPISR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25605 /* Produces a ALT_GIC_DIST_GICD_SPISR1_FLD register field value suitable for setting the register. */
25606 #define ALT_GIC_DIST_GICD_SPISR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
25607 
25608 #ifndef __ASSEMBLY__
25609 /*
25610  * WARNING: The C register and register group struct declarations are provided for
25611  * convenience and illustrative purposes. They should, however, be used with
25612  * caution as the C language standard provides no guarantees about the alignment or
25613  * atomicity of device memory accesses. The recommended practice for coding device
25614  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25615  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25616  * alt_write_dword() functions for 64 bit registers.
25617  *
25618  * The struct declaration for register ALT_GIC_DIST_GICD_SPISR1.
25619  */
25620 struct ALT_GIC_DIST_GICD_SPISR1_s
25621 {
25622  volatile uint32_t fld : 32; /* Empty */
25623 };
25624 
25625 /* The typedef declaration for register ALT_GIC_DIST_GICD_SPISR1. */
25626 typedef struct ALT_GIC_DIST_GICD_SPISR1_s ALT_GIC_DIST_GICD_SPISR1_t;
25627 #endif /* __ASSEMBLY__ */
25628 
25629 /* The reset value of the ALT_GIC_DIST_GICD_SPISR1 register. */
25630 #define ALT_GIC_DIST_GICD_SPISR1_RESET 0x00000000
25631 /* The byte offset of the ALT_GIC_DIST_GICD_SPISR1 register from the beginning of the component. */
25632 #define ALT_GIC_DIST_GICD_SPISR1_OFST 0xd08
25633 
25634 /*
25635  * Register : GICD_SPISR2
25636  *
25637  * Shared Peripheral Interrupt Status Registers
25638  *
25639  * Register Layout
25640  *
25641  * Bits | Access | Reset | Description
25642  * :-------|:-------|:------|:------------
25643  * [31:0] | RW | 0x0 | Empty
25644  *
25645  */
25646 /*
25647  * Field : Empty - fld
25648  *
25649  * Placeholder
25650  *
25651  * Field Access Macros:
25652  *
25653  */
25654 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_SPISR2_FLD register field. */
25655 #define ALT_GIC_DIST_GICD_SPISR2_FLD_LSB 0
25656 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_SPISR2_FLD register field. */
25657 #define ALT_GIC_DIST_GICD_SPISR2_FLD_MSB 31
25658 /* The width in bits of the ALT_GIC_DIST_GICD_SPISR2_FLD register field. */
25659 #define ALT_GIC_DIST_GICD_SPISR2_FLD_WIDTH 32
25660 /* The mask used to set the ALT_GIC_DIST_GICD_SPISR2_FLD register field value. */
25661 #define ALT_GIC_DIST_GICD_SPISR2_FLD_SET_MSK 0xffffffff
25662 /* The mask used to clear the ALT_GIC_DIST_GICD_SPISR2_FLD register field value. */
25663 #define ALT_GIC_DIST_GICD_SPISR2_FLD_CLR_MSK 0x00000000
25664 /* The reset value of the ALT_GIC_DIST_GICD_SPISR2_FLD register field. */
25665 #define ALT_GIC_DIST_GICD_SPISR2_FLD_RESET 0x0
25666 /* Extracts the ALT_GIC_DIST_GICD_SPISR2_FLD field value from a register. */
25667 #define ALT_GIC_DIST_GICD_SPISR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25668 /* Produces a ALT_GIC_DIST_GICD_SPISR2_FLD register field value suitable for setting the register. */
25669 #define ALT_GIC_DIST_GICD_SPISR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
25670 
25671 #ifndef __ASSEMBLY__
25672 /*
25673  * WARNING: The C register and register group struct declarations are provided for
25674  * convenience and illustrative purposes. They should, however, be used with
25675  * caution as the C language standard provides no guarantees about the alignment or
25676  * atomicity of device memory accesses. The recommended practice for coding device
25677  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25678  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25679  * alt_write_dword() functions for 64 bit registers.
25680  *
25681  * The struct declaration for register ALT_GIC_DIST_GICD_SPISR2.
25682  */
25683 struct ALT_GIC_DIST_GICD_SPISR2_s
25684 {
25685  volatile uint32_t fld : 32; /* Empty */
25686 };
25687 
25688 /* The typedef declaration for register ALT_GIC_DIST_GICD_SPISR2. */
25689 typedef struct ALT_GIC_DIST_GICD_SPISR2_s ALT_GIC_DIST_GICD_SPISR2_t;
25690 #endif /* __ASSEMBLY__ */
25691 
25692 /* The reset value of the ALT_GIC_DIST_GICD_SPISR2 register. */
25693 #define ALT_GIC_DIST_GICD_SPISR2_RESET 0x00000000
25694 /* The byte offset of the ALT_GIC_DIST_GICD_SPISR2 register from the beginning of the component. */
25695 #define ALT_GIC_DIST_GICD_SPISR2_OFST 0xd0c
25696 
25697 /*
25698  * Register : GICD_SPISR3
25699  *
25700  * Shared Peripheral Interrupt Status Registers
25701  *
25702  * Register Layout
25703  *
25704  * Bits | Access | Reset | Description
25705  * :-------|:-------|:------|:------------
25706  * [31:0] | RW | 0x0 | Empty
25707  *
25708  */
25709 /*
25710  * Field : Empty - fld
25711  *
25712  * Placeholder
25713  *
25714  * Field Access Macros:
25715  *
25716  */
25717 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_SPISR3_FLD register field. */
25718 #define ALT_GIC_DIST_GICD_SPISR3_FLD_LSB 0
25719 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_SPISR3_FLD register field. */
25720 #define ALT_GIC_DIST_GICD_SPISR3_FLD_MSB 31
25721 /* The width in bits of the ALT_GIC_DIST_GICD_SPISR3_FLD register field. */
25722 #define ALT_GIC_DIST_GICD_SPISR3_FLD_WIDTH 32
25723 /* The mask used to set the ALT_GIC_DIST_GICD_SPISR3_FLD register field value. */
25724 #define ALT_GIC_DIST_GICD_SPISR3_FLD_SET_MSK 0xffffffff
25725 /* The mask used to clear the ALT_GIC_DIST_GICD_SPISR3_FLD register field value. */
25726 #define ALT_GIC_DIST_GICD_SPISR3_FLD_CLR_MSK 0x00000000
25727 /* The reset value of the ALT_GIC_DIST_GICD_SPISR3_FLD register field. */
25728 #define ALT_GIC_DIST_GICD_SPISR3_FLD_RESET 0x0
25729 /* Extracts the ALT_GIC_DIST_GICD_SPISR3_FLD field value from a register. */
25730 #define ALT_GIC_DIST_GICD_SPISR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25731 /* Produces a ALT_GIC_DIST_GICD_SPISR3_FLD register field value suitable for setting the register. */
25732 #define ALT_GIC_DIST_GICD_SPISR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
25733 
25734 #ifndef __ASSEMBLY__
25735 /*
25736  * WARNING: The C register and register group struct declarations are provided for
25737  * convenience and illustrative purposes. They should, however, be used with
25738  * caution as the C language standard provides no guarantees about the alignment or
25739  * atomicity of device memory accesses. The recommended practice for coding device
25740  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25741  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25742  * alt_write_dword() functions for 64 bit registers.
25743  *
25744  * The struct declaration for register ALT_GIC_DIST_GICD_SPISR3.
25745  */
25746 struct ALT_GIC_DIST_GICD_SPISR3_s
25747 {
25748  volatile uint32_t fld : 32; /* Empty */
25749 };
25750 
25751 /* The typedef declaration for register ALT_GIC_DIST_GICD_SPISR3. */
25752 typedef struct ALT_GIC_DIST_GICD_SPISR3_s ALT_GIC_DIST_GICD_SPISR3_t;
25753 #endif /* __ASSEMBLY__ */
25754 
25755 /* The reset value of the ALT_GIC_DIST_GICD_SPISR3 register. */
25756 #define ALT_GIC_DIST_GICD_SPISR3_RESET 0x00000000
25757 /* The byte offset of the ALT_GIC_DIST_GICD_SPISR3 register from the beginning of the component. */
25758 #define ALT_GIC_DIST_GICD_SPISR3_OFST 0xd10
25759 
25760 /*
25761  * Register : GICD_SPISR4
25762  *
25763  * Shared Peripheral Interrupt Status Registers
25764  *
25765  * Register Layout
25766  *
25767  * Bits | Access | Reset | Description
25768  * :-------|:-------|:------|:------------
25769  * [31:0] | RW | 0x0 | Empty
25770  *
25771  */
25772 /*
25773  * Field : Empty - fld
25774  *
25775  * Placeholder
25776  *
25777  * Field Access Macros:
25778  *
25779  */
25780 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_SPISR4_FLD register field. */
25781 #define ALT_GIC_DIST_GICD_SPISR4_FLD_LSB 0
25782 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_SPISR4_FLD register field. */
25783 #define ALT_GIC_DIST_GICD_SPISR4_FLD_MSB 31
25784 /* The width in bits of the ALT_GIC_DIST_GICD_SPISR4_FLD register field. */
25785 #define ALT_GIC_DIST_GICD_SPISR4_FLD_WIDTH 32
25786 /* The mask used to set the ALT_GIC_DIST_GICD_SPISR4_FLD register field value. */
25787 #define ALT_GIC_DIST_GICD_SPISR4_FLD_SET_MSK 0xffffffff
25788 /* The mask used to clear the ALT_GIC_DIST_GICD_SPISR4_FLD register field value. */
25789 #define ALT_GIC_DIST_GICD_SPISR4_FLD_CLR_MSK 0x00000000
25790 /* The reset value of the ALT_GIC_DIST_GICD_SPISR4_FLD register field. */
25791 #define ALT_GIC_DIST_GICD_SPISR4_FLD_RESET 0x0
25792 /* Extracts the ALT_GIC_DIST_GICD_SPISR4_FLD field value from a register. */
25793 #define ALT_GIC_DIST_GICD_SPISR4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25794 /* Produces a ALT_GIC_DIST_GICD_SPISR4_FLD register field value suitable for setting the register. */
25795 #define ALT_GIC_DIST_GICD_SPISR4_FLD_SET(value) (((value) << 0) & 0xffffffff)
25796 
25797 #ifndef __ASSEMBLY__
25798 /*
25799  * WARNING: The C register and register group struct declarations are provided for
25800  * convenience and illustrative purposes. They should, however, be used with
25801  * caution as the C language standard provides no guarantees about the alignment or
25802  * atomicity of device memory accesses. The recommended practice for coding device
25803  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25804  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25805  * alt_write_dword() functions for 64 bit registers.
25806  *
25807  * The struct declaration for register ALT_GIC_DIST_GICD_SPISR4.
25808  */
25809 struct ALT_GIC_DIST_GICD_SPISR4_s
25810 {
25811  volatile uint32_t fld : 32; /* Empty */
25812 };
25813 
25814 /* The typedef declaration for register ALT_GIC_DIST_GICD_SPISR4. */
25815 typedef struct ALT_GIC_DIST_GICD_SPISR4_s ALT_GIC_DIST_GICD_SPISR4_t;
25816 #endif /* __ASSEMBLY__ */
25817 
25818 /* The reset value of the ALT_GIC_DIST_GICD_SPISR4 register. */
25819 #define ALT_GIC_DIST_GICD_SPISR4_RESET 0x00000000
25820 /* The byte offset of the ALT_GIC_DIST_GICD_SPISR4 register from the beginning of the component. */
25821 #define ALT_GIC_DIST_GICD_SPISR4_OFST 0xd14
25822 
25823 /*
25824  * Register : GICD_SPISR5
25825  *
25826  * Shared Peripheral Interrupt Status Registers
25827  *
25828  * Register Layout
25829  *
25830  * Bits | Access | Reset | Description
25831  * :-------|:-------|:------|:------------
25832  * [31:0] | RW | 0x0 | Empty
25833  *
25834  */
25835 /*
25836  * Field : Empty - fld
25837  *
25838  * Placeholder
25839  *
25840  * Field Access Macros:
25841  *
25842  */
25843 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_SPISR5_FLD register field. */
25844 #define ALT_GIC_DIST_GICD_SPISR5_FLD_LSB 0
25845 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_SPISR5_FLD register field. */
25846 #define ALT_GIC_DIST_GICD_SPISR5_FLD_MSB 31
25847 /* The width in bits of the ALT_GIC_DIST_GICD_SPISR5_FLD register field. */
25848 #define ALT_GIC_DIST_GICD_SPISR5_FLD_WIDTH 32
25849 /* The mask used to set the ALT_GIC_DIST_GICD_SPISR5_FLD register field value. */
25850 #define ALT_GIC_DIST_GICD_SPISR5_FLD_SET_MSK 0xffffffff
25851 /* The mask used to clear the ALT_GIC_DIST_GICD_SPISR5_FLD register field value. */
25852 #define ALT_GIC_DIST_GICD_SPISR5_FLD_CLR_MSK 0x00000000
25853 /* The reset value of the ALT_GIC_DIST_GICD_SPISR5_FLD register field. */
25854 #define ALT_GIC_DIST_GICD_SPISR5_FLD_RESET 0x0
25855 /* Extracts the ALT_GIC_DIST_GICD_SPISR5_FLD field value from a register. */
25856 #define ALT_GIC_DIST_GICD_SPISR5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25857 /* Produces a ALT_GIC_DIST_GICD_SPISR5_FLD register field value suitable for setting the register. */
25858 #define ALT_GIC_DIST_GICD_SPISR5_FLD_SET(value) (((value) << 0) & 0xffffffff)
25859 
25860 #ifndef __ASSEMBLY__
25861 /*
25862  * WARNING: The C register and register group struct declarations are provided for
25863  * convenience and illustrative purposes. They should, however, be used with
25864  * caution as the C language standard provides no guarantees about the alignment or
25865  * atomicity of device memory accesses. The recommended practice for coding device
25866  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25867  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25868  * alt_write_dword() functions for 64 bit registers.
25869  *
25870  * The struct declaration for register ALT_GIC_DIST_GICD_SPISR5.
25871  */
25872 struct ALT_GIC_DIST_GICD_SPISR5_s
25873 {
25874  volatile uint32_t fld : 32; /* Empty */
25875 };
25876 
25877 /* The typedef declaration for register ALT_GIC_DIST_GICD_SPISR5. */
25878 typedef struct ALT_GIC_DIST_GICD_SPISR5_s ALT_GIC_DIST_GICD_SPISR5_t;
25879 #endif /* __ASSEMBLY__ */
25880 
25881 /* The reset value of the ALT_GIC_DIST_GICD_SPISR5 register. */
25882 #define ALT_GIC_DIST_GICD_SPISR5_RESET 0x00000000
25883 /* The byte offset of the ALT_GIC_DIST_GICD_SPISR5 register from the beginning of the component. */
25884 #define ALT_GIC_DIST_GICD_SPISR5_OFST 0xd18
25885 
25886 /*
25887  * Register : GICD_SPISR6
25888  *
25889  * Shared Peripheral Interrupt Status Registers
25890  *
25891  * Register Layout
25892  *
25893  * Bits | Access | Reset | Description
25894  * :-------|:-------|:------|:------------
25895  * [31:0] | RW | 0x0 | Empty
25896  *
25897  */
25898 /*
25899  * Field : Empty - fld
25900  *
25901  * Placeholder
25902  *
25903  * Field Access Macros:
25904  *
25905  */
25906 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_SPISR6_FLD register field. */
25907 #define ALT_GIC_DIST_GICD_SPISR6_FLD_LSB 0
25908 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_SPISR6_FLD register field. */
25909 #define ALT_GIC_DIST_GICD_SPISR6_FLD_MSB 31
25910 /* The width in bits of the ALT_GIC_DIST_GICD_SPISR6_FLD register field. */
25911 #define ALT_GIC_DIST_GICD_SPISR6_FLD_WIDTH 32
25912 /* The mask used to set the ALT_GIC_DIST_GICD_SPISR6_FLD register field value. */
25913 #define ALT_GIC_DIST_GICD_SPISR6_FLD_SET_MSK 0xffffffff
25914 /* The mask used to clear the ALT_GIC_DIST_GICD_SPISR6_FLD register field value. */
25915 #define ALT_GIC_DIST_GICD_SPISR6_FLD_CLR_MSK 0x00000000
25916 /* The reset value of the ALT_GIC_DIST_GICD_SPISR6_FLD register field. */
25917 #define ALT_GIC_DIST_GICD_SPISR6_FLD_RESET 0x0
25918 /* Extracts the ALT_GIC_DIST_GICD_SPISR6_FLD field value from a register. */
25919 #define ALT_GIC_DIST_GICD_SPISR6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25920 /* Produces a ALT_GIC_DIST_GICD_SPISR6_FLD register field value suitable for setting the register. */
25921 #define ALT_GIC_DIST_GICD_SPISR6_FLD_SET(value) (((value) << 0) & 0xffffffff)
25922 
25923 #ifndef __ASSEMBLY__
25924 /*
25925  * WARNING: The C register and register group struct declarations are provided for
25926  * convenience and illustrative purposes. They should, however, be used with
25927  * caution as the C language standard provides no guarantees about the alignment or
25928  * atomicity of device memory accesses. The recommended practice for coding device
25929  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25930  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25931  * alt_write_dword() functions for 64 bit registers.
25932  *
25933  * The struct declaration for register ALT_GIC_DIST_GICD_SPISR6.
25934  */
25935 struct ALT_GIC_DIST_GICD_SPISR6_s
25936 {
25937  volatile uint32_t fld : 32; /* Empty */
25938 };
25939 
25940 /* The typedef declaration for register ALT_GIC_DIST_GICD_SPISR6. */
25941 typedef struct ALT_GIC_DIST_GICD_SPISR6_s ALT_GIC_DIST_GICD_SPISR6_t;
25942 #endif /* __ASSEMBLY__ */
25943 
25944 /* The reset value of the ALT_GIC_DIST_GICD_SPISR6 register. */
25945 #define ALT_GIC_DIST_GICD_SPISR6_RESET 0x00000000
25946 /* The byte offset of the ALT_GIC_DIST_GICD_SPISR6 register from the beginning of the component. */
25947 #define ALT_GIC_DIST_GICD_SPISR6_OFST 0xd1c
25948 
25949 /*
25950  * Register : GICD_SPISR7
25951  *
25952  * Shared Peripheral Interrupt Status Registers
25953  *
25954  * Register Layout
25955  *
25956  * Bits | Access | Reset | Description
25957  * :-------|:-------|:------|:------------
25958  * [31:0] | RW | 0x0 | Empty
25959  *
25960  */
25961 /*
25962  * Field : Empty - fld
25963  *
25964  * Placeholder
25965  *
25966  * Field Access Macros:
25967  *
25968  */
25969 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_SPISR7_FLD register field. */
25970 #define ALT_GIC_DIST_GICD_SPISR7_FLD_LSB 0
25971 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_SPISR7_FLD register field. */
25972 #define ALT_GIC_DIST_GICD_SPISR7_FLD_MSB 31
25973 /* The width in bits of the ALT_GIC_DIST_GICD_SPISR7_FLD register field. */
25974 #define ALT_GIC_DIST_GICD_SPISR7_FLD_WIDTH 32
25975 /* The mask used to set the ALT_GIC_DIST_GICD_SPISR7_FLD register field value. */
25976 #define ALT_GIC_DIST_GICD_SPISR7_FLD_SET_MSK 0xffffffff
25977 /* The mask used to clear the ALT_GIC_DIST_GICD_SPISR7_FLD register field value. */
25978 #define ALT_GIC_DIST_GICD_SPISR7_FLD_CLR_MSK 0x00000000
25979 /* The reset value of the ALT_GIC_DIST_GICD_SPISR7_FLD register field. */
25980 #define ALT_GIC_DIST_GICD_SPISR7_FLD_RESET 0x0
25981 /* Extracts the ALT_GIC_DIST_GICD_SPISR7_FLD field value from a register. */
25982 #define ALT_GIC_DIST_GICD_SPISR7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
25983 /* Produces a ALT_GIC_DIST_GICD_SPISR7_FLD register field value suitable for setting the register. */
25984 #define ALT_GIC_DIST_GICD_SPISR7_FLD_SET(value) (((value) << 0) & 0xffffffff)
25985 
25986 #ifndef __ASSEMBLY__
25987 /*
25988  * WARNING: The C register and register group struct declarations are provided for
25989  * convenience and illustrative purposes. They should, however, be used with
25990  * caution as the C language standard provides no guarantees about the alignment or
25991  * atomicity of device memory accesses. The recommended practice for coding device
25992  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
25993  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
25994  * alt_write_dword() functions for 64 bit registers.
25995  *
25996  * The struct declaration for register ALT_GIC_DIST_GICD_SPISR7.
25997  */
25998 struct ALT_GIC_DIST_GICD_SPISR7_s
25999 {
26000  volatile uint32_t fld : 32; /* Empty */
26001 };
26002 
26003 /* The typedef declaration for register ALT_GIC_DIST_GICD_SPISR7. */
26004 typedef struct ALT_GIC_DIST_GICD_SPISR7_s ALT_GIC_DIST_GICD_SPISR7_t;
26005 #endif /* __ASSEMBLY__ */
26006 
26007 /* The reset value of the ALT_GIC_DIST_GICD_SPISR7 register. */
26008 #define ALT_GIC_DIST_GICD_SPISR7_RESET 0x00000000
26009 /* The byte offset of the ALT_GIC_DIST_GICD_SPISR7 register from the beginning of the component. */
26010 #define ALT_GIC_DIST_GICD_SPISR7_OFST 0xd20
26011 
26012 /*
26013  * Register : GICD_SPISR8
26014  *
26015  * Shared Peripheral Interrupt Status Registers
26016  *
26017  * Register Layout
26018  *
26019  * Bits | Access | Reset | Description
26020  * :-------|:-------|:------|:------------
26021  * [31:0] | RW | 0x0 | Empty
26022  *
26023  */
26024 /*
26025  * Field : Empty - fld
26026  *
26027  * Placeholder
26028  *
26029  * Field Access Macros:
26030  *
26031  */
26032 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_SPISR8_FLD register field. */
26033 #define ALT_GIC_DIST_GICD_SPISR8_FLD_LSB 0
26034 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_SPISR8_FLD register field. */
26035 #define ALT_GIC_DIST_GICD_SPISR8_FLD_MSB 31
26036 /* The width in bits of the ALT_GIC_DIST_GICD_SPISR8_FLD register field. */
26037 #define ALT_GIC_DIST_GICD_SPISR8_FLD_WIDTH 32
26038 /* The mask used to set the ALT_GIC_DIST_GICD_SPISR8_FLD register field value. */
26039 #define ALT_GIC_DIST_GICD_SPISR8_FLD_SET_MSK 0xffffffff
26040 /* The mask used to clear the ALT_GIC_DIST_GICD_SPISR8_FLD register field value. */
26041 #define ALT_GIC_DIST_GICD_SPISR8_FLD_CLR_MSK 0x00000000
26042 /* The reset value of the ALT_GIC_DIST_GICD_SPISR8_FLD register field. */
26043 #define ALT_GIC_DIST_GICD_SPISR8_FLD_RESET 0x0
26044 /* Extracts the ALT_GIC_DIST_GICD_SPISR8_FLD field value from a register. */
26045 #define ALT_GIC_DIST_GICD_SPISR8_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26046 /* Produces a ALT_GIC_DIST_GICD_SPISR8_FLD register field value suitable for setting the register. */
26047 #define ALT_GIC_DIST_GICD_SPISR8_FLD_SET(value) (((value) << 0) & 0xffffffff)
26048 
26049 #ifndef __ASSEMBLY__
26050 /*
26051  * WARNING: The C register and register group struct declarations are provided for
26052  * convenience and illustrative purposes. They should, however, be used with
26053  * caution as the C language standard provides no guarantees about the alignment or
26054  * atomicity of device memory accesses. The recommended practice for coding device
26055  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26056  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26057  * alt_write_dword() functions for 64 bit registers.
26058  *
26059  * The struct declaration for register ALT_GIC_DIST_GICD_SPISR8.
26060  */
26061 struct ALT_GIC_DIST_GICD_SPISR8_s
26062 {
26063  volatile uint32_t fld : 32; /* Empty */
26064 };
26065 
26066 /* The typedef declaration for register ALT_GIC_DIST_GICD_SPISR8. */
26067 typedef struct ALT_GIC_DIST_GICD_SPISR8_s ALT_GIC_DIST_GICD_SPISR8_t;
26068 #endif /* __ASSEMBLY__ */
26069 
26070 /* The reset value of the ALT_GIC_DIST_GICD_SPISR8 register. */
26071 #define ALT_GIC_DIST_GICD_SPISR8_RESET 0x00000000
26072 /* The byte offset of the ALT_GIC_DIST_GICD_SPISR8 register from the beginning of the component. */
26073 #define ALT_GIC_DIST_GICD_SPISR8_OFST 0xd24
26074 
26075 /*
26076  * Register : GICD_SPISR9
26077  *
26078  * Shared Peripheral Interrupt Status Registers
26079  *
26080  * Register Layout
26081  *
26082  * Bits | Access | Reset | Description
26083  * :-------|:-------|:------|:------------
26084  * [31:0] | RW | 0x0 | Empty
26085  *
26086  */
26087 /*
26088  * Field : Empty - fld
26089  *
26090  * Placeholder
26091  *
26092  * Field Access Macros:
26093  *
26094  */
26095 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_SPISR9_FLD register field. */
26096 #define ALT_GIC_DIST_GICD_SPISR9_FLD_LSB 0
26097 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_SPISR9_FLD register field. */
26098 #define ALT_GIC_DIST_GICD_SPISR9_FLD_MSB 31
26099 /* The width in bits of the ALT_GIC_DIST_GICD_SPISR9_FLD register field. */
26100 #define ALT_GIC_DIST_GICD_SPISR9_FLD_WIDTH 32
26101 /* The mask used to set the ALT_GIC_DIST_GICD_SPISR9_FLD register field value. */
26102 #define ALT_GIC_DIST_GICD_SPISR9_FLD_SET_MSK 0xffffffff
26103 /* The mask used to clear the ALT_GIC_DIST_GICD_SPISR9_FLD register field value. */
26104 #define ALT_GIC_DIST_GICD_SPISR9_FLD_CLR_MSK 0x00000000
26105 /* The reset value of the ALT_GIC_DIST_GICD_SPISR9_FLD register field. */
26106 #define ALT_GIC_DIST_GICD_SPISR9_FLD_RESET 0x0
26107 /* Extracts the ALT_GIC_DIST_GICD_SPISR9_FLD field value from a register. */
26108 #define ALT_GIC_DIST_GICD_SPISR9_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26109 /* Produces a ALT_GIC_DIST_GICD_SPISR9_FLD register field value suitable for setting the register. */
26110 #define ALT_GIC_DIST_GICD_SPISR9_FLD_SET(value) (((value) << 0) & 0xffffffff)
26111 
26112 #ifndef __ASSEMBLY__
26113 /*
26114  * WARNING: The C register and register group struct declarations are provided for
26115  * convenience and illustrative purposes. They should, however, be used with
26116  * caution as the C language standard provides no guarantees about the alignment or
26117  * atomicity of device memory accesses. The recommended practice for coding device
26118  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26119  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26120  * alt_write_dword() functions for 64 bit registers.
26121  *
26122  * The struct declaration for register ALT_GIC_DIST_GICD_SPISR9.
26123  */
26124 struct ALT_GIC_DIST_GICD_SPISR9_s
26125 {
26126  volatile uint32_t fld : 32; /* Empty */
26127 };
26128 
26129 /* The typedef declaration for register ALT_GIC_DIST_GICD_SPISR9. */
26130 typedef struct ALT_GIC_DIST_GICD_SPISR9_s ALT_GIC_DIST_GICD_SPISR9_t;
26131 #endif /* __ASSEMBLY__ */
26132 
26133 /* The reset value of the ALT_GIC_DIST_GICD_SPISR9 register. */
26134 #define ALT_GIC_DIST_GICD_SPISR9_RESET 0x00000000
26135 /* The byte offset of the ALT_GIC_DIST_GICD_SPISR9 register from the beginning of the component. */
26136 #define ALT_GIC_DIST_GICD_SPISR9_OFST 0xd28
26137 
26138 /*
26139  * Register : GICD_SPISR10
26140  *
26141  * Shared Peripheral Interrupt Status Registers
26142  *
26143  * Register Layout
26144  *
26145  * Bits | Access | Reset | Description
26146  * :-------|:-------|:------|:------------
26147  * [31:0] | RW | 0x0 | Empty
26148  *
26149  */
26150 /*
26151  * Field : Empty - fld
26152  *
26153  * Placeholder
26154  *
26155  * Field Access Macros:
26156  *
26157  */
26158 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_SPISR10_FLD register field. */
26159 #define ALT_GIC_DIST_GICD_SPISR10_FLD_LSB 0
26160 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_SPISR10_FLD register field. */
26161 #define ALT_GIC_DIST_GICD_SPISR10_FLD_MSB 31
26162 /* The width in bits of the ALT_GIC_DIST_GICD_SPISR10_FLD register field. */
26163 #define ALT_GIC_DIST_GICD_SPISR10_FLD_WIDTH 32
26164 /* The mask used to set the ALT_GIC_DIST_GICD_SPISR10_FLD register field value. */
26165 #define ALT_GIC_DIST_GICD_SPISR10_FLD_SET_MSK 0xffffffff
26166 /* The mask used to clear the ALT_GIC_DIST_GICD_SPISR10_FLD register field value. */
26167 #define ALT_GIC_DIST_GICD_SPISR10_FLD_CLR_MSK 0x00000000
26168 /* The reset value of the ALT_GIC_DIST_GICD_SPISR10_FLD register field. */
26169 #define ALT_GIC_DIST_GICD_SPISR10_FLD_RESET 0x0
26170 /* Extracts the ALT_GIC_DIST_GICD_SPISR10_FLD field value from a register. */
26171 #define ALT_GIC_DIST_GICD_SPISR10_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26172 /* Produces a ALT_GIC_DIST_GICD_SPISR10_FLD register field value suitable for setting the register. */
26173 #define ALT_GIC_DIST_GICD_SPISR10_FLD_SET(value) (((value) << 0) & 0xffffffff)
26174 
26175 #ifndef __ASSEMBLY__
26176 /*
26177  * WARNING: The C register and register group struct declarations are provided for
26178  * convenience and illustrative purposes. They should, however, be used with
26179  * caution as the C language standard provides no guarantees about the alignment or
26180  * atomicity of device memory accesses. The recommended practice for coding device
26181  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26182  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26183  * alt_write_dword() functions for 64 bit registers.
26184  *
26185  * The struct declaration for register ALT_GIC_DIST_GICD_SPISR10.
26186  */
26187 struct ALT_GIC_DIST_GICD_SPISR10_s
26188 {
26189  volatile uint32_t fld : 32; /* Empty */
26190 };
26191 
26192 /* The typedef declaration for register ALT_GIC_DIST_GICD_SPISR10. */
26193 typedef struct ALT_GIC_DIST_GICD_SPISR10_s ALT_GIC_DIST_GICD_SPISR10_t;
26194 #endif /* __ASSEMBLY__ */
26195 
26196 /* The reset value of the ALT_GIC_DIST_GICD_SPISR10 register. */
26197 #define ALT_GIC_DIST_GICD_SPISR10_RESET 0x00000000
26198 /* The byte offset of the ALT_GIC_DIST_GICD_SPISR10 register from the beginning of the component. */
26199 #define ALT_GIC_DIST_GICD_SPISR10_OFST 0xd2c
26200 
26201 /*
26202  * Register : GICD_SPISR11
26203  *
26204  * Shared Peripheral Interrupt Status Registers
26205  *
26206  * Register Layout
26207  *
26208  * Bits | Access | Reset | Description
26209  * :-------|:-------|:------|:------------
26210  * [31:0] | RW | 0x0 | Empty
26211  *
26212  */
26213 /*
26214  * Field : Empty - fld
26215  *
26216  * Placeholder
26217  *
26218  * Field Access Macros:
26219  *
26220  */
26221 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_SPISR11_FLD register field. */
26222 #define ALT_GIC_DIST_GICD_SPISR11_FLD_LSB 0
26223 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_SPISR11_FLD register field. */
26224 #define ALT_GIC_DIST_GICD_SPISR11_FLD_MSB 31
26225 /* The width in bits of the ALT_GIC_DIST_GICD_SPISR11_FLD register field. */
26226 #define ALT_GIC_DIST_GICD_SPISR11_FLD_WIDTH 32
26227 /* The mask used to set the ALT_GIC_DIST_GICD_SPISR11_FLD register field value. */
26228 #define ALT_GIC_DIST_GICD_SPISR11_FLD_SET_MSK 0xffffffff
26229 /* The mask used to clear the ALT_GIC_DIST_GICD_SPISR11_FLD register field value. */
26230 #define ALT_GIC_DIST_GICD_SPISR11_FLD_CLR_MSK 0x00000000
26231 /* The reset value of the ALT_GIC_DIST_GICD_SPISR11_FLD register field. */
26232 #define ALT_GIC_DIST_GICD_SPISR11_FLD_RESET 0x0
26233 /* Extracts the ALT_GIC_DIST_GICD_SPISR11_FLD field value from a register. */
26234 #define ALT_GIC_DIST_GICD_SPISR11_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26235 /* Produces a ALT_GIC_DIST_GICD_SPISR11_FLD register field value suitable for setting the register. */
26236 #define ALT_GIC_DIST_GICD_SPISR11_FLD_SET(value) (((value) << 0) & 0xffffffff)
26237 
26238 #ifndef __ASSEMBLY__
26239 /*
26240  * WARNING: The C register and register group struct declarations are provided for
26241  * convenience and illustrative purposes. They should, however, be used with
26242  * caution as the C language standard provides no guarantees about the alignment or
26243  * atomicity of device memory accesses. The recommended practice for coding device
26244  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26245  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26246  * alt_write_dword() functions for 64 bit registers.
26247  *
26248  * The struct declaration for register ALT_GIC_DIST_GICD_SPISR11.
26249  */
26250 struct ALT_GIC_DIST_GICD_SPISR11_s
26251 {
26252  volatile uint32_t fld : 32; /* Empty */
26253 };
26254 
26255 /* The typedef declaration for register ALT_GIC_DIST_GICD_SPISR11. */
26256 typedef struct ALT_GIC_DIST_GICD_SPISR11_s ALT_GIC_DIST_GICD_SPISR11_t;
26257 #endif /* __ASSEMBLY__ */
26258 
26259 /* The reset value of the ALT_GIC_DIST_GICD_SPISR11 register. */
26260 #define ALT_GIC_DIST_GICD_SPISR11_RESET 0x00000000
26261 /* The byte offset of the ALT_GIC_DIST_GICD_SPISR11 register from the beginning of the component. */
26262 #define ALT_GIC_DIST_GICD_SPISR11_OFST 0xd30
26263 
26264 /*
26265  * Register : GICD_SPISR12
26266  *
26267  * Shared Peripheral Interrupt Status Registers
26268  *
26269  * Register Layout
26270  *
26271  * Bits | Access | Reset | Description
26272  * :-------|:-------|:------|:------------
26273  * [31:0] | RW | 0x0 | Empty
26274  *
26275  */
26276 /*
26277  * Field : Empty - fld
26278  *
26279  * Placeholder
26280  *
26281  * Field Access Macros:
26282  *
26283  */
26284 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_SPISR12_FLD register field. */
26285 #define ALT_GIC_DIST_GICD_SPISR12_FLD_LSB 0
26286 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_SPISR12_FLD register field. */
26287 #define ALT_GIC_DIST_GICD_SPISR12_FLD_MSB 31
26288 /* The width in bits of the ALT_GIC_DIST_GICD_SPISR12_FLD register field. */
26289 #define ALT_GIC_DIST_GICD_SPISR12_FLD_WIDTH 32
26290 /* The mask used to set the ALT_GIC_DIST_GICD_SPISR12_FLD register field value. */
26291 #define ALT_GIC_DIST_GICD_SPISR12_FLD_SET_MSK 0xffffffff
26292 /* The mask used to clear the ALT_GIC_DIST_GICD_SPISR12_FLD register field value. */
26293 #define ALT_GIC_DIST_GICD_SPISR12_FLD_CLR_MSK 0x00000000
26294 /* The reset value of the ALT_GIC_DIST_GICD_SPISR12_FLD register field. */
26295 #define ALT_GIC_DIST_GICD_SPISR12_FLD_RESET 0x0
26296 /* Extracts the ALT_GIC_DIST_GICD_SPISR12_FLD field value from a register. */
26297 #define ALT_GIC_DIST_GICD_SPISR12_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26298 /* Produces a ALT_GIC_DIST_GICD_SPISR12_FLD register field value suitable for setting the register. */
26299 #define ALT_GIC_DIST_GICD_SPISR12_FLD_SET(value) (((value) << 0) & 0xffffffff)
26300 
26301 #ifndef __ASSEMBLY__
26302 /*
26303  * WARNING: The C register and register group struct declarations are provided for
26304  * convenience and illustrative purposes. They should, however, be used with
26305  * caution as the C language standard provides no guarantees about the alignment or
26306  * atomicity of device memory accesses. The recommended practice for coding device
26307  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26308  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26309  * alt_write_dword() functions for 64 bit registers.
26310  *
26311  * The struct declaration for register ALT_GIC_DIST_GICD_SPISR12.
26312  */
26313 struct ALT_GIC_DIST_GICD_SPISR12_s
26314 {
26315  volatile uint32_t fld : 32; /* Empty */
26316 };
26317 
26318 /* The typedef declaration for register ALT_GIC_DIST_GICD_SPISR12. */
26319 typedef struct ALT_GIC_DIST_GICD_SPISR12_s ALT_GIC_DIST_GICD_SPISR12_t;
26320 #endif /* __ASSEMBLY__ */
26321 
26322 /* The reset value of the ALT_GIC_DIST_GICD_SPISR12 register. */
26323 #define ALT_GIC_DIST_GICD_SPISR12_RESET 0x00000000
26324 /* The byte offset of the ALT_GIC_DIST_GICD_SPISR12 register from the beginning of the component. */
26325 #define ALT_GIC_DIST_GICD_SPISR12_OFST 0xd34
26326 
26327 /*
26328  * Register : GICD_SPISR13
26329  *
26330  * Shared Peripheral Interrupt Status Registers
26331  *
26332  * Register Layout
26333  *
26334  * Bits | Access | Reset | Description
26335  * :-------|:-------|:------|:------------
26336  * [31:0] | RW | 0x0 | Empty
26337  *
26338  */
26339 /*
26340  * Field : Empty - fld
26341  *
26342  * Placeholder
26343  *
26344  * Field Access Macros:
26345  *
26346  */
26347 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_SPISR13_FLD register field. */
26348 #define ALT_GIC_DIST_GICD_SPISR13_FLD_LSB 0
26349 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_SPISR13_FLD register field. */
26350 #define ALT_GIC_DIST_GICD_SPISR13_FLD_MSB 31
26351 /* The width in bits of the ALT_GIC_DIST_GICD_SPISR13_FLD register field. */
26352 #define ALT_GIC_DIST_GICD_SPISR13_FLD_WIDTH 32
26353 /* The mask used to set the ALT_GIC_DIST_GICD_SPISR13_FLD register field value. */
26354 #define ALT_GIC_DIST_GICD_SPISR13_FLD_SET_MSK 0xffffffff
26355 /* The mask used to clear the ALT_GIC_DIST_GICD_SPISR13_FLD register field value. */
26356 #define ALT_GIC_DIST_GICD_SPISR13_FLD_CLR_MSK 0x00000000
26357 /* The reset value of the ALT_GIC_DIST_GICD_SPISR13_FLD register field. */
26358 #define ALT_GIC_DIST_GICD_SPISR13_FLD_RESET 0x0
26359 /* Extracts the ALT_GIC_DIST_GICD_SPISR13_FLD field value from a register. */
26360 #define ALT_GIC_DIST_GICD_SPISR13_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26361 /* Produces a ALT_GIC_DIST_GICD_SPISR13_FLD register field value suitable for setting the register. */
26362 #define ALT_GIC_DIST_GICD_SPISR13_FLD_SET(value) (((value) << 0) & 0xffffffff)
26363 
26364 #ifndef __ASSEMBLY__
26365 /*
26366  * WARNING: The C register and register group struct declarations are provided for
26367  * convenience and illustrative purposes. They should, however, be used with
26368  * caution as the C language standard provides no guarantees about the alignment or
26369  * atomicity of device memory accesses. The recommended practice for coding device
26370  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26371  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26372  * alt_write_dword() functions for 64 bit registers.
26373  *
26374  * The struct declaration for register ALT_GIC_DIST_GICD_SPISR13.
26375  */
26376 struct ALT_GIC_DIST_GICD_SPISR13_s
26377 {
26378  volatile uint32_t fld : 32; /* Empty */
26379 };
26380 
26381 /* The typedef declaration for register ALT_GIC_DIST_GICD_SPISR13. */
26382 typedef struct ALT_GIC_DIST_GICD_SPISR13_s ALT_GIC_DIST_GICD_SPISR13_t;
26383 #endif /* __ASSEMBLY__ */
26384 
26385 /* The reset value of the ALT_GIC_DIST_GICD_SPISR13 register. */
26386 #define ALT_GIC_DIST_GICD_SPISR13_RESET 0x00000000
26387 /* The byte offset of the ALT_GIC_DIST_GICD_SPISR13 register from the beginning of the component. */
26388 #define ALT_GIC_DIST_GICD_SPISR13_OFST 0xd38
26389 
26390 /*
26391  * Register : GICD_SPISR14
26392  *
26393  * Shared Peripheral Interrupt Status Registers
26394  *
26395  * Register Layout
26396  *
26397  * Bits | Access | Reset | Description
26398  * :-------|:-------|:------|:------------
26399  * [31:0] | RW | 0x0 | Empty
26400  *
26401  */
26402 /*
26403  * Field : Empty - fld
26404  *
26405  * Placeholder
26406  *
26407  * Field Access Macros:
26408  *
26409  */
26410 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_SPISR14_FLD register field. */
26411 #define ALT_GIC_DIST_GICD_SPISR14_FLD_LSB 0
26412 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_SPISR14_FLD register field. */
26413 #define ALT_GIC_DIST_GICD_SPISR14_FLD_MSB 31
26414 /* The width in bits of the ALT_GIC_DIST_GICD_SPISR14_FLD register field. */
26415 #define ALT_GIC_DIST_GICD_SPISR14_FLD_WIDTH 32
26416 /* The mask used to set the ALT_GIC_DIST_GICD_SPISR14_FLD register field value. */
26417 #define ALT_GIC_DIST_GICD_SPISR14_FLD_SET_MSK 0xffffffff
26418 /* The mask used to clear the ALT_GIC_DIST_GICD_SPISR14_FLD register field value. */
26419 #define ALT_GIC_DIST_GICD_SPISR14_FLD_CLR_MSK 0x00000000
26420 /* The reset value of the ALT_GIC_DIST_GICD_SPISR14_FLD register field. */
26421 #define ALT_GIC_DIST_GICD_SPISR14_FLD_RESET 0x0
26422 /* Extracts the ALT_GIC_DIST_GICD_SPISR14_FLD field value from a register. */
26423 #define ALT_GIC_DIST_GICD_SPISR14_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26424 /* Produces a ALT_GIC_DIST_GICD_SPISR14_FLD register field value suitable for setting the register. */
26425 #define ALT_GIC_DIST_GICD_SPISR14_FLD_SET(value) (((value) << 0) & 0xffffffff)
26426 
26427 #ifndef __ASSEMBLY__
26428 /*
26429  * WARNING: The C register and register group struct declarations are provided for
26430  * convenience and illustrative purposes. They should, however, be used with
26431  * caution as the C language standard provides no guarantees about the alignment or
26432  * atomicity of device memory accesses. The recommended practice for coding device
26433  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26434  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26435  * alt_write_dword() functions for 64 bit registers.
26436  *
26437  * The struct declaration for register ALT_GIC_DIST_GICD_SPISR14.
26438  */
26439 struct ALT_GIC_DIST_GICD_SPISR14_s
26440 {
26441  volatile uint32_t fld : 32; /* Empty */
26442 };
26443 
26444 /* The typedef declaration for register ALT_GIC_DIST_GICD_SPISR14. */
26445 typedef struct ALT_GIC_DIST_GICD_SPISR14_s ALT_GIC_DIST_GICD_SPISR14_t;
26446 #endif /* __ASSEMBLY__ */
26447 
26448 /* The reset value of the ALT_GIC_DIST_GICD_SPISR14 register. */
26449 #define ALT_GIC_DIST_GICD_SPISR14_RESET 0x00000000
26450 /* The byte offset of the ALT_GIC_DIST_GICD_SPISR14 register from the beginning of the component. */
26451 #define ALT_GIC_DIST_GICD_SPISR14_OFST 0xd3c
26452 
26453 /*
26454  * Register : GICD_SGIR
26455  *
26456  * Software Generated Interrupt Register
26457  *
26458  * Register Layout
26459  *
26460  * Bits | Access | Reset | Description
26461  * :-------|:-------|:--------|:------------
26462  * [31:0] | RW | Unknown | Empty
26463  *
26464  */
26465 /*
26466  * Field : Empty - fld
26467  *
26468  * Placeholder
26469  *
26470  * Field Access Macros:
26471  *
26472  */
26473 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_SGIR_FLD register field. */
26474 #define ALT_GIC_DIST_GICD_SGIR_FLD_LSB 0
26475 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_SGIR_FLD register field. */
26476 #define ALT_GIC_DIST_GICD_SGIR_FLD_MSB 31
26477 /* The width in bits of the ALT_GIC_DIST_GICD_SGIR_FLD register field. */
26478 #define ALT_GIC_DIST_GICD_SGIR_FLD_WIDTH 32
26479 /* The mask used to set the ALT_GIC_DIST_GICD_SGIR_FLD register field value. */
26480 #define ALT_GIC_DIST_GICD_SGIR_FLD_SET_MSK 0xffffffff
26481 /* The mask used to clear the ALT_GIC_DIST_GICD_SGIR_FLD register field value. */
26482 #define ALT_GIC_DIST_GICD_SGIR_FLD_CLR_MSK 0x00000000
26483 /* The reset value of the ALT_GIC_DIST_GICD_SGIR_FLD register field is UNKNOWN. */
26484 #define ALT_GIC_DIST_GICD_SGIR_FLD_RESET 0x0
26485 /* Extracts the ALT_GIC_DIST_GICD_SGIR_FLD field value from a register. */
26486 #define ALT_GIC_DIST_GICD_SGIR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26487 /* Produces a ALT_GIC_DIST_GICD_SGIR_FLD register field value suitable for setting the register. */
26488 #define ALT_GIC_DIST_GICD_SGIR_FLD_SET(value) (((value) << 0) & 0xffffffff)
26489 
26490 #ifndef __ASSEMBLY__
26491 /*
26492  * WARNING: The C register and register group struct declarations are provided for
26493  * convenience and illustrative purposes. They should, however, be used with
26494  * caution as the C language standard provides no guarantees about the alignment or
26495  * atomicity of device memory accesses. The recommended practice for coding device
26496  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26497  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26498  * alt_write_dword() functions for 64 bit registers.
26499  *
26500  * The struct declaration for register ALT_GIC_DIST_GICD_SGIR.
26501  */
26502 struct ALT_GIC_DIST_GICD_SGIR_s
26503 {
26504  volatile uint32_t fld : 32; /* Empty */
26505 };
26506 
26507 /* The typedef declaration for register ALT_GIC_DIST_GICD_SGIR. */
26508 typedef struct ALT_GIC_DIST_GICD_SGIR_s ALT_GIC_DIST_GICD_SGIR_t;
26509 #endif /* __ASSEMBLY__ */
26510 
26511 /* The reset value of the ALT_GIC_DIST_GICD_SGIR register. */
26512 #define ALT_GIC_DIST_GICD_SGIR_RESET 0x00000000
26513 /* The byte offset of the ALT_GIC_DIST_GICD_SGIR register from the beginning of the component. */
26514 #define ALT_GIC_DIST_GICD_SGIR_OFST 0xf00
26515 
26516 /*
26517  * Register : GICD_CPENDSGIR0
26518  *
26519  * SGI Clear-Pending Registers
26520  *
26521  * Register Layout
26522  *
26523  * Bits | Access | Reset | Description
26524  * :-------|:-------|:------|:------------
26525  * [31:0] | RW | 0x0 | Empty
26526  *
26527  */
26528 /*
26529  * Field : Empty - fld
26530  *
26531  * Placeholder
26532  *
26533  * Field Access Macros:
26534  *
26535  */
26536 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_CPENDSGIR0_FLD register field. */
26537 #define ALT_GIC_DIST_GICD_CPENDSGIR0_FLD_LSB 0
26538 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_CPENDSGIR0_FLD register field. */
26539 #define ALT_GIC_DIST_GICD_CPENDSGIR0_FLD_MSB 31
26540 /* The width in bits of the ALT_GIC_DIST_GICD_CPENDSGIR0_FLD register field. */
26541 #define ALT_GIC_DIST_GICD_CPENDSGIR0_FLD_WIDTH 32
26542 /* The mask used to set the ALT_GIC_DIST_GICD_CPENDSGIR0_FLD register field value. */
26543 #define ALT_GIC_DIST_GICD_CPENDSGIR0_FLD_SET_MSK 0xffffffff
26544 /* The mask used to clear the ALT_GIC_DIST_GICD_CPENDSGIR0_FLD register field value. */
26545 #define ALT_GIC_DIST_GICD_CPENDSGIR0_FLD_CLR_MSK 0x00000000
26546 /* The reset value of the ALT_GIC_DIST_GICD_CPENDSGIR0_FLD register field. */
26547 #define ALT_GIC_DIST_GICD_CPENDSGIR0_FLD_RESET 0x0
26548 /* Extracts the ALT_GIC_DIST_GICD_CPENDSGIR0_FLD field value from a register. */
26549 #define ALT_GIC_DIST_GICD_CPENDSGIR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26550 /* Produces a ALT_GIC_DIST_GICD_CPENDSGIR0_FLD register field value suitable for setting the register. */
26551 #define ALT_GIC_DIST_GICD_CPENDSGIR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
26552 
26553 #ifndef __ASSEMBLY__
26554 /*
26555  * WARNING: The C register and register group struct declarations are provided for
26556  * convenience and illustrative purposes. They should, however, be used with
26557  * caution as the C language standard provides no guarantees about the alignment or
26558  * atomicity of device memory accesses. The recommended practice for coding device
26559  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26560  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26561  * alt_write_dword() functions for 64 bit registers.
26562  *
26563  * The struct declaration for register ALT_GIC_DIST_GICD_CPENDSGIR0.
26564  */
26565 struct ALT_GIC_DIST_GICD_CPENDSGIR0_s
26566 {
26567  volatile uint32_t fld : 32; /* Empty */
26568 };
26569 
26570 /* The typedef declaration for register ALT_GIC_DIST_GICD_CPENDSGIR0. */
26571 typedef struct ALT_GIC_DIST_GICD_CPENDSGIR0_s ALT_GIC_DIST_GICD_CPENDSGIR0_t;
26572 #endif /* __ASSEMBLY__ */
26573 
26574 /* The reset value of the ALT_GIC_DIST_GICD_CPENDSGIR0 register. */
26575 #define ALT_GIC_DIST_GICD_CPENDSGIR0_RESET 0x00000000
26576 /* The byte offset of the ALT_GIC_DIST_GICD_CPENDSGIR0 register from the beginning of the component. */
26577 #define ALT_GIC_DIST_GICD_CPENDSGIR0_OFST 0xf10
26578 
26579 /*
26580  * Register : GICD_CPENDSGIR1
26581  *
26582  * SGI Clear-Pending Registers
26583  *
26584  * Register Layout
26585  *
26586  * Bits | Access | Reset | Description
26587  * :-------|:-------|:------|:------------
26588  * [31:0] | RW | 0x0 | Empty
26589  *
26590  */
26591 /*
26592  * Field : Empty - fld
26593  *
26594  * Placeholder
26595  *
26596  * Field Access Macros:
26597  *
26598  */
26599 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_CPENDSGIR1_FLD register field. */
26600 #define ALT_GIC_DIST_GICD_CPENDSGIR1_FLD_LSB 0
26601 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_CPENDSGIR1_FLD register field. */
26602 #define ALT_GIC_DIST_GICD_CPENDSGIR1_FLD_MSB 31
26603 /* The width in bits of the ALT_GIC_DIST_GICD_CPENDSGIR1_FLD register field. */
26604 #define ALT_GIC_DIST_GICD_CPENDSGIR1_FLD_WIDTH 32
26605 /* The mask used to set the ALT_GIC_DIST_GICD_CPENDSGIR1_FLD register field value. */
26606 #define ALT_GIC_DIST_GICD_CPENDSGIR1_FLD_SET_MSK 0xffffffff
26607 /* The mask used to clear the ALT_GIC_DIST_GICD_CPENDSGIR1_FLD register field value. */
26608 #define ALT_GIC_DIST_GICD_CPENDSGIR1_FLD_CLR_MSK 0x00000000
26609 /* The reset value of the ALT_GIC_DIST_GICD_CPENDSGIR1_FLD register field. */
26610 #define ALT_GIC_DIST_GICD_CPENDSGIR1_FLD_RESET 0x0
26611 /* Extracts the ALT_GIC_DIST_GICD_CPENDSGIR1_FLD field value from a register. */
26612 #define ALT_GIC_DIST_GICD_CPENDSGIR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26613 /* Produces a ALT_GIC_DIST_GICD_CPENDSGIR1_FLD register field value suitable for setting the register. */
26614 #define ALT_GIC_DIST_GICD_CPENDSGIR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
26615 
26616 #ifndef __ASSEMBLY__
26617 /*
26618  * WARNING: The C register and register group struct declarations are provided for
26619  * convenience and illustrative purposes. They should, however, be used with
26620  * caution as the C language standard provides no guarantees about the alignment or
26621  * atomicity of device memory accesses. The recommended practice for coding device
26622  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26623  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26624  * alt_write_dword() functions for 64 bit registers.
26625  *
26626  * The struct declaration for register ALT_GIC_DIST_GICD_CPENDSGIR1.
26627  */
26628 struct ALT_GIC_DIST_GICD_CPENDSGIR1_s
26629 {
26630  volatile uint32_t fld : 32; /* Empty */
26631 };
26632 
26633 /* The typedef declaration for register ALT_GIC_DIST_GICD_CPENDSGIR1. */
26634 typedef struct ALT_GIC_DIST_GICD_CPENDSGIR1_s ALT_GIC_DIST_GICD_CPENDSGIR1_t;
26635 #endif /* __ASSEMBLY__ */
26636 
26637 /* The reset value of the ALT_GIC_DIST_GICD_CPENDSGIR1 register. */
26638 #define ALT_GIC_DIST_GICD_CPENDSGIR1_RESET 0x00000000
26639 /* The byte offset of the ALT_GIC_DIST_GICD_CPENDSGIR1 register from the beginning of the component. */
26640 #define ALT_GIC_DIST_GICD_CPENDSGIR1_OFST 0xf14
26641 
26642 /*
26643  * Register : GICD_CPENDSGIR2
26644  *
26645  * SGI Clear-Pending Registers
26646  *
26647  * Register Layout
26648  *
26649  * Bits | Access | Reset | Description
26650  * :-------|:-------|:------|:------------
26651  * [31:0] | RW | 0x0 | Empty
26652  *
26653  */
26654 /*
26655  * Field : Empty - fld
26656  *
26657  * Placeholder
26658  *
26659  * Field Access Macros:
26660  *
26661  */
26662 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_CPENDSGIR2_FLD register field. */
26663 #define ALT_GIC_DIST_GICD_CPENDSGIR2_FLD_LSB 0
26664 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_CPENDSGIR2_FLD register field. */
26665 #define ALT_GIC_DIST_GICD_CPENDSGIR2_FLD_MSB 31
26666 /* The width in bits of the ALT_GIC_DIST_GICD_CPENDSGIR2_FLD register field. */
26667 #define ALT_GIC_DIST_GICD_CPENDSGIR2_FLD_WIDTH 32
26668 /* The mask used to set the ALT_GIC_DIST_GICD_CPENDSGIR2_FLD register field value. */
26669 #define ALT_GIC_DIST_GICD_CPENDSGIR2_FLD_SET_MSK 0xffffffff
26670 /* The mask used to clear the ALT_GIC_DIST_GICD_CPENDSGIR2_FLD register field value. */
26671 #define ALT_GIC_DIST_GICD_CPENDSGIR2_FLD_CLR_MSK 0x00000000
26672 /* The reset value of the ALT_GIC_DIST_GICD_CPENDSGIR2_FLD register field. */
26673 #define ALT_GIC_DIST_GICD_CPENDSGIR2_FLD_RESET 0x0
26674 /* Extracts the ALT_GIC_DIST_GICD_CPENDSGIR2_FLD field value from a register. */
26675 #define ALT_GIC_DIST_GICD_CPENDSGIR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26676 /* Produces a ALT_GIC_DIST_GICD_CPENDSGIR2_FLD register field value suitable for setting the register. */
26677 #define ALT_GIC_DIST_GICD_CPENDSGIR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
26678 
26679 #ifndef __ASSEMBLY__
26680 /*
26681  * WARNING: The C register and register group struct declarations are provided for
26682  * convenience and illustrative purposes. They should, however, be used with
26683  * caution as the C language standard provides no guarantees about the alignment or
26684  * atomicity of device memory accesses. The recommended practice for coding device
26685  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26686  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26687  * alt_write_dword() functions for 64 bit registers.
26688  *
26689  * The struct declaration for register ALT_GIC_DIST_GICD_CPENDSGIR2.
26690  */
26691 struct ALT_GIC_DIST_GICD_CPENDSGIR2_s
26692 {
26693  volatile uint32_t fld : 32; /* Empty */
26694 };
26695 
26696 /* The typedef declaration for register ALT_GIC_DIST_GICD_CPENDSGIR2. */
26697 typedef struct ALT_GIC_DIST_GICD_CPENDSGIR2_s ALT_GIC_DIST_GICD_CPENDSGIR2_t;
26698 #endif /* __ASSEMBLY__ */
26699 
26700 /* The reset value of the ALT_GIC_DIST_GICD_CPENDSGIR2 register. */
26701 #define ALT_GIC_DIST_GICD_CPENDSGIR2_RESET 0x00000000
26702 /* The byte offset of the ALT_GIC_DIST_GICD_CPENDSGIR2 register from the beginning of the component. */
26703 #define ALT_GIC_DIST_GICD_CPENDSGIR2_OFST 0xf18
26704 
26705 /*
26706  * Register : GICD_CPENDSGIR3
26707  *
26708  * SGI Clear-Pending Registers
26709  *
26710  * Register Layout
26711  *
26712  * Bits | Access | Reset | Description
26713  * :-------|:-------|:------|:------------
26714  * [31:0] | RW | 0x0 | Empty
26715  *
26716  */
26717 /*
26718  * Field : Empty - fld
26719  *
26720  * Placeholder
26721  *
26722  * Field Access Macros:
26723  *
26724  */
26725 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_CPENDSGIR3_FLD register field. */
26726 #define ALT_GIC_DIST_GICD_CPENDSGIR3_FLD_LSB 0
26727 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_CPENDSGIR3_FLD register field. */
26728 #define ALT_GIC_DIST_GICD_CPENDSGIR3_FLD_MSB 31
26729 /* The width in bits of the ALT_GIC_DIST_GICD_CPENDSGIR3_FLD register field. */
26730 #define ALT_GIC_DIST_GICD_CPENDSGIR3_FLD_WIDTH 32
26731 /* The mask used to set the ALT_GIC_DIST_GICD_CPENDSGIR3_FLD register field value. */
26732 #define ALT_GIC_DIST_GICD_CPENDSGIR3_FLD_SET_MSK 0xffffffff
26733 /* The mask used to clear the ALT_GIC_DIST_GICD_CPENDSGIR3_FLD register field value. */
26734 #define ALT_GIC_DIST_GICD_CPENDSGIR3_FLD_CLR_MSK 0x00000000
26735 /* The reset value of the ALT_GIC_DIST_GICD_CPENDSGIR3_FLD register field. */
26736 #define ALT_GIC_DIST_GICD_CPENDSGIR3_FLD_RESET 0x0
26737 /* Extracts the ALT_GIC_DIST_GICD_CPENDSGIR3_FLD field value from a register. */
26738 #define ALT_GIC_DIST_GICD_CPENDSGIR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26739 /* Produces a ALT_GIC_DIST_GICD_CPENDSGIR3_FLD register field value suitable for setting the register. */
26740 #define ALT_GIC_DIST_GICD_CPENDSGIR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
26741 
26742 #ifndef __ASSEMBLY__
26743 /*
26744  * WARNING: The C register and register group struct declarations are provided for
26745  * convenience and illustrative purposes. They should, however, be used with
26746  * caution as the C language standard provides no guarantees about the alignment or
26747  * atomicity of device memory accesses. The recommended practice for coding device
26748  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26749  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26750  * alt_write_dword() functions for 64 bit registers.
26751  *
26752  * The struct declaration for register ALT_GIC_DIST_GICD_CPENDSGIR3.
26753  */
26754 struct ALT_GIC_DIST_GICD_CPENDSGIR3_s
26755 {
26756  volatile uint32_t fld : 32; /* Empty */
26757 };
26758 
26759 /* The typedef declaration for register ALT_GIC_DIST_GICD_CPENDSGIR3. */
26760 typedef struct ALT_GIC_DIST_GICD_CPENDSGIR3_s ALT_GIC_DIST_GICD_CPENDSGIR3_t;
26761 #endif /* __ASSEMBLY__ */
26762 
26763 /* The reset value of the ALT_GIC_DIST_GICD_CPENDSGIR3 register. */
26764 #define ALT_GIC_DIST_GICD_CPENDSGIR3_RESET 0x00000000
26765 /* The byte offset of the ALT_GIC_DIST_GICD_CPENDSGIR3 register from the beginning of the component. */
26766 #define ALT_GIC_DIST_GICD_CPENDSGIR3_OFST 0xf1c
26767 
26768 /*
26769  * Register : GICD_SPENDSGIR0
26770  *
26771  * SGI Set-Pending Registers
26772  *
26773  * Register Layout
26774  *
26775  * Bits | Access | Reset | Description
26776  * :-------|:-------|:------|:------------
26777  * [31:0] | RW | 0x0 | Empty
26778  *
26779  */
26780 /*
26781  * Field : Empty - fld
26782  *
26783  * Placeholder
26784  *
26785  * Field Access Macros:
26786  *
26787  */
26788 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_SPENDSGIR0_FLD register field. */
26789 #define ALT_GIC_DIST_GICD_SPENDSGIR0_FLD_LSB 0
26790 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_SPENDSGIR0_FLD register field. */
26791 #define ALT_GIC_DIST_GICD_SPENDSGIR0_FLD_MSB 31
26792 /* The width in bits of the ALT_GIC_DIST_GICD_SPENDSGIR0_FLD register field. */
26793 #define ALT_GIC_DIST_GICD_SPENDSGIR0_FLD_WIDTH 32
26794 /* The mask used to set the ALT_GIC_DIST_GICD_SPENDSGIR0_FLD register field value. */
26795 #define ALT_GIC_DIST_GICD_SPENDSGIR0_FLD_SET_MSK 0xffffffff
26796 /* The mask used to clear the ALT_GIC_DIST_GICD_SPENDSGIR0_FLD register field value. */
26797 #define ALT_GIC_DIST_GICD_SPENDSGIR0_FLD_CLR_MSK 0x00000000
26798 /* The reset value of the ALT_GIC_DIST_GICD_SPENDSGIR0_FLD register field. */
26799 #define ALT_GIC_DIST_GICD_SPENDSGIR0_FLD_RESET 0x0
26800 /* Extracts the ALT_GIC_DIST_GICD_SPENDSGIR0_FLD field value from a register. */
26801 #define ALT_GIC_DIST_GICD_SPENDSGIR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26802 /* Produces a ALT_GIC_DIST_GICD_SPENDSGIR0_FLD register field value suitable for setting the register. */
26803 #define ALT_GIC_DIST_GICD_SPENDSGIR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
26804 
26805 #ifndef __ASSEMBLY__
26806 /*
26807  * WARNING: The C register and register group struct declarations are provided for
26808  * convenience and illustrative purposes. They should, however, be used with
26809  * caution as the C language standard provides no guarantees about the alignment or
26810  * atomicity of device memory accesses. The recommended practice for coding device
26811  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26812  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26813  * alt_write_dword() functions for 64 bit registers.
26814  *
26815  * The struct declaration for register ALT_GIC_DIST_GICD_SPENDSGIR0.
26816  */
26817 struct ALT_GIC_DIST_GICD_SPENDSGIR0_s
26818 {
26819  volatile uint32_t fld : 32; /* Empty */
26820 };
26821 
26822 /* The typedef declaration for register ALT_GIC_DIST_GICD_SPENDSGIR0. */
26823 typedef struct ALT_GIC_DIST_GICD_SPENDSGIR0_s ALT_GIC_DIST_GICD_SPENDSGIR0_t;
26824 #endif /* __ASSEMBLY__ */
26825 
26826 /* The reset value of the ALT_GIC_DIST_GICD_SPENDSGIR0 register. */
26827 #define ALT_GIC_DIST_GICD_SPENDSGIR0_RESET 0x00000000
26828 /* The byte offset of the ALT_GIC_DIST_GICD_SPENDSGIR0 register from the beginning of the component. */
26829 #define ALT_GIC_DIST_GICD_SPENDSGIR0_OFST 0xf20
26830 
26831 /*
26832  * Register : GICD_SPENDSGIR1
26833  *
26834  * SGI Set-Pending Registers
26835  *
26836  * Register Layout
26837  *
26838  * Bits | Access | Reset | Description
26839  * :-------|:-------|:------|:------------
26840  * [31:0] | RW | 0x0 | Empty
26841  *
26842  */
26843 /*
26844  * Field : Empty - fld
26845  *
26846  * Placeholder
26847  *
26848  * Field Access Macros:
26849  *
26850  */
26851 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_SPENDSGIR1_FLD register field. */
26852 #define ALT_GIC_DIST_GICD_SPENDSGIR1_FLD_LSB 0
26853 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_SPENDSGIR1_FLD register field. */
26854 #define ALT_GIC_DIST_GICD_SPENDSGIR1_FLD_MSB 31
26855 /* The width in bits of the ALT_GIC_DIST_GICD_SPENDSGIR1_FLD register field. */
26856 #define ALT_GIC_DIST_GICD_SPENDSGIR1_FLD_WIDTH 32
26857 /* The mask used to set the ALT_GIC_DIST_GICD_SPENDSGIR1_FLD register field value. */
26858 #define ALT_GIC_DIST_GICD_SPENDSGIR1_FLD_SET_MSK 0xffffffff
26859 /* The mask used to clear the ALT_GIC_DIST_GICD_SPENDSGIR1_FLD register field value. */
26860 #define ALT_GIC_DIST_GICD_SPENDSGIR1_FLD_CLR_MSK 0x00000000
26861 /* The reset value of the ALT_GIC_DIST_GICD_SPENDSGIR1_FLD register field. */
26862 #define ALT_GIC_DIST_GICD_SPENDSGIR1_FLD_RESET 0x0
26863 /* Extracts the ALT_GIC_DIST_GICD_SPENDSGIR1_FLD field value from a register. */
26864 #define ALT_GIC_DIST_GICD_SPENDSGIR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26865 /* Produces a ALT_GIC_DIST_GICD_SPENDSGIR1_FLD register field value suitable for setting the register. */
26866 #define ALT_GIC_DIST_GICD_SPENDSGIR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
26867 
26868 #ifndef __ASSEMBLY__
26869 /*
26870  * WARNING: The C register and register group struct declarations are provided for
26871  * convenience and illustrative purposes. They should, however, be used with
26872  * caution as the C language standard provides no guarantees about the alignment or
26873  * atomicity of device memory accesses. The recommended practice for coding device
26874  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26875  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26876  * alt_write_dword() functions for 64 bit registers.
26877  *
26878  * The struct declaration for register ALT_GIC_DIST_GICD_SPENDSGIR1.
26879  */
26880 struct ALT_GIC_DIST_GICD_SPENDSGIR1_s
26881 {
26882  volatile uint32_t fld : 32; /* Empty */
26883 };
26884 
26885 /* The typedef declaration for register ALT_GIC_DIST_GICD_SPENDSGIR1. */
26886 typedef struct ALT_GIC_DIST_GICD_SPENDSGIR1_s ALT_GIC_DIST_GICD_SPENDSGIR1_t;
26887 #endif /* __ASSEMBLY__ */
26888 
26889 /* The reset value of the ALT_GIC_DIST_GICD_SPENDSGIR1 register. */
26890 #define ALT_GIC_DIST_GICD_SPENDSGIR1_RESET 0x00000000
26891 /* The byte offset of the ALT_GIC_DIST_GICD_SPENDSGIR1 register from the beginning of the component. */
26892 #define ALT_GIC_DIST_GICD_SPENDSGIR1_OFST 0xf24
26893 
26894 /*
26895  * Register : GICD_SPENDSGIR2
26896  *
26897  * SGI Set-Pending Registers
26898  *
26899  * Register Layout
26900  *
26901  * Bits | Access | Reset | Description
26902  * :-------|:-------|:------|:------------
26903  * [31:0] | RW | 0x0 | Empty
26904  *
26905  */
26906 /*
26907  * Field : Empty - fld
26908  *
26909  * Placeholder
26910  *
26911  * Field Access Macros:
26912  *
26913  */
26914 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_SPENDSGIR2_FLD register field. */
26915 #define ALT_GIC_DIST_GICD_SPENDSGIR2_FLD_LSB 0
26916 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_SPENDSGIR2_FLD register field. */
26917 #define ALT_GIC_DIST_GICD_SPENDSGIR2_FLD_MSB 31
26918 /* The width in bits of the ALT_GIC_DIST_GICD_SPENDSGIR2_FLD register field. */
26919 #define ALT_GIC_DIST_GICD_SPENDSGIR2_FLD_WIDTH 32
26920 /* The mask used to set the ALT_GIC_DIST_GICD_SPENDSGIR2_FLD register field value. */
26921 #define ALT_GIC_DIST_GICD_SPENDSGIR2_FLD_SET_MSK 0xffffffff
26922 /* The mask used to clear the ALT_GIC_DIST_GICD_SPENDSGIR2_FLD register field value. */
26923 #define ALT_GIC_DIST_GICD_SPENDSGIR2_FLD_CLR_MSK 0x00000000
26924 /* The reset value of the ALT_GIC_DIST_GICD_SPENDSGIR2_FLD register field. */
26925 #define ALT_GIC_DIST_GICD_SPENDSGIR2_FLD_RESET 0x0
26926 /* Extracts the ALT_GIC_DIST_GICD_SPENDSGIR2_FLD field value from a register. */
26927 #define ALT_GIC_DIST_GICD_SPENDSGIR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26928 /* Produces a ALT_GIC_DIST_GICD_SPENDSGIR2_FLD register field value suitable for setting the register. */
26929 #define ALT_GIC_DIST_GICD_SPENDSGIR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
26930 
26931 #ifndef __ASSEMBLY__
26932 /*
26933  * WARNING: The C register and register group struct declarations are provided for
26934  * convenience and illustrative purposes. They should, however, be used with
26935  * caution as the C language standard provides no guarantees about the alignment or
26936  * atomicity of device memory accesses. The recommended practice for coding device
26937  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
26938  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
26939  * alt_write_dword() functions for 64 bit registers.
26940  *
26941  * The struct declaration for register ALT_GIC_DIST_GICD_SPENDSGIR2.
26942  */
26943 struct ALT_GIC_DIST_GICD_SPENDSGIR2_s
26944 {
26945  volatile uint32_t fld : 32; /* Empty */
26946 };
26947 
26948 /* The typedef declaration for register ALT_GIC_DIST_GICD_SPENDSGIR2. */
26949 typedef struct ALT_GIC_DIST_GICD_SPENDSGIR2_s ALT_GIC_DIST_GICD_SPENDSGIR2_t;
26950 #endif /* __ASSEMBLY__ */
26951 
26952 /* The reset value of the ALT_GIC_DIST_GICD_SPENDSGIR2 register. */
26953 #define ALT_GIC_DIST_GICD_SPENDSGIR2_RESET 0x00000000
26954 /* The byte offset of the ALT_GIC_DIST_GICD_SPENDSGIR2 register from the beginning of the component. */
26955 #define ALT_GIC_DIST_GICD_SPENDSGIR2_OFST 0xf28
26956 
26957 /*
26958  * Register : GICD_SPENDSGIR3
26959  *
26960  * SGI Set-Pending Registers
26961  *
26962  * Register Layout
26963  *
26964  * Bits | Access | Reset | Description
26965  * :-------|:-------|:------|:------------
26966  * [31:0] | RW | 0x0 | Empty
26967  *
26968  */
26969 /*
26970  * Field : Empty - fld
26971  *
26972  * Placeholder
26973  *
26974  * Field Access Macros:
26975  *
26976  */
26977 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_SPENDSGIR3_FLD register field. */
26978 #define ALT_GIC_DIST_GICD_SPENDSGIR3_FLD_LSB 0
26979 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_SPENDSGIR3_FLD register field. */
26980 #define ALT_GIC_DIST_GICD_SPENDSGIR3_FLD_MSB 31
26981 /* The width in bits of the ALT_GIC_DIST_GICD_SPENDSGIR3_FLD register field. */
26982 #define ALT_GIC_DIST_GICD_SPENDSGIR3_FLD_WIDTH 32
26983 /* The mask used to set the ALT_GIC_DIST_GICD_SPENDSGIR3_FLD register field value. */
26984 #define ALT_GIC_DIST_GICD_SPENDSGIR3_FLD_SET_MSK 0xffffffff
26985 /* The mask used to clear the ALT_GIC_DIST_GICD_SPENDSGIR3_FLD register field value. */
26986 #define ALT_GIC_DIST_GICD_SPENDSGIR3_FLD_CLR_MSK 0x00000000
26987 /* The reset value of the ALT_GIC_DIST_GICD_SPENDSGIR3_FLD register field. */
26988 #define ALT_GIC_DIST_GICD_SPENDSGIR3_FLD_RESET 0x0
26989 /* Extracts the ALT_GIC_DIST_GICD_SPENDSGIR3_FLD field value from a register. */
26990 #define ALT_GIC_DIST_GICD_SPENDSGIR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
26991 /* Produces a ALT_GIC_DIST_GICD_SPENDSGIR3_FLD register field value suitable for setting the register. */
26992 #define ALT_GIC_DIST_GICD_SPENDSGIR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
26993 
26994 #ifndef __ASSEMBLY__
26995 /*
26996  * WARNING: The C register and register group struct declarations are provided for
26997  * convenience and illustrative purposes. They should, however, be used with
26998  * caution as the C language standard provides no guarantees about the alignment or
26999  * atomicity of device memory accesses. The recommended practice for coding device
27000  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27001  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27002  * alt_write_dword() functions for 64 bit registers.
27003  *
27004  * The struct declaration for register ALT_GIC_DIST_GICD_SPENDSGIR3.
27005  */
27006 struct ALT_GIC_DIST_GICD_SPENDSGIR3_s
27007 {
27008  volatile uint32_t fld : 32; /* Empty */
27009 };
27010 
27011 /* The typedef declaration for register ALT_GIC_DIST_GICD_SPENDSGIR3. */
27012 typedef struct ALT_GIC_DIST_GICD_SPENDSGIR3_s ALT_GIC_DIST_GICD_SPENDSGIR3_t;
27013 #endif /* __ASSEMBLY__ */
27014 
27015 /* The reset value of the ALT_GIC_DIST_GICD_SPENDSGIR3 register. */
27016 #define ALT_GIC_DIST_GICD_SPENDSGIR3_RESET 0x00000000
27017 /* The byte offset of the ALT_GIC_DIST_GICD_SPENDSGIR3 register from the beginning of the component. */
27018 #define ALT_GIC_DIST_GICD_SPENDSGIR3_OFST 0xf2c
27019 
27020 /*
27021  * Register : GICD_PIDR4
27022  *
27023  * Peripheral ID4 Register
27024  *
27025  * Register Layout
27026  *
27027  * Bits | Access | Reset | Description
27028  * :-------|:-------|:------|:------------
27029  * [31:0] | RW | 0x4 | Empty
27030  *
27031  */
27032 /*
27033  * Field : Empty - fld
27034  *
27035  * Placeholder
27036  *
27037  * Field Access Macros:
27038  *
27039  */
27040 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_PIDR4_FLD register field. */
27041 #define ALT_GIC_DIST_GICD_PIDR4_FLD_LSB 0
27042 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_PIDR4_FLD register field. */
27043 #define ALT_GIC_DIST_GICD_PIDR4_FLD_MSB 31
27044 /* The width in bits of the ALT_GIC_DIST_GICD_PIDR4_FLD register field. */
27045 #define ALT_GIC_DIST_GICD_PIDR4_FLD_WIDTH 32
27046 /* The mask used to set the ALT_GIC_DIST_GICD_PIDR4_FLD register field value. */
27047 #define ALT_GIC_DIST_GICD_PIDR4_FLD_SET_MSK 0xffffffff
27048 /* The mask used to clear the ALT_GIC_DIST_GICD_PIDR4_FLD register field value. */
27049 #define ALT_GIC_DIST_GICD_PIDR4_FLD_CLR_MSK 0x00000000
27050 /* The reset value of the ALT_GIC_DIST_GICD_PIDR4_FLD register field. */
27051 #define ALT_GIC_DIST_GICD_PIDR4_FLD_RESET 0x4
27052 /* Extracts the ALT_GIC_DIST_GICD_PIDR4_FLD field value from a register. */
27053 #define ALT_GIC_DIST_GICD_PIDR4_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27054 /* Produces a ALT_GIC_DIST_GICD_PIDR4_FLD register field value suitable for setting the register. */
27055 #define ALT_GIC_DIST_GICD_PIDR4_FLD_SET(value) (((value) << 0) & 0xffffffff)
27056 
27057 #ifndef __ASSEMBLY__
27058 /*
27059  * WARNING: The C register and register group struct declarations are provided for
27060  * convenience and illustrative purposes. They should, however, be used with
27061  * caution as the C language standard provides no guarantees about the alignment or
27062  * atomicity of device memory accesses. The recommended practice for coding device
27063  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27064  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27065  * alt_write_dword() functions for 64 bit registers.
27066  *
27067  * The struct declaration for register ALT_GIC_DIST_GICD_PIDR4.
27068  */
27069 struct ALT_GIC_DIST_GICD_PIDR4_s
27070 {
27071  volatile uint32_t fld : 32; /* Empty */
27072 };
27073 
27074 /* The typedef declaration for register ALT_GIC_DIST_GICD_PIDR4. */
27075 typedef struct ALT_GIC_DIST_GICD_PIDR4_s ALT_GIC_DIST_GICD_PIDR4_t;
27076 #endif /* __ASSEMBLY__ */
27077 
27078 /* The reset value of the ALT_GIC_DIST_GICD_PIDR4 register. */
27079 #define ALT_GIC_DIST_GICD_PIDR4_RESET 0x00000004
27080 /* The byte offset of the ALT_GIC_DIST_GICD_PIDR4 register from the beginning of the component. */
27081 #define ALT_GIC_DIST_GICD_PIDR4_OFST 0xfd0
27082 
27083 /*
27084  * Register : GICD_PIDR5
27085  *
27086  * Peripheral ID5 Register
27087  *
27088  * Register Layout
27089  *
27090  * Bits | Access | Reset | Description
27091  * :-------|:-------|:------|:------------
27092  * [31:0] | RW | 0x0 | Empty
27093  *
27094  */
27095 /*
27096  * Field : Empty - fld
27097  *
27098  * Placeholder
27099  *
27100  * Field Access Macros:
27101  *
27102  */
27103 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_PIDR5_FLD register field. */
27104 #define ALT_GIC_DIST_GICD_PIDR5_FLD_LSB 0
27105 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_PIDR5_FLD register field. */
27106 #define ALT_GIC_DIST_GICD_PIDR5_FLD_MSB 31
27107 /* The width in bits of the ALT_GIC_DIST_GICD_PIDR5_FLD register field. */
27108 #define ALT_GIC_DIST_GICD_PIDR5_FLD_WIDTH 32
27109 /* The mask used to set the ALT_GIC_DIST_GICD_PIDR5_FLD register field value. */
27110 #define ALT_GIC_DIST_GICD_PIDR5_FLD_SET_MSK 0xffffffff
27111 /* The mask used to clear the ALT_GIC_DIST_GICD_PIDR5_FLD register field value. */
27112 #define ALT_GIC_DIST_GICD_PIDR5_FLD_CLR_MSK 0x00000000
27113 /* The reset value of the ALT_GIC_DIST_GICD_PIDR5_FLD register field. */
27114 #define ALT_GIC_DIST_GICD_PIDR5_FLD_RESET 0x0
27115 /* Extracts the ALT_GIC_DIST_GICD_PIDR5_FLD field value from a register. */
27116 #define ALT_GIC_DIST_GICD_PIDR5_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27117 /* Produces a ALT_GIC_DIST_GICD_PIDR5_FLD register field value suitable for setting the register. */
27118 #define ALT_GIC_DIST_GICD_PIDR5_FLD_SET(value) (((value) << 0) & 0xffffffff)
27119 
27120 #ifndef __ASSEMBLY__
27121 /*
27122  * WARNING: The C register and register group struct declarations are provided for
27123  * convenience and illustrative purposes. They should, however, be used with
27124  * caution as the C language standard provides no guarantees about the alignment or
27125  * atomicity of device memory accesses. The recommended practice for coding device
27126  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27127  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27128  * alt_write_dword() functions for 64 bit registers.
27129  *
27130  * The struct declaration for register ALT_GIC_DIST_GICD_PIDR5.
27131  */
27132 struct ALT_GIC_DIST_GICD_PIDR5_s
27133 {
27134  volatile uint32_t fld : 32; /* Empty */
27135 };
27136 
27137 /* The typedef declaration for register ALT_GIC_DIST_GICD_PIDR5. */
27138 typedef struct ALT_GIC_DIST_GICD_PIDR5_s ALT_GIC_DIST_GICD_PIDR5_t;
27139 #endif /* __ASSEMBLY__ */
27140 
27141 /* The reset value of the ALT_GIC_DIST_GICD_PIDR5 register. */
27142 #define ALT_GIC_DIST_GICD_PIDR5_RESET 0x00000000
27143 /* The byte offset of the ALT_GIC_DIST_GICD_PIDR5 register from the beginning of the component. */
27144 #define ALT_GIC_DIST_GICD_PIDR5_OFST 0xfd4
27145 
27146 /*
27147  * Register : GICD_PIDR6
27148  *
27149  * Peripheral ID6 Register
27150  *
27151  * Register Layout
27152  *
27153  * Bits | Access | Reset | Description
27154  * :-------|:-------|:------|:------------
27155  * [31:0] | RW | 0x0 | Empty
27156  *
27157  */
27158 /*
27159  * Field : Empty - fld
27160  *
27161  * Placeholder
27162  *
27163  * Field Access Macros:
27164  *
27165  */
27166 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_PIDR6_FLD register field. */
27167 #define ALT_GIC_DIST_GICD_PIDR6_FLD_LSB 0
27168 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_PIDR6_FLD register field. */
27169 #define ALT_GIC_DIST_GICD_PIDR6_FLD_MSB 31
27170 /* The width in bits of the ALT_GIC_DIST_GICD_PIDR6_FLD register field. */
27171 #define ALT_GIC_DIST_GICD_PIDR6_FLD_WIDTH 32
27172 /* The mask used to set the ALT_GIC_DIST_GICD_PIDR6_FLD register field value. */
27173 #define ALT_GIC_DIST_GICD_PIDR6_FLD_SET_MSK 0xffffffff
27174 /* The mask used to clear the ALT_GIC_DIST_GICD_PIDR6_FLD register field value. */
27175 #define ALT_GIC_DIST_GICD_PIDR6_FLD_CLR_MSK 0x00000000
27176 /* The reset value of the ALT_GIC_DIST_GICD_PIDR6_FLD register field. */
27177 #define ALT_GIC_DIST_GICD_PIDR6_FLD_RESET 0x0
27178 /* Extracts the ALT_GIC_DIST_GICD_PIDR6_FLD field value from a register. */
27179 #define ALT_GIC_DIST_GICD_PIDR6_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27180 /* Produces a ALT_GIC_DIST_GICD_PIDR6_FLD register field value suitable for setting the register. */
27181 #define ALT_GIC_DIST_GICD_PIDR6_FLD_SET(value) (((value) << 0) & 0xffffffff)
27182 
27183 #ifndef __ASSEMBLY__
27184 /*
27185  * WARNING: The C register and register group struct declarations are provided for
27186  * convenience and illustrative purposes. They should, however, be used with
27187  * caution as the C language standard provides no guarantees about the alignment or
27188  * atomicity of device memory accesses. The recommended practice for coding device
27189  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27190  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27191  * alt_write_dword() functions for 64 bit registers.
27192  *
27193  * The struct declaration for register ALT_GIC_DIST_GICD_PIDR6.
27194  */
27195 struct ALT_GIC_DIST_GICD_PIDR6_s
27196 {
27197  volatile uint32_t fld : 32; /* Empty */
27198 };
27199 
27200 /* The typedef declaration for register ALT_GIC_DIST_GICD_PIDR6. */
27201 typedef struct ALT_GIC_DIST_GICD_PIDR6_s ALT_GIC_DIST_GICD_PIDR6_t;
27202 #endif /* __ASSEMBLY__ */
27203 
27204 /* The reset value of the ALT_GIC_DIST_GICD_PIDR6 register. */
27205 #define ALT_GIC_DIST_GICD_PIDR6_RESET 0x00000000
27206 /* The byte offset of the ALT_GIC_DIST_GICD_PIDR6 register from the beginning of the component. */
27207 #define ALT_GIC_DIST_GICD_PIDR6_OFST 0xfd8
27208 
27209 /*
27210  * Register : GICD_PIDR7
27211  *
27212  * Peripheral ID7 Register
27213  *
27214  * Register Layout
27215  *
27216  * Bits | Access | Reset | Description
27217  * :-------|:-------|:------|:------------
27218  * [31:0] | RW | 0x0 | Empty
27219  *
27220  */
27221 /*
27222  * Field : Empty - fld
27223  *
27224  * Placeholder
27225  *
27226  * Field Access Macros:
27227  *
27228  */
27229 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_PIDR7_FLD register field. */
27230 #define ALT_GIC_DIST_GICD_PIDR7_FLD_LSB 0
27231 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_PIDR7_FLD register field. */
27232 #define ALT_GIC_DIST_GICD_PIDR7_FLD_MSB 31
27233 /* The width in bits of the ALT_GIC_DIST_GICD_PIDR7_FLD register field. */
27234 #define ALT_GIC_DIST_GICD_PIDR7_FLD_WIDTH 32
27235 /* The mask used to set the ALT_GIC_DIST_GICD_PIDR7_FLD register field value. */
27236 #define ALT_GIC_DIST_GICD_PIDR7_FLD_SET_MSK 0xffffffff
27237 /* The mask used to clear the ALT_GIC_DIST_GICD_PIDR7_FLD register field value. */
27238 #define ALT_GIC_DIST_GICD_PIDR7_FLD_CLR_MSK 0x00000000
27239 /* The reset value of the ALT_GIC_DIST_GICD_PIDR7_FLD register field. */
27240 #define ALT_GIC_DIST_GICD_PIDR7_FLD_RESET 0x0
27241 /* Extracts the ALT_GIC_DIST_GICD_PIDR7_FLD field value from a register. */
27242 #define ALT_GIC_DIST_GICD_PIDR7_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27243 /* Produces a ALT_GIC_DIST_GICD_PIDR7_FLD register field value suitable for setting the register. */
27244 #define ALT_GIC_DIST_GICD_PIDR7_FLD_SET(value) (((value) << 0) & 0xffffffff)
27245 
27246 #ifndef __ASSEMBLY__
27247 /*
27248  * WARNING: The C register and register group struct declarations are provided for
27249  * convenience and illustrative purposes. They should, however, be used with
27250  * caution as the C language standard provides no guarantees about the alignment or
27251  * atomicity of device memory accesses. The recommended practice for coding device
27252  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27253  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27254  * alt_write_dword() functions for 64 bit registers.
27255  *
27256  * The struct declaration for register ALT_GIC_DIST_GICD_PIDR7.
27257  */
27258 struct ALT_GIC_DIST_GICD_PIDR7_s
27259 {
27260  volatile uint32_t fld : 32; /* Empty */
27261 };
27262 
27263 /* The typedef declaration for register ALT_GIC_DIST_GICD_PIDR7. */
27264 typedef struct ALT_GIC_DIST_GICD_PIDR7_s ALT_GIC_DIST_GICD_PIDR7_t;
27265 #endif /* __ASSEMBLY__ */
27266 
27267 /* The reset value of the ALT_GIC_DIST_GICD_PIDR7 register. */
27268 #define ALT_GIC_DIST_GICD_PIDR7_RESET 0x00000000
27269 /* The byte offset of the ALT_GIC_DIST_GICD_PIDR7 register from the beginning of the component. */
27270 #define ALT_GIC_DIST_GICD_PIDR7_OFST 0xfdc
27271 
27272 /*
27273  * Register : GICD_PIDR0
27274  *
27275  * Peripheral ID0 Register
27276  *
27277  * Register Layout
27278  *
27279  * Bits | Access | Reset | Description
27280  * :-------|:-------|:------|:------------
27281  * [31:0] | RW | 0x90 | Empty
27282  *
27283  */
27284 /*
27285  * Field : Empty - fld
27286  *
27287  * Placeholder
27288  *
27289  * Field Access Macros:
27290  *
27291  */
27292 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_PIDR0_FLD register field. */
27293 #define ALT_GIC_DIST_GICD_PIDR0_FLD_LSB 0
27294 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_PIDR0_FLD register field. */
27295 #define ALT_GIC_DIST_GICD_PIDR0_FLD_MSB 31
27296 /* The width in bits of the ALT_GIC_DIST_GICD_PIDR0_FLD register field. */
27297 #define ALT_GIC_DIST_GICD_PIDR0_FLD_WIDTH 32
27298 /* The mask used to set the ALT_GIC_DIST_GICD_PIDR0_FLD register field value. */
27299 #define ALT_GIC_DIST_GICD_PIDR0_FLD_SET_MSK 0xffffffff
27300 /* The mask used to clear the ALT_GIC_DIST_GICD_PIDR0_FLD register field value. */
27301 #define ALT_GIC_DIST_GICD_PIDR0_FLD_CLR_MSK 0x00000000
27302 /* The reset value of the ALT_GIC_DIST_GICD_PIDR0_FLD register field. */
27303 #define ALT_GIC_DIST_GICD_PIDR0_FLD_RESET 0x90
27304 /* Extracts the ALT_GIC_DIST_GICD_PIDR0_FLD field value from a register. */
27305 #define ALT_GIC_DIST_GICD_PIDR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27306 /* Produces a ALT_GIC_DIST_GICD_PIDR0_FLD register field value suitable for setting the register. */
27307 #define ALT_GIC_DIST_GICD_PIDR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
27308 
27309 #ifndef __ASSEMBLY__
27310 /*
27311  * WARNING: The C register and register group struct declarations are provided for
27312  * convenience and illustrative purposes. They should, however, be used with
27313  * caution as the C language standard provides no guarantees about the alignment or
27314  * atomicity of device memory accesses. The recommended practice for coding device
27315  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27316  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27317  * alt_write_dword() functions for 64 bit registers.
27318  *
27319  * The struct declaration for register ALT_GIC_DIST_GICD_PIDR0.
27320  */
27321 struct ALT_GIC_DIST_GICD_PIDR0_s
27322 {
27323  volatile uint32_t fld : 32; /* Empty */
27324 };
27325 
27326 /* The typedef declaration for register ALT_GIC_DIST_GICD_PIDR0. */
27327 typedef struct ALT_GIC_DIST_GICD_PIDR0_s ALT_GIC_DIST_GICD_PIDR0_t;
27328 #endif /* __ASSEMBLY__ */
27329 
27330 /* The reset value of the ALT_GIC_DIST_GICD_PIDR0 register. */
27331 #define ALT_GIC_DIST_GICD_PIDR0_RESET 0x00000090
27332 /* The byte offset of the ALT_GIC_DIST_GICD_PIDR0 register from the beginning of the component. */
27333 #define ALT_GIC_DIST_GICD_PIDR0_OFST 0xfe0
27334 
27335 /*
27336  * Register : GICD_PIDR1
27337  *
27338  * Peripheral ID1 Register
27339  *
27340  * Register Layout
27341  *
27342  * Bits | Access | Reset | Description
27343  * :-------|:-------|:------|:------------
27344  * [31:0] | RW | 0xb4 | Empty
27345  *
27346  */
27347 /*
27348  * Field : Empty - fld
27349  *
27350  * Placeholder
27351  *
27352  * Field Access Macros:
27353  *
27354  */
27355 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_PIDR1_FLD register field. */
27356 #define ALT_GIC_DIST_GICD_PIDR1_FLD_LSB 0
27357 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_PIDR1_FLD register field. */
27358 #define ALT_GIC_DIST_GICD_PIDR1_FLD_MSB 31
27359 /* The width in bits of the ALT_GIC_DIST_GICD_PIDR1_FLD register field. */
27360 #define ALT_GIC_DIST_GICD_PIDR1_FLD_WIDTH 32
27361 /* The mask used to set the ALT_GIC_DIST_GICD_PIDR1_FLD register field value. */
27362 #define ALT_GIC_DIST_GICD_PIDR1_FLD_SET_MSK 0xffffffff
27363 /* The mask used to clear the ALT_GIC_DIST_GICD_PIDR1_FLD register field value. */
27364 #define ALT_GIC_DIST_GICD_PIDR1_FLD_CLR_MSK 0x00000000
27365 /* The reset value of the ALT_GIC_DIST_GICD_PIDR1_FLD register field. */
27366 #define ALT_GIC_DIST_GICD_PIDR1_FLD_RESET 0xb4
27367 /* Extracts the ALT_GIC_DIST_GICD_PIDR1_FLD field value from a register. */
27368 #define ALT_GIC_DIST_GICD_PIDR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27369 /* Produces a ALT_GIC_DIST_GICD_PIDR1_FLD register field value suitable for setting the register. */
27370 #define ALT_GIC_DIST_GICD_PIDR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
27371 
27372 #ifndef __ASSEMBLY__
27373 /*
27374  * WARNING: The C register and register group struct declarations are provided for
27375  * convenience and illustrative purposes. They should, however, be used with
27376  * caution as the C language standard provides no guarantees about the alignment or
27377  * atomicity of device memory accesses. The recommended practice for coding device
27378  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27379  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27380  * alt_write_dword() functions for 64 bit registers.
27381  *
27382  * The struct declaration for register ALT_GIC_DIST_GICD_PIDR1.
27383  */
27384 struct ALT_GIC_DIST_GICD_PIDR1_s
27385 {
27386  volatile uint32_t fld : 32; /* Empty */
27387 };
27388 
27389 /* The typedef declaration for register ALT_GIC_DIST_GICD_PIDR1. */
27390 typedef struct ALT_GIC_DIST_GICD_PIDR1_s ALT_GIC_DIST_GICD_PIDR1_t;
27391 #endif /* __ASSEMBLY__ */
27392 
27393 /* The reset value of the ALT_GIC_DIST_GICD_PIDR1 register. */
27394 #define ALT_GIC_DIST_GICD_PIDR1_RESET 0x000000b4
27395 /* The byte offset of the ALT_GIC_DIST_GICD_PIDR1 register from the beginning of the component. */
27396 #define ALT_GIC_DIST_GICD_PIDR1_OFST 0xfe4
27397 
27398 /*
27399  * Register : GICD_PIDR2
27400  *
27401  * Peripheral ID2 Register
27402  *
27403  * Register Layout
27404  *
27405  * Bits | Access | Reset | Description
27406  * :-------|:-------|:------|:------------
27407  * [31:0] | RW | 0x2b | Empty
27408  *
27409  */
27410 /*
27411  * Field : Empty - fld
27412  *
27413  * Placeholder
27414  *
27415  * Field Access Macros:
27416  *
27417  */
27418 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_PIDR2_FLD register field. */
27419 #define ALT_GIC_DIST_GICD_PIDR2_FLD_LSB 0
27420 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_PIDR2_FLD register field. */
27421 #define ALT_GIC_DIST_GICD_PIDR2_FLD_MSB 31
27422 /* The width in bits of the ALT_GIC_DIST_GICD_PIDR2_FLD register field. */
27423 #define ALT_GIC_DIST_GICD_PIDR2_FLD_WIDTH 32
27424 /* The mask used to set the ALT_GIC_DIST_GICD_PIDR2_FLD register field value. */
27425 #define ALT_GIC_DIST_GICD_PIDR2_FLD_SET_MSK 0xffffffff
27426 /* The mask used to clear the ALT_GIC_DIST_GICD_PIDR2_FLD register field value. */
27427 #define ALT_GIC_DIST_GICD_PIDR2_FLD_CLR_MSK 0x00000000
27428 /* The reset value of the ALT_GIC_DIST_GICD_PIDR2_FLD register field. */
27429 #define ALT_GIC_DIST_GICD_PIDR2_FLD_RESET 0x2b
27430 /* Extracts the ALT_GIC_DIST_GICD_PIDR2_FLD field value from a register. */
27431 #define ALT_GIC_DIST_GICD_PIDR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27432 /* Produces a ALT_GIC_DIST_GICD_PIDR2_FLD register field value suitable for setting the register. */
27433 #define ALT_GIC_DIST_GICD_PIDR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
27434 
27435 #ifndef __ASSEMBLY__
27436 /*
27437  * WARNING: The C register and register group struct declarations are provided for
27438  * convenience and illustrative purposes. They should, however, be used with
27439  * caution as the C language standard provides no guarantees about the alignment or
27440  * atomicity of device memory accesses. The recommended practice for coding device
27441  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27442  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27443  * alt_write_dword() functions for 64 bit registers.
27444  *
27445  * The struct declaration for register ALT_GIC_DIST_GICD_PIDR2.
27446  */
27447 struct ALT_GIC_DIST_GICD_PIDR2_s
27448 {
27449  volatile uint32_t fld : 32; /* Empty */
27450 };
27451 
27452 /* The typedef declaration for register ALT_GIC_DIST_GICD_PIDR2. */
27453 typedef struct ALT_GIC_DIST_GICD_PIDR2_s ALT_GIC_DIST_GICD_PIDR2_t;
27454 #endif /* __ASSEMBLY__ */
27455 
27456 /* The reset value of the ALT_GIC_DIST_GICD_PIDR2 register. */
27457 #define ALT_GIC_DIST_GICD_PIDR2_RESET 0x0000002b
27458 /* The byte offset of the ALT_GIC_DIST_GICD_PIDR2 register from the beginning of the component. */
27459 #define ALT_GIC_DIST_GICD_PIDR2_OFST 0xfe8
27460 
27461 /*
27462  * Register : GICD_PIDR3
27463  *
27464  * Peripheral ID3 Register
27465  *
27466  * Register Layout
27467  *
27468  * Bits | Access | Reset | Description
27469  * :-------|:-------|:------|:------------
27470  * [31:0] | RW | 0x0 | Empty
27471  *
27472  */
27473 /*
27474  * Field : Empty - fld
27475  *
27476  * Placeholder
27477  *
27478  * Field Access Macros:
27479  *
27480  */
27481 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_PIDR3_FLD register field. */
27482 #define ALT_GIC_DIST_GICD_PIDR3_FLD_LSB 0
27483 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_PIDR3_FLD register field. */
27484 #define ALT_GIC_DIST_GICD_PIDR3_FLD_MSB 31
27485 /* The width in bits of the ALT_GIC_DIST_GICD_PIDR3_FLD register field. */
27486 #define ALT_GIC_DIST_GICD_PIDR3_FLD_WIDTH 32
27487 /* The mask used to set the ALT_GIC_DIST_GICD_PIDR3_FLD register field value. */
27488 #define ALT_GIC_DIST_GICD_PIDR3_FLD_SET_MSK 0xffffffff
27489 /* The mask used to clear the ALT_GIC_DIST_GICD_PIDR3_FLD register field value. */
27490 #define ALT_GIC_DIST_GICD_PIDR3_FLD_CLR_MSK 0x00000000
27491 /* The reset value of the ALT_GIC_DIST_GICD_PIDR3_FLD register field. */
27492 #define ALT_GIC_DIST_GICD_PIDR3_FLD_RESET 0x0
27493 /* Extracts the ALT_GIC_DIST_GICD_PIDR3_FLD field value from a register. */
27494 #define ALT_GIC_DIST_GICD_PIDR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27495 /* Produces a ALT_GIC_DIST_GICD_PIDR3_FLD register field value suitable for setting the register. */
27496 #define ALT_GIC_DIST_GICD_PIDR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
27497 
27498 #ifndef __ASSEMBLY__
27499 /*
27500  * WARNING: The C register and register group struct declarations are provided for
27501  * convenience and illustrative purposes. They should, however, be used with
27502  * caution as the C language standard provides no guarantees about the alignment or
27503  * atomicity of device memory accesses. The recommended practice for coding device
27504  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27505  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27506  * alt_write_dword() functions for 64 bit registers.
27507  *
27508  * The struct declaration for register ALT_GIC_DIST_GICD_PIDR3.
27509  */
27510 struct ALT_GIC_DIST_GICD_PIDR3_s
27511 {
27512  volatile uint32_t fld : 32; /* Empty */
27513 };
27514 
27515 /* The typedef declaration for register ALT_GIC_DIST_GICD_PIDR3. */
27516 typedef struct ALT_GIC_DIST_GICD_PIDR3_s ALT_GIC_DIST_GICD_PIDR3_t;
27517 #endif /* __ASSEMBLY__ */
27518 
27519 /* The reset value of the ALT_GIC_DIST_GICD_PIDR3 register. */
27520 #define ALT_GIC_DIST_GICD_PIDR3_RESET 0x00000000
27521 /* The byte offset of the ALT_GIC_DIST_GICD_PIDR3 register from the beginning of the component. */
27522 #define ALT_GIC_DIST_GICD_PIDR3_OFST 0xfec
27523 
27524 /*
27525  * Register : GICD_CIDR0
27526  *
27527  * Component ID0 Register
27528  *
27529  * Register Layout
27530  *
27531  * Bits | Access | Reset | Description
27532  * :-------|:-------|:------|:------------
27533  * [31:0] | RW | 0xd | Empty
27534  *
27535  */
27536 /*
27537  * Field : Empty - fld
27538  *
27539  * Placeholder
27540  *
27541  * Field Access Macros:
27542  *
27543  */
27544 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_CIDR0_FLD register field. */
27545 #define ALT_GIC_DIST_GICD_CIDR0_FLD_LSB 0
27546 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_CIDR0_FLD register field. */
27547 #define ALT_GIC_DIST_GICD_CIDR0_FLD_MSB 31
27548 /* The width in bits of the ALT_GIC_DIST_GICD_CIDR0_FLD register field. */
27549 #define ALT_GIC_DIST_GICD_CIDR0_FLD_WIDTH 32
27550 /* The mask used to set the ALT_GIC_DIST_GICD_CIDR0_FLD register field value. */
27551 #define ALT_GIC_DIST_GICD_CIDR0_FLD_SET_MSK 0xffffffff
27552 /* The mask used to clear the ALT_GIC_DIST_GICD_CIDR0_FLD register field value. */
27553 #define ALT_GIC_DIST_GICD_CIDR0_FLD_CLR_MSK 0x00000000
27554 /* The reset value of the ALT_GIC_DIST_GICD_CIDR0_FLD register field. */
27555 #define ALT_GIC_DIST_GICD_CIDR0_FLD_RESET 0xd
27556 /* Extracts the ALT_GIC_DIST_GICD_CIDR0_FLD field value from a register. */
27557 #define ALT_GIC_DIST_GICD_CIDR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27558 /* Produces a ALT_GIC_DIST_GICD_CIDR0_FLD register field value suitable for setting the register. */
27559 #define ALT_GIC_DIST_GICD_CIDR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
27560 
27561 #ifndef __ASSEMBLY__
27562 /*
27563  * WARNING: The C register and register group struct declarations are provided for
27564  * convenience and illustrative purposes. They should, however, be used with
27565  * caution as the C language standard provides no guarantees about the alignment or
27566  * atomicity of device memory accesses. The recommended practice for coding device
27567  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27568  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27569  * alt_write_dword() functions for 64 bit registers.
27570  *
27571  * The struct declaration for register ALT_GIC_DIST_GICD_CIDR0.
27572  */
27573 struct ALT_GIC_DIST_GICD_CIDR0_s
27574 {
27575  volatile uint32_t fld : 32; /* Empty */
27576 };
27577 
27578 /* The typedef declaration for register ALT_GIC_DIST_GICD_CIDR0. */
27579 typedef struct ALT_GIC_DIST_GICD_CIDR0_s ALT_GIC_DIST_GICD_CIDR0_t;
27580 #endif /* __ASSEMBLY__ */
27581 
27582 /* The reset value of the ALT_GIC_DIST_GICD_CIDR0 register. */
27583 #define ALT_GIC_DIST_GICD_CIDR0_RESET 0x0000000d
27584 /* The byte offset of the ALT_GIC_DIST_GICD_CIDR0 register from the beginning of the component. */
27585 #define ALT_GIC_DIST_GICD_CIDR0_OFST 0xff0
27586 
27587 /*
27588  * Register : GICD_CIDR1
27589  *
27590  * Component ID1 Register
27591  *
27592  * Register Layout
27593  *
27594  * Bits | Access | Reset | Description
27595  * :-------|:-------|:------|:------------
27596  * [31:0] | RW | 0xf0 | Empty
27597  *
27598  */
27599 /*
27600  * Field : Empty - fld
27601  *
27602  * Placeholder
27603  *
27604  * Field Access Macros:
27605  *
27606  */
27607 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_CIDR1_FLD register field. */
27608 #define ALT_GIC_DIST_GICD_CIDR1_FLD_LSB 0
27609 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_CIDR1_FLD register field. */
27610 #define ALT_GIC_DIST_GICD_CIDR1_FLD_MSB 31
27611 /* The width in bits of the ALT_GIC_DIST_GICD_CIDR1_FLD register field. */
27612 #define ALT_GIC_DIST_GICD_CIDR1_FLD_WIDTH 32
27613 /* The mask used to set the ALT_GIC_DIST_GICD_CIDR1_FLD register field value. */
27614 #define ALT_GIC_DIST_GICD_CIDR1_FLD_SET_MSK 0xffffffff
27615 /* The mask used to clear the ALT_GIC_DIST_GICD_CIDR1_FLD register field value. */
27616 #define ALT_GIC_DIST_GICD_CIDR1_FLD_CLR_MSK 0x00000000
27617 /* The reset value of the ALT_GIC_DIST_GICD_CIDR1_FLD register field. */
27618 #define ALT_GIC_DIST_GICD_CIDR1_FLD_RESET 0xf0
27619 /* Extracts the ALT_GIC_DIST_GICD_CIDR1_FLD field value from a register. */
27620 #define ALT_GIC_DIST_GICD_CIDR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27621 /* Produces a ALT_GIC_DIST_GICD_CIDR1_FLD register field value suitable for setting the register. */
27622 #define ALT_GIC_DIST_GICD_CIDR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
27623 
27624 #ifndef __ASSEMBLY__
27625 /*
27626  * WARNING: The C register and register group struct declarations are provided for
27627  * convenience and illustrative purposes. They should, however, be used with
27628  * caution as the C language standard provides no guarantees about the alignment or
27629  * atomicity of device memory accesses. The recommended practice for coding device
27630  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27631  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27632  * alt_write_dword() functions for 64 bit registers.
27633  *
27634  * The struct declaration for register ALT_GIC_DIST_GICD_CIDR1.
27635  */
27636 struct ALT_GIC_DIST_GICD_CIDR1_s
27637 {
27638  volatile uint32_t fld : 32; /* Empty */
27639 };
27640 
27641 /* The typedef declaration for register ALT_GIC_DIST_GICD_CIDR1. */
27642 typedef struct ALT_GIC_DIST_GICD_CIDR1_s ALT_GIC_DIST_GICD_CIDR1_t;
27643 #endif /* __ASSEMBLY__ */
27644 
27645 /* The reset value of the ALT_GIC_DIST_GICD_CIDR1 register. */
27646 #define ALT_GIC_DIST_GICD_CIDR1_RESET 0x000000f0
27647 /* The byte offset of the ALT_GIC_DIST_GICD_CIDR1 register from the beginning of the component. */
27648 #define ALT_GIC_DIST_GICD_CIDR1_OFST 0xff4
27649 
27650 /*
27651  * Register : GICD_CIDR2
27652  *
27653  * Component ID2 Register
27654  *
27655  * Register Layout
27656  *
27657  * Bits | Access | Reset | Description
27658  * :-------|:-------|:------|:------------
27659  * [31:0] | RW | 0x5 | Empty
27660  *
27661  */
27662 /*
27663  * Field : Empty - fld
27664  *
27665  * Placeholder
27666  *
27667  * Field Access Macros:
27668  *
27669  */
27670 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_CIDR2_FLD register field. */
27671 #define ALT_GIC_DIST_GICD_CIDR2_FLD_LSB 0
27672 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_CIDR2_FLD register field. */
27673 #define ALT_GIC_DIST_GICD_CIDR2_FLD_MSB 31
27674 /* The width in bits of the ALT_GIC_DIST_GICD_CIDR2_FLD register field. */
27675 #define ALT_GIC_DIST_GICD_CIDR2_FLD_WIDTH 32
27676 /* The mask used to set the ALT_GIC_DIST_GICD_CIDR2_FLD register field value. */
27677 #define ALT_GIC_DIST_GICD_CIDR2_FLD_SET_MSK 0xffffffff
27678 /* The mask used to clear the ALT_GIC_DIST_GICD_CIDR2_FLD register field value. */
27679 #define ALT_GIC_DIST_GICD_CIDR2_FLD_CLR_MSK 0x00000000
27680 /* The reset value of the ALT_GIC_DIST_GICD_CIDR2_FLD register field. */
27681 #define ALT_GIC_DIST_GICD_CIDR2_FLD_RESET 0x5
27682 /* Extracts the ALT_GIC_DIST_GICD_CIDR2_FLD field value from a register. */
27683 #define ALT_GIC_DIST_GICD_CIDR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27684 /* Produces a ALT_GIC_DIST_GICD_CIDR2_FLD register field value suitable for setting the register. */
27685 #define ALT_GIC_DIST_GICD_CIDR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
27686 
27687 #ifndef __ASSEMBLY__
27688 /*
27689  * WARNING: The C register and register group struct declarations are provided for
27690  * convenience and illustrative purposes. They should, however, be used with
27691  * caution as the C language standard provides no guarantees about the alignment or
27692  * atomicity of device memory accesses. The recommended practice for coding device
27693  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27694  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27695  * alt_write_dword() functions for 64 bit registers.
27696  *
27697  * The struct declaration for register ALT_GIC_DIST_GICD_CIDR2.
27698  */
27699 struct ALT_GIC_DIST_GICD_CIDR2_s
27700 {
27701  volatile uint32_t fld : 32; /* Empty */
27702 };
27703 
27704 /* The typedef declaration for register ALT_GIC_DIST_GICD_CIDR2. */
27705 typedef struct ALT_GIC_DIST_GICD_CIDR2_s ALT_GIC_DIST_GICD_CIDR2_t;
27706 #endif /* __ASSEMBLY__ */
27707 
27708 /* The reset value of the ALT_GIC_DIST_GICD_CIDR2 register. */
27709 #define ALT_GIC_DIST_GICD_CIDR2_RESET 0x00000005
27710 /* The byte offset of the ALT_GIC_DIST_GICD_CIDR2 register from the beginning of the component. */
27711 #define ALT_GIC_DIST_GICD_CIDR2_OFST 0xff8
27712 
27713 /*
27714  * Register : GICD_CIDR3
27715  *
27716  * Component ID3 Register
27717  *
27718  * Register Layout
27719  *
27720  * Bits | Access | Reset | Description
27721  * :-------|:-------|:------|:------------
27722  * [31:0] | RW | 0xb1 | Empty
27723  *
27724  */
27725 /*
27726  * Field : Empty - fld
27727  *
27728  * Placeholder
27729  *
27730  * Field Access Macros:
27731  *
27732  */
27733 /* The Least Significant Bit (LSB) position of the ALT_GIC_DIST_GICD_CIDR3_FLD register field. */
27734 #define ALT_GIC_DIST_GICD_CIDR3_FLD_LSB 0
27735 /* The Most Significant Bit (MSB) position of the ALT_GIC_DIST_GICD_CIDR3_FLD register field. */
27736 #define ALT_GIC_DIST_GICD_CIDR3_FLD_MSB 31
27737 /* The width in bits of the ALT_GIC_DIST_GICD_CIDR3_FLD register field. */
27738 #define ALT_GIC_DIST_GICD_CIDR3_FLD_WIDTH 32
27739 /* The mask used to set the ALT_GIC_DIST_GICD_CIDR3_FLD register field value. */
27740 #define ALT_GIC_DIST_GICD_CIDR3_FLD_SET_MSK 0xffffffff
27741 /* The mask used to clear the ALT_GIC_DIST_GICD_CIDR3_FLD register field value. */
27742 #define ALT_GIC_DIST_GICD_CIDR3_FLD_CLR_MSK 0x00000000
27743 /* The reset value of the ALT_GIC_DIST_GICD_CIDR3_FLD register field. */
27744 #define ALT_GIC_DIST_GICD_CIDR3_FLD_RESET 0xb1
27745 /* Extracts the ALT_GIC_DIST_GICD_CIDR3_FLD field value from a register. */
27746 #define ALT_GIC_DIST_GICD_CIDR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
27747 /* Produces a ALT_GIC_DIST_GICD_CIDR3_FLD register field value suitable for setting the register. */
27748 #define ALT_GIC_DIST_GICD_CIDR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
27749 
27750 #ifndef __ASSEMBLY__
27751 /*
27752  * WARNING: The C register and register group struct declarations are provided for
27753  * convenience and illustrative purposes. They should, however, be used with
27754  * caution as the C language standard provides no guarantees about the alignment or
27755  * atomicity of device memory accesses. The recommended practice for coding device
27756  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27757  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27758  * alt_write_dword() functions for 64 bit registers.
27759  *
27760  * The struct declaration for register ALT_GIC_DIST_GICD_CIDR3.
27761  */
27762 struct ALT_GIC_DIST_GICD_CIDR3_s
27763 {
27764  volatile uint32_t fld : 32; /* Empty */
27765 };
27766 
27767 /* The typedef declaration for register ALT_GIC_DIST_GICD_CIDR3. */
27768 typedef struct ALT_GIC_DIST_GICD_CIDR3_s ALT_GIC_DIST_GICD_CIDR3_t;
27769 #endif /* __ASSEMBLY__ */
27770 
27771 /* The reset value of the ALT_GIC_DIST_GICD_CIDR3 register. */
27772 #define ALT_GIC_DIST_GICD_CIDR3_RESET 0x000000b1
27773 /* The byte offset of the ALT_GIC_DIST_GICD_CIDR3 register from the beginning of the component. */
27774 #define ALT_GIC_DIST_GICD_CIDR3_OFST 0xffc
27775 
27776 #ifndef __ASSEMBLY__
27777 /*
27778  * WARNING: The C register and register group struct declarations are provided for
27779  * convenience and illustrative purposes. They should, however, be used with
27780  * caution as the C language standard provides no guarantees about the alignment or
27781  * atomicity of device memory accesses. The recommended practice for coding device
27782  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
27783  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
27784  * alt_write_dword() functions for 64 bit registers.
27785  *
27786  * The struct declaration for register group ALT_GIC_DIST.
27787  */
27788 struct ALT_GIC_DIST_s
27789 {
27790  volatile ALT_GIC_DIST_GICD_CTLR_t GICD_CTLR; /* ALT_GIC_DIST_GICD_CTLR */
27791  volatile ALT_GIC_DIST_GICD_TYPER_t GICD_TYPER; /* ALT_GIC_DIST_GICD_TYPER */
27792  volatile ALT_GIC_DIST_GICD_IIDR_t GICD_IIDR; /* ALT_GIC_DIST_GICD_IIDR */
27793  volatile uint32_t _pad_0xc_0x7f[29]; /* *UNDEFINED* */
27794  volatile ALT_GIC_DIST_GICD_IGROUPR0_t GICD_IGROUPR0; /* ALT_GIC_DIST_GICD_IGROUPR0 */
27795  volatile ALT_GIC_DIST_GICD_IGROUPR1_t GICD_IGROUPR1; /* ALT_GIC_DIST_GICD_IGROUPR1 */
27796  volatile ALT_GIC_DIST_GICD_IGROUPR2_t GICD_IGROUPR2; /* ALT_GIC_DIST_GICD_IGROUPR2 */
27797  volatile ALT_GIC_DIST_GICD_IGROUPR3_t GICD_IGROUPR3; /* ALT_GIC_DIST_GICD_IGROUPR3 */
27798  volatile ALT_GIC_DIST_GICD_IGROUPR4_t GICD_IGROUPR4; /* ALT_GIC_DIST_GICD_IGROUPR4 */
27799  volatile ALT_GIC_DIST_GICD_IGROUPR5_t GICD_IGROUPR5; /* ALT_GIC_DIST_GICD_IGROUPR5 */
27800  volatile ALT_GIC_DIST_GICD_IGROUPR6_t GICD_IGROUPR6; /* ALT_GIC_DIST_GICD_IGROUPR6 */
27801  volatile ALT_GIC_DIST_GICD_IGROUPR7_t GICD_IGROUPR7; /* ALT_GIC_DIST_GICD_IGROUPR7 */
27802  volatile ALT_GIC_DIST_GICD_IGROUPR8_t GICD_IGROUPR8; /* ALT_GIC_DIST_GICD_IGROUPR8 */
27803  volatile ALT_GIC_DIST_GICD_IGROUPR9_t GICD_IGROUPR9; /* ALT_GIC_DIST_GICD_IGROUPR9 */
27804  volatile ALT_GIC_DIST_GICD_IGROUPR10_t GICD_IGROUPR10; /* ALT_GIC_DIST_GICD_IGROUPR10 */
27805  volatile ALT_GIC_DIST_GICD_IGROUPR11_t GICD_IGROUPR11; /* ALT_GIC_DIST_GICD_IGROUPR11 */
27806  volatile ALT_GIC_DIST_GICD_IGROUPR12_t GICD_IGROUPR12; /* ALT_GIC_DIST_GICD_IGROUPR12 */
27807  volatile ALT_GIC_DIST_GICD_IGROUPR13_t GICD_IGROUPR13; /* ALT_GIC_DIST_GICD_IGROUPR13 */
27808  volatile ALT_GIC_DIST_GICD_IGROUPR14_t GICD_IGROUPR14; /* ALT_GIC_DIST_GICD_IGROUPR14 */
27809  volatile ALT_GIC_DIST_GICD_IGROUPR15_t GICD_IGROUPR15; /* ALT_GIC_DIST_GICD_IGROUPR15 */
27810  volatile uint32_t _pad_0xc0_0xff[16]; /* *UNDEFINED* */
27811  volatile ALT_GIC_DIST_GICD_ISENABLER0_t GICD_ISENABLER0; /* ALT_GIC_DIST_GICD_ISENABLER0 */
27812  volatile ALT_GIC_DIST_GICD_ISENABLER1_t GICD_ISENABLER1; /* ALT_GIC_DIST_GICD_ISENABLER1 */
27813  volatile ALT_GIC_DIST_GICD_ISENABLER2_t GICD_ISENABLER2; /* ALT_GIC_DIST_GICD_ISENABLER2 */
27814  volatile ALT_GIC_DIST_GICD_ISENABLER3_t GICD_ISENABLER3; /* ALT_GIC_DIST_GICD_ISENABLER3 */
27815  volatile ALT_GIC_DIST_GICD_ISENABLER4_t GICD_ISENABLER4; /* ALT_GIC_DIST_GICD_ISENABLER4 */
27816  volatile ALT_GIC_DIST_GICD_ISENABLER5_t GICD_ISENABLER5; /* ALT_GIC_DIST_GICD_ISENABLER5 */
27817  volatile ALT_GIC_DIST_GICD_ISENABLER6_t GICD_ISENABLER6; /* ALT_GIC_DIST_GICD_ISENABLER6 */
27818  volatile ALT_GIC_DIST_GICD_ISENABLER7_t GICD_ISENABLER7; /* ALT_GIC_DIST_GICD_ISENABLER7 */
27819  volatile ALT_GIC_DIST_GICD_ISENABLER8_t GICD_ISENABLER8; /* ALT_GIC_DIST_GICD_ISENABLER8 */
27820  volatile ALT_GIC_DIST_GICD_ISENABLER9_t GICD_ISENABLER9; /* ALT_GIC_DIST_GICD_ISENABLER9 */
27821  volatile ALT_GIC_DIST_GICD_ISENABLER10_t GICD_ISENABLER10; /* ALT_GIC_DIST_GICD_ISENABLER10 */
27822  volatile ALT_GIC_DIST_GICD_ISENABLER11_t GICD_ISENABLER11; /* ALT_GIC_DIST_GICD_ISENABLER11 */
27823  volatile ALT_GIC_DIST_GICD_ISENABLER12_t GICD_ISENABLER12; /* ALT_GIC_DIST_GICD_ISENABLER12 */
27824  volatile ALT_GIC_DIST_GICD_ISENABLER13_t GICD_ISENABLER13; /* ALT_GIC_DIST_GICD_ISENABLER13 */
27825  volatile ALT_GIC_DIST_GICD_ISENABLER14_t GICD_ISENABLER14; /* ALT_GIC_DIST_GICD_ISENABLER14 */
27826  volatile ALT_GIC_DIST_GICD_ISENABLER15_t GICD_ISENABLER15; /* ALT_GIC_DIST_GICD_ISENABLER15 */
27827  volatile uint32_t _pad_0x140_0x17f[16]; /* *UNDEFINED* */
27828  volatile ALT_GIC_DIST_GICD_ICENABLER0_t GICD_ICENABLER0; /* ALT_GIC_DIST_GICD_ICENABLER0 */
27829  volatile ALT_GIC_DIST_GICD_ICENABLER1_t GICD_ICENABLER1; /* ALT_GIC_DIST_GICD_ICENABLER1 */
27830  volatile ALT_GIC_DIST_GICD_ICENABLER2_t GICD_ICENABLER2; /* ALT_GIC_DIST_GICD_ICENABLER2 */
27831  volatile ALT_GIC_DIST_GICD_ICENABLER3_t GICD_ICENABLER3; /* ALT_GIC_DIST_GICD_ICENABLER3 */
27832  volatile ALT_GIC_DIST_GICD_ICENABLER4_t GICD_ICENABLER4; /* ALT_GIC_DIST_GICD_ICENABLER4 */
27833  volatile ALT_GIC_DIST_GICD_ICENABLER5_t GICD_ICENABLER5; /* ALT_GIC_DIST_GICD_ICENABLER5 */
27834  volatile ALT_GIC_DIST_GICD_ICENABLER6_t GICD_ICENABLER6; /* ALT_GIC_DIST_GICD_ICENABLER6 */
27835  volatile ALT_GIC_DIST_GICD_ICENABLER7_t GICD_ICENABLER7; /* ALT_GIC_DIST_GICD_ICENABLER7 */
27836  volatile ALT_GIC_DIST_GICD_ICENABLER8_t GICD_ICENABLER8; /* ALT_GIC_DIST_GICD_ICENABLER8 */
27837  volatile ALT_GIC_DIST_GICD_ICENABLER9_t GICD_ICENABLER9; /* ALT_GIC_DIST_GICD_ICENABLER9 */
27838  volatile ALT_GIC_DIST_GICD_ICENABLER10_t GICD_ICENABLER10; /* ALT_GIC_DIST_GICD_ICENABLER10 */
27839  volatile ALT_GIC_DIST_GICD_ICENABLER11_t GICD_ICENABLER11; /* ALT_GIC_DIST_GICD_ICENABLER11 */
27840  volatile ALT_GIC_DIST_GICD_ICENABLER12_t GICD_ICENABLER12; /* ALT_GIC_DIST_GICD_ICENABLER12 */
27841  volatile ALT_GIC_DIST_GICD_ICENABLER13_t GICD_ICENABLER13; /* ALT_GIC_DIST_GICD_ICENABLER13 */
27842  volatile ALT_GIC_DIST_GICD_ICENABLER14_t GICD_ICENABLER14; /* ALT_GIC_DIST_GICD_ICENABLER14 */
27843  volatile ALT_GIC_DIST_GICD_ICENABLER15_t GICD_ICENABLER15; /* ALT_GIC_DIST_GICD_ICENABLER15 */
27844  volatile uint32_t _pad_0x1c0_0x1ff[16]; /* *UNDEFINED* */
27845  volatile ALT_GIC_DIST_GICD_ISPENDR0_t GICD_ISPENDR0; /* ALT_GIC_DIST_GICD_ISPENDR0 */
27846  volatile ALT_GIC_DIST_GICD_ISPENDR1_t GICD_ISPENDR1; /* ALT_GIC_DIST_GICD_ISPENDR1 */
27847  volatile ALT_GIC_DIST_GICD_ISPENDR2_t GICD_ISPENDR2; /* ALT_GIC_DIST_GICD_ISPENDR2 */
27848  volatile ALT_GIC_DIST_GICD_ISPENDR3_t GICD_ISPENDR3; /* ALT_GIC_DIST_GICD_ISPENDR3 */
27849  volatile ALT_GIC_DIST_GICD_ISPENDR4_t GICD_ISPENDR4; /* ALT_GIC_DIST_GICD_ISPENDR4 */
27850  volatile ALT_GIC_DIST_GICD_ISPENDR5_t GICD_ISPENDR5; /* ALT_GIC_DIST_GICD_ISPENDR5 */
27851  volatile ALT_GIC_DIST_GICD_ISPENDR6_t GICD_ISPENDR6; /* ALT_GIC_DIST_GICD_ISPENDR6 */
27852  volatile ALT_GIC_DIST_GICD_ISPENDR7_t GICD_ISPENDR7; /* ALT_GIC_DIST_GICD_ISPENDR7 */
27853  volatile ALT_GIC_DIST_GICD_ISPENDR8_t GICD_ISPENDR8; /* ALT_GIC_DIST_GICD_ISPENDR8 */
27854  volatile ALT_GIC_DIST_GICD_ISPENDR9_t GICD_ISPENDR9; /* ALT_GIC_DIST_GICD_ISPENDR9 */
27855  volatile ALT_GIC_DIST_GICD_ISPENDR10_t GICD_ISPENDR10; /* ALT_GIC_DIST_GICD_ISPENDR10 */
27856  volatile ALT_GIC_DIST_GICD_ISPENDR11_t GICD_ISPENDR11; /* ALT_GIC_DIST_GICD_ISPENDR11 */
27857  volatile ALT_GIC_DIST_GICD_ISPENDR12_t GICD_ISPENDR12; /* ALT_GIC_DIST_GICD_ISPENDR12 */
27858  volatile ALT_GIC_DIST_GICD_ISPENDR13_t GICD_ISPENDR13; /* ALT_GIC_DIST_GICD_ISPENDR13 */
27859  volatile ALT_GIC_DIST_GICD_ISPENDR14_t GICD_ISPENDR14; /* ALT_GIC_DIST_GICD_ISPENDR14 */
27860  volatile ALT_GIC_DIST_GICD_ISPENDR15_t GICD_ISPENDR15; /* ALT_GIC_DIST_GICD_ISPENDR15 */
27861  volatile uint32_t _pad_0x240_0x27f[16]; /* *UNDEFINED* */
27862  volatile ALT_GIC_DIST_GICD_ICPENDR0_t GICD_ICPENDR0; /* ALT_GIC_DIST_GICD_ICPENDR0 */
27863  volatile ALT_GIC_DIST_GICD_ICPENDR1_t GICD_ICPENDR1; /* ALT_GIC_DIST_GICD_ICPENDR1 */
27864  volatile ALT_GIC_DIST_GICD_ICPENDR2_t GICD_ICPENDR2; /* ALT_GIC_DIST_GICD_ICPENDR2 */
27865  volatile ALT_GIC_DIST_GICD_ICPENDR3_t GICD_ICPENDR3; /* ALT_GIC_DIST_GICD_ICPENDR3 */
27866  volatile ALT_GIC_DIST_GICD_ICPENDR4_t GICD_ICPENDR4; /* ALT_GIC_DIST_GICD_ICPENDR4 */
27867  volatile ALT_GIC_DIST_GICD_ICPENDR5_t GICD_ICPENDR5; /* ALT_GIC_DIST_GICD_ICPENDR5 */
27868  volatile ALT_GIC_DIST_GICD_ICPENDR6_t GICD_ICPENDR6; /* ALT_GIC_DIST_GICD_ICPENDR6 */
27869  volatile ALT_GIC_DIST_GICD_ICPENDR7_t GICD_ICPENDR7; /* ALT_GIC_DIST_GICD_ICPENDR7 */
27870  volatile ALT_GIC_DIST_GICD_ICPENDR8_t GICD_ICPENDR8; /* ALT_GIC_DIST_GICD_ICPENDR8 */
27871  volatile ALT_GIC_DIST_GICD_ICPENDR9_t GICD_ICPENDR9; /* ALT_GIC_DIST_GICD_ICPENDR9 */
27872  volatile ALT_GIC_DIST_GICD_ICPENDR10_t GICD_ICPENDR10; /* ALT_GIC_DIST_GICD_ICPENDR10 */
27873  volatile ALT_GIC_DIST_GICD_ICPENDR11_t GICD_ICPENDR11; /* ALT_GIC_DIST_GICD_ICPENDR11 */
27874  volatile ALT_GIC_DIST_GICD_ICPENDR12_t GICD_ICPENDR12; /* ALT_GIC_DIST_GICD_ICPENDR12 */
27875  volatile ALT_GIC_DIST_GICD_ICPENDR13_t GICD_ICPENDR13; /* ALT_GIC_DIST_GICD_ICPENDR13 */
27876  volatile ALT_GIC_DIST_GICD_ICPENDR14_t GICD_ICPENDR14; /* ALT_GIC_DIST_GICD_ICPENDR14 */
27877  volatile ALT_GIC_DIST_GICD_ICPENDR15_t GICD_ICPENDR15; /* ALT_GIC_DIST_GICD_ICPENDR15 */
27878  volatile uint32_t _pad_0x2c0_0x2ff[16]; /* *UNDEFINED* */
27879  volatile ALT_GIC_DIST_GICD_ISACTIVER0_t GICD_ISACTIVER0; /* ALT_GIC_DIST_GICD_ISACTIVER0 */
27880  volatile ALT_GIC_DIST_GICD_ISACTIVER1_t GICD_ISACTIVER1; /* ALT_GIC_DIST_GICD_ISACTIVER1 */
27881  volatile ALT_GIC_DIST_GICD_ISACTIVER2_t GICD_ISACTIVER2; /* ALT_GIC_DIST_GICD_ISACTIVER2 */
27882  volatile ALT_GIC_DIST_GICD_ISACTIVER3_t GICD_ISACTIVER3; /* ALT_GIC_DIST_GICD_ISACTIVER3 */
27883  volatile ALT_GIC_DIST_GICD_ISACTIVER4_t GICD_ISACTIVER4; /* ALT_GIC_DIST_GICD_ISACTIVER4 */
27884  volatile ALT_GIC_DIST_GICD_ISACTIVER5_t GICD_ISACTIVER5; /* ALT_GIC_DIST_GICD_ISACTIVER5 */
27885  volatile ALT_GIC_DIST_GICD_ISACTIVER6_t GICD_ISACTIVER6; /* ALT_GIC_DIST_GICD_ISACTIVER6 */
27886  volatile ALT_GIC_DIST_GICD_ISACTIVER7_t GICD_ISACTIVER7; /* ALT_GIC_DIST_GICD_ISACTIVER7 */
27887  volatile ALT_GIC_DIST_GICD_ISACTIVER8_t GICD_ISACTIVER8; /* ALT_GIC_DIST_GICD_ISACTIVER8 */
27888  volatile ALT_GIC_DIST_GICD_ISACTIVER9_t GICD_ISACTIVER9; /* ALT_GIC_DIST_GICD_ISACTIVER9 */
27889  volatile ALT_GIC_DIST_GICD_ISACTIVER10_t GICD_ISACTIVER10; /* ALT_GIC_DIST_GICD_ISACTIVER10 */
27890  volatile ALT_GIC_DIST_GICD_ISACTIVER11_t GICD_ISACTIVER11; /* ALT_GIC_DIST_GICD_ISACTIVER11 */
27891  volatile ALT_GIC_DIST_GICD_ISACTIVER12_t GICD_ISACTIVER12; /* ALT_GIC_DIST_GICD_ISACTIVER12 */
27892  volatile ALT_GIC_DIST_GICD_ISACTIVER13_t GICD_ISACTIVER13; /* ALT_GIC_DIST_GICD_ISACTIVER13 */
27893  volatile ALT_GIC_DIST_GICD_ISACTIVER14_t GICD_ISACTIVER14; /* ALT_GIC_DIST_GICD_ISACTIVER14 */
27894  volatile ALT_GIC_DIST_GICD_ISACTIVER15_t GICD_ISACTIVER15; /* ALT_GIC_DIST_GICD_ISACTIVER15 */
27895  volatile uint32_t _pad_0x340_0x37f[16]; /* *UNDEFINED* */
27896  volatile ALT_GIC_DIST_GICD_ICACTIVER0_t GICD_ICACTIVER0; /* ALT_GIC_DIST_GICD_ICACTIVER0 */
27897  volatile ALT_GIC_DIST_GICD_ICACTIVER1_t GICD_ICACTIVER1; /* ALT_GIC_DIST_GICD_ICACTIVER1 */
27898  volatile ALT_GIC_DIST_GICD_ICACTIVER2_t GICD_ICACTIVER2; /* ALT_GIC_DIST_GICD_ICACTIVER2 */
27899  volatile ALT_GIC_DIST_GICD_ICACTIVER3_t GICD_ICACTIVER3; /* ALT_GIC_DIST_GICD_ICACTIVER3 */
27900  volatile ALT_GIC_DIST_GICD_ICACTIVER4_t GICD_ICACTIVER4; /* ALT_GIC_DIST_GICD_ICACTIVER4 */
27901  volatile ALT_GIC_DIST_GICD_ICACTIVER5_t GICD_ICACTIVER5; /* ALT_GIC_DIST_GICD_ICACTIVER5 */
27902  volatile ALT_GIC_DIST_GICD_ICACTIVER6_t GICD_ICACTIVER6; /* ALT_GIC_DIST_GICD_ICACTIVER6 */
27903  volatile ALT_GIC_DIST_GICD_ICACTIVER7_t GICD_ICACTIVER7; /* ALT_GIC_DIST_GICD_ICACTIVER7 */
27904  volatile ALT_GIC_DIST_GICD_ICACTIVER8_t GICD_ICACTIVER8; /* ALT_GIC_DIST_GICD_ICACTIVER8 */
27905  volatile ALT_GIC_DIST_GICD_ICACTIVER9_t GICD_ICACTIVER9; /* ALT_GIC_DIST_GICD_ICACTIVER9 */
27906  volatile ALT_GIC_DIST_GICD_ICACTIVER10_t GICD_ICACTIVER10; /* ALT_GIC_DIST_GICD_ICACTIVER10 */
27907  volatile ALT_GIC_DIST_GICD_ICACTIVER11_t GICD_ICACTIVER11; /* ALT_GIC_DIST_GICD_ICACTIVER11 */
27908  volatile ALT_GIC_DIST_GICD_ICACTIVER12_t GICD_ICACTIVER12; /* ALT_GIC_DIST_GICD_ICACTIVER12 */
27909  volatile ALT_GIC_DIST_GICD_ICACTIVER13_t GICD_ICACTIVER13; /* ALT_GIC_DIST_GICD_ICACTIVER13 */
27910  volatile ALT_GIC_DIST_GICD_ICACTIVER14_t GICD_ICACTIVER14; /* ALT_GIC_DIST_GICD_ICACTIVER14 */
27911  volatile ALT_GIC_DIST_GICD_ICACTIVER15_t GICD_ICACTIVER15; /* ALT_GIC_DIST_GICD_ICACTIVER15 */
27912  volatile uint32_t _pad_0x3c0_0x3ff[16]; /* *UNDEFINED* */
27913  volatile ALT_GIC_DIST_GICD_IPRIORITYR0_t GICD_IPRIORITYR0; /* ALT_GIC_DIST_GICD_IPRIORITYR0 */
27914  volatile ALT_GIC_DIST_GICD_IPRIORITYR1_t GICD_IPRIORITYR1; /* ALT_GIC_DIST_GICD_IPRIORITYR1 */
27915  volatile ALT_GIC_DIST_GICD_IPRIORITYR2_t GICD_IPRIORITYR2; /* ALT_GIC_DIST_GICD_IPRIORITYR2 */
27916  volatile ALT_GIC_DIST_GICD_IPRIORITYR3_t GICD_IPRIORITYR3; /* ALT_GIC_DIST_GICD_IPRIORITYR3 */
27917  volatile ALT_GIC_DIST_GICD_IPRIORITYR4_t GICD_IPRIORITYR4; /* ALT_GIC_DIST_GICD_IPRIORITYR4 */
27918  volatile ALT_GIC_DIST_GICD_IPRIORITYR5_t GICD_IPRIORITYR5; /* ALT_GIC_DIST_GICD_IPRIORITYR5 */
27919  volatile ALT_GIC_DIST_GICD_IPRIORITYR6_t GICD_IPRIORITYR6; /* ALT_GIC_DIST_GICD_IPRIORITYR6 */
27920  volatile ALT_GIC_DIST_GICD_IPRIORITYR7_t GICD_IPRIORITYR7; /* ALT_GIC_DIST_GICD_IPRIORITYR7 */
27921  volatile ALT_GIC_DIST_GICD_IPRIORITYR8_t GICD_IPRIORITYR8; /* ALT_GIC_DIST_GICD_IPRIORITYR8 */
27922  volatile ALT_GIC_DIST_GICD_IPRIORITYR9_t GICD_IPRIORITYR9; /* ALT_GIC_DIST_GICD_IPRIORITYR9 */
27923  volatile ALT_GIC_DIST_GICD_IPRIORITYR10_t GICD_IPRIORITYR10; /* ALT_GIC_DIST_GICD_IPRIORITYR10 */
27924  volatile ALT_GIC_DIST_GICD_IPRIORITYR11_t GICD_IPRIORITYR11; /* ALT_GIC_DIST_GICD_IPRIORITYR11 */
27925  volatile ALT_GIC_DIST_GICD_IPRIORITYR12_t GICD_IPRIORITYR12; /* ALT_GIC_DIST_GICD_IPRIORITYR12 */
27926  volatile ALT_GIC_DIST_GICD_IPRIORITYR13_t GICD_IPRIORITYR13; /* ALT_GIC_DIST_GICD_IPRIORITYR13 */
27927  volatile ALT_GIC_DIST_GICD_IPRIORITYR14_t GICD_IPRIORITYR14; /* ALT_GIC_DIST_GICD_IPRIORITYR14 */
27928  volatile ALT_GIC_DIST_GICD_IPRIORITYR15_t GICD_IPRIORITYR15; /* ALT_GIC_DIST_GICD_IPRIORITYR15 */
27929  volatile ALT_GIC_DIST_GICD_IPRIORITYR16_t GICD_IPRIORITYR16; /* ALT_GIC_DIST_GICD_IPRIORITYR16 */
27930  volatile ALT_GIC_DIST_GICD_IPRIORITYR17_t GICD_IPRIORITYR17; /* ALT_GIC_DIST_GICD_IPRIORITYR17 */
27931  volatile ALT_GIC_DIST_GICD_IPRIORITYR18_t GICD_IPRIORITYR18; /* ALT_GIC_DIST_GICD_IPRIORITYR18 */
27932  volatile ALT_GIC_DIST_GICD_IPRIORITYR19_t GICD_IPRIORITYR19; /* ALT_GIC_DIST_GICD_IPRIORITYR19 */
27933  volatile ALT_GIC_DIST_GICD_IPRIORITYR20_t GICD_IPRIORITYR20; /* ALT_GIC_DIST_GICD_IPRIORITYR20 */
27934  volatile ALT_GIC_DIST_GICD_IPRIORITYR21_t GICD_IPRIORITYR21; /* ALT_GIC_DIST_GICD_IPRIORITYR21 */
27935  volatile ALT_GIC_DIST_GICD_IPRIORITYR22_t GICD_IPRIORITYR22; /* ALT_GIC_DIST_GICD_IPRIORITYR22 */
27936  volatile ALT_GIC_DIST_GICD_IPRIORITYR23_t GICD_IPRIORITYR23; /* ALT_GIC_DIST_GICD_IPRIORITYR23 */
27937  volatile ALT_GIC_DIST_GICD_IPRIORITYR24_t GICD_IPRIORITYR24; /* ALT_GIC_DIST_GICD_IPRIORITYR24 */
27938  volatile ALT_GIC_DIST_GICD_IPRIORITYR25_t GICD_IPRIORITYR25; /* ALT_GIC_DIST_GICD_IPRIORITYR25 */
27939  volatile ALT_GIC_DIST_GICD_IPRIORITYR26_t GICD_IPRIORITYR26; /* ALT_GIC_DIST_GICD_IPRIORITYR26 */
27940  volatile ALT_GIC_DIST_GICD_IPRIORITYR27_t GICD_IPRIORITYR27; /* ALT_GIC_DIST_GICD_IPRIORITYR27 */
27941  volatile ALT_GIC_DIST_GICD_IPRIORITYR28_t GICD_IPRIORITYR28; /* ALT_GIC_DIST_GICD_IPRIORITYR28 */
27942  volatile ALT_GIC_DIST_GICD_IPRIORITYR29_t GICD_IPRIORITYR29; /* ALT_GIC_DIST_GICD_IPRIORITYR29 */
27943  volatile ALT_GIC_DIST_GICD_IPRIORITYR30_t GICD_IPRIORITYR30; /* ALT_GIC_DIST_GICD_IPRIORITYR30 */
27944  volatile ALT_GIC_DIST_GICD_IPRIORITYR31_t GICD_IPRIORITYR31; /* ALT_GIC_DIST_GICD_IPRIORITYR31 */
27945  volatile ALT_GIC_DIST_GICD_IPRIORITYR32_t GICD_IPRIORITYR32; /* ALT_GIC_DIST_GICD_IPRIORITYR32 */
27946  volatile ALT_GIC_DIST_GICD_IPRIORITYR33_t GICD_IPRIORITYR33; /* ALT_GIC_DIST_GICD_IPRIORITYR33 */
27947  volatile ALT_GIC_DIST_GICD_IPRIORITYR34_t GICD_IPRIORITYR34; /* ALT_GIC_DIST_GICD_IPRIORITYR34 */
27948  volatile ALT_GIC_DIST_GICD_IPRIORITYR35_t GICD_IPRIORITYR35; /* ALT_GIC_DIST_GICD_IPRIORITYR35 */
27949  volatile ALT_GIC_DIST_GICD_IPRIORITYR36_t GICD_IPRIORITYR36; /* ALT_GIC_DIST_GICD_IPRIORITYR36 */
27950  volatile ALT_GIC_DIST_GICD_IPRIORITYR37_t GICD_IPRIORITYR37; /* ALT_GIC_DIST_GICD_IPRIORITYR37 */
27951  volatile ALT_GIC_DIST_GICD_IPRIORITYR38_t GICD_IPRIORITYR38; /* ALT_GIC_DIST_GICD_IPRIORITYR38 */
27952  volatile ALT_GIC_DIST_GICD_IPRIORITYR39_t GICD_IPRIORITYR39; /* ALT_GIC_DIST_GICD_IPRIORITYR39 */
27953  volatile ALT_GIC_DIST_GICD_IPRIORITYR40_t GICD_IPRIORITYR40; /* ALT_GIC_DIST_GICD_IPRIORITYR40 */
27954  volatile ALT_GIC_DIST_GICD_IPRIORITYR41_t GICD_IPRIORITYR41; /* ALT_GIC_DIST_GICD_IPRIORITYR41 */
27955  volatile ALT_GIC_DIST_GICD_IPRIORITYR42_t GICD_IPRIORITYR42; /* ALT_GIC_DIST_GICD_IPRIORITYR42 */
27956  volatile ALT_GIC_DIST_GICD_IPRIORITYR43_t GICD_IPRIORITYR43; /* ALT_GIC_DIST_GICD_IPRIORITYR43 */
27957  volatile ALT_GIC_DIST_GICD_IPRIORITYR44_t GICD_IPRIORITYR44; /* ALT_GIC_DIST_GICD_IPRIORITYR44 */
27958  volatile ALT_GIC_DIST_GICD_IPRIORITYR45_t GICD_IPRIORITYR45; /* ALT_GIC_DIST_GICD_IPRIORITYR45 */
27959  volatile ALT_GIC_DIST_GICD_IPRIORITYR46_t GICD_IPRIORITYR46; /* ALT_GIC_DIST_GICD_IPRIORITYR46 */
27960  volatile ALT_GIC_DIST_GICD_IPRIORITYR47_t GICD_IPRIORITYR47; /* ALT_GIC_DIST_GICD_IPRIORITYR47 */
27961  volatile ALT_GIC_DIST_GICD_IPRIORITYR48_t GICD_IPRIORITYR48; /* ALT_GIC_DIST_GICD_IPRIORITYR48 */
27962  volatile ALT_GIC_DIST_GICD_IPRIORITYR49_t GICD_IPRIORITYR49; /* ALT_GIC_DIST_GICD_IPRIORITYR49 */
27963  volatile ALT_GIC_DIST_GICD_IPRIORITYR50_t GICD_IPRIORITYR50; /* ALT_GIC_DIST_GICD_IPRIORITYR50 */
27964  volatile ALT_GIC_DIST_GICD_IPRIORITYR51_t GICD_IPRIORITYR51; /* ALT_GIC_DIST_GICD_IPRIORITYR51 */
27965  volatile ALT_GIC_DIST_GICD_IPRIORITYR52_t GICD_IPRIORITYR52; /* ALT_GIC_DIST_GICD_IPRIORITYR52 */
27966  volatile ALT_GIC_DIST_GICD_IPRIORITYR53_t GICD_IPRIORITYR53; /* ALT_GIC_DIST_GICD_IPRIORITYR53 */
27967  volatile ALT_GIC_DIST_GICD_IPRIORITYR54_t GICD_IPRIORITYR54; /* ALT_GIC_DIST_GICD_IPRIORITYR54 */
27968  volatile ALT_GIC_DIST_GICD_IPRIORITYR55_t GICD_IPRIORITYR55; /* ALT_GIC_DIST_GICD_IPRIORITYR55 */
27969  volatile ALT_GIC_DIST_GICD_IPRIORITYR56_t GICD_IPRIORITYR56; /* ALT_GIC_DIST_GICD_IPRIORITYR56 */
27970  volatile ALT_GIC_DIST_GICD_IPRIORITYR57_t GICD_IPRIORITYR57; /* ALT_GIC_DIST_GICD_IPRIORITYR57 */
27971  volatile ALT_GIC_DIST_GICD_IPRIORITYR58_t GICD_IPRIORITYR58; /* ALT_GIC_DIST_GICD_IPRIORITYR58 */
27972  volatile ALT_GIC_DIST_GICD_IPRIORITYR59_t GICD_IPRIORITYR59; /* ALT_GIC_DIST_GICD_IPRIORITYR59 */
27973  volatile ALT_GIC_DIST_GICD_IPRIORITYR60_t GICD_IPRIORITYR60; /* ALT_GIC_DIST_GICD_IPRIORITYR60 */
27974  volatile ALT_GIC_DIST_GICD_IPRIORITYR61_t GICD_IPRIORITYR61; /* ALT_GIC_DIST_GICD_IPRIORITYR61 */
27975  volatile ALT_GIC_DIST_GICD_IPRIORITYR62_t GICD_IPRIORITYR62; /* ALT_GIC_DIST_GICD_IPRIORITYR62 */
27976  volatile ALT_GIC_DIST_GICD_IPRIORITYR63_t GICD_IPRIORITYR63; /* ALT_GIC_DIST_GICD_IPRIORITYR63 */
27977  volatile ALT_GIC_DIST_GICD_IPRIORITYR64_t GICD_IPRIORITYR64; /* ALT_GIC_DIST_GICD_IPRIORITYR64 */
27978  volatile ALT_GIC_DIST_GICD_IPRIORITYR65_t GICD_IPRIORITYR65; /* ALT_GIC_DIST_GICD_IPRIORITYR65 */
27979  volatile ALT_GIC_DIST_GICD_IPRIORITYR66_t GICD_IPRIORITYR66; /* ALT_GIC_DIST_GICD_IPRIORITYR66 */
27980  volatile ALT_GIC_DIST_GICD_IPRIORITYR67_t GICD_IPRIORITYR67; /* ALT_GIC_DIST_GICD_IPRIORITYR67 */
27981  volatile ALT_GIC_DIST_GICD_IPRIORITYR68_t GICD_IPRIORITYR68; /* ALT_GIC_DIST_GICD_IPRIORITYR68 */
27982  volatile ALT_GIC_DIST_GICD_IPRIORITYR69_t GICD_IPRIORITYR69; /* ALT_GIC_DIST_GICD_IPRIORITYR69 */
27983  volatile ALT_GIC_DIST_GICD_IPRIORITYR70_t GICD_IPRIORITYR70; /* ALT_GIC_DIST_GICD_IPRIORITYR70 */
27984  volatile ALT_GIC_DIST_GICD_IPRIORITYR71_t GICD_IPRIORITYR71; /* ALT_GIC_DIST_GICD_IPRIORITYR71 */
27985  volatile ALT_GIC_DIST_GICD_IPRIORITYR72_t GICD_IPRIORITYR72; /* ALT_GIC_DIST_GICD_IPRIORITYR72 */
27986  volatile ALT_GIC_DIST_GICD_IPRIORITYR73_t GICD_IPRIORITYR73; /* ALT_GIC_DIST_GICD_IPRIORITYR73 */
27987  volatile ALT_GIC_DIST_GICD_IPRIORITYR74_t GICD_IPRIORITYR74; /* ALT_GIC_DIST_GICD_IPRIORITYR74 */
27988  volatile ALT_GIC_DIST_GICD_IPRIORITYR75_t GICD_IPRIORITYR75; /* ALT_GIC_DIST_GICD_IPRIORITYR75 */
27989  volatile ALT_GIC_DIST_GICD_IPRIORITYR76_t GICD_IPRIORITYR76; /* ALT_GIC_DIST_GICD_IPRIORITYR76 */
27990  volatile ALT_GIC_DIST_GICD_IPRIORITYR77_t GICD_IPRIORITYR77; /* ALT_GIC_DIST_GICD_IPRIORITYR77 */
27991  volatile ALT_GIC_DIST_GICD_IPRIORITYR78_t GICD_IPRIORITYR78; /* ALT_GIC_DIST_GICD_IPRIORITYR78 */
27992  volatile ALT_GIC_DIST_GICD_IPRIORITYR79_t GICD_IPRIORITYR79; /* ALT_GIC_DIST_GICD_IPRIORITYR79 */
27993  volatile ALT_GIC_DIST_GICD_IPRIORITYR80_t GICD_IPRIORITYR80; /* ALT_GIC_DIST_GICD_IPRIORITYR80 */
27994  volatile ALT_GIC_DIST_GICD_IPRIORITYR81_t GICD_IPRIORITYR81; /* ALT_GIC_DIST_GICD_IPRIORITYR81 */
27995  volatile ALT_GIC_DIST_GICD_IPRIORITYR82_t GICD_IPRIORITYR82; /* ALT_GIC_DIST_GICD_IPRIORITYR82 */
27996  volatile ALT_GIC_DIST_GICD_IPRIORITYR83_t GICD_IPRIORITYR83; /* ALT_GIC_DIST_GICD_IPRIORITYR83 */
27997  volatile ALT_GIC_DIST_GICD_IPRIORITYR84_t GICD_IPRIORITYR84; /* ALT_GIC_DIST_GICD_IPRIORITYR84 */
27998  volatile ALT_GIC_DIST_GICD_IPRIORITYR85_t GICD_IPRIORITYR85; /* ALT_GIC_DIST_GICD_IPRIORITYR85 */
27999  volatile ALT_GIC_DIST_GICD_IPRIORITYR86_t GICD_IPRIORITYR86; /* ALT_GIC_DIST_GICD_IPRIORITYR86 */
28000  volatile ALT_GIC_DIST_GICD_IPRIORITYR87_t GICD_IPRIORITYR87; /* ALT_GIC_DIST_GICD_IPRIORITYR87 */
28001  volatile ALT_GIC_DIST_GICD_IPRIORITYR88_t GICD_IPRIORITYR88; /* ALT_GIC_DIST_GICD_IPRIORITYR88 */
28002  volatile ALT_GIC_DIST_GICD_IPRIORITYR89_t GICD_IPRIORITYR89; /* ALT_GIC_DIST_GICD_IPRIORITYR89 */
28003  volatile ALT_GIC_DIST_GICD_IPRIORITYR90_t GICD_IPRIORITYR90; /* ALT_GIC_DIST_GICD_IPRIORITYR90 */
28004  volatile ALT_GIC_DIST_GICD_IPRIORITYR91_t GICD_IPRIORITYR91; /* ALT_GIC_DIST_GICD_IPRIORITYR91 */
28005  volatile ALT_GIC_DIST_GICD_IPRIORITYR92_t GICD_IPRIORITYR92; /* ALT_GIC_DIST_GICD_IPRIORITYR92 */
28006  volatile ALT_GIC_DIST_GICD_IPRIORITYR93_t GICD_IPRIORITYR93; /* ALT_GIC_DIST_GICD_IPRIORITYR93 */
28007  volatile ALT_GIC_DIST_GICD_IPRIORITYR94_t GICD_IPRIORITYR94; /* ALT_GIC_DIST_GICD_IPRIORITYR94 */
28008  volatile ALT_GIC_DIST_GICD_IPRIORITYR95_t GICD_IPRIORITYR95; /* ALT_GIC_DIST_GICD_IPRIORITYR95 */
28009  volatile ALT_GIC_DIST_GICD_IPRIORITYR96_t GICD_IPRIORITYR96; /* ALT_GIC_DIST_GICD_IPRIORITYR96 */
28010  volatile ALT_GIC_DIST_GICD_IPRIORITYR97_t GICD_IPRIORITYR97; /* ALT_GIC_DIST_GICD_IPRIORITYR97 */
28011  volatile ALT_GIC_DIST_GICD_IPRIORITYR98_t GICD_IPRIORITYR98; /* ALT_GIC_DIST_GICD_IPRIORITYR98 */
28012  volatile ALT_GIC_DIST_GICD_IPRIORITYR99_t GICD_IPRIORITYR99; /* ALT_GIC_DIST_GICD_IPRIORITYR99 */
28013  volatile ALT_GIC_DIST_GICD_IPRIORITYR100_t GICD_IPRIORITYR100; /* ALT_GIC_DIST_GICD_IPRIORITYR100 */
28014  volatile ALT_GIC_DIST_GICD_IPRIORITYR101_t GICD_IPRIORITYR101; /* ALT_GIC_DIST_GICD_IPRIORITYR101 */
28015  volatile ALT_GIC_DIST_GICD_IPRIORITYR102_t GICD_IPRIORITYR102; /* ALT_GIC_DIST_GICD_IPRIORITYR102 */
28016  volatile ALT_GIC_DIST_GICD_IPRIORITYR103_t GICD_IPRIORITYR103; /* ALT_GIC_DIST_GICD_IPRIORITYR103 */
28017  volatile ALT_GIC_DIST_GICD_IPRIORITYR104_t GICD_IPRIORITYR104; /* ALT_GIC_DIST_GICD_IPRIORITYR104 */
28018  volatile ALT_GIC_DIST_GICD_IPRIORITYR105_t GICD_IPRIORITYR105; /* ALT_GIC_DIST_GICD_IPRIORITYR105 */
28019  volatile ALT_GIC_DIST_GICD_IPRIORITYR106_t GICD_IPRIORITYR106; /* ALT_GIC_DIST_GICD_IPRIORITYR106 */
28020  volatile ALT_GIC_DIST_GICD_IPRIORITYR107_t GICD_IPRIORITYR107; /* ALT_GIC_DIST_GICD_IPRIORITYR107 */
28021  volatile ALT_GIC_DIST_GICD_IPRIORITYR108_t GICD_IPRIORITYR108; /* ALT_GIC_DIST_GICD_IPRIORITYR108 */
28022  volatile ALT_GIC_DIST_GICD_IPRIORITYR109_t GICD_IPRIORITYR109; /* ALT_GIC_DIST_GICD_IPRIORITYR109 */
28023  volatile ALT_GIC_DIST_GICD_IPRIORITYR110_t GICD_IPRIORITYR110; /* ALT_GIC_DIST_GICD_IPRIORITYR110 */
28024  volatile ALT_GIC_DIST_GICD_IPRIORITYR111_t GICD_IPRIORITYR111; /* ALT_GIC_DIST_GICD_IPRIORITYR111 */
28025  volatile ALT_GIC_DIST_GICD_IPRIORITYR112_t GICD_IPRIORITYR112; /* ALT_GIC_DIST_GICD_IPRIORITYR112 */
28026  volatile ALT_GIC_DIST_GICD_IPRIORITYR113_t GICD_IPRIORITYR113; /* ALT_GIC_DIST_GICD_IPRIORITYR113 */
28027  volatile ALT_GIC_DIST_GICD_IPRIORITYR114_t GICD_IPRIORITYR114; /* ALT_GIC_DIST_GICD_IPRIORITYR114 */
28028  volatile ALT_GIC_DIST_GICD_IPRIORITYR115_t GICD_IPRIORITYR115; /* ALT_GIC_DIST_GICD_IPRIORITYR115 */
28029  volatile ALT_GIC_DIST_GICD_IPRIORITYR116_t GICD_IPRIORITYR116; /* ALT_GIC_DIST_GICD_IPRIORITYR116 */
28030  volatile ALT_GIC_DIST_GICD_IPRIORITYR117_t GICD_IPRIORITYR117; /* ALT_GIC_DIST_GICD_IPRIORITYR117 */
28031  volatile ALT_GIC_DIST_GICD_IPRIORITYR118_t GICD_IPRIORITYR118; /* ALT_GIC_DIST_GICD_IPRIORITYR118 */
28032  volatile ALT_GIC_DIST_GICD_IPRIORITYR119_t GICD_IPRIORITYR119; /* ALT_GIC_DIST_GICD_IPRIORITYR119 */
28033  volatile ALT_GIC_DIST_GICD_IPRIORITYR120_t GICD_IPRIORITYR120; /* ALT_GIC_DIST_GICD_IPRIORITYR120 */
28034  volatile ALT_GIC_DIST_GICD_IPRIORITYR121_t GICD_IPRIORITYR121; /* ALT_GIC_DIST_GICD_IPRIORITYR121 */
28035  volatile ALT_GIC_DIST_GICD_IPRIORITYR122_t GICD_IPRIORITYR122; /* ALT_GIC_DIST_GICD_IPRIORITYR122 */
28036  volatile ALT_GIC_DIST_GICD_IPRIORITYR123_t GICD_IPRIORITYR123; /* ALT_GIC_DIST_GICD_IPRIORITYR123 */
28037  volatile ALT_GIC_DIST_GICD_IPRIORITYR124_t GICD_IPRIORITYR124; /* ALT_GIC_DIST_GICD_IPRIORITYR124 */
28038  volatile ALT_GIC_DIST_GICD_IPRIORITYR125_t GICD_IPRIORITYR125; /* ALT_GIC_DIST_GICD_IPRIORITYR125 */
28039  volatile ALT_GIC_DIST_GICD_IPRIORITYR126_t GICD_IPRIORITYR126; /* ALT_GIC_DIST_GICD_IPRIORITYR126 */
28040  volatile ALT_GIC_DIST_GICD_IPRIORITYR127_t GICD_IPRIORITYR127; /* ALT_GIC_DIST_GICD_IPRIORITYR127 */
28041  volatile uint32_t _pad_0x600_0x7ff[128]; /* *UNDEFINED* */
28042  volatile ALT_GIC_DIST_GICD_ITARGETSR0_t GICD_ITARGETSR0; /* ALT_GIC_DIST_GICD_ITARGETSR0 */
28043  volatile ALT_GIC_DIST_GICD_ITARGETSR1_t GICD_ITARGETSR1; /* ALT_GIC_DIST_GICD_ITARGETSR1 */
28044  volatile ALT_GIC_DIST_GICD_ITARGETSR2_t GICD_ITARGETSR2; /* ALT_GIC_DIST_GICD_ITARGETSR2 */
28045  volatile ALT_GIC_DIST_GICD_ITARGETSR3_t GICD_ITARGETSR3; /* ALT_GIC_DIST_GICD_ITARGETSR3 */
28046  volatile ALT_GIC_DIST_GICD_ITARGETSR4_t GICD_ITARGETSR4; /* ALT_GIC_DIST_GICD_ITARGETSR4 */
28047  volatile ALT_GIC_DIST_GICD_ITARGETSR5_t GICD_ITARGETSR5; /* ALT_GIC_DIST_GICD_ITARGETSR5 */
28048  volatile ALT_GIC_DIST_GICD_ITARGETSR6_t GICD_ITARGETSR6; /* ALT_GIC_DIST_GICD_ITARGETSR6 */
28049  volatile ALT_GIC_DIST_GICD_ITARGETSR7_t GICD_ITARGETSR7; /* ALT_GIC_DIST_GICD_ITARGETSR7 */
28050  volatile ALT_GIC_DIST_GICD_ITARGETSR8_t GICD_ITARGETSR8; /* ALT_GIC_DIST_GICD_ITARGETSR8 */
28051  volatile ALT_GIC_DIST_GICD_ITARGETSR9_t GICD_ITARGETSR9; /* ALT_GIC_DIST_GICD_ITARGETSR9 */
28052  volatile ALT_GIC_DIST_GICD_ITARGETSR10_t GICD_ITARGETSR10; /* ALT_GIC_DIST_GICD_ITARGETSR10 */
28053  volatile ALT_GIC_DIST_GICD_ITARGETSR11_t GICD_ITARGETSR11; /* ALT_GIC_DIST_GICD_ITARGETSR11 */
28054  volatile ALT_GIC_DIST_GICD_ITARGETSR12_t GICD_ITARGETSR12; /* ALT_GIC_DIST_GICD_ITARGETSR12 */
28055  volatile ALT_GIC_DIST_GICD_ITARGETSR13_t GICD_ITARGETSR13; /* ALT_GIC_DIST_GICD_ITARGETSR13 */
28056  volatile ALT_GIC_DIST_GICD_ITARGETSR14_t GICD_ITARGETSR14; /* ALT_GIC_DIST_GICD_ITARGETSR14 */
28057  volatile ALT_GIC_DIST_GICD_ITARGETSR15_t GICD_ITARGETSR15; /* ALT_GIC_DIST_GICD_ITARGETSR15 */
28058  volatile ALT_GIC_DIST_GICD_ITARGETSR16_t GICD_ITARGETSR16; /* ALT_GIC_DIST_GICD_ITARGETSR16 */
28059  volatile ALT_GIC_DIST_GICD_ITARGETSR17_t GICD_ITARGETSR17; /* ALT_GIC_DIST_GICD_ITARGETSR17 */
28060  volatile ALT_GIC_DIST_GICD_ITARGETSR18_t GICD_ITARGETSR18; /* ALT_GIC_DIST_GICD_ITARGETSR18 */
28061  volatile ALT_GIC_DIST_GICD_ITARGETSR19_t GICD_ITARGETSR19; /* ALT_GIC_DIST_GICD_ITARGETSR19 */
28062  volatile ALT_GIC_DIST_GICD_ITARGETSR20_t GICD_ITARGETSR20; /* ALT_GIC_DIST_GICD_ITARGETSR20 */
28063  volatile ALT_GIC_DIST_GICD_ITARGETSR21_t GICD_ITARGETSR21; /* ALT_GIC_DIST_GICD_ITARGETSR21 */
28064  volatile ALT_GIC_DIST_GICD_ITARGETSR22_t GICD_ITARGETSR22; /* ALT_GIC_DIST_GICD_ITARGETSR22 */
28065  volatile ALT_GIC_DIST_GICD_ITARGETSR23_t GICD_ITARGETSR23; /* ALT_GIC_DIST_GICD_ITARGETSR23 */
28066  volatile ALT_GIC_DIST_GICD_ITARGETSR24_t GICD_ITARGETSR24; /* ALT_GIC_DIST_GICD_ITARGETSR24 */
28067  volatile ALT_GIC_DIST_GICD_ITARGETSR25_t GICD_ITARGETSR25; /* ALT_GIC_DIST_GICD_ITARGETSR25 */
28068  volatile ALT_GIC_DIST_GICD_ITARGETSR26_t GICD_ITARGETSR26; /* ALT_GIC_DIST_GICD_ITARGETSR26 */
28069  volatile ALT_GIC_DIST_GICD_ITARGETSR27_t GICD_ITARGETSR27; /* ALT_GIC_DIST_GICD_ITARGETSR27 */
28070  volatile ALT_GIC_DIST_GICD_ITARGETSR28_t GICD_ITARGETSR28; /* ALT_GIC_DIST_GICD_ITARGETSR28 */
28071  volatile ALT_GIC_DIST_GICD_ITARGETSR29_t GICD_ITARGETSR29; /* ALT_GIC_DIST_GICD_ITARGETSR29 */
28072  volatile ALT_GIC_DIST_GICD_ITARGETSR30_t GICD_ITARGETSR30; /* ALT_GIC_DIST_GICD_ITARGETSR30 */
28073  volatile ALT_GIC_DIST_GICD_ITARGETSR31_t GICD_ITARGETSR31; /* ALT_GIC_DIST_GICD_ITARGETSR31 */
28074  volatile ALT_GIC_DIST_GICD_ITARGETSR32_t GICD_ITARGETSR32; /* ALT_GIC_DIST_GICD_ITARGETSR32 */
28075  volatile ALT_GIC_DIST_GICD_ITARGETSR33_t GICD_ITARGETSR33; /* ALT_GIC_DIST_GICD_ITARGETSR33 */
28076  volatile ALT_GIC_DIST_GICD_ITARGETSR34_t GICD_ITARGETSR34; /* ALT_GIC_DIST_GICD_ITARGETSR34 */
28077  volatile ALT_GIC_DIST_GICD_ITARGETSR35_t GICD_ITARGETSR35; /* ALT_GIC_DIST_GICD_ITARGETSR35 */
28078  volatile ALT_GIC_DIST_GICD_ITARGETSR36_t GICD_ITARGETSR36; /* ALT_GIC_DIST_GICD_ITARGETSR36 */
28079  volatile ALT_GIC_DIST_GICD_ITARGETSR37_t GICD_ITARGETSR37; /* ALT_GIC_DIST_GICD_ITARGETSR37 */
28080  volatile ALT_GIC_DIST_GICD_ITARGETSR38_t GICD_ITARGETSR38; /* ALT_GIC_DIST_GICD_ITARGETSR38 */
28081  volatile ALT_GIC_DIST_GICD_ITARGETSR39_t GICD_ITARGETSR39; /* ALT_GIC_DIST_GICD_ITARGETSR39 */
28082  volatile ALT_GIC_DIST_GICD_ITARGETSR40_t GICD_ITARGETSR40; /* ALT_GIC_DIST_GICD_ITARGETSR40 */
28083  volatile ALT_GIC_DIST_GICD_ITARGETSR41_t GICD_ITARGETSR41; /* ALT_GIC_DIST_GICD_ITARGETSR41 */
28084  volatile ALT_GIC_DIST_GICD_ITARGETSR42_t GICD_ITARGETSR42; /* ALT_GIC_DIST_GICD_ITARGETSR42 */
28085  volatile ALT_GIC_DIST_GICD_ITARGETSR43_t GICD_ITARGETSR43; /* ALT_GIC_DIST_GICD_ITARGETSR43 */
28086  volatile ALT_GIC_DIST_GICD_ITARGETSR44_t GICD_ITARGETSR44; /* ALT_GIC_DIST_GICD_ITARGETSR44 */
28087  volatile ALT_GIC_DIST_GICD_ITARGETSR45_t GICD_ITARGETSR45; /* ALT_GIC_DIST_GICD_ITARGETSR45 */
28088  volatile ALT_GIC_DIST_GICD_ITARGETSR46_t GICD_ITARGETSR46; /* ALT_GIC_DIST_GICD_ITARGETSR46 */
28089  volatile ALT_GIC_DIST_GICD_ITARGETSR47_t GICD_ITARGETSR47; /* ALT_GIC_DIST_GICD_ITARGETSR47 */
28090  volatile ALT_GIC_DIST_GICD_ITARGETSR48_t GICD_ITARGETSR48; /* ALT_GIC_DIST_GICD_ITARGETSR48 */
28091  volatile ALT_GIC_DIST_GICD_ITARGETSR49_t GICD_ITARGETSR49; /* ALT_GIC_DIST_GICD_ITARGETSR49 */
28092  volatile ALT_GIC_DIST_GICD_ITARGETSR50_t GICD_ITARGETSR50; /* ALT_GIC_DIST_GICD_ITARGETSR50 */
28093  volatile ALT_GIC_DIST_GICD_ITARGETSR51_t GICD_ITARGETSR51; /* ALT_GIC_DIST_GICD_ITARGETSR51 */
28094  volatile ALT_GIC_DIST_GICD_ITARGETSR52_t GICD_ITARGETSR52; /* ALT_GIC_DIST_GICD_ITARGETSR52 */
28095  volatile ALT_GIC_DIST_GICD_ITARGETSR53_t GICD_ITARGETSR53; /* ALT_GIC_DIST_GICD_ITARGETSR53 */
28096  volatile ALT_GIC_DIST_GICD_ITARGETSR54_t GICD_ITARGETSR54; /* ALT_GIC_DIST_GICD_ITARGETSR54 */
28097  volatile ALT_GIC_DIST_GICD_ITARGETSR55_t GICD_ITARGETSR55; /* ALT_GIC_DIST_GICD_ITARGETSR55 */
28098  volatile ALT_GIC_DIST_GICD_ITARGETSR56_t GICD_ITARGETSR56; /* ALT_GIC_DIST_GICD_ITARGETSR56 */
28099  volatile ALT_GIC_DIST_GICD_ITARGETSR57_t GICD_ITARGETSR57; /* ALT_GIC_DIST_GICD_ITARGETSR57 */
28100  volatile ALT_GIC_DIST_GICD_ITARGETSR58_t GICD_ITARGETSR58; /* ALT_GIC_DIST_GICD_ITARGETSR58 */
28101  volatile ALT_GIC_DIST_GICD_ITARGETSR59_t GICD_ITARGETSR59; /* ALT_GIC_DIST_GICD_ITARGETSR59 */
28102  volatile ALT_GIC_DIST_GICD_ITARGETSR60_t GICD_ITARGETSR60; /* ALT_GIC_DIST_GICD_ITARGETSR60 */
28103  volatile ALT_GIC_DIST_GICD_ITARGETSR61_t GICD_ITARGETSR61; /* ALT_GIC_DIST_GICD_ITARGETSR61 */
28104  volatile ALT_GIC_DIST_GICD_ITARGETSR62_t GICD_ITARGETSR62; /* ALT_GIC_DIST_GICD_ITARGETSR62 */
28105  volatile ALT_GIC_DIST_GICD_ITARGETSR63_t GICD_ITARGETSR63; /* ALT_GIC_DIST_GICD_ITARGETSR63 */
28106  volatile ALT_GIC_DIST_GICD_ITARGETSR64_t GICD_ITARGETSR64; /* ALT_GIC_DIST_GICD_ITARGETSR64 */
28107  volatile ALT_GIC_DIST_GICD_ITARGETSR65_t GICD_ITARGETSR65; /* ALT_GIC_DIST_GICD_ITARGETSR65 */
28108  volatile ALT_GIC_DIST_GICD_ITARGETSR66_t GICD_ITARGETSR66; /* ALT_GIC_DIST_GICD_ITARGETSR66 */
28109  volatile ALT_GIC_DIST_GICD_ITARGETSR67_t GICD_ITARGETSR67; /* ALT_GIC_DIST_GICD_ITARGETSR67 */
28110  volatile ALT_GIC_DIST_GICD_ITARGETSR68_t GICD_ITARGETSR68; /* ALT_GIC_DIST_GICD_ITARGETSR68 */
28111  volatile ALT_GIC_DIST_GICD_ITARGETSR69_t GICD_ITARGETSR69; /* ALT_GIC_DIST_GICD_ITARGETSR69 */
28112  volatile ALT_GIC_DIST_GICD_ITARGETSR70_t GICD_ITARGETSR70; /* ALT_GIC_DIST_GICD_ITARGETSR70 */
28113  volatile ALT_GIC_DIST_GICD_ITARGETSR71_t GICD_ITARGETSR71; /* ALT_GIC_DIST_GICD_ITARGETSR71 */
28114  volatile ALT_GIC_DIST_GICD_ITARGETSR72_t GICD_ITARGETSR72; /* ALT_GIC_DIST_GICD_ITARGETSR72 */
28115  volatile ALT_GIC_DIST_GICD_ITARGETSR73_t GICD_ITARGETSR73; /* ALT_GIC_DIST_GICD_ITARGETSR73 */
28116  volatile ALT_GIC_DIST_GICD_ITARGETSR74_t GICD_ITARGETSR74; /* ALT_GIC_DIST_GICD_ITARGETSR74 */
28117  volatile ALT_GIC_DIST_GICD_ITARGETSR75_t GICD_ITARGETSR75; /* ALT_GIC_DIST_GICD_ITARGETSR75 */
28118  volatile ALT_GIC_DIST_GICD_ITARGETSR76_t GICD_ITARGETSR76; /* ALT_GIC_DIST_GICD_ITARGETSR76 */
28119  volatile ALT_GIC_DIST_GICD_ITARGETSR77_t GICD_ITARGETSR77; /* ALT_GIC_DIST_GICD_ITARGETSR77 */
28120  volatile ALT_GIC_DIST_GICD_ITARGETSR78_t GICD_ITARGETSR78; /* ALT_GIC_DIST_GICD_ITARGETSR78 */
28121  volatile ALT_GIC_DIST_GICD_ITARGETSR79_t GICD_ITARGETSR79; /* ALT_GIC_DIST_GICD_ITARGETSR79 */
28122  volatile ALT_GIC_DIST_GICD_ITARGETSR80_t GICD_ITARGETSR80; /* ALT_GIC_DIST_GICD_ITARGETSR80 */
28123  volatile ALT_GIC_DIST_GICD_ITARGETSR81_t GICD_ITARGETSR81; /* ALT_GIC_DIST_GICD_ITARGETSR81 */
28124  volatile ALT_GIC_DIST_GICD_ITARGETSR82_t GICD_ITARGETSR82; /* ALT_GIC_DIST_GICD_ITARGETSR82 */
28125  volatile ALT_GIC_DIST_GICD_ITARGETSR83_t GICD_ITARGETSR83; /* ALT_GIC_DIST_GICD_ITARGETSR83 */
28126  volatile ALT_GIC_DIST_GICD_ITARGETSR84_t GICD_ITARGETSR84; /* ALT_GIC_DIST_GICD_ITARGETSR84 */
28127  volatile ALT_GIC_DIST_GICD_ITARGETSR85_t GICD_ITARGETSR85; /* ALT_GIC_DIST_GICD_ITARGETSR85 */
28128  volatile ALT_GIC_DIST_GICD_ITARGETSR86_t GICD_ITARGETSR86; /* ALT_GIC_DIST_GICD_ITARGETSR86 */
28129  volatile ALT_GIC_DIST_GICD_ITARGETSR87_t GICD_ITARGETSR87; /* ALT_GIC_DIST_GICD_ITARGETSR87 */
28130  volatile ALT_GIC_DIST_GICD_ITARGETSR88_t GICD_ITARGETSR88; /* ALT_GIC_DIST_GICD_ITARGETSR88 */
28131  volatile ALT_GIC_DIST_GICD_ITARGETSR89_t GICD_ITARGETSR89; /* ALT_GIC_DIST_GICD_ITARGETSR89 */
28132  volatile ALT_GIC_DIST_GICD_ITARGETSR90_t GICD_ITARGETSR90; /* ALT_GIC_DIST_GICD_ITARGETSR90 */
28133  volatile ALT_GIC_DIST_GICD_ITARGETSR91_t GICD_ITARGETSR91; /* ALT_GIC_DIST_GICD_ITARGETSR91 */
28134  volatile ALT_GIC_DIST_GICD_ITARGETSR92_t GICD_ITARGETSR92; /* ALT_GIC_DIST_GICD_ITARGETSR92 */
28135  volatile ALT_GIC_DIST_GICD_ITARGETSR93_t GICD_ITARGETSR93; /* ALT_GIC_DIST_GICD_ITARGETSR93 */
28136  volatile ALT_GIC_DIST_GICD_ITARGETSR94_t GICD_ITARGETSR94; /* ALT_GIC_DIST_GICD_ITARGETSR94 */
28137  volatile ALT_GIC_DIST_GICD_ITARGETSR95_t GICD_ITARGETSR95; /* ALT_GIC_DIST_GICD_ITARGETSR95 */
28138  volatile ALT_GIC_DIST_GICD_ITARGETSR96_t GICD_ITARGETSR96; /* ALT_GIC_DIST_GICD_ITARGETSR96 */
28139  volatile ALT_GIC_DIST_GICD_ITARGETSR97_t GICD_ITARGETSR97; /* ALT_GIC_DIST_GICD_ITARGETSR97 */
28140  volatile ALT_GIC_DIST_GICD_ITARGETSR98_t GICD_ITARGETSR98; /* ALT_GIC_DIST_GICD_ITARGETSR98 */
28141  volatile ALT_GIC_DIST_GICD_ITARGETSR99_t GICD_ITARGETSR99; /* ALT_GIC_DIST_GICD_ITARGETSR99 */
28142  volatile ALT_GIC_DIST_GICD_ITARGETSR100_t GICD_ITARGETSR100; /* ALT_GIC_DIST_GICD_ITARGETSR100 */
28143  volatile ALT_GIC_DIST_GICD_ITARGETSR101_t GICD_ITARGETSR101; /* ALT_GIC_DIST_GICD_ITARGETSR101 */
28144  volatile ALT_GIC_DIST_GICD_ITARGETSR102_t GICD_ITARGETSR102; /* ALT_GIC_DIST_GICD_ITARGETSR102 */
28145  volatile ALT_GIC_DIST_GICD_ITARGETSR103_t GICD_ITARGETSR103; /* ALT_GIC_DIST_GICD_ITARGETSR103 */
28146  volatile ALT_GIC_DIST_GICD_ITARGETSR104_t GICD_ITARGETSR104; /* ALT_GIC_DIST_GICD_ITARGETSR104 */
28147  volatile ALT_GIC_DIST_GICD_ITARGETSR105_t GICD_ITARGETSR105; /* ALT_GIC_DIST_GICD_ITARGETSR105 */
28148  volatile ALT_GIC_DIST_GICD_ITARGETSR106_t GICD_ITARGETSR106; /* ALT_GIC_DIST_GICD_ITARGETSR106 */
28149  volatile ALT_GIC_DIST_GICD_ITARGETSR107_t GICD_ITARGETSR107; /* ALT_GIC_DIST_GICD_ITARGETSR107 */
28150  volatile ALT_GIC_DIST_GICD_ITARGETSR108_t GICD_ITARGETSR108; /* ALT_GIC_DIST_GICD_ITARGETSR108 */
28151  volatile ALT_GIC_DIST_GICD_ITARGETSR109_t GICD_ITARGETSR109; /* ALT_GIC_DIST_GICD_ITARGETSR109 */
28152  volatile ALT_GIC_DIST_GICD_ITARGETSR110_t GICD_ITARGETSR110; /* ALT_GIC_DIST_GICD_ITARGETSR110 */
28153  volatile ALT_GIC_DIST_GICD_ITARGETSR111_t GICD_ITARGETSR111; /* ALT_GIC_DIST_GICD_ITARGETSR111 */
28154  volatile ALT_GIC_DIST_GICD_ITARGETSR112_t GICD_ITARGETSR112; /* ALT_GIC_DIST_GICD_ITARGETSR112 */
28155  volatile ALT_GIC_DIST_GICD_ITARGETSR113_t GICD_ITARGETSR113; /* ALT_GIC_DIST_GICD_ITARGETSR113 */
28156  volatile ALT_GIC_DIST_GICD_ITARGETSR114_t GICD_ITARGETSR114; /* ALT_GIC_DIST_GICD_ITARGETSR114 */
28157  volatile ALT_GIC_DIST_GICD_ITARGETSR115_t GICD_ITARGETSR115; /* ALT_GIC_DIST_GICD_ITARGETSR115 */
28158  volatile ALT_GIC_DIST_GICD_ITARGETSR116_t GICD_ITARGETSR116; /* ALT_GIC_DIST_GICD_ITARGETSR116 */
28159  volatile ALT_GIC_DIST_GICD_ITARGETSR117_t GICD_ITARGETSR117; /* ALT_GIC_DIST_GICD_ITARGETSR117 */
28160  volatile ALT_GIC_DIST_GICD_ITARGETSR118_t GICD_ITARGETSR118; /* ALT_GIC_DIST_GICD_ITARGETSR118 */
28161  volatile ALT_GIC_DIST_GICD_ITARGETSR119_t GICD_ITARGETSR119; /* ALT_GIC_DIST_GICD_ITARGETSR119 */
28162  volatile ALT_GIC_DIST_GICD_ITARGETSR120_t GICD_ITARGETSR120; /* ALT_GIC_DIST_GICD_ITARGETSR120 */
28163  volatile ALT_GIC_DIST_GICD_ITARGETSR121_t GICD_ITARGETSR121; /* ALT_GIC_DIST_GICD_ITARGETSR121 */
28164  volatile ALT_GIC_DIST_GICD_ITARGETSR122_t GICD_ITARGETSR122; /* ALT_GIC_DIST_GICD_ITARGETSR122 */
28165  volatile ALT_GIC_DIST_GICD_ITARGETSR123_t GICD_ITARGETSR123; /* ALT_GIC_DIST_GICD_ITARGETSR123 */
28166  volatile ALT_GIC_DIST_GICD_ITARGETSR124_t GICD_ITARGETSR124; /* ALT_GIC_DIST_GICD_ITARGETSR124 */
28167  volatile ALT_GIC_DIST_GICD_ITARGETSR125_t GICD_ITARGETSR125; /* ALT_GIC_DIST_GICD_ITARGETSR125 */
28168  volatile ALT_GIC_DIST_GICD_ITARGETSR126_t GICD_ITARGETSR126; /* ALT_GIC_DIST_GICD_ITARGETSR126 */
28169  volatile ALT_GIC_DIST_GICD_ITARGETSR127_t GICD_ITARGETSR127; /* ALT_GIC_DIST_GICD_ITARGETSR127 */
28170  volatile uint32_t _pad_0xa00_0xbff[128]; /* *UNDEFINED* */
28171  volatile ALT_GIC_DIST_GICD_ICFGR0_t GICD_ICFGR0; /* ALT_GIC_DIST_GICD_ICFGR0 */
28172  volatile ALT_GIC_DIST_GICD_ICFGR1_t GICD_ICFGR1; /* ALT_GIC_DIST_GICD_ICFGR1 */
28173  volatile ALT_GIC_DIST_GICD_ICFGR2_t GICD_ICFGR2; /* ALT_GIC_DIST_GICD_ICFGR2 */
28174  volatile ALT_GIC_DIST_GICD_ICFGR3_t GICD_ICFGR3; /* ALT_GIC_DIST_GICD_ICFGR3 */
28175  volatile ALT_GIC_DIST_GICD_ICFGR4_t GICD_ICFGR4; /* ALT_GIC_DIST_GICD_ICFGR4 */
28176  volatile ALT_GIC_DIST_GICD_ICFGR5_t GICD_ICFGR5; /* ALT_GIC_DIST_GICD_ICFGR5 */
28177  volatile ALT_GIC_DIST_GICD_ICFGR6_t GICD_ICFGR6; /* ALT_GIC_DIST_GICD_ICFGR6 */
28178  volatile ALT_GIC_DIST_GICD_ICFGR7_t GICD_ICFGR7; /* ALT_GIC_DIST_GICD_ICFGR7 */
28179  volatile ALT_GIC_DIST_GICD_ICFGR8_t GICD_ICFGR8; /* ALT_GIC_DIST_GICD_ICFGR8 */
28180  volatile ALT_GIC_DIST_GICD_ICFGR9_t GICD_ICFGR9; /* ALT_GIC_DIST_GICD_ICFGR9 */
28181  volatile ALT_GIC_DIST_GICD_ICFGR10_t GICD_ICFGR10; /* ALT_GIC_DIST_GICD_ICFGR10 */
28182  volatile ALT_GIC_DIST_GICD_ICFGR11_t GICD_ICFGR11; /* ALT_GIC_DIST_GICD_ICFGR11 */
28183  volatile ALT_GIC_DIST_GICD_ICFGR12_t GICD_ICFGR12; /* ALT_GIC_DIST_GICD_ICFGR12 */
28184  volatile ALT_GIC_DIST_GICD_ICFGR13_t GICD_ICFGR13; /* ALT_GIC_DIST_GICD_ICFGR13 */
28185  volatile ALT_GIC_DIST_GICD_ICFGR14_t GICD_ICFGR14; /* ALT_GIC_DIST_GICD_ICFGR14 */
28186  volatile ALT_GIC_DIST_GICD_ICFGR15_t GICD_ICFGR15; /* ALT_GIC_DIST_GICD_ICFGR15 */
28187  volatile ALT_GIC_DIST_GICD_ICFGR16_t GICD_ICFGR16; /* ALT_GIC_DIST_GICD_ICFGR16 */
28188  volatile ALT_GIC_DIST_GICD_ICFGR17_t GICD_ICFGR17; /* ALT_GIC_DIST_GICD_ICFGR17 */
28189  volatile ALT_GIC_DIST_GICD_ICFGR18_t GICD_ICFGR18; /* ALT_GIC_DIST_GICD_ICFGR18 */
28190  volatile ALT_GIC_DIST_GICD_ICFGR19_t GICD_ICFGR19; /* ALT_GIC_DIST_GICD_ICFGR19 */
28191  volatile ALT_GIC_DIST_GICD_ICFGR20_t GICD_ICFGR20; /* ALT_GIC_DIST_GICD_ICFGR20 */
28192  volatile ALT_GIC_DIST_GICD_ICFGR21_t GICD_ICFGR21; /* ALT_GIC_DIST_GICD_ICFGR21 */
28193  volatile ALT_GIC_DIST_GICD_ICFGR22_t GICD_ICFGR22; /* ALT_GIC_DIST_GICD_ICFGR22 */
28194  volatile ALT_GIC_DIST_GICD_ICFGR23_t GICD_ICFGR23; /* ALT_GIC_DIST_GICD_ICFGR23 */
28195  volatile ALT_GIC_DIST_GICD_ICFGR24_t GICD_ICFGR24; /* ALT_GIC_DIST_GICD_ICFGR24 */
28196  volatile ALT_GIC_DIST_GICD_ICFGR25_t GICD_ICFGR25; /* ALT_GIC_DIST_GICD_ICFGR25 */
28197  volatile ALT_GIC_DIST_GICD_ICFGR26_t GICD_ICFGR26; /* ALT_GIC_DIST_GICD_ICFGR26 */
28198  volatile ALT_GIC_DIST_GICD_ICFGR27_t GICD_ICFGR27; /* ALT_GIC_DIST_GICD_ICFGR27 */
28199  volatile ALT_GIC_DIST_GICD_ICFGR28_t GICD_ICFGR28; /* ALT_GIC_DIST_GICD_ICFGR28 */
28200  volatile ALT_GIC_DIST_GICD_ICFGR29_t GICD_ICFGR29; /* ALT_GIC_DIST_GICD_ICFGR29 */
28201  volatile ALT_GIC_DIST_GICD_ICFGR30_t GICD_ICFGR30; /* ALT_GIC_DIST_GICD_ICFGR30 */
28202  volatile ALT_GIC_DIST_GICD_ICFGR31_t GICD_ICFGR31; /* ALT_GIC_DIST_GICD_ICFGR31 */
28203  volatile uint32_t _pad_0xc80_0xcff[32]; /* *UNDEFINED* */
28204  volatile ALT_GIC_DIST_GICD_PPISR_t GICD_PPISR; /* ALT_GIC_DIST_GICD_PPISR */
28205  volatile ALT_GIC_DIST_GICD_SPISR0_t GICD_SPISR0; /* ALT_GIC_DIST_GICD_SPISR0 */
28206  volatile ALT_GIC_DIST_GICD_SPISR1_t GICD_SPISR1; /* ALT_GIC_DIST_GICD_SPISR1 */
28207  volatile ALT_GIC_DIST_GICD_SPISR2_t GICD_SPISR2; /* ALT_GIC_DIST_GICD_SPISR2 */
28208  volatile ALT_GIC_DIST_GICD_SPISR3_t GICD_SPISR3; /* ALT_GIC_DIST_GICD_SPISR3 */
28209  volatile ALT_GIC_DIST_GICD_SPISR4_t GICD_SPISR4; /* ALT_GIC_DIST_GICD_SPISR4 */
28210  volatile ALT_GIC_DIST_GICD_SPISR5_t GICD_SPISR5; /* ALT_GIC_DIST_GICD_SPISR5 */
28211  volatile ALT_GIC_DIST_GICD_SPISR6_t GICD_SPISR6; /* ALT_GIC_DIST_GICD_SPISR6 */
28212  volatile ALT_GIC_DIST_GICD_SPISR7_t GICD_SPISR7; /* ALT_GIC_DIST_GICD_SPISR7 */
28213  volatile ALT_GIC_DIST_GICD_SPISR8_t GICD_SPISR8; /* ALT_GIC_DIST_GICD_SPISR8 */
28214  volatile ALT_GIC_DIST_GICD_SPISR9_t GICD_SPISR9; /* ALT_GIC_DIST_GICD_SPISR9 */
28215  volatile ALT_GIC_DIST_GICD_SPISR10_t GICD_SPISR10; /* ALT_GIC_DIST_GICD_SPISR10 */
28216  volatile ALT_GIC_DIST_GICD_SPISR11_t GICD_SPISR11; /* ALT_GIC_DIST_GICD_SPISR11 */
28217  volatile ALT_GIC_DIST_GICD_SPISR12_t GICD_SPISR12; /* ALT_GIC_DIST_GICD_SPISR12 */
28218  volatile ALT_GIC_DIST_GICD_SPISR13_t GICD_SPISR13; /* ALT_GIC_DIST_GICD_SPISR13 */
28219  volatile ALT_GIC_DIST_GICD_SPISR14_t GICD_SPISR14; /* ALT_GIC_DIST_GICD_SPISR14 */
28220  volatile uint32_t _pad_0xd40_0xeff[112]; /* *UNDEFINED* */
28221  volatile ALT_GIC_DIST_GICD_SGIR_t GICD_SGIR; /* ALT_GIC_DIST_GICD_SGIR */
28222  volatile uint32_t _pad_0xf04_0xf0f[3]; /* *UNDEFINED* */
28223  volatile ALT_GIC_DIST_GICD_CPENDSGIR0_t GICD_CPENDSGIR0; /* ALT_GIC_DIST_GICD_CPENDSGIR0 */
28224  volatile ALT_GIC_DIST_GICD_CPENDSGIR1_t GICD_CPENDSGIR1; /* ALT_GIC_DIST_GICD_CPENDSGIR1 */
28225  volatile ALT_GIC_DIST_GICD_CPENDSGIR2_t GICD_CPENDSGIR2; /* ALT_GIC_DIST_GICD_CPENDSGIR2 */
28226  volatile ALT_GIC_DIST_GICD_CPENDSGIR3_t GICD_CPENDSGIR3; /* ALT_GIC_DIST_GICD_CPENDSGIR3 */
28227  volatile ALT_GIC_DIST_GICD_SPENDSGIR0_t GICD_SPENDSGIR0; /* ALT_GIC_DIST_GICD_SPENDSGIR0 */
28228  volatile ALT_GIC_DIST_GICD_SPENDSGIR1_t GICD_SPENDSGIR1; /* ALT_GIC_DIST_GICD_SPENDSGIR1 */
28229  volatile ALT_GIC_DIST_GICD_SPENDSGIR2_t GICD_SPENDSGIR2; /* ALT_GIC_DIST_GICD_SPENDSGIR2 */
28230  volatile ALT_GIC_DIST_GICD_SPENDSGIR3_t GICD_SPENDSGIR3; /* ALT_GIC_DIST_GICD_SPENDSGIR3 */
28231  volatile uint32_t _pad_0xf30_0xfcf[40]; /* *UNDEFINED* */
28232  volatile ALT_GIC_DIST_GICD_PIDR4_t GICD_PIDR4; /* ALT_GIC_DIST_GICD_PIDR4 */
28233  volatile ALT_GIC_DIST_GICD_PIDR5_t GICD_PIDR5; /* ALT_GIC_DIST_GICD_PIDR5 */
28234  volatile ALT_GIC_DIST_GICD_PIDR6_t GICD_PIDR6; /* ALT_GIC_DIST_GICD_PIDR6 */
28235  volatile ALT_GIC_DIST_GICD_PIDR7_t GICD_PIDR7; /* ALT_GIC_DIST_GICD_PIDR7 */
28236  volatile ALT_GIC_DIST_GICD_PIDR0_t GICD_PIDR0; /* ALT_GIC_DIST_GICD_PIDR0 */
28237  volatile ALT_GIC_DIST_GICD_PIDR1_t GICD_PIDR1; /* ALT_GIC_DIST_GICD_PIDR1 */
28238  volatile ALT_GIC_DIST_GICD_PIDR2_t GICD_PIDR2; /* ALT_GIC_DIST_GICD_PIDR2 */
28239  volatile ALT_GIC_DIST_GICD_PIDR3_t GICD_PIDR3; /* ALT_GIC_DIST_GICD_PIDR3 */
28240  volatile ALT_GIC_DIST_GICD_CIDR0_t GICD_CIDR0; /* ALT_GIC_DIST_GICD_CIDR0 */
28241  volatile ALT_GIC_DIST_GICD_CIDR1_t GICD_CIDR1; /* ALT_GIC_DIST_GICD_CIDR1 */
28242  volatile ALT_GIC_DIST_GICD_CIDR2_t GICD_CIDR2; /* ALT_GIC_DIST_GICD_CIDR2 */
28243  volatile ALT_GIC_DIST_GICD_CIDR3_t GICD_CIDR3; /* ALT_GIC_DIST_GICD_CIDR3 */
28244 };
28245 
28246 /* The typedef declaration for register group ALT_GIC_DIST. */
28247 typedef struct ALT_GIC_DIST_s ALT_GIC_DIST_t;
28248 /* The struct declaration for the raw register contents of register group ALT_GIC_DIST. */
28249 struct ALT_GIC_DIST_raw_s
28250 {
28251  volatile uint32_t GICD_CTLR; /* ALT_GIC_DIST_GICD_CTLR */
28252  volatile uint32_t GICD_TYPER; /* ALT_GIC_DIST_GICD_TYPER */
28253  volatile uint32_t GICD_IIDR; /* ALT_GIC_DIST_GICD_IIDR */
28254  volatile uint32_t _pad_0xc_0x7f[29]; /* *UNDEFINED* */
28255  volatile uint32_t GICD_IGROUPR0; /* ALT_GIC_DIST_GICD_IGROUPR0 */
28256  volatile uint32_t GICD_IGROUPR1; /* ALT_GIC_DIST_GICD_IGROUPR1 */
28257  volatile uint32_t GICD_IGROUPR2; /* ALT_GIC_DIST_GICD_IGROUPR2 */
28258  volatile uint32_t GICD_IGROUPR3; /* ALT_GIC_DIST_GICD_IGROUPR3 */
28259  volatile uint32_t GICD_IGROUPR4; /* ALT_GIC_DIST_GICD_IGROUPR4 */
28260  volatile uint32_t GICD_IGROUPR5; /* ALT_GIC_DIST_GICD_IGROUPR5 */
28261  volatile uint32_t GICD_IGROUPR6; /* ALT_GIC_DIST_GICD_IGROUPR6 */
28262  volatile uint32_t GICD_IGROUPR7; /* ALT_GIC_DIST_GICD_IGROUPR7 */
28263  volatile uint32_t GICD_IGROUPR8; /* ALT_GIC_DIST_GICD_IGROUPR8 */
28264  volatile uint32_t GICD_IGROUPR9; /* ALT_GIC_DIST_GICD_IGROUPR9 */
28265  volatile uint32_t GICD_IGROUPR10; /* ALT_GIC_DIST_GICD_IGROUPR10 */
28266  volatile uint32_t GICD_IGROUPR11; /* ALT_GIC_DIST_GICD_IGROUPR11 */
28267  volatile uint32_t GICD_IGROUPR12; /* ALT_GIC_DIST_GICD_IGROUPR12 */
28268  volatile uint32_t GICD_IGROUPR13; /* ALT_GIC_DIST_GICD_IGROUPR13 */
28269  volatile uint32_t GICD_IGROUPR14; /* ALT_GIC_DIST_GICD_IGROUPR14 */
28270  volatile uint32_t GICD_IGROUPR15; /* ALT_GIC_DIST_GICD_IGROUPR15 */
28271  volatile uint32_t _pad_0xc0_0xff[16]; /* *UNDEFINED* */
28272  volatile uint32_t GICD_ISENABLER0; /* ALT_GIC_DIST_GICD_ISENABLER0 */
28273  volatile uint32_t GICD_ISENABLER1; /* ALT_GIC_DIST_GICD_ISENABLER1 */
28274  volatile uint32_t GICD_ISENABLER2; /* ALT_GIC_DIST_GICD_ISENABLER2 */
28275  volatile uint32_t GICD_ISENABLER3; /* ALT_GIC_DIST_GICD_ISENABLER3 */
28276  volatile uint32_t GICD_ISENABLER4; /* ALT_GIC_DIST_GICD_ISENABLER4 */
28277  volatile uint32_t GICD_ISENABLER5; /* ALT_GIC_DIST_GICD_ISENABLER5 */
28278  volatile uint32_t GICD_ISENABLER6; /* ALT_GIC_DIST_GICD_ISENABLER6 */
28279  volatile uint32_t GICD_ISENABLER7; /* ALT_GIC_DIST_GICD_ISENABLER7 */
28280  volatile uint32_t GICD_ISENABLER8; /* ALT_GIC_DIST_GICD_ISENABLER8 */
28281  volatile uint32_t GICD_ISENABLER9; /* ALT_GIC_DIST_GICD_ISENABLER9 */
28282  volatile uint32_t GICD_ISENABLER10; /* ALT_GIC_DIST_GICD_ISENABLER10 */
28283  volatile uint32_t GICD_ISENABLER11; /* ALT_GIC_DIST_GICD_ISENABLER11 */
28284  volatile uint32_t GICD_ISENABLER12; /* ALT_GIC_DIST_GICD_ISENABLER12 */
28285  volatile uint32_t GICD_ISENABLER13; /* ALT_GIC_DIST_GICD_ISENABLER13 */
28286  volatile uint32_t GICD_ISENABLER14; /* ALT_GIC_DIST_GICD_ISENABLER14 */
28287  volatile uint32_t GICD_ISENABLER15; /* ALT_GIC_DIST_GICD_ISENABLER15 */
28288  volatile uint32_t _pad_0x140_0x17f[16]; /* *UNDEFINED* */
28289  volatile uint32_t GICD_ICENABLER0; /* ALT_GIC_DIST_GICD_ICENABLER0 */
28290  volatile uint32_t GICD_ICENABLER1; /* ALT_GIC_DIST_GICD_ICENABLER1 */
28291  volatile uint32_t GICD_ICENABLER2; /* ALT_GIC_DIST_GICD_ICENABLER2 */
28292  volatile uint32_t GICD_ICENABLER3; /* ALT_GIC_DIST_GICD_ICENABLER3 */
28293  volatile uint32_t GICD_ICENABLER4; /* ALT_GIC_DIST_GICD_ICENABLER4 */
28294  volatile uint32_t GICD_ICENABLER5; /* ALT_GIC_DIST_GICD_ICENABLER5 */
28295  volatile uint32_t GICD_ICENABLER6; /* ALT_GIC_DIST_GICD_ICENABLER6 */
28296  volatile uint32_t GICD_ICENABLER7; /* ALT_GIC_DIST_GICD_ICENABLER7 */
28297  volatile uint32_t GICD_ICENABLER8; /* ALT_GIC_DIST_GICD_ICENABLER8 */
28298  volatile uint32_t GICD_ICENABLER9; /* ALT_GIC_DIST_GICD_ICENABLER9 */
28299  volatile uint32_t GICD_ICENABLER10; /* ALT_GIC_DIST_GICD_ICENABLER10 */
28300  volatile uint32_t GICD_ICENABLER11; /* ALT_GIC_DIST_GICD_ICENABLER11 */
28301  volatile uint32_t GICD_ICENABLER12; /* ALT_GIC_DIST_GICD_ICENABLER12 */
28302  volatile uint32_t GICD_ICENABLER13; /* ALT_GIC_DIST_GICD_ICENABLER13 */
28303  volatile uint32_t GICD_ICENABLER14; /* ALT_GIC_DIST_GICD_ICENABLER14 */
28304  volatile uint32_t GICD_ICENABLER15; /* ALT_GIC_DIST_GICD_ICENABLER15 */
28305  volatile uint32_t _pad_0x1c0_0x1ff[16]; /* *UNDEFINED* */
28306  volatile uint32_t GICD_ISPENDR0; /* ALT_GIC_DIST_GICD_ISPENDR0 */
28307  volatile uint32_t GICD_ISPENDR1; /* ALT_GIC_DIST_GICD_ISPENDR1 */
28308  volatile uint32_t GICD_ISPENDR2; /* ALT_GIC_DIST_GICD_ISPENDR2 */
28309  volatile uint32_t GICD_ISPENDR3; /* ALT_GIC_DIST_GICD_ISPENDR3 */
28310  volatile uint32_t GICD_ISPENDR4; /* ALT_GIC_DIST_GICD_ISPENDR4 */
28311  volatile uint32_t GICD_ISPENDR5; /* ALT_GIC_DIST_GICD_ISPENDR5 */
28312  volatile uint32_t GICD_ISPENDR6; /* ALT_GIC_DIST_GICD_ISPENDR6 */
28313  volatile uint32_t GICD_ISPENDR7; /* ALT_GIC_DIST_GICD_ISPENDR7 */
28314  volatile uint32_t GICD_ISPENDR8; /* ALT_GIC_DIST_GICD_ISPENDR8 */
28315  volatile uint32_t GICD_ISPENDR9; /* ALT_GIC_DIST_GICD_ISPENDR9 */
28316  volatile uint32_t GICD_ISPENDR10; /* ALT_GIC_DIST_GICD_ISPENDR10 */
28317  volatile uint32_t GICD_ISPENDR11; /* ALT_GIC_DIST_GICD_ISPENDR11 */
28318  volatile uint32_t GICD_ISPENDR12; /* ALT_GIC_DIST_GICD_ISPENDR12 */
28319  volatile uint32_t GICD_ISPENDR13; /* ALT_GIC_DIST_GICD_ISPENDR13 */
28320  volatile uint32_t GICD_ISPENDR14; /* ALT_GIC_DIST_GICD_ISPENDR14 */
28321  volatile uint32_t GICD_ISPENDR15; /* ALT_GIC_DIST_GICD_ISPENDR15 */
28322  volatile uint32_t _pad_0x240_0x27f[16]; /* *UNDEFINED* */
28323  volatile uint32_t GICD_ICPENDR0; /* ALT_GIC_DIST_GICD_ICPENDR0 */
28324  volatile uint32_t GICD_ICPENDR1; /* ALT_GIC_DIST_GICD_ICPENDR1 */
28325  volatile uint32_t GICD_ICPENDR2; /* ALT_GIC_DIST_GICD_ICPENDR2 */
28326  volatile uint32_t GICD_ICPENDR3; /* ALT_GIC_DIST_GICD_ICPENDR3 */
28327  volatile uint32_t GICD_ICPENDR4; /* ALT_GIC_DIST_GICD_ICPENDR4 */
28328  volatile uint32_t GICD_ICPENDR5; /* ALT_GIC_DIST_GICD_ICPENDR5 */
28329  volatile uint32_t GICD_ICPENDR6; /* ALT_GIC_DIST_GICD_ICPENDR6 */
28330  volatile uint32_t GICD_ICPENDR7; /* ALT_GIC_DIST_GICD_ICPENDR7 */
28331  volatile uint32_t GICD_ICPENDR8; /* ALT_GIC_DIST_GICD_ICPENDR8 */
28332  volatile uint32_t GICD_ICPENDR9; /* ALT_GIC_DIST_GICD_ICPENDR9 */
28333  volatile uint32_t GICD_ICPENDR10; /* ALT_GIC_DIST_GICD_ICPENDR10 */
28334  volatile uint32_t GICD_ICPENDR11; /* ALT_GIC_DIST_GICD_ICPENDR11 */
28335  volatile uint32_t GICD_ICPENDR12; /* ALT_GIC_DIST_GICD_ICPENDR12 */
28336  volatile uint32_t GICD_ICPENDR13; /* ALT_GIC_DIST_GICD_ICPENDR13 */
28337  volatile uint32_t GICD_ICPENDR14; /* ALT_GIC_DIST_GICD_ICPENDR14 */
28338  volatile uint32_t GICD_ICPENDR15; /* ALT_GIC_DIST_GICD_ICPENDR15 */
28339  volatile uint32_t _pad_0x2c0_0x2ff[16]; /* *UNDEFINED* */
28340  volatile uint32_t GICD_ISACTIVER0; /* ALT_GIC_DIST_GICD_ISACTIVER0 */
28341  volatile uint32_t GICD_ISACTIVER1; /* ALT_GIC_DIST_GICD_ISACTIVER1 */
28342  volatile uint32_t GICD_ISACTIVER2; /* ALT_GIC_DIST_GICD_ISACTIVER2 */
28343  volatile uint32_t GICD_ISACTIVER3; /* ALT_GIC_DIST_GICD_ISACTIVER3 */
28344  volatile uint32_t GICD_ISACTIVER4; /* ALT_GIC_DIST_GICD_ISACTIVER4 */
28345  volatile uint32_t GICD_ISACTIVER5; /* ALT_GIC_DIST_GICD_ISACTIVER5 */
28346  volatile uint32_t GICD_ISACTIVER6; /* ALT_GIC_DIST_GICD_ISACTIVER6 */
28347  volatile uint32_t GICD_ISACTIVER7; /* ALT_GIC_DIST_GICD_ISACTIVER7 */
28348  volatile uint32_t GICD_ISACTIVER8; /* ALT_GIC_DIST_GICD_ISACTIVER8 */
28349  volatile uint32_t GICD_ISACTIVER9; /* ALT_GIC_DIST_GICD_ISACTIVER9 */
28350  volatile uint32_t GICD_ISACTIVER10; /* ALT_GIC_DIST_GICD_ISACTIVER10 */
28351  volatile uint32_t GICD_ISACTIVER11; /* ALT_GIC_DIST_GICD_ISACTIVER11 */
28352  volatile uint32_t GICD_ISACTIVER12; /* ALT_GIC_DIST_GICD_ISACTIVER12 */
28353  volatile uint32_t GICD_ISACTIVER13; /* ALT_GIC_DIST_GICD_ISACTIVER13 */
28354  volatile uint32_t GICD_ISACTIVER14; /* ALT_GIC_DIST_GICD_ISACTIVER14 */
28355  volatile uint32_t GICD_ISACTIVER15; /* ALT_GIC_DIST_GICD_ISACTIVER15 */
28356  volatile uint32_t _pad_0x340_0x37f[16]; /* *UNDEFINED* */
28357  volatile uint32_t GICD_ICACTIVER0; /* ALT_GIC_DIST_GICD_ICACTIVER0 */
28358  volatile uint32_t GICD_ICACTIVER1; /* ALT_GIC_DIST_GICD_ICACTIVER1 */
28359  volatile uint32_t GICD_ICACTIVER2; /* ALT_GIC_DIST_GICD_ICACTIVER2 */
28360  volatile uint32_t GICD_ICACTIVER3; /* ALT_GIC_DIST_GICD_ICACTIVER3 */
28361  volatile uint32_t GICD_ICACTIVER4; /* ALT_GIC_DIST_GICD_ICACTIVER4 */
28362  volatile uint32_t GICD_ICACTIVER5; /* ALT_GIC_DIST_GICD_ICACTIVER5 */
28363  volatile uint32_t GICD_ICACTIVER6; /* ALT_GIC_DIST_GICD_ICACTIVER6 */
28364  volatile uint32_t GICD_ICACTIVER7; /* ALT_GIC_DIST_GICD_ICACTIVER7 */
28365  volatile uint32_t GICD_ICACTIVER8; /* ALT_GIC_DIST_GICD_ICACTIVER8 */
28366  volatile uint32_t GICD_ICACTIVER9; /* ALT_GIC_DIST_GICD_ICACTIVER9 */
28367  volatile uint32_t GICD_ICACTIVER10; /* ALT_GIC_DIST_GICD_ICACTIVER10 */
28368  volatile uint32_t GICD_ICACTIVER11; /* ALT_GIC_DIST_GICD_ICACTIVER11 */
28369  volatile uint32_t GICD_ICACTIVER12; /* ALT_GIC_DIST_GICD_ICACTIVER12 */
28370  volatile uint32_t GICD_ICACTIVER13; /* ALT_GIC_DIST_GICD_ICACTIVER13 */
28371  volatile uint32_t GICD_ICACTIVER14; /* ALT_GIC_DIST_GICD_ICACTIVER14 */
28372  volatile uint32_t GICD_ICACTIVER15; /* ALT_GIC_DIST_GICD_ICACTIVER15 */
28373  volatile uint32_t _pad_0x3c0_0x3ff[16]; /* *UNDEFINED* */
28374  volatile uint32_t GICD_IPRIORITYR0; /* ALT_GIC_DIST_GICD_IPRIORITYR0 */
28375  volatile uint32_t GICD_IPRIORITYR1; /* ALT_GIC_DIST_GICD_IPRIORITYR1 */
28376  volatile uint32_t GICD_IPRIORITYR2; /* ALT_GIC_DIST_GICD_IPRIORITYR2 */
28377  volatile uint32_t GICD_IPRIORITYR3; /* ALT_GIC_DIST_GICD_IPRIORITYR3 */
28378  volatile uint32_t GICD_IPRIORITYR4; /* ALT_GIC_DIST_GICD_IPRIORITYR4 */
28379  volatile uint32_t GICD_IPRIORITYR5; /* ALT_GIC_DIST_GICD_IPRIORITYR5 */
28380  volatile uint32_t GICD_IPRIORITYR6; /* ALT_GIC_DIST_GICD_IPRIORITYR6 */
28381  volatile uint32_t GICD_IPRIORITYR7; /* ALT_GIC_DIST_GICD_IPRIORITYR7 */
28382  volatile uint32_t GICD_IPRIORITYR8; /* ALT_GIC_DIST_GICD_IPRIORITYR8 */
28383  volatile uint32_t GICD_IPRIORITYR9; /* ALT_GIC_DIST_GICD_IPRIORITYR9 */
28384  volatile uint32_t GICD_IPRIORITYR10; /* ALT_GIC_DIST_GICD_IPRIORITYR10 */
28385  volatile uint32_t GICD_IPRIORITYR11; /* ALT_GIC_DIST_GICD_IPRIORITYR11 */
28386  volatile uint32_t GICD_IPRIORITYR12; /* ALT_GIC_DIST_GICD_IPRIORITYR12 */
28387  volatile uint32_t GICD_IPRIORITYR13; /* ALT_GIC_DIST_GICD_IPRIORITYR13 */
28388  volatile uint32_t GICD_IPRIORITYR14; /* ALT_GIC_DIST_GICD_IPRIORITYR14 */
28389  volatile uint32_t GICD_IPRIORITYR15; /* ALT_GIC_DIST_GICD_IPRIORITYR15 */
28390  volatile uint32_t GICD_IPRIORITYR16; /* ALT_GIC_DIST_GICD_IPRIORITYR16 */
28391  volatile uint32_t GICD_IPRIORITYR17; /* ALT_GIC_DIST_GICD_IPRIORITYR17 */
28392  volatile uint32_t GICD_IPRIORITYR18; /* ALT_GIC_DIST_GICD_IPRIORITYR18 */
28393  volatile uint32_t GICD_IPRIORITYR19; /* ALT_GIC_DIST_GICD_IPRIORITYR19 */
28394  volatile uint32_t GICD_IPRIORITYR20; /* ALT_GIC_DIST_GICD_IPRIORITYR20 */
28395  volatile uint32_t GICD_IPRIORITYR21; /* ALT_GIC_DIST_GICD_IPRIORITYR21 */
28396  volatile uint32_t GICD_IPRIORITYR22; /* ALT_GIC_DIST_GICD_IPRIORITYR22 */
28397  volatile uint32_t GICD_IPRIORITYR23; /* ALT_GIC_DIST_GICD_IPRIORITYR23 */
28398  volatile uint32_t GICD_IPRIORITYR24; /* ALT_GIC_DIST_GICD_IPRIORITYR24 */
28399  volatile uint32_t GICD_IPRIORITYR25; /* ALT_GIC_DIST_GICD_IPRIORITYR25 */
28400  volatile uint32_t GICD_IPRIORITYR26; /* ALT_GIC_DIST_GICD_IPRIORITYR26 */
28401  volatile uint32_t GICD_IPRIORITYR27; /* ALT_GIC_DIST_GICD_IPRIORITYR27 */
28402  volatile uint32_t GICD_IPRIORITYR28; /* ALT_GIC_DIST_GICD_IPRIORITYR28 */
28403  volatile uint32_t GICD_IPRIORITYR29; /* ALT_GIC_DIST_GICD_IPRIORITYR29 */
28404  volatile uint32_t GICD_IPRIORITYR30; /* ALT_GIC_DIST_GICD_IPRIORITYR30 */
28405  volatile uint32_t GICD_IPRIORITYR31; /* ALT_GIC_DIST_GICD_IPRIORITYR31 */
28406  volatile uint32_t GICD_IPRIORITYR32; /* ALT_GIC_DIST_GICD_IPRIORITYR32 */
28407  volatile uint32_t GICD_IPRIORITYR33; /* ALT_GIC_DIST_GICD_IPRIORITYR33 */
28408  volatile uint32_t GICD_IPRIORITYR34; /* ALT_GIC_DIST_GICD_IPRIORITYR34 */
28409  volatile uint32_t GICD_IPRIORITYR35; /* ALT_GIC_DIST_GICD_IPRIORITYR35 */
28410  volatile uint32_t GICD_IPRIORITYR36; /* ALT_GIC_DIST_GICD_IPRIORITYR36 */
28411  volatile uint32_t GICD_IPRIORITYR37; /* ALT_GIC_DIST_GICD_IPRIORITYR37 */
28412  volatile uint32_t GICD_IPRIORITYR38; /* ALT_GIC_DIST_GICD_IPRIORITYR38 */
28413  volatile uint32_t GICD_IPRIORITYR39; /* ALT_GIC_DIST_GICD_IPRIORITYR39 */
28414  volatile uint32_t GICD_IPRIORITYR40; /* ALT_GIC_DIST_GICD_IPRIORITYR40 */
28415  volatile uint32_t GICD_IPRIORITYR41; /* ALT_GIC_DIST_GICD_IPRIORITYR41 */
28416  volatile uint32_t GICD_IPRIORITYR42; /* ALT_GIC_DIST_GICD_IPRIORITYR42 */
28417  volatile uint32_t GICD_IPRIORITYR43; /* ALT_GIC_DIST_GICD_IPRIORITYR43 */
28418  volatile uint32_t GICD_IPRIORITYR44; /* ALT_GIC_DIST_GICD_IPRIORITYR44 */
28419  volatile uint32_t GICD_IPRIORITYR45; /* ALT_GIC_DIST_GICD_IPRIORITYR45 */
28420  volatile uint32_t GICD_IPRIORITYR46; /* ALT_GIC_DIST_GICD_IPRIORITYR46 */
28421  volatile uint32_t GICD_IPRIORITYR47; /* ALT_GIC_DIST_GICD_IPRIORITYR47 */
28422  volatile uint32_t GICD_IPRIORITYR48; /* ALT_GIC_DIST_GICD_IPRIORITYR48 */
28423  volatile uint32_t GICD_IPRIORITYR49; /* ALT_GIC_DIST_GICD_IPRIORITYR49 */
28424  volatile uint32_t GICD_IPRIORITYR50; /* ALT_GIC_DIST_GICD_IPRIORITYR50 */
28425  volatile uint32_t GICD_IPRIORITYR51; /* ALT_GIC_DIST_GICD_IPRIORITYR51 */
28426  volatile uint32_t GICD_IPRIORITYR52; /* ALT_GIC_DIST_GICD_IPRIORITYR52 */
28427  volatile uint32_t GICD_IPRIORITYR53; /* ALT_GIC_DIST_GICD_IPRIORITYR53 */
28428  volatile uint32_t GICD_IPRIORITYR54; /* ALT_GIC_DIST_GICD_IPRIORITYR54 */
28429  volatile uint32_t GICD_IPRIORITYR55; /* ALT_GIC_DIST_GICD_IPRIORITYR55 */
28430  volatile uint32_t GICD_IPRIORITYR56; /* ALT_GIC_DIST_GICD_IPRIORITYR56 */
28431  volatile uint32_t GICD_IPRIORITYR57; /* ALT_GIC_DIST_GICD_IPRIORITYR57 */
28432  volatile uint32_t GICD_IPRIORITYR58; /* ALT_GIC_DIST_GICD_IPRIORITYR58 */
28433  volatile uint32_t GICD_IPRIORITYR59; /* ALT_GIC_DIST_GICD_IPRIORITYR59 */
28434  volatile uint32_t GICD_IPRIORITYR60; /* ALT_GIC_DIST_GICD_IPRIORITYR60 */
28435  volatile uint32_t GICD_IPRIORITYR61; /* ALT_GIC_DIST_GICD_IPRIORITYR61 */
28436  volatile uint32_t GICD_IPRIORITYR62; /* ALT_GIC_DIST_GICD_IPRIORITYR62 */
28437  volatile uint32_t GICD_IPRIORITYR63; /* ALT_GIC_DIST_GICD_IPRIORITYR63 */
28438  volatile uint32_t GICD_IPRIORITYR64; /* ALT_GIC_DIST_GICD_IPRIORITYR64 */
28439  volatile uint32_t GICD_IPRIORITYR65; /* ALT_GIC_DIST_GICD_IPRIORITYR65 */
28440  volatile uint32_t GICD_IPRIORITYR66; /* ALT_GIC_DIST_GICD_IPRIORITYR66 */
28441  volatile uint32_t GICD_IPRIORITYR67; /* ALT_GIC_DIST_GICD_IPRIORITYR67 */
28442  volatile uint32_t GICD_IPRIORITYR68; /* ALT_GIC_DIST_GICD_IPRIORITYR68 */
28443  volatile uint32_t GICD_IPRIORITYR69; /* ALT_GIC_DIST_GICD_IPRIORITYR69 */
28444  volatile uint32_t GICD_IPRIORITYR70; /* ALT_GIC_DIST_GICD_IPRIORITYR70 */
28445  volatile uint32_t GICD_IPRIORITYR71; /* ALT_GIC_DIST_GICD_IPRIORITYR71 */
28446  volatile uint32_t GICD_IPRIORITYR72; /* ALT_GIC_DIST_GICD_IPRIORITYR72 */
28447  volatile uint32_t GICD_IPRIORITYR73; /* ALT_GIC_DIST_GICD_IPRIORITYR73 */
28448  volatile uint32_t GICD_IPRIORITYR74; /* ALT_GIC_DIST_GICD_IPRIORITYR74 */
28449  volatile uint32_t GICD_IPRIORITYR75; /* ALT_GIC_DIST_GICD_IPRIORITYR75 */
28450  volatile uint32_t GICD_IPRIORITYR76; /* ALT_GIC_DIST_GICD_IPRIORITYR76 */
28451  volatile uint32_t GICD_IPRIORITYR77; /* ALT_GIC_DIST_GICD_IPRIORITYR77 */
28452  volatile uint32_t GICD_IPRIORITYR78; /* ALT_GIC_DIST_GICD_IPRIORITYR78 */
28453  volatile uint32_t GICD_IPRIORITYR79; /* ALT_GIC_DIST_GICD_IPRIORITYR79 */
28454  volatile uint32_t GICD_IPRIORITYR80; /* ALT_GIC_DIST_GICD_IPRIORITYR80 */
28455  volatile uint32_t GICD_IPRIORITYR81; /* ALT_GIC_DIST_GICD_IPRIORITYR81 */
28456  volatile uint32_t GICD_IPRIORITYR82; /* ALT_GIC_DIST_GICD_IPRIORITYR82 */
28457  volatile uint32_t GICD_IPRIORITYR83; /* ALT_GIC_DIST_GICD_IPRIORITYR83 */
28458  volatile uint32_t GICD_IPRIORITYR84; /* ALT_GIC_DIST_GICD_IPRIORITYR84 */
28459  volatile uint32_t GICD_IPRIORITYR85; /* ALT_GIC_DIST_GICD_IPRIORITYR85 */
28460  volatile uint32_t GICD_IPRIORITYR86; /* ALT_GIC_DIST_GICD_IPRIORITYR86 */
28461  volatile uint32_t GICD_IPRIORITYR87; /* ALT_GIC_DIST_GICD_IPRIORITYR87 */
28462  volatile uint32_t GICD_IPRIORITYR88; /* ALT_GIC_DIST_GICD_IPRIORITYR88 */
28463  volatile uint32_t GICD_IPRIORITYR89; /* ALT_GIC_DIST_GICD_IPRIORITYR89 */
28464  volatile uint32_t GICD_IPRIORITYR90; /* ALT_GIC_DIST_GICD_IPRIORITYR90 */
28465  volatile uint32_t GICD_IPRIORITYR91; /* ALT_GIC_DIST_GICD_IPRIORITYR91 */
28466  volatile uint32_t GICD_IPRIORITYR92; /* ALT_GIC_DIST_GICD_IPRIORITYR92 */
28467  volatile uint32_t GICD_IPRIORITYR93; /* ALT_GIC_DIST_GICD_IPRIORITYR93 */
28468  volatile uint32_t GICD_IPRIORITYR94; /* ALT_GIC_DIST_GICD_IPRIORITYR94 */
28469  volatile uint32_t GICD_IPRIORITYR95; /* ALT_GIC_DIST_GICD_IPRIORITYR95 */
28470  volatile uint32_t GICD_IPRIORITYR96; /* ALT_GIC_DIST_GICD_IPRIORITYR96 */
28471  volatile uint32_t GICD_IPRIORITYR97; /* ALT_GIC_DIST_GICD_IPRIORITYR97 */
28472  volatile uint32_t GICD_IPRIORITYR98; /* ALT_GIC_DIST_GICD_IPRIORITYR98 */
28473  volatile uint32_t GICD_IPRIORITYR99; /* ALT_GIC_DIST_GICD_IPRIORITYR99 */
28474  volatile uint32_t GICD_IPRIORITYR100; /* ALT_GIC_DIST_GICD_IPRIORITYR100 */
28475  volatile uint32_t GICD_IPRIORITYR101; /* ALT_GIC_DIST_GICD_IPRIORITYR101 */
28476  volatile uint32_t GICD_IPRIORITYR102; /* ALT_GIC_DIST_GICD_IPRIORITYR102 */
28477  volatile uint32_t GICD_IPRIORITYR103; /* ALT_GIC_DIST_GICD_IPRIORITYR103 */
28478  volatile uint32_t GICD_IPRIORITYR104; /* ALT_GIC_DIST_GICD_IPRIORITYR104 */
28479  volatile uint32_t GICD_IPRIORITYR105; /* ALT_GIC_DIST_GICD_IPRIORITYR105 */
28480  volatile uint32_t GICD_IPRIORITYR106; /* ALT_GIC_DIST_GICD_IPRIORITYR106 */
28481  volatile uint32_t GICD_IPRIORITYR107; /* ALT_GIC_DIST_GICD_IPRIORITYR107 */
28482  volatile uint32_t GICD_IPRIORITYR108; /* ALT_GIC_DIST_GICD_IPRIORITYR108 */
28483  volatile uint32_t GICD_IPRIORITYR109; /* ALT_GIC_DIST_GICD_IPRIORITYR109 */
28484  volatile uint32_t GICD_IPRIORITYR110; /* ALT_GIC_DIST_GICD_IPRIORITYR110 */
28485  volatile uint32_t GICD_IPRIORITYR111; /* ALT_GIC_DIST_GICD_IPRIORITYR111 */
28486  volatile uint32_t GICD_IPRIORITYR112; /* ALT_GIC_DIST_GICD_IPRIORITYR112 */
28487  volatile uint32_t GICD_IPRIORITYR113; /* ALT_GIC_DIST_GICD_IPRIORITYR113 */
28488  volatile uint32_t GICD_IPRIORITYR114; /* ALT_GIC_DIST_GICD_IPRIORITYR114 */
28489  volatile uint32_t GICD_IPRIORITYR115; /* ALT_GIC_DIST_GICD_IPRIORITYR115 */
28490  volatile uint32_t GICD_IPRIORITYR116; /* ALT_GIC_DIST_GICD_IPRIORITYR116 */
28491  volatile uint32_t GICD_IPRIORITYR117; /* ALT_GIC_DIST_GICD_IPRIORITYR117 */
28492  volatile uint32_t GICD_IPRIORITYR118; /* ALT_GIC_DIST_GICD_IPRIORITYR118 */
28493  volatile uint32_t GICD_IPRIORITYR119; /* ALT_GIC_DIST_GICD_IPRIORITYR119 */
28494  volatile uint32_t GICD_IPRIORITYR120; /* ALT_GIC_DIST_GICD_IPRIORITYR120 */
28495  volatile uint32_t GICD_IPRIORITYR121; /* ALT_GIC_DIST_GICD_IPRIORITYR121 */
28496  volatile uint32_t GICD_IPRIORITYR122; /* ALT_GIC_DIST_GICD_IPRIORITYR122 */
28497  volatile uint32_t GICD_IPRIORITYR123; /* ALT_GIC_DIST_GICD_IPRIORITYR123 */
28498  volatile uint32_t GICD_IPRIORITYR124; /* ALT_GIC_DIST_GICD_IPRIORITYR124 */
28499  volatile uint32_t GICD_IPRIORITYR125; /* ALT_GIC_DIST_GICD_IPRIORITYR125 */
28500  volatile uint32_t GICD_IPRIORITYR126; /* ALT_GIC_DIST_GICD_IPRIORITYR126 */
28501  volatile uint32_t GICD_IPRIORITYR127; /* ALT_GIC_DIST_GICD_IPRIORITYR127 */
28502  volatile uint32_t _pad_0x600_0x7ff[128]; /* *UNDEFINED* */
28503  volatile uint32_t GICD_ITARGETSR0; /* ALT_GIC_DIST_GICD_ITARGETSR0 */
28504  volatile uint32_t GICD_ITARGETSR1; /* ALT_GIC_DIST_GICD_ITARGETSR1 */
28505  volatile uint32_t GICD_ITARGETSR2; /* ALT_GIC_DIST_GICD_ITARGETSR2 */
28506  volatile uint32_t GICD_ITARGETSR3; /* ALT_GIC_DIST_GICD_ITARGETSR3 */
28507  volatile uint32_t GICD_ITARGETSR4; /* ALT_GIC_DIST_GICD_ITARGETSR4 */
28508  volatile uint32_t GICD_ITARGETSR5; /* ALT_GIC_DIST_GICD_ITARGETSR5 */
28509  volatile uint32_t GICD_ITARGETSR6; /* ALT_GIC_DIST_GICD_ITARGETSR6 */
28510  volatile uint32_t GICD_ITARGETSR7; /* ALT_GIC_DIST_GICD_ITARGETSR7 */
28511  volatile uint32_t GICD_ITARGETSR8; /* ALT_GIC_DIST_GICD_ITARGETSR8 */
28512  volatile uint32_t GICD_ITARGETSR9; /* ALT_GIC_DIST_GICD_ITARGETSR9 */
28513  volatile uint32_t GICD_ITARGETSR10; /* ALT_GIC_DIST_GICD_ITARGETSR10 */
28514  volatile uint32_t GICD_ITARGETSR11; /* ALT_GIC_DIST_GICD_ITARGETSR11 */
28515  volatile uint32_t GICD_ITARGETSR12; /* ALT_GIC_DIST_GICD_ITARGETSR12 */
28516  volatile uint32_t GICD_ITARGETSR13; /* ALT_GIC_DIST_GICD_ITARGETSR13 */
28517  volatile uint32_t GICD_ITARGETSR14; /* ALT_GIC_DIST_GICD_ITARGETSR14 */
28518  volatile uint32_t GICD_ITARGETSR15; /* ALT_GIC_DIST_GICD_ITARGETSR15 */
28519  volatile uint32_t GICD_ITARGETSR16; /* ALT_GIC_DIST_GICD_ITARGETSR16 */
28520  volatile uint32_t GICD_ITARGETSR17; /* ALT_GIC_DIST_GICD_ITARGETSR17 */
28521  volatile uint32_t GICD_ITARGETSR18; /* ALT_GIC_DIST_GICD_ITARGETSR18 */
28522  volatile uint32_t GICD_ITARGETSR19; /* ALT_GIC_DIST_GICD_ITARGETSR19 */
28523  volatile uint32_t GICD_ITARGETSR20; /* ALT_GIC_DIST_GICD_ITARGETSR20 */
28524  volatile uint32_t GICD_ITARGETSR21; /* ALT_GIC_DIST_GICD_ITARGETSR21 */
28525  volatile uint32_t GICD_ITARGETSR22; /* ALT_GIC_DIST_GICD_ITARGETSR22 */
28526  volatile uint32_t GICD_ITARGETSR23; /* ALT_GIC_DIST_GICD_ITARGETSR23 */
28527  volatile uint32_t GICD_ITARGETSR24; /* ALT_GIC_DIST_GICD_ITARGETSR24 */
28528  volatile uint32_t GICD_ITARGETSR25; /* ALT_GIC_DIST_GICD_ITARGETSR25 */
28529  volatile uint32_t GICD_ITARGETSR26; /* ALT_GIC_DIST_GICD_ITARGETSR26 */
28530  volatile uint32_t GICD_ITARGETSR27; /* ALT_GIC_DIST_GICD_ITARGETSR27 */
28531  volatile uint32_t GICD_ITARGETSR28; /* ALT_GIC_DIST_GICD_ITARGETSR28 */
28532  volatile uint32_t GICD_ITARGETSR29; /* ALT_GIC_DIST_GICD_ITARGETSR29 */
28533  volatile uint32_t GICD_ITARGETSR30; /* ALT_GIC_DIST_GICD_ITARGETSR30 */
28534  volatile uint32_t GICD_ITARGETSR31; /* ALT_GIC_DIST_GICD_ITARGETSR31 */
28535  volatile uint32_t GICD_ITARGETSR32; /* ALT_GIC_DIST_GICD_ITARGETSR32 */
28536  volatile uint32_t GICD_ITARGETSR33; /* ALT_GIC_DIST_GICD_ITARGETSR33 */
28537  volatile uint32_t GICD_ITARGETSR34; /* ALT_GIC_DIST_GICD_ITARGETSR34 */
28538  volatile uint32_t GICD_ITARGETSR35; /* ALT_GIC_DIST_GICD_ITARGETSR35 */
28539  volatile uint32_t GICD_ITARGETSR36; /* ALT_GIC_DIST_GICD_ITARGETSR36 */
28540  volatile uint32_t GICD_ITARGETSR37; /* ALT_GIC_DIST_GICD_ITARGETSR37 */
28541  volatile uint32_t GICD_ITARGETSR38; /* ALT_GIC_DIST_GICD_ITARGETSR38 */
28542  volatile uint32_t GICD_ITARGETSR39; /* ALT_GIC_DIST_GICD_ITARGETSR39 */
28543  volatile uint32_t GICD_ITARGETSR40; /* ALT_GIC_DIST_GICD_ITARGETSR40 */
28544  volatile uint32_t GICD_ITARGETSR41; /* ALT_GIC_DIST_GICD_ITARGETSR41 */
28545  volatile uint32_t GICD_ITARGETSR42; /* ALT_GIC_DIST_GICD_ITARGETSR42 */
28546  volatile uint32_t GICD_ITARGETSR43; /* ALT_GIC_DIST_GICD_ITARGETSR43 */
28547  volatile uint32_t GICD_ITARGETSR44; /* ALT_GIC_DIST_GICD_ITARGETSR44 */
28548  volatile uint32_t GICD_ITARGETSR45; /* ALT_GIC_DIST_GICD_ITARGETSR45 */
28549  volatile uint32_t GICD_ITARGETSR46; /* ALT_GIC_DIST_GICD_ITARGETSR46 */
28550  volatile uint32_t GICD_ITARGETSR47; /* ALT_GIC_DIST_GICD_ITARGETSR47 */
28551  volatile uint32_t GICD_ITARGETSR48; /* ALT_GIC_DIST_GICD_ITARGETSR48 */
28552  volatile uint32_t GICD_ITARGETSR49; /* ALT_GIC_DIST_GICD_ITARGETSR49 */
28553  volatile uint32_t GICD_ITARGETSR50; /* ALT_GIC_DIST_GICD_ITARGETSR50 */
28554  volatile uint32_t GICD_ITARGETSR51; /* ALT_GIC_DIST_GICD_ITARGETSR51 */
28555  volatile uint32_t GICD_ITARGETSR52; /* ALT_GIC_DIST_GICD_ITARGETSR52 */
28556  volatile uint32_t GICD_ITARGETSR53; /* ALT_GIC_DIST_GICD_ITARGETSR53 */
28557  volatile uint32_t GICD_ITARGETSR54; /* ALT_GIC_DIST_GICD_ITARGETSR54 */
28558  volatile uint32_t GICD_ITARGETSR55; /* ALT_GIC_DIST_GICD_ITARGETSR55 */
28559  volatile uint32_t GICD_ITARGETSR56; /* ALT_GIC_DIST_GICD_ITARGETSR56 */
28560  volatile uint32_t GICD_ITARGETSR57; /* ALT_GIC_DIST_GICD_ITARGETSR57 */
28561  volatile uint32_t GICD_ITARGETSR58; /* ALT_GIC_DIST_GICD_ITARGETSR58 */
28562  volatile uint32_t GICD_ITARGETSR59; /* ALT_GIC_DIST_GICD_ITARGETSR59 */
28563  volatile uint32_t GICD_ITARGETSR60; /* ALT_GIC_DIST_GICD_ITARGETSR60 */
28564  volatile uint32_t GICD_ITARGETSR61; /* ALT_GIC_DIST_GICD_ITARGETSR61 */
28565  volatile uint32_t GICD_ITARGETSR62; /* ALT_GIC_DIST_GICD_ITARGETSR62 */
28566  volatile uint32_t GICD_ITARGETSR63; /* ALT_GIC_DIST_GICD_ITARGETSR63 */
28567  volatile uint32_t GICD_ITARGETSR64; /* ALT_GIC_DIST_GICD_ITARGETSR64 */
28568  volatile uint32_t GICD_ITARGETSR65; /* ALT_GIC_DIST_GICD_ITARGETSR65 */
28569  volatile uint32_t GICD_ITARGETSR66; /* ALT_GIC_DIST_GICD_ITARGETSR66 */
28570  volatile uint32_t GICD_ITARGETSR67; /* ALT_GIC_DIST_GICD_ITARGETSR67 */
28571  volatile uint32_t GICD_ITARGETSR68; /* ALT_GIC_DIST_GICD_ITARGETSR68 */
28572  volatile uint32_t GICD_ITARGETSR69; /* ALT_GIC_DIST_GICD_ITARGETSR69 */
28573  volatile uint32_t GICD_ITARGETSR70; /* ALT_GIC_DIST_GICD_ITARGETSR70 */
28574  volatile uint32_t GICD_ITARGETSR71; /* ALT_GIC_DIST_GICD_ITARGETSR71 */
28575  volatile uint32_t GICD_ITARGETSR72; /* ALT_GIC_DIST_GICD_ITARGETSR72 */
28576  volatile uint32_t GICD_ITARGETSR73; /* ALT_GIC_DIST_GICD_ITARGETSR73 */
28577  volatile uint32_t GICD_ITARGETSR74; /* ALT_GIC_DIST_GICD_ITARGETSR74 */
28578  volatile uint32_t GICD_ITARGETSR75; /* ALT_GIC_DIST_GICD_ITARGETSR75 */
28579  volatile uint32_t GICD_ITARGETSR76; /* ALT_GIC_DIST_GICD_ITARGETSR76 */
28580  volatile uint32_t GICD_ITARGETSR77; /* ALT_GIC_DIST_GICD_ITARGETSR77 */
28581  volatile uint32_t GICD_ITARGETSR78; /* ALT_GIC_DIST_GICD_ITARGETSR78 */
28582  volatile uint32_t GICD_ITARGETSR79; /* ALT_GIC_DIST_GICD_ITARGETSR79 */
28583  volatile uint32_t GICD_ITARGETSR80; /* ALT_GIC_DIST_GICD_ITARGETSR80 */
28584  volatile uint32_t GICD_ITARGETSR81; /* ALT_GIC_DIST_GICD_ITARGETSR81 */
28585  volatile uint32_t GICD_ITARGETSR82; /* ALT_GIC_DIST_GICD_ITARGETSR82 */
28586  volatile uint32_t GICD_ITARGETSR83; /* ALT_GIC_DIST_GICD_ITARGETSR83 */
28587  volatile uint32_t GICD_ITARGETSR84; /* ALT_GIC_DIST_GICD_ITARGETSR84 */
28588  volatile uint32_t GICD_ITARGETSR85; /* ALT_GIC_DIST_GICD_ITARGETSR85 */
28589  volatile uint32_t GICD_ITARGETSR86; /* ALT_GIC_DIST_GICD_ITARGETSR86 */
28590  volatile uint32_t GICD_ITARGETSR87; /* ALT_GIC_DIST_GICD_ITARGETSR87 */
28591  volatile uint32_t GICD_ITARGETSR88; /* ALT_GIC_DIST_GICD_ITARGETSR88 */
28592  volatile uint32_t GICD_ITARGETSR89; /* ALT_GIC_DIST_GICD_ITARGETSR89 */
28593  volatile uint32_t GICD_ITARGETSR90; /* ALT_GIC_DIST_GICD_ITARGETSR90 */
28594  volatile uint32_t GICD_ITARGETSR91; /* ALT_GIC_DIST_GICD_ITARGETSR91 */
28595  volatile uint32_t GICD_ITARGETSR92; /* ALT_GIC_DIST_GICD_ITARGETSR92 */
28596  volatile uint32_t GICD_ITARGETSR93; /* ALT_GIC_DIST_GICD_ITARGETSR93 */
28597  volatile uint32_t GICD_ITARGETSR94; /* ALT_GIC_DIST_GICD_ITARGETSR94 */
28598  volatile uint32_t GICD_ITARGETSR95; /* ALT_GIC_DIST_GICD_ITARGETSR95 */
28599  volatile uint32_t GICD_ITARGETSR96; /* ALT_GIC_DIST_GICD_ITARGETSR96 */
28600  volatile uint32_t GICD_ITARGETSR97; /* ALT_GIC_DIST_GICD_ITARGETSR97 */
28601  volatile uint32_t GICD_ITARGETSR98; /* ALT_GIC_DIST_GICD_ITARGETSR98 */
28602  volatile uint32_t GICD_ITARGETSR99; /* ALT_GIC_DIST_GICD_ITARGETSR99 */
28603  volatile uint32_t GICD_ITARGETSR100; /* ALT_GIC_DIST_GICD_ITARGETSR100 */
28604  volatile uint32_t GICD_ITARGETSR101; /* ALT_GIC_DIST_GICD_ITARGETSR101 */
28605  volatile uint32_t GICD_ITARGETSR102; /* ALT_GIC_DIST_GICD_ITARGETSR102 */
28606  volatile uint32_t GICD_ITARGETSR103; /* ALT_GIC_DIST_GICD_ITARGETSR103 */
28607  volatile uint32_t GICD_ITARGETSR104; /* ALT_GIC_DIST_GICD_ITARGETSR104 */
28608  volatile uint32_t GICD_ITARGETSR105; /* ALT_GIC_DIST_GICD_ITARGETSR105 */
28609  volatile uint32_t GICD_ITARGETSR106; /* ALT_GIC_DIST_GICD_ITARGETSR106 */
28610  volatile uint32_t GICD_ITARGETSR107; /* ALT_GIC_DIST_GICD_ITARGETSR107 */
28611  volatile uint32_t GICD_ITARGETSR108; /* ALT_GIC_DIST_GICD_ITARGETSR108 */
28612  volatile uint32_t GICD_ITARGETSR109; /* ALT_GIC_DIST_GICD_ITARGETSR109 */
28613  volatile uint32_t GICD_ITARGETSR110; /* ALT_GIC_DIST_GICD_ITARGETSR110 */
28614  volatile uint32_t GICD_ITARGETSR111; /* ALT_GIC_DIST_GICD_ITARGETSR111 */
28615  volatile uint32_t GICD_ITARGETSR112; /* ALT_GIC_DIST_GICD_ITARGETSR112 */
28616  volatile uint32_t GICD_ITARGETSR113; /* ALT_GIC_DIST_GICD_ITARGETSR113 */
28617  volatile uint32_t GICD_ITARGETSR114; /* ALT_GIC_DIST_GICD_ITARGETSR114 */
28618  volatile uint32_t GICD_ITARGETSR115; /* ALT_GIC_DIST_GICD_ITARGETSR115 */
28619  volatile uint32_t GICD_ITARGETSR116; /* ALT_GIC_DIST_GICD_ITARGETSR116 */
28620  volatile uint32_t GICD_ITARGETSR117; /* ALT_GIC_DIST_GICD_ITARGETSR117 */
28621  volatile uint32_t GICD_ITARGETSR118; /* ALT_GIC_DIST_GICD_ITARGETSR118 */
28622  volatile uint32_t GICD_ITARGETSR119; /* ALT_GIC_DIST_GICD_ITARGETSR119 */
28623  volatile uint32_t GICD_ITARGETSR120; /* ALT_GIC_DIST_GICD_ITARGETSR120 */
28624  volatile uint32_t GICD_ITARGETSR121; /* ALT_GIC_DIST_GICD_ITARGETSR121 */
28625  volatile uint32_t GICD_ITARGETSR122; /* ALT_GIC_DIST_GICD_ITARGETSR122 */
28626  volatile uint32_t GICD_ITARGETSR123; /* ALT_GIC_DIST_GICD_ITARGETSR123 */
28627  volatile uint32_t GICD_ITARGETSR124; /* ALT_GIC_DIST_GICD_ITARGETSR124 */
28628  volatile uint32_t GICD_ITARGETSR125; /* ALT_GIC_DIST_GICD_ITARGETSR125 */
28629  volatile uint32_t GICD_ITARGETSR126; /* ALT_GIC_DIST_GICD_ITARGETSR126 */
28630  volatile uint32_t GICD_ITARGETSR127; /* ALT_GIC_DIST_GICD_ITARGETSR127 */
28631  volatile uint32_t _pad_0xa00_0xbff[128]; /* *UNDEFINED* */
28632  volatile uint32_t GICD_ICFGR0; /* ALT_GIC_DIST_GICD_ICFGR0 */
28633  volatile uint32_t GICD_ICFGR1; /* ALT_GIC_DIST_GICD_ICFGR1 */
28634  volatile uint32_t GICD_ICFGR2; /* ALT_GIC_DIST_GICD_ICFGR2 */
28635  volatile uint32_t GICD_ICFGR3; /* ALT_GIC_DIST_GICD_ICFGR3 */
28636  volatile uint32_t GICD_ICFGR4; /* ALT_GIC_DIST_GICD_ICFGR4 */
28637  volatile uint32_t GICD_ICFGR5; /* ALT_GIC_DIST_GICD_ICFGR5 */
28638  volatile uint32_t GICD_ICFGR6; /* ALT_GIC_DIST_GICD_ICFGR6 */
28639  volatile uint32_t GICD_ICFGR7; /* ALT_GIC_DIST_GICD_ICFGR7 */
28640  volatile uint32_t GICD_ICFGR8; /* ALT_GIC_DIST_GICD_ICFGR8 */
28641  volatile uint32_t GICD_ICFGR9; /* ALT_GIC_DIST_GICD_ICFGR9 */
28642  volatile uint32_t GICD_ICFGR10; /* ALT_GIC_DIST_GICD_ICFGR10 */
28643  volatile uint32_t GICD_ICFGR11; /* ALT_GIC_DIST_GICD_ICFGR11 */
28644  volatile uint32_t GICD_ICFGR12; /* ALT_GIC_DIST_GICD_ICFGR12 */
28645  volatile uint32_t GICD_ICFGR13; /* ALT_GIC_DIST_GICD_ICFGR13 */
28646  volatile uint32_t GICD_ICFGR14; /* ALT_GIC_DIST_GICD_ICFGR14 */
28647  volatile uint32_t GICD_ICFGR15; /* ALT_GIC_DIST_GICD_ICFGR15 */
28648  volatile uint32_t GICD_ICFGR16; /* ALT_GIC_DIST_GICD_ICFGR16 */
28649  volatile uint32_t GICD_ICFGR17; /* ALT_GIC_DIST_GICD_ICFGR17 */
28650  volatile uint32_t GICD_ICFGR18; /* ALT_GIC_DIST_GICD_ICFGR18 */
28651  volatile uint32_t GICD_ICFGR19; /* ALT_GIC_DIST_GICD_ICFGR19 */
28652  volatile uint32_t GICD_ICFGR20; /* ALT_GIC_DIST_GICD_ICFGR20 */
28653  volatile uint32_t GICD_ICFGR21; /* ALT_GIC_DIST_GICD_ICFGR21 */
28654  volatile uint32_t GICD_ICFGR22; /* ALT_GIC_DIST_GICD_ICFGR22 */
28655  volatile uint32_t GICD_ICFGR23; /* ALT_GIC_DIST_GICD_ICFGR23 */
28656  volatile uint32_t GICD_ICFGR24; /* ALT_GIC_DIST_GICD_ICFGR24 */
28657  volatile uint32_t GICD_ICFGR25; /* ALT_GIC_DIST_GICD_ICFGR25 */
28658  volatile uint32_t GICD_ICFGR26; /* ALT_GIC_DIST_GICD_ICFGR26 */
28659  volatile uint32_t GICD_ICFGR27; /* ALT_GIC_DIST_GICD_ICFGR27 */
28660  volatile uint32_t GICD_ICFGR28; /* ALT_GIC_DIST_GICD_ICFGR28 */
28661  volatile uint32_t GICD_ICFGR29; /* ALT_GIC_DIST_GICD_ICFGR29 */
28662  volatile uint32_t GICD_ICFGR30; /* ALT_GIC_DIST_GICD_ICFGR30 */
28663  volatile uint32_t GICD_ICFGR31; /* ALT_GIC_DIST_GICD_ICFGR31 */
28664  volatile uint32_t _pad_0xc80_0xcff[32]; /* *UNDEFINED* */
28665  volatile uint32_t GICD_PPISR; /* ALT_GIC_DIST_GICD_PPISR */
28666  volatile uint32_t GICD_SPISR0; /* ALT_GIC_DIST_GICD_SPISR0 */
28667  volatile uint32_t GICD_SPISR1; /* ALT_GIC_DIST_GICD_SPISR1 */
28668  volatile uint32_t GICD_SPISR2; /* ALT_GIC_DIST_GICD_SPISR2 */
28669  volatile uint32_t GICD_SPISR3; /* ALT_GIC_DIST_GICD_SPISR3 */
28670  volatile uint32_t GICD_SPISR4; /* ALT_GIC_DIST_GICD_SPISR4 */
28671  volatile uint32_t GICD_SPISR5; /* ALT_GIC_DIST_GICD_SPISR5 */
28672  volatile uint32_t GICD_SPISR6; /* ALT_GIC_DIST_GICD_SPISR6 */
28673  volatile uint32_t GICD_SPISR7; /* ALT_GIC_DIST_GICD_SPISR7 */
28674  volatile uint32_t GICD_SPISR8; /* ALT_GIC_DIST_GICD_SPISR8 */
28675  volatile uint32_t GICD_SPISR9; /* ALT_GIC_DIST_GICD_SPISR9 */
28676  volatile uint32_t GICD_SPISR10; /* ALT_GIC_DIST_GICD_SPISR10 */
28677  volatile uint32_t GICD_SPISR11; /* ALT_GIC_DIST_GICD_SPISR11 */
28678  volatile uint32_t GICD_SPISR12; /* ALT_GIC_DIST_GICD_SPISR12 */
28679  volatile uint32_t GICD_SPISR13; /* ALT_GIC_DIST_GICD_SPISR13 */
28680  volatile uint32_t GICD_SPISR14; /* ALT_GIC_DIST_GICD_SPISR14 */
28681  volatile uint32_t _pad_0xd40_0xeff[112]; /* *UNDEFINED* */
28682  volatile uint32_t GICD_SGIR; /* ALT_GIC_DIST_GICD_SGIR */
28683  volatile uint32_t _pad_0xf04_0xf0f[3]; /* *UNDEFINED* */
28684  volatile uint32_t GICD_CPENDSGIR0; /* ALT_GIC_DIST_GICD_CPENDSGIR0 */
28685  volatile uint32_t GICD_CPENDSGIR1; /* ALT_GIC_DIST_GICD_CPENDSGIR1 */
28686  volatile uint32_t GICD_CPENDSGIR2; /* ALT_GIC_DIST_GICD_CPENDSGIR2 */
28687  volatile uint32_t GICD_CPENDSGIR3; /* ALT_GIC_DIST_GICD_CPENDSGIR3 */
28688  volatile uint32_t GICD_SPENDSGIR0; /* ALT_GIC_DIST_GICD_SPENDSGIR0 */
28689  volatile uint32_t GICD_SPENDSGIR1; /* ALT_GIC_DIST_GICD_SPENDSGIR1 */
28690  volatile uint32_t GICD_SPENDSGIR2; /* ALT_GIC_DIST_GICD_SPENDSGIR2 */
28691  volatile uint32_t GICD_SPENDSGIR3; /* ALT_GIC_DIST_GICD_SPENDSGIR3 */
28692  volatile uint32_t _pad_0xf30_0xfcf[40]; /* *UNDEFINED* */
28693  volatile uint32_t GICD_PIDR4; /* ALT_GIC_DIST_GICD_PIDR4 */
28694  volatile uint32_t GICD_PIDR5; /* ALT_GIC_DIST_GICD_PIDR5 */
28695  volatile uint32_t GICD_PIDR6; /* ALT_GIC_DIST_GICD_PIDR6 */
28696  volatile uint32_t GICD_PIDR7; /* ALT_GIC_DIST_GICD_PIDR7 */
28697  volatile uint32_t GICD_PIDR0; /* ALT_GIC_DIST_GICD_PIDR0 */
28698  volatile uint32_t GICD_PIDR1; /* ALT_GIC_DIST_GICD_PIDR1 */
28699  volatile uint32_t GICD_PIDR2; /* ALT_GIC_DIST_GICD_PIDR2 */
28700  volatile uint32_t GICD_PIDR3; /* ALT_GIC_DIST_GICD_PIDR3 */
28701  volatile uint32_t GICD_CIDR0; /* ALT_GIC_DIST_GICD_CIDR0 */
28702  volatile uint32_t GICD_CIDR1; /* ALT_GIC_DIST_GICD_CIDR1 */
28703  volatile uint32_t GICD_CIDR2; /* ALT_GIC_DIST_GICD_CIDR2 */
28704  volatile uint32_t GICD_CIDR3; /* ALT_GIC_DIST_GICD_CIDR3 */
28705 };
28706 
28707 /* The typedef declaration for the raw register contents of register group ALT_GIC_DIST. */
28708 typedef struct ALT_GIC_DIST_raw_s ALT_GIC_DIST_raw_t;
28709 #endif /* __ASSEMBLY__ */
28710 
28711 
28712 /*
28713  * Component : CPU interface memory map - GIC_CPUIF
28714  * CPU interface memory map
28715  *
28716  * Memory map for the GIC CPU interface blocks. Contains all registers with the
28717  * GICC prefix. Note: The CPU interface block for each CPU is separate.
28718  *
28719  */
28720 /*
28721  * Register : GICC_CTLR
28722  *
28723  * CPU Interface Control Register
28724  *
28725  * Register Layout
28726  *
28727  * Bits | Access | Reset | Description
28728  * :-------|:-------|:--------|:------------
28729  * [31:0] | RW | Unknown | Empty
28730  *
28731  */
28732 /*
28733  * Field : Empty - fld
28734  *
28735  * Placeholder
28736  *
28737  * Field Access Macros:
28738  *
28739  */
28740 /* The Least Significant Bit (LSB) position of the ALT_GIC_CPUIF_GICC_CTLR_FLD register field. */
28741 #define ALT_GIC_CPUIF_GICC_CTLR_FLD_LSB 0
28742 /* The Most Significant Bit (MSB) position of the ALT_GIC_CPUIF_GICC_CTLR_FLD register field. */
28743 #define ALT_GIC_CPUIF_GICC_CTLR_FLD_MSB 31
28744 /* The width in bits of the ALT_GIC_CPUIF_GICC_CTLR_FLD register field. */
28745 #define ALT_GIC_CPUIF_GICC_CTLR_FLD_WIDTH 32
28746 /* The mask used to set the ALT_GIC_CPUIF_GICC_CTLR_FLD register field value. */
28747 #define ALT_GIC_CPUIF_GICC_CTLR_FLD_SET_MSK 0xffffffff
28748 /* The mask used to clear the ALT_GIC_CPUIF_GICC_CTLR_FLD register field value. */
28749 #define ALT_GIC_CPUIF_GICC_CTLR_FLD_CLR_MSK 0x00000000
28750 /* The reset value of the ALT_GIC_CPUIF_GICC_CTLR_FLD register field is UNKNOWN. */
28751 #define ALT_GIC_CPUIF_GICC_CTLR_FLD_RESET 0x0
28752 /* Extracts the ALT_GIC_CPUIF_GICC_CTLR_FLD field value from a register. */
28753 #define ALT_GIC_CPUIF_GICC_CTLR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
28754 /* Produces a ALT_GIC_CPUIF_GICC_CTLR_FLD register field value suitable for setting the register. */
28755 #define ALT_GIC_CPUIF_GICC_CTLR_FLD_SET(value) (((value) << 0) & 0xffffffff)
28756 
28757 #ifndef __ASSEMBLY__
28758 /*
28759  * WARNING: The C register and register group struct declarations are provided for
28760  * convenience and illustrative purposes. They should, however, be used with
28761  * caution as the C language standard provides no guarantees about the alignment or
28762  * atomicity of device memory accesses. The recommended practice for coding device
28763  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
28764  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
28765  * alt_write_dword() functions for 64 bit registers.
28766  *
28767  * The struct declaration for register ALT_GIC_CPUIF_GICC_CTLR.
28768  */
28769 struct ALT_GIC_CPUIF_GICC_CTLR_s
28770 {
28771  volatile uint32_t fld : 32; /* Empty */
28772 };
28773 
28774 /* The typedef declaration for register ALT_GIC_CPUIF_GICC_CTLR. */
28775 typedef struct ALT_GIC_CPUIF_GICC_CTLR_s ALT_GIC_CPUIF_GICC_CTLR_t;
28776 #endif /* __ASSEMBLY__ */
28777 
28778 /* The reset value of the ALT_GIC_CPUIF_GICC_CTLR register. */
28779 #define ALT_GIC_CPUIF_GICC_CTLR_RESET 0x00000000
28780 /* The byte offset of the ALT_GIC_CPUIF_GICC_CTLR register from the beginning of the component. */
28781 #define ALT_GIC_CPUIF_GICC_CTLR_OFST 0x0
28782 
28783 /*
28784  * Register : GICC_PMR
28785  *
28786  * Interrupt Priority Mask Register
28787  *
28788  * Register Layout
28789  *
28790  * Bits | Access | Reset | Description
28791  * :-------|:-------|:--------|:------------
28792  * [31:0] | RW | Unknown | Empty
28793  *
28794  */
28795 /*
28796  * Field : Empty - fld
28797  *
28798  * Placeholder
28799  *
28800  * Field Access Macros:
28801  *
28802  */
28803 /* The Least Significant Bit (LSB) position of the ALT_GIC_CPUIF_GICC_PMR_FLD register field. */
28804 #define ALT_GIC_CPUIF_GICC_PMR_FLD_LSB 0
28805 /* The Most Significant Bit (MSB) position of the ALT_GIC_CPUIF_GICC_PMR_FLD register field. */
28806 #define ALT_GIC_CPUIF_GICC_PMR_FLD_MSB 31
28807 /* The width in bits of the ALT_GIC_CPUIF_GICC_PMR_FLD register field. */
28808 #define ALT_GIC_CPUIF_GICC_PMR_FLD_WIDTH 32
28809 /* The mask used to set the ALT_GIC_CPUIF_GICC_PMR_FLD register field value. */
28810 #define ALT_GIC_CPUIF_GICC_PMR_FLD_SET_MSK 0xffffffff
28811 /* The mask used to clear the ALT_GIC_CPUIF_GICC_PMR_FLD register field value. */
28812 #define ALT_GIC_CPUIF_GICC_PMR_FLD_CLR_MSK 0x00000000
28813 /* The reset value of the ALT_GIC_CPUIF_GICC_PMR_FLD register field is UNKNOWN. */
28814 #define ALT_GIC_CPUIF_GICC_PMR_FLD_RESET 0x0
28815 /* Extracts the ALT_GIC_CPUIF_GICC_PMR_FLD field value from a register. */
28816 #define ALT_GIC_CPUIF_GICC_PMR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
28817 /* Produces a ALT_GIC_CPUIF_GICC_PMR_FLD register field value suitable for setting the register. */
28818 #define ALT_GIC_CPUIF_GICC_PMR_FLD_SET(value) (((value) << 0) & 0xffffffff)
28819 
28820 #ifndef __ASSEMBLY__
28821 /*
28822  * WARNING: The C register and register group struct declarations are provided for
28823  * convenience and illustrative purposes. They should, however, be used with
28824  * caution as the C language standard provides no guarantees about the alignment or
28825  * atomicity of device memory accesses. The recommended practice for coding device
28826  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
28827  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
28828  * alt_write_dword() functions for 64 bit registers.
28829  *
28830  * The struct declaration for register ALT_GIC_CPUIF_GICC_PMR.
28831  */
28832 struct ALT_GIC_CPUIF_GICC_PMR_s
28833 {
28834  volatile uint32_t fld : 32; /* Empty */
28835 };
28836 
28837 /* The typedef declaration for register ALT_GIC_CPUIF_GICC_PMR. */
28838 typedef struct ALT_GIC_CPUIF_GICC_PMR_s ALT_GIC_CPUIF_GICC_PMR_t;
28839 #endif /* __ASSEMBLY__ */
28840 
28841 /* The reset value of the ALT_GIC_CPUIF_GICC_PMR register. */
28842 #define ALT_GIC_CPUIF_GICC_PMR_RESET 0x00000000
28843 /* The byte offset of the ALT_GIC_CPUIF_GICC_PMR register from the beginning of the component. */
28844 #define ALT_GIC_CPUIF_GICC_PMR_OFST 0x4
28845 
28846 /*
28847  * Register : GICC_BPR
28848  *
28849  * Binary Point Register
28850  *
28851  * Register Layout
28852  *
28853  * Bits | Access | Reset | Description
28854  * :-------|:-------|:--------|:------------
28855  * [31:0] | RW | Unknown | Empty
28856  *
28857  */
28858 /*
28859  * Field : Empty - fld
28860  *
28861  * Placeholder
28862  *
28863  * Field Access Macros:
28864  *
28865  */
28866 /* The Least Significant Bit (LSB) position of the ALT_GIC_CPUIF_GICC_BPR_FLD register field. */
28867 #define ALT_GIC_CPUIF_GICC_BPR_FLD_LSB 0
28868 /* The Most Significant Bit (MSB) position of the ALT_GIC_CPUIF_GICC_BPR_FLD register field. */
28869 #define ALT_GIC_CPUIF_GICC_BPR_FLD_MSB 31
28870 /* The width in bits of the ALT_GIC_CPUIF_GICC_BPR_FLD register field. */
28871 #define ALT_GIC_CPUIF_GICC_BPR_FLD_WIDTH 32
28872 /* The mask used to set the ALT_GIC_CPUIF_GICC_BPR_FLD register field value. */
28873 #define ALT_GIC_CPUIF_GICC_BPR_FLD_SET_MSK 0xffffffff
28874 /* The mask used to clear the ALT_GIC_CPUIF_GICC_BPR_FLD register field value. */
28875 #define ALT_GIC_CPUIF_GICC_BPR_FLD_CLR_MSK 0x00000000
28876 /* The reset value of the ALT_GIC_CPUIF_GICC_BPR_FLD register field is UNKNOWN. */
28877 #define ALT_GIC_CPUIF_GICC_BPR_FLD_RESET 0x0
28878 /* Extracts the ALT_GIC_CPUIF_GICC_BPR_FLD field value from a register. */
28879 #define ALT_GIC_CPUIF_GICC_BPR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
28880 /* Produces a ALT_GIC_CPUIF_GICC_BPR_FLD register field value suitable for setting the register. */
28881 #define ALT_GIC_CPUIF_GICC_BPR_FLD_SET(value) (((value) << 0) & 0xffffffff)
28882 
28883 #ifndef __ASSEMBLY__
28884 /*
28885  * WARNING: The C register and register group struct declarations are provided for
28886  * convenience and illustrative purposes. They should, however, be used with
28887  * caution as the C language standard provides no guarantees about the alignment or
28888  * atomicity of device memory accesses. The recommended practice for coding device
28889  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
28890  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
28891  * alt_write_dword() functions for 64 bit registers.
28892  *
28893  * The struct declaration for register ALT_GIC_CPUIF_GICC_BPR.
28894  */
28895 struct ALT_GIC_CPUIF_GICC_BPR_s
28896 {
28897  volatile uint32_t fld : 32; /* Empty */
28898 };
28899 
28900 /* The typedef declaration for register ALT_GIC_CPUIF_GICC_BPR. */
28901 typedef struct ALT_GIC_CPUIF_GICC_BPR_s ALT_GIC_CPUIF_GICC_BPR_t;
28902 #endif /* __ASSEMBLY__ */
28903 
28904 /* The reset value of the ALT_GIC_CPUIF_GICC_BPR register. */
28905 #define ALT_GIC_CPUIF_GICC_BPR_RESET 0x00000002
28906 /* The byte offset of the ALT_GIC_CPUIF_GICC_BPR register from the beginning of the component. */
28907 #define ALT_GIC_CPUIF_GICC_BPR_OFST 0x8
28908 
28909 /*
28910  * Register : GICC_IAR
28911  *
28912  * Interrupt Acknowledge Register
28913  *
28914  * Register Layout
28915  *
28916  * Bits | Access | Reset | Description
28917  * :-------|:-------|:--------|:------------
28918  * [31:0] | RW | Unknown | Empty
28919  *
28920  */
28921 /*
28922  * Field : Empty - fld
28923  *
28924  * Placeholder
28925  *
28926  * Field Access Macros:
28927  *
28928  */
28929 /* The Least Significant Bit (LSB) position of the ALT_GIC_CPUIF_GICC_IAR_FLD register field. */
28930 #define ALT_GIC_CPUIF_GICC_IAR_FLD_LSB 0
28931 /* The Most Significant Bit (MSB) position of the ALT_GIC_CPUIF_GICC_IAR_FLD register field. */
28932 #define ALT_GIC_CPUIF_GICC_IAR_FLD_MSB 31
28933 /* The width in bits of the ALT_GIC_CPUIF_GICC_IAR_FLD register field. */
28934 #define ALT_GIC_CPUIF_GICC_IAR_FLD_WIDTH 32
28935 /* The mask used to set the ALT_GIC_CPUIF_GICC_IAR_FLD register field value. */
28936 #define ALT_GIC_CPUIF_GICC_IAR_FLD_SET_MSK 0xffffffff
28937 /* The mask used to clear the ALT_GIC_CPUIF_GICC_IAR_FLD register field value. */
28938 #define ALT_GIC_CPUIF_GICC_IAR_FLD_CLR_MSK 0x00000000
28939 /* The reset value of the ALT_GIC_CPUIF_GICC_IAR_FLD register field is UNKNOWN. */
28940 #define ALT_GIC_CPUIF_GICC_IAR_FLD_RESET 0x0
28941 /* Extracts the ALT_GIC_CPUIF_GICC_IAR_FLD field value from a register. */
28942 #define ALT_GIC_CPUIF_GICC_IAR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
28943 /* Produces a ALT_GIC_CPUIF_GICC_IAR_FLD register field value suitable for setting the register. */
28944 #define ALT_GIC_CPUIF_GICC_IAR_FLD_SET(value) (((value) << 0) & 0xffffffff)
28945 
28946 #ifndef __ASSEMBLY__
28947 /*
28948  * WARNING: The C register and register group struct declarations are provided for
28949  * convenience and illustrative purposes. They should, however, be used with
28950  * caution as the C language standard provides no guarantees about the alignment or
28951  * atomicity of device memory accesses. The recommended practice for coding device
28952  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
28953  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
28954  * alt_write_dword() functions for 64 bit registers.
28955  *
28956  * The struct declaration for register ALT_GIC_CPUIF_GICC_IAR.
28957  */
28958 struct ALT_GIC_CPUIF_GICC_IAR_s
28959 {
28960  volatile uint32_t fld : 32; /* Empty */
28961 };
28962 
28963 /* The typedef declaration for register ALT_GIC_CPUIF_GICC_IAR. */
28964 typedef struct ALT_GIC_CPUIF_GICC_IAR_s ALT_GIC_CPUIF_GICC_IAR_t;
28965 #endif /* __ASSEMBLY__ */
28966 
28967 /* The reset value of the ALT_GIC_CPUIF_GICC_IAR register. */
28968 #define ALT_GIC_CPUIF_GICC_IAR_RESET 0x000003ff
28969 /* The byte offset of the ALT_GIC_CPUIF_GICC_IAR register from the beginning of the component. */
28970 #define ALT_GIC_CPUIF_GICC_IAR_OFST 0xc
28971 
28972 /*
28973  * Register : GICC_EOIR
28974  *
28975  * End of Interrupt Register
28976  *
28977  * Register Layout
28978  *
28979  * Bits | Access | Reset | Description
28980  * :-------|:-------|:--------|:------------
28981  * [31:0] | RW | Unknown | Empty
28982  *
28983  */
28984 /*
28985  * Field : Empty - fld
28986  *
28987  * Placeholder
28988  *
28989  * Field Access Macros:
28990  *
28991  */
28992 /* The Least Significant Bit (LSB) position of the ALT_GIC_CPUIF_GICC_EOIR_FLD register field. */
28993 #define ALT_GIC_CPUIF_GICC_EOIR_FLD_LSB 0
28994 /* The Most Significant Bit (MSB) position of the ALT_GIC_CPUIF_GICC_EOIR_FLD register field. */
28995 #define ALT_GIC_CPUIF_GICC_EOIR_FLD_MSB 31
28996 /* The width in bits of the ALT_GIC_CPUIF_GICC_EOIR_FLD register field. */
28997 #define ALT_GIC_CPUIF_GICC_EOIR_FLD_WIDTH 32
28998 /* The mask used to set the ALT_GIC_CPUIF_GICC_EOIR_FLD register field value. */
28999 #define ALT_GIC_CPUIF_GICC_EOIR_FLD_SET_MSK 0xffffffff
29000 /* The mask used to clear the ALT_GIC_CPUIF_GICC_EOIR_FLD register field value. */
29001 #define ALT_GIC_CPUIF_GICC_EOIR_FLD_CLR_MSK 0x00000000
29002 /* The reset value of the ALT_GIC_CPUIF_GICC_EOIR_FLD register field is UNKNOWN. */
29003 #define ALT_GIC_CPUIF_GICC_EOIR_FLD_RESET 0x0
29004 /* Extracts the ALT_GIC_CPUIF_GICC_EOIR_FLD field value from a register. */
29005 #define ALT_GIC_CPUIF_GICC_EOIR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29006 /* Produces a ALT_GIC_CPUIF_GICC_EOIR_FLD register field value suitable for setting the register. */
29007 #define ALT_GIC_CPUIF_GICC_EOIR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29008 
29009 #ifndef __ASSEMBLY__
29010 /*
29011  * WARNING: The C register and register group struct declarations are provided for
29012  * convenience and illustrative purposes. They should, however, be used with
29013  * caution as the C language standard provides no guarantees about the alignment or
29014  * atomicity of device memory accesses. The recommended practice for coding device
29015  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29016  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29017  * alt_write_dword() functions for 64 bit registers.
29018  *
29019  * The struct declaration for register ALT_GIC_CPUIF_GICC_EOIR.
29020  */
29021 struct ALT_GIC_CPUIF_GICC_EOIR_s
29022 {
29023  volatile uint32_t fld : 32; /* Empty */
29024 };
29025 
29026 /* The typedef declaration for register ALT_GIC_CPUIF_GICC_EOIR. */
29027 typedef struct ALT_GIC_CPUIF_GICC_EOIR_s ALT_GIC_CPUIF_GICC_EOIR_t;
29028 #endif /* __ASSEMBLY__ */
29029 
29030 /* The reset value of the ALT_GIC_CPUIF_GICC_EOIR register. */
29031 #define ALT_GIC_CPUIF_GICC_EOIR_RESET 0x00000000
29032 /* The byte offset of the ALT_GIC_CPUIF_GICC_EOIR register from the beginning of the component. */
29033 #define ALT_GIC_CPUIF_GICC_EOIR_OFST 0x10
29034 
29035 /*
29036  * Register : GICC_RPR
29037  *
29038  * Running Priority Register
29039  *
29040  * Register Layout
29041  *
29042  * Bits | Access | Reset | Description
29043  * :-------|:-------|:--------|:------------
29044  * [31:0] | RW | Unknown | Empty
29045  *
29046  */
29047 /*
29048  * Field : Empty - fld
29049  *
29050  * Placeholder
29051  *
29052  * Field Access Macros:
29053  *
29054  */
29055 /* The Least Significant Bit (LSB) position of the ALT_GIC_CPUIF_GICC_RPR_FLD register field. */
29056 #define ALT_GIC_CPUIF_GICC_RPR_FLD_LSB 0
29057 /* The Most Significant Bit (MSB) position of the ALT_GIC_CPUIF_GICC_RPR_FLD register field. */
29058 #define ALT_GIC_CPUIF_GICC_RPR_FLD_MSB 31
29059 /* The width in bits of the ALT_GIC_CPUIF_GICC_RPR_FLD register field. */
29060 #define ALT_GIC_CPUIF_GICC_RPR_FLD_WIDTH 32
29061 /* The mask used to set the ALT_GIC_CPUIF_GICC_RPR_FLD register field value. */
29062 #define ALT_GIC_CPUIF_GICC_RPR_FLD_SET_MSK 0xffffffff
29063 /* The mask used to clear the ALT_GIC_CPUIF_GICC_RPR_FLD register field value. */
29064 #define ALT_GIC_CPUIF_GICC_RPR_FLD_CLR_MSK 0x00000000
29065 /* The reset value of the ALT_GIC_CPUIF_GICC_RPR_FLD register field is UNKNOWN. */
29066 #define ALT_GIC_CPUIF_GICC_RPR_FLD_RESET 0x0
29067 /* Extracts the ALT_GIC_CPUIF_GICC_RPR_FLD field value from a register. */
29068 #define ALT_GIC_CPUIF_GICC_RPR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29069 /* Produces a ALT_GIC_CPUIF_GICC_RPR_FLD register field value suitable for setting the register. */
29070 #define ALT_GIC_CPUIF_GICC_RPR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29071 
29072 #ifndef __ASSEMBLY__
29073 /*
29074  * WARNING: The C register and register group struct declarations are provided for
29075  * convenience and illustrative purposes. They should, however, be used with
29076  * caution as the C language standard provides no guarantees about the alignment or
29077  * atomicity of device memory accesses. The recommended practice for coding device
29078  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29079  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29080  * alt_write_dword() functions for 64 bit registers.
29081  *
29082  * The struct declaration for register ALT_GIC_CPUIF_GICC_RPR.
29083  */
29084 struct ALT_GIC_CPUIF_GICC_RPR_s
29085 {
29086  volatile uint32_t fld : 32; /* Empty */
29087 };
29088 
29089 /* The typedef declaration for register ALT_GIC_CPUIF_GICC_RPR. */
29090 typedef struct ALT_GIC_CPUIF_GICC_RPR_s ALT_GIC_CPUIF_GICC_RPR_t;
29091 #endif /* __ASSEMBLY__ */
29092 
29093 /* The reset value of the ALT_GIC_CPUIF_GICC_RPR register. */
29094 #define ALT_GIC_CPUIF_GICC_RPR_RESET 0x000000ff
29095 /* The byte offset of the ALT_GIC_CPUIF_GICC_RPR register from the beginning of the component. */
29096 #define ALT_GIC_CPUIF_GICC_RPR_OFST 0x14
29097 
29098 /*
29099  * Register : GICC_HPPIR
29100  *
29101  * Highest Priority Pending Interrupt Register
29102  *
29103  * Register Layout
29104  *
29105  * Bits | Access | Reset | Description
29106  * :-------|:-------|:--------|:------------
29107  * [31:0] | RW | Unknown | Empty
29108  *
29109  */
29110 /*
29111  * Field : Empty - fld
29112  *
29113  * Placeholder
29114  *
29115  * Field Access Macros:
29116  *
29117  */
29118 /* The Least Significant Bit (LSB) position of the ALT_GIC_CPUIF_GICC_HPPIR_FLD register field. */
29119 #define ALT_GIC_CPUIF_GICC_HPPIR_FLD_LSB 0
29120 /* The Most Significant Bit (MSB) position of the ALT_GIC_CPUIF_GICC_HPPIR_FLD register field. */
29121 #define ALT_GIC_CPUIF_GICC_HPPIR_FLD_MSB 31
29122 /* The width in bits of the ALT_GIC_CPUIF_GICC_HPPIR_FLD register field. */
29123 #define ALT_GIC_CPUIF_GICC_HPPIR_FLD_WIDTH 32
29124 /* The mask used to set the ALT_GIC_CPUIF_GICC_HPPIR_FLD register field value. */
29125 #define ALT_GIC_CPUIF_GICC_HPPIR_FLD_SET_MSK 0xffffffff
29126 /* The mask used to clear the ALT_GIC_CPUIF_GICC_HPPIR_FLD register field value. */
29127 #define ALT_GIC_CPUIF_GICC_HPPIR_FLD_CLR_MSK 0x00000000
29128 /* The reset value of the ALT_GIC_CPUIF_GICC_HPPIR_FLD register field is UNKNOWN. */
29129 #define ALT_GIC_CPUIF_GICC_HPPIR_FLD_RESET 0x0
29130 /* Extracts the ALT_GIC_CPUIF_GICC_HPPIR_FLD field value from a register. */
29131 #define ALT_GIC_CPUIF_GICC_HPPIR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29132 /* Produces a ALT_GIC_CPUIF_GICC_HPPIR_FLD register field value suitable for setting the register. */
29133 #define ALT_GIC_CPUIF_GICC_HPPIR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29134 
29135 #ifndef __ASSEMBLY__
29136 /*
29137  * WARNING: The C register and register group struct declarations are provided for
29138  * convenience and illustrative purposes. They should, however, be used with
29139  * caution as the C language standard provides no guarantees about the alignment or
29140  * atomicity of device memory accesses. The recommended practice for coding device
29141  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29142  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29143  * alt_write_dword() functions for 64 bit registers.
29144  *
29145  * The struct declaration for register ALT_GIC_CPUIF_GICC_HPPIR.
29146  */
29147 struct ALT_GIC_CPUIF_GICC_HPPIR_s
29148 {
29149  volatile uint32_t fld : 32; /* Empty */
29150 };
29151 
29152 /* The typedef declaration for register ALT_GIC_CPUIF_GICC_HPPIR. */
29153 typedef struct ALT_GIC_CPUIF_GICC_HPPIR_s ALT_GIC_CPUIF_GICC_HPPIR_t;
29154 #endif /* __ASSEMBLY__ */
29155 
29156 /* The reset value of the ALT_GIC_CPUIF_GICC_HPPIR register. */
29157 #define ALT_GIC_CPUIF_GICC_HPPIR_RESET 0x000003ff
29158 /* The byte offset of the ALT_GIC_CPUIF_GICC_HPPIR register from the beginning of the component. */
29159 #define ALT_GIC_CPUIF_GICC_HPPIR_OFST 0x18
29160 
29161 /*
29162  * Register : GICC_ABPR
29163  *
29164  * Aliased Binary Point Register
29165  *
29166  * Register Layout
29167  *
29168  * Bits | Access | Reset | Description
29169  * :-------|:-------|:--------|:------------
29170  * [31:0] | RW | Unknown | Empty
29171  *
29172  */
29173 /*
29174  * Field : Empty - fld
29175  *
29176  * Placeholder
29177  *
29178  * Field Access Macros:
29179  *
29180  */
29181 /* The Least Significant Bit (LSB) position of the ALT_GIC_CPUIF_GICC_ABPR_FLD register field. */
29182 #define ALT_GIC_CPUIF_GICC_ABPR_FLD_LSB 0
29183 /* The Most Significant Bit (MSB) position of the ALT_GIC_CPUIF_GICC_ABPR_FLD register field. */
29184 #define ALT_GIC_CPUIF_GICC_ABPR_FLD_MSB 31
29185 /* The width in bits of the ALT_GIC_CPUIF_GICC_ABPR_FLD register field. */
29186 #define ALT_GIC_CPUIF_GICC_ABPR_FLD_WIDTH 32
29187 /* The mask used to set the ALT_GIC_CPUIF_GICC_ABPR_FLD register field value. */
29188 #define ALT_GIC_CPUIF_GICC_ABPR_FLD_SET_MSK 0xffffffff
29189 /* The mask used to clear the ALT_GIC_CPUIF_GICC_ABPR_FLD register field value. */
29190 #define ALT_GIC_CPUIF_GICC_ABPR_FLD_CLR_MSK 0x00000000
29191 /* The reset value of the ALT_GIC_CPUIF_GICC_ABPR_FLD register field is UNKNOWN. */
29192 #define ALT_GIC_CPUIF_GICC_ABPR_FLD_RESET 0x0
29193 /* Extracts the ALT_GIC_CPUIF_GICC_ABPR_FLD field value from a register. */
29194 #define ALT_GIC_CPUIF_GICC_ABPR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29195 /* Produces a ALT_GIC_CPUIF_GICC_ABPR_FLD register field value suitable for setting the register. */
29196 #define ALT_GIC_CPUIF_GICC_ABPR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29197 
29198 #ifndef __ASSEMBLY__
29199 /*
29200  * WARNING: The C register and register group struct declarations are provided for
29201  * convenience and illustrative purposes. They should, however, be used with
29202  * caution as the C language standard provides no guarantees about the alignment or
29203  * atomicity of device memory accesses. The recommended practice for coding device
29204  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29205  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29206  * alt_write_dword() functions for 64 bit registers.
29207  *
29208  * The struct declaration for register ALT_GIC_CPUIF_GICC_ABPR.
29209  */
29210 struct ALT_GIC_CPUIF_GICC_ABPR_s
29211 {
29212  volatile uint32_t fld : 32; /* Empty */
29213 };
29214 
29215 /* The typedef declaration for register ALT_GIC_CPUIF_GICC_ABPR. */
29216 typedef struct ALT_GIC_CPUIF_GICC_ABPR_s ALT_GIC_CPUIF_GICC_ABPR_t;
29217 #endif /* __ASSEMBLY__ */
29218 
29219 /* The reset value of the ALT_GIC_CPUIF_GICC_ABPR register. */
29220 #define ALT_GIC_CPUIF_GICC_ABPR_RESET 0x00000003
29221 /* The byte offset of the ALT_GIC_CPUIF_GICC_ABPR register from the beginning of the component. */
29222 #define ALT_GIC_CPUIF_GICC_ABPR_OFST 0x1c
29223 
29224 /*
29225  * Register : GICC_AIAR
29226  *
29227  * Aliased Interrupt Acknowledge Register
29228  *
29229  * Register Layout
29230  *
29231  * Bits | Access | Reset | Description
29232  * :-------|:-------|:--------|:------------
29233  * [31:0] | RW | Unknown | Empty
29234  *
29235  */
29236 /*
29237  * Field : Empty - fld
29238  *
29239  * Placeholder
29240  *
29241  * Field Access Macros:
29242  *
29243  */
29244 /* The Least Significant Bit (LSB) position of the ALT_GIC_CPUIF_GICC_AIAR_FLD register field. */
29245 #define ALT_GIC_CPUIF_GICC_AIAR_FLD_LSB 0
29246 /* The Most Significant Bit (MSB) position of the ALT_GIC_CPUIF_GICC_AIAR_FLD register field. */
29247 #define ALT_GIC_CPUIF_GICC_AIAR_FLD_MSB 31
29248 /* The width in bits of the ALT_GIC_CPUIF_GICC_AIAR_FLD register field. */
29249 #define ALT_GIC_CPUIF_GICC_AIAR_FLD_WIDTH 32
29250 /* The mask used to set the ALT_GIC_CPUIF_GICC_AIAR_FLD register field value. */
29251 #define ALT_GIC_CPUIF_GICC_AIAR_FLD_SET_MSK 0xffffffff
29252 /* The mask used to clear the ALT_GIC_CPUIF_GICC_AIAR_FLD register field value. */
29253 #define ALT_GIC_CPUIF_GICC_AIAR_FLD_CLR_MSK 0x00000000
29254 /* The reset value of the ALT_GIC_CPUIF_GICC_AIAR_FLD register field is UNKNOWN. */
29255 #define ALT_GIC_CPUIF_GICC_AIAR_FLD_RESET 0x0
29256 /* Extracts the ALT_GIC_CPUIF_GICC_AIAR_FLD field value from a register. */
29257 #define ALT_GIC_CPUIF_GICC_AIAR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29258 /* Produces a ALT_GIC_CPUIF_GICC_AIAR_FLD register field value suitable for setting the register. */
29259 #define ALT_GIC_CPUIF_GICC_AIAR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29260 
29261 #ifndef __ASSEMBLY__
29262 /*
29263  * WARNING: The C register and register group struct declarations are provided for
29264  * convenience and illustrative purposes. They should, however, be used with
29265  * caution as the C language standard provides no guarantees about the alignment or
29266  * atomicity of device memory accesses. The recommended practice for coding device
29267  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29268  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29269  * alt_write_dword() functions for 64 bit registers.
29270  *
29271  * The struct declaration for register ALT_GIC_CPUIF_GICC_AIAR.
29272  */
29273 struct ALT_GIC_CPUIF_GICC_AIAR_s
29274 {
29275  volatile uint32_t fld : 32; /* Empty */
29276 };
29277 
29278 /* The typedef declaration for register ALT_GIC_CPUIF_GICC_AIAR. */
29279 typedef struct ALT_GIC_CPUIF_GICC_AIAR_s ALT_GIC_CPUIF_GICC_AIAR_t;
29280 #endif /* __ASSEMBLY__ */
29281 
29282 /* The reset value of the ALT_GIC_CPUIF_GICC_AIAR register. */
29283 #define ALT_GIC_CPUIF_GICC_AIAR_RESET 0x000003ff
29284 /* The byte offset of the ALT_GIC_CPUIF_GICC_AIAR register from the beginning of the component. */
29285 #define ALT_GIC_CPUIF_GICC_AIAR_OFST 0x20
29286 
29287 /*
29288  * Register : GICC_AEOIR
29289  *
29290  * Aliased End of Interrupt Register
29291  *
29292  * Register Layout
29293  *
29294  * Bits | Access | Reset | Description
29295  * :-------|:-------|:--------|:------------
29296  * [31:0] | RW | Unknown | Empty
29297  *
29298  */
29299 /*
29300  * Field : Empty - fld
29301  *
29302  * Placeholder
29303  *
29304  * Field Access Macros:
29305  *
29306  */
29307 /* The Least Significant Bit (LSB) position of the ALT_GIC_CPUIF_GICC_AEOIR_FLD register field. */
29308 #define ALT_GIC_CPUIF_GICC_AEOIR_FLD_LSB 0
29309 /* The Most Significant Bit (MSB) position of the ALT_GIC_CPUIF_GICC_AEOIR_FLD register field. */
29310 #define ALT_GIC_CPUIF_GICC_AEOIR_FLD_MSB 31
29311 /* The width in bits of the ALT_GIC_CPUIF_GICC_AEOIR_FLD register field. */
29312 #define ALT_GIC_CPUIF_GICC_AEOIR_FLD_WIDTH 32
29313 /* The mask used to set the ALT_GIC_CPUIF_GICC_AEOIR_FLD register field value. */
29314 #define ALT_GIC_CPUIF_GICC_AEOIR_FLD_SET_MSK 0xffffffff
29315 /* The mask used to clear the ALT_GIC_CPUIF_GICC_AEOIR_FLD register field value. */
29316 #define ALT_GIC_CPUIF_GICC_AEOIR_FLD_CLR_MSK 0x00000000
29317 /* The reset value of the ALT_GIC_CPUIF_GICC_AEOIR_FLD register field is UNKNOWN. */
29318 #define ALT_GIC_CPUIF_GICC_AEOIR_FLD_RESET 0x0
29319 /* Extracts the ALT_GIC_CPUIF_GICC_AEOIR_FLD field value from a register. */
29320 #define ALT_GIC_CPUIF_GICC_AEOIR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29321 /* Produces a ALT_GIC_CPUIF_GICC_AEOIR_FLD register field value suitable for setting the register. */
29322 #define ALT_GIC_CPUIF_GICC_AEOIR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29323 
29324 #ifndef __ASSEMBLY__
29325 /*
29326  * WARNING: The C register and register group struct declarations are provided for
29327  * convenience and illustrative purposes. They should, however, be used with
29328  * caution as the C language standard provides no guarantees about the alignment or
29329  * atomicity of device memory accesses. The recommended practice for coding device
29330  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29331  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29332  * alt_write_dword() functions for 64 bit registers.
29333  *
29334  * The struct declaration for register ALT_GIC_CPUIF_GICC_AEOIR.
29335  */
29336 struct ALT_GIC_CPUIF_GICC_AEOIR_s
29337 {
29338  volatile uint32_t fld : 32; /* Empty */
29339 };
29340 
29341 /* The typedef declaration for register ALT_GIC_CPUIF_GICC_AEOIR. */
29342 typedef struct ALT_GIC_CPUIF_GICC_AEOIR_s ALT_GIC_CPUIF_GICC_AEOIR_t;
29343 #endif /* __ASSEMBLY__ */
29344 
29345 /* The reset value of the ALT_GIC_CPUIF_GICC_AEOIR register. */
29346 #define ALT_GIC_CPUIF_GICC_AEOIR_RESET 0x00000000
29347 /* The byte offset of the ALT_GIC_CPUIF_GICC_AEOIR register from the beginning of the component. */
29348 #define ALT_GIC_CPUIF_GICC_AEOIR_OFST 0x24
29349 
29350 /*
29351  * Register : GICC_AHPPIR
29352  *
29353  * Aliased Highest Priority Pending Interrupt Register
29354  *
29355  * Register Layout
29356  *
29357  * Bits | Access | Reset | Description
29358  * :-------|:-------|:--------|:------------
29359  * [31:0] | RW | Unknown | Empty
29360  *
29361  */
29362 /*
29363  * Field : Empty - fld
29364  *
29365  * Placeholder
29366  *
29367  * Field Access Macros:
29368  *
29369  */
29370 /* The Least Significant Bit (LSB) position of the ALT_GIC_CPUIF_GICC_AHPPIR_FLD register field. */
29371 #define ALT_GIC_CPUIF_GICC_AHPPIR_FLD_LSB 0
29372 /* The Most Significant Bit (MSB) position of the ALT_GIC_CPUIF_GICC_AHPPIR_FLD register field. */
29373 #define ALT_GIC_CPUIF_GICC_AHPPIR_FLD_MSB 31
29374 /* The width in bits of the ALT_GIC_CPUIF_GICC_AHPPIR_FLD register field. */
29375 #define ALT_GIC_CPUIF_GICC_AHPPIR_FLD_WIDTH 32
29376 /* The mask used to set the ALT_GIC_CPUIF_GICC_AHPPIR_FLD register field value. */
29377 #define ALT_GIC_CPUIF_GICC_AHPPIR_FLD_SET_MSK 0xffffffff
29378 /* The mask used to clear the ALT_GIC_CPUIF_GICC_AHPPIR_FLD register field value. */
29379 #define ALT_GIC_CPUIF_GICC_AHPPIR_FLD_CLR_MSK 0x00000000
29380 /* The reset value of the ALT_GIC_CPUIF_GICC_AHPPIR_FLD register field is UNKNOWN. */
29381 #define ALT_GIC_CPUIF_GICC_AHPPIR_FLD_RESET 0x0
29382 /* Extracts the ALT_GIC_CPUIF_GICC_AHPPIR_FLD field value from a register. */
29383 #define ALT_GIC_CPUIF_GICC_AHPPIR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29384 /* Produces a ALT_GIC_CPUIF_GICC_AHPPIR_FLD register field value suitable for setting the register. */
29385 #define ALT_GIC_CPUIF_GICC_AHPPIR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29386 
29387 #ifndef __ASSEMBLY__
29388 /*
29389  * WARNING: The C register and register group struct declarations are provided for
29390  * convenience and illustrative purposes. They should, however, be used with
29391  * caution as the C language standard provides no guarantees about the alignment or
29392  * atomicity of device memory accesses. The recommended practice for coding device
29393  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29394  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29395  * alt_write_dword() functions for 64 bit registers.
29396  *
29397  * The struct declaration for register ALT_GIC_CPUIF_GICC_AHPPIR.
29398  */
29399 struct ALT_GIC_CPUIF_GICC_AHPPIR_s
29400 {
29401  volatile uint32_t fld : 32; /* Empty */
29402 };
29403 
29404 /* The typedef declaration for register ALT_GIC_CPUIF_GICC_AHPPIR. */
29405 typedef struct ALT_GIC_CPUIF_GICC_AHPPIR_s ALT_GIC_CPUIF_GICC_AHPPIR_t;
29406 #endif /* __ASSEMBLY__ */
29407 
29408 /* The reset value of the ALT_GIC_CPUIF_GICC_AHPPIR register. */
29409 #define ALT_GIC_CPUIF_GICC_AHPPIR_RESET 0x000003ff
29410 /* The byte offset of the ALT_GIC_CPUIF_GICC_AHPPIR register from the beginning of the component. */
29411 #define ALT_GIC_CPUIF_GICC_AHPPIR_OFST 0x28
29412 
29413 /*
29414  * Register : GICC_APR0
29415  *
29416  * Active Priority Register
29417  *
29418  * Register Layout
29419  *
29420  * Bits | Access | Reset | Description
29421  * :-------|:-------|:------|:------------
29422  * [31:0] | RW | 0x0 | Empty
29423  *
29424  */
29425 /*
29426  * Field : Empty - fld
29427  *
29428  * Placeholder
29429  *
29430  * Field Access Macros:
29431  *
29432  */
29433 /* The Least Significant Bit (LSB) position of the ALT_GIC_CPUIF_GICC_APR0_FLD register field. */
29434 #define ALT_GIC_CPUIF_GICC_APR0_FLD_LSB 0
29435 /* The Most Significant Bit (MSB) position of the ALT_GIC_CPUIF_GICC_APR0_FLD register field. */
29436 #define ALT_GIC_CPUIF_GICC_APR0_FLD_MSB 31
29437 /* The width in bits of the ALT_GIC_CPUIF_GICC_APR0_FLD register field. */
29438 #define ALT_GIC_CPUIF_GICC_APR0_FLD_WIDTH 32
29439 /* The mask used to set the ALT_GIC_CPUIF_GICC_APR0_FLD register field value. */
29440 #define ALT_GIC_CPUIF_GICC_APR0_FLD_SET_MSK 0xffffffff
29441 /* The mask used to clear the ALT_GIC_CPUIF_GICC_APR0_FLD register field value. */
29442 #define ALT_GIC_CPUIF_GICC_APR0_FLD_CLR_MSK 0x00000000
29443 /* The reset value of the ALT_GIC_CPUIF_GICC_APR0_FLD register field. */
29444 #define ALT_GIC_CPUIF_GICC_APR0_FLD_RESET 0x0
29445 /* Extracts the ALT_GIC_CPUIF_GICC_APR0_FLD field value from a register. */
29446 #define ALT_GIC_CPUIF_GICC_APR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29447 /* Produces a ALT_GIC_CPUIF_GICC_APR0_FLD register field value suitable for setting the register. */
29448 #define ALT_GIC_CPUIF_GICC_APR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
29449 
29450 #ifndef __ASSEMBLY__
29451 /*
29452  * WARNING: The C register and register group struct declarations are provided for
29453  * convenience and illustrative purposes. They should, however, be used with
29454  * caution as the C language standard provides no guarantees about the alignment or
29455  * atomicity of device memory accesses. The recommended practice for coding device
29456  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29457  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29458  * alt_write_dword() functions for 64 bit registers.
29459  *
29460  * The struct declaration for register ALT_GIC_CPUIF_GICC_APR0.
29461  */
29462 struct ALT_GIC_CPUIF_GICC_APR0_s
29463 {
29464  volatile uint32_t fld : 32; /* Empty */
29465 };
29466 
29467 /* The typedef declaration for register ALT_GIC_CPUIF_GICC_APR0. */
29468 typedef struct ALT_GIC_CPUIF_GICC_APR0_s ALT_GIC_CPUIF_GICC_APR0_t;
29469 #endif /* __ASSEMBLY__ */
29470 
29471 /* The reset value of the ALT_GIC_CPUIF_GICC_APR0 register. */
29472 #define ALT_GIC_CPUIF_GICC_APR0_RESET 0x00000000
29473 /* The byte offset of the ALT_GIC_CPUIF_GICC_APR0 register from the beginning of the component. */
29474 #define ALT_GIC_CPUIF_GICC_APR0_OFST 0xd0
29475 
29476 /*
29477  * Register : GICC_NSAPR0
29478  *
29479  * Non-Secure Active Priority Register
29480  *
29481  * Register Layout
29482  *
29483  * Bits | Access | Reset | Description
29484  * :-------|:-------|:------|:------------
29485  * [31:0] | RW | 0x0 | Empty
29486  *
29487  */
29488 /*
29489  * Field : Empty - fld
29490  *
29491  * Placeholder
29492  *
29493  * Field Access Macros:
29494  *
29495  */
29496 /* The Least Significant Bit (LSB) position of the ALT_GIC_CPUIF_GICC_NSAPR0_FLD register field. */
29497 #define ALT_GIC_CPUIF_GICC_NSAPR0_FLD_LSB 0
29498 /* The Most Significant Bit (MSB) position of the ALT_GIC_CPUIF_GICC_NSAPR0_FLD register field. */
29499 #define ALT_GIC_CPUIF_GICC_NSAPR0_FLD_MSB 31
29500 /* The width in bits of the ALT_GIC_CPUIF_GICC_NSAPR0_FLD register field. */
29501 #define ALT_GIC_CPUIF_GICC_NSAPR0_FLD_WIDTH 32
29502 /* The mask used to set the ALT_GIC_CPUIF_GICC_NSAPR0_FLD register field value. */
29503 #define ALT_GIC_CPUIF_GICC_NSAPR0_FLD_SET_MSK 0xffffffff
29504 /* The mask used to clear the ALT_GIC_CPUIF_GICC_NSAPR0_FLD register field value. */
29505 #define ALT_GIC_CPUIF_GICC_NSAPR0_FLD_CLR_MSK 0x00000000
29506 /* The reset value of the ALT_GIC_CPUIF_GICC_NSAPR0_FLD register field. */
29507 #define ALT_GIC_CPUIF_GICC_NSAPR0_FLD_RESET 0x0
29508 /* Extracts the ALT_GIC_CPUIF_GICC_NSAPR0_FLD field value from a register. */
29509 #define ALT_GIC_CPUIF_GICC_NSAPR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29510 /* Produces a ALT_GIC_CPUIF_GICC_NSAPR0_FLD register field value suitable for setting the register. */
29511 #define ALT_GIC_CPUIF_GICC_NSAPR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
29512 
29513 #ifndef __ASSEMBLY__
29514 /*
29515  * WARNING: The C register and register group struct declarations are provided for
29516  * convenience and illustrative purposes. They should, however, be used with
29517  * caution as the C language standard provides no guarantees about the alignment or
29518  * atomicity of device memory accesses. The recommended practice for coding device
29519  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29520  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29521  * alt_write_dword() functions for 64 bit registers.
29522  *
29523  * The struct declaration for register ALT_GIC_CPUIF_GICC_NSAPR0.
29524  */
29525 struct ALT_GIC_CPUIF_GICC_NSAPR0_s
29526 {
29527  volatile uint32_t fld : 32; /* Empty */
29528 };
29529 
29530 /* The typedef declaration for register ALT_GIC_CPUIF_GICC_NSAPR0. */
29531 typedef struct ALT_GIC_CPUIF_GICC_NSAPR0_s ALT_GIC_CPUIF_GICC_NSAPR0_t;
29532 #endif /* __ASSEMBLY__ */
29533 
29534 /* The reset value of the ALT_GIC_CPUIF_GICC_NSAPR0 register. */
29535 #define ALT_GIC_CPUIF_GICC_NSAPR0_RESET 0x00000000
29536 /* The byte offset of the ALT_GIC_CPUIF_GICC_NSAPR0 register from the beginning of the component. */
29537 #define ALT_GIC_CPUIF_GICC_NSAPR0_OFST 0xe0
29538 
29539 /*
29540  * Register : GICC_IIDR
29541  *
29542  * CPU Interface Identification Register
29543  *
29544  * Register Layout
29545  *
29546  * Bits | Access | Reset | Description
29547  * :-------|:-------|:----------|:------------
29548  * [31:0] | RW | 0x202143b | Empty
29549  *
29550  */
29551 /*
29552  * Field : Empty - fld
29553  *
29554  * Placeholder
29555  *
29556  * Field Access Macros:
29557  *
29558  */
29559 /* The Least Significant Bit (LSB) position of the ALT_GIC_CPUIF_GICC_IIDR_FLD register field. */
29560 #define ALT_GIC_CPUIF_GICC_IIDR_FLD_LSB 0
29561 /* The Most Significant Bit (MSB) position of the ALT_GIC_CPUIF_GICC_IIDR_FLD register field. */
29562 #define ALT_GIC_CPUIF_GICC_IIDR_FLD_MSB 31
29563 /* The width in bits of the ALT_GIC_CPUIF_GICC_IIDR_FLD register field. */
29564 #define ALT_GIC_CPUIF_GICC_IIDR_FLD_WIDTH 32
29565 /* The mask used to set the ALT_GIC_CPUIF_GICC_IIDR_FLD register field value. */
29566 #define ALT_GIC_CPUIF_GICC_IIDR_FLD_SET_MSK 0xffffffff
29567 /* The mask used to clear the ALT_GIC_CPUIF_GICC_IIDR_FLD register field value. */
29568 #define ALT_GIC_CPUIF_GICC_IIDR_FLD_CLR_MSK 0x00000000
29569 /* The reset value of the ALT_GIC_CPUIF_GICC_IIDR_FLD register field. */
29570 #define ALT_GIC_CPUIF_GICC_IIDR_FLD_RESET 0x202143b
29571 /* Extracts the ALT_GIC_CPUIF_GICC_IIDR_FLD field value from a register. */
29572 #define ALT_GIC_CPUIF_GICC_IIDR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29573 /* Produces a ALT_GIC_CPUIF_GICC_IIDR_FLD register field value suitable for setting the register. */
29574 #define ALT_GIC_CPUIF_GICC_IIDR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29575 
29576 #ifndef __ASSEMBLY__
29577 /*
29578  * WARNING: The C register and register group struct declarations are provided for
29579  * convenience and illustrative purposes. They should, however, be used with
29580  * caution as the C language standard provides no guarantees about the alignment or
29581  * atomicity of device memory accesses. The recommended practice for coding device
29582  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29583  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29584  * alt_write_dword() functions for 64 bit registers.
29585  *
29586  * The struct declaration for register ALT_GIC_CPUIF_GICC_IIDR.
29587  */
29588 struct ALT_GIC_CPUIF_GICC_IIDR_s
29589 {
29590  volatile uint32_t fld : 32; /* Empty */
29591 };
29592 
29593 /* The typedef declaration for register ALT_GIC_CPUIF_GICC_IIDR. */
29594 typedef struct ALT_GIC_CPUIF_GICC_IIDR_s ALT_GIC_CPUIF_GICC_IIDR_t;
29595 #endif /* __ASSEMBLY__ */
29596 
29597 /* The reset value of the ALT_GIC_CPUIF_GICC_IIDR register. */
29598 #define ALT_GIC_CPUIF_GICC_IIDR_RESET 0x0202143b
29599 /* The byte offset of the ALT_GIC_CPUIF_GICC_IIDR register from the beginning of the component. */
29600 #define ALT_GIC_CPUIF_GICC_IIDR_OFST 0xfc
29601 
29602 /*
29603  * Register : GICC_DIR
29604  *
29605  * Deactivate Interrupt Register
29606  *
29607  * Register Layout
29608  *
29609  * Bits | Access | Reset | Description
29610  * :-------|:-------|:--------|:------------
29611  * [31:0] | RW | Unknown | Empty
29612  *
29613  */
29614 /*
29615  * Field : Empty - fld
29616  *
29617  * Placeholder
29618  *
29619  * Field Access Macros:
29620  *
29621  */
29622 /* The Least Significant Bit (LSB) position of the ALT_GIC_CPUIF_GICC_DIR_FLD register field. */
29623 #define ALT_GIC_CPUIF_GICC_DIR_FLD_LSB 0
29624 /* The Most Significant Bit (MSB) position of the ALT_GIC_CPUIF_GICC_DIR_FLD register field. */
29625 #define ALT_GIC_CPUIF_GICC_DIR_FLD_MSB 31
29626 /* The width in bits of the ALT_GIC_CPUIF_GICC_DIR_FLD register field. */
29627 #define ALT_GIC_CPUIF_GICC_DIR_FLD_WIDTH 32
29628 /* The mask used to set the ALT_GIC_CPUIF_GICC_DIR_FLD register field value. */
29629 #define ALT_GIC_CPUIF_GICC_DIR_FLD_SET_MSK 0xffffffff
29630 /* The mask used to clear the ALT_GIC_CPUIF_GICC_DIR_FLD register field value. */
29631 #define ALT_GIC_CPUIF_GICC_DIR_FLD_CLR_MSK 0x00000000
29632 /* The reset value of the ALT_GIC_CPUIF_GICC_DIR_FLD register field is UNKNOWN. */
29633 #define ALT_GIC_CPUIF_GICC_DIR_FLD_RESET 0x0
29634 /* Extracts the ALT_GIC_CPUIF_GICC_DIR_FLD field value from a register. */
29635 #define ALT_GIC_CPUIF_GICC_DIR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29636 /* Produces a ALT_GIC_CPUIF_GICC_DIR_FLD register field value suitable for setting the register. */
29637 #define ALT_GIC_CPUIF_GICC_DIR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29638 
29639 #ifndef __ASSEMBLY__
29640 /*
29641  * WARNING: The C register and register group struct declarations are provided for
29642  * convenience and illustrative purposes. They should, however, be used with
29643  * caution as the C language standard provides no guarantees about the alignment or
29644  * atomicity of device memory accesses. The recommended practice for coding device
29645  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29646  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29647  * alt_write_dword() functions for 64 bit registers.
29648  *
29649  * The struct declaration for register ALT_GIC_CPUIF_GICC_DIR.
29650  */
29651 struct ALT_GIC_CPUIF_GICC_DIR_s
29652 {
29653  volatile uint32_t fld : 32; /* Empty */
29654 };
29655 
29656 /* The typedef declaration for register ALT_GIC_CPUIF_GICC_DIR. */
29657 typedef struct ALT_GIC_CPUIF_GICC_DIR_s ALT_GIC_CPUIF_GICC_DIR_t;
29658 #endif /* __ASSEMBLY__ */
29659 
29660 /* The reset value of the ALT_GIC_CPUIF_GICC_DIR register. */
29661 #define ALT_GIC_CPUIF_GICC_DIR_RESET 0x00000000
29662 /* The byte offset of the ALT_GIC_CPUIF_GICC_DIR register from the beginning of the component. */
29663 #define ALT_GIC_CPUIF_GICC_DIR_OFST 0x1000
29664 
29665 #ifndef __ASSEMBLY__
29666 /*
29667  * WARNING: The C register and register group struct declarations are provided for
29668  * convenience and illustrative purposes. They should, however, be used with
29669  * caution as the C language standard provides no guarantees about the alignment or
29670  * atomicity of device memory accesses. The recommended practice for coding device
29671  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29672  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29673  * alt_write_dword() functions for 64 bit registers.
29674  *
29675  * The struct declaration for register group ALT_GIC_CPUIF.
29676  */
29677 struct ALT_GIC_CPUIF_s
29678 {
29679  volatile ALT_GIC_CPUIF_GICC_CTLR_t GICC_CTLR; /* ALT_GIC_CPUIF_GICC_CTLR */
29680  volatile ALT_GIC_CPUIF_GICC_PMR_t GICC_PMR; /* ALT_GIC_CPUIF_GICC_PMR */
29681  volatile ALT_GIC_CPUIF_GICC_BPR_t GICC_BPR; /* ALT_GIC_CPUIF_GICC_BPR */
29682  volatile ALT_GIC_CPUIF_GICC_IAR_t GICC_IAR; /* ALT_GIC_CPUIF_GICC_IAR */
29683  volatile ALT_GIC_CPUIF_GICC_EOIR_t GICC_EOIR; /* ALT_GIC_CPUIF_GICC_EOIR */
29684  volatile ALT_GIC_CPUIF_GICC_RPR_t GICC_RPR; /* ALT_GIC_CPUIF_GICC_RPR */
29685  volatile ALT_GIC_CPUIF_GICC_HPPIR_t GICC_HPPIR; /* ALT_GIC_CPUIF_GICC_HPPIR */
29686  volatile ALT_GIC_CPUIF_GICC_ABPR_t GICC_ABPR; /* ALT_GIC_CPUIF_GICC_ABPR */
29687  volatile ALT_GIC_CPUIF_GICC_AIAR_t GICC_AIAR; /* ALT_GIC_CPUIF_GICC_AIAR */
29688  volatile ALT_GIC_CPUIF_GICC_AEOIR_t GICC_AEOIR; /* ALT_GIC_CPUIF_GICC_AEOIR */
29689  volatile ALT_GIC_CPUIF_GICC_AHPPIR_t GICC_AHPPIR; /* ALT_GIC_CPUIF_GICC_AHPPIR */
29690  volatile uint32_t _pad_0x2c_0xcf[41]; /* *UNDEFINED* */
29691  volatile ALT_GIC_CPUIF_GICC_APR0_t GICC_APR0; /* ALT_GIC_CPUIF_GICC_APR0 */
29692  volatile uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */
29693  volatile ALT_GIC_CPUIF_GICC_NSAPR0_t GICC_NSAPR0; /* ALT_GIC_CPUIF_GICC_NSAPR0 */
29694  volatile uint32_t _pad_0xe4_0xfb[6]; /* *UNDEFINED* */
29695  volatile ALT_GIC_CPUIF_GICC_IIDR_t GICC_IIDR; /* ALT_GIC_CPUIF_GICC_IIDR */
29696  volatile uint32_t _pad_0x100_0xfff[960]; /* *UNDEFINED* */
29697  volatile ALT_GIC_CPUIF_GICC_DIR_t GICC_DIR; /* ALT_GIC_CPUIF_GICC_DIR */
29698  volatile uint32_t _pad_0x1004_0x2000[1023]; /* *UNDEFINED* */
29699 };
29700 
29701 /* The typedef declaration for register group ALT_GIC_CPUIF. */
29702 typedef struct ALT_GIC_CPUIF_s ALT_GIC_CPUIF_t;
29703 /* The struct declaration for the raw register contents of register group ALT_GIC_CPUIF. */
29704 struct ALT_GIC_CPUIF_raw_s
29705 {
29706  volatile uint32_t GICC_CTLR; /* ALT_GIC_CPUIF_GICC_CTLR */
29707  volatile uint32_t GICC_PMR; /* ALT_GIC_CPUIF_GICC_PMR */
29708  volatile uint32_t GICC_BPR; /* ALT_GIC_CPUIF_GICC_BPR */
29709  volatile uint32_t GICC_IAR; /* ALT_GIC_CPUIF_GICC_IAR */
29710  volatile uint32_t GICC_EOIR; /* ALT_GIC_CPUIF_GICC_EOIR */
29711  volatile uint32_t GICC_RPR; /* ALT_GIC_CPUIF_GICC_RPR */
29712  volatile uint32_t GICC_HPPIR; /* ALT_GIC_CPUIF_GICC_HPPIR */
29713  volatile uint32_t GICC_ABPR; /* ALT_GIC_CPUIF_GICC_ABPR */
29714  volatile uint32_t GICC_AIAR; /* ALT_GIC_CPUIF_GICC_AIAR */
29715  volatile uint32_t GICC_AEOIR; /* ALT_GIC_CPUIF_GICC_AEOIR */
29716  volatile uint32_t GICC_AHPPIR; /* ALT_GIC_CPUIF_GICC_AHPPIR */
29717  volatile uint32_t _pad_0x2c_0xcf[41]; /* *UNDEFINED* */
29718  volatile uint32_t GICC_APR0; /* ALT_GIC_CPUIF_GICC_APR0 */
29719  volatile uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */
29720  volatile uint32_t GICC_NSAPR0; /* ALT_GIC_CPUIF_GICC_NSAPR0 */
29721  volatile uint32_t _pad_0xe4_0xfb[6]; /* *UNDEFINED* */
29722  volatile uint32_t GICC_IIDR; /* ALT_GIC_CPUIF_GICC_IIDR */
29723  volatile uint32_t _pad_0x100_0xfff[960]; /* *UNDEFINED* */
29724  volatile uint32_t GICC_DIR; /* ALT_GIC_CPUIF_GICC_DIR */
29725  volatile uint32_t _pad_0x1004_0x2000[1023]; /* *UNDEFINED* */
29726 };
29727 
29728 /* The typedef declaration for the raw register contents of register group ALT_GIC_CPUIF. */
29729 typedef struct ALT_GIC_CPUIF_raw_s ALT_GIC_CPUIF_raw_t;
29730 #endif /* __ASSEMBLY__ */
29731 
29732 
29733 /*
29734  * Component : Virtual CPU interface control registers - GIC_VCPUIF
29735  * Virtual CPU interface control registers
29736  *
29737  * Memory map for the GIC virtual CPU interface control registers. Contains all
29738  * registers with the GICH prefix. Note: This provides access to the control
29739  * registers for the current CPU. It is expected that this block will only be made
29740  * accessible to the hypervisor.
29741  *
29742  */
29743 /*
29744  * Register : GICH_HCR
29745  *
29746  * Hypervisor Control Register
29747  *
29748  * Register Layout
29749  *
29750  * Bits | Access | Reset | Description
29751  * :-------|:-------|:--------|:------------
29752  * [31:0] | RW | Unknown | Empty
29753  *
29754  */
29755 /*
29756  * Field : Empty - fld
29757  *
29758  * Placeholder
29759  *
29760  * Field Access Macros:
29761  *
29762  */
29763 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_GICH_HCR_FLD register field. */
29764 #define ALT_GIC_VCPUIF_GICH_HCR_FLD_LSB 0
29765 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_GICH_HCR_FLD register field. */
29766 #define ALT_GIC_VCPUIF_GICH_HCR_FLD_MSB 31
29767 /* The width in bits of the ALT_GIC_VCPUIF_GICH_HCR_FLD register field. */
29768 #define ALT_GIC_VCPUIF_GICH_HCR_FLD_WIDTH 32
29769 /* The mask used to set the ALT_GIC_VCPUIF_GICH_HCR_FLD register field value. */
29770 #define ALT_GIC_VCPUIF_GICH_HCR_FLD_SET_MSK 0xffffffff
29771 /* The mask used to clear the ALT_GIC_VCPUIF_GICH_HCR_FLD register field value. */
29772 #define ALT_GIC_VCPUIF_GICH_HCR_FLD_CLR_MSK 0x00000000
29773 /* The reset value of the ALT_GIC_VCPUIF_GICH_HCR_FLD register field is UNKNOWN. */
29774 #define ALT_GIC_VCPUIF_GICH_HCR_FLD_RESET 0x0
29775 /* Extracts the ALT_GIC_VCPUIF_GICH_HCR_FLD field value from a register. */
29776 #define ALT_GIC_VCPUIF_GICH_HCR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29777 /* Produces a ALT_GIC_VCPUIF_GICH_HCR_FLD register field value suitable for setting the register. */
29778 #define ALT_GIC_VCPUIF_GICH_HCR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29779 
29780 #ifndef __ASSEMBLY__
29781 /*
29782  * WARNING: The C register and register group struct declarations are provided for
29783  * convenience and illustrative purposes. They should, however, be used with
29784  * caution as the C language standard provides no guarantees about the alignment or
29785  * atomicity of device memory accesses. The recommended practice for coding device
29786  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29787  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29788  * alt_write_dword() functions for 64 bit registers.
29789  *
29790  * The struct declaration for register ALT_GIC_VCPUIF_GICH_HCR.
29791  */
29792 struct ALT_GIC_VCPUIF_GICH_HCR_s
29793 {
29794  volatile uint32_t fld : 32; /* Empty */
29795 };
29796 
29797 /* The typedef declaration for register ALT_GIC_VCPUIF_GICH_HCR. */
29798 typedef struct ALT_GIC_VCPUIF_GICH_HCR_s ALT_GIC_VCPUIF_GICH_HCR_t;
29799 #endif /* __ASSEMBLY__ */
29800 
29801 /* The reset value of the ALT_GIC_VCPUIF_GICH_HCR register. */
29802 #define ALT_GIC_VCPUIF_GICH_HCR_RESET 0x00000000
29803 /* The byte offset of the ALT_GIC_VCPUIF_GICH_HCR register from the beginning of the component. */
29804 #define ALT_GIC_VCPUIF_GICH_HCR_OFST 0x0
29805 /* The address of the ALT_GIC_VCPUIF_GICH_HCR register. */
29806 #define ALT_GIC_VCPUIF_GICH_HCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GIC_VCPUIF_GICH_HCR_OFST))
29807 
29808 /*
29809  * Register : GICH_VTR
29810  *
29811  * VGIC Type Register
29812  *
29813  * Register Layout
29814  *
29815  * Bits | Access | Reset | Description
29816  * :-------|:-------|:-----------|:------------
29817  * [31:0] | RW | 0x90000003 | Empty
29818  *
29819  */
29820 /*
29821  * Field : Empty - fld
29822  *
29823  * Placeholder
29824  *
29825  * Field Access Macros:
29826  *
29827  */
29828 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_GICH_VTR_FLD register field. */
29829 #define ALT_GIC_VCPUIF_GICH_VTR_FLD_LSB 0
29830 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_GICH_VTR_FLD register field. */
29831 #define ALT_GIC_VCPUIF_GICH_VTR_FLD_MSB 31
29832 /* The width in bits of the ALT_GIC_VCPUIF_GICH_VTR_FLD register field. */
29833 #define ALT_GIC_VCPUIF_GICH_VTR_FLD_WIDTH 32
29834 /* The mask used to set the ALT_GIC_VCPUIF_GICH_VTR_FLD register field value. */
29835 #define ALT_GIC_VCPUIF_GICH_VTR_FLD_SET_MSK 0xffffffff
29836 /* The mask used to clear the ALT_GIC_VCPUIF_GICH_VTR_FLD register field value. */
29837 #define ALT_GIC_VCPUIF_GICH_VTR_FLD_CLR_MSK 0x00000000
29838 /* The reset value of the ALT_GIC_VCPUIF_GICH_VTR_FLD register field. */
29839 #define ALT_GIC_VCPUIF_GICH_VTR_FLD_RESET 0x90000003
29840 /* Extracts the ALT_GIC_VCPUIF_GICH_VTR_FLD field value from a register. */
29841 #define ALT_GIC_VCPUIF_GICH_VTR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29842 /* Produces a ALT_GIC_VCPUIF_GICH_VTR_FLD register field value suitable for setting the register. */
29843 #define ALT_GIC_VCPUIF_GICH_VTR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29844 
29845 #ifndef __ASSEMBLY__
29846 /*
29847  * WARNING: The C register and register group struct declarations are provided for
29848  * convenience and illustrative purposes. They should, however, be used with
29849  * caution as the C language standard provides no guarantees about the alignment or
29850  * atomicity of device memory accesses. The recommended practice for coding device
29851  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29852  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29853  * alt_write_dword() functions for 64 bit registers.
29854  *
29855  * The struct declaration for register ALT_GIC_VCPUIF_GICH_VTR.
29856  */
29857 struct ALT_GIC_VCPUIF_GICH_VTR_s
29858 {
29859  volatile uint32_t fld : 32; /* Empty */
29860 };
29861 
29862 /* The typedef declaration for register ALT_GIC_VCPUIF_GICH_VTR. */
29863 typedef struct ALT_GIC_VCPUIF_GICH_VTR_s ALT_GIC_VCPUIF_GICH_VTR_t;
29864 #endif /* __ASSEMBLY__ */
29865 
29866 /* The reset value of the ALT_GIC_VCPUIF_GICH_VTR register. */
29867 #define ALT_GIC_VCPUIF_GICH_VTR_RESET 0x90000003
29868 /* The byte offset of the ALT_GIC_VCPUIF_GICH_VTR register from the beginning of the component. */
29869 #define ALT_GIC_VCPUIF_GICH_VTR_OFST 0x4
29870 /* The address of the ALT_GIC_VCPUIF_GICH_VTR register. */
29871 #define ALT_GIC_VCPUIF_GICH_VTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GIC_VCPUIF_GICH_VTR_OFST))
29872 
29873 /*
29874  * Register : GICH_VMCR
29875  *
29876  * Virtual Machine Control Register
29877  *
29878  * Register Layout
29879  *
29880  * Bits | Access | Reset | Description
29881  * :-------|:-------|:--------|:------------
29882  * [31:0] | RW | Unknown | Empty
29883  *
29884  */
29885 /*
29886  * Field : Empty - fld
29887  *
29888  * Placeholder
29889  *
29890  * Field Access Macros:
29891  *
29892  */
29893 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_GICH_VMCR_FLD register field. */
29894 #define ALT_GIC_VCPUIF_GICH_VMCR_FLD_LSB 0
29895 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_GICH_VMCR_FLD register field. */
29896 #define ALT_GIC_VCPUIF_GICH_VMCR_FLD_MSB 31
29897 /* The width in bits of the ALT_GIC_VCPUIF_GICH_VMCR_FLD register field. */
29898 #define ALT_GIC_VCPUIF_GICH_VMCR_FLD_WIDTH 32
29899 /* The mask used to set the ALT_GIC_VCPUIF_GICH_VMCR_FLD register field value. */
29900 #define ALT_GIC_VCPUIF_GICH_VMCR_FLD_SET_MSK 0xffffffff
29901 /* The mask used to clear the ALT_GIC_VCPUIF_GICH_VMCR_FLD register field value. */
29902 #define ALT_GIC_VCPUIF_GICH_VMCR_FLD_CLR_MSK 0x00000000
29903 /* The reset value of the ALT_GIC_VCPUIF_GICH_VMCR_FLD register field is UNKNOWN. */
29904 #define ALT_GIC_VCPUIF_GICH_VMCR_FLD_RESET 0x0
29905 /* Extracts the ALT_GIC_VCPUIF_GICH_VMCR_FLD field value from a register. */
29906 #define ALT_GIC_VCPUIF_GICH_VMCR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29907 /* Produces a ALT_GIC_VCPUIF_GICH_VMCR_FLD register field value suitable for setting the register. */
29908 #define ALT_GIC_VCPUIF_GICH_VMCR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29909 
29910 #ifndef __ASSEMBLY__
29911 /*
29912  * WARNING: The C register and register group struct declarations are provided for
29913  * convenience and illustrative purposes. They should, however, be used with
29914  * caution as the C language standard provides no guarantees about the alignment or
29915  * atomicity of device memory accesses. The recommended practice for coding device
29916  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29917  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29918  * alt_write_dword() functions for 64 bit registers.
29919  *
29920  * The struct declaration for register ALT_GIC_VCPUIF_GICH_VMCR.
29921  */
29922 struct ALT_GIC_VCPUIF_GICH_VMCR_s
29923 {
29924  volatile uint32_t fld : 32; /* Empty */
29925 };
29926 
29927 /* The typedef declaration for register ALT_GIC_VCPUIF_GICH_VMCR. */
29928 typedef struct ALT_GIC_VCPUIF_GICH_VMCR_s ALT_GIC_VCPUIF_GICH_VMCR_t;
29929 #endif /* __ASSEMBLY__ */
29930 
29931 /* The reset value of the ALT_GIC_VCPUIF_GICH_VMCR register. */
29932 #define ALT_GIC_VCPUIF_GICH_VMCR_RESET 0x004c0000
29933 /* The byte offset of the ALT_GIC_VCPUIF_GICH_VMCR register from the beginning of the component. */
29934 #define ALT_GIC_VCPUIF_GICH_VMCR_OFST 0x8
29935 /* The address of the ALT_GIC_VCPUIF_GICH_VMCR register. */
29936 #define ALT_GIC_VCPUIF_GICH_VMCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GIC_VCPUIF_GICH_VMCR_OFST))
29937 
29938 /*
29939  * Register : GICH_MISR
29940  *
29941  * Maintenance Interrupt Status Register
29942  *
29943  * Register Layout
29944  *
29945  * Bits | Access | Reset | Description
29946  * :-------|:-------|:--------|:------------
29947  * [31:0] | RW | Unknown | Empty
29948  *
29949  */
29950 /*
29951  * Field : Empty - fld
29952  *
29953  * Placeholder
29954  *
29955  * Field Access Macros:
29956  *
29957  */
29958 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_GICH_MISR_FLD register field. */
29959 #define ALT_GIC_VCPUIF_GICH_MISR_FLD_LSB 0
29960 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_GICH_MISR_FLD register field. */
29961 #define ALT_GIC_VCPUIF_GICH_MISR_FLD_MSB 31
29962 /* The width in bits of the ALT_GIC_VCPUIF_GICH_MISR_FLD register field. */
29963 #define ALT_GIC_VCPUIF_GICH_MISR_FLD_WIDTH 32
29964 /* The mask used to set the ALT_GIC_VCPUIF_GICH_MISR_FLD register field value. */
29965 #define ALT_GIC_VCPUIF_GICH_MISR_FLD_SET_MSK 0xffffffff
29966 /* The mask used to clear the ALT_GIC_VCPUIF_GICH_MISR_FLD register field value. */
29967 #define ALT_GIC_VCPUIF_GICH_MISR_FLD_CLR_MSK 0x00000000
29968 /* The reset value of the ALT_GIC_VCPUIF_GICH_MISR_FLD register field is UNKNOWN. */
29969 #define ALT_GIC_VCPUIF_GICH_MISR_FLD_RESET 0x0
29970 /* Extracts the ALT_GIC_VCPUIF_GICH_MISR_FLD field value from a register. */
29971 #define ALT_GIC_VCPUIF_GICH_MISR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
29972 /* Produces a ALT_GIC_VCPUIF_GICH_MISR_FLD register field value suitable for setting the register. */
29973 #define ALT_GIC_VCPUIF_GICH_MISR_FLD_SET(value) (((value) << 0) & 0xffffffff)
29974 
29975 #ifndef __ASSEMBLY__
29976 /*
29977  * WARNING: The C register and register group struct declarations are provided for
29978  * convenience and illustrative purposes. They should, however, be used with
29979  * caution as the C language standard provides no guarantees about the alignment or
29980  * atomicity of device memory accesses. The recommended practice for coding device
29981  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
29982  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
29983  * alt_write_dword() functions for 64 bit registers.
29984  *
29985  * The struct declaration for register ALT_GIC_VCPUIF_GICH_MISR.
29986  */
29987 struct ALT_GIC_VCPUIF_GICH_MISR_s
29988 {
29989  volatile uint32_t fld : 32; /* Empty */
29990 };
29991 
29992 /* The typedef declaration for register ALT_GIC_VCPUIF_GICH_MISR. */
29993 typedef struct ALT_GIC_VCPUIF_GICH_MISR_s ALT_GIC_VCPUIF_GICH_MISR_t;
29994 #endif /* __ASSEMBLY__ */
29995 
29996 /* The reset value of the ALT_GIC_VCPUIF_GICH_MISR register. */
29997 #define ALT_GIC_VCPUIF_GICH_MISR_RESET 0x00000000
29998 /* The byte offset of the ALT_GIC_VCPUIF_GICH_MISR register from the beginning of the component. */
29999 #define ALT_GIC_VCPUIF_GICH_MISR_OFST 0x10
30000 /* The address of the ALT_GIC_VCPUIF_GICH_MISR register. */
30001 #define ALT_GIC_VCPUIF_GICH_MISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GIC_VCPUIF_GICH_MISR_OFST))
30002 
30003 /*
30004  * Register : GICH_EISR0
30005  *
30006  * End of Interrupt Status Register
30007  *
30008  * Register Layout
30009  *
30010  * Bits | Access | Reset | Description
30011  * :-------|:-------|:--------|:------------
30012  * [31:0] | RW | Unknown | Empty
30013  *
30014  */
30015 /*
30016  * Field : Empty - fld
30017  *
30018  * Placeholder
30019  *
30020  * Field Access Macros:
30021  *
30022  */
30023 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_GICH_EISR0_FLD register field. */
30024 #define ALT_GIC_VCPUIF_GICH_EISR0_FLD_LSB 0
30025 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_GICH_EISR0_FLD register field. */
30026 #define ALT_GIC_VCPUIF_GICH_EISR0_FLD_MSB 31
30027 /* The width in bits of the ALT_GIC_VCPUIF_GICH_EISR0_FLD register field. */
30028 #define ALT_GIC_VCPUIF_GICH_EISR0_FLD_WIDTH 32
30029 /* The mask used to set the ALT_GIC_VCPUIF_GICH_EISR0_FLD register field value. */
30030 #define ALT_GIC_VCPUIF_GICH_EISR0_FLD_SET_MSK 0xffffffff
30031 /* The mask used to clear the ALT_GIC_VCPUIF_GICH_EISR0_FLD register field value. */
30032 #define ALT_GIC_VCPUIF_GICH_EISR0_FLD_CLR_MSK 0x00000000
30033 /* The reset value of the ALT_GIC_VCPUIF_GICH_EISR0_FLD register field is UNKNOWN. */
30034 #define ALT_GIC_VCPUIF_GICH_EISR0_FLD_RESET 0x0
30035 /* Extracts the ALT_GIC_VCPUIF_GICH_EISR0_FLD field value from a register. */
30036 #define ALT_GIC_VCPUIF_GICH_EISR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30037 /* Produces a ALT_GIC_VCPUIF_GICH_EISR0_FLD register field value suitable for setting the register. */
30038 #define ALT_GIC_VCPUIF_GICH_EISR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
30039 
30040 #ifndef __ASSEMBLY__
30041 /*
30042  * WARNING: The C register and register group struct declarations are provided for
30043  * convenience and illustrative purposes. They should, however, be used with
30044  * caution as the C language standard provides no guarantees about the alignment or
30045  * atomicity of device memory accesses. The recommended practice for coding device
30046  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30047  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30048  * alt_write_dword() functions for 64 bit registers.
30049  *
30050  * The struct declaration for register ALT_GIC_VCPUIF_GICH_EISR0.
30051  */
30052 struct ALT_GIC_VCPUIF_GICH_EISR0_s
30053 {
30054  volatile uint32_t fld : 32; /* Empty */
30055 };
30056 
30057 /* The typedef declaration for register ALT_GIC_VCPUIF_GICH_EISR0. */
30058 typedef struct ALT_GIC_VCPUIF_GICH_EISR0_s ALT_GIC_VCPUIF_GICH_EISR0_t;
30059 #endif /* __ASSEMBLY__ */
30060 
30061 /* The reset value of the ALT_GIC_VCPUIF_GICH_EISR0 register. */
30062 #define ALT_GIC_VCPUIF_GICH_EISR0_RESET 0x00000000
30063 /* The byte offset of the ALT_GIC_VCPUIF_GICH_EISR0 register from the beginning of the component. */
30064 #define ALT_GIC_VCPUIF_GICH_EISR0_OFST 0x20
30065 /* The address of the ALT_GIC_VCPUIF_GICH_EISR0 register. */
30066 #define ALT_GIC_VCPUIF_GICH_EISR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GIC_VCPUIF_GICH_EISR0_OFST))
30067 
30068 /*
30069  * Register : GICH_ELSR0
30070  *
30071  * Empty List register Status Register
30072  *
30073  * Register Layout
30074  *
30075  * Bits | Access | Reset | Description
30076  * :-------|:-------|:--------|:------------
30077  * [31:0] | RW | Unknown | Empty
30078  *
30079  */
30080 /*
30081  * Field : Empty - fld
30082  *
30083  * Placeholder
30084  *
30085  * Field Access Macros:
30086  *
30087  */
30088 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_GICH_ELSR0_FLD register field. */
30089 #define ALT_GIC_VCPUIF_GICH_ELSR0_FLD_LSB 0
30090 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_GICH_ELSR0_FLD register field. */
30091 #define ALT_GIC_VCPUIF_GICH_ELSR0_FLD_MSB 31
30092 /* The width in bits of the ALT_GIC_VCPUIF_GICH_ELSR0_FLD register field. */
30093 #define ALT_GIC_VCPUIF_GICH_ELSR0_FLD_WIDTH 32
30094 /* The mask used to set the ALT_GIC_VCPUIF_GICH_ELSR0_FLD register field value. */
30095 #define ALT_GIC_VCPUIF_GICH_ELSR0_FLD_SET_MSK 0xffffffff
30096 /* The mask used to clear the ALT_GIC_VCPUIF_GICH_ELSR0_FLD register field value. */
30097 #define ALT_GIC_VCPUIF_GICH_ELSR0_FLD_CLR_MSK 0x00000000
30098 /* The reset value of the ALT_GIC_VCPUIF_GICH_ELSR0_FLD register field is UNKNOWN. */
30099 #define ALT_GIC_VCPUIF_GICH_ELSR0_FLD_RESET 0x0
30100 /* Extracts the ALT_GIC_VCPUIF_GICH_ELSR0_FLD field value from a register. */
30101 #define ALT_GIC_VCPUIF_GICH_ELSR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30102 /* Produces a ALT_GIC_VCPUIF_GICH_ELSR0_FLD register field value suitable for setting the register. */
30103 #define ALT_GIC_VCPUIF_GICH_ELSR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
30104 
30105 #ifndef __ASSEMBLY__
30106 /*
30107  * WARNING: The C register and register group struct declarations are provided for
30108  * convenience and illustrative purposes. They should, however, be used with
30109  * caution as the C language standard provides no guarantees about the alignment or
30110  * atomicity of device memory accesses. The recommended practice for coding device
30111  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30112  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30113  * alt_write_dword() functions for 64 bit registers.
30114  *
30115  * The struct declaration for register ALT_GIC_VCPUIF_GICH_ELSR0.
30116  */
30117 struct ALT_GIC_VCPUIF_GICH_ELSR0_s
30118 {
30119  volatile uint32_t fld : 32; /* Empty */
30120 };
30121 
30122 /* The typedef declaration for register ALT_GIC_VCPUIF_GICH_ELSR0. */
30123 typedef struct ALT_GIC_VCPUIF_GICH_ELSR0_s ALT_GIC_VCPUIF_GICH_ELSR0_t;
30124 #endif /* __ASSEMBLY__ */
30125 
30126 /* The reset value of the ALT_GIC_VCPUIF_GICH_ELSR0 register. */
30127 #define ALT_GIC_VCPUIF_GICH_ELSR0_RESET 0x0000000f
30128 /* The byte offset of the ALT_GIC_VCPUIF_GICH_ELSR0 register from the beginning of the component. */
30129 #define ALT_GIC_VCPUIF_GICH_ELSR0_OFST 0x30
30130 /* The address of the ALT_GIC_VCPUIF_GICH_ELSR0 register. */
30131 #define ALT_GIC_VCPUIF_GICH_ELSR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GIC_VCPUIF_GICH_ELSR0_OFST))
30132 
30133 /*
30134  * Register : GICH_APR0
30135  *
30136  * Active Priority Register
30137  *
30138  * Register Layout
30139  *
30140  * Bits | Access | Reset | Description
30141  * :-------|:-------|:------|:------------
30142  * [31:0] | RW | 0x0 | Empty
30143  *
30144  */
30145 /*
30146  * Field : Empty - fld
30147  *
30148  * Placeholder
30149  *
30150  * Field Access Macros:
30151  *
30152  */
30153 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_GICH_APR0_FLD register field. */
30154 #define ALT_GIC_VCPUIF_GICH_APR0_FLD_LSB 0
30155 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_GICH_APR0_FLD register field. */
30156 #define ALT_GIC_VCPUIF_GICH_APR0_FLD_MSB 31
30157 /* The width in bits of the ALT_GIC_VCPUIF_GICH_APR0_FLD register field. */
30158 #define ALT_GIC_VCPUIF_GICH_APR0_FLD_WIDTH 32
30159 /* The mask used to set the ALT_GIC_VCPUIF_GICH_APR0_FLD register field value. */
30160 #define ALT_GIC_VCPUIF_GICH_APR0_FLD_SET_MSK 0xffffffff
30161 /* The mask used to clear the ALT_GIC_VCPUIF_GICH_APR0_FLD register field value. */
30162 #define ALT_GIC_VCPUIF_GICH_APR0_FLD_CLR_MSK 0x00000000
30163 /* The reset value of the ALT_GIC_VCPUIF_GICH_APR0_FLD register field. */
30164 #define ALT_GIC_VCPUIF_GICH_APR0_FLD_RESET 0x0
30165 /* Extracts the ALT_GIC_VCPUIF_GICH_APR0_FLD field value from a register. */
30166 #define ALT_GIC_VCPUIF_GICH_APR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30167 /* Produces a ALT_GIC_VCPUIF_GICH_APR0_FLD register field value suitable for setting the register. */
30168 #define ALT_GIC_VCPUIF_GICH_APR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
30169 
30170 #ifndef __ASSEMBLY__
30171 /*
30172  * WARNING: The C register and register group struct declarations are provided for
30173  * convenience and illustrative purposes. They should, however, be used with
30174  * caution as the C language standard provides no guarantees about the alignment or
30175  * atomicity of device memory accesses. The recommended practice for coding device
30176  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30177  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30178  * alt_write_dword() functions for 64 bit registers.
30179  *
30180  * The struct declaration for register ALT_GIC_VCPUIF_GICH_APR0.
30181  */
30182 struct ALT_GIC_VCPUIF_GICH_APR0_s
30183 {
30184  volatile uint32_t fld : 32; /* Empty */
30185 };
30186 
30187 /* The typedef declaration for register ALT_GIC_VCPUIF_GICH_APR0. */
30188 typedef struct ALT_GIC_VCPUIF_GICH_APR0_s ALT_GIC_VCPUIF_GICH_APR0_t;
30189 #endif /* __ASSEMBLY__ */
30190 
30191 /* The reset value of the ALT_GIC_VCPUIF_GICH_APR0 register. */
30192 #define ALT_GIC_VCPUIF_GICH_APR0_RESET 0x00000000
30193 /* The byte offset of the ALT_GIC_VCPUIF_GICH_APR0 register from the beginning of the component. */
30194 #define ALT_GIC_VCPUIF_GICH_APR0_OFST 0xf0
30195 /* The address of the ALT_GIC_VCPUIF_GICH_APR0 register. */
30196 #define ALT_GIC_VCPUIF_GICH_APR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GIC_VCPUIF_GICH_APR0_OFST))
30197 
30198 /*
30199  * Register : GICH_LR0
30200  *
30201  * List Register 0
30202  *
30203  * Register Layout
30204  *
30205  * Bits | Access | Reset | Description
30206  * :-------|:-------|:------|:------------
30207  * [31:0] | RW | 0x0 | Empty
30208  *
30209  */
30210 /*
30211  * Field : Empty - fld
30212  *
30213  * Placeholder
30214  *
30215  * Field Access Macros:
30216  *
30217  */
30218 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_GICH_LR0_FLD register field. */
30219 #define ALT_GIC_VCPUIF_GICH_LR0_FLD_LSB 0
30220 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_GICH_LR0_FLD register field. */
30221 #define ALT_GIC_VCPUIF_GICH_LR0_FLD_MSB 31
30222 /* The width in bits of the ALT_GIC_VCPUIF_GICH_LR0_FLD register field. */
30223 #define ALT_GIC_VCPUIF_GICH_LR0_FLD_WIDTH 32
30224 /* The mask used to set the ALT_GIC_VCPUIF_GICH_LR0_FLD register field value. */
30225 #define ALT_GIC_VCPUIF_GICH_LR0_FLD_SET_MSK 0xffffffff
30226 /* The mask used to clear the ALT_GIC_VCPUIF_GICH_LR0_FLD register field value. */
30227 #define ALT_GIC_VCPUIF_GICH_LR0_FLD_CLR_MSK 0x00000000
30228 /* The reset value of the ALT_GIC_VCPUIF_GICH_LR0_FLD register field. */
30229 #define ALT_GIC_VCPUIF_GICH_LR0_FLD_RESET 0x0
30230 /* Extracts the ALT_GIC_VCPUIF_GICH_LR0_FLD field value from a register. */
30231 #define ALT_GIC_VCPUIF_GICH_LR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30232 /* Produces a ALT_GIC_VCPUIF_GICH_LR0_FLD register field value suitable for setting the register. */
30233 #define ALT_GIC_VCPUIF_GICH_LR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
30234 
30235 #ifndef __ASSEMBLY__
30236 /*
30237  * WARNING: The C register and register group struct declarations are provided for
30238  * convenience and illustrative purposes. They should, however, be used with
30239  * caution as the C language standard provides no guarantees about the alignment or
30240  * atomicity of device memory accesses. The recommended practice for coding device
30241  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30242  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30243  * alt_write_dword() functions for 64 bit registers.
30244  *
30245  * The struct declaration for register ALT_GIC_VCPUIF_GICH_LR0.
30246  */
30247 struct ALT_GIC_VCPUIF_GICH_LR0_s
30248 {
30249  volatile uint32_t fld : 32; /* Empty */
30250 };
30251 
30252 /* The typedef declaration for register ALT_GIC_VCPUIF_GICH_LR0. */
30253 typedef struct ALT_GIC_VCPUIF_GICH_LR0_s ALT_GIC_VCPUIF_GICH_LR0_t;
30254 #endif /* __ASSEMBLY__ */
30255 
30256 /* The reset value of the ALT_GIC_VCPUIF_GICH_LR0 register. */
30257 #define ALT_GIC_VCPUIF_GICH_LR0_RESET 0x00000000
30258 /* The byte offset of the ALT_GIC_VCPUIF_GICH_LR0 register from the beginning of the component. */
30259 #define ALT_GIC_VCPUIF_GICH_LR0_OFST 0x100
30260 /* The address of the ALT_GIC_VCPUIF_GICH_LR0 register. */
30261 #define ALT_GIC_VCPUIF_GICH_LR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GIC_VCPUIF_GICH_LR0_OFST))
30262 
30263 /*
30264  * Register : GICH_LR1
30265  *
30266  * List Register 1
30267  *
30268  * Register Layout
30269  *
30270  * Bits | Access | Reset | Description
30271  * :-------|:-------|:------|:------------
30272  * [31:0] | RW | 0x0 | Empty
30273  *
30274  */
30275 /*
30276  * Field : Empty - fld
30277  *
30278  * Placeholder
30279  *
30280  * Field Access Macros:
30281  *
30282  */
30283 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_GICH_LR1_FLD register field. */
30284 #define ALT_GIC_VCPUIF_GICH_LR1_FLD_LSB 0
30285 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_GICH_LR1_FLD register field. */
30286 #define ALT_GIC_VCPUIF_GICH_LR1_FLD_MSB 31
30287 /* The width in bits of the ALT_GIC_VCPUIF_GICH_LR1_FLD register field. */
30288 #define ALT_GIC_VCPUIF_GICH_LR1_FLD_WIDTH 32
30289 /* The mask used to set the ALT_GIC_VCPUIF_GICH_LR1_FLD register field value. */
30290 #define ALT_GIC_VCPUIF_GICH_LR1_FLD_SET_MSK 0xffffffff
30291 /* The mask used to clear the ALT_GIC_VCPUIF_GICH_LR1_FLD register field value. */
30292 #define ALT_GIC_VCPUIF_GICH_LR1_FLD_CLR_MSK 0x00000000
30293 /* The reset value of the ALT_GIC_VCPUIF_GICH_LR1_FLD register field. */
30294 #define ALT_GIC_VCPUIF_GICH_LR1_FLD_RESET 0x0
30295 /* Extracts the ALT_GIC_VCPUIF_GICH_LR1_FLD field value from a register. */
30296 #define ALT_GIC_VCPUIF_GICH_LR1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30297 /* Produces a ALT_GIC_VCPUIF_GICH_LR1_FLD register field value suitable for setting the register. */
30298 #define ALT_GIC_VCPUIF_GICH_LR1_FLD_SET(value) (((value) << 0) & 0xffffffff)
30299 
30300 #ifndef __ASSEMBLY__
30301 /*
30302  * WARNING: The C register and register group struct declarations are provided for
30303  * convenience and illustrative purposes. They should, however, be used with
30304  * caution as the C language standard provides no guarantees about the alignment or
30305  * atomicity of device memory accesses. The recommended practice for coding device
30306  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30307  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30308  * alt_write_dword() functions for 64 bit registers.
30309  *
30310  * The struct declaration for register ALT_GIC_VCPUIF_GICH_LR1.
30311  */
30312 struct ALT_GIC_VCPUIF_GICH_LR1_s
30313 {
30314  volatile uint32_t fld : 32; /* Empty */
30315 };
30316 
30317 /* The typedef declaration for register ALT_GIC_VCPUIF_GICH_LR1. */
30318 typedef struct ALT_GIC_VCPUIF_GICH_LR1_s ALT_GIC_VCPUIF_GICH_LR1_t;
30319 #endif /* __ASSEMBLY__ */
30320 
30321 /* The reset value of the ALT_GIC_VCPUIF_GICH_LR1 register. */
30322 #define ALT_GIC_VCPUIF_GICH_LR1_RESET 0x00000000
30323 /* The byte offset of the ALT_GIC_VCPUIF_GICH_LR1 register from the beginning of the component. */
30324 #define ALT_GIC_VCPUIF_GICH_LR1_OFST 0x104
30325 /* The address of the ALT_GIC_VCPUIF_GICH_LR1 register. */
30326 #define ALT_GIC_VCPUIF_GICH_LR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GIC_VCPUIF_GICH_LR1_OFST))
30327 
30328 /*
30329  * Register : GICH_LR2
30330  *
30331  * List Register 2
30332  *
30333  * Register Layout
30334  *
30335  * Bits | Access | Reset | Description
30336  * :-------|:-------|:------|:------------
30337  * [31:0] | RW | 0x0 | Empty
30338  *
30339  */
30340 /*
30341  * Field : Empty - fld
30342  *
30343  * Placeholder
30344  *
30345  * Field Access Macros:
30346  *
30347  */
30348 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_GICH_LR2_FLD register field. */
30349 #define ALT_GIC_VCPUIF_GICH_LR2_FLD_LSB 0
30350 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_GICH_LR2_FLD register field. */
30351 #define ALT_GIC_VCPUIF_GICH_LR2_FLD_MSB 31
30352 /* The width in bits of the ALT_GIC_VCPUIF_GICH_LR2_FLD register field. */
30353 #define ALT_GIC_VCPUIF_GICH_LR2_FLD_WIDTH 32
30354 /* The mask used to set the ALT_GIC_VCPUIF_GICH_LR2_FLD register field value. */
30355 #define ALT_GIC_VCPUIF_GICH_LR2_FLD_SET_MSK 0xffffffff
30356 /* The mask used to clear the ALT_GIC_VCPUIF_GICH_LR2_FLD register field value. */
30357 #define ALT_GIC_VCPUIF_GICH_LR2_FLD_CLR_MSK 0x00000000
30358 /* The reset value of the ALT_GIC_VCPUIF_GICH_LR2_FLD register field. */
30359 #define ALT_GIC_VCPUIF_GICH_LR2_FLD_RESET 0x0
30360 /* Extracts the ALT_GIC_VCPUIF_GICH_LR2_FLD field value from a register. */
30361 #define ALT_GIC_VCPUIF_GICH_LR2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30362 /* Produces a ALT_GIC_VCPUIF_GICH_LR2_FLD register field value suitable for setting the register. */
30363 #define ALT_GIC_VCPUIF_GICH_LR2_FLD_SET(value) (((value) << 0) & 0xffffffff)
30364 
30365 #ifndef __ASSEMBLY__
30366 /*
30367  * WARNING: The C register and register group struct declarations are provided for
30368  * convenience and illustrative purposes. They should, however, be used with
30369  * caution as the C language standard provides no guarantees about the alignment or
30370  * atomicity of device memory accesses. The recommended practice for coding device
30371  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30372  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30373  * alt_write_dword() functions for 64 bit registers.
30374  *
30375  * The struct declaration for register ALT_GIC_VCPUIF_GICH_LR2.
30376  */
30377 struct ALT_GIC_VCPUIF_GICH_LR2_s
30378 {
30379  volatile uint32_t fld : 32; /* Empty */
30380 };
30381 
30382 /* The typedef declaration for register ALT_GIC_VCPUIF_GICH_LR2. */
30383 typedef struct ALT_GIC_VCPUIF_GICH_LR2_s ALT_GIC_VCPUIF_GICH_LR2_t;
30384 #endif /* __ASSEMBLY__ */
30385 
30386 /* The reset value of the ALT_GIC_VCPUIF_GICH_LR2 register. */
30387 #define ALT_GIC_VCPUIF_GICH_LR2_RESET 0x00000000
30388 /* The byte offset of the ALT_GIC_VCPUIF_GICH_LR2 register from the beginning of the component. */
30389 #define ALT_GIC_VCPUIF_GICH_LR2_OFST 0x108
30390 /* The address of the ALT_GIC_VCPUIF_GICH_LR2 register. */
30391 #define ALT_GIC_VCPUIF_GICH_LR2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GIC_VCPUIF_GICH_LR2_OFST))
30392 
30393 /*
30394  * Register : GICH_LR3
30395  *
30396  * List Register 3
30397  *
30398  * Register Layout
30399  *
30400  * Bits | Access | Reset | Description
30401  * :-------|:-------|:------|:------------
30402  * [31:0] | RW | 0x0 | Empty
30403  *
30404  */
30405 /*
30406  * Field : Empty - fld
30407  *
30408  * Placeholder
30409  *
30410  * Field Access Macros:
30411  *
30412  */
30413 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_GICH_LR3_FLD register field. */
30414 #define ALT_GIC_VCPUIF_GICH_LR3_FLD_LSB 0
30415 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_GICH_LR3_FLD register field. */
30416 #define ALT_GIC_VCPUIF_GICH_LR3_FLD_MSB 31
30417 /* The width in bits of the ALT_GIC_VCPUIF_GICH_LR3_FLD register field. */
30418 #define ALT_GIC_VCPUIF_GICH_LR3_FLD_WIDTH 32
30419 /* The mask used to set the ALT_GIC_VCPUIF_GICH_LR3_FLD register field value. */
30420 #define ALT_GIC_VCPUIF_GICH_LR3_FLD_SET_MSK 0xffffffff
30421 /* The mask used to clear the ALT_GIC_VCPUIF_GICH_LR3_FLD register field value. */
30422 #define ALT_GIC_VCPUIF_GICH_LR3_FLD_CLR_MSK 0x00000000
30423 /* The reset value of the ALT_GIC_VCPUIF_GICH_LR3_FLD register field. */
30424 #define ALT_GIC_VCPUIF_GICH_LR3_FLD_RESET 0x0
30425 /* Extracts the ALT_GIC_VCPUIF_GICH_LR3_FLD field value from a register. */
30426 #define ALT_GIC_VCPUIF_GICH_LR3_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30427 /* Produces a ALT_GIC_VCPUIF_GICH_LR3_FLD register field value suitable for setting the register. */
30428 #define ALT_GIC_VCPUIF_GICH_LR3_FLD_SET(value) (((value) << 0) & 0xffffffff)
30429 
30430 #ifndef __ASSEMBLY__
30431 /*
30432  * WARNING: The C register and register group struct declarations are provided for
30433  * convenience and illustrative purposes. They should, however, be used with
30434  * caution as the C language standard provides no guarantees about the alignment or
30435  * atomicity of device memory accesses. The recommended practice for coding device
30436  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30437  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30438  * alt_write_dword() functions for 64 bit registers.
30439  *
30440  * The struct declaration for register ALT_GIC_VCPUIF_GICH_LR3.
30441  */
30442 struct ALT_GIC_VCPUIF_GICH_LR3_s
30443 {
30444  volatile uint32_t fld : 32; /* Empty */
30445 };
30446 
30447 /* The typedef declaration for register ALT_GIC_VCPUIF_GICH_LR3. */
30448 typedef struct ALT_GIC_VCPUIF_GICH_LR3_s ALT_GIC_VCPUIF_GICH_LR3_t;
30449 #endif /* __ASSEMBLY__ */
30450 
30451 /* The reset value of the ALT_GIC_VCPUIF_GICH_LR3 register. */
30452 #define ALT_GIC_VCPUIF_GICH_LR3_RESET 0x00000000
30453 /* The byte offset of the ALT_GIC_VCPUIF_GICH_LR3 register from the beginning of the component. */
30454 #define ALT_GIC_VCPUIF_GICH_LR3_OFST 0x10c
30455 /* The address of the ALT_GIC_VCPUIF_GICH_LR3 register. */
30456 #define ALT_GIC_VCPUIF_GICH_LR3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GIC_VCPUIF_GICH_LR3_OFST))
30457 
30458 #ifndef __ASSEMBLY__
30459 /*
30460  * WARNING: The C register and register group struct declarations are provided for
30461  * convenience and illustrative purposes. They should, however, be used with
30462  * caution as the C language standard provides no guarantees about the alignment or
30463  * atomicity of device memory accesses. The recommended practice for coding device
30464  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30465  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30466  * alt_write_dword() functions for 64 bit registers.
30467  *
30468  * The struct declaration for register group ALT_GIC_VCPUIF.
30469  */
30470 struct ALT_GIC_VCPUIF_s
30471 {
30472  volatile ALT_GIC_VCPUIF_GICH_HCR_t GICH_HCR; /* ALT_GIC_VCPUIF_GICH_HCR */
30473  volatile ALT_GIC_VCPUIF_GICH_VTR_t GICH_VTR; /* ALT_GIC_VCPUIF_GICH_VTR */
30474  volatile ALT_GIC_VCPUIF_GICH_VMCR_t GICH_VMCR; /* ALT_GIC_VCPUIF_GICH_VMCR */
30475  volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
30476  volatile ALT_GIC_VCPUIF_GICH_MISR_t GICH_MISR; /* ALT_GIC_VCPUIF_GICH_MISR */
30477  volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
30478  volatile ALT_GIC_VCPUIF_GICH_EISR0_t GICH_EISR0; /* ALT_GIC_VCPUIF_GICH_EISR0 */
30479  volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
30480  volatile ALT_GIC_VCPUIF_GICH_ELSR0_t GICH_ELSR0; /* ALT_GIC_VCPUIF_GICH_ELSR0 */
30481  volatile uint32_t _pad_0x34_0xef[47]; /* *UNDEFINED* */
30482  volatile ALT_GIC_VCPUIF_GICH_APR0_t GICH_APR0; /* ALT_GIC_VCPUIF_GICH_APR0 */
30483  volatile uint32_t _pad_0xf4_0xff[3]; /* *UNDEFINED* */
30484  volatile ALT_GIC_VCPUIF_GICH_LR0_t GICH_LR0; /* ALT_GIC_VCPUIF_GICH_LR0 */
30485  volatile ALT_GIC_VCPUIF_GICH_LR1_t GICH_LR1; /* ALT_GIC_VCPUIF_GICH_LR1 */
30486  volatile ALT_GIC_VCPUIF_GICH_LR2_t GICH_LR2; /* ALT_GIC_VCPUIF_GICH_LR2 */
30487  volatile ALT_GIC_VCPUIF_GICH_LR3_t GICH_LR3; /* ALT_GIC_VCPUIF_GICH_LR3 */
30488  volatile uint32_t _pad_0x110_0x200[60]; /* *UNDEFINED* */
30489 };
30490 
30491 /* The typedef declaration for register group ALT_GIC_VCPUIF. */
30492 typedef struct ALT_GIC_VCPUIF_s ALT_GIC_VCPUIF_t;
30493 /* The struct declaration for the raw register contents of register group ALT_GIC_VCPUIF. */
30494 struct ALT_GIC_VCPUIF_raw_s
30495 {
30496  volatile uint32_t GICH_HCR; /* ALT_GIC_VCPUIF_GICH_HCR */
30497  volatile uint32_t GICH_VTR; /* ALT_GIC_VCPUIF_GICH_VTR */
30498  volatile uint32_t GICH_VMCR; /* ALT_GIC_VCPUIF_GICH_VMCR */
30499  volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
30500  volatile uint32_t GICH_MISR; /* ALT_GIC_VCPUIF_GICH_MISR */
30501  volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
30502  volatile uint32_t GICH_EISR0; /* ALT_GIC_VCPUIF_GICH_EISR0 */
30503  volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
30504  volatile uint32_t GICH_ELSR0; /* ALT_GIC_VCPUIF_GICH_ELSR0 */
30505  volatile uint32_t _pad_0x34_0xef[47]; /* *UNDEFINED* */
30506  volatile uint32_t GICH_APR0; /* ALT_GIC_VCPUIF_GICH_APR0 */
30507  volatile uint32_t _pad_0xf4_0xff[3]; /* *UNDEFINED* */
30508  volatile uint32_t GICH_LR0; /* ALT_GIC_VCPUIF_GICH_LR0 */
30509  volatile uint32_t GICH_LR1; /* ALT_GIC_VCPUIF_GICH_LR1 */
30510  volatile uint32_t GICH_LR2; /* ALT_GIC_VCPUIF_GICH_LR2 */
30511  volatile uint32_t GICH_LR3; /* ALT_GIC_VCPUIF_GICH_LR3 */
30512  volatile uint32_t _pad_0x110_0x200[60]; /* *UNDEFINED* */
30513 };
30514 
30515 /* The typedef declaration for the raw register contents of register group ALT_GIC_VCPUIF. */
30516 typedef struct ALT_GIC_VCPUIF_raw_s ALT_GIC_VCPUIF_raw_t;
30517 #endif /* __ASSEMBLY__ */
30518 
30519 
30520 /*
30521  * Component : Virtual CPU interface memory map - GIC_VCPUIF_HYP_VM
30522  * Virtual CPU interface memory map
30523  *
30524  * Memory map for the GIC virtual CPU interface. Contains all registers with the
30525  * GICV prefix. Note: This provides access to the virtual CPU interface for the
30526  * current CPU. It is expected that software will use the translation tables to
30527  * make this block accessible to the virtual machine in the address space normall
30528  * used for the (physical) CPU interface.
30529  *
30530  */
30531 /*
30532  * Register : GICV_CTLR
30533  *
30534  * Virtual Machine Control Register
30535  *
30536  * Register Layout
30537  *
30538  * Bits | Access | Reset | Description
30539  * :-------|:-------|:--------|:------------
30540  * [31:0] | RW | Unknown | Empty
30541  *
30542  */
30543 /*
30544  * Field : Empty - fld
30545  *
30546  * Placeholder
30547  *
30548  * Field Access Macros:
30549  *
30550  */
30551 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD register field. */
30552 #define ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD_LSB 0
30553 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD register field. */
30554 #define ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD_MSB 31
30555 /* The width in bits of the ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD register field. */
30556 #define ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD_WIDTH 32
30557 /* The mask used to set the ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD register field value. */
30558 #define ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD_SET_MSK 0xffffffff
30559 /* The mask used to clear the ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD register field value. */
30560 #define ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD_CLR_MSK 0x00000000
30561 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD register field is UNKNOWN. */
30562 #define ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD_RESET 0x0
30563 /* Extracts the ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD field value from a register. */
30564 #define ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30565 /* Produces a ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD register field value suitable for setting the register. */
30566 #define ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_FLD_SET(value) (((value) << 0) & 0xffffffff)
30567 
30568 #ifndef __ASSEMBLY__
30569 /*
30570  * WARNING: The C register and register group struct declarations are provided for
30571  * convenience and illustrative purposes. They should, however, be used with
30572  * caution as the C language standard provides no guarantees about the alignment or
30573  * atomicity of device memory accesses. The recommended practice for coding device
30574  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30575  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30576  * alt_write_dword() functions for 64 bit registers.
30577  *
30578  * The struct declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR.
30579  */
30580 struct ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_s
30581 {
30582  volatile uint32_t fld : 32; /* Empty */
30583 };
30584 
30585 /* The typedef declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR. */
30586 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_s ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_t;
30587 #endif /* __ASSEMBLY__ */
30588 
30589 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR register. */
30590 #define ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_RESET 0x00000000
30591 /* The byte offset of the ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR register from the beginning of the component. */
30592 #define ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_OFST 0x0
30593 
30594 /*
30595  * Register : GICV_PMR
30596  *
30597  * VM Priority Mask Register
30598  *
30599  * Register Layout
30600  *
30601  * Bits | Access | Reset | Description
30602  * :-------|:-------|:--------|:------------
30603  * [31:0] | RW | Unknown | Empty
30604  *
30605  */
30606 /*
30607  * Field : Empty - fld
30608  *
30609  * Placeholder
30610  *
30611  * Field Access Macros:
30612  *
30613  */
30614 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD register field. */
30615 #define ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD_LSB 0
30616 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD register field. */
30617 #define ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD_MSB 31
30618 /* The width in bits of the ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD register field. */
30619 #define ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD_WIDTH 32
30620 /* The mask used to set the ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD register field value. */
30621 #define ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD_SET_MSK 0xffffffff
30622 /* The mask used to clear the ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD register field value. */
30623 #define ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD_CLR_MSK 0x00000000
30624 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD register field is UNKNOWN. */
30625 #define ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD_RESET 0x0
30626 /* Extracts the ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD field value from a register. */
30627 #define ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30628 /* Produces a ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD register field value suitable for setting the register. */
30629 #define ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_FLD_SET(value) (((value) << 0) & 0xffffffff)
30630 
30631 #ifndef __ASSEMBLY__
30632 /*
30633  * WARNING: The C register and register group struct declarations are provided for
30634  * convenience and illustrative purposes. They should, however, be used with
30635  * caution as the C language standard provides no guarantees about the alignment or
30636  * atomicity of device memory accesses. The recommended practice for coding device
30637  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30638  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30639  * alt_write_dword() functions for 64 bit registers.
30640  *
30641  * The struct declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_PMR.
30642  */
30643 struct ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_s
30644 {
30645  volatile uint32_t fld : 32; /* Empty */
30646 };
30647 
30648 /* The typedef declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_PMR. */
30649 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_s ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_t;
30650 #endif /* __ASSEMBLY__ */
30651 
30652 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_PMR register. */
30653 #define ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_RESET 0x00000000
30654 /* The byte offset of the ALT_GIC_VCPUIF_HYP_VM_GICV_PMR register from the beginning of the component. */
30655 #define ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_OFST 0x4
30656 
30657 /*
30658  * Register : GICV_BPR
30659  *
30660  * VM Binary Point Register
30661  *
30662  * Register Layout
30663  *
30664  * Bits | Access | Reset | Description
30665  * :-------|:-------|:--------|:------------
30666  * [31:0] | RW | Unknown | Empty
30667  *
30668  */
30669 /*
30670  * Field : Empty - fld
30671  *
30672  * Placeholder
30673  *
30674  * Field Access Macros:
30675  *
30676  */
30677 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD register field. */
30678 #define ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD_LSB 0
30679 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD register field. */
30680 #define ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD_MSB 31
30681 /* The width in bits of the ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD register field. */
30682 #define ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD_WIDTH 32
30683 /* The mask used to set the ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD register field value. */
30684 #define ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD_SET_MSK 0xffffffff
30685 /* The mask used to clear the ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD register field value. */
30686 #define ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD_CLR_MSK 0x00000000
30687 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD register field is UNKNOWN. */
30688 #define ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD_RESET 0x0
30689 /* Extracts the ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD field value from a register. */
30690 #define ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30691 /* Produces a ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD register field value suitable for setting the register. */
30692 #define ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_FLD_SET(value) (((value) << 0) & 0xffffffff)
30693 
30694 #ifndef __ASSEMBLY__
30695 /*
30696  * WARNING: The C register and register group struct declarations are provided for
30697  * convenience and illustrative purposes. They should, however, be used with
30698  * caution as the C language standard provides no guarantees about the alignment or
30699  * atomicity of device memory accesses. The recommended practice for coding device
30700  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30701  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30702  * alt_write_dword() functions for 64 bit registers.
30703  *
30704  * The struct declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_BPR.
30705  */
30706 struct ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_s
30707 {
30708  volatile uint32_t fld : 32; /* Empty */
30709 };
30710 
30711 /* The typedef declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_BPR. */
30712 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_s ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_t;
30713 #endif /* __ASSEMBLY__ */
30714 
30715 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_BPR register. */
30716 #define ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_RESET 0x00000002
30717 /* The byte offset of the ALT_GIC_VCPUIF_HYP_VM_GICV_BPR register from the beginning of the component. */
30718 #define ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_OFST 0x8
30719 
30720 /*
30721  * Register : GICV_IAR
30722  *
30723  * VM Interrupt Acknowledge Register
30724  *
30725  * Register Layout
30726  *
30727  * Bits | Access | Reset | Description
30728  * :-------|:-------|:--------|:------------
30729  * [31:0] | RW | Unknown | Empty
30730  *
30731  */
30732 /*
30733  * Field : Empty - fld
30734  *
30735  * Placeholder
30736  *
30737  * Field Access Macros:
30738  *
30739  */
30740 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD register field. */
30741 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD_LSB 0
30742 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD register field. */
30743 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD_MSB 31
30744 /* The width in bits of the ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD register field. */
30745 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD_WIDTH 32
30746 /* The mask used to set the ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD register field value. */
30747 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD_SET_MSK 0xffffffff
30748 /* The mask used to clear the ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD register field value. */
30749 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD_CLR_MSK 0x00000000
30750 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD register field is UNKNOWN. */
30751 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD_RESET 0x0
30752 /* Extracts the ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD field value from a register. */
30753 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30754 /* Produces a ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD register field value suitable for setting the register. */
30755 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_FLD_SET(value) (((value) << 0) & 0xffffffff)
30756 
30757 #ifndef __ASSEMBLY__
30758 /*
30759  * WARNING: The C register and register group struct declarations are provided for
30760  * convenience and illustrative purposes. They should, however, be used with
30761  * caution as the C language standard provides no guarantees about the alignment or
30762  * atomicity of device memory accesses. The recommended practice for coding device
30763  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30764  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30765  * alt_write_dword() functions for 64 bit registers.
30766  *
30767  * The struct declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_IAR.
30768  */
30769 struct ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_s
30770 {
30771  volatile uint32_t fld : 32; /* Empty */
30772 };
30773 
30774 /* The typedef declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_IAR. */
30775 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_s ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_t;
30776 #endif /* __ASSEMBLY__ */
30777 
30778 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_IAR register. */
30779 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_RESET 0x000003ff
30780 /* The byte offset of the ALT_GIC_VCPUIF_HYP_VM_GICV_IAR register from the beginning of the component. */
30781 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_OFST 0xc
30782 
30783 /*
30784  * Register : GICV_EOIR
30785  *
30786  * VM End of Interrupt Register
30787  *
30788  * Register Layout
30789  *
30790  * Bits | Access | Reset | Description
30791  * :-------|:-------|:--------|:------------
30792  * [31:0] | RW | Unknown | Empty
30793  *
30794  */
30795 /*
30796  * Field : Empty - fld
30797  *
30798  * Placeholder
30799  *
30800  * Field Access Macros:
30801  *
30802  */
30803 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD register field. */
30804 #define ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD_LSB 0
30805 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD register field. */
30806 #define ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD_MSB 31
30807 /* The width in bits of the ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD register field. */
30808 #define ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD_WIDTH 32
30809 /* The mask used to set the ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD register field value. */
30810 #define ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD_SET_MSK 0xffffffff
30811 /* The mask used to clear the ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD register field value. */
30812 #define ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD_CLR_MSK 0x00000000
30813 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD register field is UNKNOWN. */
30814 #define ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD_RESET 0x0
30815 /* Extracts the ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD field value from a register. */
30816 #define ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30817 /* Produces a ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD register field value suitable for setting the register. */
30818 #define ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_FLD_SET(value) (((value) << 0) & 0xffffffff)
30819 
30820 #ifndef __ASSEMBLY__
30821 /*
30822  * WARNING: The C register and register group struct declarations are provided for
30823  * convenience and illustrative purposes. They should, however, be used with
30824  * caution as the C language standard provides no guarantees about the alignment or
30825  * atomicity of device memory accesses. The recommended practice for coding device
30826  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30827  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30828  * alt_write_dword() functions for 64 bit registers.
30829  *
30830  * The struct declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR.
30831  */
30832 struct ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_s
30833 {
30834  volatile uint32_t fld : 32; /* Empty */
30835 };
30836 
30837 /* The typedef declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR. */
30838 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_s ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_t;
30839 #endif /* __ASSEMBLY__ */
30840 
30841 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR register. */
30842 #define ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_RESET 0x00000000
30843 /* The byte offset of the ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR register from the beginning of the component. */
30844 #define ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_OFST 0x10
30845 
30846 /*
30847  * Register : GICV_RPR
30848  *
30849  * VM Running Priority Register
30850  *
30851  * Register Layout
30852  *
30853  * Bits | Access | Reset | Description
30854  * :-------|:-------|:--------|:------------
30855  * [31:0] | RW | Unknown | Empty
30856  *
30857  */
30858 /*
30859  * Field : Empty - fld
30860  *
30861  * Placeholder
30862  *
30863  * Field Access Macros:
30864  *
30865  */
30866 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD register field. */
30867 #define ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD_LSB 0
30868 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD register field. */
30869 #define ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD_MSB 31
30870 /* The width in bits of the ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD register field. */
30871 #define ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD_WIDTH 32
30872 /* The mask used to set the ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD register field value. */
30873 #define ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD_SET_MSK 0xffffffff
30874 /* The mask used to clear the ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD register field value. */
30875 #define ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD_CLR_MSK 0x00000000
30876 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD register field is UNKNOWN. */
30877 #define ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD_RESET 0x0
30878 /* Extracts the ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD field value from a register. */
30879 #define ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30880 /* Produces a ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD register field value suitable for setting the register. */
30881 #define ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_FLD_SET(value) (((value) << 0) & 0xffffffff)
30882 
30883 #ifndef __ASSEMBLY__
30884 /*
30885  * WARNING: The C register and register group struct declarations are provided for
30886  * convenience and illustrative purposes. They should, however, be used with
30887  * caution as the C language standard provides no guarantees about the alignment or
30888  * atomicity of device memory accesses. The recommended practice for coding device
30889  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30890  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30891  * alt_write_dword() functions for 64 bit registers.
30892  *
30893  * The struct declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_RPR.
30894  */
30895 struct ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_s
30896 {
30897  volatile uint32_t fld : 32; /* Empty */
30898 };
30899 
30900 /* The typedef declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_RPR. */
30901 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_s ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_t;
30902 #endif /* __ASSEMBLY__ */
30903 
30904 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_RPR register. */
30905 #define ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_RESET 0x000000ff
30906 /* The byte offset of the ALT_GIC_VCPUIF_HYP_VM_GICV_RPR register from the beginning of the component. */
30907 #define ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_OFST 0x14
30908 
30909 /*
30910  * Register : GICV_HPPIR
30911  *
30912  * VM Highest Priority Pending Interrupt Register
30913  *
30914  * Register Layout
30915  *
30916  * Bits | Access | Reset | Description
30917  * :-------|:-------|:--------|:------------
30918  * [31:0] | RW | Unknown | Empty
30919  *
30920  */
30921 /*
30922  * Field : Empty - fld
30923  *
30924  * Placeholder
30925  *
30926  * Field Access Macros:
30927  *
30928  */
30929 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD register field. */
30930 #define ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD_LSB 0
30931 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD register field. */
30932 #define ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD_MSB 31
30933 /* The width in bits of the ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD register field. */
30934 #define ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD_WIDTH 32
30935 /* The mask used to set the ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD register field value. */
30936 #define ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD_SET_MSK 0xffffffff
30937 /* The mask used to clear the ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD register field value. */
30938 #define ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD_CLR_MSK 0x00000000
30939 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD register field is UNKNOWN. */
30940 #define ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD_RESET 0x0
30941 /* Extracts the ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD field value from a register. */
30942 #define ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
30943 /* Produces a ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD register field value suitable for setting the register. */
30944 #define ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_FLD_SET(value) (((value) << 0) & 0xffffffff)
30945 
30946 #ifndef __ASSEMBLY__
30947 /*
30948  * WARNING: The C register and register group struct declarations are provided for
30949  * convenience and illustrative purposes. They should, however, be used with
30950  * caution as the C language standard provides no guarantees about the alignment or
30951  * atomicity of device memory accesses. The recommended practice for coding device
30952  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
30953  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
30954  * alt_write_dword() functions for 64 bit registers.
30955  *
30956  * The struct declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR.
30957  */
30958 struct ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_s
30959 {
30960  volatile uint32_t fld : 32; /* Empty */
30961 };
30962 
30963 /* The typedef declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR. */
30964 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_s ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_t;
30965 #endif /* __ASSEMBLY__ */
30966 
30967 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR register. */
30968 #define ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_RESET 0x000003ff
30969 /* The byte offset of the ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR register from the beginning of the component. */
30970 #define ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_OFST 0x18
30971 
30972 /*
30973  * Register : GICV_ABPR
30974  *
30975  * VM Aliased Binary Point Register
30976  *
30977  * Register Layout
30978  *
30979  * Bits | Access | Reset | Description
30980  * :-------|:-------|:--------|:------------
30981  * [31:0] | RW | Unknown | Empty
30982  *
30983  */
30984 /*
30985  * Field : Empty - fld
30986  *
30987  * Placeholder
30988  *
30989  * Field Access Macros:
30990  *
30991  */
30992 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD register field. */
30993 #define ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD_LSB 0
30994 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD register field. */
30995 #define ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD_MSB 31
30996 /* The width in bits of the ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD register field. */
30997 #define ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD_WIDTH 32
30998 /* The mask used to set the ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD register field value. */
30999 #define ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD_SET_MSK 0xffffffff
31000 /* The mask used to clear the ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD register field value. */
31001 #define ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD_CLR_MSK 0x00000000
31002 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD register field is UNKNOWN. */
31003 #define ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD_RESET 0x0
31004 /* Extracts the ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD field value from a register. */
31005 #define ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
31006 /* Produces a ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD register field value suitable for setting the register. */
31007 #define ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_FLD_SET(value) (((value) << 0) & 0xffffffff)
31008 
31009 #ifndef __ASSEMBLY__
31010 /*
31011  * WARNING: The C register and register group struct declarations are provided for
31012  * convenience and illustrative purposes. They should, however, be used with
31013  * caution as the C language standard provides no guarantees about the alignment or
31014  * atomicity of device memory accesses. The recommended practice for coding device
31015  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
31016  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
31017  * alt_write_dword() functions for 64 bit registers.
31018  *
31019  * The struct declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR.
31020  */
31021 struct ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_s
31022 {
31023  volatile uint32_t fld : 32; /* Empty */
31024 };
31025 
31026 /* The typedef declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR. */
31027 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_s ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_t;
31028 #endif /* __ASSEMBLY__ */
31029 
31030 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR register. */
31031 #define ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_RESET 0x00000003
31032 /* The byte offset of the ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR register from the beginning of the component. */
31033 #define ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_OFST 0x1c
31034 
31035 /*
31036  * Register : GICV_AIAR
31037  *
31038  * VM Aliased Interrupt Acknowledge Register
31039  *
31040  * Register Layout
31041  *
31042  * Bits | Access | Reset | Description
31043  * :-------|:-------|:--------|:------------
31044  * [31:0] | RW | Unknown | Empty
31045  *
31046  */
31047 /*
31048  * Field : Empty - fld
31049  *
31050  * Placeholder
31051  *
31052  * Field Access Macros:
31053  *
31054  */
31055 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD register field. */
31056 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD_LSB 0
31057 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD register field. */
31058 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD_MSB 31
31059 /* The width in bits of the ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD register field. */
31060 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD_WIDTH 32
31061 /* The mask used to set the ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD register field value. */
31062 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD_SET_MSK 0xffffffff
31063 /* The mask used to clear the ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD register field value. */
31064 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD_CLR_MSK 0x00000000
31065 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD register field is UNKNOWN. */
31066 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD_RESET 0x0
31067 /* Extracts the ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD field value from a register. */
31068 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
31069 /* Produces a ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD register field value suitable for setting the register. */
31070 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_FLD_SET(value) (((value) << 0) & 0xffffffff)
31071 
31072 #ifndef __ASSEMBLY__
31073 /*
31074  * WARNING: The C register and register group struct declarations are provided for
31075  * convenience and illustrative purposes. They should, however, be used with
31076  * caution as the C language standard provides no guarantees about the alignment or
31077  * atomicity of device memory accesses. The recommended practice for coding device
31078  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
31079  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
31080  * alt_write_dword() functions for 64 bit registers.
31081  *
31082  * The struct declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR.
31083  */
31084 struct ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_s
31085 {
31086  volatile uint32_t fld : 32; /* Empty */
31087 };
31088 
31089 /* The typedef declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR. */
31090 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_s ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_t;
31091 #endif /* __ASSEMBLY__ */
31092 
31093 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR register. */
31094 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_RESET 0x000003ff
31095 /* The byte offset of the ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR register from the beginning of the component. */
31096 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_OFST 0x20
31097 
31098 /*
31099  * Register : GICV_AEOIR
31100  *
31101  * VM Aliased End of Interrupt Register
31102  *
31103  * Register Layout
31104  *
31105  * Bits | Access | Reset | Description
31106  * :-------|:-------|:--------|:------------
31107  * [31:0] | RW | Unknown | Empty
31108  *
31109  */
31110 /*
31111  * Field : Empty - fld
31112  *
31113  * Placeholder
31114  *
31115  * Field Access Macros:
31116  *
31117  */
31118 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD register field. */
31119 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD_LSB 0
31120 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD register field. */
31121 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD_MSB 31
31122 /* The width in bits of the ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD register field. */
31123 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD_WIDTH 32
31124 /* The mask used to set the ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD register field value. */
31125 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD_SET_MSK 0xffffffff
31126 /* The mask used to clear the ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD register field value. */
31127 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD_CLR_MSK 0x00000000
31128 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD register field is UNKNOWN. */
31129 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD_RESET 0x0
31130 /* Extracts the ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD field value from a register. */
31131 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
31132 /* Produces a ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD register field value suitable for setting the register. */
31133 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_FLD_SET(value) (((value) << 0) & 0xffffffff)
31134 
31135 #ifndef __ASSEMBLY__
31136 /*
31137  * WARNING: The C register and register group struct declarations are provided for
31138  * convenience and illustrative purposes. They should, however, be used with
31139  * caution as the C language standard provides no guarantees about the alignment or
31140  * atomicity of device memory accesses. The recommended practice for coding device
31141  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
31142  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
31143  * alt_write_dword() functions for 64 bit registers.
31144  *
31145  * The struct declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR.
31146  */
31147 struct ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_s
31148 {
31149  volatile uint32_t fld : 32; /* Empty */
31150 };
31151 
31152 /* The typedef declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR. */
31153 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_s ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_t;
31154 #endif /* __ASSEMBLY__ */
31155 
31156 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR register. */
31157 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_RESET 0x00000000
31158 /* The byte offset of the ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR register from the beginning of the component. */
31159 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_OFST 0x24
31160 
31161 /*
31162  * Register : GICV_AHPPIR
31163  *
31164  * VM Aliased Highest Priority Pending Interrupt Register
31165  *
31166  * Register Layout
31167  *
31168  * Bits | Access | Reset | Description
31169  * :-------|:-------|:--------|:------------
31170  * [31:0] | RW | Unknown | Empty
31171  *
31172  */
31173 /*
31174  * Field : Empty - fld
31175  *
31176  * Placeholder
31177  *
31178  * Field Access Macros:
31179  *
31180  */
31181 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD register field. */
31182 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD_LSB 0
31183 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD register field. */
31184 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD_MSB 31
31185 /* The width in bits of the ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD register field. */
31186 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD_WIDTH 32
31187 /* The mask used to set the ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD register field value. */
31188 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD_SET_MSK 0xffffffff
31189 /* The mask used to clear the ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD register field value. */
31190 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD_CLR_MSK 0x00000000
31191 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD register field is UNKNOWN. */
31192 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD_RESET 0x0
31193 /* Extracts the ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD field value from a register. */
31194 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
31195 /* Produces a ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD register field value suitable for setting the register. */
31196 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_FLD_SET(value) (((value) << 0) & 0xffffffff)
31197 
31198 #ifndef __ASSEMBLY__
31199 /*
31200  * WARNING: The C register and register group struct declarations are provided for
31201  * convenience and illustrative purposes. They should, however, be used with
31202  * caution as the C language standard provides no guarantees about the alignment or
31203  * atomicity of device memory accesses. The recommended practice for coding device
31204  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
31205  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
31206  * alt_write_dword() functions for 64 bit registers.
31207  *
31208  * The struct declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR.
31209  */
31210 struct ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_s
31211 {
31212  volatile uint32_t fld : 32; /* Empty */
31213 };
31214 
31215 /* The typedef declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR. */
31216 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_s ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_t;
31217 #endif /* __ASSEMBLY__ */
31218 
31219 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR register. */
31220 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_RESET 0x000003ff
31221 /* The byte offset of the ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR register from the beginning of the component. */
31222 #define ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_OFST 0x28
31223 
31224 /*
31225  * Register : GICV_APR0
31226  *
31227  * VM Active Priority Register
31228  *
31229  * Register Layout
31230  *
31231  * Bits | Access | Reset | Description
31232  * :-------|:-------|:------|:------------
31233  * [31:0] | RW | 0x0 | Empty
31234  *
31235  */
31236 /*
31237  * Field : Empty - fld
31238  *
31239  * Placeholder
31240  *
31241  * Field Access Macros:
31242  *
31243  */
31244 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD register field. */
31245 #define ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD_LSB 0
31246 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD register field. */
31247 #define ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD_MSB 31
31248 /* The width in bits of the ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD register field. */
31249 #define ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD_WIDTH 32
31250 /* The mask used to set the ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD register field value. */
31251 #define ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD_SET_MSK 0xffffffff
31252 /* The mask used to clear the ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD register field value. */
31253 #define ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD_CLR_MSK 0x00000000
31254 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD register field. */
31255 #define ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD_RESET 0x0
31256 /* Extracts the ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD field value from a register. */
31257 #define ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
31258 /* Produces a ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD register field value suitable for setting the register. */
31259 #define ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_FLD_SET(value) (((value) << 0) & 0xffffffff)
31260 
31261 #ifndef __ASSEMBLY__
31262 /*
31263  * WARNING: The C register and register group struct declarations are provided for
31264  * convenience and illustrative purposes. They should, however, be used with
31265  * caution as the C language standard provides no guarantees about the alignment or
31266  * atomicity of device memory accesses. The recommended practice for coding device
31267  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
31268  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
31269  * alt_write_dword() functions for 64 bit registers.
31270  *
31271  * The struct declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_APR0.
31272  */
31273 struct ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_s
31274 {
31275  volatile uint32_t fld : 32; /* Empty */
31276 };
31277 
31278 /* The typedef declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_APR0. */
31279 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_s ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_t;
31280 #endif /* __ASSEMBLY__ */
31281 
31282 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_APR0 register. */
31283 #define ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_RESET 0x00000000
31284 /* The byte offset of the ALT_GIC_VCPUIF_HYP_VM_GICV_APR0 register from the beginning of the component. */
31285 #define ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_OFST 0xd0
31286 
31287 /*
31288  * Register : GICV_IIDR
31289  *
31290  * VM CPU Interface Identification Register
31291  *
31292  * Register Layout
31293  *
31294  * Bits | Access | Reset | Description
31295  * :-------|:-------|:----------|:------------
31296  * [31:0] | RW | 0x202143b | Empty
31297  *
31298  */
31299 /*
31300  * Field : Empty - fld
31301  *
31302  * Placeholder
31303  *
31304  * Field Access Macros:
31305  *
31306  */
31307 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD register field. */
31308 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD_LSB 0
31309 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD register field. */
31310 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD_MSB 31
31311 /* The width in bits of the ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD register field. */
31312 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD_WIDTH 32
31313 /* The mask used to set the ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD register field value. */
31314 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD_SET_MSK 0xffffffff
31315 /* The mask used to clear the ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD register field value. */
31316 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD_CLR_MSK 0x00000000
31317 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD register field. */
31318 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD_RESET 0x202143b
31319 /* Extracts the ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD field value from a register. */
31320 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
31321 /* Produces a ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD register field value suitable for setting the register. */
31322 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_FLD_SET(value) (((value) << 0) & 0xffffffff)
31323 
31324 #ifndef __ASSEMBLY__
31325 /*
31326  * WARNING: The C register and register group struct declarations are provided for
31327  * convenience and illustrative purposes. They should, however, be used with
31328  * caution as the C language standard provides no guarantees about the alignment or
31329  * atomicity of device memory accesses. The recommended practice for coding device
31330  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
31331  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
31332  * alt_write_dword() functions for 64 bit registers.
31333  *
31334  * The struct declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR.
31335  */
31336 struct ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_s
31337 {
31338  volatile uint32_t fld : 32; /* Empty */
31339 };
31340 
31341 /* The typedef declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR. */
31342 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_s ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_t;
31343 #endif /* __ASSEMBLY__ */
31344 
31345 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR register. */
31346 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_RESET 0x0202143b
31347 /* The byte offset of the ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR register from the beginning of the component. */
31348 #define ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_OFST 0xfc
31349 
31350 /*
31351  * Register : GICV_DIR
31352  *
31353  * VM Deactivate Interrupt Register
31354  *
31355  * Register Layout
31356  *
31357  * Bits | Access | Reset | Description
31358  * :-------|:-------|:--------|:------------
31359  * [31:0] | RW | Unknown | Empty
31360  *
31361  */
31362 /*
31363  * Field : Empty - fld
31364  *
31365  * Placeholder
31366  *
31367  * Field Access Macros:
31368  *
31369  */
31370 /* The Least Significant Bit (LSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD register field. */
31371 #define ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD_LSB 0
31372 /* The Most Significant Bit (MSB) position of the ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD register field. */
31373 #define ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD_MSB 31
31374 /* The width in bits of the ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD register field. */
31375 #define ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD_WIDTH 32
31376 /* The mask used to set the ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD register field value. */
31377 #define ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD_SET_MSK 0xffffffff
31378 /* The mask used to clear the ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD register field value. */
31379 #define ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD_CLR_MSK 0x00000000
31380 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD register field is UNKNOWN. */
31381 #define ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD_RESET 0x0
31382 /* Extracts the ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD field value from a register. */
31383 #define ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD_GET(value) (((value) & 0xffffffff) >> 0)
31384 /* Produces a ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD register field value suitable for setting the register. */
31385 #define ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_FLD_SET(value) (((value) << 0) & 0xffffffff)
31386 
31387 #ifndef __ASSEMBLY__
31388 /*
31389  * WARNING: The C register and register group struct declarations are provided for
31390  * convenience and illustrative purposes. They should, however, be used with
31391  * caution as the C language standard provides no guarantees about the alignment or
31392  * atomicity of device memory accesses. The recommended practice for coding device
31393  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
31394  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
31395  * alt_write_dword() functions for 64 bit registers.
31396  *
31397  * The struct declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_DIR.
31398  */
31399 struct ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_s
31400 {
31401  volatile uint32_t fld : 32; /* Empty */
31402 };
31403 
31404 /* The typedef declaration for register ALT_GIC_VCPUIF_HYP_VM_GICV_DIR. */
31405 typedef struct ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_s ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_t;
31406 #endif /* __ASSEMBLY__ */
31407 
31408 /* The reset value of the ALT_GIC_VCPUIF_HYP_VM_GICV_DIR register. */
31409 #define ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_RESET 0x00000000
31410 /* The byte offset of the ALT_GIC_VCPUIF_HYP_VM_GICV_DIR register from the beginning of the component. */
31411 #define ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_OFST 0x1000
31412 
31413 #ifndef __ASSEMBLY__
31414 /*
31415  * WARNING: The C register and register group struct declarations are provided for
31416  * convenience and illustrative purposes. They should, however, be used with
31417  * caution as the C language standard provides no guarantees about the alignment or
31418  * atomicity of device memory accesses. The recommended practice for coding device
31419  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
31420  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
31421  * alt_write_dword() functions for 64 bit registers.
31422  *
31423  * The struct declaration for register group ALT_GIC_VCPUIF_HYP_VM.
31424  */
31425 struct ALT_GIC_VCPUIF_HYP_VM_s
31426 {
31427  volatile ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR_t GICV_CTLR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR */
31428  volatile ALT_GIC_VCPUIF_HYP_VM_GICV_PMR_t GICV_PMR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_PMR */
31429  volatile ALT_GIC_VCPUIF_HYP_VM_GICV_BPR_t GICV_BPR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_BPR */
31430  volatile ALT_GIC_VCPUIF_HYP_VM_GICV_IAR_t GICV_IAR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_IAR */
31431  volatile ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR_t GICV_EOIR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR */
31432  volatile ALT_GIC_VCPUIF_HYP_VM_GICV_RPR_t GICV_RPR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_RPR */
31433  volatile ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR_t GICV_HPPIR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR */
31434  volatile ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR_t GICV_ABPR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR */
31435  volatile ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR_t GICV_AIAR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR */
31436  volatile ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR_t GICV_AEOIR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR */
31437  volatile ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR_t GICV_AHPPIR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR */
31438  volatile uint32_t _pad_0x2c_0xcf[41]; /* *UNDEFINED* */
31439  volatile ALT_GIC_VCPUIF_HYP_VM_GICV_APR0_t GICV_APR0; /* ALT_GIC_VCPUIF_HYP_VM_GICV_APR0 */
31440  volatile uint32_t _pad_0xd4_0xfb[10]; /* *UNDEFINED* */
31441  volatile ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR_t GICV_IIDR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR */
31442  volatile uint32_t _pad_0x100_0xfff[960]; /* *UNDEFINED* */
31443  volatile ALT_GIC_VCPUIF_HYP_VM_GICV_DIR_t GICV_DIR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_DIR */
31444  volatile uint32_t _pad_0x1004_0x2000[1023]; /* *UNDEFINED* */
31445 };
31446 
31447 /* The typedef declaration for register group ALT_GIC_VCPUIF_HYP_VM. */
31448 typedef struct ALT_GIC_VCPUIF_HYP_VM_s ALT_GIC_VCPUIF_HYP_VM_t;
31449 /* The struct declaration for the raw register contents of register group ALT_GIC_VCPUIF_HYP_VM. */
31450 struct ALT_GIC_VCPUIF_HYP_VM_raw_s
31451 {
31452  volatile uint32_t GICV_CTLR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_CTLR */
31453  volatile uint32_t GICV_PMR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_PMR */
31454  volatile uint32_t GICV_BPR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_BPR */
31455  volatile uint32_t GICV_IAR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_IAR */
31456  volatile uint32_t GICV_EOIR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_EOIR */
31457  volatile uint32_t GICV_RPR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_RPR */
31458  volatile uint32_t GICV_HPPIR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_HPPIR */
31459  volatile uint32_t GICV_ABPR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_ABPR */
31460  volatile uint32_t GICV_AIAR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_AIAR */
31461  volatile uint32_t GICV_AEOIR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_AEOIR */
31462  volatile uint32_t GICV_AHPPIR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_AHPPIR */
31463  volatile uint32_t _pad_0x2c_0xcf[41]; /* *UNDEFINED* */
31464  volatile uint32_t GICV_APR0; /* ALT_GIC_VCPUIF_HYP_VM_GICV_APR0 */
31465  volatile uint32_t _pad_0xd4_0xfb[10]; /* *UNDEFINED* */
31466  volatile uint32_t GICV_IIDR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_IIDR */
31467  volatile uint32_t _pad_0x100_0xfff[960]; /* *UNDEFINED* */
31468  volatile uint32_t GICV_DIR; /* ALT_GIC_VCPUIF_HYP_VM_GICV_DIR */
31469  volatile uint32_t _pad_0x1004_0x2000[1023]; /* *UNDEFINED* */
31470 };
31471 
31472 /* The typedef declaration for the raw register contents of register group ALT_GIC_VCPUIF_HYP_VM. */
31473 typedef struct ALT_GIC_VCPUIF_HYP_VM_raw_s ALT_GIC_VCPUIF_HYP_VM_raw_t;
31474 #endif /* __ASSEMBLY__ */
31475 
31476 
31477 #ifdef __cplusplus
31478 }
31479 #endif /* __cplusplus */
31480 #endif /* __ALT_SOCAL_GIC_H__ */
31481