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alt_dma.h
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32 
33 /*
34  * $Id: //acds/main/embedded/ip/hps/armv8/hwlib/include/alt_dma.h#1 $
35  */
36 
37 #ifndef __ALT_DMA_H__
38 #define __ALT_DMA_H__
39 
40 #include "hwlib.h"
41 #include "alt_dma_common.h"
42 #include "alt_dma_program.h"
43 #include "alt_mmu.h"
44 
72  #ifndef ALT_DMA_PERIPH_PROVISION_16550_SUPPORT
73  #define ALT_DMA_PERIPH_PROVISION_16550_SUPPORT (1)
74  #endif
75 
76 
77 #if defined(soc_s10)
78  #ifndef ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT
79  #define ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT (0)
80  #endif
81 
82  #ifndef ALT_DMA_PERIPH_PROVISION_I2C_SUPPORT
83  #define ALT_DMA_PERIPH_PROVISION_I2C_SUPPORT (0)
84  #endif
85 #else
86  #ifndef ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT
87  #define ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT (1)
88  #endif
89 
90  #ifndef ALT_DMA_PERIPH_PROVISION_I2C_SUPPORT
91  #define ALT_DMA_PERIPH_PROVISION_I2C_SUPPORT (1)
92  #endif
93 #endif
94 
95 #if ALT_DMA_PERIPH_PROVISION_I2C_SUPPORT
96 #include "socal/alt_i2c.h"
97 #endif
98 
103 #ifdef __cplusplus
104 extern "C"
105 {
106 #endif /* __cplusplus */
107 
122 {
129 }
131 
137 {
149 }
151 
157 {
162  ALT_DMA_MANAGER_FAULT_DBG_INSTR = (int32_t)(1UL << 30),
163 
168 
173  ALT_DMA_MANAGER_FAULT_MGR_EVNT_ERR = (int32_t)(1UL << 5),
174 
179  ALT_DMA_MANAGER_FAULT_DMAGO_ERR = (int32_t)(1UL << 4),
180 
186 
190  ALT_DMA_MANAGER_FAULT_UNDEF_INSTR = (int32_t)(1UL << 0)
191 }
193 
199 {
203  ALT_DMA_CHANNEL_FAULT_LOCKUP_ERR = (int32_t)(1UL << 31),
204 
209  ALT_DMA_CHANNEL_FAULT_DBG_INSTR = (int32_t)(1UL << 30),
210 
214  ALT_DMA_CHANNEL_FAULT_DATA_READ_ERR = (int32_t)(1UL << 18),
215 
219  ALT_DMA_CHANNEL_FAULT_DATA_WRITE_ERR = (int32_t)(1UL << 17),
220 
225 
230 
235  ALT_DMA_CHANNEL_FAULT_MFIFO_ERR = (int32_t)(1UL << 12),
236 
241  ALT_DMA_CHANNEL_FAULT_CH_RDWR_ERR = (int32_t)(1UL << 7),
242 
247  ALT_DMA_CHANNEL_FAULT_CH_PERIPH_ERR = (int32_t)(1UL << 6),
248 
254  ALT_DMA_CHANNEL_FAULT_CH_EVNT_ERR = (int32_t)(1UL << 5),
255 
261 
265  ALT_DMA_CHANNEL_FAULT_UNDEF_INSTR = (int32_t)(1UL << 0)
266 }
268 
274 {
280 
286 }
288 
293 #if defined(soc_cv_av)
294 
295 typedef enum ALT_DMA_PERIPH_MUX_e
296 {
300  ALT_DMA_PERIPH_MUX_DEFAULT = 0,
301 
305  ALT_DMA_PERIPH_MUX_FPGA = 1,
306 
310  ALT_DMA_PERIPH_MUX_CAN = 2
311 }
312 ALT_DMA_PERIPH_MUX_t;
313 
314 #elif defined(soc_a10)
315 
316 typedef enum ALT_DMA_PERIPH_MUX_e
317 {
321  ALT_DMA_PERIPH_MUX_DEFAULT = 0,
322 
326  ALT_DMA_PERIPH_MUX_FPGA = 1,
327 
332  ALT_DMA_PERIPH_MUX_SECMGR = 2,
333 
338  ALT_DMA_PERIPH_MUX_I2C = 3
339 }
340 ALT_DMA_PERIPH_MUX_t;
341 
342 #endif
343 
344 
350 typedef struct ALT_DMA_CFG_s
351 {
352 #if !defined(soc_s10)
353 
357 
364 
371 #endif
372 
373 #if defined(soc_cv_av)
374 
381  ALT_DMA_PERIPH_MUX_t periph_mux[4];
382 
383 #elif defined(soc_a10)
384 
391  ALT_DMA_PERIPH_MUX_t periph_mux[3];
392 #elif defined(soc_s10)
393  #ifdef EXECUTION_LEVEL3
394 
400  bool periph_mux_I2C_EMAC2;
401  /*
402  * DMA_Manager_Security - Determines if the DMA device can be used to
403  access secure memory
404  * ALT_DMA_SECURITY_SECURE - The DMA device is only available in EL3
405  * ALT_DMA_SECURITY_NONSECURE - The DMA manager can only execute in
406  non-secure memory and start programs can
407  only access non-secure memory
408  */
409  ALT_DMA_SECURITY_t DMA_Manager_Security;
410 
417 
418  /*
419  * DMA Periphal Access - For each peripheral, sets the accessibility
420  * ALT_DMA_SECURITY_SECURE - This device should only be accessed in
421  EL3 by the secure DMA controller
422  * ALT_DMA_SECURITY_NONSECURE - This device should only be accessed by
423  the non-secure DMA controller
424  * */
425  ALT_DMA_SECURITY_t PERIPH_FPGA_0_Security;
426  ALT_DMA_SECURITY_t PERIPH_FPGA_1_Security;
427  ALT_DMA_SECURITY_t PERIPH_FPGA_2_Security;
428  ALT_DMA_SECURITY_t PERIPH_FPGA_3_Security;
429  ALT_DMA_SECURITY_t PERIPH_FPGA_4_Security;
430  ALT_DMA_SECURITY_t PERIPH_FPGA_5_Security;
431 
432  /* The Following 2 lines can be used for either FPGA or I2C_EMAC2. The
433  * selection is made during DMA_init(), and the other peripheral will
434  * not be available. */
435  ALT_DMA_SECURITY_t PERIPH_FPGA_6_OR_I2C_EMAC2_TX_Security;
436  ALT_DMA_SECURITY_t PERIPH_FPGA_7_OR_I2C_EMAC2_RX_Security;
437 
438  ALT_DMA_SECURITY_t PERIPH_I2C0_Security;
439  ALT_DMA_SECURITY_t PERIPH_I2C1_Security;
440 
441  ALT_DMA_SECURITY_t PERIPH_I2C_EMAC0_Security;
442 
443  ALT_DMA_SECURITY_t PERIPH_I2C_EMAC1_Security;
444 
445  ALT_DMA_SECURITY_t PERIPH_SPI0_MASTER_Security;
446  ALT_DMA_SECURITY_t PERIPH_SPI0_SLAVE_Security;
447  ALT_DMA_SECURITY_t PERIPH_SPI1_MASTER_Security;
448  ALT_DMA_SECURITY_t PERIPH_SPI1_SLAVE_Security;
449 
450  ALT_DMA_SECURITY_t PERIPH_STM_Security;
451 
452  ALT_DMA_SECURITY_t PERIPH_UART0_Security;
453  ALT_DMA_SECURITY_t PERIPH_UART1_Security;
454  #else /* EXECUTION_LEVEL3 */
455  /* This placeholder is here because you can't define a structure
456  with no members. However, if you're on s10 and not in EL3, you
457  cannot configure the security of the DMA device */
458  uint32_t placeholder;
459  #endif
460 #endif
461 }
463 
494 ALT_STATUS_CODE alt_dma_init(const ALT_DMA_CFG_t * dma_cfg);
495 
505 ALT_STATUS_CODE alt_dma_uninit(void);
506 
516 ALT_STATUS_CODE alt_dma_channel_alloc(ALT_DMA_CHANNEL_t channel);
517 
530 ALT_STATUS_CODE alt_dma_channel_alloc_any(ALT_DMA_CHANNEL_t * allocated);
531 
542 ALT_STATUS_CODE alt_dma_channel_free(ALT_DMA_CHANNEL_t channel);
543 
557 ALT_STATUS_CODE alt_dma_channel_exec(ALT_DMA_CHANNEL_t channel,
558  ALT_DMA_PROGRAM_t * pgm);
559 
576 ALT_STATUS_CODE alt_dma_channel_kill(ALT_DMA_CHANNEL_t channel);
577 
594 ALT_STATUS_CODE alt_dma_channel_reg_get(ALT_DMA_CHANNEL_t channel,
595  ALT_DMA_PROGRAM_REG_t reg, uint32_t * val);
596 
632 ALT_STATUS_CODE alt_dma_send_event(ALT_DMA_EVENT_t evt_num);
633 
644 ALT_STATUS_CODE alt_dma_manager_state_get(ALT_DMA_MANAGER_STATE_t * state);
645 
660 ALT_STATUS_CODE alt_dma_channel_state_get(ALT_DMA_CHANNEL_t channel,
661  ALT_DMA_CHANNEL_STATE_t * state);
662 
674 
690  ALT_DMA_CHANNEL_FAULT_t * fault);
691 
709 ALT_STATUS_CODE alt_dma_event_int_select(ALT_DMA_EVENT_t evt_num,
711 
727 ALT_STATUS_CODE alt_dma_event_int_status_get_raw(ALT_DMA_EVENT_t evt_num);
728 
744 ALT_STATUS_CODE alt_dma_int_status_get(ALT_DMA_EVENT_t irq_num);
745 
761 ALT_STATUS_CODE alt_dma_int_clear(ALT_DMA_EVENT_t irq_num);
762 
807 #if ALT_DMA_PERIPH_PROVISION_I2C_SUPPORT
808 
820 {
824  ALT_I2C_DEV_t * i2c_dev;
825 
831 
837 
841  uint32_t scratch[4];
842 }
844 
845 #endif
846 
892 ALT_STATUS_CODE alt_dma_memory_to_memory(ALT_DMA_CHANNEL_t channel,
893  ALT_DMA_PROGRAM_t * program,
894  void * va_dest,
895  const void * va_src,
896  size_t size,
897  ALT_DMA_EVENT_t evt,
898  const uint64_t * ttb,
899  const ALT_MMU_TCR_INFO_t *ttbconfig
900  );
901 
940 ALT_STATUS_CODE alt_dma_zero_to_memory(ALT_DMA_CHANNEL_t channel,
941  ALT_DMA_PROGRAM_t * program,
942  void * buf,
943  size_t size,
944  ALT_DMA_EVENT_t evt,
945  const uint64_t * ttb,
946  const ALT_MMU_TCR_INFO_t *ttbconfig);
947 
996 ALT_STATUS_CODE alt_dma_memory_to_register(ALT_DMA_CHANNEL_t channel,
997  ALT_DMA_PROGRAM_t * program,
998  void * dst_reg,
999  const void * src_buf,
1000  size_t count,
1001  uint32_t register_width_bits,
1002  ALT_DMA_EVENT_t evt,
1003  const uint64_t * ttb,
1004  const ALT_MMU_TCR_INFO_t *ttbconfig);
1005 
1054 ALT_STATUS_CODE alt_dma_register_to_memory(ALT_DMA_CHANNEL_t channel,
1055  ALT_DMA_PROGRAM_t * program,
1056  void * dst_buf,
1057  const void * src_reg,
1058  size_t count,
1059  uint32_t register_width_bits,
1060  ALT_DMA_EVENT_t evt,
1061  const uint64_t * ttb,
1062  const ALT_MMU_TCR_INFO_t *ttbconfig);
1063 
1150 ALT_STATUS_CODE alt_dma_memory_to_periph(ALT_DMA_CHANNEL_t channel,
1151  ALT_DMA_PROGRAM_t * program,
1152  ALT_DMA_PERIPH_t dest,
1153  const void * src,
1154  size_t size,
1155  void * periph_info,
1156  ALT_DMA_EVENT_t evt,
1157  const uint64_t * ttb,
1158  const ALT_MMU_TCR_INFO_t *ttbconfig);
1159 
1245 ALT_STATUS_CODE alt_dma_periph_to_memory(ALT_DMA_CHANNEL_t channel,
1246  ALT_DMA_PROGRAM_t * program,
1247  void * dest,
1248  ALT_DMA_PERIPH_t src,
1249  size_t size,
1250  void * periph_info,
1251  ALT_DMA_EVENT_t evt,
1252  const uint64_t * ttb,
1253  const ALT_MMU_TCR_INFO_t *ttbconfig);
1254 
1259 #ifdef __cplusplus
1260 }
1261 #endif /* __cplusplus */
1262 
1267 #endif /* __ALT_DMA_H__ */