35 #ifndef __ALT_SOCAL_NOC_MPU_F2SDR1_AXI64_QOS_H__
36 #define __ALT_SOCAL_NOC_MPU_F2SDR1_AXI64_QOS_H__
72 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_COREID_TYPEID_LSB 0
74 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_COREID_TYPEID_MSB 7
76 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_COREID_TYPEID_WIDTH 8
78 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_COREID_TYPEID_SET_MSK 0x000000ff
80 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_COREID_TYPEID_CLR_MSK 0xffffff00
82 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_COREID_TYPEID_RESET 0x4
84 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_COREID_TYPEID_GET(value) (((value) & 0x000000ff) >> 0)
86 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_COREID_TYPEID_SET(value) (((value) << 0) & 0x000000ff)
97 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_COREID_CHECKSUM_LSB 8
99 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_COREID_CHECKSUM_MSB 31
101 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_COREID_CHECKSUM_WIDTH 24
103 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_COREID_CHECKSUM_SET_MSK 0xffffff00
105 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_COREID_CHECKSUM_CLR_MSK 0x000000ff
107 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_COREID_CHECKSUM_RESET 0xe0e1ef
109 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_COREID_CHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
111 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_COREID_CHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
124 struct ALT_NOC_MPU_F2SDR1_AXI64_QOS_COREID_s
126 const uint32_t CORETYPEID : 8;
127 const uint32_t CORECHECKSUM : 24;
131 typedef volatile struct ALT_NOC_MPU_F2SDR1_AXI64_QOS_COREID_s ALT_NOC_MPU_F2SDR1_AXI64_QOS_COREID_t;
135 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_COREID_RESET 0xe0e1ef04
137 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_COREID_OFST 0x0
159 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_REVID_UID_LSB 0
161 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_REVID_UID_MSB 7
163 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_REVID_UID_WIDTH 8
165 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_REVID_UID_SET_MSK 0x000000ff
167 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_REVID_UID_CLR_MSK 0xffffff00
169 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_REVID_UID_RESET 0x0
171 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_REVID_UID_GET(value) (((value) & 0x000000ff) >> 0)
173 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_REVID_UID_SET(value) (((value) << 0) & 0x000000ff)
185 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_REVID_FLEXNOCID_LSB 8
187 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_REVID_FLEXNOCID_MSB 31
189 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_REVID_FLEXNOCID_WIDTH 24
191 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_REVID_FLEXNOCID_SET_MSK 0xffffff00
193 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_REVID_FLEXNOCID_CLR_MSK 0x000000ff
195 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_REVID_FLEXNOCID_RESET 0x129ff
197 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_REVID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
199 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_REVID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
212 struct ALT_NOC_MPU_F2SDR1_AXI64_QOS_REVID_s
214 const uint32_t USERID : 8;
215 const uint32_t FLEXNOCID : 24;
219 typedef volatile struct ALT_NOC_MPU_F2SDR1_AXI64_QOS_REVID_s ALT_NOC_MPU_F2SDR1_AXI64_QOS_REVID_t;
223 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_REVID_RESET 0x0129ff00
225 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_REVID_OFST 0x4
255 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_P0_LSB 0
257 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_P0_MSB 1
259 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_P0_WIDTH 2
261 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_P0_SET_MSK 0x00000003
263 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_P0_CLR_MSK 0xfffffffc
265 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_P0_RESET 0x0
267 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_P0_GET(value) (((value) & 0x00000003) >> 0)
269 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_P0_SET(value) (((value) << 0) & 0x00000003)
283 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_P1_LSB 8
285 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_P1_MSB 9
287 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_P1_WIDTH 2
289 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_P1_SET_MSK 0x00000300
291 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_P1_CLR_MSK 0xfffffcff
293 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_P1_RESET 0x2
295 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_P1_GET(value) (((value) & 0x00000300) >> 8)
297 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_P1_SET(value) (((value) << 8) & 0x00000300)
308 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_MARK_LSB 31
310 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_MARK_MSB 31
312 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_MARK_WIDTH 1
314 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_MARK_SET_MSK 0x80000000
316 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_MARK_CLR_MSK 0x7fffffff
318 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_MARK_RESET 0x1
320 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_MARK_GET(value) (((value) & 0x80000000) >> 31)
322 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_MARK_SET(value) (((value) << 31) & 0x80000000)
335 struct ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_s
341 const uint32_t MARK : 1;
345 typedef volatile struct ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_s ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_t;
349 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_RESET 0x80000200
351 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_OFST 0x8
377 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_MOD_MOD_LSB 0
379 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_MOD_MOD_MSB 1
381 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_MOD_MOD_WIDTH 2
383 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_MOD_MOD_SET_MSK 0x00000003
385 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_MOD_MOD_CLR_MSK 0xfffffffc
387 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_MOD_MOD_RESET 0x3
389 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_MOD_MOD_GET(value) (((value) & 0x00000003) >> 0)
391 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_MOD_MOD_SET(value) (((value) << 0) & 0x00000003)
404 struct ALT_NOC_MPU_F2SDR1_AXI64_QOS_MOD_s
411 typedef volatile struct ALT_NOC_MPU_F2SDR1_AXI64_QOS_MOD_s ALT_NOC_MPU_F2SDR1_AXI64_QOS_MOD_t;
415 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_MOD_RESET 0x00000003
417 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_MOD_OFST 0xc
442 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_BWDTH_BANDWIDTH_LSB 0
444 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_BWDTH_BANDWIDTH_MSB 11
446 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_BWDTH_BANDWIDTH_WIDTH 12
448 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_BWDTH_BANDWIDTH_SET_MSK 0x00000fff
450 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_BWDTH_BANDWIDTH_CLR_MSK 0xfffff000
452 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_BWDTH_BANDWIDTH_RESET 0x780
454 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_BWDTH_BANDWIDTH_GET(value) (((value) & 0x00000fff) >> 0)
456 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_BWDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x00000fff)
469 struct ALT_NOC_MPU_F2SDR1_AXI64_QOS_BWDTH_s
471 uint32_t BANDWIDTH : 12;
476 typedef volatile struct ALT_NOC_MPU_F2SDR1_AXI64_QOS_BWDTH_s ALT_NOC_MPU_F2SDR1_AXI64_QOS_BWDTH_t;
480 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_BWDTH_RESET 0x00000780
482 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_BWDTH_OFST 0x10
508 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_SAT_SATURATION_LSB 0
510 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_SAT_SATURATION_MSB 9
512 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_SAT_SATURATION_WIDTH 10
514 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_SAT_SATURATION_SET_MSK 0x000003ff
516 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_SAT_SATURATION_CLR_MSK 0xfffffc00
518 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_SAT_SATURATION_RESET 0x8
520 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_SAT_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
522 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_SAT_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
535 struct ALT_NOC_MPU_F2SDR1_AXI64_QOS_SAT_s
537 uint32_t SATURATION : 10;
542 typedef volatile struct ALT_NOC_MPU_F2SDR1_AXI64_QOS_SAT_s ALT_NOC_MPU_F2SDR1_AXI64_QOS_SAT_t;
546 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_SAT_RESET 0x00000008
548 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_SAT_OFST 0x14
574 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_SOCKETQOSEN_LSB 0
576 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_SOCKETQOSEN_MSB 0
578 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_SOCKETQOSEN_WIDTH 1
580 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_SOCKETQOSEN_SET_MSK 0x00000001
582 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_SOCKETQOSEN_CLR_MSK 0xfffffffe
584 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_SOCKETQOSEN_RESET 0x0
586 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
588 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
599 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_EXTTHREN_LSB 1
601 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_EXTTHREN_MSB 1
603 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_EXTTHREN_WIDTH 1
605 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_EXTTHREN_SET_MSK 0x00000002
607 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_EXTTHREN_CLR_MSK 0xfffffffd
609 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_EXTTHREN_RESET 0x0
611 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
613 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
624 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_INTCLKEN_LSB 2
626 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_INTCLKEN_MSB 2
628 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_INTCLKEN_WIDTH 1
630 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_INTCLKEN_SET_MSK 0x00000004
632 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_INTCLKEN_CLR_MSK 0xfffffffb
634 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_INTCLKEN_RESET 0x0
636 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
638 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
651 struct ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_s
653 uint32_t SOCKETQOSEN : 1;
654 uint32_t EXTTHREN : 1;
655 uint32_t INTCLKEN : 1;
660 typedef volatile struct ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_s ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_t;
664 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_RESET 0x00000000
666 #define ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_OFST 0x18
679 struct ALT_NOC_MPU_F2SDR1_AXI64_QOS_s
681 ALT_NOC_MPU_F2SDR1_AXI64_QOS_COREID_t fpga2sdram1_axi64_I_main_QosGenerator_Id_CoreId;
682 ALT_NOC_MPU_F2SDR1_AXI64_QOS_REVID_t fpga2sdram1_axi64_I_main_QosGenerator_Id_RevisionId;
683 ALT_NOC_MPU_F2SDR1_AXI64_QOS_PRI_t fpga2sdram1_axi64_I_main_QosGenerator_Priority;
684 ALT_NOC_MPU_F2SDR1_AXI64_QOS_MOD_t fpga2sdram1_axi64_I_main_QosGenerator_Mode;
685 ALT_NOC_MPU_F2SDR1_AXI64_QOS_BWDTH_t fpga2sdram1_axi64_I_main_QosGenerator_Bandwidth;
686 ALT_NOC_MPU_F2SDR1_AXI64_QOS_SAT_t fpga2sdram1_axi64_I_main_QosGenerator_Saturation;
687 ALT_NOC_MPU_F2SDR1_AXI64_QOS_EXTCTL_t fpga2sdram1_axi64_I_main_QosGenerator_ExtControl;
688 volatile uint32_t _pad_0x1c_0x80[25];
692 typedef volatile struct ALT_NOC_MPU_F2SDR1_AXI64_QOS_s ALT_NOC_MPU_F2SDR1_AXI64_QOS_t;
694 struct ALT_NOC_MPU_F2SDR1_AXI64_QOS_raw_s
696 volatile uint32_t fpga2sdram1_axi64_I_main_QosGenerator_Id_CoreId;
697 volatile uint32_t fpga2sdram1_axi64_I_main_QosGenerator_Id_RevisionId;
698 volatile uint32_t fpga2sdram1_axi64_I_main_QosGenerator_Priority;
699 volatile uint32_t fpga2sdram1_axi64_I_main_QosGenerator_Mode;
700 volatile uint32_t fpga2sdram1_axi64_I_main_QosGenerator_Bandwidth;
701 volatile uint32_t fpga2sdram1_axi64_I_main_QosGenerator_Saturation;
702 volatile uint32_t fpga2sdram1_axi64_I_main_QosGenerator_ExtControl;
703 uint32_t _pad_0x1c_0x80[25];
707 typedef volatile struct ALT_NOC_MPU_F2SDR1_AXI64_QOS_raw_s ALT_NOC_MPU_F2SDR1_AXI64_QOS_raw_t;