Hardware Libraries  20.1
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alt_emac.h
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32 
33 /* Altera - ALT_EMAC */
34 
35 #ifndef __ALT_SOCAL_EMAC_H__
36 #define __ALT_SOCAL_EMAC_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_EMAC
50  *
51  */
52 /*
53  * Register : gmacgrp_mac_configuration
54  *
55  * <b> Register 0 (MAC Configuration Register) </b>
56  *
57  * The MAC Configuration register establishes receive and transmit operating modes.
58  *
59  * Register Layout
60  *
61  * Bits | Access | Reset | Description
62  * :--------|:-------|:------|:------------------------------
63  * [1:0] | RW | 0x0 | ALT_EMAC_GMAC_MAC_CFG_PRELEN
64  * [2] | RW | 0x0 | ALT_EMAC_GMAC_MAC_CFG_RE
65  * [3] | RW | 0x0 | ALT_EMAC_GMAC_MAC_CFG_TE
66  * [4] | RW | 0x0 | ALT_EMAC_GMAC_MAC_CFG_DC
67  * [6:5] | RW | 0x0 | ALT_EMAC_GMAC_MAC_CFG_BL
68  * [7] | RW | 0x0 | ALT_EMAC_GMAC_MAC_CFG_ACS
69  * [8] | R | 0x0 | ALT_EMAC_GMAC_MAC_CFG_LUD
70  * [9] | RW | 0x0 | ALT_EMAC_GMAC_MAC_CFG_DR
71  * [10] | RW | 0x0 | ALT_EMAC_GMAC_MAC_CFG_IPC
72  * [11] | RW | 0x0 | ALT_EMAC_GMAC_MAC_CFG_DM
73  * [12] | RW | 0x0 | ALT_EMAC_GMAC_MAC_CFG_LM
74  * [13] | RW | 0x0 | ALT_EMAC_GMAC_MAC_CFG_DO
75  * [14] | RW | 0x0 | ALT_EMAC_GMAC_MAC_CFG_FES
76  * [15] | RW | 0x0 | ALT_EMAC_GMAC_MAC_CFG_PS
77  * [16] | RW | 0x0 | ALT_EMAC_GMAC_MAC_CFG_DCRS
78  * [19:17] | RW | 0x0 | ALT_EMAC_GMAC_MAC_CFG_IFG
79  * [20] | RW | 0x0 | ALT_EMAC_GMAC_MAC_CFG_JE
80  * [21] | RW | 0x0 | ALT_EMAC_GMAC_MAC_CFG_BE
81  * [22] | RW | 0x0 | ALT_EMAC_GMAC_MAC_CFG_JD
82  * [23] | RW | 0x0 | ALT_EMAC_GMAC_MAC_CFG_WD
83  * [24] | R | 0x0 | ALT_EMAC_GMAC_MAC_CFG_TC
84  * [25] | RW | 0x0 | ALT_EMAC_GMAC_MAC_CFG_CST
85  * [26] | R | 0x0 | ALT_EMAC_GMAC_MAC_CFG_SFTERR
86  * [27] | RW | 0x0 | ALT_EMAC_GMAC_MAC_CFG_TWOKPE
87  * [30:28] | RW | 0x0 | ALT_EMAC_GMAC_MAC_CFG_SARC
88  * [31] | R | 0x0 | ALT_EMAC_GMAC_MAC_CFG_RSVD_31
89  *
90  */
91 /*
92  * Field : prelen
93  *
94  * Preamble Length for Transmit Frames
95  *
96  * These bits control the number of preamble bytes that are added to the beginning
97  * of every Transmit frame. The preamble reduction occurs only when the MAC is
98  * operating in the full-duplex mode.
99  *
100  * * 2'b00: 7 bytes of preamble
101  *
102  * * 2'b01: 5 byte of preamble
103  *
104  * * 2'b10: 3 bytes of preamble
105  *
106  * * 2'b11: 1 byte of preamble
107  *
108  * Field Enumeration Values:
109  *
110  * Enum | Value | Description
111  * :-------------------------------------------|:------|:------------
112  * ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM7BYTES | 0x0 |
113  * ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM5BYTES | 0x1 |
114  * ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM3BYTES | 0x2 |
115  * ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM1BYTE | 0x3 |
116  *
117  * Field Access Macros:
118  *
119  */
120 /*
121  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PRELEN
122  *
123  */
124 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM7BYTES 0x0
125 /*
126  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PRELEN
127  *
128  */
129 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM5BYTES 0x1
130 /*
131  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PRELEN
132  *
133  */
134 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM3BYTES 0x2
135 /*
136  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PRELEN
137  *
138  */
139 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM1BYTE 0x3
140 
141 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field. */
142 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_LSB 0
143 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field. */
144 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_MSB 1
145 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field. */
146 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_WIDTH 2
147 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field value. */
148 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_SET_MSK 0x00000003
149 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field value. */
150 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_CLR_MSK 0xfffffffc
151 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field. */
152 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_RESET 0x0
153 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_PRELEN field value from a register. */
154 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_GET(value) (((value) & 0x00000003) >> 0)
155 /* Produces a ALT_EMAC_GMAC_MAC_CFG_PRELEN register field value suitable for setting the register. */
156 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_SET(value) (((value) << 0) & 0x00000003)
157 
158 /*
159  * Field : re
160  *
161  * Receiver Enable
162  *
163  * When this bit is set, the receiver state machine of the MAC is enabled for
164  * receiving frames from the GMII or MII. When this bit is reset, the MAC receive
165  * state machine is disabled after the completion of the reception of the current
166  * frame, and does not receive any further frames from the GMII or MII.
167  *
168  * Field Enumeration Values:
169  *
170  * Enum | Value | Description
171  * :--------------------------------|:------|:------------
172  * ALT_EMAC_GMAC_MAC_CFG_RE_E_DISD | 0x0 |
173  * ALT_EMAC_GMAC_MAC_CFG_RE_E_END | 0x1 |
174  *
175  * Field Access Macros:
176  *
177  */
178 /*
179  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_RE
180  *
181  */
182 #define ALT_EMAC_GMAC_MAC_CFG_RE_E_DISD 0x0
183 /*
184  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_RE
185  *
186  */
187 #define ALT_EMAC_GMAC_MAC_CFG_RE_E_END 0x1
188 
189 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_RE register field. */
190 #define ALT_EMAC_GMAC_MAC_CFG_RE_LSB 2
191 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_RE register field. */
192 #define ALT_EMAC_GMAC_MAC_CFG_RE_MSB 2
193 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_RE register field. */
194 #define ALT_EMAC_GMAC_MAC_CFG_RE_WIDTH 1
195 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_RE register field value. */
196 #define ALT_EMAC_GMAC_MAC_CFG_RE_SET_MSK 0x00000004
197 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_RE register field value. */
198 #define ALT_EMAC_GMAC_MAC_CFG_RE_CLR_MSK 0xfffffffb
199 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_RE register field. */
200 #define ALT_EMAC_GMAC_MAC_CFG_RE_RESET 0x0
201 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_RE field value from a register. */
202 #define ALT_EMAC_GMAC_MAC_CFG_RE_GET(value) (((value) & 0x00000004) >> 2)
203 /* Produces a ALT_EMAC_GMAC_MAC_CFG_RE register field value suitable for setting the register. */
204 #define ALT_EMAC_GMAC_MAC_CFG_RE_SET(value) (((value) << 2) & 0x00000004)
205 
206 /*
207  * Field : te
208  *
209  * Transmitter Enable
210  *
211  * When this bit is set, the transmit state machine of the MAC is enabled for
212  * transmission on the GMII or MII. When this bit is reset, the MAC transmit state
213  * machine is disabled after the completion of the transmission of the current
214  * frame, and does not transmit any further frames.
215  *
216  * Field Enumeration Values:
217  *
218  * Enum | Value | Description
219  * :--------------------------------|:------|:------------
220  * ALT_EMAC_GMAC_MAC_CFG_TE_E_DISD | 0x0 |
221  * ALT_EMAC_GMAC_MAC_CFG_TE_E_END | 0x1 |
222  *
223  * Field Access Macros:
224  *
225  */
226 /*
227  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TE
228  *
229  */
230 #define ALT_EMAC_GMAC_MAC_CFG_TE_E_DISD 0x0
231 /*
232  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TE
233  *
234  */
235 #define ALT_EMAC_GMAC_MAC_CFG_TE_E_END 0x1
236 
237 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_TE register field. */
238 #define ALT_EMAC_GMAC_MAC_CFG_TE_LSB 3
239 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_TE register field. */
240 #define ALT_EMAC_GMAC_MAC_CFG_TE_MSB 3
241 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_TE register field. */
242 #define ALT_EMAC_GMAC_MAC_CFG_TE_WIDTH 1
243 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_TE register field value. */
244 #define ALT_EMAC_GMAC_MAC_CFG_TE_SET_MSK 0x00000008
245 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_TE register field value. */
246 #define ALT_EMAC_GMAC_MAC_CFG_TE_CLR_MSK 0xfffffff7
247 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_TE register field. */
248 #define ALT_EMAC_GMAC_MAC_CFG_TE_RESET 0x0
249 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_TE field value from a register. */
250 #define ALT_EMAC_GMAC_MAC_CFG_TE_GET(value) (((value) & 0x00000008) >> 3)
251 /* Produces a ALT_EMAC_GMAC_MAC_CFG_TE register field value suitable for setting the register. */
252 #define ALT_EMAC_GMAC_MAC_CFG_TE_SET(value) (((value) << 3) & 0x00000008)
253 
254 /*
255  * Field : dc
256  *
257  * Deferral Check
258  *
259  * When this bit is set, the deferral check function is enabled in the MAC. The MAC
260  * issues a Frame Abort status, along with the excessive deferral error bit set in
261  * the transmit frame status, when the transmit state machine is deferred for more
262  * than 24,288 bit times in the 10 or 100 Mbps mode.
263  *
264  * If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is
265  * enabled in the 10 or 100 Mbps mode, the threshold for deferral is 155,680 bits
266  * times. Deferral begins when the transmitter is ready to transmit, but it is
267  * prevented because of an active carrier sense signal (CRS) on GMII or MII.
268  *
269  * The defer time is not cumulative. For example, if the transmitter defers for
270  * 10,000 bit times because the CRS signal is active and then the CRS signal
271  * becomes inactive, the transmitter transmits and collision happens. Because of
272  * collision, the transmitter needs to back off and then defer again after back off
273  * completion. In such a scenario, the deferral timer is reset to 0 and it is
274  * restarted.
275  *
276  * When this bit is reset, the deferral check function is disabled and the MAC
277  * defers until the CRS signal goes inactive. This bit is applicable only in the
278  * half-duplex mode and is reserved (RO) in the full-duplex-only configuration.
279  *
280  * Field Enumeration Values:
281  *
282  * Enum | Value | Description
283  * :--------------------------------|:------|:------------
284  * ALT_EMAC_GMAC_MAC_CFG_DC_E_DISD | 0x0 |
285  * ALT_EMAC_GMAC_MAC_CFG_DC_E_END | 0x1 |
286  *
287  * Field Access Macros:
288  *
289  */
290 /*
291  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DC
292  *
293  */
294 #define ALT_EMAC_GMAC_MAC_CFG_DC_E_DISD 0x0
295 /*
296  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DC
297  *
298  */
299 #define ALT_EMAC_GMAC_MAC_CFG_DC_E_END 0x1
300 
301 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DC register field. */
302 #define ALT_EMAC_GMAC_MAC_CFG_DC_LSB 4
303 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DC register field. */
304 #define ALT_EMAC_GMAC_MAC_CFG_DC_MSB 4
305 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DC register field. */
306 #define ALT_EMAC_GMAC_MAC_CFG_DC_WIDTH 1
307 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DC register field value. */
308 #define ALT_EMAC_GMAC_MAC_CFG_DC_SET_MSK 0x00000010
309 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DC register field value. */
310 #define ALT_EMAC_GMAC_MAC_CFG_DC_CLR_MSK 0xffffffef
311 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_DC register field. */
312 #define ALT_EMAC_GMAC_MAC_CFG_DC_RESET 0x0
313 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_DC field value from a register. */
314 #define ALT_EMAC_GMAC_MAC_CFG_DC_GET(value) (((value) & 0x00000010) >> 4)
315 /* Produces a ALT_EMAC_GMAC_MAC_CFG_DC register field value suitable for setting the register. */
316 #define ALT_EMAC_GMAC_MAC_CFG_DC_SET(value) (((value) << 4) & 0x00000010)
317 
318 /*
319  * Field : bl
320  *
321  * Back-Off Limit
322  *
323  * The Back-Off limit determines the random integer number (r) of slot time delays
324  * (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the
325  * MAC waits before rescheduling a transmission attempt during retries after a
326  * collision. This bit is applicable only in the half-duplex mode and is reserved
327  * (RO) in the full-duplex-only configuration.
328  *
329  * * 00: k = min (n, 10)
330  *
331  * * 01: k = min (n, 8)
332  *
333  * * 10: k = min (n, 4)
334  *
335  * * 11: k = min (n, 1)
336  *
337  * where <i> n </i> = retransmission attempt. The random integer <i> r </i> takes
338  * the value in the
339  *
340  * range 0 <= r < kth power of 2
341  *
342  * Field Enumeration Values:
343  *
344  * Enum | Value | Description
345  * :---------------------------------------|:------|:------------
346  * ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMTR10 | 0x0 |
347  * ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMIRT8 | 0x1 |
348  * ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR4 | 0x2 |
349  * ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR1 | 0x3 |
350  *
351  * Field Access Macros:
352  *
353  */
354 /*
355  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL
356  *
357  */
358 #define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMTR10 0x0
359 /*
360  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL
361  *
362  */
363 #define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMIRT8 0x1
364 /*
365  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL
366  *
367  */
368 #define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR4 0x2
369 /*
370  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL
371  *
372  */
373 #define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR1 0x3
374 
375 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_BL register field. */
376 #define ALT_EMAC_GMAC_MAC_CFG_BL_LSB 5
377 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_BL register field. */
378 #define ALT_EMAC_GMAC_MAC_CFG_BL_MSB 6
379 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_BL register field. */
380 #define ALT_EMAC_GMAC_MAC_CFG_BL_WIDTH 2
381 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_BL register field value. */
382 #define ALT_EMAC_GMAC_MAC_CFG_BL_SET_MSK 0x00000060
383 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_BL register field value. */
384 #define ALT_EMAC_GMAC_MAC_CFG_BL_CLR_MSK 0xffffff9f
385 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_BL register field. */
386 #define ALT_EMAC_GMAC_MAC_CFG_BL_RESET 0x0
387 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_BL field value from a register. */
388 #define ALT_EMAC_GMAC_MAC_CFG_BL_GET(value) (((value) & 0x00000060) >> 5)
389 /* Produces a ALT_EMAC_GMAC_MAC_CFG_BL register field value suitable for setting the register. */
390 #define ALT_EMAC_GMAC_MAC_CFG_BL_SET(value) (((value) << 5) & 0x00000060)
391 
392 /*
393  * Field : acs
394  *
395  * Automatic Pad or CRC Stripping
396  *
397  * When this bit is set, the MAC strips the Pad or FCS field on the incoming frames
398  * only if the value of the length field is less than 1,536 bytes. All received
399  * frames with length field greater than or equal to 1,536 bytes are passed to the
400  * application without stripping the Pad or FCS field.
401  *
402  * When this bit is reset, the MAC passes all incoming frames, without modifying
403  * them, to the Host.
404  *
405  * Field Enumeration Values:
406  *
407  * Enum | Value | Description
408  * :---------------------------------|:------|:------------
409  * ALT_EMAC_GMAC_MAC_CFG_ACS_E_DISD | 0x0 |
410  * ALT_EMAC_GMAC_MAC_CFG_ACS_E_END | 0x1 |
411  *
412  * Field Access Macros:
413  *
414  */
415 /*
416  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_ACS
417  *
418  */
419 #define ALT_EMAC_GMAC_MAC_CFG_ACS_E_DISD 0x0
420 /*
421  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_ACS
422  *
423  */
424 #define ALT_EMAC_GMAC_MAC_CFG_ACS_E_END 0x1
425 
426 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_ACS register field. */
427 #define ALT_EMAC_GMAC_MAC_CFG_ACS_LSB 7
428 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_ACS register field. */
429 #define ALT_EMAC_GMAC_MAC_CFG_ACS_MSB 7
430 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_ACS register field. */
431 #define ALT_EMAC_GMAC_MAC_CFG_ACS_WIDTH 1
432 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_ACS register field value. */
433 #define ALT_EMAC_GMAC_MAC_CFG_ACS_SET_MSK 0x00000080
434 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_ACS register field value. */
435 #define ALT_EMAC_GMAC_MAC_CFG_ACS_CLR_MSK 0xffffff7f
436 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_ACS register field. */
437 #define ALT_EMAC_GMAC_MAC_CFG_ACS_RESET 0x0
438 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_ACS field value from a register. */
439 #define ALT_EMAC_GMAC_MAC_CFG_ACS_GET(value) (((value) & 0x00000080) >> 7)
440 /* Produces a ALT_EMAC_GMAC_MAC_CFG_ACS register field value suitable for setting the register. */
441 #define ALT_EMAC_GMAC_MAC_CFG_ACS_SET(value) (((value) << 7) & 0x00000080)
442 
443 /*
444  * Field : lud
445  *
446  * Link Up or Down
447  *
448  * This bit indicates whether the link is up or down during the transmission of
449  * configuration in the RGMII, SGMII, or SMII interface:
450  *
451  * * 0: Link Down
452  *
453  * * 1: Link Up
454  *
455  * This bit is reserved (RO with default value) and is enabled when the RGMII,
456  * SGMII, or SMII interface is enabled during core configuration.
457  *
458  * Field Enumeration Values:
459  *
460  * Enum | Value | Description
461  * :---------------------------------|:------|:------------
462  * ALT_EMAC_GMAC_MAC_CFG_LUD_E_DISD | 0x0 |
463  * ALT_EMAC_GMAC_MAC_CFG_LUD_E_END | 0x1 |
464  *
465  * Field Access Macros:
466  *
467  */
468 /*
469  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LUD
470  *
471  */
472 #define ALT_EMAC_GMAC_MAC_CFG_LUD_E_DISD 0x0
473 /*
474  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LUD
475  *
476  */
477 #define ALT_EMAC_GMAC_MAC_CFG_LUD_E_END 0x1
478 
479 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_LUD register field. */
480 #define ALT_EMAC_GMAC_MAC_CFG_LUD_LSB 8
481 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_LUD register field. */
482 #define ALT_EMAC_GMAC_MAC_CFG_LUD_MSB 8
483 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_LUD register field. */
484 #define ALT_EMAC_GMAC_MAC_CFG_LUD_WIDTH 1
485 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_LUD register field value. */
486 #define ALT_EMAC_GMAC_MAC_CFG_LUD_SET_MSK 0x00000100
487 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_LUD register field value. */
488 #define ALT_EMAC_GMAC_MAC_CFG_LUD_CLR_MSK 0xfffffeff
489 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_LUD register field. */
490 #define ALT_EMAC_GMAC_MAC_CFG_LUD_RESET 0x0
491 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_LUD field value from a register. */
492 #define ALT_EMAC_GMAC_MAC_CFG_LUD_GET(value) (((value) & 0x00000100) >> 8)
493 /* Produces a ALT_EMAC_GMAC_MAC_CFG_LUD register field value suitable for setting the register. */
494 #define ALT_EMAC_GMAC_MAC_CFG_LUD_SET(value) (((value) << 8) & 0x00000100)
495 
496 /*
497  * Field : dr
498  *
499  * Disable Retry
500  *
501  * When this bit is set, the MAC attempts only one transmission. When a collision
502  * occurs on the GMII or MII interface, the MAC ignores the current frame
503  * transmission and reports a Frame Abort with excessive collision error in the
504  * transmit frame status.
505  *
506  * When this bit is reset, the MAC attempts retries based on the settings of the BL
507  * field (Bits [6:5]). This bit is applicable only in the half-duplex mode and is
508  * reserved (RO with default value) in the full-duplex-only configuration.
509  *
510  * Field Enumeration Values:
511  *
512  * Enum | Value | Description
513  * :--------------------------------|:------|:------------
514  * ALT_EMAC_GMAC_MAC_CFG_DR_E_END | 0x0 |
515  * ALT_EMAC_GMAC_MAC_CFG_DR_E_DISD | 0x1 |
516  *
517  * Field Access Macros:
518  *
519  */
520 /*
521  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DR
522  *
523  */
524 #define ALT_EMAC_GMAC_MAC_CFG_DR_E_END 0x0
525 /*
526  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DR
527  *
528  */
529 #define ALT_EMAC_GMAC_MAC_CFG_DR_E_DISD 0x1
530 
531 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DR register field. */
532 #define ALT_EMAC_GMAC_MAC_CFG_DR_LSB 9
533 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DR register field. */
534 #define ALT_EMAC_GMAC_MAC_CFG_DR_MSB 9
535 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DR register field. */
536 #define ALT_EMAC_GMAC_MAC_CFG_DR_WIDTH 1
537 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DR register field value. */
538 #define ALT_EMAC_GMAC_MAC_CFG_DR_SET_MSK 0x00000200
539 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DR register field value. */
540 #define ALT_EMAC_GMAC_MAC_CFG_DR_CLR_MSK 0xfffffdff
541 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_DR register field. */
542 #define ALT_EMAC_GMAC_MAC_CFG_DR_RESET 0x0
543 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_DR field value from a register. */
544 #define ALT_EMAC_GMAC_MAC_CFG_DR_GET(value) (((value) & 0x00000200) >> 9)
545 /* Produces a ALT_EMAC_GMAC_MAC_CFG_DR register field value suitable for setting the register. */
546 #define ALT_EMAC_GMAC_MAC_CFG_DR_SET(value) (((value) << 9) & 0x00000200)
547 
548 /*
549  * Field : ipc
550  *
551  * Checksum Offload
552  *
553  * When this bit is set, the MAC calculates the 16-bit one's complement of the
554  * one's complement sum of all received Ethernet frame payloads. It also checks
555  * whether the IPv4 Header checksum (assumed to be bytes 2526 or 2930 (VLAN-tagged)
556  * of the received Ethernet frame) is correct for the received frame and gives the
557  * status in the receive status word. The MAC also appends the 16-bit checksum
558  * calculated for the IP header datagram payload (bytes after the IPv4 header) and
559  * appends it to the Ethernet frame transferred to the application (when Type 2 COE
560  * is deselected).
561  *
562  * When this bit is reset, this function is disabled.
563  *
564  * When Type 2 COE is selected, this bit, when set, enables the IPv4 header
565  * checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking.
566  * When this bit is reset, the COE function in the receiver is disabled and the
567  * corresponding PCE and IP HCE status bits are always cleared.
568  *
569  * If the IP Checksum Offload feature is not enabled during core configuration,
570  * this bit is reserved (RO with default value).
571  *
572  * Field Enumeration Values:
573  *
574  * Enum | Value | Description
575  * :---------------------------------|:------|:------------
576  * ALT_EMAC_GMAC_MAC_CFG_IPC_E_DISD | 0x0 |
577  * ALT_EMAC_GMAC_MAC_CFG_IPC_E_END | 0x1 |
578  *
579  * Field Access Macros:
580  *
581  */
582 /*
583  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IPC
584  *
585  */
586 #define ALT_EMAC_GMAC_MAC_CFG_IPC_E_DISD 0x0
587 /*
588  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IPC
589  *
590  */
591 #define ALT_EMAC_GMAC_MAC_CFG_IPC_E_END 0x1
592 
593 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_IPC register field. */
594 #define ALT_EMAC_GMAC_MAC_CFG_IPC_LSB 10
595 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_IPC register field. */
596 #define ALT_EMAC_GMAC_MAC_CFG_IPC_MSB 10
597 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_IPC register field. */
598 #define ALT_EMAC_GMAC_MAC_CFG_IPC_WIDTH 1
599 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_IPC register field value. */
600 #define ALT_EMAC_GMAC_MAC_CFG_IPC_SET_MSK 0x00000400
601 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_IPC register field value. */
602 #define ALT_EMAC_GMAC_MAC_CFG_IPC_CLR_MSK 0xfffffbff
603 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_IPC register field. */
604 #define ALT_EMAC_GMAC_MAC_CFG_IPC_RESET 0x0
605 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_IPC field value from a register. */
606 #define ALT_EMAC_GMAC_MAC_CFG_IPC_GET(value) (((value) & 0x00000400) >> 10)
607 /* Produces a ALT_EMAC_GMAC_MAC_CFG_IPC register field value suitable for setting the register. */
608 #define ALT_EMAC_GMAC_MAC_CFG_IPC_SET(value) (((value) << 10) & 0x00000400)
609 
610 /*
611  * Field : dm
612  *
613  * Duplex Mode
614  *
615  * When this bit is set, the MAC operates in the full-duplex mode where it can
616  * transmit and receive simultaneously. This bit is RO with default value of 1'b1
617  * in the full-duplex-only configuration.
618  *
619  * Field Enumeration Values:
620  *
621  * Enum | Value | Description
622  * :--------------------------------|:------|:------------
623  * ALT_EMAC_GMAC_MAC_CFG_DM_E_DISD | 0x0 |
624  * ALT_EMAC_GMAC_MAC_CFG_DM_E_END | 0x1 |
625  *
626  * Field Access Macros:
627  *
628  */
629 /*
630  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DM
631  *
632  */
633 #define ALT_EMAC_GMAC_MAC_CFG_DM_E_DISD 0x0
634 /*
635  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DM
636  *
637  */
638 #define ALT_EMAC_GMAC_MAC_CFG_DM_E_END 0x1
639 
640 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DM register field. */
641 #define ALT_EMAC_GMAC_MAC_CFG_DM_LSB 11
642 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DM register field. */
643 #define ALT_EMAC_GMAC_MAC_CFG_DM_MSB 11
644 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DM register field. */
645 #define ALT_EMAC_GMAC_MAC_CFG_DM_WIDTH 1
646 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DM register field value. */
647 #define ALT_EMAC_GMAC_MAC_CFG_DM_SET_MSK 0x00000800
648 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DM register field value. */
649 #define ALT_EMAC_GMAC_MAC_CFG_DM_CLR_MSK 0xfffff7ff
650 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_DM register field. */
651 #define ALT_EMAC_GMAC_MAC_CFG_DM_RESET 0x0
652 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_DM field value from a register. */
653 #define ALT_EMAC_GMAC_MAC_CFG_DM_GET(value) (((value) & 0x00000800) >> 11)
654 /* Produces a ALT_EMAC_GMAC_MAC_CFG_DM register field value suitable for setting the register. */
655 #define ALT_EMAC_GMAC_MAC_CFG_DM_SET(value) (((value) << 11) & 0x00000800)
656 
657 /*
658  * Field : lm
659  *
660  * Loopback Mode
661  *
662  * When this bit is set, the MAC operates in the loopback mode at GMII or MII. The
663  * (G)MII Receive clock input (clk_rx_i) is required for the loopback to work
664  * properly, because the Transmit clock is not looped-back internally.
665  *
666  * Field Enumeration Values:
667  *
668  * Enum | Value | Description
669  * :--------------------------------|:------|:------------
670  * ALT_EMAC_GMAC_MAC_CFG_LM_E_DISD | 0x0 |
671  * ALT_EMAC_GMAC_MAC_CFG_LM_E_END | 0x1 |
672  *
673  * Field Access Macros:
674  *
675  */
676 /*
677  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LM
678  *
679  */
680 #define ALT_EMAC_GMAC_MAC_CFG_LM_E_DISD 0x0
681 /*
682  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LM
683  *
684  */
685 #define ALT_EMAC_GMAC_MAC_CFG_LM_E_END 0x1
686 
687 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_LM register field. */
688 #define ALT_EMAC_GMAC_MAC_CFG_LM_LSB 12
689 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_LM register field. */
690 #define ALT_EMAC_GMAC_MAC_CFG_LM_MSB 12
691 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_LM register field. */
692 #define ALT_EMAC_GMAC_MAC_CFG_LM_WIDTH 1
693 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_LM register field value. */
694 #define ALT_EMAC_GMAC_MAC_CFG_LM_SET_MSK 0x00001000
695 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_LM register field value. */
696 #define ALT_EMAC_GMAC_MAC_CFG_LM_CLR_MSK 0xffffefff
697 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_LM register field. */
698 #define ALT_EMAC_GMAC_MAC_CFG_LM_RESET 0x0
699 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_LM field value from a register. */
700 #define ALT_EMAC_GMAC_MAC_CFG_LM_GET(value) (((value) & 0x00001000) >> 12)
701 /* Produces a ALT_EMAC_GMAC_MAC_CFG_LM register field value suitable for setting the register. */
702 #define ALT_EMAC_GMAC_MAC_CFG_LM_SET(value) (((value) << 12) & 0x00001000)
703 
704 /*
705  * Field : do
706  *
707  * Disable Receive Own
708  *
709  * When this bit is set, the MAC disables the reception of frames when the
710  * phy_txen_o is asserted in the half-duplex mode.
711  *
712  * When this bit is reset, the MAC receives all packets that are given by the PHY
713  * while transmitting.
714  *
715  * This bit is not applicable if the MAC is operating in the full-duplex mode. This
716  * bit is reserved (RO with default value) if the MAC is configured for the full-
717  * duplex-only operation.
718  *
719  * Field Enumeration Values:
720  *
721  * Enum | Value | Description
722  * :--------------------------------|:------|:------------
723  * ALT_EMAC_GMAC_MAC_CFG_DO_E_END | 0x0 |
724  * ALT_EMAC_GMAC_MAC_CFG_DO_E_DISD | 0x1 |
725  *
726  * Field Access Macros:
727  *
728  */
729 /*
730  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DO
731  *
732  */
733 #define ALT_EMAC_GMAC_MAC_CFG_DO_E_END 0x0
734 /*
735  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DO
736  *
737  */
738 #define ALT_EMAC_GMAC_MAC_CFG_DO_E_DISD 0x1
739 
740 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DO register field. */
741 #define ALT_EMAC_GMAC_MAC_CFG_DO_LSB 13
742 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DO register field. */
743 #define ALT_EMAC_GMAC_MAC_CFG_DO_MSB 13
744 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DO register field. */
745 #define ALT_EMAC_GMAC_MAC_CFG_DO_WIDTH 1
746 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DO register field value. */
747 #define ALT_EMAC_GMAC_MAC_CFG_DO_SET_MSK 0x00002000
748 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DO register field value. */
749 #define ALT_EMAC_GMAC_MAC_CFG_DO_CLR_MSK 0xffffdfff
750 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_DO register field. */
751 #define ALT_EMAC_GMAC_MAC_CFG_DO_RESET 0x0
752 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_DO field value from a register. */
753 #define ALT_EMAC_GMAC_MAC_CFG_DO_GET(value) (((value) & 0x00002000) >> 13)
754 /* Produces a ALT_EMAC_GMAC_MAC_CFG_DO register field value suitable for setting the register. */
755 #define ALT_EMAC_GMAC_MAC_CFG_DO_SET(value) (((value) << 13) & 0x00002000)
756 
757 /*
758  * Field : fes
759  *
760  * Speed
761  *
762  * This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII
763  * interface
764  *
765  * * 0: 10 Mbps
766  *
767  * * 1: 100 Mbps
768  *
769  * This bit is reserved (RO) by default and is enabled only when the parameter
770  * SPEED_SELECT = Enabled. This bit generates link speed encoding when Bit 24 (TC)
771  * is set in the RGMII, SMII, or SGMII mode. This bit is always enabled for RGMII,
772  * SGMII, SMII, or RevMII interface.
773  *
774  * In configurations with RGMII, SGMII, SMII, or RevMII interface, this bit is
775  * driven as an output signal (mac_speed_o[0]) to reflect the value of this bit in
776  * the mac_speed_o signal. In configurations with RMII, MII, or GMII interface, you
777  * can optionally drive this bit as an output signal (mac_speed_o[0]) to reflect
778  * its value in the mac_speed_o signal.
779  *
780  * Field Enumeration Values:
781  *
782  * Enum | Value | Description
783  * :-------------------------------------|:------|:------------
784  * ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED10 | 0x0 |
785  * ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED100 | 0x1 |
786  *
787  * Field Access Macros:
788  *
789  */
790 /*
791  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_FES
792  *
793  */
794 #define ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED10 0x0
795 /*
796  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_FES
797  *
798  */
799 #define ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED100 0x1
800 
801 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_FES register field. */
802 #define ALT_EMAC_GMAC_MAC_CFG_FES_LSB 14
803 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_FES register field. */
804 #define ALT_EMAC_GMAC_MAC_CFG_FES_MSB 14
805 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_FES register field. */
806 #define ALT_EMAC_GMAC_MAC_CFG_FES_WIDTH 1
807 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_FES register field value. */
808 #define ALT_EMAC_GMAC_MAC_CFG_FES_SET_MSK 0x00004000
809 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_FES register field value. */
810 #define ALT_EMAC_GMAC_MAC_CFG_FES_CLR_MSK 0xffffbfff
811 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_FES register field. */
812 #define ALT_EMAC_GMAC_MAC_CFG_FES_RESET 0x0
813 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_FES field value from a register. */
814 #define ALT_EMAC_GMAC_MAC_CFG_FES_GET(value) (((value) & 0x00004000) >> 14)
815 /* Produces a ALT_EMAC_GMAC_MAC_CFG_FES register field value suitable for setting the register. */
816 #define ALT_EMAC_GMAC_MAC_CFG_FES_SET(value) (((value) << 14) & 0x00004000)
817 
818 /*
819  * Field : ps
820  *
821  * Port Select
822  *
823  * This bit selects the Ethernet line speed:
824  *
825  * * 0: For 1000 Mbps operations
826  *
827  * * 1: For 10 or 100 Mbps operations
828  *
829  * In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact
830  * line speed. In the 10 or 100 Mbps-only (always 1) or 1000 Mbps-only (always 0)
831  * configurations, this bit is read-only with the appropriate value. In default 10,
832  * 100, or 1000 Mbps configuration, this bit is R_W. The mac_portselect_o signal
833  * reflects the value of this bit.
834  *
835  * Field Enumeration Values:
836  *
837  * Enum | Value | Description
838  * :---------------------------------------|:------|:------------
839  * ALT_EMAC_GMAC_MAC_CFG_PS_E_GMII1000SEL | 0x0 |
840  * ALT_EMAC_GMAC_MAC_CFG_PS_E_MII10100SEL | 0x1 |
841  *
842  * Field Access Macros:
843  *
844  */
845 /*
846  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PS
847  *
848  */
849 #define ALT_EMAC_GMAC_MAC_CFG_PS_E_GMII1000SEL 0x0
850 /*
851  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PS
852  *
853  */
854 #define ALT_EMAC_GMAC_MAC_CFG_PS_E_MII10100SEL 0x1
855 
856 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_PS register field. */
857 #define ALT_EMAC_GMAC_MAC_CFG_PS_LSB 15
858 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_PS register field. */
859 #define ALT_EMAC_GMAC_MAC_CFG_PS_MSB 15
860 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_PS register field. */
861 #define ALT_EMAC_GMAC_MAC_CFG_PS_WIDTH 1
862 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_PS register field value. */
863 #define ALT_EMAC_GMAC_MAC_CFG_PS_SET_MSK 0x00008000
864 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_PS register field value. */
865 #define ALT_EMAC_GMAC_MAC_CFG_PS_CLR_MSK 0xffff7fff
866 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_PS register field. */
867 #define ALT_EMAC_GMAC_MAC_CFG_PS_RESET 0x0
868 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_PS field value from a register. */
869 #define ALT_EMAC_GMAC_MAC_CFG_PS_GET(value) (((value) & 0x00008000) >> 15)
870 /* Produces a ALT_EMAC_GMAC_MAC_CFG_PS register field value suitable for setting the register. */
871 #define ALT_EMAC_GMAC_MAC_CFG_PS_SET(value) (((value) << 15) & 0x00008000)
872 
873 /*
874  * Field : dcrs
875  *
876  * Disable Carrier Sense During Transmission
877  *
878  * When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal
879  * during frame transmission in the half-duplex mode. This request results in no
880  * errors generated because of Loss of Carrier or No Carrier during such
881  * transmission. When this bit is low, the MAC transmitter generates such errors
882  * because of Carrier Sense and can even abort the transmissions.
883  *
884  * This bit is reserved (and RO) in the full-duplex-only configurations.
885  *
886  * Field Enumeration Values:
887  *
888  * Enum | Value | Description
889  * :----------------------------------|:------|:------------
890  * ALT_EMAC_GMAC_MAC_CFG_DCRS_E_DISD | 0x0 |
891  * ALT_EMAC_GMAC_MAC_CFG_DCRS_E_END | 0x1 |
892  *
893  * Field Access Macros:
894  *
895  */
896 /*
897  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DCRS
898  *
899  */
900 #define ALT_EMAC_GMAC_MAC_CFG_DCRS_E_DISD 0x0
901 /*
902  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DCRS
903  *
904  */
905 #define ALT_EMAC_GMAC_MAC_CFG_DCRS_E_END 0x1
906 
907 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field. */
908 #define ALT_EMAC_GMAC_MAC_CFG_DCRS_LSB 16
909 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field. */
910 #define ALT_EMAC_GMAC_MAC_CFG_DCRS_MSB 16
911 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field. */
912 #define ALT_EMAC_GMAC_MAC_CFG_DCRS_WIDTH 1
913 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DCRS register field value. */
914 #define ALT_EMAC_GMAC_MAC_CFG_DCRS_SET_MSK 0x00010000
915 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DCRS register field value. */
916 #define ALT_EMAC_GMAC_MAC_CFG_DCRS_CLR_MSK 0xfffeffff
917 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field. */
918 #define ALT_EMAC_GMAC_MAC_CFG_DCRS_RESET 0x0
919 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_DCRS field value from a register. */
920 #define ALT_EMAC_GMAC_MAC_CFG_DCRS_GET(value) (((value) & 0x00010000) >> 16)
921 /* Produces a ALT_EMAC_GMAC_MAC_CFG_DCRS register field value suitable for setting the register. */
922 #define ALT_EMAC_GMAC_MAC_CFG_DCRS_SET(value) (((value) << 16) & 0x00010000)
923 
924 /*
925  * Field : ifg
926  *
927  * Inter-Frame Gap
928  *
929  * These bits control the minimum IFG between frames during transmission.
930  *
931  * * 000: 96 bit times
932  *
933  * * 001: 88 bit times
934  *
935  * * 010: 80 bit times
936  *
937  * * ...
938  *
939  * * 111: 40 bit times
940  *
941  * In the half-duplex mode, the minimum IFG can be configured only for 64 bit times
942  * (IFG = 100). Lower values are not considered. In the 1000-Mbps mode, the minimum
943  * IFG supported is 64 bit times (and above) in the GMAC-CORE configuration and 80
944  * bit times (and above) in other configurations.
945  *
946  * Field Enumeration Values:
947  *
948  * Enum | Value | Description
949  * :------------------------------------------|:------|:------------
950  * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG96BITTIMES | 0x0 |
951  * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG88BITTIMES | 0x1 |
952  * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG80BITTIMES | 0x2 |
953  * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG72BITTIMES | 0x3 |
954  * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG64BITTIMES | 0x4 |
955  * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG56BITTIMES | 0x5 |
956  * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG48BITTIMES | 0x6 |
957  * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG40BITTIMES | 0x7 |
958  *
959  * Field Access Macros:
960  *
961  */
962 /*
963  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
964  *
965  */
966 #define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG96BITTIMES 0x0
967 /*
968  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
969  *
970  */
971 #define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG88BITTIMES 0x1
972 /*
973  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
974  *
975  */
976 #define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG80BITTIMES 0x2
977 /*
978  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
979  *
980  */
981 #define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG72BITTIMES 0x3
982 /*
983  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
984  *
985  */
986 #define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG64BITTIMES 0x4
987 /*
988  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
989  *
990  */
991 #define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG56BITTIMES 0x5
992 /*
993  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
994  *
995  */
996 #define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG48BITTIMES 0x6
997 /*
998  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
999  *
1000  */
1001 #define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG40BITTIMES 0x7
1002 
1003 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_IFG register field. */
1004 #define ALT_EMAC_GMAC_MAC_CFG_IFG_LSB 17
1005 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_IFG register field. */
1006 #define ALT_EMAC_GMAC_MAC_CFG_IFG_MSB 19
1007 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_IFG register field. */
1008 #define ALT_EMAC_GMAC_MAC_CFG_IFG_WIDTH 3
1009 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_IFG register field value. */
1010 #define ALT_EMAC_GMAC_MAC_CFG_IFG_SET_MSK 0x000e0000
1011 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_IFG register field value. */
1012 #define ALT_EMAC_GMAC_MAC_CFG_IFG_CLR_MSK 0xfff1ffff
1013 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_IFG register field. */
1014 #define ALT_EMAC_GMAC_MAC_CFG_IFG_RESET 0x0
1015 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_IFG field value from a register. */
1016 #define ALT_EMAC_GMAC_MAC_CFG_IFG_GET(value) (((value) & 0x000e0000) >> 17)
1017 /* Produces a ALT_EMAC_GMAC_MAC_CFG_IFG register field value suitable for setting the register. */
1018 #define ALT_EMAC_GMAC_MAC_CFG_IFG_SET(value) (((value) << 17) & 0x000e0000)
1019 
1020 /*
1021  * Field : je
1022  *
1023  * Jumbo Frame Enable
1024  *
1025  * When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes
1026  * for VLAN tagged frames) without reporting a giant frame error in the receive
1027  * frame status.
1028  *
1029  * Field Enumeration Values:
1030  *
1031  * Enum | Value | Description
1032  * :--------------------------------|:------|:------------
1033  * ALT_EMAC_GMAC_MAC_CFG_JE_E_DISD | 0x0 |
1034  * ALT_EMAC_GMAC_MAC_CFG_JE_E_END | 0x1 |
1035  *
1036  * Field Access Macros:
1037  *
1038  */
1039 /*
1040  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JE
1041  *
1042  */
1043 #define ALT_EMAC_GMAC_MAC_CFG_JE_E_DISD 0x0
1044 /*
1045  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JE
1046  *
1047  */
1048 #define ALT_EMAC_GMAC_MAC_CFG_JE_E_END 0x1
1049 
1050 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_JE register field. */
1051 #define ALT_EMAC_GMAC_MAC_CFG_JE_LSB 20
1052 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_JE register field. */
1053 #define ALT_EMAC_GMAC_MAC_CFG_JE_MSB 20
1054 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_JE register field. */
1055 #define ALT_EMAC_GMAC_MAC_CFG_JE_WIDTH 1
1056 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_JE register field value. */
1057 #define ALT_EMAC_GMAC_MAC_CFG_JE_SET_MSK 0x00100000
1058 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_JE register field value. */
1059 #define ALT_EMAC_GMAC_MAC_CFG_JE_CLR_MSK 0xffefffff
1060 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_JE register field. */
1061 #define ALT_EMAC_GMAC_MAC_CFG_JE_RESET 0x0
1062 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_JE field value from a register. */
1063 #define ALT_EMAC_GMAC_MAC_CFG_JE_GET(value) (((value) & 0x00100000) >> 20)
1064 /* Produces a ALT_EMAC_GMAC_MAC_CFG_JE register field value suitable for setting the register. */
1065 #define ALT_EMAC_GMAC_MAC_CFG_JE_SET(value) (((value) << 20) & 0x00100000)
1066 
1067 /*
1068  * Field : be
1069  *
1070  * Frame Burst Enable
1071  *
1072  * When this bit is set, the MAC allows frame bursting during transmission in the
1073  * GMII half-duplex mode. This bit is reserved (and RO) in the 10/100 Mbps only or
1074  * full-duplex-only configurations.
1075  *
1076  * Field Enumeration Values:
1077  *
1078  * Enum | Value | Description
1079  * :--------------------------------|:------|:------------
1080  * ALT_EMAC_GMAC_MAC_CFG_BE_E_DISD | 0x0 |
1081  * ALT_EMAC_GMAC_MAC_CFG_BE_E_END | 0x1 |
1082  *
1083  * Field Access Macros:
1084  *
1085  */
1086 /*
1087  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BE
1088  *
1089  */
1090 #define ALT_EMAC_GMAC_MAC_CFG_BE_E_DISD 0x0
1091 /*
1092  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BE
1093  *
1094  */
1095 #define ALT_EMAC_GMAC_MAC_CFG_BE_E_END 0x1
1096 
1097 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_BE register field. */
1098 #define ALT_EMAC_GMAC_MAC_CFG_BE_LSB 21
1099 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_BE register field. */
1100 #define ALT_EMAC_GMAC_MAC_CFG_BE_MSB 21
1101 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_BE register field. */
1102 #define ALT_EMAC_GMAC_MAC_CFG_BE_WIDTH 1
1103 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_BE register field value. */
1104 #define ALT_EMAC_GMAC_MAC_CFG_BE_SET_MSK 0x00200000
1105 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_BE register field value. */
1106 #define ALT_EMAC_GMAC_MAC_CFG_BE_CLR_MSK 0xffdfffff
1107 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_BE register field. */
1108 #define ALT_EMAC_GMAC_MAC_CFG_BE_RESET 0x0
1109 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_BE field value from a register. */
1110 #define ALT_EMAC_GMAC_MAC_CFG_BE_GET(value) (((value) & 0x00200000) >> 21)
1111 /* Produces a ALT_EMAC_GMAC_MAC_CFG_BE register field value suitable for setting the register. */
1112 #define ALT_EMAC_GMAC_MAC_CFG_BE_SET(value) (((value) << 21) & 0x00200000)
1113 
1114 /*
1115  * Field : jd
1116  *
1117  * Jabber Disable
1118  *
1119  * When this bit is set, the MAC disables the jabber timer on the transmitter. The
1120  * MAC can transfer frames of up to 16,384 bytes.
1121  *
1122  * When this bit is reset, the MAC cuts off the transmitter if the application
1123  * sends out more than 2,048 bytes of data (10,240 if JE is set high) during
1124  * transmission.
1125  *
1126  * Field Enumeration Values:
1127  *
1128  * Enum | Value | Description
1129  * :--------------------------------|:------|:------------
1130  * ALT_EMAC_GMAC_MAC_CFG_JD_E_END | 0x0 |
1131  * ALT_EMAC_GMAC_MAC_CFG_JD_E_DISD | 0x1 |
1132  *
1133  * Field Access Macros:
1134  *
1135  */
1136 /*
1137  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JD
1138  *
1139  */
1140 #define ALT_EMAC_GMAC_MAC_CFG_JD_E_END 0x0
1141 /*
1142  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JD
1143  *
1144  */
1145 #define ALT_EMAC_GMAC_MAC_CFG_JD_E_DISD 0x1
1146 
1147 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_JD register field. */
1148 #define ALT_EMAC_GMAC_MAC_CFG_JD_LSB 22
1149 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_JD register field. */
1150 #define ALT_EMAC_GMAC_MAC_CFG_JD_MSB 22
1151 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_JD register field. */
1152 #define ALT_EMAC_GMAC_MAC_CFG_JD_WIDTH 1
1153 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_JD register field value. */
1154 #define ALT_EMAC_GMAC_MAC_CFG_JD_SET_MSK 0x00400000
1155 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_JD register field value. */
1156 #define ALT_EMAC_GMAC_MAC_CFG_JD_CLR_MSK 0xffbfffff
1157 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_JD register field. */
1158 #define ALT_EMAC_GMAC_MAC_CFG_JD_RESET 0x0
1159 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_JD field value from a register. */
1160 #define ALT_EMAC_GMAC_MAC_CFG_JD_GET(value) (((value) & 0x00400000) >> 22)
1161 /* Produces a ALT_EMAC_GMAC_MAC_CFG_JD register field value suitable for setting the register. */
1162 #define ALT_EMAC_GMAC_MAC_CFG_JD_SET(value) (((value) << 22) & 0x00400000)
1163 
1164 /*
1165  * Field : wd
1166  *
1167  * Watchdog Disable
1168  *
1169  * When this bit is set, the MAC disables the watchdog timer on the receiver. The
1170  * MAC can receive frames of up to 16,384 bytes.
1171  *
1172  * When this bit is reset, the MAC does not allow a receive frame which more than
1173  * 2,048 bytes (10,240 if JE is set high) or the value programmed in Register 55
1174  * (Watchdog Timeout Register).
1175  *
1176  * The MAC cuts off any bytes received after the watchdog limit number of bytes.
1177  *
1178  * Field Enumeration Values:
1179  *
1180  * Enum | Value | Description
1181  * :--------------------------------|:------|:------------
1182  * ALT_EMAC_GMAC_MAC_CFG_WD_E_END | 0x0 |
1183  * ALT_EMAC_GMAC_MAC_CFG_WD_E_DISD | 0x1 |
1184  *
1185  * Field Access Macros:
1186  *
1187  */
1188 /*
1189  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_WD
1190  *
1191  */
1192 #define ALT_EMAC_GMAC_MAC_CFG_WD_E_END 0x0
1193 /*
1194  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_WD
1195  *
1196  */
1197 #define ALT_EMAC_GMAC_MAC_CFG_WD_E_DISD 0x1
1198 
1199 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_WD register field. */
1200 #define ALT_EMAC_GMAC_MAC_CFG_WD_LSB 23
1201 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_WD register field. */
1202 #define ALT_EMAC_GMAC_MAC_CFG_WD_MSB 23
1203 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_WD register field. */
1204 #define ALT_EMAC_GMAC_MAC_CFG_WD_WIDTH 1
1205 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_WD register field value. */
1206 #define ALT_EMAC_GMAC_MAC_CFG_WD_SET_MSK 0x00800000
1207 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_WD register field value. */
1208 #define ALT_EMAC_GMAC_MAC_CFG_WD_CLR_MSK 0xff7fffff
1209 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_WD register field. */
1210 #define ALT_EMAC_GMAC_MAC_CFG_WD_RESET 0x0
1211 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_WD field value from a register. */
1212 #define ALT_EMAC_GMAC_MAC_CFG_WD_GET(value) (((value) & 0x00800000) >> 23)
1213 /* Produces a ALT_EMAC_GMAC_MAC_CFG_WD register field value suitable for setting the register. */
1214 #define ALT_EMAC_GMAC_MAC_CFG_WD_SET(value) (((value) << 23) & 0x00800000)
1215 
1216 /*
1217  * Field : tc
1218  *
1219  * Transmit Configuration in RGMII, SGMII, or SMII
1220  *
1221  * When set, this bit enables the transmission of duplex mode, link speed, and link
1222  * up or down information to the PHY in the RGMII, SMII, or SGMII port. When this
1223  * bit is reset, no such information is driven to the PHY. This bit is reserved
1224  * (and RO) if the RGMII, SMII, or SGMII PHY port is not selected during core
1225  * configuration.
1226  *
1227  * Field Enumeration Values:
1228  *
1229  * Enum | Value | Description
1230  * :--------------------------------|:------|:------------
1231  * ALT_EMAC_GMAC_MAC_CFG_TC_E_DISD | 0x0 |
1232  * ALT_EMAC_GMAC_MAC_CFG_TC_E_END | 0x1 |
1233  *
1234  * Field Access Macros:
1235  *
1236  */
1237 /*
1238  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TC
1239  *
1240  */
1241 #define ALT_EMAC_GMAC_MAC_CFG_TC_E_DISD 0x0
1242 /*
1243  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TC
1244  *
1245  */
1246 #define ALT_EMAC_GMAC_MAC_CFG_TC_E_END 0x1
1247 
1248 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_TC register field. */
1249 #define ALT_EMAC_GMAC_MAC_CFG_TC_LSB 24
1250 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_TC register field. */
1251 #define ALT_EMAC_GMAC_MAC_CFG_TC_MSB 24
1252 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_TC register field. */
1253 #define ALT_EMAC_GMAC_MAC_CFG_TC_WIDTH 1
1254 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_TC register field value. */
1255 #define ALT_EMAC_GMAC_MAC_CFG_TC_SET_MSK 0x01000000
1256 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_TC register field value. */
1257 #define ALT_EMAC_GMAC_MAC_CFG_TC_CLR_MSK 0xfeffffff
1258 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_TC register field. */
1259 #define ALT_EMAC_GMAC_MAC_CFG_TC_RESET 0x0
1260 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_TC field value from a register. */
1261 #define ALT_EMAC_GMAC_MAC_CFG_TC_GET(value) (((value) & 0x01000000) >> 24)
1262 /* Produces a ALT_EMAC_GMAC_MAC_CFG_TC register field value suitable for setting the register. */
1263 #define ALT_EMAC_GMAC_MAC_CFG_TC_SET(value) (((value) << 24) & 0x01000000)
1264 
1265 /*
1266  * Field : cst
1267  *
1268  * CRC Stripping for Type Frames
1269  *
1270  * When this bit is set, the last 4 bytes (FCS) of all frames of Ether type
1271  * (Length/Type field greater than or equal to 1,536) are stripped and dropped
1272  * before forwarding the frame to the application. This function is not valid when
1273  * the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is
1274  * valid when Type 2 Checksum Offload Engine is enabled.
1275  *
1276  * Field Enumeration Values:
1277  *
1278  * Enum | Value | Description
1279  * :---------------------------------|:------|:------------
1280  * ALT_EMAC_GMAC_MAC_CFG_CST_E_DISD | 0x0 |
1281  * ALT_EMAC_GMAC_MAC_CFG_CST_E_END | 0x1 |
1282  *
1283  * Field Access Macros:
1284  *
1285  */
1286 /*
1287  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_CST
1288  *
1289  */
1290 #define ALT_EMAC_GMAC_MAC_CFG_CST_E_DISD 0x0
1291 /*
1292  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_CST
1293  *
1294  */
1295 #define ALT_EMAC_GMAC_MAC_CFG_CST_E_END 0x1
1296 
1297 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_CST register field. */
1298 #define ALT_EMAC_GMAC_MAC_CFG_CST_LSB 25
1299 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_CST register field. */
1300 #define ALT_EMAC_GMAC_MAC_CFG_CST_MSB 25
1301 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_CST register field. */
1302 #define ALT_EMAC_GMAC_MAC_CFG_CST_WIDTH 1
1303 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_CST register field value. */
1304 #define ALT_EMAC_GMAC_MAC_CFG_CST_SET_MSK 0x02000000
1305 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_CST register field value. */
1306 #define ALT_EMAC_GMAC_MAC_CFG_CST_CLR_MSK 0xfdffffff
1307 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_CST register field. */
1308 #define ALT_EMAC_GMAC_MAC_CFG_CST_RESET 0x0
1309 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_CST field value from a register. */
1310 #define ALT_EMAC_GMAC_MAC_CFG_CST_GET(value) (((value) & 0x02000000) >> 25)
1311 /* Produces a ALT_EMAC_GMAC_MAC_CFG_CST register field value suitable for setting the register. */
1312 #define ALT_EMAC_GMAC_MAC_CFG_CST_SET(value) (((value) << 25) & 0x02000000)
1313 
1314 /*
1315  * Field : sfterr
1316  *
1317  * SMII Force Transmit Error
1318  *
1319  * When set, this bit indicates to the PHY to force a transmit error in the SMII
1320  * frame being transmitted. This bit is reserved if the SMII PHY port is not
1321  * selected during core configuration.
1322  *
1323  * Field Access Macros:
1324  *
1325  */
1326 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_SFTERR register field. */
1327 #define ALT_EMAC_GMAC_MAC_CFG_SFTERR_LSB 26
1328 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_SFTERR register field. */
1329 #define ALT_EMAC_GMAC_MAC_CFG_SFTERR_MSB 26
1330 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_SFTERR register field. */
1331 #define ALT_EMAC_GMAC_MAC_CFG_SFTERR_WIDTH 1
1332 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_SFTERR register field value. */
1333 #define ALT_EMAC_GMAC_MAC_CFG_SFTERR_SET_MSK 0x04000000
1334 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_SFTERR register field value. */
1335 #define ALT_EMAC_GMAC_MAC_CFG_SFTERR_CLR_MSK 0xfbffffff
1336 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_SFTERR register field. */
1337 #define ALT_EMAC_GMAC_MAC_CFG_SFTERR_RESET 0x0
1338 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_SFTERR field value from a register. */
1339 #define ALT_EMAC_GMAC_MAC_CFG_SFTERR_GET(value) (((value) & 0x04000000) >> 26)
1340 /* Produces a ALT_EMAC_GMAC_MAC_CFG_SFTERR register field value suitable for setting the register. */
1341 #define ALT_EMAC_GMAC_MAC_CFG_SFTERR_SET(value) (((value) << 26) & 0x04000000)
1342 
1343 /*
1344  * Field : twokpe
1345  *
1346  * IEEE 802.3as Support for 2K Packets
1347  *
1348  * When set, the MAC considers all frames, with up to 2,000 bytes length, as normal
1349  * packets.
1350  *
1351  * When Bit 20 (JE) is not set, the MAC considers all received frames of size more
1352  * than 2K bytes as Giant frames. When this bit is reset and Bit 20 (JE) is not
1353  * set, the MAC considers all received frames of size more than 1,518 bytes (1,522
1354  * bytes for tagged) as Giant frames. When Bit 20 is set, setting this bit has no
1355  * effect on Giant Frame status.
1356  *
1357  * Field Access Macros:
1358  *
1359  */
1360 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field. */
1361 #define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_LSB 27
1362 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field. */
1363 #define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_MSB 27
1364 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field. */
1365 #define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_WIDTH 1
1366 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field value. */
1367 #define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_SET_MSK 0x08000000
1368 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field value. */
1369 #define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_CLR_MSK 0xf7ffffff
1370 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field. */
1371 #define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_RESET 0x0
1372 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_TWOKPE field value from a register. */
1373 #define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_GET(value) (((value) & 0x08000000) >> 27)
1374 /* Produces a ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field value suitable for setting the register. */
1375 #define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_SET(value) (((value) << 27) & 0x08000000)
1376 
1377 /*
1378  * Field : sarc
1379  *
1380  * Source Address Insertion or Replacement Control
1381  *
1382  * This field controls the source address insertion or replacement for all
1383  * transmitted frames. Bit 30 specifies which MAC Address register (0 or 1) is used
1384  * for source address insertion or replacement based on the values of Bits [29:28]:
1385  *
1386  * * 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field
1387  * generation.
1388  *
1389  * * 2'b10:
1390  *
1391  * - If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0
1392  * registers (registers 16 and 17) in the SA field of all transmitted frames.
1393  *
1394  * - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is
1395  * selected during core configuration, the MAC inserts the content of the MAC
1396  * Address 1 registers (registers 18 and 19) in the SA field of all
1397  * transmitted frames.
1398  *
1399  * * 2'b11:
1400  *
1401  * - If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0
1402  * registers (registers 16 and 17) in the SA field of all transmitted frames.
1403  *
1404  * - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is
1405  * selected during core configuration, the MAC replaces the content of the
1406  * MAC Address 1 registers (registers 18 and 19) in the SA field of all
1407  * transmitted frames.
1408  *
1409  * Note:
1410  *
1411  * - Changes to this field take effect only on the start of a frame. If you
1412  * write this register field when a frame is being transmitted, only the
1413  * subsequent frame can use the updated value, that is, the current frame
1414  * does not use the updated value.
1415  *
1416  * - These bits are reserved and RO when the Enable SA, VLAN, and CRC Insertion
1417  * on TX feature is not selected during core configuration.
1418  *
1419  * Field Access Macros:
1420  *
1421  */
1422 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_SARC register field. */
1423 #define ALT_EMAC_GMAC_MAC_CFG_SARC_LSB 28
1424 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_SARC register field. */
1425 #define ALT_EMAC_GMAC_MAC_CFG_SARC_MSB 30
1426 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_SARC register field. */
1427 #define ALT_EMAC_GMAC_MAC_CFG_SARC_WIDTH 3
1428 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_SARC register field value. */
1429 #define ALT_EMAC_GMAC_MAC_CFG_SARC_SET_MSK 0x70000000
1430 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_SARC register field value. */
1431 #define ALT_EMAC_GMAC_MAC_CFG_SARC_CLR_MSK 0x8fffffff
1432 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_SARC register field. */
1433 #define ALT_EMAC_GMAC_MAC_CFG_SARC_RESET 0x0
1434 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_SARC field value from a register. */
1435 #define ALT_EMAC_GMAC_MAC_CFG_SARC_GET(value) (((value) & 0x70000000) >> 28)
1436 /* Produces a ALT_EMAC_GMAC_MAC_CFG_SARC register field value suitable for setting the register. */
1437 #define ALT_EMAC_GMAC_MAC_CFG_SARC_SET(value) (((value) << 28) & 0x70000000)
1438 
1439 /*
1440  * Field : reserved_31
1441  *
1442  * Reserved
1443  *
1444  * Field Access Macros:
1445  *
1446  */
1447 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_RSVD_31 register field. */
1448 #define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_LSB 31
1449 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_RSVD_31 register field. */
1450 #define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_MSB 31
1451 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_RSVD_31 register field. */
1452 #define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_WIDTH 1
1453 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_RSVD_31 register field value. */
1454 #define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_SET_MSK 0x80000000
1455 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_RSVD_31 register field value. */
1456 #define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_CLR_MSK 0x7fffffff
1457 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_RSVD_31 register field. */
1458 #define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_RESET 0x0
1459 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_RSVD_31 field value from a register. */
1460 #define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_GET(value) (((value) & 0x80000000) >> 31)
1461 /* Produces a ALT_EMAC_GMAC_MAC_CFG_RSVD_31 register field value suitable for setting the register. */
1462 #define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_SET(value) (((value) << 31) & 0x80000000)
1463 
1464 #ifndef __ASSEMBLY__
1465 /*
1466  * WARNING: The C register and register group struct declarations are provided for
1467  * convenience and illustrative purposes. They should, however, be used with
1468  * caution as the C language standard provides no guarantees about the alignment or
1469  * atomicity of device memory accesses. The recommended practice for writing
1470  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1471  * alt_write_word() functions.
1472  *
1473  * The struct declaration for register ALT_EMAC_GMAC_MAC_CFG.
1474  */
1475 struct ALT_EMAC_GMAC_MAC_CFG_s
1476 {
1477  uint32_t prelen : 2; /* ALT_EMAC_GMAC_MAC_CFG_PRELEN */
1478  uint32_t re : 1; /* ALT_EMAC_GMAC_MAC_CFG_RE */
1479  uint32_t te : 1; /* ALT_EMAC_GMAC_MAC_CFG_TE */
1480  uint32_t dc : 1; /* ALT_EMAC_GMAC_MAC_CFG_DC */
1481  uint32_t bl : 2; /* ALT_EMAC_GMAC_MAC_CFG_BL */
1482  uint32_t acs : 1; /* ALT_EMAC_GMAC_MAC_CFG_ACS */
1483  const uint32_t lud : 1; /* ALT_EMAC_GMAC_MAC_CFG_LUD */
1484  uint32_t dr : 1; /* ALT_EMAC_GMAC_MAC_CFG_DR */
1485  uint32_t ipc : 1; /* ALT_EMAC_GMAC_MAC_CFG_IPC */
1486  uint32_t dm : 1; /* ALT_EMAC_GMAC_MAC_CFG_DM */
1487  uint32_t lm : 1; /* ALT_EMAC_GMAC_MAC_CFG_LM */
1488  uint32_t do_ : 1; /* ALT_EMAC_GMAC_MAC_CFG_DO */
1489  uint32_t fes : 1; /* ALT_EMAC_GMAC_MAC_CFG_FES */
1490  uint32_t ps : 1; /* ALT_EMAC_GMAC_MAC_CFG_PS */
1491  uint32_t dcrs : 1; /* ALT_EMAC_GMAC_MAC_CFG_DCRS */
1492  uint32_t ifg : 3; /* ALT_EMAC_GMAC_MAC_CFG_IFG */
1493  uint32_t je : 1; /* ALT_EMAC_GMAC_MAC_CFG_JE */
1494  uint32_t be : 1; /* ALT_EMAC_GMAC_MAC_CFG_BE */
1495  uint32_t jd : 1; /* ALT_EMAC_GMAC_MAC_CFG_JD */
1496  uint32_t wd : 1; /* ALT_EMAC_GMAC_MAC_CFG_WD */
1497  const uint32_t tc : 1; /* ALT_EMAC_GMAC_MAC_CFG_TC */
1498  uint32_t cst : 1; /* ALT_EMAC_GMAC_MAC_CFG_CST */
1499  const uint32_t sfterr : 1; /* ALT_EMAC_GMAC_MAC_CFG_SFTERR */
1500  uint32_t twokpe : 1; /* ALT_EMAC_GMAC_MAC_CFG_TWOKPE */
1501  uint32_t sarc : 3; /* ALT_EMAC_GMAC_MAC_CFG_SARC */
1502  const uint32_t reserved_31 : 1; /* ALT_EMAC_GMAC_MAC_CFG_RSVD_31 */
1503 };
1504 
1505 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_CFG. */
1506 typedef volatile struct ALT_EMAC_GMAC_MAC_CFG_s ALT_EMAC_GMAC_MAC_CFG_t;
1507 #endif /* __ASSEMBLY__ */
1508 
1509 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG register. */
1510 #define ALT_EMAC_GMAC_MAC_CFG_RESET 0x00000000
1511 /* The byte offset of the ALT_EMAC_GMAC_MAC_CFG register from the beginning of the component. */
1512 #define ALT_EMAC_GMAC_MAC_CFG_OFST 0x0
1513 /* The address of the ALT_EMAC_GMAC_MAC_CFG register. */
1514 #define ALT_EMAC_GMAC_MAC_CFG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_CFG_OFST))
1515 
1516 /*
1517  * Register : gmacgrp_mac_frame_filter
1518  *
1519  * <b> Register 1 (MAC Frame Filter) </b>
1520  *
1521  * The MAC Frame Filter register contains the filter controls for receiving frames.
1522  * Some of the controls from this register go to the address check block of the
1523  * MAC, which performs the first level of address filtering. The second level of
1524  * filtering is performed on the incoming frame, based on other controls such as
1525  * Pass Bad Frames and Pass Control Frames.
1526  *
1527  * Register Layout
1528  *
1529  * Bits | Access | Reset | Description
1530  * :--------|:-------|:------|:-------------------------------------
1531  * [0] | RW | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_PR
1532  * [1] | R | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_HUC
1533  * [2] | R | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_HMC
1534  * [3] | RW | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF
1535  * [4] | RW | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_PM
1536  * [5] | RW | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_DBF
1537  * [7:6] | RW | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_PCF
1538  * [8] | RW | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF
1539  * [9] | RW | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_SAF
1540  * [10] | R | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_HPF
1541  * [15:11] | R | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11
1542  * [16] | RW | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE
1543  * [19:17] | R | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17
1544  * [20] | RW | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE
1545  * [21] | RW | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU
1546  * [30:22] | R | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22
1547  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_RA
1548  *
1549  */
1550 /*
1551  * Field : pr
1552  *
1553  * Promiscuous Mode
1554  *
1555  * When this bit is set, the Address Filter module passes all incoming frames
1556  * regardless of its destination or source address. The SA or DA Filter Fails
1557  * status bits of the Receive Status Word are always cleared when PR is set.
1558  *
1559  * Field Enumeration Values:
1560  *
1561  * Enum | Value | Description
1562  * :------------------------------------|:------|:------------
1563  * ALT_EMAC_GMAC_MAC_FRM_FLT_PR_E_DISD | 0x0 |
1564  * ALT_EMAC_GMAC_MAC_FRM_FLT_PR_E_END | 0x1 |
1565  *
1566  * Field Access Macros:
1567  *
1568  */
1569 /*
1570  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PR
1571  *
1572  */
1573 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_E_DISD 0x0
1574 /*
1575  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PR
1576  *
1577  */
1578 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_E_END 0x1
1579 
1580 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field. */
1581 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_LSB 0
1582 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field. */
1583 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_MSB 0
1584 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field. */
1585 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_WIDTH 1
1586 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field value. */
1587 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_SET_MSK 0x00000001
1588 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field value. */
1589 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_CLR_MSK 0xfffffffe
1590 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field. */
1591 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_RESET 0x0
1592 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_PR field value from a register. */
1593 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_GET(value) (((value) & 0x00000001) >> 0)
1594 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field value suitable for setting the register. */
1595 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_SET(value) (((value) << 0) & 0x00000001)
1596 
1597 /*
1598  * Field : huc
1599  *
1600  * Hash Unicast
1601  *
1602  * When set, MAC performs destination address filtering of unicast frames according
1603  * to the hash table.
1604  *
1605  * When reset, the MAC performs a perfect destination address filtering for unicast
1606  * frames, that is, it compares the DA field with the values programmed in DA
1607  * registers.
1608  *
1609  * If Hash Filter is not selected during core configuration, this bit is reserved
1610  * (and RO).
1611  *
1612  * Field Enumeration Values:
1613  *
1614  * Enum | Value | Description
1615  * :-------------------------------------|:------|:------------
1616  * ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_E_DISD | 0x0 |
1617  * ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_E_END | 0x1 |
1618  *
1619  * Field Access Macros:
1620  *
1621  */
1622 /*
1623  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HUC
1624  *
1625  */
1626 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_E_DISD 0x0
1627 /*
1628  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HUC
1629  *
1630  */
1631 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_E_END 0x1
1632 
1633 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field. */
1634 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_LSB 1
1635 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field. */
1636 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_MSB 1
1637 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field. */
1638 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_WIDTH 1
1639 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field value. */
1640 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_SET_MSK 0x00000002
1641 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field value. */
1642 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_CLR_MSK 0xfffffffd
1643 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field. */
1644 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_RESET 0x0
1645 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC field value from a register. */
1646 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_GET(value) (((value) & 0x00000002) >> 1)
1647 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field value suitable for setting the register. */
1648 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_SET(value) (((value) << 1) & 0x00000002)
1649 
1650 /*
1651  * Field : hmc
1652  *
1653  * Hash Multicast
1654  *
1655  * When set, MAC performs destination address filtering of received multicast
1656  * frames according to the hash table.
1657  *
1658  * When reset, the MAC performs a perfect destination address filtering for
1659  * multicast frames, that is, it compares the DA field with the values programmed
1660  * in DA registers.
1661  *
1662  * If Hash Filter is not selected during core configuration, this bit is reserved
1663  * (and RO).
1664  *
1665  * Field Enumeration Values:
1666  *
1667  * Enum | Value | Description
1668  * :-------------------------------------|:------|:------------
1669  * ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_E_DISD | 0x0 |
1670  * ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_E_END | 0x1 |
1671  *
1672  * Field Access Macros:
1673  *
1674  */
1675 /*
1676  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HMC
1677  *
1678  */
1679 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_E_DISD 0x0
1680 /*
1681  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HMC
1682  *
1683  */
1684 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_E_END 0x1
1685 
1686 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field. */
1687 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_LSB 2
1688 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field. */
1689 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_MSB 2
1690 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field. */
1691 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_WIDTH 1
1692 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field value. */
1693 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_SET_MSK 0x00000004
1694 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field value. */
1695 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_CLR_MSK 0xfffffffb
1696 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field. */
1697 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_RESET 0x0
1698 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC field value from a register. */
1699 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_GET(value) (((value) & 0x00000004) >> 2)
1700 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field value suitable for setting the register. */
1701 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_SET(value) (((value) << 2) & 0x00000004)
1702 
1703 /*
1704  * Field : daif
1705  *
1706  * DA Inverse Filtering
1707  *
1708  * When this bit is set, the Address Check block operates in inverse filtering mode
1709  * for the DA address comparison for both unicast and multicast frames.
1710  *
1711  * When reset, normal filtering of frames is performed.
1712  *
1713  * Field Enumeration Values:
1714  *
1715  * Enum | Value | Description
1716  * :--------------------------------------|:------|:------------
1717  * ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_E_DISD | 0x0 |
1718  * ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_E_END | 0x1 |
1719  *
1720  * Field Access Macros:
1721  *
1722  */
1723 /*
1724  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF
1725  *
1726  */
1727 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_E_DISD 0x0
1728 /*
1729  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF
1730  *
1731  */
1732 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_E_END 0x1
1733 
1734 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field. */
1735 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_LSB 3
1736 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field. */
1737 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_MSB 3
1738 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field. */
1739 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_WIDTH 1
1740 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field value. */
1741 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_SET_MSK 0x00000008
1742 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field value. */
1743 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_CLR_MSK 0xfffffff7
1744 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field. */
1745 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_RESET 0x0
1746 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF field value from a register. */
1747 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_GET(value) (((value) & 0x00000008) >> 3)
1748 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field value suitable for setting the register. */
1749 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_SET(value) (((value) << 3) & 0x00000008)
1750 
1751 /*
1752  * Field : pm
1753  *
1754  * Pass All Multicast
1755  *
1756  * When set, this bit indicates that all received frames with a multicast
1757  * destination address (first bit in the destination address field is '1') are
1758  * passed.
1759  *
1760  * When reset, filtering of multicast frame depends on HMC bit.
1761  *
1762  * Field Enumeration Values:
1763  *
1764  * Enum | Value | Description
1765  * :------------------------------------|:------|:------------
1766  * ALT_EMAC_GMAC_MAC_FRM_FLT_PM_E_DISD | 0x0 |
1767  * ALT_EMAC_GMAC_MAC_FRM_FLT_PM_E_END | 0x1 |
1768  *
1769  * Field Access Macros:
1770  *
1771  */
1772 /*
1773  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PM
1774  *
1775  */
1776 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_E_DISD 0x0
1777 /*
1778  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PM
1779  *
1780  */
1781 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_E_END 0x1
1782 
1783 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field. */
1784 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_LSB 4
1785 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field. */
1786 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_MSB 4
1787 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field. */
1788 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_WIDTH 1
1789 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field value. */
1790 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_SET_MSK 0x00000010
1791 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field value. */
1792 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_CLR_MSK 0xffffffef
1793 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field. */
1794 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_RESET 0x0
1795 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_PM field value from a register. */
1796 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_GET(value) (((value) & 0x00000010) >> 4)
1797 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field value suitable for setting the register. */
1798 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_SET(value) (((value) << 4) & 0x00000010)
1799 
1800 /*
1801  * Field : dbf
1802  *
1803  * Disable Broadcast Frames
1804  *
1805  * When this bit is set, the AFM module filters all incoming broadcast frames. In
1806  * addition, it overrides all other filter settings.
1807  *
1808  * When this bit is reset, the AFM module passes all received broadcast frames.
1809  *
1810  * Field Enumeration Values:
1811  *
1812  * Enum | Value | Description
1813  * :-------------------------------------|:------|:------------
1814  * ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_E_DISD | 0x0 |
1815  * ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_E_END | 0x1 |
1816  *
1817  * Field Access Macros:
1818  *
1819  */
1820 /*
1821  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DBF
1822  *
1823  */
1824 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_E_DISD 0x0
1825 /*
1826  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DBF
1827  *
1828  */
1829 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_E_END 0x1
1830 
1831 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field. */
1832 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_LSB 5
1833 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field. */
1834 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_MSB 5
1835 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field. */
1836 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_WIDTH 1
1837 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field value. */
1838 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_SET_MSK 0x00000020
1839 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field value. */
1840 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_CLR_MSK 0xffffffdf
1841 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field. */
1842 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_RESET 0x0
1843 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF field value from a register. */
1844 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_GET(value) (((value) & 0x00000020) >> 5)
1845 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field value suitable for setting the register. */
1846 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_SET(value) (((value) << 5) & 0x00000020)
1847 
1848 /*
1849  * Field : pcf
1850  *
1851  * Pass Control Frames
1852  *
1853  * These bits control the forwarding of all control frames (including unicast and
1854  * multicast PAUSE frames).
1855  *
1856  * * 00: MAC filters all control frames from reaching the application.
1857  *
1858  * * 01: MAC forwards all control frames except PAUSE control frames to application
1859  * even if they fail the Address filter.
1860  *
1861  * * 10: MAC forwards all control frames to application even if they fail the
1862  * Address Filter.
1863  *
1864  * * 11: MAC forwards control frames that pass the Address Filter.
1865  *
1866  * The following conditions should be true for the PAUSE control frames processing:
1867  *
1868  * * Condition 1: The MAC is in the full-duplex mode and flow control is enabled by
1869  * setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1.
1870  *
1871  * * Condition 2: The destination address (DA) of the received frame matches the
1872  * special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register
1873  * 6 (Flow Control Register) is set.
1874  *
1875  * * Condition 3: The Type field of the received frame is 0x8808 and the OPCODE
1876  * field is 0x0001.
1877  *
1878  * Note:
1879  *
1880  * This field should be set to 01 only when the Condition 1 is true, that is, the
1881  * MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled.
1882  * Otherwise, the PAUSE frame filtering may be inconsistent. When Condition 1 is
1883  * false, the PAUSE frames are considered as generic control frames. Therefore, to
1884  * pass all control frames (including PAUSE control frames) when the full-duplex
1885  * mode and flow control is not enabled, you should set the PCF field to 10 or 11
1886  * (as required by the application).
1887  *
1888  * Field Enumeration Values:
1889  *
1890  * Enum | Value | Description
1891  * :---------------------------------------------|:------|:------------
1892  * ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFLTALLCFR | 0x0 |
1893  * ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDXPAUSE | 0x1 |
1894  * ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDFAIL | 0x2 |
1895  * ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDPASS | 0x3 |
1896  *
1897  * Field Access Macros:
1898  *
1899  */
1900 /*
1901  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PCF
1902  *
1903  */
1904 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFLTALLCFR 0x0
1905 /*
1906  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PCF
1907  *
1908  */
1909 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDXPAUSE 0x1
1910 /*
1911  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PCF
1912  *
1913  */
1914 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDFAIL 0x2
1915 /*
1916  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PCF
1917  *
1918  */
1919 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDPASS 0x3
1920 
1921 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field. */
1922 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_LSB 6
1923 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field. */
1924 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_MSB 7
1925 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field. */
1926 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_WIDTH 2
1927 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field value. */
1928 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_SET_MSK 0x000000c0
1929 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field value. */
1930 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_CLR_MSK 0xffffff3f
1931 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field. */
1932 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_RESET 0x0
1933 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF field value from a register. */
1934 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_GET(value) (((value) & 0x000000c0) >> 6)
1935 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field value suitable for setting the register. */
1936 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_SET(value) (((value) << 6) & 0x000000c0)
1937 
1938 /*
1939  * Field : saif
1940  *
1941  * SA Inverse Filtering
1942  *
1943  * When this bit is set, the Address Check block operates in inverse filtering mode
1944  * for the SA address comparison. The frames whose SA matches the SA registers are
1945  * marked as failing the SA Address filter.
1946  *
1947  * When this bit is reset, frames whose SA does not match the SA registers are
1948  * marked as failing the SA Address filter.
1949  *
1950  * Field Enumeration Values:
1951  *
1952  * Enum | Value | Description
1953  * :--------------------------------------|:------|:------------
1954  * ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_E_DISD | 0x0 |
1955  * ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_E_END | 0x1 |
1956  *
1957  * Field Access Macros:
1958  *
1959  */
1960 /*
1961  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF
1962  *
1963  */
1964 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_E_DISD 0x0
1965 /*
1966  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF
1967  *
1968  */
1969 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_E_END 0x1
1970 
1971 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field. */
1972 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_LSB 8
1973 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field. */
1974 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_MSB 8
1975 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field. */
1976 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_WIDTH 1
1977 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field value. */
1978 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_SET_MSK 0x00000100
1979 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field value. */
1980 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_CLR_MSK 0xfffffeff
1981 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field. */
1982 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_RESET 0x0
1983 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF field value from a register. */
1984 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_GET(value) (((value) & 0x00000100) >> 8)
1985 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field value suitable for setting the register. */
1986 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_SET(value) (((value) << 8) & 0x00000100)
1987 
1988 /*
1989  * Field : saf
1990  *
1991  * Source Address Filter Enable
1992  *
1993  * When this bit is set, the MAC compares the SA field of the received frames with
1994  * the values programmed in the enabled SA registers. If the comparison fails, the
1995  * MAC drops the frame.
1996  *
1997  * When this bit is reset, the MAC forwards the received frame to the application
1998  * with updated SAF bit of the Rx Status depending on the SA address comparison.
1999  *
2000  * Note: According to the IEEE specification, Bit 47 of the SA is reserved and set
2001  * to 0. However, in DWC_gmac, the MAC compares all 48 bits. The software driver
2002  * should take this into consideration while programming the MAC address registers
2003  * for SA.
2004  *
2005  * Field Enumeration Values:
2006  *
2007  * Enum | Value | Description
2008  * :-------------------------------------|:------|:------------
2009  * ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_E_DISD | 0x0 |
2010  * ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_E_END | 0x1 |
2011  *
2012  * Field Access Macros:
2013  *
2014  */
2015 /*
2016  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_SAF
2017  *
2018  */
2019 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_E_DISD 0x0
2020 /*
2021  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_SAF
2022  *
2023  */
2024 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_E_END 0x1
2025 
2026 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field. */
2027 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_LSB 9
2028 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field. */
2029 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_MSB 9
2030 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field. */
2031 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_WIDTH 1
2032 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field value. */
2033 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_SET_MSK 0x00000200
2034 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field value. */
2035 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_CLR_MSK 0xfffffdff
2036 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field. */
2037 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_RESET 0x0
2038 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF field value from a register. */
2039 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_GET(value) (((value) & 0x00000200) >> 9)
2040 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field value suitable for setting the register. */
2041 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_SET(value) (((value) << 9) & 0x00000200)
2042 
2043 /*
2044  * Field : hpf
2045  *
2046  * Hash or Perfect Filter
2047  *
2048  * When this bit is set, it configures the address filter to pass a frame if it
2049  * matches either the perfect filtering or the hash filtering as set by the HMC or
2050  * HUC bits.
2051  *
2052  * When this bit is low and the HUC or HMC bit is set, the frame is passed only if
2053  * it matches the Hash filter. This bit is reserved (and RO) if the Hash filter is
2054  * not selected during core configuration.
2055  *
2056  * Field Enumeration Values:
2057  *
2058  * Enum | Value | Description
2059  * :-------------------------------------|:------|:------------
2060  * ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_E_DISD | 0x0 |
2061  * ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_E_END | 0x1 |
2062  *
2063  * Field Access Macros:
2064  *
2065  */
2066 /*
2067  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HPF
2068  *
2069  */
2070 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_E_DISD 0x0
2071 /*
2072  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HPF
2073  *
2074  */
2075 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_E_END 0x1
2076 
2077 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field. */
2078 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_LSB 10
2079 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field. */
2080 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_MSB 10
2081 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field. */
2082 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_WIDTH 1
2083 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field value. */
2084 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_SET_MSK 0x00000400
2085 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field value. */
2086 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_CLR_MSK 0xfffffbff
2087 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field. */
2088 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_RESET 0x0
2089 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF field value from a register. */
2090 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_GET(value) (((value) & 0x00000400) >> 10)
2091 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field value suitable for setting the register. */
2092 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_SET(value) (((value) << 10) & 0x00000400)
2093 
2094 /*
2095  * Field : reserved_15_11
2096  *
2097  * Reserved
2098  *
2099  * Field Access Macros:
2100  *
2101  */
2102 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11 register field. */
2103 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_LSB 11
2104 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11 register field. */
2105 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_MSB 15
2106 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11 register field. */
2107 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_WIDTH 5
2108 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11 register field value. */
2109 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_SET_MSK 0x0000f800
2110 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11 register field value. */
2111 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_CLR_MSK 0xffff07ff
2112 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11 register field. */
2113 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_RESET 0x0
2114 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11 field value from a register. */
2115 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_GET(value) (((value) & 0x0000f800) >> 11)
2116 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11 register field value suitable for setting the register. */
2117 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_SET(value) (((value) << 11) & 0x0000f800)
2118 
2119 /*
2120  * Field : vtfe
2121  *
2122  * VLAN Tag Filter Enable
2123  *
2124  * When set, this bit enables the MAC to drop VLAN tagged frames that do not match
2125  * the VLAN Tag comparison.
2126  *
2127  * When reset, the MAC forwards all frames irrespective of the match status of the
2128  * VLAN Tag.
2129  *
2130  * Field Enumeration Values:
2131  *
2132  * Enum | Value | Description
2133  * :----------------------------------------|:------|:------------
2134  * ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_E_NODROP | 0x0 |
2135  * ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_E_DROP | 0x1 |
2136  *
2137  * Field Access Macros:
2138  *
2139  */
2140 /*
2141  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE
2142  *
2143  */
2144 #define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_E_NODROP 0x0
2145 /*
2146  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE
2147  *
2148  */
2149 #define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_E_DROP 0x1
2150 
2151 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field. */
2152 #define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_LSB 16
2153 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field. */
2154 #define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_MSB 16
2155 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field. */
2156 #define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_WIDTH 1
2157 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field value. */
2158 #define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_SET_MSK 0x00010000
2159 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field value. */
2160 #define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_CLR_MSK 0xfffeffff
2161 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field. */
2162 #define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_RESET 0x0
2163 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE field value from a register. */
2164 #define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_GET(value) (((value) & 0x00010000) >> 16)
2165 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field value suitable for setting the register. */
2166 #define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_SET(value) (((value) << 16) & 0x00010000)
2167 
2168 /*
2169  * Field : reserved_19_17
2170  *
2171  * Reserved
2172  *
2173  * Field Access Macros:
2174  *
2175  */
2176 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17 register field. */
2177 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_LSB 17
2178 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17 register field. */
2179 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_MSB 19
2180 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17 register field. */
2181 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_WIDTH 3
2182 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17 register field value. */
2183 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_SET_MSK 0x000e0000
2184 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17 register field value. */
2185 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_CLR_MSK 0xfff1ffff
2186 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17 register field. */
2187 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_RESET 0x0
2188 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17 field value from a register. */
2189 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_GET(value) (((value) & 0x000e0000) >> 17)
2190 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17 register field value suitable for setting the register. */
2191 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_SET(value) (((value) << 17) & 0x000e0000)
2192 
2193 /*
2194  * Field : ipfe
2195  *
2196  * Layer 3 and Layer 4 Filter Enable
2197  *
2198  * When set, this bit enables the MAC to drop frames that do not match the enabled
2199  * Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for
2200  * matching, this bit does not have any effect.
2201  *
2202  * When reset, the MAC forwards all frames irrespective of the match status of the
2203  * Layer 3 and Layer 4 fields.
2204  *
2205  * If the Layer 3 and Layer 4 Filtering feature is not selected during core
2206  * configuration, this bit is reserved (RO with default value).
2207  *
2208  * Field Enumeration Values:
2209  *
2210  * Enum | Value | Description
2211  * :----------------------------------------|:------|:------------
2212  * ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_E_NODROP | 0x0 |
2213  * ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_E_DROP | 0x1 |
2214  *
2215  * Field Access Macros:
2216  *
2217  */
2218 /*
2219  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE
2220  *
2221  */
2222 #define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_E_NODROP 0x0
2223 /*
2224  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE
2225  *
2226  */
2227 #define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_E_DROP 0x1
2228 
2229 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field. */
2230 #define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_LSB 20
2231 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field. */
2232 #define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_MSB 20
2233 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field. */
2234 #define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_WIDTH 1
2235 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field value. */
2236 #define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_SET_MSK 0x00100000
2237 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field value. */
2238 #define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_CLR_MSK 0xffefffff
2239 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field. */
2240 #define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_RESET 0x0
2241 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE field value from a register. */
2242 #define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_GET(value) (((value) & 0x00100000) >> 20)
2243 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field value suitable for setting the register. */
2244 #define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_SET(value) (((value) << 20) & 0x00100000)
2245 
2246 /*
2247  * Field : dntu
2248  *
2249  * Drop non-TCP/UDP over IP Frames
2250  *
2251  * When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames.
2252  * The MAC forward only those frames that are processed by the Layer 4 filter.
2253  *
2254  * When reset, this bit enables the MAC to forward all non-TCP or UDP over IP
2255  * frames.
2256  *
2257  * If the Layer 3 and Layer 4 Filtering feature is not selected during core
2258  * configuration, this bit is reserved (RO with default value).
2259  *
2260  * Field Enumeration Values:
2261  *
2262  * Enum | Value | Description
2263  * :----------------------------------------|:------|:------------
2264  * ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_E_NODROP | 0x0 |
2265  * ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_E_DROP | 0x1 |
2266  *
2267  * Field Access Macros:
2268  *
2269  */
2270 /*
2271  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU
2272  *
2273  */
2274 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_E_NODROP 0x0
2275 /*
2276  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU
2277  *
2278  */
2279 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_E_DROP 0x1
2280 
2281 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field. */
2282 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_LSB 21
2283 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field. */
2284 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_MSB 21
2285 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field. */
2286 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_WIDTH 1
2287 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field value. */
2288 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_SET_MSK 0x00200000
2289 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field value. */
2290 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_CLR_MSK 0xffdfffff
2291 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field. */
2292 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_RESET 0x0
2293 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU field value from a register. */
2294 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_GET(value) (((value) & 0x00200000) >> 21)
2295 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field value suitable for setting the register. */
2296 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_SET(value) (((value) << 21) & 0x00200000)
2297 
2298 /*
2299  * Field : reserved_30_22
2300  *
2301  * Reserved
2302  *
2303  * Field Access Macros:
2304  *
2305  */
2306 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22 register field. */
2307 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_LSB 22
2308 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22 register field. */
2309 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_MSB 30
2310 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22 register field. */
2311 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_WIDTH 9
2312 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22 register field value. */
2313 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_SET_MSK 0x7fc00000
2314 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22 register field value. */
2315 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_CLR_MSK 0x803fffff
2316 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22 register field. */
2317 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_RESET 0x0
2318 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22 field value from a register. */
2319 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_GET(value) (((value) & 0x7fc00000) >> 22)
2320 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22 register field value suitable for setting the register. */
2321 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_SET(value) (((value) << 22) & 0x7fc00000)
2322 
2323 /*
2324  * Field : ra
2325  *
2326  * Receive All
2327  *
2328  * When this bit is set, the MAC Receiver module passes all received frames,
2329  * irrespective of whether they pass the address filter or not, to the Application.
2330  * The result of the SA or DA filtering is updated (pass or fail) in the
2331  * corresponding bits in the Receive Status Word.
2332  *
2333  * When this bit is reset, the Receiver module passes only those frames to the
2334  * Application that pass the SA or DA address filter.
2335  *
2336  * Field Enumeration Values:
2337  *
2338  * Enum | Value | Description
2339  * :------------------------------------|:------|:------------
2340  * ALT_EMAC_GMAC_MAC_FRM_FLT_RA_E_DISD | 0x0 |
2341  * ALT_EMAC_GMAC_MAC_FRM_FLT_RA_E_END | 0x1 |
2342  *
2343  * Field Access Macros:
2344  *
2345  */
2346 /*
2347  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_RA
2348  *
2349  */
2350 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_E_DISD 0x0
2351 /*
2352  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_RA
2353  *
2354  */
2355 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_E_END 0x1
2356 
2357 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field. */
2358 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_LSB 31
2359 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field. */
2360 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_MSB 31
2361 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field. */
2362 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_WIDTH 1
2363 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field value. */
2364 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_SET_MSK 0x80000000
2365 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field value. */
2366 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_CLR_MSK 0x7fffffff
2367 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field. */
2368 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_RESET 0x0
2369 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_RA field value from a register. */
2370 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_GET(value) (((value) & 0x80000000) >> 31)
2371 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field value suitable for setting the register. */
2372 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_SET(value) (((value) << 31) & 0x80000000)
2373 
2374 #ifndef __ASSEMBLY__
2375 /*
2376  * WARNING: The C register and register group struct declarations are provided for
2377  * convenience and illustrative purposes. They should, however, be used with
2378  * caution as the C language standard provides no guarantees about the alignment or
2379  * atomicity of device memory accesses. The recommended practice for writing
2380  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2381  * alt_write_word() functions.
2382  *
2383  * The struct declaration for register ALT_EMAC_GMAC_MAC_FRM_FLT.
2384  */
2385 struct ALT_EMAC_GMAC_MAC_FRM_FLT_s
2386 {
2387  uint32_t pr : 1; /* ALT_EMAC_GMAC_MAC_FRM_FLT_PR */
2388  const uint32_t huc : 1; /* ALT_EMAC_GMAC_MAC_FRM_FLT_HUC */
2389  const uint32_t hmc : 1; /* ALT_EMAC_GMAC_MAC_FRM_FLT_HMC */
2390  uint32_t daif : 1; /* ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF */
2391  uint32_t pm : 1; /* ALT_EMAC_GMAC_MAC_FRM_FLT_PM */
2392  uint32_t dbf : 1; /* ALT_EMAC_GMAC_MAC_FRM_FLT_DBF */
2393  uint32_t pcf : 2; /* ALT_EMAC_GMAC_MAC_FRM_FLT_PCF */
2394  uint32_t saif : 1; /* ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF */
2395  uint32_t saf : 1; /* ALT_EMAC_GMAC_MAC_FRM_FLT_SAF */
2396  const uint32_t hpf : 1; /* ALT_EMAC_GMAC_MAC_FRM_FLT_HPF */
2397  const uint32_t reserved_15_11 : 5; /* ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11 */
2398  uint32_t vtfe : 1; /* ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE */
2399  const uint32_t reserved_19_17 : 3; /* ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17 */
2400  uint32_t ipfe : 1; /* ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE */
2401  uint32_t dntu : 1; /* ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU */
2402  const uint32_t reserved_30_22 : 9; /* ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22 */
2403  uint32_t ra : 1; /* ALT_EMAC_GMAC_MAC_FRM_FLT_RA */
2404 };
2405 
2406 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_FRM_FLT. */
2407 typedef volatile struct ALT_EMAC_GMAC_MAC_FRM_FLT_s ALT_EMAC_GMAC_MAC_FRM_FLT_t;
2408 #endif /* __ASSEMBLY__ */
2409 
2410 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT register. */
2411 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RESET 0x00000000
2412 /* The byte offset of the ALT_EMAC_GMAC_MAC_FRM_FLT register from the beginning of the component. */
2413 #define ALT_EMAC_GMAC_MAC_FRM_FLT_OFST 0x4
2414 /* The address of the ALT_EMAC_GMAC_MAC_FRM_FLT register. */
2415 #define ALT_EMAC_GMAC_MAC_FRM_FLT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_FRM_FLT_OFST))
2416 
2417 /*
2418  * Register : gmacgrp_gmii_address
2419  *
2420  * <b> Register 4 (GMII Address Register) </b>
2421  *
2422  * The GMII Address register controls the management cycles to the external PHY
2423  * through the management interface.
2424  *
2425  * Note: This register is present for all PHY interface when you select the Station
2426  * Management (MDIO) feature in coreConsultant.
2427  *
2428  * Register Layout
2429  *
2430  * Bits | Access | Reset | Description
2431  * :--------|:-------|:------|:-----------------------------------
2432  * [0] | RW | 0x0 | ALT_EMAC_GMAC_GMII_ADDR_GB
2433  * [1] | RW | 0x0 | ALT_EMAC_GMAC_GMII_ADDR_GW
2434  * [5:2] | RW | 0x0 | ALT_EMAC_GMAC_GMII_ADDR_CR
2435  * [10:6] | RW | 0x0 | ALT_EMAC_GMAC_GMII_ADDR_GR
2436  * [15:11] | RW | 0x0 | ALT_EMAC_GMAC_GMII_ADDR_PA
2437  * [31:16] | R | 0x0 | ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16
2438  *
2439  */
2440 /*
2441  * Field : gb
2442  *
2443  * GMII Busy
2444  *
2445  * This bit should read logic 0 before writing to Register 4 and Register 5. During
2446  * a PHY or RevMII register access, the software sets this bit to 1'b1 to indicate
2447  * that a Read or Write access is in progress.
2448  *
2449  * Register 5 is invalid until this bit is cleared by the MAC. Therefore, Register
2450  * 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY
2451  * Write operation. Similarly for a read operation, the contents of Register 5 are
2452  * not valid until this bit is cleared.
2453  *
2454  * The subsequent read or write operation should happen only after the previous
2455  * operation is complete. Because there is no acknowledgment from the PHY to MAC
2456  * after a read or write operation is completed, there is no change in the
2457  * functionality of this bit even when the PHY is not present.
2458  *
2459  * Field Enumeration Values:
2460  *
2461  * Enum | Value | Description
2462  * :----------------------------------|:------|:------------
2463  * ALT_EMAC_GMAC_GMII_ADDR_GB_E_DISD | 0x0 |
2464  * ALT_EMAC_GMAC_GMII_ADDR_GB_E_END | 0x1 |
2465  *
2466  * Field Access Macros:
2467  *
2468  */
2469 /*
2470  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_GB
2471  *
2472  */
2473 #define ALT_EMAC_GMAC_GMII_ADDR_GB_E_DISD 0x0
2474 /*
2475  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_GB
2476  *
2477  */
2478 #define ALT_EMAC_GMAC_GMII_ADDR_GB_E_END 0x1
2479 
2480 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GB register field. */
2481 #define ALT_EMAC_GMAC_GMII_ADDR_GB_LSB 0
2482 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GB register field. */
2483 #define ALT_EMAC_GMAC_GMII_ADDR_GB_MSB 0
2484 /* The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_GB register field. */
2485 #define ALT_EMAC_GMAC_GMII_ADDR_GB_WIDTH 1
2486 /* The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_GB register field value. */
2487 #define ALT_EMAC_GMAC_GMII_ADDR_GB_SET_MSK 0x00000001
2488 /* The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_GB register field value. */
2489 #define ALT_EMAC_GMAC_GMII_ADDR_GB_CLR_MSK 0xfffffffe
2490 /* The reset value of the ALT_EMAC_GMAC_GMII_ADDR_GB register field. */
2491 #define ALT_EMAC_GMAC_GMII_ADDR_GB_RESET 0x0
2492 /* Extracts the ALT_EMAC_GMAC_GMII_ADDR_GB field value from a register. */
2493 #define ALT_EMAC_GMAC_GMII_ADDR_GB_GET(value) (((value) & 0x00000001) >> 0)
2494 /* Produces a ALT_EMAC_GMAC_GMII_ADDR_GB register field value suitable for setting the register. */
2495 #define ALT_EMAC_GMAC_GMII_ADDR_GB_SET(value) (((value) << 0) & 0x00000001)
2496 
2497 /*
2498  * Field : gw
2499  *
2500  * GMII Write
2501  *
2502  * When set, this bit indicates to the PHY or RevMII that this is a Write operation
2503  * using the GMII Data register. If this bit is not set, it indicates that this is
2504  * a Read operation, that is, placing the data in the GMII Data register.
2505  *
2506  * Field Enumeration Values:
2507  *
2508  * Enum | Value | Description
2509  * :----------------------------------|:------|:------------
2510  * ALT_EMAC_GMAC_GMII_ADDR_GW_E_DISD | 0x0 |
2511  * ALT_EMAC_GMAC_GMII_ADDR_GW_E_END | 0x1 |
2512  *
2513  * Field Access Macros:
2514  *
2515  */
2516 /*
2517  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_GW
2518  *
2519  */
2520 #define ALT_EMAC_GMAC_GMII_ADDR_GW_E_DISD 0x0
2521 /*
2522  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_GW
2523  *
2524  */
2525 #define ALT_EMAC_GMAC_GMII_ADDR_GW_E_END 0x1
2526 
2527 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GW register field. */
2528 #define ALT_EMAC_GMAC_GMII_ADDR_GW_LSB 1
2529 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GW register field. */
2530 #define ALT_EMAC_GMAC_GMII_ADDR_GW_MSB 1
2531 /* The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_GW register field. */
2532 #define ALT_EMAC_GMAC_GMII_ADDR_GW_WIDTH 1
2533 /* The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_GW register field value. */
2534 #define ALT_EMAC_GMAC_GMII_ADDR_GW_SET_MSK 0x00000002
2535 /* The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_GW register field value. */
2536 #define ALT_EMAC_GMAC_GMII_ADDR_GW_CLR_MSK 0xfffffffd
2537 /* The reset value of the ALT_EMAC_GMAC_GMII_ADDR_GW register field. */
2538 #define ALT_EMAC_GMAC_GMII_ADDR_GW_RESET 0x0
2539 /* Extracts the ALT_EMAC_GMAC_GMII_ADDR_GW field value from a register. */
2540 #define ALT_EMAC_GMAC_GMII_ADDR_GW_GET(value) (((value) & 0x00000002) >> 1)
2541 /* Produces a ALT_EMAC_GMAC_GMII_ADDR_GW register field value suitable for setting the register. */
2542 #define ALT_EMAC_GMAC_GMII_ADDR_GW_SET(value) (((value) << 1) & 0x00000002)
2543 
2544 /*
2545  * Field : cr
2546  *
2547  * CSR Clock Range
2548  *
2549  * The CSR Clock Range selection determines the frequency of the MDC clock
2550  * according to the CSR clock frequency used in your design.
2551  *
2552  * The suggested range of CSR clock frequency applicable for each value (when
2553  * Bit[5] = 0) ensures that the MDC clock is approximately between the frequency
2554  * range 1.0 MHz - 2.5 MHz.
2555  *
2556  * * 0000: The frequency of the CSR clock is 60-100 MHz and the MDC clock is CSR
2557  * clock/42.
2558  *
2559  * * 0001: The frequency of the CSR clock is 100-150 MHz and the MDC clock is CSR
2560  * clock/62.
2561  *
2562  * * 0010: The frequency of the CSR clock is 20-35 MHz and the MDC clock is CSR
2563  * clock/16.
2564  *
2565  * * 0011: The frequency of the CSR clock is 35-60 MHz and the MDC clock is CSR
2566  * clock/26.
2567  *
2568  * * 0100: The frequency of the CSR clock is 150-250 MHz and the MDC clock is CSR
2569  * clock/102.
2570  *
2571  * * 0100: The frequency of the CSR clock is 250-300 MHz and the MDC clock is CSR
2572  * clock/124.
2573  *
2574  * * 0110 and 0111: Reserved
2575  *
2576  * When Bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE
2577  * 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower
2578  * value. For example, when CSR clock is of 100 MHz frequency and you program these
2579  * bits as 1010, then the resultant MDC clock is of 12.5 MHz which is outside the
2580  * limit of IEEE 802.3 specified range.
2581  *
2582  * Program the following values only if the interfacing chips support faster MDC
2583  * clocks:
2584  *
2585  * * 1000: CSR clock/4
2586  *
2587  * * 1001: CSR clock/6
2588  *
2589  * * 1010: CSR clock/8
2590  *
2591  * * 1011: CSR clock/10
2592  *
2593  * * 1100: CSR clock/12
2594  *
2595  * * 1101: CSR clock/14
2596  *
2597  * * 1110: CSR clock/16
2598  *
2599  * * 1111: CSR clock/18
2600  *
2601  * These bits are not used for accessing RevMII. These bits are read-only if the
2602  * RevMII interface is selected as single PHY interface.
2603  *
2604  * Field Enumeration Values:
2605  *
2606  * Enum | Value | Description
2607  * :----------------------------------------|:------|:------------
2608  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV42 | 0x0 |
2609  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV62 | 0x1 |
2610  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV16 | 0x2 |
2611  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV26 | 0x3 |
2612  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV102 | 0x4 |
2613  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV124 | 0x5 |
2614  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV4 | 0x8 |
2615  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV6 | 0x9 |
2616  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV8 | 0xa |
2617  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV10 | 0xb |
2618  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV12 | 0xc |
2619  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV14 | 0xd |
2620  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV16AGAIN | 0xe |
2621  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV18 | 0xf |
2622  *
2623  * Field Access Macros:
2624  *
2625  */
2626 /*
2627  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2628  *
2629  */
2630 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV42 0x0
2631 /*
2632  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2633  *
2634  */
2635 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV62 0x1
2636 /*
2637  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2638  *
2639  */
2640 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV16 0x2
2641 /*
2642  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2643  *
2644  */
2645 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV26 0x3
2646 /*
2647  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2648  *
2649  */
2650 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV102 0x4
2651 /*
2652  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2653  *
2654  */
2655 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV124 0x5
2656 /*
2657  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2658  *
2659  */
2660 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV4 0x8
2661 /*
2662  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2663  *
2664  */
2665 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV6 0x9
2666 /*
2667  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2668  *
2669  */
2670 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV8 0xa
2671 /*
2672  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2673  *
2674  */
2675 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV10 0xb
2676 /*
2677  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2678  *
2679  */
2680 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV12 0xc
2681 /*
2682  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2683  *
2684  */
2685 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV14 0xd
2686 /*
2687  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2688  *
2689  */
2690 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV16AGAIN 0xe
2691 /*
2692  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2693  *
2694  */
2695 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV18 0xf
2696 
2697 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_CR register field. */
2698 #define ALT_EMAC_GMAC_GMII_ADDR_CR_LSB 2
2699 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_CR register field. */
2700 #define ALT_EMAC_GMAC_GMII_ADDR_CR_MSB 5
2701 /* The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_CR register field. */
2702 #define ALT_EMAC_GMAC_GMII_ADDR_CR_WIDTH 4
2703 /* The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_CR register field value. */
2704 #define ALT_EMAC_GMAC_GMII_ADDR_CR_SET_MSK 0x0000003c
2705 /* The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_CR register field value. */
2706 #define ALT_EMAC_GMAC_GMII_ADDR_CR_CLR_MSK 0xffffffc3
2707 /* The reset value of the ALT_EMAC_GMAC_GMII_ADDR_CR register field. */
2708 #define ALT_EMAC_GMAC_GMII_ADDR_CR_RESET 0x0
2709 /* Extracts the ALT_EMAC_GMAC_GMII_ADDR_CR field value from a register. */
2710 #define ALT_EMAC_GMAC_GMII_ADDR_CR_GET(value) (((value) & 0x0000003c) >> 2)
2711 /* Produces a ALT_EMAC_GMAC_GMII_ADDR_CR register field value suitable for setting the register. */
2712 #define ALT_EMAC_GMAC_GMII_ADDR_CR_SET(value) (((value) << 2) & 0x0000003c)
2713 
2714 /*
2715  * Field : gr
2716  *
2717  * GMII Register
2718  *
2719  * These bits select the desired GMII register in the selected PHY device.
2720  *
2721  * For RevMII, these bits select the desired CSR register in the RevMII Registers
2722  * set.
2723  *
2724  * Field Access Macros:
2725  *
2726  */
2727 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GR register field. */
2728 #define ALT_EMAC_GMAC_GMII_ADDR_GR_LSB 6
2729 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GR register field. */
2730 #define ALT_EMAC_GMAC_GMII_ADDR_GR_MSB 10
2731 /* The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_GR register field. */
2732 #define ALT_EMAC_GMAC_GMII_ADDR_GR_WIDTH 5
2733 /* The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_GR register field value. */
2734 #define ALT_EMAC_GMAC_GMII_ADDR_GR_SET_MSK 0x000007c0
2735 /* The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_GR register field value. */
2736 #define ALT_EMAC_GMAC_GMII_ADDR_GR_CLR_MSK 0xfffff83f
2737 /* The reset value of the ALT_EMAC_GMAC_GMII_ADDR_GR register field. */
2738 #define ALT_EMAC_GMAC_GMII_ADDR_GR_RESET 0x0
2739 /* Extracts the ALT_EMAC_GMAC_GMII_ADDR_GR field value from a register. */
2740 #define ALT_EMAC_GMAC_GMII_ADDR_GR_GET(value) (((value) & 0x000007c0) >> 6)
2741 /* Produces a ALT_EMAC_GMAC_GMII_ADDR_GR register field value suitable for setting the register. */
2742 #define ALT_EMAC_GMAC_GMII_ADDR_GR_SET(value) (((value) << 6) & 0x000007c0)
2743 
2744 /*
2745  * Field : pa
2746  *
2747  * Physical Layer Address
2748  *
2749  * This field indicates which of the 32 possible PHY devices are being accessed.
2750  *
2751  * For RevMII, this field gives the PHY Address of the RevMII module.
2752  *
2753  * Field Access Macros:
2754  *
2755  */
2756 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_PA register field. */
2757 #define ALT_EMAC_GMAC_GMII_ADDR_PA_LSB 11
2758 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_PA register field. */
2759 #define ALT_EMAC_GMAC_GMII_ADDR_PA_MSB 15
2760 /* The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_PA register field. */
2761 #define ALT_EMAC_GMAC_GMII_ADDR_PA_WIDTH 5
2762 /* The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_PA register field value. */
2763 #define ALT_EMAC_GMAC_GMII_ADDR_PA_SET_MSK 0x0000f800
2764 /* The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_PA register field value. */
2765 #define ALT_EMAC_GMAC_GMII_ADDR_PA_CLR_MSK 0xffff07ff
2766 /* The reset value of the ALT_EMAC_GMAC_GMII_ADDR_PA register field. */
2767 #define ALT_EMAC_GMAC_GMII_ADDR_PA_RESET 0x0
2768 /* Extracts the ALT_EMAC_GMAC_GMII_ADDR_PA field value from a register. */
2769 #define ALT_EMAC_GMAC_GMII_ADDR_PA_GET(value) (((value) & 0x0000f800) >> 11)
2770 /* Produces a ALT_EMAC_GMAC_GMII_ADDR_PA register field value suitable for setting the register. */
2771 #define ALT_EMAC_GMAC_GMII_ADDR_PA_SET(value) (((value) << 11) & 0x0000f800)
2772 
2773 /*
2774  * Field : reserved_31_16
2775  *
2776  * Reserved
2777  *
2778  * Field Access Macros:
2779  *
2780  */
2781 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16 register field. */
2782 #define ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_LSB 16
2783 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16 register field. */
2784 #define ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_MSB 31
2785 /* The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16 register field. */
2786 #define ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_WIDTH 16
2787 /* The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16 register field value. */
2788 #define ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_SET_MSK 0xffff0000
2789 /* The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16 register field value. */
2790 #define ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_CLR_MSK 0x0000ffff
2791 /* The reset value of the ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16 register field. */
2792 #define ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_RESET 0x0
2793 /* Extracts the ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16 field value from a register. */
2794 #define ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_GET(value) (((value) & 0xffff0000) >> 16)
2795 /* Produces a ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16 register field value suitable for setting the register. */
2796 #define ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_SET(value) (((value) << 16) & 0xffff0000)
2797 
2798 #ifndef __ASSEMBLY__
2799 /*
2800  * WARNING: The C register and register group struct declarations are provided for
2801  * convenience and illustrative purposes. They should, however, be used with
2802  * caution as the C language standard provides no guarantees about the alignment or
2803  * atomicity of device memory accesses. The recommended practice for writing
2804  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2805  * alt_write_word() functions.
2806  *
2807  * The struct declaration for register ALT_EMAC_GMAC_GMII_ADDR.
2808  */
2809 struct ALT_EMAC_GMAC_GMII_ADDR_s
2810 {
2811  uint32_t gb : 1; /* ALT_EMAC_GMAC_GMII_ADDR_GB */
2812  uint32_t gw : 1; /* ALT_EMAC_GMAC_GMII_ADDR_GW */
2813  uint32_t cr : 4; /* ALT_EMAC_GMAC_GMII_ADDR_CR */
2814  uint32_t gr : 5; /* ALT_EMAC_GMAC_GMII_ADDR_GR */
2815  uint32_t pa : 5; /* ALT_EMAC_GMAC_GMII_ADDR_PA */
2816  const uint32_t reserved_31_16 : 16; /* ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16 */
2817 };
2818 
2819 /* The typedef declaration for register ALT_EMAC_GMAC_GMII_ADDR. */
2820 typedef volatile struct ALT_EMAC_GMAC_GMII_ADDR_s ALT_EMAC_GMAC_GMII_ADDR_t;
2821 #endif /* __ASSEMBLY__ */
2822 
2823 /* The reset value of the ALT_EMAC_GMAC_GMII_ADDR register. */
2824 #define ALT_EMAC_GMAC_GMII_ADDR_RESET 0x00000000
2825 /* The byte offset of the ALT_EMAC_GMAC_GMII_ADDR register from the beginning of the component. */
2826 #define ALT_EMAC_GMAC_GMII_ADDR_OFST 0x10
2827 /* The address of the ALT_EMAC_GMAC_GMII_ADDR register. */
2828 #define ALT_EMAC_GMAC_GMII_ADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_GMII_ADDR_OFST))
2829 
2830 /*
2831  * Register : gmacgrp_gmii_data
2832  *
2833  * <b> Register 5 (GMII Data Register) </b>
2834  *
2835  * The GMII Data register stores Write data to be written to the PHY register
2836  * located at the address specified in Register 4 (GMII Address Register). This
2837  * register also stores the Read data from the PHY register located at the address
2838  * specified by Register 4.
2839  *
2840  * Note: This register is present for all PHY interface when you select the Station
2841  * Management (MDIO) feature in coreConsultant.
2842  *
2843  * Register Layout
2844  *
2845  * Bits | Access | Reset | Description
2846  * :--------|:-------|:------|:-----------------------------------
2847  * [15:0] | RW | 0x0 | ALT_EMAC_GMAC_GMII_DATA_GD
2848  * [31:16] | R | 0x0 | ALT_EMAC_GMAC_GMII_DATA_RSVD_31_16
2849  *
2850  */
2851 /*
2852  * Field : gd
2853  *
2854  * GMII Data
2855  *
2856  * This field contains the 16-bit data value read from the PHY or RevMII after a
2857  * Management Read operation or the 16-bit data value to be written to the PHY or
2858  * RevMII before a Management Write operation.
2859  *
2860  * Field Access Macros:
2861  *
2862  */
2863 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_DATA_GD register field. */
2864 #define ALT_EMAC_GMAC_GMII_DATA_GD_LSB 0
2865 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_DATA_GD register field. */
2866 #define ALT_EMAC_GMAC_GMII_DATA_GD_MSB 15
2867 /* The width in bits of the ALT_EMAC_GMAC_GMII_DATA_GD register field. */
2868 #define ALT_EMAC_GMAC_GMII_DATA_GD_WIDTH 16
2869 /* The mask used to set the ALT_EMAC_GMAC_GMII_DATA_GD register field value. */
2870 #define ALT_EMAC_GMAC_GMII_DATA_GD_SET_MSK 0x0000ffff
2871 /* The mask used to clear the ALT_EMAC_GMAC_GMII_DATA_GD register field value. */
2872 #define ALT_EMAC_GMAC_GMII_DATA_GD_CLR_MSK 0xffff0000
2873 /* The reset value of the ALT_EMAC_GMAC_GMII_DATA_GD register field. */
2874 #define ALT_EMAC_GMAC_GMII_DATA_GD_RESET 0x0
2875 /* Extracts the ALT_EMAC_GMAC_GMII_DATA_GD field value from a register. */
2876 #define ALT_EMAC_GMAC_GMII_DATA_GD_GET(value) (((value) & 0x0000ffff) >> 0)
2877 /* Produces a ALT_EMAC_GMAC_GMII_DATA_GD register field value suitable for setting the register. */
2878 #define ALT_EMAC_GMAC_GMII_DATA_GD_SET(value) (((value) << 0) & 0x0000ffff)
2879 
2880 /*
2881  * Field : reserved_31_16
2882  *
2883  * Reserved
2884  *
2885  * Field Access Macros:
2886  *
2887  */
2888 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_DATA_RSVD_31_16 register field. */
2889 #define ALT_EMAC_GMAC_GMII_DATA_RSVD_31_16_LSB 16
2890 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_DATA_RSVD_31_16 register field. */
2891 #define ALT_EMAC_GMAC_GMII_DATA_RSVD_31_16_MSB 31
2892 /* The width in bits of the ALT_EMAC_GMAC_GMII_DATA_RSVD_31_16 register field. */
2893 #define ALT_EMAC_GMAC_GMII_DATA_RSVD_31_16_WIDTH 16
2894 /* The mask used to set the ALT_EMAC_GMAC_GMII_DATA_RSVD_31_16 register field value. */
2895 #define ALT_EMAC_GMAC_GMII_DATA_RSVD_31_16_SET_MSK 0xffff0000
2896 /* The mask used to clear the ALT_EMAC_GMAC_GMII_DATA_RSVD_31_16 register field value. */
2897 #define ALT_EMAC_GMAC_GMII_DATA_RSVD_31_16_CLR_MSK 0x0000ffff
2898 /* The reset value of the ALT_EMAC_GMAC_GMII_DATA_RSVD_31_16 register field. */
2899 #define ALT_EMAC_GMAC_GMII_DATA_RSVD_31_16_RESET 0x0
2900 /* Extracts the ALT_EMAC_GMAC_GMII_DATA_RSVD_31_16 field value from a register. */
2901 #define ALT_EMAC_GMAC_GMII_DATA_RSVD_31_16_GET(value) (((value) & 0xffff0000) >> 16)
2902 /* Produces a ALT_EMAC_GMAC_GMII_DATA_RSVD_31_16 register field value suitable for setting the register. */
2903 #define ALT_EMAC_GMAC_GMII_DATA_RSVD_31_16_SET(value) (((value) << 16) & 0xffff0000)
2904 
2905 #ifndef __ASSEMBLY__
2906 /*
2907  * WARNING: The C register and register group struct declarations are provided for
2908  * convenience and illustrative purposes. They should, however, be used with
2909  * caution as the C language standard provides no guarantees about the alignment or
2910  * atomicity of device memory accesses. The recommended practice for writing
2911  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2912  * alt_write_word() functions.
2913  *
2914  * The struct declaration for register ALT_EMAC_GMAC_GMII_DATA.
2915  */
2916 struct ALT_EMAC_GMAC_GMII_DATA_s
2917 {
2918  uint32_t gd : 16; /* ALT_EMAC_GMAC_GMII_DATA_GD */
2919  const uint32_t reserved_31_16 : 16; /* ALT_EMAC_GMAC_GMII_DATA_RSVD_31_16 */
2920 };
2921 
2922 /* The typedef declaration for register ALT_EMAC_GMAC_GMII_DATA. */
2923 typedef volatile struct ALT_EMAC_GMAC_GMII_DATA_s ALT_EMAC_GMAC_GMII_DATA_t;
2924 #endif /* __ASSEMBLY__ */
2925 
2926 /* The reset value of the ALT_EMAC_GMAC_GMII_DATA register. */
2927 #define ALT_EMAC_GMAC_GMII_DATA_RESET 0x00000000
2928 /* The byte offset of the ALT_EMAC_GMAC_GMII_DATA register from the beginning of the component. */
2929 #define ALT_EMAC_GMAC_GMII_DATA_OFST 0x14
2930 /* The address of the ALT_EMAC_GMAC_GMII_DATA register. */
2931 #define ALT_EMAC_GMAC_GMII_DATA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_GMII_DATA_OFST))
2932 
2933 /*
2934  * Register : gmacgrp_flow_control
2935  *
2936  * <b> Register 6 (Flow Control Register) </b>
2937  *
2938  * The Flow Control register controls the generation and reception of the Control
2939  * (Pause Command) frames by the MAC's Flow control module. A Write to a register
2940  * with the Busy bit set to '1' triggers the Flow Control block to generate a Pause
2941  * Control frame. The fields of the control frame are selected as specified in the
2942  * 802.3x specification, and the Pause Time value from this register is used in the
2943  * Pause Time field of the control frame. The Busy bit remains set until the
2944  * control frame is transferred onto the cable. The Host must make sure that the
2945  * Busy bit is cleared before writing to the register.
2946  *
2947  * Register Layout
2948  *
2949  * Bits | Access | Reset | Description
2950  * :--------|:-------|:------|:---------------------------------
2951  * [0] | RW | 0x0 | ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA
2952  * [1] | RW | 0x0 | ALT_EMAC_GMAC_FLOW_CTL_TFE
2953  * [2] | RW | 0x0 | ALT_EMAC_GMAC_FLOW_CTL_RFE
2954  * [3] | RW | 0x0 | ALT_EMAC_GMAC_FLOW_CTL_UP
2955  * [5:4] | RW | 0x0 | ALT_EMAC_GMAC_FLOW_CTL_PLT
2956  * [6] | R | 0x0 | ALT_EMAC_GMAC_FLOW_CTL_RSVD_6
2957  * [7] | RW | 0x0 | ALT_EMAC_GMAC_FLOW_CTL_DZPQ
2958  * [15:8] | R | 0x0 | ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8
2959  * [31:16] | RW | 0x0 | ALT_EMAC_GMAC_FLOW_CTL_PT
2960  *
2961  */
2962 /*
2963  * Field : fca_bpa
2964  *
2965  * Flow Control Busy or Backpressure Activate
2966  *
2967  * This bit initiates a Pause Control frame in the full-duplex mode and activates
2968  * the backpressure function in the half-duplex mode if the TFE bit is set.
2969  *
2970  * In the full-duplex mode, this bit should be read as 1'b0 before writing to the
2971  * Flow Control register. To initiate a Pause control frame, the Application must
2972  * set this bit to 1'b1. During a transfer of the Control Frame, this bit continues
2973  * to be set to signify that a frame transmission is in progress. After the
2974  * completion of Pause control frame transmission, the MAC resets this bit to 1'b0.
2975  * The Flow Control register should not be written to until this bit is cleared.
2976  *
2977  * In the half-duplex mode, when this bit is set (and TFE is set), then
2978  * backpressure is asserted by the MAC. During backpressure, when the MAC receives
2979  * a new frame, the transmitter starts sending a JAM pattern resulting in a
2980  * collision. This control register bit is logically ORed with the mti_flowctrl_i
2981  * input signal for the backpressure function. When the MAC is configured for the
2982  * full-duplex mode, the BPA is automatically disabled.
2983  *
2984  * Field Enumeration Values:
2985  *
2986  * Enum | Value | Description
2987  * :--------------------------------------|:------|:------------
2988  * ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_DISD | 0x0 |
2989  * ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_END | 0x1 |
2990  *
2991  * Field Access Macros:
2992  *
2993  */
2994 /*
2995  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA
2996  *
2997  */
2998 #define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_DISD 0x0
2999 /*
3000  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA
3001  *
3002  */
3003 #define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_END 0x1
3004 
3005 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field. */
3006 #define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_LSB 0
3007 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field. */
3008 #define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_MSB 0
3009 /* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field. */
3010 #define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_WIDTH 1
3011 /* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field value. */
3012 #define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_SET_MSK 0x00000001
3013 /* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field value. */
3014 #define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_CLR_MSK 0xfffffffe
3015 /* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field. */
3016 #define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_RESET 0x0
3017 /* Extracts the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA field value from a register. */
3018 #define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_GET(value) (((value) & 0x00000001) >> 0)
3019 /* Produces a ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field value suitable for setting the register. */
3020 #define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_SET(value) (((value) << 0) & 0x00000001)
3021 
3022 /*
3023  * Field : tfe
3024  *
3025  * Transmit Flow Control Enable
3026  *
3027  * In the full-duplex mode, when this bit is set, the MAC enables the flow control
3028  * operation to transmit Pause frames. When this bit is reset, the flow control
3029  * operation in the MAC is disabled, and the MAC does not transmit any Pause
3030  * frames.
3031  *
3032  * In half-duplex mode, when this bit is set, the MAC enables the back-pressure
3033  * operation. When this bit is reset, the back-pressure feature is disabled.
3034  *
3035  * Field Enumeration Values:
3036  *
3037  * Enum | Value | Description
3038  * :----------------------------------|:------|:------------
3039  * ALT_EMAC_GMAC_FLOW_CTL_TFE_E_DISD | 0x0 |
3040  * ALT_EMAC_GMAC_FLOW_CTL_TFE_E_END | 0x1 |
3041  *
3042  * Field Access Macros:
3043  *
3044  */
3045 /*
3046  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_TFE
3047  *
3048  */
3049 #define ALT_EMAC_GMAC_FLOW_CTL_TFE_E_DISD 0x0
3050 /*
3051  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_TFE
3052  *
3053  */
3054 #define ALT_EMAC_GMAC_FLOW_CTL_TFE_E_END 0x1
3055 
3056 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field. */
3057 #define ALT_EMAC_GMAC_FLOW_CTL_TFE_LSB 1
3058 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field. */
3059 #define ALT_EMAC_GMAC_FLOW_CTL_TFE_MSB 1
3060 /* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field. */
3061 #define ALT_EMAC_GMAC_FLOW_CTL_TFE_WIDTH 1
3062 /* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_TFE register field value. */
3063 #define ALT_EMAC_GMAC_FLOW_CTL_TFE_SET_MSK 0x00000002
3064 /* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_TFE register field value. */
3065 #define ALT_EMAC_GMAC_FLOW_CTL_TFE_CLR_MSK 0xfffffffd
3066 /* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field. */
3067 #define ALT_EMAC_GMAC_FLOW_CTL_TFE_RESET 0x0
3068 /* Extracts the ALT_EMAC_GMAC_FLOW_CTL_TFE field value from a register. */
3069 #define ALT_EMAC_GMAC_FLOW_CTL_TFE_GET(value) (((value) & 0x00000002) >> 1)
3070 /* Produces a ALT_EMAC_GMAC_FLOW_CTL_TFE register field value suitable for setting the register. */
3071 #define ALT_EMAC_GMAC_FLOW_CTL_TFE_SET(value) (((value) << 1) & 0x00000002)
3072 
3073 /*
3074  * Field : rfe
3075  *
3076  * Receive Flow Control Enable
3077  *
3078  * When this bit is set, the MAC decodes the received Pause frame and disables its
3079  * transmitter for a specified (Pause) time. When this bit is reset, the decode
3080  * function of the Pause frame is disabled.
3081  *
3082  * Field Enumeration Values:
3083  *
3084  * Enum | Value | Description
3085  * :----------------------------------|:------|:------------
3086  * ALT_EMAC_GMAC_FLOW_CTL_RFE_E_DISD | 0x0 |
3087  * ALT_EMAC_GMAC_FLOW_CTL_RFE_E_END | 0x1 |
3088  *
3089  * Field Access Macros:
3090  *
3091  */
3092 /*
3093  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_RFE
3094  *
3095  */
3096 #define ALT_EMAC_GMAC_FLOW_CTL_RFE_E_DISD 0x0
3097 /*
3098  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_RFE
3099  *
3100  */
3101 #define ALT_EMAC_GMAC_FLOW_CTL_RFE_E_END 0x1
3102 
3103 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field. */
3104 #define ALT_EMAC_GMAC_FLOW_CTL_RFE_LSB 2
3105 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field. */
3106 #define ALT_EMAC_GMAC_FLOW_CTL_RFE_MSB 2
3107 /* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field. */
3108 #define ALT_EMAC_GMAC_FLOW_CTL_RFE_WIDTH 1
3109 /* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_RFE register field value. */
3110 #define ALT_EMAC_GMAC_FLOW_CTL_RFE_SET_MSK 0x00000004
3111 /* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_RFE register field value. */
3112 #define ALT_EMAC_GMAC_FLOW_CTL_RFE_CLR_MSK 0xfffffffb
3113 /* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field. */
3114 #define ALT_EMAC_GMAC_FLOW_CTL_RFE_RESET 0x0
3115 /* Extracts the ALT_EMAC_GMAC_FLOW_CTL_RFE field value from a register. */
3116 #define ALT_EMAC_GMAC_FLOW_CTL_RFE_GET(value) (((value) & 0x00000004) >> 2)
3117 /* Produces a ALT_EMAC_GMAC_FLOW_CTL_RFE register field value suitable for setting the register. */
3118 #define ALT_EMAC_GMAC_FLOW_CTL_RFE_SET(value) (((value) << 2) & 0x00000004)
3119 
3120 /*
3121  * Field : up
3122  *
3123  * Unicast Pause Frame Detect
3124  *
3125  * A pause frame is processed when it has the unique multicast address specified in
3126  * the IEEE Std 802.3. When this bit is set, the MAC can also detect Pause frames
3127  * with unicast address of the station. This unicast address should be as specified
3128  * in the MAC Address0 High Register and MAC Address0 Low Register.
3129  *
3130  * When this bit is reset, the MAC only detects Pause frames with unique multicast
3131  * address.
3132  *
3133  * Note: The MAC does not process a Pause frame if the multicast address of
3134  * received frame is different from the unique multicast address.
3135  *
3136  * Field Enumeration Values:
3137  *
3138  * Enum | Value | Description
3139  * :---------------------------------|:------|:------------
3140  * ALT_EMAC_GMAC_FLOW_CTL_UP_E_DISD | 0x0 |
3141  * ALT_EMAC_GMAC_FLOW_CTL_UP_E_END | 0x1 |
3142  *
3143  * Field Access Macros:
3144  *
3145  */
3146 /*
3147  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_UP
3148  *
3149  */
3150 #define ALT_EMAC_GMAC_FLOW_CTL_UP_E_DISD 0x0
3151 /*
3152  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_UP
3153  *
3154  */
3155 #define ALT_EMAC_GMAC_FLOW_CTL_UP_E_END 0x1
3156 
3157 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_UP register field. */
3158 #define ALT_EMAC_GMAC_FLOW_CTL_UP_LSB 3
3159 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_UP register field. */
3160 #define ALT_EMAC_GMAC_FLOW_CTL_UP_MSB 3
3161 /* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_UP register field. */
3162 #define ALT_EMAC_GMAC_FLOW_CTL_UP_WIDTH 1
3163 /* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_UP register field value. */
3164 #define ALT_EMAC_GMAC_FLOW_CTL_UP_SET_MSK 0x00000008
3165 /* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_UP register field value. */
3166 #define ALT_EMAC_GMAC_FLOW_CTL_UP_CLR_MSK 0xfffffff7
3167 /* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_UP register field. */
3168 #define ALT_EMAC_GMAC_FLOW_CTL_UP_RESET 0x0
3169 /* Extracts the ALT_EMAC_GMAC_FLOW_CTL_UP field value from a register. */
3170 #define ALT_EMAC_GMAC_FLOW_CTL_UP_GET(value) (((value) & 0x00000008) >> 3)
3171 /* Produces a ALT_EMAC_GMAC_FLOW_CTL_UP register field value suitable for setting the register. */
3172 #define ALT_EMAC_GMAC_FLOW_CTL_UP_SET(value) (((value) << 3) & 0x00000008)
3173 
3174 /*
3175  * Field : plt
3176  *
3177  * Pause Low Threshold
3178  *
3179  * This field configures the threshold of the PAUSE timer at which the input flow
3180  * control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic
3181  * retransmission of PAUSE Frame.
3182  *
3183  * The threshold values should be always less than the Pause Time configured in
3184  * Bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, then a
3185  * second PAUSE frame is automatically transmitted if the mti_flowctrl_i signal is
3186  * asserted at 228 (256 - 28) slot times after the first PAUSE frame is
3187  * transmitted.
3188  *
3189  * The following list provides the threshold values for different values:
3190  *
3191  * * 00: The threshold is Pause time minus 4 slot times (PT - 4 slot times).
3192  *
3193  * * 01: The threshold is Pause time minus 28 slot times (PT - 28 slot times).
3194  *
3195  * * 10: The threshold is Pause time minus 144 slot times (PT - 144 slot times).
3196  *
3197  * * 11: The threshold is Pause time minus 256 slot times (PT - 256 slot times).
3198  *
3199  * The slot time is defined as the time taken to transmit 512 bits (64 bytes) on
3200  * the GMII or MII interface.
3201  *
3202  * Field Enumeration Values:
3203  *
3204  * Enum | Value | Description
3205  * :-------------------------------------------|:------|:------------
3206  * ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_4 | 0x0 |
3207  * ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_28 | 0x1 |
3208  * ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_144 | 0x2 |
3209  * ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_256 | 0x3 |
3210  *
3211  * Field Access Macros:
3212  *
3213  */
3214 /*
3215  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT
3216  *
3217  */
3218 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_4 0x0
3219 /*
3220  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT
3221  *
3222  */
3223 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_28 0x1
3224 /*
3225  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT
3226  *
3227  */
3228 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_144 0x2
3229 /*
3230  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT
3231  *
3232  */
3233 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_256 0x3
3234 
3235 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field. */
3236 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_LSB 4
3237 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field. */
3238 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_MSB 5
3239 /* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field. */
3240 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_WIDTH 2
3241 /* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_PLT register field value. */
3242 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_SET_MSK 0x00000030
3243 /* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_PLT register field value. */
3244 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_CLR_MSK 0xffffffcf
3245 /* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field. */
3246 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_RESET 0x0
3247 /* Extracts the ALT_EMAC_GMAC_FLOW_CTL_PLT field value from a register. */
3248 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_GET(value) (((value) & 0x00000030) >> 4)
3249 /* Produces a ALT_EMAC_GMAC_FLOW_CTL_PLT register field value suitable for setting the register. */
3250 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_SET(value) (((value) << 4) & 0x00000030)
3251 
3252 /*
3253  * Field : reserved_6
3254  *
3255  * Reserved
3256  *
3257  * Field Access Macros:
3258  *
3259  */
3260 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_RSVD_6 register field. */
3261 #define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_LSB 6
3262 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_RSVD_6 register field. */
3263 #define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_MSB 6
3264 /* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_RSVD_6 register field. */
3265 #define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_WIDTH 1
3266 /* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_RSVD_6 register field value. */
3267 #define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_SET_MSK 0x00000040
3268 /* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_RSVD_6 register field value. */
3269 #define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_CLR_MSK 0xffffffbf
3270 /* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_RSVD_6 register field. */
3271 #define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_RESET 0x0
3272 /* Extracts the ALT_EMAC_GMAC_FLOW_CTL_RSVD_6 field value from a register. */
3273 #define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_GET(value) (((value) & 0x00000040) >> 6)
3274 /* Produces a ALT_EMAC_GMAC_FLOW_CTL_RSVD_6 register field value suitable for setting the register. */
3275 #define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_SET(value) (((value) << 6) & 0x00000040)
3276 
3277 /*
3278  * Field : dzpq
3279  *
3280  * Disable Zero-Quanta Pause
3281  *
3282  * When this bit is set, it disables the automatic generation of the Zero-Quanta
3283  * Pause Control frames on the de-assertion of the flow-control signal from the
3284  * FIFO layer (MTL or external sideband flow control signal
3285  * sbd_flowctrl_i/mti_flowctrl_i).
3286  *
3287  * When this bit is reset, normal operation with automatic Zero-Quanta Pause
3288  * Control frame generation is enabled.
3289  *
3290  * Field Enumeration Values:
3291  *
3292  * Enum | Value | Description
3293  * :-----------------------------------|:------|:------------
3294  * ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_DISD | 0x0 |
3295  * ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_END | 0x1 |
3296  *
3297  * Field Access Macros:
3298  *
3299  */
3300 /*
3301  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_DZPQ
3302  *
3303  */
3304 #define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_DISD 0x0
3305 /*
3306  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_DZPQ
3307  *
3308  */
3309 #define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_END 0x1
3310 
3311 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field. */
3312 #define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_LSB 7
3313 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field. */
3314 #define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_MSB 7
3315 /* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field. */
3316 #define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_WIDTH 1
3317 /* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field value. */
3318 #define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_SET_MSK 0x00000080
3319 /* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field value. */
3320 #define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_CLR_MSK 0xffffff7f
3321 /* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field. */
3322 #define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_RESET 0x0
3323 /* Extracts the ALT_EMAC_GMAC_FLOW_CTL_DZPQ field value from a register. */
3324 #define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_GET(value) (((value) & 0x00000080) >> 7)
3325 /* Produces a ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field value suitable for setting the register. */
3326 #define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_SET(value) (((value) << 7) & 0x00000080)
3327 
3328 /*
3329  * Field : reserved_15_8
3330  *
3331  * Reserved
3332  *
3333  * Field Access Macros:
3334  *
3335  */
3336 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8 register field. */
3337 #define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_LSB 8
3338 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8 register field. */
3339 #define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_MSB 15
3340 /* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8 register field. */
3341 #define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_WIDTH 8
3342 /* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8 register field value. */
3343 #define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_SET_MSK 0x0000ff00
3344 /* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8 register field value. */
3345 #define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_CLR_MSK 0xffff00ff
3346 /* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8 register field. */
3347 #define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_RESET 0x0
3348 /* Extracts the ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8 field value from a register. */
3349 #define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_GET(value) (((value) & 0x0000ff00) >> 8)
3350 /* Produces a ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8 register field value suitable for setting the register. */
3351 #define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_SET(value) (((value) << 8) & 0x0000ff00)
3352 
3353 /*
3354  * Field : pt
3355  *
3356  * Pause Time
3357  *
3358  * This field holds the value to be used in the Pause Time field in the transmit
3359  * control frame. If the Pause Time bits is configured to be double-synchronized to
3360  * the (G)MII clock domain, then consecutive writes to this register should be
3361  * performed only after at least four clock cycles in the destination clock domain.
3362  *
3363  * Field Access Macros:
3364  *
3365  */
3366 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PT register field. */
3367 #define ALT_EMAC_GMAC_FLOW_CTL_PT_LSB 16
3368 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PT register field. */
3369 #define ALT_EMAC_GMAC_FLOW_CTL_PT_MSB 31
3370 /* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_PT register field. */
3371 #define ALT_EMAC_GMAC_FLOW_CTL_PT_WIDTH 16
3372 /* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_PT register field value. */
3373 #define ALT_EMAC_GMAC_FLOW_CTL_PT_SET_MSK 0xffff0000
3374 /* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_PT register field value. */
3375 #define ALT_EMAC_GMAC_FLOW_CTL_PT_CLR_MSK 0x0000ffff
3376 /* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_PT register field. */
3377 #define ALT_EMAC_GMAC_FLOW_CTL_PT_RESET 0x0
3378 /* Extracts the ALT_EMAC_GMAC_FLOW_CTL_PT field value from a register. */
3379 #define ALT_EMAC_GMAC_FLOW_CTL_PT_GET(value) (((value) & 0xffff0000) >> 16)
3380 /* Produces a ALT_EMAC_GMAC_FLOW_CTL_PT register field value suitable for setting the register. */
3381 #define ALT_EMAC_GMAC_FLOW_CTL_PT_SET(value) (((value) << 16) & 0xffff0000)
3382 
3383 #ifndef __ASSEMBLY__
3384 /*
3385  * WARNING: The C register and register group struct declarations are provided for
3386  * convenience and illustrative purposes. They should, however, be used with
3387  * caution as the C language standard provides no guarantees about the alignment or
3388  * atomicity of device memory accesses. The recommended practice for writing
3389  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3390  * alt_write_word() functions.
3391  *
3392  * The struct declaration for register ALT_EMAC_GMAC_FLOW_CTL.
3393  */
3394 struct ALT_EMAC_GMAC_FLOW_CTL_s
3395 {
3396  uint32_t fca_bpa : 1; /* ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA */
3397  uint32_t tfe : 1; /* ALT_EMAC_GMAC_FLOW_CTL_TFE */
3398  uint32_t rfe : 1; /* ALT_EMAC_GMAC_FLOW_CTL_RFE */
3399  uint32_t up : 1; /* ALT_EMAC_GMAC_FLOW_CTL_UP */
3400  uint32_t plt : 2; /* ALT_EMAC_GMAC_FLOW_CTL_PLT */
3401  const uint32_t reserved_6 : 1; /* ALT_EMAC_GMAC_FLOW_CTL_RSVD_6 */
3402  uint32_t dzpq : 1; /* ALT_EMAC_GMAC_FLOW_CTL_DZPQ */
3403  const uint32_t reserved_15_8 : 8; /* ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8 */
3404  uint32_t pt : 16; /* ALT_EMAC_GMAC_FLOW_CTL_PT */
3405 };
3406 
3407 /* The typedef declaration for register ALT_EMAC_GMAC_FLOW_CTL. */
3408 typedef volatile struct ALT_EMAC_GMAC_FLOW_CTL_s ALT_EMAC_GMAC_FLOW_CTL_t;
3409 #endif /* __ASSEMBLY__ */
3410 
3411 /* The reset value of the ALT_EMAC_GMAC_FLOW_CTL register. */
3412 #define ALT_EMAC_GMAC_FLOW_CTL_RESET 0x00000000
3413 /* The byte offset of the ALT_EMAC_GMAC_FLOW_CTL register from the beginning of the component. */
3414 #define ALT_EMAC_GMAC_FLOW_CTL_OFST 0x18
3415 /* The address of the ALT_EMAC_GMAC_FLOW_CTL register. */
3416 #define ALT_EMAC_GMAC_FLOW_CTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_FLOW_CTL_OFST))
3417 
3418 /*
3419  * Register : gmacgrp_vlan_tag
3420  *
3421  * <b> Register 7 (VLAN Tag Register) </b>
3422  *
3423  * The VLAN Tag register contains the IEEE 802.1Q VLAN Tag to identify the VLAN
3424  * frames. The MAC compares the 13th and 14th bytes of the receiving frame
3425  * (Length/Type) with 16'h8100, and the following two bytes are compared with the
3426  * VLAN tag. If a match occurs, the MAC sets the received VLAN bit in the receive
3427  * frame status. The legal length of the frame is increased from 1,518 bytes to
3428  * 1,522 bytes.
3429  *
3430  * If the VLAN Tag register is configured to be double-synchronized to the (G)MII
3431  * clock domain, then consecutive writes to these register should be performed only
3432  * after at least four clock cycles in the destination clock domain.
3433  *
3434  * Register Layout
3435  *
3436  * Bits | Access | Reset | Description
3437  * :--------|:-------|:------|:----------------------------------
3438  * [15:0] | RW | 0x0 | ALT_EMAC_GMAC_VLAN_TAG_VL
3439  * [16] | RW | 0x0 | ALT_EMAC_GMAC_VLAN_TAG_ETV
3440  * [17] | RW | 0x0 | ALT_EMAC_GMAC_VLAN_TAG_VTIM
3441  * [18] | RW | 0x0 | ALT_EMAC_GMAC_VLAN_TAG_ESVL
3442  * [19] | R | 0x0 | ALT_EMAC_GMAC_VLAN_TAG_VTHM
3443  * [31:20] | R | 0x0 | ALT_EMAC_GMAC_VLAN_TAG_RSVD_31_20
3444  *
3445  */
3446 /*
3447  * Field : vl
3448  *
3449  * VLAN Tag Identifier for Receive Frames
3450  *
3451  * This field contains the 802.1Q VLAN tag to identify the VLAN frames and is
3452  * compared to the 15th and 16th bytes of the frames being received for VLAN
3453  * frames. The following list describes the bits of this field:
3454  *
3455  * * Bits [15:13]: User Priority
3456  *
3457  * * Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI)
3458  *
3459  * * Bits[11:0]: VLAN tag's VLAN Identifier (VID) field
3460  *
3461  * When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison.
3462  *
3463  * If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the
3464  * fifteenth and 16th bytes for VLAN tag comparison, and declares all frames with a
3465  * Type field value of 0x8100 or 0x88a8 as VLAN frames.
3466  *
3467  * Field Access Macros:
3468  *
3469  */
3470 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VL register field. */
3471 #define ALT_EMAC_GMAC_VLAN_TAG_VL_LSB 0
3472 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VL register field. */
3473 #define ALT_EMAC_GMAC_VLAN_TAG_VL_MSB 15
3474 /* The width in bits of the ALT_EMAC_GMAC_VLAN_TAG_VL register field. */
3475 #define ALT_EMAC_GMAC_VLAN_TAG_VL_WIDTH 16
3476 /* The mask used to set the ALT_EMAC_GMAC_VLAN_TAG_VL register field value. */
3477 #define ALT_EMAC_GMAC_VLAN_TAG_VL_SET_MSK 0x0000ffff
3478 /* The mask used to clear the ALT_EMAC_GMAC_VLAN_TAG_VL register field value. */
3479 #define ALT_EMAC_GMAC_VLAN_TAG_VL_CLR_MSK 0xffff0000
3480 /* The reset value of the ALT_EMAC_GMAC_VLAN_TAG_VL register field. */
3481 #define ALT_EMAC_GMAC_VLAN_TAG_VL_RESET 0x0
3482 /* Extracts the ALT_EMAC_GMAC_VLAN_TAG_VL field value from a register. */
3483 #define ALT_EMAC_GMAC_VLAN_TAG_VL_GET(value) (((value) & 0x0000ffff) >> 0)
3484 /* Produces a ALT_EMAC_GMAC_VLAN_TAG_VL register field value suitable for setting the register. */
3485 #define ALT_EMAC_GMAC_VLAN_TAG_VL_SET(value) (((value) << 0) & 0x0000ffff)
3486 
3487 /*
3488  * Field : etv
3489  *
3490  * Enable 12-Bit VLAN Tag Comparison
3491  *
3492  * When this bit is set, a 12-bit VLAN identifier is used for comparing and
3493  * filtering instead of the complete 16-bit VLAN tag. Bits [11:0] of VLAN tag are
3494  * compared with the corresponding field in the received VLAN-tagged frame.
3495  * Similarly, when enabled, only 12 bits of the VLAN tag in the received frame are
3496  * used for hash-based VLAN filtering.
3497  *
3498  * When this bit is reset, all 16 bits of the 15th and 16th bytes of the received
3499  * VLAN frame are used for comparison and VLAN hash filtering.
3500  *
3501  * Field Enumeration Values:
3502  *
3503  * Enum | Value | Description
3504  * :----------------------------------|:------|:------------
3505  * ALT_EMAC_GMAC_VLAN_TAG_ETV_E_DISD | 0x0 |
3506  * ALT_EMAC_GMAC_VLAN_TAG_ETV_E_END | 0x1 |
3507  *
3508  * Field Access Macros:
3509  *
3510  */
3511 /*
3512  * Enumerated value for register field ALT_EMAC_GMAC_VLAN_TAG_ETV
3513  *
3514  */
3515 #define ALT_EMAC_GMAC_VLAN_TAG_ETV_E_DISD 0x0
3516 /*
3517  * Enumerated value for register field ALT_EMAC_GMAC_VLAN_TAG_ETV
3518  *
3519  */
3520 #define ALT_EMAC_GMAC_VLAN_TAG_ETV_E_END 0x1
3521 
3522 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_TAG_ETV register field. */
3523 #define ALT_EMAC_GMAC_VLAN_TAG_ETV_LSB 16
3524 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_TAG_ETV register field. */
3525 #define ALT_EMAC_GMAC_VLAN_TAG_ETV_MSB 16
3526 /* The width in bits of the ALT_EMAC_GMAC_VLAN_TAG_ETV register field. */
3527 #define ALT_EMAC_GMAC_VLAN_TAG_ETV_WIDTH 1
3528 /* The mask used to set the ALT_EMAC_GMAC_VLAN_TAG_ETV register field value. */
3529 #define ALT_EMAC_GMAC_VLAN_TAG_ETV_SET_MSK 0x00010000
3530 /* The mask used to clear the ALT_EMAC_GMAC_VLAN_TAG_ETV register field value. */
3531 #define ALT_EMAC_GMAC_VLAN_TAG_ETV_CLR_MSK 0xfffeffff
3532 /* The reset value of the ALT_EMAC_GMAC_VLAN_TAG_ETV register field. */
3533 #define ALT_EMAC_GMAC_VLAN_TAG_ETV_RESET 0x0
3534 /* Extracts the ALT_EMAC_GMAC_VLAN_TAG_ETV field value from a register. */
3535 #define ALT_EMAC_GMAC_VLAN_TAG_ETV_GET(value) (((value) & 0x00010000) >> 16)
3536 /* Produces a ALT_EMAC_GMAC_VLAN_TAG_ETV register field value suitable for setting the register. */
3537 #define ALT_EMAC_GMAC_VLAN_TAG_ETV_SET(value) (((value) << 16) & 0x00010000)
3538 
3539 /*
3540  * Field : vtim
3541  *
3542  * VLAN Tag Inverse Match Enable
3543  *
3544  * When set, this bit enables the VLAN Tag inverse matching. The frames that do not
3545  * have matching VLAN Tag are marked as matched.
3546  *
3547  * When reset, this bit enables the VLAN Tag perfect matching. The frames with
3548  * matched VLAN Tag are marked as matched.
3549  *
3550  * Field Access Macros:
3551  *
3552  */
3553 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field. */
3554 #define ALT_EMAC_GMAC_VLAN_TAG_VTIM_LSB 17
3555 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field. */
3556 #define ALT_EMAC_GMAC_VLAN_TAG_VTIM_MSB 17
3557 /* The width in bits of the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field. */
3558 #define ALT_EMAC_GMAC_VLAN_TAG_VTIM_WIDTH 1
3559 /* The mask used to set the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field value. */
3560 #define ALT_EMAC_GMAC_VLAN_TAG_VTIM_SET_MSK 0x00020000
3561 /* The mask used to clear the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field value. */
3562 #define ALT_EMAC_GMAC_VLAN_TAG_VTIM_CLR_MSK 0xfffdffff
3563 /* The reset value of the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field. */
3564 #define ALT_EMAC_GMAC_VLAN_TAG_VTIM_RESET 0x0
3565 /* Extracts the ALT_EMAC_GMAC_VLAN_TAG_VTIM field value from a register. */
3566 #define ALT_EMAC_GMAC_VLAN_TAG_VTIM_GET(value) (((value) & 0x00020000) >> 17)
3567 /* Produces a ALT_EMAC_GMAC_VLAN_TAG_VTIM register field value suitable for setting the register. */
3568 #define ALT_EMAC_GMAC_VLAN_TAG_VTIM_SET(value) (((value) << 17) & 0x00020000)
3569 
3570 /*
3571  * Field : esvl
3572  *
3573  * Enable S-VLAN
3574  *
3575  * When this bit is set, the MAC transmitter and receiver also consider the S-VLAN
3576  * (Type = 0x88A8) frames as valid VLAN tagged frames.
3577  *
3578  * Field Access Macros:
3579  *
3580  */
3581 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field. */
3582 #define ALT_EMAC_GMAC_VLAN_TAG_ESVL_LSB 18
3583 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field. */
3584 #define ALT_EMAC_GMAC_VLAN_TAG_ESVL_MSB 18
3585 /* The width in bits of the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field. */
3586 #define ALT_EMAC_GMAC_VLAN_TAG_ESVL_WIDTH 1
3587 /* The mask used to set the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field value. */
3588 #define ALT_EMAC_GMAC_VLAN_TAG_ESVL_SET_MSK 0x00040000
3589 /* The mask used to clear the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field value. */
3590 #define ALT_EMAC_GMAC_VLAN_TAG_ESVL_CLR_MSK 0xfffbffff
3591 /* The reset value of the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field. */
3592 #define ALT_EMAC_GMAC_VLAN_TAG_ESVL_RESET 0x0
3593 /* Extracts the ALT_EMAC_GMAC_VLAN_TAG_ESVL field value from a register. */
3594 #define ALT_EMAC_GMAC_VLAN_TAG_ESVL_GET(value) (((value) & 0x00040000) >> 18)
3595 /* Produces a ALT_EMAC_GMAC_VLAN_TAG_ESVL register field value suitable for setting the register. */
3596 #define ALT_EMAC_GMAC_VLAN_TAG_ESVL_SET(value) (((value) << 18) & 0x00040000)
3597 
3598 /*
3599  * Field : vthm
3600  *
3601  * VLAN Tag Hash Table Match Enable
3602  *
3603  * When set, the most significant four bits of the VLAN tag's CRC are used to index
3604  * the content of Register 354 (VLAN Hash Table Register). A value of 1 in the VLAN
3605  * Hash Table register, corresponding to the index, indicates that the frame
3606  * matched the VLAN hash table.
3607  *
3608  * When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used
3609  * for comparison whereas when ETV is reset, the CRC of the 16-bit VLAN tag is used
3610  * for comparison.
3611  *
3612  * When reset, the VLAN Hash Match operation is not performed. If the VLAN Hash
3613  * feature is not enabled during core configuration, this bit is reserved (RO with
3614  * default value).
3615  *
3616  * Field Access Macros:
3617  *
3618  */
3619 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field. */
3620 #define ALT_EMAC_GMAC_VLAN_TAG_VTHM_LSB 19
3621 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field. */
3622 #define ALT_EMAC_GMAC_VLAN_TAG_VTHM_MSB 19
3623 /* The width in bits of the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field. */
3624 #define ALT_EMAC_GMAC_VLAN_TAG_VTHM_WIDTH 1
3625 /* The mask used to set the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field value. */
3626 #define ALT_EMAC_GMAC_VLAN_TAG_VTHM_SET_MSK 0x00080000
3627 /* The mask used to clear the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field value. */
3628 #define ALT_EMAC_GMAC_VLAN_TAG_VTHM_CLR_MSK 0xfff7ffff
3629 /* The reset value of the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field. */
3630 #define ALT_EMAC_GMAC_VLAN_TAG_VTHM_RESET 0x0
3631 /* Extracts the ALT_EMAC_GMAC_VLAN_TAG_VTHM field value from a register. */
3632 #define ALT_EMAC_GMAC_VLAN_TAG_VTHM_GET(value) (((value) & 0x00080000) >> 19)
3633 /* Produces a ALT_EMAC_GMAC_VLAN_TAG_VTHM register field value suitable for setting the register. */
3634 #define ALT_EMAC_GMAC_VLAN_TAG_VTHM_SET(value) (((value) << 19) & 0x00080000)
3635 
3636 /*
3637  * Field : reserved_31_20
3638  *
3639  * Reserved
3640  *
3641  * Field Access Macros:
3642  *
3643  */
3644 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_TAG_RSVD_31_20 register field. */
3645 #define ALT_EMAC_GMAC_VLAN_TAG_RSVD_31_20_LSB 20
3646 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_TAG_RSVD_31_20 register field. */
3647 #define ALT_EMAC_GMAC_VLAN_TAG_RSVD_31_20_MSB 31
3648 /* The width in bits of the ALT_EMAC_GMAC_VLAN_TAG_RSVD_31_20 register field. */
3649 #define ALT_EMAC_GMAC_VLAN_TAG_RSVD_31_20_WIDTH 12
3650 /* The mask used to set the ALT_EMAC_GMAC_VLAN_TAG_RSVD_31_20 register field value. */
3651 #define ALT_EMAC_GMAC_VLAN_TAG_RSVD_31_20_SET_MSK 0xfff00000
3652 /* The mask used to clear the ALT_EMAC_GMAC_VLAN_TAG_RSVD_31_20 register field value. */
3653 #define ALT_EMAC_GMAC_VLAN_TAG_RSVD_31_20_CLR_MSK 0x000fffff
3654 /* The reset value of the ALT_EMAC_GMAC_VLAN_TAG_RSVD_31_20 register field. */
3655 #define ALT_EMAC_GMAC_VLAN_TAG_RSVD_31_20_RESET 0x0
3656 /* Extracts the ALT_EMAC_GMAC_VLAN_TAG_RSVD_31_20 field value from a register. */
3657 #define ALT_EMAC_GMAC_VLAN_TAG_RSVD_31_20_GET(value) (((value) & 0xfff00000) >> 20)
3658 /* Produces a ALT_EMAC_GMAC_VLAN_TAG_RSVD_31_20 register field value suitable for setting the register. */
3659 #define ALT_EMAC_GMAC_VLAN_TAG_RSVD_31_20_SET(value) (((value) << 20) & 0xfff00000)
3660 
3661 #ifndef __ASSEMBLY__
3662 /*
3663  * WARNING: The C register and register group struct declarations are provided for
3664  * convenience and illustrative purposes. They should, however, be used with
3665  * caution as the C language standard provides no guarantees about the alignment or
3666  * atomicity of device memory accesses. The recommended practice for writing
3667  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3668  * alt_write_word() functions.
3669  *
3670  * The struct declaration for register ALT_EMAC_GMAC_VLAN_TAG.
3671  */
3672 struct ALT_EMAC_GMAC_VLAN_TAG_s
3673 {
3674  uint32_t vl : 16; /* ALT_EMAC_GMAC_VLAN_TAG_VL */
3675  uint32_t etv : 1; /* ALT_EMAC_GMAC_VLAN_TAG_ETV */
3676  uint32_t vtim : 1; /* ALT_EMAC_GMAC_VLAN_TAG_VTIM */
3677  uint32_t esvl : 1; /* ALT_EMAC_GMAC_VLAN_TAG_ESVL */
3678  const uint32_t vthm : 1; /* ALT_EMAC_GMAC_VLAN_TAG_VTHM */
3679  const uint32_t reserved_31_20 : 12; /* ALT_EMAC_GMAC_VLAN_TAG_RSVD_31_20 */
3680 };
3681 
3682 /* The typedef declaration for register ALT_EMAC_GMAC_VLAN_TAG. */
3683 typedef volatile struct ALT_EMAC_GMAC_VLAN_TAG_s ALT_EMAC_GMAC_VLAN_TAG_t;
3684 #endif /* __ASSEMBLY__ */
3685 
3686 /* The reset value of the ALT_EMAC_GMAC_VLAN_TAG register. */
3687 #define ALT_EMAC_GMAC_VLAN_TAG_RESET 0x00000000
3688 /* The byte offset of the ALT_EMAC_GMAC_VLAN_TAG register from the beginning of the component. */
3689 #define ALT_EMAC_GMAC_VLAN_TAG_OFST 0x1c
3690 /* The address of the ALT_EMAC_GMAC_VLAN_TAG register. */
3691 #define ALT_EMAC_GMAC_VLAN_TAG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_VLAN_TAG_OFST))
3692 
3693 /*
3694  * Register : gmacgrp_version
3695  *
3696  * <b> Register 8 (Version Register) </b>
3697  *
3698  * The Version registers identifies the version of the DWC_gmac. This register
3699  * contains two bytes: one that Synopsys uses to identify the core release number,
3700  * and the other that you set during core configuration.
3701  *
3702  * Register Layout
3703  *
3704  * Bits | Access | Reset | Description
3705  * :--------|:-------|:------|:-----------------------------
3706  * [7:0] | R | 0x37 | ALT_EMAC_GMAC_VER_SNPSVER
3707  * [15:8] | R | 0x10 | ALT_EMAC_GMAC_VER_USERVER
3708  * [31:16] | R | 0x0 | ALT_EMAC_GMAC_VER_RSVD_31_16
3709  *
3710  */
3711 /*
3712  * Field : snpsver
3713  *
3714  * Synopsys-defined Version (3.7)
3715  *
3716  * Field Access Macros:
3717  *
3718  */
3719 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VER_SNPSVER register field. */
3720 #define ALT_EMAC_GMAC_VER_SNPSVER_LSB 0
3721 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VER_SNPSVER register field. */
3722 #define ALT_EMAC_GMAC_VER_SNPSVER_MSB 7
3723 /* The width in bits of the ALT_EMAC_GMAC_VER_SNPSVER register field. */
3724 #define ALT_EMAC_GMAC_VER_SNPSVER_WIDTH 8
3725 /* The mask used to set the ALT_EMAC_GMAC_VER_SNPSVER register field value. */
3726 #define ALT_EMAC_GMAC_VER_SNPSVER_SET_MSK 0x000000ff
3727 /* The mask used to clear the ALT_EMAC_GMAC_VER_SNPSVER register field value. */
3728 #define ALT_EMAC_GMAC_VER_SNPSVER_CLR_MSK 0xffffff00
3729 /* The reset value of the ALT_EMAC_GMAC_VER_SNPSVER register field. */
3730 #define ALT_EMAC_GMAC_VER_SNPSVER_RESET 0x37
3731 /* Extracts the ALT_EMAC_GMAC_VER_SNPSVER field value from a register. */
3732 #define ALT_EMAC_GMAC_VER_SNPSVER_GET(value) (((value) & 0x000000ff) >> 0)
3733 /* Produces a ALT_EMAC_GMAC_VER_SNPSVER register field value suitable for setting the register. */
3734 #define ALT_EMAC_GMAC_VER_SNPSVER_SET(value) (((value) << 0) & 0x000000ff)
3735 
3736 /*
3737  * Field : userver
3738  *
3739  * User-defined Version (Configured with the coreConsultant)
3740  *
3741  * Field Access Macros:
3742  *
3743  */
3744 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VER_USERVER register field. */
3745 #define ALT_EMAC_GMAC_VER_USERVER_LSB 8
3746 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VER_USERVER register field. */
3747 #define ALT_EMAC_GMAC_VER_USERVER_MSB 15
3748 /* The width in bits of the ALT_EMAC_GMAC_VER_USERVER register field. */
3749 #define ALT_EMAC_GMAC_VER_USERVER_WIDTH 8
3750 /* The mask used to set the ALT_EMAC_GMAC_VER_USERVER register field value. */
3751 #define ALT_EMAC_GMAC_VER_USERVER_SET_MSK 0x0000ff00
3752 /* The mask used to clear the ALT_EMAC_GMAC_VER_USERVER register field value. */
3753 #define ALT_EMAC_GMAC_VER_USERVER_CLR_MSK 0xffff00ff
3754 /* The reset value of the ALT_EMAC_GMAC_VER_USERVER register field. */
3755 #define ALT_EMAC_GMAC_VER_USERVER_RESET 0x10
3756 /* Extracts the ALT_EMAC_GMAC_VER_USERVER field value from a register. */
3757 #define ALT_EMAC_GMAC_VER_USERVER_GET(value) (((value) & 0x0000ff00) >> 8)
3758 /* Produces a ALT_EMAC_GMAC_VER_USERVER register field value suitable for setting the register. */
3759 #define ALT_EMAC_GMAC_VER_USERVER_SET(value) (((value) << 8) & 0x0000ff00)
3760 
3761 /*
3762  * Field : reserved_31_16
3763  *
3764  * Reserved
3765  *
3766  * Field Access Macros:
3767  *
3768  */
3769 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VER_RSVD_31_16 register field. */
3770 #define ALT_EMAC_GMAC_VER_RSVD_31_16_LSB 16
3771 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VER_RSVD_31_16 register field. */
3772 #define ALT_EMAC_GMAC_VER_RSVD_31_16_MSB 31
3773 /* The width in bits of the ALT_EMAC_GMAC_VER_RSVD_31_16 register field. */
3774 #define ALT_EMAC_GMAC_VER_RSVD_31_16_WIDTH 16
3775 /* The mask used to set the ALT_EMAC_GMAC_VER_RSVD_31_16 register field value. */
3776 #define ALT_EMAC_GMAC_VER_RSVD_31_16_SET_MSK 0xffff0000
3777 /* The mask used to clear the ALT_EMAC_GMAC_VER_RSVD_31_16 register field value. */
3778 #define ALT_EMAC_GMAC_VER_RSVD_31_16_CLR_MSK 0x0000ffff
3779 /* The reset value of the ALT_EMAC_GMAC_VER_RSVD_31_16 register field. */
3780 #define ALT_EMAC_GMAC_VER_RSVD_31_16_RESET 0x0
3781 /* Extracts the ALT_EMAC_GMAC_VER_RSVD_31_16 field value from a register. */
3782 #define ALT_EMAC_GMAC_VER_RSVD_31_16_GET(value) (((value) & 0xffff0000) >> 16)
3783 /* Produces a ALT_EMAC_GMAC_VER_RSVD_31_16 register field value suitable for setting the register. */
3784 #define ALT_EMAC_GMAC_VER_RSVD_31_16_SET(value) (((value) << 16) & 0xffff0000)
3785 
3786 #ifndef __ASSEMBLY__
3787 /*
3788  * WARNING: The C register and register group struct declarations are provided for
3789  * convenience and illustrative purposes. They should, however, be used with
3790  * caution as the C language standard provides no guarantees about the alignment or
3791  * atomicity of device memory accesses. The recommended practice for writing
3792  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3793  * alt_write_word() functions.
3794  *
3795  * The struct declaration for register ALT_EMAC_GMAC_VER.
3796  */
3797 struct ALT_EMAC_GMAC_VER_s
3798 {
3799  const uint32_t snpsver : 8; /* ALT_EMAC_GMAC_VER_SNPSVER */
3800  const uint32_t userver : 8; /* ALT_EMAC_GMAC_VER_USERVER */
3801  const uint32_t reserved_31_16 : 16; /* ALT_EMAC_GMAC_VER_RSVD_31_16 */
3802 };
3803 
3804 /* The typedef declaration for register ALT_EMAC_GMAC_VER. */
3805 typedef volatile struct ALT_EMAC_GMAC_VER_s ALT_EMAC_GMAC_VER_t;
3806 #endif /* __ASSEMBLY__ */
3807 
3808 /* The reset value of the ALT_EMAC_GMAC_VER register. */
3809 #define ALT_EMAC_GMAC_VER_RESET 0x00001037
3810 /* The byte offset of the ALT_EMAC_GMAC_VER register from the beginning of the component. */
3811 #define ALT_EMAC_GMAC_VER_OFST 0x20
3812 /* The address of the ALT_EMAC_GMAC_VER register. */
3813 #define ALT_EMAC_GMAC_VER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_VER_OFST))
3814 
3815 /*
3816  * Register : gmacgrp_debug
3817  *
3818  * <b> Register 9 (Debug Register) </b>
3819  *
3820  * The Debug register gives the status of all main modules of the transmit and
3821  * receive data-paths and the FIFOs. An all-zero status indicates that the MAC is
3822  * in idle state (and FIFOs are empty) and no activity is going on in the data-
3823  * paths.
3824  *
3825  * Note:
3826  *
3827  * The reset values, given for the Debug register, are valid only if the following
3828  * clocks are present during the reset operation:
3829  *
3830  * * clk_csr_i, clk_app_i, hclk_i, or aclk_i
3831  *
3832  * * clk_tx_i
3833  *
3834  * * clk_rx_i
3835  *
3836  * Register Layout
3837  *
3838  * Bits | Access | Reset | Description
3839  * :--------|:-------|:------|:-----------------------------
3840  * [0] | R | 0x0 | ALT_EMAC_GMAC_DBG_RPESTS
3841  * [2:1] | R | 0x0 | ALT_EMAC_GMAC_DBG_RFCFCSTS
3842  * [3] | R | 0x0 | ALT_EMAC_GMAC_DBG_RSVD_3
3843  * [4] | R | 0x0 | ALT_EMAC_GMAC_DBG_RWCSTS
3844  * [6:5] | R | 0x0 | ALT_EMAC_GMAC_DBG_RRCSTS
3845  * [7] | R | 0x0 | ALT_EMAC_GMAC_DBG_RSVD_7
3846  * [9:8] | R | 0x0 | ALT_EMAC_GMAC_DBG_RXFSTS
3847  * [15:10] | R | 0x0 | ALT_EMAC_GMAC_DBG_RSVD_15_10
3848  * [16] | R | 0x0 | ALT_EMAC_GMAC_DBG_TPESTS
3849  * [18:17] | R | 0x0 | ALT_EMAC_GMAC_DBG_TFCSTS
3850  * [19] | R | 0x0 | ALT_EMAC_GMAC_DBG_TXPAUSED
3851  * [21:20] | R | 0x0 | ALT_EMAC_GMAC_DBG_TRCSTS
3852  * [22] | R | 0x0 | ALT_EMAC_GMAC_DBG_TWCSTS
3853  * [23] | R | 0x0 | ALT_EMAC_GMAC_DBG_RSVD_23
3854  * [24] | R | 0x0 | ALT_EMAC_GMAC_DBG_TXFSTS
3855  * [25] | R | 0x0 | ALT_EMAC_GMAC_DBG_TXSTSFSTS
3856  * [31:26] | R | 0x0 | ALT_EMAC_GMAC_DBG_RSVD_31_26
3857  *
3858  */
3859 /*
3860  * Field : rpests
3861  *
3862  * MAC GMII or MII Receive Protocol Engine Status
3863  *
3864  * When high, this bit indicates that the MAC GMII or MII receive protocol engine
3865  * is actively receiving data and not in IDLE state.
3866  *
3867  * Field Enumeration Values:
3868  *
3869  * Enum | Value | Description
3870  * :---------------------------------|:------|:------------
3871  * ALT_EMAC_GMAC_DBG_RPESTS_E_INACT | 0x0 |
3872  * ALT_EMAC_GMAC_DBG_RPESTS_E_ACT | 0x1 |
3873  *
3874  * Field Access Macros:
3875  *
3876  */
3877 /*
3878  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RPESTS
3879  *
3880  */
3881 #define ALT_EMAC_GMAC_DBG_RPESTS_E_INACT 0x0
3882 /*
3883  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RPESTS
3884  *
3885  */
3886 #define ALT_EMAC_GMAC_DBG_RPESTS_E_ACT 0x1
3887 
3888 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RPESTS register field. */
3889 #define ALT_EMAC_GMAC_DBG_RPESTS_LSB 0
3890 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RPESTS register field. */
3891 #define ALT_EMAC_GMAC_DBG_RPESTS_MSB 0
3892 /* The width in bits of the ALT_EMAC_GMAC_DBG_RPESTS register field. */
3893 #define ALT_EMAC_GMAC_DBG_RPESTS_WIDTH 1
3894 /* The mask used to set the ALT_EMAC_GMAC_DBG_RPESTS register field value. */
3895 #define ALT_EMAC_GMAC_DBG_RPESTS_SET_MSK 0x00000001
3896 /* The mask used to clear the ALT_EMAC_GMAC_DBG_RPESTS register field value. */
3897 #define ALT_EMAC_GMAC_DBG_RPESTS_CLR_MSK 0xfffffffe
3898 /* The reset value of the ALT_EMAC_GMAC_DBG_RPESTS register field. */
3899 #define ALT_EMAC_GMAC_DBG_RPESTS_RESET 0x0
3900 /* Extracts the ALT_EMAC_GMAC_DBG_RPESTS field value from a register. */
3901 #define ALT_EMAC_GMAC_DBG_RPESTS_GET(value) (((value) & 0x00000001) >> 0)
3902 /* Produces a ALT_EMAC_GMAC_DBG_RPESTS register field value suitable for setting the register. */
3903 #define ALT_EMAC_GMAC_DBG_RPESTS_SET(value) (((value) << 0) & 0x00000001)
3904 
3905 /*
3906  * Field : rfcfcsts
3907  *
3908  * MAC Receive Frame Controller FIFO Status
3909  *
3910  * When high, this field indicates the active state of the small FIFO Read and
3911  * Write controllers of the MAC Receive Frame Controller Module.
3912  *
3913  * Field Enumeration Values:
3914  *
3915  * Enum | Value | Description
3916  * :-----------------------------------|:------|:------------
3917  * ALT_EMAC_GMAC_DBG_RFCFCSTS_E_INACT | 0x0 |
3918  * ALT_EMAC_GMAC_DBG_RFCFCSTS_E_ACT | 0x1 |
3919  *
3920  * Field Access Macros:
3921  *
3922  */
3923 /*
3924  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RFCFCSTS
3925  *
3926  */
3927 #define ALT_EMAC_GMAC_DBG_RFCFCSTS_E_INACT 0x0
3928 /*
3929  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RFCFCSTS
3930  *
3931  */
3932 #define ALT_EMAC_GMAC_DBG_RFCFCSTS_E_ACT 0x1
3933 
3934 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RFCFCSTS register field. */
3935 #define ALT_EMAC_GMAC_DBG_RFCFCSTS_LSB 1
3936 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RFCFCSTS register field. */
3937 #define ALT_EMAC_GMAC_DBG_RFCFCSTS_MSB 2
3938 /* The width in bits of the ALT_EMAC_GMAC_DBG_RFCFCSTS register field. */
3939 #define ALT_EMAC_GMAC_DBG_RFCFCSTS_WIDTH 2
3940 /* The mask used to set the ALT_EMAC_GMAC_DBG_RFCFCSTS register field value. */
3941 #define ALT_EMAC_GMAC_DBG_RFCFCSTS_SET_MSK 0x00000006
3942 /* The mask used to clear the ALT_EMAC_GMAC_DBG_RFCFCSTS register field value. */
3943 #define ALT_EMAC_GMAC_DBG_RFCFCSTS_CLR_MSK 0xfffffff9
3944 /* The reset value of the ALT_EMAC_GMAC_DBG_RFCFCSTS register field. */
3945 #define ALT_EMAC_GMAC_DBG_RFCFCSTS_RESET 0x0
3946 /* Extracts the ALT_EMAC_GMAC_DBG_RFCFCSTS field value from a register. */
3947 #define ALT_EMAC_GMAC_DBG_RFCFCSTS_GET(value) (((value) & 0x00000006) >> 1)
3948 /* Produces a ALT_EMAC_GMAC_DBG_RFCFCSTS register field value suitable for setting the register. */
3949 #define ALT_EMAC_GMAC_DBG_RFCFCSTS_SET(value) (((value) << 1) & 0x00000006)
3950 
3951 /*
3952  * Field : reserved_3
3953  *
3954  * Reserved
3955  *
3956  * Field Access Macros:
3957  *
3958  */
3959 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RSVD_3 register field. */
3960 #define ALT_EMAC_GMAC_DBG_RSVD_3_LSB 3
3961 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RSVD_3 register field. */
3962 #define ALT_EMAC_GMAC_DBG_RSVD_3_MSB 3
3963 /* The width in bits of the ALT_EMAC_GMAC_DBG_RSVD_3 register field. */
3964 #define ALT_EMAC_GMAC_DBG_RSVD_3_WIDTH 1
3965 /* The mask used to set the ALT_EMAC_GMAC_DBG_RSVD_3 register field value. */
3966 #define ALT_EMAC_GMAC_DBG_RSVD_3_SET_MSK 0x00000008
3967 /* The mask used to clear the ALT_EMAC_GMAC_DBG_RSVD_3 register field value. */
3968 #define ALT_EMAC_GMAC_DBG_RSVD_3_CLR_MSK 0xfffffff7
3969 /* The reset value of the ALT_EMAC_GMAC_DBG_RSVD_3 register field. */
3970 #define ALT_EMAC_GMAC_DBG_RSVD_3_RESET 0x0
3971 /* Extracts the ALT_EMAC_GMAC_DBG_RSVD_3 field value from a register. */
3972 #define ALT_EMAC_GMAC_DBG_RSVD_3_GET(value) (((value) & 0x00000008) >> 3)
3973 /* Produces a ALT_EMAC_GMAC_DBG_RSVD_3 register field value suitable for setting the register. */
3974 #define ALT_EMAC_GMAC_DBG_RSVD_3_SET(value) (((value) << 3) & 0x00000008)
3975 
3976 /*
3977  * Field : rwcsts
3978  *
3979  * MTL Rx FIFO Write Controller Active Status
3980  *
3981  * When high, this bit indicates that the MTL Rx FIFO Write Controller is active
3982  * and is transferring a received frame to the FIFO.
3983  *
3984  * Field Enumeration Values:
3985  *
3986  * Enum | Value | Description
3987  * :---------------------------------|:------|:------------
3988  * ALT_EMAC_GMAC_DBG_RWCSTS_E_INACT | 0x0 |
3989  * ALT_EMAC_GMAC_DBG_RWCSTS_E_ACT | 0x1 |
3990  *
3991  * Field Access Macros:
3992  *
3993  */
3994 /*
3995  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RWCSTS
3996  *
3997  */
3998 #define ALT_EMAC_GMAC_DBG_RWCSTS_E_INACT 0x0
3999 /*
4000  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RWCSTS
4001  *
4002  */
4003 #define ALT_EMAC_GMAC_DBG_RWCSTS_E_ACT 0x1
4004 
4005 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RWCSTS register field. */
4006 #define ALT_EMAC_GMAC_DBG_RWCSTS_LSB 4
4007 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RWCSTS register field. */
4008 #define ALT_EMAC_GMAC_DBG_RWCSTS_MSB 4
4009 /* The width in bits of the ALT_EMAC_GMAC_DBG_RWCSTS register field. */
4010 #define ALT_EMAC_GMAC_DBG_RWCSTS_WIDTH 1
4011 /* The mask used to set the ALT_EMAC_GMAC_DBG_RWCSTS register field value. */
4012 #define ALT_EMAC_GMAC_DBG_RWCSTS_SET_MSK 0x00000010
4013 /* The mask used to clear the ALT_EMAC_GMAC_DBG_RWCSTS register field value. */
4014 #define ALT_EMAC_GMAC_DBG_RWCSTS_CLR_MSK 0xffffffef
4015 /* The reset value of the ALT_EMAC_GMAC_DBG_RWCSTS register field. */
4016 #define ALT_EMAC_GMAC_DBG_RWCSTS_RESET 0x0
4017 /* Extracts the ALT_EMAC_GMAC_DBG_RWCSTS field value from a register. */
4018 #define ALT_EMAC_GMAC_DBG_RWCSTS_GET(value) (((value) & 0x00000010) >> 4)
4019 /* Produces a ALT_EMAC_GMAC_DBG_RWCSTS register field value suitable for setting the register. */
4020 #define ALT_EMAC_GMAC_DBG_RWCSTS_SET(value) (((value) << 4) & 0x00000010)
4021 
4022 /*
4023  * Field : rrcsts
4024  *
4025  * MTL Rx FIFO Read Controller State
4026  *
4027  * This field gives the state of the Rx FIFO read Controller:
4028  *
4029  * * 00: IDLE state
4030  *
4031  * * 01: Reading frame data
4032  *
4033  * * 10: Reading frame status (or timestamp)
4034  *
4035  * * 11: Flushing the frame data and status
4036  *
4037  * Field Enumeration Values:
4038  *
4039  * Enum | Value | Description
4040  * :-------------------------------------|:------|:------------
4041  * ALT_EMAC_GMAC_DBG_RRCSTS_E_IDLE | 0x0 |
4042  * ALT_EMAC_GMAC_DBG_RRCSTS_E_RDFRMDATA | 0x1 |
4043  * ALT_EMAC_GMAC_DBG_RRCSTS_E_RDFRMSTAT | 0x2 |
4044  * ALT_EMAC_GMAC_DBG_RRCSTS_E_FLUSHFRDS | 0x3 |
4045  *
4046  * Field Access Macros:
4047  *
4048  */
4049 /*
4050  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RRCSTS
4051  *
4052  */
4053 #define ALT_EMAC_GMAC_DBG_RRCSTS_E_IDLE 0x0
4054 /*
4055  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RRCSTS
4056  *
4057  */
4058 #define ALT_EMAC_GMAC_DBG_RRCSTS_E_RDFRMDATA 0x1
4059 /*
4060  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RRCSTS
4061  *
4062  */
4063 #define ALT_EMAC_GMAC_DBG_RRCSTS_E_RDFRMSTAT 0x2
4064 /*
4065  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RRCSTS
4066  *
4067  */
4068 #define ALT_EMAC_GMAC_DBG_RRCSTS_E_FLUSHFRDS 0x3
4069 
4070 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RRCSTS register field. */
4071 #define ALT_EMAC_GMAC_DBG_RRCSTS_LSB 5
4072 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RRCSTS register field. */
4073 #define ALT_EMAC_GMAC_DBG_RRCSTS_MSB 6
4074 /* The width in bits of the ALT_EMAC_GMAC_DBG_RRCSTS register field. */
4075 #define ALT_EMAC_GMAC_DBG_RRCSTS_WIDTH 2
4076 /* The mask used to set the ALT_EMAC_GMAC_DBG_RRCSTS register field value. */
4077 #define ALT_EMAC_GMAC_DBG_RRCSTS_SET_MSK 0x00000060
4078 /* The mask used to clear the ALT_EMAC_GMAC_DBG_RRCSTS register field value. */
4079 #define ALT_EMAC_GMAC_DBG_RRCSTS_CLR_MSK 0xffffff9f
4080 /* The reset value of the ALT_EMAC_GMAC_DBG_RRCSTS register field. */
4081 #define ALT_EMAC_GMAC_DBG_RRCSTS_RESET 0x0
4082 /* Extracts the ALT_EMAC_GMAC_DBG_RRCSTS field value from a register. */
4083 #define ALT_EMAC_GMAC_DBG_RRCSTS_GET(value) (((value) & 0x00000060) >> 5)
4084 /* Produces a ALT_EMAC_GMAC_DBG_RRCSTS register field value suitable for setting the register. */
4085 #define ALT_EMAC_GMAC_DBG_RRCSTS_SET(value) (((value) << 5) & 0x00000060)
4086 
4087 /*
4088  * Field : reserved_7
4089  *
4090  * Reserved
4091  *
4092  * Field Access Macros:
4093  *
4094  */
4095 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RSVD_7 register field. */
4096 #define ALT_EMAC_GMAC_DBG_RSVD_7_LSB 7
4097 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RSVD_7 register field. */
4098 #define ALT_EMAC_GMAC_DBG_RSVD_7_MSB 7
4099 /* The width in bits of the ALT_EMAC_GMAC_DBG_RSVD_7 register field. */
4100 #define ALT_EMAC_GMAC_DBG_RSVD_7_WIDTH 1
4101 /* The mask used to set the ALT_EMAC_GMAC_DBG_RSVD_7 register field value. */
4102 #define ALT_EMAC_GMAC_DBG_RSVD_7_SET_MSK 0x00000080
4103 /* The mask used to clear the ALT_EMAC_GMAC_DBG_RSVD_7 register field value. */
4104 #define ALT_EMAC_GMAC_DBG_RSVD_7_CLR_MSK 0xffffff7f
4105 /* The reset value of the ALT_EMAC_GMAC_DBG_RSVD_7 register field. */
4106 #define ALT_EMAC_GMAC_DBG_RSVD_7_RESET 0x0
4107 /* Extracts the ALT_EMAC_GMAC_DBG_RSVD_7 field value from a register. */
4108 #define ALT_EMAC_GMAC_DBG_RSVD_7_GET(value) (((value) & 0x00000080) >> 7)
4109 /* Produces a ALT_EMAC_GMAC_DBG_RSVD_7 register field value suitable for setting the register. */
4110 #define ALT_EMAC_GMAC_DBG_RSVD_7_SET(value) (((value) << 7) & 0x00000080)
4111 
4112 /*
4113  * Field : rxfsts
4114  *
4115  * MTL Rx FIFO Fill-level Status
4116  *
4117  * This field gives the status of the fill-level of the Rx FIFO:
4118  *
4119  * * 00: Rx FIFO Empty
4120  *
4121  * * 01: Rx FIFO fill level is below the flow-control deactivate threshold
4122  *
4123  * * 10: Rx FIFO fill level is above the flow-control activate threshold
4124  *
4125  * * 11: Rx FIFO Full
4126  *
4127  * Field Enumeration Values:
4128  *
4129  * Enum | Value | Description
4130  * :----------------------------------------|:------|:------------
4131  * ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOEMPTY | 0x0 |
4132  * ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOBELLVL | 0x1 |
4133  * ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOABLVL | 0x2 |
4134  * ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOFULL | 0x3 |
4135  *
4136  * Field Access Macros:
4137  *
4138  */
4139 /*
4140  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RXFSTS
4141  *
4142  */
4143 #define ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOEMPTY 0x0
4144 /*
4145  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RXFSTS
4146  *
4147  */
4148 #define ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOBELLVL 0x1
4149 /*
4150  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RXFSTS
4151  *
4152  */
4153 #define ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOABLVL 0x2
4154 /*
4155  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RXFSTS
4156  *
4157  */
4158 #define ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOFULL 0x3
4159 
4160 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RXFSTS register field. */
4161 #define ALT_EMAC_GMAC_DBG_RXFSTS_LSB 8
4162 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RXFSTS register field. */
4163 #define ALT_EMAC_GMAC_DBG_RXFSTS_MSB 9
4164 /* The width in bits of the ALT_EMAC_GMAC_DBG_RXFSTS register field. */
4165 #define ALT_EMAC_GMAC_DBG_RXFSTS_WIDTH 2
4166 /* The mask used to set the ALT_EMAC_GMAC_DBG_RXFSTS register field value. */
4167 #define ALT_EMAC_GMAC_DBG_RXFSTS_SET_MSK 0x00000300
4168 /* The mask used to clear the ALT_EMAC_GMAC_DBG_RXFSTS register field value. */
4169 #define ALT_EMAC_GMAC_DBG_RXFSTS_CLR_MSK 0xfffffcff
4170 /* The reset value of the ALT_EMAC_GMAC_DBG_RXFSTS register field. */
4171 #define ALT_EMAC_GMAC_DBG_RXFSTS_RESET 0x0
4172 /* Extracts the ALT_EMAC_GMAC_DBG_RXFSTS field value from a register. */
4173 #define ALT_EMAC_GMAC_DBG_RXFSTS_GET(value) (((value) & 0x00000300) >> 8)
4174 /* Produces a ALT_EMAC_GMAC_DBG_RXFSTS register field value suitable for setting the register. */
4175 #define ALT_EMAC_GMAC_DBG_RXFSTS_SET(value) (((value) << 8) & 0x00000300)
4176 
4177 /*
4178  * Field : reserved_15_10
4179  *
4180  * Reserved
4181  *
4182  * Field Access Macros:
4183  *
4184  */
4185 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RSVD_15_10 register field. */
4186 #define ALT_EMAC_GMAC_DBG_RSVD_15_10_LSB 10
4187 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RSVD_15_10 register field. */
4188 #define ALT_EMAC_GMAC_DBG_RSVD_15_10_MSB 15
4189 /* The width in bits of the ALT_EMAC_GMAC_DBG_RSVD_15_10 register field. */
4190 #define ALT_EMAC_GMAC_DBG_RSVD_15_10_WIDTH 6
4191 /* The mask used to set the ALT_EMAC_GMAC_DBG_RSVD_15_10 register field value. */
4192 #define ALT_EMAC_GMAC_DBG_RSVD_15_10_SET_MSK 0x0000fc00
4193 /* The mask used to clear the ALT_EMAC_GMAC_DBG_RSVD_15_10 register field value. */
4194 #define ALT_EMAC_GMAC_DBG_RSVD_15_10_CLR_MSK 0xffff03ff
4195 /* The reset value of the ALT_EMAC_GMAC_DBG_RSVD_15_10 register field. */
4196 #define ALT_EMAC_GMAC_DBG_RSVD_15_10_RESET 0x0
4197 /* Extracts the ALT_EMAC_GMAC_DBG_RSVD_15_10 field value from a register. */
4198 #define ALT_EMAC_GMAC_DBG_RSVD_15_10_GET(value) (((value) & 0x0000fc00) >> 10)
4199 /* Produces a ALT_EMAC_GMAC_DBG_RSVD_15_10 register field value suitable for setting the register. */
4200 #define ALT_EMAC_GMAC_DBG_RSVD_15_10_SET(value) (((value) << 10) & 0x0000fc00)
4201 
4202 /*
4203  * Field : tpests
4204  *
4205  * MAC GMII or MII Transmit Protocol Engine Status
4206  *
4207  * When high, this bit indicates that the MAC GMII or MII transmit protocol engine
4208  * is actively transmitting data and is not in the IDLE state.
4209  *
4210  * Field Enumeration Values:
4211  *
4212  * Enum | Value | Description
4213  * :--------------------------------|:------|:------------
4214  * ALT_EMAC_GMAC_DBG_TPESTS_E_DISD | 0x0 |
4215  * ALT_EMAC_GMAC_DBG_TPESTS_E_END | 0x1 |
4216  *
4217  * Field Access Macros:
4218  *
4219  */
4220 /*
4221  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TPESTS
4222  *
4223  */
4224 #define ALT_EMAC_GMAC_DBG_TPESTS_E_DISD 0x0
4225 /*
4226  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TPESTS
4227  *
4228  */
4229 #define ALT_EMAC_GMAC_DBG_TPESTS_E_END 0x1
4230 
4231 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TPESTS register field. */
4232 #define ALT_EMAC_GMAC_DBG_TPESTS_LSB 16
4233 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TPESTS register field. */
4234 #define ALT_EMAC_GMAC_DBG_TPESTS_MSB 16
4235 /* The width in bits of the ALT_EMAC_GMAC_DBG_TPESTS register field. */
4236 #define ALT_EMAC_GMAC_DBG_TPESTS_WIDTH 1
4237 /* The mask used to set the ALT_EMAC_GMAC_DBG_TPESTS register field value. */
4238 #define ALT_EMAC_GMAC_DBG_TPESTS_SET_MSK 0x00010000
4239 /* The mask used to clear the ALT_EMAC_GMAC_DBG_TPESTS register field value. */
4240 #define ALT_EMAC_GMAC_DBG_TPESTS_CLR_MSK 0xfffeffff
4241 /* The reset value of the ALT_EMAC_GMAC_DBG_TPESTS register field. */
4242 #define ALT_EMAC_GMAC_DBG_TPESTS_RESET 0x0
4243 /* Extracts the ALT_EMAC_GMAC_DBG_TPESTS field value from a register. */
4244 #define ALT_EMAC_GMAC_DBG_TPESTS_GET(value) (((value) & 0x00010000) >> 16)
4245 /* Produces a ALT_EMAC_GMAC_DBG_TPESTS register field value suitable for setting the register. */
4246 #define ALT_EMAC_GMAC_DBG_TPESTS_SET(value) (((value) << 16) & 0x00010000)
4247 
4248 /*
4249  * Field : tfcsts
4250  *
4251  * MAC Transmit Frame Controller Status
4252  *
4253  * This field indicates the state of the MAC Transmit Frame Controller module:
4254  *
4255  * * 00: IDLE state
4256  *
4257  * * 01: Waiting for Status of previous frame or IFG or backoff period to be over
4258  *
4259  * * 10: Generating and transmitting a PAUSE control frame (in the full-duplex
4260  * mode)
4261  *
4262  * * 11: Transferring input frame for transmission
4263  *
4264  * Field Enumeration Values:
4265  *
4266  * Enum | Value | Description
4267  * :-----------------------------------|:------|:------------
4268  * ALT_EMAC_GMAC_DBG_TFCSTS_E_IDLE | 0x0 |
4269  * ALT_EMAC_GMAC_DBG_TFCSTS_E_WAITIFG | 0x1 |
4270  * ALT_EMAC_GMAC_DBG_TFCSTS_E_XTPAUSE | 0x2 |
4271  * ALT_EMAC_GMAC_DBG_TFCSTS_E_XTINFRM | 0x3 |
4272  *
4273  * Field Access Macros:
4274  *
4275  */
4276 /*
4277  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TFCSTS
4278  *
4279  */
4280 #define ALT_EMAC_GMAC_DBG_TFCSTS_E_IDLE 0x0
4281 /*
4282  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TFCSTS
4283  *
4284  */
4285 #define ALT_EMAC_GMAC_DBG_TFCSTS_E_WAITIFG 0x1
4286 /*
4287  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TFCSTS
4288  *
4289  */
4290 #define ALT_EMAC_GMAC_DBG_TFCSTS_E_XTPAUSE 0x2
4291 /*
4292  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TFCSTS
4293  *
4294  */
4295 #define ALT_EMAC_GMAC_DBG_TFCSTS_E_XTINFRM 0x3
4296 
4297 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TFCSTS register field. */
4298 #define ALT_EMAC_GMAC_DBG_TFCSTS_LSB 17
4299 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TFCSTS register field. */
4300 #define ALT_EMAC_GMAC_DBG_TFCSTS_MSB 18
4301 /* The width in bits of the ALT_EMAC_GMAC_DBG_TFCSTS register field. */
4302 #define ALT_EMAC_GMAC_DBG_TFCSTS_WIDTH 2
4303 /* The mask used to set the ALT_EMAC_GMAC_DBG_TFCSTS register field value. */
4304 #define ALT_EMAC_GMAC_DBG_TFCSTS_SET_MSK 0x00060000
4305 /* The mask used to clear the ALT_EMAC_GMAC_DBG_TFCSTS register field value. */
4306 #define ALT_EMAC_GMAC_DBG_TFCSTS_CLR_MSK 0xfff9ffff
4307 /* The reset value of the ALT_EMAC_GMAC_DBG_TFCSTS register field. */
4308 #define ALT_EMAC_GMAC_DBG_TFCSTS_RESET 0x0
4309 /* Extracts the ALT_EMAC_GMAC_DBG_TFCSTS field value from a register. */
4310 #define ALT_EMAC_GMAC_DBG_TFCSTS_GET(value) (((value) & 0x00060000) >> 17)
4311 /* Produces a ALT_EMAC_GMAC_DBG_TFCSTS register field value suitable for setting the register. */
4312 #define ALT_EMAC_GMAC_DBG_TFCSTS_SET(value) (((value) << 17) & 0x00060000)
4313 
4314 /*
4315  * Field : txpaused
4316  *
4317  * MAC transmitter in PAUSE
4318  *
4319  * When high, this bit indicates that the MAC transmitter is in the PAUSE condition
4320  * (in the full-duplex only mode) and hence does not schedule any frame for
4321  * transmission.
4322  *
4323  * Field Enumeration Values:
4324  *
4325  * Enum | Value | Description
4326  * :---------------------------------|:------|:------------
4327  * ALT_EMAC_GMAC_DBG_TXPAUSED_E_DIS | 0x0 |
4328  * ALT_EMAC_GMAC_DBG_TXPAUSED_E_END | 0x1 |
4329  *
4330  * Field Access Macros:
4331  *
4332  */
4333 /*
4334  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXPAUSED
4335  *
4336  */
4337 #define ALT_EMAC_GMAC_DBG_TXPAUSED_E_DIS 0x0
4338 /*
4339  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXPAUSED
4340  *
4341  */
4342 #define ALT_EMAC_GMAC_DBG_TXPAUSED_E_END 0x1
4343 
4344 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TXPAUSED register field. */
4345 #define ALT_EMAC_GMAC_DBG_TXPAUSED_LSB 19
4346 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TXPAUSED register field. */
4347 #define ALT_EMAC_GMAC_DBG_TXPAUSED_MSB 19
4348 /* The width in bits of the ALT_EMAC_GMAC_DBG_TXPAUSED register field. */
4349 #define ALT_EMAC_GMAC_DBG_TXPAUSED_WIDTH 1
4350 /* The mask used to set the ALT_EMAC_GMAC_DBG_TXPAUSED register field value. */
4351 #define ALT_EMAC_GMAC_DBG_TXPAUSED_SET_MSK 0x00080000
4352 /* The mask used to clear the ALT_EMAC_GMAC_DBG_TXPAUSED register field value. */
4353 #define ALT_EMAC_GMAC_DBG_TXPAUSED_CLR_MSK 0xfff7ffff
4354 /* The reset value of the ALT_EMAC_GMAC_DBG_TXPAUSED register field. */
4355 #define ALT_EMAC_GMAC_DBG_TXPAUSED_RESET 0x0
4356 /* Extracts the ALT_EMAC_GMAC_DBG_TXPAUSED field value from a register. */
4357 #define ALT_EMAC_GMAC_DBG_TXPAUSED_GET(value) (((value) & 0x00080000) >> 19)
4358 /* Produces a ALT_EMAC_GMAC_DBG_TXPAUSED register field value suitable for setting the register. */
4359 #define ALT_EMAC_GMAC_DBG_TXPAUSED_SET(value) (((value) << 19) & 0x00080000)
4360 
4361 /*
4362  * Field : trcsts
4363  *
4364  * MTL Tx FIFO Read Controller Status
4365  *
4366  * This field indicates the state of the Tx FIFO Read Controller:
4367  *
4368  * * 00: IDLE state
4369  *
4370  * * 01: READ state (transferring data to MAC transmitter)
4371  *
4372  * * 10: Waiting for TxStatus from MAC transmitter
4373  *
4374  * * 11: Writing the received TxStatus or flushing the Tx FIFO
4375  *
4376  * Field Enumeration Values:
4377  *
4378  * Enum | Value | Description
4379  * :--------------------------------------|:------|:------------
4380  * ALT_EMAC_GMAC_DBG_TRCSTS_E_IDLE | 0x0 |
4381  * ALT_EMAC_GMAC_DBG_TRCSTS_E_RDSTATE | 0x1 |
4382  * ALT_EMAC_GMAC_DBG_TRCSTS_E_WAITTXSTAT | 0x2 |
4383  * ALT_EMAC_GMAC_DBG_TRCSTS_E_WRTXSTAT | 0x3 |
4384  *
4385  * Field Access Macros:
4386  *
4387  */
4388 /*
4389  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TRCSTS
4390  *
4391  */
4392 #define ALT_EMAC_GMAC_DBG_TRCSTS_E_IDLE 0x0
4393 /*
4394  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TRCSTS
4395  *
4396  */
4397 #define ALT_EMAC_GMAC_DBG_TRCSTS_E_RDSTATE 0x1
4398 /*
4399  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TRCSTS
4400  *
4401  */
4402 #define ALT_EMAC_GMAC_DBG_TRCSTS_E_WAITTXSTAT 0x2
4403 /*
4404  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TRCSTS
4405  *
4406  */
4407 #define ALT_EMAC_GMAC_DBG_TRCSTS_E_WRTXSTAT 0x3
4408 
4409 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TRCSTS register field. */
4410 #define ALT_EMAC_GMAC_DBG_TRCSTS_LSB 20
4411 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TRCSTS register field. */
4412 #define ALT_EMAC_GMAC_DBG_TRCSTS_MSB 21
4413 /* The width in bits of the ALT_EMAC_GMAC_DBG_TRCSTS register field. */
4414 #define ALT_EMAC_GMAC_DBG_TRCSTS_WIDTH 2
4415 /* The mask used to set the ALT_EMAC_GMAC_DBG_TRCSTS register field value. */
4416 #define ALT_EMAC_GMAC_DBG_TRCSTS_SET_MSK 0x00300000
4417 /* The mask used to clear the ALT_EMAC_GMAC_DBG_TRCSTS register field value. */
4418 #define ALT_EMAC_GMAC_DBG_TRCSTS_CLR_MSK 0xffcfffff
4419 /* The reset value of the ALT_EMAC_GMAC_DBG_TRCSTS register field. */
4420 #define ALT_EMAC_GMAC_DBG_TRCSTS_RESET 0x0
4421 /* Extracts the ALT_EMAC_GMAC_DBG_TRCSTS field value from a register. */
4422 #define ALT_EMAC_GMAC_DBG_TRCSTS_GET(value) (((value) & 0x00300000) >> 20)
4423 /* Produces a ALT_EMAC_GMAC_DBG_TRCSTS register field value suitable for setting the register. */
4424 #define ALT_EMAC_GMAC_DBG_TRCSTS_SET(value) (((value) << 20) & 0x00300000)
4425 
4426 /*
4427  * Field : twcsts
4428  *
4429  * MTL Tx FIFO Write Controller Active Status
4430  *
4431  * When high, this bit indicates that the MTL Tx FIFO Write Controller is active
4432  * and transferring data to the Tx FIFO.
4433  *
4434  * Field Enumeration Values:
4435  *
4436  * Enum | Value | Description
4437  * :---------------------------------|:------|:------------
4438  * ALT_EMAC_GMAC_DBG_TWCSTS_E_INACT | 0x0 |
4439  * ALT_EMAC_GMAC_DBG_TWCSTS_E_ACT | 0x1 |
4440  *
4441  * Field Access Macros:
4442  *
4443  */
4444 /*
4445  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TWCSTS
4446  *
4447  */
4448 #define ALT_EMAC_GMAC_DBG_TWCSTS_E_INACT 0x0
4449 /*
4450  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TWCSTS
4451  *
4452  */
4453 #define ALT_EMAC_GMAC_DBG_TWCSTS_E_ACT 0x1
4454 
4455 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TWCSTS register field. */
4456 #define ALT_EMAC_GMAC_DBG_TWCSTS_LSB 22
4457 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TWCSTS register field. */
4458 #define ALT_EMAC_GMAC_DBG_TWCSTS_MSB 22
4459 /* The width in bits of the ALT_EMAC_GMAC_DBG_TWCSTS register field. */
4460 #define ALT_EMAC_GMAC_DBG_TWCSTS_WIDTH 1
4461 /* The mask used to set the ALT_EMAC_GMAC_DBG_TWCSTS register field value. */
4462 #define ALT_EMAC_GMAC_DBG_TWCSTS_SET_MSK 0x00400000
4463 /* The mask used to clear the ALT_EMAC_GMAC_DBG_TWCSTS register field value. */
4464 #define ALT_EMAC_GMAC_DBG_TWCSTS_CLR_MSK 0xffbfffff
4465 /* The reset value of the ALT_EMAC_GMAC_DBG_TWCSTS register field. */
4466 #define ALT_EMAC_GMAC_DBG_TWCSTS_RESET 0x0
4467 /* Extracts the ALT_EMAC_GMAC_DBG_TWCSTS field value from a register. */
4468 #define ALT_EMAC_GMAC_DBG_TWCSTS_GET(value) (((value) & 0x00400000) >> 22)
4469 /* Produces a ALT_EMAC_GMAC_DBG_TWCSTS register field value suitable for setting the register. */
4470 #define ALT_EMAC_GMAC_DBG_TWCSTS_SET(value) (((value) << 22) & 0x00400000)
4471 
4472 /*
4473  * Field : reserved_23
4474  *
4475  * Reserved
4476  *
4477  * Field Access Macros:
4478  *
4479  */
4480 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RSVD_23 register field. */
4481 #define ALT_EMAC_GMAC_DBG_RSVD_23_LSB 23
4482 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RSVD_23 register field. */
4483 #define ALT_EMAC_GMAC_DBG_RSVD_23_MSB 23
4484 /* The width in bits of the ALT_EMAC_GMAC_DBG_RSVD_23 register field. */
4485 #define ALT_EMAC_GMAC_DBG_RSVD_23_WIDTH 1
4486 /* The mask used to set the ALT_EMAC_GMAC_DBG_RSVD_23 register field value. */
4487 #define ALT_EMAC_GMAC_DBG_RSVD_23_SET_MSK 0x00800000
4488 /* The mask used to clear the ALT_EMAC_GMAC_DBG_RSVD_23 register field value. */
4489 #define ALT_EMAC_GMAC_DBG_RSVD_23_CLR_MSK 0xff7fffff
4490 /* The reset value of the ALT_EMAC_GMAC_DBG_RSVD_23 register field. */
4491 #define ALT_EMAC_GMAC_DBG_RSVD_23_RESET 0x0
4492 /* Extracts the ALT_EMAC_GMAC_DBG_RSVD_23 field value from a register. */
4493 #define ALT_EMAC_GMAC_DBG_RSVD_23_GET(value) (((value) & 0x00800000) >> 23)
4494 /* Produces a ALT_EMAC_GMAC_DBG_RSVD_23 register field value suitable for setting the register. */
4495 #define ALT_EMAC_GMAC_DBG_RSVD_23_SET(value) (((value) << 23) & 0x00800000)
4496 
4497 /*
4498  * Field : txfsts
4499  *
4500  * MTL Tx FIFO Not Empty Status
4501  *
4502  * When high, this bit indicates that the MTL Tx FIFO is not empty and some data is
4503  * left for transmission.
4504  *
4505  * Field Enumeration Values:
4506  *
4507  * Enum | Value | Description
4508  * :---------------------------------|:------|:------------
4509  * ALT_EMAC_GMAC_DBG_TXFSTS_E_INACT | 0x0 |
4510  * ALT_EMAC_GMAC_DBG_TXFSTS_E_ACT | 0x1 |
4511  *
4512  * Field Access Macros:
4513  *
4514  */
4515 /*
4516  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXFSTS
4517  *
4518  */
4519 #define ALT_EMAC_GMAC_DBG_TXFSTS_E_INACT 0x0
4520 /*
4521  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXFSTS
4522  *
4523  */
4524 #define ALT_EMAC_GMAC_DBG_TXFSTS_E_ACT 0x1
4525 
4526 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TXFSTS register field. */
4527 #define ALT_EMAC_GMAC_DBG_TXFSTS_LSB 24
4528 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TXFSTS register field. */
4529 #define ALT_EMAC_GMAC_DBG_TXFSTS_MSB 24
4530 /* The width in bits of the ALT_EMAC_GMAC_DBG_TXFSTS register field. */
4531 #define ALT_EMAC_GMAC_DBG_TXFSTS_WIDTH 1
4532 /* The mask used to set the ALT_EMAC_GMAC_DBG_TXFSTS register field value. */
4533 #define ALT_EMAC_GMAC_DBG_TXFSTS_SET_MSK 0x01000000
4534 /* The mask used to clear the ALT_EMAC_GMAC_DBG_TXFSTS register field value. */
4535 #define ALT_EMAC_GMAC_DBG_TXFSTS_CLR_MSK 0xfeffffff
4536 /* The reset value of the ALT_EMAC_GMAC_DBG_TXFSTS register field. */
4537 #define ALT_EMAC_GMAC_DBG_TXFSTS_RESET 0x0
4538 /* Extracts the ALT_EMAC_GMAC_DBG_TXFSTS field value from a register. */
4539 #define ALT_EMAC_GMAC_DBG_TXFSTS_GET(value) (((value) & 0x01000000) >> 24)
4540 /* Produces a ALT_EMAC_GMAC_DBG_TXFSTS register field value suitable for setting the register. */
4541 #define ALT_EMAC_GMAC_DBG_TXFSTS_SET(value) (((value) << 24) & 0x01000000)
4542 
4543 /*
4544  * Field : txstsfsts
4545  *
4546  * MTL TxStatus FIFO Full Status
4547  *
4548  * When high, this bit indicates that the MTL TxStatus FIFO is full. Therefore, the
4549  * MTL cannot accept any more frames for transmission. This bit is reserved in the
4550  * GMAC-AHB and GMAC-DMA configurations.
4551  *
4552  * Field Enumeration Values:
4553  *
4554  * Enum | Value | Description
4555  * :------------------------------------|:------|:------------
4556  * ALT_EMAC_GMAC_DBG_TXSTSFSTS_E_INACT | 0x0 |
4557  * ALT_EMAC_GMAC_DBG_TXSTSFSTS_E_ACT | 0x1 |
4558  *
4559  * Field Access Macros:
4560  *
4561  */
4562 /*
4563  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXSTSFSTS
4564  *
4565  */
4566 #define ALT_EMAC_GMAC_DBG_TXSTSFSTS_E_INACT 0x0
4567 /*
4568  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXSTSFSTS
4569  *
4570  */
4571 #define ALT_EMAC_GMAC_DBG_TXSTSFSTS_E_ACT 0x1
4572 
4573 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field. */
4574 #define ALT_EMAC_GMAC_DBG_TXSTSFSTS_LSB 25
4575 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field. */
4576 #define ALT_EMAC_GMAC_DBG_TXSTSFSTS_MSB 25
4577 /* The width in bits of the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field. */
4578 #define ALT_EMAC_GMAC_DBG_TXSTSFSTS_WIDTH 1
4579 /* The mask used to set the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field value. */
4580 #define ALT_EMAC_GMAC_DBG_TXSTSFSTS_SET_MSK 0x02000000
4581 /* The mask used to clear the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field value. */
4582 #define ALT_EMAC_GMAC_DBG_TXSTSFSTS_CLR_MSK 0xfdffffff
4583 /* The reset value of the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field. */
4584 #define ALT_EMAC_GMAC_DBG_TXSTSFSTS_RESET 0x0
4585 /* Extracts the ALT_EMAC_GMAC_DBG_TXSTSFSTS field value from a register. */
4586 #define ALT_EMAC_GMAC_DBG_TXSTSFSTS_GET(value) (((value) & 0x02000000) >> 25)
4587 /* Produces a ALT_EMAC_GMAC_DBG_TXSTSFSTS register field value suitable for setting the register. */
4588 #define ALT_EMAC_GMAC_DBG_TXSTSFSTS_SET(value) (((value) << 25) & 0x02000000)
4589 
4590 /*
4591  * Field : reserved_31_26
4592  *
4593  * Reserved
4594  *
4595  * Field Access Macros:
4596  *
4597  */
4598 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RSVD_31_26 register field. */
4599 #define ALT_EMAC_GMAC_DBG_RSVD_31_26_LSB 26
4600 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RSVD_31_26 register field. */
4601 #define ALT_EMAC_GMAC_DBG_RSVD_31_26_MSB 31
4602 /* The width in bits of the ALT_EMAC_GMAC_DBG_RSVD_31_26 register field. */
4603 #define ALT_EMAC_GMAC_DBG_RSVD_31_26_WIDTH 6
4604 /* The mask used to set the ALT_EMAC_GMAC_DBG_RSVD_31_26 register field value. */
4605 #define ALT_EMAC_GMAC_DBG_RSVD_31_26_SET_MSK 0xfc000000
4606 /* The mask used to clear the ALT_EMAC_GMAC_DBG_RSVD_31_26 register field value. */
4607 #define ALT_EMAC_GMAC_DBG_RSVD_31_26_CLR_MSK 0x03ffffff
4608 /* The reset value of the ALT_EMAC_GMAC_DBG_RSVD_31_26 register field. */
4609 #define ALT_EMAC_GMAC_DBG_RSVD_31_26_RESET 0x0
4610 /* Extracts the ALT_EMAC_GMAC_DBG_RSVD_31_26 field value from a register. */
4611 #define ALT_EMAC_GMAC_DBG_RSVD_31_26_GET(value) (((value) & 0xfc000000) >> 26)
4612 /* Produces a ALT_EMAC_GMAC_DBG_RSVD_31_26 register field value suitable for setting the register. */
4613 #define ALT_EMAC_GMAC_DBG_RSVD_31_26_SET(value) (((value) << 26) & 0xfc000000)
4614 
4615 #ifndef __ASSEMBLY__
4616 /*
4617  * WARNING: The C register and register group struct declarations are provided for
4618  * convenience and illustrative purposes. They should, however, be used with
4619  * caution as the C language standard provides no guarantees about the alignment or
4620  * atomicity of device memory accesses. The recommended practice for writing
4621  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4622  * alt_write_word() functions.
4623  *
4624  * The struct declaration for register ALT_EMAC_GMAC_DBG.
4625  */
4626 struct ALT_EMAC_GMAC_DBG_s
4627 {
4628  const uint32_t rpests : 1; /* ALT_EMAC_GMAC_DBG_RPESTS */
4629  const uint32_t rfcfcsts : 2; /* ALT_EMAC_GMAC_DBG_RFCFCSTS */
4630  const uint32_t reserved_3 : 1; /* ALT_EMAC_GMAC_DBG_RSVD_3 */
4631  const uint32_t rwcsts : 1; /* ALT_EMAC_GMAC_DBG_RWCSTS */
4632  const uint32_t rrcsts : 2; /* ALT_EMAC_GMAC_DBG_RRCSTS */
4633  const uint32_t reserved_7 : 1; /* ALT_EMAC_GMAC_DBG_RSVD_7 */
4634  const uint32_t rxfsts : 2; /* ALT_EMAC_GMAC_DBG_RXFSTS */
4635  const uint32_t reserved_15_10 : 6; /* ALT_EMAC_GMAC_DBG_RSVD_15_10 */
4636  const uint32_t tpests : 1; /* ALT_EMAC_GMAC_DBG_TPESTS */
4637  const uint32_t tfcsts : 2; /* ALT_EMAC_GMAC_DBG_TFCSTS */
4638  const uint32_t txpaused : 1; /* ALT_EMAC_GMAC_DBG_TXPAUSED */
4639  const uint32_t trcsts : 2; /* ALT_EMAC_GMAC_DBG_TRCSTS */
4640  const uint32_t twcsts : 1; /* ALT_EMAC_GMAC_DBG_TWCSTS */
4641  const uint32_t reserved_23 : 1; /* ALT_EMAC_GMAC_DBG_RSVD_23 */
4642  const uint32_t txfsts : 1; /* ALT_EMAC_GMAC_DBG_TXFSTS */
4643  const uint32_t txstsfsts : 1; /* ALT_EMAC_GMAC_DBG_TXSTSFSTS */
4644  const uint32_t reserved_31_26 : 6; /* ALT_EMAC_GMAC_DBG_RSVD_31_26 */
4645 };
4646 
4647 /* The typedef declaration for register ALT_EMAC_GMAC_DBG. */
4648 typedef volatile struct ALT_EMAC_GMAC_DBG_s ALT_EMAC_GMAC_DBG_t;
4649 #endif /* __ASSEMBLY__ */
4650 
4651 /* The reset value of the ALT_EMAC_GMAC_DBG register. */
4652 #define ALT_EMAC_GMAC_DBG_RESET 0x00000000
4653 /* The byte offset of the ALT_EMAC_GMAC_DBG register from the beginning of the component. */
4654 #define ALT_EMAC_GMAC_DBG_OFST 0x24
4655 /* The address of the ALT_EMAC_GMAC_DBG register. */
4656 #define ALT_EMAC_GMAC_DBG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_DBG_OFST))
4657 
4658 /*
4659  * Register : gmacgrp_lpi_control_status
4660  *
4661  * <b> Register 12 (LPI Control and Status Register) </b>
4662  *
4663  * The LPI Control and Status Register controls the LPI functions and provides the
4664  * LPI interrupt status. The status bits are cleared when this register is read.
4665  * This register is present only when you select the Energy Efficient Ethernet
4666  * feature during core configuration.
4667  *
4668  * Register Layout
4669  *
4670  * Bits | Access | Reset | Description
4671  * :--------|:-------|:------|:--------------------------------------
4672  * [0] | R | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN
4673  * [1] | R | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX
4674  * [2] | R | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN
4675  * [3] | R | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX
4676  * [7:4] | R | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4
4677  * [8] | R | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST
4678  * [9] | R | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST
4679  * [15:10] | R | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10
4680  * [16] | RW | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN
4681  * [17] | RW | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_PLS
4682  * [18] | R | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN
4683  * [19] | RW | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA
4684  * [31:20] | R | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20
4685  *
4686  */
4687 /*
4688  * Field : tlpien
4689  *
4690  * Transmit LPI Entry
4691  *
4692  * When set, this bit indicates that the MAC Transmitter has entered the LPI state
4693  * because of the setting of the LPIEN bit. This bit is cleared by a read into this
4694  * register.
4695  *
4696  * Field Enumeration Values:
4697  *
4698  * Enum | Value | Description
4699  * :------------------------------------------|:------|:------------
4700  * ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_INACT | 0x0 |
4701  * ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_ACT | 0x1 |
4702  *
4703  * Field Access Macros:
4704  *
4705  */
4706 /*
4707  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN
4708  *
4709  */
4710 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_INACT 0x0
4711 /*
4712  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN
4713  *
4714  */
4715 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_ACT 0x1
4716 
4717 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field. */
4718 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_LSB 0
4719 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field. */
4720 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_MSB 0
4721 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field. */
4722 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_WIDTH 1
4723 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field value. */
4724 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_SET_MSK 0x00000001
4725 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field value. */
4726 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_CLR_MSK 0xfffffffe
4727 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field. */
4728 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_RESET 0x0
4729 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN field value from a register. */
4730 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_GET(value) (((value) & 0x00000001) >> 0)
4731 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field value suitable for setting the register. */
4732 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_SET(value) (((value) << 0) & 0x00000001)
4733 
4734 /*
4735  * Field : tlpiex
4736  *
4737  * Transmit LPI Exit
4738  *
4739  * When set, this bit indicates that the MAC transmitter has exited the LPI state
4740  * after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This
4741  * bit is cleared by a read into this register.
4742  *
4743  * Field Enumeration Values:
4744  *
4745  * Enum | Value | Description
4746  * :------------------------------------------|:------|:------------
4747  * ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_INACT | 0x0 |
4748  * ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_ACT | 0x1 |
4749  *
4750  * Field Access Macros:
4751  *
4752  */
4753 /*
4754  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX
4755  *
4756  */
4757 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_INACT 0x0
4758 /*
4759  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX
4760  *
4761  */
4762 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_ACT 0x1
4763 
4764 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field. */
4765 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_LSB 1
4766 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field. */
4767 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_MSB 1
4768 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field. */
4769 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_WIDTH 1
4770 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field value. */
4771 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_SET_MSK 0x00000002
4772 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field value. */
4773 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_CLR_MSK 0xfffffffd
4774 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field. */
4775 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_RESET 0x0
4776 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX field value from a register. */
4777 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_GET(value) (((value) & 0x00000002) >> 1)
4778 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field value suitable for setting the register. */
4779 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_SET(value) (((value) << 1) & 0x00000002)
4780 
4781 /*
4782  * Field : rlpien
4783  *
4784  * Receive LPI Entry
4785  *
4786  * When set, this bit indicates that the MAC Receiver has received an LPI pattern
4787  * and entered the LPI state. This bit is cleared by a read into this register.
4788  *
4789  * Note:
4790  *
4791  * This bit may not get set if the MAC stops receiving the LPI pattern for a very
4792  * short duration, such as, less than 3 clock cycles of CSR clock.
4793  *
4794  * Field Enumeration Values:
4795  *
4796  * Enum | Value | Description
4797  * :------------------------------------------|:------|:------------
4798  * ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_INACT | 0x0 |
4799  * ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_ACT | 0x1 |
4800  *
4801  * Field Access Macros:
4802  *
4803  */
4804 /*
4805  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN
4806  *
4807  */
4808 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_INACT 0x0
4809 /*
4810  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN
4811  *
4812  */
4813 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_ACT 0x1
4814 
4815 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field. */
4816 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_LSB 2
4817 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field. */
4818 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_MSB 2
4819 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field. */
4820 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_WIDTH 1
4821 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field value. */
4822 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_SET_MSK 0x00000004
4823 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field value. */
4824 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_CLR_MSK 0xfffffffb
4825 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field. */
4826 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_RESET 0x0
4827 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN field value from a register. */
4828 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_GET(value) (((value) & 0x00000004) >> 2)
4829 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field value suitable for setting the register. */
4830 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_SET(value) (((value) << 2) & 0x00000004)
4831 
4832 /*
4833  * Field : rlpiex
4834  *
4835  * Receive LPI Exit
4836  *
4837  * When set, this bit indicates that the MAC Receiver has stopped receiving the LPI
4838  * pattern on the GMII or MII interface, exited the LPI state, and resumed the
4839  * normal reception. This bit is cleared by a read into this register.
4840  *
4841  * Note:
4842  *
4843  * This bit may not get set if the MAC stops receiving the LPI pattern for a very
4844  * short duration, such as, less than 3 clock cycles of CSR clock.
4845  *
4846  * Field Enumeration Values:
4847  *
4848  * Enum | Value | Description
4849  * :------------------------------------------|:------|:------------
4850  * ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_INACT | 0x0 |
4851  * ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_ACT | 0x1 |
4852  *
4853  * Field Access Macros:
4854  *
4855  */
4856 /*
4857  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX
4858  *
4859  */
4860 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_INACT 0x0
4861 /*
4862  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX
4863  *
4864  */
4865 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_ACT 0x1
4866 
4867 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field. */
4868 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_LSB 3
4869 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field. */
4870 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_MSB 3
4871 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field. */
4872 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_WIDTH 1
4873 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field value. */
4874 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_SET_MSK 0x00000008
4875 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field value. */
4876 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_CLR_MSK 0xfffffff7
4877 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field. */
4878 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_RESET 0x0
4879 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX field value from a register. */
4880 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_GET(value) (((value) & 0x00000008) >> 3)
4881 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field value suitable for setting the register. */
4882 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_SET(value) (((value) << 3) & 0x00000008)
4883 
4884 /*
4885  * Field : reserved_7_4
4886  *
4887  * Reserved
4888  *
4889  * Field Access Macros:
4890  *
4891  */
4892 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4 register field. */
4893 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_LSB 4
4894 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4 register field. */
4895 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_MSB 7
4896 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4 register field. */
4897 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_WIDTH 4
4898 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4 register field value. */
4899 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_SET_MSK 0x000000f0
4900 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4 register field value. */
4901 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_CLR_MSK 0xffffff0f
4902 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4 register field. */
4903 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_RESET 0x0
4904 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4 field value from a register. */
4905 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_GET(value) (((value) & 0x000000f0) >> 4)
4906 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4 register field value suitable for setting the register. */
4907 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_SET(value) (((value) << 4) & 0x000000f0)
4908 
4909 /*
4910  * Field : tlpist
4911  *
4912  * Transmit LPI State
4913  *
4914  * When set, this bit indicates that the MAC is transmitting the LPI pattern on the
4915  * GMII or MII interface.
4916  *
4917  * Field Enumeration Values:
4918  *
4919  * Enum | Value | Description
4920  * :------------------------------------------|:------|:------------
4921  * ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_INACT | 0x0 |
4922  * ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_ACT | 0x1 |
4923  *
4924  * Field Access Macros:
4925  *
4926  */
4927 /*
4928  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST
4929  *
4930  */
4931 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_INACT 0x0
4932 /*
4933  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST
4934  *
4935  */
4936 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_ACT 0x1
4937 
4938 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field. */
4939 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_LSB 8
4940 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field. */
4941 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_MSB 8
4942 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field. */
4943 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_WIDTH 1
4944 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field value. */
4945 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_SET_MSK 0x00000100
4946 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field value. */
4947 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_CLR_MSK 0xfffffeff
4948 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field. */
4949 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_RESET 0x0
4950 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST field value from a register. */
4951 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_GET(value) (((value) & 0x00000100) >> 8)
4952 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field value suitable for setting the register. */
4953 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_SET(value) (((value) << 8) & 0x00000100)
4954 
4955 /*
4956  * Field : rlpist
4957  *
4958  * Receive LPI State
4959  *
4960  * When set, this bit indicates that the MAC is receiving the LPI pattern on the
4961  * GMII or MII interface.
4962  *
4963  * Field Enumeration Values:
4964  *
4965  * Enum | Value | Description
4966  * :------------------------------------------|:------|:------------
4967  * ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_INACT | 0x0 |
4968  * ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_ACT | 0x1 |
4969  *
4970  * Field Access Macros:
4971  *
4972  */
4973 /*
4974  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST
4975  *
4976  */
4977 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_INACT 0x0
4978 /*
4979  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST
4980  *
4981  */
4982 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_ACT 0x1
4983 
4984 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field. */
4985 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_LSB 9
4986 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field. */
4987 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_MSB 9
4988 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field. */
4989 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_WIDTH 1
4990 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field value. */
4991 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_SET_MSK 0x00000200
4992 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field value. */
4993 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_CLR_MSK 0xfffffdff
4994 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field. */
4995 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_RESET 0x0
4996 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST field value from a register. */
4997 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_GET(value) (((value) & 0x00000200) >> 9)
4998 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field value suitable for setting the register. */
4999 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_SET(value) (((value) << 9) & 0x00000200)
5000 
5001 /*
5002  * Field : reserved_15_10
5003  *
5004  * Reserved
5005  *
5006  * Field Access Macros:
5007  *
5008  */
5009 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10 register field. */
5010 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_LSB 10
5011 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10 register field. */
5012 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_MSB 15
5013 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10 register field. */
5014 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_WIDTH 6
5015 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10 register field value. */
5016 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_SET_MSK 0x0000fc00
5017 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10 register field value. */
5018 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_CLR_MSK 0xffff03ff
5019 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10 register field. */
5020 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_RESET 0x0
5021 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10 field value from a register. */
5022 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_GET(value) (((value) & 0x0000fc00) >> 10)
5023 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10 register field value suitable for setting the register. */
5024 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_SET(value) (((value) << 10) & 0x0000fc00)
5025 
5026 /*
5027  * Field : lpien
5028  *
5029  * LPI Enable
5030  *
5031  * When set, this bit instructs the MAC Transmitter to enter the LPI state. When
5032  * reset, this bit instructs the MAC to exit the LPI state and resume normal
5033  * transmission.
5034  *
5035  * This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state
5036  * because of the arrival of a new packet for transmission.
5037  *
5038  * Field Enumeration Values:
5039  *
5040  * Enum | Value | Description
5041  * :----------------------------------------|:------|:------------
5042  * ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_DISD | 0x0 |
5043  * ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_END | 0x1 |
5044  *
5045  * Field Access Macros:
5046  *
5047  */
5048 /*
5049  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN
5050  *
5051  */
5052 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_DISD 0x0
5053 /*
5054  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN
5055  *
5056  */
5057 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_END 0x1
5058 
5059 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field. */
5060 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_LSB 16
5061 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field. */
5062 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_MSB 16
5063 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field. */
5064 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_WIDTH 1
5065 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field value. */
5066 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_SET_MSK 0x00010000
5067 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field value. */
5068 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_CLR_MSK 0xfffeffff
5069 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field. */
5070 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_RESET 0x0
5071 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN field value from a register. */
5072 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_GET(value) (((value) & 0x00010000) >> 16)
5073 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field value suitable for setting the register. */
5074 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_SET(value) (((value) << 16) & 0x00010000)
5075 
5076 /*
5077  * Field : pls
5078  *
5079  * PHY Link Status
5080  *
5081  * This bit indicates the link status of the PHY. The MAC Transmitter asserts the
5082  * LPI pattern only when the link status is up (okay) at least for the time
5083  * indicated by the LPI LS TIMER.
5084  *
5085  * When set, the link is considered to be okay (up) and when reset, the link is
5086  * considered to be down.
5087  *
5088  * Field Enumeration Values:
5089  *
5090  * Enum | Value | Description
5091  * :--------------------------------------|:------|:------------
5092  * ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_DISD | 0x0 |
5093  * ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_END | 0x1 |
5094  *
5095  * Field Access Macros:
5096  *
5097  */
5098 /*
5099  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLS
5100  *
5101  */
5102 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_DISD 0x0
5103 /*
5104  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLS
5105  *
5106  */
5107 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_END 0x1
5108 
5109 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field. */
5110 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_LSB 17
5111 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field. */
5112 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_MSB 17
5113 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field. */
5114 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_WIDTH 1
5115 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field value. */
5116 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_SET_MSK 0x00020000
5117 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field value. */
5118 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_CLR_MSK 0xfffdffff
5119 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field. */
5120 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_RESET 0x0
5121 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS field value from a register. */
5122 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_GET(value) (((value) & 0x00020000) >> 17)
5123 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field value suitable for setting the register. */
5124 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_SET(value) (((value) << 17) & 0x00020000)
5125 
5126 /*
5127  * Field : plsen
5128  *
5129  * PHY Link Status Enable
5130  *
5131  * This bit enables the link status received on the RGMII, SGMII, or SMII receive
5132  * paths to be used for activating the LPI LS TIMER.
5133  *
5134  * When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII
5135  * Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. When cleared,
5136  * the MAC ignores the link-status bits of Register 54 and takes only the PLS bit.
5137  *
5138  * This bit is RO and reserved if you have not selected the RGMII, SGMII, or SMII
5139  * PHY interface.
5140  *
5141  * Field Enumeration Values:
5142  *
5143  * Enum | Value | Description
5144  * :----------------------------------------|:------|:------------
5145  * ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_DISD | 0x0 |
5146  * ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_END | 0x1 |
5147  *
5148  * Field Access Macros:
5149  *
5150  */
5151 /*
5152  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN
5153  *
5154  */
5155 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_DISD 0x0
5156 /*
5157  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN
5158  *
5159  */
5160 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_END 0x1
5161 
5162 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field. */
5163 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_LSB 18
5164 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field. */
5165 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_MSB 18
5166 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field. */
5167 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_WIDTH 1
5168 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field value. */
5169 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_SET_MSK 0x00040000
5170 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field value. */
5171 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_CLR_MSK 0xfffbffff
5172 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field. */
5173 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_RESET 0x0
5174 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN field value from a register. */
5175 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_GET(value) (((value) & 0x00040000) >> 18)
5176 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field value suitable for setting the register. */
5177 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_SET(value) (((value) << 18) & 0x00040000)
5178 
5179 /*
5180  * Field : lpitxa
5181  *
5182  * LPI TX Automate
5183  *
5184  * This bit controls the behavior of the MAC when it is entering or coming out of
5185  * the LPI mode on the transmit side. This bit is not functional in the GMAC-CORE
5186  * configuration in which the Tx clock gating is done during the LPI mode.
5187  *
5188  * If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only
5189  * after all outstanding frames (in the core) and pending frames (in the
5190  * application interface) have been transmitted. The MAC comes out of the LPI mode
5191  * when the application sends any frame for transmission or the application issues
5192  * a TX FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit
5193  * when it exits the LPI state. If TX FIFO Flush is set, in Bit 20 of Register 6
5194  * (Operation Mode Register), when the MAC is in the LPI mode, the MAC exits the
5195  * LPI mode.
5196  *
5197  * When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it
5198  * is entering or coming out of the LPI mode.
5199  *
5200  * Field Enumeration Values:
5201  *
5202  * Enum | Value | Description
5203  * :-----------------------------------------|:------|:------------
5204  * ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_DISD | 0x0 |
5205  * ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_END | 0x1 |
5206  *
5207  * Field Access Macros:
5208  *
5209  */
5210 /*
5211  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA
5212  *
5213  */
5214 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_DISD 0x0
5215 /*
5216  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA
5217  *
5218  */
5219 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_END 0x1
5220 
5221 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field. */
5222 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_LSB 19
5223 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field. */
5224 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_MSB 19
5225 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field. */
5226 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_WIDTH 1
5227 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field value. */
5228 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_SET_MSK 0x00080000
5229 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field value. */
5230 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_CLR_MSK 0xfff7ffff
5231 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field. */
5232 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_RESET 0x0
5233 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA field value from a register. */
5234 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_GET(value) (((value) & 0x00080000) >> 19)
5235 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field value suitable for setting the register. */
5236 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_SET(value) (((value) << 19) & 0x00080000)
5237 
5238 /*
5239  * Field : reserved_31_20
5240  *
5241  * Reserved
5242  *
5243  * Field Access Macros:
5244  *
5245  */
5246 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20 register field. */
5247 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_LSB 20
5248 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20 register field. */
5249 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_MSB 31
5250 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20 register field. */
5251 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_WIDTH 12
5252 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20 register field value. */
5253 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_SET_MSK 0xfff00000
5254 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20 register field value. */
5255 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_CLR_MSK 0x000fffff
5256 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20 register field. */
5257 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_RESET 0x0
5258 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20 field value from a register. */
5259 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_GET(value) (((value) & 0xfff00000) >> 20)
5260 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20 register field value suitable for setting the register. */
5261 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_SET(value) (((value) << 20) & 0xfff00000)
5262 
5263 #ifndef __ASSEMBLY__
5264 /*
5265  * WARNING: The C register and register group struct declarations are provided for
5266  * convenience and illustrative purposes. They should, however, be used with
5267  * caution as the C language standard provides no guarantees about the alignment or
5268  * atomicity of device memory accesses. The recommended practice for writing
5269  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5270  * alt_write_word() functions.
5271  *
5272  * The struct declaration for register ALT_EMAC_GMAC_LPI_CTL_STAT.
5273  */
5274 struct ALT_EMAC_GMAC_LPI_CTL_STAT_s
5275 {
5276  const uint32_t tlpien : 1; /* ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN */
5277  const uint32_t tlpiex : 1; /* ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX */
5278  const uint32_t rlpien : 1; /* ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN */
5279  const uint32_t rlpiex : 1; /* ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX */
5280  const uint32_t reserved_7_4 : 4; /* ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4 */
5281  const uint32_t tlpist : 1; /* ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST */
5282  const uint32_t rlpist : 1; /* ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST */
5283  const uint32_t reserved_15_10 : 6; /* ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10 */
5284  uint32_t lpien : 1; /* ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN */
5285  uint32_t pls : 1; /* ALT_EMAC_GMAC_LPI_CTL_STAT_PLS */
5286  const uint32_t plsen : 1; /* ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN */
5287  uint32_t lpitxa : 1; /* ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA */
5288  const uint32_t reserved_31_20 : 12; /* ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20 */
5289 };
5290 
5291 /* The typedef declaration for register ALT_EMAC_GMAC_LPI_CTL_STAT. */
5292 typedef volatile struct ALT_EMAC_GMAC_LPI_CTL_STAT_s ALT_EMAC_GMAC_LPI_CTL_STAT_t;
5293 #endif /* __ASSEMBLY__ */
5294 
5295 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT register. */
5296 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RESET 0x00000000
5297 /* The byte offset of the ALT_EMAC_GMAC_LPI_CTL_STAT register from the beginning of the component. */
5298 #define ALT_EMAC_GMAC_LPI_CTL_STAT_OFST 0x30
5299 /* The address of the ALT_EMAC_GMAC_LPI_CTL_STAT register. */
5300 #define ALT_EMAC_GMAC_LPI_CTL_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LPI_CTL_STAT_OFST))
5301 
5302 /*
5303  * Register : gmacgrp_lpi_timers_control
5304  *
5305  * <b> Register 13 (LPI Timers Control Register) </b>
5306  *
5307  * The LPI Timers Control register controls the timeout values in the LPI states.
5308  * It specifies the time for which the MAC transmits the LPI pattern and also the
5309  * time for which the MAC waits before resuming the normal transmission. This
5310  * register is present only when you select the Energy Efficient Ethernet feature
5311  * during core configuration.
5312  *
5313  * Register Layout
5314  *
5315  * Bits | Access | Reset | Description
5316  * :--------|:-------|:------|:--------------------------------------
5317  * [15:0] | RW | 0x0 | ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT
5318  * [25:16] | RW | 0x3e8 | ALT_EMAC_GMAC_LPI_TMRS_CTL_LST
5319  * [31:26] | R | 0x0 | ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26
5320  *
5321  */
5322 /*
5323  * Field : twt
5324  *
5325  * LPI TW Timer
5326  *
5327  * This field specifies the minimum time (in microseconds) for which the MAC waits
5328  * after it stops transmitting the LPI pattern to the PHY and before it resumes the
5329  * normal transmission. The TLPIEX status bit is set after the expiry of this
5330  * timer.
5331  *
5332  * Field Access Macros:
5333  *
5334  */
5335 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field. */
5336 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_LSB 0
5337 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field. */
5338 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_MSB 15
5339 /* The width in bits of the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field. */
5340 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_WIDTH 16
5341 /* The mask used to set the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field value. */
5342 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_SET_MSK 0x0000ffff
5343 /* The mask used to clear the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field value. */
5344 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_CLR_MSK 0xffff0000
5345 /* The reset value of the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field. */
5346 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_RESET 0x0
5347 /* Extracts the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT field value from a register. */
5348 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_GET(value) (((value) & 0x0000ffff) >> 0)
5349 /* Produces a ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field value suitable for setting the register. */
5350 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_SET(value) (((value) << 0) & 0x0000ffff)
5351 
5352 /*
5353  * Field : lst
5354  *
5355  * LPI LS Timer
5356  *
5357  * This field specifies the minimum time (in milliseconds) for which the link
5358  * status from the PHY should be up (OKAY) before the LPI pattern can be
5359  * transmitted to the PHY. The MAC does not transmit the LPI pattern even when the
5360  * LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count.
5361  * The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE
5362  * standard.
5363  *
5364  * Field Access Macros:
5365  *
5366  */
5367 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field. */
5368 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_LSB 16
5369 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field. */
5370 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_MSB 25
5371 /* The width in bits of the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field. */
5372 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_WIDTH 10
5373 /* The mask used to set the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field value. */
5374 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_SET_MSK 0x03ff0000
5375 /* The mask used to clear the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field value. */
5376 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_CLR_MSK 0xfc00ffff
5377 /* The reset value of the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field. */
5378 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_RESET 0x3e8
5379 /* Extracts the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST field value from a register. */
5380 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_GET(value) (((value) & 0x03ff0000) >> 16)
5381 /* Produces a ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field value suitable for setting the register. */
5382 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_SET(value) (((value) << 16) & 0x03ff0000)
5383 
5384 /*
5385  * Field : reserved_31_26
5386  *
5387  * Reserved
5388  *
5389  * Field Access Macros:
5390  *
5391  */
5392 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26 register field. */
5393 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_LSB 26
5394 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26 register field. */
5395 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_MSB 31
5396 /* The width in bits of the ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26 register field. */
5397 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_WIDTH 6
5398 /* The mask used to set the ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26 register field value. */
5399 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_SET_MSK 0xfc000000
5400 /* The mask used to clear the ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26 register field value. */
5401 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_CLR_MSK 0x03ffffff
5402 /* The reset value of the ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26 register field. */
5403 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_RESET 0x0
5404 /* Extracts the ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26 field value from a register. */
5405 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_GET(value) (((value) & 0xfc000000) >> 26)
5406 /* Produces a ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26 register field value suitable for setting the register. */
5407 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_SET(value) (((value) << 26) & 0xfc000000)
5408 
5409 #ifndef __ASSEMBLY__
5410 /*
5411  * WARNING: The C register and register group struct declarations are provided for
5412  * convenience and illustrative purposes. They should, however, be used with
5413  * caution as the C language standard provides no guarantees about the alignment or
5414  * atomicity of device memory accesses. The recommended practice for writing
5415  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5416  * alt_write_word() functions.
5417  *
5418  * The struct declaration for register ALT_EMAC_GMAC_LPI_TMRS_CTL.
5419  */
5420 struct ALT_EMAC_GMAC_LPI_TMRS_CTL_s
5421 {
5422  uint32_t twt : 16; /* ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT */
5423  uint32_t lst : 10; /* ALT_EMAC_GMAC_LPI_TMRS_CTL_LST */
5424  const uint32_t reserved_31_26 : 6; /* ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26 */
5425 };
5426 
5427 /* The typedef declaration for register ALT_EMAC_GMAC_LPI_TMRS_CTL. */
5428 typedef volatile struct ALT_EMAC_GMAC_LPI_TMRS_CTL_s ALT_EMAC_GMAC_LPI_TMRS_CTL_t;
5429 #endif /* __ASSEMBLY__ */
5430 
5431 /* The reset value of the ALT_EMAC_GMAC_LPI_TMRS_CTL register. */
5432 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_RESET 0x03e80000
5433 /* The byte offset of the ALT_EMAC_GMAC_LPI_TMRS_CTL register from the beginning of the component. */
5434 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_OFST 0x34
5435 /* The address of the ALT_EMAC_GMAC_LPI_TMRS_CTL register. */
5436 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LPI_TMRS_CTL_OFST))
5437 
5438 /*
5439  * Register : gmacgrp_interrupt_status
5440  *
5441  * <b> Register 14 (Interrupt Register) </b>
5442  *
5443  * The Interrupt Status register identifies the events in the MAC that can generate
5444  * interrupt. All interrupt events are generated only when the corresponding
5445  * optional feature is selected during core configuration and enabled during
5446  * operation. Therefore, these bits are reserved when the corresponding features
5447  * are not present in the core.
5448  *
5449  * Register Layout
5450  *
5451  * Bits | Access | Reset | Description
5452  * :--------|:-------|:------|:----------------------------------
5453  * [0] | R | 0x0 | ALT_EMAC_GMAC_INT_STAT_RGSMIIIS
5454  * [1] | R | 0x0 | ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS
5455  * [2] | R | 0x0 | ALT_EMAC_GMAC_INT_STAT_PCSANCIS
5456  * [3] | R | 0x0 | ALT_EMAC_GMAC_INT_STAT_PMTIS
5457  * [4] | R | 0x0 | ALT_EMAC_GMAC_INT_STAT_MMCIS
5458  * [5] | R | 0x0 | ALT_EMAC_GMAC_INT_STAT_MMCRXIS
5459  * [6] | R | 0x0 | ALT_EMAC_GMAC_INT_STAT_MMCTXIS
5460  * [7] | R | 0x0 | ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS
5461  * [8] | R | 0x0 | ALT_EMAC_GMAC_INT_STAT_RSVD_8
5462  * [9] | R | 0x0 | ALT_EMAC_GMAC_INT_STAT_TSIS
5463  * [10] | R | 0x0 | ALT_EMAC_GMAC_INT_STAT_LPIIS
5464  * [11] | R | 0x0 | ALT_EMAC_GMAC_INT_STAT_GPIIS
5465  * [31:12] | R | 0x0 | ALT_EMAC_GMAC_INT_STAT_RSVD_31_12
5466  *
5467  */
5468 /*
5469  * Field : rgsmiiis
5470  *
5471  * RGMII or SMII Interrupt Status
5472  *
5473  * This bit is set because of any change in value of the Link Status of RGMII or
5474  * SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Status Register)). This
5475  * bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Status
5476  * Register.
5477  *
5478  * This bit is valid only when you select the optional RGMII or SMII PHY interface
5479  * during core configuration and operation.
5480  *
5481  * Field Enumeration Values:
5482  *
5483  * Enum | Value | Description
5484  * :----------------------------------------|:------|:------------
5485  * ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_E_INACT | 0x0 |
5486  * ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_E_ACT | 0x1 |
5487  *
5488  * Field Access Macros:
5489  *
5490  */
5491 /*
5492  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_RGSMIIIS
5493  *
5494  */
5495 #define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_E_INACT 0x0
5496 /*
5497  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_RGSMIIIS
5498  *
5499  */
5500 #define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_E_ACT 0x1
5501 
5502 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field. */
5503 #define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_LSB 0
5504 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field. */
5505 #define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_MSB 0
5506 /* The width in bits of the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field. */
5507 #define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_WIDTH 1
5508 /* The mask used to set the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field value. */
5509 #define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_SET_MSK 0x00000001
5510 /* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field value. */
5511 #define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_CLR_MSK 0xfffffffe
5512 /* The reset value of the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field. */
5513 #define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_RESET 0x0
5514 /* Extracts the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS field value from a register. */
5515 #define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_GET(value) (((value) & 0x00000001) >> 0)
5516 /* Produces a ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field value suitable for setting the register. */
5517 #define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_SET(value) (((value) << 0) & 0x00000001)
5518 
5519 /*
5520  * Field : pcslchgis
5521  *
5522  * PCS Link Status Changed
5523  *
5524  * This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII
5525  * PHY interface (Bit 2 in Register 49 (AN Status Register)). This bit is cleared
5526  * when you perform a read operation on the AN Status register.
5527  *
5528  * This bit is valid only when you select the optional TBI, RTBI, or SGMII PHY
5529  * interface during core configuration and operation.
5530  *
5531  * Field Access Macros:
5532  *
5533  */
5534 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field. */
5535 #define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_LSB 1
5536 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field. */
5537 #define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_MSB 1
5538 /* The width in bits of the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field. */
5539 #define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_WIDTH 1
5540 /* The mask used to set the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field value. */
5541 #define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_SET_MSK 0x00000002
5542 /* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field value. */
5543 #define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_CLR_MSK 0xfffffffd
5544 /* The reset value of the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field. */
5545 #define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_RESET 0x0
5546 /* Extracts the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS field value from a register. */
5547 #define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_GET(value) (((value) & 0x00000002) >> 1)
5548 /* Produces a ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field value suitable for setting the register. */
5549 #define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_SET(value) (((value) << 1) & 0x00000002)
5550 
5551 /*
5552  * Field : pcsancis
5553  *
5554  * PCS Auto-Negotiation Complete
5555  *
5556  * This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or
5557  * SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). This bit is
5558  * cleared when you perform a read operation to the AN Status register.
5559  *
5560  * This bit is valid only when you select the optional TBI, RTBI, or SGMII PHY
5561  * interface during core configuration and operation.
5562  *
5563  * Field Access Macros:
5564  *
5565  */
5566 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field. */
5567 #define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_LSB 2
5568 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field. */
5569 #define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_MSB 2
5570 /* The width in bits of the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field. */
5571 #define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_WIDTH 1
5572 /* The mask used to set the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field value. */
5573 #define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_SET_MSK 0x00000004
5574 /* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field value. */
5575 #define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_CLR_MSK 0xfffffffb
5576 /* The reset value of the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field. */
5577 #define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_RESET 0x0
5578 /* Extracts the ALT_EMAC_GMAC_INT_STAT_PCSANCIS field value from a register. */
5579 #define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_GET(value) (((value) & 0x00000004) >> 2)
5580 /* Produces a ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field value suitable for setting the register. */
5581 #define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_SET(value) (((value) << 2) & 0x00000004)
5582 
5583 /*
5584  * Field : pmtis
5585  *
5586  * PMT Interrupt Status
5587  *
5588  * This bit is set when a Magic packet or Wake-on-LAN frame is received in the
5589  * power-down mode (see Bits 5 and 6 in the PMT Control and Status Register). This
5590  * bit is cleared when both Bits[6:5] are cleared because of a read operation to
5591  * the PMT Control and Status register.
5592  *
5593  * This bit is valid only when you select the optional PMT module during core
5594  * configuration.
5595  *
5596  * Field Access Macros:
5597  *
5598  */
5599 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_PMTIS register field. */
5600 #define ALT_EMAC_GMAC_INT_STAT_PMTIS_LSB 3
5601 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_PMTIS register field. */
5602 #define ALT_EMAC_GMAC_INT_STAT_PMTIS_MSB 3
5603 /* The width in bits of the ALT_EMAC_GMAC_INT_STAT_PMTIS register field. */
5604 #define ALT_EMAC_GMAC_INT_STAT_PMTIS_WIDTH 1
5605 /* The mask used to set the ALT_EMAC_GMAC_INT_STAT_PMTIS register field value. */
5606 #define ALT_EMAC_GMAC_INT_STAT_PMTIS_SET_MSK 0x00000008
5607 /* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_PMTIS register field value. */
5608 #define ALT_EMAC_GMAC_INT_STAT_PMTIS_CLR_MSK 0xfffffff7
5609 /* The reset value of the ALT_EMAC_GMAC_INT_STAT_PMTIS register field. */
5610 #define ALT_EMAC_GMAC_INT_STAT_PMTIS_RESET 0x0
5611 /* Extracts the ALT_EMAC_GMAC_INT_STAT_PMTIS field value from a register. */
5612 #define ALT_EMAC_GMAC_INT_STAT_PMTIS_GET(value) (((value) & 0x00000008) >> 3)
5613 /* Produces a ALT_EMAC_GMAC_INT_STAT_PMTIS register field value suitable for setting the register. */
5614 #define ALT_EMAC_GMAC_INT_STAT_PMTIS_SET(value) (((value) << 3) & 0x00000008)
5615 
5616 /*
5617  * Field : mmcis
5618  *
5619  * MMC Interrupt Status
5620  *
5621  * This bit is set high when any of the Bits [7:5] is set high and cleared only
5622  * when all of these bits are low.
5623  *
5624  * This bit is valid only when you select the optional MMC module during core
5625  * configuration.
5626  *
5627  * Field Enumeration Values:
5628  *
5629  * Enum | Value | Description
5630  * :-------------------------------------|:------|:------------
5631  * ALT_EMAC_GMAC_INT_STAT_MMCIS_E_INACT | 0x0 |
5632  * ALT_EMAC_GMAC_INT_STAT_MMCIS_E_ACT | 0x1 |
5633  *
5634  * Field Access Macros:
5635  *
5636  */
5637 /*
5638  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCIS
5639  *
5640  */
5641 #define ALT_EMAC_GMAC_INT_STAT_MMCIS_E_INACT 0x0
5642 /*
5643  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCIS
5644  *
5645  */
5646 #define ALT_EMAC_GMAC_INT_STAT_MMCIS_E_ACT 0x1
5647 
5648 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCIS register field. */
5649 #define ALT_EMAC_GMAC_INT_STAT_MMCIS_LSB 4
5650 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCIS register field. */
5651 #define ALT_EMAC_GMAC_INT_STAT_MMCIS_MSB 4
5652 /* The width in bits of the ALT_EMAC_GMAC_INT_STAT_MMCIS register field. */
5653 #define ALT_EMAC_GMAC_INT_STAT_MMCIS_WIDTH 1
5654 /* The mask used to set the ALT_EMAC_GMAC_INT_STAT_MMCIS register field value. */
5655 #define ALT_EMAC_GMAC_INT_STAT_MMCIS_SET_MSK 0x00000010
5656 /* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_MMCIS register field value. */
5657 #define ALT_EMAC_GMAC_INT_STAT_MMCIS_CLR_MSK 0xffffffef
5658 /* The reset value of the ALT_EMAC_GMAC_INT_STAT_MMCIS register field. */
5659 #define ALT_EMAC_GMAC_INT_STAT_MMCIS_RESET 0x0
5660 /* Extracts the ALT_EMAC_GMAC_INT_STAT_MMCIS field value from a register. */
5661 #define ALT_EMAC_GMAC_INT_STAT_MMCIS_GET(value) (((value) & 0x00000010) >> 4)
5662 /* Produces a ALT_EMAC_GMAC_INT_STAT_MMCIS register field value suitable for setting the register. */
5663 #define ALT_EMAC_GMAC_INT_STAT_MMCIS_SET(value) (((value) << 4) & 0x00000010)
5664 
5665 /*
5666  * Field : mmcrxis
5667  *
5668  * MMC Receive Interrupt Status
5669  *
5670  * This bit is set high when an interrupt is generated in the MMC Receive Interrupt
5671  * Register. This bit is cleared when all the bits in this interrupt register are
5672  * cleared.
5673  *
5674  * This bit is valid only when you select the optional MMC module during core
5675  * configuration.
5676  *
5677  * Field Enumeration Values:
5678  *
5679  * Enum | Value | Description
5680  * :--------------------------------------|:------|:------------
5681  * ALT_EMAC_GMAC_INT_STAT_MMCRXIS_E_DISD | 0x0 |
5682  * ALT_EMAC_GMAC_INT_STAT_MMCRXIS_E_END | 0x1 |
5683  *
5684  * Field Access Macros:
5685  *
5686  */
5687 /*
5688  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCRXIS
5689  *
5690  */
5691 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_E_DISD 0x0
5692 /*
5693  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCRXIS
5694  *
5695  */
5696 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_E_END 0x1
5697 
5698 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field. */
5699 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_LSB 5
5700 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field. */
5701 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_MSB 5
5702 /* The width in bits of the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field. */
5703 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_WIDTH 1
5704 /* The mask used to set the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field value. */
5705 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_SET_MSK 0x00000020
5706 /* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field value. */
5707 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_CLR_MSK 0xffffffdf
5708 /* The reset value of the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field. */
5709 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_RESET 0x0
5710 /* Extracts the ALT_EMAC_GMAC_INT_STAT_MMCRXIS field value from a register. */
5711 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_GET(value) (((value) & 0x00000020) >> 5)
5712 /* Produces a ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field value suitable for setting the register. */
5713 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_SET(value) (((value) << 5) & 0x00000020)
5714 
5715 /*
5716  * Field : mmctxis
5717  *
5718  * MMC Transmit Interrupt Status
5719  *
5720  * This bit is set high when an interrupt is generated in the MMC Transmit
5721  * Interrupt Register. This bit is cleared when all the bits in this interrupt
5722  * register are cleared.
5723  *
5724  * This bit is valid only when you select the optional MMC module during core
5725  * configuration.
5726  *
5727  * Field Enumeration Values:
5728  *
5729  * Enum | Value | Description
5730  * :---------------------------------------|:------|:------------
5731  * ALT_EMAC_GMAC_INT_STAT_MMCTXIS_E_INACT | 0x0 |
5732  * ALT_EMAC_GMAC_INT_STAT_MMCTXIS_E_ACT | 0x1 |
5733  *
5734  * Field Access Macros:
5735  *
5736  */
5737 /*
5738  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCTXIS
5739  *
5740  */
5741 #define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_E_INACT 0x0
5742 /*
5743  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCTXIS
5744  *
5745  */
5746 #define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_E_ACT 0x1
5747 
5748 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field. */
5749 #define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_LSB 6
5750 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field. */
5751 #define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_MSB 6
5752 /* The width in bits of the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field. */
5753 #define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_WIDTH 1
5754 /* The mask used to set the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field value. */
5755 #define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_SET_MSK 0x00000040
5756 /* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field value. */
5757 #define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_CLR_MSK 0xffffffbf
5758 /* The reset value of the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field. */
5759 #define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_RESET 0x0
5760 /* Extracts the ALT_EMAC_GMAC_INT_STAT_MMCTXIS field value from a register. */
5761 #define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_GET(value) (((value) & 0x00000040) >> 6)
5762 /* Produces a ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field value suitable for setting the register. */
5763 #define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_SET(value) (((value) << 6) & 0x00000040)
5764 
5765 /*
5766  * Field : mmcrxipis
5767  *
5768  * MMC Receive Checksum Offload Interrupt Status
5769  *
5770  * This bit is set high when an interrupt is generated in the MMC Receive Checksum
5771  * Offload Interrupt Register. This bit is cleared when all the bits in this
5772  * interrupt register are cleared.
5773  *
5774  * This bit is valid only when you select the optional MMC module and Checksum
5775  * Offload Engine (Type 2) during core configuration.
5776  *
5777  * Field Enumeration Values:
5778  *
5779  * Enum | Value | Description
5780  * :-----------------------------------------|:------|:------------
5781  * ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_E_INACT | 0x0 |
5782  * ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_E_ACT | 0x1 |
5783  *
5784  * Field Access Macros:
5785  *
5786  */
5787 /*
5788  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS
5789  *
5790  */
5791 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_E_INACT 0x0
5792 /*
5793  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS
5794  *
5795  */
5796 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_E_ACT 0x1
5797 
5798 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field. */
5799 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_LSB 7
5800 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field. */
5801 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_MSB 7
5802 /* The width in bits of the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field. */
5803 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_WIDTH 1
5804 /* The mask used to set the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field value. */
5805 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_SET_MSK 0x00000080
5806 /* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field value. */
5807 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_CLR_MSK 0xffffff7f
5808 /* The reset value of the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field. */
5809 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_RESET 0x0
5810 /* Extracts the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS field value from a register. */
5811 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_GET(value) (((value) & 0x00000080) >> 7)
5812 /* Produces a ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field value suitable for setting the register. */
5813 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_SET(value) (((value) << 7) & 0x00000080)
5814 
5815 /*
5816  * Field : reserved_8
5817  *
5818  * Reserved
5819  *
5820  * Field Access Macros:
5821  *
5822  */
5823 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_RSVD_8 register field. */
5824 #define ALT_EMAC_GMAC_INT_STAT_RSVD_8_LSB 8
5825 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_RSVD_8 register field. */
5826 #define ALT_EMAC_GMAC_INT_STAT_RSVD_8_MSB 8
5827 /* The width in bits of the ALT_EMAC_GMAC_INT_STAT_RSVD_8 register field. */
5828 #define ALT_EMAC_GMAC_INT_STAT_RSVD_8_WIDTH 1
5829 /* The mask used to set the ALT_EMAC_GMAC_INT_STAT_RSVD_8 register field value. */
5830 #define ALT_EMAC_GMAC_INT_STAT_RSVD_8_SET_MSK 0x00000100
5831 /* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_RSVD_8 register field value. */
5832 #define ALT_EMAC_GMAC_INT_STAT_RSVD_8_CLR_MSK 0xfffffeff
5833 /* The reset value of the ALT_EMAC_GMAC_INT_STAT_RSVD_8 register field. */
5834 #define ALT_EMAC_GMAC_INT_STAT_RSVD_8_RESET 0x0
5835 /* Extracts the ALT_EMAC_GMAC_INT_STAT_RSVD_8 field value from a register. */
5836 #define ALT_EMAC_GMAC_INT_STAT_RSVD_8_GET(value) (((value) & 0x00000100) >> 8)
5837 /* Produces a ALT_EMAC_GMAC_INT_STAT_RSVD_8 register field value suitable for setting the register. */
5838 #define ALT_EMAC_GMAC_INT_STAT_RSVD_8_SET(value) (((value) << 8) & 0x00000100)
5839 
5840 /*
5841  * Field : tsis
5842  *
5843  * Timestamp Interrupt Status
5844  *
5845  * When the Advanced Timestamp feature is enabled, this bit is set when any of the
5846  * following conditions is true:
5847  *
5848  * * The system time value equals or exceeds the value specified in the Target Time
5849  * High and Low registers.
5850  *
5851  * * There is an overflow in the seconds register.
5852  *
5853  * * The Auxiliary snapshot trigger is asserted.
5854  *
5855  * This bit is cleared on reading Bit 0 of the Register 458 (Timestamp Status
5856  * Register).
5857  *
5858  * If default Timestamping is enabled, when set, this bit indicates that the system
5859  * time value is equal to or exceeds the value specified in the Target Time
5860  * registers. In this mode, this bit is cleared after the completion of the read of
5861  * this bit. In all other modes, this bit is reserved.
5862  *
5863  * Field Enumeration Values:
5864  *
5865  * Enum | Value | Description
5866  * :------------------------------------|:------|:------------
5867  * ALT_EMAC_GMAC_INT_STAT_TSIS_E_INACT | 0x0 |
5868  * ALT_EMAC_GMAC_INT_STAT_TSIS_E_ACT | 0x1 |
5869  *
5870  * Field Access Macros:
5871  *
5872  */
5873 /*
5874  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_TSIS
5875  *
5876  */
5877 #define ALT_EMAC_GMAC_INT_STAT_TSIS_E_INACT 0x0
5878 /*
5879  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_TSIS
5880  *
5881  */
5882 #define ALT_EMAC_GMAC_INT_STAT_TSIS_E_ACT 0x1
5883 
5884 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_TSIS register field. */
5885 #define ALT_EMAC_GMAC_INT_STAT_TSIS_LSB 9
5886 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_TSIS register field. */
5887 #define ALT_EMAC_GMAC_INT_STAT_TSIS_MSB 9
5888 /* The width in bits of the ALT_EMAC_GMAC_INT_STAT_TSIS register field. */
5889 #define ALT_EMAC_GMAC_INT_STAT_TSIS_WIDTH 1
5890 /* The mask used to set the ALT_EMAC_GMAC_INT_STAT_TSIS register field value. */
5891 #define ALT_EMAC_GMAC_INT_STAT_TSIS_SET_MSK 0x00000200
5892 /* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_TSIS register field value. */
5893 #define ALT_EMAC_GMAC_INT_STAT_TSIS_CLR_MSK 0xfffffdff
5894 /* The reset value of the ALT_EMAC_GMAC_INT_STAT_TSIS register field. */
5895 #define ALT_EMAC_GMAC_INT_STAT_TSIS_RESET 0x0
5896 /* Extracts the ALT_EMAC_GMAC_INT_STAT_TSIS field value from a register. */
5897 #define ALT_EMAC_GMAC_INT_STAT_TSIS_GET(value) (((value) & 0x00000200) >> 9)
5898 /* Produces a ALT_EMAC_GMAC_INT_STAT_TSIS register field value suitable for setting the register. */
5899 #define ALT_EMAC_GMAC_INT_STAT_TSIS_SET(value) (((value) << 9) & 0x00000200)
5900 
5901 /*
5902  * Field : lpiis
5903  *
5904  * LPI Interrupt Status
5905  *
5906  * When the Energy Efficient Ethernet feature is enabled, this bit is set for any
5907  * LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared
5908  * on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other
5909  * modes, this bit is reserved.
5910  *
5911  * Field Enumeration Values:
5912  *
5913  * Enum | Value | Description
5914  * :-------------------------------------|:------|:------------
5915  * ALT_EMAC_GMAC_INT_STAT_LPIIS_E_INACT | 0x0 |
5916  * ALT_EMAC_GMAC_INT_STAT_LPIIS_E_ACT | 0x1 |
5917  *
5918  * Field Access Macros:
5919  *
5920  */
5921 /*
5922  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_LPIIS
5923  *
5924  */
5925 #define ALT_EMAC_GMAC_INT_STAT_LPIIS_E_INACT 0x0
5926 /*
5927  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_LPIIS
5928  *
5929  */
5930 #define ALT_EMAC_GMAC_INT_STAT_LPIIS_E_ACT 0x1
5931 
5932 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_LPIIS register field. */
5933 #define ALT_EMAC_GMAC_INT_STAT_LPIIS_LSB 10
5934 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_LPIIS register field. */
5935 #define ALT_EMAC_GMAC_INT_STAT_LPIIS_MSB 10
5936 /* The width in bits of the ALT_EMAC_GMAC_INT_STAT_LPIIS register field. */
5937 #define ALT_EMAC_GMAC_INT_STAT_LPIIS_WIDTH 1
5938 /* The mask used to set the ALT_EMAC_GMAC_INT_STAT_LPIIS register field value. */
5939 #define ALT_EMAC_GMAC_INT_STAT_LPIIS_SET_MSK 0x00000400
5940 /* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_LPIIS register field value. */
5941 #define ALT_EMAC_GMAC_INT_STAT_LPIIS_CLR_MSK 0xfffffbff
5942 /* The reset value of the ALT_EMAC_GMAC_INT_STAT_LPIIS register field. */
5943 #define ALT_EMAC_GMAC_INT_STAT_LPIIS_RESET 0x0
5944 /* Extracts the ALT_EMAC_GMAC_INT_STAT_LPIIS field value from a register. */
5945 #define ALT_EMAC_GMAC_INT_STAT_LPIIS_GET(value) (((value) & 0x00000400) >> 10)
5946 /* Produces a ALT_EMAC_GMAC_INT_STAT_LPIIS register field value suitable for setting the register. */
5947 #define ALT_EMAC_GMAC_INT_STAT_LPIIS_SET(value) (((value) << 10) & 0x00000400)
5948 
5949 /*
5950  * Field : gpiis
5951  *
5952  * GPI Interrupt Status
5953  *
5954  * When the GPIO feature is enabled, this bit is set when any active event (LL or
5955  * LH) occurs on GPIS field (Bits [3:0]) of Register 56 (General Purpose IO
5956  * Register) and the corresponding GPIE bit is enabled. This bit is cleared on
5957  * reading the lane 0 (GPIS) of Register 56 (Genaral Purpose IO Register). When the
5958  * GPIO feature is not enabled, this bit is reserved.
5959  *
5960  * Field Access Macros:
5961  *
5962  */
5963 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_GPIIS register field. */
5964 #define ALT_EMAC_GMAC_INT_STAT_GPIIS_LSB 11
5965 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_GPIIS register field. */
5966 #define ALT_EMAC_GMAC_INT_STAT_GPIIS_MSB 11
5967 /* The width in bits of the ALT_EMAC_GMAC_INT_STAT_GPIIS register field. */
5968 #define ALT_EMAC_GMAC_INT_STAT_GPIIS_WIDTH 1
5969 /* The mask used to set the ALT_EMAC_GMAC_INT_STAT_GPIIS register field value. */
5970 #define ALT_EMAC_GMAC_INT_STAT_GPIIS_SET_MSK 0x00000800
5971 /* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_GPIIS register field value. */
5972 #define ALT_EMAC_GMAC_INT_STAT_GPIIS_CLR_MSK 0xfffff7ff
5973 /* The reset value of the ALT_EMAC_GMAC_INT_STAT_GPIIS register field. */
5974 #define ALT_EMAC_GMAC_INT_STAT_GPIIS_RESET 0x0
5975 /* Extracts the ALT_EMAC_GMAC_INT_STAT_GPIIS field value from a register. */
5976 #define ALT_EMAC_GMAC_INT_STAT_GPIIS_GET(value) (((value) & 0x00000800) >> 11)
5977 /* Produces a ALT_EMAC_GMAC_INT_STAT_GPIIS register field value suitable for setting the register. */
5978 #define ALT_EMAC_GMAC_INT_STAT_GPIIS_SET(value) (((value) << 11) & 0x00000800)
5979 
5980 /*
5981  * Field : reserved_31_12
5982  *
5983  * Reserved
5984  *
5985  * Field Access Macros:
5986  *
5987  */
5988 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_RSVD_31_12 register field. */
5989 #define ALT_EMAC_GMAC_INT_STAT_RSVD_31_12_LSB 12
5990 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_RSVD_31_12 register field. */
5991 #define ALT_EMAC_GMAC_INT_STAT_RSVD_31_12_MSB 31
5992 /* The width in bits of the ALT_EMAC_GMAC_INT_STAT_RSVD_31_12 register field. */
5993 #define ALT_EMAC_GMAC_INT_STAT_RSVD_31_12_WIDTH 20
5994 /* The mask used to set the ALT_EMAC_GMAC_INT_STAT_RSVD_31_12 register field value. */
5995 #define ALT_EMAC_GMAC_INT_STAT_RSVD_31_12_SET_MSK 0xfffff000
5996 /* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_RSVD_31_12 register field value. */
5997 #define ALT_EMAC_GMAC_INT_STAT_RSVD_31_12_CLR_MSK 0x00000fff
5998 /* The reset value of the ALT_EMAC_GMAC_INT_STAT_RSVD_31_12 register field. */
5999 #define ALT_EMAC_GMAC_INT_STAT_RSVD_31_12_RESET 0x0
6000 /* Extracts the ALT_EMAC_GMAC_INT_STAT_RSVD_31_12 field value from a register. */
6001 #define ALT_EMAC_GMAC_INT_STAT_RSVD_31_12_GET(value) (((value) & 0xfffff000) >> 12)
6002 /* Produces a ALT_EMAC_GMAC_INT_STAT_RSVD_31_12 register field value suitable for setting the register. */
6003 #define ALT_EMAC_GMAC_INT_STAT_RSVD_31_12_SET(value) (((value) << 12) & 0xfffff000)
6004 
6005 #ifndef __ASSEMBLY__
6006 /*
6007  * WARNING: The C register and register group struct declarations are provided for
6008  * convenience and illustrative purposes. They should, however, be used with
6009  * caution as the C language standard provides no guarantees about the alignment or
6010  * atomicity of device memory accesses. The recommended practice for writing
6011  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6012  * alt_write_word() functions.
6013  *
6014  * The struct declaration for register ALT_EMAC_GMAC_INT_STAT.
6015  */
6016 struct ALT_EMAC_GMAC_INT_STAT_s
6017 {
6018  const uint32_t rgsmiiis : 1; /* ALT_EMAC_GMAC_INT_STAT_RGSMIIIS */
6019  const uint32_t pcslchgis : 1; /* ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS */
6020  const uint32_t pcsancis : 1; /* ALT_EMAC_GMAC_INT_STAT_PCSANCIS */
6021  const uint32_t pmtis : 1; /* ALT_EMAC_GMAC_INT_STAT_PMTIS */
6022  const uint32_t mmcis : 1; /* ALT_EMAC_GMAC_INT_STAT_MMCIS */
6023  const uint32_t mmcrxis : 1; /* ALT_EMAC_GMAC_INT_STAT_MMCRXIS */
6024  const uint32_t mmctxis : 1; /* ALT_EMAC_GMAC_INT_STAT_MMCTXIS */
6025  const uint32_t mmcrxipis : 1; /* ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS */
6026  const uint32_t reserved_8 : 1; /* ALT_EMAC_GMAC_INT_STAT_RSVD_8 */
6027  const uint32_t tsis : 1; /* ALT_EMAC_GMAC_INT_STAT_TSIS */
6028  const uint32_t lpiis : 1; /* ALT_EMAC_GMAC_INT_STAT_LPIIS */
6029  const uint32_t gpiis : 1; /* ALT_EMAC_GMAC_INT_STAT_GPIIS */
6030  const uint32_t reserved_31_12 : 20; /* ALT_EMAC_GMAC_INT_STAT_RSVD_31_12 */
6031 };
6032 
6033 /* The typedef declaration for register ALT_EMAC_GMAC_INT_STAT. */
6034 typedef volatile struct ALT_EMAC_GMAC_INT_STAT_s ALT_EMAC_GMAC_INT_STAT_t;
6035 #endif /* __ASSEMBLY__ */
6036 
6037 /* The reset value of the ALT_EMAC_GMAC_INT_STAT register. */
6038 #define ALT_EMAC_GMAC_INT_STAT_RESET 0x00000000
6039 /* The byte offset of the ALT_EMAC_GMAC_INT_STAT register from the beginning of the component. */
6040 #define ALT_EMAC_GMAC_INT_STAT_OFST 0x38
6041 /* The address of the ALT_EMAC_GMAC_INT_STAT register. */
6042 #define ALT_EMAC_GMAC_INT_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_INT_STAT_OFST))
6043 
6044 /*
6045  * Register : gmacgrp_interrupt_mask
6046  *
6047  * <b> Register 15 (Interrupt Mask Register) </b>
6048  *
6049  * The Interrupt Mask Register bits enable you to mask the interrupt signal because
6050  * of the corresponding event in the Interrupt Status Register. The interrupt
6051  * signal is sbd_intr_o in the GMAC-AHB, GMAC-AXI, and GMAC-DMA configuration and
6052  * mci_intr_o in the GMAC-MTL and GMAC-CORE configuration.
6053  *
6054  * Register Layout
6055  *
6056  * Bits | Access | Reset | Description
6057  * :--------|:-------|:------|:---------------------------------
6058  * [0] | R | 0x0 | ALT_EMAC_GMAC_INT_MSK_RGSMIIIM
6059  * [1] | R | 0x0 | ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM
6060  * [2] | R | 0x0 | ALT_EMAC_GMAC_INT_MSK_PCSANCIM
6061  * [3] | RW | 0x0 | ALT_EMAC_GMAC_INT_MSK_PMTIM
6062  * [8:4] | R | 0x0 | ALT_EMAC_GMAC_INT_MSK_RSVD_8_4
6063  * [9] | R | 0x0 | ALT_EMAC_GMAC_INT_MSK_TSIM
6064  * [10] | RW | 0x0 | ALT_EMAC_GMAC_INT_MSK_LPIIM
6065  * [31:11] | R | 0x0 | ALT_EMAC_GMAC_INT_MSK_RSVD_31_11
6066  *
6067  */
6068 /*
6069  * Field : rgsmiiim
6070  *
6071  * RGMII or SMII Interrupt Mask
6072  *
6073  * When set, this bit disables the assertion of the interrupt signal because of the
6074  * setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt
6075  * Status Register).
6076  *
6077  * Field Enumeration Values:
6078  *
6079  * Enum | Value | Description
6080  * :--------------------------------------|:------|:------------
6081  * ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_DISD | 0x0 |
6082  * ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_END | 0x1 |
6083  *
6084  * Field Access Macros:
6085  *
6086  */
6087 /*
6088  * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_RGSMIIIM
6089  *
6090  */
6091 #define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_DISD 0x0
6092 /*
6093  * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_RGSMIIIM
6094  *
6095  */
6096 #define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_END 0x1
6097 
6098 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field. */
6099 #define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_LSB 0
6100 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field. */
6101 #define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_MSB 0
6102 /* The width in bits of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field. */
6103 #define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_WIDTH 1
6104 /* The mask used to set the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field value. */
6105 #define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_SET_MSK 0x00000001
6106 /* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field value. */
6107 #define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_CLR_MSK 0xfffffffe
6108 /* The reset value of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field. */
6109 #define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_RESET 0x0
6110 /* Extracts the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM field value from a register. */
6111 #define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_GET(value) (((value) & 0x00000001) >> 0)
6112 /* Produces a ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field value suitable for setting the register. */
6113 #define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_SET(value) (((value) << 0) & 0x00000001)
6114 
6115 /*
6116  * Field : pcslchgim
6117  *
6118  * PCS Link Status Interrupt Mask
6119  *
6120  * When set, this bit disables the assertion of the interrupt signal because of the
6121  * setting of the PCS Link-status changed bit in Register 14 (Interrupt Status
6122  * Register).
6123  *
6124  * Field Access Macros:
6125  *
6126  */
6127 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field. */
6128 #define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_LSB 1
6129 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field. */
6130 #define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_MSB 1
6131 /* The width in bits of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field. */
6132 #define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_WIDTH 1
6133 /* The mask used to set the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field value. */
6134 #define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_SET_MSK 0x00000002
6135 /* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field value. */
6136 #define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_CLR_MSK 0xfffffffd
6137 /* The reset value of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field. */
6138 #define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_RESET 0x0
6139 /* Extracts the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM field value from a register. */
6140 #define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_GET(value) (((value) & 0x00000002) >> 1)
6141 /* Produces a ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field value suitable for setting the register. */
6142 #define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_SET(value) (((value) << 1) & 0x00000002)
6143 
6144 /*
6145  * Field : pcsancim
6146  *
6147  * PCS AN Completion Interrupt Mask
6148  *
6149  * When set, this bit disables the assertion of the interrupt signal because of the
6150  * setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status
6151  * Register).
6152  *
6153  * Field Access Macros:
6154  *
6155  */
6156 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field. */
6157 #define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_LSB 2
6158 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field. */
6159 #define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_MSB 2
6160 /* The width in bits of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field. */
6161 #define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_WIDTH 1
6162 /* The mask used to set the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field value. */
6163 #define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_SET_MSK 0x00000004
6164 /* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field value. */
6165 #define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_CLR_MSK 0xfffffffb
6166 /* The reset value of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field. */
6167 #define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_RESET 0x0
6168 /* Extracts the ALT_EMAC_GMAC_INT_MSK_PCSANCIM field value from a register. */
6169 #define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_GET(value) (((value) & 0x00000004) >> 2)
6170 /* Produces a ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field value suitable for setting the register. */
6171 #define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_SET(value) (((value) << 2) & 0x00000004)
6172 
6173 /*
6174  * Field : pmtim
6175  *
6176  * PMT Interrupt Mask
6177  *
6178  * When set, this bit disables the assertion of the interrupt signal because of the
6179  * setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register).
6180  *
6181  * Field Access Macros:
6182  *
6183  */
6184 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_PMTIM register field. */
6185 #define ALT_EMAC_GMAC_INT_MSK_PMTIM_LSB 3
6186 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_PMTIM register field. */
6187 #define ALT_EMAC_GMAC_INT_MSK_PMTIM_MSB 3
6188 /* The width in bits of the ALT_EMAC_GMAC_INT_MSK_PMTIM register field. */
6189 #define ALT_EMAC_GMAC_INT_MSK_PMTIM_WIDTH 1
6190 /* The mask used to set the ALT_EMAC_GMAC_INT_MSK_PMTIM register field value. */
6191 #define ALT_EMAC_GMAC_INT_MSK_PMTIM_SET_MSK 0x00000008
6192 /* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_PMTIM register field value. */
6193 #define ALT_EMAC_GMAC_INT_MSK_PMTIM_CLR_MSK 0xfffffff7
6194 /* The reset value of the ALT_EMAC_GMAC_INT_MSK_PMTIM register field. */
6195 #define ALT_EMAC_GMAC_INT_MSK_PMTIM_RESET 0x0
6196 /* Extracts the ALT_EMAC_GMAC_INT_MSK_PMTIM field value from a register. */
6197 #define ALT_EMAC_GMAC_INT_MSK_PMTIM_GET(value) (((value) & 0x00000008) >> 3)
6198 /* Produces a ALT_EMAC_GMAC_INT_MSK_PMTIM register field value suitable for setting the register. */
6199 #define ALT_EMAC_GMAC_INT_MSK_PMTIM_SET(value) (((value) << 3) & 0x00000008)
6200 
6201 /*
6202  * Field : reserved_8_4
6203  *
6204  * Reserved
6205  *
6206  * Field Access Macros:
6207  *
6208  */
6209 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_RSVD_8_4 register field. */
6210 #define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_LSB 4
6211 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_RSVD_8_4 register field. */
6212 #define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_MSB 8
6213 /* The width in bits of the ALT_EMAC_GMAC_INT_MSK_RSVD_8_4 register field. */
6214 #define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_WIDTH 5
6215 /* The mask used to set the ALT_EMAC_GMAC_INT_MSK_RSVD_8_4 register field value. */
6216 #define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_SET_MSK 0x000001f0
6217 /* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_RSVD_8_4 register field value. */
6218 #define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_CLR_MSK 0xfffffe0f
6219 /* The reset value of the ALT_EMAC_GMAC_INT_MSK_RSVD_8_4 register field. */
6220 #define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_RESET 0x0
6221 /* Extracts the ALT_EMAC_GMAC_INT_MSK_RSVD_8_4 field value from a register. */
6222 #define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_GET(value) (((value) & 0x000001f0) >> 4)
6223 /* Produces a ALT_EMAC_GMAC_INT_MSK_RSVD_8_4 register field value suitable for setting the register. */
6224 #define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_SET(value) (((value) << 4) & 0x000001f0)
6225 
6226 /*
6227  * Field : tsim
6228  *
6229  * Timestamp Interrupt Mask
6230  *
6231  * When set, this bit disables the assertion of the interrupt signal because of the
6232  * setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status
6233  * Register).
6234  *
6235  * This bit is valid only when IEEE1588 timestamping is enabled. In all other
6236  * modes, this bit is reserved.
6237  *
6238  * Field Enumeration Values:
6239  *
6240  * Enum | Value | Description
6241  * :----------------------------------|:------|:------------
6242  * ALT_EMAC_GMAC_INT_MSK_TSIM_E_DISD | 0x0 |
6243  * ALT_EMAC_GMAC_INT_MSK_TSIM_E_END | 0x1 |
6244  *
6245  * Field Access Macros:
6246  *
6247  */
6248 /*
6249  * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_TSIM
6250  *
6251  */
6252 #define ALT_EMAC_GMAC_INT_MSK_TSIM_E_DISD 0x0
6253 /*
6254  * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_TSIM
6255  *
6256  */
6257 #define ALT_EMAC_GMAC_INT_MSK_TSIM_E_END 0x1
6258 
6259 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_TSIM register field. */
6260 #define ALT_EMAC_GMAC_INT_MSK_TSIM_LSB 9
6261 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_TSIM register field. */
6262 #define ALT_EMAC_GMAC_INT_MSK_TSIM_MSB 9
6263 /* The width in bits of the ALT_EMAC_GMAC_INT_MSK_TSIM register field. */
6264 #define ALT_EMAC_GMAC_INT_MSK_TSIM_WIDTH 1
6265 /* The mask used to set the ALT_EMAC_GMAC_INT_MSK_TSIM register field value. */
6266 #define ALT_EMAC_GMAC_INT_MSK_TSIM_SET_MSK 0x00000200
6267 /* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_TSIM register field value. */
6268 #define ALT_EMAC_GMAC_INT_MSK_TSIM_CLR_MSK 0xfffffdff
6269 /* The reset value of the ALT_EMAC_GMAC_INT_MSK_TSIM register field. */
6270 #define ALT_EMAC_GMAC_INT_MSK_TSIM_RESET 0x0
6271 /* Extracts the ALT_EMAC_GMAC_INT_MSK_TSIM field value from a register. */
6272 #define ALT_EMAC_GMAC_INT_MSK_TSIM_GET(value) (((value) & 0x00000200) >> 9)
6273 /* Produces a ALT_EMAC_GMAC_INT_MSK_TSIM register field value suitable for setting the register. */
6274 #define ALT_EMAC_GMAC_INT_MSK_TSIM_SET(value) (((value) << 9) & 0x00000200)
6275 
6276 /*
6277  * Field : lpiim
6278  *
6279  * LPI Interrupt Mask
6280  *
6281  * When set, this bit disables the assertion of the interrupt signal because of the
6282  * setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status
6283  * Register).
6284  *
6285  * This bit is valid only when you select the Energy Efficient Ethernet feature
6286  * during core configuration. In all other modes, this bit is reserved.
6287  *
6288  * Field Enumeration Values:
6289  *
6290  * Enum | Value | Description
6291  * :-----------------------------------|:------|:------------
6292  * ALT_EMAC_GMAC_INT_MSK_LPIIM_E_DISD | 0x0 |
6293  * ALT_EMAC_GMAC_INT_MSK_LPIIM_E_END | 0x1 |
6294  *
6295  * Field Access Macros:
6296  *
6297  */
6298 /*
6299  * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_LPIIM
6300  *
6301  */
6302 #define ALT_EMAC_GMAC_INT_MSK_LPIIM_E_DISD 0x0
6303 /*
6304  * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_LPIIM
6305  *
6306  */
6307 #define ALT_EMAC_GMAC_INT_MSK_LPIIM_E_END 0x1
6308 
6309 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field. */
6310 #define ALT_EMAC_GMAC_INT_MSK_LPIIM_LSB 10
6311 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field. */
6312 #define ALT_EMAC_GMAC_INT_MSK_LPIIM_MSB 10
6313 /* The width in bits of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field. */
6314 #define ALT_EMAC_GMAC_INT_MSK_LPIIM_WIDTH 1
6315 /* The mask used to set the ALT_EMAC_GMAC_INT_MSK_LPIIM register field value. */
6316 #define ALT_EMAC_GMAC_INT_MSK_LPIIM_SET_MSK 0x00000400
6317 /* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_LPIIM register field value. */
6318 #define ALT_EMAC_GMAC_INT_MSK_LPIIM_CLR_MSK 0xfffffbff
6319 /* The reset value of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field. */
6320 #define ALT_EMAC_GMAC_INT_MSK_LPIIM_RESET 0x0
6321 /* Extracts the ALT_EMAC_GMAC_INT_MSK_LPIIM field value from a register. */
6322 #define ALT_EMAC_GMAC_INT_MSK_LPIIM_GET(value) (((value) & 0x00000400) >> 10)
6323 /* Produces a ALT_EMAC_GMAC_INT_MSK_LPIIM register field value suitable for setting the register. */
6324 #define ALT_EMAC_GMAC_INT_MSK_LPIIM_SET(value) (((value) << 10) & 0x00000400)
6325 
6326 /*
6327  * Field : reserved_31_11
6328  *
6329  * Reserved
6330  *
6331  * Field Access Macros:
6332  *
6333  */
6334 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_RSVD_31_11 register field. */
6335 #define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_LSB 11
6336 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_RSVD_31_11 register field. */
6337 #define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_MSB 31
6338 /* The width in bits of the ALT_EMAC_GMAC_INT_MSK_RSVD_31_11 register field. */
6339 #define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_WIDTH 21
6340 /* The mask used to set the ALT_EMAC_GMAC_INT_MSK_RSVD_31_11 register field value. */
6341 #define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_SET_MSK 0xfffff800
6342 /* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_RSVD_31_11 register field value. */
6343 #define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_CLR_MSK 0x000007ff
6344 /* The reset value of the ALT_EMAC_GMAC_INT_MSK_RSVD_31_11 register field. */
6345 #define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_RESET 0x0
6346 /* Extracts the ALT_EMAC_GMAC_INT_MSK_RSVD_31_11 field value from a register. */
6347 #define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_GET(value) (((value) & 0xfffff800) >> 11)
6348 /* Produces a ALT_EMAC_GMAC_INT_MSK_RSVD_31_11 register field value suitable for setting the register. */
6349 #define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_SET(value) (((value) << 11) & 0xfffff800)
6350 
6351 #ifndef __ASSEMBLY__
6352 /*
6353  * WARNING: The C register and register group struct declarations are provided for
6354  * convenience and illustrative purposes. They should, however, be used with
6355  * caution as the C language standard provides no guarantees about the alignment or
6356  * atomicity of device memory accesses. The recommended practice for writing
6357  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6358  * alt_write_word() functions.
6359  *
6360  * The struct declaration for register ALT_EMAC_GMAC_INT_MSK.
6361  */
6362 struct ALT_EMAC_GMAC_INT_MSK_s
6363 {
6364  const uint32_t rgsmiiim : 1; /* ALT_EMAC_GMAC_INT_MSK_RGSMIIIM */
6365  const uint32_t pcslchgim : 1; /* ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM */
6366  const uint32_t pcsancim : 1; /* ALT_EMAC_GMAC_INT_MSK_PCSANCIM */
6367  uint32_t pmtim : 1; /* ALT_EMAC_GMAC_INT_MSK_PMTIM */
6368  const uint32_t reserved_8_4 : 5; /* ALT_EMAC_GMAC_INT_MSK_RSVD_8_4 */
6369  const uint32_t tsim : 1; /* ALT_EMAC_GMAC_INT_MSK_TSIM */
6370  uint32_t lpiim : 1; /* ALT_EMAC_GMAC_INT_MSK_LPIIM */
6371  const uint32_t reserved_31_11 : 21; /* ALT_EMAC_GMAC_INT_MSK_RSVD_31_11 */
6372 };
6373 
6374 /* The typedef declaration for register ALT_EMAC_GMAC_INT_MSK. */
6375 typedef volatile struct ALT_EMAC_GMAC_INT_MSK_s ALT_EMAC_GMAC_INT_MSK_t;
6376 #endif /* __ASSEMBLY__ */
6377 
6378 /* The reset value of the ALT_EMAC_GMAC_INT_MSK register. */
6379 #define ALT_EMAC_GMAC_INT_MSK_RESET 0x00000000
6380 /* The byte offset of the ALT_EMAC_GMAC_INT_MSK register from the beginning of the component. */
6381 #define ALT_EMAC_GMAC_INT_MSK_OFST 0x3c
6382 /* The address of the ALT_EMAC_GMAC_INT_MSK register. */
6383 #define ALT_EMAC_GMAC_INT_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_INT_MSK_OFST))
6384 
6385 /*
6386  * Register : gmacgrp_mac_address0_high
6387  *
6388  * <b> Register 16 (MAC Address0 High Register) </b>
6389  *
6390  * The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC
6391  * address of the station. The first DA byte that is received on the (G)MII
6392  * interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low
6393  * register. For example, if 0x112233445566 is received (0x11 in lane 0 of the
6394  * first column) on the (G)MII as the destination address, then the MacAddress0
6395  * Register [47:0] is compared with 0x665544332211.
6396  *
6397  * If the MAC address registers are configured to be double-synchronized to the
6398  * (G)MII clock domains, then the synchronization is triggered only when
6399  * Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC
6400  * Address0 Low Register are written. For proper synchronization updates, the
6401  * consecutive writes to this Address Low Register should be performed after at
6402  * least four clock cycles in the destination clock domain.
6403  *
6404  * Register Layout
6405  *
6406  * Bits | Access | Reset | Description
6407  * :--------|:-------|:-------|:----------------------------------------
6408  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI
6409  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR0_HIGH_RSVD_30_16
6410  * [31] | R | 0x1 | ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE
6411  *
6412  */
6413 /*
6414  * Field : addrhi
6415  *
6416  * MAC Address0 [47:32]
6417  *
6418  * This field contains the upper 16 bits (47:32) of the first 6-byte MAC address.
6419  * The MAC uses this field for filtering the received frames and inserting the MAC
6420  * address in the Transmit Flow Control (PAUSE) Frames.
6421  *
6422  * Field Access Macros:
6423  *
6424  */
6425 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field. */
6426 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_LSB 0
6427 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field. */
6428 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_MSB 15
6429 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field. */
6430 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_WIDTH 16
6431 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field value. */
6432 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_SET_MSK 0x0000ffff
6433 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field value. */
6434 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_CLR_MSK 0xffff0000
6435 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field. */
6436 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_RESET 0xffff
6437 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI field value from a register. */
6438 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
6439 /* Produces a ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field value suitable for setting the register. */
6440 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
6441 
6442 /*
6443  * Field : reserved_30_16
6444  *
6445  * Reserved
6446  *
6447  * Field Access Macros:
6448  *
6449  */
6450 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_RSVD_30_16 register field. */
6451 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_RSVD_30_16_LSB 16
6452 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_RSVD_30_16 register field. */
6453 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_RSVD_30_16_MSB 30
6454 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_RSVD_30_16 register field. */
6455 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_RSVD_30_16_WIDTH 15
6456 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_RSVD_30_16 register field value. */
6457 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
6458 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_RSVD_30_16 register field value. */
6459 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
6460 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_RSVD_30_16 register field. */
6461 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_RSVD_30_16_RESET 0x0
6462 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_RSVD_30_16 field value from a register. */
6463 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
6464 /* Produces a ALT_EMAC_GMAC_MAC_ADDR0_HIGH_RSVD_30_16 register field value suitable for setting the register. */
6465 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
6466 
6467 /*
6468  * Field : ae
6469  *
6470  * Address Enable
6471  *
6472  * This bit is always set to 1.
6473  *
6474  * Field Access Macros:
6475  *
6476  */
6477 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field. */
6478 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_LSB 31
6479 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field. */
6480 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_MSB 31
6481 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field. */
6482 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_WIDTH 1
6483 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field value. */
6484 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_SET_MSK 0x80000000
6485 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field value. */
6486 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_CLR_MSK 0x7fffffff
6487 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field. */
6488 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_RESET 0x1
6489 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE field value from a register. */
6490 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
6491 /* Produces a ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field value suitable for setting the register. */
6492 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
6493 
6494 #ifndef __ASSEMBLY__
6495 /*
6496  * WARNING: The C register and register group struct declarations are provided for
6497  * convenience and illustrative purposes. They should, however, be used with
6498  * caution as the C language standard provides no guarantees about the alignment or
6499  * atomicity of device memory accesses. The recommended practice for writing
6500  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6501  * alt_write_word() functions.
6502  *
6503  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR0_HIGH.
6504  */
6505 struct ALT_EMAC_GMAC_MAC_ADDR0_HIGH_s
6506 {
6507  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI */
6508  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR0_HIGH_RSVD_30_16 */
6509  const uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE */
6510 };
6511 
6512 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR0_HIGH. */
6513 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR0_HIGH_s ALT_EMAC_GMAC_MAC_ADDR0_HIGH_t;
6514 #endif /* __ASSEMBLY__ */
6515 
6516 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH register. */
6517 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_RESET 0x8000ffff
6518 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH register from the beginning of the component. */
6519 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_OFST 0x40
6520 /* The address of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH register. */
6521 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR0_HIGH_OFST))
6522 
6523 /*
6524  * Register : gmacgrp_mac_address0_low
6525  *
6526  * <b> Register 17 (MAC Address0 Low Register) </b>
6527  *
6528  * The MAC Address0 Low register holds the lower 32 bits of the first 6-byte MAC
6529  * address of the station.
6530  *
6531  * Register Layout
6532  *
6533  * Bits | Access | Reset | Description
6534  * :-------|:-------|:-----------|:-----------------------------------
6535  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO
6536  *
6537  */
6538 /*
6539  * Field : addrlo
6540  *
6541  * MAC Address0 [31:0]
6542  *
6543  * This field contains the lower 32 bits of the first 6-byte MAC address. This is
6544  * used by the MAC for filtering the received frames and inserting the MAC address
6545  * in the Transmit Flow Control (PAUSE) Frames.
6546  *
6547  * Field Access Macros:
6548  *
6549  */
6550 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field. */
6551 #define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_LSB 0
6552 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field. */
6553 #define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_MSB 31
6554 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field. */
6555 #define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_WIDTH 32
6556 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field value. */
6557 #define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_SET_MSK 0xffffffff
6558 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field value. */
6559 #define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_CLR_MSK 0x00000000
6560 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field. */
6561 #define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_RESET 0xffffffff
6562 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO field value from a register. */
6563 #define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
6564 /* Produces a ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field value suitable for setting the register. */
6565 #define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
6566 
6567 #ifndef __ASSEMBLY__
6568 /*
6569  * WARNING: The C register and register group struct declarations are provided for
6570  * convenience and illustrative purposes. They should, however, be used with
6571  * caution as the C language standard provides no guarantees about the alignment or
6572  * atomicity of device memory accesses. The recommended practice for writing
6573  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6574  * alt_write_word() functions.
6575  *
6576  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR0_LOW.
6577  */
6578 struct ALT_EMAC_GMAC_MAC_ADDR0_LOW_s
6579 {
6580  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO */
6581 };
6582 
6583 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR0_LOW. */
6584 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR0_LOW_s ALT_EMAC_GMAC_MAC_ADDR0_LOW_t;
6585 #endif /* __ASSEMBLY__ */
6586 
6587 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR0_LOW register. */
6588 #define ALT_EMAC_GMAC_MAC_ADDR0_LOW_RESET 0xffffffff
6589 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR0_LOW register from the beginning of the component. */
6590 #define ALT_EMAC_GMAC_MAC_ADDR0_LOW_OFST 0x44
6591 /* The address of the ALT_EMAC_GMAC_MAC_ADDR0_LOW register. */
6592 #define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR0_LOW_OFST))
6593 
6594 /*
6595  * Register : gmacgrp_mac_address1_high
6596  *
6597  * <b> Register 18 (MAC Address1 High Register) </b>
6598  *
6599  * The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC
6600  * address of the station.
6601  *
6602  * If the MAC address registers are configured to be double-synchronized to the
6603  * (G)MII clock domains, then the synchronization is triggered only when
6604  * Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC
6605  * Address1 Low Register are written. For proper synchronization updates, the
6606  * consecutive writes to this Address Low Register should be performed after at
6607  * least four clock cycles in the destination clock domain.
6608  *
6609  * Register Layout
6610  *
6611  * Bits | Access | Reset | Description
6612  * :--------|:-------|:-------|:----------------------------------------
6613  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI
6614  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR1_HIGH_RSVD_23_16
6615  * [24] | RW | 0x0 | Mask Byte Control
6616  * [25] | RW | 0x0 | Mask Byte Control
6617  * [26] | RW | 0x0 | Mask Byte Control
6618  * [27] | RW | 0x0 | Mask Byte Control
6619  * [28] | RW | 0x0 | Mask Byte Control
6620  * [29] | RW | 0x0 | Mask Byte Control
6621  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA
6622  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE
6623  *
6624  */
6625 /*
6626  * Field : addrhi
6627  *
6628  * MAC Address1 [47:32]
6629  *
6630  * This field contains the upper 16 bits (47:32) of the second 6-byte MAC address.
6631  *
6632  * Field Access Macros:
6633  *
6634  */
6635 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field. */
6636 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_LSB 0
6637 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field. */
6638 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_MSB 15
6639 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field. */
6640 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_WIDTH 16
6641 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field value. */
6642 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_SET_MSK 0x0000ffff
6643 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field value. */
6644 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_CLR_MSK 0xffff0000
6645 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field. */
6646 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_RESET 0xffff
6647 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI field value from a register. */
6648 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
6649 /* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field value suitable for setting the register. */
6650 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
6651 
6652 /*
6653  * Field : reserved_23_16
6654  *
6655  * Reserved
6656  *
6657  * Field Access Macros:
6658  *
6659  */
6660 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_RSVD_23_16 register field. */
6661 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_RSVD_23_16_LSB 16
6662 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_RSVD_23_16 register field. */
6663 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_RSVD_23_16_MSB 23
6664 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_RSVD_23_16 register field. */
6665 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_RSVD_23_16_WIDTH 8
6666 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_RSVD_23_16 register field value. */
6667 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
6668 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_RSVD_23_16 register field value. */
6669 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
6670 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_RSVD_23_16 register field. */
6671 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_RSVD_23_16_RESET 0x0
6672 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_RSVD_23_16 field value from a register. */
6673 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
6674 /* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_RSVD_23_16 register field value suitable for setting the register. */
6675 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
6676 
6677 /*
6678  * Field : Mask Byte Control - mbc_0
6679  *
6680  * This array of bits are mask control bits for comparison of each of the MAC
6681  * Address bytes. When masked, the MAC does not compare the corresponding byte of
6682  * received DA or SA with the contents of MAC Address1 high and low registers. Each
6683  * bit controls the masking of the bytes. You can filter a group of addresses
6684  * (known as group address filtering) by masking one or more bytes of the address.
6685  *
6686  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
6687  *
6688  * Field Enumeration Values:
6689  *
6690  * Enum | Value | Description
6691  * :---------------------------------------------|:------|:------------
6692  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_E_UNMSKED | 0x0 |
6693  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_E_MSKED | 0x1 |
6694  *
6695  * Field Access Macros:
6696  *
6697  */
6698 /*
6699  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0
6700  *
6701  */
6702 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_E_UNMSKED 0x0
6703 /*
6704  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0
6705  *
6706  */
6707 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_E_MSKED 0x1
6708 
6709 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field. */
6710 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_LSB 24
6711 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field. */
6712 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_MSB 24
6713 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field. */
6714 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_WIDTH 1
6715 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field value. */
6716 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_SET_MSK 0x01000000
6717 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field value. */
6718 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_CLR_MSK 0xfeffffff
6719 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field. */
6720 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_RESET 0x0
6721 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 field value from a register. */
6722 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
6723 /* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field value suitable for setting the register. */
6724 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
6725 
6726 /*
6727  * Field : Mask Byte Control - mbc_1
6728  *
6729  * This array of bits are mask control bits for comparison of each of the MAC
6730  * Address bytes. When masked, the MAC does not compare the corresponding byte of
6731  * received DA or SA with the contents of MAC Address1 high and low registers. Each
6732  * bit controls the masking of the bytes. You can filter a group of addresses
6733  * (known as group address filtering) by masking one or more bytes of the address.
6734  *
6735  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
6736  *
6737  * Field Enumeration Values:
6738  *
6739  * Enum | Value | Description
6740  * :---------------------------------------------|:------|:------------
6741  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_E_UNMSKED | 0x0 |
6742  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_E_MSKED | 0x1 |
6743  *
6744  * Field Access Macros:
6745  *
6746  */
6747 /*
6748  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1
6749  *
6750  */
6751 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_E_UNMSKED 0x0
6752 /*
6753  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1
6754  *
6755  */
6756 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_E_MSKED 0x1
6757 
6758 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field. */
6759 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_LSB 25
6760 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field. */
6761 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_MSB 25
6762 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field. */
6763 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_WIDTH 1
6764 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field value. */
6765 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_SET_MSK 0x02000000
6766 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field value. */
6767 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_CLR_MSK 0xfdffffff
6768 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field. */
6769 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_RESET 0x0
6770 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 field value from a register. */
6771 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
6772 /* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field value suitable for setting the register. */
6773 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
6774 
6775 /*
6776  * Field : Mask Byte Control - mbc_2
6777  *
6778  * This array of bits are mask control bits for comparison of each of the MAC
6779  * Address bytes. When masked, the MAC does not compare the corresponding byte of
6780  * received DA or SA with the contents of MAC Address1 high and low registers. Each
6781  * bit controls the masking of the bytes. You can filter a group of addresses
6782  * (known as group address filtering) by masking one or more bytes of the address.
6783  *
6784  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
6785  *
6786  * Field Enumeration Values:
6787  *
6788  * Enum | Value | Description
6789  * :---------------------------------------------|:------|:------------
6790  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_E_UNMSKED | 0x0 |
6791  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_E_MSKED | 0x1 |
6792  *
6793  * Field Access Macros:
6794  *
6795  */
6796 /*
6797  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2
6798  *
6799  */
6800 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_E_UNMSKED 0x0
6801 /*
6802  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2
6803  *
6804  */
6805 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_E_MSKED 0x1
6806 
6807 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field. */
6808 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_LSB 26
6809 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field. */
6810 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_MSB 26
6811 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field. */
6812 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_WIDTH 1
6813 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field value. */
6814 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_SET_MSK 0x04000000
6815 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field value. */
6816 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_CLR_MSK 0xfbffffff
6817 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field. */
6818 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_RESET 0x0
6819 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 field value from a register. */
6820 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
6821 /* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field value suitable for setting the register. */
6822 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
6823 
6824 /*
6825  * Field : Mask Byte Control - mbc_3
6826  *
6827  * This array of bits are mask control bits for comparison of each of the MAC
6828  * Address bytes. When masked, the MAC does not compare the corresponding byte of
6829  * received DA or SA with the contents of MAC Address1 high and low registers. Each
6830  * bit controls the masking of the bytes. You can filter a group of addresses
6831  * (known as group address filtering) by masking one or more bytes of the address.
6832  *
6833  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
6834  *
6835  * Field Enumeration Values:
6836  *
6837  * Enum | Value | Description
6838  * :---------------------------------------------|:------|:------------
6839  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_E_UNMSKED | 0x0 |
6840  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_E_MSKED | 0x1 |
6841  *
6842  * Field Access Macros:
6843  *
6844  */
6845 /*
6846  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3
6847  *
6848  */
6849 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_E_UNMSKED 0x0
6850 /*
6851  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3
6852  *
6853  */
6854 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_E_MSKED 0x1
6855 
6856 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field. */
6857 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_LSB 27
6858 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field. */
6859 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_MSB 27
6860 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field. */
6861 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_WIDTH 1
6862 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field value. */
6863 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_SET_MSK 0x08000000
6864 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field value. */
6865 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_CLR_MSK 0xf7ffffff
6866 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field. */
6867 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_RESET 0x0
6868 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 field value from a register. */
6869 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
6870 /* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field value suitable for setting the register. */
6871 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
6872 
6873 /*
6874  * Field : Mask Byte Control - mbc_4
6875  *
6876  * This array of bits are mask control bits for comparison of each of the MAC
6877  * Address bytes. When masked, the MAC does not compare the corresponding byte of
6878  * received DA or SA with the contents of MAC Address1 high and low registers. Each
6879  * bit controls the masking of the bytes. You can filter a group of addresses
6880  * (known as group address filtering) by masking one or more bytes of the address.
6881  *
6882  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
6883  *
6884  * Field Enumeration Values:
6885  *
6886  * Enum | Value | Description
6887  * :---------------------------------------------|:------|:------------
6888  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_E_UNMSKED | 0x0 |
6889  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_E_MSKED | 0x1 |
6890  *
6891  * Field Access Macros:
6892  *
6893  */
6894 /*
6895  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4
6896  *
6897  */
6898 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_E_UNMSKED 0x0
6899 /*
6900  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4
6901  *
6902  */
6903 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_E_MSKED 0x1
6904 
6905 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field. */
6906 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_LSB 28
6907 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field. */
6908 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_MSB 28
6909 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field. */
6910 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_WIDTH 1
6911 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field value. */
6912 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_SET_MSK 0x10000000
6913 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field value. */
6914 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_CLR_MSK 0xefffffff
6915 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field. */
6916 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_RESET 0x0
6917 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 field value from a register. */
6918 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
6919 /* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field value suitable for setting the register. */
6920 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
6921 
6922 /*
6923  * Field : Mask Byte Control - mbc_5
6924  *
6925  * This array of bits are mask control bits for comparison of each of the MAC
6926  * Address bytes. When masked, the MAC does not compare the corresponding byte of
6927  * received DA or SA with the contents of MAC Address1 high and low registers. Each
6928  * bit controls the masking of the bytes. You can filter a group of addresses
6929  * (known as group address filtering) by masking one or more bytes of the address.
6930  *
6931  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
6932  *
6933  * Field Enumeration Values:
6934  *
6935  * Enum | Value | Description
6936  * :---------------------------------------------|:------|:------------
6937  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_E_UNMSKED | 0x0 |
6938  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_E_MSKED | 0x1 |
6939  *
6940  * Field Access Macros:
6941  *
6942  */
6943 /*
6944  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5
6945  *
6946  */
6947 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_E_UNMSKED 0x0
6948 /*
6949  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5
6950  *
6951  */
6952 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_E_MSKED 0x1
6953 
6954 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field. */
6955 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_LSB 29
6956 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field. */
6957 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_MSB 29
6958 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field. */
6959 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_WIDTH 1
6960 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field value. */
6961 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_SET_MSK 0x20000000
6962 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field value. */
6963 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_CLR_MSK 0xdfffffff
6964 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field. */
6965 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_RESET 0x0
6966 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 field value from a register. */
6967 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
6968 /* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field value suitable for setting the register. */
6969 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
6970 
6971 /*
6972  * Field : sa
6973  *
6974  * Source Address
6975  *
6976  * When this bit is set, the MAC Address1[47:0] is used to compare with the SA
6977  * fields of the received frame.
6978  *
6979  * When this bit is reset, the MAC Address1[47:0] is used to compare with the DA
6980  * fields of the received frame.
6981  *
6982  * Field Enumeration Values:
6983  *
6984  * Enum | Value | Description
6985  * :---------------------------------------|:------|:------------
6986  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_E_DISD | 0x0 |
6987  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_E_END | 0x1 |
6988  *
6989  * Field Access Macros:
6990  *
6991  */
6992 /*
6993  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA
6994  *
6995  */
6996 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_E_DISD 0x0
6997 /*
6998  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA
6999  *
7000  */
7001 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_E_END 0x1
7002 
7003 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field. */
7004 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_LSB 30
7005 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field. */
7006 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_MSB 30
7007 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field. */
7008 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_WIDTH 1
7009 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field value. */
7010 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_SET_MSK 0x40000000
7011 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field value. */
7012 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_CLR_MSK 0xbfffffff
7013 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field. */
7014 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_RESET 0x0
7015 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA field value from a register. */
7016 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
7017 /* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field value suitable for setting the register. */
7018 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
7019 
7020 /*
7021  * Field : ae
7022  *
7023  * Address Enable
7024  *
7025  * When this bit is set, the address filter module uses the second MAC address for
7026  * perfect filtering.
7027  *
7028  * When this bit is reset, the address filter module ignores the address for
7029  * filtering.
7030  *
7031  * Field Enumeration Values:
7032  *
7033  * Enum | Value | Description
7034  * :---------------------------------------|:------|:------------
7035  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_E_DISD | 0x0 |
7036  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_E_END | 0x1 |
7037  *
7038  * Field Access Macros:
7039  *
7040  */
7041 /*
7042  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE
7043  *
7044  */
7045 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_E_DISD 0x0
7046 /*
7047  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE
7048  *
7049  */
7050 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_E_END 0x1
7051 
7052 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field. */
7053 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_LSB 31
7054 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field. */
7055 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_MSB 31
7056 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field. */
7057 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_WIDTH 1
7058 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field value. */
7059 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_SET_MSK 0x80000000
7060 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field value. */
7061 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_CLR_MSK 0x7fffffff
7062 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field. */
7063 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_RESET 0x0
7064 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE field value from a register. */
7065 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
7066 /* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field value suitable for setting the register. */
7067 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
7068 
7069 #ifndef __ASSEMBLY__
7070 /*
7071  * WARNING: The C register and register group struct declarations are provided for
7072  * convenience and illustrative purposes. They should, however, be used with
7073  * caution as the C language standard provides no guarantees about the alignment or
7074  * atomicity of device memory accesses. The recommended practice for writing
7075  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7076  * alt_write_word() functions.
7077  *
7078  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR1_HIGH.
7079  */
7080 struct ALT_EMAC_GMAC_MAC_ADDR1_HIGH_s
7081 {
7082  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI */
7083  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR1_HIGH_RSVD_23_16 */
7084  uint32_t mbc_0 : 1; /* Mask Byte Control */
7085  uint32_t mbc_1 : 1; /* Mask Byte Control */
7086  uint32_t mbc_2 : 1; /* Mask Byte Control */
7087  uint32_t mbc_3 : 1; /* Mask Byte Control */
7088  uint32_t mbc_4 : 1; /* Mask Byte Control */
7089  uint32_t mbc_5 : 1; /* Mask Byte Control */
7090  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA */
7091  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE */
7092 };
7093 
7094 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR1_HIGH. */
7095 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR1_HIGH_s ALT_EMAC_GMAC_MAC_ADDR1_HIGH_t;
7096 #endif /* __ASSEMBLY__ */
7097 
7098 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH register. */
7099 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_RESET 0x0000ffff
7100 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH register from the beginning of the component. */
7101 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_OFST 0x48
7102 /* The address of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH register. */
7103 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR1_HIGH_OFST))
7104 
7105 /*
7106  * Register : gmacgrp_mac_address1_low
7107  *
7108  * <b> Register 19 (MAC Address1 Low Register) </b>
7109  *
7110  * The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC
7111  * address of the station.
7112  *
7113  * Register Layout
7114  *
7115  * Bits | Access | Reset | Description
7116  * :-------|:-------|:-----------|:-----------------------------------
7117  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO
7118  *
7119  */
7120 /*
7121  * Field : addrlo
7122  *
7123  * MAC Address1 [31:0]
7124  *
7125  * This field contains the lower 32 bits of the second 6-byte MAC address. The
7126  * content of this field is undefined until loaded by the Application after the
7127  * initialization process.
7128  *
7129  * Field Access Macros:
7130  *
7131  */
7132 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field. */
7133 #define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_LSB 0
7134 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field. */
7135 #define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_MSB 31
7136 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field. */
7137 #define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_WIDTH 32
7138 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field value. */
7139 #define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_SET_MSK 0xffffffff
7140 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field value. */
7141 #define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_CLR_MSK 0x00000000
7142 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field. */
7143 #define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_RESET 0xffffffff
7144 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO field value from a register. */
7145 #define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
7146 /* Produces a ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field value suitable for setting the register. */
7147 #define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
7148 
7149 #ifndef __ASSEMBLY__
7150 /*
7151  * WARNING: The C register and register group struct declarations are provided for
7152  * convenience and illustrative purposes. They should, however, be used with
7153  * caution as the C language standard provides no guarantees about the alignment or
7154  * atomicity of device memory accesses. The recommended practice for writing
7155  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7156  * alt_write_word() functions.
7157  *
7158  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR1_LOW.
7159  */
7160 struct ALT_EMAC_GMAC_MAC_ADDR1_LOW_s
7161 {
7162  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO */
7163 };
7164 
7165 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR1_LOW. */
7166 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR1_LOW_s ALT_EMAC_GMAC_MAC_ADDR1_LOW_t;
7167 #endif /* __ASSEMBLY__ */
7168 
7169 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_LOW register. */
7170 #define ALT_EMAC_GMAC_MAC_ADDR1_LOW_RESET 0xffffffff
7171 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR1_LOW register from the beginning of the component. */
7172 #define ALT_EMAC_GMAC_MAC_ADDR1_LOW_OFST 0x4c
7173 /* The address of the ALT_EMAC_GMAC_MAC_ADDR1_LOW register. */
7174 #define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR1_LOW_OFST))
7175 
7176 /*
7177  * Register : gmacgrp_mac_address2_high
7178  *
7179  * <b> Register 20 (MAC Address2 High Register) </b>
7180  *
7181  * The MAC Address2 High register holds the upper 16 bits of the third 6-byte MAC
7182  * address of the station.
7183  *
7184  * If the MAC address registers are configured to be double-synchronized to the
7185  * (G)MII clock domains, then
7186  *
7187  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
7188  * or Bits[7:0] (in big-endian mode) of the MAC Address2 Low Register are written.
7189  * For proper synchronization updates, consecutive writes to this MAC Address2 Low
7190  * Register must be performed after at least four clock cycles in the destination
7191  * clock domain.
7192  *
7193  * Register Layout
7194  *
7195  * Bits | Access | Reset | Description
7196  * :--------|:-------|:-------|:----------------------------------------
7197  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI
7198  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR2_HIGH_RSVD_23_16
7199  * [24] | RW | 0x0 | Mask Byte Control
7200  * [25] | RW | 0x0 | Mask Byte Control
7201  * [26] | RW | 0x0 | Mask Byte Control
7202  * [27] | RW | 0x0 | Mask Byte Control
7203  * [28] | RW | 0x0 | Mask Byte Control
7204  * [29] | RW | 0x0 | Mask Byte Control
7205  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA
7206  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE
7207  *
7208  */
7209 /*
7210  * Field : addrhi
7211  *
7212  * MAC Address2 [47:32]
7213  *
7214  * This field contains the upper 16 bits (47:32) of the third 6-byte MAC address.
7215  *
7216  * Field Access Macros:
7217  *
7218  */
7219 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field. */
7220 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_LSB 0
7221 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field. */
7222 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_MSB 15
7223 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field. */
7224 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_WIDTH 16
7225 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field value. */
7226 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_SET_MSK 0x0000ffff
7227 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field value. */
7228 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_CLR_MSK 0xffff0000
7229 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field. */
7230 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_RESET 0xffff
7231 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI field value from a register. */
7232 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
7233 /* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field value suitable for setting the register. */
7234 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
7235 
7236 /*
7237  * Field : reserved_23_16
7238  *
7239  * Reserved
7240  *
7241  * Field Access Macros:
7242  *
7243  */
7244 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_RSVD_23_16 register field. */
7245 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_RSVD_23_16_LSB 16
7246 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_RSVD_23_16 register field. */
7247 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_RSVD_23_16_MSB 23
7248 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_RSVD_23_16 register field. */
7249 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_RSVD_23_16_WIDTH 8
7250 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_RSVD_23_16 register field value. */
7251 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
7252 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_RSVD_23_16 register field value. */
7253 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
7254 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_RSVD_23_16 register field. */
7255 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_RSVD_23_16_RESET 0x0
7256 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_RSVD_23_16 field value from a register. */
7257 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
7258 /* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_RSVD_23_16 register field value suitable for setting the register. */
7259 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
7260 
7261 /*
7262  * Field : Mask Byte Control - mbc_0
7263  *
7264  * This array of bits are mask control bits for comparison of each of the MAC
7265  * Address bytes. When masked, the MAC does not compare the corresponding byte of
7266  * received DA or SA with the contents of MAC Address2 high and low registers. Each
7267  * bit controls the masking of the bytes. You can filter a group of addresses
7268  * (known as group address filtering) by masking one or more bytes of the address.
7269  *
7270  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
7271  *
7272  * Field Enumeration Values:
7273  *
7274  * Enum | Value | Description
7275  * :---------------------------------------------|:------|:------------
7276  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_E_UNMSKED | 0x0 |
7277  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_E_MSKED | 0x1 |
7278  *
7279  * Field Access Macros:
7280  *
7281  */
7282 /*
7283  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0
7284  *
7285  */
7286 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_E_UNMSKED 0x0
7287 /*
7288  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0
7289  *
7290  */
7291 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_E_MSKED 0x1
7292 
7293 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field. */
7294 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_LSB 24
7295 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field. */
7296 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_MSB 24
7297 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field. */
7298 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_WIDTH 1
7299 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field value. */
7300 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_SET_MSK 0x01000000
7301 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field value. */
7302 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_CLR_MSK 0xfeffffff
7303 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field. */
7304 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_RESET 0x0
7305 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 field value from a register. */
7306 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
7307 /* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field value suitable for setting the register. */
7308 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
7309 
7310 /*
7311  * Field : Mask Byte Control - mbc_1
7312  *
7313  * This array of bits are mask control bits for comparison of each of the MAC
7314  * Address bytes. When masked, the MAC does not compare the corresponding byte of
7315  * received DA or SA with the contents of MAC Address2 high and low registers. Each
7316  * bit controls the masking of the bytes. You can filter a group of addresses
7317  * (known as group address filtering) by masking one or more bytes of the address.
7318  *
7319  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
7320  *
7321  * Field Enumeration Values:
7322  *
7323  * Enum | Value | Description
7324  * :---------------------------------------------|:------|:------------
7325  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_E_UNMSKED | 0x0 |
7326  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_E_MSKED | 0x1 |
7327  *
7328  * Field Access Macros:
7329  *
7330  */
7331 /*
7332  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1
7333  *
7334  */
7335 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_E_UNMSKED 0x0
7336 /*
7337  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1
7338  *
7339  */
7340 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_E_MSKED 0x1
7341 
7342 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field. */
7343 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_LSB 25
7344 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field. */
7345 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_MSB 25
7346 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field. */
7347 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_WIDTH 1
7348 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field value. */
7349 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_SET_MSK 0x02000000
7350 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field value. */
7351 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_CLR_MSK 0xfdffffff
7352 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field. */
7353 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_RESET 0x0
7354 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 field value from a register. */
7355 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
7356 /* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field value suitable for setting the register. */
7357 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
7358 
7359 /*
7360  * Field : Mask Byte Control - mbc_2
7361  *
7362  * This array of bits are mask control bits for comparison of each of the MAC
7363  * Address bytes. When masked, the MAC does not compare the corresponding byte of
7364  * received DA or SA with the contents of MAC Address2 high and low registers. Each
7365  * bit controls the masking of the bytes. You can filter a group of addresses
7366  * (known as group address filtering) by masking one or more bytes of the address.
7367  *
7368  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
7369  *
7370  * Field Enumeration Values:
7371  *
7372  * Enum | Value | Description
7373  * :---------------------------------------------|:------|:------------
7374  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_E_UNMSKED | 0x0 |
7375  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_E_MSKED | 0x1 |
7376  *
7377  * Field Access Macros:
7378  *
7379  */
7380 /*
7381  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2
7382  *
7383  */
7384 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_E_UNMSKED 0x0
7385 /*
7386  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2
7387  *
7388  */
7389 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_E_MSKED 0x1
7390 
7391 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field. */
7392 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_LSB 26
7393 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field. */
7394 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_MSB 26
7395 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field. */
7396 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_WIDTH 1
7397 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field value. */
7398 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_SET_MSK 0x04000000
7399 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field value. */
7400 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_CLR_MSK 0xfbffffff
7401 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field. */
7402 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_RESET 0x0
7403 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 field value from a register. */
7404 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
7405 /* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field value suitable for setting the register. */
7406 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
7407 
7408 /*
7409  * Field : Mask Byte Control - mbc_3
7410  *
7411  * This array of bits are mask control bits for comparison of each of the MAC
7412  * Address bytes. When masked, the MAC does not compare the corresponding byte of
7413  * received DA or SA with the contents of MAC Address2 high and low registers. Each
7414  * bit controls the masking of the bytes. You can filter a group of addresses
7415  * (known as group address filtering) by masking one or more bytes of the address.
7416  *
7417  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
7418  *
7419  * Field Enumeration Values:
7420  *
7421  * Enum | Value | Description
7422  * :---------------------------------------------|:------|:------------
7423  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_E_UNMSKED | 0x0 |
7424  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_E_MSKED | 0x1 |
7425  *
7426  * Field Access Macros:
7427  *
7428  */
7429 /*
7430  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3
7431  *
7432  */
7433 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_E_UNMSKED 0x0
7434 /*
7435  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3
7436  *
7437  */
7438 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_E_MSKED 0x1
7439 
7440 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field. */
7441 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_LSB 27
7442 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field. */
7443 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_MSB 27
7444 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field. */
7445 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_WIDTH 1
7446 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field value. */
7447 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_SET_MSK 0x08000000
7448 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field value. */
7449 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_CLR_MSK 0xf7ffffff
7450 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field. */
7451 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_RESET 0x0
7452 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 field value from a register. */
7453 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
7454 /* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field value suitable for setting the register. */
7455 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
7456 
7457 /*
7458  * Field : Mask Byte Control - mbc_4
7459  *
7460  * This array of bits are mask control bits for comparison of each of the MAC
7461  * Address bytes. When masked, the MAC does not compare the corresponding byte of
7462  * received DA or SA with the contents of MAC Address2 high and low registers. Each
7463  * bit controls the masking of the bytes. You can filter a group of addresses
7464  * (known as group address filtering) by masking one or more bytes of the address.
7465  *
7466  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
7467  *
7468  * Field Enumeration Values:
7469  *
7470  * Enum | Value | Description
7471  * :---------------------------------------------|:------|:------------
7472  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_E_UNMSKED | 0x0 |
7473  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_E_MSKED | 0x1 |
7474  *
7475  * Field Access Macros:
7476  *
7477  */
7478 /*
7479  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4
7480  *
7481  */
7482 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_E_UNMSKED 0x0
7483 /*
7484  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4
7485  *
7486  */
7487 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_E_MSKED 0x1
7488 
7489 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field. */
7490 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_LSB 28
7491 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field. */
7492 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_MSB 28
7493 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field. */
7494 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_WIDTH 1
7495 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field value. */
7496 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_SET_MSK 0x10000000
7497 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field value. */
7498 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_CLR_MSK 0xefffffff
7499 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field. */
7500 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_RESET 0x0
7501 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 field value from a register. */
7502 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
7503 /* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field value suitable for setting the register. */
7504 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
7505 
7506 /*
7507  * Field : Mask Byte Control - mbc_5
7508  *
7509  * This array of bits are mask control bits for comparison of each of the MAC
7510  * Address bytes. When masked, the MAC does not compare the corresponding byte of
7511  * received DA or SA with the contents of MAC Address2 high and low registers. Each
7512  * bit controls the masking of the bytes. You can filter a group of addresses
7513  * (known as group address filtering) by masking one or more bytes of the address.
7514  *
7515  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
7516  *
7517  * Field Enumeration Values:
7518  *
7519  * Enum | Value | Description
7520  * :---------------------------------------------|:------|:------------
7521  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_E_UNMSKED | 0x0 |
7522  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_E_MSKED | 0x1 |
7523  *
7524  * Field Access Macros:
7525  *
7526  */
7527 /*
7528  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5
7529  *
7530  */
7531 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_E_UNMSKED 0x0
7532 /*
7533  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5
7534  *
7535  */
7536 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_E_MSKED 0x1
7537 
7538 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field. */
7539 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_LSB 29
7540 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field. */
7541 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_MSB 29
7542 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field. */
7543 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_WIDTH 1
7544 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field value. */
7545 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_SET_MSK 0x20000000
7546 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field value. */
7547 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_CLR_MSK 0xdfffffff
7548 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field. */
7549 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_RESET 0x0
7550 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 field value from a register. */
7551 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
7552 /* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field value suitable for setting the register. */
7553 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
7554 
7555 /*
7556  * Field : sa
7557  *
7558  * Source Address
7559  *
7560  * When this bit is set, the MAC Address2[47:0] is used to compare with the SA
7561  * fields of the received frame.
7562  *
7563  * When this bit is reset, the MAC Address2[47:0] is used to compare with the DA
7564  * fields of the received frame.
7565  *
7566  * Field Enumeration Values:
7567  *
7568  * Enum | Value | Description
7569  * :---------------------------------------|:------|:------------
7570  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_E_DISD | 0x0 |
7571  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_E_END | 0x1 |
7572  *
7573  * Field Access Macros:
7574  *
7575  */
7576 /*
7577  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA
7578  *
7579  */
7580 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_E_DISD 0x0
7581 /*
7582  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA
7583  *
7584  */
7585 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_E_END 0x1
7586 
7587 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field. */
7588 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_LSB 30
7589 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field. */
7590 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_MSB 30
7591 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field. */
7592 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_WIDTH 1
7593 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field value. */
7594 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_SET_MSK 0x40000000
7595 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field value. */
7596 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_CLR_MSK 0xbfffffff
7597 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field. */
7598 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_RESET 0x0
7599 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA field value from a register. */
7600 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
7601 /* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field value suitable for setting the register. */
7602 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
7603 
7604 /*
7605  * Field : ae
7606  *
7607  * Address Enable
7608  *
7609  * When this bit is set, the address filter module uses the third MAC address for
7610  * perfect filtering.
7611  *
7612  * When this bit is reset, the address filter module ignores the address for
7613  * filtering.
7614  *
7615  * Field Enumeration Values:
7616  *
7617  * Enum | Value | Description
7618  * :---------------------------------------|:------|:------------
7619  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_E_DISD | 0x0 |
7620  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_E_END | 0x1 |
7621  *
7622  * Field Access Macros:
7623  *
7624  */
7625 /*
7626  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE
7627  *
7628  */
7629 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_E_DISD 0x0
7630 /*
7631  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE
7632  *
7633  */
7634 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_E_END 0x1
7635 
7636 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field. */
7637 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_LSB 31
7638 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field. */
7639 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_MSB 31
7640 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field. */
7641 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_WIDTH 1
7642 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field value. */
7643 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_SET_MSK 0x80000000
7644 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field value. */
7645 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_CLR_MSK 0x7fffffff
7646 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field. */
7647 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_RESET 0x0
7648 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE field value from a register. */
7649 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
7650 /* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field value suitable for setting the register. */
7651 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
7652 
7653 #ifndef __ASSEMBLY__
7654 /*
7655  * WARNING: The C register and register group struct declarations are provided for
7656  * convenience and illustrative purposes. They should, however, be used with
7657  * caution as the C language standard provides no guarantees about the alignment or
7658  * atomicity of device memory accesses. The recommended practice for writing
7659  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7660  * alt_write_word() functions.
7661  *
7662  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR2_HIGH.
7663  */
7664 struct ALT_EMAC_GMAC_MAC_ADDR2_HIGH_s
7665 {
7666  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI */
7667  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR2_HIGH_RSVD_23_16 */
7668  uint32_t mbc_0 : 1; /* Mask Byte Control */
7669  uint32_t mbc_1 : 1; /* Mask Byte Control */
7670  uint32_t mbc_2 : 1; /* Mask Byte Control */
7671  uint32_t mbc_3 : 1; /* Mask Byte Control */
7672  uint32_t mbc_4 : 1; /* Mask Byte Control */
7673  uint32_t mbc_5 : 1; /* Mask Byte Control */
7674  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA */
7675  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE */
7676 };
7677 
7678 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR2_HIGH. */
7679 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR2_HIGH_s ALT_EMAC_GMAC_MAC_ADDR2_HIGH_t;
7680 #endif /* __ASSEMBLY__ */
7681 
7682 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH register. */
7683 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_RESET 0x0000ffff
7684 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH register from the beginning of the component. */
7685 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_OFST 0x50
7686 /* The address of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH register. */
7687 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR2_HIGH_OFST))
7688 
7689 /*
7690  * Register : gmacgrp_mac_address2_low
7691  *
7692  * <b> Register 21 (MAC Address2 Low Register) </b>
7693  *
7694  * The MAC Address2 Low register holds the lower 32 bits of the third 6-byte MAC
7695  * address of the station.
7696  *
7697  * Register Layout
7698  *
7699  * Bits | Access | Reset | Description
7700  * :-------|:-------|:-----------|:-----------------------------------
7701  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO
7702  *
7703  */
7704 /*
7705  * Field : addrlo
7706  *
7707  * MAC Address2 [31:0]
7708  *
7709  * This field contains the lower 32 bits of the third 6-byte MAC address. The
7710  * content of this field is undefined until loaded by the Application after the
7711  * initialization process.
7712  *
7713  * Field Access Macros:
7714  *
7715  */
7716 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field. */
7717 #define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_LSB 0
7718 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field. */
7719 #define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_MSB 31
7720 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field. */
7721 #define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_WIDTH 32
7722 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field value. */
7723 #define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_SET_MSK 0xffffffff
7724 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field value. */
7725 #define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_CLR_MSK 0x00000000
7726 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field. */
7727 #define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_RESET 0xffffffff
7728 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO field value from a register. */
7729 #define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
7730 /* Produces a ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field value suitable for setting the register. */
7731 #define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
7732 
7733 #ifndef __ASSEMBLY__
7734 /*
7735  * WARNING: The C register and register group struct declarations are provided for
7736  * convenience and illustrative purposes. They should, however, be used with
7737  * caution as the C language standard provides no guarantees about the alignment or
7738  * atomicity of device memory accesses. The recommended practice for writing
7739  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7740  * alt_write_word() functions.
7741  *
7742  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR2_LOW.
7743  */
7744 struct ALT_EMAC_GMAC_MAC_ADDR2_LOW_s
7745 {
7746  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO */
7747 };
7748 
7749 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR2_LOW. */
7750 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR2_LOW_s ALT_EMAC_GMAC_MAC_ADDR2_LOW_t;
7751 #endif /* __ASSEMBLY__ */
7752 
7753 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_LOW register. */
7754 #define ALT_EMAC_GMAC_MAC_ADDR2_LOW_RESET 0xffffffff
7755 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR2_LOW register from the beginning of the component. */
7756 #define ALT_EMAC_GMAC_MAC_ADDR2_LOW_OFST 0x54
7757 /* The address of the ALT_EMAC_GMAC_MAC_ADDR2_LOW register. */
7758 #define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR2_LOW_OFST))
7759 
7760 /*
7761  * Register : gmacgrp_mac_address3_high
7762  *
7763  * <b> Register 22 (MAC Address3 High Register) </b>
7764  *
7765  * The MAC Address3 High register holds the upper 16 bits of the fourth 6-byte MAC
7766  * address of the station.
7767  *
7768  * If the MAC address registers are configured to be double-synchronized to the
7769  * (G)MII clock domains, then
7770  *
7771  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
7772  * or Bits[7:0] (in big-endian mode) of the MAC Address3 Low Register are written.
7773  * For proper synchronization updates, consecutive writes to this MAC Address3 Low
7774  * Register must be performed after at least four clock cycles in the destination
7775  * clock domain.
7776  *
7777  * Register Layout
7778  *
7779  * Bits | Access | Reset | Description
7780  * :--------|:-------|:-------|:----------------------------------------
7781  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI
7782  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR3_HIGH_RSVD_23_16
7783  * [24] | RW | 0x0 | Mask Byte Control
7784  * [25] | RW | 0x0 | Mask Byte Control
7785  * [26] | RW | 0x0 | Mask Byte Control
7786  * [27] | RW | 0x0 | Mask Byte Control
7787  * [28] | RW | 0x0 | Mask Byte Control
7788  * [29] | RW | 0x0 | Mask Byte Control
7789  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA
7790  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE
7791  *
7792  */
7793 /*
7794  * Field : addrhi
7795  *
7796  * MAC Address3 [47:32]
7797  *
7798  * This field contains the upper 16 bits (47:32) of the fourth 6-byte MAC address.
7799  *
7800  * Field Access Macros:
7801  *
7802  */
7803 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field. */
7804 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_LSB 0
7805 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field. */
7806 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_MSB 15
7807 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field. */
7808 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_WIDTH 16
7809 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field value. */
7810 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_SET_MSK 0x0000ffff
7811 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field value. */
7812 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_CLR_MSK 0xffff0000
7813 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field. */
7814 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_RESET 0xffff
7815 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI field value from a register. */
7816 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
7817 /* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field value suitable for setting the register. */
7818 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
7819 
7820 /*
7821  * Field : reserved_23_16
7822  *
7823  * Reserved
7824  *
7825  * Field Access Macros:
7826  *
7827  */
7828 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_RSVD_23_16 register field. */
7829 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_RSVD_23_16_LSB 16
7830 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_RSVD_23_16 register field. */
7831 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_RSVD_23_16_MSB 23
7832 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_RSVD_23_16 register field. */
7833 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_RSVD_23_16_WIDTH 8
7834 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_RSVD_23_16 register field value. */
7835 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
7836 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_RSVD_23_16 register field value. */
7837 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
7838 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_RSVD_23_16 register field. */
7839 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_RSVD_23_16_RESET 0x0
7840 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_RSVD_23_16 field value from a register. */
7841 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
7842 /* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_RSVD_23_16 register field value suitable for setting the register. */
7843 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
7844 
7845 /*
7846  * Field : Mask Byte Control - mbc_0
7847  *
7848  * This array of bits are mask control bits for comparison of each of the MAC
7849  * Address bytes. When masked, the MAC does not compare the corresponding byte of
7850  * received DA or SA with the contents of MAC Address3 high and low registers. Each
7851  * bit controls the masking of the bytes. You can filter a group of addresses
7852  * (known as group address filtering) by masking one or more bytes of the address.
7853  *
7854  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
7855  *
7856  * Field Enumeration Values:
7857  *
7858  * Enum | Value | Description
7859  * :---------------------------------------------|:------|:------------
7860  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_E_UNMSKED | 0x0 |
7861  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_E_MSKED | 0x1 |
7862  *
7863  * Field Access Macros:
7864  *
7865  */
7866 /*
7867  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0
7868  *
7869  */
7870 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_E_UNMSKED 0x0
7871 /*
7872  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0
7873  *
7874  */
7875 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_E_MSKED 0x1
7876 
7877 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field. */
7878 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_LSB 24
7879 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field. */
7880 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_MSB 24
7881 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field. */
7882 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_WIDTH 1
7883 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field value. */
7884 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_SET_MSK 0x01000000
7885 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field value. */
7886 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_CLR_MSK 0xfeffffff
7887 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field. */
7888 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_RESET 0x0
7889 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 field value from a register. */
7890 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
7891 /* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field value suitable for setting the register. */
7892 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
7893 
7894 /*
7895  * Field : Mask Byte Control - mbc_1
7896  *
7897  * This array of bits are mask control bits for comparison of each of the MAC
7898  * Address bytes. When masked, the MAC does not compare the corresponding byte of
7899  * received DA or SA with the contents of MAC Address3 high and low registers. Each
7900  * bit controls the masking of the bytes. You can filter a group of addresses
7901  * (known as group address filtering) by masking one or more bytes of the address.
7902  *
7903  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
7904  *
7905  * Field Enumeration Values:
7906  *
7907  * Enum | Value | Description
7908  * :---------------------------------------------|:------|:------------
7909  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_E_UNMSKED | 0x0 |
7910  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_E_MSKED | 0x1 |
7911  *
7912  * Field Access Macros:
7913  *
7914  */
7915 /*
7916  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1
7917  *
7918  */
7919 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_E_UNMSKED 0x0
7920 /*
7921  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1
7922  *
7923  */
7924 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_E_MSKED 0x1
7925 
7926 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field. */
7927 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_LSB 25
7928 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field. */
7929 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_MSB 25
7930 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field. */
7931 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_WIDTH 1
7932 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field value. */
7933 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_SET_MSK 0x02000000
7934 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field value. */
7935 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_CLR_MSK 0xfdffffff
7936 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field. */
7937 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_RESET 0x0
7938 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 field value from a register. */
7939 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
7940 /* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field value suitable for setting the register. */
7941 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
7942 
7943 /*
7944  * Field : Mask Byte Control - mbc_2
7945  *
7946  * This array of bits are mask control bits for comparison of each of the MAC
7947  * Address bytes. When masked, the MAC does not compare the corresponding byte of
7948  * received DA or SA with the contents of MAC Address3 high and low registers. Each
7949  * bit controls the masking of the bytes. You can filter a group of addresses
7950  * (known as group address filtering) by masking one or more bytes of the address.
7951  *
7952  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
7953  *
7954  * Field Enumeration Values:
7955  *
7956  * Enum | Value | Description
7957  * :---------------------------------------------|:------|:------------
7958  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_E_UNMSKED | 0x0 |
7959  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_E_MSKED | 0x1 |
7960  *
7961  * Field Access Macros:
7962  *
7963  */
7964 /*
7965  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2
7966  *
7967  */
7968 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_E_UNMSKED 0x0
7969 /*
7970  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2
7971  *
7972  */
7973 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_E_MSKED 0x1
7974 
7975 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field. */
7976 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_LSB 26
7977 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field. */
7978 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_MSB 26
7979 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field. */
7980 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_WIDTH 1
7981 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field value. */
7982 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_SET_MSK 0x04000000
7983 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field value. */
7984 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_CLR_MSK 0xfbffffff
7985 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field. */
7986 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_RESET 0x0
7987 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 field value from a register. */
7988 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
7989 /* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field value suitable for setting the register. */
7990 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
7991 
7992 /*
7993  * Field : Mask Byte Control - mbc_3
7994  *
7995  * This array of bits are mask control bits for comparison of each of the MAC
7996  * Address bytes. When masked, the MAC does not compare the corresponding byte of
7997  * received DA or SA with the contents of MAC Address3 high and low registers. Each
7998  * bit controls the masking of the bytes. You can filter a group of addresses
7999  * (known as group address filtering) by masking one or more bytes of the address.
8000  *
8001  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
8002  *
8003  * Field Enumeration Values:
8004  *
8005  * Enum | Value | Description
8006  * :---------------------------------------------|:------|:------------
8007  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_E_UNMSKED | 0x0 |
8008  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_E_MSKED | 0x1 |
8009  *
8010  * Field Access Macros:
8011  *
8012  */
8013 /*
8014  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3
8015  *
8016  */
8017 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_E_UNMSKED 0x0
8018 /*
8019  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3
8020  *
8021  */
8022 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_E_MSKED 0x1
8023 
8024 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field. */
8025 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_LSB 27
8026 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field. */
8027 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_MSB 27
8028 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field. */
8029 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_WIDTH 1
8030 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field value. */
8031 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_SET_MSK 0x08000000
8032 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field value. */
8033 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_CLR_MSK 0xf7ffffff
8034 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field. */
8035 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_RESET 0x0
8036 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 field value from a register. */
8037 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
8038 /* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field value suitable for setting the register. */
8039 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
8040 
8041 /*
8042  * Field : Mask Byte Control - mbc_4
8043  *
8044  * This array of bits are mask control bits for comparison of each of the MAC
8045  * Address bytes. When masked, the MAC does not compare the corresponding byte of
8046  * received DA or SA with the contents of MAC Address3 high and low registers. Each
8047  * bit controls the masking of the bytes. You can filter a group of addresses
8048  * (known as group address filtering) by masking one or more bytes of the address.
8049  *
8050  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
8051  *
8052  * Field Enumeration Values:
8053  *
8054  * Enum | Value | Description
8055  * :---------------------------------------------|:------|:------------
8056  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_E_UNMSKED | 0x0 |
8057  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_E_MSKED | 0x1 |
8058  *
8059  * Field Access Macros:
8060  *
8061  */
8062 /*
8063  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4
8064  *
8065  */
8066 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_E_UNMSKED 0x0
8067 /*
8068  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4
8069  *
8070  */
8071 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_E_MSKED 0x1
8072 
8073 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field. */
8074 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_LSB 28
8075 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field. */
8076 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_MSB 28
8077 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field. */
8078 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_WIDTH 1
8079 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field value. */
8080 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_SET_MSK 0x10000000
8081 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field value. */
8082 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_CLR_MSK 0xefffffff
8083 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field. */
8084 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_RESET 0x0
8085 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 field value from a register. */
8086 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
8087 /* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field value suitable for setting the register. */
8088 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
8089 
8090 /*
8091  * Field : Mask Byte Control - mbc_5
8092  *
8093  * This array of bits are mask control bits for comparison of each of the MAC
8094  * Address bytes. When masked, the MAC does not compare the corresponding byte of
8095  * received DA or SA with the contents of MAC Address3 high and low registers. Each
8096  * bit controls the masking of the bytes. You can filter a group of addresses
8097  * (known as group address filtering) by masking one or more bytes of the address.
8098  *
8099  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
8100  *
8101  * Field Enumeration Values:
8102  *
8103  * Enum | Value | Description
8104  * :---------------------------------------------|:------|:------------
8105  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_E_UNMSKED | 0x0 |
8106  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_E_MSKED | 0x1 |
8107  *
8108  * Field Access Macros:
8109  *
8110  */
8111 /*
8112  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5
8113  *
8114  */
8115 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_E_UNMSKED 0x0
8116 /*
8117  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5
8118  *
8119  */
8120 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_E_MSKED 0x1
8121 
8122 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field. */
8123 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_LSB 29
8124 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field. */
8125 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_MSB 29
8126 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field. */
8127 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_WIDTH 1
8128 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field value. */
8129 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_SET_MSK 0x20000000
8130 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field value. */
8131 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_CLR_MSK 0xdfffffff
8132 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field. */
8133 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_RESET 0x0
8134 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 field value from a register. */
8135 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
8136 /* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field value suitable for setting the register. */
8137 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
8138 
8139 /*
8140  * Field : sa
8141  *
8142  * Source Address
8143  *
8144  * When this bit is set, the MAC Address3[47:0] is used to compare with the SA
8145  * fields of the received frame.
8146  *
8147  * When this bit is reset, the MAC Address3[47:0] is used to compare with the DA
8148  * fields of the received frame.
8149  *
8150  * Field Enumeration Values:
8151  *
8152  * Enum | Value | Description
8153  * :---------------------------------------|:------|:------------
8154  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_E_DISD | 0x0 |
8155  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_E_END | 0x1 |
8156  *
8157  * Field Access Macros:
8158  *
8159  */
8160 /*
8161  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA
8162  *
8163  */
8164 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_E_DISD 0x0
8165 /*
8166  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA
8167  *
8168  */
8169 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_E_END 0x1
8170 
8171 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field. */
8172 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_LSB 30
8173 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field. */
8174 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_MSB 30
8175 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field. */
8176 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_WIDTH 1
8177 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field value. */
8178 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_SET_MSK 0x40000000
8179 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field value. */
8180 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_CLR_MSK 0xbfffffff
8181 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field. */
8182 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_RESET 0x0
8183 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA field value from a register. */
8184 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
8185 /* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field value suitable for setting the register. */
8186 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
8187 
8188 /*
8189  * Field : ae
8190  *
8191  * Address Enable
8192  *
8193  * When this bit is set, the address filter module uses the fourth MAC address for
8194  * perfect filtering.
8195  *
8196  * When this bit is reset, the address filter module ignores the address for
8197  * filtering.
8198  *
8199  * Field Enumeration Values:
8200  *
8201  * Enum | Value | Description
8202  * :---------------------------------------|:------|:------------
8203  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_E_DISD | 0x0 |
8204  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_E_END | 0x1 |
8205  *
8206  * Field Access Macros:
8207  *
8208  */
8209 /*
8210  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE
8211  *
8212  */
8213 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_E_DISD 0x0
8214 /*
8215  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE
8216  *
8217  */
8218 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_E_END 0x1
8219 
8220 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field. */
8221 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_LSB 31
8222 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field. */
8223 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_MSB 31
8224 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field. */
8225 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_WIDTH 1
8226 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field value. */
8227 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_SET_MSK 0x80000000
8228 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field value. */
8229 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_CLR_MSK 0x7fffffff
8230 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field. */
8231 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_RESET 0x0
8232 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE field value from a register. */
8233 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
8234 /* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field value suitable for setting the register. */
8235 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
8236 
8237 #ifndef __ASSEMBLY__
8238 /*
8239  * WARNING: The C register and register group struct declarations are provided for
8240  * convenience and illustrative purposes. They should, however, be used with
8241  * caution as the C language standard provides no guarantees about the alignment or
8242  * atomicity of device memory accesses. The recommended practice for writing
8243  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8244  * alt_write_word() functions.
8245  *
8246  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR3_HIGH.
8247  */
8248 struct ALT_EMAC_GMAC_MAC_ADDR3_HIGH_s
8249 {
8250  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI */
8251  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR3_HIGH_RSVD_23_16 */
8252  uint32_t mbc_0 : 1; /* Mask Byte Control */
8253  uint32_t mbc_1 : 1; /* Mask Byte Control */
8254  uint32_t mbc_2 : 1; /* Mask Byte Control */
8255  uint32_t mbc_3 : 1; /* Mask Byte Control */
8256  uint32_t mbc_4 : 1; /* Mask Byte Control */
8257  uint32_t mbc_5 : 1; /* Mask Byte Control */
8258  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA */
8259  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE */
8260 };
8261 
8262 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR3_HIGH. */
8263 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR3_HIGH_s ALT_EMAC_GMAC_MAC_ADDR3_HIGH_t;
8264 #endif /* __ASSEMBLY__ */
8265 
8266 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH register. */
8267 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_RESET 0x0000ffff
8268 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH register from the beginning of the component. */
8269 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_OFST 0x58
8270 /* The address of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH register. */
8271 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR3_HIGH_OFST))
8272 
8273 /*
8274  * Register : gmacgrp_mac_address3_low
8275  *
8276  * <b> Register 23 (MAC Address3 Low Register) </b>
8277  *
8278  * The MAC Address3 Low register holds the lower 32 bits of the fourth 6-byte MAC
8279  * address of the station.
8280  *
8281  * Register Layout
8282  *
8283  * Bits | Access | Reset | Description
8284  * :-------|:-------|:-----------|:-----------------------------------
8285  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO
8286  *
8287  */
8288 /*
8289  * Field : addrlo
8290  *
8291  * MAC Address3 [31:0]
8292  *
8293  * This field contains the lower 32 bits of the fourth 6-byte MAC address. The
8294  * content of this field is undefined until loaded by the Application after the
8295  * initialization process.
8296  *
8297  * Field Access Macros:
8298  *
8299  */
8300 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field. */
8301 #define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_LSB 0
8302 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field. */
8303 #define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_MSB 31
8304 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field. */
8305 #define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_WIDTH 32
8306 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field value. */
8307 #define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_SET_MSK 0xffffffff
8308 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field value. */
8309 #define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_CLR_MSK 0x00000000
8310 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field. */
8311 #define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_RESET 0xffffffff
8312 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO field value from a register. */
8313 #define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
8314 /* Produces a ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field value suitable for setting the register. */
8315 #define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
8316 
8317 #ifndef __ASSEMBLY__
8318 /*
8319  * WARNING: The C register and register group struct declarations are provided for
8320  * convenience and illustrative purposes. They should, however, be used with
8321  * caution as the C language standard provides no guarantees about the alignment or
8322  * atomicity of device memory accesses. The recommended practice for writing
8323  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8324  * alt_write_word() functions.
8325  *
8326  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR3_LOW.
8327  */
8328 struct ALT_EMAC_GMAC_MAC_ADDR3_LOW_s
8329 {
8330  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO */
8331 };
8332 
8333 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR3_LOW. */
8334 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR3_LOW_s ALT_EMAC_GMAC_MAC_ADDR3_LOW_t;
8335 #endif /* __ASSEMBLY__ */
8336 
8337 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_LOW register. */
8338 #define ALT_EMAC_GMAC_MAC_ADDR3_LOW_RESET 0xffffffff
8339 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR3_LOW register from the beginning of the component. */
8340 #define ALT_EMAC_GMAC_MAC_ADDR3_LOW_OFST 0x5c
8341 /* The address of the ALT_EMAC_GMAC_MAC_ADDR3_LOW register. */
8342 #define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR3_LOW_OFST))
8343 
8344 /*
8345  * Register : gmacgrp_mac_address4_high
8346  *
8347  * <b> Register 24 (MAC Address4 High Register) </b>
8348  *
8349  * The MAC Address4 High register holds the upper 16 bits of the fifth 6-byte MAC
8350  * address of the station.
8351  *
8352  * If the MAC address registers are configured to be double-synchronized to the
8353  * (G)MII clock domains, then
8354  *
8355  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
8356  * or Bits[7:0] (in big-endian mode) of the MAC Address4 Low Register are written.
8357  * For proper synchronization updates, consecutive writes to this MAC Address4 Low
8358  * Register must be performed after at least four clock cycles in the destination
8359  * clock domain.
8360  *
8361  * Register Layout
8362  *
8363  * Bits | Access | Reset | Description
8364  * :--------|:-------|:-------|:----------------------------------------
8365  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI
8366  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR4_HIGH_RSVD_23_16
8367  * [24] | RW | 0x0 | Mask Byte Control
8368  * [25] | RW | 0x0 | Mask Byte Control
8369  * [26] | RW | 0x0 | Mask Byte Control
8370  * [27] | RW | 0x0 | Mask Byte Control
8371  * [28] | RW | 0x0 | Mask Byte Control
8372  * [29] | RW | 0x0 | Mask Byte Control
8373  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA
8374  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE
8375  *
8376  */
8377 /*
8378  * Field : addrhi
8379  *
8380  * MAC Address4 [47:32]
8381  *
8382  * This field contains the upper 16 bits (47:32) of the fifth 6-byte MAC address.
8383  *
8384  * Field Access Macros:
8385  *
8386  */
8387 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field. */
8388 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_LSB 0
8389 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field. */
8390 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_MSB 15
8391 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field. */
8392 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_WIDTH 16
8393 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field value. */
8394 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_SET_MSK 0x0000ffff
8395 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field value. */
8396 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_CLR_MSK 0xffff0000
8397 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field. */
8398 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_RESET 0xffff
8399 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI field value from a register. */
8400 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
8401 /* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field value suitable for setting the register. */
8402 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
8403 
8404 /*
8405  * Field : reserved_23_16
8406  *
8407  * Reserved
8408  *
8409  * Field Access Macros:
8410  *
8411  */
8412 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_RSVD_23_16 register field. */
8413 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_RSVD_23_16_LSB 16
8414 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_RSVD_23_16 register field. */
8415 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_RSVD_23_16_MSB 23
8416 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_RSVD_23_16 register field. */
8417 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_RSVD_23_16_WIDTH 8
8418 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_RSVD_23_16 register field value. */
8419 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
8420 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_RSVD_23_16 register field value. */
8421 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
8422 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_RSVD_23_16 register field. */
8423 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_RSVD_23_16_RESET 0x0
8424 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_RSVD_23_16 field value from a register. */
8425 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
8426 /* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_RSVD_23_16 register field value suitable for setting the register. */
8427 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
8428 
8429 /*
8430  * Field : Mask Byte Control - mbc_0
8431  *
8432  * This array of bits are mask control bits for comparison of each of the MAC
8433  * Address bytes. When masked, the MAC does not compare the corresponding byte of
8434  * received DA or SA with the contents of MAC Address4 high and low registers. Each
8435  * bit controls the masking of the bytes. You can filter a group of addresses
8436  * (known as group address filtering) by masking one or more bytes of the address.
8437  *
8438  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
8439  *
8440  * Field Enumeration Values:
8441  *
8442  * Enum | Value | Description
8443  * :---------------------------------------------|:------|:------------
8444  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_E_UNMSKED | 0x0 |
8445  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_E_MSKED | 0x1 |
8446  *
8447  * Field Access Macros:
8448  *
8449  */
8450 /*
8451  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0
8452  *
8453  */
8454 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_E_UNMSKED 0x0
8455 /*
8456  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0
8457  *
8458  */
8459 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_E_MSKED 0x1
8460 
8461 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field. */
8462 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_LSB 24
8463 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field. */
8464 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_MSB 24
8465 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field. */
8466 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_WIDTH 1
8467 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field value. */
8468 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_SET_MSK 0x01000000
8469 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field value. */
8470 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_CLR_MSK 0xfeffffff
8471 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field. */
8472 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_RESET 0x0
8473 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 field value from a register. */
8474 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
8475 /* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field value suitable for setting the register. */
8476 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
8477 
8478 /*
8479  * Field : Mask Byte Control - mbc_1
8480  *
8481  * This array of bits are mask control bits for comparison of each of the MAC
8482  * Address bytes. When masked, the MAC does not compare the corresponding byte of
8483  * received DA or SA with the contents of MAC Address4 high and low registers. Each
8484  * bit controls the masking of the bytes. You can filter a group of addresses
8485  * (known as group address filtering) by masking one or more bytes of the address.
8486  *
8487  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
8488  *
8489  * Field Enumeration Values:
8490  *
8491  * Enum | Value | Description
8492  * :---------------------------------------------|:------|:------------
8493  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_E_UNMSKED | 0x0 |
8494  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_E_MSKED | 0x1 |
8495  *
8496  * Field Access Macros:
8497  *
8498  */
8499 /*
8500  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1
8501  *
8502  */
8503 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_E_UNMSKED 0x0
8504 /*
8505  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1
8506  *
8507  */
8508 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_E_MSKED 0x1
8509 
8510 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field. */
8511 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_LSB 25
8512 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field. */
8513 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_MSB 25
8514 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field. */
8515 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_WIDTH 1
8516 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field value. */
8517 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_SET_MSK 0x02000000
8518 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field value. */
8519 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_CLR_MSK 0xfdffffff
8520 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field. */
8521 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_RESET 0x0
8522 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 field value from a register. */
8523 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
8524 /* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field value suitable for setting the register. */
8525 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
8526 
8527 /*
8528  * Field : Mask Byte Control - mbc_2
8529  *
8530  * This array of bits are mask control bits for comparison of each of the MAC
8531  * Address bytes. When masked, the MAC does not compare the corresponding byte of
8532  * received DA or SA with the contents of MAC Address4 high and low registers. Each
8533  * bit controls the masking of the bytes. You can filter a group of addresses
8534  * (known as group address filtering) by masking one or more bytes of the address.
8535  *
8536  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
8537  *
8538  * Field Enumeration Values:
8539  *
8540  * Enum | Value | Description
8541  * :---------------------------------------------|:------|:------------
8542  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_E_UNMSKED | 0x0 |
8543  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_E_MSKED | 0x1 |
8544  *
8545  * Field Access Macros:
8546  *
8547  */
8548 /*
8549  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2
8550  *
8551  */
8552 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_E_UNMSKED 0x0
8553 /*
8554  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2
8555  *
8556  */
8557 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_E_MSKED 0x1
8558 
8559 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field. */
8560 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_LSB 26
8561 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field. */
8562 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_MSB 26
8563 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field. */
8564 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_WIDTH 1
8565 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field value. */
8566 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_SET_MSK 0x04000000
8567 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field value. */
8568 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_CLR_MSK 0xfbffffff
8569 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field. */
8570 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_RESET 0x0
8571 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 field value from a register. */
8572 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
8573 /* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field value suitable for setting the register. */
8574 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
8575 
8576 /*
8577  * Field : Mask Byte Control - mbc_3
8578  *
8579  * This array of bits are mask control bits for comparison of each of the MAC
8580  * Address bytes. When masked, the MAC does not compare the corresponding byte of
8581  * received DA or SA with the contents of MAC Address4 high and low registers. Each
8582  * bit controls the masking of the bytes. You can filter a group of addresses
8583  * (known as group address filtering) by masking one or more bytes of the address.
8584  *
8585  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
8586  *
8587  * Field Enumeration Values:
8588  *
8589  * Enum | Value | Description
8590  * :---------------------------------------------|:------|:------------
8591  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_E_UNMSKED | 0x0 |
8592  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_E_MSKED | 0x1 |
8593  *
8594  * Field Access Macros:
8595  *
8596  */
8597 /*
8598  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3
8599  *
8600  */
8601 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_E_UNMSKED 0x0
8602 /*
8603  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3
8604  *
8605  */
8606 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_E_MSKED 0x1
8607 
8608 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field. */
8609 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_LSB 27
8610 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field. */
8611 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_MSB 27
8612 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field. */
8613 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_WIDTH 1
8614 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field value. */
8615 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_SET_MSK 0x08000000
8616 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field value. */
8617 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_CLR_MSK 0xf7ffffff
8618 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field. */
8619 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_RESET 0x0
8620 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 field value from a register. */
8621 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
8622 /* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field value suitable for setting the register. */
8623 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
8624 
8625 /*
8626  * Field : Mask Byte Control - mbc_4
8627  *
8628  * This array of bits are mask control bits for comparison of each of the MAC
8629  * Address bytes. When masked, the MAC does not compare the corresponding byte of
8630  * received DA or SA with the contents of MAC Address4 high and low registers. Each
8631  * bit controls the masking of the bytes. You can filter a group of addresses
8632  * (known as group address filtering) by masking one or more bytes of the address.
8633  *
8634  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
8635  *
8636  * Field Enumeration Values:
8637  *
8638  * Enum | Value | Description
8639  * :---------------------------------------------|:------|:------------
8640  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_E_UNMSKED | 0x0 |
8641  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_E_MSKED | 0x1 |
8642  *
8643  * Field Access Macros:
8644  *
8645  */
8646 /*
8647  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4
8648  *
8649  */
8650 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_E_UNMSKED 0x0
8651 /*
8652  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4
8653  *
8654  */
8655 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_E_MSKED 0x1
8656 
8657 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field. */
8658 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_LSB 28
8659 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field. */
8660 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_MSB 28
8661 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field. */
8662 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_WIDTH 1
8663 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field value. */
8664 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_SET_MSK 0x10000000
8665 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field value. */
8666 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_CLR_MSK 0xefffffff
8667 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field. */
8668 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_RESET 0x0
8669 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 field value from a register. */
8670 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
8671 /* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field value suitable for setting the register. */
8672 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
8673 
8674 /*
8675  * Field : Mask Byte Control - mbc_5
8676  *
8677  * This array of bits are mask control bits for comparison of each of the MAC
8678  * Address bytes. When masked, the MAC does not compare the corresponding byte of
8679  * received DA or SA with the contents of MAC Address4 high and low registers. Each
8680  * bit controls the masking of the bytes. You can filter a group of addresses
8681  * (known as group address filtering) by masking one or more bytes of the address.
8682  *
8683  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
8684  *
8685  * Field Enumeration Values:
8686  *
8687  * Enum | Value | Description
8688  * :---------------------------------------------|:------|:------------
8689  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_E_UNMSKED | 0x0 |
8690  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_E_MSKED | 0x1 |
8691  *
8692  * Field Access Macros:
8693  *
8694  */
8695 /*
8696  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5
8697  *
8698  */
8699 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_E_UNMSKED 0x0
8700 /*
8701  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5
8702  *
8703  */
8704 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_E_MSKED 0x1
8705 
8706 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field. */
8707 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_LSB 29
8708 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field. */
8709 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_MSB 29
8710 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field. */
8711 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_WIDTH 1
8712 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field value. */
8713 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_SET_MSK 0x20000000
8714 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field value. */
8715 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_CLR_MSK 0xdfffffff
8716 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field. */
8717 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_RESET 0x0
8718 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 field value from a register. */
8719 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
8720 /* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field value suitable for setting the register. */
8721 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
8722 
8723 /*
8724  * Field : sa
8725  *
8726  * Source Address
8727  *
8728  * When this bit is set, the MAC Address4[47:0] is used to compare with the SA
8729  * fields of the received frame.
8730  *
8731  * When this bit is reset, the MAC Address4[47:0] is used to compare with the DA
8732  * fields of the received frame.
8733  *
8734  * Field Enumeration Values:
8735  *
8736  * Enum | Value | Description
8737  * :---------------------------------------|:------|:------------
8738  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_E_DISD | 0x0 |
8739  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_E_END | 0x1 |
8740  *
8741  * Field Access Macros:
8742  *
8743  */
8744 /*
8745  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA
8746  *
8747  */
8748 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_E_DISD 0x0
8749 /*
8750  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA
8751  *
8752  */
8753 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_E_END 0x1
8754 
8755 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field. */
8756 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_LSB 30
8757 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field. */
8758 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_MSB 30
8759 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field. */
8760 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_WIDTH 1
8761 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field value. */
8762 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_SET_MSK 0x40000000
8763 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field value. */
8764 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_CLR_MSK 0xbfffffff
8765 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field. */
8766 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_RESET 0x0
8767 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA field value from a register. */
8768 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
8769 /* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field value suitable for setting the register. */
8770 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
8771 
8772 /*
8773  * Field : ae
8774  *
8775  * Address Enable
8776  *
8777  * When this bit is set, the address filter module uses the fifth MAC address for
8778  * perfect filtering.
8779  *
8780  * When this bit is reset, the address filter module ignores the address for
8781  * filtering.
8782  *
8783  * Field Enumeration Values:
8784  *
8785  * Enum | Value | Description
8786  * :---------------------------------------|:------|:------------
8787  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_E_DISD | 0x0 |
8788  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_E_END | 0x1 |
8789  *
8790  * Field Access Macros:
8791  *
8792  */
8793 /*
8794  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE
8795  *
8796  */
8797 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_E_DISD 0x0
8798 /*
8799  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE
8800  *
8801  */
8802 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_E_END 0x1
8803 
8804 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field. */
8805 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_LSB 31
8806 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field. */
8807 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_MSB 31
8808 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field. */
8809 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_WIDTH 1
8810 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field value. */
8811 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_SET_MSK 0x80000000
8812 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field value. */
8813 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_CLR_MSK 0x7fffffff
8814 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field. */
8815 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_RESET 0x0
8816 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE field value from a register. */
8817 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
8818 /* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field value suitable for setting the register. */
8819 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
8820 
8821 #ifndef __ASSEMBLY__
8822 /*
8823  * WARNING: The C register and register group struct declarations are provided for
8824  * convenience and illustrative purposes. They should, however, be used with
8825  * caution as the C language standard provides no guarantees about the alignment or
8826  * atomicity of device memory accesses. The recommended practice for writing
8827  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8828  * alt_write_word() functions.
8829  *
8830  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR4_HIGH.
8831  */
8832 struct ALT_EMAC_GMAC_MAC_ADDR4_HIGH_s
8833 {
8834  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI */
8835  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR4_HIGH_RSVD_23_16 */
8836  uint32_t mbc_0 : 1; /* Mask Byte Control */
8837  uint32_t mbc_1 : 1; /* Mask Byte Control */
8838  uint32_t mbc_2 : 1; /* Mask Byte Control */
8839  uint32_t mbc_3 : 1; /* Mask Byte Control */
8840  uint32_t mbc_4 : 1; /* Mask Byte Control */
8841  uint32_t mbc_5 : 1; /* Mask Byte Control */
8842  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA */
8843  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE */
8844 };
8845 
8846 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR4_HIGH. */
8847 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR4_HIGH_s ALT_EMAC_GMAC_MAC_ADDR4_HIGH_t;
8848 #endif /* __ASSEMBLY__ */
8849 
8850 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH register. */
8851 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_RESET 0x0000ffff
8852 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH register from the beginning of the component. */
8853 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_OFST 0x60
8854 /* The address of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH register. */
8855 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR4_HIGH_OFST))
8856 
8857 /*
8858  * Register : gmacgrp_mac_address4_low
8859  *
8860  * <b> Register 25 (MAC Address4 Low Register) </b>
8861  *
8862  * The MAC Address4 Low register holds the lower 32 bits of the fifth 6-byte MAC
8863  * address of the station.
8864  *
8865  * Register Layout
8866  *
8867  * Bits | Access | Reset | Description
8868  * :-------|:-------|:-----------|:-----------------------------------
8869  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO
8870  *
8871  */
8872 /*
8873  * Field : addrlo
8874  *
8875  * MAC Address4 [31:0]
8876  *
8877  * This field contains the lower 32 bits of the fifth 6-byte MAC address. The
8878  * content of this field is undefined until loaded by the Application after the
8879  * initialization process.
8880  *
8881  * Field Access Macros:
8882  *
8883  */
8884 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field. */
8885 #define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_LSB 0
8886 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field. */
8887 #define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_MSB 31
8888 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field. */
8889 #define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_WIDTH 32
8890 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field value. */
8891 #define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_SET_MSK 0xffffffff
8892 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field value. */
8893 #define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_CLR_MSK 0x00000000
8894 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field. */
8895 #define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_RESET 0xffffffff
8896 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO field value from a register. */
8897 #define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
8898 /* Produces a ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field value suitable for setting the register. */
8899 #define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
8900 
8901 #ifndef __ASSEMBLY__
8902 /*
8903  * WARNING: The C register and register group struct declarations are provided for
8904  * convenience and illustrative purposes. They should, however, be used with
8905  * caution as the C language standard provides no guarantees about the alignment or
8906  * atomicity of device memory accesses. The recommended practice for writing
8907  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8908  * alt_write_word() functions.
8909  *
8910  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR4_LOW.
8911  */
8912 struct ALT_EMAC_GMAC_MAC_ADDR4_LOW_s
8913 {
8914  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO */
8915 };
8916 
8917 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR4_LOW. */
8918 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR4_LOW_s ALT_EMAC_GMAC_MAC_ADDR4_LOW_t;
8919 #endif /* __ASSEMBLY__ */
8920 
8921 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_LOW register. */
8922 #define ALT_EMAC_GMAC_MAC_ADDR4_LOW_RESET 0xffffffff
8923 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR4_LOW register from the beginning of the component. */
8924 #define ALT_EMAC_GMAC_MAC_ADDR4_LOW_OFST 0x64
8925 /* The address of the ALT_EMAC_GMAC_MAC_ADDR4_LOW register. */
8926 #define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR4_LOW_OFST))
8927 
8928 /*
8929  * Register : gmacgrp_mac_address5_high
8930  *
8931  * <b> Register 26 (MAC Address5 High Register) </b>
8932  *
8933  * The MAC Address5 High register holds the upper 16 bits of the sixth 6-byte MAC
8934  * address of the station.
8935  *
8936  * If the MAC address registers are configured to be double-synchronized to the
8937  * (G)MII clock domains, then
8938  *
8939  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
8940  * or Bits[7:0] (in big-endian mode) of the MAC Address5 Low Register are written.
8941  * For proper synchronization updates, consecutive writes to this MAC Address5 Low
8942  * Register must be performed after at least four clock cycles in the destination
8943  * clock domain.
8944  *
8945  * Register Layout
8946  *
8947  * Bits | Access | Reset | Description
8948  * :--------|:-------|:-------|:----------------------------------------
8949  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI
8950  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR5_HIGH_RSVD_23_16
8951  * [24] | RW | 0x0 | Mask Byte Control
8952  * [25] | RW | 0x0 | Mask Byte Control
8953  * [26] | RW | 0x0 | Mask Byte Control
8954  * [27] | RW | 0x0 | Mask Byte Control
8955  * [28] | RW | 0x0 | Mask Byte Control
8956  * [29] | RW | 0x0 | Mask Byte Control
8957  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA
8958  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE
8959  *
8960  */
8961 /*
8962  * Field : addrhi
8963  *
8964  * MAC Address5 [47:32]
8965  *
8966  * This field contains the upper 16 bits (47:32) of the sixth 6-byte MAC address.
8967  *
8968  * Field Access Macros:
8969  *
8970  */
8971 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field. */
8972 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_LSB 0
8973 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field. */
8974 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_MSB 15
8975 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field. */
8976 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_WIDTH 16
8977 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field value. */
8978 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_SET_MSK 0x0000ffff
8979 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field value. */
8980 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_CLR_MSK 0xffff0000
8981 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field. */
8982 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_RESET 0xffff
8983 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI field value from a register. */
8984 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
8985 /* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field value suitable for setting the register. */
8986 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
8987 
8988 /*
8989  * Field : reserved_23_16
8990  *
8991  * Reserved
8992  *
8993  * Field Access Macros:
8994  *
8995  */
8996 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_RSVD_23_16 register field. */
8997 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_RSVD_23_16_LSB 16
8998 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_RSVD_23_16 register field. */
8999 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_RSVD_23_16_MSB 23
9000 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_RSVD_23_16 register field. */
9001 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_RSVD_23_16_WIDTH 8
9002 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_RSVD_23_16 register field value. */
9003 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
9004 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_RSVD_23_16 register field value. */
9005 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
9006 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_RSVD_23_16 register field. */
9007 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_RSVD_23_16_RESET 0x0
9008 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_RSVD_23_16 field value from a register. */
9009 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
9010 /* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_RSVD_23_16 register field value suitable for setting the register. */
9011 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
9012 
9013 /*
9014  * Field : Mask Byte Control - mbc_0
9015  *
9016  * This array of bits are mask control bits for comparison of each of the MAC
9017  * Address bytes. When masked, the MAC does not compare the corresponding byte of
9018  * received DA or SA with the contents of MAC Address5 high and low registers. Each
9019  * bit controls the masking of the bytes. You can filter a group of addresses
9020  * (known as group address filtering) by masking one or more bytes of the address.
9021  *
9022  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
9023  *
9024  * Field Enumeration Values:
9025  *
9026  * Enum | Value | Description
9027  * :---------------------------------------------|:------|:------------
9028  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_E_UNMSKED | 0x0 |
9029  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_E_MSKED | 0x1 |
9030  *
9031  * Field Access Macros:
9032  *
9033  */
9034 /*
9035  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0
9036  *
9037  */
9038 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_E_UNMSKED 0x0
9039 /*
9040  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0
9041  *
9042  */
9043 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_E_MSKED 0x1
9044 
9045 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field. */
9046 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_LSB 24
9047 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field. */
9048 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_MSB 24
9049 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field. */
9050 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_WIDTH 1
9051 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field value. */
9052 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_SET_MSK 0x01000000
9053 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field value. */
9054 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_CLR_MSK 0xfeffffff
9055 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field. */
9056 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_RESET 0x0
9057 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 field value from a register. */
9058 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
9059 /* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field value suitable for setting the register. */
9060 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
9061 
9062 /*
9063  * Field : Mask Byte Control - mbc_1
9064  *
9065  * This array of bits are mask control bits for comparison of each of the MAC
9066  * Address bytes. When masked, the MAC does not compare the corresponding byte of
9067  * received DA or SA with the contents of MAC Address5 high and low registers. Each
9068  * bit controls the masking of the bytes. You can filter a group of addresses
9069  * (known as group address filtering) by masking one or more bytes of the address.
9070  *
9071  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
9072  *
9073  * Field Enumeration Values:
9074  *
9075  * Enum | Value | Description
9076  * :---------------------------------------------|:------|:------------
9077  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_E_UNMSKED | 0x0 |
9078  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_E_MSKED | 0x1 |
9079  *
9080  * Field Access Macros:
9081  *
9082  */
9083 /*
9084  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1
9085  *
9086  */
9087 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_E_UNMSKED 0x0
9088 /*
9089  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1
9090  *
9091  */
9092 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_E_MSKED 0x1
9093 
9094 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field. */
9095 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_LSB 25
9096 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field. */
9097 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_MSB 25
9098 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field. */
9099 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_WIDTH 1
9100 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field value. */
9101 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_SET_MSK 0x02000000
9102 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field value. */
9103 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_CLR_MSK 0xfdffffff
9104 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field. */
9105 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_RESET 0x0
9106 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 field value from a register. */
9107 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
9108 /* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field value suitable for setting the register. */
9109 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
9110 
9111 /*
9112  * Field : Mask Byte Control - mbc_2
9113  *
9114  * This array of bits are mask control bits for comparison of each of the MAC
9115  * Address bytes. When masked, the MAC does not compare the corresponding byte of
9116  * received DA or SA with the contents of MAC Address5 high and low registers. Each
9117  * bit controls the masking of the bytes. You can filter a group of addresses
9118  * (known as group address filtering) by masking one or more bytes of the address.
9119  *
9120  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
9121  *
9122  * Field Enumeration Values:
9123  *
9124  * Enum | Value | Description
9125  * :---------------------------------------------|:------|:------------
9126  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_E_UNMSKED | 0x0 |
9127  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_E_MSKED | 0x1 |
9128  *
9129  * Field Access Macros:
9130  *
9131  */
9132 /*
9133  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2
9134  *
9135  */
9136 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_E_UNMSKED 0x0
9137 /*
9138  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2
9139  *
9140  */
9141 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_E_MSKED 0x1
9142 
9143 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field. */
9144 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_LSB 26
9145 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field. */
9146 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_MSB 26
9147 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field. */
9148 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_WIDTH 1
9149 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field value. */
9150 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_SET_MSK 0x04000000
9151 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field value. */
9152 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_CLR_MSK 0xfbffffff
9153 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field. */
9154 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_RESET 0x0
9155 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 field value from a register. */
9156 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
9157 /* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field value suitable for setting the register. */
9158 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
9159 
9160 /*
9161  * Field : Mask Byte Control - mbc_3
9162  *
9163  * This array of bits are mask control bits for comparison of each of the MAC
9164  * Address bytes. When masked, the MAC does not compare the corresponding byte of
9165  * received DA or SA with the contents of MAC Address5 high and low registers. Each
9166  * bit controls the masking of the bytes. You can filter a group of addresses
9167  * (known as group address filtering) by masking one or more bytes of the address.
9168  *
9169  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
9170  *
9171  * Field Enumeration Values:
9172  *
9173  * Enum | Value | Description
9174  * :---------------------------------------------|:------|:------------
9175  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_E_UNMSKED | 0x0 |
9176  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_E_MSKED | 0x1 |
9177  *
9178  * Field Access Macros:
9179  *
9180  */
9181 /*
9182  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3
9183  *
9184  */
9185 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_E_UNMSKED 0x0
9186 /*
9187  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3
9188  *
9189  */
9190 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_E_MSKED 0x1
9191 
9192 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field. */
9193 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_LSB 27
9194 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field. */
9195 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_MSB 27
9196 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field. */
9197 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_WIDTH 1
9198 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field value. */
9199 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_SET_MSK 0x08000000
9200 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field value. */
9201 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_CLR_MSK 0xf7ffffff
9202 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field. */
9203 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_RESET 0x0
9204 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 field value from a register. */
9205 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
9206 /* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field value suitable for setting the register. */
9207 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
9208 
9209 /*
9210  * Field : Mask Byte Control - mbc_4
9211  *
9212  * This array of bits are mask control bits for comparison of each of the MAC
9213  * Address bytes. When masked, the MAC does not compare the corresponding byte of
9214  * received DA or SA with the contents of MAC Address5 high and low registers. Each
9215  * bit controls the masking of the bytes. You can filter a group of addresses
9216  * (known as group address filtering) by masking one or more bytes of the address.
9217  *
9218  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
9219  *
9220  * Field Enumeration Values:
9221  *
9222  * Enum | Value | Description
9223  * :---------------------------------------------|:------|:------------
9224  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_E_UNMSKED | 0x0 |
9225  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_E_MSKED | 0x1 |
9226  *
9227  * Field Access Macros:
9228  *
9229  */
9230 /*
9231  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4
9232  *
9233  */
9234 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_E_UNMSKED 0x0
9235 /*
9236  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4
9237  *
9238  */
9239 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_E_MSKED 0x1
9240 
9241 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field. */
9242 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_LSB 28
9243 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field. */
9244 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_MSB 28
9245 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field. */
9246 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_WIDTH 1
9247 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field value. */
9248 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_SET_MSK 0x10000000
9249 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field value. */
9250 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_CLR_MSK 0xefffffff
9251 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field. */
9252 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_RESET 0x0
9253 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 field value from a register. */
9254 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
9255 /* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field value suitable for setting the register. */
9256 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
9257 
9258 /*
9259  * Field : Mask Byte Control - mbc_5
9260  *
9261  * This array of bits are mask control bits for comparison of each of the MAC
9262  * Address bytes. When masked, the MAC does not compare the corresponding byte of
9263  * received DA or SA with the contents of MAC Address5 high and low registers. Each
9264  * bit controls the masking of the bytes. You can filter a group of addresses
9265  * (known as group address filtering) by masking one or more bytes of the address.
9266  *
9267  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
9268  *
9269  * Field Enumeration Values:
9270  *
9271  * Enum | Value | Description
9272  * :---------------------------------------------|:------|:------------
9273  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_E_UNMSKED | 0x0 |
9274  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_E_MSKED | 0x1 |
9275  *
9276  * Field Access Macros:
9277  *
9278  */
9279 /*
9280  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5
9281  *
9282  */
9283 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_E_UNMSKED 0x0
9284 /*
9285  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5
9286  *
9287  */
9288 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_E_MSKED 0x1
9289 
9290 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field. */
9291 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_LSB 29
9292 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field. */
9293 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_MSB 29
9294 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field. */
9295 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_WIDTH 1
9296 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field value. */
9297 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_SET_MSK 0x20000000
9298 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field value. */
9299 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_CLR_MSK 0xdfffffff
9300 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field. */
9301 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_RESET 0x0
9302 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 field value from a register. */
9303 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
9304 /* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field value suitable for setting the register. */
9305 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
9306 
9307 /*
9308  * Field : sa
9309  *
9310  * Source Address
9311  *
9312  * When this bit is set, the MAC Address5[47:0] is used to compare with the SA
9313  * fields of the received frame.
9314  *
9315  * When this bit is reset, the MAC Address5[47:0] is used to compare with the DA
9316  * fields of the received frame.
9317  *
9318  * Field Enumeration Values:
9319  *
9320  * Enum | Value | Description
9321  * :---------------------------------------|:------|:------------
9322  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_E_DISD | 0x0 |
9323  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_E_END | 0x1 |
9324  *
9325  * Field Access Macros:
9326  *
9327  */
9328 /*
9329  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA
9330  *
9331  */
9332 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_E_DISD 0x0
9333 /*
9334  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA
9335  *
9336  */
9337 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_E_END 0x1
9338 
9339 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field. */
9340 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_LSB 30
9341 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field. */
9342 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_MSB 30
9343 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field. */
9344 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_WIDTH 1
9345 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field value. */
9346 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_SET_MSK 0x40000000
9347 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field value. */
9348 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_CLR_MSK 0xbfffffff
9349 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field. */
9350 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_RESET 0x0
9351 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA field value from a register. */
9352 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
9353 /* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field value suitable for setting the register. */
9354 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
9355 
9356 /*
9357  * Field : ae
9358  *
9359  * Address Enable
9360  *
9361  * When this bit is set, the address filter module uses the sixth MAC address for
9362  * perfect filtering. When this bit is reset, the address filter module ignores the
9363  * address for filtering.
9364  *
9365  * Field Enumeration Values:
9366  *
9367  * Enum | Value | Description
9368  * :---------------------------------------|:------|:------------
9369  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_E_DISD | 0x0 |
9370  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_E_END | 0x1 |
9371  *
9372  * Field Access Macros:
9373  *
9374  */
9375 /*
9376  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE
9377  *
9378  */
9379 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_E_DISD 0x0
9380 /*
9381  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE
9382  *
9383  */
9384 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_E_END 0x1
9385 
9386 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field. */
9387 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_LSB 31
9388 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field. */
9389 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_MSB 31
9390 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field. */
9391 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_WIDTH 1
9392 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field value. */
9393 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_SET_MSK 0x80000000
9394 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field value. */
9395 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_CLR_MSK 0x7fffffff
9396 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field. */
9397 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_RESET 0x0
9398 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE field value from a register. */
9399 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
9400 /* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field value suitable for setting the register. */
9401 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
9402 
9403 #ifndef __ASSEMBLY__
9404 /*
9405  * WARNING: The C register and register group struct declarations are provided for
9406  * convenience and illustrative purposes. They should, however, be used with
9407  * caution as the C language standard provides no guarantees about the alignment or
9408  * atomicity of device memory accesses. The recommended practice for writing
9409  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9410  * alt_write_word() functions.
9411  *
9412  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR5_HIGH.
9413  */
9414 struct ALT_EMAC_GMAC_MAC_ADDR5_HIGH_s
9415 {
9416  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI */
9417  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR5_HIGH_RSVD_23_16 */
9418  uint32_t mbc_0 : 1; /* Mask Byte Control */
9419  uint32_t mbc_1 : 1; /* Mask Byte Control */
9420  uint32_t mbc_2 : 1; /* Mask Byte Control */
9421  uint32_t mbc_3 : 1; /* Mask Byte Control */
9422  uint32_t mbc_4 : 1; /* Mask Byte Control */
9423  uint32_t mbc_5 : 1; /* Mask Byte Control */
9424  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA */
9425  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE */
9426 };
9427 
9428 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR5_HIGH. */
9429 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR5_HIGH_s ALT_EMAC_GMAC_MAC_ADDR5_HIGH_t;
9430 #endif /* __ASSEMBLY__ */
9431 
9432 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH register. */
9433 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_RESET 0x0000ffff
9434 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH register from the beginning of the component. */
9435 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_OFST 0x68
9436 /* The address of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH register. */
9437 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR5_HIGH_OFST))
9438 
9439 /*
9440  * Register : gmacgrp_mac_address5_low
9441  *
9442  * <b> Register 27 (MAC Address5 Low Register) </b>
9443  *
9444  * The MAC Address5 Low register holds the lower 32 bits of the sixth 6-byte MAC
9445  * address of the station.
9446  *
9447  * Register Layout
9448  *
9449  * Bits | Access | Reset | Description
9450  * :-------|:-------|:-----------|:-----------------------------------
9451  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO
9452  *
9453  */
9454 /*
9455  * Field : addrlo
9456  *
9457  * MAC Address5 [31:0]
9458  *
9459  * This field contains the lower 32 bits of the sixth 6-byte MAC address. The
9460  * content of this field is undefined until loaded by the Application after the
9461  * initialization process.
9462  *
9463  * Field Access Macros:
9464  *
9465  */
9466 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field. */
9467 #define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_LSB 0
9468 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field. */
9469 #define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_MSB 31
9470 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field. */
9471 #define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_WIDTH 32
9472 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field value. */
9473 #define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_SET_MSK 0xffffffff
9474 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field value. */
9475 #define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_CLR_MSK 0x00000000
9476 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field. */
9477 #define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_RESET 0xffffffff
9478 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO field value from a register. */
9479 #define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
9480 /* Produces a ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field value suitable for setting the register. */
9481 #define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
9482 
9483 #ifndef __ASSEMBLY__
9484 /*
9485  * WARNING: The C register and register group struct declarations are provided for
9486  * convenience and illustrative purposes. They should, however, be used with
9487  * caution as the C language standard provides no guarantees about the alignment or
9488  * atomicity of device memory accesses. The recommended practice for writing
9489  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9490  * alt_write_word() functions.
9491  *
9492  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR5_LOW.
9493  */
9494 struct ALT_EMAC_GMAC_MAC_ADDR5_LOW_s
9495 {
9496  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO */
9497 };
9498 
9499 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR5_LOW. */
9500 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR5_LOW_s ALT_EMAC_GMAC_MAC_ADDR5_LOW_t;
9501 #endif /* __ASSEMBLY__ */
9502 
9503 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_LOW register. */
9504 #define ALT_EMAC_GMAC_MAC_ADDR5_LOW_RESET 0xffffffff
9505 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR5_LOW register from the beginning of the component. */
9506 #define ALT_EMAC_GMAC_MAC_ADDR5_LOW_OFST 0x6c
9507 /* The address of the ALT_EMAC_GMAC_MAC_ADDR5_LOW register. */
9508 #define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR5_LOW_OFST))
9509 
9510 /*
9511  * Register : gmacgrp_mac_address6_high
9512  *
9513  * <b> Register 28 (MAC Address6 High Register) </b>
9514  *
9515  * The MAC Address6 High register holds the upper 16 bits of the seventh 6-byte MAC
9516  * address of the station.
9517  *
9518  * If the MAC address registers are configured to be double-synchronized to the
9519  * (G)MII clock domains, then the synchronization is triggered only when
9520  * Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC
9521  * Address6 Low Register are written. For proper synchronization updates, the
9522  * consecutive writes to this MAC Address6 Low Register should be performed after
9523  * at least four clock cycles in the destination clock domain.
9524  *
9525  * Register Layout
9526  *
9527  * Bits | Access | Reset | Description
9528  * :--------|:-------|:-------|:----------------------------------------
9529  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI
9530  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR6_HIGH_RSVD_23_16
9531  * [24] | RW | 0x0 | Mask Byte Control
9532  * [25] | RW | 0x0 | Mask Byte Control
9533  * [26] | RW | 0x0 | Mask Byte Control
9534  * [27] | RW | 0x0 | Mask Byte Control
9535  * [28] | RW | 0x0 | Mask Byte Control
9536  * [29] | RW | 0x0 | Mask Byte Control
9537  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA
9538  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE
9539  *
9540  */
9541 /*
9542  * Field : addrhi
9543  *
9544  * MAC Address6 [47:32]
9545  *
9546  * This field contains the upper 16 bits (47:32) of the seventh 6-byte MAC address.
9547  *
9548  * Field Access Macros:
9549  *
9550  */
9551 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field. */
9552 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_LSB 0
9553 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field. */
9554 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_MSB 15
9555 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field. */
9556 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_WIDTH 16
9557 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field value. */
9558 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_SET_MSK 0x0000ffff
9559 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field value. */
9560 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_CLR_MSK 0xffff0000
9561 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field. */
9562 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_RESET 0xffff
9563 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI field value from a register. */
9564 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
9565 /* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field value suitable for setting the register. */
9566 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
9567 
9568 /*
9569  * Field : reserved_23_16
9570  *
9571  * Reserved
9572  *
9573  * Field Access Macros:
9574  *
9575  */
9576 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_RSVD_23_16 register field. */
9577 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_RSVD_23_16_LSB 16
9578 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_RSVD_23_16 register field. */
9579 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_RSVD_23_16_MSB 23
9580 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_RSVD_23_16 register field. */
9581 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_RSVD_23_16_WIDTH 8
9582 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_RSVD_23_16 register field value. */
9583 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
9584 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_RSVD_23_16 register field value. */
9585 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
9586 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_RSVD_23_16 register field. */
9587 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_RSVD_23_16_RESET 0x0
9588 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_RSVD_23_16 field value from a register. */
9589 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
9590 /* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_RSVD_23_16 register field value suitable for setting the register. */
9591 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
9592 
9593 /*
9594  * Field : Mask Byte Control - mbc_0
9595  *
9596  * This array of bits are mask control bits for comparison of each of the MAC
9597  * Address bytes. When masked, the MAC does not compare the corresponding byte of
9598  * received DA or SA with the contents of MAC Address6 high and low registers. Each
9599  * bit controls the masking of the bytes. You can filter a group of addresses
9600  * (known as group address filtering) by masking one or more bytes of the address.
9601  *
9602  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
9603  *
9604  * Field Enumeration Values:
9605  *
9606  * Enum | Value | Description
9607  * :---------------------------------------------|:------|:------------
9608  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_E_UNMSKED | 0x0 |
9609  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_E_MSKED | 0x1 |
9610  *
9611  * Field Access Macros:
9612  *
9613  */
9614 /*
9615  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0
9616  *
9617  */
9618 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_E_UNMSKED 0x0
9619 /*
9620  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0
9621  *
9622  */
9623 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_E_MSKED 0x1
9624 
9625 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field. */
9626 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_LSB 24
9627 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field. */
9628 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_MSB 24
9629 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field. */
9630 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_WIDTH 1
9631 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field value. */
9632 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_SET_MSK 0x01000000
9633 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field value. */
9634 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_CLR_MSK 0xfeffffff
9635 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field. */
9636 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_RESET 0x0
9637 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 field value from a register. */
9638 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
9639 /* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field value suitable for setting the register. */
9640 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
9641 
9642 /*
9643  * Field : Mask Byte Control - mbc_1
9644  *
9645  * This array of bits are mask control bits for comparison of each of the MAC
9646  * Address bytes. When masked, the MAC does not compare the corresponding byte of
9647  * received DA or SA with the contents of MAC Address6 high and low registers. Each
9648  * bit controls the masking of the bytes. You can filter a group of addresses
9649  * (known as group address filtering) by masking one or more bytes of the address.
9650  *
9651  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
9652  *
9653  * Field Enumeration Values:
9654  *
9655  * Enum | Value | Description
9656  * :---------------------------------------------|:------|:------------
9657  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_E_UNMSKED | 0x0 |
9658  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_E_MSKED | 0x1 |
9659  *
9660  * Field Access Macros:
9661  *
9662  */
9663 /*
9664  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1
9665  *
9666  */
9667 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_E_UNMSKED 0x0
9668 /*
9669  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1
9670  *
9671  */
9672 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_E_MSKED 0x1
9673 
9674 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field. */
9675 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_LSB 25
9676 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field. */
9677 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_MSB 25
9678 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field. */
9679 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_WIDTH 1
9680 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field value. */
9681 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_SET_MSK 0x02000000
9682 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field value. */
9683 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_CLR_MSK 0xfdffffff
9684 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field. */
9685 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_RESET 0x0
9686 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 field value from a register. */
9687 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
9688 /* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field value suitable for setting the register. */
9689 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
9690 
9691 /*
9692  * Field : Mask Byte Control - mbc_2
9693  *
9694  * This array of bits are mask control bits for comparison of each of the MAC
9695  * Address bytes. When masked, the MAC does not compare the corresponding byte of
9696  * received DA or SA with the contents of MAC Address6 high and low registers. Each
9697  * bit controls the masking of the bytes. You can filter a group of addresses
9698  * (known as group address filtering) by masking one or more bytes of the address.
9699  *
9700  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
9701  *
9702  * Field Enumeration Values:
9703  *
9704  * Enum | Value | Description
9705  * :---------------------------------------------|:------|:------------
9706  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_E_UNMSKED | 0x0 |
9707  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_E_MSKED | 0x1 |
9708  *
9709  * Field Access Macros:
9710  *
9711  */
9712 /*
9713  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2
9714  *
9715  */
9716 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_E_UNMSKED 0x0
9717 /*
9718  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2
9719  *
9720  */
9721 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_E_MSKED 0x1
9722 
9723 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field. */
9724 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_LSB 26
9725 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field. */
9726 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_MSB 26
9727 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field. */
9728 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_WIDTH 1
9729 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field value. */
9730 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_SET_MSK 0x04000000
9731 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field value. */
9732 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_CLR_MSK 0xfbffffff
9733 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field. */
9734 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_RESET 0x0
9735 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 field value from a register. */
9736 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
9737 /* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field value suitable for setting the register. */
9738 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
9739 
9740 /*
9741  * Field : Mask Byte Control - mbc_3
9742  *
9743  * This array of bits are mask control bits for comparison of each of the MAC
9744  * Address bytes. When masked, the MAC does not compare the corresponding byte of
9745  * received DA or SA with the contents of MAC Address6 high and low registers. Each
9746  * bit controls the masking of the bytes. You can filter a group of addresses
9747  * (known as group address filtering) by masking one or more bytes of the address.
9748  *
9749  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
9750  *
9751  * Field Enumeration Values:
9752  *
9753  * Enum | Value | Description
9754  * :---------------------------------------------|:------|:------------
9755  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_E_UNMSKED | 0x0 |
9756  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_E_MSKED | 0x1 |
9757  *
9758  * Field Access Macros:
9759  *
9760  */
9761 /*
9762  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3
9763  *
9764  */
9765 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_E_UNMSKED 0x0
9766 /*
9767  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3
9768  *
9769  */
9770 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_E_MSKED 0x1
9771 
9772 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field. */
9773 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_LSB 27
9774 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field. */
9775 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_MSB 27
9776 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field. */
9777 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_WIDTH 1
9778 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field value. */
9779 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_SET_MSK 0x08000000
9780 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field value. */
9781 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_CLR_MSK 0xf7ffffff
9782 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field. */
9783 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_RESET 0x0
9784 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 field value from a register. */
9785 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
9786 /* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field value suitable for setting the register. */
9787 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
9788 
9789 /*
9790  * Field : Mask Byte Control - mbc_4
9791  *
9792  * This array of bits are mask control bits for comparison of each of the MAC
9793  * Address bytes. When masked, the MAC does not compare the corresponding byte of
9794  * received DA or SA with the contents of MAC Address6 high and low registers. Each
9795  * bit controls the masking of the bytes. You can filter a group of addresses
9796  * (known as group address filtering) by masking one or more bytes of the address.
9797  *
9798  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
9799  *
9800  * Field Enumeration Values:
9801  *
9802  * Enum | Value | Description
9803  * :---------------------------------------------|:------|:------------
9804  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_E_UNMSKED | 0x0 |
9805  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_E_MSKED | 0x1 |
9806  *
9807  * Field Access Macros:
9808  *
9809  */
9810 /*
9811  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4
9812  *
9813  */
9814 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_E_UNMSKED 0x0
9815 /*
9816  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4
9817  *
9818  */
9819 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_E_MSKED 0x1
9820 
9821 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field. */
9822 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_LSB 28
9823 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field. */
9824 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_MSB 28
9825 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field. */
9826 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_WIDTH 1
9827 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field value. */
9828 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_SET_MSK 0x10000000
9829 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field value. */
9830 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_CLR_MSK 0xefffffff
9831 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field. */
9832 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_RESET 0x0
9833 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 field value from a register. */
9834 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
9835 /* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field value suitable for setting the register. */
9836 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
9837 
9838 /*
9839  * Field : Mask Byte Control - mbc_5
9840  *
9841  * This array of bits are mask control bits for comparison of each of the MAC
9842  * Address bytes. When masked, the MAC does not compare the corresponding byte of
9843  * received DA or SA with the contents of MAC Address6 high and low registers. Each
9844  * bit controls the masking of the bytes. You can filter a group of addresses
9845  * (known as group address filtering) by masking one or more bytes of the address.
9846  *
9847  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
9848  *
9849  * Field Enumeration Values:
9850  *
9851  * Enum | Value | Description
9852  * :---------------------------------------------|:------|:------------
9853  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_E_UNMSKED | 0x0 |
9854  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_E_MSKED | 0x1 |
9855  *
9856  * Field Access Macros:
9857  *
9858  */
9859 /*
9860  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5
9861  *
9862  */
9863 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_E_UNMSKED 0x0
9864 /*
9865  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5
9866  *
9867  */
9868 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_E_MSKED 0x1
9869 
9870 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field. */
9871 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_LSB 29
9872 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field. */
9873 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_MSB 29
9874 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field. */
9875 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_WIDTH 1
9876 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field value. */
9877 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_SET_MSK 0x20000000
9878 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field value. */
9879 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_CLR_MSK 0xdfffffff
9880 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field. */
9881 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_RESET 0x0
9882 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 field value from a register. */
9883 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
9884 /* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field value suitable for setting the register. */
9885 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
9886 
9887 /*
9888  * Field : sa
9889  *
9890  * Source Address
9891  *
9892  * When this bit is set, the MAC Address6[47:0] is used to compare with the SA
9893  * fields of the received frame. When this bit is reset, the MAC Address6[47:0] is
9894  * used to compare with the DA fields of the received frame.
9895  *
9896  * Field Enumeration Values:
9897  *
9898  * Enum | Value | Description
9899  * :---------------------------------------|:------|:------------
9900  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_E_DISD | 0x0 |
9901  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_E_END | 0x1 |
9902  *
9903  * Field Access Macros:
9904  *
9905  */
9906 /*
9907  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA
9908  *
9909  */
9910 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_E_DISD 0x0
9911 /*
9912  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA
9913  *
9914  */
9915 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_E_END 0x1
9916 
9917 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field. */
9918 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_LSB 30
9919 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field. */
9920 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_MSB 30
9921 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field. */
9922 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_WIDTH 1
9923 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field value. */
9924 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_SET_MSK 0x40000000
9925 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field value. */
9926 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_CLR_MSK 0xbfffffff
9927 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field. */
9928 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_RESET 0x0
9929 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA field value from a register. */
9930 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
9931 /* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field value suitable for setting the register. */
9932 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
9933 
9934 /*
9935  * Field : ae
9936  *
9937  * Address Enable
9938  *
9939  * When this bit is set, the address filter module uses the seventh MAC address for
9940  * perfect filtering.
9941  *
9942  * When this bit is reset, the address filter module ignores the address for
9943  * filtering.
9944  *
9945  * Field Enumeration Values:
9946  *
9947  * Enum | Value | Description
9948  * :---------------------------------------|:------|:------------
9949  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_E_DISD | 0x0 |
9950  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_E_END | 0x1 |
9951  *
9952  * Field Access Macros:
9953  *
9954  */
9955 /*
9956  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE
9957  *
9958  */
9959 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_E_DISD 0x0
9960 /*
9961  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE
9962  *
9963  */
9964 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_E_END 0x1
9965 
9966 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field. */
9967 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_LSB 31
9968 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field. */
9969 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_MSB 31
9970 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field. */
9971 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_WIDTH 1
9972 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field value. */
9973 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_SET_MSK 0x80000000
9974 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field value. */
9975 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_CLR_MSK 0x7fffffff
9976 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field. */
9977 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_RESET 0x0
9978 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE field value from a register. */
9979 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
9980 /* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field value suitable for setting the register. */
9981 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
9982 
9983 #ifndef __ASSEMBLY__
9984 /*
9985  * WARNING: The C register and register group struct declarations are provided for
9986  * convenience and illustrative purposes. They should, however, be used with
9987  * caution as the C language standard provides no guarantees about the alignment or
9988  * atomicity of device memory accesses. The recommended practice for writing
9989  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9990  * alt_write_word() functions.
9991  *
9992  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR6_HIGH.
9993  */
9994 struct ALT_EMAC_GMAC_MAC_ADDR6_HIGH_s
9995 {
9996  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI */
9997  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR6_HIGH_RSVD_23_16 */
9998  uint32_t mbc_0 : 1; /* Mask Byte Control */
9999  uint32_t mbc_1 : 1; /* Mask Byte Control */
10000  uint32_t mbc_2 : 1; /* Mask Byte Control */
10001  uint32_t mbc_3 : 1; /* Mask Byte Control */
10002  uint32_t mbc_4 : 1; /* Mask Byte Control */
10003  uint32_t mbc_5 : 1; /* Mask Byte Control */
10004  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA */
10005  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE */
10006 };
10007 
10008 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR6_HIGH. */
10009 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR6_HIGH_s ALT_EMAC_GMAC_MAC_ADDR6_HIGH_t;
10010 #endif /* __ASSEMBLY__ */
10011 
10012 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH register. */
10013 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_RESET 0x0000ffff
10014 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH register from the beginning of the component. */
10015 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_OFST 0x70
10016 /* The address of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH register. */
10017 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR6_HIGH_OFST))
10018 
10019 /*
10020  * Register : gmacgrp_mac_address6_low
10021  *
10022  * <b> Register 29 (MAC Address6 Low Register) </b>
10023  *
10024  * The MAC Address6 Low register holds the lower 32 bits of the seventh 6-byte MAC
10025  * address of the station.
10026  *
10027  * Register Layout
10028  *
10029  * Bits | Access | Reset | Description
10030  * :-------|:-------|:-----------|:-----------------------------------
10031  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO
10032  *
10033  */
10034 /*
10035  * Field : addrlo
10036  *
10037  * MAC Address6 [31:0]
10038  *
10039  * This field contains the lower 32 bits of the seventh 6-byte MAC address. The
10040  * content of this field is undefined until loaded by the Application after the
10041  * initialization process.
10042  *
10043  * Field Access Macros:
10044  *
10045  */
10046 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field. */
10047 #define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_LSB 0
10048 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field. */
10049 #define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_MSB 31
10050 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field. */
10051 #define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_WIDTH 32
10052 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field value. */
10053 #define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_SET_MSK 0xffffffff
10054 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field value. */
10055 #define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_CLR_MSK 0x00000000
10056 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field. */
10057 #define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_RESET 0xffffffff
10058 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO field value from a register. */
10059 #define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
10060 /* Produces a ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field value suitable for setting the register. */
10061 #define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
10062 
10063 #ifndef __ASSEMBLY__
10064 /*
10065  * WARNING: The C register and register group struct declarations are provided for
10066  * convenience and illustrative purposes. They should, however, be used with
10067  * caution as the C language standard provides no guarantees about the alignment or
10068  * atomicity of device memory accesses. The recommended practice for writing
10069  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10070  * alt_write_word() functions.
10071  *
10072  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR6_LOW.
10073  */
10074 struct ALT_EMAC_GMAC_MAC_ADDR6_LOW_s
10075 {
10076  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO */
10077 };
10078 
10079 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR6_LOW. */
10080 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR6_LOW_s ALT_EMAC_GMAC_MAC_ADDR6_LOW_t;
10081 #endif /* __ASSEMBLY__ */
10082 
10083 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_LOW register. */
10084 #define ALT_EMAC_GMAC_MAC_ADDR6_LOW_RESET 0xffffffff
10085 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR6_LOW register from the beginning of the component. */
10086 #define ALT_EMAC_GMAC_MAC_ADDR6_LOW_OFST 0x74
10087 /* The address of the ALT_EMAC_GMAC_MAC_ADDR6_LOW register. */
10088 #define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR6_LOW_OFST))
10089 
10090 /*
10091  * Register : gmacgrp_mac_address7_high
10092  *
10093  * <b> Register 30 (MAC Address7 High Register) </b>
10094  *
10095  * The MAC Address7 High register holds the upper 16 bits of the eighth 6-byte MAC
10096  * address of the station.
10097  *
10098  * If the MAC address registers are configured to be double-synchronized to the
10099  * (G)MII clock domains, then the synchronization is triggered only when
10100  * Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC
10101  * Address7 Low Register are written. For proper synchronization updates, the
10102  * consecutive writes to this MAC Address7 Low Register should be performed after
10103  * at least four clock cycles in the destination clock domain.
10104  *
10105  * Register Layout
10106  *
10107  * Bits | Access | Reset | Description
10108  * :--------|:-------|:-------|:----------------------------------------
10109  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI
10110  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR7_HIGH_RSVD_23_16
10111  * [24] | RW | 0x0 | Mask Byte Control
10112  * [25] | RW | 0x0 | Mask Byte Control
10113  * [26] | RW | 0x0 | Mask Byte Control
10114  * [27] | RW | 0x0 | Mask Byte Control
10115  * [28] | RW | 0x0 | Mask Byte Control
10116  * [29] | RW | 0x0 | Mask Byte Control
10117  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA
10118  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE
10119  *
10120  */
10121 /*
10122  * Field : addrhi
10123  *
10124  * MAC Address7 [47:32]
10125  *
10126  * This field contains the upper 16 bits (47:32) of the eighth 6-byte MAC address.
10127  *
10128  * Field Access Macros:
10129  *
10130  */
10131 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field. */
10132 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_LSB 0
10133 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field. */
10134 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_MSB 15
10135 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field. */
10136 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_WIDTH 16
10137 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field value. */
10138 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_SET_MSK 0x0000ffff
10139 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field value. */
10140 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_CLR_MSK 0xffff0000
10141 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field. */
10142 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_RESET 0xffff
10143 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI field value from a register. */
10144 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
10145 /* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field value suitable for setting the register. */
10146 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
10147 
10148 /*
10149  * Field : reserved_23_16
10150  *
10151  * Reserved
10152  *
10153  * Field Access Macros:
10154  *
10155  */
10156 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_RSVD_23_16 register field. */
10157 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_RSVD_23_16_LSB 16
10158 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_RSVD_23_16 register field. */
10159 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_RSVD_23_16_MSB 23
10160 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_RSVD_23_16 register field. */
10161 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_RSVD_23_16_WIDTH 8
10162 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_RSVD_23_16 register field value. */
10163 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
10164 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_RSVD_23_16 register field value. */
10165 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
10166 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_RSVD_23_16 register field. */
10167 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_RSVD_23_16_RESET 0x0
10168 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_RSVD_23_16 field value from a register. */
10169 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
10170 /* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_RSVD_23_16 register field value suitable for setting the register. */
10171 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
10172 
10173 /*
10174  * Field : Mask Byte Control - mbc_0
10175  *
10176  * This array of bits are mask control bits for comparison of each of the MAC
10177  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10178  * received DA or SA with the contents of MAC Address7 high and low registers. Each
10179  * bit controls the masking of the bytes. You can filter a group of addresses
10180  * (known as group address filtering) by masking one or more bytes of the address.
10181  *
10182  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10183  *
10184  * Field Enumeration Values:
10185  *
10186  * Enum | Value | Description
10187  * :---------------------------------------------|:------|:------------
10188  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_E_UNMSKED | 0x0 |
10189  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_E_MSKED | 0x1 |
10190  *
10191  * Field Access Macros:
10192  *
10193  */
10194 /*
10195  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0
10196  *
10197  */
10198 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_E_UNMSKED 0x0
10199 /*
10200  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0
10201  *
10202  */
10203 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_E_MSKED 0x1
10204 
10205 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field. */
10206 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_LSB 24
10207 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field. */
10208 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_MSB 24
10209 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field. */
10210 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_WIDTH 1
10211 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field value. */
10212 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_SET_MSK 0x01000000
10213 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field value. */
10214 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_CLR_MSK 0xfeffffff
10215 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field. */
10216 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_RESET 0x0
10217 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 field value from a register. */
10218 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
10219 /* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field value suitable for setting the register. */
10220 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
10221 
10222 /*
10223  * Field : Mask Byte Control - mbc_1
10224  *
10225  * This array of bits are mask control bits for comparison of each of the MAC
10226  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10227  * received DA or SA with the contents of MAC Address7 high and low registers. Each
10228  * bit controls the masking of the bytes. You can filter a group of addresses
10229  * (known as group address filtering) by masking one or more bytes of the address.
10230  *
10231  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10232  *
10233  * Field Enumeration Values:
10234  *
10235  * Enum | Value | Description
10236  * :---------------------------------------------|:------|:------------
10237  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_E_UNMSKED | 0x0 |
10238  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_E_MSKED | 0x1 |
10239  *
10240  * Field Access Macros:
10241  *
10242  */
10243 /*
10244  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1
10245  *
10246  */
10247 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_E_UNMSKED 0x0
10248 /*
10249  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1
10250  *
10251  */
10252 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_E_MSKED 0x1
10253 
10254 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field. */
10255 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_LSB 25
10256 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field. */
10257 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_MSB 25
10258 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field. */
10259 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_WIDTH 1
10260 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field value. */
10261 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_SET_MSK 0x02000000
10262 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field value. */
10263 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_CLR_MSK 0xfdffffff
10264 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field. */
10265 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_RESET 0x0
10266 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 field value from a register. */
10267 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
10268 /* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field value suitable for setting the register. */
10269 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
10270 
10271 /*
10272  * Field : Mask Byte Control - mbc_2
10273  *
10274  * This array of bits are mask control bits for comparison of each of the MAC
10275  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10276  * received DA or SA with the contents of MAC Address7 high and low registers. Each
10277  * bit controls the masking of the bytes. You can filter a group of addresses
10278  * (known as group address filtering) by masking one or more bytes of the address.
10279  *
10280  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10281  *
10282  * Field Enumeration Values:
10283  *
10284  * Enum | Value | Description
10285  * :---------------------------------------------|:------|:------------
10286  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_E_UNMSKED | 0x0 |
10287  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_E_MSKED | 0x1 |
10288  *
10289  * Field Access Macros:
10290  *
10291  */
10292 /*
10293  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2
10294  *
10295  */
10296 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_E_UNMSKED 0x0
10297 /*
10298  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2
10299  *
10300  */
10301 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_E_MSKED 0x1
10302 
10303 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field. */
10304 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_LSB 26
10305 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field. */
10306 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_MSB 26
10307 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field. */
10308 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_WIDTH 1
10309 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field value. */
10310 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_SET_MSK 0x04000000
10311 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field value. */
10312 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_CLR_MSK 0xfbffffff
10313 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field. */
10314 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_RESET 0x0
10315 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 field value from a register. */
10316 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
10317 /* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field value suitable for setting the register. */
10318 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
10319 
10320 /*
10321  * Field : Mask Byte Control - mbc_3
10322  *
10323  * This array of bits are mask control bits for comparison of each of the MAC
10324  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10325  * received DA or SA with the contents of MAC Address7 high and low registers. Each
10326  * bit controls the masking of the bytes. You can filter a group of addresses
10327  * (known as group address filtering) by masking one or more bytes of the address.
10328  *
10329  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10330  *
10331  * Field Enumeration Values:
10332  *
10333  * Enum | Value | Description
10334  * :---------------------------------------------|:------|:------------
10335  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_E_UNMSKED | 0x0 |
10336  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_E_MSKED | 0x1 |
10337  *
10338  * Field Access Macros:
10339  *
10340  */
10341 /*
10342  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3
10343  *
10344  */
10345 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_E_UNMSKED 0x0
10346 /*
10347  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3
10348  *
10349  */
10350 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_E_MSKED 0x1
10351 
10352 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field. */
10353 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_LSB 27
10354 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field. */
10355 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_MSB 27
10356 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field. */
10357 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_WIDTH 1
10358 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field value. */
10359 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_SET_MSK 0x08000000
10360 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field value. */
10361 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_CLR_MSK 0xf7ffffff
10362 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field. */
10363 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_RESET 0x0
10364 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 field value from a register. */
10365 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
10366 /* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field value suitable for setting the register. */
10367 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
10368 
10369 /*
10370  * Field : Mask Byte Control - mbc_4
10371  *
10372  * This array of bits are mask control bits for comparison of each of the MAC
10373  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10374  * received DA or SA with the contents of MAC Address7 high and low registers. Each
10375  * bit controls the masking of the bytes. You can filter a group of addresses
10376  * (known as group address filtering) by masking one or more bytes of the address.
10377  *
10378  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10379  *
10380  * Field Enumeration Values:
10381  *
10382  * Enum | Value | Description
10383  * :---------------------------------------------|:------|:------------
10384  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_E_UNMSKED | 0x0 |
10385  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_E_MSKED | 0x1 |
10386  *
10387  * Field Access Macros:
10388  *
10389  */
10390 /*
10391  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4
10392  *
10393  */
10394 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_E_UNMSKED 0x0
10395 /*
10396  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4
10397  *
10398  */
10399 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_E_MSKED 0x1
10400 
10401 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field. */
10402 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_LSB 28
10403 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field. */
10404 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_MSB 28
10405 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field. */
10406 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_WIDTH 1
10407 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field value. */
10408 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_SET_MSK 0x10000000
10409 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field value. */
10410 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_CLR_MSK 0xefffffff
10411 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field. */
10412 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_RESET 0x0
10413 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 field value from a register. */
10414 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
10415 /* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field value suitable for setting the register. */
10416 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
10417 
10418 /*
10419  * Field : Mask Byte Control - mbc_5
10420  *
10421  * This array of bits are mask control bits for comparison of each of the MAC
10422  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10423  * received DA or SA with the contents of MAC Address7 high and low registers. Each
10424  * bit controls the masking of the bytes. You can filter a group of addresses
10425  * (known as group address filtering) by masking one or more bytes of the address.
10426  *
10427  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10428  *
10429  * Field Enumeration Values:
10430  *
10431  * Enum | Value | Description
10432  * :---------------------------------------------|:------|:------------
10433  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_E_UNMSKED | 0x0 |
10434  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_E_MSKED | 0x1 |
10435  *
10436  * Field Access Macros:
10437  *
10438  */
10439 /*
10440  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5
10441  *
10442  */
10443 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_E_UNMSKED 0x0
10444 /*
10445  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5
10446  *
10447  */
10448 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_E_MSKED 0x1
10449 
10450 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field. */
10451 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_LSB 29
10452 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field. */
10453 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_MSB 29
10454 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field. */
10455 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_WIDTH 1
10456 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field value. */
10457 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_SET_MSK 0x20000000
10458 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field value. */
10459 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_CLR_MSK 0xdfffffff
10460 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field. */
10461 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_RESET 0x0
10462 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 field value from a register. */
10463 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
10464 /* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field value suitable for setting the register. */
10465 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
10466 
10467 /*
10468  * Field : sa
10469  *
10470  * Source Address
10471  *
10472  * When this bit is set, the MAC Address7[47:0] is used to compare with the SA
10473  * fields of the received frame.
10474  *
10475  * When this bit is reset, the MAC Address7[47:0] is used to compare with the DA
10476  * fields of the received frame.
10477  *
10478  * Field Enumeration Values:
10479  *
10480  * Enum | Value | Description
10481  * :---------------------------------------|:------|:------------
10482  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_E_DISD | 0x0 |
10483  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_E_END | 0x1 |
10484  *
10485  * Field Access Macros:
10486  *
10487  */
10488 /*
10489  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA
10490  *
10491  */
10492 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_E_DISD 0x0
10493 /*
10494  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA
10495  *
10496  */
10497 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_E_END 0x1
10498 
10499 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field. */
10500 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_LSB 30
10501 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field. */
10502 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_MSB 30
10503 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field. */
10504 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_WIDTH 1
10505 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field value. */
10506 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_SET_MSK 0x40000000
10507 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field value. */
10508 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_CLR_MSK 0xbfffffff
10509 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field. */
10510 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_RESET 0x0
10511 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA field value from a register. */
10512 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
10513 /* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field value suitable for setting the register. */
10514 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
10515 
10516 /*
10517  * Field : ae
10518  *
10519  * Address Enable
10520  *
10521  * When this bit is set, the address filter module uses the eighth MAC address for
10522  * perfect filtering.
10523  *
10524  * When this bit is reset, the address filter module ignores the address for
10525  * filtering.
10526  *
10527  * Field Enumeration Values:
10528  *
10529  * Enum | Value | Description
10530  * :---------------------------------------|:------|:------------
10531  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_E_DISD | 0x0 |
10532  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_E_END | 0x1 |
10533  *
10534  * Field Access Macros:
10535  *
10536  */
10537 /*
10538  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE
10539  *
10540  */
10541 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_E_DISD 0x0
10542 /*
10543  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE
10544  *
10545  */
10546 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_E_END 0x1
10547 
10548 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field. */
10549 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_LSB 31
10550 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field. */
10551 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_MSB 31
10552 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field. */
10553 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_WIDTH 1
10554 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field value. */
10555 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_SET_MSK 0x80000000
10556 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field value. */
10557 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_CLR_MSK 0x7fffffff
10558 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field. */
10559 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_RESET 0x0
10560 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE field value from a register. */
10561 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
10562 /* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field value suitable for setting the register. */
10563 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
10564 
10565 #ifndef __ASSEMBLY__
10566 /*
10567  * WARNING: The C register and register group struct declarations are provided for
10568  * convenience and illustrative purposes. They should, however, be used with
10569  * caution as the C language standard provides no guarantees about the alignment or
10570  * atomicity of device memory accesses. The recommended practice for writing
10571  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10572  * alt_write_word() functions.
10573  *
10574  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR7_HIGH.
10575  */
10576 struct ALT_EMAC_GMAC_MAC_ADDR7_HIGH_s
10577 {
10578  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI */
10579  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR7_HIGH_RSVD_23_16 */
10580  uint32_t mbc_0 : 1; /* Mask Byte Control */
10581  uint32_t mbc_1 : 1; /* Mask Byte Control */
10582  uint32_t mbc_2 : 1; /* Mask Byte Control */
10583  uint32_t mbc_3 : 1; /* Mask Byte Control */
10584  uint32_t mbc_4 : 1; /* Mask Byte Control */
10585  uint32_t mbc_5 : 1; /* Mask Byte Control */
10586  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA */
10587  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE */
10588 };
10589 
10590 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR7_HIGH. */
10591 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR7_HIGH_s ALT_EMAC_GMAC_MAC_ADDR7_HIGH_t;
10592 #endif /* __ASSEMBLY__ */
10593 
10594 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH register. */
10595 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_RESET 0x0000ffff
10596 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH register from the beginning of the component. */
10597 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_OFST 0x78
10598 /* The address of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH register. */
10599 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR7_HIGH_OFST))
10600 
10601 /*
10602  * Register : gmacgrp_mac_address7_low
10603  *
10604  * <b> Register 31 (MAC Address7 Low Register) </b>
10605  *
10606  * The MAC Address7 Low register holds the lower 32 bits of the eighth 6-byte MAC
10607  * address of the station.
10608  *
10609  * Register Layout
10610  *
10611  * Bits | Access | Reset | Description
10612  * :-------|:-------|:-----------|:-----------------------------------
10613  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO
10614  *
10615  */
10616 /*
10617  * Field : addrlo
10618  *
10619  * MAC Address7 [31:0]
10620  *
10621  * This field contains the lower 32 bits of the eighth 6-byte MAC address. The
10622  * content of this field is undefined until loaded by the Application after the
10623  * initialization process.
10624  *
10625  * Field Access Macros:
10626  *
10627  */
10628 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field. */
10629 #define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_LSB 0
10630 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field. */
10631 #define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_MSB 31
10632 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field. */
10633 #define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_WIDTH 32
10634 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field value. */
10635 #define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_SET_MSK 0xffffffff
10636 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field value. */
10637 #define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_CLR_MSK 0x00000000
10638 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field. */
10639 #define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_RESET 0xffffffff
10640 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO field value from a register. */
10641 #define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
10642 /* Produces a ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field value suitable for setting the register. */
10643 #define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
10644 
10645 #ifndef __ASSEMBLY__
10646 /*
10647  * WARNING: The C register and register group struct declarations are provided for
10648  * convenience and illustrative purposes. They should, however, be used with
10649  * caution as the C language standard provides no guarantees about the alignment or
10650  * atomicity of device memory accesses. The recommended practice for writing
10651  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10652  * alt_write_word() functions.
10653  *
10654  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR7_LOW.
10655  */
10656 struct ALT_EMAC_GMAC_MAC_ADDR7_LOW_s
10657 {
10658  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO */
10659 };
10660 
10661 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR7_LOW. */
10662 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR7_LOW_s ALT_EMAC_GMAC_MAC_ADDR7_LOW_t;
10663 #endif /* __ASSEMBLY__ */
10664 
10665 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_LOW register. */
10666 #define ALT_EMAC_GMAC_MAC_ADDR7_LOW_RESET 0xffffffff
10667 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR7_LOW register from the beginning of the component. */
10668 #define ALT_EMAC_GMAC_MAC_ADDR7_LOW_OFST 0x7c
10669 /* The address of the ALT_EMAC_GMAC_MAC_ADDR7_LOW register. */
10670 #define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR7_LOW_OFST))
10671 
10672 /*
10673  * Register : gmacgrp_mac_address8_high
10674  *
10675  * <b> Register 32 (MAC Address8 High Register) </b>
10676  *
10677  * The MAC Address8 High register holds the upper 16 bits of the nineth 6-byte MAC
10678  * address of the station.
10679  *
10680  * If the MAC address registers are configured to be double-synchronized to the
10681  * (G)MII clock domains, then the synchronization is triggered only when
10682  * Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC
10683  * Address8 Low Register are written. For proper synchronization updates, the
10684  * consecutive writes to this MAC Address8 Low Register should be performed after
10685  * at least four clock cycles in the destination clock domain.
10686  *
10687  * Register Layout
10688  *
10689  * Bits | Access | Reset | Description
10690  * :--------|:-------|:-------|:----------------------------------------
10691  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI
10692  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR8_HIGH_RSVD_23_16
10693  * [24] | RW | 0x0 | Mask Byte Control
10694  * [25] | RW | 0x0 | Mask Byte Control
10695  * [26] | RW | 0x0 | Mask Byte Control
10696  * [27] | RW | 0x0 | Mask Byte Control
10697  * [28] | RW | 0x0 | Mask Byte Control
10698  * [29] | RW | 0x0 | Mask Byte Control
10699  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA
10700  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE
10701  *
10702  */
10703 /*
10704  * Field : addrhi
10705  *
10706  * MAC Address8 [47:32]
10707  *
10708  * This field contains the upper 16 bits (47:32) of the nineth 6-byte MAC address.
10709  *
10710  * Field Access Macros:
10711  *
10712  */
10713 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field. */
10714 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_LSB 0
10715 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field. */
10716 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_MSB 15
10717 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field. */
10718 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_WIDTH 16
10719 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field value. */
10720 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_SET_MSK 0x0000ffff
10721 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field value. */
10722 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_CLR_MSK 0xffff0000
10723 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field. */
10724 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_RESET 0xffff
10725 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI field value from a register. */
10726 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
10727 /* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field value suitable for setting the register. */
10728 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
10729 
10730 /*
10731  * Field : reserved_23_16
10732  *
10733  * Reserved
10734  *
10735  * Field Access Macros:
10736  *
10737  */
10738 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_RSVD_23_16 register field. */
10739 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_RSVD_23_16_LSB 16
10740 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_RSVD_23_16 register field. */
10741 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_RSVD_23_16_MSB 23
10742 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_RSVD_23_16 register field. */
10743 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_RSVD_23_16_WIDTH 8
10744 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_RSVD_23_16 register field value. */
10745 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
10746 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_RSVD_23_16 register field value. */
10747 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
10748 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_RSVD_23_16 register field. */
10749 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_RSVD_23_16_RESET 0x0
10750 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_RSVD_23_16 field value from a register. */
10751 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
10752 /* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_RSVD_23_16 register field value suitable for setting the register. */
10753 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
10754 
10755 /*
10756  * Field : Mask Byte Control - mbc_0
10757  *
10758  * This array of bits are mask control bits for comparison of each of the MAC
10759  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10760  * received DA or SA with the contents of MAC Address8 high and low registers. Each
10761  * bit controls the masking of the bytes. You can filter a group of addresses
10762  * (known as group address filtering) by masking one or more bytes of the address.
10763  *
10764  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10765  *
10766  * Field Enumeration Values:
10767  *
10768  * Enum | Value | Description
10769  * :---------------------------------------------|:------|:------------
10770  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_E_UNMSKED | 0x0 |
10771  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_E_MSKED | 0x1 |
10772  *
10773  * Field Access Macros:
10774  *
10775  */
10776 /*
10777  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0
10778  *
10779  */
10780 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_E_UNMSKED 0x0
10781 /*
10782  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0
10783  *
10784  */
10785 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_E_MSKED 0x1
10786 
10787 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field. */
10788 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_LSB 24
10789 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field. */
10790 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_MSB 24
10791 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field. */
10792 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_WIDTH 1
10793 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field value. */
10794 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_SET_MSK 0x01000000
10795 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field value. */
10796 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_CLR_MSK 0xfeffffff
10797 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field. */
10798 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_RESET 0x0
10799 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 field value from a register. */
10800 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
10801 /* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field value suitable for setting the register. */
10802 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
10803 
10804 /*
10805  * Field : Mask Byte Control - mbc_1
10806  *
10807  * This array of bits are mask control bits for comparison of each of the MAC
10808  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10809  * received DA or SA with the contents of MAC Address8 high and low registers. Each
10810  * bit controls the masking of the bytes. You can filter a group of addresses
10811  * (known as group address filtering) by masking one or more bytes of the address.
10812  *
10813  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10814  *
10815  * Field Enumeration Values:
10816  *
10817  * Enum | Value | Description
10818  * :---------------------------------------------|:------|:------------
10819  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_E_UNMSKED | 0x0 |
10820  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_E_MSKED | 0x1 |
10821  *
10822  * Field Access Macros:
10823  *
10824  */
10825 /*
10826  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1
10827  *
10828  */
10829 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_E_UNMSKED 0x0
10830 /*
10831  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1
10832  *
10833  */
10834 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_E_MSKED 0x1
10835 
10836 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field. */
10837 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_LSB 25
10838 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field. */
10839 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_MSB 25
10840 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field. */
10841 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_WIDTH 1
10842 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field value. */
10843 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_SET_MSK 0x02000000
10844 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field value. */
10845 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_CLR_MSK 0xfdffffff
10846 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field. */
10847 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_RESET 0x0
10848 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 field value from a register. */
10849 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
10850 /* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field value suitable for setting the register. */
10851 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
10852 
10853 /*
10854  * Field : Mask Byte Control - mbc_2
10855  *
10856  * This array of bits are mask control bits for comparison of each of the MAC
10857  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10858  * received DA or SA with the contents of MAC Address8 high and low registers. Each
10859  * bit controls the masking of the bytes. You can filter a group of addresses
10860  * (known as group address filtering) by masking one or more bytes of the address.
10861  *
10862  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10863  *
10864  * Field Enumeration Values:
10865  *
10866  * Enum | Value | Description
10867  * :---------------------------------------------|:------|:------------
10868  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_E_UNMSKED | 0x0 |
10869  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_E_MSKED | 0x1 |
10870  *
10871  * Field Access Macros:
10872  *
10873  */
10874 /*
10875  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2
10876  *
10877  */
10878 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_E_UNMSKED 0x0
10879 /*
10880  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2
10881  *
10882  */
10883 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_E_MSKED 0x1
10884 
10885 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field. */
10886 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_LSB 26
10887 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field. */
10888 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_MSB 26
10889 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field. */
10890 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_WIDTH 1
10891 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field value. */
10892 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_SET_MSK 0x04000000
10893 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field value. */
10894 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_CLR_MSK 0xfbffffff
10895 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field. */
10896 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_RESET 0x0
10897 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 field value from a register. */
10898 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
10899 /* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field value suitable for setting the register. */
10900 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
10901 
10902 /*
10903  * Field : Mask Byte Control - mbc_3
10904  *
10905  * This array of bits are mask control bits for comparison of each of the MAC
10906  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10907  * received DA or SA with the contents of MAC Address8 high and low registers. Each
10908  * bit controls the masking of the bytes. You can filter a group of addresses
10909  * (known as group address filtering) by masking one or more bytes of the address.
10910  *
10911  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10912  *
10913  * Field Enumeration Values:
10914  *
10915  * Enum | Value | Description
10916  * :---------------------------------------------|:------|:------------
10917  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_E_UNMSKED | 0x0 |
10918  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_E_MSKED | 0x1 |
10919  *
10920  * Field Access Macros:
10921  *
10922  */
10923 /*
10924  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3
10925  *
10926  */
10927 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_E_UNMSKED 0x0
10928 /*
10929  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3
10930  *
10931  */
10932 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_E_MSKED 0x1
10933 
10934 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field. */
10935 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_LSB 27
10936 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field. */
10937 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_MSB 27
10938 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field. */
10939 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_WIDTH 1
10940 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field value. */
10941 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_SET_MSK 0x08000000
10942 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field value. */
10943 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_CLR_MSK 0xf7ffffff
10944 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field. */
10945 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_RESET 0x0
10946 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 field value from a register. */
10947 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
10948 /* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field value suitable for setting the register. */
10949 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
10950 
10951 /*
10952  * Field : Mask Byte Control - mbc_4
10953  *
10954  * This array of bits are mask control bits for comparison of each of the MAC
10955  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10956  * received DA or SA with the contents of MAC Address8 high and low registers. Each
10957  * bit controls the masking of the bytes. You can filter a group of addresses
10958  * (known as group address filtering) by masking one or more bytes of the address.
10959  *
10960  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10961  *
10962  * Field Enumeration Values:
10963  *
10964  * Enum | Value | Description
10965  * :---------------------------------------------|:------|:------------
10966  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_E_UNMSKED | 0x0 |
10967  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_E_MSKED | 0x1 |
10968  *
10969  * Field Access Macros:
10970  *
10971  */
10972 /*
10973  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4
10974  *
10975  */
10976 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_E_UNMSKED 0x0
10977 /*
10978  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4
10979  *
10980  */
10981 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_E_MSKED 0x1
10982 
10983 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field. */
10984 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_LSB 28
10985 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field. */
10986 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_MSB 28
10987 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field. */
10988 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_WIDTH 1
10989 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field value. */
10990 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_SET_MSK 0x10000000
10991 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field value. */
10992 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_CLR_MSK 0xefffffff
10993 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field. */
10994 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_RESET 0x0
10995 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 field value from a register. */
10996 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
10997 /* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field value suitable for setting the register. */
10998 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
10999 
11000 /*
11001  * Field : Mask Byte Control - mbc_5
11002  *
11003  * This array of bits are mask control bits for comparison of each of the MAC
11004  * Address bytes. When masked, the MAC does not compare the corresponding byte of
11005  * received DA or SA with the contents of MAC Address8 high and low registers. Each
11006  * bit controls the masking of the bytes. You can filter a group of addresses
11007  * (known as group address filtering) by masking one or more bytes of the address.
11008  *
11009  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
11010  *
11011  * Field Enumeration Values:
11012  *
11013  * Enum | Value | Description
11014  * :---------------------------------------------|:------|:------------
11015  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_E_UNMSKED | 0x0 |
11016  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_E_MSKED | 0x1 |
11017  *
11018  * Field Access Macros:
11019  *
11020  */
11021 /*
11022  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5
11023  *
11024  */
11025 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_E_UNMSKED 0x0
11026 /*
11027  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5
11028  *
11029  */
11030 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_E_MSKED 0x1
11031 
11032 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field. */
11033 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_LSB 29
11034 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field. */
11035 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_MSB 29
11036 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field. */
11037 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_WIDTH 1
11038 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field value. */
11039 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_SET_MSK 0x20000000
11040 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field value. */
11041 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_CLR_MSK 0xdfffffff
11042 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field. */
11043 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_RESET 0x0
11044 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 field value from a register. */
11045 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
11046 /* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field value suitable for setting the register. */
11047 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
11048 
11049 /*
11050  * Field : sa
11051  *
11052  * Source Address
11053  *
11054  * When this bit is set, the MAC Address8[47:0] is used to compare with the SA
11055  * fields of the received frame. When this bit is reset, the MAC Address8[47:0] is
11056  * used to compare with the DA fields of the received frame.
11057  *
11058  * Field Enumeration Values:
11059  *
11060  * Enum | Value | Description
11061  * :---------------------------------------|:------|:------------
11062  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_E_DISD | 0x0 |
11063  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_E_END | 0x1 |
11064  *
11065  * Field Access Macros:
11066  *
11067  */
11068 /*
11069  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA
11070  *
11071  */
11072 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_E_DISD 0x0
11073 /*
11074  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA
11075  *
11076  */
11077 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_E_END 0x1
11078 
11079 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field. */
11080 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_LSB 30
11081 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field. */
11082 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_MSB 30
11083 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field. */
11084 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_WIDTH 1
11085 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field value. */
11086 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_SET_MSK 0x40000000
11087 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field value. */
11088 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_CLR_MSK 0xbfffffff
11089 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field. */
11090 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_RESET 0x0
11091 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA field value from a register. */
11092 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
11093 /* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field value suitable for setting the register. */
11094 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
11095 
11096 /*
11097  * Field : ae
11098  *
11099  * Address Enable
11100  *
11101  * When this bit is set, the address filter module uses the nineth MAC address for
11102  * perfect filtering. When this bit is reset, the address filter module ignores the
11103  * address for filtering.
11104  *
11105  * Field Enumeration Values:
11106  *
11107  * Enum | Value | Description
11108  * :---------------------------------------|:------|:------------
11109  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_E_DISD | 0x0 |
11110  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_E_END | 0x1 |
11111  *
11112  * Field Access Macros:
11113  *
11114  */
11115 /*
11116  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE
11117  *
11118  */
11119 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_E_DISD 0x0
11120 /*
11121  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE
11122  *
11123  */
11124 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_E_END 0x1
11125 
11126 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field. */
11127 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_LSB 31
11128 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field. */
11129 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_MSB 31
11130 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field. */
11131 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_WIDTH 1
11132 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field value. */
11133 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_SET_MSK 0x80000000
11134 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field value. */
11135 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_CLR_MSK 0x7fffffff
11136 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field. */
11137 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_RESET 0x0
11138 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE field value from a register. */
11139 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
11140 /* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field value suitable for setting the register. */
11141 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
11142 
11143 #ifndef __ASSEMBLY__
11144 /*
11145  * WARNING: The C register and register group struct declarations are provided for
11146  * convenience and illustrative purposes. They should, however, be used with
11147  * caution as the C language standard provides no guarantees about the alignment or
11148  * atomicity of device memory accesses. The recommended practice for writing
11149  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11150  * alt_write_word() functions.
11151  *
11152  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR8_HIGH.
11153  */
11154 struct ALT_EMAC_GMAC_MAC_ADDR8_HIGH_s
11155 {
11156  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI */
11157  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR8_HIGH_RSVD_23_16 */
11158  uint32_t mbc_0 : 1; /* Mask Byte Control */
11159  uint32_t mbc_1 : 1; /* Mask Byte Control */
11160  uint32_t mbc_2 : 1; /* Mask Byte Control */
11161  uint32_t mbc_3 : 1; /* Mask Byte Control */
11162  uint32_t mbc_4 : 1; /* Mask Byte Control */
11163  uint32_t mbc_5 : 1; /* Mask Byte Control */
11164  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA */
11165  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE */
11166 };
11167 
11168 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR8_HIGH. */
11169 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR8_HIGH_s ALT_EMAC_GMAC_MAC_ADDR8_HIGH_t;
11170 #endif /* __ASSEMBLY__ */
11171 
11172 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH register. */
11173 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_RESET 0x0000ffff
11174 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH register from the beginning of the component. */
11175 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_OFST 0x80
11176 /* The address of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH register. */
11177 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR8_HIGH_OFST))
11178 
11179 /*
11180  * Register : gmacgrp_mac_address8_low
11181  *
11182  * <b> Register 33 (MAC Address8 Low Register) </b>
11183  *
11184  * The MAC Address8 Low register holds the lower 32 bits of the nineth 6-byte MAC
11185  * address of the station.
11186  *
11187  * Register Layout
11188  *
11189  * Bits | Access | Reset | Description
11190  * :-------|:-------|:-----------|:-----------------------------------
11191  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO
11192  *
11193  */
11194 /*
11195  * Field : addrlo
11196  *
11197  * MAC Address8 [31:0]
11198  *
11199  * This field contains the lower 32 bits of the nineth 6-byte MAC address. The
11200  * content of this field is undefined until loaded by the Application after the
11201  * initialization process.
11202  *
11203  * Field Access Macros:
11204  *
11205  */
11206 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field. */
11207 #define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_LSB 0
11208 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field. */
11209 #define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_MSB 31
11210 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field. */
11211 #define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_WIDTH 32
11212 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field value. */
11213 #define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_SET_MSK 0xffffffff
11214 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field value. */
11215 #define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_CLR_MSK 0x00000000
11216 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field. */
11217 #define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_RESET 0xffffffff
11218 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO field value from a register. */
11219 #define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
11220 /* Produces a ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field value suitable for setting the register. */
11221 #define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
11222 
11223 #ifndef __ASSEMBLY__
11224 /*
11225  * WARNING: The C register and register group struct declarations are provided for
11226  * convenience and illustrative purposes. They should, however, be used with
11227  * caution as the C language standard provides no guarantees about the alignment or
11228  * atomicity of device memory accesses. The recommended practice for writing
11229  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11230  * alt_write_word() functions.
11231  *
11232  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR8_LOW.
11233  */
11234 struct ALT_EMAC_GMAC_MAC_ADDR8_LOW_s
11235 {
11236  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO */
11237 };
11238 
11239 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR8_LOW. */
11240 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR8_LOW_s ALT_EMAC_GMAC_MAC_ADDR8_LOW_t;
11241 #endif /* __ASSEMBLY__ */
11242 
11243 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_LOW register. */
11244 #define ALT_EMAC_GMAC_MAC_ADDR8_LOW_RESET 0xffffffff
11245 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR8_LOW register from the beginning of the component. */
11246 #define ALT_EMAC_GMAC_MAC_ADDR8_LOW_OFST 0x84
11247 /* The address of the ALT_EMAC_GMAC_MAC_ADDR8_LOW register. */
11248 #define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR8_LOW_OFST))
11249 
11250 /*
11251  * Register : gmacgrp_mac_address9_high
11252  *
11253  * <b> Register 34 (MAC Address9 High Register) </b>
11254  *
11255  * The MAC Address9 High register holds the upper 16 bits of the tenth 6-byte MAC
11256  * address of the station.
11257  *
11258  * If the MAC address registers are configured to be double-synchronized to the
11259  * (G)MII clock domains, then the synchronization is triggered only when
11260  * Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC
11261  * Address9 Low Register are written. For proper synchronization updates, the
11262  * consecutive writes to this MAC Address9 Low Register should be performed after
11263  * at least four clock cycles in the destination clock domain.
11264  *
11265  * Register Layout
11266  *
11267  * Bits | Access | Reset | Description
11268  * :--------|:-------|:-------|:----------------------------------------
11269  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI
11270  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR9_HIGH_RSVD_23_16
11271  * [24] | RW | 0x0 | Mask Byte Control
11272  * [25] | RW | 0x0 | Mask Byte Control
11273  * [26] | RW | 0x0 | Mask Byte Control
11274  * [27] | RW | 0x0 | Mask Byte Control
11275  * [28] | RW | 0x0 | Mask Byte Control
11276  * [29] | RW | 0x0 | Mask Byte Control
11277  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA
11278  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE
11279  *
11280  */
11281 /*
11282  * Field : addrhi
11283  *
11284  * MAC Address9 [47:32]
11285  *
11286  * This field contains the upper 16 bits (47:32) of the tenth 6-byte MAC address.
11287  *
11288  * Field Access Macros:
11289  *
11290  */
11291 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field. */
11292 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_LSB 0
11293 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field. */
11294 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_MSB 15
11295 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field. */
11296 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_WIDTH 16
11297 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field value. */
11298 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_SET_MSK 0x0000ffff
11299 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field value. */
11300 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_CLR_MSK 0xffff0000
11301 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field. */
11302 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_RESET 0xffff
11303 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI field value from a register. */
11304 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
11305 /* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field value suitable for setting the register. */
11306 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
11307 
11308 /*
11309  * Field : reserved_23_16
11310  *
11311  * Reserved
11312  *
11313  * Field Access Macros:
11314  *
11315  */
11316 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_RSVD_23_16 register field. */
11317 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_RSVD_23_16_LSB 16
11318 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_RSVD_23_16 register field. */
11319 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_RSVD_23_16_MSB 23
11320 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_RSVD_23_16 register field. */
11321 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_RSVD_23_16_WIDTH 8
11322 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_RSVD_23_16 register field value. */
11323 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
11324 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_RSVD_23_16 register field value. */
11325 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
11326 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_RSVD_23_16 register field. */
11327 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_RSVD_23_16_RESET 0x0
11328 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_RSVD_23_16 field value from a register. */
11329 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
11330 /* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_RSVD_23_16 register field value suitable for setting the register. */
11331 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
11332 
11333 /*
11334  * Field : Mask Byte Control - mbc_0
11335  *
11336  * This array of bits are mask control bits for comparison of each of the MAC
11337  * Address bytes. When masked, the MAC does not compare the corresponding byte of
11338  * received DA or SA with the contents of MAC Address9 high and low registers. Each
11339  * bit controls the masking of the bytes. You can filter a group of addresses
11340  * (known as group address filtering) by masking one or more bytes of the address.
11341  *
11342  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
11343  *
11344  * Field Enumeration Values:
11345  *
11346  * Enum | Value | Description
11347  * :---------------------------------------------|:------|:------------
11348  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_E_UNMSKED | 0x0 |
11349  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_E_MSKED | 0x1 |
11350  *
11351  * Field Access Macros:
11352  *
11353  */
11354 /*
11355  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0
11356  *
11357  */
11358 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_E_UNMSKED 0x0
11359 /*
11360  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0
11361  *
11362  */
11363 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_E_MSKED 0x1
11364 
11365 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field. */
11366 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_LSB 24
11367 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field. */
11368 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_MSB 24
11369 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field. */
11370 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_WIDTH 1
11371 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field value. */
11372 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_SET_MSK 0x01000000
11373 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field value. */
11374 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_CLR_MSK 0xfeffffff
11375 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field. */
11376 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_RESET 0x0
11377 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 field value from a register. */
11378 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
11379 /* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field value suitable for setting the register. */
11380 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
11381 
11382 /*
11383  * Field : Mask Byte Control - mbc_1
11384  *
11385  * This array of bits are mask control bits for comparison of each of the MAC
11386  * Address bytes. When masked, the MAC does not compare the corresponding byte of
11387  * received DA or SA with the contents of MAC Address9 high and low registers. Each
11388  * bit controls the masking of the bytes. You can filter a group of addresses
11389  * (known as group address filtering) by masking one or more bytes of the address.
11390  *
11391  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
11392  *
11393  * Field Enumeration Values:
11394  *
11395  * Enum | Value | Description
11396  * :---------------------------------------------|:------|:------------
11397  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_E_UNMSKED | 0x0 |
11398  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_E_MSKED | 0x1 |
11399  *
11400  * Field Access Macros:
11401  *
11402  */
11403 /*
11404  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1
11405  *
11406  */
11407 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_E_UNMSKED 0x0
11408 /*
11409  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1
11410  *
11411  */
11412 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_E_MSKED 0x1
11413 
11414 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field. */
11415 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_LSB 25
11416 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field. */
11417 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_MSB 25
11418 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field. */
11419 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_WIDTH 1
11420 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field value. */
11421 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_SET_MSK 0x02000000
11422 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field value. */
11423 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_CLR_MSK 0xfdffffff
11424 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field. */
11425 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_RESET 0x0
11426 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 field value from a register. */
11427 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
11428 /* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field value suitable for setting the register. */
11429 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
11430 
11431 /*
11432  * Field : Mask Byte Control - mbc_2
11433  *
11434  * This array of bits are mask control bits for comparison of each of the MAC
11435  * Address bytes. When masked, the MAC does not compare the corresponding byte of
11436  * received DA or SA with the contents of MAC Address9 high and low registers. Each
11437  * bit controls the masking of the bytes. You can filter a group of addresses
11438  * (known as group address filtering) by masking one or more bytes of the address.
11439  *
11440  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
11441  *
11442  * Field Enumeration Values:
11443  *
11444  * Enum | Value | Description
11445  * :---------------------------------------------|:------|:------------
11446  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_E_UNMSKED | 0x0 |
11447  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_E_MSKED | 0x1 |
11448  *
11449  * Field Access Macros:
11450  *
11451  */
11452 /*
11453  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2
11454  *
11455  */
11456 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_E_UNMSKED 0x0
11457 /*
11458  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2
11459  *
11460  */
11461 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_E_MSKED 0x1
11462 
11463 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field. */
11464 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_LSB 26
11465 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field. */
11466 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_MSB 26
11467 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field. */
11468 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_WIDTH 1
11469 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field value. */
11470 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_SET_MSK 0x04000000
11471 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field value. */
11472 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_CLR_MSK 0xfbffffff
11473 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field. */
11474 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_RESET 0x0
11475 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 field value from a register. */
11476 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
11477 /* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field value suitable for setting the register. */
11478 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
11479 
11480 /*
11481  * Field : Mask Byte Control - mbc_3
11482  *
11483  * This array of bits are mask control bits for comparison of each of the MAC
11484  * Address bytes. When masked, the MAC does not compare the corresponding byte of
11485  * received DA or SA with the contents of MAC Address9 high and low registers. Each
11486  * bit controls the masking of the bytes. You can filter a group of addresses
11487  * (known as group address filtering) by masking one or more bytes of the address.
11488  *
11489  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
11490  *
11491  * Field Enumeration Values:
11492  *
11493  * Enum | Value | Description
11494  * :---------------------------------------------|:------|:------------
11495  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_E_UNMSKED | 0x0 |
11496  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_E_MSKED | 0x1 |
11497  *
11498  * Field Access Macros:
11499  *
11500  */
11501 /*
11502  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3
11503  *
11504  */
11505 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_E_UNMSKED 0x0
11506 /*
11507  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3
11508  *
11509  */
11510 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_E_MSKED 0x1
11511 
11512 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field. */
11513 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_LSB 27
11514 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field. */
11515 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_MSB 27
11516 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field. */
11517 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_WIDTH 1
11518 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field value. */
11519 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_SET_MSK 0x08000000
11520 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field value. */
11521 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_CLR_MSK 0xf7ffffff
11522 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field. */
11523 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_RESET 0x0
11524 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 field value from a register. */
11525 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
11526 /* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field value suitable for setting the register. */
11527 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
11528 
11529 /*
11530  * Field : Mask Byte Control - mbc_4
11531  *
11532  * This array of bits are mask control bits for comparison of each of the MAC
11533  * Address bytes. When masked, the MAC does not compare the corresponding byte of
11534  * received DA or SA with the contents of MAC Address9 high and low registers. Each
11535  * bit controls the masking of the bytes. You can filter a group of addresses
11536  * (known as group address filtering) by masking one or more bytes of the address.
11537  *
11538  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
11539  *
11540  * Field Enumeration Values:
11541  *
11542  * Enum | Value | Description
11543  * :---------------------------------------------|:------|:------------
11544  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_E_UNMSKED | 0x0 |
11545  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_E_MSKED | 0x1 |
11546  *
11547  * Field Access Macros:
11548  *
11549  */
11550 /*
11551  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4
11552  *
11553  */
11554 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_E_UNMSKED 0x0
11555 /*
11556  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4
11557  *
11558  */
11559 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_E_MSKED 0x1
11560 
11561 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field. */
11562 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_LSB 28
11563 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field. */
11564 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_MSB 28
11565 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field. */
11566 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_WIDTH 1
11567 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field value. */
11568 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_SET_MSK 0x10000000
11569 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field value. */
11570 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_CLR_MSK 0xefffffff
11571 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field. */
11572 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_RESET 0x0
11573 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 field value from a register. */
11574 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
11575 /* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field value suitable for setting the register. */
11576 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
11577 
11578 /*
11579  * Field : Mask Byte Control - mbc_5
11580  *
11581  * This array of bits are mask control bits for comparison of each of the MAC
11582  * Address bytes. When masked, the MAC does not compare the corresponding byte of
11583  * received DA or SA with the contents of MAC Address9 high and low registers. Each
11584  * bit controls the masking of the bytes. You can filter a group of addresses
11585  * (known as group address filtering) by masking one or more bytes of the address.
11586  *
11587  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
11588  *
11589  * Field Enumeration Values:
11590  *
11591  * Enum | Value | Description
11592  * :---------------------------------------------|:------|:------------
11593  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_E_UNMSKED | 0x0 |
11594  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_E_MSKED | 0x1 |
11595  *
11596  * Field Access Macros:
11597  *
11598  */
11599 /*
11600  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5
11601  *
11602  */
11603 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_E_UNMSKED 0x0
11604 /*
11605  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5
11606  *
11607  */
11608 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_E_MSKED 0x1
11609 
11610 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field. */
11611 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_LSB 29
11612 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field. */
11613 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_MSB 29
11614 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field. */
11615 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_WIDTH 1
11616 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field value. */
11617 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_SET_MSK 0x20000000
11618 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field value. */
11619 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_CLR_MSK 0xdfffffff
11620 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field. */
11621 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_RESET 0x0
11622 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 field value from a register. */
11623 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
11624 /* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field value suitable for setting the register. */
11625 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
11626 
11627 /*
11628  * Field : sa
11629  *
11630  * Source Address
11631  *
11632  * When this bit is set, the MAC Address9[47:0] is used to compare with the SA
11633  * fields of the received frame.
11634  *
11635  * When this bit is reset, the MAC Address9[47:0] is used to compare with the DA
11636  * fields of the received frame.
11637  *
11638  * Field Enumeration Values:
11639  *
11640  * Enum | Value | Description
11641  * :---------------------------------------|:------|:------------
11642  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_E_DISD | 0x0 |
11643  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_E_END | 0x1 |
11644  *
11645  * Field Access Macros:
11646  *
11647  */
11648 /*
11649  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA
11650  *
11651  */
11652 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_E_DISD 0x0
11653 /*
11654  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA
11655  *
11656  */
11657 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_E_END 0x1
11658 
11659 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field. */
11660 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_LSB 30
11661 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field. */
11662 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_MSB 30
11663 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field. */
11664 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_WIDTH 1
11665 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field value. */
11666 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_SET_MSK 0x40000000
11667 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field value. */
11668 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_CLR_MSK 0xbfffffff
11669 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field. */
11670 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_RESET 0x0
11671 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA field value from a register. */
11672 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
11673 /* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field value suitable for setting the register. */
11674 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
11675 
11676 /*
11677  * Field : ae
11678  *
11679  * Address Enable
11680  *
11681  * When this bit is set, the address filter module uses the tenth MAC address for
11682  * perfect filtering. When this bit is reset, the address filter module ignores the
11683  * address for filtering.
11684  *
11685  * Field Enumeration Values:
11686  *
11687  * Enum | Value | Description
11688  * :---------------------------------------|:------|:------------
11689  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_E_DISD | 0x0 |
11690  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_E_END | 0x1 |
11691  *
11692  * Field Access Macros:
11693  *
11694  */
11695 /*
11696  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE
11697  *
11698  */
11699 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_E_DISD 0x0
11700 /*
11701  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE
11702  *
11703  */
11704 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_E_END 0x1
11705 
11706 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field. */
11707 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_LSB 31
11708 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field. */
11709 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_MSB 31
11710 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field. */
11711 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_WIDTH 1
11712 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field value. */
11713 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_SET_MSK 0x80000000
11714 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field value. */
11715 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_CLR_MSK 0x7fffffff
11716 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field. */
11717 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_RESET 0x0
11718 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE field value from a register. */
11719 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
11720 /* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field value suitable for setting the register. */
11721 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
11722 
11723 #ifndef __ASSEMBLY__
11724 /*
11725  * WARNING: The C register and register group struct declarations are provided for
11726  * convenience and illustrative purposes. They should, however, be used with
11727  * caution as the C language standard provides no guarantees about the alignment or
11728  * atomicity of device memory accesses. The recommended practice for writing
11729  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11730  * alt_write_word() functions.
11731  *
11732  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR9_HIGH.
11733  */
11734 struct ALT_EMAC_GMAC_MAC_ADDR9_HIGH_s
11735 {
11736  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI */
11737  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR9_HIGH_RSVD_23_16 */
11738  uint32_t mbc_0 : 1; /* Mask Byte Control */
11739  uint32_t mbc_1 : 1; /* Mask Byte Control */
11740  uint32_t mbc_2 : 1; /* Mask Byte Control */
11741  uint32_t mbc_3 : 1; /* Mask Byte Control */
11742  uint32_t mbc_4 : 1; /* Mask Byte Control */
11743  uint32_t mbc_5 : 1; /* Mask Byte Control */
11744  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA */
11745  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE */
11746 };
11747 
11748 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR9_HIGH. */
11749 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR9_HIGH_s ALT_EMAC_GMAC_MAC_ADDR9_HIGH_t;
11750 #endif /* __ASSEMBLY__ */
11751 
11752 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH register. */
11753 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_RESET 0x0000ffff
11754 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH register from the beginning of the component. */
11755 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_OFST 0x88
11756 /* The address of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH register. */
11757 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR9_HIGH_OFST))
11758 
11759 /*
11760  * Register : gmacgrp_mac_address9_low
11761  *
11762  * <b> Register 35 (MAC Address9 Low Register) </b>
11763  *
11764  * The MAC Address9 Low register holds the lower 32 bits of the tenth 6-byte MAC
11765  * address of the station.
11766  *
11767  * Register Layout
11768  *
11769  * Bits | Access | Reset | Description
11770  * :-------|:-------|:-----------|:-----------------------------------
11771  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO
11772  *
11773  */
11774 /*
11775  * Field : addrlo
11776  *
11777  * MAC Address9 [31:0]
11778  *
11779  * This field contains the lower 32 bits of the tenth 6-byte MAC address. The
11780  * content of this field is undefined until loaded by the Application after the
11781  * initialization process.
11782  *
11783  * Field Access Macros:
11784  *
11785  */
11786 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field. */
11787 #define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_LSB 0
11788 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field. */
11789 #define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_MSB 31
11790 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field. */
11791 #define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_WIDTH 32
11792 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field value. */
11793 #define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_SET_MSK 0xffffffff
11794 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field value. */
11795 #define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_CLR_MSK 0x00000000
11796 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field. */
11797 #define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_RESET 0xffffffff
11798 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO field value from a register. */
11799 #define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
11800 /* Produces a ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field value suitable for setting the register. */
11801 #define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
11802 
11803 #ifndef __ASSEMBLY__
11804 /*
11805  * WARNING: The C register and register group struct declarations are provided for
11806  * convenience and illustrative purposes. They should, however, be used with
11807  * caution as the C language standard provides no guarantees about the alignment or
11808  * atomicity of device memory accesses. The recommended practice for writing
11809  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11810  * alt_write_word() functions.
11811  *
11812  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR9_LOW.
11813  */
11814 struct ALT_EMAC_GMAC_MAC_ADDR9_LOW_s
11815 {
11816  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO */
11817 };
11818 
11819 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR9_LOW. */
11820 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR9_LOW_s ALT_EMAC_GMAC_MAC_ADDR9_LOW_t;
11821 #endif /* __ASSEMBLY__ */
11822 
11823 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_LOW register. */
11824 #define ALT_EMAC_GMAC_MAC_ADDR9_LOW_RESET 0xffffffff
11825 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR9_LOW register from the beginning of the component. */
11826 #define ALT_EMAC_GMAC_MAC_ADDR9_LOW_OFST 0x8c
11827 /* The address of the ALT_EMAC_GMAC_MAC_ADDR9_LOW register. */
11828 #define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR9_LOW_OFST))
11829 
11830 /*
11831  * Register : gmacgrp_mac_address10_high
11832  *
11833  * <b> Register 36 (MAC Address10 High Register) </b>
11834  *
11835  * The MAC Address10 High register holds the upper 16 bits of the 11th 6-byte MAC
11836  * address of the station.
11837  *
11838  * If the MAC address registers are configured to be double-synchronized to the
11839  * (G)MII clock domains, then the synchronization is triggered only when
11840  * Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC
11841  * Address10 Low Register are written. For proper synchronization updates, the
11842  * consecutive writes to this MAC Address10 Low Register should be performed after
11843  * at least four clock cycles in the destination clock domain.
11844  *
11845  * Register Layout
11846  *
11847  * Bits | Access | Reset | Description
11848  * :--------|:-------|:-------|:-----------------------------------------
11849  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI
11850  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR10_HIGH_RSVD_23_16
11851  * [24] | RW | 0x0 | Mask Byte Control
11852  * [25] | RW | 0x0 | Mask Byte Control
11853  * [26] | RW | 0x0 | Mask Byte Control
11854  * [27] | RW | 0x0 | Mask Byte Control
11855  * [28] | RW | 0x0 | Mask Byte Control
11856  * [29] | RW | 0x0 | Mask Byte Control
11857  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA
11858  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE
11859  *
11860  */
11861 /*
11862  * Field : addrhi
11863  *
11864  * MAC Address10 [47:32]
11865  *
11866  * This field contains the upper 16 bits (47:32) of the 11th 6-byte MAC address.
11867  *
11868  * Field Access Macros:
11869  *
11870  */
11871 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field. */
11872 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_LSB 0
11873 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field. */
11874 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_MSB 15
11875 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field. */
11876 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_WIDTH 16
11877 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field value. */
11878 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_SET_MSK 0x0000ffff
11879 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field value. */
11880 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_CLR_MSK 0xffff0000
11881 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field. */
11882 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_RESET 0xffff
11883 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI field value from a register. */
11884 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
11885 /* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field value suitable for setting the register. */
11886 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
11887 
11888 /*
11889  * Field : reserved_23_16
11890  *
11891  * Reserved
11892  *
11893  * Field Access Macros:
11894  *
11895  */
11896 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_RSVD_23_16 register field. */
11897 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_RSVD_23_16_LSB 16
11898 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_RSVD_23_16 register field. */
11899 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_RSVD_23_16_MSB 23
11900 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_RSVD_23_16 register field. */
11901 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_RSVD_23_16_WIDTH 8
11902 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_RSVD_23_16 register field value. */
11903 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
11904 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_RSVD_23_16 register field value. */
11905 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
11906 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_RSVD_23_16 register field. */
11907 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_RSVD_23_16_RESET 0x0
11908 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_RSVD_23_16 field value from a register. */
11909 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
11910 /* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_RSVD_23_16 register field value suitable for setting the register. */
11911 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
11912 
11913 /*
11914  * Field : Mask Byte Control - mbc_0
11915  *
11916  * This array of bits are mask control bits for comparison of each of the MAC
11917  * Address bytes. When masked, the MAC does not compare the corresponding byte of
11918  * received DA or SA with the contents of MAC Address10 high and low registers.
11919  * Each bit controls the masking of the bytes. You can filter a group of addresses
11920  * (known as group address filtering) by masking one or more bytes of the address.
11921  *
11922  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
11923  *
11924  * Field Enumeration Values:
11925  *
11926  * Enum | Value | Description
11927  * :----------------------------------------------|:------|:------------
11928  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_E_UNMSKED | 0x0 |
11929  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_E_MSKED | 0x1 |
11930  *
11931  * Field Access Macros:
11932  *
11933  */
11934 /*
11935  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0
11936  *
11937  */
11938 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_E_UNMSKED 0x0
11939 /*
11940  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0
11941  *
11942  */
11943 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_E_MSKED 0x1
11944 
11945 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field. */
11946 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_LSB 24
11947 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field. */
11948 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_MSB 24
11949 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field. */
11950 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_WIDTH 1
11951 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field value. */
11952 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_SET_MSK 0x01000000
11953 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field value. */
11954 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_CLR_MSK 0xfeffffff
11955 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field. */
11956 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_RESET 0x0
11957 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 field value from a register. */
11958 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
11959 /* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field value suitable for setting the register. */
11960 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
11961 
11962 /*
11963  * Field : Mask Byte Control - mbc_1
11964  *
11965  * This array of bits are mask control bits for comparison of each of the MAC
11966  * Address bytes. When masked, the MAC does not compare the corresponding byte of
11967  * received DA or SA with the contents of MAC Address10 high and low registers.
11968  * Each bit controls the masking of the bytes. You can filter a group of addresses
11969  * (known as group address filtering) by masking one or more bytes of the address.
11970  *
11971  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
11972  *
11973  * Field Enumeration Values:
11974  *
11975  * Enum | Value | Description
11976  * :----------------------------------------------|:------|:------------
11977  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_E_UNMSKED | 0x0 |
11978  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_E_MSKED | 0x1 |
11979  *
11980  * Field Access Macros:
11981  *
11982  */
11983 /*
11984  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1
11985  *
11986  */
11987 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_E_UNMSKED 0x0
11988 /*
11989  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1
11990  *
11991  */
11992 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_E_MSKED 0x1
11993 
11994 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field. */
11995 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_LSB 25
11996 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field. */
11997 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_MSB 25
11998 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field. */
11999 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_WIDTH 1
12000 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field value. */
12001 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_SET_MSK 0x02000000
12002 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field value. */
12003 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_CLR_MSK 0xfdffffff
12004 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field. */
12005 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_RESET 0x0
12006 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 field value from a register. */
12007 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
12008 /* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field value suitable for setting the register. */
12009 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
12010 
12011 /*
12012  * Field : Mask Byte Control - mbc_2
12013  *
12014  * This array of bits are mask control bits for comparison of each of the MAC
12015  * Address bytes. When masked, the MAC does not compare the corresponding byte of
12016  * received DA or SA with the contents of MAC Address10 high and low registers.
12017  * Each bit controls the masking of the bytes. You can filter a group of addresses
12018  * (known as group address filtering) by masking one or more bytes of the address.
12019  *
12020  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
12021  *
12022  * Field Enumeration Values:
12023  *
12024  * Enum | Value | Description
12025  * :----------------------------------------------|:------|:------------
12026  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_E_UNMSKED | 0x0 |
12027  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_E_MSKED | 0x1 |
12028  *
12029  * Field Access Macros:
12030  *
12031  */
12032 /*
12033  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2
12034  *
12035  */
12036 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_E_UNMSKED 0x0
12037 /*
12038  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2
12039  *
12040  */
12041 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_E_MSKED 0x1
12042 
12043 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field. */
12044 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_LSB 26
12045 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field. */
12046 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_MSB 26
12047 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field. */
12048 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_WIDTH 1
12049 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field value. */
12050 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_SET_MSK 0x04000000
12051 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field value. */
12052 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_CLR_MSK 0xfbffffff
12053 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field. */
12054 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_RESET 0x0
12055 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 field value from a register. */
12056 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
12057 /* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field value suitable for setting the register. */
12058 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
12059 
12060 /*
12061  * Field : Mask Byte Control - mbc_3
12062  *
12063  * This array of bits are mask control bits for comparison of each of the MAC
12064  * Address bytes. When masked, the MAC does not compare the corresponding byte of
12065  * received DA or SA with the contents of MAC Address10 high and low registers.
12066  * Each bit controls the masking of the bytes. You can filter a group of addresses
12067  * (known as group address filtering) by masking one or more bytes of the address.
12068  *
12069  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
12070  *
12071  * Field Enumeration Values:
12072  *
12073  * Enum | Value | Description
12074  * :----------------------------------------------|:------|:------------
12075  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_E_UNMSKED | 0x0 |
12076  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_E_MSKED | 0x1 |
12077  *
12078  * Field Access Macros:
12079  *
12080  */
12081 /*
12082  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3
12083  *
12084  */
12085 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_E_UNMSKED 0x0
12086 /*
12087  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3
12088  *
12089  */
12090 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_E_MSKED 0x1
12091 
12092 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field. */
12093 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_LSB 27
12094 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field. */
12095 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_MSB 27
12096 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field. */
12097 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_WIDTH 1
12098 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field value. */
12099 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_SET_MSK 0x08000000
12100 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field value. */
12101 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_CLR_MSK 0xf7ffffff
12102 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field. */
12103 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_RESET 0x0
12104 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 field value from a register. */
12105 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
12106 /* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field value suitable for setting the register. */
12107 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
12108 
12109 /*
12110  * Field : Mask Byte Control - mbc_4
12111  *
12112  * This array of bits are mask control bits for comparison of each of the MAC
12113  * Address bytes. When masked, the MAC does not compare the corresponding byte of
12114  * received DA or SA with the contents of MAC Address10 high and low registers.
12115  * Each bit controls the masking of the bytes. You can filter a group of addresses
12116  * (known as group address filtering) by masking one or more bytes of the address.
12117  *
12118  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
12119  *
12120  * Field Enumeration Values:
12121  *
12122  * Enum | Value | Description
12123  * :----------------------------------------------|:------|:------------
12124  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_E_UNMSKED | 0x0 |
12125  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_E_MSKED | 0x1 |
12126  *
12127  * Field Access Macros:
12128  *
12129  */
12130 /*
12131  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4
12132  *
12133  */
12134 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_E_UNMSKED 0x0
12135 /*
12136  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4
12137  *
12138  */
12139 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_E_MSKED 0x1
12140 
12141 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field. */
12142 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_LSB 28
12143 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field. */
12144 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_MSB 28
12145 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field. */
12146 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_WIDTH 1
12147 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field value. */
12148 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_SET_MSK 0x10000000
12149 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field value. */
12150 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_CLR_MSK 0xefffffff
12151 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field. */
12152 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_RESET 0x0
12153 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 field value from a register. */
12154 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
12155 /* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field value suitable for setting the register. */
12156 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
12157 
12158 /*
12159  * Field : Mask Byte Control - mbc_5
12160  *
12161  * This array of bits are mask control bits for comparison of each of the MAC
12162  * Address bytes. When masked, the MAC does not compare the corresponding byte of
12163  * received DA or SA with the contents of MAC Address10 high and low registers.
12164  * Each bit controls the masking of the bytes. You can filter a group of addresses
12165  * (known as group address filtering) by masking one or more bytes of the address.
12166  *
12167  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
12168  *
12169  * Field Enumeration Values:
12170  *
12171  * Enum | Value | Description
12172  * :----------------------------------------------|:------|:------------
12173  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_E_UNMSKED | 0x0 |
12174  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_E_MSKED | 0x1 |
12175  *
12176  * Field Access Macros:
12177  *
12178  */
12179 /*
12180  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5
12181  *
12182  */
12183 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_E_UNMSKED 0x0
12184 /*
12185  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5
12186  *
12187  */
12188 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_E_MSKED 0x1
12189 
12190 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field. */
12191 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_LSB 29
12192 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field. */
12193 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_MSB 29
12194 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field. */
12195 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_WIDTH 1
12196 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field value. */
12197 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_SET_MSK 0x20000000
12198 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field value. */
12199 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_CLR_MSK 0xdfffffff
12200 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field. */
12201 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_RESET 0x0
12202 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 field value from a register. */
12203 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
12204 /* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field value suitable for setting the register. */
12205 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
12206 
12207 /*
12208  * Field : sa
12209  *
12210  * Source Address
12211  *
12212  * When this bit is set, the MAC Address10[47:0] is used to compare with the SA
12213  * fields of the received frame. When this bit is reset, the MAC Address10[47:0] is
12214  * used to compare with the DA fields of the received frame.
12215  *
12216  * Field Enumeration Values:
12217  *
12218  * Enum | Value | Description
12219  * :----------------------------------------|:------|:------------
12220  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_E_DISD | 0x0 |
12221  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_E_END | 0x1 |
12222  *
12223  * Field Access Macros:
12224  *
12225  */
12226 /*
12227  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA
12228  *
12229  */
12230 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_E_DISD 0x0
12231 /*
12232  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA
12233  *
12234  */
12235 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_E_END 0x1
12236 
12237 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field. */
12238 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_LSB 30
12239 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field. */
12240 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_MSB 30
12241 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field. */
12242 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_WIDTH 1
12243 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field value. */
12244 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_SET_MSK 0x40000000
12245 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field value. */
12246 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_CLR_MSK 0xbfffffff
12247 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field. */
12248 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_RESET 0x0
12249 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA field value from a register. */
12250 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
12251 /* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field value suitable for setting the register. */
12252 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
12253 
12254 /*
12255  * Field : ae
12256  *
12257  * Address Enable
12258  *
12259  * When this bit is set, the address filter module uses the 11th MAC address for
12260  * perfect filtering. When this bit is reset, the address filter module ignores the
12261  * address for filtering.
12262  *
12263  * Field Enumeration Values:
12264  *
12265  * Enum | Value | Description
12266  * :----------------------------------------|:------|:------------
12267  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_E_DISD | 0x0 |
12268  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_E_END | 0x1 |
12269  *
12270  * Field Access Macros:
12271  *
12272  */
12273 /*
12274  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE
12275  *
12276  */
12277 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_E_DISD 0x0
12278 /*
12279  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE
12280  *
12281  */
12282 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_E_END 0x1
12283 
12284 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field. */
12285 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_LSB 31
12286 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field. */
12287 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_MSB 31
12288 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field. */
12289 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_WIDTH 1
12290 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field value. */
12291 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_SET_MSK 0x80000000
12292 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field value. */
12293 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_CLR_MSK 0x7fffffff
12294 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field. */
12295 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_RESET 0x0
12296 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE field value from a register. */
12297 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
12298 /* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field value suitable for setting the register. */
12299 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
12300 
12301 #ifndef __ASSEMBLY__
12302 /*
12303  * WARNING: The C register and register group struct declarations are provided for
12304  * convenience and illustrative purposes. They should, however, be used with
12305  * caution as the C language standard provides no guarantees about the alignment or
12306  * atomicity of device memory accesses. The recommended practice for writing
12307  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12308  * alt_write_word() functions.
12309  *
12310  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR10_HIGH.
12311  */
12312 struct ALT_EMAC_GMAC_MAC_ADDR10_HIGH_s
12313 {
12314  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI */
12315  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR10_HIGH_RSVD_23_16 */
12316  uint32_t mbc_0 : 1; /* Mask Byte Control */
12317  uint32_t mbc_1 : 1; /* Mask Byte Control */
12318  uint32_t mbc_2 : 1; /* Mask Byte Control */
12319  uint32_t mbc_3 : 1; /* Mask Byte Control */
12320  uint32_t mbc_4 : 1; /* Mask Byte Control */
12321  uint32_t mbc_5 : 1; /* Mask Byte Control */
12322  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA */
12323  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE */
12324 };
12325 
12326 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR10_HIGH. */
12327 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR10_HIGH_s ALT_EMAC_GMAC_MAC_ADDR10_HIGH_t;
12328 #endif /* __ASSEMBLY__ */
12329 
12330 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH register. */
12331 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_RESET 0x0000ffff
12332 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH register from the beginning of the component. */
12333 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_OFST 0x90
12334 /* The address of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH register. */
12335 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR10_HIGH_OFST))
12336 
12337 /*
12338  * Register : gmacgrp_mac_address10_low
12339  *
12340  * <b> Register 37 (MAC Address10 Low Register) </b>
12341  *
12342  * The MAC Address10 Low register holds the lower 32 bits of the 11th 6-byte MAC
12343  * address of the station.
12344  *
12345  * Register Layout
12346  *
12347  * Bits | Access | Reset | Description
12348  * :-------|:-------|:-----------|:------------------------------------
12349  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO
12350  *
12351  */
12352 /*
12353  * Field : addrlo
12354  *
12355  * MAC Address10 [31:0]
12356  *
12357  * This field contains the lower 32 bits of the 11th 6-byte MAC address. The
12358  * content of this field is undefined until loaded by the Application after the
12359  * initialization process.
12360  *
12361  * Field Access Macros:
12362  *
12363  */
12364 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field. */
12365 #define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_LSB 0
12366 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field. */
12367 #define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_MSB 31
12368 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field. */
12369 #define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_WIDTH 32
12370 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field value. */
12371 #define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_SET_MSK 0xffffffff
12372 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field value. */
12373 #define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_CLR_MSK 0x00000000
12374 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field. */
12375 #define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_RESET 0xffffffff
12376 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO field value from a register. */
12377 #define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
12378 /* Produces a ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field value suitable for setting the register. */
12379 #define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
12380 
12381 #ifndef __ASSEMBLY__
12382 /*
12383  * WARNING: The C register and register group struct declarations are provided for
12384  * convenience and illustrative purposes. They should, however, be used with
12385  * caution as the C language standard provides no guarantees about the alignment or
12386  * atomicity of device memory accesses. The recommended practice for writing
12387  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12388  * alt_write_word() functions.
12389  *
12390  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR10_LOW.
12391  */
12392 struct ALT_EMAC_GMAC_MAC_ADDR10_LOW_s
12393 {
12394  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO */
12395 };
12396 
12397 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR10_LOW. */
12398 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR10_LOW_s ALT_EMAC_GMAC_MAC_ADDR10_LOW_t;
12399 #endif /* __ASSEMBLY__ */
12400 
12401 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_LOW register. */
12402 #define ALT_EMAC_GMAC_MAC_ADDR10_LOW_RESET 0xffffffff
12403 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR10_LOW register from the beginning of the component. */
12404 #define ALT_EMAC_GMAC_MAC_ADDR10_LOW_OFST 0x94
12405 /* The address of the ALT_EMAC_GMAC_MAC_ADDR10_LOW register. */
12406 #define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR10_LOW_OFST))
12407 
12408 /*
12409  * Register : gmacgrp_mac_address11_high
12410  *
12411  * <b> Register 38 (MAC Address11 High Register) </b>
12412  *
12413  * The MAC Address11 High register holds the upper 16 bits of the 12th 6-byte MAC
12414  * address of the station.
12415  *
12416  * If the MAC address registers are configured to be double-synchronized to the
12417  * (G)MII clock domains, then the synchronization is triggered only when
12418  * Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC
12419  * Address11 Low Register are written. For proper synchronization updates, the
12420  * consecutive writes to this MAC Address11 Low Register should be performed after
12421  * at least four clock cycles in the destination clock domain.
12422  *
12423  * Register Layout
12424  *
12425  * Bits | Access | Reset | Description
12426  * :--------|:-------|:-------|:-----------------------------------------
12427  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI
12428  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR11_HIGH_RSVD_23_16
12429  * [24] | RW | 0x0 | Mask Byte Control
12430  * [25] | RW | 0x0 | Mask Byte Control
12431  * [26] | RW | 0x0 | Mask Byte Control
12432  * [27] | RW | 0x0 | Mask Byte Control
12433  * [28] | RW | 0x0 | Mask Byte Control
12434  * [29] | RW | 0x0 | Mask Byte Control
12435  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA
12436  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE
12437  *
12438  */
12439 /*
12440  * Field : addrhi
12441  *
12442  * MAC Address11 [47:32]
12443  *
12444  * This field contains the upper 16 bits (47:32) of the 12th 6-byte MAC address.
12445  *
12446  * Field Access Macros:
12447  *
12448  */
12449 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field. */
12450 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_LSB 0
12451 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field. */
12452 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_MSB 15
12453 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field. */
12454 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_WIDTH 16
12455 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field value. */
12456 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_SET_MSK 0x0000ffff
12457 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field value. */
12458 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_CLR_MSK 0xffff0000
12459 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field. */
12460 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_RESET 0xffff
12461 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI field value from a register. */
12462 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
12463 /* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field value suitable for setting the register. */
12464 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
12465 
12466 /*
12467  * Field : reserved_23_16
12468  *
12469  * Reserved
12470  *
12471  * Field Access Macros:
12472  *
12473  */
12474 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_RSVD_23_16 register field. */
12475 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_RSVD_23_16_LSB 16
12476 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_RSVD_23_16 register field. */
12477 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_RSVD_23_16_MSB 23
12478 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_RSVD_23_16 register field. */
12479 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_RSVD_23_16_WIDTH 8
12480 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_RSVD_23_16 register field value. */
12481 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
12482 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_RSVD_23_16 register field value. */
12483 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
12484 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_RSVD_23_16 register field. */
12485 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_RSVD_23_16_RESET 0x0
12486 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_RSVD_23_16 field value from a register. */
12487 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
12488 /* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_RSVD_23_16 register field value suitable for setting the register. */
12489 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
12490 
12491 /*
12492  * Field : Mask Byte Control - mbc_0
12493  *
12494  * This array of bits are mask control bits for comparison of each of the MAC
12495  * Address bytes. When masked, the MAC does not compare the corresponding byte of
12496  * received DA or SA with the contents of MAC Address11 high and low registers.
12497  * Each bit controls the masking of the bytes. You can filter a group of addresses
12498  * (known as group address filtering) by masking one or more bytes of the address.
12499  *
12500  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
12501  *
12502  * Field Enumeration Values:
12503  *
12504  * Enum | Value | Description
12505  * :----------------------------------------------|:------|:------------
12506  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_E_UNMSKED | 0x0 |
12507  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_E_MSKED | 0x1 |
12508  *
12509  * Field Access Macros:
12510  *
12511  */
12512 /*
12513  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0
12514  *
12515  */
12516 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_E_UNMSKED 0x0
12517 /*
12518  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0
12519  *
12520  */
12521 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_E_MSKED 0x1
12522 
12523 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field. */
12524 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_LSB 24
12525 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field. */
12526 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_MSB 24
12527 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field. */
12528 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_WIDTH 1
12529 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field value. */
12530 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_SET_MSK 0x01000000
12531 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field value. */
12532 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_CLR_MSK 0xfeffffff
12533 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field. */
12534 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_RESET 0x0
12535 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 field value from a register. */
12536 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
12537 /* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field value suitable for setting the register. */
12538 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
12539 
12540 /*
12541  * Field : Mask Byte Control - mbc_1
12542  *
12543  * This array of bits are mask control bits for comparison of each of the MAC
12544  * Address bytes. When masked, the MAC does not compare the corresponding byte of
12545  * received DA or SA with the contents of MAC Address11 high and low registers.
12546  * Each bit controls the masking of the bytes. You can filter a group of addresses
12547  * (known as group address filtering) by masking one or more bytes of the address.
12548  *
12549  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
12550  *
12551  * Field Enumeration Values:
12552  *
12553  * Enum | Value | Description
12554  * :----------------------------------------------|:------|:------------
12555  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_E_UNMSKED | 0x0 |
12556  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_E_MSKED | 0x1 |
12557  *
12558  * Field Access Macros:
12559  *
12560  */
12561 /*
12562  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1
12563  *
12564  */
12565 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_E_UNMSKED 0x0
12566 /*
12567  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1
12568  *
12569  */
12570 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_E_MSKED 0x1
12571 
12572 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field. */
12573 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_LSB 25
12574 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field. */
12575 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_MSB 25
12576 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field. */
12577 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_WIDTH 1
12578 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field value. */
12579 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_SET_MSK 0x02000000
12580 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field value. */
12581 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_CLR_MSK 0xfdffffff
12582 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field. */
12583 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_RESET 0x0
12584 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 field value from a register. */
12585 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
12586 /* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field value suitable for setting the register. */
12587 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
12588 
12589 /*
12590  * Field : Mask Byte Control - mbc_2
12591  *
12592  * This array of bits are mask control bits for comparison of each of the MAC
12593  * Address bytes. When masked, the MAC does not compare the corresponding byte of
12594  * received DA or SA with the contents of MAC Address11 high and low registers.
12595  * Each bit controls the masking of the bytes. You can filter a group of addresses
12596  * (known as group address filtering) by masking one or more bytes of the address.
12597  *
12598  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
12599  *
12600  * Field Enumeration Values:
12601  *
12602  * Enum | Value | Description
12603  * :----------------------------------------------|:------|:------------
12604  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_E_UNMSKED | 0x0 |
12605  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_E_MSKED | 0x1 |
12606  *
12607  * Field Access Macros:
12608  *
12609  */
12610 /*
12611  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2
12612  *
12613  */
12614 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_E_UNMSKED 0x0
12615 /*
12616  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2
12617  *
12618  */
12619 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_E_MSKED 0x1
12620 
12621 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field. */
12622 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_LSB 26
12623 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field. */
12624 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_MSB 26
12625 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field. */
12626 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_WIDTH 1
12627 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field value. */
12628 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_SET_MSK 0x04000000
12629 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field value. */
12630 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_CLR_MSK 0xfbffffff
12631 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field. */
12632 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_RESET 0x0
12633 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 field value from a register. */
12634 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
12635 /* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field value suitable for setting the register. */
12636 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
12637 
12638 /*
12639  * Field : Mask Byte Control - mbc_3
12640  *
12641  * This array of bits are mask control bits for comparison of each of the MAC
12642  * Address bytes. When masked, the MAC does not compare the corresponding byte of
12643  * received DA or SA with the contents of MAC Address11 high and low registers.
12644  * Each bit controls the masking of the bytes. You can filter a group of addresses
12645  * (known as group address filtering) by masking one or more bytes of the address.
12646  *
12647  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
12648  *
12649  * Field Enumeration Values:
12650  *
12651  * Enum | Value | Description
12652  * :----------------------------------------------|:------|:------------
12653  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_E_UNMSKED | 0x0 |
12654  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_E_MSKED | 0x1 |
12655  *
12656  * Field Access Macros:
12657  *
12658  */
12659 /*
12660  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3
12661  *
12662  */
12663 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_E_UNMSKED 0x0
12664 /*
12665  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3
12666  *
12667  */
12668 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_E_MSKED 0x1
12669 
12670 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field. */
12671 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_LSB 27
12672 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field. */
12673 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_MSB 27
12674 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field. */
12675 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_WIDTH 1
12676 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field value. */
12677 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_SET_MSK 0x08000000
12678 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field value. */
12679 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_CLR_MSK 0xf7ffffff
12680 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field. */
12681 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_RESET 0x0
12682 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 field value from a register. */
12683 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
12684 /* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field value suitable for setting the register. */
12685 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
12686 
12687 /*
12688  * Field : Mask Byte Control - mbc_4
12689  *
12690  * This array of bits are mask control bits for comparison of each of the MAC
12691  * Address bytes. When masked, the MAC does not compare the corresponding byte of
12692  * received DA or SA with the contents of MAC Address11 high and low registers.
12693  * Each bit controls the masking of the bytes. You can filter a group of addresses
12694  * (known as group address filtering) by masking one or more bytes of the address.
12695  *
12696  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
12697  *
12698  * Field Enumeration Values:
12699  *
12700  * Enum | Value | Description
12701  * :----------------------------------------------|:------|:------------
12702  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_E_UNMSKED | 0x0 |
12703  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_E_MSKED | 0x1 |
12704  *
12705  * Field Access Macros:
12706  *
12707  */
12708 /*
12709  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4
12710  *
12711  */
12712 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_E_UNMSKED 0x0
12713 /*
12714  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4
12715  *
12716  */
12717 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_E_MSKED 0x1
12718 
12719 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field. */
12720 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_LSB 28
12721 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field. */
12722 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_MSB 28
12723 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field. */
12724 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_WIDTH 1
12725 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field value. */
12726 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_SET_MSK 0x10000000
12727 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field value. */
12728 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_CLR_MSK 0xefffffff
12729 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field. */
12730 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_RESET 0x0
12731 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 field value from a register. */
12732 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
12733 /* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field value suitable for setting the register. */
12734 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
12735 
12736 /*
12737  * Field : Mask Byte Control - mbc_5
12738  *
12739  * This array of bits are mask control bits for comparison of each of the MAC
12740  * Address bytes. When masked, the MAC does not compare the corresponding byte of
12741  * received DA or SA with the contents of MAC Address11 high and low registers.
12742  * Each bit controls the masking of the bytes. You can filter a group of addresses
12743  * (known as group address filtering) by masking one or more bytes of the address.
12744  *
12745  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
12746  *
12747  * Field Enumeration Values:
12748  *
12749  * Enum | Value | Description
12750  * :----------------------------------------------|:------|:------------
12751  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_E_UNMSKED | 0x0 |
12752  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_E_MSKED | 0x1 |
12753  *
12754  * Field Access Macros:
12755  *
12756  */
12757 /*
12758  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5
12759  *
12760  */
12761 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_E_UNMSKED 0x0
12762 /*
12763  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5
12764  *
12765  */
12766 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_E_MSKED 0x1
12767 
12768 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field. */
12769 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_LSB 29
12770 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field. */
12771 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_MSB 29
12772 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field. */
12773 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_WIDTH 1
12774 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field value. */
12775 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_SET_MSK 0x20000000
12776 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field value. */
12777 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_CLR_MSK 0xdfffffff
12778 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field. */
12779 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_RESET 0x0
12780 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 field value from a register. */
12781 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
12782 /* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field value suitable for setting the register. */
12783 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
12784 
12785 /*
12786  * Field : sa
12787  *
12788  * Source Address
12789  *
12790  * When this bit is set, the MAC Address11[47:0] is used to compare with the SA
12791  * fields of the received frame. When this bit is reset, the MAC Address11[47:0] is
12792  * used to compare with the DA fields of the received frame.
12793  *
12794  * Field Enumeration Values:
12795  *
12796  * Enum | Value | Description
12797  * :----------------------------------------|:------|:------------
12798  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_E_DISD | 0x0 |
12799  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_E_END | 0x1 |
12800  *
12801  * Field Access Macros:
12802  *
12803  */
12804 /*
12805  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA
12806  *
12807  */
12808 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_E_DISD 0x0
12809 /*
12810  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA
12811  *
12812  */
12813 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_E_END 0x1
12814 
12815 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field. */
12816 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_LSB 30
12817 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field. */
12818 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_MSB 30
12819 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field. */
12820 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_WIDTH 1
12821 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field value. */
12822 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_SET_MSK 0x40000000
12823 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field value. */
12824 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_CLR_MSK 0xbfffffff
12825 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field. */
12826 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_RESET 0x0
12827 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA field value from a register. */
12828 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
12829 /* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field value suitable for setting the register. */
12830 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
12831 
12832 /*
12833  * Field : ae
12834  *
12835  * Address Enable
12836  *
12837  * When this bit is set, the address filter module uses the twelfth MAC address for
12838  * perfect filtering. When this bit is reset, the address filter module ignores the
12839  * address for filtering.
12840  *
12841  * Field Enumeration Values:
12842  *
12843  * Enum | Value | Description
12844  * :----------------------------------------|:------|:------------
12845  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_E_DISD | 0x0 |
12846  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_E_END | 0x1 |
12847  *
12848  * Field Access Macros:
12849  *
12850  */
12851 /*
12852  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE
12853  *
12854  */
12855 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_E_DISD 0x0
12856 /*
12857  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE
12858  *
12859  */
12860 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_E_END 0x1
12861 
12862 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field. */
12863 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_LSB 31
12864 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field. */
12865 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_MSB 31
12866 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field. */
12867 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_WIDTH 1
12868 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field value. */
12869 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_SET_MSK 0x80000000
12870 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field value. */
12871 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_CLR_MSK 0x7fffffff
12872 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field. */
12873 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_RESET 0x0
12874 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE field value from a register. */
12875 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
12876 /* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field value suitable for setting the register. */
12877 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
12878 
12879 #ifndef __ASSEMBLY__
12880 /*
12881  * WARNING: The C register and register group struct declarations are provided for
12882  * convenience and illustrative purposes. They should, however, be used with
12883  * caution as the C language standard provides no guarantees about the alignment or
12884  * atomicity of device memory accesses. The recommended practice for writing
12885  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12886  * alt_write_word() functions.
12887  *
12888  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR11_HIGH.
12889  */
12890 struct ALT_EMAC_GMAC_MAC_ADDR11_HIGH_s
12891 {
12892  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI */
12893  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR11_HIGH_RSVD_23_16 */
12894  uint32_t mbc_0 : 1; /* Mask Byte Control */
12895  uint32_t mbc_1 : 1; /* Mask Byte Control */
12896  uint32_t mbc_2 : 1; /* Mask Byte Control */
12897  uint32_t mbc_3 : 1; /* Mask Byte Control */
12898  uint32_t mbc_4 : 1; /* Mask Byte Control */
12899  uint32_t mbc_5 : 1; /* Mask Byte Control */
12900  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA */
12901  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE */
12902 };
12903 
12904 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR11_HIGH. */
12905 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR11_HIGH_s ALT_EMAC_GMAC_MAC_ADDR11_HIGH_t;
12906 #endif /* __ASSEMBLY__ */
12907 
12908 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH register. */
12909 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_RESET 0x0000ffff
12910 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH register from the beginning of the component. */
12911 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_OFST 0x98
12912 /* The address of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH register. */
12913 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR11_HIGH_OFST))
12914 
12915 /*
12916  * Register : gmacgrp_mac_address11_low
12917  *
12918  * <b> Register 39 (MAC Address1 Low Register) </b>
12919  *
12920  * The MAC Address11 Low register holds the lower 32 bits of the 12th 6-byte MAC
12921  * address of the station.
12922  *
12923  * Register Layout
12924  *
12925  * Bits | Access | Reset | Description
12926  * :-------|:-------|:-----------|:------------------------------------
12927  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO
12928  *
12929  */
12930 /*
12931  * Field : addrlo
12932  *
12933  * MAC Address11 [31:0]
12934  *
12935  * This field contains the lower 32 bits of the 12th 6-byte MAC address. The
12936  * content of this field is undefined until loaded by the Application after the
12937  * initialization process.
12938  *
12939  * Field Access Macros:
12940  *
12941  */
12942 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field. */
12943 #define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_LSB 0
12944 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field. */
12945 #define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_MSB 31
12946 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field. */
12947 #define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_WIDTH 32
12948 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field value. */
12949 #define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_SET_MSK 0xffffffff
12950 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field value. */
12951 #define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_CLR_MSK 0x00000000
12952 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field. */
12953 #define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_RESET 0xffffffff
12954 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO field value from a register. */
12955 #define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
12956 /* Produces a ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field value suitable for setting the register. */
12957 #define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
12958 
12959 #ifndef __ASSEMBLY__
12960 /*
12961  * WARNING: The C register and register group struct declarations are provided for
12962  * convenience and illustrative purposes. They should, however, be used with
12963  * caution as the C language standard provides no guarantees about the alignment or
12964  * atomicity of device memory accesses. The recommended practice for writing
12965  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12966  * alt_write_word() functions.
12967  *
12968  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR11_LOW.
12969  */
12970 struct ALT_EMAC_GMAC_MAC_ADDR11_LOW_s
12971 {
12972  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO */
12973 };
12974 
12975 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR11_LOW. */
12976 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR11_LOW_s ALT_EMAC_GMAC_MAC_ADDR11_LOW_t;
12977 #endif /* __ASSEMBLY__ */
12978 
12979 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_LOW register. */
12980 #define ALT_EMAC_GMAC_MAC_ADDR11_LOW_RESET 0xffffffff
12981 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR11_LOW register from the beginning of the component. */
12982 #define ALT_EMAC_GMAC_MAC_ADDR11_LOW_OFST 0x9c
12983 /* The address of the ALT_EMAC_GMAC_MAC_ADDR11_LOW register. */
12984 #define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR11_LOW_OFST))
12985 
12986 /*
12987  * Register : gmacgrp_mac_address12_high
12988  *
12989  * <b> Register 40 (MAC Address12 High Register ) </b>
12990  *
12991  * The MAC Address12 High register holds the upper 16 bits of the 13th 6-byte MAC
12992  * address of the station.
12993  *
12994  * If the MAC address registers are configured to be double-synchronized to the
12995  * (G)MII clock domains, then the synchronization is triggered only when
12996  * Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC
12997  * Address13 Low Register are written. For proper synchronization updates, the
12998  * consecutive writes to this MAC Address12 Low Register should be performed after
12999  * at least four clock cycles in the destination clock domain.
13000  *
13001  * Register Layout
13002  *
13003  * Bits | Access | Reset | Description
13004  * :--------|:-------|:-------|:-----------------------------------------
13005  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI
13006  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR12_HIGH_RSVD_23_16
13007  * [24] | RW | 0x0 | Mask Byte Control
13008  * [25] | RW | 0x0 | Mask Byte Control
13009  * [26] | RW | 0x0 | Mask Byte Control
13010  * [27] | RW | 0x0 | Mask Byte Control
13011  * [28] | RW | 0x0 | Mask Byte Control
13012  * [29] | RW | 0x0 | Mask Byte Control
13013  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA
13014  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE
13015  *
13016  */
13017 /*
13018  * Field : addrhi
13019  *
13020  * MAC Address12 [47:32]
13021  *
13022  * This field contains the upper 16 bits (47:32) of the 13th 6-byte MAC address.
13023  *
13024  * Field Access Macros:
13025  *
13026  */
13027 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field. */
13028 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_LSB 0
13029 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field. */
13030 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_MSB 15
13031 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field. */
13032 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_WIDTH 16
13033 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field value. */
13034 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_SET_MSK 0x0000ffff
13035 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field value. */
13036 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_CLR_MSK 0xffff0000
13037 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field. */
13038 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_RESET 0xffff
13039 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI field value from a register. */
13040 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
13041 /* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field value suitable for setting the register. */
13042 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
13043 
13044 /*
13045  * Field : reserved_23_16
13046  *
13047  * Reserved
13048  *
13049  * Field Access Macros:
13050  *
13051  */
13052 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_RSVD_23_16 register field. */
13053 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_RSVD_23_16_LSB 16
13054 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_RSVD_23_16 register field. */
13055 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_RSVD_23_16_MSB 23
13056 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_RSVD_23_16 register field. */
13057 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_RSVD_23_16_WIDTH 8
13058 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_RSVD_23_16 register field value. */
13059 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
13060 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_RSVD_23_16 register field value. */
13061 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
13062 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_RSVD_23_16 register field. */
13063 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_RSVD_23_16_RESET 0x0
13064 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_RSVD_23_16 field value from a register. */
13065 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
13066 /* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_RSVD_23_16 register field value suitable for setting the register. */
13067 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
13068 
13069 /*
13070  * Field : Mask Byte Control - mbc_0
13071  *
13072  * This array of bits are mask control bits for comparison of each of the MAC
13073  * Address bytes. When masked, the MAC does not compare the corresponding byte of
13074  * received DA or SA with the contents of MAC Address12 high and low registers.
13075  * Each bit controls the masking of the bytes. You can filter a group of addresses
13076  * (known as group address filtering) by masking one or more bytes of the address.
13077  *
13078  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
13079  *
13080  * Field Enumeration Values:
13081  *
13082  * Enum | Value | Description
13083  * :----------------------------------------------|:------|:------------
13084  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_E_UNMSKED | 0x0 |
13085  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_E_MSKED | 0x1 |
13086  *
13087  * Field Access Macros:
13088  *
13089  */
13090 /*
13091  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0
13092  *
13093  */
13094 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_E_UNMSKED 0x0
13095 /*
13096  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0
13097  *
13098  */
13099 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_E_MSKED 0x1
13100 
13101 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field. */
13102 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_LSB 24
13103 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field. */
13104 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_MSB 24
13105 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field. */
13106 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_WIDTH 1
13107 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field value. */
13108 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_SET_MSK 0x01000000
13109 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field value. */
13110 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_CLR_MSK 0xfeffffff
13111 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field. */
13112 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_RESET 0x0
13113 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 field value from a register. */
13114 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
13115 /* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field value suitable for setting the register. */
13116 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
13117 
13118 /*
13119  * Field : Mask Byte Control - mbc_1
13120  *
13121  * This array of bits are mask control bits for comparison of each of the MAC
13122  * Address bytes. When masked, the MAC does not compare the corresponding byte of
13123  * received DA or SA with the contents of MAC Address12 high and low registers.
13124  * Each bit controls the masking of the bytes. You can filter a group of addresses
13125  * (known as group address filtering) by masking one or more bytes of the address.
13126  *
13127  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
13128  *
13129  * Field Enumeration Values:
13130  *
13131  * Enum | Value | Description
13132  * :----------------------------------------------|:------|:------------
13133  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_E_UNMSKED | 0x0 |
13134  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_E_MSKED | 0x1 |
13135  *
13136  * Field Access Macros:
13137  *
13138  */
13139 /*
13140  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1
13141  *
13142  */
13143 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_E_UNMSKED 0x0
13144 /*
13145  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1
13146  *
13147  */
13148 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_E_MSKED 0x1
13149 
13150 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field. */
13151 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_LSB 25
13152 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field. */
13153 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_MSB 25
13154 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field. */
13155 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_WIDTH 1
13156 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field value. */
13157 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_SET_MSK 0x02000000
13158 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field value. */
13159 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_CLR_MSK 0xfdffffff
13160 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field. */
13161 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_RESET 0x0
13162 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 field value from a register. */
13163 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
13164 /* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field value suitable for setting the register. */
13165 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
13166 
13167 /*
13168  * Field : Mask Byte Control - mbc_2
13169  *
13170  * This array of bits are mask control bits for comparison of each of the MAC
13171  * Address bytes. When masked, the MAC does not compare the corresponding byte of
13172  * received DA or SA with the contents of MAC Address12 high and low registers.
13173  * Each bit controls the masking of the bytes. You can filter a group of addresses
13174  * (known as group address filtering) by masking one or more bytes of the address.
13175  *
13176  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
13177  *
13178  * Field Enumeration Values:
13179  *
13180  * Enum | Value | Description
13181  * :----------------------------------------------|:------|:------------
13182  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_E_UNMSKED | 0x0 |
13183  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_E_MSKED | 0x1 |
13184  *
13185  * Field Access Macros:
13186  *
13187  */
13188 /*
13189  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2
13190  *
13191  */
13192 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_E_UNMSKED 0x0
13193 /*
13194  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2
13195  *
13196  */
13197 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_E_MSKED 0x1
13198 
13199 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field. */
13200 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_LSB 26
13201 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field. */
13202 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_MSB 26
13203 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field. */
13204 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_WIDTH 1
13205 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field value. */
13206 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_SET_MSK 0x04000000
13207 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field value. */
13208 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_CLR_MSK 0xfbffffff
13209 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field. */
13210 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_RESET 0x0
13211 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 field value from a register. */
13212 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
13213 /* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field value suitable for setting the register. */
13214 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
13215 
13216 /*
13217  * Field : Mask Byte Control - mbc_3
13218  *
13219  * This array of bits are mask control bits for comparison of each of the MAC
13220  * Address bytes. When masked, the MAC does not compare the corresponding byte of
13221  * received DA or SA with the contents of MAC Address12 high and low registers.
13222  * Each bit controls the masking of the bytes. You can filter a group of addresses
13223  * (known as group address filtering) by masking one or more bytes of the address.
13224  *
13225  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
13226  *
13227  * Field Enumeration Values:
13228  *
13229  * Enum | Value | Description
13230  * :----------------------------------------------|:------|:------------
13231  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_E_UNMSKED | 0x0 |
13232  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_E_MSKED | 0x1 |
13233  *
13234  * Field Access Macros:
13235  *
13236  */
13237 /*
13238  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3
13239  *
13240  */
13241 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_E_UNMSKED 0x0
13242 /*
13243  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3
13244  *
13245  */
13246 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_E_MSKED 0x1
13247 
13248 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field. */
13249 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_LSB 27
13250 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field. */
13251 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_MSB 27
13252 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field. */
13253 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_WIDTH 1
13254 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field value. */
13255 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_SET_MSK 0x08000000
13256 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field value. */
13257 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_CLR_MSK 0xf7ffffff
13258 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field. */
13259 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_RESET 0x0
13260 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 field value from a register. */
13261 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
13262 /* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field value suitable for setting the register. */
13263 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
13264 
13265 /*
13266  * Field : Mask Byte Control - mbc_4
13267  *
13268  * This array of bits are mask control bits for comparison of each of the MAC
13269  * Address bytes. When masked, the MAC does not compare the corresponding byte of
13270  * received DA or SA with the contents of MAC Address12 high and low registers.
13271  * Each bit controls the masking of the bytes. You can filter a group of addresses
13272  * (known as group address filtering) by masking one or more bytes of the address.
13273  *
13274  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
13275  *
13276  * Field Enumeration Values:
13277  *
13278  * Enum | Value | Description
13279  * :----------------------------------------------|:------|:------------
13280  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_E_UNMSKED | 0x0 |
13281  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_E_MSKED | 0x1 |
13282  *
13283  * Field Access Macros:
13284  *
13285  */
13286 /*
13287  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4
13288  *
13289  */
13290 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_E_UNMSKED 0x0
13291 /*
13292  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4
13293  *
13294  */
13295 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_E_MSKED 0x1
13296 
13297 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field. */
13298 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_LSB 28
13299 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field. */
13300 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_MSB 28
13301 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field. */
13302 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_WIDTH 1
13303 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field value. */
13304 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_SET_MSK 0x10000000
13305 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field value. */
13306 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_CLR_MSK 0xefffffff
13307 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field. */
13308 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_RESET 0x0
13309 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 field value from a register. */
13310 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
13311 /* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field value suitable for setting the register. */
13312 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
13313 
13314 /*
13315  * Field : Mask Byte Control - mbc_5
13316  *
13317  * This array of bits are mask control bits for comparison of each of the MAC
13318  * Address bytes. When masked, the MAC does not compare the corresponding byte of
13319  * received DA or SA with the contents of MAC Address12 high and low registers.
13320  * Each bit controls the masking of the bytes. You can filter a group of addresses
13321  * (known as group address filtering) by masking one or more bytes of the address.
13322  *
13323  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
13324  *
13325  * Field Enumeration Values:
13326  *
13327  * Enum | Value | Description
13328  * :----------------------------------------------|:------|:------------
13329  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_E_UNMSKED | 0x0 |
13330  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_E_MSKED | 0x1 |
13331  *
13332  * Field Access Macros:
13333  *
13334  */
13335 /*
13336  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5
13337  *
13338  */
13339 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_E_UNMSKED 0x0
13340 /*
13341  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5
13342  *
13343  */
13344 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_E_MSKED 0x1
13345 
13346 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field. */
13347 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_LSB 29
13348 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field. */
13349 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_MSB 29
13350 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field. */
13351 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_WIDTH 1
13352 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field value. */
13353 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_SET_MSK 0x20000000
13354 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field value. */
13355 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_CLR_MSK 0xdfffffff
13356 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field. */
13357 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_RESET 0x0
13358 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 field value from a register. */
13359 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
13360 /* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field value suitable for setting the register. */
13361 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
13362 
13363 /*
13364  * Field : sa
13365  *
13366  * Source Address
13367  *
13368  * When this bit is set, the MAC Address12[47:0] is used to compare with the SA
13369  * fields of the received frame. When this bit is reset, the MAC Address12[47:0] is
13370  * used to compare with the DA fields of the received frame.
13371  *
13372  * Field Enumeration Values:
13373  *
13374  * Enum | Value | Description
13375  * :----------------------------------------|:------|:------------
13376  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_E_DISD | 0x0 |
13377  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_E_END | 0x1 |
13378  *
13379  * Field Access Macros:
13380  *
13381  */
13382 /*
13383  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA
13384  *
13385  */
13386 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_E_DISD 0x0
13387 /*
13388  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA
13389  *
13390  */
13391 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_E_END 0x1
13392 
13393 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field. */
13394 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_LSB 30
13395 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field. */
13396 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_MSB 30
13397 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field. */
13398 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_WIDTH 1
13399 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field value. */
13400 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_SET_MSK 0x40000000
13401 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field value. */
13402 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_CLR_MSK 0xbfffffff
13403 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field. */
13404 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_RESET 0x0
13405 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA field value from a register. */
13406 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
13407 /* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field value suitable for setting the register. */
13408 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
13409 
13410 /*
13411  * Field : ae
13412  *
13413  * Address Enable
13414  *
13415  * When this bit is set, the address filter module uses the 13th MAC address for
13416  * perfect filtering. When this bit is reset, the address filter module ignores the
13417  * address for filtering.
13418  *
13419  * Field Enumeration Values:
13420  *
13421  * Enum | Value | Description
13422  * :----------------------------------------|:------|:------------
13423  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_E_DISD | 0x0 |
13424  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_E_END | 0x1 |
13425  *
13426  * Field Access Macros:
13427  *
13428  */
13429 /*
13430  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE
13431  *
13432  */
13433 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_E_DISD 0x0
13434 /*
13435  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE
13436  *
13437  */
13438 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_E_END 0x1
13439 
13440 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field. */
13441 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_LSB 31
13442 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field. */
13443 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_MSB 31
13444 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field. */
13445 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_WIDTH 1
13446 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field value. */
13447 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_SET_MSK 0x80000000
13448 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field value. */
13449 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_CLR_MSK 0x7fffffff
13450 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field. */
13451 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_RESET 0x0
13452 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE field value from a register. */
13453 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
13454 /* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field value suitable for setting the register. */
13455 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
13456 
13457 #ifndef __ASSEMBLY__
13458 /*
13459  * WARNING: The C register and register group struct declarations are provided for
13460  * convenience and illustrative purposes. They should, however, be used with
13461  * caution as the C language standard provides no guarantees about the alignment or
13462  * atomicity of device memory accesses. The recommended practice for writing
13463  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13464  * alt_write_word() functions.
13465  *
13466  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR12_HIGH.
13467  */
13468 struct ALT_EMAC_GMAC_MAC_ADDR12_HIGH_s
13469 {
13470  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI */
13471  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR12_HIGH_RSVD_23_16 */
13472  uint32_t mbc_0 : 1; /* Mask Byte Control */
13473  uint32_t mbc_1 : 1; /* Mask Byte Control */
13474  uint32_t mbc_2 : 1; /* Mask Byte Control */
13475  uint32_t mbc_3 : 1; /* Mask Byte Control */
13476  uint32_t mbc_4 : 1; /* Mask Byte Control */
13477  uint32_t mbc_5 : 1; /* Mask Byte Control */
13478  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA */
13479  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE */
13480 };
13481 
13482 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR12_HIGH. */
13483 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR12_HIGH_s ALT_EMAC_GMAC_MAC_ADDR12_HIGH_t;
13484 #endif /* __ASSEMBLY__ */
13485 
13486 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH register. */
13487 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_RESET 0x0000ffff
13488 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH register from the beginning of the component. */
13489 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_OFST 0xa0
13490 /* The address of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH register. */
13491 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR12_HIGH_OFST))
13492 
13493 /*
13494  * Register : gmacgrp_mac_address12_low
13495  *
13496  * <b> Register 41 (MAC Address12 Low Register) </b>
13497  *
13498  * The MAC Address12 Low register holds the lower 32 bits of the 13th 6-byte MAC
13499  * address of the station.
13500  *
13501  * Register Layout
13502  *
13503  * Bits | Access | Reset | Description
13504  * :-------|:-------|:-----------|:------------------------------------
13505  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO
13506  *
13507  */
13508 /*
13509  * Field : addrlo
13510  *
13511  * MAC Address12 [31:0]
13512  *
13513  * This field contains the lower 32 bits of the 13th 6-byte MAC address. The
13514  * content of this field is undefined until loaded by the Application after the
13515  * initialization process.
13516  *
13517  * Field Access Macros:
13518  *
13519  */
13520 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field. */
13521 #define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_LSB 0
13522 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field. */
13523 #define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_MSB 31
13524 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field. */
13525 #define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_WIDTH 32
13526 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field value. */
13527 #define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_SET_MSK 0xffffffff
13528 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field value. */
13529 #define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_CLR_MSK 0x00000000
13530 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field. */
13531 #define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_RESET 0xffffffff
13532 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO field value from a register. */
13533 #define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
13534 /* Produces a ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field value suitable for setting the register. */
13535 #define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
13536 
13537 #ifndef __ASSEMBLY__
13538 /*
13539  * WARNING: The C register and register group struct declarations are provided for
13540  * convenience and illustrative purposes. They should, however, be used with
13541  * caution as the C language standard provides no guarantees about the alignment or
13542  * atomicity of device memory accesses. The recommended practice for writing
13543  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13544  * alt_write_word() functions.
13545  *
13546  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR12_LOW.
13547  */
13548 struct ALT_EMAC_GMAC_MAC_ADDR12_LOW_s
13549 {
13550  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO */
13551 };
13552 
13553 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR12_LOW. */
13554 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR12_LOW_s ALT_EMAC_GMAC_MAC_ADDR12_LOW_t;
13555 #endif /* __ASSEMBLY__ */
13556 
13557 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_LOW register. */
13558 #define ALT_EMAC_GMAC_MAC_ADDR12_LOW_RESET 0xffffffff
13559 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR12_LOW register from the beginning of the component. */
13560 #define ALT_EMAC_GMAC_MAC_ADDR12_LOW_OFST 0xa4
13561 /* The address of the ALT_EMAC_GMAC_MAC_ADDR12_LOW register. */
13562 #define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR12_LOW_OFST))
13563 
13564 /*
13565  * Register : gmacgrp_mac_address13_high
13566  *
13567  * <b> Register 42 (MAC Address13 High Register) </b>
13568  *
13569  * The MAC Address13 High register holds the upper 16 bits of the 14th 6-byte MAC
13570  * address of the station.
13571  *
13572  * If the MAC address registers are configured to be double-synchronized to the
13573  * (G)MII clock domains, then the synchronization is triggered only when
13574  * Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC
13575  * Address13 Low Register are written. For proper synchronization updates, the
13576  * consecutive writes to this MAC Address13 Low Register should be performed after
13577  * at least four clock cycles in the destination clock domain.
13578  *
13579  * Register Layout
13580  *
13581  * Bits | Access | Reset | Description
13582  * :--------|:-------|:-------|:-----------------------------------------
13583  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI
13584  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR13_HIGH_RSVD_23_16
13585  * [24] | RW | 0x0 | Mask Byte Control
13586  * [25] | RW | 0x0 | Mask Byte Control
13587  * [26] | RW | 0x0 | Mask Byte Control
13588  * [27] | RW | 0x0 | Mask Byte Control
13589  * [28] | RW | 0x0 | Mask Byte Control
13590  * [29] | RW | 0x0 | Mask Byte Control
13591  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA
13592  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE
13593  *
13594  */
13595 /*
13596  * Field : addrhi
13597  *
13598  * MAC Address13 [47:32]
13599  *
13600  * This field contains the upper 16 bits (47:32) of the 14th 6-byte MAC address.
13601  *
13602  * Field Access Macros:
13603  *
13604  */
13605 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field. */
13606 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_LSB 0
13607 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field. */
13608 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_MSB 15
13609 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field. */
13610 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_WIDTH 16
13611 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field value. */
13612 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_SET_MSK 0x0000ffff
13613 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field value. */
13614 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_CLR_MSK 0xffff0000
13615 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field. */
13616 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_RESET 0xffff
13617 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI field value from a register. */
13618 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
13619 /* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field value suitable for setting the register. */
13620 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
13621 
13622 /*
13623  * Field : reserved_23_16
13624  *
13625  * Reserved
13626  *
13627  * Field Access Macros:
13628  *
13629  */
13630 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_RSVD_23_16 register field. */
13631 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_RSVD_23_16_LSB 16
13632 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_RSVD_23_16 register field. */
13633 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_RSVD_23_16_MSB 23
13634 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_RSVD_23_16 register field. */
13635 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_RSVD_23_16_WIDTH 8
13636 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_RSVD_23_16 register field value. */
13637 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
13638 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_RSVD_23_16 register field value. */
13639 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
13640 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_RSVD_23_16 register field. */
13641 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_RSVD_23_16_RESET 0x0
13642 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_RSVD_23_16 field value from a register. */
13643 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
13644 /* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_RSVD_23_16 register field value suitable for setting the register. */
13645 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
13646 
13647 /*
13648  * Field : Mask Byte Control - mbc_0
13649  *
13650  * This array of bits are mask control bits for comparison of each of the MAC
13651  * Address bytes. When masked, the MAC does not compare the corresponding byte of
13652  * received DA or SA with the contents of MAC Address13 high and low registers.
13653  * Each bit controls the masking of the bytes. You can filter a group of addresses
13654  * (known as group address filtering) by masking one or more bytes of the address.
13655  *
13656  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
13657  *
13658  * Field Enumeration Values:
13659  *
13660  * Enum | Value | Description
13661  * :----------------------------------------------|:------|:------------
13662  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_E_UNMSKED | 0x0 |
13663  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_E_MSKED | 0x1 |
13664  *
13665  * Field Access Macros:
13666  *
13667  */
13668 /*
13669  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0
13670  *
13671  */
13672 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_E_UNMSKED 0x0
13673 /*
13674  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0
13675  *
13676  */
13677 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_E_MSKED 0x1
13678 
13679 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field. */
13680 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_LSB 24
13681 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field. */
13682 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_MSB 24
13683 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field. */
13684 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_WIDTH 1
13685 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field value. */
13686 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_SET_MSK 0x01000000
13687 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field value. */
13688 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_CLR_MSK 0xfeffffff
13689 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field. */
13690 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_RESET 0x0
13691 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 field value from a register. */
13692 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
13693 /* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field value suitable for setting the register. */
13694 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
13695 
13696 /*
13697  * Field : Mask Byte Control - mbc_1
13698  *
13699  * This array of bits are mask control bits for comparison of each of the MAC
13700  * Address bytes. When masked, the MAC does not compare the corresponding byte of
13701  * received DA or SA with the contents of MAC Address13 high and low registers.
13702  * Each bit controls the masking of the bytes. You can filter a group of addresses
13703  * (known as group address filtering) by masking one or more bytes of the address.
13704  *
13705  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
13706  *
13707  * Field Enumeration Values:
13708  *
13709  * Enum | Value | Description
13710  * :----------------------------------------------|:------|:------------
13711  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_E_UNMSKED | 0x0 |
13712  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_E_MSKED | 0x1 |
13713  *
13714  * Field Access Macros:
13715  *
13716  */
13717 /*
13718  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1
13719  *
13720  */
13721 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_E_UNMSKED 0x0
13722 /*
13723  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1
13724  *
13725  */
13726 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_E_MSKED 0x1
13727 
13728 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field. */
13729 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_LSB 25
13730 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field. */
13731 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_MSB 25
13732 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field. */
13733 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_WIDTH 1
13734 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field value. */
13735 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_SET_MSK 0x02000000
13736 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field value. */
13737 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_CLR_MSK 0xfdffffff
13738 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field. */
13739 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_RESET 0x0
13740 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 field value from a register. */
13741 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
13742 /* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field value suitable for setting the register. */
13743 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
13744 
13745 /*
13746  * Field : Mask Byte Control - mbc_2
13747  *
13748  * This array of bits are mask control bits for comparison of each of the MAC
13749  * Address bytes. When masked, the MAC does not compare the corresponding byte of
13750  * received DA or SA with the contents of MAC Address13 high and low registers.
13751  * Each bit controls the masking of the bytes. You can filter a group of addresses
13752  * (known as group address filtering) by masking one or more bytes of the address.
13753  *
13754  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
13755  *
13756  * Field Enumeration Values:
13757  *
13758  * Enum | Value | Description
13759  * :----------------------------------------------|:------|:------------
13760  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_E_UNMSKED | 0x0 |
13761  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_E_MSKED | 0x1 |
13762  *
13763  * Field Access Macros:
13764  *
13765  */
13766 /*
13767  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2
13768  *
13769  */
13770 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_E_UNMSKED 0x0
13771 /*
13772  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2
13773  *
13774  */
13775 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_E_MSKED 0x1
13776 
13777 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field. */
13778 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_LSB 26
13779 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field. */
13780 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_MSB 26
13781 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field. */
13782 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_WIDTH 1
13783 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field value. */
13784 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_SET_MSK 0x04000000
13785 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field value. */
13786 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_CLR_MSK 0xfbffffff
13787 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field. */
13788 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_RESET 0x0
13789 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 field value from a register. */
13790 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
13791 /* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field value suitable for setting the register. */
13792 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
13793 
13794 /*
13795  * Field : Mask Byte Control - mbc_3
13796  *
13797  * This array of bits are mask control bits for comparison of each of the MAC
13798  * Address bytes. When masked, the MAC does not compare the corresponding byte of
13799  * received DA or SA with the contents of MAC Address13 high and low registers.
13800  * Each bit controls the masking of the bytes. You can filter a group of addresses
13801  * (known as group address filtering) by masking one or more bytes of the address.
13802  *
13803  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
13804  *
13805  * Field Enumeration Values:
13806  *
13807  * Enum | Value | Description
13808  * :----------------------------------------------|:------|:------------
13809  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_E_UNMSKED | 0x0 |
13810  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_E_MSKED | 0x1 |
13811  *
13812  * Field Access Macros:
13813  *
13814  */
13815 /*
13816  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3
13817  *
13818  */
13819 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_E_UNMSKED 0x0
13820 /*
13821  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3
13822  *
13823  */
13824 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_E_MSKED 0x1
13825 
13826 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field. */
13827 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_LSB 27
13828 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field. */
13829 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_MSB 27
13830 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field. */
13831 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_WIDTH 1
13832 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field value. */
13833 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_SET_MSK 0x08000000
13834 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field value. */
13835 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_CLR_MSK 0xf7ffffff
13836 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field. */
13837 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_RESET 0x0
13838 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 field value from a register. */
13839 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
13840 /* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field value suitable for setting the register. */
13841 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
13842 
13843 /*
13844  * Field : Mask Byte Control - mbc_4
13845  *
13846  * This array of bits are mask control bits for comparison of each of the MAC
13847  * Address bytes. When masked, the MAC does not compare the corresponding byte of
13848  * received DA or SA with the contents of MAC Address13 high and low registers.
13849  * Each bit controls the masking of the bytes. You can filter a group of addresses
13850  * (known as group address filtering) by masking one or more bytes of the address.
13851  *
13852  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
13853  *
13854  * Field Enumeration Values:
13855  *
13856  * Enum | Value | Description
13857  * :----------------------------------------------|:------|:------------
13858  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_E_UNMSKED | 0x0 |
13859  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_E_MSKED | 0x1 |
13860  *
13861  * Field Access Macros:
13862  *
13863  */
13864 /*
13865  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4
13866  *
13867  */
13868 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_E_UNMSKED 0x0
13869 /*
13870  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4
13871  *
13872  */
13873 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_E_MSKED 0x1
13874 
13875 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field. */
13876 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_LSB 28
13877 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field. */
13878 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_MSB 28
13879 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field. */
13880 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_WIDTH 1
13881 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field value. */
13882 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_SET_MSK 0x10000000
13883 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field value. */
13884 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_CLR_MSK 0xefffffff
13885 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field. */
13886 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_RESET 0x0
13887 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 field value from a register. */
13888 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
13889 /* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field value suitable for setting the register. */
13890 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
13891 
13892 /*
13893  * Field : Mask Byte Control - mbc_5
13894  *
13895  * This array of bits are mask control bits for comparison of each of the MAC
13896  * Address bytes. When masked, the MAC does not compare the corresponding byte of
13897  * received DA or SA with the contents of MAC Address13 high and low registers.
13898  * Each bit controls the masking of the bytes. You can filter a group of addresses
13899  * (known as group address filtering) by masking one or more bytes of the address.
13900  *
13901  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
13902  *
13903  * Field Enumeration Values:
13904  *
13905  * Enum | Value | Description
13906  * :----------------------------------------------|:------|:------------
13907  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_E_UNMSKED | 0x0 |
13908  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_E_MSKED | 0x1 |
13909  *
13910  * Field Access Macros:
13911  *
13912  */
13913 /*
13914  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5
13915  *
13916  */
13917 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_E_UNMSKED 0x0
13918 /*
13919  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5
13920  *
13921  */
13922 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_E_MSKED 0x1
13923 
13924 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field. */
13925 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_LSB 29
13926 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field. */
13927 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_MSB 29
13928 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field. */
13929 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_WIDTH 1
13930 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field value. */
13931 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_SET_MSK 0x20000000
13932 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field value. */
13933 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_CLR_MSK 0xdfffffff
13934 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field. */
13935 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_RESET 0x0
13936 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 field value from a register. */
13937 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
13938 /* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field value suitable for setting the register. */
13939 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
13940 
13941 /*
13942  * Field : sa
13943  *
13944  * Source Address
13945  *
13946  * When this bit is set, the MAC Address13[47:0] is used to compare with the SA
13947  * fields of the received frame. When this bit is reset, the MAC Address13[47:0] is
13948  * used to compare with the DA fields of the received frame.
13949  *
13950  * Field Enumeration Values:
13951  *
13952  * Enum | Value | Description
13953  * :----------------------------------------|:------|:------------
13954  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_E_DISD | 0x0 |
13955  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_E_END | 0x1 |
13956  *
13957  * Field Access Macros:
13958  *
13959  */
13960 /*
13961  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA
13962  *
13963  */
13964 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_E_DISD 0x0
13965 /*
13966  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA
13967  *
13968  */
13969 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_E_END 0x1
13970 
13971 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field. */
13972 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_LSB 30
13973 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field. */
13974 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_MSB 30
13975 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field. */
13976 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_WIDTH 1
13977 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field value. */
13978 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_SET_MSK 0x40000000
13979 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field value. */
13980 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_CLR_MSK 0xbfffffff
13981 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field. */
13982 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_RESET 0x0
13983 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA field value from a register. */
13984 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
13985 /* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field value suitable for setting the register. */
13986 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
13987 
13988 /*
13989  * Field : ae
13990  *
13991  * Address Enable
13992  *
13993  * When this bit is set, the address filter module uses the 14th MAC address for
13994  * perfect filtering. When this bit is reset, the address filter module ignores the
13995  * address for filtering.
13996  *
13997  * Field Enumeration Values:
13998  *
13999  * Enum | Value | Description
14000  * :----------------------------------------|:------|:------------
14001  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_E_DISD | 0x0 |
14002  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_E_END | 0x1 |
14003  *
14004  * Field Access Macros:
14005  *
14006  */
14007 /*
14008  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE
14009  *
14010  */
14011 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_E_DISD 0x0
14012 /*
14013  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE
14014  *
14015  */
14016 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_E_END 0x1
14017 
14018 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field. */
14019 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_LSB 31
14020 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field. */
14021 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_MSB 31
14022 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field. */
14023 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_WIDTH 1
14024 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field value. */
14025 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_SET_MSK 0x80000000
14026 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field value. */
14027 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_CLR_MSK 0x7fffffff
14028 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field. */
14029 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_RESET 0x0
14030 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE field value from a register. */
14031 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
14032 /* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field value suitable for setting the register. */
14033 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
14034 
14035 #ifndef __ASSEMBLY__
14036 /*
14037  * WARNING: The C register and register group struct declarations are provided for
14038  * convenience and illustrative purposes. They should, however, be used with
14039  * caution as the C language standard provides no guarantees about the alignment or
14040  * atomicity of device memory accesses. The recommended practice for writing
14041  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14042  * alt_write_word() functions.
14043  *
14044  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR13_HIGH.
14045  */
14046 struct ALT_EMAC_GMAC_MAC_ADDR13_HIGH_s
14047 {
14048  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI */
14049  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR13_HIGH_RSVD_23_16 */
14050  uint32_t mbc_0 : 1; /* Mask Byte Control */
14051  uint32_t mbc_1 : 1; /* Mask Byte Control */
14052  uint32_t mbc_2 : 1; /* Mask Byte Control */
14053  uint32_t mbc_3 : 1; /* Mask Byte Control */
14054  uint32_t mbc_4 : 1; /* Mask Byte Control */
14055  uint32_t mbc_5 : 1; /* Mask Byte Control */
14056  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA */
14057  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE */
14058 };
14059 
14060 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR13_HIGH. */
14061 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR13_HIGH_s ALT_EMAC_GMAC_MAC_ADDR13_HIGH_t;
14062 #endif /* __ASSEMBLY__ */
14063 
14064 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH register. */
14065 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_RESET 0x0000ffff
14066 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH register from the beginning of the component. */
14067 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_OFST 0xa8
14068 /* The address of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH register. */
14069 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR13_HIGH_OFST))
14070 
14071 /*
14072  * Register : gmacgrp_mac_address13_low
14073  *
14074  * <b> Register 43 (MAC Address13 Low Register) </b>
14075  *
14076  * The MAC Address13 Low register holds the lower 32 bits of the 14th 6-byte MAC
14077  * address of the station.
14078  *
14079  * Register Layout
14080  *
14081  * Bits | Access | Reset | Description
14082  * :-------|:-------|:-----------|:------------------------------------
14083  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO
14084  *
14085  */
14086 /*
14087  * Field : addrlo
14088  *
14089  * MAC Address13 [31:0]
14090  *
14091  * This field contains the lower 32 bits of the 14th 6-byte MAC address. The
14092  * content of this field is undefined until loaded by the Application after the
14093  * initialization process.
14094  *
14095  * Field Access Macros:
14096  *
14097  */
14098 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field. */
14099 #define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_LSB 0
14100 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field. */
14101 #define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_MSB 31
14102 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field. */
14103 #define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_WIDTH 32
14104 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field value. */
14105 #define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_SET_MSK 0xffffffff
14106 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field value. */
14107 #define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_CLR_MSK 0x00000000
14108 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field. */
14109 #define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_RESET 0xffffffff
14110 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO field value from a register. */
14111 #define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
14112 /* Produces a ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field value suitable for setting the register. */
14113 #define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
14114 
14115 #ifndef __ASSEMBLY__
14116 /*
14117  * WARNING: The C register and register group struct declarations are provided for
14118  * convenience and illustrative purposes. They should, however, be used with
14119  * caution as the C language standard provides no guarantees about the alignment or
14120  * atomicity of device memory accesses. The recommended practice for writing
14121  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14122  * alt_write_word() functions.
14123  *
14124  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR13_LOW.
14125  */
14126 struct ALT_EMAC_GMAC_MAC_ADDR13_LOW_s
14127 {
14128  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO */
14129 };
14130 
14131 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR13_LOW. */
14132 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR13_LOW_s ALT_EMAC_GMAC_MAC_ADDR13_LOW_t;
14133 #endif /* __ASSEMBLY__ */
14134 
14135 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_LOW register. */
14136 #define ALT_EMAC_GMAC_MAC_ADDR13_LOW_RESET 0xffffffff
14137 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR13_LOW register from the beginning of the component. */
14138 #define ALT_EMAC_GMAC_MAC_ADDR13_LOW_OFST 0xac
14139 /* The address of the ALT_EMAC_GMAC_MAC_ADDR13_LOW register. */
14140 #define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR13_LOW_OFST))
14141 
14142 /*
14143  * Register : gmacgrp_mac_address14_high
14144  *
14145  * <b> Register 44 (MAC Address14 High Register) </b>
14146  *
14147  * The MAC Address14 High register holds the upper 16 bits of the 15th 6-byte MAC
14148  * address of the station.
14149  *
14150  * If the MAC address registers are configured to be double-synchronized to the
14151  * (G)MII clock domains, then the synchronization is triggered only when
14152  * Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC
14153  * Address15 Low Register are written. For proper synchronization updates, the
14154  * consecutive writes to this MAC Address14 Low Register should be performed after
14155  * at least four clock cycles in the destination clock domain.
14156  *
14157  * Register Layout
14158  *
14159  * Bits | Access | Reset | Description
14160  * :--------|:-------|:-------|:-----------------------------------------
14161  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI
14162  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR14_HIGH_RSVD_23_16
14163  * [24] | RW | 0x0 | Mask Byte Control
14164  * [25] | RW | 0x0 | Mask Byte Control
14165  * [26] | RW | 0x0 | Mask Byte Control
14166  * [27] | RW | 0x0 | Mask Byte Control
14167  * [28] | RW | 0x0 | Mask Byte Control
14168  * [29] | RW | 0x0 | Mask Byte Control
14169  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA
14170  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE
14171  *
14172  */
14173 /*
14174  * Field : addrhi
14175  *
14176  * MAC Address14 [47:32]
14177  *
14178  * This field contains the upper 16 bits (47:32) of the 15th 6-byte MAC address.
14179  *
14180  * Field Access Macros:
14181  *
14182  */
14183 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field. */
14184 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_LSB 0
14185 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field. */
14186 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_MSB 15
14187 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field. */
14188 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_WIDTH 16
14189 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field value. */
14190 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_SET_MSK 0x0000ffff
14191 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field value. */
14192 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_CLR_MSK 0xffff0000
14193 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field. */
14194 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_RESET 0xffff
14195 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI field value from a register. */
14196 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
14197 /* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field value suitable for setting the register. */
14198 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
14199 
14200 /*
14201  * Field : reserved_23_16
14202  *
14203  * Reserved
14204  *
14205  * Field Access Macros:
14206  *
14207  */
14208 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_RSVD_23_16 register field. */
14209 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_RSVD_23_16_LSB 16
14210 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_RSVD_23_16 register field. */
14211 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_RSVD_23_16_MSB 23
14212 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_RSVD_23_16 register field. */
14213 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_RSVD_23_16_WIDTH 8
14214 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_RSVD_23_16 register field value. */
14215 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
14216 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_RSVD_23_16 register field value. */
14217 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
14218 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_RSVD_23_16 register field. */
14219 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_RSVD_23_16_RESET 0x0
14220 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_RSVD_23_16 field value from a register. */
14221 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
14222 /* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_RSVD_23_16 register field value suitable for setting the register. */
14223 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
14224 
14225 /*
14226  * Field : Mask Byte Control - mbc_0
14227  *
14228  * This array of bits are mask control bits for comparison of each of the MAC
14229  * Address bytes. When masked, the MAC does not compare the corresponding byte of
14230  * received DA or SA with the contents of MAC Address14 high and low registers.
14231  * Each bit controls the masking of the bytes. You can filter a group of addresses
14232  * (known as group address filtering) by masking one or more bytes of the address.
14233  *
14234  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
14235  *
14236  * Field Enumeration Values:
14237  *
14238  * Enum | Value | Description
14239  * :----------------------------------------------|:------|:------------
14240  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_E_UNMSKED | 0x0 |
14241  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_E_MSKED | 0x1 |
14242  *
14243  * Field Access Macros:
14244  *
14245  */
14246 /*
14247  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0
14248  *
14249  */
14250 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_E_UNMSKED 0x0
14251 /*
14252  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0
14253  *
14254  */
14255 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_E_MSKED 0x1
14256 
14257 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field. */
14258 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_LSB 24
14259 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field. */
14260 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_MSB 24
14261 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field. */
14262 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_WIDTH 1
14263 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field value. */
14264 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_SET_MSK 0x01000000
14265 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field value. */
14266 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_CLR_MSK 0xfeffffff
14267 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field. */
14268 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_RESET 0x0
14269 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 field value from a register. */
14270 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
14271 /* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field value suitable for setting the register. */
14272 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
14273 
14274 /*
14275  * Field : Mask Byte Control - mbc_1
14276  *
14277  * This array of bits are mask control bits for comparison of each of the MAC
14278  * Address bytes. When masked, the MAC does not compare the corresponding byte of
14279  * received DA or SA with the contents of MAC Address14 high and low registers.
14280  * Each bit controls the masking of the bytes. You can filter a group of addresses
14281  * (known as group address filtering) by masking one or more bytes of the address.
14282  *
14283  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
14284  *
14285  * Field Enumeration Values:
14286  *
14287  * Enum | Value | Description
14288  * :----------------------------------------------|:------|:------------
14289  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_E_UNMSKED | 0x0 |
14290  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_E_MSKED | 0x1 |
14291  *
14292  * Field Access Macros:
14293  *
14294  */
14295 /*
14296  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1
14297  *
14298  */
14299 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_E_UNMSKED 0x0
14300 /*
14301  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1
14302  *
14303  */
14304 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_E_MSKED 0x1
14305 
14306 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field. */
14307 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_LSB 25
14308 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field. */
14309 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_MSB 25
14310 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field. */
14311 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_WIDTH 1
14312 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field value. */
14313 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_SET_MSK 0x02000000
14314 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field value. */
14315 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_CLR_MSK 0xfdffffff
14316 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field. */
14317 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_RESET 0x0
14318 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 field value from a register. */
14319 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
14320 /* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field value suitable for setting the register. */
14321 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
14322 
14323 /*
14324  * Field : Mask Byte Control - mbc_2
14325  *
14326  * This array of bits are mask control bits for comparison of each of the MAC
14327  * Address bytes. When masked, the MAC does not compare the corresponding byte of
14328  * received DA or SA with the contents of MAC Address14 high and low registers.
14329  * Each bit controls the masking of the bytes. You can filter a group of addresses
14330  * (known as group address filtering) by masking one or more bytes of the address.
14331  *
14332  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
14333  *
14334  * Field Enumeration Values:
14335  *
14336  * Enum | Value | Description
14337  * :----------------------------------------------|:------|:------------
14338  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_E_UNMSKED | 0x0 |
14339  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_E_MSKED | 0x1 |
14340  *
14341  * Field Access Macros:
14342  *
14343  */
14344 /*
14345  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2
14346  *
14347  */
14348 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_E_UNMSKED 0x0
14349 /*
14350  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2
14351  *
14352  */
14353 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_E_MSKED 0x1
14354 
14355 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field. */
14356 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_LSB 26
14357 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field. */
14358 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_MSB 26
14359 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field. */
14360 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_WIDTH 1
14361 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field value. */
14362 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_SET_MSK 0x04000000
14363 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field value. */
14364 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_CLR_MSK 0xfbffffff
14365 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field. */
14366 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_RESET 0x0
14367 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 field value from a register. */
14368 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
14369 /* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field value suitable for setting the register. */
14370 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
14371 
14372 /*
14373  * Field : Mask Byte Control - mbc_3
14374  *
14375  * This array of bits are mask control bits for comparison of each of the MAC
14376  * Address bytes. When masked, the MAC does not compare the corresponding byte of
14377  * received DA or SA with the contents of MAC Address14 high and low registers.
14378  * Each bit controls the masking of the bytes. You can filter a group of addresses
14379  * (known as group address filtering) by masking one or more bytes of the address.
14380  *
14381  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
14382  *
14383  * Field Enumeration Values:
14384  *
14385  * Enum | Value | Description
14386  * :----------------------------------------------|:------|:------------
14387  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_E_UNMSKED | 0x0 |
14388  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_E_MSKED | 0x1 |
14389  *
14390  * Field Access Macros:
14391  *
14392  */
14393 /*
14394  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3
14395  *
14396  */
14397 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_E_UNMSKED 0x0
14398 /*
14399  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3
14400  *
14401  */
14402 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_E_MSKED 0x1
14403 
14404 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field. */
14405 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_LSB 27
14406 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field. */
14407 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_MSB 27
14408 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field. */
14409 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_WIDTH 1
14410 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field value. */
14411 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_SET_MSK 0x08000000
14412 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field value. */
14413 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_CLR_MSK 0xf7ffffff
14414 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field. */
14415 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_RESET 0x0
14416 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 field value from a register. */
14417 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
14418 /* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field value suitable for setting the register. */
14419 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
14420 
14421 /*
14422  * Field : Mask Byte Control - mbc_4
14423  *
14424  * This array of bits are mask control bits for comparison of each of the MAC
14425  * Address bytes. When masked, the MAC does not compare the corresponding byte of
14426  * received DA or SA with the contents of MAC Address14 high and low registers.
14427  * Each bit controls the masking of the bytes. You can filter a group of addresses
14428  * (known as group address filtering) by masking one or more bytes of the address.
14429  *
14430  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
14431  *
14432  * Field Enumeration Values:
14433  *
14434  * Enum | Value | Description
14435  * :----------------------------------------------|:------|:------------
14436  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_E_UNMSKED | 0x0 |
14437  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_E_MSKED | 0x1 |
14438  *
14439  * Field Access Macros:
14440  *
14441  */
14442 /*
14443  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4
14444  *
14445  */
14446 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_E_UNMSKED 0x0
14447 /*
14448  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4
14449  *
14450  */
14451 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_E_MSKED 0x1
14452 
14453 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field. */
14454 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_LSB 28
14455 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field. */
14456 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_MSB 28
14457 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field. */
14458 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_WIDTH 1
14459 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field value. */
14460 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_SET_MSK 0x10000000
14461 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field value. */
14462 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_CLR_MSK 0xefffffff
14463 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field. */
14464 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_RESET 0x0
14465 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 field value from a register. */
14466 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
14467 /* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field value suitable for setting the register. */
14468 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
14469 
14470 /*
14471  * Field : Mask Byte Control - mbc_5
14472  *
14473  * This array of bits are mask control bits for comparison of each of the MAC
14474  * Address bytes. When masked, the MAC does not compare the corresponding byte of
14475  * received DA or SA with the contents of MAC Address14 high and low registers.
14476  * Each bit controls the masking of the bytes. You can filter a group of addresses
14477  * (known as group address filtering) by masking one or more bytes of the address.
14478  *
14479  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
14480  *
14481  * Field Enumeration Values:
14482  *
14483  * Enum | Value | Description
14484  * :----------------------------------------------|:------|:------------
14485  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_E_UNMSKED | 0x0 |
14486  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_E_MSKED | 0x1 |
14487  *
14488  * Field Access Macros:
14489  *
14490  */
14491 /*
14492  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5
14493  *
14494  */
14495 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_E_UNMSKED 0x0
14496 /*
14497  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5
14498  *
14499  */
14500 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_E_MSKED 0x1
14501 
14502 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field. */
14503 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_LSB 29
14504 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field. */
14505 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_MSB 29
14506 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field. */
14507 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_WIDTH 1
14508 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field value. */
14509 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_SET_MSK 0x20000000
14510 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field value. */
14511 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_CLR_MSK 0xdfffffff
14512 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field. */
14513 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_RESET 0x0
14514 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 field value from a register. */
14515 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
14516 /* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field value suitable for setting the register. */
14517 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
14518 
14519 /*
14520  * Field : sa
14521  *
14522  * Source Address
14523  *
14524  * When this bit is set, the MAC Address14[47:0] is used to compare with the SA
14525  * fields of the received frame. When this bit is reset, the MAC Address14[47:0] is
14526  * used to compare with the DA fields of the received frame.
14527  *
14528  * Field Enumeration Values:
14529  *
14530  * Enum | Value | Description
14531  * :----------------------------------------|:------|:------------
14532  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_E_DISD | 0x0 |
14533  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_E_END | 0x1 |
14534  *
14535  * Field Access Macros:
14536  *
14537  */
14538 /*
14539  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA
14540  *
14541  */
14542 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_E_DISD 0x0
14543 /*
14544  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA
14545  *
14546  */
14547 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_E_END 0x1
14548 
14549 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field. */
14550 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_LSB 30
14551 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field. */
14552 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_MSB 30
14553 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field. */
14554 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_WIDTH 1
14555 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field value. */
14556 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_SET_MSK 0x40000000
14557 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field value. */
14558 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_CLR_MSK 0xbfffffff
14559 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field. */
14560 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_RESET 0x0
14561 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA field value from a register. */
14562 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
14563 /* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field value suitable for setting the register. */
14564 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
14565 
14566 /*
14567  * Field : ae
14568  *
14569  * Address Enable
14570  *
14571  * When this bit is set, the address filter module uses the 15th MAC address for
14572  * perfect filtering. When this bit is reset, the address filter module ignores the
14573  * address for filtering.
14574  *
14575  * Field Enumeration Values:
14576  *
14577  * Enum | Value | Description
14578  * :----------------------------------------|:------|:------------
14579  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_E_DISD | 0x0 |
14580  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_E_END | 0x1 |
14581  *
14582  * Field Access Macros:
14583  *
14584  */
14585 /*
14586  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE
14587  *
14588  */
14589 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_E_DISD 0x0
14590 /*
14591  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE
14592  *
14593  */
14594 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_E_END 0x1
14595 
14596 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field. */
14597 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_LSB 31
14598 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field. */
14599 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_MSB 31
14600 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field. */
14601 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_WIDTH 1
14602 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field value. */
14603 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_SET_MSK 0x80000000
14604 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field value. */
14605 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_CLR_MSK 0x7fffffff
14606 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field. */
14607 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_RESET 0x0
14608 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE field value from a register. */
14609 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
14610 /* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field value suitable for setting the register. */
14611 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
14612 
14613 #ifndef __ASSEMBLY__
14614 /*
14615  * WARNING: The C register and register group struct declarations are provided for
14616  * convenience and illustrative purposes. They should, however, be used with
14617  * caution as the C language standard provides no guarantees about the alignment or
14618  * atomicity of device memory accesses. The recommended practice for writing
14619  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14620  * alt_write_word() functions.
14621  *
14622  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR14_HIGH.
14623  */
14624 struct ALT_EMAC_GMAC_MAC_ADDR14_HIGH_s
14625 {
14626  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI */
14627  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR14_HIGH_RSVD_23_16 */
14628  uint32_t mbc_0 : 1; /* Mask Byte Control */
14629  uint32_t mbc_1 : 1; /* Mask Byte Control */
14630  uint32_t mbc_2 : 1; /* Mask Byte Control */
14631  uint32_t mbc_3 : 1; /* Mask Byte Control */
14632  uint32_t mbc_4 : 1; /* Mask Byte Control */
14633  uint32_t mbc_5 : 1; /* Mask Byte Control */
14634  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA */
14635  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE */
14636 };
14637 
14638 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR14_HIGH. */
14639 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR14_HIGH_s ALT_EMAC_GMAC_MAC_ADDR14_HIGH_t;
14640 #endif /* __ASSEMBLY__ */
14641 
14642 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH register. */
14643 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_RESET 0x0000ffff
14644 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH register from the beginning of the component. */
14645 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_OFST 0xb0
14646 /* The address of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH register. */
14647 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR14_HIGH_OFST))
14648 
14649 /*
14650  * Register : gmacgrp_mac_address14_low
14651  *
14652  * <b> Register 45 (MAC Address14 Low Register) </b>
14653  *
14654  * The MAC Address14 Low register holds the lower 32 bits of the 15th 6-byte MAC
14655  * address of the station.
14656  *
14657  * Register Layout
14658  *
14659  * Bits | Access | Reset | Description
14660  * :-------|:-------|:-----------|:------------------------------------
14661  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO
14662  *
14663  */
14664 /*
14665  * Field : addrlo
14666  *
14667  * MAC Address14 [31:0]
14668  *
14669  * This field contains the lower 32 bits of the 15th 6-byte MAC address. The
14670  * content of this field is undefined until loaded by the Application after the
14671  * initialization process.
14672  *
14673  * Field Access Macros:
14674  *
14675  */
14676 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field. */
14677 #define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_LSB 0
14678 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field. */
14679 #define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_MSB 31
14680 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field. */
14681 #define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_WIDTH 32
14682 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field value. */
14683 #define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_SET_MSK 0xffffffff
14684 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field value. */
14685 #define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_CLR_MSK 0x00000000
14686 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field. */
14687 #define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_RESET 0xffffffff
14688 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO field value from a register. */
14689 #define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
14690 /* Produces a ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field value suitable for setting the register. */
14691 #define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
14692 
14693 #ifndef __ASSEMBLY__
14694 /*
14695  * WARNING: The C register and register group struct declarations are provided for
14696  * convenience and illustrative purposes. They should, however, be used with
14697  * caution as the C language standard provides no guarantees about the alignment or
14698  * atomicity of device memory accesses. The recommended practice for writing
14699  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14700  * alt_write_word() functions.
14701  *
14702  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR14_LOW.
14703  */
14704 struct ALT_EMAC_GMAC_MAC_ADDR14_LOW_s
14705 {
14706  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO */
14707 };
14708 
14709 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR14_LOW. */
14710 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR14_LOW_s ALT_EMAC_GMAC_MAC_ADDR14_LOW_t;
14711 #endif /* __ASSEMBLY__ */
14712 
14713 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_LOW register. */
14714 #define ALT_EMAC_GMAC_MAC_ADDR14_LOW_RESET 0xffffffff
14715 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR14_LOW register from the beginning of the component. */
14716 #define ALT_EMAC_GMAC_MAC_ADDR14_LOW_OFST 0xb4
14717 /* The address of the ALT_EMAC_GMAC_MAC_ADDR14_LOW register. */
14718 #define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR14_LOW_OFST))
14719 
14720 /*
14721  * Register : gmacgrp_mac_address15_high
14722  *
14723  * <b> Register 46 (MAC Address15 High Register) </b>
14724  *
14725  * The MAC Address15 High register holds the upper 16 bits of the 16th 6-byte MAC
14726  * address of the station.
14727  *
14728  * If the MAC address registers are configured to be double-synchronized to the
14729  * (G)MII clock domains, then the synchronization is triggered only when
14730  * Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC
14731  * Address15 Low Register are written. For proper synchronization updates, the
14732  * consecutive writes to this MAC Address15 Low Register should be performed after
14733  * at least four clock cycles in the destination clock domain.
14734  *
14735  * Register Layout
14736  *
14737  * Bits | Access | Reset | Description
14738  * :--------|:-------|:-------|:-----------------------------------------
14739  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI
14740  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR15_HIGH_RSVD_23_16
14741  * [24] | RW | 0x0 | Mask Byte Control
14742  * [25] | RW | 0x0 | Mask Byte Control
14743  * [26] | RW | 0x0 | Mask Byte Control
14744  * [27] | RW | 0x0 | Mask Byte Control
14745  * [28] | RW | 0x0 | Mask Byte Control
14746  * [29] | RW | 0x0 | Mask Byte Control
14747  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA
14748  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE
14749  *
14750  */
14751 /*
14752  * Field : addrhi
14753  *
14754  * MAC Address15 [47:32] This field contains the upper 16 bits (47:32) of the 16th
14755  * 6-byte MAC address.
14756  *
14757  * Field Access Macros:
14758  *
14759  */
14760 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field. */
14761 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_LSB 0
14762 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field. */
14763 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_MSB 15
14764 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field. */
14765 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_WIDTH 16
14766 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field value. */
14767 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_SET_MSK 0x0000ffff
14768 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field value. */
14769 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_CLR_MSK 0xffff0000
14770 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field. */
14771 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_RESET 0xffff
14772 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI field value from a register. */
14773 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
14774 /* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field value suitable for setting the register. */
14775 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
14776 
14777 /*
14778  * Field : reserved_23_16
14779  *
14780  * Reserved
14781  *
14782  * Field Access Macros:
14783  *
14784  */
14785 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_RSVD_23_16 register field. */
14786 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_RSVD_23_16_LSB 16
14787 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_RSVD_23_16 register field. */
14788 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_RSVD_23_16_MSB 23
14789 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_RSVD_23_16 register field. */
14790 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_RSVD_23_16_WIDTH 8
14791 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_RSVD_23_16 register field value. */
14792 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
14793 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_RSVD_23_16 register field value. */
14794 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
14795 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_RSVD_23_16 register field. */
14796 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_RSVD_23_16_RESET 0x0
14797 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_RSVD_23_16 field value from a register. */
14798 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
14799 /* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_RSVD_23_16 register field value suitable for setting the register. */
14800 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
14801 
14802 /*
14803  * Field : Mask Byte Control - mbc_0
14804  *
14805  * This array of bits are mask control bits for comparison of each of the MAC
14806  * Address bytes. When masked, the MAC does not compare the corresponding byte of
14807  * received DA or SA with the contents of MAC Address15 high and low registers.
14808  * Each bit controls the masking of the bytes. You can filter a group of addresses
14809  * (known as group address filtering) by masking one or more bytes of the address.
14810  *
14811  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
14812  *
14813  * Field Enumeration Values:
14814  *
14815  * Enum | Value | Description
14816  * :----------------------------------------------|:------|:------------
14817  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_E_UNMSKED | 0x0 |
14818  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_E_MSKED | 0x1 |
14819  *
14820  * Field Access Macros:
14821  *
14822  */
14823 /*
14824  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0
14825  *
14826  */
14827 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_E_UNMSKED 0x0
14828 /*
14829  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0
14830  *
14831  */
14832 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_E_MSKED 0x1
14833 
14834 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field. */
14835 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_LSB 24
14836 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field. */
14837 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_MSB 24
14838 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field. */
14839 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_WIDTH 1
14840 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field value. */
14841 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_SET_MSK 0x01000000
14842 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field value. */
14843 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_CLR_MSK 0xfeffffff
14844 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field. */
14845 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_RESET 0x0
14846 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 field value from a register. */
14847 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
14848 /* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field value suitable for setting the register. */
14849 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
14850 
14851 /*
14852  * Field : Mask Byte Control - mbc_1
14853  *
14854  * This array of bits are mask control bits for comparison of each of the MAC
14855  * Address bytes. When masked, the MAC does not compare the corresponding byte of
14856  * received DA or SA with the contents of MAC Address15 high and low registers.
14857  * Each bit controls the masking of the bytes. You can filter a group of addresses
14858  * (known as group address filtering) by masking one or more bytes of the address.
14859  *
14860  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
14861  *
14862  * Field Enumeration Values:
14863  *
14864  * Enum | Value | Description
14865  * :----------------------------------------------|:------|:------------
14866  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_E_UNMSKED | 0x0 |
14867  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_E_MSKED | 0x1 |
14868  *
14869  * Field Access Macros:
14870  *
14871  */
14872 /*
14873  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1
14874  *
14875  */
14876 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_E_UNMSKED 0x0
14877 /*
14878  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1
14879  *
14880  */
14881 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_E_MSKED 0x1
14882 
14883 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field. */
14884 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_LSB 25
14885 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field. */
14886 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_MSB 25
14887 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field. */
14888 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_WIDTH 1
14889 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field value. */
14890 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_SET_MSK 0x02000000
14891 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field value. */
14892 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_CLR_MSK 0xfdffffff
14893 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field. */
14894 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_RESET 0x0
14895 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 field value from a register. */
14896 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
14897 /* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field value suitable for setting the register. */
14898 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
14899 
14900 /*
14901  * Field : Mask Byte Control - mbc_2
14902  *
14903  * This array of bits are mask control bits for comparison of each of the MAC
14904  * Address bytes. When masked, the MAC does not compare the corresponding byte of
14905  * received DA or SA with the contents of MAC Address15 high and low registers.
14906  * Each bit controls the masking of the bytes. You can filter a group of addresses
14907  * (known as group address filtering) by masking one or more bytes of the address.
14908  *
14909  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
14910  *
14911  * Field Enumeration Values:
14912  *
14913  * Enum | Value | Description
14914  * :----------------------------------------------|:------|:------------
14915  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_E_UNMSKED | 0x0 |
14916  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_E_MSKED | 0x1 |
14917  *
14918  * Field Access Macros:
14919  *
14920  */
14921 /*
14922  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2
14923  *
14924  */
14925 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_E_UNMSKED 0x0
14926 /*
14927  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2
14928  *
14929  */
14930 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_E_MSKED 0x1
14931 
14932 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field. */
14933 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_LSB 26
14934 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field. */
14935 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_MSB 26
14936 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field. */
14937 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_WIDTH 1
14938 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field value. */
14939 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_SET_MSK 0x04000000
14940 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field value. */
14941 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_CLR_MSK 0xfbffffff
14942 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field. */
14943 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_RESET 0x0
14944 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 field value from a register. */
14945 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
14946 /* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field value suitable for setting the register. */
14947 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
14948 
14949 /*
14950  * Field : Mask Byte Control - mbc_3
14951  *
14952  * This array of bits are mask control bits for comparison of each of the MAC
14953  * Address bytes. When masked, the MAC does not compare the corresponding byte of
14954  * received DA or SA with the contents of MAC Address15 high and low registers.
14955  * Each bit controls the masking of the bytes. You can filter a group of addresses
14956  * (known as group address filtering) by masking one or more bytes of the address.
14957  *
14958  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
14959  *
14960  * Field Enumeration Values:
14961  *
14962  * Enum | Value | Description
14963  * :----------------------------------------------|:------|:------------
14964  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_E_UNMSKED | 0x0 |
14965  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_E_MSKED | 0x1 |
14966  *
14967  * Field Access Macros:
14968  *
14969  */
14970 /*
14971  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3
14972  *
14973  */
14974 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_E_UNMSKED 0x0
14975 /*
14976  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3
14977  *
14978  */
14979 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_E_MSKED 0x1
14980 
14981 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field. */
14982 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_LSB 27
14983 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field. */
14984 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_MSB 27
14985 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field. */
14986 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_WIDTH 1
14987 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field value. */
14988 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_SET_MSK 0x08000000
14989 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field value. */
14990 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_CLR_MSK 0xf7ffffff
14991 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field. */
14992 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_RESET 0x0
14993 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 field value from a register. */
14994 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
14995 /* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field value suitable for setting the register. */
14996 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
14997 
14998 /*
14999  * Field : Mask Byte Control - mbc_4
15000  *
15001  * This array of bits are mask control bits for comparison of each of the MAC
15002  * Address bytes. When masked, the MAC does not compare the corresponding byte of
15003  * received DA or SA with the contents of MAC Address15 high and low registers.
15004  * Each bit controls the masking of the bytes. You can filter a group of addresses
15005  * (known as group address filtering) by masking one or more bytes of the address.
15006  *
15007  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
15008  *
15009  * Field Enumeration Values:
15010  *
15011  * Enum | Value | Description
15012  * :----------------------------------------------|:------|:------------
15013  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_E_UNMSKED | 0x0 |
15014  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_E_MSKED | 0x1 |
15015  *
15016  * Field Access Macros:
15017  *
15018  */
15019 /*
15020  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4
15021  *
15022  */
15023 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_E_UNMSKED 0x0
15024 /*
15025  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4
15026  *
15027  */
15028 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_E_MSKED 0x1
15029 
15030 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field. */
15031 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_LSB 28
15032 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field. */
15033 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_MSB 28
15034 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field. */
15035 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_WIDTH 1
15036 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field value. */
15037 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_SET_MSK 0x10000000
15038 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field value. */
15039 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_CLR_MSK 0xefffffff
15040 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field. */
15041 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_RESET 0x0
15042 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 field value from a register. */
15043 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
15044 /* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field value suitable for setting the register. */
15045 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
15046 
15047 /*
15048  * Field : Mask Byte Control - mbc_5
15049  *
15050  * This array of bits are mask control bits for comparison of each of the MAC
15051  * Address bytes. When masked, the MAC does not compare the corresponding byte of
15052  * received DA or SA with the contents of MAC Address15 high and low registers.
15053  * Each bit controls the masking of the bytes. You can filter a group of addresses
15054  * (known as group address filtering) by masking one or more bytes of the address.
15055  *
15056  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
15057  *
15058  * Field Enumeration Values:
15059  *
15060  * Enum | Value | Description
15061  * :----------------------------------------------|:------|:------------
15062  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_E_UNMSKED | 0x0 |
15063  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_E_MSKED | 0x1 |
15064  *
15065  * Field Access Macros:
15066  *
15067  */
15068 /*
15069  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5
15070  *
15071  */
15072 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_E_UNMSKED 0x0
15073 /*
15074  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5
15075  *
15076  */
15077 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_E_MSKED 0x1
15078 
15079 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field. */
15080 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_LSB 29
15081 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field. */
15082 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_MSB 29
15083 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field. */
15084 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_WIDTH 1
15085 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field value. */
15086 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_SET_MSK 0x20000000
15087 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field value. */
15088 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_CLR_MSK 0xdfffffff
15089 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field. */
15090 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_RESET 0x0
15091 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 field value from a register. */
15092 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
15093 /* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field value suitable for setting the register. */
15094 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
15095 
15096 /*
15097  * Field : sa
15098  *
15099  * Source Address
15100  *
15101  * When this bit is set, the MAC Address15[47:0] is used to compare with the SA
15102  * fields of the received frame. When this bit is reset, the MAC Address15[47:0] is
15103  * used to compare with the DA fields of the received frame.
15104  *
15105  * Field Enumeration Values:
15106  *
15107  * Enum | Value | Description
15108  * :----------------------------------------|:------|:------------
15109  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_E_DISD | 0x0 |
15110  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_E_END | 0x1 |
15111  *
15112  * Field Access Macros:
15113  *
15114  */
15115 /*
15116  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA
15117  *
15118  */
15119 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_E_DISD 0x0
15120 /*
15121  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA
15122  *
15123  */
15124 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_E_END 0x1
15125 
15126 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field. */
15127 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_LSB 30
15128 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field. */
15129 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_MSB 30
15130 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field. */
15131 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_WIDTH 1
15132 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field value. */
15133 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_SET_MSK 0x40000000
15134 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field value. */
15135 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_CLR_MSK 0xbfffffff
15136 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field. */
15137 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_RESET 0x0
15138 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA field value from a register. */
15139 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
15140 /* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field value suitable for setting the register. */
15141 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
15142 
15143 /*
15144  * Field : ae
15145  *
15146  * Address Enable
15147  *
15148  * When this bit is set, the address filter module uses the 16th MAC address for
15149  * perfect filtering. When this bit is reset, the address filter module ignores the
15150  * address for filtering.
15151  *
15152  * Field Enumeration Values:
15153  *
15154  * Enum | Value | Description
15155  * :----------------------------------------|:------|:------------
15156  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_E_DISD | 0x0 |
15157  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_E_END | 0x1 |
15158  *
15159  * Field Access Macros:
15160  *
15161  */
15162 /*
15163  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE
15164  *
15165  */
15166 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_E_DISD 0x0
15167 /*
15168  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE
15169  *
15170  */
15171 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_E_END 0x1
15172 
15173 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field. */
15174 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_LSB 31
15175 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field. */
15176 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_MSB 31
15177 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field. */
15178 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_WIDTH 1
15179 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field value. */
15180 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_SET_MSK 0x80000000
15181 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field value. */
15182 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_CLR_MSK 0x7fffffff
15183 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field. */
15184 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_RESET 0x0
15185 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE field value from a register. */
15186 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
15187 /* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field value suitable for setting the register. */
15188 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
15189 
15190 #ifndef __ASSEMBLY__
15191 /*
15192  * WARNING: The C register and register group struct declarations are provided for
15193  * convenience and illustrative purposes. They should, however, be used with
15194  * caution as the C language standard provides no guarantees about the alignment or
15195  * atomicity of device memory accesses. The recommended practice for writing
15196  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15197  * alt_write_word() functions.
15198  *
15199  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR15_HIGH.
15200  */
15201 struct ALT_EMAC_GMAC_MAC_ADDR15_HIGH_s
15202 {
15203  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI */
15204  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR15_HIGH_RSVD_23_16 */
15205  uint32_t mbc_0 : 1; /* Mask Byte Control */
15206  uint32_t mbc_1 : 1; /* Mask Byte Control */
15207  uint32_t mbc_2 : 1; /* Mask Byte Control */
15208  uint32_t mbc_3 : 1; /* Mask Byte Control */
15209  uint32_t mbc_4 : 1; /* Mask Byte Control */
15210  uint32_t mbc_5 : 1; /* Mask Byte Control */
15211  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA */
15212  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE */
15213 };
15214 
15215 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR15_HIGH. */
15216 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR15_HIGH_s ALT_EMAC_GMAC_MAC_ADDR15_HIGH_t;
15217 #endif /* __ASSEMBLY__ */
15218 
15219 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH register. */
15220 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_RESET 0x0000ffff
15221 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH register from the beginning of the component. */
15222 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_OFST 0xb8
15223 /* The address of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH register. */
15224 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR15_HIGH_OFST))
15225 
15226 /*
15227  * Register : gmacgrp_mac_address15_low
15228  *
15229  * <b> Register 47 (MAC Address15 Low Register) </b>
15230  *
15231  * The MAC Address15 Low register holds the lower 32 bits of the 16th 6-byte MAC
15232  * address of the station.
15233  *
15234  * Register Layout
15235  *
15236  * Bits | Access | Reset | Description
15237  * :-------|:-------|:-----------|:------------------------------------
15238  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO
15239  *
15240  */
15241 /*
15242  * Field : addrlo
15243  *
15244  * MAC Address15 [31:0]
15245  *
15246  * This field contains the lower 32 bits of the 16th 6-byte MAC address. The
15247  * content of this field is undefined until loaded by the Application after the
15248  * initialization process.
15249  *
15250  * Field Access Macros:
15251  *
15252  */
15253 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field. */
15254 #define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_LSB 0
15255 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field. */
15256 #define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_MSB 31
15257 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field. */
15258 #define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_WIDTH 32
15259 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field value. */
15260 #define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_SET_MSK 0xffffffff
15261 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field value. */
15262 #define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_CLR_MSK 0x00000000
15263 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field. */
15264 #define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_RESET 0xffffffff
15265 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO field value from a register. */
15266 #define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
15267 /* Produces a ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field value suitable for setting the register. */
15268 #define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
15269 
15270 #ifndef __ASSEMBLY__
15271 /*
15272  * WARNING: The C register and register group struct declarations are provided for
15273  * convenience and illustrative purposes. They should, however, be used with
15274  * caution as the C language standard provides no guarantees about the alignment or
15275  * atomicity of device memory accesses. The recommended practice for writing
15276  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15277  * alt_write_word() functions.
15278  *
15279  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR15_LOW.
15280  */
15281 struct ALT_EMAC_GMAC_MAC_ADDR15_LOW_s
15282 {
15283  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO */
15284 };
15285 
15286 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR15_LOW. */
15287 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR15_LOW_s ALT_EMAC_GMAC_MAC_ADDR15_LOW_t;
15288 #endif /* __ASSEMBLY__ */
15289 
15290 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_LOW register. */
15291 #define ALT_EMAC_GMAC_MAC_ADDR15_LOW_RESET 0xffffffff
15292 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR15_LOW register from the beginning of the component. */
15293 #define ALT_EMAC_GMAC_MAC_ADDR15_LOW_OFST 0xbc
15294 /* The address of the ALT_EMAC_GMAC_MAC_ADDR15_LOW register. */
15295 #define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR15_LOW_OFST))
15296 
15297 /*
15298  * Register : Register 54 (SGMII/RGMII/SMII Status Register) - gmacgrp_sgmii_rgmii_smii_control_status
15299  *
15300  * The SGMII/RGMII/SMII Status register indicates the status signals received by
15301  * the RGMII interface (selected at reset) from the PHY.
15302  *
15303  * Register Layout
15304  *
15305  * Bits | Access | Reset | Description
15306  * :-------|:-------|:------|:------------
15307  * [0] | R | 0x0 | Link Mode
15308  * [2:1] | R | 0x0 | Link Speed
15309  * [3] | R | 0x0 | Link Status
15310  * [31:4] | ??? | 0x0 | *UNDEFINED*
15311  *
15312  */
15313 /*
15314  * Field : Link Mode - lnkmod
15315  *
15316  * This bit indicates the current mode of operation of the link
15317  *
15318  * Field Enumeration Values:
15319  *
15320  * Enum | Value | Description
15321  * :--------------------------------------------|:------|:------------
15322  * ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_E_HALFDUP | 0x0 |
15323  * ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_E_FULLDUP | 0x1 |
15324  *
15325  * Field Access Macros:
15326  *
15327  */
15328 /*
15329  * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD
15330  *
15331  */
15332 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_E_HALFDUP 0x0
15333 /*
15334  * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD
15335  *
15336  */
15337 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_E_FULLDUP 0x1
15338 
15339 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field. */
15340 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_LSB 0
15341 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field. */
15342 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_MSB 0
15343 /* The width in bits of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field. */
15344 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_WIDTH 1
15345 /* The mask used to set the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field value. */
15346 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_SET_MSK 0x00000001
15347 /* The mask used to clear the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field value. */
15348 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_CLR_MSK 0xfffffffe
15349 /* The reset value of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field. */
15350 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_RESET 0x0
15351 /* Extracts the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD field value from a register. */
15352 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_GET(value) (((value) & 0x00000001) >> 0)
15353 /* Produces a ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field value suitable for setting the register. */
15354 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_SET(value) (((value) << 0) & 0x00000001)
15355 
15356 /*
15357  * Field : Link Speed - lnkspeed
15358  *
15359  * This bit indicates the current speed of the link. Bit 2 is reserved when the MAC
15360  * is configured for the SMII PHY interface.
15361  *
15362  * Field Enumeration Values:
15363  *
15364  * Enum | Value | Description
15365  * :------------------------------------------------------|:------|:------------
15366  * ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED2POINT5MHZ | 0x0 |
15367  * ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED25MHZ | 0x1 |
15368  * ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED125MHZ | 0x2 |
15369  *
15370  * Field Access Macros:
15371  *
15372  */
15373 /*
15374  * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED
15375  *
15376  */
15377 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED2POINT5MHZ 0x0
15378 /*
15379  * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED
15380  *
15381  */
15382 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED25MHZ 0x1
15383 /*
15384  * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED
15385  *
15386  */
15387 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED125MHZ 0x2
15388 
15389 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field. */
15390 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_LSB 1
15391 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field. */
15392 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_MSB 2
15393 /* The width in bits of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field. */
15394 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_WIDTH 2
15395 /* The mask used to set the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field value. */
15396 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_SET_MSK 0x00000006
15397 /* The mask used to clear the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field value. */
15398 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_CLR_MSK 0xfffffff9
15399 /* The reset value of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field. */
15400 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_RESET 0x0
15401 /* Extracts the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED field value from a register. */
15402 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_GET(value) (((value) & 0x00000006) >> 1)
15403 /* Produces a ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field value suitable for setting the register. */
15404 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_SET(value) (((value) << 1) & 0x00000006)
15405 
15406 /*
15407  * Field : Link Status - lnksts
15408  *
15409  * This bit indicates whether the link is up (1'b1) or down (1'b0).
15410  *
15411  * Field Enumeration Values:
15412  *
15413  * Enum | Value | Description
15414  * :---------------------------------------------|:------|:------------
15415  * ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_E_LINKDOWN | 0x0 |
15416  * ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_E_LINKUP | 0x1 |
15417  *
15418  * Field Access Macros:
15419  *
15420  */
15421 /*
15422  * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS
15423  *
15424  */
15425 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_E_LINKDOWN 0x0
15426 /*
15427  * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS
15428  *
15429  */
15430 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_E_LINKUP 0x1
15431 
15432 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field. */
15433 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_LSB 3
15434 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field. */
15435 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_MSB 3
15436 /* The width in bits of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field. */
15437 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_WIDTH 1
15438 /* The mask used to set the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field value. */
15439 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_SET_MSK 0x00000008
15440 /* The mask used to clear the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field value. */
15441 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_CLR_MSK 0xfffffff7
15442 /* The reset value of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field. */
15443 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_RESET 0x0
15444 /* Extracts the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS field value from a register. */
15445 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_GET(value) (((value) & 0x00000008) >> 3)
15446 /* Produces a ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field value suitable for setting the register. */
15447 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_SET(value) (((value) << 3) & 0x00000008)
15448 
15449 #ifndef __ASSEMBLY__
15450 /*
15451  * WARNING: The C register and register group struct declarations are provided for
15452  * convenience and illustrative purposes. They should, however, be used with
15453  * caution as the C language standard provides no guarantees about the alignment or
15454  * atomicity of device memory accesses. The recommended practice for writing
15455  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15456  * alt_write_word() functions.
15457  *
15458  * The struct declaration for register ALT_EMAC_GMAC_MII_CTL_STAT.
15459  */
15460 struct ALT_EMAC_GMAC_MII_CTL_STAT_s
15461 {
15462  const uint32_t lnkmod : 1; /* Link Mode */
15463  const uint32_t lnkspeed : 2; /* Link Speed */
15464  const uint32_t lnksts : 1; /* Link Status */
15465  uint32_t : 28; /* *UNDEFINED* */
15466 };
15467 
15468 /* The typedef declaration for register ALT_EMAC_GMAC_MII_CTL_STAT. */
15469 typedef volatile struct ALT_EMAC_GMAC_MII_CTL_STAT_s ALT_EMAC_GMAC_MII_CTL_STAT_t;
15470 #endif /* __ASSEMBLY__ */
15471 
15472 /* The reset value of the ALT_EMAC_GMAC_MII_CTL_STAT register. */
15473 #define ALT_EMAC_GMAC_MII_CTL_STAT_RESET 0x00000000
15474 /* The byte offset of the ALT_EMAC_GMAC_MII_CTL_STAT register from the beginning of the component. */
15475 #define ALT_EMAC_GMAC_MII_CTL_STAT_OFST 0xd8
15476 /* The address of the ALT_EMAC_GMAC_MII_CTL_STAT register. */
15477 #define ALT_EMAC_GMAC_MII_CTL_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MII_CTL_STAT_OFST))
15478 
15479 /*
15480  * Register : gmacgrp_wdog_timeout
15481  *
15482  * <b> Register 55 (Watchdog Timeout Register) </b>
15483  *
15484  * This register controls the watchdog timeout for received frames.
15485  *
15486  * Register Layout
15487  *
15488  * Bits | Access | Reset | Description
15489  * :--------|:-------|:------|:----------------------------------
15490  * [13:0] | RW | 0x0 | ALT_EMAC_GMAC_WDOG_TMO_WTO
15491  * [15:14] | R | 0x0 | ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14
15492  * [16] | RW | 0x0 | ALT_EMAC_GMAC_WDOG_TMO_PWE
15493  * [31:17] | R | 0x0 | ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17
15494  *
15495  */
15496 /*
15497  * Field : wto
15498  *
15499  * Watchdog Timeout
15500  *
15501  * When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration
15502  * Register) is reset, this field is used as watchdog timeout for a received frame.
15503  * If the length of a received frame exceeds the value of this field, such frame is
15504  * terminated and declared as an error frame.
15505  *
15506  * Note: When Bit 16 (PWE) is set, the value in this field should be more than
15507  * 1,522 (0x05F2). Otherwise, the IEEE Std 802.3-specified valid tagged frames are
15508  * declared as error frames and are dropped.
15509  *
15510  * Field Access Macros:
15511  *
15512  */
15513 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_WDOG_TMO_WTO register field. */
15514 #define ALT_EMAC_GMAC_WDOG_TMO_WTO_LSB 0
15515 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_WDOG_TMO_WTO register field. */
15516 #define ALT_EMAC_GMAC_WDOG_TMO_WTO_MSB 13
15517 /* The width in bits of the ALT_EMAC_GMAC_WDOG_TMO_WTO register field. */
15518 #define ALT_EMAC_GMAC_WDOG_TMO_WTO_WIDTH 14
15519 /* The mask used to set the ALT_EMAC_GMAC_WDOG_TMO_WTO register field value. */
15520 #define ALT_EMAC_GMAC_WDOG_TMO_WTO_SET_MSK 0x00003fff
15521 /* The mask used to clear the ALT_EMAC_GMAC_WDOG_TMO_WTO register field value. */
15522 #define ALT_EMAC_GMAC_WDOG_TMO_WTO_CLR_MSK 0xffffc000
15523 /* The reset value of the ALT_EMAC_GMAC_WDOG_TMO_WTO register field. */
15524 #define ALT_EMAC_GMAC_WDOG_TMO_WTO_RESET 0x0
15525 /* Extracts the ALT_EMAC_GMAC_WDOG_TMO_WTO field value from a register. */
15526 #define ALT_EMAC_GMAC_WDOG_TMO_WTO_GET(value) (((value) & 0x00003fff) >> 0)
15527 /* Produces a ALT_EMAC_GMAC_WDOG_TMO_WTO register field value suitable for setting the register. */
15528 #define ALT_EMAC_GMAC_WDOG_TMO_WTO_SET(value) (((value) << 0) & 0x00003fff)
15529 
15530 /*
15531  * Field : reserved_15_14
15532  *
15533  * Reserved
15534  *
15535  * Field Access Macros:
15536  *
15537  */
15538 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14 register field. */
15539 #define ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_LSB 14
15540 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14 register field. */
15541 #define ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_MSB 15
15542 /* The width in bits of the ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14 register field. */
15543 #define ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_WIDTH 2
15544 /* The mask used to set the ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14 register field value. */
15545 #define ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_SET_MSK 0x0000c000
15546 /* The mask used to clear the ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14 register field value. */
15547 #define ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_CLR_MSK 0xffff3fff
15548 /* The reset value of the ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14 register field. */
15549 #define ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_RESET 0x0
15550 /* Extracts the ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14 field value from a register. */
15551 #define ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_GET(value) (((value) & 0x0000c000) >> 14)
15552 /* Produces a ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14 register field value suitable for setting the register. */
15553 #define ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_SET(value) (((value) << 14) & 0x0000c000)
15554 
15555 /*
15556  * Field : pwe
15557  *
15558  * Programmable Watchdog Enable
15559  *
15560  * When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register)
15561  * is reset, the WTO field (Bits[13:0]) is used as watchdog timeout for a received
15562  * frame.
15563  *
15564  * When this bit is cleared, the watchdog timeout for a received frame is
15565  * controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC
15566  * Configuration Register).
15567  *
15568  * Field Access Macros:
15569  *
15570  */
15571 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_WDOG_TMO_PWE register field. */
15572 #define ALT_EMAC_GMAC_WDOG_TMO_PWE_LSB 16
15573 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_WDOG_TMO_PWE register field. */
15574 #define ALT_EMAC_GMAC_WDOG_TMO_PWE_MSB 16
15575 /* The width in bits of the ALT_EMAC_GMAC_WDOG_TMO_PWE register field. */
15576 #define ALT_EMAC_GMAC_WDOG_TMO_PWE_WIDTH 1
15577 /* The mask used to set the ALT_EMAC_GMAC_WDOG_TMO_PWE register field value. */
15578 #define ALT_EMAC_GMAC_WDOG_TMO_PWE_SET_MSK 0x00010000
15579 /* The mask used to clear the ALT_EMAC_GMAC_WDOG_TMO_PWE register field value. */
15580 #define ALT_EMAC_GMAC_WDOG_TMO_PWE_CLR_MSK 0xfffeffff
15581 /* The reset value of the ALT_EMAC_GMAC_WDOG_TMO_PWE register field. */
15582 #define ALT_EMAC_GMAC_WDOG_TMO_PWE_RESET 0x0
15583 /* Extracts the ALT_EMAC_GMAC_WDOG_TMO_PWE field value from a register. */
15584 #define ALT_EMAC_GMAC_WDOG_TMO_PWE_GET(value) (((value) & 0x00010000) >> 16)
15585 /* Produces a ALT_EMAC_GMAC_WDOG_TMO_PWE register field value suitable for setting the register. */
15586 #define ALT_EMAC_GMAC_WDOG_TMO_PWE_SET(value) (((value) << 16) & 0x00010000)
15587 
15588 /*
15589  * Field : reserved_31_17
15590  *
15591  * Reserved
15592  *
15593  * Field Access Macros:
15594  *
15595  */
15596 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17 register field. */
15597 #define ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_LSB 17
15598 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17 register field. */
15599 #define ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_MSB 31
15600 /* The width in bits of the ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17 register field. */
15601 #define ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_WIDTH 15
15602 /* The mask used to set the ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17 register field value. */
15603 #define ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_SET_MSK 0xfffe0000
15604 /* The mask used to clear the ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17 register field value. */
15605 #define ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_CLR_MSK 0x0001ffff
15606 /* The reset value of the ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17 register field. */
15607 #define ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_RESET 0x0
15608 /* Extracts the ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17 field value from a register. */
15609 #define ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_GET(value) (((value) & 0xfffe0000) >> 17)
15610 /* Produces a ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17 register field value suitable for setting the register. */
15611 #define ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_SET(value) (((value) << 17) & 0xfffe0000)
15612 
15613 #ifndef __ASSEMBLY__
15614 /*
15615  * WARNING: The C register and register group struct declarations are provided for
15616  * convenience and illustrative purposes. They should, however, be used with
15617  * caution as the C language standard provides no guarantees about the alignment or
15618  * atomicity of device memory accesses. The recommended practice for writing
15619  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15620  * alt_write_word() functions.
15621  *
15622  * The struct declaration for register ALT_EMAC_GMAC_WDOG_TMO.
15623  */
15624 struct ALT_EMAC_GMAC_WDOG_TMO_s
15625 {
15626  uint32_t wto : 14; /* ALT_EMAC_GMAC_WDOG_TMO_WTO */
15627  const uint32_t reserved_15_14 : 2; /* ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14 */
15628  uint32_t pwe : 1; /* ALT_EMAC_GMAC_WDOG_TMO_PWE */
15629  const uint32_t reserved_31_17 : 15; /* ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17 */
15630 };
15631 
15632 /* The typedef declaration for register ALT_EMAC_GMAC_WDOG_TMO. */
15633 typedef volatile struct ALT_EMAC_GMAC_WDOG_TMO_s ALT_EMAC_GMAC_WDOG_TMO_t;
15634 #endif /* __ASSEMBLY__ */
15635 
15636 /* The reset value of the ALT_EMAC_GMAC_WDOG_TMO register. */
15637 #define ALT_EMAC_GMAC_WDOG_TMO_RESET 0x00000000
15638 /* The byte offset of the ALT_EMAC_GMAC_WDOG_TMO register from the beginning of the component. */
15639 #define ALT_EMAC_GMAC_WDOG_TMO_OFST 0xdc
15640 /* The address of the ALT_EMAC_GMAC_WDOG_TMO register. */
15641 #define ALT_EMAC_GMAC_WDOG_TMO_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_WDOG_TMO_OFST))
15642 
15643 /*
15644  * Register : gmacgrp_genpio
15645  *
15646  * <b> Register 56 (General Purpose IO Register) </b>
15647  *
15648  * This register provides the control to drive up to 4 bits of output ports (GPO)
15649  * and the status of up to 4 input
15650  *
15651  * ports (GPIS). It also provides the control to generate interrupts on events
15652  * occurring on the gpi_i pin.
15653  *
15654  * Register Layout
15655  *
15656  * Bits | Access | Reset | Description
15657  * :--------|:-------|:------|:-------------------------------
15658  * [0] | R | 0x0 | ALT_EMAC_GMAC_GENPIO_GPIS
15659  * [7:1] | R | 0x0 | ALT_EMAC_GMAC_GENPIO_RSVD_7_X
15660  * [8] | RW | 0x0 | ALT_EMAC_GMAC_GENPIO_GPO
15661  * [15:9] | R | 0x0 | ALT_EMAC_GMAC_GENPIO_RSVD_15_X
15662  * [16] | RW | 0x0 | ALT_EMAC_GMAC_GENPIO_GPIE
15663  * [23:17] | R | 0x0 | ALT_EMAC_GMAC_GENPIO_RSVD_23_X
15664  * [24] | RW | 0x0 | ALT_EMAC_GMAC_GENPIO_GPIT
15665  * [31:25] | R | 0x0 | ALT_EMAC_GMAC_GENPIO_RSVD_31_X
15666  *
15667  */
15668 /*
15669  * Field : gpis
15670  *
15671  * General Purpose Input Status
15672  *
15673  * This field gives the status of the signals connected to the gpi_i input ports.
15674  * This field is of the following types based on the setting of the corresponding
15675  * GPIT field of this register:
15676  *
15677  * * Latched-low (LL): This field is cleared when the corresponding gpi_i input
15678  * becomes low. This field remains low until the host reads this field. After
15679  * this, this field reflects the current value of the gpi_i input.
15680  *
15681  * * Latched-high (LH): This field is set when the corresponding gpi_i input
15682  * becomes high. This field remains high until the host reads this field. After
15683  * this, this field reflects the current value of the gpi_i input.
15684  *
15685  * <br>
15686  *
15687  * The number of bits available in this field depend on the GP Input Signal Width
15688  * option. Other bits are not used (reserved and always reset).
15689  *
15690  * Field Access Macros:
15691  *
15692  */
15693 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GENPIO_GPIS register field. */
15694 #define ALT_EMAC_GMAC_GENPIO_GPIS_LSB 0
15695 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GENPIO_GPIS register field. */
15696 #define ALT_EMAC_GMAC_GENPIO_GPIS_MSB 0
15697 /* The width in bits of the ALT_EMAC_GMAC_GENPIO_GPIS register field. */
15698 #define ALT_EMAC_GMAC_GENPIO_GPIS_WIDTH 1
15699 /* The mask used to set the ALT_EMAC_GMAC_GENPIO_GPIS register field value. */
15700 #define ALT_EMAC_GMAC_GENPIO_GPIS_SET_MSK 0x00000001
15701 /* The mask used to clear the ALT_EMAC_GMAC_GENPIO_GPIS register field value. */
15702 #define ALT_EMAC_GMAC_GENPIO_GPIS_CLR_MSK 0xfffffffe
15703 /* The reset value of the ALT_EMAC_GMAC_GENPIO_GPIS register field. */
15704 #define ALT_EMAC_GMAC_GENPIO_GPIS_RESET 0x0
15705 /* Extracts the ALT_EMAC_GMAC_GENPIO_GPIS field value from a register. */
15706 #define ALT_EMAC_GMAC_GENPIO_GPIS_GET(value) (((value) & 0x00000001) >> 0)
15707 /* Produces a ALT_EMAC_GMAC_GENPIO_GPIS register field value suitable for setting the register. */
15708 #define ALT_EMAC_GMAC_GENPIO_GPIS_SET(value) (((value) << 0) & 0x00000001)
15709 
15710 /*
15711  * Field : reserved_7_x
15712  *
15713  * Reserved
15714  *
15715  * Field Access Macros:
15716  *
15717  */
15718 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GENPIO_RSVD_7_X register field. */
15719 #define ALT_EMAC_GMAC_GENPIO_RSVD_7_X_LSB 1
15720 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GENPIO_RSVD_7_X register field. */
15721 #define ALT_EMAC_GMAC_GENPIO_RSVD_7_X_MSB 7
15722 /* The width in bits of the ALT_EMAC_GMAC_GENPIO_RSVD_7_X register field. */
15723 #define ALT_EMAC_GMAC_GENPIO_RSVD_7_X_WIDTH 7
15724 /* The mask used to set the ALT_EMAC_GMAC_GENPIO_RSVD_7_X register field value. */
15725 #define ALT_EMAC_GMAC_GENPIO_RSVD_7_X_SET_MSK 0x000000fe
15726 /* The mask used to clear the ALT_EMAC_GMAC_GENPIO_RSVD_7_X register field value. */
15727 #define ALT_EMAC_GMAC_GENPIO_RSVD_7_X_CLR_MSK 0xffffff01
15728 /* The reset value of the ALT_EMAC_GMAC_GENPIO_RSVD_7_X register field. */
15729 #define ALT_EMAC_GMAC_GENPIO_RSVD_7_X_RESET 0x0
15730 /* Extracts the ALT_EMAC_GMAC_GENPIO_RSVD_7_X field value from a register. */
15731 #define ALT_EMAC_GMAC_GENPIO_RSVD_7_X_GET(value) (((value) & 0x000000fe) >> 1)
15732 /* Produces a ALT_EMAC_GMAC_GENPIO_RSVD_7_X register field value suitable for setting the register. */
15733 #define ALT_EMAC_GMAC_GENPIO_RSVD_7_X_SET(value) (((value) << 1) & 0x000000fe)
15734 
15735 /*
15736  * Field : gpo
15737  *
15738  * General Purpose Output
15739  *
15740  * When this bit is set, it directly drives the gpo_o output ports. When this bit
15741  * is reset, it does not directly drive the gpo_o output ports.
15742  *
15743  * The number of bits available in this field depend on the GP Output Signal Width
15744  * option. Other bits are not used (reserved and always reset).
15745  *
15746  * Field Access Macros:
15747  *
15748  */
15749 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GENPIO_GPO register field. */
15750 #define ALT_EMAC_GMAC_GENPIO_GPO_LSB 8
15751 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GENPIO_GPO register field. */
15752 #define ALT_EMAC_GMAC_GENPIO_GPO_MSB 8
15753 /* The width in bits of the ALT_EMAC_GMAC_GENPIO_GPO register field. */
15754 #define ALT_EMAC_GMAC_GENPIO_GPO_WIDTH 1
15755 /* The mask used to set the ALT_EMAC_GMAC_GENPIO_GPO register field value. */
15756 #define ALT_EMAC_GMAC_GENPIO_GPO_SET_MSK 0x00000100
15757 /* The mask used to clear the ALT_EMAC_GMAC_GENPIO_GPO register field value. */
15758 #define ALT_EMAC_GMAC_GENPIO_GPO_CLR_MSK 0xfffffeff
15759 /* The reset value of the ALT_EMAC_GMAC_GENPIO_GPO register field. */
15760 #define ALT_EMAC_GMAC_GENPIO_GPO_RESET 0x0
15761 /* Extracts the ALT_EMAC_GMAC_GENPIO_GPO field value from a register. */
15762 #define ALT_EMAC_GMAC_GENPIO_GPO_GET(value) (((value) & 0x00000100) >> 8)
15763 /* Produces a ALT_EMAC_GMAC_GENPIO_GPO register field value suitable for setting the register. */
15764 #define ALT_EMAC_GMAC_GENPIO_GPO_SET(value) (((value) << 8) & 0x00000100)
15765 
15766 /*
15767  * Field : reserved_15_x
15768  *
15769  * Reserved
15770  *
15771  * Field Access Macros:
15772  *
15773  */
15774 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GENPIO_RSVD_15_X register field. */
15775 #define ALT_EMAC_GMAC_GENPIO_RSVD_15_X_LSB 9
15776 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GENPIO_RSVD_15_X register field. */
15777 #define ALT_EMAC_GMAC_GENPIO_RSVD_15_X_MSB 15
15778 /* The width in bits of the ALT_EMAC_GMAC_GENPIO_RSVD_15_X register field. */
15779 #define ALT_EMAC_GMAC_GENPIO_RSVD_15_X_WIDTH 7
15780 /* The mask used to set the ALT_EMAC_GMAC_GENPIO_RSVD_15_X register field value. */
15781 #define ALT_EMAC_GMAC_GENPIO_RSVD_15_X_SET_MSK 0x0000fe00
15782 /* The mask used to clear the ALT_EMAC_GMAC_GENPIO_RSVD_15_X register field value. */
15783 #define ALT_EMAC_GMAC_GENPIO_RSVD_15_X_CLR_MSK 0xffff01ff
15784 /* The reset value of the ALT_EMAC_GMAC_GENPIO_RSVD_15_X register field. */
15785 #define ALT_EMAC_GMAC_GENPIO_RSVD_15_X_RESET 0x0
15786 /* Extracts the ALT_EMAC_GMAC_GENPIO_RSVD_15_X field value from a register. */
15787 #define ALT_EMAC_GMAC_GENPIO_RSVD_15_X_GET(value) (((value) & 0x0000fe00) >> 9)
15788 /* Produces a ALT_EMAC_GMAC_GENPIO_RSVD_15_X register field value suitable for setting the register. */
15789 #define ALT_EMAC_GMAC_GENPIO_RSVD_15_X_SET(value) (((value) << 9) & 0x0000fe00)
15790 
15791 /*
15792  * Field : gpie
15793  *
15794  * GPI Interrupt Enable
15795  *
15796  * When this bit is set and the programmed event (LL or LH) occurs on the
15797  * corresponding GPIS bit, Bit 11 (GPIIS) of Register 14 (Interrupt Status
15798  * Register) is set. Accordingly, the interrupt is generated on the mci_intr_o or
15799  * sbd_intr_o. The GPIIS bit is cleared when the host reads the Bits[7:0] of this
15800  * register.
15801  *
15802  * When reset, Bit 11 (GPIIS) of Register 14 (Interrupt Status Register) is not set
15803  * when any event occurs on the corresponding GPIS bits.
15804  *
15805  * The number of bits available in this field depend on the GP Input Signal Width
15806  * option. Other bits are not used (reserved and always reset).
15807  *
15808  * Field Access Macros:
15809  *
15810  */
15811 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GENPIO_GPIE register field. */
15812 #define ALT_EMAC_GMAC_GENPIO_GPIE_LSB 16
15813 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GENPIO_GPIE register field. */
15814 #define ALT_EMAC_GMAC_GENPIO_GPIE_MSB 16
15815 /* The width in bits of the ALT_EMAC_GMAC_GENPIO_GPIE register field. */
15816 #define ALT_EMAC_GMAC_GENPIO_GPIE_WIDTH 1
15817 /* The mask used to set the ALT_EMAC_GMAC_GENPIO_GPIE register field value. */
15818 #define ALT_EMAC_GMAC_GENPIO_GPIE_SET_MSK 0x00010000
15819 /* The mask used to clear the ALT_EMAC_GMAC_GENPIO_GPIE register field value. */
15820 #define ALT_EMAC_GMAC_GENPIO_GPIE_CLR_MSK 0xfffeffff
15821 /* The reset value of the ALT_EMAC_GMAC_GENPIO_GPIE register field. */
15822 #define ALT_EMAC_GMAC_GENPIO_GPIE_RESET 0x0
15823 /* Extracts the ALT_EMAC_GMAC_GENPIO_GPIE field value from a register. */
15824 #define ALT_EMAC_GMAC_GENPIO_GPIE_GET(value) (((value) & 0x00010000) >> 16)
15825 /* Produces a ALT_EMAC_GMAC_GENPIO_GPIE register field value suitable for setting the register. */
15826 #define ALT_EMAC_GMAC_GENPIO_GPIE_SET(value) (((value) << 16) & 0x00010000)
15827 
15828 /*
15829  * Field : reserved_23_x
15830  *
15831  * Reserved
15832  *
15833  * Field Access Macros:
15834  *
15835  */
15836 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GENPIO_RSVD_23_X register field. */
15837 #define ALT_EMAC_GMAC_GENPIO_RSVD_23_X_LSB 17
15838 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GENPIO_RSVD_23_X register field. */
15839 #define ALT_EMAC_GMAC_GENPIO_RSVD_23_X_MSB 23
15840 /* The width in bits of the ALT_EMAC_GMAC_GENPIO_RSVD_23_X register field. */
15841 #define ALT_EMAC_GMAC_GENPIO_RSVD_23_X_WIDTH 7
15842 /* The mask used to set the ALT_EMAC_GMAC_GENPIO_RSVD_23_X register field value. */
15843 #define ALT_EMAC_GMAC_GENPIO_RSVD_23_X_SET_MSK 0x00fe0000
15844 /* The mask used to clear the ALT_EMAC_GMAC_GENPIO_RSVD_23_X register field value. */
15845 #define ALT_EMAC_GMAC_GENPIO_RSVD_23_X_CLR_MSK 0xff01ffff
15846 /* The reset value of the ALT_EMAC_GMAC_GENPIO_RSVD_23_X register field. */
15847 #define ALT_EMAC_GMAC_GENPIO_RSVD_23_X_RESET 0x0
15848 /* Extracts the ALT_EMAC_GMAC_GENPIO_RSVD_23_X field value from a register. */
15849 #define ALT_EMAC_GMAC_GENPIO_RSVD_23_X_GET(value) (((value) & 0x00fe0000) >> 17)
15850 /* Produces a ALT_EMAC_GMAC_GENPIO_RSVD_23_X register field value suitable for setting the register. */
15851 #define ALT_EMAC_GMAC_GENPIO_RSVD_23_X_SET(value) (((value) << 17) & 0x00fe0000)
15852 
15853 /*
15854  * Field : gpit
15855  *
15856  * GPI Type
15857  *
15858  * When set, this bit indicates that the corresponding GPIS is of latched-low (LL)
15859  * type. When reset, this bit indicates that the corresponding GPIS is of latched-
15860  * high (LH) type.
15861  *
15862  * The number of bits available in this field depend on the GP Input Signal Width
15863  * option. Other bits are not used (reserved and always reset).
15864  *
15865  * Field Access Macros:
15866  *
15867  */
15868 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GENPIO_GPIT register field. */
15869 #define ALT_EMAC_GMAC_GENPIO_GPIT_LSB 24
15870 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GENPIO_GPIT register field. */
15871 #define ALT_EMAC_GMAC_GENPIO_GPIT_MSB 24
15872 /* The width in bits of the ALT_EMAC_GMAC_GENPIO_GPIT register field. */
15873 #define ALT_EMAC_GMAC_GENPIO_GPIT_WIDTH 1
15874 /* The mask used to set the ALT_EMAC_GMAC_GENPIO_GPIT register field value. */
15875 #define ALT_EMAC_GMAC_GENPIO_GPIT_SET_MSK 0x01000000
15876 /* The mask used to clear the ALT_EMAC_GMAC_GENPIO_GPIT register field value. */
15877 #define ALT_EMAC_GMAC_GENPIO_GPIT_CLR_MSK 0xfeffffff
15878 /* The reset value of the ALT_EMAC_GMAC_GENPIO_GPIT register field. */
15879 #define ALT_EMAC_GMAC_GENPIO_GPIT_RESET 0x0
15880 /* Extracts the ALT_EMAC_GMAC_GENPIO_GPIT field value from a register. */
15881 #define ALT_EMAC_GMAC_GENPIO_GPIT_GET(value) (((value) & 0x01000000) >> 24)
15882 /* Produces a ALT_EMAC_GMAC_GENPIO_GPIT register field value suitable for setting the register. */
15883 #define ALT_EMAC_GMAC_GENPIO_GPIT_SET(value) (((value) << 24) & 0x01000000)
15884 
15885 /*
15886  * Field : reserved_31_x
15887  *
15888  * Reserved
15889  *
15890  * Field Access Macros:
15891  *
15892  */
15893 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GENPIO_RSVD_31_X register field. */
15894 #define ALT_EMAC_GMAC_GENPIO_RSVD_31_X_LSB 25
15895 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GENPIO_RSVD_31_X register field. */
15896 #define ALT_EMAC_GMAC_GENPIO_RSVD_31_X_MSB 31
15897 /* The width in bits of the ALT_EMAC_GMAC_GENPIO_RSVD_31_X register field. */
15898 #define ALT_EMAC_GMAC_GENPIO_RSVD_31_X_WIDTH 7
15899 /* The mask used to set the ALT_EMAC_GMAC_GENPIO_RSVD_31_X register field value. */
15900 #define ALT_EMAC_GMAC_GENPIO_RSVD_31_X_SET_MSK 0xfe000000
15901 /* The mask used to clear the ALT_EMAC_GMAC_GENPIO_RSVD_31_X register field value. */
15902 #define ALT_EMAC_GMAC_GENPIO_RSVD_31_X_CLR_MSK 0x01ffffff
15903 /* The reset value of the ALT_EMAC_GMAC_GENPIO_RSVD_31_X register field. */
15904 #define ALT_EMAC_GMAC_GENPIO_RSVD_31_X_RESET 0x0
15905 /* Extracts the ALT_EMAC_GMAC_GENPIO_RSVD_31_X field value from a register. */
15906 #define ALT_EMAC_GMAC_GENPIO_RSVD_31_X_GET(value) (((value) & 0xfe000000) >> 25)
15907 /* Produces a ALT_EMAC_GMAC_GENPIO_RSVD_31_X register field value suitable for setting the register. */
15908 #define ALT_EMAC_GMAC_GENPIO_RSVD_31_X_SET(value) (((value) << 25) & 0xfe000000)
15909 
15910 #ifndef __ASSEMBLY__
15911 /*
15912  * WARNING: The C register and register group struct declarations are provided for
15913  * convenience and illustrative purposes. They should, however, be used with
15914  * caution as the C language standard provides no guarantees about the alignment or
15915  * atomicity of device memory accesses. The recommended practice for writing
15916  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15917  * alt_write_word() functions.
15918  *
15919  * The struct declaration for register ALT_EMAC_GMAC_GENPIO.
15920  */
15921 struct ALT_EMAC_GMAC_GENPIO_s
15922 {
15923  const uint32_t gpis : 1; /* ALT_EMAC_GMAC_GENPIO_GPIS */
15924  const uint32_t reserved_7_x : 7; /* ALT_EMAC_GMAC_GENPIO_RSVD_7_X */
15925  uint32_t gpo : 1; /* ALT_EMAC_GMAC_GENPIO_GPO */
15926  const uint32_t reserved_15_x : 7; /* ALT_EMAC_GMAC_GENPIO_RSVD_15_X */
15927  uint32_t gpie : 1; /* ALT_EMAC_GMAC_GENPIO_GPIE */
15928  const uint32_t reserved_23_x : 7; /* ALT_EMAC_GMAC_GENPIO_RSVD_23_X */
15929  uint32_t gpit : 1; /* ALT_EMAC_GMAC_GENPIO_GPIT */
15930  const uint32_t reserved_31_x : 7; /* ALT_EMAC_GMAC_GENPIO_RSVD_31_X */
15931 };
15932 
15933 /* The typedef declaration for register ALT_EMAC_GMAC_GENPIO. */
15934 typedef volatile struct ALT_EMAC_GMAC_GENPIO_s ALT_EMAC_GMAC_GENPIO_t;
15935 #endif /* __ASSEMBLY__ */
15936 
15937 /* The reset value of the ALT_EMAC_GMAC_GENPIO register. */
15938 #define ALT_EMAC_GMAC_GENPIO_RESET 0x00000000
15939 /* The byte offset of the ALT_EMAC_GMAC_GENPIO register from the beginning of the component. */
15940 #define ALT_EMAC_GMAC_GENPIO_OFST 0xe0
15941 /* The address of the ALT_EMAC_GMAC_GENPIO register. */
15942 #define ALT_EMAC_GMAC_GENPIO_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_GENPIO_OFST))
15943 
15944 /*
15945  * Register : gmacgrp_mmc_control
15946  *
15947  * <b> Register 64 (MMC Control Register) </b>
15948  *
15949  * The MMC Control register establishes the operating mode of the management
15950  * counters.
15951  *
15952  * Note:
15953  *
15954  * The bit 0 (Counters Reset) has higher priority than bit 4 (Counter Preset).
15955  * Therefore, when the Software tries to set both bits in the same write cycle, all
15956  * counters are cleared and the bit 4 is not set.
15957  *
15958  * Register Layout
15959  *
15960  * Bits | Access | Reset | Description
15961  * :-------|:-------|:------|:---------------------------------
15962  * [0] | RW | 0x0 | ALT_EMAC_GMAC_MMC_CTL_CNTRST
15963  * [1] | RW | 0x0 | ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO
15964  * [2] | RW | 0x0 | ALT_EMAC_GMAC_MMC_CTL_RSTONRD
15965  * [3] | RW | 0x0 | ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ
15966  * [4] | RW | 0x0 | ALT_EMAC_GMAC_MMC_CTL_CNTPRST
15967  * [5] | RW | 0x0 | ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL
15968  * [7:6] | R | 0x0 | ALT_EMAC_GMAC_MMC_CTL_RSVD_7_6
15969  * [8] | RW | 0x0 | ALT_EMAC_GMAC_MMC_CTL_UCDBC
15970  * [31:9] | R | 0x0 | ALT_EMAC_GMAC_MMC_CTL_RSVD_31_9
15971  *
15972  */
15973 /*
15974  * Field : cntrst
15975  *
15976  * Counters Reset
15977  *
15978  * When this bit is set, all counters are reset. This bit is cleared automatically
15979  * after one clock cycle.
15980  *
15981  * Field Enumeration Values:
15982  *
15983  * Enum | Value | Description
15984  * :------------------------------------|:------|:------------
15985  * ALT_EMAC_GMAC_MMC_CTL_CNTRST_E_DISD | 0x0 |
15986  * ALT_EMAC_GMAC_MMC_CTL_CNTRST_E_END | 0x1 |
15987  *
15988  * Field Access Macros:
15989  *
15990  */
15991 /*
15992  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTRST
15993  *
15994  */
15995 #define ALT_EMAC_GMAC_MMC_CTL_CNTRST_E_DISD 0x0
15996 /*
15997  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTRST
15998  *
15999  */
16000 #define ALT_EMAC_GMAC_MMC_CTL_CNTRST_E_END 0x1
16001 
16002 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field. */
16003 #define ALT_EMAC_GMAC_MMC_CTL_CNTRST_LSB 0
16004 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field. */
16005 #define ALT_EMAC_GMAC_MMC_CTL_CNTRST_MSB 0
16006 /* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field. */
16007 #define ALT_EMAC_GMAC_MMC_CTL_CNTRST_WIDTH 1
16008 /* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field value. */
16009 #define ALT_EMAC_GMAC_MMC_CTL_CNTRST_SET_MSK 0x00000001
16010 /* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field value. */
16011 #define ALT_EMAC_GMAC_MMC_CTL_CNTRST_CLR_MSK 0xfffffffe
16012 /* The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field. */
16013 #define ALT_EMAC_GMAC_MMC_CTL_CNTRST_RESET 0x0
16014 /* Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTRST field value from a register. */
16015 #define ALT_EMAC_GMAC_MMC_CTL_CNTRST_GET(value) (((value) & 0x00000001) >> 0)
16016 /* Produces a ALT_EMAC_GMAC_MMC_CTL_CNTRST register field value suitable for setting the register. */
16017 #define ALT_EMAC_GMAC_MMC_CTL_CNTRST_SET(value) (((value) << 0) & 0x00000001)
16018 
16019 /*
16020  * Field : cntstopro
16021  *
16022  * Counters Stop Rollover
16023  *
16024  * When this bit is set, after reaching maximum value, the counter does not roll
16025  * over to zero.
16026  *
16027  * Field Enumeration Values:
16028  *
16029  * Enum | Value | Description
16030  * :---------------------------------------|:------|:------------
16031  * ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_E_DISD | 0x0 |
16032  * ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_E_END | 0x1 |
16033  *
16034  * Field Access Macros:
16035  *
16036  */
16037 /*
16038  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO
16039  *
16040  */
16041 #define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_E_DISD 0x0
16042 /*
16043  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO
16044  *
16045  */
16046 #define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_E_END 0x1
16047 
16048 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field. */
16049 #define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_LSB 1
16050 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field. */
16051 #define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_MSB 1
16052 /* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field. */
16053 #define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_WIDTH 1
16054 /* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field value. */
16055 #define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_SET_MSK 0x00000002
16056 /* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field value. */
16057 #define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_CLR_MSK 0xfffffffd
16058 /* The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field. */
16059 #define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_RESET 0x0
16060 /* Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO field value from a register. */
16061 #define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_GET(value) (((value) & 0x00000002) >> 1)
16062 /* Produces a ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field value suitable for setting the register. */
16063 #define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_SET(value) (((value) << 1) & 0x00000002)
16064 
16065 /*
16066  * Field : rstonrd
16067  *
16068  * Reset on Read
16069  *
16070  * When this bit is set, the MMC counters are reset to zero after Read (self-
16071  * clearing after reset). The counters are cleared when the least significant byte
16072  * lane (bits[7:0]) is read.
16073  *
16074  * Field Enumeration Values:
16075  *
16076  * Enum | Value | Description
16077  * :-------------------------------------|:------|:------------
16078  * ALT_EMAC_GMAC_MMC_CTL_RSTONRD_E_DISD | 0x0 |
16079  * ALT_EMAC_GMAC_MMC_CTL_RSTONRD_E_END | 0x1 |
16080  *
16081  * Field Access Macros:
16082  *
16083  */
16084 /*
16085  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_RSTONRD
16086  *
16087  */
16088 #define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_E_DISD 0x0
16089 /*
16090  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_RSTONRD
16091  *
16092  */
16093 #define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_E_END 0x1
16094 
16095 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field. */
16096 #define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_LSB 2
16097 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field. */
16098 #define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_MSB 2
16099 /* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field. */
16100 #define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_WIDTH 1
16101 /* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field value. */
16102 #define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_SET_MSK 0x00000004
16103 /* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field value. */
16104 #define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_CLR_MSK 0xfffffffb
16105 /* The reset value of the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field. */
16106 #define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_RESET 0x0
16107 /* Extracts the ALT_EMAC_GMAC_MMC_CTL_RSTONRD field value from a register. */
16108 #define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_GET(value) (((value) & 0x00000004) >> 2)
16109 /* Produces a ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field value suitable for setting the register. */
16110 #define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_SET(value) (((value) << 2) & 0x00000004)
16111 
16112 /*
16113  * Field : cntfreez
16114  *
16115  * MMC Counter Freeze
16116  *
16117  * When this bit is set, it freezes all MMC counters to their current value. Until
16118  * this bit is reset to 0, no MMC counter is updated because of any transmitted or
16119  * received frame. If any MMC counter is read with the Reset on Read bit set, then
16120  * that counter is also cleared in this mode.
16121  *
16122  * Field Enumeration Values:
16123  *
16124  * Enum | Value | Description
16125  * :--------------------------------------|:------|:------------
16126  * ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_E_DISD | 0x0 |
16127  * ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_E_END | 0x1 |
16128  *
16129  * Field Access Macros:
16130  *
16131  */
16132 /*
16133  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ
16134  *
16135  */
16136 #define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_E_DISD 0x0
16137 /*
16138  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ
16139  *
16140  */
16141 #define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_E_END 0x1
16142 
16143 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field. */
16144 #define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_LSB 3
16145 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field. */
16146 #define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_MSB 3
16147 /* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field. */
16148 #define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_WIDTH 1
16149 /* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field value. */
16150 #define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_SET_MSK 0x00000008
16151 /* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field value. */
16152 #define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_CLR_MSK 0xfffffff7
16153 /* The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field. */
16154 #define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_RESET 0x0
16155 /* Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ field value from a register. */
16156 #define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_GET(value) (((value) & 0x00000008) >> 3)
16157 /* Produces a ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field value suitable for setting the register. */
16158 #define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_SET(value) (((value) << 3) & 0x00000008)
16159 
16160 /*
16161  * Field : cntprst
16162  *
16163  * Counters Preset
16164  *
16165  * When this bit is set, all counters are initialized or preset to almost full or
16166  * almost half according to bit 5. This bit is cleared automatically after 1 clock
16167  * cycle. This bit, along with bit 5, is useful for debugging and testing the
16168  * assertion of interrupts because of MMC counter becoming half-full or full.
16169  *
16170  * Field Enumeration Values:
16171  *
16172  * Enum | Value | Description
16173  * :-------------------------------------|:------|:------------
16174  * ALT_EMAC_GMAC_MMC_CTL_CNTPRST_E_DISD | 0x0 |
16175  * ALT_EMAC_GMAC_MMC_CTL_CNTPRST_E_END | 0x1 |
16176  *
16177  * Field Access Macros:
16178  *
16179  */
16180 /*
16181  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTPRST
16182  *
16183  */
16184 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_E_DISD 0x0
16185 /*
16186  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTPRST
16187  *
16188  */
16189 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_E_END 0x1
16190 
16191 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field. */
16192 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_LSB 4
16193 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field. */
16194 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_MSB 4
16195 /* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field. */
16196 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_WIDTH 1
16197 /* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field value. */
16198 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_SET_MSK 0x00000010
16199 /* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field value. */
16200 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_CLR_MSK 0xffffffef
16201 /* The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field. */
16202 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_RESET 0x0
16203 /* Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTPRST field value from a register. */
16204 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_GET(value) (((value) & 0x00000010) >> 4)
16205 /* Produces a ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field value suitable for setting the register. */
16206 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_SET(value) (((value) << 4) & 0x00000010)
16207 
16208 /*
16209  * Field : cntprstlvl
16210  *
16211  * Full-Half Preset
16212  *
16213  * When low and bit 4 is set, all MMC counters get preset to almost-half value. All
16214  * octet counters get preset to 0x7FFF_F800 (half - 2KBytes) and all frame-counters
16215  * gets preset to 0x7FFF_FFF0 (half - 16).
16216  *
16217  * When this bit is high and bit 4 is set, all MMC counters get preset to almost-
16218  * full value. All octet counters get preset to 0xFFFF_F800 (full - 2KBytes) and
16219  * all frame-counters gets preset to 0xFFFF_FFF0 (full - 16).
16220  *
16221  * For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the
16222  * respective octet and frame counters. Similarly, the almost-full preset values
16223  * for the 16-bit counters are 0xF800 and 0xFFF0.
16224  *
16225  * Field Enumeration Values:
16226  *
16227  * Enum | Value | Description
16228  * :----------------------------------------------|:------|:------------
16229  * ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_E_ALMOSTHALF | 0x0 |
16230  * ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_E_ALMOSTFULL | 0x1 |
16231  *
16232  * Field Access Macros:
16233  *
16234  */
16235 /*
16236  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL
16237  *
16238  */
16239 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_E_ALMOSTHALF 0x0
16240 /*
16241  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL
16242  *
16243  */
16244 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_E_ALMOSTFULL 0x1
16245 
16246 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field. */
16247 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_LSB 5
16248 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field. */
16249 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_MSB 5
16250 /* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field. */
16251 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_WIDTH 1
16252 /* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field value. */
16253 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_SET_MSK 0x00000020
16254 /* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field value. */
16255 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_CLR_MSK 0xffffffdf
16256 /* The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field. */
16257 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_RESET 0x0
16258 /* Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL field value from a register. */
16259 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_GET(value) (((value) & 0x00000020) >> 5)
16260 /* Produces a ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field value suitable for setting the register. */
16261 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_SET(value) (((value) << 5) & 0x00000020)
16262 
16263 /*
16264  * Field : reserved_7_6
16265  *
16266  * Reserved
16267  *
16268  * Field Access Macros:
16269  *
16270  */
16271 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_RSVD_7_6 register field. */
16272 #define ALT_EMAC_GMAC_MMC_CTL_RSVD_7_6_LSB 6
16273 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_RSVD_7_6 register field. */
16274 #define ALT_EMAC_GMAC_MMC_CTL_RSVD_7_6_MSB 7
16275 /* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_RSVD_7_6 register field. */
16276 #define ALT_EMAC_GMAC_MMC_CTL_RSVD_7_6_WIDTH 2
16277 /* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_RSVD_7_6 register field value. */
16278 #define ALT_EMAC_GMAC_MMC_CTL_RSVD_7_6_SET_MSK 0x000000c0
16279 /* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_RSVD_7_6 register field value. */
16280 #define ALT_EMAC_GMAC_MMC_CTL_RSVD_7_6_CLR_MSK 0xffffff3f
16281 /* The reset value of the ALT_EMAC_GMAC_MMC_CTL_RSVD_7_6 register field. */
16282 #define ALT_EMAC_GMAC_MMC_CTL_RSVD_7_6_RESET 0x0
16283 /* Extracts the ALT_EMAC_GMAC_MMC_CTL_RSVD_7_6 field value from a register. */
16284 #define ALT_EMAC_GMAC_MMC_CTL_RSVD_7_6_GET(value) (((value) & 0x000000c0) >> 6)
16285 /* Produces a ALT_EMAC_GMAC_MMC_CTL_RSVD_7_6 register field value suitable for setting the register. */
16286 #define ALT_EMAC_GMAC_MMC_CTL_RSVD_7_6_SET(value) (((value) << 6) & 0x000000c0)
16287 
16288 /*
16289  * Field : ucdbc
16290  *
16291  * Update MMC Counters for Dropped Broadcast Frames
16292  *
16293  * When set, this bit enables MAC to update all the related MMC Counters for
16294  * Broadcast frames dropped due to setting of DBF bit (Disable Broadcast Frames) of
16295  * MAC Filter Register at offset 0x0004.
16296  *
16297  * When reset, MMC Counters are not updated for dropped Broadcast frames.
16298  *
16299  * Field Access Macros:
16300  *
16301  */
16302 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field. */
16303 #define ALT_EMAC_GMAC_MMC_CTL_UCDBC_LSB 8
16304 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field. */
16305 #define ALT_EMAC_GMAC_MMC_CTL_UCDBC_MSB 8
16306 /* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field. */
16307 #define ALT_EMAC_GMAC_MMC_CTL_UCDBC_WIDTH 1
16308 /* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field value. */
16309 #define ALT_EMAC_GMAC_MMC_CTL_UCDBC_SET_MSK 0x00000100
16310 /* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field value. */
16311 #define ALT_EMAC_GMAC_MMC_CTL_UCDBC_CLR_MSK 0xfffffeff
16312 /* The reset value of the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field. */
16313 #define ALT_EMAC_GMAC_MMC_CTL_UCDBC_RESET 0x0
16314 /* Extracts the ALT_EMAC_GMAC_MMC_CTL_UCDBC field value from a register. */
16315 #define ALT_EMAC_GMAC_MMC_CTL_UCDBC_GET(value) (((value) & 0x00000100) >> 8)
16316 /* Produces a ALT_EMAC_GMAC_MMC_CTL_UCDBC register field value suitable for setting the register. */
16317 #define ALT_EMAC_GMAC_MMC_CTL_UCDBC_SET(value) (((value) << 8) & 0x00000100)
16318 
16319 /*
16320  * Field : reserved_31_9
16321  *
16322  * Reserved
16323  *
16324  * Field Access Macros:
16325  *
16326  */
16327 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_RSVD_31_9 register field. */
16328 #define ALT_EMAC_GMAC_MMC_CTL_RSVD_31_9_LSB 9
16329 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_RSVD_31_9 register field. */
16330 #define ALT_EMAC_GMAC_MMC_CTL_RSVD_31_9_MSB 31
16331 /* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_RSVD_31_9 register field. */
16332 #define ALT_EMAC_GMAC_MMC_CTL_RSVD_31_9_WIDTH 23
16333 /* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_RSVD_31_9 register field value. */
16334 #define ALT_EMAC_GMAC_MMC_CTL_RSVD_31_9_SET_MSK 0xfffffe00
16335 /* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_RSVD_31_9 register field value. */
16336 #define ALT_EMAC_GMAC_MMC_CTL_RSVD_31_9_CLR_MSK 0x000001ff
16337 /* The reset value of the ALT_EMAC_GMAC_MMC_CTL_RSVD_31_9 register field. */
16338 #define ALT_EMAC_GMAC_MMC_CTL_RSVD_31_9_RESET 0x0
16339 /* Extracts the ALT_EMAC_GMAC_MMC_CTL_RSVD_31_9 field value from a register. */
16340 #define ALT_EMAC_GMAC_MMC_CTL_RSVD_31_9_GET(value) (((value) & 0xfffffe00) >> 9)
16341 /* Produces a ALT_EMAC_GMAC_MMC_CTL_RSVD_31_9 register field value suitable for setting the register. */
16342 #define ALT_EMAC_GMAC_MMC_CTL_RSVD_31_9_SET(value) (((value) << 9) & 0xfffffe00)
16343 
16344 #ifndef __ASSEMBLY__
16345 /*
16346  * WARNING: The C register and register group struct declarations are provided for
16347  * convenience and illustrative purposes. They should, however, be used with
16348  * caution as the C language standard provides no guarantees about the alignment or
16349  * atomicity of device memory accesses. The recommended practice for writing
16350  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16351  * alt_write_word() functions.
16352  *
16353  * The struct declaration for register ALT_EMAC_GMAC_MMC_CTL.
16354  */
16355 struct ALT_EMAC_GMAC_MMC_CTL_s
16356 {
16357  uint32_t cntrst : 1; /* ALT_EMAC_GMAC_MMC_CTL_CNTRST */
16358  uint32_t cntstopro : 1; /* ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO */
16359  uint32_t rstonrd : 1; /* ALT_EMAC_GMAC_MMC_CTL_RSTONRD */
16360  uint32_t cntfreez : 1; /* ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ */
16361  uint32_t cntprst : 1; /* ALT_EMAC_GMAC_MMC_CTL_CNTPRST */
16362  uint32_t cntprstlvl : 1; /* ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL */
16363  const uint32_t reserved_7_6 : 2; /* ALT_EMAC_GMAC_MMC_CTL_RSVD_7_6 */
16364  uint32_t ucdbc : 1; /* ALT_EMAC_GMAC_MMC_CTL_UCDBC */
16365  const uint32_t reserved_31_9 : 23; /* ALT_EMAC_GMAC_MMC_CTL_RSVD_31_9 */
16366 };
16367 
16368 /* The typedef declaration for register ALT_EMAC_GMAC_MMC_CTL. */
16369 typedef volatile struct ALT_EMAC_GMAC_MMC_CTL_s ALT_EMAC_GMAC_MMC_CTL_t;
16370 #endif /* __ASSEMBLY__ */
16371 
16372 /* The reset value of the ALT_EMAC_GMAC_MMC_CTL register. */
16373 #define ALT_EMAC_GMAC_MMC_CTL_RESET 0x00000000
16374 /* The byte offset of the ALT_EMAC_GMAC_MMC_CTL register from the beginning of the component. */
16375 #define ALT_EMAC_GMAC_MMC_CTL_OFST 0x100
16376 /* The address of the ALT_EMAC_GMAC_MMC_CTL register. */
16377 #define ALT_EMAC_GMAC_MMC_CTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_CTL_OFST))
16378 
16379 /*
16380  * Register : gmacgrp_mmc_receive_interrupt
16381  *
16382  * <b> Register 65 (MMC Receive Interrupt Register) </b>
16383  *
16384  * The MMC Receive Interrupt register maintains the interrupts that are generated
16385  * when the following happens:
16386  *
16387  * * Receive statistic counters reach half of their maximum values (0x8000_0000 for
16388  * 32-bit counter and 0x8000 for 16-bit counter).
16389  *
16390  * * Receive statistic counters cross their maximum values (0xFFFF_FFFF for 32-bit
16391  * counter and 0xFFFF for 16-bit counter).
16392  *
16393  * When the Counter Stop Rollover is set, then interrupts are set but the counter
16394  * remains at all-ones. The MMC Receive Interrupt register is a 32-bit wide
16395  * register. An interrupt bit is cleared when the respective MMC counter that
16396  * caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the
16397  * respective counter must be read in order to clear the interrupt bit.
16398  *
16399  * Register Layout
16400  *
16401  * Bits | Access | Reset | Description
16402  * :--------|:-------|:------|:------------------------------------------
16403  * [0] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS
16404  * [1] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS
16405  * [2] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS
16406  * [3] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS
16407  * [4] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS
16408  * [5] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS
16409  * [6] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS
16410  * [7] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS
16411  * [8] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS
16412  * [9] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS
16413  * [10] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS
16414  * [11] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS
16415  * [12] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS
16416  * [13] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS
16417  * [14] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS
16418  * [15] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS
16419  * [16] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS
16420  * [17] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS
16421  * [18] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS
16422  * [19] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS
16423  * [20] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS
16424  * [21] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS
16425  * [22] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS
16426  * [23] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS
16427  * [24] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS
16428  * [25] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS
16429  * [31:26] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_RSVD_31_26
16430  *
16431  */
16432 /*
16433  * Field : rxgbfrmis
16434  *
16435  * MMC Receive Good Bad Frame Counter Interrupt Status
16436  *
16437  * This bit is set when the rxframecount_bg counter reaches half of the maximum
16438  * value or the maximum value.
16439  *
16440  * Field Enumeration Values:
16441  *
16442  * Enum | Value | Description
16443  * :----------------------------------------------|:------|:------------
16444  * ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_E_ALMOSTHALF | 0x0 |
16445  * ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_E_ALMOSTFULL | 0x1 |
16446  *
16447  * Field Access Macros:
16448  *
16449  */
16450 /*
16451  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS
16452  *
16453  */
16454 #define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_E_ALMOSTHALF 0x0
16455 /*
16456  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS
16457  *
16458  */
16459 #define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_E_ALMOSTFULL 0x1
16460 
16461 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field. */
16462 #define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_LSB 0
16463 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field. */
16464 #define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_MSB 0
16465 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field. */
16466 #define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_WIDTH 1
16467 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field value. */
16468 #define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_SET_MSK 0x00000001
16469 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field value. */
16470 #define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_CLR_MSK 0xfffffffe
16471 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field. */
16472 #define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_RESET 0x0
16473 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS field value from a register. */
16474 #define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_GET(value) (((value) & 0x00000001) >> 0)
16475 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field value suitable for setting the register. */
16476 #define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_SET(value) (((value) << 0) & 0x00000001)
16477 
16478 /*
16479  * Field : rxgboctis
16480  *
16481  * MMC Receive Good Bad Octet Counter Interrupt Status
16482  *
16483  * This bit is set when the rxoctetcount_bg counter reaches half of the maximum
16484  * value or the maximum value.
16485  *
16486  * Field Enumeration Values:
16487  *
16488  * Enum | Value | Description
16489  * :-----------------------------------------|:------|:------------
16490  * ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_E_INACT | 0x0 |
16491  * ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_E_ACT | 0x1 |
16492  *
16493  * Field Access Macros:
16494  *
16495  */
16496 /*
16497  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS
16498  *
16499  */
16500 #define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_E_INACT 0x0
16501 /*
16502  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS
16503  *
16504  */
16505 #define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_E_ACT 0x1
16506 
16507 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field. */
16508 #define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_LSB 1
16509 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field. */
16510 #define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_MSB 1
16511 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field. */
16512 #define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_WIDTH 1
16513 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field value. */
16514 #define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_SET_MSK 0x00000002
16515 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field value. */
16516 #define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_CLR_MSK 0xfffffffd
16517 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field. */
16518 #define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_RESET 0x0
16519 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS field value from a register. */
16520 #define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_GET(value) (((value) & 0x00000002) >> 1)
16521 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field value suitable for setting the register. */
16522 #define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_SET(value) (((value) << 1) & 0x00000002)
16523 
16524 /*
16525  * Field : rxgoctis
16526  *
16527  * MMC Receive Good Octet Counter Interrupt Status.
16528  *
16529  * This bit is set when the rxoctetcount_g counter reaches half of the maximum
16530  * value or the maximum value.
16531  *
16532  * Field Enumeration Values:
16533  *
16534  * Enum | Value | Description
16535  * :----------------------------------------|:------|:------------
16536  * ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_E_INACT | 0x0 |
16537  * ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_E_ACT | 0x1 |
16538  *
16539  * Field Access Macros:
16540  *
16541  */
16542 /*
16543  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS
16544  *
16545  */
16546 #define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_E_INACT 0x0
16547 /*
16548  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS
16549  *
16550  */
16551 #define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_E_ACT 0x1
16552 
16553 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field. */
16554 #define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_LSB 2
16555 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field. */
16556 #define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_MSB 2
16557 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field. */
16558 #define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_WIDTH 1
16559 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field value. */
16560 #define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_SET_MSK 0x00000004
16561 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field value. */
16562 #define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_CLR_MSK 0xfffffffb
16563 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field. */
16564 #define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_RESET 0x0
16565 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS field value from a register. */
16566 #define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_GET(value) (((value) & 0x00000004) >> 2)
16567 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field value suitable for setting the register. */
16568 #define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_SET(value) (((value) << 2) & 0x00000004)
16569 
16570 /*
16571  * Field : rxbcgfis
16572  *
16573  * MMC Receive Broadcast Good Frame Counter Interrupt Status.
16574  *
16575  * This bit is set when the rxbroadcastframes_g counter reaches half of the maximum
16576  * value or the maximum value.
16577  *
16578  * Field Access Macros:
16579  *
16580  */
16581 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field. */
16582 #define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_LSB 3
16583 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field. */
16584 #define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_MSB 3
16585 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field. */
16586 #define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_WIDTH 1
16587 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field value. */
16588 #define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_SET_MSK 0x00000008
16589 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field value. */
16590 #define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_CLR_MSK 0xfffffff7
16591 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field. */
16592 #define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_RESET 0x0
16593 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS field value from a register. */
16594 #define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_GET(value) (((value) & 0x00000008) >> 3)
16595 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field value suitable for setting the register. */
16596 #define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_SET(value) (((value) << 3) & 0x00000008)
16597 
16598 /*
16599  * Field : rxmcgfis
16600  *
16601  * MMC Receive Multicast Good Frame Counter Interrupt Status
16602  *
16603  * This bit is set when the rxmulticastframes_g counter reaches half of the maximum
16604  * value or the maximum value.
16605  *
16606  * Field Enumeration Values:
16607  *
16608  * Enum | Value | Description
16609  * :----------------------------------------|:------|:------------
16610  * ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_E_INACT | 0x0 |
16611  * ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_E_ACT | 0x1 |
16612  *
16613  * Field Access Macros:
16614  *
16615  */
16616 /*
16617  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS
16618  *
16619  */
16620 #define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_E_INACT 0x0
16621 /*
16622  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS
16623  *
16624  */
16625 #define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_E_ACT 0x1
16626 
16627 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field. */
16628 #define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_LSB 4
16629 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field. */
16630 #define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_MSB 4
16631 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field. */
16632 #define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_WIDTH 1
16633 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field value. */
16634 #define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_SET_MSK 0x00000010
16635 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field value. */
16636 #define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_CLR_MSK 0xffffffef
16637 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field. */
16638 #define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_RESET 0x0
16639 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS field value from a register. */
16640 #define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_GET(value) (((value) & 0x00000010) >> 4)
16641 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field value suitable for setting the register. */
16642 #define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_SET(value) (((value) << 4) & 0x00000010)
16643 
16644 /*
16645  * Field : rxcrcerfis
16646  *
16647  * MMC Receive CRC Error Frame Counter Interrupt Status
16648  *
16649  * This bit is set when the rxcrcerror counter reaches half of the maximum value or
16650  * the maximum value.
16651  *
16652  * Field Enumeration Values:
16653  *
16654  * Enum | Value | Description
16655  * :------------------------------------------|:------|:------------
16656  * ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_E_INACT | 0x0 |
16657  * ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_E_ACT | 0x1 |
16658  *
16659  * Field Access Macros:
16660  *
16661  */
16662 /*
16663  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS
16664  *
16665  */
16666 #define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_E_INACT 0x0
16667 /*
16668  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS
16669  *
16670  */
16671 #define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_E_ACT 0x1
16672 
16673 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field. */
16674 #define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_LSB 5
16675 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field. */
16676 #define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_MSB 5
16677 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field. */
16678 #define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_WIDTH 1
16679 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field value. */
16680 #define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_SET_MSK 0x00000020
16681 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field value. */
16682 #define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_CLR_MSK 0xffffffdf
16683 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field. */
16684 #define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_RESET 0x0
16685 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS field value from a register. */
16686 #define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_GET(value) (((value) & 0x00000020) >> 5)
16687 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field value suitable for setting the register. */
16688 #define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_SET(value) (((value) << 5) & 0x00000020)
16689 
16690 /*
16691  * Field : rxalgnerfis
16692  *
16693  * MMC Receive Alignment Error Frame Counter Interrupt Status
16694  *
16695  * This bit is set when the rxalignmenterror counter reaches half of the maximum
16696  * value or the maximum value.
16697  *
16698  * Field Enumeration Values:
16699  *
16700  * Enum | Value | Description
16701  * :-------------------------------------------|:------|:------------
16702  * ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_E_INACT | 0x0 |
16703  * ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_E_ACT | 0x1 |
16704  *
16705  * Field Access Macros:
16706  *
16707  */
16708 /*
16709  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS
16710  *
16711  */
16712 #define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_E_INACT 0x0
16713 /*
16714  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS
16715  *
16716  */
16717 #define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_E_ACT 0x1
16718 
16719 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field. */
16720 #define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_LSB 6
16721 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field. */
16722 #define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_MSB 6
16723 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field. */
16724 #define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_WIDTH 1
16725 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field value. */
16726 #define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_SET_MSK 0x00000040
16727 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field value. */
16728 #define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_CLR_MSK 0xffffffbf
16729 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field. */
16730 #define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_RESET 0x0
16731 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS field value from a register. */
16732 #define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_GET(value) (((value) & 0x00000040) >> 6)
16733 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field value suitable for setting the register. */
16734 #define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_SET(value) (((value) << 6) & 0x00000040)
16735 
16736 /*
16737  * Field : rxruntfis
16738  *
16739  * MMC Receive Runt Frame Counter Interrupt Status
16740  *
16741  * This bit is set when the rxrunterror counter reaches half of the maximum value
16742  * or the maximum value.
16743  *
16744  * Field Enumeration Values:
16745  *
16746  * Enum | Value | Description
16747  * :-----------------------------------------|:------|:------------
16748  * ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_E_INACT | 0x0 |
16749  * ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_E_ACT | 0x1 |
16750  *
16751  * Field Access Macros:
16752  *
16753  */
16754 /*
16755  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS
16756  *
16757  */
16758 #define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_E_INACT 0x0
16759 /*
16760  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS
16761  *
16762  */
16763 #define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_E_ACT 0x1
16764 
16765 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field. */
16766 #define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_LSB 7
16767 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field. */
16768 #define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_MSB 7
16769 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field. */
16770 #define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_WIDTH 1
16771 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field value. */
16772 #define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_SET_MSK 0x00000080
16773 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field value. */
16774 #define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_CLR_MSK 0xffffff7f
16775 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field. */
16776 #define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_RESET 0x0
16777 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS field value from a register. */
16778 #define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_GET(value) (((value) & 0x00000080) >> 7)
16779 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field value suitable for setting the register. */
16780 #define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_SET(value) (((value) << 7) & 0x00000080)
16781 
16782 /*
16783  * Field : rxjaberfis
16784  *
16785  * MMC Receive Jabber Error Frame Counter Interrupt Status
16786  *
16787  * This bit is set when the rxjabbererror counter reaches half of the maximum value
16788  * or the maximum value.
16789  *
16790  * Field Enumeration Values:
16791  *
16792  * Enum | Value | Description
16793  * :------------------------------------------|:------|:------------
16794  * ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_E_INACT | 0x0 |
16795  * ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_E_ACT | 0x1 |
16796  *
16797  * Field Access Macros:
16798  *
16799  */
16800 /*
16801  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS
16802  *
16803  */
16804 #define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_E_INACT 0x0
16805 /*
16806  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS
16807  *
16808  */
16809 #define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_E_ACT 0x1
16810 
16811 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field. */
16812 #define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_LSB 8
16813 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field. */
16814 #define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_MSB 8
16815 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field. */
16816 #define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_WIDTH 1
16817 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field value. */
16818 #define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_SET_MSK 0x00000100
16819 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field value. */
16820 #define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_CLR_MSK 0xfffffeff
16821 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field. */
16822 #define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_RESET 0x0
16823 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS field value from a register. */
16824 #define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_GET(value) (((value) & 0x00000100) >> 8)
16825 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field value suitable for setting the register. */
16826 #define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_SET(value) (((value) << 8) & 0x00000100)
16827 
16828 /*
16829  * Field : rxusizegfis
16830  *
16831  * MMC Receive Undersize Good Frame Counter Interrupt Status
16832  *
16833  * This bit is set when the rxundersize_g counter reaches half of the maximum value
16834  * or the maximum value.
16835  *
16836  * Field Enumeration Values:
16837  *
16838  * Enum | Value | Description
16839  * :-------------------------------------------|:------|:------------
16840  * ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_E_INACT | 0x0 |
16841  * ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_E_ACT | 0x1 |
16842  *
16843  * Field Access Macros:
16844  *
16845  */
16846 /*
16847  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS
16848  *
16849  */
16850 #define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_E_INACT 0x0
16851 /*
16852  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS
16853  *
16854  */
16855 #define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_E_ACT 0x1
16856 
16857 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field. */
16858 #define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_LSB 9
16859 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field. */
16860 #define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_MSB 9
16861 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field. */
16862 #define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_WIDTH 1
16863 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field value. */
16864 #define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_SET_MSK 0x00000200
16865 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field value. */
16866 #define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_CLR_MSK 0xfffffdff
16867 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field. */
16868 #define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_RESET 0x0
16869 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS field value from a register. */
16870 #define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_GET(value) (((value) & 0x00000200) >> 9)
16871 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field value suitable for setting the register. */
16872 #define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_SET(value) (((value) << 9) & 0x00000200)
16873 
16874 /*
16875  * Field : rxosizegfis
16876  *
16877  * MMC Receive Oversize Good Frame Counter Interrupt Status
16878  *
16879  * This bit is set when the rxoversize_g counter reaches half of the maximum value
16880  * or the maximum value.
16881  *
16882  * Field Enumeration Values:
16883  *
16884  * Enum | Value | Description
16885  * :-------------------------------------------|:------|:------------
16886  * ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_E_INACT | 0x0 |
16887  * ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_E_ACT | 0x1 |
16888  *
16889  * Field Access Macros:
16890  *
16891  */
16892 /*
16893  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS
16894  *
16895  */
16896 #define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_E_INACT 0x0
16897 /*
16898  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS
16899  *
16900  */
16901 #define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_E_ACT 0x1
16902 
16903 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field. */
16904 #define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_LSB 10
16905 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field. */
16906 #define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_MSB 10
16907 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field. */
16908 #define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_WIDTH 1
16909 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field value. */
16910 #define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_SET_MSK 0x00000400
16911 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field value. */
16912 #define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_CLR_MSK 0xfffffbff
16913 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field. */
16914 #define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_RESET 0x0
16915 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS field value from a register. */
16916 #define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_GET(value) (((value) & 0x00000400) >> 10)
16917 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field value suitable for setting the register. */
16918 #define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_SET(value) (((value) << 10) & 0x00000400)
16919 
16920 /*
16921  * Field : rx64octgbfis
16922  *
16923  * MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status
16924  *
16925  * This bit is set when the rx64octets_gb counter reaches half of the maximum value
16926  * or the maximum value.
16927  *
16928  * Field Enumeration Values:
16929  *
16930  * Enum | Value | Description
16931  * :--------------------------------------------|:------|:------------
16932  * ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_E_INACT | 0x0 |
16933  * ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_E_ACT | 0x1 |
16934  *
16935  * Field Access Macros:
16936  *
16937  */
16938 /*
16939  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS
16940  *
16941  */
16942 #define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_E_INACT 0x0
16943 /*
16944  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS
16945  *
16946  */
16947 #define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_E_ACT 0x1
16948 
16949 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field. */
16950 #define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_LSB 11
16951 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field. */
16952 #define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_MSB 11
16953 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field. */
16954 #define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_WIDTH 1
16955 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field value. */
16956 #define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_SET_MSK 0x00000800
16957 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field value. */
16958 #define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_CLR_MSK 0xfffff7ff
16959 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field. */
16960 #define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_RESET 0x0
16961 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS field value from a register. */
16962 #define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_GET(value) (((value) & 0x00000800) >> 11)
16963 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field value suitable for setting the register. */
16964 #define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_SET(value) (((value) << 11) & 0x00000800)
16965 
16966 /*
16967  * Field : rx65t127octgbfis
16968  *
16969  * MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status
16970  *
16971  * This is set when the rx65to127octets_gb counter reaches half of the maximum
16972  * value or the maximum value.
16973  *
16974  * Field Enumeration Values:
16975  *
16976  * Enum | Value | Description
16977  * :------------------------------------------------|:------|:------------
16978  * ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_E_INACT | 0x0 |
16979  * ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_E_ACT | 0x1 |
16980  *
16981  * Field Access Macros:
16982  *
16983  */
16984 /*
16985  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS
16986  *
16987  */
16988 #define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_E_INACT 0x0
16989 /*
16990  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS
16991  *
16992  */
16993 #define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_E_ACT 0x1
16994 
16995 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field. */
16996 #define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_LSB 12
16997 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field. */
16998 #define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_MSB 12
16999 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field. */
17000 #define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_WIDTH 1
17001 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field value. */
17002 #define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_SET_MSK 0x00001000
17003 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field value. */
17004 #define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_CLR_MSK 0xffffefff
17005 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field. */
17006 #define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_RESET 0x0
17007 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS field value from a register. */
17008 #define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_GET(value) (((value) & 0x00001000) >> 12)
17009 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field value suitable for setting the register. */
17010 #define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_SET(value) (((value) << 12) & 0x00001000)
17011 
17012 /*
17013  * Field : rx128t255octgbfis
17014  *
17015  * MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status
17016  *
17017  * This bit is set when the rx128to255octets_gb counter reaches half of the maximum
17018  * value or the maximum value.
17019  *
17020  * Field Enumeration Values:
17021  *
17022  * Enum | Value | Description
17023  * :-------------------------------------------------|:------|:------------
17024  * ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_E_INACT | 0x0 |
17025  * ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_E_ACT | 0x1 |
17026  *
17027  * Field Access Macros:
17028  *
17029  */
17030 /*
17031  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS
17032  *
17033  */
17034 #define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_E_INACT 0x0
17035 /*
17036  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS
17037  *
17038  */
17039 #define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_E_ACT 0x1
17040 
17041 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field. */
17042 #define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_LSB 13
17043 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field. */
17044 #define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_MSB 13
17045 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field. */
17046 #define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_WIDTH 1
17047 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field value. */
17048 #define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_SET_MSK 0x00002000
17049 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field value. */
17050 #define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_CLR_MSK 0xffffdfff
17051 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field. */
17052 #define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_RESET 0x0
17053 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS field value from a register. */
17054 #define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_GET(value) (((value) & 0x00002000) >> 13)
17055 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field value suitable for setting the register. */
17056 #define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_SET(value) (((value) << 13) & 0x00002000)
17057 
17058 /*
17059  * Field : rx256t511octgbfis
17060  *
17061  * MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status
17062  *
17063  * This bit is set when the rx256to511octets_gb counter reaches half of the maximum
17064  * value or the maximum value.
17065  *
17066  * Field Enumeration Values:
17067  *
17068  * Enum | Value | Description
17069  * :-------------------------------------------------|:------|:------------
17070  * ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_E_INACT | 0x0 |
17071  * ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_E_ACT | 0x1 |
17072  *
17073  * Field Access Macros:
17074  *
17075  */
17076 /*
17077  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS
17078  *
17079  */
17080 #define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_E_INACT 0x0
17081 /*
17082  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS
17083  *
17084  */
17085 #define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_E_ACT 0x1
17086 
17087 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field. */
17088 #define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_LSB 14
17089 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field. */
17090 #define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_MSB 14
17091 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field. */
17092 #define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_WIDTH 1
17093 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field value. */
17094 #define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_SET_MSK 0x00004000
17095 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field value. */
17096 #define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_CLR_MSK 0xffffbfff
17097 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field. */
17098 #define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_RESET 0x0
17099 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS field value from a register. */
17100 #define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_GET(value) (((value) & 0x00004000) >> 14)
17101 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field value suitable for setting the register. */
17102 #define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_SET(value) (((value) << 14) & 0x00004000)
17103 
17104 /*
17105  * Field : rx512t1023octgbfis
17106  *
17107  * MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status
17108  *
17109  * This bit is set when the rx512to1023octets_gb counter reaches half of the
17110  * maximum value or the maximum value.
17111  *
17112  * Field Enumeration Values:
17113  *
17114  * Enum | Value | Description
17115  * :--------------------------------------------------|:------|:------------
17116  * ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_E_INACT | 0x0 |
17117  * ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_E_ACT | 0x1 |
17118  *
17119  * Field Access Macros:
17120  *
17121  */
17122 /*
17123  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS
17124  *
17125  */
17126 #define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_E_INACT 0x0
17127 /*
17128  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS
17129  *
17130  */
17131 #define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_E_ACT 0x1
17132 
17133 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field. */
17134 #define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_LSB 15
17135 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field. */
17136 #define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_MSB 15
17137 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field. */
17138 #define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_WIDTH 1
17139 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field value. */
17140 #define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_SET_MSK 0x00008000
17141 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field value. */
17142 #define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_CLR_MSK 0xffff7fff
17143 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field. */
17144 #define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_RESET 0x0
17145 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS field value from a register. */
17146 #define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_GET(value) (((value) & 0x00008000) >> 15)
17147 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field value suitable for setting the register. */
17148 #define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_SET(value) (((value) << 15) & 0x00008000)
17149 
17150 /*
17151  * Field : rx1024tmaxoctgbfis
17152  *
17153  * MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status
17154  *
17155  * This bit is set when the rx1024tomaxoctets_gb counter reaches half of the
17156  * maximum value or the maximum value.
17157  *
17158  * Field Enumeration Values:
17159  *
17160  * Enum | Value | Description
17161  * :--------------------------------------------------|:------|:------------
17162  * ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_E_INACT | 0x0 |
17163  * ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_E_ACT | 0x1 |
17164  *
17165  * Field Access Macros:
17166  *
17167  */
17168 /*
17169  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS
17170  *
17171  */
17172 #define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_E_INACT 0x0
17173 /*
17174  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS
17175  *
17176  */
17177 #define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_E_ACT 0x1
17178 
17179 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field. */
17180 #define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_LSB 16
17181 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field. */
17182 #define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_MSB 16
17183 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field. */
17184 #define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_WIDTH 1
17185 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field value. */
17186 #define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_SET_MSK 0x00010000
17187 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field value. */
17188 #define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_CLR_MSK 0xfffeffff
17189 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field. */
17190 #define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_RESET 0x0
17191 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS field value from a register. */
17192 #define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_GET(value) (((value) & 0x00010000) >> 16)
17193 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field value suitable for setting the register. */
17194 #define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_SET(value) (((value) << 16) & 0x00010000)
17195 
17196 /*
17197  * Field : rxucgfis
17198  *
17199  * MMC Receive Unicast Good Frame Counter Interrupt Status
17200  *
17201  * This bit is set when the rxunicastframes_gb counter reaches half of the maximum
17202  * value or the maximum value.
17203  *
17204  * Field Enumeration Values:
17205  *
17206  * Enum | Value | Description
17207  * :----------------------------------------|:------|:------------
17208  * ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_E_INACT | 0x0 |
17209  * ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_E_ACT | 0x1 |
17210  *
17211  * Field Access Macros:
17212  *
17213  */
17214 /*
17215  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS
17216  *
17217  */
17218 #define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_E_INACT 0x0
17219 /*
17220  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS
17221  *
17222  */
17223 #define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_E_ACT 0x1
17224 
17225 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field. */
17226 #define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_LSB 17
17227 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field. */
17228 #define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_MSB 17
17229 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field. */
17230 #define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_WIDTH 1
17231 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field value. */
17232 #define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_SET_MSK 0x00020000
17233 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field value. */
17234 #define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_CLR_MSK 0xfffdffff
17235 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field. */
17236 #define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_RESET 0x0
17237 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS field value from a register. */
17238 #define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_GET(value) (((value) & 0x00020000) >> 17)
17239 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field value suitable for setting the register. */
17240 #define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_SET(value) (((value) << 17) & 0x00020000)
17241 
17242 /*
17243  * Field : rxlenerfis
17244  *
17245  * MMC Receive Length Error Frame Counter Interrupt Status
17246  *
17247  * This bit is set when the rxlengtherror counter reaches half of the maximum value
17248  * or the maximum value.
17249  *
17250  * Field Enumeration Values:
17251  *
17252  * Enum | Value | Description
17253  * :------------------------------------------|:------|:------------
17254  * ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_E_INACT | 0x0 |
17255  * ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_E_ACT | 0x1 |
17256  *
17257  * Field Access Macros:
17258  *
17259  */
17260 /*
17261  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS
17262  *
17263  */
17264 #define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_E_INACT 0x0
17265 /*
17266  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS
17267  *
17268  */
17269 #define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_E_ACT 0x1
17270 
17271 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field. */
17272 #define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_LSB 18
17273 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field. */
17274 #define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_MSB 18
17275 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field. */
17276 #define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_WIDTH 1
17277 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field value. */
17278 #define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_SET_MSK 0x00040000
17279 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field value. */
17280 #define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_CLR_MSK 0xfffbffff
17281 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field. */
17282 #define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_RESET 0x0
17283 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS field value from a register. */
17284 #define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_GET(value) (((value) & 0x00040000) >> 18)
17285 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field value suitable for setting the register. */
17286 #define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_SET(value) (((value) << 18) & 0x00040000)
17287 
17288 /*
17289  * Field : rxorangefis
17290  *
17291  * MMC Receive Out Of Range Error Frame Counter Interrupt Status
17292  *
17293  * This bit is set when the rxoutofrangetype counter reaches half of the maximum
17294  * value or the maximum value.
17295  *
17296  * Field Enumeration Values:
17297  *
17298  * Enum | Value | Description
17299  * :-------------------------------------------|:------|:------------
17300  * ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_E_INACT | 0x0 |
17301  * ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_E_ACT | 0x1 |
17302  *
17303  * Field Access Macros:
17304  *
17305  */
17306 /*
17307  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS
17308  *
17309  */
17310 #define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_E_INACT 0x0
17311 /*
17312  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS
17313  *
17314  */
17315 #define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_E_ACT 0x1
17316 
17317 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field. */
17318 #define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_LSB 19
17319 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field. */
17320 #define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_MSB 19
17321 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field. */
17322 #define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_WIDTH 1
17323 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field value. */
17324 #define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_SET_MSK 0x00080000
17325 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field value. */
17326 #define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_CLR_MSK 0xfff7ffff
17327 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field. */
17328 #define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_RESET 0x0
17329 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS field value from a register. */
17330 #define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_GET(value) (((value) & 0x00080000) >> 19)
17331 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field value suitable for setting the register. */
17332 #define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_SET(value) (((value) << 19) & 0x00080000)
17333 
17334 /*
17335  * Field : rxpausfis
17336  *
17337  * MMC Receive Pause Frame Counter Interrupt Status
17338  *
17339  * This bit is set when the rxpauseframe counter reaches half of the maximum value
17340  * or the maximum value.
17341  *
17342  * Field Enumeration Values:
17343  *
17344  * Enum | Value | Description
17345  * :-----------------------------------------|:------|:------------
17346  * ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_E_INACT | 0x0 |
17347  * ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_E_ACT | 0x1 |
17348  *
17349  * Field Access Macros:
17350  *
17351  */
17352 /*
17353  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS
17354  *
17355  */
17356 #define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_E_INACT 0x0
17357 /*
17358  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS
17359  *
17360  */
17361 #define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_E_ACT 0x1
17362 
17363 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field. */
17364 #define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_LSB 20
17365 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field. */
17366 #define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_MSB 20
17367 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field. */
17368 #define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_WIDTH 1
17369 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field value. */
17370 #define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_SET_MSK 0x00100000
17371 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field value. */
17372 #define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_CLR_MSK 0xffefffff
17373 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field. */
17374 #define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_RESET 0x0
17375 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS field value from a register. */
17376 #define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_GET(value) (((value) & 0x00100000) >> 20)
17377 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field value suitable for setting the register. */
17378 #define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_SET(value) (((value) << 20) & 0x00100000)
17379 
17380 /*
17381  * Field : rxfovfis
17382  *
17383  * MMC Receive FIFO Overflow Frame Counter Interrupt Status
17384  *
17385  * This bit is set when the rxfifooverflow counter reaches half of the maximum
17386  * value or the maximum value.
17387  *
17388  * Field Enumeration Values:
17389  *
17390  * Enum | Value | Description
17391  * :----------------------------------------|:------|:------------
17392  * ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_E_INACT | 0x0 |
17393  * ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_E_ACT | 0x1 |
17394  *
17395  * Field Access Macros:
17396  *
17397  */
17398 /*
17399  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS
17400  *
17401  */
17402 #define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_E_INACT 0x0
17403 /*
17404  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS
17405  *
17406  */
17407 #define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_E_ACT 0x1
17408 
17409 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field. */
17410 #define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_LSB 21
17411 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field. */
17412 #define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_MSB 21
17413 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field. */
17414 #define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_WIDTH 1
17415 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field value. */
17416 #define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_SET_MSK 0x00200000
17417 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field value. */
17418 #define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_CLR_MSK 0xffdfffff
17419 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field. */
17420 #define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_RESET 0x0
17421 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS field value from a register. */
17422 #define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_GET(value) (((value) & 0x00200000) >> 21)
17423 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field value suitable for setting the register. */
17424 #define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_SET(value) (((value) << 21) & 0x00200000)
17425 
17426 /*
17427  * Field : rxvlangbfis
17428  *
17429  * MMC Receive VLAN Good Bad Frame Counter Interrupt Status
17430  *
17431  * This bit is set when the rxvlanframes_gb counter reaches half of the maximum
17432  * value or the maximum value.
17433  *
17434  * Field Enumeration Values:
17435  *
17436  * Enum | Value | Description
17437  * :-------------------------------------------|:------|:------------
17438  * ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_E_INACT | 0x0 |
17439  * ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_E_ACT | 0x1 |
17440  *
17441  * Field Access Macros:
17442  *
17443  */
17444 /*
17445  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS
17446  *
17447  */
17448 #define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_E_INACT 0x0
17449 /*
17450  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS
17451  *
17452  */
17453 #define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_E_ACT 0x1
17454 
17455 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field. */
17456 #define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_LSB 22
17457 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field. */
17458 #define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_MSB 22
17459 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field. */
17460 #define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_WIDTH 1
17461 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field value. */
17462 #define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_SET_MSK 0x00400000
17463 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field value. */
17464 #define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_CLR_MSK 0xffbfffff
17465 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field. */
17466 #define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_RESET 0x0
17467 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS field value from a register. */
17468 #define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_GET(value) (((value) & 0x00400000) >> 22)
17469 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field value suitable for setting the register. */
17470 #define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_SET(value) (((value) << 22) & 0x00400000)
17471 
17472 /*
17473  * Field : rxwdogfis
17474  *
17475  * MMC Receive Watchdog Error Frame Counter Interrupt Status
17476  *
17477  * This bit is set when the rxwatchdogerror counter reaches half of the maximum
17478  * value or the maximum value.
17479  *
17480  * Field Enumeration Values:
17481  *
17482  * Enum | Value | Description
17483  * :-----------------------------------------|:------|:------------
17484  * ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_E_INACT | 0x0 |
17485  * ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_E_ACT | 0x1 |
17486  *
17487  * Field Access Macros:
17488  *
17489  */
17490 /*
17491  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS
17492  *
17493  */
17494 #define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_E_INACT 0x0
17495 /*
17496  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS
17497  *
17498  */
17499 #define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_E_ACT 0x1
17500 
17501 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field. */
17502 #define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_LSB 23
17503 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field. */
17504 #define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_MSB 23
17505 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field. */
17506 #define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_WIDTH 1
17507 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field value. */
17508 #define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_SET_MSK 0x00800000
17509 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field value. */
17510 #define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_CLR_MSK 0xff7fffff
17511 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field. */
17512 #define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_RESET 0x0
17513 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS field value from a register. */
17514 #define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_GET(value) (((value) & 0x00800000) >> 23)
17515 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field value suitable for setting the register. */
17516 #define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_SET(value) (((value) << 23) & 0x00800000)
17517 
17518 /*
17519  * Field : rxrcverrfis
17520  *
17521  * MMC Receive Error Frame Counter Interrupt Status
17522  *
17523  * This bit is set when the rxrcverror counter reaches half of the maximum value or
17524  * the maximum value.
17525  *
17526  * Field Access Macros:
17527  *
17528  */
17529 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field. */
17530 #define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_LSB 24
17531 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field. */
17532 #define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_MSB 24
17533 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field. */
17534 #define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_WIDTH 1
17535 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field value. */
17536 #define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_SET_MSK 0x01000000
17537 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field value. */
17538 #define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_CLR_MSK 0xfeffffff
17539 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field. */
17540 #define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_RESET 0x0
17541 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS field value from a register. */
17542 #define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_GET(value) (((value) & 0x01000000) >> 24)
17543 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field value suitable for setting the register. */
17544 #define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_SET(value) (((value) << 24) & 0x01000000)
17545 
17546 /*
17547  * Field : rxctrlfis
17548  *
17549  * MMC Receive Control Frame Counter Interrupt Status
17550  *
17551  * This bit is set when the rxctrlframes_g counter reaches half of the maximum
17552  * value or the maximum value.
17553  *
17554  * Field Access Macros:
17555  *
17556  */
17557 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field. */
17558 #define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_LSB 25
17559 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field. */
17560 #define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_MSB 25
17561 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field. */
17562 #define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_WIDTH 1
17563 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field value. */
17564 #define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_SET_MSK 0x02000000
17565 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field value. */
17566 #define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_CLR_MSK 0xfdffffff
17567 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field. */
17568 #define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_RESET 0x0
17569 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS field value from a register. */
17570 #define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_GET(value) (((value) & 0x02000000) >> 25)
17571 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field value suitable for setting the register. */
17572 #define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_SET(value) (((value) << 25) & 0x02000000)
17573 
17574 /*
17575  * Field : reserved_31_26
17576  *
17577  * Reserved
17578  *
17579  * Field Access Macros:
17580  *
17581  */
17582 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_RSVD_31_26 register field. */
17583 #define ALT_EMAC_GMAC_MMC_RX_INT_RSVD_31_26_LSB 26
17584 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_RSVD_31_26 register field. */
17585 #define ALT_EMAC_GMAC_MMC_RX_INT_RSVD_31_26_MSB 31
17586 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_RSVD_31_26 register field. */
17587 #define ALT_EMAC_GMAC_MMC_RX_INT_RSVD_31_26_WIDTH 6
17588 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_RSVD_31_26 register field value. */
17589 #define ALT_EMAC_GMAC_MMC_RX_INT_RSVD_31_26_SET_MSK 0xfc000000
17590 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_RSVD_31_26 register field value. */
17591 #define ALT_EMAC_GMAC_MMC_RX_INT_RSVD_31_26_CLR_MSK 0x03ffffff
17592 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_RSVD_31_26 register field. */
17593 #define ALT_EMAC_GMAC_MMC_RX_INT_RSVD_31_26_RESET 0x0
17594 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_RSVD_31_26 field value from a register. */
17595 #define ALT_EMAC_GMAC_MMC_RX_INT_RSVD_31_26_GET(value) (((value) & 0xfc000000) >> 26)
17596 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_RSVD_31_26 register field value suitable for setting the register. */
17597 #define ALT_EMAC_GMAC_MMC_RX_INT_RSVD_31_26_SET(value) (((value) << 26) & 0xfc000000)
17598 
17599 #ifndef __ASSEMBLY__
17600 /*
17601  * WARNING: The C register and register group struct declarations are provided for
17602  * convenience and illustrative purposes. They should, however, be used with
17603  * caution as the C language standard provides no guarantees about the alignment or
17604  * atomicity of device memory accesses. The recommended practice for writing
17605  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17606  * alt_write_word() functions.
17607  *
17608  * The struct declaration for register ALT_EMAC_GMAC_MMC_RX_INT.
17609  */
17610 struct ALT_EMAC_GMAC_MMC_RX_INT_s
17611 {
17612  const uint32_t rxgbfrmis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS */
17613  const uint32_t rxgboctis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS */
17614  const uint32_t rxgoctis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS */
17615  const uint32_t rxbcgfis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS */
17616  const uint32_t rxmcgfis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS */
17617  const uint32_t rxcrcerfis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS */
17618  const uint32_t rxalgnerfis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS */
17619  const uint32_t rxruntfis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS */
17620  const uint32_t rxjaberfis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS */
17621  const uint32_t rxusizegfis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS */
17622  const uint32_t rxosizegfis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS */
17623  const uint32_t rx64octgbfis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS */
17624  const uint32_t rx65t127octgbfis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS */
17625  const uint32_t rx128t255octgbfis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS */
17626  const uint32_t rx256t511octgbfis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS */
17627  const uint32_t rx512t1023octgbfis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS */
17628  const uint32_t rx1024tmaxoctgbfis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS */
17629  const uint32_t rxucgfis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS */
17630  const uint32_t rxlenerfis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS */
17631  const uint32_t rxorangefis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS */
17632  const uint32_t rxpausfis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS */
17633  const uint32_t rxfovfis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS */
17634  const uint32_t rxvlangbfis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS */
17635  const uint32_t rxwdogfis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS */
17636  const uint32_t rxrcverrfis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS */
17637  const uint32_t rxctrlfis : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS */
17638  const uint32_t reserved_31_26 : 6; /* ALT_EMAC_GMAC_MMC_RX_INT_RSVD_31_26 */
17639 };
17640 
17641 /* The typedef declaration for register ALT_EMAC_GMAC_MMC_RX_INT. */
17642 typedef volatile struct ALT_EMAC_GMAC_MMC_RX_INT_s ALT_EMAC_GMAC_MMC_RX_INT_t;
17643 #endif /* __ASSEMBLY__ */
17644 
17645 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT register. */
17646 #define ALT_EMAC_GMAC_MMC_RX_INT_RESET 0x00000000
17647 /* The byte offset of the ALT_EMAC_GMAC_MMC_RX_INT register from the beginning of the component. */
17648 #define ALT_EMAC_GMAC_MMC_RX_INT_OFST 0x104
17649 /* The address of the ALT_EMAC_GMAC_MMC_RX_INT register. */
17650 #define ALT_EMAC_GMAC_MMC_RX_INT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_RX_INT_OFST))
17651 
17652 /*
17653  * Register : gmacgrp_mmc_transmit_interrupt
17654  *
17655  * <b> Register 66 (MMC Transmit Interrupt Register) </b>
17656  *
17657  * The MMC Transmit Interrupt register maintains the interrupts generated when
17658  * transmit statistic counters reach half of their maximum values (0x8000_0000 for
17659  * 32-bit counter and 0x8000 for 16-bit counter), and the maximum values
17660  * (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter
17661  * Stop Rollover is set, then interrupts are set but the counter remains at all-
17662  * ones. The MMC Transmit Interrupt register is a 32-bit wide register. An
17663  * interrupt bit is cleared when the respective MMC counter that caused the
17664  * interrupt is read. The least significant byte lane (Bits[7:0]) of the respective
17665  * counter must be read in order to clear the interrupt bit.
17666  *
17667  * Register Layout
17668  *
17669  * Bits | Access | Reset | Description
17670  * :--------|:-------|:------|:------------------------------------------
17671  * [0] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS
17672  * [1] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS
17673  * [2] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS
17674  * [3] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS
17675  * [4] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS
17676  * [5] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS
17677  * [6] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS
17678  * [7] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS
17679  * [8] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS
17680  * [9] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS
17681  * [10] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS
17682  * [11] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS
17683  * [12] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS
17684  * [13] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS
17685  * [14] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS
17686  * [15] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS
17687  * [16] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS
17688  * [17] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS
17689  * [18] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS
17690  * [19] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS
17691  * [20] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS
17692  * [21] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS
17693  * [22] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS
17694  * [23] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS
17695  * [24] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS
17696  * [25] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS
17697  * [31:26] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26
17698  *
17699  */
17700 /*
17701  * Field : txgboctis
17702  *
17703  * MMC Transmit Good Bad Octet Counter Interrupt Status
17704  *
17705  * This bit is set when the txoctetcount_gb counter reaches half of the maximum
17706  * value or the maximum value.
17707  *
17708  * Field Enumeration Values:
17709  *
17710  * Enum | Value | Description
17711  * :-----------------------------------------|:------|:------------
17712  * ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_E_INACT | 0x0 |
17713  * ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_E_ACT | 0x1 |
17714  *
17715  * Field Access Macros:
17716  *
17717  */
17718 /*
17719  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS
17720  *
17721  */
17722 #define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_E_INACT 0x0
17723 /*
17724  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS
17725  *
17726  */
17727 #define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_E_ACT 0x1
17728 
17729 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field. */
17730 #define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_LSB 0
17731 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field. */
17732 #define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_MSB 0
17733 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field. */
17734 #define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_WIDTH 1
17735 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field value. */
17736 #define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_SET_MSK 0x00000001
17737 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field value. */
17738 #define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_CLR_MSK 0xfffffffe
17739 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field. */
17740 #define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_RESET 0x0
17741 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS field value from a register. */
17742 #define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_GET(value) (((value) & 0x00000001) >> 0)
17743 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field value suitable for setting the register. */
17744 #define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_SET(value) (((value) << 0) & 0x00000001)
17745 
17746 /*
17747  * Field : txgbfrmis
17748  *
17749  * MMC Transmit Good Bad Frame Counter Interrupt Status
17750  *
17751  * This bit is set when the txframecount_gb counter reaches half of the maximum
17752  * value or the maximum value.
17753  *
17754  * Field Enumeration Values:
17755  *
17756  * Enum | Value | Description
17757  * :-----------------------------------------|:------|:------------
17758  * ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_E_INACT | 0x0 |
17759  * ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_E_ACT | 0x1 |
17760  *
17761  * Field Access Macros:
17762  *
17763  */
17764 /*
17765  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS
17766  *
17767  */
17768 #define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_E_INACT 0x0
17769 /*
17770  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS
17771  *
17772  */
17773 #define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_E_ACT 0x1
17774 
17775 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field. */
17776 #define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_LSB 1
17777 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field. */
17778 #define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_MSB 1
17779 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field. */
17780 #define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_WIDTH 1
17781 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field value. */
17782 #define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_SET_MSK 0x00000002
17783 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field value. */
17784 #define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_CLR_MSK 0xfffffffd
17785 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field. */
17786 #define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_RESET 0x0
17787 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS field value from a register. */
17788 #define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_GET(value) (((value) & 0x00000002) >> 1)
17789 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field value suitable for setting the register. */
17790 #define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_SET(value) (((value) << 1) & 0x00000002)
17791 
17792 /*
17793  * Field : txbcgfis
17794  *
17795  * MMC Transmit Broadcast Good Frame Counter Interrupt Status
17796  *
17797  * This bit is set when the txbroadcastframes_g counter reaches half of the maximum
17798  * value or the maximum value.
17799  *
17800  * Field Enumeration Values:
17801  *
17802  * Enum | Value | Description
17803  * :----------------------------------------|:------|:------------
17804  * ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_E_INACT | 0x0 |
17805  * ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_E_ACT | 0x1 |
17806  *
17807  * Field Access Macros:
17808  *
17809  */
17810 /*
17811  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS
17812  *
17813  */
17814 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_E_INACT 0x0
17815 /*
17816  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS
17817  *
17818  */
17819 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_E_ACT 0x1
17820 
17821 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field. */
17822 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_LSB 2
17823 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field. */
17824 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_MSB 2
17825 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field. */
17826 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_WIDTH 1
17827 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field value. */
17828 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_SET_MSK 0x00000004
17829 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field value. */
17830 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_CLR_MSK 0xfffffffb
17831 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field. */
17832 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_RESET 0x0
17833 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS field value from a register. */
17834 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_GET(value) (((value) & 0x00000004) >> 2)
17835 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field value suitable for setting the register. */
17836 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_SET(value) (((value) << 2) & 0x00000004)
17837 
17838 /*
17839  * Field : txmcgfis
17840  *
17841  * MMC Transmit Multicast Good Frame Counter Interrupt Status
17842  *
17843  * This bit is set when the txmulticastframes_g counter reaches half of the maximum
17844  * value or the maximum value.
17845  *
17846  * Field Enumeration Values:
17847  *
17848  * Enum | Value | Description
17849  * :----------------------------------------|:------|:------------
17850  * ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_E_INACT | 0x0 |
17851  * ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_E_ACT | 0x1 |
17852  *
17853  * Field Access Macros:
17854  *
17855  */
17856 /*
17857  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS
17858  *
17859  */
17860 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_E_INACT 0x0
17861 /*
17862  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS
17863  *
17864  */
17865 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_E_ACT 0x1
17866 
17867 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field. */
17868 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_LSB 3
17869 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field. */
17870 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_MSB 3
17871 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field. */
17872 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_WIDTH 1
17873 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field value. */
17874 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_SET_MSK 0x00000008
17875 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field value. */
17876 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_CLR_MSK 0xfffffff7
17877 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field. */
17878 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_RESET 0x0
17879 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS field value from a register. */
17880 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_GET(value) (((value) & 0x00000008) >> 3)
17881 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field value suitable for setting the register. */
17882 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_SET(value) (((value) << 3) & 0x00000008)
17883 
17884 /*
17885  * Field : tx64octgbfis
17886  *
17887  * MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status.
17888  *
17889  * This bit is set when the tx64octets_gb counter reaches half of the maximum value
17890  * or the maximum value.
17891  *
17892  * Field Enumeration Values:
17893  *
17894  * Enum | Value | Description
17895  * :-------------------------------------------|:------|:------------
17896  * ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_E_DISD | 0x0 |
17897  * ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_E_END | 0x1 |
17898  *
17899  * Field Access Macros:
17900  *
17901  */
17902 /*
17903  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS
17904  *
17905  */
17906 #define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_E_DISD 0x0
17907 /*
17908  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS
17909  *
17910  */
17911 #define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_E_END 0x1
17912 
17913 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field. */
17914 #define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_LSB 4
17915 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field. */
17916 #define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_MSB 4
17917 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field. */
17918 #define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_WIDTH 1
17919 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field value. */
17920 #define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_SET_MSK 0x00000010
17921 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field value. */
17922 #define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_CLR_MSK 0xffffffef
17923 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field. */
17924 #define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_RESET 0x0
17925 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS field value from a register. */
17926 #define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_GET(value) (((value) & 0x00000010) >> 4)
17927 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field value suitable for setting the register. */
17928 #define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_SET(value) (((value) << 4) & 0x00000010)
17929 
17930 /*
17931  * Field : tx65t127octgbfis
17932  *
17933  * MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status
17934  *
17935  * This bit is set when the tx65to127octets_gb counter reaches half of the maximum
17936  * value or the maximum value.
17937  *
17938  * Field Enumeration Values:
17939  *
17940  * Enum | Value | Description
17941  * :------------------------------------------------|:------|:------------
17942  * ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_E_INACT | 0x0 |
17943  * ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_E_ACT | 0x1 |
17944  *
17945  * Field Access Macros:
17946  *
17947  */
17948 /*
17949  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS
17950  *
17951  */
17952 #define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_E_INACT 0x0
17953 /*
17954  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS
17955  *
17956  */
17957 #define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_E_ACT 0x1
17958 
17959 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field. */
17960 #define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_LSB 5
17961 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field. */
17962 #define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_MSB 5
17963 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field. */
17964 #define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_WIDTH 1
17965 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field value. */
17966 #define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_SET_MSK 0x00000020
17967 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field value. */
17968 #define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_CLR_MSK 0xffffffdf
17969 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field. */
17970 #define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_RESET 0x0
17971 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS field value from a register. */
17972 #define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_GET(value) (((value) & 0x00000020) >> 5)
17973 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field value suitable for setting the register. */
17974 #define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_SET(value) (((value) << 5) & 0x00000020)
17975 
17976 /*
17977  * Field : tx128t255octgbfis
17978  *
17979  * MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status
17980  *
17981  * This bit is set when the tx128to255octets_gb counter reaches half of the maximum
17982  * value or the maximum value.
17983  *
17984  * Field Enumeration Values:
17985  *
17986  * Enum | Value | Description
17987  * :-------------------------------------------------|:------|:------------
17988  * ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_E_INACT | 0x0 |
17989  * ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_E_ACT | 0x1 |
17990  *
17991  * Field Access Macros:
17992  *
17993  */
17994 /*
17995  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS
17996  *
17997  */
17998 #define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_E_INACT 0x0
17999 /*
18000  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS
18001  *
18002  */
18003 #define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_E_ACT 0x1
18004 
18005 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field. */
18006 #define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_LSB 6
18007 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field. */
18008 #define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_MSB 6
18009 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field. */
18010 #define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_WIDTH 1
18011 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field value. */
18012 #define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_SET_MSK 0x00000040
18013 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field value. */
18014 #define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_CLR_MSK 0xffffffbf
18015 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field. */
18016 #define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_RESET 0x0
18017 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS field value from a register. */
18018 #define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_GET(value) (((value) & 0x00000040) >> 6)
18019 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field value suitable for setting the register. */
18020 #define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_SET(value) (((value) << 6) & 0x00000040)
18021 
18022 /*
18023  * Field : tx256t511octgbfis
18024  *
18025  * MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status
18026  *
18027  * This bit is set when the tx256to511octets_gb counter reaches half of the maximum
18028  * value or the maximum value.
18029  *
18030  * Field Enumeration Values:
18031  *
18032  * Enum | Value | Description
18033  * :-------------------------------------------------|:------|:------------
18034  * ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_E_INACT | 0x0 |
18035  * ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_E_ACT | 0x1 |
18036  *
18037  * Field Access Macros:
18038  *
18039  */
18040 /*
18041  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS
18042  *
18043  */
18044 #define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_E_INACT 0x0
18045 /*
18046  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS
18047  *
18048  */
18049 #define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_E_ACT 0x1
18050 
18051 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field. */
18052 #define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_LSB 7
18053 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field. */
18054 #define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_MSB 7
18055 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field. */
18056 #define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_WIDTH 1
18057 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field value. */
18058 #define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_SET_MSK 0x00000080
18059 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field value. */
18060 #define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_CLR_MSK 0xffffff7f
18061 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field. */
18062 #define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_RESET 0x0
18063 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS field value from a register. */
18064 #define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_GET(value) (((value) & 0x00000080) >> 7)
18065 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field value suitable for setting the register. */
18066 #define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_SET(value) (((value) << 7) & 0x00000080)
18067 
18068 /*
18069  * Field : tx512t1023octgbfis
18070  *
18071  * MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status
18072  *
18073  * This bit is set when the tx512to1023octets_gb counter reaches half of the
18074  * maximum value or the maximum value.
18075  *
18076  * Field Enumeration Values:
18077  *
18078  * Enum | Value | Description
18079  * :--------------------------------------------------|:------|:------------
18080  * ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_E_INACT | 0x0 |
18081  * ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_E_ACT | 0x1 |
18082  *
18083  * Field Access Macros:
18084  *
18085  */
18086 /*
18087  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS
18088  *
18089  */
18090 #define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_E_INACT 0x0
18091 /*
18092  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS
18093  *
18094  */
18095 #define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_E_ACT 0x1
18096 
18097 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field. */
18098 #define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_LSB 8
18099 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field. */
18100 #define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_MSB 8
18101 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field. */
18102 #define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_WIDTH 1
18103 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field value. */
18104 #define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_SET_MSK 0x00000100
18105 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field value. */
18106 #define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_CLR_MSK 0xfffffeff
18107 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field. */
18108 #define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_RESET 0x0
18109 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS field value from a register. */
18110 #define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_GET(value) (((value) & 0x00000100) >> 8)
18111 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field value suitable for setting the register. */
18112 #define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_SET(value) (((value) << 8) & 0x00000100)
18113 
18114 /*
18115  * Field : tx1024tmaxoctgbfis
18116  *
18117  * MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status
18118  *
18119  * This bit is set when the tx1024tomaxoctets_gb counter reaches half of the
18120  * maximum value or the maximum value.
18121  *
18122  * Field Enumeration Values:
18123  *
18124  * Enum | Value | Description
18125  * :--------------------------------------------------|:------|:------------
18126  * ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_E_INACT | 0x0 |
18127  * ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_E_ACT | 0x1 |
18128  *
18129  * Field Access Macros:
18130  *
18131  */
18132 /*
18133  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS
18134  *
18135  */
18136 #define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_E_INACT 0x0
18137 /*
18138  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS
18139  *
18140  */
18141 #define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_E_ACT 0x1
18142 
18143 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field. */
18144 #define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_LSB 9
18145 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field. */
18146 #define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_MSB 9
18147 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field. */
18148 #define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_WIDTH 1
18149 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field value. */
18150 #define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_SET_MSK 0x00000200
18151 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field value. */
18152 #define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_CLR_MSK 0xfffffdff
18153 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field. */
18154 #define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_RESET 0x0
18155 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS field value from a register. */
18156 #define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_GET(value) (((value) & 0x00000200) >> 9)
18157 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field value suitable for setting the register. */
18158 #define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_SET(value) (((value) << 9) & 0x00000200)
18159 
18160 /*
18161  * Field : txucgbfis
18162  *
18163  * MMC Transmit Unicast Good Bad Frame Counter Interrupt Status
18164  *
18165  * This bit is set when the txunicastframes_gb counter reaches half of the maximum
18166  * value or the maximum value.
18167  *
18168  * Field Enumeration Values:
18169  *
18170  * Enum | Value | Description
18171  * :-----------------------------------------|:------|:------------
18172  * ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_E_INACT | 0x0 |
18173  * ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_E_ACT | 0x1 |
18174  *
18175  * Field Access Macros:
18176  *
18177  */
18178 /*
18179  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS
18180  *
18181  */
18182 #define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_E_INACT 0x0
18183 /*
18184  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS
18185  *
18186  */
18187 #define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_E_ACT 0x1
18188 
18189 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field. */
18190 #define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_LSB 10
18191 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field. */
18192 #define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_MSB 10
18193 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field. */
18194 #define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_WIDTH 1
18195 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field value. */
18196 #define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_SET_MSK 0x00000400
18197 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field value. */
18198 #define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_CLR_MSK 0xfffffbff
18199 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field. */
18200 #define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_RESET 0x0
18201 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS field value from a register. */
18202 #define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_GET(value) (((value) & 0x00000400) >> 10)
18203 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field value suitable for setting the register. */
18204 #define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_SET(value) (((value) << 10) & 0x00000400)
18205 
18206 /*
18207  * Field : txmcgbfis
18208  *
18209  * MMC Transmit Multicast Good Bad Frame Counter Interrupt Status
18210  *
18211  * This bit is set when the txmulticastframes_gb counter reaches half of the
18212  * maximum value or the maximum value.
18213  *
18214  * Field Enumeration Values:
18215  *
18216  * Enum | Value | Description
18217  * :-----------------------------------------|:------|:------------
18218  * ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_E_INACT | 0x0 |
18219  * ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_E_ACT | 0x1 |
18220  *
18221  * Field Access Macros:
18222  *
18223  */
18224 /*
18225  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS
18226  *
18227  */
18228 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_E_INACT 0x0
18229 /*
18230  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS
18231  *
18232  */
18233 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_E_ACT 0x1
18234 
18235 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field. */
18236 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_LSB 11
18237 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field. */
18238 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_MSB 11
18239 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field. */
18240 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_WIDTH 1
18241 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field value. */
18242 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_SET_MSK 0x00000800
18243 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field value. */
18244 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_CLR_MSK 0xfffff7ff
18245 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field. */
18246 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_RESET 0x0
18247 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS field value from a register. */
18248 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_GET(value) (((value) & 0x00000800) >> 11)
18249 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field value suitable for setting the register. */
18250 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_SET(value) (((value) << 11) & 0x00000800)
18251 
18252 /*
18253  * Field : txbcgbfis
18254  *
18255  * MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status
18256  *
18257  * This bit is set when the txbroadcastframes_gb counter reaches half of the
18258  * maximum value or the maximum value.
18259  *
18260  * Field Enumeration Values:
18261  *
18262  * Enum | Value | Description
18263  * :----------------------------------------|:------|:------------
18264  * ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_E_DISD | 0x0 |
18265  * ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_E_END | 0x1 |
18266  *
18267  * Field Access Macros:
18268  *
18269  */
18270 /*
18271  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS
18272  *
18273  */
18274 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_E_DISD 0x0
18275 /*
18276  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS
18277  *
18278  */
18279 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_E_END 0x1
18280 
18281 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field. */
18282 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_LSB 12
18283 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field. */
18284 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_MSB 12
18285 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field. */
18286 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_WIDTH 1
18287 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field value. */
18288 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_SET_MSK 0x00001000
18289 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field value. */
18290 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_CLR_MSK 0xffffefff
18291 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field. */
18292 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_RESET 0x0
18293 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS field value from a register. */
18294 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_GET(value) (((value) & 0x00001000) >> 12)
18295 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field value suitable for setting the register. */
18296 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_SET(value) (((value) << 12) & 0x00001000)
18297 
18298 /*
18299  * Field : txuflowerfis
18300  *
18301  * MMC Transmit Underflow Error Frame Counter Interrupt Status
18302  *
18303  * This bit is set when the txunderflowerror counter reaches half of the maximum
18304  * value or the maximum value.
18305  *
18306  * Field Enumeration Values:
18307  *
18308  * Enum | Value | Description
18309  * :-------------------------------------------|:------|:------------
18310  * ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_E_DISD | 0x0 |
18311  * ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_E_END | 0x1 |
18312  *
18313  * Field Access Macros:
18314  *
18315  */
18316 /*
18317  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS
18318  *
18319  */
18320 #define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_E_DISD 0x0
18321 /*
18322  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS
18323  *
18324  */
18325 #define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_E_END 0x1
18326 
18327 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field. */
18328 #define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_LSB 13
18329 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field. */
18330 #define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_MSB 13
18331 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field. */
18332 #define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_WIDTH 1
18333 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field value. */
18334 #define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_SET_MSK 0x00002000
18335 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field value. */
18336 #define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_CLR_MSK 0xffffdfff
18337 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field. */
18338 #define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_RESET 0x0
18339 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS field value from a register. */
18340 #define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_GET(value) (((value) & 0x00002000) >> 13)
18341 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field value suitable for setting the register. */
18342 #define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_SET(value) (((value) << 13) & 0x00002000)
18343 
18344 /*
18345  * Field : txscolgfis
18346  *
18347  * MMC Transmit Single Collision Good Frame Counter Interrupt Status
18348  *
18349  * This bit is set when the txsinglecol_g counter reaches half of the maximum value
18350  * or the maximum value.
18351  *
18352  * Field Enumeration Values:
18353  *
18354  * Enum | Value | Description
18355  * :-----------------------------------------|:------|:------------
18356  * ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_E_DISD | 0x0 |
18357  * ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_E_END | 0x1 |
18358  *
18359  * Field Access Macros:
18360  *
18361  */
18362 /*
18363  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS
18364  *
18365  */
18366 #define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_E_DISD 0x0
18367 /*
18368  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS
18369  *
18370  */
18371 #define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_E_END 0x1
18372 
18373 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field. */
18374 #define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_LSB 14
18375 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field. */
18376 #define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_MSB 14
18377 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field. */
18378 #define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_WIDTH 1
18379 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field value. */
18380 #define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_SET_MSK 0x00004000
18381 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field value. */
18382 #define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_CLR_MSK 0xffffbfff
18383 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field. */
18384 #define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_RESET 0x0
18385 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS field value from a register. */
18386 #define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_GET(value) (((value) & 0x00004000) >> 14)
18387 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field value suitable for setting the register. */
18388 #define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_SET(value) (((value) << 14) & 0x00004000)
18389 
18390 /*
18391  * Field : txmcolgfis
18392  *
18393  * MMC Transmit Multiple Collision Good Frame Counter Interrupt Status
18394  *
18395  * This bit is set when the txmulticol_g counter reaches half of the maximum value
18396  * or the maximum value.
18397  *
18398  * Field Enumeration Values:
18399  *
18400  * Enum | Value | Description
18401  * :-----------------------------------------|:------|:------------
18402  * ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_E_DISD | 0x0 |
18403  * ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_E_END | 0x1 |
18404  *
18405  * Field Access Macros:
18406  *
18407  */
18408 /*
18409  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS
18410  *
18411  */
18412 #define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_E_DISD 0x0
18413 /*
18414  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS
18415  *
18416  */
18417 #define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_E_END 0x1
18418 
18419 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field. */
18420 #define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_LSB 15
18421 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field. */
18422 #define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_MSB 15
18423 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field. */
18424 #define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_WIDTH 1
18425 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field value. */
18426 #define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_SET_MSK 0x00008000
18427 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field value. */
18428 #define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_CLR_MSK 0xffff7fff
18429 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field. */
18430 #define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_RESET 0x0
18431 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS field value from a register. */
18432 #define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_GET(value) (((value) & 0x00008000) >> 15)
18433 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field value suitable for setting the register. */
18434 #define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_SET(value) (((value) << 15) & 0x00008000)
18435 
18436 /*
18437  * Field : txdeffis
18438  *
18439  * MMC Transmit Deferred Frame Counter Interrupt Status
18440  *
18441  * This bit is set when the txdeferred counter reaches half of the maximum value or
18442  * the maximum value.
18443  *
18444  * Field Enumeration Values:
18445  *
18446  * Enum | Value | Description
18447  * :---------------------------------------|:------|:------------
18448  * ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_E_DISD | 0x0 |
18449  * ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_E_END | 0x1 |
18450  *
18451  * Field Access Macros:
18452  *
18453  */
18454 /*
18455  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS
18456  *
18457  */
18458 #define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_E_DISD 0x0
18459 /*
18460  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS
18461  *
18462  */
18463 #define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_E_END 0x1
18464 
18465 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field. */
18466 #define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_LSB 16
18467 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field. */
18468 #define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_MSB 16
18469 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field. */
18470 #define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_WIDTH 1
18471 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field value. */
18472 #define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_SET_MSK 0x00010000
18473 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field value. */
18474 #define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_CLR_MSK 0xfffeffff
18475 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field. */
18476 #define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_RESET 0x0
18477 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS field value from a register. */
18478 #define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_GET(value) (((value) & 0x00010000) >> 16)
18479 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field value suitable for setting the register. */
18480 #define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_SET(value) (((value) << 16) & 0x00010000)
18481 
18482 /*
18483  * Field : txlatcolfis
18484  *
18485  * MMC Transmit Late Collision Frame Counter Interrupt Status
18486  *
18487  * This bit is set when the txlatecol counter reaches half of the maximum value or
18488  * the maximum value.
18489  *
18490  * Field Enumeration Values:
18491  *
18492  * Enum | Value | Description
18493  * :------------------------------------------|:------|:------------
18494  * ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_E_DISD | 0x0 |
18495  * ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_E_END | 0x1 |
18496  *
18497  * Field Access Macros:
18498  *
18499  */
18500 /*
18501  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS
18502  *
18503  */
18504 #define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_E_DISD 0x0
18505 /*
18506  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS
18507  *
18508  */
18509 #define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_E_END 0x1
18510 
18511 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field. */
18512 #define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_LSB 17
18513 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field. */
18514 #define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_MSB 17
18515 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field. */
18516 #define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_WIDTH 1
18517 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field value. */
18518 #define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_SET_MSK 0x00020000
18519 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field value. */
18520 #define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_CLR_MSK 0xfffdffff
18521 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field. */
18522 #define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_RESET 0x0
18523 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS field value from a register. */
18524 #define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_GET(value) (((value) & 0x00020000) >> 17)
18525 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field value suitable for setting the register. */
18526 #define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_SET(value) (((value) << 17) & 0x00020000)
18527 
18528 /*
18529  * Field : txexcolfis
18530  *
18531  * MMC Transmit Excessive Collision Frame Counter Interrupt Status
18532  *
18533  * This bit is set when the txexcesscol counter reaches half of the maximum value
18534  * or the maximum value.
18535  *
18536  * Field Enumeration Values:
18537  *
18538  * Enum | Value | Description
18539  * :-----------------------------------------|:------|:------------
18540  * ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_E_DISD | 0x0 |
18541  * ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_E_END | 0x1 |
18542  *
18543  * Field Access Macros:
18544  *
18545  */
18546 /*
18547  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS
18548  *
18549  */
18550 #define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_E_DISD 0x0
18551 /*
18552  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS
18553  *
18554  */
18555 #define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_E_END 0x1
18556 
18557 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field. */
18558 #define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_LSB 18
18559 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field. */
18560 #define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_MSB 18
18561 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field. */
18562 #define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_WIDTH 1
18563 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field value. */
18564 #define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_SET_MSK 0x00040000
18565 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field value. */
18566 #define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_CLR_MSK 0xfffbffff
18567 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field. */
18568 #define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_RESET 0x0
18569 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS field value from a register. */
18570 #define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_GET(value) (((value) & 0x00040000) >> 18)
18571 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field value suitable for setting the register. */
18572 #define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_SET(value) (((value) << 18) & 0x00040000)
18573 
18574 /*
18575  * Field : txcarerfis
18576  *
18577  * MMC Transmit Carrier Error Frame Counter Interrupt Status
18578  *
18579  * This bit is set when the txcarriererror counter reaches half of the maximum
18580  * value or the maximum value.
18581  *
18582  * Field Enumeration Values:
18583  *
18584  * Enum | Value | Description
18585  * :-----------------------------------------|:------|:------------
18586  * ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_E_DISD | 0x0 |
18587  * ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_E_END | 0x1 |
18588  *
18589  * Field Access Macros:
18590  *
18591  */
18592 /*
18593  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS
18594  *
18595  */
18596 #define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_E_DISD 0x0
18597 /*
18598  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS
18599  *
18600  */
18601 #define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_E_END 0x1
18602 
18603 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field. */
18604 #define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_LSB 19
18605 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field. */
18606 #define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_MSB 19
18607 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field. */
18608 #define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_WIDTH 1
18609 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field value. */
18610 #define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_SET_MSK 0x00080000
18611 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field value. */
18612 #define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_CLR_MSK 0xfff7ffff
18613 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field. */
18614 #define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_RESET 0x0
18615 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS field value from a register. */
18616 #define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_GET(value) (((value) & 0x00080000) >> 19)
18617 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field value suitable for setting the register. */
18618 #define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_SET(value) (((value) << 19) & 0x00080000)
18619 
18620 /*
18621  * Field : txgoctis
18622  *
18623  * MMC Transmit Good Octet Counter Interrupt Status
18624  *
18625  * This bit is set when the txoctetcount_g counter reaches half of the maximum
18626  * value or the maximum value.
18627  *
18628  * Field Enumeration Values:
18629  *
18630  * Enum | Value | Description
18631  * :---------------------------------------|:------|:------------
18632  * ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_E_DISD | 0x0 |
18633  * ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_E_END | 0x1 |
18634  *
18635  * Field Access Macros:
18636  *
18637  */
18638 /*
18639  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS
18640  *
18641  */
18642 #define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_E_DISD 0x0
18643 /*
18644  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS
18645  *
18646  */
18647 #define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_E_END 0x1
18648 
18649 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field. */
18650 #define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_LSB 20
18651 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field. */
18652 #define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_MSB 20
18653 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field. */
18654 #define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_WIDTH 1
18655 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field value. */
18656 #define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_SET_MSK 0x00100000
18657 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field value. */
18658 #define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_CLR_MSK 0xffefffff
18659 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field. */
18660 #define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_RESET 0x0
18661 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS field value from a register. */
18662 #define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_GET(value) (((value) & 0x00100000) >> 20)
18663 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field value suitable for setting the register. */
18664 #define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_SET(value) (((value) << 20) & 0x00100000)
18665 
18666 /*
18667  * Field : txgfrmis
18668  *
18669  * MMC Transmit Good Frame Counter Interrupt Status
18670  *
18671  * This bit is set when the txframecount_g counter reaches half of the maximum
18672  * value or the maximum value.
18673  *
18674  * Field Enumeration Values:
18675  *
18676  * Enum | Value | Description
18677  * :---------------------------------------|:------|:------------
18678  * ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_E_DISD | 0x0 |
18679  * ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_E_END | 0x1 |
18680  *
18681  * Field Access Macros:
18682  *
18683  */
18684 /*
18685  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS
18686  *
18687  */
18688 #define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_E_DISD 0x0
18689 /*
18690  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS
18691  *
18692  */
18693 #define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_E_END 0x1
18694 
18695 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field. */
18696 #define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_LSB 21
18697 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field. */
18698 #define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_MSB 21
18699 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field. */
18700 #define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_WIDTH 1
18701 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field value. */
18702 #define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_SET_MSK 0x00200000
18703 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field value. */
18704 #define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_CLR_MSK 0xffdfffff
18705 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field. */
18706 #define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_RESET 0x0
18707 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS field value from a register. */
18708 #define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_GET(value) (((value) & 0x00200000) >> 21)
18709 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field value suitable for setting the register. */
18710 #define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_SET(value) (((value) << 21) & 0x00200000)
18711 
18712 /*
18713  * Field : txexdeffis
18714  *
18715  * MMC Transmit Excessive Deferral Frame Counter Interrupt Status
18716  *
18717  * This bit is set when the txexcessdef counter reaches half of the maximum value
18718  * or the maximum value.
18719  *
18720  * Field Enumeration Values:
18721  *
18722  * Enum | Value | Description
18723  * :-----------------------------------------|:------|:------------
18724  * ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_E_DISD | 0x0 |
18725  * ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_E_END | 0x1 |
18726  *
18727  * Field Access Macros:
18728  *
18729  */
18730 /*
18731  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS
18732  *
18733  */
18734 #define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_E_DISD 0x0
18735 /*
18736  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS
18737  *
18738  */
18739 #define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_E_END 0x1
18740 
18741 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field. */
18742 #define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_LSB 22
18743 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field. */
18744 #define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_MSB 22
18745 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field. */
18746 #define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_WIDTH 1
18747 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field value. */
18748 #define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_SET_MSK 0x00400000
18749 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field value. */
18750 #define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_CLR_MSK 0xffbfffff
18751 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field. */
18752 #define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_RESET 0x0
18753 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS field value from a register. */
18754 #define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_GET(value) (((value) & 0x00400000) >> 22)
18755 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field value suitable for setting the register. */
18756 #define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_SET(value) (((value) << 22) & 0x00400000)
18757 
18758 /*
18759  * Field : txpausfis
18760  *
18761  * MMC Transmit Pause Frame Counter Interrupt Status
18762  *
18763  * This bit is set when the txpauseframeserror counter reaches half of the maximum
18764  * value or the maximum value.
18765  *
18766  * Field Enumeration Values:
18767  *
18768  * Enum | Value | Description
18769  * :----------------------------------------|:------|:------------
18770  * ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_E_DISD | 0x0 |
18771  * ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_E_END | 0x1 |
18772  *
18773  * Field Access Macros:
18774  *
18775  */
18776 /*
18777  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS
18778  *
18779  */
18780 #define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_E_DISD 0x0
18781 /*
18782  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS
18783  *
18784  */
18785 #define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_E_END 0x1
18786 
18787 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field. */
18788 #define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_LSB 23
18789 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field. */
18790 #define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_MSB 23
18791 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field. */
18792 #define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_WIDTH 1
18793 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field value. */
18794 #define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_SET_MSK 0x00800000
18795 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field value. */
18796 #define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_CLR_MSK 0xff7fffff
18797 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field. */
18798 #define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_RESET 0x0
18799 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS field value from a register. */
18800 #define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_GET(value) (((value) & 0x00800000) >> 23)
18801 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field value suitable for setting the register. */
18802 #define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_SET(value) (((value) << 23) & 0x00800000)
18803 
18804 /*
18805  * Field : txvlangfis
18806  *
18807  * MMC Transmit VLAN Good Frame Counter Interrupt Status
18808  *
18809  * This bit is set when the txvlanframes_g counter reaches half of the maximum
18810  * value or the maximum value.
18811  *
18812  * Field Enumeration Values:
18813  *
18814  * Enum | Value | Description
18815  * :-----------------------------------------|:------|:------------
18816  * ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_E_DISD | 0x0 |
18817  * ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_E_END | 0x1 |
18818  *
18819  * Field Access Macros:
18820  *
18821  */
18822 /*
18823  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS
18824  *
18825  */
18826 #define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_E_DISD 0x0
18827 /*
18828  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS
18829  *
18830  */
18831 #define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_E_END 0x1
18832 
18833 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field. */
18834 #define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_LSB 24
18835 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field. */
18836 #define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_MSB 24
18837 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field. */
18838 #define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_WIDTH 1
18839 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field value. */
18840 #define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_SET_MSK 0x01000000
18841 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field value. */
18842 #define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_CLR_MSK 0xfeffffff
18843 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field. */
18844 #define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_RESET 0x0
18845 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS field value from a register. */
18846 #define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_GET(value) (((value) & 0x01000000) >> 24)
18847 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field value suitable for setting the register. */
18848 #define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_SET(value) (((value) << 24) & 0x01000000)
18849 
18850 /*
18851  * Field : txosizegfis
18852  *
18853  * MMC Transmit Oversize Good Frame Counter Interrupt Status
18854  *
18855  * This bit is set when the txoversize_g counter reaches half of the maximum value
18856  * or the maximum value.
18857  *
18858  * Field Access Macros:
18859  *
18860  */
18861 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field. */
18862 #define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_LSB 25
18863 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field. */
18864 #define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_MSB 25
18865 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field. */
18866 #define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_WIDTH 1
18867 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field value. */
18868 #define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_SET_MSK 0x02000000
18869 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field value. */
18870 #define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_CLR_MSK 0xfdffffff
18871 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field. */
18872 #define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_RESET 0x0
18873 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS field value from a register. */
18874 #define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_GET(value) (((value) & 0x02000000) >> 25)
18875 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field value suitable for setting the register. */
18876 #define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_SET(value) (((value) << 25) & 0x02000000)
18877 
18878 /*
18879  * Field : reserved_31_26
18880  *
18881  * Reserved
18882  *
18883  * Field Access Macros:
18884  *
18885  */
18886 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26 register field. */
18887 #define ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_LSB 26
18888 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26 register field. */
18889 #define ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_MSB 31
18890 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26 register field. */
18891 #define ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_WIDTH 6
18892 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26 register field value. */
18893 #define ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_SET_MSK 0xfc000000
18894 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26 register field value. */
18895 #define ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_CLR_MSK 0x03ffffff
18896 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26 register field. */
18897 #define ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_RESET 0x0
18898 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26 field value from a register. */
18899 #define ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_GET(value) (((value) & 0xfc000000) >> 26)
18900 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26 register field value suitable for setting the register. */
18901 #define ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_SET(value) (((value) << 26) & 0xfc000000)
18902 
18903 #ifndef __ASSEMBLY__
18904 /*
18905  * WARNING: The C register and register group struct declarations are provided for
18906  * convenience and illustrative purposes. They should, however, be used with
18907  * caution as the C language standard provides no guarantees about the alignment or
18908  * atomicity of device memory accesses. The recommended practice for writing
18909  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18910  * alt_write_word() functions.
18911  *
18912  * The struct declaration for register ALT_EMAC_GMAC_MMC_TX_INT.
18913  */
18914 struct ALT_EMAC_GMAC_MMC_TX_INT_s
18915 {
18916  const uint32_t txgboctis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS */
18917  const uint32_t txgbfrmis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS */
18918  const uint32_t txbcgfis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS */
18919  const uint32_t txmcgfis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS */
18920  const uint32_t tx64octgbfis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS */
18921  const uint32_t tx65t127octgbfis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS */
18922  const uint32_t tx128t255octgbfis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS */
18923  const uint32_t tx256t511octgbfis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS */
18924  const uint32_t tx512t1023octgbfis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS */
18925  const uint32_t tx1024tmaxoctgbfis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS */
18926  const uint32_t txucgbfis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS */
18927  const uint32_t txmcgbfis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS */
18928  const uint32_t txbcgbfis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS */
18929  const uint32_t txuflowerfis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS */
18930  const uint32_t txscolgfis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS */
18931  const uint32_t txmcolgfis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS */
18932  const uint32_t txdeffis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS */
18933  const uint32_t txlatcolfis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS */
18934  const uint32_t txexcolfis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS */
18935  const uint32_t txcarerfis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS */
18936  const uint32_t txgoctis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS */
18937  const uint32_t txgfrmis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS */
18938  const uint32_t txexdeffis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS */
18939  const uint32_t txpausfis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS */
18940  const uint32_t txvlangfis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS */
18941  const uint32_t txosizegfis : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS */
18942  const uint32_t reserved_31_26 : 6; /* ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26 */
18943 };
18944 
18945 /* The typedef declaration for register ALT_EMAC_GMAC_MMC_TX_INT. */
18946 typedef volatile struct ALT_EMAC_GMAC_MMC_TX_INT_s ALT_EMAC_GMAC_MMC_TX_INT_t;
18947 #endif /* __ASSEMBLY__ */
18948 
18949 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT register. */
18950 #define ALT_EMAC_GMAC_MMC_TX_INT_RESET 0x00000000
18951 /* The byte offset of the ALT_EMAC_GMAC_MMC_TX_INT register from the beginning of the component. */
18952 #define ALT_EMAC_GMAC_MMC_TX_INT_OFST 0x108
18953 /* The address of the ALT_EMAC_GMAC_MMC_TX_INT register. */
18954 #define ALT_EMAC_GMAC_MMC_TX_INT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_TX_INT_OFST))
18955 
18956 /*
18957  * Register : gmacgrp_mmc_receive_interrupt_mask
18958  *
18959  * Regsiter 67 (MMC Receive Interrupt Mask Register)
18960  *
18961  * The MMC Receive Interrupt Mask register maintains the masks for the interrupts
18962  * generated when the receive statistic counters reach half of their maximum value,
18963  * or maximum value. This register is 32-bits wide.
18964  *
18965  * Register Layout
18966  *
18967  * Bits | Access | Reset | Description
18968  * :--------|:-------|:------|:----------------------------------------------
18969  * [0] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM
18970  * [1] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM
18971  * [2] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM
18972  * [3] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM
18973  * [4] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM
18974  * [5] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM
18975  * [6] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM
18976  * [7] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM
18977  * [8] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM
18978  * [9] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM
18979  * [10] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM
18980  * [11] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM
18981  * [12] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM
18982  * [13] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM
18983  * [14] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM
18984  * [15] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM
18985  * [16] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM
18986  * [17] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM
18987  * [18] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM
18988  * [19] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM
18989  * [20] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM
18990  * [21] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM
18991  * [22] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM
18992  * [23] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM
18993  * [24] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM
18994  * [25] | RW | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM
18995  * [31:26] | R | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26
18996  *
18997  */
18998 /*
18999  * Field : rxgbfrmim
19000  *
19001  * MMC Receive Good Bad Frame Counter Interrupt Mask
19002  *
19003  * Setting this bit masks the interrupt when the rxframecount_gb counter reaches
19004  * half of the maximum value or the maximum value.
19005  *
19006  * Field Enumeration Values:
19007  *
19008  * Enum | Value | Description
19009  * :-------------------------------------------------|:------|:------------
19010  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_E_NOMSKINTR | 0x0 |
19011  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_E_MSKINTR | 0x1 |
19012  *
19013  * Field Access Macros:
19014  *
19015  */
19016 /*
19017  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM
19018  *
19019  */
19020 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_E_NOMSKINTR 0x0
19021 /*
19022  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM
19023  *
19024  */
19025 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_E_MSKINTR 0x1
19026 
19027 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field. */
19028 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_LSB 0
19029 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field. */
19030 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_MSB 0
19031 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field. */
19032 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_WIDTH 1
19033 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field value. */
19034 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_SET_MSK 0x00000001
19035 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field value. */
19036 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_CLR_MSK 0xfffffffe
19037 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field. */
19038 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_RESET 0x0
19039 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM field value from a register. */
19040 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_GET(value) (((value) & 0x00000001) >> 0)
19041 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field value suitable for setting the register. */
19042 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_SET(value) (((value) << 0) & 0x00000001)
19043 
19044 /*
19045  * Field : rxgboctim
19046  *
19047  * MMC Receive Good Bad Octet Counter Interrupt Mask
19048  *
19049  * Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches
19050  * half of the maximum value or the maximum value.
19051  *
19052  * Field Enumeration Values:
19053  *
19054  * Enum | Value | Description
19055  * :-------------------------------------------------|:------|:------------
19056  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_E_NOMSKINTR | 0x0 |
19057  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_E_MSKINTR | 0x1 |
19058  *
19059  * Field Access Macros:
19060  *
19061  */
19062 /*
19063  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM
19064  *
19065  */
19066 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_E_NOMSKINTR 0x0
19067 /*
19068  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM
19069  *
19070  */
19071 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_E_MSKINTR 0x1
19072 
19073 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field. */
19074 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_LSB 1
19075 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field. */
19076 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_MSB 1
19077 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field. */
19078 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_WIDTH 1
19079 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field value. */
19080 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_SET_MSK 0x00000002
19081 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field value. */
19082 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_CLR_MSK 0xfffffffd
19083 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field. */
19084 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_RESET 0x0
19085 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM field value from a register. */
19086 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_GET(value) (((value) & 0x00000002) >> 1)
19087 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field value suitable for setting the register. */
19088 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_SET(value) (((value) << 1) & 0x00000002)
19089 
19090 /*
19091  * Field : rxgoctim
19092  *
19093  * MMC Receive Good Octet Counter Interrupt Mask
19094  *
19095  * Setting this bit masks the interrupt when the rxoctetcount_g counter reaches
19096  * half of the maximum value or the maximum value.
19097  *
19098  * Field Enumeration Values:
19099  *
19100  * Enum | Value | Description
19101  * :------------------------------------------------|:------|:------------
19102  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_E_NOMSKINTR | 0x0 |
19103  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_E_MSKINTR | 0x1 |
19104  *
19105  * Field Access Macros:
19106  *
19107  */
19108 /*
19109  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM
19110  *
19111  */
19112 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_E_NOMSKINTR 0x0
19113 /*
19114  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM
19115  *
19116  */
19117 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_E_MSKINTR 0x1
19118 
19119 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field. */
19120 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_LSB 2
19121 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field. */
19122 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_MSB 2
19123 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field. */
19124 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_WIDTH 1
19125 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field value. */
19126 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_SET_MSK 0x00000004
19127 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field value. */
19128 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_CLR_MSK 0xfffffffb
19129 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field. */
19130 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_RESET 0x0
19131 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM field value from a register. */
19132 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_GET(value) (((value) & 0x00000004) >> 2)
19133 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field value suitable for setting the register. */
19134 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_SET(value) (((value) << 2) & 0x00000004)
19135 
19136 /*
19137  * Field : rxbcgfim
19138  *
19139  * MMC Receive Broadcast Good Frame Counter Interrupt Mask
19140  *
19141  * Setting this bit masks the interrupt when the rxbroadcastframes_g counter
19142  * reaches half of the maximum value or the maximum value.
19143  *
19144  * Field Enumeration Values:
19145  *
19146  * Enum | Value | Description
19147  * :------------------------------------------------|:------|:------------
19148  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_E_NOMSKINTR | 0x0 |
19149  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_E_MSKINTR | 0x1 |
19150  *
19151  * Field Access Macros:
19152  *
19153  */
19154 /*
19155  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM
19156  *
19157  */
19158 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_E_NOMSKINTR 0x0
19159 /*
19160  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM
19161  *
19162  */
19163 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_E_MSKINTR 0x1
19164 
19165 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field. */
19166 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_LSB 3
19167 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field. */
19168 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_MSB 3
19169 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field. */
19170 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_WIDTH 1
19171 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field value. */
19172 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_SET_MSK 0x00000008
19173 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field value. */
19174 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_CLR_MSK 0xfffffff7
19175 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field. */
19176 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_RESET 0x0
19177 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM field value from a register. */
19178 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_GET(value) (((value) & 0x00000008) >> 3)
19179 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field value suitable for setting the register. */
19180 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_SET(value) (((value) << 3) & 0x00000008)
19181 
19182 /*
19183  * Field : rxmcgfim
19184  *
19185  * MMC Receive Multicast Good Frame Counter Interrupt Mask
19186  *
19187  * Setting this bit masks the interrupt when the rxmulticastframes_g counter
19188  * reaches half of the maximum value or the maximum value.
19189  *
19190  * Field Enumeration Values:
19191  *
19192  * Enum | Value | Description
19193  * :------------------------------------------------|:------|:------------
19194  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_E_NOMSKINTR | 0x0 |
19195  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_E_MSKINTR | 0x1 |
19196  *
19197  * Field Access Macros:
19198  *
19199  */
19200 /*
19201  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM
19202  *
19203  */
19204 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_E_NOMSKINTR 0x0
19205 /*
19206  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM
19207  *
19208  */
19209 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_E_MSKINTR 0x1
19210 
19211 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field. */
19212 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_LSB 4
19213 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field. */
19214 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_MSB 4
19215 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field. */
19216 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_WIDTH 1
19217 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field value. */
19218 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_SET_MSK 0x00000010
19219 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field value. */
19220 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_CLR_MSK 0xffffffef
19221 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field. */
19222 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_RESET 0x0
19223 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM field value from a register. */
19224 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_GET(value) (((value) & 0x00000010) >> 4)
19225 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field value suitable for setting the register. */
19226 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_SET(value) (((value) << 4) & 0x00000010)
19227 
19228 /*
19229  * Field : rxcrcerfim
19230  *
19231  * MMC Receive CRC Error Frame Counter Interrupt Mask
19232  *
19233  * Setting this bit masks the interrupt when the rxcrcerror counter reaches half of
19234  * the maximum value or the maximum value.
19235  *
19236  * Field Enumeration Values:
19237  *
19238  * Enum | Value | Description
19239  * :--------------------------------------------------|:------|:------------
19240  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_E_NOMSKINTR | 0x0 |
19241  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_E_MSKINTR | 0x1 |
19242  *
19243  * Field Access Macros:
19244  *
19245  */
19246 /*
19247  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM
19248  *
19249  */
19250 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_E_NOMSKINTR 0x0
19251 /*
19252  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM
19253  *
19254  */
19255 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_E_MSKINTR 0x1
19256 
19257 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field. */
19258 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_LSB 5
19259 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field. */
19260 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_MSB 5
19261 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field. */
19262 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_WIDTH 1
19263 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field value. */
19264 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_SET_MSK 0x00000020
19265 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field value. */
19266 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_CLR_MSK 0xffffffdf
19267 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field. */
19268 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_RESET 0x0
19269 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM field value from a register. */
19270 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_GET(value) (((value) & 0x00000020) >> 5)
19271 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field value suitable for setting the register. */
19272 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_SET(value) (((value) << 5) & 0x00000020)
19273 
19274 /*
19275  * Field : rxalgnerfim
19276  *
19277  * MMC Receive Alignment Error Frame Counter Interrupt Mask
19278  *
19279  * Setting this bit masks the interrupt when the rxalignmenterror counter reaches
19280  * half of the maximum value or the maximum value.
19281  *
19282  * Field Enumeration Values:
19283  *
19284  * Enum | Value | Description
19285  * :---------------------------------------------------|:------|:------------
19286  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_E_NOMSKINTR | 0x0 |
19287  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_E_MSKINTR | 0x1 |
19288  *
19289  * Field Access Macros:
19290  *
19291  */
19292 /*
19293  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM
19294  *
19295  */
19296 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_E_NOMSKINTR 0x0
19297 /*
19298  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM
19299  *
19300  */
19301 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_E_MSKINTR 0x1
19302 
19303 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field. */
19304 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_LSB 6
19305 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field. */
19306 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_MSB 6
19307 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field. */
19308 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_WIDTH 1
19309 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field value. */
19310 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_SET_MSK 0x00000040
19311 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field value. */
19312 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_CLR_MSK 0xffffffbf
19313 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field. */
19314 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_RESET 0x0
19315 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM field value from a register. */
19316 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_GET(value) (((value) & 0x00000040) >> 6)
19317 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field value suitable for setting the register. */
19318 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_SET(value) (((value) << 6) & 0x00000040)
19319 
19320 /*
19321  * Field : rxruntfim
19322  *
19323  * MMC Receive Runt Frame Counter Interrupt Mask
19324  *
19325  * Setting this bit masks the interrupt when the rxrunterror counter reaches half
19326  * of the maximum value or the maximum value.
19327  *
19328  * Field Enumeration Values:
19329  *
19330  * Enum | Value | Description
19331  * :-------------------------------------------------|:------|:------------
19332  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_E_NOMSKINTR | 0x0 |
19333  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_E_MSKINTR | 0x1 |
19334  *
19335  * Field Access Macros:
19336  *
19337  */
19338 /*
19339  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM
19340  *
19341  */
19342 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_E_NOMSKINTR 0x0
19343 /*
19344  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM
19345  *
19346  */
19347 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_E_MSKINTR 0x1
19348 
19349 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field. */
19350 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_LSB 7
19351 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field. */
19352 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_MSB 7
19353 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field. */
19354 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_WIDTH 1
19355 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field value. */
19356 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_SET_MSK 0x00000080
19357 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field value. */
19358 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_CLR_MSK 0xffffff7f
19359 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field. */
19360 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_RESET 0x0
19361 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM field value from a register. */
19362 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_GET(value) (((value) & 0x00000080) >> 7)
19363 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field value suitable for setting the register. */
19364 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_SET(value) (((value) << 7) & 0x00000080)
19365 
19366 /*
19367  * Field : rxjaberfim
19368  *
19369  * MMC Receive Jabber Error Frame Counter Interrupt Mask
19370  *
19371  * Setting this bit masks the interrupt when the rxjabbererror counter reaches half
19372  * of the maximum value or the maximum value.
19373  *
19374  * Field Enumeration Values:
19375  *
19376  * Enum | Value | Description
19377  * :--------------------------------------------------|:------|:------------
19378  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_E_NOMSKINTR | 0x0 |
19379  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_E_MSKINTR | 0x1 |
19380  *
19381  * Field Access Macros:
19382  *
19383  */
19384 /*
19385  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM
19386  *
19387  */
19388 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_E_NOMSKINTR 0x0
19389 /*
19390  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM
19391  *
19392  */
19393 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_E_MSKINTR 0x1
19394 
19395 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field. */
19396 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_LSB 8
19397 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field. */
19398 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_MSB 8
19399 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field. */
19400 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_WIDTH 1
19401 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field value. */
19402 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_SET_MSK 0x00000100
19403 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field value. */
19404 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_CLR_MSK 0xfffffeff
19405 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field. */
19406 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_RESET 0x0
19407 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM field value from a register. */
19408 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_GET(value) (((value) & 0x00000100) >> 8)
19409 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field value suitable for setting the register. */
19410 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_SET(value) (((value) << 8) & 0x00000100)
19411 
19412 /*
19413  * Field : rxusizegfim
19414  *
19415  * MMC Receive Undersize Good Frame Counter Interrupt Mask
19416  *
19417  * Setting this bit masks the interrupt when the rxundersize_g counter reaches half
19418  * of the maximum value or the maximum value.
19419  *
19420  * Field Enumeration Values:
19421  *
19422  * Enum | Value | Description
19423  * :---------------------------------------------------|:------|:------------
19424  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_E_NOMSKINTR | 0x0 |
19425  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_E_MSKINTR | 0x1 |
19426  *
19427  * Field Access Macros:
19428  *
19429  */
19430 /*
19431  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM
19432  *
19433  */
19434 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_E_NOMSKINTR 0x0
19435 /*
19436  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM
19437  *
19438  */
19439 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_E_MSKINTR 0x1
19440 
19441 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field. */
19442 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_LSB 9
19443 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field. */
19444 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_MSB 9
19445 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field. */
19446 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_WIDTH 1
19447 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field value. */
19448 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_SET_MSK 0x00000200
19449 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field value. */
19450 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_CLR_MSK 0xfffffdff
19451 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field. */
19452 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_RESET 0x0
19453 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM field value from a register. */
19454 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_GET(value) (((value) & 0x00000200) >> 9)
19455 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field value suitable for setting the register. */
19456 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_SET(value) (((value) << 9) & 0x00000200)
19457 
19458 /*
19459  * Field : rxosizegfim
19460  *
19461  * MMC Receive Oversize Good Frame Counter Interrupt Mask
19462  *
19463  * Setting this bit masks the interrupt when the rxoversize_g counter reaches half
19464  * of the maximum value or the maximum value.
19465  *
19466  * Field Enumeration Values:
19467  *
19468  * Enum | Value | Description
19469  * :---------------------------------------------------|:------|:------------
19470  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_E_NOMSKINTR | 0x0 |
19471  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_E_MSKINTR | 0x1 |
19472  *
19473  * Field Access Macros:
19474  *
19475  */
19476 /*
19477  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM
19478  *
19479  */
19480 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_E_NOMSKINTR 0x0
19481 /*
19482  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM
19483  *
19484  */
19485 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_E_MSKINTR 0x1
19486 
19487 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field. */
19488 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_LSB 10
19489 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field. */
19490 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_MSB 10
19491 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field. */
19492 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_WIDTH 1
19493 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field value. */
19494 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_SET_MSK 0x00000400
19495 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field value. */
19496 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_CLR_MSK 0xfffffbff
19497 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field. */
19498 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_RESET 0x0
19499 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM field value from a register. */
19500 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_GET(value) (((value) & 0x00000400) >> 10)
19501 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field value suitable for setting the register. */
19502 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_SET(value) (((value) << 10) & 0x00000400)
19503 
19504 /*
19505  * Field : rx64octgbfim
19506  *
19507  * MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask
19508  *
19509  * Setting this bit masks the interrupt when the rx64octets_gb counter reaches half
19510  * of the maximum value or the maximum value.
19511  *
19512  * Field Enumeration Values:
19513  *
19514  * Enum | Value | Description
19515  * :----------------------------------------------------|:------|:------------
19516  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_E_NOMSKINTR | 0x0 |
19517  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_E_MSKINTR | 0x1 |
19518  *
19519  * Field Access Macros:
19520  *
19521  */
19522 /*
19523  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM
19524  *
19525  */
19526 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_E_NOMSKINTR 0x0
19527 /*
19528  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM
19529  *
19530  */
19531 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_E_MSKINTR 0x1
19532 
19533 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field. */
19534 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_LSB 11
19535 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field. */
19536 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_MSB 11
19537 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field. */
19538 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_WIDTH 1
19539 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field value. */
19540 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_SET_MSK 0x00000800
19541 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field value. */
19542 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_CLR_MSK 0xfffff7ff
19543 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field. */
19544 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_RESET 0x0
19545 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM field value from a register. */
19546 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_GET(value) (((value) & 0x00000800) >> 11)
19547 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field value suitable for setting the register. */
19548 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_SET(value) (((value) << 11) & 0x00000800)
19549 
19550 /*
19551  * Field : rx65t127octgbfim
19552  *
19553  * MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask
19554  *
19555  * Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches
19556  * half of the maximum value or the maximum value.
19557  *
19558  * Field Enumeration Values:
19559  *
19560  * Enum | Value | Description
19561  * :--------------------------------------------------------|:------|:------------
19562  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_E_NOMSKINTR | 0x0 |
19563  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_E_MSKINTR | 0x1 |
19564  *
19565  * Field Access Macros:
19566  *
19567  */
19568 /*
19569  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM
19570  *
19571  */
19572 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_E_NOMSKINTR 0x0
19573 /*
19574  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM
19575  *
19576  */
19577 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_E_MSKINTR 0x1
19578 
19579 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field. */
19580 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_LSB 12
19581 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field. */
19582 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_MSB 12
19583 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field. */
19584 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_WIDTH 1
19585 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field value. */
19586 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_SET_MSK 0x00001000
19587 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field value. */
19588 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_CLR_MSK 0xffffefff
19589 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field. */
19590 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_RESET 0x0
19591 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM field value from a register. */
19592 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_GET(value) (((value) & 0x00001000) >> 12)
19593 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field value suitable for setting the register. */
19594 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_SET(value) (((value) << 12) & 0x00001000)
19595 
19596 /*
19597  * Field : rx128t255octgbfim
19598  *
19599  * MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask
19600  *
19601  * Setting this bit masks the interrupt when the rx128to255octets_gb counter
19602  * reaches half of the maximum value or the maximum value.
19603  *
19604  * Field Enumeration Values:
19605  *
19606  * Enum | Value | Description
19607  * :---------------------------------------------------------|:------|:------------
19608  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_E_NOMSKINTR | 0x0 |
19609  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_E_MSKINTR | 0x1 |
19610  *
19611  * Field Access Macros:
19612  *
19613  */
19614 /*
19615  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM
19616  *
19617  */
19618 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_E_NOMSKINTR 0x0
19619 /*
19620  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM
19621  *
19622  */
19623 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_E_MSKINTR 0x1
19624 
19625 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field. */
19626 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_LSB 13
19627 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field. */
19628 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_MSB 13
19629 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field. */
19630 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_WIDTH 1
19631 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field value. */
19632 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_SET_MSK 0x00002000
19633 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field value. */
19634 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_CLR_MSK 0xffffdfff
19635 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field. */
19636 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_RESET 0x0
19637 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM field value from a register. */
19638 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_GET(value) (((value) & 0x00002000) >> 13)
19639 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field value suitable for setting the register. */
19640 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_SET(value) (((value) << 13) & 0x00002000)
19641 
19642 /*
19643  * Field : rx256t511octgbfim
19644  *
19645  * MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask
19646  *
19647  * Setting this bit masks the interrupt when the rx256to511octets_gb counter
19648  * reaches half of the maximum value or the maximum value.
19649  *
19650  * Field Enumeration Values:
19651  *
19652  * Enum | Value | Description
19653  * :---------------------------------------------------------|:------|:------------
19654  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_E_NOMSKINTR | 0x0 |
19655  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_E_MSKINTR | 0x1 |
19656  *
19657  * Field Access Macros:
19658  *
19659  */
19660 /*
19661  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM
19662  *
19663  */
19664 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_E_NOMSKINTR 0x0
19665 /*
19666  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM
19667  *
19668  */
19669 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_E_MSKINTR 0x1
19670 
19671 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field. */
19672 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_LSB 14
19673 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field. */
19674 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_MSB 14
19675 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field. */
19676 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_WIDTH 1
19677 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field value. */
19678 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_SET_MSK 0x00004000
19679 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field value. */
19680 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_CLR_MSK 0xffffbfff
19681 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field. */
19682 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_RESET 0x0
19683 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM field value from a register. */
19684 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_GET(value) (((value) & 0x00004000) >> 14)
19685 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field value suitable for setting the register. */
19686 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_SET(value) (((value) << 14) & 0x00004000)
19687 
19688 /*
19689  * Field : rx512t1023octgbfim
19690  *
19691  * MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask
19692  *
19693  * Setting this bit masks the interrupt when the rx512to1023octets_gb counter
19694  * reaches half of the maximum value or the maximum value.
19695  *
19696  * Field Enumeration Values:
19697  *
19698  * Enum | Value | Description
19699  * :----------------------------------------------------------|:------|:------------
19700  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_E_NOMSKINTR | 0x0 |
19701  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_E_MSKINTR | 0x1 |
19702  *
19703  * Field Access Macros:
19704  *
19705  */
19706 /*
19707  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM
19708  *
19709  */
19710 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_E_NOMSKINTR 0x0
19711 /*
19712  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM
19713  *
19714  */
19715 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_E_MSKINTR 0x1
19716 
19717 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field. */
19718 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_LSB 15
19719 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field. */
19720 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_MSB 15
19721 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field. */
19722 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_WIDTH 1
19723 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field value. */
19724 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_SET_MSK 0x00008000
19725 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field value. */
19726 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_CLR_MSK 0xffff7fff
19727 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field. */
19728 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_RESET 0x0
19729 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM field value from a register. */
19730 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_GET(value) (((value) & 0x00008000) >> 15)
19731 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field value suitable for setting the register. */
19732 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_SET(value) (((value) << 15) & 0x00008000)
19733 
19734 /*
19735  * Field : rx1024tmaxoctgbfim
19736  *
19737  * MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask
19738  *
19739  * Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter
19740  * reaches half of the maximum value or the maximum value.
19741  *
19742  * Field Enumeration Values:
19743  *
19744  * Enum | Value | Description
19745  * :----------------------------------------------------------|:------|:------------
19746  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_E_NOMSKINTR | 0x0 |
19747  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_E_MSKINTR | 0x1 |
19748  *
19749  * Field Access Macros:
19750  *
19751  */
19752 /*
19753  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM
19754  *
19755  */
19756 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_E_NOMSKINTR 0x0
19757 /*
19758  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM
19759  *
19760  */
19761 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_E_MSKINTR 0x1
19762 
19763 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field. */
19764 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_LSB 16
19765 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field. */
19766 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_MSB 16
19767 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field. */
19768 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_WIDTH 1
19769 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field value. */
19770 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_SET_MSK 0x00010000
19771 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field value. */
19772 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_CLR_MSK 0xfffeffff
19773 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field. */
19774 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_RESET 0x0
19775 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM field value from a register. */
19776 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_GET(value) (((value) & 0x00010000) >> 16)
19777 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field value suitable for setting the register. */
19778 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_SET(value) (((value) << 16) & 0x00010000)
19779 
19780 /*
19781  * Field : rxucgfim
19782  *
19783  * MMC Receive Unicast Good Frame Counter Interrupt Mask
19784  *
19785  * Setting this bit masks the interrupt when the rxunicastframes_g counter reaches
19786  * half of the maximum value or the maximum value.
19787  *
19788  * Field Enumeration Values:
19789  *
19790  * Enum | Value | Description
19791  * :------------------------------------------------|:------|:------------
19792  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_E_NOMSKINTR | 0x0 |
19793  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_E_MSKINTR | 0x1 |
19794  *
19795  * Field Access Macros:
19796  *
19797  */
19798 /*
19799  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM
19800  *
19801  */
19802 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_E_NOMSKINTR 0x0
19803 /*
19804  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM
19805  *
19806  */
19807 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_E_MSKINTR 0x1
19808 
19809 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field. */
19810 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_LSB 17
19811 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field. */
19812 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_MSB 17
19813 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field. */
19814 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_WIDTH 1
19815 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field value. */
19816 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_SET_MSK 0x00020000
19817 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field value. */
19818 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_CLR_MSK 0xfffdffff
19819 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field. */
19820 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_RESET 0x0
19821 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM field value from a register. */
19822 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_GET(value) (((value) & 0x00020000) >> 17)
19823 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field value suitable for setting the register. */
19824 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_SET(value) (((value) << 17) & 0x00020000)
19825 
19826 /*
19827  * Field : rxlenerfim
19828  *
19829  * MMC Receive Length Error Frame Counter Interrupt Mask
19830  *
19831  * Setting this bit masks the interrupt when the rxlengtherror counter reaches half
19832  * of the maximum value or the maximum value.
19833  *
19834  * Field Enumeration Values:
19835  *
19836  * Enum | Value | Description
19837  * :--------------------------------------------------|:------|:------------
19838  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_E_NOMSKINTR | 0x0 |
19839  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_E_MSKINTR | 0x1 |
19840  *
19841  * Field Access Macros:
19842  *
19843  */
19844 /*
19845  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM
19846  *
19847  */
19848 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_E_NOMSKINTR 0x0
19849 /*
19850  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM
19851  *
19852  */
19853 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_E_MSKINTR 0x1
19854 
19855 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field. */
19856 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_LSB 18
19857 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field. */
19858 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_MSB 18
19859 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field. */
19860 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_WIDTH 1
19861 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field value. */
19862 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_SET_MSK 0x00040000
19863 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field value. */
19864 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_CLR_MSK 0xfffbffff
19865 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field. */
19866 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_RESET 0x0
19867 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM field value from a register. */
19868 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_GET(value) (((value) & 0x00040000) >> 18)
19869 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field value suitable for setting the register. */
19870 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_SET(value) (((value) << 18) & 0x00040000)
19871 
19872 /*
19873  * Field : rxorangefim
19874  *
19875  * MMC Receive Out Of Range Error Frame Counter Interrupt Mask
19876  *
19877  * Setting this bit masks the interrupt when the rxoutofrangetype counter reaches
19878  * half of the maximum value or the maximum value.
19879  *
19880  * Field Enumeration Values:
19881  *
19882  * Enum | Value | Description
19883  * :---------------------------------------------------|:------|:------------
19884  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_E_NOMSKINTR | 0x0 |
19885  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_E_MSKINTR | 0x1 |
19886  *
19887  * Field Access Macros:
19888  *
19889  */
19890 /*
19891  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM
19892  *
19893  */
19894 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_E_NOMSKINTR 0x0
19895 /*
19896  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM
19897  *
19898  */
19899 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_E_MSKINTR 0x1
19900 
19901 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field. */
19902 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_LSB 19
19903 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field. */
19904 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_MSB 19
19905 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field. */
19906 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_WIDTH 1
19907 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field value. */
19908 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_SET_MSK 0x00080000
19909 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field value. */
19910 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_CLR_MSK 0xfff7ffff
19911 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field. */
19912 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_RESET 0x0
19913 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM field value from a register. */
19914 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_GET(value) (((value) & 0x00080000) >> 19)
19915 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field value suitable for setting the register. */
19916 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_SET(value) (((value) << 19) & 0x00080000)
19917 
19918 /*
19919  * Field : rxpausfim
19920  *
19921  * MMC Receive Pause Frame Counter Interrupt Mask
19922  *
19923  * Setting this bit masks the interrupt when the rxpauseframes counter reaches half
19924  * of the maximum value or the maximum value.
19925  *
19926  * Field Enumeration Values:
19927  *
19928  * Enum | Value | Description
19929  * :-------------------------------------------------|:------|:------------
19930  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_E_NOMSKINTR | 0x0 |
19931  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_E_MSKINTR | 0x1 |
19932  *
19933  * Field Access Macros:
19934  *
19935  */
19936 /*
19937  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM
19938  *
19939  */
19940 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_E_NOMSKINTR 0x0
19941 /*
19942  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM
19943  *
19944  */
19945 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_E_MSKINTR 0x1
19946 
19947 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field. */
19948 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_LSB 20
19949 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field. */
19950 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_MSB 20
19951 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field. */
19952 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_WIDTH 1
19953 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field value. */
19954 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_SET_MSK 0x00100000
19955 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field value. */
19956 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_CLR_MSK 0xffefffff
19957 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field. */
19958 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_RESET 0x0
19959 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM field value from a register. */
19960 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_GET(value) (((value) & 0x00100000) >> 20)
19961 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field value suitable for setting the register. */
19962 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_SET(value) (((value) << 20) & 0x00100000)
19963 
19964 /*
19965  * Field : rxfovfim
19966  *
19967  * MMC Receive FIFO Overflow Frame Counter Interrupt Mask
19968  *
19969  * Setting this bit masks the interrupt when the rxfifooverflow counter reaches
19970  * half of the maximum value or the maximum value.
19971  *
19972  * Field Enumeration Values:
19973  *
19974  * Enum | Value | Description
19975  * :------------------------------------------------|:------|:------------
19976  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_E_NOMSKINTR | 0x0 |
19977  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_E_MSKINTR | 0x1 |
19978  *
19979  * Field Access Macros:
19980  *
19981  */
19982 /*
19983  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM
19984  *
19985  */
19986 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_E_NOMSKINTR 0x0
19987 /*
19988  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM
19989  *
19990  */
19991 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_E_MSKINTR 0x1
19992 
19993 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field. */
19994 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_LSB 21
19995 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field. */
19996 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_MSB 21
19997 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field. */
19998 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_WIDTH 1
19999 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field value. */
20000 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_SET_MSK 0x00200000
20001 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field value. */
20002 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_CLR_MSK 0xffdfffff
20003 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field. */
20004 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_RESET 0x0
20005 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM field value from a register. */
20006 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_GET(value) (((value) & 0x00200000) >> 21)
20007 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field value suitable for setting the register. */
20008 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_SET(value) (((value) << 21) & 0x00200000)
20009 
20010 /*
20011  * Field : rxvlangbfim
20012  *
20013  * MMC Receive VLAN Good Bad Frame Counter Interrupt Mask
20014  *
20015  * Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches
20016  * half of the maximum value or the maximum value.
20017  *
20018  * Field Enumeration Values:
20019  *
20020  * Enum | Value | Description
20021  * :---------------------------------------------------|:------|:------------
20022  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_E_NOMSKINTR | 0x0 |
20023  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_E_MSKINTR | 0x1 |
20024  *
20025  * Field Access Macros:
20026  *
20027  */
20028 /*
20029  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM
20030  *
20031  */
20032 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_E_NOMSKINTR 0x0
20033 /*
20034  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM
20035  *
20036  */
20037 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_E_MSKINTR 0x1
20038 
20039 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field. */
20040 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_LSB 22
20041 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field. */
20042 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_MSB 22
20043 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field. */
20044 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_WIDTH 1
20045 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field value. */
20046 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_SET_MSK 0x00400000
20047 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field value. */
20048 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_CLR_MSK 0xffbfffff
20049 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field. */
20050 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_RESET 0x0
20051 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM field value from a register. */
20052 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_GET(value) (((value) & 0x00400000) >> 22)
20053 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field value suitable for setting the register. */
20054 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_SET(value) (((value) << 22) & 0x00400000)
20055 
20056 /*
20057  * Field : rxwdogfim
20058  *
20059  * MMC Receive Watchdog Error Frame Counter Interrupt Mask
20060  *
20061  * Setting this bit masks the interrupt when the rxwatchdog counter reaches half of
20062  * the maximum value or the maximum value.
20063  *
20064  * Field Enumeration Values:
20065  *
20066  * Enum | Value | Description
20067  * :-------------------------------------------------|:------|:------------
20068  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_E_NOMSKINTR | 0x0 |
20069  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_E_MSKINTR | 0x1 |
20070  *
20071  * Field Access Macros:
20072  *
20073  */
20074 /*
20075  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM
20076  *
20077  */
20078 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_E_NOMSKINTR 0x0
20079 /*
20080  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM
20081  *
20082  */
20083 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_E_MSKINTR 0x1
20084 
20085 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field. */
20086 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_LSB 23
20087 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field. */
20088 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_MSB 23
20089 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field. */
20090 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_WIDTH 1
20091 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field value. */
20092 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_SET_MSK 0x00800000
20093 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field value. */
20094 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_CLR_MSK 0xff7fffff
20095 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field. */
20096 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_RESET 0x0
20097 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM field value from a register. */
20098 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_GET(value) (((value) & 0x00800000) >> 23)
20099 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field value suitable for setting the register. */
20100 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_SET(value) (((value) << 23) & 0x00800000)
20101 
20102 /*
20103  * Field : rxrcverrfim
20104  *
20105  * MMC Receive Error Frame Counter Interrupt Mask
20106  *
20107  * Setting this bit masks the interrupt when the rxrcverror error counter reaches
20108  * half the maximum value, and also when it reaches the maximum value.
20109  *
20110  * Field Enumeration Values:
20111  *
20112  * Enum | Value | Description
20113  * :---------------------------------------------------|:------|:------------
20114  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_E_NOMSKINTR | 0x0 |
20115  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_E_MSKINTR | 0x1 |
20116  *
20117  * Field Access Macros:
20118  *
20119  */
20120 /*
20121  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM
20122  *
20123  */
20124 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_E_NOMSKINTR 0x0
20125 /*
20126  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM
20127  *
20128  */
20129 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_E_MSKINTR 0x1
20130 
20131 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field. */
20132 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_LSB 24
20133 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field. */
20134 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_MSB 24
20135 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field. */
20136 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_WIDTH 1
20137 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field value. */
20138 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_SET_MSK 0x01000000
20139 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field value. */
20140 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_CLR_MSK 0xfeffffff
20141 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field. */
20142 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_RESET 0x0
20143 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM field value from a register. */
20144 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_GET(value) (((value) & 0x01000000) >> 24)
20145 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field value suitable for setting the register. */
20146 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_SET(value) (((value) << 24) & 0x01000000)
20147 
20148 /*
20149  * Field : rxctrlfim
20150  *
20151  * MMC Receive Control Frame Counter Interrupt Mask
20152  *
20153  * Setting this bit masks the interrupt when the rxctrlframes counter reaches half
20154  * the maximum value, and also when it reaches the maximum value.
20155  *
20156  * Field Enumeration Values:
20157  *
20158  * Enum | Value | Description
20159  * :------------------------------------------------|:------|:------------
20160  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_E_NOMSKINTR | 0x0 |
20161  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_E_MSKINTR | 0x1 |
20162  *
20163  * Field Access Macros:
20164  *
20165  */
20166 /*
20167  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM
20168  *
20169  */
20170 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_E_NOMSKINTR 0x0
20171 /*
20172  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM
20173  *
20174  */
20175 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_E_MSKINTR 0x1
20176 
20177 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field. */
20178 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_LSB 25
20179 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field. */
20180 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_MSB 25
20181 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field. */
20182 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_WIDTH 1
20183 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field value. */
20184 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_SET_MSK 0x02000000
20185 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field value. */
20186 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_CLR_MSK 0xfdffffff
20187 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field. */
20188 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_RESET 0x0
20189 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM field value from a register. */
20190 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_GET(value) (((value) & 0x02000000) >> 25)
20191 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field value suitable for setting the register. */
20192 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_SET(value) (((value) << 25) & 0x02000000)
20193 
20194 /*
20195  * Field : reserved_31_26
20196  *
20197  * Reserved
20198  *
20199  * Field Access Macros:
20200  *
20201  */
20202 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26 register field. */
20203 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_LSB 26
20204 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26 register field. */
20205 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_MSB 31
20206 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26 register field. */
20207 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_WIDTH 6
20208 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26 register field value. */
20209 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_SET_MSK 0xfc000000
20210 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26 register field value. */
20211 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_CLR_MSK 0x03ffffff
20212 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26 register field. */
20213 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_RESET 0x0
20214 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26 field value from a register. */
20215 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_GET(value) (((value) & 0xfc000000) >> 26)
20216 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26 register field value suitable for setting the register. */
20217 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_SET(value) (((value) << 26) & 0xfc000000)
20218 
20219 #ifndef __ASSEMBLY__
20220 /*
20221  * WARNING: The C register and register group struct declarations are provided for
20222  * convenience and illustrative purposes. They should, however, be used with
20223  * caution as the C language standard provides no guarantees about the alignment or
20224  * atomicity of device memory accesses. The recommended practice for writing
20225  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20226  * alt_write_word() functions.
20227  *
20228  * The struct declaration for register ALT_EMAC_GMAC_MMC_RX_INT_MSK.
20229  */
20230 struct ALT_EMAC_GMAC_MMC_RX_INT_MSK_s
20231 {
20232  uint32_t rxgbfrmim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM */
20233  uint32_t rxgboctim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM */
20234  uint32_t rxgoctim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM */
20235  uint32_t rxbcgfim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM */
20236  uint32_t rxmcgfim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM */
20237  uint32_t rxcrcerfim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM */
20238  uint32_t rxalgnerfim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM */
20239  uint32_t rxruntfim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM */
20240  uint32_t rxjaberfim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM */
20241  uint32_t rxusizegfim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM */
20242  uint32_t rxosizegfim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM */
20243  uint32_t rx64octgbfim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM */
20244  uint32_t rx65t127octgbfim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM */
20245  uint32_t rx128t255octgbfim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM */
20246  uint32_t rx256t511octgbfim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM */
20247  uint32_t rx512t1023octgbfim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM */
20248  uint32_t rx1024tmaxoctgbfim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM */
20249  uint32_t rxucgfim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM */
20250  uint32_t rxlenerfim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM */
20251  uint32_t rxorangefim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM */
20252  uint32_t rxpausfim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM */
20253  uint32_t rxfovfim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM */
20254  uint32_t rxvlangbfim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM */
20255  uint32_t rxwdogfim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM */
20256  uint32_t rxrcverrfim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM */
20257  uint32_t rxctrlfim : 1; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM */
20258  const uint32_t reserved_31_26 : 6; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26 */
20259 };
20260 
20261 /* The typedef declaration for register ALT_EMAC_GMAC_MMC_RX_INT_MSK. */
20262 typedef volatile struct ALT_EMAC_GMAC_MMC_RX_INT_MSK_s ALT_EMAC_GMAC_MMC_RX_INT_MSK_t;
20263 #endif /* __ASSEMBLY__ */
20264 
20265 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK register. */
20266 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RESET 0x00000000
20267 /* The byte offset of the ALT_EMAC_GMAC_MMC_RX_INT_MSK register from the beginning of the component. */
20268 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OFST 0x10c
20269 /* The address of the ALT_EMAC_GMAC_MMC_RX_INT_MSK register. */
20270 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_RX_INT_MSK_OFST))
20271 
20272 /*
20273  * Register : gmacgrp_mmc_transmit_interrupt_mask
20274  *
20275  * <b> Register 68 (MMC Transmit Interrupt Mask Register) </b>
20276  *
20277  * The MMC Transmit Interrupt Mask register maintains the masks for the interrupts
20278  * generated when the transmit statistic counters reach half of their maximum value
20279  * or maximum value. This register is 32-bits wide.
20280  *
20281  * Register Layout
20282  *
20283  * Bits | Access | Reset | Description
20284  * :--------|:-------|:------|:----------------------------------------------
20285  * [0] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM
20286  * [1] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM
20287  * [2] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM
20288  * [3] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM
20289  * [4] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM
20290  * [5] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM
20291  * [6] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM
20292  * [7] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM
20293  * [8] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM
20294  * [9] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM
20295  * [10] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM
20296  * [11] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM
20297  * [12] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM
20298  * [13] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM
20299  * [14] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM
20300  * [15] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM
20301  * [16] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM
20302  * [17] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM
20303  * [18] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM
20304  * [19] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM
20305  * [20] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM
20306  * [21] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM
20307  * [22] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM
20308  * [23] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM
20309  * [24] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM
20310  * [25] | RW | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM
20311  * [31:26] | R | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MSK_RSVD_31_26
20312  *
20313  */
20314 /*
20315  * Field : txgboctim
20316  *
20317  * MMC Transmit Good Bad Octet Counter Interrupt Mask
20318  *
20319  * Setting this bit masks the interrupt when the txoctetcount_gb counter reaches
20320  * half of the maximum value or the maximum value.
20321  *
20322  * Field Enumeration Values:
20323  *
20324  * Enum | Value | Description
20325  * :-------------------------------------------------|:------|:------------
20326  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_E_NOMSKINTR | 0x0 |
20327  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_E_MSKINTR | 0x1 |
20328  *
20329  * Field Access Macros:
20330  *
20331  */
20332 /*
20333  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM
20334  *
20335  */
20336 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_E_NOMSKINTR 0x0
20337 /*
20338  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM
20339  *
20340  */
20341 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_E_MSKINTR 0x1
20342 
20343 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field. */
20344 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_LSB 0
20345 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field. */
20346 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_MSB 0
20347 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field. */
20348 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_WIDTH 1
20349 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field value. */
20350 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_SET_MSK 0x00000001
20351 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field value. */
20352 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_CLR_MSK 0xfffffffe
20353 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field. */
20354 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_RESET 0x0
20355 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM field value from a register. */
20356 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_GET(value) (((value) & 0x00000001) >> 0)
20357 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field value suitable for setting the register. */
20358 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_SET(value) (((value) << 0) & 0x00000001)
20359 
20360 /*
20361  * Field : txgbfrmim
20362  *
20363  * MMC Transmit Good Bad Frame Counter Interrupt Mask
20364  *
20365  * Setting this bit masks the interrupt when the txframecount_gb counter reaches
20366  * half of the maximum value or the maximum value.
20367  *
20368  * Field Enumeration Values:
20369  *
20370  * Enum | Value | Description
20371  * :-------------------------------------------------|:------|:------------
20372  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_E_NOMSKINTR | 0x0 |
20373  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_E_MSKINTR | 0x1 |
20374  *
20375  * Field Access Macros:
20376  *
20377  */
20378 /*
20379  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM
20380  *
20381  */
20382 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_E_NOMSKINTR 0x0
20383 /*
20384  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM
20385  *
20386  */
20387 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_E_MSKINTR 0x1
20388 
20389 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field. */
20390 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_LSB 1
20391 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field. */
20392 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_MSB 1
20393 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field. */
20394 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_WIDTH 1
20395 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field value. */
20396 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_SET_MSK 0x00000002
20397 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field value. */
20398 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_CLR_MSK 0xfffffffd
20399 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field. */
20400 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_RESET 0x0
20401 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM field value from a register. */
20402 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_GET(value) (((value) & 0x00000002) >> 1)
20403 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field value suitable for setting the register. */
20404 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_SET(value) (((value) << 1) & 0x00000002)
20405 
20406 /*
20407  * Field : txbcgfim
20408  *
20409  * MMC Transmit Broadcast Good Frame Counter Interrupt Mask
20410  *
20411  * Setting this bit masks the interrupt when the txbroadcastframes_g counter
20412  * reaches half of the maximum value or the maximum value.
20413  *
20414  * Field Enumeration Values:
20415  *
20416  * Enum | Value | Description
20417  * :------------------------------------------------|:------|:------------
20418  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_E_NOMSKINTR | 0x0 |
20419  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_E_MSKINTR | 0x1 |
20420  *
20421  * Field Access Macros:
20422  *
20423  */
20424 /*
20425  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM
20426  *
20427  */
20428 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_E_NOMSKINTR 0x0
20429 /*
20430  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM
20431  *
20432  */
20433 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_E_MSKINTR 0x1
20434 
20435 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field. */
20436 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_LSB 2
20437 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field. */
20438 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_MSB 2
20439 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field. */
20440 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_WIDTH 1
20441 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field value. */
20442 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_SET_MSK 0x00000004
20443 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field value. */
20444 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_CLR_MSK 0xfffffffb
20445 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field. */
20446 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_RESET 0x0
20447 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM field value from a register. */
20448 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_GET(value) (((value) & 0x00000004) >> 2)
20449 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field value suitable for setting the register. */
20450 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_SET(value) (((value) << 2) & 0x00000004)
20451 
20452 /*
20453  * Field : txmcgfim
20454  *
20455  * MMC Transmit Multicast Good Frame Counter Interrupt Mask
20456  *
20457  * Setting this bit masks the interrupt when the txmulticastframes_g counter
20458  * reaches half of the maximum value or the maximum value.
20459  *
20460  * Field Enumeration Values:
20461  *
20462  * Enum | Value | Description
20463  * :------------------------------------------------|:------|:------------
20464  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_E_NOMSKINTR | 0x0 |
20465  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_E_MSKINTR | 0x1 |
20466  *
20467  * Field Access Macros:
20468  *
20469  */
20470 /*
20471  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM
20472  *
20473  */
20474 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_E_NOMSKINTR 0x0
20475 /*
20476  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM
20477  *
20478  */
20479 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_E_MSKINTR 0x1
20480 
20481 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field. */
20482 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_LSB 3
20483 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field. */
20484 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_MSB 3
20485 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field. */
20486 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_WIDTH 1
20487 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field value. */
20488 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_SET_MSK 0x00000008
20489 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field value. */
20490 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_CLR_MSK 0xfffffff7
20491 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field. */
20492 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_RESET 0x0
20493 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM field value from a register. */
20494 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_GET(value) (((value) & 0x00000008) >> 3)
20495 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field value suitable for setting the register. */
20496 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_SET(value) (((value) << 3) & 0x00000008)
20497 
20498 /*
20499  * Field : tx64octgbfim
20500  *
20501  * MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask
20502  *
20503  * Setting this bit masks the interrupt when the tx64octets_gb counter reaches half
20504  * of the maximum value or the maximum value.
20505  *
20506  * Field Enumeration Values:
20507  *
20508  * Enum | Value | Description
20509  * :----------------------------------------------------|:------|:------------
20510  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_E_NOMSKINTR | 0x0 |
20511  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_E_MSKINTR | 0x1 |
20512  *
20513  * Field Access Macros:
20514  *
20515  */
20516 /*
20517  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM
20518  *
20519  */
20520 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_E_NOMSKINTR 0x0
20521 /*
20522  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM
20523  *
20524  */
20525 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_E_MSKINTR 0x1
20526 
20527 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field. */
20528 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_LSB 4
20529 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field. */
20530 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_MSB 4
20531 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field. */
20532 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_WIDTH 1
20533 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field value. */
20534 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_SET_MSK 0x00000010
20535 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field value. */
20536 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_CLR_MSK 0xffffffef
20537 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field. */
20538 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_RESET 0x0
20539 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM field value from a register. */
20540 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_GET(value) (((value) & 0x00000010) >> 4)
20541 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field value suitable for setting the register. */
20542 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_SET(value) (((value) << 4) & 0x00000010)
20543 
20544 /*
20545  * Field : tx65t127octgbfim
20546  *
20547  * MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask
20548  *
20549  * Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches
20550  * half of the maximum value or the maximum value.
20551  *
20552  * Field Enumeration Values:
20553  *
20554  * Enum | Value | Description
20555  * :--------------------------------------------------------|:------|:------------
20556  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_E_NOMSKINTR | 0x0 |
20557  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_E_MSKINTR | 0x1 |
20558  *
20559  * Field Access Macros:
20560  *
20561  */
20562 /*
20563  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM
20564  *
20565  */
20566 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_E_NOMSKINTR 0x0
20567 /*
20568  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM
20569  *
20570  */
20571 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_E_MSKINTR 0x1
20572 
20573 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field. */
20574 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_LSB 5
20575 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field. */
20576 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_MSB 5
20577 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field. */
20578 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_WIDTH 1
20579 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field value. */
20580 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_SET_MSK 0x00000020
20581 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field value. */
20582 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_CLR_MSK 0xffffffdf
20583 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field. */
20584 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_RESET 0x0
20585 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM field value from a register. */
20586 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_GET(value) (((value) & 0x00000020) >> 5)
20587 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field value suitable for setting the register. */
20588 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_SET(value) (((value) << 5) & 0x00000020)
20589 
20590 /*
20591  * Field : tx128t255octgbfim
20592  *
20593  * MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask
20594  *
20595  * Setting this bit masks the interrupt when the tx128to255octets_gb counter
20596  * reaches half of the maximum value or the maximum value.
20597  *
20598  * Field Enumeration Values:
20599  *
20600  * Enum | Value | Description
20601  * :---------------------------------------------------------|:------|:------------
20602  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_E_NOMSKINTR | 0x0 |
20603  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_E_MSKINTR | 0x1 |
20604  *
20605  * Field Access Macros:
20606  *
20607  */
20608 /*
20609  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM
20610  *
20611  */
20612 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_E_NOMSKINTR 0x0
20613 /*
20614  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM
20615  *
20616  */
20617 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_E_MSKINTR 0x1
20618 
20619 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field. */
20620 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_LSB 6
20621 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field. */
20622 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_MSB 6
20623 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field. */
20624 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_WIDTH 1
20625 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field value. */
20626 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_SET_MSK 0x00000040
20627 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field value. */
20628 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_CLR_MSK 0xffffffbf
20629 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field. */
20630 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_RESET 0x0
20631 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM field value from a register. */
20632 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_GET(value) (((value) & 0x00000040) >> 6)
20633 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field value suitable for setting the register. */
20634 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_SET(value) (((value) << 6) & 0x00000040)
20635 
20636 /*
20637  * Field : tx256t511octgbfim
20638  *
20639  * MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask
20640  *
20641  * Setting this bit masks the interrupt when the tx256to511octets_gb counter
20642  * reaches half of the maximum value or the maximum value.
20643  *
20644  * Field Enumeration Values:
20645  *
20646  * Enum | Value | Description
20647  * :---------------------------------------------------------|:------|:------------
20648  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_E_NOMSKINTR | 0x0 |
20649  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_E_MSKINTR | 0x1 |
20650  *
20651  * Field Access Macros:
20652  *
20653  */
20654 /*
20655  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM
20656  *
20657  */
20658 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_E_NOMSKINTR 0x0
20659 /*
20660  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM
20661  *
20662  */
20663 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_E_MSKINTR 0x1
20664 
20665 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field. */
20666 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_LSB 7
20667 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field. */
20668 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_MSB 7
20669 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field. */
20670 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_WIDTH 1
20671 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field value. */
20672 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_SET_MSK 0x00000080
20673 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field value. */
20674 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_CLR_MSK 0xffffff7f
20675 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field. */
20676 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_RESET 0x0
20677 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM field value from a register. */
20678 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_GET(value) (((value) & 0x00000080) >> 7)
20679 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field value suitable for setting the register. */
20680 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_SET(value) (((value) << 7) & 0x00000080)
20681 
20682 /*
20683  * Field : tx512t1023octgbfim
20684  *
20685  * MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask
20686  *
20687  * Setting this bit masks the interrupt when the tx512to1023octets_gb counter
20688  * reaches half of the maximum value or the maximum value.
20689  *
20690  * Field Enumeration Values:
20691  *
20692  * Enum | Value | Description
20693  * :----------------------------------------------------------|:------|:------------
20694  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_E_NOMSKINTR | 0x0 |
20695  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_E_MSKINTR | 0x1 |
20696  *
20697  * Field Access Macros:
20698  *
20699  */
20700 /*
20701  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM
20702  *
20703  */
20704 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_E_NOMSKINTR 0x0
20705 /*
20706  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM
20707  *
20708  */
20709 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_E_MSKINTR 0x1
20710 
20711 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field. */
20712 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_LSB 8
20713 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field. */
20714 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_MSB 8
20715 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field. */
20716 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_WIDTH 1
20717 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field value. */
20718 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_SET_MSK 0x00000100
20719 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field value. */
20720 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_CLR_MSK 0xfffffeff
20721 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field. */
20722 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_RESET 0x0
20723 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM field value from a register. */
20724 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_GET(value) (((value) & 0x00000100) >> 8)
20725 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field value suitable for setting the register. */
20726 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_SET(value) (((value) << 8) & 0x00000100)
20727 
20728 /*
20729  * Field : tx1024tmaxoctgbfim
20730  *
20731  * MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask
20732  *
20733  * Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter
20734  * reaches half of the maximum value or the maximum value.
20735  *
20736  * Field Enumeration Values:
20737  *
20738  * Enum | Value | Description
20739  * :----------------------------------------------------------|:------|:------------
20740  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_E_NOMSKINTR | 0x0 |
20741  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_E_MSKINTR | 0x1 |
20742  *
20743  * Field Access Macros:
20744  *
20745  */
20746 /*
20747  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM
20748  *
20749  */
20750 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_E_NOMSKINTR 0x0
20751 /*
20752  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM
20753  *
20754  */
20755 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_E_MSKINTR 0x1
20756 
20757 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field. */
20758 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_LSB 9
20759 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field. */
20760 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_MSB 9
20761 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field. */
20762 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_WIDTH 1
20763 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field value. */
20764 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_SET_MSK 0x00000200
20765 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field value. */
20766 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_CLR_MSK 0xfffffdff
20767 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field. */
20768 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_RESET 0x0
20769 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM field value from a register. */
20770 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_GET(value) (((value) & 0x00000200) >> 9)
20771 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field value suitable for setting the register. */
20772 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_SET(value) (((value) << 9) & 0x00000200)
20773 
20774 /*
20775  * Field : txucgbfim
20776  *
20777  * MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask
20778  *
20779  * Setting this bit masks the interrupt when the txunicastframes_gb counter reaches
20780  * half of the maximum value or the maximum value.
20781  *
20782  * Field Enumeration Values:
20783  *
20784  * Enum | Value | Description
20785  * :-------------------------------------------------|:------|:------------
20786  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_E_NOMSKINTR | 0x0 |
20787  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_E_MSKINTR | 0x1 |
20788  *
20789  * Field Access Macros:
20790  *
20791  */
20792 /*
20793  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM
20794  *
20795  */
20796 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_E_NOMSKINTR 0x0
20797 /*
20798  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM
20799  *
20800  */
20801 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_E_MSKINTR 0x1
20802 
20803 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field. */
20804 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_LSB 10
20805 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field. */
20806 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_MSB 10
20807 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field. */
20808 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_WIDTH 1
20809 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field value. */
20810 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_SET_MSK 0x00000400
20811 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field value. */
20812 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_CLR_MSK 0xfffffbff
20813 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field. */
20814 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_RESET 0x0
20815 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM field value from a register. */
20816 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_GET(value) (((value) & 0x00000400) >> 10)
20817 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field value suitable for setting the register. */
20818 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_SET(value) (((value) << 10) & 0x00000400)
20819 
20820 /*
20821  * Field : txmcgbfim
20822  *
20823  * MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask
20824  *
20825  * Setting this bit masks the interrupt when the txmulticastframes_gb counter
20826  * reaches half of the maximum value or the maximum value.
20827  *
20828  * Field Enumeration Values:
20829  *
20830  * Enum | Value | Description
20831  * :-------------------------------------------------|:------|:------------
20832  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_E_NOMSKINTR | 0x0 |
20833  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_E_MSKINTR | 0x1 |
20834  *
20835  * Field Access Macros:
20836  *
20837  */
20838 /*
20839  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM
20840  *
20841  */
20842 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_E_NOMSKINTR 0x0
20843 /*
20844  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM
20845  *
20846  */
20847 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_E_MSKINTR 0x1
20848 
20849 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field. */
20850 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_LSB 11
20851 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field. */
20852 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_MSB 11
20853 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field. */
20854 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_WIDTH 1
20855 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field value. */
20856 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_SET_MSK 0x00000800
20857 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field value. */
20858 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_CLR_MSK 0xfffff7ff
20859 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field. */
20860 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_RESET 0x0
20861 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM field value from a register. */
20862 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_GET(value) (((value) & 0x00000800) >> 11)
20863 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field value suitable for setting the register. */
20864 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_SET(value) (((value) << 11) & 0x00000800)
20865 
20866 /*
20867  * Field : txbcgbfim
20868  *
20869  * MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask
20870  *
20871  * Setting this bit masks the interrupt when the txbroadcastframes_gb counter
20872  * reaches half of the maximum value or the maximum value.
20873  *
20874  * Field Enumeration Values:
20875  *
20876  * Enum | Value | Description
20877  * :-------------------------------------------------|:------|:------------
20878  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_E_NOMSKINTR | 0x0 |
20879  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_E_MSKINTR | 0x1 |
20880  *
20881  * Field Access Macros:
20882  *
20883  */
20884 /*
20885  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM
20886  *
20887  */
20888 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_E_NOMSKINTR 0x0
20889 /*
20890  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM
20891  *
20892  */
20893 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_E_MSKINTR 0x1
20894 
20895 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field. */
20896 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_LSB 12
20897 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field. */
20898 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_MSB 12
20899 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field. */
20900 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_WIDTH 1
20901 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field value. */
20902 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_SET_MSK 0x00001000
20903 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field value. */
20904 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_CLR_MSK 0xffffefff
20905 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field. */
20906 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_RESET 0x0
20907 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM field value from a register. */
20908 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_GET(value) (((value) & 0x00001000) >> 12)
20909 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field value suitable for setting the register. */
20910 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_SET(value) (((value) << 12) & 0x00001000)
20911 
20912 /*
20913  * Field : txuflowerfim
20914  *
20915  * MMC Transmit Underflow Error Frame Counter Interrupt Mask
20916  *
20917  * Setting this bit masks the interrupt when the txunderflowerror counter reaches
20918  * half of the maximum value or the maximum value.
20919  *
20920  * Field Enumeration Values:
20921  *
20922  * Enum | Value | Description
20923  * :----------------------------------------------------|:------|:------------
20924  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_E_NOMSKINTR | 0x0 |
20925  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_E_MSKINTR | 0x1 |
20926  *
20927  * Field Access Macros:
20928  *
20929  */
20930 /*
20931  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM
20932  *
20933  */
20934 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_E_NOMSKINTR 0x0
20935 /*
20936  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM
20937  *
20938  */
20939 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_E_MSKINTR 0x1
20940 
20941 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field. */
20942 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_LSB 13
20943 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field. */
20944 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_MSB 13
20945 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field. */
20946 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_WIDTH 1
20947 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field value. */
20948 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_SET_MSK 0x00002000
20949 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field value. */
20950 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_CLR_MSK 0xffffdfff
20951 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field. */
20952 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_RESET 0x0
20953 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM field value from a register. */
20954 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_GET(value) (((value) & 0x00002000) >> 13)
20955 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field value suitable for setting the register. */
20956 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_SET(value) (((value) << 13) & 0x00002000)
20957 
20958 /*
20959  * Field : txscolgfim
20960  *
20961  * MMC Transmit Single Collision Good Frame Counter Interrupt Mask
20962  *
20963  * Setting this bit masks the interrupt when the txsinglecol_g counter reaches half
20964  * of the maximum value or the maximum value.
20965  *
20966  * Field Enumeration Values:
20967  *
20968  * Enum | Value | Description
20969  * :--------------------------------------------------|:------|:------------
20970  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_E_NOMSKINTR | 0x0 |
20971  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_E_MSKINTR | 0x1 |
20972  *
20973  * Field Access Macros:
20974  *
20975  */
20976 /*
20977  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM
20978  *
20979  */
20980 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_E_NOMSKINTR 0x0
20981 /*
20982  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM
20983  *
20984  */
20985 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_E_MSKINTR 0x1
20986 
20987 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field. */
20988 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_LSB 14
20989 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field. */
20990 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_MSB 14
20991 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field. */
20992 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_WIDTH 1
20993 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field value. */
20994 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_SET_MSK 0x00004000
20995 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field value. */
20996 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_CLR_MSK 0xffffbfff
20997 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field. */
20998 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_RESET 0x0
20999 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM field value from a register. */
21000 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_GET(value) (((value) & 0x00004000) >> 14)
21001 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field value suitable for setting the register. */
21002 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_SET(value) (((value) << 14) & 0x00004000)
21003 
21004 /*
21005  * Field : txmcolgfim
21006  *
21007  * MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask
21008  *
21009  * Setting this bit masks the interrupt when the txmulticol_g counter reaches half
21010  * of the maximum value or the maximum value.
21011  *
21012  * Field Enumeration Values:
21013  *
21014  * Enum | Value | Description
21015  * :--------------------------------------------------|:------|:------------
21016  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_E_NOMSKINTR | 0x0 |
21017  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_E_MSKINTR | 0x1 |
21018  *
21019  * Field Access Macros:
21020  *
21021  */
21022 /*
21023  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM
21024  *
21025  */
21026 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_E_NOMSKINTR 0x0
21027 /*
21028  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM
21029  *
21030  */
21031 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_E_MSKINTR 0x1
21032 
21033 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field. */
21034 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_LSB 15
21035 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field. */
21036 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_MSB 15
21037 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field. */
21038 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_WIDTH 1
21039 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field value. */
21040 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_SET_MSK 0x00008000
21041 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field value. */
21042 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_CLR_MSK 0xffff7fff
21043 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field. */
21044 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_RESET 0x0
21045 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM field value from a register. */
21046 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_GET(value) (((value) & 0x00008000) >> 15)
21047 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field value suitable for setting the register. */
21048 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_SET(value) (((value) << 15) & 0x00008000)
21049 
21050 /*
21051  * Field : txdeffim
21052  *
21053  * MMC Transmit Deferred Frame Counter Interrupt Mask
21054  *
21055  * Setting this bit masks the interrupt when the txdeferred counter reaches half of
21056  * the maximum value or the maximum value.
21057  *
21058  * Field Enumeration Values:
21059  *
21060  * Enum | Value | Description
21061  * :------------------------------------------------|:------|:------------
21062  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_E_NOMSKINTR | 0x0 |
21063  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_E_MSKINTR | 0x1 |
21064  *
21065  * Field Access Macros:
21066  *
21067  */
21068 /*
21069  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM
21070  *
21071  */
21072 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_E_NOMSKINTR 0x0
21073 /*
21074  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM
21075  *
21076  */
21077 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_E_MSKINTR 0x1
21078 
21079 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field. */
21080 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_LSB 16
21081 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field. */
21082 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_MSB 16
21083 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field. */
21084 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_WIDTH 1
21085 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field value. */
21086 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_SET_MSK 0x00010000
21087 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field value. */
21088 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_CLR_MSK 0xfffeffff
21089 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field. */
21090 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_RESET 0x0
21091 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM field value from a register. */
21092 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_GET(value) (((value) & 0x00010000) >> 16)
21093 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field value suitable for setting the register. */
21094 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_SET(value) (((value) << 16) & 0x00010000)
21095 
21096 /*
21097  * Field : txlatcolfim
21098  *
21099  * MMC Transmit Late Collision Frame Counter Interrupt Mask
21100  *
21101  * Setting this bit masks the interrupt when the txlatecol counter reaches half of
21102  * the maximum value or the maximum value.
21103  *
21104  * Field Enumeration Values:
21105  *
21106  * Enum | Value | Description
21107  * :---------------------------------------------------|:------|:------------
21108  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_E_NOMSKINTR | 0x0 |
21109  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_E_MSKINTR | 0x1 |
21110  *
21111  * Field Access Macros:
21112  *
21113  */
21114 /*
21115  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM
21116  *
21117  */
21118 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_E_NOMSKINTR 0x0
21119 /*
21120  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM
21121  *
21122  */
21123 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_E_MSKINTR 0x1
21124 
21125 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field. */
21126 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_LSB 17
21127 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field. */
21128 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_MSB 17
21129 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field. */
21130 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_WIDTH 1
21131 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field value. */
21132 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_SET_MSK 0x00020000
21133 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field value. */
21134 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_CLR_MSK 0xfffdffff
21135 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field. */
21136 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_RESET 0x0
21137 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM field value from a register. */
21138 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_GET(value) (((value) & 0x00020000) >> 17)
21139 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field value suitable for setting the register. */
21140 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_SET(value) (((value) << 17) & 0x00020000)
21141 
21142 /*
21143  * Field : txexcolfim
21144  *
21145  * MMC Transmit Excessive Collision Frame Counter Interrupt Mask
21146  *
21147  * Setting this bit masks the interrupt when the txexcesscol counter reaches half
21148  * of the maximum value or the maximum value.
21149  *
21150  * Field Enumeration Values:
21151  *
21152  * Enum | Value | Description
21153  * :--------------------------------------------------|:------|:------------
21154  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_E_NOMSKINTR | 0x0 |
21155  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_E_MSKINTR | 0x1 |
21156  *
21157  * Field Access Macros:
21158  *
21159  */
21160 /*
21161  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM
21162  *
21163  */
21164 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_E_NOMSKINTR 0x0
21165 /*
21166  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM
21167  *
21168  */
21169 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_E_MSKINTR 0x1
21170 
21171 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field. */
21172 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_LSB 18
21173 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field. */
21174 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_MSB 18
21175 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field. */
21176 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_WIDTH 1
21177 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field value. */
21178 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_SET_MSK 0x00040000
21179 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field value. */
21180 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_CLR_MSK 0xfffbffff
21181 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field. */
21182 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_RESET 0x0
21183 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM field value from a register. */
21184 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_GET(value) (((value) & 0x00040000) >> 18)
21185 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field value suitable for setting the register. */
21186 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_SET(value) (((value) << 18) & 0x00040000)
21187 
21188 /*
21189  * Field : txcarerfim
21190  *
21191  * MMC Transmit Carrier Error Frame Counter Interrupt Mask
21192  *
21193  * Setting this bit masks the interrupt when the txcarriererror counter reaches
21194  * half of the maximum value or the maximum value.
21195  *
21196  * Field Enumeration Values:
21197  *
21198  * Enum | Value | Description
21199  * :--------------------------------------------------|:------|:------------
21200  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_E_NOMSKINTR | 0x0 |
21201  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_E_MSKINTR | 0x1 |
21202  *
21203  * Field Access Macros:
21204  *
21205  */
21206 /*
21207  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM
21208  *
21209  */
21210 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_E_NOMSKINTR 0x0
21211 /*
21212  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM
21213  *
21214  */
21215 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_E_MSKINTR 0x1
21216 
21217 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field. */
21218 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_LSB 19
21219 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field. */
21220 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_MSB 19
21221 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field. */
21222 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_WIDTH 1
21223 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field value. */
21224 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_SET_MSK 0x00080000
21225 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field value. */
21226 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_CLR_MSK 0xfff7ffff
21227 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field. */
21228 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_RESET 0x0
21229 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM field value from a register. */
21230 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_GET(value) (((value) & 0x00080000) >> 19)
21231 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field value suitable for setting the register. */
21232 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_SET(value) (((value) << 19) & 0x00080000)
21233 
21234 /*
21235  * Field : txgoctim
21236  *
21237  * MMC Transmit Good Octet Counter Interrupt Mask
21238  *
21239  * Setting this bit masks the interrupt when the txoctetcount_g counter reaches
21240  * half of the maximum value or the maximum value.
21241  *
21242  * Field Enumeration Values:
21243  *
21244  * Enum | Value | Description
21245  * :------------------------------------------------|:------|:------------
21246  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_E_NOMSKINTR | 0x0 |
21247  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_E_MSKINTR | 0x1 |
21248  *
21249  * Field Access Macros:
21250  *
21251  */
21252 /*
21253  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM
21254  *
21255  */
21256 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_E_NOMSKINTR 0x0
21257 /*
21258  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM
21259  *
21260  */
21261 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_E_MSKINTR 0x1
21262 
21263 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field. */
21264 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_LSB 20
21265 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field. */
21266 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_MSB 20
21267 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field. */
21268 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_WIDTH 1
21269 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field value. */
21270 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_SET_MSK 0x00100000
21271 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field value. */
21272 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_CLR_MSK 0xffefffff
21273 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field. */
21274 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_RESET 0x0
21275 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM field value from a register. */
21276 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_GET(value) (((value) & 0x00100000) >> 20)
21277 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field value suitable for setting the register. */
21278 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_SET(value) (((value) << 20) & 0x00100000)
21279 
21280 /*
21281  * Field : txgfrmim
21282  *
21283  * MMC Transmit Good Frame Counter Interrupt Mask
21284  *
21285  * Setting this bit masks the interrupt when the txframecount_g counter reaches
21286  * half of the maximum value or the maximum value.
21287  *
21288  * Field Enumeration Values:
21289  *
21290  * Enum | Value | Description
21291  * :------------------------------------------------|:------|:------------
21292  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_E_NOMSKINTR | 0x0 |
21293  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_E_MSKINTR | 0x1 |
21294  *
21295  * Field Access Macros:
21296  *
21297  */
21298 /*
21299  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM
21300  *
21301  */
21302 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_E_NOMSKINTR 0x0
21303 /*
21304  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM
21305  *
21306  */
21307 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_E_MSKINTR 0x1
21308 
21309 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field. */
21310 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_LSB 21
21311 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field. */
21312 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_MSB 21
21313 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field. */
21314 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_WIDTH 1
21315 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field value. */
21316 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_SET_MSK 0x00200000
21317 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field value. */
21318 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_CLR_MSK 0xffdfffff
21319 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field. */
21320 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_RESET 0x0
21321 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM field value from a register. */
21322 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_GET(value) (((value) & 0x00200000) >> 21)
21323 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field value suitable for setting the register. */
21324 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_SET(value) (((value) << 21) & 0x00200000)
21325 
21326 /*
21327  * Field : txexdeffim
21328  *
21329  * MMC Transmit Excessive Deferral Frame Counter Interrupt Mask
21330  *
21331  * Setting this bit masks the interrupt when the txexcessdef counter reaches half
21332  * of the maximum value or the maximum value.
21333  *
21334  * Field Enumeration Values:
21335  *
21336  * Enum | Value | Description
21337  * :--------------------------------------------------|:------|:------------
21338  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_E_NOMSKINTR | 0x0 |
21339  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_E_MSKINTR | 0x1 |
21340  *
21341  * Field Access Macros:
21342  *
21343  */
21344 /*
21345  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM
21346  *
21347  */
21348 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_E_NOMSKINTR 0x0
21349 /*
21350  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM
21351  *
21352  */
21353 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_E_MSKINTR 0x1
21354 
21355 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field. */
21356 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_LSB 22
21357 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field. */
21358 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_MSB 22
21359 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field. */
21360 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_WIDTH 1
21361 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field value. */
21362 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_SET_MSK 0x00400000
21363 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field value. */
21364 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_CLR_MSK 0xffbfffff
21365 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field. */
21366 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_RESET 0x0
21367 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM field value from a register. */
21368 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_GET(value) (((value) & 0x00400000) >> 22)
21369 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field value suitable for setting the register. */
21370 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_SET(value) (((value) << 22) & 0x00400000)
21371 
21372 /*
21373  * Field : txpausfim
21374  *
21375  * MMC Transmit Pause Frame Counter Interrupt Mask
21376  *
21377  * Setting this bit masks the interrupt when the txpauseframes counter reaches half
21378  * of the maximum value or the maximum value.
21379  *
21380  * Field Enumeration Values:
21381  *
21382  * Enum | Value | Description
21383  * :-------------------------------------------------|:------|:------------
21384  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_E_NOMSKINTR | 0x0 |
21385  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_E_MSKINTR | 0x1 |
21386  *
21387  * Field Access Macros:
21388  *
21389  */
21390 /*
21391  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM
21392  *
21393  */
21394 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_E_NOMSKINTR 0x0
21395 /*
21396  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM
21397  *
21398  */
21399 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_E_MSKINTR 0x1
21400 
21401 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field. */
21402 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_LSB 23
21403 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field. */
21404 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_MSB 23
21405 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field. */
21406 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_WIDTH 1
21407 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field value. */
21408 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_SET_MSK 0x00800000
21409 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field value. */
21410 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_CLR_MSK 0xff7fffff
21411 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field. */
21412 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_RESET 0x0
21413 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM field value from a register. */
21414 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_GET(value) (((value) & 0x00800000) >> 23)
21415 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field value suitable for setting the register. */
21416 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_SET(value) (((value) << 23) & 0x00800000)
21417 
21418 /*
21419  * Field : txvlangfim
21420  *
21421  * MMC Transmit VLAN Good Frame Counter Interrupt Mask
21422  *
21423  * Setting this bit masks the interrupt when the txvlanframes_g counter reaches
21424  * half of the maximum value or the maximum value.
21425  *
21426  * Field Enumeration Values:
21427  *
21428  * Enum | Value | Description
21429  * :--------------------------------------------------|:------|:------------
21430  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_E_NOMSKINTR | 0x0 |
21431  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_E_MSKINTR | 0x1 |
21432  *
21433  * Field Access Macros:
21434  *
21435  */
21436 /*
21437  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM
21438  *
21439  */
21440 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_E_NOMSKINTR 0x0
21441 /*
21442  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM
21443  *
21444  */
21445 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_E_MSKINTR 0x1
21446 
21447 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field. */
21448 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_LSB 24
21449 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field. */
21450 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_MSB 24
21451 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field. */
21452 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_WIDTH 1
21453 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field value. */
21454 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_SET_MSK 0x01000000
21455 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field value. */
21456 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_CLR_MSK 0xfeffffff
21457 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field. */
21458 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_RESET 0x0
21459 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM field value from a register. */
21460 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_GET(value) (((value) & 0x01000000) >> 24)
21461 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field value suitable for setting the register. */
21462 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_SET(value) (((value) << 24) & 0x01000000)
21463 
21464 /*
21465  * Field : txosizegfim
21466  *
21467  * MMC Transmit Oversize Good Frame Counter Interrupt Mask
21468  *
21469  * Setting this bit masks the interrupt when the txoversize_g counter reaches half
21470  * of the maximum value or the maximum value.
21471  *
21472  * Field Enumeration Values:
21473  *
21474  * Enum | Value | Description
21475  * :---------------------------------------------------|:------|:------------
21476  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_E_NOMSKINTR | 0x0 |
21477  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_E_MSKINTR | 0x1 |
21478  *
21479  * Field Access Macros:
21480  *
21481  */
21482 /*
21483  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM
21484  *
21485  */
21486 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_E_NOMSKINTR 0x0
21487 /*
21488  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM
21489  *
21490  */
21491 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_E_MSKINTR 0x1
21492 
21493 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field. */
21494 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_LSB 25
21495 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field. */
21496 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_MSB 25
21497 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field. */
21498 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_WIDTH 1
21499 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field value. */
21500 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_SET_MSK 0x02000000
21501 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field value. */
21502 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_CLR_MSK 0xfdffffff
21503 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field. */
21504 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_RESET 0x0
21505 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM field value from a register. */
21506 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_GET(value) (((value) & 0x02000000) >> 25)
21507 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field value suitable for setting the register. */
21508 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_SET(value) (((value) << 25) & 0x02000000)
21509 
21510 /*
21511  * Field : reserved_31_26
21512  *
21513  * Reserved
21514  *
21515  * Field Access Macros:
21516  *
21517  */
21518 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_RSVD_31_26 register field. */
21519 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_RSVD_31_26_LSB 26
21520 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_RSVD_31_26 register field. */
21521 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_RSVD_31_26_MSB 31
21522 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_RSVD_31_26 register field. */
21523 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_RSVD_31_26_WIDTH 6
21524 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_RSVD_31_26 register field value. */
21525 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_RSVD_31_26_SET_MSK 0xfc000000
21526 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_RSVD_31_26 register field value. */
21527 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_RSVD_31_26_CLR_MSK 0x03ffffff
21528 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_RSVD_31_26 register field. */
21529 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_RSVD_31_26_RESET 0x0
21530 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_RSVD_31_26 field value from a register. */
21531 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_RSVD_31_26_GET(value) (((value) & 0xfc000000) >> 26)
21532 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_RSVD_31_26 register field value suitable for setting the register. */
21533 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_RSVD_31_26_SET(value) (((value) << 26) & 0xfc000000)
21534 
21535 #ifndef __ASSEMBLY__
21536 /*
21537  * WARNING: The C register and register group struct declarations are provided for
21538  * convenience and illustrative purposes. They should, however, be used with
21539  * caution as the C language standard provides no guarantees about the alignment or
21540  * atomicity of device memory accesses. The recommended practice for writing
21541  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21542  * alt_write_word() functions.
21543  *
21544  * The struct declaration for register ALT_EMAC_GMAC_MMC_TX_INT_MSK.
21545  */
21546 struct ALT_EMAC_GMAC_MMC_TX_INT_MSK_s
21547 {
21548  uint32_t txgboctim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM */
21549  uint32_t txgbfrmim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM */
21550  uint32_t txbcgfim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM */
21551  uint32_t txmcgfim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM */
21552  uint32_t tx64octgbfim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM */
21553  uint32_t tx65t127octgbfim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM */
21554  uint32_t tx128t255octgbfim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM */
21555  uint32_t tx256t511octgbfim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM */
21556  uint32_t tx512t1023octgbfim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM */
21557  uint32_t tx1024tmaxoctgbfim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM */
21558  uint32_t txucgbfim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM */
21559  uint32_t txmcgbfim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM */
21560  uint32_t txbcgbfim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM */
21561  uint32_t txuflowerfim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM */
21562  uint32_t txscolgfim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM */
21563  uint32_t txmcolgfim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM */
21564  uint32_t txdeffim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM */
21565  uint32_t txlatcolfim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM */
21566  uint32_t txexcolfim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM */
21567  uint32_t txcarerfim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM */
21568  uint32_t txgoctim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM */
21569  uint32_t txgfrmim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM */
21570  uint32_t txexdeffim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM */
21571  uint32_t txpausfim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM */
21572  uint32_t txvlangfim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM */
21573  uint32_t txosizegfim : 1; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM */
21574  const uint32_t reserved_31_26 : 6; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK_RSVD_31_26 */
21575 };
21576 
21577 /* The typedef declaration for register ALT_EMAC_GMAC_MMC_TX_INT_MSK. */
21578 typedef volatile struct ALT_EMAC_GMAC_MMC_TX_INT_MSK_s ALT_EMAC_GMAC_MMC_TX_INT_MSK_t;
21579 #endif /* __ASSEMBLY__ */
21580 
21581 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK register. */
21582 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_RESET 0x00000000
21583 /* The byte offset of the ALT_EMAC_GMAC_MMC_TX_INT_MSK register from the beginning of the component. */
21584 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OFST 0x110
21585 /* The address of the ALT_EMAC_GMAC_MMC_TX_INT_MSK register. */
21586 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_TX_INT_MSK_OFST))
21587 
21588 /*
21589  * Register : gmacgrp_txoctetcount_gb
21590  *
21591  * <b> Register 69 (Transmit Octet Count for Good and Bad Frames) </b>
21592  *
21593  * This register maintains the number of bytes transmitted in good and bad frames
21594  * exclusive of preamble and retried bytes.
21595  *
21596  * Register Layout
21597  *
21598  * Bits | Access | Reset | Description
21599  * :-------|:-------|:------|:----------------------------------
21600  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT
21601  *
21602  */
21603 /*
21604  * Field : cnt
21605  *
21606  * This field indicates the number of bytes transmitted in good and bad frames
21607  * exclusive of preamble and retried bytes.
21608  *
21609  * Field Access Macros:
21610  *
21611  */
21612 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field. */
21613 #define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_LSB 0
21614 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field. */
21615 #define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_MSB 31
21616 /* The width in bits of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field. */
21617 #define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_WIDTH 32
21618 /* The mask used to set the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field value. */
21619 #define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_SET_MSK 0xffffffff
21620 /* The mask used to clear the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field value. */
21621 #define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_CLR_MSK 0x00000000
21622 /* The reset value of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field. */
21623 #define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_RESET 0x0
21624 /* Extracts the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT field value from a register. */
21625 #define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21626 /* Produces a ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field value suitable for setting the register. */
21627 #define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
21628 
21629 #ifndef __ASSEMBLY__
21630 /*
21631  * WARNING: The C register and register group struct declarations are provided for
21632  * convenience and illustrative purposes. They should, however, be used with
21633  * caution as the C language standard provides no guarantees about the alignment or
21634  * atomicity of device memory accesses. The recommended practice for writing
21635  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21636  * alt_write_word() functions.
21637  *
21638  * The struct declaration for register ALT_EMAC_GMAC_TXOCTETCOUNT_GB.
21639  */
21640 struct ALT_EMAC_GMAC_TXOCTETCOUNT_GB_s
21641 {
21642  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT */
21643 };
21644 
21645 /* The typedef declaration for register ALT_EMAC_GMAC_TXOCTETCOUNT_GB. */
21646 typedef volatile struct ALT_EMAC_GMAC_TXOCTETCOUNT_GB_s ALT_EMAC_GMAC_TXOCTETCOUNT_GB_t;
21647 #endif /* __ASSEMBLY__ */
21648 
21649 /* The reset value of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB register. */
21650 #define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_RESET 0x00000000
21651 /* The byte offset of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB register from the beginning of the component. */
21652 #define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_OFST 0x114
21653 /* The address of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB register. */
21654 #define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXOCTETCOUNT_GB_OFST))
21655 
21656 /*
21657  * Register : gmacgrp_txframecount_gb
21658  *
21659  * <b> Register 70 (Transmit Frame Count for Good and Bad Frames) </b>
21660  *
21661  * This register maintains the number of good and bad frames transmitted, exclusive
21662  * of retried frames.
21663  *
21664  * Register Layout
21665  *
21666  * Bits | Access | Reset | Description
21667  * :-------|:-------|:------|:--------------------------------
21668  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT
21669  *
21670  */
21671 /*
21672  * Field : cnt
21673  *
21674  * This field indicates the number of good and bad frames transmitted, exclusive of
21675  * retried frames
21676  *
21677  * Field Access Macros:
21678  *
21679  */
21680 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field. */
21681 #define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_LSB 0
21682 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field. */
21683 #define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_MSB 31
21684 /* The width in bits of the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field. */
21685 #define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_WIDTH 32
21686 /* The mask used to set the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field value. */
21687 #define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_SET_MSK 0xffffffff
21688 /* The mask used to clear the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field value. */
21689 #define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_CLR_MSK 0x00000000
21690 /* The reset value of the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field. */
21691 #define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_RESET 0x0
21692 /* Extracts the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT field value from a register. */
21693 #define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21694 /* Produces a ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field value suitable for setting the register. */
21695 #define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
21696 
21697 #ifndef __ASSEMBLY__
21698 /*
21699  * WARNING: The C register and register group struct declarations are provided for
21700  * convenience and illustrative purposes. They should, however, be used with
21701  * caution as the C language standard provides no guarantees about the alignment or
21702  * atomicity of device memory accesses. The recommended practice for writing
21703  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21704  * alt_write_word() functions.
21705  *
21706  * The struct declaration for register ALT_EMAC_GMAC_TXFRMCOUNT_GB.
21707  */
21708 struct ALT_EMAC_GMAC_TXFRMCOUNT_GB_s
21709 {
21710  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT */
21711 };
21712 
21713 /* The typedef declaration for register ALT_EMAC_GMAC_TXFRMCOUNT_GB. */
21714 typedef volatile struct ALT_EMAC_GMAC_TXFRMCOUNT_GB_s ALT_EMAC_GMAC_TXFRMCOUNT_GB_t;
21715 #endif /* __ASSEMBLY__ */
21716 
21717 /* The reset value of the ALT_EMAC_GMAC_TXFRMCOUNT_GB register. */
21718 #define ALT_EMAC_GMAC_TXFRMCOUNT_GB_RESET 0x00000000
21719 /* The byte offset of the ALT_EMAC_GMAC_TXFRMCOUNT_GB register from the beginning of the component. */
21720 #define ALT_EMAC_GMAC_TXFRMCOUNT_GB_OFST 0x118
21721 /* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_GB register. */
21722 #define ALT_EMAC_GMAC_TXFRMCOUNT_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXFRMCOUNT_GB_OFST))
21723 
21724 /*
21725  * Register : gmacgrp_txbroadcastframes_g
21726  *
21727  * <b> Register 71 (Transmit Frame Count for Good Broadcast Frames) </b>
21728  *
21729  * This register maintains the number of transmitted good broadcast frames.
21730  *
21731  * Register Layout
21732  *
21733  * Bits | Access | Reset | Description
21734  * :-------|:-------|:------|:--------------------------------
21735  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT
21736  *
21737  */
21738 /*
21739  * Field : cnt
21740  *
21741  * This field indicates the number of transmitted good broadcast frames.
21742  *
21743  * Field Access Macros:
21744  *
21745  */
21746 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field. */
21747 #define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_LSB 0
21748 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field. */
21749 #define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_MSB 31
21750 /* The width in bits of the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field. */
21751 #define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_WIDTH 32
21752 /* The mask used to set the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field value. */
21753 #define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_SET_MSK 0xffffffff
21754 /* The mask used to clear the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field value. */
21755 #define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_CLR_MSK 0x00000000
21756 /* The reset value of the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field. */
21757 #define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_RESET 0x0
21758 /* Extracts the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT field value from a register. */
21759 #define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21760 /* Produces a ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field value suitable for setting the register. */
21761 #define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
21762 
21763 #ifndef __ASSEMBLY__
21764 /*
21765  * WARNING: The C register and register group struct declarations are provided for
21766  * convenience and illustrative purposes. They should, however, be used with
21767  * caution as the C language standard provides no guarantees about the alignment or
21768  * atomicity of device memory accesses. The recommended practice for writing
21769  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21770  * alt_write_word() functions.
21771  *
21772  * The struct declaration for register ALT_EMAC_GMAC_TXBCASTFRMS_G.
21773  */
21774 struct ALT_EMAC_GMAC_TXBCASTFRMS_G_s
21775 {
21776  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT */
21777 };
21778 
21779 /* The typedef declaration for register ALT_EMAC_GMAC_TXBCASTFRMS_G. */
21780 typedef volatile struct ALT_EMAC_GMAC_TXBCASTFRMS_G_s ALT_EMAC_GMAC_TXBCASTFRMS_G_t;
21781 #endif /* __ASSEMBLY__ */
21782 
21783 /* The reset value of the ALT_EMAC_GMAC_TXBCASTFRMS_G register. */
21784 #define ALT_EMAC_GMAC_TXBCASTFRMS_G_RESET 0x00000000
21785 /* The byte offset of the ALT_EMAC_GMAC_TXBCASTFRMS_G register from the beginning of the component. */
21786 #define ALT_EMAC_GMAC_TXBCASTFRMS_G_OFST 0x11c
21787 /* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_G register. */
21788 #define ALT_EMAC_GMAC_TXBCASTFRMS_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXBCASTFRMS_G_OFST))
21789 
21790 /*
21791  * Register : gmacgrp_txmulticastframes_g
21792  *
21793  * <b> Register 72 (Transmit Frame Count for Good Multicast Frames) </b>
21794  *
21795  * This register maintains the number of transmitted good multicast frames.
21796  *
21797  * Register Layout
21798  *
21799  * Bits | Access | Reset | Description
21800  * :-------|:-------|:------|:--------------------------------
21801  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT
21802  *
21803  */
21804 /*
21805  * Field : cnt
21806  *
21807  * This field indicates the number of transmitted good multicast frames.
21808  *
21809  * Field Access Macros:
21810  *
21811  */
21812 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field. */
21813 #define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_LSB 0
21814 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field. */
21815 #define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_MSB 31
21816 /* The width in bits of the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field. */
21817 #define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_WIDTH 32
21818 /* The mask used to set the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field value. */
21819 #define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_SET_MSK 0xffffffff
21820 /* The mask used to clear the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field value. */
21821 #define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_CLR_MSK 0x00000000
21822 /* The reset value of the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field. */
21823 #define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_RESET 0x0
21824 /* Extracts the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT field value from a register. */
21825 #define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21826 /* Produces a ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field value suitable for setting the register. */
21827 #define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
21828 
21829 #ifndef __ASSEMBLY__
21830 /*
21831  * WARNING: The C register and register group struct declarations are provided for
21832  * convenience and illustrative purposes. They should, however, be used with
21833  * caution as the C language standard provides no guarantees about the alignment or
21834  * atomicity of device memory accesses. The recommended practice for writing
21835  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21836  * alt_write_word() functions.
21837  *
21838  * The struct declaration for register ALT_EMAC_GMAC_TXMCASTFRMS_G.
21839  */
21840 struct ALT_EMAC_GMAC_TXMCASTFRMS_G_s
21841 {
21842  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT */
21843 };
21844 
21845 /* The typedef declaration for register ALT_EMAC_GMAC_TXMCASTFRMS_G. */
21846 typedef volatile struct ALT_EMAC_GMAC_TXMCASTFRMS_G_s ALT_EMAC_GMAC_TXMCASTFRMS_G_t;
21847 #endif /* __ASSEMBLY__ */
21848 
21849 /* The reset value of the ALT_EMAC_GMAC_TXMCASTFRMS_G register. */
21850 #define ALT_EMAC_GMAC_TXMCASTFRMS_G_RESET 0x00000000
21851 /* The byte offset of the ALT_EMAC_GMAC_TXMCASTFRMS_G register from the beginning of the component. */
21852 #define ALT_EMAC_GMAC_TXMCASTFRMS_G_OFST 0x120
21853 /* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_G register. */
21854 #define ALT_EMAC_GMAC_TXMCASTFRMS_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXMCASTFRMS_G_OFST))
21855 
21856 /*
21857  * Register : gmacgrp_tx64octets_gb
21858  *
21859  * <b> Register 73 (Transmit Octet Count for Good and Bad 64 Byte Frames) </b>
21860  *
21861  * This register maintains the number of transmitted good and bad frames with
21862  * length of 64 bytes, exclusive of preamble and retried frames.
21863  *
21864  * Register Layout
21865  *
21866  * Bits | Access | Reset | Description
21867  * :-------|:-------|:------|:--------------------------------
21868  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TX64OCTETS_GB_CNT
21869  *
21870  */
21871 /*
21872  * Field : cnt
21873  *
21874  * This field indicates the number of transmitted good and bad frames with length
21875  * of 64 bytes, exclusive of preamble and retried frames.
21876  *
21877  * Field Access Macros:
21878  *
21879  */
21880 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field. */
21881 #define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_LSB 0
21882 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field. */
21883 #define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_MSB 31
21884 /* The width in bits of the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field. */
21885 #define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_WIDTH 32
21886 /* The mask used to set the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field value. */
21887 #define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_SET_MSK 0xffffffff
21888 /* The mask used to clear the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field value. */
21889 #define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_CLR_MSK 0x00000000
21890 /* The reset value of the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field. */
21891 #define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_RESET 0x0
21892 /* Extracts the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT field value from a register. */
21893 #define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21894 /* Produces a ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field value suitable for setting the register. */
21895 #define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
21896 
21897 #ifndef __ASSEMBLY__
21898 /*
21899  * WARNING: The C register and register group struct declarations are provided for
21900  * convenience and illustrative purposes. They should, however, be used with
21901  * caution as the C language standard provides no guarantees about the alignment or
21902  * atomicity of device memory accesses. The recommended practice for writing
21903  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21904  * alt_write_word() functions.
21905  *
21906  * The struct declaration for register ALT_EMAC_GMAC_TX64OCTETS_GB.
21907  */
21908 struct ALT_EMAC_GMAC_TX64OCTETS_GB_s
21909 {
21910  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TX64OCTETS_GB_CNT */
21911 };
21912 
21913 /* The typedef declaration for register ALT_EMAC_GMAC_TX64OCTETS_GB. */
21914 typedef volatile struct ALT_EMAC_GMAC_TX64OCTETS_GB_s ALT_EMAC_GMAC_TX64OCTETS_GB_t;
21915 #endif /* __ASSEMBLY__ */
21916 
21917 /* The reset value of the ALT_EMAC_GMAC_TX64OCTETS_GB register. */
21918 #define ALT_EMAC_GMAC_TX64OCTETS_GB_RESET 0x00000000
21919 /* The byte offset of the ALT_EMAC_GMAC_TX64OCTETS_GB register from the beginning of the component. */
21920 #define ALT_EMAC_GMAC_TX64OCTETS_GB_OFST 0x124
21921 /* The address of the ALT_EMAC_GMAC_TX64OCTETS_GB register. */
21922 #define ALT_EMAC_GMAC_TX64OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX64OCTETS_GB_OFST))
21923 
21924 /*
21925  * Register : gmacgrp_tx65to127octets_gb
21926  *
21927  * <b> Register 74 (Transmit Octet Count for Good and Bad 65 to 127 Bytes Frames)
21928  * </b>
21929  *
21930  * This register maintains the number of transmitted good and bad frames with
21931  * length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried
21932  * frames.
21933  *
21934  * Register Layout
21935  *
21936  * Bits | Access | Reset | Description
21937  * :-------|:-------|:------|:-------------------------------------
21938  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT
21939  *
21940  */
21941 /*
21942  * Field : cnt
21943  *
21944  * This field indicates the number of transmitted good and bad frames with length
21945  * between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames.
21946  *
21947  * Field Access Macros:
21948  *
21949  */
21950 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field. */
21951 #define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_LSB 0
21952 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field. */
21953 #define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_MSB 31
21954 /* The width in bits of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field. */
21955 #define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_WIDTH 32
21956 /* The mask used to set the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field value. */
21957 #define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_SET_MSK 0xffffffff
21958 /* The mask used to clear the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field value. */
21959 #define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_CLR_MSK 0x00000000
21960 /* The reset value of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field. */
21961 #define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_RESET 0x0
21962 /* Extracts the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT field value from a register. */
21963 #define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21964 /* Produces a ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field value suitable for setting the register. */
21965 #define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
21966 
21967 #ifndef __ASSEMBLY__
21968 /*
21969  * WARNING: The C register and register group struct declarations are provided for
21970  * convenience and illustrative purposes. They should, however, be used with
21971  * caution as the C language standard provides no guarantees about the alignment or
21972  * atomicity of device memory accesses. The recommended practice for writing
21973  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21974  * alt_write_word() functions.
21975  *
21976  * The struct declaration for register ALT_EMAC_GMAC_TX65TO127OCTETS_GB.
21977  */
21978 struct ALT_EMAC_GMAC_TX65TO127OCTETS_GB_s
21979 {
21980  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT */
21981 };
21982 
21983 /* The typedef declaration for register ALT_EMAC_GMAC_TX65TO127OCTETS_GB. */
21984 typedef volatile struct ALT_EMAC_GMAC_TX65TO127OCTETS_GB_s ALT_EMAC_GMAC_TX65TO127OCTETS_GB_t;
21985 #endif /* __ASSEMBLY__ */
21986 
21987 /* The reset value of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB register. */
21988 #define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_RESET 0x00000000
21989 /* The byte offset of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB register from the beginning of the component. */
21990 #define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_OFST 0x128
21991 /* The address of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB register. */
21992 #define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX65TO127OCTETS_GB_OFST))
21993 
21994 /*
21995  * Register : gmacgrp_tx128to255octets_gb
21996  *
21997  * <b> Register 75 (Transmit Octet Count for Good and Bad 128 to 255 Bytes Frames)
21998  * </b>
21999  *
22000  * This register maintains the number of transmitted good and bad frames with
22001  * length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried
22002  * frames.
22003  *
22004  * Register Layout
22005  *
22006  * Bits | Access | Reset | Description
22007  * :-------|:-------|:------|:--------------------------------------
22008  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT
22009  *
22010  */
22011 /*
22012  * Field : cnt
22013  *
22014  * This field indicates the number of transmitted good and bad frames with length
22015  * between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames.
22016  *
22017  * Field Access Macros:
22018  *
22019  */
22020 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field. */
22021 #define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_LSB 0
22022 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field. */
22023 #define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_MSB 31
22024 /* The width in bits of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field. */
22025 #define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_WIDTH 32
22026 /* The mask used to set the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field value. */
22027 #define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_SET_MSK 0xffffffff
22028 /* The mask used to clear the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field value. */
22029 #define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_CLR_MSK 0x00000000
22030 /* The reset value of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field. */
22031 #define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_RESET 0x0
22032 /* Extracts the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT field value from a register. */
22033 #define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22034 /* Produces a ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field value suitable for setting the register. */
22035 #define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
22036 
22037 #ifndef __ASSEMBLY__
22038 /*
22039  * WARNING: The C register and register group struct declarations are provided for
22040  * convenience and illustrative purposes. They should, however, be used with
22041  * caution as the C language standard provides no guarantees about the alignment or
22042  * atomicity of device memory accesses. The recommended practice for writing
22043  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22044  * alt_write_word() functions.
22045  *
22046  * The struct declaration for register ALT_EMAC_GMAC_TX128TO255OCTETS_GB.
22047  */
22048 struct ALT_EMAC_GMAC_TX128TO255OCTETS_GB_s
22049 {
22050  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT */
22051 };
22052 
22053 /* The typedef declaration for register ALT_EMAC_GMAC_TX128TO255OCTETS_GB. */
22054 typedef volatile struct ALT_EMAC_GMAC_TX128TO255OCTETS_GB_s ALT_EMAC_GMAC_TX128TO255OCTETS_GB_t;
22055 #endif /* __ASSEMBLY__ */
22056 
22057 /* The reset value of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB register. */
22058 #define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_RESET 0x00000000
22059 /* The byte offset of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB register from the beginning of the component. */
22060 #define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_OFST 0x12c
22061 /* The address of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB register. */
22062 #define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX128TO255OCTETS_GB_OFST))
22063 
22064 /*
22065  * Register : gmacgrp_tx256to511octets_gb
22066  *
22067  * <b> Register 76 (Transmit Octet Count for Good and Bad 256 to 511 Bytes Frames)
22068  * </b>
22069  *
22070  * This register maintains the number of transmitted good and bad frames with
22071  * length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried
22072  * frames.
22073  *
22074  * Register Layout
22075  *
22076  * Bits | Access | Reset | Description
22077  * :-------|:-------|:------|:--------------------------------------
22078  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT
22079  *
22080  */
22081 /*
22082  * Field : cnt
22083  *
22084  * This field indicates the number of transmitted good and bad frames with length
22085  * between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames.
22086  *
22087  * Field Access Macros:
22088  *
22089  */
22090 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field. */
22091 #define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_LSB 0
22092 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field. */
22093 #define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_MSB 31
22094 /* The width in bits of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field. */
22095 #define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_WIDTH 32
22096 /* The mask used to set the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field value. */
22097 #define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_SET_MSK 0xffffffff
22098 /* The mask used to clear the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field value. */
22099 #define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_CLR_MSK 0x00000000
22100 /* The reset value of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field. */
22101 #define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_RESET 0x0
22102 /* Extracts the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT field value from a register. */
22103 #define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22104 /* Produces a ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field value suitable for setting the register. */
22105 #define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
22106 
22107 #ifndef __ASSEMBLY__
22108 /*
22109  * WARNING: The C register and register group struct declarations are provided for
22110  * convenience and illustrative purposes. They should, however, be used with
22111  * caution as the C language standard provides no guarantees about the alignment or
22112  * atomicity of device memory accesses. The recommended practice for writing
22113  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22114  * alt_write_word() functions.
22115  *
22116  * The struct declaration for register ALT_EMAC_GMAC_TX256TO511OCTETS_GB.
22117  */
22118 struct ALT_EMAC_GMAC_TX256TO511OCTETS_GB_s
22119 {
22120  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT */
22121 };
22122 
22123 /* The typedef declaration for register ALT_EMAC_GMAC_TX256TO511OCTETS_GB. */
22124 typedef volatile struct ALT_EMAC_GMAC_TX256TO511OCTETS_GB_s ALT_EMAC_GMAC_TX256TO511OCTETS_GB_t;
22125 #endif /* __ASSEMBLY__ */
22126 
22127 /* The reset value of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB register. */
22128 #define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_RESET 0x00000000
22129 /* The byte offset of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB register from the beginning of the component. */
22130 #define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_OFST 0x130
22131 /* The address of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB register. */
22132 #define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX256TO511OCTETS_GB_OFST))
22133 
22134 /*
22135  * Register : gmacgrp_tx512to1023octets_gb
22136  *
22137  * <b> Register 77 (Transmit Octet Count for Good and Bad 512 to 1023 Bytes Frames)
22138  * </b>
22139  *
22140  * This register maintains the number of transmitted good and bad frames with
22141  * length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and
22142  * retried frames.
22143  *
22144  * Register Layout
22145  *
22146  * Bits | Access | Reset | Description
22147  * :-------|:-------|:------|:---------------------------------------
22148  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT
22149  *
22150  */
22151 /*
22152  * Field : cnt
22153  *
22154  * This field indicates the number of transmitted good and bad frames with length
22155  * between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried
22156  * frames.
22157  *
22158  * Field Access Macros:
22159  *
22160  */
22161 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field. */
22162 #define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_LSB 0
22163 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field. */
22164 #define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_MSB 31
22165 /* The width in bits of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field. */
22166 #define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_WIDTH 32
22167 /* The mask used to set the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field value. */
22168 #define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_SET_MSK 0xffffffff
22169 /* The mask used to clear the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field value. */
22170 #define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_CLR_MSK 0x00000000
22171 /* The reset value of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field. */
22172 #define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_RESET 0x0
22173 /* Extracts the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT field value from a register. */
22174 #define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22175 /* Produces a ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field value suitable for setting the register. */
22176 #define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
22177 
22178 #ifndef __ASSEMBLY__
22179 /*
22180  * WARNING: The C register and register group struct declarations are provided for
22181  * convenience and illustrative purposes. They should, however, be used with
22182  * caution as the C language standard provides no guarantees about the alignment or
22183  * atomicity of device memory accesses. The recommended practice for writing
22184  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22185  * alt_write_word() functions.
22186  *
22187  * The struct declaration for register ALT_EMAC_GMAC_TX512TO1023OCTETS_GB.
22188  */
22189 struct ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_s
22190 {
22191  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT */
22192 };
22193 
22194 /* The typedef declaration for register ALT_EMAC_GMAC_TX512TO1023OCTETS_GB. */
22195 typedef volatile struct ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_s ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_t;
22196 #endif /* __ASSEMBLY__ */
22197 
22198 /* The reset value of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB register. */
22199 #define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_RESET 0x00000000
22200 /* The byte offset of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB register from the beginning of the component. */
22201 #define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_OFST 0x134
22202 /* The address of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB register. */
22203 #define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_OFST))
22204 
22205 /*
22206  * Register : gmacgrp_tx1024tomaxoctets_gb
22207  *
22208  * <b> Register 78 (Transmit Octet Count for Good and Bad 1024 to Maxsize Bytes
22209  * Frames) </b>
22210  *
22211  * This register maintains the number of transmitted good and bad frames with
22212  * length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and
22213  * retried frames.
22214  *
22215  * Register Layout
22216  *
22217  * Bits | Access | Reset | Description
22218  * :-------|:-------|:------|:---------------------------------------
22219  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT
22220  *
22221  */
22222 /*
22223  * Field : cnt
22224  *
22225  * This field indicates the number of good and bad frames transmitted with length
22226  * between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried
22227  * frames.
22228  *
22229  * Field Access Macros:
22230  *
22231  */
22232 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field. */
22233 #define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_LSB 0
22234 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field. */
22235 #define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_MSB 31
22236 /* The width in bits of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field. */
22237 #define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_WIDTH 32
22238 /* The mask used to set the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field value. */
22239 #define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_SET_MSK 0xffffffff
22240 /* The mask used to clear the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field value. */
22241 #define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_CLR_MSK 0x00000000
22242 /* The reset value of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field. */
22243 #define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_RESET 0x0
22244 /* Extracts the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT field value from a register. */
22245 #define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22246 /* Produces a ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field value suitable for setting the register. */
22247 #define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
22248 
22249 #ifndef __ASSEMBLY__
22250 /*
22251  * WARNING: The C register and register group struct declarations are provided for
22252  * convenience and illustrative purposes. They should, however, be used with
22253  * caution as the C language standard provides no guarantees about the alignment or
22254  * atomicity of device memory accesses. The recommended practice for writing
22255  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22256  * alt_write_word() functions.
22257  *
22258  * The struct declaration for register ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB.
22259  */
22260 struct ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_s
22261 {
22262  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT */
22263 };
22264 
22265 /* The typedef declaration for register ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB. */
22266 typedef volatile struct ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_s ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_t;
22267 #endif /* __ASSEMBLY__ */
22268 
22269 /* The reset value of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB register. */
22270 #define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_RESET 0x00000000
22271 /* The byte offset of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB register from the beginning of the component. */
22272 #define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_OFST 0x138
22273 /* The address of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB register. */
22274 #define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_OFST))
22275 
22276 /*
22277  * Register : gmacgrp_txunicastframes_gb
22278  *
22279  * <b> Register 79 (Transmit Frame Count for Good and Bad Unicast Frames) </b>
22280  *
22281  * This register maintains the number of transmitted good and bad unicast frames.
22282  *
22283  * Register Layout
22284  *
22285  * Bits | Access | Reset | Description
22286  * :-------|:-------|:------|:-----------------------------------
22287  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT
22288  *
22289  */
22290 /*
22291  * Field : cnt
22292  *
22293  * This field indicates the number of transmitted good and bad unicast frames.
22294  *
22295  * Field Access Macros:
22296  *
22297  */
22298 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field. */
22299 #define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_LSB 0
22300 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field. */
22301 #define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_MSB 31
22302 /* The width in bits of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field. */
22303 #define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_WIDTH 32
22304 /* The mask used to set the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field value. */
22305 #define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_SET_MSK 0xffffffff
22306 /* The mask used to clear the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field value. */
22307 #define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_CLR_MSK 0x00000000
22308 /* The reset value of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field. */
22309 #define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_RESET 0x0
22310 /* Extracts the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT field value from a register. */
22311 #define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22312 /* Produces a ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field value suitable for setting the register. */
22313 #define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
22314 
22315 #ifndef __ASSEMBLY__
22316 /*
22317  * WARNING: The C register and register group struct declarations are provided for
22318  * convenience and illustrative purposes. They should, however, be used with
22319  * caution as the C language standard provides no guarantees about the alignment or
22320  * atomicity of device memory accesses. The recommended practice for writing
22321  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22322  * alt_write_word() functions.
22323  *
22324  * The struct declaration for register ALT_EMAC_GMAC_TXUNICASTFRMS_GB.
22325  */
22326 struct ALT_EMAC_GMAC_TXUNICASTFRMS_GB_s
22327 {
22328  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT */
22329 };
22330 
22331 /* The typedef declaration for register ALT_EMAC_GMAC_TXUNICASTFRMS_GB. */
22332 typedef volatile struct ALT_EMAC_GMAC_TXUNICASTFRMS_GB_s ALT_EMAC_GMAC_TXUNICASTFRMS_GB_t;
22333 #endif /* __ASSEMBLY__ */
22334 
22335 /* The reset value of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB register. */
22336 #define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_RESET 0x00000000
22337 /* The byte offset of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB register from the beginning of the component. */
22338 #define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_OFST 0x13c
22339 /* The address of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB register. */
22340 #define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXUNICASTFRMS_GB_OFST))
22341 
22342 /*
22343  * Register : gmacgrp_txmulticastframes_gb
22344  *
22345  * <b> Register 80 (Transmit Frame Count for Good and Bad Multicast Frames) </b>
22346  *
22347  * This register maintains the number of transmitted good and bad multicast frames.
22348  *
22349  * Register Layout
22350  *
22351  * Bits | Access | Reset | Description
22352  * :-------|:-------|:------|:---------------------------------
22353  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT
22354  *
22355  */
22356 /*
22357  * Field : cnt
22358  *
22359  * This field indicates the number of transmitted good and bad multicast frames.
22360  *
22361  * Field Access Macros:
22362  *
22363  */
22364 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field. */
22365 #define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_LSB 0
22366 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field. */
22367 #define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_MSB 31
22368 /* The width in bits of the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field. */
22369 #define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_WIDTH 32
22370 /* The mask used to set the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field value. */
22371 #define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_SET_MSK 0xffffffff
22372 /* The mask used to clear the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field value. */
22373 #define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_CLR_MSK 0x00000000
22374 /* The reset value of the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field. */
22375 #define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_RESET 0x0
22376 /* Extracts the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT field value from a register. */
22377 #define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22378 /* Produces a ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field value suitable for setting the register. */
22379 #define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
22380 
22381 #ifndef __ASSEMBLY__
22382 /*
22383  * WARNING: The C register and register group struct declarations are provided for
22384  * convenience and illustrative purposes. They should, however, be used with
22385  * caution as the C language standard provides no guarantees about the alignment or
22386  * atomicity of device memory accesses. The recommended practice for writing
22387  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22388  * alt_write_word() functions.
22389  *
22390  * The struct declaration for register ALT_EMAC_GMAC_TXMCASTFRMS_GB.
22391  */
22392 struct ALT_EMAC_GMAC_TXMCASTFRMS_GB_s
22393 {
22394  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT */
22395 };
22396 
22397 /* The typedef declaration for register ALT_EMAC_GMAC_TXMCASTFRMS_GB. */
22398 typedef volatile struct ALT_EMAC_GMAC_TXMCASTFRMS_GB_s ALT_EMAC_GMAC_TXMCASTFRMS_GB_t;
22399 #endif /* __ASSEMBLY__ */
22400 
22401 /* The reset value of the ALT_EMAC_GMAC_TXMCASTFRMS_GB register. */
22402 #define ALT_EMAC_GMAC_TXMCASTFRMS_GB_RESET 0x00000000
22403 /* The byte offset of the ALT_EMAC_GMAC_TXMCASTFRMS_GB register from the beginning of the component. */
22404 #define ALT_EMAC_GMAC_TXMCASTFRMS_GB_OFST 0x140
22405 /* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_GB register. */
22406 #define ALT_EMAC_GMAC_TXMCASTFRMS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXMCASTFRMS_GB_OFST))
22407 
22408 /*
22409  * Register : gmacgrp_txbroadcastframes_gb
22410  *
22411  * <b> Register 81 (Transmit Frame Count for Good and Bad Broadcast Frames) </b>
22412  *
22413  * This register maintains the number of transmitted good and bad broadcast frames.
22414  *
22415  * Register Layout
22416  *
22417  * Bits | Access | Reset | Description
22418  * :-------|:-------|:------|:---------------------------------
22419  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT
22420  *
22421  */
22422 /*
22423  * Field : cnt
22424  *
22425  * This field indicates the number of transmitted good and bad broadcast frames.
22426  *
22427  * Field Access Macros:
22428  *
22429  */
22430 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field. */
22431 #define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_LSB 0
22432 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field. */
22433 #define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_MSB 31
22434 /* The width in bits of the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field. */
22435 #define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_WIDTH 32
22436 /* The mask used to set the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field value. */
22437 #define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_SET_MSK 0xffffffff
22438 /* The mask used to clear the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field value. */
22439 #define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_CLR_MSK 0x00000000
22440 /* The reset value of the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field. */
22441 #define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_RESET 0x0
22442 /* Extracts the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT field value from a register. */
22443 #define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22444 /* Produces a ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field value suitable for setting the register. */
22445 #define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
22446 
22447 #ifndef __ASSEMBLY__
22448 /*
22449  * WARNING: The C register and register group struct declarations are provided for
22450  * convenience and illustrative purposes. They should, however, be used with
22451  * caution as the C language standard provides no guarantees about the alignment or
22452  * atomicity of device memory accesses. The recommended practice for writing
22453  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22454  * alt_write_word() functions.
22455  *
22456  * The struct declaration for register ALT_EMAC_GMAC_TXBCASTFRMS_GB.
22457  */
22458 struct ALT_EMAC_GMAC_TXBCASTFRMS_GB_s
22459 {
22460  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT */
22461 };
22462 
22463 /* The typedef declaration for register ALT_EMAC_GMAC_TXBCASTFRMS_GB. */
22464 typedef volatile struct ALT_EMAC_GMAC_TXBCASTFRMS_GB_s ALT_EMAC_GMAC_TXBCASTFRMS_GB_t;
22465 #endif /* __ASSEMBLY__ */
22466 
22467 /* The reset value of the ALT_EMAC_GMAC_TXBCASTFRMS_GB register. */
22468 #define ALT_EMAC_GMAC_TXBCASTFRMS_GB_RESET 0x00000000
22469 /* The byte offset of the ALT_EMAC_GMAC_TXBCASTFRMS_GB register from the beginning of the component. */
22470 #define ALT_EMAC_GMAC_TXBCASTFRMS_GB_OFST 0x144
22471 /* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_GB register. */
22472 #define ALT_EMAC_GMAC_TXBCASTFRMS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXBCASTFRMS_GB_OFST))
22473 
22474 /*
22475  * Register : gmacgrp_txunderflowerror
22476  *
22477  * <b> Register 82 (Transmit Frame Count for Underflow Error Frames) </b>
22478  *
22479  * This register maintains the number of frames aborted because of frame underflow
22480  * error.
22481  *
22482  * Register Layout
22483  *
22484  * Bits | Access | Reset | Description
22485  * :-------|:-------|:------|:-----------------------------------
22486  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT
22487  *
22488  */
22489 /*
22490  * Field : cnt
22491  *
22492  * This field indicates the number of frames aborted because of frame underflow
22493  * error.
22494  *
22495  * Field Access Macros:
22496  *
22497  */
22498 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field. */
22499 #define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_LSB 0
22500 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field. */
22501 #define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_MSB 31
22502 /* The width in bits of the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field. */
22503 #define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_WIDTH 32
22504 /* The mask used to set the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field value. */
22505 #define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_SET_MSK 0xffffffff
22506 /* The mask used to clear the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field value. */
22507 #define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_CLR_MSK 0x00000000
22508 /* The reset value of the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field. */
22509 #define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_RESET 0x0
22510 /* Extracts the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT field value from a register. */
22511 #define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22512 /* Produces a ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field value suitable for setting the register. */
22513 #define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)
22514 
22515 #ifndef __ASSEMBLY__
22516 /*
22517  * WARNING: The C register and register group struct declarations are provided for
22518  * convenience and illustrative purposes. They should, however, be used with
22519  * caution as the C language standard provides no guarantees about the alignment or
22520  * atomicity of device memory accesses. The recommended practice for writing
22521  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22522  * alt_write_word() functions.
22523  *
22524  * The struct declaration for register ALT_EMAC_GMAC_TXUNDERFLOWERROR.
22525  */
22526 struct ALT_EMAC_GMAC_TXUNDERFLOWERROR_s
22527 {
22528  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT */
22529 };
22530 
22531 /* The typedef declaration for register ALT_EMAC_GMAC_TXUNDERFLOWERROR. */
22532 typedef volatile struct ALT_EMAC_GMAC_TXUNDERFLOWERROR_s ALT_EMAC_GMAC_TXUNDERFLOWERROR_t;
22533 #endif /* __ASSEMBLY__ */
22534 
22535 /* The reset value of the ALT_EMAC_GMAC_TXUNDERFLOWERROR register. */
22536 #define ALT_EMAC_GMAC_TXUNDERFLOWERROR_RESET 0x00000000
22537 /* The byte offset of the ALT_EMAC_GMAC_TXUNDERFLOWERROR register from the beginning of the component. */
22538 #define ALT_EMAC_GMAC_TXUNDERFLOWERROR_OFST 0x148
22539 /* The address of the ALT_EMAC_GMAC_TXUNDERFLOWERROR register. */
22540 #define ALT_EMAC_GMAC_TXUNDERFLOWERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXUNDERFLOWERROR_OFST))
22541 
22542 /*
22543  * Register : gmacgrp_txsinglecol_g
22544  *
22545  * <b> Register 83 (Transmit Frame Count for Frames Transmitted after Single
22546  * Collision) </b>
22547  *
22548  * This register maintains the number of successfully transmitted frames after a
22549  * single collision in the half-duplex mode.
22550  *
22551  * Register Layout
22552  *
22553  * Bits | Access | Reset | Description
22554  * :-------|:-------|:------|:--------------------------------
22555  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TXSINGLECOL_G_CNT
22556  *
22557  */
22558 /*
22559  * Field : cnt
22560  *
22561  * This field indicates the number of successfully transmitted frames after a
22562  * single collision in the half-duplex mode.
22563  *
22564  * Field Access Macros:
22565  *
22566  */
22567 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field. */
22568 #define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_LSB 0
22569 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field. */
22570 #define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_MSB 31
22571 /* The width in bits of the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field. */
22572 #define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_WIDTH 32
22573 /* The mask used to set the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field value. */
22574 #define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_SET_MSK 0xffffffff
22575 /* The mask used to clear the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field value. */
22576 #define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_CLR_MSK 0x00000000
22577 /* The reset value of the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field. */
22578 #define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_RESET 0x0
22579 /* Extracts the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT field value from a register. */
22580 #define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22581 /* Produces a ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field value suitable for setting the register. */
22582 #define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
22583 
22584 #ifndef __ASSEMBLY__
22585 /*
22586  * WARNING: The C register and register group struct declarations are provided for
22587  * convenience and illustrative purposes. They should, however, be used with
22588  * caution as the C language standard provides no guarantees about the alignment or
22589  * atomicity of device memory accesses. The recommended practice for writing
22590  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22591  * alt_write_word() functions.
22592  *
22593  * The struct declaration for register ALT_EMAC_GMAC_TXSINGLECOL_G.
22594  */
22595 struct ALT_EMAC_GMAC_TXSINGLECOL_G_s
22596 {
22597  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TXSINGLECOL_G_CNT */
22598 };
22599 
22600 /* The typedef declaration for register ALT_EMAC_GMAC_TXSINGLECOL_G. */
22601 typedef volatile struct ALT_EMAC_GMAC_TXSINGLECOL_G_s ALT_EMAC_GMAC_TXSINGLECOL_G_t;
22602 #endif /* __ASSEMBLY__ */
22603 
22604 /* The reset value of the ALT_EMAC_GMAC_TXSINGLECOL_G register. */
22605 #define ALT_EMAC_GMAC_TXSINGLECOL_G_RESET 0x00000000
22606 /* The byte offset of the ALT_EMAC_GMAC_TXSINGLECOL_G register from the beginning of the component. */
22607 #define ALT_EMAC_GMAC_TXSINGLECOL_G_OFST 0x14c
22608 /* The address of the ALT_EMAC_GMAC_TXSINGLECOL_G register. */
22609 #define ALT_EMAC_GMAC_TXSINGLECOL_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXSINGLECOL_G_OFST))
22610 
22611 /*
22612  * Register : gmacgrp_txmulticol_g
22613  *
22614  * <b> Register 84 (Transmit Frame Count for Frames Transmitted after Multiple
22615  * Collision) </b>
22616  *
22617  * This register maintains the number of successfully transmitted frames after
22618  * multiple collisions in the half-duplex mode.
22619  *
22620  * Register Layout
22621  *
22622  * Bits | Access | Reset | Description
22623  * :-------|:-------|:------|:-------------------------------
22624  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TXMULTICOL_G_CNT
22625  *
22626  */
22627 /*
22628  * Field : cnt
22629  *
22630  * This field indicates the number of successfully transmitted frames after
22631  * multiple collisions in the half-duplex mode.
22632  *
22633  * Field Access Macros:
22634  *
22635  */
22636 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field. */
22637 #define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_LSB 0
22638 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field. */
22639 #define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_MSB 31
22640 /* The width in bits of the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field. */
22641 #define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_WIDTH 32
22642 /* The mask used to set the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field value. */
22643 #define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_SET_MSK 0xffffffff
22644 /* The mask used to clear the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field value. */
22645 #define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_CLR_MSK 0x00000000
22646 /* The reset value of the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field. */
22647 #define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_RESET 0x0
22648 /* Extracts the ALT_EMAC_GMAC_TXMULTICOL_G_CNT field value from a register. */
22649 #define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22650 /* Produces a ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field value suitable for setting the register. */
22651 #define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
22652 
22653 #ifndef __ASSEMBLY__
22654 /*
22655  * WARNING: The C register and register group struct declarations are provided for
22656  * convenience and illustrative purposes. They should, however, be used with
22657  * caution as the C language standard provides no guarantees about the alignment or
22658  * atomicity of device memory accesses. The recommended practice for writing
22659  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22660  * alt_write_word() functions.
22661  *
22662  * The struct declaration for register ALT_EMAC_GMAC_TXMULTICOL_G.
22663  */
22664 struct ALT_EMAC_GMAC_TXMULTICOL_G_s
22665 {
22666  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TXMULTICOL_G_CNT */
22667 };
22668 
22669 /* The typedef declaration for register ALT_EMAC_GMAC_TXMULTICOL_G. */
22670 typedef volatile struct ALT_EMAC_GMAC_TXMULTICOL_G_s ALT_EMAC_GMAC_TXMULTICOL_G_t;
22671 #endif /* __ASSEMBLY__ */
22672 
22673 /* The reset value of the ALT_EMAC_GMAC_TXMULTICOL_G register. */
22674 #define ALT_EMAC_GMAC_TXMULTICOL_G_RESET 0x00000000
22675 /* The byte offset of the ALT_EMAC_GMAC_TXMULTICOL_G register from the beginning of the component. */
22676 #define ALT_EMAC_GMAC_TXMULTICOL_G_OFST 0x150
22677 /* The address of the ALT_EMAC_GMAC_TXMULTICOL_G register. */
22678 #define ALT_EMAC_GMAC_TXMULTICOL_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXMULTICOL_G_OFST))
22679 
22680 /*
22681  * Register : gmacgrp_txdeferred
22682  *
22683  * <b> Register 85 (Transmit Frame Count for Deferred Frames) </b>
22684  *
22685  * This register maintains the number of successfully transmitted frames after a
22686  * deferral in the half-duplex mode.
22687  *
22688  * Register Layout
22689  *
22690  * Bits | Access | Reset | Description
22691  * :-------|:-------|:------|:-----------------------------
22692  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TXDEFERRED_CNT
22693  *
22694  */
22695 /*
22696  * Field : cnt
22697  *
22698  * This field indicates the number of successfully transmitted frames after a
22699  * deferral in the half-duplex mode.
22700  *
22701  * Field Access Macros:
22702  *
22703  */
22704 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXDEFERRED_CNT register field. */
22705 #define ALT_EMAC_GMAC_TXDEFERRED_CNT_LSB 0
22706 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXDEFERRED_CNT register field. */
22707 #define ALT_EMAC_GMAC_TXDEFERRED_CNT_MSB 31
22708 /* The width in bits of the ALT_EMAC_GMAC_TXDEFERRED_CNT register field. */
22709 #define ALT_EMAC_GMAC_TXDEFERRED_CNT_WIDTH 32
22710 /* The mask used to set the ALT_EMAC_GMAC_TXDEFERRED_CNT register field value. */
22711 #define ALT_EMAC_GMAC_TXDEFERRED_CNT_SET_MSK 0xffffffff
22712 /* The mask used to clear the ALT_EMAC_GMAC_TXDEFERRED_CNT register field value. */
22713 #define ALT_EMAC_GMAC_TXDEFERRED_CNT_CLR_MSK 0x00000000
22714 /* The reset value of the ALT_EMAC_GMAC_TXDEFERRED_CNT register field. */
22715 #define ALT_EMAC_GMAC_TXDEFERRED_CNT_RESET 0x0
22716 /* Extracts the ALT_EMAC_GMAC_TXDEFERRED_CNT field value from a register. */
22717 #define ALT_EMAC_GMAC_TXDEFERRED_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22718 /* Produces a ALT_EMAC_GMAC_TXDEFERRED_CNT register field value suitable for setting the register. */
22719 #define ALT_EMAC_GMAC_TXDEFERRED_CNT_SET(value) (((value) << 0) & 0xffffffff)
22720 
22721 #ifndef __ASSEMBLY__
22722 /*
22723  * WARNING: The C register and register group struct declarations are provided for
22724  * convenience and illustrative purposes. They should, however, be used with
22725  * caution as the C language standard provides no guarantees about the alignment or
22726  * atomicity of device memory accesses. The recommended practice for writing
22727  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22728  * alt_write_word() functions.
22729  *
22730  * The struct declaration for register ALT_EMAC_GMAC_TXDEFERRED.
22731  */
22732 struct ALT_EMAC_GMAC_TXDEFERRED_s
22733 {
22734  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TXDEFERRED_CNT */
22735 };
22736 
22737 /* The typedef declaration for register ALT_EMAC_GMAC_TXDEFERRED. */
22738 typedef volatile struct ALT_EMAC_GMAC_TXDEFERRED_s ALT_EMAC_GMAC_TXDEFERRED_t;
22739 #endif /* __ASSEMBLY__ */
22740 
22741 /* The reset value of the ALT_EMAC_GMAC_TXDEFERRED register. */
22742 #define ALT_EMAC_GMAC_TXDEFERRED_RESET 0x00000000
22743 /* The byte offset of the ALT_EMAC_GMAC_TXDEFERRED register from the beginning of the component. */
22744 #define ALT_EMAC_GMAC_TXDEFERRED_OFST 0x154
22745 /* The address of the ALT_EMAC_GMAC_TXDEFERRED register. */
22746 #define ALT_EMAC_GMAC_TXDEFERRED_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXDEFERRED_OFST))
22747 
22748 /*
22749  * Register : gmacgrp_txlatecol
22750  *
22751  * <b> Register 86 (Transmit Frame Count for Late Collision Error Frames) </b>
22752  *
22753  * This register maintains the number of frames aborted because of late collision
22754  * error.
22755  *
22756  * Register Layout
22757  *
22758  * Bits | Access | Reset | Description
22759  * :-------|:-------|:------|:----------------------------
22760  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TXLATECOL_CNT
22761  *
22762  */
22763 /*
22764  * Field : cnt
22765  *
22766  * This field indicates the number of frames aborted because of late collision
22767  * error.
22768  *
22769  * Field Access Macros:
22770  *
22771  */
22772 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXLATECOL_CNT register field. */
22773 #define ALT_EMAC_GMAC_TXLATECOL_CNT_LSB 0
22774 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXLATECOL_CNT register field. */
22775 #define ALT_EMAC_GMAC_TXLATECOL_CNT_MSB 31
22776 /* The width in bits of the ALT_EMAC_GMAC_TXLATECOL_CNT register field. */
22777 #define ALT_EMAC_GMAC_TXLATECOL_CNT_WIDTH 32
22778 /* The mask used to set the ALT_EMAC_GMAC_TXLATECOL_CNT register field value. */
22779 #define ALT_EMAC_GMAC_TXLATECOL_CNT_SET_MSK 0xffffffff
22780 /* The mask used to clear the ALT_EMAC_GMAC_TXLATECOL_CNT register field value. */
22781 #define ALT_EMAC_GMAC_TXLATECOL_CNT_CLR_MSK 0x00000000
22782 /* The reset value of the ALT_EMAC_GMAC_TXLATECOL_CNT register field. */
22783 #define ALT_EMAC_GMAC_TXLATECOL_CNT_RESET 0x0
22784 /* Extracts the ALT_EMAC_GMAC_TXLATECOL_CNT field value from a register. */
22785 #define ALT_EMAC_GMAC_TXLATECOL_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22786 /* Produces a ALT_EMAC_GMAC_TXLATECOL_CNT register field value suitable for setting the register. */
22787 #define ALT_EMAC_GMAC_TXLATECOL_CNT_SET(value) (((value) << 0) & 0xffffffff)
22788 
22789 #ifndef __ASSEMBLY__
22790 /*
22791  * WARNING: The C register and register group struct declarations are provided for
22792  * convenience and illustrative purposes. They should, however, be used with
22793  * caution as the C language standard provides no guarantees about the alignment or
22794  * atomicity of device memory accesses. The recommended practice for writing
22795  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22796  * alt_write_word() functions.
22797  *
22798  * The struct declaration for register ALT_EMAC_GMAC_TXLATECOL.
22799  */
22800 struct ALT_EMAC_GMAC_TXLATECOL_s
22801 {
22802  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TXLATECOL_CNT */
22803 };
22804 
22805 /* The typedef declaration for register ALT_EMAC_GMAC_TXLATECOL. */
22806 typedef volatile struct ALT_EMAC_GMAC_TXLATECOL_s ALT_EMAC_GMAC_TXLATECOL_t;
22807 #endif /* __ASSEMBLY__ */
22808 
22809 /* The reset value of the ALT_EMAC_GMAC_TXLATECOL register. */
22810 #define ALT_EMAC_GMAC_TXLATECOL_RESET 0x00000000
22811 /* The byte offset of the ALT_EMAC_GMAC_TXLATECOL register from the beginning of the component. */
22812 #define ALT_EMAC_GMAC_TXLATECOL_OFST 0x158
22813 /* The address of the ALT_EMAC_GMAC_TXLATECOL register. */
22814 #define ALT_EMAC_GMAC_TXLATECOL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXLATECOL_OFST))
22815 
22816 /*
22817  * Register : gmacgrp_txexesscol
22818  *
22819  * <b> Register 87 (Transmit Frame Count for Excessive Collision Error Frames) </b>
22820  *
22821  * This register maintains the number of frames aborted because of excessive (16)
22822  * collision error.
22823  *
22824  * Register Layout
22825  *
22826  * Bits | Access | Reset | Description
22827  * :-------|:-------|:------|:-----------------------------
22828  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TXEXESSCOL_CNT
22829  *
22830  */
22831 /*
22832  * Field : cnt
22833  *
22834  * This field indicates the number of frames aborted because of excessive (16)
22835  * collision error.
22836  *
22837  * Field Access Macros:
22838  *
22839  */
22840 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field. */
22841 #define ALT_EMAC_GMAC_TXEXESSCOL_CNT_LSB 0
22842 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field. */
22843 #define ALT_EMAC_GMAC_TXEXESSCOL_CNT_MSB 31
22844 /* The width in bits of the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field. */
22845 #define ALT_EMAC_GMAC_TXEXESSCOL_CNT_WIDTH 32
22846 /* The mask used to set the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field value. */
22847 #define ALT_EMAC_GMAC_TXEXESSCOL_CNT_SET_MSK 0xffffffff
22848 /* The mask used to clear the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field value. */
22849 #define ALT_EMAC_GMAC_TXEXESSCOL_CNT_CLR_MSK 0x00000000
22850 /* The reset value of the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field. */
22851 #define ALT_EMAC_GMAC_TXEXESSCOL_CNT_RESET 0x0
22852 /* Extracts the ALT_EMAC_GMAC_TXEXESSCOL_CNT field value from a register. */
22853 #define ALT_EMAC_GMAC_TXEXESSCOL_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22854 /* Produces a ALT_EMAC_GMAC_TXEXESSCOL_CNT register field value suitable for setting the register. */
22855 #define ALT_EMAC_GMAC_TXEXESSCOL_CNT_SET(value) (((value) << 0) & 0xffffffff)
22856 
22857 #ifndef __ASSEMBLY__
22858 /*
22859  * WARNING: The C register and register group struct declarations are provided for
22860  * convenience and illustrative purposes. They should, however, be used with
22861  * caution as the C language standard provides no guarantees about the alignment or
22862  * atomicity of device memory accesses. The recommended practice for writing
22863  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22864  * alt_write_word() functions.
22865  *
22866  * The struct declaration for register ALT_EMAC_GMAC_TXEXESSCOL.
22867  */
22868 struct ALT_EMAC_GMAC_TXEXESSCOL_s
22869 {
22870  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TXEXESSCOL_CNT */
22871 };
22872 
22873 /* The typedef declaration for register ALT_EMAC_GMAC_TXEXESSCOL. */
22874 typedef volatile struct ALT_EMAC_GMAC_TXEXESSCOL_s ALT_EMAC_GMAC_TXEXESSCOL_t;
22875 #endif /* __ASSEMBLY__ */
22876 
22877 /* The reset value of the ALT_EMAC_GMAC_TXEXESSCOL register. */
22878 #define ALT_EMAC_GMAC_TXEXESSCOL_RESET 0x00000000
22879 /* The byte offset of the ALT_EMAC_GMAC_TXEXESSCOL register from the beginning of the component. */
22880 #define ALT_EMAC_GMAC_TXEXESSCOL_OFST 0x15c
22881 /* The address of the ALT_EMAC_GMAC_TXEXESSCOL register. */
22882 #define ALT_EMAC_GMAC_TXEXESSCOL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXEXESSCOL_OFST))
22883 
22884 /*
22885  * Register : gmacgrp_txcarriererr
22886  *
22887  * <b> Register 88 (Transmit Frame Count for Carrier Sense Error Frames) </b>
22888  *
22889  * This register maintains the number of frames aborted because of carrier sense
22890  * error (no carrier or loss of carrier).
22891  *
22892  * Register Layout
22893  *
22894  * Bits | Access | Reset | Description
22895  * :-------|:-------|:------|:-------------------------------
22896  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TXCARRIERERR_CNT
22897  *
22898  */
22899 /*
22900  * Field : cnt
22901  *
22902  * This field indicates the number of frames aborted because of carrier sense error
22903  * (no carrier or loss of carrier).
22904  *
22905  * Field Access Macros:
22906  *
22907  */
22908 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field. */
22909 #define ALT_EMAC_GMAC_TXCARRIERERR_CNT_LSB 0
22910 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field. */
22911 #define ALT_EMAC_GMAC_TXCARRIERERR_CNT_MSB 31
22912 /* The width in bits of the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field. */
22913 #define ALT_EMAC_GMAC_TXCARRIERERR_CNT_WIDTH 32
22914 /* The mask used to set the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field value. */
22915 #define ALT_EMAC_GMAC_TXCARRIERERR_CNT_SET_MSK 0xffffffff
22916 /* The mask used to clear the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field value. */
22917 #define ALT_EMAC_GMAC_TXCARRIERERR_CNT_CLR_MSK 0x00000000
22918 /* The reset value of the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field. */
22919 #define ALT_EMAC_GMAC_TXCARRIERERR_CNT_RESET 0x0
22920 /* Extracts the ALT_EMAC_GMAC_TXCARRIERERR_CNT field value from a register. */
22921 #define ALT_EMAC_GMAC_TXCARRIERERR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22922 /* Produces a ALT_EMAC_GMAC_TXCARRIERERR_CNT register field value suitable for setting the register. */
22923 #define ALT_EMAC_GMAC_TXCARRIERERR_CNT_SET(value) (((value) << 0) & 0xffffffff)
22924 
22925 #ifndef __ASSEMBLY__
22926 /*
22927  * WARNING: The C register and register group struct declarations are provided for
22928  * convenience and illustrative purposes. They should, however, be used with
22929  * caution as the C language standard provides no guarantees about the alignment or
22930  * atomicity of device memory accesses. The recommended practice for writing
22931  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22932  * alt_write_word() functions.
22933  *
22934  * The struct declaration for register ALT_EMAC_GMAC_TXCARRIERERR.
22935  */
22936 struct ALT_EMAC_GMAC_TXCARRIERERR_s
22937 {
22938  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TXCARRIERERR_CNT */
22939 };
22940 
22941 /* The typedef declaration for register ALT_EMAC_GMAC_TXCARRIERERR. */
22942 typedef volatile struct ALT_EMAC_GMAC_TXCARRIERERR_s ALT_EMAC_GMAC_TXCARRIERERR_t;
22943 #endif /* __ASSEMBLY__ */
22944 
22945 /* The reset value of the ALT_EMAC_GMAC_TXCARRIERERR register. */
22946 #define ALT_EMAC_GMAC_TXCARRIERERR_RESET 0x00000000
22947 /* The byte offset of the ALT_EMAC_GMAC_TXCARRIERERR register from the beginning of the component. */
22948 #define ALT_EMAC_GMAC_TXCARRIERERR_OFST 0x160
22949 /* The address of the ALT_EMAC_GMAC_TXCARRIERERR register. */
22950 #define ALT_EMAC_GMAC_TXCARRIERERR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXCARRIERERR_OFST))
22951 
22952 /*
22953  * Register : gmacgrp_txoctetcnt
22954  *
22955  * <b> Register 89 (Transmit Octet Count for Good Frames) </b>
22956  *
22957  * This register maintains the number of bytes transmitted, exclusive of preamble,
22958  * in good frames.
22959  *
22960  * Register Layout
22961  *
22962  * Bits | Access | Reset | Description
22963  * :-------|:-------|:------|:----------------------------------------
22964  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G
22965  *
22966  */
22967 /*
22968  * Field : txoctetcount_g
22969  *
22970  * This field indicates the number of bytes transmitted, exclusive of preamble, in
22971  * good frames.
22972  *
22973  * Field Access Macros:
22974  *
22975  */
22976 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field. */
22977 #define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_LSB 0
22978 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field. */
22979 #define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_MSB 31
22980 /* The width in bits of the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field. */
22981 #define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_WIDTH 32
22982 /* The mask used to set the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field value. */
22983 #define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_SET_MSK 0xffffffff
22984 /* The mask used to clear the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field value. */
22985 #define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_CLR_MSK 0x00000000
22986 /* The reset value of the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field. */
22987 #define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_RESET 0x0
22988 /* Extracts the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G field value from a register. */
22989 #define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_GET(value) (((value) & 0xffffffff) >> 0)
22990 /* Produces a ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field value suitable for setting the register. */
22991 #define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_SET(value) (((value) << 0) & 0xffffffff)
22992 
22993 #ifndef __ASSEMBLY__
22994 /*
22995  * WARNING: The C register and register group struct declarations are provided for
22996  * convenience and illustrative purposes. They should, however, be used with
22997  * caution as the C language standard provides no guarantees about the alignment or
22998  * atomicity of device memory accesses. The recommended practice for writing
22999  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23000  * alt_write_word() functions.
23001  *
23002  * The struct declaration for register ALT_EMAC_GMAC_TXOCTETCNT.
23003  */
23004 struct ALT_EMAC_GMAC_TXOCTETCNT_s
23005 {
23006  const uint32_t txoctetcount_g : 32; /* ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G */
23007 };
23008 
23009 /* The typedef declaration for register ALT_EMAC_GMAC_TXOCTETCNT. */
23010 typedef volatile struct ALT_EMAC_GMAC_TXOCTETCNT_s ALT_EMAC_GMAC_TXOCTETCNT_t;
23011 #endif /* __ASSEMBLY__ */
23012 
23013 /* The reset value of the ALT_EMAC_GMAC_TXOCTETCNT register. */
23014 #define ALT_EMAC_GMAC_TXOCTETCNT_RESET 0x00000000
23015 /* The byte offset of the ALT_EMAC_GMAC_TXOCTETCNT register from the beginning of the component. */
23016 #define ALT_EMAC_GMAC_TXOCTETCNT_OFST 0x164
23017 /* The address of the ALT_EMAC_GMAC_TXOCTETCNT register. */
23018 #define ALT_EMAC_GMAC_TXOCTETCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXOCTETCNT_OFST))
23019 
23020 /*
23021  * Register : gmacgrp_txframecount_g
23022  *
23023  * <b> Register 90 (Transmit Frame Count for Good Frames) </b>
23024  *
23025  * This register maintains the number of transmitted good frames, exclusive of
23026  * preamble.
23027  *
23028  * Register Layout
23029  *
23030  * Bits | Access | Reset | Description
23031  * :-------|:-------|:------|:-------------------------------
23032  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT
23033  *
23034  */
23035 /*
23036  * Field : cnt
23037  *
23038  * This field indicates the number of transmitted good frames, exclusive of
23039  * preamble.
23040  *
23041  * Field Access Macros:
23042  *
23043  */
23044 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field. */
23045 #define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_LSB 0
23046 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field. */
23047 #define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_MSB 31
23048 /* The width in bits of the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field. */
23049 #define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_WIDTH 32
23050 /* The mask used to set the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field value. */
23051 #define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_SET_MSK 0xffffffff
23052 /* The mask used to clear the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field value. */
23053 #define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_CLR_MSK 0x00000000
23054 /* The reset value of the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field. */
23055 #define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_RESET 0x0
23056 /* Extracts the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT field value from a register. */
23057 #define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
23058 /* Produces a ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field value suitable for setting the register. */
23059 #define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
23060 
23061 #ifndef __ASSEMBLY__
23062 /*
23063  * WARNING: The C register and register group struct declarations are provided for
23064  * convenience and illustrative purposes. They should, however, be used with
23065  * caution as the C language standard provides no guarantees about the alignment or
23066  * atomicity of device memory accesses. The recommended practice for writing
23067  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23068  * alt_write_word() functions.
23069  *
23070  * The struct declaration for register ALT_EMAC_GMAC_TXFRMCOUNT_G.
23071  */
23072 struct ALT_EMAC_GMAC_TXFRMCOUNT_G_s
23073 {
23074  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT */
23075 };
23076 
23077 /* The typedef declaration for register ALT_EMAC_GMAC_TXFRMCOUNT_G. */
23078 typedef volatile struct ALT_EMAC_GMAC_TXFRMCOUNT_G_s ALT_EMAC_GMAC_TXFRMCOUNT_G_t;
23079 #endif /* __ASSEMBLY__ */
23080 
23081 /* The reset value of the ALT_EMAC_GMAC_TXFRMCOUNT_G register. */
23082 #define ALT_EMAC_GMAC_TXFRMCOUNT_G_RESET 0x00000000
23083 /* The byte offset of the ALT_EMAC_GMAC_TXFRMCOUNT_G register from the beginning of the component. */
23084 #define ALT_EMAC_GMAC_TXFRMCOUNT_G_OFST 0x168
23085 /* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_G register. */
23086 #define ALT_EMAC_GMAC_TXFRMCOUNT_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXFRMCOUNT_G_OFST))
23087 
23088 /*
23089  * Register : gmacgrp_txexcessdef
23090  *
23091  * <b> Register 91 (Transmit Frame Count for Excessive Deferral Error Frames) </b>
23092  *
23093  * This register maintains the number of frames aborted because of excessive
23094  * deferral error, that is, frames deferred for more than two max-sized frame
23095  * times.
23096  *
23097  * Register Layout
23098  *
23099  * Bits | Access | Reset | Description
23100  * :-------|:-------|:------|:------------------------------
23101  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TXEXCESSDEF_CNT
23102  *
23103  */
23104 /*
23105  * Field : cnt
23106  *
23107  * This field indicates the number of frames aborted because of excessive deferral
23108  * error, that is, frames deferred for more than two max-sized frame times.
23109  *
23110  * Field Access Macros:
23111  *
23112  */
23113 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field. */
23114 #define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_LSB 0
23115 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field. */
23116 #define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_MSB 31
23117 /* The width in bits of the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field. */
23118 #define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_WIDTH 32
23119 /* The mask used to set the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field value. */
23120 #define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_SET_MSK 0xffffffff
23121 /* The mask used to clear the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field value. */
23122 #define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_CLR_MSK 0x00000000
23123 /* The reset value of the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field. */
23124 #define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_RESET 0x0
23125 /* Extracts the ALT_EMAC_GMAC_TXEXCESSDEF_CNT field value from a register. */
23126 #define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_GET(value) (((value) & 0xffffffff) >> 0)
23127 /* Produces a ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field value suitable for setting the register. */
23128 #define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_SET(value) (((value) << 0) & 0xffffffff)
23129 
23130 #ifndef __ASSEMBLY__
23131 /*
23132  * WARNING: The C register and register group struct declarations are provided for
23133  * convenience and illustrative purposes. They should, however, be used with
23134  * caution as the C language standard provides no guarantees about the alignment or
23135  * atomicity of device memory accesses. The recommended practice for writing
23136  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23137  * alt_write_word() functions.
23138  *
23139  * The struct declaration for register ALT_EMAC_GMAC_TXEXCESSDEF.
23140  */
23141 struct ALT_EMAC_GMAC_TXEXCESSDEF_s
23142 {
23143  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TXEXCESSDEF_CNT */
23144 };
23145 
23146 /* The typedef declaration for register ALT_EMAC_GMAC_TXEXCESSDEF. */
23147 typedef volatile struct ALT_EMAC_GMAC_TXEXCESSDEF_s ALT_EMAC_GMAC_TXEXCESSDEF_t;
23148 #endif /* __ASSEMBLY__ */
23149 
23150 /* The reset value of the ALT_EMAC_GMAC_TXEXCESSDEF register. */
23151 #define ALT_EMAC_GMAC_TXEXCESSDEF_RESET 0x00000000
23152 /* The byte offset of the ALT_EMAC_GMAC_TXEXCESSDEF register from the beginning of the component. */
23153 #define ALT_EMAC_GMAC_TXEXCESSDEF_OFST 0x16c
23154 /* The address of the ALT_EMAC_GMAC_TXEXCESSDEF register. */
23155 #define ALT_EMAC_GMAC_TXEXCESSDEF_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXEXCESSDEF_OFST))
23156 
23157 /*
23158  * Register : gmacgrp_txpauseframes
23159  *
23160  * <b> Register 92 (Transmit Frame Count for Good PAUSE Frames) </b>
23161  *
23162  * This register maintains the number of transmitted good PAUSE frames.
23163  *
23164  * Register Layout
23165  *
23166  * Bits | Access | Reset | Description
23167  * :-------|:-------|:------|:------------------------------
23168  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TXPAUSEFRMS_CNT
23169  *
23170  */
23171 /*
23172  * Field : cnt
23173  *
23174  * This field indicates the number of transmitted good PAUSE frames.
23175  *
23176  * Field Access Macros:
23177  *
23178  */
23179 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field. */
23180 #define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_LSB 0
23181 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field. */
23182 #define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_MSB 31
23183 /* The width in bits of the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field. */
23184 #define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_WIDTH 32
23185 /* The mask used to set the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field value. */
23186 #define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_SET_MSK 0xffffffff
23187 /* The mask used to clear the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field value. */
23188 #define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_CLR_MSK 0x00000000
23189 /* The reset value of the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field. */
23190 #define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_RESET 0x0
23191 /* Extracts the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT field value from a register. */
23192 #define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
23193 /* Produces a ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field value suitable for setting the register. */
23194 #define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
23195 
23196 #ifndef __ASSEMBLY__
23197 /*
23198  * WARNING: The C register and register group struct declarations are provided for
23199  * convenience and illustrative purposes. They should, however, be used with
23200  * caution as the C language standard provides no guarantees about the alignment or
23201  * atomicity of device memory accesses. The recommended practice for writing
23202  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23203  * alt_write_word() functions.
23204  *
23205  * The struct declaration for register ALT_EMAC_GMAC_TXPAUSEFRMS.
23206  */
23207 struct ALT_EMAC_GMAC_TXPAUSEFRMS_s
23208 {
23209  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TXPAUSEFRMS_CNT */
23210 };
23211 
23212 /* The typedef declaration for register ALT_EMAC_GMAC_TXPAUSEFRMS. */
23213 typedef volatile struct ALT_EMAC_GMAC_TXPAUSEFRMS_s ALT_EMAC_GMAC_TXPAUSEFRMS_t;
23214 #endif /* __ASSEMBLY__ */
23215 
23216 /* The reset value of the ALT_EMAC_GMAC_TXPAUSEFRMS register. */
23217 #define ALT_EMAC_GMAC_TXPAUSEFRMS_RESET 0x00000000
23218 /* The byte offset of the ALT_EMAC_GMAC_TXPAUSEFRMS register from the beginning of the component. */
23219 #define ALT_EMAC_GMAC_TXPAUSEFRMS_OFST 0x170
23220 /* The address of the ALT_EMAC_GMAC_TXPAUSEFRMS register. */
23221 #define ALT_EMAC_GMAC_TXPAUSEFRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXPAUSEFRMS_OFST))
23222 
23223 /*
23224  * Register : gmacgrp_txvlanframes_g
23225  *
23226  * <b> Register 93 (Transmit Frame Count for Good VLAN Frames) </b>
23227  *
23228  * This register maintains the number of transmitted good VLAN frames, exclusive of
23229  * retried frames.
23230  *
23231  * Register Layout
23232  *
23233  * Bits | Access | Reset | Description
23234  * :-------|:-------|:------|:-------------------------------
23235  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TXVLANFRMS_G_CNT
23236  *
23237  */
23238 /*
23239  * Field : cnt
23240  *
23241  * This register maintains the number of transmitted good VLAN frames, exclusive of
23242  * retried frames.
23243  *
23244  * Field Access Macros:
23245  *
23246  */
23247 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field. */
23248 #define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_LSB 0
23249 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field. */
23250 #define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_MSB 31
23251 /* The width in bits of the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field. */
23252 #define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_WIDTH 32
23253 /* The mask used to set the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field value. */
23254 #define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_SET_MSK 0xffffffff
23255 /* The mask used to clear the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field value. */
23256 #define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_CLR_MSK 0x00000000
23257 /* The reset value of the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field. */
23258 #define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_RESET 0x0
23259 /* Extracts the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT field value from a register. */
23260 #define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
23261 /* Produces a ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field value suitable for setting the register. */
23262 #define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
23263 
23264 #ifndef __ASSEMBLY__
23265 /*
23266  * WARNING: The C register and register group struct declarations are provided for
23267  * convenience and illustrative purposes. They should, however, be used with
23268  * caution as the C language standard provides no guarantees about the alignment or
23269  * atomicity of device memory accesses. The recommended practice for writing
23270  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23271  * alt_write_word() functions.
23272  *
23273  * The struct declaration for register ALT_EMAC_GMAC_TXVLANFRMS_G.
23274  */
23275 struct ALT_EMAC_GMAC_TXVLANFRMS_G_s
23276 {
23277  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TXVLANFRMS_G_CNT */
23278 };
23279 
23280 /* The typedef declaration for register ALT_EMAC_GMAC_TXVLANFRMS_G. */
23281 typedef volatile struct ALT_EMAC_GMAC_TXVLANFRMS_G_s ALT_EMAC_GMAC_TXVLANFRMS_G_t;
23282 #endif /* __ASSEMBLY__ */
23283 
23284 /* The reset value of the ALT_EMAC_GMAC_TXVLANFRMS_G register. */
23285 #define ALT_EMAC_GMAC_TXVLANFRMS_G_RESET 0x00000000
23286 /* The byte offset of the ALT_EMAC_GMAC_TXVLANFRMS_G register from the beginning of the component. */
23287 #define ALT_EMAC_GMAC_TXVLANFRMS_G_OFST 0x174
23288 /* The address of the ALT_EMAC_GMAC_TXVLANFRMS_G register. */
23289 #define ALT_EMAC_GMAC_TXVLANFRMS_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXVLANFRMS_G_OFST))
23290 
23291 /*
23292  * Register : gmacgrp_txoversize_g
23293  *
23294  * <b> Register 94 (Transmit Frame Count for Good Oversize Frames) </b>
23295  *
23296  * This register maintains the number of transmitted good Oversize frames,
23297  * exclusive of retried frames.
23298  *
23299  * Register Layout
23300  *
23301  * Bits | Access | Reset | Description
23302  * :-------|:-------|:------|:-------------------------------
23303  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_TXOVERSIZE_G_CNT
23304  *
23305  */
23306 /*
23307  * Field : cnt
23308  *
23309  * This field indicates the number of frames transmitted without errors and with
23310  * length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged frames;
23311  * 2000 bytes if enabled in bit 27 of Register 0 (MAC Configuration Register)).
23312  *
23313  * Field Access Macros:
23314  *
23315  */
23316 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field. */
23317 #define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_LSB 0
23318 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field. */
23319 #define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_MSB 31
23320 /* The width in bits of the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field. */
23321 #define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_WIDTH 32
23322 /* The mask used to set the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field value. */
23323 #define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_SET_MSK 0xffffffff
23324 /* The mask used to clear the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field value. */
23325 #define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_CLR_MSK 0x00000000
23326 /* The reset value of the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field. */
23327 #define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_RESET 0x0
23328 /* Extracts the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT field value from a register. */
23329 #define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
23330 /* Produces a ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field value suitable for setting the register. */
23331 #define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
23332 
23333 #ifndef __ASSEMBLY__
23334 /*
23335  * WARNING: The C register and register group struct declarations are provided for
23336  * convenience and illustrative purposes. They should, however, be used with
23337  * caution as the C language standard provides no guarantees about the alignment or
23338  * atomicity of device memory accesses. The recommended practice for writing
23339  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23340  * alt_write_word() functions.
23341  *
23342  * The struct declaration for register ALT_EMAC_GMAC_TXOVERSIZE_G.
23343  */
23344 struct ALT_EMAC_GMAC_TXOVERSIZE_G_s
23345 {
23346  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_TXOVERSIZE_G_CNT */
23347 };
23348 
23349 /* The typedef declaration for register ALT_EMAC_GMAC_TXOVERSIZE_G. */
23350 typedef volatile struct ALT_EMAC_GMAC_TXOVERSIZE_G_s ALT_EMAC_GMAC_TXOVERSIZE_G_t;
23351 #endif /* __ASSEMBLY__ */
23352 
23353 /* The reset value of the ALT_EMAC_GMAC_TXOVERSIZE_G register. */
23354 #define ALT_EMAC_GMAC_TXOVERSIZE_G_RESET 0x00000000
23355 /* The byte offset of the ALT_EMAC_GMAC_TXOVERSIZE_G register from the beginning of the component. */
23356 #define ALT_EMAC_GMAC_TXOVERSIZE_G_OFST 0x178
23357 /* The address of the ALT_EMAC_GMAC_TXOVERSIZE_G register. */
23358 #define ALT_EMAC_GMAC_TXOVERSIZE_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXOVERSIZE_G_OFST))
23359 
23360 /*
23361  * Register : gmacgrp_rxframecount_gb
23362  *
23363  * <b> Register 96 (Receive Frame Count for Good and Bad Frames) </b>
23364  *
23365  * This register maintains the number of received good and bad frames.
23366  *
23367  * Register Layout
23368  *
23369  * Bits | Access | Reset | Description
23370  * :-------|:-------|:------|:--------------------------------
23371  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT
23372  *
23373  */
23374 /*
23375  * Field : cnt
23376  *
23377  * This field indicates the number of received good and bad frames.
23378  *
23379  * Field Access Macros:
23380  *
23381  */
23382 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field. */
23383 #define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_LSB 0
23384 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field. */
23385 #define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_MSB 31
23386 /* The width in bits of the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field. */
23387 #define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_WIDTH 32
23388 /* The mask used to set the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field value. */
23389 #define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_SET_MSK 0xffffffff
23390 /* The mask used to clear the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field value. */
23391 #define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_CLR_MSK 0x00000000
23392 /* The reset value of the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field. */
23393 #define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_RESET 0x0
23394 /* Extracts the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT field value from a register. */
23395 #define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
23396 /* Produces a ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field value suitable for setting the register. */
23397 #define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
23398 
23399 #ifndef __ASSEMBLY__
23400 /*
23401  * WARNING: The C register and register group struct declarations are provided for
23402  * convenience and illustrative purposes. They should, however, be used with
23403  * caution as the C language standard provides no guarantees about the alignment or
23404  * atomicity of device memory accesses. The recommended practice for writing
23405  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23406  * alt_write_word() functions.
23407  *
23408  * The struct declaration for register ALT_EMAC_GMAC_RXFRMCOUNT_GB.
23409  */
23410 struct ALT_EMAC_GMAC_RXFRMCOUNT_GB_s
23411 {
23412  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT */
23413 };
23414 
23415 /* The typedef declaration for register ALT_EMAC_GMAC_RXFRMCOUNT_GB. */
23416 typedef volatile struct ALT_EMAC_GMAC_RXFRMCOUNT_GB_s ALT_EMAC_GMAC_RXFRMCOUNT_GB_t;
23417 #endif /* __ASSEMBLY__ */
23418 
23419 /* The reset value of the ALT_EMAC_GMAC_RXFRMCOUNT_GB register. */
23420 #define ALT_EMAC_GMAC_RXFRMCOUNT_GB_RESET 0x00000000
23421 /* The byte offset of the ALT_EMAC_GMAC_RXFRMCOUNT_GB register from the beginning of the component. */
23422 #define ALT_EMAC_GMAC_RXFRMCOUNT_GB_OFST 0x180
23423 /* The address of the ALT_EMAC_GMAC_RXFRMCOUNT_GB register. */
23424 #define ALT_EMAC_GMAC_RXFRMCOUNT_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXFRMCOUNT_GB_OFST))
23425 
23426 /*
23427  * Register : gmacgrp_rxoctetcount_gb
23428  *
23429  * <b> Register 97 (Receive Octet Count for Good and Bad Frames) </b>
23430  *
23431  * This register maintains the number of bytes received, exclusive of preamble, in
23432  * good and bad frames.
23433  *
23434  * Register Layout
23435  *
23436  * Bits | Access | Reset | Description
23437  * :-------|:-------|:------|:----------------------------------
23438  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT
23439  *
23440  */
23441 /*
23442  * Field : cnt
23443  *
23444  * This field indicates the number of bytes received, exclusive of preamble, in
23445  * good and bad frames.
23446  *
23447  * Field Access Macros:
23448  *
23449  */
23450 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field. */
23451 #define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_LSB 0
23452 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field. */
23453 #define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_MSB 31
23454 /* The width in bits of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field. */
23455 #define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_WIDTH 32
23456 /* The mask used to set the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field value. */
23457 #define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_SET_MSK 0xffffffff
23458 /* The mask used to clear the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field value. */
23459 #define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_CLR_MSK 0x00000000
23460 /* The reset value of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field. */
23461 #define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_RESET 0x0
23462 /* Extracts the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT field value from a register. */
23463 #define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
23464 /* Produces a ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field value suitable for setting the register. */
23465 #define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
23466 
23467 #ifndef __ASSEMBLY__
23468 /*
23469  * WARNING: The C register and register group struct declarations are provided for
23470  * convenience and illustrative purposes. They should, however, be used with
23471  * caution as the C language standard provides no guarantees about the alignment or
23472  * atomicity of device memory accesses. The recommended practice for writing
23473  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23474  * alt_write_word() functions.
23475  *
23476  * The struct declaration for register ALT_EMAC_GMAC_RXOCTETCOUNT_GB.
23477  */
23478 struct ALT_EMAC_GMAC_RXOCTETCOUNT_GB_s
23479 {
23480  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT */
23481 };
23482 
23483 /* The typedef declaration for register ALT_EMAC_GMAC_RXOCTETCOUNT_GB. */
23484 typedef volatile struct ALT_EMAC_GMAC_RXOCTETCOUNT_GB_s ALT_EMAC_GMAC_RXOCTETCOUNT_GB_t;
23485 #endif /* __ASSEMBLY__ */
23486 
23487 /* The reset value of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB register. */
23488 #define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_RESET 0x00000000
23489 /* The byte offset of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB register from the beginning of the component. */
23490 #define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_OFST 0x184
23491 /* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB register. */
23492 #define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXOCTETCOUNT_GB_OFST))
23493 
23494 /*
23495  * Register : gmacgrp_rxoctetcount_g
23496  *
23497  * <b> Register 98 (Receive Octet Count for Good Frames) </b>
23498  *
23499  * This register maintains the number of bytes received, exclusive of preamble,
23500  * only in good frames.
23501  *
23502  * Register Layout
23503  *
23504  * Bits | Access | Reset | Description
23505  * :-------|:-------|:------|:---------------------------------
23506  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT
23507  *
23508  */
23509 /*
23510  * Field : cnt
23511  *
23512  * This field indicates the number of bytes received, exclusive of preamble, only
23513  * in good frames.
23514  *
23515  * Field Access Macros:
23516  *
23517  */
23518 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field. */
23519 #define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_LSB 0
23520 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field. */
23521 #define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_MSB 31
23522 /* The width in bits of the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field. */
23523 #define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_WIDTH 32
23524 /* The mask used to set the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field value. */
23525 #define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_SET_MSK 0xffffffff
23526 /* The mask used to clear the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field value. */
23527 #define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_CLR_MSK 0x00000000
23528 /* The reset value of the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field. */
23529 #define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_RESET 0x0
23530 /* Extracts the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT field value from a register. */
23531 #define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
23532 /* Produces a ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field value suitable for setting the register. */
23533 #define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
23534 
23535 #ifndef __ASSEMBLY__
23536 /*
23537  * WARNING: The C register and register group struct declarations are provided for
23538  * convenience and illustrative purposes. They should, however, be used with
23539  * caution as the C language standard provides no guarantees about the alignment or
23540  * atomicity of device memory accesses. The recommended practice for writing
23541  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23542  * alt_write_word() functions.
23543  *
23544  * The struct declaration for register ALT_EMAC_GMAC_RXOCTETCOUNT_G.
23545  */
23546 struct ALT_EMAC_GMAC_RXOCTETCOUNT_G_s
23547 {
23548  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT */
23549 };
23550 
23551 /* The typedef declaration for register ALT_EMAC_GMAC_RXOCTETCOUNT_G. */
23552 typedef volatile struct ALT_EMAC_GMAC_RXOCTETCOUNT_G_s ALT_EMAC_GMAC_RXOCTETCOUNT_G_t;
23553 #endif /* __ASSEMBLY__ */
23554 
23555 /* The reset value of the ALT_EMAC_GMAC_RXOCTETCOUNT_G register. */
23556 #define ALT_EMAC_GMAC_RXOCTETCOUNT_G_RESET 0x00000000
23557 /* The byte offset of the ALT_EMAC_GMAC_RXOCTETCOUNT_G register from the beginning of the component. */
23558 #define ALT_EMAC_GMAC_RXOCTETCOUNT_G_OFST 0x188
23559 /* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_G register. */
23560 #define ALT_EMAC_GMAC_RXOCTETCOUNT_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXOCTETCOUNT_G_OFST))
23561 
23562 /*
23563  * Register : gmacgrp_rxbroadcastframes_g
23564  *
23565  * <b> Register 99 (Receive Frame Count for Good Broadcast Frames) </b>
23566  *
23567  * This register maintains the number of received good broadcast frames.
23568  *
23569  * Register Layout
23570  *
23571  * Bits | Access | Reset | Description
23572  * :-------|:-------|:------|:--------------------------------
23573  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT
23574  *
23575  */
23576 /*
23577  * Field : cnt
23578  *
23579  * This field indicates the number of received good broadcast frames.
23580  *
23581  * Field Access Macros:
23582  *
23583  */
23584 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field. */
23585 #define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_LSB 0
23586 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field. */
23587 #define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_MSB 31
23588 /* The width in bits of the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field. */
23589 #define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_WIDTH 32
23590 /* The mask used to set the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field value. */
23591 #define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_SET_MSK 0xffffffff
23592 /* The mask used to clear the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field value. */
23593 #define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_CLR_MSK 0x00000000
23594 /* The reset value of the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field. */
23595 #define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_RESET 0x0
23596 /* Extracts the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT field value from a register. */
23597 #define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
23598 /* Produces a ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field value suitable for setting the register. */
23599 #define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
23600 
23601 #ifndef __ASSEMBLY__
23602 /*
23603  * WARNING: The C register and register group struct declarations are provided for
23604  * convenience and illustrative purposes. They should, however, be used with
23605  * caution as the C language standard provides no guarantees about the alignment or
23606  * atomicity of device memory accesses. The recommended practice for writing
23607  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23608  * alt_write_word() functions.
23609  *
23610  * The struct declaration for register ALT_EMAC_GMAC_RXBCASTFRMS_G.
23611  */
23612 struct ALT_EMAC_GMAC_RXBCASTFRMS_G_s
23613 {
23614  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT */
23615 };
23616 
23617 /* The typedef declaration for register ALT_EMAC_GMAC_RXBCASTFRMS_G. */
23618 typedef volatile struct ALT_EMAC_GMAC_RXBCASTFRMS_G_s ALT_EMAC_GMAC_RXBCASTFRMS_G_t;
23619 #endif /* __ASSEMBLY__ */
23620 
23621 /* The reset value of the ALT_EMAC_GMAC_RXBCASTFRMS_G register. */
23622 #define ALT_EMAC_GMAC_RXBCASTFRMS_G_RESET 0x00000000
23623 /* The byte offset of the ALT_EMAC_GMAC_RXBCASTFRMS_G register from the beginning of the component. */
23624 #define ALT_EMAC_GMAC_RXBCASTFRMS_G_OFST 0x18c
23625 /* The address of the ALT_EMAC_GMAC_RXBCASTFRMS_G register. */
23626 #define ALT_EMAC_GMAC_RXBCASTFRMS_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXBCASTFRMS_G_OFST))
23627 
23628 /*
23629  * Register : gmacgrp_rxmulticastframes_g
23630  *
23631  * <b> Register 100 (Receive Frame Count for Good Multicast Frames) </b>
23632  *
23633  * This register maintains the number of received good multicast frames.
23634  *
23635  * Register Layout
23636  *
23637  * Bits | Access | Reset | Description
23638  * :-------|:-------|:------|:--------------------------------
23639  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT
23640  *
23641  */
23642 /*
23643  * Field : cnt
23644  *
23645  * This field indicates the number of received good multicast frames.
23646  *
23647  * Field Access Macros:
23648  *
23649  */
23650 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field. */
23651 #define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_LSB 0
23652 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field. */
23653 #define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_MSB 31
23654 /* The width in bits of the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field. */
23655 #define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_WIDTH 32
23656 /* The mask used to set the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field value. */
23657 #define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_SET_MSK 0xffffffff
23658 /* The mask used to clear the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field value. */
23659 #define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_CLR_MSK 0x00000000
23660 /* The reset value of the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field. */
23661 #define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_RESET 0x0
23662 /* Extracts the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT field value from a register. */
23663 #define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
23664 /* Produces a ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field value suitable for setting the register. */
23665 #define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
23666 
23667 #ifndef __ASSEMBLY__
23668 /*
23669  * WARNING: The C register and register group struct declarations are provided for
23670  * convenience and illustrative purposes. They should, however, be used with
23671  * caution as the C language standard provides no guarantees about the alignment or
23672  * atomicity of device memory accesses. The recommended practice for writing
23673  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23674  * alt_write_word() functions.
23675  *
23676  * The struct declaration for register ALT_EMAC_GMAC_RXMCASTFRMS_G.
23677  */
23678 struct ALT_EMAC_GMAC_RXMCASTFRMS_G_s
23679 {
23680  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT */
23681 };
23682 
23683 /* The typedef declaration for register ALT_EMAC_GMAC_RXMCASTFRMS_G. */
23684 typedef volatile struct ALT_EMAC_GMAC_RXMCASTFRMS_G_s ALT_EMAC_GMAC_RXMCASTFRMS_G_t;
23685 #endif /* __ASSEMBLY__ */
23686 
23687 /* The reset value of the ALT_EMAC_GMAC_RXMCASTFRMS_G register. */
23688 #define ALT_EMAC_GMAC_RXMCASTFRMS_G_RESET 0x00000000
23689 /* The byte offset of the ALT_EMAC_GMAC_RXMCASTFRMS_G register from the beginning of the component. */
23690 #define ALT_EMAC_GMAC_RXMCASTFRMS_G_OFST 0x190
23691 /* The address of the ALT_EMAC_GMAC_RXMCASTFRMS_G register. */
23692 #define ALT_EMAC_GMAC_RXMCASTFRMS_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXMCASTFRMS_G_OFST))
23693 
23694 /*
23695  * Register : gmacgrp_rxcrcerror
23696  *
23697  * <b> Register 101 (Receive Frame Count for CRC Error Frames) </b>
23698  *
23699  * This register maintains the number of frames received with CRC error.
23700  *
23701  * Register Layout
23702  *
23703  * Bits | Access | Reset | Description
23704  * :-------|:-------|:------|:-----------------------------
23705  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RXCRCERROR_CNT
23706  *
23707  */
23708 /*
23709  * Field : cnt
23710  *
23711  * This field indicates the number of frames received with CRC error.
23712  *
23713  * Field Access Macros:
23714  *
23715  */
23716 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXCRCERROR_CNT register field. */
23717 #define ALT_EMAC_GMAC_RXCRCERROR_CNT_LSB 0
23718 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXCRCERROR_CNT register field. */
23719 #define ALT_EMAC_GMAC_RXCRCERROR_CNT_MSB 31
23720 /* The width in bits of the ALT_EMAC_GMAC_RXCRCERROR_CNT register field. */
23721 #define ALT_EMAC_GMAC_RXCRCERROR_CNT_WIDTH 32
23722 /* The mask used to set the ALT_EMAC_GMAC_RXCRCERROR_CNT register field value. */
23723 #define ALT_EMAC_GMAC_RXCRCERROR_CNT_SET_MSK 0xffffffff
23724 /* The mask used to clear the ALT_EMAC_GMAC_RXCRCERROR_CNT register field value. */
23725 #define ALT_EMAC_GMAC_RXCRCERROR_CNT_CLR_MSK 0x00000000
23726 /* The reset value of the ALT_EMAC_GMAC_RXCRCERROR_CNT register field. */
23727 #define ALT_EMAC_GMAC_RXCRCERROR_CNT_RESET 0x0
23728 /* Extracts the ALT_EMAC_GMAC_RXCRCERROR_CNT field value from a register. */
23729 #define ALT_EMAC_GMAC_RXCRCERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
23730 /* Produces a ALT_EMAC_GMAC_RXCRCERROR_CNT register field value suitable for setting the register. */
23731 #define ALT_EMAC_GMAC_RXCRCERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)
23732 
23733 #ifndef __ASSEMBLY__
23734 /*
23735  * WARNING: The C register and register group struct declarations are provided for
23736  * convenience and illustrative purposes. They should, however, be used with
23737  * caution as the C language standard provides no guarantees about the alignment or
23738  * atomicity of device memory accesses. The recommended practice for writing
23739  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23740  * alt_write_word() functions.
23741  *
23742  * The struct declaration for register ALT_EMAC_GMAC_RXCRCERROR.
23743  */
23744 struct ALT_EMAC_GMAC_RXCRCERROR_s
23745 {
23746  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RXCRCERROR_CNT */
23747 };
23748 
23749 /* The typedef declaration for register ALT_EMAC_GMAC_RXCRCERROR. */
23750 typedef volatile struct ALT_EMAC_GMAC_RXCRCERROR_s ALT_EMAC_GMAC_RXCRCERROR_t;
23751 #endif /* __ASSEMBLY__ */
23752 
23753 /* The reset value of the ALT_EMAC_GMAC_RXCRCERROR register. */
23754 #define ALT_EMAC_GMAC_RXCRCERROR_RESET 0x00000000
23755 /* The byte offset of the ALT_EMAC_GMAC_RXCRCERROR register from the beginning of the component. */
23756 #define ALT_EMAC_GMAC_RXCRCERROR_OFST 0x194
23757 /* The address of the ALT_EMAC_GMAC_RXCRCERROR register. */
23758 #define ALT_EMAC_GMAC_RXCRCERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXCRCERROR_OFST))
23759 
23760 /*
23761  * Register : gmacgrp_rxalignmenterror
23762  *
23763  * <b> Register 102 (Receive Frame Count for Alignment Error Frames) </b>
23764  *
23765  * This register maintains the number of frames received with alignment (dribble)
23766  * error. This field is valid only in the 10 or 100 Mbps mode.
23767  *
23768  * Register Layout
23769  *
23770  * Bits | Access | Reset | Description
23771  * :-------|:-------|:------|:-----------------------------------
23772  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT
23773  *
23774  */
23775 /*
23776  * Field : cnt
23777  *
23778  * This field indicates the number of frames received with alignment (dribble)
23779  * error. This field is valid only in the 10 or 100 Mbps mode.
23780  *
23781  * Field Access Macros:
23782  *
23783  */
23784 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field. */
23785 #define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_LSB 0
23786 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field. */
23787 #define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_MSB 31
23788 /* The width in bits of the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field. */
23789 #define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_WIDTH 32
23790 /* The mask used to set the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field value. */
23791 #define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_SET_MSK 0xffffffff
23792 /* The mask used to clear the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field value. */
23793 #define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_CLR_MSK 0x00000000
23794 /* The reset value of the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field. */
23795 #define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_RESET 0x0
23796 /* Extracts the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT field value from a register. */
23797 #define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
23798 /* Produces a ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field value suitable for setting the register. */
23799 #define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)
23800 
23801 #ifndef __ASSEMBLY__
23802 /*
23803  * WARNING: The C register and register group struct declarations are provided for
23804  * convenience and illustrative purposes. They should, however, be used with
23805  * caution as the C language standard provides no guarantees about the alignment or
23806  * atomicity of device memory accesses. The recommended practice for writing
23807  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23808  * alt_write_word() functions.
23809  *
23810  * The struct declaration for register ALT_EMAC_GMAC_RXALIGNMENTERROR.
23811  */
23812 struct ALT_EMAC_GMAC_RXALIGNMENTERROR_s
23813 {
23814  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT */
23815 };
23816 
23817 /* The typedef declaration for register ALT_EMAC_GMAC_RXALIGNMENTERROR. */
23818 typedef volatile struct ALT_EMAC_GMAC_RXALIGNMENTERROR_s ALT_EMAC_GMAC_RXALIGNMENTERROR_t;
23819 #endif /* __ASSEMBLY__ */
23820 
23821 /* The reset value of the ALT_EMAC_GMAC_RXALIGNMENTERROR register. */
23822 #define ALT_EMAC_GMAC_RXALIGNMENTERROR_RESET 0x00000000
23823 /* The byte offset of the ALT_EMAC_GMAC_RXALIGNMENTERROR register from the beginning of the component. */
23824 #define ALT_EMAC_GMAC_RXALIGNMENTERROR_OFST 0x198
23825 /* The address of the ALT_EMAC_GMAC_RXALIGNMENTERROR register. */
23826 #define ALT_EMAC_GMAC_RXALIGNMENTERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXALIGNMENTERROR_OFST))
23827 
23828 /*
23829  * Register : gmacgrp_rxrunterror
23830  *
23831  * <b> Register 103 (Receive Frame Count for Runt Error Frames) </b>
23832  *
23833  * This register maintains the number of frames received with runt error(<64 bytes
23834  * and CRC error).
23835  *
23836  * Register Layout
23837  *
23838  * Bits | Access | Reset | Description
23839  * :-------|:-------|:------|:------------------------------
23840  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RXRUNTERROR_CNT
23841  *
23842  */
23843 /*
23844  * Field : cnt
23845  *
23846  * This field indicates the number of frames received with runt error(<64 bytes and
23847  * CRC error).
23848  *
23849  * Field Access Macros:
23850  *
23851  */
23852 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field. */
23853 #define ALT_EMAC_GMAC_RXRUNTERROR_CNT_LSB 0
23854 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field. */
23855 #define ALT_EMAC_GMAC_RXRUNTERROR_CNT_MSB 31
23856 /* The width in bits of the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field. */
23857 #define ALT_EMAC_GMAC_RXRUNTERROR_CNT_WIDTH 32
23858 /* The mask used to set the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field value. */
23859 #define ALT_EMAC_GMAC_RXRUNTERROR_CNT_SET_MSK 0xffffffff
23860 /* The mask used to clear the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field value. */
23861 #define ALT_EMAC_GMAC_RXRUNTERROR_CNT_CLR_MSK 0x00000000
23862 /* The reset value of the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field. */
23863 #define ALT_EMAC_GMAC_RXRUNTERROR_CNT_RESET 0x0
23864 /* Extracts the ALT_EMAC_GMAC_RXRUNTERROR_CNT field value from a register. */
23865 #define ALT_EMAC_GMAC_RXRUNTERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
23866 /* Produces a ALT_EMAC_GMAC_RXRUNTERROR_CNT register field value suitable for setting the register. */
23867 #define ALT_EMAC_GMAC_RXRUNTERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)
23868 
23869 #ifndef __ASSEMBLY__
23870 /*
23871  * WARNING: The C register and register group struct declarations are provided for
23872  * convenience and illustrative purposes. They should, however, be used with
23873  * caution as the C language standard provides no guarantees about the alignment or
23874  * atomicity of device memory accesses. The recommended practice for writing
23875  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23876  * alt_write_word() functions.
23877  *
23878  * The struct declaration for register ALT_EMAC_GMAC_RXRUNTERROR.
23879  */
23880 struct ALT_EMAC_GMAC_RXRUNTERROR_s
23881 {
23882  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RXRUNTERROR_CNT */
23883 };
23884 
23885 /* The typedef declaration for register ALT_EMAC_GMAC_RXRUNTERROR. */
23886 typedef volatile struct ALT_EMAC_GMAC_RXRUNTERROR_s ALT_EMAC_GMAC_RXRUNTERROR_t;
23887 #endif /* __ASSEMBLY__ */
23888 
23889 /* The reset value of the ALT_EMAC_GMAC_RXRUNTERROR register. */
23890 #define ALT_EMAC_GMAC_RXRUNTERROR_RESET 0x00000000
23891 /* The byte offset of the ALT_EMAC_GMAC_RXRUNTERROR register from the beginning of the component. */
23892 #define ALT_EMAC_GMAC_RXRUNTERROR_OFST 0x19c
23893 /* The address of the ALT_EMAC_GMAC_RXRUNTERROR register. */
23894 #define ALT_EMAC_GMAC_RXRUNTERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXRUNTERROR_OFST))
23895 
23896 /*
23897  * Register : gmacgrp_rxjabbererror
23898  *
23899  * <b> Register 104 (Receive Frame Count for Jabber Error Frames) </b>
23900  *
23901  * This register maintains the number of giant frames received with length
23902  * (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with
23903  * CRC error. If Jumbo Frame mode is enabled, then frames of length greater than
23904  * 9,018 bytes (9,022 for VLAN tagged) are considered as giant frames.
23905  *
23906  * Register Layout
23907  *
23908  * Bits | Access | Reset | Description
23909  * :-------|:-------|:------|:--------------------------------
23910  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RXJABBERERROR_CNT
23911  *
23912  */
23913 /*
23914  * Field : cnt
23915  *
23916  * This field indicates the number of giant frames received with length (including
23917  * CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC error.
23918  * If Jumbo Frame mode is enabled, then frames of length greater than 9,018 bytes
23919  * (9,022 for VLAN tagged) are considered as giant frames.
23920  *
23921  * Field Access Macros:
23922  *
23923  */
23924 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field. */
23925 #define ALT_EMAC_GMAC_RXJABBERERROR_CNT_LSB 0
23926 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field. */
23927 #define ALT_EMAC_GMAC_RXJABBERERROR_CNT_MSB 31
23928 /* The width in bits of the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field. */
23929 #define ALT_EMAC_GMAC_RXJABBERERROR_CNT_WIDTH 32
23930 /* The mask used to set the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field value. */
23931 #define ALT_EMAC_GMAC_RXJABBERERROR_CNT_SET_MSK 0xffffffff
23932 /* The mask used to clear the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field value. */
23933 #define ALT_EMAC_GMAC_RXJABBERERROR_CNT_CLR_MSK 0x00000000
23934 /* The reset value of the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field. */
23935 #define ALT_EMAC_GMAC_RXJABBERERROR_CNT_RESET 0x0
23936 /* Extracts the ALT_EMAC_GMAC_RXJABBERERROR_CNT field value from a register. */
23937 #define ALT_EMAC_GMAC_RXJABBERERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
23938 /* Produces a ALT_EMAC_GMAC_RXJABBERERROR_CNT register field value suitable for setting the register. */
23939 #define ALT_EMAC_GMAC_RXJABBERERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)
23940 
23941 #ifndef __ASSEMBLY__
23942 /*
23943  * WARNING: The C register and register group struct declarations are provided for
23944  * convenience and illustrative purposes. They should, however, be used with
23945  * caution as the C language standard provides no guarantees about the alignment or
23946  * atomicity of device memory accesses. The recommended practice for writing
23947  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23948  * alt_write_word() functions.
23949  *
23950  * The struct declaration for register ALT_EMAC_GMAC_RXJABBERERROR.
23951  */
23952 struct ALT_EMAC_GMAC_RXJABBERERROR_s
23953 {
23954  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RXJABBERERROR_CNT */
23955 };
23956 
23957 /* The typedef declaration for register ALT_EMAC_GMAC_RXJABBERERROR. */
23958 typedef volatile struct ALT_EMAC_GMAC_RXJABBERERROR_s ALT_EMAC_GMAC_RXJABBERERROR_t;
23959 #endif /* __ASSEMBLY__ */
23960 
23961 /* The reset value of the ALT_EMAC_GMAC_RXJABBERERROR register. */
23962 #define ALT_EMAC_GMAC_RXJABBERERROR_RESET 0x00000000
23963 /* The byte offset of the ALT_EMAC_GMAC_RXJABBERERROR register from the beginning of the component. */
23964 #define ALT_EMAC_GMAC_RXJABBERERROR_OFST 0x1a0
23965 /* The address of the ALT_EMAC_GMAC_RXJABBERERROR register. */
23966 #define ALT_EMAC_GMAC_RXJABBERERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXJABBERERROR_OFST))
23967 
23968 /*
23969  * Register : gmacgrp_rxundersize_g
23970  *
23971  * <b> Register 105 (Receive Frame Count for Undersize Frames) </b>
23972  *
23973  * This register maintains the number of frames received with length less than 64
23974  * bytes and without errors.
23975  *
23976  * Register Layout
23977  *
23978  * Bits | Access | Reset | Description
23979  * :-------|:-------|:------|:--------------------------------
23980  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT
23981  *
23982  */
23983 /*
23984  * Field : cnt
23985  *
23986  * This field indicates the number of frames received with length less than 64
23987  * bytes and without errors.
23988  *
23989  * Field Access Macros:
23990  *
23991  */
23992 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field. */
23993 #define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_LSB 0
23994 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field. */
23995 #define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_MSB 31
23996 /* The width in bits of the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field. */
23997 #define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_WIDTH 32
23998 /* The mask used to set the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field value. */
23999 #define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_SET_MSK 0xffffffff
24000 /* The mask used to clear the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field value. */
24001 #define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_CLR_MSK 0x00000000
24002 /* The reset value of the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field. */
24003 #define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_RESET 0x0
24004 /* Extracts the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT field value from a register. */
24005 #define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
24006 /* Produces a ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field value suitable for setting the register. */
24007 #define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
24008 
24009 #ifndef __ASSEMBLY__
24010 /*
24011  * WARNING: The C register and register group struct declarations are provided for
24012  * convenience and illustrative purposes. They should, however, be used with
24013  * caution as the C language standard provides no guarantees about the alignment or
24014  * atomicity of device memory accesses. The recommended practice for writing
24015  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24016  * alt_write_word() functions.
24017  *
24018  * The struct declaration for register ALT_EMAC_GMAC_RXUNDERSIZE_G.
24019  */
24020 struct ALT_EMAC_GMAC_RXUNDERSIZE_G_s
24021 {
24022  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT */
24023 };
24024 
24025 /* The typedef declaration for register ALT_EMAC_GMAC_RXUNDERSIZE_G. */
24026 typedef volatile struct ALT_EMAC_GMAC_RXUNDERSIZE_G_s ALT_EMAC_GMAC_RXUNDERSIZE_G_t;
24027 #endif /* __ASSEMBLY__ */
24028 
24029 /* The reset value of the ALT_EMAC_GMAC_RXUNDERSIZE_G register. */
24030 #define ALT_EMAC_GMAC_RXUNDERSIZE_G_RESET 0x00000000
24031 /* The byte offset of the ALT_EMAC_GMAC_RXUNDERSIZE_G register from the beginning of the component. */
24032 #define ALT_EMAC_GMAC_RXUNDERSIZE_G_OFST 0x1a4
24033 /* The address of the ALT_EMAC_GMAC_RXUNDERSIZE_G register. */
24034 #define ALT_EMAC_GMAC_RXUNDERSIZE_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUNDERSIZE_G_OFST))
24035 
24036 /*
24037  * Register : gmacgrp_rxoversize_g
24038  *
24039  * <b> Register 106 (Receive Frame Count for Oversize Frames) </b>
24040  *
24041  * This register maintains the number of frames received with length greater than
24042  * the maxsize (1,518 or 1,522 for VLAN tagged frames) and without errors.
24043  *
24044  * Register Layout
24045  *
24046  * Bits | Access | Reset | Description
24047  * :-------|:-------|:------|:-------------------------------
24048  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RXOVERSIZE_G_CNT
24049  *
24050  */
24051 /*
24052  * Field : cnt
24053  *
24054  * This field indicates the number of frames received without errors, with length
24055  * greater than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 bytes if
24056  * enabled in bit 27 of Register 0 (MAC Configuration Register)).
24057  *
24058  * Field Access Macros:
24059  *
24060  */
24061 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field. */
24062 #define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_LSB 0
24063 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field. */
24064 #define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_MSB 31
24065 /* The width in bits of the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field. */
24066 #define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_WIDTH 32
24067 /* The mask used to set the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field value. */
24068 #define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_SET_MSK 0xffffffff
24069 /* The mask used to clear the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field value. */
24070 #define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_CLR_MSK 0x00000000
24071 /* The reset value of the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field. */
24072 #define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_RESET 0x0
24073 /* Extracts the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT field value from a register. */
24074 #define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
24075 /* Produces a ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field value suitable for setting the register. */
24076 #define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
24077 
24078 #ifndef __ASSEMBLY__
24079 /*
24080  * WARNING: The C register and register group struct declarations are provided for
24081  * convenience and illustrative purposes. They should, however, be used with
24082  * caution as the C language standard provides no guarantees about the alignment or
24083  * atomicity of device memory accesses. The recommended practice for writing
24084  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24085  * alt_write_word() functions.
24086  *
24087  * The struct declaration for register ALT_EMAC_GMAC_RXOVERSIZE_G.
24088  */
24089 struct ALT_EMAC_GMAC_RXOVERSIZE_G_s
24090 {
24091  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RXOVERSIZE_G_CNT */
24092 };
24093 
24094 /* The typedef declaration for register ALT_EMAC_GMAC_RXOVERSIZE_G. */
24095 typedef volatile struct ALT_EMAC_GMAC_RXOVERSIZE_G_s ALT_EMAC_GMAC_RXOVERSIZE_G_t;
24096 #endif /* __ASSEMBLY__ */
24097 
24098 /* The reset value of the ALT_EMAC_GMAC_RXOVERSIZE_G register. */
24099 #define ALT_EMAC_GMAC_RXOVERSIZE_G_RESET 0x00000000
24100 /* The byte offset of the ALT_EMAC_GMAC_RXOVERSIZE_G register from the beginning of the component. */
24101 #define ALT_EMAC_GMAC_RXOVERSIZE_G_OFST 0x1a8
24102 /* The address of the ALT_EMAC_GMAC_RXOVERSIZE_G register. */
24103 #define ALT_EMAC_GMAC_RXOVERSIZE_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXOVERSIZE_G_OFST))
24104 
24105 /*
24106  * Register : gmacgrp_rx64octets_gb
24107  *
24108  * <b> Register 107 (Receive Frame Count for Good and Bad 64 Byte Frames) </b>
24109  *
24110  * This register maintains the number of received good and bad frames with length
24111  * 64 bytes, exclusive of preamble.
24112  *
24113  * Register Layout
24114  *
24115  * Bits | Access | Reset | Description
24116  * :-------|:-------|:------|:--------------------------------
24117  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RX64OCTETS_GB_CNT
24118  *
24119  */
24120 /*
24121  * Field : cnt
24122  *
24123  * This field indicates the number of received good and bad frames with length 64
24124  * bytes, exclusive of preamble.
24125  *
24126  * Field Access Macros:
24127  *
24128  */
24129 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field. */
24130 #define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_LSB 0
24131 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field. */
24132 #define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_MSB 31
24133 /* The width in bits of the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field. */
24134 #define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_WIDTH 32
24135 /* The mask used to set the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field value. */
24136 #define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_SET_MSK 0xffffffff
24137 /* The mask used to clear the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field value. */
24138 #define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_CLR_MSK 0x00000000
24139 /* The reset value of the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field. */
24140 #define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_RESET 0x0
24141 /* Extracts the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT field value from a register. */
24142 #define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
24143 /* Produces a ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field value suitable for setting the register. */
24144 #define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
24145 
24146 #ifndef __ASSEMBLY__
24147 /*
24148  * WARNING: The C register and register group struct declarations are provided for
24149  * convenience and illustrative purposes. They should, however, be used with
24150  * caution as the C language standard provides no guarantees about the alignment or
24151  * atomicity of device memory accesses. The recommended practice for writing
24152  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24153  * alt_write_word() functions.
24154  *
24155  * The struct declaration for register ALT_EMAC_GMAC_RX64OCTETS_GB.
24156  */
24157 struct ALT_EMAC_GMAC_RX64OCTETS_GB_s
24158 {
24159  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RX64OCTETS_GB_CNT */
24160 };
24161 
24162 /* The typedef declaration for register ALT_EMAC_GMAC_RX64OCTETS_GB. */
24163 typedef volatile struct ALT_EMAC_GMAC_RX64OCTETS_GB_s ALT_EMAC_GMAC_RX64OCTETS_GB_t;
24164 #endif /* __ASSEMBLY__ */
24165 
24166 /* The reset value of the ALT_EMAC_GMAC_RX64OCTETS_GB register. */
24167 #define ALT_EMAC_GMAC_RX64OCTETS_GB_RESET 0x00000000
24168 /* The byte offset of the ALT_EMAC_GMAC_RX64OCTETS_GB register from the beginning of the component. */
24169 #define ALT_EMAC_GMAC_RX64OCTETS_GB_OFST 0x1ac
24170 /* The address of the ALT_EMAC_GMAC_RX64OCTETS_GB register. */
24171 #define ALT_EMAC_GMAC_RX64OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX64OCTETS_GB_OFST))
24172 
24173 /*
24174  * Register : gmacgrp_rx65to127octets_gb
24175  *
24176  * <b> Register 108 (Receive Frame Count for Good and Bad 65 to 127 Bytes Frames)
24177  * </b>
24178  *
24179  * This register maintains the number of received good and bad frames received with
24180  * length between 65 and 127 (inclusive) bytes, exclusive of preamble.
24181  *
24182  * Register Layout
24183  *
24184  * Bits | Access | Reset | Description
24185  * :-------|:-------|:------|:-------------------------------------
24186  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT
24187  *
24188  */
24189 /*
24190  * Field : cnt
24191  *
24192  * This field indicates the number of received good and bad frames received with
24193  * length between 65 and 127 (inclusive) bytes, exclusive of preamble.
24194  *
24195  * Field Access Macros:
24196  *
24197  */
24198 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field. */
24199 #define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_LSB 0
24200 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field. */
24201 #define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_MSB 31
24202 /* The width in bits of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field. */
24203 #define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_WIDTH 32
24204 /* The mask used to set the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field value. */
24205 #define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_SET_MSK 0xffffffff
24206 /* The mask used to clear the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field value. */
24207 #define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_CLR_MSK 0x00000000
24208 /* The reset value of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field. */
24209 #define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_RESET 0x0
24210 /* Extracts the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT field value from a register. */
24211 #define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
24212 /* Produces a ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field value suitable for setting the register. */
24213 #define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
24214 
24215 #ifndef __ASSEMBLY__
24216 /*
24217  * WARNING: The C register and register group struct declarations are provided for
24218  * convenience and illustrative purposes. They should, however, be used with
24219  * caution as the C language standard provides no guarantees about the alignment or
24220  * atomicity of device memory accesses. The recommended practice for writing
24221  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24222  * alt_write_word() functions.
24223  *
24224  * The struct declaration for register ALT_EMAC_GMAC_RX65TO127OCTETS_GB.
24225  */
24226 struct ALT_EMAC_GMAC_RX65TO127OCTETS_GB_s
24227 {
24228  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT */
24229 };
24230 
24231 /* The typedef declaration for register ALT_EMAC_GMAC_RX65TO127OCTETS_GB. */
24232 typedef volatile struct ALT_EMAC_GMAC_RX65TO127OCTETS_GB_s ALT_EMAC_GMAC_RX65TO127OCTETS_GB_t;
24233 #endif /* __ASSEMBLY__ */
24234 
24235 /* The reset value of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB register. */
24236 #define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_RESET 0x00000000
24237 /* The byte offset of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB register from the beginning of the component. */
24238 #define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_OFST 0x1b0
24239 /* The address of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB register. */
24240 #define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX65TO127OCTETS_GB_OFST))
24241 
24242 /*
24243  * Register : gmacgrp_rx128to255octets_gb
24244  *
24245  * <b> Register 109 (Receive Frame Count for Good and Bad 128 to 255 Bytes Frames)
24246  * </b>
24247  *
24248  * This register maintains the number of received good and bad frames with length
24249  * between 128 and 255 (inclusive) bytes, exclusive of preamble.
24250  *
24251  * Register Layout
24252  *
24253  * Bits | Access | Reset | Description
24254  * :-------|:-------|:------|:--------------------------------------
24255  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT
24256  *
24257  */
24258 /*
24259  * Field : cnt
24260  *
24261  * This field indicates the number of received good and bad frames with length
24262  * between 128 and 255 (inclusive) bytes, exclusive of preamble.
24263  *
24264  * Field Access Macros:
24265  *
24266  */
24267 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field. */
24268 #define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_LSB 0
24269 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field. */
24270 #define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_MSB 31
24271 /* The width in bits of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field. */
24272 #define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_WIDTH 32
24273 /* The mask used to set the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field value. */
24274 #define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_SET_MSK 0xffffffff
24275 /* The mask used to clear the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field value. */
24276 #define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_CLR_MSK 0x00000000
24277 /* The reset value of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field. */
24278 #define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_RESET 0x0
24279 /* Extracts the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT field value from a register. */
24280 #define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
24281 /* Produces a ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field value suitable for setting the register. */
24282 #define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
24283 
24284 #ifndef __ASSEMBLY__
24285 /*
24286  * WARNING: The C register and register group struct declarations are provided for
24287  * convenience and illustrative purposes. They should, however, be used with
24288  * caution as the C language standard provides no guarantees about the alignment or
24289  * atomicity of device memory accesses. The recommended practice for writing
24290  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24291  * alt_write_word() functions.
24292  *
24293  * The struct declaration for register ALT_EMAC_GMAC_RX128TO255OCTETS_GB.
24294  */
24295 struct ALT_EMAC_GMAC_RX128TO255OCTETS_GB_s
24296 {
24297  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT */
24298 };
24299 
24300 /* The typedef declaration for register ALT_EMAC_GMAC_RX128TO255OCTETS_GB. */
24301 typedef volatile struct ALT_EMAC_GMAC_RX128TO255OCTETS_GB_s ALT_EMAC_GMAC_RX128TO255OCTETS_GB_t;
24302 #endif /* __ASSEMBLY__ */
24303 
24304 /* The reset value of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB register. */
24305 #define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_RESET 0x00000000
24306 /* The byte offset of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB register from the beginning of the component. */
24307 #define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_OFST 0x1b4
24308 /* The address of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB register. */
24309 #define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX128TO255OCTETS_GB_OFST))
24310 
24311 /*
24312  * Register : gmacgrp_rx256to511octets_gb
24313  *
24314  * <b> Register 110 (Receive Frame Count for Good and Bad 256 to 511 Bytes Frames)
24315  * </b>
24316  *
24317  * This register maintains the number of received good and bad frames with length
24318  * between 256 and 511 (inclusive) bytes, exclusive of preamble.
24319  *
24320  * Register Layout
24321  *
24322  * Bits | Access | Reset | Description
24323  * :-------|:-------|:------|:--------------------------------------
24324  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT
24325  *
24326  */
24327 /*
24328  * Field : cnt
24329  *
24330  * This field indicates the number of received good and bad frames with length
24331  * between 256 and 511 (inclusive) bytes, exclusive of preamble.
24332  *
24333  * Field Access Macros:
24334  *
24335  */
24336 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field. */
24337 #define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_LSB 0
24338 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field. */
24339 #define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_MSB 31
24340 /* The width in bits of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field. */
24341 #define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_WIDTH 32
24342 /* The mask used to set the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field value. */
24343 #define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_SET_MSK 0xffffffff
24344 /* The mask used to clear the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field value. */
24345 #define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_CLR_MSK 0x00000000
24346 /* The reset value of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field. */
24347 #define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_RESET 0x0
24348 /* Extracts the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT field value from a register. */
24349 #define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
24350 /* Produces a ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field value suitable for setting the register. */
24351 #define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
24352 
24353 #ifndef __ASSEMBLY__
24354 /*
24355  * WARNING: The C register and register group struct declarations are provided for
24356  * convenience and illustrative purposes. They should, however, be used with
24357  * caution as the C language standard provides no guarantees about the alignment or
24358  * atomicity of device memory accesses. The recommended practice for writing
24359  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24360  * alt_write_word() functions.
24361  *
24362  * The struct declaration for register ALT_EMAC_GMAC_RX256TO511OCTETS_GB.
24363  */
24364 struct ALT_EMAC_GMAC_RX256TO511OCTETS_GB_s
24365 {
24366  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT */
24367 };
24368 
24369 /* The typedef declaration for register ALT_EMAC_GMAC_RX256TO511OCTETS_GB. */
24370 typedef volatile struct ALT_EMAC_GMAC_RX256TO511OCTETS_GB_s ALT_EMAC_GMAC_RX256TO511OCTETS_GB_t;
24371 #endif /* __ASSEMBLY__ */
24372 
24373 /* The reset value of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB register. */
24374 #define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_RESET 0x00000000
24375 /* The byte offset of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB register from the beginning of the component. */
24376 #define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_OFST 0x1b8
24377 /* The address of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB register. */
24378 #define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX256TO511OCTETS_GB_OFST))
24379 
24380 /*
24381  * Register : gmacgrp_rx512to1023octets_gb
24382  *
24383  * <b> Register 111 (Receive Frame Count for Good and Bad 512 to 1,023 Bytes
24384  * Frames) </b>
24385  *
24386  * This register maintains the number of received good and bad frames with length
24387  * between 512 and 1,023 (inclusive) bytes, exclusive of preamble.
24388  *
24389  * Register Layout
24390  *
24391  * Bits | Access | Reset | Description
24392  * :-------|:-------|:------|:---------------------------------------
24393  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT
24394  *
24395  */
24396 /*
24397  * Field : cnt
24398  *
24399  * This field indicates the number of received good and bad frames with length
24400  * between 512 and 1,023 (inclusive) bytes, exclusive of preamble.
24401  *
24402  * Field Access Macros:
24403  *
24404  */
24405 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field. */
24406 #define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_LSB 0
24407 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field. */
24408 #define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_MSB 31
24409 /* The width in bits of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field. */
24410 #define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_WIDTH 32
24411 /* The mask used to set the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field value. */
24412 #define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_SET_MSK 0xffffffff
24413 /* The mask used to clear the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field value. */
24414 #define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_CLR_MSK 0x00000000
24415 /* The reset value of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field. */
24416 #define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_RESET 0x0
24417 /* Extracts the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT field value from a register. */
24418 #define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
24419 /* Produces a ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field value suitable for setting the register. */
24420 #define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
24421 
24422 #ifndef __ASSEMBLY__
24423 /*
24424  * WARNING: The C register and register group struct declarations are provided for
24425  * convenience and illustrative purposes. They should, however, be used with
24426  * caution as the C language standard provides no guarantees about the alignment or
24427  * atomicity of device memory accesses. The recommended practice for writing
24428  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24429  * alt_write_word() functions.
24430  *
24431  * The struct declaration for register ALT_EMAC_GMAC_RX512TO1023OCTETS_GB.
24432  */
24433 struct ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_s
24434 {
24435  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT */
24436 };
24437 
24438 /* The typedef declaration for register ALT_EMAC_GMAC_RX512TO1023OCTETS_GB. */
24439 typedef volatile struct ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_s ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_t;
24440 #endif /* __ASSEMBLY__ */
24441 
24442 /* The reset value of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB register. */
24443 #define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_RESET 0x00000000
24444 /* The byte offset of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB register from the beginning of the component. */
24445 #define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_OFST 0x1bc
24446 /* The address of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB register. */
24447 #define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_OFST))
24448 
24449 /*
24450  * Register : gmacgrp_rx1024tomaxoctets_gb
24451  *
24452  * <b> Register 112 (Receive Frame Count for Good and Bad 1,024 to Maxsize Bytes
24453  * Frames) </b>
24454  *
24455  * This register maintains the number of received good and bad frames with length
24456  * between 1,024 and maxsize (inclusive) bytes, exclusive of preamble.
24457  *
24458  * Register Layout
24459  *
24460  * Bits | Access | Reset | Description
24461  * :-------|:-------|:------|:---------------------------------------
24462  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT
24463  *
24464  */
24465 /*
24466  * Field : cnt
24467  *
24468  * This field indicates the number of received good and bad frames with length
24469  * between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried
24470  * frames.
24471  *
24472  * Field Access Macros:
24473  *
24474  */
24475 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field. */
24476 #define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_LSB 0
24477 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field. */
24478 #define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_MSB 31
24479 /* The width in bits of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field. */
24480 #define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_WIDTH 32
24481 /* The mask used to set the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field value. */
24482 #define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_SET_MSK 0xffffffff
24483 /* The mask used to clear the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field value. */
24484 #define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_CLR_MSK 0x00000000
24485 /* The reset value of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field. */
24486 #define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_RESET 0x0
24487 /* Extracts the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT field value from a register. */
24488 #define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
24489 /* Produces a ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field value suitable for setting the register. */
24490 #define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
24491 
24492 #ifndef __ASSEMBLY__
24493 /*
24494  * WARNING: The C register and register group struct declarations are provided for
24495  * convenience and illustrative purposes. They should, however, be used with
24496  * caution as the C language standard provides no guarantees about the alignment or
24497  * atomicity of device memory accesses. The recommended practice for writing
24498  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24499  * alt_write_word() functions.
24500  *
24501  * The struct declaration for register ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB.
24502  */
24503 struct ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_s
24504 {
24505  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT */
24506 };
24507 
24508 /* The typedef declaration for register ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB. */
24509 typedef volatile struct ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_s ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_t;
24510 #endif /* __ASSEMBLY__ */
24511 
24512 /* The reset value of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB register. */
24513 #define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_RESET 0x00000000
24514 /* The byte offset of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB register from the beginning of the component. */
24515 #define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_OFST 0x1c0
24516 /* The address of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB register. */
24517 #define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_OFST))
24518 
24519 /*
24520  * Register : gmacgrp_rxunicastframes_g
24521  *
24522  * <b> Register 113 (Receive Frame Count for Good Unicast Frames) </b>
24523  *
24524  * This register maintains the number of received good unicast frames.
24525  *
24526  * Register Layout
24527  *
24528  * Bits | Access | Reset | Description
24529  * :-------|:-------|:------|:----------------------------------
24530  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT
24531  *
24532  */
24533 /*
24534  * Field : cnt
24535  *
24536  * This field indicates the number of received good unicast frames.
24537  *
24538  * Field Access Macros:
24539  *
24540  */
24541 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field. */
24542 #define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_LSB 0
24543 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field. */
24544 #define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_MSB 31
24545 /* The width in bits of the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field. */
24546 #define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_WIDTH 32
24547 /* The mask used to set the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field value. */
24548 #define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_SET_MSK 0xffffffff
24549 /* The mask used to clear the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field value. */
24550 #define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_CLR_MSK 0x00000000
24551 /* The reset value of the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field. */
24552 #define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_RESET 0x0
24553 /* Extracts the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT field value from a register. */
24554 #define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
24555 /* Produces a ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field value suitable for setting the register. */
24556 #define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
24557 
24558 #ifndef __ASSEMBLY__
24559 /*
24560  * WARNING: The C register and register group struct declarations are provided for
24561  * convenience and illustrative purposes. They should, however, be used with
24562  * caution as the C language standard provides no guarantees about the alignment or
24563  * atomicity of device memory accesses. The recommended practice for writing
24564  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24565  * alt_write_word() functions.
24566  *
24567  * The struct declaration for register ALT_EMAC_GMAC_RXUNICASTFRMS_G.
24568  */
24569 struct ALT_EMAC_GMAC_RXUNICASTFRMS_G_s
24570 {
24571  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT */
24572 };
24573 
24574 /* The typedef declaration for register ALT_EMAC_GMAC_RXUNICASTFRMS_G. */
24575 typedef volatile struct ALT_EMAC_GMAC_RXUNICASTFRMS_G_s ALT_EMAC_GMAC_RXUNICASTFRMS_G_t;
24576 #endif /* __ASSEMBLY__ */
24577 
24578 /* The reset value of the ALT_EMAC_GMAC_RXUNICASTFRMS_G register. */
24579 #define ALT_EMAC_GMAC_RXUNICASTFRMS_G_RESET 0x00000000
24580 /* The byte offset of the ALT_EMAC_GMAC_RXUNICASTFRMS_G register from the beginning of the component. */
24581 #define ALT_EMAC_GMAC_RXUNICASTFRMS_G_OFST 0x1c4
24582 /* The address of the ALT_EMAC_GMAC_RXUNICASTFRMS_G register. */
24583 #define ALT_EMAC_GMAC_RXUNICASTFRMS_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUNICASTFRMS_G_OFST))
24584 
24585 /*
24586  * Register : gmacgrp_rxlengtherror
24587  *
24588  * <b> Register 114 (Receive Frame Count for Length Error Frames) </b>
24589  *
24590  * This register maintains the number of frames received with length error (Length
24591  * type field not equal to frame size) for all frames with valid length field.
24592  *
24593  * Register Layout
24594  *
24595  * Bits | Access | Reset | Description
24596  * :-------|:-------|:------|:-----------------------------
24597  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RXLENERROR_CNT
24598  *
24599  */
24600 /*
24601  * Field : cnt
24602  *
24603  * This field indicates the number of frames received with length error (Length
24604  * type field not equal to frame size) for all frames with valid length field.
24605  *
24606  * Field Access Macros:
24607  *
24608  */
24609 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXLENERROR_CNT register field. */
24610 #define ALT_EMAC_GMAC_RXLENERROR_CNT_LSB 0
24611 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXLENERROR_CNT register field. */
24612 #define ALT_EMAC_GMAC_RXLENERROR_CNT_MSB 31
24613 /* The width in bits of the ALT_EMAC_GMAC_RXLENERROR_CNT register field. */
24614 #define ALT_EMAC_GMAC_RXLENERROR_CNT_WIDTH 32
24615 /* The mask used to set the ALT_EMAC_GMAC_RXLENERROR_CNT register field value. */
24616 #define ALT_EMAC_GMAC_RXLENERROR_CNT_SET_MSK 0xffffffff
24617 /* The mask used to clear the ALT_EMAC_GMAC_RXLENERROR_CNT register field value. */
24618 #define ALT_EMAC_GMAC_RXLENERROR_CNT_CLR_MSK 0x00000000
24619 /* The reset value of the ALT_EMAC_GMAC_RXLENERROR_CNT register field. */
24620 #define ALT_EMAC_GMAC_RXLENERROR_CNT_RESET 0x0
24621 /* Extracts the ALT_EMAC_GMAC_RXLENERROR_CNT field value from a register. */
24622 #define ALT_EMAC_GMAC_RXLENERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
24623 /* Produces a ALT_EMAC_GMAC_RXLENERROR_CNT register field value suitable for setting the register. */
24624 #define ALT_EMAC_GMAC_RXLENERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)
24625 
24626 #ifndef __ASSEMBLY__
24627 /*
24628  * WARNING: The C register and register group struct declarations are provided for
24629  * convenience and illustrative purposes. They should, however, be used with
24630  * caution as the C language standard provides no guarantees about the alignment or
24631  * atomicity of device memory accesses. The recommended practice for writing
24632  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24633  * alt_write_word() functions.
24634  *
24635  * The struct declaration for register ALT_EMAC_GMAC_RXLENERROR.
24636  */
24637 struct ALT_EMAC_GMAC_RXLENERROR_s
24638 {
24639  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RXLENERROR_CNT */
24640 };
24641 
24642 /* The typedef declaration for register ALT_EMAC_GMAC_RXLENERROR. */
24643 typedef volatile struct ALT_EMAC_GMAC_RXLENERROR_s ALT_EMAC_GMAC_RXLENERROR_t;
24644 #endif /* __ASSEMBLY__ */
24645 
24646 /* The reset value of the ALT_EMAC_GMAC_RXLENERROR register. */
24647 #define ALT_EMAC_GMAC_RXLENERROR_RESET 0x00000000
24648 /* The byte offset of the ALT_EMAC_GMAC_RXLENERROR register from the beginning of the component. */
24649 #define ALT_EMAC_GMAC_RXLENERROR_OFST 0x1c8
24650 /* The address of the ALT_EMAC_GMAC_RXLENERROR register. */
24651 #define ALT_EMAC_GMAC_RXLENERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXLENERROR_OFST))
24652 
24653 /*
24654  * Register : gmacgrp_rxoutofrangetype
24655  *
24656  * <b> Register 115 (Receive Frame Count for Out of Range Frames) </b>
24657  *
24658  * This register maintains the number of received frames with length field not
24659  * equal to the valid frame size (greater than 1,500 but less than 1,536).
24660  *
24661  * Register Layout
24662  *
24663  * Bits | Access | Reset | Description
24664  * :-------|:-------|:------|:-----------------------------------
24665  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT
24666  *
24667  */
24668 /*
24669  * Field : cnt
24670  *
24671  * This field indicates the number of received frames with length field not equal
24672  * to the valid frame size (greater than 1,500 but less than 1,536).
24673  *
24674  * Field Access Macros:
24675  *
24676  */
24677 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field. */
24678 #define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_LSB 0
24679 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field. */
24680 #define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_MSB 31
24681 /* The width in bits of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field. */
24682 #define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_WIDTH 32
24683 /* The mask used to set the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field value. */
24684 #define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_SET_MSK 0xffffffff
24685 /* The mask used to clear the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field value. */
24686 #define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_CLR_MSK 0x00000000
24687 /* The reset value of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field. */
24688 #define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_RESET 0x0
24689 /* Extracts the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT field value from a register. */
24690 #define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_GET(value) (((value) & 0xffffffff) >> 0)
24691 /* Produces a ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field value suitable for setting the register. */
24692 #define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_SET(value) (((value) << 0) & 0xffffffff)
24693 
24694 #ifndef __ASSEMBLY__
24695 /*
24696  * WARNING: The C register and register group struct declarations are provided for
24697  * convenience and illustrative purposes. They should, however, be used with
24698  * caution as the C language standard provides no guarantees about the alignment or
24699  * atomicity of device memory accesses. The recommended practice for writing
24700  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24701  * alt_write_word() functions.
24702  *
24703  * The struct declaration for register ALT_EMAC_GMAC_RXOUTOFRANGETYPE.
24704  */
24705 struct ALT_EMAC_GMAC_RXOUTOFRANGETYPE_s
24706 {
24707  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT */
24708 };
24709 
24710 /* The typedef declaration for register ALT_EMAC_GMAC_RXOUTOFRANGETYPE. */
24711 typedef volatile struct ALT_EMAC_GMAC_RXOUTOFRANGETYPE_s ALT_EMAC_GMAC_RXOUTOFRANGETYPE_t;
24712 #endif /* __ASSEMBLY__ */
24713 
24714 /* The reset value of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE register. */
24715 #define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_RESET 0x00000000
24716 /* The byte offset of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE register from the beginning of the component. */
24717 #define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_OFST 0x1cc
24718 /* The address of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE register. */
24719 #define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXOUTOFRANGETYPE_OFST))
24720 
24721 /*
24722  * Register : gmacgrp_rxpauseframes
24723  *
24724  * <b> Register 116 (Receive Frame Count for PAUSE Frames) </b>
24725  *
24726  * This register maintains the number of received good and valid PAUSE frames.
24727  *
24728  * Register Layout
24729  *
24730  * Bits | Access | Reset | Description
24731  * :-------|:-------|:------|:------------------------------
24732  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RXPAUSEFRMS_CNT
24733  *
24734  */
24735 /*
24736  * Field : cnt
24737  *
24738  * This field indicates the number of received good and valid PAUSE frames.
24739  *
24740  * Field Access Macros:
24741  *
24742  */
24743 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field. */
24744 #define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_LSB 0
24745 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field. */
24746 #define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_MSB 31
24747 /* The width in bits of the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field. */
24748 #define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_WIDTH 32
24749 /* The mask used to set the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field value. */
24750 #define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_SET_MSK 0xffffffff
24751 /* The mask used to clear the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field value. */
24752 #define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_CLR_MSK 0x00000000
24753 /* The reset value of the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field. */
24754 #define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_RESET 0x0
24755 /* Extracts the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT field value from a register. */
24756 #define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
24757 /* Produces a ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field value suitable for setting the register. */
24758 #define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
24759 
24760 #ifndef __ASSEMBLY__
24761 /*
24762  * WARNING: The C register and register group struct declarations are provided for
24763  * convenience and illustrative purposes. They should, however, be used with
24764  * caution as the C language standard provides no guarantees about the alignment or
24765  * atomicity of device memory accesses. The recommended practice for writing
24766  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24767  * alt_write_word() functions.
24768  *
24769  * The struct declaration for register ALT_EMAC_GMAC_RXPAUSEFRMS.
24770  */
24771 struct ALT_EMAC_GMAC_RXPAUSEFRMS_s
24772 {
24773  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RXPAUSEFRMS_CNT */
24774 };
24775 
24776 /* The typedef declaration for register ALT_EMAC_GMAC_RXPAUSEFRMS. */
24777 typedef volatile struct ALT_EMAC_GMAC_RXPAUSEFRMS_s ALT_EMAC_GMAC_RXPAUSEFRMS_t;
24778 #endif /* __ASSEMBLY__ */
24779 
24780 /* The reset value of the ALT_EMAC_GMAC_RXPAUSEFRMS register. */
24781 #define ALT_EMAC_GMAC_RXPAUSEFRMS_RESET 0x00000000
24782 /* The byte offset of the ALT_EMAC_GMAC_RXPAUSEFRMS register from the beginning of the component. */
24783 #define ALT_EMAC_GMAC_RXPAUSEFRMS_OFST 0x1d0
24784 /* The address of the ALT_EMAC_GMAC_RXPAUSEFRMS register. */
24785 #define ALT_EMAC_GMAC_RXPAUSEFRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXPAUSEFRMS_OFST))
24786 
24787 /*
24788  * Register : gmacgrp_rxfifooverflow
24789  *
24790  * <b> Register 117 (Receive Frame Count for FIFO Overflow Frames) </b>
24791  *
24792  * This register maintains the number of received frames missed because of FIFO
24793  * overflow.
24794  *
24795  * Register Layout
24796  *
24797  * Bits | Access | Reset | Description
24798  * :-------|:-------|:------|:----------------------------
24799  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RXFIFOOVF_CNT
24800  *
24801  */
24802 /*
24803  * Field : cnt
24804  *
24805  * This field indicates the number of received frames missed because of FIFO
24806  * overflow.
24807  *
24808  * Field Access Macros:
24809  *
24810  */
24811 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field. */
24812 #define ALT_EMAC_GMAC_RXFIFOOVF_CNT_LSB 0
24813 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field. */
24814 #define ALT_EMAC_GMAC_RXFIFOOVF_CNT_MSB 31
24815 /* The width in bits of the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field. */
24816 #define ALT_EMAC_GMAC_RXFIFOOVF_CNT_WIDTH 32
24817 /* The mask used to set the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field value. */
24818 #define ALT_EMAC_GMAC_RXFIFOOVF_CNT_SET_MSK 0xffffffff
24819 /* The mask used to clear the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field value. */
24820 #define ALT_EMAC_GMAC_RXFIFOOVF_CNT_CLR_MSK 0x00000000
24821 /* The reset value of the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field. */
24822 #define ALT_EMAC_GMAC_RXFIFOOVF_CNT_RESET 0x0
24823 /* Extracts the ALT_EMAC_GMAC_RXFIFOOVF_CNT field value from a register. */
24824 #define ALT_EMAC_GMAC_RXFIFOOVF_CNT_GET(value) (((value) & 0xffffffff) >> 0)
24825 /* Produces a ALT_EMAC_GMAC_RXFIFOOVF_CNT register field value suitable for setting the register. */
24826 #define ALT_EMAC_GMAC_RXFIFOOVF_CNT_SET(value) (((value) << 0) & 0xffffffff)
24827 
24828 #ifndef __ASSEMBLY__
24829 /*
24830  * WARNING: The C register and register group struct declarations are provided for
24831  * convenience and illustrative purposes. They should, however, be used with
24832  * caution as the C language standard provides no guarantees about the alignment or
24833  * atomicity of device memory accesses. The recommended practice for writing
24834  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24835  * alt_write_word() functions.
24836  *
24837  * The struct declaration for register ALT_EMAC_GMAC_RXFIFOOVF.
24838  */
24839 struct ALT_EMAC_GMAC_RXFIFOOVF_s
24840 {
24841  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RXFIFOOVF_CNT */
24842 };
24843 
24844 /* The typedef declaration for register ALT_EMAC_GMAC_RXFIFOOVF. */
24845 typedef volatile struct ALT_EMAC_GMAC_RXFIFOOVF_s ALT_EMAC_GMAC_RXFIFOOVF_t;
24846 #endif /* __ASSEMBLY__ */
24847 
24848 /* The reset value of the ALT_EMAC_GMAC_RXFIFOOVF register. */
24849 #define ALT_EMAC_GMAC_RXFIFOOVF_RESET 0x00000000
24850 /* The byte offset of the ALT_EMAC_GMAC_RXFIFOOVF register from the beginning of the component. */
24851 #define ALT_EMAC_GMAC_RXFIFOOVF_OFST 0x1d4
24852 /* The address of the ALT_EMAC_GMAC_RXFIFOOVF register. */
24853 #define ALT_EMAC_GMAC_RXFIFOOVF_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXFIFOOVF_OFST))
24854 
24855 /*
24856  * Register : gmacgrp_rxvlanframes_gb
24857  *
24858  * <b> Register 118 (Receive Frame Count for Good and Bad VLAN Frames) </b>
24859  *
24860  * This register maintains the number of received good and bad VLAN frames.
24861  *
24862  * Register Layout
24863  *
24864  * Bits | Access | Reset | Description
24865  * :-------|:-------|:------|:--------------------------------
24866  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT
24867  *
24868  */
24869 /*
24870  * Field : cnt
24871  *
24872  * This field indicates the number of received good and bad VLAN frames.
24873  *
24874  * Field Access Macros:
24875  *
24876  */
24877 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field. */
24878 #define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_LSB 0
24879 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field. */
24880 #define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_MSB 31
24881 /* The width in bits of the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field. */
24882 #define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_WIDTH 32
24883 /* The mask used to set the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field value. */
24884 #define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_SET_MSK 0xffffffff
24885 /* The mask used to clear the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field value. */
24886 #define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_CLR_MSK 0x00000000
24887 /* The reset value of the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field. */
24888 #define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_RESET 0x0
24889 /* Extracts the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT field value from a register. */
24890 #define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
24891 /* Produces a ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field value suitable for setting the register. */
24892 #define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
24893 
24894 #ifndef __ASSEMBLY__
24895 /*
24896  * WARNING: The C register and register group struct declarations are provided for
24897  * convenience and illustrative purposes. They should, however, be used with
24898  * caution as the C language standard provides no guarantees about the alignment or
24899  * atomicity of device memory accesses. The recommended practice for writing
24900  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24901  * alt_write_word() functions.
24902  *
24903  * The struct declaration for register ALT_EMAC_GMAC_RXVLANFRMS_GB.
24904  */
24905 struct ALT_EMAC_GMAC_RXVLANFRMS_GB_s
24906 {
24907  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT */
24908 };
24909 
24910 /* The typedef declaration for register ALT_EMAC_GMAC_RXVLANFRMS_GB. */
24911 typedef volatile struct ALT_EMAC_GMAC_RXVLANFRMS_GB_s ALT_EMAC_GMAC_RXVLANFRMS_GB_t;
24912 #endif /* __ASSEMBLY__ */
24913 
24914 /* The reset value of the ALT_EMAC_GMAC_RXVLANFRMS_GB register. */
24915 #define ALT_EMAC_GMAC_RXVLANFRMS_GB_RESET 0x00000000
24916 /* The byte offset of the ALT_EMAC_GMAC_RXVLANFRMS_GB register from the beginning of the component. */
24917 #define ALT_EMAC_GMAC_RXVLANFRMS_GB_OFST 0x1d8
24918 /* The address of the ALT_EMAC_GMAC_RXVLANFRMS_GB register. */
24919 #define ALT_EMAC_GMAC_RXVLANFRMS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXVLANFRMS_GB_OFST))
24920 
24921 /*
24922  * Register : gmacgrp_rxwatchdogerror
24923  *
24924  * <b> Register 119 (Receive Frame Count for Watchdog Error Frames) </b>
24925  *
24926  * This register maintains the number of frames received with error because of the
24927  * watchdog timeout error (frames with more than 2,048 bytes or value programmed in
24928  * Register 55 (Watchdog Timeout Register)).
24929  *
24930  * Register Layout
24931  *
24932  * Bits | Access | Reset | Description
24933  * :-------|:-------|:------|:----------------------------
24934  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RXWDERROR_CNT
24935  *
24936  */
24937 /*
24938  * Field : cnt
24939  *
24940  * This field indicates the number of frames received with error because of the
24941  * watchdog timeout error (frames with more than 2,048 bytes or value programmed in
24942  * Register 55 (Watchdog Timeout Register)).
24943  *
24944  * Field Access Macros:
24945  *
24946  */
24947 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXWDERROR_CNT register field. */
24948 #define ALT_EMAC_GMAC_RXWDERROR_CNT_LSB 0
24949 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXWDERROR_CNT register field. */
24950 #define ALT_EMAC_GMAC_RXWDERROR_CNT_MSB 31
24951 /* The width in bits of the ALT_EMAC_GMAC_RXWDERROR_CNT register field. */
24952 #define ALT_EMAC_GMAC_RXWDERROR_CNT_WIDTH 32
24953 /* The mask used to set the ALT_EMAC_GMAC_RXWDERROR_CNT register field value. */
24954 #define ALT_EMAC_GMAC_RXWDERROR_CNT_SET_MSK 0xffffffff
24955 /* The mask used to clear the ALT_EMAC_GMAC_RXWDERROR_CNT register field value. */
24956 #define ALT_EMAC_GMAC_RXWDERROR_CNT_CLR_MSK 0x00000000
24957 /* The reset value of the ALT_EMAC_GMAC_RXWDERROR_CNT register field. */
24958 #define ALT_EMAC_GMAC_RXWDERROR_CNT_RESET 0x0
24959 /* Extracts the ALT_EMAC_GMAC_RXWDERROR_CNT field value from a register. */
24960 #define ALT_EMAC_GMAC_RXWDERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
24961 /* Produces a ALT_EMAC_GMAC_RXWDERROR_CNT register field value suitable for setting the register. */
24962 #define ALT_EMAC_GMAC_RXWDERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)
24963 
24964 #ifndef __ASSEMBLY__
24965 /*
24966  * WARNING: The C register and register group struct declarations are provided for
24967  * convenience and illustrative purposes. They should, however, be used with
24968  * caution as the C language standard provides no guarantees about the alignment or
24969  * atomicity of device memory accesses. The recommended practice for writing
24970  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24971  * alt_write_word() functions.
24972  *
24973  * The struct declaration for register ALT_EMAC_GMAC_RXWDERROR.
24974  */
24975 struct ALT_EMAC_GMAC_RXWDERROR_s
24976 {
24977  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RXWDERROR_CNT */
24978 };
24979 
24980 /* The typedef declaration for register ALT_EMAC_GMAC_RXWDERROR. */
24981 typedef volatile struct ALT_EMAC_GMAC_RXWDERROR_s ALT_EMAC_GMAC_RXWDERROR_t;
24982 #endif /* __ASSEMBLY__ */
24983 
24984 /* The reset value of the ALT_EMAC_GMAC_RXWDERROR register. */
24985 #define ALT_EMAC_GMAC_RXWDERROR_RESET 0x00000000
24986 /* The byte offset of the ALT_EMAC_GMAC_RXWDERROR register from the beginning of the component. */
24987 #define ALT_EMAC_GMAC_RXWDERROR_OFST 0x1dc
24988 /* The address of the ALT_EMAC_GMAC_RXWDERROR register. */
24989 #define ALT_EMAC_GMAC_RXWDERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXWDERROR_OFST))
24990 
24991 /*
24992  * Register : gmacgrp_rxrcverror
24993  *
24994  * <b> Register 120 (Receive Frame Count for Receive Error Frames) </b>
24995  *
24996  * This register maintains the number of frames received with error because of the
24997  * GMII/MII RXER error.
24998  *
24999  * Register Layout
25000  *
25001  * Bits | Access | Reset | Description
25002  * :-------|:-------|:------|:-----------------------------
25003  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RXRCVERROR_CNT
25004  *
25005  */
25006 /*
25007  * Field : cnt
25008  *
25009  * This field indicates the number of frames received with error because of the
25010  * GMII/MII RXER error or Frame Extension error on GMII.
25011  *
25012  * Field Access Macros:
25013  *
25014  */
25015 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXRCVERROR_CNT register field. */
25016 #define ALT_EMAC_GMAC_RXRCVERROR_CNT_LSB 0
25017 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXRCVERROR_CNT register field. */
25018 #define ALT_EMAC_GMAC_RXRCVERROR_CNT_MSB 31
25019 /* The width in bits of the ALT_EMAC_GMAC_RXRCVERROR_CNT register field. */
25020 #define ALT_EMAC_GMAC_RXRCVERROR_CNT_WIDTH 32
25021 /* The mask used to set the ALT_EMAC_GMAC_RXRCVERROR_CNT register field value. */
25022 #define ALT_EMAC_GMAC_RXRCVERROR_CNT_SET_MSK 0xffffffff
25023 /* The mask used to clear the ALT_EMAC_GMAC_RXRCVERROR_CNT register field value. */
25024 #define ALT_EMAC_GMAC_RXRCVERROR_CNT_CLR_MSK 0x00000000
25025 /* The reset value of the ALT_EMAC_GMAC_RXRCVERROR_CNT register field. */
25026 #define ALT_EMAC_GMAC_RXRCVERROR_CNT_RESET 0x0
25027 /* Extracts the ALT_EMAC_GMAC_RXRCVERROR_CNT field value from a register. */
25028 #define ALT_EMAC_GMAC_RXRCVERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
25029 /* Produces a ALT_EMAC_GMAC_RXRCVERROR_CNT register field value suitable for setting the register. */
25030 #define ALT_EMAC_GMAC_RXRCVERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)
25031 
25032 #ifndef __ASSEMBLY__
25033 /*
25034  * WARNING: The C register and register group struct declarations are provided for
25035  * convenience and illustrative purposes. They should, however, be used with
25036  * caution as the C language standard provides no guarantees about the alignment or
25037  * atomicity of device memory accesses. The recommended practice for writing
25038  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
25039  * alt_write_word() functions.
25040  *
25041  * The struct declaration for register ALT_EMAC_GMAC_RXRCVERROR.
25042  */
25043 struct ALT_EMAC_GMAC_RXRCVERROR_s
25044 {
25045  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RXRCVERROR_CNT */
25046 };
25047 
25048 /* The typedef declaration for register ALT_EMAC_GMAC_RXRCVERROR. */
25049 typedef volatile struct ALT_EMAC_GMAC_RXRCVERROR_s ALT_EMAC_GMAC_RXRCVERROR_t;
25050 #endif /* __ASSEMBLY__ */
25051 
25052 /* The reset value of the ALT_EMAC_GMAC_RXRCVERROR register. */
25053 #define ALT_EMAC_GMAC_RXRCVERROR_RESET 0x00000000
25054 /* The byte offset of the ALT_EMAC_GMAC_RXRCVERROR register from the beginning of the component. */
25055 #define ALT_EMAC_GMAC_RXRCVERROR_OFST 0x1e0
25056 /* The address of the ALT_EMAC_GMAC_RXRCVERROR register. */
25057 #define ALT_EMAC_GMAC_RXRCVERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXRCVERROR_OFST))
25058 
25059 /*
25060  * Register : gmacgrp_rxctrlframes_g
25061  *
25062  * <b> Register 121 (Receive Frame Count for Good Control Frames Frames) </b>
25063  *
25064  * This register maintains the number of good control frames received.
25065  *
25066  * Register Layout
25067  *
25068  * Bits | Access | Reset | Description
25069  * :-------|:-------|:------|:------------------------------
25070  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RXCTLFRMS_G_CNT
25071  *
25072  */
25073 /*
25074  * Field : cnt
25075  *
25076  * This field indicates the number of good control frames received.
25077  *
25078  * Field Access Macros:
25079  *
25080  */
25081 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field. */
25082 #define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_LSB 0
25083 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field. */
25084 #define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_MSB 31
25085 /* The width in bits of the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field. */
25086 #define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_WIDTH 32
25087 /* The mask used to set the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field value. */
25088 #define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_SET_MSK 0xffffffff
25089 /* The mask used to clear the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field value. */
25090 #define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_CLR_MSK 0x00000000
25091 /* The reset value of the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field. */
25092 #define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_RESET 0x0
25093 /* Extracts the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT field value from a register. */
25094 #define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
25095 /* Produces a ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field value suitable for setting the register. */
25096 #define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
25097 
25098 #ifndef __ASSEMBLY__
25099 /*
25100  * WARNING: The C register and register group struct declarations are provided for
25101  * convenience and illustrative purposes. They should, however, be used with
25102  * caution as the C language standard provides no guarantees about the alignment or
25103  * atomicity of device memory accesses. The recommended practice for writing
25104  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
25105  * alt_write_word() functions.
25106  *
25107  * The struct declaration for register ALT_EMAC_GMAC_RXCTLFRMS_G.
25108  */
25109 struct ALT_EMAC_GMAC_RXCTLFRMS_G_s
25110 {
25111  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RXCTLFRMS_G_CNT */
25112 };
25113 
25114 /* The typedef declaration for register ALT_EMAC_GMAC_RXCTLFRMS_G. */
25115 typedef volatile struct ALT_EMAC_GMAC_RXCTLFRMS_G_s ALT_EMAC_GMAC_RXCTLFRMS_G_t;
25116 #endif /* __ASSEMBLY__ */
25117 
25118 /* The reset value of the ALT_EMAC_GMAC_RXCTLFRMS_G register. */
25119 #define ALT_EMAC_GMAC_RXCTLFRMS_G_RESET 0x00000000
25120 /* The byte offset of the ALT_EMAC_GMAC_RXCTLFRMS_G register from the beginning of the component. */
25121 #define ALT_EMAC_GMAC_RXCTLFRMS_G_OFST 0x1e4
25122 /* The address of the ALT_EMAC_GMAC_RXCTLFRMS_G register. */
25123 #define ALT_EMAC_GMAC_RXCTLFRMS_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXCTLFRMS_G_OFST))
25124 
25125 /*
25126  * Register : Register 128 (MMC Receive Checksum Offload Interrupt Mask Register) - gmacgrp_mmc_ipc_receive_interrupt_mask
25127  *
25128  * This register maintains the mask for the interrupt generated from the receive
25129  * IPC statistic
25130  *
25131  * counters.
25132  *
25133  * Register Layout
25134  *
25135  * Bits | Access | Reset | Description
25136  * :--------|:-------|:------|:--------------------------------------------------------------------
25137  * [0] | RW | 0x0 | MMC Receive IPV4 Good Frame Counter Interrupt Mask
25138  * [1] | RW | 0x0 | MMC Receive IPV4 Header Error Frame Counter Interrupt Mask
25139  * [2] | RW | 0x0 | MMC Receive IPV4 No Payload Frame Counter Interrupt Mask
25140  * [3] | RW | 0x0 | MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask
25141  * [4] | RW | 0x0 | MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask
25142  * [5] | RW | 0x0 | MMC Receive IPV6 Good Frame Counter Interrupt Mask
25143  * [6] | RW | 0x0 | MMC Receive IPV6 Header Error Frame Counter Interrupt Mask
25144  * [7] | RW | 0x0 | MMC Receive IPV6 No Payload Frame Counter Interrupt Mask
25145  * [8] | RW | 0x0 | MMC Receive UDP Good Frame Counter Interrupt Mask
25146  * [9] | RW | 0x0 | MMC Receive UDP Error Frame Counter Interrupt Mask
25147  * [10] | RW | 0x0 | MMC Receive TCP Good Frame Counter Interrupt Mask
25148  * [11] | RW | 0x0 | MMC Receive TCP Error Frame Counter Interrupt Mask
25149  * [12] | RW | 0x0 | MMC Receive ICMP Good Frame Counter Interrupt Mask
25150  * [13] | RW | 0x0 | MMC Receive ICMP Error Frame Counter Interrupt Mask
25151  * [15:14] | ??? | 0x0 | *UNDEFINED*
25152  * [16] | RW | 0x0 | MMC Receive IPV4 Good Octet Counter Interrupt Mask
25153  * [17] | RW | 0x0 | MMC Receive IPV4 Header Error Octet Counter Interrupt Mask
25154  * [18] | RW | 0x0 | MMC Receive IPV4 No Payload Octet Counter Interrupt Mask
25155  * [19] | RW | 0x0 | MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask
25156  * [20] | RW | 0x0 | MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask
25157  * [21] | RW | 0x0 | MMC Receive IPV6 Good Octet Counter Interrupt Mask
25158  * [22] | RW | 0x0 | MMC Receive IPV6 Header Error Octet Counter Interrupt Mask
25159  * [23] | RW | 0x0 | MMC Receive IPV6 No Payload Octet Counter Interrupt Mask
25160  * [24] | RW | 0x0 | MMC Receive UDP Good Octet Counter Interrupt Mask
25161  * [25] | RW | 0x0 | MMC Receive UDP Error Octet Counter Interrupt Mask
25162  * [26] | RW | 0x0 | MMC Receive TCP Good Octet Counter Interrupt Mask
25163  * [27] | RW | 0x0 | MMC Receive TCP Error Octet Counter Interrupt Mask
25164  * [28] | RW | 0x0 | MMC Receive ICMP Good Octet Counter Interrupt Mask
25165  * [29] | RW | 0x0 | MMC Receive ICMP Error Octet Counter Interrupt Mask
25166  * [31:30] | ??? | 0x0 | *UNDEFINED*
25167  *
25168  */
25169 /*
25170  * Field : MMC Receive IPV4 Good Frame Counter Interrupt Mask - rxipv4gfim
25171  *
25172  * Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches
25173  * half of the maximum value or the maximum value.
25174  *
25175  * Field Enumeration Values:
25176  *
25177  * Enum | Value | Description
25178  * :------------------------------------------------------|:------|:------------
25179  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_E_NOMSKINTR | 0x0 |
25180  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_E_MSKINTR | 0x1 |
25181  *
25182  * Field Access Macros:
25183  *
25184  */
25185 /*
25186  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM
25187  *
25188  */
25189 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_E_NOMSKINTR 0x0
25190 /*
25191  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM
25192  *
25193  */
25194 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_E_MSKINTR 0x1
25195 
25196 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field. */
25197 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_LSB 0
25198 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field. */
25199 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_MSB 0
25200 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field. */
25201 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_WIDTH 1
25202 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field value. */
25203 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_SET_MSK 0x00000001
25204 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field value. */
25205 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_CLR_MSK 0xfffffffe
25206 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field. */
25207 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_RESET 0x0
25208 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM field value from a register. */
25209 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_GET(value) (((value) & 0x00000001) >> 0)
25210 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field value suitable for setting the register. */
25211 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_SET(value) (((value) << 0) & 0x00000001)
25212 
25213 /*
25214  * Field : MMC Receive IPV4 Header Error Frame Counter Interrupt Mask - rxipv4herfim
25215  *
25216  * Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches
25217  * half of the maximum value or the maximum value.
25218  *
25219  * Field Enumeration Values:
25220  *
25221  * Enum | Value | Description
25222  * :--------------------------------------------------------|:------|:------------
25223  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_E_NOMSKINTR | 0x0 |
25224  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_E_MSKINTR | 0x1 |
25225  *
25226  * Field Access Macros:
25227  *
25228  */
25229 /*
25230  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM
25231  *
25232  */
25233 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_E_NOMSKINTR 0x0
25234 /*
25235  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM
25236  *
25237  */
25238 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_E_MSKINTR 0x1
25239 
25240 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field. */
25241 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_LSB 1
25242 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field. */
25243 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_MSB 1
25244 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field. */
25245 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_WIDTH 1
25246 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field value. */
25247 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_SET_MSK 0x00000002
25248 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field value. */
25249 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_CLR_MSK 0xfffffffd
25250 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field. */
25251 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_RESET 0x0
25252 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM field value from a register. */
25253 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_GET(value) (((value) & 0x00000002) >> 1)
25254 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field value suitable for setting the register. */
25255 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_SET(value) (((value) << 1) & 0x00000002)
25256 
25257 /*
25258  * Field : MMC Receive IPV4 No Payload Frame Counter Interrupt Mask - rxipv4nopayfim
25259  *
25260  * Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches
25261  * half of the maximum value or the maximum value.
25262  *
25263  * Field Enumeration Values:
25264  *
25265  * Enum | Value | Description
25266  * :----------------------------------------------------------|:------|:------------
25267  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_E_NOMSKINTR | 0x0 |
25268  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_E_MSKINTR | 0x1 |
25269  *
25270  * Field Access Macros:
25271  *
25272  */
25273 /*
25274  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM
25275  *
25276  */
25277 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_E_NOMSKINTR 0x0
25278 /*
25279  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM
25280  *
25281  */
25282 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_E_MSKINTR 0x1
25283 
25284 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field. */
25285 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_LSB 2
25286 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field. */
25287 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_MSB 2
25288 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field. */
25289 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_WIDTH 1
25290 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field value. */
25291 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_SET_MSK 0x00000004
25292 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field value. */
25293 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_CLR_MSK 0xfffffffb
25294 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field. */
25295 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_RESET 0x0
25296 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM field value from a register. */
25297 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_GET(value) (((value) & 0x00000004) >> 2)
25298 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field value suitable for setting the register. */
25299 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_SET(value) (((value) << 2) & 0x00000004)
25300 
25301 /*
25302  * Field : MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask - rxipv4fragfim
25303  *
25304  * Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches
25305  * half of the maximum value or the maximum value.
25306  *
25307  * Field Enumeration Values:
25308  *
25309  * Enum | Value | Description
25310  * :---------------------------------------------------------|:------|:------------
25311  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_E_NOMSKINTR | 0x0 |
25312  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_E_MSKINTR | 0x1 |
25313  *
25314  * Field Access Macros:
25315  *
25316  */
25317 /*
25318  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM
25319  *
25320  */
25321 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_E_NOMSKINTR 0x0
25322 /*
25323  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM
25324  *
25325  */
25326 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_E_MSKINTR 0x1
25327 
25328 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field. */
25329 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_LSB 3
25330 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field. */
25331 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_MSB 3
25332 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field. */
25333 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_WIDTH 1
25334 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field value. */
25335 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_SET_MSK 0x00000008
25336 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field value. */
25337 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_CLR_MSK 0xfffffff7
25338 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field. */
25339 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_RESET 0x0
25340 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM field value from a register. */
25341 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_GET(value) (((value) & 0x00000008) >> 3)
25342 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field value suitable for setting the register. */
25343 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_SET(value) (((value) << 3) & 0x00000008)
25344 
25345 /*
25346  * Field : MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask - rxipv4udsblfim
25347  *
25348  * Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches
25349  * half of the maximum value or the maximum value.
25350  *
25351  * Field Enumeration Values:
25352  *
25353  * Enum | Value | Description
25354  * :----------------------------------------------------------|:------|:------------
25355  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_E_NOMSKINTR | 0x0 |
25356  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_E_MSKINTR | 0x1 |
25357  *
25358  * Field Access Macros:
25359  *
25360  */
25361 /*
25362  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM
25363  *
25364  */
25365 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_E_NOMSKINTR 0x0
25366 /*
25367  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM
25368  *
25369  */
25370 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_E_MSKINTR 0x1
25371 
25372 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field. */
25373 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_LSB 4
25374 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field. */
25375 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_MSB 4
25376 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field. */
25377 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_WIDTH 1
25378 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field value. */
25379 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_SET_MSK 0x00000010
25380 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field value. */
25381 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_CLR_MSK 0xffffffef
25382 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field. */
25383 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_RESET 0x0
25384 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM field value from a register. */
25385 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_GET(value) (((value) & 0x00000010) >> 4)
25386 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field value suitable for setting the register. */
25387 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_SET(value) (((value) << 4) & 0x00000010)
25388 
25389 /*
25390  * Field : MMC Receive IPV6 Good Frame Counter Interrupt Mask - rxipv6gfim
25391  *
25392  * Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches
25393  * half of the maximum value or the maximum value.
25394  *
25395  * Field Enumeration Values:
25396  *
25397  * Enum | Value | Description
25398  * :------------------------------------------------------|:------|:------------
25399  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_E_NOMSKINTR | 0x0 |
25400  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_E_MSKINTR | 0x1 |
25401  *
25402  * Field Access Macros:
25403  *
25404  */
25405 /*
25406  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM
25407  *
25408  */
25409 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_E_NOMSKINTR 0x0
25410 /*
25411  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM
25412  *
25413  */
25414 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_E_MSKINTR 0x1
25415 
25416 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field. */
25417 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_LSB 5
25418 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field. */
25419 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_MSB 5
25420 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field. */
25421 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_WIDTH 1
25422 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field value. */
25423 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_SET_MSK 0x00000020
25424 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field value. */
25425 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_CLR_MSK 0xffffffdf
25426 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field. */
25427 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_RESET 0x0
25428 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM field value from a register. */
25429 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_GET(value) (((value) & 0x00000020) >> 5)
25430 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field value suitable for setting the register. */
25431 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_SET(value) (((value) << 5) & 0x00000020)
25432 
25433 /*
25434  * Field : MMC Receive IPV6 Header Error Frame Counter Interrupt Mask - rxipv6herfim
25435  *
25436  * Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches
25437  * half of the maximum value or the maximum value.
25438  *
25439  * Field Enumeration Values:
25440  *
25441  * Enum | Value | Description
25442  * :--------------------------------------------------------|:------|:------------
25443  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_E_NOMSKINTR | 0x0 |
25444  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_E_MSKINTR | 0x1 |
25445  *
25446  * Field Access Macros:
25447  *
25448  */
25449 /*
25450  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM
25451  *
25452  */
25453 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_E_NOMSKINTR 0x0
25454 /*
25455  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM
25456  *
25457  */
25458 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_E_MSKINTR 0x1
25459 
25460 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field. */
25461 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_LSB 6
25462 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field. */
25463 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_MSB 6
25464 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field. */
25465 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_WIDTH 1
25466 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field value. */
25467 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_SET_MSK 0x00000040
25468 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field value. */
25469 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_CLR_MSK 0xffffffbf
25470 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field. */
25471 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_RESET 0x0
25472 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM field value from a register. */
25473 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_GET(value) (((value) & 0x00000040) >> 6)
25474 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field value suitable for setting the register. */
25475 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_SET(value) (((value) << 6) & 0x00000040)
25476 
25477 /*
25478  * Field : MMC Receive IPV6 No Payload Frame Counter Interrupt Mask - rxipv6nopayfim
25479  *
25480  * Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches
25481  * half of the maximum value or the maximum value.
25482  *
25483  * Field Enumeration Values:
25484  *
25485  * Enum | Value | Description
25486  * :----------------------------------------------------------|:------|:------------
25487  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_E_NOMSKINTR | 0x0 |
25488  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_E_MSKINTR | 0x1 |
25489  *
25490  * Field Access Macros:
25491  *
25492  */
25493 /*
25494  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM
25495  *
25496  */
25497 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_E_NOMSKINTR 0x0
25498 /*
25499  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM
25500  *
25501  */
25502 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_E_MSKINTR 0x1
25503 
25504 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field. */
25505 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_LSB 7
25506 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field. */
25507 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_MSB 7
25508 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field. */
25509 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_WIDTH 1
25510 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field value. */
25511 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_SET_MSK 0x00000080
25512 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field value. */
25513 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_CLR_MSK 0xffffff7f
25514 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field. */
25515 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_RESET 0x0
25516 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM field value from a register. */
25517 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_GET(value) (((value) & 0x00000080) >> 7)
25518 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field value suitable for setting the register. */
25519 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_SET(value) (((value) << 7) & 0x00000080)
25520 
25521 /*
25522  * Field : MMC Receive UDP Good Frame Counter Interrupt Mask - rxudpgfim
25523  *
25524  * Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half
25525  * of the maximum value or the maximum value.
25526  *
25527  * Field Enumeration Values:
25528  *
25529  * Enum | Value | Description
25530  * :-----------------------------------------------------|:------|:------------
25531  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_E_NOMSKINTR | 0x0 |
25532  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_E_MSKINTR | 0x1 |
25533  *
25534  * Field Access Macros:
25535  *
25536  */
25537 /*
25538  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM
25539  *
25540  */
25541 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_E_NOMSKINTR 0x0
25542 /*
25543  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM
25544  *
25545  */
25546 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_E_MSKINTR 0x1
25547 
25548 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field. */
25549 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_LSB 8
25550 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field. */
25551 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_MSB 8
25552 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field. */
25553 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_WIDTH 1
25554 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field value. */
25555 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_SET_MSK 0x00000100
25556 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field value. */
25557 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_CLR_MSK 0xfffffeff
25558 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field. */
25559 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_RESET 0x0
25560 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM field value from a register. */
25561 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_GET(value) (((value) & 0x00000100) >> 8)
25562 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field value suitable for setting the register. */
25563 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_SET(value) (((value) << 8) & 0x00000100)
25564 
25565 /*
25566  * Field : MMC Receive UDP Error Frame Counter Interrupt Mask - rxudperfim
25567  *
25568  * Setting this bit masks the interrupt when the rxudp_err_frms counter reaches
25569  * half of the maximum value or the maximum value.
25570  *
25571  * Field Enumeration Values:
25572  *
25573  * Enum | Value | Description
25574  * :------------------------------------------------------|:------|:------------
25575  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_E_NOMSKINTR | 0x0 |
25576  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_E_MSKINTR | 0x1 |
25577  *
25578  * Field Access Macros:
25579  *
25580  */
25581 /*
25582  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM
25583  *
25584  */
25585 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_E_NOMSKINTR 0x0
25586 /*
25587  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM
25588  *
25589  */
25590 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_E_MSKINTR 0x1
25591 
25592 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field. */
25593 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_LSB 9
25594 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field. */
25595 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_MSB 9
25596 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field. */
25597 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_WIDTH 1
25598 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field value. */
25599 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_SET_MSK 0x00000200
25600 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field value. */
25601 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_CLR_MSK 0xfffffdff
25602 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field. */
25603 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_RESET 0x0
25604 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM field value from a register. */
25605 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_GET(value) (((value) & 0x00000200) >> 9)
25606 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field value suitable for setting the register. */
25607 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_SET(value) (((value) << 9) & 0x00000200)
25608 
25609 /*
25610  * Field : MMC Receive TCP Good Frame Counter Interrupt Mask - rxtcpgfim
25611  *
25612  * Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half
25613  * of the maximum value or the maximum value.
25614  *
25615  * Field Enumeration Values:
25616  *
25617  * Enum | Value | Description
25618  * :-----------------------------------------------------|:------|:------------
25619  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_E_NOMSKINTR | 0x0 |
25620  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_E_MSKINTR | 0x1 |
25621  *
25622  * Field Access Macros:
25623  *
25624  */
25625 /*
25626  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM
25627  *
25628  */
25629 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_E_NOMSKINTR 0x0
25630 /*
25631  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM
25632  *
25633  */
25634 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_E_MSKINTR 0x1
25635 
25636 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field. */
25637 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_LSB 10
25638 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field. */
25639 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_MSB 10
25640 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field. */
25641 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_WIDTH 1
25642 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field value. */
25643 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_SET_MSK 0x00000400
25644 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field value. */
25645 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_CLR_MSK 0xfffffbff
25646 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field. */
25647 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_RESET 0x0
25648 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM field value from a register. */
25649 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_GET(value) (((value) & 0x00000400) >> 10)
25650 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field value suitable for setting the register. */
25651 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_SET(value) (((value) << 10) & 0x00000400)
25652 
25653 /*
25654  * Field : MMC Receive TCP Error Frame Counter Interrupt Mask - rxtcperfim
25655  *
25656  * Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches
25657  * half of the maximum value or the maximum value.
25658  *
25659  * Field Enumeration Values:
25660  *
25661  * Enum | Value | Description
25662  * :------------------------------------------------------|:------|:------------
25663  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_E_NOMSKINTR | 0x0 |
25664  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_E_MSKINTR | 0x1 |
25665  *
25666  * Field Access Macros:
25667  *
25668  */
25669 /*
25670  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM
25671  *
25672  */
25673 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_E_NOMSKINTR 0x0
25674 /*
25675  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM
25676  *
25677  */
25678 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_E_MSKINTR 0x1
25679 
25680 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field. */
25681 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_LSB 11
25682 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field. */
25683 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_MSB 11
25684 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field. */
25685 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_WIDTH 1
25686 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field value. */
25687 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_SET_MSK 0x00000800
25688 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field value. */
25689 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_CLR_MSK 0xfffff7ff
25690 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field. */
25691 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_RESET 0x0
25692 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM field value from a register. */
25693 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_GET(value) (((value) & 0x00000800) >> 11)
25694 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field value suitable for setting the register. */
25695 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_SET(value) (((value) << 11) & 0x00000800)
25696 
25697 /*
25698  * Field : MMC Receive ICMP Good Frame Counter Interrupt Mask - rxicmpgfim
25699  *
25700  * Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches
25701  * half of the maximum value or the maximum value.
25702  *
25703  * Field Enumeration Values:
25704  *
25705  * Enum | Value | Description
25706  * :------------------------------------------------------|:------|:------------
25707  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_E_NOMSKINTR | 0x0 |
25708  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_E_MSKINTR | 0x1 |
25709  *
25710  * Field Access Macros:
25711  *
25712  */
25713 /*
25714  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM
25715  *
25716  */
25717 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_E_NOMSKINTR 0x0
25718 /*
25719  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM
25720  *
25721  */
25722 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_E_MSKINTR 0x1
25723 
25724 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field. */
25725 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_LSB 12
25726 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field. */
25727 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_MSB 12
25728 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field. */
25729 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_WIDTH 1
25730 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field value. */
25731 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_SET_MSK 0x00001000
25732 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field value. */
25733 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_CLR_MSK 0xffffefff
25734 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field. */
25735 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_RESET 0x0
25736 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM field value from a register. */
25737 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_GET(value) (((value) & 0x00001000) >> 12)
25738 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field value suitable for setting the register. */
25739 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_SET(value) (((value) << 12) & 0x00001000)
25740 
25741 /*
25742  * Field : MMC Receive ICMP Error Frame Counter Interrupt Mask - rxicmperfim
25743  *
25744  * Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches
25745  * half of the maximum value or the maximum value.
25746  *
25747  * Field Enumeration Values:
25748  *
25749  * Enum | Value | Description
25750  * :-------------------------------------------------------|:------|:------------
25751  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_E_NOMSKINTR | 0x0 |
25752  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_E_MSKINTR | 0x1 |
25753  *
25754  * Field Access Macros:
25755  *
25756  */
25757 /*
25758  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM
25759  *
25760  */
25761 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_E_NOMSKINTR 0x0
25762 /*
25763  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM
25764  *
25765  */
25766 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_E_MSKINTR 0x1
25767 
25768 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field. */
25769 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_LSB 13
25770 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field. */
25771 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_MSB 13
25772 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field. */
25773 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_WIDTH 1
25774 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field value. */
25775 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_SET_MSK 0x00002000
25776 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field value. */
25777 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_CLR_MSK 0xffffdfff
25778 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field. */
25779 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_RESET 0x0
25780 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM field value from a register. */
25781 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_GET(value) (((value) & 0x00002000) >> 13)
25782 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field value suitable for setting the register. */
25783 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_SET(value) (((value) << 13) & 0x00002000)
25784 
25785 /*
25786  * Field : MMC Receive IPV4 Good Octet Counter Interrupt Mask - rxipv4goim
25787  *
25788  * Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches
25789  * half of the maximum value or the maximum value.
25790  *
25791  * Field Enumeration Values:
25792  *
25793  * Enum | Value | Description
25794  * :------------------------------------------------------|:------|:------------
25795  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_E_NOMSKINTR | 0x0 |
25796  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_E_MSKINTR | 0x1 |
25797  *
25798  * Field Access Macros:
25799  *
25800  */
25801 /*
25802  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM
25803  *
25804  */
25805 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_E_NOMSKINTR 0x0
25806 /*
25807  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM
25808  *
25809  */
25810 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_E_MSKINTR 0x1
25811 
25812 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field. */
25813 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_LSB 16
25814 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field. */
25815 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_MSB 16
25816 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field. */
25817 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_WIDTH 1
25818 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field value. */
25819 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_SET_MSK 0x00010000
25820 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field value. */
25821 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_CLR_MSK 0xfffeffff
25822 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field. */
25823 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_RESET 0x0
25824 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM field value from a register. */
25825 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_GET(value) (((value) & 0x00010000) >> 16)
25826 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field value suitable for setting the register. */
25827 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_SET(value) (((value) << 16) & 0x00010000)
25828 
25829 /*
25830  * Field : MMC Receive IPV4 Header Error Octet Counter Interrupt Mask - rxipv4heroim
25831  *
25832  * Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter
25833  * reaches half of the maximum value or the maximum value.
25834  *
25835  * Field Enumeration Values:
25836  *
25837  * Enum | Value | Description
25838  * :--------------------------------------------------------|:------|:------------
25839  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_E_NOMSKINTR | 0x0 |
25840  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_E_MSKINTR | 0x1 |
25841  *
25842  * Field Access Macros:
25843  *
25844  */
25845 /*
25846  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM
25847  *
25848  */
25849 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_E_NOMSKINTR 0x0
25850 /*
25851  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM
25852  *
25853  */
25854 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_E_MSKINTR 0x1
25855 
25856 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field. */
25857 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_LSB 17
25858 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field. */
25859 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_MSB 17
25860 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field. */
25861 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_WIDTH 1
25862 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field value. */
25863 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_SET_MSK 0x00020000
25864 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field value. */
25865 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_CLR_MSK 0xfffdffff
25866 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field. */
25867 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_RESET 0x0
25868 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM field value from a register. */
25869 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_GET(value) (((value) & 0x00020000) >> 17)
25870 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field value suitable for setting the register. */
25871 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_SET(value) (((value) << 17) & 0x00020000)
25872 
25873 /*
25874  * Field : MMC Receive IPV4 No Payload Octet Counter Interrupt Mask - rxipv4nopayoim
25875  *
25876  * Setting this bit masks the interrupt when the rxipv4_nopay_octets counter
25877  * reaches half of the maximum value or the maximum value.
25878  *
25879  * Field Enumeration Values:
25880  *
25881  * Enum | Value | Description
25882  * :----------------------------------------------------------|:------|:------------
25883  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_E_NOMSKINTR | 0x0 |
25884  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_E_MSKINTR | 0x1 |
25885  *
25886  * Field Access Macros:
25887  *
25888  */
25889 /*
25890  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM
25891  *
25892  */
25893 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_E_NOMSKINTR 0x0
25894 /*
25895  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM
25896  *
25897  */
25898 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_E_MSKINTR 0x1
25899 
25900 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field. */
25901 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_LSB 18
25902 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field. */
25903 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_MSB 18
25904 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field. */
25905 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_WIDTH 1
25906 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field value. */
25907 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_SET_MSK 0x00040000
25908 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field value. */
25909 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_CLR_MSK 0xfffbffff
25910 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field. */
25911 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_RESET 0x0
25912 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM field value from a register. */
25913 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_GET(value) (((value) & 0x00040000) >> 18)
25914 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field value suitable for setting the register. */
25915 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_SET(value) (((value) << 18) & 0x00040000)
25916 
25917 /*
25918  * Field : MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask - rxipv4fragoim
25919  *
25920  * Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches
25921  * half of the maximum value or the maximum value.
25922  *
25923  * Field Enumeration Values:
25924  *
25925  * Enum | Value | Description
25926  * :---------------------------------------------------------|:------|:------------
25927  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_E_NOMSKINTR | 0x0 |
25928  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_E_MSKINTR | 0x1 |
25929  *
25930  * Field Access Macros:
25931  *
25932  */
25933 /*
25934  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM
25935  *
25936  */
25937 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_E_NOMSKINTR 0x0
25938 /*
25939  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM
25940  *
25941  */
25942 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_E_MSKINTR 0x1
25943 
25944 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field. */
25945 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_LSB 19
25946 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field. */
25947 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_MSB 19
25948 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field. */
25949 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_WIDTH 1
25950 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field value. */
25951 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_SET_MSK 0x00080000
25952 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field value. */
25953 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_CLR_MSK 0xfff7ffff
25954 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field. */
25955 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_RESET 0x0
25956 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM field value from a register. */
25957 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_GET(value) (((value) & 0x00080000) >> 19)
25958 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field value suitable for setting the register. */
25959 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_SET(value) (((value) << 19) & 0x00080000)
25960 
25961 /*
25962  * Field : MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask - rxipv4udsbloim
25963  *
25964  * Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter
25965  * reaches half of the maximum value or the maximum value.
25966  *
25967  * Field Enumeration Values:
25968  *
25969  * Enum | Value | Description
25970  * :----------------------------------------------------------|:------|:------------
25971  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_E_NOMSKINTR | 0x0 |
25972  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_E_MSKINTR | 0x1 |
25973  *
25974  * Field Access Macros:
25975  *
25976  */
25977 /*
25978  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM
25979  *
25980  */
25981 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_E_NOMSKINTR 0x0
25982 /*
25983  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM
25984  *
25985  */
25986 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_E_MSKINTR 0x1
25987 
25988 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field. */
25989 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_LSB 20
25990 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field. */
25991 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_MSB 20
25992 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field. */
25993 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_WIDTH 1
25994 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field value. */
25995 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_SET_MSK 0x00100000
25996 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field value. */
25997 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_CLR_MSK 0xffefffff
25998 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field. */
25999 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_RESET 0x0
26000 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM field value from a register. */
26001 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_GET(value) (((value) & 0x00100000) >> 20)
26002 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field value suitable for setting the register. */
26003 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_SET(value) (((value) << 20) & 0x00100000)
26004 
26005 /*
26006  * Field : MMC Receive IPV6 Good Octet Counter Interrupt Mask - rxipv6goim
26007  *
26008  * Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches
26009  * half of the maximum value or the maximum value.
26010  *
26011  * Field Enumeration Values:
26012  *
26013  * Enum | Value | Description
26014  * :------------------------------------------------------|:------|:------------
26015  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_E_NOMSKINTR | 0x0 |
26016  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_E_MSKINTR | 0x1 |
26017  *
26018  * Field Access Macros:
26019  *
26020  */
26021 /*
26022  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM
26023  *
26024  */
26025 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_E_NOMSKINTR 0x0
26026 /*
26027  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM
26028  *
26029  */
26030 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_E_MSKINTR 0x1
26031 
26032 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field. */
26033 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_LSB 21
26034 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field. */
26035 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_MSB 21
26036 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field. */
26037 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_WIDTH 1
26038 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field value. */
26039 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_SET_MSK 0x00200000
26040 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field value. */
26041 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_CLR_MSK 0xffdfffff
26042 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field. */
26043 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_RESET 0x0
26044 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM field value from a register. */
26045 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_GET(value) (((value) & 0x00200000) >> 21)
26046 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field value suitable for setting the register. */
26047 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_SET(value) (((value) << 21) & 0x00200000)
26048 
26049 /*
26050  * Field : MMC Receive IPV6 Header Error Octet Counter Interrupt Mask - rxipv6heroim
26051  *
26052  * Setting this bit masks interrupt when the rxipv6_hdrerr_octets counter reaches
26053  * half of the maximum value or the maximum value.
26054  *
26055  * Field Enumeration Values:
26056  *
26057  * Enum | Value | Description
26058  * :--------------------------------------------------------|:------|:------------
26059  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_E_NOMSKINTR | 0x0 |
26060  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_E_MSKINTR | 0x1 |
26061  *
26062  * Field Access Macros:
26063  *
26064  */
26065 /*
26066  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM
26067  *
26068  */
26069 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_E_NOMSKINTR 0x0
26070 /*
26071  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM
26072  *
26073  */
26074 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_E_MSKINTR 0x1
26075 
26076 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field. */
26077 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_LSB 22
26078 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field. */
26079 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_MSB 22
26080 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field. */
26081 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_WIDTH 1
26082 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field value. */
26083 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_SET_MSK 0x00400000
26084 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field value. */
26085 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_CLR_MSK 0xffbfffff
26086 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field. */
26087 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_RESET 0x0
26088 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM field value from a register. */
26089 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_GET(value) (((value) & 0x00400000) >> 22)
26090 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field value suitable for setting the register. */
26091 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_SET(value) (((value) << 22) & 0x00400000)
26092 
26093 /*
26094  * Field : MMC Receive IPV6 No Payload Octet Counter Interrupt Mask - rxipv6nopayoim
26095  *
26096  * Setting this bit masks the interrupt when the rxipv6_nopay_octets counter
26097  * reaches half of the maximum value or the maximum value.
26098  *
26099  * Field Enumeration Values:
26100  *
26101  * Enum | Value | Description
26102  * :----------------------------------------------------------|:------|:------------
26103  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_E_NOMSKINTR | 0x0 |
26104  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_E_MSKINTR | 0x1 |
26105  *
26106  * Field Access Macros:
26107  *
26108  */
26109 /*
26110  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM
26111  *
26112  */
26113 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_E_NOMSKINTR 0x0
26114 /*
26115  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM
26116  *
26117  */
26118 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_E_MSKINTR 0x1
26119 
26120 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field. */
26121 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_LSB 23
26122 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field. */
26123 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_MSB 23
26124 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field. */
26125 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_WIDTH 1
26126 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field value. */
26127 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_SET_MSK 0x00800000
26128 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field value. */
26129 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_CLR_MSK 0xff7fffff
26130 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field. */
26131 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_RESET 0x0
26132 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM field value from a register. */
26133 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_GET(value) (((value) & 0x00800000) >> 23)
26134 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field value suitable for setting the register. */
26135 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_SET(value) (((value) << 23) & 0x00800000)
26136 
26137 /*
26138  * Field : MMC Receive UDP Good Octet Counter Interrupt Mask - rxudpgoim
26139  *
26140  * Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches
26141  * half of the maximum value or the maximum value.
26142  *
26143  * Field Enumeration Values:
26144  *
26145  * Enum | Value | Description
26146  * :-----------------------------------------------------|:------|:------------
26147  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_E_NOMSKINTR | 0x0 |
26148  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_E_MSKINTR | 0x1 |
26149  *
26150  * Field Access Macros:
26151  *
26152  */
26153 /*
26154  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM
26155  *
26156  */
26157 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_E_NOMSKINTR 0x0
26158 /*
26159  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM
26160  *
26161  */
26162 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_E_MSKINTR 0x1
26163 
26164 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field. */
26165 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_LSB 24
26166 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field. */
26167 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_MSB 24
26168 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field. */
26169 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_WIDTH 1
26170 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field value. */
26171 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_SET_MSK 0x01000000
26172 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field value. */
26173 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_CLR_MSK 0xfeffffff
26174 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field. */
26175 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_RESET 0x0
26176 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM field value from a register. */
26177 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_GET(value) (((value) & 0x01000000) >> 24)
26178 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field value suitable for setting the register. */
26179 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_SET(value) (((value) << 24) & 0x01000000)
26180 
26181 /*
26182  * Field : MMC Receive UDP Error Octet Counter Interrupt Mask - rxudperoim
26183  *
26184  * Setting this bit masks the interrupt when the rxudp_err_octets counter reaches
26185  * half of the maximum value or the maximum value.
26186  *
26187  * Field Enumeration Values:
26188  *
26189  * Enum | Value | Description
26190  * :------------------------------------------------------|:------|:------------
26191  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_E_NOMSKINTR | 0x0 |
26192  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_E_MSKINTR | 0x1 |
26193  *
26194  * Field Access Macros:
26195  *
26196  */
26197 /*
26198  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM
26199  *
26200  */
26201 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_E_NOMSKINTR 0x0
26202 /*
26203  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM
26204  *
26205  */
26206 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_E_MSKINTR 0x1
26207 
26208 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field. */
26209 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_LSB 25
26210 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field. */
26211 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_MSB 25
26212 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field. */
26213 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_WIDTH 1
26214 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field value. */
26215 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_SET_MSK 0x02000000
26216 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field value. */
26217 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_CLR_MSK 0xfdffffff
26218 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field. */
26219 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_RESET 0x0
26220 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM field value from a register. */
26221 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_GET(value) (((value) & 0x02000000) >> 25)
26222 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field value suitable for setting the register. */
26223 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_SET(value) (((value) << 25) & 0x02000000)
26224 
26225 /*
26226  * Field : MMC Receive TCP Good Octet Counter Interrupt Mask - rxtcpgoim
26227  *
26228  * Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches
26229  * half of the maximum value or the maximum value.
26230  *
26231  * Field Enumeration Values:
26232  *
26233  * Enum | Value | Description
26234  * :-----------------------------------------------------|:------|:------------
26235  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_E_NOMSKINTR | 0x0 |
26236  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_E_MSKINTR | 0x1 |
26237  *
26238  * Field Access Macros:
26239  *
26240  */
26241 /*
26242  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM
26243  *
26244  */
26245 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_E_NOMSKINTR 0x0
26246 /*
26247  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM
26248  *
26249  */
26250 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_E_MSKINTR 0x1
26251 
26252 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field. */
26253 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_LSB 26
26254 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field. */
26255 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_MSB 26
26256 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field. */
26257 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_WIDTH 1
26258 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field value. */
26259 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_SET_MSK 0x04000000
26260 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field value. */
26261 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_CLR_MSK 0xfbffffff
26262 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field. */
26263 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_RESET 0x0
26264 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM field value from a register. */
26265 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_GET(value) (((value) & 0x04000000) >> 26)
26266 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field value suitable for setting the register. */
26267 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_SET(value) (((value) << 26) & 0x04000000)
26268 
26269 /*
26270  * Field : MMC Receive TCP Error Octet Counter Interrupt Mask - rxtcperoim
26271  *
26272  * Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches
26273  * half of the maximum value or the maximum value.
26274  *
26275  * Field Enumeration Values:
26276  *
26277  * Enum | Value | Description
26278  * :------------------------------------------------------|:------|:------------
26279  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_E_NOMSKINTR | 0x0 |
26280  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_E_MSKINTR | 0x1 |
26281  *
26282  * Field Access Macros:
26283  *
26284  */
26285 /*
26286  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM
26287  *
26288  */
26289 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_E_NOMSKINTR 0x0
26290 /*
26291  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM
26292  *
26293  */
26294 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_E_MSKINTR 0x1
26295 
26296 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field. */
26297 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_LSB 27
26298 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field. */
26299 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_MSB 27
26300 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field. */
26301 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_WIDTH 1
26302 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field value. */
26303 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_SET_MSK 0x08000000
26304 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field value. */
26305 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_CLR_MSK 0xf7ffffff
26306 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field. */
26307 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_RESET 0x0
26308 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM field value from a register. */
26309 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_GET(value) (((value) & 0x08000000) >> 27)
26310 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field value suitable for setting the register. */
26311 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_SET(value) (((value) << 27) & 0x08000000)
26312 
26313 /*
26314  * Field : MMC Receive ICMP Good Octet Counter Interrupt Mask - rxicmpgoim
26315  *
26316  * Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches
26317  * half of the maximum value or the maximum value.
26318  *
26319  * Field Enumeration Values:
26320  *
26321  * Enum | Value | Description
26322  * :------------------------------------------------------|:------|:------------
26323  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_E_NOMSKINTR | 0x0 |
26324  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_E_MSKINTR | 0x1 |
26325  *
26326  * Field Access Macros:
26327  *
26328  */
26329 /*
26330  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM
26331  *
26332  */
26333 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_E_NOMSKINTR 0x0
26334 /*
26335  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM
26336  *
26337  */
26338 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_E_MSKINTR 0x1
26339 
26340 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field. */
26341 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_LSB 28
26342 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field. */
26343 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_MSB 28
26344 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field. */
26345 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_WIDTH 1
26346 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field value. */
26347 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_SET_MSK 0x10000000
26348 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field value. */
26349 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_CLR_MSK 0xefffffff
26350 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field. */
26351 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_RESET 0x0
26352 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM field value from a register. */
26353 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_GET(value) (((value) & 0x10000000) >> 28)
26354 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field value suitable for setting the register. */
26355 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_SET(value) (((value) << 28) & 0x10000000)
26356 
26357 /*
26358  * Field : MMC Receive ICMP Error Octet Counter Interrupt Mask - rxicmperoim
26359  *
26360  * Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches
26361  * half of the maximum value or the maximum value.
26362  *
26363  * Field Enumeration Values:
26364  *
26365  * Enum | Value | Description
26366  * :-------------------------------------------------------|:------|:------------
26367  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_E_NOMSKINTR | 0x0 |
26368  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_E_MSKINTR | 0x1 |
26369  *
26370  * Field Access Macros:
26371  *
26372  */
26373 /*
26374  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM
26375  *
26376  */
26377 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_E_NOMSKINTR 0x0
26378 /*
26379  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM
26380  *
26381  */
26382 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_E_MSKINTR 0x1
26383 
26384 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field. */
26385 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_LSB 29
26386 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field. */
26387 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_MSB 29
26388 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field. */
26389 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_WIDTH 1
26390 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field value. */
26391 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_SET_MSK 0x20000000
26392 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field value. */
26393 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_CLR_MSK 0xdfffffff
26394 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field. */
26395 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_RESET 0x0
26396 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM field value from a register. */
26397 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_GET(value) (((value) & 0x20000000) >> 29)
26398 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field value suitable for setting the register. */
26399 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_SET(value) (((value) << 29) & 0x20000000)
26400 
26401 #ifndef __ASSEMBLY__
26402 /*
26403  * WARNING: The C register and register group struct declarations are provided for
26404  * convenience and illustrative purposes. They should, however, be used with
26405  * caution as the C language standard provides no guarantees about the alignment or
26406  * atomicity of device memory accesses. The recommended practice for writing
26407  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
26408  * alt_write_word() functions.
26409  *
26410  * The struct declaration for register ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK.
26411  */
26412 struct ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_s
26413 {
26414  uint32_t rxipv4gfim : 1; /* MMC Receive IPV4 Good Frame Counter Interrupt Mask */
26415  uint32_t rxipv4herfim : 1; /* MMC Receive IPV4 Header Error Frame Counter Interrupt Mask */
26416  uint32_t rxipv4nopayfim : 1; /* MMC Receive IPV4 No Payload Frame Counter Interrupt Mask */
26417  uint32_t rxipv4fragfim : 1; /* MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask */
26418  uint32_t rxipv4udsblfim : 1; /* MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask */
26419  uint32_t rxipv6gfim : 1; /* MMC Receive IPV6 Good Frame Counter Interrupt Mask */
26420  uint32_t rxipv6herfim : 1; /* MMC Receive IPV6 Header Error Frame Counter Interrupt Mask */
26421  uint32_t rxipv6nopayfim : 1; /* MMC Receive IPV6 No Payload Frame Counter Interrupt Mask */
26422  uint32_t rxudpgfim : 1; /* MMC Receive UDP Good Frame Counter Interrupt Mask */
26423  uint32_t rxudperfim : 1; /* MMC Receive UDP Error Frame Counter Interrupt Mask */
26424  uint32_t rxtcpgfim : 1; /* MMC Receive TCP Good Frame Counter Interrupt Mask */
26425  uint32_t rxtcperfim : 1; /* MMC Receive TCP Error Frame Counter Interrupt Mask */
26426  uint32_t rxicmpgfim : 1; /* MMC Receive ICMP Good Frame Counter Interrupt Mask */
26427  uint32_t rxicmperfim : 1; /* MMC Receive ICMP Error Frame Counter Interrupt Mask */
26428  uint32_t : 2; /* *UNDEFINED* */
26429  uint32_t rxipv4goim : 1; /* MMC Receive IPV4 Good Octet Counter Interrupt Mask */
26430  uint32_t rxipv4heroim : 1; /* MMC Receive IPV4 Header Error Octet Counter Interrupt Mask */
26431  uint32_t rxipv4nopayoim : 1; /* MMC Receive IPV4 No Payload Octet Counter Interrupt Mask */
26432  uint32_t rxipv4fragoim : 1; /* MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask */
26433  uint32_t rxipv4udsbloim : 1; /* MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask */
26434  uint32_t rxipv6goim : 1; /* MMC Receive IPV6 Good Octet Counter Interrupt Mask */
26435  uint32_t rxipv6heroim : 1; /* MMC Receive IPV6 Header Error Octet Counter Interrupt Mask */
26436  uint32_t rxipv6nopayoim : 1; /* MMC Receive IPV6 No Payload Octet Counter Interrupt Mask */
26437  uint32_t rxudpgoim : 1; /* MMC Receive UDP Good Octet Counter Interrupt Mask */
26438  uint32_t rxudperoim : 1; /* MMC Receive UDP Error Octet Counter Interrupt Mask */
26439  uint32_t rxtcpgoim : 1; /* MMC Receive TCP Good Octet Counter Interrupt Mask */
26440  uint32_t rxtcperoim : 1; /* MMC Receive TCP Error Octet Counter Interrupt Mask */
26441  uint32_t rxicmpgoim : 1; /* MMC Receive ICMP Good Octet Counter Interrupt Mask */
26442  uint32_t rxicmperoim : 1; /* MMC Receive ICMP Error Octet Counter Interrupt Mask */
26443  uint32_t : 2; /* *UNDEFINED* */
26444 };
26445 
26446 /* The typedef declaration for register ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK. */
26447 typedef volatile struct ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_s ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_t;
26448 #endif /* __ASSEMBLY__ */
26449 
26450 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK register. */
26451 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_RESET 0x00000000
26452 /* The byte offset of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK register from the beginning of the component. */
26453 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_OFST 0x200
26454 /* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK register. */
26455 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_OFST))
26456 
26457 /*
26458  * Register : Register 130 (MMC Receive Checksum Offload Interrupt Register) - gmacgrp_mmc_ipc_receive_interrupt
26459  *
26460  * This register maintains the interrupts generated when receive IPC statistic
26461  * counters reach half their maximum values (0x8000_0000 for 32-bit counter and
26462  * 0x8000 for 16-bit counter), and when they cross their maximum values
26463  * (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter
26464  * Stop Rollover is set, then interrupts are set but the counter remains at all-
26465  * ones. The MMC Receive Checksum Offload Interrupt register is 32-bits wide. When
26466  * the MMC IPC counter that caused the interrupt is read, its corresponding
26467  * interrupt bit is cleared. The counter's least-significant byte lane (bits[7:0])
26468  * must be read to clear the interrupt bit.
26469  *
26470  * Register Layout
26471  *
26472  * Bits | Access | Reset | Description
26473  * :--------|:-------|:------|:----------------------------------------------------------------------
26474  * [0] | R | 0x0 | MMC Receive IPV4 Good Frame Counter Interrupt Status
26475  * [1] | R | 0x0 | MMC Receive IPV4 Header Error Frame Counter Interrupt Status
26476  * [2] | R | 0x0 | MMC Receive IPV4 No Payload Frame Counter Interrupt Status
26477  * [3] | R | 0x0 | MMC Receive IPV4 Fragmented Frame Counter Interrupt Status
26478  * [4] | R | 0x0 | MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status
26479  * [5] | R | 0x0 | MMC Receive IPV6 Good Frame Counter Interrupt Status
26480  * [6] | R | 0x0 | MMC Receive IPV6 Header Error Frame Counter Interrupt Status
26481  * [7] | R | 0x0 | MMC Receive IPV6 No Payload Frame Counter Interrupt Status
26482  * [8] | R | 0x0 | MMC Receive UDP Good Frame Counter Interrupt Status
26483  * [9] | R | 0x0 | MMC Receive UDP Error Frame Counter Interrupt Status
26484  * [10] | R | 0x0 | MMC Receive TCP Good Frame Counter Interrupt Status
26485  * [11] | R | 0x0 | MMC Receive TCP Error Frame Counter Interrupt Status
26486  * [12] | R | 0x0 | MMC Receive ICMP Good Frame Counter Interrupt Status
26487  * [13] | R | 0x0 | MMC Receive ICMP Error Frame Counter Interrupt Status
26488  * [15:14] | ??? | 0x0 | *UNDEFINED*
26489  * [16] | R | 0x0 | MMC Receive IPV4 Good Octet Counter Interrupt Status
26490  * [17] | R | 0x0 | MMC Receive IPV4 Header Error Octet Counter Interrupt Status
26491  * [18] | R | 0x0 | MMC Receive IPV4 No Payload Octet Counter Interrupt Status
26492  * [19] | R | 0x0 | MMC Receive IPV4 Fragmented Octet Counter Interrupt Status
26493  * [20] | R | 0x0 | MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status
26494  * [21] | R | 0x0 | MMC Receive IPV6 Good Octet Counter Interrupt Status
26495  * [22] | R | 0x0 | MMC Receive IPV6 Header Error Octet Counter Interrupt Status
26496  * [23] | R | 0x0 | MMC Receive IPV6 No Payload Octet Counter Interrupt Status
26497  * [24] | R | 0x0 | MMC Receive UDP Good Octet Counter Interrupt Status
26498  * [25] | R | 0x0 | MMC Receive UDP Error Octet Counter Interrupt Status
26499  * [26] | R | 0x0 | MMC Receive TCP Good Octet Counter Interrupt Status
26500  * [27] | R | 0x0 | MMC Receive TCP Error Octet Counter Interrupt Status
26501  * [28] | R | 0x0 | MMC Receive ICMP Good Octet Counter Interrupt Status
26502  * [29] | R | 0x0 | MMC Receive ICMP Error Octet Counter Interrupt Status
26503  * [31:30] | ??? | 0x0 | *UNDEFINED*
26504  *
26505  */
26506 /*
26507  * Field : MMC Receive IPV4 Good Frame Counter Interrupt Status - rxipv4gfis
26508  *
26509  * This bit is set when the rxipv4_gd_frms counter reaches half of the maximum
26510  * value or the maximum value.
26511  *
26512  * Field Enumeration Values:
26513  *
26514  * Enum | Value | Description
26515  * :-----------------------------------------------|:------|:------------
26516  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_E_NOINT | 0x0 |
26517  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_E_INTERR | 0x1 |
26518  *
26519  * Field Access Macros:
26520  *
26521  */
26522 /*
26523  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS
26524  *
26525  */
26526 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_E_NOINT 0x0
26527 /*
26528  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS
26529  *
26530  */
26531 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_E_INTERR 0x1
26532 
26533 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field. */
26534 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_LSB 0
26535 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field. */
26536 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_MSB 0
26537 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field. */
26538 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_WIDTH 1
26539 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field value. */
26540 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_SET_MSK 0x00000001
26541 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field value. */
26542 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_CLR_MSK 0xfffffffe
26543 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field. */
26544 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_RESET 0x0
26545 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS field value from a register. */
26546 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_GET(value) (((value) & 0x00000001) >> 0)
26547 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field value suitable for setting the register. */
26548 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_SET(value) (((value) << 0) & 0x00000001)
26549 
26550 /*
26551  * Field : MMC Receive IPV4 Header Error Frame Counter Interrupt Status - rxipv4herfis
26552  *
26553  * This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum
26554  * value or the maximum value.
26555  *
26556  * Field Enumeration Values:
26557  *
26558  * Enum | Value | Description
26559  * :-------------------------------------------------|:------|:------------
26560  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_E_NOINT | 0x0 |
26561  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_E_INTERR | 0x1 |
26562  *
26563  * Field Access Macros:
26564  *
26565  */
26566 /*
26567  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS
26568  *
26569  */
26570 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_E_NOINT 0x0
26571 /*
26572  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS
26573  *
26574  */
26575 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_E_INTERR 0x1
26576 
26577 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field. */
26578 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_LSB 1
26579 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field. */
26580 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_MSB 1
26581 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field. */
26582 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_WIDTH 1
26583 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field value. */
26584 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_SET_MSK 0x00000002
26585 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field value. */
26586 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_CLR_MSK 0xfffffffd
26587 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field. */
26588 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_RESET 0x0
26589 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS field value from a register. */
26590 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_GET(value) (((value) & 0x00000002) >> 1)
26591 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field value suitable for setting the register. */
26592 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_SET(value) (((value) << 1) & 0x00000002)
26593 
26594 /*
26595  * Field : MMC Receive IPV4 No Payload Frame Counter Interrupt Status - rxipv4nopayfis
26596  *
26597  * This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum
26598  * value or the maximum value.
26599  *
26600  * Field Enumeration Values:
26601  *
26602  * Enum | Value | Description
26603  * :---------------------------------------------------|:------|:------------
26604  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_E_NOINT | 0x0 |
26605  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_E_INTERR | 0x1 |
26606  *
26607  * Field Access Macros:
26608  *
26609  */
26610 /*
26611  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS
26612  *
26613  */
26614 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_E_NOINT 0x0
26615 /*
26616  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS
26617  *
26618  */
26619 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_E_INTERR 0x1
26620 
26621 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field. */
26622 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_LSB 2
26623 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field. */
26624 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_MSB 2
26625 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field. */
26626 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_WIDTH 1
26627 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field value. */
26628 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_SET_MSK 0x00000004
26629 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field value. */
26630 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_CLR_MSK 0xfffffffb
26631 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field. */
26632 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_RESET 0x0
26633 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS field value from a register. */
26634 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_GET(value) (((value) & 0x00000004) >> 2)
26635 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field value suitable for setting the register. */
26636 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_SET(value) (((value) << 2) & 0x00000004)
26637 
26638 /*
26639  * Field : MMC Receive IPV4 Fragmented Frame Counter Interrupt Status - rxipv4fragfis
26640  *
26641  * This bit is set when the rxipv4_frag_frms counter reaches half of the maximum
26642  * value or the maximum value.
26643  *
26644  * Field Enumeration Values:
26645  *
26646  * Enum | Value | Description
26647  * :--------------------------------------------------|:------|:------------
26648  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_E_NOINT | 0x0 |
26649  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_E_INTERR | 0x1 |
26650  *
26651  * Field Access Macros:
26652  *
26653  */
26654 /*
26655  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS
26656  *
26657  */
26658 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_E_NOINT 0x0
26659 /*
26660  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS
26661  *
26662  */
26663 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_E_INTERR 0x1
26664 
26665 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field. */
26666 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_LSB 3
26667 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field. */
26668 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_MSB 3
26669 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field. */
26670 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_WIDTH 1
26671 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field value. */
26672 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_SET_MSK 0x00000008
26673 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field value. */
26674 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_CLR_MSK 0xfffffff7
26675 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field. */
26676 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_RESET 0x0
26677 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS field value from a register. */
26678 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_GET(value) (((value) & 0x00000008) >> 3)
26679 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field value suitable for setting the register. */
26680 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_SET(value) (((value) << 3) & 0x00000008)
26681 
26682 /*
26683  * Field : MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status - rxipv4udsblfis
26684  *
26685  * This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum
26686  * value or the maximum value.
26687  *
26688  * Field Enumeration Values:
26689  *
26690  * Enum | Value | Description
26691  * :---------------------------------------------------|:------|:------------
26692  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_E_NOINT | 0x0 |
26693  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_E_INTERR | 0x1 |
26694  *
26695  * Field Access Macros:
26696  *
26697  */
26698 /*
26699  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS
26700  *
26701  */
26702 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_E_NOINT 0x0
26703 /*
26704  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS
26705  *
26706  */
26707 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_E_INTERR 0x1
26708 
26709 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field. */
26710 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_LSB 4
26711 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field. */
26712 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_MSB 4
26713 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field. */
26714 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_WIDTH 1
26715 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field value. */
26716 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_SET_MSK 0x00000010
26717 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field value. */
26718 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_CLR_MSK 0xffffffef
26719 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field. */
26720 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_RESET 0x0
26721 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS field value from a register. */
26722 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_GET(value) (((value) & 0x00000010) >> 4)
26723 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field value suitable for setting the register. */
26724 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_SET(value) (((value) << 4) & 0x00000010)
26725 
26726 /*
26727  * Field : MMC Receive IPV6 Good Frame Counter Interrupt Status - rxipv6gfis
26728  *
26729  * This bit is set when the rxipv6_gd_frms counter reaches half of the maximum
26730  * value or the maximum value.
26731  *
26732  * Field Enumeration Values:
26733  *
26734  * Enum | Value | Description
26735  * :-----------------------------------------------|:------|:------------
26736  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_E_NOINT | 0x0 |
26737  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_E_INTERR | 0x1 |
26738  *
26739  * Field Access Macros:
26740  *
26741  */
26742 /*
26743  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS
26744  *
26745  */
26746 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_E_NOINT 0x0
26747 /*
26748  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS
26749  *
26750  */
26751 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_E_INTERR 0x1
26752 
26753 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field. */
26754 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_LSB 5
26755 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field. */
26756 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_MSB 5
26757 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field. */
26758 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_WIDTH 1
26759 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field value. */
26760 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_SET_MSK 0x00000020
26761 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field value. */
26762 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_CLR_MSK 0xffffffdf
26763 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field. */
26764 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_RESET 0x0
26765 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS field value from a register. */
26766 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_GET(value) (((value) & 0x00000020) >> 5)
26767 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field value suitable for setting the register. */
26768 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_SET(value) (((value) << 5) & 0x00000020)
26769 
26770 /*
26771  * Field : MMC Receive IPV6 Header Error Frame Counter Interrupt Status - rxipv6herfis
26772  *
26773  * This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum
26774  * value or the maximum value.
26775  *
26776  * Field Enumeration Values:
26777  *
26778  * Enum | Value | Description
26779  * :-------------------------------------------------|:------|:------------
26780  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_E_NOINT | 0x0 |
26781  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_E_INTERR | 0x1 |
26782  *
26783  * Field Access Macros:
26784  *
26785  */
26786 /*
26787  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS
26788  *
26789  */
26790 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_E_NOINT 0x0
26791 /*
26792  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS
26793  *
26794  */
26795 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_E_INTERR 0x1
26796 
26797 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field. */
26798 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_LSB 6
26799 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field. */
26800 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_MSB 6
26801 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field. */
26802 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_WIDTH 1
26803 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field value. */
26804 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_SET_MSK 0x00000040
26805 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field value. */
26806 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_CLR_MSK 0xffffffbf
26807 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field. */
26808 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_RESET 0x0
26809 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS field value from a register. */
26810 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_GET(value) (((value) & 0x00000040) >> 6)
26811 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field value suitable for setting the register. */
26812 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_SET(value) (((value) << 6) & 0x00000040)
26813 
26814 /*
26815  * Field : MMC Receive IPV6 No Payload Frame Counter Interrupt Status - rxipv6nopayfis
26816  *
26817  * This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum
26818  * value or the maximum value.
26819  *
26820  * Field Enumeration Values:
26821  *
26822  * Enum | Value | Description
26823  * :---------------------------------------------------|:------|:------------
26824  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_E_NOINT | 0x0 |
26825  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_E_INTERR | 0x1 |
26826  *
26827  * Field Access Macros:
26828  *
26829  */
26830 /*
26831  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS
26832  *
26833  */
26834 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_E_NOINT 0x0
26835 /*
26836  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS
26837  *
26838  */
26839 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_E_INTERR 0x1
26840 
26841 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field. */
26842 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_LSB 7
26843 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field. */
26844 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_MSB 7
26845 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field. */
26846 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_WIDTH 1
26847 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field value. */
26848 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_SET_MSK 0x00000080
26849 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field value. */
26850 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_CLR_MSK 0xffffff7f
26851 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field. */
26852 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_RESET 0x0
26853 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS field value from a register. */
26854 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_GET(value) (((value) & 0x00000080) >> 7)
26855 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field value suitable for setting the register. */
26856 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_SET(value) (((value) << 7) & 0x00000080)
26857 
26858 /*
26859  * Field : MMC Receive UDP Good Frame Counter Interrupt Status - rxudpgfis
26860  *
26861  * This bit is set when the rxudp_gd_frms counter reaches half of the maximum value
26862  * or the maximum value.
26863  *
26864  * Field Enumeration Values:
26865  *
26866  * Enum | Value | Description
26867  * :----------------------------------------------|:------|:------------
26868  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_E_NOINT | 0x0 |
26869  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_E_INTERR | 0x1 |
26870  *
26871  * Field Access Macros:
26872  *
26873  */
26874 /*
26875  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS
26876  *
26877  */
26878 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_E_NOINT 0x0
26879 /*
26880  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS
26881  *
26882  */
26883 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_E_INTERR 0x1
26884 
26885 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field. */
26886 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_LSB 8
26887 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field. */
26888 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_MSB 8
26889 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field. */
26890 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_WIDTH 1
26891 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field value. */
26892 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_SET_MSK 0x00000100
26893 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field value. */
26894 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_CLR_MSK 0xfffffeff
26895 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field. */
26896 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_RESET 0x0
26897 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS field value from a register. */
26898 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_GET(value) (((value) & 0x00000100) >> 8)
26899 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field value suitable for setting the register. */
26900 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_SET(value) (((value) << 8) & 0x00000100)
26901 
26902 /*
26903  * Field : MMC Receive UDP Error Frame Counter Interrupt Status - rxudperfis
26904  *
26905  * This bit is set when the rxudp_err_frms counter reaches half of the maximum
26906  * value or the maximum value.
26907  *
26908  * Field Enumeration Values:
26909  *
26910  * Enum | Value | Description
26911  * :-----------------------------------------------|:------|:------------
26912  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_E_NOINT | 0x0 |
26913  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_E_INTERR | 0x1 |
26914  *
26915  * Field Access Macros:
26916  *
26917  */
26918 /*
26919  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS
26920  *
26921  */
26922 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_E_NOINT 0x0
26923 /*
26924  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS
26925  *
26926  */
26927 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_E_INTERR 0x1
26928 
26929 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field. */
26930 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_LSB 9
26931 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field. */
26932 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_MSB 9
26933 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field. */
26934 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_WIDTH 1
26935 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field value. */
26936 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_SET_MSK 0x00000200
26937 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field value. */
26938 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_CLR_MSK 0xfffffdff
26939 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field. */
26940 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_RESET 0x0
26941 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS field value from a register. */
26942 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_GET(value) (((value) & 0x00000200) >> 9)
26943 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field value suitable for setting the register. */
26944 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_SET(value) (((value) << 9) & 0x00000200)
26945 
26946 /*
26947  * Field : MMC Receive TCP Good Frame Counter Interrupt Status - rxtcpgfis
26948  *
26949  * This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value
26950  * or the maximum value.
26951  *
26952  * Field Enumeration Values:
26953  *
26954  * Enum | Value | Description
26955  * :----------------------------------------------|:------|:------------
26956  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_E_NOINT | 0x0 |
26957  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_E_INTERR | 0x1 |
26958  *
26959  * Field Access Macros:
26960  *
26961  */
26962 /*
26963  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS
26964  *
26965  */
26966 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_E_NOINT 0x0
26967 /*
26968  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS
26969  *
26970  */
26971 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_E_INTERR 0x1
26972 
26973 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field. */
26974 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_LSB 10
26975 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field. */
26976 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_MSB 10
26977 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field. */
26978 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_WIDTH 1
26979 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field value. */
26980 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_SET_MSK 0x00000400
26981 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field value. */
26982 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_CLR_MSK 0xfffffbff
26983 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field. */
26984 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_RESET 0x0
26985 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS field value from a register. */
26986 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_GET(value) (((value) & 0x00000400) >> 10)
26987 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field value suitable for setting the register. */
26988 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_SET(value) (((value) << 10) & 0x00000400)
26989 
26990 /*
26991  * Field : MMC Receive TCP Error Frame Counter Interrupt Status - rxtcperfis
26992  *
26993  * This bit is set when the rxtcp_err_frms counter reaches half of the maximum
26994  * value or the maximum value.
26995  *
26996  * Field Enumeration Values:
26997  *
26998  * Enum | Value | Description
26999  * :-----------------------------------------------|:------|:------------
27000  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_E_NOINT | 0x0 |
27001  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_E_INTERR | 0x1 |
27002  *
27003  * Field Access Macros:
27004  *
27005  */
27006 /*
27007  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS
27008  *
27009  */
27010 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_E_NOINT 0x0
27011 /*
27012  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS
27013  *
27014  */
27015 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_E_INTERR 0x1
27016 
27017 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field. */
27018 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_LSB 11
27019 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field. */
27020 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_MSB 11
27021 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field. */
27022 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_WIDTH 1
27023 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field value. */
27024 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_SET_MSK 0x00000800
27025 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field value. */
27026 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_CLR_MSK 0xfffff7ff
27027 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field. */
27028 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_RESET 0x0
27029 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS field value from a register. */
27030 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_GET(value) (((value) & 0x00000800) >> 11)
27031 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field value suitable for setting the register. */
27032 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_SET(value) (((value) << 11) & 0x00000800)
27033 
27034 /*
27035  * Field : MMC Receive ICMP Good Frame Counter Interrupt Status - rxicmpgfis
27036  *
27037  * This bit is set when the rxicmp_gd_frms counter reaches half of the maximum
27038  * value or the maximum value.
27039  *
27040  * Field Enumeration Values:
27041  *
27042  * Enum | Value | Description
27043  * :-----------------------------------------------|:------|:------------
27044  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_E_NOINT | 0x0 |
27045  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_E_INTERR | 0x1 |
27046  *
27047  * Field Access Macros:
27048  *
27049  */
27050 /*
27051  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS
27052  *
27053  */
27054 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_E_NOINT 0x0
27055 /*
27056  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS
27057  *
27058  */
27059 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_E_INTERR 0x1
27060 
27061 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field. */
27062 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_LSB 12
27063 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field. */
27064 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_MSB 12
27065 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field. */
27066 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_WIDTH 1
27067 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field value. */
27068 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_SET_MSK 0x00001000
27069 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field value. */
27070 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_CLR_MSK 0xffffefff
27071 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field. */
27072 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_RESET 0x0
27073 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS field value from a register. */
27074 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_GET(value) (((value) & 0x00001000) >> 12)
27075 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field value suitable for setting the register. */
27076 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_SET(value) (((value) << 12) & 0x00001000)
27077 
27078 /*
27079  * Field : MMC Receive ICMP Error Frame Counter Interrupt Status - rxicmperfis
27080  *
27081  * This bit is set when the rxicmp_err_frms counter reaches half of the maximum
27082  * value or the maximum value.
27083  *
27084  * Field Enumeration Values:
27085  *
27086  * Enum | Value | Description
27087  * :------------------------------------------------|:------|:------------
27088  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_E_NOINT | 0x0 |
27089  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_E_INTERR | 0x1 |
27090  *
27091  * Field Access Macros:
27092  *
27093  */
27094 /*
27095  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS
27096  *
27097  */
27098 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_E_NOINT 0x0
27099 /*
27100  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS
27101  *
27102  */
27103 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_E_INTERR 0x1
27104 
27105 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field. */
27106 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_LSB 13
27107 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field. */
27108 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_MSB 13
27109 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field. */
27110 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_WIDTH 1
27111 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field value. */
27112 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_SET_MSK 0x00002000
27113 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field value. */
27114 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_CLR_MSK 0xffffdfff
27115 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field. */
27116 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_RESET 0x0
27117 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS field value from a register. */
27118 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_GET(value) (((value) & 0x00002000) >> 13)
27119 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field value suitable for setting the register. */
27120 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_SET(value) (((value) << 13) & 0x00002000)
27121 
27122 /*
27123  * Field : MMC Receive IPV4 Good Octet Counter Interrupt Status - rxipv4gois
27124  *
27125  * This bit is set when the rxipv4_gd_octets counter reaches half of the maximum
27126  * value or the maximum value.
27127  *
27128  * Field Enumeration Values:
27129  *
27130  * Enum | Value | Description
27131  * :-----------------------------------------------|:------|:------------
27132  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_E_NOINT | 0x0 |
27133  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_E_INTERR | 0x1 |
27134  *
27135  * Field Access Macros:
27136  *
27137  */
27138 /*
27139  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS
27140  *
27141  */
27142 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_E_NOINT 0x0
27143 /*
27144  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS
27145  *
27146  */
27147 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_E_INTERR 0x1
27148 
27149 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field. */
27150 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_LSB 16
27151 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field. */
27152 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_MSB 16
27153 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field. */
27154 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_WIDTH 1
27155 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field value. */
27156 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_SET_MSK 0x00010000
27157 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field value. */
27158 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_CLR_MSK 0xfffeffff
27159 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field. */
27160 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_RESET 0x0
27161 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS field value from a register. */
27162 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_GET(value) (((value) & 0x00010000) >> 16)
27163 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field value suitable for setting the register. */
27164 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_SET(value) (((value) << 16) & 0x00010000)
27165 
27166 /*
27167  * Field : MMC Receive IPV4 Header Error Octet Counter Interrupt Status - rxipv4herois
27168  *
27169  * This bit is set when the rxipv4_hdrerr_octets counter reaches half of the
27170  * maximum value or the maximum value.
27171  *
27172  * Field Enumeration Values:
27173  *
27174  * Enum | Value | Description
27175  * :-------------------------------------------------|:------|:------------
27176  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_E_NOINT | 0x0 |
27177  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_E_INTERR | 0x1 |
27178  *
27179  * Field Access Macros:
27180  *
27181  */
27182 /*
27183  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS
27184  *
27185  */
27186 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_E_NOINT 0x0
27187 /*
27188  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS
27189  *
27190  */
27191 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_E_INTERR 0x1
27192 
27193 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field. */
27194 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_LSB 17
27195 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field. */
27196 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_MSB 17
27197 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field. */
27198 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_WIDTH 1
27199 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field value. */
27200 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_SET_MSK 0x00020000
27201 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field value. */
27202 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_CLR_MSK 0xfffdffff
27203 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field. */
27204 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_RESET 0x0
27205 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS field value from a register. */
27206 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_GET(value) (((value) & 0x00020000) >> 17)
27207 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field value suitable for setting the register. */
27208 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_SET(value) (((value) << 17) & 0x00020000)
27209 
27210 /*
27211  * Field : MMC Receive IPV4 No Payload Octet Counter Interrupt Status - rxipv4nopayois
27212  *
27213  * This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum
27214  * value or the maximum value.
27215  *
27216  * Field Enumeration Values:
27217  *
27218  * Enum | Value | Description
27219  * :---------------------------------------------------|:------|:------------
27220  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_E_NOINT | 0x0 |
27221  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_E_INTERR | 0x1 |
27222  *
27223  * Field Access Macros:
27224  *
27225  */
27226 /*
27227  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS
27228  *
27229  */
27230 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_E_NOINT 0x0
27231 /*
27232  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS
27233  *
27234  */
27235 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_E_INTERR 0x1
27236 
27237 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field. */
27238 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_LSB 18
27239 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field. */
27240 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_MSB 18
27241 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field. */
27242 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_WIDTH 1
27243 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field value. */
27244 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_SET_MSK 0x00040000
27245 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field value. */
27246 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_CLR_MSK 0xfffbffff
27247 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field. */
27248 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_RESET 0x0
27249 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS field value from a register. */
27250 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_GET(value) (((value) & 0x00040000) >> 18)
27251 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field value suitable for setting the register. */
27252 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_SET(value) (((value) << 18) & 0x00040000)
27253 
27254 /*
27255  * Field : MMC Receive IPV4 Fragmented Octet Counter Interrupt Status - rxipv4fragois
27256  *
27257  * This bit is set when the rxipv4_frag_octets counter reaches half of the maximum
27258  * value or the maximum value.
27259  *
27260  * Field Enumeration Values:
27261  *
27262  * Enum | Value | Description
27263  * :--------------------------------------------------|:------|:------------
27264  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_E_NOINT | 0x0 |
27265  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_E_INTERR | 0x1 |
27266  *
27267  * Field Access Macros:
27268  *
27269  */
27270 /*
27271  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS
27272  *
27273  */
27274 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_E_NOINT 0x0
27275 /*
27276  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS
27277  *
27278  */
27279 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_E_INTERR 0x1
27280 
27281 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field. */
27282 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_LSB 19
27283 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field. */
27284 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_MSB 19
27285 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field. */
27286 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_WIDTH 1
27287 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field value. */
27288 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_SET_MSK 0x00080000
27289 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field value. */
27290 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_CLR_MSK 0xfff7ffff
27291 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field. */
27292 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_RESET 0x0
27293 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS field value from a register. */
27294 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_GET(value) (((value) & 0x00080000) >> 19)
27295 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field value suitable for setting the register. */
27296 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_SET(value) (((value) << 19) & 0x00080000)
27297 
27298 /*
27299  * Field : MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status - rxipv4udsblois
27300  *
27301  * This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum
27302  * value or the maximum value.
27303  *
27304  * Field Enumeration Values:
27305  *
27306  * Enum | Value | Description
27307  * :---------------------------------------------------|:------|:------------
27308  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_E_NOINT | 0x0 |
27309  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_E_INTERR | 0x1 |
27310  *
27311  * Field Access Macros:
27312  *
27313  */
27314 /*
27315  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS
27316  *
27317  */
27318 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_E_NOINT 0x0
27319 /*
27320  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS
27321  *
27322  */
27323 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_E_INTERR 0x1
27324 
27325 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field. */
27326 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_LSB 20
27327 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field. */
27328 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_MSB 20
27329 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field. */
27330 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_WIDTH 1
27331 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field value. */
27332 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_SET_MSK 0x00100000
27333 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field value. */
27334 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_CLR_MSK 0xffefffff
27335 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field. */
27336 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_RESET 0x0
27337 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS field value from a register. */
27338 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_GET(value) (((value) & 0x00100000) >> 20)
27339 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field value suitable for setting the register. */
27340 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_SET(value) (((value) << 20) & 0x00100000)
27341 
27342 /*
27343  * Field : MMC Receive IPV6 Good Octet Counter Interrupt Status - rxipv6gois
27344  *
27345  * This bit is set when the rxipv6_gd_octets counter reaches half of the maximum
27346  * value or the maximum value.
27347  *
27348  * Field Enumeration Values:
27349  *
27350  * Enum | Value | Description
27351  * :-----------------------------------------------|:------|:------------
27352  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_E_NOINT | 0x0 |
27353  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_E_INTERR | 0x1 |
27354  *
27355  * Field Access Macros:
27356  *
27357  */
27358 /*
27359  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS
27360  *
27361  */
27362 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_E_NOINT 0x0
27363 /*
27364  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS
27365  *
27366  */
27367 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_E_INTERR 0x1
27368 
27369 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field. */
27370 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_LSB 21
27371 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field. */
27372 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_MSB 21
27373 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field. */
27374 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_WIDTH 1
27375 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field value. */
27376 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_SET_MSK 0x00200000
27377 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field value. */
27378 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_CLR_MSK 0xffdfffff
27379 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field. */
27380 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_RESET 0x0
27381 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS field value from a register. */
27382 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_GET(value) (((value) & 0x00200000) >> 21)
27383 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field value suitable for setting the register. */
27384 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_SET(value) (((value) << 21) & 0x00200000)
27385 
27386 /*
27387  * Field : MMC Receive IPV6 Header Error Octet Counter Interrupt Status - rxipv6herois
27388  *
27389  * This bit is set when the rxipv6_hdrerr_octets counter reaches half of the
27390  * maximum value or the maximum value.
27391  *
27392  * Field Enumeration Values:
27393  *
27394  * Enum | Value | Description
27395  * :-------------------------------------------------|:------|:------------
27396  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_E_NOINT | 0x0 |
27397  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_E_INTERR | 0x1 |
27398  *
27399  * Field Access Macros:
27400  *
27401  */
27402 /*
27403  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS
27404  *
27405  */
27406 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_E_NOINT 0x0
27407 /*
27408  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS
27409  *
27410  */
27411 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_E_INTERR 0x1
27412 
27413 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field. */
27414 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_LSB 22
27415 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field. */
27416 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_MSB 22
27417 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field. */
27418 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_WIDTH 1
27419 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field value. */
27420 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_SET_MSK 0x00400000
27421 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field value. */
27422 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_CLR_MSK 0xffbfffff
27423 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field. */
27424 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_RESET 0x0
27425 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS field value from a register. */
27426 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_GET(value) (((value) & 0x00400000) >> 22)
27427 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field value suitable for setting the register. */
27428 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_SET(value) (((value) << 22) & 0x00400000)
27429 
27430 /*
27431  * Field : MMC Receive IPV6 No Payload Octet Counter Interrupt Status - rxipv6nopayois
27432  *
27433  * This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum
27434  * value or the maximum value.
27435  *
27436  * Field Enumeration Values:
27437  *
27438  * Enum | Value | Description
27439  * :---------------------------------------------------|:------|:------------
27440  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_E_NOINT | 0x0 |
27441  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_E_INTERR | 0x1 |
27442  *
27443  * Field Access Macros:
27444  *
27445  */
27446 /*
27447  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS
27448  *
27449  */
27450 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_E_NOINT 0x0
27451 /*
27452  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS
27453  *
27454  */
27455 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_E_INTERR 0x1
27456 
27457 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field. */
27458 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_LSB 23
27459 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field. */
27460 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_MSB 23
27461 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field. */
27462 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_WIDTH 1
27463 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field value. */
27464 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_SET_MSK 0x00800000
27465 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field value. */
27466 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_CLR_MSK 0xff7fffff
27467 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field. */
27468 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_RESET 0x0
27469 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS field value from a register. */
27470 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_GET(value) (((value) & 0x00800000) >> 23)
27471 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field value suitable for setting the register. */
27472 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_SET(value) (((value) << 23) & 0x00800000)
27473 
27474 /*
27475  * Field : MMC Receive UDP Good Octet Counter Interrupt Status - rxudpgois
27476  *
27477  * This bit is set when the rxudp_gd_octets counter reaches half of the maximum
27478  * value or the maximum value.
27479  *
27480  * Field Enumeration Values:
27481  *
27482  * Enum | Value | Description
27483  * :----------------------------------------------|:------|:------------
27484  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_E_NOINT | 0x0 |
27485  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_E_INTERR | 0x1 |
27486  *
27487  * Field Access Macros:
27488  *
27489  */
27490 /*
27491  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS
27492  *
27493  */
27494 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_E_NOINT 0x0
27495 /*
27496  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS
27497  *
27498  */
27499 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_E_INTERR 0x1
27500 
27501 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field. */
27502 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_LSB 24
27503 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field. */
27504 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_MSB 24
27505 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field. */
27506 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_WIDTH 1
27507 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field value. */
27508 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_SET_MSK 0x01000000
27509 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field value. */
27510 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_CLR_MSK 0xfeffffff
27511 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field. */
27512 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_RESET 0x0
27513 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS field value from a register. */
27514 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_GET(value) (((value) & 0x01000000) >> 24)
27515 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field value suitable for setting the register. */
27516 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_SET(value) (((value) << 24) & 0x01000000)
27517 
27518 /*
27519  * Field : MMC Receive UDP Error Octet Counter Interrupt Status - rxudperois
27520  *
27521  * This bit is set when the rxudp_err_octets counter reaches half the maximum value
27522  * or the maximum value.
27523  *
27524  * Field Enumeration Values:
27525  *
27526  * Enum | Value | Description
27527  * :-----------------------------------------------|:------|:------------
27528  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_E_NOINT | 0x0 |
27529  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_E_INTERR | 0x1 |
27530  *
27531  * Field Access Macros:
27532  *
27533  */
27534 /*
27535  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS
27536  *
27537  */
27538 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_E_NOINT 0x0
27539 /*
27540  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS
27541  *
27542  */
27543 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_E_INTERR 0x1
27544 
27545 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field. */
27546 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_LSB 25
27547 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field. */
27548 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_MSB 25
27549 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field. */
27550 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_WIDTH 1
27551 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field value. */
27552 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_SET_MSK 0x02000000
27553 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field value. */
27554 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_CLR_MSK 0xfdffffff
27555 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field. */
27556 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_RESET 0x0
27557 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS field value from a register. */
27558 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_GET(value) (((value) & 0x02000000) >> 25)
27559 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field value suitable for setting the register. */
27560 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_SET(value) (((value) << 25) & 0x02000000)
27561 
27562 /*
27563  * Field : MMC Receive TCP Good Octet Counter Interrupt Status - rxtcpgois
27564  *
27565  * This bit is set when the rxtcp_gd_octets counter reaches half the maximum value
27566  * or the maximum value.
27567  *
27568  * Field Enumeration Values:
27569  *
27570  * Enum | Value | Description
27571  * :----------------------------------------------|:------|:------------
27572  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_E_NOINT | 0x0 |
27573  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_E_INTERR | 0x1 |
27574  *
27575  * Field Access Macros:
27576  *
27577  */
27578 /*
27579  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS
27580  *
27581  */
27582 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_E_NOINT 0x0
27583 /*
27584  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS
27585  *
27586  */
27587 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_E_INTERR 0x1
27588 
27589 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field. */
27590 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_LSB 26
27591 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field. */
27592 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_MSB 26
27593 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field. */
27594 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_WIDTH 1
27595 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field value. */
27596 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_SET_MSK 0x04000000
27597 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field value. */
27598 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_CLR_MSK 0xfbffffff
27599 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field. */
27600 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_RESET 0x0
27601 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS field value from a register. */
27602 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_GET(value) (((value) & 0x04000000) >> 26)
27603 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field value suitable for setting the register. */
27604 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_SET(value) (((value) << 26) & 0x04000000)
27605 
27606 /*
27607  * Field : MMC Receive TCP Error Octet Counter Interrupt Status - rxtcperois
27608  *
27609  * This bit is set when the rxtcp_err_octets counter reaches half of the maximum
27610  * value or the maximum value.
27611  *
27612  * Field Enumeration Values:
27613  *
27614  * Enum | Value | Description
27615  * :-----------------------------------------------|:------|:------------
27616  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_E_NOINT | 0x0 |
27617  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_E_INTERR | 0x1 |
27618  *
27619  * Field Access Macros:
27620  *
27621  */
27622 /*
27623  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS
27624  *
27625  */
27626 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_E_NOINT 0x0
27627 /*
27628  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS
27629  *
27630  */
27631 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_E_INTERR 0x1
27632 
27633 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field. */
27634 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_LSB 27
27635 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field. */
27636 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_MSB 27
27637 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field. */
27638 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_WIDTH 1
27639 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field value. */
27640 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_SET_MSK 0x08000000
27641 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field value. */
27642 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_CLR_MSK 0xf7ffffff
27643 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field. */
27644 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_RESET 0x0
27645 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS field value from a register. */
27646 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_GET(value) (((value) & 0x08000000) >> 27)
27647 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field value suitable for setting the register. */
27648 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_SET(value) (((value) << 27) & 0x08000000)
27649 
27650 /*
27651  * Field : MMC Receive ICMP Good Octet Counter Interrupt Status - rxicmpgois
27652  *
27653  * This bit is set when the rxicmp_gd_octets counter reaches half of the maximum
27654  * value or the maximum value.
27655  *
27656  * Field Enumeration Values:
27657  *
27658  * Enum | Value | Description
27659  * :-----------------------------------------------|:------|:------------
27660  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_E_NOINT | 0x0 |
27661  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_E_INTERR | 0x1 |
27662  *
27663  * Field Access Macros:
27664  *
27665  */
27666 /*
27667  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS
27668  *
27669  */
27670 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_E_NOINT 0x0
27671 /*
27672  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS
27673  *
27674  */
27675 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_E_INTERR 0x1
27676 
27677 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field. */
27678 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_LSB 28
27679 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field. */
27680 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_MSB 28
27681 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field. */
27682 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_WIDTH 1
27683 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field value. */
27684 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_SET_MSK 0x10000000
27685 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field value. */
27686 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_CLR_MSK 0xefffffff
27687 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field. */
27688 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_RESET 0x0
27689 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS field value from a register. */
27690 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_GET(value) (((value) & 0x10000000) >> 28)
27691 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field value suitable for setting the register. */
27692 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_SET(value) (((value) << 28) & 0x10000000)
27693 
27694 /*
27695  * Field : MMC Receive ICMP Error Octet Counter Interrupt Status - rxicmperois
27696  *
27697  * This bit is set when the rxicmp_err_octets counter reaches half of the maximum
27698  * value or the maximum value.
27699  *
27700  * Field Enumeration Values:
27701  *
27702  * Enum | Value | Description
27703  * :------------------------------------------------|:------|:------------
27704  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_E_NOINT | 0x0 |
27705  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_E_INTERR | 0x1 |
27706  *
27707  * Field Access Macros:
27708  *
27709  */
27710 /*
27711  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS
27712  *
27713  */
27714 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_E_NOINT 0x0
27715 /*
27716  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS
27717  *
27718  */
27719 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_E_INTERR 0x1
27720 
27721 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field. */
27722 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_LSB 29
27723 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field. */
27724 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_MSB 29
27725 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field. */
27726 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_WIDTH 1
27727 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field value. */
27728 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_SET_MSK 0x20000000
27729 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field value. */
27730 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_CLR_MSK 0xdfffffff
27731 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field. */
27732 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_RESET 0x0
27733 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS field value from a register. */
27734 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_GET(value) (((value) & 0x20000000) >> 29)
27735 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field value suitable for setting the register. */
27736 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_SET(value) (((value) << 29) & 0x20000000)
27737 
27738 #ifndef __ASSEMBLY__
27739 /*
27740  * WARNING: The C register and register group struct declarations are provided for
27741  * convenience and illustrative purposes. They should, however, be used with
27742  * caution as the C language standard provides no guarantees about the alignment or
27743  * atomicity of device memory accesses. The recommended practice for writing
27744  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
27745  * alt_write_word() functions.
27746  *
27747  * The struct declaration for register ALT_EMAC_GMAC_MMC_IPC_RX_INT.
27748  */
27749 struct ALT_EMAC_GMAC_MMC_IPC_RX_INT_s
27750 {
27751  const uint32_t rxipv4gfis : 1; /* MMC Receive IPV4 Good Frame Counter Interrupt Status */
27752  const uint32_t rxipv4herfis : 1; /* MMC Receive IPV4 Header Error Frame Counter Interrupt Status */
27753  const uint32_t rxipv4nopayfis : 1; /* MMC Receive IPV4 No Payload Frame Counter Interrupt Status */
27754  const uint32_t rxipv4fragfis : 1; /* MMC Receive IPV4 Fragmented Frame Counter Interrupt Status */
27755  const uint32_t rxipv4udsblfis : 1; /* MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status */
27756  const uint32_t rxipv6gfis : 1; /* MMC Receive IPV6 Good Frame Counter Interrupt Status */
27757  const uint32_t rxipv6herfis : 1; /* MMC Receive IPV6 Header Error Frame Counter Interrupt Status */
27758  const uint32_t rxipv6nopayfis : 1; /* MMC Receive IPV6 No Payload Frame Counter Interrupt Status */
27759  const uint32_t rxudpgfis : 1; /* MMC Receive UDP Good Frame Counter Interrupt Status */
27760  const uint32_t rxudperfis : 1; /* MMC Receive UDP Error Frame Counter Interrupt Status */
27761  const uint32_t rxtcpgfis : 1; /* MMC Receive TCP Good Frame Counter Interrupt Status */
27762  const uint32_t rxtcperfis : 1; /* MMC Receive TCP Error Frame Counter Interrupt Status */
27763  const uint32_t rxicmpgfis : 1; /* MMC Receive ICMP Good Frame Counter Interrupt Status */
27764  const uint32_t rxicmperfis : 1; /* MMC Receive ICMP Error Frame Counter Interrupt Status */
27765  uint32_t : 2; /* *UNDEFINED* */
27766  const uint32_t rxipv4gois : 1; /* MMC Receive IPV4 Good Octet Counter Interrupt Status */
27767  const uint32_t rxipv4herois : 1; /* MMC Receive IPV4 Header Error Octet Counter Interrupt Status */
27768  const uint32_t rxipv4nopayois : 1; /* MMC Receive IPV4 No Payload Octet Counter Interrupt Status */
27769  const uint32_t rxipv4fragois : 1; /* MMC Receive IPV4 Fragmented Octet Counter Interrupt Status */
27770  const uint32_t rxipv4udsblois : 1; /* MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status */
27771  const uint32_t rxipv6gois : 1; /* MMC Receive IPV6 Good Octet Counter Interrupt Status */
27772  const uint32_t rxipv6herois : 1; /* MMC Receive IPV6 Header Error Octet Counter Interrupt Status */
27773  const uint32_t rxipv6nopayois : 1; /* MMC Receive IPV6 No Payload Octet Counter Interrupt Status */
27774  const uint32_t rxudpgois : 1; /* MMC Receive UDP Good Octet Counter Interrupt Status */
27775  const uint32_t rxudperois : 1; /* MMC Receive UDP Error Octet Counter Interrupt Status */
27776  const uint32_t rxtcpgois : 1; /* MMC Receive TCP Good Octet Counter Interrupt Status */
27777  const uint32_t rxtcperois : 1; /* MMC Receive TCP Error Octet Counter Interrupt Status */
27778  const uint32_t rxicmpgois : 1; /* MMC Receive ICMP Good Octet Counter Interrupt Status */
27779  const uint32_t rxicmperois : 1; /* MMC Receive ICMP Error Octet Counter Interrupt Status */
27780  uint32_t : 2; /* *UNDEFINED* */
27781 };
27782 
27783 /* The typedef declaration for register ALT_EMAC_GMAC_MMC_IPC_RX_INT. */
27784 typedef volatile struct ALT_EMAC_GMAC_MMC_IPC_RX_INT_s ALT_EMAC_GMAC_MMC_IPC_RX_INT_t;
27785 #endif /* __ASSEMBLY__ */
27786 
27787 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT register. */
27788 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_RESET 0x00000000
27789 /* The byte offset of the ALT_EMAC_GMAC_MMC_IPC_RX_INT register from the beginning of the component. */
27790 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_OFST 0x208
27791 /* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT register. */
27792 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_IPC_RX_INT_OFST))
27793 
27794 /*
27795  * Register : Register 132 (rxipv4_gd_frms Register) - gmacgrp_rxipv4_gd_frms
27796  *
27797  * Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload
27798  *
27799  * Register Layout
27800  *
27801  * Bits | Access | Reset | Description
27802  * :-------|:-------|:------|:---------------
27803  * [31:0] | R | 0x0 | rxipv4_gd_frms
27804  *
27805  */
27806 /*
27807  * Field : rxipv4_gd_frms - cnt
27808  *
27809  * Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload
27810  *
27811  * Field Access Macros:
27812  *
27813  */
27814 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field. */
27815 #define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_LSB 0
27816 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field. */
27817 #define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_MSB 31
27818 /* The width in bits of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field. */
27819 #define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_WIDTH 32
27820 /* The mask used to set the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field value. */
27821 #define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_SET_MSK 0xffffffff
27822 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field value. */
27823 #define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_CLR_MSK 0x00000000
27824 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field. */
27825 #define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_RESET 0x0
27826 /* Extracts the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT field value from a register. */
27827 #define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
27828 /* Produces a ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field value suitable for setting the register. */
27829 #define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
27830 
27831 #ifndef __ASSEMBLY__
27832 /*
27833  * WARNING: The C register and register group struct declarations are provided for
27834  * convenience and illustrative purposes. They should, however, be used with
27835  * caution as the C language standard provides no guarantees about the alignment or
27836  * atomicity of device memory accesses. The recommended practice for writing
27837  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
27838  * alt_write_word() functions.
27839  *
27840  * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_GD_FRMS.
27841  */
27842 struct ALT_EMAC_GMAC_RXIPV4_GD_FRMS_s
27843 {
27844  const uint32_t cnt : 32; /* rxipv4_gd_frms */
27845 };
27846 
27847 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_GD_FRMS. */
27848 typedef volatile struct ALT_EMAC_GMAC_RXIPV4_GD_FRMS_s ALT_EMAC_GMAC_RXIPV4_GD_FRMS_t;
27849 #endif /* __ASSEMBLY__ */
27850 
27851 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS register. */
27852 #define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_RESET 0x00000000
27853 /* The byte offset of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS register from the beginning of the component. */
27854 #define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_OFST 0x210
27855 /* The address of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS register. */
27856 #define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_GD_FRMS_OFST))
27857 
27858 /*
27859  * Register : Register 133 (rxipv4_hdrerr_frms Register) - gmacgrp_rxipv4_hdrerr_frms
27860  *
27861  * Number of IPv4 datagrams received with header (checksum, length, or version
27862  * mismatch) errors
27863  *
27864  * Register Layout
27865  *
27866  * Bits | Access | Reset | Description
27867  * :-------|:-------|:------|:-------------------
27868  * [31:0] | R | 0x0 | rxipv4_hdrerr_frms
27869  *
27870  */
27871 /*
27872  * Field : rxipv4_hdrerr_frms - cnt
27873  *
27874  * Number of IPv4 datagrams received with header (checksum, length, or version
27875  * mismatch) errors
27876  *
27877  * Field Access Macros:
27878  *
27879  */
27880 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field. */
27881 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_LSB 0
27882 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field. */
27883 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_MSB 31
27884 /* The width in bits of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field. */
27885 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_WIDTH 32
27886 /* The mask used to set the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field value. */
27887 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_SET_MSK 0xffffffff
27888 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field value. */
27889 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_CLR_MSK 0x00000000
27890 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field. */
27891 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_RESET 0x0
27892 /* Extracts the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT field value from a register. */
27893 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
27894 /* Produces a ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field value suitable for setting the register. */
27895 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
27896 
27897 #ifndef __ASSEMBLY__
27898 /*
27899  * WARNING: The C register and register group struct declarations are provided for
27900  * convenience and illustrative purposes. They should, however, be used with
27901  * caution as the C language standard provides no guarantees about the alignment or
27902  * atomicity of device memory accesses. The recommended practice for writing
27903  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
27904  * alt_write_word() functions.
27905  *
27906  * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS.
27907  */
27908 struct ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_s
27909 {
27910  const uint32_t cnt : 32; /* rxipv4_hdrerr_frms */
27911 };
27912 
27913 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS. */
27914 typedef volatile struct ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_s ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_t;
27915 #endif /* __ASSEMBLY__ */
27916 
27917 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS register. */
27918 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_RESET 0x00000000
27919 /* The byte offset of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS register from the beginning of the component. */
27920 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_OFST 0x214
27921 /* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS register. */
27922 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_OFST))
27923 
27924 /*
27925  * Register : Register 134 (rxipv4_nopay_frms Register) - gmacgrp_rxipv4_nopay_frms
27926  *
27927  * Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP
27928  * payload processed by the Checksum engine
27929  *
27930  * Register Layout
27931  *
27932  * Bits | Access | Reset | Description
27933  * :-------|:-------|:------|:------------------
27934  * [31:0] | R | 0x0 | rxipv4_nopay_frms
27935  *
27936  */
27937 /*
27938  * Field : rxipv4_nopay_frms - cnt
27939  *
27940  * Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP
27941  * payload processed by the Checksum engine
27942  *
27943  * Field Access Macros:
27944  *
27945  */
27946 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field. */
27947 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_LSB 0
27948 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field. */
27949 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_MSB 31
27950 /* The width in bits of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field. */
27951 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_WIDTH 32
27952 /* The mask used to set the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field value. */
27953 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_SET_MSK 0xffffffff
27954 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field value. */
27955 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_CLR_MSK 0x00000000
27956 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field. */
27957 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_RESET 0x0
27958 /* Extracts the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT field value from a register. */
27959 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
27960 /* Produces a ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field value suitable for setting the register. */
27961 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
27962 
27963 #ifndef __ASSEMBLY__
27964 /*
27965  * WARNING: The C register and register group struct declarations are provided for
27966  * convenience and illustrative purposes. They should, however, be used with
27967  * caution as the C language standard provides no guarantees about the alignment or
27968  * atomicity of device memory accesses. The recommended practice for writing
27969  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
27970  * alt_write_word() functions.
27971  *
27972  * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS.
27973  */
27974 struct ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_s
27975 {
27976  const uint32_t cnt : 32; /* rxipv4_nopay_frms */
27977 };
27978 
27979 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS. */
27980 typedef volatile struct ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_s ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_t;
27981 #endif /* __ASSEMBLY__ */
27982 
27983 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS register. */
27984 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_RESET 0x00000000
27985 /* The byte offset of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS register from the beginning of the component. */
27986 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_OFST 0x218
27987 /* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS register. */
27988 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_OFST))
27989 
27990 /*
27991  * Register : Register 135 (rxipv4_frag_frms Register) - gmacgrp_rxipv4_frag_frms
27992  *
27993  * Number of good IPv4 datagrams with fragmentation
27994  *
27995  * Register Layout
27996  *
27997  * Bits | Access | Reset | Description
27998  * :-------|:-------|:------|:-----------------
27999  * [31:0] | R | 0x0 | rxipv4_frag_frms
28000  *
28001  */
28002 /*
28003  * Field : rxipv4_frag_frms - cnt
28004  *
28005  * Number of good IPv4 datagrams with fragmentation
28006  *
28007  * Field Access Macros:
28008  *
28009  */
28010 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field. */
28011 #define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_LSB 0
28012 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field. */
28013 #define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_MSB 31
28014 /* The width in bits of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field. */
28015 #define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_WIDTH 32
28016 /* The mask used to set the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field value. */
28017 #define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_SET_MSK 0xffffffff
28018 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field value. */
28019 #define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_CLR_MSK 0x00000000
28020 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field. */
28021 #define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_RESET 0x0
28022 /* Extracts the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT field value from a register. */
28023 #define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
28024 /* Produces a ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field value suitable for setting the register. */
28025 #define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
28026 
28027 #ifndef __ASSEMBLY__
28028 /*
28029  * WARNING: The C register and register group struct declarations are provided for
28030  * convenience and illustrative purposes. They should, however, be used with
28031  * caution as the C language standard provides no guarantees about the alignment or
28032  * atomicity of device memory accesses. The recommended practice for writing
28033  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28034  * alt_write_word() functions.
28035  *
28036  * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS.
28037  */
28038 struct ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_s
28039 {
28040  const uint32_t cnt : 32; /* rxipv4_frag_frms */
28041 };
28042 
28043 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS. */
28044 typedef volatile struct ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_s ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_t;
28045 #endif /* __ASSEMBLY__ */
28046 
28047 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS register. */
28048 #define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_RESET 0x00000000
28049 /* The byte offset of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS register from the beginning of the component. */
28050 #define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_OFST 0x21c
28051 /* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS register. */
28052 #define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_OFST))
28053 
28054 /*
28055  * Register : Register 136 (rxipv4_udsbl_frms Register) - gmacgrp_rxipv4_udsbl_frms
28056  *
28057  * Number of good IPv4 datagrams received that had a UDP payload with checksum
28058  * disabled
28059  *
28060  * Register Layout
28061  *
28062  * Bits | Access | Reset | Description
28063  * :-------|:-------|:------|:------------------
28064  * [31:0] | R | 0x0 | rxipv4_udsbl_frms
28065  *
28066  */
28067 /*
28068  * Field : rxipv4_udsbl_frms - cnt
28069  *
28070  * Number of good IPv4 datagrams received that had a UDP payload with checksum
28071  * disabled
28072  *
28073  * Field Access Macros:
28074  *
28075  */
28076 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field. */
28077 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_LSB 0
28078 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field. */
28079 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_MSB 31
28080 /* The width in bits of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field. */
28081 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_WIDTH 32
28082 /* The mask used to set the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field value. */
28083 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_SET_MSK 0xffffffff
28084 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field value. */
28085 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_CLR_MSK 0x00000000
28086 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field. */
28087 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_RESET 0x0
28088 /* Extracts the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT field value from a register. */
28089 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
28090 /* Produces a ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field value suitable for setting the register. */
28091 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
28092 
28093 #ifndef __ASSEMBLY__
28094 /*
28095  * WARNING: The C register and register group struct declarations are provided for
28096  * convenience and illustrative purposes. They should, however, be used with
28097  * caution as the C language standard provides no guarantees about the alignment or
28098  * atomicity of device memory accesses. The recommended practice for writing
28099  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28100  * alt_write_word() functions.
28101  *
28102  * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS.
28103  */
28104 struct ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_s
28105 {
28106  const uint32_t cnt : 32; /* rxipv4_udsbl_frms */
28107 };
28108 
28109 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS. */
28110 typedef volatile struct ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_s ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_t;
28111 #endif /* __ASSEMBLY__ */
28112 
28113 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS register. */
28114 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_RESET 0x00000000
28115 /* The byte offset of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS register from the beginning of the component. */
28116 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_OFST 0x220
28117 /* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS register. */
28118 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_OFST))
28119 
28120 /*
28121  * Register : Register 137 (rxipv6_gd_frms Register) - gmacgrp_rxipv6_gd_frms
28122  *
28123  * Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads
28124  *
28125  * Register Layout
28126  *
28127  * Bits | Access | Reset | Description
28128  * :-------|:-------|:------|:---------------
28129  * [31:0] | R | 0x0 | rxipv6_gd_frms
28130  *
28131  */
28132 /*
28133  * Field : rxipv6_gd_frms - cnt
28134  *
28135  * Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads
28136  *
28137  * Field Access Macros:
28138  *
28139  */
28140 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field. */
28141 #define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_LSB 0
28142 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field. */
28143 #define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_MSB 31
28144 /* The width in bits of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field. */
28145 #define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_WIDTH 32
28146 /* The mask used to set the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field value. */
28147 #define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_SET_MSK 0xffffffff
28148 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field value. */
28149 #define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_CLR_MSK 0x00000000
28150 /* The reset value of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field. */
28151 #define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_RESET 0x0
28152 /* Extracts the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT field value from a register. */
28153 #define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
28154 /* Produces a ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field value suitable for setting the register. */
28155 #define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
28156 
28157 #ifndef __ASSEMBLY__
28158 /*
28159  * WARNING: The C register and register group struct declarations are provided for
28160  * convenience and illustrative purposes. They should, however, be used with
28161  * caution as the C language standard provides no guarantees about the alignment or
28162  * atomicity of device memory accesses. The recommended practice for writing
28163  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28164  * alt_write_word() functions.
28165  *
28166  * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_GD_FRMS.
28167  */
28168 struct ALT_EMAC_GMAC_RXIPV6_GD_FRMS_s
28169 {
28170  const uint32_t cnt : 32; /* rxipv6_gd_frms */
28171 };
28172 
28173 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_GD_FRMS. */
28174 typedef volatile struct ALT_EMAC_GMAC_RXIPV6_GD_FRMS_s ALT_EMAC_GMAC_RXIPV6_GD_FRMS_t;
28175 #endif /* __ASSEMBLY__ */
28176 
28177 /* The reset value of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS register. */
28178 #define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_RESET 0x00000000
28179 /* The byte offset of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS register from the beginning of the component. */
28180 #define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_OFST 0x224
28181 /* The address of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS register. */
28182 #define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_GD_FRMS_OFST))
28183 
28184 /*
28185  * Register : Register 138 (rxipv6_hdrerr_frms Register) - gmacgrp_rxipv6_hdrerr_frms
28186  *
28187  * Number of IPv6 datagrams received with header errors (length or version
28188  * mismatch)
28189  *
28190  * Register Layout
28191  *
28192  * Bits | Access | Reset | Description
28193  * :-------|:-------|:------|:-------------------
28194  * [31:0] | R | 0x0 | rxipv6_hdrerr_frms
28195  *
28196  */
28197 /*
28198  * Field : rxipv6_hdrerr_frms - cnt
28199  *
28200  * Number of IPv6 datagrams received with header errors (length or version
28201  * mismatch)
28202  *
28203  * Field Access Macros:
28204  *
28205  */
28206 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field. */
28207 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_LSB 0
28208 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field. */
28209 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_MSB 31
28210 /* The width in bits of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field. */
28211 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_WIDTH 32
28212 /* The mask used to set the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field value. */
28213 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_SET_MSK 0xffffffff
28214 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field value. */
28215 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_CLR_MSK 0x00000000
28216 /* The reset value of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field. */
28217 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_RESET 0x0
28218 /* Extracts the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT field value from a register. */
28219 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
28220 /* Produces a ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field value suitable for setting the register. */
28221 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
28222 
28223 #ifndef __ASSEMBLY__
28224 /*
28225  * WARNING: The C register and register group struct declarations are provided for
28226  * convenience and illustrative purposes. They should, however, be used with
28227  * caution as the C language standard provides no guarantees about the alignment or
28228  * atomicity of device memory accesses. The recommended practice for writing
28229  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28230  * alt_write_word() functions.
28231  *
28232  * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS.
28233  */
28234 struct ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_s
28235 {
28236  const uint32_t cnt : 32; /* rxipv6_hdrerr_frms */
28237 };
28238 
28239 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS. */
28240 typedef volatile struct ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_s ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_t;
28241 #endif /* __ASSEMBLY__ */
28242 
28243 /* The reset value of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS register. */
28244 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_RESET 0x00000000
28245 /* The byte offset of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS register from the beginning of the component. */
28246 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_OFST 0x228
28247 /* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS register. */
28248 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_OFST))
28249 
28250 /*
28251  * Register : Register 139 (rxipv6_nopay_frms) - gmacgrp_rxipv6_nopay_frms
28252  *
28253  * Number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP
28254  * payload. This includes all IPv6 datagrams with fragmentation or security
28255  * extension headers
28256  *
28257  * Register Layout
28258  *
28259  * Bits | Access | Reset | Description
28260  * :-------|:-------|:------|:------------------
28261  * [31:0] | R | 0x0 | rxipv6_nopay_frms
28262  *
28263  */
28264 /*
28265  * Field : rxipv6_nopay_frms - cnt
28266  *
28267  * Number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP
28268  * payload. This includes all IPv6 datagrams with fragmentation or security
28269  * extension headers
28270  *
28271  * Field Access Macros:
28272  *
28273  */
28274 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field. */
28275 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_LSB 0
28276 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field. */
28277 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_MSB 31
28278 /* The width in bits of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field. */
28279 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_WIDTH 32
28280 /* The mask used to set the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field value. */
28281 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_SET_MSK 0xffffffff
28282 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field value. */
28283 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_CLR_MSK 0x00000000
28284 /* The reset value of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field. */
28285 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_RESET 0x0
28286 /* Extracts the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT field value from a register. */
28287 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
28288 /* Produces a ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field value suitable for setting the register. */
28289 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
28290 
28291 #ifndef __ASSEMBLY__
28292 /*
28293  * WARNING: The C register and register group struct declarations are provided for
28294  * convenience and illustrative purposes. They should, however, be used with
28295  * caution as the C language standard provides no guarantees about the alignment or
28296  * atomicity of device memory accesses. The recommended practice for writing
28297  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28298  * alt_write_word() functions.
28299  *
28300  * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS.
28301  */
28302 struct ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_s
28303 {
28304  const uint32_t cnt : 32; /* rxipv6_nopay_frms */
28305 };
28306 
28307 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS. */
28308 typedef volatile struct ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_s ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_t;
28309 #endif /* __ASSEMBLY__ */
28310 
28311 /* The reset value of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS register. */
28312 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_RESET 0x00000000
28313 /* The byte offset of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS register from the beginning of the component. */
28314 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_OFST 0x22c
28315 /* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS register. */
28316 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_OFST))
28317 
28318 /*
28319  * Register : Register 140 (rxudp_gd_frms Register) - gmacgrp_rxudp_gd_frms
28320  *
28321  * Number of good IP datagrams with a good UDP payload. This counter is not updated
28322  * when the counter is incremented
28323  *
28324  * Register Layout
28325  *
28326  * Bits | Access | Reset | Description
28327  * :-------|:-------|:------|:--------------
28328  * [31:0] | R | 0x0 | rxudp_gd_frms
28329  *
28330  */
28331 /*
28332  * Field : rxudp_gd_frms - cnt
28333  *
28334  * Number of good IP datagrams with a good UDP payload. This counter is not updated
28335  * when the counter is incremented
28336  *
28337  * Field Access Macros:
28338  *
28339  */
28340 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field. */
28341 #define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_LSB 0
28342 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field. */
28343 #define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_MSB 31
28344 /* The width in bits of the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field. */
28345 #define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_WIDTH 32
28346 /* The mask used to set the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field value. */
28347 #define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_SET_MSK 0xffffffff
28348 /* The mask used to clear the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field value. */
28349 #define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_CLR_MSK 0x00000000
28350 /* The reset value of the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field. */
28351 #define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_RESET 0x0
28352 /* Extracts the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT field value from a register. */
28353 #define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
28354 /* Produces a ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field value suitable for setting the register. */
28355 #define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
28356 
28357 #ifndef __ASSEMBLY__
28358 /*
28359  * WARNING: The C register and register group struct declarations are provided for
28360  * convenience and illustrative purposes. They should, however, be used with
28361  * caution as the C language standard provides no guarantees about the alignment or
28362  * atomicity of device memory accesses. The recommended practice for writing
28363  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28364  * alt_write_word() functions.
28365  *
28366  * The struct declaration for register ALT_EMAC_GMAC_RXUDP_GD_FRMS.
28367  */
28368 struct ALT_EMAC_GMAC_RXUDP_GD_FRMS_s
28369 {
28370  const uint32_t cnt : 32; /* rxudp_gd_frms */
28371 };
28372 
28373 /* The typedef declaration for register ALT_EMAC_GMAC_RXUDP_GD_FRMS. */
28374 typedef volatile struct ALT_EMAC_GMAC_RXUDP_GD_FRMS_s ALT_EMAC_GMAC_RXUDP_GD_FRMS_t;
28375 #endif /* __ASSEMBLY__ */
28376 
28377 /* The reset value of the ALT_EMAC_GMAC_RXUDP_GD_FRMS register. */
28378 #define ALT_EMAC_GMAC_RXUDP_GD_FRMS_RESET 0x00000000
28379 /* The byte offset of the ALT_EMAC_GMAC_RXUDP_GD_FRMS register from the beginning of the component. */
28380 #define ALT_EMAC_GMAC_RXUDP_GD_FRMS_OFST 0x230
28381 /* The address of the ALT_EMAC_GMAC_RXUDP_GD_FRMS register. */
28382 #define ALT_EMAC_GMAC_RXUDP_GD_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUDP_GD_FRMS_OFST))
28383 
28384 /*
28385  * Register : Register 141 (rxudp_err_frms Register) - gmacgrp_rxudp_err_frms
28386  *
28387  * Number of good IP datagrams whose UDP payload has a checksum error
28388  *
28389  * Register Layout
28390  *
28391  * Bits | Access | Reset | Description
28392  * :-------|:-------|:------|:---------------
28393  * [31:0] | R | 0x0 | rxudp_err_frms
28394  *
28395  */
28396 /*
28397  * Field : rxudp_err_frms - cnt
28398  *
28399  * Number of good IP datagrams whose UDP payload has a checksum error
28400  *
28401  * Field Access Macros:
28402  *
28403  */
28404 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field. */
28405 #define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_LSB 0
28406 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field. */
28407 #define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_MSB 31
28408 /* The width in bits of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field. */
28409 #define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_WIDTH 32
28410 /* The mask used to set the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field value. */
28411 #define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_SET_MSK 0xffffffff
28412 /* The mask used to clear the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field value. */
28413 #define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_CLR_MSK 0x00000000
28414 /* The reset value of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field. */
28415 #define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_RESET 0x0
28416 /* Extracts the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT field value from a register. */
28417 #define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
28418 /* Produces a ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field value suitable for setting the register. */
28419 #define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
28420 
28421 #ifndef __ASSEMBLY__
28422 /*
28423  * WARNING: The C register and register group struct declarations are provided for
28424  * convenience and illustrative purposes. They should, however, be used with
28425  * caution as the C language standard provides no guarantees about the alignment or
28426  * atomicity of device memory accesses. The recommended practice for writing
28427  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28428  * alt_write_word() functions.
28429  *
28430  * The struct declaration for register ALT_EMAC_GMAC_RXUDP_ERR_FRMS.
28431  */
28432 struct ALT_EMAC_GMAC_RXUDP_ERR_FRMS_s
28433 {
28434  const uint32_t cnt : 32; /* rxudp_err_frms */
28435 };
28436 
28437 /* The typedef declaration for register ALT_EMAC_GMAC_RXUDP_ERR_FRMS. */
28438 typedef volatile struct ALT_EMAC_GMAC_RXUDP_ERR_FRMS_s ALT_EMAC_GMAC_RXUDP_ERR_FRMS_t;
28439 #endif /* __ASSEMBLY__ */
28440 
28441 /* The reset value of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS register. */
28442 #define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_RESET 0x00000000
28443 /* The byte offset of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS register from the beginning of the component. */
28444 #define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_OFST 0x234
28445 /* The address of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS register. */
28446 #define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUDP_ERR_FRMS_OFST))
28447 
28448 /*
28449  * Register : Register 142 (rxtcp_gd_frms Register) - gmacgrp_rxtcp_gd_frms
28450  *
28451  * Number of good IP datagrams with a good TCP payload
28452  *
28453  * Register Layout
28454  *
28455  * Bits | Access | Reset | Description
28456  * :-------|:-------|:------|:-----------------------
28457  * [31:0] | R | 0x0 | rxtcp_gd_frms Register
28458  *
28459  */
28460 /*
28461  * Field : rxtcp_gd_frms Register - cnt
28462  *
28463  * Number of good IP datagrams with a good TCP payload
28464  *
28465  * Field Access Macros:
28466  *
28467  */
28468 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field. */
28469 #define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_LSB 0
28470 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field. */
28471 #define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_MSB 31
28472 /* The width in bits of the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field. */
28473 #define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_WIDTH 32
28474 /* The mask used to set the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field value. */
28475 #define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_SET_MSK 0xffffffff
28476 /* The mask used to clear the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field value. */
28477 #define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_CLR_MSK 0x00000000
28478 /* The reset value of the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field. */
28479 #define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_RESET 0x0
28480 /* Extracts the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT field value from a register. */
28481 #define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
28482 /* Produces a ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field value suitable for setting the register. */
28483 #define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
28484 
28485 #ifndef __ASSEMBLY__
28486 /*
28487  * WARNING: The C register and register group struct declarations are provided for
28488  * convenience and illustrative purposes. They should, however, be used with
28489  * caution as the C language standard provides no guarantees about the alignment or
28490  * atomicity of device memory accesses. The recommended practice for writing
28491  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28492  * alt_write_word() functions.
28493  *
28494  * The struct declaration for register ALT_EMAC_GMAC_RXTCP_GD_FRMS.
28495  */
28496 struct ALT_EMAC_GMAC_RXTCP_GD_FRMS_s
28497 {
28498  const uint32_t cnt : 32; /* rxtcp_gd_frms Register */
28499 };
28500 
28501 /* The typedef declaration for register ALT_EMAC_GMAC_RXTCP_GD_FRMS. */
28502 typedef volatile struct ALT_EMAC_GMAC_RXTCP_GD_FRMS_s ALT_EMAC_GMAC_RXTCP_GD_FRMS_t;
28503 #endif /* __ASSEMBLY__ */
28504 
28505 /* The reset value of the ALT_EMAC_GMAC_RXTCP_GD_FRMS register. */
28506 #define ALT_EMAC_GMAC_RXTCP_GD_FRMS_RESET 0x00000000
28507 /* The byte offset of the ALT_EMAC_GMAC_RXTCP_GD_FRMS register from the beginning of the component. */
28508 #define ALT_EMAC_GMAC_RXTCP_GD_FRMS_OFST 0x238
28509 /* The address of the ALT_EMAC_GMAC_RXTCP_GD_FRMS register. */
28510 #define ALT_EMAC_GMAC_RXTCP_GD_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXTCP_GD_FRMS_OFST))
28511 
28512 /*
28513  * Register : Register 143 (rxtcp_err_frms Register) - gmacgrp_rxtcp_err_frms
28514  *
28515  * Number of good IP datagrams whose TCP payload has a checksum error
28516  *
28517  * Register Layout
28518  *
28519  * Bits | Access | Reset | Description
28520  * :-------|:-------|:------|:---------------
28521  * [31:0] | R | 0x0 | rxtcp_err_frms
28522  *
28523  */
28524 /*
28525  * Field : rxtcp_err_frms - cnt
28526  *
28527  * Number of good IP datagrams whose TCP payload has a checksum error
28528  *
28529  * Field Access Macros:
28530  *
28531  */
28532 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field. */
28533 #define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_LSB 0
28534 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field. */
28535 #define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_MSB 31
28536 /* The width in bits of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field. */
28537 #define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_WIDTH 32
28538 /* The mask used to set the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field value. */
28539 #define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_SET_MSK 0xffffffff
28540 /* The mask used to clear the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field value. */
28541 #define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_CLR_MSK 0x00000000
28542 /* The reset value of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field. */
28543 #define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_RESET 0x0
28544 /* Extracts the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT field value from a register. */
28545 #define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
28546 /* Produces a ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field value suitable for setting the register. */
28547 #define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
28548 
28549 #ifndef __ASSEMBLY__
28550 /*
28551  * WARNING: The C register and register group struct declarations are provided for
28552  * convenience and illustrative purposes. They should, however, be used with
28553  * caution as the C language standard provides no guarantees about the alignment or
28554  * atomicity of device memory accesses. The recommended practice for writing
28555  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28556  * alt_write_word() functions.
28557  *
28558  * The struct declaration for register ALT_EMAC_GMAC_RXTCP_ERR_FRMS.
28559  */
28560 struct ALT_EMAC_GMAC_RXTCP_ERR_FRMS_s
28561 {
28562  const uint32_t cnt : 32; /* rxtcp_err_frms */
28563 };
28564 
28565 /* The typedef declaration for register ALT_EMAC_GMAC_RXTCP_ERR_FRMS. */
28566 typedef volatile struct ALT_EMAC_GMAC_RXTCP_ERR_FRMS_s ALT_EMAC_GMAC_RXTCP_ERR_FRMS_t;
28567 #endif /* __ASSEMBLY__ */
28568 
28569 /* The reset value of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS register. */
28570 #define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_RESET 0x00000000
28571 /* The byte offset of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS register from the beginning of the component. */
28572 #define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_OFST 0x23c
28573 /* The address of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS register. */
28574 #define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXTCP_ERR_FRMS_OFST))
28575 
28576 /*
28577  * Register : Register 144 (rxicmp_gd_frms Register) - gmacgrp_rxicmp_gd_frms
28578  *
28579  * Number of good IP datagrams with a good ICMP payload
28580  *
28581  * Register Layout
28582  *
28583  * Bits | Access | Reset | Description
28584  * :-------|:-------|:------|:---------------
28585  * [31:0] | R | 0x0 | rxicmp_gd_frms
28586  *
28587  */
28588 /*
28589  * Field : rxicmp_gd_frms - cnt
28590  *
28591  * Number of good IP datagrams with a good ICMP payload
28592  *
28593  * Field Access Macros:
28594  *
28595  */
28596 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field. */
28597 #define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_LSB 0
28598 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field. */
28599 #define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_MSB 31
28600 /* The width in bits of the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field. */
28601 #define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_WIDTH 32
28602 /* The mask used to set the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field value. */
28603 #define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_SET_MSK 0xffffffff
28604 /* The mask used to clear the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field value. */
28605 #define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_CLR_MSK 0x00000000
28606 /* The reset value of the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field. */
28607 #define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_RESET 0x0
28608 /* Extracts the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT field value from a register. */
28609 #define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
28610 /* Produces a ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field value suitable for setting the register. */
28611 #define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
28612 
28613 #ifndef __ASSEMBLY__
28614 /*
28615  * WARNING: The C register and register group struct declarations are provided for
28616  * convenience and illustrative purposes. They should, however, be used with
28617  * caution as the C language standard provides no guarantees about the alignment or
28618  * atomicity of device memory accesses. The recommended practice for writing
28619  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28620  * alt_write_word() functions.
28621  *
28622  * The struct declaration for register ALT_EMAC_GMAC_RXICMP_GD_FRMS.
28623  */
28624 struct ALT_EMAC_GMAC_RXICMP_GD_FRMS_s
28625 {
28626  const uint32_t cnt : 32; /* rxicmp_gd_frms */
28627 };
28628 
28629 /* The typedef declaration for register ALT_EMAC_GMAC_RXICMP_GD_FRMS. */
28630 typedef volatile struct ALT_EMAC_GMAC_RXICMP_GD_FRMS_s ALT_EMAC_GMAC_RXICMP_GD_FRMS_t;
28631 #endif /* __ASSEMBLY__ */
28632 
28633 /* The reset value of the ALT_EMAC_GMAC_RXICMP_GD_FRMS register. */
28634 #define ALT_EMAC_GMAC_RXICMP_GD_FRMS_RESET 0x00000000
28635 /* The byte offset of the ALT_EMAC_GMAC_RXICMP_GD_FRMS register from the beginning of the component. */
28636 #define ALT_EMAC_GMAC_RXICMP_GD_FRMS_OFST 0x240
28637 /* The address of the ALT_EMAC_GMAC_RXICMP_GD_FRMS register. */
28638 #define ALT_EMAC_GMAC_RXICMP_GD_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXICMP_GD_FRMS_OFST))
28639 
28640 /*
28641  * Register : Register 145 (rxicmp_err_frms Register) - gmacgrp_rxicmp_err_frms
28642  *
28643  * Number of good IP datagrams whose ICMP payload has a checksum error
28644  *
28645  * Register Layout
28646  *
28647  * Bits | Access | Reset | Description
28648  * :-------|:-------|:------|:----------------
28649  * [31:0] | R | 0x0 | rxicmp_err_frms
28650  *
28651  */
28652 /*
28653  * Field : rxicmp_err_frms - cnt
28654  *
28655  * Number of good IP datagrams whose ICMP payload has a checksum error
28656  *
28657  * Field Access Macros:
28658  *
28659  */
28660 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field. */
28661 #define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_LSB 0
28662 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field. */
28663 #define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_MSB 31
28664 /* The width in bits of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field. */
28665 #define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_WIDTH 32
28666 /* The mask used to set the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field value. */
28667 #define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_SET_MSK 0xffffffff
28668 /* The mask used to clear the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field value. */
28669 #define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_CLR_MSK 0x00000000
28670 /* The reset value of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field. */
28671 #define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_RESET 0x0
28672 /* Extracts the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT field value from a register. */
28673 #define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
28674 /* Produces a ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field value suitable for setting the register. */
28675 #define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
28676 
28677 #ifndef __ASSEMBLY__
28678 /*
28679  * WARNING: The C register and register group struct declarations are provided for
28680  * convenience and illustrative purposes. They should, however, be used with
28681  * caution as the C language standard provides no guarantees about the alignment or
28682  * atomicity of device memory accesses. The recommended practice for writing
28683  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28684  * alt_write_word() functions.
28685  *
28686  * The struct declaration for register ALT_EMAC_GMAC_RXICMP_ERR_FRMS.
28687  */
28688 struct ALT_EMAC_GMAC_RXICMP_ERR_FRMS_s
28689 {
28690  const uint32_t cnt : 32; /* rxicmp_err_frms */
28691 };
28692 
28693 /* The typedef declaration for register ALT_EMAC_GMAC_RXICMP_ERR_FRMS. */
28694 typedef volatile struct ALT_EMAC_GMAC_RXICMP_ERR_FRMS_s ALT_EMAC_GMAC_RXICMP_ERR_FRMS_t;
28695 #endif /* __ASSEMBLY__ */
28696 
28697 /* The reset value of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS register. */
28698 #define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_RESET 0x00000000
28699 /* The byte offset of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS register from the beginning of the component. */
28700 #define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_OFST 0x244
28701 /* The address of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS register. */
28702 #define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXICMP_ERR_FRMS_OFST))
28703 
28704 /*
28705  * Register : Register 148 (rxipv4_gd_octets Register) - gmacgrp_rxipv4_gd_octets
28706  *
28707  * Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP
28708  * data
28709  *
28710  * Register Layout
28711  *
28712  * Bits | Access | Reset | Description
28713  * :-------|:-------|:------|:-----------------
28714  * [31:0] | R | 0x0 | rxipv4_gd_octets
28715  *
28716  */
28717 /*
28718  * Field : rxipv4_gd_octets - cnt
28719  *
28720  * Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP
28721  * data
28722  *
28723  * Field Access Macros:
28724  *
28725  */
28726 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field. */
28727 #define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_LSB 0
28728 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field. */
28729 #define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_MSB 31
28730 /* The width in bits of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field. */
28731 #define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_WIDTH 32
28732 /* The mask used to set the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field value. */
28733 #define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_SET_MSK 0xffffffff
28734 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field value. */
28735 #define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_CLR_MSK 0x00000000
28736 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field. */
28737 #define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_RESET 0x0
28738 /* Extracts the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT field value from a register. */
28739 #define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
28740 /* Produces a ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field value suitable for setting the register. */
28741 #define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
28742 
28743 #ifndef __ASSEMBLY__
28744 /*
28745  * WARNING: The C register and register group struct declarations are provided for
28746  * convenience and illustrative purposes. They should, however, be used with
28747  * caution as the C language standard provides no guarantees about the alignment or
28748  * atomicity of device memory accesses. The recommended practice for writing
28749  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28750  * alt_write_word() functions.
28751  *
28752  * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_GD_OCTETS.
28753  */
28754 struct ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_s
28755 {
28756  const uint32_t cnt : 32; /* rxipv4_gd_octets */
28757 };
28758 
28759 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_GD_OCTETS. */
28760 typedef volatile struct ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_s ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_t;
28761 #endif /* __ASSEMBLY__ */
28762 
28763 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS register. */
28764 #define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_RESET 0x00000000
28765 /* The byte offset of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS register from the beginning of the component. */
28766 #define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_OFST 0x250
28767 /* The address of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS register. */
28768 #define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_OFST))
28769 
28770 /*
28771  * Register : Register 149 (rxipv4_hdrerr_octets) - gmacgrp_rxipv4_hdrerr_octets
28772  *
28773  * Number of bytes received in IPv4 datagrams with header errors (checksum, length,
28774  * version mismatch). The value in the Length field of IPv4 header is used to
28775  * update this counter
28776  *
28777  * Register Layout
28778  *
28779  * Bits | Access | Reset | Description
28780  * :-------|:-------|:------|:------------------------------
28781  * [31:0] | R | 0x0 | rxipv4_hdrerr_octets Register
28782  *
28783  */
28784 /*
28785  * Field : rxipv4_hdrerr_octets Register - cnt
28786  *
28787  * Number of bytes received in IPv4 datagrams with header errors (checksum, length,
28788  * version mismatch). The value in the Length field of IPv4 header is used to
28789  * update this counter
28790  *
28791  * Field Access Macros:
28792  *
28793  */
28794 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field. */
28795 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_LSB 0
28796 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field. */
28797 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_MSB 31
28798 /* The width in bits of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field. */
28799 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_WIDTH 32
28800 /* The mask used to set the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field value. */
28801 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_SET_MSK 0xffffffff
28802 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field value. */
28803 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_CLR_MSK 0x00000000
28804 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field. */
28805 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_RESET 0x0
28806 /* Extracts the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT field value from a register. */
28807 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
28808 /* Produces a ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field value suitable for setting the register. */
28809 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
28810 
28811 #ifndef __ASSEMBLY__
28812 /*
28813  * WARNING: The C register and register group struct declarations are provided for
28814  * convenience and illustrative purposes. They should, however, be used with
28815  * caution as the C language standard provides no guarantees about the alignment or
28816  * atomicity of device memory accesses. The recommended practice for writing
28817  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28818  * alt_write_word() functions.
28819  *
28820  * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS.
28821  */
28822 struct ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_s
28823 {
28824  const uint32_t cnt : 32; /* rxipv4_hdrerr_octets Register */
28825 };
28826 
28827 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS. */
28828 typedef volatile struct ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_s ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_t;
28829 #endif /* __ASSEMBLY__ */
28830 
28831 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS register. */
28832 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_RESET 0x00000000
28833 /* The byte offset of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS register from the beginning of the component. */
28834 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_OFST 0x254
28835 /* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS register. */
28836 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_OFST))
28837 
28838 /*
28839  * Register : Register 150 (rxipv4_nopay_octets Register) - gmacgrp_rxipv4_nopay_octets
28840  *
28841  * Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP
28842  * payload. The value in the IPv4 headers Length field is used to update this
28843  * counter
28844  *
28845  * Register Layout
28846  *
28847  * Bits | Access | Reset | Description
28848  * :-------|:-------|:------|:--------------------
28849  * [31:0] | R | 0x0 | rxipv4_nopay_octets
28850  *
28851  */
28852 /*
28853  * Field : rxipv4_nopay_octets - cnt
28854  *
28855  * Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP
28856  * payload. The value in the IPv4 headers Length field is used to update this
28857  * counter
28858  *
28859  * Field Access Macros:
28860  *
28861  */
28862 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field. */
28863 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_LSB 0
28864 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field. */
28865 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_MSB 31
28866 /* The width in bits of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field. */
28867 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_WIDTH 32
28868 /* The mask used to set the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field value. */
28869 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_SET_MSK 0xffffffff
28870 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field value. */
28871 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_CLR_MSK 0x00000000
28872 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field. */
28873 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_RESET 0x0
28874 /* Extracts the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT field value from a register. */
28875 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
28876 /* Produces a ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field value suitable for setting the register. */
28877 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
28878 
28879 #ifndef __ASSEMBLY__
28880 /*
28881  * WARNING: The C register and register group struct declarations are provided for
28882  * convenience and illustrative purposes. They should, however, be used with
28883  * caution as the C language standard provides no guarantees about the alignment or
28884  * atomicity of device memory accesses. The recommended practice for writing
28885  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28886  * alt_write_word() functions.
28887  *
28888  * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS.
28889  */
28890 struct ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_s
28891 {
28892  const uint32_t cnt : 32; /* rxipv4_nopay_octets */
28893 };
28894 
28895 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS. */
28896 typedef volatile struct ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_s ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_t;
28897 #endif /* __ASSEMBLY__ */
28898 
28899 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS register. */
28900 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_RESET 0x00000000
28901 /* The byte offset of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS register from the beginning of the component. */
28902 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_OFST 0x258
28903 /* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS register. */
28904 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_OFST))
28905 
28906 /*
28907  * Register : Register 151 (rxipv4_frag_octets Register) - gmacgrp_rxipv4_frag_octets
28908  *
28909  * Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4
28910  * headers Length field is used to update this counter
28911  *
28912  * Register Layout
28913  *
28914  * Bits | Access | Reset | Description
28915  * :-------|:-------|:------|:-------------------
28916  * [31:0] | R | 0x0 | rxipv4_frag_octets
28917  *
28918  */
28919 /*
28920  * Field : rxipv4_frag_octets - cnt
28921  *
28922  * Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4
28923  * headers Length field is used to update this counter
28924  *
28925  * Field Access Macros:
28926  *
28927  */
28928 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field. */
28929 #define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_LSB 0
28930 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field. */
28931 #define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_MSB 31
28932 /* The width in bits of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field. */
28933 #define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_WIDTH 32
28934 /* The mask used to set the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field value. */
28935 #define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_SET_MSK 0xffffffff
28936 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field value. */
28937 #define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_CLR_MSK 0x00000000
28938 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field. */
28939 #define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_RESET 0x0
28940 /* Extracts the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT field value from a register. */
28941 #define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
28942 /* Produces a ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field value suitable for setting the register. */
28943 #define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
28944 
28945 #ifndef __ASSEMBLY__
28946 /*
28947  * WARNING: The C register and register group struct declarations are provided for
28948  * convenience and illustrative purposes. They should, however, be used with
28949  * caution as the C language standard provides no guarantees about the alignment or
28950  * atomicity of device memory accesses. The recommended practice for writing
28951  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28952  * alt_write_word() functions.
28953  *
28954  * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS.
28955  */
28956 struct ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_s
28957 {
28958  const uint32_t cnt : 32; /* rxipv4_frag_octets */
28959 };
28960 
28961 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS. */
28962 typedef volatile struct ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_s ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_t;
28963 #endif /* __ASSEMBLY__ */
28964 
28965 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS register. */
28966 #define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_RESET 0x00000000
28967 /* The byte offset of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS register from the beginning of the component. */
28968 #define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_OFST 0x25c
28969 /* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS register. */
28970 #define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_OFST))
28971 
28972 /*
28973  * Register : Register 152 (rxipv4_udsbl_octets Register) - gmacgrp_rxipv4_udsbl_octets
28974  *
28975  * Number of bytes received in a UDP segment that had the UDP checksum disabled.
28976  * This counter does not count IP Header bytes
28977  *
28978  * Register Layout
28979  *
28980  * Bits | Access | Reset | Description
28981  * :-------|:-------|:------|:--------------------
28982  * [31:0] | R | 0x0 | rxipv4_udsbl_octets
28983  *
28984  */
28985 /*
28986  * Field : rxipv4_udsbl_octets - cnt
28987  *
28988  * Number of bytes received in a UDP segment that had the UDP checksum disabled.
28989  * This counter does not count IP Header bytes
28990  *
28991  * Field Access Macros:
28992  *
28993  */
28994 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field. */
28995 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_LSB 0
28996 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field. */
28997 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_MSB 31
28998 /* The width in bits of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field. */
28999 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_WIDTH 32
29000 /* The mask used to set the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field value. */
29001 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_SET_MSK 0xffffffff
29002 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field value. */
29003 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_CLR_MSK 0x00000000
29004 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field. */
29005 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_RESET 0x0
29006 /* Extracts the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT field value from a register. */
29007 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
29008 /* Produces a ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field value suitable for setting the register. */
29009 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
29010 
29011 #ifndef __ASSEMBLY__
29012 /*
29013  * WARNING: The C register and register group struct declarations are provided for
29014  * convenience and illustrative purposes. They should, however, be used with
29015  * caution as the C language standard provides no guarantees about the alignment or
29016  * atomicity of device memory accesses. The recommended practice for writing
29017  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
29018  * alt_write_word() functions.
29019  *
29020  * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS.
29021  */
29022 struct ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_s
29023 {
29024  const uint32_t cnt : 32; /* rxipv4_udsbl_octets */
29025 };
29026 
29027 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS. */
29028 typedef volatile struct ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_s ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_t;
29029 #endif /* __ASSEMBLY__ */
29030 
29031 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS register. */
29032 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_RESET 0x00000000
29033 /* The byte offset of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS register from the beginning of the component. */
29034 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_OFST 0x260
29035 /* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS register. */
29036 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_OFST))
29037 
29038 /*
29039  * Register : Register 153 (rxipv6_gd_octets Register) - gmacgrp_rxipv6_gd_octets
29040  *
29041  * Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6
29042  * data
29043  *
29044  * Register Layout
29045  *
29046  * Bits | Access | Reset | Description
29047  * :-------|:-------|:------|:-----------------
29048  * [31:0] | R | 0x0 | rxipv6_gd_octets
29049  *
29050  */
29051 /*
29052  * Field : rxipv6_gd_octets - cnt
29053  *
29054  * Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6
29055  * data
29056  *
29057  * Field Access Macros:
29058  *
29059  */
29060 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field. */
29061 #define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_LSB 0
29062 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field. */
29063 #define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_MSB 31
29064 /* The width in bits of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field. */
29065 #define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_WIDTH 32
29066 /* The mask used to set the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field value. */
29067 #define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_SET_MSK 0xffffffff
29068 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field value. */
29069 #define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_CLR_MSK 0x00000000
29070 /* The reset value of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field. */
29071 #define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_RESET 0x0
29072 /* Extracts the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT field value from a register. */
29073 #define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
29074 /* Produces a ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field value suitable for setting the register. */
29075 #define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
29076 
29077 #ifndef __ASSEMBLY__
29078 /*
29079  * WARNING: The C register and register group struct declarations are provided for
29080  * convenience and illustrative purposes. They should, however, be used with
29081  * caution as the C language standard provides no guarantees about the alignment or
29082  * atomicity of device memory accesses. The recommended practice for writing
29083  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
29084  * alt_write_word() functions.
29085  *
29086  * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_GD_OCTETS.
29087  */
29088 struct ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_s
29089 {
29090  const uint32_t cnt : 32; /* rxipv6_gd_octets */
29091 };
29092 
29093 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_GD_OCTETS. */
29094 typedef volatile struct ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_s ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_t;
29095 #endif /* __ASSEMBLY__ */
29096 
29097 /* The reset value of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS register. */
29098 #define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_RESET 0x00000000
29099 /* The byte offset of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS register from the beginning of the component. */
29100 #define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_OFST 0x264
29101 /* The address of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS register. */
29102 #define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_OFST))
29103 
29104 /*
29105  * Register : Register 154 (rxipv6_hdrerr_octets Register) - gmacgrp_rxipv6_hdrerr_octets
29106  *
29107  * Number of bytes received in IPv6 datagrams with header errors (length, version
29108  * mismatch). The value in the IPv6 headers Length field is used to update this
29109  * counter
29110  *
29111  * Register Layout
29112  *
29113  * Bits | Access | Reset | Description
29114  * :-------|:-------|:------|:---------------------
29115  * [31:0] | R | 0x0 | rxipv6_hdrerr_octets
29116  *
29117  */
29118 /*
29119  * Field : rxipv6_hdrerr_octets - cnt
29120  *
29121  * Number of bytes received in IPv6 datagrams with header errors (length, version
29122  * mismatch). The value in the IPv6 headers Length field is used to update this
29123  * counter
29124  *
29125  * Field Access Macros:
29126  *
29127  */
29128 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field. */
29129 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_LSB 0
29130 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field. */
29131 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_MSB 31
29132 /* The width in bits of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field. */
29133 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_WIDTH 32
29134 /* The mask used to set the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field value. */
29135 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_SET_MSK 0xffffffff
29136 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field value. */
29137 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_CLR_MSK 0x00000000
29138 /* The reset value of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field. */
29139 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_RESET 0x0
29140 /* Extracts the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT field value from a register. */
29141 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
29142 /* Produces a ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field value suitable for setting the register. */
29143 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
29144 
29145 #ifndef __ASSEMBLY__
29146 /*
29147  * WARNING: The C register and register group struct declarations are provided for
29148  * convenience and illustrative purposes. They should, however, be used with
29149  * caution as the C language standard provides no guarantees about the alignment or
29150  * atomicity of device memory accesses. The recommended practice for writing
29151  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
29152  * alt_write_word() functions.
29153  *
29154  * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS.
29155  */
29156 struct ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_s
29157 {
29158  const uint32_t cnt : 32; /* rxipv6_hdrerr_octets */
29159 };
29160 
29161 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS. */
29162 typedef volatile struct ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_s ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_t;
29163 #endif /* __ASSEMBLY__ */
29164 
29165 /* The reset value of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS register. */
29166 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_RESET 0x00000000
29167 /* The byte offset of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS register from the beginning of the component. */
29168 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_OFST 0x268
29169 /* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS register. */
29170 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_OFST))
29171 
29172 /*
29173  * Register : Register 155 (rxipv6_nopay_octets Register) - gmacgrp_rxipv6_nopay_octets
29174  *
29175  * Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP
29176  * payload. The value in the IPv6 headers Length field is used to update this
29177  * counter
29178  *
29179  * Register Layout
29180  *
29181  * Bits | Access | Reset | Description
29182  * :-------|:-------|:------|:--------------------
29183  * [31:0] | R | 0x0 | rxipv6_nopay_octets
29184  *
29185  */
29186 /*
29187  * Field : rxipv6_nopay_octets - cnt
29188  *
29189  * Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP
29190  * payload. The value in the IPv6 headers Length field is used to update this
29191  * counter
29192  *
29193  * Field Access Macros:
29194  *
29195  */
29196 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field. */
29197 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_LSB 0
29198 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field. */
29199 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_MSB 31
29200 /* The width in bits of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field. */
29201 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_WIDTH 32
29202 /* The mask used to set the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field value. */
29203 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_SET_MSK 0xffffffff
29204 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field value. */
29205 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_CLR_MSK 0x00000000
29206 /* The reset value of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field. */
29207 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_RESET 0x0
29208 /* Extracts the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT field value from a register. */
29209 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
29210 /* Produces a ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field value suitable for setting the register. */
29211 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
29212 
29213 #ifndef __ASSEMBLY__
29214 /*
29215  * WARNING: The C register and register group struct declarations are provided for
29216  * convenience and illustrative purposes. They should, however, be used with
29217  * caution as the C language standard provides no guarantees about the alignment or
29218  * atomicity of device memory accesses. The recommended practice for writing
29219  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
29220  * alt_write_word() functions.
29221  *
29222  * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS.
29223  */
29224 struct ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_s
29225 {
29226  const uint32_t cnt : 32; /* rxipv6_nopay_octets */
29227 };
29228 
29229 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS. */
29230 typedef volatile struct ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_s ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_t;
29231 #endif /* __ASSEMBLY__ */
29232 
29233 /* The reset value of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS register. */
29234 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_RESET 0x00000000
29235 /* The byte offset of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS register from the beginning of the component. */
29236 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_OFST 0x26c
29237 /* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS register. */
29238 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_OFST))
29239 
29240 /*
29241  * Register : Register 156 (rxudp_gd_octets Register) - gmacgrp_rxudp_gd_octets
29242  *
29243  * Number of bytes received in a good UDP segment. This counter does not count IP
29244  * header bytes
29245  *
29246  * Register Layout
29247  *
29248  * Bits | Access | Reset | Description
29249  * :-------|:-------|:------|:----------------
29250  * [31:0] | R | 0x0 | rxudp_gd_octets
29251  *
29252  */
29253 /*
29254  * Field : rxudp_gd_octets - cnt
29255  *
29256  * Number of bytes received in a good UDP segment. This counter does not count IP
29257  * header bytes
29258  *
29259  * Field Access Macros:
29260  *
29261  */
29262 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field. */
29263 #define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_LSB 0
29264 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field. */
29265 #define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_MSB 31
29266 /* The width in bits of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field. */
29267 #define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_WIDTH 32
29268 /* The mask used to set the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field value. */
29269 #define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_SET_MSK 0xffffffff
29270 /* The mask used to clear the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field value. */
29271 #define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_CLR_MSK 0x00000000
29272 /* The reset value of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field. */
29273 #define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_RESET 0x0
29274 /* Extracts the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT field value from a register. */
29275 #define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
29276 /* Produces a ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field value suitable for setting the register. */
29277 #define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
29278 
29279 #ifndef __ASSEMBLY__
29280 /*
29281  * WARNING: The C register and register group struct declarations are provided for
29282  * convenience and illustrative purposes. They should, however, be used with
29283  * caution as the C language standard provides no guarantees about the alignment or
29284  * atomicity of device memory accesses. The recommended practice for writing
29285  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
29286  * alt_write_word() functions.
29287  *
29288  * The struct declaration for register ALT_EMAC_GMAC_RXUDP_GD_OCTETS.
29289  */
29290 struct ALT_EMAC_GMAC_RXUDP_GD_OCTETS_s
29291 {
29292  const uint32_t cnt : 32; /* rxudp_gd_octets */
29293 };
29294 
29295 /* The typedef declaration for register ALT_EMAC_GMAC_RXUDP_GD_OCTETS. */
29296 typedef volatile struct ALT_EMAC_GMAC_RXUDP_GD_OCTETS_s ALT_EMAC_GMAC_RXUDP_GD_OCTETS_t;
29297 #endif /* __ASSEMBLY__ */
29298 
29299 /* The reset value of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS register. */
29300 #define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_RESET 0x00000000
29301 /* The byte offset of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS register from the beginning of the component. */
29302 #define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_OFST 0x270
29303 /* The address of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS register. */
29304 #define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUDP_GD_OCTETS_OFST))
29305 
29306 /*
29307  * Register : Register 157 (rxudp_err_octets Register) - gmacgrp_rxudp_err_octets
29308  *
29309  * Number of bytes received in a UDP segment that had checksum errors
29310  *
29311  * Register Layout
29312  *
29313  * Bits | Access | Reset | Description
29314  * :-------|:-------|:------|:-----------------
29315  * [31:0] | R | 0x0 | rxudp_err_octets
29316  *
29317  */
29318 /*
29319  * Field : rxudp_err_octets - cnt
29320  *
29321  * Number of bytes received in a UDP segment that had checksum errors
29322  *
29323  * Field Access Macros:
29324  *
29325  */
29326 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field. */
29327 #define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_LSB 0
29328 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field. */
29329 #define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_MSB 31
29330 /* The width in bits of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field. */
29331 #define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_WIDTH 32
29332 /* The mask used to set the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field value. */
29333 #define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_SET_MSK 0xffffffff
29334 /* The mask used to clear the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field value. */
29335 #define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_CLR_MSK 0x00000000
29336 /* The reset value of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field. */
29337 #define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_RESET 0x0
29338 /* Extracts the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT field value from a register. */
29339 #define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
29340 /* Produces a ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field value suitable for setting the register. */
29341 #define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
29342 
29343 #ifndef __ASSEMBLY__
29344 /*
29345  * WARNING: The C register and register group struct declarations are provided for
29346  * convenience and illustrative purposes. They should, however, be used with
29347  * caution as the C language standard provides no guarantees about the alignment or
29348  * atomicity of device memory accesses. The recommended practice for writing
29349  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
29350  * alt_write_word() functions.
29351  *
29352  * The struct declaration for register ALT_EMAC_GMAC_RXUDP_ERR_OCTETS.
29353  */
29354 struct ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_s
29355 {
29356  const uint32_t cnt : 32; /* rxudp_err_octets */
29357 };
29358 
29359 /* The typedef declaration for register ALT_EMAC_GMAC_RXUDP_ERR_OCTETS. */
29360 typedef volatile struct ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_s ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_t;
29361 #endif /* __ASSEMBLY__ */
29362 
29363 /* The reset value of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS register. */
29364 #define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_RESET 0x00000000
29365 /* The byte offset of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS register from the beginning of the component. */
29366 #define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_OFST 0x274
29367 /* The address of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS register. */
29368 #define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_OFST))
29369 
29370 /*
29371  * Register : Register 158 (rxtcp_gd_octets Register) - gmacgrp_rxtcp_gd_octets
29372  *
29373  * Number of bytes received in a good TCP segment
29374  *
29375  * Register Layout
29376  *
29377  * Bits | Access | Reset | Description
29378  * :-------|:-------|:------|:----------------
29379  * [31:0] | R | 0x0 | rxtcp_gd_octets
29380  *
29381  */
29382 /*
29383  * Field : rxtcp_gd_octets - cnt
29384  *
29385  * Number of bytes received in a good TCP segment
29386  *
29387  * Field Access Macros:
29388  *
29389  */
29390 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field. */
29391 #define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_LSB 0
29392 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field. */
29393 #define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_MSB 31
29394 /* The width in bits of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field. */
29395 #define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_WIDTH 32
29396 /* The mask used to set the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field value. */
29397 #define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_SET_MSK 0xffffffff
29398 /* The mask used to clear the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field value. */
29399 #define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_CLR_MSK 0x00000000
29400 /* The reset value of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field. */
29401 #define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_RESET 0x0
29402 /* Extracts the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT field value from a register. */
29403 #define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
29404 /* Produces a ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field value suitable for setting the register. */
29405 #define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
29406 
29407 #ifndef __ASSEMBLY__
29408 /*
29409  * WARNING: The C register and register group struct declarations are provided for
29410  * convenience and illustrative purposes. They should, however, be used with
29411  * caution as the C language standard provides no guarantees about the alignment or
29412  * atomicity of device memory accesses. The recommended practice for writing
29413  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
29414  * alt_write_word() functions.
29415  *
29416  * The struct declaration for register ALT_EMAC_GMAC_RXTCP_GD_OCTETS.
29417  */
29418 struct ALT_EMAC_GMAC_RXTCP_GD_OCTETS_s
29419 {
29420  const uint32_t cnt : 32; /* rxtcp_gd_octets */
29421 };
29422 
29423 /* The typedef declaration for register ALT_EMAC_GMAC_RXTCP_GD_OCTETS. */
29424 typedef volatile struct ALT_EMAC_GMAC_RXTCP_GD_OCTETS_s ALT_EMAC_GMAC_RXTCP_GD_OCTETS_t;
29425 #endif /* __ASSEMBLY__ */
29426 
29427 /* The reset value of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS register. */
29428 #define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_RESET 0x00000000
29429 /* The byte offset of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS register from the beginning of the component. */
29430 #define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_OFST 0x278
29431 /* The address of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS register. */
29432 #define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXTCP_GD_OCTETS_OFST))
29433 
29434 /*
29435  * Register : Register 159 (rxtcp_err_octets Register) - gmacgrp_rxtcperroctets
29436  *
29437  * Number of bytes received in a TCP segment with checksum errors
29438  *
29439  * Register Layout
29440  *
29441  * Bits | Access | Reset | Description
29442  * :-------|:-------|:------|:-----------------
29443  * [31:0] | R | 0x0 | rxtcp_err_octets
29444  *
29445  */
29446 /*
29447  * Field : rxtcp_err_octets - rxtcp_err_octets
29448  *
29449  * Number of bytes received in a TCP segment with checksum errors
29450  *
29451  * Field Access Macros:
29452  *
29453  */
29454 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field. */
29455 #define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_LSB 0
29456 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field. */
29457 #define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_MSB 31
29458 /* The width in bits of the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field. */
29459 #define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_WIDTH 32
29460 /* The mask used to set the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field value. */
29461 #define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_SET_MSK 0xffffffff
29462 /* The mask used to clear the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field value. */
29463 #define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_CLR_MSK 0x00000000
29464 /* The reset value of the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field. */
29465 #define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_RESET 0x0
29466 /* Extracts the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS field value from a register. */
29467 #define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_GET(value) (((value) & 0xffffffff) >> 0)
29468 /* Produces a ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field value suitable for setting the register. */
29469 #define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_SET(value) (((value) << 0) & 0xffffffff)
29470 
29471 #ifndef __ASSEMBLY__
29472 /*
29473  * WARNING: The C register and register group struct declarations are provided for
29474  * convenience and illustrative purposes. They should, however, be used with
29475  * caution as the C language standard provides no guarantees about the alignment or
29476  * atomicity of device memory accesses. The recommended practice for writing
29477  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
29478  * alt_write_word() functions.
29479  *
29480  * The struct declaration for register ALT_EMAC_GMAC_RXTCPERROCTETS.
29481  */
29482 struct ALT_EMAC_GMAC_RXTCPERROCTETS_s
29483 {
29484  const uint32_t rxtcp_err_octets : 32; /* rxtcp_err_octets */
29485 };
29486 
29487 /* The typedef declaration for register ALT_EMAC_GMAC_RXTCPERROCTETS. */
29488 typedef volatile struct ALT_EMAC_GMAC_RXTCPERROCTETS_s ALT_EMAC_GMAC_RXTCPERROCTETS_t;
29489 #endif /* __ASSEMBLY__ */
29490 
29491 /* The reset value of the ALT_EMAC_GMAC_RXTCPERROCTETS register. */
29492 #define ALT_EMAC_GMAC_RXTCPERROCTETS_RESET 0x00000000
29493 /* The byte offset of the ALT_EMAC_GMAC_RXTCPERROCTETS register from the beginning of the component. */
29494 #define ALT_EMAC_GMAC_RXTCPERROCTETS_OFST 0x27c
29495 /* The address of the ALT_EMAC_GMAC_RXTCPERROCTETS register. */
29496 #define ALT_EMAC_GMAC_RXTCPERROCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXTCPERROCTETS_OFST))
29497 
29498 /*
29499  * Register : Register 160 (rxicmp_gd_octets Register) - gmacgrp_rxicmp_gd_octets
29500  *
29501  * Number of bytes received in a good ICMP segment
29502  *
29503  * Register Layout
29504  *
29505  * Bits | Access | Reset | Description
29506  * :-------|:-------|:------|:-----------------
29507  * [31:0] | R | 0x0 | rxicmp_gd_octets
29508  *
29509  */
29510 /*
29511  * Field : rxicmp_gd_octets - cnt
29512  *
29513  * Number of bytes received in a good ICMP segment
29514  *
29515  * Field Access Macros:
29516  *
29517  */
29518 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field. */
29519 #define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_LSB 0
29520 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field. */
29521 #define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_MSB 31
29522 /* The width in bits of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field. */
29523 #define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_WIDTH 32
29524 /* The mask used to set the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field value. */
29525 #define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_SET_MSK 0xffffffff
29526 /* The mask used to clear the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field value. */
29527 #define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_CLR_MSK 0x00000000
29528 /* The reset value of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field. */
29529 #define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_RESET 0x0
29530 /* Extracts the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT field value from a register. */
29531 #define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
29532 /* Produces a ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field value suitable for setting the register. */
29533 #define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
29534 
29535 #ifndef __ASSEMBLY__
29536 /*
29537  * WARNING: The C register and register group struct declarations are provided for
29538  * convenience and illustrative purposes. They should, however, be used with
29539  * caution as the C language standard provides no guarantees about the alignment or
29540  * atomicity of device memory accesses. The recommended practice for writing
29541  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
29542  * alt_write_word() functions.
29543  *
29544  * The struct declaration for register ALT_EMAC_GMAC_RXICMP_GD_OCTETS.
29545  */
29546 struct ALT_EMAC_GMAC_RXICMP_GD_OCTETS_s
29547 {
29548  const uint32_t cnt : 32; /* rxicmp_gd_octets */
29549 };
29550 
29551 /* The typedef declaration for register ALT_EMAC_GMAC_RXICMP_GD_OCTETS. */
29552 typedef volatile struct ALT_EMAC_GMAC_RXICMP_GD_OCTETS_s ALT_EMAC_GMAC_RXICMP_GD_OCTETS_t;
29553 #endif /* __ASSEMBLY__ */
29554 
29555 /* The reset value of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS register. */
29556 #define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_RESET 0x00000000
29557 /* The byte offset of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS register from the beginning of the component. */
29558 #define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_OFST 0x280
29559 /* The address of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS register. */
29560 #define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXICMP_GD_OCTETS_OFST))
29561 
29562 /*
29563  * Register : Register 161 (rxicmp_err_octets Register) - gmacgrp_rxicmp_err_octets
29564  *
29565  * Number of bytes received in an ICMP segment with checksum errors
29566  *
29567  * Register Layout
29568  *
29569  * Bits | Access | Reset | Description
29570  * :-------|:-------|:------|:------------------
29571  * [31:0] | R | 0x0 | rxicmp_err_octets
29572  *
29573  */
29574 /*
29575  * Field : rxicmp_err_octets - cnt
29576  *
29577  * Number of bytes received in an ICMP segment with checksum errors
29578  *
29579  * Field Access Macros:
29580  *
29581  */
29582 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field. */
29583 #define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_LSB 0
29584 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field. */
29585 #define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_MSB 31
29586 /* The width in bits of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field. */
29587 #define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_WIDTH 32
29588 /* The mask used to set the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field value. */
29589 #define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_SET_MSK 0xffffffff
29590 /* The mask used to clear the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field value. */
29591 #define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_CLR_MSK 0x00000000
29592 /* The reset value of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field. */
29593 #define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_RESET 0x0
29594 /* Extracts the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT field value from a register. */
29595 #define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
29596 /* Produces a ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field value suitable for setting the register. */
29597 #define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
29598 
29599 #ifndef __ASSEMBLY__
29600 /*
29601  * WARNING: The C register and register group struct declarations are provided for
29602  * convenience and illustrative purposes. They should, however, be used with
29603  * caution as the C language standard provides no guarantees about the alignment or
29604  * atomicity of device memory accesses. The recommended practice for writing
29605  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
29606  * alt_write_word() functions.
29607  *
29608  * The struct declaration for register ALT_EMAC_GMAC_RXICMP_ERR_OCTETS.
29609  */
29610 struct ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_s
29611 {
29612  const uint32_t cnt : 32; /* rxicmp_err_octets */
29613 };
29614 
29615 /* The typedef declaration for register ALT_EMAC_GMAC_RXICMP_ERR_OCTETS. */
29616 typedef volatile struct ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_s ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_t;
29617 #endif /* __ASSEMBLY__ */
29618 
29619 /* The reset value of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS register. */
29620 #define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_RESET 0x00000000
29621 /* The byte offset of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS register from the beginning of the component. */
29622 #define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_OFST 0x284
29623 /* The address of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS register. */
29624 #define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_OFST))
29625 
29626 /*
29627  * Register : gmacgrp_l3_l4_control0
29628  *
29629  * <b> Register 256 (Layer 3 and Layer 4 Control Register 0) </b>
29630  *
29631  * This register controls the operations of the filter 0 of Layer 3 and Layer 4.
29632  * This register is reserved if the Layer 3 and Layer 4 Filtering feature is not
29633  * selected during core configuration.
29634  *
29635  * Register Layout
29636  *
29637  * Bits | Access | Reset | Description
29638  * :--------|:-------|:------|:------------------------------------
29639  * [0] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0
29640  * [1] | R | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1
29641  * [2] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0
29642  * [3] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0
29643  * [4] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0
29644  * [5] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0
29645  * [10:6] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0
29646  * [15:11] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0
29647  * [16] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0
29648  * [17] | R | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17
29649  * [18] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0
29650  * [19] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0
29651  * [20] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0
29652  * [21] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0
29653  * [31:22] | R | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22
29654  *
29655  */
29656 /*
29657  * Field : l3pen0
29658  *
29659  * Layer 3 Protocol Enable
29660  *
29661  * When set, this bit indicates that the Layer 3 IP Source or Destination Address
29662  * matching is enabled for the IPv6 frames. When reset, this bit indicates that the
29663  * Layer 3 IP Source or Destination Address matching is enabled for the IPv4
29664  * frames.
29665  *
29666  * The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high.
29667  *
29668  * Field Access Macros:
29669  *
29670  */
29671 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field. */
29672 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_LSB 0
29673 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field. */
29674 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_MSB 0
29675 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field. */
29676 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_WIDTH 1
29677 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field value. */
29678 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_SET_MSK 0x00000001
29679 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field value. */
29680 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_CLR_MSK 0xfffffffe
29681 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field. */
29682 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_RESET 0x0
29683 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 field value from a register. */
29684 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_GET(value) (((value) & 0x00000001) >> 0)
29685 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field value suitable for setting the register. */
29686 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_SET(value) (((value) << 0) & 0x00000001)
29687 
29688 /*
29689  * Field : reserved_1
29690  *
29691  * Reserved
29692  *
29693  * Field Access Macros:
29694  *
29695  */
29696 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1 register field. */
29697 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_LSB 1
29698 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1 register field. */
29699 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_MSB 1
29700 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1 register field. */
29701 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_WIDTH 1
29702 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1 register field value. */
29703 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_SET_MSK 0x00000002
29704 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1 register field value. */
29705 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_CLR_MSK 0xfffffffd
29706 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1 register field. */
29707 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_RESET 0x0
29708 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1 field value from a register. */
29709 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_GET(value) (((value) & 0x00000002) >> 1)
29710 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1 register field value suitable for setting the register. */
29711 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_SET(value) (((value) << 1) & 0x00000002)
29712 
29713 /*
29714  * Field : l3sam0
29715  *
29716  * Layer 3 IP SA Match Enable
29717  *
29718  * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
29719  * for matching. When reset, the MAC ignores the Layer 3 IP Source Address field
29720  * for matching.
29721  *
29722  * Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 4
29723  * (L3DAM0) because either IPv6 SA or DA can be checked for filtering.
29724  *
29725  * Field Access Macros:
29726  *
29727  */
29728 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field. */
29729 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_LSB 2
29730 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field. */
29731 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_MSB 2
29732 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field. */
29733 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_WIDTH 1
29734 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field value. */
29735 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_SET_MSK 0x00000004
29736 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field value. */
29737 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_CLR_MSK 0xfffffffb
29738 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field. */
29739 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_RESET 0x0
29740 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 field value from a register. */
29741 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_GET(value) (((value) & 0x00000004) >> 2)
29742 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field value suitable for setting the register. */
29743 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_SET(value) (((value) << 2) & 0x00000004)
29744 
29745 /*
29746  * Field : l3saim0
29747  *
29748  * Layer 3 IP SA Inverse Match Enable
29749  *
29750  * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
29751  * for inverse matching. When reset, this bit indicates that the Layer 3 IP Source
29752  * Address field is enabled for perfect matching.
29753  *
29754  * This bit is valid and applicable only when Bit 2 (L3SAM0) is set high.
29755  *
29756  * Field Access Macros:
29757  *
29758  */
29759 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field. */
29760 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_LSB 3
29761 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field. */
29762 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_MSB 3
29763 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field. */
29764 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_WIDTH 1
29765 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field value. */
29766 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_SET_MSK 0x00000008
29767 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field value. */
29768 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_CLR_MSK 0xfffffff7
29769 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field. */
29770 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_RESET 0x0
29771 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 field value from a register. */
29772 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_GET(value) (((value) & 0x00000008) >> 3)
29773 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field value suitable for setting the register. */
29774 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_SET(value) (((value) << 3) & 0x00000008)
29775 
29776 /*
29777  * Field : l3dam0
29778  *
29779  * Layer 3 IP DA Match Enable
29780  *
29781  * When set, this bit indicates that Layer 3 IP Destination Address field is
29782  * enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination
29783  * Address field for matching.
29784  *
29785  * Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2
29786  * (L3SAM0) because either IPv6 DA or SA can be checked for filtering.
29787  *
29788  * Field Access Macros:
29789  *
29790  */
29791 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field. */
29792 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_LSB 4
29793 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field. */
29794 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_MSB 4
29795 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field. */
29796 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_WIDTH 1
29797 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field value. */
29798 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_SET_MSK 0x00000010
29799 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field value. */
29800 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_CLR_MSK 0xffffffef
29801 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field. */
29802 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_RESET 0x0
29803 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 field value from a register. */
29804 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_GET(value) (((value) & 0x00000010) >> 4)
29805 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field value suitable for setting the register. */
29806 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_SET(value) (((value) << 4) & 0x00000010)
29807 
29808 /*
29809  * Field : l3daim0
29810  *
29811  * Layer 3 IP DA Inverse Match Enable
29812  *
29813  * When set, this bit indicates that the Layer 3 IP Destination Address field is
29814  * enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP
29815  * Destination Address field is enabled for perfect matching.
29816  *
29817  * This bit is valid and applicable only when Bit 4 (L3DAM0) is set high.
29818  *
29819  * Field Access Macros:
29820  *
29821  */
29822 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field. */
29823 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_LSB 5
29824 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field. */
29825 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_MSB 5
29826 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field. */
29827 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_WIDTH 1
29828 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field value. */
29829 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_SET_MSK 0x00000020
29830 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field value. */
29831 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_CLR_MSK 0xffffffdf
29832 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field. */
29833 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_RESET 0x0
29834 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 field value from a register. */
29835 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_GET(value) (((value) & 0x00000020) >> 5)
29836 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field value suitable for setting the register. */
29837 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_SET(value) (((value) << 5) & 0x00000020)
29838 
29839 /*
29840  * Field : l3hsbm0
29841  *
29842  * Layer 3 IP SA Higher Bits Match
29843  *
29844  * IPv4 Frames:
29845  *
29846  * This field contains the number of lower bits of IP Source Address that are
29847  * masked for matching in the IPv4 frames. The following list describes the values
29848  * of this field:
29849  *
29850  * * 0: No bits are masked.
29851  *
29852  * * 1: LSb[0] is masked.
29853  *
29854  * * 2: Two LSbs [1:0] are masked.
29855  *
29856  * * ...
29857  *
29858  * * 31: All bits except MSb are masked.
29859  *
29860  * IPv6 Frames:
29861  *
29862  * This field contains Bits [4:0] of the field that indicates the number of higher
29863  * bits of IP Source or Destination Address matched in the IPv6 frames.
29864  *
29865  * This field is valid and applicable only if L3DAM0 or L3SAM0 is set high.
29866  *
29867  * Field Access Macros:
29868  *
29869  */
29870 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field. */
29871 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_LSB 6
29872 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field. */
29873 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_MSB 10
29874 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field. */
29875 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_WIDTH 5
29876 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field value. */
29877 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_SET_MSK 0x000007c0
29878 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field value. */
29879 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_CLR_MSK 0xfffff83f
29880 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field. */
29881 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_RESET 0x0
29882 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 field value from a register. */
29883 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_GET(value) (((value) & 0x000007c0) >> 6)
29884 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field value suitable for setting the register. */
29885 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_SET(value) (((value) << 6) & 0x000007c0)
29886 
29887 /*
29888  * Field : l3hdbm0
29889  *
29890  * Layer 3 IP DA Higher Bits Match
29891  *
29892  * IPv4 Frames:
29893  *
29894  * This field contains the number of higher bits of IP Destination Address that are
29895  * matched in the IPv4 frames. The following list describes the values of this
29896  * field:
29897  *
29898  * * 0: No bits are masked.
29899  *
29900  * * 1: LSb[0] is masked.
29901  *
29902  * * 2: Two LSbs [1:0] are masked.
29903  *
29904  * * ...
29905  *
29906  * * 31: All bits except MSb are masked.
29907  *
29908  * IPv6 Frames:
29909  *
29910  * Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate
29911  * the number of lower bits of IP Source or Destination Address that are masked in
29912  * the IPv6 frames. The following list describes the concatenated values of the
29913  * L3HDBM0[1:0] and L3HSBM0 bits:
29914  *
29915  * * 0: No bits are masked.
29916  *
29917  * * 1: LSb[0] is masked.
29918  *
29919  * * 2: Two LSbs [1:0] are masked.
29920  *
29921  * * ...
29922  *
29923  * * 127: All bits except MSb are masked.
29924  *
29925  * This field is valid and applicable only if L3DAM0 or L3SAM0 is set high.
29926  *
29927  * Field Access Macros:
29928  *
29929  */
29930 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field. */
29931 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_LSB 11
29932 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field. */
29933 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_MSB 15
29934 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field. */
29935 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_WIDTH 5
29936 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field value. */
29937 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_SET_MSK 0x0000f800
29938 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field value. */
29939 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_CLR_MSK 0xffff07ff
29940 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field. */
29941 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_RESET 0x0
29942 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 field value from a register. */
29943 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_GET(value) (((value) & 0x0000f800) >> 11)
29944 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field value suitable for setting the register. */
29945 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_SET(value) (((value) << 11) & 0x0000f800)
29946 
29947 /*
29948  * Field : l4pen0
29949  *
29950  * Layer 4 Protocol Enable
29951  *
29952  * When set, this bit indicates that the Source and Destination Port number fields
29953  * for UDP frames are used for matching. When reset, this bit indicates that the
29954  * Source and Destination Port number fields for TCP frames are used for matching.
29955  *
29956  * The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high.
29957  *
29958  * Field Access Macros:
29959  *
29960  */
29961 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field. */
29962 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_LSB 16
29963 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field. */
29964 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_MSB 16
29965 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field. */
29966 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_WIDTH 1
29967 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field value. */
29968 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_SET_MSK 0x00010000
29969 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field value. */
29970 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_CLR_MSK 0xfffeffff
29971 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field. */
29972 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_RESET 0x0
29973 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 field value from a register. */
29974 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_GET(value) (((value) & 0x00010000) >> 16)
29975 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field value suitable for setting the register. */
29976 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_SET(value) (((value) << 16) & 0x00010000)
29977 
29978 /*
29979  * Field : reserved_17
29980  *
29981  * Reserved
29982  *
29983  * Field Access Macros:
29984  *
29985  */
29986 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17 register field. */
29987 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_LSB 17
29988 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17 register field. */
29989 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_MSB 17
29990 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17 register field. */
29991 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_WIDTH 1
29992 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17 register field value. */
29993 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_SET_MSK 0x00020000
29994 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17 register field value. */
29995 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_CLR_MSK 0xfffdffff
29996 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17 register field. */
29997 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_RESET 0x0
29998 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17 field value from a register. */
29999 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_GET(value) (((value) & 0x00020000) >> 17)
30000 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17 register field value suitable for setting the register. */
30001 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_SET(value) (((value) << 17) & 0x00020000)
30002 
30003 /*
30004  * Field : l4spm0
30005  *
30006  * Layer 4 Source Port Match Enable
30007  *
30008  * When set, this bit indicates that the Layer 4 Source Port number field is
30009  * enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number
30010  * field for matching.
30011  *
30012  * Field Access Macros:
30013  *
30014  */
30015 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field. */
30016 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_LSB 18
30017 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field. */
30018 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_MSB 18
30019 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field. */
30020 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_WIDTH 1
30021 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field value. */
30022 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_SET_MSK 0x00040000
30023 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field value. */
30024 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_CLR_MSK 0xfffbffff
30025 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field. */
30026 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_RESET 0x0
30027 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 field value from a register. */
30028 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_GET(value) (((value) & 0x00040000) >> 18)
30029 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field value suitable for setting the register. */
30030 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_SET(value) (((value) << 18) & 0x00040000)
30031 
30032 /*
30033  * Field : l4spim0
30034  *
30035  * Layer 4 Source Port Inverse Match Enable
30036  *
30037  * When set, this bit indicates that the Layer 4 Source Port number field is
30038  * enabled for inverse matching. When reset, this bit indicates that the Layer 4
30039  * Source Port number field is enabled for perfect matching.
30040  *
30041  * This bit is valid and applicable only when Bit 18 (L4SPM0) is set high.
30042  *
30043  * Field Access Macros:
30044  *
30045  */
30046 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field. */
30047 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_LSB 19
30048 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field. */
30049 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_MSB 19
30050 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field. */
30051 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_WIDTH 1
30052 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field value. */
30053 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_SET_MSK 0x00080000
30054 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field value. */
30055 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_CLR_MSK 0xfff7ffff
30056 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field. */
30057 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_RESET 0x0
30058 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 field value from a register. */
30059 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_GET(value) (((value) & 0x00080000) >> 19)
30060 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field value suitable for setting the register. */
30061 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_SET(value) (((value) << 19) & 0x00080000)
30062 
30063 /*
30064  * Field : l4dpm0
30065  *
30066  * Layer 4 Destination Port Match Enable
30067  *
30068  * When set, this bit indicates that the Layer 4 Destination Port number field is
30069  * enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port
30070  * number field for matching.
30071  *
30072  * Field Access Macros:
30073  *
30074  */
30075 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field. */
30076 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_LSB 20
30077 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field. */
30078 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_MSB 20
30079 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field. */
30080 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_WIDTH 1
30081 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field value. */
30082 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_SET_MSK 0x00100000
30083 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field value. */
30084 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_CLR_MSK 0xffefffff
30085 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field. */
30086 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_RESET 0x0
30087 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 field value from a register. */
30088 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_GET(value) (((value) & 0x00100000) >> 20)
30089 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field value suitable for setting the register. */
30090 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_SET(value) (((value) << 20) & 0x00100000)
30091 
30092 /*
30093  * Field : l4dpim0
30094  *
30095  * Layer 4 Destination Port Inverse Match Enable
30096  *
30097  * When set, this bit indicates that the Layer 4 Destination Port number field is
30098  * enabled for inverse matching. When reset, this bit indicates that the Layer 4
30099  * Destination Port number field is enabled for perfect matching.
30100  *
30101  * This bit is valid and applicable only when Bit 20 (L4DPM0) is set high.
30102  *
30103  * Field Access Macros:
30104  *
30105  */
30106 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field. */
30107 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_LSB 21
30108 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field. */
30109 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_MSB 21
30110 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field. */
30111 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_WIDTH 1
30112 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field value. */
30113 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_SET_MSK 0x00200000
30114 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field value. */
30115 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_CLR_MSK 0xffdfffff
30116 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field. */
30117 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_RESET 0x0
30118 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 field value from a register. */
30119 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_GET(value) (((value) & 0x00200000) >> 21)
30120 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field value suitable for setting the register. */
30121 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_SET(value) (((value) << 21) & 0x00200000)
30122 
30123 /*
30124  * Field : reserved_31_22
30125  *
30126  * Reserved
30127  *
30128  * Field Access Macros:
30129  *
30130  */
30131 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22 register field. */
30132 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_LSB 22
30133 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22 register field. */
30134 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_MSB 31
30135 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22 register field. */
30136 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_WIDTH 10
30137 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22 register field value. */
30138 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_SET_MSK 0xffc00000
30139 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22 register field value. */
30140 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_CLR_MSK 0x003fffff
30141 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22 register field. */
30142 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_RESET 0x0
30143 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22 field value from a register. */
30144 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_GET(value) (((value) & 0xffc00000) >> 22)
30145 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22 register field value suitable for setting the register. */
30146 #define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_SET(value) (((value) << 22) & 0xffc00000)
30147 
30148 #ifndef __ASSEMBLY__
30149 /*
30150  * WARNING: The C register and register group struct declarations are provided for
30151  * convenience and illustrative purposes. They should, however, be used with
30152  * caution as the C language standard provides no guarantees about the alignment or
30153  * atomicity of device memory accesses. The recommended practice for writing
30154  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
30155  * alt_write_word() functions.
30156  *
30157  * The struct declaration for register ALT_EMAC_GMAC_L3_L4_CTL0.
30158  */
30159 struct ALT_EMAC_GMAC_L3_L4_CTL0_s
30160 {
30161  uint32_t l3pen0 : 1; /* ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 */
30162  const uint32_t reserved_1 : 1; /* ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1 */
30163  uint32_t l3sam0 : 1; /* ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 */
30164  uint32_t l3saim0 : 1; /* ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 */
30165  uint32_t l3dam0 : 1; /* ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 */
30166  uint32_t l3daim0 : 1; /* ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 */
30167  uint32_t l3hsbm0 : 5; /* ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 */
30168  uint32_t l3hdbm0 : 5; /* ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 */
30169  uint32_t l4pen0 : 1; /* ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 */
30170  const uint32_t reserved_17 : 1; /* ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17 */
30171  uint32_t l4spm0 : 1; /* ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 */
30172  uint32_t l4spim0 : 1; /* ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 */
30173  uint32_t l4dpm0 : 1; /* ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 */
30174  uint32_t l4dpim0 : 1; /* ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 */
30175  const uint32_t reserved_31_22 : 10; /* ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22 */
30176 };
30177 
30178 /* The typedef declaration for register ALT_EMAC_GMAC_L3_L4_CTL0. */
30179 typedef volatile struct ALT_EMAC_GMAC_L3_L4_CTL0_s ALT_EMAC_GMAC_L3_L4_CTL0_t;
30180 #endif /* __ASSEMBLY__ */
30181 
30182 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0 register. */
30183 #define ALT_EMAC_GMAC_L3_L4_CTL0_RESET 0x00000000
30184 /* The byte offset of the ALT_EMAC_GMAC_L3_L4_CTL0 register from the beginning of the component. */
30185 #define ALT_EMAC_GMAC_L3_L4_CTL0_OFST 0x400
30186 /* The address of the ALT_EMAC_GMAC_L3_L4_CTL0 register. */
30187 #define ALT_EMAC_GMAC_L3_L4_CTL0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_L3_L4_CTL0_OFST))
30188 
30189 /*
30190  * Register : gmacgrp_layer4_address0
30191  *
30192  * <b> Register 257 (Layer 4 Address Register 0)
30193  *
30194  * </b>
30195  *
30196  * You can configure the Layer 3 and Layer 4 Address Registers to be double-
30197  * synchronized by selecting the Synchronize Layer 3 and Layer 4 Address Registers
30198  * to Rx Clock Domain option in coreConsultant. If the Layer 3 and Layer 4 Address
30199  * Registers are configured to be double-synchronized to the Rx clock domains, then
30200  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
30201  * or Bits[7:0] (in big-endian mode) of the Layer 3 and Layer 4 Address Registers
30202  * are written. For proper synchronization updates, you should perform the
30203  * consecutive writes to the same Layer 3 and Layer 4 Address Registers after at
30204  * least four clock cycles delay of the destination clock.
30205  *
30206  * If the Layer 3 and Layer 4 Filtering feature is not selected during core
30207  * configuration, this register and registers 260 through 299 are reserved (RO with
30208  * default value).
30209  *
30210  * Register Layout
30211  *
30212  * Bits | Access | Reset | Description
30213  * :--------|:-------|:------|:-------------------------------
30214  * [15:0] | RW | 0x0 | ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0
30215  * [31:16] | RW | 0x0 | ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0
30216  *
30217  */
30218 /*
30219  * Field : l4sp0
30220  *
30221  * Layer 4 Source Port Number Field
30222  *
30223  * Layer 4 Source Port Number Field
30224  *
30225  * When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer
30226  * 3 and Layer 4 Control Register 0), this field contains the value to be matched
30227  * with the TCP Source Port Number field in the IPv4 or IPv6 frames.
30228  *
30229  * When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and
30230  * Layer 4 Control Register 0), this field contains the value to be matched with
30231  * the UDP Source Port Number field in the IPv4 or IPv6 frames.
30232  *
30233  * Field Access Macros:
30234  *
30235  */
30236 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field. */
30237 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_LSB 0
30238 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field. */
30239 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_MSB 15
30240 /* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field. */
30241 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_WIDTH 16
30242 /* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field value. */
30243 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_SET_MSK 0x0000ffff
30244 /* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field value. */
30245 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_CLR_MSK 0xffff0000
30246 /* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field. */
30247 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_RESET 0x0
30248 /* Extracts the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 field value from a register. */
30249 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_GET(value) (((value) & 0x0000ffff) >> 0)
30250 /* Produces a ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field value suitable for setting the register. */
30251 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_SET(value) (((value) << 0) & 0x0000ffff)
30252 
30253 /*
30254  * Field : l4dp0
30255  *
30256  * Layer 4 Destination Port Number Field
30257  *
30258  * When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer
30259  * 3 and Layer 4 Control Register 0), this field contains the value to be matched
30260  * with the TCP Destination Port Number field in the IPv4 or IPv6 frames.
30261  *
30262  * When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and
30263  * Layer 4 Control Register 0), this field contains the value to be matched with
30264  * the UDP Destination Port Number field in the IPv4 or IPv6 frames.
30265  *
30266  * Field Access Macros:
30267  *
30268  */
30269 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field. */
30270 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_LSB 16
30271 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field. */
30272 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_MSB 31
30273 /* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field. */
30274 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_WIDTH 16
30275 /* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field value. */
30276 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_SET_MSK 0xffff0000
30277 /* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field value. */
30278 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_CLR_MSK 0x0000ffff
30279 /* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field. */
30280 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_RESET 0x0
30281 /* Extracts the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 field value from a register. */
30282 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_GET(value) (((value) & 0xffff0000) >> 16)
30283 /* Produces a ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field value suitable for setting the register. */
30284 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_SET(value) (((value) << 16) & 0xffff0000)
30285 
30286 #ifndef __ASSEMBLY__
30287 /*
30288  * WARNING: The C register and register group struct declarations are provided for
30289  * convenience and illustrative purposes. They should, however, be used with
30290  * caution as the C language standard provides no guarantees about the alignment or
30291  * atomicity of device memory accesses. The recommended practice for writing
30292  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
30293  * alt_write_word() functions.
30294  *
30295  * The struct declaration for register ALT_EMAC_GMAC_LYR4_ADDR0.
30296  */
30297 struct ALT_EMAC_GMAC_LYR4_ADDR0_s
30298 {
30299  uint32_t l4sp0 : 16; /* ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 */
30300  uint32_t l4dp0 : 16; /* ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 */
30301 };
30302 
30303 /* The typedef declaration for register ALT_EMAC_GMAC_LYR4_ADDR0. */
30304 typedef volatile struct ALT_EMAC_GMAC_LYR4_ADDR0_s ALT_EMAC_GMAC_LYR4_ADDR0_t;
30305 #endif /* __ASSEMBLY__ */
30306 
30307 /* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR0 register. */
30308 #define ALT_EMAC_GMAC_LYR4_ADDR0_RESET 0x00000000
30309 /* The byte offset of the ALT_EMAC_GMAC_LYR4_ADDR0 register from the beginning of the component. */
30310 #define ALT_EMAC_GMAC_LYR4_ADDR0_OFST 0x404
30311 /* The address of the ALT_EMAC_GMAC_LYR4_ADDR0 register. */
30312 #define ALT_EMAC_GMAC_LYR4_ADDR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR4_ADDR0_OFST))
30313 
30314 /*
30315  * Register : gmacgrp_layer3_addr0_reg0
30316  *
30317  * <b> Register 260 (Layer 3 Address 0 Register 0) </b>
30318  *
30319  * For IPv4 frames, the Layer 3 Address 0 Register 0 contains the 32-bit IP Source
30320  * Address field. For IPv6 frames, it contains Bits[31:0] of the 128-bit IP Source
30321  * Address or Destination Address field.
30322  *
30323  * Register Layout
30324  *
30325  * Bits | Access | Reset | Description
30326  * :-------|:-------|:------|:------------------------------------
30327  * [31:0] | RW | 0x0 | ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00
30328  *
30329  */
30330 /*
30331  * Field : l3a00
30332  *
30333  * Layer 3 Address 0 Field
30334  *
30335  * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and
30336  * Layer 4 Control Register 0), this field contains the value to be matched with
30337  * Bits[31:0] of the IP Source Address field in the IPv6 frames.
30338  *
30339  * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and
30340  * Layer 4 Control Register 0), this field contains the value to be matched with
30341  * Bits [31:0] of the IP Destination Address field in the IPv6 frames.
30342  *
30343  * When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3
30344  * and Layer 4 Control Register 0), this field contains the value to be matched
30345  * with the IP Source Address field in the IPv4 frames.
30346  *
30347  * Field Access Macros:
30348  *
30349  */
30350 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field. */
30351 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_LSB 0
30352 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field. */
30353 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_MSB 31
30354 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field. */
30355 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_WIDTH 32
30356 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field value. */
30357 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_SET_MSK 0xffffffff
30358 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field value. */
30359 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_CLR_MSK 0x00000000
30360 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field. */
30361 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_RESET 0x0
30362 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 field value from a register. */
30363 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_GET(value) (((value) & 0xffffffff) >> 0)
30364 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field value suitable for setting the register. */
30365 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_SET(value) (((value) << 0) & 0xffffffff)
30366 
30367 #ifndef __ASSEMBLY__
30368 /*
30369  * WARNING: The C register and register group struct declarations are provided for
30370  * convenience and illustrative purposes. They should, however, be used with
30371  * caution as the C language standard provides no guarantees about the alignment or
30372  * atomicity of device memory accesses. The recommended practice for writing
30373  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
30374  * alt_write_word() functions.
30375  *
30376  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG0.
30377  */
30378 struct ALT_EMAC_GMAC_LYR3_ADDR0_REG0_s
30379 {
30380  uint32_t l3a00 : 32; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 */
30381 };
30382 
30383 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG0. */
30384 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR0_REG0_s ALT_EMAC_GMAC_LYR3_ADDR0_REG0_t;
30385 #endif /* __ASSEMBLY__ */
30386 
30387 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0 register. */
30388 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_RESET 0x00000000
30389 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0 register from the beginning of the component. */
30390 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_OFST 0x410
30391 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0 register. */
30392 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR0_REG0_OFST))
30393 
30394 /*
30395  * Register : gmacgrp_layer3_addr1_reg0
30396  *
30397  * <b> Register 261 (Layer 3 Address 1 Register 0) </b>
30398  *
30399  * For IPv4 frames, the Layer 3 Address 1 Register 0 contains the 32-bit IP
30400  * Destination Address field. For IPv6 frames, it contains Bits[63:32] of the
30401  * 128-bit IP Source Address or Destination Address field.
30402  *
30403  * Register Layout
30404  *
30405  * Bits | Access | Reset | Description
30406  * :-------|:-------|:------|:------------------------------------
30407  * [31:0] | RW | 0x0 | ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10
30408  *
30409  */
30410 /*
30411  * Field : l3a10
30412  *
30413  * Layer 3 Address 1 Field
30414  *
30415  * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and
30416  * Layer 4 Control Register 0), this field contains the value to be matched with
30417  * Bits [63:32] of the IP Source Address field in the IPv6 frames.
30418  *
30419  * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and
30420  * Layer 4 Control Register 0), this field contains the value to be matched with
30421  * Bits [63:32] of the IP Destination Address field in the IPv6 frames.
30422  *
30423  * When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3
30424  * and Layer 4 Control Register 0), this field contains the value to be matched
30425  * with the IP Destination Address field in the IPv4 frames.
30426  *
30427  * Field Access Macros:
30428  *
30429  */
30430 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field. */
30431 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_LSB 0
30432 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field. */
30433 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_MSB 31
30434 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field. */
30435 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_WIDTH 32
30436 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field value. */
30437 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_SET_MSK 0xffffffff
30438 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field value. */
30439 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_CLR_MSK 0x00000000
30440 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field. */
30441 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_RESET 0x0
30442 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 field value from a register. */
30443 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_GET(value) (((value) & 0xffffffff) >> 0)
30444 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field value suitable for setting the register. */
30445 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_SET(value) (((value) << 0) & 0xffffffff)
30446 
30447 #ifndef __ASSEMBLY__
30448 /*
30449  * WARNING: The C register and register group struct declarations are provided for
30450  * convenience and illustrative purposes. They should, however, be used with
30451  * caution as the C language standard provides no guarantees about the alignment or
30452  * atomicity of device memory accesses. The recommended practice for writing
30453  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
30454  * alt_write_word() functions.
30455  *
30456  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG0.
30457  */
30458 struct ALT_EMAC_GMAC_LYR3_ADDR1_REG0_s
30459 {
30460  uint32_t l3a10 : 32; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 */
30461 };
30462 
30463 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG0. */
30464 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR1_REG0_s ALT_EMAC_GMAC_LYR3_ADDR1_REG0_t;
30465 #endif /* __ASSEMBLY__ */
30466 
30467 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0 register. */
30468 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_RESET 0x00000000
30469 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0 register from the beginning of the component. */
30470 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_OFST 0x414
30471 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0 register. */
30472 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR1_REG0_OFST))
30473 
30474 /*
30475  * Register : gmacgrp_layer3_addr2_reg0
30476  *
30477  * <b> Register 262 (Layer 3 Address 2 Register 0) </b>
30478  *
30479  * For IPv4 frames, the Layer 3 Address 2 Register 0 is reserved. For IPv6 frames,
30480  * it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address
30481  * field.
30482  *
30483  * Register Layout
30484  *
30485  * Bits | Access | Reset | Description
30486  * :-------|:-------|:------|:------------------------------------
30487  * [31:0] | RW | 0x0 | ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20
30488  *
30489  */
30490 /*
30491  * Field : l3a20
30492  *
30493  * Layer 3 Address 2 Field
30494  *
30495  * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and
30496  * Layer 4 Control Register 0), this field contains the value to be matched with
30497  * Bits [95:64] of the IP Source Address field in the IPv6 frames.
30498  *
30499  * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and
30500  * Layer 4 Control Register 0), this field contains value to be matched with Bits
30501  * [95:64] of the IP Destination Address field in the IPv6 frames.
30502  *
30503  * When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control
30504  * Register 0), this register is not used.
30505  *
30506  * Field Access Macros:
30507  *
30508  */
30509 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field. */
30510 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_LSB 0
30511 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field. */
30512 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_MSB 31
30513 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field. */
30514 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_WIDTH 32
30515 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field value. */
30516 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_SET_MSK 0xffffffff
30517 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field value. */
30518 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_CLR_MSK 0x00000000
30519 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field. */
30520 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_RESET 0x0
30521 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 field value from a register. */
30522 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_GET(value) (((value) & 0xffffffff) >> 0)
30523 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field value suitable for setting the register. */
30524 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_SET(value) (((value) << 0) & 0xffffffff)
30525 
30526 #ifndef __ASSEMBLY__
30527 /*
30528  * WARNING: The C register and register group struct declarations are provided for
30529  * convenience and illustrative purposes. They should, however, be used with
30530  * caution as the C language standard provides no guarantees about the alignment or
30531  * atomicity of device memory accesses. The recommended practice for writing
30532  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
30533  * alt_write_word() functions.
30534  *
30535  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG0.
30536  */
30537 struct ALT_EMAC_GMAC_LYR3_ADDR2_REG0_s
30538 {
30539  uint32_t l3a20 : 32; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 */
30540 };
30541 
30542 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG0. */
30543 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR2_REG0_s ALT_EMAC_GMAC_LYR3_ADDR2_REG0_t;
30544 #endif /* __ASSEMBLY__ */
30545 
30546 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0 register. */
30547 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_RESET 0x00000000
30548 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0 register from the beginning of the component. */
30549 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_OFST 0x418
30550 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0 register. */
30551 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR2_REG0_OFST))
30552 
30553 /*
30554  * Register : gmacgrp_layer3_addr3_reg0
30555  *
30556  * <b> Register 263 (Layer 3 Address 3 Register 0) </b>
30557  *
30558  * For IPv4 frames, the Layer 3 Address 3 Register 0 is reserved. For IPv6 frames,
30559  * it contains Bits [127:96] of the 128-bit IP Source Address or Destination
30560  * Address field.
30561  *
30562  * Register Layout
30563  *
30564  * Bits | Access | Reset | Description
30565  * :-------|:-------|:------|:------------------------------------
30566  * [31:0] | RW | 0x0 | ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30
30567  *
30568  */
30569 /*
30570  * Field : l3a30
30571  *
30572  * Layer 3 Address 3 Field
30573  *
30574  * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and
30575  * Layer 4 Control Register 0), this field contains the value to be matched with
30576  * Bits [127:96] of the IP Source Address field in the IPv6 frames.
30577  *
30578  * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and
30579  * Layer 4 Control Register 0), this field contains the value to be matched with
30580  * Bits [127:96] of the IP Destination Address field in the IPv6 frames.
30581  *
30582  * When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control
30583  * Register 0), this register is not used.
30584  *
30585  * Field Access Macros:
30586  *
30587  */
30588 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field. */
30589 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_LSB 0
30590 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field. */
30591 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_MSB 31
30592 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field. */
30593 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_WIDTH 32
30594 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field value. */
30595 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_SET_MSK 0xffffffff
30596 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field value. */
30597 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_CLR_MSK 0x00000000
30598 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field. */
30599 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_RESET 0x0
30600 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 field value from a register. */
30601 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_GET(value) (((value) & 0xffffffff) >> 0)
30602 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field value suitable for setting the register. */
30603 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_SET(value) (((value) << 0) & 0xffffffff)
30604 
30605 #ifndef __ASSEMBLY__
30606 /*
30607  * WARNING: The C register and register group struct declarations are provided for
30608  * convenience and illustrative purposes. They should, however, be used with
30609  * caution as the C language standard provides no guarantees about the alignment or
30610  * atomicity of device memory accesses. The recommended practice for writing
30611  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
30612  * alt_write_word() functions.
30613  *
30614  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG0.
30615  */
30616 struct ALT_EMAC_GMAC_LYR3_ADDR3_REG0_s
30617 {
30618  uint32_t l3a30 : 32; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 */
30619 };
30620 
30621 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG0. */
30622 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR3_REG0_s ALT_EMAC_GMAC_LYR3_ADDR3_REG0_t;
30623 #endif /* __ASSEMBLY__ */
30624 
30625 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0 register. */
30626 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_RESET 0x00000000
30627 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0 register from the beginning of the component. */
30628 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_OFST 0x41c
30629 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0 register. */
30630 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR3_REG0_OFST))
30631 
30632 /*
30633  * Register : Register 268 (Layer 3 and Layer 4 Control Register 1) - gmacgrp_l3_l4_control1
30634  *
30635  * This register controls the operations of the filter 0 of Layer 3 and Layer 4.
30636  *
30637  * Register Layout
30638  *
30639  * Bits | Access | Reset | Description
30640  * :--------|:-------|:------|:----------------------------------------------
30641  * [0] | RW | 0x0 | Layer 3 Protocol Enable
30642  * [1] | ??? | 0x0 | *UNDEFINED*
30643  * [2] | RW | 0x0 | Layer 3 IP SA Match Enable
30644  * [3] | RW | 0x0 | Layer 3 IP SA Inverse Match Enable
30645  * [4] | RW | 0x0 | Layer 3 IP DA Match Enable
30646  * [5] | RW | 0x0 | Layer 3 IP DA Inverse Match Enable
30647  * [10:6] | RW | 0x0 | Layer 3 IP SA Higher Bits Match
30648  * [15:11] | RW | 0x0 | Layer 3 IP DA Higher Bits Match
30649  * [16] | RW | 0x0 | Layer 4 Protocol Enable
30650  * [17] | ??? | 0x0 | *UNDEFINED*
30651  * [18] | RW | 0x0 | Layer 4 Source Port Match Enable
30652  * [19] | RW | 0x0 | Layer 4 Source Port Inverse Match Enable
30653  * [20] | RW | 0x0 | Layer 4 Destination Port Match Enable
30654  * [21] | RW | 0x0 | Layer 4 Destination Port Inverse Match Enable
30655  * [31:22] | ??? | 0x0 | *UNDEFINED*
30656  *
30657  */
30658 /*
30659  * Field : Layer 3 Protocol Enable - l3pen1
30660  *
30661  * When set, this bit indicates that the Layer 3 IP Source or Destination Address
30662  * matching is enabled for the IPv6 frames. When reset, this bit indicates that the
30663  * Layer 3 IP Source or Destination Address matching is enabled for the IPv4
30664  * frames.
30665  *
30666  * The Layer 3 matching is done only when either L3SAM1 or L3DAM1 bit is set high.
30667  *
30668  * Field Access Macros:
30669  *
30670  */
30671 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field. */
30672 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_LSB 0
30673 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field. */
30674 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_MSB 0
30675 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field. */
30676 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_WIDTH 1
30677 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field value. */
30678 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_SET_MSK 0x00000001
30679 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field value. */
30680 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_CLR_MSK 0xfffffffe
30681 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field. */
30682 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_RESET 0x0
30683 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 field value from a register. */
30684 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_GET(value) (((value) & 0x00000001) >> 0)
30685 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field value suitable for setting the register. */
30686 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_SET(value) (((value) << 0) & 0x00000001)
30687 
30688 /*
30689  * Field : Layer 3 IP SA Match Enable - l3sam1
30690  *
30691  * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
30692  * for matching. When reset, the MAC ignores the Layer 3 IP Source Address field
30693  * for matching.
30694  *
30695  * Note: When Bit 0 (L3PEN1) is set, you should set either this bit or Bit 4
30696  * (L3DAM1) because either IPv6 SA or DA can be checked for filtering.
30697  *
30698  * Field Access Macros:
30699  *
30700  */
30701 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field. */
30702 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_LSB 2
30703 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field. */
30704 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_MSB 2
30705 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field. */
30706 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_WIDTH 1
30707 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field value. */
30708 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_SET_MSK 0x00000004
30709 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field value. */
30710 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_CLR_MSK 0xfffffffb
30711 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field. */
30712 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_RESET 0x0
30713 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 field value from a register. */
30714 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_GET(value) (((value) & 0x00000004) >> 2)
30715 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field value suitable for setting the register. */
30716 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_SET(value) (((value) << 2) & 0x00000004)
30717 
30718 /*
30719  * Field : Layer 3 IP SA Inverse Match Enable - l3saim1
30720  *
30721  * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
30722  * for inverse matching. When reset, this bit indicates that the Layer 3 IP Source
30723  * Address field is enabled for perfect matching.
30724  *
30725  * This bit is valid and applicable only when Bit 2 (L3SAM1) is set high.
30726  *
30727  * Field Access Macros:
30728  *
30729  */
30730 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field. */
30731 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_LSB 3
30732 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field. */
30733 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_MSB 3
30734 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field. */
30735 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_WIDTH 1
30736 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field value. */
30737 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_SET_MSK 0x00000008
30738 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field value. */
30739 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_CLR_MSK 0xfffffff7
30740 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field. */
30741 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_RESET 0x0
30742 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 field value from a register. */
30743 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_GET(value) (((value) & 0x00000008) >> 3)
30744 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field value suitable for setting the register. */
30745 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_SET(value) (((value) << 3) & 0x00000008)
30746 
30747 /*
30748  * Field : Layer 3 IP DA Match Enable - l3dam1
30749  *
30750  * When set, this bit indicates that Layer 3 IP Destination Address field is
30751  * enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination
30752  * Address field for matching.
30753  *
30754  * Note: When Bit 1 (L3PEN1) is set, you should set either this bit or Bit 2
30755  * (L3SAM1) because either IPv6 DA or SA can be checked for filtering.
30756  *
30757  * Field Access Macros:
30758  *
30759  */
30760 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field. */
30761 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_LSB 4
30762 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field. */
30763 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_MSB 4
30764 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field. */
30765 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_WIDTH 1
30766 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field value. */
30767 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_SET_MSK 0x00000010
30768 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field value. */
30769 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_CLR_MSK 0xffffffef
30770 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field. */
30771 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_RESET 0x0
30772 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 field value from a register. */
30773 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_GET(value) (((value) & 0x00000010) >> 4)
30774 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field value suitable for setting the register. */
30775 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_SET(value) (((value) << 4) & 0x00000010)
30776 
30777 /*
30778  * Field : Layer 3 IP DA Inverse Match Enable - l3daim1
30779  *
30780  * When set, this bit indicates that the Layer 3 IP Destination Address field is
30781  * enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP
30782  * Destination Address field is enabled for perfect matching.
30783  *
30784  * This bit is valid and applicable only when Bit 4 (L3DAM1) is set high.
30785  *
30786  * Field Access Macros:
30787  *
30788  */
30789 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field. */
30790 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_LSB 5
30791 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field. */
30792 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_MSB 5
30793 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field. */
30794 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_WIDTH 1
30795 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field value. */
30796 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_SET_MSK 0x00000020
30797 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field value. */
30798 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_CLR_MSK 0xffffffdf
30799 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field. */
30800 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_RESET 0x0
30801 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 field value from a register. */
30802 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_GET(value) (((value) & 0x00000020) >> 5)
30803 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field value suitable for setting the register. */
30804 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_SET(value) (((value) << 5) & 0x00000020)
30805 
30806 /*
30807  * Field : Layer 3 IP SA Higher Bits Match - l3hsbm1
30808  *
30809  * IPv4 Frames:
30810  *
30811  * This field contains the number of lower bits of IP Source Address that are
30812  * masked for matching in the IPv4 frames. The following list describes the values
30813  * of this field:
30814  *
30815  * * 0: No bits are masked.
30816  *
30817  * * 1: LSb[0] is masked.
30818  *
30819  * * 2: Two LSbs [1:0] are masked.
30820  *
30821  * * ...
30822  *
30823  * * 31: All bits except MSb are masked.
30824  *
30825  * IPv6 Frames:
30826  *
30827  * This field contains Bits [4:0] of the field that indicates the number of higher
30828  * bits of IP Source or Destination Address matched in the IPv6 frames.
30829  *
30830  * This field is valid and applicable only if L3DAM1 or L3SAM1 is set high.
30831  *
30832  * Field Access Macros:
30833  *
30834  */
30835 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field. */
30836 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_LSB 6
30837 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field. */
30838 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_MSB 10
30839 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field. */
30840 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_WIDTH 5
30841 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field value. */
30842 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_SET_MSK 0x000007c0
30843 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field value. */
30844 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_CLR_MSK 0xfffff83f
30845 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field. */
30846 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_RESET 0x0
30847 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 field value from a register. */
30848 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_GET(value) (((value) & 0x000007c0) >> 6)
30849 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field value suitable for setting the register. */
30850 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_SET(value) (((value) << 6) & 0x000007c0)
30851 
30852 /*
30853  * Field : Layer 3 IP DA Higher Bits Match - l3hdbm1
30854  *
30855  * IPv4 Frames:
30856  *
30857  * This field contains the number of higher bits of IP Destination Address that are
30858  * matched in the IPv4 frames. The following list describes the values of this
30859  * field:
30860  *
30861  * * 0: No bits are masked.
30862  *
30863  * * 1: LSb[0] is masked.
30864  *
30865  * * 2: Two LSbs [1:0] are masked.
30866  *
30867  * * ...
30868  *
30869  * * 31: All bits except MSb are masked.
30870  *
30871  * IPv6 Frames:
30872  *
30873  * Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM1, which indicate
30874  * the number of lower bits of IP Source or Destination Address that are masked in
30875  * the IPv6 frames. The following list describes the concatenated values of the
30876  * L3HDBM1[1:0] and L3HSBM1 bits:
30877  *
30878  * * 0: No bits are masked.
30879  *
30880  * * 1: LSb[0] is masked.
30881  *
30882  * * 2: Two LSbs [1:0] are masked.
30883  *
30884  * * ...
30885  *
30886  * * 127: All bits except MSb are masked.
30887  *
30888  * This field is valid and applicable only if L3DAM1 or L3SAM1 is set high.
30889  *
30890  * Field Access Macros:
30891  *
30892  */
30893 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field. */
30894 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_LSB 11
30895 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field. */
30896 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_MSB 15
30897 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field. */
30898 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_WIDTH 5
30899 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field value. */
30900 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_SET_MSK 0x0000f800
30901 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field value. */
30902 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_CLR_MSK 0xffff07ff
30903 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field. */
30904 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_RESET 0x0
30905 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 field value from a register. */
30906 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_GET(value) (((value) & 0x0000f800) >> 11)
30907 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field value suitable for setting the register. */
30908 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_SET(value) (((value) << 11) & 0x0000f800)
30909 
30910 /*
30911  * Field : Layer 4 Protocol Enable - l4pen1
30912  *
30913  * When set, this bit indicates that the Source and Destination Port number fields
30914  * for UDP frames are used for matching. When reset, this bit indicates that the
30915  * Source and Destination Port number fields for TCP frames are used for matching.
30916  *
30917  * The Layer 4 matching is done only when either L4SPM1 or L4DPM1 bit is set high.
30918  *
30919  * Field Access Macros:
30920  *
30921  */
30922 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field. */
30923 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_LSB 16
30924 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field. */
30925 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_MSB 16
30926 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field. */
30927 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_WIDTH 1
30928 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field value. */
30929 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_SET_MSK 0x00010000
30930 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field value. */
30931 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_CLR_MSK 0xfffeffff
30932 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field. */
30933 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_RESET 0x0
30934 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 field value from a register. */
30935 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_GET(value) (((value) & 0x00010000) >> 16)
30936 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field value suitable for setting the register. */
30937 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_SET(value) (((value) << 16) & 0x00010000)
30938 
30939 /*
30940  * Field : Layer 4 Source Port Match Enable - l4spm1
30941  *
30942  * When set, this bit indicates that the Layer 4 Source Port number field is
30943  * enabled for matching.
30944  *
30945  * When reset, the MAC ignores the Layer 4 Source Port number field for matching.
30946  *
30947  * Field Access Macros:
30948  *
30949  */
30950 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field. */
30951 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_LSB 18
30952 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field. */
30953 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_MSB 18
30954 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field. */
30955 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_WIDTH 1
30956 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field value. */
30957 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_SET_MSK 0x00040000
30958 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field value. */
30959 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_CLR_MSK 0xfffbffff
30960 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field. */
30961 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_RESET 0x0
30962 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 field value from a register. */
30963 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_GET(value) (((value) & 0x00040000) >> 18)
30964 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field value suitable for setting the register. */
30965 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_SET(value) (((value) << 18) & 0x00040000)
30966 
30967 /*
30968  * Field : Layer 4 Source Port Inverse Match Enable - l4spim1
30969  *
30970  * When set, this bit indicates that the Layer 4 Source Port number field is
30971  * enabled for inverse matching.
30972  *
30973  * When reset, this bit indicates that the Layer 4 Source Port number field is
30974  * enabled for perfect matching.
30975  *
30976  * This bit is valid and applicable only when Bit 18 (L4SPM1) is set high.
30977  *
30978  * Field Access Macros:
30979  *
30980  */
30981 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field. */
30982 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_LSB 19
30983 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field. */
30984 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_MSB 19
30985 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field. */
30986 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_WIDTH 1
30987 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field value. */
30988 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_SET_MSK 0x00080000
30989 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field value. */
30990 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_CLR_MSK 0xfff7ffff
30991 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field. */
30992 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_RESET 0x0
30993 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 field value from a register. */
30994 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_GET(value) (((value) & 0x00080000) >> 19)
30995 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field value suitable for setting the register. */
30996 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_SET(value) (((value) << 19) & 0x00080000)
30997 
30998 /*
30999  * Field : Layer 4 Destination Port Match Enable - l4dpm1
31000  *
31001  * When set, this bit indicates that the Layer 4 Destination Port number field is
31002  * enabled for matching.
31003  *
31004  * When reset, the MAC ignores the Layer 4 Destination Port number field for
31005  * matching.
31006  *
31007  * Field Access Macros:
31008  *
31009  */
31010 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field. */
31011 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_LSB 20
31012 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field. */
31013 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_MSB 20
31014 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field. */
31015 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_WIDTH 1
31016 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field value. */
31017 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_SET_MSK 0x00100000
31018 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field value. */
31019 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_CLR_MSK 0xffefffff
31020 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field. */
31021 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_RESET 0x0
31022 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 field value from a register. */
31023 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_GET(value) (((value) & 0x00100000) >> 20)
31024 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field value suitable for setting the register. */
31025 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_SET(value) (((value) << 20) & 0x00100000)
31026 
31027 /*
31028  * Field : Layer 4 Destination Port Inverse Match Enable - l4dpim1
31029  *
31030  * When set, this bit indicates that the Layer 4 Destination Port number field is
31031  * enabled for inverse matching.
31032  *
31033  * When reset, this bit indicates that the Layer 4 Destination Port number field is
31034  * enabled for perfect matching.
31035  *
31036  * This bit is valid and applicable only when Bit 20 (L4DPM1) is set high.
31037  *
31038  * Field Access Macros:
31039  *
31040  */
31041 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field. */
31042 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_LSB 21
31043 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field. */
31044 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_MSB 21
31045 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field. */
31046 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_WIDTH 1
31047 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field value. */
31048 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_SET_MSK 0x00200000
31049 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field value. */
31050 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_CLR_MSK 0xffdfffff
31051 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field. */
31052 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_RESET 0x0
31053 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 field value from a register. */
31054 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_GET(value) (((value) & 0x00200000) >> 21)
31055 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field value suitable for setting the register. */
31056 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_SET(value) (((value) << 21) & 0x00200000)
31057 
31058 #ifndef __ASSEMBLY__
31059 /*
31060  * WARNING: The C register and register group struct declarations are provided for
31061  * convenience and illustrative purposes. They should, however, be used with
31062  * caution as the C language standard provides no guarantees about the alignment or
31063  * atomicity of device memory accesses. The recommended practice for writing
31064  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
31065  * alt_write_word() functions.
31066  *
31067  * The struct declaration for register ALT_EMAC_GMAC_L3_L4_CTL1.
31068  */
31069 struct ALT_EMAC_GMAC_L3_L4_CTL1_s
31070 {
31071  uint32_t l3pen1 : 1; /* Layer 3 Protocol Enable */
31072  uint32_t : 1; /* *UNDEFINED* */
31073  uint32_t l3sam1 : 1; /* Layer 3 IP SA Match Enable */
31074  uint32_t l3saim1 : 1; /* Layer 3 IP SA Inverse Match Enable */
31075  uint32_t l3dam1 : 1; /* Layer 3 IP DA Match Enable */
31076  uint32_t l3daim1 : 1; /* Layer 3 IP DA Inverse Match Enable */
31077  uint32_t l3hsbm1 : 5; /* Layer 3 IP SA Higher Bits Match */
31078  uint32_t l3hdbm1 : 5; /* Layer 3 IP DA Higher Bits Match */
31079  uint32_t l4pen1 : 1; /* Layer 4 Protocol Enable */
31080  uint32_t : 1; /* *UNDEFINED* */
31081  uint32_t l4spm1 : 1; /* Layer 4 Source Port Match Enable */
31082  uint32_t l4spim1 : 1; /* Layer 4 Source Port Inverse Match Enable */
31083  uint32_t l4dpm1 : 1; /* Layer 4 Destination Port Match Enable */
31084  uint32_t l4dpim1 : 1; /* Layer 4 Destination Port Inverse Match Enable */
31085  uint32_t : 10; /* *UNDEFINED* */
31086 };
31087 
31088 /* The typedef declaration for register ALT_EMAC_GMAC_L3_L4_CTL1. */
31089 typedef volatile struct ALT_EMAC_GMAC_L3_L4_CTL1_s ALT_EMAC_GMAC_L3_L4_CTL1_t;
31090 #endif /* __ASSEMBLY__ */
31091 
31092 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1 register. */
31093 #define ALT_EMAC_GMAC_L3_L4_CTL1_RESET 0x00000000
31094 /* The byte offset of the ALT_EMAC_GMAC_L3_L4_CTL1 register from the beginning of the component. */
31095 #define ALT_EMAC_GMAC_L3_L4_CTL1_OFST 0x430
31096 /* The address of the ALT_EMAC_GMAC_L3_L4_CTL1 register. */
31097 #define ALT_EMAC_GMAC_L3_L4_CTL1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_L3_L4_CTL1_OFST))
31098 
31099 /*
31100  * Register : Register 269 (Layer 4 Address Register 1) - gmacgrp_layer4_address1
31101  *
31102  * Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the
31103  * Rx clock domains, then the synchronization is triggered only when Bits[31:24]
31104  * (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and
31105  * Layer 4 Address Registers are written. For proper synchronization updates, you
31106  * should perform the consecutive writes to the same Layer 3 and Layer 4 Address
31107  * Registers after at least four clock cycles delay of the destination clock.
31108  *
31109  * Register Layout
31110  *
31111  * Bits | Access | Reset | Description
31112  * :--------|:-------|:------|:--------------------------------------
31113  * [15:0] | RW | 0x0 | Layer 4 Source Port Number Field
31114  * [31:16] | RW | 0x0 | Layer 4 Destination Port Number Field
31115  *
31116  */
31117 /*
31118  * Field : Layer 4 Source Port Number Field - l4sp1
31119  *
31120  * When Bit 16 (L4PEN1) is reset and Bit 20 (L4DPM1) is set in Register 268 (Layer
31121  * 3 and Layer 4 Control Register 1), this field contains the value to be matched
31122  * with the TCP Source Port Number field in the IPv4 or IPv6 frames.
31123  *
31124  * When Bit 16 (L4PEN1) and Bit 20 (L4DPM1) are set in Register 268 (Layer 3 and
31125  * Layer 4 Control Register 1), this field contains the value to be matched with
31126  * the UDP Source Port Number field in the IPv4 or IPv6 frames.
31127  *
31128  * Field Access Macros:
31129  *
31130  */
31131 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field. */
31132 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_LSB 0
31133 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field. */
31134 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_MSB 15
31135 /* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field. */
31136 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_WIDTH 16
31137 /* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field value. */
31138 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_SET_MSK 0x0000ffff
31139 /* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field value. */
31140 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_CLR_MSK 0xffff0000
31141 /* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field. */
31142 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_RESET 0x0
31143 /* Extracts the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 field value from a register. */
31144 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_GET(value) (((value) & 0x0000ffff) >> 0)
31145 /* Produces a ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field value suitable for setting the register. */
31146 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_SET(value) (((value) << 0) & 0x0000ffff)
31147 
31148 /*
31149  * Field : Layer 4 Destination Port Number Field - l4dp1
31150  *
31151  * When Bit 16 (L4PEN1) is reset and Bit 20 (L4DPM1) is set in Register 268 (Layer
31152  * 3 and Layer 4 Control Register 0), this field contains the value to be matched
31153  * with the TCP Destination Port Number field in the IPv4 or IPv6 frames.
31154  *
31155  * When Bit 16 (L4PEN1) and Bit 20 (L4DPM1) are set in Register 268 (Layer 3 and
31156  * Layer 4 Control Register 1), this field contains the value to be matched with
31157  * the UDP Destination Port Number field in the IPv4 or IPv6 frames.
31158  *
31159  * Field Access Macros:
31160  *
31161  */
31162 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field. */
31163 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_LSB 16
31164 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field. */
31165 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_MSB 31
31166 /* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field. */
31167 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_WIDTH 16
31168 /* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field value. */
31169 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_SET_MSK 0xffff0000
31170 /* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field value. */
31171 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_CLR_MSK 0x0000ffff
31172 /* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field. */
31173 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_RESET 0x0
31174 /* Extracts the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 field value from a register. */
31175 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_GET(value) (((value) & 0xffff0000) >> 16)
31176 /* Produces a ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field value suitable for setting the register. */
31177 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_SET(value) (((value) << 16) & 0xffff0000)
31178 
31179 #ifndef __ASSEMBLY__
31180 /*
31181  * WARNING: The C register and register group struct declarations are provided for
31182  * convenience and illustrative purposes. They should, however, be used with
31183  * caution as the C language standard provides no guarantees about the alignment or
31184  * atomicity of device memory accesses. The recommended practice for writing
31185  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
31186  * alt_write_word() functions.
31187  *
31188  * The struct declaration for register ALT_EMAC_GMAC_LYR4_ADDR1.
31189  */
31190 struct ALT_EMAC_GMAC_LYR4_ADDR1_s
31191 {
31192  uint32_t l4sp1 : 16; /* Layer 4 Source Port Number Field */
31193  uint32_t l4dp1 : 16; /* Layer 4 Destination Port Number Field */
31194 };
31195 
31196 /* The typedef declaration for register ALT_EMAC_GMAC_LYR4_ADDR1. */
31197 typedef volatile struct ALT_EMAC_GMAC_LYR4_ADDR1_s ALT_EMAC_GMAC_LYR4_ADDR1_t;
31198 #endif /* __ASSEMBLY__ */
31199 
31200 /* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR1 register. */
31201 #define ALT_EMAC_GMAC_LYR4_ADDR1_RESET 0x00000000
31202 /* The byte offset of the ALT_EMAC_GMAC_LYR4_ADDR1 register from the beginning of the component. */
31203 #define ALT_EMAC_GMAC_LYR4_ADDR1_OFST 0x434
31204 /* The address of the ALT_EMAC_GMAC_LYR4_ADDR1 register. */
31205 #define ALT_EMAC_GMAC_LYR4_ADDR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR4_ADDR1_OFST))
31206 
31207 /*
31208  * Register : Register 272 (Layer 3 Address 0 Register 1) - gmacgrp_layer3_addr0_reg1
31209  *
31210  * For IPv4 frames, the Layer 3 Address 0 Register 1 contains the 32-bit IP Source
31211  * Address field. For IPv6 frames, it contains Bits[31:0] of the 128-bit IP Source
31212  * Address or Destination Address field.
31213  *
31214  * Register Layout
31215  *
31216  * Bits | Access | Reset | Description
31217  * :-------|:-------|:------|:------------------------
31218  * [31:0] | RW | 0x0 | Layer 3 Address 0 Field
31219  *
31220  */
31221 /*
31222  * Field : Layer 3 Address 0 Field - l3a01
31223  *
31224  * When Bit 0 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and
31225  * Layer 4 Control Register 1), this field contains the value to be matched with
31226  * Bits[31:0] of the IP Source Address field in the IPv6 frames.
31227  *
31228  * When Bit 0 (L3PEN1) and Bit 4 (L3DAM1) are set in Register 268 (Layer 3 and
31229  * Layer 4 Control Register 1), this field contains the value to be matched with
31230  * Bits [31:0] of the IP Destination Address field in the IPv6 frames.
31231  *
31232  * When Bit 0 (L3PEN1) is reset and Bit 2 (L3SAM1) is set in Register 268 (Layer 3
31233  * and Layer 4 Control Register 1), this field contains the value to be matched
31234  * with the IP Source Address field in the IPv4 frames.
31235  *
31236  * Field Access Macros:
31237  *
31238  */
31239 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field. */
31240 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_LSB 0
31241 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field. */
31242 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_MSB 31
31243 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field. */
31244 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_WIDTH 32
31245 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field value. */
31246 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_SET_MSK 0xffffffff
31247 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field value. */
31248 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_CLR_MSK 0x00000000
31249 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field. */
31250 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_RESET 0x0
31251 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 field value from a register. */
31252 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_GET(value) (((value) & 0xffffffff) >> 0)
31253 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field value suitable for setting the register. */
31254 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_SET(value) (((value) << 0) & 0xffffffff)
31255 
31256 #ifndef __ASSEMBLY__
31257 /*
31258  * WARNING: The C register and register group struct declarations are provided for
31259  * convenience and illustrative purposes. They should, however, be used with
31260  * caution as the C language standard provides no guarantees about the alignment or
31261  * atomicity of device memory accesses. The recommended practice for writing
31262  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
31263  * alt_write_word() functions.
31264  *
31265  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG1.
31266  */
31267 struct ALT_EMAC_GMAC_LYR3_ADDR0_REG1_s
31268 {
31269  uint32_t l3a01 : 32; /* Layer 3 Address 0 Field */
31270 };
31271 
31272 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG1. */
31273 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR0_REG1_s ALT_EMAC_GMAC_LYR3_ADDR0_REG1_t;
31274 #endif /* __ASSEMBLY__ */
31275 
31276 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1 register. */
31277 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_RESET 0x00000000
31278 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1 register from the beginning of the component. */
31279 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_OFST 0x440
31280 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1 register. */
31281 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR0_REG1_OFST))
31282 
31283 /*
31284  * Register : Register 273 (Layer 3 Address 1 Register 1) - gmacgrp_layer3_addr1_reg1
31285  *
31286  * For IPv4 frames, the Layer 3 Address 1 Register 1 contains the 32-bit IP
31287  * Destination Address field. For IPv6 frames, it contains Bits[63:32] of the
31288  * 128-bit IP Source Address or Destination Address field
31289  *
31290  * Register Layout
31291  *
31292  * Bits | Access | Reset | Description
31293  * :-------|:-------|:------|:------------------------
31294  * [31:0] | RW | 0x0 | Layer 3 Address 1 Field
31295  *
31296  */
31297 /*
31298  * Field : Layer 3 Address 1 Field - l3a11
31299  *
31300  * When Bit 0 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and
31301  * Layer 4 Control Register 1), this field contains the value to be matched with
31302  * Bits [63:32] of the IP Source Address field in the IPv6 frames.
31303  *
31304  * When Bit 0 (L3PEN1) and Bit 4 (L3DAM1) are set in Register 268 (Layer 3 and
31305  * Layer 4 Control Register 1), this field contains the value to be matched with
31306  * Bits [63:32] of the IP Destination Address field in the IPv6 frames.
31307  *
31308  * When Bit 0 (L3PEN1) is reset and Bit 4 (L3DAM1) is set in Register 268 (Layer 3
31309  * and Layer 4 Control Register 1), this field contains the value to be matched
31310  * with the IP Destination Address field in the IPv4 frames.
31311  *
31312  * Field Access Macros:
31313  *
31314  */
31315 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field. */
31316 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_LSB 0
31317 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field. */
31318 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_MSB 31
31319 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field. */
31320 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_WIDTH 32
31321 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field value. */
31322 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_SET_MSK 0xffffffff
31323 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field value. */
31324 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_CLR_MSK 0x00000000
31325 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field. */
31326 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_RESET 0x0
31327 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 field value from a register. */
31328 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_GET(value) (((value) & 0xffffffff) >> 0)
31329 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field value suitable for setting the register. */
31330 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_SET(value) (((value) << 0) & 0xffffffff)
31331 
31332 #ifndef __ASSEMBLY__
31333 /*
31334  * WARNING: The C register and register group struct declarations are provided for
31335  * convenience and illustrative purposes. They should, however, be used with
31336  * caution as the C language standard provides no guarantees about the alignment or
31337  * atomicity of device memory accesses. The recommended practice for writing
31338  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
31339  * alt_write_word() functions.
31340  *
31341  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG1.
31342  */
31343 struct ALT_EMAC_GMAC_LYR3_ADDR1_REG1_s
31344 {
31345  uint32_t l3a11 : 32; /* Layer 3 Address 1 Field */
31346 };
31347 
31348 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG1. */
31349 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR1_REG1_s ALT_EMAC_GMAC_LYR3_ADDR1_REG1_t;
31350 #endif /* __ASSEMBLY__ */
31351 
31352 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1 register. */
31353 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_RESET 0x00000000
31354 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1 register from the beginning of the component. */
31355 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_OFST 0x444
31356 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1 register. */
31357 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR1_REG1_OFST))
31358 
31359 /*
31360  * Register : Register 274 (Layer 3 Address 2 Register 1) - gmacgrp_layer3_addr2_reg1
31361  *
31362  * For IPv4 frames, the Layer 3 Address 2 Register 1 is reserved. For IPv6 frames,
31363  * it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address
31364  * field.
31365  *
31366  * Register Layout
31367  *
31368  * Bits | Access | Reset | Description
31369  * :-------|:-------|:------|:------------------------
31370  * [31:0] | RW | 0x0 | Layer 3 Address 2 Field
31371  *
31372  */
31373 /*
31374  * Field : Layer 3 Address 2 Field - l3a21
31375  *
31376  * When Bit 0 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and
31377  * Layer 4 Control Register 1), this field contains the value to be matched with
31378  * Bits [95:64] of the IP Source Address field in the IPv6 frames.
31379  *
31380  * When Bit 0 (L3PEN1) and Bit 4 (L3DAM1) are set in Register 268 (Layer 3 and
31381  * Layer 4 Control Register 1), this field contains value to be matched with Bits
31382  * [95:64] of the IP Destination Address field in the IPv6 frames.
31383  *
31384  * Field Access Macros:
31385  *
31386  */
31387 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field. */
31388 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_LSB 0
31389 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field. */
31390 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_MSB 31
31391 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field. */
31392 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_WIDTH 32
31393 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field value. */
31394 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_SET_MSK 0xffffffff
31395 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field value. */
31396 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_CLR_MSK 0x00000000
31397 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field. */
31398 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_RESET 0x0
31399 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 field value from a register. */
31400 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_GET(value) (((value) & 0xffffffff) >> 0)
31401 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field value suitable for setting the register. */
31402 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_SET(value) (((value) << 0) & 0xffffffff)
31403 
31404 #ifndef __ASSEMBLY__
31405 /*
31406  * WARNING: The C register and register group struct declarations are provided for
31407  * convenience and illustrative purposes. They should, however, be used with
31408  * caution as the C language standard provides no guarantees about the alignment or
31409  * atomicity of device memory accesses. The recommended practice for writing
31410  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
31411  * alt_write_word() functions.
31412  *
31413  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG1.
31414  */
31415 struct ALT_EMAC_GMAC_LYR3_ADDR2_REG1_s
31416 {
31417  uint32_t l3a21 : 32; /* Layer 3 Address 2 Field */
31418 };
31419 
31420 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG1. */
31421 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR2_REG1_s ALT_EMAC_GMAC_LYR3_ADDR2_REG1_t;
31422 #endif /* __ASSEMBLY__ */
31423 
31424 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1 register. */
31425 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_RESET 0x00000000
31426 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1 register from the beginning of the component. */
31427 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_OFST 0x448
31428 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1 register. */
31429 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR2_REG1_OFST))
31430 
31431 /*
31432  * Register : Register 275 (Layer 3 Address 3 Register 1) - gmacgrp_layer3_addr3_reg1
31433  *
31434  * For IPv4 frames, the Layer 3 Address 3 Register 1 is reserved. For IPv6 frames,
31435  * it contains Bits [127:96] of the 128-bit IP Source Address or Destination
31436  * Address field.
31437  *
31438  * Register Layout
31439  *
31440  * Bits | Access | Reset | Description
31441  * :-------|:-------|:------|:------------------------
31442  * [31:0] | RW | 0x0 | Layer 3 Address 3 Field
31443  *
31444  */
31445 /*
31446  * Field : Layer 3 Address 3 Field - l3a31
31447  *
31448  * When Bit 1 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and
31449  * Layer 4 Control Register 1), this field contains the value to be matched with
31450  * Bits [127:96] of the IP Source Address field in the IPv6 frames.
31451  *
31452  * When Bit 0 (L3PEN1) and Bit 4 (L3DAM1) are set in Register 268 (Layer 3 and
31453  * Layer 4 Control Register 1), this field contains the value to be matched with
31454  * Bits [127:96] of the IP Destination Address field in the IPv6 frames.
31455  *
31456  * When Bit 0 (L3PEN1) is reset in Register 268 (Layer 3 and Layer 4 Control
31457  * Register 1), this register is not used.
31458  *
31459  * Field Access Macros:
31460  *
31461  */
31462 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field. */
31463 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_LSB 0
31464 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field. */
31465 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_MSB 31
31466 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field. */
31467 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_WIDTH 32
31468 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field value. */
31469 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_SET_MSK 0xffffffff
31470 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field value. */
31471 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_CLR_MSK 0x00000000
31472 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field. */
31473 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_RESET 0x0
31474 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 field value from a register. */
31475 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_GET(value) (((value) & 0xffffffff) >> 0)
31476 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field value suitable for setting the register. */
31477 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_SET(value) (((value) << 0) & 0xffffffff)
31478 
31479 #ifndef __ASSEMBLY__
31480 /*
31481  * WARNING: The C register and register group struct declarations are provided for
31482  * convenience and illustrative purposes. They should, however, be used with
31483  * caution as the C language standard provides no guarantees about the alignment or
31484  * atomicity of device memory accesses. The recommended practice for writing
31485  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
31486  * alt_write_word() functions.
31487  *
31488  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG1.
31489  */
31490 struct ALT_EMAC_GMAC_LYR3_ADDR3_REG1_s
31491 {
31492  uint32_t l3a31 : 32; /* Layer 3 Address 3 Field */
31493 };
31494 
31495 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG1. */
31496 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR3_REG1_s ALT_EMAC_GMAC_LYR3_ADDR3_REG1_t;
31497 #endif /* __ASSEMBLY__ */
31498 
31499 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1 register. */
31500 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_RESET 0x00000000
31501 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1 register from the beginning of the component. */
31502 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_OFST 0x44c
31503 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1 register. */
31504 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR3_REG1_OFST))
31505 
31506 /*
31507  * Register : Register 280 (Layer 3 and Layer 4 Control Register 2) - gmacgrp_l3_l4_control2
31508  *
31509  * This register controls the operations of the filter 2 of Layer 3 and Layer 4.
31510  *
31511  * Register Layout
31512  *
31513  * Bits | Access | Reset | Description
31514  * :--------|:-------|:------|:----------------------------------------------
31515  * [0] | RW | 0x0 | Layer 3 Protocol Enable
31516  * [1] | ??? | 0x0 | *UNDEFINED*
31517  * [2] | RW | 0x0 | Layer 3 IP SA Match Enable
31518  * [3] | RW | 0x0 | Layer 3 IP SA Inverse Match Enable
31519  * [4] | RW | 0x0 | Layer 3 IP DA Match Enable
31520  * [5] | RW | 0x0 | Layer 3 IP DA Inverse Match Enable
31521  * [10:6] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2
31522  * [15:11] | RW | 0x0 | Layer 3 IP DA Higher Bits Match
31523  * [16] | RW | 0x0 | Layer 4 Protocol Enable
31524  * [17] | ??? | 0x0 | *UNDEFINED*
31525  * [18] | RW | 0x0 | Layer 4 Source Port Match Enable
31526  * [19] | RW | 0x0 | Layer 4 Source Port Inverse Match Enable
31527  * [20] | RW | 0x0 | Layer 4 Destination Port Match Enable
31528  * [21] | RW | 0x0 | Layer 4 Destination Port Inverse Match Enable
31529  * [31:22] | ??? | 0x0 | *UNDEFINED*
31530  *
31531  */
31532 /*
31533  * Field : Layer 3 Protocol Enable - l3pen2
31534  *
31535  * When set, this bit indicates that the Layer 3 IP Source or Destination Address
31536  * matching is enabled for the IPv6 frames. When reset, this bit indicates that the
31537  * Layer 3 IP Source or Destination Address matching is enabled for the IPv4
31538  * frames.
31539  *
31540  * The Layer 3 matching is done only when either L3SAM2 or L3DAM2 bit is set high.
31541  *
31542  * Field Access Macros:
31543  *
31544  */
31545 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field. */
31546 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_LSB 0
31547 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field. */
31548 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_MSB 0
31549 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field. */
31550 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_WIDTH 1
31551 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field value. */
31552 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_SET_MSK 0x00000001
31553 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field value. */
31554 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_CLR_MSK 0xfffffffe
31555 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field. */
31556 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_RESET 0x0
31557 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 field value from a register. */
31558 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_GET(value) (((value) & 0x00000001) >> 0)
31559 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field value suitable for setting the register. */
31560 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_SET(value) (((value) << 0) & 0x00000001)
31561 
31562 /*
31563  * Field : Layer 3 IP SA Match Enable - l3sam2
31564  *
31565  * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
31566  * for matching. When reset, the MAC ignores the Layer 3 IP Source Address field
31567  * for matching.
31568  *
31569  * Note: When Bit 0 (L3PEN2) is set, you should set either this bit or Bit 4
31570  * (L3DAM2) because either IPv6 SA or DA can be checked for filtering.
31571  *
31572  * Field Access Macros:
31573  *
31574  */
31575 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field. */
31576 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_LSB 2
31577 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field. */
31578 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_MSB 2
31579 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field. */
31580 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_WIDTH 1
31581 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field value. */
31582 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_SET_MSK 0x00000004
31583 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field value. */
31584 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_CLR_MSK 0xfffffffb
31585 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field. */
31586 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_RESET 0x0
31587 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 field value from a register. */
31588 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_GET(value) (((value) & 0x00000004) >> 2)
31589 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field value suitable for setting the register. */
31590 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_SET(value) (((value) << 2) & 0x00000004)
31591 
31592 /*
31593  * Field : Layer 3 IP SA Inverse Match Enable - l3saim2
31594  *
31595  * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
31596  * for inverse matching. When reset, this bit indicates that the Layer 3 IP Source
31597  * Address field is enabled for perfect matching.
31598  *
31599  * This bit is valid and applicable only when Bit 2 (L3SAM2) is set high.
31600  *
31601  * Field Access Macros:
31602  *
31603  */
31604 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field. */
31605 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_LSB 3
31606 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field. */
31607 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_MSB 3
31608 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field. */
31609 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_WIDTH 1
31610 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field value. */
31611 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_SET_MSK 0x00000008
31612 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field value. */
31613 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_CLR_MSK 0xfffffff7
31614 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field. */
31615 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_RESET 0x0
31616 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 field value from a register. */
31617 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_GET(value) (((value) & 0x00000008) >> 3)
31618 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field value suitable for setting the register. */
31619 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_SET(value) (((value) << 3) & 0x00000008)
31620 
31621 /*
31622  * Field : Layer 3 IP DA Match Enable - l3dam2
31623  *
31624  * When set, this bit indicates that Layer 3 IP Destination Address field is
31625  * enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination
31626  * Address field for matching.
31627  *
31628  * Note: When Bit 0 (L3PEN2) is set, you should set either this bit or Bit 2
31629  * (L3SAM2) because either IPv6 DA or SA can be checked for filtering.
31630  *
31631  * Field Access Macros:
31632  *
31633  */
31634 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field. */
31635 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_LSB 4
31636 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field. */
31637 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_MSB 4
31638 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field. */
31639 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_WIDTH 1
31640 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field value. */
31641 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_SET_MSK 0x00000010
31642 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field value. */
31643 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_CLR_MSK 0xffffffef
31644 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field. */
31645 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_RESET 0x0
31646 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 field value from a register. */
31647 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_GET(value) (((value) & 0x00000010) >> 4)
31648 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field value suitable for setting the register. */
31649 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_SET(value) (((value) << 4) & 0x00000010)
31650 
31651 /*
31652  * Field : Layer 3 IP DA Inverse Match Enable - l3daim2
31653  *
31654  * When set, this bit indicates that the Layer 3 IP Destination Address field is
31655  * enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP
31656  * Destination Address field is enabled for perfect matching.
31657  *
31658  * This bit is valid and applicable only when Bit 4 (L3DAM2) is set high.
31659  *
31660  * Field Access Macros:
31661  *
31662  */
31663 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field. */
31664 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_LSB 5
31665 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field. */
31666 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_MSB 5
31667 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field. */
31668 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_WIDTH 1
31669 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field value. */
31670 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_SET_MSK 0x00000020
31671 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field value. */
31672 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_CLR_MSK 0xffffffdf
31673 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field. */
31674 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_RESET 0x0
31675 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 field value from a register. */
31676 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_GET(value) (((value) & 0x00000020) >> 5)
31677 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field value suitable for setting the register. */
31678 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_SET(value) (((value) << 5) & 0x00000020)
31679 
31680 /*
31681  * Field : l3hsbm2
31682  *
31683  * Layer 3 IP SA Higher Bits Match
31684  *
31685  * IPv4 Frames:
31686  *
31687  * This field contains the number of lower bits of IP Source Address that are
31688  * masked for matching in the IPv4 frames. The following list describes the values
31689  * of this field:
31690  *
31691  * * 0: No bits are masked.
31692  *
31693  * * 1: LSb[0] is masked.
31694  *
31695  * * 2: Two LSbs [1:0] are masked.
31696  *
31697  * * ...
31698  *
31699  * * 31: All bits except MSb are masked.
31700  *
31701  * IPv6 Frames:
31702  *
31703  * This field contains Bits [4:0] of the field that indicates the number of higher
31704  * bits of IP Source or Destination Address matched in the IPv6 frames.
31705  *
31706  * This field is valid and applicable only if L3DAM2 or L3SAM2 is set high.
31707  *
31708  * Field Access Macros:
31709  *
31710  */
31711 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field. */
31712 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_LSB 6
31713 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field. */
31714 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_MSB 10
31715 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field. */
31716 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_WIDTH 5
31717 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field value. */
31718 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_SET_MSK 0x000007c0
31719 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field value. */
31720 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_CLR_MSK 0xfffff83f
31721 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field. */
31722 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_RESET 0x0
31723 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 field value from a register. */
31724 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_GET(value) (((value) & 0x000007c0) >> 6)
31725 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field value suitable for setting the register. */
31726 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_SET(value) (((value) << 6) & 0x000007c0)
31727 
31728 /*
31729  * Field : Layer 3 IP DA Higher Bits Match - l3hdbm2
31730  *
31731  * IPv4 Frames:
31732  *
31733  * This field contains the number of higher bits of IP Destination Address that are
31734  * matched in the IPv4 frames. The following list describes the values of this
31735  * field:
31736  *
31737  * * 0: No bits are masked.
31738  *
31739  * * 1: LSb[0] is masked.
31740  *
31741  * * 2: Two LSbs [1:0] are masked.
31742  *
31743  * * ...
31744  *
31745  * * 31: All bits except MSb are masked.
31746  *
31747  * IPv6 Frames:
31748  *
31749  * Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM2, which indicate
31750  * the number of lower bits of IP Source or Destination Address that are masked in
31751  * the IPv6 frames. The following list describes the concatenated values of the
31752  * L3HDBM2[1:0] and L3HSBM2 bits:
31753  *
31754  * * 0: No bits are masked.
31755  *
31756  * * 1: LSb[0] is masked.
31757  *
31758  * * 2: Two LSbs [1:0] are masked.
31759  *
31760  * * ...
31761  *
31762  * * 127: All bits except MSb are masked.
31763  *
31764  * This field is valid and applicable only if L3DAM2 or L3SAM2 is set high.
31765  *
31766  * Field Access Macros:
31767  *
31768  */
31769 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field. */
31770 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_LSB 11
31771 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field. */
31772 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_MSB 15
31773 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field. */
31774 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_WIDTH 5
31775 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field value. */
31776 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_SET_MSK 0x0000f800
31777 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field value. */
31778 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_CLR_MSK 0xffff07ff
31779 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field. */
31780 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_RESET 0x0
31781 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 field value from a register. */
31782 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_GET(value) (((value) & 0x0000f800) >> 11)
31783 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field value suitable for setting the register. */
31784 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_SET(value) (((value) << 11) & 0x0000f800)
31785 
31786 /*
31787  * Field : Layer 4 Protocol Enable - l4pen2
31788  *
31789  * When set, this bit indicates that the Source and Destination Port number fields
31790  * for UDP frames are used for matching. When reset, this bit indicates that the
31791  * Source and Destination Port number fields for TCP frames are used for matching.
31792  *
31793  * The Layer 4 matching is done only when either L4SPM2 or L4DPM2 bit is set high.
31794  *
31795  * Field Access Macros:
31796  *
31797  */
31798 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field. */
31799 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_LSB 16
31800 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field. */
31801 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_MSB 16
31802 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field. */
31803 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_WIDTH 1
31804 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field value. */
31805 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_SET_MSK 0x00010000
31806 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field value. */
31807 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_CLR_MSK 0xfffeffff
31808 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field. */
31809 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_RESET 0x0
31810 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 field value from a register. */
31811 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_GET(value) (((value) & 0x00010000) >> 16)
31812 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field value suitable for setting the register. */
31813 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_SET(value) (((value) << 16) & 0x00010000)
31814 
31815 /*
31816  * Field : Layer 4 Source Port Match Enable - l4spm2
31817  *
31818  * When set, this bit indicates that the Layer 4 Source Port number field is
31819  * enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number
31820  * field for matching.
31821  *
31822  * Field Access Macros:
31823  *
31824  */
31825 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field. */
31826 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_LSB 18
31827 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field. */
31828 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_MSB 18
31829 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field. */
31830 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_WIDTH 1
31831 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field value. */
31832 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_SET_MSK 0x00040000
31833 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field value. */
31834 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_CLR_MSK 0xfffbffff
31835 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field. */
31836 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_RESET 0x0
31837 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 field value from a register. */
31838 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_GET(value) (((value) & 0x00040000) >> 18)
31839 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field value suitable for setting the register. */
31840 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_SET(value) (((value) << 18) & 0x00040000)
31841 
31842 /*
31843  * Field : Layer 4 Source Port Inverse Match Enable - l4spim2
31844  *
31845  * When set, this bit indicates that the Layer 4 Source Port number field is
31846  * enabled for inverse matching. When reset, this bit indicates that the Layer 4
31847  * Source Port number field is enabled for perfect matching.
31848  *
31849  * This bit is valid and applicable only when Bit 18 (L4SPM2) is set high.
31850  *
31851  * Field Access Macros:
31852  *
31853  */
31854 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field. */
31855 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_LSB 19
31856 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field. */
31857 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_MSB 19
31858 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field. */
31859 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_WIDTH 1
31860 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field value. */
31861 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_SET_MSK 0x00080000
31862 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field value. */
31863 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_CLR_MSK 0xfff7ffff
31864 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field. */
31865 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_RESET 0x0
31866 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 field value from a register. */
31867 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_GET(value) (((value) & 0x00080000) >> 19)
31868 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field value suitable for setting the register. */
31869 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_SET(value) (((value) << 19) & 0x00080000)
31870 
31871 /*
31872  * Field : Layer 4 Destination Port Match Enable - l4dpm2
31873  *
31874  * When set, this bit indicates that the Layer 4 Destination Port number field is
31875  * enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port
31876  * number field for matching.
31877  *
31878  * Field Access Macros:
31879  *
31880  */
31881 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field. */
31882 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_LSB 20
31883 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field. */
31884 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_MSB 20
31885 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field. */
31886 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_WIDTH 1
31887 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field value. */
31888 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_SET_MSK 0x00100000
31889 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field value. */
31890 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_CLR_MSK 0xffefffff
31891 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field. */
31892 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_RESET 0x0
31893 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 field value from a register. */
31894 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_GET(value) (((value) & 0x00100000) >> 20)
31895 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field value suitable for setting the register. */
31896 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_SET(value) (((value) << 20) & 0x00100000)
31897 
31898 /*
31899  * Field : Layer 4 Destination Port Inverse Match Enable - l4dpim2
31900  *
31901  * When set, this bit indicates that the Layer 4 Destination Port number field is
31902  * enabled for inverse matching. When reset, this bit indicates that the Layer 4
31903  * Destination Port number field is enabled for perfect matching.
31904  *
31905  * This bit is valid and applicable only when Bit 20 (L4DPM0) is set high.
31906  *
31907  * Field Access Macros:
31908  *
31909  */
31910 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field. */
31911 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_LSB 21
31912 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field. */
31913 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_MSB 21
31914 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field. */
31915 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_WIDTH 1
31916 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field value. */
31917 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_SET_MSK 0x00200000
31918 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field value. */
31919 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_CLR_MSK 0xffdfffff
31920 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field. */
31921 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_RESET 0x0
31922 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 field value from a register. */
31923 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_GET(value) (((value) & 0x00200000) >> 21)
31924 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field value suitable for setting the register. */
31925 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_SET(value) (((value) << 21) & 0x00200000)
31926 
31927 #ifndef __ASSEMBLY__
31928 /*
31929  * WARNING: The C register and register group struct declarations are provided for
31930  * convenience and illustrative purposes. They should, however, be used with
31931  * caution as the C language standard provides no guarantees about the alignment or
31932  * atomicity of device memory accesses. The recommended practice for writing
31933  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
31934  * alt_write_word() functions.
31935  *
31936  * The struct declaration for register ALT_EMAC_GMAC_L3_L4_CTL2.
31937  */
31938 struct ALT_EMAC_GMAC_L3_L4_CTL2_s
31939 {
31940  uint32_t l3pen2 : 1; /* Layer 3 Protocol Enable */
31941  uint32_t : 1; /* *UNDEFINED* */
31942  uint32_t l3sam2 : 1; /* Layer 3 IP SA Match Enable */
31943  uint32_t l3saim2 : 1; /* Layer 3 IP SA Inverse Match Enable */
31944  uint32_t l3dam2 : 1; /* Layer 3 IP DA Match Enable */
31945  uint32_t l3daim2 : 1; /* Layer 3 IP DA Inverse Match Enable */
31946  uint32_t l3hsbm2 : 5; /* ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 */
31947  uint32_t l3hdbm2 : 5; /* Layer 3 IP DA Higher Bits Match */
31948  uint32_t l4pen2 : 1; /* Layer 4 Protocol Enable */
31949  uint32_t : 1; /* *UNDEFINED* */
31950  uint32_t l4spm2 : 1; /* Layer 4 Source Port Match Enable */
31951  uint32_t l4spim2 : 1; /* Layer 4 Source Port Inverse Match Enable */
31952  uint32_t l4dpm2 : 1; /* Layer 4 Destination Port Match Enable */
31953  uint32_t l4dpim2 : 1; /* Layer 4 Destination Port Inverse Match Enable */
31954  uint32_t : 10; /* *UNDEFINED* */
31955 };
31956 
31957 /* The typedef declaration for register ALT_EMAC_GMAC_L3_L4_CTL2. */
31958 typedef volatile struct ALT_EMAC_GMAC_L3_L4_CTL2_s ALT_EMAC_GMAC_L3_L4_CTL2_t;
31959 #endif /* __ASSEMBLY__ */
31960 
31961 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2 register. */
31962 #define ALT_EMAC_GMAC_L3_L4_CTL2_RESET 0x00000000
31963 /* The byte offset of the ALT_EMAC_GMAC_L3_L4_CTL2 register from the beginning of the component. */
31964 #define ALT_EMAC_GMAC_L3_L4_CTL2_OFST 0x460
31965 /* The address of the ALT_EMAC_GMAC_L3_L4_CTL2 register. */
31966 #define ALT_EMAC_GMAC_L3_L4_CTL2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_L3_L4_CTL2_OFST))
31967 
31968 /*
31969  * Register : Register 281 (Layer 4 Address Register 2) - gmacgrp_layer4_address2
31970  *
31971  * Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the
31972  * Rx clock domains, then the synchronization is triggered only when Bits[31:24]
31973  * (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and
31974  * Layer 4 Address Registers are written. For proper synchronization updates, you
31975  * should perform the consecutive writes to the same Layer 3 and Layer 4 Address
31976  * Registers after at least four clock cycles delay of the destination clock.
31977  *
31978  * Register Layout
31979  *
31980  * Bits | Access | Reset | Description
31981  * :--------|:-------|:------|:--------------------------------------
31982  * [15:0] | RW | 0x0 | Layer 4 Source Port Number Field
31983  * [31:16] | RW | 0x0 | Layer 4 Destination Port Number Field
31984  *
31985  */
31986 /*
31987  * Field : Layer 4 Source Port Number Field - l4sp2
31988  *
31989  * When Bit 16 (L4PEN2) is reset and Bit 20 (L4DPM2) is set in Register 280 (Layer
31990  * 3 and Layer 4 Control Register 2), this field contains the value to be matched
31991  * with the TCP Source Port Number field in the IPv4 or IPv6 frames.
31992  *
31993  * When Bit 16 (L4PEN2) and Bit 20 (L4DPM2) are set in Register 280 (Layer 3 and
31994  * Layer 4 Control Register 2), this field contains the value to be matched with
31995  * the UDP Source Port Number field in the IPv4 or IPv6 frames.
31996  *
31997  * Field Access Macros:
31998  *
31999  */
32000 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field. */
32001 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_LSB 0
32002 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field. */
32003 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_MSB 15
32004 /* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field. */
32005 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_WIDTH 16
32006 /* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field value. */
32007 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_SET_MSK 0x0000ffff
32008 /* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field value. */
32009 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_CLR_MSK 0xffff0000
32010 /* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field. */
32011 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_RESET 0x0
32012 /* Extracts the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 field value from a register. */
32013 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_GET(value) (((value) & 0x0000ffff) >> 0)
32014 /* Produces a ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field value suitable for setting the register. */
32015 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_SET(value) (((value) << 0) & 0x0000ffff)
32016 
32017 /*
32018  * Field : Layer 4 Destination Port Number Field - l4dp2
32019  *
32020  * When Bit 16 (L4PEN2) is reset and Bit 20 (L4DPM2) is set in Register 280 (Layer
32021  * 3 and Layer 4 Control Register 2), this field contains the value to be matched
32022  * with the TCP Destination Port Number field in the IPv4 or IPv6 frames.
32023  *
32024  * When Bit 16 (L4PEN2) and Bit 20 (L4DPM2) are set in Register 280 (Layer 3 and
32025  * Layer 4 Control Register 2), this field contains the value to be matched with
32026  * the UDP Destination Port Number field in the IPv4 or IPv6 frames.
32027  *
32028  * Field Access Macros:
32029  *
32030  */
32031 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field. */
32032 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_LSB 16
32033 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field. */
32034 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_MSB 31
32035 /* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field. */
32036 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_WIDTH 16
32037 /* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field value. */
32038 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_SET_MSK 0xffff0000
32039 /* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field value. */
32040 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_CLR_MSK 0x0000ffff
32041 /* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field. */
32042 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_RESET 0x0
32043 /* Extracts the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 field value from a register. */
32044 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_GET(value) (((value) & 0xffff0000) >> 16)
32045 /* Produces a ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field value suitable for setting the register. */
32046 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_SET(value) (((value) << 16) & 0xffff0000)
32047 
32048 #ifndef __ASSEMBLY__
32049 /*
32050  * WARNING: The C register and register group struct declarations are provided for
32051  * convenience and illustrative purposes. They should, however, be used with
32052  * caution as the C language standard provides no guarantees about the alignment or
32053  * atomicity of device memory accesses. The recommended practice for writing
32054  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
32055  * alt_write_word() functions.
32056  *
32057  * The struct declaration for register ALT_EMAC_GMAC_LYR4_ADDR2.
32058  */
32059 struct ALT_EMAC_GMAC_LYR4_ADDR2_s
32060 {
32061  uint32_t l4sp2 : 16; /* Layer 4 Source Port Number Field */
32062  uint32_t l4dp2 : 16; /* Layer 4 Destination Port Number Field */
32063 };
32064 
32065 /* The typedef declaration for register ALT_EMAC_GMAC_LYR4_ADDR2. */
32066 typedef volatile struct ALT_EMAC_GMAC_LYR4_ADDR2_s ALT_EMAC_GMAC_LYR4_ADDR2_t;
32067 #endif /* __ASSEMBLY__ */
32068 
32069 /* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR2 register. */
32070 #define ALT_EMAC_GMAC_LYR4_ADDR2_RESET 0x00000000
32071 /* The byte offset of the ALT_EMAC_GMAC_LYR4_ADDR2 register from the beginning of the component. */
32072 #define ALT_EMAC_GMAC_LYR4_ADDR2_OFST 0x464
32073 /* The address of the ALT_EMAC_GMAC_LYR4_ADDR2 register. */
32074 #define ALT_EMAC_GMAC_LYR4_ADDR2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR4_ADDR2_OFST))
32075 
32076 /*
32077  * Register : Register 284 (Layer 3 Address 0 Register 2) - gmacgrp_layer3_addr0_reg2
32078  *
32079  * For IPv4 frames, the Layer 3 Address 0 Register 2 contains the 32-bit IP Source
32080  * Address field. For IPv6 frames, it contains Bits [31:0] of the 128-bit IP Source
32081  * Address or Destination Address field.
32082  *
32083  * Register Layout
32084  *
32085  * Bits | Access | Reset | Description
32086  * :-------|:-------|:------|:------------------------
32087  * [31:0] | RW | 0x0 | Layer 3 Address 0 Field
32088  *
32089  */
32090 /*
32091  * Field : Layer 3 Address 0 Field - l3a02
32092  *
32093  * When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and
32094  * Layer 4 Control Register 2), this field contains the value to be matched with
32095  * Bits [31:0] of the IP Source Address field in the IPv6 frames.
32096  *
32097  * When Bit 0 (L3PEN2) and Bit 4 (L3DAM2) are set in Register 280 (Layer 3 and
32098  * Layer 4 Control Register 2), this field contains the value to be matched with
32099  * Bits [31:0] of the IP Destination Address field in the IPv6 frames.
32100  *
32101  * When Bit 0 (L3PEN2) is reset and Bit 2 (L3SAM2) is set in Register 280 (Layer 3
32102  * and Layer 4 Control Register 2), this field contains the value to be matched
32103  * with the IP Source Address field in the IPv4 frames.
32104  *
32105  * Field Access Macros:
32106  *
32107  */
32108 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field. */
32109 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_LSB 0
32110 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field. */
32111 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_MSB 31
32112 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field. */
32113 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_WIDTH 32
32114 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field value. */
32115 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_SET_MSK 0xffffffff
32116 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field value. */
32117 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_CLR_MSK 0x00000000
32118 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field. */
32119 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_RESET 0x0
32120 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 field value from a register. */
32121 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_GET(value) (((value) & 0xffffffff) >> 0)
32122 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field value suitable for setting the register. */
32123 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_SET(value) (((value) << 0) & 0xffffffff)
32124 
32125 #ifndef __ASSEMBLY__
32126 /*
32127  * WARNING: The C register and register group struct declarations are provided for
32128  * convenience and illustrative purposes. They should, however, be used with
32129  * caution as the C language standard provides no guarantees about the alignment or
32130  * atomicity of device memory accesses. The recommended practice for writing
32131  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
32132  * alt_write_word() functions.
32133  *
32134  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG2.
32135  */
32136 struct ALT_EMAC_GMAC_LYR3_ADDR0_REG2_s
32137 {
32138  uint32_t l3a02 : 32; /* Layer 3 Address 0 Field */
32139 };
32140 
32141 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG2. */
32142 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR0_REG2_s ALT_EMAC_GMAC_LYR3_ADDR0_REG2_t;
32143 #endif /* __ASSEMBLY__ */
32144 
32145 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2 register. */
32146 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_RESET 0x00000000
32147 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2 register from the beginning of the component. */
32148 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_OFST 0x470
32149 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2 register. */
32150 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR0_REG2_OFST))
32151 
32152 /*
32153  * Register : Register 285 (Layer 3 Address 1 Register 2) - gmacgrp_layer3_addr1_reg2
32154  *
32155  * For IPv4 frames, the Layer 3 Address 1 Register 2 contains the 32-bit IP
32156  * Destination Address field. For IPv6 frames, it contains Bits [63:32] of the
32157  * 128-bit IP Source Address or Destination Address field.
32158  *
32159  * Register Layout
32160  *
32161  * Bits | Access | Reset | Description
32162  * :-------|:-------|:------|:------------------------
32163  * [31:0] | RW | 0x0 | Layer 3 Address 1 Field
32164  *
32165  */
32166 /*
32167  * Field : Layer 3 Address 1 Field - l3a12
32168  *
32169  * Layer 3 Address 1 Field
32170  *
32171  * When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and
32172  * Layer 4 Control Register 2), this field contains the value to be matched with
32173  * Bits [63:32] of the IP Source Address field in the IPv6 frames.
32174  *
32175  * When Bit 0 (L3PEN2) and Bit 4 (L3DAM2) are set in Register 280 (Layer 3 and
32176  * Layer 4 Control Register 2), this field contains the value to be matched with
32177  * Bits [63:32] of the IP Destination Address field in the IPv6 frames.
32178  *
32179  * When Bit 0 (L3PEN2) is reset and Bit 4 (L3DAM2) is set in Register 280 (Layer 3
32180  * and Layer 4 Control Register 2), this field contains the value to be matched
32181  * with the IP Destination Address field in the IPv4 frames.
32182  *
32183  * Field Access Macros:
32184  *
32185  */
32186 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field. */
32187 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_LSB 0
32188 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field. */
32189 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_MSB 31
32190 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field. */
32191 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_WIDTH 32
32192 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field value. */
32193 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_SET_MSK 0xffffffff
32194 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field value. */
32195 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_CLR_MSK 0x00000000
32196 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field. */
32197 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_RESET 0x0
32198 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 field value from a register. */
32199 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_GET(value) (((value) & 0xffffffff) >> 0)
32200 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field value suitable for setting the register. */
32201 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_SET(value) (((value) << 0) & 0xffffffff)
32202 
32203 #ifndef __ASSEMBLY__
32204 /*
32205  * WARNING: The C register and register group struct declarations are provided for
32206  * convenience and illustrative purposes. They should, however, be used with
32207  * caution as the C language standard provides no guarantees about the alignment or
32208  * atomicity of device memory accesses. The recommended practice for writing
32209  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
32210  * alt_write_word() functions.
32211  *
32212  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG2.
32213  */
32214 struct ALT_EMAC_GMAC_LYR3_ADDR1_REG2_s
32215 {
32216  uint32_t l3a12 : 32; /* Layer 3 Address 1 Field */
32217 };
32218 
32219 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG2. */
32220 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR1_REG2_s ALT_EMAC_GMAC_LYR3_ADDR1_REG2_t;
32221 #endif /* __ASSEMBLY__ */
32222 
32223 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2 register. */
32224 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_RESET 0x00000000
32225 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2 register from the beginning of the component. */
32226 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_OFST 0x474
32227 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2 register. */
32228 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR1_REG2_OFST))
32229 
32230 /*
32231  * Register : Register 286 (Layer 3 Address 2 Register 2) - gmacgrp_layer3_addr2_reg2
32232  *
32233  * For IPv4 frames, the Layer 3 Address 2 Register 2 is reserved. For IPv6 frames,
32234  * it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address
32235  * field.
32236  *
32237  * Register Layout
32238  *
32239  * Bits | Access | Reset | Description
32240  * :-------|:-------|:------|:------------------------
32241  * [31:0] | RW | 0x0 | Layer 3 Address 2 Field
32242  *
32243  */
32244 /*
32245  * Field : Layer 3 Address 2 Field - l3a22
32246  *
32247  * When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and
32248  * Layer 4 Control Register 2), this field contains the value to be matched with
32249  * Bits [95:64] of the IP Source Address field in the IPv6 frames.
32250  *
32251  * When Bit 0 (L3PEN2) and Bit 4 (L3DAM2) are set in Register 256 (Layer 3 and
32252  * Layer 4 Control Register 2), this field contains value to be matched with Bits
32253  * [95:64] of the IP Destination Address field in the IPv6 frames.
32254  *
32255  * When Bit 0 (L3PEN2) is reset in Register 280 (Layer 3 and Layer 4 Control
32256  * Register 2), this register is not used.
32257  *
32258  * Field Access Macros:
32259  *
32260  */
32261 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field. */
32262 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_LSB 0
32263 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field. */
32264 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_MSB 31
32265 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field. */
32266 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_WIDTH 32
32267 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field value. */
32268 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_SET_MSK 0xffffffff
32269 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field value. */
32270 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_CLR_MSK 0x00000000
32271 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field. */
32272 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_RESET 0x0
32273 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 field value from a register. */
32274 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_GET(value) (((value) & 0xffffffff) >> 0)
32275 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field value suitable for setting the register. */
32276 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_SET(value) (((value) << 0) & 0xffffffff)
32277 
32278 #ifndef __ASSEMBLY__
32279 /*
32280  * WARNING: The C register and register group struct declarations are provided for
32281  * convenience and illustrative purposes. They should, however, be used with
32282  * caution as the C language standard provides no guarantees about the alignment or
32283  * atomicity of device memory accesses. The recommended practice for writing
32284  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
32285  * alt_write_word() functions.
32286  *
32287  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG2.
32288  */
32289 struct ALT_EMAC_GMAC_LYR3_ADDR2_REG2_s
32290 {
32291  uint32_t l3a22 : 32; /* Layer 3 Address 2 Field */
32292 };
32293 
32294 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG2. */
32295 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR2_REG2_s ALT_EMAC_GMAC_LYR3_ADDR2_REG2_t;
32296 #endif /* __ASSEMBLY__ */
32297 
32298 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2 register. */
32299 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_RESET 0x00000000
32300 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2 register from the beginning of the component. */
32301 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_OFST 0x478
32302 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2 register. */
32303 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR2_REG2_OFST))
32304 
32305 /*
32306  * Register : Register 287 (Layer 3 Address 3 Register 2) - gmacgrp_layer3_addr3_reg2
32307  *
32308  * For IPv4 frames, the Layer 3 Address 3 Register 2 is reserved. For IPv6 frames,
32309  * it contains Bits [127:96] of the 128-bit IP Source Address or Destination
32310  * Address field.
32311  *
32312  * Register Layout
32313  *
32314  * Bits | Access | Reset | Description
32315  * :-------|:-------|:------|:------------------------
32316  * [31:0] | RW | 0x0 | Layer 3 Address 3 Field
32317  *
32318  */
32319 /*
32320  * Field : Layer 3 Address 3 Field - l3a32
32321  *
32322  * When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and
32323  * Layer 4 Control Register 2), this field contains the value to be matched with
32324  * Bits [127:96] of the IP Source Address field in the IPv6 frames.
32325  *
32326  * When Bit 0 (L3PEN2) and Bit 4 (L3DAM2) are set in Register 280 (Layer 3 and
32327  * Layer 4 Control Register 2), this field contains the value to be matched with
32328  * Bits [127:96] of the IP Destination Address field in the IPv6 frames.
32329  *
32330  * When Bit 0 (L3PEN2) is reset in Register 280 (Layer 3 and Layer 4 Control
32331  * Register 2), this register is not used.
32332  *
32333  * Field Access Macros:
32334  *
32335  */
32336 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field. */
32337 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_LSB 0
32338 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field. */
32339 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_MSB 31
32340 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field. */
32341 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_WIDTH 32
32342 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field value. */
32343 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_SET_MSK 0xffffffff
32344 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field value. */
32345 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_CLR_MSK 0x00000000
32346 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field. */
32347 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_RESET 0x0
32348 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 field value from a register. */
32349 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_GET(value) (((value) & 0xffffffff) >> 0)
32350 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field value suitable for setting the register. */
32351 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_SET(value) (((value) << 0) & 0xffffffff)
32352 
32353 #ifndef __ASSEMBLY__
32354 /*
32355  * WARNING: The C register and register group struct declarations are provided for
32356  * convenience and illustrative purposes. They should, however, be used with
32357  * caution as the C language standard provides no guarantees about the alignment or
32358  * atomicity of device memory accesses. The recommended practice for writing
32359  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
32360  * alt_write_word() functions.
32361  *
32362  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG2.
32363  */
32364 struct ALT_EMAC_GMAC_LYR3_ADDR3_REG2_s
32365 {
32366  uint32_t l3a32 : 32; /* Layer 3 Address 3 Field */
32367 };
32368 
32369 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG2. */
32370 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR3_REG2_s ALT_EMAC_GMAC_LYR3_ADDR3_REG2_t;
32371 #endif /* __ASSEMBLY__ */
32372 
32373 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2 register. */
32374 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_RESET 0x00000000
32375 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2 register from the beginning of the component. */
32376 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_OFST 0x47c
32377 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2 register. */
32378 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR3_REG2_OFST))
32379 
32380 /*
32381  * Register : Register 292 (Layer 3 and Layer 4 Control Register 3) - gmacgrp_l3_l4_control3
32382  *
32383  * This register controls the operations of the filter 0 of Layer 3 and Layer 4.
32384  *
32385  * Register Layout
32386  *
32387  * Bits | Access | Reset | Description
32388  * :--------|:-------|:------|:----------------------------------------------
32389  * [0] | RW | 0x0 | Layer 3 Protocol Enable
32390  * [1] | ??? | 0x0 | *UNDEFINED*
32391  * [2] | RW | 0x0 | Layer 3 IP SA Match Enable
32392  * [3] | RW | 0x0 | Layer 3 IP SA Inverse Match Enable
32393  * [4] | RW | 0x0 | Layer 3 IP DA Match Enable
32394  * [5] | RW | 0x0 | Layer 3 IP DA Inverse Match Enable
32395  * [10:6] | RW | 0x0 | Layer 3 IP SA Higher Bits Match
32396  * [15:11] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3
32397  * [16] | RW | 0x0 | Layer 4 Protocol Enable
32398  * [17] | ??? | 0x0 | *UNDEFINED*
32399  * [18] | RW | 0x0 | Layer 4 Source Port Match Enable
32400  * [19] | RW | 0x0 | Layer 4 Source Port Inverse Match Enable
32401  * [20] | RW | 0x0 | Layer 4 Destination Port Match Enable
32402  * [21] | RW | 0x0 | Layer 4 Destination Port Inverse Match Enable
32403  * [31:22] | ??? | 0x0 | *UNDEFINED*
32404  *
32405  */
32406 /*
32407  * Field : Layer 3 Protocol Enable - l3pen3
32408  *
32409  * When set, this bit indicates that the Layer 3 IP Source or Destination Address
32410  * matching is enabled for the IPv6 frames. When reset, this bit indicates that the
32411  * Layer 3 IP Source or Destination Address matching is enabled for the IPv4
32412  * frames.
32413  *
32414  * The Layer 3 matching is done only when either L3SAM3 or L3DAM3 bit is set high.
32415  *
32416  * Field Access Macros:
32417  *
32418  */
32419 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field. */
32420 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_LSB 0
32421 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field. */
32422 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_MSB 0
32423 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field. */
32424 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_WIDTH 1
32425 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field value. */
32426 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_SET_MSK 0x00000001
32427 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field value. */
32428 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_CLR_MSK 0xfffffffe
32429 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field. */
32430 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_RESET 0x0
32431 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 field value from a register. */
32432 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_GET(value) (((value) & 0x00000001) >> 0)
32433 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field value suitable for setting the register. */
32434 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_SET(value) (((value) << 0) & 0x00000001)
32435 
32436 /*
32437  * Field : Layer 3 IP SA Match Enable - l3sam3
32438  *
32439  * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
32440  * for matching. When reset, the MAC ignores the Layer 3 IP Source Address field
32441  * for matching.
32442  *
32443  * Note: When Bit 0 (L3PEN3) is set, you should set either this bit or Bit 4
32444  * (L3DAM3) because either IPv6 SA or DA can be checked for filtering.
32445  *
32446  * Field Access Macros:
32447  *
32448  */
32449 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field. */
32450 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_LSB 2
32451 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field. */
32452 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_MSB 2
32453 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field. */
32454 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_WIDTH 1
32455 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field value. */
32456 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_SET_MSK 0x00000004
32457 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field value. */
32458 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_CLR_MSK 0xfffffffb
32459 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field. */
32460 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_RESET 0x0
32461 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 field value from a register. */
32462 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_GET(value) (((value) & 0x00000004) >> 2)
32463 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field value suitable for setting the register. */
32464 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_SET(value) (((value) << 2) & 0x00000004)
32465 
32466 /*
32467  * Field : Layer 3 IP SA Inverse Match Enable - l3saim3
32468  *
32469  * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
32470  * for inverse matching. When reset, this bit indicates that the Layer 3 IP Source
32471  * Address field is enabled for perfect matching.
32472  *
32473  * This bit is valid and applicable only when Bit 2 (L3SAM3) is set high.
32474  *
32475  * Field Access Macros:
32476  *
32477  */
32478 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field. */
32479 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_LSB 3
32480 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field. */
32481 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_MSB 3
32482 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field. */
32483 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_WIDTH 1
32484 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field value. */
32485 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_SET_MSK 0x00000008
32486 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field value. */
32487 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_CLR_MSK 0xfffffff7
32488 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field. */
32489 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_RESET 0x0
32490 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 field value from a register. */
32491 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_GET(value) (((value) & 0x00000008) >> 3)
32492 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field value suitable for setting the register. */
32493 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_SET(value) (((value) << 3) & 0x00000008)
32494 
32495 /*
32496  * Field : Layer 3 IP DA Match Enable - l3dam3
32497  *
32498  * When set, this bit indicates that Layer 3 IP Destination Address field is
32499  * enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination
32500  * Address field for matching.
32501  *
32502  * Note: When Bit 0 (L3PEN3) is set, you should set either this bit or Bit 2
32503  * (L3SAM3) because either IPv6 DA or SA can be checked for filtering.
32504  *
32505  * Field Access Macros:
32506  *
32507  */
32508 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field. */
32509 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_LSB 4
32510 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field. */
32511 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_MSB 4
32512 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field. */
32513 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_WIDTH 1
32514 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field value. */
32515 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_SET_MSK 0x00000010
32516 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field value. */
32517 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_CLR_MSK 0xffffffef
32518 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field. */
32519 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_RESET 0x0
32520 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 field value from a register. */
32521 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_GET(value) (((value) & 0x00000010) >> 4)
32522 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field value suitable for setting the register. */
32523 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_SET(value) (((value) << 4) & 0x00000010)
32524 
32525 /*
32526  * Field : Layer 3 IP DA Inverse Match Enable - l3daim3
32527  *
32528  * When set, this bit indicates that the Layer 3 IP Destination Address field is
32529  * enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP
32530  * Destination Address field is enabled for perfect matching.
32531  *
32532  * This bit is valid and applicable only when Bit 4 (L3DAM3) is set high.
32533  *
32534  * Field Access Macros:
32535  *
32536  */
32537 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field. */
32538 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_LSB 5
32539 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field. */
32540 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_MSB 5
32541 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field. */
32542 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_WIDTH 1
32543 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field value. */
32544 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_SET_MSK 0x00000020
32545 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field value. */
32546 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_CLR_MSK 0xffffffdf
32547 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field. */
32548 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_RESET 0x0
32549 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 field value from a register. */
32550 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_GET(value) (((value) & 0x00000020) >> 5)
32551 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field value suitable for setting the register. */
32552 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_SET(value) (((value) << 5) & 0x00000020)
32553 
32554 /*
32555  * Field : Layer 3 IP SA Higher Bits Match - l3hsbm3
32556  *
32557  * IPv4 Frames:
32558  *
32559  * This field contains the number of lower bits of IP Source Address that are
32560  * masked for matching in the IPv4 frames. The following list describes the values
32561  * of this field:
32562  *
32563  * * 0: No bits are masked.
32564  *
32565  * * 1: LSb[0] is masked.
32566  *
32567  * * 2: Two LSbs [1:0] are masked.
32568  *
32569  * * ...
32570  *
32571  * * 31: All bits except MSb are masked.
32572  *
32573  * IPv6 Frames:
32574  *
32575  * This field contains Bits [4:0] of the field that indicates the number of higher
32576  * bits of IP Source or Destination Address matched in the IPv6 frames.
32577  *
32578  * This field is valid and applicable only if L3DAM3 or L3SAM3 is set high.
32579  *
32580  * Field Access Macros:
32581  *
32582  */
32583 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field. */
32584 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_LSB 6
32585 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field. */
32586 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_MSB 10
32587 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field. */
32588 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_WIDTH 5
32589 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field value. */
32590 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_SET_MSK 0x000007c0
32591 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field value. */
32592 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_CLR_MSK 0xfffff83f
32593 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field. */
32594 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_RESET 0x0
32595 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 field value from a register. */
32596 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_GET(value) (((value) & 0x000007c0) >> 6)
32597 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field value suitable for setting the register. */
32598 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_SET(value) (((value) << 6) & 0x000007c0)
32599 
32600 /*
32601  * Field : l3hdbm3
32602  *
32603  * Layer 3 IP DA Higher Bits Match
32604  *
32605  * IPv4 Frames:
32606  *
32607  * This field contains the number of higher bits of IP Destination Address that are
32608  * matched in the IPv4 frames. The following list describes the values of this
32609  * field:
32610  *
32611  * * 0: No bits are masked.
32612  *
32613  * * 1: LSb[0] is masked.
32614  *
32615  * * 2: Two LSbs [1:0] are masked.
32616  *
32617  * * ...
32618  *
32619  * * 31: All bits except MSb are masked.
32620  *
32621  * IPv6 Frames:
32622  *
32623  * Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM3, which indicate
32624  * the number of lower bits of IP Source or Destination Address that are masked in
32625  * the IPv6 frames. The following list describes the concatenated values of the
32626  * L3HDBM3[1:0] and L3HSBM3 bits:
32627  *
32628  * * 0: No bits are masked.
32629  *
32630  * * 1: LSb[0] is masked.
32631  *
32632  * * 2: Two LSbs [1:0] are masked.
32633  *
32634  * * ...
32635  *
32636  * * 127: All bits except MSb are masked.
32637  *
32638  * This field is valid and applicable only if L3DAM3 or L3SAM3 is set high.
32639  *
32640  * Field Access Macros:
32641  *
32642  */
32643 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field. */
32644 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_LSB 11
32645 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field. */
32646 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_MSB 15
32647 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field. */
32648 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_WIDTH 5
32649 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field value. */
32650 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_SET_MSK 0x0000f800
32651 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field value. */
32652 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_CLR_MSK 0xffff07ff
32653 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field. */
32654 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_RESET 0x0
32655 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 field value from a register. */
32656 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_GET(value) (((value) & 0x0000f800) >> 11)
32657 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field value suitable for setting the register. */
32658 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_SET(value) (((value) << 11) & 0x0000f800)
32659 
32660 /*
32661  * Field : Layer 4 Protocol Enable - l4pen3
32662  *
32663  * When set, this bit indicates that the Source and Destination Port number fields
32664  * for UDP frames are used for matching. When reset, this bit indicates that the
32665  * Source and Destination Port number fields for TCP frames are used for matching.
32666  *
32667  * The Layer 4 matching is done only when either L4SPM3 or L4DPM3 bit is set high.
32668  *
32669  * Field Access Macros:
32670  *
32671  */
32672 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field. */
32673 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_LSB 16
32674 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field. */
32675 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_MSB 16
32676 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field. */
32677 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_WIDTH 1
32678 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field value. */
32679 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_SET_MSK 0x00010000
32680 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field value. */
32681 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_CLR_MSK 0xfffeffff
32682 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field. */
32683 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_RESET 0x0
32684 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 field value from a register. */
32685 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_GET(value) (((value) & 0x00010000) >> 16)
32686 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field value suitable for setting the register. */
32687 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_SET(value) (((value) << 16) & 0x00010000)
32688 
32689 /*
32690  * Field : Layer 4 Source Port Match Enable - l4spm3
32691  *
32692  * When set, this bit indicates that the Layer 4 Source Port number field is
32693  * enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number
32694  * field for matching.
32695  *
32696  * Field Access Macros:
32697  *
32698  */
32699 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field. */
32700 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_LSB 18
32701 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field. */
32702 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_MSB 18
32703 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field. */
32704 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_WIDTH 1
32705 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field value. */
32706 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_SET_MSK 0x00040000
32707 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field value. */
32708 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_CLR_MSK 0xfffbffff
32709 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field. */
32710 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_RESET 0x0
32711 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 field value from a register. */
32712 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_GET(value) (((value) & 0x00040000) >> 18)
32713 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field value suitable for setting the register. */
32714 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_SET(value) (((value) << 18) & 0x00040000)
32715 
32716 /*
32717  * Field : Layer 4 Source Port Inverse Match Enable - l4spim3
32718  *
32719  * When set, this bit indicates that the Layer 4 Source Port number field is
32720  * enabled for inverse matching. When reset, this bit indicates that the Layer 4
32721  * Source Port number field is enabled for perfect matching.
32722  *
32723  * This bit is valid and applicable only when Bit 18 (L4SPM3) is set high.
32724  *
32725  * Field Access Macros:
32726  *
32727  */
32728 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field. */
32729 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_LSB 19
32730 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field. */
32731 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_MSB 19
32732 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field. */
32733 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_WIDTH 1
32734 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field value. */
32735 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_SET_MSK 0x00080000
32736 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field value. */
32737 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_CLR_MSK 0xfff7ffff
32738 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field. */
32739 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_RESET 0x0
32740 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 field value from a register. */
32741 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_GET(value) (((value) & 0x00080000) >> 19)
32742 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field value suitable for setting the register. */
32743 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_SET(value) (((value) << 19) & 0x00080000)
32744 
32745 /*
32746  * Field : Layer 4 Destination Port Match Enable - l4dpm3
32747  *
32748  * When set, this bit indicates that the Layer 4 Destination Port number field is
32749  * enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port
32750  * number field for matching.
32751  *
32752  * Field Access Macros:
32753  *
32754  */
32755 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field. */
32756 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_LSB 20
32757 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field. */
32758 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_MSB 20
32759 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field. */
32760 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_WIDTH 1
32761 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field value. */
32762 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_SET_MSK 0x00100000
32763 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field value. */
32764 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_CLR_MSK 0xffefffff
32765 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field. */
32766 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_RESET 0x0
32767 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 field value from a register. */
32768 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_GET(value) (((value) & 0x00100000) >> 20)
32769 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field value suitable for setting the register. */
32770 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_SET(value) (((value) << 20) & 0x00100000)
32771 
32772 /*
32773  * Field : Layer 4 Destination Port Inverse Match Enable - l4dpim3
32774  *
32775  * When set, this bit indicates that the Layer 4 Destination Port number field is
32776  * enabled for inverse matching. When reset, this bit indicates that the Layer 4
32777  * Destination Port number field is enabled for perfect matching.
32778  *
32779  * This bit is valid and applicable only when Bit 20 (L4DPM3) is set high.
32780  *
32781  * Field Access Macros:
32782  *
32783  */
32784 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field. */
32785 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_LSB 21
32786 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field. */
32787 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_MSB 21
32788 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field. */
32789 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_WIDTH 1
32790 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field value. */
32791 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_SET_MSK 0x00200000
32792 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field value. */
32793 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_CLR_MSK 0xffdfffff
32794 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field. */
32795 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_RESET 0x0
32796 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 field value from a register. */
32797 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_GET(value) (((value) & 0x00200000) >> 21)
32798 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field value suitable for setting the register. */
32799 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_SET(value) (((value) << 21) & 0x00200000)
32800 
32801 #ifndef __ASSEMBLY__
32802 /*
32803  * WARNING: The C register and register group struct declarations are provided for
32804  * convenience and illustrative purposes. They should, however, be used with
32805  * caution as the C language standard provides no guarantees about the alignment or
32806  * atomicity of device memory accesses. The recommended practice for writing
32807  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
32808  * alt_write_word() functions.
32809  *
32810  * The struct declaration for register ALT_EMAC_GMAC_L3_L4_CTL3.
32811  */
32812 struct ALT_EMAC_GMAC_L3_L4_CTL3_s
32813 {
32814  uint32_t l3pen3 : 1; /* Layer 3 Protocol Enable */
32815  uint32_t : 1; /* *UNDEFINED* */
32816  uint32_t l3sam3 : 1; /* Layer 3 IP SA Match Enable */
32817  uint32_t l3saim3 : 1; /* Layer 3 IP SA Inverse Match Enable */
32818  uint32_t l3dam3 : 1; /* Layer 3 IP DA Match Enable */
32819  uint32_t l3daim3 : 1; /* Layer 3 IP DA Inverse Match Enable */
32820  uint32_t l3hsbm3 : 5; /* Layer 3 IP SA Higher Bits Match */
32821  uint32_t l3hdbm3 : 5; /* ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 */
32822  uint32_t l4pen3 : 1; /* Layer 4 Protocol Enable */
32823  uint32_t : 1; /* *UNDEFINED* */
32824  uint32_t l4spm3 : 1; /* Layer 4 Source Port Match Enable */
32825  uint32_t l4spim3 : 1; /* Layer 4 Source Port Inverse Match Enable */
32826  uint32_t l4dpm3 : 1; /* Layer 4 Destination Port Match Enable */
32827  uint32_t l4dpim3 : 1; /* Layer 4 Destination Port Inverse Match Enable */
32828  uint32_t : 10; /* *UNDEFINED* */
32829 };
32830 
32831 /* The typedef declaration for register ALT_EMAC_GMAC_L3_L4_CTL3. */
32832 typedef volatile struct ALT_EMAC_GMAC_L3_L4_CTL3_s ALT_EMAC_GMAC_L3_L4_CTL3_t;
32833 #endif /* __ASSEMBLY__ */
32834 
32835 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3 register. */
32836 #define ALT_EMAC_GMAC_L3_L4_CTL3_RESET 0x00000000
32837 /* The byte offset of the ALT_EMAC_GMAC_L3_L4_CTL3 register from the beginning of the component. */
32838 #define ALT_EMAC_GMAC_L3_L4_CTL3_OFST 0x490
32839 /* The address of the ALT_EMAC_GMAC_L3_L4_CTL3 register. */
32840 #define ALT_EMAC_GMAC_L3_L4_CTL3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_L3_L4_CTL3_OFST))
32841 
32842 /*
32843  * Register : Register 293 (Layer 4 Address Register 3) - gmacgrp_layer4_address3
32844  *
32845  * Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the
32846  * Rx clock domains, then the synchronization is triggered only when Bits[31:24]
32847  * (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and
32848  * Layer 4 Address Registers are written. For proper synchronization updates, you
32849  * should perform the consecutive writes to the same Layer 3 and Layer 4 Address
32850  * Registers after at least four clock cycles delay of the destination clock.
32851  *
32852  * Register Layout
32853  *
32854  * Bits | Access | Reset | Description
32855  * :--------|:-------|:------|:--------------------------------------
32856  * [15:0] | RW | 0x0 | Layer 4 Source Port Number Field
32857  * [31:16] | RW | 0x0 | Layer 4 Destination Port Number Field
32858  *
32859  */
32860 /*
32861  * Field : Layer 4 Source Port Number Field - l4sp3
32862  *
32863  * When Bit 16 (L4PEN3) is reset and Bit 20 (L4DPM3) is set in Register 292 (Layer
32864  * 3 and Layer 4 Control Register 3), this field contains the value to be matched
32865  * with the TCP Source Port Number field in the IPv4 or IPv6 frames.
32866  *
32867  * When Bit 16 (L4PEN3) and Bit 20 (L4DPM3) are set in Register 292 (Layer 3 and
32868  * Layer 4 Control Register 3), this field contains the value to be matched with
32869  * the UDP Source Port Number field in the IPv4 or IPv6 frames.
32870  *
32871  * Field Access Macros:
32872  *
32873  */
32874 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field. */
32875 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_LSB 0
32876 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field. */
32877 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_MSB 15
32878 /* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field. */
32879 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_WIDTH 16
32880 /* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field value. */
32881 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_SET_MSK 0x0000ffff
32882 /* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field value. */
32883 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_CLR_MSK 0xffff0000
32884 /* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field. */
32885 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_RESET 0x0
32886 /* Extracts the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 field value from a register. */
32887 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_GET(value) (((value) & 0x0000ffff) >> 0)
32888 /* Produces a ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field value suitable for setting the register. */
32889 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_SET(value) (((value) << 0) & 0x0000ffff)
32890 
32891 /*
32892  * Field : Layer 4 Destination Port Number Field - l4dp3
32893  *
32894  * When Bit 16 (L4PEN3) is reset and Bit 20 (L4DPM3) is set in Register 292 (Layer
32895  * 3 and Layer 4 Control Register 3), this field contains the value to be matched
32896  * with the TCP Destination Port Number field in the IPv4 or IPv6 frames.
32897  *
32898  * When Bit 16 (L4PEN3) and Bit 20 (L4DPM3) are set in Register 292 (Layer 3 and
32899  * Layer 4 Control Register 3), this field contains the value to be matched with
32900  * the UDP Destination Port Number field in the IPv4 or IPv6 frames.
32901  *
32902  * Field Access Macros:
32903  *
32904  */
32905 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field. */
32906 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_LSB 16
32907 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field. */
32908 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_MSB 31
32909 /* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field. */
32910 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_WIDTH 16
32911 /* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field value. */
32912 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_SET_MSK 0xffff0000
32913 /* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field value. */
32914 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_CLR_MSK 0x0000ffff
32915 /* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field. */
32916 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_RESET 0x0
32917 /* Extracts the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 field value from a register. */
32918 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_GET(value) (((value) & 0xffff0000) >> 16)
32919 /* Produces a ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field value suitable for setting the register. */
32920 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_SET(value) (((value) << 16) & 0xffff0000)
32921 
32922 #ifndef __ASSEMBLY__
32923 /*
32924  * WARNING: The C register and register group struct declarations are provided for
32925  * convenience and illustrative purposes. They should, however, be used with
32926  * caution as the C language standard provides no guarantees about the alignment or
32927  * atomicity of device memory accesses. The recommended practice for writing
32928  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
32929  * alt_write_word() functions.
32930  *
32931  * The struct declaration for register ALT_EMAC_GMAC_LYR4_ADDR3.
32932  */
32933 struct ALT_EMAC_GMAC_LYR4_ADDR3_s
32934 {
32935  uint32_t l4sp3 : 16; /* Layer 4 Source Port Number Field */
32936  uint32_t l4dp3 : 16; /* Layer 4 Destination Port Number Field */
32937 };
32938 
32939 /* The typedef declaration for register ALT_EMAC_GMAC_LYR4_ADDR3. */
32940 typedef volatile struct ALT_EMAC_GMAC_LYR4_ADDR3_s ALT_EMAC_GMAC_LYR4_ADDR3_t;
32941 #endif /* __ASSEMBLY__ */
32942 
32943 /* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR3 register. */
32944 #define ALT_EMAC_GMAC_LYR4_ADDR3_RESET 0x00000000
32945 /* The byte offset of the ALT_EMAC_GMAC_LYR4_ADDR3 register from the beginning of the component. */
32946 #define ALT_EMAC_GMAC_LYR4_ADDR3_OFST 0x494
32947 /* The address of the ALT_EMAC_GMAC_LYR4_ADDR3 register. */
32948 #define ALT_EMAC_GMAC_LYR4_ADDR3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR4_ADDR3_OFST))
32949 
32950 /*
32951  * Register : Register 296 (Layer 3 Address 0 Register 3) - gmacgrp_layer3_addr0_reg3
32952  *
32953  * For IPv4 frames, the Layer 3 Address 0 Register 3 contains the 32-bit IP Source
32954  * Address field. For IPv6 frames, it contains Bits [31:0] of the 128-bit IP Source
32955  * Address or Destination Address field.
32956  *
32957  * Register Layout
32958  *
32959  * Bits | Access | Reset | Description
32960  * :-------|:-------|:------|:------------------------
32961  * [31:0] | RW | 0x0 | Layer 3 Address 0 Field
32962  *
32963  */
32964 /*
32965  * Field : Layer 3 Address 0 Field - l3a03
32966  *
32967  * When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and
32968  * Layer 4 Control Register 3), this field contains the value to be matched with
32969  * Bits [31:0] of the IP Source Address field in the IPv6 frames.
32970  *
32971  * When Bit 0 (L3PEN3) and Bit 4 (L3DAM3) are set in Register 292 (Layer 3 and
32972  * Layer 4 Control Register 3), this field contains the value to be matched with
32973  * Bits [31:0] of the IP Destination Address field in the IPv6 frames.
32974  *
32975  * When Bit 0 (L3PEN3) is reset and Bit 2 (L3SAM3) is set in Register 292 (Layer 3
32976  * and Layer 4 Control Register 3), this field contains the value to be matched
32977  * with the IP Source Address field in the IPv4 frames.
32978  *
32979  * Field Access Macros:
32980  *
32981  */
32982 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field. */
32983 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_LSB 0
32984 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field. */
32985 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_MSB 31
32986 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field. */
32987 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_WIDTH 32
32988 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field value. */
32989 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_SET_MSK 0xffffffff
32990 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field value. */
32991 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_CLR_MSK 0x00000000
32992 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field. */
32993 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_RESET 0x0
32994 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 field value from a register. */
32995 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_GET(value) (((value) & 0xffffffff) >> 0)
32996 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field value suitable for setting the register. */
32997 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_SET(value) (((value) << 0) & 0xffffffff)
32998 
32999 #ifndef __ASSEMBLY__
33000 /*
33001  * WARNING: The C register and register group struct declarations are provided for
33002  * convenience and illustrative purposes. They should, however, be used with
33003  * caution as the C language standard provides no guarantees about the alignment or
33004  * atomicity of device memory accesses. The recommended practice for writing
33005  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33006  * alt_write_word() functions.
33007  *
33008  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG3.
33009  */
33010 struct ALT_EMAC_GMAC_LYR3_ADDR0_REG3_s
33011 {
33012  uint32_t l3a03 : 32; /* Layer 3 Address 0 Field */
33013 };
33014 
33015 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG3. */
33016 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR0_REG3_s ALT_EMAC_GMAC_LYR3_ADDR0_REG3_t;
33017 #endif /* __ASSEMBLY__ */
33018 
33019 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3 register. */
33020 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_RESET 0x00000000
33021 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3 register from the beginning of the component. */
33022 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_OFST 0x4a0
33023 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3 register. */
33024 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR0_REG3_OFST))
33025 
33026 /*
33027  * Register : Register 297 (Layer 3 Address 1 Register 3) - gmacgrp_layer3_addr1_reg3
33028  *
33029  * For IPv4 frames, the Layer 3 Address 1 Register 3 contains the 32-bit IP
33030  * Destination Address field. For IPv6 frames, it contains Bits [63:32] of the
33031  * 128-bit IP Source Address or Destination Address field.
33032  *
33033  * Register Layout
33034  *
33035  * Bits | Access | Reset | Description
33036  * :-------|:-------|:------|:------------------------
33037  * [31:0] | RW | 0x0 | Layer 3 Address 1 Field
33038  *
33039  */
33040 /*
33041  * Field : Layer 3 Address 1 Field - l3a13
33042  *
33043  * When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and
33044  * Layer 4 Control Register 3), this field contains the value to be matched with
33045  * Bits [63:32] of the IP Source Address field in the IPv6 frames.
33046  *
33047  * When Bit 0 (L3PEN3) and Bit 4 (L3DAM3) are set in Register 292 (Layer 3 and
33048  * Layer 4 Control Register 3), this field contains the value to be matched with
33049  * Bits [63:32] of the IP Destination Address field in the IPv6 frames.
33050  *
33051  * When Bit 0 (L3PEN3) is reset and Bit 4 (L3DAM3) is set in Register 292 (Layer 3
33052  * and Layer 4 Control Register 3), this field contains the value to be matched
33053  * with the IP Destination Address field in the IPv4 frames.
33054  *
33055  * Field Access Macros:
33056  *
33057  */
33058 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field. */
33059 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_LSB 0
33060 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field. */
33061 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_MSB 31
33062 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field. */
33063 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_WIDTH 32
33064 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field value. */
33065 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_SET_MSK 0xffffffff
33066 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field value. */
33067 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_CLR_MSK 0x00000000
33068 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field. */
33069 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_RESET 0x0
33070 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 field value from a register. */
33071 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_GET(value) (((value) & 0xffffffff) >> 0)
33072 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field value suitable for setting the register. */
33073 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_SET(value) (((value) << 0) & 0xffffffff)
33074 
33075 #ifndef __ASSEMBLY__
33076 /*
33077  * WARNING: The C register and register group struct declarations are provided for
33078  * convenience and illustrative purposes. They should, however, be used with
33079  * caution as the C language standard provides no guarantees about the alignment or
33080  * atomicity of device memory accesses. The recommended practice for writing
33081  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33082  * alt_write_word() functions.
33083  *
33084  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG3.
33085  */
33086 struct ALT_EMAC_GMAC_LYR3_ADDR1_REG3_s
33087 {
33088  uint32_t l3a13 : 32; /* Layer 3 Address 1 Field */
33089 };
33090 
33091 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG3. */
33092 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR1_REG3_s ALT_EMAC_GMAC_LYR3_ADDR1_REG3_t;
33093 #endif /* __ASSEMBLY__ */
33094 
33095 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3 register. */
33096 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_RESET 0x00000000
33097 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3 register from the beginning of the component. */
33098 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_OFST 0x4a4
33099 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3 register. */
33100 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR1_REG3_OFST))
33101 
33102 /*
33103  * Register : Register 298 (Layer 3 Address 2 Register 3) - gmacgrp_layer3_addr2_reg3
33104  *
33105  * For IPv4 frames, the Layer 3 Address 2 Register 3 is reserved. For IPv6 frames,
33106  * it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address
33107  * field.
33108  *
33109  * Register Layout
33110  *
33111  * Bits | Access | Reset | Description
33112  * :-------|:-------|:------|:------------------------
33113  * [31:0] | RW | 0x0 | Layer 3 Address 2 Field
33114  *
33115  */
33116 /*
33117  * Field : Layer 3 Address 2 Field - l3a23
33118  *
33119  * When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and
33120  * Layer 4 Control Register 3), this field contains the value to be matched with
33121  * Bits [95:64] of the IP Source Address field in the IPv6 frames.
33122  *
33123  * When Bit 0 (L3PEN3) and Bit 4 (L3DAM3) are set in Register 292 (Layer 3 and
33124  * Layer 4 Control Register 3), this field contains value to be matched with Bits
33125  * [95:64] of the IP Destination Address field in the IPv6 frames.
33126  *
33127  * When Bit 0 (L3PEN3) is reset in Register 292 (Layer 3 and Layer 4 Control
33128  * Register 3), this register is not used.
33129  *
33130  * Field Access Macros:
33131  *
33132  */
33133 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field. */
33134 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_LSB 0
33135 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field. */
33136 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_MSB 31
33137 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field. */
33138 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_WIDTH 32
33139 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field value. */
33140 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_SET_MSK 0xffffffff
33141 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field value. */
33142 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_CLR_MSK 0x00000000
33143 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field. */
33144 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_RESET 0x0
33145 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 field value from a register. */
33146 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_GET(value) (((value) & 0xffffffff) >> 0)
33147 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field value suitable for setting the register. */
33148 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_SET(value) (((value) << 0) & 0xffffffff)
33149 
33150 #ifndef __ASSEMBLY__
33151 /*
33152  * WARNING: The C register and register group struct declarations are provided for
33153  * convenience and illustrative purposes. They should, however, be used with
33154  * caution as the C language standard provides no guarantees about the alignment or
33155  * atomicity of device memory accesses. The recommended practice for writing
33156  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33157  * alt_write_word() functions.
33158  *
33159  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG3.
33160  */
33161 struct ALT_EMAC_GMAC_LYR3_ADDR2_REG3_s
33162 {
33163  uint32_t l3a23 : 32; /* Layer 3 Address 2 Field */
33164 };
33165 
33166 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG3. */
33167 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR2_REG3_s ALT_EMAC_GMAC_LYR3_ADDR2_REG3_t;
33168 #endif /* __ASSEMBLY__ */
33169 
33170 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3 register. */
33171 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_RESET 0x00000000
33172 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3 register from the beginning of the component. */
33173 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_OFST 0x4a8
33174 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3 register. */
33175 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR2_REG3_OFST))
33176 
33177 /*
33178  * Register : Register 299 (Layer 3 Address 3 Register 3) - gmacgrp_layer3_addr3_reg3
33179  *
33180  * For IPv4 frames, the Layer 3 Address 3 Register 3 is reserved. For IPv6 frames,
33181  * it contains Bits [127:96] of the 128-bit IP Source Address or Destination
33182  * Address field.
33183  *
33184  * Register Layout
33185  *
33186  * Bits | Access | Reset | Description
33187  * :-------|:-------|:------|:------------------------
33188  * [31:0] | RW | 0x0 | Layer 3 Address 3 Field
33189  *
33190  */
33191 /*
33192  * Field : Layer 3 Address 3 Field - l3a33
33193  *
33194  * When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and
33195  * Layer 4 Control Register 3), this field contains the value to be matched with
33196  * Bits [127:96] of the IP Source Address field in the IPv6 frames.
33197  *
33198  * When Bit 0 (L3PEN3) and Bit 4 (L3DAM3) are set in Register 292 (Layer 3 and
33199  * Layer 4 Control Register 3), this field contains the value to be matched with
33200  * Bits [127:96] of the IP Destination Address field in the IPv6 frames.
33201  *
33202  * When Bit 0 (L3PEN3) is reset in Register 292 (Layer 3 and Layer 4 Control
33203  * Register 3), this register is not used.
33204  *
33205  * Field Access Macros:
33206  *
33207  */
33208 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field. */
33209 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_LSB 0
33210 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field. */
33211 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_MSB 31
33212 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field. */
33213 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_WIDTH 32
33214 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field value. */
33215 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_SET_MSK 0xffffffff
33216 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field value. */
33217 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_CLR_MSK 0x00000000
33218 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field. */
33219 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_RESET 0x0
33220 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 field value from a register. */
33221 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_GET(value) (((value) & 0xffffffff) >> 0)
33222 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field value suitable for setting the register. */
33223 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_SET(value) (((value) << 0) & 0xffffffff)
33224 
33225 #ifndef __ASSEMBLY__
33226 /*
33227  * WARNING: The C register and register group struct declarations are provided for
33228  * convenience and illustrative purposes. They should, however, be used with
33229  * caution as the C language standard provides no guarantees about the alignment or
33230  * atomicity of device memory accesses. The recommended practice for writing
33231  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33232  * alt_write_word() functions.
33233  *
33234  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG3.
33235  */
33236 struct ALT_EMAC_GMAC_LYR3_ADDR3_REG3_s
33237 {
33238  uint32_t l3a33 : 32; /* Layer 3 Address 3 Field */
33239 };
33240 
33241 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG3. */
33242 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR3_REG3_s ALT_EMAC_GMAC_LYR3_ADDR3_REG3_t;
33243 #endif /* __ASSEMBLY__ */
33244 
33245 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3 register. */
33246 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_RESET 0x00000000
33247 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3 register from the beginning of the component. */
33248 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_OFST 0x4ac
33249 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3 register. */
33250 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR3_REG3_OFST))
33251 
33252 /*
33253  * Register : Register 320 (Hash Table Register 0) - gmacgrp_hash_table_reg0
33254  *
33255  * This register contains the first 32 bits of the hash table.
33256  *
33257  * The 256-bit Hash table is used for group address filtering. For hash filtering,
33258  * the content of the destination address in the incoming frame is passed through
33259  * the CRC logic and the upper eight bits of the CRC register are used to index the
33260  * content of the Hash table. The most significant bits determines the register to
33261  * be used (Hash Table Register X), and the least significant five bits determine
33262  * the bit within the register. For example, a hash value of 8b'10111111 selects
33263  * Bit 31 of the Hash Table Register 5.
33264  *
33265  * The hash value of the destination address is calculated in the following way:
33266  *
33267  * 1. Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the
33268  * steps to calculate CRC32).
33269  *
33270  * 2. Perform bitwise reversal for the value obtained in Step 1.
33271  *
33272  * 3. Take the upper 8 bits from the value obtained in Step 2.
33273  *
33274  * If the corresponding bit value of the register is 1'b1, the frame is accepted.
33275  * Otherwise, it is rejected. If the Bit 1 (Pass All Multicast) is set in Register
33276  * 1 (MAC Frame Filter), then all multicast frames are accepted regardless of the
33277  * multicast hash values.
33278  *
33279  * Because the Hash Table register is double-synchronized to the (G)MII clock
33280  * domain, the synchronization is triggered only when Bits[31:24] (in little-endian
33281  * mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers
33282  * are written.
33283  *
33284  * Note: Because of double-synchronization, consecutive writes to this register
33285  * should be performed after at least four clock cycles in the destination clock
33286  * domain.
33287  *
33288  * Register Layout
33289  *
33290  * Bits | Access | Reset | Description
33291  * :-------|:-------|:------|:----------------------------
33292  * [31:0] | RW | 0x0 | First 32 bits of Hash Table
33293  *
33294  */
33295 /*
33296  * Field : First 32 bits of Hash Table - ht31t0
33297  *
33298  * This field contains the first 32 Bits (31:0) of the Hash table.
33299  *
33300  * Field Access Macros:
33301  *
33302  */
33303 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field. */
33304 #define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_LSB 0
33305 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field. */
33306 #define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_MSB 31
33307 /* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field. */
33308 #define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_WIDTH 32
33309 /* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field value. */
33310 #define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_SET_MSK 0xffffffff
33311 /* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field value. */
33312 #define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_CLR_MSK 0x00000000
33313 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field. */
33314 #define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_RESET 0x0
33315 /* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 field value from a register. */
33316 #define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_GET(value) (((value) & 0xffffffff) >> 0)
33317 /* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field value suitable for setting the register. */
33318 #define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_SET(value) (((value) << 0) & 0xffffffff)
33319 
33320 #ifndef __ASSEMBLY__
33321 /*
33322  * WARNING: The C register and register group struct declarations are provided for
33323  * convenience and illustrative purposes. They should, however, be used with
33324  * caution as the C language standard provides no guarantees about the alignment or
33325  * atomicity of device memory accesses. The recommended practice for writing
33326  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33327  * alt_write_word() functions.
33328  *
33329  * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG0.
33330  */
33331 struct ALT_EMAC_GMAC_HASH_TABLE_REG0_s
33332 {
33333  uint32_t ht31t0 : 32; /* First 32 bits of Hash Table */
33334 };
33335 
33336 /* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG0. */
33337 typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG0_s ALT_EMAC_GMAC_HASH_TABLE_REG0_t;
33338 #endif /* __ASSEMBLY__ */
33339 
33340 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG0 register. */
33341 #define ALT_EMAC_GMAC_HASH_TABLE_REG0_RESET 0x00000000
33342 /* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG0 register from the beginning of the component. */
33343 #define ALT_EMAC_GMAC_HASH_TABLE_REG0_OFST 0x500
33344 /* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG0 register. */
33345 #define ALT_EMAC_GMAC_HASH_TABLE_REG0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG0_OFST))
33346 
33347 /*
33348  * Register : Register 321 (Hash Table Register 1) - gmacgrp_hash_table_reg1
33349  *
33350  * This register contains the second 32 bits of the hash table.
33351  *
33352  * Register Layout
33353  *
33354  * Bits | Access | Reset | Description
33355  * :-------|:-------|:------|:-----------------------------
33356  * [31:0] | RW | 0x0 | Second 32 bits of Hash Table
33357  *
33358  */
33359 /*
33360  * Field : Second 32 bits of Hash Table - ht63t32
33361  *
33362  * This field contains the second 32 Bits (63:32) of the Hash table.
33363  *
33364  * Field Access Macros:
33365  *
33366  */
33367 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field. */
33368 #define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_LSB 0
33369 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field. */
33370 #define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_MSB 31
33371 /* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field. */
33372 #define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_WIDTH 32
33373 /* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field value. */
33374 #define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_SET_MSK 0xffffffff
33375 /* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field value. */
33376 #define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_CLR_MSK 0x00000000
33377 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field. */
33378 #define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_RESET 0x0
33379 /* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 field value from a register. */
33380 #define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_GET(value) (((value) & 0xffffffff) >> 0)
33381 /* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field value suitable for setting the register. */
33382 #define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_SET(value) (((value) << 0) & 0xffffffff)
33383 
33384 #ifndef __ASSEMBLY__
33385 /*
33386  * WARNING: The C register and register group struct declarations are provided for
33387  * convenience and illustrative purposes. They should, however, be used with
33388  * caution as the C language standard provides no guarantees about the alignment or
33389  * atomicity of device memory accesses. The recommended practice for writing
33390  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33391  * alt_write_word() functions.
33392  *
33393  * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG1.
33394  */
33395 struct ALT_EMAC_GMAC_HASH_TABLE_REG1_s
33396 {
33397  uint32_t ht63t32 : 32; /* Second 32 bits of Hash Table */
33398 };
33399 
33400 /* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG1. */
33401 typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG1_s ALT_EMAC_GMAC_HASH_TABLE_REG1_t;
33402 #endif /* __ASSEMBLY__ */
33403 
33404 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG1 register. */
33405 #define ALT_EMAC_GMAC_HASH_TABLE_REG1_RESET 0x00000000
33406 /* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG1 register from the beginning of the component. */
33407 #define ALT_EMAC_GMAC_HASH_TABLE_REG1_OFST 0x504
33408 /* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG1 register. */
33409 #define ALT_EMAC_GMAC_HASH_TABLE_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG1_OFST))
33410 
33411 /*
33412  * Register : Register 322 (Hash Table Register 2) - gmacgrp_hash_table_reg2
33413  *
33414  * This register contains the third 32 bits of the hash table.
33415  *
33416  * Register Layout
33417  *
33418  * Bits | Access | Reset | Description
33419  * :-------|:-------|:------|:----------------------------
33420  * [31:0] | RW | 0x0 | Third 32 bits of Hash Table
33421  *
33422  */
33423 /*
33424  * Field : Third 32 bits of Hash Table - ht95t64
33425  *
33426  * This field contains the third 32 Bits (95:64) of the Hash table.
33427  *
33428  * Field Access Macros:
33429  *
33430  */
33431 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field. */
33432 #define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_LSB 0
33433 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field. */
33434 #define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_MSB 31
33435 /* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field. */
33436 #define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_WIDTH 32
33437 /* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field value. */
33438 #define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_SET_MSK 0xffffffff
33439 /* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field value. */
33440 #define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_CLR_MSK 0x00000000
33441 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field. */
33442 #define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_RESET 0x0
33443 /* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 field value from a register. */
33444 #define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_GET(value) (((value) & 0xffffffff) >> 0)
33445 /* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field value suitable for setting the register. */
33446 #define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_SET(value) (((value) << 0) & 0xffffffff)
33447 
33448 #ifndef __ASSEMBLY__
33449 /*
33450  * WARNING: The C register and register group struct declarations are provided for
33451  * convenience and illustrative purposes. They should, however, be used with
33452  * caution as the C language standard provides no guarantees about the alignment or
33453  * atomicity of device memory accesses. The recommended practice for writing
33454  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33455  * alt_write_word() functions.
33456  *
33457  * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG2.
33458  */
33459 struct ALT_EMAC_GMAC_HASH_TABLE_REG2_s
33460 {
33461  uint32_t ht95t64 : 32; /* Third 32 bits of Hash Table */
33462 };
33463 
33464 /* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG2. */
33465 typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG2_s ALT_EMAC_GMAC_HASH_TABLE_REG2_t;
33466 #endif /* __ASSEMBLY__ */
33467 
33468 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG2 register. */
33469 #define ALT_EMAC_GMAC_HASH_TABLE_REG2_RESET 0x00000000
33470 /* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG2 register from the beginning of the component. */
33471 #define ALT_EMAC_GMAC_HASH_TABLE_REG2_OFST 0x508
33472 /* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG2 register. */
33473 #define ALT_EMAC_GMAC_HASH_TABLE_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG2_OFST))
33474 
33475 /*
33476  * Register : Register 323 (Hash Table Register 3) - gmacgrp_hash_table_reg3
33477  *
33478  * This register contains the fourth 32 bits of the hash table.
33479  *
33480  * Register Layout
33481  *
33482  * Bits | Access | Reset | Description
33483  * :-------|:-------|:------|:-----------------------------
33484  * [31:0] | RW | 0x0 | Fourth 32 bits of Hash Table
33485  *
33486  */
33487 /*
33488  * Field : Fourth 32 bits of Hash Table - ht127t96
33489  *
33490  * This field contains the fourth 32 Bits (127:96) of the Hash table.
33491  *
33492  * Field Access Macros:
33493  *
33494  */
33495 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field. */
33496 #define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_LSB 0
33497 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field. */
33498 #define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_MSB 31
33499 /* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field. */
33500 #define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_WIDTH 32
33501 /* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field value. */
33502 #define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_SET_MSK 0xffffffff
33503 /* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field value. */
33504 #define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_CLR_MSK 0x00000000
33505 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field. */
33506 #define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_RESET 0x0
33507 /* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 field value from a register. */
33508 #define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_GET(value) (((value) & 0xffffffff) >> 0)
33509 /* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field value suitable for setting the register. */
33510 #define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_SET(value) (((value) << 0) & 0xffffffff)
33511 
33512 #ifndef __ASSEMBLY__
33513 /*
33514  * WARNING: The C register and register group struct declarations are provided for
33515  * convenience and illustrative purposes. They should, however, be used with
33516  * caution as the C language standard provides no guarantees about the alignment or
33517  * atomicity of device memory accesses. The recommended practice for writing
33518  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33519  * alt_write_word() functions.
33520  *
33521  * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG3.
33522  */
33523 struct ALT_EMAC_GMAC_HASH_TABLE_REG3_s
33524 {
33525  uint32_t ht127t96 : 32; /* Fourth 32 bits of Hash Table */
33526 };
33527 
33528 /* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG3. */
33529 typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG3_s ALT_EMAC_GMAC_HASH_TABLE_REG3_t;
33530 #endif /* __ASSEMBLY__ */
33531 
33532 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG3 register. */
33533 #define ALT_EMAC_GMAC_HASH_TABLE_REG3_RESET 0x00000000
33534 /* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG3 register from the beginning of the component. */
33535 #define ALT_EMAC_GMAC_HASH_TABLE_REG3_OFST 0x50c
33536 /* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG3 register. */
33537 #define ALT_EMAC_GMAC_HASH_TABLE_REG3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG3_OFST))
33538 
33539 /*
33540  * Register : Register 324 (Hash Table Register 4) - gmacgrp_hash_table_reg4
33541  *
33542  * This register contains the fifth 32 bits of the hash table.
33543  *
33544  * Register Layout
33545  *
33546  * Bits | Access | Reset | Description
33547  * :-------|:-------|:------|:----------------------------
33548  * [31:0] | RW | 0x0 | Fifth 32 bits of Hash Table
33549  *
33550  */
33551 /*
33552  * Field : Fifth 32 bits of Hash Table - ht159t128
33553  *
33554  * This field contains the fifth 32 Bits (159:128) of the Hash table.
33555  *
33556  * Field Access Macros:
33557  *
33558  */
33559 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field. */
33560 #define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_LSB 0
33561 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field. */
33562 #define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_MSB 31
33563 /* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field. */
33564 #define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_WIDTH 32
33565 /* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field value. */
33566 #define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_SET_MSK 0xffffffff
33567 /* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field value. */
33568 #define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_CLR_MSK 0x00000000
33569 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field. */
33570 #define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_RESET 0x0
33571 /* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 field value from a register. */
33572 #define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_GET(value) (((value) & 0xffffffff) >> 0)
33573 /* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field value suitable for setting the register. */
33574 #define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_SET(value) (((value) << 0) & 0xffffffff)
33575 
33576 #ifndef __ASSEMBLY__
33577 /*
33578  * WARNING: The C register and register group struct declarations are provided for
33579  * convenience and illustrative purposes. They should, however, be used with
33580  * caution as the C language standard provides no guarantees about the alignment or
33581  * atomicity of device memory accesses. The recommended practice for writing
33582  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33583  * alt_write_word() functions.
33584  *
33585  * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG4.
33586  */
33587 struct ALT_EMAC_GMAC_HASH_TABLE_REG4_s
33588 {
33589  uint32_t ht159t128 : 32; /* Fifth 32 bits of Hash Table */
33590 };
33591 
33592 /* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG4. */
33593 typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG4_s ALT_EMAC_GMAC_HASH_TABLE_REG4_t;
33594 #endif /* __ASSEMBLY__ */
33595 
33596 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG4 register. */
33597 #define ALT_EMAC_GMAC_HASH_TABLE_REG4_RESET 0x00000000
33598 /* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG4 register from the beginning of the component. */
33599 #define ALT_EMAC_GMAC_HASH_TABLE_REG4_OFST 0x510
33600 /* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG4 register. */
33601 #define ALT_EMAC_GMAC_HASH_TABLE_REG4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG4_OFST))
33602 
33603 /*
33604  * Register : Register 325 (Hash Table Register 5) - gmacgrp_hash_table_reg5
33605  *
33606  * This register contains the sixth 32 bits of the hash table.
33607  *
33608  * Register Layout
33609  *
33610  * Bits | Access | Reset | Description
33611  * :-------|:-------|:------|:----------------------------
33612  * [31:0] | RW | 0x0 | Sixth 32 bits of Hash Table
33613  *
33614  */
33615 /*
33616  * Field : Sixth 32 bits of Hash Table - ht191t160
33617  *
33618  * This field contains the sixth 32 Bits (191:160) of the Hash table.
33619  *
33620  * Field Access Macros:
33621  *
33622  */
33623 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field. */
33624 #define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_LSB 0
33625 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field. */
33626 #define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_MSB 31
33627 /* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field. */
33628 #define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_WIDTH 32
33629 /* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field value. */
33630 #define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_SET_MSK 0xffffffff
33631 /* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field value. */
33632 #define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_CLR_MSK 0x00000000
33633 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field. */
33634 #define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_RESET 0x0
33635 /* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 field value from a register. */
33636 #define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_GET(value) (((value) & 0xffffffff) >> 0)
33637 /* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field value suitable for setting the register. */
33638 #define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_SET(value) (((value) << 0) & 0xffffffff)
33639 
33640 #ifndef __ASSEMBLY__
33641 /*
33642  * WARNING: The C register and register group struct declarations are provided for
33643  * convenience and illustrative purposes. They should, however, be used with
33644  * caution as the C language standard provides no guarantees about the alignment or
33645  * atomicity of device memory accesses. The recommended practice for writing
33646  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33647  * alt_write_word() functions.
33648  *
33649  * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG5.
33650  */
33651 struct ALT_EMAC_GMAC_HASH_TABLE_REG5_s
33652 {
33653  uint32_t ht191t160 : 32; /* Sixth 32 bits of Hash Table */
33654 };
33655 
33656 /* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG5. */
33657 typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG5_s ALT_EMAC_GMAC_HASH_TABLE_REG5_t;
33658 #endif /* __ASSEMBLY__ */
33659 
33660 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG5 register. */
33661 #define ALT_EMAC_GMAC_HASH_TABLE_REG5_RESET 0x00000000
33662 /* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG5 register from the beginning of the component. */
33663 #define ALT_EMAC_GMAC_HASH_TABLE_REG5_OFST 0x514
33664 /* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG5 register. */
33665 #define ALT_EMAC_GMAC_HASH_TABLE_REG5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG5_OFST))
33666 
33667 /*
33668  * Register : Register 326 (Hash Table Register 6) - gmacgrp_hash_table_reg6
33669  *
33670  * This register contains the seventh 32 bits of the hash table.
33671  *
33672  * Register Layout
33673  *
33674  * Bits | Access | Reset | Description
33675  * :-------|:-------|:------|:------------------------------
33676  * [31:0] | RW | 0x0 | Seventh 32 bits of Hash Table
33677  *
33678  */
33679 /*
33680  * Field : Seventh 32 bits of Hash Table - ht223t196
33681  *
33682  * This field contains the seventh 32 Bits (223:196) of the Hash table.
33683  *
33684  * Field Access Macros:
33685  *
33686  */
33687 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field. */
33688 #define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_LSB 0
33689 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field. */
33690 #define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_MSB 31
33691 /* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field. */
33692 #define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_WIDTH 32
33693 /* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field value. */
33694 #define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_SET_MSK 0xffffffff
33695 /* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field value. */
33696 #define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_CLR_MSK 0x00000000
33697 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field. */
33698 #define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_RESET 0x0
33699 /* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 field value from a register. */
33700 #define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_GET(value) (((value) & 0xffffffff) >> 0)
33701 /* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field value suitable for setting the register. */
33702 #define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_SET(value) (((value) << 0) & 0xffffffff)
33703 
33704 #ifndef __ASSEMBLY__
33705 /*
33706  * WARNING: The C register and register group struct declarations are provided for
33707  * convenience and illustrative purposes. They should, however, be used with
33708  * caution as the C language standard provides no guarantees about the alignment or
33709  * atomicity of device memory accesses. The recommended practice for writing
33710  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33711  * alt_write_word() functions.
33712  *
33713  * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG6.
33714  */
33715 struct ALT_EMAC_GMAC_HASH_TABLE_REG6_s
33716 {
33717  uint32_t ht223t196 : 32; /* Seventh 32 bits of Hash Table */
33718 };
33719 
33720 /* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG6. */
33721 typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG6_s ALT_EMAC_GMAC_HASH_TABLE_REG6_t;
33722 #endif /* __ASSEMBLY__ */
33723 
33724 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG6 register. */
33725 #define ALT_EMAC_GMAC_HASH_TABLE_REG6_RESET 0x00000000
33726 /* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG6 register from the beginning of the component. */
33727 #define ALT_EMAC_GMAC_HASH_TABLE_REG6_OFST 0x518
33728 /* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG6 register. */
33729 #define ALT_EMAC_GMAC_HASH_TABLE_REG6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG6_OFST))
33730 
33731 /*
33732  * Register : Register 327 (Hash Table Register 7) - gmacgrp_hash_table_reg7
33733  *
33734  * This register contains the eighth 32 bits of the hash table.
33735  *
33736  * Register Layout
33737  *
33738  * Bits | Access | Reset | Description
33739  * :-------|:-------|:------|:-----------------------------
33740  * [31:0] | RW | 0x0 | Eighth 32 bits of Hash Table
33741  *
33742  */
33743 /*
33744  * Field : Eighth 32 bits of Hash Table - ht255t224
33745  *
33746  * This field contains the eighth 32 Bits (255:224) of the Hash table.
33747  *
33748  * Field Access Macros:
33749  *
33750  */
33751 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field. */
33752 #define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_LSB 0
33753 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field. */
33754 #define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_MSB 31
33755 /* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field. */
33756 #define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_WIDTH 32
33757 /* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field value. */
33758 #define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_SET_MSK 0xffffffff
33759 /* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field value. */
33760 #define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_CLR_MSK 0x00000000
33761 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field. */
33762 #define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_RESET 0x0
33763 /* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 field value from a register. */
33764 #define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_GET(value) (((value) & 0xffffffff) >> 0)
33765 /* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field value suitable for setting the register. */
33766 #define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_SET(value) (((value) << 0) & 0xffffffff)
33767 
33768 #ifndef __ASSEMBLY__
33769 /*
33770  * WARNING: The C register and register group struct declarations are provided for
33771  * convenience and illustrative purposes. They should, however, be used with
33772  * caution as the C language standard provides no guarantees about the alignment or
33773  * atomicity of device memory accesses. The recommended practice for writing
33774  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33775  * alt_write_word() functions.
33776  *
33777  * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG7.
33778  */
33779 struct ALT_EMAC_GMAC_HASH_TABLE_REG7_s
33780 {
33781  uint32_t ht255t224 : 32; /* Eighth 32 bits of Hash Table */
33782 };
33783 
33784 /* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG7. */
33785 typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG7_s ALT_EMAC_GMAC_HASH_TABLE_REG7_t;
33786 #endif /* __ASSEMBLY__ */
33787 
33788 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG7 register. */
33789 #define ALT_EMAC_GMAC_HASH_TABLE_REG7_RESET 0x00000000
33790 /* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG7 register from the beginning of the component. */
33791 #define ALT_EMAC_GMAC_HASH_TABLE_REG7_OFST 0x51c
33792 /* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG7 register. */
33793 #define ALT_EMAC_GMAC_HASH_TABLE_REG7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG7_OFST))
33794 
33795 /*
33796  * Register : gmacgrp_vlan_incl_reg
33797  *
33798  * <b> Register 353 (VLAN Tag Inclusion or Replacement Register) </b>
33799  *
33800  * The VLAN Tag Inclusion or Replacement register contains the VLAN tag for
33801  * insertion or replacement in the transmit frames. This register is present only
33802  * when the Enable SA, VLAN, and CRC Insertion on TX option is selected during core
33803  * configuration.
33804  *
33805  * Register Layout
33806  *
33807  * Bits | Access | Reset | Description
33808  * :--------|:-------|:--------|:---------------------------------------
33809  * [15:0] | RW | Unknown | ALT_EMAC_GMAC_VLAN_INCL_REG_VLT
33810  * [17:16] | RW | Unknown | ALT_EMAC_GMAC_VLAN_INCL_REG_VLC
33811  * [18] | RW | Unknown | ALT_EMAC_GMAC_VLAN_INCL_REG_VLP
33812  * [19] | RW | Unknown | ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL
33813  * [31:20] | R | Unknown | ALT_EMAC_GMAC_VLAN_INCL_REG_RSVD_31_20
33814  *
33815  */
33816 /*
33817  * Field : vlt
33818  *
33819  * VLAN Tag for Transmit Frames
33820  *
33821  * This field contains the value of the VLAN tag to be inserted or replaced. The
33822  * value must only be changed when the transmit lines are inactive or during the
33823  * initialization phase. Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI,
33824  * and Bits[11:0] are the VLAN tag's VID field.
33825  *
33826  * Field Access Macros:
33827  *
33828  */
33829 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field. */
33830 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_LSB 0
33831 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field. */
33832 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_MSB 15
33833 /* The width in bits of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field. */
33834 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_WIDTH 16
33835 /* The mask used to set the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field value. */
33836 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_SET_MSK 0x0000ffff
33837 /* The mask used to clear the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field value. */
33838 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_CLR_MSK 0xffff0000
33839 /* The reset value of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field is UNKNOWN. */
33840 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_RESET 0x0
33841 /* Extracts the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT field value from a register. */
33842 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_GET(value) (((value) & 0x0000ffff) >> 0)
33843 /* Produces a ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field value suitable for setting the register. */
33844 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_SET(value) (((value) << 0) & 0x0000ffff)
33845 
33846 /*
33847  * Field : vlc
33848  *
33849  * VLAN Tag Control in Transmit Frames
33850  *
33851  * * 2'b00: No VLAN tag deletion, insertion, or replacement
33852  *
33853  * * 2'b01: VLAN tag deletion
33854  *
33855  * The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16)
33856  * of all transmitted frames with VLAN tags.
33857  *
33858  * * 2'b10: VLAN tag insertion
33859  *
33860  * The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type
33861  * value (0x8100/0x88a8) in bytes 13 and 14. This operation is performed on all
33862  * transmitted frames, irrespective of whether they already have a VLAN tag.
33863  *
33864  * * 2'b11: VLAN tag replacement
33865  *
33866  * The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames
33867  * (Bytes 13 and 14 are 0x8100/0x88a8).
33868  *
33869  * Note: Changes to this field take effect only on the start of a frame. If you
33870  * write this register field when a frame is being transmitted, only the subsequent
33871  * frame can use the updated value, that is, the current frame does not use the
33872  * updated value.
33873  *
33874  * Field Access Macros:
33875  *
33876  */
33877 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field. */
33878 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_LSB 16
33879 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field. */
33880 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_MSB 17
33881 /* The width in bits of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field. */
33882 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_WIDTH 2
33883 /* The mask used to set the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field value. */
33884 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_SET_MSK 0x00030000
33885 /* The mask used to clear the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field value. */
33886 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_CLR_MSK 0xfffcffff
33887 /* The reset value of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field is UNKNOWN. */
33888 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_RESET 0x0
33889 /* Extracts the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC field value from a register. */
33890 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_GET(value) (((value) & 0x00030000) >> 16)
33891 /* Produces a ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field value suitable for setting the register. */
33892 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_SET(value) (((value) << 16) & 0x00030000)
33893 
33894 /*
33895  * Field : vlp
33896  *
33897  * VLAN Priority Control
33898  *
33899  * When this bit is set, the control Bits [17:16] are used for VLAN deletion,
33900  * insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control
33901  * input is used, and Bits [17:16] are ignored.
33902  *
33903  * Field Access Macros:
33904  *
33905  */
33906 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field. */
33907 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_LSB 18
33908 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field. */
33909 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_MSB 18
33910 /* The width in bits of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field. */
33911 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_WIDTH 1
33912 /* The mask used to set the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field value. */
33913 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_SET_MSK 0x00040000
33914 /* The mask used to clear the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field value. */
33915 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_CLR_MSK 0xfffbffff
33916 /* The reset value of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field is UNKNOWN. */
33917 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_RESET 0x0
33918 /* Extracts the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP field value from a register. */
33919 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_GET(value) (((value) & 0x00040000) >> 18)
33920 /* Produces a ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field value suitable for setting the register. */
33921 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_SET(value) (((value) << 18) & 0x00040000)
33922 
33923 /*
33924  * Field : csvl
33925  *
33926  * C-VLAN or S-VLAN
33927  *
33928  * When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th
33929  * and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type
33930  * (0x8100) is inserted or replaced in the transmitted frames.
33931  *
33932  * Field Access Macros:
33933  *
33934  */
33935 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field. */
33936 #define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_LSB 19
33937 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field. */
33938 #define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_MSB 19
33939 /* The width in bits of the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field. */
33940 #define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_WIDTH 1
33941 /* The mask used to set the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field value. */
33942 #define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_SET_MSK 0x00080000
33943 /* The mask used to clear the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field value. */
33944 #define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_CLR_MSK 0xfff7ffff
33945 /* The reset value of the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field is UNKNOWN. */
33946 #define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_RESET 0x0
33947 /* Extracts the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL field value from a register. */
33948 #define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_GET(value) (((value) & 0x00080000) >> 19)
33949 /* Produces a ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field value suitable for setting the register. */
33950 #define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_SET(value) (((value) << 19) & 0x00080000)
33951 
33952 /*
33953  * Field : reserved_31_20
33954  *
33955  * Reserved
33956  *
33957  * Field Access Macros:
33958  *
33959  */
33960 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_RSVD_31_20 register field. */
33961 #define ALT_EMAC_GMAC_VLAN_INCL_REG_RSVD_31_20_LSB 20
33962 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_RSVD_31_20 register field. */
33963 #define ALT_EMAC_GMAC_VLAN_INCL_REG_RSVD_31_20_MSB 31
33964 /* The width in bits of the ALT_EMAC_GMAC_VLAN_INCL_REG_RSVD_31_20 register field. */
33965 #define ALT_EMAC_GMAC_VLAN_INCL_REG_RSVD_31_20_WIDTH 12
33966 /* The mask used to set the ALT_EMAC_GMAC_VLAN_INCL_REG_RSVD_31_20 register field value. */
33967 #define ALT_EMAC_GMAC_VLAN_INCL_REG_RSVD_31_20_SET_MSK 0xfff00000
33968 /* The mask used to clear the ALT_EMAC_GMAC_VLAN_INCL_REG_RSVD_31_20 register field value. */
33969 #define ALT_EMAC_GMAC_VLAN_INCL_REG_RSVD_31_20_CLR_MSK 0x000fffff
33970 /* The reset value of the ALT_EMAC_GMAC_VLAN_INCL_REG_RSVD_31_20 register field is UNKNOWN. */
33971 #define ALT_EMAC_GMAC_VLAN_INCL_REG_RSVD_31_20_RESET 0x0
33972 /* Extracts the ALT_EMAC_GMAC_VLAN_INCL_REG_RSVD_31_20 field value from a register. */
33973 #define ALT_EMAC_GMAC_VLAN_INCL_REG_RSVD_31_20_GET(value) (((value) & 0xfff00000) >> 20)
33974 /* Produces a ALT_EMAC_GMAC_VLAN_INCL_REG_RSVD_31_20 register field value suitable for setting the register. */
33975 #define ALT_EMAC_GMAC_VLAN_INCL_REG_RSVD_31_20_SET(value) (((value) << 20) & 0xfff00000)
33976 
33977 #ifndef __ASSEMBLY__
33978 /*
33979  * WARNING: The C register and register group struct declarations are provided for
33980  * convenience and illustrative purposes. They should, however, be used with
33981  * caution as the C language standard provides no guarantees about the alignment or
33982  * atomicity of device memory accesses. The recommended practice for writing
33983  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33984  * alt_write_word() functions.
33985  *
33986  * The struct declaration for register ALT_EMAC_GMAC_VLAN_INCL_REG.
33987  */
33988 struct ALT_EMAC_GMAC_VLAN_INCL_REG_s
33989 {
33990  uint32_t vlt : 16; /* ALT_EMAC_GMAC_VLAN_INCL_REG_VLT */
33991  uint32_t vlc : 2; /* ALT_EMAC_GMAC_VLAN_INCL_REG_VLC */
33992  uint32_t vlp : 1; /* ALT_EMAC_GMAC_VLAN_INCL_REG_VLP */
33993  uint32_t csvl : 1; /* ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL */
33994  const uint32_t reserved_31_20 : 12; /* ALT_EMAC_GMAC_VLAN_INCL_REG_RSVD_31_20 */
33995 };
33996 
33997 /* The typedef declaration for register ALT_EMAC_GMAC_VLAN_INCL_REG. */
33998 typedef volatile struct ALT_EMAC_GMAC_VLAN_INCL_REG_s ALT_EMAC_GMAC_VLAN_INCL_REG_t;
33999 #endif /* __ASSEMBLY__ */
34000 
34001 /* The reset value of the ALT_EMAC_GMAC_VLAN_INCL_REG register. */
34002 #define ALT_EMAC_GMAC_VLAN_INCL_REG_RESET 0x00000000
34003 /* The byte offset of the ALT_EMAC_GMAC_VLAN_INCL_REG register from the beginning of the component. */
34004 #define ALT_EMAC_GMAC_VLAN_INCL_REG_OFST 0x584
34005 /* The address of the ALT_EMAC_GMAC_VLAN_INCL_REG register. */
34006 #define ALT_EMAC_GMAC_VLAN_INCL_REG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_VLAN_INCL_REG_OFST))
34007 
34008 /*
34009  * Register : Register 354 (VLAN Hash Table Register) - gmacgrp_vlan_hash_table_reg
34010  *
34011  * The 16-bit Hash table is used for group address filtering based on VLAN tag when
34012  * Bit 18 (VTHM) of Register 7 (VLAN Tag Register) is set. For hash filtering, the
34013  * content of the 16-bit VLAN tag or 12-bit VLAN ID (based on Bit 16 (ETV) of VLAN
34014  * Tag Register) in the incoming frame is passed through the CRC logic and the
34015  * upper four bits of the calculated CRC are used to index the contents of the VLAN
34016  * Hash table. For example, a hash value of 4b'1000 selects Bit 8 of the VLAN Hash
34017  * table.
34018  *
34019  * The hash value of the destination address is calculated in the following way:
34020  *
34021  * 1. Calculate the 32-bit CRC for the VLAN tag or ID (See IEEE 802.3, Section
34022  * 3.2.8 for the steps to calculate CRC32).
34023  *
34024  * 2. Perform bitwise reversal for the value obtained in Step 1.
34025  *
34026  * 3. Take the upper four bits from the value obtained in Step 2.
34027  *
34028  * If the corresponding bit value of the register is 1'b1, the frame is accepted.
34029  * Otherwise, it is rejected. Because the Hash Table register is double-
34030  * synchronized to the (G)MII clock domain, the synchronization is triggered only
34031  * when Bits[15:8] (in little-endian mode) or Bits[7:0] (in big-endian mode) of
34032  * this register are written.
34033  *
34034  * Notes:
34035  *
34036  * * Because of double-synchronization, consecutive writes to this register should
34037  * be performed after at least four clock cycles in the destination clock domain.
34038  *
34039  * Register Layout
34040  *
34041  * Bits | Access | Reset | Description
34042  * :--------|:-------|:------|:----------------
34043  * [15:0] | RW | 0x0 | VLAN Hash Table
34044  * [31:16] | ??? | 0x0 | *UNDEFINED*
34045  *
34046  */
34047 /*
34048  * Field : VLAN Hash Table - vlht
34049  *
34050  * This field contains the 16-bit VLAN Hash Table.
34051  *
34052  * Field Access Macros:
34053  *
34054  */
34055 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field. */
34056 #define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_LSB 0
34057 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field. */
34058 #define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_MSB 15
34059 /* The width in bits of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field. */
34060 #define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_WIDTH 16
34061 /* The mask used to set the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field value. */
34062 #define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_SET_MSK 0x0000ffff
34063 /* The mask used to clear the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field value. */
34064 #define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_CLR_MSK 0xffff0000
34065 /* The reset value of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field. */
34066 #define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_RESET 0x0
34067 /* Extracts the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT field value from a register. */
34068 #define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_GET(value) (((value) & 0x0000ffff) >> 0)
34069 /* Produces a ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field value suitable for setting the register. */
34070 #define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_SET(value) (((value) << 0) & 0x0000ffff)
34071 
34072 #ifndef __ASSEMBLY__
34073 /*
34074  * WARNING: The C register and register group struct declarations are provided for
34075  * convenience and illustrative purposes. They should, however, be used with
34076  * caution as the C language standard provides no guarantees about the alignment or
34077  * atomicity of device memory accesses. The recommended practice for writing
34078  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
34079  * alt_write_word() functions.
34080  *
34081  * The struct declaration for register ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG.
34082  */
34083 struct ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_s
34084 {
34085  uint32_t vlht : 16; /* VLAN Hash Table */
34086  uint32_t : 16; /* *UNDEFINED* */
34087 };
34088 
34089 /* The typedef declaration for register ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG. */
34090 typedef volatile struct ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_s ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_t;
34091 #endif /* __ASSEMBLY__ */
34092 
34093 /* The reset value of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG register. */
34094 #define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_RESET 0x00000000
34095 /* The byte offset of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG register from the beginning of the component. */
34096 #define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_OFST 0x588
34097 /* The address of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG register. */
34098 #define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_OFST))
34099 
34100 /*
34101  * Register : gmacgrp_timestamp_control
34102  *
34103  * <b> Register 448 (Timestamp Control Register) </b>
34104  *
34105  * This register controls the operation of the System Time generator and the
34106  * processing of PTP packets for timestamping in the Receiver.
34107  *
34108  * Note:
34109  *
34110  * * Bits[5:1] are reserved when External Timestamp Input feature is enabled.
34111  *
34112  * * Bits[19:8] are reserved and read-only when Advanced Timestamp feature is not
34113  * enabled.
34114  *
34115  * * Bits[28:24] are reserved and read-only when Auxiliary Snapshot feature is not
34116  * enabled.
34117  *
34118  * * Release 3.60a onwards, the functions of Bits 17 and 16 (SNAPTYPSEL) have
34119  * changed. These functions are not backward compatible with the functions
34120  * described in release 3.50a.
34121  *
34122  * Register Layout
34123  *
34124  * Bits | Access | Reset | Description
34125  * :--------|:-------|:------|:---------------------------------
34126  * [0] | RW | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSENA
34127  * [1] | R | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSCFUPDT
34128  * [2] | R | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSINIT
34129  * [3] | R | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSUPDT
34130  * [4] | R | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSTRIG
34131  * [5] | R | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSADDREG
34132  * [7:6] | R | 0x0 | ALT_EMAC_GMAC_TS_CTL_RSVD_7_6
34133  * [8] | RW | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSENALL
34134  * [9] | RW | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSCTLSSR
34135  * [10] | RW | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSVER2ENA
34136  * [11] | RW | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSIPENA
34137  * [12] | RW | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA
34138  * [13] | RW | 0x1 | ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA
34139  * [14] | RW | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSEVNTENA
34140  * [15] | RW | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSMSTRENA
34141  * [17:16] | RW | 0x0 | ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL
34142  * [18] | RW | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSENMACADDR
34143  * [23:19] | R | 0x0 | ALT_EMAC_GMAC_TS_CTL_RSVD_23_19
34144  * [24] | R | 0x0 | ALT_EMAC_GMAC_TS_CTL_ATSFC
34145  * [25] | R | 0x0 | ALT_EMAC_GMAC_TS_CTL_ATSEN0
34146  * [26] | R | 0x0 | ALT_EMAC_GMAC_TS_CTL_ATSEN1
34147  * [27] | R | 0x0 | ALT_EMAC_GMAC_TS_CTL_ATSEN2
34148  * [28] | R | 0x0 | ALT_EMAC_GMAC_TS_CTL_ATSEN3
34149  * [31:29] | R | 0x0 | ALT_EMAC_GMAC_TS_CTL_RSVD_31_29
34150  *
34151  */
34152 /*
34153  * Field : tsena
34154  *
34155  * Timestamp Enable
34156  *
34157  * When set, the timestamp is added for the transmit and receive frames. When
34158  * disabled, timestamp is not added for the transmit and receive frames and the
34159  * Timestamp Generator is also suspended. You need to initialize the Timestamp
34160  * (system time) after enabling this mode.
34161  *
34162  * On the receive side, the MAC processes the 1588 frames only if this bit is set.
34163  *
34164  * Field Enumeration Values:
34165  *
34166  * Enum | Value | Description
34167  * :----------------------------------|:------|:------------
34168  * ALT_EMAC_GMAC_TS_CTL_TSENA_E_NOTS | 0x0 |
34169  * ALT_EMAC_GMAC_TS_CTL_TSENA_E_TS | 0x1 |
34170  *
34171  * Field Access Macros:
34172  *
34173  */
34174 /*
34175  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENA
34176  *
34177  */
34178 #define ALT_EMAC_GMAC_TS_CTL_TSENA_E_NOTS 0x0
34179 /*
34180  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENA
34181  *
34182  */
34183 #define ALT_EMAC_GMAC_TS_CTL_TSENA_E_TS 0x1
34184 
34185 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENA register field. */
34186 #define ALT_EMAC_GMAC_TS_CTL_TSENA_LSB 0
34187 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENA register field. */
34188 #define ALT_EMAC_GMAC_TS_CTL_TSENA_MSB 0
34189 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSENA register field. */
34190 #define ALT_EMAC_GMAC_TS_CTL_TSENA_WIDTH 1
34191 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSENA register field value. */
34192 #define ALT_EMAC_GMAC_TS_CTL_TSENA_SET_MSK 0x00000001
34193 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSENA register field value. */
34194 #define ALT_EMAC_GMAC_TS_CTL_TSENA_CLR_MSK 0xfffffffe
34195 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSENA register field. */
34196 #define ALT_EMAC_GMAC_TS_CTL_TSENA_RESET 0x0
34197 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSENA field value from a register. */
34198 #define ALT_EMAC_GMAC_TS_CTL_TSENA_GET(value) (((value) & 0x00000001) >> 0)
34199 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSENA register field value suitable for setting the register. */
34200 #define ALT_EMAC_GMAC_TS_CTL_TSENA_SET(value) (((value) << 0) & 0x00000001)
34201 
34202 /*
34203  * Field : tscfupdt
34204  *
34205  * Timestamp Fine or Coarse Update
34206  *
34207  * When set, this bit indicates that the system times update should be done using
34208  * the fine update method. When reset, it indicates the system timestamp update
34209  * should be done using the Coarse method.
34210  *
34211  * Field Enumeration Values:
34212  *
34213  * Enum | Value | Description
34214  * :------------------------------------------|:------|:------------
34215  * ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_COARSE | 0x0 |
34216  * ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_FINE | 0x1 |
34217  *
34218  * Field Access Macros:
34219  *
34220  */
34221 /*
34222  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCFUPDT
34223  *
34224  */
34225 #define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_COARSE 0x0
34226 /*
34227  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCFUPDT
34228  *
34229  */
34230 #define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_FINE 0x1
34231 
34232 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field. */
34233 #define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_LSB 1
34234 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field. */
34235 #define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_MSB 1
34236 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field. */
34237 #define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_WIDTH 1
34238 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field value. */
34239 #define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_SET_MSK 0x00000002
34240 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field value. */
34241 #define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_CLR_MSK 0xfffffffd
34242 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field. */
34243 #define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_RESET 0x0
34244 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT field value from a register. */
34245 #define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_GET(value) (((value) & 0x00000002) >> 1)
34246 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field value suitable for setting the register. */
34247 #define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_SET(value) (((value) << 1) & 0x00000002)
34248 
34249 /*
34250  * Field : tsinit
34251  *
34252  * Timestamp Initialize
34253  *
34254  * When set, the system time is initialized (overwritten) with the value specified
34255  * in the Register 452 (System Time - Seconds Update Register) and Register 453
34256  * (System Time - Nanoseconds Update Register).
34257  *
34258  * This bit should be read zero before updating it. This bit is reset when the
34259  * initialization is complete. The Timestamp Higher Word register (if enabled
34260  * during core configuration) can only be initialized.
34261  *
34262  * Field Enumeration Values:
34263  *
34264  * Enum | Value | Description
34265  * :----------------------------------------|:------|:------------
34266  * ALT_EMAC_GMAC_TS_CTL_TSINIT_E_NOTS_INIT | 0x0 |
34267  * ALT_EMAC_GMAC_TS_CTL_TSINIT_E_TS_INIT | 0x1 |
34268  *
34269  * Field Access Macros:
34270  *
34271  */
34272 /*
34273  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSINIT
34274  *
34275  */
34276 #define ALT_EMAC_GMAC_TS_CTL_TSINIT_E_NOTS_INIT 0x0
34277 /*
34278  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSINIT
34279  *
34280  */
34281 #define ALT_EMAC_GMAC_TS_CTL_TSINIT_E_TS_INIT 0x1
34282 
34283 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field. */
34284 #define ALT_EMAC_GMAC_TS_CTL_TSINIT_LSB 2
34285 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field. */
34286 #define ALT_EMAC_GMAC_TS_CTL_TSINIT_MSB 2
34287 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field. */
34288 #define ALT_EMAC_GMAC_TS_CTL_TSINIT_WIDTH 1
34289 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSINIT register field value. */
34290 #define ALT_EMAC_GMAC_TS_CTL_TSINIT_SET_MSK 0x00000004
34291 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSINIT register field value. */
34292 #define ALT_EMAC_GMAC_TS_CTL_TSINIT_CLR_MSK 0xfffffffb
34293 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field. */
34294 #define ALT_EMAC_GMAC_TS_CTL_TSINIT_RESET 0x0
34295 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSINIT field value from a register. */
34296 #define ALT_EMAC_GMAC_TS_CTL_TSINIT_GET(value) (((value) & 0x00000004) >> 2)
34297 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSINIT register field value suitable for setting the register. */
34298 #define ALT_EMAC_GMAC_TS_CTL_TSINIT_SET(value) (((value) << 2) & 0x00000004)
34299 
34300 /*
34301  * Field : tsupdt
34302  *
34303  * Timestamp Update
34304  *
34305  * When set, the system time is updated (added or subtracted) with the value
34306  * specified in Register 452 (System Time - Seconds Update Register) and Register
34307  * 453 (System Time - Nanoseconds Update Register).
34308  *
34309  * This bit should be read zero before updating it. This bit is reset when the
34310  * update is completed in hardware. The Timestamp Higher Word register (if enabled
34311  * during core configuration) is not updated.
34312  *
34313  * Field Enumeration Values:
34314  *
34315  * Enum | Value | Description
34316  * :-------------------------------------------|:------|:------------
34317  * ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_NOTS_UPDATED | 0x0 |
34318  * ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_TS_UPDATED | 0x1 |
34319  *
34320  * Field Access Macros:
34321  *
34322  */
34323 /*
34324  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSUPDT
34325  *
34326  */
34327 #define ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_NOTS_UPDATED 0x0
34328 /*
34329  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSUPDT
34330  *
34331  */
34332 #define ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_TS_UPDATED 0x1
34333 
34334 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field. */
34335 #define ALT_EMAC_GMAC_TS_CTL_TSUPDT_LSB 3
34336 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field. */
34337 #define ALT_EMAC_GMAC_TS_CTL_TSUPDT_MSB 3
34338 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field. */
34339 #define ALT_EMAC_GMAC_TS_CTL_TSUPDT_WIDTH 1
34340 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field value. */
34341 #define ALT_EMAC_GMAC_TS_CTL_TSUPDT_SET_MSK 0x00000008
34342 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field value. */
34343 #define ALT_EMAC_GMAC_TS_CTL_TSUPDT_CLR_MSK 0xfffffff7
34344 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field. */
34345 #define ALT_EMAC_GMAC_TS_CTL_TSUPDT_RESET 0x0
34346 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSUPDT field value from a register. */
34347 #define ALT_EMAC_GMAC_TS_CTL_TSUPDT_GET(value) (((value) & 0x00000008) >> 3)
34348 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSUPDT register field value suitable for setting the register. */
34349 #define ALT_EMAC_GMAC_TS_CTL_TSUPDT_SET(value) (((value) << 3) & 0x00000008)
34350 
34351 /*
34352  * Field : tstrig
34353  *
34354  * Timestamp Interrupt Trigger Enable
34355  *
34356  * When set, the timestamp interrupt is generated when the System Time becomes
34357  * greater than the value written in the Target Time register. This bit is reset
34358  * after the generation of the Timestamp Trigger Interrupt.
34359  *
34360  * Field Enumeration Values:
34361  *
34362  * Enum | Value | Description
34363  * :------------------------------------------------|:------|:------------
34364  * ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_NOTS_INTR_TRIG_EN | 0x0 |
34365  * ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_TS_INTR_TRIG_EN | 0x1 |
34366  *
34367  * Field Access Macros:
34368  *
34369  */
34370 /*
34371  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSTRIG
34372  *
34373  */
34374 #define ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_NOTS_INTR_TRIG_EN 0x0
34375 /*
34376  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSTRIG
34377  *
34378  */
34379 #define ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_TS_INTR_TRIG_EN 0x1
34380 
34381 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field. */
34382 #define ALT_EMAC_GMAC_TS_CTL_TSTRIG_LSB 4
34383 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field. */
34384 #define ALT_EMAC_GMAC_TS_CTL_TSTRIG_MSB 4
34385 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field. */
34386 #define ALT_EMAC_GMAC_TS_CTL_TSTRIG_WIDTH 1
34387 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field value. */
34388 #define ALT_EMAC_GMAC_TS_CTL_TSTRIG_SET_MSK 0x00000010
34389 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field value. */
34390 #define ALT_EMAC_GMAC_TS_CTL_TSTRIG_CLR_MSK 0xffffffef
34391 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field. */
34392 #define ALT_EMAC_GMAC_TS_CTL_TSTRIG_RESET 0x0
34393 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSTRIG field value from a register. */
34394 #define ALT_EMAC_GMAC_TS_CTL_TSTRIG_GET(value) (((value) & 0x00000010) >> 4)
34395 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSTRIG register field value suitable for setting the register. */
34396 #define ALT_EMAC_GMAC_TS_CTL_TSTRIG_SET(value) (((value) << 4) & 0x00000010)
34397 
34398 /*
34399  * Field : tsaddreg
34400  *
34401  * Addend Reg Update
34402  *
34403  * When set, the content of the Timestamp Addend register is updated in the PTP
34404  * block for fine correction. This is cleared when the update is completed. This
34405  * register bit should be zero before setting it.
34406  *
34407  * Field Enumeration Values:
34408  *
34409  * Enum | Value | Description
34410  * :----------------------------------------------------|:------|:------------
34411  * ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_NOTS_ADDEND_UPDATED | 0x0 |
34412  * ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_TS_ADDEND_UPDATED | 0x1 |
34413  *
34414  * Field Access Macros:
34415  *
34416  */
34417 /*
34418  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSADDREG
34419  *
34420  */
34421 #define ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_NOTS_ADDEND_UPDATED 0x0
34422 /*
34423  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSADDREG
34424  *
34425  */
34426 #define ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_TS_ADDEND_UPDATED 0x1
34427 
34428 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field. */
34429 #define ALT_EMAC_GMAC_TS_CTL_TSADDREG_LSB 5
34430 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field. */
34431 #define ALT_EMAC_GMAC_TS_CTL_TSADDREG_MSB 5
34432 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field. */
34433 #define ALT_EMAC_GMAC_TS_CTL_TSADDREG_WIDTH 1
34434 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field value. */
34435 #define ALT_EMAC_GMAC_TS_CTL_TSADDREG_SET_MSK 0x00000020
34436 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field value. */
34437 #define ALT_EMAC_GMAC_TS_CTL_TSADDREG_CLR_MSK 0xffffffdf
34438 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field. */
34439 #define ALT_EMAC_GMAC_TS_CTL_TSADDREG_RESET 0x0
34440 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSADDREG field value from a register. */
34441 #define ALT_EMAC_GMAC_TS_CTL_TSADDREG_GET(value) (((value) & 0x00000020) >> 5)
34442 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSADDREG register field value suitable for setting the register. */
34443 #define ALT_EMAC_GMAC_TS_CTL_TSADDREG_SET(value) (((value) << 5) & 0x00000020)
34444 
34445 /*
34446  * Field : reserved_7_6
34447  *
34448  * Reserved
34449  *
34450  * Field Access Macros:
34451  *
34452  */
34453 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_RSVD_7_6 register field. */
34454 #define ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_LSB 6
34455 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_RSVD_7_6 register field. */
34456 #define ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_MSB 7
34457 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_RSVD_7_6 register field. */
34458 #define ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_WIDTH 2
34459 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_RSVD_7_6 register field value. */
34460 #define ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_SET_MSK 0x000000c0
34461 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_RSVD_7_6 register field value. */
34462 #define ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_CLR_MSK 0xffffff3f
34463 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_RSVD_7_6 register field. */
34464 #define ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_RESET 0x0
34465 /* Extracts the ALT_EMAC_GMAC_TS_CTL_RSVD_7_6 field value from a register. */
34466 #define ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_GET(value) (((value) & 0x000000c0) >> 6)
34467 /* Produces a ALT_EMAC_GMAC_TS_CTL_RSVD_7_6 register field value suitable for setting the register. */
34468 #define ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_SET(value) (((value) << 6) & 0x000000c0)
34469 
34470 /*
34471  * Field : tsenall
34472  *
34473  * Enable Timestamp for All Frames
34474  *
34475  * When set, the timestamp snapshot is enabled for all frames received by the MAC.
34476  *
34477  * Field Enumeration Values:
34478  *
34479  * Enum | Value | Description
34480  * :------------------------------------|:------|:------------
34481  * ALT_EMAC_GMAC_TS_CTL_TSENALL_E_DISD | 0x0 |
34482  * ALT_EMAC_GMAC_TS_CTL_TSENALL_E_END | 0x1 |
34483  *
34484  * Field Access Macros:
34485  *
34486  */
34487 /*
34488  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENALL
34489  *
34490  */
34491 #define ALT_EMAC_GMAC_TS_CTL_TSENALL_E_DISD 0x0
34492 /*
34493  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENALL
34494  *
34495  */
34496 #define ALT_EMAC_GMAC_TS_CTL_TSENALL_E_END 0x1
34497 
34498 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field. */
34499 #define ALT_EMAC_GMAC_TS_CTL_TSENALL_LSB 8
34500 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field. */
34501 #define ALT_EMAC_GMAC_TS_CTL_TSENALL_MSB 8
34502 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field. */
34503 #define ALT_EMAC_GMAC_TS_CTL_TSENALL_WIDTH 1
34504 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSENALL register field value. */
34505 #define ALT_EMAC_GMAC_TS_CTL_TSENALL_SET_MSK 0x00000100
34506 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSENALL register field value. */
34507 #define ALT_EMAC_GMAC_TS_CTL_TSENALL_CLR_MSK 0xfffffeff
34508 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field. */
34509 #define ALT_EMAC_GMAC_TS_CTL_TSENALL_RESET 0x0
34510 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSENALL field value from a register. */
34511 #define ALT_EMAC_GMAC_TS_CTL_TSENALL_GET(value) (((value) & 0x00000100) >> 8)
34512 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSENALL register field value suitable for setting the register. */
34513 #define ALT_EMAC_GMAC_TS_CTL_TSENALL_SET(value) (((value) << 8) & 0x00000100)
34514 
34515 /*
34516  * Field : tsctrlssr
34517  *
34518  * Timestamp Digital or Binary Rollover Control
34519  *
34520  * When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that
34521  * is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When
34522  * reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second
34523  * increment has to be programmed correctly depending on the PTP reference clock
34524  * frequency and the value of this bit.
34525  *
34526  * Field Enumeration Values:
34527  *
34528  * Enum | Value | Description
34529  * :--------------------------------------------------|:------|:------------
34530  * ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_NOTS_LOW_ROLL_MAX | 0x0 |
34531  * ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_TS_LOW_ROLL_1NS | 0x1 |
34532  *
34533  * Field Access Macros:
34534  *
34535  */
34536 /*
34537  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCTLSSR
34538  *
34539  */
34540 #define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_NOTS_LOW_ROLL_MAX 0x0
34541 /*
34542  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCTLSSR
34543  *
34544  */
34545 #define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_TS_LOW_ROLL_1NS 0x1
34546 
34547 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field. */
34548 #define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_LSB 9
34549 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field. */
34550 #define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_MSB 9
34551 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field. */
34552 #define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_WIDTH 1
34553 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field value. */
34554 #define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_SET_MSK 0x00000200
34555 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field value. */
34556 #define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_CLR_MSK 0xfffffdff
34557 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field. */
34558 #define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_RESET 0x0
34559 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR field value from a register. */
34560 #define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_GET(value) (((value) & 0x00000200) >> 9)
34561 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field value suitable for setting the register. */
34562 #define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_SET(value) (((value) << 9) & 0x00000200)
34563 
34564 /*
34565  * Field : tsver2ena
34566  *
34567  * Enable PTP packet Processing for Version 2 Format
34568  *
34569  * When set, the PTP packets are processed using the 1588 version 2 format.
34570  * Otherwise, the PTP packets are processed using the version 1 format.
34571  *
34572  * Field Enumeration Values:
34573  *
34574  * Enum | Value | Description
34575  * :-----------------------------------------------|:------|:------------
34576  * ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER1 | 0x0 |
34577  * ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER2 | 0x1 |
34578  *
34579  * Field Access Macros:
34580  *
34581  */
34582 /*
34583  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSVER2ENA
34584  *
34585  */
34586 #define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER1 0x0
34587 /*
34588  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSVER2ENA
34589  *
34590  */
34591 #define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER2 0x1
34592 
34593 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field. */
34594 #define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_LSB 10
34595 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field. */
34596 #define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_MSB 10
34597 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field. */
34598 #define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_WIDTH 1
34599 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field value. */
34600 #define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_SET_MSK 0x00000400
34601 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field value. */
34602 #define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_CLR_MSK 0xfffffbff
34603 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field. */
34604 #define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_RESET 0x0
34605 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA field value from a register. */
34606 #define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_GET(value) (((value) & 0x00000400) >> 10)
34607 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field value suitable for setting the register. */
34608 #define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_SET(value) (((value) << 10) & 0x00000400)
34609 
34610 /*
34611  * Field : tsipena
34612  *
34613  * Enable Processing of PTP over Ethernet Frames
34614  *
34615  * When set, the MAC receiver processes the PTP packets encapsulated directly in
34616  * the Ethernet frames. When this bit is clear, the MAC ignores the PTP over
34617  * Ethernet packets.
34618  *
34619  * Field Enumeration Values:
34620  *
34621  * Enum | Value | Description
34622  * :----------------------------------------------|:------|:------------
34623  * ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_NO_PROCESS_PTP | 0x0 |
34624  * ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_PROCESS_PTP | 0x1 |
34625  *
34626  * Field Access Macros:
34627  *
34628  */
34629 /*
34630  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPENA
34631  *
34632  */
34633 #define ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_NO_PROCESS_PTP 0x0
34634 /*
34635  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPENA
34636  *
34637  */
34638 #define ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_PROCESS_PTP 0x1
34639 
34640 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field. */
34641 #define ALT_EMAC_GMAC_TS_CTL_TSIPENA_LSB 11
34642 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field. */
34643 #define ALT_EMAC_GMAC_TS_CTL_TSIPENA_MSB 11
34644 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field. */
34645 #define ALT_EMAC_GMAC_TS_CTL_TSIPENA_WIDTH 1
34646 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field value. */
34647 #define ALT_EMAC_GMAC_TS_CTL_TSIPENA_SET_MSK 0x00000800
34648 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field value. */
34649 #define ALT_EMAC_GMAC_TS_CTL_TSIPENA_CLR_MSK 0xfffff7ff
34650 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field. */
34651 #define ALT_EMAC_GMAC_TS_CTL_TSIPENA_RESET 0x0
34652 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSIPENA field value from a register. */
34653 #define ALT_EMAC_GMAC_TS_CTL_TSIPENA_GET(value) (((value) & 0x00000800) >> 11)
34654 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSIPENA register field value suitable for setting the register. */
34655 #define ALT_EMAC_GMAC_TS_CTL_TSIPENA_SET(value) (((value) << 11) & 0x00000800)
34656 
34657 /*
34658  * Field : tsipv6ena
34659  *
34660  * Enable Processing of PTP Frames Sent Over IPv6-UDP
34661  *
34662  * When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6
34663  * packets. When this bit is clear, the MAC ignores the PTP transported over UDP-
34664  * IPv6 packets.
34665  *
34666  * Field Enumeration Values:
34667  *
34668  * Enum | Value | Description
34669  * :------------------------------------------------|:------|:------------
34670  * ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_NO_PROCESS_PTP | 0x0 |
34671  * ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_PROCESS_PTP | 0x1 |
34672  *
34673  * Field Access Macros:
34674  *
34675  */
34676 /*
34677  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA
34678  *
34679  */
34680 #define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_NO_PROCESS_PTP 0x0
34681 /*
34682  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA
34683  *
34684  */
34685 #define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_PROCESS_PTP 0x1
34686 
34687 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field. */
34688 #define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_LSB 12
34689 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field. */
34690 #define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_MSB 12
34691 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field. */
34692 #define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_WIDTH 1
34693 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field value. */
34694 #define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_SET_MSK 0x00001000
34695 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field value. */
34696 #define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_CLR_MSK 0xffffefff
34697 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field. */
34698 #define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_RESET 0x0
34699 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA field value from a register. */
34700 #define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_GET(value) (((value) & 0x00001000) >> 12)
34701 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field value suitable for setting the register. */
34702 #define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_SET(value) (((value) << 12) & 0x00001000)
34703 
34704 /*
34705  * Field : tsipv4ena
34706  *
34707  * Enable Processing of PTP Frames Sent over IPv4-UDP
34708  *
34709  * When set, the MAC receiver processes the PTP packets encapsulated in UDP over
34710  * IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over
34711  * UDP-IPv4 packets. This bit is set by default.
34712  *
34713  * Field Enumeration Values:
34714  *
34715  * Enum | Value | Description
34716  * :------------------------------------------------|:------|:------------
34717  * ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_NO_PROCESS_PTP | 0x0 |
34718  * ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_PROCESS_PTP | 0x1 |
34719  *
34720  * Field Access Macros:
34721  *
34722  */
34723 /*
34724  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA
34725  *
34726  */
34727 #define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_NO_PROCESS_PTP 0x0
34728 /*
34729  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA
34730  *
34731  */
34732 #define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_PROCESS_PTP 0x1
34733 
34734 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field. */
34735 #define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_LSB 13
34736 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field. */
34737 #define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_MSB 13
34738 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field. */
34739 #define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_WIDTH 1
34740 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field value. */
34741 #define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_SET_MSK 0x00002000
34742 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field value. */
34743 #define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_CLR_MSK 0xffffdfff
34744 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field. */
34745 #define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_RESET 0x1
34746 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA field value from a register. */
34747 #define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_GET(value) (((value) & 0x00002000) >> 13)
34748 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field value suitable for setting the register. */
34749 #define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_SET(value) (((value) << 13) & 0x00002000)
34750 
34751 /*
34752  * Field : tsevntena
34753  *
34754  * Enable Timestamp Snapshot for Event Messages
34755  *
34756  * When set, the timestamp snapshot is taken only for event messages (SYNC,
34757  * Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for
34758  * all messages except Announce, Management, and Signaling.
34759  *
34760  * Field Enumeration Values:
34761  *
34762  * Enum | Value | Description
34763  * :--------------------------------------|:------|:------------
34764  * ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_DISD | 0x0 |
34765  * ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_END | 0x1 |
34766  *
34767  * Field Access Macros:
34768  *
34769  */
34770 /*
34771  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSEVNTENA
34772  *
34773  */
34774 #define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_DISD 0x0
34775 /*
34776  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSEVNTENA
34777  *
34778  */
34779 #define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_END 0x1
34780 
34781 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field. */
34782 #define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_LSB 14
34783 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field. */
34784 #define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_MSB 14
34785 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field. */
34786 #define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_WIDTH 1
34787 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field value. */
34788 #define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_SET_MSK 0x00004000
34789 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field value. */
34790 #define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_CLR_MSK 0xffffbfff
34791 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field. */
34792 #define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_RESET 0x0
34793 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA field value from a register. */
34794 #define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_GET(value) (((value) & 0x00004000) >> 14)
34795 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field value suitable for setting the register. */
34796 #define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_SET(value) (((value) << 14) & 0x00004000)
34797 
34798 /*
34799  * Field : tsmstrena
34800  *
34801  * Enable Snapshot for Messages Relevant to Master
34802  *
34803  * When set, the snapshot is taken only for the messages relevant to the master
34804  * node. Otherwise, the snapshot is taken for the messages relevant to the slave
34805  * node.
34806  *
34807  * Field Enumeration Values:
34808  *
34809  * Enum | Value | Description
34810  * :-------------------------------------|:------|:------------
34811  * ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_SLV | 0x0 |
34812  * ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_MST | 0x1 |
34813  *
34814  * Field Access Macros:
34815  *
34816  */
34817 /*
34818  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSMSTRENA
34819  *
34820  */
34821 #define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_SLV 0x0
34822 /*
34823  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSMSTRENA
34824  *
34825  */
34826 #define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_MST 0x1
34827 
34828 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field. */
34829 #define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_LSB 15
34830 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field. */
34831 #define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_MSB 15
34832 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field. */
34833 #define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_WIDTH 1
34834 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field value. */
34835 #define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_SET_MSK 0x00008000
34836 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field value. */
34837 #define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_CLR_MSK 0xffff7fff
34838 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field. */
34839 #define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_RESET 0x0
34840 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA field value from a register. */
34841 #define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_GET(value) (((value) & 0x00008000) >> 15)
34842 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field value suitable for setting the register. */
34843 #define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_SET(value) (((value) << 15) & 0x00008000)
34844 
34845 /*
34846  * Field : snaptypsel
34847  *
34848  * Select PTP packets for Taking Snapshots
34849  *
34850  * These bits along with Bits 15 and 14 decide the set of PTP packet types for
34851  * which snapshot needs to be taken.
34852  *
34853  * Field Access Macros:
34854  *
34855  */
34856 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field. */
34857 #define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_LSB 16
34858 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field. */
34859 #define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_MSB 17
34860 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field. */
34861 #define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_WIDTH 2
34862 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field value. */
34863 #define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_SET_MSK 0x00030000
34864 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field value. */
34865 #define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_CLR_MSK 0xfffcffff
34866 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field. */
34867 #define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_RESET 0x0
34868 /* Extracts the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL field value from a register. */
34869 #define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_GET(value) (((value) & 0x00030000) >> 16)
34870 /* Produces a ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field value suitable for setting the register. */
34871 #define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_SET(value) (((value) << 16) & 0x00030000)
34872 
34873 /*
34874  * Field : tsenmacaddr
34875  *
34876  * Enable MAC address for PTP Frame Filtering
34877  *
34878  * When set, the DA MAC address (that matches any MAC Address register) is used to
34879  * filter the PTP frames when PTP is directly sent over Ethernet.
34880  *
34881  * Field Enumeration Values:
34882  *
34883  * Enum | Value | Description
34884  * :----------------------------------------|:------|:------------
34885  * ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_DISD | 0x0 |
34886  * ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_END | 0x1 |
34887  *
34888  * Field Access Macros:
34889  *
34890  */
34891 /*
34892  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENMACADDR
34893  *
34894  */
34895 #define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_DISD 0x0
34896 /*
34897  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENMACADDR
34898  *
34899  */
34900 #define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_END 0x1
34901 
34902 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field. */
34903 #define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_LSB 18
34904 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field. */
34905 #define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_MSB 18
34906 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field. */
34907 #define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_WIDTH 1
34908 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field value. */
34909 #define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_SET_MSK 0x00040000
34910 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field value. */
34911 #define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_CLR_MSK 0xfffbffff
34912 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field. */
34913 #define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_RESET 0x0
34914 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR field value from a register. */
34915 #define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_GET(value) (((value) & 0x00040000) >> 18)
34916 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field value suitable for setting the register. */
34917 #define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_SET(value) (((value) << 18) & 0x00040000)
34918 
34919 /*
34920  * Field : reserved_23_19
34921  *
34922  * Reserved
34923  *
34924  * Field Access Macros:
34925  *
34926  */
34927 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_RSVD_23_19 register field. */
34928 #define ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_LSB 19
34929 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_RSVD_23_19 register field. */
34930 #define ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_MSB 23
34931 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_RSVD_23_19 register field. */
34932 #define ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_WIDTH 5
34933 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_RSVD_23_19 register field value. */
34934 #define ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_SET_MSK 0x00f80000
34935 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_RSVD_23_19 register field value. */
34936 #define ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_CLR_MSK 0xff07ffff
34937 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_RSVD_23_19 register field. */
34938 #define ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_RESET 0x0
34939 /* Extracts the ALT_EMAC_GMAC_TS_CTL_RSVD_23_19 field value from a register. */
34940 #define ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_GET(value) (((value) & 0x00f80000) >> 19)
34941 /* Produces a ALT_EMAC_GMAC_TS_CTL_RSVD_23_19 register field value suitable for setting the register. */
34942 #define ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_SET(value) (((value) << 19) & 0x00f80000)
34943 
34944 /*
34945  * Field : atsfc
34946  *
34947  * Auxiliary Snapshot FIFO Clear
34948  *
34949  * When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is
34950  * cleared when the pointers are reset and the FIFO is empty. When this bit is
34951  * high, auxiliary snapshots get stored in the FIFO. This bit is reserved when the
34952  * Add IEEE 1588 Auxiliary Snapshot option is not selected during core
34953  * configuration.
34954  *
34955  * Field Enumeration Values:
34956  *
34957  * Enum | Value | Description
34958  * :----------------------------------|:------|:------------
34959  * ALT_EMAC_GMAC_TS_CTL_ATSFC_E_DISD | 0x0 |
34960  * ALT_EMAC_GMAC_TS_CTL_ATSFC_E_END | 0x1 |
34961  *
34962  * Field Access Macros:
34963  *
34964  */
34965 /*
34966  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSFC
34967  *
34968  */
34969 #define ALT_EMAC_GMAC_TS_CTL_ATSFC_E_DISD 0x0
34970 /*
34971  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSFC
34972  *
34973  */
34974 #define ALT_EMAC_GMAC_TS_CTL_ATSFC_E_END 0x1
34975 
34976 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field. */
34977 #define ALT_EMAC_GMAC_TS_CTL_ATSFC_LSB 24
34978 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field. */
34979 #define ALT_EMAC_GMAC_TS_CTL_ATSFC_MSB 24
34980 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field. */
34981 #define ALT_EMAC_GMAC_TS_CTL_ATSFC_WIDTH 1
34982 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_ATSFC register field value. */
34983 #define ALT_EMAC_GMAC_TS_CTL_ATSFC_SET_MSK 0x01000000
34984 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_ATSFC register field value. */
34985 #define ALT_EMAC_GMAC_TS_CTL_ATSFC_CLR_MSK 0xfeffffff
34986 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field. */
34987 #define ALT_EMAC_GMAC_TS_CTL_ATSFC_RESET 0x0
34988 /* Extracts the ALT_EMAC_GMAC_TS_CTL_ATSFC field value from a register. */
34989 #define ALT_EMAC_GMAC_TS_CTL_ATSFC_GET(value) (((value) & 0x01000000) >> 24)
34990 /* Produces a ALT_EMAC_GMAC_TS_CTL_ATSFC register field value suitable for setting the register. */
34991 #define ALT_EMAC_GMAC_TS_CTL_ATSFC_SET(value) (((value) << 24) & 0x01000000)
34992 
34993 /*
34994  * Field : atsen0
34995  *
34996  * Auxiliary Snapshot 0 Enable
34997  *
34998  * This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is
34999  * set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When
35000  * this bit is reset, the events on this input are ignored.
35001  *
35002  * This bit is reserved when the <i>Add IEEE 1588 Auxiliary Snapshot</i> option is
35003  * not selected during core configuration.
35004  *
35005  * Field Enumeration Values:
35006  *
35007  * Enum | Value | Description
35008  * :-----------------------------------|:------|:------------
35009  * ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_DISD | 0x0 |
35010  * ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_END | 0x1 |
35011  *
35012  * Field Access Macros:
35013  *
35014  */
35015 /*
35016  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSEN0
35017  *
35018  */
35019 #define ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_DISD 0x0
35020 /*
35021  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSEN0
35022  *
35023  */
35024 #define ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_END 0x1
35025 
35026 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field. */
35027 #define ALT_EMAC_GMAC_TS_CTL_ATSEN0_LSB 25
35028 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field. */
35029 #define ALT_EMAC_GMAC_TS_CTL_ATSEN0_MSB 25
35030 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field. */
35031 #define ALT_EMAC_GMAC_TS_CTL_ATSEN0_WIDTH 1
35032 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field value. */
35033 #define ALT_EMAC_GMAC_TS_CTL_ATSEN0_SET_MSK 0x02000000
35034 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field value. */
35035 #define ALT_EMAC_GMAC_TS_CTL_ATSEN0_CLR_MSK 0xfdffffff
35036 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field. */
35037 #define ALT_EMAC_GMAC_TS_CTL_ATSEN0_RESET 0x0
35038 /* Extracts the ALT_EMAC_GMAC_TS_CTL_ATSEN0 field value from a register. */
35039 #define ALT_EMAC_GMAC_TS_CTL_ATSEN0_GET(value) (((value) & 0x02000000) >> 25)
35040 /* Produces a ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field value suitable for setting the register. */
35041 #define ALT_EMAC_GMAC_TS_CTL_ATSEN0_SET(value) (((value) << 25) & 0x02000000)
35042 
35043 /*
35044  * Field : atsen1
35045  *
35046  * Auxiliary Snapshot 1 Enable
35047  *
35048  * This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is
35049  * set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When
35050  * this bit is reset, the events on this input are ignored.
35051  *
35052  * This bit is reserved when the <i>Add IEEE 1588 Auxiliary Snapshot</i> option is
35053  * not selected during core configuration or the selected number in the <i>Number
35054  * of IEEE 1588 Auxiliary Snapshot Inputs</i> option is less than two.
35055  *
35056  * Field Access Macros:
35057  *
35058  */
35059 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN1 register field. */
35060 #define ALT_EMAC_GMAC_TS_CTL_ATSEN1_LSB 26
35061 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN1 register field. */
35062 #define ALT_EMAC_GMAC_TS_CTL_ATSEN1_MSB 26
35063 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_ATSEN1 register field. */
35064 #define ALT_EMAC_GMAC_TS_CTL_ATSEN1_WIDTH 1
35065 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_ATSEN1 register field value. */
35066 #define ALT_EMAC_GMAC_TS_CTL_ATSEN1_SET_MSK 0x04000000
35067 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_ATSEN1 register field value. */
35068 #define ALT_EMAC_GMAC_TS_CTL_ATSEN1_CLR_MSK 0xfbffffff
35069 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_ATSEN1 register field. */
35070 #define ALT_EMAC_GMAC_TS_CTL_ATSEN1_RESET 0x0
35071 /* Extracts the ALT_EMAC_GMAC_TS_CTL_ATSEN1 field value from a register. */
35072 #define ALT_EMAC_GMAC_TS_CTL_ATSEN1_GET(value) (((value) & 0x04000000) >> 26)
35073 /* Produces a ALT_EMAC_GMAC_TS_CTL_ATSEN1 register field value suitable for setting the register. */
35074 #define ALT_EMAC_GMAC_TS_CTL_ATSEN1_SET(value) (((value) << 26) & 0x04000000)
35075 
35076 /*
35077  * Field : atsen2
35078  *
35079  * Auxiliary Snapshot 2 Enable
35080  *
35081  * This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is
35082  * set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When
35083  * this bit is reset, the events on this input are ignored.
35084  *
35085  * This bit is reserved when the <i>Add IEEE 1588 Auxiliary Snapshot</i> option is
35086  * not selected during core configuration or the selected number in the <i>Number
35087  * of IEEE 1588 Auxiliary Snapshot Inputs</i> option is less than three.
35088  *
35089  * Field Access Macros:
35090  *
35091  */
35092 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN2 register field. */
35093 #define ALT_EMAC_GMAC_TS_CTL_ATSEN2_LSB 27
35094 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN2 register field. */
35095 #define ALT_EMAC_GMAC_TS_CTL_ATSEN2_MSB 27
35096 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_ATSEN2 register field. */
35097 #define ALT_EMAC_GMAC_TS_CTL_ATSEN2_WIDTH 1
35098 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_ATSEN2 register field value. */
35099 #define ALT_EMAC_GMAC_TS_CTL_ATSEN2_SET_MSK 0x08000000
35100 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_ATSEN2 register field value. */
35101 #define ALT_EMAC_GMAC_TS_CTL_ATSEN2_CLR_MSK 0xf7ffffff
35102 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_ATSEN2 register field. */
35103 #define ALT_EMAC_GMAC_TS_CTL_ATSEN2_RESET 0x0
35104 /* Extracts the ALT_EMAC_GMAC_TS_CTL_ATSEN2 field value from a register. */
35105 #define ALT_EMAC_GMAC_TS_CTL_ATSEN2_GET(value) (((value) & 0x08000000) >> 27)
35106 /* Produces a ALT_EMAC_GMAC_TS_CTL_ATSEN2 register field value suitable for setting the register. */
35107 #define ALT_EMAC_GMAC_TS_CTL_ATSEN2_SET(value) (((value) << 27) & 0x08000000)
35108 
35109 /*
35110  * Field : atsen3
35111  *
35112  * Auxiliary Snapshot 3 Enable
35113  *
35114  * This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is
35115  * set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When
35116  * this bit is reset, the events on this input are ignored.
35117  *
35118  * This bit is reserved when the <i>Add IEEE 1588 Auxiliary Snapshot</i> option is
35119  * not selected during core configuration or the selected number in the <i>Number
35120  * of IEEE 1588 Auxiliary Snapshot Inputs</i> option is less than four.
35121  *
35122  * Field Access Macros:
35123  *
35124  */
35125 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN3 register field. */
35126 #define ALT_EMAC_GMAC_TS_CTL_ATSEN3_LSB 28
35127 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN3 register field. */
35128 #define ALT_EMAC_GMAC_TS_CTL_ATSEN3_MSB 28
35129 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_ATSEN3 register field. */
35130 #define ALT_EMAC_GMAC_TS_CTL_ATSEN3_WIDTH 1
35131 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_ATSEN3 register field value. */
35132 #define ALT_EMAC_GMAC_TS_CTL_ATSEN3_SET_MSK 0x10000000
35133 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_ATSEN3 register field value. */
35134 #define ALT_EMAC_GMAC_TS_CTL_ATSEN3_CLR_MSK 0xefffffff
35135 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_ATSEN3 register field. */
35136 #define ALT_EMAC_GMAC_TS_CTL_ATSEN3_RESET 0x0
35137 /* Extracts the ALT_EMAC_GMAC_TS_CTL_ATSEN3 field value from a register. */
35138 #define ALT_EMAC_GMAC_TS_CTL_ATSEN3_GET(value) (((value) & 0x10000000) >> 28)
35139 /* Produces a ALT_EMAC_GMAC_TS_CTL_ATSEN3 register field value suitable for setting the register. */
35140 #define ALT_EMAC_GMAC_TS_CTL_ATSEN3_SET(value) (((value) << 28) & 0x10000000)
35141 
35142 /*
35143  * Field : reserved_31_29
35144  *
35145  * Reserved
35146  *
35147  * Field Access Macros:
35148  *
35149  */
35150 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_RSVD_31_29 register field. */
35151 #define ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_LSB 29
35152 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_RSVD_31_29 register field. */
35153 #define ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_MSB 31
35154 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_RSVD_31_29 register field. */
35155 #define ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_WIDTH 3
35156 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_RSVD_31_29 register field value. */
35157 #define ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_SET_MSK 0xe0000000
35158 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_RSVD_31_29 register field value. */
35159 #define ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_CLR_MSK 0x1fffffff
35160 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_RSVD_31_29 register field. */
35161 #define ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_RESET 0x0
35162 /* Extracts the ALT_EMAC_GMAC_TS_CTL_RSVD_31_29 field value from a register. */
35163 #define ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_GET(value) (((value) & 0xe0000000) >> 29)
35164 /* Produces a ALT_EMAC_GMAC_TS_CTL_RSVD_31_29 register field value suitable for setting the register. */
35165 #define ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_SET(value) (((value) << 29) & 0xe0000000)
35166 
35167 #ifndef __ASSEMBLY__
35168 /*
35169  * WARNING: The C register and register group struct declarations are provided for
35170  * convenience and illustrative purposes. They should, however, be used with
35171  * caution as the C language standard provides no guarantees about the alignment or
35172  * atomicity of device memory accesses. The recommended practice for writing
35173  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
35174  * alt_write_word() functions.
35175  *
35176  * The struct declaration for register ALT_EMAC_GMAC_TS_CTL.
35177  */
35178 struct ALT_EMAC_GMAC_TS_CTL_s
35179 {
35180  uint32_t tsena : 1; /* ALT_EMAC_GMAC_TS_CTL_TSENA */
35181  const uint32_t tscfupdt : 1; /* ALT_EMAC_GMAC_TS_CTL_TSCFUPDT */
35182  const uint32_t tsinit : 1; /* ALT_EMAC_GMAC_TS_CTL_TSINIT */
35183  const uint32_t tsupdt : 1; /* ALT_EMAC_GMAC_TS_CTL_TSUPDT */
35184  const uint32_t tstrig : 1; /* ALT_EMAC_GMAC_TS_CTL_TSTRIG */
35185  const uint32_t tsaddreg : 1; /* ALT_EMAC_GMAC_TS_CTL_TSADDREG */
35186  const uint32_t reserved_7_6 : 2; /* ALT_EMAC_GMAC_TS_CTL_RSVD_7_6 */
35187  uint32_t tsenall : 1; /* ALT_EMAC_GMAC_TS_CTL_TSENALL */
35188  uint32_t tsctrlssr : 1; /* ALT_EMAC_GMAC_TS_CTL_TSCTLSSR */
35189  uint32_t tsver2ena : 1; /* ALT_EMAC_GMAC_TS_CTL_TSVER2ENA */
35190  uint32_t tsipena : 1; /* ALT_EMAC_GMAC_TS_CTL_TSIPENA */
35191  uint32_t tsipv6ena : 1; /* ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA */
35192  uint32_t tsipv4ena : 1; /* ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA */
35193  uint32_t tsevntena : 1; /* ALT_EMAC_GMAC_TS_CTL_TSEVNTENA */
35194  uint32_t tsmstrena : 1; /* ALT_EMAC_GMAC_TS_CTL_TSMSTRENA */
35195  uint32_t snaptypsel : 2; /* ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL */
35196  uint32_t tsenmacaddr : 1; /* ALT_EMAC_GMAC_TS_CTL_TSENMACADDR */
35197  const uint32_t reserved_23_19 : 5; /* ALT_EMAC_GMAC_TS_CTL_RSVD_23_19 */
35198  const uint32_t atsfc : 1; /* ALT_EMAC_GMAC_TS_CTL_ATSFC */
35199  const uint32_t atsen0 : 1; /* ALT_EMAC_GMAC_TS_CTL_ATSEN0 */
35200  const uint32_t atsen1 : 1; /* ALT_EMAC_GMAC_TS_CTL_ATSEN1 */
35201  const uint32_t atsen2 : 1; /* ALT_EMAC_GMAC_TS_CTL_ATSEN2 */
35202  const uint32_t atsen3 : 1; /* ALT_EMAC_GMAC_TS_CTL_ATSEN3 */
35203  const uint32_t reserved_31_29 : 3; /* ALT_EMAC_GMAC_TS_CTL_RSVD_31_29 */
35204 };
35205 
35206 /* The typedef declaration for register ALT_EMAC_GMAC_TS_CTL. */
35207 typedef volatile struct ALT_EMAC_GMAC_TS_CTL_s ALT_EMAC_GMAC_TS_CTL_t;
35208 #endif /* __ASSEMBLY__ */
35209 
35210 /* The reset value of the ALT_EMAC_GMAC_TS_CTL register. */
35211 #define ALT_EMAC_GMAC_TS_CTL_RESET 0x00002000
35212 /* The byte offset of the ALT_EMAC_GMAC_TS_CTL register from the beginning of the component. */
35213 #define ALT_EMAC_GMAC_TS_CTL_OFST 0x700
35214 /* The address of the ALT_EMAC_GMAC_TS_CTL register. */
35215 #define ALT_EMAC_GMAC_TS_CTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TS_CTL_OFST))
35216 
35217 /*
35218  * Register : Register 449 (Sub-Second Increment Register) - gmacgrp_sub_second_increment
35219  *
35220  * In the Coarse Update mode (TSCFUPDT bit in Register 448), the value in this
35221  * register is added to the system time every clock cycle of clk_ptp_ref_i. In the
35222  * Fine Update mode, the value in this register is added to the system time
35223  * whenever the Accumulator gets an overflow.
35224  *
35225  * Register Layout
35226  *
35227  * Bits | Access | Reset | Description
35228  * :-------|:-------|:------|:---------------------------
35229  * [7:0] | RW | 0x0 | Sub-second Increment Value
35230  * [31:8] | ??? | 0x0 | *UNDEFINED*
35231  *
35232  */
35233 /*
35234  * Field : Sub-second Increment Value - ssinc
35235  *
35236  * The value programmed in this field is accumulated every clock cycle (of
35237  * clk_ptp_i) with the contents of the sub-second register. For example, when PTP
35238  * clock is 50 MHz (period is 20 ns), you should program 20 (0x14) when the System
35239  * Time-Nanoseconds register has an accuracy of 1 ns (TSCTRLSSR bit is set). When
35240  * TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. In
35241  * this case, you should program a value of 43 (0x2B) that is derived by
35242  * 20ns/0.465.
35243  *
35244  * Field Access Macros:
35245  *
35246  */
35247 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field. */
35248 #define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_LSB 0
35249 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field. */
35250 #define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_MSB 7
35251 /* The width in bits of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field. */
35252 #define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_WIDTH 8
35253 /* The mask used to set the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field value. */
35254 #define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_SET_MSK 0x000000ff
35255 /* The mask used to clear the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field value. */
35256 #define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_CLR_MSK 0xffffff00
35257 /* The reset value of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field. */
35258 #define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_RESET 0x0
35259 /* Extracts the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC field value from a register. */
35260 #define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_GET(value) (((value) & 0x000000ff) >> 0)
35261 /* Produces a ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field value suitable for setting the register. */
35262 #define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_SET(value) (((value) << 0) & 0x000000ff)
35263 
35264 #ifndef __ASSEMBLY__
35265 /*
35266  * WARNING: The C register and register group struct declarations are provided for
35267  * convenience and illustrative purposes. They should, however, be used with
35268  * caution as the C language standard provides no guarantees about the alignment or
35269  * atomicity of device memory accesses. The recommended practice for writing
35270  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
35271  * alt_write_word() functions.
35272  *
35273  * The struct declaration for register ALT_EMAC_GMAC_SUB_SEC_INCREMENT.
35274  */
35275 struct ALT_EMAC_GMAC_SUB_SEC_INCREMENT_s
35276 {
35277  uint32_t ssinc : 8; /* Sub-second Increment Value */
35278  uint32_t : 24; /* *UNDEFINED* */
35279 };
35280 
35281 /* The typedef declaration for register ALT_EMAC_GMAC_SUB_SEC_INCREMENT. */
35282 typedef volatile struct ALT_EMAC_GMAC_SUB_SEC_INCREMENT_s ALT_EMAC_GMAC_SUB_SEC_INCREMENT_t;
35283 #endif /* __ASSEMBLY__ */
35284 
35285 /* The reset value of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT register. */
35286 #define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_RESET 0x00000000
35287 /* The byte offset of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT register from the beginning of the component. */
35288 #define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_OFST 0x704
35289 /* The address of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT register. */
35290 #define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SUB_SEC_INCREMENT_OFST))
35291 
35292 /*
35293  * Register : Register 450 (System Time - Seconds Register) - gmacgrp_system_time_seconds
35294  *
35295  * The System Time -Seconds register, along with System-TimeNanoseconds register,
35296  * indicates the current value of the system time maintained by the MAC. Though it
35297  * is updated on a continuous basis, there is some delay from the actual time
35298  * because of clock domain transfer latencies (from clk_ptp_ref_i to l3_sp_clk).
35299  *
35300  * Register Layout
35301  *
35302  * Bits | Access | Reset | Description
35303  * :-------|:-------|:------|:-----------------
35304  * [31:0] | R | 0x0 | Timestamp Second
35305  *
35306  */
35307 /*
35308  * Field : Timestamp Second - tss
35309  *
35310  * The value in this field indicates the current value in seconds of the System
35311  * Time maintained by the MAC.
35312  *
35313  * Field Access Macros:
35314  *
35315  */
35316 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field. */
35317 #define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_LSB 0
35318 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field. */
35319 #define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_MSB 31
35320 /* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field. */
35321 #define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_WIDTH 32
35322 /* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field value. */
35323 #define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_SET_MSK 0xffffffff
35324 /* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field value. */
35325 #define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_CLR_MSK 0x00000000
35326 /* The reset value of the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field. */
35327 #define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_RESET 0x0
35328 /* Extracts the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS field value from a register. */
35329 #define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_GET(value) (((value) & 0xffffffff) >> 0)
35330 /* Produces a ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field value suitable for setting the register. */
35331 #define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_SET(value) (((value) << 0) & 0xffffffff)
35332 
35333 #ifndef __ASSEMBLY__
35334 /*
35335  * WARNING: The C register and register group struct declarations are provided for
35336  * convenience and illustrative purposes. They should, however, be used with
35337  * caution as the C language standard provides no guarantees about the alignment or
35338  * atomicity of device memory accesses. The recommended practice for writing
35339  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
35340  * alt_write_word() functions.
35341  *
35342  * The struct declaration for register ALT_EMAC_GMAC_SYS_TIME_SECS.
35343  */
35344 struct ALT_EMAC_GMAC_SYS_TIME_SECS_s
35345 {
35346  const uint32_t tss : 32; /* Timestamp Second */
35347 };
35348 
35349 /* The typedef declaration for register ALT_EMAC_GMAC_SYS_TIME_SECS. */
35350 typedef volatile struct ALT_EMAC_GMAC_SYS_TIME_SECS_s ALT_EMAC_GMAC_SYS_TIME_SECS_t;
35351 #endif /* __ASSEMBLY__ */
35352 
35353 /* The reset value of the ALT_EMAC_GMAC_SYS_TIME_SECS register. */
35354 #define ALT_EMAC_GMAC_SYS_TIME_SECS_RESET 0x00000000
35355 /* The byte offset of the ALT_EMAC_GMAC_SYS_TIME_SECS register from the beginning of the component. */
35356 #define ALT_EMAC_GMAC_SYS_TIME_SECS_OFST 0x708
35357 /* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS register. */
35358 #define ALT_EMAC_GMAC_SYS_TIME_SECS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SYS_TIME_SECS_OFST))
35359 
35360 /*
35361  * Register : Register 451 (System Time - Nanoseconds Register) - gmacgrp_system_time_nanoseconds
35362  *
35363  * The value in this field has the sub second representation of time, with an
35364  * accuracy of 0.46 ns. When TSCTRLSSR is set, each bit represents 1 ns and the
35365  * maximum value is 0x3B9A_C9FF, after which it rolls-over to zero.
35366  *
35367  * Register Layout
35368  *
35369  * Bits | Access | Reset | Description
35370  * :-------|:-------|:------|:----------------------
35371  * [30:0] | R | 0x0 | Timestamp Sub Seconds
35372  * [31] | ??? | 0x0 | *UNDEFINED*
35373  *
35374  */
35375 /*
35376  * Field : Timestamp Sub Seconds - tsss
35377  *
35378  * The value in this field has the sub second representation of time, with an
35379  * accuracy of 0.46 ns. When bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp
35380  * Control Register), each bit represents 1 ns and the maximum value is
35381  * 0x3B9A_C9FF, after which it rolls-over to zero.
35382  *
35383  * Field Access Macros:
35384  *
35385  */
35386 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field. */
35387 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_LSB 0
35388 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field. */
35389 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_MSB 30
35390 /* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field. */
35391 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_WIDTH 31
35392 /* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field value. */
35393 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_SET_MSK 0x7fffffff
35394 /* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field value. */
35395 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_CLR_MSK 0x80000000
35396 /* The reset value of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field. */
35397 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_RESET 0x0
35398 /* Extracts the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS field value from a register. */
35399 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_GET(value) (((value) & 0x7fffffff) >> 0)
35400 /* Produces a ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field value suitable for setting the register. */
35401 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_SET(value) (((value) << 0) & 0x7fffffff)
35402 
35403 #ifndef __ASSEMBLY__
35404 /*
35405  * WARNING: The C register and register group struct declarations are provided for
35406  * convenience and illustrative purposes. They should, however, be used with
35407  * caution as the C language standard provides no guarantees about the alignment or
35408  * atomicity of device memory accesses. The recommended practice for writing
35409  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
35410  * alt_write_word() functions.
35411  *
35412  * The struct declaration for register ALT_EMAC_GMAC_SYS_TIME_NANOSECS.
35413  */
35414 struct ALT_EMAC_GMAC_SYS_TIME_NANOSECS_s
35415 {
35416  const uint32_t tsss : 31; /* Timestamp Sub Seconds */
35417  uint32_t : 1; /* *UNDEFINED* */
35418 };
35419 
35420 /* The typedef declaration for register ALT_EMAC_GMAC_SYS_TIME_NANOSECS. */
35421 typedef volatile struct ALT_EMAC_GMAC_SYS_TIME_NANOSECS_s ALT_EMAC_GMAC_SYS_TIME_NANOSECS_t;
35422 #endif /* __ASSEMBLY__ */
35423 
35424 /* The reset value of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS register. */
35425 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_RESET 0x00000000
35426 /* The byte offset of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS register from the beginning of the component. */
35427 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_OFST 0x70c
35428 /* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS register. */
35429 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SYS_TIME_NANOSECS_OFST))
35430 
35431 /*
35432  * Register : Register 452 (System Time - Seconds Update Register) - gmacgrp_system_time_seconds_update
35433  *
35434  * The System Time - Seconds Update register, along with the System Time -
35435  * Nanoseconds Update register, initializes or updates the system time maintained
35436  * by the MAC. You must write both of these registers before setting the TSINIT or
35437  * TSUPDT bits in the Timestamp Control register.
35438  *
35439  * Register Layout
35440  *
35441  * Bits | Access | Reset | Description
35442  * :-------|:-------|:------|:-----------------
35443  * [31:0] | RW | 0x0 | Timestamp Second
35444  *
35445  */
35446 /*
35447  * Field : Timestamp Second - tss
35448  *
35449  * The value in this field indicates the time in seconds to be initialized or added
35450  * to the system time.
35451  *
35452  * Field Access Macros:
35453  *
35454  */
35455 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field. */
35456 #define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_LSB 0
35457 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field. */
35458 #define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_MSB 31
35459 /* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field. */
35460 #define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_WIDTH 32
35461 /* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field value. */
35462 #define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_SET_MSK 0xffffffff
35463 /* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field value. */
35464 #define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_CLR_MSK 0x00000000
35465 /* The reset value of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field. */
35466 #define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_RESET 0x0
35467 /* Extracts the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS field value from a register. */
35468 #define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_GET(value) (((value) & 0xffffffff) >> 0)
35469 /* Produces a ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field value suitable for setting the register. */
35470 #define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_SET(value) (((value) << 0) & 0xffffffff)
35471 
35472 #ifndef __ASSEMBLY__
35473 /*
35474  * WARNING: The C register and register group struct declarations are provided for
35475  * convenience and illustrative purposes. They should, however, be used with
35476  * caution as the C language standard provides no guarantees about the alignment or
35477  * atomicity of device memory accesses. The recommended practice for writing
35478  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
35479  * alt_write_word() functions.
35480  *
35481  * The struct declaration for register ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE.
35482  */
35483 struct ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_s
35484 {
35485  uint32_t tss : 32; /* Timestamp Second */
35486 };
35487 
35488 /* The typedef declaration for register ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE. */
35489 typedef volatile struct ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_s ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_t;
35490 #endif /* __ASSEMBLY__ */
35491 
35492 /* The reset value of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE register. */
35493 #define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_RESET 0x00000000
35494 /* The byte offset of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE register from the beginning of the component. */
35495 #define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_OFST 0x710
35496 /* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE register. */
35497 #define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_OFST))
35498 
35499 /*
35500  * Register : Register 453 (System Time - Nanoseconds Update Register) - gmacgrp_system_time_nanoseconds_update
35501  *
35502  * Update system time
35503  *
35504  * Register Layout
35505  *
35506  * Bits | Access | Reset | Description
35507  * :-------|:-------|:------|:---------------------
35508  * [30:0] | RW | 0x0 | Timestamp Sub Second
35509  * [31] | RW | 0x0 | Add or subtract time
35510  *
35511  */
35512 /*
35513  * Field : Timestamp Sub Second - tsss
35514  *
35515  * The value in this field has the sub second representation of time, with an
35516  * accuracy of 0.46 ns. When bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp
35517  * Control Register), each bit represents 1 ns and the programmed value should not
35518  * exceed 0x3B9A_C9FF.
35519  *
35520  * Field Access Macros:
35521  *
35522  */
35523 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field. */
35524 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_LSB 0
35525 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field. */
35526 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_MSB 30
35527 /* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field. */
35528 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_WIDTH 31
35529 /* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field value. */
35530 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_SET_MSK 0x7fffffff
35531 /* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field value. */
35532 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_CLR_MSK 0x80000000
35533 /* The reset value of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field. */
35534 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_RESET 0x0
35535 /* Extracts the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS field value from a register. */
35536 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_GET(value) (((value) & 0x7fffffff) >> 0)
35537 /* Produces a ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field value suitable for setting the register. */
35538 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_SET(value) (((value) << 0) & 0x7fffffff)
35539 
35540 /*
35541  * Field : Add or subtract time - addsub
35542  *
35543  * When this bit is set, the time value is subtracted with the contents of the
35544  * update register. When this bit is reset, the time value is added with the
35545  * contents of the update register.
35546  *
35547  * Field Enumeration Values:
35548  *
35549  * Enum | Value | Description
35550  * :-----------------------------------------------------|:------|:------------
35551  * ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_E_DISD | 0x0 |
35552  * ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_E_END | 0x1 |
35553  *
35554  * Field Access Macros:
35555  *
35556  */
35557 /*
35558  * Enumerated value for register field ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB
35559  *
35560  */
35561 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_E_DISD 0x0
35562 /*
35563  * Enumerated value for register field ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB
35564  *
35565  */
35566 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_E_END 0x1
35567 
35568 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field. */
35569 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_LSB 31
35570 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field. */
35571 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_MSB 31
35572 /* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field. */
35573 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_WIDTH 1
35574 /* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field value. */
35575 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_SET_MSK 0x80000000
35576 /* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field value. */
35577 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_CLR_MSK 0x7fffffff
35578 /* The reset value of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field. */
35579 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_RESET 0x0
35580 /* Extracts the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB field value from a register. */
35581 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_GET(value) (((value) & 0x80000000) >> 31)
35582 /* Produces a ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field value suitable for setting the register. */
35583 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_SET(value) (((value) << 31) & 0x80000000)
35584 
35585 #ifndef __ASSEMBLY__
35586 /*
35587  * WARNING: The C register and register group struct declarations are provided for
35588  * convenience and illustrative purposes. They should, however, be used with
35589  * caution as the C language standard provides no guarantees about the alignment or
35590  * atomicity of device memory accesses. The recommended practice for writing
35591  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
35592  * alt_write_word() functions.
35593  *
35594  * The struct declaration for register ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE.
35595  */
35596 struct ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_s
35597 {
35598  uint32_t tsss : 31; /* Timestamp Sub Second */
35599  uint32_t addsub : 1; /* Add or subtract time */
35600 };
35601 
35602 /* The typedef declaration for register ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE. */
35603 typedef volatile struct ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_s ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_t;
35604 #endif /* __ASSEMBLY__ */
35605 
35606 /* The reset value of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE register. */
35607 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_RESET 0x00000000
35608 /* The byte offset of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE register from the beginning of the component. */
35609 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_OFST 0x714
35610 /* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE register. */
35611 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_OFST))
35612 
35613 /*
35614  * Register : Register 454 (Timestamp Addend Register) - gmacgrp_timestamp_addend
35615  *
35616  * This register value is used only when the system time is configured for Fine
35617  * Update mode (TSCFUPDT bit in Register 448). This register content is added to a
35618  * 32-bit accumulator in every clock cycle (of clk_ptp_ref_i) and the system time
35619  * is updated whenever the accumulator overflows.
35620  *
35621  * Register Layout
35622  *
35623  * Bits | Access | Reset | Description
35624  * :-------|:-------|:------|:--------------------------
35625  * [31:0] | RW | 0x0 | Timestamp Addend Register
35626  *
35627  */
35628 /*
35629  * Field : Timestamp Addend Register - tsar
35630  *
35631  * This field indicates the 32-bit time value to be added to the Accumulator
35632  * register to achieve time synchronization.
35633  *
35634  * Field Access Macros:
35635  *
35636  */
35637 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field. */
35638 #define ALT_EMAC_GMAC_TS_ADDEND_TSAR_LSB 0
35639 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field. */
35640 #define ALT_EMAC_GMAC_TS_ADDEND_TSAR_MSB 31
35641 /* The width in bits of the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field. */
35642 #define ALT_EMAC_GMAC_TS_ADDEND_TSAR_WIDTH 32
35643 /* The mask used to set the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field value. */
35644 #define ALT_EMAC_GMAC_TS_ADDEND_TSAR_SET_MSK 0xffffffff
35645 /* The mask used to clear the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field value. */
35646 #define ALT_EMAC_GMAC_TS_ADDEND_TSAR_CLR_MSK 0x00000000
35647 /* The reset value of the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field. */
35648 #define ALT_EMAC_GMAC_TS_ADDEND_TSAR_RESET 0x0
35649 /* Extracts the ALT_EMAC_GMAC_TS_ADDEND_TSAR field value from a register. */
35650 #define ALT_EMAC_GMAC_TS_ADDEND_TSAR_GET(value) (((value) & 0xffffffff) >> 0)
35651 /* Produces a ALT_EMAC_GMAC_TS_ADDEND_TSAR register field value suitable for setting the register. */
35652 #define ALT_EMAC_GMAC_TS_ADDEND_TSAR_SET(value) (((value) << 0) & 0xffffffff)
35653 
35654 #ifndef __ASSEMBLY__
35655 /*
35656  * WARNING: The C register and register group struct declarations are provided for
35657  * convenience and illustrative purposes. They should, however, be used with
35658  * caution as the C language standard provides no guarantees about the alignment or
35659  * atomicity of device memory accesses. The recommended practice for writing
35660  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
35661  * alt_write_word() functions.
35662  *
35663  * The struct declaration for register ALT_EMAC_GMAC_TS_ADDEND.
35664  */
35665 struct ALT_EMAC_GMAC_TS_ADDEND_s
35666 {
35667  uint32_t tsar : 32; /* Timestamp Addend Register */
35668 };
35669 
35670 /* The typedef declaration for register ALT_EMAC_GMAC_TS_ADDEND. */
35671 typedef volatile struct ALT_EMAC_GMAC_TS_ADDEND_s ALT_EMAC_GMAC_TS_ADDEND_t;
35672 #endif /* __ASSEMBLY__ */
35673 
35674 /* The reset value of the ALT_EMAC_GMAC_TS_ADDEND register. */
35675 #define ALT_EMAC_GMAC_TS_ADDEND_RESET 0x00000000
35676 /* The byte offset of the ALT_EMAC_GMAC_TS_ADDEND register from the beginning of the component. */
35677 #define ALT_EMAC_GMAC_TS_ADDEND_OFST 0x718
35678 /* The address of the ALT_EMAC_GMAC_TS_ADDEND register. */
35679 #define ALT_EMAC_GMAC_TS_ADDEND_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TS_ADDEND_OFST))
35680 
35681 /*
35682  * Register : Register 455 (Target Time Seconds Register) - gmacgrp_target_time_seconds
35683  *
35684  * The Target Time Seconds register, along with Target Time Nanoseconds register,
35685  * is used to schedule an interrupt event (Register 458[1] when Advanced
35686  * Timestamping is enabled; otherwise, TS interrupt bit in Register14[9]) when the
35687  * system time exceeds the value programmed in these registers.
35688  *
35689  * Register Layout
35690  *
35691  * Bits | Access | Reset | Description
35692  * :-------|:-------|:------|:-----------------------------
35693  * [31:0] | RW | 0x0 | Target Time Seconds Register
35694  *
35695  */
35696 /*
35697  * Field : Target Time Seconds Register - tstr
35698  *
35699  * This register stores the time in seconds. When the timestamp value matches or
35700  * exceeds both Target Timestamp registers, then based on Bits [6:5] of Register
35701  * 459 (PPS Control Register), the MAC starts or stops the PPS signal output and
35702  * generates an interrupt (if enabled).
35703  *
35704  * Field Access Macros:
35705  *
35706  */
35707 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field. */
35708 #define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_LSB 0
35709 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field. */
35710 #define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_MSB 31
35711 /* The width in bits of the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field. */
35712 #define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_WIDTH 32
35713 /* The mask used to set the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field value. */
35714 #define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_SET_MSK 0xffffffff
35715 /* The mask used to clear the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field value. */
35716 #define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_CLR_MSK 0x00000000
35717 /* The reset value of the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field. */
35718 #define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_RESET 0x0
35719 /* Extracts the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR field value from a register. */
35720 #define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_GET(value) (((value) & 0xffffffff) >> 0)
35721 /* Produces a ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field value suitable for setting the register. */
35722 #define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_SET(value) (((value) << 0) & 0xffffffff)
35723 
35724 #ifndef __ASSEMBLY__
35725 /*
35726  * WARNING: The C register and register group struct declarations are provided for
35727  * convenience and illustrative purposes. They should, however, be used with
35728  * caution as the C language standard provides no guarantees about the alignment or
35729  * atomicity of device memory accesses. The recommended practice for writing
35730  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
35731  * alt_write_word() functions.
35732  *
35733  * The struct declaration for register ALT_EMAC_GMAC_TGT_TIME_SECS.
35734  */
35735 struct ALT_EMAC_GMAC_TGT_TIME_SECS_s
35736 {
35737  uint32_t tstr : 32; /* Target Time Seconds Register */
35738 };
35739 
35740 /* The typedef declaration for register ALT_EMAC_GMAC_TGT_TIME_SECS. */
35741 typedef volatile struct ALT_EMAC_GMAC_TGT_TIME_SECS_s ALT_EMAC_GMAC_TGT_TIME_SECS_t;
35742 #endif /* __ASSEMBLY__ */
35743 
35744 /* The reset value of the ALT_EMAC_GMAC_TGT_TIME_SECS register. */
35745 #define ALT_EMAC_GMAC_TGT_TIME_SECS_RESET 0x00000000
35746 /* The byte offset of the ALT_EMAC_GMAC_TGT_TIME_SECS register from the beginning of the component. */
35747 #define ALT_EMAC_GMAC_TGT_TIME_SECS_OFST 0x71c
35748 /* The address of the ALT_EMAC_GMAC_TGT_TIME_SECS register. */
35749 #define ALT_EMAC_GMAC_TGT_TIME_SECS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TGT_TIME_SECS_OFST))
35750 
35751 /*
35752  * Register : Register 456 (Target Time Nanoseconds Register) - gmacgrp_target_time_nanoseconds
35753  *
35754  * Target time
35755  *
35756  * Register Layout
35757  *
35758  * Bits | Access | Reset | Description
35759  * :-------|:-------|:------|:------------------------------
35760  * [30:0] | RW | 0x0 | Target Timestamp Low Register
35761  * [31] | R | 0x0 | Target Time Register Busy
35762  *
35763  */
35764 /*
35765  * Field : Target Timestamp Low Register - ttslo
35766  *
35767  * This register stores the time in (signed) nanoseconds. When the value of the
35768  * timestamp matches the both Target Timestamp registers, then based on the
35769  * TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), the MAC
35770  * starts or stops the PPS signal output and generates an interrupt (if enabled).
35771  *
35772  * This value should not exceed 0x3B9A_C9FF when TSCTRLSSR is set in the Timestamp
35773  * control register. The actual start or stop time of the PPS signal output may
35774  * have an error margin up to one unit of sub-second increment value.
35775  *
35776  * Field Access Macros:
35777  *
35778  */
35779 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field. */
35780 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_LSB 0
35781 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field. */
35782 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_MSB 30
35783 /* The width in bits of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field. */
35784 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_WIDTH 31
35785 /* The mask used to set the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field value. */
35786 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_SET_MSK 0x7fffffff
35787 /* The mask used to clear the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field value. */
35788 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_CLR_MSK 0x80000000
35789 /* The reset value of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field. */
35790 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_RESET 0x0
35791 /* Extracts the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO field value from a register. */
35792 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_GET(value) (((value) & 0x7fffffff) >> 0)
35793 /* Produces a ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field value suitable for setting the register. */
35794 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_SET(value) (((value) << 0) & 0x7fffffff)
35795 
35796 /*
35797  * Field : Target Time Register Busy - trgtbusy
35798  *
35799  * The MAC sets this bit when the PPSCMD field (Bits[3:0]) in Register 459 (PPS
35800  * Control Register) is programmed to 010 or 011. Programming the PPSCMD field to
35801  * 010 or 011, instructs the MAC to synchronize the Target Time Registers to the
35802  * PTP clock domain.
35803  *
35804  * The MAC clears this bit after synchronizing the Target Time Registers to the PTP
35805  * clock domain The application must not update the Target Time Registers when this
35806  * bit is read as 1. Otherwise, the synchronization of the previous programmed time
35807  * gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second
35808  * Output feature is not selected.
35809  *
35810  * Field Access Macros:
35811  *
35812  */
35813 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field. */
35814 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_LSB 31
35815 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field. */
35816 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_MSB 31
35817 /* The width in bits of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field. */
35818 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_WIDTH 1
35819 /* The mask used to set the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field value. */
35820 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_SET_MSK 0x80000000
35821 /* The mask used to clear the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field value. */
35822 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_CLR_MSK 0x7fffffff
35823 /* The reset value of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field. */
35824 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_RESET 0x0
35825 /* Extracts the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY field value from a register. */
35826 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_GET(value) (((value) & 0x80000000) >> 31)
35827 /* Produces a ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field value suitable for setting the register. */
35828 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_SET(value) (((value) << 31) & 0x80000000)
35829 
35830 #ifndef __ASSEMBLY__
35831 /*
35832  * WARNING: The C register and register group struct declarations are provided for
35833  * convenience and illustrative purposes. They should, however, be used with
35834  * caution as the C language standard provides no guarantees about the alignment or
35835  * atomicity of device memory accesses. The recommended practice for writing
35836  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
35837  * alt_write_word() functions.
35838  *
35839  * The struct declaration for register ALT_EMAC_GMAC_TGT_TIME_NANOSECS.
35840  */
35841 struct ALT_EMAC_GMAC_TGT_TIME_NANOSECS_s
35842 {
35843  uint32_t ttslo : 31; /* Target Timestamp Low Register */
35844  const uint32_t trgtbusy : 1; /* Target Time Register Busy */
35845 };
35846 
35847 /* The typedef declaration for register ALT_EMAC_GMAC_TGT_TIME_NANOSECS. */
35848 typedef volatile struct ALT_EMAC_GMAC_TGT_TIME_NANOSECS_s ALT_EMAC_GMAC_TGT_TIME_NANOSECS_t;
35849 #endif /* __ASSEMBLY__ */
35850 
35851 /* The reset value of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS register. */
35852 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_RESET 0x00000000
35853 /* The byte offset of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS register from the beginning of the component. */
35854 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_OFST 0x720
35855 /* The address of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS register. */
35856 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TGT_TIME_NANOSECS_OFST))
35857 
35858 /*
35859  * Register : Register 457 (System Time - Higher Word Seconds Register) - gmacgrp_system_time_higher_word_seconds
35860  *
35861  * System time higher word
35862  *
35863  * Register Layout
35864  *
35865  * Bits | Access | Reset | Description
35866  * :--------|:-------|:------|:-------------------------------
35867  * [15:0] | RW | 0x0 | Timestamp Higher Word Register
35868  * [31:16] | ??? | 0x0 | *UNDEFINED*
35869  *
35870  */
35871 /*
35872  * Field : Timestamp Higher Word Register - tshwr
35873  *
35874  * This field contains the most significant 16-bits of the timestamp seconds value.
35875  * The register is directly written to initialize the value. This register is
35876  * incremented when there is an overflow from the 32-bits of the System Time -
35877  * Seconds register.
35878  *
35879  * Field Access Macros:
35880  *
35881  */
35882 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field. */
35883 #define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_LSB 0
35884 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field. */
35885 #define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_MSB 15
35886 /* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field. */
35887 #define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_WIDTH 16
35888 /* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field value. */
35889 #define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_SET_MSK 0x0000ffff
35890 /* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field value. */
35891 #define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_CLR_MSK 0xffff0000
35892 /* The reset value of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field. */
35893 #define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_RESET 0x0
35894 /* Extracts the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR field value from a register. */
35895 #define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_GET(value) (((value) & 0x0000ffff) >> 0)
35896 /* Produces a ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field value suitable for setting the register. */
35897 #define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_SET(value) (((value) << 0) & 0x0000ffff)
35898 
35899 #ifndef __ASSEMBLY__
35900 /*
35901  * WARNING: The C register and register group struct declarations are provided for
35902  * convenience and illustrative purposes. They should, however, be used with
35903  * caution as the C language standard provides no guarantees about the alignment or
35904  * atomicity of device memory accesses. The recommended practice for writing
35905  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
35906  * alt_write_word() functions.
35907  *
35908  * The struct declaration for register ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS.
35909  */
35910 struct ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_s
35911 {
35912  uint32_t tshwr : 16; /* Timestamp Higher Word Register */
35913  uint32_t : 16; /* *UNDEFINED* */
35914 };
35915 
35916 /* The typedef declaration for register ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS. */
35917 typedef volatile struct ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_s ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_t;
35918 #endif /* __ASSEMBLY__ */
35919 
35920 /* The reset value of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS register. */
35921 #define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_RESET 0x00000000
35922 /* The byte offset of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS register from the beginning of the component. */
35923 #define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_OFST 0x724
35924 /* The address of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS register. */
35925 #define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_OFST))
35926 
35927 /*
35928  * Register : Register 458 (Timestamp Status Register) - gmacgrp_timestamp_status
35929  *
35930  * Timestamp status. All bits except Bits[27:25] get cleared when the host reads
35931  * this register.
35932  *
35933  * Register Layout
35934  *
35935  * Bits | Access | Reset | Description
35936  * :--------|:-------|:------|:------------------------------------------------
35937  * [0] | R | 0x0 | Timestamp Seconds Overflow
35938  * [1] | R | 0x0 | Timestamp Target Time Reached
35939  * [2] | R | 0x0 | Auxiliary Timestamp Trigger Snapshot
35940  * [3] | R | 0x0 | Timestamp Target Time Error
35941  * [15:4] | ??? | 0x0 | *UNDEFINED*
35942  * [19:16] | R | 0x0 | Auxiliary Timestamp Snapshot Trigger Identifier
35943  * [23:20] | ??? | 0x0 | *UNDEFINED*
35944  * [24] | R | 0x0 | Auxiliary Timestamp Snapshot Trigger Missed
35945  * [29:25] | R | 0x0 | Number of Auxiliary Timestamp Snapshots
35946  * [31:30] | ??? | 0x0 | *UNDEFINED*
35947  *
35948  */
35949 /*
35950  * Field : Timestamp Seconds Overflow - tssovf
35951  *
35952  * When set, this bit indicates that the seconds value of the timestamp (when
35953  * supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF.
35954  *
35955  * Field Enumeration Values:
35956  *
35957  * Enum | Value | Description
35958  * :-----------------------------------|:------|:------------
35959  * ALT_EMAC_GMAC_TS_STAT_TSSOVF_E_RST | 0x0 |
35960  * ALT_EMAC_GMAC_TS_STAT_TSSOVF_E_SET | 0x1 |
35961  *
35962  * Field Access Macros:
35963  *
35964  */
35965 /*
35966  * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSSOVF
35967  *
35968  */
35969 #define ALT_EMAC_GMAC_TS_STAT_TSSOVF_E_RST 0x0
35970 /*
35971  * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSSOVF
35972  *
35973  */
35974 #define ALT_EMAC_GMAC_TS_STAT_TSSOVF_E_SET 0x1
35975 
35976 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field. */
35977 #define ALT_EMAC_GMAC_TS_STAT_TSSOVF_LSB 0
35978 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field. */
35979 #define ALT_EMAC_GMAC_TS_STAT_TSSOVF_MSB 0
35980 /* The width in bits of the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field. */
35981 #define ALT_EMAC_GMAC_TS_STAT_TSSOVF_WIDTH 1
35982 /* The mask used to set the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field value. */
35983 #define ALT_EMAC_GMAC_TS_STAT_TSSOVF_SET_MSK 0x00000001
35984 /* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field value. */
35985 #define ALT_EMAC_GMAC_TS_STAT_TSSOVF_CLR_MSK 0xfffffffe
35986 /* The reset value of the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field. */
35987 #define ALT_EMAC_GMAC_TS_STAT_TSSOVF_RESET 0x0
35988 /* Extracts the ALT_EMAC_GMAC_TS_STAT_TSSOVF field value from a register. */
35989 #define ALT_EMAC_GMAC_TS_STAT_TSSOVF_GET(value) (((value) & 0x00000001) >> 0)
35990 /* Produces a ALT_EMAC_GMAC_TS_STAT_TSSOVF register field value suitable for setting the register. */
35991 #define ALT_EMAC_GMAC_TS_STAT_TSSOVF_SET(value) (((value) << 0) & 0x00000001)
35992 
35993 /*
35994  * Field : Timestamp Target Time Reached - tstargt
35995  *
35996  * When set, this bit indicates that the value of system time is greater or equal
35997  * to the value specified in the Register 455 (Target Time Seconds Register) and
35998  * Register 456 (Target Time Nanoseconds Register).
35999  *
36000  * Field Enumeration Values:
36001  *
36002  * Enum | Value | Description
36003  * :------------------------------------|:------|:------------
36004  * ALT_EMAC_GMAC_TS_STAT_TSTARGT_E_RST | 0x0 |
36005  * ALT_EMAC_GMAC_TS_STAT_TSTARGT_E_SET | 0x1 |
36006  *
36007  * Field Access Macros:
36008  *
36009  */
36010 /*
36011  * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSTARGT
36012  *
36013  */
36014 #define ALT_EMAC_GMAC_TS_STAT_TSTARGT_E_RST 0x0
36015 /*
36016  * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSTARGT
36017  *
36018  */
36019 #define ALT_EMAC_GMAC_TS_STAT_TSTARGT_E_SET 0x1
36020 
36021 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field. */
36022 #define ALT_EMAC_GMAC_TS_STAT_TSTARGT_LSB 1
36023 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field. */
36024 #define ALT_EMAC_GMAC_TS_STAT_TSTARGT_MSB 1
36025 /* The width in bits of the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field. */
36026 #define ALT_EMAC_GMAC_TS_STAT_TSTARGT_WIDTH 1
36027 /* The mask used to set the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field value. */
36028 #define ALT_EMAC_GMAC_TS_STAT_TSTARGT_SET_MSK 0x00000002
36029 /* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field value. */
36030 #define ALT_EMAC_GMAC_TS_STAT_TSTARGT_CLR_MSK 0xfffffffd
36031 /* The reset value of the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field. */
36032 #define ALT_EMAC_GMAC_TS_STAT_TSTARGT_RESET 0x0
36033 /* Extracts the ALT_EMAC_GMAC_TS_STAT_TSTARGT field value from a register. */
36034 #define ALT_EMAC_GMAC_TS_STAT_TSTARGT_GET(value) (((value) & 0x00000002) >> 1)
36035 /* Produces a ALT_EMAC_GMAC_TS_STAT_TSTARGT register field value suitable for setting the register. */
36036 #define ALT_EMAC_GMAC_TS_STAT_TSTARGT_SET(value) (((value) << 1) & 0x00000002)
36037 
36038 /*
36039  * Field : Auxiliary Timestamp Trigger Snapshot - auxtstrig
36040  *
36041  * This bit is set high when the auxiliary snapshot is written to the FIFO.
36042  *
36043  * Field Enumeration Values:
36044  *
36045  * Enum | Value | Description
36046  * :--------------------------------------|:------|:------------
36047  * ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_E_RST | 0x0 |
36048  * ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_E_SET | 0x1 |
36049  *
36050  * Field Access Macros:
36051  *
36052  */
36053 /*
36054  * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG
36055  *
36056  */
36057 #define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_E_RST 0x0
36058 /*
36059  * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG
36060  *
36061  */
36062 #define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_E_SET 0x1
36063 
36064 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field. */
36065 #define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_LSB 2
36066 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field. */
36067 #define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_MSB 2
36068 /* The width in bits of the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field. */
36069 #define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_WIDTH 1
36070 /* The mask used to set the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field value. */
36071 #define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_SET_MSK 0x00000004
36072 /* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field value. */
36073 #define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_CLR_MSK 0xfffffffb
36074 /* The reset value of the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field. */
36075 #define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_RESET 0x0
36076 /* Extracts the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG field value from a register. */
36077 #define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_GET(value) (((value) & 0x00000004) >> 2)
36078 /* Produces a ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field value suitable for setting the register. */
36079 #define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_SET(value) (((value) << 2) & 0x00000004)
36080 
36081 /*
36082  * Field : Timestamp Target Time Error - tstrgterr
36083  *
36084  * This bit is set when the target time, being programmed in Target Time Registers,
36085  * is already elapsed. This bit is cleared when read by the application.
36086  *
36087  * Field Enumeration Values:
36088  *
36089  * Enum | Value | Description
36090  * :--------------------------------------|:------|:------------
36091  * ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_E_RST | 0x0 |
36092  * ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_E_SET | 0x1 |
36093  *
36094  * Field Access Macros:
36095  *
36096  */
36097 /*
36098  * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSTRGTERR
36099  *
36100  */
36101 #define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_E_RST 0x0
36102 /*
36103  * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSTRGTERR
36104  *
36105  */
36106 #define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_E_SET 0x1
36107 
36108 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field. */
36109 #define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_LSB 3
36110 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field. */
36111 #define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_MSB 3
36112 /* The width in bits of the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field. */
36113 #define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_WIDTH 1
36114 /* The mask used to set the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field value. */
36115 #define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_SET_MSK 0x00000008
36116 /* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field value. */
36117 #define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_CLR_MSK 0xfffffff7
36118 /* The reset value of the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field. */
36119 #define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_RESET 0x0
36120 /* Extracts the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR field value from a register. */
36121 #define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_GET(value) (((value) & 0x00000008) >> 3)
36122 /* Produces a ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field value suitable for setting the register. */
36123 #define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_SET(value) (((value) << 3) & 0x00000008)
36124 
36125 /*
36126  * Field : Auxiliary Timestamp Snapshot Trigger Identifier - atsstn
36127  *
36128  * These bits identify the Auxiliary trigger inputs for which the timestamp
36129  * available in the Auxiliary Snapshot Register is applicable. When more than one
36130  * bit is set at the same time, it means that corresponding auxiliary triggers were
36131  * sampled at the same clock. These bits are applicable only if the number of
36132  * Auxiliary snapshots is more than one. One bit is assigned for each trigger as
36133  * shown in the following list:
36134  *
36135  * * Bit 16: Auxiliary trigger 0
36136  *
36137  * * Bit 17: Auxiliary trigger 1
36138  *
36139  * * Bit 18: Auxiliary trigger 2
36140  *
36141  * * Bit 19: Auxiliary trigger 3
36142  *
36143  * The software can read this register to find the triggers that are set when the
36144  * timestamp is taken.
36145  *
36146  * Field Access Macros:
36147  *
36148  */
36149 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field. */
36150 #define ALT_EMAC_GMAC_TS_STAT_ATSSTN_LSB 16
36151 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field. */
36152 #define ALT_EMAC_GMAC_TS_STAT_ATSSTN_MSB 19
36153 /* The width in bits of the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field. */
36154 #define ALT_EMAC_GMAC_TS_STAT_ATSSTN_WIDTH 4
36155 /* The mask used to set the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field value. */
36156 #define ALT_EMAC_GMAC_TS_STAT_ATSSTN_SET_MSK 0x000f0000
36157 /* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field value. */
36158 #define ALT_EMAC_GMAC_TS_STAT_ATSSTN_CLR_MSK 0xfff0ffff
36159 /* The reset value of the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field. */
36160 #define ALT_EMAC_GMAC_TS_STAT_ATSSTN_RESET 0x0
36161 /* Extracts the ALT_EMAC_GMAC_TS_STAT_ATSSTN field value from a register. */
36162 #define ALT_EMAC_GMAC_TS_STAT_ATSSTN_GET(value) (((value) & 0x000f0000) >> 16)
36163 /* Produces a ALT_EMAC_GMAC_TS_STAT_ATSSTN register field value suitable for setting the register. */
36164 #define ALT_EMAC_GMAC_TS_STAT_ATSSTN_SET(value) (((value) << 16) & 0x000f0000)
36165 
36166 /*
36167  * Field : Auxiliary Timestamp Snapshot Trigger Missed - atsstm
36168  *
36169  * This bit is set when the Auxiliary timestamp snapshot FIFO is full and external
36170  * trigger was set. This indicates that the latest snapshot is not stored in the
36171  * FIFO.
36172  *
36173  * Field Enumeration Values:
36174  *
36175  * Enum | Value | Description
36176  * :---------------------------------------|:------|:------------
36177  * ALT_EMAC_GMAC_TS_STAT_ATSSTM_E_NOTFULL | 0x0 |
36178  * ALT_EMAC_GMAC_TS_STAT_ATSSTM_E_FULL | 0x1 |
36179  *
36180  * Field Access Macros:
36181  *
36182  */
36183 /*
36184  * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_ATSSTM
36185  *
36186  */
36187 #define ALT_EMAC_GMAC_TS_STAT_ATSSTM_E_NOTFULL 0x0
36188 /*
36189  * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_ATSSTM
36190  *
36191  */
36192 #define ALT_EMAC_GMAC_TS_STAT_ATSSTM_E_FULL 0x1
36193 
36194 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field. */
36195 #define ALT_EMAC_GMAC_TS_STAT_ATSSTM_LSB 24
36196 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field. */
36197 #define ALT_EMAC_GMAC_TS_STAT_ATSSTM_MSB 24
36198 /* The width in bits of the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field. */
36199 #define ALT_EMAC_GMAC_TS_STAT_ATSSTM_WIDTH 1
36200 /* The mask used to set the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field value. */
36201 #define ALT_EMAC_GMAC_TS_STAT_ATSSTM_SET_MSK 0x01000000
36202 /* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field value. */
36203 #define ALT_EMAC_GMAC_TS_STAT_ATSSTM_CLR_MSK 0xfeffffff
36204 /* The reset value of the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field. */
36205 #define ALT_EMAC_GMAC_TS_STAT_ATSSTM_RESET 0x0
36206 /* Extracts the ALT_EMAC_GMAC_TS_STAT_ATSSTM field value from a register. */
36207 #define ALT_EMAC_GMAC_TS_STAT_ATSSTM_GET(value) (((value) & 0x01000000) >> 24)
36208 /* Produces a ALT_EMAC_GMAC_TS_STAT_ATSSTM register field value suitable for setting the register. */
36209 #define ALT_EMAC_GMAC_TS_STAT_ATSSTM_SET(value) (((value) << 24) & 0x01000000)
36210 
36211 /*
36212  * Field : Number of Auxiliary Timestamp Snapshots - atsns
36213  *
36214  * This field indicates the number of Snapshots available in the FIFO. A value of
36215  * 16 (equal to the depth of the FIFO) indicates that the Auxiliary Snapshot FIFO
36216  * is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO
36217  * clear bit is set.
36218  *
36219  * Field Access Macros:
36220  *
36221  */
36222 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSNS register field. */
36223 #define ALT_EMAC_GMAC_TS_STAT_ATSNS_LSB 25
36224 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSNS register field. */
36225 #define ALT_EMAC_GMAC_TS_STAT_ATSNS_MSB 29
36226 /* The width in bits of the ALT_EMAC_GMAC_TS_STAT_ATSNS register field. */
36227 #define ALT_EMAC_GMAC_TS_STAT_ATSNS_WIDTH 5
36228 /* The mask used to set the ALT_EMAC_GMAC_TS_STAT_ATSNS register field value. */
36229 #define ALT_EMAC_GMAC_TS_STAT_ATSNS_SET_MSK 0x3e000000
36230 /* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_ATSNS register field value. */
36231 #define ALT_EMAC_GMAC_TS_STAT_ATSNS_CLR_MSK 0xc1ffffff
36232 /* The reset value of the ALT_EMAC_GMAC_TS_STAT_ATSNS register field. */
36233 #define ALT_EMAC_GMAC_TS_STAT_ATSNS_RESET 0x0
36234 /* Extracts the ALT_EMAC_GMAC_TS_STAT_ATSNS field value from a register. */
36235 #define ALT_EMAC_GMAC_TS_STAT_ATSNS_GET(value) (((value) & 0x3e000000) >> 25)
36236 /* Produces a ALT_EMAC_GMAC_TS_STAT_ATSNS register field value suitable for setting the register. */
36237 #define ALT_EMAC_GMAC_TS_STAT_ATSNS_SET(value) (((value) << 25) & 0x3e000000)
36238 
36239 #ifndef __ASSEMBLY__
36240 /*
36241  * WARNING: The C register and register group struct declarations are provided for
36242  * convenience and illustrative purposes. They should, however, be used with
36243  * caution as the C language standard provides no guarantees about the alignment or
36244  * atomicity of device memory accesses. The recommended practice for writing
36245  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
36246  * alt_write_word() functions.
36247  *
36248  * The struct declaration for register ALT_EMAC_GMAC_TS_STAT.
36249  */
36250 struct ALT_EMAC_GMAC_TS_STAT_s
36251 {
36252  const uint32_t tssovf : 1; /* Timestamp Seconds Overflow */
36253  const uint32_t tstargt : 1; /* Timestamp Target Time Reached */
36254  const uint32_t auxtstrig : 1; /* Auxiliary Timestamp Trigger Snapshot */
36255  const uint32_t tstrgterr : 1; /* Timestamp Target Time Error */
36256  uint32_t : 12; /* *UNDEFINED* */
36257  const uint32_t atsstn : 4; /* Auxiliary Timestamp Snapshot Trigger Identifier */
36258  uint32_t : 4; /* *UNDEFINED* */
36259  const uint32_t atsstm : 1; /* Auxiliary Timestamp Snapshot Trigger Missed */
36260  const uint32_t atsns : 5; /* Number of Auxiliary Timestamp Snapshots */
36261  uint32_t : 2; /* *UNDEFINED* */
36262 };
36263 
36264 /* The typedef declaration for register ALT_EMAC_GMAC_TS_STAT. */
36265 typedef volatile struct ALT_EMAC_GMAC_TS_STAT_s ALT_EMAC_GMAC_TS_STAT_t;
36266 #endif /* __ASSEMBLY__ */
36267 
36268 /* The reset value of the ALT_EMAC_GMAC_TS_STAT register. */
36269 #define ALT_EMAC_GMAC_TS_STAT_RESET 0x00000000
36270 /* The byte offset of the ALT_EMAC_GMAC_TS_STAT register from the beginning of the component. */
36271 #define ALT_EMAC_GMAC_TS_STAT_OFST 0x728
36272 /* The address of the ALT_EMAC_GMAC_TS_STAT register. */
36273 #define ALT_EMAC_GMAC_TS_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TS_STAT_OFST))
36274 
36275 /*
36276  * Register : Register 459 (PPS Control Register) - gmacgrp_pps_control
36277  *
36278  * Controls timestamp Pulse-Per-Second output
36279  *
36280  * Register Layout
36281  *
36282  * Bits | Access | Reset | Description
36283  * :-------|:-------|:------|:------------------------------------------
36284  * [3:0] | RW | 0x0 | PPSCTRL0 or PPSCMD0
36285  * [4] | RW | 0x0 | Flexible PPS Output Mode Enable
36286  * [6:5] | RW | 0x0 | Target Time Register Mode for PPS0 Output
36287  * [31:7] | ??? | 0x0 | *UNDEFINED*
36288  *
36289  */
36290 /*
36291  * Field : PPSCTRL0 or PPSCMD0 - ppsctrl_ppscmd
36292  *
36293  * PPSCTRL0: PPS0 Output Frequency Control
36294  *
36295  * This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. The
36296  * default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width
36297  * clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a
36298  * generated clock of following frequencies:
36299  *
36300  * * 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz.
36301  *
36302  * * 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz.
36303  *
36304  * * 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz.
36305  *
36306  * * 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz.
36307  *
36308  * * ...
36309  *
36310  * * 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384
36311  * KHz.
36312  *
36313  * Note:
36314  *
36315  * In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50
36316  * percent with these frequencies.
36317  *
36318  * In the digital rollover mode, the PPS output frequency is an average number. The
36319  * actual clock is of different frequency that gets synchronized every second. For
36320  * example:
36321  *
36322  * - When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high
36323  * period of 463 ms
36324  *
36325  * - When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of:
36326  *
36327  * * One clock of 50 percent duty cycle and 537 ms period
36328  *
36329  * * Second clock of 463 ms period (268 ms low and 195 ms high)
36330  *
36331  * - When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of:
36332  *
36333  * * Three clocks of 50 percent duty cycle and 268 ms period
36334  *
36335  * * Fourth clock of 195 ms period (134 ms low and 61 ms high)
36336  *
36337  * This behavior is because of the non-linear toggling of bits in the digital
36338  * rollover mode in Register 451 (System Time - Nanoseconds Register).
36339  *
36340  * Flexible PPS0 Output (ptp_pps_o[0]) Control
36341  *
36342  * Programming these bits with a non-zero value instructs the MAC to initiate an
36343  * event. Once the command is transferred or synchronized to the PTP clock domain,
36344  * these bits get cleared automatically. The Software should ensure that these bits
36345  * are programmed only when they are all-zero. The following list describes the
36346  * values of PPSCMD0:
36347  *
36348  * - 0000: No Command
36349  *
36350  * - 0001: START Single Pulse
36351  *
36352  * This command generates single pulse rising at the start point defined in Target
36353  * Time Registers (register 455 and 456) and of a duration defined in the PPS0
36354  * Width Register.
36355  *
36356  * - 0010: START Pulse Train
36357  *
36358  * This command generates the train of pulses rising at the start point defined in
36359  * the Target Time Registers and of a duration defined in the PPS0 Width Register
36360  * and repeated at interval defined in the PPS Interval Register. By default, the
36361  * PPS pulse train is free-running unless stopped by 'STOP Pulse train at time' or
36362  * 'STOP Pulse Train immediately' commands.
36363  *
36364  * - 0011: Cancel START
36365  *
36366  * This command cancels the START Single Pulse and START Pulse Train commands if
36367  * the system time has not crossed the programmed start time.
36368  *
36369  * - 0100: STOP Pulse train at time
36370  *
36371  * This command stops the train of pulses initiated by the START Pulse Train
36372  * command (PPSCMD = 0010) after the time programmed in the Target Time registers
36373  * elapses.
36374  *
36375  * - 0101: STOP Pulse Train immediately
36376  *
36377  * This command immediately stops the train of pulses initiated by the START Pulse
36378  * Train command (PPSCMD = 0010).
36379  *
36380  * - 0110: Cancel STOP Pulse train
36381  *
36382  * This command cancels the STOP pulse train at time command if the programmed stop
36383  * time has not elapsed. The PPS pulse train becomes free-running on the successful
36384  * execution of this command.
36385  *
36386  * - 0111-1111: Reserved
36387  *
36388  * Field Access Macros:
36389  *
36390  */
36391 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field. */
36392 #define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_LSB 0
36393 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field. */
36394 #define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_MSB 3
36395 /* The width in bits of the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field. */
36396 #define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_WIDTH 4
36397 /* The mask used to set the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field value. */
36398 #define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_SET_MSK 0x0000000f
36399 /* The mask used to clear the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field value. */
36400 #define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_CLR_MSK 0xfffffff0
36401 /* The reset value of the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field. */
36402 #define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_RESET 0x0
36403 /* Extracts the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD field value from a register. */
36404 #define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_GET(value) (((value) & 0x0000000f) >> 0)
36405 /* Produces a ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field value suitable for setting the register. */
36406 #define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_SET(value) (((value) << 0) & 0x0000000f)
36407 
36408 /*
36409  * Field : Flexible PPS Output Mode Enable - ppsen0
36410  *
36411  * When set low, Bits[3:0] function as PPSCTRL (backward compatible). When set
36412  * high, Bits[3:0] function as PPSCMD.
36413  *
36414  * Field Enumeration Values:
36415  *
36416  * Enum | Value | Description
36417  * :--------------------------------------|:------|:------------
36418  * ALT_EMAC_GMAC_PPS_CTL_PPSEN0_E_PPSCTL | 0x0 |
36419  * ALT_EMAC_GMAC_PPS_CTL_PPSEN0_E_PPSCMD | 0x1 |
36420  *
36421  * Field Access Macros:
36422  *
36423  */
36424 /*
36425  * Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_PPSEN0
36426  *
36427  */
36428 #define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_E_PPSCTL 0x0
36429 /*
36430  * Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_PPSEN0
36431  *
36432  */
36433 #define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_E_PPSCMD 0x1
36434 
36435 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field. */
36436 #define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_LSB 4
36437 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field. */
36438 #define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_MSB 4
36439 /* The width in bits of the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field. */
36440 #define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_WIDTH 1
36441 /* The mask used to set the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field value. */
36442 #define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_SET_MSK 0x00000010
36443 /* The mask used to clear the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field value. */
36444 #define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_CLR_MSK 0xffffffef
36445 /* The reset value of the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field. */
36446 #define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_RESET 0x0
36447 /* Extracts the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 field value from a register. */
36448 #define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_GET(value) (((value) & 0x00000010) >> 4)
36449 /* Produces a ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field value suitable for setting the register. */
36450 #define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_SET(value) (((value) << 4) & 0x00000010)
36451 
36452 /*
36453  * Field : Target Time Register Mode for PPS0 Output - trgtmodsel0
36454  *
36455  * This field indicates the Target Time registers (register 455 and 456) mode for
36456  * PPS0 output signal
36457  *
36458  * Field Enumeration Values:
36459  *
36460  * Enum | Value | Description
36461  * :--------------------------------------------------|:------|:------------
36462  * ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTINTERONLY | 0x0 |
36463  * ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTINTPPS0 | 0x2 |
36464  * ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTNOINTER | 0x3 |
36465  *
36466  * Field Access Macros:
36467  *
36468  */
36469 /*
36470  * Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0
36471  *
36472  */
36473 #define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTINTERONLY 0x0
36474 /*
36475  * Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0
36476  *
36477  */
36478 #define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTINTPPS0 0x2
36479 /*
36480  * Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0
36481  *
36482  */
36483 #define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTNOINTER 0x3
36484 
36485 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field. */
36486 #define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_LSB 5
36487 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field. */
36488 #define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_MSB 6
36489 /* The width in bits of the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field. */
36490 #define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_WIDTH 2
36491 /* The mask used to set the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field value. */
36492 #define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_SET_MSK 0x00000060
36493 /* The mask used to clear the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field value. */
36494 #define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_CLR_MSK 0xffffff9f
36495 /* The reset value of the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field. */
36496 #define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_RESET 0x0
36497 /* Extracts the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 field value from a register. */
36498 #define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_GET(value) (((value) & 0x00000060) >> 5)
36499 /* Produces a ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field value suitable for setting the register. */
36500 #define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_SET(value) (((value) << 5) & 0x00000060)
36501 
36502 #ifndef __ASSEMBLY__
36503 /*
36504  * WARNING: The C register and register group struct declarations are provided for
36505  * convenience and illustrative purposes. They should, however, be used with
36506  * caution as the C language standard provides no guarantees about the alignment or
36507  * atomicity of device memory accesses. The recommended practice for writing
36508  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
36509  * alt_write_word() functions.
36510  *
36511  * The struct declaration for register ALT_EMAC_GMAC_PPS_CTL.
36512  */
36513 struct ALT_EMAC_GMAC_PPS_CTL_s
36514 {
36515  uint32_t ppsctrl_ppscmd : 4; /* PPSCTRL0 or PPSCMD0 */
36516  uint32_t ppsen0 : 1; /* Flexible PPS Output Mode Enable */
36517  uint32_t trgtmodsel0 : 2; /* Target Time Register Mode for PPS0 Output */
36518  uint32_t : 25; /* *UNDEFINED* */
36519 };
36520 
36521 /* The typedef declaration for register ALT_EMAC_GMAC_PPS_CTL. */
36522 typedef volatile struct ALT_EMAC_GMAC_PPS_CTL_s ALT_EMAC_GMAC_PPS_CTL_t;
36523 #endif /* __ASSEMBLY__ */
36524 
36525 /* The reset value of the ALT_EMAC_GMAC_PPS_CTL register. */
36526 #define ALT_EMAC_GMAC_PPS_CTL_RESET 0x00000000
36527 /* The byte offset of the ALT_EMAC_GMAC_PPS_CTL register from the beginning of the component. */
36528 #define ALT_EMAC_GMAC_PPS_CTL_OFST 0x72c
36529 /* The address of the ALT_EMAC_GMAC_PPS_CTL register. */
36530 #define ALT_EMAC_GMAC_PPS_CTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_PPS_CTL_OFST))
36531 
36532 /*
36533  * Register : Register 460 (Auxiliary Timestamp - Nanoseconds Register) - gmacgrp_auxiliary_timestamp_nanoseconds
36534  *
36535  * This register, along with Register 461 (Auxiliary Timestamp Seconds Register),
36536  * gives the 64-bit timestamp stored as auxiliary snapshot. The two registers
36537  * together form the read port of a 64-bit wide FIFO with a depth of 16. Multiple
36538  * snapshots can be stored in this FIFO. The ATSNS bits in the Timestamp Status
36539  * register indicate the fill-level of this FIFO. The top of the FIFO is removed
36540  * only when the last byte of Register 461 (Auxiliary Timestamp - Seconds Register)
36541  * is read. In the little-endian mode, this means when Bits[31:24] are read. In
36542  * big-endian mode, it corresponds to the reading of Bits[7:0] of Register 461
36543  * (Auxiliary Timestamp - Seconds Register).
36544  *
36545  * Register Layout
36546  *
36547  * Bits | Access | Reset | Description
36548  * :-------|:-------|:------|:--------------------------------------
36549  * [30:0] | R | 0x0 | ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO
36550  * [31] | ??? | 0x0 | *UNDEFINED*
36551  *
36552  */
36553 /*
36554  * Field : auxtslo
36555  *
36556  * Contains the lower 32 bits (nano-seconds field) of the auxiliary timestamp.
36557  *
36558  * Field Access Macros:
36559  *
36560  */
36561 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field. */
36562 #define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_LSB 0
36563 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field. */
36564 #define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_MSB 30
36565 /* The width in bits of the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field. */
36566 #define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_WIDTH 31
36567 /* The mask used to set the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field value. */
36568 #define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_SET_MSK 0x7fffffff
36569 /* The mask used to clear the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field value. */
36570 #define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_CLR_MSK 0x80000000
36571 /* The reset value of the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field. */
36572 #define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_RESET 0x0
36573 /* Extracts the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO field value from a register. */
36574 #define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_GET(value) (((value) & 0x7fffffff) >> 0)
36575 /* Produces a ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field value suitable for setting the register. */
36576 #define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_SET(value) (((value) << 0) & 0x7fffffff)
36577 
36578 #ifndef __ASSEMBLY__
36579 /*
36580  * WARNING: The C register and register group struct declarations are provided for
36581  * convenience and illustrative purposes. They should, however, be used with
36582  * caution as the C language standard provides no guarantees about the alignment or
36583  * atomicity of device memory accesses. The recommended practice for writing
36584  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
36585  * alt_write_word() functions.
36586  *
36587  * The struct declaration for register ALT_EMAC_GMAC_AUX_TS_NANOSECS.
36588  */
36589 struct ALT_EMAC_GMAC_AUX_TS_NANOSECS_s
36590 {
36591  const uint32_t auxtslo : 31; /* ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO */
36592  uint32_t : 1; /* *UNDEFINED* */
36593 };
36594 
36595 /* The typedef declaration for register ALT_EMAC_GMAC_AUX_TS_NANOSECS. */
36596 typedef volatile struct ALT_EMAC_GMAC_AUX_TS_NANOSECS_s ALT_EMAC_GMAC_AUX_TS_NANOSECS_t;
36597 #endif /* __ASSEMBLY__ */
36598 
36599 /* The reset value of the ALT_EMAC_GMAC_AUX_TS_NANOSECS register. */
36600 #define ALT_EMAC_GMAC_AUX_TS_NANOSECS_RESET 0x00000000
36601 /* The byte offset of the ALT_EMAC_GMAC_AUX_TS_NANOSECS register from the beginning of the component. */
36602 #define ALT_EMAC_GMAC_AUX_TS_NANOSECS_OFST 0x730
36603 /* The address of the ALT_EMAC_GMAC_AUX_TS_NANOSECS register. */
36604 #define ALT_EMAC_GMAC_AUX_TS_NANOSECS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_AUX_TS_NANOSECS_OFST))
36605 
36606 /*
36607  * Register : Register 461 (Auxiliary Timestamp - Seconds Register) - gmacgrp_auxiliary_timestamp_seconds
36608  *
36609  * Contains the higher 32 bits (Seconds field) of the auxiliary timestamp.
36610  *
36611  * Register Layout
36612  *
36613  * Bits | Access | Reset | Description
36614  * :-------|:-------|:------|:----------------------------------
36615  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI
36616  *
36617  */
36618 /*
36619  * Field : auxtshi
36620  *
36621  * Contains the higher 32 bits (Seconds field) of the auxiliary timestamp.
36622  *
36623  * Field Access Macros:
36624  *
36625  */
36626 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field. */
36627 #define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_LSB 0
36628 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field. */
36629 #define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_MSB 31
36630 /* The width in bits of the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field. */
36631 #define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_WIDTH 32
36632 /* The mask used to set the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field value. */
36633 #define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_SET_MSK 0xffffffff
36634 /* The mask used to clear the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field value. */
36635 #define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_CLR_MSK 0x00000000
36636 /* The reset value of the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field. */
36637 #define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_RESET 0x0
36638 /* Extracts the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI field value from a register. */
36639 #define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_GET(value) (((value) & 0xffffffff) >> 0)
36640 /* Produces a ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field value suitable for setting the register. */
36641 #define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_SET(value) (((value) << 0) & 0xffffffff)
36642 
36643 #ifndef __ASSEMBLY__
36644 /*
36645  * WARNING: The C register and register group struct declarations are provided for
36646  * convenience and illustrative purposes. They should, however, be used with
36647  * caution as the C language standard provides no guarantees about the alignment or
36648  * atomicity of device memory accesses. The recommended practice for writing
36649  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
36650  * alt_write_word() functions.
36651  *
36652  * The struct declaration for register ALT_EMAC_GMAC_AUX_TS_SECS.
36653  */
36654 struct ALT_EMAC_GMAC_AUX_TS_SECS_s
36655 {
36656  const uint32_t auxtshi : 32; /* ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI */
36657 };
36658 
36659 /* The typedef declaration for register ALT_EMAC_GMAC_AUX_TS_SECS. */
36660 typedef volatile struct ALT_EMAC_GMAC_AUX_TS_SECS_s ALT_EMAC_GMAC_AUX_TS_SECS_t;
36661 #endif /* __ASSEMBLY__ */
36662 
36663 /* The reset value of the ALT_EMAC_GMAC_AUX_TS_SECS register. */
36664 #define ALT_EMAC_GMAC_AUX_TS_SECS_RESET 0x00000000
36665 /* The byte offset of the ALT_EMAC_GMAC_AUX_TS_SECS register from the beginning of the component. */
36666 #define ALT_EMAC_GMAC_AUX_TS_SECS_OFST 0x734
36667 /* The address of the ALT_EMAC_GMAC_AUX_TS_SECS register. */
36668 #define ALT_EMAC_GMAC_AUX_TS_SECS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_AUX_TS_SECS_OFST))
36669 
36670 /*
36671  * Register : Register 472 (PPS0 Interval Register) - gmacgrp_pps0_interval
36672  *
36673  * The PPS0 Interval register contains the number of units of sub-second increment
36674  * value between the rising edges of PPS0 signal output (ptp_pps_o[0]).
36675  *
36676  * Register Layout
36677  *
36678  * Bits | Access | Reset | Description
36679  * :-------|:-------|:------|:----------------------------
36680  * [31:0] | RW | 0x0 | PPS0 Output Signal Interval
36681  *
36682  */
36683 /*
36684  * Field : PPS0 Output Signal Interval - ppsint
36685  *
36686  * These bits store the interval between the rising edges of PPS0 signal output in
36687  * terms of units of sub-second increment value.
36688  *
36689  * You need to program one value less than the required interval. For example, if
36690  * the PTP reference clock is 50 MHz (period of 20ns), and desired interval between
36691  * rising edges of PPS0 signal output is 100ns (that is, five units of sub-second
36692  * increment value), then you should program value 4 (5 -1) in this register.
36693  *
36694  * Field Access Macros:
36695  *
36696  */
36697 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field. */
36698 #define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_LSB 0
36699 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field. */
36700 #define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_MSB 31
36701 /* The width in bits of the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field. */
36702 #define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_WIDTH 32
36703 /* The mask used to set the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field value. */
36704 #define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_SET_MSK 0xffffffff
36705 /* The mask used to clear the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field value. */
36706 #define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_CLR_MSK 0x00000000
36707 /* The reset value of the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field. */
36708 #define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_RESET 0x0
36709 /* Extracts the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT field value from a register. */
36710 #define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_GET(value) (((value) & 0xffffffff) >> 0)
36711 /* Produces a ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field value suitable for setting the register. */
36712 #define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_SET(value) (((value) << 0) & 0xffffffff)
36713 
36714 #ifndef __ASSEMBLY__
36715 /*
36716  * WARNING: The C register and register group struct declarations are provided for
36717  * convenience and illustrative purposes. They should, however, be used with
36718  * caution as the C language standard provides no guarantees about the alignment or
36719  * atomicity of device memory accesses. The recommended practice for writing
36720  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
36721  * alt_write_word() functions.
36722  *
36723  * The struct declaration for register ALT_EMAC_GMAC_PPS0_INTERVAL.
36724  */
36725 struct ALT_EMAC_GMAC_PPS0_INTERVAL_s
36726 {
36727  uint32_t ppsint : 32; /* PPS0 Output Signal Interval */
36728 };
36729 
36730 /* The typedef declaration for register ALT_EMAC_GMAC_PPS0_INTERVAL. */
36731 typedef volatile struct ALT_EMAC_GMAC_PPS0_INTERVAL_s ALT_EMAC_GMAC_PPS0_INTERVAL_t;
36732 #endif /* __ASSEMBLY__ */
36733 
36734 /* The reset value of the ALT_EMAC_GMAC_PPS0_INTERVAL register. */
36735 #define ALT_EMAC_GMAC_PPS0_INTERVAL_RESET 0x00000000
36736 /* The byte offset of the ALT_EMAC_GMAC_PPS0_INTERVAL register from the beginning of the component. */
36737 #define ALT_EMAC_GMAC_PPS0_INTERVAL_OFST 0x760
36738 /* The address of the ALT_EMAC_GMAC_PPS0_INTERVAL register. */
36739 #define ALT_EMAC_GMAC_PPS0_INTERVAL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_PPS0_INTERVAL_OFST))
36740 
36741 /*
36742  * Register : Register 473 (PPS0 Width Register) - gmacgrp_pps0_width
36743  *
36744  * The PPS0 Width register contains the number of units of sub-second increment
36745  * value between the rising and corresponding falling edges of the PPS0 signal
36746  * output (ptp_pps_o[0]).
36747  *
36748  * Register Layout
36749  *
36750  * Bits | Access | Reset | Description
36751  * :-------|:-------|:------|:-------------------------
36752  * [31:0] | RW | 0x0 | PPS0 Output Signal Width
36753  *
36754  */
36755 /*
36756  * Field : PPS0 Output Signal Width - ppswidth
36757  *
36758  * These bits store the width between the rising edge and corresponding falling
36759  * edge of the PPS0 signal output in terms of units of sub-second increment value.
36760  *
36761  * You need to program one value less than the required interval. For example, if
36762  * PTP reference clock is 50 MHz (period of 20ns), and desired width between the
36763  * rising and corresponding falling edges of PPS0 signal output is 80ns (that is,
36764  * four units of sub-second increment value), then you should program value 3 (4-1)
36765  * in this register.
36766  *
36767  * Note:
36768  *
36769  * The value programmed in this register must be lesser than the value programmed
36770  * in Register 472 (PPS0 Interval Register).
36771  *
36772  * Field Access Macros:
36773  *
36774  */
36775 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field. */
36776 #define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_LSB 0
36777 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field. */
36778 #define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_MSB 31
36779 /* The width in bits of the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field. */
36780 #define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_WIDTH 32
36781 /* The mask used to set the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field value. */
36782 #define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_SET_MSK 0xffffffff
36783 /* The mask used to clear the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field value. */
36784 #define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_CLR_MSK 0x00000000
36785 /* The reset value of the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field. */
36786 #define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_RESET 0x0
36787 /* Extracts the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH field value from a register. */
36788 #define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_GET(value) (((value) & 0xffffffff) >> 0)
36789 /* Produces a ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field value suitable for setting the register. */
36790 #define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_SET(value) (((value) << 0) & 0xffffffff)
36791 
36792 #ifndef __ASSEMBLY__
36793 /*
36794  * WARNING: The C register and register group struct declarations are provided for
36795  * convenience and illustrative purposes. They should, however, be used with
36796  * caution as the C language standard provides no guarantees about the alignment or
36797  * atomicity of device memory accesses. The recommended practice for writing
36798  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
36799  * alt_write_word() functions.
36800  *
36801  * The struct declaration for register ALT_EMAC_GMAC_PPS0_WIDTH.
36802  */
36803 struct ALT_EMAC_GMAC_PPS0_WIDTH_s
36804 {
36805  uint32_t ppswidth : 32; /* PPS0 Output Signal Width */
36806 };
36807 
36808 /* The typedef declaration for register ALT_EMAC_GMAC_PPS0_WIDTH. */
36809 typedef volatile struct ALT_EMAC_GMAC_PPS0_WIDTH_s ALT_EMAC_GMAC_PPS0_WIDTH_t;
36810 #endif /* __ASSEMBLY__ */
36811 
36812 /* The reset value of the ALT_EMAC_GMAC_PPS0_WIDTH register. */
36813 #define ALT_EMAC_GMAC_PPS0_WIDTH_RESET 0x00000000
36814 /* The byte offset of the ALT_EMAC_GMAC_PPS0_WIDTH register from the beginning of the component. */
36815 #define ALT_EMAC_GMAC_PPS0_WIDTH_OFST 0x764
36816 /* The address of the ALT_EMAC_GMAC_PPS0_WIDTH register. */
36817 #define ALT_EMAC_GMAC_PPS0_WIDTH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_PPS0_WIDTH_OFST))
36818 
36819 /*
36820  * Register : gmacgrp_mac_address16_high
36821  *
36822  * <b> Register 512 (MAC Address16 High Register) </b>
36823  *
36824  * The MAC Address16 High register holds the upper 16 bits of the 17th 6-byte MAC
36825  * address of the station.
36826  *
36827  * If the MAC address registers are configured to be double-synchronized to the
36828  * (G)MII clock domains, then
36829  *
36830  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
36831  * or Bits[7:0] (in big-endian mode) of the MAC Address16 Low Register are written.
36832  * For proper synchronization updates, consecutive writes to this MAC Address16 Low
36833  * Register must be performed after at least four clock cycles in the destination
36834  * clock domain.
36835  *
36836  * Register Layout
36837  *
36838  * Bits | Access | Reset | Description
36839  * :--------|:-------|:-------|:-----------------------------------------
36840  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI
36841  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR16_HIGH_RSVD_23_16
36842  * [24] | RW | 0x0 | Mask Byte Control
36843  * [25] | RW | 0x0 | Mask Byte Control
36844  * [26] | RW | 0x0 | Mask Byte Control
36845  * [27] | RW | 0x0 | Mask Byte Control
36846  * [28] | RW | 0x0 | Mask Byte Control
36847  * [29] | RW | 0x0 | Mask Byte Control
36848  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA
36849  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE
36850  *
36851  */
36852 /*
36853  * Field : addrhi
36854  *
36855  * MAC Address16 [47:32]
36856  *
36857  * This field contains the upper 16 bits (47:32) of the 17th 6-byte MAC address.
36858  *
36859  * Field Access Macros:
36860  *
36861  */
36862 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field. */
36863 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_LSB 0
36864 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field. */
36865 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_MSB 15
36866 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field. */
36867 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_WIDTH 16
36868 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field value. */
36869 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_SET_MSK 0x0000ffff
36870 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field value. */
36871 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_CLR_MSK 0xffff0000
36872 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field. */
36873 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_RESET 0xffff
36874 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI field value from a register. */
36875 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
36876 /* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field value suitable for setting the register. */
36877 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
36878 
36879 /*
36880  * Field : reserved_23_16
36881  *
36882  * Reserved
36883  *
36884  * Field Access Macros:
36885  *
36886  */
36887 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_RSVD_23_16 register field. */
36888 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_RSVD_23_16_LSB 16
36889 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_RSVD_23_16 register field. */
36890 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_RSVD_23_16_MSB 23
36891 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_RSVD_23_16 register field. */
36892 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_RSVD_23_16_WIDTH 8
36893 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_RSVD_23_16 register field value. */
36894 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
36895 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_RSVD_23_16 register field value. */
36896 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
36897 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_RSVD_23_16 register field. */
36898 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_RSVD_23_16_RESET 0x0
36899 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_RSVD_23_16 field value from a register. */
36900 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
36901 /* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_RSVD_23_16 register field value suitable for setting the register. */
36902 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
36903 
36904 /*
36905  * Field : Mask Byte Control - mbc_0
36906  *
36907  * This array of bits are mask control bits for comparison of each of the MAC
36908  * Address bytes. When masked, the MAC does not compare the corresponding byte of
36909  * received DA or SA with the contents of MAC Address16 high and low registers.
36910  * Each bit controls the masking of the bytes. You can filter a group of addresses
36911  * (known as group address filtering) by masking one or more bytes of the address.
36912  *
36913  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
36914  *
36915  * Field Enumeration Values:
36916  *
36917  * Enum | Value | Description
36918  * :----------------------------------------------|:------|:------------
36919  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_E_UNMSKED | 0x0 |
36920  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_E_MSKED | 0x1 |
36921  *
36922  * Field Access Macros:
36923  *
36924  */
36925 /*
36926  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0
36927  *
36928  */
36929 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_E_UNMSKED 0x0
36930 /*
36931  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0
36932  *
36933  */
36934 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_E_MSKED 0x1
36935 
36936 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field. */
36937 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_LSB 24
36938 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field. */
36939 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_MSB 24
36940 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field. */
36941 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_WIDTH 1
36942 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field value. */
36943 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_SET_MSK 0x01000000
36944 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field value. */
36945 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_CLR_MSK 0xfeffffff
36946 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field. */
36947 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_RESET 0x0
36948 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 field value from a register. */
36949 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
36950 /* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field value suitable for setting the register. */
36951 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
36952 
36953 /*
36954  * Field : Mask Byte Control - mbc_1
36955  *
36956  * This array of bits are mask control bits for comparison of each of the MAC
36957  * Address bytes. When masked, the MAC does not compare the corresponding byte of
36958  * received DA or SA with the contents of MAC Address16 high and low registers.
36959  * Each bit controls the masking of the bytes. You can filter a group of addresses
36960  * (known as group address filtering) by masking one or more bytes of the address.
36961  *
36962  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
36963  *
36964  * Field Enumeration Values:
36965  *
36966  * Enum | Value | Description
36967  * :----------------------------------------------|:------|:------------
36968  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_E_UNMSKED | 0x0 |
36969  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_E_MSKED | 0x1 |
36970  *
36971  * Field Access Macros:
36972  *
36973  */
36974 /*
36975  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1
36976  *
36977  */
36978 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_E_UNMSKED 0x0
36979 /*
36980  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1
36981  *
36982  */
36983 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_E_MSKED 0x1
36984 
36985 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field. */
36986 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_LSB 25
36987 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field. */
36988 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_MSB 25
36989 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field. */
36990 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_WIDTH 1
36991 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field value. */
36992 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_SET_MSK 0x02000000
36993 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field value. */
36994 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_CLR_MSK 0xfdffffff
36995 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field. */
36996 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_RESET 0x0
36997 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 field value from a register. */
36998 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
36999 /* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field value suitable for setting the register. */
37000 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
37001 
37002 /*
37003  * Field : Mask Byte Control - mbc_2
37004  *
37005  * This array of bits are mask control bits for comparison of each of the MAC
37006  * Address bytes. When masked, the MAC does not compare the corresponding byte of
37007  * received DA or SA with the contents of MAC Address16 high and low registers.
37008  * Each bit controls the masking of the bytes. You can filter a group of addresses
37009  * (known as group address filtering) by masking one or more bytes of the address.
37010  *
37011  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
37012  *
37013  * Field Enumeration Values:
37014  *
37015  * Enum | Value | Description
37016  * :----------------------------------------------|:------|:------------
37017  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_E_UNMSKED | 0x0 |
37018  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_E_MSKED | 0x1 |
37019  *
37020  * Field Access Macros:
37021  *
37022  */
37023 /*
37024  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2
37025  *
37026  */
37027 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_E_UNMSKED 0x0
37028 /*
37029  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2
37030  *
37031  */
37032 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_E_MSKED 0x1
37033 
37034 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field. */
37035 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_LSB 26
37036 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field. */
37037 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_MSB 26
37038 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field. */
37039 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_WIDTH 1
37040 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field value. */
37041 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_SET_MSK 0x04000000
37042 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field value. */
37043 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_CLR_MSK 0xfbffffff
37044 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field. */
37045 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_RESET 0x0
37046 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 field value from a register. */
37047 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
37048 /* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field value suitable for setting the register. */
37049 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
37050 
37051 /*
37052  * Field : Mask Byte Control - mbc_3
37053  *
37054  * This array of bits are mask control bits for comparison of each of the MAC
37055  * Address bytes. When masked, the MAC does not compare the corresponding byte of
37056  * received DA or SA with the contents of MAC Address16 high and low registers.
37057  * Each bit controls the masking of the bytes. You can filter a group of addresses
37058  * (known as group address filtering) by masking one or more bytes of the address.
37059  *
37060  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
37061  *
37062  * Field Enumeration Values:
37063  *
37064  * Enum | Value | Description
37065  * :----------------------------------------------|:------|:------------
37066  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_E_UNMSKED | 0x0 |
37067  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_E_MSKED | 0x1 |
37068  *
37069  * Field Access Macros:
37070  *
37071  */
37072 /*
37073  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3
37074  *
37075  */
37076 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_E_UNMSKED 0x0
37077 /*
37078  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3
37079  *
37080  */
37081 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_E_MSKED 0x1
37082 
37083 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field. */
37084 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_LSB 27
37085 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field. */
37086 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_MSB 27
37087 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field. */
37088 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_WIDTH 1
37089 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field value. */
37090 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_SET_MSK 0x08000000
37091 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field value. */
37092 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_CLR_MSK 0xf7ffffff
37093 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field. */
37094 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_RESET 0x0
37095 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 field value from a register. */
37096 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
37097 /* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field value suitable for setting the register. */
37098 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
37099 
37100 /*
37101  * Field : Mask Byte Control - mbc_4
37102  *
37103  * This array of bits are mask control bits for comparison of each of the MAC
37104  * Address bytes. When masked, the MAC does not compare the corresponding byte of
37105  * received DA or SA with the contents of MAC Address16 high and low registers.
37106  * Each bit controls the masking of the bytes. You can filter a group of addresses
37107  * (known as group address filtering) by masking one or more bytes of the address.
37108  *
37109  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
37110  *
37111  * Field Enumeration Values:
37112  *
37113  * Enum | Value | Description
37114  * :----------------------------------------------|:------|:------------
37115  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_E_UNMSKED | 0x0 |
37116  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_E_MSKED | 0x1 |
37117  *
37118  * Field Access Macros:
37119  *
37120  */
37121 /*
37122  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4
37123  *
37124  */
37125 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_E_UNMSKED 0x0
37126 /*
37127  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4
37128  *
37129  */
37130 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_E_MSKED 0x1
37131 
37132 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field. */
37133 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_LSB 28
37134 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field. */
37135 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_MSB 28
37136 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field. */
37137 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_WIDTH 1
37138 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field value. */
37139 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_SET_MSK 0x10000000
37140 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field value. */
37141 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_CLR_MSK 0xefffffff
37142 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field. */
37143 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_RESET 0x0
37144 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 field value from a register. */
37145 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
37146 /* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field value suitable for setting the register. */
37147 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
37148 
37149 /*
37150  * Field : Mask Byte Control - mbc_5
37151  *
37152  * This array of bits are mask control bits for comparison of each of the MAC
37153  * Address bytes. When masked, the MAC does not compare the corresponding byte of
37154  * received DA or SA with the contents of MAC Address16 high and low registers.
37155  * Each bit controls the masking of the bytes. You can filter a group of addresses
37156  * (known as group address filtering) by masking one or more bytes of the address.
37157  *
37158  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
37159  *
37160  * Field Enumeration Values:
37161  *
37162  * Enum | Value | Description
37163  * :----------------------------------------------|:------|:------------
37164  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_E_UNMSKED | 0x0 |
37165  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_E_MSKED | 0x1 |
37166  *
37167  * Field Access Macros:
37168  *
37169  */
37170 /*
37171  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5
37172  *
37173  */
37174 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_E_UNMSKED 0x0
37175 /*
37176  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5
37177  *
37178  */
37179 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_E_MSKED 0x1
37180 
37181 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field. */
37182 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_LSB 29
37183 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field. */
37184 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_MSB 29
37185 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field. */
37186 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_WIDTH 1
37187 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field value. */
37188 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_SET_MSK 0x20000000
37189 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field value. */
37190 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_CLR_MSK 0xdfffffff
37191 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field. */
37192 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_RESET 0x0
37193 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 field value from a register. */
37194 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
37195 /* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field value suitable for setting the register. */
37196 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
37197 
37198 /*
37199  * Field : sa
37200  *
37201  * Source Address
37202  *
37203  * When this bit is set, the MAC Address16[47:0] is used to compare with the SA
37204  * fields of the received frame. When this bit is reset, the MAC Address16[47:0] is
37205  * used to compare with the DA fields of the received frame.
37206  *
37207  * Field Enumeration Values:
37208  *
37209  * Enum | Value | Description
37210  * :----------------------------------------|:------|:------------
37211  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_E_DISD | 0x0 |
37212  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_E_END | 0x1 |
37213  *
37214  * Field Access Macros:
37215  *
37216  */
37217 /*
37218  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA
37219  *
37220  */
37221 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_E_DISD 0x0
37222 /*
37223  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA
37224  *
37225  */
37226 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_E_END 0x1
37227 
37228 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field. */
37229 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_LSB 30
37230 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field. */
37231 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_MSB 30
37232 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field. */
37233 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_WIDTH 1
37234 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field value. */
37235 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_SET_MSK 0x40000000
37236 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field value. */
37237 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_CLR_MSK 0xbfffffff
37238 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field. */
37239 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_RESET 0x0
37240 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA field value from a register. */
37241 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
37242 /* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field value suitable for setting the register. */
37243 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
37244 
37245 /*
37246  * Field : ae
37247  *
37248  * Address Enable
37249  *
37250  * When this bit is set, the address filter module uses the 17th MAC address for
37251  * perfect filtering.
37252  *
37253  * When this bit is reset, the address filter module ignores the address for
37254  * filtering.
37255  *
37256  * Field Enumeration Values:
37257  *
37258  * Enum | Value | Description
37259  * :----------------------------------------|:------|:------------
37260  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_E_DISD | 0x0 |
37261  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_E_END | 0x1 |
37262  *
37263  * Field Access Macros:
37264  *
37265  */
37266 /*
37267  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE
37268  *
37269  */
37270 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_E_DISD 0x0
37271 /*
37272  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE
37273  *
37274  */
37275 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_E_END 0x1
37276 
37277 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field. */
37278 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_LSB 31
37279 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field. */
37280 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_MSB 31
37281 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field. */
37282 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_WIDTH 1
37283 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field value. */
37284 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_SET_MSK 0x80000000
37285 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field value. */
37286 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_CLR_MSK 0x7fffffff
37287 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field. */
37288 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_RESET 0x0
37289 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE field value from a register. */
37290 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
37291 /* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field value suitable for setting the register. */
37292 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
37293 
37294 #ifndef __ASSEMBLY__
37295 /*
37296  * WARNING: The C register and register group struct declarations are provided for
37297  * convenience and illustrative purposes. They should, however, be used with
37298  * caution as the C language standard provides no guarantees about the alignment or
37299  * atomicity of device memory accesses. The recommended practice for writing
37300  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
37301  * alt_write_word() functions.
37302  *
37303  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR16_HIGH.
37304  */
37305 struct ALT_EMAC_GMAC_MAC_ADDR16_HIGH_s
37306 {
37307  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI */
37308  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR16_HIGH_RSVD_23_16 */
37309  uint32_t mbc_0 : 1; /* Mask Byte Control */
37310  uint32_t mbc_1 : 1; /* Mask Byte Control */
37311  uint32_t mbc_2 : 1; /* Mask Byte Control */
37312  uint32_t mbc_3 : 1; /* Mask Byte Control */
37313  uint32_t mbc_4 : 1; /* Mask Byte Control */
37314  uint32_t mbc_5 : 1; /* Mask Byte Control */
37315  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA */
37316  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE */
37317 };
37318 
37319 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR16_HIGH. */
37320 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR16_HIGH_s ALT_EMAC_GMAC_MAC_ADDR16_HIGH_t;
37321 #endif /* __ASSEMBLY__ */
37322 
37323 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH register. */
37324 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_RESET 0x0000ffff
37325 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH register from the beginning of the component. */
37326 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_OFST 0x800
37327 /* The address of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH register. */
37328 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR16_HIGH_OFST))
37329 
37330 /*
37331  * Register : gmacgrp_mac_address16_low
37332  *
37333  * <b> Register 513 (MAC Address16 Low Register) </b>
37334  *
37335  * The MAC Address16 Low register holds the lower 32 bits of the 17th 6-byte MAC
37336  * address of the station.
37337  *
37338  * Register Layout
37339  *
37340  * Bits | Access | Reset | Description
37341  * :-------|:-------|:-----------|:------------------------------------
37342  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO
37343  *
37344  */
37345 /*
37346  * Field : addrlo
37347  *
37348  * MAC Address16 [31:0]
37349  *
37350  * This field contains the lower 32 bits of the 17th 6-byte MAC address. The
37351  * content of this field is undefined until loaded by the Application after the
37352  * initialization process.
37353  *
37354  * Field Access Macros:
37355  *
37356  */
37357 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field. */
37358 #define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_LSB 0
37359 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field. */
37360 #define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_MSB 31
37361 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field. */
37362 #define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_WIDTH 32
37363 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field value. */
37364 #define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_SET_MSK 0xffffffff
37365 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field value. */
37366 #define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_CLR_MSK 0x00000000
37367 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field. */
37368 #define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_RESET 0xffffffff
37369 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO field value from a register. */
37370 #define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
37371 /* Produces a ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field value suitable for setting the register. */
37372 #define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
37373 
37374 #ifndef __ASSEMBLY__
37375 /*
37376  * WARNING: The C register and register group struct declarations are provided for
37377  * convenience and illustrative purposes. They should, however, be used with
37378  * caution as the C language standard provides no guarantees about the alignment or
37379  * atomicity of device memory accesses. The recommended practice for writing
37380  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
37381  * alt_write_word() functions.
37382  *
37383  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR16_LOW.
37384  */
37385 struct ALT_EMAC_GMAC_MAC_ADDR16_LOW_s
37386 {
37387  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO */
37388 };
37389 
37390 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR16_LOW. */
37391 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR16_LOW_s ALT_EMAC_GMAC_MAC_ADDR16_LOW_t;
37392 #endif /* __ASSEMBLY__ */
37393 
37394 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_LOW register. */
37395 #define ALT_EMAC_GMAC_MAC_ADDR16_LOW_RESET 0xffffffff
37396 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR16_LOW register from the beginning of the component. */
37397 #define ALT_EMAC_GMAC_MAC_ADDR16_LOW_OFST 0x804
37398 /* The address of the ALT_EMAC_GMAC_MAC_ADDR16_LOW register. */
37399 #define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR16_LOW_OFST))
37400 
37401 /*
37402  * Register : gmacgrp_mac_address17_high
37403  *
37404  * <b> Register 514 (MAC Address17 High Register) </b>
37405  *
37406  * The MAC Address17 High register holds the upper 16 bits of the 18th 6-byte MAC
37407  * address of the station.
37408  *
37409  * If the MAC address registers are configured to be double-synchronized to the
37410  * (G)MII clock domains, then
37411  *
37412  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
37413  * or Bits[7:0] (in big-endian mode) of the MAC Address17 Low Register are written.
37414  * For proper synchronization updates, consecutive writes to this MAC Address17 Low
37415  * Register must be performed after at least four clock cycles in the destination
37416  * clock domain.
37417  *
37418  * Register Layout
37419  *
37420  * Bits | Access | Reset | Description
37421  * :--------|:-------|:-------|:-----------------------------------------
37422  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI
37423  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR17_HIGH_RSVD_23_16
37424  * [24] | RW | 0x0 | Mask Byte Control
37425  * [25] | RW | 0x0 | Mask Byte Control
37426  * [26] | RW | 0x0 | Mask Byte Control
37427  * [27] | RW | 0x0 | Mask Byte Control
37428  * [28] | RW | 0x0 | Mask Byte Control
37429  * [29] | RW | 0x0 | Mask Byte Control
37430  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA
37431  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE
37432  *
37433  */
37434 /*
37435  * Field : addrhi
37436  *
37437  * MAC Address18 [47:32]
37438  *
37439  * This field contains the upper 16 bits (47:32) of the 19th 6-byte MAC address.
37440  *
37441  * Field Access Macros:
37442  *
37443  */
37444 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field. */
37445 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_LSB 0
37446 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field. */
37447 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_MSB 15
37448 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field. */
37449 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_WIDTH 16
37450 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field value. */
37451 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_SET_MSK 0x0000ffff
37452 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field value. */
37453 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_CLR_MSK 0xffff0000
37454 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field. */
37455 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_RESET 0xffff
37456 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI field value from a register. */
37457 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
37458 /* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field value suitable for setting the register. */
37459 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
37460 
37461 /*
37462  * Field : reserved_23_16
37463  *
37464  * Reserved
37465  *
37466  * Field Access Macros:
37467  *
37468  */
37469 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_RSVD_23_16 register field. */
37470 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_RSVD_23_16_LSB 16
37471 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_RSVD_23_16 register field. */
37472 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_RSVD_23_16_MSB 23
37473 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_RSVD_23_16 register field. */
37474 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_RSVD_23_16_WIDTH 8
37475 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_RSVD_23_16 register field value. */
37476 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
37477 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_RSVD_23_16 register field value. */
37478 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
37479 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_RSVD_23_16 register field. */
37480 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_RSVD_23_16_RESET 0x0
37481 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_RSVD_23_16 field value from a register. */
37482 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
37483 /* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_RSVD_23_16 register field value suitable for setting the register. */
37484 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
37485 
37486 /*
37487  * Field : Mask Byte Control - mbc_0
37488  *
37489  * This array of bits are mask control bits for comparison of each of the MAC
37490  * Address bytes. When masked, the MAC does not compare the corresponding byte of
37491  * received DA or SA with the contents of MAC Address17 high and low registers.
37492  * Each bit controls the masking of the bytes. You can filter a group of addresses
37493  * (known as group address filtering) by masking one or more bytes of the address.
37494  *
37495  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
37496  *
37497  * Field Enumeration Values:
37498  *
37499  * Enum | Value | Description
37500  * :----------------------------------------------|:------|:------------
37501  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_E_UNMSKED | 0x0 |
37502  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_E_MSKED | 0x1 |
37503  *
37504  * Field Access Macros:
37505  *
37506  */
37507 /*
37508  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0
37509  *
37510  */
37511 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_E_UNMSKED 0x0
37512 /*
37513  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0
37514  *
37515  */
37516 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_E_MSKED 0x1
37517 
37518 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field. */
37519 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_LSB 24
37520 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field. */
37521 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_MSB 24
37522 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field. */
37523 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_WIDTH 1
37524 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field value. */
37525 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_SET_MSK 0x01000000
37526 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field value. */
37527 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_CLR_MSK 0xfeffffff
37528 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field. */
37529 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_RESET 0x0
37530 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 field value from a register. */
37531 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
37532 /* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field value suitable for setting the register. */
37533 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
37534 
37535 /*
37536  * Field : Mask Byte Control - mbc_1
37537  *
37538  * This array of bits are mask control bits for comparison of each of the MAC
37539  * Address bytes. When masked, the MAC does not compare the corresponding byte of
37540  * received DA or SA with the contents of MAC Address17 high and low registers.
37541  * Each bit controls the masking of the bytes. You can filter a group of addresses
37542  * (known as group address filtering) by masking one or more bytes of the address.
37543  *
37544  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
37545  *
37546  * Field Enumeration Values:
37547  *
37548  * Enum | Value | Description
37549  * :----------------------------------------------|:------|:------------
37550  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_E_UNMSKED | 0x0 |
37551  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_E_MSKED | 0x1 |
37552  *
37553  * Field Access Macros:
37554  *
37555  */
37556 /*
37557  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1
37558  *
37559  */
37560 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_E_UNMSKED 0x0
37561 /*
37562  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1
37563  *
37564  */
37565 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_E_MSKED 0x1
37566 
37567 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field. */
37568 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_LSB 25
37569 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field. */
37570 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_MSB 25
37571 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field. */
37572 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_WIDTH 1
37573 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field value. */
37574 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_SET_MSK 0x02000000
37575 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field value. */
37576 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_CLR_MSK 0xfdffffff
37577 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field. */
37578 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_RESET 0x0
37579 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 field value from a register. */
37580 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
37581 /* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field value suitable for setting the register. */
37582 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
37583 
37584 /*
37585  * Field : Mask Byte Control - mbc_2
37586  *
37587  * This array of bits are mask control bits for comparison of each of the MAC
37588  * Address bytes. When masked, the MAC does not compare the corresponding byte of
37589  * received DA or SA with the contents of MAC Address17 high and low registers.
37590  * Each bit controls the masking of the bytes. You can filter a group of addresses
37591  * (known as group address filtering) by masking one or more bytes of the address.
37592  *
37593  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
37594  *
37595  * Field Enumeration Values:
37596  *
37597  * Enum | Value | Description
37598  * :----------------------------------------------|:------|:------------
37599  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_E_UNMSKED | 0x0 |
37600  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_E_MSKED | 0x1 |
37601  *
37602  * Field Access Macros:
37603  *
37604  */
37605 /*
37606  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2
37607  *
37608  */
37609 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_E_UNMSKED 0x0
37610 /*
37611  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2
37612  *
37613  */
37614 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_E_MSKED 0x1
37615 
37616 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field. */
37617 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_LSB 26
37618 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field. */
37619 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_MSB 26
37620 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field. */
37621 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_WIDTH 1
37622 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field value. */
37623 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_SET_MSK 0x04000000
37624 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field value. */
37625 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_CLR_MSK 0xfbffffff
37626 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field. */
37627 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_RESET 0x0
37628 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 field value from a register. */
37629 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
37630 /* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field value suitable for setting the register. */
37631 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
37632 
37633 /*
37634  * Field : Mask Byte Control - mbc_3
37635  *
37636  * This array of bits are mask control bits for comparison of each of the MAC
37637  * Address bytes. When masked, the MAC does not compare the corresponding byte of
37638  * received DA or SA with the contents of MAC Address17 high and low registers.
37639  * Each bit controls the masking of the bytes. You can filter a group of addresses
37640  * (known as group address filtering) by masking one or more bytes of the address.
37641  *
37642  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
37643  *
37644  * Field Enumeration Values:
37645  *
37646  * Enum | Value | Description
37647  * :----------------------------------------------|:------|:------------
37648  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_E_UNMSKED | 0x0 |
37649  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_E_MSKED | 0x1 |
37650  *
37651  * Field Access Macros:
37652  *
37653  */
37654 /*
37655  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3
37656  *
37657  */
37658 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_E_UNMSKED 0x0
37659 /*
37660  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3
37661  *
37662  */
37663 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_E_MSKED 0x1
37664 
37665 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field. */
37666 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_LSB 27
37667 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field. */
37668 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_MSB 27
37669 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field. */
37670 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_WIDTH 1
37671 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field value. */
37672 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_SET_MSK 0x08000000
37673 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field value. */
37674 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_CLR_MSK 0xf7ffffff
37675 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field. */
37676 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_RESET 0x0
37677 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 field value from a register. */
37678 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
37679 /* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field value suitable for setting the register. */
37680 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
37681 
37682 /*
37683  * Field : Mask Byte Control - mbc_4
37684  *
37685  * This array of bits are mask control bits for comparison of each of the MAC
37686  * Address bytes. When masked, the MAC does not compare the corresponding byte of
37687  * received DA or SA with the contents of MAC Address17 high and low registers.
37688  * Each bit controls the masking of the bytes. You can filter a group of addresses
37689  * (known as group address filtering) by masking one or more bytes of the address.
37690  *
37691  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
37692  *
37693  * Field Enumeration Values:
37694  *
37695  * Enum | Value | Description
37696  * :----------------------------------------------|:------|:------------
37697  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_E_UNMSKED | 0x0 |
37698  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_E_MSKED | 0x1 |
37699  *
37700  * Field Access Macros:
37701  *
37702  */
37703 /*
37704  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4
37705  *
37706  */
37707 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_E_UNMSKED 0x0
37708 /*
37709  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4
37710  *
37711  */
37712 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_E_MSKED 0x1
37713 
37714 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field. */
37715 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_LSB 28
37716 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field. */
37717 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_MSB 28
37718 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field. */
37719 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_WIDTH 1
37720 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field value. */
37721 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_SET_MSK 0x10000000
37722 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field value. */
37723 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_CLR_MSK 0xefffffff
37724 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field. */
37725 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_RESET 0x0
37726 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 field value from a register. */
37727 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
37728 /* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field value suitable for setting the register. */
37729 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
37730 
37731 /*
37732  * Field : Mask Byte Control - mbc_5
37733  *
37734  * This array of bits are mask control bits for comparison of each of the MAC
37735  * Address bytes. When masked, the MAC does not compare the corresponding byte of
37736  * received DA or SA with the contents of MAC Address17 high and low registers.
37737  * Each bit controls the masking of the bytes. You can filter a group of addresses
37738  * (known as group address filtering) by masking one or more bytes of the address.
37739  *
37740  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
37741  *
37742  * Field Enumeration Values:
37743  *
37744  * Enum | Value | Description
37745  * :----------------------------------------------|:------|:------------
37746  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_E_UNMSKED | 0x0 |
37747  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_E_MSKED | 0x1 |
37748  *
37749  * Field Access Macros:
37750  *
37751  */
37752 /*
37753  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5
37754  *
37755  */
37756 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_E_UNMSKED 0x0
37757 /*
37758  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5
37759  *
37760  */
37761 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_E_MSKED 0x1
37762 
37763 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field. */
37764 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_LSB 29
37765 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field. */
37766 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_MSB 29
37767 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field. */
37768 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_WIDTH 1
37769 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field value. */
37770 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_SET_MSK 0x20000000
37771 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field value. */
37772 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_CLR_MSK 0xdfffffff
37773 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field. */
37774 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_RESET 0x0
37775 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 field value from a register. */
37776 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
37777 /* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field value suitable for setting the register. */
37778 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
37779 
37780 /*
37781  * Field : sa
37782  *
37783  * Source Address
37784  *
37785  * When this bit is set, the MAC Address17[47:0] is used to compare with the SA
37786  * fields of the received frame.
37787  *
37788  * When this bit is reset, the MAC Address17[47:0] is used to compare with the DA
37789  * fields of the received frame.
37790  *
37791  * Field Enumeration Values:
37792  *
37793  * Enum | Value | Description
37794  * :----------------------------------------|:------|:------------
37795  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_E_DISD | 0x0 |
37796  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_E_END | 0x1 |
37797  *
37798  * Field Access Macros:
37799  *
37800  */
37801 /*
37802  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA
37803  *
37804  */
37805 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_E_DISD 0x0
37806 /*
37807  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA
37808  *
37809  */
37810 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_E_END 0x1
37811 
37812 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field. */
37813 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_LSB 30
37814 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field. */
37815 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_MSB 30
37816 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field. */
37817 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_WIDTH 1
37818 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field value. */
37819 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_SET_MSK 0x40000000
37820 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field value. */
37821 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_CLR_MSK 0xbfffffff
37822 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field. */
37823 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_RESET 0x0
37824 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA field value from a register. */
37825 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
37826 /* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field value suitable for setting the register. */
37827 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
37828 
37829 /*
37830  * Field : ae
37831  *
37832  * Address Enable
37833  *
37834  * When this bit is set, the address filter module uses the 18th MAC address for
37835  * perfect filtering.
37836  *
37837  * When this bit is reset, the address filter module ignores the address for
37838  * filtering.
37839  *
37840  * Field Enumeration Values:
37841  *
37842  * Enum | Value | Description
37843  * :----------------------------------------|:------|:------------
37844  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_E_DISD | 0x0 |
37845  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_E_END | 0x1 |
37846  *
37847  * Field Access Macros:
37848  *
37849  */
37850 /*
37851  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE
37852  *
37853  */
37854 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_E_DISD 0x0
37855 /*
37856  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE
37857  *
37858  */
37859 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_E_END 0x1
37860 
37861 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field. */
37862 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_LSB 31
37863 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field. */
37864 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_MSB 31
37865 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field. */
37866 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_WIDTH 1
37867 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field value. */
37868 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_SET_MSK 0x80000000
37869 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field value. */
37870 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_CLR_MSK 0x7fffffff
37871 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field. */
37872 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_RESET 0x0
37873 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE field value from a register. */
37874 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
37875 /* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field value suitable for setting the register. */
37876 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
37877 
37878 #ifndef __ASSEMBLY__
37879 /*
37880  * WARNING: The C register and register group struct declarations are provided for
37881  * convenience and illustrative purposes. They should, however, be used with
37882  * caution as the C language standard provides no guarantees about the alignment or
37883  * atomicity of device memory accesses. The recommended practice for writing
37884  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
37885  * alt_write_word() functions.
37886  *
37887  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR17_HIGH.
37888  */
37889 struct ALT_EMAC_GMAC_MAC_ADDR17_HIGH_s
37890 {
37891  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI */
37892  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR17_HIGH_RSVD_23_16 */
37893  uint32_t mbc_0 : 1; /* Mask Byte Control */
37894  uint32_t mbc_1 : 1; /* Mask Byte Control */
37895  uint32_t mbc_2 : 1; /* Mask Byte Control */
37896  uint32_t mbc_3 : 1; /* Mask Byte Control */
37897  uint32_t mbc_4 : 1; /* Mask Byte Control */
37898  uint32_t mbc_5 : 1; /* Mask Byte Control */
37899  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA */
37900  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE */
37901 };
37902 
37903 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR17_HIGH. */
37904 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR17_HIGH_s ALT_EMAC_GMAC_MAC_ADDR17_HIGH_t;
37905 #endif /* __ASSEMBLY__ */
37906 
37907 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH register. */
37908 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_RESET 0x0000ffff
37909 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH register from the beginning of the component. */
37910 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_OFST 0x808
37911 /* The address of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH register. */
37912 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR17_HIGH_OFST))
37913 
37914 /*
37915  * Register : gmacgrp_mac_address17_low
37916  *
37917  * <b> Register 515 (MAC Address17 Low Register) </b>
37918  *
37919  * The MAC Address17 Low register holds the lower 32 bits of the 18th 6-byte MAC
37920  * address of the station.
37921  *
37922  * Register Layout
37923  *
37924  * Bits | Access | Reset | Description
37925  * :-------|:-------|:-----------|:------------------------------------
37926  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO
37927  *
37928  */
37929 /*
37930  * Field : addrlo
37931  *
37932  * MAC Address17 [31:0]
37933  *
37934  * This field contains the lower 32 bits of the 18th 6-byte MAC address. The
37935  * content of this field is undefined until loaded by the Application after the
37936  * initialization process.
37937  *
37938  * Field Access Macros:
37939  *
37940  */
37941 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field. */
37942 #define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_LSB 0
37943 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field. */
37944 #define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_MSB 31
37945 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field. */
37946 #define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_WIDTH 32
37947 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field value. */
37948 #define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_SET_MSK 0xffffffff
37949 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field value. */
37950 #define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_CLR_MSK 0x00000000
37951 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field. */
37952 #define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_RESET 0xffffffff
37953 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO field value from a register. */
37954 #define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
37955 /* Produces a ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field value suitable for setting the register. */
37956 #define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
37957 
37958 #ifndef __ASSEMBLY__
37959 /*
37960  * WARNING: The C register and register group struct declarations are provided for
37961  * convenience and illustrative purposes. They should, however, be used with
37962  * caution as the C language standard provides no guarantees about the alignment or
37963  * atomicity of device memory accesses. The recommended practice for writing
37964  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
37965  * alt_write_word() functions.
37966  *
37967  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR17_LOW.
37968  */
37969 struct ALT_EMAC_GMAC_MAC_ADDR17_LOW_s
37970 {
37971  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO */
37972 };
37973 
37974 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR17_LOW. */
37975 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR17_LOW_s ALT_EMAC_GMAC_MAC_ADDR17_LOW_t;
37976 #endif /* __ASSEMBLY__ */
37977 
37978 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_LOW register. */
37979 #define ALT_EMAC_GMAC_MAC_ADDR17_LOW_RESET 0xffffffff
37980 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR17_LOW register from the beginning of the component. */
37981 #define ALT_EMAC_GMAC_MAC_ADDR17_LOW_OFST 0x80c
37982 /* The address of the ALT_EMAC_GMAC_MAC_ADDR17_LOW register. */
37983 #define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR17_LOW_OFST))
37984 
37985 /*
37986  * Register : gmacgrp_mac_address18_high
37987  *
37988  * <b> Register 516 (MAC Address18 High Register) </b>
37989  *
37990  * The MAC Address18 High register holds the upper 16 bits of the 19th 6-byte MAC
37991  * address of the station.
37992  *
37993  * If the MAC address registers are configured to be double-synchronized to the
37994  * (G)MII clock domains, then
37995  *
37996  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
37997  * or Bits[7:0] (in big-endian mode) of the MAC Address18 Low Register are written.
37998  * For proper synchronization updates, consecutive writes to this MAC Address18 Low
37999  * Register must be performed after at least four clock cycles in the destination
38000  * clock domain.
38001  *
38002  * Register Layout
38003  *
38004  * Bits | Access | Reset | Description
38005  * :--------|:-------|:-------|:-----------------------------------------
38006  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI
38007  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR18_HIGH_RSVD_23_16
38008  * [24] | RW | 0x0 | Mask Byte Control
38009  * [25] | RW | 0x0 | Mask Byte Control
38010  * [26] | RW | 0x0 | Mask Byte Control
38011  * [27] | RW | 0x0 | Mask Byte Control
38012  * [28] | RW | 0x0 | Mask Byte Control
38013  * [29] | RW | 0x0 | Mask Byte Control
38014  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA
38015  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE
38016  *
38017  */
38018 /*
38019  * Field : addrhi
38020  *
38021  * MAC Address18 [47:32]
38022  *
38023  * This field contains the upper 16 bits (47:32) of the 19th 6-byte MAC address.
38024  *
38025  * Field Access Macros:
38026  *
38027  */
38028 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field. */
38029 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_LSB 0
38030 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field. */
38031 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_MSB 15
38032 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field. */
38033 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_WIDTH 16
38034 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field value. */
38035 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_SET_MSK 0x0000ffff
38036 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field value. */
38037 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_CLR_MSK 0xffff0000
38038 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field. */
38039 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_RESET 0xffff
38040 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI field value from a register. */
38041 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
38042 /* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field value suitable for setting the register. */
38043 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
38044 
38045 /*
38046  * Field : reserved_23_16
38047  *
38048  * Reserved
38049  *
38050  * Field Access Macros:
38051  *
38052  */
38053 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_RSVD_23_16 register field. */
38054 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_RSVD_23_16_LSB 16
38055 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_RSVD_23_16 register field. */
38056 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_RSVD_23_16_MSB 23
38057 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_RSVD_23_16 register field. */
38058 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_RSVD_23_16_WIDTH 8
38059 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_RSVD_23_16 register field value. */
38060 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
38061 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_RSVD_23_16 register field value. */
38062 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
38063 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_RSVD_23_16 register field. */
38064 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_RSVD_23_16_RESET 0x0
38065 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_RSVD_23_16 field value from a register. */
38066 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
38067 /* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_RSVD_23_16 register field value suitable for setting the register. */
38068 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
38069 
38070 /*
38071  * Field : Mask Byte Control - mbc_0
38072  *
38073  * This array of bits are mask control bits for comparison of each of the MAC
38074  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38075  * received DA or SA with the contents of MAC Address18 high and low registers.
38076  * Each bit controls the masking of the bytes. You can filter a group of addresses
38077  * (known as group address filtering) by masking one or more bytes of the address.
38078  *
38079  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38080  *
38081  * Field Enumeration Values:
38082  *
38083  * Enum | Value | Description
38084  * :----------------------------------------------|:------|:------------
38085  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_E_UNMSKED | 0x0 |
38086  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_E_MSKED | 0x1 |
38087  *
38088  * Field Access Macros:
38089  *
38090  */
38091 /*
38092  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0
38093  *
38094  */
38095 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_E_UNMSKED 0x0
38096 /*
38097  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0
38098  *
38099  */
38100 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_E_MSKED 0x1
38101 
38102 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field. */
38103 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_LSB 24
38104 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field. */
38105 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_MSB 24
38106 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field. */
38107 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_WIDTH 1
38108 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field value. */
38109 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_SET_MSK 0x01000000
38110 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field value. */
38111 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_CLR_MSK 0xfeffffff
38112 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field. */
38113 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_RESET 0x0
38114 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 field value from a register. */
38115 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
38116 /* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field value suitable for setting the register. */
38117 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
38118 
38119 /*
38120  * Field : Mask Byte Control - mbc_1
38121  *
38122  * This array of bits are mask control bits for comparison of each of the MAC
38123  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38124  * received DA or SA with the contents of MAC Address18 high and low registers.
38125  * Each bit controls the masking of the bytes. You can filter a group of addresses
38126  * (known as group address filtering) by masking one or more bytes of the address.
38127  *
38128  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38129  *
38130  * Field Enumeration Values:
38131  *
38132  * Enum | Value | Description
38133  * :----------------------------------------------|:------|:------------
38134  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_E_UNMSKED | 0x0 |
38135  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_E_MSKED | 0x1 |
38136  *
38137  * Field Access Macros:
38138  *
38139  */
38140 /*
38141  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1
38142  *
38143  */
38144 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_E_UNMSKED 0x0
38145 /*
38146  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1
38147  *
38148  */
38149 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_E_MSKED 0x1
38150 
38151 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field. */
38152 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_LSB 25
38153 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field. */
38154 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_MSB 25
38155 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field. */
38156 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_WIDTH 1
38157 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field value. */
38158 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_SET_MSK 0x02000000
38159 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field value. */
38160 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_CLR_MSK 0xfdffffff
38161 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field. */
38162 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_RESET 0x0
38163 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 field value from a register. */
38164 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
38165 /* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field value suitable for setting the register. */
38166 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
38167 
38168 /*
38169  * Field : Mask Byte Control - mbc_2
38170  *
38171  * This array of bits are mask control bits for comparison of each of the MAC
38172  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38173  * received DA or SA with the contents of MAC Address18 high and low registers.
38174  * Each bit controls the masking of the bytes. You can filter a group of addresses
38175  * (known as group address filtering) by masking one or more bytes of the address.
38176  *
38177  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38178  *
38179  * Field Enumeration Values:
38180  *
38181  * Enum | Value | Description
38182  * :----------------------------------------------|:------|:------------
38183  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_E_UNMSKED | 0x0 |
38184  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_E_MSKED | 0x1 |
38185  *
38186  * Field Access Macros:
38187  *
38188  */
38189 /*
38190  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2
38191  *
38192  */
38193 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_E_UNMSKED 0x0
38194 /*
38195  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2
38196  *
38197  */
38198 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_E_MSKED 0x1
38199 
38200 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field. */
38201 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_LSB 26
38202 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field. */
38203 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_MSB 26
38204 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field. */
38205 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_WIDTH 1
38206 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field value. */
38207 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_SET_MSK 0x04000000
38208 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field value. */
38209 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_CLR_MSK 0xfbffffff
38210 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field. */
38211 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_RESET 0x0
38212 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 field value from a register. */
38213 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
38214 /* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field value suitable for setting the register. */
38215 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
38216 
38217 /*
38218  * Field : Mask Byte Control - mbc_3
38219  *
38220  * This array of bits are mask control bits for comparison of each of the MAC
38221  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38222  * received DA or SA with the contents of MAC Address18 high and low registers.
38223  * Each bit controls the masking of the bytes. You can filter a group of addresses
38224  * (known as group address filtering) by masking one or more bytes of the address.
38225  *
38226  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38227  *
38228  * Field Enumeration Values:
38229  *
38230  * Enum | Value | Description
38231  * :----------------------------------------------|:------|:------------
38232  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_E_UNMSKED | 0x0 |
38233  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_E_MSKED | 0x1 |
38234  *
38235  * Field Access Macros:
38236  *
38237  */
38238 /*
38239  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3
38240  *
38241  */
38242 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_E_UNMSKED 0x0
38243 /*
38244  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3
38245  *
38246  */
38247 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_E_MSKED 0x1
38248 
38249 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field. */
38250 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_LSB 27
38251 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field. */
38252 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_MSB 27
38253 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field. */
38254 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_WIDTH 1
38255 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field value. */
38256 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_SET_MSK 0x08000000
38257 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field value. */
38258 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_CLR_MSK 0xf7ffffff
38259 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field. */
38260 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_RESET 0x0
38261 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 field value from a register. */
38262 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
38263 /* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field value suitable for setting the register. */
38264 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
38265 
38266 /*
38267  * Field : Mask Byte Control - mbc_4
38268  *
38269  * This array of bits are mask control bits for comparison of each of the MAC
38270  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38271  * received DA or SA with the contents of MAC Address18 high and low registers.
38272  * Each bit controls the masking of the bytes. You can filter a group of addresses
38273  * (known as group address filtering) by masking one or more bytes of the address.
38274  *
38275  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38276  *
38277  * Field Enumeration Values:
38278  *
38279  * Enum | Value | Description
38280  * :----------------------------------------------|:------|:------------
38281  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_E_UNMSKED | 0x0 |
38282  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_E_MSKED | 0x1 |
38283  *
38284  * Field Access Macros:
38285  *
38286  */
38287 /*
38288  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4
38289  *
38290  */
38291 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_E_UNMSKED 0x0
38292 /*
38293  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4
38294  *
38295  */
38296 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_E_MSKED 0x1
38297 
38298 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field. */
38299 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_LSB 28
38300 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field. */
38301 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_MSB 28
38302 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field. */
38303 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_WIDTH 1
38304 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field value. */
38305 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_SET_MSK 0x10000000
38306 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field value. */
38307 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_CLR_MSK 0xefffffff
38308 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field. */
38309 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_RESET 0x0
38310 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 field value from a register. */
38311 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
38312 /* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field value suitable for setting the register. */
38313 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
38314 
38315 /*
38316  * Field : Mask Byte Control - mbc_5
38317  *
38318  * This array of bits are mask control bits for comparison of each of the MAC
38319  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38320  * received DA or SA with the contents of MAC Address18 high and low registers.
38321  * Each bit controls the masking of the bytes. You can filter a group of addresses
38322  * (known as group address filtering) by masking one or more bytes of the address.
38323  *
38324  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38325  *
38326  * Field Enumeration Values:
38327  *
38328  * Enum | Value | Description
38329  * :----------------------------------------------|:------|:------------
38330  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_E_UNMSKED | 0x0 |
38331  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_E_MSKED | 0x1 |
38332  *
38333  * Field Access Macros:
38334  *
38335  */
38336 /*
38337  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5
38338  *
38339  */
38340 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_E_UNMSKED 0x0
38341 /*
38342  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5
38343  *
38344  */
38345 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_E_MSKED 0x1
38346 
38347 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field. */
38348 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_LSB 29
38349 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field. */
38350 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_MSB 29
38351 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field. */
38352 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_WIDTH 1
38353 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field value. */
38354 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_SET_MSK 0x20000000
38355 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field value. */
38356 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_CLR_MSK 0xdfffffff
38357 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field. */
38358 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_RESET 0x0
38359 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 field value from a register. */
38360 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
38361 /* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field value suitable for setting the register. */
38362 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
38363 
38364 /*
38365  * Field : sa
38366  *
38367  * Source Address
38368  *
38369  * When this bit is set, the MAC Address18[47:0] is used to compare with the SA
38370  * fields of the received frame.
38371  *
38372  * When this bit is reset, the MAC Address18[47:0] is used to compare with the DA
38373  * fields of the received frame.
38374  *
38375  * Field Enumeration Values:
38376  *
38377  * Enum | Value | Description
38378  * :----------------------------------------|:------|:------------
38379  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_E_DISD | 0x0 |
38380  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_E_END | 0x1 |
38381  *
38382  * Field Access Macros:
38383  *
38384  */
38385 /*
38386  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA
38387  *
38388  */
38389 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_E_DISD 0x0
38390 /*
38391  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA
38392  *
38393  */
38394 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_E_END 0x1
38395 
38396 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field. */
38397 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_LSB 30
38398 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field. */
38399 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_MSB 30
38400 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field. */
38401 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_WIDTH 1
38402 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field value. */
38403 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_SET_MSK 0x40000000
38404 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field value. */
38405 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_CLR_MSK 0xbfffffff
38406 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field. */
38407 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_RESET 0x0
38408 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA field value from a register. */
38409 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
38410 /* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field value suitable for setting the register. */
38411 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
38412 
38413 /*
38414  * Field : ae
38415  *
38416  * Address Enable
38417  *
38418  * When this bit is set, the address filter module uses the 19th MAC address for
38419  * perfect filtering.
38420  *
38421  * When this bit is reset, the address filter module ignores the address for
38422  * filtering.
38423  *
38424  * Field Enumeration Values:
38425  *
38426  * Enum | Value | Description
38427  * :----------------------------------------|:------|:------------
38428  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_E_DISD | 0x0 |
38429  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_E_END | 0x1 |
38430  *
38431  * Field Access Macros:
38432  *
38433  */
38434 /*
38435  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE
38436  *
38437  */
38438 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_E_DISD 0x0
38439 /*
38440  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE
38441  *
38442  */
38443 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_E_END 0x1
38444 
38445 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field. */
38446 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_LSB 31
38447 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field. */
38448 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_MSB 31
38449 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field. */
38450 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_WIDTH 1
38451 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field value. */
38452 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_SET_MSK 0x80000000
38453 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field value. */
38454 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_CLR_MSK 0x7fffffff
38455 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field. */
38456 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_RESET 0x0
38457 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE field value from a register. */
38458 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
38459 /* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field value suitable for setting the register. */
38460 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
38461 
38462 #ifndef __ASSEMBLY__
38463 /*
38464  * WARNING: The C register and register group struct declarations are provided for
38465  * convenience and illustrative purposes. They should, however, be used with
38466  * caution as the C language standard provides no guarantees about the alignment or
38467  * atomicity of device memory accesses. The recommended practice for writing
38468  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
38469  * alt_write_word() functions.
38470  *
38471  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR18_HIGH.
38472  */
38473 struct ALT_EMAC_GMAC_MAC_ADDR18_HIGH_s
38474 {
38475  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI */
38476  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR18_HIGH_RSVD_23_16 */
38477  uint32_t mbc_0 : 1; /* Mask Byte Control */
38478  uint32_t mbc_1 : 1; /* Mask Byte Control */
38479  uint32_t mbc_2 : 1; /* Mask Byte Control */
38480  uint32_t mbc_3 : 1; /* Mask Byte Control */
38481  uint32_t mbc_4 : 1; /* Mask Byte Control */
38482  uint32_t mbc_5 : 1; /* Mask Byte Control */
38483  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA */
38484  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE */
38485 };
38486 
38487 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR18_HIGH. */
38488 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR18_HIGH_s ALT_EMAC_GMAC_MAC_ADDR18_HIGH_t;
38489 #endif /* __ASSEMBLY__ */
38490 
38491 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH register. */
38492 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_RESET 0x0000ffff
38493 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH register from the beginning of the component. */
38494 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_OFST 0x810
38495 /* The address of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH register. */
38496 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR18_HIGH_OFST))
38497 
38498 /*
38499  * Register : gmacgrp_mac_address18_low
38500  *
38501  * <b> Register 517 (MAC Address18 Low Register) </b>
38502  *
38503  * The MAC Address18 Low register holds the lower 32 bits of the 19th 6-byte MAC
38504  * address of the station.
38505  *
38506  * Register Layout
38507  *
38508  * Bits | Access | Reset | Description
38509  * :-------|:-------|:-----------|:------------------------------------
38510  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO
38511  *
38512  */
38513 /*
38514  * Field : addrlo
38515  *
38516  * MAC Address18 [31:0]
38517  *
38518  * This field contains the lower 32 bits of the 19th 6-byte MAC address. The
38519  * content of this field is undefined until loaded by the Application after the
38520  * initialization process.
38521  *
38522  * Field Access Macros:
38523  *
38524  */
38525 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field. */
38526 #define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_LSB 0
38527 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field. */
38528 #define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_MSB 31
38529 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field. */
38530 #define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_WIDTH 32
38531 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field value. */
38532 #define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_SET_MSK 0xffffffff
38533 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field value. */
38534 #define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_CLR_MSK 0x00000000
38535 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field. */
38536 #define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_RESET 0xffffffff
38537 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO field value from a register. */
38538 #define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
38539 /* Produces a ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field value suitable for setting the register. */
38540 #define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
38541 
38542 #ifndef __ASSEMBLY__
38543 /*
38544  * WARNING: The C register and register group struct declarations are provided for
38545  * convenience and illustrative purposes. They should, however, be used with
38546  * caution as the C language standard provides no guarantees about the alignment or
38547  * atomicity of device memory accesses. The recommended practice for writing
38548  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
38549  * alt_write_word() functions.
38550  *
38551  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR18_LOW.
38552  */
38553 struct ALT_EMAC_GMAC_MAC_ADDR18_LOW_s
38554 {
38555  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO */
38556 };
38557 
38558 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR18_LOW. */
38559 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR18_LOW_s ALT_EMAC_GMAC_MAC_ADDR18_LOW_t;
38560 #endif /* __ASSEMBLY__ */
38561 
38562 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_LOW register. */
38563 #define ALT_EMAC_GMAC_MAC_ADDR18_LOW_RESET 0xffffffff
38564 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR18_LOW register from the beginning of the component. */
38565 #define ALT_EMAC_GMAC_MAC_ADDR18_LOW_OFST 0x814
38566 /* The address of the ALT_EMAC_GMAC_MAC_ADDR18_LOW register. */
38567 #define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR18_LOW_OFST))
38568 
38569 /*
38570  * Register : gmacgrp_mac_address19_high
38571  *
38572  * <b> Register 518 (MAC Address19 High Register) </b>
38573  *
38574  * The MAC Address19 High register holds the upper 16 bits of the 20th 6-byte MAC
38575  * address of the station.
38576  *
38577  * If the MAC address registers are configured to be double-synchronized to the
38578  * (G)MII clock domains, then
38579  *
38580  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
38581  * or Bits[7:0] (in big-endian mode) of the MAC Address19 Low Register are written.
38582  * For proper synchronization updates, consecutive writes to this MAC Address19 Low
38583  * Register must be performed after at least four clock cycles in the destination
38584  * clock domain.
38585  *
38586  * Register Layout
38587  *
38588  * Bits | Access | Reset | Description
38589  * :--------|:-------|:-------|:-----------------------------------------
38590  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI
38591  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR19_HIGH_RSVD_23_16
38592  * [24] | RW | 0x0 | Mask Byte Control
38593  * [25] | RW | 0x0 | Mask Byte Control
38594  * [26] | RW | 0x0 | Mask Byte Control
38595  * [27] | RW | 0x0 | Mask Byte Control
38596  * [28] | RW | 0x0 | Mask Byte Control
38597  * [29] | RW | 0x0 | Mask Byte Control
38598  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA
38599  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE
38600  *
38601  */
38602 /*
38603  * Field : addrhi
38604  *
38605  * MAC Address19 [47:32]
38606  *
38607  * This field contains the upper 16 bits (47:32) of the 20th 6-byte MAC address.
38608  *
38609  * Field Access Macros:
38610  *
38611  */
38612 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field. */
38613 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_LSB 0
38614 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field. */
38615 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_MSB 15
38616 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field. */
38617 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_WIDTH 16
38618 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field value. */
38619 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_SET_MSK 0x0000ffff
38620 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field value. */
38621 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_CLR_MSK 0xffff0000
38622 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field. */
38623 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_RESET 0xffff
38624 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI field value from a register. */
38625 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
38626 /* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field value suitable for setting the register. */
38627 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
38628 
38629 /*
38630  * Field : reserved_23_16
38631  *
38632  * Reserved
38633  *
38634  * Field Access Macros:
38635  *
38636  */
38637 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_RSVD_23_16 register field. */
38638 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_RSVD_23_16_LSB 16
38639 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_RSVD_23_16 register field. */
38640 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_RSVD_23_16_MSB 23
38641 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_RSVD_23_16 register field. */
38642 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_RSVD_23_16_WIDTH 8
38643 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_RSVD_23_16 register field value. */
38644 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
38645 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_RSVD_23_16 register field value. */
38646 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
38647 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_RSVD_23_16 register field. */
38648 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_RSVD_23_16_RESET 0x0
38649 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_RSVD_23_16 field value from a register. */
38650 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
38651 /* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_RSVD_23_16 register field value suitable for setting the register. */
38652 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
38653 
38654 /*
38655  * Field : Mask Byte Control - mbc_0
38656  *
38657  * This array of bits are mask control bits for comparison of each of the MAC
38658  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38659  * received DA or SA with the contents of MAC Address19 high and low registers.
38660  * Each bit controls the masking of the bytes. You can filter a group of addresses
38661  * (known as group address filtering) by masking one or more bytes of the address.
38662  *
38663  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38664  *
38665  * Field Enumeration Values:
38666  *
38667  * Enum | Value | Description
38668  * :----------------------------------------------|:------|:------------
38669  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_E_UNMSKED | 0x0 |
38670  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_E_MSKED | 0x1 |
38671  *
38672  * Field Access Macros:
38673  *
38674  */
38675 /*
38676  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0
38677  *
38678  */
38679 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_E_UNMSKED 0x0
38680 /*
38681  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0
38682  *
38683  */
38684 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_E_MSKED 0x1
38685 
38686 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field. */
38687 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_LSB 24
38688 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field. */
38689 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_MSB 24
38690 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field. */
38691 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_WIDTH 1
38692 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field value. */
38693 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_SET_MSK 0x01000000
38694 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field value. */
38695 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_CLR_MSK 0xfeffffff
38696 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field. */
38697 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_RESET 0x0
38698 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 field value from a register. */
38699 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
38700 /* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field value suitable for setting the register. */
38701 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
38702 
38703 /*
38704  * Field : Mask Byte Control - mbc_1
38705  *
38706  * This array of bits are mask control bits for comparison of each of the MAC
38707  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38708  * received DA or SA with the contents of MAC Address19 high and low registers.
38709  * Each bit controls the masking of the bytes. You can filter a group of addresses
38710  * (known as group address filtering) by masking one or more bytes of the address.
38711  *
38712  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38713  *
38714  * Field Enumeration Values:
38715  *
38716  * Enum | Value | Description
38717  * :----------------------------------------------|:------|:------------
38718  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_E_UNMSKED | 0x0 |
38719  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_E_MSKED | 0x1 |
38720  *
38721  * Field Access Macros:
38722  *
38723  */
38724 /*
38725  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1
38726  *
38727  */
38728 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_E_UNMSKED 0x0
38729 /*
38730  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1
38731  *
38732  */
38733 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_E_MSKED 0x1
38734 
38735 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field. */
38736 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_LSB 25
38737 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field. */
38738 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_MSB 25
38739 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field. */
38740 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_WIDTH 1
38741 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field value. */
38742 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_SET_MSK 0x02000000
38743 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field value. */
38744 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_CLR_MSK 0xfdffffff
38745 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field. */
38746 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_RESET 0x0
38747 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 field value from a register. */
38748 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
38749 /* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field value suitable for setting the register. */
38750 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
38751 
38752 /*
38753  * Field : Mask Byte Control - mbc_2
38754  *
38755  * This array of bits are mask control bits for comparison of each of the MAC
38756  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38757  * received DA or SA with the contents of MAC Address19 high and low registers.
38758  * Each bit controls the masking of the bytes. You can filter a group of addresses
38759  * (known as group address filtering) by masking one or more bytes of the address.
38760  *
38761  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38762  *
38763  * Field Enumeration Values:
38764  *
38765  * Enum | Value | Description
38766  * :----------------------------------------------|:------|:------------
38767  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_E_UNMSKED | 0x0 |
38768  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_E_MSKED | 0x1 |
38769  *
38770  * Field Access Macros:
38771  *
38772  */
38773 /*
38774  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2
38775  *
38776  */
38777 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_E_UNMSKED 0x0
38778 /*
38779  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2
38780  *
38781  */
38782 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_E_MSKED 0x1
38783 
38784 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field. */
38785 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_LSB 26
38786 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field. */
38787 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_MSB 26
38788 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field. */
38789 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_WIDTH 1
38790 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field value. */
38791 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_SET_MSK 0x04000000
38792 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field value. */
38793 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_CLR_MSK 0xfbffffff
38794 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field. */
38795 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_RESET 0x0
38796 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 field value from a register. */
38797 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
38798 /* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field value suitable for setting the register. */
38799 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
38800 
38801 /*
38802  * Field : Mask Byte Control - mbc_3
38803  *
38804  * This array of bits are mask control bits for comparison of each of the MAC
38805  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38806  * received DA or SA with the contents of MAC Address19 high and low registers.
38807  * Each bit controls the masking of the bytes. You can filter a group of addresses
38808  * (known as group address filtering) by masking one or more bytes of the address.
38809  *
38810  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38811  *
38812  * Field Enumeration Values:
38813  *
38814  * Enum | Value | Description
38815  * :----------------------------------------------|:------|:------------
38816  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_E_UNMSKED | 0x0 |
38817  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_E_MSKED | 0x1 |
38818  *
38819  * Field Access Macros:
38820  *
38821  */
38822 /*
38823  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3
38824  *
38825  */
38826 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_E_UNMSKED 0x0
38827 /*
38828  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3
38829  *
38830  */
38831 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_E_MSKED 0x1
38832 
38833 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field. */
38834 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_LSB 27
38835 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field. */
38836 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_MSB 27
38837 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field. */
38838 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_WIDTH 1
38839 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field value. */
38840 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_SET_MSK 0x08000000
38841 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field value. */
38842 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_CLR_MSK 0xf7ffffff
38843 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field. */
38844 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_RESET 0x0
38845 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 field value from a register. */
38846 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
38847 /* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field value suitable for setting the register. */
38848 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
38849 
38850 /*
38851  * Field : Mask Byte Control - mbc_4
38852  *
38853  * This array of bits are mask control bits for comparison of each of the MAC
38854  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38855  * received DA or SA with the contents of MAC Address19 high and low registers.
38856  * Each bit controls the masking of the bytes. You can filter a group of addresses
38857  * (known as group address filtering) by masking one or more bytes of the address.
38858  *
38859  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38860  *
38861  * Field Enumeration Values:
38862  *
38863  * Enum | Value | Description
38864  * :----------------------------------------------|:------|:------------
38865  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_E_UNMSKED | 0x0 |
38866  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_E_MSKED | 0x1 |
38867  *
38868  * Field Access Macros:
38869  *
38870  */
38871 /*
38872  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4
38873  *
38874  */
38875 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_E_UNMSKED 0x0
38876 /*
38877  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4
38878  *
38879  */
38880 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_E_MSKED 0x1
38881 
38882 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field. */
38883 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_LSB 28
38884 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field. */
38885 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_MSB 28
38886 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field. */
38887 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_WIDTH 1
38888 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field value. */
38889 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_SET_MSK 0x10000000
38890 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field value. */
38891 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_CLR_MSK 0xefffffff
38892 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field. */
38893 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_RESET 0x0
38894 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 field value from a register. */
38895 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
38896 /* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field value suitable for setting the register. */
38897 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
38898 
38899 /*
38900  * Field : Mask Byte Control - mbc_5
38901  *
38902  * This array of bits are mask control bits for comparison of each of the MAC
38903  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38904  * received DA or SA with the contents of MAC Address19 high and low registers.
38905  * Each bit controls the masking of the bytes. You can filter a group of addresses
38906  * (known as group address filtering) by masking one or more bytes of the address.
38907  *
38908  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38909  *
38910  * Field Enumeration Values:
38911  *
38912  * Enum | Value | Description
38913  * :----------------------------------------------|:------|:------------
38914  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_E_UNMSKED | 0x0 |
38915  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_E_MSKED | 0x1 |
38916  *
38917  * Field Access Macros:
38918  *
38919  */
38920 /*
38921  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5
38922  *
38923  */
38924 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_E_UNMSKED 0x0
38925 /*
38926  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5
38927  *
38928  */
38929 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_E_MSKED 0x1
38930 
38931 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field. */
38932 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_LSB 29
38933 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field. */
38934 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_MSB 29
38935 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field. */
38936 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_WIDTH 1
38937 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field value. */
38938 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_SET_MSK 0x20000000
38939 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field value. */
38940 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_CLR_MSK 0xdfffffff
38941 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field. */
38942 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_RESET 0x0
38943 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 field value from a register. */
38944 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
38945 /* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field value suitable for setting the register. */
38946 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
38947 
38948 /*
38949  * Field : sa
38950  *
38951  * Source Address
38952  *
38953  * When this bit is set, the MAC Address19[47:0] is used to compare with the SA
38954  * fields of the received frame.
38955  *
38956  * When this bit is reset, the MAC Address19[47:0] is used to compare with the DA
38957  * fields of the received frame.
38958  *
38959  * Field Enumeration Values:
38960  *
38961  * Enum | Value | Description
38962  * :----------------------------------------|:------|:------------
38963  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_E_DISD | 0x0 |
38964  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_E_END | 0x1 |
38965  *
38966  * Field Access Macros:
38967  *
38968  */
38969 /*
38970  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA
38971  *
38972  */
38973 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_E_DISD 0x0
38974 /*
38975  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA
38976  *
38977  */
38978 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_E_END 0x1
38979 
38980 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field. */
38981 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_LSB 30
38982 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field. */
38983 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_MSB 30
38984 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field. */
38985 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_WIDTH 1
38986 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field value. */
38987 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_SET_MSK 0x40000000
38988 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field value. */
38989 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_CLR_MSK 0xbfffffff
38990 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field. */
38991 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_RESET 0x0
38992 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA field value from a register. */
38993 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
38994 /* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field value suitable for setting the register. */
38995 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
38996 
38997 /*
38998  * Field : ae
38999  *
39000  * Address Enable
39001  *
39002  * When this bit is set, the address filter module uses the 20th MAC address for
39003  * perfect filtering.
39004  *
39005  * When this bit is reset, the address filter module ignores the address for
39006  * filtering.
39007  *
39008  * Field Enumeration Values:
39009  *
39010  * Enum | Value | Description
39011  * :----------------------------------------|:------|:------------
39012  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_E_DISD | 0x0 |
39013  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_E_END | 0x1 |
39014  *
39015  * Field Access Macros:
39016  *
39017  */
39018 /*
39019  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE
39020  *
39021  */
39022 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_E_DISD 0x0
39023 /*
39024  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE
39025  *
39026  */
39027 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_E_END 0x1
39028 
39029 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field. */
39030 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_LSB 31
39031 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field. */
39032 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_MSB 31
39033 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field. */
39034 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_WIDTH 1
39035 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field value. */
39036 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_SET_MSK 0x80000000
39037 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field value. */
39038 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_CLR_MSK 0x7fffffff
39039 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field. */
39040 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_RESET 0x0
39041 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE field value from a register. */
39042 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
39043 /* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field value suitable for setting the register. */
39044 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
39045 
39046 #ifndef __ASSEMBLY__
39047 /*
39048  * WARNING: The C register and register group struct declarations are provided for
39049  * convenience and illustrative purposes. They should, however, be used with
39050  * caution as the C language standard provides no guarantees about the alignment or
39051  * atomicity of device memory accesses. The recommended practice for writing
39052  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
39053  * alt_write_word() functions.
39054  *
39055  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR19_HIGH.
39056  */
39057 struct ALT_EMAC_GMAC_MAC_ADDR19_HIGH_s
39058 {
39059  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI */
39060  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR19_HIGH_RSVD_23_16 */
39061  uint32_t mbc_0 : 1; /* Mask Byte Control */
39062  uint32_t mbc_1 : 1; /* Mask Byte Control */
39063  uint32_t mbc_2 : 1; /* Mask Byte Control */
39064  uint32_t mbc_3 : 1; /* Mask Byte Control */
39065  uint32_t mbc_4 : 1; /* Mask Byte Control */
39066  uint32_t mbc_5 : 1; /* Mask Byte Control */
39067  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA */
39068  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE */
39069 };
39070 
39071 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR19_HIGH. */
39072 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR19_HIGH_s ALT_EMAC_GMAC_MAC_ADDR19_HIGH_t;
39073 #endif /* __ASSEMBLY__ */
39074 
39075 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH register. */
39076 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_RESET 0x0000ffff
39077 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH register from the beginning of the component. */
39078 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_OFST 0x818
39079 /* The address of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH register. */
39080 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR19_HIGH_OFST))
39081 
39082 /*
39083  * Register : gmacgrp_mac_address19_low
39084  *
39085  * <b> Register 519 (MAC Address19 Low Register) </b>
39086  *
39087  * The MAC Address19 Low register holds the lower 32 bits of the 20th 6-byte MAC
39088  * address of the station.
39089  *
39090  * Register Layout
39091  *
39092  * Bits | Access | Reset | Description
39093  * :-------|:-------|:-----------|:------------------------------------
39094  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO
39095  *
39096  */
39097 /*
39098  * Field : addrlo
39099  *
39100  * MAC Address19 [31:0]
39101  *
39102  * This field contains the lower 32 bits of the 20th 6-byte MAC address. The
39103  * content of this field is undefined until loaded by the Application after the
39104  * initialization process.
39105  *
39106  * Field Access Macros:
39107  *
39108  */
39109 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field. */
39110 #define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_LSB 0
39111 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field. */
39112 #define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_MSB 31
39113 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field. */
39114 #define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_WIDTH 32
39115 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field value. */
39116 #define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_SET_MSK 0xffffffff
39117 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field value. */
39118 #define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_CLR_MSK 0x00000000
39119 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field. */
39120 #define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_RESET 0xffffffff
39121 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO field value from a register. */
39122 #define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
39123 /* Produces a ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field value suitable for setting the register. */
39124 #define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
39125 
39126 #ifndef __ASSEMBLY__
39127 /*
39128  * WARNING: The C register and register group struct declarations are provided for
39129  * convenience and illustrative purposes. They should, however, be used with
39130  * caution as the C language standard provides no guarantees about the alignment or
39131  * atomicity of device memory accesses. The recommended practice for writing
39132  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
39133  * alt_write_word() functions.
39134  *
39135  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR19_LOW.
39136  */
39137 struct ALT_EMAC_GMAC_MAC_ADDR19_LOW_s
39138 {
39139  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO */
39140 };
39141 
39142 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR19_LOW. */
39143 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR19_LOW_s ALT_EMAC_GMAC_MAC_ADDR19_LOW_t;
39144 #endif /* __ASSEMBLY__ */
39145 
39146 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_LOW register. */
39147 #define ALT_EMAC_GMAC_MAC_ADDR19_LOW_RESET 0xffffffff
39148 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR19_LOW register from the beginning of the component. */
39149 #define ALT_EMAC_GMAC_MAC_ADDR19_LOW_OFST 0x81c
39150 /* The address of the ALT_EMAC_GMAC_MAC_ADDR19_LOW register. */
39151 #define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR19_LOW_OFST))
39152 
39153 /*
39154  * Register : gmacgrp_mac_address20_high
39155  *
39156  * <b> Register 520 (MAC Address20 High Register) </b>
39157  *
39158  * The MAC Address20 High register holds the upper 16 bits of the 21st 6-byte MAC
39159  * address of the station.
39160  *
39161  * If the MAC address registers are configured to be double-synchronized to the
39162  * (G)MII clock domains, then
39163  *
39164  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
39165  * or Bits[7:0] (in big-endian mode) of the MAC Address20 Low Register are written.
39166  * For proper synchronization updates, consecutive writes to this MAC Address20 Low
39167  * Register must be performed after at least four clock cycles in the destination
39168  * clock domain.
39169  *
39170  * Register Layout
39171  *
39172  * Bits | Access | Reset | Description
39173  * :--------|:-------|:-------|:-----------------------------------------
39174  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI
39175  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR20_HIGH_RSVD_23_16
39176  * [24] | RW | 0x0 | Mask Byte Control
39177  * [25] | RW | 0x0 | Mask Byte Control
39178  * [26] | RW | 0x0 | Mask Byte Control
39179  * [27] | RW | 0x0 | Mask Byte Control
39180  * [28] | RW | 0x0 | Mask Byte Control
39181  * [29] | RW | 0x0 | Mask Byte Control
39182  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA
39183  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE
39184  *
39185  */
39186 /*
39187  * Field : addrhi
39188  *
39189  * MAC Address20 [47:32]
39190  *
39191  * This field contains the upper 16 bits (47:32) of the 20th 6-byte MAC address.
39192  *
39193  * Field Access Macros:
39194  *
39195  */
39196 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field. */
39197 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_LSB 0
39198 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field. */
39199 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_MSB 15
39200 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field. */
39201 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_WIDTH 16
39202 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field value. */
39203 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_SET_MSK 0x0000ffff
39204 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field value. */
39205 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_CLR_MSK 0xffff0000
39206 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field. */
39207 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_RESET 0xffff
39208 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI field value from a register. */
39209 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
39210 /* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field value suitable for setting the register. */
39211 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
39212 
39213 /*
39214  * Field : reserved_23_16
39215  *
39216  * Reserved
39217  *
39218  * Field Access Macros:
39219  *
39220  */
39221 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_RSVD_23_16 register field. */
39222 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_RSVD_23_16_LSB 16
39223 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_RSVD_23_16 register field. */
39224 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_RSVD_23_16_MSB 23
39225 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_RSVD_23_16 register field. */
39226 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_RSVD_23_16_WIDTH 8
39227 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_RSVD_23_16 register field value. */
39228 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
39229 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_RSVD_23_16 register field value. */
39230 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
39231 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_RSVD_23_16 register field. */
39232 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_RSVD_23_16_RESET 0x0
39233 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_RSVD_23_16 field value from a register. */
39234 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
39235 /* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_RSVD_23_16 register field value suitable for setting the register. */
39236 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
39237 
39238 /*
39239  * Field : Mask Byte Control - mbc_0
39240  *
39241  * This array of bits are mask control bits for comparison of each of the MAC
39242  * Address bytes. When masked, the MAC does not compare the corresponding byte of
39243  * received DA or SA with the contents of MAC Address20 high and low registers.
39244  * Each bit controls the masking of the bytes. You can filter a group of addresses
39245  * (known as group address filtering) by masking one or more bytes of the address.
39246  *
39247  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
39248  *
39249  * Field Enumeration Values:
39250  *
39251  * Enum | Value | Description
39252  * :----------------------------------------------|:------|:------------
39253  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_E_UNMSKED | 0x0 |
39254  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_E_MSKED | 0x1 |
39255  *
39256  * Field Access Macros:
39257  *
39258  */
39259 /*
39260  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0
39261  *
39262  */
39263 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_E_UNMSKED 0x0
39264 /*
39265  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0
39266  *
39267  */
39268 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_E_MSKED 0x1
39269 
39270 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field. */
39271 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_LSB 24
39272 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field. */
39273 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_MSB 24
39274 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field. */
39275 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_WIDTH 1
39276 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field value. */
39277 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_SET_MSK 0x01000000
39278 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field value. */
39279 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_CLR_MSK 0xfeffffff
39280 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field. */
39281 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_RESET 0x0
39282 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 field value from a register. */
39283 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
39284 /* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field value suitable for setting the register. */
39285 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
39286 
39287 /*
39288  * Field : Mask Byte Control - mbc_1
39289  *
39290  * This array of bits are mask control bits for comparison of each of the MAC
39291  * Address bytes. When masked, the MAC does not compare the corresponding byte of
39292  * received DA or SA with the contents of MAC Address20 high and low registers.
39293  * Each bit controls the masking of the bytes. You can filter a group of addresses
39294  * (known as group address filtering) by masking one or more bytes of the address.
39295  *
39296  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
39297  *
39298  * Field Enumeration Values:
39299  *
39300  * Enum | Value | Description
39301  * :----------------------------------------------|:------|:------------
39302  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_E_UNMSKED | 0x0 |
39303  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_E_MSKED | 0x1 |
39304  *
39305  * Field Access Macros:
39306  *
39307  */
39308 /*
39309  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1
39310  *
39311  */
39312 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_E_UNMSKED 0x0
39313 /*
39314  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1
39315  *
39316  */
39317 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_E_MSKED 0x1
39318 
39319 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field. */
39320 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_LSB 25
39321 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field. */
39322 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_MSB 25
39323 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field. */
39324 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_WIDTH 1
39325 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field value. */
39326 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_SET_MSK 0x02000000
39327 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field value. */
39328 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_CLR_MSK 0xfdffffff
39329 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field. */
39330 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_RESET 0x0
39331 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 field value from a register. */
39332 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
39333 /* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field value suitable for setting the register. */
39334 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
39335 
39336 /*
39337  * Field : Mask Byte Control - mbc_2
39338  *
39339  * This array of bits are mask control bits for comparison of each of the MAC
39340  * Address bytes. When masked, the MAC does not compare the corresponding byte of
39341  * received DA or SA with the contents of MAC Address20 high and low registers.
39342  * Each bit controls the masking of the bytes. You can filter a group of addresses
39343  * (known as group address filtering) by masking one or more bytes of the address.
39344  *
39345  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
39346  *
39347  * Field Enumeration Values:
39348  *
39349  * Enum | Value | Description
39350  * :----------------------------------------------|:------|:------------
39351  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_E_UNMSKED | 0x0 |
39352  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_E_MSKED | 0x1 |
39353  *
39354  * Field Access Macros:
39355  *
39356  */
39357 /*
39358  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2
39359  *
39360  */
39361 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_E_UNMSKED 0x0
39362 /*
39363  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2
39364  *
39365  */
39366 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_E_MSKED 0x1
39367 
39368 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field. */
39369 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_LSB 26
39370 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field. */
39371 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_MSB 26
39372 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field. */
39373 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_WIDTH 1
39374 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field value. */
39375 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_SET_MSK 0x04000000
39376 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field value. */
39377 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_CLR_MSK 0xfbffffff
39378 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field. */
39379 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_RESET 0x0
39380 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 field value from a register. */
39381 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
39382 /* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field value suitable for setting the register. */
39383 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
39384 
39385 /*
39386  * Field : Mask Byte Control - mbc_3
39387  *
39388  * This array of bits are mask control bits for comparison of each of the MAC
39389  * Address bytes. When masked, the MAC does not compare the corresponding byte of
39390  * received DA or SA with the contents of MAC Address20 high and low registers.
39391  * Each bit controls the masking of the bytes. You can filter a group of addresses
39392  * (known as group address filtering) by masking one or more bytes of the address.
39393  *
39394  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
39395  *
39396  * Field Enumeration Values:
39397  *
39398  * Enum | Value | Description
39399  * :----------------------------------------------|:------|:------------
39400  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_E_UNMSKED | 0x0 |
39401  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_E_MSKED | 0x1 |
39402  *
39403  * Field Access Macros:
39404  *
39405  */
39406 /*
39407  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3
39408  *
39409  */
39410 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_E_UNMSKED 0x0
39411 /*
39412  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3
39413  *
39414  */
39415 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_E_MSKED 0x1
39416 
39417 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field. */
39418 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_LSB 27
39419 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field. */
39420 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_MSB 27
39421 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field. */
39422 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_WIDTH 1
39423 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field value. */
39424 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_SET_MSK 0x08000000
39425 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field value. */
39426 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_CLR_MSK 0xf7ffffff
39427 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field. */
39428 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_RESET 0x0
39429 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 field value from a register. */
39430 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
39431 /* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field value suitable for setting the register. */
39432 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
39433 
39434 /*
39435  * Field : Mask Byte Control - mbc_4
39436  *
39437  * This array of bits are mask control bits for comparison of each of the MAC
39438  * Address bytes. When masked, the MAC does not compare the corresponding byte of
39439  * received DA or SA with the contents of MAC Address20 high and low registers.
39440  * Each bit controls the masking of the bytes. You can filter a group of addresses
39441  * (known as group address filtering) by masking one or more bytes of the address.
39442  *
39443  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
39444  *
39445  * Field Enumeration Values:
39446  *
39447  * Enum | Value | Description
39448  * :----------------------------------------------|:------|:------------
39449  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_E_UNMSKED | 0x0 |
39450  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_E_MSKED | 0x1 |
39451  *
39452  * Field Access Macros:
39453  *
39454  */
39455 /*
39456  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4
39457  *
39458  */
39459 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_E_UNMSKED 0x0
39460 /*
39461  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4
39462  *
39463  */
39464 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_E_MSKED 0x1
39465 
39466 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field. */
39467 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_LSB 28
39468 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field. */
39469 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_MSB 28
39470 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field. */
39471 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_WIDTH 1
39472 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field value. */
39473 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_SET_MSK 0x10000000
39474 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field value. */
39475 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_CLR_MSK 0xefffffff
39476 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field. */
39477 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_RESET 0x0
39478 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 field value from a register. */
39479 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
39480 /* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field value suitable for setting the register. */
39481 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
39482 
39483 /*
39484  * Field : Mask Byte Control - mbc_5
39485  *
39486  * This array of bits are mask control bits for comparison of each of the MAC
39487  * Address bytes. When masked, the MAC does not compare the corresponding byte of
39488  * received DA or SA with the contents of MAC Address20 high and low registers.
39489  * Each bit controls the masking of the bytes. You can filter a group of addresses
39490  * (known as group address filtering) by masking one or more bytes of the address.
39491  *
39492  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
39493  *
39494  * Field Enumeration Values:
39495  *
39496  * Enum | Value | Description
39497  * :----------------------------------------------|:------|:------------
39498  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_E_UNMSKED | 0x0 |
39499  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_E_MSKED | 0x1 |
39500  *
39501  * Field Access Macros:
39502  *
39503  */
39504 /*
39505  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5
39506  *
39507  */
39508 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_E_UNMSKED 0x0
39509 /*
39510  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5
39511  *
39512  */
39513 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_E_MSKED 0x1
39514 
39515 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field. */
39516 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_LSB 29
39517 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field. */
39518 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_MSB 29
39519 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field. */
39520 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_WIDTH 1
39521 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field value. */
39522 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_SET_MSK 0x20000000
39523 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field value. */
39524 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_CLR_MSK 0xdfffffff
39525 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field. */
39526 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_RESET 0x0
39527 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 field value from a register. */
39528 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
39529 /* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field value suitable for setting the register. */
39530 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
39531 
39532 /*
39533  * Field : sa
39534  *
39535  * Source Address
39536  *
39537  * When this bit is set, the MAC Address20[47:0] is used to compare with the SA
39538  * fields of the received frame.
39539  *
39540  * When this bit is reset, the MAC Address20[47:0] is used to compare with the DA
39541  * fields of the received frame.
39542  *
39543  * Field Enumeration Values:
39544  *
39545  * Enum | Value | Description
39546  * :----------------------------------------|:------|:------------
39547  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_E_DISD | 0x0 |
39548  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_E_END | 0x1 |
39549  *
39550  * Field Access Macros:
39551  *
39552  */
39553 /*
39554  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA
39555  *
39556  */
39557 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_E_DISD 0x0
39558 /*
39559  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA
39560  *
39561  */
39562 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_E_END 0x1
39563 
39564 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field. */
39565 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_LSB 30
39566 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field. */
39567 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_MSB 30
39568 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field. */
39569 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_WIDTH 1
39570 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field value. */
39571 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_SET_MSK 0x40000000
39572 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field value. */
39573 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_CLR_MSK 0xbfffffff
39574 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field. */
39575 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_RESET 0x0
39576 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA field value from a register. */
39577 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
39578 /* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field value suitable for setting the register. */
39579 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
39580 
39581 /*
39582  * Field : ae
39583  *
39584  * Address Enable
39585  *
39586  * When this bit is set, the address filter module uses the 21st MAC address for
39587  * perfect filtering.
39588  *
39589  * When this bit is reset, the address filter module ignores the address for
39590  * filtering.
39591  *
39592  * Field Enumeration Values:
39593  *
39594  * Enum | Value | Description
39595  * :----------------------------------------|:------|:------------
39596  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_E_DISD | 0x0 |
39597  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_E_END | 0x1 |
39598  *
39599  * Field Access Macros:
39600  *
39601  */
39602 /*
39603  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE
39604  *
39605  */
39606 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_E_DISD 0x0
39607 /*
39608  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE
39609  *
39610  */
39611 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_E_END 0x1
39612 
39613 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field. */
39614 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_LSB 31
39615 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field. */
39616 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_MSB 31
39617 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field. */
39618 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_WIDTH 1
39619 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field value. */
39620 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_SET_MSK 0x80000000
39621 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field value. */
39622 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_CLR_MSK 0x7fffffff
39623 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field. */
39624 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_RESET 0x0
39625 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE field value from a register. */
39626 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
39627 /* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field value suitable for setting the register. */
39628 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
39629 
39630 #ifndef __ASSEMBLY__
39631 /*
39632  * WARNING: The C register and register group struct declarations are provided for
39633  * convenience and illustrative purposes. They should, however, be used with
39634  * caution as the C language standard provides no guarantees about the alignment or
39635  * atomicity of device memory accesses. The recommended practice for writing
39636  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
39637  * alt_write_word() functions.
39638  *
39639  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR20_HIGH.
39640  */
39641 struct ALT_EMAC_GMAC_MAC_ADDR20_HIGH_s
39642 {
39643  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI */
39644  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR20_HIGH_RSVD_23_16 */
39645  uint32_t mbc_0 : 1; /* Mask Byte Control */
39646  uint32_t mbc_1 : 1; /* Mask Byte Control */
39647  uint32_t mbc_2 : 1; /* Mask Byte Control */
39648  uint32_t mbc_3 : 1; /* Mask Byte Control */
39649  uint32_t mbc_4 : 1; /* Mask Byte Control */
39650  uint32_t mbc_5 : 1; /* Mask Byte Control */
39651  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA */
39652  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE */
39653 };
39654 
39655 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR20_HIGH. */
39656 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR20_HIGH_s ALT_EMAC_GMAC_MAC_ADDR20_HIGH_t;
39657 #endif /* __ASSEMBLY__ */
39658 
39659 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH register. */
39660 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_RESET 0x0000ffff
39661 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH register from the beginning of the component. */
39662 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_OFST 0x820
39663 /* The address of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH register. */
39664 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR20_HIGH_OFST))
39665 
39666 /*
39667  * Register : gmacgrp_mac_address20_low
39668  *
39669  * <b> Register 521 (MAC Address20 Low Register) </b>
39670  *
39671  * The MAC Address20 Low register holds the lower 32 bits of the 21st 6-byte MAC
39672  * address of the station.
39673  *
39674  * Register Layout
39675  *
39676  * Bits | Access | Reset | Description
39677  * :-------|:-------|:-----------|:------------------------------------
39678  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO
39679  *
39680  */
39681 /*
39682  * Field : addrlo
39683  *
39684  * MAC Address20 [31:0]
39685  *
39686  * This field contains the lower 32 bits of the 21st 6-byte MAC address. The
39687  * content of this field is undefined until loaded by the Application after the
39688  * initialization process.
39689  *
39690  * Field Access Macros:
39691  *
39692  */
39693 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field. */
39694 #define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_LSB 0
39695 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field. */
39696 #define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_MSB 31
39697 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field. */
39698 #define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_WIDTH 32
39699 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field value. */
39700 #define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_SET_MSK 0xffffffff
39701 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field value. */
39702 #define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_CLR_MSK 0x00000000
39703 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field. */
39704 #define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_RESET 0xffffffff
39705 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO field value from a register. */
39706 #define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
39707 /* Produces a ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field value suitable for setting the register. */
39708 #define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
39709 
39710 #ifndef __ASSEMBLY__
39711 /*
39712  * WARNING: The C register and register group struct declarations are provided for
39713  * convenience and illustrative purposes. They should, however, be used with
39714  * caution as the C language standard provides no guarantees about the alignment or
39715  * atomicity of device memory accesses. The recommended practice for writing
39716  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
39717  * alt_write_word() functions.
39718  *
39719  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR20_LOW.
39720  */
39721 struct ALT_EMAC_GMAC_MAC_ADDR20_LOW_s
39722 {
39723  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO */
39724 };
39725 
39726 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR20_LOW. */
39727 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR20_LOW_s ALT_EMAC_GMAC_MAC_ADDR20_LOW_t;
39728 #endif /* __ASSEMBLY__ */
39729 
39730 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_LOW register. */
39731 #define ALT_EMAC_GMAC_MAC_ADDR20_LOW_RESET 0xffffffff
39732 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR20_LOW register from the beginning of the component. */
39733 #define ALT_EMAC_GMAC_MAC_ADDR20_LOW_OFST 0x824
39734 /* The address of the ALT_EMAC_GMAC_MAC_ADDR20_LOW register. */
39735 #define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR20_LOW_OFST))
39736 
39737 /*
39738  * Register : gmacgrp_mac_address21_high
39739  *
39740  * <b> Register 522 (MAC Address21 High Register) </b>
39741  *
39742  * The MAC Address21 High register holds the upper 16 bits of the 22nd 6-byte MAC
39743  * address of the station.
39744  *
39745  * If the MAC address registers are configured to be double-synchronized to the
39746  * (G)MII clock domains, then
39747  *
39748  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
39749  * or Bits[7:0] (in big-endian mode) of the MAC Address21 Low Register are written.
39750  * For proper synchronization updates, consecutive writes to this MAC Address21 Low
39751  * Register must be performed after at least four clock cycles in the destination
39752  * clock domain.
39753  *
39754  * Register Layout
39755  *
39756  * Bits | Access | Reset | Description
39757  * :--------|:-------|:-------|:-----------------------------------------
39758  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI
39759  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR21_HIGH_RSVD_23_16
39760  * [24] | RW | 0x0 | Mask Byte Control
39761  * [25] | RW | 0x0 | Mask Byte Control
39762  * [26] | RW | 0x0 | Mask Byte Control
39763  * [27] | RW | 0x0 | Mask Byte Control
39764  * [28] | RW | 0x0 | Mask Byte Control
39765  * [29] | RW | 0x0 | Mask Byte Control
39766  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA
39767  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE
39768  *
39769  */
39770 /*
39771  * Field : addrhi
39772  *
39773  * MAC Address21 [47:32]
39774  *
39775  * This field contains the upper 16 bits (47:32) of the 6-byte 22nd MAC address.
39776  *
39777  * Field Access Macros:
39778  *
39779  */
39780 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field. */
39781 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_LSB 0
39782 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field. */
39783 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_MSB 15
39784 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field. */
39785 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_WIDTH 16
39786 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field value. */
39787 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_SET_MSK 0x0000ffff
39788 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field value. */
39789 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_CLR_MSK 0xffff0000
39790 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field. */
39791 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_RESET 0xffff
39792 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI field value from a register. */
39793 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
39794 /* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field value suitable for setting the register. */
39795 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
39796 
39797 /*
39798  * Field : reserved_23_16
39799  *
39800  * Reserved
39801  *
39802  * Field Access Macros:
39803  *
39804  */
39805 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_RSVD_23_16 register field. */
39806 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_RSVD_23_16_LSB 16
39807 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_RSVD_23_16 register field. */
39808 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_RSVD_23_16_MSB 23
39809 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_RSVD_23_16 register field. */
39810 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_RSVD_23_16_WIDTH 8
39811 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_RSVD_23_16 register field value. */
39812 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
39813 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_RSVD_23_16 register field value. */
39814 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
39815 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_RSVD_23_16 register field. */
39816 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_RSVD_23_16_RESET 0x0
39817 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_RSVD_23_16 field value from a register. */
39818 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
39819 /* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_RSVD_23_16 register field value suitable for setting the register. */
39820 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
39821 
39822 /*
39823  * Field : Mask Byte Control - mbc_0
39824  *
39825  * This array of bits are mask control bits for comparison of each of the MAC
39826  * Address bytes. When masked, the MAC does not compare the corresponding byte of
39827  * received DA or SA with the contents of MAC Address21 high and low registers.
39828  * Each bit controls the masking of the bytes. You can filter a group of addresses
39829  * (known as group address filtering) by masking one or more bytes of the address.
39830  *
39831  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
39832  *
39833  * Field Enumeration Values:
39834  *
39835  * Enum | Value | Description
39836  * :----------------------------------------------|:------|:------------
39837  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_E_UNMSKED | 0x0 |
39838  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_E_MSKED | 0x1 |
39839  *
39840  * Field Access Macros:
39841  *
39842  */
39843 /*
39844  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0
39845  *
39846  */
39847 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_E_UNMSKED 0x0
39848 /*
39849  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0
39850  *
39851  */
39852 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_E_MSKED 0x1
39853 
39854 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field. */
39855 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_LSB 24
39856 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field. */
39857 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_MSB 24
39858 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field. */
39859 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_WIDTH 1
39860 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field value. */
39861 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_SET_MSK 0x01000000
39862 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field value. */
39863 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_CLR_MSK 0xfeffffff
39864 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field. */
39865 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_RESET 0x0
39866 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 field value from a register. */
39867 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
39868 /* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field value suitable for setting the register. */
39869 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
39870 
39871 /*
39872  * Field : Mask Byte Control - mbc_1
39873  *
39874  * This array of bits are mask control bits for comparison of each of the MAC
39875  * Address bytes. When masked, the MAC does not compare the corresponding byte of
39876  * received DA or SA with the contents of MAC Address21 high and low registers.
39877  * Each bit controls the masking of the bytes. You can filter a group of addresses
39878  * (known as group address filtering) by masking one or more bytes of the address.
39879  *
39880  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
39881  *
39882  * Field Enumeration Values:
39883  *
39884  * Enum | Value | Description
39885  * :----------------------------------------------|:------|:------------
39886  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_E_UNMSKED | 0x0 |
39887  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_E_MSKED | 0x1 |
39888  *
39889  * Field Access Macros:
39890  *
39891  */
39892 /*
39893  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1
39894  *
39895  */
39896 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_E_UNMSKED 0x0
39897 /*
39898  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1
39899  *
39900  */
39901 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_E_MSKED 0x1
39902 
39903 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field. */
39904 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_LSB 25
39905 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field. */
39906 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_MSB 25
39907 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field. */
39908 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_WIDTH 1
39909 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field value. */
39910 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_SET_MSK 0x02000000
39911 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field value. */
39912 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_CLR_MSK 0xfdffffff
39913 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field. */
39914 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_RESET 0x0
39915 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 field value from a register. */
39916 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
39917 /* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field value suitable for setting the register. */
39918 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
39919 
39920 /*
39921  * Field : Mask Byte Control - mbc_2
39922  *
39923  * This array of bits are mask control bits for comparison of each of the MAC
39924  * Address bytes. When masked, the MAC does not compare the corresponding byte of
39925  * received DA or SA with the contents of MAC Address21 high and low registers.
39926  * Each bit controls the masking of the bytes. You can filter a group of addresses
39927  * (known as group address filtering) by masking one or more bytes of the address.
39928  *
39929  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
39930  *
39931  * Field Enumeration Values:
39932  *
39933  * Enum | Value | Description
39934  * :----------------------------------------------|:------|:------------
39935  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_E_UNMSKED | 0x0 |
39936  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_E_MSKED | 0x1 |
39937  *
39938  * Field Access Macros:
39939  *
39940  */
39941 /*
39942  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2
39943  *
39944  */
39945 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_E_UNMSKED 0x0
39946 /*
39947  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2
39948  *
39949  */
39950 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_E_MSKED 0x1
39951 
39952 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field. */
39953 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_LSB 26
39954 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field. */
39955 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_MSB 26
39956 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field. */
39957 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_WIDTH 1
39958 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field value. */
39959 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_SET_MSK 0x04000000
39960 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field value. */
39961 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_CLR_MSK 0xfbffffff
39962 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field. */
39963 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_RESET 0x0
39964 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 field value from a register. */
39965 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
39966 /* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field value suitable for setting the register. */
39967 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
39968 
39969 /*
39970  * Field : Mask Byte Control - mbc_3
39971  *
39972  * This array of bits are mask control bits for comparison of each of the MAC
39973  * Address bytes. When masked, the MAC does not compare the corresponding byte of
39974  * received DA or SA with the contents of MAC Address21 high and low registers.
39975  * Each bit controls the masking of the bytes. You can filter a group of addresses
39976  * (known as group address filtering) by masking one or more bytes of the address.
39977  *
39978  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
39979  *
39980  * Field Enumeration Values:
39981  *
39982  * Enum | Value | Description
39983  * :----------------------------------------------|:------|:------------
39984  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_E_UNMSKED | 0x0 |
39985  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_E_MSKED | 0x1 |
39986  *
39987  * Field Access Macros:
39988  *
39989  */
39990 /*
39991  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3
39992  *
39993  */
39994 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_E_UNMSKED 0x0
39995 /*
39996  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3
39997  *
39998  */
39999 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_E_MSKED 0x1
40000 
40001 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field. */
40002 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_LSB 27
40003 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field. */
40004 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_MSB 27
40005 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field. */
40006 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_WIDTH 1
40007 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field value. */
40008 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_SET_MSK 0x08000000
40009 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field value. */
40010 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_CLR_MSK 0xf7ffffff
40011 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field. */
40012 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_RESET 0x0
40013 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 field value from a register. */
40014 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
40015 /* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field value suitable for setting the register. */
40016 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
40017 
40018 /*
40019  * Field : Mask Byte Control - mbc_4
40020  *
40021  * This array of bits are mask control bits for comparison of each of the MAC
40022  * Address bytes. When masked, the MAC does not compare the corresponding byte of
40023  * received DA or SA with the contents of MAC Address21 high and low registers.
40024  * Each bit controls the masking of the bytes. You can filter a group of addresses
40025  * (known as group address filtering) by masking one or more bytes of the address.
40026  *
40027  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
40028  *
40029  * Field Enumeration Values:
40030  *
40031  * Enum | Value | Description
40032  * :----------------------------------------------|:------|:------------
40033  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_E_UNMSKED | 0x0 |
40034  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_E_MSKED | 0x1 |
40035  *
40036  * Field Access Macros:
40037  *
40038  */
40039 /*
40040  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4
40041  *
40042  */
40043 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_E_UNMSKED 0x0
40044 /*
40045  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4
40046  *
40047  */
40048 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_E_MSKED 0x1
40049 
40050 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field. */
40051 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_LSB 28
40052 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field. */
40053 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_MSB 28
40054 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field. */
40055 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_WIDTH 1
40056 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field value. */
40057 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_SET_MSK 0x10000000
40058 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field value. */
40059 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_CLR_MSK 0xefffffff
40060 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field. */
40061 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_RESET 0x0
40062 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 field value from a register. */
40063 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
40064 /* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field value suitable for setting the register. */
40065 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
40066 
40067 /*
40068  * Field : Mask Byte Control - mbc_5
40069  *
40070  * This array of bits are mask control bits for comparison of each of the MAC
40071  * Address bytes. When masked, the MAC does not compare the corresponding byte of
40072  * received DA or SA with the contents of MAC Address21 high and low registers.
40073  * Each bit controls the masking of the bytes. You can filter a group of addresses
40074  * (known as group address filtering) by masking one or more bytes of the address.
40075  *
40076  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
40077  *
40078  * Field Enumeration Values:
40079  *
40080  * Enum | Value | Description
40081  * :----------------------------------------------|:------|:------------
40082  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_E_UNMSKED | 0x0 |
40083  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_E_MSKED | 0x1 |
40084  *
40085  * Field Access Macros:
40086  *
40087  */
40088 /*
40089  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5
40090  *
40091  */
40092 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_E_UNMSKED 0x0
40093 /*
40094  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5
40095  *
40096  */
40097 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_E_MSKED 0x1
40098 
40099 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field. */
40100 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_LSB 29
40101 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field. */
40102 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_MSB 29
40103 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field. */
40104 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_WIDTH 1
40105 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field value. */
40106 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_SET_MSK 0x20000000
40107 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field value. */
40108 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_CLR_MSK 0xdfffffff
40109 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field. */
40110 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_RESET 0x0
40111 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 field value from a register. */
40112 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
40113 /* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field value suitable for setting the register. */
40114 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
40115 
40116 /*
40117  * Field : sa
40118  *
40119  * Source Address
40120  *
40121  * When this bit is set, the MAC Address21[47:0] is used to compare with the SA
40122  * fields of the received frame.
40123  *
40124  * When this bit is reset, the MAC Address21[47:0] is used to compare with the DA
40125  * fields of the received frame.
40126  *
40127  * Field Enumeration Values:
40128  *
40129  * Enum | Value | Description
40130  * :----------------------------------------|:------|:------------
40131  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_E_DISD | 0x0 |
40132  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_E_END | 0x1 |
40133  *
40134  * Field Access Macros:
40135  *
40136  */
40137 /*
40138  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA
40139  *
40140  */
40141 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_E_DISD 0x0
40142 /*
40143  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA
40144  *
40145  */
40146 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_E_END 0x1
40147 
40148 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field. */
40149 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_LSB 30
40150 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field. */
40151 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_MSB 30
40152 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field. */
40153 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_WIDTH 1
40154 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field value. */
40155 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_SET_MSK 0x40000000
40156 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field value. */
40157 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_CLR_MSK 0xbfffffff
40158 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field. */
40159 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_RESET 0x0
40160 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA field value from a register. */
40161 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
40162 /* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field value suitable for setting the register. */
40163 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
40164 
40165 /*
40166  * Field : ae
40167  *
40168  * Address Enable
40169  *
40170  * When this bit is set, the address filter module uses the 22nd MAC address for
40171  * perfect filtering.
40172  *
40173  * When this bit is reset, the address filter module ignores the address for
40174  * filtering.
40175  *
40176  * Field Enumeration Values:
40177  *
40178  * Enum | Value | Description
40179  * :----------------------------------------|:------|:------------
40180  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_E_DISD | 0x0 |
40181  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_E_END | 0x1 |
40182  *
40183  * Field Access Macros:
40184  *
40185  */
40186 /*
40187  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE
40188  *
40189  */
40190 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_E_DISD 0x0
40191 /*
40192  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE
40193  *
40194  */
40195 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_E_END 0x1
40196 
40197 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field. */
40198 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_LSB 31
40199 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field. */
40200 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_MSB 31
40201 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field. */
40202 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_WIDTH 1
40203 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field value. */
40204 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_SET_MSK 0x80000000
40205 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field value. */
40206 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_CLR_MSK 0x7fffffff
40207 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field. */
40208 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_RESET 0x0
40209 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE field value from a register. */
40210 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
40211 /* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field value suitable for setting the register. */
40212 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
40213 
40214 #ifndef __ASSEMBLY__
40215 /*
40216  * WARNING: The C register and register group struct declarations are provided for
40217  * convenience and illustrative purposes. They should, however, be used with
40218  * caution as the C language standard provides no guarantees about the alignment or
40219  * atomicity of device memory accesses. The recommended practice for writing
40220  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
40221  * alt_write_word() functions.
40222  *
40223  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR21_HIGH.
40224  */
40225 struct ALT_EMAC_GMAC_MAC_ADDR21_HIGH_s
40226 {
40227  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI */
40228  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR21_HIGH_RSVD_23_16 */
40229  uint32_t mbc_0 : 1; /* Mask Byte Control */
40230  uint32_t mbc_1 : 1; /* Mask Byte Control */
40231  uint32_t mbc_2 : 1; /* Mask Byte Control */
40232  uint32_t mbc_3 : 1; /* Mask Byte Control */
40233  uint32_t mbc_4 : 1; /* Mask Byte Control */
40234  uint32_t mbc_5 : 1; /* Mask Byte Control */
40235  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA */
40236  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE */
40237 };
40238 
40239 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR21_HIGH. */
40240 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR21_HIGH_s ALT_EMAC_GMAC_MAC_ADDR21_HIGH_t;
40241 #endif /* __ASSEMBLY__ */
40242 
40243 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH register. */
40244 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_RESET 0x0000ffff
40245 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH register from the beginning of the component. */
40246 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_OFST 0x828
40247 /* The address of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH register. */
40248 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR21_HIGH_OFST))
40249 
40250 /*
40251  * Register : gmacgrp_mac_address21_low
40252  *
40253  * <b> Register 523 (MAC Address21 Low Register) </b>
40254  *
40255  * The MAC Address21 Low register holds the lower 32 bits of the 22nd 6-byte MAC
40256  * address of the station.
40257  *
40258  * Register Layout
40259  *
40260  * Bits | Access | Reset | Description
40261  * :-------|:-------|:-----------|:------------------------------------
40262  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO
40263  *
40264  */
40265 /*
40266  * Field : addrlo
40267  *
40268  * MAC Address21 [31:0]
40269  *
40270  * This field contains the lower 32 bits of the 22nd 6-byte MAC address. The
40271  * content of this field is undefined until loaded by the Application after the
40272  * initialization process.
40273  *
40274  * Field Access Macros:
40275  *
40276  */
40277 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field. */
40278 #define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_LSB 0
40279 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field. */
40280 #define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_MSB 31
40281 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field. */
40282 #define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_WIDTH 32
40283 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field value. */
40284 #define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_SET_MSK 0xffffffff
40285 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field value. */
40286 #define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_CLR_MSK 0x00000000
40287 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field. */
40288 #define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_RESET 0xffffffff
40289 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO field value from a register. */
40290 #define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
40291 /* Produces a ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field value suitable for setting the register. */
40292 #define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
40293 
40294 #ifndef __ASSEMBLY__
40295 /*
40296  * WARNING: The C register and register group struct declarations are provided for
40297  * convenience and illustrative purposes. They should, however, be used with
40298  * caution as the C language standard provides no guarantees about the alignment or
40299  * atomicity of device memory accesses. The recommended practice for writing
40300  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
40301  * alt_write_word() functions.
40302  *
40303  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR21_LOW.
40304  */
40305 struct ALT_EMAC_GMAC_MAC_ADDR21_LOW_s
40306 {
40307  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO */
40308 };
40309 
40310 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR21_LOW. */
40311 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR21_LOW_s ALT_EMAC_GMAC_MAC_ADDR21_LOW_t;
40312 #endif /* __ASSEMBLY__ */
40313 
40314 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_LOW register. */
40315 #define ALT_EMAC_GMAC_MAC_ADDR21_LOW_RESET 0xffffffff
40316 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR21_LOW register from the beginning of the component. */
40317 #define ALT_EMAC_GMAC_MAC_ADDR21_LOW_OFST 0x82c
40318 /* The address of the ALT_EMAC_GMAC_MAC_ADDR21_LOW register. */
40319 #define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR21_LOW_OFST))
40320 
40321 /*
40322  * Register : gmacgrp_mac_address22_high
40323  *
40324  * <b> Register 524 (MAC Address22 High Register) </b>
40325  *
40326  * The MAC Address22 High register holds the upper 16 bits of the 23rd 6-byte MAC
40327  * address of the station.
40328  *
40329  * If the MAC address registers are configured to be double-synchronized to the
40330  * (G)MII clock domains, then
40331  *
40332  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
40333  * or Bits[7:0] (in big-endian mode) of the MAC Address22 Low Register are written.
40334  * For proper synchronization updates, consecutive writes to this MAC Address22 Low
40335  * Register must be performed after at least four clock cycles in the destination
40336  * clock domain.
40337  *
40338  * Register Layout
40339  *
40340  * Bits | Access | Reset | Description
40341  * :--------|:-------|:-------|:-----------------------------------------
40342  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI
40343  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR22_HIGH_RSVD_23_16
40344  * [24] | RW | 0x0 | Mask Byte Control
40345  * [25] | RW | 0x0 | Mask Byte Control
40346  * [26] | RW | 0x0 | Mask Byte Control
40347  * [27] | RW | 0x0 | Mask Byte Control
40348  * [28] | RW | 0x0 | Mask Byte Control
40349  * [29] | RW | 0x0 | Mask Byte Control
40350  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA
40351  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE
40352  *
40353  */
40354 /*
40355  * Field : addrhi
40356  *
40357  * MAC Address22 [47:32]
40358  *
40359  * This field contains the upper 16 bits (47:32) of the 23rd 6-byte MAC address.
40360  *
40361  * Field Access Macros:
40362  *
40363  */
40364 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field. */
40365 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_LSB 0
40366 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field. */
40367 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_MSB 15
40368 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field. */
40369 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_WIDTH 16
40370 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field value. */
40371 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_SET_MSK 0x0000ffff
40372 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field value. */
40373 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_CLR_MSK 0xffff0000
40374 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field. */
40375 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_RESET 0xffff
40376 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI field value from a register. */
40377 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
40378 /* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field value suitable for setting the register. */
40379 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
40380 
40381 /*
40382  * Field : reserved_23_16
40383  *
40384  * Reserved
40385  *
40386  * Field Access Macros:
40387  *
40388  */
40389 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_RSVD_23_16 register field. */
40390 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_RSVD_23_16_LSB 16
40391 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_RSVD_23_16 register field. */
40392 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_RSVD_23_16_MSB 23
40393 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_RSVD_23_16 register field. */
40394 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_RSVD_23_16_WIDTH 8
40395 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_RSVD_23_16 register field value. */
40396 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
40397 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_RSVD_23_16 register field value. */
40398 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
40399 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_RSVD_23_16 register field. */
40400 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_RSVD_23_16_RESET 0x0
40401 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_RSVD_23_16 field value from a register. */
40402 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
40403 /* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_RSVD_23_16 register field value suitable for setting the register. */
40404 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
40405 
40406 /*
40407  * Field : Mask Byte Control - mbc_0
40408  *
40409  * This array of bits are mask control bits for comparison of each of the MAC
40410  * Address bytes. When masked, the MAC does not compare the corresponding byte of
40411  * received DA or SA with the contents of MAC Address22 high and low registers.
40412  * Each bit controls the masking of the bytes. You can filter a group of addresses
40413  * (known as group address filtering) by masking one or more bytes of the address.
40414  *
40415  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
40416  *
40417  * Field Enumeration Values:
40418  *
40419  * Enum | Value | Description
40420  * :----------------------------------------------|:------|:------------
40421  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_E_UNMSKED | 0x0 |
40422  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_E_MSKED | 0x1 |
40423  *
40424  * Field Access Macros:
40425  *
40426  */
40427 /*
40428  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0
40429  *
40430  */
40431 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_E_UNMSKED 0x0
40432 /*
40433  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0
40434  *
40435  */
40436 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_E_MSKED 0x1
40437 
40438 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field. */
40439 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_LSB 24
40440 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field. */
40441 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_MSB 24
40442 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field. */
40443 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_WIDTH 1
40444 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field value. */
40445 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_SET_MSK 0x01000000
40446 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field value. */
40447 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_CLR_MSK 0xfeffffff
40448 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field. */
40449 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_RESET 0x0
40450 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 field value from a register. */
40451 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
40452 /* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field value suitable for setting the register. */
40453 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
40454 
40455 /*
40456  * Field : Mask Byte Control - mbc_1
40457  *
40458  * This array of bits are mask control bits for comparison of each of the MAC
40459  * Address bytes. When masked, the MAC does not compare the corresponding byte of
40460  * received DA or SA with the contents of MAC Address22 high and low registers.
40461  * Each bit controls the masking of the bytes. You can filter a group of addresses
40462  * (known as group address filtering) by masking one or more bytes of the address.
40463  *
40464  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
40465  *
40466  * Field Enumeration Values:
40467  *
40468  * Enum | Value | Description
40469  * :----------------------------------------------|:------|:------------
40470  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_E_UNMSKED | 0x0 |
40471  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_E_MSKED | 0x1 |
40472  *
40473  * Field Access Macros:
40474  *
40475  */
40476 /*
40477  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1
40478  *
40479  */
40480 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_E_UNMSKED 0x0
40481 /*
40482  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1
40483  *
40484  */
40485 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_E_MSKED 0x1
40486 
40487 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field. */
40488 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_LSB 25
40489 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field. */
40490 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_MSB 25
40491 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field. */
40492 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_WIDTH 1
40493 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field value. */
40494 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_SET_MSK 0x02000000
40495 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field value. */
40496 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_CLR_MSK 0xfdffffff
40497 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field. */
40498 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_RESET 0x0
40499 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 field value from a register. */
40500 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
40501 /* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field value suitable for setting the register. */
40502 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
40503 
40504 /*
40505  * Field : Mask Byte Control - mbc_2
40506  *
40507  * This array of bits are mask control bits for comparison of each of the MAC
40508  * Address bytes. When masked, the MAC does not compare the corresponding byte of
40509  * received DA or SA with the contents of MAC Address22 high and low registers.
40510  * Each bit controls the masking of the bytes. You can filter a group of addresses
40511  * (known as group address filtering) by masking one or more bytes of the address.
40512  *
40513  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
40514  *
40515  * Field Enumeration Values:
40516  *
40517  * Enum | Value | Description
40518  * :----------------------------------------------|:------|:------------
40519  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_E_UNMSKED | 0x0 |
40520  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_E_MSKED | 0x1 |
40521  *
40522  * Field Access Macros:
40523  *
40524  */
40525 /*
40526  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2
40527  *
40528  */
40529 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_E_UNMSKED 0x0
40530 /*
40531  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2
40532  *
40533  */
40534 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_E_MSKED 0x1
40535 
40536 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field. */
40537 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_LSB 26
40538 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field. */
40539 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_MSB 26
40540 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field. */
40541 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_WIDTH 1
40542 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field value. */
40543 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_SET_MSK 0x04000000
40544 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field value. */
40545 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_CLR_MSK 0xfbffffff
40546 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field. */
40547 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_RESET 0x0
40548 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 field value from a register. */
40549 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
40550 /* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field value suitable for setting the register. */
40551 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
40552 
40553 /*
40554  * Field : Mask Byte Control - mbc_3
40555  *
40556  * This array of bits are mask control bits for comparison of each of the MAC
40557  * Address bytes. When masked, the MAC does not compare the corresponding byte of
40558  * received DA or SA with the contents of MAC Address22 high and low registers.
40559  * Each bit controls the masking of the bytes. You can filter a group of addresses
40560  * (known as group address filtering) by masking one or more bytes of the address.
40561  *
40562  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
40563  *
40564  * Field Enumeration Values:
40565  *
40566  * Enum | Value | Description
40567  * :----------------------------------------------|:------|:------------
40568  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_E_UNMSKED | 0x0 |
40569  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_E_MSKED | 0x1 |
40570  *
40571  * Field Access Macros:
40572  *
40573  */
40574 /*
40575  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3
40576  *
40577  */
40578 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_E_UNMSKED 0x0
40579 /*
40580  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3
40581  *
40582  */
40583 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_E_MSKED 0x1
40584 
40585 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field. */
40586 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_LSB 27
40587 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field. */
40588 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_MSB 27
40589 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field. */
40590 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_WIDTH 1
40591 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field value. */
40592 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_SET_MSK 0x08000000
40593 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field value. */
40594 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_CLR_MSK 0xf7ffffff
40595 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field. */
40596 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_RESET 0x0
40597 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 field value from a register. */
40598 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
40599 /* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field value suitable for setting the register. */
40600 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
40601 
40602 /*
40603  * Field : Mask Byte Control - mbc_4
40604  *
40605  * This array of bits are mask control bits for comparison of each of the MAC
40606  * Address bytes. When masked, the MAC does not compare the corresponding byte of
40607  * received DA or SA with the contents of MAC Address22 high and low registers.
40608  * Each bit controls the masking of the bytes. You can filter a group of addresses
40609  * (known as group address filtering) by masking one or more bytes of the address.
40610  *
40611  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
40612  *
40613  * Field Enumeration Values:
40614  *
40615  * Enum | Value | Description
40616  * :----------------------------------------------|:------|:------------
40617  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_E_UNMSKED | 0x0 |
40618  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_E_MSKED | 0x1 |
40619  *
40620  * Field Access Macros:
40621  *
40622  */
40623 /*
40624  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4
40625  *
40626  */
40627 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_E_UNMSKED 0x0
40628 /*
40629  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4
40630  *
40631  */
40632 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_E_MSKED 0x1
40633 
40634 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field. */
40635 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_LSB 28
40636 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field. */
40637 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_MSB 28
40638 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field. */
40639 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_WIDTH 1
40640 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field value. */
40641 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_SET_MSK 0x10000000
40642 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field value. */
40643 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_CLR_MSK 0xefffffff
40644 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field. */
40645 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_RESET 0x0
40646 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 field value from a register. */
40647 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
40648 /* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field value suitable for setting the register. */
40649 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
40650 
40651 /*
40652  * Field : Mask Byte Control - mbc_5
40653  *
40654  * This array of bits are mask control bits for comparison of each of the MAC
40655  * Address bytes. When masked, the MAC does not compare the corresponding byte of
40656  * received DA or SA with the contents of MAC Address22 high and low registers.
40657  * Each bit controls the masking of the bytes. You can filter a group of addresses
40658  * (known as group address filtering) by masking one or more bytes of the address.
40659  *
40660  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
40661  *
40662  * Field Enumeration Values:
40663  *
40664  * Enum | Value | Description
40665  * :----------------------------------------------|:------|:------------
40666  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_E_UNMSKED | 0x0 |
40667  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_E_MSKED | 0x1 |
40668  *
40669  * Field Access Macros:
40670  *
40671  */
40672 /*
40673  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5
40674  *
40675  */
40676 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_E_UNMSKED 0x0
40677 /*
40678  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5
40679  *
40680  */
40681 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_E_MSKED 0x1
40682 
40683 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field. */
40684 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_LSB 29
40685 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field. */
40686 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_MSB 29
40687 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field. */
40688 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_WIDTH 1
40689 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field value. */
40690 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_SET_MSK 0x20000000
40691 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field value. */
40692 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_CLR_MSK 0xdfffffff
40693 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field. */
40694 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_RESET 0x0
40695 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 field value from a register. */
40696 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
40697 /* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field value suitable for setting the register. */
40698 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
40699 
40700 /*
40701  * Field : sa
40702  *
40703  * Source Address
40704  *
40705  * When this bit is set, the MAC Address22[47:0] is used to compare with the SA
40706  * fields of the received frame.
40707  *
40708  * When this bit is reset, the MAC Address22[47:0] is used to compare with the DA
40709  * fields of the received frame.
40710  *
40711  * Field Enumeration Values:
40712  *
40713  * Enum | Value | Description
40714  * :----------------------------------------|:------|:------------
40715  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_E_DISD | 0x0 |
40716  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_E_END | 0x1 |
40717  *
40718  * Field Access Macros:
40719  *
40720  */
40721 /*
40722  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA
40723  *
40724  */
40725 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_E_DISD 0x0
40726 /*
40727  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA
40728  *
40729  */
40730 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_E_END 0x1
40731 
40732 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field. */
40733 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_LSB 30
40734 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field. */
40735 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_MSB 30
40736 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field. */
40737 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_WIDTH 1
40738 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field value. */
40739 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_SET_MSK 0x40000000
40740 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field value. */
40741 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_CLR_MSK 0xbfffffff
40742 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field. */
40743 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_RESET 0x0
40744 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA field value from a register. */
40745 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
40746 /* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field value suitable for setting the register. */
40747 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
40748 
40749 /*
40750  * Field : ae
40751  *
40752  * Address Enable
40753  *
40754  * When this bit is set, the address filter module uses the 23rd MAC address for
40755  * perfect filtering.
40756  *
40757  * When this bit is reset, the address filter module ignores the address for
40758  * filtering.
40759  *
40760  * Field Enumeration Values:
40761  *
40762  * Enum | Value | Description
40763  * :----------------------------------------|:------|:------------
40764  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_E_DISD | 0x0 |
40765  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_E_END | 0x1 |
40766  *
40767  * Field Access Macros:
40768  *
40769  */
40770 /*
40771  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE
40772  *
40773  */
40774 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_E_DISD 0x0
40775 /*
40776  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE
40777  *
40778  */
40779 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_E_END 0x1
40780 
40781 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field. */
40782 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_LSB 31
40783 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field. */
40784 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_MSB 31
40785 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field. */
40786 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_WIDTH 1
40787 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field value. */
40788 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_SET_MSK 0x80000000
40789 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field value. */
40790 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_CLR_MSK 0x7fffffff
40791 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field. */
40792 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_RESET 0x0
40793 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE field value from a register. */
40794 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
40795 /* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field value suitable for setting the register. */
40796 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
40797 
40798 #ifndef __ASSEMBLY__
40799 /*
40800  * WARNING: The C register and register group struct declarations are provided for
40801  * convenience and illustrative purposes. They should, however, be used with
40802  * caution as the C language standard provides no guarantees about the alignment or
40803  * atomicity of device memory accesses. The recommended practice for writing
40804  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
40805  * alt_write_word() functions.
40806  *
40807  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR22_HIGH.
40808  */
40809 struct ALT_EMAC_GMAC_MAC_ADDR22_HIGH_s
40810 {
40811  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI */
40812  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR22_HIGH_RSVD_23_16 */
40813  uint32_t mbc_0 : 1; /* Mask Byte Control */
40814  uint32_t mbc_1 : 1; /* Mask Byte Control */
40815  uint32_t mbc_2 : 1; /* Mask Byte Control */
40816  uint32_t mbc_3 : 1; /* Mask Byte Control */
40817  uint32_t mbc_4 : 1; /* Mask Byte Control */
40818  uint32_t mbc_5 : 1; /* Mask Byte Control */
40819  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA */
40820  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE */
40821 };
40822 
40823 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR22_HIGH. */
40824 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR22_HIGH_s ALT_EMAC_GMAC_MAC_ADDR22_HIGH_t;
40825 #endif /* __ASSEMBLY__ */
40826 
40827 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH register. */
40828 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_RESET 0x0000ffff
40829 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH register from the beginning of the component. */
40830 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_OFST 0x830
40831 /* The address of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH register. */
40832 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR22_HIGH_OFST))
40833 
40834 /*
40835  * Register : gmacgrp_mac_address22_low
40836  *
40837  * <b> Register 525 (MAC Address22 Low Register) </b>
40838  *
40839  * The MAC Address22 Low register holds the lower 32 bits of the 23rd 6-byte MAC
40840  * address of the station.
40841  *
40842  * Register Layout
40843  *
40844  * Bits | Access | Reset | Description
40845  * :-------|:-------|:-----------|:------------------------------------
40846  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO
40847  *
40848  */
40849 /*
40850  * Field : addrlo
40851  *
40852  * MAC Address22 [31:0]
40853  *
40854  * This field contains the lower 32 bits of the 23rd 6-byte MAC address. The
40855  * content of this field is undefined until loaded by the Application after the
40856  * initialization process.
40857  *
40858  * Field Access Macros:
40859  *
40860  */
40861 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field. */
40862 #define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_LSB 0
40863 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field. */
40864 #define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_MSB 31
40865 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field. */
40866 #define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_WIDTH 32
40867 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field value. */
40868 #define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_SET_MSK 0xffffffff
40869 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field value. */
40870 #define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_CLR_MSK 0x00000000
40871 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field. */
40872 #define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_RESET 0xffffffff
40873 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO field value from a register. */
40874 #define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
40875 /* Produces a ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field value suitable for setting the register. */
40876 #define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
40877 
40878 #ifndef __ASSEMBLY__
40879 /*
40880  * WARNING: The C register and register group struct declarations are provided for
40881  * convenience and illustrative purposes. They should, however, be used with
40882  * caution as the C language standard provides no guarantees about the alignment or
40883  * atomicity of device memory accesses. The recommended practice for writing
40884  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
40885  * alt_write_word() functions.
40886  *
40887  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR22_LOW.
40888  */
40889 struct ALT_EMAC_GMAC_MAC_ADDR22_LOW_s
40890 {
40891  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO */
40892 };
40893 
40894 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR22_LOW. */
40895 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR22_LOW_s ALT_EMAC_GMAC_MAC_ADDR22_LOW_t;
40896 #endif /* __ASSEMBLY__ */
40897 
40898 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_LOW register. */
40899 #define ALT_EMAC_GMAC_MAC_ADDR22_LOW_RESET 0xffffffff
40900 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR22_LOW register from the beginning of the component. */
40901 #define ALT_EMAC_GMAC_MAC_ADDR22_LOW_OFST 0x834
40902 /* The address of the ALT_EMAC_GMAC_MAC_ADDR22_LOW register. */
40903 #define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR22_LOW_OFST))
40904 
40905 /*
40906  * Register : gmacgrp_mac_address23_high
40907  *
40908  * <b> Register 526 (MAC Address23 High Register </b>
40909  *
40910  * The MAC Address23 High register holds the upper 16 bits of the 24th 6-byte MAC
40911  * address of the station.
40912  *
40913  * If the MAC address registers are configured to be double-synchronized to the
40914  * (G)MII clock domains, then
40915  *
40916  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
40917  * or Bits[7:0] (in big-endian mode) of the MAC Address23 Low Register are written.
40918  * For proper synchronization updates, consecutive writes to this MAC Address23 Low
40919  * Register must be performed after at least four clock cycles in the destination
40920  * clock domain.
40921  *
40922  * Register Layout
40923  *
40924  * Bits | Access | Reset | Description
40925  * :--------|:-------|:-------|:-----------------------------------------
40926  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI
40927  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR23_HIGH_RSVD_23_16
40928  * [24] | RW | 0x0 | Mask Byte Control
40929  * [25] | RW | 0x0 | Mask Byte Control
40930  * [26] | RW | 0x0 | Mask Byte Control
40931  * [27] | RW | 0x0 | Mask Byte Control
40932  * [28] | RW | 0x0 | Mask Byte Control
40933  * [29] | RW | 0x0 | Mask Byte Control
40934  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA
40935  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE
40936  *
40937  */
40938 /*
40939  * Field : addrhi
40940  *
40941  * MAC Address23 [47:32]
40942  *
40943  * This field contains the upper 16 bits (47:32) of the 24th 6-byte MAC address.
40944  *
40945  * Field Access Macros:
40946  *
40947  */
40948 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field. */
40949 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_LSB 0
40950 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field. */
40951 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_MSB 15
40952 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field. */
40953 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_WIDTH 16
40954 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field value. */
40955 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_SET_MSK 0x0000ffff
40956 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field value. */
40957 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_CLR_MSK 0xffff0000
40958 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field. */
40959 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_RESET 0xffff
40960 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI field value from a register. */
40961 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
40962 /* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field value suitable for setting the register. */
40963 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
40964 
40965 /*
40966  * Field : reserved_23_16
40967  *
40968  * Reserved
40969  *
40970  * Field Access Macros:
40971  *
40972  */
40973 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_RSVD_23_16 register field. */
40974 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_RSVD_23_16_LSB 16
40975 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_RSVD_23_16 register field. */
40976 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_RSVD_23_16_MSB 23
40977 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_RSVD_23_16 register field. */
40978 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_RSVD_23_16_WIDTH 8
40979 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_RSVD_23_16 register field value. */
40980 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
40981 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_RSVD_23_16 register field value. */
40982 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
40983 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_RSVD_23_16 register field. */
40984 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_RSVD_23_16_RESET 0x0
40985 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_RSVD_23_16 field value from a register. */
40986 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
40987 /* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_RSVD_23_16 register field value suitable for setting the register. */
40988 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
40989 
40990 /*
40991  * Field : Mask Byte Control - mbc_0
40992  *
40993  * This array of bits are mask control bits for comparison of each of the MAC
40994  * Address bytes. When masked, the MAC does not compare the corresponding byte of
40995  * received DA or SA with the contents of MAC Address23 high and low registers.
40996  * Each bit controls the masking of the bytes. You can filter a group of addresses
40997  * (known as group address filtering) by masking one or more bytes of the address.
40998  *
40999  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
41000  *
41001  * Field Enumeration Values:
41002  *
41003  * Enum | Value | Description
41004  * :----------------------------------------------|:------|:------------
41005  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_E_UNMSKED | 0x0 |
41006  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_E_MSKED | 0x1 |
41007  *
41008  * Field Access Macros:
41009  *
41010  */
41011 /*
41012  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0
41013  *
41014  */
41015 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_E_UNMSKED 0x0
41016 /*
41017  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0
41018  *
41019  */
41020 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_E_MSKED 0x1
41021 
41022 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field. */
41023 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_LSB 24
41024 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field. */
41025 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_MSB 24
41026 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field. */
41027 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_WIDTH 1
41028 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field value. */
41029 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_SET_MSK 0x01000000
41030 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field value. */
41031 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_CLR_MSK 0xfeffffff
41032 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field. */
41033 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_RESET 0x0
41034 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 field value from a register. */
41035 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
41036 /* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field value suitable for setting the register. */
41037 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
41038 
41039 /*
41040  * Field : Mask Byte Control - mbc_1
41041  *
41042  * This array of bits are mask control bits for comparison of each of the MAC
41043  * Address bytes. When masked, the MAC does not compare the corresponding byte of
41044  * received DA or SA with the contents of MAC Address23 high and low registers.
41045  * Each bit controls the masking of the bytes. You can filter a group of addresses
41046  * (known as group address filtering) by masking one or more bytes of the address.
41047  *
41048  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
41049  *
41050  * Field Enumeration Values:
41051  *
41052  * Enum | Value | Description
41053  * :----------------------------------------------|:------|:------------
41054  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_E_UNMSKED | 0x0 |
41055  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_E_MSKED | 0x1 |
41056  *
41057  * Field Access Macros:
41058  *
41059  */
41060 /*
41061  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1
41062  *
41063  */
41064 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_E_UNMSKED 0x0
41065 /*
41066  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1
41067  *
41068  */
41069 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_E_MSKED 0x1
41070 
41071 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field. */
41072 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_LSB 25
41073 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field. */
41074 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_MSB 25
41075 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field. */
41076 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_WIDTH 1
41077 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field value. */
41078 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_SET_MSK 0x02000000
41079 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field value. */
41080 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_CLR_MSK 0xfdffffff
41081 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field. */
41082 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_RESET 0x0
41083 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 field value from a register. */
41084 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
41085 /* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field value suitable for setting the register. */
41086 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
41087 
41088 /*
41089  * Field : Mask Byte Control - mbc_2
41090  *
41091  * This array of bits are mask control bits for comparison of each of the MAC
41092  * Address bytes. When masked, the MAC does not compare the corresponding byte of
41093  * received DA or SA with the contents of MAC Address23 high and low registers.
41094  * Each bit controls the masking of the bytes. You can filter a group of addresses
41095  * (known as group address filtering) by masking one or more bytes of the address.
41096  *
41097  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
41098  *
41099  * Field Enumeration Values:
41100  *
41101  * Enum | Value | Description
41102  * :----------------------------------------------|:------|:------------
41103  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_E_UNMSKED | 0x0 |
41104  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_E_MSKED | 0x1 |
41105  *
41106  * Field Access Macros:
41107  *
41108  */
41109 /*
41110  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2
41111  *
41112  */
41113 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_E_UNMSKED 0x0
41114 /*
41115  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2
41116  *
41117  */
41118 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_E_MSKED 0x1
41119 
41120 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field. */
41121 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_LSB 26
41122 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field. */
41123 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_MSB 26
41124 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field. */
41125 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_WIDTH 1
41126 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field value. */
41127 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_SET_MSK 0x04000000
41128 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field value. */
41129 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_CLR_MSK 0xfbffffff
41130 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field. */
41131 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_RESET 0x0
41132 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 field value from a register. */
41133 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
41134 /* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field value suitable for setting the register. */
41135 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
41136 
41137 /*
41138  * Field : Mask Byte Control - mbc_3
41139  *
41140  * This array of bits are mask control bits for comparison of each of the MAC
41141  * Address bytes. When masked, the MAC does not compare the corresponding byte of
41142  * received DA or SA with the contents of MAC Address23 high and low registers.
41143  * Each bit controls the masking of the bytes. You can filter a group of addresses
41144  * (known as group address filtering) by masking one or more bytes of the address.
41145  *
41146  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
41147  *
41148  * Field Enumeration Values:
41149  *
41150  * Enum | Value | Description
41151  * :----------------------------------------------|:------|:------------
41152  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_E_UNMSKED | 0x0 |
41153  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_E_MSKED | 0x1 |
41154  *
41155  * Field Access Macros:
41156  *
41157  */
41158 /*
41159  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3
41160  *
41161  */
41162 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_E_UNMSKED 0x0
41163 /*
41164  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3
41165  *
41166  */
41167 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_E_MSKED 0x1
41168 
41169 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field. */
41170 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_LSB 27
41171 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field. */
41172 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_MSB 27
41173 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field. */
41174 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_WIDTH 1
41175 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field value. */
41176 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_SET_MSK 0x08000000
41177 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field value. */
41178 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_CLR_MSK 0xf7ffffff
41179 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field. */
41180 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_RESET 0x0
41181 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 field value from a register. */
41182 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
41183 /* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field value suitable for setting the register. */
41184 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
41185 
41186 /*
41187  * Field : Mask Byte Control - mbc_4
41188  *
41189  * This array of bits are mask control bits for comparison of each of the MAC
41190  * Address bytes. When masked, the MAC does not compare the corresponding byte of
41191  * received DA or SA with the contents of MAC Address23 high and low registers.
41192  * Each bit controls the masking of the bytes. You can filter a group of addresses
41193  * (known as group address filtering) by masking one or more bytes of the address.
41194  *
41195  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
41196  *
41197  * Field Enumeration Values:
41198  *
41199  * Enum | Value | Description
41200  * :----------------------------------------------|:------|:------------
41201  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_E_UNMSKED | 0x0 |
41202  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_E_MSKED | 0x1 |
41203  *
41204  * Field Access Macros:
41205  *
41206  */
41207 /*
41208  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4
41209  *
41210  */
41211 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_E_UNMSKED 0x0
41212 /*
41213  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4
41214  *
41215  */
41216 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_E_MSKED 0x1
41217 
41218 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field. */
41219 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_LSB 28
41220 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field. */
41221 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_MSB 28
41222 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field. */
41223 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_WIDTH 1
41224 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field value. */
41225 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_SET_MSK 0x10000000
41226 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field value. */
41227 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_CLR_MSK 0xefffffff
41228 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field. */
41229 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_RESET 0x0
41230 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 field value from a register. */
41231 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
41232 /* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field value suitable for setting the register. */
41233 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
41234 
41235 /*
41236  * Field : Mask Byte Control - mbc_5
41237  *
41238  * This array of bits are mask control bits for comparison of each of the MAC
41239  * Address bytes. When masked, the MAC does not compare the corresponding byte of
41240  * received DA or SA with the contents of MAC Address23 high and low registers.
41241  * Each bit controls the masking of the bytes. You can filter a group of addresses
41242  * (known as group address filtering) by masking one or more bytes of the address.
41243  *
41244  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
41245  *
41246  * Field Enumeration Values:
41247  *
41248  * Enum | Value | Description
41249  * :----------------------------------------------|:------|:------------
41250  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_E_UNMSKED | 0x0 |
41251  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_E_MSKED | 0x1 |
41252  *
41253  * Field Access Macros:
41254  *
41255  */
41256 /*
41257  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5
41258  *
41259  */
41260 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_E_UNMSKED 0x0
41261 /*
41262  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5
41263  *
41264  */
41265 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_E_MSKED 0x1
41266 
41267 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field. */
41268 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_LSB 29
41269 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field. */
41270 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_MSB 29
41271 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field. */
41272 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_WIDTH 1
41273 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field value. */
41274 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_SET_MSK 0x20000000
41275 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field value. */
41276 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_CLR_MSK 0xdfffffff
41277 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field. */
41278 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_RESET 0x0
41279 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 field value from a register. */
41280 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
41281 /* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field value suitable for setting the register. */
41282 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
41283 
41284 /*
41285  * Field : sa
41286  *
41287  * Source Address
41288  *
41289  * When this bit is set, the MAC Address23[47:0] is used to compare with the SA
41290  * fields of the received frame.
41291  *
41292  * When this bit is reset, the MAC Address23[47:0] is used to compare with the DA
41293  * fields of the received frame.
41294  *
41295  * Field Enumeration Values:
41296  *
41297  * Enum | Value | Description
41298  * :----------------------------------------|:------|:------------
41299  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_E_DISD | 0x0 |
41300  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_E_END | 0x1 |
41301  *
41302  * Field Access Macros:
41303  *
41304  */
41305 /*
41306  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA
41307  *
41308  */
41309 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_E_DISD 0x0
41310 /*
41311  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA
41312  *
41313  */
41314 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_E_END 0x1
41315 
41316 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field. */
41317 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_LSB 30
41318 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field. */
41319 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_MSB 30
41320 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field. */
41321 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_WIDTH 1
41322 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field value. */
41323 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_SET_MSK 0x40000000
41324 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field value. */
41325 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_CLR_MSK 0xbfffffff
41326 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field. */
41327 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_RESET 0x0
41328 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA field value from a register. */
41329 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
41330 /* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field value suitable for setting the register. */
41331 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
41332 
41333 /*
41334  * Field : ae
41335  *
41336  * Address Enable
41337  *
41338  * When this bit is set, the address filter module uses the 24th MAC address for
41339  * perfect filtering.
41340  *
41341  * When this bit is reset, the address filter module ignores the address for
41342  * filtering.
41343  *
41344  * Field Enumeration Values:
41345  *
41346  * Enum | Value | Description
41347  * :----------------------------------------|:------|:------------
41348  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_E_DISD | 0x0 |
41349  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_E_END | 0x1 |
41350  *
41351  * Field Access Macros:
41352  *
41353  */
41354 /*
41355  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE
41356  *
41357  */
41358 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_E_DISD 0x0
41359 /*
41360  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE
41361  *
41362  */
41363 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_E_END 0x1
41364 
41365 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field. */
41366 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_LSB 31
41367 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field. */
41368 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_MSB 31
41369 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field. */
41370 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_WIDTH 1
41371 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field value. */
41372 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_SET_MSK 0x80000000
41373 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field value. */
41374 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_CLR_MSK 0x7fffffff
41375 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field. */
41376 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_RESET 0x0
41377 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE field value from a register. */
41378 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
41379 /* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field value suitable for setting the register. */
41380 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
41381 
41382 #ifndef __ASSEMBLY__
41383 /*
41384  * WARNING: The C register and register group struct declarations are provided for
41385  * convenience and illustrative purposes. They should, however, be used with
41386  * caution as the C language standard provides no guarantees about the alignment or
41387  * atomicity of device memory accesses. The recommended practice for writing
41388  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
41389  * alt_write_word() functions.
41390  *
41391  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR23_HIGH.
41392  */
41393 struct ALT_EMAC_GMAC_MAC_ADDR23_HIGH_s
41394 {
41395  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI */
41396  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR23_HIGH_RSVD_23_16 */
41397  uint32_t mbc_0 : 1; /* Mask Byte Control */
41398  uint32_t mbc_1 : 1; /* Mask Byte Control */
41399  uint32_t mbc_2 : 1; /* Mask Byte Control */
41400  uint32_t mbc_3 : 1; /* Mask Byte Control */
41401  uint32_t mbc_4 : 1; /* Mask Byte Control */
41402  uint32_t mbc_5 : 1; /* Mask Byte Control */
41403  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA */
41404  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE */
41405 };
41406 
41407 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR23_HIGH. */
41408 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR23_HIGH_s ALT_EMAC_GMAC_MAC_ADDR23_HIGH_t;
41409 #endif /* __ASSEMBLY__ */
41410 
41411 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH register. */
41412 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_RESET 0x0000ffff
41413 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH register from the beginning of the component. */
41414 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_OFST 0x838
41415 /* The address of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH register. */
41416 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR23_HIGH_OFST))
41417 
41418 /*
41419  * Register : gmacgrp_mac_address23_low
41420  *
41421  * <b> Register 527 (MAC Address23 Low Register) </b>
41422  *
41423  * The MAC Address23 Low register holds the lower 32 bits of the 24th 6-byte MAC
41424  * address of the station.
41425  *
41426  * Register Layout
41427  *
41428  * Bits | Access | Reset | Description
41429  * :-------|:-------|:-----------|:------------------------------------
41430  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO
41431  *
41432  */
41433 /*
41434  * Field : addrlo
41435  *
41436  * MAC Address23 [31:0]
41437  *
41438  * This field contains the lower 32 bits of the 24th 6-byte MAC address. The
41439  * content of this field is undefined until loaded by the Application after the
41440  * initialization process.
41441  *
41442  * Field Access Macros:
41443  *
41444  */
41445 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field. */
41446 #define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_LSB 0
41447 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field. */
41448 #define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_MSB 31
41449 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field. */
41450 #define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_WIDTH 32
41451 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field value. */
41452 #define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_SET_MSK 0xffffffff
41453 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field value. */
41454 #define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_CLR_MSK 0x00000000
41455 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field. */
41456 #define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_RESET 0xffffffff
41457 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO field value from a register. */
41458 #define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
41459 /* Produces a ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field value suitable for setting the register. */
41460 #define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
41461 
41462 #ifndef __ASSEMBLY__
41463 /*
41464  * WARNING: The C register and register group struct declarations are provided for
41465  * convenience and illustrative purposes. They should, however, be used with
41466  * caution as the C language standard provides no guarantees about the alignment or
41467  * atomicity of device memory accesses. The recommended practice for writing
41468  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
41469  * alt_write_word() functions.
41470  *
41471  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR23_LOW.
41472  */
41473 struct ALT_EMAC_GMAC_MAC_ADDR23_LOW_s
41474 {
41475  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO */
41476 };
41477 
41478 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR23_LOW. */
41479 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR23_LOW_s ALT_EMAC_GMAC_MAC_ADDR23_LOW_t;
41480 #endif /* __ASSEMBLY__ */
41481 
41482 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_LOW register. */
41483 #define ALT_EMAC_GMAC_MAC_ADDR23_LOW_RESET 0xffffffff
41484 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR23_LOW register from the beginning of the component. */
41485 #define ALT_EMAC_GMAC_MAC_ADDR23_LOW_OFST 0x83c
41486 /* The address of the ALT_EMAC_GMAC_MAC_ADDR23_LOW register. */
41487 #define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR23_LOW_OFST))
41488 
41489 /*
41490  * Register : gmacgrp_mac_address24_high
41491  *
41492  * <b> Register 528 (MAC Address24 High Register) </b>
41493  *
41494  * The MAC Address24 High register holds the upper 16 bits of the 25th 6-byte MAC
41495  * address of the station.
41496  *
41497  * If the MAC address registers are configured to be double-synchronized to the
41498  * (G)MII clock domains, then
41499  *
41500  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
41501  * or Bits[7:0] (in big-endian mode) of the MAC Address24 Low Register are written.
41502  * For proper synchronization updates, consecutive writes to this MAC Address24 Low
41503  * Register must be performed after at least four clock cycles in the destination
41504  * clock domain.
41505  *
41506  * Register Layout
41507  *
41508  * Bits | Access | Reset | Description
41509  * :--------|:-------|:-------|:-----------------------------------------
41510  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI
41511  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR24_HIGH_RSVD_23_16
41512  * [24] | RW | 0x0 | Mask Byte Control
41513  * [25] | RW | 0x0 | Mask Byte Control
41514  * [26] | RW | 0x0 | Mask Byte Control
41515  * [27] | RW | 0x0 | Mask Byte Control
41516  * [28] | RW | 0x0 | Mask Byte Control
41517  * [29] | RW | 0x0 | Mask Byte Control
41518  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA
41519  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE
41520  *
41521  */
41522 /*
41523  * Field : addrhi
41524  *
41525  * MAC Address1 [47:32]
41526  *
41527  * This field contains the upper 16 bits (47:32) of the 25th 6-byte MAC address.
41528  *
41529  * Field Access Macros:
41530  *
41531  */
41532 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field. */
41533 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_LSB 0
41534 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field. */
41535 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_MSB 15
41536 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field. */
41537 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_WIDTH 16
41538 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field value. */
41539 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_SET_MSK 0x0000ffff
41540 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field value. */
41541 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_CLR_MSK 0xffff0000
41542 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field. */
41543 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_RESET 0xffff
41544 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI field value from a register. */
41545 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
41546 /* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field value suitable for setting the register. */
41547 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
41548 
41549 /*
41550  * Field : reserved_23_16
41551  *
41552  * Reserved
41553  *
41554  * Field Access Macros:
41555  *
41556  */
41557 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_RSVD_23_16 register field. */
41558 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_RSVD_23_16_LSB 16
41559 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_RSVD_23_16 register field. */
41560 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_RSVD_23_16_MSB 23
41561 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_RSVD_23_16 register field. */
41562 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_RSVD_23_16_WIDTH 8
41563 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_RSVD_23_16 register field value. */
41564 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
41565 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_RSVD_23_16 register field value. */
41566 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
41567 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_RSVD_23_16 register field. */
41568 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_RSVD_23_16_RESET 0x0
41569 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_RSVD_23_16 field value from a register. */
41570 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
41571 /* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_RSVD_23_16 register field value suitable for setting the register. */
41572 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
41573 
41574 /*
41575  * Field : Mask Byte Control - mbc_0
41576  *
41577  * This array of bits are mask control bits for comparison of each of the MAC
41578  * Address bytes. When masked, the MAC does not compare the corresponding byte of
41579  * received DA or SA with the contents of MAC Address24 high and low registers.
41580  * Each bit controls the masking of the bytes. You can filter a group of addresses
41581  * (known as group address filtering) by masking one or more bytes of the address.
41582  *
41583  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
41584  *
41585  * Field Enumeration Values:
41586  *
41587  * Enum | Value | Description
41588  * :----------------------------------------------|:------|:------------
41589  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_E_UNMSKED | 0x0 |
41590  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_E_MSKED | 0x1 |
41591  *
41592  * Field Access Macros:
41593  *
41594  */
41595 /*
41596  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0
41597  *
41598  */
41599 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_E_UNMSKED 0x0
41600 /*
41601  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0
41602  *
41603  */
41604 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_E_MSKED 0x1
41605 
41606 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field. */
41607 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_LSB 24
41608 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field. */
41609 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_MSB 24
41610 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field. */
41611 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_WIDTH 1
41612 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field value. */
41613 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_SET_MSK 0x01000000
41614 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field value. */
41615 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_CLR_MSK 0xfeffffff
41616 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field. */
41617 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_RESET 0x0
41618 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 field value from a register. */
41619 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
41620 /* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field value suitable for setting the register. */
41621 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
41622 
41623 /*
41624  * Field : Mask Byte Control - mbc_1
41625  *
41626  * This array of bits are mask control bits for comparison of each of the MAC
41627  * Address bytes. When masked, the MAC does not compare the corresponding byte of
41628  * received DA or SA with the contents of MAC Address24 high and low registers.
41629  * Each bit controls the masking of the bytes. You can filter a group of addresses
41630  * (known as group address filtering) by masking one or more bytes of the address.
41631  *
41632  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
41633  *
41634  * Field Enumeration Values:
41635  *
41636  * Enum | Value | Description
41637  * :----------------------------------------------|:------|:------------
41638  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_E_UNMSKED | 0x0 |
41639  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_E_MSKED | 0x1 |
41640  *
41641  * Field Access Macros:
41642  *
41643  */
41644 /*
41645  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1
41646  *
41647  */
41648 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_E_UNMSKED 0x0
41649 /*
41650  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1
41651  *
41652  */
41653 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_E_MSKED 0x1
41654 
41655 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field. */
41656 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_LSB 25
41657 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field. */
41658 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_MSB 25
41659 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field. */
41660 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_WIDTH 1
41661 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field value. */
41662 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_SET_MSK 0x02000000
41663 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field value. */
41664 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_CLR_MSK 0xfdffffff
41665 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field. */
41666 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_RESET 0x0
41667 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 field value from a register. */
41668 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
41669 /* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field value suitable for setting the register. */
41670 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
41671 
41672 /*
41673  * Field : Mask Byte Control - mbc_2
41674  *
41675  * This array of bits are mask control bits for comparison of each of the MAC
41676  * Address bytes. When masked, the MAC does not compare the corresponding byte of
41677  * received DA or SA with the contents of MAC Address24 high and low registers.
41678  * Each bit controls the masking of the bytes. You can filter a group of addresses
41679  * (known as group address filtering) by masking one or more bytes of the address.
41680  *
41681  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
41682  *
41683  * Field Enumeration Values:
41684  *
41685  * Enum | Value | Description
41686  * :----------------------------------------------|:------|:------------
41687  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_E_UNMSKED | 0x0 |
41688  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_E_MSKED | 0x1 |
41689  *
41690  * Field Access Macros:
41691  *
41692  */
41693 /*
41694  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2
41695  *
41696  */
41697 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_E_UNMSKED 0x0
41698 /*
41699  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2
41700  *
41701  */
41702 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_E_MSKED 0x1
41703 
41704 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field. */
41705 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_LSB 26
41706 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field. */
41707 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_MSB 26
41708 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field. */
41709 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_WIDTH 1
41710 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field value. */
41711 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_SET_MSK 0x04000000
41712 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field value. */
41713 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_CLR_MSK 0xfbffffff
41714 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field. */
41715 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_RESET 0x0
41716 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 field value from a register. */
41717 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
41718 /* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field value suitable for setting the register. */
41719 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
41720 
41721 /*
41722  * Field : Mask Byte Control - mbc_3
41723  *
41724  * This array of bits are mask control bits for comparison of each of the MAC
41725  * Address bytes. When masked, the MAC does not compare the corresponding byte of
41726  * received DA or SA with the contents of MAC Address24 high and low registers.
41727  * Each bit controls the masking of the bytes. You can filter a group of addresses
41728  * (known as group address filtering) by masking one or more bytes of the address.
41729  *
41730  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
41731  *
41732  * Field Enumeration Values:
41733  *
41734  * Enum | Value | Description
41735  * :----------------------------------------------|:------|:------------
41736  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_E_UNMSKED | 0x0 |
41737  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_E_MSKED | 0x1 |
41738  *
41739  * Field Access Macros:
41740  *
41741  */
41742 /*
41743  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3
41744  *
41745  */
41746 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_E_UNMSKED 0x0
41747 /*
41748  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3
41749  *
41750  */
41751 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_E_MSKED 0x1
41752 
41753 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field. */
41754 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_LSB 27
41755 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field. */
41756 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_MSB 27
41757 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field. */
41758 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_WIDTH 1
41759 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field value. */
41760 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_SET_MSK 0x08000000
41761 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field value. */
41762 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_CLR_MSK 0xf7ffffff
41763 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field. */
41764 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_RESET 0x0
41765 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 field value from a register. */
41766 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
41767 /* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field value suitable for setting the register. */
41768 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
41769 
41770 /*
41771  * Field : Mask Byte Control - mbc_4
41772  *
41773  * This array of bits are mask control bits for comparison of each of the MAC
41774  * Address bytes. When masked, the MAC does not compare the corresponding byte of
41775  * received DA or SA with the contents of MAC Address24 high and low registers.
41776  * Each bit controls the masking of the bytes. You can filter a group of addresses
41777  * (known as group address filtering) by masking one or more bytes of the address.
41778  *
41779  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
41780  *
41781  * Field Enumeration Values:
41782  *
41783  * Enum | Value | Description
41784  * :----------------------------------------------|:------|:------------
41785  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_E_UNMSKED | 0x0 |
41786  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_E_MSKED | 0x1 |
41787  *
41788  * Field Access Macros:
41789  *
41790  */
41791 /*
41792  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4
41793  *
41794  */
41795 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_E_UNMSKED 0x0
41796 /*
41797  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4
41798  *
41799  */
41800 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_E_MSKED 0x1
41801 
41802 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field. */
41803 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_LSB 28
41804 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field. */
41805 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_MSB 28
41806 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field. */
41807 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_WIDTH 1
41808 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field value. */
41809 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_SET_MSK 0x10000000
41810 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field value. */
41811 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_CLR_MSK 0xefffffff
41812 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field. */
41813 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_RESET 0x0
41814 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 field value from a register. */
41815 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
41816 /* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field value suitable for setting the register. */
41817 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
41818 
41819 /*
41820  * Field : Mask Byte Control - mbc_5
41821  *
41822  * This array of bits are mask control bits for comparison of each of the MAC
41823  * Address bytes. When masked, the MAC does not compare the corresponding byte of
41824  * received DA or SA with the contents of MAC Address24 high and low registers.
41825  * Each bit controls the masking of the bytes. You can filter a group of addresses
41826  * (known as group address filtering) by masking one or more bytes of the address.
41827  *
41828  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
41829  *
41830  * Field Enumeration Values:
41831  *
41832  * Enum | Value | Description
41833  * :----------------------------------------------|:------|:------------
41834  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_E_UNMSKED | 0x0 |
41835  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_E_MSKED | 0x1 |
41836  *
41837  * Field Access Macros:
41838  *
41839  */
41840 /*
41841  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5
41842  *
41843  */
41844 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_E_UNMSKED 0x0
41845 /*
41846  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5
41847  *
41848  */
41849 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_E_MSKED 0x1
41850 
41851 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field. */
41852 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_LSB 29
41853 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field. */
41854 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_MSB 29
41855 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field. */
41856 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_WIDTH 1
41857 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field value. */
41858 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_SET_MSK 0x20000000
41859 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field value. */
41860 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_CLR_MSK 0xdfffffff
41861 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field. */
41862 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_RESET 0x0
41863 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 field value from a register. */
41864 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
41865 /* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field value suitable for setting the register. */
41866 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
41867 
41868 /*
41869  * Field : sa
41870  *
41871  * Source Address
41872  *
41873  * When this bit is set, the MAC Address24[47:0] is used to compare with the SA
41874  * fields of the received frame.
41875  *
41876  * When this bit is reset, the MAC Address24[47:0] is used to compare with the DA
41877  * fields of the received frame.
41878  *
41879  * Field Enumeration Values:
41880  *
41881  * Enum | Value | Description
41882  * :----------------------------------------|:------|:------------
41883  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_E_DISD | 0x0 |
41884  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_E_END | 0x1 |
41885  *
41886  * Field Access Macros:
41887  *
41888  */
41889 /*
41890  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA
41891  *
41892  */
41893 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_E_DISD 0x0
41894 /*
41895  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA
41896  *
41897  */
41898 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_E_END 0x1
41899 
41900 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field. */
41901 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_LSB 30
41902 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field. */
41903 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_MSB 30
41904 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field. */
41905 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_WIDTH 1
41906 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field value. */
41907 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_SET_MSK 0x40000000
41908 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field value. */
41909 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_CLR_MSK 0xbfffffff
41910 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field. */
41911 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_RESET 0x0
41912 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA field value from a register. */
41913 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
41914 /* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field value suitable for setting the register. */
41915 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
41916 
41917 /*
41918  * Field : ae
41919  *
41920  * Address Enable
41921  *
41922  * When this bit is set, the address filter module uses the 25th MAC address for
41923  * perfect filtering.
41924  *
41925  * When this bit is reset, the address filter module ignores the address for
41926  * filtering.
41927  *
41928  * Field Enumeration Values:
41929  *
41930  * Enum | Value | Description
41931  * :----------------------------------------|:------|:------------
41932  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_E_DISD | 0x0 |
41933  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_E_END | 0x1 |
41934  *
41935  * Field Access Macros:
41936  *
41937  */
41938 /*
41939  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE
41940  *
41941  */
41942 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_E_DISD 0x0
41943 /*
41944  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE
41945  *
41946  */
41947 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_E_END 0x1
41948 
41949 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field. */
41950 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_LSB 31
41951 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field. */
41952 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_MSB 31
41953 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field. */
41954 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_WIDTH 1
41955 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field value. */
41956 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_SET_MSK 0x80000000
41957 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field value. */
41958 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_CLR_MSK 0x7fffffff
41959 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field. */
41960 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_RESET 0x0
41961 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE field value from a register. */
41962 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
41963 /* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field value suitable for setting the register. */
41964 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
41965 
41966 #ifndef __ASSEMBLY__
41967 /*
41968  * WARNING: The C register and register group struct declarations are provided for
41969  * convenience and illustrative purposes. They should, however, be used with
41970  * caution as the C language standard provides no guarantees about the alignment or
41971  * atomicity of device memory accesses. The recommended practice for writing
41972  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
41973  * alt_write_word() functions.
41974  *
41975  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR24_HIGH.
41976  */
41977 struct ALT_EMAC_GMAC_MAC_ADDR24_HIGH_s
41978 {
41979  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI */
41980  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR24_HIGH_RSVD_23_16 */
41981  uint32_t mbc_0 : 1; /* Mask Byte Control */
41982  uint32_t mbc_1 : 1; /* Mask Byte Control */
41983  uint32_t mbc_2 : 1; /* Mask Byte Control */
41984  uint32_t mbc_3 : 1; /* Mask Byte Control */
41985  uint32_t mbc_4 : 1; /* Mask Byte Control */
41986  uint32_t mbc_5 : 1; /* Mask Byte Control */
41987  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA */
41988  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE */
41989 };
41990 
41991 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR24_HIGH. */
41992 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR24_HIGH_s ALT_EMAC_GMAC_MAC_ADDR24_HIGH_t;
41993 #endif /* __ASSEMBLY__ */
41994 
41995 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH register. */
41996 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_RESET 0x0000ffff
41997 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH register from the beginning of the component. */
41998 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_OFST 0x840
41999 /* The address of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH register. */
42000 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR24_HIGH_OFST))
42001 
42002 /*
42003  * Register : gmacgrp_mac_address24_low
42004  *
42005  * <b> Register 529 (MAC Address24 Low Register) </b>
42006  *
42007  * The MAC Address24 Low register holds the lower 32 bits of the 25th 6-byte MAC
42008  * address of the station.
42009  *
42010  * Register Layout
42011  *
42012  * Bits | Access | Reset | Description
42013  * :-------|:-------|:-----------|:------------------------------------
42014  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO
42015  *
42016  */
42017 /*
42018  * Field : addrlo
42019  *
42020  * MAC Address24 [31:0]
42021  *
42022  * This field contains the lower 32 bits of the 25th 6-byte MAC address. The
42023  * content of this field is undefined until loaded by the Application after the
42024  * initialization process.
42025  *
42026  * Field Access Macros:
42027  *
42028  */
42029 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field. */
42030 #define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_LSB 0
42031 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field. */
42032 #define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_MSB 31
42033 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field. */
42034 #define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_WIDTH 32
42035 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field value. */
42036 #define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_SET_MSK 0xffffffff
42037 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field value. */
42038 #define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_CLR_MSK 0x00000000
42039 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field. */
42040 #define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_RESET 0xffffffff
42041 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO field value from a register. */
42042 #define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
42043 /* Produces a ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field value suitable for setting the register. */
42044 #define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
42045 
42046 #ifndef __ASSEMBLY__
42047 /*
42048  * WARNING: The C register and register group struct declarations are provided for
42049  * convenience and illustrative purposes. They should, however, be used with
42050  * caution as the C language standard provides no guarantees about the alignment or
42051  * atomicity of device memory accesses. The recommended practice for writing
42052  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
42053  * alt_write_word() functions.
42054  *
42055  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR24_LOW.
42056  */
42057 struct ALT_EMAC_GMAC_MAC_ADDR24_LOW_s
42058 {
42059  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO */
42060 };
42061 
42062 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR24_LOW. */
42063 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR24_LOW_s ALT_EMAC_GMAC_MAC_ADDR24_LOW_t;
42064 #endif /* __ASSEMBLY__ */
42065 
42066 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_LOW register. */
42067 #define ALT_EMAC_GMAC_MAC_ADDR24_LOW_RESET 0xffffffff
42068 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR24_LOW register from the beginning of the component. */
42069 #define ALT_EMAC_GMAC_MAC_ADDR24_LOW_OFST 0x844
42070 /* The address of the ALT_EMAC_GMAC_MAC_ADDR24_LOW register. */
42071 #define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR24_LOW_OFST))
42072 
42073 /*
42074  * Register : gmacgrp_mac_address25_high
42075  *
42076  * <b> Register 530 (MAC Address25 High Register) </b>
42077  *
42078  * The MAC Address25 High register holds the upper 16 bits of the 6-byte 26th MAC
42079  * address of the station.
42080  *
42081  * If the MAC address registers are configured to be double-synchronized to the
42082  * (G)MII clock domains, then
42083  *
42084  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
42085  * or Bits[7:0] (in big-endian mode) of the MAC Address25 Low Register are written.
42086  * For proper synchronization updates, consecutive writes to this MAC Address25 Low
42087  * Register must be performed after at least four clock cycles in the destination
42088  * clock domain.
42089  *
42090  * Register Layout
42091  *
42092  * Bits | Access | Reset | Description
42093  * :--------|:-------|:-------|:-----------------------------------------
42094  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI
42095  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR25_HIGH_RSVD_23_16
42096  * [24] | RW | 0x0 | Mask Byte Control
42097  * [25] | RW | 0x0 | Mask Byte Control
42098  * [26] | RW | 0x0 | Mask Byte Control
42099  * [27] | RW | 0x0 | Mask Byte Control
42100  * [28] | RW | 0x0 | Mask Byte Control
42101  * [29] | RW | 0x0 | Mask Byte Control
42102  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA
42103  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE
42104  *
42105  */
42106 /*
42107  * Field : addrhi
42108  *
42109  * MAC Address25 [47:32]
42110  *
42111  * This field contains the upper 16 bits (47:32) of the 26th 6-byte MAC address.
42112  *
42113  * Field Access Macros:
42114  *
42115  */
42116 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field. */
42117 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_LSB 0
42118 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field. */
42119 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_MSB 15
42120 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field. */
42121 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_WIDTH 16
42122 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field value. */
42123 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_SET_MSK 0x0000ffff
42124 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field value. */
42125 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_CLR_MSK 0xffff0000
42126 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field. */
42127 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_RESET 0xffff
42128 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI field value from a register. */
42129 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
42130 /* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field value suitable for setting the register. */
42131 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
42132 
42133 /*
42134  * Field : reserved_23_16
42135  *
42136  * Reserved
42137  *
42138  * Field Access Macros:
42139  *
42140  */
42141 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_RSVD_23_16 register field. */
42142 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_RSVD_23_16_LSB 16
42143 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_RSVD_23_16 register field. */
42144 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_RSVD_23_16_MSB 23
42145 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_RSVD_23_16 register field. */
42146 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_RSVD_23_16_WIDTH 8
42147 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_RSVD_23_16 register field value. */
42148 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
42149 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_RSVD_23_16 register field value. */
42150 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
42151 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_RSVD_23_16 register field. */
42152 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_RSVD_23_16_RESET 0x0
42153 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_RSVD_23_16 field value from a register. */
42154 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
42155 /* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_RSVD_23_16 register field value suitable for setting the register. */
42156 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
42157 
42158 /*
42159  * Field : Mask Byte Control - mbc_0
42160  *
42161  * This array of bits are mask control bits for comparison of each of the MAC
42162  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42163  * received DA or SA with the contents of MAC Address25 high and low registers.
42164  * Each bit controls the masking of the bytes. You can filter a group of addresses
42165  * (known as group address filtering) by masking one or more bytes of the address.
42166  *
42167  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42168  *
42169  * Field Enumeration Values:
42170  *
42171  * Enum | Value | Description
42172  * :----------------------------------------------|:------|:------------
42173  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_E_UNMSKED | 0x0 |
42174  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_E_MSKED | 0x1 |
42175  *
42176  * Field Access Macros:
42177  *
42178  */
42179 /*
42180  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0
42181  *
42182  */
42183 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_E_UNMSKED 0x0
42184 /*
42185  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0
42186  *
42187  */
42188 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_E_MSKED 0x1
42189 
42190 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field. */
42191 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_LSB 24
42192 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field. */
42193 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_MSB 24
42194 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field. */
42195 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_WIDTH 1
42196 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field value. */
42197 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_SET_MSK 0x01000000
42198 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field value. */
42199 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_CLR_MSK 0xfeffffff
42200 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field. */
42201 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_RESET 0x0
42202 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 field value from a register. */
42203 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
42204 /* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field value suitable for setting the register. */
42205 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
42206 
42207 /*
42208  * Field : Mask Byte Control - mbc_1
42209  *
42210  * This array of bits are mask control bits for comparison of each of the MAC
42211  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42212  * received DA or SA with the contents of MAC Address25 high and low registers.
42213  * Each bit controls the masking of the bytes. You can filter a group of addresses
42214  * (known as group address filtering) by masking one or more bytes of the address.
42215  *
42216  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42217  *
42218  * Field Enumeration Values:
42219  *
42220  * Enum | Value | Description
42221  * :----------------------------------------------|:------|:------------
42222  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_E_UNMSKED | 0x0 |
42223  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_E_MSKED | 0x1 |
42224  *
42225  * Field Access Macros:
42226  *
42227  */
42228 /*
42229  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1
42230  *
42231  */
42232 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_E_UNMSKED 0x0
42233 /*
42234  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1
42235  *
42236  */
42237 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_E_MSKED 0x1
42238 
42239 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field. */
42240 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_LSB 25
42241 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field. */
42242 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_MSB 25
42243 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field. */
42244 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_WIDTH 1
42245 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field value. */
42246 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_SET_MSK 0x02000000
42247 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field value. */
42248 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_CLR_MSK 0xfdffffff
42249 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field. */
42250 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_RESET 0x0
42251 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 field value from a register. */
42252 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
42253 /* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field value suitable for setting the register. */
42254 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
42255 
42256 /*
42257  * Field : Mask Byte Control - mbc_2
42258  *
42259  * This array of bits are mask control bits for comparison of each of the MAC
42260  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42261  * received DA or SA with the contents of MAC Address25 high and low registers.
42262  * Each bit controls the masking of the bytes. You can filter a group of addresses
42263  * (known as group address filtering) by masking one or more bytes of the address.
42264  *
42265  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42266  *
42267  * Field Enumeration Values:
42268  *
42269  * Enum | Value | Description
42270  * :----------------------------------------------|:------|:------------
42271  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_E_UNMSKED | 0x0 |
42272  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_E_MSKED | 0x1 |
42273  *
42274  * Field Access Macros:
42275  *
42276  */
42277 /*
42278  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2
42279  *
42280  */
42281 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_E_UNMSKED 0x0
42282 /*
42283  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2
42284  *
42285  */
42286 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_E_MSKED 0x1
42287 
42288 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field. */
42289 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_LSB 26
42290 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field. */
42291 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_MSB 26
42292 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field. */
42293 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_WIDTH 1
42294 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field value. */
42295 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_SET_MSK 0x04000000
42296 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field value. */
42297 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_CLR_MSK 0xfbffffff
42298 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field. */
42299 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_RESET 0x0
42300 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 field value from a register. */
42301 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
42302 /* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field value suitable for setting the register. */
42303 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
42304 
42305 /*
42306  * Field : Mask Byte Control - mbc_3
42307  *
42308  * This array of bits are mask control bits for comparison of each of the MAC
42309  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42310  * received DA or SA with the contents of MAC Address25 high and low registers.
42311  * Each bit controls the masking of the bytes. You can filter a group of addresses
42312  * (known as group address filtering) by masking one or more bytes of the address.
42313  *
42314  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42315  *
42316  * Field Enumeration Values:
42317  *
42318  * Enum | Value | Description
42319  * :----------------------------------------------|:------|:------------
42320  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_E_UNMSKED | 0x0 |
42321  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_E_MSKED | 0x1 |
42322  *
42323  * Field Access Macros:
42324  *
42325  */
42326 /*
42327  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3
42328  *
42329  */
42330 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_E_UNMSKED 0x0
42331 /*
42332  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3
42333  *
42334  */
42335 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_E_MSKED 0x1
42336 
42337 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field. */
42338 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_LSB 27
42339 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field. */
42340 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_MSB 27
42341 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field. */
42342 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_WIDTH 1
42343 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field value. */
42344 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_SET_MSK 0x08000000
42345 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field value. */
42346 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_CLR_MSK 0xf7ffffff
42347 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field. */
42348 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_RESET 0x0
42349 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 field value from a register. */
42350 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
42351 /* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field value suitable for setting the register. */
42352 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
42353 
42354 /*
42355  * Field : Mask Byte Control - mbc_4
42356  *
42357  * This array of bits are mask control bits for comparison of each of the MAC
42358  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42359  * received DA or SA with the contents of MAC Address25 high and low registers.
42360  * Each bit controls the masking of the bytes. You can filter a group of addresses
42361  * (known as group address filtering) by masking one or more bytes of the address.
42362  *
42363  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42364  *
42365  * Field Enumeration Values:
42366  *
42367  * Enum | Value | Description
42368  * :----------------------------------------------|:------|:------------
42369  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_E_UNMSKED | 0x0 |
42370  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_E_MSKED | 0x1 |
42371  *
42372  * Field Access Macros:
42373  *
42374  */
42375 /*
42376  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4
42377  *
42378  */
42379 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_E_UNMSKED 0x0
42380 /*
42381  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4
42382  *
42383  */
42384 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_E_MSKED 0x1
42385 
42386 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field. */
42387 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_LSB 28
42388 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field. */
42389 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_MSB 28
42390 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field. */
42391 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_WIDTH 1
42392 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field value. */
42393 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_SET_MSK 0x10000000
42394 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field value. */
42395 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_CLR_MSK 0xefffffff
42396 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field. */
42397 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_RESET 0x0
42398 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 field value from a register. */
42399 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
42400 /* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field value suitable for setting the register. */
42401 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
42402 
42403 /*
42404  * Field : Mask Byte Control - mbc_5
42405  *
42406  * This array of bits are mask control bits for comparison of each of the MAC
42407  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42408  * received DA or SA with the contents of MAC Address25 high and low registers.
42409  * Each bit controls the masking of the bytes. You can filter a group of addresses
42410  * (known as group address filtering) by masking one or more bytes of the address.
42411  *
42412  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42413  *
42414  * Field Enumeration Values:
42415  *
42416  * Enum | Value | Description
42417  * :----------------------------------------------|:------|:------------
42418  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_E_UNMSKED | 0x0 |
42419  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_E_MSKED | 0x1 |
42420  *
42421  * Field Access Macros:
42422  *
42423  */
42424 /*
42425  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5
42426  *
42427  */
42428 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_E_UNMSKED 0x0
42429 /*
42430  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5
42431  *
42432  */
42433 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_E_MSKED 0x1
42434 
42435 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field. */
42436 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_LSB 29
42437 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field. */
42438 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_MSB 29
42439 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field. */
42440 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_WIDTH 1
42441 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field value. */
42442 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_SET_MSK 0x20000000
42443 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field value. */
42444 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_CLR_MSK 0xdfffffff
42445 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field. */
42446 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_RESET 0x0
42447 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 field value from a register. */
42448 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
42449 /* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field value suitable for setting the register. */
42450 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
42451 
42452 /*
42453  * Field : sa
42454  *
42455  * Source Address
42456  *
42457  * When this bit is set, the MAC Address25[47:0] is used to compare with the SA
42458  * fields of the received frame.
42459  *
42460  * When this bit is reset, the MAC Address25[47:0] is used to compare with the DA
42461  * fields of the received frame.
42462  *
42463  * Field Enumeration Values:
42464  *
42465  * Enum | Value | Description
42466  * :----------------------------------------|:------|:------------
42467  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_E_DISD | 0x0 |
42468  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_E_END | 0x1 |
42469  *
42470  * Field Access Macros:
42471  *
42472  */
42473 /*
42474  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA
42475  *
42476  */
42477 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_E_DISD 0x0
42478 /*
42479  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA
42480  *
42481  */
42482 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_E_END 0x1
42483 
42484 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field. */
42485 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_LSB 30
42486 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field. */
42487 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_MSB 30
42488 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field. */
42489 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_WIDTH 1
42490 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field value. */
42491 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_SET_MSK 0x40000000
42492 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field value. */
42493 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_CLR_MSK 0xbfffffff
42494 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field. */
42495 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_RESET 0x0
42496 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA field value from a register. */
42497 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
42498 /* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field value suitable for setting the register. */
42499 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
42500 
42501 /*
42502  * Field : ae
42503  *
42504  * Address Enable
42505  *
42506  * When this bit is set, the address filter module uses the 26th MAC address for
42507  * perfect filtering.
42508  *
42509  * When this bit is reset, the address filter module ignores the address for
42510  * filtering.
42511  *
42512  * Field Enumeration Values:
42513  *
42514  * Enum | Value | Description
42515  * :----------------------------------------|:------|:------------
42516  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_E_DISD | 0x0 |
42517  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_E_END | 0x1 |
42518  *
42519  * Field Access Macros:
42520  *
42521  */
42522 /*
42523  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE
42524  *
42525  */
42526 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_E_DISD 0x0
42527 /*
42528  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE
42529  *
42530  */
42531 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_E_END 0x1
42532 
42533 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field. */
42534 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_LSB 31
42535 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field. */
42536 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_MSB 31
42537 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field. */
42538 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_WIDTH 1
42539 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field value. */
42540 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_SET_MSK 0x80000000
42541 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field value. */
42542 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_CLR_MSK 0x7fffffff
42543 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field. */
42544 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_RESET 0x0
42545 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE field value from a register. */
42546 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
42547 /* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field value suitable for setting the register. */
42548 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
42549 
42550 #ifndef __ASSEMBLY__
42551 /*
42552  * WARNING: The C register and register group struct declarations are provided for
42553  * convenience and illustrative purposes. They should, however, be used with
42554  * caution as the C language standard provides no guarantees about the alignment or
42555  * atomicity of device memory accesses. The recommended practice for writing
42556  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
42557  * alt_write_word() functions.
42558  *
42559  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR25_HIGH.
42560  */
42561 struct ALT_EMAC_GMAC_MAC_ADDR25_HIGH_s
42562 {
42563  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI */
42564  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR25_HIGH_RSVD_23_16 */
42565  uint32_t mbc_0 : 1; /* Mask Byte Control */
42566  uint32_t mbc_1 : 1; /* Mask Byte Control */
42567  uint32_t mbc_2 : 1; /* Mask Byte Control */
42568  uint32_t mbc_3 : 1; /* Mask Byte Control */
42569  uint32_t mbc_4 : 1; /* Mask Byte Control */
42570  uint32_t mbc_5 : 1; /* Mask Byte Control */
42571  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA */
42572  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE */
42573 };
42574 
42575 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR25_HIGH. */
42576 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR25_HIGH_s ALT_EMAC_GMAC_MAC_ADDR25_HIGH_t;
42577 #endif /* __ASSEMBLY__ */
42578 
42579 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH register. */
42580 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_RESET 0x0000ffff
42581 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH register from the beginning of the component. */
42582 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_OFST 0x848
42583 /* The address of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH register. */
42584 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR25_HIGH_OFST))
42585 
42586 /*
42587  * Register : gmacgrp_mac_address25_low
42588  *
42589  * <b> Register 531 (MAC Address25 Low Register) </b>
42590  *
42591  * The MAC Address25 Low register holds the lower 32 bits of the 26th 6-byte MAC
42592  * address of the station.
42593  *
42594  * Register Layout
42595  *
42596  * Bits | Access | Reset | Description
42597  * :-------|:-------|:-----------|:------------------------------------
42598  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO
42599  *
42600  */
42601 /*
42602  * Field : addrlo
42603  *
42604  * MAC Address25 [31:0]
42605  *
42606  * This field contains the lower 32 bits of the 26th 6-byte MAC address. The
42607  * content of this field is undefined until loaded by the Application after the
42608  * initialization process.
42609  *
42610  * Field Access Macros:
42611  *
42612  */
42613 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field. */
42614 #define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_LSB 0
42615 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field. */
42616 #define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_MSB 31
42617 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field. */
42618 #define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_WIDTH 32
42619 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field value. */
42620 #define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_SET_MSK 0xffffffff
42621 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field value. */
42622 #define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_CLR_MSK 0x00000000
42623 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field. */
42624 #define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_RESET 0xffffffff
42625 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO field value from a register. */
42626 #define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
42627 /* Produces a ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field value suitable for setting the register. */
42628 #define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
42629 
42630 #ifndef __ASSEMBLY__
42631 /*
42632  * WARNING: The C register and register group struct declarations are provided for
42633  * convenience and illustrative purposes. They should, however, be used with
42634  * caution as the C language standard provides no guarantees about the alignment or
42635  * atomicity of device memory accesses. The recommended practice for writing
42636  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
42637  * alt_write_word() functions.
42638  *
42639  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR25_LOW.
42640  */
42641 struct ALT_EMAC_GMAC_MAC_ADDR25_LOW_s
42642 {
42643  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO */
42644 };
42645 
42646 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR25_LOW. */
42647 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR25_LOW_s ALT_EMAC_GMAC_MAC_ADDR25_LOW_t;
42648 #endif /* __ASSEMBLY__ */
42649 
42650 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_LOW register. */
42651 #define ALT_EMAC_GMAC_MAC_ADDR25_LOW_RESET 0xffffffff
42652 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR25_LOW register from the beginning of the component. */
42653 #define ALT_EMAC_GMAC_MAC_ADDR25_LOW_OFST 0x84c
42654 /* The address of the ALT_EMAC_GMAC_MAC_ADDR25_LOW register. */
42655 #define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR25_LOW_OFST))
42656 
42657 /*
42658  * Register : gmacgrp_mac_address26_high
42659  *
42660  * <b> Register 532 (MAC Address26 High Register) </b>
42661  *
42662  * The MAC Address26 High register holds the upper 16 bits of the 27th 6-byte MAC
42663  * address of the station.
42664  *
42665  * If the MAC address registers are configured to be double-synchronized to the
42666  * (G)MII clock domains, then
42667  *
42668  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
42669  * or Bits[7:0] (in big-endian mode) of the MAC Address26 Low Register are written.
42670  * For proper synchronization updates, consecutive writes to this MAC Address26 Low
42671  * Register must be performed after at least four clock cycles in the destination
42672  * clock domain.
42673  *
42674  * Register Layout
42675  *
42676  * Bits | Access | Reset | Description
42677  * :--------|:-------|:-------|:-----------------------------------------
42678  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI
42679  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR26_HIGH_RSVD_23_16
42680  * [24] | RW | 0x0 | Mask Byte Control
42681  * [25] | RW | 0x0 | Mask Byte Control
42682  * [26] | RW | 0x0 | Mask Byte Control
42683  * [27] | RW | 0x0 | Mask Byte Control
42684  * [28] | RW | 0x0 | Mask Byte Control
42685  * [29] | RW | 0x0 | Mask Byte Control
42686  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA
42687  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE
42688  *
42689  */
42690 /*
42691  * Field : addrhi
42692  *
42693  * MAC Address26 [47:32]
42694  *
42695  * This field contains the upper 16 bits (47:32) of the 27th 6-byte MAC address.
42696  *
42697  * Field Access Macros:
42698  *
42699  */
42700 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field. */
42701 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_LSB 0
42702 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field. */
42703 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_MSB 15
42704 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field. */
42705 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_WIDTH 16
42706 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field value. */
42707 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_SET_MSK 0x0000ffff
42708 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field value. */
42709 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_CLR_MSK 0xffff0000
42710 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field. */
42711 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_RESET 0xffff
42712 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI field value from a register. */
42713 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
42714 /* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field value suitable for setting the register. */
42715 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
42716 
42717 /*
42718  * Field : reserved_23_16
42719  *
42720  * Reserved
42721  *
42722  * Field Access Macros:
42723  *
42724  */
42725 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_RSVD_23_16 register field. */
42726 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_RSVD_23_16_LSB 16
42727 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_RSVD_23_16 register field. */
42728 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_RSVD_23_16_MSB 23
42729 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_RSVD_23_16 register field. */
42730 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_RSVD_23_16_WIDTH 8
42731 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_RSVD_23_16 register field value. */
42732 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
42733 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_RSVD_23_16 register field value. */
42734 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
42735 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_RSVD_23_16 register field. */
42736 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_RSVD_23_16_RESET 0x0
42737 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_RSVD_23_16 field value from a register. */
42738 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
42739 /* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_RSVD_23_16 register field value suitable for setting the register. */
42740 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
42741 
42742 /*
42743  * Field : Mask Byte Control - mbc_0
42744  *
42745  * This array of bits are mask control bits for comparison of each of the MAC
42746  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42747  * received DA or SA with the contents of MAC Address26 high and low registers.
42748  * Each bit controls the masking of the bytes. You can filter a group of addresses
42749  * (known as group address filtering) by masking one or more bytes of the address.
42750  *
42751  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42752  *
42753  * Field Enumeration Values:
42754  *
42755  * Enum | Value | Description
42756  * :----------------------------------------------|:------|:------------
42757  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_E_UNMSKED | 0x0 |
42758  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_E_MSKED | 0x1 |
42759  *
42760  * Field Access Macros:
42761  *
42762  */
42763 /*
42764  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0
42765  *
42766  */
42767 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_E_UNMSKED 0x0
42768 /*
42769  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0
42770  *
42771  */
42772 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_E_MSKED 0x1
42773 
42774 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field. */
42775 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_LSB 24
42776 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field. */
42777 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_MSB 24
42778 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field. */
42779 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_WIDTH 1
42780 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field value. */
42781 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_SET_MSK 0x01000000
42782 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field value. */
42783 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_CLR_MSK 0xfeffffff
42784 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field. */
42785 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_RESET 0x0
42786 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 field value from a register. */
42787 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
42788 /* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field value suitable for setting the register. */
42789 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
42790 
42791 /*
42792  * Field : Mask Byte Control - mbc_1
42793  *
42794  * This array of bits are mask control bits for comparison of each of the MAC
42795  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42796  * received DA or SA with the contents of MAC Address26 high and low registers.
42797  * Each bit controls the masking of the bytes. You can filter a group of addresses
42798  * (known as group address filtering) by masking one or more bytes of the address.
42799  *
42800  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42801  *
42802  * Field Enumeration Values:
42803  *
42804  * Enum | Value | Description
42805  * :----------------------------------------------|:------|:------------
42806  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_E_UNMSKED | 0x0 |
42807  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_E_MSKED | 0x1 |
42808  *
42809  * Field Access Macros:
42810  *
42811  */
42812 /*
42813  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1
42814  *
42815  */
42816 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_E_UNMSKED 0x0
42817 /*
42818  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1
42819  *
42820  */
42821 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_E_MSKED 0x1
42822 
42823 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field. */
42824 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_LSB 25
42825 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field. */
42826 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_MSB 25
42827 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field. */
42828 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_WIDTH 1
42829 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field value. */
42830 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_SET_MSK 0x02000000
42831 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field value. */
42832 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_CLR_MSK 0xfdffffff
42833 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field. */
42834 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_RESET 0x0
42835 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 field value from a register. */
42836 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
42837 /* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field value suitable for setting the register. */
42838 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
42839 
42840 /*
42841  * Field : Mask Byte Control - mbc_2
42842  *
42843  * This array of bits are mask control bits for comparison of each of the MAC
42844  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42845  * received DA or SA with the contents of MAC Address26 high and low registers.
42846  * Each bit controls the masking of the bytes. You can filter a group of addresses
42847  * (known as group address filtering) by masking one or more bytes of the address.
42848  *
42849  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42850  *
42851  * Field Enumeration Values:
42852  *
42853  * Enum | Value | Description
42854  * :----------------------------------------------|:------|:------------
42855  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_E_UNMSKED | 0x0 |
42856  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_E_MSKED | 0x1 |
42857  *
42858  * Field Access Macros:
42859  *
42860  */
42861 /*
42862  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2
42863  *
42864  */
42865 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_E_UNMSKED 0x0
42866 /*
42867  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2
42868  *
42869  */
42870 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_E_MSKED 0x1
42871 
42872 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field. */
42873 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_LSB 26
42874 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field. */
42875 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_MSB 26
42876 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field. */
42877 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_WIDTH 1
42878 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field value. */
42879 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_SET_MSK 0x04000000
42880 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field value. */
42881 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_CLR_MSK 0xfbffffff
42882 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field. */
42883 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_RESET 0x0
42884 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 field value from a register. */
42885 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
42886 /* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field value suitable for setting the register. */
42887 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
42888 
42889 /*
42890  * Field : Mask Byte Control - mbc_3
42891  *
42892  * This array of bits are mask control bits for comparison of each of the MAC
42893  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42894  * received DA or SA with the contents of MAC Address26 high and low registers.
42895  * Each bit controls the masking of the bytes. You can filter a group of addresses
42896  * (known as group address filtering) by masking one or more bytes of the address.
42897  *
42898  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42899  *
42900  * Field Enumeration Values:
42901  *
42902  * Enum | Value | Description
42903  * :----------------------------------------------|:------|:------------
42904  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_E_UNMSKED | 0x0 |
42905  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_E_MSKED | 0x1 |
42906  *
42907  * Field Access Macros:
42908  *
42909  */
42910 /*
42911  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3
42912  *
42913  */
42914 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_E_UNMSKED 0x0
42915 /*
42916  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3
42917  *
42918  */
42919 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_E_MSKED 0x1
42920 
42921 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field. */
42922 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_LSB 27
42923 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field. */
42924 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_MSB 27
42925 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field. */
42926 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_WIDTH 1
42927 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field value. */
42928 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_SET_MSK 0x08000000
42929 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field value. */
42930 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_CLR_MSK 0xf7ffffff
42931 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field. */
42932 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_RESET 0x0
42933 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 field value from a register. */
42934 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
42935 /* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field value suitable for setting the register. */
42936 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
42937 
42938 /*
42939  * Field : Mask Byte Control - mbc_4
42940  *
42941  * This array of bits are mask control bits for comparison of each of the MAC
42942  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42943  * received DA or SA with the contents of MAC Address26 high and low registers.
42944  * Each bit controls the masking of the bytes. You can filter a group of addresses
42945  * (known as group address filtering) by masking one or more bytes of the address.
42946  *
42947  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42948  *
42949  * Field Enumeration Values:
42950  *
42951  * Enum | Value | Description
42952  * :----------------------------------------------|:------|:------------
42953  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_E_UNMSKED | 0x0 |
42954  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_E_MSKED | 0x1 |
42955  *
42956  * Field Access Macros:
42957  *
42958  */
42959 /*
42960  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4
42961  *
42962  */
42963 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_E_UNMSKED 0x0
42964 /*
42965  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4
42966  *
42967  */
42968 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_E_MSKED 0x1
42969 
42970 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field. */
42971 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_LSB 28
42972 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field. */
42973 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_MSB 28
42974 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field. */
42975 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_WIDTH 1
42976 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field value. */
42977 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_SET_MSK 0x10000000
42978 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field value. */
42979 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_CLR_MSK 0xefffffff
42980 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field. */
42981 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_RESET 0x0
42982 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 field value from a register. */
42983 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
42984 /* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field value suitable for setting the register. */
42985 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
42986 
42987 /*
42988  * Field : Mask Byte Control - mbc_5
42989  *
42990  * This array of bits are mask control bits for comparison of each of the MAC
42991  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42992  * received DA or SA with the contents of MAC Address26 high and low registers.
42993  * Each bit controls the masking of the bytes. You can filter a group of addresses
42994  * (known as group address filtering) by masking one or more bytes of the address.
42995  *
42996  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42997  *
42998  * Field Enumeration Values:
42999  *
43000  * Enum | Value | Description
43001  * :----------------------------------------------|:------|:------------
43002  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_E_UNMSKED | 0x0 |
43003  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_E_MSKED | 0x1 |
43004  *
43005  * Field Access Macros:
43006  *
43007  */
43008 /*
43009  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5
43010  *
43011  */
43012 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_E_UNMSKED 0x0
43013 /*
43014  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5
43015  *
43016  */
43017 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_E_MSKED 0x1
43018 
43019 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field. */
43020 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_LSB 29
43021 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field. */
43022 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_MSB 29
43023 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field. */
43024 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_WIDTH 1
43025 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field value. */
43026 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_SET_MSK 0x20000000
43027 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field value. */
43028 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_CLR_MSK 0xdfffffff
43029 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field. */
43030 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_RESET 0x0
43031 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 field value from a register. */
43032 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
43033 /* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field value suitable for setting the register. */
43034 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
43035 
43036 /*
43037  * Field : sa
43038  *
43039  * Source Address
43040  *
43041  * When this bit is set, the MAC Address26[47:0] is used to compare with the SA
43042  * fields of the received frame.
43043  *
43044  * When this bit is reset, the MAC Address26[47:0] is used to compare with the DA
43045  * fields of the received frame.
43046  *
43047  * Field Enumeration Values:
43048  *
43049  * Enum | Value | Description
43050  * :----------------------------------------|:------|:------------
43051  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_E_DISD | 0x0 |
43052  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_E_END | 0x1 |
43053  *
43054  * Field Access Macros:
43055  *
43056  */
43057 /*
43058  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA
43059  *
43060  */
43061 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_E_DISD 0x0
43062 /*
43063  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA
43064  *
43065  */
43066 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_E_END 0x1
43067 
43068 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field. */
43069 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_LSB 30
43070 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field. */
43071 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_MSB 30
43072 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field. */
43073 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_WIDTH 1
43074 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field value. */
43075 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_SET_MSK 0x40000000
43076 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field value. */
43077 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_CLR_MSK 0xbfffffff
43078 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field. */
43079 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_RESET 0x0
43080 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA field value from a register. */
43081 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
43082 /* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field value suitable for setting the register. */
43083 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
43084 
43085 /*
43086  * Field : ae
43087  *
43088  * Address Enable
43089  *
43090  * When this bit is set, the address filter module uses the 27th MAC address for
43091  * perfect filtering.
43092  *
43093  * When this bit is reset, the address filter module ignores the address for
43094  * filtering.
43095  *
43096  * Field Enumeration Values:
43097  *
43098  * Enum | Value | Description
43099  * :----------------------------------------|:------|:------------
43100  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_E_DISD | 0x0 |
43101  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_E_END | 0x1 |
43102  *
43103  * Field Access Macros:
43104  *
43105  */
43106 /*
43107  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE
43108  *
43109  */
43110 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_E_DISD 0x0
43111 /*
43112  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE
43113  *
43114  */
43115 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_E_END 0x1
43116 
43117 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field. */
43118 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_LSB 31
43119 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field. */
43120 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_MSB 31
43121 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field. */
43122 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_WIDTH 1
43123 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field value. */
43124 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_SET_MSK 0x80000000
43125 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field value. */
43126 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_CLR_MSK 0x7fffffff
43127 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field. */
43128 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_RESET 0x0
43129 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE field value from a register. */
43130 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
43131 /* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field value suitable for setting the register. */
43132 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
43133 
43134 #ifndef __ASSEMBLY__
43135 /*
43136  * WARNING: The C register and register group struct declarations are provided for
43137  * convenience and illustrative purposes. They should, however, be used with
43138  * caution as the C language standard provides no guarantees about the alignment or
43139  * atomicity of device memory accesses. The recommended practice for writing
43140  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
43141  * alt_write_word() functions.
43142  *
43143  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR26_HIGH.
43144  */
43145 struct ALT_EMAC_GMAC_MAC_ADDR26_HIGH_s
43146 {
43147  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI */
43148  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR26_HIGH_RSVD_23_16 */
43149  uint32_t mbc_0 : 1; /* Mask Byte Control */
43150  uint32_t mbc_1 : 1; /* Mask Byte Control */
43151  uint32_t mbc_2 : 1; /* Mask Byte Control */
43152  uint32_t mbc_3 : 1; /* Mask Byte Control */
43153  uint32_t mbc_4 : 1; /* Mask Byte Control */
43154  uint32_t mbc_5 : 1; /* Mask Byte Control */
43155  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA */
43156  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE */
43157 };
43158 
43159 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR26_HIGH. */
43160 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR26_HIGH_s ALT_EMAC_GMAC_MAC_ADDR26_HIGH_t;
43161 #endif /* __ASSEMBLY__ */
43162 
43163 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH register. */
43164 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_RESET 0x0000ffff
43165 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH register from the beginning of the component. */
43166 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_OFST 0x850
43167 /* The address of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH register. */
43168 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR26_HIGH_OFST))
43169 
43170 /*
43171  * Register : gmacgrp_mac_address26_low
43172  *
43173  * <b> Register 533 (MAC Address26 Low Register) </b>
43174  *
43175  * The MAC Address26 Low register holds the lower 32 bits of the 27th 6-byte MAC
43176  * address of the station.
43177  *
43178  * Register Layout
43179  *
43180  * Bits | Access | Reset | Description
43181  * :-------|:-------|:-----------|:------------------------------------
43182  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO
43183  *
43184  */
43185 /*
43186  * Field : addrlo
43187  *
43188  * MAC Address26 [31:0]
43189  *
43190  * This field contains the lower 32 bits of the 27th 6-byte MAC address. The
43191  * content of this field is undefined until loaded by the Application after the
43192  * initialization process.
43193  *
43194  * Field Access Macros:
43195  *
43196  */
43197 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field. */
43198 #define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_LSB 0
43199 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field. */
43200 #define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_MSB 31
43201 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field. */
43202 #define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_WIDTH 32
43203 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field value. */
43204 #define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_SET_MSK 0xffffffff
43205 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field value. */
43206 #define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_CLR_MSK 0x00000000
43207 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field. */
43208 #define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_RESET 0xffffffff
43209 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO field value from a register. */
43210 #define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
43211 /* Produces a ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field value suitable for setting the register. */
43212 #define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
43213 
43214 #ifndef __ASSEMBLY__
43215 /*
43216  * WARNING: The C register and register group struct declarations are provided for
43217  * convenience and illustrative purposes. They should, however, be used with
43218  * caution as the C language standard provides no guarantees about the alignment or
43219  * atomicity of device memory accesses. The recommended practice for writing
43220  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
43221  * alt_write_word() functions.
43222  *
43223  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR26_LOW.
43224  */
43225 struct ALT_EMAC_GMAC_MAC_ADDR26_LOW_s
43226 {
43227  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO */
43228 };
43229 
43230 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR26_LOW. */
43231 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR26_LOW_s ALT_EMAC_GMAC_MAC_ADDR26_LOW_t;
43232 #endif /* __ASSEMBLY__ */
43233 
43234 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_LOW register. */
43235 #define ALT_EMAC_GMAC_MAC_ADDR26_LOW_RESET 0xffffffff
43236 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR26_LOW register from the beginning of the component. */
43237 #define ALT_EMAC_GMAC_MAC_ADDR26_LOW_OFST 0x854
43238 /* The address of the ALT_EMAC_GMAC_MAC_ADDR26_LOW register. */
43239 #define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR26_LOW_OFST))
43240 
43241 /*
43242  * Register : gmacgrp_mac_address27_high
43243  *
43244  * <b> Register 534 (MAC Address27 High Register) </b>
43245  *
43246  * The MAC Address27 High register holds the upper 16 bits of the 28th 6-byte MAC
43247  * address of the station.
43248  *
43249  * If the MAC address registers are configured to be double-synchronized to the
43250  * (G)MII clock domains, then
43251  *
43252  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
43253  * or Bits[7:0] (in big-endian mode) of the MAC Address27 Low Register are written.
43254  * For proper synchronization updates, consecutive writes to this MAC Address27 Low
43255  * Register must be performed after at least four clock cycles in the destination
43256  * clock domain.
43257  *
43258  * Register Layout
43259  *
43260  * Bits | Access | Reset | Description
43261  * :--------|:-------|:-------|:-----------------------------------------
43262  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI
43263  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR27_HIGH_RSVD_23_16
43264  * [24] | RW | 0x0 | Mask Byte Control
43265  * [25] | RW | 0x0 | Mask Byte Control
43266  * [26] | RW | 0x0 | Mask Byte Control
43267  * [27] | RW | 0x0 | Mask Byte Control
43268  * [28] | RW | 0x0 | Mask Byte Control
43269  * [29] | RW | 0x0 | Mask Byte Control
43270  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA
43271  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE
43272  *
43273  */
43274 /*
43275  * Field : addrhi
43276  *
43277  * MAC Address27 [47:32]
43278  *
43279  * This field contains the upper 16 bits (47:32) of the 28th 6-byte MAC address.
43280  *
43281  * Field Access Macros:
43282  *
43283  */
43284 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field. */
43285 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_LSB 0
43286 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field. */
43287 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_MSB 15
43288 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field. */
43289 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_WIDTH 16
43290 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field value. */
43291 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_SET_MSK 0x0000ffff
43292 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field value. */
43293 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_CLR_MSK 0xffff0000
43294 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field. */
43295 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_RESET 0xffff
43296 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI field value from a register. */
43297 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
43298 /* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field value suitable for setting the register. */
43299 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
43300 
43301 /*
43302  * Field : reserved_23_16
43303  *
43304  * Reserved
43305  *
43306  * Field Access Macros:
43307  *
43308  */
43309 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_RSVD_23_16 register field. */
43310 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_RSVD_23_16_LSB 16
43311 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_RSVD_23_16 register field. */
43312 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_RSVD_23_16_MSB 23
43313 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_RSVD_23_16 register field. */
43314 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_RSVD_23_16_WIDTH 8
43315 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_RSVD_23_16 register field value. */
43316 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
43317 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_RSVD_23_16 register field value. */
43318 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
43319 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_RSVD_23_16 register field. */
43320 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_RSVD_23_16_RESET 0x0
43321 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_RSVD_23_16 field value from a register. */
43322 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
43323 /* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_RSVD_23_16 register field value suitable for setting the register. */
43324 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
43325 
43326 /*
43327  * Field : Mask Byte Control - mbc_0
43328  *
43329  * This array of bits are mask control bits for comparison of each of the MAC
43330  * Address bytes. When masked, the MAC does not compare the corresponding byte of
43331  * received DA or SA with the contents of MAC Address27 high and low registers.
43332  * Each bit controls the masking of the bytes. You can filter a group of addresses
43333  * (known as group address filtering) by masking one or more bytes of the address.
43334  *
43335  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
43336  *
43337  * Field Enumeration Values:
43338  *
43339  * Enum | Value | Description
43340  * :----------------------------------------------|:------|:------------
43341  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_E_UNMSKED | 0x0 |
43342  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_E_MSKED | 0x1 |
43343  *
43344  * Field Access Macros:
43345  *
43346  */
43347 /*
43348  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0
43349  *
43350  */
43351 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_E_UNMSKED 0x0
43352 /*
43353  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0
43354  *
43355  */
43356 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_E_MSKED 0x1
43357 
43358 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field. */
43359 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_LSB 24
43360 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field. */
43361 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_MSB 24
43362 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field. */
43363 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_WIDTH 1
43364 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field value. */
43365 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_SET_MSK 0x01000000
43366 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field value. */
43367 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_CLR_MSK 0xfeffffff
43368 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field. */
43369 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_RESET 0x0
43370 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 field value from a register. */
43371 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
43372 /* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field value suitable for setting the register. */
43373 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
43374 
43375 /*
43376  * Field : Mask Byte Control - mbc_1
43377  *
43378  * This array of bits are mask control bits for comparison of each of the MAC
43379  * Address bytes. When masked, the MAC does not compare the corresponding byte of
43380  * received DA or SA with the contents of MAC Address27 high and low registers.
43381  * Each bit controls the masking of the bytes. You can filter a group of addresses
43382  * (known as group address filtering) by masking one or more bytes of the address.
43383  *
43384  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
43385  *
43386  * Field Enumeration Values:
43387  *
43388  * Enum | Value | Description
43389  * :----------------------------------------------|:------|:------------
43390  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_E_UNMSKED | 0x0 |
43391  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_E_MSKED | 0x1 |
43392  *
43393  * Field Access Macros:
43394  *
43395  */
43396 /*
43397  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1
43398  *
43399  */
43400 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_E_UNMSKED 0x0
43401 /*
43402  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1
43403  *
43404  */
43405 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_E_MSKED 0x1
43406 
43407 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field. */
43408 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_LSB 25
43409 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field. */
43410 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_MSB 25
43411 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field. */
43412 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_WIDTH 1
43413 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field value. */
43414 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_SET_MSK 0x02000000
43415 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field value. */
43416 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_CLR_MSK 0xfdffffff
43417 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field. */
43418 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_RESET 0x0
43419 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 field value from a register. */
43420 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
43421 /* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field value suitable for setting the register. */
43422 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
43423 
43424 /*
43425  * Field : Mask Byte Control - mbc_2
43426  *
43427  * This array of bits are mask control bits for comparison of each of the MAC
43428  * Address bytes. When masked, the MAC does not compare the corresponding byte of
43429  * received DA or SA with the contents of MAC Address27 high and low registers.
43430  * Each bit controls the masking of the bytes. You can filter a group of addresses
43431  * (known as group address filtering) by masking one or more bytes of the address.
43432  *
43433  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
43434  *
43435  * Field Enumeration Values:
43436  *
43437  * Enum | Value | Description
43438  * :----------------------------------------------|:------|:------------
43439  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_E_UNMSKED | 0x0 |
43440  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_E_MSKED | 0x1 |
43441  *
43442  * Field Access Macros:
43443  *
43444  */
43445 /*
43446  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2
43447  *
43448  */
43449 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_E_UNMSKED 0x0
43450 /*
43451  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2
43452  *
43453  */
43454 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_E_MSKED 0x1
43455 
43456 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field. */
43457 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_LSB 26
43458 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field. */
43459 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_MSB 26
43460 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field. */
43461 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_WIDTH 1
43462 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field value. */
43463 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_SET_MSK 0x04000000
43464 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field value. */
43465 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_CLR_MSK 0xfbffffff
43466 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field. */
43467 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_RESET 0x0
43468 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 field value from a register. */
43469 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
43470 /* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field value suitable for setting the register. */
43471 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
43472 
43473 /*
43474  * Field : Mask Byte Control - mbc_3
43475  *
43476  * This array of bits are mask control bits for comparison of each of the MAC
43477  * Address bytes. When masked, the MAC does not compare the corresponding byte of
43478  * received DA or SA with the contents of MAC Address27 high and low registers.
43479  * Each bit controls the masking of the bytes. You can filter a group of addresses
43480  * (known as group address filtering) by masking one or more bytes of the address.
43481  *
43482  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
43483  *
43484  * Field Enumeration Values:
43485  *
43486  * Enum | Value | Description
43487  * :----------------------------------------------|:------|:------------
43488  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_E_UNMSKED | 0x0 |
43489  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_E_MSKED | 0x1 |
43490  *
43491  * Field Access Macros:
43492  *
43493  */
43494 /*
43495  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3
43496  *
43497  */
43498 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_E_UNMSKED 0x0
43499 /*
43500  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3
43501  *
43502  */
43503 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_E_MSKED 0x1
43504 
43505 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field. */
43506 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_LSB 27
43507 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field. */
43508 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_MSB 27
43509 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field. */
43510 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_WIDTH 1
43511 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field value. */
43512 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_SET_MSK 0x08000000
43513 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field value. */
43514 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_CLR_MSK 0xf7ffffff
43515 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field. */
43516 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_RESET 0x0
43517 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 field value from a register. */
43518 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
43519 /* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field value suitable for setting the register. */
43520 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
43521 
43522 /*
43523  * Field : Mask Byte Control - mbc_4
43524  *
43525  * This array of bits are mask control bits for comparison of each of the MAC
43526  * Address bytes. When masked, the MAC does not compare the corresponding byte of
43527  * received DA or SA with the contents of MAC Address27 high and low registers.
43528  * Each bit controls the masking of the bytes. You can filter a group of addresses
43529  * (known as group address filtering) by masking one or more bytes of the address.
43530  *
43531  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
43532  *
43533  * Field Enumeration Values:
43534  *
43535  * Enum | Value | Description
43536  * :----------------------------------------------|:------|:------------
43537  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_E_UNMSKED | 0x0 |
43538  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_E_MSKED | 0x1 |
43539  *
43540  * Field Access Macros:
43541  *
43542  */
43543 /*
43544  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4
43545  *
43546  */
43547 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_E_UNMSKED 0x0
43548 /*
43549  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4
43550  *
43551  */
43552 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_E_MSKED 0x1
43553 
43554 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field. */
43555 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_LSB 28
43556 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field. */
43557 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_MSB 28
43558 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field. */
43559 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_WIDTH 1
43560 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field value. */
43561 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_SET_MSK 0x10000000
43562 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field value. */
43563 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_CLR_MSK 0xefffffff
43564 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field. */
43565 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_RESET 0x0
43566 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 field value from a register. */
43567 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
43568 /* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field value suitable for setting the register. */
43569 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
43570 
43571 /*
43572  * Field : Mask Byte Control - mbc_5
43573  *
43574  * This array of bits are mask control bits for comparison of each of the MAC
43575  * Address bytes. When masked, the MAC does not compare the corresponding byte of
43576  * received DA or SA with the contents of MAC Address27 high and low registers.
43577  * Each bit controls the masking of the bytes. You can filter a group of addresses
43578  * (known as group address filtering) by masking one or more bytes of the address.
43579  *
43580  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
43581  *
43582  * Field Enumeration Values:
43583  *
43584  * Enum | Value | Description
43585  * :----------------------------------------------|:------|:------------
43586  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_E_UNMSKED | 0x0 |
43587  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_E_MSKED | 0x1 |
43588  *
43589  * Field Access Macros:
43590  *
43591  */
43592 /*
43593  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5
43594  *
43595  */
43596 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_E_UNMSKED 0x0
43597 /*
43598  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5
43599  *
43600  */
43601 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_E_MSKED 0x1
43602 
43603 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field. */
43604 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_LSB 29
43605 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field. */
43606 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_MSB 29
43607 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field. */
43608 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_WIDTH 1
43609 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field value. */
43610 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_SET_MSK 0x20000000
43611 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field value. */
43612 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_CLR_MSK 0xdfffffff
43613 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field. */
43614 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_RESET 0x0
43615 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 field value from a register. */
43616 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
43617 /* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field value suitable for setting the register. */
43618 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
43619 
43620 /*
43621  * Field : sa
43622  *
43623  * Source Address
43624  *
43625  * When this bit is set, the MAC Address27[47:0] is used to compare with the SA
43626  * fields of the received frame.
43627  *
43628  * When this bit is reset, the MAC Address27[47:0] is used to compare with the DA
43629  * fields of the received frame.
43630  *
43631  * Field Enumeration Values:
43632  *
43633  * Enum | Value | Description
43634  * :----------------------------------------|:------|:------------
43635  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_E_DISD | 0x0 |
43636  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_E_END | 0x1 |
43637  *
43638  * Field Access Macros:
43639  *
43640  */
43641 /*
43642  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA
43643  *
43644  */
43645 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_E_DISD 0x0
43646 /*
43647  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA
43648  *
43649  */
43650 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_E_END 0x1
43651 
43652 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field. */
43653 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_LSB 30
43654 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field. */
43655 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_MSB 30
43656 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field. */
43657 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_WIDTH 1
43658 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field value. */
43659 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_SET_MSK 0x40000000
43660 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field value. */
43661 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_CLR_MSK 0xbfffffff
43662 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field. */
43663 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_RESET 0x0
43664 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA field value from a register. */
43665 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
43666 /* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field value suitable for setting the register. */
43667 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
43668 
43669 /*
43670  * Field : ae
43671  *
43672  * Address Enable
43673  *
43674  * When this bit is set, the address filter module uses the 28th MAC address for
43675  * perfect filtering.
43676  *
43677  * When this bit is reset, the address filter module ignores the address for
43678  * filtering.
43679  *
43680  * Field Enumeration Values:
43681  *
43682  * Enum | Value | Description
43683  * :----------------------------------------|:------|:------------
43684  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_E_DISD | 0x0 |
43685  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_E_END | 0x1 |
43686  *
43687  * Field Access Macros:
43688  *
43689  */
43690 /*
43691  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE
43692  *
43693  */
43694 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_E_DISD 0x0
43695 /*
43696  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE
43697  *
43698  */
43699 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_E_END 0x1
43700 
43701 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field. */
43702 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_LSB 31
43703 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field. */
43704 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_MSB 31
43705 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field. */
43706 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_WIDTH 1
43707 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field value. */
43708 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_SET_MSK 0x80000000
43709 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field value. */
43710 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_CLR_MSK 0x7fffffff
43711 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field. */
43712 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_RESET 0x0
43713 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE field value from a register. */
43714 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
43715 /* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field value suitable for setting the register. */
43716 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
43717 
43718 #ifndef __ASSEMBLY__
43719 /*
43720  * WARNING: The C register and register group struct declarations are provided for
43721  * convenience and illustrative purposes. They should, however, be used with
43722  * caution as the C language standard provides no guarantees about the alignment or
43723  * atomicity of device memory accesses. The recommended practice for writing
43724  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
43725  * alt_write_word() functions.
43726  *
43727  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR27_HIGH.
43728  */
43729 struct ALT_EMAC_GMAC_MAC_ADDR27_HIGH_s
43730 {
43731  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI */
43732  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR27_HIGH_RSVD_23_16 */
43733  uint32_t mbc_0 : 1; /* Mask Byte Control */
43734  uint32_t mbc_1 : 1; /* Mask Byte Control */
43735  uint32_t mbc_2 : 1; /* Mask Byte Control */
43736  uint32_t mbc_3 : 1; /* Mask Byte Control */
43737  uint32_t mbc_4 : 1; /* Mask Byte Control */
43738  uint32_t mbc_5 : 1; /* Mask Byte Control */
43739  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA */
43740  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE */
43741 };
43742 
43743 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR27_HIGH. */
43744 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR27_HIGH_s ALT_EMAC_GMAC_MAC_ADDR27_HIGH_t;
43745 #endif /* __ASSEMBLY__ */
43746 
43747 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH register. */
43748 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_RESET 0x0000ffff
43749 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH register from the beginning of the component. */
43750 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_OFST 0x858
43751 /* The address of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH register. */
43752 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR27_HIGH_OFST))
43753 
43754 /*
43755  * Register : gmacgrp_mac_address27_low
43756  *
43757  * <b> Register 535 (MAC Address27 Low Register) </b>
43758  *
43759  * The MAC Address27 Low register holds the lower 32 bits of the 28th 6-byte MAC
43760  * address of the station.
43761  *
43762  * Register Layout
43763  *
43764  * Bits | Access | Reset | Description
43765  * :-------|:-------|:-----------|:------------------------------------
43766  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO
43767  *
43768  */
43769 /*
43770  * Field : addrlo
43771  *
43772  * MAC Address27 [31:0]
43773  *
43774  * This field contains the lower 32 bits of the 28th 6-byte MAC address. The
43775  * content of this field is undefined until loaded by the Application after the
43776  * initialization process.
43777  *
43778  * Field Access Macros:
43779  *
43780  */
43781 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field. */
43782 #define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_LSB 0
43783 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field. */
43784 #define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_MSB 31
43785 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field. */
43786 #define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_WIDTH 32
43787 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field value. */
43788 #define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_SET_MSK 0xffffffff
43789 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field value. */
43790 #define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_CLR_MSK 0x00000000
43791 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field. */
43792 #define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_RESET 0xffffffff
43793 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO field value from a register. */
43794 #define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
43795 /* Produces a ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field value suitable for setting the register. */
43796 #define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
43797 
43798 #ifndef __ASSEMBLY__
43799 /*
43800  * WARNING: The C register and register group struct declarations are provided for
43801  * convenience and illustrative purposes. They should, however, be used with
43802  * caution as the C language standard provides no guarantees about the alignment or
43803  * atomicity of device memory accesses. The recommended practice for writing
43804  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
43805  * alt_write_word() functions.
43806  *
43807  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR27_LOW.
43808  */
43809 struct ALT_EMAC_GMAC_MAC_ADDR27_LOW_s
43810 {
43811  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO */
43812 };
43813 
43814 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR27_LOW. */
43815 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR27_LOW_s ALT_EMAC_GMAC_MAC_ADDR27_LOW_t;
43816 #endif /* __ASSEMBLY__ */
43817 
43818 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_LOW register. */
43819 #define ALT_EMAC_GMAC_MAC_ADDR27_LOW_RESET 0xffffffff
43820 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR27_LOW register from the beginning of the component. */
43821 #define ALT_EMAC_GMAC_MAC_ADDR27_LOW_OFST 0x85c
43822 /* The address of the ALT_EMAC_GMAC_MAC_ADDR27_LOW register. */
43823 #define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR27_LOW_OFST))
43824 
43825 /*
43826  * Register : gmacgrp_mac_address28_high
43827  *
43828  * <b> Register 536 (MAC Address28 High Register) </b>
43829  *
43830  * The MAC Address28 High register holds the upper 16 bits of the 29th 6-byte MAC
43831  * address of the station.
43832  *
43833  * If the MAC address registers are configured to be double-synchronized to the
43834  * (G)MII clock domains, then
43835  *
43836  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
43837  * or Bits[7:0] (in big-endian mode) of the MAC Address28 Low Register are written.
43838  * For proper synchronization updates, consecutive writes to this MAC Address28 Low
43839  * Register must be performed after at least four clock cycles in the destination
43840  * clock domain.
43841  *
43842  * Register Layout
43843  *
43844  * Bits | Access | Reset | Description
43845  * :--------|:-------|:-------|:-----------------------------------------
43846  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI
43847  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR28_HIGH_RSVD_23_16
43848  * [24] | RW | 0x0 | Mask Byte Control
43849  * [25] | RW | 0x0 | Mask Byte Control
43850  * [26] | RW | 0x0 | Mask Byte Control
43851  * [27] | RW | 0x0 | Mask Byte Control
43852  * [28] | RW | 0x0 | Mask Byte Control
43853  * [29] | RW | 0x0 | Mask Byte Control
43854  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA
43855  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE
43856  *
43857  */
43858 /*
43859  * Field : addrhi
43860  *
43861  * MAC Address28 [47:32]
43862  *
43863  * This field contains the upper 16 bits (47:32) of the 29th 6-byte MAC address.
43864  *
43865  * Field Access Macros:
43866  *
43867  */
43868 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field. */
43869 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_LSB 0
43870 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field. */
43871 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_MSB 15
43872 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field. */
43873 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_WIDTH 16
43874 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field value. */
43875 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_SET_MSK 0x0000ffff
43876 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field value. */
43877 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_CLR_MSK 0xffff0000
43878 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field. */
43879 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_RESET 0xffff
43880 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI field value from a register. */
43881 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
43882 /* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field value suitable for setting the register. */
43883 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
43884 
43885 /*
43886  * Field : reserved_23_16
43887  *
43888  * Reserved
43889  *
43890  * Field Access Macros:
43891  *
43892  */
43893 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_RSVD_23_16 register field. */
43894 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_RSVD_23_16_LSB 16
43895 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_RSVD_23_16 register field. */
43896 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_RSVD_23_16_MSB 23
43897 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_RSVD_23_16 register field. */
43898 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_RSVD_23_16_WIDTH 8
43899 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_RSVD_23_16 register field value. */
43900 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
43901 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_RSVD_23_16 register field value. */
43902 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
43903 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_RSVD_23_16 register field. */
43904 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_RSVD_23_16_RESET 0x0
43905 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_RSVD_23_16 field value from a register. */
43906 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
43907 /* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_RSVD_23_16 register field value suitable for setting the register. */
43908 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
43909 
43910 /*
43911  * Field : Mask Byte Control - mbc_0
43912  *
43913  * This array of bits are mask control bits for comparison of each of the MAC
43914  * Address bytes. When masked, the MAC does not compare the corresponding byte of
43915  * received DA or SA with the contents of MAC Address28 high and low registers.
43916  * Each bit controls the masking of the bytes. You can filter a group of addresses
43917  * (known as group address filtering) by masking one or more bytes of the address.
43918  *
43919  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
43920  *
43921  * Field Enumeration Values:
43922  *
43923  * Enum | Value | Description
43924  * :----------------------------------------------|:------|:------------
43925  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_E_UNMSKED | 0x0 |
43926  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_E_MSKED | 0x1 |
43927  *
43928  * Field Access Macros:
43929  *
43930  */
43931 /*
43932  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0
43933  *
43934  */
43935 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_E_UNMSKED 0x0
43936 /*
43937  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0
43938  *
43939  */
43940 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_E_MSKED 0x1
43941 
43942 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field. */
43943 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_LSB 24
43944 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field. */
43945 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_MSB 24
43946 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field. */
43947 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_WIDTH 1
43948 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field value. */
43949 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_SET_MSK 0x01000000
43950 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field value. */
43951 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_CLR_MSK 0xfeffffff
43952 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field. */
43953 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_RESET 0x0
43954 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 field value from a register. */
43955 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
43956 /* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field value suitable for setting the register. */
43957 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
43958 
43959 /*
43960  * Field : Mask Byte Control - mbc_1
43961  *
43962  * This array of bits are mask control bits for comparison of each of the MAC
43963  * Address bytes. When masked, the MAC does not compare the corresponding byte of
43964  * received DA or SA with the contents of MAC Address28 high and low registers.
43965  * Each bit controls the masking of the bytes. You can filter a group of addresses
43966  * (known as group address filtering) by masking one or more bytes of the address.
43967  *
43968  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
43969  *
43970  * Field Enumeration Values:
43971  *
43972  * Enum | Value | Description
43973  * :----------------------------------------------|:------|:------------
43974  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_E_UNMSKED | 0x0 |
43975  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_E_MSKED | 0x1 |
43976  *
43977  * Field Access Macros:
43978  *
43979  */
43980 /*
43981  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1
43982  *
43983  */
43984 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_E_UNMSKED 0x0
43985 /*
43986  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1
43987  *
43988  */
43989 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_E_MSKED 0x1
43990 
43991 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field. */
43992 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_LSB 25
43993 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field. */
43994 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_MSB 25
43995 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field. */
43996 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_WIDTH 1
43997 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field value. */
43998 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_SET_MSK 0x02000000
43999 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field value. */
44000 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_CLR_MSK 0xfdffffff
44001 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field. */
44002 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_RESET 0x0
44003 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 field value from a register. */
44004 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
44005 /* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field value suitable for setting the register. */
44006 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
44007 
44008 /*
44009  * Field : Mask Byte Control - mbc_2
44010  *
44011  * This array of bits are mask control bits for comparison of each of the MAC
44012  * Address bytes. When masked, the MAC does not compare the corresponding byte of
44013  * received DA or SA with the contents of MAC Address28 high and low registers.
44014  * Each bit controls the masking of the bytes. You can filter a group of addresses
44015  * (known as group address filtering) by masking one or more bytes of the address.
44016  *
44017  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
44018  *
44019  * Field Enumeration Values:
44020  *
44021  * Enum | Value | Description
44022  * :----------------------------------------------|:------|:------------
44023  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_E_UNMSKED | 0x0 |
44024  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_E_MSKED | 0x1 |
44025  *
44026  * Field Access Macros:
44027  *
44028  */
44029 /*
44030  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2
44031  *
44032  */
44033 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_E_UNMSKED 0x0
44034 /*
44035  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2
44036  *
44037  */
44038 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_E_MSKED 0x1
44039 
44040 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field. */
44041 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_LSB 26
44042 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field. */
44043 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_MSB 26
44044 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field. */
44045 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_WIDTH 1
44046 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field value. */
44047 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_SET_MSK 0x04000000
44048 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field value. */
44049 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_CLR_MSK 0xfbffffff
44050 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field. */
44051 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_RESET 0x0
44052 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 field value from a register. */
44053 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
44054 /* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field value suitable for setting the register. */
44055 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
44056 
44057 /*
44058  * Field : Mask Byte Control - mbc_3
44059  *
44060  * This array of bits are mask control bits for comparison of each of the MAC
44061  * Address bytes. When masked, the MAC does not compare the corresponding byte of
44062  * received DA or SA with the contents of MAC Address28 high and low registers.
44063  * Each bit controls the masking of the bytes. You can filter a group of addresses
44064  * (known as group address filtering) by masking one or more bytes of the address.
44065  *
44066  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
44067  *
44068  * Field Enumeration Values:
44069  *
44070  * Enum | Value | Description
44071  * :----------------------------------------------|:------|:------------
44072  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_E_UNMSKED | 0x0 |
44073  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_E_MSKED | 0x1 |
44074  *
44075  * Field Access Macros:
44076  *
44077  */
44078 /*
44079  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3
44080  *
44081  */
44082 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_E_UNMSKED 0x0
44083 /*
44084  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3
44085  *
44086  */
44087 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_E_MSKED 0x1
44088 
44089 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field. */
44090 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_LSB 27
44091 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field. */
44092 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_MSB 27
44093 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field. */
44094 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_WIDTH 1
44095 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field value. */
44096 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_SET_MSK 0x08000000
44097 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field value. */
44098 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_CLR_MSK 0xf7ffffff
44099 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field. */
44100 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_RESET 0x0
44101 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 field value from a register. */
44102 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
44103 /* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field value suitable for setting the register. */
44104 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
44105 
44106 /*
44107  * Field : Mask Byte Control - mbc_4
44108  *
44109  * This array of bits are mask control bits for comparison of each of the MAC
44110  * Address bytes. When masked, the MAC does not compare the corresponding byte of
44111  * received DA or SA with the contents of MAC Address28 high and low registers.
44112  * Each bit controls the masking of the bytes. You can filter a group of addresses
44113  * (known as group address filtering) by masking one or more bytes of the address.
44114  *
44115  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
44116  *
44117  * Field Enumeration Values:
44118  *
44119  * Enum | Value | Description
44120  * :----------------------------------------------|:------|:------------
44121  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_E_UNMSKED | 0x0 |
44122  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_E_MSKED | 0x1 |
44123  *
44124  * Field Access Macros:
44125  *
44126  */
44127 /*
44128  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4
44129  *
44130  */
44131 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_E_UNMSKED 0x0
44132 /*
44133  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4
44134  *
44135  */
44136 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_E_MSKED 0x1
44137 
44138 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field. */
44139 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_LSB 28
44140 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field. */
44141 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_MSB 28
44142 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field. */
44143 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_WIDTH 1
44144 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field value. */
44145 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_SET_MSK 0x10000000
44146 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field value. */
44147 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_CLR_MSK 0xefffffff
44148 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field. */
44149 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_RESET 0x0
44150 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 field value from a register. */
44151 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
44152 /* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field value suitable for setting the register. */
44153 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
44154 
44155 /*
44156  * Field : Mask Byte Control - mbc_5
44157  *
44158  * This array of bits are mask control bits for comparison of each of the MAC
44159  * Address bytes. When masked, the MAC does not compare the corresponding byte of
44160  * received DA or SA with the contents of MAC Address28 high and low registers.
44161  * Each bit controls the masking of the bytes. You can filter a group of addresses
44162  * (known as group address filtering) by masking one or more bytes of the address.
44163  *
44164  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
44165  *
44166  * Field Enumeration Values:
44167  *
44168  * Enum | Value | Description
44169  * :----------------------------------------------|:------|:------------
44170  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_E_UNMSKED | 0x0 |
44171  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_E_MSKED | 0x1 |
44172  *
44173  * Field Access Macros:
44174  *
44175  */
44176 /*
44177  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5
44178  *
44179  */
44180 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_E_UNMSKED 0x0
44181 /*
44182  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5
44183  *
44184  */
44185 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_E_MSKED 0x1
44186 
44187 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field. */
44188 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_LSB 29
44189 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field. */
44190 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_MSB 29
44191 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field. */
44192 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_WIDTH 1
44193 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field value. */
44194 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_SET_MSK 0x20000000
44195 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field value. */
44196 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_CLR_MSK 0xdfffffff
44197 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field. */
44198 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_RESET 0x0
44199 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 field value from a register. */
44200 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
44201 /* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field value suitable for setting the register. */
44202 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
44203 
44204 /*
44205  * Field : sa
44206  *
44207  * Source Address
44208  *
44209  * When this bit is set, the MAC Address28[47:0] is used to compare with the SA
44210  * fields of the received frame.
44211  *
44212  * When this bit is reset, the MAC Address28[47:0] is used to compare with the DA
44213  * fields of the received frame.
44214  *
44215  * Field Enumeration Values:
44216  *
44217  * Enum | Value | Description
44218  * :----------------------------------------|:------|:------------
44219  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_E_DISD | 0x0 |
44220  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_E_END | 0x1 |
44221  *
44222  * Field Access Macros:
44223  *
44224  */
44225 /*
44226  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA
44227  *
44228  */
44229 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_E_DISD 0x0
44230 /*
44231  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA
44232  *
44233  */
44234 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_E_END 0x1
44235 
44236 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field. */
44237 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_LSB 30
44238 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field. */
44239 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_MSB 30
44240 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field. */
44241 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_WIDTH 1
44242 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field value. */
44243 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_SET_MSK 0x40000000
44244 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field value. */
44245 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_CLR_MSK 0xbfffffff
44246 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field. */
44247 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_RESET 0x0
44248 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA field value from a register. */
44249 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
44250 /* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field value suitable for setting the register. */
44251 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
44252 
44253 /*
44254  * Field : ae
44255  *
44256  * Address Enable
44257  *
44258  * When this bit is set, the address filter module uses the 29th MAC address for
44259  * perfect filtering.
44260  *
44261  * When this bit is reset, the address filter module ignores the address for
44262  * filtering.
44263  *
44264  * Field Enumeration Values:
44265  *
44266  * Enum | Value | Description
44267  * :----------------------------------------|:------|:------------
44268  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_E_DISD | 0x0 |
44269  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_E_END | 0x1 |
44270  *
44271  * Field Access Macros:
44272  *
44273  */
44274 /*
44275  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE
44276  *
44277  */
44278 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_E_DISD 0x0
44279 /*
44280  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE
44281  *
44282  */
44283 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_E_END 0x1
44284 
44285 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field. */
44286 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_LSB 31
44287 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field. */
44288 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_MSB 31
44289 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field. */
44290 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_WIDTH 1
44291 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field value. */
44292 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_SET_MSK 0x80000000
44293 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field value. */
44294 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_CLR_MSK 0x7fffffff
44295 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field. */
44296 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_RESET 0x0
44297 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE field value from a register. */
44298 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
44299 /* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field value suitable for setting the register. */
44300 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
44301 
44302 #ifndef __ASSEMBLY__
44303 /*
44304  * WARNING: The C register and register group struct declarations are provided for
44305  * convenience and illustrative purposes. They should, however, be used with
44306  * caution as the C language standard provides no guarantees about the alignment or
44307  * atomicity of device memory accesses. The recommended practice for writing
44308  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
44309  * alt_write_word() functions.
44310  *
44311  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR28_HIGH.
44312  */
44313 struct ALT_EMAC_GMAC_MAC_ADDR28_HIGH_s
44314 {
44315  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI */
44316  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR28_HIGH_RSVD_23_16 */
44317  uint32_t mbc_0 : 1; /* Mask Byte Control */
44318  uint32_t mbc_1 : 1; /* Mask Byte Control */
44319  uint32_t mbc_2 : 1; /* Mask Byte Control */
44320  uint32_t mbc_3 : 1; /* Mask Byte Control */
44321  uint32_t mbc_4 : 1; /* Mask Byte Control */
44322  uint32_t mbc_5 : 1; /* Mask Byte Control */
44323  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA */
44324  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE */
44325 };
44326 
44327 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR28_HIGH. */
44328 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR28_HIGH_s ALT_EMAC_GMAC_MAC_ADDR28_HIGH_t;
44329 #endif /* __ASSEMBLY__ */
44330 
44331 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH register. */
44332 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_RESET 0x0000ffff
44333 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH register from the beginning of the component. */
44334 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_OFST 0x860
44335 /* The address of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH register. */
44336 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR28_HIGH_OFST))
44337 
44338 /*
44339  * Register : gmacgrp_mac_address28_low
44340  *
44341  * <b> Register 537 (MAC Address28 Low Register) </b>
44342  *
44343  * The MAC Address28 Low register holds the lower 32 bits of the 29th 6-byte MAC
44344  * address of the station.
44345  *
44346  * Register Layout
44347  *
44348  * Bits | Access | Reset | Description
44349  * :-------|:-------|:-----------|:------------------------------------
44350  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO
44351  *
44352  */
44353 /*
44354  * Field : addrlo
44355  *
44356  * MAC Address28 [31:0]
44357  *
44358  * This field contains the lower 32 bits of the 29th 6-byte MAC address. The
44359  * content of this field is undefined until loaded by the Application after the
44360  * initialization process.
44361  *
44362  * Field Access Macros:
44363  *
44364  */
44365 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field. */
44366 #define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_LSB 0
44367 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field. */
44368 #define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_MSB 31
44369 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field. */
44370 #define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_WIDTH 32
44371 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field value. */
44372 #define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_SET_MSK 0xffffffff
44373 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field value. */
44374 #define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_CLR_MSK 0x00000000
44375 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field. */
44376 #define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_RESET 0xffffffff
44377 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO field value from a register. */
44378 #define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
44379 /* Produces a ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field value suitable for setting the register. */
44380 #define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
44381 
44382 #ifndef __ASSEMBLY__
44383 /*
44384  * WARNING: The C register and register group struct declarations are provided for
44385  * convenience and illustrative purposes. They should, however, be used with
44386  * caution as the C language standard provides no guarantees about the alignment or
44387  * atomicity of device memory accesses. The recommended practice for writing
44388  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
44389  * alt_write_word() functions.
44390  *
44391  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR28_LOW.
44392  */
44393 struct ALT_EMAC_GMAC_MAC_ADDR28_LOW_s
44394 {
44395  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO */
44396 };
44397 
44398 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR28_LOW. */
44399 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR28_LOW_s ALT_EMAC_GMAC_MAC_ADDR28_LOW_t;
44400 #endif /* __ASSEMBLY__ */
44401 
44402 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_LOW register. */
44403 #define ALT_EMAC_GMAC_MAC_ADDR28_LOW_RESET 0xffffffff
44404 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR28_LOW register from the beginning of the component. */
44405 #define ALT_EMAC_GMAC_MAC_ADDR28_LOW_OFST 0x864
44406 /* The address of the ALT_EMAC_GMAC_MAC_ADDR28_LOW register. */
44407 #define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR28_LOW_OFST))
44408 
44409 /*
44410  * Register : gmacgrp_mac_address29_high
44411  *
44412  * <b> Register 538 (MAC Address29 High Register) </b>
44413  *
44414  * The MAC Address29 High register holds the upper 16 bits of the 6-byte 30th MAC
44415  * address of the station.
44416  *
44417  * If the MAC address registers are configured to be double-synchronized to the
44418  * (G)MII clock domains, then
44419  *
44420  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
44421  * or Bits[7:0] (in big-endian mode) of the MAC Address29 Low Register are written.
44422  * For proper synchronization updates, consecutive writes to this MAC Address29 Low
44423  * Register must be performed after at least four clock cycles in the destination
44424  * clock domain.
44425  *
44426  * Register Layout
44427  *
44428  * Bits | Access | Reset | Description
44429  * :--------|:-------|:-------|:-----------------------------------------
44430  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI
44431  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR29_HIGH_RSVD_23_16
44432  * [24] | RW | 0x0 | Mask Byte Control
44433  * [25] | RW | 0x0 | Mask Byte Control
44434  * [26] | RW | 0x0 | Mask Byte Control
44435  * [27] | RW | 0x0 | Mask Byte Control
44436  * [28] | RW | 0x0 | Mask Byte Control
44437  * [29] | RW | 0x0 | Mask Byte Control
44438  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA
44439  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE
44440  *
44441  */
44442 /*
44443  * Field : addrhi
44444  *
44445  * MAC Address29 [47:32]
44446  *
44447  * This field contains the upper 16 bits (47:32) of the 30th 6-byte MAC address.
44448  *
44449  * Field Access Macros:
44450  *
44451  */
44452 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field. */
44453 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_LSB 0
44454 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field. */
44455 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_MSB 15
44456 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field. */
44457 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_WIDTH 16
44458 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field value. */
44459 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_SET_MSK 0x0000ffff
44460 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field value. */
44461 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_CLR_MSK 0xffff0000
44462 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field. */
44463 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_RESET 0xffff
44464 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI field value from a register. */
44465 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
44466 /* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field value suitable for setting the register. */
44467 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
44468 
44469 /*
44470  * Field : reserved_23_16
44471  *
44472  * Reserved
44473  *
44474  * Field Access Macros:
44475  *
44476  */
44477 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_RSVD_23_16 register field. */
44478 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_RSVD_23_16_LSB 16
44479 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_RSVD_23_16 register field. */
44480 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_RSVD_23_16_MSB 23
44481 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_RSVD_23_16 register field. */
44482 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_RSVD_23_16_WIDTH 8
44483 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_RSVD_23_16 register field value. */
44484 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
44485 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_RSVD_23_16 register field value. */
44486 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
44487 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_RSVD_23_16 register field. */
44488 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_RSVD_23_16_RESET 0x0
44489 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_RSVD_23_16 field value from a register. */
44490 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
44491 /* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_RSVD_23_16 register field value suitable for setting the register. */
44492 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
44493 
44494 /*
44495  * Field : Mask Byte Control - mbc_0
44496  *
44497  * This array of bits are mask control bits for comparison of each of the MAC
44498  * Address bytes. When masked, the MAC does not compare the corresponding byte of
44499  * received DA or SA with the contents of MAC Address29 high and low registers.
44500  * Each bit controls the masking of the bytes. You can filter a group of addresses
44501  * (known as group address filtering) by masking one or more bytes of the address.
44502  *
44503  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
44504  *
44505  * Field Enumeration Values:
44506  *
44507  * Enum | Value | Description
44508  * :----------------------------------------------|:------|:------------
44509  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_E_UNMSKED | 0x0 |
44510  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_E_MSKED | 0x1 |
44511  *
44512  * Field Access Macros:
44513  *
44514  */
44515 /*
44516  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0
44517  *
44518  */
44519 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_E_UNMSKED 0x0
44520 /*
44521  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0
44522  *
44523  */
44524 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_E_MSKED 0x1
44525 
44526 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field. */
44527 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_LSB 24
44528 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field. */
44529 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_MSB 24
44530 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field. */
44531 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_WIDTH 1
44532 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field value. */
44533 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_SET_MSK 0x01000000
44534 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field value. */
44535 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_CLR_MSK 0xfeffffff
44536 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field. */
44537 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_RESET 0x0
44538 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 field value from a register. */
44539 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
44540 /* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field value suitable for setting the register. */
44541 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
44542 
44543 /*
44544  * Field : Mask Byte Control - mbc_1
44545  *
44546  * This array of bits are mask control bits for comparison of each of the MAC
44547  * Address bytes. When masked, the MAC does not compare the corresponding byte of
44548  * received DA or SA with the contents of MAC Address29 high and low registers.
44549  * Each bit controls the masking of the bytes. You can filter a group of addresses
44550  * (known as group address filtering) by masking one or more bytes of the address.
44551  *
44552  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
44553  *
44554  * Field Enumeration Values:
44555  *
44556  * Enum | Value | Description
44557  * :----------------------------------------------|:------|:------------
44558  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_E_UNMSKED | 0x0 |
44559  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_E_MSKED | 0x1 |
44560  *
44561  * Field Access Macros:
44562  *
44563  */
44564 /*
44565  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1
44566  *
44567  */
44568 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_E_UNMSKED 0x0
44569 /*
44570  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1
44571  *
44572  */
44573 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_E_MSKED 0x1
44574 
44575 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field. */
44576 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_LSB 25
44577 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field. */
44578 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_MSB 25
44579 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field. */
44580 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_WIDTH 1
44581 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field value. */
44582 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_SET_MSK 0x02000000
44583 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field value. */
44584 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_CLR_MSK 0xfdffffff
44585 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field. */
44586 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_RESET 0x0
44587 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 field value from a register. */
44588 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
44589 /* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field value suitable for setting the register. */
44590 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
44591 
44592 /*
44593  * Field : Mask Byte Control - mbc_2
44594  *
44595  * This array of bits are mask control bits for comparison of each of the MAC
44596  * Address bytes. When masked, the MAC does not compare the corresponding byte of
44597  * received DA or SA with the contents of MAC Address29 high and low registers.
44598  * Each bit controls the masking of the bytes. You can filter a group of addresses
44599  * (known as group address filtering) by masking one or more bytes of the address.
44600  *
44601  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
44602  *
44603  * Field Enumeration Values:
44604  *
44605  * Enum | Value | Description
44606  * :----------------------------------------------|:------|:------------
44607  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_E_UNMSKED | 0x0 |
44608  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_E_MSKED | 0x1 |
44609  *
44610  * Field Access Macros:
44611  *
44612  */
44613 /*
44614  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2
44615  *
44616  */
44617 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_E_UNMSKED 0x0
44618 /*
44619  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2
44620  *
44621  */
44622 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_E_MSKED 0x1
44623 
44624 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field. */
44625 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_LSB 26
44626 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field. */
44627 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_MSB 26
44628 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field. */
44629 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_WIDTH 1
44630 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field value. */
44631 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_SET_MSK 0x04000000
44632 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field value. */
44633 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_CLR_MSK 0xfbffffff
44634 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field. */
44635 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_RESET 0x0
44636 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 field value from a register. */
44637 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
44638 /* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field value suitable for setting the register. */
44639 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
44640 
44641 /*
44642  * Field : Mask Byte Control - mbc_3
44643  *
44644  * This array of bits are mask control bits for comparison of each of the MAC
44645  * Address bytes. When masked, the MAC does not compare the corresponding byte of
44646  * received DA or SA with the contents of MAC Address29 high and low registers.
44647  * Each bit controls the masking of the bytes. You can filter a group of addresses
44648  * (known as group address filtering) by masking one or more bytes of the address.
44649  *
44650  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
44651  *
44652  * Field Enumeration Values:
44653  *
44654  * Enum | Value | Description
44655  * :----------------------------------------------|:------|:------------
44656  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_E_UNMSKED | 0x0 |
44657  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_E_MSKED | 0x1 |
44658  *
44659  * Field Access Macros:
44660  *
44661  */
44662 /*
44663  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3
44664  *
44665  */
44666 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_E_UNMSKED 0x0
44667 /*
44668  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3
44669  *
44670  */
44671 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_E_MSKED 0x1
44672 
44673 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field. */
44674 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_LSB 27
44675 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field. */
44676 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_MSB 27
44677 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field. */
44678 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_WIDTH 1
44679 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field value. */
44680 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_SET_MSK 0x08000000
44681 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field value. */
44682 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_CLR_MSK 0xf7ffffff
44683 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field. */
44684 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_RESET 0x0
44685 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 field value from a register. */
44686 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
44687 /* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field value suitable for setting the register. */
44688 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
44689 
44690 /*
44691  * Field : Mask Byte Control - mbc_4
44692  *
44693  * This array of bits are mask control bits for comparison of each of the MAC
44694  * Address bytes. When masked, the MAC does not compare the corresponding byte of
44695  * received DA or SA with the contents of MAC Address29 high and low registers.
44696  * Each bit controls the masking of the bytes. You can filter a group of addresses
44697  * (known as group address filtering) by masking one or more bytes of the address.
44698  *
44699  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
44700  *
44701  * Field Enumeration Values:
44702  *
44703  * Enum | Value | Description
44704  * :----------------------------------------------|:------|:------------
44705  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_E_UNMSKED | 0x0 |
44706  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_E_MSKED | 0x1 |
44707  *
44708  * Field Access Macros:
44709  *
44710  */
44711 /*
44712  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4
44713  *
44714  */
44715 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_E_UNMSKED 0x0
44716 /*
44717  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4
44718  *
44719  */
44720 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_E_MSKED 0x1
44721 
44722 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field. */
44723 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_LSB 28
44724 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field. */
44725 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_MSB 28
44726 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field. */
44727 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_WIDTH 1
44728 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field value. */
44729 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_SET_MSK 0x10000000
44730 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field value. */
44731 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_CLR_MSK 0xefffffff
44732 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field. */
44733 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_RESET 0x0
44734 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 field value from a register. */
44735 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
44736 /* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field value suitable for setting the register. */
44737 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
44738 
44739 /*
44740  * Field : Mask Byte Control - mbc_5
44741  *
44742  * This array of bits are mask control bits for comparison of each of the MAC
44743  * Address bytes. When masked, the MAC does not compare the corresponding byte of
44744  * received DA or SA with the contents of MAC Address29 high and low registers.
44745  * Each bit controls the masking of the bytes. You can filter a group of addresses
44746  * (known as group address filtering) by masking one or more bytes of the address.
44747  *
44748  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
44749  *
44750  * Field Enumeration Values:
44751  *
44752  * Enum | Value | Description
44753  * :----------------------------------------------|:------|:------------
44754  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_E_UNMSKED | 0x0 |
44755  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_E_MSKED | 0x1 |
44756  *
44757  * Field Access Macros:
44758  *
44759  */
44760 /*
44761  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5
44762  *
44763  */
44764 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_E_UNMSKED 0x0
44765 /*
44766  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5
44767  *
44768  */
44769 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_E_MSKED 0x1
44770 
44771 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field. */
44772 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_LSB 29
44773 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field. */
44774 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_MSB 29
44775 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field. */
44776 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_WIDTH 1
44777 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field value. */
44778 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_SET_MSK 0x20000000
44779 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field value. */
44780 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_CLR_MSK 0xdfffffff
44781 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field. */
44782 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_RESET 0x0
44783 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 field value from a register. */
44784 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
44785 /* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field value suitable for setting the register. */
44786 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
44787 
44788 /*
44789  * Field : sa
44790  *
44791  * Source Address
44792  *
44793  * When this bit is set, the MAC Address29[47:0] is used to compare with the SA
44794  * fields of the received frame.
44795  *
44796  * When this bit is reset, the MAC Address29[47:0] is used to compare with the DA
44797  * fields of the received frame.
44798  *
44799  * Field Enumeration Values:
44800  *
44801  * Enum | Value | Description
44802  * :----------------------------------------|:------|:------------
44803  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_E_DISD | 0x0 |
44804  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_E_END | 0x1 |
44805  *
44806  * Field Access Macros:
44807  *
44808  */
44809 /*
44810  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA
44811  *
44812  */
44813 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_E_DISD 0x0
44814 /*
44815  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA
44816  *
44817  */
44818 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_E_END 0x1
44819 
44820 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field. */
44821 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_LSB 30
44822 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field. */
44823 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_MSB 30
44824 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field. */
44825 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_WIDTH 1
44826 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field value. */
44827 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_SET_MSK 0x40000000
44828 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field value. */
44829 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_CLR_MSK 0xbfffffff
44830 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field. */
44831 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_RESET 0x0
44832 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA field value from a register. */
44833 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
44834 /* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field value suitable for setting the register. */
44835 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
44836 
44837 /*
44838  * Field : ae
44839  *
44840  * Address Enable
44841  *
44842  * When this bit is set, the address filter module uses the 30th MAC address for
44843  * perfect filtering.
44844  *
44845  * When this bit is reset, the address filter module ignores the address for
44846  * filtering.
44847  *
44848  * Field Enumeration Values:
44849  *
44850  * Enum | Value | Description
44851  * :----------------------------------------|:------|:------------
44852  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_E_DISD | 0x0 |
44853  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_E_END | 0x1 |
44854  *
44855  * Field Access Macros:
44856  *
44857  */
44858 /*
44859  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE
44860  *
44861  */
44862 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_E_DISD 0x0
44863 /*
44864  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE
44865  *
44866  */
44867 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_E_END 0x1
44868 
44869 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field. */
44870 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_LSB 31
44871 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field. */
44872 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_MSB 31
44873 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field. */
44874 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_WIDTH 1
44875 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field value. */
44876 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_SET_MSK 0x80000000
44877 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field value. */
44878 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_CLR_MSK 0x7fffffff
44879 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field. */
44880 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_RESET 0x0
44881 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE field value from a register. */
44882 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
44883 /* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field value suitable for setting the register. */
44884 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
44885 
44886 #ifndef __ASSEMBLY__
44887 /*
44888  * WARNING: The C register and register group struct declarations are provided for
44889  * convenience and illustrative purposes. They should, however, be used with
44890  * caution as the C language standard provides no guarantees about the alignment or
44891  * atomicity of device memory accesses. The recommended practice for writing
44892  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
44893  * alt_write_word() functions.
44894  *
44895  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR29_HIGH.
44896  */
44897 struct ALT_EMAC_GMAC_MAC_ADDR29_HIGH_s
44898 {
44899  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI */
44900  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR29_HIGH_RSVD_23_16 */
44901  uint32_t mbc_0 : 1; /* Mask Byte Control */
44902  uint32_t mbc_1 : 1; /* Mask Byte Control */
44903  uint32_t mbc_2 : 1; /* Mask Byte Control */
44904  uint32_t mbc_3 : 1; /* Mask Byte Control */
44905  uint32_t mbc_4 : 1; /* Mask Byte Control */
44906  uint32_t mbc_5 : 1; /* Mask Byte Control */
44907  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA */
44908  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE */
44909 };
44910 
44911 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR29_HIGH. */
44912 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR29_HIGH_s ALT_EMAC_GMAC_MAC_ADDR29_HIGH_t;
44913 #endif /* __ASSEMBLY__ */
44914 
44915 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH register. */
44916 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_RESET 0x0000ffff
44917 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH register from the beginning of the component. */
44918 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_OFST 0x868
44919 /* The address of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH register. */
44920 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR29_HIGH_OFST))
44921 
44922 /*
44923  * Register : gmacgrp_mac_address29_low
44924  *
44925  * <b> Register 539 (MAC Address29 Low Register) </b>
44926  *
44927  * The MAC Address29 Low register holds the lower 32 bits of the 30th 6-byte MAC
44928  * address of the station.
44929  *
44930  * Register Layout
44931  *
44932  * Bits | Access | Reset | Description
44933  * :-------|:-------|:-----------|:------------------------------------
44934  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO
44935  *
44936  */
44937 /*
44938  * Field : addrlo
44939  *
44940  * MAC Address29 [31:0]
44941  *
44942  * This field contains the lower 32 bits of the 30th 6-byte MAC address. The
44943  * content of this field is undefined until loaded by the Application after the
44944  * initialization process.
44945  *
44946  * Field Access Macros:
44947  *
44948  */
44949 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field. */
44950 #define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_LSB 0
44951 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field. */
44952 #define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_MSB 31
44953 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field. */
44954 #define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_WIDTH 32
44955 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field value. */
44956 #define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_SET_MSK 0xffffffff
44957 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field value. */
44958 #define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_CLR_MSK 0x00000000
44959 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field. */
44960 #define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_RESET 0xffffffff
44961 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO field value from a register. */
44962 #define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
44963 /* Produces a ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field value suitable for setting the register. */
44964 #define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
44965 
44966 #ifndef __ASSEMBLY__
44967 /*
44968  * WARNING: The C register and register group struct declarations are provided for
44969  * convenience and illustrative purposes. They should, however, be used with
44970  * caution as the C language standard provides no guarantees about the alignment or
44971  * atomicity of device memory accesses. The recommended practice for writing
44972  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
44973  * alt_write_word() functions.
44974  *
44975  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR29_LOW.
44976  */
44977 struct ALT_EMAC_GMAC_MAC_ADDR29_LOW_s
44978 {
44979  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO */
44980 };
44981 
44982 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR29_LOW. */
44983 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR29_LOW_s ALT_EMAC_GMAC_MAC_ADDR29_LOW_t;
44984 #endif /* __ASSEMBLY__ */
44985 
44986 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_LOW register. */
44987 #define ALT_EMAC_GMAC_MAC_ADDR29_LOW_RESET 0xffffffff
44988 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR29_LOW register from the beginning of the component. */
44989 #define ALT_EMAC_GMAC_MAC_ADDR29_LOW_OFST 0x86c
44990 /* The address of the ALT_EMAC_GMAC_MAC_ADDR29_LOW register. */
44991 #define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR29_LOW_OFST))
44992 
44993 /*
44994  * Register : gmacgrp_mac_address30_high
44995  *
44996  * <b> Register 540 (MAC Address30 High Register) </b>
44997  *
44998  * The MAC Address30 High register holds the upper 16 bits of the 31st 6-byte MAC
44999  * address of the station.
45000  *
45001  * If the MAC address registers are configured to be double-synchronized to the
45002  * (G)MII clock domains, then
45003  *
45004  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
45005  * or Bits[7:0] (in big-endian mode) of the MAC Address30 Low Register are written.
45006  * For proper synchronization updates, consecutive writes to this MAC Address30 Low
45007  * Register must be performed after at least four clock cycles in the destination
45008  * clock domain.
45009  *
45010  * Register Layout
45011  *
45012  * Bits | Access | Reset | Description
45013  * :--------|:-------|:-------|:-----------------------------------------
45014  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI
45015  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR30_HIGH_RSVD_23_16
45016  * [24] | RW | 0x0 | Mask Byte Control
45017  * [25] | RW | 0x0 | Mask Byte Control
45018  * [26] | RW | 0x0 | Mask Byte Control
45019  * [27] | RW | 0x0 | Mask Byte Control
45020  * [28] | RW | 0x0 | Mask Byte Control
45021  * [29] | RW | 0x0 | Mask Byte Control
45022  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA
45023  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE
45024  *
45025  */
45026 /*
45027  * Field : addrhi
45028  *
45029  * MAC Address30 [47:32]
45030  *
45031  * This field contains the upper 16 bits (47:32) of the 31st 6-byte MAC address.
45032  *
45033  * Field Access Macros:
45034  *
45035  */
45036 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field. */
45037 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_LSB 0
45038 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field. */
45039 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_MSB 15
45040 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field. */
45041 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_WIDTH 16
45042 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field value. */
45043 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_SET_MSK 0x0000ffff
45044 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field value. */
45045 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_CLR_MSK 0xffff0000
45046 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field. */
45047 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_RESET 0xffff
45048 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI field value from a register. */
45049 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
45050 /* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field value suitable for setting the register. */
45051 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
45052 
45053 /*
45054  * Field : reserved_23_16
45055  *
45056  * Reserved
45057  *
45058  * Field Access Macros:
45059  *
45060  */
45061 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_RSVD_23_16 register field. */
45062 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_RSVD_23_16_LSB 16
45063 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_RSVD_23_16 register field. */
45064 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_RSVD_23_16_MSB 23
45065 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_RSVD_23_16 register field. */
45066 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_RSVD_23_16_WIDTH 8
45067 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_RSVD_23_16 register field value. */
45068 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
45069 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_RSVD_23_16 register field value. */
45070 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
45071 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_RSVD_23_16 register field. */
45072 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_RSVD_23_16_RESET 0x0
45073 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_RSVD_23_16 field value from a register. */
45074 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
45075 /* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_RSVD_23_16 register field value suitable for setting the register. */
45076 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
45077 
45078 /*
45079  * Field : Mask Byte Control - mbc_0
45080  *
45081  * This array of bits are mask control bits for comparison of each of the MAC
45082  * Address bytes. When masked, the MAC does not compare the corresponding byte of
45083  * received DA or SA with the contents of MAC Address30 high and low registers.
45084  * Each bit controls the masking of the bytes. You can filter a group of addresses
45085  * (known as group address filtering) by masking one or more bytes of the address.
45086  *
45087  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
45088  *
45089  * Field Enumeration Values:
45090  *
45091  * Enum | Value | Description
45092  * :----------------------------------------------|:------|:------------
45093  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_E_UNMSKED | 0x0 |
45094  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_E_MSKED | 0x1 |
45095  *
45096  * Field Access Macros:
45097  *
45098  */
45099 /*
45100  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0
45101  *
45102  */
45103 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_E_UNMSKED 0x0
45104 /*
45105  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0
45106  *
45107  */
45108 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_E_MSKED 0x1
45109 
45110 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field. */
45111 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_LSB 24
45112 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field. */
45113 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_MSB 24
45114 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field. */
45115 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_WIDTH 1
45116 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field value. */
45117 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_SET_MSK 0x01000000
45118 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field value. */
45119 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_CLR_MSK 0xfeffffff
45120 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field. */
45121 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_RESET 0x0
45122 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 field value from a register. */
45123 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
45124 /* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field value suitable for setting the register. */
45125 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
45126 
45127 /*
45128  * Field : Mask Byte Control - mbc_1
45129  *
45130  * This array of bits are mask control bits for comparison of each of the MAC
45131  * Address bytes. When masked, the MAC does not compare the corresponding byte of
45132  * received DA or SA with the contents of MAC Address30 high and low registers.
45133  * Each bit controls the masking of the bytes. You can filter a group of addresses
45134  * (known as group address filtering) by masking one or more bytes of the address.
45135  *
45136  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
45137  *
45138  * Field Enumeration Values:
45139  *
45140  * Enum | Value | Description
45141  * :----------------------------------------------|:------|:------------
45142  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_E_UNMSKED | 0x0 |
45143  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_E_MSKED | 0x1 |
45144  *
45145  * Field Access Macros:
45146  *
45147  */
45148 /*
45149  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1
45150  *
45151  */
45152 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_E_UNMSKED 0x0
45153 /*
45154  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1
45155  *
45156  */
45157 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_E_MSKED 0x1
45158 
45159 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field. */
45160 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_LSB 25
45161 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field. */
45162 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_MSB 25
45163 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field. */
45164 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_WIDTH 1
45165 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field value. */
45166 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_SET_MSK 0x02000000
45167 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field value. */
45168 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_CLR_MSK 0xfdffffff
45169 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field. */
45170 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_RESET 0x0
45171 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 field value from a register. */
45172 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
45173 /* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field value suitable for setting the register. */
45174 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
45175 
45176 /*
45177  * Field : Mask Byte Control - mbc_2
45178  *
45179  * This array of bits are mask control bits for comparison of each of the MAC
45180  * Address bytes. When masked, the MAC does not compare the corresponding byte of
45181  * received DA or SA with the contents of MAC Address30 high and low registers.
45182  * Each bit controls the masking of the bytes. You can filter a group of addresses
45183  * (known as group address filtering) by masking one or more bytes of the address.
45184  *
45185  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
45186  *
45187  * Field Enumeration Values:
45188  *
45189  * Enum | Value | Description
45190  * :----------------------------------------------|:------|:------------
45191  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_E_UNMSKED | 0x0 |
45192  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_E_MSKED | 0x1 |
45193  *
45194  * Field Access Macros:
45195  *
45196  */
45197 /*
45198  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2
45199  *
45200  */
45201 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_E_UNMSKED 0x0
45202 /*
45203  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2
45204  *
45205  */
45206 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_E_MSKED 0x1
45207 
45208 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field. */
45209 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_LSB 26
45210 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field. */
45211 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_MSB 26
45212 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field. */
45213 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_WIDTH 1
45214 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field value. */
45215 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_SET_MSK 0x04000000
45216 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field value. */
45217 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_CLR_MSK 0xfbffffff
45218 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field. */
45219 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_RESET 0x0
45220 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 field value from a register. */
45221 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
45222 /* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field value suitable for setting the register. */
45223 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
45224 
45225 /*
45226  * Field : Mask Byte Control - mbc_3
45227  *
45228  * This array of bits are mask control bits for comparison of each of the MAC
45229  * Address bytes. When masked, the MAC does not compare the corresponding byte of
45230  * received DA or SA with the contents of MAC Address30 high and low registers.
45231  * Each bit controls the masking of the bytes. You can filter a group of addresses
45232  * (known as group address filtering) by masking one or more bytes of the address.
45233  *
45234  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
45235  *
45236  * Field Enumeration Values:
45237  *
45238  * Enum | Value | Description
45239  * :----------------------------------------------|:------|:------------
45240  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_E_UNMSKED | 0x0 |
45241  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_E_MSKED | 0x1 |
45242  *
45243  * Field Access Macros:
45244  *
45245  */
45246 /*
45247  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3
45248  *
45249  */
45250 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_E_UNMSKED 0x0
45251 /*
45252  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3
45253  *
45254  */
45255 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_E_MSKED 0x1
45256 
45257 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field. */
45258 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_LSB 27
45259 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field. */
45260 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_MSB 27
45261 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field. */
45262 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_WIDTH 1
45263 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field value. */
45264 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_SET_MSK 0x08000000
45265 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field value. */
45266 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_CLR_MSK 0xf7ffffff
45267 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field. */
45268 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_RESET 0x0
45269 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 field value from a register. */
45270 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
45271 /* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field value suitable for setting the register. */
45272 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
45273 
45274 /*
45275  * Field : Mask Byte Control - mbc_4
45276  *
45277  * This array of bits are mask control bits for comparison of each of the MAC
45278  * Address bytes. When masked, the MAC does not compare the corresponding byte of
45279  * received DA or SA with the contents of MAC Address30 high and low registers.
45280  * Each bit controls the masking of the bytes. You can filter a group of addresses
45281  * (known as group address filtering) by masking one or more bytes of the address.
45282  *
45283  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
45284  *
45285  * Field Enumeration Values:
45286  *
45287  * Enum | Value | Description
45288  * :----------------------------------------------|:------|:------------
45289  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_E_UNMSKED | 0x0 |
45290  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_E_MSKED | 0x1 |
45291  *
45292  * Field Access Macros:
45293  *
45294  */
45295 /*
45296  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4
45297  *
45298  */
45299 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_E_UNMSKED 0x0
45300 /*
45301  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4
45302  *
45303  */
45304 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_E_MSKED 0x1
45305 
45306 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field. */
45307 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_LSB 28
45308 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field. */
45309 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_MSB 28
45310 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field. */
45311 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_WIDTH 1
45312 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field value. */
45313 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_SET_MSK 0x10000000
45314 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field value. */
45315 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_CLR_MSK 0xefffffff
45316 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field. */
45317 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_RESET 0x0
45318 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 field value from a register. */
45319 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
45320 /* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field value suitable for setting the register. */
45321 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
45322 
45323 /*
45324  * Field : Mask Byte Control - mbc_5
45325  *
45326  * This array of bits are mask control bits for comparison of each of the MAC
45327  * Address bytes. When masked, the MAC does not compare the corresponding byte of
45328  * received DA or SA with the contents of MAC Address30 high and low registers.
45329  * Each bit controls the masking of the bytes. You can filter a group of addresses
45330  * (known as group address filtering) by masking one or more bytes of the address.
45331  *
45332  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
45333  *
45334  * Field Enumeration Values:
45335  *
45336  * Enum | Value | Description
45337  * :----------------------------------------------|:------|:------------
45338  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_E_UNMSKED | 0x0 |
45339  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_E_MSKED | 0x1 |
45340  *
45341  * Field Access Macros:
45342  *
45343  */
45344 /*
45345  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5
45346  *
45347  */
45348 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_E_UNMSKED 0x0
45349 /*
45350  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5
45351  *
45352  */
45353 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_E_MSKED 0x1
45354 
45355 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field. */
45356 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_LSB 29
45357 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field. */
45358 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_MSB 29
45359 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field. */
45360 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_WIDTH 1
45361 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field value. */
45362 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_SET_MSK 0x20000000
45363 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field value. */
45364 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_CLR_MSK 0xdfffffff
45365 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field. */
45366 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_RESET 0x0
45367 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 field value from a register. */
45368 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
45369 /* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field value suitable for setting the register. */
45370 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
45371 
45372 /*
45373  * Field : sa
45374  *
45375  * Source Address
45376  *
45377  * When this bit is set, the MAC Address30[47:0] is used to compare with the SA
45378  * fields of the received frame.
45379  *
45380  * When this bit is reset, the MAC Address30[47:0] is used to compare with the DA
45381  * fields of the received frame.
45382  *
45383  * Field Enumeration Values:
45384  *
45385  * Enum | Value | Description
45386  * :----------------------------------------|:------|:------------
45387  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_E_DISD | 0x0 |
45388  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_E_END | 0x1 |
45389  *
45390  * Field Access Macros:
45391  *
45392  */
45393 /*
45394  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA
45395  *
45396  */
45397 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_E_DISD 0x0
45398 /*
45399  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA
45400  *
45401  */
45402 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_E_END 0x1
45403 
45404 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field. */
45405 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_LSB 30
45406 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field. */
45407 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_MSB 30
45408 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field. */
45409 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_WIDTH 1
45410 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field value. */
45411 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_SET_MSK 0x40000000
45412 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field value. */
45413 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_CLR_MSK 0xbfffffff
45414 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field. */
45415 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_RESET 0x0
45416 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA field value from a register. */
45417 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
45418 /* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field value suitable for setting the register. */
45419 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
45420 
45421 /*
45422  * Field : ae
45423  *
45424  * Address Enable
45425  *
45426  * When this bit is set, the address filter module uses the 31st MAC address for
45427  * perfect filtering.
45428  *
45429  * When this bit is reset, the address filter module ignores the address for
45430  * filtering.
45431  *
45432  * Field Enumeration Values:
45433  *
45434  * Enum | Value | Description
45435  * :----------------------------------------|:------|:------------
45436  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_E_DISD | 0x0 |
45437  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_E_END | 0x1 |
45438  *
45439  * Field Access Macros:
45440  *
45441  */
45442 /*
45443  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE
45444  *
45445  */
45446 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_E_DISD 0x0
45447 /*
45448  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE
45449  *
45450  */
45451 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_E_END 0x1
45452 
45453 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field. */
45454 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_LSB 31
45455 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field. */
45456 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_MSB 31
45457 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field. */
45458 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_WIDTH 1
45459 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field value. */
45460 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_SET_MSK 0x80000000
45461 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field value. */
45462 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_CLR_MSK 0x7fffffff
45463 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field. */
45464 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_RESET 0x0
45465 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE field value from a register. */
45466 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
45467 /* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field value suitable for setting the register. */
45468 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
45469 
45470 #ifndef __ASSEMBLY__
45471 /*
45472  * WARNING: The C register and register group struct declarations are provided for
45473  * convenience and illustrative purposes. They should, however, be used with
45474  * caution as the C language standard provides no guarantees about the alignment or
45475  * atomicity of device memory accesses. The recommended practice for writing
45476  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
45477  * alt_write_word() functions.
45478  *
45479  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR30_HIGH.
45480  */
45481 struct ALT_EMAC_GMAC_MAC_ADDR30_HIGH_s
45482 {
45483  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI */
45484  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR30_HIGH_RSVD_23_16 */
45485  uint32_t mbc_0 : 1; /* Mask Byte Control */
45486  uint32_t mbc_1 : 1; /* Mask Byte Control */
45487  uint32_t mbc_2 : 1; /* Mask Byte Control */
45488  uint32_t mbc_3 : 1; /* Mask Byte Control */
45489  uint32_t mbc_4 : 1; /* Mask Byte Control */
45490  uint32_t mbc_5 : 1; /* Mask Byte Control */
45491  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA */
45492  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE */
45493 };
45494 
45495 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR30_HIGH. */
45496 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR30_HIGH_s ALT_EMAC_GMAC_MAC_ADDR30_HIGH_t;
45497 #endif /* __ASSEMBLY__ */
45498 
45499 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH register. */
45500 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_RESET 0x0000ffff
45501 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH register from the beginning of the component. */
45502 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_OFST 0x870
45503 /* The address of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH register. */
45504 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR30_HIGH_OFST))
45505 
45506 /*
45507  * Register : gmacgrp_mac_address30_low
45508  *
45509  * <b> Register 541 (MAC Address30 Low Register) </b>
45510  *
45511  * The MAC Address30 Low register holds the lower 32 bits of the 31st 6-byte MAC
45512  * address of the station.
45513  *
45514  * Register Layout
45515  *
45516  * Bits | Access | Reset | Description
45517  * :-------|:-------|:-----------|:------------------------------------
45518  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO
45519  *
45520  */
45521 /*
45522  * Field : addrlo
45523  *
45524  * MAC Address30 [31:0]
45525  *
45526  * This field contains the lower 32 bits of the 31st 6-byte MAC address. The
45527  * content of this field is undefined until loaded by the Application after the
45528  * initialization process.
45529  *
45530  * Field Access Macros:
45531  *
45532  */
45533 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field. */
45534 #define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_LSB 0
45535 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field. */
45536 #define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_MSB 31
45537 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field. */
45538 #define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_WIDTH 32
45539 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field value. */
45540 #define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_SET_MSK 0xffffffff
45541 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field value. */
45542 #define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_CLR_MSK 0x00000000
45543 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field. */
45544 #define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_RESET 0xffffffff
45545 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO field value from a register. */
45546 #define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
45547 /* Produces a ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field value suitable for setting the register. */
45548 #define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
45549 
45550 #ifndef __ASSEMBLY__
45551 /*
45552  * WARNING: The C register and register group struct declarations are provided for
45553  * convenience and illustrative purposes. They should, however, be used with
45554  * caution as the C language standard provides no guarantees about the alignment or
45555  * atomicity of device memory accesses. The recommended practice for writing
45556  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
45557  * alt_write_word() functions.
45558  *
45559  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR30_LOW.
45560  */
45561 struct ALT_EMAC_GMAC_MAC_ADDR30_LOW_s
45562 {
45563  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO */
45564 };
45565 
45566 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR30_LOW. */
45567 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR30_LOW_s ALT_EMAC_GMAC_MAC_ADDR30_LOW_t;
45568 #endif /* __ASSEMBLY__ */
45569 
45570 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_LOW register. */
45571 #define ALT_EMAC_GMAC_MAC_ADDR30_LOW_RESET 0xffffffff
45572 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR30_LOW register from the beginning of the component. */
45573 #define ALT_EMAC_GMAC_MAC_ADDR30_LOW_OFST 0x874
45574 /* The address of the ALT_EMAC_GMAC_MAC_ADDR30_LOW register. */
45575 #define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR30_LOW_OFST))
45576 
45577 /*
45578  * Register : gmacgrp_mac_address31_high
45579  *
45580  * <b> Register 542 (MAC Address31 High Register) </b>
45581  *
45582  * The MAC Address31 High register holds the upper 16 bits of the 32nd 6-byte MAC
45583  * address of the station. If the MAC address registers are configured to be
45584  * double-synchronized to the (G)MII clock domains, then the synchronization is
45585  * triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
45586  * endian mode) of the MAC Address31 Low Register are written. For proper
45587  * synchronization updates, consecutive writes to this MAC Address31 Low Register
45588  * must be performed after at least four clock cycles in the destination clock
45589  * domain.
45590  *
45591  * Register Layout
45592  *
45593  * Bits | Access | Reset | Description
45594  * :--------|:-------|:-------|:-----------------------------------------
45595  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI
45596  * [23:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR31_HIGH_RSVD_23_16
45597  * [24] | RW | 0x0 | Mask Byte Control
45598  * [25] | RW | 0x0 | Mask Byte Control
45599  * [26] | RW | 0x0 | Mask Byte Control
45600  * [27] | RW | 0x0 | Mask Byte Control
45601  * [28] | RW | 0x0 | Mask Byte Control
45602  * [29] | RW | 0x0 | Mask Byte Control
45603  * [30] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA
45604  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE
45605  *
45606  */
45607 /*
45608  * Field : addrhi
45609  *
45610  * MAC Address31 [47:32]
45611  *
45612  * This field contains the upper 16 bits (47:32) of the 32nd 6-byte MAC address.
45613  *
45614  * Field Access Macros:
45615  *
45616  */
45617 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field. */
45618 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_LSB 0
45619 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field. */
45620 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_MSB 15
45621 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field. */
45622 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_WIDTH 16
45623 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field value. */
45624 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_SET_MSK 0x0000ffff
45625 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field value. */
45626 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_CLR_MSK 0xffff0000
45627 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field. */
45628 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_RESET 0xffff
45629 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI field value from a register. */
45630 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
45631 /* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field value suitable for setting the register. */
45632 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
45633 
45634 /*
45635  * Field : reserved_23_16
45636  *
45637  * Reserved
45638  *
45639  * Field Access Macros:
45640  *
45641  */
45642 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_RSVD_23_16 register field. */
45643 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_RSVD_23_16_LSB 16
45644 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_RSVD_23_16 register field. */
45645 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_RSVD_23_16_MSB 23
45646 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_RSVD_23_16 register field. */
45647 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_RSVD_23_16_WIDTH 8
45648 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_RSVD_23_16 register field value. */
45649 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_RSVD_23_16_SET_MSK 0x00ff0000
45650 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_RSVD_23_16 register field value. */
45651 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_RSVD_23_16_CLR_MSK 0xff00ffff
45652 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_RSVD_23_16 register field. */
45653 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_RSVD_23_16_RESET 0x0
45654 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_RSVD_23_16 field value from a register. */
45655 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_RSVD_23_16_GET(value) (((value) & 0x00ff0000) >> 16)
45656 /* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_RSVD_23_16 register field value suitable for setting the register. */
45657 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_RSVD_23_16_SET(value) (((value) << 16) & 0x00ff0000)
45658 
45659 /*
45660  * Field : Mask Byte Control - mbc_0
45661  *
45662  * This array of bits are mask control bits for comparison of each of the MAC
45663  * Address bytes. When masked, the MAC does not compare the corresponding byte of
45664  * received DA or SA with the contents of MAC Address31 high and low registers.
45665  * Each bit controls the masking of the bytes. You can filter a group of addresses
45666  * (known as group address filtering) by masking one or more bytes of the address.
45667  *
45668  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
45669  *
45670  * Field Enumeration Values:
45671  *
45672  * Enum | Value | Description
45673  * :----------------------------------------------|:------|:------------
45674  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_E_UNMSKED | 0x0 |
45675  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_E_MSKED | 0x1 |
45676  *
45677  * Field Access Macros:
45678  *
45679  */
45680 /*
45681  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0
45682  *
45683  */
45684 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_E_UNMSKED 0x0
45685 /*
45686  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0
45687  *
45688  */
45689 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_E_MSKED 0x1
45690 
45691 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field. */
45692 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_LSB 24
45693 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field. */
45694 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_MSB 24
45695 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field. */
45696 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_WIDTH 1
45697 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field value. */
45698 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_SET_MSK 0x01000000
45699 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field value. */
45700 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_CLR_MSK 0xfeffffff
45701 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field. */
45702 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_RESET 0x0
45703 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 field value from a register. */
45704 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
45705 /* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field value suitable for setting the register. */
45706 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
45707 
45708 /*
45709  * Field : Mask Byte Control - mbc_1
45710  *
45711  * This array of bits are mask control bits for comparison of each of the MAC
45712  * Address bytes. When masked, the MAC does not compare the corresponding byte of
45713  * received DA or SA with the contents of MAC Address31 high and low registers.
45714  * Each bit controls the masking of the bytes. You can filter a group of addresses
45715  * (known as group address filtering) by masking one or more bytes of the address.
45716  *
45717  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
45718  *
45719  * Field Enumeration Values:
45720  *
45721  * Enum | Value | Description
45722  * :----------------------------------------------|:------|:------------
45723  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_E_UNMSKED | 0x0 |
45724  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_E_MSKED | 0x1 |
45725  *
45726  * Field Access Macros:
45727  *
45728  */
45729 /*
45730  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1
45731  *
45732  */
45733 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_E_UNMSKED 0x0
45734 /*
45735  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1
45736  *
45737  */
45738 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_E_MSKED 0x1
45739 
45740 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field. */
45741 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_LSB 25
45742 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field. */
45743 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_MSB 25
45744 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field. */
45745 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_WIDTH 1
45746 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field value. */
45747 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_SET_MSK 0x02000000
45748 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field value. */
45749 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_CLR_MSK 0xfdffffff
45750 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field. */
45751 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_RESET 0x0
45752 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 field value from a register. */
45753 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
45754 /* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field value suitable for setting the register. */
45755 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
45756 
45757 /*
45758  * Field : Mask Byte Control - mbc_2
45759  *
45760  * This array of bits are mask control bits for comparison of each of the MAC
45761  * Address bytes. When masked, the MAC does not compare the corresponding byte of
45762  * received DA or SA with the contents of MAC Address31 high and low registers.
45763  * Each bit controls the masking of the bytes. You can filter a group of addresses
45764  * (known as group address filtering) by masking one or more bytes of the address.
45765  *
45766  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
45767  *
45768  * Field Enumeration Values:
45769  *
45770  * Enum | Value | Description
45771  * :----------------------------------------------|:------|:------------
45772  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_E_UNMSKED | 0x0 |
45773  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_E_MSKED | 0x1 |
45774  *
45775  * Field Access Macros:
45776  *
45777  */
45778 /*
45779  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2
45780  *
45781  */
45782 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_E_UNMSKED 0x0
45783 /*
45784  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2
45785  *
45786  */
45787 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_E_MSKED 0x1
45788 
45789 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field. */
45790 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_LSB 26
45791 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field. */
45792 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_MSB 26
45793 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field. */
45794 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_WIDTH 1
45795 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field value. */
45796 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_SET_MSK 0x04000000
45797 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field value. */
45798 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_CLR_MSK 0xfbffffff
45799 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field. */
45800 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_RESET 0x0
45801 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 field value from a register. */
45802 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
45803 /* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field value suitable for setting the register. */
45804 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
45805 
45806 /*
45807  * Field : Mask Byte Control - mbc_3
45808  *
45809  * This array of bits are mask control bits for comparison of each of the MAC
45810  * Address bytes. When masked, the MAC does not compare the corresponding byte of
45811  * received DA or SA with the contents of MAC Address31 high and low registers.
45812  * Each bit controls the masking of the bytes. You can filter a group of addresses
45813  * (known as group address filtering) by masking one or more bytes of the address.
45814  *
45815  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
45816  *
45817  * Field Enumeration Values:
45818  *
45819  * Enum | Value | Description
45820  * :----------------------------------------------|:------|:------------
45821  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_E_UNMSKED | 0x0 |
45822  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_E_MSKED | 0x1 |
45823  *
45824  * Field Access Macros:
45825  *
45826  */
45827 /*
45828  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3
45829  *
45830  */
45831 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_E_UNMSKED 0x0
45832 /*
45833  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3
45834  *
45835  */
45836 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_E_MSKED 0x1
45837 
45838 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field. */
45839 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_LSB 27
45840 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field. */
45841 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_MSB 27
45842 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field. */
45843 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_WIDTH 1
45844 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field value. */
45845 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_SET_MSK 0x08000000
45846 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field value. */
45847 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_CLR_MSK 0xf7ffffff
45848 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field. */
45849 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_RESET 0x0
45850 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 field value from a register. */
45851 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
45852 /* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field value suitable for setting the register. */
45853 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
45854 
45855 /*
45856  * Field : Mask Byte Control - mbc_4
45857  *
45858  * This array of bits are mask control bits for comparison of each of the MAC
45859  * Address bytes. When masked, the MAC does not compare the corresponding byte of
45860  * received DA or SA with the contents of MAC Address31 high and low registers.
45861  * Each bit controls the masking of the bytes. You can filter a group of addresses
45862  * (known as group address filtering) by masking one or more bytes of the address.
45863  *
45864  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
45865  *
45866  * Field Enumeration Values:
45867  *
45868  * Enum | Value | Description
45869  * :----------------------------------------------|:------|:------------
45870  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_E_UNMSKED | 0x0 |
45871  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_E_MSKED | 0x1 |
45872  *
45873  * Field Access Macros:
45874  *
45875  */
45876 /*
45877  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4
45878  *
45879  */
45880 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_E_UNMSKED 0x0
45881 /*
45882  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4
45883  *
45884  */
45885 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_E_MSKED 0x1
45886 
45887 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field. */
45888 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_LSB 28
45889 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field. */
45890 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_MSB 28
45891 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field. */
45892 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_WIDTH 1
45893 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field value. */
45894 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_SET_MSK 0x10000000
45895 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field value. */
45896 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_CLR_MSK 0xefffffff
45897 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field. */
45898 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_RESET 0x0
45899 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 field value from a register. */
45900 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
45901 /* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field value suitable for setting the register. */
45902 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
45903 
45904 /*
45905  * Field : Mask Byte Control - mbc_5
45906  *
45907  * This array of bits are mask control bits for comparison of each of the MAC
45908  * Address bytes. When masked, the MAC does not compare the corresponding byte of
45909  * received DA or SA with the contents of MAC Address31 high and low registers.
45910  * Each bit controls the masking of the bytes. You can filter a group of addresses
45911  * (known as group address filtering) by masking one or more bytes of the address.
45912  *
45913  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
45914  *
45915  * Field Enumeration Values:
45916  *
45917  * Enum | Value | Description
45918  * :----------------------------------------------|:------|:------------
45919  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_E_UNMSKED | 0x0 |
45920  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_E_MSKED | 0x1 |
45921  *
45922  * Field Access Macros:
45923  *
45924  */
45925 /*
45926  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5
45927  *
45928  */
45929 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_E_UNMSKED 0x0
45930 /*
45931  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5
45932  *
45933  */
45934 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_E_MSKED 0x1
45935 
45936 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field. */
45937 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_LSB 29
45938 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field. */
45939 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_MSB 29
45940 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field. */
45941 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_WIDTH 1
45942 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field value. */
45943 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_SET_MSK 0x20000000
45944 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field value. */
45945 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_CLR_MSK 0xdfffffff
45946 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field. */
45947 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_RESET 0x0
45948 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 field value from a register. */
45949 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
45950 /* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field value suitable for setting the register. */
45951 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
45952 
45953 /*
45954  * Field : sa
45955  *
45956  * Source Address
45957  *
45958  * When this bit is set, the MAC Address31[47:0] is used to compare with the SA
45959  * fields of the received frame.
45960  *
45961  * When this bit is reset, the MAC Address31[47:0] is used to compare with the DA
45962  * fields of the received frame.
45963  *
45964  * Field Enumeration Values:
45965  *
45966  * Enum | Value | Description
45967  * :----------------------------------------|:------|:------------
45968  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_E_DISD | 0x0 |
45969  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_E_END | 0x1 |
45970  *
45971  * Field Access Macros:
45972  *
45973  */
45974 /*
45975  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA
45976  *
45977  */
45978 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_E_DISD 0x0
45979 /*
45980  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA
45981  *
45982  */
45983 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_E_END 0x1
45984 
45985 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field. */
45986 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_LSB 30
45987 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field. */
45988 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_MSB 30
45989 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field. */
45990 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_WIDTH 1
45991 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field value. */
45992 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_SET_MSK 0x40000000
45993 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field value. */
45994 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_CLR_MSK 0xbfffffff
45995 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field. */
45996 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_RESET 0x0
45997 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA field value from a register. */
45998 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
45999 /* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field value suitable for setting the register. */
46000 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
46001 
46002 /*
46003  * Field : ae
46004  *
46005  * Address Enable
46006  *
46007  * When this bit is set, the address filter module uses the 32nd MAC address for
46008  * perfect filtering.
46009  *
46010  * When this bit is reset, the address filter module ignores the address for
46011  * filtering.
46012  *
46013  * Field Enumeration Values:
46014  *
46015  * Enum | Value | Description
46016  * :----------------------------------------|:------|:------------
46017  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_E_DISD | 0x0 |
46018  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_E_END | 0x1 |
46019  *
46020  * Field Access Macros:
46021  *
46022  */
46023 /*
46024  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE
46025  *
46026  */
46027 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_E_DISD 0x0
46028 /*
46029  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE
46030  *
46031  */
46032 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_E_END 0x1
46033 
46034 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field. */
46035 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_LSB 31
46036 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field. */
46037 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_MSB 31
46038 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field. */
46039 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_WIDTH 1
46040 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field value. */
46041 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_SET_MSK 0x80000000
46042 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field value. */
46043 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_CLR_MSK 0x7fffffff
46044 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field. */
46045 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_RESET 0x0
46046 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE field value from a register. */
46047 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
46048 /* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field value suitable for setting the register. */
46049 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
46050 
46051 #ifndef __ASSEMBLY__
46052 /*
46053  * WARNING: The C register and register group struct declarations are provided for
46054  * convenience and illustrative purposes. They should, however, be used with
46055  * caution as the C language standard provides no guarantees about the alignment or
46056  * atomicity of device memory accesses. The recommended practice for writing
46057  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
46058  * alt_write_word() functions.
46059  *
46060  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR31_HIGH.
46061  */
46062 struct ALT_EMAC_GMAC_MAC_ADDR31_HIGH_s
46063 {
46064  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI */
46065  const uint32_t reserved_23_16 : 8; /* ALT_EMAC_GMAC_MAC_ADDR31_HIGH_RSVD_23_16 */
46066  uint32_t mbc_0 : 1; /* Mask Byte Control */
46067  uint32_t mbc_1 : 1; /* Mask Byte Control */
46068  uint32_t mbc_2 : 1; /* Mask Byte Control */
46069  uint32_t mbc_3 : 1; /* Mask Byte Control */
46070  uint32_t mbc_4 : 1; /* Mask Byte Control */
46071  uint32_t mbc_5 : 1; /* Mask Byte Control */
46072  uint32_t sa : 1; /* ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA */
46073  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE */
46074 };
46075 
46076 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR31_HIGH. */
46077 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR31_HIGH_s ALT_EMAC_GMAC_MAC_ADDR31_HIGH_t;
46078 #endif /* __ASSEMBLY__ */
46079 
46080 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH register. */
46081 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_RESET 0x0000ffff
46082 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH register from the beginning of the component. */
46083 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_OFST 0x878
46084 /* The address of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH register. */
46085 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR31_HIGH_OFST))
46086 
46087 /*
46088  * Register : gmacgrp_mac_address31_low
46089  *
46090  * <b> Register 543 (MAC Address31 Low Register) </b>
46091  *
46092  * The MAC Address31 Low register holds the lower 32 bits of the 32nd 6-byte MAC
46093  * address of the station.
46094  *
46095  * Register Layout
46096  *
46097  * Bits | Access | Reset | Description
46098  * :-------|:-------|:-----------|:------------------------------------
46099  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO
46100  *
46101  */
46102 /*
46103  * Field : addrlo
46104  *
46105  * MAC Address31 [31:0]
46106  *
46107  * This field contains the lower 32 bits of the 32nd 6-byte MAC address. The
46108  * content of this field is undefined until loaded by the Application after the
46109  * initialization process.
46110  *
46111  * Field Access Macros:
46112  *
46113  */
46114 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field. */
46115 #define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_LSB 0
46116 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field. */
46117 #define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_MSB 31
46118 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field. */
46119 #define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_WIDTH 32
46120 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field value. */
46121 #define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_SET_MSK 0xffffffff
46122 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field value. */
46123 #define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_CLR_MSK 0x00000000
46124 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field. */
46125 #define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_RESET 0xffffffff
46126 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO field value from a register. */
46127 #define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
46128 /* Produces a ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field value suitable for setting the register. */
46129 #define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
46130 
46131 #ifndef __ASSEMBLY__
46132 /*
46133  * WARNING: The C register and register group struct declarations are provided for
46134  * convenience and illustrative purposes. They should, however, be used with
46135  * caution as the C language standard provides no guarantees about the alignment or
46136  * atomicity of device memory accesses. The recommended practice for writing
46137  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
46138  * alt_write_word() functions.
46139  *
46140  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR31_LOW.
46141  */
46142 struct ALT_EMAC_GMAC_MAC_ADDR31_LOW_s
46143 {
46144  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO */
46145 };
46146 
46147 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR31_LOW. */
46148 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR31_LOW_s ALT_EMAC_GMAC_MAC_ADDR31_LOW_t;
46149 #endif /* __ASSEMBLY__ */
46150 
46151 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_LOW register. */
46152 #define ALT_EMAC_GMAC_MAC_ADDR31_LOW_RESET 0xffffffff
46153 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR31_LOW register from the beginning of the component. */
46154 #define ALT_EMAC_GMAC_MAC_ADDR31_LOW_OFST 0x87c
46155 /* The address of the ALT_EMAC_GMAC_MAC_ADDR31_LOW register. */
46156 #define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR31_LOW_OFST))
46157 
46158 /*
46159  * Register : gmacgrp_mac_address32_high
46160  *
46161  * <b> Register 544 (MAC Address32 High Register) </b>
46162  *
46163  * The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC
46164  * address of the station.
46165  *
46166  * If the MAC address registers are configured to be double-synchronized to the
46167  * (G)MII clock domains, then
46168  *
46169  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
46170  * or Bits[7:0] (in big-endian mode) of the MAC Address32 Low Register are written.
46171  * For proper synchronization updates, consecutive writes to this MAC Address32 Low
46172  * Register must be performed after at least four clock cycles in the destination
46173  * clock domain.
46174  *
46175  * Register Layout
46176  *
46177  * Bits | Access | Reset | Description
46178  * :--------|:-------|:-------|:-----------------------------------------
46179  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI
46180  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR32_HIGH_RSVD_30_16
46181  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE
46182  *
46183  */
46184 /*
46185  * Field : addrhi
46186  *
46187  * MAC Address32 [47:32]
46188  *
46189  * This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address.
46190  *
46191  * Field Access Macros:
46192  *
46193  */
46194 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field. */
46195 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_LSB 0
46196 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field. */
46197 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_MSB 15
46198 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field. */
46199 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_WIDTH 16
46200 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field value. */
46201 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_SET_MSK 0x0000ffff
46202 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field value. */
46203 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_CLR_MSK 0xffff0000
46204 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field. */
46205 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_RESET 0xffff
46206 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI field value from a register. */
46207 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
46208 /* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field value suitable for setting the register. */
46209 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
46210 
46211 /*
46212  * Field : reserved_30_16
46213  *
46214  * Reserved
46215  *
46216  * Field Access Macros:
46217  *
46218  */
46219 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_RSVD_30_16 register field. */
46220 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_RSVD_30_16_LSB 16
46221 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_RSVD_30_16 register field. */
46222 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_RSVD_30_16_MSB 30
46223 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_RSVD_30_16 register field. */
46224 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_RSVD_30_16_WIDTH 15
46225 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_RSVD_30_16 register field value. */
46226 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
46227 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_RSVD_30_16 register field value. */
46228 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
46229 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_RSVD_30_16 register field. */
46230 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_RSVD_30_16_RESET 0x0
46231 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_RSVD_30_16 field value from a register. */
46232 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
46233 /* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_RSVD_30_16 register field value suitable for setting the register. */
46234 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
46235 
46236 /*
46237  * Field : ae
46238  *
46239  * Address Enable
46240  *
46241  * When this bit is set, the address filter module uses the 33rd MAC address for
46242  * perfect filtering.
46243  *
46244  * When this bit is reset, the address filter module ignores the address for
46245  * filtering.
46246  *
46247  * Field Enumeration Values:
46248  *
46249  * Enum | Value | Description
46250  * :----------------------------------------|:------|:------------
46251  * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_E_DISD | 0x0 |
46252  * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_E_END | 0x1 |
46253  *
46254  * Field Access Macros:
46255  *
46256  */
46257 /*
46258  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE
46259  *
46260  */
46261 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_E_DISD 0x0
46262 /*
46263  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE
46264  *
46265  */
46266 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_E_END 0x1
46267 
46268 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field. */
46269 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_LSB 31
46270 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field. */
46271 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_MSB 31
46272 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field. */
46273 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_WIDTH 1
46274 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field value. */
46275 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_SET_MSK 0x80000000
46276 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field value. */
46277 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_CLR_MSK 0x7fffffff
46278 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field. */
46279 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_RESET 0x0
46280 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE field value from a register. */
46281 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
46282 /* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field value suitable for setting the register. */
46283 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
46284 
46285 #ifndef __ASSEMBLY__
46286 /*
46287  * WARNING: The C register and register group struct declarations are provided for
46288  * convenience and illustrative purposes. They should, however, be used with
46289  * caution as the C language standard provides no guarantees about the alignment or
46290  * atomicity of device memory accesses. The recommended practice for writing
46291  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
46292  * alt_write_word() functions.
46293  *
46294  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR32_HIGH.
46295  */
46296 struct ALT_EMAC_GMAC_MAC_ADDR32_HIGH_s
46297 {
46298  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI */
46299  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR32_HIGH_RSVD_30_16 */
46300  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE */
46301 };
46302 
46303 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR32_HIGH. */
46304 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR32_HIGH_s ALT_EMAC_GMAC_MAC_ADDR32_HIGH_t;
46305 #endif /* __ASSEMBLY__ */
46306 
46307 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH register. */
46308 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_RESET 0x0000ffff
46309 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH register from the beginning of the component. */
46310 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_OFST 0x880
46311 /* The address of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH register. */
46312 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR32_HIGH_OFST))
46313 
46314 /*
46315  * Register : gmacgrp_mac_address32_low
46316  *
46317  * <b> Register 545 (MAC Address32 Low Register) </b>
46318  *
46319  * The MAC Address32 Low register holds the lower 32 bits of the 33rd 6-byte MAC
46320  * address of the station.
46321  *
46322  * Register Layout
46323  *
46324  * Bits | Access | Reset | Description
46325  * :-------|:-------|:-----------|:------------------------------------
46326  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO
46327  *
46328  */
46329 /*
46330  * Field : addrlo
46331  *
46332  * MAC Address32 [31:0]
46333  *
46334  * This field contains the lower 32 bits of the 33rd 6-byte MAC address. The
46335  * content of this field is undefined until loaded by the Application after the
46336  * initialization process.
46337  *
46338  * Field Access Macros:
46339  *
46340  */
46341 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field. */
46342 #define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_LSB 0
46343 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field. */
46344 #define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_MSB 31
46345 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field. */
46346 #define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_WIDTH 32
46347 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field value. */
46348 #define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_SET_MSK 0xffffffff
46349 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field value. */
46350 #define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_CLR_MSK 0x00000000
46351 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field. */
46352 #define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_RESET 0xffffffff
46353 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO field value from a register. */
46354 #define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
46355 /* Produces a ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field value suitable for setting the register. */
46356 #define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
46357 
46358 #ifndef __ASSEMBLY__
46359 /*
46360  * WARNING: The C register and register group struct declarations are provided for
46361  * convenience and illustrative purposes. They should, however, be used with
46362  * caution as the C language standard provides no guarantees about the alignment or
46363  * atomicity of device memory accesses. The recommended practice for writing
46364  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
46365  * alt_write_word() functions.
46366  *
46367  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR32_LOW.
46368  */
46369 struct ALT_EMAC_GMAC_MAC_ADDR32_LOW_s
46370 {
46371  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO */
46372 };
46373 
46374 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR32_LOW. */
46375 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR32_LOW_s ALT_EMAC_GMAC_MAC_ADDR32_LOW_t;
46376 #endif /* __ASSEMBLY__ */
46377 
46378 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_LOW register. */
46379 #define ALT_EMAC_GMAC_MAC_ADDR32_LOW_RESET 0xffffffff
46380 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR32_LOW register from the beginning of the component. */
46381 #define ALT_EMAC_GMAC_MAC_ADDR32_LOW_OFST 0x884
46382 /* The address of the ALT_EMAC_GMAC_MAC_ADDR32_LOW register. */
46383 #define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR32_LOW_OFST))
46384 
46385 /*
46386  * Register : gmacgrp_mac_address33_high
46387  *
46388  * <b> Register 546 (MAC Address33 High Register) </b>
46389  *
46390  * The MAC Address33 High register holds the upper 16 bits of the 34th 6-byte MAC
46391  * address of the station.
46392  *
46393  * If the MAC address registers are configured to be double-synchronized to the
46394  * (G)MII clock domains, then
46395  *
46396  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
46397  * or Bits[7:0] (in big-endian mode) of the MAC Address33 Low Register are written.
46398  * For proper synchronization updates, consecutive writes to this MAC Address33 Low
46399  * Register must be performed after at least four clock cycles in the destination
46400  * clock domain.
46401  *
46402  * Register Layout
46403  *
46404  * Bits | Access | Reset | Description
46405  * :--------|:-------|:-------|:-----------------------------------------
46406  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI
46407  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR33_HIGH_RSVD_30_16
46408  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE
46409  *
46410  */
46411 /*
46412  * Field : addrhi
46413  *
46414  * MAC Address33 [47:32]
46415  *
46416  * This field contains the upper 16 bits (47:32) of the 34th 6-byte MAC address.
46417  *
46418  * Field Access Macros:
46419  *
46420  */
46421 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field. */
46422 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_LSB 0
46423 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field. */
46424 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_MSB 15
46425 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field. */
46426 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_WIDTH 16
46427 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field value. */
46428 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_SET_MSK 0x0000ffff
46429 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field value. */
46430 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_CLR_MSK 0xffff0000
46431 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field. */
46432 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_RESET 0xffff
46433 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI field value from a register. */
46434 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
46435 /* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field value suitable for setting the register. */
46436 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
46437 
46438 /*
46439  * Field : reserved_30_16
46440  *
46441  * Reserved
46442  *
46443  * Field Access Macros:
46444  *
46445  */
46446 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_RSVD_30_16 register field. */
46447 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_RSVD_30_16_LSB 16
46448 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_RSVD_30_16 register field. */
46449 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_RSVD_30_16_MSB 30
46450 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_RSVD_30_16 register field. */
46451 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_RSVD_30_16_WIDTH 15
46452 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_RSVD_30_16 register field value. */
46453 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
46454 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_RSVD_30_16 register field value. */
46455 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
46456 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_RSVD_30_16 register field. */
46457 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_RSVD_30_16_RESET 0x0
46458 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_RSVD_30_16 field value from a register. */
46459 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
46460 /* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_RSVD_30_16 register field value suitable for setting the register. */
46461 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
46462 
46463 /*
46464  * Field : ae
46465  *
46466  * Address Enable
46467  *
46468  * When this bit is set, the address filter module uses the 34th MAC address for
46469  * perfect filtering.
46470  *
46471  * When this bit is reset, the address filter module ignores the address for
46472  * filtering.
46473  *
46474  * Field Enumeration Values:
46475  *
46476  * Enum | Value | Description
46477  * :----------------------------------------|:------|:------------
46478  * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_E_DISD | 0x0 |
46479  * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_E_END | 0x1 |
46480  *
46481  * Field Access Macros:
46482  *
46483  */
46484 /*
46485  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE
46486  *
46487  */
46488 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_E_DISD 0x0
46489 /*
46490  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE
46491  *
46492  */
46493 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_E_END 0x1
46494 
46495 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field. */
46496 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_LSB 31
46497 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field. */
46498 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_MSB 31
46499 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field. */
46500 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_WIDTH 1
46501 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field value. */
46502 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_SET_MSK 0x80000000
46503 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field value. */
46504 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_CLR_MSK 0x7fffffff
46505 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field. */
46506 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_RESET 0x0
46507 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE field value from a register. */
46508 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
46509 /* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field value suitable for setting the register. */
46510 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
46511 
46512 #ifndef __ASSEMBLY__
46513 /*
46514  * WARNING: The C register and register group struct declarations are provided for
46515  * convenience and illustrative purposes. They should, however, be used with
46516  * caution as the C language standard provides no guarantees about the alignment or
46517  * atomicity of device memory accesses. The recommended practice for writing
46518  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
46519  * alt_write_word() functions.
46520  *
46521  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR33_HIGH.
46522  */
46523 struct ALT_EMAC_GMAC_MAC_ADDR33_HIGH_s
46524 {
46525  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI */
46526  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR33_HIGH_RSVD_30_16 */
46527  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE */
46528 };
46529 
46530 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR33_HIGH. */
46531 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR33_HIGH_s ALT_EMAC_GMAC_MAC_ADDR33_HIGH_t;
46532 #endif /* __ASSEMBLY__ */
46533 
46534 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH register. */
46535 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_RESET 0x0000ffff
46536 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH register from the beginning of the component. */
46537 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_OFST 0x888
46538 /* The address of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH register. */
46539 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR33_HIGH_OFST))
46540 
46541 /*
46542  * Register : gmacgrp_mac_address33_low
46543  *
46544  * <b> Register 547 (MAC Address33 Low Register) </b>
46545  *
46546  * The MAC Address33 Low register holds the lower 32 bits of the 34th 6-byte MAC
46547  * address of the station.
46548  *
46549  * Register Layout
46550  *
46551  * Bits | Access | Reset | Description
46552  * :-------|:-------|:-----------|:------------------------------------
46553  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO
46554  *
46555  */
46556 /*
46557  * Field : addrlo
46558  *
46559  * MAC Address33 [31:0]
46560  *
46561  * This field contains the lower 32 bits of the 34th 6-byte MAC address. The
46562  * content of this field is undefined until loaded by the Application after the
46563  * initialization process.
46564  *
46565  * Field Access Macros:
46566  *
46567  */
46568 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field. */
46569 #define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_LSB 0
46570 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field. */
46571 #define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_MSB 31
46572 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field. */
46573 #define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_WIDTH 32
46574 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field value. */
46575 #define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_SET_MSK 0xffffffff
46576 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field value. */
46577 #define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_CLR_MSK 0x00000000
46578 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field. */
46579 #define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_RESET 0xffffffff
46580 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO field value from a register. */
46581 #define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
46582 /* Produces a ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field value suitable for setting the register. */
46583 #define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
46584 
46585 #ifndef __ASSEMBLY__
46586 /*
46587  * WARNING: The C register and register group struct declarations are provided for
46588  * convenience and illustrative purposes. They should, however, be used with
46589  * caution as the C language standard provides no guarantees about the alignment or
46590  * atomicity of device memory accesses. The recommended practice for writing
46591  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
46592  * alt_write_word() functions.
46593  *
46594  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR33_LOW.
46595  */
46596 struct ALT_EMAC_GMAC_MAC_ADDR33_LOW_s
46597 {
46598  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO */
46599 };
46600 
46601 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR33_LOW. */
46602 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR33_LOW_s ALT_EMAC_GMAC_MAC_ADDR33_LOW_t;
46603 #endif /* __ASSEMBLY__ */
46604 
46605 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_LOW register. */
46606 #define ALT_EMAC_GMAC_MAC_ADDR33_LOW_RESET 0xffffffff
46607 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR33_LOW register from the beginning of the component. */
46608 #define ALT_EMAC_GMAC_MAC_ADDR33_LOW_OFST 0x88c
46609 /* The address of the ALT_EMAC_GMAC_MAC_ADDR33_LOW register. */
46610 #define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR33_LOW_OFST))
46611 
46612 /*
46613  * Register : gmacgrp_mac_address34_high
46614  *
46615  * <b> Register 548 (MAC Address34 High Register) </b>
46616  *
46617  * The MAC Address34 High register holds the upper 16 bits of the 35th 6-byte MAC
46618  * address of the station.
46619  *
46620  * If the MAC address registers are configured to be double-synchronized to the
46621  * (G)MII clock domains, then
46622  *
46623  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
46624  * or Bits[7:0] (in big-endian mode) of the MAC Address34 Low Register are written.
46625  * For proper synchronization updates, consecutive writes to this MAC Address34 Low
46626  * Register must be performed after at least four clock cycles in the destination
46627  * clock domain.
46628  *
46629  * Register Layout
46630  *
46631  * Bits | Access | Reset | Description
46632  * :--------|:-------|:-------|:-----------------------------------------
46633  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI
46634  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR34_HIGH_RSVD_30_16
46635  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE
46636  *
46637  */
46638 /*
46639  * Field : addrhi
46640  *
46641  * MAC Address34 [47:32]
46642  *
46643  * This field contains the upper 16 bits (47:32) of the 35th 6-byte MAC address.
46644  *
46645  * Field Access Macros:
46646  *
46647  */
46648 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field. */
46649 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_LSB 0
46650 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field. */
46651 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_MSB 15
46652 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field. */
46653 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_WIDTH 16
46654 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field value. */
46655 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_SET_MSK 0x0000ffff
46656 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field value. */
46657 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_CLR_MSK 0xffff0000
46658 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field. */
46659 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_RESET 0xffff
46660 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI field value from a register. */
46661 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
46662 /* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field value suitable for setting the register. */
46663 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
46664 
46665 /*
46666  * Field : reserved_30_16
46667  *
46668  * Reserved
46669  *
46670  * Field Access Macros:
46671  *
46672  */
46673 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_RSVD_30_16 register field. */
46674 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_RSVD_30_16_LSB 16
46675 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_RSVD_30_16 register field. */
46676 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_RSVD_30_16_MSB 30
46677 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_RSVD_30_16 register field. */
46678 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_RSVD_30_16_WIDTH 15
46679 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_RSVD_30_16 register field value. */
46680 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
46681 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_RSVD_30_16 register field value. */
46682 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
46683 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_RSVD_30_16 register field. */
46684 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_RSVD_30_16_RESET 0x0
46685 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_RSVD_30_16 field value from a register. */
46686 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
46687 /* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_RSVD_30_16 register field value suitable for setting the register. */
46688 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
46689 
46690 /*
46691  * Field : ae
46692  *
46693  * Address Enable
46694  *
46695  * When this bit is set, the address filter module uses the 35th MAC address for
46696  * perfect filtering.
46697  *
46698  * When this bit is reset, the address filter module ignores the address for
46699  * filtering.
46700  *
46701  * Field Enumeration Values:
46702  *
46703  * Enum | Value | Description
46704  * :----------------------------------------|:------|:------------
46705  * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_E_DISD | 0x0 |
46706  * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_E_END | 0x1 |
46707  *
46708  * Field Access Macros:
46709  *
46710  */
46711 /*
46712  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE
46713  *
46714  */
46715 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_E_DISD 0x0
46716 /*
46717  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE
46718  *
46719  */
46720 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_E_END 0x1
46721 
46722 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field. */
46723 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_LSB 31
46724 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field. */
46725 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_MSB 31
46726 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field. */
46727 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_WIDTH 1
46728 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field value. */
46729 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_SET_MSK 0x80000000
46730 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field value. */
46731 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_CLR_MSK 0x7fffffff
46732 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field. */
46733 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_RESET 0x0
46734 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE field value from a register. */
46735 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
46736 /* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field value suitable for setting the register. */
46737 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
46738 
46739 #ifndef __ASSEMBLY__
46740 /*
46741  * WARNING: The C register and register group struct declarations are provided for
46742  * convenience and illustrative purposes. They should, however, be used with
46743  * caution as the C language standard provides no guarantees about the alignment or
46744  * atomicity of device memory accesses. The recommended practice for writing
46745  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
46746  * alt_write_word() functions.
46747  *
46748  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR34_HIGH.
46749  */
46750 struct ALT_EMAC_GMAC_MAC_ADDR34_HIGH_s
46751 {
46752  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI */
46753  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR34_HIGH_RSVD_30_16 */
46754  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE */
46755 };
46756 
46757 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR34_HIGH. */
46758 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR34_HIGH_s ALT_EMAC_GMAC_MAC_ADDR34_HIGH_t;
46759 #endif /* __ASSEMBLY__ */
46760 
46761 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH register. */
46762 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_RESET 0x0000ffff
46763 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH register from the beginning of the component. */
46764 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_OFST 0x890
46765 /* The address of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH register. */
46766 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR34_HIGH_OFST))
46767 
46768 /*
46769  * Register : gmacgrp_mac_address34_low
46770  *
46771  * <b> Register 549 (MAC Address34 Low Register) </b>
46772  *
46773  * The MAC Address34 Low register holds the lower 32 bits of the 35th 6-byte MAC
46774  * address of the station.
46775  *
46776  * Register Layout
46777  *
46778  * Bits | Access | Reset | Description
46779  * :-------|:-------|:-----------|:------------------------------------
46780  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO
46781  *
46782  */
46783 /*
46784  * Field : addrlo
46785  *
46786  * MAC Address34 [31:0]
46787  *
46788  * This field contains the lower 32 bits of the 35th 6-byte MAC address. The
46789  * content of this field is undefined until loaded by the Application after the
46790  * initialization process.
46791  *
46792  * Field Access Macros:
46793  *
46794  */
46795 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field. */
46796 #define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_LSB 0
46797 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field. */
46798 #define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_MSB 31
46799 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field. */
46800 #define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_WIDTH 32
46801 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field value. */
46802 #define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_SET_MSK 0xffffffff
46803 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field value. */
46804 #define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_CLR_MSK 0x00000000
46805 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field. */
46806 #define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_RESET 0xffffffff
46807 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO field value from a register. */
46808 #define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
46809 /* Produces a ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field value suitable for setting the register. */
46810 #define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
46811 
46812 #ifndef __ASSEMBLY__
46813 /*
46814  * WARNING: The C register and register group struct declarations are provided for
46815  * convenience and illustrative purposes. They should, however, be used with
46816  * caution as the C language standard provides no guarantees about the alignment or
46817  * atomicity of device memory accesses. The recommended practice for writing
46818  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
46819  * alt_write_word() functions.
46820  *
46821  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR34_LOW.
46822  */
46823 struct ALT_EMAC_GMAC_MAC_ADDR34_LOW_s
46824 {
46825  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO */
46826 };
46827 
46828 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR34_LOW. */
46829 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR34_LOW_s ALT_EMAC_GMAC_MAC_ADDR34_LOW_t;
46830 #endif /* __ASSEMBLY__ */
46831 
46832 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_LOW register. */
46833 #define ALT_EMAC_GMAC_MAC_ADDR34_LOW_RESET 0xffffffff
46834 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR34_LOW register from the beginning of the component. */
46835 #define ALT_EMAC_GMAC_MAC_ADDR34_LOW_OFST 0x894
46836 /* The address of the ALT_EMAC_GMAC_MAC_ADDR34_LOW register. */
46837 #define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR34_LOW_OFST))
46838 
46839 /*
46840  * Register : gmacgrp_mac_address35_high
46841  *
46842  * <b> Register 550 (MAC Address35 High Register) </b>
46843  *
46844  * The MAC Address35 High register holds the upper 16 bits of the 36th 6-byte MAC
46845  * address of the station.
46846  *
46847  * If the MAC address registers are configured to be double-synchronized to the
46848  * (G)MII clock domains, then
46849  *
46850  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
46851  * or Bits[7:0] (in big-endian mode) of the MAC Address35 Low Register are written.
46852  * For proper synchronization updates, consecutive writes to this MAC Address35 Low
46853  * Register must be performed after at least four clock cycles in the destination
46854  * clock domain.
46855  *
46856  * Register Layout
46857  *
46858  * Bits | Access | Reset | Description
46859  * :--------|:-------|:-------|:-----------------------------------------
46860  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI
46861  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR35_HIGH_RSVD_30_16
46862  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE
46863  *
46864  */
46865 /*
46866  * Field : addrhi
46867  *
46868  * MAC Address35 [47:32]
46869  *
46870  * This field contains the upper 16 bits (47:32) of the 36th 6-byte MAC address.
46871  *
46872  * Field Access Macros:
46873  *
46874  */
46875 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field. */
46876 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_LSB 0
46877 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field. */
46878 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_MSB 15
46879 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field. */
46880 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_WIDTH 16
46881 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field value. */
46882 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_SET_MSK 0x0000ffff
46883 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field value. */
46884 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_CLR_MSK 0xffff0000
46885 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field. */
46886 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_RESET 0xffff
46887 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI field value from a register. */
46888 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
46889 /* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field value suitable for setting the register. */
46890 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
46891 
46892 /*
46893  * Field : reserved_30_16
46894  *
46895  * Reserved
46896  *
46897  * Field Access Macros:
46898  *
46899  */
46900 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_RSVD_30_16 register field. */
46901 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_RSVD_30_16_LSB 16
46902 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_RSVD_30_16 register field. */
46903 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_RSVD_30_16_MSB 30
46904 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_RSVD_30_16 register field. */
46905 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_RSVD_30_16_WIDTH 15
46906 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_RSVD_30_16 register field value. */
46907 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
46908 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_RSVD_30_16 register field value. */
46909 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
46910 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_RSVD_30_16 register field. */
46911 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_RSVD_30_16_RESET 0x0
46912 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_RSVD_30_16 field value from a register. */
46913 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
46914 /* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_RSVD_30_16 register field value suitable for setting the register. */
46915 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
46916 
46917 /*
46918  * Field : ae
46919  *
46920  * Address Enable
46921  *
46922  * When this bit is set, the address filter module uses the 36th MAC address for
46923  * perfect filtering. When this bit is reset, the address filter module ignores the
46924  * address for filtering.
46925  *
46926  * Field Enumeration Values:
46927  *
46928  * Enum | Value | Description
46929  * :----------------------------------------|:------|:------------
46930  * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_E_DISD | 0x0 |
46931  * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_E_END | 0x1 |
46932  *
46933  * Field Access Macros:
46934  *
46935  */
46936 /*
46937  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE
46938  *
46939  */
46940 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_E_DISD 0x0
46941 /*
46942  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE
46943  *
46944  */
46945 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_E_END 0x1
46946 
46947 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field. */
46948 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_LSB 31
46949 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field. */
46950 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_MSB 31
46951 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field. */
46952 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_WIDTH 1
46953 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field value. */
46954 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_SET_MSK 0x80000000
46955 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field value. */
46956 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_CLR_MSK 0x7fffffff
46957 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field. */
46958 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_RESET 0x0
46959 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE field value from a register. */
46960 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
46961 /* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field value suitable for setting the register. */
46962 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
46963 
46964 #ifndef __ASSEMBLY__
46965 /*
46966  * WARNING: The C register and register group struct declarations are provided for
46967  * convenience and illustrative purposes. They should, however, be used with
46968  * caution as the C language standard provides no guarantees about the alignment or
46969  * atomicity of device memory accesses. The recommended practice for writing
46970  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
46971  * alt_write_word() functions.
46972  *
46973  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR35_HIGH.
46974  */
46975 struct ALT_EMAC_GMAC_MAC_ADDR35_HIGH_s
46976 {
46977  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI */
46978  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR35_HIGH_RSVD_30_16 */
46979  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE */
46980 };
46981 
46982 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR35_HIGH. */
46983 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR35_HIGH_s ALT_EMAC_GMAC_MAC_ADDR35_HIGH_t;
46984 #endif /* __ASSEMBLY__ */
46985 
46986 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH register. */
46987 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_RESET 0x0000ffff
46988 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH register from the beginning of the component. */
46989 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_OFST 0x898
46990 /* The address of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH register. */
46991 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR35_HIGH_OFST))
46992 
46993 /*
46994  * Register : gmacgrp_mac_address35_low
46995  *
46996  * <b> Register 551 (MAC Address35 Low Register) </b>
46997  *
46998  * The MAC Address35 Low register holds the lower 32 bits of the 36th 6-byte MAC
46999  * address of the station.
47000  *
47001  * Register Layout
47002  *
47003  * Bits | Access | Reset | Description
47004  * :-------|:-------|:-----------|:------------------------------------
47005  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO
47006  *
47007  */
47008 /*
47009  * Field : addrlo
47010  *
47011  * MAC Address35 [31:0]
47012  *
47013  * This field contains the lower 32 bits of the 36th 6-byte MAC address. The
47014  * content of this field is undefined until loaded by the Application after the
47015  * initialization process.
47016  *
47017  * Field Access Macros:
47018  *
47019  */
47020 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field. */
47021 #define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_LSB 0
47022 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field. */
47023 #define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_MSB 31
47024 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field. */
47025 #define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_WIDTH 32
47026 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field value. */
47027 #define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_SET_MSK 0xffffffff
47028 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field value. */
47029 #define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_CLR_MSK 0x00000000
47030 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field. */
47031 #define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_RESET 0xffffffff
47032 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO field value from a register. */
47033 #define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
47034 /* Produces a ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field value suitable for setting the register. */
47035 #define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
47036 
47037 #ifndef __ASSEMBLY__
47038 /*
47039  * WARNING: The C register and register group struct declarations are provided for
47040  * convenience and illustrative purposes. They should, however, be used with
47041  * caution as the C language standard provides no guarantees about the alignment or
47042  * atomicity of device memory accesses. The recommended practice for writing
47043  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
47044  * alt_write_word() functions.
47045  *
47046  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR35_LOW.
47047  */
47048 struct ALT_EMAC_GMAC_MAC_ADDR35_LOW_s
47049 {
47050  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO */
47051 };
47052 
47053 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR35_LOW. */
47054 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR35_LOW_s ALT_EMAC_GMAC_MAC_ADDR35_LOW_t;
47055 #endif /* __ASSEMBLY__ */
47056 
47057 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_LOW register. */
47058 #define ALT_EMAC_GMAC_MAC_ADDR35_LOW_RESET 0xffffffff
47059 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR35_LOW register from the beginning of the component. */
47060 #define ALT_EMAC_GMAC_MAC_ADDR35_LOW_OFST 0x89c
47061 /* The address of the ALT_EMAC_GMAC_MAC_ADDR35_LOW register. */
47062 #define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR35_LOW_OFST))
47063 
47064 /*
47065  * Register : gmacgrp_mac_address36_high
47066  *
47067  * <b> Register 552 (MAC Address36 High Register) </b>
47068  *
47069  * The MAC Address36 High register holds the upper 16 bits of the 37th 6-byte MAC
47070  * address of the station.
47071  *
47072  * If the MAC address registers are configured to be double-synchronized to the
47073  * (G)MII clock domains, then
47074  *
47075  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
47076  * or Bits[7:0] (in big-endian mode) of the MAC Address36 Low Register are written.
47077  * For proper synchronization updates, consecutive writes to this MAC Address36 Low
47078  * Register must be performed after at least four clock cycles in the destination
47079  * clock domain.
47080  *
47081  * Register Layout
47082  *
47083  * Bits | Access | Reset | Description
47084  * :--------|:-------|:-------|:-----------------------------------------
47085  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI
47086  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR36_HIGH_RSVD_30_16
47087  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE
47088  *
47089  */
47090 /*
47091  * Field : addrhi
47092  *
47093  * MAC Address36 [47:32]
47094  *
47095  * This field contains the upper 16 bits (47:32) of the 37th 6-byte MAC address.
47096  *
47097  * Field Access Macros:
47098  *
47099  */
47100 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field. */
47101 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_LSB 0
47102 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field. */
47103 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_MSB 15
47104 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field. */
47105 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_WIDTH 16
47106 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field value. */
47107 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_SET_MSK 0x0000ffff
47108 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field value. */
47109 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_CLR_MSK 0xffff0000
47110 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field. */
47111 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_RESET 0xffff
47112 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI field value from a register. */
47113 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
47114 /* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field value suitable for setting the register. */
47115 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
47116 
47117 /*
47118  * Field : reserved_30_16
47119  *
47120  * Reserved
47121  *
47122  * Field Access Macros:
47123  *
47124  */
47125 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_RSVD_30_16 register field. */
47126 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_RSVD_30_16_LSB 16
47127 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_RSVD_30_16 register field. */
47128 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_RSVD_30_16_MSB 30
47129 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_RSVD_30_16 register field. */
47130 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_RSVD_30_16_WIDTH 15
47131 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_RSVD_30_16 register field value. */
47132 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
47133 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_RSVD_30_16 register field value. */
47134 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
47135 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_RSVD_30_16 register field. */
47136 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_RSVD_30_16_RESET 0x0
47137 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_RSVD_30_16 field value from a register. */
47138 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
47139 /* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_RSVD_30_16 register field value suitable for setting the register. */
47140 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
47141 
47142 /*
47143  * Field : ae
47144  *
47145  * Address Enable
47146  *
47147  * When this bit is set, the address filter module uses the 37th MAC address for
47148  * perfect filtering.
47149  *
47150  * When this bit is reset, the address filter module ignores the address for
47151  * filtering.
47152  *
47153  * Field Enumeration Values:
47154  *
47155  * Enum | Value | Description
47156  * :----------------------------------------|:------|:------------
47157  * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_E_DISD | 0x0 |
47158  * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_E_END | 0x1 |
47159  *
47160  * Field Access Macros:
47161  *
47162  */
47163 /*
47164  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE
47165  *
47166  */
47167 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_E_DISD 0x0
47168 /*
47169  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE
47170  *
47171  */
47172 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_E_END 0x1
47173 
47174 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field. */
47175 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_LSB 31
47176 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field. */
47177 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_MSB 31
47178 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field. */
47179 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_WIDTH 1
47180 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field value. */
47181 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_SET_MSK 0x80000000
47182 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field value. */
47183 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_CLR_MSK 0x7fffffff
47184 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field. */
47185 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_RESET 0x0
47186 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE field value from a register. */
47187 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
47188 /* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field value suitable for setting the register. */
47189 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
47190 
47191 #ifndef __ASSEMBLY__
47192 /*
47193  * WARNING: The C register and register group struct declarations are provided for
47194  * convenience and illustrative purposes. They should, however, be used with
47195  * caution as the C language standard provides no guarantees about the alignment or
47196  * atomicity of device memory accesses. The recommended practice for writing
47197  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
47198  * alt_write_word() functions.
47199  *
47200  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR36_HIGH.
47201  */
47202 struct ALT_EMAC_GMAC_MAC_ADDR36_HIGH_s
47203 {
47204  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI */
47205  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR36_HIGH_RSVD_30_16 */
47206  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE */
47207 };
47208 
47209 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR36_HIGH. */
47210 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR36_HIGH_s ALT_EMAC_GMAC_MAC_ADDR36_HIGH_t;
47211 #endif /* __ASSEMBLY__ */
47212 
47213 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH register. */
47214 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_RESET 0x0000ffff
47215 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH register from the beginning of the component. */
47216 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_OFST 0x8a0
47217 /* The address of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH register. */
47218 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR36_HIGH_OFST))
47219 
47220 /*
47221  * Register : gmacgrp_mac_address36_low
47222  *
47223  * <b> Register 553 (MAC Address36 Low Register) </b>
47224  *
47225  * The MAC Address36 Low register holds the lower 32 bits of the 34th 6-byte MAC
47226  * address of the station.
47227  *
47228  * Register Layout
47229  *
47230  * Bits | Access | Reset | Description
47231  * :-------|:-------|:-----------|:------------------------------------
47232  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO
47233  *
47234  */
47235 /*
47236  * Field : addrlo
47237  *
47238  * MAC Address36 [31:0]
47239  *
47240  * This field contains the lower 32 bits of the 37th 6-byte MAC address. The
47241  * content of this field is undefined until loaded by the Application after the
47242  * initialization process.
47243  *
47244  * Field Access Macros:
47245  *
47246  */
47247 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field. */
47248 #define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_LSB 0
47249 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field. */
47250 #define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_MSB 31
47251 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field. */
47252 #define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_WIDTH 32
47253 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field value. */
47254 #define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_SET_MSK 0xffffffff
47255 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field value. */
47256 #define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_CLR_MSK 0x00000000
47257 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field. */
47258 #define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_RESET 0xffffffff
47259 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO field value from a register. */
47260 #define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
47261 /* Produces a ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field value suitable for setting the register. */
47262 #define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
47263 
47264 #ifndef __ASSEMBLY__
47265 /*
47266  * WARNING: The C register and register group struct declarations are provided for
47267  * convenience and illustrative purposes. They should, however, be used with
47268  * caution as the C language standard provides no guarantees about the alignment or
47269  * atomicity of device memory accesses. The recommended practice for writing
47270  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
47271  * alt_write_word() functions.
47272  *
47273  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR36_LOW.
47274  */
47275 struct ALT_EMAC_GMAC_MAC_ADDR36_LOW_s
47276 {
47277  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO */
47278 };
47279 
47280 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR36_LOW. */
47281 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR36_LOW_s ALT_EMAC_GMAC_MAC_ADDR36_LOW_t;
47282 #endif /* __ASSEMBLY__ */
47283 
47284 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_LOW register. */
47285 #define ALT_EMAC_GMAC_MAC_ADDR36_LOW_RESET 0xffffffff
47286 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR36_LOW register from the beginning of the component. */
47287 #define ALT_EMAC_GMAC_MAC_ADDR36_LOW_OFST 0x8a4
47288 /* The address of the ALT_EMAC_GMAC_MAC_ADDR36_LOW register. */
47289 #define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR36_LOW_OFST))
47290 
47291 /*
47292  * Register : gmacgrp_mac_address37_high
47293  *
47294  * <b> Register 554 (MAC Address37 High Register) </b>
47295  *
47296  * The MAC Address37 High register holds the upper 16 bits of the 38th 6-byte MAC
47297  * address of the station.
47298  *
47299  * If the MAC address registers are configured to be double-synchronized to the
47300  * (G)MII clock domains, then
47301  *
47302  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
47303  * or Bits[7:0] (in big-endian mode) of the MAC Address37 Low Register are written.
47304  * For proper synchronization updates, consecutive writes to this MAC Address37 Low
47305  * Register must be performed after at least four clock cycles in the destination
47306  * clock domain.
47307  *
47308  * Register Layout
47309  *
47310  * Bits | Access | Reset | Description
47311  * :--------|:-------|:-------|:-----------------------------------------
47312  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI
47313  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR37_HIGH_RSVD_30_16
47314  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE
47315  *
47316  */
47317 /*
47318  * Field : addrhi
47319  *
47320  * MAC Address37 [47:32]
47321  *
47322  * This field contains the upper 16 bits (47:32) of the 38th 6-byte MAC address.
47323  *
47324  * Field Access Macros:
47325  *
47326  */
47327 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field. */
47328 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_LSB 0
47329 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field. */
47330 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_MSB 15
47331 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field. */
47332 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_WIDTH 16
47333 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field value. */
47334 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_SET_MSK 0x0000ffff
47335 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field value. */
47336 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_CLR_MSK 0xffff0000
47337 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field. */
47338 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_RESET 0xffff
47339 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI field value from a register. */
47340 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
47341 /* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field value suitable for setting the register. */
47342 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
47343 
47344 /*
47345  * Field : reserved_30_16
47346  *
47347  * Reserved
47348  *
47349  * Field Access Macros:
47350  *
47351  */
47352 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_RSVD_30_16 register field. */
47353 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_RSVD_30_16_LSB 16
47354 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_RSVD_30_16 register field. */
47355 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_RSVD_30_16_MSB 30
47356 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_RSVD_30_16 register field. */
47357 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_RSVD_30_16_WIDTH 15
47358 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_RSVD_30_16 register field value. */
47359 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
47360 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_RSVD_30_16 register field value. */
47361 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
47362 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_RSVD_30_16 register field. */
47363 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_RSVD_30_16_RESET 0x0
47364 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_RSVD_30_16 field value from a register. */
47365 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
47366 /* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_RSVD_30_16 register field value suitable for setting the register. */
47367 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
47368 
47369 /*
47370  * Field : ae
47371  *
47372  * Address Enable
47373  *
47374  * When this bit is set, the address filter module uses the 38th MAC address for
47375  * perfect filtering.
47376  *
47377  * When this bit is reset, the address filter module ignores the address for
47378  * filtering.
47379  *
47380  * Field Enumeration Values:
47381  *
47382  * Enum | Value | Description
47383  * :----------------------------------------|:------|:------------
47384  * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_E_DISD | 0x0 |
47385  * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_E_END | 0x1 |
47386  *
47387  * Field Access Macros:
47388  *
47389  */
47390 /*
47391  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE
47392  *
47393  */
47394 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_E_DISD 0x0
47395 /*
47396  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE
47397  *
47398  */
47399 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_E_END 0x1
47400 
47401 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field. */
47402 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_LSB 31
47403 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field. */
47404 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_MSB 31
47405 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field. */
47406 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_WIDTH 1
47407 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field value. */
47408 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_SET_MSK 0x80000000
47409 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field value. */
47410 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_CLR_MSK 0x7fffffff
47411 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field. */
47412 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_RESET 0x0
47413 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE field value from a register. */
47414 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
47415 /* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field value suitable for setting the register. */
47416 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
47417 
47418 #ifndef __ASSEMBLY__
47419 /*
47420  * WARNING: The C register and register group struct declarations are provided for
47421  * convenience and illustrative purposes. They should, however, be used with
47422  * caution as the C language standard provides no guarantees about the alignment or
47423  * atomicity of device memory accesses. The recommended practice for writing
47424  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
47425  * alt_write_word() functions.
47426  *
47427  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR37_HIGH.
47428  */
47429 struct ALT_EMAC_GMAC_MAC_ADDR37_HIGH_s
47430 {
47431  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI */
47432  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR37_HIGH_RSVD_30_16 */
47433  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE */
47434 };
47435 
47436 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR37_HIGH. */
47437 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR37_HIGH_s ALT_EMAC_GMAC_MAC_ADDR37_HIGH_t;
47438 #endif /* __ASSEMBLY__ */
47439 
47440 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH register. */
47441 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_RESET 0x0000ffff
47442 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH register from the beginning of the component. */
47443 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_OFST 0x8a8
47444 /* The address of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH register. */
47445 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR37_HIGH_OFST))
47446 
47447 /*
47448  * Register : gmacgrp_mac_address37_low
47449  *
47450  * <b> Register 555 (MAC Address37 Low Register) </b>
47451  *
47452  * The MAC Address37 Low register holds the lower 32 bits of the 37th 6-byte MAC
47453  * address of the station.
47454  *
47455  * Register Layout
47456  *
47457  * Bits | Access | Reset | Description
47458  * :-------|:-------|:-----------|:------------------------------------
47459  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO
47460  *
47461  */
47462 /*
47463  * Field : addrlo
47464  *
47465  * MAC Address37 [31:0]
47466  *
47467  * This field contains the lower 32 bits of the 38th 6-byte MAC address. The
47468  * content of this field is undefined until loaded by the Application after the
47469  * initialization process.
47470  *
47471  * Field Access Macros:
47472  *
47473  */
47474 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field. */
47475 #define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_LSB 0
47476 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field. */
47477 #define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_MSB 31
47478 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field. */
47479 #define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_WIDTH 32
47480 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field value. */
47481 #define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_SET_MSK 0xffffffff
47482 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field value. */
47483 #define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_CLR_MSK 0x00000000
47484 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field. */
47485 #define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_RESET 0xffffffff
47486 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO field value from a register. */
47487 #define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
47488 /* Produces a ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field value suitable for setting the register. */
47489 #define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
47490 
47491 #ifndef __ASSEMBLY__
47492 /*
47493  * WARNING: The C register and register group struct declarations are provided for
47494  * convenience and illustrative purposes. They should, however, be used with
47495  * caution as the C language standard provides no guarantees about the alignment or
47496  * atomicity of device memory accesses. The recommended practice for writing
47497  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
47498  * alt_write_word() functions.
47499  *
47500  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR37_LOW.
47501  */
47502 struct ALT_EMAC_GMAC_MAC_ADDR37_LOW_s
47503 {
47504  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO */
47505 };
47506 
47507 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR37_LOW. */
47508 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR37_LOW_s ALT_EMAC_GMAC_MAC_ADDR37_LOW_t;
47509 #endif /* __ASSEMBLY__ */
47510 
47511 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_LOW register. */
47512 #define ALT_EMAC_GMAC_MAC_ADDR37_LOW_RESET 0xffffffff
47513 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR37_LOW register from the beginning of the component. */
47514 #define ALT_EMAC_GMAC_MAC_ADDR37_LOW_OFST 0x8ac
47515 /* The address of the ALT_EMAC_GMAC_MAC_ADDR37_LOW register. */
47516 #define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR37_LOW_OFST))
47517 
47518 /*
47519  * Register : gmacgrp_mac_address38_high
47520  *
47521  * <b> Register 556 (MAC Address38 High Register) </b>
47522  *
47523  * The MAC Address38 High register holds the upper 16 bits of the 39th 6-byte MAC
47524  * address of the station.
47525  *
47526  * If the MAC address registers are configured to be double-synchronized to the
47527  * (G)MII clock domains, then
47528  *
47529  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
47530  * or Bits[7:0] (in big-endian mode) of the MAC Address38 Low Register are written.
47531  * For proper synchronization updates, consecutive writes to this MAC Address38 Low
47532  * Register must be performed after at least four clock cycles in the destination
47533  * clock domain.
47534  *
47535  * Register Layout
47536  *
47537  * Bits | Access | Reset | Description
47538  * :--------|:-------|:-------|:-----------------------------------------
47539  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI
47540  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR38_HIGH_RSVD_30_16
47541  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE
47542  *
47543  */
47544 /*
47545  * Field : addrhi
47546  *
47547  * MAC Address38 [47:32]
47548  *
47549  * This field contains the upper 16 bits (47:32) of the 39th 6-byte MAC address.
47550  *
47551  * Field Access Macros:
47552  *
47553  */
47554 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field. */
47555 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_LSB 0
47556 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field. */
47557 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_MSB 15
47558 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field. */
47559 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_WIDTH 16
47560 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field value. */
47561 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_SET_MSK 0x0000ffff
47562 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field value. */
47563 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_CLR_MSK 0xffff0000
47564 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field. */
47565 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_RESET 0xffff
47566 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI field value from a register. */
47567 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
47568 /* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field value suitable for setting the register. */
47569 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
47570 
47571 /*
47572  * Field : reserved_30_16
47573  *
47574  * Reserved
47575  *
47576  * Field Access Macros:
47577  *
47578  */
47579 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_RSVD_30_16 register field. */
47580 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_RSVD_30_16_LSB 16
47581 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_RSVD_30_16 register field. */
47582 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_RSVD_30_16_MSB 30
47583 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_RSVD_30_16 register field. */
47584 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_RSVD_30_16_WIDTH 15
47585 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_RSVD_30_16 register field value. */
47586 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
47587 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_RSVD_30_16 register field value. */
47588 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
47589 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_RSVD_30_16 register field. */
47590 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_RSVD_30_16_RESET 0x0
47591 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_RSVD_30_16 field value from a register. */
47592 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
47593 /* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_RSVD_30_16 register field value suitable for setting the register. */
47594 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
47595 
47596 /*
47597  * Field : ae
47598  *
47599  * Address Enable
47600  *
47601  * When this bit is set, the address filter module uses the 39th MAC address for
47602  * perfect filtering.
47603  *
47604  * When this bit is reset, the address filter module ignores the address for
47605  * filtering.
47606  *
47607  * Field Enumeration Values:
47608  *
47609  * Enum | Value | Description
47610  * :----------------------------------------|:------|:------------
47611  * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_E_DISD | 0x0 |
47612  * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_E_END | 0x1 |
47613  *
47614  * Field Access Macros:
47615  *
47616  */
47617 /*
47618  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE
47619  *
47620  */
47621 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_E_DISD 0x0
47622 /*
47623  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE
47624  *
47625  */
47626 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_E_END 0x1
47627 
47628 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field. */
47629 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_LSB 31
47630 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field. */
47631 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_MSB 31
47632 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field. */
47633 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_WIDTH 1
47634 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field value. */
47635 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_SET_MSK 0x80000000
47636 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field value. */
47637 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_CLR_MSK 0x7fffffff
47638 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field. */
47639 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_RESET 0x0
47640 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE field value from a register. */
47641 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
47642 /* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field value suitable for setting the register. */
47643 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
47644 
47645 #ifndef __ASSEMBLY__
47646 /*
47647  * WARNING: The C register and register group struct declarations are provided for
47648  * convenience and illustrative purposes. They should, however, be used with
47649  * caution as the C language standard provides no guarantees about the alignment or
47650  * atomicity of device memory accesses. The recommended practice for writing
47651  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
47652  * alt_write_word() functions.
47653  *
47654  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR38_HIGH.
47655  */
47656 struct ALT_EMAC_GMAC_MAC_ADDR38_HIGH_s
47657 {
47658  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI */
47659  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR38_HIGH_RSVD_30_16 */
47660  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE */
47661 };
47662 
47663 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR38_HIGH. */
47664 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR38_HIGH_s ALT_EMAC_GMAC_MAC_ADDR38_HIGH_t;
47665 #endif /* __ASSEMBLY__ */
47666 
47667 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH register. */
47668 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_RESET 0x0000ffff
47669 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH register from the beginning of the component. */
47670 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_OFST 0x8b0
47671 /* The address of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH register. */
47672 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR38_HIGH_OFST))
47673 
47674 /*
47675  * Register : gmacgrp_mac_address38_low
47676  *
47677  * <b> Register 557 (MAC Address38 Low Register) </b>
47678  *
47679  * The MAC Address38 Low register holds the lower 32 bits of the 39th 6-byte MAC
47680  * address of the station.
47681  *
47682  * Register Layout
47683  *
47684  * Bits | Access | Reset | Description
47685  * :-------|:-------|:-----------|:------------------------------------
47686  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO
47687  *
47688  */
47689 /*
47690  * Field : addrlo
47691  *
47692  * MAC Address38 [31:0]
47693  *
47694  * This field contains the lower 32 bits of the 39th 6-byte MAC address. The
47695  * content of this field is undefined until loaded by the Application after the
47696  * initialization process.
47697  *
47698  * Field Access Macros:
47699  *
47700  */
47701 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field. */
47702 #define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_LSB 0
47703 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field. */
47704 #define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_MSB 31
47705 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field. */
47706 #define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_WIDTH 32
47707 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field value. */
47708 #define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_SET_MSK 0xffffffff
47709 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field value. */
47710 #define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_CLR_MSK 0x00000000
47711 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field. */
47712 #define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_RESET 0xffffffff
47713 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO field value from a register. */
47714 #define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
47715 /* Produces a ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field value suitable for setting the register. */
47716 #define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
47717 
47718 #ifndef __ASSEMBLY__
47719 /*
47720  * WARNING: The C register and register group struct declarations are provided for
47721  * convenience and illustrative purposes. They should, however, be used with
47722  * caution as the C language standard provides no guarantees about the alignment or
47723  * atomicity of device memory accesses. The recommended practice for writing
47724  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
47725  * alt_write_word() functions.
47726  *
47727  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR38_LOW.
47728  */
47729 struct ALT_EMAC_GMAC_MAC_ADDR38_LOW_s
47730 {
47731  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO */
47732 };
47733 
47734 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR38_LOW. */
47735 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR38_LOW_s ALT_EMAC_GMAC_MAC_ADDR38_LOW_t;
47736 #endif /* __ASSEMBLY__ */
47737 
47738 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_LOW register. */
47739 #define ALT_EMAC_GMAC_MAC_ADDR38_LOW_RESET 0xffffffff
47740 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR38_LOW register from the beginning of the component. */
47741 #define ALT_EMAC_GMAC_MAC_ADDR38_LOW_OFST 0x8b4
47742 /* The address of the ALT_EMAC_GMAC_MAC_ADDR38_LOW register. */
47743 #define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR38_LOW_OFST))
47744 
47745 /*
47746  * Register : gmacgrp_mac_address39_high
47747  *
47748  * <b> Register 558 (MAC Address39 High Register) </b>
47749  *
47750  * The MAC Address39 High register holds the upper 16 bits of the 40th 6-byte MAC
47751  * address of the station. If the MAC address registers are configured to be
47752  * double-synchronized to the (G)MII clock domains, then the synchronization is
47753  * triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
47754  * endian mode) of the MAC Address40 Low Register are written. For proper
47755  * synchronization updates, consecutive writes to this MAC Address40 Low Register
47756  * must be performed after at least four clock cycles in the destination clock
47757  * domain.
47758  *
47759  * Register Layout
47760  *
47761  * Bits | Access | Reset | Description
47762  * :--------|:-------|:-------|:-----------------------------------------
47763  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI
47764  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR39_HIGH_RSVD_30_16
47765  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE
47766  *
47767  */
47768 /*
47769  * Field : addrhi
47770  *
47771  * MAC Address39 [47:32]
47772  *
47773  * This field contains the upper 16 bits (47:32) of the 40th 6-byte MAC address.
47774  *
47775  * Field Access Macros:
47776  *
47777  */
47778 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field. */
47779 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_LSB 0
47780 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field. */
47781 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_MSB 15
47782 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field. */
47783 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_WIDTH 16
47784 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field value. */
47785 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_SET_MSK 0x0000ffff
47786 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field value. */
47787 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_CLR_MSK 0xffff0000
47788 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field. */
47789 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_RESET 0xffff
47790 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI field value from a register. */
47791 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
47792 /* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field value suitable for setting the register. */
47793 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
47794 
47795 /*
47796  * Field : reserved_30_16
47797  *
47798  * Reserved
47799  *
47800  * Field Access Macros:
47801  *
47802  */
47803 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_RSVD_30_16 register field. */
47804 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_RSVD_30_16_LSB 16
47805 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_RSVD_30_16 register field. */
47806 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_RSVD_30_16_MSB 30
47807 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_RSVD_30_16 register field. */
47808 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_RSVD_30_16_WIDTH 15
47809 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_RSVD_30_16 register field value. */
47810 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
47811 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_RSVD_30_16 register field value. */
47812 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
47813 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_RSVD_30_16 register field. */
47814 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_RSVD_30_16_RESET 0x0
47815 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_RSVD_30_16 field value from a register. */
47816 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
47817 /* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_RSVD_30_16 register field value suitable for setting the register. */
47818 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
47819 
47820 /*
47821  * Field : ae
47822  *
47823  * Address Enable
47824  *
47825  * When this bit is set, the address filter module uses the 40th MAC address for
47826  * perfect filtering.
47827  *
47828  * When this bit is reset, the address filter module ignores the address for
47829  * filtering.
47830  *
47831  * Field Enumeration Values:
47832  *
47833  * Enum | Value | Description
47834  * :----------------------------------------|:------|:------------
47835  * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_E_DISD | 0x0 |
47836  * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_E_END | 0x1 |
47837  *
47838  * Field Access Macros:
47839  *
47840  */
47841 /*
47842  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE
47843  *
47844  */
47845 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_E_DISD 0x0
47846 /*
47847  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE
47848  *
47849  */
47850 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_E_END 0x1
47851 
47852 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field. */
47853 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_LSB 31
47854 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field. */
47855 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_MSB 31
47856 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field. */
47857 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_WIDTH 1
47858 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field value. */
47859 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_SET_MSK 0x80000000
47860 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field value. */
47861 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_CLR_MSK 0x7fffffff
47862 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field. */
47863 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_RESET 0x0
47864 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE field value from a register. */
47865 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
47866 /* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field value suitable for setting the register. */
47867 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
47868 
47869 #ifndef __ASSEMBLY__
47870 /*
47871  * WARNING: The C register and register group struct declarations are provided for
47872  * convenience and illustrative purposes. They should, however, be used with
47873  * caution as the C language standard provides no guarantees about the alignment or
47874  * atomicity of device memory accesses. The recommended practice for writing
47875  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
47876  * alt_write_word() functions.
47877  *
47878  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR39_HIGH.
47879  */
47880 struct ALT_EMAC_GMAC_MAC_ADDR39_HIGH_s
47881 {
47882  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI */
47883  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR39_HIGH_RSVD_30_16 */
47884  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE */
47885 };
47886 
47887 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR39_HIGH. */
47888 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR39_HIGH_s ALT_EMAC_GMAC_MAC_ADDR39_HIGH_t;
47889 #endif /* __ASSEMBLY__ */
47890 
47891 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH register. */
47892 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_RESET 0x0000ffff
47893 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH register from the beginning of the component. */
47894 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_OFST 0x8b8
47895 /* The address of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH register. */
47896 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR39_HIGH_OFST))
47897 
47898 /*
47899  * Register : gmacgrp_mac_address39_low
47900  *
47901  * <b> Register 559 (MAC Address39 Low Register) </b>
47902  *
47903  * The MAC Address39 Low register holds the lower 32 bits of the 40th 6-byte MAC
47904  * address of the station.
47905  *
47906  * Register Layout
47907  *
47908  * Bits | Access | Reset | Description
47909  * :-------|:-------|:-----------|:------------------------------------
47910  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO
47911  *
47912  */
47913 /*
47914  * Field : addrlo
47915  *
47916  * MAC Address39 [31:0]
47917  *
47918  * This field contains the lower 32 bits of the 40th 6-byte MAC address. The
47919  * content of this field is undefined until loaded by the Application after the
47920  * initialization process.
47921  *
47922  * Field Access Macros:
47923  *
47924  */
47925 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field. */
47926 #define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_LSB 0
47927 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field. */
47928 #define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_MSB 31
47929 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field. */
47930 #define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_WIDTH 32
47931 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field value. */
47932 #define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_SET_MSK 0xffffffff
47933 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field value. */
47934 #define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_CLR_MSK 0x00000000
47935 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field. */
47936 #define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_RESET 0xffffffff
47937 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO field value from a register. */
47938 #define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
47939 /* Produces a ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field value suitable for setting the register. */
47940 #define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
47941 
47942 #ifndef __ASSEMBLY__
47943 /*
47944  * WARNING: The C register and register group struct declarations are provided for
47945  * convenience and illustrative purposes. They should, however, be used with
47946  * caution as the C language standard provides no guarantees about the alignment or
47947  * atomicity of device memory accesses. The recommended practice for writing
47948  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
47949  * alt_write_word() functions.
47950  *
47951  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR39_LOW.
47952  */
47953 struct ALT_EMAC_GMAC_MAC_ADDR39_LOW_s
47954 {
47955  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO */
47956 };
47957 
47958 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR39_LOW. */
47959 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR39_LOW_s ALT_EMAC_GMAC_MAC_ADDR39_LOW_t;
47960 #endif /* __ASSEMBLY__ */
47961 
47962 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_LOW register. */
47963 #define ALT_EMAC_GMAC_MAC_ADDR39_LOW_RESET 0xffffffff
47964 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR39_LOW register from the beginning of the component. */
47965 #define ALT_EMAC_GMAC_MAC_ADDR39_LOW_OFST 0x8bc
47966 /* The address of the ALT_EMAC_GMAC_MAC_ADDR39_LOW register. */
47967 #define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR39_LOW_OFST))
47968 
47969 /*
47970  * Register : gmacgrp_mac_address40_high
47971  *
47972  * <b> Register 560 (MAC Address40 High Register) </b>
47973  *
47974  * The MAC Address40 High register holds the upper 16 bits of the 41st 6-byte MAC
47975  * address of the station.
47976  *
47977  * If the MAC address registers are configured to be double-synchronized to the
47978  * (G)MII clock domains, then
47979  *
47980  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
47981  * or Bits[7:0] (in big-endian mode) of the MAC Address40 Low Register are written.
47982  * For proper synchronization updates, consecutive writes to this MAC Address40 Low
47983  * Register must be performed after at least four clock cycles in the destination
47984  * clock domain.
47985  *
47986  * Register Layout
47987  *
47988  * Bits | Access | Reset | Description
47989  * :--------|:-------|:-------|:-----------------------------------------
47990  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI
47991  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR40_HIGH_RSVD_30_16
47992  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE
47993  *
47994  */
47995 /*
47996  * Field : addrhi
47997  *
47998  * MAC Address40 [47:32]
47999  *
48000  * This field contains the upper 16 bits (47:32) of the 41st 6-byte MAC address.
48001  *
48002  * Field Access Macros:
48003  *
48004  */
48005 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field. */
48006 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_LSB 0
48007 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field. */
48008 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_MSB 15
48009 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field. */
48010 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_WIDTH 16
48011 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field value. */
48012 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_SET_MSK 0x0000ffff
48013 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field value. */
48014 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_CLR_MSK 0xffff0000
48015 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field. */
48016 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_RESET 0xffff
48017 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI field value from a register. */
48018 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
48019 /* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field value suitable for setting the register. */
48020 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
48021 
48022 /*
48023  * Field : reserved_30_16
48024  *
48025  * Reserved
48026  *
48027  * Field Access Macros:
48028  *
48029  */
48030 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_RSVD_30_16 register field. */
48031 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_RSVD_30_16_LSB 16
48032 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_RSVD_30_16 register field. */
48033 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_RSVD_30_16_MSB 30
48034 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_RSVD_30_16 register field. */
48035 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_RSVD_30_16_WIDTH 15
48036 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_RSVD_30_16 register field value. */
48037 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
48038 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_RSVD_30_16 register field value. */
48039 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
48040 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_RSVD_30_16 register field. */
48041 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_RSVD_30_16_RESET 0x0
48042 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_RSVD_30_16 field value from a register. */
48043 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
48044 /* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_RSVD_30_16 register field value suitable for setting the register. */
48045 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
48046 
48047 /*
48048  * Field : ae
48049  *
48050  * Address Enable
48051  *
48052  * When this bit is set, the address filter module uses the 41st MAC address for
48053  * perfect filtering.
48054  *
48055  * When this bit is reset, the address filter module ignores the address for
48056  * filtering.
48057  *
48058  * Field Enumeration Values:
48059  *
48060  * Enum | Value | Description
48061  * :----------------------------------------|:------|:------------
48062  * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_E_DISD | 0x0 |
48063  * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_E_END | 0x1 |
48064  *
48065  * Field Access Macros:
48066  *
48067  */
48068 /*
48069  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE
48070  *
48071  */
48072 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_E_DISD 0x0
48073 /*
48074  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE
48075  *
48076  */
48077 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_E_END 0x1
48078 
48079 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field. */
48080 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_LSB 31
48081 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field. */
48082 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_MSB 31
48083 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field. */
48084 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_WIDTH 1
48085 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field value. */
48086 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_SET_MSK 0x80000000
48087 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field value. */
48088 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_CLR_MSK 0x7fffffff
48089 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field. */
48090 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_RESET 0x0
48091 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE field value from a register. */
48092 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
48093 /* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field value suitable for setting the register. */
48094 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
48095 
48096 #ifndef __ASSEMBLY__
48097 /*
48098  * WARNING: The C register and register group struct declarations are provided for
48099  * convenience and illustrative purposes. They should, however, be used with
48100  * caution as the C language standard provides no guarantees about the alignment or
48101  * atomicity of device memory accesses. The recommended practice for writing
48102  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
48103  * alt_write_word() functions.
48104  *
48105  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR40_HIGH.
48106  */
48107 struct ALT_EMAC_GMAC_MAC_ADDR40_HIGH_s
48108 {
48109  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI */
48110  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR40_HIGH_RSVD_30_16 */
48111  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE */
48112 };
48113 
48114 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR40_HIGH. */
48115 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR40_HIGH_s ALT_EMAC_GMAC_MAC_ADDR40_HIGH_t;
48116 #endif /* __ASSEMBLY__ */
48117 
48118 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH register. */
48119 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_RESET 0x0000ffff
48120 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH register from the beginning of the component. */
48121 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_OFST 0x8c0
48122 /* The address of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH register. */
48123 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR40_HIGH_OFST))
48124 
48125 /*
48126  * Register : gmacgrp_mac_address40_low
48127  *
48128  * <b> Register 561 (MAC Address40 Low Register) </b>
48129  *
48130  * The MAC Address40 Low register holds the lower 32 bits of the 41st 6-byte MAC
48131  * address of the station.
48132  *
48133  * Register Layout
48134  *
48135  * Bits | Access | Reset | Description
48136  * :-------|:-------|:-----------|:------------------------------------
48137  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO
48138  *
48139  */
48140 /*
48141  * Field : addrlo
48142  *
48143  * MAC Address40 [31:0]
48144  *
48145  * This field contains the lower 32 bits of the 41st 6-byte MAC address. The
48146  * content of this field is undefined until loaded by the Application after the
48147  * initialization process.
48148  *
48149  * Field Access Macros:
48150  *
48151  */
48152 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field. */
48153 #define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_LSB 0
48154 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field. */
48155 #define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_MSB 31
48156 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field. */
48157 #define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_WIDTH 32
48158 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field value. */
48159 #define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_SET_MSK 0xffffffff
48160 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field value. */
48161 #define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_CLR_MSK 0x00000000
48162 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field. */
48163 #define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_RESET 0xffffffff
48164 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO field value from a register. */
48165 #define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
48166 /* Produces a ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field value suitable for setting the register. */
48167 #define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
48168 
48169 #ifndef __ASSEMBLY__
48170 /*
48171  * WARNING: The C register and register group struct declarations are provided for
48172  * convenience and illustrative purposes. They should, however, be used with
48173  * caution as the C language standard provides no guarantees about the alignment or
48174  * atomicity of device memory accesses. The recommended practice for writing
48175  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
48176  * alt_write_word() functions.
48177  *
48178  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR40_LOW.
48179  */
48180 struct ALT_EMAC_GMAC_MAC_ADDR40_LOW_s
48181 {
48182  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO */
48183 };
48184 
48185 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR40_LOW. */
48186 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR40_LOW_s ALT_EMAC_GMAC_MAC_ADDR40_LOW_t;
48187 #endif /* __ASSEMBLY__ */
48188 
48189 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_LOW register. */
48190 #define ALT_EMAC_GMAC_MAC_ADDR40_LOW_RESET 0xffffffff
48191 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR40_LOW register from the beginning of the component. */
48192 #define ALT_EMAC_GMAC_MAC_ADDR40_LOW_OFST 0x8c4
48193 /* The address of the ALT_EMAC_GMAC_MAC_ADDR40_LOW register. */
48194 #define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR40_LOW_OFST))
48195 
48196 /*
48197  * Register : gmacgrp_mac_address41_high
48198  *
48199  * <b> Register 562 (MAC Address41 High Register) </b>
48200  *
48201  * The MAC Address41 High register holds the upper 16 bits of the 42nd 6-byte MAC
48202  * address of the station.
48203  *
48204  * If the MAC address registers are configured to be double-synchronized to the
48205  * (G)MII clock domains, then
48206  *
48207  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
48208  * or Bits[7:0] (in big-endian mode) of the MAC Address41 Low Register are written.
48209  * For proper synchronization updates, consecutive writes to this MAC Address41 Low
48210  * Register must be performed after at least four clock cycles in the destination
48211  * clock domain.
48212  *
48213  * Register Layout
48214  *
48215  * Bits | Access | Reset | Description
48216  * :--------|:-------|:-------|:-----------------------------------------
48217  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI
48218  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR41_HIGH_RSVD_30_16
48219  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE
48220  *
48221  */
48222 /*
48223  * Field : addrhi
48224  *
48225  * MAC Address41 [47:32]
48226  *
48227  * This field contains the upper 16 bits (47:32) of the 42nd 6-byte MAC address.
48228  *
48229  * Field Access Macros:
48230  *
48231  */
48232 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field. */
48233 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_LSB 0
48234 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field. */
48235 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_MSB 15
48236 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field. */
48237 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_WIDTH 16
48238 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field value. */
48239 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_SET_MSK 0x0000ffff
48240 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field value. */
48241 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_CLR_MSK 0xffff0000
48242 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field. */
48243 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_RESET 0xffff
48244 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI field value from a register. */
48245 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
48246 /* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field value suitable for setting the register. */
48247 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
48248 
48249 /*
48250  * Field : reserved_30_16
48251  *
48252  * Reserved
48253  *
48254  * Field Access Macros:
48255  *
48256  */
48257 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_RSVD_30_16 register field. */
48258 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_RSVD_30_16_LSB 16
48259 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_RSVD_30_16 register field. */
48260 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_RSVD_30_16_MSB 30
48261 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_RSVD_30_16 register field. */
48262 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_RSVD_30_16_WIDTH 15
48263 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_RSVD_30_16 register field value. */
48264 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
48265 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_RSVD_30_16 register field value. */
48266 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
48267 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_RSVD_30_16 register field. */
48268 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_RSVD_30_16_RESET 0x0
48269 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_RSVD_30_16 field value from a register. */
48270 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
48271 /* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_RSVD_30_16 register field value suitable for setting the register. */
48272 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
48273 
48274 /*
48275  * Field : ae
48276  *
48277  * Address Enable
48278  *
48279  * When this bit is set, the address filter module uses the 42nd MAC address for
48280  * perfect filtering.
48281  *
48282  * When this bit is reset, the address filter module ignores the address for
48283  * filtering.
48284  *
48285  * Field Enumeration Values:
48286  *
48287  * Enum | Value | Description
48288  * :----------------------------------------|:------|:------------
48289  * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_E_DISD | 0x0 |
48290  * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_E_END | 0x1 |
48291  *
48292  * Field Access Macros:
48293  *
48294  */
48295 /*
48296  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE
48297  *
48298  */
48299 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_E_DISD 0x0
48300 /*
48301  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE
48302  *
48303  */
48304 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_E_END 0x1
48305 
48306 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field. */
48307 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_LSB 31
48308 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field. */
48309 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_MSB 31
48310 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field. */
48311 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_WIDTH 1
48312 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field value. */
48313 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_SET_MSK 0x80000000
48314 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field value. */
48315 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_CLR_MSK 0x7fffffff
48316 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field. */
48317 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_RESET 0x0
48318 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE field value from a register. */
48319 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
48320 /* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field value suitable for setting the register. */
48321 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
48322 
48323 #ifndef __ASSEMBLY__
48324 /*
48325  * WARNING: The C register and register group struct declarations are provided for
48326  * convenience and illustrative purposes. They should, however, be used with
48327  * caution as the C language standard provides no guarantees about the alignment or
48328  * atomicity of device memory accesses. The recommended practice for writing
48329  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
48330  * alt_write_word() functions.
48331  *
48332  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR41_HIGH.
48333  */
48334 struct ALT_EMAC_GMAC_MAC_ADDR41_HIGH_s
48335 {
48336  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI */
48337  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR41_HIGH_RSVD_30_16 */
48338  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE */
48339 };
48340 
48341 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR41_HIGH. */
48342 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR41_HIGH_s ALT_EMAC_GMAC_MAC_ADDR41_HIGH_t;
48343 #endif /* __ASSEMBLY__ */
48344 
48345 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH register. */
48346 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_RESET 0x0000ffff
48347 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH register from the beginning of the component. */
48348 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_OFST 0x8c8
48349 /* The address of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH register. */
48350 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR41_HIGH_OFST))
48351 
48352 /*
48353  * Register : gmacgrp_mac_address41_low
48354  *
48355  * <b> Register 563 (MAC Address41 Low Register) </b>
48356  *
48357  * The MAC Address41 Low register holds the lower 32 bits of the 42nd 6-byte MAC
48358  * address of the station.
48359  *
48360  * Register Layout
48361  *
48362  * Bits | Access | Reset | Description
48363  * :-------|:-------|:-----------|:------------------------------------
48364  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO
48365  *
48366  */
48367 /*
48368  * Field : addrlo
48369  *
48370  * MAC Address41 [31:0]
48371  *
48372  * This field contains the lower 32 bits of the 42nd 6-byte MAC address. The
48373  * content of this field is undefined until loaded by the Application after the
48374  * initialization process.
48375  *
48376  * Field Access Macros:
48377  *
48378  */
48379 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field. */
48380 #define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_LSB 0
48381 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field. */
48382 #define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_MSB 31
48383 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field. */
48384 #define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_WIDTH 32
48385 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field value. */
48386 #define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_SET_MSK 0xffffffff
48387 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field value. */
48388 #define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_CLR_MSK 0x00000000
48389 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field. */
48390 #define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_RESET 0xffffffff
48391 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO field value from a register. */
48392 #define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
48393 /* Produces a ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field value suitable for setting the register. */
48394 #define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
48395 
48396 #ifndef __ASSEMBLY__
48397 /*
48398  * WARNING: The C register and register group struct declarations are provided for
48399  * convenience and illustrative purposes. They should, however, be used with
48400  * caution as the C language standard provides no guarantees about the alignment or
48401  * atomicity of device memory accesses. The recommended practice for writing
48402  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
48403  * alt_write_word() functions.
48404  *
48405  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR41_LOW.
48406  */
48407 struct ALT_EMAC_GMAC_MAC_ADDR41_LOW_s
48408 {
48409  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO */
48410 };
48411 
48412 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR41_LOW. */
48413 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR41_LOW_s ALT_EMAC_GMAC_MAC_ADDR41_LOW_t;
48414 #endif /* __ASSEMBLY__ */
48415 
48416 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_LOW register. */
48417 #define ALT_EMAC_GMAC_MAC_ADDR41_LOW_RESET 0xffffffff
48418 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR41_LOW register from the beginning of the component. */
48419 #define ALT_EMAC_GMAC_MAC_ADDR41_LOW_OFST 0x8cc
48420 /* The address of the ALT_EMAC_GMAC_MAC_ADDR41_LOW register. */
48421 #define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR41_LOW_OFST))
48422 
48423 /*
48424  * Register : gmacgrp_mac_address42_high
48425  *
48426  * <b> Register 564 (MAC Address42 High Register) </b>
48427  *
48428  * The MAC Address42 High register holds the upper 16 bits of the 43rd 6-byte MAC
48429  * address of the station.
48430  *
48431  * If the MAC address registers are configured to be double-synchronized to the
48432  * (G)MII clock domains, then
48433  *
48434  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
48435  * or Bits[7:0] (in big-endian mode) of the MAC Address42 Low Register are written.
48436  * For proper synchronization updates, consecutive writes to this MAC Address42 Low
48437  * Register must be performed after at least four clock cycles in the destination
48438  * clock domain.
48439  *
48440  * Register Layout
48441  *
48442  * Bits | Access | Reset | Description
48443  * :--------|:-------|:-------|:-----------------------------------------
48444  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI
48445  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR42_HIGH_RSVD_30_16
48446  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE
48447  *
48448  */
48449 /*
48450  * Field : addrhi
48451  *
48452  * MAC Address42 [47:32]
48453  *
48454  * This field contains the upper 16 bits (47:32) of the 43rd 6-byte MAC address.
48455  *
48456  * Field Access Macros:
48457  *
48458  */
48459 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field. */
48460 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_LSB 0
48461 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field. */
48462 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_MSB 15
48463 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field. */
48464 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_WIDTH 16
48465 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field value. */
48466 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_SET_MSK 0x0000ffff
48467 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field value. */
48468 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_CLR_MSK 0xffff0000
48469 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field. */
48470 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_RESET 0xffff
48471 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI field value from a register. */
48472 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
48473 /* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field value suitable for setting the register. */
48474 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
48475 
48476 /*
48477  * Field : reserved_30_16
48478  *
48479  * Reserved
48480  *
48481  * Field Access Macros:
48482  *
48483  */
48484 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_RSVD_30_16 register field. */
48485 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_RSVD_30_16_LSB 16
48486 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_RSVD_30_16 register field. */
48487 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_RSVD_30_16_MSB 30
48488 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_RSVD_30_16 register field. */
48489 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_RSVD_30_16_WIDTH 15
48490 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_RSVD_30_16 register field value. */
48491 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
48492 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_RSVD_30_16 register field value. */
48493 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
48494 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_RSVD_30_16 register field. */
48495 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_RSVD_30_16_RESET 0x0
48496 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_RSVD_30_16 field value from a register. */
48497 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
48498 /* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_RSVD_30_16 register field value suitable for setting the register. */
48499 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
48500 
48501 /*
48502  * Field : ae
48503  *
48504  * Address Enable
48505  *
48506  * When this bit is set, the address filter module uses the 43rd MAC address for
48507  * perfect filtering.
48508  *
48509  * When this bit is reset, the address filter module ignores the address for
48510  * filtering.
48511  *
48512  * Field Enumeration Values:
48513  *
48514  * Enum | Value | Description
48515  * :----------------------------------------|:------|:------------
48516  * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_E_DISD | 0x0 |
48517  * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_E_END | 0x1 |
48518  *
48519  * Field Access Macros:
48520  *
48521  */
48522 /*
48523  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE
48524  *
48525  */
48526 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_E_DISD 0x0
48527 /*
48528  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE
48529  *
48530  */
48531 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_E_END 0x1
48532 
48533 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field. */
48534 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_LSB 31
48535 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field. */
48536 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_MSB 31
48537 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field. */
48538 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_WIDTH 1
48539 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field value. */
48540 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_SET_MSK 0x80000000
48541 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field value. */
48542 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_CLR_MSK 0x7fffffff
48543 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field. */
48544 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_RESET 0x0
48545 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE field value from a register. */
48546 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
48547 /* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field value suitable for setting the register. */
48548 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
48549 
48550 #ifndef __ASSEMBLY__
48551 /*
48552  * WARNING: The C register and register group struct declarations are provided for
48553  * convenience and illustrative purposes. They should, however, be used with
48554  * caution as the C language standard provides no guarantees about the alignment or
48555  * atomicity of device memory accesses. The recommended practice for writing
48556  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
48557  * alt_write_word() functions.
48558  *
48559  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR42_HIGH.
48560  */
48561 struct ALT_EMAC_GMAC_MAC_ADDR42_HIGH_s
48562 {
48563  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI */
48564  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR42_HIGH_RSVD_30_16 */
48565  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE */
48566 };
48567 
48568 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR42_HIGH. */
48569 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR42_HIGH_s ALT_EMAC_GMAC_MAC_ADDR42_HIGH_t;
48570 #endif /* __ASSEMBLY__ */
48571 
48572 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH register. */
48573 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_RESET 0x0000ffff
48574 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH register from the beginning of the component. */
48575 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_OFST 0x8d0
48576 /* The address of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH register. */
48577 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR42_HIGH_OFST))
48578 
48579 /*
48580  * Register : gmacgrp_mac_address42_low
48581  *
48582  * <b> Register 565 (MAC Address42 Low Register) </b>
48583  *
48584  * The MAC Address42 Low register holds the lower 32 bits of the 43rd 6-byte MAC
48585  * address of the station.
48586  *
48587  * Register Layout
48588  *
48589  * Bits | Access | Reset | Description
48590  * :-------|:-------|:-----------|:------------------------------------
48591  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO
48592  *
48593  */
48594 /*
48595  * Field : addrlo
48596  *
48597  * MAC Address42 [31:0]
48598  *
48599  * This field contains the lower 32 bits of the 43rd 6-byte MAC address. The
48600  * content of this field is undefined until loaded by the Application after the
48601  * initialization process.
48602  *
48603  * Field Access Macros:
48604  *
48605  */
48606 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field. */
48607 #define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_LSB 0
48608 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field. */
48609 #define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_MSB 31
48610 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field. */
48611 #define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_WIDTH 32
48612 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field value. */
48613 #define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_SET_MSK 0xffffffff
48614 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field value. */
48615 #define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_CLR_MSK 0x00000000
48616 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field. */
48617 #define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_RESET 0xffffffff
48618 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO field value from a register. */
48619 #define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
48620 /* Produces a ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field value suitable for setting the register. */
48621 #define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
48622 
48623 #ifndef __ASSEMBLY__
48624 /*
48625  * WARNING: The C register and register group struct declarations are provided for
48626  * convenience and illustrative purposes. They should, however, be used with
48627  * caution as the C language standard provides no guarantees about the alignment or
48628  * atomicity of device memory accesses. The recommended practice for writing
48629  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
48630  * alt_write_word() functions.
48631  *
48632  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR42_LOW.
48633  */
48634 struct ALT_EMAC_GMAC_MAC_ADDR42_LOW_s
48635 {
48636  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO */
48637 };
48638 
48639 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR42_LOW. */
48640 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR42_LOW_s ALT_EMAC_GMAC_MAC_ADDR42_LOW_t;
48641 #endif /* __ASSEMBLY__ */
48642 
48643 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_LOW register. */
48644 #define ALT_EMAC_GMAC_MAC_ADDR42_LOW_RESET 0xffffffff
48645 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR42_LOW register from the beginning of the component. */
48646 #define ALT_EMAC_GMAC_MAC_ADDR42_LOW_OFST 0x8d4
48647 /* The address of the ALT_EMAC_GMAC_MAC_ADDR42_LOW register. */
48648 #define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR42_LOW_OFST))
48649 
48650 /*
48651  * Register : gmacgrp_mac_address43_high
48652  *
48653  * <b> Register 566 (MAC Address43 High Register) </b>
48654  *
48655  * The MAC Address43 High register holds the upper 16 bits of the 44th 6-byte MAC
48656  * address of the station.
48657  *
48658  * If the MAC address registers are configured to be double-synchronized to the
48659  * (G)MII clock domains, then
48660  *
48661  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
48662  * or Bits[7:0] (in big-endian mode) of the MAC Address43 Low Register are written.
48663  * For proper synchronization updates, consecutive writes to this MAC Address43 Low
48664  * Register must be performed after at least four clock cycles in the destination
48665  * clock domain.
48666  *
48667  * Register Layout
48668  *
48669  * Bits | Access | Reset | Description
48670  * :--------|:-------|:-------|:-----------------------------------------
48671  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI
48672  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR43_HIGH_RSVD_30_16
48673  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE
48674  *
48675  */
48676 /*
48677  * Field : addrhi
48678  *
48679  * MAC Address43 [47:32]
48680  *
48681  * This field contains the upper 16 bits (47:32) of the 44th 6-byte MAC address.
48682  *
48683  * Field Access Macros:
48684  *
48685  */
48686 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field. */
48687 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_LSB 0
48688 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field. */
48689 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_MSB 15
48690 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field. */
48691 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_WIDTH 16
48692 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field value. */
48693 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_SET_MSK 0x0000ffff
48694 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field value. */
48695 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_CLR_MSK 0xffff0000
48696 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field. */
48697 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_RESET 0xffff
48698 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI field value from a register. */
48699 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
48700 /* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field value suitable for setting the register. */
48701 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
48702 
48703 /*
48704  * Field : reserved_30_16
48705  *
48706  * Reserved
48707  *
48708  * Field Access Macros:
48709  *
48710  */
48711 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_RSVD_30_16 register field. */
48712 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_RSVD_30_16_LSB 16
48713 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_RSVD_30_16 register field. */
48714 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_RSVD_30_16_MSB 30
48715 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_RSVD_30_16 register field. */
48716 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_RSVD_30_16_WIDTH 15
48717 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_RSVD_30_16 register field value. */
48718 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
48719 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_RSVD_30_16 register field value. */
48720 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
48721 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_RSVD_30_16 register field. */
48722 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_RSVD_30_16_RESET 0x0
48723 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_RSVD_30_16 field value from a register. */
48724 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
48725 /* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_RSVD_30_16 register field value suitable for setting the register. */
48726 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
48727 
48728 /*
48729  * Field : ae
48730  *
48731  * Address Enable
48732  *
48733  * When this bit is set, the address filter module uses the 44th MAC address for
48734  * perfect filtering.
48735  *
48736  * When this bit is reset, the address filter module ignores the address for
48737  * filtering.
48738  *
48739  * Field Enumeration Values:
48740  *
48741  * Enum | Value | Description
48742  * :----------------------------------------|:------|:------------
48743  * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_E_DISD | 0x0 |
48744  * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_E_END | 0x1 |
48745  *
48746  * Field Access Macros:
48747  *
48748  */
48749 /*
48750  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE
48751  *
48752  */
48753 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_E_DISD 0x0
48754 /*
48755  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE
48756  *
48757  */
48758 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_E_END 0x1
48759 
48760 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field. */
48761 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_LSB 31
48762 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field. */
48763 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_MSB 31
48764 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field. */
48765 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_WIDTH 1
48766 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field value. */
48767 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_SET_MSK 0x80000000
48768 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field value. */
48769 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_CLR_MSK 0x7fffffff
48770 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field. */
48771 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_RESET 0x0
48772 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE field value from a register. */
48773 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
48774 /* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field value suitable for setting the register. */
48775 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
48776 
48777 #ifndef __ASSEMBLY__
48778 /*
48779  * WARNING: The C register and register group struct declarations are provided for
48780  * convenience and illustrative purposes. They should, however, be used with
48781  * caution as the C language standard provides no guarantees about the alignment or
48782  * atomicity of device memory accesses. The recommended practice for writing
48783  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
48784  * alt_write_word() functions.
48785  *
48786  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR43_HIGH.
48787  */
48788 struct ALT_EMAC_GMAC_MAC_ADDR43_HIGH_s
48789 {
48790  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI */
48791  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR43_HIGH_RSVD_30_16 */
48792  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE */
48793 };
48794 
48795 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR43_HIGH. */
48796 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR43_HIGH_s ALT_EMAC_GMAC_MAC_ADDR43_HIGH_t;
48797 #endif /* __ASSEMBLY__ */
48798 
48799 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH register. */
48800 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_RESET 0x0000ffff
48801 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH register from the beginning of the component. */
48802 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_OFST 0x8d8
48803 /* The address of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH register. */
48804 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR43_HIGH_OFST))
48805 
48806 /*
48807  * Register : gmacgrp_mac_address43_low
48808  *
48809  * <b> Register 567 (MAC Address43 Low Register) </b>
48810  *
48811  * The MAC Address43 Low register holds the lower 32 bits of the 44th 6-byte MAC
48812  * address of the station.
48813  *
48814  * Register Layout
48815  *
48816  * Bits | Access | Reset | Description
48817  * :-------|:-------|:-----------|:------------------------------------
48818  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO
48819  *
48820  */
48821 /*
48822  * Field : addrlo
48823  *
48824  * MAC Address43 [31:0]
48825  *
48826  * This field contains the lower 32 bits of the 44th 6-byte MAC address. The
48827  * content of this field is undefined until loaded by the Application after the
48828  * initialization process.
48829  *
48830  * Field Access Macros:
48831  *
48832  */
48833 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field. */
48834 #define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_LSB 0
48835 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field. */
48836 #define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_MSB 31
48837 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field. */
48838 #define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_WIDTH 32
48839 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field value. */
48840 #define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_SET_MSK 0xffffffff
48841 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field value. */
48842 #define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_CLR_MSK 0x00000000
48843 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field. */
48844 #define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_RESET 0xffffffff
48845 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO field value from a register. */
48846 #define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
48847 /* Produces a ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field value suitable for setting the register. */
48848 #define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
48849 
48850 #ifndef __ASSEMBLY__
48851 /*
48852  * WARNING: The C register and register group struct declarations are provided for
48853  * convenience and illustrative purposes. They should, however, be used with
48854  * caution as the C language standard provides no guarantees about the alignment or
48855  * atomicity of device memory accesses. The recommended practice for writing
48856  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
48857  * alt_write_word() functions.
48858  *
48859  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR43_LOW.
48860  */
48861 struct ALT_EMAC_GMAC_MAC_ADDR43_LOW_s
48862 {
48863  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO */
48864 };
48865 
48866 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR43_LOW. */
48867 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR43_LOW_s ALT_EMAC_GMAC_MAC_ADDR43_LOW_t;
48868 #endif /* __ASSEMBLY__ */
48869 
48870 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_LOW register. */
48871 #define ALT_EMAC_GMAC_MAC_ADDR43_LOW_RESET 0xffffffff
48872 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR43_LOW register from the beginning of the component. */
48873 #define ALT_EMAC_GMAC_MAC_ADDR43_LOW_OFST 0x8dc
48874 /* The address of the ALT_EMAC_GMAC_MAC_ADDR43_LOW register. */
48875 #define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR43_LOW_OFST))
48876 
48877 /*
48878  * Register : gmacgrp_mac_address44_high
48879  *
48880  * <b> Register 568 (MAC Address44 High Register) </b>
48881  *
48882  * The MAC Address44 High register holds the upper 16 bits of the 45th 6-byte MAC
48883  * address of the station.
48884  *
48885  * If the MAC address registers are configured to be double-synchronized to the
48886  * (G)MII clock domains, then
48887  *
48888  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
48889  * or Bits[7:0] (in big-endian mode) of the MAC Address44 Low Register are written.
48890  * For proper synchronization updates, consecutive writes to this MAC Address44 Low
48891  * Register must be performed after at least four clock cycles in the destination
48892  * clock domain.
48893  *
48894  * Register Layout
48895  *
48896  * Bits | Access | Reset | Description
48897  * :--------|:-------|:-------|:-----------------------------------------
48898  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI
48899  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR44_HIGH_RSVD_30_16
48900  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE
48901  *
48902  */
48903 /*
48904  * Field : addrhi
48905  *
48906  * MAC Address44 [47:32]
48907  *
48908  * This field contains the upper 16 bits (47:32) of the 45th 6-byte MAC address.
48909  *
48910  * Field Access Macros:
48911  *
48912  */
48913 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field. */
48914 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_LSB 0
48915 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field. */
48916 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_MSB 15
48917 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field. */
48918 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_WIDTH 16
48919 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field value. */
48920 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_SET_MSK 0x0000ffff
48921 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field value. */
48922 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_CLR_MSK 0xffff0000
48923 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field. */
48924 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_RESET 0xffff
48925 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI field value from a register. */
48926 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
48927 /* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field value suitable for setting the register. */
48928 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
48929 
48930 /*
48931  * Field : reserved_30_16
48932  *
48933  * Reserved
48934  *
48935  * Field Access Macros:
48936  *
48937  */
48938 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_RSVD_30_16 register field. */
48939 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_RSVD_30_16_LSB 16
48940 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_RSVD_30_16 register field. */
48941 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_RSVD_30_16_MSB 30
48942 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_RSVD_30_16 register field. */
48943 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_RSVD_30_16_WIDTH 15
48944 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_RSVD_30_16 register field value. */
48945 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
48946 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_RSVD_30_16 register field value. */
48947 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
48948 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_RSVD_30_16 register field. */
48949 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_RSVD_30_16_RESET 0x0
48950 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_RSVD_30_16 field value from a register. */
48951 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
48952 /* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_RSVD_30_16 register field value suitable for setting the register. */
48953 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
48954 
48955 /*
48956  * Field : ae
48957  *
48958  * Address Enable
48959  *
48960  * When this bit is set, the address filter module uses the 45th MAC address for
48961  * perfect filtering.
48962  *
48963  * When this bit is reset, the address filter module ignores the address for
48964  * filtering.
48965  *
48966  * Field Enumeration Values:
48967  *
48968  * Enum | Value | Description
48969  * :----------------------------------------|:------|:------------
48970  * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_E_DISD | 0x0 |
48971  * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_E_END | 0x1 |
48972  *
48973  * Field Access Macros:
48974  *
48975  */
48976 /*
48977  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE
48978  *
48979  */
48980 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_E_DISD 0x0
48981 /*
48982  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE
48983  *
48984  */
48985 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_E_END 0x1
48986 
48987 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field. */
48988 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_LSB 31
48989 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field. */
48990 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_MSB 31
48991 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field. */
48992 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_WIDTH 1
48993 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field value. */
48994 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_SET_MSK 0x80000000
48995 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field value. */
48996 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_CLR_MSK 0x7fffffff
48997 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field. */
48998 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_RESET 0x0
48999 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE field value from a register. */
49000 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
49001 /* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field value suitable for setting the register. */
49002 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
49003 
49004 #ifndef __ASSEMBLY__
49005 /*
49006  * WARNING: The C register and register group struct declarations are provided for
49007  * convenience and illustrative purposes. They should, however, be used with
49008  * caution as the C language standard provides no guarantees about the alignment or
49009  * atomicity of device memory accesses. The recommended practice for writing
49010  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
49011  * alt_write_word() functions.
49012  *
49013  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR44_HIGH.
49014  */
49015 struct ALT_EMAC_GMAC_MAC_ADDR44_HIGH_s
49016 {
49017  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI */
49018  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR44_HIGH_RSVD_30_16 */
49019  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE */
49020 };
49021 
49022 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR44_HIGH. */
49023 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR44_HIGH_s ALT_EMAC_GMAC_MAC_ADDR44_HIGH_t;
49024 #endif /* __ASSEMBLY__ */
49025 
49026 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH register. */
49027 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_RESET 0x0000ffff
49028 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH register from the beginning of the component. */
49029 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_OFST 0x8e0
49030 /* The address of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH register. */
49031 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR44_HIGH_OFST))
49032 
49033 /*
49034  * Register : gmacgrp_mac_address44_low
49035  *
49036  * <b> Register 569 (MAC Address44 Low Register) </b>
49037  *
49038  * The MAC Address44 Low register holds the lower 32 bits of the 45th 6-byte MAC
49039  * address of the station.
49040  *
49041  * Register Layout
49042  *
49043  * Bits | Access | Reset | Description
49044  * :-------|:-------|:-----------|:------------------------------------
49045  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO
49046  *
49047  */
49048 /*
49049  * Field : addrlo
49050  *
49051  * MAC Address44 [31:0]
49052  *
49053  * This field contains the lower 32 bits of the 45th 6-byte MAC address. The
49054  * content of this field is undefined until loaded by the Application after the
49055  * initialization process.
49056  *
49057  * Field Access Macros:
49058  *
49059  */
49060 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field. */
49061 #define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_LSB 0
49062 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field. */
49063 #define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_MSB 31
49064 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field. */
49065 #define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_WIDTH 32
49066 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field value. */
49067 #define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_SET_MSK 0xffffffff
49068 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field value. */
49069 #define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_CLR_MSK 0x00000000
49070 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field. */
49071 #define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_RESET 0xffffffff
49072 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO field value from a register. */
49073 #define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
49074 /* Produces a ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field value suitable for setting the register. */
49075 #define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
49076 
49077 #ifndef __ASSEMBLY__
49078 /*
49079  * WARNING: The C register and register group struct declarations are provided for
49080  * convenience and illustrative purposes. They should, however, be used with
49081  * caution as the C language standard provides no guarantees about the alignment or
49082  * atomicity of device memory accesses. The recommended practice for writing
49083  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
49084  * alt_write_word() functions.
49085  *
49086  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR44_LOW.
49087  */
49088 struct ALT_EMAC_GMAC_MAC_ADDR44_LOW_s
49089 {
49090  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO */
49091 };
49092 
49093 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR44_LOW. */
49094 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR44_LOW_s ALT_EMAC_GMAC_MAC_ADDR44_LOW_t;
49095 #endif /* __ASSEMBLY__ */
49096 
49097 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_LOW register. */
49098 #define ALT_EMAC_GMAC_MAC_ADDR44_LOW_RESET 0xffffffff
49099 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR44_LOW register from the beginning of the component. */
49100 #define ALT_EMAC_GMAC_MAC_ADDR44_LOW_OFST 0x8e4
49101 /* The address of the ALT_EMAC_GMAC_MAC_ADDR44_LOW register. */
49102 #define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR44_LOW_OFST))
49103 
49104 /*
49105  * Register : gmacgrp_mac_address45_high
49106  *
49107  * <b> Register 570 (MAC Address45 High Register) </b>
49108  *
49109  * The MAC Address45 High register holds the upper 16 bits of the 46th 6-byte MAC
49110  * address of the station.
49111  *
49112  * If the MAC address registers are configured to be double-synchronized to the
49113  * (G)MII clock domains, then
49114  *
49115  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
49116  * or Bits[7:0] (in big-endian mode) of the MAC Address45 Low Register are written.
49117  * For proper synchronization updates, consecutive writes to this MAC Address45 Low
49118  * Register must be performed after at least four clock cycles in the destination
49119  * clock domain.
49120  *
49121  * Register Layout
49122  *
49123  * Bits | Access | Reset | Description
49124  * :--------|:-------|:-------|:-----------------------------------------
49125  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI
49126  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR45_HIGH_RSVD_30_16
49127  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE
49128  *
49129  */
49130 /*
49131  * Field : addrhi
49132  *
49133  * MAC Address45 [47:32]
49134  *
49135  * This field contains the upper 16 bits (47:32) of the 46th 6-byte MAC address.
49136  *
49137  * Field Access Macros:
49138  *
49139  */
49140 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field. */
49141 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_LSB 0
49142 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field. */
49143 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_MSB 15
49144 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field. */
49145 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_WIDTH 16
49146 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field value. */
49147 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_SET_MSK 0x0000ffff
49148 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field value. */
49149 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_CLR_MSK 0xffff0000
49150 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field. */
49151 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_RESET 0xffff
49152 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI field value from a register. */
49153 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
49154 /* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field value suitable for setting the register. */
49155 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
49156 
49157 /*
49158  * Field : reserved_30_16
49159  *
49160  * Reserved
49161  *
49162  * Field Access Macros:
49163  *
49164  */
49165 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_RSVD_30_16 register field. */
49166 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_RSVD_30_16_LSB 16
49167 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_RSVD_30_16 register field. */
49168 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_RSVD_30_16_MSB 30
49169 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_RSVD_30_16 register field. */
49170 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_RSVD_30_16_WIDTH 15
49171 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_RSVD_30_16 register field value. */
49172 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
49173 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_RSVD_30_16 register field value. */
49174 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
49175 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_RSVD_30_16 register field. */
49176 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_RSVD_30_16_RESET 0x0
49177 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_RSVD_30_16 field value from a register. */
49178 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
49179 /* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_RSVD_30_16 register field value suitable for setting the register. */
49180 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
49181 
49182 /*
49183  * Field : ae
49184  *
49185  * Address Enable
49186  *
49187  * When this bit is set, the address filter module uses the 46th MAC address for
49188  * perfect filtering.
49189  *
49190  * When this bit is reset, the address filter module ignores the address for
49191  * filtering.
49192  *
49193  * Field Enumeration Values:
49194  *
49195  * Enum | Value | Description
49196  * :----------------------------------------|:------|:------------
49197  * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_E_DISD | 0x0 |
49198  * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_E_END | 0x1 |
49199  *
49200  * Field Access Macros:
49201  *
49202  */
49203 /*
49204  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE
49205  *
49206  */
49207 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_E_DISD 0x0
49208 /*
49209  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE
49210  *
49211  */
49212 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_E_END 0x1
49213 
49214 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field. */
49215 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_LSB 31
49216 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field. */
49217 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_MSB 31
49218 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field. */
49219 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_WIDTH 1
49220 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field value. */
49221 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_SET_MSK 0x80000000
49222 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field value. */
49223 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_CLR_MSK 0x7fffffff
49224 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field. */
49225 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_RESET 0x0
49226 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE field value from a register. */
49227 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
49228 /* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field value suitable for setting the register. */
49229 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
49230 
49231 #ifndef __ASSEMBLY__
49232 /*
49233  * WARNING: The C register and register group struct declarations are provided for
49234  * convenience and illustrative purposes. They should, however, be used with
49235  * caution as the C language standard provides no guarantees about the alignment or
49236  * atomicity of device memory accesses. The recommended practice for writing
49237  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
49238  * alt_write_word() functions.
49239  *
49240  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR45_HIGH.
49241  */
49242 struct ALT_EMAC_GMAC_MAC_ADDR45_HIGH_s
49243 {
49244  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI */
49245  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR45_HIGH_RSVD_30_16 */
49246  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE */
49247 };
49248 
49249 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR45_HIGH. */
49250 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR45_HIGH_s ALT_EMAC_GMAC_MAC_ADDR45_HIGH_t;
49251 #endif /* __ASSEMBLY__ */
49252 
49253 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH register. */
49254 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_RESET 0x0000ffff
49255 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH register from the beginning of the component. */
49256 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_OFST 0x8e8
49257 /* The address of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH register. */
49258 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR45_HIGH_OFST))
49259 
49260 /*
49261  * Register : gmacgrp_mac_address45_low
49262  *
49263  * <b> Register 571 (MAC Address45 Low Register) </b>
49264  *
49265  * The MAC Address45 Low register holds the lower 32 bits of the 46th 6-byte MAC
49266  * address of the station.
49267  *
49268  * Register Layout
49269  *
49270  * Bits | Access | Reset | Description
49271  * :-------|:-------|:-----------|:------------------------------------
49272  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO
49273  *
49274  */
49275 /*
49276  * Field : addrlo
49277  *
49278  * MAC Address45 [31:0]
49279  *
49280  * This field contains the lower 32 bits of the 46th 6-byte MAC address. The
49281  * content of this field is undefined until loaded by the Application after the
49282  * initialization process.
49283  *
49284  * Field Access Macros:
49285  *
49286  */
49287 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field. */
49288 #define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_LSB 0
49289 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field. */
49290 #define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_MSB 31
49291 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field. */
49292 #define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_WIDTH 32
49293 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field value. */
49294 #define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_SET_MSK 0xffffffff
49295 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field value. */
49296 #define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_CLR_MSK 0x00000000
49297 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field. */
49298 #define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_RESET 0xffffffff
49299 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO field value from a register. */
49300 #define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
49301 /* Produces a ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field value suitable for setting the register. */
49302 #define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
49303 
49304 #ifndef __ASSEMBLY__
49305 /*
49306  * WARNING: The C register and register group struct declarations are provided for
49307  * convenience and illustrative purposes. They should, however, be used with
49308  * caution as the C language standard provides no guarantees about the alignment or
49309  * atomicity of device memory accesses. The recommended practice for writing
49310  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
49311  * alt_write_word() functions.
49312  *
49313  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR45_LOW.
49314  */
49315 struct ALT_EMAC_GMAC_MAC_ADDR45_LOW_s
49316 {
49317  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO */
49318 };
49319 
49320 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR45_LOW. */
49321 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR45_LOW_s ALT_EMAC_GMAC_MAC_ADDR45_LOW_t;
49322 #endif /* __ASSEMBLY__ */
49323 
49324 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_LOW register. */
49325 #define ALT_EMAC_GMAC_MAC_ADDR45_LOW_RESET 0xffffffff
49326 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR45_LOW register from the beginning of the component. */
49327 #define ALT_EMAC_GMAC_MAC_ADDR45_LOW_OFST 0x8ec
49328 /* The address of the ALT_EMAC_GMAC_MAC_ADDR45_LOW register. */
49329 #define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR45_LOW_OFST))
49330 
49331 /*
49332  * Register : gmacgrp_mac_address46_high
49333  *
49334  * <b> Register 572 (MAC Address46 High Register) </b>
49335  *
49336  * The MAC Address46 High register holds the upper 16 bits of the 47th 6-byte MAC
49337  * address of the station.
49338  *
49339  * If the MAC address registers are configured to be double-synchronized to the
49340  * (G)MII clock domains, then
49341  *
49342  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
49343  * or Bits[7:0] (in big-endian mode) of the MAC Address46 Low Register are written.
49344  * For proper synchronization updates, consecutive writes to this MAC Address46 Low
49345  * Register must be performed after at least four clock cycles in the destination
49346  * clock domain.
49347  *
49348  * Register Layout
49349  *
49350  * Bits | Access | Reset | Description
49351  * :--------|:-------|:-------|:-----------------------------------------
49352  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI
49353  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR46_HIGH_RSVD_30_16
49354  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE
49355  *
49356  */
49357 /*
49358  * Field : addrhi
49359  *
49360  * MAC Address46 [47:32]
49361  *
49362  * This field contains the upper 16 bits (47:32) of the 47th 6-byte MAC address.
49363  *
49364  * Field Access Macros:
49365  *
49366  */
49367 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field. */
49368 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_LSB 0
49369 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field. */
49370 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_MSB 15
49371 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field. */
49372 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_WIDTH 16
49373 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field value. */
49374 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_SET_MSK 0x0000ffff
49375 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field value. */
49376 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_CLR_MSK 0xffff0000
49377 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field. */
49378 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_RESET 0xffff
49379 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI field value from a register. */
49380 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
49381 /* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field value suitable for setting the register. */
49382 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
49383 
49384 /*
49385  * Field : reserved_30_16
49386  *
49387  * Reserved
49388  *
49389  * Field Access Macros:
49390  *
49391  */
49392 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_RSVD_30_16 register field. */
49393 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_RSVD_30_16_LSB 16
49394 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_RSVD_30_16 register field. */
49395 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_RSVD_30_16_MSB 30
49396 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_RSVD_30_16 register field. */
49397 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_RSVD_30_16_WIDTH 15
49398 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_RSVD_30_16 register field value. */
49399 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
49400 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_RSVD_30_16 register field value. */
49401 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
49402 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_RSVD_30_16 register field. */
49403 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_RSVD_30_16_RESET 0x0
49404 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_RSVD_30_16 field value from a register. */
49405 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
49406 /* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_RSVD_30_16 register field value suitable for setting the register. */
49407 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
49408 
49409 /*
49410  * Field : ae
49411  *
49412  * Address Enable
49413  *
49414  * When this bit is set, the address filter module uses the 47th MAC address for
49415  * perfect filtering.
49416  *
49417  * When this bit is reset, the address filter module ignores the address for
49418  * filtering.
49419  *
49420  * Field Enumeration Values:
49421  *
49422  * Enum | Value | Description
49423  * :----------------------------------------|:------|:------------
49424  * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_E_DISD | 0x0 |
49425  * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_E_END | 0x1 |
49426  *
49427  * Field Access Macros:
49428  *
49429  */
49430 /*
49431  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE
49432  *
49433  */
49434 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_E_DISD 0x0
49435 /*
49436  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE
49437  *
49438  */
49439 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_E_END 0x1
49440 
49441 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field. */
49442 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_LSB 31
49443 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field. */
49444 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_MSB 31
49445 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field. */
49446 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_WIDTH 1
49447 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field value. */
49448 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_SET_MSK 0x80000000
49449 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field value. */
49450 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_CLR_MSK 0x7fffffff
49451 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field. */
49452 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_RESET 0x0
49453 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE field value from a register. */
49454 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
49455 /* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field value suitable for setting the register. */
49456 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
49457 
49458 #ifndef __ASSEMBLY__
49459 /*
49460  * WARNING: The C register and register group struct declarations are provided for
49461  * convenience and illustrative purposes. They should, however, be used with
49462  * caution as the C language standard provides no guarantees about the alignment or
49463  * atomicity of device memory accesses. The recommended practice for writing
49464  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
49465  * alt_write_word() functions.
49466  *
49467  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR46_HIGH.
49468  */
49469 struct ALT_EMAC_GMAC_MAC_ADDR46_HIGH_s
49470 {
49471  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI */
49472  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR46_HIGH_RSVD_30_16 */
49473  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE */
49474 };
49475 
49476 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR46_HIGH. */
49477 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR46_HIGH_s ALT_EMAC_GMAC_MAC_ADDR46_HIGH_t;
49478 #endif /* __ASSEMBLY__ */
49479 
49480 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH register. */
49481 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_RESET 0x0000ffff
49482 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH register from the beginning of the component. */
49483 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_OFST 0x8f0
49484 /* The address of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH register. */
49485 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR46_HIGH_OFST))
49486 
49487 /*
49488  * Register : gmacgrp_mac_address46_low
49489  *
49490  * <b> Register 573 (MAC Address46 Low Register) </b>
49491  *
49492  * The MAC Address46 Low register holds the lower 32 bits of the 47th 6-byte MAC
49493  * address of the station.
49494  *
49495  * Register Layout
49496  *
49497  * Bits | Access | Reset | Description
49498  * :-------|:-------|:-----------|:------------------------------------
49499  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO
49500  *
49501  */
49502 /*
49503  * Field : addrlo
49504  *
49505  * MAC Address46 [31:0]
49506  *
49507  * This field contains the lower 32 bits of the 47th 6-byte MAC address. The
49508  * content of this field is undefined until loaded by the Application after the
49509  * initialization process.
49510  *
49511  * Field Access Macros:
49512  *
49513  */
49514 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field. */
49515 #define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_LSB 0
49516 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field. */
49517 #define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_MSB 31
49518 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field. */
49519 #define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_WIDTH 32
49520 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field value. */
49521 #define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_SET_MSK 0xffffffff
49522 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field value. */
49523 #define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_CLR_MSK 0x00000000
49524 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field. */
49525 #define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_RESET 0xffffffff
49526 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO field value from a register. */
49527 #define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
49528 /* Produces a ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field value suitable for setting the register. */
49529 #define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
49530 
49531 #ifndef __ASSEMBLY__
49532 /*
49533  * WARNING: The C register and register group struct declarations are provided for
49534  * convenience and illustrative purposes. They should, however, be used with
49535  * caution as the C language standard provides no guarantees about the alignment or
49536  * atomicity of device memory accesses. The recommended practice for writing
49537  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
49538  * alt_write_word() functions.
49539  *
49540  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR46_LOW.
49541  */
49542 struct ALT_EMAC_GMAC_MAC_ADDR46_LOW_s
49543 {
49544  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO */
49545 };
49546 
49547 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR46_LOW. */
49548 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR46_LOW_s ALT_EMAC_GMAC_MAC_ADDR46_LOW_t;
49549 #endif /* __ASSEMBLY__ */
49550 
49551 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_LOW register. */
49552 #define ALT_EMAC_GMAC_MAC_ADDR46_LOW_RESET 0xffffffff
49553 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR46_LOW register from the beginning of the component. */
49554 #define ALT_EMAC_GMAC_MAC_ADDR46_LOW_OFST 0x8f4
49555 /* The address of the ALT_EMAC_GMAC_MAC_ADDR46_LOW register. */
49556 #define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR46_LOW_OFST))
49557 
49558 /*
49559  * Register : gmacgrp_mac_address47_high
49560  *
49561  * <b> Register 574 (MAC Address47 High Register) </b>
49562  *
49563  * The MAC Address47 High register holds the upper 16 bits of the 48th 6-byte MAC
49564  * address of the station.
49565  *
49566  * If the MAC address registers are configured to be double-synchronized to the
49567  * (G)MII clock domains, then
49568  *
49569  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
49570  * or Bits[7:0] (in big-endian mode) of the MAC Address47 Low Register are written.
49571  * For proper synchronization updates, consecutive writes to this MAC Address47 Low
49572  * Register must be performed after at least four clock cycles in the destination
49573  * clock domain.
49574  *
49575  * Register Layout
49576  *
49577  * Bits | Access | Reset | Description
49578  * :--------|:-------|:-------|:-----------------------------------------
49579  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI
49580  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR47_HIGH_RSVD_30_16
49581  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE
49582  *
49583  */
49584 /*
49585  * Field : addrhi
49586  *
49587  * MAC Address47 [47:32]
49588  *
49589  * This field contains the upper 16 bits (47:32) of the 48th 6-byte MAC address.
49590  *
49591  * Field Access Macros:
49592  *
49593  */
49594 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field. */
49595 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_LSB 0
49596 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field. */
49597 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_MSB 15
49598 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field. */
49599 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_WIDTH 16
49600 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field value. */
49601 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_SET_MSK 0x0000ffff
49602 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field value. */
49603 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_CLR_MSK 0xffff0000
49604 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field. */
49605 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_RESET 0xffff
49606 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI field value from a register. */
49607 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
49608 /* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field value suitable for setting the register. */
49609 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
49610 
49611 /*
49612  * Field : reserved_30_16
49613  *
49614  * Reserved
49615  *
49616  * Field Access Macros:
49617  *
49618  */
49619 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_RSVD_30_16 register field. */
49620 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_RSVD_30_16_LSB 16
49621 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_RSVD_30_16 register field. */
49622 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_RSVD_30_16_MSB 30
49623 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_RSVD_30_16 register field. */
49624 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_RSVD_30_16_WIDTH 15
49625 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_RSVD_30_16 register field value. */
49626 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
49627 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_RSVD_30_16 register field value. */
49628 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
49629 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_RSVD_30_16 register field. */
49630 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_RSVD_30_16_RESET 0x0
49631 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_RSVD_30_16 field value from a register. */
49632 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
49633 /* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_RSVD_30_16 register field value suitable for setting the register. */
49634 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
49635 
49636 /*
49637  * Field : ae
49638  *
49639  * Address Enable
49640  *
49641  * When this bit is set, the address filter module uses the 48th MAC address for
49642  * perfect filtering.
49643  *
49644  * When this bit is reset, the address filter module ignores the address for
49645  * filtering.
49646  *
49647  * Field Enumeration Values:
49648  *
49649  * Enum | Value | Description
49650  * :----------------------------------------|:------|:------------
49651  * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_E_DISD | 0x0 |
49652  * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_E_END | 0x1 |
49653  *
49654  * Field Access Macros:
49655  *
49656  */
49657 /*
49658  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE
49659  *
49660  */
49661 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_E_DISD 0x0
49662 /*
49663  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE
49664  *
49665  */
49666 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_E_END 0x1
49667 
49668 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field. */
49669 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_LSB 31
49670 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field. */
49671 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_MSB 31
49672 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field. */
49673 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_WIDTH 1
49674 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field value. */
49675 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_SET_MSK 0x80000000
49676 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field value. */
49677 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_CLR_MSK 0x7fffffff
49678 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field. */
49679 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_RESET 0x0
49680 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE field value from a register. */
49681 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
49682 /* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field value suitable for setting the register. */
49683 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
49684 
49685 #ifndef __ASSEMBLY__
49686 /*
49687  * WARNING: The C register and register group struct declarations are provided for
49688  * convenience and illustrative purposes. They should, however, be used with
49689  * caution as the C language standard provides no guarantees about the alignment or
49690  * atomicity of device memory accesses. The recommended practice for writing
49691  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
49692  * alt_write_word() functions.
49693  *
49694  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR47_HIGH.
49695  */
49696 struct ALT_EMAC_GMAC_MAC_ADDR47_HIGH_s
49697 {
49698  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI */
49699  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR47_HIGH_RSVD_30_16 */
49700  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE */
49701 };
49702 
49703 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR47_HIGH. */
49704 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR47_HIGH_s ALT_EMAC_GMAC_MAC_ADDR47_HIGH_t;
49705 #endif /* __ASSEMBLY__ */
49706 
49707 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH register. */
49708 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_RESET 0x0000ffff
49709 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH register from the beginning of the component. */
49710 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_OFST 0x8f8
49711 /* The address of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH register. */
49712 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR47_HIGH_OFST))
49713 
49714 /*
49715  * Register : gmacgrp_mac_address47_low
49716  *
49717  * <b> Register 575 (MAC Address47 Low Register) </b>
49718  *
49719  * The MAC Address47 Low register holds the lower 32 bits of the 48th 6-byte MAC
49720  * address of the station.
49721  *
49722  * Register Layout
49723  *
49724  * Bits | Access | Reset | Description
49725  * :-------|:-------|:-----------|:------------------------------------
49726  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO
49727  *
49728  */
49729 /*
49730  * Field : addrlo
49731  *
49732  * MAC Address47 [31:0]
49733  *
49734  * This field contains the lower 32 bits of the 48th 6-byte MAC address. The
49735  * content of this field is undefined until loaded by the Application after the
49736  * initialization process.
49737  *
49738  * Field Access Macros:
49739  *
49740  */
49741 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field. */
49742 #define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_LSB 0
49743 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field. */
49744 #define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_MSB 31
49745 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field. */
49746 #define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_WIDTH 32
49747 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field value. */
49748 #define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_SET_MSK 0xffffffff
49749 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field value. */
49750 #define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_CLR_MSK 0x00000000
49751 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field. */
49752 #define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_RESET 0xffffffff
49753 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO field value from a register. */
49754 #define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
49755 /* Produces a ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field value suitable for setting the register. */
49756 #define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
49757 
49758 #ifndef __ASSEMBLY__
49759 /*
49760  * WARNING: The C register and register group struct declarations are provided for
49761  * convenience and illustrative purposes. They should, however, be used with
49762  * caution as the C language standard provides no guarantees about the alignment or
49763  * atomicity of device memory accesses. The recommended practice for writing
49764  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
49765  * alt_write_word() functions.
49766  *
49767  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR47_LOW.
49768  */
49769 struct ALT_EMAC_GMAC_MAC_ADDR47_LOW_s
49770 {
49771  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO */
49772 };
49773 
49774 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR47_LOW. */
49775 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR47_LOW_s ALT_EMAC_GMAC_MAC_ADDR47_LOW_t;
49776 #endif /* __ASSEMBLY__ */
49777 
49778 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_LOW register. */
49779 #define ALT_EMAC_GMAC_MAC_ADDR47_LOW_RESET 0xffffffff
49780 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR47_LOW register from the beginning of the component. */
49781 #define ALT_EMAC_GMAC_MAC_ADDR47_LOW_OFST 0x8fc
49782 /* The address of the ALT_EMAC_GMAC_MAC_ADDR47_LOW register. */
49783 #define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR47_LOW_OFST))
49784 
49785 /*
49786  * Register : gmacgrp_mac_address48_high
49787  *
49788  * <b> Register 576 (MAC Address48 High Register) </b>
49789  *
49790  * The MAC Address48 High register holds the upper 16 bits of the 49th 6-byte MAC
49791  * address of the station.
49792  *
49793  * If the MAC address registers are configured to be double-synchronized to the
49794  * (G)MII clock domains, then
49795  *
49796  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
49797  * or Bits[7:0] (in big-endian mode) of the MAC Address48 Low Register are written.
49798  * For proper synchronization updates, consecutive writes to this MAC Address48 Low
49799  * Register must be performed after at least four clock cycles in the destination
49800  * clock domain.
49801  *
49802  * Register Layout
49803  *
49804  * Bits | Access | Reset | Description
49805  * :--------|:-------|:-------|:-----------------------------------------
49806  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI
49807  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR48_HIGH_RSVD_30_16
49808  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE
49809  *
49810  */
49811 /*
49812  * Field : addrhi
49813  *
49814  * MAC Address48 [47:32]
49815  *
49816  * This field contains the upper 16 bits (47:32) of the 49th 6-byte MAC address.
49817  *
49818  * Field Access Macros:
49819  *
49820  */
49821 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field. */
49822 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_LSB 0
49823 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field. */
49824 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_MSB 15
49825 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field. */
49826 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_WIDTH 16
49827 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field value. */
49828 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_SET_MSK 0x0000ffff
49829 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field value. */
49830 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_CLR_MSK 0xffff0000
49831 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field. */
49832 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_RESET 0xffff
49833 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI field value from a register. */
49834 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
49835 /* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field value suitable for setting the register. */
49836 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
49837 
49838 /*
49839  * Field : reserved_30_16
49840  *
49841  * Reserved
49842  *
49843  * Field Access Macros:
49844  *
49845  */
49846 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_RSVD_30_16 register field. */
49847 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_RSVD_30_16_LSB 16
49848 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_RSVD_30_16 register field. */
49849 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_RSVD_30_16_MSB 30
49850 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_RSVD_30_16 register field. */
49851 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_RSVD_30_16_WIDTH 15
49852 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_RSVD_30_16 register field value. */
49853 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
49854 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_RSVD_30_16 register field value. */
49855 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
49856 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_RSVD_30_16 register field. */
49857 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_RSVD_30_16_RESET 0x0
49858 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_RSVD_30_16 field value from a register. */
49859 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
49860 /* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_RSVD_30_16 register field value suitable for setting the register. */
49861 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
49862 
49863 /*
49864  * Field : ae
49865  *
49866  * Address Enable
49867  *
49868  * When this bit is set, the address filter module uses the 49th MAC address for
49869  * perfect filtering.
49870  *
49871  * When this bit is reset, the address filter module ignores the address for
49872  * filtering.
49873  *
49874  * Field Enumeration Values:
49875  *
49876  * Enum | Value | Description
49877  * :----------------------------------------|:------|:------------
49878  * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_E_DISD | 0x0 |
49879  * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_E_END | 0x1 |
49880  *
49881  * Field Access Macros:
49882  *
49883  */
49884 /*
49885  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE
49886  *
49887  */
49888 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_E_DISD 0x0
49889 /*
49890  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE
49891  *
49892  */
49893 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_E_END 0x1
49894 
49895 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field. */
49896 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_LSB 31
49897 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field. */
49898 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_MSB 31
49899 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field. */
49900 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_WIDTH 1
49901 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field value. */
49902 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_SET_MSK 0x80000000
49903 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field value. */
49904 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_CLR_MSK 0x7fffffff
49905 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field. */
49906 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_RESET 0x0
49907 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE field value from a register. */
49908 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
49909 /* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field value suitable for setting the register. */
49910 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
49911 
49912 #ifndef __ASSEMBLY__
49913 /*
49914  * WARNING: The C register and register group struct declarations are provided for
49915  * convenience and illustrative purposes. They should, however, be used with
49916  * caution as the C language standard provides no guarantees about the alignment or
49917  * atomicity of device memory accesses. The recommended practice for writing
49918  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
49919  * alt_write_word() functions.
49920  *
49921  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR48_HIGH.
49922  */
49923 struct ALT_EMAC_GMAC_MAC_ADDR48_HIGH_s
49924 {
49925  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI */
49926  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR48_HIGH_RSVD_30_16 */
49927  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE */
49928 };
49929 
49930 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR48_HIGH. */
49931 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR48_HIGH_s ALT_EMAC_GMAC_MAC_ADDR48_HIGH_t;
49932 #endif /* __ASSEMBLY__ */
49933 
49934 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH register. */
49935 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_RESET 0x0000ffff
49936 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH register from the beginning of the component. */
49937 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_OFST 0x900
49938 /* The address of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH register. */
49939 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR48_HIGH_OFST))
49940 
49941 /*
49942  * Register : gmacgrp_mac_address48_low
49943  *
49944  * <b> Register 577 (MAC Address48 Low Register) </b>
49945  *
49946  * The MAC Address48 Low register holds the lower 32 bits of the 49th 6-byte MAC
49947  * address of the station.
49948  *
49949  * Register Layout
49950  *
49951  * Bits | Access | Reset | Description
49952  * :-------|:-------|:-----------|:------------------------------------
49953  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO
49954  *
49955  */
49956 /*
49957  * Field : addrlo
49958  *
49959  * MAC Address48 [31:0]
49960  *
49961  * This field contains the lower 32 bits of the 49th 6-byte MAC address. The
49962  * content of this field is undefined until loaded by the Application after the
49963  * initialization process.
49964  *
49965  * Field Access Macros:
49966  *
49967  */
49968 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field. */
49969 #define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_LSB 0
49970 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field. */
49971 #define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_MSB 31
49972 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field. */
49973 #define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_WIDTH 32
49974 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field value. */
49975 #define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_SET_MSK 0xffffffff
49976 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field value. */
49977 #define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_CLR_MSK 0x00000000
49978 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field. */
49979 #define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_RESET 0xffffffff
49980 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO field value from a register. */
49981 #define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
49982 /* Produces a ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field value suitable for setting the register. */
49983 #define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
49984 
49985 #ifndef __ASSEMBLY__
49986 /*
49987  * WARNING: The C register and register group struct declarations are provided for
49988  * convenience and illustrative purposes. They should, however, be used with
49989  * caution as the C language standard provides no guarantees about the alignment or
49990  * atomicity of device memory accesses. The recommended practice for writing
49991  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
49992  * alt_write_word() functions.
49993  *
49994  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR48_LOW.
49995  */
49996 struct ALT_EMAC_GMAC_MAC_ADDR48_LOW_s
49997 {
49998  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO */
49999 };
50000 
50001 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR48_LOW. */
50002 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR48_LOW_s ALT_EMAC_GMAC_MAC_ADDR48_LOW_t;
50003 #endif /* __ASSEMBLY__ */
50004 
50005 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_LOW register. */
50006 #define ALT_EMAC_GMAC_MAC_ADDR48_LOW_RESET 0xffffffff
50007 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR48_LOW register from the beginning of the component. */
50008 #define ALT_EMAC_GMAC_MAC_ADDR48_LOW_OFST 0x904
50009 /* The address of the ALT_EMAC_GMAC_MAC_ADDR48_LOW register. */
50010 #define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR48_LOW_OFST))
50011 
50012 /*
50013  * Register : gmacgrp_mac_address49_high
50014  *
50015  * <b> Register 578 (MAC Address49 High Register) </b>
50016  *
50017  * The MAC Address49 High register holds the upper 16 bits of the 50th 6-byte MAC
50018  * address of the station.
50019  *
50020  * If the MAC address registers are configured to be double-synchronized to the
50021  * (G)MII clock domains, then
50022  *
50023  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
50024  * or Bits[7:0] (in big-endian mode) of the MAC Address49 Low Register are written.
50025  * For proper synchronization updates, consecutive writes to this MAC Address49 Low
50026  * Register must be performed after at least four clock cycles in the destination
50027  * clock domain.
50028  *
50029  * Register Layout
50030  *
50031  * Bits | Access | Reset | Description
50032  * :--------|:-------|:-------|:-----------------------------------------
50033  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI
50034  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR49_HIGH_RSVD_30_16
50035  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE
50036  *
50037  */
50038 /*
50039  * Field : addrhi
50040  *
50041  * MAC Address49 [47:32]
50042  *
50043  * This field contains the upper 16 bits (47:32) of the 50th 6-byte MAC address.
50044  *
50045  * Field Access Macros:
50046  *
50047  */
50048 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field. */
50049 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_LSB 0
50050 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field. */
50051 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_MSB 15
50052 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field. */
50053 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_WIDTH 16
50054 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field value. */
50055 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_SET_MSK 0x0000ffff
50056 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field value. */
50057 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_CLR_MSK 0xffff0000
50058 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field. */
50059 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_RESET 0xffff
50060 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI field value from a register. */
50061 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
50062 /* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field value suitable for setting the register. */
50063 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
50064 
50065 /*
50066  * Field : reserved_30_16
50067  *
50068  * Reserved
50069  *
50070  * Field Access Macros:
50071  *
50072  */
50073 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_RSVD_30_16 register field. */
50074 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_RSVD_30_16_LSB 16
50075 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_RSVD_30_16 register field. */
50076 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_RSVD_30_16_MSB 30
50077 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_RSVD_30_16 register field. */
50078 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_RSVD_30_16_WIDTH 15
50079 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_RSVD_30_16 register field value. */
50080 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
50081 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_RSVD_30_16 register field value. */
50082 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
50083 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_RSVD_30_16 register field. */
50084 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_RSVD_30_16_RESET 0x0
50085 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_RSVD_30_16 field value from a register. */
50086 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
50087 /* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_RSVD_30_16 register field value suitable for setting the register. */
50088 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
50089 
50090 /*
50091  * Field : ae
50092  *
50093  * Address Enable
50094  *
50095  * When this bit is set, the address filter module uses the 50th MAC address for
50096  * perfect filtering.
50097  *
50098  * When this bit is reset, the address filter module ignores the address for
50099  * filtering.
50100  *
50101  * Field Enumeration Values:
50102  *
50103  * Enum | Value | Description
50104  * :----------------------------------------|:------|:------------
50105  * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_E_DISD | 0x0 |
50106  * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_E_END | 0x1 |
50107  *
50108  * Field Access Macros:
50109  *
50110  */
50111 /*
50112  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE
50113  *
50114  */
50115 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_E_DISD 0x0
50116 /*
50117  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE
50118  *
50119  */
50120 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_E_END 0x1
50121 
50122 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field. */
50123 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_LSB 31
50124 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field. */
50125 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_MSB 31
50126 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field. */
50127 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_WIDTH 1
50128 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field value. */
50129 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_SET_MSK 0x80000000
50130 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field value. */
50131 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_CLR_MSK 0x7fffffff
50132 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field. */
50133 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_RESET 0x0
50134 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE field value from a register. */
50135 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
50136 /* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field value suitable for setting the register. */
50137 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
50138 
50139 #ifndef __ASSEMBLY__
50140 /*
50141  * WARNING: The C register and register group struct declarations are provided for
50142  * convenience and illustrative purposes. They should, however, be used with
50143  * caution as the C language standard provides no guarantees about the alignment or
50144  * atomicity of device memory accesses. The recommended practice for writing
50145  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
50146  * alt_write_word() functions.
50147  *
50148  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR49_HIGH.
50149  */
50150 struct ALT_EMAC_GMAC_MAC_ADDR49_HIGH_s
50151 {
50152  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI */
50153  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR49_HIGH_RSVD_30_16 */
50154  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE */
50155 };
50156 
50157 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR49_HIGH. */
50158 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR49_HIGH_s ALT_EMAC_GMAC_MAC_ADDR49_HIGH_t;
50159 #endif /* __ASSEMBLY__ */
50160 
50161 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH register. */
50162 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_RESET 0x0000ffff
50163 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH register from the beginning of the component. */
50164 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_OFST 0x908
50165 /* The address of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH register. */
50166 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR49_HIGH_OFST))
50167 
50168 /*
50169  * Register : gmacgrp_mac_address49_low
50170  *
50171  * <b> Register 579 (MAC Address49 Low Register) </b>
50172  *
50173  * The MAC Address49 Low register holds the lower 32 bits of the 50th 6-byte MAC
50174  * address of the station.
50175  *
50176  * Register Layout
50177  *
50178  * Bits | Access | Reset | Description
50179  * :-------|:-------|:-----------|:------------------------------------
50180  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO
50181  *
50182  */
50183 /*
50184  * Field : addrlo
50185  *
50186  * MAC Address49 [31:0]
50187  *
50188  * This field contains the lower 32 bits of the 50th 6-byte MAC address. The
50189  * content of this field is undefined until loaded by the Application after the
50190  * initialization process.
50191  *
50192  * Field Access Macros:
50193  *
50194  */
50195 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field. */
50196 #define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_LSB 0
50197 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field. */
50198 #define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_MSB 31
50199 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field. */
50200 #define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_WIDTH 32
50201 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field value. */
50202 #define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_SET_MSK 0xffffffff
50203 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field value. */
50204 #define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_CLR_MSK 0x00000000
50205 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field. */
50206 #define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_RESET 0xffffffff
50207 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO field value from a register. */
50208 #define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
50209 /* Produces a ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field value suitable for setting the register. */
50210 #define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
50211 
50212 #ifndef __ASSEMBLY__
50213 /*
50214  * WARNING: The C register and register group struct declarations are provided for
50215  * convenience and illustrative purposes. They should, however, be used with
50216  * caution as the C language standard provides no guarantees about the alignment or
50217  * atomicity of device memory accesses. The recommended practice for writing
50218  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
50219  * alt_write_word() functions.
50220  *
50221  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR49_LOW.
50222  */
50223 struct ALT_EMAC_GMAC_MAC_ADDR49_LOW_s
50224 {
50225  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO */
50226 };
50227 
50228 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR49_LOW. */
50229 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR49_LOW_s ALT_EMAC_GMAC_MAC_ADDR49_LOW_t;
50230 #endif /* __ASSEMBLY__ */
50231 
50232 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_LOW register. */
50233 #define ALT_EMAC_GMAC_MAC_ADDR49_LOW_RESET 0xffffffff
50234 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR49_LOW register from the beginning of the component. */
50235 #define ALT_EMAC_GMAC_MAC_ADDR49_LOW_OFST 0x90c
50236 /* The address of the ALT_EMAC_GMAC_MAC_ADDR49_LOW register. */
50237 #define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR49_LOW_OFST))
50238 
50239 /*
50240  * Register : gmacgrp_mac_address50_high
50241  *
50242  * <b> Register 580 (MAC Address50 High Register) </b>
50243  *
50244  * The MAC Address50 High register holds the upper 16 bits of the 51st 6-byte MAC
50245  * address of the station.
50246  *
50247  * If the MAC address registers are configured to be double-synchronized to the
50248  * (G)MII clock domains, then
50249  *
50250  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
50251  * or Bits[7:0] (in big-endian mode) of the MAC Address50 Low Register are written.
50252  * For proper synchronization updates, consecutive writes to this MAC Address50 Low
50253  * Register must be performed after at least four clock cycles in the destination
50254  * clock domain.
50255  *
50256  * Register Layout
50257  *
50258  * Bits | Access | Reset | Description
50259  * :--------|:-------|:-------|:-----------------------------------------
50260  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI
50261  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR50_HIGH_RSVD_30_16
50262  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE
50263  *
50264  */
50265 /*
50266  * Field : addrhi
50267  *
50268  * MAC Address50 [47:32]
50269  *
50270  * This field contains the upper 16 bits (47:32) of the 51st 6-byte MAC address.
50271  *
50272  * Field Access Macros:
50273  *
50274  */
50275 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field. */
50276 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_LSB 0
50277 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field. */
50278 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_MSB 15
50279 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field. */
50280 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_WIDTH 16
50281 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field value. */
50282 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_SET_MSK 0x0000ffff
50283 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field value. */
50284 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_CLR_MSK 0xffff0000
50285 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field. */
50286 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_RESET 0xffff
50287 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI field value from a register. */
50288 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
50289 /* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field value suitable for setting the register. */
50290 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
50291 
50292 /*
50293  * Field : reserved_30_16
50294  *
50295  * Reserved
50296  *
50297  * Field Access Macros:
50298  *
50299  */
50300 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_RSVD_30_16 register field. */
50301 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_RSVD_30_16_LSB 16
50302 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_RSVD_30_16 register field. */
50303 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_RSVD_30_16_MSB 30
50304 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_RSVD_30_16 register field. */
50305 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_RSVD_30_16_WIDTH 15
50306 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_RSVD_30_16 register field value. */
50307 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
50308 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_RSVD_30_16 register field value. */
50309 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
50310 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_RSVD_30_16 register field. */
50311 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_RSVD_30_16_RESET 0x0
50312 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_RSVD_30_16 field value from a register. */
50313 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
50314 /* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_RSVD_30_16 register field value suitable for setting the register. */
50315 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
50316 
50317 /*
50318  * Field : ae
50319  *
50320  * Address Enable
50321  *
50322  * When this bit is set, the address filter module uses the 51st MAC address for
50323  * perfect filtering.
50324  *
50325  * When this bit is reset, the address filter module ignores the address for
50326  * filtering.
50327  *
50328  * Field Enumeration Values:
50329  *
50330  * Enum | Value | Description
50331  * :----------------------------------------|:------|:------------
50332  * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_E_DISD | 0x0 |
50333  * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_E_END | 0x1 |
50334  *
50335  * Field Access Macros:
50336  *
50337  */
50338 /*
50339  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE
50340  *
50341  */
50342 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_E_DISD 0x0
50343 /*
50344  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE
50345  *
50346  */
50347 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_E_END 0x1
50348 
50349 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field. */
50350 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_LSB 31
50351 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field. */
50352 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_MSB 31
50353 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field. */
50354 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_WIDTH 1
50355 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field value. */
50356 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_SET_MSK 0x80000000
50357 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field value. */
50358 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_CLR_MSK 0x7fffffff
50359 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field. */
50360 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_RESET 0x0
50361 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE field value from a register. */
50362 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
50363 /* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field value suitable for setting the register. */
50364 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
50365 
50366 #ifndef __ASSEMBLY__
50367 /*
50368  * WARNING: The C register and register group struct declarations are provided for
50369  * convenience and illustrative purposes. They should, however, be used with
50370  * caution as the C language standard provides no guarantees about the alignment or
50371  * atomicity of device memory accesses. The recommended practice for writing
50372  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
50373  * alt_write_word() functions.
50374  *
50375  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR50_HIGH.
50376  */
50377 struct ALT_EMAC_GMAC_MAC_ADDR50_HIGH_s
50378 {
50379  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI */
50380  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR50_HIGH_RSVD_30_16 */
50381  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE */
50382 };
50383 
50384 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR50_HIGH. */
50385 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR50_HIGH_s ALT_EMAC_GMAC_MAC_ADDR50_HIGH_t;
50386 #endif /* __ASSEMBLY__ */
50387 
50388 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH register. */
50389 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_RESET 0x0000ffff
50390 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH register from the beginning of the component. */
50391 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_OFST 0x910
50392 /* The address of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH register. */
50393 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR50_HIGH_OFST))
50394 
50395 /*
50396  * Register : gmacgrp_mac_address50_low
50397  *
50398  * <b> Register 581 (MAC Address50 Low Register) </b>
50399  *
50400  * The MAC Address50 Low register holds the lower 32 bits of the 51st 6-byte MAC
50401  * address of the station.
50402  *
50403  * Register Layout
50404  *
50405  * Bits | Access | Reset | Description
50406  * :-------|:-------|:-----------|:------------------------------------
50407  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO
50408  *
50409  */
50410 /*
50411  * Field : addrlo
50412  *
50413  * MAC Address50 [31:0]
50414  *
50415  * This field contains the lower 32 bits of the 51st 6-byte MAC address. The
50416  * content of this field is undefined until loaded by the Application after the
50417  * initialization process.
50418  *
50419  * Field Access Macros:
50420  *
50421  */
50422 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field. */
50423 #define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_LSB 0
50424 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field. */
50425 #define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_MSB 31
50426 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field. */
50427 #define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_WIDTH 32
50428 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field value. */
50429 #define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_SET_MSK 0xffffffff
50430 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field value. */
50431 #define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_CLR_MSK 0x00000000
50432 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field. */
50433 #define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_RESET 0xffffffff
50434 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO field value from a register. */
50435 #define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
50436 /* Produces a ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field value suitable for setting the register. */
50437 #define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
50438 
50439 #ifndef __ASSEMBLY__
50440 /*
50441  * WARNING: The C register and register group struct declarations are provided for
50442  * convenience and illustrative purposes. They should, however, be used with
50443  * caution as the C language standard provides no guarantees about the alignment or
50444  * atomicity of device memory accesses. The recommended practice for writing
50445  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
50446  * alt_write_word() functions.
50447  *
50448  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR50_LOW.
50449  */
50450 struct ALT_EMAC_GMAC_MAC_ADDR50_LOW_s
50451 {
50452  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO */
50453 };
50454 
50455 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR50_LOW. */
50456 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR50_LOW_s ALT_EMAC_GMAC_MAC_ADDR50_LOW_t;
50457 #endif /* __ASSEMBLY__ */
50458 
50459 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_LOW register. */
50460 #define ALT_EMAC_GMAC_MAC_ADDR50_LOW_RESET 0xffffffff
50461 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR50_LOW register from the beginning of the component. */
50462 #define ALT_EMAC_GMAC_MAC_ADDR50_LOW_OFST 0x914
50463 /* The address of the ALT_EMAC_GMAC_MAC_ADDR50_LOW register. */
50464 #define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR50_LOW_OFST))
50465 
50466 /*
50467  * Register : gmacgrp_mac_address51_high
50468  *
50469  * <b> Register 582 (MAC Address51 High Register) </b>
50470  *
50471  * The MAC Address51 High register holds the upper 16 bits of the 52nd 6-byte MAC
50472  * address of the station.
50473  *
50474  * If the MAC address registers are configured to be double-synchronized to the
50475  * (G)MII clock domains, then
50476  *
50477  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
50478  * or Bits[7:0] (in big-endian mode) of the MAC Address51 Low Register are written.
50479  * For proper synchronization updates, consecutive writes to this MAC Address51 Low
50480  * Register must be performed after at least four clock cycles in the destination
50481  * clock domain.
50482  *
50483  * Register Layout
50484  *
50485  * Bits | Access | Reset | Description
50486  * :--------|:-------|:-------|:-----------------------------------------
50487  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI
50488  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR51_HIGH_RSVD_30_16
50489  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE
50490  *
50491  */
50492 /*
50493  * Field : addrhi
50494  *
50495  * MAC Address51 [47:32]
50496  *
50497  * This field contains the upper 16 bits (47:32) of the 52nd 6-byte MAC address.
50498  *
50499  * Field Access Macros:
50500  *
50501  */
50502 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field. */
50503 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_LSB 0
50504 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field. */
50505 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_MSB 15
50506 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field. */
50507 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_WIDTH 16
50508 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field value. */
50509 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_SET_MSK 0x0000ffff
50510 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field value. */
50511 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_CLR_MSK 0xffff0000
50512 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field. */
50513 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_RESET 0xffff
50514 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI field value from a register. */
50515 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
50516 /* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field value suitable for setting the register. */
50517 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
50518 
50519 /*
50520  * Field : reserved_30_16
50521  *
50522  * Reserved
50523  *
50524  * Field Access Macros:
50525  *
50526  */
50527 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_RSVD_30_16 register field. */
50528 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_RSVD_30_16_LSB 16
50529 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_RSVD_30_16 register field. */
50530 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_RSVD_30_16_MSB 30
50531 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_RSVD_30_16 register field. */
50532 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_RSVD_30_16_WIDTH 15
50533 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_RSVD_30_16 register field value. */
50534 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
50535 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_RSVD_30_16 register field value. */
50536 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
50537 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_RSVD_30_16 register field. */
50538 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_RSVD_30_16_RESET 0x0
50539 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_RSVD_30_16 field value from a register. */
50540 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
50541 /* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_RSVD_30_16 register field value suitable for setting the register. */
50542 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
50543 
50544 /*
50545  * Field : ae
50546  *
50547  * Address Enable
50548  *
50549  * When this bit is set, the address filter module uses the 52nd MAC address for
50550  * perfect filtering.
50551  *
50552  * When this bit is reset, the address filter module ignores the address for
50553  * filtering.
50554  *
50555  * Field Enumeration Values:
50556  *
50557  * Enum | Value | Description
50558  * :----------------------------------------|:------|:------------
50559  * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_E_DISD | 0x0 |
50560  * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_E_END | 0x1 |
50561  *
50562  * Field Access Macros:
50563  *
50564  */
50565 /*
50566  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE
50567  *
50568  */
50569 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_E_DISD 0x0
50570 /*
50571  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE
50572  *
50573  */
50574 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_E_END 0x1
50575 
50576 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field. */
50577 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_LSB 31
50578 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field. */
50579 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_MSB 31
50580 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field. */
50581 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_WIDTH 1
50582 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field value. */
50583 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_SET_MSK 0x80000000
50584 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field value. */
50585 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_CLR_MSK 0x7fffffff
50586 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field. */
50587 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_RESET 0x0
50588 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE field value from a register. */
50589 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
50590 /* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field value suitable for setting the register. */
50591 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
50592 
50593 #ifndef __ASSEMBLY__
50594 /*
50595  * WARNING: The C register and register group struct declarations are provided for
50596  * convenience and illustrative purposes. They should, however, be used with
50597  * caution as the C language standard provides no guarantees about the alignment or
50598  * atomicity of device memory accesses. The recommended practice for writing
50599  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
50600  * alt_write_word() functions.
50601  *
50602  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR51_HIGH.
50603  */
50604 struct ALT_EMAC_GMAC_MAC_ADDR51_HIGH_s
50605 {
50606  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI */
50607  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR51_HIGH_RSVD_30_16 */
50608  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE */
50609 };
50610 
50611 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR51_HIGH. */
50612 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR51_HIGH_s ALT_EMAC_GMAC_MAC_ADDR51_HIGH_t;
50613 #endif /* __ASSEMBLY__ */
50614 
50615 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH register. */
50616 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_RESET 0x0000ffff
50617 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH register from the beginning of the component. */
50618 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_OFST 0x918
50619 /* The address of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH register. */
50620 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR51_HIGH_OFST))
50621 
50622 /*
50623  * Register : gmacgrp_mac_address51_low
50624  *
50625  * <b> Register 583 (MAC Address51 Low Register) </b>
50626  *
50627  * The MAC Address51 Low register holds the lower 32 bits of the 52nd 6-byte MAC
50628  * address of the station.
50629  *
50630  * Register Layout
50631  *
50632  * Bits | Access | Reset | Description
50633  * :-------|:-------|:-----------|:------------------------------------
50634  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO
50635  *
50636  */
50637 /*
50638  * Field : addrlo
50639  *
50640  * MAC Address51 [31:0]
50641  *
50642  * This field contains the lower 32 bits of the 52nd 6-byte MAC address. The
50643  * content of this field is undefined until loaded by the Application after the
50644  * initialization process.
50645  *
50646  * Field Access Macros:
50647  *
50648  */
50649 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field. */
50650 #define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_LSB 0
50651 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field. */
50652 #define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_MSB 31
50653 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field. */
50654 #define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_WIDTH 32
50655 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field value. */
50656 #define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_SET_MSK 0xffffffff
50657 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field value. */
50658 #define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_CLR_MSK 0x00000000
50659 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field. */
50660 #define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_RESET 0xffffffff
50661 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO field value from a register. */
50662 #define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
50663 /* Produces a ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field value suitable for setting the register. */
50664 #define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
50665 
50666 #ifndef __ASSEMBLY__
50667 /*
50668  * WARNING: The C register and register group struct declarations are provided for
50669  * convenience and illustrative purposes. They should, however, be used with
50670  * caution as the C language standard provides no guarantees about the alignment or
50671  * atomicity of device memory accesses. The recommended practice for writing
50672  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
50673  * alt_write_word() functions.
50674  *
50675  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR51_LOW.
50676  */
50677 struct ALT_EMAC_GMAC_MAC_ADDR51_LOW_s
50678 {
50679  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO */
50680 };
50681 
50682 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR51_LOW. */
50683 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR51_LOW_s ALT_EMAC_GMAC_MAC_ADDR51_LOW_t;
50684 #endif /* __ASSEMBLY__ */
50685 
50686 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_LOW register. */
50687 #define ALT_EMAC_GMAC_MAC_ADDR51_LOW_RESET 0xffffffff
50688 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR51_LOW register from the beginning of the component. */
50689 #define ALT_EMAC_GMAC_MAC_ADDR51_LOW_OFST 0x91c
50690 /* The address of the ALT_EMAC_GMAC_MAC_ADDR51_LOW register. */
50691 #define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR51_LOW_OFST))
50692 
50693 /*
50694  * Register : gmacgrp_mac_address52_high
50695  *
50696  * <b> Register 584 (MAC Address52 High Register) </b>
50697  *
50698  * The MAC Address52 High register holds the upper 16 bits of the 53rd 6-byte MAC
50699  * address of the station.
50700  *
50701  * If the MAC address registers are configured to be double-synchronized to the
50702  * (G)MII clock domains, then
50703  *
50704  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
50705  * or Bits[7:0] (in big-endian mode) of the MAC Address52 Low Register are written.
50706  * For proper synchronization updates, consecutive writes to this MAC Address52 Low
50707  * Register must be performed after at least four clock cycles in the destination
50708  * clock domain.
50709  *
50710  * Register Layout
50711  *
50712  * Bits | Access | Reset | Description
50713  * :--------|:-------|:-------|:-----------------------------------------
50714  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI
50715  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR52_HIGH_RSVD_30_16
50716  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE
50717  *
50718  */
50719 /*
50720  * Field : addrhi
50721  *
50722  * MAC Address52 [47:32]
50723  *
50724  * This field contains the upper 16 bits (47:32) of the 53rd 6-byte MAC address.
50725  *
50726  * Field Access Macros:
50727  *
50728  */
50729 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field. */
50730 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_LSB 0
50731 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field. */
50732 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_MSB 15
50733 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field. */
50734 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_WIDTH 16
50735 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field value. */
50736 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_SET_MSK 0x0000ffff
50737 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field value. */
50738 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_CLR_MSK 0xffff0000
50739 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field. */
50740 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_RESET 0xffff
50741 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI field value from a register. */
50742 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
50743 /* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field value suitable for setting the register. */
50744 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
50745 
50746 /*
50747  * Field : reserved_30_16
50748  *
50749  * Reserved
50750  *
50751  * Field Access Macros:
50752  *
50753  */
50754 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_RSVD_30_16 register field. */
50755 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_RSVD_30_16_LSB 16
50756 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_RSVD_30_16 register field. */
50757 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_RSVD_30_16_MSB 30
50758 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_RSVD_30_16 register field. */
50759 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_RSVD_30_16_WIDTH 15
50760 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_RSVD_30_16 register field value. */
50761 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
50762 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_RSVD_30_16 register field value. */
50763 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
50764 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_RSVD_30_16 register field. */
50765 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_RSVD_30_16_RESET 0x0
50766 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_RSVD_30_16 field value from a register. */
50767 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
50768 /* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_RSVD_30_16 register field value suitable for setting the register. */
50769 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
50770 
50771 /*
50772  * Field : ae
50773  *
50774  * Address Enable
50775  *
50776  * When this bit is set, the address filter module uses the 53rd MAC address for
50777  * perfect filtering.
50778  *
50779  * When this bit is reset, the address filter module ignores the address for
50780  * filtering.
50781  *
50782  * Field Enumeration Values:
50783  *
50784  * Enum | Value | Description
50785  * :----------------------------------------|:------|:------------
50786  * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_E_DISD | 0x0 |
50787  * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_E_END | 0x1 |
50788  *
50789  * Field Access Macros:
50790  *
50791  */
50792 /*
50793  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE
50794  *
50795  */
50796 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_E_DISD 0x0
50797 /*
50798  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE
50799  *
50800  */
50801 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_E_END 0x1
50802 
50803 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field. */
50804 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_LSB 31
50805 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field. */
50806 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_MSB 31
50807 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field. */
50808 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_WIDTH 1
50809 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field value. */
50810 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_SET_MSK 0x80000000
50811 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field value. */
50812 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_CLR_MSK 0x7fffffff
50813 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field. */
50814 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_RESET 0x0
50815 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE field value from a register. */
50816 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
50817 /* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field value suitable for setting the register. */
50818 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
50819 
50820 #ifndef __ASSEMBLY__
50821 /*
50822  * WARNING: The C register and register group struct declarations are provided for
50823  * convenience and illustrative purposes. They should, however, be used with
50824  * caution as the C language standard provides no guarantees about the alignment or
50825  * atomicity of device memory accesses. The recommended practice for writing
50826  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
50827  * alt_write_word() functions.
50828  *
50829  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR52_HIGH.
50830  */
50831 struct ALT_EMAC_GMAC_MAC_ADDR52_HIGH_s
50832 {
50833  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI */
50834  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR52_HIGH_RSVD_30_16 */
50835  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE */
50836 };
50837 
50838 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR52_HIGH. */
50839 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR52_HIGH_s ALT_EMAC_GMAC_MAC_ADDR52_HIGH_t;
50840 #endif /* __ASSEMBLY__ */
50841 
50842 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH register. */
50843 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_RESET 0x0000ffff
50844 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH register from the beginning of the component. */
50845 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_OFST 0x920
50846 /* The address of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH register. */
50847 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR52_HIGH_OFST))
50848 
50849 /*
50850  * Register : gmacgrp_mac_address52_low
50851  *
50852  * <b> Register 585 (MAC Address52 Low Register) </b>
50853  *
50854  * The MAC Address52 Low register holds the lower 32 bits of the 53rd 6-byte MAC
50855  * address of the station.
50856  *
50857  * Register Layout
50858  *
50859  * Bits | Access | Reset | Description
50860  * :-------|:-------|:-----------|:------------------------------------
50861  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO
50862  *
50863  */
50864 /*
50865  * Field : addrlo
50866  *
50867  * MAC Address52 [31:0]
50868  *
50869  * This field contains the lower 32 bits of the 53rd 6-byte MAC address. The
50870  * content of this field is undefined until loaded by the Application after the
50871  * initialization process.
50872  *
50873  * Field Access Macros:
50874  *
50875  */
50876 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field. */
50877 #define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_LSB 0
50878 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field. */
50879 #define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_MSB 31
50880 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field. */
50881 #define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_WIDTH 32
50882 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field value. */
50883 #define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_SET_MSK 0xffffffff
50884 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field value. */
50885 #define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_CLR_MSK 0x00000000
50886 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field. */
50887 #define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_RESET 0xffffffff
50888 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO field value from a register. */
50889 #define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
50890 /* Produces a ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field value suitable for setting the register. */
50891 #define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
50892 
50893 #ifndef __ASSEMBLY__
50894 /*
50895  * WARNING: The C register and register group struct declarations are provided for
50896  * convenience and illustrative purposes. They should, however, be used with
50897  * caution as the C language standard provides no guarantees about the alignment or
50898  * atomicity of device memory accesses. The recommended practice for writing
50899  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
50900  * alt_write_word() functions.
50901  *
50902  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR52_LOW.
50903  */
50904 struct ALT_EMAC_GMAC_MAC_ADDR52_LOW_s
50905 {
50906  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO */
50907 };
50908 
50909 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR52_LOW. */
50910 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR52_LOW_s ALT_EMAC_GMAC_MAC_ADDR52_LOW_t;
50911 #endif /* __ASSEMBLY__ */
50912 
50913 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_LOW register. */
50914 #define ALT_EMAC_GMAC_MAC_ADDR52_LOW_RESET 0xffffffff
50915 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR52_LOW register from the beginning of the component. */
50916 #define ALT_EMAC_GMAC_MAC_ADDR52_LOW_OFST 0x924
50917 /* The address of the ALT_EMAC_GMAC_MAC_ADDR52_LOW register. */
50918 #define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR52_LOW_OFST))
50919 
50920 /*
50921  * Register : gmacgrp_mac_address53_high
50922  *
50923  * <b> Register 586 (MAC Address53 High Register)</b>
50924  *
50925  * The MAC Address53 High register holds the upper 16 bits of the 54th 6-byte MAC
50926  * address of the station.
50927  *
50928  * If the MAC address registers are configured to be double-synchronized to the
50929  * (G)MII clock domains, then
50930  *
50931  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
50932  * or Bits[7:0] (in big-endian mode) of the MAC Address53 Low Register are written.
50933  * For proper synchronization updates, consecutive writes to this MAC Address53 Low
50934  * Register must be performed after at least four clock cycles in the destination
50935  * clock domain.
50936  *
50937  * Register Layout
50938  *
50939  * Bits | Access | Reset | Description
50940  * :--------|:-------|:-------|:-----------------------------------------
50941  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI
50942  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR53_HIGH_RSVD_30_16
50943  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE
50944  *
50945  */
50946 /*
50947  * Field : addrhi
50948  *
50949  * MAC Address53 [47:32]
50950  *
50951  * This field contains the upper 16 bits (47:32) of the 54th 6-byte MAC address.
50952  *
50953  * Field Access Macros:
50954  *
50955  */
50956 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field. */
50957 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_LSB 0
50958 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field. */
50959 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_MSB 15
50960 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field. */
50961 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_WIDTH 16
50962 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field value. */
50963 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_SET_MSK 0x0000ffff
50964 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field value. */
50965 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_CLR_MSK 0xffff0000
50966 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field. */
50967 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_RESET 0xffff
50968 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI field value from a register. */
50969 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
50970 /* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field value suitable for setting the register. */
50971 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
50972 
50973 /*
50974  * Field : reserved_30_16
50975  *
50976  * Reserved
50977  *
50978  * Field Access Macros:
50979  *
50980  */
50981 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_RSVD_30_16 register field. */
50982 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_RSVD_30_16_LSB 16
50983 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_RSVD_30_16 register field. */
50984 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_RSVD_30_16_MSB 30
50985 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_RSVD_30_16 register field. */
50986 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_RSVD_30_16_WIDTH 15
50987 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_RSVD_30_16 register field value. */
50988 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
50989 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_RSVD_30_16 register field value. */
50990 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
50991 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_RSVD_30_16 register field. */
50992 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_RSVD_30_16_RESET 0x0
50993 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_RSVD_30_16 field value from a register. */
50994 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
50995 /* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_RSVD_30_16 register field value suitable for setting the register. */
50996 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
50997 
50998 /*
50999  * Field : ae
51000  *
51001  * Address Enable
51002  *
51003  * When this bit is set, the address filter module uses the 54th MAC address for
51004  * perfect filtering.
51005  *
51006  * When this bit is reset, the address filter module ignores the address for
51007  * filtering.
51008  *
51009  * Field Enumeration Values:
51010  *
51011  * Enum | Value | Description
51012  * :----------------------------------------|:------|:------------
51013  * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_E_DISD | 0x0 |
51014  * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_E_END | 0x1 |
51015  *
51016  * Field Access Macros:
51017  *
51018  */
51019 /*
51020  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE
51021  *
51022  */
51023 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_E_DISD 0x0
51024 /*
51025  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE
51026  *
51027  */
51028 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_E_END 0x1
51029 
51030 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field. */
51031 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_LSB 31
51032 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field. */
51033 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_MSB 31
51034 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field. */
51035 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_WIDTH 1
51036 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field value. */
51037 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_SET_MSK 0x80000000
51038 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field value. */
51039 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_CLR_MSK 0x7fffffff
51040 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field. */
51041 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_RESET 0x0
51042 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE field value from a register. */
51043 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
51044 /* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field value suitable for setting the register. */
51045 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
51046 
51047 #ifndef __ASSEMBLY__
51048 /*
51049  * WARNING: The C register and register group struct declarations are provided for
51050  * convenience and illustrative purposes. They should, however, be used with
51051  * caution as the C language standard provides no guarantees about the alignment or
51052  * atomicity of device memory accesses. The recommended practice for writing
51053  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
51054  * alt_write_word() functions.
51055  *
51056  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR53_HIGH.
51057  */
51058 struct ALT_EMAC_GMAC_MAC_ADDR53_HIGH_s
51059 {
51060  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI */
51061  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR53_HIGH_RSVD_30_16 */
51062  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE */
51063 };
51064 
51065 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR53_HIGH. */
51066 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR53_HIGH_s ALT_EMAC_GMAC_MAC_ADDR53_HIGH_t;
51067 #endif /* __ASSEMBLY__ */
51068 
51069 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH register. */
51070 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_RESET 0x0000ffff
51071 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH register from the beginning of the component. */
51072 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_OFST 0x928
51073 /* The address of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH register. */
51074 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR53_HIGH_OFST))
51075 
51076 /*
51077  * Register : gmacgrp_mac_address53_low
51078  *
51079  * <b> Register 587 (MAC Address53 Low Register)</b>
51080  *
51081  * The MAC Address53 Low register holds the lower 32 bits of the 54th 6-byte MAC
51082  * address of the station.
51083  *
51084  * Register Layout
51085  *
51086  * Bits | Access | Reset | Description
51087  * :-------|:-------|:-----------|:------------------------------------
51088  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO
51089  *
51090  */
51091 /*
51092  * Field : addrlo
51093  *
51094  * MAC Address53 [31:0]
51095  *
51096  * This field contains the lower 32 bits of the 54th 6-byte MAC address. The
51097  * content of this field is undefined until loaded by the Application after the
51098  * initialization process.
51099  *
51100  * Field Access Macros:
51101  *
51102  */
51103 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field. */
51104 #define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_LSB 0
51105 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field. */
51106 #define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_MSB 31
51107 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field. */
51108 #define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_WIDTH 32
51109 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field value. */
51110 #define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_SET_MSK 0xffffffff
51111 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field value. */
51112 #define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_CLR_MSK 0x00000000
51113 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field. */
51114 #define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_RESET 0xffffffff
51115 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO field value from a register. */
51116 #define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
51117 /* Produces a ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field value suitable for setting the register. */
51118 #define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
51119 
51120 #ifndef __ASSEMBLY__
51121 /*
51122  * WARNING: The C register and register group struct declarations are provided for
51123  * convenience and illustrative purposes. They should, however, be used with
51124  * caution as the C language standard provides no guarantees about the alignment or
51125  * atomicity of device memory accesses. The recommended practice for writing
51126  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
51127  * alt_write_word() functions.
51128  *
51129  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR53_LOW.
51130  */
51131 struct ALT_EMAC_GMAC_MAC_ADDR53_LOW_s
51132 {
51133  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO */
51134 };
51135 
51136 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR53_LOW. */
51137 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR53_LOW_s ALT_EMAC_GMAC_MAC_ADDR53_LOW_t;
51138 #endif /* __ASSEMBLY__ */
51139 
51140 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_LOW register. */
51141 #define ALT_EMAC_GMAC_MAC_ADDR53_LOW_RESET 0xffffffff
51142 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR53_LOW register from the beginning of the component. */
51143 #define ALT_EMAC_GMAC_MAC_ADDR53_LOW_OFST 0x92c
51144 /* The address of the ALT_EMAC_GMAC_MAC_ADDR53_LOW register. */
51145 #define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR53_LOW_OFST))
51146 
51147 /*
51148  * Register : gmacgrp_mac_address54_high
51149  *
51150  * <b> Register 588 (MAC Address54 High Register)</b>
51151  *
51152  * The MAC Address54 High register holds the upper 16 bits of the 55th 6-byte MAC
51153  * address of the station.
51154  *
51155  * If the MAC address registers are configured to be double-synchronized to the
51156  * (G)MII clock domains, then
51157  *
51158  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
51159  * or Bits[7:0] (in big-endian mode) of the MAC Address54 Low Register are written.
51160  * For proper synchronization updates, consecutive writes to this MAC Address54 Low
51161  * Register must be performed after at least four clock cycles in the destination
51162  * clock domain.
51163  *
51164  * Register Layout
51165  *
51166  * Bits | Access | Reset | Description
51167  * :--------|:-------|:-------|:-----------------------------------------
51168  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI
51169  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR54_HIGH_RSVD_30_16
51170  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE
51171  *
51172  */
51173 /*
51174  * Field : addrhi
51175  *
51176  * MAC Address54 [47:32]
51177  *
51178  * This field contains the upper 16 bits (47:32) of the 55th 6-byte MAC address.
51179  *
51180  * Field Access Macros:
51181  *
51182  */
51183 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field. */
51184 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_LSB 0
51185 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field. */
51186 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_MSB 15
51187 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field. */
51188 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_WIDTH 16
51189 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field value. */
51190 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_SET_MSK 0x0000ffff
51191 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field value. */
51192 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_CLR_MSK 0xffff0000
51193 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field. */
51194 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_RESET 0xffff
51195 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI field value from a register. */
51196 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
51197 /* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field value suitable for setting the register. */
51198 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
51199 
51200 /*
51201  * Field : reserved_30_16
51202  *
51203  * Reserved
51204  *
51205  * Field Access Macros:
51206  *
51207  */
51208 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_RSVD_30_16 register field. */
51209 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_RSVD_30_16_LSB 16
51210 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_RSVD_30_16 register field. */
51211 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_RSVD_30_16_MSB 30
51212 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_RSVD_30_16 register field. */
51213 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_RSVD_30_16_WIDTH 15
51214 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_RSVD_30_16 register field value. */
51215 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
51216 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_RSVD_30_16 register field value. */
51217 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
51218 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_RSVD_30_16 register field. */
51219 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_RSVD_30_16_RESET 0x0
51220 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_RSVD_30_16 field value from a register. */
51221 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
51222 /* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_RSVD_30_16 register field value suitable for setting the register. */
51223 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
51224 
51225 /*
51226  * Field : ae
51227  *
51228  * Address Enable
51229  *
51230  * When this bit is set, the address filter module uses the 55th MAC address for
51231  * perfect filtering.
51232  *
51233  * When this bit is reset, the address filter module ignores the address for
51234  * filtering.
51235  *
51236  * Field Enumeration Values:
51237  *
51238  * Enum | Value | Description
51239  * :----------------------------------------|:------|:------------
51240  * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_E_DISD | 0x0 |
51241  * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_E_END | 0x1 |
51242  *
51243  * Field Access Macros:
51244  *
51245  */
51246 /*
51247  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE
51248  *
51249  */
51250 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_E_DISD 0x0
51251 /*
51252  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE
51253  *
51254  */
51255 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_E_END 0x1
51256 
51257 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field. */
51258 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_LSB 31
51259 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field. */
51260 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_MSB 31
51261 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field. */
51262 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_WIDTH 1
51263 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field value. */
51264 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_SET_MSK 0x80000000
51265 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field value. */
51266 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_CLR_MSK 0x7fffffff
51267 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field. */
51268 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_RESET 0x0
51269 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE field value from a register. */
51270 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
51271 /* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field value suitable for setting the register. */
51272 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
51273 
51274 #ifndef __ASSEMBLY__
51275 /*
51276  * WARNING: The C register and register group struct declarations are provided for
51277  * convenience and illustrative purposes. They should, however, be used with
51278  * caution as the C language standard provides no guarantees about the alignment or
51279  * atomicity of device memory accesses. The recommended practice for writing
51280  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
51281  * alt_write_word() functions.
51282  *
51283  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR54_HIGH.
51284  */
51285 struct ALT_EMAC_GMAC_MAC_ADDR54_HIGH_s
51286 {
51287  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI */
51288  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR54_HIGH_RSVD_30_16 */
51289  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE */
51290 };
51291 
51292 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR54_HIGH. */
51293 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR54_HIGH_s ALT_EMAC_GMAC_MAC_ADDR54_HIGH_t;
51294 #endif /* __ASSEMBLY__ */
51295 
51296 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH register. */
51297 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_RESET 0x0000ffff
51298 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH register from the beginning of the component. */
51299 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_OFST 0x930
51300 /* The address of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH register. */
51301 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR54_HIGH_OFST))
51302 
51303 /*
51304  * Register : gmacgrp_mac_address54_low
51305  *
51306  * <b> Register 589 (MAC Address54 Low Register)</b>
51307  *
51308  * The MAC Address54 Low register holds the lower 32 bits of the 55th 6-byte MAC
51309  * address of the station.
51310  *
51311  * Register Layout
51312  *
51313  * Bits | Access | Reset | Description
51314  * :-------|:-------|:-----------|:------------------------------------
51315  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO
51316  *
51317  */
51318 /*
51319  * Field : addrlo
51320  *
51321  * MAC Address54 [31:0]
51322  *
51323  * This field contains the lower 32 bits of the 55th 6-byte MAC address. The
51324  * content of this field is undefined until loaded by the Application after the
51325  * initialization process.
51326  *
51327  * Field Access Macros:
51328  *
51329  */
51330 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field. */
51331 #define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_LSB 0
51332 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field. */
51333 #define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_MSB 31
51334 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field. */
51335 #define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_WIDTH 32
51336 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field value. */
51337 #define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_SET_MSK 0xffffffff
51338 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field value. */
51339 #define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_CLR_MSK 0x00000000
51340 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field. */
51341 #define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_RESET 0xffffffff
51342 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO field value from a register. */
51343 #define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
51344 /* Produces a ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field value suitable for setting the register. */
51345 #define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
51346 
51347 #ifndef __ASSEMBLY__
51348 /*
51349  * WARNING: The C register and register group struct declarations are provided for
51350  * convenience and illustrative purposes. They should, however, be used with
51351  * caution as the C language standard provides no guarantees about the alignment or
51352  * atomicity of device memory accesses. The recommended practice for writing
51353  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
51354  * alt_write_word() functions.
51355  *
51356  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR54_LOW.
51357  */
51358 struct ALT_EMAC_GMAC_MAC_ADDR54_LOW_s
51359 {
51360  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO */
51361 };
51362 
51363 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR54_LOW. */
51364 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR54_LOW_s ALT_EMAC_GMAC_MAC_ADDR54_LOW_t;
51365 #endif /* __ASSEMBLY__ */
51366 
51367 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_LOW register. */
51368 #define ALT_EMAC_GMAC_MAC_ADDR54_LOW_RESET 0xffffffff
51369 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR54_LOW register from the beginning of the component. */
51370 #define ALT_EMAC_GMAC_MAC_ADDR54_LOW_OFST 0x934
51371 /* The address of the ALT_EMAC_GMAC_MAC_ADDR54_LOW register. */
51372 #define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR54_LOW_OFST))
51373 
51374 /*
51375  * Register : gmacgrp_mac_address55_high
51376  *
51377  * <b> Register 590 (MAC Address55 High Register) </b>
51378  *
51379  * The MAC Address55 High register holds the upper 16 bits of the 56th 6-byte MAC
51380  * address of the station.
51381  *
51382  * If the MAC address registers are configured to be double-synchronized to the
51383  * (G)MII clock domains, then
51384  *
51385  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
51386  * or Bits[7:0] (in big-endian mode) of the MAC Address55 Low Register are written.
51387  * For proper synchronization updates, consecutive writes to this MAC Address55 Low
51388  * Register must be performed after at least four clock cycles in the destination
51389  * clock domain.
51390  *
51391  * Register Layout
51392  *
51393  * Bits | Access | Reset | Description
51394  * :--------|:-------|:-------|:-----------------------------------------
51395  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI
51396  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR55_HIGH_RSVD_30_16
51397  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE
51398  *
51399  */
51400 /*
51401  * Field : addrhi
51402  *
51403  * MAC Address55 [47:32]
51404  *
51405  * This field contains the upper 16 bits (47:32) of the 56th 6-byte MAC address.
51406  *
51407  * Field Access Macros:
51408  *
51409  */
51410 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field. */
51411 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_LSB 0
51412 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field. */
51413 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_MSB 15
51414 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field. */
51415 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_WIDTH 16
51416 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field value. */
51417 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_SET_MSK 0x0000ffff
51418 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field value. */
51419 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_CLR_MSK 0xffff0000
51420 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field. */
51421 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_RESET 0xffff
51422 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI field value from a register. */
51423 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
51424 /* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field value suitable for setting the register. */
51425 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
51426 
51427 /*
51428  * Field : reserved_30_16
51429  *
51430  * Reserved
51431  *
51432  * Field Access Macros:
51433  *
51434  */
51435 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_RSVD_30_16 register field. */
51436 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_RSVD_30_16_LSB 16
51437 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_RSVD_30_16 register field. */
51438 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_RSVD_30_16_MSB 30
51439 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_RSVD_30_16 register field. */
51440 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_RSVD_30_16_WIDTH 15
51441 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_RSVD_30_16 register field value. */
51442 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
51443 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_RSVD_30_16 register field value. */
51444 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
51445 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_RSVD_30_16 register field. */
51446 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_RSVD_30_16_RESET 0x0
51447 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_RSVD_30_16 field value from a register. */
51448 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
51449 /* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_RSVD_30_16 register field value suitable for setting the register. */
51450 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
51451 
51452 /*
51453  * Field : ae
51454  *
51455  * Address Enable
51456  *
51457  * When this bit is set, the address filter module uses the 56th MAC address for
51458  * perfect filtering.
51459  *
51460  * When this bit is reset, the address filter module ignores the address for
51461  * filtering.
51462  *
51463  * Field Enumeration Values:
51464  *
51465  * Enum | Value | Description
51466  * :----------------------------------------|:------|:------------
51467  * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_E_DISD | 0x0 |
51468  * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_E_END | 0x1 |
51469  *
51470  * Field Access Macros:
51471  *
51472  */
51473 /*
51474  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE
51475  *
51476  */
51477 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_E_DISD 0x0
51478 /*
51479  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE
51480  *
51481  */
51482 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_E_END 0x1
51483 
51484 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field. */
51485 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_LSB 31
51486 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field. */
51487 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_MSB 31
51488 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field. */
51489 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_WIDTH 1
51490 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field value. */
51491 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_SET_MSK 0x80000000
51492 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field value. */
51493 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_CLR_MSK 0x7fffffff
51494 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field. */
51495 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_RESET 0x0
51496 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE field value from a register. */
51497 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
51498 /* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field value suitable for setting the register. */
51499 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
51500 
51501 #ifndef __ASSEMBLY__
51502 /*
51503  * WARNING: The C register and register group struct declarations are provided for
51504  * convenience and illustrative purposes. They should, however, be used with
51505  * caution as the C language standard provides no guarantees about the alignment or
51506  * atomicity of device memory accesses. The recommended practice for writing
51507  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
51508  * alt_write_word() functions.
51509  *
51510  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR55_HIGH.
51511  */
51512 struct ALT_EMAC_GMAC_MAC_ADDR55_HIGH_s
51513 {
51514  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI */
51515  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR55_HIGH_RSVD_30_16 */
51516  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE */
51517 };
51518 
51519 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR55_HIGH. */
51520 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR55_HIGH_s ALT_EMAC_GMAC_MAC_ADDR55_HIGH_t;
51521 #endif /* __ASSEMBLY__ */
51522 
51523 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH register. */
51524 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_RESET 0x0000ffff
51525 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH register from the beginning of the component. */
51526 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_OFST 0x938
51527 /* The address of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH register. */
51528 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR55_HIGH_OFST))
51529 
51530 /*
51531  * Register : gmacgrp_mac_address55_low
51532  *
51533  * <b> Register 591 (MAC Address55 Low Register) </b>
51534  *
51535  * The MAC Address55 Low register holds the lower 32 bits of the 56th 6-byte MAC
51536  * address of the station.
51537  *
51538  * Register Layout
51539  *
51540  * Bits | Access | Reset | Description
51541  * :-------|:-------|:-----------|:------------------------------------
51542  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO
51543  *
51544  */
51545 /*
51546  * Field : addrlo
51547  *
51548  * MAC Address55 [31:0]
51549  *
51550  * This field contains the lower 32 bits of the 56th 6-byte MAC address. The
51551  * content of this field is undefined until loaded by the Application after the
51552  * initialization process.
51553  *
51554  * Field Access Macros:
51555  *
51556  */
51557 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field. */
51558 #define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_LSB 0
51559 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field. */
51560 #define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_MSB 31
51561 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field. */
51562 #define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_WIDTH 32
51563 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field value. */
51564 #define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_SET_MSK 0xffffffff
51565 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field value. */
51566 #define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_CLR_MSK 0x00000000
51567 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field. */
51568 #define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_RESET 0xffffffff
51569 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO field value from a register. */
51570 #define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
51571 /* Produces a ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field value suitable for setting the register. */
51572 #define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
51573 
51574 #ifndef __ASSEMBLY__
51575 /*
51576  * WARNING: The C register and register group struct declarations are provided for
51577  * convenience and illustrative purposes. They should, however, be used with
51578  * caution as the C language standard provides no guarantees about the alignment or
51579  * atomicity of device memory accesses. The recommended practice for writing
51580  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
51581  * alt_write_word() functions.
51582  *
51583  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR55_LOW.
51584  */
51585 struct ALT_EMAC_GMAC_MAC_ADDR55_LOW_s
51586 {
51587  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO */
51588 };
51589 
51590 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR55_LOW. */
51591 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR55_LOW_s ALT_EMAC_GMAC_MAC_ADDR55_LOW_t;
51592 #endif /* __ASSEMBLY__ */
51593 
51594 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_LOW register. */
51595 #define ALT_EMAC_GMAC_MAC_ADDR55_LOW_RESET 0xffffffff
51596 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR55_LOW register from the beginning of the component. */
51597 #define ALT_EMAC_GMAC_MAC_ADDR55_LOW_OFST 0x93c
51598 /* The address of the ALT_EMAC_GMAC_MAC_ADDR55_LOW register. */
51599 #define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR55_LOW_OFST))
51600 
51601 /*
51602  * Register : gmacgrp_mac_address56_high
51603  *
51604  * <b> Register 592 (MAC Address56 High Register) </b>
51605  *
51606  * The MAC Address56 High register holds the upper 16 bits of the 57th 6-byte MAC
51607  * address of the station.
51608  *
51609  * If the MAC address registers are configured to be double-synchronized to the
51610  * (G)MII clock domains, then
51611  *
51612  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
51613  * or Bits[7:0] (in big-endian mode) of the MAC Address56 Low Register are written.
51614  * For proper synchronization updates, consecutive writes to this MAC Address56 Low
51615  * Register must be performed after at least four clock cycles in the destination
51616  * clock domain.
51617  *
51618  * Register Layout
51619  *
51620  * Bits | Access | Reset | Description
51621  * :--------|:-------|:-------|:-----------------------------------------
51622  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI
51623  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR56_HIGH_RSVD_30_16
51624  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE
51625  *
51626  */
51627 /*
51628  * Field : addrhi
51629  *
51630  * MAC Address56 [47:32]
51631  *
51632  * This field contains the upper 16 bits (47:32) of the 57th 6-byte MAC address.
51633  *
51634  * Field Access Macros:
51635  *
51636  */
51637 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field. */
51638 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_LSB 0
51639 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field. */
51640 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_MSB 15
51641 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field. */
51642 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_WIDTH 16
51643 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field value. */
51644 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_SET_MSK 0x0000ffff
51645 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field value. */
51646 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_CLR_MSK 0xffff0000
51647 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field. */
51648 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_RESET 0xffff
51649 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI field value from a register. */
51650 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
51651 /* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field value suitable for setting the register. */
51652 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
51653 
51654 /*
51655  * Field : reserved_30_16
51656  *
51657  * Reserved
51658  *
51659  * Field Access Macros:
51660  *
51661  */
51662 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_RSVD_30_16 register field. */
51663 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_RSVD_30_16_LSB 16
51664 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_RSVD_30_16 register field. */
51665 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_RSVD_30_16_MSB 30
51666 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_RSVD_30_16 register field. */
51667 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_RSVD_30_16_WIDTH 15
51668 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_RSVD_30_16 register field value. */
51669 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
51670 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_RSVD_30_16 register field value. */
51671 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
51672 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_RSVD_30_16 register field. */
51673 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_RSVD_30_16_RESET 0x0
51674 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_RSVD_30_16 field value from a register. */
51675 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
51676 /* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_RSVD_30_16 register field value suitable for setting the register. */
51677 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
51678 
51679 /*
51680  * Field : ae
51681  *
51682  * Address Enable
51683  *
51684  * When this bit is set, the address filter module uses the 57th MAC address for
51685  * perfect filtering.
51686  *
51687  * When this bit is reset, the address filter module ignores the address for
51688  * filtering.
51689  *
51690  * Field Enumeration Values:
51691  *
51692  * Enum | Value | Description
51693  * :----------------------------------------|:------|:------------
51694  * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_E_DISD | 0x0 |
51695  * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_E_END | 0x1 |
51696  *
51697  * Field Access Macros:
51698  *
51699  */
51700 /*
51701  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE
51702  *
51703  */
51704 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_E_DISD 0x0
51705 /*
51706  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE
51707  *
51708  */
51709 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_E_END 0x1
51710 
51711 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field. */
51712 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_LSB 31
51713 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field. */
51714 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_MSB 31
51715 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field. */
51716 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_WIDTH 1
51717 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field value. */
51718 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_SET_MSK 0x80000000
51719 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field value. */
51720 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_CLR_MSK 0x7fffffff
51721 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field. */
51722 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_RESET 0x0
51723 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE field value from a register. */
51724 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
51725 /* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field value suitable for setting the register. */
51726 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
51727 
51728 #ifndef __ASSEMBLY__
51729 /*
51730  * WARNING: The C register and register group struct declarations are provided for
51731  * convenience and illustrative purposes. They should, however, be used with
51732  * caution as the C language standard provides no guarantees about the alignment or
51733  * atomicity of device memory accesses. The recommended practice for writing
51734  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
51735  * alt_write_word() functions.
51736  *
51737  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR56_HIGH.
51738  */
51739 struct ALT_EMAC_GMAC_MAC_ADDR56_HIGH_s
51740 {
51741  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI */
51742  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR56_HIGH_RSVD_30_16 */
51743  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE */
51744 };
51745 
51746 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR56_HIGH. */
51747 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR56_HIGH_s ALT_EMAC_GMAC_MAC_ADDR56_HIGH_t;
51748 #endif /* __ASSEMBLY__ */
51749 
51750 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH register. */
51751 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_RESET 0x0000ffff
51752 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH register from the beginning of the component. */
51753 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_OFST 0x940
51754 /* The address of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH register. */
51755 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR56_HIGH_OFST))
51756 
51757 /*
51758  * Register : gmacgrp_mac_address56_low
51759  *
51760  * <b> Register 593 (MAC Address56 Low Register) </b>
51761  *
51762  * The MAC Address56 Low register holds the lower 32 bits of the 57th 6-byte MAC
51763  * address of the station.
51764  *
51765  * Register Layout
51766  *
51767  * Bits | Access | Reset | Description
51768  * :-------|:-------|:-----------|:------------------------------------
51769  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO
51770  *
51771  */
51772 /*
51773  * Field : addrlo
51774  *
51775  * MAC Address56 [31:0]
51776  *
51777  * This field contains the lower 32 bits of the 57th 6-byte MAC address. The
51778  * content of this field is undefined until loaded by the Application after the
51779  * initialization process.
51780  *
51781  * Field Access Macros:
51782  *
51783  */
51784 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field. */
51785 #define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_LSB 0
51786 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field. */
51787 #define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_MSB 31
51788 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field. */
51789 #define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_WIDTH 32
51790 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field value. */
51791 #define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_SET_MSK 0xffffffff
51792 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field value. */
51793 #define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_CLR_MSK 0x00000000
51794 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field. */
51795 #define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_RESET 0xffffffff
51796 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO field value from a register. */
51797 #define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
51798 /* Produces a ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field value suitable for setting the register. */
51799 #define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
51800 
51801 #ifndef __ASSEMBLY__
51802 /*
51803  * WARNING: The C register and register group struct declarations are provided for
51804  * convenience and illustrative purposes. They should, however, be used with
51805  * caution as the C language standard provides no guarantees about the alignment or
51806  * atomicity of device memory accesses. The recommended practice for writing
51807  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
51808  * alt_write_word() functions.
51809  *
51810  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR56_LOW.
51811  */
51812 struct ALT_EMAC_GMAC_MAC_ADDR56_LOW_s
51813 {
51814  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO */
51815 };
51816 
51817 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR56_LOW. */
51818 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR56_LOW_s ALT_EMAC_GMAC_MAC_ADDR56_LOW_t;
51819 #endif /* __ASSEMBLY__ */
51820 
51821 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_LOW register. */
51822 #define ALT_EMAC_GMAC_MAC_ADDR56_LOW_RESET 0xffffffff
51823 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR56_LOW register from the beginning of the component. */
51824 #define ALT_EMAC_GMAC_MAC_ADDR56_LOW_OFST 0x944
51825 /* The address of the ALT_EMAC_GMAC_MAC_ADDR56_LOW register. */
51826 #define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR56_LOW_OFST))
51827 
51828 /*
51829  * Register : gmacgrp_mac_address57_high
51830  *
51831  * <b> Register 594 (MAC Address57 High Register) </b>
51832  *
51833  * The MAC Address57 High register holds the upper 16 bits of the 58th 6-byte MAC
51834  * address of the station.
51835  *
51836  * If the MAC address registers are configured to be double-synchronized to the
51837  * (G)MII clock domains, then
51838  *
51839  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
51840  * or Bits[7:0] (in big-endian mode) of the MAC Address57 Low Register are written.
51841  * For proper synchronization updates, consecutive writes to this MAC Address57 Low
51842  * Register must be performed after at least four clock cycles in the destination
51843  * clock domain.
51844  *
51845  * Register Layout
51846  *
51847  * Bits | Access | Reset | Description
51848  * :--------|:-------|:-------|:-----------------------------------------
51849  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI
51850  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR57_HIGH_RSVD_30_16
51851  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE
51852  *
51853  */
51854 /*
51855  * Field : addrhi
51856  *
51857  * MAC Address57 [47:32]
51858  *
51859  * This field contains the upper 16 bits (47:32) of the 58th 6-byte MAC address.
51860  *
51861  * Field Access Macros:
51862  *
51863  */
51864 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field. */
51865 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_LSB 0
51866 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field. */
51867 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_MSB 15
51868 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field. */
51869 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_WIDTH 16
51870 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field value. */
51871 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_SET_MSK 0x0000ffff
51872 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field value. */
51873 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_CLR_MSK 0xffff0000
51874 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field. */
51875 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_RESET 0xffff
51876 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI field value from a register. */
51877 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
51878 /* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field value suitable for setting the register. */
51879 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
51880 
51881 /*
51882  * Field : reserved_30_16
51883  *
51884  * Reserved
51885  *
51886  * Field Access Macros:
51887  *
51888  */
51889 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_RSVD_30_16 register field. */
51890 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_RSVD_30_16_LSB 16
51891 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_RSVD_30_16 register field. */
51892 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_RSVD_30_16_MSB 30
51893 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_RSVD_30_16 register field. */
51894 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_RSVD_30_16_WIDTH 15
51895 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_RSVD_30_16 register field value. */
51896 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
51897 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_RSVD_30_16 register field value. */
51898 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
51899 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_RSVD_30_16 register field. */
51900 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_RSVD_30_16_RESET 0x0
51901 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_RSVD_30_16 field value from a register. */
51902 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
51903 /* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_RSVD_30_16 register field value suitable for setting the register. */
51904 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
51905 
51906 /*
51907  * Field : ae
51908  *
51909  * Address Enable
51910  *
51911  * When this bit is set, the address filter module uses the 58th MAC address for
51912  * perfect filtering.
51913  *
51914  * When this bit is reset, the address filter module ignores the address for
51915  * filtering.
51916  *
51917  * Field Enumeration Values:
51918  *
51919  * Enum | Value | Description
51920  * :----------------------------------------|:------|:------------
51921  * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_E_DISD | 0x0 |
51922  * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_E_END | 0x1 |
51923  *
51924  * Field Access Macros:
51925  *
51926  */
51927 /*
51928  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE
51929  *
51930  */
51931 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_E_DISD 0x0
51932 /*
51933  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE
51934  *
51935  */
51936 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_E_END 0x1
51937 
51938 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field. */
51939 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_LSB 31
51940 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field. */
51941 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_MSB 31
51942 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field. */
51943 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_WIDTH 1
51944 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field value. */
51945 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_SET_MSK 0x80000000
51946 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field value. */
51947 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_CLR_MSK 0x7fffffff
51948 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field. */
51949 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_RESET 0x0
51950 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE field value from a register. */
51951 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
51952 /* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field value suitable for setting the register. */
51953 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
51954 
51955 #ifndef __ASSEMBLY__
51956 /*
51957  * WARNING: The C register and register group struct declarations are provided for
51958  * convenience and illustrative purposes. They should, however, be used with
51959  * caution as the C language standard provides no guarantees about the alignment or
51960  * atomicity of device memory accesses. The recommended practice for writing
51961  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
51962  * alt_write_word() functions.
51963  *
51964  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR57_HIGH.
51965  */
51966 struct ALT_EMAC_GMAC_MAC_ADDR57_HIGH_s
51967 {
51968  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI */
51969  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR57_HIGH_RSVD_30_16 */
51970  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE */
51971 };
51972 
51973 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR57_HIGH. */
51974 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR57_HIGH_s ALT_EMAC_GMAC_MAC_ADDR57_HIGH_t;
51975 #endif /* __ASSEMBLY__ */
51976 
51977 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH register. */
51978 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_RESET 0x0000ffff
51979 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH register from the beginning of the component. */
51980 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_OFST 0x948
51981 /* The address of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH register. */
51982 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR57_HIGH_OFST))
51983 
51984 /*
51985  * Register : gmacgrp_mac_address57_low
51986  *
51987  * <b> Register 595 (MAC Address57 Low Register)</b>
51988  *
51989  * The MAC Address57 Low register holds the lower 32 bits of the 58th 6-byte MAC
51990  * address of the station.
51991  *
51992  * Register Layout
51993  *
51994  * Bits | Access | Reset | Description
51995  * :-------|:-------|:-----------|:------------------------------------
51996  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO
51997  *
51998  */
51999 /*
52000  * Field : addrlo
52001  *
52002  * MAC Address57 [31:0]
52003  *
52004  * This field contains the lower 32 bits of the 58th 6-byte MAC address. The
52005  * content of this field is undefined until loaded by the Application after the
52006  * initialization process.
52007  *
52008  * Field Access Macros:
52009  *
52010  */
52011 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field. */
52012 #define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_LSB 0
52013 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field. */
52014 #define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_MSB 31
52015 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field. */
52016 #define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_WIDTH 32
52017 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field value. */
52018 #define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_SET_MSK 0xffffffff
52019 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field value. */
52020 #define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_CLR_MSK 0x00000000
52021 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field. */
52022 #define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_RESET 0xffffffff
52023 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO field value from a register. */
52024 #define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
52025 /* Produces a ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field value suitable for setting the register. */
52026 #define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
52027 
52028 #ifndef __ASSEMBLY__
52029 /*
52030  * WARNING: The C register and register group struct declarations are provided for
52031  * convenience and illustrative purposes. They should, however, be used with
52032  * caution as the C language standard provides no guarantees about the alignment or
52033  * atomicity of device memory accesses. The recommended practice for writing
52034  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
52035  * alt_write_word() functions.
52036  *
52037  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR57_LOW.
52038  */
52039 struct ALT_EMAC_GMAC_MAC_ADDR57_LOW_s
52040 {
52041  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO */
52042 };
52043 
52044 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR57_LOW. */
52045 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR57_LOW_s ALT_EMAC_GMAC_MAC_ADDR57_LOW_t;
52046 #endif /* __ASSEMBLY__ */
52047 
52048 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_LOW register. */
52049 #define ALT_EMAC_GMAC_MAC_ADDR57_LOW_RESET 0xffffffff
52050 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR57_LOW register from the beginning of the component. */
52051 #define ALT_EMAC_GMAC_MAC_ADDR57_LOW_OFST 0x94c
52052 /* The address of the ALT_EMAC_GMAC_MAC_ADDR57_LOW register. */
52053 #define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR57_LOW_OFST))
52054 
52055 /*
52056  * Register : gmacgrp_mac_address58_high
52057  *
52058  * <b> Register 596 (MAC Address58 High Register)</b>
52059  *
52060  * The MAC Address58 High register holds the upper 16 bits of the 59th 6-byte MAC
52061  * address of the station.
52062  *
52063  * If the MAC address registers are configured to be double-synchronized to the
52064  * (G)MII clock domains, then
52065  *
52066  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
52067  * or Bits[7:0] (in big-endian mode) of the MAC Address58 Low Register are written.
52068  * For proper synchronization updates, consecutive writes to this MAC Address58 Low
52069  * Register must be performed after at least four clock cycles in the destination
52070  * clock domain.
52071  *
52072  * Register Layout
52073  *
52074  * Bits | Access | Reset | Description
52075  * :--------|:-------|:-------|:-----------------------------------------
52076  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI
52077  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR58_HIGH_RSVD_30_16
52078  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE
52079  *
52080  */
52081 /*
52082  * Field : addrhi
52083  *
52084  * MAC Address58 [47:32]
52085  *
52086  * This field contains the upper 16 bits (47:32) of the 59th 6-byte MAC address.
52087  *
52088  * Field Access Macros:
52089  *
52090  */
52091 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field. */
52092 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_LSB 0
52093 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field. */
52094 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_MSB 15
52095 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field. */
52096 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_WIDTH 16
52097 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field value. */
52098 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_SET_MSK 0x0000ffff
52099 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field value. */
52100 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_CLR_MSK 0xffff0000
52101 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field. */
52102 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_RESET 0xffff
52103 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI field value from a register. */
52104 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
52105 /* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field value suitable for setting the register. */
52106 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
52107 
52108 /*
52109  * Field : reserved_30_16
52110  *
52111  * Reserved
52112  *
52113  * Field Access Macros:
52114  *
52115  */
52116 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_RSVD_30_16 register field. */
52117 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_RSVD_30_16_LSB 16
52118 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_RSVD_30_16 register field. */
52119 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_RSVD_30_16_MSB 30
52120 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_RSVD_30_16 register field. */
52121 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_RSVD_30_16_WIDTH 15
52122 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_RSVD_30_16 register field value. */
52123 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
52124 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_RSVD_30_16 register field value. */
52125 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
52126 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_RSVD_30_16 register field. */
52127 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_RSVD_30_16_RESET 0x0
52128 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_RSVD_30_16 field value from a register. */
52129 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
52130 /* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_RSVD_30_16 register field value suitable for setting the register. */
52131 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
52132 
52133 /*
52134  * Field : ae
52135  *
52136  * Address Enable
52137  *
52138  * When this bit is set, the address filter module uses the 59th MAC address for
52139  * perfect filtering.
52140  *
52141  * When this bit is reset, the address filter module ignores the address for
52142  * filtering.
52143  *
52144  * Field Enumeration Values:
52145  *
52146  * Enum | Value | Description
52147  * :----------------------------------------|:------|:------------
52148  * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_E_DISD | 0x0 |
52149  * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_E_END | 0x1 |
52150  *
52151  * Field Access Macros:
52152  *
52153  */
52154 /*
52155  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE
52156  *
52157  */
52158 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_E_DISD 0x0
52159 /*
52160  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE
52161  *
52162  */
52163 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_E_END 0x1
52164 
52165 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field. */
52166 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_LSB 31
52167 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field. */
52168 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_MSB 31
52169 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field. */
52170 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_WIDTH 1
52171 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field value. */
52172 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_SET_MSK 0x80000000
52173 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field value. */
52174 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_CLR_MSK 0x7fffffff
52175 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field. */
52176 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_RESET 0x0
52177 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE field value from a register. */
52178 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
52179 /* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field value suitable for setting the register. */
52180 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
52181 
52182 #ifndef __ASSEMBLY__
52183 /*
52184  * WARNING: The C register and register group struct declarations are provided for
52185  * convenience and illustrative purposes. They should, however, be used with
52186  * caution as the C language standard provides no guarantees about the alignment or
52187  * atomicity of device memory accesses. The recommended practice for writing
52188  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
52189  * alt_write_word() functions.
52190  *
52191  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR58_HIGH.
52192  */
52193 struct ALT_EMAC_GMAC_MAC_ADDR58_HIGH_s
52194 {
52195  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI */
52196  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR58_HIGH_RSVD_30_16 */
52197  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE */
52198 };
52199 
52200 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR58_HIGH. */
52201 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR58_HIGH_s ALT_EMAC_GMAC_MAC_ADDR58_HIGH_t;
52202 #endif /* __ASSEMBLY__ */
52203 
52204 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH register. */
52205 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_RESET 0x0000ffff
52206 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH register from the beginning of the component. */
52207 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_OFST 0x950
52208 /* The address of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH register. */
52209 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR58_HIGH_OFST))
52210 
52211 /*
52212  * Register : gmacgrp_mac_address58_low
52213  *
52214  * <b> Register 597 (MAC Address58 Low Register)</b>
52215  *
52216  * The MAC Address58 Low register holds the lower 32 bits of the 59th 6-byte MAC
52217  * address of the station.
52218  *
52219  * Register Layout
52220  *
52221  * Bits | Access | Reset | Description
52222  * :-------|:-------|:-----------|:------------------------------------
52223  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO
52224  *
52225  */
52226 /*
52227  * Field : addrlo
52228  *
52229  * MAC Address58 [31:0]
52230  *
52231  * This field contains the lower 32 bits of the 59th 6-byte MAC address. The
52232  * content of this field is undefined until loaded by the Application after the
52233  * initialization process.
52234  *
52235  * Field Access Macros:
52236  *
52237  */
52238 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field. */
52239 #define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_LSB 0
52240 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field. */
52241 #define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_MSB 31
52242 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field. */
52243 #define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_WIDTH 32
52244 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field value. */
52245 #define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_SET_MSK 0xffffffff
52246 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field value. */
52247 #define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_CLR_MSK 0x00000000
52248 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field. */
52249 #define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_RESET 0xffffffff
52250 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO field value from a register. */
52251 #define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
52252 /* Produces a ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field value suitable for setting the register. */
52253 #define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
52254 
52255 #ifndef __ASSEMBLY__
52256 /*
52257  * WARNING: The C register and register group struct declarations are provided for
52258  * convenience and illustrative purposes. They should, however, be used with
52259  * caution as the C language standard provides no guarantees about the alignment or
52260  * atomicity of device memory accesses. The recommended practice for writing
52261  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
52262  * alt_write_word() functions.
52263  *
52264  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR58_LOW.
52265  */
52266 struct ALT_EMAC_GMAC_MAC_ADDR58_LOW_s
52267 {
52268  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO */
52269 };
52270 
52271 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR58_LOW. */
52272 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR58_LOW_s ALT_EMAC_GMAC_MAC_ADDR58_LOW_t;
52273 #endif /* __ASSEMBLY__ */
52274 
52275 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_LOW register. */
52276 #define ALT_EMAC_GMAC_MAC_ADDR58_LOW_RESET 0xffffffff
52277 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR58_LOW register from the beginning of the component. */
52278 #define ALT_EMAC_GMAC_MAC_ADDR58_LOW_OFST 0x954
52279 /* The address of the ALT_EMAC_GMAC_MAC_ADDR58_LOW register. */
52280 #define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR58_LOW_OFST))
52281 
52282 /*
52283  * Register : gmacgrp_mac_address59_high
52284  *
52285  * <b> Register 598 (MAC Address59 High Register) </b>
52286  *
52287  * The MAC Address59 High register holds the upper 16 bits of the 60th 6-byte MAC
52288  * address of the station.
52289  *
52290  * If the MAC address registers are configured to be double-synchronized to the
52291  * (G)MII clock domains, then
52292  *
52293  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
52294  * or Bits[7:0] (in big-endian mode) of the MAC Address59 Low Register are written.
52295  * For proper synchronization updates, consecutive writes to this MAC Address59 Low
52296  * Register must be performed after at least four clock cycles in the destination
52297  * clock domain.
52298  *
52299  * Register Layout
52300  *
52301  * Bits | Access | Reset | Description
52302  * :--------|:-------|:-------|:-----------------------------------------
52303  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI
52304  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR59_HIGH_RSVD_30_16
52305  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE
52306  *
52307  */
52308 /*
52309  * Field : addrhi
52310  *
52311  * MAC Address59 [47:32]
52312  *
52313  * This field contains the upper 16 bits (47:32) of the 60th 6-byte MAC address.
52314  *
52315  * Field Access Macros:
52316  *
52317  */
52318 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field. */
52319 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_LSB 0
52320 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field. */
52321 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_MSB 15
52322 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field. */
52323 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_WIDTH 16
52324 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field value. */
52325 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_SET_MSK 0x0000ffff
52326 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field value. */
52327 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_CLR_MSK 0xffff0000
52328 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field. */
52329 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_RESET 0xffff
52330 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI field value from a register. */
52331 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
52332 /* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field value suitable for setting the register. */
52333 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
52334 
52335 /*
52336  * Field : reserved_30_16
52337  *
52338  * Reserved
52339  *
52340  * Field Access Macros:
52341  *
52342  */
52343 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_RSVD_30_16 register field. */
52344 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_RSVD_30_16_LSB 16
52345 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_RSVD_30_16 register field. */
52346 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_RSVD_30_16_MSB 30
52347 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_RSVD_30_16 register field. */
52348 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_RSVD_30_16_WIDTH 15
52349 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_RSVD_30_16 register field value. */
52350 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
52351 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_RSVD_30_16 register field value. */
52352 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
52353 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_RSVD_30_16 register field. */
52354 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_RSVD_30_16_RESET 0x0
52355 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_RSVD_30_16 field value from a register. */
52356 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
52357 /* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_RSVD_30_16 register field value suitable for setting the register. */
52358 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
52359 
52360 /*
52361  * Field : ae
52362  *
52363  * Address Enable
52364  *
52365  * When this bit is set, the address filter module uses the 60th MAC address for
52366  * perfect filtering.
52367  *
52368  * When this bit is reset, the address filter module ignores the address for
52369  * filtering.
52370  *
52371  * Field Enumeration Values:
52372  *
52373  * Enum | Value | Description
52374  * :----------------------------------------|:------|:------------
52375  * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_E_DISD | 0x0 |
52376  * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_E_END | 0x1 |
52377  *
52378  * Field Access Macros:
52379  *
52380  */
52381 /*
52382  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE
52383  *
52384  */
52385 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_E_DISD 0x0
52386 /*
52387  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE
52388  *
52389  */
52390 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_E_END 0x1
52391 
52392 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field. */
52393 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_LSB 31
52394 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field. */
52395 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_MSB 31
52396 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field. */
52397 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_WIDTH 1
52398 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field value. */
52399 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_SET_MSK 0x80000000
52400 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field value. */
52401 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_CLR_MSK 0x7fffffff
52402 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field. */
52403 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_RESET 0x0
52404 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE field value from a register. */
52405 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
52406 /* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field value suitable for setting the register. */
52407 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
52408 
52409 #ifndef __ASSEMBLY__
52410 /*
52411  * WARNING: The C register and register group struct declarations are provided for
52412  * convenience and illustrative purposes. They should, however, be used with
52413  * caution as the C language standard provides no guarantees about the alignment or
52414  * atomicity of device memory accesses. The recommended practice for writing
52415  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
52416  * alt_write_word() functions.
52417  *
52418  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR59_HIGH.
52419  */
52420 struct ALT_EMAC_GMAC_MAC_ADDR59_HIGH_s
52421 {
52422  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI */
52423  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR59_HIGH_RSVD_30_16 */
52424  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE */
52425 };
52426 
52427 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR59_HIGH. */
52428 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR59_HIGH_s ALT_EMAC_GMAC_MAC_ADDR59_HIGH_t;
52429 #endif /* __ASSEMBLY__ */
52430 
52431 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH register. */
52432 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_RESET 0x0000ffff
52433 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH register from the beginning of the component. */
52434 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_OFST 0x958
52435 /* The address of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH register. */
52436 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR59_HIGH_OFST))
52437 
52438 /*
52439  * Register : gmacgrp_mac_address59_low
52440  *
52441  * <b> Register 599 (MAC Address59 Low Register) </b>
52442  *
52443  * The MAC Address59 Low register holds the lower 32 bits of the 60th 6-byte MAC
52444  * address of the station.
52445  *
52446  * Register Layout
52447  *
52448  * Bits | Access | Reset | Description
52449  * :-------|:-------|:-----------|:------------------------------------
52450  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO
52451  *
52452  */
52453 /*
52454  * Field : addrlo
52455  *
52456  * MAC Address59 [31:0]
52457  *
52458  * This field contains the lower 32 bits of the 60th 6-byte MAC address. The
52459  * content of this field is undefined until loaded by the Application after the
52460  * initialization process.
52461  *
52462  * Field Access Macros:
52463  *
52464  */
52465 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field. */
52466 #define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_LSB 0
52467 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field. */
52468 #define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_MSB 31
52469 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field. */
52470 #define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_WIDTH 32
52471 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field value. */
52472 #define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_SET_MSK 0xffffffff
52473 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field value. */
52474 #define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_CLR_MSK 0x00000000
52475 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field. */
52476 #define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_RESET 0xffffffff
52477 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO field value from a register. */
52478 #define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
52479 /* Produces a ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field value suitable for setting the register. */
52480 #define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
52481 
52482 #ifndef __ASSEMBLY__
52483 /*
52484  * WARNING: The C register and register group struct declarations are provided for
52485  * convenience and illustrative purposes. They should, however, be used with
52486  * caution as the C language standard provides no guarantees about the alignment or
52487  * atomicity of device memory accesses. The recommended practice for writing
52488  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
52489  * alt_write_word() functions.
52490  *
52491  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR59_LOW.
52492  */
52493 struct ALT_EMAC_GMAC_MAC_ADDR59_LOW_s
52494 {
52495  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO */
52496 };
52497 
52498 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR59_LOW. */
52499 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR59_LOW_s ALT_EMAC_GMAC_MAC_ADDR59_LOW_t;
52500 #endif /* __ASSEMBLY__ */
52501 
52502 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_LOW register. */
52503 #define ALT_EMAC_GMAC_MAC_ADDR59_LOW_RESET 0xffffffff
52504 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR59_LOW register from the beginning of the component. */
52505 #define ALT_EMAC_GMAC_MAC_ADDR59_LOW_OFST 0x95c
52506 /* The address of the ALT_EMAC_GMAC_MAC_ADDR59_LOW register. */
52507 #define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR59_LOW_OFST))
52508 
52509 /*
52510  * Register : gmacgrp_mac_address60_high
52511  *
52512  * <b> Register 600 (MAC Address60 High Register) </b>
52513  *
52514  * The MAC Address60 High register holds the upper 16 bits of the 61st 6-byte MAC
52515  * address of the station.
52516  *
52517  * If the MAC address registers are configured to be double-synchronized to the
52518  * (G)MII clock domains, then
52519  *
52520  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
52521  * or Bits[7:0] (in big-endian mode) of the MAC Address60 Low Register are written.
52522  * For proper synchronization updates, consecutive writes to this MAC Address60 Low
52523  * Register must be performed after at least four clock cycles in the destination
52524  * clock domain.
52525  *
52526  * Register Layout
52527  *
52528  * Bits | Access | Reset | Description
52529  * :--------|:-------|:-------|:-----------------------------------------
52530  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI
52531  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR60_HIGH_RSVD_30_16
52532  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE
52533  *
52534  */
52535 /*
52536  * Field : addrhi
52537  *
52538  * MAC Address60 [47:32]
52539  *
52540  * This field contains the upper 16 bits (47:32) of the 61st 6-byte MAC address.
52541  *
52542  * Field Access Macros:
52543  *
52544  */
52545 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field. */
52546 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_LSB 0
52547 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field. */
52548 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_MSB 15
52549 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field. */
52550 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_WIDTH 16
52551 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field value. */
52552 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_SET_MSK 0x0000ffff
52553 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field value. */
52554 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_CLR_MSK 0xffff0000
52555 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field. */
52556 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_RESET 0xffff
52557 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI field value from a register. */
52558 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
52559 /* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field value suitable for setting the register. */
52560 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
52561 
52562 /*
52563  * Field : reserved_30_16
52564  *
52565  * Reserved
52566  *
52567  * Field Access Macros:
52568  *
52569  */
52570 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_RSVD_30_16 register field. */
52571 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_RSVD_30_16_LSB 16
52572 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_RSVD_30_16 register field. */
52573 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_RSVD_30_16_MSB 30
52574 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_RSVD_30_16 register field. */
52575 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_RSVD_30_16_WIDTH 15
52576 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_RSVD_30_16 register field value. */
52577 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
52578 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_RSVD_30_16 register field value. */
52579 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
52580 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_RSVD_30_16 register field. */
52581 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_RSVD_30_16_RESET 0x0
52582 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_RSVD_30_16 field value from a register. */
52583 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
52584 /* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_RSVD_30_16 register field value suitable for setting the register. */
52585 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
52586 
52587 /*
52588  * Field : ae
52589  *
52590  * Address Enable
52591  *
52592  * When this bit is set, the address filter module uses the 61st MAC address for
52593  * perfect filtering.
52594  *
52595  * When this bit is reset, the address filter module ignores the address for
52596  * filtering.
52597  *
52598  * Field Enumeration Values:
52599  *
52600  * Enum | Value | Description
52601  * :----------------------------------------|:------|:------------
52602  * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_E_DISD | 0x0 |
52603  * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_E_END | 0x1 |
52604  *
52605  * Field Access Macros:
52606  *
52607  */
52608 /*
52609  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE
52610  *
52611  */
52612 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_E_DISD 0x0
52613 /*
52614  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE
52615  *
52616  */
52617 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_E_END 0x1
52618 
52619 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field. */
52620 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_LSB 31
52621 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field. */
52622 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_MSB 31
52623 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field. */
52624 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_WIDTH 1
52625 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field value. */
52626 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_SET_MSK 0x80000000
52627 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field value. */
52628 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_CLR_MSK 0x7fffffff
52629 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field. */
52630 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_RESET 0x0
52631 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE field value from a register. */
52632 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
52633 /* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field value suitable for setting the register. */
52634 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
52635 
52636 #ifndef __ASSEMBLY__
52637 /*
52638  * WARNING: The C register and register group struct declarations are provided for
52639  * convenience and illustrative purposes. They should, however, be used with
52640  * caution as the C language standard provides no guarantees about the alignment or
52641  * atomicity of device memory accesses. The recommended practice for writing
52642  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
52643  * alt_write_word() functions.
52644  *
52645  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR60_HIGH.
52646  */
52647 struct ALT_EMAC_GMAC_MAC_ADDR60_HIGH_s
52648 {
52649  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI */
52650  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR60_HIGH_RSVD_30_16 */
52651  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE */
52652 };
52653 
52654 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR60_HIGH. */
52655 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR60_HIGH_s ALT_EMAC_GMAC_MAC_ADDR60_HIGH_t;
52656 #endif /* __ASSEMBLY__ */
52657 
52658 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH register. */
52659 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_RESET 0x0000ffff
52660 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH register from the beginning of the component. */
52661 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_OFST 0x960
52662 /* The address of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH register. */
52663 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR60_HIGH_OFST))
52664 
52665 /*
52666  * Register : gmacgrp_mac_address60_low
52667  *
52668  * <b> Register 601 (MAC Address60 Low Register) </b>
52669  *
52670  * The MAC Address60 Low register holds the lower 32 bits of the 61st 6-byte MAC
52671  * address of the station.
52672  *
52673  * Register Layout
52674  *
52675  * Bits | Access | Reset | Description
52676  * :-------|:-------|:-----------|:------------------------------------
52677  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO
52678  *
52679  */
52680 /*
52681  * Field : addrlo
52682  *
52683  * MAC Address60 [31:0]
52684  *
52685  * This field contains the lower 32 bits of the 61st 6-byte MAC address. The
52686  * content of this field is undefined until loaded by the Application after the
52687  * initialization process.
52688  *
52689  * Field Access Macros:
52690  *
52691  */
52692 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field. */
52693 #define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_LSB 0
52694 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field. */
52695 #define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_MSB 31
52696 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field. */
52697 #define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_WIDTH 32
52698 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field value. */
52699 #define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_SET_MSK 0xffffffff
52700 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field value. */
52701 #define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_CLR_MSK 0x00000000
52702 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field. */
52703 #define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_RESET 0xffffffff
52704 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO field value from a register. */
52705 #define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
52706 /* Produces a ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field value suitable for setting the register. */
52707 #define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
52708 
52709 #ifndef __ASSEMBLY__
52710 /*
52711  * WARNING: The C register and register group struct declarations are provided for
52712  * convenience and illustrative purposes. They should, however, be used with
52713  * caution as the C language standard provides no guarantees about the alignment or
52714  * atomicity of device memory accesses. The recommended practice for writing
52715  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
52716  * alt_write_word() functions.
52717  *
52718  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR60_LOW.
52719  */
52720 struct ALT_EMAC_GMAC_MAC_ADDR60_LOW_s
52721 {
52722  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO */
52723 };
52724 
52725 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR60_LOW. */
52726 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR60_LOW_s ALT_EMAC_GMAC_MAC_ADDR60_LOW_t;
52727 #endif /* __ASSEMBLY__ */
52728 
52729 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_LOW register. */
52730 #define ALT_EMAC_GMAC_MAC_ADDR60_LOW_RESET 0xffffffff
52731 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR60_LOW register from the beginning of the component. */
52732 #define ALT_EMAC_GMAC_MAC_ADDR60_LOW_OFST 0x964
52733 /* The address of the ALT_EMAC_GMAC_MAC_ADDR60_LOW register. */
52734 #define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR60_LOW_OFST))
52735 
52736 /*
52737  * Register : gmacgrp_mac_address61_high
52738  *
52739  * <b> Register 602 (MAC Address61 High Register) </b>
52740  *
52741  * The MAC Address61 High register holds the upper 16 bits of the 62nd 6-byte MAC
52742  * address of the station.
52743  *
52744  * If the MAC address registers are configured to be double-synchronized to the
52745  * (G)MII clock domains, then
52746  *
52747  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
52748  * or Bits[7:0] (in big-endian mode) of the MAC Address61 Low Register are written.
52749  * For proper synchronization updates, consecutive writes to this MAC Address61 Low
52750  * Register must be performed after at least four clock cycles in the destination
52751  * clock domain.
52752  *
52753  * Register Layout
52754  *
52755  * Bits | Access | Reset | Description
52756  * :--------|:-------|:-------|:-----------------------------------------
52757  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI
52758  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR61_HIGH_RSVD_30_16
52759  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE
52760  *
52761  */
52762 /*
52763  * Field : addrhi
52764  *
52765  * MAC Address61 [47:32]
52766  *
52767  * This field contains the upper 16 bits (47:32) of the 62nd 6-byte MAC address.
52768  *
52769  * Field Access Macros:
52770  *
52771  */
52772 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field. */
52773 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_LSB 0
52774 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field. */
52775 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_MSB 15
52776 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field. */
52777 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_WIDTH 16
52778 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field value. */
52779 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_SET_MSK 0x0000ffff
52780 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field value. */
52781 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_CLR_MSK 0xffff0000
52782 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field. */
52783 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_RESET 0xffff
52784 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI field value from a register. */
52785 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
52786 /* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field value suitable for setting the register. */
52787 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
52788 
52789 /*
52790  * Field : reserved_30_16
52791  *
52792  * Reserved
52793  *
52794  * Field Access Macros:
52795  *
52796  */
52797 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_RSVD_30_16 register field. */
52798 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_RSVD_30_16_LSB 16
52799 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_RSVD_30_16 register field. */
52800 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_RSVD_30_16_MSB 30
52801 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_RSVD_30_16 register field. */
52802 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_RSVD_30_16_WIDTH 15
52803 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_RSVD_30_16 register field value. */
52804 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
52805 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_RSVD_30_16 register field value. */
52806 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
52807 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_RSVD_30_16 register field. */
52808 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_RSVD_30_16_RESET 0x0
52809 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_RSVD_30_16 field value from a register. */
52810 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
52811 /* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_RSVD_30_16 register field value suitable for setting the register. */
52812 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
52813 
52814 /*
52815  * Field : ae
52816  *
52817  * Address Enable
52818  *
52819  * When this bit is set, the address filter module uses the 62nd MAC address for
52820  * perfect filtering.
52821  *
52822  * When this bit is reset, the address filter module ignores the address for
52823  * filtering.
52824  *
52825  * Field Enumeration Values:
52826  *
52827  * Enum | Value | Description
52828  * :----------------------------------------|:------|:------------
52829  * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_E_DISD | 0x0 |
52830  * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_E_END | 0x1 |
52831  *
52832  * Field Access Macros:
52833  *
52834  */
52835 /*
52836  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE
52837  *
52838  */
52839 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_E_DISD 0x0
52840 /*
52841  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE
52842  *
52843  */
52844 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_E_END 0x1
52845 
52846 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field. */
52847 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_LSB 31
52848 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field. */
52849 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_MSB 31
52850 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field. */
52851 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_WIDTH 1
52852 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field value. */
52853 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_SET_MSK 0x80000000
52854 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field value. */
52855 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_CLR_MSK 0x7fffffff
52856 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field. */
52857 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_RESET 0x0
52858 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE field value from a register. */
52859 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
52860 /* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field value suitable for setting the register. */
52861 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
52862 
52863 #ifndef __ASSEMBLY__
52864 /*
52865  * WARNING: The C register and register group struct declarations are provided for
52866  * convenience and illustrative purposes. They should, however, be used with
52867  * caution as the C language standard provides no guarantees about the alignment or
52868  * atomicity of device memory accesses. The recommended practice for writing
52869  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
52870  * alt_write_word() functions.
52871  *
52872  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR61_HIGH.
52873  */
52874 struct ALT_EMAC_GMAC_MAC_ADDR61_HIGH_s
52875 {
52876  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI */
52877  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR61_HIGH_RSVD_30_16 */
52878  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE */
52879 };
52880 
52881 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR61_HIGH. */
52882 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR61_HIGH_s ALT_EMAC_GMAC_MAC_ADDR61_HIGH_t;
52883 #endif /* __ASSEMBLY__ */
52884 
52885 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH register. */
52886 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_RESET 0x0000ffff
52887 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH register from the beginning of the component. */
52888 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_OFST 0x968
52889 /* The address of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH register. */
52890 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR61_HIGH_OFST))
52891 
52892 /*
52893  * Register : gmacgrp_mac_address61_low
52894  *
52895  * <b> Register 603 (MAC Address61 Low Register)</b>
52896  *
52897  * The MAC Address61 Low register holds the lower 32 bits of the 62nd 6-byte MAC
52898  * address of the station.
52899  *
52900  * Register Layout
52901  *
52902  * Bits | Access | Reset | Description
52903  * :-------|:-------|:-----------|:------------------------------------
52904  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO
52905  *
52906  */
52907 /*
52908  * Field : addrlo
52909  *
52910  * MAC Address61 [31:0]
52911  *
52912  * This field contains the lower 32 bits of the 62nd 6-byte MAC address. The
52913  * content of this field is undefined until loaded by the Application after the
52914  * initialization process.
52915  *
52916  * Field Access Macros:
52917  *
52918  */
52919 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field. */
52920 #define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_LSB 0
52921 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field. */
52922 #define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_MSB 31
52923 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field. */
52924 #define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_WIDTH 32
52925 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field value. */
52926 #define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_SET_MSK 0xffffffff
52927 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field value. */
52928 #define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_CLR_MSK 0x00000000
52929 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field. */
52930 #define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_RESET 0xffffffff
52931 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO field value from a register. */
52932 #define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
52933 /* Produces a ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field value suitable for setting the register. */
52934 #define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
52935 
52936 #ifndef __ASSEMBLY__
52937 /*
52938  * WARNING: The C register and register group struct declarations are provided for
52939  * convenience and illustrative purposes. They should, however, be used with
52940  * caution as the C language standard provides no guarantees about the alignment or
52941  * atomicity of device memory accesses. The recommended practice for writing
52942  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
52943  * alt_write_word() functions.
52944  *
52945  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR61_LOW.
52946  */
52947 struct ALT_EMAC_GMAC_MAC_ADDR61_LOW_s
52948 {
52949  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO */
52950 };
52951 
52952 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR61_LOW. */
52953 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR61_LOW_s ALT_EMAC_GMAC_MAC_ADDR61_LOW_t;
52954 #endif /* __ASSEMBLY__ */
52955 
52956 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_LOW register. */
52957 #define ALT_EMAC_GMAC_MAC_ADDR61_LOW_RESET 0xffffffff
52958 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR61_LOW register from the beginning of the component. */
52959 #define ALT_EMAC_GMAC_MAC_ADDR61_LOW_OFST 0x96c
52960 /* The address of the ALT_EMAC_GMAC_MAC_ADDR61_LOW register. */
52961 #define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR61_LOW_OFST))
52962 
52963 /*
52964  * Register : gmacgrp_mac_address62_high
52965  *
52966  * <b> Register 604 (MAC Address62 High Register)</b>
52967  *
52968  * The MAC Address62 High register holds the upper 16 bits of the 63rd 6-byte MAC
52969  * address of the station.
52970  *
52971  * If the MAC address registers are configured to be double-synchronized to the
52972  * (G)MII clock domains, then
52973  *
52974  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
52975  * or Bits[7:0] (in big-endian mode) of the MAC Address62 Low Register are written.
52976  * For proper synchronization updates, consecutive writes to this MAC Address62 Low
52977  * Register must be performed after at least four clock cycles in the destination
52978  * clock domain.
52979  *
52980  * Register Layout
52981  *
52982  * Bits | Access | Reset | Description
52983  * :--------|:-------|:-------|:-----------------------------------------
52984  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI
52985  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR62_HIGH_RSVD_30_16
52986  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE
52987  *
52988  */
52989 /*
52990  * Field : addrhi
52991  *
52992  * MAC Address62 [47:32]
52993  *
52994  * This field contains the upper 16 bits (47:32) of the 63rd 6-byte MAC address.
52995  *
52996  * Field Access Macros:
52997  *
52998  */
52999 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field. */
53000 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_LSB 0
53001 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field. */
53002 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_MSB 15
53003 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field. */
53004 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_WIDTH 16
53005 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field value. */
53006 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_SET_MSK 0x0000ffff
53007 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field value. */
53008 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_CLR_MSK 0xffff0000
53009 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field. */
53010 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_RESET 0xffff
53011 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI field value from a register. */
53012 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
53013 /* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field value suitable for setting the register. */
53014 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
53015 
53016 /*
53017  * Field : reserved_30_16
53018  *
53019  * Reserved
53020  *
53021  * Field Access Macros:
53022  *
53023  */
53024 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_RSVD_30_16 register field. */
53025 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_RSVD_30_16_LSB 16
53026 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_RSVD_30_16 register field. */
53027 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_RSVD_30_16_MSB 30
53028 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_RSVD_30_16 register field. */
53029 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_RSVD_30_16_WIDTH 15
53030 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_RSVD_30_16 register field value. */
53031 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
53032 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_RSVD_30_16 register field value. */
53033 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
53034 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_RSVD_30_16 register field. */
53035 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_RSVD_30_16_RESET 0x0
53036 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_RSVD_30_16 field value from a register. */
53037 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
53038 /* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_RSVD_30_16 register field value suitable for setting the register. */
53039 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
53040 
53041 /*
53042  * Field : ae
53043  *
53044  * Address Enable
53045  *
53046  * When this bit is set, the address filter module uses the 63rd MAC address for
53047  * perfect filtering.
53048  *
53049  * When this bit is reset, the address filter module ignores the address for
53050  * filtering.
53051  *
53052  * Field Enumeration Values:
53053  *
53054  * Enum | Value | Description
53055  * :----------------------------------------|:------|:------------
53056  * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_E_DISD | 0x0 |
53057  * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_E_END | 0x1 |
53058  *
53059  * Field Access Macros:
53060  *
53061  */
53062 /*
53063  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE
53064  *
53065  */
53066 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_E_DISD 0x0
53067 /*
53068  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE
53069  *
53070  */
53071 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_E_END 0x1
53072 
53073 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field. */
53074 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_LSB 31
53075 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field. */
53076 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_MSB 31
53077 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field. */
53078 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_WIDTH 1
53079 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field value. */
53080 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_SET_MSK 0x80000000
53081 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field value. */
53082 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_CLR_MSK 0x7fffffff
53083 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field. */
53084 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_RESET 0x0
53085 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE field value from a register. */
53086 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
53087 /* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field value suitable for setting the register. */
53088 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
53089 
53090 #ifndef __ASSEMBLY__
53091 /*
53092  * WARNING: The C register and register group struct declarations are provided for
53093  * convenience and illustrative purposes. They should, however, be used with
53094  * caution as the C language standard provides no guarantees about the alignment or
53095  * atomicity of device memory accesses. The recommended practice for writing
53096  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
53097  * alt_write_word() functions.
53098  *
53099  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR62_HIGH.
53100  */
53101 struct ALT_EMAC_GMAC_MAC_ADDR62_HIGH_s
53102 {
53103  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI */
53104  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR62_HIGH_RSVD_30_16 */
53105  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE */
53106 };
53107 
53108 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR62_HIGH. */
53109 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR62_HIGH_s ALT_EMAC_GMAC_MAC_ADDR62_HIGH_t;
53110 #endif /* __ASSEMBLY__ */
53111 
53112 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH register. */
53113 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_RESET 0x0000ffff
53114 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH register from the beginning of the component. */
53115 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_OFST 0x970
53116 /* The address of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH register. */
53117 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR62_HIGH_OFST))
53118 
53119 /*
53120  * Register : gmacgrp_mac_address62_low
53121  *
53122  * <b> Register 605 (MAC Address62 Low Register)</b>
53123  *
53124  * The MAC Address62 Low register holds the lower 32 bits of the 63rd 6-byte MAC
53125  * address of the station.
53126  *
53127  * Register Layout
53128  *
53129  * Bits | Access | Reset | Description
53130  * :-------|:-------|:-----------|:------------------------------------
53131  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO
53132  *
53133  */
53134 /*
53135  * Field : addrlo
53136  *
53137  * MAC Address62 [31:0]
53138  *
53139  * This field contains the lower 32 bits of the 63rd 6-byte MAC address. The
53140  * content of this field is undefined until loaded by the Application after the
53141  * initialization process.
53142  *
53143  * Field Access Macros:
53144  *
53145  */
53146 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field. */
53147 #define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_LSB 0
53148 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field. */
53149 #define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_MSB 31
53150 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field. */
53151 #define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_WIDTH 32
53152 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field value. */
53153 #define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_SET_MSK 0xffffffff
53154 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field value. */
53155 #define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_CLR_MSK 0x00000000
53156 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field. */
53157 #define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_RESET 0xffffffff
53158 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO field value from a register. */
53159 #define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
53160 /* Produces a ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field value suitable for setting the register. */
53161 #define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
53162 
53163 #ifndef __ASSEMBLY__
53164 /*
53165  * WARNING: The C register and register group struct declarations are provided for
53166  * convenience and illustrative purposes. They should, however, be used with
53167  * caution as the C language standard provides no guarantees about the alignment or
53168  * atomicity of device memory accesses. The recommended practice for writing
53169  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
53170  * alt_write_word() functions.
53171  *
53172  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR62_LOW.
53173  */
53174 struct ALT_EMAC_GMAC_MAC_ADDR62_LOW_s
53175 {
53176  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO */
53177 };
53178 
53179 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR62_LOW. */
53180 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR62_LOW_s ALT_EMAC_GMAC_MAC_ADDR62_LOW_t;
53181 #endif /* __ASSEMBLY__ */
53182 
53183 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_LOW register. */
53184 #define ALT_EMAC_GMAC_MAC_ADDR62_LOW_RESET 0xffffffff
53185 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR62_LOW register from the beginning of the component. */
53186 #define ALT_EMAC_GMAC_MAC_ADDR62_LOW_OFST 0x974
53187 /* The address of the ALT_EMAC_GMAC_MAC_ADDR62_LOW register. */
53188 #define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR62_LOW_OFST))
53189 
53190 /*
53191  * Register : gmacgrp_mac_address63_high
53192  *
53193  * <b> Register 606 (MAC Address63 High Register) </b>
53194  *
53195  * The MAC Address63 High register holds the upper 16 bits of the 64th 6-byte MAC
53196  * address of the station.
53197  *
53198  * If the MAC address registers are configured to be double-synchronized to the
53199  * (G)MII clock domains, then
53200  *
53201  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
53202  * or Bits[7:0] (in big-endian mode) of the MAC Address63 Low Register are written.
53203  * For proper synchronization updates, consecutive writes to this MAC Address63 Low
53204  * Register must be performed after at least four clock cycles in the destination
53205  * clock domain.
53206  *
53207  * Register Layout
53208  *
53209  * Bits | Access | Reset | Description
53210  * :--------|:-------|:-------|:-----------------------------------------
53211  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI
53212  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR63_HIGH_RSVD_30_16
53213  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE
53214  *
53215  */
53216 /*
53217  * Field : addrhi
53218  *
53219  * MAC Address63 [47:32]
53220  *
53221  * This field contains the upper 16 bits (47:32) of the 64th 6-byte MAC address.
53222  *
53223  * Field Access Macros:
53224  *
53225  */
53226 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field. */
53227 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_LSB 0
53228 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field. */
53229 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_MSB 15
53230 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field. */
53231 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_WIDTH 16
53232 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field value. */
53233 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_SET_MSK 0x0000ffff
53234 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field value. */
53235 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_CLR_MSK 0xffff0000
53236 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field. */
53237 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_RESET 0xffff
53238 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI field value from a register. */
53239 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
53240 /* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field value suitable for setting the register. */
53241 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
53242 
53243 /*
53244  * Field : reserved_30_16
53245  *
53246  * Reserved
53247  *
53248  * Field Access Macros:
53249  *
53250  */
53251 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_RSVD_30_16 register field. */
53252 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_RSVD_30_16_LSB 16
53253 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_RSVD_30_16 register field. */
53254 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_RSVD_30_16_MSB 30
53255 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_RSVD_30_16 register field. */
53256 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_RSVD_30_16_WIDTH 15
53257 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_RSVD_30_16 register field value. */
53258 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
53259 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_RSVD_30_16 register field value. */
53260 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
53261 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_RSVD_30_16 register field. */
53262 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_RSVD_30_16_RESET 0x0
53263 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_RSVD_30_16 field value from a register. */
53264 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
53265 /* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_RSVD_30_16 register field value suitable for setting the register. */
53266 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
53267 
53268 /*
53269  * Field : ae
53270  *
53271  * Address Enable
53272  *
53273  * When this bit is set, the address filter module uses the 64th MAC address for
53274  * perfect filtering.
53275  *
53276  * When this bit is reset, the address filter module ignores the address for
53277  * filtering.
53278  *
53279  * Field Enumeration Values:
53280  *
53281  * Enum | Value | Description
53282  * :----------------------------------------|:------|:------------
53283  * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_E_DISD | 0x0 |
53284  * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_E_END | 0x1 |
53285  *
53286  * Field Access Macros:
53287  *
53288  */
53289 /*
53290  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE
53291  *
53292  */
53293 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_E_DISD 0x0
53294 /*
53295  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE
53296  *
53297  */
53298 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_E_END 0x1
53299 
53300 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field. */
53301 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_LSB 31
53302 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field. */
53303 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_MSB 31
53304 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field. */
53305 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_WIDTH 1
53306 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field value. */
53307 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_SET_MSK 0x80000000
53308 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field value. */
53309 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_CLR_MSK 0x7fffffff
53310 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field. */
53311 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_RESET 0x0
53312 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE field value from a register. */
53313 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
53314 /* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field value suitable for setting the register. */
53315 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
53316 
53317 #ifndef __ASSEMBLY__
53318 /*
53319  * WARNING: The C register and register group struct declarations are provided for
53320  * convenience and illustrative purposes. They should, however, be used with
53321  * caution as the C language standard provides no guarantees about the alignment or
53322  * atomicity of device memory accesses. The recommended practice for writing
53323  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
53324  * alt_write_word() functions.
53325  *
53326  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR63_HIGH.
53327  */
53328 struct ALT_EMAC_GMAC_MAC_ADDR63_HIGH_s
53329 {
53330  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI */
53331  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR63_HIGH_RSVD_30_16 */
53332  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE */
53333 };
53334 
53335 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR63_HIGH. */
53336 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR63_HIGH_s ALT_EMAC_GMAC_MAC_ADDR63_HIGH_t;
53337 #endif /* __ASSEMBLY__ */
53338 
53339 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH register. */
53340 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_RESET 0x0000ffff
53341 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH register from the beginning of the component. */
53342 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_OFST 0x978
53343 /* The address of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH register. */
53344 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR63_HIGH_OFST))
53345 
53346 /*
53347  * Register : gmacgrp_mac_address63_low
53348  *
53349  * <b> Register 607 (MAC Address63 Low Register) </b>
53350  *
53351  * The MAC Address63 Low register holds the lower 32 bits of the 64th 6-byte MAC
53352  * address of the station.
53353  *
53354  * Register Layout
53355  *
53356  * Bits | Access | Reset | Description
53357  * :-------|:-------|:-----------|:------------------------------------
53358  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO
53359  *
53360  */
53361 /*
53362  * Field : addrlo
53363  *
53364  * MAC Address63 [31:0]
53365  *
53366  * This field contains the lower 32 bits of the 64th 6-byte MAC address. The
53367  * content of this field is undefined until loaded by the Application after the
53368  * initialization process.
53369  *
53370  * Field Access Macros:
53371  *
53372  */
53373 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field. */
53374 #define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_LSB 0
53375 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field. */
53376 #define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_MSB 31
53377 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field. */
53378 #define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_WIDTH 32
53379 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field value. */
53380 #define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_SET_MSK 0xffffffff
53381 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field value. */
53382 #define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_CLR_MSK 0x00000000
53383 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field. */
53384 #define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_RESET 0xffffffff
53385 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO field value from a register. */
53386 #define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
53387 /* Produces a ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field value suitable for setting the register. */
53388 #define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
53389 
53390 #ifndef __ASSEMBLY__
53391 /*
53392  * WARNING: The C register and register group struct declarations are provided for
53393  * convenience and illustrative purposes. They should, however, be used with
53394  * caution as the C language standard provides no guarantees about the alignment or
53395  * atomicity of device memory accesses. The recommended practice for writing
53396  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
53397  * alt_write_word() functions.
53398  *
53399  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR63_LOW.
53400  */
53401 struct ALT_EMAC_GMAC_MAC_ADDR63_LOW_s
53402 {
53403  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO */
53404 };
53405 
53406 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR63_LOW. */
53407 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR63_LOW_s ALT_EMAC_GMAC_MAC_ADDR63_LOW_t;
53408 #endif /* __ASSEMBLY__ */
53409 
53410 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_LOW register. */
53411 #define ALT_EMAC_GMAC_MAC_ADDR63_LOW_RESET 0xffffffff
53412 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR63_LOW register from the beginning of the component. */
53413 #define ALT_EMAC_GMAC_MAC_ADDR63_LOW_OFST 0x97c
53414 /* The address of the ALT_EMAC_GMAC_MAC_ADDR63_LOW register. */
53415 #define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR63_LOW_OFST))
53416 
53417 /*
53418  * Register : gmacgrp_mac_address64_high
53419  *
53420  * <b> Register 608 (MAC Address64 High Register) </b>
53421  *
53422  * The MAC Address64 High register holds the upper 16 bits of the 65th 6-byte MAC
53423  * address of the station.
53424  *
53425  * If the MAC address registers are configured to be double-synchronized to the
53426  * (G)MII clock domains, then
53427  *
53428  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
53429  * or Bits[7:0] (in big-endian mode) of the MAC Address64 Low Register are written.
53430  * For proper synchronization updates, consecutive writes to this MAC Address64 Low
53431  * Register must be performed after at least four clock cycles in the destination
53432  * clock domain.
53433  *
53434  * Register Layout
53435  *
53436  * Bits | Access | Reset | Description
53437  * :--------|:-------|:-------|:-----------------------------------------
53438  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI
53439  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR64_HIGH_RSVD_30_16
53440  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE
53441  *
53442  */
53443 /*
53444  * Field : addrhi
53445  *
53446  * MAC Address64 [47:32]
53447  *
53448  * This field contains the upper 16 bits (47:32) of the 65th 6-byte MAC address.
53449  *
53450  * Field Access Macros:
53451  *
53452  */
53453 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field. */
53454 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_LSB 0
53455 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field. */
53456 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_MSB 15
53457 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field. */
53458 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_WIDTH 16
53459 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field value. */
53460 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_SET_MSK 0x0000ffff
53461 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field value. */
53462 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_CLR_MSK 0xffff0000
53463 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field. */
53464 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_RESET 0xffff
53465 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI field value from a register. */
53466 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
53467 /* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field value suitable for setting the register. */
53468 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
53469 
53470 /*
53471  * Field : reserved_30_16
53472  *
53473  * Reserved
53474  *
53475  * Field Access Macros:
53476  *
53477  */
53478 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_RSVD_30_16 register field. */
53479 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_RSVD_30_16_LSB 16
53480 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_RSVD_30_16 register field. */
53481 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_RSVD_30_16_MSB 30
53482 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_RSVD_30_16 register field. */
53483 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_RSVD_30_16_WIDTH 15
53484 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_RSVD_30_16 register field value. */
53485 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
53486 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_RSVD_30_16 register field value. */
53487 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
53488 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_RSVD_30_16 register field. */
53489 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_RSVD_30_16_RESET 0x0
53490 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_RSVD_30_16 field value from a register. */
53491 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
53492 /* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_RSVD_30_16 register field value suitable for setting the register. */
53493 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
53494 
53495 /*
53496  * Field : ae
53497  *
53498  * Address Enable
53499  *
53500  * When this bit is set, the address filter module uses the 65th MAC address for
53501  * perfect filtering.
53502  *
53503  * When this bit is reset, the address filter module ignores the address for
53504  * filtering.
53505  *
53506  * Field Enumeration Values:
53507  *
53508  * Enum | Value | Description
53509  * :----------------------------------------|:------|:------------
53510  * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_E_DISD | 0x0 |
53511  * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_E_END | 0x1 |
53512  *
53513  * Field Access Macros:
53514  *
53515  */
53516 /*
53517  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE
53518  *
53519  */
53520 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_E_DISD 0x0
53521 /*
53522  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE
53523  *
53524  */
53525 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_E_END 0x1
53526 
53527 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field. */
53528 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_LSB 31
53529 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field. */
53530 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_MSB 31
53531 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field. */
53532 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_WIDTH 1
53533 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field value. */
53534 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_SET_MSK 0x80000000
53535 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field value. */
53536 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_CLR_MSK 0x7fffffff
53537 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field. */
53538 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_RESET 0x0
53539 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE field value from a register. */
53540 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
53541 /* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field value suitable for setting the register. */
53542 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
53543 
53544 #ifndef __ASSEMBLY__
53545 /*
53546  * WARNING: The C register and register group struct declarations are provided for
53547  * convenience and illustrative purposes. They should, however, be used with
53548  * caution as the C language standard provides no guarantees about the alignment or
53549  * atomicity of device memory accesses. The recommended practice for writing
53550  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
53551  * alt_write_word() functions.
53552  *
53553  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR64_HIGH.
53554  */
53555 struct ALT_EMAC_GMAC_MAC_ADDR64_HIGH_s
53556 {
53557  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI */
53558  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR64_HIGH_RSVD_30_16 */
53559  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE */
53560 };
53561 
53562 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR64_HIGH. */
53563 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR64_HIGH_s ALT_EMAC_GMAC_MAC_ADDR64_HIGH_t;
53564 #endif /* __ASSEMBLY__ */
53565 
53566 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH register. */
53567 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_RESET 0x0000ffff
53568 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH register from the beginning of the component. */
53569 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_OFST 0x980
53570 /* The address of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH register. */
53571 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR64_HIGH_OFST))
53572 
53573 /*
53574  * Register : gmacgrp_mac_address64_low
53575  *
53576  * <b> Register 609 (MAC Address64 Low Register) </b>
53577  *
53578  * The MAC Address64 Low register holds the lower 32 bits of the 65th 6-byte MAC
53579  * address of the station.
53580  *
53581  * Register Layout
53582  *
53583  * Bits | Access | Reset | Description
53584  * :-------|:-------|:-----------|:------------------------------------
53585  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO
53586  *
53587  */
53588 /*
53589  * Field : addrlo
53590  *
53591  * MAC Address64 [31:0]
53592  *
53593  * This field contains the lower 32 bits of the 65th 6-byte MAC address. The
53594  * content of this field is undefined until loaded by the Application after the
53595  * initialization process.
53596  *
53597  * Field Access Macros:
53598  *
53599  */
53600 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field. */
53601 #define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_LSB 0
53602 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field. */
53603 #define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_MSB 31
53604 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field. */
53605 #define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_WIDTH 32
53606 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field value. */
53607 #define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_SET_MSK 0xffffffff
53608 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field value. */
53609 #define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_CLR_MSK 0x00000000
53610 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field. */
53611 #define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_RESET 0xffffffff
53612 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO field value from a register. */
53613 #define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
53614 /* Produces a ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field value suitable for setting the register. */
53615 #define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
53616 
53617 #ifndef __ASSEMBLY__
53618 /*
53619  * WARNING: The C register and register group struct declarations are provided for
53620  * convenience and illustrative purposes. They should, however, be used with
53621  * caution as the C language standard provides no guarantees about the alignment or
53622  * atomicity of device memory accesses. The recommended practice for writing
53623  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
53624  * alt_write_word() functions.
53625  *
53626  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR64_LOW.
53627  */
53628 struct ALT_EMAC_GMAC_MAC_ADDR64_LOW_s
53629 {
53630  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO */
53631 };
53632 
53633 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR64_LOW. */
53634 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR64_LOW_s ALT_EMAC_GMAC_MAC_ADDR64_LOW_t;
53635 #endif /* __ASSEMBLY__ */
53636 
53637 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_LOW register. */
53638 #define ALT_EMAC_GMAC_MAC_ADDR64_LOW_RESET 0xffffffff
53639 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR64_LOW register from the beginning of the component. */
53640 #define ALT_EMAC_GMAC_MAC_ADDR64_LOW_OFST 0x984
53641 /* The address of the ALT_EMAC_GMAC_MAC_ADDR64_LOW register. */
53642 #define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR64_LOW_OFST))
53643 
53644 /*
53645  * Register : gmacgrp_mac_address65_high
53646  *
53647  * <b> Register 610 (MAC Address65 High Register) </b>
53648  *
53649  * The MAC Address65 High register holds the upper 16 bits of the 66th 6-byte MAC
53650  * address of the station.
53651  *
53652  * If the MAC address registers are configured to be double-synchronized to the
53653  * (G)MII clock domains, then
53654  *
53655  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
53656  * or Bits[7:0] (in big-endian mode) of the MAC Address65 Low Register are written.
53657  * For proper synchronization updates, consecutive writes to this MAC Address65 Low
53658  * Register must be performed after at least four clock cycles in the destination
53659  * clock domain.
53660  *
53661  * Register Layout
53662  *
53663  * Bits | Access | Reset | Description
53664  * :--------|:-------|:-------|:-----------------------------------------
53665  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI
53666  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR65_HIGH_RSVD_30_16
53667  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE
53668  *
53669  */
53670 /*
53671  * Field : addrhi
53672  *
53673  * MAC Address65 [47:32]
53674  *
53675  * This field contains the upper 16 bits (47:32) of the 66th 6-byte MAC address.
53676  *
53677  * Field Access Macros:
53678  *
53679  */
53680 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field. */
53681 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_LSB 0
53682 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field. */
53683 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_MSB 15
53684 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field. */
53685 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_WIDTH 16
53686 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field value. */
53687 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_SET_MSK 0x0000ffff
53688 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field value. */
53689 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_CLR_MSK 0xffff0000
53690 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field. */
53691 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_RESET 0xffff
53692 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI field value from a register. */
53693 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
53694 /* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field value suitable for setting the register. */
53695 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
53696 
53697 /*
53698  * Field : reserved_30_16
53699  *
53700  * Reserved
53701  *
53702  * Field Access Macros:
53703  *
53704  */
53705 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_RSVD_30_16 register field. */
53706 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_RSVD_30_16_LSB 16
53707 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_RSVD_30_16 register field. */
53708 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_RSVD_30_16_MSB 30
53709 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_RSVD_30_16 register field. */
53710 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_RSVD_30_16_WIDTH 15
53711 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_RSVD_30_16 register field value. */
53712 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
53713 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_RSVD_30_16 register field value. */
53714 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
53715 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_RSVD_30_16 register field. */
53716 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_RSVD_30_16_RESET 0x0
53717 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_RSVD_30_16 field value from a register. */
53718 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
53719 /* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_RSVD_30_16 register field value suitable for setting the register. */
53720 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
53721 
53722 /*
53723  * Field : ae
53724  *
53725  * Address Enable
53726  *
53727  * When this bit is set, the address filter module uses the 66th MAC address for
53728  * perfect filtering.
53729  *
53730  * When this bit is reset, the address filter module ignores the address for
53731  * filtering.
53732  *
53733  * Field Enumeration Values:
53734  *
53735  * Enum | Value | Description
53736  * :----------------------------------------|:------|:------------
53737  * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_E_DISD | 0x0 |
53738  * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_E_END | 0x1 |
53739  *
53740  * Field Access Macros:
53741  *
53742  */
53743 /*
53744  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE
53745  *
53746  */
53747 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_E_DISD 0x0
53748 /*
53749  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE
53750  *
53751  */
53752 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_E_END 0x1
53753 
53754 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field. */
53755 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_LSB 31
53756 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field. */
53757 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_MSB 31
53758 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field. */
53759 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_WIDTH 1
53760 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field value. */
53761 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_SET_MSK 0x80000000
53762 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field value. */
53763 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_CLR_MSK 0x7fffffff
53764 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field. */
53765 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_RESET 0x0
53766 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE field value from a register. */
53767 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
53768 /* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field value suitable for setting the register. */
53769 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
53770 
53771 #ifndef __ASSEMBLY__
53772 /*
53773  * WARNING: The C register and register group struct declarations are provided for
53774  * convenience and illustrative purposes. They should, however, be used with
53775  * caution as the C language standard provides no guarantees about the alignment or
53776  * atomicity of device memory accesses. The recommended practice for writing
53777  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
53778  * alt_write_word() functions.
53779  *
53780  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR65_HIGH.
53781  */
53782 struct ALT_EMAC_GMAC_MAC_ADDR65_HIGH_s
53783 {
53784  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI */
53785  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR65_HIGH_RSVD_30_16 */
53786  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE */
53787 };
53788 
53789 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR65_HIGH. */
53790 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR65_HIGH_s ALT_EMAC_GMAC_MAC_ADDR65_HIGH_t;
53791 #endif /* __ASSEMBLY__ */
53792 
53793 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH register. */
53794 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_RESET 0x0000ffff
53795 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH register from the beginning of the component. */
53796 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_OFST 0x988
53797 /* The address of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH register. */
53798 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR65_HIGH_OFST))
53799 
53800 /*
53801  * Register : gmacgrp_mac_address65_low
53802  *
53803  * <b> Register 611 (MAC Address65 Low Register)</b>
53804  *
53805  * The MAC Address65 Low register holds the lower 32 bits of the 66th 6-byte MAC
53806  * address of the station.
53807  *
53808  * Register Layout
53809  *
53810  * Bits | Access | Reset | Description
53811  * :-------|:-------|:-----------|:------------------------------------
53812  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO
53813  *
53814  */
53815 /*
53816  * Field : addrlo
53817  *
53818  * MAC Address65 [31:0]
53819  *
53820  * This field contains the lower 32 bits of the 66th 6-byte MAC address. The
53821  * content of this field is undefined until loaded by the Application after the
53822  * initialization process.
53823  *
53824  * Field Access Macros:
53825  *
53826  */
53827 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field. */
53828 #define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_LSB 0
53829 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field. */
53830 #define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_MSB 31
53831 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field. */
53832 #define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_WIDTH 32
53833 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field value. */
53834 #define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_SET_MSK 0xffffffff
53835 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field value. */
53836 #define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_CLR_MSK 0x00000000
53837 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field. */
53838 #define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_RESET 0xffffffff
53839 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO field value from a register. */
53840 #define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
53841 /* Produces a ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field value suitable for setting the register. */
53842 #define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
53843 
53844 #ifndef __ASSEMBLY__
53845 /*
53846  * WARNING: The C register and register group struct declarations are provided for
53847  * convenience and illustrative purposes. They should, however, be used with
53848  * caution as the C language standard provides no guarantees about the alignment or
53849  * atomicity of device memory accesses. The recommended practice for writing
53850  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
53851  * alt_write_word() functions.
53852  *
53853  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR65_LOW.
53854  */
53855 struct ALT_EMAC_GMAC_MAC_ADDR65_LOW_s
53856 {
53857  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO */
53858 };
53859 
53860 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR65_LOW. */
53861 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR65_LOW_s ALT_EMAC_GMAC_MAC_ADDR65_LOW_t;
53862 #endif /* __ASSEMBLY__ */
53863 
53864 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_LOW register. */
53865 #define ALT_EMAC_GMAC_MAC_ADDR65_LOW_RESET 0xffffffff
53866 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR65_LOW register from the beginning of the component. */
53867 #define ALT_EMAC_GMAC_MAC_ADDR65_LOW_OFST 0x98c
53868 /* The address of the ALT_EMAC_GMAC_MAC_ADDR65_LOW register. */
53869 #define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR65_LOW_OFST))
53870 
53871 /*
53872  * Register : gmacgrp_mac_address66_high
53873  *
53874  * <b> Register 612 (MAC Address66 High Register)</b>
53875  *
53876  * The MAC Address66 High register holds the upper 16 bits of the 67th 6-byte MAC
53877  * address of the station.
53878  *
53879  * If the MAC address registers are configured to be double-synchronized to the
53880  * (G)MII clock domains, then
53881  *
53882  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
53883  * or Bits[7:0] (in big-endian mode) of the MAC Address66 Low Register are written.
53884  * For proper synchronization updates, consecutive writes to this MAC Address66 Low
53885  * Register must be performed after at least four clock cycles in the destination
53886  * clock domain.
53887  *
53888  * Register Layout
53889  *
53890  * Bits | Access | Reset | Description
53891  * :--------|:-------|:-------|:-----------------------------------------
53892  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI
53893  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR66_HIGH_RSVD_30_16
53894  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE
53895  *
53896  */
53897 /*
53898  * Field : addrhi
53899  *
53900  * MAC Address66 [47:32]
53901  *
53902  * This field contains the upper 16 bits (47:32) of the 67th 6-byte MAC address.
53903  *
53904  * Field Access Macros:
53905  *
53906  */
53907 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field. */
53908 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_LSB 0
53909 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field. */
53910 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_MSB 15
53911 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field. */
53912 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_WIDTH 16
53913 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field value. */
53914 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_SET_MSK 0x0000ffff
53915 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field value. */
53916 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_CLR_MSK 0xffff0000
53917 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field. */
53918 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_RESET 0xffff
53919 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI field value from a register. */
53920 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
53921 /* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field value suitable for setting the register. */
53922 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
53923 
53924 /*
53925  * Field : reserved_30_16
53926  *
53927  * Reserved
53928  *
53929  * Field Access Macros:
53930  *
53931  */
53932 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_RSVD_30_16 register field. */
53933 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_RSVD_30_16_LSB 16
53934 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_RSVD_30_16 register field. */
53935 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_RSVD_30_16_MSB 30
53936 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_RSVD_30_16 register field. */
53937 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_RSVD_30_16_WIDTH 15
53938 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_RSVD_30_16 register field value. */
53939 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
53940 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_RSVD_30_16 register field value. */
53941 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
53942 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_RSVD_30_16 register field. */
53943 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_RSVD_30_16_RESET 0x0
53944 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_RSVD_30_16 field value from a register. */
53945 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
53946 /* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_RSVD_30_16 register field value suitable for setting the register. */
53947 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
53948 
53949 /*
53950  * Field : ae
53951  *
53952  * Address Enable
53953  *
53954  * When this bit is set, the address filter module uses the 67th MAC address for
53955  * perfect filtering.
53956  *
53957  * When this bit is reset, the address filter module ignores the address for
53958  * filtering.
53959  *
53960  * Field Enumeration Values:
53961  *
53962  * Enum | Value | Description
53963  * :----------------------------------------|:------|:------------
53964  * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_E_DISD | 0x0 |
53965  * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_E_END | 0x1 |
53966  *
53967  * Field Access Macros:
53968  *
53969  */
53970 /*
53971  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE
53972  *
53973  */
53974 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_E_DISD 0x0
53975 /*
53976  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE
53977  *
53978  */
53979 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_E_END 0x1
53980 
53981 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field. */
53982 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_LSB 31
53983 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field. */
53984 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_MSB 31
53985 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field. */
53986 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_WIDTH 1
53987 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field value. */
53988 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_SET_MSK 0x80000000
53989 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field value. */
53990 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_CLR_MSK 0x7fffffff
53991 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field. */
53992 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_RESET 0x0
53993 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE field value from a register. */
53994 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
53995 /* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field value suitable for setting the register. */
53996 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
53997 
53998 #ifndef __ASSEMBLY__
53999 /*
54000  * WARNING: The C register and register group struct declarations are provided for
54001  * convenience and illustrative purposes. They should, however, be used with
54002  * caution as the C language standard provides no guarantees about the alignment or
54003  * atomicity of device memory accesses. The recommended practice for writing
54004  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
54005  * alt_write_word() functions.
54006  *
54007  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR66_HIGH.
54008  */
54009 struct ALT_EMAC_GMAC_MAC_ADDR66_HIGH_s
54010 {
54011  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI */
54012  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR66_HIGH_RSVD_30_16 */
54013  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE */
54014 };
54015 
54016 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR66_HIGH. */
54017 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR66_HIGH_s ALT_EMAC_GMAC_MAC_ADDR66_HIGH_t;
54018 #endif /* __ASSEMBLY__ */
54019 
54020 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH register. */
54021 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_RESET 0x0000ffff
54022 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH register from the beginning of the component. */
54023 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_OFST 0x990
54024 /* The address of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH register. */
54025 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR66_HIGH_OFST))
54026 
54027 /*
54028  * Register : gmacgrp_mac_address66_low
54029  *
54030  * <b> Register 613 (MAC Address66 Low Register)</b>
54031  *
54032  * The MAC Address66 Low register holds the lower 32 bits of the 67th 6-byte MAC
54033  * address of the station.
54034  *
54035  * Register Layout
54036  *
54037  * Bits | Access | Reset | Description
54038  * :-------|:-------|:-----------|:------------------------------------
54039  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO
54040  *
54041  */
54042 /*
54043  * Field : addrlo
54044  *
54045  * MAC Address66 [31:0]
54046  *
54047  * This field contains the lower 32 bits of the 67th 6-byte MAC address. The
54048  * content of this field is undefined until loaded by the Application after the
54049  * initialization process.
54050  *
54051  * Field Access Macros:
54052  *
54053  */
54054 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field. */
54055 #define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_LSB 0
54056 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field. */
54057 #define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_MSB 31
54058 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field. */
54059 #define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_WIDTH 32
54060 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field value. */
54061 #define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_SET_MSK 0xffffffff
54062 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field value. */
54063 #define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_CLR_MSK 0x00000000
54064 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field. */
54065 #define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_RESET 0xffffffff
54066 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO field value from a register. */
54067 #define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
54068 /* Produces a ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field value suitable for setting the register. */
54069 #define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
54070 
54071 #ifndef __ASSEMBLY__
54072 /*
54073  * WARNING: The C register and register group struct declarations are provided for
54074  * convenience and illustrative purposes. They should, however, be used with
54075  * caution as the C language standard provides no guarantees about the alignment or
54076  * atomicity of device memory accesses. The recommended practice for writing
54077  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
54078  * alt_write_word() functions.
54079  *
54080  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR66_LOW.
54081  */
54082 struct ALT_EMAC_GMAC_MAC_ADDR66_LOW_s
54083 {
54084  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO */
54085 };
54086 
54087 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR66_LOW. */
54088 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR66_LOW_s ALT_EMAC_GMAC_MAC_ADDR66_LOW_t;
54089 #endif /* __ASSEMBLY__ */
54090 
54091 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_LOW register. */
54092 #define ALT_EMAC_GMAC_MAC_ADDR66_LOW_RESET 0xffffffff
54093 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR66_LOW register from the beginning of the component. */
54094 #define ALT_EMAC_GMAC_MAC_ADDR66_LOW_OFST 0x994
54095 /* The address of the ALT_EMAC_GMAC_MAC_ADDR66_LOW register. */
54096 #define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR66_LOW_OFST))
54097 
54098 /*
54099  * Register : gmacgrp_mac_address67_high
54100  *
54101  * <b> Register 614 (MAC Address67 High Register)</b>
54102  *
54103  * The MAC Address67 High register holds the upper 16 bits of the 68th 6-byte MAC
54104  * address of the station.
54105  *
54106  * If the MAC address registers are configured to be double-synchronized to the
54107  * (G)MII clock domains, then
54108  *
54109  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
54110  * or Bits[7:0] (in big-endian mode) of the MAC Address67 Low Register are written.
54111  * For proper synchronization updates, consecutive writes to this MAC Address67 Low
54112  * Register must be performed after at least four clock cycles in the destination
54113  * clock domain.
54114  *
54115  * Register Layout
54116  *
54117  * Bits | Access | Reset | Description
54118  * :--------|:-------|:-------|:-----------------------------------------
54119  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI
54120  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR67_HIGH_RSVD_30_16
54121  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE
54122  *
54123  */
54124 /*
54125  * Field : addrhi
54126  *
54127  * MAC Address67 [47:32]
54128  *
54129  * This field contains the upper 16 bits (47:32) of the 68th 6-byte MAC address.
54130  *
54131  * Field Access Macros:
54132  *
54133  */
54134 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field. */
54135 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_LSB 0
54136 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field. */
54137 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_MSB 15
54138 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field. */
54139 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_WIDTH 16
54140 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field value. */
54141 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_SET_MSK 0x0000ffff
54142 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field value. */
54143 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_CLR_MSK 0xffff0000
54144 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field. */
54145 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_RESET 0xffff
54146 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI field value from a register. */
54147 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
54148 /* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field value suitable for setting the register. */
54149 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
54150 
54151 /*
54152  * Field : reserved_30_16
54153  *
54154  * Reserved
54155  *
54156  * Field Access Macros:
54157  *
54158  */
54159 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_RSVD_30_16 register field. */
54160 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_RSVD_30_16_LSB 16
54161 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_RSVD_30_16 register field. */
54162 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_RSVD_30_16_MSB 30
54163 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_RSVD_30_16 register field. */
54164 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_RSVD_30_16_WIDTH 15
54165 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_RSVD_30_16 register field value. */
54166 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
54167 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_RSVD_30_16 register field value. */
54168 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
54169 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_RSVD_30_16 register field. */
54170 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_RSVD_30_16_RESET 0x0
54171 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_RSVD_30_16 field value from a register. */
54172 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
54173 /* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_RSVD_30_16 register field value suitable for setting the register. */
54174 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
54175 
54176 /*
54177  * Field : ae
54178  *
54179  * Address Enable
54180  *
54181  * When this bit is set, the address filter module uses the 68th MAC address for
54182  * perfect filtering.
54183  *
54184  * When this bit is reset, the address filter module ignores the address for
54185  * filtering.
54186  *
54187  * Field Enumeration Values:
54188  *
54189  * Enum | Value | Description
54190  * :----------------------------------------|:------|:------------
54191  * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_E_DISD | 0x0 |
54192  * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_E_END | 0x1 |
54193  *
54194  * Field Access Macros:
54195  *
54196  */
54197 /*
54198  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE
54199  *
54200  */
54201 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_E_DISD 0x0
54202 /*
54203  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE
54204  *
54205  */
54206 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_E_END 0x1
54207 
54208 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field. */
54209 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_LSB 31
54210 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field. */
54211 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_MSB 31
54212 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field. */
54213 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_WIDTH 1
54214 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field value. */
54215 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_SET_MSK 0x80000000
54216 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field value. */
54217 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_CLR_MSK 0x7fffffff
54218 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field. */
54219 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_RESET 0x0
54220 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE field value from a register. */
54221 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
54222 /* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field value suitable for setting the register. */
54223 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
54224 
54225 #ifndef __ASSEMBLY__
54226 /*
54227  * WARNING: The C register and register group struct declarations are provided for
54228  * convenience and illustrative purposes. They should, however, be used with
54229  * caution as the C language standard provides no guarantees about the alignment or
54230  * atomicity of device memory accesses. The recommended practice for writing
54231  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
54232  * alt_write_word() functions.
54233  *
54234  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR67_HIGH.
54235  */
54236 struct ALT_EMAC_GMAC_MAC_ADDR67_HIGH_s
54237 {
54238  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI */
54239  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR67_HIGH_RSVD_30_16 */
54240  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE */
54241 };
54242 
54243 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR67_HIGH. */
54244 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR67_HIGH_s ALT_EMAC_GMAC_MAC_ADDR67_HIGH_t;
54245 #endif /* __ASSEMBLY__ */
54246 
54247 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH register. */
54248 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_RESET 0x0000ffff
54249 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH register from the beginning of the component. */
54250 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_OFST 0x998
54251 /* The address of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH register. */
54252 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR67_HIGH_OFST))
54253 
54254 /*
54255  * Register : gmacgrp_mac_address67_low
54256  *
54257  * <b> Register 615 (MAC Address67 Low Register)</b>
54258  *
54259  * The MAC Address67 Low register holds the lower 32 bits of the 68th 6-byte MAC
54260  * address of the station.
54261  *
54262  * Register Layout
54263  *
54264  * Bits | Access | Reset | Description
54265  * :-------|:-------|:-----------|:------------------------------------
54266  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO
54267  *
54268  */
54269 /*
54270  * Field : addrlo
54271  *
54272  * MAC Address67 [31:0]
54273  *
54274  * This field contains the lower 32 bits of the 68th 6-byte MAC address. The
54275  * content of this field is undefined until loaded by the Application after the
54276  * initialization process.
54277  *
54278  * Field Access Macros:
54279  *
54280  */
54281 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field. */
54282 #define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_LSB 0
54283 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field. */
54284 #define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_MSB 31
54285 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field. */
54286 #define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_WIDTH 32
54287 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field value. */
54288 #define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_SET_MSK 0xffffffff
54289 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field value. */
54290 #define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_CLR_MSK 0x00000000
54291 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field. */
54292 #define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_RESET 0xffffffff
54293 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO field value from a register. */
54294 #define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
54295 /* Produces a ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field value suitable for setting the register. */
54296 #define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
54297 
54298 #ifndef __ASSEMBLY__
54299 /*
54300  * WARNING: The C register and register group struct declarations are provided for
54301  * convenience and illustrative purposes. They should, however, be used with
54302  * caution as the C language standard provides no guarantees about the alignment or
54303  * atomicity of device memory accesses. The recommended practice for writing
54304  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
54305  * alt_write_word() functions.
54306  *
54307  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR67_LOW.
54308  */
54309 struct ALT_EMAC_GMAC_MAC_ADDR67_LOW_s
54310 {
54311  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO */
54312 };
54313 
54314 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR67_LOW. */
54315 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR67_LOW_s ALT_EMAC_GMAC_MAC_ADDR67_LOW_t;
54316 #endif /* __ASSEMBLY__ */
54317 
54318 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_LOW register. */
54319 #define ALT_EMAC_GMAC_MAC_ADDR67_LOW_RESET 0xffffffff
54320 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR67_LOW register from the beginning of the component. */
54321 #define ALT_EMAC_GMAC_MAC_ADDR67_LOW_OFST 0x99c
54322 /* The address of the ALT_EMAC_GMAC_MAC_ADDR67_LOW register. */
54323 #define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR67_LOW_OFST))
54324 
54325 /*
54326  * Register : gmacgrp_mac_address68_high
54327  *
54328  * <b> Register 616 (MAC Address68 High Register)</b>
54329  *
54330  * The MAC Address68 High register holds the upper 16 bits of the 69th 6-byte MAC
54331  * address of the station.
54332  *
54333  * If the MAC address registers are configured to be double-synchronized to the
54334  * (G)MII clock domains, then
54335  *
54336  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
54337  * or Bits[7:0] (in big-endian mode) of the MAC Address68 Low Register are written.
54338  * For proper synchronization updates, consecutive writes to this MAC Address68 Low
54339  * Register must be performed after at least four clock cycles in the destination
54340  * clock domain.
54341  *
54342  * Register Layout
54343  *
54344  * Bits | Access | Reset | Description
54345  * :--------|:-------|:-------|:-----------------------------------------
54346  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI
54347  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR68_HIGH_RSVD_30_16
54348  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE
54349  *
54350  */
54351 /*
54352  * Field : addrhi
54353  *
54354  * MAC Address68 [47:32]
54355  *
54356  * This field contains the upper 16 bits (47:32) of the 69th 6-byte MAC address.
54357  *
54358  * Field Access Macros:
54359  *
54360  */
54361 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field. */
54362 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_LSB 0
54363 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field. */
54364 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_MSB 15
54365 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field. */
54366 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_WIDTH 16
54367 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field value. */
54368 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_SET_MSK 0x0000ffff
54369 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field value. */
54370 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_CLR_MSK 0xffff0000
54371 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field. */
54372 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_RESET 0xffff
54373 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI field value from a register. */
54374 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
54375 /* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field value suitable for setting the register. */
54376 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
54377 
54378 /*
54379  * Field : reserved_30_16
54380  *
54381  * Reserved
54382  *
54383  * Field Access Macros:
54384  *
54385  */
54386 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_RSVD_30_16 register field. */
54387 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_RSVD_30_16_LSB 16
54388 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_RSVD_30_16 register field. */
54389 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_RSVD_30_16_MSB 30
54390 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_RSVD_30_16 register field. */
54391 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_RSVD_30_16_WIDTH 15
54392 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_RSVD_30_16 register field value. */
54393 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
54394 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_RSVD_30_16 register field value. */
54395 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
54396 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_RSVD_30_16 register field. */
54397 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_RSVD_30_16_RESET 0x0
54398 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_RSVD_30_16 field value from a register. */
54399 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
54400 /* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_RSVD_30_16 register field value suitable for setting the register. */
54401 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
54402 
54403 /*
54404  * Field : ae
54405  *
54406  * Address Enable
54407  *
54408  * When this bit is set, the address filter module uses the 69th MAC address for
54409  * perfect filtering.
54410  *
54411  * When this bit is reset, the address filter module ignores the address for
54412  * filtering.
54413  *
54414  * Field Enumeration Values:
54415  *
54416  * Enum | Value | Description
54417  * :----------------------------------------|:------|:------------
54418  * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_E_DISD | 0x0 |
54419  * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_E_END | 0x1 |
54420  *
54421  * Field Access Macros:
54422  *
54423  */
54424 /*
54425  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE
54426  *
54427  */
54428 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_E_DISD 0x0
54429 /*
54430  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE
54431  *
54432  */
54433 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_E_END 0x1
54434 
54435 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field. */
54436 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_LSB 31
54437 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field. */
54438 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_MSB 31
54439 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field. */
54440 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_WIDTH 1
54441 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field value. */
54442 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_SET_MSK 0x80000000
54443 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field value. */
54444 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_CLR_MSK 0x7fffffff
54445 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field. */
54446 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_RESET 0x0
54447 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE field value from a register. */
54448 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
54449 /* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field value suitable for setting the register. */
54450 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
54451 
54452 #ifndef __ASSEMBLY__
54453 /*
54454  * WARNING: The C register and register group struct declarations are provided for
54455  * convenience and illustrative purposes. They should, however, be used with
54456  * caution as the C language standard provides no guarantees about the alignment or
54457  * atomicity of device memory accesses. The recommended practice for writing
54458  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
54459  * alt_write_word() functions.
54460  *
54461  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR68_HIGH.
54462  */
54463 struct ALT_EMAC_GMAC_MAC_ADDR68_HIGH_s
54464 {
54465  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI */
54466  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR68_HIGH_RSVD_30_16 */
54467  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE */
54468 };
54469 
54470 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR68_HIGH. */
54471 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR68_HIGH_s ALT_EMAC_GMAC_MAC_ADDR68_HIGH_t;
54472 #endif /* __ASSEMBLY__ */
54473 
54474 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH register. */
54475 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_RESET 0x0000ffff
54476 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH register from the beginning of the component. */
54477 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_OFST 0x9a0
54478 /* The address of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH register. */
54479 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR68_HIGH_OFST))
54480 
54481 /*
54482  * Register : gmacgrp_mac_address68_low
54483  *
54484  * <b> Register 617 (MAC Address68 Low Register)</b>
54485  *
54486  * The MAC Address68 Low register holds the lower 32 bits of the 69th 6-byte MAC
54487  * address of the station.
54488  *
54489  * Register Layout
54490  *
54491  * Bits | Access | Reset | Description
54492  * :-------|:-------|:-----------|:------------------------------------
54493  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO
54494  *
54495  */
54496 /*
54497  * Field : addrlo
54498  *
54499  * MAC Address68 [31:0]
54500  *
54501  * This field contains the lower 32 bits of the 69th 6-byte MAC address. The
54502  * content of this field is undefined until loaded by the Application after the
54503  * initialization process.
54504  *
54505  * Field Access Macros:
54506  *
54507  */
54508 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field. */
54509 #define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_LSB 0
54510 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field. */
54511 #define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_MSB 31
54512 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field. */
54513 #define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_WIDTH 32
54514 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field value. */
54515 #define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_SET_MSK 0xffffffff
54516 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field value. */
54517 #define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_CLR_MSK 0x00000000
54518 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field. */
54519 #define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_RESET 0xffffffff
54520 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO field value from a register. */
54521 #define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
54522 /* Produces a ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field value suitable for setting the register. */
54523 #define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
54524 
54525 #ifndef __ASSEMBLY__
54526 /*
54527  * WARNING: The C register and register group struct declarations are provided for
54528  * convenience and illustrative purposes. They should, however, be used with
54529  * caution as the C language standard provides no guarantees about the alignment or
54530  * atomicity of device memory accesses. The recommended practice for writing
54531  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
54532  * alt_write_word() functions.
54533  *
54534  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR68_LOW.
54535  */
54536 struct ALT_EMAC_GMAC_MAC_ADDR68_LOW_s
54537 {
54538  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO */
54539 };
54540 
54541 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR68_LOW. */
54542 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR68_LOW_s ALT_EMAC_GMAC_MAC_ADDR68_LOW_t;
54543 #endif /* __ASSEMBLY__ */
54544 
54545 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_LOW register. */
54546 #define ALT_EMAC_GMAC_MAC_ADDR68_LOW_RESET 0xffffffff
54547 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR68_LOW register from the beginning of the component. */
54548 #define ALT_EMAC_GMAC_MAC_ADDR68_LOW_OFST 0x9a4
54549 /* The address of the ALT_EMAC_GMAC_MAC_ADDR68_LOW register. */
54550 #define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR68_LOW_OFST))
54551 
54552 /*
54553  * Register : gmacgrp_mac_address69_high
54554  *
54555  * <b> Register 618 (MAC Address69 High Register) </b>
54556  *
54557  * The MAC Address69 High register holds the upper 16 bits of the 70th 6-byte MAC
54558  * address of the station.
54559  *
54560  * If the MAC address registers are configured to be double-synchronized to the
54561  * (G)MII clock domains, then
54562  *
54563  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
54564  * or Bits[7:0] (in big-endian mode) of the MAC Address69 Low Register are written.
54565  * For proper synchronization updates, consecutive writes to this MAC Address70 Low
54566  * Register must be performed after at least four clock cycles in the destination
54567  * clock domain.
54568  *
54569  * Register Layout
54570  *
54571  * Bits | Access | Reset | Description
54572  * :--------|:-------|:-------|:-----------------------------------------
54573  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI
54574  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR69_HIGH_RSVD_30_16
54575  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE
54576  *
54577  */
54578 /*
54579  * Field : addrhi
54580  *
54581  * MAC Address69 [47:32]
54582  *
54583  * This field contains the upper 16 bits (47:32) of the 70th 6-byte MAC address.
54584  *
54585  * Field Access Macros:
54586  *
54587  */
54588 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field. */
54589 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_LSB 0
54590 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field. */
54591 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_MSB 15
54592 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field. */
54593 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_WIDTH 16
54594 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field value. */
54595 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_SET_MSK 0x0000ffff
54596 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field value. */
54597 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_CLR_MSK 0xffff0000
54598 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field. */
54599 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_RESET 0xffff
54600 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI field value from a register. */
54601 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
54602 /* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field value suitable for setting the register. */
54603 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
54604 
54605 /*
54606  * Field : reserved_30_16
54607  *
54608  * Reserved
54609  *
54610  * Field Access Macros:
54611  *
54612  */
54613 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_RSVD_30_16 register field. */
54614 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_RSVD_30_16_LSB 16
54615 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_RSVD_30_16 register field. */
54616 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_RSVD_30_16_MSB 30
54617 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_RSVD_30_16 register field. */
54618 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_RSVD_30_16_WIDTH 15
54619 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_RSVD_30_16 register field value. */
54620 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
54621 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_RSVD_30_16 register field value. */
54622 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
54623 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_RSVD_30_16 register field. */
54624 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_RSVD_30_16_RESET 0x0
54625 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_RSVD_30_16 field value from a register. */
54626 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
54627 /* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_RSVD_30_16 register field value suitable for setting the register. */
54628 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
54629 
54630 /*
54631  * Field : ae
54632  *
54633  * Address Enable
54634  *
54635  * When this bit is set, the address filter module uses the 70th MAC address for
54636  * perfect filtering.
54637  *
54638  * When this bit is reset, the address filter module ignores the address for
54639  * filtering.
54640  *
54641  * Field Enumeration Values:
54642  *
54643  * Enum | Value | Description
54644  * :----------------------------------------|:------|:------------
54645  * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_E_DISD | 0x0 |
54646  * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_E_END | 0x1 |
54647  *
54648  * Field Access Macros:
54649  *
54650  */
54651 /*
54652  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE
54653  *
54654  */
54655 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_E_DISD 0x0
54656 /*
54657  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE
54658  *
54659  */
54660 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_E_END 0x1
54661 
54662 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field. */
54663 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_LSB 31
54664 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field. */
54665 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_MSB 31
54666 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field. */
54667 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_WIDTH 1
54668 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field value. */
54669 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_SET_MSK 0x80000000
54670 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field value. */
54671 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_CLR_MSK 0x7fffffff
54672 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field. */
54673 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_RESET 0x0
54674 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE field value from a register. */
54675 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
54676 /* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field value suitable for setting the register. */
54677 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
54678 
54679 #ifndef __ASSEMBLY__
54680 /*
54681  * WARNING: The C register and register group struct declarations are provided for
54682  * convenience and illustrative purposes. They should, however, be used with
54683  * caution as the C language standard provides no guarantees about the alignment or
54684  * atomicity of device memory accesses. The recommended practice for writing
54685  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
54686  * alt_write_word() functions.
54687  *
54688  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR69_HIGH.
54689  */
54690 struct ALT_EMAC_GMAC_MAC_ADDR69_HIGH_s
54691 {
54692  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI */
54693  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR69_HIGH_RSVD_30_16 */
54694  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE */
54695 };
54696 
54697 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR69_HIGH. */
54698 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR69_HIGH_s ALT_EMAC_GMAC_MAC_ADDR69_HIGH_t;
54699 #endif /* __ASSEMBLY__ */
54700 
54701 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH register. */
54702 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_RESET 0x0000ffff
54703 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH register from the beginning of the component. */
54704 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_OFST 0x9a8
54705 /* The address of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH register. */
54706 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR69_HIGH_OFST))
54707 
54708 /*
54709  * Register : gmacgrp_mac_address69_low
54710  *
54711  * <b> Register 619 (MAC Address69 Low Register) </b>
54712  *
54713  * The MAC Address69 Low register holds the lower 32 bits of the 70th 6-byte MAC
54714  * address of the station.
54715  *
54716  * Register Layout
54717  *
54718  * Bits | Access | Reset | Description
54719  * :-------|:-------|:-----------|:------------------------------------
54720  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO
54721  *
54722  */
54723 /*
54724  * Field : addrlo
54725  *
54726  * MAC Address69 [31:0]
54727  *
54728  * This field contains the lower 32 bits of the 70th 6-byte MAC address. The
54729  * content of this field is undefined until loaded by the Application after the
54730  * initialization process.
54731  *
54732  * Field Access Macros:
54733  *
54734  */
54735 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field. */
54736 #define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_LSB 0
54737 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field. */
54738 #define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_MSB 31
54739 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field. */
54740 #define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_WIDTH 32
54741 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field value. */
54742 #define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_SET_MSK 0xffffffff
54743 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field value. */
54744 #define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_CLR_MSK 0x00000000
54745 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field. */
54746 #define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_RESET 0xffffffff
54747 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO field value from a register. */
54748 #define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
54749 /* Produces a ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field value suitable for setting the register. */
54750 #define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
54751 
54752 #ifndef __ASSEMBLY__
54753 /*
54754  * WARNING: The C register and register group struct declarations are provided for
54755  * convenience and illustrative purposes. They should, however, be used with
54756  * caution as the C language standard provides no guarantees about the alignment or
54757  * atomicity of device memory accesses. The recommended practice for writing
54758  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
54759  * alt_write_word() functions.
54760  *
54761  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR69_LOW.
54762  */
54763 struct ALT_EMAC_GMAC_MAC_ADDR69_LOW_s
54764 {
54765  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO */
54766 };
54767 
54768 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR69_LOW. */
54769 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR69_LOW_s ALT_EMAC_GMAC_MAC_ADDR69_LOW_t;
54770 #endif /* __ASSEMBLY__ */
54771 
54772 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_LOW register. */
54773 #define ALT_EMAC_GMAC_MAC_ADDR69_LOW_RESET 0xffffffff
54774 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR69_LOW register from the beginning of the component. */
54775 #define ALT_EMAC_GMAC_MAC_ADDR69_LOW_OFST 0x9ac
54776 /* The address of the ALT_EMAC_GMAC_MAC_ADDR69_LOW register. */
54777 #define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR69_LOW_OFST))
54778 
54779 /*
54780  * Register : gmacgrp_mac_address70_high
54781  *
54782  * <b> Register 620 (MAC Address70 High Register) </b>
54783  *
54784  * The MAC Address70 High register holds the upper 16 bits of the 71st 6-byte MAC
54785  * address of the station.
54786  *
54787  * If the MAC address registers are configured to be double-synchronized to the
54788  * (G)MII clock domains, then
54789  *
54790  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
54791  * or Bits[7:0] (in big-endian mode) of the MAC Address70 Low Register are written.
54792  * For proper synchronization updates, consecutive writes to this MAC Address70 Low
54793  * Register must be performed after at least four clock cycles in the destination
54794  * clock domain.
54795  *
54796  * Register Layout
54797  *
54798  * Bits | Access | Reset | Description
54799  * :--------|:-------|:-------|:-----------------------------------------
54800  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI
54801  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR70_HIGH_RSVD_30_16
54802  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE
54803  *
54804  */
54805 /*
54806  * Field : addrhi
54807  *
54808  * MAC Address70 [47:32]
54809  *
54810  * This field contains the upper 16 bits (47:32) of the 71st 6-byte MAC address.
54811  *
54812  * Field Access Macros:
54813  *
54814  */
54815 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field. */
54816 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_LSB 0
54817 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field. */
54818 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_MSB 15
54819 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field. */
54820 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_WIDTH 16
54821 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field value. */
54822 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_SET_MSK 0x0000ffff
54823 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field value. */
54824 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_CLR_MSK 0xffff0000
54825 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field. */
54826 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_RESET 0xffff
54827 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI field value from a register. */
54828 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
54829 /* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field value suitable for setting the register. */
54830 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
54831 
54832 /*
54833  * Field : reserved_30_16
54834  *
54835  * Reserved
54836  *
54837  * Field Access Macros:
54838  *
54839  */
54840 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_RSVD_30_16 register field. */
54841 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_RSVD_30_16_LSB 16
54842 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_RSVD_30_16 register field. */
54843 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_RSVD_30_16_MSB 30
54844 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_RSVD_30_16 register field. */
54845 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_RSVD_30_16_WIDTH 15
54846 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_RSVD_30_16 register field value. */
54847 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
54848 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_RSVD_30_16 register field value. */
54849 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
54850 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_RSVD_30_16 register field. */
54851 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_RSVD_30_16_RESET 0x0
54852 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_RSVD_30_16 field value from a register. */
54853 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
54854 /* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_RSVD_30_16 register field value suitable for setting the register. */
54855 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
54856 
54857 /*
54858  * Field : ae
54859  *
54860  * Address Enable
54861  *
54862  * When this bit is set, the address filter module uses the 71st MAC address for
54863  * perfect filtering.
54864  *
54865  * When this bit is reset, the address filter module ignores the address for
54866  * filtering.
54867  *
54868  * Field Enumeration Values:
54869  *
54870  * Enum | Value | Description
54871  * :----------------------------------------|:------|:------------
54872  * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_E_DISD | 0x0 |
54873  * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_E_END | 0x1 |
54874  *
54875  * Field Access Macros:
54876  *
54877  */
54878 /*
54879  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE
54880  *
54881  */
54882 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_E_DISD 0x0
54883 /*
54884  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE
54885  *
54886  */
54887 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_E_END 0x1
54888 
54889 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field. */
54890 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_LSB 31
54891 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field. */
54892 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_MSB 31
54893 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field. */
54894 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_WIDTH 1
54895 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field value. */
54896 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_SET_MSK 0x80000000
54897 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field value. */
54898 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_CLR_MSK 0x7fffffff
54899 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field. */
54900 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_RESET 0x0
54901 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE field value from a register. */
54902 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
54903 /* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field value suitable for setting the register. */
54904 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
54905 
54906 #ifndef __ASSEMBLY__
54907 /*
54908  * WARNING: The C register and register group struct declarations are provided for
54909  * convenience and illustrative purposes. They should, however, be used with
54910  * caution as the C language standard provides no guarantees about the alignment or
54911  * atomicity of device memory accesses. The recommended practice for writing
54912  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
54913  * alt_write_word() functions.
54914  *
54915  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR70_HIGH.
54916  */
54917 struct ALT_EMAC_GMAC_MAC_ADDR70_HIGH_s
54918 {
54919  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI */
54920  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR70_HIGH_RSVD_30_16 */
54921  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE */
54922 };
54923 
54924 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR70_HIGH. */
54925 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR70_HIGH_s ALT_EMAC_GMAC_MAC_ADDR70_HIGH_t;
54926 #endif /* __ASSEMBLY__ */
54927 
54928 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH register. */
54929 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_RESET 0x0000ffff
54930 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH register from the beginning of the component. */
54931 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_OFST 0x9b0
54932 /* The address of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH register. */
54933 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR70_HIGH_OFST))
54934 
54935 /*
54936  * Register : gmacgrp_mac_address70_low
54937  *
54938  * <b> Register 621 (MAC Address70 Low Register) </b>
54939  *
54940  * The MAC Address70 Low register holds the lower 32 bits of the 71st 6-byte MAC
54941  * address of the station.
54942  *
54943  * Register Layout
54944  *
54945  * Bits | Access | Reset | Description
54946  * :-------|:-------|:-----------|:------------------------------------
54947  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO
54948  *
54949  */
54950 /*
54951  * Field : addrlo
54952  *
54953  * MAC Address70 [31:0]
54954  *
54955  * This field contains the lower 32 bits of the 71st 6-byte MAC address. The
54956  * content of this field is undefined until loaded by the Application after the
54957  * initialization process.
54958  *
54959  * Field Access Macros:
54960  *
54961  */
54962 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field. */
54963 #define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_LSB 0
54964 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field. */
54965 #define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_MSB 31
54966 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field. */
54967 #define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_WIDTH 32
54968 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field value. */
54969 #define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_SET_MSK 0xffffffff
54970 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field value. */
54971 #define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_CLR_MSK 0x00000000
54972 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field. */
54973 #define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_RESET 0xffffffff
54974 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO field value from a register. */
54975 #define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
54976 /* Produces a ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field value suitable for setting the register. */
54977 #define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
54978 
54979 #ifndef __ASSEMBLY__
54980 /*
54981  * WARNING: The C register and register group struct declarations are provided for
54982  * convenience and illustrative purposes. They should, however, be used with
54983  * caution as the C language standard provides no guarantees about the alignment or
54984  * atomicity of device memory accesses. The recommended practice for writing
54985  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
54986  * alt_write_word() functions.
54987  *
54988  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR70_LOW.
54989  */
54990 struct ALT_EMAC_GMAC_MAC_ADDR70_LOW_s
54991 {
54992  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO */
54993 };
54994 
54995 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR70_LOW. */
54996 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR70_LOW_s ALT_EMAC_GMAC_MAC_ADDR70_LOW_t;
54997 #endif /* __ASSEMBLY__ */
54998 
54999 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_LOW register. */
55000 #define ALT_EMAC_GMAC_MAC_ADDR70_LOW_RESET 0xffffffff
55001 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR70_LOW register from the beginning of the component. */
55002 #define ALT_EMAC_GMAC_MAC_ADDR70_LOW_OFST 0x9b4
55003 /* The address of the ALT_EMAC_GMAC_MAC_ADDR70_LOW register. */
55004 #define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR70_LOW_OFST))
55005 
55006 /*
55007  * Register : gmacgrp_mac_address71_high
55008  *
55009  * <b> Register 622 (MAC Address71 High Register) </b>
55010  *
55011  * The MAC Address71 High register holds the upper 16 bits of the 72nd 6-byte MAC
55012  * address of the station.
55013  *
55014  * If the MAC address registers are configured to be double-synchronized to the
55015  * (G)MII clock domains, then
55016  *
55017  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
55018  * or Bits[7:0] (in big-endian mode) of the MAC Address71 Low Register are written.
55019  * For proper synchronization updates, consecutive writes to this MAC Address71 Low
55020  * Register must be performed after at least four clock cycles in the destination
55021  * clock domain.
55022  *
55023  * Register Layout
55024  *
55025  * Bits | Access | Reset | Description
55026  * :--------|:-------|:-------|:-----------------------------------------
55027  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI
55028  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR71_HIGH_RSVD_30_16
55029  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE
55030  *
55031  */
55032 /*
55033  * Field : addrhi
55034  *
55035  * MAC Address71 [47:32]
55036  *
55037  * This field contains the upper 16 bits (47:32) of the 72nd 6-byte MAC address.
55038  *
55039  * Field Access Macros:
55040  *
55041  */
55042 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field. */
55043 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_LSB 0
55044 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field. */
55045 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_MSB 15
55046 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field. */
55047 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_WIDTH 16
55048 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field value. */
55049 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_SET_MSK 0x0000ffff
55050 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field value. */
55051 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_CLR_MSK 0xffff0000
55052 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field. */
55053 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_RESET 0xffff
55054 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI field value from a register. */
55055 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
55056 /* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field value suitable for setting the register. */
55057 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
55058 
55059 /*
55060  * Field : reserved_30_16
55061  *
55062  * Reserved
55063  *
55064  * Field Access Macros:
55065  *
55066  */
55067 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_RSVD_30_16 register field. */
55068 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_RSVD_30_16_LSB 16
55069 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_RSVD_30_16 register field. */
55070 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_RSVD_30_16_MSB 30
55071 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_RSVD_30_16 register field. */
55072 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_RSVD_30_16_WIDTH 15
55073 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_RSVD_30_16 register field value. */
55074 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
55075 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_RSVD_30_16 register field value. */
55076 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
55077 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_RSVD_30_16 register field. */
55078 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_RSVD_30_16_RESET 0x0
55079 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_RSVD_30_16 field value from a register. */
55080 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
55081 /* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_RSVD_30_16 register field value suitable for setting the register. */
55082 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
55083 
55084 /*
55085  * Field : ae
55086  *
55087  * Address Enable
55088  *
55089  * When this bit is set, the address filter module uses the 72nd MAC address for
55090  * perfect filtering.
55091  *
55092  * When this bit is reset, the address filter module ignores the address for
55093  * filtering.
55094  *
55095  * Field Enumeration Values:
55096  *
55097  * Enum | Value | Description
55098  * :----------------------------------------|:------|:------------
55099  * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_E_DISD | 0x0 |
55100  * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_E_END | 0x1 |
55101  *
55102  * Field Access Macros:
55103  *
55104  */
55105 /*
55106  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE
55107  *
55108  */
55109 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_E_DISD 0x0
55110 /*
55111  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE
55112  *
55113  */
55114 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_E_END 0x1
55115 
55116 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field. */
55117 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_LSB 31
55118 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field. */
55119 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_MSB 31
55120 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field. */
55121 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_WIDTH 1
55122 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field value. */
55123 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_SET_MSK 0x80000000
55124 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field value. */
55125 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_CLR_MSK 0x7fffffff
55126 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field. */
55127 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_RESET 0x0
55128 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE field value from a register. */
55129 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
55130 /* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field value suitable for setting the register. */
55131 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
55132 
55133 #ifndef __ASSEMBLY__
55134 /*
55135  * WARNING: The C register and register group struct declarations are provided for
55136  * convenience and illustrative purposes. They should, however, be used with
55137  * caution as the C language standard provides no guarantees about the alignment or
55138  * atomicity of device memory accesses. The recommended practice for writing
55139  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
55140  * alt_write_word() functions.
55141  *
55142  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR71_HIGH.
55143  */
55144 struct ALT_EMAC_GMAC_MAC_ADDR71_HIGH_s
55145 {
55146  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI */
55147  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR71_HIGH_RSVD_30_16 */
55148  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE */
55149 };
55150 
55151 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR71_HIGH. */
55152 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR71_HIGH_s ALT_EMAC_GMAC_MAC_ADDR71_HIGH_t;
55153 #endif /* __ASSEMBLY__ */
55154 
55155 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH register. */
55156 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_RESET 0x0000ffff
55157 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH register from the beginning of the component. */
55158 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_OFST 0x9b8
55159 /* The address of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH register. */
55160 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR71_HIGH_OFST))
55161 
55162 /*
55163  * Register : gmacgrp_mac_address71_low
55164  *
55165  * <b> Register 623 (MAC Address71 Low Register)</b>
55166  *
55167  * The MAC Address71 Low register holds the lower 32 bits of the 72nd 6-byte MAC
55168  * address of the station.
55169  *
55170  * Register Layout
55171  *
55172  * Bits | Access | Reset | Description
55173  * :-------|:-------|:-----------|:------------------------------------
55174  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO
55175  *
55176  */
55177 /*
55178  * Field : addrlo
55179  *
55180  * MAC Address71 [31:0]
55181  *
55182  * This field contains the lower 32 bits of the 72nd 6-byte MAC address. The
55183  * content of this field is undefined until loaded by the Application after the
55184  * initialization process.
55185  *
55186  * Field Access Macros:
55187  *
55188  */
55189 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field. */
55190 #define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_LSB 0
55191 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field. */
55192 #define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_MSB 31
55193 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field. */
55194 #define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_WIDTH 32
55195 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field value. */
55196 #define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_SET_MSK 0xffffffff
55197 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field value. */
55198 #define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_CLR_MSK 0x00000000
55199 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field. */
55200 #define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_RESET 0xffffffff
55201 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO field value from a register. */
55202 #define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
55203 /* Produces a ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field value suitable for setting the register. */
55204 #define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
55205 
55206 #ifndef __ASSEMBLY__
55207 /*
55208  * WARNING: The C register and register group struct declarations are provided for
55209  * convenience and illustrative purposes. They should, however, be used with
55210  * caution as the C language standard provides no guarantees about the alignment or
55211  * atomicity of device memory accesses. The recommended practice for writing
55212  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
55213  * alt_write_word() functions.
55214  *
55215  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR71_LOW.
55216  */
55217 struct ALT_EMAC_GMAC_MAC_ADDR71_LOW_s
55218 {
55219  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO */
55220 };
55221 
55222 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR71_LOW. */
55223 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR71_LOW_s ALT_EMAC_GMAC_MAC_ADDR71_LOW_t;
55224 #endif /* __ASSEMBLY__ */
55225 
55226 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_LOW register. */
55227 #define ALT_EMAC_GMAC_MAC_ADDR71_LOW_RESET 0xffffffff
55228 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR71_LOW register from the beginning of the component. */
55229 #define ALT_EMAC_GMAC_MAC_ADDR71_LOW_OFST 0x9bc
55230 /* The address of the ALT_EMAC_GMAC_MAC_ADDR71_LOW register. */
55231 #define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR71_LOW_OFST))
55232 
55233 /*
55234  * Register : gmacgrp_mac_address72_high
55235  *
55236  * <b> Register 624 (MAC Address72 High Register)</b>
55237  *
55238  * The MAC Address72 High register holds the upper 16 bits of the 73rd 6-byte MAC
55239  * address of the station.
55240  *
55241  * If the MAC address registers are configured to be double-synchronized to the
55242  * (G)MII clock domains, then
55243  *
55244  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
55245  * or Bits[7:0] (in big-endian mode) of the MAC Address72 Low Register are written.
55246  * For proper synchronization updates, consecutive writes to this MAC Address72 Low
55247  * Register must be performed after at least four clock cycles in the destination
55248  * clock domain.
55249  *
55250  * Register Layout
55251  *
55252  * Bits | Access | Reset | Description
55253  * :--------|:-------|:-------|:-----------------------------------------
55254  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI
55255  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR72_HIGH_RSVD_30_16
55256  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE
55257  *
55258  */
55259 /*
55260  * Field : addrhi
55261  *
55262  * MAC Address72 [47:32]
55263  *
55264  * This field contains the upper 16 bits (47:32) of the 73rd 6-byte MAC address.
55265  *
55266  * Field Access Macros:
55267  *
55268  */
55269 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field. */
55270 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_LSB 0
55271 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field. */
55272 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_MSB 15
55273 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field. */
55274 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_WIDTH 16
55275 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field value. */
55276 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_SET_MSK 0x0000ffff
55277 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field value. */
55278 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_CLR_MSK 0xffff0000
55279 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field. */
55280 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_RESET 0xffff
55281 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI field value from a register. */
55282 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
55283 /* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field value suitable for setting the register. */
55284 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
55285 
55286 /*
55287  * Field : reserved_30_16
55288  *
55289  * Reserved
55290  *
55291  * Field Access Macros:
55292  *
55293  */
55294 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_RSVD_30_16 register field. */
55295 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_RSVD_30_16_LSB 16
55296 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_RSVD_30_16 register field. */
55297 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_RSVD_30_16_MSB 30
55298 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_RSVD_30_16 register field. */
55299 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_RSVD_30_16_WIDTH 15
55300 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_RSVD_30_16 register field value. */
55301 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
55302 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_RSVD_30_16 register field value. */
55303 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
55304 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_RSVD_30_16 register field. */
55305 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_RSVD_30_16_RESET 0x0
55306 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_RSVD_30_16 field value from a register. */
55307 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
55308 /* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_RSVD_30_16 register field value suitable for setting the register. */
55309 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
55310 
55311 /*
55312  * Field : ae
55313  *
55314  * Address Enable
55315  *
55316  * When this bit is set, the address filter module uses the 73rd MAC address for
55317  * perfect filtering.
55318  *
55319  * When this bit is reset, the address filter module ignores the address for
55320  * filtering.
55321  *
55322  * Field Enumeration Values:
55323  *
55324  * Enum | Value | Description
55325  * :----------------------------------------|:------|:------------
55326  * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_E_DISD | 0x0 |
55327  * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_E_END | 0x1 |
55328  *
55329  * Field Access Macros:
55330  *
55331  */
55332 /*
55333  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE
55334  *
55335  */
55336 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_E_DISD 0x0
55337 /*
55338  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE
55339  *
55340  */
55341 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_E_END 0x1
55342 
55343 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field. */
55344 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_LSB 31
55345 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field. */
55346 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_MSB 31
55347 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field. */
55348 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_WIDTH 1
55349 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field value. */
55350 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_SET_MSK 0x80000000
55351 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field value. */
55352 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_CLR_MSK 0x7fffffff
55353 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field. */
55354 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_RESET 0x0
55355 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE field value from a register. */
55356 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
55357 /* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field value suitable for setting the register. */
55358 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
55359 
55360 #ifndef __ASSEMBLY__
55361 /*
55362  * WARNING: The C register and register group struct declarations are provided for
55363  * convenience and illustrative purposes. They should, however, be used with
55364  * caution as the C language standard provides no guarantees about the alignment or
55365  * atomicity of device memory accesses. The recommended practice for writing
55366  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
55367  * alt_write_word() functions.
55368  *
55369  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR72_HIGH.
55370  */
55371 struct ALT_EMAC_GMAC_MAC_ADDR72_HIGH_s
55372 {
55373  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI */
55374  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR72_HIGH_RSVD_30_16 */
55375  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE */
55376 };
55377 
55378 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR72_HIGH. */
55379 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR72_HIGH_s ALT_EMAC_GMAC_MAC_ADDR72_HIGH_t;
55380 #endif /* __ASSEMBLY__ */
55381 
55382 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH register. */
55383 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_RESET 0x0000ffff
55384 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH register from the beginning of the component. */
55385 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_OFST 0x9c0
55386 /* The address of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH register. */
55387 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR72_HIGH_OFST))
55388 
55389 /*
55390  * Register : gmacgrp_mac_address72_low
55391  *
55392  * <b> Register 625 (MAC Address72 Low Register)</b>
55393  *
55394  * The MAC Address72 Low register holds the lower 32 bits of the 73rd 6-byte MAC
55395  * address of the station.
55396  *
55397  * Register Layout
55398  *
55399  * Bits | Access | Reset | Description
55400  * :-------|:-------|:-----------|:------------------------------------
55401  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO
55402  *
55403  */
55404 /*
55405  * Field : addrlo
55406  *
55407  * MAC Address72 [31:0]
55408  *
55409  * This field contains the lower 32 bits of the 73rd 6-byte MAC address. The
55410  * content of this field is undefined until loaded by the Application after the
55411  * initialization process.
55412  *
55413  * Field Access Macros:
55414  *
55415  */
55416 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field. */
55417 #define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_LSB 0
55418 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field. */
55419 #define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_MSB 31
55420 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field. */
55421 #define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_WIDTH 32
55422 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field value. */
55423 #define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_SET_MSK 0xffffffff
55424 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field value. */
55425 #define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_CLR_MSK 0x00000000
55426 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field. */
55427 #define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_RESET 0xffffffff
55428 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO field value from a register. */
55429 #define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
55430 /* Produces a ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field value suitable for setting the register. */
55431 #define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
55432 
55433 #ifndef __ASSEMBLY__
55434 /*
55435  * WARNING: The C register and register group struct declarations are provided for
55436  * convenience and illustrative purposes. They should, however, be used with
55437  * caution as the C language standard provides no guarantees about the alignment or
55438  * atomicity of device memory accesses. The recommended practice for writing
55439  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
55440  * alt_write_word() functions.
55441  *
55442  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR72_LOW.
55443  */
55444 struct ALT_EMAC_GMAC_MAC_ADDR72_LOW_s
55445 {
55446  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO */
55447 };
55448 
55449 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR72_LOW. */
55450 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR72_LOW_s ALT_EMAC_GMAC_MAC_ADDR72_LOW_t;
55451 #endif /* __ASSEMBLY__ */
55452 
55453 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_LOW register. */
55454 #define ALT_EMAC_GMAC_MAC_ADDR72_LOW_RESET 0xffffffff
55455 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR72_LOW register from the beginning of the component. */
55456 #define ALT_EMAC_GMAC_MAC_ADDR72_LOW_OFST 0x9c4
55457 /* The address of the ALT_EMAC_GMAC_MAC_ADDR72_LOW register. */
55458 #define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR72_LOW_OFST))
55459 
55460 /*
55461  * Register : gmacgrp_mac_address73_high
55462  *
55463  * <b> Register 626 (MAC Address73 High Register)</b>
55464  *
55465  * The MAC Address73 High register holds the upper 16 bits of the 74th 6-byte MAC
55466  * address of the station.
55467  *
55468  * If the MAC address registers are configured to be double-synchronized to the
55469  * (G)MII clock domains, then
55470  *
55471  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
55472  * or Bits[7:0] (in big-endian mode) of the MAC Address73 Low Register are written.
55473  * For proper synchronization updates, consecutive writes to this MAC Address73 Low
55474  * Register must be performed after at least four clock cycles in the destination
55475  * clock domain.
55476  *
55477  * Register Layout
55478  *
55479  * Bits | Access | Reset | Description
55480  * :--------|:-------|:-------|:-----------------------------------------
55481  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI
55482  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR73_HIGH_RSVD_30_16
55483  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE
55484  *
55485  */
55486 /*
55487  * Field : addrhi
55488  *
55489  * MAC Address73 [47:32]
55490  *
55491  * This field contains the upper 16 bits (47:32) of the 74th 6-byte MAC address.
55492  *
55493  * Field Access Macros:
55494  *
55495  */
55496 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field. */
55497 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_LSB 0
55498 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field. */
55499 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_MSB 15
55500 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field. */
55501 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_WIDTH 16
55502 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field value. */
55503 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_SET_MSK 0x0000ffff
55504 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field value. */
55505 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_CLR_MSK 0xffff0000
55506 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field. */
55507 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_RESET 0xffff
55508 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI field value from a register. */
55509 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
55510 /* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field value suitable for setting the register. */
55511 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
55512 
55513 /*
55514  * Field : reserved_30_16
55515  *
55516  * Reserved
55517  *
55518  * Field Access Macros:
55519  *
55520  */
55521 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_RSVD_30_16 register field. */
55522 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_RSVD_30_16_LSB 16
55523 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_RSVD_30_16 register field. */
55524 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_RSVD_30_16_MSB 30
55525 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_RSVD_30_16 register field. */
55526 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_RSVD_30_16_WIDTH 15
55527 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_RSVD_30_16 register field value. */
55528 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
55529 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_RSVD_30_16 register field value. */
55530 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
55531 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_RSVD_30_16 register field. */
55532 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_RSVD_30_16_RESET 0x0
55533 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_RSVD_30_16 field value from a register. */
55534 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
55535 /* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_RSVD_30_16 register field value suitable for setting the register. */
55536 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
55537 
55538 /*
55539  * Field : ae
55540  *
55541  * Address Enable
55542  *
55543  * When this bit is set, the address filter module uses the 74th MAC address for
55544  * perfect filtering.
55545  *
55546  * When this bit is reset, the address filter module ignores the address for
55547  * filtering.
55548  *
55549  * Field Enumeration Values:
55550  *
55551  * Enum | Value | Description
55552  * :----------------------------------------|:------|:------------
55553  * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_E_DISD | 0x0 |
55554  * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_E_END | 0x1 |
55555  *
55556  * Field Access Macros:
55557  *
55558  */
55559 /*
55560  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE
55561  *
55562  */
55563 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_E_DISD 0x0
55564 /*
55565  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE
55566  *
55567  */
55568 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_E_END 0x1
55569 
55570 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field. */
55571 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_LSB 31
55572 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field. */
55573 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_MSB 31
55574 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field. */
55575 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_WIDTH 1
55576 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field value. */
55577 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_SET_MSK 0x80000000
55578 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field value. */
55579 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_CLR_MSK 0x7fffffff
55580 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field. */
55581 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_RESET 0x0
55582 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE field value from a register. */
55583 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
55584 /* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field value suitable for setting the register. */
55585 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
55586 
55587 #ifndef __ASSEMBLY__
55588 /*
55589  * WARNING: The C register and register group struct declarations are provided for
55590  * convenience and illustrative purposes. They should, however, be used with
55591  * caution as the C language standard provides no guarantees about the alignment or
55592  * atomicity of device memory accesses. The recommended practice for writing
55593  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
55594  * alt_write_word() functions.
55595  *
55596  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR73_HIGH.
55597  */
55598 struct ALT_EMAC_GMAC_MAC_ADDR73_HIGH_s
55599 {
55600  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI */
55601  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR73_HIGH_RSVD_30_16 */
55602  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE */
55603 };
55604 
55605 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR73_HIGH. */
55606 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR73_HIGH_s ALT_EMAC_GMAC_MAC_ADDR73_HIGH_t;
55607 #endif /* __ASSEMBLY__ */
55608 
55609 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH register. */
55610 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_RESET 0x0000ffff
55611 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH register from the beginning of the component. */
55612 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_OFST 0x9c8
55613 /* The address of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH register. */
55614 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR73_HIGH_OFST))
55615 
55616 /*
55617  * Register : gmacgrp_mac_address73_low
55618  *
55619  * <b> Register 627 (MAC Address73 Low Register)</b>
55620  *
55621  * The MAC Address73 Low register holds the lower 32 bits of the 74th 6-byte MAC
55622  * address of the station.
55623  *
55624  * Register Layout
55625  *
55626  * Bits | Access | Reset | Description
55627  * :-------|:-------|:-----------|:------------------------------------
55628  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO
55629  *
55630  */
55631 /*
55632  * Field : addrlo
55633  *
55634  * MAC Address73 [31:0]
55635  *
55636  * This field contains the lower 32 bits of the 74th 6-byte MAC address. The
55637  * content of this field is undefined until loaded by the Application after the
55638  * initialization process.
55639  *
55640  * Field Access Macros:
55641  *
55642  */
55643 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field. */
55644 #define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_LSB 0
55645 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field. */
55646 #define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_MSB 31
55647 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field. */
55648 #define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_WIDTH 32
55649 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field value. */
55650 #define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_SET_MSK 0xffffffff
55651 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field value. */
55652 #define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_CLR_MSK 0x00000000
55653 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field. */
55654 #define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_RESET 0xffffffff
55655 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO field value from a register. */
55656 #define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
55657 /* Produces a ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field value suitable for setting the register. */
55658 #define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
55659 
55660 #ifndef __ASSEMBLY__
55661 /*
55662  * WARNING: The C register and register group struct declarations are provided for
55663  * convenience and illustrative purposes. They should, however, be used with
55664  * caution as the C language standard provides no guarantees about the alignment or
55665  * atomicity of device memory accesses. The recommended practice for writing
55666  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
55667  * alt_write_word() functions.
55668  *
55669  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR73_LOW.
55670  */
55671 struct ALT_EMAC_GMAC_MAC_ADDR73_LOW_s
55672 {
55673  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO */
55674 };
55675 
55676 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR73_LOW. */
55677 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR73_LOW_s ALT_EMAC_GMAC_MAC_ADDR73_LOW_t;
55678 #endif /* __ASSEMBLY__ */
55679 
55680 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_LOW register. */
55681 #define ALT_EMAC_GMAC_MAC_ADDR73_LOW_RESET 0xffffffff
55682 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR73_LOW register from the beginning of the component. */
55683 #define ALT_EMAC_GMAC_MAC_ADDR73_LOW_OFST 0x9cc
55684 /* The address of the ALT_EMAC_GMAC_MAC_ADDR73_LOW register. */
55685 #define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR73_LOW_OFST))
55686 
55687 /*
55688  * Register : gmacgrp_mac_address74_high
55689  *
55690  * <b> Register 628 (MAC Address74 High Register)</b>
55691  *
55692  * The MAC Address74 High register holds the upper 16 bits of the 75th 6-byte MAC
55693  * address of the station.
55694  *
55695  * If the MAC address registers are configured to be double-synchronized to the
55696  * (G)MII clock domains, then
55697  *
55698  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
55699  * or Bits[7:0] (in big-endian mode) of the MAC Address74 Low Register are written.
55700  * For proper synchronization updates, consecutive writes to this MAC Address74 Low
55701  * Register must be performed after at least four clock cycles in the destination
55702  * clock domain.
55703  *
55704  * Register Layout
55705  *
55706  * Bits | Access | Reset | Description
55707  * :--------|:-------|:-------|:-----------------------------------------
55708  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI
55709  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR74_HIGH_RSVD_30_16
55710  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE
55711  *
55712  */
55713 /*
55714  * Field : addrhi
55715  *
55716  * MAC Address74 [47:32]
55717  *
55718  * This field contains the upper 16 bits (47:32) of the 75th 6-byte MAC address.
55719  *
55720  * Field Access Macros:
55721  *
55722  */
55723 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field. */
55724 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_LSB 0
55725 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field. */
55726 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_MSB 15
55727 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field. */
55728 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_WIDTH 16
55729 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field value. */
55730 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_SET_MSK 0x0000ffff
55731 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field value. */
55732 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_CLR_MSK 0xffff0000
55733 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field. */
55734 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_RESET 0xffff
55735 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI field value from a register. */
55736 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
55737 /* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field value suitable for setting the register. */
55738 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
55739 
55740 /*
55741  * Field : reserved_30_16
55742  *
55743  * Reserved
55744  *
55745  * Field Access Macros:
55746  *
55747  */
55748 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_RSVD_30_16 register field. */
55749 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_RSVD_30_16_LSB 16
55750 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_RSVD_30_16 register field. */
55751 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_RSVD_30_16_MSB 30
55752 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_RSVD_30_16 register field. */
55753 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_RSVD_30_16_WIDTH 15
55754 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_RSVD_30_16 register field value. */
55755 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
55756 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_RSVD_30_16 register field value. */
55757 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
55758 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_RSVD_30_16 register field. */
55759 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_RSVD_30_16_RESET 0x0
55760 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_RSVD_30_16 field value from a register. */
55761 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
55762 /* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_RSVD_30_16 register field value suitable for setting the register. */
55763 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
55764 
55765 /*
55766  * Field : ae
55767  *
55768  * Address Enable
55769  *
55770  * When this bit is set, the address filter module uses the 75th MAC address for
55771  * perfect filtering.
55772  *
55773  * When this bit is reset, the address filter module ignores the address for
55774  * filtering.
55775  *
55776  * Field Enumeration Values:
55777  *
55778  * Enum | Value | Description
55779  * :----------------------------------------|:------|:------------
55780  * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_E_DISD | 0x0 |
55781  * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_E_END | 0x1 |
55782  *
55783  * Field Access Macros:
55784  *
55785  */
55786 /*
55787  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE
55788  *
55789  */
55790 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_E_DISD 0x0
55791 /*
55792  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE
55793  *
55794  */
55795 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_E_END 0x1
55796 
55797 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field. */
55798 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_LSB 31
55799 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field. */
55800 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_MSB 31
55801 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field. */
55802 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_WIDTH 1
55803 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field value. */
55804 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_SET_MSK 0x80000000
55805 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field value. */
55806 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_CLR_MSK 0x7fffffff
55807 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field. */
55808 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_RESET 0x0
55809 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE field value from a register. */
55810 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
55811 /* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field value suitable for setting the register. */
55812 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
55813 
55814 #ifndef __ASSEMBLY__
55815 /*
55816  * WARNING: The C register and register group struct declarations are provided for
55817  * convenience and illustrative purposes. They should, however, be used with
55818  * caution as the C language standard provides no guarantees about the alignment or
55819  * atomicity of device memory accesses. The recommended practice for writing
55820  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
55821  * alt_write_word() functions.
55822  *
55823  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR74_HIGH.
55824  */
55825 struct ALT_EMAC_GMAC_MAC_ADDR74_HIGH_s
55826 {
55827  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI */
55828  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR74_HIGH_RSVD_30_16 */
55829  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE */
55830 };
55831 
55832 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR74_HIGH. */
55833 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR74_HIGH_s ALT_EMAC_GMAC_MAC_ADDR74_HIGH_t;
55834 #endif /* __ASSEMBLY__ */
55835 
55836 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH register. */
55837 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_RESET 0x0000ffff
55838 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH register from the beginning of the component. */
55839 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_OFST 0x9d0
55840 /* The address of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH register. */
55841 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR74_HIGH_OFST))
55842 
55843 /*
55844  * Register : gmacgrp_mac_address74_low
55845  *
55846  * <b> Register 629 (MAC Address74 Low Register)</b>
55847  *
55848  * The MAC Address74 Low register holds the lower 32 bits of the 75th 6-byte MAC
55849  * address of the station.
55850  *
55851  * Register Layout
55852  *
55853  * Bits | Access | Reset | Description
55854  * :-------|:-------|:-----------|:------------------------------------
55855  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO
55856  *
55857  */
55858 /*
55859  * Field : addrlo
55860  *
55861  * MAC Address74 [31:0]
55862  *
55863  * This field contains the lower 32 bits of the 75th 6-byte MAC address. The
55864  * content of this field is undefined until loaded by the Application after the
55865  * initialization process.
55866  *
55867  * Field Access Macros:
55868  *
55869  */
55870 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field. */
55871 #define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_LSB 0
55872 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field. */
55873 #define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_MSB 31
55874 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field. */
55875 #define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_WIDTH 32
55876 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field value. */
55877 #define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_SET_MSK 0xffffffff
55878 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field value. */
55879 #define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_CLR_MSK 0x00000000
55880 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field. */
55881 #define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_RESET 0xffffffff
55882 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO field value from a register. */
55883 #define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
55884 /* Produces a ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field value suitable for setting the register. */
55885 #define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
55886 
55887 #ifndef __ASSEMBLY__
55888 /*
55889  * WARNING: The C register and register group struct declarations are provided for
55890  * convenience and illustrative purposes. They should, however, be used with
55891  * caution as the C language standard provides no guarantees about the alignment or
55892  * atomicity of device memory accesses. The recommended practice for writing
55893  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
55894  * alt_write_word() functions.
55895  *
55896  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR74_LOW.
55897  */
55898 struct ALT_EMAC_GMAC_MAC_ADDR74_LOW_s
55899 {
55900  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO */
55901 };
55902 
55903 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR74_LOW. */
55904 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR74_LOW_s ALT_EMAC_GMAC_MAC_ADDR74_LOW_t;
55905 #endif /* __ASSEMBLY__ */
55906 
55907 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_LOW register. */
55908 #define ALT_EMAC_GMAC_MAC_ADDR74_LOW_RESET 0xffffffff
55909 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR74_LOW register from the beginning of the component. */
55910 #define ALT_EMAC_GMAC_MAC_ADDR74_LOW_OFST 0x9d4
55911 /* The address of the ALT_EMAC_GMAC_MAC_ADDR74_LOW register. */
55912 #define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR74_LOW_OFST))
55913 
55914 /*
55915  * Register : gmacgrp_mac_address75_high
55916  *
55917  * <b> Register 630 (MAC Address75 High Register) </b>
55918  *
55919  * The MAC Address75 High register holds the upper 16 bits of the 76th 6-byte MAC
55920  * address of the station.
55921  *
55922  * If the MAC address registers are configured to be double-synchronized to the
55923  * (G)MII clock domains, then
55924  *
55925  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
55926  * or Bits[7:0] (in big-endian mode) of the MAC Address75 Low Register are written.
55927  * For proper synchronization updates, consecutive writes to this MAC Address75 Low
55928  * Register must be performed after at least four clock cycles in the destination
55929  * clock domain.
55930  *
55931  * Register Layout
55932  *
55933  * Bits | Access | Reset | Description
55934  * :--------|:-------|:-------|:-----------------------------------------
55935  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI
55936  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR75_HIGH_RSVD_30_16
55937  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE
55938  *
55939  */
55940 /*
55941  * Field : addrhi
55942  *
55943  * MAC Address75 [47:32]
55944  *
55945  * This field contains the upper 16 bits (47:32) of the 76th 6-byte MAC address.
55946  *
55947  * Field Access Macros:
55948  *
55949  */
55950 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field. */
55951 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_LSB 0
55952 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field. */
55953 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_MSB 15
55954 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field. */
55955 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_WIDTH 16
55956 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field value. */
55957 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_SET_MSK 0x0000ffff
55958 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field value. */
55959 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_CLR_MSK 0xffff0000
55960 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field. */
55961 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_RESET 0xffff
55962 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI field value from a register. */
55963 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
55964 /* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field value suitable for setting the register. */
55965 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
55966 
55967 /*
55968  * Field : reserved_30_16
55969  *
55970  * Reserved
55971  *
55972  * Field Access Macros:
55973  *
55974  */
55975 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_RSVD_30_16 register field. */
55976 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_RSVD_30_16_LSB 16
55977 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_RSVD_30_16 register field. */
55978 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_RSVD_30_16_MSB 30
55979 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_RSVD_30_16 register field. */
55980 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_RSVD_30_16_WIDTH 15
55981 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_RSVD_30_16 register field value. */
55982 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
55983 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_RSVD_30_16 register field value. */
55984 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
55985 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_RSVD_30_16 register field. */
55986 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_RSVD_30_16_RESET 0x0
55987 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_RSVD_30_16 field value from a register. */
55988 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
55989 /* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_RSVD_30_16 register field value suitable for setting the register. */
55990 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
55991 
55992 /*
55993  * Field : ae
55994  *
55995  * Address Enable
55996  *
55997  * When this bit is set, the address filter module uses the 76th MAC address for
55998  * perfect filtering.
55999  *
56000  * When this bit is reset, the address filter module ignores the address for
56001  * filtering.
56002  *
56003  * Field Enumeration Values:
56004  *
56005  * Enum | Value | Description
56006  * :----------------------------------------|:------|:------------
56007  * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_E_DISD | 0x0 |
56008  * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_E_END | 0x1 |
56009  *
56010  * Field Access Macros:
56011  *
56012  */
56013 /*
56014  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE
56015  *
56016  */
56017 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_E_DISD 0x0
56018 /*
56019  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE
56020  *
56021  */
56022 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_E_END 0x1
56023 
56024 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field. */
56025 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_LSB 31
56026 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field. */
56027 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_MSB 31
56028 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field. */
56029 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_WIDTH 1
56030 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field value. */
56031 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_SET_MSK 0x80000000
56032 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field value. */
56033 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_CLR_MSK 0x7fffffff
56034 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field. */
56035 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_RESET 0x0
56036 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE field value from a register. */
56037 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
56038 /* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field value suitable for setting the register. */
56039 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
56040 
56041 #ifndef __ASSEMBLY__
56042 /*
56043  * WARNING: The C register and register group struct declarations are provided for
56044  * convenience and illustrative purposes. They should, however, be used with
56045  * caution as the C language standard provides no guarantees about the alignment or
56046  * atomicity of device memory accesses. The recommended practice for writing
56047  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
56048  * alt_write_word() functions.
56049  *
56050  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR75_HIGH.
56051  */
56052 struct ALT_EMAC_GMAC_MAC_ADDR75_HIGH_s
56053 {
56054  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI */
56055  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR75_HIGH_RSVD_30_16 */
56056  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE */
56057 };
56058 
56059 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR75_HIGH. */
56060 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR75_HIGH_s ALT_EMAC_GMAC_MAC_ADDR75_HIGH_t;
56061 #endif /* __ASSEMBLY__ */
56062 
56063 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH register. */
56064 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_RESET 0x0000ffff
56065 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH register from the beginning of the component. */
56066 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_OFST 0x9d8
56067 /* The address of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH register. */
56068 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR75_HIGH_OFST))
56069 
56070 /*
56071  * Register : gmacgrp_mac_address75_low
56072  *
56073  * <b> Register 631 (MAC Address75 Low Register) </b>
56074  *
56075  * The MAC Address75 Low register holds the lower 32 bits of the 76th 6-byte MAC
56076  * address of the station.
56077  *
56078  * Register Layout
56079  *
56080  * Bits | Access | Reset | Description
56081  * :-------|:-------|:-----------|:------------------------------------
56082  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO
56083  *
56084  */
56085 /*
56086  * Field : addrlo
56087  *
56088  * MAC Address75 [31:0]
56089  *
56090  * This field contains the lower 32 bits of the 76th 6-byte MAC address. The
56091  * content of this field is undefined until loaded by the Application after the
56092  * initialization process.
56093  *
56094  * Field Access Macros:
56095  *
56096  */
56097 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field. */
56098 #define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_LSB 0
56099 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field. */
56100 #define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_MSB 31
56101 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field. */
56102 #define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_WIDTH 32
56103 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field value. */
56104 #define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_SET_MSK 0xffffffff
56105 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field value. */
56106 #define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_CLR_MSK 0x00000000
56107 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field. */
56108 #define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_RESET 0xffffffff
56109 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO field value from a register. */
56110 #define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
56111 /* Produces a ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field value suitable for setting the register. */
56112 #define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
56113 
56114 #ifndef __ASSEMBLY__
56115 /*
56116  * WARNING: The C register and register group struct declarations are provided for
56117  * convenience and illustrative purposes. They should, however, be used with
56118  * caution as the C language standard provides no guarantees about the alignment or
56119  * atomicity of device memory accesses. The recommended practice for writing
56120  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
56121  * alt_write_word() functions.
56122  *
56123  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR75_LOW.
56124  */
56125 struct ALT_EMAC_GMAC_MAC_ADDR75_LOW_s
56126 {
56127  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO */
56128 };
56129 
56130 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR75_LOW. */
56131 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR75_LOW_s ALT_EMAC_GMAC_MAC_ADDR75_LOW_t;
56132 #endif /* __ASSEMBLY__ */
56133 
56134 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_LOW register. */
56135 #define ALT_EMAC_GMAC_MAC_ADDR75_LOW_RESET 0xffffffff
56136 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR75_LOW register from the beginning of the component. */
56137 #define ALT_EMAC_GMAC_MAC_ADDR75_LOW_OFST 0x9dc
56138 /* The address of the ALT_EMAC_GMAC_MAC_ADDR75_LOW register. */
56139 #define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR75_LOW_OFST))
56140 
56141 /*
56142  * Register : gmacgrp_mac_address76_high
56143  *
56144  * <b> Register 632 (MAC Address76 High Register) </b>
56145  *
56146  * The MAC Address76 High register holds the upper 16 bits of the 77th 6-byte MAC
56147  * address of the station.
56148  *
56149  * If the MAC address registers are configured to be double-synchronized to the
56150  * (G)MII clock domains, then
56151  *
56152  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
56153  * or Bits[7:0] (in big-endian mode) of the MAC Address76 Low Register are written.
56154  * For proper synchronization updates, consecutive writes to this MAC Address76 Low
56155  * Register must be performed after at least four clock cycles in the destination
56156  * clock domain.
56157  *
56158  * Register Layout
56159  *
56160  * Bits | Access | Reset | Description
56161  * :--------|:-------|:-------|:-----------------------------------------
56162  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI
56163  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR76_HIGH_RSVD_30_16
56164  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE
56165  *
56166  */
56167 /*
56168  * Field : addrhi
56169  *
56170  * MAC Address76 [47:32]
56171  *
56172  * This field contains the upper 16 bits (47:32) of the 77th 6-byte MAC address.
56173  *
56174  * Field Access Macros:
56175  *
56176  */
56177 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field. */
56178 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_LSB 0
56179 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field. */
56180 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_MSB 15
56181 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field. */
56182 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_WIDTH 16
56183 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field value. */
56184 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_SET_MSK 0x0000ffff
56185 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field value. */
56186 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_CLR_MSK 0xffff0000
56187 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field. */
56188 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_RESET 0xffff
56189 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI field value from a register. */
56190 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
56191 /* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field value suitable for setting the register. */
56192 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
56193 
56194 /*
56195  * Field : reserved_30_16
56196  *
56197  * Reserved
56198  *
56199  * Field Access Macros:
56200  *
56201  */
56202 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_RSVD_30_16 register field. */
56203 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_RSVD_30_16_LSB 16
56204 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_RSVD_30_16 register field. */
56205 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_RSVD_30_16_MSB 30
56206 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_RSVD_30_16 register field. */
56207 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_RSVD_30_16_WIDTH 15
56208 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_RSVD_30_16 register field value. */
56209 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
56210 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_RSVD_30_16 register field value. */
56211 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
56212 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_RSVD_30_16 register field. */
56213 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_RSVD_30_16_RESET 0x0
56214 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_RSVD_30_16 field value from a register. */
56215 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
56216 /* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_RSVD_30_16 register field value suitable for setting the register. */
56217 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
56218 
56219 /*
56220  * Field : ae
56221  *
56222  * Address Enable
56223  *
56224  * When this bit is set, the address filter module uses the 77th MAC address for
56225  * perfect filtering.
56226  *
56227  * When this bit is reset, the address filter module ignores the address for
56228  * filtering.
56229  *
56230  * Field Enumeration Values:
56231  *
56232  * Enum | Value | Description
56233  * :----------------------------------------|:------|:------------
56234  * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_E_DISD | 0x0 |
56235  * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_E_END | 0x1 |
56236  *
56237  * Field Access Macros:
56238  *
56239  */
56240 /*
56241  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE
56242  *
56243  */
56244 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_E_DISD 0x0
56245 /*
56246  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE
56247  *
56248  */
56249 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_E_END 0x1
56250 
56251 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field. */
56252 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_LSB 31
56253 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field. */
56254 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_MSB 31
56255 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field. */
56256 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_WIDTH 1
56257 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field value. */
56258 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_SET_MSK 0x80000000
56259 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field value. */
56260 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_CLR_MSK 0x7fffffff
56261 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field. */
56262 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_RESET 0x0
56263 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE field value from a register. */
56264 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
56265 /* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field value suitable for setting the register. */
56266 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
56267 
56268 #ifndef __ASSEMBLY__
56269 /*
56270  * WARNING: The C register and register group struct declarations are provided for
56271  * convenience and illustrative purposes. They should, however, be used with
56272  * caution as the C language standard provides no guarantees about the alignment or
56273  * atomicity of device memory accesses. The recommended practice for writing
56274  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
56275  * alt_write_word() functions.
56276  *
56277  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR76_HIGH.
56278  */
56279 struct ALT_EMAC_GMAC_MAC_ADDR76_HIGH_s
56280 {
56281  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI */
56282  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR76_HIGH_RSVD_30_16 */
56283  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE */
56284 };
56285 
56286 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR76_HIGH. */
56287 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR76_HIGH_s ALT_EMAC_GMAC_MAC_ADDR76_HIGH_t;
56288 #endif /* __ASSEMBLY__ */
56289 
56290 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH register. */
56291 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_RESET 0x0000ffff
56292 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH register from the beginning of the component. */
56293 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_OFST 0x9e0
56294 /* The address of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH register. */
56295 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR76_HIGH_OFST))
56296 
56297 /*
56298  * Register : gmacgrp_mac_address76_low
56299  *
56300  * <b> Register 633 (MAC Address76 Low Register) </b>
56301  *
56302  * The MAC Address76 Low register holds the lower 32 bits of the 77th 6-byte MAC
56303  * address of the station.
56304  *
56305  * Register Layout
56306  *
56307  * Bits | Access | Reset | Description
56308  * :-------|:-------|:-----------|:------------------------------------
56309  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO
56310  *
56311  */
56312 /*
56313  * Field : addrlo
56314  *
56315  * MAC Address76 [31:0]
56316  *
56317  * This field contains the lower 32 bits of the 77th 6-byte MAC address. The
56318  * content of this field is undefined until loaded by the Application after the
56319  * initialization process.
56320  *
56321  * Field Access Macros:
56322  *
56323  */
56324 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field. */
56325 #define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_LSB 0
56326 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field. */
56327 #define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_MSB 31
56328 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field. */
56329 #define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_WIDTH 32
56330 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field value. */
56331 #define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_SET_MSK 0xffffffff
56332 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field value. */
56333 #define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_CLR_MSK 0x00000000
56334 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field. */
56335 #define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_RESET 0xffffffff
56336 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO field value from a register. */
56337 #define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
56338 /* Produces a ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field value suitable for setting the register. */
56339 #define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
56340 
56341 #ifndef __ASSEMBLY__
56342 /*
56343  * WARNING: The C register and register group struct declarations are provided for
56344  * convenience and illustrative purposes. They should, however, be used with
56345  * caution as the C language standard provides no guarantees about the alignment or
56346  * atomicity of device memory accesses. The recommended practice for writing
56347  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
56348  * alt_write_word() functions.
56349  *
56350  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR76_LOW.
56351  */
56352 struct ALT_EMAC_GMAC_MAC_ADDR76_LOW_s
56353 {
56354  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO */
56355 };
56356 
56357 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR76_LOW. */
56358 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR76_LOW_s ALT_EMAC_GMAC_MAC_ADDR76_LOW_t;
56359 #endif /* __ASSEMBLY__ */
56360 
56361 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_LOW register. */
56362 #define ALT_EMAC_GMAC_MAC_ADDR76_LOW_RESET 0xffffffff
56363 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR76_LOW register from the beginning of the component. */
56364 #define ALT_EMAC_GMAC_MAC_ADDR76_LOW_OFST 0x9e4
56365 /* The address of the ALT_EMAC_GMAC_MAC_ADDR76_LOW register. */
56366 #define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR76_LOW_OFST))
56367 
56368 /*
56369  * Register : gmacgrp_mac_address77_high
56370  *
56371  * <b> Register 634 (MAC Address77 High Register) </b>
56372  *
56373  * The MAC Address77 High register holds the upper 16 bits of the 78th 6-byte MAC
56374  * address of the station.
56375  *
56376  * If the MAC address registers are configured to be double-synchronized to the
56377  * (G)MII clock domains, then
56378  *
56379  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
56380  * or Bits[7:0] (in big-endian mode) of the MAC Address77 Low Register are written.
56381  * For proper synchronization updates, consecutive writes to this MAC Address77 Low
56382  * Register must be performed after at least four clock cycles in the destination
56383  * clock domain.
56384  *
56385  * Register Layout
56386  *
56387  * Bits | Access | Reset | Description
56388  * :--------|:-------|:-------|:-----------------------------------------
56389  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI
56390  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR77_HIGH_RSVD_30_16
56391  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE
56392  *
56393  */
56394 /*
56395  * Field : addrhi
56396  *
56397  * MAC Address77 [47:32]
56398  *
56399  * This field contains the upper 16 bits (47:32) of the 78th 6-byte MAC address.
56400  *
56401  * Field Access Macros:
56402  *
56403  */
56404 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field. */
56405 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_LSB 0
56406 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field. */
56407 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_MSB 15
56408 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field. */
56409 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_WIDTH 16
56410 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field value. */
56411 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_SET_MSK 0x0000ffff
56412 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field value. */
56413 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_CLR_MSK 0xffff0000
56414 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field. */
56415 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_RESET 0xffff
56416 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI field value from a register. */
56417 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
56418 /* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field value suitable for setting the register. */
56419 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
56420 
56421 /*
56422  * Field : reserved_30_16
56423  *
56424  * Reserved
56425  *
56426  * Field Access Macros:
56427  *
56428  */
56429 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_RSVD_30_16 register field. */
56430 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_RSVD_30_16_LSB 16
56431 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_RSVD_30_16 register field. */
56432 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_RSVD_30_16_MSB 30
56433 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_RSVD_30_16 register field. */
56434 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_RSVD_30_16_WIDTH 15
56435 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_RSVD_30_16 register field value. */
56436 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
56437 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_RSVD_30_16 register field value. */
56438 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
56439 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_RSVD_30_16 register field. */
56440 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_RSVD_30_16_RESET 0x0
56441 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_RSVD_30_16 field value from a register. */
56442 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
56443 /* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_RSVD_30_16 register field value suitable for setting the register. */
56444 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
56445 
56446 /*
56447  * Field : ae
56448  *
56449  * Address Enable
56450  *
56451  * When this bit is set, the address filter module uses the 78th MAC address for
56452  * perfect filtering.
56453  *
56454  * When this bit is reset, the address filter module ignores the address for
56455  * filtering.
56456  *
56457  * Field Enumeration Values:
56458  *
56459  * Enum | Value | Description
56460  * :----------------------------------------|:------|:------------
56461  * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_E_DISD | 0x0 |
56462  * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_E_END | 0x1 |
56463  *
56464  * Field Access Macros:
56465  *
56466  */
56467 /*
56468  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE
56469  *
56470  */
56471 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_E_DISD 0x0
56472 /*
56473  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE
56474  *
56475  */
56476 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_E_END 0x1
56477 
56478 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field. */
56479 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_LSB 31
56480 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field. */
56481 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_MSB 31
56482 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field. */
56483 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_WIDTH 1
56484 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field value. */
56485 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_SET_MSK 0x80000000
56486 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field value. */
56487 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_CLR_MSK 0x7fffffff
56488 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field. */
56489 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_RESET 0x0
56490 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE field value from a register. */
56491 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
56492 /* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field value suitable for setting the register. */
56493 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
56494 
56495 #ifndef __ASSEMBLY__
56496 /*
56497  * WARNING: The C register and register group struct declarations are provided for
56498  * convenience and illustrative purposes. They should, however, be used with
56499  * caution as the C language standard provides no guarantees about the alignment or
56500  * atomicity of device memory accesses. The recommended practice for writing
56501  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
56502  * alt_write_word() functions.
56503  *
56504  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR77_HIGH.
56505  */
56506 struct ALT_EMAC_GMAC_MAC_ADDR77_HIGH_s
56507 {
56508  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI */
56509  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR77_HIGH_RSVD_30_16 */
56510  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE */
56511 };
56512 
56513 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR77_HIGH. */
56514 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR77_HIGH_s ALT_EMAC_GMAC_MAC_ADDR77_HIGH_t;
56515 #endif /* __ASSEMBLY__ */
56516 
56517 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH register. */
56518 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_RESET 0x0000ffff
56519 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH register from the beginning of the component. */
56520 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_OFST 0x9e8
56521 /* The address of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH register. */
56522 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR77_HIGH_OFST))
56523 
56524 /*
56525  * Register : gmacgrp_mac_address77_low
56526  *
56527  * <b> Register 635 (MAC Address77 Low Register)</b>
56528  *
56529  * The MAC Address77 Low register holds the lower 32 bits of the 78th 6-byte MAC
56530  * address of the station.
56531  *
56532  * Register Layout
56533  *
56534  * Bits | Access | Reset | Description
56535  * :-------|:-------|:-----------|:------------------------------------
56536  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO
56537  *
56538  */
56539 /*
56540  * Field : addrlo
56541  *
56542  * MAC Address77 [31:0]
56543  *
56544  * This field contains the lower 32 bits of the 78th 6-byte MAC address. The
56545  * content of this field is undefined until loaded by the Application after the
56546  * initialization process.
56547  *
56548  * Field Access Macros:
56549  *
56550  */
56551 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field. */
56552 #define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_LSB 0
56553 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field. */
56554 #define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_MSB 31
56555 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field. */
56556 #define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_WIDTH 32
56557 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field value. */
56558 #define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_SET_MSK 0xffffffff
56559 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field value. */
56560 #define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_CLR_MSK 0x00000000
56561 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field. */
56562 #define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_RESET 0xffffffff
56563 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO field value from a register. */
56564 #define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
56565 /* Produces a ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field value suitable for setting the register. */
56566 #define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
56567 
56568 #ifndef __ASSEMBLY__
56569 /*
56570  * WARNING: The C register and register group struct declarations are provided for
56571  * convenience and illustrative purposes. They should, however, be used with
56572  * caution as the C language standard provides no guarantees about the alignment or
56573  * atomicity of device memory accesses. The recommended practice for writing
56574  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
56575  * alt_write_word() functions.
56576  *
56577  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR77_LOW.
56578  */
56579 struct ALT_EMAC_GMAC_MAC_ADDR77_LOW_s
56580 {
56581  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO */
56582 };
56583 
56584 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR77_LOW. */
56585 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR77_LOW_s ALT_EMAC_GMAC_MAC_ADDR77_LOW_t;
56586 #endif /* __ASSEMBLY__ */
56587 
56588 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_LOW register. */
56589 #define ALT_EMAC_GMAC_MAC_ADDR77_LOW_RESET 0xffffffff
56590 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR77_LOW register from the beginning of the component. */
56591 #define ALT_EMAC_GMAC_MAC_ADDR77_LOW_OFST 0x9ec
56592 /* The address of the ALT_EMAC_GMAC_MAC_ADDR77_LOW register. */
56593 #define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR77_LOW_OFST))
56594 
56595 /*
56596  * Register : gmacgrp_mac_address78_high
56597  *
56598  * <b> Register 636 (MAC Address78 High Register)</b>
56599  *
56600  * The MAC Address78 High register holds the upper 16 bits of the 79th 6-byte MAC
56601  * address of the station.
56602  *
56603  * If the MAC address registers are configured to be double-synchronized to the
56604  * (G)MII clock domains, then
56605  *
56606  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
56607  * or Bits[7:0] (in big-endian mode) of the MAC Address78 Low Register are written.
56608  * For proper synchronization updates, consecutive writes to this MAC Address78 Low
56609  * Register must be performed after at least four clock cycles in the destination
56610  * clock domain.
56611  *
56612  * Register Layout
56613  *
56614  * Bits | Access | Reset | Description
56615  * :--------|:-------|:-------|:-----------------------------------------
56616  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI
56617  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR78_HIGH_RSVD_30_16
56618  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE
56619  *
56620  */
56621 /*
56622  * Field : addrhi
56623  *
56624  * MAC Address78 [47:32]
56625  *
56626  * This field contains the upper 16 bits (47:32) of the 79th 6-byte MAC address.
56627  *
56628  * Field Access Macros:
56629  *
56630  */
56631 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field. */
56632 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_LSB 0
56633 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field. */
56634 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_MSB 15
56635 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field. */
56636 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_WIDTH 16
56637 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field value. */
56638 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_SET_MSK 0x0000ffff
56639 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field value. */
56640 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_CLR_MSK 0xffff0000
56641 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field. */
56642 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_RESET 0xffff
56643 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI field value from a register. */
56644 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
56645 /* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field value suitable for setting the register. */
56646 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
56647 
56648 /*
56649  * Field : reserved_30_16
56650  *
56651  * Reserved
56652  *
56653  * Field Access Macros:
56654  *
56655  */
56656 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_RSVD_30_16 register field. */
56657 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_RSVD_30_16_LSB 16
56658 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_RSVD_30_16 register field. */
56659 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_RSVD_30_16_MSB 30
56660 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_RSVD_30_16 register field. */
56661 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_RSVD_30_16_WIDTH 15
56662 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_RSVD_30_16 register field value. */
56663 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
56664 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_RSVD_30_16 register field value. */
56665 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
56666 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_RSVD_30_16 register field. */
56667 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_RSVD_30_16_RESET 0x0
56668 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_RSVD_30_16 field value from a register. */
56669 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
56670 /* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_RSVD_30_16 register field value suitable for setting the register. */
56671 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
56672 
56673 /*
56674  * Field : ae
56675  *
56676  * Address Enable
56677  *
56678  * When this bit is set, the address filter module uses the 79th MAC address for
56679  * perfect filtering.
56680  *
56681  * When this bit is reset, the address filter module ignores the address for
56682  * filtering.
56683  *
56684  * Field Enumeration Values:
56685  *
56686  * Enum | Value | Description
56687  * :----------------------------------------|:------|:------------
56688  * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_E_DISD | 0x0 |
56689  * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_E_END | 0x1 |
56690  *
56691  * Field Access Macros:
56692  *
56693  */
56694 /*
56695  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE
56696  *
56697  */
56698 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_E_DISD 0x0
56699 /*
56700  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE
56701  *
56702  */
56703 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_E_END 0x1
56704 
56705 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field. */
56706 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_LSB 31
56707 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field. */
56708 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_MSB 31
56709 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field. */
56710 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_WIDTH 1
56711 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field value. */
56712 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_SET_MSK 0x80000000
56713 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field value. */
56714 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_CLR_MSK 0x7fffffff
56715 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field. */
56716 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_RESET 0x0
56717 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE field value from a register. */
56718 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
56719 /* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field value suitable for setting the register. */
56720 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
56721 
56722 #ifndef __ASSEMBLY__
56723 /*
56724  * WARNING: The C register and register group struct declarations are provided for
56725  * convenience and illustrative purposes. They should, however, be used with
56726  * caution as the C language standard provides no guarantees about the alignment or
56727  * atomicity of device memory accesses. The recommended practice for writing
56728  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
56729  * alt_write_word() functions.
56730  *
56731  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR78_HIGH.
56732  */
56733 struct ALT_EMAC_GMAC_MAC_ADDR78_HIGH_s
56734 {
56735  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI */
56736  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR78_HIGH_RSVD_30_16 */
56737  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE */
56738 };
56739 
56740 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR78_HIGH. */
56741 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR78_HIGH_s ALT_EMAC_GMAC_MAC_ADDR78_HIGH_t;
56742 #endif /* __ASSEMBLY__ */
56743 
56744 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH register. */
56745 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_RESET 0x0000ffff
56746 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH register from the beginning of the component. */
56747 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_OFST 0x9f0
56748 /* The address of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH register. */
56749 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR78_HIGH_OFST))
56750 
56751 /*
56752  * Register : gmacgrp_mac_address78_low
56753  *
56754  * <b> Register 637 (MAC Address78 Low Register)</b>
56755  *
56756  * The MAC Address78 Low register holds the lower 32 bits of the 79th 6-byte MAC
56757  * address of the station.
56758  *
56759  * Register Layout
56760  *
56761  * Bits | Access | Reset | Description
56762  * :-------|:-------|:-----------|:------------------------------------
56763  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO
56764  *
56765  */
56766 /*
56767  * Field : addrlo
56768  *
56769  * MAC Address78 [31:0]
56770  *
56771  * This field contains the lower 32 bits of the 79th 6-byte MAC address. The
56772  * content of this field is undefined until loaded by the Application after the
56773  * initialization process.
56774  *
56775  * Field Access Macros:
56776  *
56777  */
56778 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field. */
56779 #define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_LSB 0
56780 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field. */
56781 #define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_MSB 31
56782 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field. */
56783 #define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_WIDTH 32
56784 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field value. */
56785 #define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_SET_MSK 0xffffffff
56786 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field value. */
56787 #define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_CLR_MSK 0x00000000
56788 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field. */
56789 #define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_RESET 0xffffffff
56790 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO field value from a register. */
56791 #define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
56792 /* Produces a ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field value suitable for setting the register. */
56793 #define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
56794 
56795 #ifndef __ASSEMBLY__
56796 /*
56797  * WARNING: The C register and register group struct declarations are provided for
56798  * convenience and illustrative purposes. They should, however, be used with
56799  * caution as the C language standard provides no guarantees about the alignment or
56800  * atomicity of device memory accesses. The recommended practice for writing
56801  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
56802  * alt_write_word() functions.
56803  *
56804  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR78_LOW.
56805  */
56806 struct ALT_EMAC_GMAC_MAC_ADDR78_LOW_s
56807 {
56808  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO */
56809 };
56810 
56811 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR78_LOW. */
56812 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR78_LOW_s ALT_EMAC_GMAC_MAC_ADDR78_LOW_t;
56813 #endif /* __ASSEMBLY__ */
56814 
56815 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_LOW register. */
56816 #define ALT_EMAC_GMAC_MAC_ADDR78_LOW_RESET 0xffffffff
56817 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR78_LOW register from the beginning of the component. */
56818 #define ALT_EMAC_GMAC_MAC_ADDR78_LOW_OFST 0x9f4
56819 /* The address of the ALT_EMAC_GMAC_MAC_ADDR78_LOW register. */
56820 #define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR78_LOW_OFST))
56821 
56822 /*
56823  * Register : gmacgrp_mac_address79_high
56824  *
56825  * <b> Register 638 (MAC Address79 High Register)</b>
56826  *
56827  * The MAC Address79 High register holds the upper 16 bits of the 80th 6-byte MAC
56828  * address of the station.
56829  *
56830  * If the MAC address registers are configured to be double-synchronized to the
56831  * (G)MII clock domains, then
56832  *
56833  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
56834  * or Bits[7:0] (in big-endian mode) of the MAC Address79 Low Register are written.
56835  * For proper synchronization updates, consecutive writes to this MAC Address79 Low
56836  * Register must be performed after at least four clock cycles in the destination
56837  * clock domain.
56838  *
56839  * Register Layout
56840  *
56841  * Bits | Access | Reset | Description
56842  * :--------|:-------|:-------|:-----------------------------------------
56843  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI
56844  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR79_HIGH_RSVD_30_16
56845  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE
56846  *
56847  */
56848 /*
56849  * Field : addrhi
56850  *
56851  * MAC Address79 [47:32]
56852  *
56853  * This field contains the upper 16 bits (47:32) of the 80th 6-byte MAC address.
56854  *
56855  * Field Access Macros:
56856  *
56857  */
56858 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field. */
56859 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_LSB 0
56860 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field. */
56861 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_MSB 15
56862 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field. */
56863 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_WIDTH 16
56864 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field value. */
56865 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_SET_MSK 0x0000ffff
56866 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field value. */
56867 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_CLR_MSK 0xffff0000
56868 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field. */
56869 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_RESET 0xffff
56870 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI field value from a register. */
56871 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
56872 /* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field value suitable for setting the register. */
56873 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
56874 
56875 /*
56876  * Field : reserved_30_16
56877  *
56878  * Reserved
56879  *
56880  * Field Access Macros:
56881  *
56882  */
56883 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_RSVD_30_16 register field. */
56884 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_RSVD_30_16_LSB 16
56885 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_RSVD_30_16 register field. */
56886 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_RSVD_30_16_MSB 30
56887 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_RSVD_30_16 register field. */
56888 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_RSVD_30_16_WIDTH 15
56889 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_RSVD_30_16 register field value. */
56890 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
56891 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_RSVD_30_16 register field value. */
56892 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
56893 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_RSVD_30_16 register field. */
56894 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_RSVD_30_16_RESET 0x0
56895 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_RSVD_30_16 field value from a register. */
56896 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
56897 /* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_RSVD_30_16 register field value suitable for setting the register. */
56898 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
56899 
56900 /*
56901  * Field : ae
56902  *
56903  * Address Enable
56904  *
56905  * When this bit is set, the address filter module uses the 80th MAC address for
56906  * perfect filtering.
56907  *
56908  * When this bit is reset, the address filter module ignores the address for
56909  * filtering.
56910  *
56911  * Field Enumeration Values:
56912  *
56913  * Enum | Value | Description
56914  * :----------------------------------------|:------|:------------
56915  * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_E_DISD | 0x0 |
56916  * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_E_END | 0x1 |
56917  *
56918  * Field Access Macros:
56919  *
56920  */
56921 /*
56922  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE
56923  *
56924  */
56925 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_E_DISD 0x0
56926 /*
56927  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE
56928  *
56929  */
56930 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_E_END 0x1
56931 
56932 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field. */
56933 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_LSB 31
56934 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field. */
56935 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_MSB 31
56936 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field. */
56937 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_WIDTH 1
56938 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field value. */
56939 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_SET_MSK 0x80000000
56940 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field value. */
56941 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_CLR_MSK 0x7fffffff
56942 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field. */
56943 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_RESET 0x0
56944 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE field value from a register. */
56945 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
56946 /* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field value suitable for setting the register. */
56947 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
56948 
56949 #ifndef __ASSEMBLY__
56950 /*
56951  * WARNING: The C register and register group struct declarations are provided for
56952  * convenience and illustrative purposes. They should, however, be used with
56953  * caution as the C language standard provides no guarantees about the alignment or
56954  * atomicity of device memory accesses. The recommended practice for writing
56955  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
56956  * alt_write_word() functions.
56957  *
56958  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR79_HIGH.
56959  */
56960 struct ALT_EMAC_GMAC_MAC_ADDR79_HIGH_s
56961 {
56962  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI */
56963  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR79_HIGH_RSVD_30_16 */
56964  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE */
56965 };
56966 
56967 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR79_HIGH. */
56968 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR79_HIGH_s ALT_EMAC_GMAC_MAC_ADDR79_HIGH_t;
56969 #endif /* __ASSEMBLY__ */
56970 
56971 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH register. */
56972 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_RESET 0x0000ffff
56973 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH register from the beginning of the component. */
56974 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_OFST 0x9f8
56975 /* The address of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH register. */
56976 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR79_HIGH_OFST))
56977 
56978 /*
56979  * Register : gmacgrp_mac_address79_low
56980  *
56981  * <b> Register 639 (MAC Address79 Low Register)</b>
56982  *
56983  * The MAC Address79 Low register holds the lower 32 bits of the 80th 6-byte MAC
56984  * address of the station.
56985  *
56986  * Register Layout
56987  *
56988  * Bits | Access | Reset | Description
56989  * :-------|:-------|:-----------|:------------------------------------
56990  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO
56991  *
56992  */
56993 /*
56994  * Field : addrlo
56995  *
56996  * MAC Address79 [31:0]
56997  *
56998  * This field contains the lower 32 bits of the 80th 6-byte MAC address. The
56999  * content of this field is undefined until loaded by the Application after the
57000  * initialization process.
57001  *
57002  * Field Access Macros:
57003  *
57004  */
57005 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field. */
57006 #define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_LSB 0
57007 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field. */
57008 #define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_MSB 31
57009 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field. */
57010 #define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_WIDTH 32
57011 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field value. */
57012 #define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_SET_MSK 0xffffffff
57013 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field value. */
57014 #define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_CLR_MSK 0x00000000
57015 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field. */
57016 #define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_RESET 0xffffffff
57017 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO field value from a register. */
57018 #define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
57019 /* Produces a ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field value suitable for setting the register. */
57020 #define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
57021 
57022 #ifndef __ASSEMBLY__
57023 /*
57024  * WARNING: The C register and register group struct declarations are provided for
57025  * convenience and illustrative purposes. They should, however, be used with
57026  * caution as the C language standard provides no guarantees about the alignment or
57027  * atomicity of device memory accesses. The recommended practice for writing
57028  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
57029  * alt_write_word() functions.
57030  *
57031  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR79_LOW.
57032  */
57033 struct ALT_EMAC_GMAC_MAC_ADDR79_LOW_s
57034 {
57035  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO */
57036 };
57037 
57038 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR79_LOW. */
57039 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR79_LOW_s ALT_EMAC_GMAC_MAC_ADDR79_LOW_t;
57040 #endif /* __ASSEMBLY__ */
57041 
57042 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_LOW register. */
57043 #define ALT_EMAC_GMAC_MAC_ADDR79_LOW_RESET 0xffffffff
57044 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR79_LOW register from the beginning of the component. */
57045 #define ALT_EMAC_GMAC_MAC_ADDR79_LOW_OFST 0x9fc
57046 /* The address of the ALT_EMAC_GMAC_MAC_ADDR79_LOW register. */
57047 #define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR79_LOW_OFST))
57048 
57049 /*
57050  * Register : gmacgrp_mac_address80_high
57051  *
57052  * <b> Register 640 (MAC Address80 High Register)</b>
57053  *
57054  * The MAC Address80 High register holds the upper 16 bits of the 81st 6-byte MAC
57055  * address of the station.
57056  *
57057  * If the MAC address registers are configured to be double-synchronized to the
57058  * (G)MII clock domains, then
57059  *
57060  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
57061  * or Bits[7:0] (in big-endian mode) of the MAC Address80 Low Register are written.
57062  * For proper synchronization updates, consecutive writes to this MAC Address80 Low
57063  * Register must be performed after at least four clock cycles in the destination
57064  * clock domain.
57065  *
57066  * Register Layout
57067  *
57068  * Bits | Access | Reset | Description
57069  * :--------|:-------|:-------|:-----------------------------------------
57070  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI
57071  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR80_HIGH_RSVD_30_16
57072  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE
57073  *
57074  */
57075 /*
57076  * Field : addrhi
57077  *
57078  * MAC Address80 [47:32]
57079  *
57080  * This field contains the upper 16 bits (47:32) of the 81st 6-byte MAC address.
57081  *
57082  * Field Access Macros:
57083  *
57084  */
57085 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field. */
57086 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_LSB 0
57087 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field. */
57088 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_MSB 15
57089 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field. */
57090 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_WIDTH 16
57091 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field value. */
57092 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_SET_MSK 0x0000ffff
57093 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field value. */
57094 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_CLR_MSK 0xffff0000
57095 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field. */
57096 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_RESET 0xffff
57097 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI field value from a register. */
57098 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
57099 /* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field value suitable for setting the register. */
57100 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
57101 
57102 /*
57103  * Field : reserved_30_16
57104  *
57105  * Reserved
57106  *
57107  * Field Access Macros:
57108  *
57109  */
57110 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_RSVD_30_16 register field. */
57111 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_RSVD_30_16_LSB 16
57112 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_RSVD_30_16 register field. */
57113 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_RSVD_30_16_MSB 30
57114 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_RSVD_30_16 register field. */
57115 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_RSVD_30_16_WIDTH 15
57116 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_RSVD_30_16 register field value. */
57117 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
57118 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_RSVD_30_16 register field value. */
57119 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
57120 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_RSVD_30_16 register field. */
57121 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_RSVD_30_16_RESET 0x0
57122 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_RSVD_30_16 field value from a register. */
57123 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
57124 /* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_RSVD_30_16 register field value suitable for setting the register. */
57125 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
57126 
57127 /*
57128  * Field : ae
57129  *
57130  * Address Enable
57131  *
57132  * When this bit is set, the address filter module uses the 81st MAC address for
57133  * perfect filtering.
57134  *
57135  * When this bit is reset, the address filter module ignores the address for
57136  * filtering.
57137  *
57138  * Field Enumeration Values:
57139  *
57140  * Enum | Value | Description
57141  * :----------------------------------------|:------|:------------
57142  * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_E_DISD | 0x0 |
57143  * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_E_END | 0x1 |
57144  *
57145  * Field Access Macros:
57146  *
57147  */
57148 /*
57149  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE
57150  *
57151  */
57152 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_E_DISD 0x0
57153 /*
57154  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE
57155  *
57156  */
57157 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_E_END 0x1
57158 
57159 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field. */
57160 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_LSB 31
57161 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field. */
57162 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_MSB 31
57163 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field. */
57164 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_WIDTH 1
57165 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field value. */
57166 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_SET_MSK 0x80000000
57167 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field value. */
57168 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_CLR_MSK 0x7fffffff
57169 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field. */
57170 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_RESET 0x0
57171 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE field value from a register. */
57172 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
57173 /* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field value suitable for setting the register. */
57174 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
57175 
57176 #ifndef __ASSEMBLY__
57177 /*
57178  * WARNING: The C register and register group struct declarations are provided for
57179  * convenience and illustrative purposes. They should, however, be used with
57180  * caution as the C language standard provides no guarantees about the alignment or
57181  * atomicity of device memory accesses. The recommended practice for writing
57182  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
57183  * alt_write_word() functions.
57184  *
57185  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR80_HIGH.
57186  */
57187 struct ALT_EMAC_GMAC_MAC_ADDR80_HIGH_s
57188 {
57189  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI */
57190  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR80_HIGH_RSVD_30_16 */
57191  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE */
57192 };
57193 
57194 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR80_HIGH. */
57195 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR80_HIGH_s ALT_EMAC_GMAC_MAC_ADDR80_HIGH_t;
57196 #endif /* __ASSEMBLY__ */
57197 
57198 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH register. */
57199 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_RESET 0x0000ffff
57200 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH register from the beginning of the component. */
57201 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_OFST 0xa00
57202 /* The address of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH register. */
57203 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR80_HIGH_OFST))
57204 
57205 /*
57206  * Register : gmacgrp_mac_address80_low
57207  *
57208  * <b> Register 641 (MAC Address80 Low Register) </b>
57209  *
57210  * The MAC Address80 Low register holds the lower 32 bits of the 81st 6-byte MAC
57211  * address of the station.
57212  *
57213  * Register Layout
57214  *
57215  * Bits | Access | Reset | Description
57216  * :-------|:-------|:-----------|:------------------------------------
57217  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO
57218  *
57219  */
57220 /*
57221  * Field : addrlo
57222  *
57223  * MAC Address80 [31:0]
57224  *
57225  * This field contains the lower 32 bits of the 81st 6-byte MAC address. The
57226  * content of this field is undefined until loaded by the Application after the
57227  * initialization process.
57228  *
57229  * Field Access Macros:
57230  *
57231  */
57232 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field. */
57233 #define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_LSB 0
57234 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field. */
57235 #define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_MSB 31
57236 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field. */
57237 #define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_WIDTH 32
57238 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field value. */
57239 #define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_SET_MSK 0xffffffff
57240 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field value. */
57241 #define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_CLR_MSK 0x00000000
57242 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field. */
57243 #define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_RESET 0xffffffff
57244 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO field value from a register. */
57245 #define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
57246 /* Produces a ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field value suitable for setting the register. */
57247 #define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
57248 
57249 #ifndef __ASSEMBLY__
57250 /*
57251  * WARNING: The C register and register group struct declarations are provided for
57252  * convenience and illustrative purposes. They should, however, be used with
57253  * caution as the C language standard provides no guarantees about the alignment or
57254  * atomicity of device memory accesses. The recommended practice for writing
57255  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
57256  * alt_write_word() functions.
57257  *
57258  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR80_LOW.
57259  */
57260 struct ALT_EMAC_GMAC_MAC_ADDR80_LOW_s
57261 {
57262  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO */
57263 };
57264 
57265 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR80_LOW. */
57266 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR80_LOW_s ALT_EMAC_GMAC_MAC_ADDR80_LOW_t;
57267 #endif /* __ASSEMBLY__ */
57268 
57269 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_LOW register. */
57270 #define ALT_EMAC_GMAC_MAC_ADDR80_LOW_RESET 0xffffffff
57271 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR80_LOW register from the beginning of the component. */
57272 #define ALT_EMAC_GMAC_MAC_ADDR80_LOW_OFST 0xa04
57273 /* The address of the ALT_EMAC_GMAC_MAC_ADDR80_LOW register. */
57274 #define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR80_LOW_OFST))
57275 
57276 /*
57277  * Register : gmacgrp_mac_address81_high
57278  *
57279  * <b> Register 642 (MAC Address81 High Register) </b>
57280  *
57281  * The MAC Address81 High register holds the upper 16 bits of the 82nd 6-byte MAC
57282  * address of the station.
57283  *
57284  * If the MAC address registers are configured to be double-synchronized to the
57285  * (G)MII clock domains, then
57286  *
57287  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
57288  * or Bits[7:0] (in big-endian mode) of the MAC Address81 Low Register are written.
57289  * For proper synchronization updates, consecutive writes to this MAC Address81 Low
57290  * Register must be performed after at least four clock cycles in the destination
57291  * clock domain.
57292  *
57293  * Register Layout
57294  *
57295  * Bits | Access | Reset | Description
57296  * :--------|:-------|:-------|:-----------------------------------------
57297  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI
57298  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR81_HIGH_RSVD_30_16
57299  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE
57300  *
57301  */
57302 /*
57303  * Field : addrhi
57304  *
57305  * MAC Address81 [47:32]
57306  *
57307  * This field contains the upper 16 bits (47:32) of the 82nd 6-byte MAC address.
57308  *
57309  * Field Access Macros:
57310  *
57311  */
57312 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field. */
57313 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_LSB 0
57314 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field. */
57315 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_MSB 15
57316 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field. */
57317 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_WIDTH 16
57318 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field value. */
57319 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_SET_MSK 0x0000ffff
57320 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field value. */
57321 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_CLR_MSK 0xffff0000
57322 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field. */
57323 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_RESET 0xffff
57324 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI field value from a register. */
57325 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
57326 /* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field value suitable for setting the register. */
57327 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
57328 
57329 /*
57330  * Field : reserved_30_16
57331  *
57332  * Reserved
57333  *
57334  * Field Access Macros:
57335  *
57336  */
57337 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_RSVD_30_16 register field. */
57338 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_RSVD_30_16_LSB 16
57339 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_RSVD_30_16 register field. */
57340 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_RSVD_30_16_MSB 30
57341 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_RSVD_30_16 register field. */
57342 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_RSVD_30_16_WIDTH 15
57343 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_RSVD_30_16 register field value. */
57344 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
57345 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_RSVD_30_16 register field value. */
57346 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
57347 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_RSVD_30_16 register field. */
57348 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_RSVD_30_16_RESET 0x0
57349 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_RSVD_30_16 field value from a register. */
57350 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
57351 /* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_RSVD_30_16 register field value suitable for setting the register. */
57352 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
57353 
57354 /*
57355  * Field : ae
57356  *
57357  * Address Enable
57358  *
57359  * When this bit is set, the address filter module uses the 82nd MAC address for
57360  * perfect filtering.
57361  *
57362  * When this bit is reset, the address filter module ignores the address for
57363  * filtering.
57364  *
57365  * Field Enumeration Values:
57366  *
57367  * Enum | Value | Description
57368  * :----------------------------------------|:------|:------------
57369  * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_E_DISD | 0x0 |
57370  * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_E_END | 0x1 |
57371  *
57372  * Field Access Macros:
57373  *
57374  */
57375 /*
57376  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE
57377  *
57378  */
57379 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_E_DISD 0x0
57380 /*
57381  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE
57382  *
57383  */
57384 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_E_END 0x1
57385 
57386 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field. */
57387 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_LSB 31
57388 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field. */
57389 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_MSB 31
57390 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field. */
57391 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_WIDTH 1
57392 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field value. */
57393 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_SET_MSK 0x80000000
57394 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field value. */
57395 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_CLR_MSK 0x7fffffff
57396 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field. */
57397 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_RESET 0x0
57398 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE field value from a register. */
57399 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
57400 /* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field value suitable for setting the register. */
57401 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
57402 
57403 #ifndef __ASSEMBLY__
57404 /*
57405  * WARNING: The C register and register group struct declarations are provided for
57406  * convenience and illustrative purposes. They should, however, be used with
57407  * caution as the C language standard provides no guarantees about the alignment or
57408  * atomicity of device memory accesses. The recommended practice for writing
57409  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
57410  * alt_write_word() functions.
57411  *
57412  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR81_HIGH.
57413  */
57414 struct ALT_EMAC_GMAC_MAC_ADDR81_HIGH_s
57415 {
57416  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI */
57417  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR81_HIGH_RSVD_30_16 */
57418  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE */
57419 };
57420 
57421 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR81_HIGH. */
57422 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR81_HIGH_s ALT_EMAC_GMAC_MAC_ADDR81_HIGH_t;
57423 #endif /* __ASSEMBLY__ */
57424 
57425 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH register. */
57426 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_RESET 0x0000ffff
57427 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH register from the beginning of the component. */
57428 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_OFST 0xa08
57429 /* The address of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH register. */
57430 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR81_HIGH_OFST))
57431 
57432 /*
57433  * Register : gmacgrp_mac_address81_low
57434  *
57435  * <b> Register 643 (MAC Address81 Low Register) </b>
57436  *
57437  * The MAC Address81 Low register holds the lower 32 bits of the 82nd 6-byte MAC
57438  * address of the station.
57439  *
57440  * Register Layout
57441  *
57442  * Bits | Access | Reset | Description
57443  * :-------|:-------|:-----------|:------------------------------------
57444  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO
57445  *
57446  */
57447 /*
57448  * Field : addrlo
57449  *
57450  * MAC Address81 [31:0]
57451  *
57452  * This field contains the lower 32 bits of the 82nd 6-byte MAC address. The
57453  * content of this field is undefined until loaded by the Application after the
57454  * initialization process.
57455  *
57456  * Field Access Macros:
57457  *
57458  */
57459 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field. */
57460 #define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_LSB 0
57461 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field. */
57462 #define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_MSB 31
57463 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field. */
57464 #define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_WIDTH 32
57465 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field value. */
57466 #define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_SET_MSK 0xffffffff
57467 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field value. */
57468 #define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_CLR_MSK 0x00000000
57469 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field. */
57470 #define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_RESET 0xffffffff
57471 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO field value from a register. */
57472 #define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
57473 /* Produces a ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field value suitable for setting the register. */
57474 #define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
57475 
57476 #ifndef __ASSEMBLY__
57477 /*
57478  * WARNING: The C register and register group struct declarations are provided for
57479  * convenience and illustrative purposes. They should, however, be used with
57480  * caution as the C language standard provides no guarantees about the alignment or
57481  * atomicity of device memory accesses. The recommended practice for writing
57482  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
57483  * alt_write_word() functions.
57484  *
57485  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR81_LOW.
57486  */
57487 struct ALT_EMAC_GMAC_MAC_ADDR81_LOW_s
57488 {
57489  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO */
57490 };
57491 
57492 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR81_LOW. */
57493 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR81_LOW_s ALT_EMAC_GMAC_MAC_ADDR81_LOW_t;
57494 #endif /* __ASSEMBLY__ */
57495 
57496 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_LOW register. */
57497 #define ALT_EMAC_GMAC_MAC_ADDR81_LOW_RESET 0xffffffff
57498 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR81_LOW register from the beginning of the component. */
57499 #define ALT_EMAC_GMAC_MAC_ADDR81_LOW_OFST 0xa0c
57500 /* The address of the ALT_EMAC_GMAC_MAC_ADDR81_LOW register. */
57501 #define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR81_LOW_OFST))
57502 
57503 /*
57504  * Register : gmacgrp_mac_address82_high
57505  *
57506  * <b> Register 644 (MAC Address82 High Register) </b>
57507  *
57508  * The MAC Address82 High register holds the upper 16 bits of the 83rd 6-byte MAC
57509  * address of the station.
57510  *
57511  * If the MAC address registers are configured to be double-synchronized to the
57512  * (G)MII clock domains, then
57513  *
57514  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
57515  * or Bits[7:0] (in big-endian mode) of the MAC Address82 Low Register are written.
57516  * For proper synchronization updates, consecutive writes to this MAC Address82 Low
57517  * Register must be performed after at least four clock cycles in the destination
57518  * clock domain.
57519  *
57520  * Register Layout
57521  *
57522  * Bits | Access | Reset | Description
57523  * :--------|:-------|:-------|:-----------------------------------------
57524  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI
57525  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR82_HIGH_RSVD_30_16
57526  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE
57527  *
57528  */
57529 /*
57530  * Field : addrhi
57531  *
57532  * MAC Address82 [47:32]
57533  *
57534  * This field contains the upper 16 bits (47:32) of the 83rd 6-byte MAC address.
57535  *
57536  * Field Access Macros:
57537  *
57538  */
57539 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field. */
57540 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_LSB 0
57541 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field. */
57542 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_MSB 15
57543 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field. */
57544 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_WIDTH 16
57545 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field value. */
57546 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_SET_MSK 0x0000ffff
57547 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field value. */
57548 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_CLR_MSK 0xffff0000
57549 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field. */
57550 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_RESET 0xffff
57551 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI field value from a register. */
57552 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
57553 /* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field value suitable for setting the register. */
57554 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
57555 
57556 /*
57557  * Field : reserved_30_16
57558  *
57559  * Reserved
57560  *
57561  * Field Access Macros:
57562  *
57563  */
57564 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_RSVD_30_16 register field. */
57565 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_RSVD_30_16_LSB 16
57566 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_RSVD_30_16 register field. */
57567 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_RSVD_30_16_MSB 30
57568 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_RSVD_30_16 register field. */
57569 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_RSVD_30_16_WIDTH 15
57570 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_RSVD_30_16 register field value. */
57571 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
57572 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_RSVD_30_16 register field value. */
57573 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
57574 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_RSVD_30_16 register field. */
57575 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_RSVD_30_16_RESET 0x0
57576 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_RSVD_30_16 field value from a register. */
57577 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
57578 /* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_RSVD_30_16 register field value suitable for setting the register. */
57579 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
57580 
57581 /*
57582  * Field : ae
57583  *
57584  * Address Enable
57585  *
57586  * When this bit is set, the address filter module uses the MAC address for perfect
57587  * filtering.
57588  *
57589  * When this bit is reset, the address filter module ignores the address for
57590  * filtering.
57591  *
57592  * Field Enumeration Values:
57593  *
57594  * Enum | Value | Description
57595  * :----------------------------------------|:------|:------------
57596  * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_E_DISD | 0x0 |
57597  * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_E_END | 0x1 |
57598  *
57599  * Field Access Macros:
57600  *
57601  */
57602 /*
57603  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE
57604  *
57605  */
57606 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_E_DISD 0x0
57607 /*
57608  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE
57609  *
57610  */
57611 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_E_END 0x1
57612 
57613 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field. */
57614 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_LSB 31
57615 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field. */
57616 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_MSB 31
57617 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field. */
57618 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_WIDTH 1
57619 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field value. */
57620 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_SET_MSK 0x80000000
57621 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field value. */
57622 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_CLR_MSK 0x7fffffff
57623 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field. */
57624 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_RESET 0x0
57625 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE field value from a register. */
57626 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
57627 /* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field value suitable for setting the register. */
57628 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
57629 
57630 #ifndef __ASSEMBLY__
57631 /*
57632  * WARNING: The C register and register group struct declarations are provided for
57633  * convenience and illustrative purposes. They should, however, be used with
57634  * caution as the C language standard provides no guarantees about the alignment or
57635  * atomicity of device memory accesses. The recommended practice for writing
57636  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
57637  * alt_write_word() functions.
57638  *
57639  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR82_HIGH.
57640  */
57641 struct ALT_EMAC_GMAC_MAC_ADDR82_HIGH_s
57642 {
57643  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI */
57644  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR82_HIGH_RSVD_30_16 */
57645  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE */
57646 };
57647 
57648 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR82_HIGH. */
57649 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR82_HIGH_s ALT_EMAC_GMAC_MAC_ADDR82_HIGH_t;
57650 #endif /* __ASSEMBLY__ */
57651 
57652 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH register. */
57653 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_RESET 0x0000ffff
57654 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH register from the beginning of the component. */
57655 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_OFST 0xa10
57656 /* The address of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH register. */
57657 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR82_HIGH_OFST))
57658 
57659 /*
57660  * Register : gmacgrp_mac_address82_low
57661  *
57662  * <b> Register 645 (MAC Address82 Low Register) </b>
57663  *
57664  * The MAC Address82 Low register holds the lower 32 bits of the 83rd 6-byte MAC
57665  * address of the station.
57666  *
57667  * Register Layout
57668  *
57669  * Bits | Access | Reset | Description
57670  * :-------|:-------|:-----------|:------------------------------------
57671  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO
57672  *
57673  */
57674 /*
57675  * Field : addrlo
57676  *
57677  * MAC Address82 [31:0]
57678  *
57679  * This field contains the lower 32 bits of the 83rd 6-byte MAC address. The
57680  * content of this field is undefined until loaded by the Application after the
57681  * initialization process.
57682  *
57683  * Field Access Macros:
57684  *
57685  */
57686 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field. */
57687 #define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_LSB 0
57688 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field. */
57689 #define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_MSB 31
57690 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field. */
57691 #define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_WIDTH 32
57692 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field value. */
57693 #define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_SET_MSK 0xffffffff
57694 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field value. */
57695 #define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_CLR_MSK 0x00000000
57696 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field. */
57697 #define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_RESET 0xffffffff
57698 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO field value from a register. */
57699 #define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
57700 /* Produces a ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field value suitable for setting the register. */
57701 #define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
57702 
57703 #ifndef __ASSEMBLY__
57704 /*
57705  * WARNING: The C register and register group struct declarations are provided for
57706  * convenience and illustrative purposes. They should, however, be used with
57707  * caution as the C language standard provides no guarantees about the alignment or
57708  * atomicity of device memory accesses. The recommended practice for writing
57709  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
57710  * alt_write_word() functions.
57711  *
57712  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR82_LOW.
57713  */
57714 struct ALT_EMAC_GMAC_MAC_ADDR82_LOW_s
57715 {
57716  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO */
57717 };
57718 
57719 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR82_LOW. */
57720 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR82_LOW_s ALT_EMAC_GMAC_MAC_ADDR82_LOW_t;
57721 #endif /* __ASSEMBLY__ */
57722 
57723 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_LOW register. */
57724 #define ALT_EMAC_GMAC_MAC_ADDR82_LOW_RESET 0xffffffff
57725 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR82_LOW register from the beginning of the component. */
57726 #define ALT_EMAC_GMAC_MAC_ADDR82_LOW_OFST 0xa14
57727 /* The address of the ALT_EMAC_GMAC_MAC_ADDR82_LOW register. */
57728 #define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR82_LOW_OFST))
57729 
57730 /*
57731  * Register : gmacgrp_mac_address83_high
57732  *
57733  * <b> Register 646 (MAC Address83 High Register) </b>
57734  *
57735  * The MAC Address83 High register holds the upper 16 bits of the 84th 6-byte MAC
57736  * address of the station.
57737  *
57738  * If the MAC address registers are configured to be double-synchronized to the
57739  * (G)MII clock domains, then
57740  *
57741  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
57742  * or Bits[7:0] (in big-endian mode) of the MAC Address83 Low Register are written.
57743  * For proper synchronization updates, consecutive writes to this MAC Address83 Low
57744  * Register must be performed after at least four clock cycles in the destination
57745  * clock domain.
57746  *
57747  * Register Layout
57748  *
57749  * Bits | Access | Reset | Description
57750  * :--------|:-------|:-------|:-----------------------------------------
57751  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI
57752  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR83_HIGH_RSVD_30_16
57753  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE
57754  *
57755  */
57756 /*
57757  * Field : addrhi
57758  *
57759  * MAC Address83 [47:32]
57760  *
57761  * This field contains the upper 16 bits (47:32) of the 84th 6-byte MAC address.
57762  *
57763  * Field Access Macros:
57764  *
57765  */
57766 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field. */
57767 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_LSB 0
57768 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field. */
57769 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_MSB 15
57770 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field. */
57771 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_WIDTH 16
57772 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field value. */
57773 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_SET_MSK 0x0000ffff
57774 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field value. */
57775 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_CLR_MSK 0xffff0000
57776 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field. */
57777 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_RESET 0xffff
57778 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI field value from a register. */
57779 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
57780 /* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field value suitable for setting the register. */
57781 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
57782 
57783 /*
57784  * Field : reserved_30_16
57785  *
57786  * Reserved
57787  *
57788  * Field Access Macros:
57789  *
57790  */
57791 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_RSVD_30_16 register field. */
57792 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_RSVD_30_16_LSB 16
57793 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_RSVD_30_16 register field. */
57794 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_RSVD_30_16_MSB 30
57795 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_RSVD_30_16 register field. */
57796 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_RSVD_30_16_WIDTH 15
57797 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_RSVD_30_16 register field value. */
57798 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
57799 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_RSVD_30_16 register field value. */
57800 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
57801 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_RSVD_30_16 register field. */
57802 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_RSVD_30_16_RESET 0x0
57803 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_RSVD_30_16 field value from a register. */
57804 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
57805 /* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_RSVD_30_16 register field value suitable for setting the register. */
57806 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
57807 
57808 /*
57809  * Field : ae
57810  *
57811  * Address Enable
57812  *
57813  * When this bit is set, the address filter module uses the 84th MAC address for
57814  * perfect filtering.
57815  *
57816  * When this bit is reset, the address filter module ignores the address for
57817  * filtering.
57818  *
57819  * Field Enumeration Values:
57820  *
57821  * Enum | Value | Description
57822  * :----------------------------------------|:------|:------------
57823  * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_E_DISD | 0x0 |
57824  * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_E_END | 0x1 |
57825  *
57826  * Field Access Macros:
57827  *
57828  */
57829 /*
57830  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE
57831  *
57832  */
57833 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_E_DISD 0x0
57834 /*
57835  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE
57836  *
57837  */
57838 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_E_END 0x1
57839 
57840 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field. */
57841 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_LSB 31
57842 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field. */
57843 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_MSB 31
57844 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field. */
57845 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_WIDTH 1
57846 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field value. */
57847 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_SET_MSK 0x80000000
57848 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field value. */
57849 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_CLR_MSK 0x7fffffff
57850 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field. */
57851 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_RESET 0x0
57852 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE field value from a register. */
57853 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
57854 /* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field value suitable for setting the register. */
57855 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
57856 
57857 #ifndef __ASSEMBLY__
57858 /*
57859  * WARNING: The C register and register group struct declarations are provided for
57860  * convenience and illustrative purposes. They should, however, be used with
57861  * caution as the C language standard provides no guarantees about the alignment or
57862  * atomicity of device memory accesses. The recommended practice for writing
57863  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
57864  * alt_write_word() functions.
57865  *
57866  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR83_HIGH.
57867  */
57868 struct ALT_EMAC_GMAC_MAC_ADDR83_HIGH_s
57869 {
57870  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI */
57871  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR83_HIGH_RSVD_30_16 */
57872  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE */
57873 };
57874 
57875 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR83_HIGH. */
57876 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR83_HIGH_s ALT_EMAC_GMAC_MAC_ADDR83_HIGH_t;
57877 #endif /* __ASSEMBLY__ */
57878 
57879 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH register. */
57880 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_RESET 0x0000ffff
57881 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH register from the beginning of the component. */
57882 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_OFST 0xa18
57883 /* The address of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH register. */
57884 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR83_HIGH_OFST))
57885 
57886 /*
57887  * Register : gmacgrp_mac_address83_low
57888  *
57889  * <b> Register 647 (MAC Address83 Low Register)</b>
57890  *
57891  * The MAC Address83 Low register holds the lower 32 bits of the 84th 6-byte MAC
57892  * address of the station.
57893  *
57894  * Register Layout
57895  *
57896  * Bits | Access | Reset | Description
57897  * :-------|:-------|:-----------|:------------------------------------
57898  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO
57899  *
57900  */
57901 /*
57902  * Field : addrlo
57903  *
57904  * MAC Address83 [31:0]
57905  *
57906  * This field contains the lower 32 bits of the 84th 6-byte MAC address. The
57907  * content of this field is undefined until loaded by the Application after the
57908  * initialization process.
57909  *
57910  * Field Access Macros:
57911  *
57912  */
57913 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field. */
57914 #define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_LSB 0
57915 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field. */
57916 #define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_MSB 31
57917 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field. */
57918 #define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_WIDTH 32
57919 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field value. */
57920 #define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_SET_MSK 0xffffffff
57921 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field value. */
57922 #define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_CLR_MSK 0x00000000
57923 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field. */
57924 #define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_RESET 0xffffffff
57925 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO field value from a register. */
57926 #define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
57927 /* Produces a ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field value suitable for setting the register. */
57928 #define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
57929 
57930 #ifndef __ASSEMBLY__
57931 /*
57932  * WARNING: The C register and register group struct declarations are provided for
57933  * convenience and illustrative purposes. They should, however, be used with
57934  * caution as the C language standard provides no guarantees about the alignment or
57935  * atomicity of device memory accesses. The recommended practice for writing
57936  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
57937  * alt_write_word() functions.
57938  *
57939  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR83_LOW.
57940  */
57941 struct ALT_EMAC_GMAC_MAC_ADDR83_LOW_s
57942 {
57943  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO */
57944 };
57945 
57946 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR83_LOW. */
57947 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR83_LOW_s ALT_EMAC_GMAC_MAC_ADDR83_LOW_t;
57948 #endif /* __ASSEMBLY__ */
57949 
57950 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_LOW register. */
57951 #define ALT_EMAC_GMAC_MAC_ADDR83_LOW_RESET 0xffffffff
57952 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR83_LOW register from the beginning of the component. */
57953 #define ALT_EMAC_GMAC_MAC_ADDR83_LOW_OFST 0xa1c
57954 /* The address of the ALT_EMAC_GMAC_MAC_ADDR83_LOW register. */
57955 #define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR83_LOW_OFST))
57956 
57957 /*
57958  * Register : gmacgrp_mac_address84_high
57959  *
57960  * <b> Register 648 (MAC Address84 High Register)</b>
57961  *
57962  * The MAC Address84 High register holds the upper 16 bits of the 85th 6-byte MAC
57963  * address of the station.
57964  *
57965  * If the MAC address registers are configured to be double-synchronized to the
57966  * (G)MII clock domains, then
57967  *
57968  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
57969  * or Bits[7:0] (in big-endian mode) of the MAC Address84 Low Register are written.
57970  * For proper synchronization updates, consecutive writes to this MAC Address84 Low
57971  * Register must be performed after at least four clock cycles in the destination
57972  * clock domain.
57973  *
57974  * Register Layout
57975  *
57976  * Bits | Access | Reset | Description
57977  * :--------|:-------|:-------|:-----------------------------------------
57978  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI
57979  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR84_HIGH_RSVD_30_16
57980  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE
57981  *
57982  */
57983 /*
57984  * Field : addrhi
57985  *
57986  * MAC Address84 [47:32]
57987  *
57988  * This field contains the upper 16 bits (47:32) of the 85th 6-byte MAC address.
57989  *
57990  * Field Access Macros:
57991  *
57992  */
57993 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field. */
57994 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_LSB 0
57995 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field. */
57996 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_MSB 15
57997 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field. */
57998 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_WIDTH 16
57999 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field value. */
58000 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_SET_MSK 0x0000ffff
58001 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field value. */
58002 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_CLR_MSK 0xffff0000
58003 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field. */
58004 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_RESET 0xffff
58005 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI field value from a register. */
58006 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
58007 /* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field value suitable for setting the register. */
58008 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
58009 
58010 /*
58011  * Field : reserved_30_16
58012  *
58013  * Reserved
58014  *
58015  * Field Access Macros:
58016  *
58017  */
58018 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_RSVD_30_16 register field. */
58019 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_RSVD_30_16_LSB 16
58020 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_RSVD_30_16 register field. */
58021 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_RSVD_30_16_MSB 30
58022 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_RSVD_30_16 register field. */
58023 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_RSVD_30_16_WIDTH 15
58024 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_RSVD_30_16 register field value. */
58025 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
58026 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_RSVD_30_16 register field value. */
58027 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
58028 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_RSVD_30_16 register field. */
58029 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_RSVD_30_16_RESET 0x0
58030 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_RSVD_30_16 field value from a register. */
58031 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
58032 /* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_RSVD_30_16 register field value suitable for setting the register. */
58033 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
58034 
58035 /*
58036  * Field : ae
58037  *
58038  * Address Enable
58039  *
58040  * When this bit is set, the address filter module uses the 85th MAC address for
58041  * perfect filtering.
58042  *
58043  * When this bit is reset, the address filter module ignores the address for
58044  * filtering.
58045  *
58046  * Field Enumeration Values:
58047  *
58048  * Enum | Value | Description
58049  * :----------------------------------------|:------|:------------
58050  * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_E_DISD | 0x0 |
58051  * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_E_END | 0x1 |
58052  *
58053  * Field Access Macros:
58054  *
58055  */
58056 /*
58057  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE
58058  *
58059  */
58060 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_E_DISD 0x0
58061 /*
58062  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE
58063  *
58064  */
58065 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_E_END 0x1
58066 
58067 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field. */
58068 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_LSB 31
58069 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field. */
58070 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_MSB 31
58071 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field. */
58072 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_WIDTH 1
58073 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field value. */
58074 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_SET_MSK 0x80000000
58075 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field value. */
58076 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_CLR_MSK 0x7fffffff
58077 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field. */
58078 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_RESET 0x0
58079 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE field value from a register. */
58080 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
58081 /* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field value suitable for setting the register. */
58082 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
58083 
58084 #ifndef __ASSEMBLY__
58085 /*
58086  * WARNING: The C register and register group struct declarations are provided for
58087  * convenience and illustrative purposes. They should, however, be used with
58088  * caution as the C language standard provides no guarantees about the alignment or
58089  * atomicity of device memory accesses. The recommended practice for writing
58090  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
58091  * alt_write_word() functions.
58092  *
58093  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR84_HIGH.
58094  */
58095 struct ALT_EMAC_GMAC_MAC_ADDR84_HIGH_s
58096 {
58097  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI */
58098  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR84_HIGH_RSVD_30_16 */
58099  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE */
58100 };
58101 
58102 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR84_HIGH. */
58103 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR84_HIGH_s ALT_EMAC_GMAC_MAC_ADDR84_HIGH_t;
58104 #endif /* __ASSEMBLY__ */
58105 
58106 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH register. */
58107 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_RESET 0x0000ffff
58108 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH register from the beginning of the component. */
58109 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_OFST 0xa20
58110 /* The address of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH register. */
58111 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR84_HIGH_OFST))
58112 
58113 /*
58114  * Register : gmacgrp_mac_address84_low
58115  *
58116  * <b> Register 649 (MAC Address84 Low Register)</b>
58117  *
58118  * The MAC Address84 Low register holds the lower 32 bits of the 85th 6-byte MAC
58119  * address of the station.
58120  *
58121  * Register Layout
58122  *
58123  * Bits | Access | Reset | Description
58124  * :-------|:-------|:-----------|:------------------------------------
58125  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO
58126  *
58127  */
58128 /*
58129  * Field : addrlo
58130  *
58131  * MAC Address84 [31:0]
58132  *
58133  * This field contains the lower 32 bits of the 85th 6-byte MAC address. The
58134  * content of this field is undefined until loaded by the Application after the
58135  * initialization process.
58136  *
58137  * Field Access Macros:
58138  *
58139  */
58140 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field. */
58141 #define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_LSB 0
58142 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field. */
58143 #define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_MSB 31
58144 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field. */
58145 #define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_WIDTH 32
58146 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field value. */
58147 #define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_SET_MSK 0xffffffff
58148 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field value. */
58149 #define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_CLR_MSK 0x00000000
58150 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field. */
58151 #define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_RESET 0xffffffff
58152 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO field value from a register. */
58153 #define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
58154 /* Produces a ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field value suitable for setting the register. */
58155 #define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
58156 
58157 #ifndef __ASSEMBLY__
58158 /*
58159  * WARNING: The C register and register group struct declarations are provided for
58160  * convenience and illustrative purposes. They should, however, be used with
58161  * caution as the C language standard provides no guarantees about the alignment or
58162  * atomicity of device memory accesses. The recommended practice for writing
58163  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
58164  * alt_write_word() functions.
58165  *
58166  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR84_LOW.
58167  */
58168 struct ALT_EMAC_GMAC_MAC_ADDR84_LOW_s
58169 {
58170  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO */
58171 };
58172 
58173 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR84_LOW. */
58174 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR84_LOW_s ALT_EMAC_GMAC_MAC_ADDR84_LOW_t;
58175 #endif /* __ASSEMBLY__ */
58176 
58177 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_LOW register. */
58178 #define ALT_EMAC_GMAC_MAC_ADDR84_LOW_RESET 0xffffffff
58179 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR84_LOW register from the beginning of the component. */
58180 #define ALT_EMAC_GMAC_MAC_ADDR84_LOW_OFST 0xa24
58181 /* The address of the ALT_EMAC_GMAC_MAC_ADDR84_LOW register. */
58182 #define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR84_LOW_OFST))
58183 
58184 /*
58185  * Register : gmacgrp_mac_address85_high
58186  *
58187  * <b> Register 650 (MAC Address85 High Register)</b>
58188  *
58189  * The MAC Address85 High register holds the upper 16 bits of the 86th 6-byte MAC
58190  * address of the station.
58191  *
58192  * If the MAC address registers are configured to be double-synchronized to the
58193  * (G)MII clock domains, then
58194  *
58195  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
58196  * or Bits[7:0] (in big-endian mode) of the MAC Address85 Low Register are written.
58197  * For proper synchronization updates, consecutive writes to this MAC Address85 Low
58198  * Register must be performed after at least four clock cycles in the destination
58199  * clock domain.
58200  *
58201  * Register Layout
58202  *
58203  * Bits | Access | Reset | Description
58204  * :--------|:-------|:-------|:-----------------------------------------
58205  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI
58206  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR85_HIGH_RSVD_30_16
58207  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE
58208  *
58209  */
58210 /*
58211  * Field : addrhi
58212  *
58213  * MAC Address85 [47:32]
58214  *
58215  * This field contains the upper 16 bits (47:32) of the 86th 6-byte MAC address.
58216  *
58217  * Field Access Macros:
58218  *
58219  */
58220 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field. */
58221 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_LSB 0
58222 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field. */
58223 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_MSB 15
58224 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field. */
58225 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_WIDTH 16
58226 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field value. */
58227 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_SET_MSK 0x0000ffff
58228 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field value. */
58229 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_CLR_MSK 0xffff0000
58230 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field. */
58231 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_RESET 0xffff
58232 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI field value from a register. */
58233 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
58234 /* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field value suitable for setting the register. */
58235 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
58236 
58237 /*
58238  * Field : reserved_30_16
58239  *
58240  * Reserved
58241  *
58242  * Field Access Macros:
58243  *
58244  */
58245 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_RSVD_30_16 register field. */
58246 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_RSVD_30_16_LSB 16
58247 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_RSVD_30_16 register field. */
58248 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_RSVD_30_16_MSB 30
58249 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_RSVD_30_16 register field. */
58250 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_RSVD_30_16_WIDTH 15
58251 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_RSVD_30_16 register field value. */
58252 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
58253 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_RSVD_30_16 register field value. */
58254 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
58255 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_RSVD_30_16 register field. */
58256 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_RSVD_30_16_RESET 0x0
58257 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_RSVD_30_16 field value from a register. */
58258 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
58259 /* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_RSVD_30_16 register field value suitable for setting the register. */
58260 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
58261 
58262 /*
58263  * Field : ae
58264  *
58265  * Address Enable
58266  *
58267  * When this bit is set, the address filter module uses the 86th MAC address for
58268  * perfect filtering.
58269  *
58270  * When this bit is reset, the address filter module ignores the address for
58271  * filtering.
58272  *
58273  * Field Enumeration Values:
58274  *
58275  * Enum | Value | Description
58276  * :----------------------------------------|:------|:------------
58277  * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_E_DISD | 0x0 |
58278  * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_E_END | 0x1 |
58279  *
58280  * Field Access Macros:
58281  *
58282  */
58283 /*
58284  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE
58285  *
58286  */
58287 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_E_DISD 0x0
58288 /*
58289  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE
58290  *
58291  */
58292 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_E_END 0x1
58293 
58294 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field. */
58295 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_LSB 31
58296 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field. */
58297 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_MSB 31
58298 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field. */
58299 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_WIDTH 1
58300 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field value. */
58301 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_SET_MSK 0x80000000
58302 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field value. */
58303 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_CLR_MSK 0x7fffffff
58304 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field. */
58305 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_RESET 0x0
58306 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE field value from a register. */
58307 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
58308 /* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field value suitable for setting the register. */
58309 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
58310 
58311 #ifndef __ASSEMBLY__
58312 /*
58313  * WARNING: The C register and register group struct declarations are provided for
58314  * convenience and illustrative purposes. They should, however, be used with
58315  * caution as the C language standard provides no guarantees about the alignment or
58316  * atomicity of device memory accesses. The recommended practice for writing
58317  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
58318  * alt_write_word() functions.
58319  *
58320  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR85_HIGH.
58321  */
58322 struct ALT_EMAC_GMAC_MAC_ADDR85_HIGH_s
58323 {
58324  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI */
58325  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR85_HIGH_RSVD_30_16 */
58326  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE */
58327 };
58328 
58329 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR85_HIGH. */
58330 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR85_HIGH_s ALT_EMAC_GMAC_MAC_ADDR85_HIGH_t;
58331 #endif /* __ASSEMBLY__ */
58332 
58333 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH register. */
58334 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_RESET 0x0000ffff
58335 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH register from the beginning of the component. */
58336 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_OFST 0xa28
58337 /* The address of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH register. */
58338 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR85_HIGH_OFST))
58339 
58340 /*
58341  * Register : gmacgrp_mac_address85_low
58342  *
58343  * <b> Register 651 (MAC Address85 Low Register)</b>
58344  *
58345  * The MAC Address85 Low register holds the lower 32 bits of the 86th 6-byte MAC
58346  * address of the station.
58347  *
58348  * Register Layout
58349  *
58350  * Bits | Access | Reset | Description
58351  * :-------|:-------|:-----------|:------------------------------------
58352  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO
58353  *
58354  */
58355 /*
58356  * Field : addrlo
58357  *
58358  * MAC Address85 [31:0]
58359  *
58360  * This field contains the lower 32 bits of the 86th 6-byte MAC address. The
58361  * content of this field is undefined until loaded by the Application after the
58362  * initialization process.
58363  *
58364  * Field Access Macros:
58365  *
58366  */
58367 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field. */
58368 #define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_LSB 0
58369 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field. */
58370 #define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_MSB 31
58371 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field. */
58372 #define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_WIDTH 32
58373 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field value. */
58374 #define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_SET_MSK 0xffffffff
58375 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field value. */
58376 #define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_CLR_MSK 0x00000000
58377 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field. */
58378 #define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_RESET 0xffffffff
58379 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO field value from a register. */
58380 #define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
58381 /* Produces a ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field value suitable for setting the register. */
58382 #define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
58383 
58384 #ifndef __ASSEMBLY__
58385 /*
58386  * WARNING: The C register and register group struct declarations are provided for
58387  * convenience and illustrative purposes. They should, however, be used with
58388  * caution as the C language standard provides no guarantees about the alignment or
58389  * atomicity of device memory accesses. The recommended practice for writing
58390  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
58391  * alt_write_word() functions.
58392  *
58393  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR85_LOW.
58394  */
58395 struct ALT_EMAC_GMAC_MAC_ADDR85_LOW_s
58396 {
58397  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO */
58398 };
58399 
58400 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR85_LOW. */
58401 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR85_LOW_s ALT_EMAC_GMAC_MAC_ADDR85_LOW_t;
58402 #endif /* __ASSEMBLY__ */
58403 
58404 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_LOW register. */
58405 #define ALT_EMAC_GMAC_MAC_ADDR85_LOW_RESET 0xffffffff
58406 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR85_LOW register from the beginning of the component. */
58407 #define ALT_EMAC_GMAC_MAC_ADDR85_LOW_OFST 0xa2c
58408 /* The address of the ALT_EMAC_GMAC_MAC_ADDR85_LOW register. */
58409 #define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR85_LOW_OFST))
58410 
58411 /*
58412  * Register : gmacgrp_mac_address86_high
58413  *
58414  * <b> Register 652 (MAC Address86 High Register)</b>
58415  *
58416  * The MAC Address86 High register holds the upper 16 bits of the 87th 6-byte MAC
58417  * address of the station.
58418  *
58419  * If the MAC address registers are configured to be double-synchronized to the
58420  * (G)MII clock domains, then
58421  *
58422  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
58423  * or Bits[7:0] (in big-endian mode) of the MAC Address86 Low Register are written.
58424  * For proper synchronization updates, consecutive writes to this MAC Address86 Low
58425  * Register must be performed after at least four clock cycles in the destination
58426  * clock domain.
58427  *
58428  * Register Layout
58429  *
58430  * Bits | Access | Reset | Description
58431  * :--------|:-------|:-------|:-----------------------------------------
58432  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI
58433  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR86_HIGH_RSVD_30_16
58434  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE
58435  *
58436  */
58437 /*
58438  * Field : addrhi
58439  *
58440  * MAC Address86 [47:32]
58441  *
58442  * This field contains the upper 16 bits (47:32) of the 87th 6-byte MAC address.
58443  *
58444  * Field Access Macros:
58445  *
58446  */
58447 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field. */
58448 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_LSB 0
58449 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field. */
58450 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_MSB 15
58451 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field. */
58452 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_WIDTH 16
58453 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field value. */
58454 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_SET_MSK 0x0000ffff
58455 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field value. */
58456 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_CLR_MSK 0xffff0000
58457 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field. */
58458 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_RESET 0xffff
58459 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI field value from a register. */
58460 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
58461 /* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field value suitable for setting the register. */
58462 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
58463 
58464 /*
58465  * Field : reserved_30_16
58466  *
58467  * Reserved
58468  *
58469  * Field Access Macros:
58470  *
58471  */
58472 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_RSVD_30_16 register field. */
58473 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_RSVD_30_16_LSB 16
58474 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_RSVD_30_16 register field. */
58475 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_RSVD_30_16_MSB 30
58476 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_RSVD_30_16 register field. */
58477 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_RSVD_30_16_WIDTH 15
58478 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_RSVD_30_16 register field value. */
58479 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
58480 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_RSVD_30_16 register field value. */
58481 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
58482 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_RSVD_30_16 register field. */
58483 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_RSVD_30_16_RESET 0x0
58484 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_RSVD_30_16 field value from a register. */
58485 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
58486 /* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_RSVD_30_16 register field value suitable for setting the register. */
58487 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
58488 
58489 /*
58490  * Field : ae
58491  *
58492  * Address Enable
58493  *
58494  * When this bit is set, the address filter module uses the 87th MAC address for
58495  * perfect filtering.
58496  *
58497  * When this bit is reset, the address filter module ignores the address for
58498  * filtering.
58499  *
58500  * Field Enumeration Values:
58501  *
58502  * Enum | Value | Description
58503  * :----------------------------------------|:------|:------------
58504  * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_E_DISD | 0x0 |
58505  * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_E_END | 0x1 |
58506  *
58507  * Field Access Macros:
58508  *
58509  */
58510 /*
58511  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE
58512  *
58513  */
58514 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_E_DISD 0x0
58515 /*
58516  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE
58517  *
58518  */
58519 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_E_END 0x1
58520 
58521 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field. */
58522 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_LSB 31
58523 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field. */
58524 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_MSB 31
58525 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field. */
58526 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_WIDTH 1
58527 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field value. */
58528 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_SET_MSK 0x80000000
58529 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field value. */
58530 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_CLR_MSK 0x7fffffff
58531 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field. */
58532 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_RESET 0x0
58533 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE field value from a register. */
58534 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
58535 /* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field value suitable for setting the register. */
58536 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
58537 
58538 #ifndef __ASSEMBLY__
58539 /*
58540  * WARNING: The C register and register group struct declarations are provided for
58541  * convenience and illustrative purposes. They should, however, be used with
58542  * caution as the C language standard provides no guarantees about the alignment or
58543  * atomicity of device memory accesses. The recommended practice for writing
58544  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
58545  * alt_write_word() functions.
58546  *
58547  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR86_HIGH.
58548  */
58549 struct ALT_EMAC_GMAC_MAC_ADDR86_HIGH_s
58550 {
58551  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI */
58552  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR86_HIGH_RSVD_30_16 */
58553  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE */
58554 };
58555 
58556 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR86_HIGH. */
58557 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR86_HIGH_s ALT_EMAC_GMAC_MAC_ADDR86_HIGH_t;
58558 #endif /* __ASSEMBLY__ */
58559 
58560 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH register. */
58561 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_RESET 0x0000ffff
58562 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH register from the beginning of the component. */
58563 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_OFST 0xa30
58564 /* The address of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH register. */
58565 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR86_HIGH_OFST))
58566 
58567 /*
58568  * Register : gmacgrp_mac_address86_low
58569  *
58570  * <b> Register 653 (MAC Address86 Low Register)</b>
58571  *
58572  * The MAC Address86 Low register holds the lower 32 bits of the 87th 6-byte MAC
58573  * address of the station.
58574  *
58575  * Register Layout
58576  *
58577  * Bits | Access | Reset | Description
58578  * :-------|:-------|:-----------|:------------------------------------
58579  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO
58580  *
58581  */
58582 /*
58583  * Field : addrlo
58584  *
58585  * MAC Address86 [31:0]
58586  *
58587  * This field contains the lower 32 bits of the 87th 6-byte MAC address. The
58588  * content of this field is undefined until loaded by the Application after the
58589  * initialization process.
58590  *
58591  * Field Access Macros:
58592  *
58593  */
58594 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field. */
58595 #define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_LSB 0
58596 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field. */
58597 #define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_MSB 31
58598 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field. */
58599 #define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_WIDTH 32
58600 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field value. */
58601 #define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_SET_MSK 0xffffffff
58602 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field value. */
58603 #define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_CLR_MSK 0x00000000
58604 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field. */
58605 #define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_RESET 0xffffffff
58606 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO field value from a register. */
58607 #define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
58608 /* Produces a ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field value suitable for setting the register. */
58609 #define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
58610 
58611 #ifndef __ASSEMBLY__
58612 /*
58613  * WARNING: The C register and register group struct declarations are provided for
58614  * convenience and illustrative purposes. They should, however, be used with
58615  * caution as the C language standard provides no guarantees about the alignment or
58616  * atomicity of device memory accesses. The recommended practice for writing
58617  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
58618  * alt_write_word() functions.
58619  *
58620  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR86_LOW.
58621  */
58622 struct ALT_EMAC_GMAC_MAC_ADDR86_LOW_s
58623 {
58624  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO */
58625 };
58626 
58627 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR86_LOW. */
58628 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR86_LOW_s ALT_EMAC_GMAC_MAC_ADDR86_LOW_t;
58629 #endif /* __ASSEMBLY__ */
58630 
58631 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_LOW register. */
58632 #define ALT_EMAC_GMAC_MAC_ADDR86_LOW_RESET 0xffffffff
58633 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR86_LOW register from the beginning of the component. */
58634 #define ALT_EMAC_GMAC_MAC_ADDR86_LOW_OFST 0xa34
58635 /* The address of the ALT_EMAC_GMAC_MAC_ADDR86_LOW register. */
58636 #define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR86_LOW_OFST))
58637 
58638 /*
58639  * Register : gmacgrp_mac_address87_high
58640  *
58641  * <b> Register 654 (MAC Address87 High Register)</b>
58642  *
58643  * The MAC Address87 High register holds the upper 16 bits of the 88th 6-byte MAC
58644  * address of the station.
58645  *
58646  * If the MAC address registers are configured to be double-synchronized to the
58647  * (G)MII clock domains, then
58648  *
58649  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
58650  * or Bits[7:0] (in big-endian mode) of the MAC Address87 Low Register are written.
58651  * For proper synchronization updates, consecutive writes to this MAC Address87 Low
58652  * Register must be performed after at least four clock cycles in the destination
58653  * clock domain.
58654  *
58655  * Register Layout
58656  *
58657  * Bits | Access | Reset | Description
58658  * :--------|:-------|:-------|:-----------------------------------------
58659  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI
58660  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR87_HIGH_RSVD_30_16
58661  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE
58662  *
58663  */
58664 /*
58665  * Field : addrhi
58666  *
58667  * MAC Address87 [47:32]
58668  *
58669  * This field contains the upper 16 bits (47:32) of the 88th 6-byte MAC address.
58670  *
58671  * Field Access Macros:
58672  *
58673  */
58674 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field. */
58675 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_LSB 0
58676 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field. */
58677 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_MSB 15
58678 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field. */
58679 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_WIDTH 16
58680 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field value. */
58681 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_SET_MSK 0x0000ffff
58682 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field value. */
58683 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_CLR_MSK 0xffff0000
58684 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field. */
58685 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_RESET 0xffff
58686 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI field value from a register. */
58687 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
58688 /* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field value suitable for setting the register. */
58689 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
58690 
58691 /*
58692  * Field : reserved_30_16
58693  *
58694  * Reserved
58695  *
58696  * Field Access Macros:
58697  *
58698  */
58699 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_RSVD_30_16 register field. */
58700 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_RSVD_30_16_LSB 16
58701 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_RSVD_30_16 register field. */
58702 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_RSVD_30_16_MSB 30
58703 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_RSVD_30_16 register field. */
58704 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_RSVD_30_16_WIDTH 15
58705 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_RSVD_30_16 register field value. */
58706 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
58707 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_RSVD_30_16 register field value. */
58708 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
58709 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_RSVD_30_16 register field. */
58710 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_RSVD_30_16_RESET 0x0
58711 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_RSVD_30_16 field value from a register. */
58712 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
58713 /* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_RSVD_30_16 register field value suitable for setting the register. */
58714 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
58715 
58716 /*
58717  * Field : ae
58718  *
58719  * Address Enable
58720  *
58721  * When this bit is set, the address filter module uses the 88th MAC address for
58722  * perfect filtering.
58723  *
58724  * When this bit is reset, the address filter module ignores the address for
58725  * filtering.
58726  *
58727  * Field Enumeration Values:
58728  *
58729  * Enum | Value | Description
58730  * :----------------------------------------|:------|:------------
58731  * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_E_DISD | 0x0 |
58732  * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_E_END | 0x1 |
58733  *
58734  * Field Access Macros:
58735  *
58736  */
58737 /*
58738  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE
58739  *
58740  */
58741 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_E_DISD 0x0
58742 /*
58743  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE
58744  *
58745  */
58746 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_E_END 0x1
58747 
58748 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field. */
58749 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_LSB 31
58750 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field. */
58751 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_MSB 31
58752 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field. */
58753 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_WIDTH 1
58754 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field value. */
58755 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_SET_MSK 0x80000000
58756 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field value. */
58757 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_CLR_MSK 0x7fffffff
58758 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field. */
58759 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_RESET 0x0
58760 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE field value from a register. */
58761 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
58762 /* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field value suitable for setting the register. */
58763 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
58764 
58765 #ifndef __ASSEMBLY__
58766 /*
58767  * WARNING: The C register and register group struct declarations are provided for
58768  * convenience and illustrative purposes. They should, however, be used with
58769  * caution as the C language standard provides no guarantees about the alignment or
58770  * atomicity of device memory accesses. The recommended practice for writing
58771  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
58772  * alt_write_word() functions.
58773  *
58774  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR87_HIGH.
58775  */
58776 struct ALT_EMAC_GMAC_MAC_ADDR87_HIGH_s
58777 {
58778  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI */
58779  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR87_HIGH_RSVD_30_16 */
58780  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE */
58781 };
58782 
58783 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR87_HIGH. */
58784 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR87_HIGH_s ALT_EMAC_GMAC_MAC_ADDR87_HIGH_t;
58785 #endif /* __ASSEMBLY__ */
58786 
58787 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH register. */
58788 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_RESET 0x0000ffff
58789 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH register from the beginning of the component. */
58790 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_OFST 0xa38
58791 /* The address of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH register. */
58792 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR87_HIGH_OFST))
58793 
58794 /*
58795  * Register : gmacgrp_mac_address87_low
58796  *
58797  * <b> Register 655 (MAC Address87 Low Register)</b>
58798  *
58799  * The MAC Address87 Low register holds the lower 32 bits of the 88th 6-byte MAC
58800  * address of the station.
58801  *
58802  * Register Layout
58803  *
58804  * Bits | Access | Reset | Description
58805  * :-------|:-------|:-----------|:------------------------------------
58806  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO
58807  *
58808  */
58809 /*
58810  * Field : addrlo
58811  *
58812  * MAC Address87 [31:0]
58813  *
58814  * This field contains the lower 32 bits of the 88th 6-byte MAC address. The
58815  * content of this field is undefined until loaded by the Application after the
58816  * initialization process.
58817  *
58818  * Field Access Macros:
58819  *
58820  */
58821 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field. */
58822 #define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_LSB 0
58823 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field. */
58824 #define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_MSB 31
58825 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field. */
58826 #define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_WIDTH 32
58827 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field value. */
58828 #define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_SET_MSK 0xffffffff
58829 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field value. */
58830 #define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_CLR_MSK 0x00000000
58831 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field. */
58832 #define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_RESET 0xffffffff
58833 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO field value from a register. */
58834 #define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
58835 /* Produces a ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field value suitable for setting the register. */
58836 #define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
58837 
58838 #ifndef __ASSEMBLY__
58839 /*
58840  * WARNING: The C register and register group struct declarations are provided for
58841  * convenience and illustrative purposes. They should, however, be used with
58842  * caution as the C language standard provides no guarantees about the alignment or
58843  * atomicity of device memory accesses. The recommended practice for writing
58844  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
58845  * alt_write_word() functions.
58846  *
58847  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR87_LOW.
58848  */
58849 struct ALT_EMAC_GMAC_MAC_ADDR87_LOW_s
58850 {
58851  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO */
58852 };
58853 
58854 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR87_LOW. */
58855 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR87_LOW_s ALT_EMAC_GMAC_MAC_ADDR87_LOW_t;
58856 #endif /* __ASSEMBLY__ */
58857 
58858 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_LOW register. */
58859 #define ALT_EMAC_GMAC_MAC_ADDR87_LOW_RESET 0xffffffff
58860 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR87_LOW register from the beginning of the component. */
58861 #define ALT_EMAC_GMAC_MAC_ADDR87_LOW_OFST 0xa3c
58862 /* The address of the ALT_EMAC_GMAC_MAC_ADDR87_LOW register. */
58863 #define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR87_LOW_OFST))
58864 
58865 /*
58866  * Register : gmacgrp_mac_address88_high
58867  *
58868  * <b> Register 656 (MAC Address88 High Register)</b>
58869  *
58870  * The MAC Address88 High register holds the upper 16 bits of the 89th 6-byte MAC
58871  * address of the station.
58872  *
58873  * If the MAC address registers are configured to be double-synchronized to the
58874  * (G)MII clock domains, then
58875  *
58876  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
58877  * or Bits[7:0] (in big-endian mode) of the MAC Address88 Low Register are written.
58878  * For proper synchronization updates, consecutive writes to this MAC Address88 Low
58879  * Register must be performed after at least four clock cycles in the destination
58880  * clock domain.
58881  *
58882  * Register Layout
58883  *
58884  * Bits | Access | Reset | Description
58885  * :--------|:-------|:-------|:-----------------------------------------
58886  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI
58887  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR88_HIGH_RSVD_30_16
58888  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE
58889  *
58890  */
58891 /*
58892  * Field : addrhi
58893  *
58894  * MAC Address88 [47:32]
58895  *
58896  * This field contains the upper 16 bits (47:32) of the 89th 6-byte MAC address.
58897  *
58898  * Field Access Macros:
58899  *
58900  */
58901 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field. */
58902 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_LSB 0
58903 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field. */
58904 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_MSB 15
58905 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field. */
58906 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_WIDTH 16
58907 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field value. */
58908 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_SET_MSK 0x0000ffff
58909 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field value. */
58910 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_CLR_MSK 0xffff0000
58911 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field. */
58912 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_RESET 0xffff
58913 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI field value from a register. */
58914 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
58915 /* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field value suitable for setting the register. */
58916 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
58917 
58918 /*
58919  * Field : reserved_30_16
58920  *
58921  * Reserved
58922  *
58923  * Field Access Macros:
58924  *
58925  */
58926 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_RSVD_30_16 register field. */
58927 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_RSVD_30_16_LSB 16
58928 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_RSVD_30_16 register field. */
58929 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_RSVD_30_16_MSB 30
58930 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_RSVD_30_16 register field. */
58931 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_RSVD_30_16_WIDTH 15
58932 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_RSVD_30_16 register field value. */
58933 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
58934 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_RSVD_30_16 register field value. */
58935 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
58936 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_RSVD_30_16 register field. */
58937 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_RSVD_30_16_RESET 0x0
58938 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_RSVD_30_16 field value from a register. */
58939 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
58940 /* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_RSVD_30_16 register field value suitable for setting the register. */
58941 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
58942 
58943 /*
58944  * Field : ae
58945  *
58946  * Address Enable
58947  *
58948  * When this bit is set, the address filter module uses the 89th MAC address for
58949  * perfect filtering.
58950  *
58951  * When this bit is reset, the address filter module ignores the address for
58952  * filtering.
58953  *
58954  * Field Enumeration Values:
58955  *
58956  * Enum | Value | Description
58957  * :----------------------------------------|:------|:------------
58958  * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_E_DISD | 0x0 |
58959  * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_E_END | 0x1 |
58960  *
58961  * Field Access Macros:
58962  *
58963  */
58964 /*
58965  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE
58966  *
58967  */
58968 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_E_DISD 0x0
58969 /*
58970  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE
58971  *
58972  */
58973 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_E_END 0x1
58974 
58975 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field. */
58976 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_LSB 31
58977 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field. */
58978 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_MSB 31
58979 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field. */
58980 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_WIDTH 1
58981 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field value. */
58982 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_SET_MSK 0x80000000
58983 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field value. */
58984 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_CLR_MSK 0x7fffffff
58985 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field. */
58986 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_RESET 0x0
58987 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE field value from a register. */
58988 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
58989 /* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field value suitable for setting the register. */
58990 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
58991 
58992 #ifndef __ASSEMBLY__
58993 /*
58994  * WARNING: The C register and register group struct declarations are provided for
58995  * convenience and illustrative purposes. They should, however, be used with
58996  * caution as the C language standard provides no guarantees about the alignment or
58997  * atomicity of device memory accesses. The recommended practice for writing
58998  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
58999  * alt_write_word() functions.
59000  *
59001  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR88_HIGH.
59002  */
59003 struct ALT_EMAC_GMAC_MAC_ADDR88_HIGH_s
59004 {
59005  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI */
59006  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR88_HIGH_RSVD_30_16 */
59007  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE */
59008 };
59009 
59010 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR88_HIGH. */
59011 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR88_HIGH_s ALT_EMAC_GMAC_MAC_ADDR88_HIGH_t;
59012 #endif /* __ASSEMBLY__ */
59013 
59014 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH register. */
59015 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_RESET 0x0000ffff
59016 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH register from the beginning of the component. */
59017 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_OFST 0xa40
59018 /* The address of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH register. */
59019 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR88_HIGH_OFST))
59020 
59021 /*
59022  * Register : gmacgrp_mac_address88_low
59023  *
59024  * <b> Register 657 (MAC Address88 Low Register)</b>
59025  *
59026  * The MAC Address88 Low register holds the lower 32 bits of the 89th 6-byte MAC
59027  * address of the station.
59028  *
59029  * Register Layout
59030  *
59031  * Bits | Access | Reset | Description
59032  * :-------|:-------|:-----------|:------------------------------------
59033  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO
59034  *
59035  */
59036 /*
59037  * Field : addrlo
59038  *
59039  * MAC Address88 [31:0]
59040  *
59041  * This field contains the lower 32 bits of the 89th 6-byte MAC address. The
59042  * content of this field is undefined until loaded by the Application after the
59043  * initialization process.
59044  *
59045  * Field Access Macros:
59046  *
59047  */
59048 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field. */
59049 #define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_LSB 0
59050 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field. */
59051 #define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_MSB 31
59052 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field. */
59053 #define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_WIDTH 32
59054 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field value. */
59055 #define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_SET_MSK 0xffffffff
59056 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field value. */
59057 #define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_CLR_MSK 0x00000000
59058 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field. */
59059 #define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_RESET 0xffffffff
59060 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO field value from a register. */
59061 #define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
59062 /* Produces a ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field value suitable for setting the register. */
59063 #define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
59064 
59065 #ifndef __ASSEMBLY__
59066 /*
59067  * WARNING: The C register and register group struct declarations are provided for
59068  * convenience and illustrative purposes. They should, however, be used with
59069  * caution as the C language standard provides no guarantees about the alignment or
59070  * atomicity of device memory accesses. The recommended practice for writing
59071  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
59072  * alt_write_word() functions.
59073  *
59074  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR88_LOW.
59075  */
59076 struct ALT_EMAC_GMAC_MAC_ADDR88_LOW_s
59077 {
59078  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO */
59079 };
59080 
59081 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR88_LOW. */
59082 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR88_LOW_s ALT_EMAC_GMAC_MAC_ADDR88_LOW_t;
59083 #endif /* __ASSEMBLY__ */
59084 
59085 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_LOW register. */
59086 #define ALT_EMAC_GMAC_MAC_ADDR88_LOW_RESET 0xffffffff
59087 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR88_LOW register from the beginning of the component. */
59088 #define ALT_EMAC_GMAC_MAC_ADDR88_LOW_OFST 0xa44
59089 /* The address of the ALT_EMAC_GMAC_MAC_ADDR88_LOW register. */
59090 #define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR88_LOW_OFST))
59091 
59092 /*
59093  * Register : gmacgrp_mac_address89_high
59094  *
59095  * <b> Register 658 (MAC Address89 High Register)</b>
59096  *
59097  * The MAC Address89 High register holds the upper 16 bits of the 90th 6-byte MAC
59098  * address of the station.
59099  *
59100  * If the MAC address registers are configured to be double-synchronized to the
59101  * (G)MII clock domains, then
59102  *
59103  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
59104  * or Bits[7:0] (in big-endian mode) of the MAC Address89 Low Register are written.
59105  * For proper synchronization updates, consecutive writes to this MAC Address89 Low
59106  * Register must be performed after at least four clock cycles in the destination
59107  * clock domain.
59108  *
59109  * Register Layout
59110  *
59111  * Bits | Access | Reset | Description
59112  * :--------|:-------|:-------|:-----------------------------------------
59113  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI
59114  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR89_HIGH_RSVD_30_16
59115  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE
59116  *
59117  */
59118 /*
59119  * Field : addrhi
59120  *
59121  * MAC Address89 [47:32]
59122  *
59123  * This field contains the upper 16 bits (47:32) of the 90th 6-byte MAC address.
59124  *
59125  * Field Access Macros:
59126  *
59127  */
59128 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field. */
59129 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_LSB 0
59130 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field. */
59131 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_MSB 15
59132 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field. */
59133 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_WIDTH 16
59134 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field value. */
59135 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_SET_MSK 0x0000ffff
59136 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field value. */
59137 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_CLR_MSK 0xffff0000
59138 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field. */
59139 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_RESET 0xffff
59140 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI field value from a register. */
59141 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
59142 /* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field value suitable for setting the register. */
59143 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
59144 
59145 /*
59146  * Field : reserved_30_16
59147  *
59148  * Reserved
59149  *
59150  * Field Access Macros:
59151  *
59152  */
59153 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_RSVD_30_16 register field. */
59154 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_RSVD_30_16_LSB 16
59155 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_RSVD_30_16 register field. */
59156 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_RSVD_30_16_MSB 30
59157 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_RSVD_30_16 register field. */
59158 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_RSVD_30_16_WIDTH 15
59159 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_RSVD_30_16 register field value. */
59160 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
59161 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_RSVD_30_16 register field value. */
59162 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
59163 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_RSVD_30_16 register field. */
59164 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_RSVD_30_16_RESET 0x0
59165 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_RSVD_30_16 field value from a register. */
59166 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
59167 /* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_RSVD_30_16 register field value suitable for setting the register. */
59168 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
59169 
59170 /*
59171  * Field : ae
59172  *
59173  * Address Enable
59174  *
59175  * When this bit is set, the address filter module uses the 90th MAC address for
59176  * perfect filtering.
59177  *
59178  * When this bit is reset, the address filter module ignores the address for
59179  * filtering.
59180  *
59181  * Field Enumeration Values:
59182  *
59183  * Enum | Value | Description
59184  * :----------------------------------------|:------|:------------
59185  * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_E_DISD | 0x0 |
59186  * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_E_END | 0x1 |
59187  *
59188  * Field Access Macros:
59189  *
59190  */
59191 /*
59192  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE
59193  *
59194  */
59195 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_E_DISD 0x0
59196 /*
59197  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE
59198  *
59199  */
59200 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_E_END 0x1
59201 
59202 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field. */
59203 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_LSB 31
59204 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field. */
59205 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_MSB 31
59206 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field. */
59207 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_WIDTH 1
59208 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field value. */
59209 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_SET_MSK 0x80000000
59210 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field value. */
59211 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_CLR_MSK 0x7fffffff
59212 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field. */
59213 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_RESET 0x0
59214 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE field value from a register. */
59215 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
59216 /* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field value suitable for setting the register. */
59217 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
59218 
59219 #ifndef __ASSEMBLY__
59220 /*
59221  * WARNING: The C register and register group struct declarations are provided for
59222  * convenience and illustrative purposes. They should, however, be used with
59223  * caution as the C language standard provides no guarantees about the alignment or
59224  * atomicity of device memory accesses. The recommended practice for writing
59225  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
59226  * alt_write_word() functions.
59227  *
59228  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR89_HIGH.
59229  */
59230 struct ALT_EMAC_GMAC_MAC_ADDR89_HIGH_s
59231 {
59232  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI */
59233  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR89_HIGH_RSVD_30_16 */
59234  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE */
59235 };
59236 
59237 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR89_HIGH. */
59238 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR89_HIGH_s ALT_EMAC_GMAC_MAC_ADDR89_HIGH_t;
59239 #endif /* __ASSEMBLY__ */
59240 
59241 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH register. */
59242 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_RESET 0x0000ffff
59243 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH register from the beginning of the component. */
59244 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_OFST 0xa48
59245 /* The address of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH register. */
59246 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR89_HIGH_OFST))
59247 
59248 /*
59249  * Register : gmacgrp_mac_address89_low
59250  *
59251  * <b> Register 659 (MAC Address89 Low Register)</b>
59252  *
59253  * The MAC Address89 Low register holds the lower 32 bits of the 90th 6-byte MAC
59254  * address of the station.
59255  *
59256  * Register Layout
59257  *
59258  * Bits | Access | Reset | Description
59259  * :-------|:-------|:-----------|:------------------------------------
59260  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO
59261  *
59262  */
59263 /*
59264  * Field : addrlo
59265  *
59266  * MAC Address89 [31:0]
59267  *
59268  * This field contains the lower 32 bits of the 90th 6-byte MAC address. The
59269  * content of this field is undefined until loaded by the Application after the
59270  * initialization process.
59271  *
59272  * Field Access Macros:
59273  *
59274  */
59275 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field. */
59276 #define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_LSB 0
59277 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field. */
59278 #define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_MSB 31
59279 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field. */
59280 #define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_WIDTH 32
59281 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field value. */
59282 #define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_SET_MSK 0xffffffff
59283 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field value. */
59284 #define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_CLR_MSK 0x00000000
59285 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field. */
59286 #define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_RESET 0xffffffff
59287 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO field value from a register. */
59288 #define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
59289 /* Produces a ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field value suitable for setting the register. */
59290 #define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
59291 
59292 #ifndef __ASSEMBLY__
59293 /*
59294  * WARNING: The C register and register group struct declarations are provided for
59295  * convenience and illustrative purposes. They should, however, be used with
59296  * caution as the C language standard provides no guarantees about the alignment or
59297  * atomicity of device memory accesses. The recommended practice for writing
59298  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
59299  * alt_write_word() functions.
59300  *
59301  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR89_LOW.
59302  */
59303 struct ALT_EMAC_GMAC_MAC_ADDR89_LOW_s
59304 {
59305  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO */
59306 };
59307 
59308 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR89_LOW. */
59309 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR89_LOW_s ALT_EMAC_GMAC_MAC_ADDR89_LOW_t;
59310 #endif /* __ASSEMBLY__ */
59311 
59312 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_LOW register. */
59313 #define ALT_EMAC_GMAC_MAC_ADDR89_LOW_RESET 0xffffffff
59314 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR89_LOW register from the beginning of the component. */
59315 #define ALT_EMAC_GMAC_MAC_ADDR89_LOW_OFST 0xa4c
59316 /* The address of the ALT_EMAC_GMAC_MAC_ADDR89_LOW register. */
59317 #define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR89_LOW_OFST))
59318 
59319 /*
59320  * Register : gmacgrp_mac_address90_high
59321  *
59322  * <b> Register 660 (MAC Address90 High Register)</b>
59323  *
59324  * The MAC Address90 High register holds the upper 16 bits of the 91st 6-byte MAC
59325  * address of the station.
59326  *
59327  * If the MAC address registers are configured to be double-synchronized to the
59328  * (G)MII clock domains, then
59329  *
59330  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
59331  * or Bits[7:0] (in big-endian mode) of the MAC Address90 Low Register are written.
59332  * For proper synchronization updates, consecutive writes to this MAC Address90 Low
59333  * Register must be performed after at least four clock cycles in the destination
59334  * clock domain.
59335  *
59336  * Register Layout
59337  *
59338  * Bits | Access | Reset | Description
59339  * :--------|:-------|:-------|:-----------------------------------------
59340  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI
59341  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR90_HIGH_RSVD_30_16
59342  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE
59343  *
59344  */
59345 /*
59346  * Field : addrhi
59347  *
59348  * MAC Address90 [47:32]
59349  *
59350  * This field contains the upper 16 bits (47:32) of the 91st 6-byte MAC address.
59351  *
59352  * Field Access Macros:
59353  *
59354  */
59355 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field. */
59356 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_LSB 0
59357 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field. */
59358 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_MSB 15
59359 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field. */
59360 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_WIDTH 16
59361 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field value. */
59362 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_SET_MSK 0x0000ffff
59363 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field value. */
59364 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_CLR_MSK 0xffff0000
59365 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field. */
59366 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_RESET 0xffff
59367 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI field value from a register. */
59368 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
59369 /* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field value suitable for setting the register. */
59370 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
59371 
59372 /*
59373  * Field : reserved_30_16
59374  *
59375  * Reserved
59376  *
59377  * Field Access Macros:
59378  *
59379  */
59380 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_RSVD_30_16 register field. */
59381 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_RSVD_30_16_LSB 16
59382 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_RSVD_30_16 register field. */
59383 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_RSVD_30_16_MSB 30
59384 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_RSVD_30_16 register field. */
59385 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_RSVD_30_16_WIDTH 15
59386 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_RSVD_30_16 register field value. */
59387 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
59388 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_RSVD_30_16 register field value. */
59389 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
59390 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_RSVD_30_16 register field. */
59391 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_RSVD_30_16_RESET 0x0
59392 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_RSVD_30_16 field value from a register. */
59393 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
59394 /* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_RSVD_30_16 register field value suitable for setting the register. */
59395 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
59396 
59397 /*
59398  * Field : ae
59399  *
59400  * Address Enable
59401  *
59402  * When this bit is set, the address filter module uses the 91st MAC address for
59403  * perfect filtering.
59404  *
59405  * When this bit is reset, the address filter module ignores the address for
59406  * filtering.
59407  *
59408  * Field Enumeration Values:
59409  *
59410  * Enum | Value | Description
59411  * :----------------------------------------|:------|:------------
59412  * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_E_DISD | 0x0 |
59413  * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_E_END | 0x1 |
59414  *
59415  * Field Access Macros:
59416  *
59417  */
59418 /*
59419  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE
59420  *
59421  */
59422 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_E_DISD 0x0
59423 /*
59424  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE
59425  *
59426  */
59427 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_E_END 0x1
59428 
59429 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field. */
59430 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_LSB 31
59431 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field. */
59432 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_MSB 31
59433 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field. */
59434 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_WIDTH 1
59435 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field value. */
59436 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_SET_MSK 0x80000000
59437 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field value. */
59438 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_CLR_MSK 0x7fffffff
59439 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field. */
59440 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_RESET 0x0
59441 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE field value from a register. */
59442 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
59443 /* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field value suitable for setting the register. */
59444 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
59445 
59446 #ifndef __ASSEMBLY__
59447 /*
59448  * WARNING: The C register and register group struct declarations are provided for
59449  * convenience and illustrative purposes. They should, however, be used with
59450  * caution as the C language standard provides no guarantees about the alignment or
59451  * atomicity of device memory accesses. The recommended practice for writing
59452  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
59453  * alt_write_word() functions.
59454  *
59455  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR90_HIGH.
59456  */
59457 struct ALT_EMAC_GMAC_MAC_ADDR90_HIGH_s
59458 {
59459  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI */
59460  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR90_HIGH_RSVD_30_16 */
59461  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE */
59462 };
59463 
59464 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR90_HIGH. */
59465 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR90_HIGH_s ALT_EMAC_GMAC_MAC_ADDR90_HIGH_t;
59466 #endif /* __ASSEMBLY__ */
59467 
59468 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH register. */
59469 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_RESET 0x0000ffff
59470 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH register from the beginning of the component. */
59471 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_OFST 0xa50
59472 /* The address of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH register. */
59473 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR90_HIGH_OFST))
59474 
59475 /*
59476  * Register : gmacgrp_mac_address90_low
59477  *
59478  * <b> Register 661 (MAC Address90 Low Register)</b>
59479  *
59480  * The MAC Address90 Low register holds the lower 32 bits of the 91st 6-byte MAC
59481  * address of the station.
59482  *
59483  * Register Layout
59484  *
59485  * Bits | Access | Reset | Description
59486  * :-------|:-------|:-----------|:------------------------------------
59487  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO
59488  *
59489  */
59490 /*
59491  * Field : addrlo
59492  *
59493  * MAC Address90 [31:0]
59494  *
59495  * This field contains the lower 32 bits of the 91st 6-byte MAC address. The
59496  * content of this field is undefined until loaded by the Application after the
59497  * initialization process.
59498  *
59499  * Field Access Macros:
59500  *
59501  */
59502 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field. */
59503 #define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_LSB 0
59504 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field. */
59505 #define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_MSB 31
59506 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field. */
59507 #define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_WIDTH 32
59508 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field value. */
59509 #define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_SET_MSK 0xffffffff
59510 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field value. */
59511 #define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_CLR_MSK 0x00000000
59512 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field. */
59513 #define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_RESET 0xffffffff
59514 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO field value from a register. */
59515 #define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
59516 /* Produces a ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field value suitable for setting the register. */
59517 #define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
59518 
59519 #ifndef __ASSEMBLY__
59520 /*
59521  * WARNING: The C register and register group struct declarations are provided for
59522  * convenience and illustrative purposes. They should, however, be used with
59523  * caution as the C language standard provides no guarantees about the alignment or
59524  * atomicity of device memory accesses. The recommended practice for writing
59525  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
59526  * alt_write_word() functions.
59527  *
59528  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR90_LOW.
59529  */
59530 struct ALT_EMAC_GMAC_MAC_ADDR90_LOW_s
59531 {
59532  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO */
59533 };
59534 
59535 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR90_LOW. */
59536 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR90_LOW_s ALT_EMAC_GMAC_MAC_ADDR90_LOW_t;
59537 #endif /* __ASSEMBLY__ */
59538 
59539 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_LOW register. */
59540 #define ALT_EMAC_GMAC_MAC_ADDR90_LOW_RESET 0xffffffff
59541 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR90_LOW register from the beginning of the component. */
59542 #define ALT_EMAC_GMAC_MAC_ADDR90_LOW_OFST 0xa54
59543 /* The address of the ALT_EMAC_GMAC_MAC_ADDR90_LOW register. */
59544 #define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR90_LOW_OFST))
59545 
59546 /*
59547  * Register : gmacgrp_mac_address91_high
59548  *
59549  * <b> Register 662 (MAC Address91 High Register)</b>
59550  *
59551  * The MAC Address91 High register holds the upper 16 bits of the 92nd 6-byte MAC
59552  * address of the station.
59553  *
59554  * If the MAC address registers are configured to be double-synchronized to the
59555  * (G)MII clock domains, then
59556  *
59557  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
59558  * or Bits[7:0] (in big-endian mode) of the MAC Address32 Low Register are written.
59559  * For proper synchronization updates, consecutive writes to this MAC Address91 Low
59560  * Register must be performed after at least four clock cycles in the destination
59561  * clock domain.
59562  *
59563  * Register Layout
59564  *
59565  * Bits | Access | Reset | Description
59566  * :--------|:-------|:-------|:-----------------------------------------
59567  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI
59568  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR91_HIGH_RSVD_30_16
59569  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE
59570  *
59571  */
59572 /*
59573  * Field : addrhi
59574  *
59575  * MAC Address91 [47:32]
59576  *
59577  * This field contains the upper 16 bits (47:32) of the 92nd 6-byte MAC address.
59578  *
59579  * Field Access Macros:
59580  *
59581  */
59582 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field. */
59583 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_LSB 0
59584 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field. */
59585 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_MSB 15
59586 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field. */
59587 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_WIDTH 16
59588 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field value. */
59589 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_SET_MSK 0x0000ffff
59590 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field value. */
59591 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_CLR_MSK 0xffff0000
59592 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field. */
59593 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_RESET 0xffff
59594 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI field value from a register. */
59595 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
59596 /* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field value suitable for setting the register. */
59597 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
59598 
59599 /*
59600  * Field : reserved_30_16
59601  *
59602  * Reserved
59603  *
59604  * Field Access Macros:
59605  *
59606  */
59607 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_RSVD_30_16 register field. */
59608 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_RSVD_30_16_LSB 16
59609 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_RSVD_30_16 register field. */
59610 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_RSVD_30_16_MSB 30
59611 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_RSVD_30_16 register field. */
59612 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_RSVD_30_16_WIDTH 15
59613 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_RSVD_30_16 register field value. */
59614 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
59615 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_RSVD_30_16 register field value. */
59616 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
59617 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_RSVD_30_16 register field. */
59618 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_RSVD_30_16_RESET 0x0
59619 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_RSVD_30_16 field value from a register. */
59620 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
59621 /* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_RSVD_30_16 register field value suitable for setting the register. */
59622 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
59623 
59624 /*
59625  * Field : ae
59626  *
59627  * Address Enable
59628  *
59629  * When this bit is set, the address filter module uses the 92nd MAC address for
59630  * perfect filtering.
59631  *
59632  * When this bit is reset, the address filter module ignores the address for
59633  * filtering.
59634  *
59635  * Field Enumeration Values:
59636  *
59637  * Enum | Value | Description
59638  * :----------------------------------------|:------|:------------
59639  * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_E_DISD | 0x0 |
59640  * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_E_END | 0x1 |
59641  *
59642  * Field Access Macros:
59643  *
59644  */
59645 /*
59646  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE
59647  *
59648  */
59649 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_E_DISD 0x0
59650 /*
59651  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE
59652  *
59653  */
59654 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_E_END 0x1
59655 
59656 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field. */
59657 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_LSB 31
59658 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field. */
59659 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_MSB 31
59660 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field. */
59661 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_WIDTH 1
59662 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field value. */
59663 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_SET_MSK 0x80000000
59664 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field value. */
59665 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_CLR_MSK 0x7fffffff
59666 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field. */
59667 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_RESET 0x0
59668 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE field value from a register. */
59669 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
59670 /* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field value suitable for setting the register. */
59671 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
59672 
59673 #ifndef __ASSEMBLY__
59674 /*
59675  * WARNING: The C register and register group struct declarations are provided for
59676  * convenience and illustrative purposes. They should, however, be used with
59677  * caution as the C language standard provides no guarantees about the alignment or
59678  * atomicity of device memory accesses. The recommended practice for writing
59679  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
59680  * alt_write_word() functions.
59681  *
59682  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR91_HIGH.
59683  */
59684 struct ALT_EMAC_GMAC_MAC_ADDR91_HIGH_s
59685 {
59686  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI */
59687  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR91_HIGH_RSVD_30_16 */
59688  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE */
59689 };
59690 
59691 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR91_HIGH. */
59692 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR91_HIGH_s ALT_EMAC_GMAC_MAC_ADDR91_HIGH_t;
59693 #endif /* __ASSEMBLY__ */
59694 
59695 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH register. */
59696 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_RESET 0x0000ffff
59697 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH register from the beginning of the component. */
59698 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_OFST 0xa58
59699 /* The address of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH register. */
59700 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR91_HIGH_OFST))
59701 
59702 /*
59703  * Register : gmacgrp_mac_address91_low
59704  *
59705  * <b> Register 663 (MAC Address91 Low Register)</b>
59706  *
59707  * The MAC Address91 Low register holds the lower 32 bits of the 92nd 6-byte MAC
59708  * address of the station.
59709  *
59710  * Register Layout
59711  *
59712  * Bits | Access | Reset | Description
59713  * :-------|:-------|:-----------|:------------------------------------
59714  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO
59715  *
59716  */
59717 /*
59718  * Field : addrlo
59719  *
59720  * MAC Address91 [31:0]
59721  *
59722  * This field contains the lower 32 bits of the 92nd 6-byte MAC address. The
59723  * content of this field is undefined until loaded by the Application after the
59724  * initialization process.
59725  *
59726  * Field Access Macros:
59727  *
59728  */
59729 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field. */
59730 #define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_LSB 0
59731 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field. */
59732 #define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_MSB 31
59733 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field. */
59734 #define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_WIDTH 32
59735 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field value. */
59736 #define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_SET_MSK 0xffffffff
59737 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field value. */
59738 #define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_CLR_MSK 0x00000000
59739 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field. */
59740 #define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_RESET 0xffffffff
59741 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO field value from a register. */
59742 #define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
59743 /* Produces a ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field value suitable for setting the register. */
59744 #define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
59745 
59746 #ifndef __ASSEMBLY__
59747 /*
59748  * WARNING: The C register and register group struct declarations are provided for
59749  * convenience and illustrative purposes. They should, however, be used with
59750  * caution as the C language standard provides no guarantees about the alignment or
59751  * atomicity of device memory accesses. The recommended practice for writing
59752  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
59753  * alt_write_word() functions.
59754  *
59755  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR91_LOW.
59756  */
59757 struct ALT_EMAC_GMAC_MAC_ADDR91_LOW_s
59758 {
59759  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO */
59760 };
59761 
59762 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR91_LOW. */
59763 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR91_LOW_s ALT_EMAC_GMAC_MAC_ADDR91_LOW_t;
59764 #endif /* __ASSEMBLY__ */
59765 
59766 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_LOW register. */
59767 #define ALT_EMAC_GMAC_MAC_ADDR91_LOW_RESET 0xffffffff
59768 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR91_LOW register from the beginning of the component. */
59769 #define ALT_EMAC_GMAC_MAC_ADDR91_LOW_OFST 0xa5c
59770 /* The address of the ALT_EMAC_GMAC_MAC_ADDR91_LOW register. */
59771 #define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR91_LOW_OFST))
59772 
59773 /*
59774  * Register : gmacgrp_mac_address92_high
59775  *
59776  * <b> Register 664 (MAC Address92 High Register)</b>
59777  *
59778  * The MAC Address92 High register holds the upper 16 bits of the 93rd 6-byte MAC
59779  * address of the station.
59780  *
59781  * If the MAC address registers are configured to be double-synchronized to the
59782  * (G)MII clock domains, then
59783  *
59784  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
59785  * or Bits[7:0] (in big-endian mode) of the MAC Address92 Low Register are written.
59786  * For proper synchronization updates, consecutive writes to this MAC Address92 Low
59787  * Register must be performed after at least four clock cycles in the destination
59788  * clock domain.
59789  *
59790  * Register Layout
59791  *
59792  * Bits | Access | Reset | Description
59793  * :--------|:-------|:-------|:-----------------------------------------
59794  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI
59795  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR92_HIGH_RSVD_30_16
59796  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE
59797  *
59798  */
59799 /*
59800  * Field : addrhi
59801  *
59802  * MAC Address92 [47:32]
59803  *
59804  * This field contains the upper 16 bits (47:32) of the 93rd 6-byte MAC address.
59805  *
59806  * Field Access Macros:
59807  *
59808  */
59809 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field. */
59810 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_LSB 0
59811 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field. */
59812 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_MSB 15
59813 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field. */
59814 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_WIDTH 16
59815 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field value. */
59816 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_SET_MSK 0x0000ffff
59817 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field value. */
59818 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_CLR_MSK 0xffff0000
59819 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field. */
59820 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_RESET 0xffff
59821 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI field value from a register. */
59822 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
59823 /* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field value suitable for setting the register. */
59824 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
59825 
59826 /*
59827  * Field : reserved_30_16
59828  *
59829  * Reserved
59830  *
59831  * Field Access Macros:
59832  *
59833  */
59834 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_RSVD_30_16 register field. */
59835 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_RSVD_30_16_LSB 16
59836 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_RSVD_30_16 register field. */
59837 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_RSVD_30_16_MSB 30
59838 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_RSVD_30_16 register field. */
59839 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_RSVD_30_16_WIDTH 15
59840 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_RSVD_30_16 register field value. */
59841 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
59842 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_RSVD_30_16 register field value. */
59843 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
59844 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_RSVD_30_16 register field. */
59845 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_RSVD_30_16_RESET 0x0
59846 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_RSVD_30_16 field value from a register. */
59847 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
59848 /* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_RSVD_30_16 register field value suitable for setting the register. */
59849 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
59850 
59851 /*
59852  * Field : ae
59853  *
59854  * Address Enable
59855  *
59856  * When this bit is set, the address filter module uses the 93rd MAC address for
59857  * perfect filtering.
59858  *
59859  * When this bit is reset, the address filter module ignores the address for
59860  * filtering.
59861  *
59862  * Field Enumeration Values:
59863  *
59864  * Enum | Value | Description
59865  * :----------------------------------------|:------|:------------
59866  * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_E_DISD | 0x0 |
59867  * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_E_END | 0x1 |
59868  *
59869  * Field Access Macros:
59870  *
59871  */
59872 /*
59873  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE
59874  *
59875  */
59876 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_E_DISD 0x0
59877 /*
59878  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE
59879  *
59880  */
59881 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_E_END 0x1
59882 
59883 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field. */
59884 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_LSB 31
59885 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field. */
59886 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_MSB 31
59887 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field. */
59888 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_WIDTH 1
59889 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field value. */
59890 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_SET_MSK 0x80000000
59891 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field value. */
59892 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_CLR_MSK 0x7fffffff
59893 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field. */
59894 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_RESET 0x0
59895 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE field value from a register. */
59896 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
59897 /* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field value suitable for setting the register. */
59898 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
59899 
59900 #ifndef __ASSEMBLY__
59901 /*
59902  * WARNING: The C register and register group struct declarations are provided for
59903  * convenience and illustrative purposes. They should, however, be used with
59904  * caution as the C language standard provides no guarantees about the alignment or
59905  * atomicity of device memory accesses. The recommended practice for writing
59906  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
59907  * alt_write_word() functions.
59908  *
59909  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR92_HIGH.
59910  */
59911 struct ALT_EMAC_GMAC_MAC_ADDR92_HIGH_s
59912 {
59913  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI */
59914  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR92_HIGH_RSVD_30_16 */
59915  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE */
59916 };
59917 
59918 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR92_HIGH. */
59919 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR92_HIGH_s ALT_EMAC_GMAC_MAC_ADDR92_HIGH_t;
59920 #endif /* __ASSEMBLY__ */
59921 
59922 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH register. */
59923 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_RESET 0x0000ffff
59924 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH register from the beginning of the component. */
59925 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_OFST 0xa60
59926 /* The address of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH register. */
59927 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR92_HIGH_OFST))
59928 
59929 /*
59930  * Register : gmacgrp_mac_address92_low
59931  *
59932  * <b> Register 665 (MAC Address92 Low Register)</b>
59933  *
59934  * The MAC Address92 Low register holds the lower 32 bits of the 93rd 6-byte MAC
59935  * address of the station.
59936  *
59937  * Register Layout
59938  *
59939  * Bits | Access | Reset | Description
59940  * :-------|:-------|:-----------|:------------------------------------
59941  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO
59942  *
59943  */
59944 /*
59945  * Field : addrlo
59946  *
59947  * MAC Address92 [31:0]
59948  *
59949  * This field contains the lower 32 bits of the 93rd 6-byte MAC address. The
59950  * content of this field is undefined until loaded by the Application after the
59951  * initialization process.
59952  *
59953  * Field Access Macros:
59954  *
59955  */
59956 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field. */
59957 #define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_LSB 0
59958 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field. */
59959 #define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_MSB 31
59960 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field. */
59961 #define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_WIDTH 32
59962 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field value. */
59963 #define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_SET_MSK 0xffffffff
59964 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field value. */
59965 #define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_CLR_MSK 0x00000000
59966 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field. */
59967 #define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_RESET 0xffffffff
59968 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO field value from a register. */
59969 #define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
59970 /* Produces a ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field value suitable for setting the register. */
59971 #define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
59972 
59973 #ifndef __ASSEMBLY__
59974 /*
59975  * WARNING: The C register and register group struct declarations are provided for
59976  * convenience and illustrative purposes. They should, however, be used with
59977  * caution as the C language standard provides no guarantees about the alignment or
59978  * atomicity of device memory accesses. The recommended practice for writing
59979  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
59980  * alt_write_word() functions.
59981  *
59982  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR92_LOW.
59983  */
59984 struct ALT_EMAC_GMAC_MAC_ADDR92_LOW_s
59985 {
59986  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO */
59987 };
59988 
59989 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR92_LOW. */
59990 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR92_LOW_s ALT_EMAC_GMAC_MAC_ADDR92_LOW_t;
59991 #endif /* __ASSEMBLY__ */
59992 
59993 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_LOW register. */
59994 #define ALT_EMAC_GMAC_MAC_ADDR92_LOW_RESET 0xffffffff
59995 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR92_LOW register from the beginning of the component. */
59996 #define ALT_EMAC_GMAC_MAC_ADDR92_LOW_OFST 0xa64
59997 /* The address of the ALT_EMAC_GMAC_MAC_ADDR92_LOW register. */
59998 #define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR92_LOW_OFST))
59999 
60000 /*
60001  * Register : gmacgrp_mac_address93_high
60002  *
60003  * <b> Register 666 (MAC Address93 High Register)</b>
60004  *
60005  * The MAC Address93 High register holds the upper 16 bits of the 94th 6-byte MAC
60006  * address of the station.
60007  *
60008  * If the MAC address registers are configured to be double-synchronized to the
60009  * (G)MII clock domains, then
60010  *
60011  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
60012  * or Bits[7:0] (in big-endian mode) of the MAC Address93 Low Register are written.
60013  * For proper synchronization updates, consecutive writes to this MAC Address93 Low
60014  * Register must be performed after at least four clock cycles in the destination
60015  * clock domain.
60016  *
60017  * Register Layout
60018  *
60019  * Bits | Access | Reset | Description
60020  * :--------|:-------|:-------|:-----------------------------------------
60021  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI
60022  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR93_HIGH_RSVD_30_16
60023  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE
60024  *
60025  */
60026 /*
60027  * Field : addrhi
60028  *
60029  * MAC Address93 [47:32]
60030  *
60031  * This field contains the upper 16 bits (47:32) of the 94th 6-byte MAC address.
60032  *
60033  * Field Access Macros:
60034  *
60035  */
60036 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field. */
60037 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_LSB 0
60038 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field. */
60039 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_MSB 15
60040 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field. */
60041 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_WIDTH 16
60042 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field value. */
60043 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_SET_MSK 0x0000ffff
60044 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field value. */
60045 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_CLR_MSK 0xffff0000
60046 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field. */
60047 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_RESET 0xffff
60048 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI field value from a register. */
60049 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
60050 /* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field value suitable for setting the register. */
60051 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
60052 
60053 /*
60054  * Field : reserved_30_16
60055  *
60056  * Reserved
60057  *
60058  * Field Access Macros:
60059  *
60060  */
60061 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_RSVD_30_16 register field. */
60062 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_RSVD_30_16_LSB 16
60063 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_RSVD_30_16 register field. */
60064 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_RSVD_30_16_MSB 30
60065 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_RSVD_30_16 register field. */
60066 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_RSVD_30_16_WIDTH 15
60067 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_RSVD_30_16 register field value. */
60068 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
60069 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_RSVD_30_16 register field value. */
60070 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
60071 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_RSVD_30_16 register field. */
60072 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_RSVD_30_16_RESET 0x0
60073 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_RSVD_30_16 field value from a register. */
60074 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
60075 /* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_RSVD_30_16 register field value suitable for setting the register. */
60076 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
60077 
60078 /*
60079  * Field : ae
60080  *
60081  * Address Enable
60082  *
60083  * When this bit is set, the address filter module uses the 94th MAC address for
60084  * perfect filtering.
60085  *
60086  * When this bit is reset, the address filter module ignores the address for
60087  * filtering.
60088  *
60089  * Field Enumeration Values:
60090  *
60091  * Enum | Value | Description
60092  * :----------------------------------------|:------|:------------
60093  * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_E_DISD | 0x0 |
60094  * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_E_END | 0x1 |
60095  *
60096  * Field Access Macros:
60097  *
60098  */
60099 /*
60100  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE
60101  *
60102  */
60103 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_E_DISD 0x0
60104 /*
60105  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE
60106  *
60107  */
60108 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_E_END 0x1
60109 
60110 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field. */
60111 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_LSB 31
60112 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field. */
60113 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_MSB 31
60114 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field. */
60115 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_WIDTH 1
60116 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field value. */
60117 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_SET_MSK 0x80000000
60118 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field value. */
60119 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_CLR_MSK 0x7fffffff
60120 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field. */
60121 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_RESET 0x0
60122 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE field value from a register. */
60123 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
60124 /* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field value suitable for setting the register. */
60125 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
60126 
60127 #ifndef __ASSEMBLY__
60128 /*
60129  * WARNING: The C register and register group struct declarations are provided for
60130  * convenience and illustrative purposes. They should, however, be used with
60131  * caution as the C language standard provides no guarantees about the alignment or
60132  * atomicity of device memory accesses. The recommended practice for writing
60133  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
60134  * alt_write_word() functions.
60135  *
60136  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR93_HIGH.
60137  */
60138 struct ALT_EMAC_GMAC_MAC_ADDR93_HIGH_s
60139 {
60140  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI */
60141  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR93_HIGH_RSVD_30_16 */
60142  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE */
60143 };
60144 
60145 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR93_HIGH. */
60146 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR93_HIGH_s ALT_EMAC_GMAC_MAC_ADDR93_HIGH_t;
60147 #endif /* __ASSEMBLY__ */
60148 
60149 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH register. */
60150 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_RESET 0x0000ffff
60151 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH register from the beginning of the component. */
60152 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_OFST 0xa68
60153 /* The address of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH register. */
60154 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR93_HIGH_OFST))
60155 
60156 /*
60157  * Register : gmacgrp_mac_address93_low
60158  *
60159  * <b> Register 667 (MAC Address93 Low Register)</b>
60160  *
60161  * The MAC Address93 Low register holds the lower 32 bits of the 94th 6-byte MAC
60162  * address of the station.
60163  *
60164  * Register Layout
60165  *
60166  * Bits | Access | Reset | Description
60167  * :-------|:-------|:-----------|:------------------------------------
60168  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO
60169  *
60170  */
60171 /*
60172  * Field : addrlo
60173  *
60174  * MAC Address93 [31:0]
60175  *
60176  * This field contains the lower 32 bits of the 94th 6-byte MAC address. The
60177  * content of this field is undefined until loaded by the Application after the
60178  * initialization process.
60179  *
60180  * Field Access Macros:
60181  *
60182  */
60183 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field. */
60184 #define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_LSB 0
60185 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field. */
60186 #define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_MSB 31
60187 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field. */
60188 #define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_WIDTH 32
60189 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field value. */
60190 #define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_SET_MSK 0xffffffff
60191 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field value. */
60192 #define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_CLR_MSK 0x00000000
60193 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field. */
60194 #define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_RESET 0xffffffff
60195 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO field value from a register. */
60196 #define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
60197 /* Produces a ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field value suitable for setting the register. */
60198 #define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
60199 
60200 #ifndef __ASSEMBLY__
60201 /*
60202  * WARNING: The C register and register group struct declarations are provided for
60203  * convenience and illustrative purposes. They should, however, be used with
60204  * caution as the C language standard provides no guarantees about the alignment or
60205  * atomicity of device memory accesses. The recommended practice for writing
60206  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
60207  * alt_write_word() functions.
60208  *
60209  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR93_LOW.
60210  */
60211 struct ALT_EMAC_GMAC_MAC_ADDR93_LOW_s
60212 {
60213  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO */
60214 };
60215 
60216 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR93_LOW. */
60217 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR93_LOW_s ALT_EMAC_GMAC_MAC_ADDR93_LOW_t;
60218 #endif /* __ASSEMBLY__ */
60219 
60220 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_LOW register. */
60221 #define ALT_EMAC_GMAC_MAC_ADDR93_LOW_RESET 0xffffffff
60222 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR93_LOW register from the beginning of the component. */
60223 #define ALT_EMAC_GMAC_MAC_ADDR93_LOW_OFST 0xa6c
60224 /* The address of the ALT_EMAC_GMAC_MAC_ADDR93_LOW register. */
60225 #define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR93_LOW_OFST))
60226 
60227 /*
60228  * Register : gmacgrp_mac_address94_high
60229  *
60230  * <b> Register 668 (MAC Address94 High Register)</b>
60231  *
60232  * The MAC Address94 High register holds the upper 16 bits of the 95th 6-byte MAC
60233  * address of the station.
60234  *
60235  * If the MAC address registers are configured to be double-synchronized to the
60236  * (G)MII clock domains, then
60237  *
60238  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
60239  * or Bits[7:0] (in big-endian mode) of the MAC Address94 Low Register are written.
60240  * For proper synchronization updates, consecutive writes to this MAC Address94 Low
60241  * Register must be performed after at least four clock cycles in the destination
60242  * clock domain.
60243  *
60244  * Register Layout
60245  *
60246  * Bits | Access | Reset | Description
60247  * :--------|:-------|:-------|:-----------------------------------------
60248  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI
60249  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR94_HIGH_RSVD_30_16
60250  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE
60251  *
60252  */
60253 /*
60254  * Field : addrhi
60255  *
60256  * MAC Address94 [47:32]
60257  *
60258  * This field contains the upper 16 bits (47:32) of the 95th 6-byte MAC address.
60259  *
60260  * Field Access Macros:
60261  *
60262  */
60263 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field. */
60264 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_LSB 0
60265 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field. */
60266 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_MSB 15
60267 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field. */
60268 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_WIDTH 16
60269 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field value. */
60270 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_SET_MSK 0x0000ffff
60271 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field value. */
60272 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_CLR_MSK 0xffff0000
60273 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field. */
60274 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_RESET 0xffff
60275 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI field value from a register. */
60276 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
60277 /* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field value suitable for setting the register. */
60278 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
60279 
60280 /*
60281  * Field : reserved_30_16
60282  *
60283  * Reserved
60284  *
60285  * Field Access Macros:
60286  *
60287  */
60288 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_RSVD_30_16 register field. */
60289 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_RSVD_30_16_LSB 16
60290 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_RSVD_30_16 register field. */
60291 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_RSVD_30_16_MSB 30
60292 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_RSVD_30_16 register field. */
60293 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_RSVD_30_16_WIDTH 15
60294 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_RSVD_30_16 register field value. */
60295 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
60296 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_RSVD_30_16 register field value. */
60297 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
60298 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_RSVD_30_16 register field. */
60299 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_RSVD_30_16_RESET 0x0
60300 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_RSVD_30_16 field value from a register. */
60301 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
60302 /* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_RSVD_30_16 register field value suitable for setting the register. */
60303 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
60304 
60305 /*
60306  * Field : ae
60307  *
60308  * Address Enable
60309  *
60310  * When this bit is set, the address filter module uses the 95th MAC address for
60311  * perfect filtering.
60312  *
60313  * When this bit is reset, the address filter module ignores the address for
60314  * filtering.
60315  *
60316  * Field Enumeration Values:
60317  *
60318  * Enum | Value | Description
60319  * :----------------------------------------|:------|:------------
60320  * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_E_DISD | 0x0 |
60321  * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_E_END | 0x1 |
60322  *
60323  * Field Access Macros:
60324  *
60325  */
60326 /*
60327  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE
60328  *
60329  */
60330 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_E_DISD 0x0
60331 /*
60332  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE
60333  *
60334  */
60335 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_E_END 0x1
60336 
60337 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field. */
60338 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_LSB 31
60339 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field. */
60340 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_MSB 31
60341 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field. */
60342 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_WIDTH 1
60343 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field value. */
60344 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_SET_MSK 0x80000000
60345 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field value. */
60346 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_CLR_MSK 0x7fffffff
60347 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field. */
60348 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_RESET 0x0
60349 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE field value from a register. */
60350 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
60351 /* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field value suitable for setting the register. */
60352 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
60353 
60354 #ifndef __ASSEMBLY__
60355 /*
60356  * WARNING: The C register and register group struct declarations are provided for
60357  * convenience and illustrative purposes. They should, however, be used with
60358  * caution as the C language standard provides no guarantees about the alignment or
60359  * atomicity of device memory accesses. The recommended practice for writing
60360  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
60361  * alt_write_word() functions.
60362  *
60363  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR94_HIGH.
60364  */
60365 struct ALT_EMAC_GMAC_MAC_ADDR94_HIGH_s
60366 {
60367  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI */
60368  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR94_HIGH_RSVD_30_16 */
60369  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE */
60370 };
60371 
60372 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR94_HIGH. */
60373 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR94_HIGH_s ALT_EMAC_GMAC_MAC_ADDR94_HIGH_t;
60374 #endif /* __ASSEMBLY__ */
60375 
60376 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH register. */
60377 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_RESET 0x0000ffff
60378 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH register from the beginning of the component. */
60379 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_OFST 0xa70
60380 /* The address of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH register. */
60381 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR94_HIGH_OFST))
60382 
60383 /*
60384  * Register : gmacgrp_mac_address94_low
60385  *
60386  * <b> Register 669 (MAC Address94 Low Register)</b>
60387  *
60388  * The MAC Address94 Low register holds the lower 32 bits of the 95th 6-byte MAC
60389  * address of the station.
60390  *
60391  * Register Layout
60392  *
60393  * Bits | Access | Reset | Description
60394  * :-------|:-------|:-----------|:------------------------------------
60395  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO
60396  *
60397  */
60398 /*
60399  * Field : addrlo
60400  *
60401  * MAC Address94 [31:0]
60402  *
60403  * This field contains the lower 32 bits of the 95th 6-byte MAC address. The
60404  * content of this field is undefined until loaded by the Application after the
60405  * initialization process.
60406  *
60407  * Field Access Macros:
60408  *
60409  */
60410 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field. */
60411 #define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_LSB 0
60412 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field. */
60413 #define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_MSB 31
60414 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field. */
60415 #define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_WIDTH 32
60416 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field value. */
60417 #define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_SET_MSK 0xffffffff
60418 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field value. */
60419 #define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_CLR_MSK 0x00000000
60420 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field. */
60421 #define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_RESET 0xffffffff
60422 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO field value from a register. */
60423 #define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
60424 /* Produces a ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field value suitable for setting the register. */
60425 #define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
60426 
60427 #ifndef __ASSEMBLY__
60428 /*
60429  * WARNING: The C register and register group struct declarations are provided for
60430  * convenience and illustrative purposes. They should, however, be used with
60431  * caution as the C language standard provides no guarantees about the alignment or
60432  * atomicity of device memory accesses. The recommended practice for writing
60433  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
60434  * alt_write_word() functions.
60435  *
60436  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR94_LOW.
60437  */
60438 struct ALT_EMAC_GMAC_MAC_ADDR94_LOW_s
60439 {
60440  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO */
60441 };
60442 
60443 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR94_LOW. */
60444 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR94_LOW_s ALT_EMAC_GMAC_MAC_ADDR94_LOW_t;
60445 #endif /* __ASSEMBLY__ */
60446 
60447 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_LOW register. */
60448 #define ALT_EMAC_GMAC_MAC_ADDR94_LOW_RESET 0xffffffff
60449 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR94_LOW register from the beginning of the component. */
60450 #define ALT_EMAC_GMAC_MAC_ADDR94_LOW_OFST 0xa74
60451 /* The address of the ALT_EMAC_GMAC_MAC_ADDR94_LOW register. */
60452 #define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR94_LOW_OFST))
60453 
60454 /*
60455  * Register : gmacgrp_mac_address95_high
60456  *
60457  * <b> Register 670 (MAC Address95 High Register)</b>
60458  *
60459  * The MAC Address95 High register holds the upper 16 bits of the 96th 6-byte MAC
60460  * address of the station.
60461  *
60462  * If the MAC address registers are configured to be double-synchronized to the
60463  * (G)MII clock domains, then
60464  *
60465  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
60466  * or Bits[7:0] (in big-endian mode) of the MAC Address95 Low Register are written.
60467  * For proper synchronization updates, consecutive writes to this MAC Address95 Low
60468  * Register must be performed after at least four clock cycles in the destination
60469  * clock domain.
60470  *
60471  * Register Layout
60472  *
60473  * Bits | Access | Reset | Description
60474  * :--------|:-------|:-------|:-----------------------------------------
60475  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI
60476  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR95_HIGH_RSVD_30_16
60477  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE
60478  *
60479  */
60480 /*
60481  * Field : addrhi
60482  *
60483  * MAC Address95 [47:32]
60484  *
60485  * This field contains the upper 16 bits (47:32) of the 96th 6-byte MAC address.
60486  *
60487  * Field Access Macros:
60488  *
60489  */
60490 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field. */
60491 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_LSB 0
60492 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field. */
60493 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_MSB 15
60494 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field. */
60495 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_WIDTH 16
60496 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field value. */
60497 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_SET_MSK 0x0000ffff
60498 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field value. */
60499 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_CLR_MSK 0xffff0000
60500 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field. */
60501 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_RESET 0xffff
60502 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI field value from a register. */
60503 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
60504 /* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field value suitable for setting the register. */
60505 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
60506 
60507 /*
60508  * Field : reserved_30_16
60509  *
60510  * Reserved
60511  *
60512  * Field Access Macros:
60513  *
60514  */
60515 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_RSVD_30_16 register field. */
60516 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_RSVD_30_16_LSB 16
60517 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_RSVD_30_16 register field. */
60518 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_RSVD_30_16_MSB 30
60519 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_RSVD_30_16 register field. */
60520 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_RSVD_30_16_WIDTH 15
60521 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_RSVD_30_16 register field value. */
60522 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
60523 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_RSVD_30_16 register field value. */
60524 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
60525 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_RSVD_30_16 register field. */
60526 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_RSVD_30_16_RESET 0x0
60527 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_RSVD_30_16 field value from a register. */
60528 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
60529 /* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_RSVD_30_16 register field value suitable for setting the register. */
60530 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
60531 
60532 /*
60533  * Field : ae
60534  *
60535  * Address Enable
60536  *
60537  * When this bit is set, the address filter module uses the 96th MAC address for
60538  * perfect filtering.
60539  *
60540  * When this bit is reset, the address filter module ignores the address for
60541  * filtering.
60542  *
60543  * Field Enumeration Values:
60544  *
60545  * Enum | Value | Description
60546  * :----------------------------------------|:------|:------------
60547  * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_E_DISD | 0x0 |
60548  * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_E_END | 0x1 |
60549  *
60550  * Field Access Macros:
60551  *
60552  */
60553 /*
60554  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE
60555  *
60556  */
60557 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_E_DISD 0x0
60558 /*
60559  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE
60560  *
60561  */
60562 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_E_END 0x1
60563 
60564 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field. */
60565 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_LSB 31
60566 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field. */
60567 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_MSB 31
60568 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field. */
60569 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_WIDTH 1
60570 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field value. */
60571 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_SET_MSK 0x80000000
60572 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field value. */
60573 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_CLR_MSK 0x7fffffff
60574 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field. */
60575 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_RESET 0x0
60576 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE field value from a register. */
60577 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
60578 /* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field value suitable for setting the register. */
60579 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
60580 
60581 #ifndef __ASSEMBLY__
60582 /*
60583  * WARNING: The C register and register group struct declarations are provided for
60584  * convenience and illustrative purposes. They should, however, be used with
60585  * caution as the C language standard provides no guarantees about the alignment or
60586  * atomicity of device memory accesses. The recommended practice for writing
60587  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
60588  * alt_write_word() functions.
60589  *
60590  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR95_HIGH.
60591  */
60592 struct ALT_EMAC_GMAC_MAC_ADDR95_HIGH_s
60593 {
60594  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI */
60595  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR95_HIGH_RSVD_30_16 */
60596  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE */
60597 };
60598 
60599 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR95_HIGH. */
60600 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR95_HIGH_s ALT_EMAC_GMAC_MAC_ADDR95_HIGH_t;
60601 #endif /* __ASSEMBLY__ */
60602 
60603 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH register. */
60604 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_RESET 0x0000ffff
60605 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH register from the beginning of the component. */
60606 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_OFST 0xa78
60607 /* The address of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH register. */
60608 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR95_HIGH_OFST))
60609 
60610 /*
60611  * Register : gmacgrp_mac_address95_low
60612  *
60613  * <b> Register 671 (MAC Address95 Low Register)</b>
60614  *
60615  * The MAC Address95 Low register holds the lower 32 bits of the 96th 6-byte MAC
60616  * address of the station.
60617  *
60618  * Register Layout
60619  *
60620  * Bits | Access | Reset | Description
60621  * :-------|:-------|:-----------|:------------------------------------
60622  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO
60623  *
60624  */
60625 /*
60626  * Field : addrlo
60627  *
60628  * MAC Address95 [31:0]
60629  *
60630  * This field contains the lower 32 bits of the 96th 6-byte MAC address. The
60631  * content of this field is undefined until loaded by the Application after the
60632  * initialization process.
60633  *
60634  * Field Access Macros:
60635  *
60636  */
60637 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field. */
60638 #define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_LSB 0
60639 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field. */
60640 #define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_MSB 31
60641 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field. */
60642 #define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_WIDTH 32
60643 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field value. */
60644 #define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_SET_MSK 0xffffffff
60645 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field value. */
60646 #define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_CLR_MSK 0x00000000
60647 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field. */
60648 #define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_RESET 0xffffffff
60649 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO field value from a register. */
60650 #define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
60651 /* Produces a ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field value suitable for setting the register. */
60652 #define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
60653 
60654 #ifndef __ASSEMBLY__
60655 /*
60656  * WARNING: The C register and register group struct declarations are provided for
60657  * convenience and illustrative purposes. They should, however, be used with
60658  * caution as the C language standard provides no guarantees about the alignment or
60659  * atomicity of device memory accesses. The recommended practice for writing
60660  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
60661  * alt_write_word() functions.
60662  *
60663  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR95_LOW.
60664  */
60665 struct ALT_EMAC_GMAC_MAC_ADDR95_LOW_s
60666 {
60667  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO */
60668 };
60669 
60670 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR95_LOW. */
60671 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR95_LOW_s ALT_EMAC_GMAC_MAC_ADDR95_LOW_t;
60672 #endif /* __ASSEMBLY__ */
60673 
60674 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_LOW register. */
60675 #define ALT_EMAC_GMAC_MAC_ADDR95_LOW_RESET 0xffffffff
60676 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR95_LOW register from the beginning of the component. */
60677 #define ALT_EMAC_GMAC_MAC_ADDR95_LOW_OFST 0xa7c
60678 /* The address of the ALT_EMAC_GMAC_MAC_ADDR95_LOW register. */
60679 #define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR95_LOW_OFST))
60680 
60681 /*
60682  * Register : gmacgrp_mac_address96_high
60683  *
60684  * <b> Register 672 (MAC Address96 High Register)</b>
60685  *
60686  * The MAC Address96 High register holds the upper 16 bits of the 97th 6-byte MAC
60687  * address of the station.
60688  *
60689  * If the MAC address registers are configured to be double-synchronized to the
60690  * (G)MII clock domains, then
60691  *
60692  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
60693  * or Bits[7:0] (in big-endian mode) of the MAC Address96 Low Register are written.
60694  * For proper synchronization updates, consecutive writes to this MAC Address96 Low
60695  * Register must be performed after at least four clock cycles in the destination
60696  * clock domain.
60697  *
60698  * Register Layout
60699  *
60700  * Bits | Access | Reset | Description
60701  * :--------|:-------|:-------|:-----------------------------------------
60702  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI
60703  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR96_HIGH_RSVD_30_16
60704  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE
60705  *
60706  */
60707 /*
60708  * Field : addrhi
60709  *
60710  * MAC Address96 [47:32]
60711  *
60712  * This field contains the upper 16 bits (47:32) of the 97th 6-byte MAC address.
60713  *
60714  * Field Access Macros:
60715  *
60716  */
60717 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field. */
60718 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_LSB 0
60719 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field. */
60720 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_MSB 15
60721 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field. */
60722 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_WIDTH 16
60723 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field value. */
60724 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_SET_MSK 0x0000ffff
60725 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field value. */
60726 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_CLR_MSK 0xffff0000
60727 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field. */
60728 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_RESET 0xffff
60729 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI field value from a register. */
60730 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
60731 /* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field value suitable for setting the register. */
60732 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
60733 
60734 /*
60735  * Field : reserved_30_16
60736  *
60737  * Reserved
60738  *
60739  * Field Access Macros:
60740  *
60741  */
60742 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_RSVD_30_16 register field. */
60743 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_RSVD_30_16_LSB 16
60744 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_RSVD_30_16 register field. */
60745 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_RSVD_30_16_MSB 30
60746 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_RSVD_30_16 register field. */
60747 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_RSVD_30_16_WIDTH 15
60748 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_RSVD_30_16 register field value. */
60749 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
60750 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_RSVD_30_16 register field value. */
60751 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
60752 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_RSVD_30_16 register field. */
60753 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_RSVD_30_16_RESET 0x0
60754 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_RSVD_30_16 field value from a register. */
60755 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
60756 /* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_RSVD_30_16 register field value suitable for setting the register. */
60757 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
60758 
60759 /*
60760  * Field : ae
60761  *
60762  * Address Enable
60763  *
60764  * When this bit is set, the address filter module uses the 97th MAC address for
60765  * perfect filtering.
60766  *
60767  * When this bit is reset, the address filter module ignores the address for
60768  * filtering.
60769  *
60770  * Field Enumeration Values:
60771  *
60772  * Enum | Value | Description
60773  * :----------------------------------------|:------|:------------
60774  * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_E_DISD | 0x0 |
60775  * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_E_END | 0x1 |
60776  *
60777  * Field Access Macros:
60778  *
60779  */
60780 /*
60781  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE
60782  *
60783  */
60784 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_E_DISD 0x0
60785 /*
60786  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE
60787  *
60788  */
60789 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_E_END 0x1
60790 
60791 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field. */
60792 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_LSB 31
60793 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field. */
60794 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_MSB 31
60795 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field. */
60796 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_WIDTH 1
60797 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field value. */
60798 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_SET_MSK 0x80000000
60799 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field value. */
60800 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_CLR_MSK 0x7fffffff
60801 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field. */
60802 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_RESET 0x0
60803 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE field value from a register. */
60804 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
60805 /* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field value suitable for setting the register. */
60806 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
60807 
60808 #ifndef __ASSEMBLY__
60809 /*
60810  * WARNING: The C register and register group struct declarations are provided for
60811  * convenience and illustrative purposes. They should, however, be used with
60812  * caution as the C language standard provides no guarantees about the alignment or
60813  * atomicity of device memory accesses. The recommended practice for writing
60814  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
60815  * alt_write_word() functions.
60816  *
60817  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR96_HIGH.
60818  */
60819 struct ALT_EMAC_GMAC_MAC_ADDR96_HIGH_s
60820 {
60821  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI */
60822  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR96_HIGH_RSVD_30_16 */
60823  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE */
60824 };
60825 
60826 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR96_HIGH. */
60827 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR96_HIGH_s ALT_EMAC_GMAC_MAC_ADDR96_HIGH_t;
60828 #endif /* __ASSEMBLY__ */
60829 
60830 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH register. */
60831 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_RESET 0x0000ffff
60832 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH register from the beginning of the component. */
60833 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_OFST 0xa80
60834 /* The address of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH register. */
60835 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR96_HIGH_OFST))
60836 
60837 /*
60838  * Register : gmacgrp_mac_address96_low
60839  *
60840  * <b> Register 673 (MAC Address96 Low Register)</b>
60841  *
60842  * The MAC Address96 Low register holds the lower 32 bits of the 97th 6-byte MAC
60843  * address of the station.
60844  *
60845  * Register Layout
60846  *
60847  * Bits | Access | Reset | Description
60848  * :-------|:-------|:-----------|:------------------------------------
60849  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO
60850  *
60851  */
60852 /*
60853  * Field : addrlo
60854  *
60855  * MAC Address96 [31:0]
60856  *
60857  * This field contains the lower 32 bits of the 97th 6-byte MAC address. The
60858  * content of this field is undefined until loaded by the Application after the
60859  * initialization process.
60860  *
60861  * Field Access Macros:
60862  *
60863  */
60864 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field. */
60865 #define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_LSB 0
60866 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field. */
60867 #define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_MSB 31
60868 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field. */
60869 #define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_WIDTH 32
60870 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field value. */
60871 #define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_SET_MSK 0xffffffff
60872 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field value. */
60873 #define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_CLR_MSK 0x00000000
60874 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field. */
60875 #define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_RESET 0xffffffff
60876 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO field value from a register. */
60877 #define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
60878 /* Produces a ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field value suitable for setting the register. */
60879 #define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
60880 
60881 #ifndef __ASSEMBLY__
60882 /*
60883  * WARNING: The C register and register group struct declarations are provided for
60884  * convenience and illustrative purposes. They should, however, be used with
60885  * caution as the C language standard provides no guarantees about the alignment or
60886  * atomicity of device memory accesses. The recommended practice for writing
60887  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
60888  * alt_write_word() functions.
60889  *
60890  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR96_LOW.
60891  */
60892 struct ALT_EMAC_GMAC_MAC_ADDR96_LOW_s
60893 {
60894  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO */
60895 };
60896 
60897 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR96_LOW. */
60898 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR96_LOW_s ALT_EMAC_GMAC_MAC_ADDR96_LOW_t;
60899 #endif /* __ASSEMBLY__ */
60900 
60901 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_LOW register. */
60902 #define ALT_EMAC_GMAC_MAC_ADDR96_LOW_RESET 0xffffffff
60903 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR96_LOW register from the beginning of the component. */
60904 #define ALT_EMAC_GMAC_MAC_ADDR96_LOW_OFST 0xa84
60905 /* The address of the ALT_EMAC_GMAC_MAC_ADDR96_LOW register. */
60906 #define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR96_LOW_OFST))
60907 
60908 /*
60909  * Register : gmacgrp_mac_address97_high
60910  *
60911  * <b> Register 674 (MAC Address97 High Register)</b>
60912  *
60913  * The MAC Address97 High register holds the upper 16 bits of the 98th 6-byte MAC
60914  * address of the station.
60915  *
60916  * If the MAC address registers are configured to be double-synchronized to the
60917  * (G)MII clock domains, then
60918  *
60919  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
60920  * or Bits[7:0] (in big-endian mode) of the MAC Address97 Low Register are written.
60921  * For proper synchronization updates, consecutive writes to this MAC Address97 Low
60922  * Register must be performed after at least four clock cycles in the destination
60923  * clock domain.
60924  *
60925  * Register Layout
60926  *
60927  * Bits | Access | Reset | Description
60928  * :--------|:-------|:-------|:-----------------------------------------
60929  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI
60930  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR97_HIGH_RSVD_30_16
60931  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE
60932  *
60933  */
60934 /*
60935  * Field : addrhi
60936  *
60937  * MAC Address97 [47:32]
60938  *
60939  * This field contains the upper 16 bits (47:32) of the 98th 6-byte MAC address.
60940  *
60941  * Field Access Macros:
60942  *
60943  */
60944 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field. */
60945 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_LSB 0
60946 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field. */
60947 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_MSB 15
60948 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field. */
60949 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_WIDTH 16
60950 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field value. */
60951 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_SET_MSK 0x0000ffff
60952 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field value. */
60953 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_CLR_MSK 0xffff0000
60954 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field. */
60955 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_RESET 0xffff
60956 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI field value from a register. */
60957 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
60958 /* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field value suitable for setting the register. */
60959 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
60960 
60961 /*
60962  * Field : reserved_30_16
60963  *
60964  * Reserved
60965  *
60966  * Field Access Macros:
60967  *
60968  */
60969 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_RSVD_30_16 register field. */
60970 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_RSVD_30_16_LSB 16
60971 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_RSVD_30_16 register field. */
60972 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_RSVD_30_16_MSB 30
60973 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_RSVD_30_16 register field. */
60974 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_RSVD_30_16_WIDTH 15
60975 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_RSVD_30_16 register field value. */
60976 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
60977 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_RSVD_30_16 register field value. */
60978 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
60979 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_RSVD_30_16 register field. */
60980 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_RSVD_30_16_RESET 0x0
60981 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_RSVD_30_16 field value from a register. */
60982 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
60983 /* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_RSVD_30_16 register field value suitable for setting the register. */
60984 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
60985 
60986 /*
60987  * Field : ae
60988  *
60989  * Address Enable
60990  *
60991  * When this bit is set, the address filter module uses the 98th MAC address for
60992  * perfect filtering.
60993  *
60994  * When this bit is reset, the address filter module ignores the address for
60995  * filtering.
60996  *
60997  * Field Enumeration Values:
60998  *
60999  * Enum | Value | Description
61000  * :----------------------------------------|:------|:------------
61001  * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_E_DISD | 0x0 |
61002  * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_E_END | 0x1 |
61003  *
61004  * Field Access Macros:
61005  *
61006  */
61007 /*
61008  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE
61009  *
61010  */
61011 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_E_DISD 0x0
61012 /*
61013  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE
61014  *
61015  */
61016 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_E_END 0x1
61017 
61018 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field. */
61019 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_LSB 31
61020 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field. */
61021 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_MSB 31
61022 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field. */
61023 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_WIDTH 1
61024 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field value. */
61025 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_SET_MSK 0x80000000
61026 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field value. */
61027 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_CLR_MSK 0x7fffffff
61028 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field. */
61029 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_RESET 0x0
61030 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE field value from a register. */
61031 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
61032 /* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field value suitable for setting the register. */
61033 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
61034 
61035 #ifndef __ASSEMBLY__
61036 /*
61037  * WARNING: The C register and register group struct declarations are provided for
61038  * convenience and illustrative purposes. They should, however, be used with
61039  * caution as the C language standard provides no guarantees about the alignment or
61040  * atomicity of device memory accesses. The recommended practice for writing
61041  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
61042  * alt_write_word() functions.
61043  *
61044  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR97_HIGH.
61045  */
61046 struct ALT_EMAC_GMAC_MAC_ADDR97_HIGH_s
61047 {
61048  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI */
61049  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR97_HIGH_RSVD_30_16 */
61050  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE */
61051 };
61052 
61053 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR97_HIGH. */
61054 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR97_HIGH_s ALT_EMAC_GMAC_MAC_ADDR97_HIGH_t;
61055 #endif /* __ASSEMBLY__ */
61056 
61057 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH register. */
61058 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_RESET 0x0000ffff
61059 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH register from the beginning of the component. */
61060 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_OFST 0xa88
61061 /* The address of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH register. */
61062 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR97_HIGH_OFST))
61063 
61064 /*
61065  * Register : gmacgrp_mac_address97_low
61066  *
61067  * <b> Register 675 (MAC Address97 Low Register)</b>
61068  *
61069  * The MAC Address97 Low register holds the lower 32 bits of the 98th 6-byte MAC
61070  * address of the station.
61071  *
61072  * Register Layout
61073  *
61074  * Bits | Access | Reset | Description
61075  * :-------|:-------|:-----------|:------------------------------------
61076  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO
61077  *
61078  */
61079 /*
61080  * Field : addrlo
61081  *
61082  * MAC Address97 [31:0]
61083  *
61084  * This field contains the lower 32 bits of the 98th 6-byte MAC address. The
61085  * content of this field is undefined until loaded by the Application after the
61086  * initialization process.
61087  *
61088  * Field Access Macros:
61089  *
61090  */
61091 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field. */
61092 #define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_LSB 0
61093 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field. */
61094 #define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_MSB 31
61095 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field. */
61096 #define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_WIDTH 32
61097 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field value. */
61098 #define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_SET_MSK 0xffffffff
61099 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field value. */
61100 #define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_CLR_MSK 0x00000000
61101 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field. */
61102 #define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_RESET 0xffffffff
61103 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO field value from a register. */
61104 #define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
61105 /* Produces a ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field value suitable for setting the register. */
61106 #define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
61107 
61108 #ifndef __ASSEMBLY__
61109 /*
61110  * WARNING: The C register and register group struct declarations are provided for
61111  * convenience and illustrative purposes. They should, however, be used with
61112  * caution as the C language standard provides no guarantees about the alignment or
61113  * atomicity of device memory accesses. The recommended practice for writing
61114  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
61115  * alt_write_word() functions.
61116  *
61117  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR97_LOW.
61118  */
61119 struct ALT_EMAC_GMAC_MAC_ADDR97_LOW_s
61120 {
61121  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO */
61122 };
61123 
61124 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR97_LOW. */
61125 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR97_LOW_s ALT_EMAC_GMAC_MAC_ADDR97_LOW_t;
61126 #endif /* __ASSEMBLY__ */
61127 
61128 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_LOW register. */
61129 #define ALT_EMAC_GMAC_MAC_ADDR97_LOW_RESET 0xffffffff
61130 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR97_LOW register from the beginning of the component. */
61131 #define ALT_EMAC_GMAC_MAC_ADDR97_LOW_OFST 0xa8c
61132 /* The address of the ALT_EMAC_GMAC_MAC_ADDR97_LOW register. */
61133 #define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR97_LOW_OFST))
61134 
61135 /*
61136  * Register : gmacgrp_mac_address98_high
61137  *
61138  * <b> Register 676 (MAC Address98 High Register)</b>
61139  *
61140  * The MAC Address99 High register holds the upper 16 bits of the 100th 6-byte MAC
61141  * address of the station.
61142  *
61143  * If the MAC address registers are configured to be double-synchronized to the
61144  * (G)MII clock domains, then
61145  *
61146  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
61147  * or Bits[7:0] (in big-endian mode) of the MAC Address99 Low Register are written.
61148  * For proper synchronization updates, consecutive writes to this MAC Address99 Low
61149  * Register must be performed after at least four clock cycles in the destination
61150  * clock domain.
61151  *
61152  * Register Layout
61153  *
61154  * Bits | Access | Reset | Description
61155  * :--------|:-------|:-------|:-----------------------------------------
61156  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI
61157  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR98_HIGH_RSVD_30_16
61158  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE
61159  *
61160  */
61161 /*
61162  * Field : addrhi
61163  *
61164  * MAC Address98 [47:32]
61165  *
61166  * This field contains the upper 16 bits (47:32) of the 99th 6-byte MAC address.
61167  *
61168  * Field Access Macros:
61169  *
61170  */
61171 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field. */
61172 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_LSB 0
61173 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field. */
61174 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_MSB 15
61175 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field. */
61176 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_WIDTH 16
61177 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field value. */
61178 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_SET_MSK 0x0000ffff
61179 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field value. */
61180 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_CLR_MSK 0xffff0000
61181 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field. */
61182 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_RESET 0xffff
61183 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI field value from a register. */
61184 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
61185 /* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field value suitable for setting the register. */
61186 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
61187 
61188 /*
61189  * Field : reserved_30_16
61190  *
61191  * Reserved
61192  *
61193  * Field Access Macros:
61194  *
61195  */
61196 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_RSVD_30_16 register field. */
61197 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_RSVD_30_16_LSB 16
61198 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_RSVD_30_16 register field. */
61199 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_RSVD_30_16_MSB 30
61200 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_RSVD_30_16 register field. */
61201 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_RSVD_30_16_WIDTH 15
61202 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_RSVD_30_16 register field value. */
61203 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
61204 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_RSVD_30_16 register field value. */
61205 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
61206 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_RSVD_30_16 register field. */
61207 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_RSVD_30_16_RESET 0x0
61208 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_RSVD_30_16 field value from a register. */
61209 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
61210 /* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_RSVD_30_16 register field value suitable for setting the register. */
61211 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
61212 
61213 /*
61214  * Field : ae
61215  *
61216  * Address Enable
61217  *
61218  * When this bit is set, the address filter module uses the 99th MAC address for
61219  * perfect filtering.
61220  *
61221  * When this bit is reset, the address filter module ignores the address for
61222  * filtering.
61223  *
61224  * Field Enumeration Values:
61225  *
61226  * Enum | Value | Description
61227  * :----------------------------------------|:------|:------------
61228  * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_E_DISD | 0x0 |
61229  * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_E_END | 0x1 |
61230  *
61231  * Field Access Macros:
61232  *
61233  */
61234 /*
61235  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE
61236  *
61237  */
61238 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_E_DISD 0x0
61239 /*
61240  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE
61241  *
61242  */
61243 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_E_END 0x1
61244 
61245 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field. */
61246 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_LSB 31
61247 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field. */
61248 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_MSB 31
61249 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field. */
61250 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_WIDTH 1
61251 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field value. */
61252 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_SET_MSK 0x80000000
61253 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field value. */
61254 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_CLR_MSK 0x7fffffff
61255 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field. */
61256 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_RESET 0x0
61257 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE field value from a register. */
61258 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
61259 /* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field value suitable for setting the register. */
61260 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
61261 
61262 #ifndef __ASSEMBLY__
61263 /*
61264  * WARNING: The C register and register group struct declarations are provided for
61265  * convenience and illustrative purposes. They should, however, be used with
61266  * caution as the C language standard provides no guarantees about the alignment or
61267  * atomicity of device memory accesses. The recommended practice for writing
61268  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
61269  * alt_write_word() functions.
61270  *
61271  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR98_HIGH.
61272  */
61273 struct ALT_EMAC_GMAC_MAC_ADDR98_HIGH_s
61274 {
61275  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI */
61276  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR98_HIGH_RSVD_30_16 */
61277  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE */
61278 };
61279 
61280 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR98_HIGH. */
61281 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR98_HIGH_s ALT_EMAC_GMAC_MAC_ADDR98_HIGH_t;
61282 #endif /* __ASSEMBLY__ */
61283 
61284 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH register. */
61285 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_RESET 0x0000ffff
61286 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH register from the beginning of the component. */
61287 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_OFST 0xa90
61288 /* The address of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH register. */
61289 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR98_HIGH_OFST))
61290 
61291 /*
61292  * Register : gmacgrp_mac_address98_low
61293  *
61294  * <b> Register 677 (MAC Address98 Low Register)</b>
61295  *
61296  * The MAC Address98 Low register holds the lower 32 bits of the 99th 6-byte MAC
61297  * address of the station.
61298  *
61299  * Register Layout
61300  *
61301  * Bits | Access | Reset | Description
61302  * :-------|:-------|:-----------|:------------------------------------
61303  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO
61304  *
61305  */
61306 /*
61307  * Field : addrlo
61308  *
61309  * MAC Address98 [31:0]
61310  *
61311  * This field contains the lower 32 bits of the 99th 6-byte MAC address. The
61312  * content of this field is undefined until loaded by the Application after the
61313  * initialization process.
61314  *
61315  * Field Access Macros:
61316  *
61317  */
61318 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field. */
61319 #define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_LSB 0
61320 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field. */
61321 #define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_MSB 31
61322 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field. */
61323 #define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_WIDTH 32
61324 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field value. */
61325 #define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_SET_MSK 0xffffffff
61326 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field value. */
61327 #define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_CLR_MSK 0x00000000
61328 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field. */
61329 #define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_RESET 0xffffffff
61330 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO field value from a register. */
61331 #define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
61332 /* Produces a ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field value suitable for setting the register. */
61333 #define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
61334 
61335 #ifndef __ASSEMBLY__
61336 /*
61337  * WARNING: The C register and register group struct declarations are provided for
61338  * convenience and illustrative purposes. They should, however, be used with
61339  * caution as the C language standard provides no guarantees about the alignment or
61340  * atomicity of device memory accesses. The recommended practice for writing
61341  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
61342  * alt_write_word() functions.
61343  *
61344  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR98_LOW.
61345  */
61346 struct ALT_EMAC_GMAC_MAC_ADDR98_LOW_s
61347 {
61348  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO */
61349 };
61350 
61351 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR98_LOW. */
61352 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR98_LOW_s ALT_EMAC_GMAC_MAC_ADDR98_LOW_t;
61353 #endif /* __ASSEMBLY__ */
61354 
61355 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_LOW register. */
61356 #define ALT_EMAC_GMAC_MAC_ADDR98_LOW_RESET 0xffffffff
61357 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR98_LOW register from the beginning of the component. */
61358 #define ALT_EMAC_GMAC_MAC_ADDR98_LOW_OFST 0xa94
61359 /* The address of the ALT_EMAC_GMAC_MAC_ADDR98_LOW register. */
61360 #define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR98_LOW_OFST))
61361 
61362 /*
61363  * Register : gmacgrp_mac_address99_high
61364  *
61365  * <b> Register 678 (MAC Address99 High Register)</b>
61366  *
61367  * The MAC Address99 High register holds the upper 16 bits of the 6-byte 100th MAC
61368  * address of the station. If the MAC address registers are configured to be
61369  * double-synchronized to the (G)MII clock domains, then the synchronization is
61370  * triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
61371  * endian mode) of the MAC Address99 Low Register are written. For proper
61372  * synchronization updates, consecutive writes to this MAC Address99 Low Register
61373  * must be performed after at least four clock cycles in the destination clock
61374  * domain.
61375  *
61376  * Register Layout
61377  *
61378  * Bits | Access | Reset | Description
61379  * :--------|:-------|:-------|:-----------------------------------------
61380  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI
61381  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR99_HIGH_RSVD_30_16
61382  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE
61383  *
61384  */
61385 /*
61386  * Field : addrhi
61387  *
61388  * MAC Address99 [47:32]
61389  *
61390  * This field contains the upper 16 bits (47:32) of the 100th 6-byte MAC address.
61391  *
61392  * Field Access Macros:
61393  *
61394  */
61395 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field. */
61396 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_LSB 0
61397 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field. */
61398 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_MSB 15
61399 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field. */
61400 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_WIDTH 16
61401 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field value. */
61402 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_SET_MSK 0x0000ffff
61403 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field value. */
61404 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_CLR_MSK 0xffff0000
61405 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field. */
61406 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_RESET 0xffff
61407 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI field value from a register. */
61408 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
61409 /* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field value suitable for setting the register. */
61410 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
61411 
61412 /*
61413  * Field : reserved_30_16
61414  *
61415  * Reserved
61416  *
61417  * Field Access Macros:
61418  *
61419  */
61420 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_RSVD_30_16 register field. */
61421 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_RSVD_30_16_LSB 16
61422 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_RSVD_30_16 register field. */
61423 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_RSVD_30_16_MSB 30
61424 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_RSVD_30_16 register field. */
61425 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_RSVD_30_16_WIDTH 15
61426 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_RSVD_30_16 register field value. */
61427 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
61428 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_RSVD_30_16 register field value. */
61429 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
61430 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_RSVD_30_16 register field. */
61431 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_RSVD_30_16_RESET 0x0
61432 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_RSVD_30_16 field value from a register. */
61433 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
61434 /* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_RSVD_30_16 register field value suitable for setting the register. */
61435 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
61436 
61437 /*
61438  * Field : ae
61439  *
61440  * Address Enable
61441  *
61442  * When this bit is set, the address filter module uses the 100th MAC address for
61443  * perfect filtering.
61444  *
61445  * When this bit is reset, the address filter module ignores the address for
61446  * filtering.
61447  *
61448  * Field Enumeration Values:
61449  *
61450  * Enum | Value | Description
61451  * :----------------------------------------|:------|:------------
61452  * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_E_DISD | 0x0 |
61453  * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_E_END | 0x1 |
61454  *
61455  * Field Access Macros:
61456  *
61457  */
61458 /*
61459  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE
61460  *
61461  */
61462 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_E_DISD 0x0
61463 /*
61464  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE
61465  *
61466  */
61467 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_E_END 0x1
61468 
61469 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field. */
61470 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_LSB 31
61471 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field. */
61472 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_MSB 31
61473 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field. */
61474 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_WIDTH 1
61475 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field value. */
61476 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_SET_MSK 0x80000000
61477 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field value. */
61478 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_CLR_MSK 0x7fffffff
61479 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field. */
61480 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_RESET 0x0
61481 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE field value from a register. */
61482 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
61483 /* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field value suitable for setting the register. */
61484 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
61485 
61486 #ifndef __ASSEMBLY__
61487 /*
61488  * WARNING: The C register and register group struct declarations are provided for
61489  * convenience and illustrative purposes. They should, however, be used with
61490  * caution as the C language standard provides no guarantees about the alignment or
61491  * atomicity of device memory accesses. The recommended practice for writing
61492  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
61493  * alt_write_word() functions.
61494  *
61495  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR99_HIGH.
61496  */
61497 struct ALT_EMAC_GMAC_MAC_ADDR99_HIGH_s
61498 {
61499  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI */
61500  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR99_HIGH_RSVD_30_16 */
61501  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE */
61502 };
61503 
61504 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR99_HIGH. */
61505 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR99_HIGH_s ALT_EMAC_GMAC_MAC_ADDR99_HIGH_t;
61506 #endif /* __ASSEMBLY__ */
61507 
61508 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH register. */
61509 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_RESET 0x0000ffff
61510 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH register from the beginning of the component. */
61511 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_OFST 0xa98
61512 /* The address of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH register. */
61513 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR99_HIGH_OFST))
61514 
61515 /*
61516  * Register : gmacgrp_mac_address99_low
61517  *
61518  * <b> Register 679 (MAC Address99 Low Register)</b>
61519  *
61520  * The MAC Address99 Low register holds the lower 32 bits of the 100th 6-byte MAC
61521  * address of the station.
61522  *
61523  * Register Layout
61524  *
61525  * Bits | Access | Reset | Description
61526  * :-------|:-------|:-----------|:------------------------------------
61527  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO
61528  *
61529  */
61530 /*
61531  * Field : addrlo
61532  *
61533  * MAC Address99 [31:0]
61534  *
61535  * This field contains the lower 32 bits of the 100th 6-byte MAC address. The
61536  * content of this field is undefined until loaded by the Application after the
61537  * initialization process.
61538  *
61539  * Field Access Macros:
61540  *
61541  */
61542 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field. */
61543 #define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_LSB 0
61544 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field. */
61545 #define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_MSB 31
61546 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field. */
61547 #define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_WIDTH 32
61548 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field value. */
61549 #define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_SET_MSK 0xffffffff
61550 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field value. */
61551 #define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_CLR_MSK 0x00000000
61552 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field. */
61553 #define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_RESET 0xffffffff
61554 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO field value from a register. */
61555 #define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
61556 /* Produces a ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field value suitable for setting the register. */
61557 #define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
61558 
61559 #ifndef __ASSEMBLY__
61560 /*
61561  * WARNING: The C register and register group struct declarations are provided for
61562  * convenience and illustrative purposes. They should, however, be used with
61563  * caution as the C language standard provides no guarantees about the alignment or
61564  * atomicity of device memory accesses. The recommended practice for writing
61565  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
61566  * alt_write_word() functions.
61567  *
61568  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR99_LOW.
61569  */
61570 struct ALT_EMAC_GMAC_MAC_ADDR99_LOW_s
61571 {
61572  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO */
61573 };
61574 
61575 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR99_LOW. */
61576 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR99_LOW_s ALT_EMAC_GMAC_MAC_ADDR99_LOW_t;
61577 #endif /* __ASSEMBLY__ */
61578 
61579 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_LOW register. */
61580 #define ALT_EMAC_GMAC_MAC_ADDR99_LOW_RESET 0xffffffff
61581 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR99_LOW register from the beginning of the component. */
61582 #define ALT_EMAC_GMAC_MAC_ADDR99_LOW_OFST 0xa9c
61583 /* The address of the ALT_EMAC_GMAC_MAC_ADDR99_LOW register. */
61584 #define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR99_LOW_OFST))
61585 
61586 /*
61587  * Register : gmacgrp_mac_address100_high
61588  *
61589  * <b> Register 680 (MAC Address100 High Register)</b>
61590  *
61591  * The MAC Address100 High register holds the upper 16 bits of the 101th 6-byte MAC
61592  * address of the station.
61593  *
61594  * If the MAC address registers are configured to be double-synchronized to the
61595  * (G)MII clock domains, then
61596  *
61597  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
61598  * or Bits[7:0] (in big-endian mode) of the MAC Address100 Low Register are
61599  * written. For proper synchronization updates, consecutive writes to this MAC
61600  * Address100 Low Register must be performed after at least four clock cycles in
61601  * the destination clock domain.
61602  *
61603  * Register Layout
61604  *
61605  * Bits | Access | Reset | Description
61606  * :--------|:-------|:-------|:------------------------------------------
61607  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI
61608  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR100_HIGH_RSVD_30_16
61609  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE
61610  *
61611  */
61612 /*
61613  * Field : addrhi
61614  *
61615  * MAC Address100 [47:32]
61616  *
61617  * This field contains the upper 16 bits (47:32) of the 101th 6-byte MAC address.
61618  *
61619  * Field Access Macros:
61620  *
61621  */
61622 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field. */
61623 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_LSB 0
61624 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field. */
61625 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_MSB 15
61626 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field. */
61627 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_WIDTH 16
61628 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field value. */
61629 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_SET_MSK 0x0000ffff
61630 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field value. */
61631 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_CLR_MSK 0xffff0000
61632 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field. */
61633 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_RESET 0xffff
61634 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI field value from a register. */
61635 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
61636 /* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field value suitable for setting the register. */
61637 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
61638 
61639 /*
61640  * Field : reserved_30_16
61641  *
61642  * Reserved
61643  *
61644  * Field Access Macros:
61645  *
61646  */
61647 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_RSVD_30_16 register field. */
61648 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_RSVD_30_16_LSB 16
61649 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_RSVD_30_16 register field. */
61650 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_RSVD_30_16_MSB 30
61651 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_RSVD_30_16 register field. */
61652 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_RSVD_30_16_WIDTH 15
61653 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_RSVD_30_16 register field value. */
61654 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
61655 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_RSVD_30_16 register field value. */
61656 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
61657 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_RSVD_30_16 register field. */
61658 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_RSVD_30_16_RESET 0x0
61659 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_RSVD_30_16 field value from a register. */
61660 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
61661 /* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_RSVD_30_16 register field value suitable for setting the register. */
61662 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
61663 
61664 /*
61665  * Field : ae
61666  *
61667  * Address Enable
61668  *
61669  * When this bit is set, the address filter module uses the 101th MAC address for
61670  * perfect filtering.
61671  *
61672  * When this bit is reset, the address filter module ignores the address for
61673  * filtering.
61674  *
61675  * Field Enumeration Values:
61676  *
61677  * Enum | Value | Description
61678  * :-----------------------------------------|:------|:------------
61679  * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_E_DISD | 0x0 |
61680  * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_E_END | 0x1 |
61681  *
61682  * Field Access Macros:
61683  *
61684  */
61685 /*
61686  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE
61687  *
61688  */
61689 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_E_DISD 0x0
61690 /*
61691  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE
61692  *
61693  */
61694 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_E_END 0x1
61695 
61696 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field. */
61697 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_LSB 31
61698 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field. */
61699 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_MSB 31
61700 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field. */
61701 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_WIDTH 1
61702 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field value. */
61703 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_SET_MSK 0x80000000
61704 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field value. */
61705 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_CLR_MSK 0x7fffffff
61706 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field. */
61707 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_RESET 0x0
61708 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE field value from a register. */
61709 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
61710 /* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field value suitable for setting the register. */
61711 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
61712 
61713 #ifndef __ASSEMBLY__
61714 /*
61715  * WARNING: The C register and register group struct declarations are provided for
61716  * convenience and illustrative purposes. They should, however, be used with
61717  * caution as the C language standard provides no guarantees about the alignment or
61718  * atomicity of device memory accesses. The recommended practice for writing
61719  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
61720  * alt_write_word() functions.
61721  *
61722  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR100_HIGH.
61723  */
61724 struct ALT_EMAC_GMAC_MAC_ADDR100_HIGH_s
61725 {
61726  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI */
61727  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR100_HIGH_RSVD_30_16 */
61728  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE */
61729 };
61730 
61731 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR100_HIGH. */
61732 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR100_HIGH_s ALT_EMAC_GMAC_MAC_ADDR100_HIGH_t;
61733 #endif /* __ASSEMBLY__ */
61734 
61735 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH register. */
61736 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_RESET 0x0000ffff
61737 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH register from the beginning of the component. */
61738 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_OFST 0xaa0
61739 /* The address of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH register. */
61740 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR100_HIGH_OFST))
61741 
61742 /*
61743  * Register : gmacgrp_mac_address100_low
61744  *
61745  * <b> Register 681 (MAC Address100 Low Register)</b>
61746  *
61747  * The MAC Address100 Low register holds the lower 32 bits of the 101th 6-byte MAC
61748  * address of the station.
61749  *
61750  * Register Layout
61751  *
61752  * Bits | Access | Reset | Description
61753  * :-------|:-------|:-----------|:-------------------------------------
61754  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO
61755  *
61756  */
61757 /*
61758  * Field : addrlo
61759  *
61760  * MAC Address100 [31:0]
61761  *
61762  * This field contains the lower 32 bits of the 101th 6-byte MAC address. The
61763  * content of this field is undefined until loaded by the Application after the
61764  * initialization process.
61765  *
61766  * Field Access Macros:
61767  *
61768  */
61769 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field. */
61770 #define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_LSB 0
61771 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field. */
61772 #define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_MSB 31
61773 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field. */
61774 #define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_WIDTH 32
61775 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field value. */
61776 #define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_SET_MSK 0xffffffff
61777 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field value. */
61778 #define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_CLR_MSK 0x00000000
61779 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field. */
61780 #define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_RESET 0xffffffff
61781 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO field value from a register. */
61782 #define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
61783 /* Produces a ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field value suitable for setting the register. */
61784 #define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
61785 
61786 #ifndef __ASSEMBLY__
61787 /*
61788  * WARNING: The C register and register group struct declarations are provided for
61789  * convenience and illustrative purposes. They should, however, be used with
61790  * caution as the C language standard provides no guarantees about the alignment or
61791  * atomicity of device memory accesses. The recommended practice for writing
61792  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
61793  * alt_write_word() functions.
61794  *
61795  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR100_LOW.
61796  */
61797 struct ALT_EMAC_GMAC_MAC_ADDR100_LOW_s
61798 {
61799  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO */
61800 };
61801 
61802 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR100_LOW. */
61803 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR100_LOW_s ALT_EMAC_GMAC_MAC_ADDR100_LOW_t;
61804 #endif /* __ASSEMBLY__ */
61805 
61806 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_LOW register. */
61807 #define ALT_EMAC_GMAC_MAC_ADDR100_LOW_RESET 0xffffffff
61808 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR100_LOW register from the beginning of the component. */
61809 #define ALT_EMAC_GMAC_MAC_ADDR100_LOW_OFST 0xaa4
61810 /* The address of the ALT_EMAC_GMAC_MAC_ADDR100_LOW register. */
61811 #define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR100_LOW_OFST))
61812 
61813 /*
61814  * Register : gmacgrp_mac_address101_high
61815  *
61816  * <b> Register 682 (MAC Address101 High Register)</b>
61817  *
61818  * The MAC Address101 High register holds the upper 16 bits of the 102nd 6-byte MAC
61819  * address of the station.
61820  *
61821  * If the MAC address registers are configured to be double-synchronized to the
61822  * (G)MII clock domains, then
61823  *
61824  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
61825  * or Bits[7:0] (in big-endian mode) of the MAC Address101 Low Register are
61826  * written. For proper synchronization updates, consecutive writes to this MAC
61827  * Address101 Low Register must be performed after at least four clock cycles in
61828  * the destination clock domain.
61829  *
61830  * Register Layout
61831  *
61832  * Bits | Access | Reset | Description
61833  * :--------|:-------|:-------|:------------------------------------------
61834  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI
61835  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR101_HIGH_RSVD_30_16
61836  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE
61837  *
61838  */
61839 /*
61840  * Field : addrhi
61841  *
61842  * MAC Address101 [47:32]
61843  *
61844  * This field contains the upper 16 bits (47:32) of the 102nd 6-byte MAC address.
61845  *
61846  * Field Access Macros:
61847  *
61848  */
61849 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field. */
61850 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_LSB 0
61851 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field. */
61852 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_MSB 15
61853 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field. */
61854 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_WIDTH 16
61855 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field value. */
61856 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_SET_MSK 0x0000ffff
61857 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field value. */
61858 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_CLR_MSK 0xffff0000
61859 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field. */
61860 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_RESET 0xffff
61861 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI field value from a register. */
61862 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
61863 /* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field value suitable for setting the register. */
61864 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
61865 
61866 /*
61867  * Field : reserved_30_16
61868  *
61869  * Reserved
61870  *
61871  * Field Access Macros:
61872  *
61873  */
61874 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_RSVD_30_16 register field. */
61875 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_RSVD_30_16_LSB 16
61876 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_RSVD_30_16 register field. */
61877 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_RSVD_30_16_MSB 30
61878 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_RSVD_30_16 register field. */
61879 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_RSVD_30_16_WIDTH 15
61880 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_RSVD_30_16 register field value. */
61881 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
61882 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_RSVD_30_16 register field value. */
61883 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
61884 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_RSVD_30_16 register field. */
61885 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_RSVD_30_16_RESET 0x0
61886 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_RSVD_30_16 field value from a register. */
61887 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
61888 /* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_RSVD_30_16 register field value suitable for setting the register. */
61889 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
61890 
61891 /*
61892  * Field : ae
61893  *
61894  * Address Enable
61895  *
61896  * When this bit is set, the address filter module uses the 102nd MAC address for
61897  * perfect filtering.
61898  *
61899  * When this bit is reset, the address filter module ignores the address for
61900  * filtering.
61901  *
61902  * Field Enumeration Values:
61903  *
61904  * Enum | Value | Description
61905  * :-----------------------------------------|:------|:------------
61906  * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_E_DISD | 0x0 |
61907  * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_E_END | 0x1 |
61908  *
61909  * Field Access Macros:
61910  *
61911  */
61912 /*
61913  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE
61914  *
61915  */
61916 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_E_DISD 0x0
61917 /*
61918  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE
61919  *
61920  */
61921 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_E_END 0x1
61922 
61923 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field. */
61924 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_LSB 31
61925 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field. */
61926 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_MSB 31
61927 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field. */
61928 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_WIDTH 1
61929 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field value. */
61930 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_SET_MSK 0x80000000
61931 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field value. */
61932 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_CLR_MSK 0x7fffffff
61933 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field. */
61934 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_RESET 0x0
61935 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE field value from a register. */
61936 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
61937 /* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field value suitable for setting the register. */
61938 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
61939 
61940 #ifndef __ASSEMBLY__
61941 /*
61942  * WARNING: The C register and register group struct declarations are provided for
61943  * convenience and illustrative purposes. They should, however, be used with
61944  * caution as the C language standard provides no guarantees about the alignment or
61945  * atomicity of device memory accesses. The recommended practice for writing
61946  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
61947  * alt_write_word() functions.
61948  *
61949  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR101_HIGH.
61950  */
61951 struct ALT_EMAC_GMAC_MAC_ADDR101_HIGH_s
61952 {
61953  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI */
61954  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR101_HIGH_RSVD_30_16 */
61955  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE */
61956 };
61957 
61958 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR101_HIGH. */
61959 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR101_HIGH_s ALT_EMAC_GMAC_MAC_ADDR101_HIGH_t;
61960 #endif /* __ASSEMBLY__ */
61961 
61962 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH register. */
61963 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_RESET 0x0000ffff
61964 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH register from the beginning of the component. */
61965 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_OFST 0xaa8
61966 /* The address of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH register. */
61967 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR101_HIGH_OFST))
61968 
61969 /*
61970  * Register : gmacgrp_mac_address101_low
61971  *
61972  * <b> Register 683 (MAC Address101 Low Register)</b>
61973  *
61974  * The MAC Address101 Low register holds the lower 32 bits of the 102nd 6-byte MAC
61975  * address of the station.
61976  *
61977  * Register Layout
61978  *
61979  * Bits | Access | Reset | Description
61980  * :-------|:-------|:-----------|:-------------------------------------
61981  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO
61982  *
61983  */
61984 /*
61985  * Field : addrlo
61986  *
61987  * MAC Address101 [31:0]
61988  *
61989  * This field contains the lower 32 bits of the 102nd 6-byte MAC address. The
61990  * content of this field is undefined until loaded by the Application after the
61991  * initialization process.
61992  *
61993  * Field Access Macros:
61994  *
61995  */
61996 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field. */
61997 #define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_LSB 0
61998 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field. */
61999 #define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_MSB 31
62000 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field. */
62001 #define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_WIDTH 32
62002 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field value. */
62003 #define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_SET_MSK 0xffffffff
62004 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field value. */
62005 #define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_CLR_MSK 0x00000000
62006 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field. */
62007 #define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_RESET 0xffffffff
62008 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO field value from a register. */
62009 #define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
62010 /* Produces a ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field value suitable for setting the register. */
62011 #define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
62012 
62013 #ifndef __ASSEMBLY__
62014 /*
62015  * WARNING: The C register and register group struct declarations are provided for
62016  * convenience and illustrative purposes. They should, however, be used with
62017  * caution as the C language standard provides no guarantees about the alignment or
62018  * atomicity of device memory accesses. The recommended practice for writing
62019  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
62020  * alt_write_word() functions.
62021  *
62022  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR101_LOW.
62023  */
62024 struct ALT_EMAC_GMAC_MAC_ADDR101_LOW_s
62025 {
62026  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO */
62027 };
62028 
62029 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR101_LOW. */
62030 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR101_LOW_s ALT_EMAC_GMAC_MAC_ADDR101_LOW_t;
62031 #endif /* __ASSEMBLY__ */
62032 
62033 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_LOW register. */
62034 #define ALT_EMAC_GMAC_MAC_ADDR101_LOW_RESET 0xffffffff
62035 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR101_LOW register from the beginning of the component. */
62036 #define ALT_EMAC_GMAC_MAC_ADDR101_LOW_OFST 0xaac
62037 /* The address of the ALT_EMAC_GMAC_MAC_ADDR101_LOW register. */
62038 #define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR101_LOW_OFST))
62039 
62040 /*
62041  * Register : gmacgrp_mac_address102_high
62042  *
62043  * <b> Register 684 (MAC Address102 High Register)</b>
62044  *
62045  * The MAC Address102 High register holds the upper 16 bits of the 6-byte 103rd MAC
62046  * address of the station.
62047  *
62048  * If the MAC address registers are configured to be double-synchronized to the
62049  * (G)MII clock domains, then
62050  *
62051  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
62052  * or Bits[7:0] (in big-endian mode) of the MAC Address102 Low Register are
62053  * written. For proper synchronization updates, consecutive writes to this MAC
62054  * Address102 Low Register must be performed after at least four clock cycles in
62055  * the destination clock domain.
62056  *
62057  * Register Layout
62058  *
62059  * Bits | Access | Reset | Description
62060  * :--------|:-------|:-------|:------------------------------------------
62061  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI
62062  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR102_HIGH_RSVD_30_16
62063  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE
62064  *
62065  */
62066 /*
62067  * Field : addrhi
62068  *
62069  * MAC Address102 [47:32]
62070  *
62071  * This field contains the upper 16 bits (47:32) of the 103rd 6-byte MAC address.
62072  *
62073  * Field Access Macros:
62074  *
62075  */
62076 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field. */
62077 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_LSB 0
62078 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field. */
62079 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_MSB 15
62080 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field. */
62081 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_WIDTH 16
62082 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field value. */
62083 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_SET_MSK 0x0000ffff
62084 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field value. */
62085 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_CLR_MSK 0xffff0000
62086 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field. */
62087 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_RESET 0xffff
62088 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI field value from a register. */
62089 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
62090 /* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field value suitable for setting the register. */
62091 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
62092 
62093 /*
62094  * Field : reserved_30_16
62095  *
62096  * Reserved
62097  *
62098  * Field Access Macros:
62099  *
62100  */
62101 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_RSVD_30_16 register field. */
62102 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_RSVD_30_16_LSB 16
62103 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_RSVD_30_16 register field. */
62104 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_RSVD_30_16_MSB 30
62105 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_RSVD_30_16 register field. */
62106 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_RSVD_30_16_WIDTH 15
62107 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_RSVD_30_16 register field value. */
62108 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
62109 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_RSVD_30_16 register field value. */
62110 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
62111 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_RSVD_30_16 register field. */
62112 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_RSVD_30_16_RESET 0x0
62113 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_RSVD_30_16 field value from a register. */
62114 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
62115 /* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_RSVD_30_16 register field value suitable for setting the register. */
62116 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
62117 
62118 /*
62119  * Field : ae
62120  *
62121  * Address Enable
62122  *
62123  * When this bit is set, the address filter module uses the 103rd MAC address for
62124  * perfect filtering.
62125  *
62126  * When this bit is reset, the address filter module ignores the address for
62127  * filtering.
62128  *
62129  * Field Enumeration Values:
62130  *
62131  * Enum | Value | Description
62132  * :-----------------------------------------|:------|:------------
62133  * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_E_DISD | 0x0 |
62134  * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_E_END | 0x1 |
62135  *
62136  * Field Access Macros:
62137  *
62138  */
62139 /*
62140  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE
62141  *
62142  */
62143 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_E_DISD 0x0
62144 /*
62145  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE
62146  *
62147  */
62148 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_E_END 0x1
62149 
62150 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field. */
62151 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_LSB 31
62152 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field. */
62153 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_MSB 31
62154 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field. */
62155 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_WIDTH 1
62156 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field value. */
62157 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_SET_MSK 0x80000000
62158 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field value. */
62159 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_CLR_MSK 0x7fffffff
62160 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field. */
62161 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_RESET 0x0
62162 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE field value from a register. */
62163 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
62164 /* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field value suitable for setting the register. */
62165 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
62166 
62167 #ifndef __ASSEMBLY__
62168 /*
62169  * WARNING: The C register and register group struct declarations are provided for
62170  * convenience and illustrative purposes. They should, however, be used with
62171  * caution as the C language standard provides no guarantees about the alignment or
62172  * atomicity of device memory accesses. The recommended practice for writing
62173  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
62174  * alt_write_word() functions.
62175  *
62176  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR102_HIGH.
62177  */
62178 struct ALT_EMAC_GMAC_MAC_ADDR102_HIGH_s
62179 {
62180  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI */
62181  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR102_HIGH_RSVD_30_16 */
62182  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE */
62183 };
62184 
62185 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR102_HIGH. */
62186 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR102_HIGH_s ALT_EMAC_GMAC_MAC_ADDR102_HIGH_t;
62187 #endif /* __ASSEMBLY__ */
62188 
62189 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH register. */
62190 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_RESET 0x0000ffff
62191 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH register from the beginning of the component. */
62192 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_OFST 0xab0
62193 /* The address of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH register. */
62194 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR102_HIGH_OFST))
62195 
62196 /*
62197  * Register : gmacgrp_mac_address102_low
62198  *
62199  * <b> Register 685 (MAC Address102 Low Register)</b>
62200  *
62201  * The MAC Address102 Low register holds the lower 32 bits of the 103rd 6-byte MAC
62202  * address of the station.
62203  *
62204  * Register Layout
62205  *
62206  * Bits | Access | Reset | Description
62207  * :-------|:-------|:-----------|:-------------------------------------
62208  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO
62209  *
62210  */
62211 /*
62212  * Field : addrlo
62213  *
62214  * MAC Address102 [31:0]
62215  *
62216  * This field contains the lower 32 bits of the 103rd 6-byte MAC address. The
62217  * content of this field is undefined until loaded by the Application after the
62218  * initialization process.
62219  *
62220  * Field Access Macros:
62221  *
62222  */
62223 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field. */
62224 #define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_LSB 0
62225 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field. */
62226 #define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_MSB 31
62227 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field. */
62228 #define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_WIDTH 32
62229 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field value. */
62230 #define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_SET_MSK 0xffffffff
62231 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field value. */
62232 #define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_CLR_MSK 0x00000000
62233 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field. */
62234 #define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_RESET 0xffffffff
62235 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO field value from a register. */
62236 #define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
62237 /* Produces a ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field value suitable for setting the register. */
62238 #define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
62239 
62240 #ifndef __ASSEMBLY__
62241 /*
62242  * WARNING: The C register and register group struct declarations are provided for
62243  * convenience and illustrative purposes. They should, however, be used with
62244  * caution as the C language standard provides no guarantees about the alignment or
62245  * atomicity of device memory accesses. The recommended practice for writing
62246  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
62247  * alt_write_word() functions.
62248  *
62249  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR102_LOW.
62250  */
62251 struct ALT_EMAC_GMAC_MAC_ADDR102_LOW_s
62252 {
62253  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO */
62254 };
62255 
62256 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR102_LOW. */
62257 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR102_LOW_s ALT_EMAC_GMAC_MAC_ADDR102_LOW_t;
62258 #endif /* __ASSEMBLY__ */
62259 
62260 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_LOW register. */
62261 #define ALT_EMAC_GMAC_MAC_ADDR102_LOW_RESET 0xffffffff
62262 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR102_LOW register from the beginning of the component. */
62263 #define ALT_EMAC_GMAC_MAC_ADDR102_LOW_OFST 0xab4
62264 /* The address of the ALT_EMAC_GMAC_MAC_ADDR102_LOW register. */
62265 #define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR102_LOW_OFST))
62266 
62267 /*
62268  * Register : gmacgrp_mac_address103_high
62269  *
62270  * <b> Register 686 (MAC Address103 High Register)</b>
62271  *
62272  * The MAC Address103 High register holds the upper 16 bits of the 6-byte 104th MAC
62273  * address of the station.
62274  *
62275  * If the MAC address registers are configured to be double-synchronized to the
62276  * (G)MII clock domains, then
62277  *
62278  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
62279  * or Bits[7:0] (in big-endian mode) of the MAC Address103 Low Register are
62280  * written. For proper synchronization updates, consecutive writes to this MAC
62281  * Address103 Low Register must be performed after at least four clock cycles in
62282  * the destination clock domain.
62283  *
62284  * Register Layout
62285  *
62286  * Bits | Access | Reset | Description
62287  * :--------|:-------|:-------|:------------------------------------------
62288  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI
62289  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR103_HIGH_RSVD_30_16
62290  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE
62291  *
62292  */
62293 /*
62294  * Field : addrhi
62295  *
62296  * MAC Address103 [47:32]
62297  *
62298  * This field contains the upper 16 bits (47:32) of the 104th 6-byte MAC address.
62299  *
62300  * Field Access Macros:
62301  *
62302  */
62303 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field. */
62304 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_LSB 0
62305 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field. */
62306 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_MSB 15
62307 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field. */
62308 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_WIDTH 16
62309 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field value. */
62310 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_SET_MSK 0x0000ffff
62311 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field value. */
62312 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_CLR_MSK 0xffff0000
62313 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field. */
62314 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_RESET 0xffff
62315 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI field value from a register. */
62316 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
62317 /* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field value suitable for setting the register. */
62318 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
62319 
62320 /*
62321  * Field : reserved_30_16
62322  *
62323  * Reserved
62324  *
62325  * Field Access Macros:
62326  *
62327  */
62328 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_RSVD_30_16 register field. */
62329 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_RSVD_30_16_LSB 16
62330 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_RSVD_30_16 register field. */
62331 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_RSVD_30_16_MSB 30
62332 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_RSVD_30_16 register field. */
62333 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_RSVD_30_16_WIDTH 15
62334 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_RSVD_30_16 register field value. */
62335 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
62336 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_RSVD_30_16 register field value. */
62337 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
62338 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_RSVD_30_16 register field. */
62339 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_RSVD_30_16_RESET 0x0
62340 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_RSVD_30_16 field value from a register. */
62341 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
62342 /* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_RSVD_30_16 register field value suitable for setting the register. */
62343 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
62344 
62345 /*
62346  * Field : ae
62347  *
62348  * Address Enable
62349  *
62350  * When this bit is set, the address filter module uses the 104th MAC address for
62351  * perfect filtering.
62352  *
62353  * When this bit is reset, the address filter module ignores the address for
62354  * filtering.
62355  *
62356  * Field Enumeration Values:
62357  *
62358  * Enum | Value | Description
62359  * :-----------------------------------------|:------|:------------
62360  * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_E_DISD | 0x0 |
62361  * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_E_END | 0x1 |
62362  *
62363  * Field Access Macros:
62364  *
62365  */
62366 /*
62367  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE
62368  *
62369  */
62370 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_E_DISD 0x0
62371 /*
62372  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE
62373  *
62374  */
62375 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_E_END 0x1
62376 
62377 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field. */
62378 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_LSB 31
62379 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field. */
62380 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_MSB 31
62381 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field. */
62382 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_WIDTH 1
62383 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field value. */
62384 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_SET_MSK 0x80000000
62385 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field value. */
62386 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_CLR_MSK 0x7fffffff
62387 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field. */
62388 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_RESET 0x0
62389 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE field value from a register. */
62390 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
62391 /* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field value suitable for setting the register. */
62392 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
62393 
62394 #ifndef __ASSEMBLY__
62395 /*
62396  * WARNING: The C register and register group struct declarations are provided for
62397  * convenience and illustrative purposes. They should, however, be used with
62398  * caution as the C language standard provides no guarantees about the alignment or
62399  * atomicity of device memory accesses. The recommended practice for writing
62400  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
62401  * alt_write_word() functions.
62402  *
62403  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR103_HIGH.
62404  */
62405 struct ALT_EMAC_GMAC_MAC_ADDR103_HIGH_s
62406 {
62407  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI */
62408  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR103_HIGH_RSVD_30_16 */
62409  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE */
62410 };
62411 
62412 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR103_HIGH. */
62413 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR103_HIGH_s ALT_EMAC_GMAC_MAC_ADDR103_HIGH_t;
62414 #endif /* __ASSEMBLY__ */
62415 
62416 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH register. */
62417 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_RESET 0x0000ffff
62418 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH register from the beginning of the component. */
62419 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_OFST 0xab8
62420 /* The address of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH register. */
62421 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR103_HIGH_OFST))
62422 
62423 /*
62424  * Register : gmacgrp_mac_address103_low
62425  *
62426  * <b> Register 687 (MAC Address103 Low Register)</b>
62427  *
62428  * The MAC Address103 Low register holds the lower 32 bits of the 104th 6-byte MAC
62429  * address of the station.
62430  *
62431  * Register Layout
62432  *
62433  * Bits | Access | Reset | Description
62434  * :-------|:-------|:-----------|:-------------------------------------
62435  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO
62436  *
62437  */
62438 /*
62439  * Field : addrlo
62440  *
62441  * MAC Address103 [31:0]
62442  *
62443  * This field contains the lower 32 bits of the 104th 6-byte MAC address. The
62444  * content of this field is undefined until loaded by the Application after the
62445  * initialization process.
62446  *
62447  * Field Access Macros:
62448  *
62449  */
62450 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field. */
62451 #define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_LSB 0
62452 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field. */
62453 #define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_MSB 31
62454 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field. */
62455 #define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_WIDTH 32
62456 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field value. */
62457 #define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_SET_MSK 0xffffffff
62458 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field value. */
62459 #define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_CLR_MSK 0x00000000
62460 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field. */
62461 #define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_RESET 0xffffffff
62462 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO field value from a register. */
62463 #define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
62464 /* Produces a ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field value suitable for setting the register. */
62465 #define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
62466 
62467 #ifndef __ASSEMBLY__
62468 /*
62469  * WARNING: The C register and register group struct declarations are provided for
62470  * convenience and illustrative purposes. They should, however, be used with
62471  * caution as the C language standard provides no guarantees about the alignment or
62472  * atomicity of device memory accesses. The recommended practice for writing
62473  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
62474  * alt_write_word() functions.
62475  *
62476  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR103_LOW.
62477  */
62478 struct ALT_EMAC_GMAC_MAC_ADDR103_LOW_s
62479 {
62480  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO */
62481 };
62482 
62483 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR103_LOW. */
62484 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR103_LOW_s ALT_EMAC_GMAC_MAC_ADDR103_LOW_t;
62485 #endif /* __ASSEMBLY__ */
62486 
62487 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_LOW register. */
62488 #define ALT_EMAC_GMAC_MAC_ADDR103_LOW_RESET 0xffffffff
62489 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR103_LOW register from the beginning of the component. */
62490 #define ALT_EMAC_GMAC_MAC_ADDR103_LOW_OFST 0xabc
62491 /* The address of the ALT_EMAC_GMAC_MAC_ADDR103_LOW register. */
62492 #define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR103_LOW_OFST))
62493 
62494 /*
62495  * Register : gmacgrp_mac_address104_high
62496  *
62497  * <b> Register 688 (MAC Address104 High Register)</b>
62498  *
62499  * The MAC Address104 High register holds the upper 16 bits of the 105th 6-byte MAC
62500  * address of the station.
62501  *
62502  * If the MAC address registers are configured to be double-synchronized to the
62503  * (G)MII clock domains, then
62504  *
62505  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
62506  * or Bits[7:0] (in big-endian mode) of the MAC Address104 Low Register are
62507  * written. For proper synchronization updates, consecutive writes to this MAC
62508  * Address104 Low Register must be performed after at least four clock cycles in
62509  * the destination clock domain.
62510  *
62511  * Register Layout
62512  *
62513  * Bits | Access | Reset | Description
62514  * :--------|:-------|:-------|:------------------------------------------
62515  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI
62516  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR104_HIGH_RSVD_30_16
62517  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE
62518  *
62519  */
62520 /*
62521  * Field : addrhi
62522  *
62523  * MAC Address104 [47:32]
62524  *
62525  * This field contains the upper 16 bits (47:32) of the 105th 6-byte MAC address.
62526  *
62527  * Field Access Macros:
62528  *
62529  */
62530 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field. */
62531 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_LSB 0
62532 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field. */
62533 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_MSB 15
62534 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field. */
62535 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_WIDTH 16
62536 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field value. */
62537 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_SET_MSK 0x0000ffff
62538 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field value. */
62539 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_CLR_MSK 0xffff0000
62540 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field. */
62541 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_RESET 0xffff
62542 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI field value from a register. */
62543 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
62544 /* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field value suitable for setting the register. */
62545 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
62546 
62547 /*
62548  * Field : reserved_30_16
62549  *
62550  * Reserved
62551  *
62552  * Field Access Macros:
62553  *
62554  */
62555 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_RSVD_30_16 register field. */
62556 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_RSVD_30_16_LSB 16
62557 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_RSVD_30_16 register field. */
62558 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_RSVD_30_16_MSB 30
62559 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_RSVD_30_16 register field. */
62560 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_RSVD_30_16_WIDTH 15
62561 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_RSVD_30_16 register field value. */
62562 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
62563 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_RSVD_30_16 register field value. */
62564 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
62565 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_RSVD_30_16 register field. */
62566 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_RSVD_30_16_RESET 0x0
62567 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_RSVD_30_16 field value from a register. */
62568 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
62569 /* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_RSVD_30_16 register field value suitable for setting the register. */
62570 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
62571 
62572 /*
62573  * Field : ae
62574  *
62575  * Address Enable
62576  *
62577  * When this bit is set, the address filter module uses the 105th MAC address for
62578  * perfect filtering.
62579  *
62580  * When this bit is reset, the address filter module ignores the address for
62581  * filtering.
62582  *
62583  * Field Enumeration Values:
62584  *
62585  * Enum | Value | Description
62586  * :-----------------------------------------|:------|:------------
62587  * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_E_DISD | 0x0 |
62588  * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_E_END | 0x1 |
62589  *
62590  * Field Access Macros:
62591  *
62592  */
62593 /*
62594  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE
62595  *
62596  */
62597 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_E_DISD 0x0
62598 /*
62599  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE
62600  *
62601  */
62602 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_E_END 0x1
62603 
62604 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field. */
62605 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_LSB 31
62606 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field. */
62607 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_MSB 31
62608 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field. */
62609 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_WIDTH 1
62610 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field value. */
62611 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_SET_MSK 0x80000000
62612 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field value. */
62613 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_CLR_MSK 0x7fffffff
62614 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field. */
62615 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_RESET 0x0
62616 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE field value from a register. */
62617 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
62618 /* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field value suitable for setting the register. */
62619 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
62620 
62621 #ifndef __ASSEMBLY__
62622 /*
62623  * WARNING: The C register and register group struct declarations are provided for
62624  * convenience and illustrative purposes. They should, however, be used with
62625  * caution as the C language standard provides no guarantees about the alignment or
62626  * atomicity of device memory accesses. The recommended practice for writing
62627  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
62628  * alt_write_word() functions.
62629  *
62630  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR104_HIGH.
62631  */
62632 struct ALT_EMAC_GMAC_MAC_ADDR104_HIGH_s
62633 {
62634  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI */
62635  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR104_HIGH_RSVD_30_16 */
62636  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE */
62637 };
62638 
62639 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR104_HIGH. */
62640 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR104_HIGH_s ALT_EMAC_GMAC_MAC_ADDR104_HIGH_t;
62641 #endif /* __ASSEMBLY__ */
62642 
62643 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH register. */
62644 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_RESET 0x0000ffff
62645 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH register from the beginning of the component. */
62646 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_OFST 0xac0
62647 /* The address of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH register. */
62648 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR104_HIGH_OFST))
62649 
62650 /*
62651  * Register : gmacgrp_mac_address104_low
62652  *
62653  * <b> Register 689 (MAC Address104 Low Register)</b>
62654  *
62655  * The MAC Address104 Low register holds the lower 32 bits of the 105th 6-byte MAC
62656  * address of the station.
62657  *
62658  * Register Layout
62659  *
62660  * Bits | Access | Reset | Description
62661  * :-------|:-------|:-----------|:-------------------------------------
62662  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO
62663  *
62664  */
62665 /*
62666  * Field : addrlo
62667  *
62668  * MAC Address104 [31:0]
62669  *
62670  * This field contains the lower 32 bits of the 105th 6-byte MAC address. The
62671  * content of this field is undefined until loaded by the Application after the
62672  * initialization process.
62673  *
62674  * Field Access Macros:
62675  *
62676  */
62677 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field. */
62678 #define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_LSB 0
62679 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field. */
62680 #define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_MSB 31
62681 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field. */
62682 #define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_WIDTH 32
62683 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field value. */
62684 #define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_SET_MSK 0xffffffff
62685 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field value. */
62686 #define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_CLR_MSK 0x00000000
62687 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field. */
62688 #define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_RESET 0xffffffff
62689 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO field value from a register. */
62690 #define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
62691 /* Produces a ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field value suitable for setting the register. */
62692 #define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
62693 
62694 #ifndef __ASSEMBLY__
62695 /*
62696  * WARNING: The C register and register group struct declarations are provided for
62697  * convenience and illustrative purposes. They should, however, be used with
62698  * caution as the C language standard provides no guarantees about the alignment or
62699  * atomicity of device memory accesses. The recommended practice for writing
62700  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
62701  * alt_write_word() functions.
62702  *
62703  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR104_LOW.
62704  */
62705 struct ALT_EMAC_GMAC_MAC_ADDR104_LOW_s
62706 {
62707  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO */
62708 };
62709 
62710 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR104_LOW. */
62711 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR104_LOW_s ALT_EMAC_GMAC_MAC_ADDR104_LOW_t;
62712 #endif /* __ASSEMBLY__ */
62713 
62714 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_LOW register. */
62715 #define ALT_EMAC_GMAC_MAC_ADDR104_LOW_RESET 0xffffffff
62716 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR104_LOW register from the beginning of the component. */
62717 #define ALT_EMAC_GMAC_MAC_ADDR104_LOW_OFST 0xac4
62718 /* The address of the ALT_EMAC_GMAC_MAC_ADDR104_LOW register. */
62719 #define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR104_LOW_OFST))
62720 
62721 /*
62722  * Register : gmacgrp_mac_address105_high
62723  *
62724  * <b> Register 690 (MAC Address105 High Register)</b>
62725  *
62726  * The MAC Address105 High register holds the upper 16 bits of the 106th 6-byte MAC
62727  * address of the station.
62728  *
62729  * If the MAC address registers are configured to be double-synchronized to the
62730  * (G)MII clock domains, then
62731  *
62732  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
62733  * or Bits[7:0] (in big-endian mode) of the MAC Address105 Low Register are
62734  * written. For proper synchronization updates, consecutive writes to this MAC
62735  * Address105 Low Register must be performed after at least four clock cycles in
62736  * the destination clock domain.
62737  *
62738  * Register Layout
62739  *
62740  * Bits | Access | Reset | Description
62741  * :--------|:-------|:-------|:------------------------------------------
62742  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI
62743  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR105_HIGH_RSVD_30_16
62744  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE
62745  *
62746  */
62747 /*
62748  * Field : addrhi
62749  *
62750  * MAC Address105 [47:32]
62751  *
62752  * This field contains the upper 16 bits (47:32) of the 106th 6-byte MAC address.
62753  *
62754  * Field Access Macros:
62755  *
62756  */
62757 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field. */
62758 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_LSB 0
62759 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field. */
62760 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_MSB 15
62761 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field. */
62762 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_WIDTH 16
62763 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field value. */
62764 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_SET_MSK 0x0000ffff
62765 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field value. */
62766 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_CLR_MSK 0xffff0000
62767 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field. */
62768 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_RESET 0xffff
62769 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI field value from a register. */
62770 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
62771 /* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field value suitable for setting the register. */
62772 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
62773 
62774 /*
62775  * Field : reserved_30_16
62776  *
62777  * Reserved
62778  *
62779  * Field Access Macros:
62780  *
62781  */
62782 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_RSVD_30_16 register field. */
62783 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_RSVD_30_16_LSB 16
62784 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_RSVD_30_16 register field. */
62785 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_RSVD_30_16_MSB 30
62786 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_RSVD_30_16 register field. */
62787 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_RSVD_30_16_WIDTH 15
62788 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_RSVD_30_16 register field value. */
62789 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
62790 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_RSVD_30_16 register field value. */
62791 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
62792 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_RSVD_30_16 register field. */
62793 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_RSVD_30_16_RESET 0x0
62794 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_RSVD_30_16 field value from a register. */
62795 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
62796 /* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_RSVD_30_16 register field value suitable for setting the register. */
62797 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
62798 
62799 /*
62800  * Field : ae
62801  *
62802  * Address Enable
62803  *
62804  * When this bit is set, the address filter module uses the 106th MAC address for
62805  * perfect filtering.
62806  *
62807  * When this bit is reset, the address filter module ignores the address for
62808  * filtering.
62809  *
62810  * Field Enumeration Values:
62811  *
62812  * Enum | Value | Description
62813  * :-----------------------------------------|:------|:------------
62814  * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_E_DISD | 0x0 |
62815  * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_E_END | 0x1 |
62816  *
62817  * Field Access Macros:
62818  *
62819  */
62820 /*
62821  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE
62822  *
62823  */
62824 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_E_DISD 0x0
62825 /*
62826  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE
62827  *
62828  */
62829 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_E_END 0x1
62830 
62831 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field. */
62832 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_LSB 31
62833 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field. */
62834 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_MSB 31
62835 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field. */
62836 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_WIDTH 1
62837 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field value. */
62838 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_SET_MSK 0x80000000
62839 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field value. */
62840 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_CLR_MSK 0x7fffffff
62841 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field. */
62842 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_RESET 0x0
62843 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE field value from a register. */
62844 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
62845 /* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field value suitable for setting the register. */
62846 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
62847 
62848 #ifndef __ASSEMBLY__
62849 /*
62850  * WARNING: The C register and register group struct declarations are provided for
62851  * convenience and illustrative purposes. They should, however, be used with
62852  * caution as the C language standard provides no guarantees about the alignment or
62853  * atomicity of device memory accesses. The recommended practice for writing
62854  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
62855  * alt_write_word() functions.
62856  *
62857  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR105_HIGH.
62858  */
62859 struct ALT_EMAC_GMAC_MAC_ADDR105_HIGH_s
62860 {
62861  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI */
62862  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR105_HIGH_RSVD_30_16 */
62863  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE */
62864 };
62865 
62866 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR105_HIGH. */
62867 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR105_HIGH_s ALT_EMAC_GMAC_MAC_ADDR105_HIGH_t;
62868 #endif /* __ASSEMBLY__ */
62869 
62870 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH register. */
62871 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_RESET 0x0000ffff
62872 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH register from the beginning of the component. */
62873 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_OFST 0xac8
62874 /* The address of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH register. */
62875 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR105_HIGH_OFST))
62876 
62877 /*
62878  * Register : gmacgrp_mac_address105_low
62879  *
62880  * <b> Register 691 (MAC Address105 Low Register)</b>
62881  *
62882  * The MAC Address105 Low register holds the lower 32 bits of the 106th 6-byte MAC
62883  * address of the station.
62884  *
62885  * Register Layout
62886  *
62887  * Bits | Access | Reset | Description
62888  * :-------|:-------|:-----------|:-------------------------------------
62889  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO
62890  *
62891  */
62892 /*
62893  * Field : addrlo
62894  *
62895  * MAC Address105 [31:0]
62896  *
62897  * This field contains the lower 32 bits of the 106th 6-byte MAC address. The
62898  * content of this field is undefined until loaded by the Application after the
62899  * initialization process.
62900  *
62901  * Field Access Macros:
62902  *
62903  */
62904 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field. */
62905 #define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_LSB 0
62906 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field. */
62907 #define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_MSB 31
62908 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field. */
62909 #define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_WIDTH 32
62910 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field value. */
62911 #define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_SET_MSK 0xffffffff
62912 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field value. */
62913 #define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_CLR_MSK 0x00000000
62914 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field. */
62915 #define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_RESET 0xffffffff
62916 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO field value from a register. */
62917 #define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
62918 /* Produces a ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field value suitable for setting the register. */
62919 #define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
62920 
62921 #ifndef __ASSEMBLY__
62922 /*
62923  * WARNING: The C register and register group struct declarations are provided for
62924  * convenience and illustrative purposes. They should, however, be used with
62925  * caution as the C language standard provides no guarantees about the alignment or
62926  * atomicity of device memory accesses. The recommended practice for writing
62927  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
62928  * alt_write_word() functions.
62929  *
62930  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR105_LOW.
62931  */
62932 struct ALT_EMAC_GMAC_MAC_ADDR105_LOW_s
62933 {
62934  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO */
62935 };
62936 
62937 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR105_LOW. */
62938 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR105_LOW_s ALT_EMAC_GMAC_MAC_ADDR105_LOW_t;
62939 #endif /* __ASSEMBLY__ */
62940 
62941 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_LOW register. */
62942 #define ALT_EMAC_GMAC_MAC_ADDR105_LOW_RESET 0xffffffff
62943 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR105_LOW register from the beginning of the component. */
62944 #define ALT_EMAC_GMAC_MAC_ADDR105_LOW_OFST 0xacc
62945 /* The address of the ALT_EMAC_GMAC_MAC_ADDR105_LOW register. */
62946 #define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR105_LOW_OFST))
62947 
62948 /*
62949  * Register : gmacgrp_mac_address106_high
62950  *
62951  * <b> Register 692 (MAC Address106 High Register)</b>
62952  *
62953  * The MAC Address106 High register holds the upper 16 bits of the 107th 6-byte MAC
62954  * address of the station.
62955  *
62956  * If the MAC address registers are configured to be double-synchronized to the
62957  * (G)MII clock domains, then
62958  *
62959  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
62960  * or Bits[7:0] (in big-endian mode) of the MAC Address106 Low Register are
62961  * written. For proper synchronization updates, consecutive writes to this MAC
62962  * Address106 Low Register must be performed after at least four clock cycles in
62963  * the destination clock domain.
62964  *
62965  * Register Layout
62966  *
62967  * Bits | Access | Reset | Description
62968  * :--------|:-------|:-------|:------------------------------------------
62969  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI
62970  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR106_HIGH_RSVD_30_16
62971  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE
62972  *
62973  */
62974 /*
62975  * Field : addrhi
62976  *
62977  * MAC Address106 [47:32]
62978  *
62979  * This field contains the upper 16 bits (47:32) of the 107th 6-byte MAC address.
62980  *
62981  * Field Access Macros:
62982  *
62983  */
62984 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field. */
62985 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_LSB 0
62986 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field. */
62987 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_MSB 15
62988 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field. */
62989 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_WIDTH 16
62990 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field value. */
62991 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_SET_MSK 0x0000ffff
62992 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field value. */
62993 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_CLR_MSK 0xffff0000
62994 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field. */
62995 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_RESET 0xffff
62996 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI field value from a register. */
62997 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
62998 /* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field value suitable for setting the register. */
62999 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
63000 
63001 /*
63002  * Field : reserved_30_16
63003  *
63004  * Reserved
63005  *
63006  * Field Access Macros:
63007  *
63008  */
63009 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_RSVD_30_16 register field. */
63010 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_RSVD_30_16_LSB 16
63011 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_RSVD_30_16 register field. */
63012 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_RSVD_30_16_MSB 30
63013 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_RSVD_30_16 register field. */
63014 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_RSVD_30_16_WIDTH 15
63015 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_RSVD_30_16 register field value. */
63016 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
63017 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_RSVD_30_16 register field value. */
63018 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
63019 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_RSVD_30_16 register field. */
63020 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_RSVD_30_16_RESET 0x0
63021 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_RSVD_30_16 field value from a register. */
63022 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
63023 /* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_RSVD_30_16 register field value suitable for setting the register. */
63024 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
63025 
63026 /*
63027  * Field : ae
63028  *
63029  * Address Enable
63030  *
63031  * When this bit is set, the address filter module uses the 107th MAC address for
63032  * perfect filtering.
63033  *
63034  * When this bit is reset, the address filter module ignores the address for
63035  * filtering.
63036  *
63037  * Field Enumeration Values:
63038  *
63039  * Enum | Value | Description
63040  * :-----------------------------------------|:------|:------------
63041  * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_E_DISD | 0x0 |
63042  * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_E_END | 0x1 |
63043  *
63044  * Field Access Macros:
63045  *
63046  */
63047 /*
63048  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE
63049  *
63050  */
63051 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_E_DISD 0x0
63052 /*
63053  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE
63054  *
63055  */
63056 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_E_END 0x1
63057 
63058 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field. */
63059 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_LSB 31
63060 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field. */
63061 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_MSB 31
63062 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field. */
63063 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_WIDTH 1
63064 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field value. */
63065 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_SET_MSK 0x80000000
63066 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field value. */
63067 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_CLR_MSK 0x7fffffff
63068 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field. */
63069 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_RESET 0x0
63070 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE field value from a register. */
63071 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
63072 /* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field value suitable for setting the register. */
63073 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
63074 
63075 #ifndef __ASSEMBLY__
63076 /*
63077  * WARNING: The C register and register group struct declarations are provided for
63078  * convenience and illustrative purposes. They should, however, be used with
63079  * caution as the C language standard provides no guarantees about the alignment or
63080  * atomicity of device memory accesses. The recommended practice for writing
63081  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
63082  * alt_write_word() functions.
63083  *
63084  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR106_HIGH.
63085  */
63086 struct ALT_EMAC_GMAC_MAC_ADDR106_HIGH_s
63087 {
63088  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI */
63089  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR106_HIGH_RSVD_30_16 */
63090  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE */
63091 };
63092 
63093 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR106_HIGH. */
63094 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR106_HIGH_s ALT_EMAC_GMAC_MAC_ADDR106_HIGH_t;
63095 #endif /* __ASSEMBLY__ */
63096 
63097 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH register. */
63098 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_RESET 0x0000ffff
63099 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH register from the beginning of the component. */
63100 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_OFST 0xad0
63101 /* The address of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH register. */
63102 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR106_HIGH_OFST))
63103 
63104 /*
63105  * Register : gmacgrp_mac_address106_low
63106  *
63107  * <b> Register 693 (MAC Address106 Low Register)</b>
63108  *
63109  * The MAC Address106 Low register holds the lower 32 bits of the 107th 6-byte MAC
63110  * address of the station.
63111  *
63112  * Register Layout
63113  *
63114  * Bits | Access | Reset | Description
63115  * :-------|:-------|:-----------|:-------------------------------------
63116  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO
63117  *
63118  */
63119 /*
63120  * Field : addrlo
63121  *
63122  * MAC Address106 [31:0]
63123  *
63124  * This field contains the lower 32 bits of the 107th 6-byte MAC address. The
63125  * content of this field is undefined until loaded by the Application after the
63126  * initialization process.
63127  *
63128  * Field Access Macros:
63129  *
63130  */
63131 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field. */
63132 #define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_LSB 0
63133 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field. */
63134 #define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_MSB 31
63135 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field. */
63136 #define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_WIDTH 32
63137 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field value. */
63138 #define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_SET_MSK 0xffffffff
63139 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field value. */
63140 #define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_CLR_MSK 0x00000000
63141 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field. */
63142 #define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_RESET 0xffffffff
63143 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO field value from a register. */
63144 #define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
63145 /* Produces a ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field value suitable for setting the register. */
63146 #define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
63147 
63148 #ifndef __ASSEMBLY__
63149 /*
63150  * WARNING: The C register and register group struct declarations are provided for
63151  * convenience and illustrative purposes. They should, however, be used with
63152  * caution as the C language standard provides no guarantees about the alignment or
63153  * atomicity of device memory accesses. The recommended practice for writing
63154  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
63155  * alt_write_word() functions.
63156  *
63157  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR106_LOW.
63158  */
63159 struct ALT_EMAC_GMAC_MAC_ADDR106_LOW_s
63160 {
63161  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO */
63162 };
63163 
63164 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR106_LOW. */
63165 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR106_LOW_s ALT_EMAC_GMAC_MAC_ADDR106_LOW_t;
63166 #endif /* __ASSEMBLY__ */
63167 
63168 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_LOW register. */
63169 #define ALT_EMAC_GMAC_MAC_ADDR106_LOW_RESET 0xffffffff
63170 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR106_LOW register from the beginning of the component. */
63171 #define ALT_EMAC_GMAC_MAC_ADDR106_LOW_OFST 0xad4
63172 /* The address of the ALT_EMAC_GMAC_MAC_ADDR106_LOW register. */
63173 #define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR106_LOW_OFST))
63174 
63175 /*
63176  * Register : gmacgrp_mac_address107_high
63177  *
63178  * <b> Register 694 (MAC Address107 High Register)</b>
63179  *
63180  * The MAC Address107 High register holds the upper 16 bits of the 108th 6-byte MAC
63181  * address of the station.
63182  *
63183  * If the MAC address registers are configured to be double-synchronized to the
63184  * (G)MII clock domains, then
63185  *
63186  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
63187  * or Bits[7:0] (in big-endian mode) of the MAC Address107 Low Register are
63188  * written. For proper synchronization updates, consecutive writes to this MAC
63189  * Address107 Low Register must be performed after at least four clock cycles in
63190  * the destination clock domain.
63191  *
63192  * Register Layout
63193  *
63194  * Bits | Access | Reset | Description
63195  * :--------|:-------|:-------|:------------------------------------------
63196  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI
63197  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR107_HIGH_RSVD_30_16
63198  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE
63199  *
63200  */
63201 /*
63202  * Field : addrhi
63203  *
63204  * MAC Address107 [47:32]
63205  *
63206  * This field contains the upper 16 bits (47:32) of the 108th 6-byte MAC address.
63207  *
63208  * Field Access Macros:
63209  *
63210  */
63211 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field. */
63212 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_LSB 0
63213 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field. */
63214 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_MSB 15
63215 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field. */
63216 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_WIDTH 16
63217 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field value. */
63218 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_SET_MSK 0x0000ffff
63219 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field value. */
63220 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_CLR_MSK 0xffff0000
63221 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field. */
63222 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_RESET 0xffff
63223 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI field value from a register. */
63224 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
63225 /* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field value suitable for setting the register. */
63226 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
63227 
63228 /*
63229  * Field : reserved_30_16
63230  *
63231  * Reserved
63232  *
63233  * Field Access Macros:
63234  *
63235  */
63236 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_RSVD_30_16 register field. */
63237 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_RSVD_30_16_LSB 16
63238 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_RSVD_30_16 register field. */
63239 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_RSVD_30_16_MSB 30
63240 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_RSVD_30_16 register field. */
63241 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_RSVD_30_16_WIDTH 15
63242 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_RSVD_30_16 register field value. */
63243 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
63244 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_RSVD_30_16 register field value. */
63245 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
63246 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_RSVD_30_16 register field. */
63247 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_RSVD_30_16_RESET 0x0
63248 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_RSVD_30_16 field value from a register. */
63249 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
63250 /* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_RSVD_30_16 register field value suitable for setting the register. */
63251 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
63252 
63253 /*
63254  * Field : ae
63255  *
63256  * Address Enable
63257  *
63258  * When this bit is set, the address filter module uses the 108th MAC address for
63259  * perfect filtering.
63260  *
63261  * When this bit is reset, the address filter module ignores the address for
63262  * filtering.
63263  *
63264  * Field Enumeration Values:
63265  *
63266  * Enum | Value | Description
63267  * :-----------------------------------------|:------|:------------
63268  * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_E_DISD | 0x0 |
63269  * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_E_END | 0x1 |
63270  *
63271  * Field Access Macros:
63272  *
63273  */
63274 /*
63275  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE
63276  *
63277  */
63278 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_E_DISD 0x0
63279 /*
63280  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE
63281  *
63282  */
63283 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_E_END 0x1
63284 
63285 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field. */
63286 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_LSB 31
63287 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field. */
63288 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_MSB 31
63289 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field. */
63290 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_WIDTH 1
63291 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field value. */
63292 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_SET_MSK 0x80000000
63293 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field value. */
63294 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_CLR_MSK 0x7fffffff
63295 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field. */
63296 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_RESET 0x0
63297 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE field value from a register. */
63298 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
63299 /* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field value suitable for setting the register. */
63300 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
63301 
63302 #ifndef __ASSEMBLY__
63303 /*
63304  * WARNING: The C register and register group struct declarations are provided for
63305  * convenience and illustrative purposes. They should, however, be used with
63306  * caution as the C language standard provides no guarantees about the alignment or
63307  * atomicity of device memory accesses. The recommended practice for writing
63308  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
63309  * alt_write_word() functions.
63310  *
63311  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR107_HIGH.
63312  */
63313 struct ALT_EMAC_GMAC_MAC_ADDR107_HIGH_s
63314 {
63315  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI */
63316  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR107_HIGH_RSVD_30_16 */
63317  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE */
63318 };
63319 
63320 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR107_HIGH. */
63321 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR107_HIGH_s ALT_EMAC_GMAC_MAC_ADDR107_HIGH_t;
63322 #endif /* __ASSEMBLY__ */
63323 
63324 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH register. */
63325 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_RESET 0x0000ffff
63326 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH register from the beginning of the component. */
63327 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_OFST 0xad8
63328 /* The address of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH register. */
63329 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR107_HIGH_OFST))
63330 
63331 /*
63332  * Register : gmacgrp_mac_address107_low
63333  *
63334  * <b> Register 695 (MAC Address107 Low Register)</b>
63335  *
63336  * The MAC Address107 Low register holds the lower 32 bits of the 108th 6-byte MAC
63337  * address of the station.
63338  *
63339  * Register Layout
63340  *
63341  * Bits | Access | Reset | Description
63342  * :-------|:-------|:-----------|:-------------------------------------
63343  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO
63344  *
63345  */
63346 /*
63347  * Field : addrlo
63348  *
63349  * MAC Address107 [31:0]
63350  *
63351  * This field contains the lower 32 bits of the 108th 6-byte MAC address. The
63352  * content of this field is undefined until loaded by the Application after the
63353  * initialization process.
63354  *
63355  * Field Access Macros:
63356  *
63357  */
63358 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field. */
63359 #define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_LSB 0
63360 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field. */
63361 #define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_MSB 31
63362 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field. */
63363 #define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_WIDTH 32
63364 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field value. */
63365 #define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_SET_MSK 0xffffffff
63366 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field value. */
63367 #define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_CLR_MSK 0x00000000
63368 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field. */
63369 #define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_RESET 0xffffffff
63370 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO field value from a register. */
63371 #define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
63372 /* Produces a ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field value suitable for setting the register. */
63373 #define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
63374 
63375 #ifndef __ASSEMBLY__
63376 /*
63377  * WARNING: The C register and register group struct declarations are provided for
63378  * convenience and illustrative purposes. They should, however, be used with
63379  * caution as the C language standard provides no guarantees about the alignment or
63380  * atomicity of device memory accesses. The recommended practice for writing
63381  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
63382  * alt_write_word() functions.
63383  *
63384  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR107_LOW.
63385  */
63386 struct ALT_EMAC_GMAC_MAC_ADDR107_LOW_s
63387 {
63388  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO */
63389 };
63390 
63391 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR107_LOW. */
63392 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR107_LOW_s ALT_EMAC_GMAC_MAC_ADDR107_LOW_t;
63393 #endif /* __ASSEMBLY__ */
63394 
63395 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_LOW register. */
63396 #define ALT_EMAC_GMAC_MAC_ADDR107_LOW_RESET 0xffffffff
63397 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR107_LOW register from the beginning of the component. */
63398 #define ALT_EMAC_GMAC_MAC_ADDR107_LOW_OFST 0xadc
63399 /* The address of the ALT_EMAC_GMAC_MAC_ADDR107_LOW register. */
63400 #define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR107_LOW_OFST))
63401 
63402 /*
63403  * Register : gmacgrp_mac_address108_high
63404  *
63405  * <b> Register 696 (MAC Address108 High Register)</b>
63406  *
63407  * The MAC Address108 High register holds the upper 16 bits of the 109th 6-byte MAC
63408  * address of the station.
63409  *
63410  * If the MAC address registers are configured to be double-synchronized to the
63411  * (G)MII clock domains, then
63412  *
63413  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
63414  * or Bits[7:0] (in big-endian mode) of the MAC Address108 Low Register are
63415  * written. For proper synchronization updates, consecutive writes to this MAC
63416  * Address108 Low Register must be performed after at least four clock cycles in
63417  * the destination clock domain.
63418  *
63419  * Register Layout
63420  *
63421  * Bits | Access | Reset | Description
63422  * :--------|:-------|:-------|:------------------------------------------
63423  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI
63424  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR108_HIGH_RSVD_30_16
63425  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE
63426  *
63427  */
63428 /*
63429  * Field : addrhi
63430  *
63431  * MAC Address108 [47:32]
63432  *
63433  * This field contains the upper 16 bits (47:32) of the 109th 6-byte MAC address.
63434  *
63435  * Field Access Macros:
63436  *
63437  */
63438 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field. */
63439 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_LSB 0
63440 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field. */
63441 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_MSB 15
63442 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field. */
63443 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_WIDTH 16
63444 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field value. */
63445 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_SET_MSK 0x0000ffff
63446 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field value. */
63447 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_CLR_MSK 0xffff0000
63448 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field. */
63449 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_RESET 0xffff
63450 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI field value from a register. */
63451 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
63452 /* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field value suitable for setting the register. */
63453 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
63454 
63455 /*
63456  * Field : reserved_30_16
63457  *
63458  * Reserved
63459  *
63460  * Field Access Macros:
63461  *
63462  */
63463 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_RSVD_30_16 register field. */
63464 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_RSVD_30_16_LSB 16
63465 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_RSVD_30_16 register field. */
63466 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_RSVD_30_16_MSB 30
63467 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_RSVD_30_16 register field. */
63468 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_RSVD_30_16_WIDTH 15
63469 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_RSVD_30_16 register field value. */
63470 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
63471 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_RSVD_30_16 register field value. */
63472 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
63473 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_RSVD_30_16 register field. */
63474 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_RSVD_30_16_RESET 0x0
63475 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_RSVD_30_16 field value from a register. */
63476 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
63477 /* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_RSVD_30_16 register field value suitable for setting the register. */
63478 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
63479 
63480 /*
63481  * Field : ae
63482  *
63483  * Address Enable
63484  *
63485  * When this bit is set, the address filter module uses the 109th MAC address for
63486  * perfect filtering.
63487  *
63488  * When this bit is reset, the address filter module ignores the address for
63489  * filtering.
63490  *
63491  * Field Enumeration Values:
63492  *
63493  * Enum | Value | Description
63494  * :-----------------------------------------|:------|:------------
63495  * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_E_DISD | 0x0 |
63496  * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_E_END | 0x1 |
63497  *
63498  * Field Access Macros:
63499  *
63500  */
63501 /*
63502  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE
63503  *
63504  */
63505 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_E_DISD 0x0
63506 /*
63507  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE
63508  *
63509  */
63510 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_E_END 0x1
63511 
63512 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field. */
63513 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_LSB 31
63514 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field. */
63515 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_MSB 31
63516 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field. */
63517 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_WIDTH 1
63518 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field value. */
63519 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_SET_MSK 0x80000000
63520 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field value. */
63521 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_CLR_MSK 0x7fffffff
63522 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field. */
63523 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_RESET 0x0
63524 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE field value from a register. */
63525 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
63526 /* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field value suitable for setting the register. */
63527 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
63528 
63529 #ifndef __ASSEMBLY__
63530 /*
63531  * WARNING: The C register and register group struct declarations are provided for
63532  * convenience and illustrative purposes. They should, however, be used with
63533  * caution as the C language standard provides no guarantees about the alignment or
63534  * atomicity of device memory accesses. The recommended practice for writing
63535  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
63536  * alt_write_word() functions.
63537  *
63538  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR108_HIGH.
63539  */
63540 struct ALT_EMAC_GMAC_MAC_ADDR108_HIGH_s
63541 {
63542  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI */
63543  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR108_HIGH_RSVD_30_16 */
63544  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE */
63545 };
63546 
63547 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR108_HIGH. */
63548 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR108_HIGH_s ALT_EMAC_GMAC_MAC_ADDR108_HIGH_t;
63549 #endif /* __ASSEMBLY__ */
63550 
63551 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH register. */
63552 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_RESET 0x0000ffff
63553 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH register from the beginning of the component. */
63554 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_OFST 0xae0
63555 /* The address of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH register. */
63556 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR108_HIGH_OFST))
63557 
63558 /*
63559  * Register : gmacgrp_mac_address108_low
63560  *
63561  * <b> Register 697 (MAC Address108 Low Register)</b>
63562  *
63563  * The MAC Address108 Low register holds the lower 32 bits of the 109th 6-byte MAC
63564  * address of the station.
63565  *
63566  * Register Layout
63567  *
63568  * Bits | Access | Reset | Description
63569  * :-------|:-------|:-----------|:-------------------------------------
63570  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO
63571  *
63572  */
63573 /*
63574  * Field : addrlo
63575  *
63576  * MAC Address108 [31:0]
63577  *
63578  * This field contains the lower 32 bits of the 109th 6-byte MAC address. The
63579  * content of this field is undefined until loaded by the Application after the
63580  * initialization process.
63581  *
63582  * Field Access Macros:
63583  *
63584  */
63585 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field. */
63586 #define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_LSB 0
63587 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field. */
63588 #define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_MSB 31
63589 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field. */
63590 #define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_WIDTH 32
63591 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field value. */
63592 #define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_SET_MSK 0xffffffff
63593 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field value. */
63594 #define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_CLR_MSK 0x00000000
63595 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field. */
63596 #define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_RESET 0xffffffff
63597 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO field value from a register. */
63598 #define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
63599 /* Produces a ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field value suitable for setting the register. */
63600 #define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
63601 
63602 #ifndef __ASSEMBLY__
63603 /*
63604  * WARNING: The C register and register group struct declarations are provided for
63605  * convenience and illustrative purposes. They should, however, be used with
63606  * caution as the C language standard provides no guarantees about the alignment or
63607  * atomicity of device memory accesses. The recommended practice for writing
63608  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
63609  * alt_write_word() functions.
63610  *
63611  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR108_LOW.
63612  */
63613 struct ALT_EMAC_GMAC_MAC_ADDR108_LOW_s
63614 {
63615  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO */
63616 };
63617 
63618 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR108_LOW. */
63619 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR108_LOW_s ALT_EMAC_GMAC_MAC_ADDR108_LOW_t;
63620 #endif /* __ASSEMBLY__ */
63621 
63622 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_LOW register. */
63623 #define ALT_EMAC_GMAC_MAC_ADDR108_LOW_RESET 0xffffffff
63624 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR108_LOW register from the beginning of the component. */
63625 #define ALT_EMAC_GMAC_MAC_ADDR108_LOW_OFST 0xae4
63626 /* The address of the ALT_EMAC_GMAC_MAC_ADDR108_LOW register. */
63627 #define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR108_LOW_OFST))
63628 
63629 /*
63630  * Register : gmacgrp_mac_address109_high
63631  *
63632  * <b> Register 698 (MAC Address109 High Register)</b>
63633  *
63634  * The MAC Address109 High register holds the upper 16 bits of the 110th 6-byte MAC
63635  * address of the station.
63636  *
63637  * If the MAC address registers are configured to be double-synchronized to the
63638  * (G)MII clock domains, then
63639  *
63640  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
63641  * or Bits[7:0] (in big-endian mode) of the MAC Address109 Low Register are
63642  * written. For proper synchronization updates, consecutive writes to this MAC
63643  * Address109 Low Register must be performed after at least four clock cycles in
63644  * the destination clock domain.
63645  *
63646  * Register Layout
63647  *
63648  * Bits | Access | Reset | Description
63649  * :--------|:-------|:-------|:------------------------------------------
63650  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI
63651  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR109_HIGH_RSVD_30_16
63652  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE
63653  *
63654  */
63655 /*
63656  * Field : addrhi
63657  *
63658  * MAC Address109 [47:32]
63659  *
63660  * This field contains the upper 16 bits (47:32) of the 110th 6-byte MAC address.
63661  *
63662  * Field Access Macros:
63663  *
63664  */
63665 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field. */
63666 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_LSB 0
63667 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field. */
63668 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_MSB 15
63669 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field. */
63670 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_WIDTH 16
63671 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field value. */
63672 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_SET_MSK 0x0000ffff
63673 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field value. */
63674 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_CLR_MSK 0xffff0000
63675 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field. */
63676 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_RESET 0xffff
63677 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI field value from a register. */
63678 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
63679 /* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field value suitable for setting the register. */
63680 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
63681 
63682 /*
63683  * Field : reserved_30_16
63684  *
63685  * Reserved
63686  *
63687  * Field Access Macros:
63688  *
63689  */
63690 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_RSVD_30_16 register field. */
63691 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_RSVD_30_16_LSB 16
63692 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_RSVD_30_16 register field. */
63693 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_RSVD_30_16_MSB 30
63694 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_RSVD_30_16 register field. */
63695 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_RSVD_30_16_WIDTH 15
63696 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_RSVD_30_16 register field value. */
63697 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
63698 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_RSVD_30_16 register field value. */
63699 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
63700 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_RSVD_30_16 register field. */
63701 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_RSVD_30_16_RESET 0x0
63702 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_RSVD_30_16 field value from a register. */
63703 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
63704 /* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_RSVD_30_16 register field value suitable for setting the register. */
63705 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
63706 
63707 /*
63708  * Field : ae
63709  *
63710  * Address Enable
63711  *
63712  * When this bit is set, the address filter module uses the 110th MAC address for
63713  * perfect filtering.
63714  *
63715  * When this bit is reset, the address filter module ignores the address for
63716  * filtering.
63717  *
63718  * Field Enumeration Values:
63719  *
63720  * Enum | Value | Description
63721  * :-----------------------------------------|:------|:------------
63722  * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_E_DISD | 0x0 |
63723  * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_E_END | 0x1 |
63724  *
63725  * Field Access Macros:
63726  *
63727  */
63728 /*
63729  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE
63730  *
63731  */
63732 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_E_DISD 0x0
63733 /*
63734  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE
63735  *
63736  */
63737 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_E_END 0x1
63738 
63739 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field. */
63740 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_LSB 31
63741 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field. */
63742 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_MSB 31
63743 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field. */
63744 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_WIDTH 1
63745 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field value. */
63746 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_SET_MSK 0x80000000
63747 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field value. */
63748 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_CLR_MSK 0x7fffffff
63749 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field. */
63750 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_RESET 0x0
63751 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE field value from a register. */
63752 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
63753 /* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field value suitable for setting the register. */
63754 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
63755 
63756 #ifndef __ASSEMBLY__
63757 /*
63758  * WARNING: The C register and register group struct declarations are provided for
63759  * convenience and illustrative purposes. They should, however, be used with
63760  * caution as the C language standard provides no guarantees about the alignment or
63761  * atomicity of device memory accesses. The recommended practice for writing
63762  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
63763  * alt_write_word() functions.
63764  *
63765  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR109_HIGH.
63766  */
63767 struct ALT_EMAC_GMAC_MAC_ADDR109_HIGH_s
63768 {
63769  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI */
63770  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR109_HIGH_RSVD_30_16 */
63771  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE */
63772 };
63773 
63774 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR109_HIGH. */
63775 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR109_HIGH_s ALT_EMAC_GMAC_MAC_ADDR109_HIGH_t;
63776 #endif /* __ASSEMBLY__ */
63777 
63778 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH register. */
63779 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_RESET 0x0000ffff
63780 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH register from the beginning of the component. */
63781 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_OFST 0xae8
63782 /* The address of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH register. */
63783 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR109_HIGH_OFST))
63784 
63785 /*
63786  * Register : gmacgrp_mac_address109_low
63787  *
63788  * <b> Register 699 (MAC Address109 Low Register)</b>
63789  *
63790  * The MAC Address109 Low register holds the lower 32 bits of the 110th 6-byte MAC
63791  * address of the station.
63792  *
63793  * Register Layout
63794  *
63795  * Bits | Access | Reset | Description
63796  * :-------|:-------|:-----------|:-------------------------------------
63797  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO
63798  *
63799  */
63800 /*
63801  * Field : addrlo
63802  *
63803  * MAC Address109 [31:0]
63804  *
63805  * This field contains the lower 32 bits of the 110th 6-byte MAC address. The
63806  * content of this field is undefined until loaded by the Application after the
63807  * initialization process.
63808  *
63809  * Field Access Macros:
63810  *
63811  */
63812 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field. */
63813 #define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_LSB 0
63814 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field. */
63815 #define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_MSB 31
63816 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field. */
63817 #define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_WIDTH 32
63818 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field value. */
63819 #define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_SET_MSK 0xffffffff
63820 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field value. */
63821 #define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_CLR_MSK 0x00000000
63822 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field. */
63823 #define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_RESET 0xffffffff
63824 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO field value from a register. */
63825 #define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
63826 /* Produces a ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field value suitable for setting the register. */
63827 #define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
63828 
63829 #ifndef __ASSEMBLY__
63830 /*
63831  * WARNING: The C register and register group struct declarations are provided for
63832  * convenience and illustrative purposes. They should, however, be used with
63833  * caution as the C language standard provides no guarantees about the alignment or
63834  * atomicity of device memory accesses. The recommended practice for writing
63835  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
63836  * alt_write_word() functions.
63837  *
63838  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR109_LOW.
63839  */
63840 struct ALT_EMAC_GMAC_MAC_ADDR109_LOW_s
63841 {
63842  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO */
63843 };
63844 
63845 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR109_LOW. */
63846 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR109_LOW_s ALT_EMAC_GMAC_MAC_ADDR109_LOW_t;
63847 #endif /* __ASSEMBLY__ */
63848 
63849 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_LOW register. */
63850 #define ALT_EMAC_GMAC_MAC_ADDR109_LOW_RESET 0xffffffff
63851 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR109_LOW register from the beginning of the component. */
63852 #define ALT_EMAC_GMAC_MAC_ADDR109_LOW_OFST 0xaec
63853 /* The address of the ALT_EMAC_GMAC_MAC_ADDR109_LOW register. */
63854 #define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR109_LOW_OFST))
63855 
63856 /*
63857  * Register : gmacgrp_mac_address110_high
63858  *
63859  * <b> Register XXX (MAC AddressXX High Register)</b>
63860  *
63861  * The MAC Address110 High register holds the upper 16 bits of the 111th 6-byte MAC
63862  * address of the station.
63863  *
63864  * If the MAC address registers are configured to be double-synchronized to the
63865  * (G)MII clock domains, then
63866  *
63867  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
63868  * or Bits[7:0] (in big-endian mode) of the MAC Address110 Low Register are
63869  * written. For proper synchronization updates, consecutive writes to this MAC
63870  * Address110 Low Register must be performed after at least four clock cycles in
63871  * the destination clock domain.
63872  *
63873  * Register Layout
63874  *
63875  * Bits | Access | Reset | Description
63876  * :--------|:-------|:-------|:------------------------------------------
63877  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI
63878  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR110_HIGH_RSVD_30_16
63879  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE
63880  *
63881  */
63882 /*
63883  * Field : addrhi
63884  *
63885  * MAC Address110 [47:32]
63886  *
63887  * This field contains the upper 16 bits (47:32) of the 111th 6-byte MAC address.
63888  *
63889  * Field Access Macros:
63890  *
63891  */
63892 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field. */
63893 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_LSB 0
63894 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field. */
63895 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_MSB 15
63896 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field. */
63897 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_WIDTH 16
63898 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field value. */
63899 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_SET_MSK 0x0000ffff
63900 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field value. */
63901 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_CLR_MSK 0xffff0000
63902 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field. */
63903 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_RESET 0xffff
63904 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI field value from a register. */
63905 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
63906 /* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field value suitable for setting the register. */
63907 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
63908 
63909 /*
63910  * Field : reserved_30_16
63911  *
63912  * Reserved
63913  *
63914  * Field Access Macros:
63915  *
63916  */
63917 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_RSVD_30_16 register field. */
63918 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_RSVD_30_16_LSB 16
63919 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_RSVD_30_16 register field. */
63920 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_RSVD_30_16_MSB 30
63921 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_RSVD_30_16 register field. */
63922 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_RSVD_30_16_WIDTH 15
63923 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_RSVD_30_16 register field value. */
63924 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
63925 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_RSVD_30_16 register field value. */
63926 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
63927 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_RSVD_30_16 register field. */
63928 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_RSVD_30_16_RESET 0x0
63929 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_RSVD_30_16 field value from a register. */
63930 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
63931 /* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_RSVD_30_16 register field value suitable for setting the register. */
63932 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
63933 
63934 /*
63935  * Field : ae
63936  *
63937  * Address Enable
63938  *
63939  * When this bit is set, the address filter module uses the 111th MAC address for
63940  * perfect filtering.
63941  *
63942  * When this bit is reset, the address filter module ignores the address for
63943  * filtering.
63944  *
63945  * Field Enumeration Values:
63946  *
63947  * Enum | Value | Description
63948  * :-----------------------------------------|:------|:------------
63949  * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_E_DISD | 0x0 |
63950  * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_E_END | 0x1 |
63951  *
63952  * Field Access Macros:
63953  *
63954  */
63955 /*
63956  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE
63957  *
63958  */
63959 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_E_DISD 0x0
63960 /*
63961  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE
63962  *
63963  */
63964 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_E_END 0x1
63965 
63966 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field. */
63967 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_LSB 31
63968 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field. */
63969 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_MSB 31
63970 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field. */
63971 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_WIDTH 1
63972 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field value. */
63973 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_SET_MSK 0x80000000
63974 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field value. */
63975 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_CLR_MSK 0x7fffffff
63976 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field. */
63977 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_RESET 0x0
63978 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE field value from a register. */
63979 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
63980 /* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field value suitable for setting the register. */
63981 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
63982 
63983 #ifndef __ASSEMBLY__
63984 /*
63985  * WARNING: The C register and register group struct declarations are provided for
63986  * convenience and illustrative purposes. They should, however, be used with
63987  * caution as the C language standard provides no guarantees about the alignment or
63988  * atomicity of device memory accesses. The recommended practice for writing
63989  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
63990  * alt_write_word() functions.
63991  *
63992  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR110_HIGH.
63993  */
63994 struct ALT_EMAC_GMAC_MAC_ADDR110_HIGH_s
63995 {
63996  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI */
63997  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR110_HIGH_RSVD_30_16 */
63998  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE */
63999 };
64000 
64001 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR110_HIGH. */
64002 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR110_HIGH_s ALT_EMAC_GMAC_MAC_ADDR110_HIGH_t;
64003 #endif /* __ASSEMBLY__ */
64004 
64005 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH register. */
64006 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_RESET 0x0000ffff
64007 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH register from the beginning of the component. */
64008 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_OFST 0xaf0
64009 /* The address of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH register. */
64010 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR110_HIGH_OFST))
64011 
64012 /*
64013  * Register : gmacgrp_mac_address110_low
64014  *
64015  * <b> Register 700 (MAC Address110 Low Register)</b>
64016  *
64017  * The MAC Address110 Low register holds the lower 32 bits of the 111th 6-byte MAC
64018  * address of the station.
64019  *
64020  * Register Layout
64021  *
64022  * Bits | Access | Reset | Description
64023  * :-------|:-------|:-----------|:-------------------------------------
64024  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO
64025  *
64026  */
64027 /*
64028  * Field : addrlo
64029  *
64030  * MAC Address110 [31:0]
64031  *
64032  * This field contains the lower 32 bits of the 111th 6-byte MAC address. The
64033  * content of this field is undefined until loaded by the Application after the
64034  * initialization process.
64035  *
64036  * Field Access Macros:
64037  *
64038  */
64039 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field. */
64040 #define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_LSB 0
64041 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field. */
64042 #define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_MSB 31
64043 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field. */
64044 #define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_WIDTH 32
64045 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field value. */
64046 #define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_SET_MSK 0xffffffff
64047 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field value. */
64048 #define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_CLR_MSK 0x00000000
64049 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field. */
64050 #define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_RESET 0xffffffff
64051 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO field value from a register. */
64052 #define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
64053 /* Produces a ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field value suitable for setting the register. */
64054 #define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
64055 
64056 #ifndef __ASSEMBLY__
64057 /*
64058  * WARNING: The C register and register group struct declarations are provided for
64059  * convenience and illustrative purposes. They should, however, be used with
64060  * caution as the C language standard provides no guarantees about the alignment or
64061  * atomicity of device memory accesses. The recommended practice for writing
64062  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
64063  * alt_write_word() functions.
64064  *
64065  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR110_LOW.
64066  */
64067 struct ALT_EMAC_GMAC_MAC_ADDR110_LOW_s
64068 {
64069  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO */
64070 };
64071 
64072 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR110_LOW. */
64073 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR110_LOW_s ALT_EMAC_GMAC_MAC_ADDR110_LOW_t;
64074 #endif /* __ASSEMBLY__ */
64075 
64076 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_LOW register. */
64077 #define ALT_EMAC_GMAC_MAC_ADDR110_LOW_RESET 0xffffffff
64078 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR110_LOW register from the beginning of the component. */
64079 #define ALT_EMAC_GMAC_MAC_ADDR110_LOW_OFST 0xaf4
64080 /* The address of the ALT_EMAC_GMAC_MAC_ADDR110_LOW register. */
64081 #define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR110_LOW_OFST))
64082 
64083 /*
64084  * Register : gmacgrp_mac_address111_high
64085  *
64086  * <b> Register 701 (MAC Address111 High Register)</b>
64087  *
64088  * The MAC Address111 High register holds the upper 16 bits of the 6-byte 112th MAC
64089  * address of the station.
64090  *
64091  * If the MAC address registers are configured to be double-synchronized to the
64092  * (G)MII clock domains, then
64093  *
64094  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
64095  * or Bits[7:0] (in big-endian mode) of the MAC Address111 Low Register are
64096  * written. For proper synchronization updates, consecutive writes to this MAC
64097  * Address111 Low Register must be performed after at least four clock cycles in
64098  * the destination clock domain.
64099  *
64100  * Register Layout
64101  *
64102  * Bits | Access | Reset | Description
64103  * :--------|:-------|:-------|:------------------------------------------
64104  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI
64105  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR111_HIGH_RSVD_30_16
64106  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE
64107  *
64108  */
64109 /*
64110  * Field : addrhi
64111  *
64112  * MAC Address111 [47:32]
64113  *
64114  * This field contains the upper 16 bits (47:32) of the 112th 6-byte MAC address.
64115  *
64116  * Field Access Macros:
64117  *
64118  */
64119 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field. */
64120 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_LSB 0
64121 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field. */
64122 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_MSB 15
64123 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field. */
64124 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_WIDTH 16
64125 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field value. */
64126 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_SET_MSK 0x0000ffff
64127 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field value. */
64128 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_CLR_MSK 0xffff0000
64129 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field. */
64130 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_RESET 0xffff
64131 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI field value from a register. */
64132 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
64133 /* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field value suitable for setting the register. */
64134 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
64135 
64136 /*
64137  * Field : reserved_30_16
64138  *
64139  * Reserved
64140  *
64141  * Field Access Macros:
64142  *
64143  */
64144 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_RSVD_30_16 register field. */
64145 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_RSVD_30_16_LSB 16
64146 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_RSVD_30_16 register field. */
64147 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_RSVD_30_16_MSB 30
64148 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_RSVD_30_16 register field. */
64149 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_RSVD_30_16_WIDTH 15
64150 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_RSVD_30_16 register field value. */
64151 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
64152 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_RSVD_30_16 register field value. */
64153 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
64154 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_RSVD_30_16 register field. */
64155 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_RSVD_30_16_RESET 0x0
64156 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_RSVD_30_16 field value from a register. */
64157 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
64158 /* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_RSVD_30_16 register field value suitable for setting the register. */
64159 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
64160 
64161 /*
64162  * Field : ae
64163  *
64164  * Address Enable
64165  *
64166  * When this bit is set, the address filter module uses the 112th MAC address for
64167  * perfect filtering.
64168  *
64169  * When this bit is reset, the address filter module ignores the address for
64170  * filtering.
64171  *
64172  * Field Enumeration Values:
64173  *
64174  * Enum | Value | Description
64175  * :-----------------------------------------|:------|:------------
64176  * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_E_DISD | 0x0 |
64177  * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_E_END | 0x1 |
64178  *
64179  * Field Access Macros:
64180  *
64181  */
64182 /*
64183  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE
64184  *
64185  */
64186 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_E_DISD 0x0
64187 /*
64188  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE
64189  *
64190  */
64191 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_E_END 0x1
64192 
64193 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field. */
64194 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_LSB 31
64195 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field. */
64196 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_MSB 31
64197 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field. */
64198 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_WIDTH 1
64199 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field value. */
64200 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_SET_MSK 0x80000000
64201 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field value. */
64202 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_CLR_MSK 0x7fffffff
64203 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field. */
64204 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_RESET 0x0
64205 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE field value from a register. */
64206 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
64207 /* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field value suitable for setting the register. */
64208 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
64209 
64210 #ifndef __ASSEMBLY__
64211 /*
64212  * WARNING: The C register and register group struct declarations are provided for
64213  * convenience and illustrative purposes. They should, however, be used with
64214  * caution as the C language standard provides no guarantees about the alignment or
64215  * atomicity of device memory accesses. The recommended practice for writing
64216  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
64217  * alt_write_word() functions.
64218  *
64219  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR111_HIGH.
64220  */
64221 struct ALT_EMAC_GMAC_MAC_ADDR111_HIGH_s
64222 {
64223  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI */
64224  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR111_HIGH_RSVD_30_16 */
64225  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE */
64226 };
64227 
64228 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR111_HIGH. */
64229 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR111_HIGH_s ALT_EMAC_GMAC_MAC_ADDR111_HIGH_t;
64230 #endif /* __ASSEMBLY__ */
64231 
64232 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH register. */
64233 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_RESET 0x0000ffff
64234 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH register from the beginning of the component. */
64235 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_OFST 0xaf8
64236 /* The address of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH register. */
64237 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR111_HIGH_OFST))
64238 
64239 /*
64240  * Register : gmacgrp_mac_address111_low
64241  *
64242  * <b> Register 702 (MAC Address111 Low Register)</b>
64243  *
64244  * The MAC Address111 Low register holds the lower 32 bits of the 112th 6-byte MAC
64245  * address of the station.
64246  *
64247  * Register Layout
64248  *
64249  * Bits | Access | Reset | Description
64250  * :-------|:-------|:-----------|:-------------------------------------
64251  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO
64252  *
64253  */
64254 /*
64255  * Field : addrlo
64256  *
64257  * MAC Address111 [31:0]
64258  *
64259  * This field contains the lower 32 bits of the 112th 6-byte MAC address. The
64260  * content of this field is undefined until loaded by the Application after the
64261  * initialization process.
64262  *
64263  * Field Access Macros:
64264  *
64265  */
64266 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field. */
64267 #define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_LSB 0
64268 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field. */
64269 #define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_MSB 31
64270 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field. */
64271 #define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_WIDTH 32
64272 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field value. */
64273 #define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_SET_MSK 0xffffffff
64274 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field value. */
64275 #define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_CLR_MSK 0x00000000
64276 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field. */
64277 #define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_RESET 0xffffffff
64278 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO field value from a register. */
64279 #define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
64280 /* Produces a ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field value suitable for setting the register. */
64281 #define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
64282 
64283 #ifndef __ASSEMBLY__
64284 /*
64285  * WARNING: The C register and register group struct declarations are provided for
64286  * convenience and illustrative purposes. They should, however, be used with
64287  * caution as the C language standard provides no guarantees about the alignment or
64288  * atomicity of device memory accesses. The recommended practice for writing
64289  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
64290  * alt_write_word() functions.
64291  *
64292  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR111_LOW.
64293  */
64294 struct ALT_EMAC_GMAC_MAC_ADDR111_LOW_s
64295 {
64296  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO */
64297 };
64298 
64299 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR111_LOW. */
64300 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR111_LOW_s ALT_EMAC_GMAC_MAC_ADDR111_LOW_t;
64301 #endif /* __ASSEMBLY__ */
64302 
64303 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_LOW register. */
64304 #define ALT_EMAC_GMAC_MAC_ADDR111_LOW_RESET 0xffffffff
64305 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR111_LOW register from the beginning of the component. */
64306 #define ALT_EMAC_GMAC_MAC_ADDR111_LOW_OFST 0xafc
64307 /* The address of the ALT_EMAC_GMAC_MAC_ADDR111_LOW register. */
64308 #define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR111_LOW_OFST))
64309 
64310 /*
64311  * Register : gmacgrp_mac_address112_high
64312  *
64313  * <b> Register 703 (MAC Address112 High Register)</b>
64314  *
64315  * The MAC Address112 High register holds the upper 16 bits of the 113th 6-byte MAC
64316  * address of the station.
64317  *
64318  * If the MAC address registers are configured to be double-synchronized to the
64319  * (G)MII clock domains, then
64320  *
64321  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
64322  * or Bits[7:0] (in big-endian mode) of the MAC Address112 Low Register are
64323  * written. For proper synchronization updates, consecutive writes to this MAC
64324  * Address112 Low Register must be performed after at least four clock cycles in
64325  * the destination clock domain.
64326  *
64327  * Register Layout
64328  *
64329  * Bits | Access | Reset | Description
64330  * :--------|:-------|:-------|:------------------------------------------
64331  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI
64332  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR112_HIGH_RSVD_30_16
64333  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE
64334  *
64335  */
64336 /*
64337  * Field : addrhi
64338  *
64339  * MAC Address112 [47:32]
64340  *
64341  * This field contains the upper 16 bits (47:32) of the 113th 6-byte MAC address.
64342  *
64343  * Field Access Macros:
64344  *
64345  */
64346 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field. */
64347 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_LSB 0
64348 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field. */
64349 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_MSB 15
64350 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field. */
64351 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_WIDTH 16
64352 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field value. */
64353 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_SET_MSK 0x0000ffff
64354 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field value. */
64355 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_CLR_MSK 0xffff0000
64356 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field. */
64357 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_RESET 0xffff
64358 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI field value from a register. */
64359 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
64360 /* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field value suitable for setting the register. */
64361 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
64362 
64363 /*
64364  * Field : reserved_30_16
64365  *
64366  * Reserved
64367  *
64368  * Field Access Macros:
64369  *
64370  */
64371 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_RSVD_30_16 register field. */
64372 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_RSVD_30_16_LSB 16
64373 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_RSVD_30_16 register field. */
64374 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_RSVD_30_16_MSB 30
64375 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_RSVD_30_16 register field. */
64376 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_RSVD_30_16_WIDTH 15
64377 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_RSVD_30_16 register field value. */
64378 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
64379 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_RSVD_30_16 register field value. */
64380 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
64381 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_RSVD_30_16 register field. */
64382 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_RSVD_30_16_RESET 0x0
64383 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_RSVD_30_16 field value from a register. */
64384 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
64385 /* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_RSVD_30_16 register field value suitable for setting the register. */
64386 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
64387 
64388 /*
64389  * Field : ae
64390  *
64391  * Address Enable
64392  *
64393  * When this bit is set, the address filter module uses the 113th MAC address for
64394  * perfect filtering.
64395  *
64396  * When this bit is reset, the address filter module ignores the address for
64397  * filtering.
64398  *
64399  * Field Enumeration Values:
64400  *
64401  * Enum | Value | Description
64402  * :-----------------------------------------|:------|:------------
64403  * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_E_DISD | 0x0 |
64404  * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_E_END | 0x1 |
64405  *
64406  * Field Access Macros:
64407  *
64408  */
64409 /*
64410  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE
64411  *
64412  */
64413 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_E_DISD 0x0
64414 /*
64415  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE
64416  *
64417  */
64418 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_E_END 0x1
64419 
64420 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field. */
64421 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_LSB 31
64422 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field. */
64423 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_MSB 31
64424 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field. */
64425 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_WIDTH 1
64426 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field value. */
64427 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_SET_MSK 0x80000000
64428 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field value. */
64429 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_CLR_MSK 0x7fffffff
64430 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field. */
64431 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_RESET 0x0
64432 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE field value from a register. */
64433 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
64434 /* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field value suitable for setting the register. */
64435 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
64436 
64437 #ifndef __ASSEMBLY__
64438 /*
64439  * WARNING: The C register and register group struct declarations are provided for
64440  * convenience and illustrative purposes. They should, however, be used with
64441  * caution as the C language standard provides no guarantees about the alignment or
64442  * atomicity of device memory accesses. The recommended practice for writing
64443  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
64444  * alt_write_word() functions.
64445  *
64446  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR112_HIGH.
64447  */
64448 struct ALT_EMAC_GMAC_MAC_ADDR112_HIGH_s
64449 {
64450  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI */
64451  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR112_HIGH_RSVD_30_16 */
64452  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE */
64453 };
64454 
64455 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR112_HIGH. */
64456 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR112_HIGH_s ALT_EMAC_GMAC_MAC_ADDR112_HIGH_t;
64457 #endif /* __ASSEMBLY__ */
64458 
64459 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH register. */
64460 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_RESET 0x0000ffff
64461 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH register from the beginning of the component. */
64462 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_OFST 0xb00
64463 /* The address of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH register. */
64464 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR112_HIGH_OFST))
64465 
64466 /*
64467  * Register : gmacgrp_mac_address112_low
64468  *
64469  * <b> Register 704 (MAC Address112 Low Register)</b>
64470  *
64471  * The MAC Address112 Low register holds the lower 32 bits of the 113th 6-byte MAC
64472  * address of the station.
64473  *
64474  * Register Layout
64475  *
64476  * Bits | Access | Reset | Description
64477  * :-------|:-------|:-----------|:-------------------------------------
64478  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO
64479  *
64480  */
64481 /*
64482  * Field : addrlo
64483  *
64484  * MAC Address112 [31:0]
64485  *
64486  * This field contains the lower 32 bits of the 113th 6-byte MAC address. The
64487  * content of this field is undefined until loaded by the Application after the
64488  * initialization process.
64489  *
64490  * Field Access Macros:
64491  *
64492  */
64493 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field. */
64494 #define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_LSB 0
64495 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field. */
64496 #define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_MSB 31
64497 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field. */
64498 #define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_WIDTH 32
64499 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field value. */
64500 #define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_SET_MSK 0xffffffff
64501 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field value. */
64502 #define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_CLR_MSK 0x00000000
64503 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field. */
64504 #define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_RESET 0xffffffff
64505 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO field value from a register. */
64506 #define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
64507 /* Produces a ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field value suitable for setting the register. */
64508 #define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
64509 
64510 #ifndef __ASSEMBLY__
64511 /*
64512  * WARNING: The C register and register group struct declarations are provided for
64513  * convenience and illustrative purposes. They should, however, be used with
64514  * caution as the C language standard provides no guarantees about the alignment or
64515  * atomicity of device memory accesses. The recommended practice for writing
64516  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
64517  * alt_write_word() functions.
64518  *
64519  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR112_LOW.
64520  */
64521 struct ALT_EMAC_GMAC_MAC_ADDR112_LOW_s
64522 {
64523  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO */
64524 };
64525 
64526 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR112_LOW. */
64527 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR112_LOW_s ALT_EMAC_GMAC_MAC_ADDR112_LOW_t;
64528 #endif /* __ASSEMBLY__ */
64529 
64530 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_LOW register. */
64531 #define ALT_EMAC_GMAC_MAC_ADDR112_LOW_RESET 0xffffffff
64532 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR112_LOW register from the beginning of the component. */
64533 #define ALT_EMAC_GMAC_MAC_ADDR112_LOW_OFST 0xb04
64534 /* The address of the ALT_EMAC_GMAC_MAC_ADDR112_LOW register. */
64535 #define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR112_LOW_OFST))
64536 
64537 /*
64538  * Register : gmacgrp_mac_address113_high
64539  *
64540  * <b> Register 705 (MAC Address113 High Register)</b>
64541  *
64542  * The MAC Address113 High register holds the upper 16 bits of the 114th 6-byte MAC
64543  * address of the station.
64544  *
64545  * If the MAC address registers are configured to be double-synchronized to the
64546  * (G)MII clock domains, then
64547  *
64548  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
64549  * or Bits[7:0] (in big-endian mode) of the MAC Address113 Low Register are
64550  * written. For proper synchronization updates, consecutive writes to this MAC
64551  * Address113 Low Register must be performed after at least four clock cycles in
64552  * the destination clock domain.
64553  *
64554  * Register Layout
64555  *
64556  * Bits | Access | Reset | Description
64557  * :--------|:-------|:-------|:------------------------------------------
64558  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI
64559  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR113_HIGH_RSVD_30_16
64560  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE
64561  *
64562  */
64563 /*
64564  * Field : addrhi
64565  *
64566  * MAC Address113 [47:32]
64567  *
64568  * This field contains the upper 16 bits (47:32) of the 114th 6-byte MAC address.
64569  *
64570  * Field Access Macros:
64571  *
64572  */
64573 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field. */
64574 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_LSB 0
64575 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field. */
64576 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_MSB 15
64577 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field. */
64578 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_WIDTH 16
64579 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field value. */
64580 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_SET_MSK 0x0000ffff
64581 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field value. */
64582 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_CLR_MSK 0xffff0000
64583 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field. */
64584 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_RESET 0xffff
64585 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI field value from a register. */
64586 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
64587 /* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field value suitable for setting the register. */
64588 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
64589 
64590 /*
64591  * Field : reserved_30_16
64592  *
64593  * Reserved
64594  *
64595  * Field Access Macros:
64596  *
64597  */
64598 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_RSVD_30_16 register field. */
64599 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_RSVD_30_16_LSB 16
64600 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_RSVD_30_16 register field. */
64601 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_RSVD_30_16_MSB 30
64602 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_RSVD_30_16 register field. */
64603 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_RSVD_30_16_WIDTH 15
64604 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_RSVD_30_16 register field value. */
64605 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
64606 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_RSVD_30_16 register field value. */
64607 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
64608 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_RSVD_30_16 register field. */
64609 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_RSVD_30_16_RESET 0x0
64610 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_RSVD_30_16 field value from a register. */
64611 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
64612 /* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_RSVD_30_16 register field value suitable for setting the register. */
64613 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
64614 
64615 /*
64616  * Field : ae
64617  *
64618  * Address Enable
64619  *
64620  * When this bit is set, the address filter module uses the 114th MAC address for
64621  * perfect filtering.
64622  *
64623  * When this bit is reset, the address filter module ignores the address for
64624  * filtering.
64625  *
64626  * Field Enumeration Values:
64627  *
64628  * Enum | Value | Description
64629  * :-----------------------------------------|:------|:------------
64630  * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_E_DISD | 0x0 |
64631  * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_E_END | 0x1 |
64632  *
64633  * Field Access Macros:
64634  *
64635  */
64636 /*
64637  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE
64638  *
64639  */
64640 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_E_DISD 0x0
64641 /*
64642  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE
64643  *
64644  */
64645 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_E_END 0x1
64646 
64647 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field. */
64648 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_LSB 31
64649 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field. */
64650 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_MSB 31
64651 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field. */
64652 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_WIDTH 1
64653 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field value. */
64654 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_SET_MSK 0x80000000
64655 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field value. */
64656 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_CLR_MSK 0x7fffffff
64657 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field. */
64658 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_RESET 0x0
64659 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE field value from a register. */
64660 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
64661 /* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field value suitable for setting the register. */
64662 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
64663 
64664 #ifndef __ASSEMBLY__
64665 /*
64666  * WARNING: The C register and register group struct declarations are provided for
64667  * convenience and illustrative purposes. They should, however, be used with
64668  * caution as the C language standard provides no guarantees about the alignment or
64669  * atomicity of device memory accesses. The recommended practice for writing
64670  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
64671  * alt_write_word() functions.
64672  *
64673  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR113_HIGH.
64674  */
64675 struct ALT_EMAC_GMAC_MAC_ADDR113_HIGH_s
64676 {
64677  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI */
64678  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR113_HIGH_RSVD_30_16 */
64679  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE */
64680 };
64681 
64682 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR113_HIGH. */
64683 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR113_HIGH_s ALT_EMAC_GMAC_MAC_ADDR113_HIGH_t;
64684 #endif /* __ASSEMBLY__ */
64685 
64686 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH register. */
64687 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_RESET 0x0000ffff
64688 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH register from the beginning of the component. */
64689 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_OFST 0xb08
64690 /* The address of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH register. */
64691 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR113_HIGH_OFST))
64692 
64693 /*
64694  * Register : gmacgrp_mac_address113_low
64695  *
64696  * <b> Register 706 (MAC Address113 Low Register)</b>
64697  *
64698  * The MAC Address113 Low register holds the lower 32 bits of the 114th 6-byte MAC
64699  * address of the station.
64700  *
64701  * Register Layout
64702  *
64703  * Bits | Access | Reset | Description
64704  * :-------|:-------|:-----------|:-------------------------------------
64705  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO
64706  *
64707  */
64708 /*
64709  * Field : addrlo
64710  *
64711  * MAC Address113 [31:0]
64712  *
64713  * This field contains the lower 32 bits of the 114th 6-byte MAC address. The
64714  * content of this field is undefined until loaded by the Application after the
64715  * initialization process.
64716  *
64717  * Field Access Macros:
64718  *
64719  */
64720 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field. */
64721 #define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_LSB 0
64722 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field. */
64723 #define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_MSB 31
64724 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field. */
64725 #define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_WIDTH 32
64726 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field value. */
64727 #define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_SET_MSK 0xffffffff
64728 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field value. */
64729 #define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_CLR_MSK 0x00000000
64730 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field. */
64731 #define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_RESET 0xffffffff
64732 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO field value from a register. */
64733 #define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
64734 /* Produces a ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field value suitable for setting the register. */
64735 #define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
64736 
64737 #ifndef __ASSEMBLY__
64738 /*
64739  * WARNING: The C register and register group struct declarations are provided for
64740  * convenience and illustrative purposes. They should, however, be used with
64741  * caution as the C language standard provides no guarantees about the alignment or
64742  * atomicity of device memory accesses. The recommended practice for writing
64743  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
64744  * alt_write_word() functions.
64745  *
64746  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR113_LOW.
64747  */
64748 struct ALT_EMAC_GMAC_MAC_ADDR113_LOW_s
64749 {
64750  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO */
64751 };
64752 
64753 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR113_LOW. */
64754 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR113_LOW_s ALT_EMAC_GMAC_MAC_ADDR113_LOW_t;
64755 #endif /* __ASSEMBLY__ */
64756 
64757 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_LOW register. */
64758 #define ALT_EMAC_GMAC_MAC_ADDR113_LOW_RESET 0xffffffff
64759 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR113_LOW register from the beginning of the component. */
64760 #define ALT_EMAC_GMAC_MAC_ADDR113_LOW_OFST 0xb0c
64761 /* The address of the ALT_EMAC_GMAC_MAC_ADDR113_LOW register. */
64762 #define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR113_LOW_OFST))
64763 
64764 /*
64765  * Register : gmacgrp_mac_address114_high
64766  *
64767  * <b> Register 707 (MAC Address114 High Register)</b>
64768  *
64769  * The MAC Address114 High register holds the upper 16 bits of the 115th 6-byte MAC
64770  * address of the station.
64771  *
64772  * If the MAC address registers are configured to be double-synchronized to the
64773  * (G)MII clock domains, then
64774  *
64775  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
64776  * or Bits[7:0] (in big-endian mode) of the MAC Address114 Low Register are
64777  * written. For proper synchronization updates, consecutive writes to this MAC
64778  * Address114 Low Register must be performed after at least four clock cycles in
64779  * the destination clock domain.
64780  *
64781  * Register Layout
64782  *
64783  * Bits | Access | Reset | Description
64784  * :--------|:-------|:-------|:------------------------------------------
64785  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI
64786  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR114_HIGH_RSVD_30_16
64787  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE
64788  *
64789  */
64790 /*
64791  * Field : addrhi
64792  *
64793  * MAC Address114 [47:32]
64794  *
64795  * This field contains the upper 16 bits (47:32) of the 115th 6-byte MAC address.
64796  *
64797  * Field Access Macros:
64798  *
64799  */
64800 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field. */
64801 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_LSB 0
64802 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field. */
64803 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_MSB 15
64804 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field. */
64805 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_WIDTH 16
64806 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field value. */
64807 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_SET_MSK 0x0000ffff
64808 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field value. */
64809 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_CLR_MSK 0xffff0000
64810 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field. */
64811 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_RESET 0xffff
64812 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI field value from a register. */
64813 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
64814 /* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field value suitable for setting the register. */
64815 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
64816 
64817 /*
64818  * Field : reserved_30_16
64819  *
64820  * Reserved
64821  *
64822  * Field Access Macros:
64823  *
64824  */
64825 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_RSVD_30_16 register field. */
64826 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_RSVD_30_16_LSB 16
64827 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_RSVD_30_16 register field. */
64828 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_RSVD_30_16_MSB 30
64829 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_RSVD_30_16 register field. */
64830 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_RSVD_30_16_WIDTH 15
64831 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_RSVD_30_16 register field value. */
64832 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
64833 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_RSVD_30_16 register field value. */
64834 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
64835 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_RSVD_30_16 register field. */
64836 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_RSVD_30_16_RESET 0x0
64837 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_RSVD_30_16 field value from a register. */
64838 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
64839 /* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_RSVD_30_16 register field value suitable for setting the register. */
64840 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
64841 
64842 /*
64843  * Field : ae
64844  *
64845  * Address Enable
64846  *
64847  * When this bit is set, the address filter module uses the 115th MAC address for
64848  * perfect filtering.
64849  *
64850  * When this bit is reset, the address filter module ignores the address for
64851  * filtering.
64852  *
64853  * Field Enumeration Values:
64854  *
64855  * Enum | Value | Description
64856  * :-----------------------------------------|:------|:------------
64857  * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_E_DISD | 0x0 |
64858  * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_E_END | 0x1 |
64859  *
64860  * Field Access Macros:
64861  *
64862  */
64863 /*
64864  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE
64865  *
64866  */
64867 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_E_DISD 0x0
64868 /*
64869  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE
64870  *
64871  */
64872 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_E_END 0x1
64873 
64874 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field. */
64875 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_LSB 31
64876 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field. */
64877 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_MSB 31
64878 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field. */
64879 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_WIDTH 1
64880 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field value. */
64881 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_SET_MSK 0x80000000
64882 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field value. */
64883 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_CLR_MSK 0x7fffffff
64884 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field. */
64885 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_RESET 0x0
64886 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE field value from a register. */
64887 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
64888 /* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field value suitable for setting the register. */
64889 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
64890 
64891 #ifndef __ASSEMBLY__
64892 /*
64893  * WARNING: The C register and register group struct declarations are provided for
64894  * convenience and illustrative purposes. They should, however, be used with
64895  * caution as the C language standard provides no guarantees about the alignment or
64896  * atomicity of device memory accesses. The recommended practice for writing
64897  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
64898  * alt_write_word() functions.
64899  *
64900  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR114_HIGH.
64901  */
64902 struct ALT_EMAC_GMAC_MAC_ADDR114_HIGH_s
64903 {
64904  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI */
64905  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR114_HIGH_RSVD_30_16 */
64906  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE */
64907 };
64908 
64909 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR114_HIGH. */
64910 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR114_HIGH_s ALT_EMAC_GMAC_MAC_ADDR114_HIGH_t;
64911 #endif /* __ASSEMBLY__ */
64912 
64913 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH register. */
64914 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_RESET 0x0000ffff
64915 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH register from the beginning of the component. */
64916 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_OFST 0xb10
64917 /* The address of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH register. */
64918 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR114_HIGH_OFST))
64919 
64920 /*
64921  * Register : gmacgrp_mac_address114_low
64922  *
64923  * <b> Register 708 (MAC Address114 Low Register)</b>
64924  *
64925  * The MAC Address114 Low register holds the lower 32 bits of the 115th 6-byte MAC
64926  * address of the station.
64927  *
64928  * Register Layout
64929  *
64930  * Bits | Access | Reset | Description
64931  * :-------|:-------|:-----------|:-------------------------------------
64932  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO
64933  *
64934  */
64935 /*
64936  * Field : addrlo
64937  *
64938  * MAC Address114 [31:0]
64939  *
64940  * This field contains the lower 32 bits of the 115th 6-byte MAC address. The
64941  * content of this field is undefined until loaded by the Application after the
64942  * initialization process.
64943  *
64944  * Field Access Macros:
64945  *
64946  */
64947 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field. */
64948 #define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_LSB 0
64949 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field. */
64950 #define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_MSB 31
64951 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field. */
64952 #define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_WIDTH 32
64953 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field value. */
64954 #define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_SET_MSK 0xffffffff
64955 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field value. */
64956 #define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_CLR_MSK 0x00000000
64957 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field. */
64958 #define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_RESET 0xffffffff
64959 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO field value from a register. */
64960 #define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
64961 /* Produces a ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field value suitable for setting the register. */
64962 #define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
64963 
64964 #ifndef __ASSEMBLY__
64965 /*
64966  * WARNING: The C register and register group struct declarations are provided for
64967  * convenience and illustrative purposes. They should, however, be used with
64968  * caution as the C language standard provides no guarantees about the alignment or
64969  * atomicity of device memory accesses. The recommended practice for writing
64970  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
64971  * alt_write_word() functions.
64972  *
64973  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR114_LOW.
64974  */
64975 struct ALT_EMAC_GMAC_MAC_ADDR114_LOW_s
64976 {
64977  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO */
64978 };
64979 
64980 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR114_LOW. */
64981 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR114_LOW_s ALT_EMAC_GMAC_MAC_ADDR114_LOW_t;
64982 #endif /* __ASSEMBLY__ */
64983 
64984 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_LOW register. */
64985 #define ALT_EMAC_GMAC_MAC_ADDR114_LOW_RESET 0xffffffff
64986 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR114_LOW register from the beginning of the component. */
64987 #define ALT_EMAC_GMAC_MAC_ADDR114_LOW_OFST 0xb14
64988 /* The address of the ALT_EMAC_GMAC_MAC_ADDR114_LOW register. */
64989 #define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR114_LOW_OFST))
64990 
64991 /*
64992  * Register : gmacgrp_mac_address115_high
64993  *
64994  * <b> Register 709 (MAC Address115 High Register)</b>
64995  *
64996  * The MAC Address115 High register holds the upper 16 bits of the 116th 6-byte MAC
64997  * address of the station.
64998  *
64999  * If the MAC address registers are configured to be double-synchronized to the
65000  * (G)MII clock domains, then
65001  *
65002  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
65003  * or Bits[7:0] (in big-endian mode) of the MAC Address115 Low Register are
65004  * written. For proper synchronization updates, consecutive writes to this MAC
65005  * Address115 Low Register must be performed after at least four clock cycles in
65006  * the destination clock domain.
65007  *
65008  * Register Layout
65009  *
65010  * Bits | Access | Reset | Description
65011  * :--------|:-------|:-------|:------------------------------------------
65012  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI
65013  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR115_HIGH_RSVD_30_16
65014  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE
65015  *
65016  */
65017 /*
65018  * Field : addrhi
65019  *
65020  * MAC Address115 [47:32]
65021  *
65022  * This field contains the upper 16 bits (47:32) of the 116th 6-byte MAC address.
65023  *
65024  * Field Access Macros:
65025  *
65026  */
65027 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field. */
65028 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_LSB 0
65029 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field. */
65030 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_MSB 15
65031 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field. */
65032 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_WIDTH 16
65033 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field value. */
65034 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_SET_MSK 0x0000ffff
65035 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field value. */
65036 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_CLR_MSK 0xffff0000
65037 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field. */
65038 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_RESET 0xffff
65039 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI field value from a register. */
65040 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
65041 /* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field value suitable for setting the register. */
65042 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
65043 
65044 /*
65045  * Field : reserved_30_16
65046  *
65047  * Reserved
65048  *
65049  * Field Access Macros:
65050  *
65051  */
65052 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_RSVD_30_16 register field. */
65053 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_RSVD_30_16_LSB 16
65054 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_RSVD_30_16 register field. */
65055 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_RSVD_30_16_MSB 30
65056 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_RSVD_30_16 register field. */
65057 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_RSVD_30_16_WIDTH 15
65058 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_RSVD_30_16 register field value. */
65059 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
65060 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_RSVD_30_16 register field value. */
65061 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
65062 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_RSVD_30_16 register field. */
65063 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_RSVD_30_16_RESET 0x0
65064 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_RSVD_30_16 field value from a register. */
65065 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
65066 /* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_RSVD_30_16 register field value suitable for setting the register. */
65067 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
65068 
65069 /*
65070  * Field : ae
65071  *
65072  * Address Enable
65073  *
65074  * When this bit is set, the address filter module uses the 116th MAC address for
65075  * perfect filtering.
65076  *
65077  * When this bit is reset, the address filter module ignores the address for
65078  * filtering.
65079  *
65080  * Field Enumeration Values:
65081  *
65082  * Enum | Value | Description
65083  * :-----------------------------------------|:------|:------------
65084  * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_E_DISD | 0x0 |
65085  * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_E_END | 0x1 |
65086  *
65087  * Field Access Macros:
65088  *
65089  */
65090 /*
65091  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE
65092  *
65093  */
65094 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_E_DISD 0x0
65095 /*
65096  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE
65097  *
65098  */
65099 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_E_END 0x1
65100 
65101 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field. */
65102 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_LSB 31
65103 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field. */
65104 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_MSB 31
65105 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field. */
65106 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_WIDTH 1
65107 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field value. */
65108 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_SET_MSK 0x80000000
65109 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field value. */
65110 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_CLR_MSK 0x7fffffff
65111 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field. */
65112 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_RESET 0x0
65113 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE field value from a register. */
65114 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
65115 /* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field value suitable for setting the register. */
65116 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
65117 
65118 #ifndef __ASSEMBLY__
65119 /*
65120  * WARNING: The C register and register group struct declarations are provided for
65121  * convenience and illustrative purposes. They should, however, be used with
65122  * caution as the C language standard provides no guarantees about the alignment or
65123  * atomicity of device memory accesses. The recommended practice for writing
65124  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
65125  * alt_write_word() functions.
65126  *
65127  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR115_HIGH.
65128  */
65129 struct ALT_EMAC_GMAC_MAC_ADDR115_HIGH_s
65130 {
65131  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI */
65132  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR115_HIGH_RSVD_30_16 */
65133  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE */
65134 };
65135 
65136 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR115_HIGH. */
65137 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR115_HIGH_s ALT_EMAC_GMAC_MAC_ADDR115_HIGH_t;
65138 #endif /* __ASSEMBLY__ */
65139 
65140 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH register. */
65141 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_RESET 0x0000ffff
65142 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH register from the beginning of the component. */
65143 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_OFST 0xb18
65144 /* The address of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH register. */
65145 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR115_HIGH_OFST))
65146 
65147 /*
65148  * Register : gmacgrp_mac_address115_low
65149  *
65150  * <b> Register 710 (MAC Address115 Low Register)</b>
65151  *
65152  * The MAC Address115 Low register holds the lower 32 bits of the 116th 6-byte MAC
65153  * address of the station.
65154  *
65155  * Register Layout
65156  *
65157  * Bits | Access | Reset | Description
65158  * :-------|:-------|:-----------|:-------------------------------------
65159  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO
65160  *
65161  */
65162 /*
65163  * Field : addrlo
65164  *
65165  * MAC Address115 [31:0]
65166  *
65167  * This field contains the lower 32 bits of the 116th 6-byte MAC address. The
65168  * content of this field is undefined until loaded by the Application after the
65169  * initialization process.
65170  *
65171  * Field Access Macros:
65172  *
65173  */
65174 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field. */
65175 #define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_LSB 0
65176 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field. */
65177 #define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_MSB 31
65178 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field. */
65179 #define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_WIDTH 32
65180 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field value. */
65181 #define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_SET_MSK 0xffffffff
65182 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field value. */
65183 #define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_CLR_MSK 0x00000000
65184 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field. */
65185 #define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_RESET 0xffffffff
65186 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO field value from a register. */
65187 #define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
65188 /* Produces a ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field value suitable for setting the register. */
65189 #define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
65190 
65191 #ifndef __ASSEMBLY__
65192 /*
65193  * WARNING: The C register and register group struct declarations are provided for
65194  * convenience and illustrative purposes. They should, however, be used with
65195  * caution as the C language standard provides no guarantees about the alignment or
65196  * atomicity of device memory accesses. The recommended practice for writing
65197  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
65198  * alt_write_word() functions.
65199  *
65200  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR115_LOW.
65201  */
65202 struct ALT_EMAC_GMAC_MAC_ADDR115_LOW_s
65203 {
65204  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO */
65205 };
65206 
65207 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR115_LOW. */
65208 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR115_LOW_s ALT_EMAC_GMAC_MAC_ADDR115_LOW_t;
65209 #endif /* __ASSEMBLY__ */
65210 
65211 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_LOW register. */
65212 #define ALT_EMAC_GMAC_MAC_ADDR115_LOW_RESET 0xffffffff
65213 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR115_LOW register from the beginning of the component. */
65214 #define ALT_EMAC_GMAC_MAC_ADDR115_LOW_OFST 0xb1c
65215 /* The address of the ALT_EMAC_GMAC_MAC_ADDR115_LOW register. */
65216 #define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR115_LOW_OFST))
65217 
65218 /*
65219  * Register : gmacgrp_mac_address116_high
65220  *
65221  * <b> Register 711 (MAC Address116 High Register)</b>
65222  *
65223  * The MAC Address116 High register holds the upper 16 bits of the 117th 6-byte MAC
65224  * address of the station.
65225  *
65226  * If the MAC address registers are configured to be double-synchronized to the
65227  * (G)MII clock domains, then
65228  *
65229  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
65230  * or Bits[7:0] (in big-endian mode) of the MAC Address116 Low Register are
65231  * written. For proper synchronization updates, consecutive writes to this MAC
65232  * Address116 Low Register must be performed after at least four clock cycles in
65233  * the destination clock domain.
65234  *
65235  * Register Layout
65236  *
65237  * Bits | Access | Reset | Description
65238  * :--------|:-------|:-------|:------------------------------------------
65239  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI
65240  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR116_HIGH_RSVD_30_16
65241  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE
65242  *
65243  */
65244 /*
65245  * Field : addrhi
65246  *
65247  * MAC Address116 [47:32]
65248  *
65249  * This field contains the upper 16 bits (47:32) of the 117th 6-byte MAC address.
65250  *
65251  * Field Access Macros:
65252  *
65253  */
65254 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field. */
65255 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_LSB 0
65256 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field. */
65257 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_MSB 15
65258 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field. */
65259 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_WIDTH 16
65260 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field value. */
65261 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_SET_MSK 0x0000ffff
65262 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field value. */
65263 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_CLR_MSK 0xffff0000
65264 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field. */
65265 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_RESET 0xffff
65266 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI field value from a register. */
65267 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
65268 /* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field value suitable for setting the register. */
65269 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
65270 
65271 /*
65272  * Field : reserved_30_16
65273  *
65274  * Reserved
65275  *
65276  * Field Access Macros:
65277  *
65278  */
65279 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_RSVD_30_16 register field. */
65280 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_RSVD_30_16_LSB 16
65281 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_RSVD_30_16 register field. */
65282 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_RSVD_30_16_MSB 30
65283 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_RSVD_30_16 register field. */
65284 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_RSVD_30_16_WIDTH 15
65285 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_RSVD_30_16 register field value. */
65286 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
65287 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_RSVD_30_16 register field value. */
65288 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
65289 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_RSVD_30_16 register field. */
65290 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_RSVD_30_16_RESET 0x0
65291 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_RSVD_30_16 field value from a register. */
65292 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
65293 /* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_RSVD_30_16 register field value suitable for setting the register. */
65294 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
65295 
65296 /*
65297  * Field : ae
65298  *
65299  * Address Enable
65300  *
65301  * When this bit is set, the address filter module uses the 117th MAC address for
65302  * perfect filtering.
65303  *
65304  * When this bit is reset, the address filter module ignores the address for
65305  * filtering.
65306  *
65307  * Field Enumeration Values:
65308  *
65309  * Enum | Value | Description
65310  * :-----------------------------------------|:------|:------------
65311  * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_E_DISD | 0x0 |
65312  * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_E_END | 0x1 |
65313  *
65314  * Field Access Macros:
65315  *
65316  */
65317 /*
65318  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE
65319  *
65320  */
65321 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_E_DISD 0x0
65322 /*
65323  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE
65324  *
65325  */
65326 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_E_END 0x1
65327 
65328 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field. */
65329 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_LSB 31
65330 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field. */
65331 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_MSB 31
65332 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field. */
65333 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_WIDTH 1
65334 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field value. */
65335 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_SET_MSK 0x80000000
65336 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field value. */
65337 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_CLR_MSK 0x7fffffff
65338 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field. */
65339 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_RESET 0x0
65340 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE field value from a register. */
65341 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
65342 /* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field value suitable for setting the register. */
65343 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
65344 
65345 #ifndef __ASSEMBLY__
65346 /*
65347  * WARNING: The C register and register group struct declarations are provided for
65348  * convenience and illustrative purposes. They should, however, be used with
65349  * caution as the C language standard provides no guarantees about the alignment or
65350  * atomicity of device memory accesses. The recommended practice for writing
65351  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
65352  * alt_write_word() functions.
65353  *
65354  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR116_HIGH.
65355  */
65356 struct ALT_EMAC_GMAC_MAC_ADDR116_HIGH_s
65357 {
65358  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI */
65359  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR116_HIGH_RSVD_30_16 */
65360  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE */
65361 };
65362 
65363 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR116_HIGH. */
65364 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR116_HIGH_s ALT_EMAC_GMAC_MAC_ADDR116_HIGH_t;
65365 #endif /* __ASSEMBLY__ */
65366 
65367 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH register. */
65368 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_RESET 0x0000ffff
65369 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH register from the beginning of the component. */
65370 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_OFST 0xb20
65371 /* The address of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH register. */
65372 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR116_HIGH_OFST))
65373 
65374 /*
65375  * Register : gmacgrp_mac_address116_low
65376  *
65377  * <b> Register 712 (MAC Address116 Low Register)</b>
65378  *
65379  * The MAC Address116 Low register holds the lower 32 bits of the 117th 6-byte MAC
65380  * address of the station.
65381  *
65382  * Register Layout
65383  *
65384  * Bits | Access | Reset | Description
65385  * :-------|:-------|:-----------|:-------------------------------------
65386  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO
65387  *
65388  */
65389 /*
65390  * Field : addrlo
65391  *
65392  * MAC Address116 [31:0]
65393  *
65394  * This field contains the lower 32 bits of the 117th 6-byte MAC address. The
65395  * content of this field is undefined until loaded by the Application after the
65396  * initialization process.
65397  *
65398  * Field Access Macros:
65399  *
65400  */
65401 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field. */
65402 #define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_LSB 0
65403 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field. */
65404 #define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_MSB 31
65405 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field. */
65406 #define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_WIDTH 32
65407 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field value. */
65408 #define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_SET_MSK 0xffffffff
65409 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field value. */
65410 #define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_CLR_MSK 0x00000000
65411 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field. */
65412 #define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_RESET 0xffffffff
65413 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO field value from a register. */
65414 #define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
65415 /* Produces a ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field value suitable for setting the register. */
65416 #define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
65417 
65418 #ifndef __ASSEMBLY__
65419 /*
65420  * WARNING: The C register and register group struct declarations are provided for
65421  * convenience and illustrative purposes. They should, however, be used with
65422  * caution as the C language standard provides no guarantees about the alignment or
65423  * atomicity of device memory accesses. The recommended practice for writing
65424  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
65425  * alt_write_word() functions.
65426  *
65427  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR116_LOW.
65428  */
65429 struct ALT_EMAC_GMAC_MAC_ADDR116_LOW_s
65430 {
65431  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO */
65432 };
65433 
65434 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR116_LOW. */
65435 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR116_LOW_s ALT_EMAC_GMAC_MAC_ADDR116_LOW_t;
65436 #endif /* __ASSEMBLY__ */
65437 
65438 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_LOW register. */
65439 #define ALT_EMAC_GMAC_MAC_ADDR116_LOW_RESET 0xffffffff
65440 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR116_LOW register from the beginning of the component. */
65441 #define ALT_EMAC_GMAC_MAC_ADDR116_LOW_OFST 0xb24
65442 /* The address of the ALT_EMAC_GMAC_MAC_ADDR116_LOW register. */
65443 #define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR116_LOW_OFST))
65444 
65445 /*
65446  * Register : gmacgrp_mac_address117_high
65447  *
65448  * <b> Register 713 (MAC Address117 High Register)</b>
65449  *
65450  * The MAC Address117 High register holds the upper 16 bits of the 118th 6-byte MAC
65451  * address of the station.
65452  *
65453  * If the MAC address registers are configured to be double-synchronized to the
65454  * (G)MII clock domains, then
65455  *
65456  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
65457  * or Bits[7:0] (in big-endian mode) of the MAC Address117 Low Register are
65458  * written. For proper synchronization updates, consecutive writes to this MAC
65459  * Address117 Low Register must be performed after at least four clock cycles in
65460  * the destination clock domain.
65461  *
65462  * Register Layout
65463  *
65464  * Bits | Access | Reset | Description
65465  * :--------|:-------|:-------|:------------------------------------------
65466  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI
65467  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR117_HIGH_RSVD_30_16
65468  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE
65469  *
65470  */
65471 /*
65472  * Field : addrhi
65473  *
65474  * MAC Address117 [47:32]
65475  *
65476  * This field contains the upper 16 bits (47:32) of the 118th 6-byte MAC address.
65477  *
65478  * Field Access Macros:
65479  *
65480  */
65481 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field. */
65482 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_LSB 0
65483 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field. */
65484 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_MSB 15
65485 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field. */
65486 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_WIDTH 16
65487 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field value. */
65488 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_SET_MSK 0x0000ffff
65489 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field value. */
65490 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_CLR_MSK 0xffff0000
65491 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field. */
65492 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_RESET 0xffff
65493 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI field value from a register. */
65494 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
65495 /* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field value suitable for setting the register. */
65496 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
65497 
65498 /*
65499  * Field : reserved_30_16
65500  *
65501  * Reserved
65502  *
65503  * Field Access Macros:
65504  *
65505  */
65506 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_RSVD_30_16 register field. */
65507 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_RSVD_30_16_LSB 16
65508 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_RSVD_30_16 register field. */
65509 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_RSVD_30_16_MSB 30
65510 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_RSVD_30_16 register field. */
65511 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_RSVD_30_16_WIDTH 15
65512 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_RSVD_30_16 register field value. */
65513 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
65514 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_RSVD_30_16 register field value. */
65515 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
65516 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_RSVD_30_16 register field. */
65517 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_RSVD_30_16_RESET 0x0
65518 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_RSVD_30_16 field value from a register. */
65519 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
65520 /* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_RSVD_30_16 register field value suitable for setting the register. */
65521 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
65522 
65523 /*
65524  * Field : ae
65525  *
65526  * Address Enable
65527  *
65528  * When this bit is set, the address filter module uses the 118th MAC address for
65529  * perfect filtering.
65530  *
65531  * When this bit is reset, the address filter module ignores the address for
65532  * filtering.
65533  *
65534  * Field Enumeration Values:
65535  *
65536  * Enum | Value | Description
65537  * :-----------------------------------------|:------|:------------
65538  * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_E_DISD | 0x0 |
65539  * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_E_END | 0x1 |
65540  *
65541  * Field Access Macros:
65542  *
65543  */
65544 /*
65545  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE
65546  *
65547  */
65548 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_E_DISD 0x0
65549 /*
65550  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE
65551  *
65552  */
65553 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_E_END 0x1
65554 
65555 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field. */
65556 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_LSB 31
65557 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field. */
65558 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_MSB 31
65559 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field. */
65560 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_WIDTH 1
65561 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field value. */
65562 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_SET_MSK 0x80000000
65563 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field value. */
65564 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_CLR_MSK 0x7fffffff
65565 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field. */
65566 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_RESET 0x0
65567 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE field value from a register. */
65568 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
65569 /* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field value suitable for setting the register. */
65570 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
65571 
65572 #ifndef __ASSEMBLY__
65573 /*
65574  * WARNING: The C register and register group struct declarations are provided for
65575  * convenience and illustrative purposes. They should, however, be used with
65576  * caution as the C language standard provides no guarantees about the alignment or
65577  * atomicity of device memory accesses. The recommended practice for writing
65578  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
65579  * alt_write_word() functions.
65580  *
65581  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR117_HIGH.
65582  */
65583 struct ALT_EMAC_GMAC_MAC_ADDR117_HIGH_s
65584 {
65585  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI */
65586  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR117_HIGH_RSVD_30_16 */
65587  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE */
65588 };
65589 
65590 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR117_HIGH. */
65591 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR117_HIGH_s ALT_EMAC_GMAC_MAC_ADDR117_HIGH_t;
65592 #endif /* __ASSEMBLY__ */
65593 
65594 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH register. */
65595 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_RESET 0x0000ffff
65596 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH register from the beginning of the component. */
65597 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_OFST 0xb28
65598 /* The address of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH register. */
65599 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR117_HIGH_OFST))
65600 
65601 /*
65602  * Register : gmacgrp_mac_address117_low
65603  *
65604  * <b> Register 714 (MAC Address117 Low Register)</b>
65605  *
65606  * The MAC Address117 Low register holds the lower 32 bits of the 118th 6-byte MAC
65607  * address of the station.
65608  *
65609  * Register Layout
65610  *
65611  * Bits | Access | Reset | Description
65612  * :-------|:-------|:-----------|:-------------------------------------
65613  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO
65614  *
65615  */
65616 /*
65617  * Field : addrlo
65618  *
65619  * MAC Address117 [31:0]
65620  *
65621  * This field contains the lower 32 bits of the 118t118thh 6-byte MAC address. The
65622  * content of this field is undefined until loaded by the Application after the
65623  * initialization process.
65624  *
65625  * Field Access Macros:
65626  *
65627  */
65628 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field. */
65629 #define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_LSB 0
65630 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field. */
65631 #define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_MSB 31
65632 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field. */
65633 #define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_WIDTH 32
65634 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field value. */
65635 #define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_SET_MSK 0xffffffff
65636 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field value. */
65637 #define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_CLR_MSK 0x00000000
65638 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field. */
65639 #define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_RESET 0xffffffff
65640 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO field value from a register. */
65641 #define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
65642 /* Produces a ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field value suitable for setting the register. */
65643 #define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
65644 
65645 #ifndef __ASSEMBLY__
65646 /*
65647  * WARNING: The C register and register group struct declarations are provided for
65648  * convenience and illustrative purposes. They should, however, be used with
65649  * caution as the C language standard provides no guarantees about the alignment or
65650  * atomicity of device memory accesses. The recommended practice for writing
65651  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
65652  * alt_write_word() functions.
65653  *
65654  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR117_LOW.
65655  */
65656 struct ALT_EMAC_GMAC_MAC_ADDR117_LOW_s
65657 {
65658  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO */
65659 };
65660 
65661 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR117_LOW. */
65662 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR117_LOW_s ALT_EMAC_GMAC_MAC_ADDR117_LOW_t;
65663 #endif /* __ASSEMBLY__ */
65664 
65665 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_LOW register. */
65666 #define ALT_EMAC_GMAC_MAC_ADDR117_LOW_RESET 0xffffffff
65667 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR117_LOW register from the beginning of the component. */
65668 #define ALT_EMAC_GMAC_MAC_ADDR117_LOW_OFST 0xb2c
65669 /* The address of the ALT_EMAC_GMAC_MAC_ADDR117_LOW register. */
65670 #define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR117_LOW_OFST))
65671 
65672 /*
65673  * Register : gmacgrp_mac_address118_high
65674  *
65675  * <b> Register 715 (MAC Address118 High Register)</b>
65676  *
65677  * The MAC Address118 High register holds the upper 16 bits of the 119th 6-byte MAC
65678  * address of the station.
65679  *
65680  * If the MAC address registers are configured to be double-synchronized to the
65681  * (G)MII clock domains, then
65682  *
65683  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
65684  * or Bits[7:0] (in big-endian mode) of the MAC Address118 Low Register are
65685  * written. For proper synchronization updates, consecutive writes to this MAC
65686  * Address118 Low Register must be performed after at least four clock cycles in
65687  * the destination clock domain.
65688  *
65689  * Register Layout
65690  *
65691  * Bits | Access | Reset | Description
65692  * :--------|:-------|:-------|:------------------------------------------
65693  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI
65694  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR118_HIGH_RSVD_30_16
65695  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE
65696  *
65697  */
65698 /*
65699  * Field : addrhi
65700  *
65701  * MAC Address118 [47:32]
65702  *
65703  * This field contains the upper 16 bits (47:32) of the 119th 6-byte MAC address.
65704  *
65705  * Field Access Macros:
65706  *
65707  */
65708 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field. */
65709 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_LSB 0
65710 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field. */
65711 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_MSB 15
65712 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field. */
65713 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_WIDTH 16
65714 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field value. */
65715 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_SET_MSK 0x0000ffff
65716 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field value. */
65717 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_CLR_MSK 0xffff0000
65718 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field. */
65719 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_RESET 0xffff
65720 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI field value from a register. */
65721 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
65722 /* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field value suitable for setting the register. */
65723 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
65724 
65725 /*
65726  * Field : reserved_30_16
65727  *
65728  * Reserved
65729  *
65730  * Field Access Macros:
65731  *
65732  */
65733 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_RSVD_30_16 register field. */
65734 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_RSVD_30_16_LSB 16
65735 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_RSVD_30_16 register field. */
65736 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_RSVD_30_16_MSB 30
65737 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_RSVD_30_16 register field. */
65738 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_RSVD_30_16_WIDTH 15
65739 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_RSVD_30_16 register field value. */
65740 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
65741 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_RSVD_30_16 register field value. */
65742 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
65743 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_RSVD_30_16 register field. */
65744 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_RSVD_30_16_RESET 0x0
65745 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_RSVD_30_16 field value from a register. */
65746 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
65747 /* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_RSVD_30_16 register field value suitable for setting the register. */
65748 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
65749 
65750 /*
65751  * Field : ae
65752  *
65753  * Address Enable
65754  *
65755  * When this bit is set, the address filter module uses the 119th MAC address for
65756  * perfect filtering.
65757  *
65758  * When this bit is reset, the address filter module ignores the address for
65759  * filtering.
65760  *
65761  * Field Enumeration Values:
65762  *
65763  * Enum | Value | Description
65764  * :-----------------------------------------|:------|:------------
65765  * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_E_DISD | 0x0 |
65766  * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_E_END | 0x1 |
65767  *
65768  * Field Access Macros:
65769  *
65770  */
65771 /*
65772  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE
65773  *
65774  */
65775 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_E_DISD 0x0
65776 /*
65777  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE
65778  *
65779  */
65780 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_E_END 0x1
65781 
65782 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field. */
65783 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_LSB 31
65784 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field. */
65785 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_MSB 31
65786 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field. */
65787 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_WIDTH 1
65788 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field value. */
65789 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_SET_MSK 0x80000000
65790 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field value. */
65791 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_CLR_MSK 0x7fffffff
65792 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field. */
65793 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_RESET 0x0
65794 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE field value from a register. */
65795 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
65796 /* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field value suitable for setting the register. */
65797 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
65798 
65799 #ifndef __ASSEMBLY__
65800 /*
65801  * WARNING: The C register and register group struct declarations are provided for
65802  * convenience and illustrative purposes. They should, however, be used with
65803  * caution as the C language standard provides no guarantees about the alignment or
65804  * atomicity of device memory accesses. The recommended practice for writing
65805  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
65806  * alt_write_word() functions.
65807  *
65808  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR118_HIGH.
65809  */
65810 struct ALT_EMAC_GMAC_MAC_ADDR118_HIGH_s
65811 {
65812  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI */
65813  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR118_HIGH_RSVD_30_16 */
65814  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE */
65815 };
65816 
65817 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR118_HIGH. */
65818 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR118_HIGH_s ALT_EMAC_GMAC_MAC_ADDR118_HIGH_t;
65819 #endif /* __ASSEMBLY__ */
65820 
65821 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH register. */
65822 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_RESET 0x0000ffff
65823 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH register from the beginning of the component. */
65824 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_OFST 0xb30
65825 /* The address of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH register. */
65826 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR118_HIGH_OFST))
65827 
65828 /*
65829  * Register : gmacgrp_mac_address118_low
65830  *
65831  * <b> Register 716 (MAC Address118 Low Register)</b>
65832  *
65833  * The MAC Address118 Low register holds the lower 32 bits of the 119th 6-byte MAC
65834  * address of the station.
65835  *
65836  * Register Layout
65837  *
65838  * Bits | Access | Reset | Description
65839  * :-------|:-------|:-----------|:-------------------------------------
65840  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO
65841  *
65842  */
65843 /*
65844  * Field : addrlo
65845  *
65846  * MAC Address118 [31:0]
65847  *
65848  * This field contains the lower 32 bits of the 119th 6-byte MAC address. The
65849  * content of this field is undefined until loaded by the Application after the
65850  * initialization process.
65851  *
65852  * Field Access Macros:
65853  *
65854  */
65855 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field. */
65856 #define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_LSB 0
65857 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field. */
65858 #define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_MSB 31
65859 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field. */
65860 #define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_WIDTH 32
65861 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field value. */
65862 #define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_SET_MSK 0xffffffff
65863 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field value. */
65864 #define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_CLR_MSK 0x00000000
65865 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field. */
65866 #define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_RESET 0xffffffff
65867 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO field value from a register. */
65868 #define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
65869 /* Produces a ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field value suitable for setting the register. */
65870 #define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
65871 
65872 #ifndef __ASSEMBLY__
65873 /*
65874  * WARNING: The C register and register group struct declarations are provided for
65875  * convenience and illustrative purposes. They should, however, be used with
65876  * caution as the C language standard provides no guarantees about the alignment or
65877  * atomicity of device memory accesses. The recommended practice for writing
65878  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
65879  * alt_write_word() functions.
65880  *
65881  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR118_LOW.
65882  */
65883 struct ALT_EMAC_GMAC_MAC_ADDR118_LOW_s
65884 {
65885  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO */
65886 };
65887 
65888 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR118_LOW. */
65889 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR118_LOW_s ALT_EMAC_GMAC_MAC_ADDR118_LOW_t;
65890 #endif /* __ASSEMBLY__ */
65891 
65892 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_LOW register. */
65893 #define ALT_EMAC_GMAC_MAC_ADDR118_LOW_RESET 0xffffffff
65894 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR118_LOW register from the beginning of the component. */
65895 #define ALT_EMAC_GMAC_MAC_ADDR118_LOW_OFST 0xb34
65896 /* The address of the ALT_EMAC_GMAC_MAC_ADDR118_LOW register. */
65897 #define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR118_LOW_OFST))
65898 
65899 /*
65900  * Register : gmacgrp_mac_address119_high
65901  *
65902  * <b> Register 717 (MAC Address119 High Register)</b>
65903  *
65904  * The MAC Address119 High register holds the upper 16 bits of the 120th 6-byte MAC
65905  * address of the station.
65906  *
65907  * If the MAC address registers are configured to be double-synchronized to the
65908  * (G)MII clock domains, then
65909  *
65910  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
65911  * or Bits[7:0] (in big-endian mode) of the MAC Address119 Low Register are
65912  * written. For proper synchronization updates, consecutive writes to this MAC
65913  * Address119 Low Register must be performed after at least four clock cycles in
65914  * the destination clock domain.
65915  *
65916  * Register Layout
65917  *
65918  * Bits | Access | Reset | Description
65919  * :--------|:-------|:-------|:------------------------------------------
65920  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI
65921  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR119_HIGH_RSVD_30_16
65922  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE
65923  *
65924  */
65925 /*
65926  * Field : addrhi
65927  *
65928  * MAC Address119 [47:32]
65929  *
65930  * This field contains the upper 16 bits (47:32) of the 120th 6-byte MAC address.
65931  *
65932  * Field Access Macros:
65933  *
65934  */
65935 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field. */
65936 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_LSB 0
65937 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field. */
65938 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_MSB 15
65939 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field. */
65940 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_WIDTH 16
65941 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field value. */
65942 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_SET_MSK 0x0000ffff
65943 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field value. */
65944 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_CLR_MSK 0xffff0000
65945 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field. */
65946 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_RESET 0xffff
65947 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI field value from a register. */
65948 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
65949 /* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field value suitable for setting the register. */
65950 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
65951 
65952 /*
65953  * Field : reserved_30_16
65954  *
65955  * Reserved
65956  *
65957  * Field Access Macros:
65958  *
65959  */
65960 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_RSVD_30_16 register field. */
65961 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_RSVD_30_16_LSB 16
65962 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_RSVD_30_16 register field. */
65963 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_RSVD_30_16_MSB 30
65964 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_RSVD_30_16 register field. */
65965 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_RSVD_30_16_WIDTH 15
65966 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_RSVD_30_16 register field value. */
65967 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
65968 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_RSVD_30_16 register field value. */
65969 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
65970 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_RSVD_30_16 register field. */
65971 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_RSVD_30_16_RESET 0x0
65972 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_RSVD_30_16 field value from a register. */
65973 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
65974 /* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_RSVD_30_16 register field value suitable for setting the register. */
65975 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
65976 
65977 /*
65978  * Field : ae
65979  *
65980  * Address Enable
65981  *
65982  * When this bit is set, the address filter module uses the 120th MAC address for
65983  * perfect filtering.
65984  *
65985  * When this bit is reset, the address filter module ignores the address for
65986  * filtering.
65987  *
65988  * Field Enumeration Values:
65989  *
65990  * Enum | Value | Description
65991  * :-----------------------------------------|:------|:------------
65992  * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_E_DISD | 0x0 |
65993  * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_E_END | 0x1 |
65994  *
65995  * Field Access Macros:
65996  *
65997  */
65998 /*
65999  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE
66000  *
66001  */
66002 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_E_DISD 0x0
66003 /*
66004  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE
66005  *
66006  */
66007 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_E_END 0x1
66008 
66009 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field. */
66010 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_LSB 31
66011 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field. */
66012 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_MSB 31
66013 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field. */
66014 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_WIDTH 1
66015 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field value. */
66016 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_SET_MSK 0x80000000
66017 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field value. */
66018 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_CLR_MSK 0x7fffffff
66019 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field. */
66020 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_RESET 0x0
66021 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE field value from a register. */
66022 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
66023 /* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field value suitable for setting the register. */
66024 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
66025 
66026 #ifndef __ASSEMBLY__
66027 /*
66028  * WARNING: The C register and register group struct declarations are provided for
66029  * convenience and illustrative purposes. They should, however, be used with
66030  * caution as the C language standard provides no guarantees about the alignment or
66031  * atomicity of device memory accesses. The recommended practice for writing
66032  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
66033  * alt_write_word() functions.
66034  *
66035  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR119_HIGH.
66036  */
66037 struct ALT_EMAC_GMAC_MAC_ADDR119_HIGH_s
66038 {
66039  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI */
66040  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR119_HIGH_RSVD_30_16 */
66041  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE */
66042 };
66043 
66044 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR119_HIGH. */
66045 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR119_HIGH_s ALT_EMAC_GMAC_MAC_ADDR119_HIGH_t;
66046 #endif /* __ASSEMBLY__ */
66047 
66048 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH register. */
66049 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_RESET 0x0000ffff
66050 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH register from the beginning of the component. */
66051 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_OFST 0xb38
66052 /* The address of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH register. */
66053 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR119_HIGH_OFST))
66054 
66055 /*
66056  * Register : gmacgrp_mac_address119_low
66057  *
66058  * <b> Register 718 (MAC Address119 Low Register)</b>
66059  *
66060  * The MAC Address119 Low register holds the lower 32 bits of the 120th 6-byte MAC
66061  * address of the station.
66062  *
66063  * Register Layout
66064  *
66065  * Bits | Access | Reset | Description
66066  * :-------|:-------|:-----------|:-------------------------------------
66067  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO
66068  *
66069  */
66070 /*
66071  * Field : addrlo
66072  *
66073  * MAC Address119 [31:0]
66074  *
66075  * This field contains the lower 32 bits of the 120th 6-byte MAC address. The
66076  * content of this field is undefined until loaded by the Application after the
66077  * initialization process.
66078  *
66079  * Field Access Macros:
66080  *
66081  */
66082 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field. */
66083 #define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_LSB 0
66084 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field. */
66085 #define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_MSB 31
66086 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field. */
66087 #define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_WIDTH 32
66088 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field value. */
66089 #define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_SET_MSK 0xffffffff
66090 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field value. */
66091 #define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_CLR_MSK 0x00000000
66092 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field. */
66093 #define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_RESET 0xffffffff
66094 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO field value from a register. */
66095 #define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
66096 /* Produces a ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field value suitable for setting the register. */
66097 #define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
66098 
66099 #ifndef __ASSEMBLY__
66100 /*
66101  * WARNING: The C register and register group struct declarations are provided for
66102  * convenience and illustrative purposes. They should, however, be used with
66103  * caution as the C language standard provides no guarantees about the alignment or
66104  * atomicity of device memory accesses. The recommended practice for writing
66105  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
66106  * alt_write_word() functions.
66107  *
66108  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR119_LOW.
66109  */
66110 struct ALT_EMAC_GMAC_MAC_ADDR119_LOW_s
66111 {
66112  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO */
66113 };
66114 
66115 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR119_LOW. */
66116 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR119_LOW_s ALT_EMAC_GMAC_MAC_ADDR119_LOW_t;
66117 #endif /* __ASSEMBLY__ */
66118 
66119 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_LOW register. */
66120 #define ALT_EMAC_GMAC_MAC_ADDR119_LOW_RESET 0xffffffff
66121 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR119_LOW register from the beginning of the component. */
66122 #define ALT_EMAC_GMAC_MAC_ADDR119_LOW_OFST 0xb3c
66123 /* The address of the ALT_EMAC_GMAC_MAC_ADDR119_LOW register. */
66124 #define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR119_LOW_OFST))
66125 
66126 /*
66127  * Register : gmacgrp_mac_address120_high
66128  *
66129  * <b> Register 719 (MAC Address120 High Register)</b>
66130  *
66131  * The MAC Address120 High register holds the upper 16 bits of the 6-byte 121st MAC
66132  * address of the station.
66133  *
66134  * If the MAC address registers are configured to be double-synchronized to the
66135  * (G)MII clock domains, then
66136  *
66137  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
66138  * or Bits[7:0] (in big-endian mode) of the MAC Address120 Low Register are
66139  * written. For proper synchronization updates, consecutive writes to this MAC
66140  * Address120 Low Register must be performed after at least four clock cycles in
66141  * the destination clock domain.
66142  *
66143  * Register Layout
66144  *
66145  * Bits | Access | Reset | Description
66146  * :--------|:-------|:-------|:------------------------------------------
66147  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI
66148  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR120_HIGH_RSVD_30_16
66149  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE
66150  *
66151  */
66152 /*
66153  * Field : addrhi
66154  *
66155  * MAC Address120 [47:32]
66156  *
66157  * This field contains the upper 16 bits (47:32) of the 6-byte 121st MAC address.
66158  *
66159  * Field Access Macros:
66160  *
66161  */
66162 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field. */
66163 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_LSB 0
66164 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field. */
66165 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_MSB 15
66166 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field. */
66167 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_WIDTH 16
66168 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field value. */
66169 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_SET_MSK 0x0000ffff
66170 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field value. */
66171 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_CLR_MSK 0xffff0000
66172 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field. */
66173 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_RESET 0xffff
66174 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI field value from a register. */
66175 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
66176 /* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field value suitable for setting the register. */
66177 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
66178 
66179 /*
66180  * Field : reserved_30_16
66181  *
66182  * Reserved
66183  *
66184  * Field Access Macros:
66185  *
66186  */
66187 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_RSVD_30_16 register field. */
66188 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_RSVD_30_16_LSB 16
66189 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_RSVD_30_16 register field. */
66190 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_RSVD_30_16_MSB 30
66191 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_RSVD_30_16 register field. */
66192 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_RSVD_30_16_WIDTH 15
66193 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_RSVD_30_16 register field value. */
66194 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
66195 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_RSVD_30_16 register field value. */
66196 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
66197 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_RSVD_30_16 register field. */
66198 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_RSVD_30_16_RESET 0x0
66199 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_RSVD_30_16 field value from a register. */
66200 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
66201 /* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_RSVD_30_16 register field value suitable for setting the register. */
66202 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
66203 
66204 /*
66205  * Field : ae
66206  *
66207  * Address Enable
66208  *
66209  * When this bit is set, the address filter module uses the 121st MAC address for
66210  * perfect filtering.
66211  *
66212  * When this bit is reset, the address filter module ignores the address for
66213  * filtering.
66214  *
66215  * Field Enumeration Values:
66216  *
66217  * Enum | Value | Description
66218  * :-----------------------------------------|:------|:------------
66219  * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_E_DISD | 0x0 |
66220  * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_E_END | 0x1 |
66221  *
66222  * Field Access Macros:
66223  *
66224  */
66225 /*
66226  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE
66227  *
66228  */
66229 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_E_DISD 0x0
66230 /*
66231  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE
66232  *
66233  */
66234 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_E_END 0x1
66235 
66236 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field. */
66237 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_LSB 31
66238 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field. */
66239 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_MSB 31
66240 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field. */
66241 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_WIDTH 1
66242 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field value. */
66243 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_SET_MSK 0x80000000
66244 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field value. */
66245 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_CLR_MSK 0x7fffffff
66246 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field. */
66247 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_RESET 0x0
66248 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE field value from a register. */
66249 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
66250 /* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field value suitable for setting the register. */
66251 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
66252 
66253 #ifndef __ASSEMBLY__
66254 /*
66255  * WARNING: The C register and register group struct declarations are provided for
66256  * convenience and illustrative purposes. They should, however, be used with
66257  * caution as the C language standard provides no guarantees about the alignment or
66258  * atomicity of device memory accesses. The recommended practice for writing
66259  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
66260  * alt_write_word() functions.
66261  *
66262  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR120_HIGH.
66263  */
66264 struct ALT_EMAC_GMAC_MAC_ADDR120_HIGH_s
66265 {
66266  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI */
66267  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR120_HIGH_RSVD_30_16 */
66268  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE */
66269 };
66270 
66271 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR120_HIGH. */
66272 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR120_HIGH_s ALT_EMAC_GMAC_MAC_ADDR120_HIGH_t;
66273 #endif /* __ASSEMBLY__ */
66274 
66275 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH register. */
66276 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_RESET 0x0000ffff
66277 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH register from the beginning of the component. */
66278 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_OFST 0xb40
66279 /* The address of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH register. */
66280 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR120_HIGH_OFST))
66281 
66282 /*
66283  * Register : gmacgrp_mac_address120_low
66284  *
66285  * <b> Register 720 (MAC Address120 Low Register)</b>
66286  *
66287  * The MAC Address120 Low register holds the lower 32 bits of the 121st 6-byte MAC
66288  * address of the station.
66289  *
66290  * Register Layout
66291  *
66292  * Bits | Access | Reset | Description
66293  * :-------|:-------|:-----------|:-------------------------------------
66294  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO
66295  *
66296  */
66297 /*
66298  * Field : addrlo
66299  *
66300  * MAC Address120 [31:0]
66301  *
66302  * This field contains the lower 32 bits of the 122nd 6-byte MAC address. The
66303  * content of this field is undefined until loaded by the Application after the
66304  * initialization process.
66305  *
66306  * Field Access Macros:
66307  *
66308  */
66309 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field. */
66310 #define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_LSB 0
66311 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field. */
66312 #define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_MSB 31
66313 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field. */
66314 #define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_WIDTH 32
66315 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field value. */
66316 #define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_SET_MSK 0xffffffff
66317 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field value. */
66318 #define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_CLR_MSK 0x00000000
66319 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field. */
66320 #define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_RESET 0xffffffff
66321 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO field value from a register. */
66322 #define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
66323 /* Produces a ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field value suitable for setting the register. */
66324 #define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
66325 
66326 #ifndef __ASSEMBLY__
66327 /*
66328  * WARNING: The C register and register group struct declarations are provided for
66329  * convenience and illustrative purposes. They should, however, be used with
66330  * caution as the C language standard provides no guarantees about the alignment or
66331  * atomicity of device memory accesses. The recommended practice for writing
66332  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
66333  * alt_write_word() functions.
66334  *
66335  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR120_LOW.
66336  */
66337 struct ALT_EMAC_GMAC_MAC_ADDR120_LOW_s
66338 {
66339  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO */
66340 };
66341 
66342 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR120_LOW. */
66343 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR120_LOW_s ALT_EMAC_GMAC_MAC_ADDR120_LOW_t;
66344 #endif /* __ASSEMBLY__ */
66345 
66346 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_LOW register. */
66347 #define ALT_EMAC_GMAC_MAC_ADDR120_LOW_RESET 0xffffffff
66348 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR120_LOW register from the beginning of the component. */
66349 #define ALT_EMAC_GMAC_MAC_ADDR120_LOW_OFST 0xb44
66350 /* The address of the ALT_EMAC_GMAC_MAC_ADDR120_LOW register. */
66351 #define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR120_LOW_OFST))
66352 
66353 /*
66354  * Register : gmacgrp_mac_address121_high
66355  *
66356  * <b> Register 721 (MAC Address121 High Register)</b>
66357  *
66358  * The MAC Address121 High register holds the upper 16 bits of the 122nd 6-byte MAC
66359  * address of the station.
66360  *
66361  * If the MAC address registers are configured to be double-synchronized to the
66362  * (G)MII clock domains, then
66363  *
66364  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
66365  * or Bits[7:0] (in big-endian mode) of the MAC Address121 Low Register are
66366  * written. For proper synchronization updates, consecutive writes to this MAC
66367  * Address121 Low Register must be performed after at least four clock cycles in
66368  * the destination clock domain.
66369  *
66370  * Register Layout
66371  *
66372  * Bits | Access | Reset | Description
66373  * :--------|:-------|:-------|:------------------------------------------
66374  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI
66375  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR121_HIGH_RSVD_30_16
66376  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE
66377  *
66378  */
66379 /*
66380  * Field : addrhi
66381  *
66382  * MAC Address121 [47:32]
66383  *
66384  * This field contains the upper 16 bits (47:32) of the 122nd 6-byte MAC address.
66385  *
66386  * Field Access Macros:
66387  *
66388  */
66389 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field. */
66390 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_LSB 0
66391 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field. */
66392 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_MSB 15
66393 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field. */
66394 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_WIDTH 16
66395 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field value. */
66396 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_SET_MSK 0x0000ffff
66397 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field value. */
66398 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_CLR_MSK 0xffff0000
66399 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field. */
66400 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_RESET 0xffff
66401 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI field value from a register. */
66402 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
66403 /* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field value suitable for setting the register. */
66404 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
66405 
66406 /*
66407  * Field : reserved_30_16
66408  *
66409  * Reserved
66410  *
66411  * Field Access Macros:
66412  *
66413  */
66414 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_RSVD_30_16 register field. */
66415 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_RSVD_30_16_LSB 16
66416 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_RSVD_30_16 register field. */
66417 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_RSVD_30_16_MSB 30
66418 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_RSVD_30_16 register field. */
66419 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_RSVD_30_16_WIDTH 15
66420 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_RSVD_30_16 register field value. */
66421 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
66422 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_RSVD_30_16 register field value. */
66423 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
66424 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_RSVD_30_16 register field. */
66425 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_RSVD_30_16_RESET 0x0
66426 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_RSVD_30_16 field value from a register. */
66427 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
66428 /* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_RSVD_30_16 register field value suitable for setting the register. */
66429 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
66430 
66431 /*
66432  * Field : ae
66433  *
66434  * Address Enable
66435  *
66436  * When this bit is set, the address filter module uses the 122nd MAC address for
66437  * perfect filtering.
66438  *
66439  * When this bit is reset, the address filter module ignores the address for
66440  * filtering.
66441  *
66442  * Field Enumeration Values:
66443  *
66444  * Enum | Value | Description
66445  * :-----------------------------------------|:------|:------------
66446  * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_E_DISD | 0x0 |
66447  * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_E_END | 0x1 |
66448  *
66449  * Field Access Macros:
66450  *
66451  */
66452 /*
66453  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE
66454  *
66455  */
66456 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_E_DISD 0x0
66457 /*
66458  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE
66459  *
66460  */
66461 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_E_END 0x1
66462 
66463 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field. */
66464 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_LSB 31
66465 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field. */
66466 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_MSB 31
66467 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field. */
66468 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_WIDTH 1
66469 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field value. */
66470 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_SET_MSK 0x80000000
66471 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field value. */
66472 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_CLR_MSK 0x7fffffff
66473 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field. */
66474 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_RESET 0x0
66475 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE field value from a register. */
66476 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
66477 /* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field value suitable for setting the register. */
66478 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
66479 
66480 #ifndef __ASSEMBLY__
66481 /*
66482  * WARNING: The C register and register group struct declarations are provided for
66483  * convenience and illustrative purposes. They should, however, be used with
66484  * caution as the C language standard provides no guarantees about the alignment or
66485  * atomicity of device memory accesses. The recommended practice for writing
66486  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
66487  * alt_write_word() functions.
66488  *
66489  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR121_HIGH.
66490  */
66491 struct ALT_EMAC_GMAC_MAC_ADDR121_HIGH_s
66492 {
66493  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI */
66494  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR121_HIGH_RSVD_30_16 */
66495  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE */
66496 };
66497 
66498 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR121_HIGH. */
66499 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR121_HIGH_s ALT_EMAC_GMAC_MAC_ADDR121_HIGH_t;
66500 #endif /* __ASSEMBLY__ */
66501 
66502 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH register. */
66503 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_RESET 0x0000ffff
66504 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH register from the beginning of the component. */
66505 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_OFST 0xb48
66506 /* The address of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH register. */
66507 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR121_HIGH_OFST))
66508 
66509 /*
66510  * Register : gmacgrp_mac_address121_low
66511  *
66512  * <b> Register 722 (MAC Address121 Low Register)</b>
66513  *
66514  * The MAC Address121 Low register holds the lower 32 bits of the 122nd 6-byte MAC
66515  * address of the station.
66516  *
66517  * Register Layout
66518  *
66519  * Bits | Access | Reset | Description
66520  * :-------|:-------|:-----------|:-------------------------------------
66521  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO
66522  *
66523  */
66524 /*
66525  * Field : addrlo
66526  *
66527  * MAC Address121 [31:0]
66528  *
66529  * This field contains the lower 32 bits of the 122nd 6-byte MAC address. The
66530  * content of this field is undefined until loaded by the Application after the
66531  * initialization process.
66532  *
66533  * Field Access Macros:
66534  *
66535  */
66536 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field. */
66537 #define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_LSB 0
66538 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field. */
66539 #define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_MSB 31
66540 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field. */
66541 #define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_WIDTH 32
66542 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field value. */
66543 #define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_SET_MSK 0xffffffff
66544 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field value. */
66545 #define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_CLR_MSK 0x00000000
66546 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field. */
66547 #define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_RESET 0xffffffff
66548 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO field value from a register. */
66549 #define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
66550 /* Produces a ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field value suitable for setting the register. */
66551 #define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
66552 
66553 #ifndef __ASSEMBLY__
66554 /*
66555  * WARNING: The C register and register group struct declarations are provided for
66556  * convenience and illustrative purposes. They should, however, be used with
66557  * caution as the C language standard provides no guarantees about the alignment or
66558  * atomicity of device memory accesses. The recommended practice for writing
66559  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
66560  * alt_write_word() functions.
66561  *
66562  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR121_LOW.
66563  */
66564 struct ALT_EMAC_GMAC_MAC_ADDR121_LOW_s
66565 {
66566  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO */
66567 };
66568 
66569 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR121_LOW. */
66570 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR121_LOW_s ALT_EMAC_GMAC_MAC_ADDR121_LOW_t;
66571 #endif /* __ASSEMBLY__ */
66572 
66573 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_LOW register. */
66574 #define ALT_EMAC_GMAC_MAC_ADDR121_LOW_RESET 0xffffffff
66575 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR121_LOW register from the beginning of the component. */
66576 #define ALT_EMAC_GMAC_MAC_ADDR121_LOW_OFST 0xb4c
66577 /* The address of the ALT_EMAC_GMAC_MAC_ADDR121_LOW register. */
66578 #define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR121_LOW_OFST))
66579 
66580 /*
66581  * Register : gmacgrp_mac_address122_high
66582  *
66583  * <b> Register 723 (MAC Address122 High Register)</b>
66584  *
66585  * The MAC Address122 High register holds the upper 16 bits of the 123rd 6-byte MAC
66586  * address of the station.
66587  *
66588  * If the MAC address registers are configured to be double-synchronized to the
66589  * (G)MII clock domains, then
66590  *
66591  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
66592  * or Bits[7:0] (in big-endian mode) of the MAC Address122 Low Register are
66593  * written. For proper synchronization updates, consecutive writes to this MAC
66594  * Address122 Low Register must be performed after at least four clock cycles in
66595  * the destination clock domain.
66596  *
66597  * Register Layout
66598  *
66599  * Bits | Access | Reset | Description
66600  * :--------|:-------|:-------|:------------------------------------------
66601  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI
66602  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR122_HIGH_RSVD_30_16
66603  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE
66604  *
66605  */
66606 /*
66607  * Field : addrhi
66608  *
66609  * MAC Address122 [47:32]
66610  *
66611  * This field contains the upper 16 bits (47:32) of the 123rd 6-byte MAC address.
66612  *
66613  * Field Access Macros:
66614  *
66615  */
66616 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field. */
66617 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_LSB 0
66618 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field. */
66619 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_MSB 15
66620 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field. */
66621 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_WIDTH 16
66622 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field value. */
66623 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_SET_MSK 0x0000ffff
66624 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field value. */
66625 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_CLR_MSK 0xffff0000
66626 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field. */
66627 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_RESET 0xffff
66628 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI field value from a register. */
66629 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
66630 /* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field value suitable for setting the register. */
66631 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
66632 
66633 /*
66634  * Field : reserved_30_16
66635  *
66636  * Reserved
66637  *
66638  * Field Access Macros:
66639  *
66640  */
66641 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_RSVD_30_16 register field. */
66642 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_RSVD_30_16_LSB 16
66643 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_RSVD_30_16 register field. */
66644 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_RSVD_30_16_MSB 30
66645 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_RSVD_30_16 register field. */
66646 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_RSVD_30_16_WIDTH 15
66647 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_RSVD_30_16 register field value. */
66648 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
66649 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_RSVD_30_16 register field value. */
66650 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
66651 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_RSVD_30_16 register field. */
66652 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_RSVD_30_16_RESET 0x0
66653 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_RSVD_30_16 field value from a register. */
66654 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
66655 /* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_RSVD_30_16 register field value suitable for setting the register. */
66656 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
66657 
66658 /*
66659  * Field : ae
66660  *
66661  * Address Enable
66662  *
66663  * When this bit is set, the address filter module uses the 123rd MAC address for
66664  * perfect filtering.
66665  *
66666  * When this bit is reset, the address filter module ignores the address for
66667  * filtering.
66668  *
66669  * Field Enumeration Values:
66670  *
66671  * Enum | Value | Description
66672  * :-----------------------------------------|:------|:------------
66673  * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_E_DISD | 0x0 |
66674  * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_E_END | 0x1 |
66675  *
66676  * Field Access Macros:
66677  *
66678  */
66679 /*
66680  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE
66681  *
66682  */
66683 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_E_DISD 0x0
66684 /*
66685  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE
66686  *
66687  */
66688 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_E_END 0x1
66689 
66690 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field. */
66691 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_LSB 31
66692 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field. */
66693 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_MSB 31
66694 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field. */
66695 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_WIDTH 1
66696 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field value. */
66697 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_SET_MSK 0x80000000
66698 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field value. */
66699 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_CLR_MSK 0x7fffffff
66700 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field. */
66701 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_RESET 0x0
66702 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE field value from a register. */
66703 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
66704 /* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field value suitable for setting the register. */
66705 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
66706 
66707 #ifndef __ASSEMBLY__
66708 /*
66709  * WARNING: The C register and register group struct declarations are provided for
66710  * convenience and illustrative purposes. They should, however, be used with
66711  * caution as the C language standard provides no guarantees about the alignment or
66712  * atomicity of device memory accesses. The recommended practice for writing
66713  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
66714  * alt_write_word() functions.
66715  *
66716  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR122_HIGH.
66717  */
66718 struct ALT_EMAC_GMAC_MAC_ADDR122_HIGH_s
66719 {
66720  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI */
66721  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR122_HIGH_RSVD_30_16 */
66722  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE */
66723 };
66724 
66725 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR122_HIGH. */
66726 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR122_HIGH_s ALT_EMAC_GMAC_MAC_ADDR122_HIGH_t;
66727 #endif /* __ASSEMBLY__ */
66728 
66729 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH register. */
66730 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_RESET 0x0000ffff
66731 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH register from the beginning of the component. */
66732 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_OFST 0xb50
66733 /* The address of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH register. */
66734 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR122_HIGH_OFST))
66735 
66736 /*
66737  * Register : gmacgrp_mac_address122_low
66738  *
66739  * <b> Register 724 (MAC Address122 Low Register)</b>
66740  *
66741  * The MAC Address122 Low register holds the lower 32 bits of the 123rd 6-byte MAC
66742  * address of the station.
66743  *
66744  * Register Layout
66745  *
66746  * Bits | Access | Reset | Description
66747  * :-------|:-------|:-----------|:-------------------------------------
66748  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO
66749  *
66750  */
66751 /*
66752  * Field : addrlo
66753  *
66754  * MAC Address122 [31:0]
66755  *
66756  * This field contains the lower 32 bits of the 123rd 6-byte MAC address. The
66757  * content of this field is undefined until loaded by the Application after the
66758  * initialization process.
66759  *
66760  * Field Access Macros:
66761  *
66762  */
66763 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field. */
66764 #define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_LSB 0
66765 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field. */
66766 #define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_MSB 31
66767 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field. */
66768 #define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_WIDTH 32
66769 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field value. */
66770 #define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_SET_MSK 0xffffffff
66771 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field value. */
66772 #define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_CLR_MSK 0x00000000
66773 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field. */
66774 #define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_RESET 0xffffffff
66775 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO field value from a register. */
66776 #define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
66777 /* Produces a ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field value suitable for setting the register. */
66778 #define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
66779 
66780 #ifndef __ASSEMBLY__
66781 /*
66782  * WARNING: The C register and register group struct declarations are provided for
66783  * convenience and illustrative purposes. They should, however, be used with
66784  * caution as the C language standard provides no guarantees about the alignment or
66785  * atomicity of device memory accesses. The recommended practice for writing
66786  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
66787  * alt_write_word() functions.
66788  *
66789  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR122_LOW.
66790  */
66791 struct ALT_EMAC_GMAC_MAC_ADDR122_LOW_s
66792 {
66793  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO */
66794 };
66795 
66796 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR122_LOW. */
66797 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR122_LOW_s ALT_EMAC_GMAC_MAC_ADDR122_LOW_t;
66798 #endif /* __ASSEMBLY__ */
66799 
66800 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_LOW register. */
66801 #define ALT_EMAC_GMAC_MAC_ADDR122_LOW_RESET 0xffffffff
66802 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR122_LOW register from the beginning of the component. */
66803 #define ALT_EMAC_GMAC_MAC_ADDR122_LOW_OFST 0xb54
66804 /* The address of the ALT_EMAC_GMAC_MAC_ADDR122_LOW register. */
66805 #define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR122_LOW_OFST))
66806 
66807 /*
66808  * Register : gmacgrp_mac_address123_high
66809  *
66810  * <b> Register 725 (MAC Address123 High Register)</b>
66811  *
66812  * The MAC Address123 High register holds the upper 16 bits of the 124th 6-byte MAC
66813  * address of the station.
66814  *
66815  * If the MAC address registers are configured to be double-synchronized to the
66816  * (G)MII clock domains, then
66817  *
66818  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
66819  * or Bits[7:0] (in big-endian mode) of the MAC Address123 Low Register are
66820  * written. For proper synchronization updates, consecutive writes to this MAC
66821  * Address123 Low Register must be performed after at least four clock cycles in
66822  * the destination clock domain.
66823  *
66824  * Register Layout
66825  *
66826  * Bits | Access | Reset | Description
66827  * :--------|:-------|:-------|:------------------------------------------
66828  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI
66829  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR123_HIGH_RSVD_30_16
66830  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE
66831  *
66832  */
66833 /*
66834  * Field : addrhi
66835  *
66836  * MAC Address123 [47:32]
66837  *
66838  * This field contains the upper 16 bits (47:32) of the 124th 6-byte MAC address.
66839  *
66840  * Field Access Macros:
66841  *
66842  */
66843 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field. */
66844 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_LSB 0
66845 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field. */
66846 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_MSB 15
66847 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field. */
66848 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_WIDTH 16
66849 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field value. */
66850 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_SET_MSK 0x0000ffff
66851 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field value. */
66852 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_CLR_MSK 0xffff0000
66853 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field. */
66854 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_RESET 0xffff
66855 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI field value from a register. */
66856 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
66857 /* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field value suitable for setting the register. */
66858 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
66859 
66860 /*
66861  * Field : reserved_30_16
66862  *
66863  * Reserved
66864  *
66865  * Field Access Macros:
66866  *
66867  */
66868 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_RSVD_30_16 register field. */
66869 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_RSVD_30_16_LSB 16
66870 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_RSVD_30_16 register field. */
66871 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_RSVD_30_16_MSB 30
66872 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_RSVD_30_16 register field. */
66873 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_RSVD_30_16_WIDTH 15
66874 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_RSVD_30_16 register field value. */
66875 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
66876 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_RSVD_30_16 register field value. */
66877 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
66878 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_RSVD_30_16 register field. */
66879 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_RSVD_30_16_RESET 0x0
66880 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_RSVD_30_16 field value from a register. */
66881 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
66882 /* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_RSVD_30_16 register field value suitable for setting the register. */
66883 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
66884 
66885 /*
66886  * Field : ae
66887  *
66888  * Address Enable
66889  *
66890  * When this bit is set, the address filter module uses the 124th MAC address for
66891  * perfect filtering.
66892  *
66893  * When this bit is reset, the address filter module ignores the address for
66894  * filtering.
66895  *
66896  * Field Enumeration Values:
66897  *
66898  * Enum | Value | Description
66899  * :-----------------------------------------|:------|:------------
66900  * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_E_DISD | 0x0 |
66901  * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_E_END | 0x1 |
66902  *
66903  * Field Access Macros:
66904  *
66905  */
66906 /*
66907  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE
66908  *
66909  */
66910 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_E_DISD 0x0
66911 /*
66912  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE
66913  *
66914  */
66915 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_E_END 0x1
66916 
66917 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field. */
66918 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_LSB 31
66919 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field. */
66920 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_MSB 31
66921 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field. */
66922 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_WIDTH 1
66923 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field value. */
66924 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_SET_MSK 0x80000000
66925 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field value. */
66926 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_CLR_MSK 0x7fffffff
66927 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field. */
66928 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_RESET 0x0
66929 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE field value from a register. */
66930 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
66931 /* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field value suitable for setting the register. */
66932 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
66933 
66934 #ifndef __ASSEMBLY__
66935 /*
66936  * WARNING: The C register and register group struct declarations are provided for
66937  * convenience and illustrative purposes. They should, however, be used with
66938  * caution as the C language standard provides no guarantees about the alignment or
66939  * atomicity of device memory accesses. The recommended practice for writing
66940  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
66941  * alt_write_word() functions.
66942  *
66943  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR123_HIGH.
66944  */
66945 struct ALT_EMAC_GMAC_MAC_ADDR123_HIGH_s
66946 {
66947  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI */
66948  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR123_HIGH_RSVD_30_16 */
66949  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE */
66950 };
66951 
66952 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR123_HIGH. */
66953 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR123_HIGH_s ALT_EMAC_GMAC_MAC_ADDR123_HIGH_t;
66954 #endif /* __ASSEMBLY__ */
66955 
66956 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH register. */
66957 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_RESET 0x0000ffff
66958 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH register from the beginning of the component. */
66959 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_OFST 0xb58
66960 /* The address of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH register. */
66961 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR123_HIGH_OFST))
66962 
66963 /*
66964  * Register : gmacgrp_mac_address123_low
66965  *
66966  * <b> Register 726 (MAC AddressXX 123 Register)</b>
66967  *
66968  * The MAC Address123 Low register holds the lower 32 bits of the 124th 6-byte MAC
66969  * address of the station.
66970  *
66971  * Register Layout
66972  *
66973  * Bits | Access | Reset | Description
66974  * :-------|:-------|:-----------|:-------------------------------------
66975  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO
66976  *
66977  */
66978 /*
66979  * Field : addrlo
66980  *
66981  * MAC Address123 [31:0]
66982  *
66983  * This field contains the lower 32 bits of the 124th 6-byte MAC address. The
66984  * content of this field is undefined until loaded by the Application after the
66985  * initialization process.
66986  *
66987  * Field Access Macros:
66988  *
66989  */
66990 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field. */
66991 #define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_LSB 0
66992 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field. */
66993 #define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_MSB 31
66994 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field. */
66995 #define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_WIDTH 32
66996 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field value. */
66997 #define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_SET_MSK 0xffffffff
66998 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field value. */
66999 #define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_CLR_MSK 0x00000000
67000 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field. */
67001 #define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_RESET 0xffffffff
67002 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO field value from a register. */
67003 #define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
67004 /* Produces a ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field value suitable for setting the register. */
67005 #define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
67006 
67007 #ifndef __ASSEMBLY__
67008 /*
67009  * WARNING: The C register and register group struct declarations are provided for
67010  * convenience and illustrative purposes. They should, however, be used with
67011  * caution as the C language standard provides no guarantees about the alignment or
67012  * atomicity of device memory accesses. The recommended practice for writing
67013  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
67014  * alt_write_word() functions.
67015  *
67016  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR123_LOW.
67017  */
67018 struct ALT_EMAC_GMAC_MAC_ADDR123_LOW_s
67019 {
67020  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO */
67021 };
67022 
67023 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR123_LOW. */
67024 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR123_LOW_s ALT_EMAC_GMAC_MAC_ADDR123_LOW_t;
67025 #endif /* __ASSEMBLY__ */
67026 
67027 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_LOW register. */
67028 #define ALT_EMAC_GMAC_MAC_ADDR123_LOW_RESET 0xffffffff
67029 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR123_LOW register from the beginning of the component. */
67030 #define ALT_EMAC_GMAC_MAC_ADDR123_LOW_OFST 0xb5c
67031 /* The address of the ALT_EMAC_GMAC_MAC_ADDR123_LOW register. */
67032 #define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR123_LOW_OFST))
67033 
67034 /*
67035  * Register : gmacgrp_mac_address124_high
67036  *
67037  * <b> Register 727 (MAC Address124 High Register)</b>
67038  *
67039  * The MAC Address124 High register holds the upper 16 bits of the 125th 6-byte MAC
67040  * address of the station.
67041  *
67042  * If the MAC address registers are configured to be double-synchronized to the
67043  * (G)MII clock domains, then
67044  *
67045  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
67046  * or Bits[7:0] (in big-endian mode) of the MAC Address124 Low Register are
67047  * written. For proper synchronization updates, consecutive writes to this MAC
67048  * Address124 Low Register must be performed after at least four clock cycles in
67049  * the destination clock domain.
67050  *
67051  * Register Layout
67052  *
67053  * Bits | Access | Reset | Description
67054  * :--------|:-------|:-------|:------------------------------------------
67055  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI
67056  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR124_HIGH_RSVD_30_16
67057  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE
67058  *
67059  */
67060 /*
67061  * Field : addrhi
67062  *
67063  * MAC Address124 [47:32]
67064  *
67065  * This field contains the upper 16 bits (47:32) of the 125th 6-byte MAC address.
67066  *
67067  * Field Access Macros:
67068  *
67069  */
67070 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field. */
67071 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_LSB 0
67072 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field. */
67073 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_MSB 15
67074 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field. */
67075 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_WIDTH 16
67076 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field value. */
67077 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_SET_MSK 0x0000ffff
67078 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field value. */
67079 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_CLR_MSK 0xffff0000
67080 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field. */
67081 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_RESET 0xffff
67082 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI field value from a register. */
67083 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
67084 /* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field value suitable for setting the register. */
67085 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
67086 
67087 /*
67088  * Field : reserved_30_16
67089  *
67090  * Reserved
67091  *
67092  * Field Access Macros:
67093  *
67094  */
67095 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_RSVD_30_16 register field. */
67096 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_RSVD_30_16_LSB 16
67097 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_RSVD_30_16 register field. */
67098 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_RSVD_30_16_MSB 30
67099 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_RSVD_30_16 register field. */
67100 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_RSVD_30_16_WIDTH 15
67101 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_RSVD_30_16 register field value. */
67102 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
67103 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_RSVD_30_16 register field value. */
67104 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
67105 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_RSVD_30_16 register field. */
67106 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_RSVD_30_16_RESET 0x0
67107 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_RSVD_30_16 field value from a register. */
67108 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
67109 /* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_RSVD_30_16 register field value suitable for setting the register. */
67110 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
67111 
67112 /*
67113  * Field : ae
67114  *
67115  * Address Enable
67116  *
67117  * When this bit is set, the address filter module uses the 125th MAC address for
67118  * perfect filtering.
67119  *
67120  * When this bit is reset, the address filter module ignores the address for
67121  * filtering.
67122  *
67123  * Field Enumeration Values:
67124  *
67125  * Enum | Value | Description
67126  * :-----------------------------------------|:------|:------------
67127  * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_E_DISD | 0x0 |
67128  * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_E_END | 0x1 |
67129  *
67130  * Field Access Macros:
67131  *
67132  */
67133 /*
67134  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE
67135  *
67136  */
67137 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_E_DISD 0x0
67138 /*
67139  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE
67140  *
67141  */
67142 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_E_END 0x1
67143 
67144 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field. */
67145 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_LSB 31
67146 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field. */
67147 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_MSB 31
67148 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field. */
67149 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_WIDTH 1
67150 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field value. */
67151 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_SET_MSK 0x80000000
67152 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field value. */
67153 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_CLR_MSK 0x7fffffff
67154 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field. */
67155 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_RESET 0x0
67156 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE field value from a register. */
67157 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
67158 /* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field value suitable for setting the register. */
67159 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
67160 
67161 #ifndef __ASSEMBLY__
67162 /*
67163  * WARNING: The C register and register group struct declarations are provided for
67164  * convenience and illustrative purposes. They should, however, be used with
67165  * caution as the C language standard provides no guarantees about the alignment or
67166  * atomicity of device memory accesses. The recommended practice for writing
67167  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
67168  * alt_write_word() functions.
67169  *
67170  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR124_HIGH.
67171  */
67172 struct ALT_EMAC_GMAC_MAC_ADDR124_HIGH_s
67173 {
67174  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI */
67175  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR124_HIGH_RSVD_30_16 */
67176  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE */
67177 };
67178 
67179 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR124_HIGH. */
67180 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR124_HIGH_s ALT_EMAC_GMAC_MAC_ADDR124_HIGH_t;
67181 #endif /* __ASSEMBLY__ */
67182 
67183 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH register. */
67184 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_RESET 0x0000ffff
67185 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH register from the beginning of the component. */
67186 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_OFST 0xb60
67187 /* The address of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH register. */
67188 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR124_HIGH_OFST))
67189 
67190 /*
67191  * Register : gmacgrp_mac_address124_low
67192  *
67193  * <b> Register 728 (MAC Address124 Low Register)</b>
67194  *
67195  * The MAC Address124 Low register holds the lower 32 bits of the 125th 6-byte MAC
67196  * address of the station.
67197  *
67198  * Register Layout
67199  *
67200  * Bits | Access | Reset | Description
67201  * :-------|:-------|:-----------|:-------------------------------------
67202  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO
67203  *
67204  */
67205 /*
67206  * Field : addrlo
67207  *
67208  * MAC Address124 [31:0]
67209  *
67210  * This field contains the lower 32 bits of the 125th 6-byte MAC address. The
67211  * content of this field is undefined until loaded by the Application after the
67212  * initialization process.
67213  *
67214  * Field Access Macros:
67215  *
67216  */
67217 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field. */
67218 #define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_LSB 0
67219 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field. */
67220 #define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_MSB 31
67221 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field. */
67222 #define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_WIDTH 32
67223 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field value. */
67224 #define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_SET_MSK 0xffffffff
67225 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field value. */
67226 #define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_CLR_MSK 0x00000000
67227 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field. */
67228 #define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_RESET 0xffffffff
67229 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO field value from a register. */
67230 #define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
67231 /* Produces a ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field value suitable for setting the register. */
67232 #define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
67233 
67234 #ifndef __ASSEMBLY__
67235 /*
67236  * WARNING: The C register and register group struct declarations are provided for
67237  * convenience and illustrative purposes. They should, however, be used with
67238  * caution as the C language standard provides no guarantees about the alignment or
67239  * atomicity of device memory accesses. The recommended practice for writing
67240  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
67241  * alt_write_word() functions.
67242  *
67243  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR124_LOW.
67244  */
67245 struct ALT_EMAC_GMAC_MAC_ADDR124_LOW_s
67246 {
67247  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO */
67248 };
67249 
67250 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR124_LOW. */
67251 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR124_LOW_s ALT_EMAC_GMAC_MAC_ADDR124_LOW_t;
67252 #endif /* __ASSEMBLY__ */
67253 
67254 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_LOW register. */
67255 #define ALT_EMAC_GMAC_MAC_ADDR124_LOW_RESET 0xffffffff
67256 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR124_LOW register from the beginning of the component. */
67257 #define ALT_EMAC_GMAC_MAC_ADDR124_LOW_OFST 0xb64
67258 /* The address of the ALT_EMAC_GMAC_MAC_ADDR124_LOW register. */
67259 #define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR124_LOW_OFST))
67260 
67261 /*
67262  * Register : gmacgrp_mac_address125_high
67263  *
67264  * <b> Register 729 (MAC Address125 High Register)</b>
67265  *
67266  * The MAC Address125 High register holds the upper 16 bits of the 126th 6-byte MAC
67267  * address of the station.
67268  *
67269  * If the MAC address registers are configured to be double-synchronized to the
67270  * (G)MII clock domains, then
67271  *
67272  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
67273  * or Bits[7:0] (in big-endian mode) of the MAC Address125 Low Register are
67274  * written. For proper synchronization updates, consecutive writes to this MAC
67275  * Address125 Low Register must be performed after at least four clock cycles in
67276  * the destination clock domain.
67277  *
67278  * Register Layout
67279  *
67280  * Bits | Access | Reset | Description
67281  * :--------|:-------|:-------|:------------------------------------------
67282  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI
67283  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR125_HIGH_RSVD_30_16
67284  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE
67285  *
67286  */
67287 /*
67288  * Field : addrhi
67289  *
67290  * MAC Address125 [47:32]
67291  *
67292  * This field contains the upper 16 bits (47:32) of the 126th 6-byte MAC address.
67293  *
67294  * Field Access Macros:
67295  *
67296  */
67297 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field. */
67298 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_LSB 0
67299 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field. */
67300 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_MSB 15
67301 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field. */
67302 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_WIDTH 16
67303 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field value. */
67304 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_SET_MSK 0x0000ffff
67305 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field value. */
67306 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_CLR_MSK 0xffff0000
67307 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field. */
67308 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_RESET 0xffff
67309 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI field value from a register. */
67310 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
67311 /* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field value suitable for setting the register. */
67312 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
67313 
67314 /*
67315  * Field : reserved_30_16
67316  *
67317  * Reserved
67318  *
67319  * Field Access Macros:
67320  *
67321  */
67322 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_RSVD_30_16 register field. */
67323 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_RSVD_30_16_LSB 16
67324 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_RSVD_30_16 register field. */
67325 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_RSVD_30_16_MSB 30
67326 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_RSVD_30_16 register field. */
67327 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_RSVD_30_16_WIDTH 15
67328 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_RSVD_30_16 register field value. */
67329 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
67330 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_RSVD_30_16 register field value. */
67331 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
67332 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_RSVD_30_16 register field. */
67333 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_RSVD_30_16_RESET 0x0
67334 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_RSVD_30_16 field value from a register. */
67335 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
67336 /* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_RSVD_30_16 register field value suitable for setting the register. */
67337 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
67338 
67339 /*
67340  * Field : ae
67341  *
67342  * Address Enable
67343  *
67344  * When this bit is set, the address filter module uses the 126th MAC address for
67345  * perfect filtering.
67346  *
67347  * When this bit is reset, the address filter module ignores the address for
67348  * filtering.
67349  *
67350  * Field Enumeration Values:
67351  *
67352  * Enum | Value | Description
67353  * :-----------------------------------------|:------|:------------
67354  * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_E_DISD | 0x0 |
67355  * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_E_END | 0x1 |
67356  *
67357  * Field Access Macros:
67358  *
67359  */
67360 /*
67361  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE
67362  *
67363  */
67364 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_E_DISD 0x0
67365 /*
67366  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE
67367  *
67368  */
67369 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_E_END 0x1
67370 
67371 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field. */
67372 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_LSB 31
67373 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field. */
67374 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_MSB 31
67375 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field. */
67376 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_WIDTH 1
67377 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field value. */
67378 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_SET_MSK 0x80000000
67379 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field value. */
67380 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_CLR_MSK 0x7fffffff
67381 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field. */
67382 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_RESET 0x0
67383 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE field value from a register. */
67384 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
67385 /* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field value suitable for setting the register. */
67386 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
67387 
67388 #ifndef __ASSEMBLY__
67389 /*
67390  * WARNING: The C register and register group struct declarations are provided for
67391  * convenience and illustrative purposes. They should, however, be used with
67392  * caution as the C language standard provides no guarantees about the alignment or
67393  * atomicity of device memory accesses. The recommended practice for writing
67394  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
67395  * alt_write_word() functions.
67396  *
67397  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR125_HIGH.
67398  */
67399 struct ALT_EMAC_GMAC_MAC_ADDR125_HIGH_s
67400 {
67401  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI */
67402  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR125_HIGH_RSVD_30_16 */
67403  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE */
67404 };
67405 
67406 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR125_HIGH. */
67407 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR125_HIGH_s ALT_EMAC_GMAC_MAC_ADDR125_HIGH_t;
67408 #endif /* __ASSEMBLY__ */
67409 
67410 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH register. */
67411 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_RESET 0x0000ffff
67412 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH register from the beginning of the component. */
67413 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_OFST 0xb68
67414 /* The address of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH register. */
67415 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR125_HIGH_OFST))
67416 
67417 /*
67418  * Register : gmacgrp_mac_address125_low
67419  *
67420  * <b> Register 730 (MAC Address125 Low Register)</b>
67421  *
67422  * The MAC Address125 Low register holds the lower 32 bits of the 126th 6-byte MAC
67423  * address of the station.
67424  *
67425  * Register Layout
67426  *
67427  * Bits | Access | Reset | Description
67428  * :-------|:-------|:-----------|:-------------------------------------
67429  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO
67430  *
67431  */
67432 /*
67433  * Field : addrlo
67434  *
67435  * MAC Address125 [31:0]
67436  *
67437  * This field contains the lower 32 bits of the 126th 6-byte MAC address. The
67438  * content of this field is undefined until loaded by the Application after the
67439  * initialization process.
67440  *
67441  * Field Access Macros:
67442  *
67443  */
67444 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field. */
67445 #define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_LSB 0
67446 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field. */
67447 #define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_MSB 31
67448 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field. */
67449 #define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_WIDTH 32
67450 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field value. */
67451 #define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_SET_MSK 0xffffffff
67452 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field value. */
67453 #define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_CLR_MSK 0x00000000
67454 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field. */
67455 #define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_RESET 0xffffffff
67456 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO field value from a register. */
67457 #define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
67458 /* Produces a ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field value suitable for setting the register. */
67459 #define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
67460 
67461 #ifndef __ASSEMBLY__
67462 /*
67463  * WARNING: The C register and register group struct declarations are provided for
67464  * convenience and illustrative purposes. They should, however, be used with
67465  * caution as the C language standard provides no guarantees about the alignment or
67466  * atomicity of device memory accesses. The recommended practice for writing
67467  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
67468  * alt_write_word() functions.
67469  *
67470  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR125_LOW.
67471  */
67472 struct ALT_EMAC_GMAC_MAC_ADDR125_LOW_s
67473 {
67474  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO */
67475 };
67476 
67477 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR125_LOW. */
67478 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR125_LOW_s ALT_EMAC_GMAC_MAC_ADDR125_LOW_t;
67479 #endif /* __ASSEMBLY__ */
67480 
67481 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_LOW register. */
67482 #define ALT_EMAC_GMAC_MAC_ADDR125_LOW_RESET 0xffffffff
67483 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR125_LOW register from the beginning of the component. */
67484 #define ALT_EMAC_GMAC_MAC_ADDR125_LOW_OFST 0xb6c
67485 /* The address of the ALT_EMAC_GMAC_MAC_ADDR125_LOW register. */
67486 #define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR125_LOW_OFST))
67487 
67488 /*
67489  * Register : gmacgrp_mac_address126_high
67490  *
67491  * <b> Register 731 (MAC Address126 High Register)</b>
67492  *
67493  * The MAC Address126 High register holds the upper 16 bits of the 127th 6-byte MAC
67494  * address of the station.
67495  *
67496  * If the MAC address registers are configured to be double-synchronized to the
67497  * (G)MII clock domains, then
67498  *
67499  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
67500  * or Bits[7:0] (in big-endian mode) of the MAC Address126 Low Register are
67501  * written. For proper synchronization updates, consecutive writes to this MAC
67502  * Address126 Low Register must be performed after at least four clock cycles in
67503  * the destination clock domain.
67504  *
67505  * Register Layout
67506  *
67507  * Bits | Access | Reset | Description
67508  * :--------|:-------|:-------|:------------------------------------------
67509  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI
67510  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR126_HIGH_RSVD_30_16
67511  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE
67512  *
67513  */
67514 /*
67515  * Field : addrhi
67516  *
67517  * MAC Address126 [47:32]
67518  *
67519  * This field contains the upper 16 bits (47:32) of the 127th 6-byte MAC address.
67520  *
67521  * Field Access Macros:
67522  *
67523  */
67524 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field. */
67525 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_LSB 0
67526 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field. */
67527 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_MSB 15
67528 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field. */
67529 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_WIDTH 16
67530 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field value. */
67531 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_SET_MSK 0x0000ffff
67532 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field value. */
67533 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_CLR_MSK 0xffff0000
67534 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field. */
67535 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_RESET 0xffff
67536 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI field value from a register. */
67537 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
67538 /* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field value suitable for setting the register. */
67539 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
67540 
67541 /*
67542  * Field : reserved_30_16
67543  *
67544  * Reserved
67545  *
67546  * Field Access Macros:
67547  *
67548  */
67549 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_RSVD_30_16 register field. */
67550 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_RSVD_30_16_LSB 16
67551 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_RSVD_30_16 register field. */
67552 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_RSVD_30_16_MSB 30
67553 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_RSVD_30_16 register field. */
67554 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_RSVD_30_16_WIDTH 15
67555 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_RSVD_30_16 register field value. */
67556 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
67557 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_RSVD_30_16 register field value. */
67558 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
67559 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_RSVD_30_16 register field. */
67560 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_RSVD_30_16_RESET 0x0
67561 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_RSVD_30_16 field value from a register. */
67562 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
67563 /* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_RSVD_30_16 register field value suitable for setting the register. */
67564 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
67565 
67566 /*
67567  * Field : ae
67568  *
67569  * Address Enable
67570  *
67571  * When this bit is set, the address filter module uses the 127th MAC address for
67572  * perfect filtering.
67573  *
67574  * When this bit is reset, the address filter module ignores the address for
67575  * filtering.
67576  *
67577  * Field Enumeration Values:
67578  *
67579  * Enum | Value | Description
67580  * :-----------------------------------------|:------|:------------
67581  * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_E_DISD | 0x0 |
67582  * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_E_END | 0x1 |
67583  *
67584  * Field Access Macros:
67585  *
67586  */
67587 /*
67588  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE
67589  *
67590  */
67591 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_E_DISD 0x0
67592 /*
67593  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE
67594  *
67595  */
67596 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_E_END 0x1
67597 
67598 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field. */
67599 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_LSB 31
67600 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field. */
67601 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_MSB 31
67602 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field. */
67603 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_WIDTH 1
67604 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field value. */
67605 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_SET_MSK 0x80000000
67606 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field value. */
67607 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_CLR_MSK 0x7fffffff
67608 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field. */
67609 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_RESET 0x0
67610 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE field value from a register. */
67611 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
67612 /* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field value suitable for setting the register. */
67613 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
67614 
67615 #ifndef __ASSEMBLY__
67616 /*
67617  * WARNING: The C register and register group struct declarations are provided for
67618  * convenience and illustrative purposes. They should, however, be used with
67619  * caution as the C language standard provides no guarantees about the alignment or
67620  * atomicity of device memory accesses. The recommended practice for writing
67621  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
67622  * alt_write_word() functions.
67623  *
67624  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR126_HIGH.
67625  */
67626 struct ALT_EMAC_GMAC_MAC_ADDR126_HIGH_s
67627 {
67628  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI */
67629  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR126_HIGH_RSVD_30_16 */
67630  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE */
67631 };
67632 
67633 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR126_HIGH. */
67634 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR126_HIGH_s ALT_EMAC_GMAC_MAC_ADDR126_HIGH_t;
67635 #endif /* __ASSEMBLY__ */
67636 
67637 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH register. */
67638 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_RESET 0x0000ffff
67639 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH register from the beginning of the component. */
67640 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_OFST 0xb70
67641 /* The address of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH register. */
67642 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR126_HIGH_OFST))
67643 
67644 /*
67645  * Register : gmacgrp_mac_address126_low
67646  *
67647  * <b> Register 732 (MAC Address126 Low Register)</b>
67648  *
67649  * The MAC Address126 Low register holds the lower 32 bits of the 127th 6-byte MAC
67650  * address of the station.
67651  *
67652  * Register Layout
67653  *
67654  * Bits | Access | Reset | Description
67655  * :-------|:-------|:-----------|:-------------------------------------
67656  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO
67657  *
67658  */
67659 /*
67660  * Field : addrlo
67661  *
67662  * MAC Address126 [31:0]
67663  *
67664  * This field contains the lower 32 bits of the 127th 6-byte MAC address. The
67665  * content of this field is undefined until loaded by the Application after the
67666  * initialization process.
67667  *
67668  * Field Access Macros:
67669  *
67670  */
67671 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field. */
67672 #define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_LSB 0
67673 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field. */
67674 #define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_MSB 31
67675 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field. */
67676 #define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_WIDTH 32
67677 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field value. */
67678 #define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_SET_MSK 0xffffffff
67679 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field value. */
67680 #define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_CLR_MSK 0x00000000
67681 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field. */
67682 #define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_RESET 0xffffffff
67683 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO field value from a register. */
67684 #define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
67685 /* Produces a ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field value suitable for setting the register. */
67686 #define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
67687 
67688 #ifndef __ASSEMBLY__
67689 /*
67690  * WARNING: The C register and register group struct declarations are provided for
67691  * convenience and illustrative purposes. They should, however, be used with
67692  * caution as the C language standard provides no guarantees about the alignment or
67693  * atomicity of device memory accesses. The recommended practice for writing
67694  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
67695  * alt_write_word() functions.
67696  *
67697  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR126_LOW.
67698  */
67699 struct ALT_EMAC_GMAC_MAC_ADDR126_LOW_s
67700 {
67701  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO */
67702 };
67703 
67704 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR126_LOW. */
67705 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR126_LOW_s ALT_EMAC_GMAC_MAC_ADDR126_LOW_t;
67706 #endif /* __ASSEMBLY__ */
67707 
67708 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_LOW register. */
67709 #define ALT_EMAC_GMAC_MAC_ADDR126_LOW_RESET 0xffffffff
67710 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR126_LOW register from the beginning of the component. */
67711 #define ALT_EMAC_GMAC_MAC_ADDR126_LOW_OFST 0xb74
67712 /* The address of the ALT_EMAC_GMAC_MAC_ADDR126_LOW register. */
67713 #define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR126_LOW_OFST))
67714 
67715 /*
67716  * Register : gmacgrp_mac_address127_high
67717  *
67718  * <b> Register 733 (MAC Address127 High Register)</b>
67719  *
67720  * The MAC Address127 High register holds the upper 16 bits of the 128th 6-byte MAC
67721  * address of the station.
67722  *
67723  * If the MAC address registers are configured to be double-synchronized to the
67724  * (G)MII clock domains, then
67725  *
67726  * the synchronization is triggered only when Bits[31:24] (in little-endian mode)
67727  * or Bits[7:0] (in big-endian mode) of the MAC Address127 Low Register are
67728  * written. For proper synchronization updates, consecutive writes to this MAC
67729  * Address127 Low Register must be performed after at least four clock cycles in
67730  * the destination clock domain.
67731  *
67732  * Register Layout
67733  *
67734  * Bits | Access | Reset | Description
67735  * :--------|:-------|:-------|:------------------------------------------
67736  * [15:0] | RW | 0xffff | ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI
67737  * [30:16] | R | 0x0 | ALT_EMAC_GMAC_MAC_ADDR127_HIGH_RSVD_30_16
67738  * [31] | RW | 0x0 | ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE
67739  *
67740  */
67741 /*
67742  * Field : addrhi
67743  *
67744  * MAC Address127 [47:32]
67745  *
67746  * This field contains the upper 16 bits (47:32) of the 128th 6-byte MAC address.
67747  *
67748  * Field Access Macros:
67749  *
67750  */
67751 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field. */
67752 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_LSB 0
67753 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field. */
67754 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_MSB 15
67755 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field. */
67756 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_WIDTH 16
67757 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field value. */
67758 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_SET_MSK 0x0000ffff
67759 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field value. */
67760 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_CLR_MSK 0xffff0000
67761 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field. */
67762 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_RESET 0xffff
67763 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI field value from a register. */
67764 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
67765 /* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field value suitable for setting the register. */
67766 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
67767 
67768 /*
67769  * Field : reserved_30_16
67770  *
67771  * Reserved
67772  *
67773  * Field Access Macros:
67774  *
67775  */
67776 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_RSVD_30_16 register field. */
67777 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_RSVD_30_16_LSB 16
67778 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_RSVD_30_16 register field. */
67779 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_RSVD_30_16_MSB 30
67780 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_RSVD_30_16 register field. */
67781 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_RSVD_30_16_WIDTH 15
67782 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_RSVD_30_16 register field value. */
67783 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_RSVD_30_16_SET_MSK 0x7fff0000
67784 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_RSVD_30_16 register field value. */
67785 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_RSVD_30_16_CLR_MSK 0x8000ffff
67786 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_RSVD_30_16 register field. */
67787 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_RSVD_30_16_RESET 0x0
67788 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_RSVD_30_16 field value from a register. */
67789 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_RSVD_30_16_GET(value) (((value) & 0x7fff0000) >> 16)
67790 /* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_RSVD_30_16 register field value suitable for setting the register. */
67791 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_RSVD_30_16_SET(value) (((value) << 16) & 0x7fff0000)
67792 
67793 /*
67794  * Field : ae
67795  *
67796  * Address Enable
67797  *
67798  * When this bit is set, the address filter module uses the 128th MAC address for
67799  * perfect filtering.
67800  *
67801  * When this bit is reset, the address filter module ignores the address for
67802  * filtering.
67803  *
67804  * Field Enumeration Values:
67805  *
67806  * Enum | Value | Description
67807  * :-----------------------------------------|:------|:------------
67808  * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_E_DISD | 0x0 |
67809  * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_E_END | 0x1 |
67810  *
67811  * Field Access Macros:
67812  *
67813  */
67814 /*
67815  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE
67816  *
67817  */
67818 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_E_DISD 0x0
67819 /*
67820  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE
67821  *
67822  */
67823 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_E_END 0x1
67824 
67825 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field. */
67826 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_LSB 31
67827 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field. */
67828 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_MSB 31
67829 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field. */
67830 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_WIDTH 1
67831 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field value. */
67832 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_SET_MSK 0x80000000
67833 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field value. */
67834 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_CLR_MSK 0x7fffffff
67835 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field. */
67836 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_RESET 0x0
67837 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE field value from a register. */
67838 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
67839 /* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field value suitable for setting the register. */
67840 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
67841 
67842 #ifndef __ASSEMBLY__
67843 /*
67844  * WARNING: The C register and register group struct declarations are provided for
67845  * convenience and illustrative purposes. They should, however, be used with
67846  * caution as the C language standard provides no guarantees about the alignment or
67847  * atomicity of device memory accesses. The recommended practice for writing
67848  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
67849  * alt_write_word() functions.
67850  *
67851  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR127_HIGH.
67852  */
67853 struct ALT_EMAC_GMAC_MAC_ADDR127_HIGH_s
67854 {
67855  uint32_t addrhi : 16; /* ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI */
67856  const uint32_t reserved_30_16 : 15; /* ALT_EMAC_GMAC_MAC_ADDR127_HIGH_RSVD_30_16 */
67857  uint32_t ae : 1; /* ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE */
67858 };
67859 
67860 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR127_HIGH. */
67861 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR127_HIGH_s ALT_EMAC_GMAC_MAC_ADDR127_HIGH_t;
67862 #endif /* __ASSEMBLY__ */
67863 
67864 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH register. */
67865 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_RESET 0x0000ffff
67866 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH register from the beginning of the component. */
67867 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_OFST 0xb78
67868 /* The address of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH register. */
67869 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR127_HIGH_OFST))
67870 
67871 /*
67872  * Register : gmacgrp_mac_address127_low
67873  *
67874  * <b> Register 734 (MAC Address127 Low Register)</b>
67875  *
67876  * The MAC Address127 Low register holds the lower 32 bits of the 128th 6-byte MAC
67877  * address of the station.
67878  *
67879  * Register Layout
67880  *
67881  * Bits | Access | Reset | Description
67882  * :-------|:-------|:-----------|:-------------------------------------
67883  * [31:0] | RW | 0xffffffff | ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO
67884  *
67885  */
67886 /*
67887  * Field : addrlo
67888  *
67889  * MAC Address127 [31:0]
67890  *
67891  * This field contains the lower 32 bits of the 128th 6-byte MAC address. The
67892  * content of this field is undefined
67893  *
67894  * until loaded by the Application after the initialization process.
67895  *
67896  * Field Access Macros:
67897  *
67898  */
67899 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field. */
67900 #define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_LSB 0
67901 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field. */
67902 #define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_MSB 31
67903 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field. */
67904 #define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_WIDTH 32
67905 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field value. */
67906 #define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_SET_MSK 0xffffffff
67907 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field value. */
67908 #define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_CLR_MSK 0x00000000
67909 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field. */
67910 #define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_RESET 0xffffffff
67911 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO field value from a register. */
67912 #define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
67913 /* Produces a ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field value suitable for setting the register. */
67914 #define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
67915 
67916 #ifndef __ASSEMBLY__
67917 /*
67918  * WARNING: The C register and register group struct declarations are provided for
67919  * convenience and illustrative purposes. They should, however, be used with
67920  * caution as the C language standard provides no guarantees about the alignment or
67921  * atomicity of device memory accesses. The recommended practice for writing
67922  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
67923  * alt_write_word() functions.
67924  *
67925  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR127_LOW.
67926  */
67927 struct ALT_EMAC_GMAC_MAC_ADDR127_LOW_s
67928 {
67929  uint32_t addrlo : 32; /* ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO */
67930 };
67931 
67932 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR127_LOW. */
67933 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR127_LOW_s ALT_EMAC_GMAC_MAC_ADDR127_LOW_t;
67934 #endif /* __ASSEMBLY__ */
67935 
67936 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_LOW register. */
67937 #define ALT_EMAC_GMAC_MAC_ADDR127_LOW_RESET 0xffffffff
67938 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR127_LOW register from the beginning of the component. */
67939 #define ALT_EMAC_GMAC_MAC_ADDR127_LOW_OFST 0xb7c
67940 /* The address of the ALT_EMAC_GMAC_MAC_ADDR127_LOW register. */
67941 #define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR127_LOW_OFST))
67942 
67943 /*
67944  * Register : dmagrp_bus_mode
67945  *
67946  * <b> Register 0 (Bus Mode Register) </b>
67947  *
67948  * The Bus Mode register establishes the bus operating modes for the DMA.
67949  *
67950  * Register Layout
67951  *
67952  * Bits | Access | Reset | Description
67953  * :--------|:-------|:------|:-------------------------------
67954  * [0] | RW | 0x1 | ALT_EMAC_DMA_BUS_MOD_SWR
67955  * [1] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_DA
67956  * [6:2] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_DSL
67957  * [7] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_ATDS
67958  * [13:8] | RW | 0x1 | ALT_EMAC_DMA_BUS_MOD_PBL
67959  * [15:14] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_PR
67960  * [16] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_FB
67961  * [22:17] | RW | 0x1 | ALT_EMAC_DMA_BUS_MOD_RPBL
67962  * [23] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_USP
67963  * [24] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL
67964  * [25] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_AAL
67965  * [26] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_MB
67966  * [27] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_TXPR
67967  * [29:28] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_PRWG
67968  * [30] | R | 0x0 | ALT_EMAC_DMA_BUS_MOD_RSVD_30
67969  * [31] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_RIB
67970  *
67971  */
67972 /*
67973  * Field : swr
67974  *
67975  * Software Reset
67976  *
67977  * When this bit is set, the MAC DMA Controller resets the logic and all internal
67978  * registers of the MAC. It is cleared automatically after the reset operation has
67979  * completed in all of the DWC_gmac clock domains. Before reprogramming any
67980  * register of the DWC_gmac, you should read a zero (0) value in this bit .
67981  *
67982  * <b> Note: </b><br>
67983  *
67984  * * The Software reset function is driven only by this bit. Bit 0 of Register 64
67985  * (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register)
67986  * has no impact on the Software reset function.
67987  *
67988  * * The reset operation is completed only when all resets in all active clock
67989  * domains are de-asserted. Therefore, it is essential that all the PHY inputs
67990  * clocks (applicable for the selected PHY interface) are present for the
67991  * software reset completion.
67992  *
67993  * Field Enumeration Values:
67994  *
67995  * Enum | Value | Description
67996  * :----------------------------------|:------|:------------
67997  * ALT_EMAC_DMA_BUS_MOD_SWR_E_CLRRST | 0x0 |
67998  * ALT_EMAC_DMA_BUS_MOD_SWR_E_RST | 0x1 |
67999  *
68000  * Field Access Macros:
68001  *
68002  */
68003 /*
68004  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_SWR
68005  *
68006  */
68007 #define ALT_EMAC_DMA_BUS_MOD_SWR_E_CLRRST 0x0
68008 /*
68009  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_SWR
68010  *
68011  */
68012 #define ALT_EMAC_DMA_BUS_MOD_SWR_E_RST 0x1
68013 
68014 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_SWR register field. */
68015 #define ALT_EMAC_DMA_BUS_MOD_SWR_LSB 0
68016 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_SWR register field. */
68017 #define ALT_EMAC_DMA_BUS_MOD_SWR_MSB 0
68018 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_SWR register field. */
68019 #define ALT_EMAC_DMA_BUS_MOD_SWR_WIDTH 1
68020 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_SWR register field value. */
68021 #define ALT_EMAC_DMA_BUS_MOD_SWR_SET_MSK 0x00000001
68022 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_SWR register field value. */
68023 #define ALT_EMAC_DMA_BUS_MOD_SWR_CLR_MSK 0xfffffffe
68024 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_SWR register field. */
68025 #define ALT_EMAC_DMA_BUS_MOD_SWR_RESET 0x1
68026 /* Extracts the ALT_EMAC_DMA_BUS_MOD_SWR field value from a register. */
68027 #define ALT_EMAC_DMA_BUS_MOD_SWR_GET(value) (((value) & 0x00000001) >> 0)
68028 /* Produces a ALT_EMAC_DMA_BUS_MOD_SWR register field value suitable for setting the register. */
68029 #define ALT_EMAC_DMA_BUS_MOD_SWR_SET(value) (((value) << 0) & 0x00000001)
68030 
68031 /*
68032  * Field : da
68033  *
68034  * DMA Arbitration Scheme
68035  *
68036  * This bit specifies the arbitration scheme between the transmit and receive paths
68037  * of Channel 0.
68038  *
68039  * * 0: Weighted round-robin with Rx:Tx or Tx:Rx
68040  *
68041  * The priority between the paths is according to the priority specified in bits
68042  * 15:14 (PR) and priority weights specified in Bit 27 (TXPR).
68043  *
68044  * * 1: Fixed priority
68045  *
68046  * The transmit path has priority over receive path when Bit 27 (TXPR) is set.
68047  * Otherwise, receive path has priority over the transmit path.
68048  *
68049  * In the GMAC-AXI configuration, these bits are reserved and read-only (RO).
68050  *
68051  * Field Access Macros:
68052  *
68053  */
68054 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_DA register field. */
68055 #define ALT_EMAC_DMA_BUS_MOD_DA_LSB 1
68056 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_DA register field. */
68057 #define ALT_EMAC_DMA_BUS_MOD_DA_MSB 1
68058 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_DA register field. */
68059 #define ALT_EMAC_DMA_BUS_MOD_DA_WIDTH 1
68060 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_DA register field value. */
68061 #define ALT_EMAC_DMA_BUS_MOD_DA_SET_MSK 0x00000002
68062 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_DA register field value. */
68063 #define ALT_EMAC_DMA_BUS_MOD_DA_CLR_MSK 0xfffffffd
68064 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_DA register field. */
68065 #define ALT_EMAC_DMA_BUS_MOD_DA_RESET 0x0
68066 /* Extracts the ALT_EMAC_DMA_BUS_MOD_DA field value from a register. */
68067 #define ALT_EMAC_DMA_BUS_MOD_DA_GET(value) (((value) & 0x00000002) >> 1)
68068 /* Produces a ALT_EMAC_DMA_BUS_MOD_DA register field value suitable for setting the register. */
68069 #define ALT_EMAC_DMA_BUS_MOD_DA_SET(value) (((value) << 1) & 0x00000002)
68070 
68071 /*
68072  * Field : dsl
68073  *
68074  * Descriptor Skip Length
68075  *
68076  * This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit,
68077  * 64-bit, or 128-bit bus) to skip between two unchained descriptors. The address
68078  * skipping starts from the end of current descriptor to the start of next
68079  * descriptor. When the DSL value is equal to zero, the descriptor table is taken
68080  * as contiguous by the DMA in Ring mode.
68081  *
68082  * Field Access Macros:
68083  *
68084  */
68085 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_DSL register field. */
68086 #define ALT_EMAC_DMA_BUS_MOD_DSL_LSB 2
68087 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_DSL register field. */
68088 #define ALT_EMAC_DMA_BUS_MOD_DSL_MSB 6
68089 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_DSL register field. */
68090 #define ALT_EMAC_DMA_BUS_MOD_DSL_WIDTH 5
68091 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_DSL register field value. */
68092 #define ALT_EMAC_DMA_BUS_MOD_DSL_SET_MSK 0x0000007c
68093 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_DSL register field value. */
68094 #define ALT_EMAC_DMA_BUS_MOD_DSL_CLR_MSK 0xffffff83
68095 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_DSL register field. */
68096 #define ALT_EMAC_DMA_BUS_MOD_DSL_RESET 0x0
68097 /* Extracts the ALT_EMAC_DMA_BUS_MOD_DSL field value from a register. */
68098 #define ALT_EMAC_DMA_BUS_MOD_DSL_GET(value) (((value) & 0x0000007c) >> 2)
68099 /* Produces a ALT_EMAC_DMA_BUS_MOD_DSL register field value suitable for setting the register. */
68100 #define ALT_EMAC_DMA_BUS_MOD_DSL_SET(value) (((value) << 2) & 0x0000007c)
68101 
68102 /*
68103  * Field : atds
68104  *
68105  * Alternate Descriptor Size
68106  *
68107  * When set, the size of the alternate descriptor increases to 32 bytes (8 DWORDS).
68108  * This is required when the Advanced Timestamp feature or the IPC Full Offload
68109  * Engine (Type 2) is enabled in the receiver. The enhanced descriptor is not
68110  * required if the Advanced Timestamp and IPC Full Checksum Offload (Type 2)
68111  * features are not enabled. In such cases, you can use the 16 bytes descriptor to
68112  * save 4 bytes of memory.
68113  *
68114  * This bit is present only when you select the Alternate Descriptor feature and
68115  * any one of the following features during core configuration:
68116  *
68117  * * Advanced Timestamp feature
68118  *
68119  * * IPC Full Checksum Offload Engine (Type 2) feature
68120  *
68121  * Otherwise, this bit is reserved and read-only.
68122  *
68123  * When reset, the descriptor size reverts back to 4 DWORDs (16 bytes).
68124  *
68125  * This bit preserves the backward compatibility for the descriptor size. In
68126  * versions prior to 3.50a, the descriptor size is 16 bytes for both normal and
68127  * enhanced descriptor. In version 3.50a, descriptor size is increased to 32 bytes
68128  * because of the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2)
68129  * features.
68130  *
68131  * Field Enumeration Values:
68132  *
68133  * Enum | Value | Description
68134  * :-----------------------------------|:------|:------------
68135  * ALT_EMAC_DMA_BUS_MOD_ATDS_E_CLRRST | 0x0 |
68136  * ALT_EMAC_DMA_BUS_MOD_ATDS_E_RST | 0x1 |
68137  *
68138  * Field Access Macros:
68139  *
68140  */
68141 /*
68142  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_ATDS
68143  *
68144  */
68145 #define ALT_EMAC_DMA_BUS_MOD_ATDS_E_CLRRST 0x0
68146 /*
68147  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_ATDS
68148  *
68149  */
68150 #define ALT_EMAC_DMA_BUS_MOD_ATDS_E_RST 0x1
68151 
68152 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_ATDS register field. */
68153 #define ALT_EMAC_DMA_BUS_MOD_ATDS_LSB 7
68154 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_ATDS register field. */
68155 #define ALT_EMAC_DMA_BUS_MOD_ATDS_MSB 7
68156 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_ATDS register field. */
68157 #define ALT_EMAC_DMA_BUS_MOD_ATDS_WIDTH 1
68158 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_ATDS register field value. */
68159 #define ALT_EMAC_DMA_BUS_MOD_ATDS_SET_MSK 0x00000080
68160 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_ATDS register field value. */
68161 #define ALT_EMAC_DMA_BUS_MOD_ATDS_CLR_MSK 0xffffff7f
68162 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_ATDS register field. */
68163 #define ALT_EMAC_DMA_BUS_MOD_ATDS_RESET 0x0
68164 /* Extracts the ALT_EMAC_DMA_BUS_MOD_ATDS field value from a register. */
68165 #define ALT_EMAC_DMA_BUS_MOD_ATDS_GET(value) (((value) & 0x00000080) >> 7)
68166 /* Produces a ALT_EMAC_DMA_BUS_MOD_ATDS register field value suitable for setting the register. */
68167 #define ALT_EMAC_DMA_BUS_MOD_ATDS_SET(value) (((value) << 7) & 0x00000080)
68168 
68169 /*
68170  * Field : pbl
68171  *
68172  * Programmable Burst Length
68173  *
68174  * These bits indicate the maximum number of beats to be transferred in one DMA
68175  * transaction. This is the maximum value that is used in a single block Read or
68176  * Write. The DMA always attempts to burst as specified in PBL each time it starts
68177  * a Burst transfer on the host bus. PBL can be programmed with permissible values
68178  * of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. When
68179  * USP is set high, this PBL value is applicable only for Tx DMA transactions.
68180  *
68181  * If the number of beats to be transferred is more than 32, then perform the
68182  * following steps:
68183  *
68184  * 1. Set the PBLx8 mode. <br>
68185  *
68186  * 2. Set the PBL. <br>
68187  *
68188  * For example, if the maximum number of beats to be transferred is 64, then first
68189  * set PBLx8 to 1 and then set PBL to 8. The PBL values have the following
68190  * limitation: The maximum number of possible beats (PBL) is limited by the size of
68191  * the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The
68192  * FIFO has a constraint that the maximum beat supported is half the depth of the
68193  * FIFO, except when specified.
68194  *
68195  * For different data bus widths and FIFO sizes, the valid PBL range (including x8
68196  * mode) is provided in the following list. If the PBL is common for both transmit
68197  * and receive DMA, the minimum Rx FIFO and Tx FIFO depths must be considered.
68198  *
68199  * Note: In the half-duplex mode, the valid PBL range specified in the following
68200  * list is applicable only for Tx FIFO.
68201  *
68202  * * 32-Bit Data Bus Width
68203  *
68204  * - 128 Bytes FIFO Depth: In the full-duplex mode, the valid PBL range is 16
68205  * or less. In the half-duplex mode, the valid PBL range is 8 or less for the
68206  * 10 or 100 Mbps mode.
68207  *
68208  * - 256 Bytes FIFO Depth: In the full-duplex mode and the half-duplex (10 or
68209  * 100 Mbps) modes, the valid PBL range is 32 or less.
68210  *
68211  * - 512 Bytes FIFO Depth: In the full-duplex mode and the half-duplex (10 or
68212  * 100 Mbps) modes, the valid PBL range is 64 or less.
68213  *
68214  * - 1 KB FIFO Depth: In the full-duplex mode, the valid PBL range is 128 or
68215  * less. In the half-duplex mode, the valid PBL range is 128 or less in the
68216  * 10 or 100 Mbps mode and 64 or less in the 1000 Mbps mode.
68217  *
68218  * - 2 KB and Higher FIFO Depth: All PBL values are supported in the full-
68219  * duplex mode and half-duplex modes.
68220  *
68221  * * 64-Bit Data Bus Width
68222  *
68223  * - 128 Bytes FIFO Depth: In the full-duplex mode, the valid PBL range is 8 or
68224  * less. In the half-duplex mode, the valid PBL range is 4 or less for the 10
68225  * or 100 Mbps mode.
68226  *
68227  * - 256 Bytes FIFO Depth: In the full-duplex mode and the half-duplex (10 or
68228  * 100 Mbps) modes, the valid PBL range is 16 or less.
68229  *
68230  * - 512 Bytes FIFO Depth: In the full-duplex mode and the half-duplex (10 or
68231  * 100 Mbps) modes, the valid PBL range is 32 or less.
68232  *
68233  * - 1 KB FIFO Depth: In the full-duplex mode, the valid PBL range is 64 or
68234  * less. In the half-duplex mode, the valid PBL range is 64 or less in the 10
68235  * or 100 Mbps mode and 32 or less in the 1000-Mbps mode.
68236  *
68237  * - 2 KB FIFO Depth: In the full-duplex mode and the half-duplex (10 or 100
68238  * Mbps) modes, the valid PBL range is 128 or less.
68239  *
68240  * - 4 KB and Higher FIFO Depth: All PBL values are supported in the full-
68241  * duplex and half-duplex modes.
68242  *
68243  * * 128-Bit Data Bus Width
68244  *
68245  * - 128 Bytes FIFO Depth: In the full-duplex mode, the valid PBL range is 4 or
68246  * less. In the half-duplex mode, the valid PBL range is 2 or less for the 10
68247  * or 100 Mbps mode.
68248  *
68249  * - 256 Bytes FIFO Depth: In the full-duplex mode and the half-duplex (10 or
68250  * 100 Mbps) modes, the valid PBL range is 8 or less.
68251  *
68252  * - 512 Bytes FIFO Depth: In the full-duplex mode and the half-duplex (10 or
68253  * 100 Mbps) modes, the valid PBL range is 16 or less.
68254  *
68255  * - 1 KB FIFO Depth: In the full-duplex mode, the valid PBL range is 32 or
68256  * less. In the half-duplex mode, the valid PBL range is 32 or less in the 10
68257  * or 100 Mbps mode and 16 or less in the 1000-Mbps mode.
68258  *
68259  * - 2 KB FIFO Depth: In the full-duplex mode and the half-duplex (10 or 100
68260  * Mbps) modes, the valid PBL range is 64 or less.
68261  *
68262  * - 4 KB FIFO Depth: In the full-duplex mode and the half-duplex (10 or 100
68263  * Mbps) modes, the valid PBL range is 128 or less.
68264  *
68265  * - 8 KB and Higher FIFO Depth: All PBL values are supported in the full-
68266  * duplex and half-duplex modes.
68267  *
68268  * Field Access Macros:
68269  *
68270  */
68271 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_PBL register field. */
68272 #define ALT_EMAC_DMA_BUS_MOD_PBL_LSB 8
68273 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_PBL register field. */
68274 #define ALT_EMAC_DMA_BUS_MOD_PBL_MSB 13
68275 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_PBL register field. */
68276 #define ALT_EMAC_DMA_BUS_MOD_PBL_WIDTH 6
68277 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_PBL register field value. */
68278 #define ALT_EMAC_DMA_BUS_MOD_PBL_SET_MSK 0x00003f00
68279 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_PBL register field value. */
68280 #define ALT_EMAC_DMA_BUS_MOD_PBL_CLR_MSK 0xffffc0ff
68281 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_PBL register field. */
68282 #define ALT_EMAC_DMA_BUS_MOD_PBL_RESET 0x1
68283 /* Extracts the ALT_EMAC_DMA_BUS_MOD_PBL field value from a register. */
68284 #define ALT_EMAC_DMA_BUS_MOD_PBL_GET(value) (((value) & 0x00003f00) >> 8)
68285 /* Produces a ALT_EMAC_DMA_BUS_MOD_PBL register field value suitable for setting the register. */
68286 #define ALT_EMAC_DMA_BUS_MOD_PBL_SET(value) (((value) << 8) & 0x00003f00)
68287 
68288 /*
68289  * Field : pr
68290  *
68291  * Priority Ratio
68292  *
68293  * These bits control the priority ratio in the weighted round-robin arbitration
68294  * between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is
68295  * reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR)
68296  * is reset or set.
68297  *
68298  * * 00: The Priority Ratio is 1:1.
68299  *
68300  * * 01: The Priority Ratio is 2:1.
68301  *
68302  * * 10: The Priority Ratio is 3:1.
68303  *
68304  * * 11: The Priority Ratio is 4:1.
68305  *
68306  * In the GMAC-AXI configuration, these bits are reserved and read-only (RO).
68307  *
68308  * Field Access Macros:
68309  *
68310  */
68311 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_PR register field. */
68312 #define ALT_EMAC_DMA_BUS_MOD_PR_LSB 14
68313 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_PR register field. */
68314 #define ALT_EMAC_DMA_BUS_MOD_PR_MSB 15
68315 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_PR register field. */
68316 #define ALT_EMAC_DMA_BUS_MOD_PR_WIDTH 2
68317 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_PR register field value. */
68318 #define ALT_EMAC_DMA_BUS_MOD_PR_SET_MSK 0x0000c000
68319 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_PR register field value. */
68320 #define ALT_EMAC_DMA_BUS_MOD_PR_CLR_MSK 0xffff3fff
68321 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_PR register field. */
68322 #define ALT_EMAC_DMA_BUS_MOD_PR_RESET 0x0
68323 /* Extracts the ALT_EMAC_DMA_BUS_MOD_PR field value from a register. */
68324 #define ALT_EMAC_DMA_BUS_MOD_PR_GET(value) (((value) & 0x0000c000) >> 14)
68325 /* Produces a ALT_EMAC_DMA_BUS_MOD_PR register field value suitable for setting the register. */
68326 #define ALT_EMAC_DMA_BUS_MOD_PR_SET(value) (((value) << 14) & 0x0000c000)
68327 
68328 /*
68329  * Field : fb
68330  *
68331  * Fixed Burst
68332  *
68333  * This bit controls whether the AHB or AXI Master interface performs fixed burst
68334  * transfers or not. When set, the AHB interface uses only SINGLE, INCR4, INCR8, or
68335  * INCR16 during start of the normal burst transfers. When reset, the AHB or AXI
68336  * interface uses SINGLE and INCR burst transfer operations.
68337  *
68338  * For more information, see Bit 0 (UNDEF) of the AXI Bus Mode register in the
68339  * GMAC-AXI configuration.
68340  *
68341  * Field Enumeration Values:
68342  *
68343  * Enum | Value | Description
68344  * :-------------------------------------|:------|:------------
68345  * ALT_EMAC_DMA_BUS_MOD_FB_E_NONFB | 0x0 |
68346  * ALT_EMAC_DMA_BUS_MOD_FB_E_FB1_4_8_16 | 0x1 |
68347  *
68348  * Field Access Macros:
68349  *
68350  */
68351 /*
68352  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_FB
68353  *
68354  */
68355 #define ALT_EMAC_DMA_BUS_MOD_FB_E_NONFB 0x0
68356 /*
68357  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_FB
68358  *
68359  */
68360 #define ALT_EMAC_DMA_BUS_MOD_FB_E_FB1_4_8_16 0x1
68361 
68362 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_FB register field. */
68363 #define ALT_EMAC_DMA_BUS_MOD_FB_LSB 16
68364 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_FB register field. */
68365 #define ALT_EMAC_DMA_BUS_MOD_FB_MSB 16
68366 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_FB register field. */
68367 #define ALT_EMAC_DMA_BUS_MOD_FB_WIDTH 1
68368 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_FB register field value. */
68369 #define ALT_EMAC_DMA_BUS_MOD_FB_SET_MSK 0x00010000
68370 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_FB register field value. */
68371 #define ALT_EMAC_DMA_BUS_MOD_FB_CLR_MSK 0xfffeffff
68372 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_FB register field. */
68373 #define ALT_EMAC_DMA_BUS_MOD_FB_RESET 0x0
68374 /* Extracts the ALT_EMAC_DMA_BUS_MOD_FB field value from a register. */
68375 #define ALT_EMAC_DMA_BUS_MOD_FB_GET(value) (((value) & 0x00010000) >> 16)
68376 /* Produces a ALT_EMAC_DMA_BUS_MOD_FB register field value suitable for setting the register. */
68377 #define ALT_EMAC_DMA_BUS_MOD_FB_SET(value) (((value) << 16) & 0x00010000)
68378 
68379 /*
68380  * Field : rpbl
68381  *
68382  * Rx DMA PBL
68383  *
68384  * This field indicates the maximum number of beats to be transferred in one Rx DMA
68385  * transaction. This is the maximum value that is used in a single block Read or
68386  * Write.
68387  *
68388  * The Rx DMA always attempts to burst as specified in the RPBL bit each time it
68389  * starts a Burst transfer on the host bus. You can program RPBL with values of 1,
68390  * 2, 4, 8, 16, and 32. Any other value results in undefined behavior.
68391  *
68392  * This field is valid and applicable only when USP is set high.
68393  *
68394  * Field Enumeration Values:
68395  *
68396  * Enum | Value | Description
68397  * :---------------------------------------|:------|:------------
68398  * ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL1 | 0x1 |
68399  * ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL2 | 0x2 |
68400  * ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL4 | 0x4 |
68401  * ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL8 | 0x8 |
68402  * ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL6 | 0x10 |
68403  * ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL32 | 0x20 |
68404  *
68405  * Field Access Macros:
68406  *
68407  */
68408 /*
68409  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
68410  *
68411  */
68412 #define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL1 0x1
68413 /*
68414  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
68415  *
68416  */
68417 #define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL2 0x2
68418 /*
68419  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
68420  *
68421  */
68422 #define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL4 0x4
68423 /*
68424  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
68425  *
68426  */
68427 #define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL8 0x8
68428 /*
68429  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
68430  *
68431  */
68432 #define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL6 0x10
68433 /*
68434  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
68435  *
68436  */
68437 #define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL32 0x20
68438 
68439 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_RPBL register field. */
68440 #define ALT_EMAC_DMA_BUS_MOD_RPBL_LSB 17
68441 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_RPBL register field. */
68442 #define ALT_EMAC_DMA_BUS_MOD_RPBL_MSB 22
68443 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_RPBL register field. */
68444 #define ALT_EMAC_DMA_BUS_MOD_RPBL_WIDTH 6
68445 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_RPBL register field value. */
68446 #define ALT_EMAC_DMA_BUS_MOD_RPBL_SET_MSK 0x007e0000
68447 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_RPBL register field value. */
68448 #define ALT_EMAC_DMA_BUS_MOD_RPBL_CLR_MSK 0xff81ffff
68449 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_RPBL register field. */
68450 #define ALT_EMAC_DMA_BUS_MOD_RPBL_RESET 0x1
68451 /* Extracts the ALT_EMAC_DMA_BUS_MOD_RPBL field value from a register. */
68452 #define ALT_EMAC_DMA_BUS_MOD_RPBL_GET(value) (((value) & 0x007e0000) >> 17)
68453 /* Produces a ALT_EMAC_DMA_BUS_MOD_RPBL register field value suitable for setting the register. */
68454 #define ALT_EMAC_DMA_BUS_MOD_RPBL_SET(value) (((value) << 17) & 0x007e0000)
68455 
68456 /*
68457  * Field : usp
68458  *
68459  * Use Seperate PBL
68460  *
68461  * When set high, this bit configures the Rx DMA to use the value configured in
68462  * Bits[22:17] as PBL. The PBL value in Bits[13:8] is applicable only to the Tx DMA
68463  * operations.
68464  *
68465  * When reset to low, the PBL value in Bits[13:8] is applicable for both DMA
68466  * engines.
68467  *
68468  * Field Enumeration Values:
68469  *
68470  * Enum | Value | Description
68471  * :--------------------------------|:------|:------------
68472  * ALT_EMAC_DMA_BUS_MOD_USP_E_DISD | 0x0 |
68473  * ALT_EMAC_DMA_BUS_MOD_USP_E_END | 0x1 |
68474  *
68475  * Field Access Macros:
68476  *
68477  */
68478 /*
68479  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_USP
68480  *
68481  */
68482 #define ALT_EMAC_DMA_BUS_MOD_USP_E_DISD 0x0
68483 /*
68484  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_USP
68485  *
68486  */
68487 #define ALT_EMAC_DMA_BUS_MOD_USP_E_END 0x1
68488 
68489 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_USP register field. */
68490 #define ALT_EMAC_DMA_BUS_MOD_USP_LSB 23
68491 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_USP register field. */
68492 #define ALT_EMAC_DMA_BUS_MOD_USP_MSB 23
68493 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_USP register field. */
68494 #define ALT_EMAC_DMA_BUS_MOD_USP_WIDTH 1
68495 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_USP register field value. */
68496 #define ALT_EMAC_DMA_BUS_MOD_USP_SET_MSK 0x00800000
68497 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_USP register field value. */
68498 #define ALT_EMAC_DMA_BUS_MOD_USP_CLR_MSK 0xff7fffff
68499 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_USP register field. */
68500 #define ALT_EMAC_DMA_BUS_MOD_USP_RESET 0x0
68501 /* Extracts the ALT_EMAC_DMA_BUS_MOD_USP field value from a register. */
68502 #define ALT_EMAC_DMA_BUS_MOD_USP_GET(value) (((value) & 0x00800000) >> 23)
68503 /* Produces a ALT_EMAC_DMA_BUS_MOD_USP register field value suitable for setting the register. */
68504 #define ALT_EMAC_DMA_BUS_MOD_USP_SET(value) (((value) << 23) & 0x00800000)
68505 
68506 /*
68507  * Field : eightxpbl
68508  *
68509  * PBLx8 Mode
68510  *
68511  * When set high, this bit multiplies the programmed PBL value (Bits[22:17] and
68512  * Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64,
68513  * 128, and 256 beats depending on the PBL value.
68514  *
68515  * Note: This bit function is not backward compatible. Before release 3.50a, this
68516  * bit was 4xPBL.
68517  *
68518  * Field Enumeration Values:
68519  *
68520  * Enum | Value | Description
68521  * :--------------------------------------|:------|:------------
68522  * ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_DISD | 0x0 |
68523  * ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_END | 0x1 |
68524  *
68525  * Field Access Macros:
68526  *
68527  */
68528 /*
68529  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL
68530  *
68531  */
68532 #define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_DISD 0x0
68533 /*
68534  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL
68535  *
68536  */
68537 #define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_END 0x1
68538 
68539 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field. */
68540 #define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_LSB 24
68541 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field. */
68542 #define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_MSB 24
68543 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field. */
68544 #define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_WIDTH 1
68545 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field value. */
68546 #define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_SET_MSK 0x01000000
68547 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field value. */
68548 #define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_CLR_MSK 0xfeffffff
68549 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field. */
68550 #define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_RESET 0x0
68551 /* Extracts the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL field value from a register. */
68552 #define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_GET(value) (((value) & 0x01000000) >> 24)
68553 /* Produces a ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field value suitable for setting the register. */
68554 #define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_SET(value) (((value) << 24) & 0x01000000)
68555 
68556 /*
68557  * Field : aal
68558  *
68559  * Address Aligned Beats
68560  *
68561  * When this bit is set high and the FB bit is equal to 1, the AHB or AXI interface
68562  * generates all bursts aligned to the start address LS bits. If the FB bit is
68563  * equal to 0, the first burst (accessing the data buffer's start address) is not
68564  * aligned, but subsequent bursts are aligned to the address.
68565  *
68566  * This bit is valid only in the GMAC-AHB and GMAC-AXI configuration and is
68567  * reserved (RO with default value 0) in all other configurations.
68568  *
68569  * Field Enumeration Values:
68570  *
68571  * Enum | Value | Description
68572  * :--------------------------------|:------|:------------
68573  * ALT_EMAC_DMA_BUS_MOD_AAL_E_DISD | 0x0 |
68574  * ALT_EMAC_DMA_BUS_MOD_AAL_E_END | 0x1 |
68575  *
68576  * Field Access Macros:
68577  *
68578  */
68579 /*
68580  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_AAL
68581  *
68582  */
68583 #define ALT_EMAC_DMA_BUS_MOD_AAL_E_DISD 0x0
68584 /*
68585  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_AAL
68586  *
68587  */
68588 #define ALT_EMAC_DMA_BUS_MOD_AAL_E_END 0x1
68589 
68590 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_AAL register field. */
68591 #define ALT_EMAC_DMA_BUS_MOD_AAL_LSB 25
68592 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_AAL register field. */
68593 #define ALT_EMAC_DMA_BUS_MOD_AAL_MSB 25
68594 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_AAL register field. */
68595 #define ALT_EMAC_DMA_BUS_MOD_AAL_WIDTH 1
68596 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_AAL register field value. */
68597 #define ALT_EMAC_DMA_BUS_MOD_AAL_SET_MSK 0x02000000
68598 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_AAL register field value. */
68599 #define ALT_EMAC_DMA_BUS_MOD_AAL_CLR_MSK 0xfdffffff
68600 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_AAL register field. */
68601 #define ALT_EMAC_DMA_BUS_MOD_AAL_RESET 0x0
68602 /* Extracts the ALT_EMAC_DMA_BUS_MOD_AAL field value from a register. */
68603 #define ALT_EMAC_DMA_BUS_MOD_AAL_GET(value) (((value) & 0x02000000) >> 25)
68604 /* Produces a ALT_EMAC_DMA_BUS_MOD_AAL register field value suitable for setting the register. */
68605 #define ALT_EMAC_DMA_BUS_MOD_AAL_SET(value) (((value) << 25) & 0x02000000)
68606 
68607 /*
68608  * Field : mb
68609  *
68610  * Mixed Burst
68611  *
68612  * When this bit is set high and the FB bit is low, the AHB Master interface starts
68613  * all bursts of length more than 16 with INCR (undefined burst) whereas it reverts
68614  * to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less.
68615  *
68616  * This bit is valid only in the GMAC-AHB configuration and reserved in all other
68617  * configuration.
68618  *
68619  * Field Access Macros:
68620  *
68621  */
68622 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_MB register field. */
68623 #define ALT_EMAC_DMA_BUS_MOD_MB_LSB 26
68624 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_MB register field. */
68625 #define ALT_EMAC_DMA_BUS_MOD_MB_MSB 26
68626 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_MB register field. */
68627 #define ALT_EMAC_DMA_BUS_MOD_MB_WIDTH 1
68628 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_MB register field value. */
68629 #define ALT_EMAC_DMA_BUS_MOD_MB_SET_MSK 0x04000000
68630 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_MB register field value. */
68631 #define ALT_EMAC_DMA_BUS_MOD_MB_CLR_MSK 0xfbffffff
68632 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_MB register field. */
68633 #define ALT_EMAC_DMA_BUS_MOD_MB_RESET 0x0
68634 /* Extracts the ALT_EMAC_DMA_BUS_MOD_MB field value from a register. */
68635 #define ALT_EMAC_DMA_BUS_MOD_MB_GET(value) (((value) & 0x04000000) >> 26)
68636 /* Produces a ALT_EMAC_DMA_BUS_MOD_MB register field value suitable for setting the register. */
68637 #define ALT_EMAC_DMA_BUS_MOD_MB_SET(value) (((value) << 26) & 0x04000000)
68638 
68639 /*
68640  * Field : txpr
68641  *
68642  * Transmit Priority
68643  *
68644  * When set, this bit indicates that the transmit DMA has higher priority than the
68645  * receive DMA during arbitration for the system-side bus. In the GMAC-AXI
68646  * configuration, this bit is reserved and read-only (RO).
68647  *
68648  * Field Access Macros:
68649  *
68650  */
68651 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_TXPR register field. */
68652 #define ALT_EMAC_DMA_BUS_MOD_TXPR_LSB 27
68653 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_TXPR register field. */
68654 #define ALT_EMAC_DMA_BUS_MOD_TXPR_MSB 27
68655 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_TXPR register field. */
68656 #define ALT_EMAC_DMA_BUS_MOD_TXPR_WIDTH 1
68657 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_TXPR register field value. */
68658 #define ALT_EMAC_DMA_BUS_MOD_TXPR_SET_MSK 0x08000000
68659 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_TXPR register field value. */
68660 #define ALT_EMAC_DMA_BUS_MOD_TXPR_CLR_MSK 0xf7ffffff
68661 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_TXPR register field. */
68662 #define ALT_EMAC_DMA_BUS_MOD_TXPR_RESET 0x0
68663 /* Extracts the ALT_EMAC_DMA_BUS_MOD_TXPR field value from a register. */
68664 #define ALT_EMAC_DMA_BUS_MOD_TXPR_GET(value) (((value) & 0x08000000) >> 27)
68665 /* Produces a ALT_EMAC_DMA_BUS_MOD_TXPR register field value suitable for setting the register. */
68666 #define ALT_EMAC_DMA_BUS_MOD_TXPR_SET(value) (((value) << 27) & 0x08000000)
68667 
68668 /*
68669  * Field : prwg
68670  *
68671  * Channel Priority Weights
68672  *
68673  * This field sets the priority weights for Channel 0 during the round-robin
68674  * arbitration between the DMA channels for the system bus.
68675  *
68676  * * 00: The priority weight is 1.
68677  *
68678  * * 01: The priority weight is 2.
68679  *
68680  * * 10: The priority weight is 3.
68681  *
68682  * * 11: The priority weight is 4.
68683  *
68684  * This field is present in all DWC_gmac configurations except GMAC-AXI when you
68685  * select the AV feature. Otherwise, this field is reserved and read-only (RO).
68686  *
68687  * Field Access Macros:
68688  *
68689  */
68690 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_PRWG register field. */
68691 #define ALT_EMAC_DMA_BUS_MOD_PRWG_LSB 28
68692 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_PRWG register field. */
68693 #define ALT_EMAC_DMA_BUS_MOD_PRWG_MSB 29
68694 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_PRWG register field. */
68695 #define ALT_EMAC_DMA_BUS_MOD_PRWG_WIDTH 2
68696 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_PRWG register field value. */
68697 #define ALT_EMAC_DMA_BUS_MOD_PRWG_SET_MSK 0x30000000
68698 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_PRWG register field value. */
68699 #define ALT_EMAC_DMA_BUS_MOD_PRWG_CLR_MSK 0xcfffffff
68700 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_PRWG register field. */
68701 #define ALT_EMAC_DMA_BUS_MOD_PRWG_RESET 0x0
68702 /* Extracts the ALT_EMAC_DMA_BUS_MOD_PRWG field value from a register. */
68703 #define ALT_EMAC_DMA_BUS_MOD_PRWG_GET(value) (((value) & 0x30000000) >> 28)
68704 /* Produces a ALT_EMAC_DMA_BUS_MOD_PRWG register field value suitable for setting the register. */
68705 #define ALT_EMAC_DMA_BUS_MOD_PRWG_SET(value) (((value) << 28) & 0x30000000)
68706 
68707 /*
68708  * Field : reserved_30
68709  *
68710  * Reserved
68711  *
68712  * Field Access Macros:
68713  *
68714  */
68715 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_RSVD_30 register field. */
68716 #define ALT_EMAC_DMA_BUS_MOD_RSVD_30_LSB 30
68717 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_RSVD_30 register field. */
68718 #define ALT_EMAC_DMA_BUS_MOD_RSVD_30_MSB 30
68719 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_RSVD_30 register field. */
68720 #define ALT_EMAC_DMA_BUS_MOD_RSVD_30_WIDTH 1
68721 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_RSVD_30 register field value. */
68722 #define ALT_EMAC_DMA_BUS_MOD_RSVD_30_SET_MSK 0x40000000
68723 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_RSVD_30 register field value. */
68724 #define ALT_EMAC_DMA_BUS_MOD_RSVD_30_CLR_MSK 0xbfffffff
68725 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_RSVD_30 register field. */
68726 #define ALT_EMAC_DMA_BUS_MOD_RSVD_30_RESET 0x0
68727 /* Extracts the ALT_EMAC_DMA_BUS_MOD_RSVD_30 field value from a register. */
68728 #define ALT_EMAC_DMA_BUS_MOD_RSVD_30_GET(value) (((value) & 0x40000000) >> 30)
68729 /* Produces a ALT_EMAC_DMA_BUS_MOD_RSVD_30 register field value suitable for setting the register. */
68730 #define ALT_EMAC_DMA_BUS_MOD_RSVD_30_SET(value) (((value) << 30) & 0x40000000)
68731 
68732 /*
68733  * Field : rib
68734  *
68735  * Rebuild INCRx Burst
68736  *
68737  * When this bit is set high and the AHB master gets an EBT (Retry, Split, or
68738  * Losing bus grant), the AHB master interface rebuilds the pending beats of any
68739  * burst transfer initiated with INCRx. The AHB master interface rebuilds the beats
68740  * with a combination of specified bursts with INCRx and SINGLE. By default, the
68741  * AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR)
68742  * burst.
68743  *
68744  * This bit is valid only in the GMAC-AHB configuration. It is reserved in all
68745  * other configuration.
68746  *
68747  * Field Access Macros:
68748  *
68749  */
68750 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_RIB register field. */
68751 #define ALT_EMAC_DMA_BUS_MOD_RIB_LSB 31
68752 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_RIB register field. */
68753 #define ALT_EMAC_DMA_BUS_MOD_RIB_MSB 31
68754 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_RIB register field. */
68755 #define ALT_EMAC_DMA_BUS_MOD_RIB_WIDTH 1
68756 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_RIB register field value. */
68757 #define ALT_EMAC_DMA_BUS_MOD_RIB_SET_MSK 0x80000000
68758 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_RIB register field value. */
68759 #define ALT_EMAC_DMA_BUS_MOD_RIB_CLR_MSK 0x7fffffff
68760 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_RIB register field. */
68761 #define ALT_EMAC_DMA_BUS_MOD_RIB_RESET 0x0
68762 /* Extracts the ALT_EMAC_DMA_BUS_MOD_RIB field value from a register. */
68763 #define ALT_EMAC_DMA_BUS_MOD_RIB_GET(value) (((value) & 0x80000000) >> 31)
68764 /* Produces a ALT_EMAC_DMA_BUS_MOD_RIB register field value suitable for setting the register. */
68765 #define ALT_EMAC_DMA_BUS_MOD_RIB_SET(value) (((value) << 31) & 0x80000000)
68766 
68767 #ifndef __ASSEMBLY__
68768 /*
68769  * WARNING: The C register and register group struct declarations are provided for
68770  * convenience and illustrative purposes. They should, however, be used with
68771  * caution as the C language standard provides no guarantees about the alignment or
68772  * atomicity of device memory accesses. The recommended practice for writing
68773  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
68774  * alt_write_word() functions.
68775  *
68776  * The struct declaration for register ALT_EMAC_DMA_BUS_MOD.
68777  */
68778 struct ALT_EMAC_DMA_BUS_MOD_s
68779 {
68780  uint32_t swr : 1; /* ALT_EMAC_DMA_BUS_MOD_SWR */
68781  uint32_t da : 1; /* ALT_EMAC_DMA_BUS_MOD_DA */
68782  uint32_t dsl : 5; /* ALT_EMAC_DMA_BUS_MOD_DSL */
68783  uint32_t atds : 1; /* ALT_EMAC_DMA_BUS_MOD_ATDS */
68784  uint32_t pbl : 6; /* ALT_EMAC_DMA_BUS_MOD_PBL */
68785  uint32_t pr : 2; /* ALT_EMAC_DMA_BUS_MOD_PR */
68786  uint32_t fb : 1; /* ALT_EMAC_DMA_BUS_MOD_FB */
68787  uint32_t rpbl : 6; /* ALT_EMAC_DMA_BUS_MOD_RPBL */
68788  uint32_t usp : 1; /* ALT_EMAC_DMA_BUS_MOD_USP */
68789  uint32_t eightxpbl : 1; /* ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL */
68790  uint32_t aal : 1; /* ALT_EMAC_DMA_BUS_MOD_AAL */
68791  uint32_t mb : 1; /* ALT_EMAC_DMA_BUS_MOD_MB */
68792  uint32_t txpr : 1; /* ALT_EMAC_DMA_BUS_MOD_TXPR */
68793  uint32_t prwg : 2; /* ALT_EMAC_DMA_BUS_MOD_PRWG */
68794  const uint32_t reserved_30 : 1; /* ALT_EMAC_DMA_BUS_MOD_RSVD_30 */
68795  uint32_t rib : 1; /* ALT_EMAC_DMA_BUS_MOD_RIB */
68796 };
68797 
68798 /* The typedef declaration for register ALT_EMAC_DMA_BUS_MOD. */
68799 typedef volatile struct ALT_EMAC_DMA_BUS_MOD_s ALT_EMAC_DMA_BUS_MOD_t;
68800 #endif /* __ASSEMBLY__ */
68801 
68802 /* The reset value of the ALT_EMAC_DMA_BUS_MOD register. */
68803 #define ALT_EMAC_DMA_BUS_MOD_RESET 0x00020101
68804 /* The byte offset of the ALT_EMAC_DMA_BUS_MOD register from the beginning of the component. */
68805 #define ALT_EMAC_DMA_BUS_MOD_OFST 0x1000
68806 /* The address of the ALT_EMAC_DMA_BUS_MOD register. */
68807 #define ALT_EMAC_DMA_BUS_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_BUS_MOD_OFST))
68808 
68809 /*
68810  * Register : dmagrp_transmit_poll_demand
68811  *
68812  * <b> Register 1 (Transmit Poll Demand Register) </b>
68813  *
68814  * The Transmit Poll Demand register enables the Tx DMA to check whether or not the
68815  * DMA owns the current descriptor. The Transmit Poll Demand command is given to
68816  * wake up the Tx DMA if it is in the Suspend mode. The Tx DMA can go into the
68817  * Suspend mode because of an Underflow error in a transmitted frame or the
68818  * unavailability of descriptors owned by it. You can give this command anytime and
68819  * the Tx DMA resets this command when it again starts fetching the current
68820  * descriptor from host memory. When this register is read, it always returns zero.
68821  *
68822  * Register Layout
68823  *
68824  * Bits | Access | Reset | Description
68825  * :-------|:-------|:------|:--------------------------------
68826  * [31:0] | RW | 0x0 | ALT_EMAC_DMA_TX_POLL_DEMAND_TPD
68827  *
68828  */
68829 /*
68830  * Field : tpd
68831  *
68832  * Transmit Poll Demand
68833  *
68834  * When these bits are written with any value, the DMA reads the current descriptor
68835  * pointed to by Register 18 (Current Host Transmit Descriptor Register). If that
68836  * descriptor is not available (owned by the Host), the transmission returns to the
68837  * Suspend state and the Bit 2 (TU) of Register 5 (Status Register) is asserted. If
68838  * the descriptor is available, the transmission resumes.
68839  *
68840  * Field Access Macros:
68841  *
68842  */
68843 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field. */
68844 #define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_LSB 0
68845 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field. */
68846 #define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_MSB 31
68847 /* The width in bits of the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field. */
68848 #define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_WIDTH 32
68849 /* The mask used to set the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field value. */
68850 #define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_SET_MSK 0xffffffff
68851 /* The mask used to clear the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field value. */
68852 #define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_CLR_MSK 0x00000000
68853 /* The reset value of the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field. */
68854 #define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_RESET 0x0
68855 /* Extracts the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD field value from a register. */
68856 #define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_GET(value) (((value) & 0xffffffff) >> 0)
68857 /* Produces a ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field value suitable for setting the register. */
68858 #define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_SET(value) (((value) << 0) & 0xffffffff)
68859 
68860 #ifndef __ASSEMBLY__
68861 /*
68862  * WARNING: The C register and register group struct declarations are provided for
68863  * convenience and illustrative purposes. They should, however, be used with
68864  * caution as the C language standard provides no guarantees about the alignment or
68865  * atomicity of device memory accesses. The recommended practice for writing
68866  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
68867  * alt_write_word() functions.
68868  *
68869  * The struct declaration for register ALT_EMAC_DMA_TX_POLL_DEMAND.
68870  */
68871 struct ALT_EMAC_DMA_TX_POLL_DEMAND_s
68872 {
68873  uint32_t tpd : 32; /* ALT_EMAC_DMA_TX_POLL_DEMAND_TPD */
68874 };
68875 
68876 /* The typedef declaration for register ALT_EMAC_DMA_TX_POLL_DEMAND. */
68877 typedef volatile struct ALT_EMAC_DMA_TX_POLL_DEMAND_s ALT_EMAC_DMA_TX_POLL_DEMAND_t;
68878 #endif /* __ASSEMBLY__ */
68879 
68880 /* The reset value of the ALT_EMAC_DMA_TX_POLL_DEMAND register. */
68881 #define ALT_EMAC_DMA_TX_POLL_DEMAND_RESET 0x00000000
68882 /* The byte offset of the ALT_EMAC_DMA_TX_POLL_DEMAND register from the beginning of the component. */
68883 #define ALT_EMAC_DMA_TX_POLL_DEMAND_OFST 0x1004
68884 /* The address of the ALT_EMAC_DMA_TX_POLL_DEMAND register. */
68885 #define ALT_EMAC_DMA_TX_POLL_DEMAND_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_TX_POLL_DEMAND_OFST))
68886 
68887 /*
68888  * Register : dmagrp_receive_poll_demand
68889  *
68890  * <b>Register 2 (Receive Poll Demand Register) </b>
68891  *
68892  * The Receive Poll Demand register enables the receive DMA to check for new
68893  * descriptors. This command is used to wake up the Rx DMA from the SUSPEND state.
68894  * The RxDMA can go into the SUSPEND state only because of the unavailability of
68895  * descriptors it owns. When this register is read, it always returns zero.
68896  *
68897  * Register Layout
68898  *
68899  * Bits | Access | Reset | Description
68900  * :-------|:-------|:------|:--------------------------------
68901  * [31:0] | RW | 0x0 | ALT_EMAC_DMA_RX_POLL_DEMAND_RPD
68902  *
68903  */
68904 /*
68905  * Field : rpd
68906  *
68907  * Receive Poll Demand
68908  *
68909  * When these bits are written with any value, the DMA reads the current descriptor
68910  * pointed to by Register 19 (Current Host Receive Descriptor Register). If that
68911  * descriptor is not available (owned by the Host), the reception returns to the
68912  * Suspended state and the Bit 7 (RU) of Register 5 (Status Register) is not
68913  * asserted. If the descriptor is available, the Rx DMA returns to the active
68914  * state.
68915  *
68916  * Field Access Macros:
68917  *
68918  */
68919 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field. */
68920 #define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_LSB 0
68921 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field. */
68922 #define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_MSB 31
68923 /* The width in bits of the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field. */
68924 #define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_WIDTH 32
68925 /* The mask used to set the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field value. */
68926 #define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_SET_MSK 0xffffffff
68927 /* The mask used to clear the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field value. */
68928 #define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_CLR_MSK 0x00000000
68929 /* The reset value of the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field. */
68930 #define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_RESET 0x0
68931 /* Extracts the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD field value from a register. */
68932 #define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_GET(value) (((value) & 0xffffffff) >> 0)
68933 /* Produces a ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field value suitable for setting the register. */
68934 #define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_SET(value) (((value) << 0) & 0xffffffff)
68935 
68936 #ifndef __ASSEMBLY__
68937 /*
68938  * WARNING: The C register and register group struct declarations are provided for
68939  * convenience and illustrative purposes. They should, however, be used with
68940  * caution as the C language standard provides no guarantees about the alignment or
68941  * atomicity of device memory accesses. The recommended practice for writing
68942  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
68943  * alt_write_word() functions.
68944  *
68945  * The struct declaration for register ALT_EMAC_DMA_RX_POLL_DEMAND.
68946  */
68947 struct ALT_EMAC_DMA_RX_POLL_DEMAND_s
68948 {
68949  uint32_t rpd : 32; /* ALT_EMAC_DMA_RX_POLL_DEMAND_RPD */
68950 };
68951 
68952 /* The typedef declaration for register ALT_EMAC_DMA_RX_POLL_DEMAND. */
68953 typedef volatile struct ALT_EMAC_DMA_RX_POLL_DEMAND_s ALT_EMAC_DMA_RX_POLL_DEMAND_t;
68954 #endif /* __ASSEMBLY__ */
68955 
68956 /* The reset value of the ALT_EMAC_DMA_RX_POLL_DEMAND register. */
68957 #define ALT_EMAC_DMA_RX_POLL_DEMAND_RESET 0x00000000
68958 /* The byte offset of the ALT_EMAC_DMA_RX_POLL_DEMAND register from the beginning of the component. */
68959 #define ALT_EMAC_DMA_RX_POLL_DEMAND_OFST 0x1008
68960 /* The address of the ALT_EMAC_DMA_RX_POLL_DEMAND register. */
68961 #define ALT_EMAC_DMA_RX_POLL_DEMAND_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_RX_POLL_DEMAND_OFST))
68962 
68963 /*
68964  * Register : dmagrp_receive_descriptor_list_address
68965  *
68966  * <b>Register 3 (Receive Descriptor List Address Register) </b>
68967  *
68968  * The Receive Descriptor List Address register points to the start of the Receive
68969  * Descriptor List. The descriptor lists reside in the host's physical memory space
68970  * and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or 128-bit data
68971  * bus). The DMA internally converts it to bus width aligned address by making the
68972  * corresponding LS bits low. Writing to this register is permitted only when
68973  * reception is stopped. When stopped, this register must be written to before the
68974  * receive Start command is given.
68975  *
68976  * You can write to this register only when Rx DMA has stopped, that is, Bit 1 (SR)
68977  * is set to zero in Register 6 (Operation Mode Register). When stopped, this
68978  * register can be written with a new descriptor list address. When you set the SR
68979  * bit to 1, the DMA takes the newly programmed descriptor base address.
68980  *
68981  * If this register is not changed when the SR bit is set to 0, then the DMA takes
68982  * the descriptor address where it was stopped earlier.
68983  *
68984  * Register Layout
68985  *
68986  * Bits | Access | Reset | Description
68987  * :-------|:-------|:------|:----------------------
68988  * [1:0] | ??? | 0x0 | *UNDEFINED*
68989  * [31:2] | RW | 0x0 | Start of Receive List
68990  *
68991  */
68992 /*
68993  * Field : Start of Receive List - rdesla_32bit
68994  *
68995  * This field contains the base address of the first descriptor in the Receive
68996  * Descriptor list. The LSB bits (1:0) are ignored (32-bit wide bus) and internally
68997  * taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO).
68998  *
68999  * Field Access Macros:
69000  *
69001  */
69002 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field. */
69003 #define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_LSB 2
69004 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field. */
69005 #define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_MSB 31
69006 /* The width in bits of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field. */
69007 #define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_WIDTH 30
69008 /* The mask used to set the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field value. */
69009 #define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_SET_MSK 0xfffffffc
69010 /* The mask used to clear the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field value. */
69011 #define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_CLR_MSK 0x00000003
69012 /* The reset value of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field. */
69013 #define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_RESET 0x0
69014 /* Extracts the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT field value from a register. */
69015 #define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_GET(value) (((value) & 0xfffffffc) >> 2)
69016 /* Produces a ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field value suitable for setting the register. */
69017 #define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_SET(value) (((value) << 2) & 0xfffffffc)
69018 
69019 #ifndef __ASSEMBLY__
69020 /*
69021  * WARNING: The C register and register group struct declarations are provided for
69022  * convenience and illustrative purposes. They should, however, be used with
69023  * caution as the C language standard provides no guarantees about the alignment or
69024  * atomicity of device memory accesses. The recommended practice for writing
69025  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
69026  * alt_write_word() functions.
69027  *
69028  * The struct declaration for register ALT_EMAC_DMA_RX_DESC_LIST_ADDR.
69029  */
69030 struct ALT_EMAC_DMA_RX_DESC_LIST_ADDR_s
69031 {
69032  uint32_t : 2; /* *UNDEFINED* */
69033  uint32_t rdesla_32bit : 30; /* Start of Receive List */
69034 };
69035 
69036 /* The typedef declaration for register ALT_EMAC_DMA_RX_DESC_LIST_ADDR. */
69037 typedef volatile struct ALT_EMAC_DMA_RX_DESC_LIST_ADDR_s ALT_EMAC_DMA_RX_DESC_LIST_ADDR_t;
69038 #endif /* __ASSEMBLY__ */
69039 
69040 /* The reset value of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR register. */
69041 #define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RESET 0x00000000
69042 /* The byte offset of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR register from the beginning of the component. */
69043 #define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_OFST 0x100c
69044 /* The address of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR register. */
69045 #define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_RX_DESC_LIST_ADDR_OFST))
69046 
69047 /*
69048  * Register : dmagrp_transmit_descriptor_list_address
69049  *
69050  * <b>Register 4 (Transmit Descriptor List Address Register)</b>
69051  *
69052  * The Transmit Descriptor List Address register points to the start of the
69053  * Transmit Descriptor List. The descriptor lists reside in the host's physical
69054  * memory space and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or
69055  * 128-bit data bus). The DMA internally converts it to bus width aligned address
69056  * by making the corresponding LSB to low.
69057  *
69058  * You can write to this register only when the Tx DMA has stopped, that is, Bit 13
69059  * (ST) is set to zero in Register 6 (Operation Mode Register). When stopped, this
69060  * register can be written with a new descriptor list address. When you set the ST
69061  * bit to 1, the DMA takes the newly programmed descriptor base address.
69062  *
69063  * If this register is not changed when the ST bit is set to 0, then the DMA takes
69064  * the descriptor address where it was stopped earlier.
69065  *
69066  * Register Layout
69067  *
69068  * Bits | Access | Reset | Description
69069  * :-------|:-------|:------|:-----------------------
69070  * [1:0] | ??? | 0x0 | *UNDEFINED*
69071  * [31:2] | RW | 0x0 | Start of Transmit List
69072  *
69073  */
69074 /*
69075  * Field : Start of Transmit List - tdesla_32bit
69076  *
69077  * This field contains the base address of the first descriptor in the Transmit
69078  * Descriptor list. The LSB bits (1:0) are ignored (32-bit wide bus) and are
69079  * internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only
69080  * (RO).
69081  *
69082  * Field Access Macros:
69083  *
69084  */
69085 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field. */
69086 #define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_LSB 2
69087 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field. */
69088 #define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_MSB 31
69089 /* The width in bits of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field. */
69090 #define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_WIDTH 30
69091 /* The mask used to set the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field value. */
69092 #define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_SET_MSK 0xfffffffc
69093 /* The mask used to clear the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field value. */
69094 #define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_CLR_MSK 0x00000003
69095 /* The reset value of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field. */
69096 #define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_RESET 0x0
69097 /* Extracts the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT field value from a register. */
69098 #define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_GET(value) (((value) & 0xfffffffc) >> 2)
69099 /* Produces a ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field value suitable for setting the register. */
69100 #define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_SET(value) (((value) << 2) & 0xfffffffc)
69101 
69102 #ifndef __ASSEMBLY__
69103 /*
69104  * WARNING: The C register and register group struct declarations are provided for
69105  * convenience and illustrative purposes. They should, however, be used with
69106  * caution as the C language standard provides no guarantees about the alignment or
69107  * atomicity of device memory accesses. The recommended practice for writing
69108  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
69109  * alt_write_word() functions.
69110  *
69111  * The struct declaration for register ALT_EMAC_DMA_TX_DESC_LIST_ADDR.
69112  */
69113 struct ALT_EMAC_DMA_TX_DESC_LIST_ADDR_s
69114 {
69115  uint32_t : 2; /* *UNDEFINED* */
69116  uint32_t tdesla_32bit : 30; /* Start of Transmit List */
69117 };
69118 
69119 /* The typedef declaration for register ALT_EMAC_DMA_TX_DESC_LIST_ADDR. */
69120 typedef volatile struct ALT_EMAC_DMA_TX_DESC_LIST_ADDR_s ALT_EMAC_DMA_TX_DESC_LIST_ADDR_t;
69121 #endif /* __ASSEMBLY__ */
69122 
69123 /* The reset value of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR register. */
69124 #define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_RESET 0x00000000
69125 /* The byte offset of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR register from the beginning of the component. */
69126 #define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_OFST 0x1010
69127 /* The address of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR register. */
69128 #define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_TX_DESC_LIST_ADDR_OFST))
69129 
69130 /*
69131  * Register : dmagrp_status
69132  *
69133  * <b>Register 5 (Status Register) </b>
69134  *
69135  * The Status register contains all status bits that the DMA reports to the host.
69136  * The Software driver reads this register during an interrupt service routine or
69137  * polling. Most of the fields in this register cause the host to be interrupted.
69138  * The bits of this register are not cleared when read. Writing 1'b1 to
69139  * (unreserved) Bits[16:0] of this register clears these bits and writing 1'b0 has
69140  * no effect. Each field (Bits[16:0]) can be masked by masking the appropriate bit
69141  * in Register 7 (Interrupt Enable Register).
69142  *
69143  * Register Layout
69144  *
69145  * Bits | Access | Reset | Description
69146  * :--------|:-------|:------|:-----------------------------
69147  * [0] | RW | 0x0 | ALT_EMAC_DMA_STAT_TI
69148  * [1] | RW | 0x0 | ALT_EMAC_DMA_STAT_TPS
69149  * [2] | RW | 0x0 | ALT_EMAC_DMA_STAT_TU
69150  * [3] | RW | 0x0 | ALT_EMAC_DMA_STAT_TJT
69151  * [4] | RW | 0x0 | ALT_EMAC_DMA_STAT_OVF
69152  * [5] | RW | 0x0 | ALT_EMAC_DMA_STAT_UNF
69153  * [6] | RW | 0x0 | ALT_EMAC_DMA_STAT_RI
69154  * [7] | RW | 0x0 | ALT_EMAC_DMA_STAT_RU
69155  * [8] | RW | 0x0 | ALT_EMAC_DMA_STAT_RPS
69156  * [9] | RW | 0x0 | ALT_EMAC_DMA_STAT_RWT
69157  * [10] | RW | 0x0 | ALT_EMAC_DMA_STAT_ETI
69158  * [12:11] | R | 0x0 | ALT_EMAC_DMA_STAT_RSVD_12_11
69159  * [13] | RW | 0x0 | ALT_EMAC_DMA_STAT_FBI
69160  * [14] | RW | 0x0 | ALT_EMAC_DMA_STAT_ERI
69161  * [15] | RW | 0x0 | ALT_EMAC_DMA_STAT_AIS
69162  * [16] | RW | 0x0 | ALT_EMAC_DMA_STAT_NIS
69163  * [19:17] | R | 0x0 | ALT_EMAC_DMA_STAT_RS
69164  * [22:20] | R | 0x0 | ALT_EMAC_DMA_STAT_TS
69165  * [25:23] | R | 0x0 | ALT_EMAC_DMA_STAT_EB
69166  * [26] | R | 0x0 | ALT_EMAC_DMA_STAT_GLI
69167  * [27] | R | 0x0 | ALT_EMAC_DMA_STAT_GMI
69168  * [28] | R | 0x0 | ALT_EMAC_DMA_STAT_GPI
69169  * [29] | R | 0x0 | ALT_EMAC_DMA_STAT_TTI
69170  * [30] | R | 0x0 | ALT_EMAC_DMA_STAT_GLPII
69171  * [31] | R | 0x0 | ALT_EMAC_DMA_STAT_RSVD_31
69172  *
69173  */
69174 /*
69175  * Field : ti
69176  *
69177  * Transmit Interrupt
69178  *
69179  * This bit indicates that the frame transmission is complete. When transmission is
69180  * complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status
69181  * information is updated in the descriptor.
69182  *
69183  * Field Access Macros:
69184  *
69185  */
69186 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TI register field. */
69187 #define ALT_EMAC_DMA_STAT_TI_LSB 0
69188 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TI register field. */
69189 #define ALT_EMAC_DMA_STAT_TI_MSB 0
69190 /* The width in bits of the ALT_EMAC_DMA_STAT_TI register field. */
69191 #define ALT_EMAC_DMA_STAT_TI_WIDTH 1
69192 /* The mask used to set the ALT_EMAC_DMA_STAT_TI register field value. */
69193 #define ALT_EMAC_DMA_STAT_TI_SET_MSK 0x00000001
69194 /* The mask used to clear the ALT_EMAC_DMA_STAT_TI register field value. */
69195 #define ALT_EMAC_DMA_STAT_TI_CLR_MSK 0xfffffffe
69196 /* The reset value of the ALT_EMAC_DMA_STAT_TI register field. */
69197 #define ALT_EMAC_DMA_STAT_TI_RESET 0x0
69198 /* Extracts the ALT_EMAC_DMA_STAT_TI field value from a register. */
69199 #define ALT_EMAC_DMA_STAT_TI_GET(value) (((value) & 0x00000001) >> 0)
69200 /* Produces a ALT_EMAC_DMA_STAT_TI register field value suitable for setting the register. */
69201 #define ALT_EMAC_DMA_STAT_TI_SET(value) (((value) << 0) & 0x00000001)
69202 
69203 /*
69204  * Field : tps
69205  *
69206  * Transmit Process Stopped
69207  *
69208  * This bit is set when the transmission is stopped.
69209  *
69210  * Field Access Macros:
69211  *
69212  */
69213 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TPS register field. */
69214 #define ALT_EMAC_DMA_STAT_TPS_LSB 1
69215 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TPS register field. */
69216 #define ALT_EMAC_DMA_STAT_TPS_MSB 1
69217 /* The width in bits of the ALT_EMAC_DMA_STAT_TPS register field. */
69218 #define ALT_EMAC_DMA_STAT_TPS_WIDTH 1
69219 /* The mask used to set the ALT_EMAC_DMA_STAT_TPS register field value. */
69220 #define ALT_EMAC_DMA_STAT_TPS_SET_MSK 0x00000002
69221 /* The mask used to clear the ALT_EMAC_DMA_STAT_TPS register field value. */
69222 #define ALT_EMAC_DMA_STAT_TPS_CLR_MSK 0xfffffffd
69223 /* The reset value of the ALT_EMAC_DMA_STAT_TPS register field. */
69224 #define ALT_EMAC_DMA_STAT_TPS_RESET 0x0
69225 /* Extracts the ALT_EMAC_DMA_STAT_TPS field value from a register. */
69226 #define ALT_EMAC_DMA_STAT_TPS_GET(value) (((value) & 0x00000002) >> 1)
69227 /* Produces a ALT_EMAC_DMA_STAT_TPS register field value suitable for setting the register. */
69228 #define ALT_EMAC_DMA_STAT_TPS_SET(value) (((value) << 1) & 0x00000002)
69229 
69230 /*
69231  * Field : tu
69232  *
69233  * Transmit Buffer Unavailable
69234  *
69235  * This bit indicates that the host owns the Next Descriptor in the Transmit List
69236  * and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain
69237  * the Transmit Process state transitions.
69238  *
69239  * To resume processing Transmit descriptors, the host should change the ownership
69240  * of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand
69241  * command.
69242  *
69243  * Field Access Macros:
69244  *
69245  */
69246 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TU register field. */
69247 #define ALT_EMAC_DMA_STAT_TU_LSB 2
69248 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TU register field. */
69249 #define ALT_EMAC_DMA_STAT_TU_MSB 2
69250 /* The width in bits of the ALT_EMAC_DMA_STAT_TU register field. */
69251 #define ALT_EMAC_DMA_STAT_TU_WIDTH 1
69252 /* The mask used to set the ALT_EMAC_DMA_STAT_TU register field value. */
69253 #define ALT_EMAC_DMA_STAT_TU_SET_MSK 0x00000004
69254 /* The mask used to clear the ALT_EMAC_DMA_STAT_TU register field value. */
69255 #define ALT_EMAC_DMA_STAT_TU_CLR_MSK 0xfffffffb
69256 /* The reset value of the ALT_EMAC_DMA_STAT_TU register field. */
69257 #define ALT_EMAC_DMA_STAT_TU_RESET 0x0
69258 /* Extracts the ALT_EMAC_DMA_STAT_TU field value from a register. */
69259 #define ALT_EMAC_DMA_STAT_TU_GET(value) (((value) & 0x00000004) >> 2)
69260 /* Produces a ALT_EMAC_DMA_STAT_TU register field value suitable for setting the register. */
69261 #define ALT_EMAC_DMA_STAT_TU_SET(value) (((value) << 2) & 0x00000004)
69262 
69263 /*
69264  * Field : tjt
69265  *
69266  * Transmit Jabber Timeout
69267  *
69268  * This bit indicates that the Transmit Jabber Timer expired, which happens when
69269  * the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled).
69270  * When the Jabber Timeout occurs, the transmission process is aborted and placed
69271  * in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to
69272  * assert.
69273  *
69274  * Field Access Macros:
69275  *
69276  */
69277 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TJT register field. */
69278 #define ALT_EMAC_DMA_STAT_TJT_LSB 3
69279 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TJT register field. */
69280 #define ALT_EMAC_DMA_STAT_TJT_MSB 3
69281 /* The width in bits of the ALT_EMAC_DMA_STAT_TJT register field. */
69282 #define ALT_EMAC_DMA_STAT_TJT_WIDTH 1
69283 /* The mask used to set the ALT_EMAC_DMA_STAT_TJT register field value. */
69284 #define ALT_EMAC_DMA_STAT_TJT_SET_MSK 0x00000008
69285 /* The mask used to clear the ALT_EMAC_DMA_STAT_TJT register field value. */
69286 #define ALT_EMAC_DMA_STAT_TJT_CLR_MSK 0xfffffff7
69287 /* The reset value of the ALT_EMAC_DMA_STAT_TJT register field. */
69288 #define ALT_EMAC_DMA_STAT_TJT_RESET 0x0
69289 /* Extracts the ALT_EMAC_DMA_STAT_TJT field value from a register. */
69290 #define ALT_EMAC_DMA_STAT_TJT_GET(value) (((value) & 0x00000008) >> 3)
69291 /* Produces a ALT_EMAC_DMA_STAT_TJT register field value suitable for setting the register. */
69292 #define ALT_EMAC_DMA_STAT_TJT_SET(value) (((value) << 3) & 0x00000008)
69293 
69294 /*
69295  * Field : ovf
69296  *
69297  * Receive Overflow
69298  *
69299  * This bit indicates that the Receive Buffer had an Overflow during frame
69300  * reception. If the partial frame is transferred to the application, the overflow
69301  * status is set in RDES0[11].
69302  *
69303  * Field Access Macros:
69304  *
69305  */
69306 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_OVF register field. */
69307 #define ALT_EMAC_DMA_STAT_OVF_LSB 4
69308 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_OVF register field. */
69309 #define ALT_EMAC_DMA_STAT_OVF_MSB 4
69310 /* The width in bits of the ALT_EMAC_DMA_STAT_OVF register field. */
69311 #define ALT_EMAC_DMA_STAT_OVF_WIDTH 1
69312 /* The mask used to set the ALT_EMAC_DMA_STAT_OVF register field value. */
69313 #define ALT_EMAC_DMA_STAT_OVF_SET_MSK 0x00000010
69314 /* The mask used to clear the ALT_EMAC_DMA_STAT_OVF register field value. */
69315 #define ALT_EMAC_DMA_STAT_OVF_CLR_MSK 0xffffffef
69316 /* The reset value of the ALT_EMAC_DMA_STAT_OVF register field. */
69317 #define ALT_EMAC_DMA_STAT_OVF_RESET 0x0
69318 /* Extracts the ALT_EMAC_DMA_STAT_OVF field value from a register. */
69319 #define ALT_EMAC_DMA_STAT_OVF_GET(value) (((value) & 0x00000010) >> 4)
69320 /* Produces a ALT_EMAC_DMA_STAT_OVF register field value suitable for setting the register. */
69321 #define ALT_EMAC_DMA_STAT_OVF_SET(value) (((value) << 4) & 0x00000010)
69322 
69323 /*
69324  * Field : unf
69325  *
69326  * Transmit Underflow
69327  *
69328  * This bit indicates that the Transmit Buffer had an Underflow during frame
69329  * transmission. Transmission is suspended and an Underflow Error TDES0[1] is set.
69330  *
69331  * Field Access Macros:
69332  *
69333  */
69334 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_UNF register field. */
69335 #define ALT_EMAC_DMA_STAT_UNF_LSB 5
69336 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_UNF register field. */
69337 #define ALT_EMAC_DMA_STAT_UNF_MSB 5
69338 /* The width in bits of the ALT_EMAC_DMA_STAT_UNF register field. */
69339 #define ALT_EMAC_DMA_STAT_UNF_WIDTH 1
69340 /* The mask used to set the ALT_EMAC_DMA_STAT_UNF register field value. */
69341 #define ALT_EMAC_DMA_STAT_UNF_SET_MSK 0x00000020
69342 /* The mask used to clear the ALT_EMAC_DMA_STAT_UNF register field value. */
69343 #define ALT_EMAC_DMA_STAT_UNF_CLR_MSK 0xffffffdf
69344 /* The reset value of the ALT_EMAC_DMA_STAT_UNF register field. */
69345 #define ALT_EMAC_DMA_STAT_UNF_RESET 0x0
69346 /* Extracts the ALT_EMAC_DMA_STAT_UNF field value from a register. */
69347 #define ALT_EMAC_DMA_STAT_UNF_GET(value) (((value) & 0x00000020) >> 5)
69348 /* Produces a ALT_EMAC_DMA_STAT_UNF register field value suitable for setting the register. */
69349 #define ALT_EMAC_DMA_STAT_UNF_SET(value) (((value) << 5) & 0x00000020)
69350 
69351 /*
69352  * Field : ri
69353  *
69354  * Receive Interrupt
69355  *
69356  * This bit indicates that the frame reception is complete. When reception is
69357  * complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the
69358  * last Descriptor, and the specific frame status information is updated in the
69359  * descriptor.
69360  *
69361  * The reception remains in the Running state.
69362  *
69363  * Field Access Macros:
69364  *
69365  */
69366 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RI register field. */
69367 #define ALT_EMAC_DMA_STAT_RI_LSB 6
69368 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RI register field. */
69369 #define ALT_EMAC_DMA_STAT_RI_MSB 6
69370 /* The width in bits of the ALT_EMAC_DMA_STAT_RI register field. */
69371 #define ALT_EMAC_DMA_STAT_RI_WIDTH 1
69372 /* The mask used to set the ALT_EMAC_DMA_STAT_RI register field value. */
69373 #define ALT_EMAC_DMA_STAT_RI_SET_MSK 0x00000040
69374 /* The mask used to clear the ALT_EMAC_DMA_STAT_RI register field value. */
69375 #define ALT_EMAC_DMA_STAT_RI_CLR_MSK 0xffffffbf
69376 /* The reset value of the ALT_EMAC_DMA_STAT_RI register field. */
69377 #define ALT_EMAC_DMA_STAT_RI_RESET 0x0
69378 /* Extracts the ALT_EMAC_DMA_STAT_RI field value from a register. */
69379 #define ALT_EMAC_DMA_STAT_RI_GET(value) (((value) & 0x00000040) >> 6)
69380 /* Produces a ALT_EMAC_DMA_STAT_RI register field value suitable for setting the register. */
69381 #define ALT_EMAC_DMA_STAT_RI_SET(value) (((value) << 6) & 0x00000040)
69382 
69383 /*
69384  * Field : ru
69385  *
69386  * Receive Buffer Unavailable
69387  *
69388  * This bit indicates that the host owns the Next Descriptor in the Receive List
69389  * and the DMA cannot acquire it. The Receive Process is suspended. To resume
69390  * processing Receive descriptors, the host should change the ownership of the
69391  * descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is
69392  * issued, the Receive Process resumes when the next recognized incoming frame is
69393  * received. This bit is set only when the previous Receive Descriptor is owned by
69394  * the DMA.
69395  *
69396  * Field Access Macros:
69397  *
69398  */
69399 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RU register field. */
69400 #define ALT_EMAC_DMA_STAT_RU_LSB 7
69401 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RU register field. */
69402 #define ALT_EMAC_DMA_STAT_RU_MSB 7
69403 /* The width in bits of the ALT_EMAC_DMA_STAT_RU register field. */
69404 #define ALT_EMAC_DMA_STAT_RU_WIDTH 1
69405 /* The mask used to set the ALT_EMAC_DMA_STAT_RU register field value. */
69406 #define ALT_EMAC_DMA_STAT_RU_SET_MSK 0x00000080
69407 /* The mask used to clear the ALT_EMAC_DMA_STAT_RU register field value. */
69408 #define ALT_EMAC_DMA_STAT_RU_CLR_MSK 0xffffff7f
69409 /* The reset value of the ALT_EMAC_DMA_STAT_RU register field. */
69410 #define ALT_EMAC_DMA_STAT_RU_RESET 0x0
69411 /* Extracts the ALT_EMAC_DMA_STAT_RU field value from a register. */
69412 #define ALT_EMAC_DMA_STAT_RU_GET(value) (((value) & 0x00000080) >> 7)
69413 /* Produces a ALT_EMAC_DMA_STAT_RU register field value suitable for setting the register. */
69414 #define ALT_EMAC_DMA_STAT_RU_SET(value) (((value) << 7) & 0x00000080)
69415 
69416 /*
69417  * Field : rps
69418  *
69419  * Receive Process Stopped
69420  *
69421  * This bit is asserted when the Receive Process enters the Stopped state.
69422  *
69423  * Field Access Macros:
69424  *
69425  */
69426 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RPS register field. */
69427 #define ALT_EMAC_DMA_STAT_RPS_LSB 8
69428 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RPS register field. */
69429 #define ALT_EMAC_DMA_STAT_RPS_MSB 8
69430 /* The width in bits of the ALT_EMAC_DMA_STAT_RPS register field. */
69431 #define ALT_EMAC_DMA_STAT_RPS_WIDTH 1
69432 /* The mask used to set the ALT_EMAC_DMA_STAT_RPS register field value. */
69433 #define ALT_EMAC_DMA_STAT_RPS_SET_MSK 0x00000100
69434 /* The mask used to clear the ALT_EMAC_DMA_STAT_RPS register field value. */
69435 #define ALT_EMAC_DMA_STAT_RPS_CLR_MSK 0xfffffeff
69436 /* The reset value of the ALT_EMAC_DMA_STAT_RPS register field. */
69437 #define ALT_EMAC_DMA_STAT_RPS_RESET 0x0
69438 /* Extracts the ALT_EMAC_DMA_STAT_RPS field value from a register. */
69439 #define ALT_EMAC_DMA_STAT_RPS_GET(value) (((value) & 0x00000100) >> 8)
69440 /* Produces a ALT_EMAC_DMA_STAT_RPS register field value suitable for setting the register. */
69441 #define ALT_EMAC_DMA_STAT_RPS_SET(value) (((value) << 8) & 0x00000100)
69442 
69443 /*
69444  * Field : rwt
69445  *
69446  * Receive Watchdog Timeout
69447  *
69448  * When set, this bit indicates that the Receive Watchdog Timer expired while
69449  * receiving the current frame and the current frame is truncated after the
69450  * watchdog timeout.
69451  *
69452  * Field Access Macros:
69453  *
69454  */
69455 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RWT register field. */
69456 #define ALT_EMAC_DMA_STAT_RWT_LSB 9
69457 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RWT register field. */
69458 #define ALT_EMAC_DMA_STAT_RWT_MSB 9
69459 /* The width in bits of the ALT_EMAC_DMA_STAT_RWT register field. */
69460 #define ALT_EMAC_DMA_STAT_RWT_WIDTH 1
69461 /* The mask used to set the ALT_EMAC_DMA_STAT_RWT register field value. */
69462 #define ALT_EMAC_DMA_STAT_RWT_SET_MSK 0x00000200
69463 /* The mask used to clear the ALT_EMAC_DMA_STAT_RWT register field value. */
69464 #define ALT_EMAC_DMA_STAT_RWT_CLR_MSK 0xfffffdff
69465 /* The reset value of the ALT_EMAC_DMA_STAT_RWT register field. */
69466 #define ALT_EMAC_DMA_STAT_RWT_RESET 0x0
69467 /* Extracts the ALT_EMAC_DMA_STAT_RWT field value from a register. */
69468 #define ALT_EMAC_DMA_STAT_RWT_GET(value) (((value) & 0x00000200) >> 9)
69469 /* Produces a ALT_EMAC_DMA_STAT_RWT register field value suitable for setting the register. */
69470 #define ALT_EMAC_DMA_STAT_RWT_SET(value) (((value) << 9) & 0x00000200)
69471 
69472 /*
69473  * Field : eti
69474  *
69475  * Early Transmit Interrupt
69476  *
69477  * This bit indicates that the frame to be transmitted is fully transferred to the
69478  * MTL Transmit FIFO.
69479  *
69480  * Field Access Macros:
69481  *
69482  */
69483 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_ETI register field. */
69484 #define ALT_EMAC_DMA_STAT_ETI_LSB 10
69485 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_ETI register field. */
69486 #define ALT_EMAC_DMA_STAT_ETI_MSB 10
69487 /* The width in bits of the ALT_EMAC_DMA_STAT_ETI register field. */
69488 #define ALT_EMAC_DMA_STAT_ETI_WIDTH 1
69489 /* The mask used to set the ALT_EMAC_DMA_STAT_ETI register field value. */
69490 #define ALT_EMAC_DMA_STAT_ETI_SET_MSK 0x00000400
69491 /* The mask used to clear the ALT_EMAC_DMA_STAT_ETI register field value. */
69492 #define ALT_EMAC_DMA_STAT_ETI_CLR_MSK 0xfffffbff
69493 /* The reset value of the ALT_EMAC_DMA_STAT_ETI register field. */
69494 #define ALT_EMAC_DMA_STAT_ETI_RESET 0x0
69495 /* Extracts the ALT_EMAC_DMA_STAT_ETI field value from a register. */
69496 #define ALT_EMAC_DMA_STAT_ETI_GET(value) (((value) & 0x00000400) >> 10)
69497 /* Produces a ALT_EMAC_DMA_STAT_ETI register field value suitable for setting the register. */
69498 #define ALT_EMAC_DMA_STAT_ETI_SET(value) (((value) << 10) & 0x00000400)
69499 
69500 /*
69501  * Field : reserved_12_11
69502  *
69503  * Reserved
69504  *
69505  * Field Access Macros:
69506  *
69507  */
69508 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RSVD_12_11 register field. */
69509 #define ALT_EMAC_DMA_STAT_RSVD_12_11_LSB 11
69510 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RSVD_12_11 register field. */
69511 #define ALT_EMAC_DMA_STAT_RSVD_12_11_MSB 12
69512 /* The width in bits of the ALT_EMAC_DMA_STAT_RSVD_12_11 register field. */
69513 #define ALT_EMAC_DMA_STAT_RSVD_12_11_WIDTH 2
69514 /* The mask used to set the ALT_EMAC_DMA_STAT_RSVD_12_11 register field value. */
69515 #define ALT_EMAC_DMA_STAT_RSVD_12_11_SET_MSK 0x00001800
69516 /* The mask used to clear the ALT_EMAC_DMA_STAT_RSVD_12_11 register field value. */
69517 #define ALT_EMAC_DMA_STAT_RSVD_12_11_CLR_MSK 0xffffe7ff
69518 /* The reset value of the ALT_EMAC_DMA_STAT_RSVD_12_11 register field. */
69519 #define ALT_EMAC_DMA_STAT_RSVD_12_11_RESET 0x0
69520 /* Extracts the ALT_EMAC_DMA_STAT_RSVD_12_11 field value from a register. */
69521 #define ALT_EMAC_DMA_STAT_RSVD_12_11_GET(value) (((value) & 0x00001800) >> 11)
69522 /* Produces a ALT_EMAC_DMA_STAT_RSVD_12_11 register field value suitable for setting the register. */
69523 #define ALT_EMAC_DMA_STAT_RSVD_12_11_SET(value) (((value) << 11) & 0x00001800)
69524 
69525 /*
69526  * Field : fbi
69527  *
69528  * Fatal Bus Error Interrupt
69529  *
69530  * This bit indicates that a bus error occurred, as described in Bits[25:23]. When
69531  * this bit is set, the corresponding DMA engine disables all of its bus accesses.
69532  *
69533  * Field Access Macros:
69534  *
69535  */
69536 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_FBI register field. */
69537 #define ALT_EMAC_DMA_STAT_FBI_LSB 13
69538 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_FBI register field. */
69539 #define ALT_EMAC_DMA_STAT_FBI_MSB 13
69540 /* The width in bits of the ALT_EMAC_DMA_STAT_FBI register field. */
69541 #define ALT_EMAC_DMA_STAT_FBI_WIDTH 1
69542 /* The mask used to set the ALT_EMAC_DMA_STAT_FBI register field value. */
69543 #define ALT_EMAC_DMA_STAT_FBI_SET_MSK 0x00002000
69544 /* The mask used to clear the ALT_EMAC_DMA_STAT_FBI register field value. */
69545 #define ALT_EMAC_DMA_STAT_FBI_CLR_MSK 0xffffdfff
69546 /* The reset value of the ALT_EMAC_DMA_STAT_FBI register field. */
69547 #define ALT_EMAC_DMA_STAT_FBI_RESET 0x0
69548 /* Extracts the ALT_EMAC_DMA_STAT_FBI field value from a register. */
69549 #define ALT_EMAC_DMA_STAT_FBI_GET(value) (((value) & 0x00002000) >> 13)
69550 /* Produces a ALT_EMAC_DMA_STAT_FBI register field value suitable for setting the register. */
69551 #define ALT_EMAC_DMA_STAT_FBI_SET(value) (((value) << 13) & 0x00002000)
69552 
69553 /*
69554  * Field : eri
69555  *
69556  * Early Receive Interrupt
69557  *
69558  * This bit indicates that the DMA filled the first data buffer of the packet. This
69559  * bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this
69560  * register is set (whichever occurs earlier).
69561  *
69562  * Field Access Macros:
69563  *
69564  */
69565 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_ERI register field. */
69566 #define ALT_EMAC_DMA_STAT_ERI_LSB 14
69567 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_ERI register field. */
69568 #define ALT_EMAC_DMA_STAT_ERI_MSB 14
69569 /* The width in bits of the ALT_EMAC_DMA_STAT_ERI register field. */
69570 #define ALT_EMAC_DMA_STAT_ERI_WIDTH 1
69571 /* The mask used to set the ALT_EMAC_DMA_STAT_ERI register field value. */
69572 #define ALT_EMAC_DMA_STAT_ERI_SET_MSK 0x00004000
69573 /* The mask used to clear the ALT_EMAC_DMA_STAT_ERI register field value. */
69574 #define ALT_EMAC_DMA_STAT_ERI_CLR_MSK 0xffffbfff
69575 /* The reset value of the ALT_EMAC_DMA_STAT_ERI register field. */
69576 #define ALT_EMAC_DMA_STAT_ERI_RESET 0x0
69577 /* Extracts the ALT_EMAC_DMA_STAT_ERI field value from a register. */
69578 #define ALT_EMAC_DMA_STAT_ERI_GET(value) (((value) & 0x00004000) >> 14)
69579 /* Produces a ALT_EMAC_DMA_STAT_ERI register field value suitable for setting the register. */
69580 #define ALT_EMAC_DMA_STAT_ERI_SET(value) (((value) << 14) & 0x00004000)
69581 
69582 /*
69583  * Field : ais
69584  *
69585  * Abnormal Interrupt Summary
69586  *
69587  * Abnormal Interrupt Summary bit value is the logical OR of the following when the
69588  * corresponding interrupt bits are enabled in Register 7 (Interrupt Enable
69589  * Register):
69590  *
69591  * * Register 5[1]: Transmit Process Stopped
69592  *
69593  * * Register 5[3]: Transmit Jabber Timeout
69594  *
69595  * * Register 5[4]: Receive FIFO Overflow
69596  *
69597  * * Register 5[5]: Transmit Underflow
69598  *
69599  * * Register 5[7]: Receive Buffer Unavailable
69600  *
69601  * * Register 5[8]: Receive Process Stopped
69602  *
69603  * * Register 5[9]: Receive Watchdog Timeout
69604  *
69605  * * Register 5[10]: Early Transmit Interrupt
69606  *
69607  * * Register 5[13]: Fatal Bus Error
69608  *
69609  * Only unmasked bits affect the Abnormal Interrupt Summary bit.
69610  *
69611  * This is a sticky bit and must be cleared each time a corresponding bit, which
69612  * causes AIS to be set, is cleared.
69613  *
69614  * Field Access Macros:
69615  *
69616  */
69617 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_AIS register field. */
69618 #define ALT_EMAC_DMA_STAT_AIS_LSB 15
69619 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_AIS register field. */
69620 #define ALT_EMAC_DMA_STAT_AIS_MSB 15
69621 /* The width in bits of the ALT_EMAC_DMA_STAT_AIS register field. */
69622 #define ALT_EMAC_DMA_STAT_AIS_WIDTH 1
69623 /* The mask used to set the ALT_EMAC_DMA_STAT_AIS register field value. */
69624 #define ALT_EMAC_DMA_STAT_AIS_SET_MSK 0x00008000
69625 /* The mask used to clear the ALT_EMAC_DMA_STAT_AIS register field value. */
69626 #define ALT_EMAC_DMA_STAT_AIS_CLR_MSK 0xffff7fff
69627 /* The reset value of the ALT_EMAC_DMA_STAT_AIS register field. */
69628 #define ALT_EMAC_DMA_STAT_AIS_RESET 0x0
69629 /* Extracts the ALT_EMAC_DMA_STAT_AIS field value from a register. */
69630 #define ALT_EMAC_DMA_STAT_AIS_GET(value) (((value) & 0x00008000) >> 15)
69631 /* Produces a ALT_EMAC_DMA_STAT_AIS register field value suitable for setting the register. */
69632 #define ALT_EMAC_DMA_STAT_AIS_SET(value) (((value) << 15) & 0x00008000)
69633 
69634 /*
69635  * Field : nis
69636  *
69637  * Normal Interrupt Summary
69638  *
69639  * Normal Interrupt Summary bit value is the logical OR of the following when the
69640  * corresponding interrupt bits are enabled in Register 7 (Interrupt Enable
69641  * Register):
69642  *
69643  * * Register 5[0]: Transmit Interrupt
69644  *
69645  * * Register 5[2]: Transmit Buffer Unavailable
69646  *
69647  * * Register 5[6]: Receive Interrupt
69648  *
69649  * * Register 5[14]: Early Receive Interrupt
69650  *
69651  * Only unmasked bits (interrupts for which interrupt enable is set in Register 7)
69652  * affect the Normal Interrupt Summary bit.
69653  *
69654  * This is a sticky bit and must be cleared (by writing 1 to this bit) each time a
69655  * corresponding bit, which causes NIS to be set, is cleared.
69656  *
69657  * Field Access Macros:
69658  *
69659  */
69660 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_NIS register field. */
69661 #define ALT_EMAC_DMA_STAT_NIS_LSB 16
69662 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_NIS register field. */
69663 #define ALT_EMAC_DMA_STAT_NIS_MSB 16
69664 /* The width in bits of the ALT_EMAC_DMA_STAT_NIS register field. */
69665 #define ALT_EMAC_DMA_STAT_NIS_WIDTH 1
69666 /* The mask used to set the ALT_EMAC_DMA_STAT_NIS register field value. */
69667 #define ALT_EMAC_DMA_STAT_NIS_SET_MSK 0x00010000
69668 /* The mask used to clear the ALT_EMAC_DMA_STAT_NIS register field value. */
69669 #define ALT_EMAC_DMA_STAT_NIS_CLR_MSK 0xfffeffff
69670 /* The reset value of the ALT_EMAC_DMA_STAT_NIS register field. */
69671 #define ALT_EMAC_DMA_STAT_NIS_RESET 0x0
69672 /* Extracts the ALT_EMAC_DMA_STAT_NIS field value from a register. */
69673 #define ALT_EMAC_DMA_STAT_NIS_GET(value) (((value) & 0x00010000) >> 16)
69674 /* Produces a ALT_EMAC_DMA_STAT_NIS register field value suitable for setting the register. */
69675 #define ALT_EMAC_DMA_STAT_NIS_SET(value) (((value) << 16) & 0x00010000)
69676 
69677 /*
69678  * Field : rs
69679  *
69680  * Received Process State
69681  *
69682  * This field indicates the Receive DMA FSM state. This field does not generate an
69683  * interrupt.
69684  *
69685  * * 3'b000: Stopped: Reset or Stop Receive Command issued
69686  *
69687  * * 3'b001: Running: Fetching Receive Transfer Descriptor
69688  *
69689  * * 3'b010: Reserved for future use
69690  *
69691  * * 3'b011: Running: Waiting for receive packet
69692  *
69693  * * 3'b100: Suspended: Receive Descriptor Unavailable
69694  *
69695  * * 3'b101: Running: Closing Receive Descriptor
69696  *
69697  * * 3'b110: TIME_STAMP write state
69698  *
69699  * * 3'b111: Running: Transferring the receive packet data from receive buffer to
69700  * host memory
69701  *
69702  * Field Enumeration Values:
69703  *
69704  * Enum | Value | Description
69705  * :--------------------------------|:------|:------------
69706  * ALT_EMAC_DMA_STAT_RS_E_STOPPED | 0x0 |
69707  * ALT_EMAC_DMA_STAT_RS_E_RUNFETCH | 0x1 |
69708  * ALT_EMAC_DMA_STAT_RS_E_RESERVE | 0x2 |
69709  * ALT_EMAC_DMA_STAT_RS_E_RUNWAIT | 0x3 |
69710  * ALT_EMAC_DMA_STAT_RS_E_SUSPEND | 0x4 |
69711  * ALT_EMAC_DMA_STAT_RS_E_RUNCLOSE | 0x5 |
69712  * ALT_EMAC_DMA_STAT_RS_E_TIMESTMP | 0x6 |
69713  * ALT_EMAC_DMA_STAT_RS_E_RUNTRANS | 0x7 |
69714  *
69715  * Field Access Macros:
69716  *
69717  */
69718 /*
69719  * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
69720  *
69721  */
69722 #define ALT_EMAC_DMA_STAT_RS_E_STOPPED 0x0
69723 /*
69724  * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
69725  *
69726  */
69727 #define ALT_EMAC_DMA_STAT_RS_E_RUNFETCH 0x1
69728 /*
69729  * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
69730  *
69731  */
69732 #define ALT_EMAC_DMA_STAT_RS_E_RESERVE 0x2
69733 /*
69734  * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
69735  *
69736  */
69737 #define ALT_EMAC_DMA_STAT_RS_E_RUNWAIT 0x3
69738 /*
69739  * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
69740  *
69741  */
69742 #define ALT_EMAC_DMA_STAT_RS_E_SUSPEND 0x4
69743 /*
69744  * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
69745  *
69746  */
69747 #define ALT_EMAC_DMA_STAT_RS_E_RUNCLOSE 0x5
69748 /*
69749  * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
69750  *
69751  */
69752 #define ALT_EMAC_DMA_STAT_RS_E_TIMESTMP 0x6
69753 /*
69754  * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
69755  *
69756  */
69757 #define ALT_EMAC_DMA_STAT_RS_E_RUNTRANS 0x7
69758 
69759 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RS register field. */
69760 #define ALT_EMAC_DMA_STAT_RS_LSB 17
69761 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RS register field. */
69762 #define ALT_EMAC_DMA_STAT_RS_MSB 19
69763 /* The width in bits of the ALT_EMAC_DMA_STAT_RS register field. */
69764 #define ALT_EMAC_DMA_STAT_RS_WIDTH 3
69765 /* The mask used to set the ALT_EMAC_DMA_STAT_RS register field value. */
69766 #define ALT_EMAC_DMA_STAT_RS_SET_MSK 0x000e0000
69767 /* The mask used to clear the ALT_EMAC_DMA_STAT_RS register field value. */
69768 #define ALT_EMAC_DMA_STAT_RS_CLR_MSK 0xfff1ffff
69769 /* The reset value of the ALT_EMAC_DMA_STAT_RS register field. */
69770 #define ALT_EMAC_DMA_STAT_RS_RESET 0x0
69771 /* Extracts the ALT_EMAC_DMA_STAT_RS field value from a register. */
69772 #define ALT_EMAC_DMA_STAT_RS_GET(value) (((value) & 0x000e0000) >> 17)
69773 /* Produces a ALT_EMAC_DMA_STAT_RS register field value suitable for setting the register. */
69774 #define ALT_EMAC_DMA_STAT_RS_SET(value) (((value) << 17) & 0x000e0000)
69775 
69776 /*
69777  * Field : ts
69778  *
69779  * Transmit Process State
69780  *
69781  * This field indicates the Transmit DMA FSM state. This field does not generate an
69782  * interrupt.
69783  *
69784  * * 3'b000: Stopped; Reset or Stop Transmit Command issued
69785  *
69786  * * 3'b001: Running; Fetching Transmit Transfer Descriptor
69787  *
69788  * * 3'b010: Running; Waiting for status
69789  *
69790  * * 3'b011: Running; Reading Data from host memory buffer and queuing it to
69791  * transmit buffer (Tx FIFO)
69792  *
69793  * * 3'b100: TIME_STAMP write state
69794  *
69795  * * 3'b101: Reserved for future use
69796  *
69797  * * 3'b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer
69798  * Underflow
69799  *
69800  * * 3'b111: Running; Closing Transmit Descriptor
69801  *
69802  * Field Enumeration Values:
69803  *
69804  * Enum | Value | Description
69805  * :--------------------------------|:------|:------------
69806  * ALT_EMAC_DMA_STAT_TS_E_STOPPED | 0x0 |
69807  * ALT_EMAC_DMA_STAT_TS_E_RUNFETCH | 0x1 |
69808  * ALT_EMAC_DMA_STAT_TS_E_RUNWAIT | 0x2 |
69809  * ALT_EMAC_DMA_STAT_TS_E_RUNRD | 0x3 |
69810  * ALT_EMAC_DMA_STAT_TS_E_TIMESTMP | 0x4 |
69811  * ALT_EMAC_DMA_STAT_TS_E_RESERVE | 0x5 |
69812  * ALT_EMAC_DMA_STAT_TS_E_SUSPTX | 0x6 |
69813  * ALT_EMAC_DMA_STAT_TS_E_RUNCLOSE | 0x7 |
69814  *
69815  * Field Access Macros:
69816  *
69817  */
69818 /*
69819  * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
69820  *
69821  */
69822 #define ALT_EMAC_DMA_STAT_TS_E_STOPPED 0x0
69823 /*
69824  * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
69825  *
69826  */
69827 #define ALT_EMAC_DMA_STAT_TS_E_RUNFETCH 0x1
69828 /*
69829  * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
69830  *
69831  */
69832 #define ALT_EMAC_DMA_STAT_TS_E_RUNWAIT 0x2
69833 /*
69834  * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
69835  *
69836  */
69837 #define ALT_EMAC_DMA_STAT_TS_E_RUNRD 0x3
69838 /*
69839  * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
69840  *
69841  */
69842 #define ALT_EMAC_DMA_STAT_TS_E_TIMESTMP 0x4
69843 /*
69844  * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
69845  *
69846  */
69847 #define ALT_EMAC_DMA_STAT_TS_E_RESERVE 0x5
69848 /*
69849  * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
69850  *
69851  */
69852 #define ALT_EMAC_DMA_STAT_TS_E_SUSPTX 0x6
69853 /*
69854  * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
69855  *
69856  */
69857 #define ALT_EMAC_DMA_STAT_TS_E_RUNCLOSE 0x7
69858 
69859 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TS register field. */
69860 #define ALT_EMAC_DMA_STAT_TS_LSB 20
69861 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TS register field. */
69862 #define ALT_EMAC_DMA_STAT_TS_MSB 22
69863 /* The width in bits of the ALT_EMAC_DMA_STAT_TS register field. */
69864 #define ALT_EMAC_DMA_STAT_TS_WIDTH 3
69865 /* The mask used to set the ALT_EMAC_DMA_STAT_TS register field value. */
69866 #define ALT_EMAC_DMA_STAT_TS_SET_MSK 0x00700000
69867 /* The mask used to clear the ALT_EMAC_DMA_STAT_TS register field value. */
69868 #define ALT_EMAC_DMA_STAT_TS_CLR_MSK 0xff8fffff
69869 /* The reset value of the ALT_EMAC_DMA_STAT_TS register field. */
69870 #define ALT_EMAC_DMA_STAT_TS_RESET 0x0
69871 /* Extracts the ALT_EMAC_DMA_STAT_TS field value from a register. */
69872 #define ALT_EMAC_DMA_STAT_TS_GET(value) (((value) & 0x00700000) >> 20)
69873 /* Produces a ALT_EMAC_DMA_STAT_TS register field value suitable for setting the register. */
69874 #define ALT_EMAC_DMA_STAT_TS_SET(value) (((value) << 20) & 0x00700000)
69875 
69876 /*
69877  * Field : eb
69878  *
69879  * Error Bits
69880  *
69881  * This field indicates the type of error that caused a Bus Error, for example,
69882  * error response on the AHB or AXI interface. This field is valid only when Bit 13
69883  * (FBI) is set. This field does not generate an interrupt.
69884  *
69885  * * 0 0 0: Error during Rx DMA Write Data Transfer
69886  *
69887  * * 0 1 1: Error during Tx DMA Read Data Transfer
69888  *
69889  * * 1 0 0: Error during Rx DMA Descriptor Write Access
69890  *
69891  * * 1 0 1: Error during Tx DMA Descriptor Write Access
69892  *
69893  * * 1 1 0: Error during Rx DMA Descriptor Read Access
69894  *
69895  * * 1 1 1: Error during Tx DMA Descriptor Read Access
69896  *
69897  * Note: 001 and 010 are reserved.
69898  *
69899  * Field Access Macros:
69900  *
69901  */
69902 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_EB register field. */
69903 #define ALT_EMAC_DMA_STAT_EB_LSB 23
69904 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_EB register field. */
69905 #define ALT_EMAC_DMA_STAT_EB_MSB 25
69906 /* The width in bits of the ALT_EMAC_DMA_STAT_EB register field. */
69907 #define ALT_EMAC_DMA_STAT_EB_WIDTH 3
69908 /* The mask used to set the ALT_EMAC_DMA_STAT_EB register field value. */
69909 #define ALT_EMAC_DMA_STAT_EB_SET_MSK 0x03800000
69910 /* The mask used to clear the ALT_EMAC_DMA_STAT_EB register field value. */
69911 #define ALT_EMAC_DMA_STAT_EB_CLR_MSK 0xfc7fffff
69912 /* The reset value of the ALT_EMAC_DMA_STAT_EB register field. */
69913 #define ALT_EMAC_DMA_STAT_EB_RESET 0x0
69914 /* Extracts the ALT_EMAC_DMA_STAT_EB field value from a register. */
69915 #define ALT_EMAC_DMA_STAT_EB_GET(value) (((value) & 0x03800000) >> 23)
69916 /* Produces a ALT_EMAC_DMA_STAT_EB register field value suitable for setting the register. */
69917 #define ALT_EMAC_DMA_STAT_EB_SET(value) (((value) << 23) & 0x03800000)
69918 
69919 /*
69920  * Field : gli
69921  *
69922  * GMAC Line interface Interrupt
69923  *
69924  * When set, this bit reflects any of the following interrupt events in the
69925  * DWC_gmac
69926  *
69927  * interfaces (if present and enabled in your configuration):
69928  *
69929  * * PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event
69930  *
69931  * * SMII or RGMII: Link change event
69932  *
69933  * * General Purpose Input Status (GPIS): Any LL or LH event on the gpi_i input
69934  * ports
69935  *
69936  * To identify the exact cause of the interrupt, the software must first read Bit
69937  * 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear
69938  * the source of interrupt (which also clears the GLI interrupt), read any of the
69939  * following corresponding registers:
69940  *
69941  * * PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register)
69942  *
69943  * * SMII or RGMII: Register 54 (SGMII/RGMII/SMII Status Register)
69944  *
69945  * * General Purpose Input (GPI): Register 56 (General Purpose IO Register)
69946  *
69947  * The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this
69948  * bit is high.
69949  *
69950  * Field Enumeration Values:
69951  *
69952  * Enum | Value | Description
69953  * :-----------------------------------|:------|:------------
69954  * ALT_EMAC_DMA_STAT_GLI_E_NOINTERRUP | 0x0 |
69955  * ALT_EMAC_DMA_STAT_GLI_E_INTERRUP | 0x1 |
69956  *
69957  * Field Access Macros:
69958  *
69959  */
69960 /*
69961  * Enumerated value for register field ALT_EMAC_DMA_STAT_GLI
69962  *
69963  */
69964 #define ALT_EMAC_DMA_STAT_GLI_E_NOINTERRUP 0x0
69965 /*
69966  * Enumerated value for register field ALT_EMAC_DMA_STAT_GLI
69967  *
69968  */
69969 #define ALT_EMAC_DMA_STAT_GLI_E_INTERRUP 0x1
69970 
69971 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_GLI register field. */
69972 #define ALT_EMAC_DMA_STAT_GLI_LSB 26
69973 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_GLI register field. */
69974 #define ALT_EMAC_DMA_STAT_GLI_MSB 26
69975 /* The width in bits of the ALT_EMAC_DMA_STAT_GLI register field. */
69976 #define ALT_EMAC_DMA_STAT_GLI_WIDTH 1
69977 /* The mask used to set the ALT_EMAC_DMA_STAT_GLI register field value. */
69978 #define ALT_EMAC_DMA_STAT_GLI_SET_MSK 0x04000000
69979 /* The mask used to clear the ALT_EMAC_DMA_STAT_GLI register field value. */
69980 #define ALT_EMAC_DMA_STAT_GLI_CLR_MSK 0xfbffffff
69981 /* The reset value of the ALT_EMAC_DMA_STAT_GLI register field. */
69982 #define ALT_EMAC_DMA_STAT_GLI_RESET 0x0
69983 /* Extracts the ALT_EMAC_DMA_STAT_GLI field value from a register. */
69984 #define ALT_EMAC_DMA_STAT_GLI_GET(value) (((value) & 0x04000000) >> 26)
69985 /* Produces a ALT_EMAC_DMA_STAT_GLI register field value suitable for setting the register. */
69986 #define ALT_EMAC_DMA_STAT_GLI_SET(value) (((value) << 26) & 0x04000000)
69987 
69988 /*
69989  * Field : gmi
69990  *
69991  * GMAC MMC Interrupt
69992  *
69993  * This bit reflects an interrupt event in the MMC module of the DWC_gmac. The
69994  * software must read the corresponding registers in the DWC_gmac to get the exact
69995  * cause of interrupt and clear the source of interrupt to make this bit as 1'b0.
69996  * The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this
69997  * bit is high.
69998  *
69999  * This bit is applicable only when the MAC Management Counters (MMC) are enabled.
70000  * Otherwise, this bit is reserved.
70001  *
70002  * Field Enumeration Values:
70003  *
70004  * Enum | Value | Description
70005  * :-----------------------------------|:------|:------------
70006  * ALT_EMAC_DMA_STAT_GMI_E_NOINTERRUP | 0x0 |
70007  * ALT_EMAC_DMA_STAT_GMI_E_INTERRUP | 0x1 |
70008  *
70009  * Field Access Macros:
70010  *
70011  */
70012 /*
70013  * Enumerated value for register field ALT_EMAC_DMA_STAT_GMI
70014  *
70015  */
70016 #define ALT_EMAC_DMA_STAT_GMI_E_NOINTERRUP 0x0
70017 /*
70018  * Enumerated value for register field ALT_EMAC_DMA_STAT_GMI
70019  *
70020  */
70021 #define ALT_EMAC_DMA_STAT_GMI_E_INTERRUP 0x1
70022 
70023 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_GMI register field. */
70024 #define ALT_EMAC_DMA_STAT_GMI_LSB 27
70025 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_GMI register field. */
70026 #define ALT_EMAC_DMA_STAT_GMI_MSB 27
70027 /* The width in bits of the ALT_EMAC_DMA_STAT_GMI register field. */
70028 #define ALT_EMAC_DMA_STAT_GMI_WIDTH 1
70029 /* The mask used to set the ALT_EMAC_DMA_STAT_GMI register field value. */
70030 #define ALT_EMAC_DMA_STAT_GMI_SET_MSK 0x08000000
70031 /* The mask used to clear the ALT_EMAC_DMA_STAT_GMI register field value. */
70032 #define ALT_EMAC_DMA_STAT_GMI_CLR_MSK 0xf7ffffff
70033 /* The reset value of the ALT_EMAC_DMA_STAT_GMI register field. */
70034 #define ALT_EMAC_DMA_STAT_GMI_RESET 0x0
70035 /* Extracts the ALT_EMAC_DMA_STAT_GMI field value from a register. */
70036 #define ALT_EMAC_DMA_STAT_GMI_GET(value) (((value) & 0x08000000) >> 27)
70037 /* Produces a ALT_EMAC_DMA_STAT_GMI register field value suitable for setting the register. */
70038 #define ALT_EMAC_DMA_STAT_GMI_SET(value) (((value) << 27) & 0x08000000)
70039 
70040 /*
70041  * Field : gpi
70042  *
70043  * GMAC PMT Interrupt
70044  *
70045  * This bit indicates an interrupt event in the PMT module of the DWC_gmac. The
70046  * software must read the PMT Control and Status Register in the MAC to get the
70047  * exact cause of interrupt and clear its source to reset this bit to 1'b0. The
70048  * interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit
70049  * is high.
70050  *
70051  * This bit is applicable only when the Power Management feature is enabled.
70052  * Otherwise, this bit is reserved.
70053  *
70054  * Note: The GPI and pmt_intr_o interrupts are generated in different clock
70055  * domains.
70056  *
70057  * Field Access Macros:
70058  *
70059  */
70060 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_GPI register field. */
70061 #define ALT_EMAC_DMA_STAT_GPI_LSB 28
70062 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_GPI register field. */
70063 #define ALT_EMAC_DMA_STAT_GPI_MSB 28
70064 /* The width in bits of the ALT_EMAC_DMA_STAT_GPI register field. */
70065 #define ALT_EMAC_DMA_STAT_GPI_WIDTH 1
70066 /* The mask used to set the ALT_EMAC_DMA_STAT_GPI register field value. */
70067 #define ALT_EMAC_DMA_STAT_GPI_SET_MSK 0x10000000
70068 /* The mask used to clear the ALT_EMAC_DMA_STAT_GPI register field value. */
70069 #define ALT_EMAC_DMA_STAT_GPI_CLR_MSK 0xefffffff
70070 /* The reset value of the ALT_EMAC_DMA_STAT_GPI register field. */
70071 #define ALT_EMAC_DMA_STAT_GPI_RESET 0x0
70072 /* Extracts the ALT_EMAC_DMA_STAT_GPI field value from a register. */
70073 #define ALT_EMAC_DMA_STAT_GPI_GET(value) (((value) & 0x10000000) >> 28)
70074 /* Produces a ALT_EMAC_DMA_STAT_GPI register field value suitable for setting the register. */
70075 #define ALT_EMAC_DMA_STAT_GPI_SET(value) (((value) << 28) & 0x10000000)
70076 
70077 /*
70078  * Field : tti
70079  *
70080  * Timestamp Trigger Interrupt
70081  *
70082  * This bit indicates an interrupt event in the Timestamp Generator block of
70083  * DWC_gmac. The software must read the corresponding registers in the DWC_gmac to
70084  * get the exact cause of interrupt and clear its source to reset this bit to 1'b0.
70085  * When this bit is high, the interrupt signal from the DWC_gmac subsystem
70086  * (sbd_intr_o) is high.
70087  *
70088  * This bit is applicable only when the IEEE 1588 Timestamp feature is enabled.
70089  * Otherwise, this bit is reserved.
70090  *
70091  * Field Enumeration Values:
70092  *
70093  * Enum | Value | Description
70094  * :-----------------------------------|:------|:------------
70095  * ALT_EMAC_DMA_STAT_TTI_E_NOINTERRUP | 0x0 |
70096  * ALT_EMAC_DMA_STAT_TTI_E_INTERRUP | 0x1 |
70097  *
70098  * Field Access Macros:
70099  *
70100  */
70101 /*
70102  * Enumerated value for register field ALT_EMAC_DMA_STAT_TTI
70103  *
70104  */
70105 #define ALT_EMAC_DMA_STAT_TTI_E_NOINTERRUP 0x0
70106 /*
70107  * Enumerated value for register field ALT_EMAC_DMA_STAT_TTI
70108  *
70109  */
70110 #define ALT_EMAC_DMA_STAT_TTI_E_INTERRUP 0x1
70111 
70112 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TTI register field. */
70113 #define ALT_EMAC_DMA_STAT_TTI_LSB 29
70114 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TTI register field. */
70115 #define ALT_EMAC_DMA_STAT_TTI_MSB 29
70116 /* The width in bits of the ALT_EMAC_DMA_STAT_TTI register field. */
70117 #define ALT_EMAC_DMA_STAT_TTI_WIDTH 1
70118 /* The mask used to set the ALT_EMAC_DMA_STAT_TTI register field value. */
70119 #define ALT_EMAC_DMA_STAT_TTI_SET_MSK 0x20000000
70120 /* The mask used to clear the ALT_EMAC_DMA_STAT_TTI register field value. */
70121 #define ALT_EMAC_DMA_STAT_TTI_CLR_MSK 0xdfffffff
70122 /* The reset value of the ALT_EMAC_DMA_STAT_TTI register field. */
70123 #define ALT_EMAC_DMA_STAT_TTI_RESET 0x0
70124 /* Extracts the ALT_EMAC_DMA_STAT_TTI field value from a register. */
70125 #define ALT_EMAC_DMA_STAT_TTI_GET(value) (((value) & 0x20000000) >> 29)
70126 /* Produces a ALT_EMAC_DMA_STAT_TTI register field value suitable for setting the register. */
70127 #define ALT_EMAC_DMA_STAT_TTI_SET(value) (((value) << 29) & 0x20000000)
70128 
70129 /*
70130  * Field : glpii
70131  *
70132  * GMAC LPI Interrupt (for Channel 0)
70133  *
70134  * This bit indicates an interrupt event in the LPI logic of the DWC_gmac. To reset
70135  * this bit to 1'b0, the software must read the corresponding registers in the
70136  * DWC_gmac to get the exact cause of the interrupt and clear its source.
70137  *
70138  * Note: GLPII status is given only in Channel 0 DMA register and is applicable
70139  * only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit
70140  * is reserved.When this bit is high, the interrupt signal from the MAC
70141  * (sbd_intr_o) is high.
70142  *
70143  * Field Enumeration Values:
70144  *
70145  * Enum | Value | Description
70146  * :-------------------------------------|:------|:------------
70147  * ALT_EMAC_DMA_STAT_GLPII_E_NOINTERRUP | 0x0 |
70148  * ALT_EMAC_DMA_STAT_GLPII_E_INTERRUP | 0x1 |
70149  *
70150  * Field Access Macros:
70151  *
70152  */
70153 /*
70154  * Enumerated value for register field ALT_EMAC_DMA_STAT_GLPII
70155  *
70156  */
70157 #define ALT_EMAC_DMA_STAT_GLPII_E_NOINTERRUP 0x0
70158 /*
70159  * Enumerated value for register field ALT_EMAC_DMA_STAT_GLPII
70160  *
70161  */
70162 #define ALT_EMAC_DMA_STAT_GLPII_E_INTERRUP 0x1
70163 
70164 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_GLPII register field. */
70165 #define ALT_EMAC_DMA_STAT_GLPII_LSB 30
70166 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_GLPII register field. */
70167 #define ALT_EMAC_DMA_STAT_GLPII_MSB 30
70168 /* The width in bits of the ALT_EMAC_DMA_STAT_GLPII register field. */
70169 #define ALT_EMAC_DMA_STAT_GLPII_WIDTH 1
70170 /* The mask used to set the ALT_EMAC_DMA_STAT_GLPII register field value. */
70171 #define ALT_EMAC_DMA_STAT_GLPII_SET_MSK 0x40000000
70172 /* The mask used to clear the ALT_EMAC_DMA_STAT_GLPII register field value. */
70173 #define ALT_EMAC_DMA_STAT_GLPII_CLR_MSK 0xbfffffff
70174 /* The reset value of the ALT_EMAC_DMA_STAT_GLPII register field. */
70175 #define ALT_EMAC_DMA_STAT_GLPII_RESET 0x0
70176 /* Extracts the ALT_EMAC_DMA_STAT_GLPII field value from a register. */
70177 #define ALT_EMAC_DMA_STAT_GLPII_GET(value) (((value) & 0x40000000) >> 30)
70178 /* Produces a ALT_EMAC_DMA_STAT_GLPII register field value suitable for setting the register. */
70179 #define ALT_EMAC_DMA_STAT_GLPII_SET(value) (((value) << 30) & 0x40000000)
70180 
70181 /*
70182  * Field : reserved_31
70183  *
70184  * Reserved
70185  *
70186  * Field Access Macros:
70187  *
70188  */
70189 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RSVD_31 register field. */
70190 #define ALT_EMAC_DMA_STAT_RSVD_31_LSB 31
70191 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RSVD_31 register field. */
70192 #define ALT_EMAC_DMA_STAT_RSVD_31_MSB 31
70193 /* The width in bits of the ALT_EMAC_DMA_STAT_RSVD_31 register field. */
70194 #define ALT_EMAC_DMA_STAT_RSVD_31_WIDTH 1
70195 /* The mask used to set the ALT_EMAC_DMA_STAT_RSVD_31 register field value. */
70196 #define ALT_EMAC_DMA_STAT_RSVD_31_SET_MSK 0x80000000
70197 /* The mask used to clear the ALT_EMAC_DMA_STAT_RSVD_31 register field value. */
70198 #define ALT_EMAC_DMA_STAT_RSVD_31_CLR_MSK 0x7fffffff
70199 /* The reset value of the ALT_EMAC_DMA_STAT_RSVD_31 register field. */
70200 #define ALT_EMAC_DMA_STAT_RSVD_31_RESET 0x0
70201 /* Extracts the ALT_EMAC_DMA_STAT_RSVD_31 field value from a register. */
70202 #define ALT_EMAC_DMA_STAT_RSVD_31_GET(value) (((value) & 0x80000000) >> 31)
70203 /* Produces a ALT_EMAC_DMA_STAT_RSVD_31 register field value suitable for setting the register. */
70204 #define ALT_EMAC_DMA_STAT_RSVD_31_SET(value) (((value) << 31) & 0x80000000)
70205 
70206 #ifndef __ASSEMBLY__
70207 /*
70208  * WARNING: The C register and register group struct declarations are provided for
70209  * convenience and illustrative purposes. They should, however, be used with
70210  * caution as the C language standard provides no guarantees about the alignment or
70211  * atomicity of device memory accesses. The recommended practice for writing
70212  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
70213  * alt_write_word() functions.
70214  *
70215  * The struct declaration for register ALT_EMAC_DMA_STAT.
70216  */
70217 struct ALT_EMAC_DMA_STAT_s
70218 {
70219  uint32_t ti : 1; /* ALT_EMAC_DMA_STAT_TI */
70220  uint32_t tps : 1; /* ALT_EMAC_DMA_STAT_TPS */
70221  uint32_t tu : 1; /* ALT_EMAC_DMA_STAT_TU */
70222  uint32_t tjt : 1; /* ALT_EMAC_DMA_STAT_TJT */
70223  uint32_t ovf : 1; /* ALT_EMAC_DMA_STAT_OVF */
70224  uint32_t unf : 1; /* ALT_EMAC_DMA_STAT_UNF */
70225  uint32_t ri : 1; /* ALT_EMAC_DMA_STAT_RI */
70226  uint32_t ru : 1; /* ALT_EMAC_DMA_STAT_RU */
70227  uint32_t rps : 1; /* ALT_EMAC_DMA_STAT_RPS */
70228  uint32_t rwt : 1; /* ALT_EMAC_DMA_STAT_RWT */
70229  uint32_t eti : 1; /* ALT_EMAC_DMA_STAT_ETI */
70230  const uint32_t reserved_12_11 : 2; /* ALT_EMAC_DMA_STAT_RSVD_12_11 */
70231  uint32_t fbi : 1; /* ALT_EMAC_DMA_STAT_FBI */
70232  uint32_t eri : 1; /* ALT_EMAC_DMA_STAT_ERI */
70233  uint32_t ais : 1; /* ALT_EMAC_DMA_STAT_AIS */
70234  uint32_t nis : 1; /* ALT_EMAC_DMA_STAT_NIS */
70235  const uint32_t rs : 3; /* ALT_EMAC_DMA_STAT_RS */
70236  const uint32_t ts : 3; /* ALT_EMAC_DMA_STAT_TS */
70237  const uint32_t eb : 3; /* ALT_EMAC_DMA_STAT_EB */
70238  const uint32_t gli : 1; /* ALT_EMAC_DMA_STAT_GLI */
70239  const uint32_t gmi : 1; /* ALT_EMAC_DMA_STAT_GMI */
70240  const uint32_t gpi : 1; /* ALT_EMAC_DMA_STAT_GPI */
70241  const uint32_t tti : 1; /* ALT_EMAC_DMA_STAT_TTI */
70242  const uint32_t glpii : 1; /* ALT_EMAC_DMA_STAT_GLPII */
70243  const uint32_t reserved_31 : 1; /* ALT_EMAC_DMA_STAT_RSVD_31 */
70244 };
70245 
70246 /* The typedef declaration for register ALT_EMAC_DMA_STAT. */
70247 typedef volatile struct ALT_EMAC_DMA_STAT_s ALT_EMAC_DMA_STAT_t;
70248 #endif /* __ASSEMBLY__ */
70249 
70250 /* The reset value of the ALT_EMAC_DMA_STAT register. */
70251 #define ALT_EMAC_DMA_STAT_RESET 0x00000000
70252 /* The byte offset of the ALT_EMAC_DMA_STAT register from the beginning of the component. */
70253 #define ALT_EMAC_DMA_STAT_OFST 0x1014
70254 /* The address of the ALT_EMAC_DMA_STAT register. */
70255 #define ALT_EMAC_DMA_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_STAT_OFST))
70256 
70257 /*
70258  * Register : dmagrp_operation_mode
70259  *
70260  * <b> Register 6 (Operation Mode Register) </b>
70261  *
70262  * The Operation Mode register establishes the Transmit and Receive operating modes
70263  * and commands. This register should be the last CSR to be written as part of the
70264  * DMA initialization. This register is also present in the GMAC-MTL configuration
70265  * with unused and reserved bits 24, 13, 2, and 1.
70266  *
70267  * Register Layout
70268  *
70269  * Bits | Access | Reset | Description
70270  * :--------|:-------|:------|:-------------------------------
70271  * [0] | R | 0x0 | ALT_EMAC_DMA_OP_MOD_RSVD_0
70272  * [1] | RW | 0x0 | ALT_EMAC_DMA_OP_MOD_SR
70273  * [2] | RW | 0x0 | ALT_EMAC_DMA_OP_MOD_OSF
70274  * [4:3] | RW | 0x0 | ALT_EMAC_DMA_OP_MOD_RTC
70275  * [5] | RW | 0x0 | ALT_EMAC_DMA_OP_MOD_DGF
70276  * [6] | RW | 0x0 | ALT_EMAC_DMA_OP_MOD_FUF
70277  * [7] | RW | 0x0 | ALT_EMAC_DMA_OP_MOD_FEF
70278  * [8] | R | 0x0 | ALT_EMAC_DMA_OP_MOD_EFC
70279  * [10:9] | R | 0x0 | ALT_EMAC_DMA_OP_MOD_RFA
70280  * [12:11] | R | 0x0 | ALT_EMAC_DMA_OP_MOD_RFD
70281  * [13] | RW | 0x0 | ALT_EMAC_DMA_OP_MOD_ST
70282  * [16:14] | RW | 0x0 | ALT_EMAC_DMA_OP_MOD_TTC
70283  * [19:17] | R | 0x0 | ALT_EMAC_DMA_OP_MOD_RSVD_19_17
70284  * [20] | RW | 0x0 | ALT_EMAC_DMA_OP_MOD_FTF
70285  * [21] | RW | 0x0 | ALT_EMAC_DMA_OP_MOD_TSF
70286  * [22] | R | 0x0 | ALT_EMAC_DMA_OP_MOD_RFD_2
70287  * [23] | R | 0x0 | ALT_EMAC_DMA_OP_MOD_RFA_2
70288  * [24] | RW | 0x0 | ALT_EMAC_DMA_OP_MOD_DFF
70289  * [25] | RW | 0x0 | ALT_EMAC_DMA_OP_MOD_RSF
70290  * [26] | RW | 0x0 | ALT_EMAC_DMA_OP_MOD_DT
70291  * [31:27] | R | 0x0 | ALT_EMAC_DMA_OP_MOD_RSVD_31_27
70292  *
70293  */
70294 /*
70295  * Field : reserved_0
70296  *
70297  * Reserved
70298  *
70299  * Field Access Macros:
70300  *
70301  */
70302 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RSVD_0 register field. */
70303 #define ALT_EMAC_DMA_OP_MOD_RSVD_0_LSB 0
70304 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RSVD_0 register field. */
70305 #define ALT_EMAC_DMA_OP_MOD_RSVD_0_MSB 0
70306 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_RSVD_0 register field. */
70307 #define ALT_EMAC_DMA_OP_MOD_RSVD_0_WIDTH 1
70308 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_RSVD_0 register field value. */
70309 #define ALT_EMAC_DMA_OP_MOD_RSVD_0_SET_MSK 0x00000001
70310 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_RSVD_0 register field value. */
70311 #define ALT_EMAC_DMA_OP_MOD_RSVD_0_CLR_MSK 0xfffffffe
70312 /* The reset value of the ALT_EMAC_DMA_OP_MOD_RSVD_0 register field. */
70313 #define ALT_EMAC_DMA_OP_MOD_RSVD_0_RESET 0x0
70314 /* Extracts the ALT_EMAC_DMA_OP_MOD_RSVD_0 field value from a register. */
70315 #define ALT_EMAC_DMA_OP_MOD_RSVD_0_GET(value) (((value) & 0x00000001) >> 0)
70316 /* Produces a ALT_EMAC_DMA_OP_MOD_RSVD_0 register field value suitable for setting the register. */
70317 #define ALT_EMAC_DMA_OP_MOD_RSVD_0_SET(value) (((value) << 0) & 0x00000001)
70318 
70319 /*
70320  * Field : sr
70321  *
70322  * Start or Stop Receive
70323  *
70324  * When this bit is set, the Receive process is placed in the Running state. The
70325  * DMA attempts to acquire the descriptor from the Receive list and processes the
70326  * incoming frames. The descriptor acquisition is attempted from the current
70327  * position in the list, which is the address set by Register 3 (Receive Descriptor
70328  * List Address Register) or the position retained when the Receive process was
70329  * previously stopped. If the DMA does not own the descriptor, reception is
70330  * suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register)
70331  * is set. The Start Receive command is effective only when the reception has
70332  * stopped. If the command is issued before setting Register 3 (Receive Descriptor
70333  * List Address Register), the DMA behavior is unpredictable.
70334  *
70335  * When this bit is cleared, the Rx DMA operation is stopped after the transfer of
70336  * the current frame. The next descriptor position in the Receive list is saved and
70337  * becomes the current position after the Receive process is restarted. The Stop
70338  * Receive command is effective only when the Receive process is in either the
70339  * Running (waiting for receive packet) or in the Suspended state.
70340  *
70341  * Field Enumeration Values:
70342  *
70343  * Enum | Value | Description
70344  * :------------------------------|:------|:------------
70345  * ALT_EMAC_DMA_OP_MOD_SR_E_DISD | 0x0 |
70346  * ALT_EMAC_DMA_OP_MOD_SR_E_END | 0x1 |
70347  *
70348  * Field Access Macros:
70349  *
70350  */
70351 /*
70352  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_SR
70353  *
70354  */
70355 #define ALT_EMAC_DMA_OP_MOD_SR_E_DISD 0x0
70356 /*
70357  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_SR
70358  *
70359  */
70360 #define ALT_EMAC_DMA_OP_MOD_SR_E_END 0x1
70361 
70362 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_SR register field. */
70363 #define ALT_EMAC_DMA_OP_MOD_SR_LSB 1
70364 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_SR register field. */
70365 #define ALT_EMAC_DMA_OP_MOD_SR_MSB 1
70366 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_SR register field. */
70367 #define ALT_EMAC_DMA_OP_MOD_SR_WIDTH 1
70368 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_SR register field value. */
70369 #define ALT_EMAC_DMA_OP_MOD_SR_SET_MSK 0x00000002
70370 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_SR register field value. */
70371 #define ALT_EMAC_DMA_OP_MOD_SR_CLR_MSK 0xfffffffd
70372 /* The reset value of the ALT_EMAC_DMA_OP_MOD_SR register field. */
70373 #define ALT_EMAC_DMA_OP_MOD_SR_RESET 0x0
70374 /* Extracts the ALT_EMAC_DMA_OP_MOD_SR field value from a register. */
70375 #define ALT_EMAC_DMA_OP_MOD_SR_GET(value) (((value) & 0x00000002) >> 1)
70376 /* Produces a ALT_EMAC_DMA_OP_MOD_SR register field value suitable for setting the register. */
70377 #define ALT_EMAC_DMA_OP_MOD_SR_SET(value) (((value) << 1) & 0x00000002)
70378 
70379 /*
70380  * Field : osf
70381  *
70382  * Operate on Second Frame
70383  *
70384  * When this bit is set, it instructs the DMA to process the second frame of the
70385  * Transmit data even before the status for the first frame is obtained.
70386  *
70387  * Field Enumeration Values:
70388  *
70389  * Enum | Value | Description
70390  * :-------------------------------|:------|:------------
70391  * ALT_EMAC_DMA_OP_MOD_OSF_E_DISD | 0x0 |
70392  * ALT_EMAC_DMA_OP_MOD_OSF_E_END | 0x1 |
70393  *
70394  * Field Access Macros:
70395  *
70396  */
70397 /*
70398  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_OSF
70399  *
70400  */
70401 #define ALT_EMAC_DMA_OP_MOD_OSF_E_DISD 0x0
70402 /*
70403  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_OSF
70404  *
70405  */
70406 #define ALT_EMAC_DMA_OP_MOD_OSF_E_END 0x1
70407 
70408 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_OSF register field. */
70409 #define ALT_EMAC_DMA_OP_MOD_OSF_LSB 2
70410 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_OSF register field. */
70411 #define ALT_EMAC_DMA_OP_MOD_OSF_MSB 2
70412 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_OSF register field. */
70413 #define ALT_EMAC_DMA_OP_MOD_OSF_WIDTH 1
70414 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_OSF register field value. */
70415 #define ALT_EMAC_DMA_OP_MOD_OSF_SET_MSK 0x00000004
70416 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_OSF register field value. */
70417 #define ALT_EMAC_DMA_OP_MOD_OSF_CLR_MSK 0xfffffffb
70418 /* The reset value of the ALT_EMAC_DMA_OP_MOD_OSF register field. */
70419 #define ALT_EMAC_DMA_OP_MOD_OSF_RESET 0x0
70420 /* Extracts the ALT_EMAC_DMA_OP_MOD_OSF field value from a register. */
70421 #define ALT_EMAC_DMA_OP_MOD_OSF_GET(value) (((value) & 0x00000004) >> 2)
70422 /* Produces a ALT_EMAC_DMA_OP_MOD_OSF register field value suitable for setting the register. */
70423 #define ALT_EMAC_DMA_OP_MOD_OSF_SET(value) (((value) << 2) & 0x00000004)
70424 
70425 /*
70426  * Field : rtc
70427  *
70428  * Receive Threshold Control
70429  *
70430  * These two bits control the threshold level of the MTL Receive FIFO. Transfer
70431  * (request) to DMA starts when the frame size within the MTL Receive FIFO is
70432  * larger than the threshold. In addition, full frames with length less than the
70433  * threshold are transferred automatically.
70434  *
70435  * The value of 11 is not applicable if the configured Receive FIFO size is 128
70436  * bytes. These bits are valid only when the RSF bit is zero, and are ignored when
70437  * the RSF bit is set to 1.
70438  *
70439  * * 00: 64
70440  *
70441  * * 01: 32
70442  *
70443  * * 10: 96
70444  *
70445  * * 11: 128
70446  *
70447  * Field Enumeration Values:
70448  *
70449  * Enum | Value | Description
70450  * :-------------------------------------|:------|:------------
70451  * ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO64 | 0x0 |
70452  * ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO32 | 0x1 |
70453  * ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO96 | 0x2 |
70454  * ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO128 | 0x3 |
70455  *
70456  * Field Access Macros:
70457  *
70458  */
70459 /*
70460  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC
70461  *
70462  */
70463 #define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO64 0x0
70464 /*
70465  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC
70466  *
70467  */
70468 #define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO32 0x1
70469 /*
70470  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC
70471  *
70472  */
70473 #define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO96 0x2
70474 /*
70475  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC
70476  *
70477  */
70478 #define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO128 0x3
70479 
70480 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RTC register field. */
70481 #define ALT_EMAC_DMA_OP_MOD_RTC_LSB 3
70482 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RTC register field. */
70483 #define ALT_EMAC_DMA_OP_MOD_RTC_MSB 4
70484 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_RTC register field. */
70485 #define ALT_EMAC_DMA_OP_MOD_RTC_WIDTH 2
70486 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_RTC register field value. */
70487 #define ALT_EMAC_DMA_OP_MOD_RTC_SET_MSK 0x00000018
70488 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_RTC register field value. */
70489 #define ALT_EMAC_DMA_OP_MOD_RTC_CLR_MSK 0xffffffe7
70490 /* The reset value of the ALT_EMAC_DMA_OP_MOD_RTC register field. */
70491 #define ALT_EMAC_DMA_OP_MOD_RTC_RESET 0x0
70492 /* Extracts the ALT_EMAC_DMA_OP_MOD_RTC field value from a register. */
70493 #define ALT_EMAC_DMA_OP_MOD_RTC_GET(value) (((value) & 0x00000018) >> 3)
70494 /* Produces a ALT_EMAC_DMA_OP_MOD_RTC register field value suitable for setting the register. */
70495 #define ALT_EMAC_DMA_OP_MOD_RTC_SET(value) (((value) << 3) & 0x00000018)
70496 
70497 /*
70498  * Field : dgf
70499  *
70500  * Drop Giant Frames
70501  *
70502  * When set, the MAC drops the received giant frames in the Rx FIFO, that is,
70503  * frames that are larger than the computed giant frame limit. When reset, the MAC
70504  * does not drop the giant frames in the Rx FIFO.
70505  *
70506  * Note: This bit is available in the following configurations in which the giant
70507  * frame status is not provided in Rx status and giant frames are not dropped by
70508  * default:
70509  *
70510  * * Configurations in which IP Checksum Offload (Type 1) is selected in Rx
70511  *
70512  * * Configurations in which the IPC Full Checksum Offload Engine (Type 2) is
70513  * selected in Rx with normal descriptor format
70514  *
70515  * * Configurations in which the Advanced Timestamp feature is selected
70516  *
70517  * In all other configurations, this bit is not used (reserved and always reset).
70518  *
70519  * Field Access Macros:
70520  *
70521  */
70522 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_DGF register field. */
70523 #define ALT_EMAC_DMA_OP_MOD_DGF_LSB 5
70524 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_DGF register field. */
70525 #define ALT_EMAC_DMA_OP_MOD_DGF_MSB 5
70526 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_DGF register field. */
70527 #define ALT_EMAC_DMA_OP_MOD_DGF_WIDTH 1
70528 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_DGF register field value. */
70529 #define ALT_EMAC_DMA_OP_MOD_DGF_SET_MSK 0x00000020
70530 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_DGF register field value. */
70531 #define ALT_EMAC_DMA_OP_MOD_DGF_CLR_MSK 0xffffffdf
70532 /* The reset value of the ALT_EMAC_DMA_OP_MOD_DGF register field. */
70533 #define ALT_EMAC_DMA_OP_MOD_DGF_RESET 0x0
70534 /* Extracts the ALT_EMAC_DMA_OP_MOD_DGF field value from a register. */
70535 #define ALT_EMAC_DMA_OP_MOD_DGF_GET(value) (((value) & 0x00000020) >> 5)
70536 /* Produces a ALT_EMAC_DMA_OP_MOD_DGF register field value suitable for setting the register. */
70537 #define ALT_EMAC_DMA_OP_MOD_DGF_SET(value) (((value) << 5) & 0x00000020)
70538 
70539 /*
70540  * Field : fuf
70541  *
70542  * Forward Undersized Good Frames
70543  *
70544  * When set, the Rx FIFO forwards Undersized frames (frames with no Error and
70545  * length less than 64 bytes) including pad-bytes and CRC.
70546  *
70547  * When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame
70548  * is already transferred because of the lower value of Receive Threshold, for
70549  * example, RTC = 01.
70550  *
70551  * Field Enumeration Values:
70552  *
70553  * Enum | Value | Description
70554  * :-------------------------------|:------|:------------
70555  * ALT_EMAC_DMA_OP_MOD_FUF_E_DISD | 0x0 |
70556  * ALT_EMAC_DMA_OP_MOD_FUF_E_END | 0x1 |
70557  *
70558  * Field Access Macros:
70559  *
70560  */
70561 /*
70562  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FUF
70563  *
70564  */
70565 #define ALT_EMAC_DMA_OP_MOD_FUF_E_DISD 0x0
70566 /*
70567  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FUF
70568  *
70569  */
70570 #define ALT_EMAC_DMA_OP_MOD_FUF_E_END 0x1
70571 
70572 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_FUF register field. */
70573 #define ALT_EMAC_DMA_OP_MOD_FUF_LSB 6
70574 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_FUF register field. */
70575 #define ALT_EMAC_DMA_OP_MOD_FUF_MSB 6
70576 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_FUF register field. */
70577 #define ALT_EMAC_DMA_OP_MOD_FUF_WIDTH 1
70578 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_FUF register field value. */
70579 #define ALT_EMAC_DMA_OP_MOD_FUF_SET_MSK 0x00000040
70580 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_FUF register field value. */
70581 #define ALT_EMAC_DMA_OP_MOD_FUF_CLR_MSK 0xffffffbf
70582 /* The reset value of the ALT_EMAC_DMA_OP_MOD_FUF register field. */
70583 #define ALT_EMAC_DMA_OP_MOD_FUF_RESET 0x0
70584 /* Extracts the ALT_EMAC_DMA_OP_MOD_FUF field value from a register. */
70585 #define ALT_EMAC_DMA_OP_MOD_FUF_GET(value) (((value) & 0x00000040) >> 6)
70586 /* Produces a ALT_EMAC_DMA_OP_MOD_FUF register field value suitable for setting the register. */
70587 #define ALT_EMAC_DMA_OP_MOD_FUF_SET(value) (((value) << 6) & 0x00000040)
70588 
70589 /*
70590  * Field : fef
70591  *
70592  * Forward Error Frames
70593  *
70594  * When this bit is reset, the Rx FIFO drops frames with error status (CRC error,
70595  * collision error, GMII_ER, giant frame, watchdog timeout, or overflow). However,
70596  * if the start byte (write) pointer of a frame is already transferred to the read
70597  * controller side (in Threshold mode), then the frame is not dropped.
70598  *
70599  * In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled
70600  * during core configuration, the Rx FIFO drops the error frames if that frame's
70601  * start byte is not transferred (output) on the ARI bus.
70602  *
70603  * When the FEF bit is set, all frames except runt error frames are forwarded to
70604  * the DMA. If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial
70605  * frame is written, then the frame is dropped irrespective of the FEF bit setting.
70606  * However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial
70607  * frame is
70608  *
70609  * written, then a partial frame may be forwarded to the DMA.
70610  *
70611  * Note: When FEF bit is reset, the giant frames are dropped if the giant frame
70612  * status is given in Rx Status in the following configurations:
70613  *
70614  * * The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are
70615  * not selected.
70616  *
70617  * * The advanced timestamp feature is not selected but the extended status is
70618  * selected. The extended status is available with the following features:
70619  *
70620  * - L3-L4 filter in GMAC-CORE or GMAC-MTL configurations
70621  *
70622  * - Full checksum offload engine (Type 2) with enhanced descriptor format in
70623  * the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations.
70624  *
70625  * Field Enumeration Values:
70626  *
70627  * Enum | Value | Description
70628  * :-------------------------------|:------|:------------
70629  * ALT_EMAC_DMA_OP_MOD_FEF_E_DISD | 0x0 |
70630  * ALT_EMAC_DMA_OP_MOD_FEF_E_END | 0x1 |
70631  *
70632  * Field Access Macros:
70633  *
70634  */
70635 /*
70636  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FEF
70637  *
70638  */
70639 #define ALT_EMAC_DMA_OP_MOD_FEF_E_DISD 0x0
70640 /*
70641  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FEF
70642  *
70643  */
70644 #define ALT_EMAC_DMA_OP_MOD_FEF_E_END 0x1
70645 
70646 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_FEF register field. */
70647 #define ALT_EMAC_DMA_OP_MOD_FEF_LSB 7
70648 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_FEF register field. */
70649 #define ALT_EMAC_DMA_OP_MOD_FEF_MSB 7
70650 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_FEF register field. */
70651 #define ALT_EMAC_DMA_OP_MOD_FEF_WIDTH 1
70652 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_FEF register field value. */
70653 #define ALT_EMAC_DMA_OP_MOD_FEF_SET_MSK 0x00000080
70654 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_FEF register field value. */
70655 #define ALT_EMAC_DMA_OP_MOD_FEF_CLR_MSK 0xffffff7f
70656 /* The reset value of the ALT_EMAC_DMA_OP_MOD_FEF register field. */
70657 #define ALT_EMAC_DMA_OP_MOD_FEF_RESET 0x0
70658 /* Extracts the ALT_EMAC_DMA_OP_MOD_FEF field value from a register. */
70659 #define ALT_EMAC_DMA_OP_MOD_FEF_GET(value) (((value) & 0x00000080) >> 7)
70660 /* Produces a ALT_EMAC_DMA_OP_MOD_FEF register field value suitable for setting the register. */
70661 #define ALT_EMAC_DMA_OP_MOD_FEF_SET(value) (((value) << 7) & 0x00000080)
70662 
70663 /*
70664  * Field : efc
70665  *
70666  * Reserved
70667  *
70668  * Field Enumeration Values:
70669  *
70670  * Enum | Value | Description
70671  * :-------------------------------|:------|:------------
70672  * ALT_EMAC_DMA_OP_MOD_EFC_E_DISD | 0x0 |
70673  * ALT_EMAC_DMA_OP_MOD_EFC_E_END | 0x1 |
70674  *
70675  * Field Access Macros:
70676  *
70677  */
70678 /*
70679  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_EFC
70680  *
70681  */
70682 #define ALT_EMAC_DMA_OP_MOD_EFC_E_DISD 0x0
70683 /*
70684  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_EFC
70685  *
70686  */
70687 #define ALT_EMAC_DMA_OP_MOD_EFC_E_END 0x1
70688 
70689 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_EFC register field. */
70690 #define ALT_EMAC_DMA_OP_MOD_EFC_LSB 8
70691 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_EFC register field. */
70692 #define ALT_EMAC_DMA_OP_MOD_EFC_MSB 8
70693 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_EFC register field. */
70694 #define ALT_EMAC_DMA_OP_MOD_EFC_WIDTH 1
70695 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_EFC register field value. */
70696 #define ALT_EMAC_DMA_OP_MOD_EFC_SET_MSK 0x00000100
70697 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_EFC register field value. */
70698 #define ALT_EMAC_DMA_OP_MOD_EFC_CLR_MSK 0xfffffeff
70699 /* The reset value of the ALT_EMAC_DMA_OP_MOD_EFC register field. */
70700 #define ALT_EMAC_DMA_OP_MOD_EFC_RESET 0x0
70701 /* Extracts the ALT_EMAC_DMA_OP_MOD_EFC field value from a register. */
70702 #define ALT_EMAC_DMA_OP_MOD_EFC_GET(value) (((value) & 0x00000100) >> 8)
70703 /* Produces a ALT_EMAC_DMA_OP_MOD_EFC register field value suitable for setting the register. */
70704 #define ALT_EMAC_DMA_OP_MOD_EFC_SET(value) (((value) << 8) & 0x00000100)
70705 
70706 /*
70707  * Field : rfa
70708  *
70709  * Threshold for Activating Flow Control (in half-duplex and full-duplex)
70710  *
70711  * These bits control the threshold (Fill level of Rx FIFO) at which the flow
70712  * control is activated.
70713  *
70714  * * 00: Full minus 1 KB, that is, FULL - 1KB
70715  *
70716  * * 01: Full minus 2 KB, that is, FULL - 2KB
70717  *
70718  * * 10: Full minus 3 KB, that is, FULL - 3KB
70719  *
70720  * * 11: Full minus 4 KB, that is, FULL - 4KB
70721  *
70722  * These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8
70723  * (EFC) is set high. If the Rx FIFO is 8 KB or more, an additional Bit (RFA_2) is
70724  * used for more threshold levels as described in Bit 23. These bits are reserved
70725  * and read-only when the depth of Rx FIFO is less than 4 KB.
70726  *
70727  * Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to
70728  * program the value of these bits to 11, the software should not program these
70729  * bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition.
70730  *
70731  * Field Enumeration Values:
70732  *
70733  * Enum | Value | Description
70734  * :--------------------------------------|:------|:------------
70735  * ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_1K | 0x0 |
70736  * ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_2K | 0x1 |
70737  * ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_3K | 0x2 |
70738  * ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_4K | 0x3 |
70739  *
70740  * Field Access Macros:
70741  *
70742  */
70743 /*
70744  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA
70745  *
70746  */
70747 #define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_1K 0x0
70748 /*
70749  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA
70750  *
70751  */
70752 #define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_2K 0x1
70753 /*
70754  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA
70755  *
70756  */
70757 #define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_3K 0x2
70758 /*
70759  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA
70760  *
70761  */
70762 #define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_4K 0x3
70763 
70764 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RFA register field. */
70765 #define ALT_EMAC_DMA_OP_MOD_RFA_LSB 9
70766 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RFA register field. */
70767 #define ALT_EMAC_DMA_OP_MOD_RFA_MSB 10
70768 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_RFA register field. */
70769 #define ALT_EMAC_DMA_OP_MOD_RFA_WIDTH 2
70770 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_RFA register field value. */
70771 #define ALT_EMAC_DMA_OP_MOD_RFA_SET_MSK 0x00000600
70772 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_RFA register field value. */
70773 #define ALT_EMAC_DMA_OP_MOD_RFA_CLR_MSK 0xfffff9ff
70774 /* The reset value of the ALT_EMAC_DMA_OP_MOD_RFA register field. */
70775 #define ALT_EMAC_DMA_OP_MOD_RFA_RESET 0x0
70776 /* Extracts the ALT_EMAC_DMA_OP_MOD_RFA field value from a register. */
70777 #define ALT_EMAC_DMA_OP_MOD_RFA_GET(value) (((value) & 0x00000600) >> 9)
70778 /* Produces a ALT_EMAC_DMA_OP_MOD_RFA register field value suitable for setting the register. */
70779 #define ALT_EMAC_DMA_OP_MOD_RFA_SET(value) (((value) << 9) & 0x00000600)
70780 
70781 /*
70782  * Field : rfd
70783  *
70784  * Threshold for Deactivating Flow Control (in half-duplex and full-duplex)
70785  *
70786  * These bits control the threshold (Fill-level of Rx FIFO) at which the flow
70787  * control is de-asserted after activation.
70788  *
70789  * * 00: Full minus 1 KB, that is, FULL - 1KB
70790  *
70791  * * 01: Full minus 2 KB, that is, FULL - 2KB
70792  *
70793  * * 10: Full minus 3 KB, that is, FULL - 3KB
70794  *
70795  * * 11: Full minus 4 KB, that is, FULL - 4KB
70796  *
70797  * The de-assertion is effective only after flow control is asserted. If the Rx
70798  * FIFO is 8 KB or more, an additional bit (RFD_2) is used for more threshold
70799  * levels as described in Bit 22. These bits are reserved and read-only when the Rx
70800  * FIFO depth is less than 4 KB.
70801  *
70802  * Note: For proper flow control, the value programmed in the "RFD_2, RFD" fields
70803  * should be equal to or more than the value programmed in the "RFA_2, RFA" fields.
70804  *
70805  * Field Enumeration Values:
70806  *
70807  * Enum | Value | Description
70808  * :--------------------------------------|:------|:------------
70809  * ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_1K | 0x0 |
70810  * ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_2K | 0x1 |
70811  * ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_3K | 0x2 |
70812  * ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_4K | 0x3 |
70813  *
70814  * Field Access Macros:
70815  *
70816  */
70817 /*
70818  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD
70819  *
70820  */
70821 #define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_1K 0x0
70822 /*
70823  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD
70824  *
70825  */
70826 #define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_2K 0x1
70827 /*
70828  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD
70829  *
70830  */
70831 #define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_3K 0x2
70832 /*
70833  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD
70834  *
70835  */
70836 #define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_4K 0x3
70837 
70838 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RFD register field. */
70839 #define ALT_EMAC_DMA_OP_MOD_RFD_LSB 11
70840 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RFD register field. */
70841 #define ALT_EMAC_DMA_OP_MOD_RFD_MSB 12
70842 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_RFD register field. */
70843 #define ALT_EMAC_DMA_OP_MOD_RFD_WIDTH 2
70844 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_RFD register field value. */
70845 #define ALT_EMAC_DMA_OP_MOD_RFD_SET_MSK 0x00001800
70846 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_RFD register field value. */
70847 #define ALT_EMAC_DMA_OP_MOD_RFD_CLR_MSK 0xffffe7ff
70848 /* The reset value of the ALT_EMAC_DMA_OP_MOD_RFD register field. */
70849 #define ALT_EMAC_DMA_OP_MOD_RFD_RESET 0x0
70850 /* Extracts the ALT_EMAC_DMA_OP_MOD_RFD field value from a register. */
70851 #define ALT_EMAC_DMA_OP_MOD_RFD_GET(value) (((value) & 0x00001800) >> 11)
70852 /* Produces a ALT_EMAC_DMA_OP_MOD_RFD register field value suitable for setting the register. */
70853 #define ALT_EMAC_DMA_OP_MOD_RFD_SET(value) (((value) << 11) & 0x00001800)
70854 
70855 /*
70856  * Field : st
70857  *
70858  * Start or Stop Transmission Command
70859  *
70860  * When this bit is set, transmission is placed in the Running state, and the DMA
70861  * checks the Transmit List at the current position for a frame to be transmitted.
70862  * Descriptor acquisition is attempted either from the current position in the
70863  * list, which is the Transmit List Base Address set by Register 4 (Transmit
70864  * Descriptor List Address Register), or from the position retained when
70865  * transmission was stopped previously. If the DMA does not own the current
70866  * descriptor, transmission enters the Suspended state and Bit 2 (Transmit Buffer
70867  * Unavailable) of Register 5 (Status Register) is set. The Start Transmission
70868  * command is effective only when transmission is stopped. If the command is issued
70869  * before setting Register 4 (Transmit Descriptor List Address Register), then the
70870  * DMA behavior is unpredictable.
70871  *
70872  * When this bit is reset, the transmission process is placed in the Stopped state
70873  * after completing the transmission of the current frame. The Next Descriptor
70874  * position in the Transmit List is saved, and it becomes the current position when
70875  * transmission is restarted. To change the list address, you need to program
70876  * Register 4 (Transmit Descriptor List Address Register) with a new value when
70877  * this bit is reset. The new value is considered when this bit is set again. The
70878  * stop transmission command is effective only when the transmission of the current
70879  * frame is complete or the transmission is in the Suspended state.
70880  *
70881  * Field Enumeration Values:
70882  *
70883  * Enum | Value | Description
70884  * :------------------------------|:------|:------------
70885  * ALT_EMAC_DMA_OP_MOD_ST_E_DISD | 0x0 |
70886  * ALT_EMAC_DMA_OP_MOD_ST_E_END | 0x1 |
70887  *
70888  * Field Access Macros:
70889  *
70890  */
70891 /*
70892  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_ST
70893  *
70894  */
70895 #define ALT_EMAC_DMA_OP_MOD_ST_E_DISD 0x0
70896 /*
70897  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_ST
70898  *
70899  */
70900 #define ALT_EMAC_DMA_OP_MOD_ST_E_END 0x1
70901 
70902 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_ST register field. */
70903 #define ALT_EMAC_DMA_OP_MOD_ST_LSB 13
70904 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_ST register field. */
70905 #define ALT_EMAC_DMA_OP_MOD_ST_MSB 13
70906 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_ST register field. */
70907 #define ALT_EMAC_DMA_OP_MOD_ST_WIDTH 1
70908 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_ST register field value. */
70909 #define ALT_EMAC_DMA_OP_MOD_ST_SET_MSK 0x00002000
70910 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_ST register field value. */
70911 #define ALT_EMAC_DMA_OP_MOD_ST_CLR_MSK 0xffffdfff
70912 /* The reset value of the ALT_EMAC_DMA_OP_MOD_ST register field. */
70913 #define ALT_EMAC_DMA_OP_MOD_ST_RESET 0x0
70914 /* Extracts the ALT_EMAC_DMA_OP_MOD_ST field value from a register. */
70915 #define ALT_EMAC_DMA_OP_MOD_ST_GET(value) (((value) & 0x00002000) >> 13)
70916 /* Produces a ALT_EMAC_DMA_OP_MOD_ST register field value suitable for setting the register. */
70917 #define ALT_EMAC_DMA_OP_MOD_ST_SET(value) (((value) << 13) & 0x00002000)
70918 
70919 /*
70920  * Field : ttc
70921  *
70922  * Transmit Threshold Control
70923  *
70924  * These bits control the threshold level of the MTL Transmit FIFO. Transmission
70925  * starts when the frame size within the MTL Transmit FIFO is larger than the
70926  * threshold. In addition, full frames with a length less than the threshold are
70927  * also transmitted. These bits are used only when Bit 21 (TSF) is reset.
70928  *
70929  * * 000: 64
70930  *
70931  * * 001: 128
70932  *
70933  * * 010: 192
70934  *
70935  * * 011: 256
70936  *
70937  * * 100: 40
70938  *
70939  * * 101: 32
70940  *
70941  * * 110: 24
70942  *
70943  * * 111: 16
70944  *
70945  * Field Enumeration Values:
70946  *
70947  * Enum | Value | Description
70948  * :--------------------------------------|:------|:------------
70949  * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHESH64 | 0x0 |
70950  * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES128 | 0x1 |
70951  * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES192 | 0x2 |
70952  * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES256 | 0x3 |
70953  * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES40 | 0x4 |
70954  * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES32 | 0x5 |
70955  * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES24 | 0x6 |
70956  * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES16 | 0x7 |
70957  *
70958  * Field Access Macros:
70959  *
70960  */
70961 /*
70962  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
70963  *
70964  */
70965 #define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHESH64 0x0
70966 /*
70967  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
70968  *
70969  */
70970 #define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES128 0x1
70971 /*
70972  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
70973  *
70974  */
70975 #define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES192 0x2
70976 /*
70977  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
70978  *
70979  */
70980 #define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES256 0x3
70981 /*
70982  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
70983  *
70984  */
70985 #define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES40 0x4
70986 /*
70987  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
70988  *
70989  */
70990 #define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES32 0x5
70991 /*
70992  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
70993  *
70994  */
70995 #define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES24 0x6
70996 /*
70997  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
70998  *
70999  */
71000 #define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES16 0x7
71001 
71002 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_TTC register field. */
71003 #define ALT_EMAC_DMA_OP_MOD_TTC_LSB 14
71004 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_TTC register field. */
71005 #define ALT_EMAC_DMA_OP_MOD_TTC_MSB 16
71006 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_TTC register field. */
71007 #define ALT_EMAC_DMA_OP_MOD_TTC_WIDTH 3
71008 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_TTC register field value. */
71009 #define ALT_EMAC_DMA_OP_MOD_TTC_SET_MSK 0x0001c000
71010 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_TTC register field value. */
71011 #define ALT_EMAC_DMA_OP_MOD_TTC_CLR_MSK 0xfffe3fff
71012 /* The reset value of the ALT_EMAC_DMA_OP_MOD_TTC register field. */
71013 #define ALT_EMAC_DMA_OP_MOD_TTC_RESET 0x0
71014 /* Extracts the ALT_EMAC_DMA_OP_MOD_TTC field value from a register. */
71015 #define ALT_EMAC_DMA_OP_MOD_TTC_GET(value) (((value) & 0x0001c000) >> 14)
71016 /* Produces a ALT_EMAC_DMA_OP_MOD_TTC register field value suitable for setting the register. */
71017 #define ALT_EMAC_DMA_OP_MOD_TTC_SET(value) (((value) << 14) & 0x0001c000)
71018 
71019 /*
71020  * Field : reserved_19_17
71021  *
71022  * Reserved
71023  *
71024  * Field Access Macros:
71025  *
71026  */
71027 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RSVD_19_17 register field. */
71028 #define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_LSB 17
71029 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RSVD_19_17 register field. */
71030 #define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_MSB 19
71031 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_RSVD_19_17 register field. */
71032 #define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_WIDTH 3
71033 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_RSVD_19_17 register field value. */
71034 #define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_SET_MSK 0x000e0000
71035 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_RSVD_19_17 register field value. */
71036 #define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_CLR_MSK 0xfff1ffff
71037 /* The reset value of the ALT_EMAC_DMA_OP_MOD_RSVD_19_17 register field. */
71038 #define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_RESET 0x0
71039 /* Extracts the ALT_EMAC_DMA_OP_MOD_RSVD_19_17 field value from a register. */
71040 #define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_GET(value) (((value) & 0x000e0000) >> 17)
71041 /* Produces a ALT_EMAC_DMA_OP_MOD_RSVD_19_17 register field value suitable for setting the register. */
71042 #define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_SET(value) (((value) << 17) & 0x000e0000)
71043 
71044 /*
71045  * Field : ftf
71046  *
71047  * Flush Transmit FIFO
71048  *
71049  * When this bit is set, the transmit FIFO controller logic is reset to its default
71050  * values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared
71051  * internally when the flushing operation is completed. The Operation Mode register
71052  * should not be written to until this bit is cleared. The data which is already
71053  * accepted by the MAC transmitter is not flushed. It is scheduled for transmission
71054  * and results in underflow and runt frame transmission.
71055  *
71056  * Note: The flush operation is complete only when the Tx FIFO is emptied of its
71057  * contents and all the pending Transmit Status of the transmitted frames are
71058  * accepted by the host. To complete this flush operation, the PHY transmit clock
71059  * (clk_tx_i) is required to be active.
71060  *
71061  * Field Enumeration Values:
71062  *
71063  * Enum | Value | Description
71064  * :-------------------------------|:------|:------------
71065  * ALT_EMAC_DMA_OP_MOD_FTF_E_DISD | 0x0 |
71066  * ALT_EMAC_DMA_OP_MOD_FTF_E_END | 0x1 |
71067  *
71068  * Field Access Macros:
71069  *
71070  */
71071 /*
71072  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FTF
71073  *
71074  */
71075 #define ALT_EMAC_DMA_OP_MOD_FTF_E_DISD 0x0
71076 /*
71077  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FTF
71078  *
71079  */
71080 #define ALT_EMAC_DMA_OP_MOD_FTF_E_END 0x1
71081 
71082 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_FTF register field. */
71083 #define ALT_EMAC_DMA_OP_MOD_FTF_LSB 20
71084 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_FTF register field. */
71085 #define ALT_EMAC_DMA_OP_MOD_FTF_MSB 20
71086 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_FTF register field. */
71087 #define ALT_EMAC_DMA_OP_MOD_FTF_WIDTH 1
71088 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_FTF register field value. */
71089 #define ALT_EMAC_DMA_OP_MOD_FTF_SET_MSK 0x00100000
71090 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_FTF register field value. */
71091 #define ALT_EMAC_DMA_OP_MOD_FTF_CLR_MSK 0xffefffff
71092 /* The reset value of the ALT_EMAC_DMA_OP_MOD_FTF register field. */
71093 #define ALT_EMAC_DMA_OP_MOD_FTF_RESET 0x0
71094 /* Extracts the ALT_EMAC_DMA_OP_MOD_FTF field value from a register. */
71095 #define ALT_EMAC_DMA_OP_MOD_FTF_GET(value) (((value) & 0x00100000) >> 20)
71096 /* Produces a ALT_EMAC_DMA_OP_MOD_FTF register field value suitable for setting the register. */
71097 #define ALT_EMAC_DMA_OP_MOD_FTF_SET(value) (((value) << 20) & 0x00100000)
71098 
71099 /*
71100  * Field : tsf
71101  *
71102  * Transmit Store and Forward
71103  *
71104  * When this bit is set, transmission starts when a full frame resides in the MTL
71105  * Transmit FIFO. When this bit is set, the TTC values specified in Bits[16:14] are
71106  * ignored. This bit should be changed only when the transmission is stopped.
71107  *
71108  * Field Enumeration Values:
71109  *
71110  * Enum | Value | Description
71111  * :-------------------------------|:------|:------------
71112  * ALT_EMAC_DMA_OP_MOD_TSF_E_DISD | 0x0 |
71113  * ALT_EMAC_DMA_OP_MOD_TSF_E_END | 0x1 |
71114  *
71115  * Field Access Macros:
71116  *
71117  */
71118 /*
71119  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TSF
71120  *
71121  */
71122 #define ALT_EMAC_DMA_OP_MOD_TSF_E_DISD 0x0
71123 /*
71124  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TSF
71125  *
71126  */
71127 #define ALT_EMAC_DMA_OP_MOD_TSF_E_END 0x1
71128 
71129 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_TSF register field. */
71130 #define ALT_EMAC_DMA_OP_MOD_TSF_LSB 21
71131 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_TSF register field. */
71132 #define ALT_EMAC_DMA_OP_MOD_TSF_MSB 21
71133 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_TSF register field. */
71134 #define ALT_EMAC_DMA_OP_MOD_TSF_WIDTH 1
71135 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_TSF register field value. */
71136 #define ALT_EMAC_DMA_OP_MOD_TSF_SET_MSK 0x00200000
71137 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_TSF register field value. */
71138 #define ALT_EMAC_DMA_OP_MOD_TSF_CLR_MSK 0xffdfffff
71139 /* The reset value of the ALT_EMAC_DMA_OP_MOD_TSF register field. */
71140 #define ALT_EMAC_DMA_OP_MOD_TSF_RESET 0x0
71141 /* Extracts the ALT_EMAC_DMA_OP_MOD_TSF field value from a register. */
71142 #define ALT_EMAC_DMA_OP_MOD_TSF_GET(value) (((value) & 0x00200000) >> 21)
71143 /* Produces a ALT_EMAC_DMA_OP_MOD_TSF register field value suitable for setting the register. */
71144 #define ALT_EMAC_DMA_OP_MOD_TSF_SET(value) (((value) << 21) & 0x00200000)
71145 
71146 /*
71147  * Field : rfd_2
71148  *
71149  * MSB of Threshold for Deactivating Flow Control
71150  *
71151  * If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, this bit (when
71152  * set) provides additional threshold levels for deactivating the flow control in
71153  * both half-duplex and full-duplex modes. This bit (as Most Significant Bit) along
71154  * with the RFD (Bits[12:11]) gives the following thresholds for deactivating flow
71155  * control:
71156  *
71157  * * 100: Full minus 5 KB, that is, FULL - 5KB
71158  *
71159  * * 101: Full minus 6 KB, that is, FULL - 6KB
71160  *
71161  * * 110: Full minus 7 KB, that is, FULL - 7KB
71162  *
71163  * * 111: Reserved
71164  *
71165  * This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep.
71166  *
71167  * Field Access Macros:
71168  *
71169  */
71170 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RFD_2 register field. */
71171 #define ALT_EMAC_DMA_OP_MOD_RFD_2_LSB 22
71172 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RFD_2 register field. */
71173 #define ALT_EMAC_DMA_OP_MOD_RFD_2_MSB 22
71174 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_RFD_2 register field. */
71175 #define ALT_EMAC_DMA_OP_MOD_RFD_2_WIDTH 1
71176 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_RFD_2 register field value. */
71177 #define ALT_EMAC_DMA_OP_MOD_RFD_2_SET_MSK 0x00400000
71178 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_RFD_2 register field value. */
71179 #define ALT_EMAC_DMA_OP_MOD_RFD_2_CLR_MSK 0xffbfffff
71180 /* The reset value of the ALT_EMAC_DMA_OP_MOD_RFD_2 register field. */
71181 #define ALT_EMAC_DMA_OP_MOD_RFD_2_RESET 0x0
71182 /* Extracts the ALT_EMAC_DMA_OP_MOD_RFD_2 field value from a register. */
71183 #define ALT_EMAC_DMA_OP_MOD_RFD_2_GET(value) (((value) & 0x00400000) >> 22)
71184 /* Produces a ALT_EMAC_DMA_OP_MOD_RFD_2 register field value suitable for setting the register. */
71185 #define ALT_EMAC_DMA_OP_MOD_RFD_2_SET(value) (((value) << 22) & 0x00400000)
71186 
71187 /*
71188  * Field : rfa_2
71189  *
71190  * MSB of Threshold for Activating Flow Control
71191  *
71192  * If the DWC_gmac is configured for an Rx FIFO depth of 8 KB or more, this bit
71193  * (when set) provides additional threshold levels for activating the flow control
71194  * in both half-duplex and full-duplex modes. This bit (as Most Significant Bit)
71195  * along with the RFA (Bits[10:9]) gives the following thresholds for activating
71196  * flow control:
71197  *
71198  * * 100: Full minus 5 KB, that is, FULL - 5KB
71199  *
71200  * * 101: Full minus 6 KB, that is, FULL - 6KB
71201  *
71202  * * 110: Full minus 7 KB, that is, FULL - 7KB
71203  *
71204  * * 111: Reserved
71205  *
71206  * This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep.
71207  *
71208  * Field Access Macros:
71209  *
71210  */
71211 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RFA_2 register field. */
71212 #define ALT_EMAC_DMA_OP_MOD_RFA_2_LSB 23
71213 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RFA_2 register field. */
71214 #define ALT_EMAC_DMA_OP_MOD_RFA_2_MSB 23
71215 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_RFA_2 register field. */
71216 #define ALT_EMAC_DMA_OP_MOD_RFA_2_WIDTH 1
71217 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_RFA_2 register field value. */
71218 #define ALT_EMAC_DMA_OP_MOD_RFA_2_SET_MSK 0x00800000
71219 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_RFA_2 register field value. */
71220 #define ALT_EMAC_DMA_OP_MOD_RFA_2_CLR_MSK 0xff7fffff
71221 /* The reset value of the ALT_EMAC_DMA_OP_MOD_RFA_2 register field. */
71222 #define ALT_EMAC_DMA_OP_MOD_RFA_2_RESET 0x0
71223 /* Extracts the ALT_EMAC_DMA_OP_MOD_RFA_2 field value from a register. */
71224 #define ALT_EMAC_DMA_OP_MOD_RFA_2_GET(value) (((value) & 0x00800000) >> 23)
71225 /* Produces a ALT_EMAC_DMA_OP_MOD_RFA_2 register field value suitable for setting the register. */
71226 #define ALT_EMAC_DMA_OP_MOD_RFA_2_SET(value) (((value) << 23) & 0x00800000)
71227 
71228 /*
71229  * Field : dff
71230  *
71231  * Disable Flushing of Received Frames
71232  *
71233  * When this bit is set, the Rx DMA does not flush any frames because of the
71234  * unavailability of receive descriptors or buffers as it does normally when this
71235  * bit is reset.
71236  *
71237  * This bit is reserved (and RO) in the GMAC-MTL configuration.
71238  *
71239  * Field Enumeration Values:
71240  *
71241  * Enum | Value | Description
71242  * :-------------------------------|:------|:------------
71243  * ALT_EMAC_DMA_OP_MOD_DFF_E_DISD | 0x0 |
71244  * ALT_EMAC_DMA_OP_MOD_DFF_E_END | 0x1 |
71245  *
71246  * Field Access Macros:
71247  *
71248  */
71249 /*
71250  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DFF
71251  *
71252  */
71253 #define ALT_EMAC_DMA_OP_MOD_DFF_E_DISD 0x0
71254 /*
71255  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DFF
71256  *
71257  */
71258 #define ALT_EMAC_DMA_OP_MOD_DFF_E_END 0x1
71259 
71260 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_DFF register field. */
71261 #define ALT_EMAC_DMA_OP_MOD_DFF_LSB 24
71262 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_DFF register field. */
71263 #define ALT_EMAC_DMA_OP_MOD_DFF_MSB 24
71264 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_DFF register field. */
71265 #define ALT_EMAC_DMA_OP_MOD_DFF_WIDTH 1
71266 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_DFF register field value. */
71267 #define ALT_EMAC_DMA_OP_MOD_DFF_SET_MSK 0x01000000
71268 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_DFF register field value. */
71269 #define ALT_EMAC_DMA_OP_MOD_DFF_CLR_MSK 0xfeffffff
71270 /* The reset value of the ALT_EMAC_DMA_OP_MOD_DFF register field. */
71271 #define ALT_EMAC_DMA_OP_MOD_DFF_RESET 0x0
71272 /* Extracts the ALT_EMAC_DMA_OP_MOD_DFF field value from a register. */
71273 #define ALT_EMAC_DMA_OP_MOD_DFF_GET(value) (((value) & 0x01000000) >> 24)
71274 /* Produces a ALT_EMAC_DMA_OP_MOD_DFF register field value suitable for setting the register. */
71275 #define ALT_EMAC_DMA_OP_MOD_DFF_SET(value) (((value) << 24) & 0x01000000)
71276 
71277 /*
71278  * Field : rsf
71279  *
71280  * Receive Store and Forward
71281  *
71282  * When this bit is set, the MTL reads a frame from the Rx FIFO only after the
71283  * complete frame has been written to it, ignoring the RTC bits. When this bit is
71284  * reset, the Rx FIFO operates in the cut-through mode, subject to the threshold
71285  * specified by the RTC bits.
71286  *
71287  * Field Enumeration Values:
71288  *
71289  * Enum | Value | Description
71290  * :-------------------------------|:------|:------------
71291  * ALT_EMAC_DMA_OP_MOD_RSF_E_DISD | 0x0 |
71292  * ALT_EMAC_DMA_OP_MOD_RSF_E_END | 0x1 |
71293  *
71294  * Field Access Macros:
71295  *
71296  */
71297 /*
71298  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RSF
71299  *
71300  */
71301 #define ALT_EMAC_DMA_OP_MOD_RSF_E_DISD 0x0
71302 /*
71303  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RSF
71304  *
71305  */
71306 #define ALT_EMAC_DMA_OP_MOD_RSF_E_END 0x1
71307 
71308 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RSF register field. */
71309 #define ALT_EMAC_DMA_OP_MOD_RSF_LSB 25
71310 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RSF register field. */
71311 #define ALT_EMAC_DMA_OP_MOD_RSF_MSB 25
71312 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_RSF register field. */
71313 #define ALT_EMAC_DMA_OP_MOD_RSF_WIDTH 1
71314 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_RSF register field value. */
71315 #define ALT_EMAC_DMA_OP_MOD_RSF_SET_MSK 0x02000000
71316 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_RSF register field value. */
71317 #define ALT_EMAC_DMA_OP_MOD_RSF_CLR_MSK 0xfdffffff
71318 /* The reset value of the ALT_EMAC_DMA_OP_MOD_RSF register field. */
71319 #define ALT_EMAC_DMA_OP_MOD_RSF_RESET 0x0
71320 /* Extracts the ALT_EMAC_DMA_OP_MOD_RSF field value from a register. */
71321 #define ALT_EMAC_DMA_OP_MOD_RSF_GET(value) (((value) & 0x02000000) >> 25)
71322 /* Produces a ALT_EMAC_DMA_OP_MOD_RSF register field value suitable for setting the register. */
71323 #define ALT_EMAC_DMA_OP_MOD_RSF_SET(value) (((value) << 25) & 0x02000000)
71324 
71325 /*
71326  * Field : dt
71327  *
71328  * Disable Dropping of TCP/IP Checksum Error Frames
71329  *
71330  * When this bit is set, the MAC does not drop the frames which only have errors
71331  * detected by the Receive Checksum Offload engine. Such frames do not have any
71332  * errors (including FCS error) in the Ethernet frame received by the MAC but have
71333  * errors only in the encapsulated payload. When this bit is reset, all error
71334  * frames are dropped if the FEF bit is reset.
71335  *
71336  * If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is
71337  * reserved (RO with value 1'b0).
71338  *
71339  * Field Enumeration Values:
71340  *
71341  * Enum | Value | Description
71342  * :------------------------------|:------|:------------
71343  * ALT_EMAC_DMA_OP_MOD_DT_E_DISD | 0x0 |
71344  * ALT_EMAC_DMA_OP_MOD_DT_E_END | 0x1 |
71345  *
71346  * Field Access Macros:
71347  *
71348  */
71349 /*
71350  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DT
71351  *
71352  */
71353 #define ALT_EMAC_DMA_OP_MOD_DT_E_DISD 0x0
71354 /*
71355  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DT
71356  *
71357  */
71358 #define ALT_EMAC_DMA_OP_MOD_DT_E_END 0x1
71359 
71360 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_DT register field. */
71361 #define ALT_EMAC_DMA_OP_MOD_DT_LSB 26
71362 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_DT register field. */
71363 #define ALT_EMAC_DMA_OP_MOD_DT_MSB 26
71364 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_DT register field. */
71365 #define ALT_EMAC_DMA_OP_MOD_DT_WIDTH 1
71366 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_DT register field value. */
71367 #define ALT_EMAC_DMA_OP_MOD_DT_SET_MSK 0x04000000
71368 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_DT register field value. */
71369 #define ALT_EMAC_DMA_OP_MOD_DT_CLR_MSK 0xfbffffff
71370 /* The reset value of the ALT_EMAC_DMA_OP_MOD_DT register field. */
71371 #define ALT_EMAC_DMA_OP_MOD_DT_RESET 0x0
71372 /* Extracts the ALT_EMAC_DMA_OP_MOD_DT field value from a register. */
71373 #define ALT_EMAC_DMA_OP_MOD_DT_GET(value) (((value) & 0x04000000) >> 26)
71374 /* Produces a ALT_EMAC_DMA_OP_MOD_DT register field value suitable for setting the register. */
71375 #define ALT_EMAC_DMA_OP_MOD_DT_SET(value) (((value) << 26) & 0x04000000)
71376 
71377 /*
71378  * Field : reserved_31_27
71379  *
71380  * Reserved
71381  *
71382  * Field Access Macros:
71383  *
71384  */
71385 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RSVD_31_27 register field. */
71386 #define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_LSB 27
71387 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RSVD_31_27 register field. */
71388 #define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_MSB 31
71389 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_RSVD_31_27 register field. */
71390 #define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_WIDTH 5
71391 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_RSVD_31_27 register field value. */
71392 #define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_SET_MSK 0xf8000000
71393 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_RSVD_31_27 register field value. */
71394 #define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_CLR_MSK 0x07ffffff
71395 /* The reset value of the ALT_EMAC_DMA_OP_MOD_RSVD_31_27 register field. */
71396 #define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_RESET 0x0
71397 /* Extracts the ALT_EMAC_DMA_OP_MOD_RSVD_31_27 field value from a register. */
71398 #define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_GET(value) (((value) & 0xf8000000) >> 27)
71399 /* Produces a ALT_EMAC_DMA_OP_MOD_RSVD_31_27 register field value suitable for setting the register. */
71400 #define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_SET(value) (((value) << 27) & 0xf8000000)
71401 
71402 #ifndef __ASSEMBLY__
71403 /*
71404  * WARNING: The C register and register group struct declarations are provided for
71405  * convenience and illustrative purposes. They should, however, be used with
71406  * caution as the C language standard provides no guarantees about the alignment or
71407  * atomicity of device memory accesses. The recommended practice for writing
71408  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
71409  * alt_write_word() functions.
71410  *
71411  * The struct declaration for register ALT_EMAC_DMA_OP_MOD.
71412  */
71413 struct ALT_EMAC_DMA_OP_MOD_s
71414 {
71415  const uint32_t reserved_0 : 1; /* ALT_EMAC_DMA_OP_MOD_RSVD_0 */
71416  uint32_t sr : 1; /* ALT_EMAC_DMA_OP_MOD_SR */
71417  uint32_t osf : 1; /* ALT_EMAC_DMA_OP_MOD_OSF */
71418  uint32_t rtc : 2; /* ALT_EMAC_DMA_OP_MOD_RTC */
71419  uint32_t dgf : 1; /* ALT_EMAC_DMA_OP_MOD_DGF */
71420  uint32_t fuf : 1; /* ALT_EMAC_DMA_OP_MOD_FUF */
71421  uint32_t fef : 1; /* ALT_EMAC_DMA_OP_MOD_FEF */
71422  const uint32_t efc : 1; /* ALT_EMAC_DMA_OP_MOD_EFC */
71423  const uint32_t rfa : 2; /* ALT_EMAC_DMA_OP_MOD_RFA */
71424  const uint32_t rfd : 2; /* ALT_EMAC_DMA_OP_MOD_RFD */
71425  uint32_t st : 1; /* ALT_EMAC_DMA_OP_MOD_ST */
71426  uint32_t ttc : 3; /* ALT_EMAC_DMA_OP_MOD_TTC */
71427  const uint32_t reserved_19_17 : 3; /* ALT_EMAC_DMA_OP_MOD_RSVD_19_17 */
71428  uint32_t ftf : 1; /* ALT_EMAC_DMA_OP_MOD_FTF */
71429  uint32_t tsf : 1; /* ALT_EMAC_DMA_OP_MOD_TSF */
71430  const uint32_t rfd_2 : 1; /* ALT_EMAC_DMA_OP_MOD_RFD_2 */
71431  const uint32_t rfa_2 : 1; /* ALT_EMAC_DMA_OP_MOD_RFA_2 */
71432  uint32_t dff : 1; /* ALT_EMAC_DMA_OP_MOD_DFF */
71433  uint32_t rsf : 1; /* ALT_EMAC_DMA_OP_MOD_RSF */
71434  uint32_t dt : 1; /* ALT_EMAC_DMA_OP_MOD_DT */
71435  const uint32_t reserved_31_27 : 5; /* ALT_EMAC_DMA_OP_MOD_RSVD_31_27 */
71436 };
71437 
71438 /* The typedef declaration for register ALT_EMAC_DMA_OP_MOD. */
71439 typedef volatile struct ALT_EMAC_DMA_OP_MOD_s ALT_EMAC_DMA_OP_MOD_t;
71440 #endif /* __ASSEMBLY__ */
71441 
71442 /* The reset value of the ALT_EMAC_DMA_OP_MOD register. */
71443 #define ALT_EMAC_DMA_OP_MOD_RESET 0x00000000
71444 /* The byte offset of the ALT_EMAC_DMA_OP_MOD register from the beginning of the component. */
71445 #define ALT_EMAC_DMA_OP_MOD_OFST 0x1018
71446 /* The address of the ALT_EMAC_DMA_OP_MOD register. */
71447 #define ALT_EMAC_DMA_OP_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_OP_MOD_OFST))
71448 
71449 /*
71450  * Register : dmagrp_interrupt_enable
71451  *
71452  * <b> Register 7 (Interrupt Enable Register) </b>
71453  *
71454  * The Interrupt Enable register enables the interrupts reported by Register 5
71455  * (Status Register). Setting a bit to 1'b1 enables a corresponding interrupt.
71456  * After a hardware or software reset, all interrupts are disabled.
71457  *
71458  * Register Layout
71459  *
71460  * Bits | Access | Reset | Description
71461  * :--------|:-------|:------|:-------------------------------
71462  * [0] | RW | 0x0 | ALT_EMAC_DMA_INT_EN_TIE
71463  * [1] | RW | 0x0 | ALT_EMAC_DMA_INT_EN_TSE
71464  * [2] | RW | 0x0 | ALT_EMAC_DMA_INT_EN_TUE
71465  * [3] | RW | 0x0 | ALT_EMAC_DMA_INT_EN_TJE
71466  * [4] | RW | 0x0 | ALT_EMAC_DMA_INT_EN_OVE
71467  * [5] | RW | 0x0 | ALT_EMAC_DMA_INT_EN_UNE
71468  * [6] | RW | 0x0 | ALT_EMAC_DMA_INT_EN_RIE
71469  * [7] | RW | 0x0 | ALT_EMAC_DMA_INT_EN_RUE
71470  * [8] | RW | 0x0 | ALT_EMAC_DMA_INT_EN_RSE
71471  * [9] | RW | 0x0 | ALT_EMAC_DMA_INT_EN_RWE
71472  * [10] | RW | 0x0 | ALT_EMAC_DMA_INT_EN_ETE
71473  * [12:11] | R | 0x0 | ALT_EMAC_DMA_INT_EN_RSVD_12_11
71474  * [13] | RW | 0x0 | ALT_EMAC_DMA_INT_EN_FBE
71475  * [14] | RW | 0x0 | ALT_EMAC_DMA_INT_EN_ERE
71476  * [15] | RW | 0x0 | ALT_EMAC_DMA_INT_EN_AIE
71477  * [16] | RW | 0x0 | ALT_EMAC_DMA_INT_EN_NIE
71478  * [31:17] | R | 0x0 | ALT_EMAC_DMA_INT_EN_RSVD_31_17
71479  *
71480  */
71481 /*
71482  * Field : tie
71483  *
71484  * Transmit Interrupt Enable
71485  *
71486  * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit
71487  * Interrupt is enabled. When this bit is reset, the Transmit Interrupt is
71488  * disabled.
71489  *
71490  * Field Enumeration Values:
71491  *
71492  * Enum | Value | Description
71493  * :-------------------------------|:------|:------------
71494  * ALT_EMAC_DMA_INT_EN_TIE_E_DISD | 0x0 |
71495  * ALT_EMAC_DMA_INT_EN_TIE_E_END | 0x1 |
71496  *
71497  * Field Access Macros:
71498  *
71499  */
71500 /*
71501  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TIE
71502  *
71503  */
71504 #define ALT_EMAC_DMA_INT_EN_TIE_E_DISD 0x0
71505 /*
71506  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TIE
71507  *
71508  */
71509 #define ALT_EMAC_DMA_INT_EN_TIE_E_END 0x1
71510 
71511 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_TIE register field. */
71512 #define ALT_EMAC_DMA_INT_EN_TIE_LSB 0
71513 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_TIE register field. */
71514 #define ALT_EMAC_DMA_INT_EN_TIE_MSB 0
71515 /* The width in bits of the ALT_EMAC_DMA_INT_EN_TIE register field. */
71516 #define ALT_EMAC_DMA_INT_EN_TIE_WIDTH 1
71517 /* The mask used to set the ALT_EMAC_DMA_INT_EN_TIE register field value. */
71518 #define ALT_EMAC_DMA_INT_EN_TIE_SET_MSK 0x00000001
71519 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_TIE register field value. */
71520 #define ALT_EMAC_DMA_INT_EN_TIE_CLR_MSK 0xfffffffe
71521 /* The reset value of the ALT_EMAC_DMA_INT_EN_TIE register field. */
71522 #define ALT_EMAC_DMA_INT_EN_TIE_RESET 0x0
71523 /* Extracts the ALT_EMAC_DMA_INT_EN_TIE field value from a register. */
71524 #define ALT_EMAC_DMA_INT_EN_TIE_GET(value) (((value) & 0x00000001) >> 0)
71525 /* Produces a ALT_EMAC_DMA_INT_EN_TIE register field value suitable for setting the register. */
71526 #define ALT_EMAC_DMA_INT_EN_TIE_SET(value) (((value) << 0) & 0x00000001)
71527 
71528 /*
71529  * Field : tse
71530  *
71531  * Transmit Stopped Enable
71532  *
71533  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
71534  * Transmission Stopped Interrupt is enabled. When this bit is reset, the
71535  * Transmission Stopped Interrupt is disabled.
71536  *
71537  * Field Enumeration Values:
71538  *
71539  * Enum | Value | Description
71540  * :-------------------------------|:------|:------------
71541  * ALT_EMAC_DMA_INT_EN_TSE_E_DISD | 0x0 |
71542  * ALT_EMAC_DMA_INT_EN_TSE_E_END | 0x1 |
71543  *
71544  * Field Access Macros:
71545  *
71546  */
71547 /*
71548  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TSE
71549  *
71550  */
71551 #define ALT_EMAC_DMA_INT_EN_TSE_E_DISD 0x0
71552 /*
71553  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TSE
71554  *
71555  */
71556 #define ALT_EMAC_DMA_INT_EN_TSE_E_END 0x1
71557 
71558 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_TSE register field. */
71559 #define ALT_EMAC_DMA_INT_EN_TSE_LSB 1
71560 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_TSE register field. */
71561 #define ALT_EMAC_DMA_INT_EN_TSE_MSB 1
71562 /* The width in bits of the ALT_EMAC_DMA_INT_EN_TSE register field. */
71563 #define ALT_EMAC_DMA_INT_EN_TSE_WIDTH 1
71564 /* The mask used to set the ALT_EMAC_DMA_INT_EN_TSE register field value. */
71565 #define ALT_EMAC_DMA_INT_EN_TSE_SET_MSK 0x00000002
71566 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_TSE register field value. */
71567 #define ALT_EMAC_DMA_INT_EN_TSE_CLR_MSK 0xfffffffd
71568 /* The reset value of the ALT_EMAC_DMA_INT_EN_TSE register field. */
71569 #define ALT_EMAC_DMA_INT_EN_TSE_RESET 0x0
71570 /* Extracts the ALT_EMAC_DMA_INT_EN_TSE field value from a register. */
71571 #define ALT_EMAC_DMA_INT_EN_TSE_GET(value) (((value) & 0x00000002) >> 1)
71572 /* Produces a ALT_EMAC_DMA_INT_EN_TSE register field value suitable for setting the register. */
71573 #define ALT_EMAC_DMA_INT_EN_TSE_SET(value) (((value) << 1) & 0x00000002)
71574 
71575 /*
71576  * Field : tue
71577  *
71578  * Transmit Buffer Unavailable Enable
71579  *
71580  * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit
71581  * Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit
71582  * Buffer Unavailable Interrupt is disabled.
71583  *
71584  * Field Enumeration Values:
71585  *
71586  * Enum | Value | Description
71587  * :-------------------------------|:------|:------------
71588  * ALT_EMAC_DMA_INT_EN_TUE_E_DISD | 0x0 |
71589  * ALT_EMAC_DMA_INT_EN_TUE_E_END | 0x1 |
71590  *
71591  * Field Access Macros:
71592  *
71593  */
71594 /*
71595  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TUE
71596  *
71597  */
71598 #define ALT_EMAC_DMA_INT_EN_TUE_E_DISD 0x0
71599 /*
71600  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TUE
71601  *
71602  */
71603 #define ALT_EMAC_DMA_INT_EN_TUE_E_END 0x1
71604 
71605 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_TUE register field. */
71606 #define ALT_EMAC_DMA_INT_EN_TUE_LSB 2
71607 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_TUE register field. */
71608 #define ALT_EMAC_DMA_INT_EN_TUE_MSB 2
71609 /* The width in bits of the ALT_EMAC_DMA_INT_EN_TUE register field. */
71610 #define ALT_EMAC_DMA_INT_EN_TUE_WIDTH 1
71611 /* The mask used to set the ALT_EMAC_DMA_INT_EN_TUE register field value. */
71612 #define ALT_EMAC_DMA_INT_EN_TUE_SET_MSK 0x00000004
71613 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_TUE register field value. */
71614 #define ALT_EMAC_DMA_INT_EN_TUE_CLR_MSK 0xfffffffb
71615 /* The reset value of the ALT_EMAC_DMA_INT_EN_TUE register field. */
71616 #define ALT_EMAC_DMA_INT_EN_TUE_RESET 0x0
71617 /* Extracts the ALT_EMAC_DMA_INT_EN_TUE field value from a register. */
71618 #define ALT_EMAC_DMA_INT_EN_TUE_GET(value) (((value) & 0x00000004) >> 2)
71619 /* Produces a ALT_EMAC_DMA_INT_EN_TUE register field value suitable for setting the register. */
71620 #define ALT_EMAC_DMA_INT_EN_TUE_SET(value) (((value) << 2) & 0x00000004)
71621 
71622 /*
71623  * Field : tje
71624  *
71625  * Transmit Jabber Timeout Enable
71626  *
71627  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
71628  * Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the
71629  * Transmit Jabber Timeout Interrupt is disabled.
71630  *
71631  * Field Enumeration Values:
71632  *
71633  * Enum | Value | Description
71634  * :-------------------------------|:------|:------------
71635  * ALT_EMAC_DMA_INT_EN_TJE_E_DISD | 0x0 |
71636  * ALT_EMAC_DMA_INT_EN_TJE_E_END | 0x1 |
71637  *
71638  * Field Access Macros:
71639  *
71640  */
71641 /*
71642  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TJE
71643  *
71644  */
71645 #define ALT_EMAC_DMA_INT_EN_TJE_E_DISD 0x0
71646 /*
71647  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TJE
71648  *
71649  */
71650 #define ALT_EMAC_DMA_INT_EN_TJE_E_END 0x1
71651 
71652 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_TJE register field. */
71653 #define ALT_EMAC_DMA_INT_EN_TJE_LSB 3
71654 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_TJE register field. */
71655 #define ALT_EMAC_DMA_INT_EN_TJE_MSB 3
71656 /* The width in bits of the ALT_EMAC_DMA_INT_EN_TJE register field. */
71657 #define ALT_EMAC_DMA_INT_EN_TJE_WIDTH 1
71658 /* The mask used to set the ALT_EMAC_DMA_INT_EN_TJE register field value. */
71659 #define ALT_EMAC_DMA_INT_EN_TJE_SET_MSK 0x00000008
71660 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_TJE register field value. */
71661 #define ALT_EMAC_DMA_INT_EN_TJE_CLR_MSK 0xfffffff7
71662 /* The reset value of the ALT_EMAC_DMA_INT_EN_TJE register field. */
71663 #define ALT_EMAC_DMA_INT_EN_TJE_RESET 0x0
71664 /* Extracts the ALT_EMAC_DMA_INT_EN_TJE field value from a register. */
71665 #define ALT_EMAC_DMA_INT_EN_TJE_GET(value) (((value) & 0x00000008) >> 3)
71666 /* Produces a ALT_EMAC_DMA_INT_EN_TJE register field value suitable for setting the register. */
71667 #define ALT_EMAC_DMA_INT_EN_TJE_SET(value) (((value) << 3) & 0x00000008)
71668 
71669 /*
71670  * Field : ove
71671  *
71672  * Overflow Interrupt Enable
71673  *
71674  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
71675  * Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow
71676  * Interrupt is disabled.
71677  *
71678  * Field Enumeration Values:
71679  *
71680  * Enum | Value | Description
71681  * :-------------------------------|:------|:------------
71682  * ALT_EMAC_DMA_INT_EN_OVE_E_DISD | 0x0 |
71683  * ALT_EMAC_DMA_INT_EN_OVE_E_END | 0x1 |
71684  *
71685  * Field Access Macros:
71686  *
71687  */
71688 /*
71689  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_OVE
71690  *
71691  */
71692 #define ALT_EMAC_DMA_INT_EN_OVE_E_DISD 0x0
71693 /*
71694  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_OVE
71695  *
71696  */
71697 #define ALT_EMAC_DMA_INT_EN_OVE_E_END 0x1
71698 
71699 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_OVE register field. */
71700 #define ALT_EMAC_DMA_INT_EN_OVE_LSB 4
71701 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_OVE register field. */
71702 #define ALT_EMAC_DMA_INT_EN_OVE_MSB 4
71703 /* The width in bits of the ALT_EMAC_DMA_INT_EN_OVE register field. */
71704 #define ALT_EMAC_DMA_INT_EN_OVE_WIDTH 1
71705 /* The mask used to set the ALT_EMAC_DMA_INT_EN_OVE register field value. */
71706 #define ALT_EMAC_DMA_INT_EN_OVE_SET_MSK 0x00000010
71707 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_OVE register field value. */
71708 #define ALT_EMAC_DMA_INT_EN_OVE_CLR_MSK 0xffffffef
71709 /* The reset value of the ALT_EMAC_DMA_INT_EN_OVE register field. */
71710 #define ALT_EMAC_DMA_INT_EN_OVE_RESET 0x0
71711 /* Extracts the ALT_EMAC_DMA_INT_EN_OVE field value from a register. */
71712 #define ALT_EMAC_DMA_INT_EN_OVE_GET(value) (((value) & 0x00000010) >> 4)
71713 /* Produces a ALT_EMAC_DMA_INT_EN_OVE register field value suitable for setting the register. */
71714 #define ALT_EMAC_DMA_INT_EN_OVE_SET(value) (((value) << 4) & 0x00000010)
71715 
71716 /*
71717  * Field : une
71718  *
71719  * Underflow Interrupt Enable
71720  *
71721  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
71722  * Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow
71723  * Interrupt is disabled.
71724  *
71725  * Field Enumeration Values:
71726  *
71727  * Enum | Value | Description
71728  * :-------------------------------|:------|:------------
71729  * ALT_EMAC_DMA_INT_EN_UNE_E_DISD | 0x0 |
71730  * ALT_EMAC_DMA_INT_EN_UNE_E_END | 0x1 |
71731  *
71732  * Field Access Macros:
71733  *
71734  */
71735 /*
71736  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_UNE
71737  *
71738  */
71739 #define ALT_EMAC_DMA_INT_EN_UNE_E_DISD 0x0
71740 /*
71741  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_UNE
71742  *
71743  */
71744 #define ALT_EMAC_DMA_INT_EN_UNE_E_END 0x1
71745 
71746 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_UNE register field. */
71747 #define ALT_EMAC_DMA_INT_EN_UNE_LSB 5
71748 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_UNE register field. */
71749 #define ALT_EMAC_DMA_INT_EN_UNE_MSB 5
71750 /* The width in bits of the ALT_EMAC_DMA_INT_EN_UNE register field. */
71751 #define ALT_EMAC_DMA_INT_EN_UNE_WIDTH 1
71752 /* The mask used to set the ALT_EMAC_DMA_INT_EN_UNE register field value. */
71753 #define ALT_EMAC_DMA_INT_EN_UNE_SET_MSK 0x00000020
71754 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_UNE register field value. */
71755 #define ALT_EMAC_DMA_INT_EN_UNE_CLR_MSK 0xffffffdf
71756 /* The reset value of the ALT_EMAC_DMA_INT_EN_UNE register field. */
71757 #define ALT_EMAC_DMA_INT_EN_UNE_RESET 0x0
71758 /* Extracts the ALT_EMAC_DMA_INT_EN_UNE field value from a register. */
71759 #define ALT_EMAC_DMA_INT_EN_UNE_GET(value) (((value) & 0x00000020) >> 5)
71760 /* Produces a ALT_EMAC_DMA_INT_EN_UNE register field value suitable for setting the register. */
71761 #define ALT_EMAC_DMA_INT_EN_UNE_SET(value) (((value) << 5) & 0x00000020)
71762 
71763 /*
71764  * Field : rie
71765  *
71766  * Receive Interrupt Enable
71767  *
71768  * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive
71769  * Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled.
71770  *
71771  * Field Enumeration Values:
71772  *
71773  * Enum | Value | Description
71774  * :-------------------------------|:------|:------------
71775  * ALT_EMAC_DMA_INT_EN_RIE_E_DISD | 0x0 |
71776  * ALT_EMAC_DMA_INT_EN_RIE_E_END | 0x1 |
71777  *
71778  * Field Access Macros:
71779  *
71780  */
71781 /*
71782  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RIE
71783  *
71784  */
71785 #define ALT_EMAC_DMA_INT_EN_RIE_E_DISD 0x0
71786 /*
71787  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RIE
71788  *
71789  */
71790 #define ALT_EMAC_DMA_INT_EN_RIE_E_END 0x1
71791 
71792 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_RIE register field. */
71793 #define ALT_EMAC_DMA_INT_EN_RIE_LSB 6
71794 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_RIE register field. */
71795 #define ALT_EMAC_DMA_INT_EN_RIE_MSB 6
71796 /* The width in bits of the ALT_EMAC_DMA_INT_EN_RIE register field. */
71797 #define ALT_EMAC_DMA_INT_EN_RIE_WIDTH 1
71798 /* The mask used to set the ALT_EMAC_DMA_INT_EN_RIE register field value. */
71799 #define ALT_EMAC_DMA_INT_EN_RIE_SET_MSK 0x00000040
71800 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_RIE register field value. */
71801 #define ALT_EMAC_DMA_INT_EN_RIE_CLR_MSK 0xffffffbf
71802 /* The reset value of the ALT_EMAC_DMA_INT_EN_RIE register field. */
71803 #define ALT_EMAC_DMA_INT_EN_RIE_RESET 0x0
71804 /* Extracts the ALT_EMAC_DMA_INT_EN_RIE field value from a register. */
71805 #define ALT_EMAC_DMA_INT_EN_RIE_GET(value) (((value) & 0x00000040) >> 6)
71806 /* Produces a ALT_EMAC_DMA_INT_EN_RIE register field value suitable for setting the register. */
71807 #define ALT_EMAC_DMA_INT_EN_RIE_SET(value) (((value) << 6) & 0x00000040)
71808 
71809 /*
71810  * Field : rue
71811  *
71812  * Receive Buffer Unavailable Enable
71813  *
71814  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
71815  * Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the
71816  * Receive Buffer Unavailable Interrupt is disabled.
71817  *
71818  * Field Access Macros:
71819  *
71820  */
71821 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_RUE register field. */
71822 #define ALT_EMAC_DMA_INT_EN_RUE_LSB 7
71823 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_RUE register field. */
71824 #define ALT_EMAC_DMA_INT_EN_RUE_MSB 7
71825 /* The width in bits of the ALT_EMAC_DMA_INT_EN_RUE register field. */
71826 #define ALT_EMAC_DMA_INT_EN_RUE_WIDTH 1
71827 /* The mask used to set the ALT_EMAC_DMA_INT_EN_RUE register field value. */
71828 #define ALT_EMAC_DMA_INT_EN_RUE_SET_MSK 0x00000080
71829 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_RUE register field value. */
71830 #define ALT_EMAC_DMA_INT_EN_RUE_CLR_MSK 0xffffff7f
71831 /* The reset value of the ALT_EMAC_DMA_INT_EN_RUE register field. */
71832 #define ALT_EMAC_DMA_INT_EN_RUE_RESET 0x0
71833 /* Extracts the ALT_EMAC_DMA_INT_EN_RUE field value from a register. */
71834 #define ALT_EMAC_DMA_INT_EN_RUE_GET(value) (((value) & 0x00000080) >> 7)
71835 /* Produces a ALT_EMAC_DMA_INT_EN_RUE register field value suitable for setting the register. */
71836 #define ALT_EMAC_DMA_INT_EN_RUE_SET(value) (((value) << 7) & 0x00000080)
71837 
71838 /*
71839  * Field : rse
71840  *
71841  * Receive Stopped Enable
71842  *
71843  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
71844  * Receive Stopped Interrupt is enabled. When this bit is reset, the Receive
71845  * Stopped Interrupt is disabled.
71846  *
71847  * Field Enumeration Values:
71848  *
71849  * Enum | Value | Description
71850  * :-------------------------------|:------|:------------
71851  * ALT_EMAC_DMA_INT_EN_RSE_E_DISD | 0x0 |
71852  * ALT_EMAC_DMA_INT_EN_RSE_E_END | 0x1 |
71853  *
71854  * Field Access Macros:
71855  *
71856  */
71857 /*
71858  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RSE
71859  *
71860  */
71861 #define ALT_EMAC_DMA_INT_EN_RSE_E_DISD 0x0
71862 /*
71863  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RSE
71864  *
71865  */
71866 #define ALT_EMAC_DMA_INT_EN_RSE_E_END 0x1
71867 
71868 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_RSE register field. */
71869 #define ALT_EMAC_DMA_INT_EN_RSE_LSB 8
71870 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_RSE register field. */
71871 #define ALT_EMAC_DMA_INT_EN_RSE_MSB 8
71872 /* The width in bits of the ALT_EMAC_DMA_INT_EN_RSE register field. */
71873 #define ALT_EMAC_DMA_INT_EN_RSE_WIDTH 1
71874 /* The mask used to set the ALT_EMAC_DMA_INT_EN_RSE register field value. */
71875 #define ALT_EMAC_DMA_INT_EN_RSE_SET_MSK 0x00000100
71876 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_RSE register field value. */
71877 #define ALT_EMAC_DMA_INT_EN_RSE_CLR_MSK 0xfffffeff
71878 /* The reset value of the ALT_EMAC_DMA_INT_EN_RSE register field. */
71879 #define ALT_EMAC_DMA_INT_EN_RSE_RESET 0x0
71880 /* Extracts the ALT_EMAC_DMA_INT_EN_RSE field value from a register. */
71881 #define ALT_EMAC_DMA_INT_EN_RSE_GET(value) (((value) & 0x00000100) >> 8)
71882 /* Produces a ALT_EMAC_DMA_INT_EN_RSE register field value suitable for setting the register. */
71883 #define ALT_EMAC_DMA_INT_EN_RSE_SET(value) (((value) << 8) & 0x00000100)
71884 
71885 /*
71886  * Field : rwe
71887  *
71888  * Receive Watchdog Timeout Enable
71889  *
71890  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
71891  * Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the
71892  * Receive Watchdog Timeout Interrupt is disabled.
71893  *
71894  * Field Enumeration Values:
71895  *
71896  * Enum | Value | Description
71897  * :-------------------------------|:------|:------------
71898  * ALT_EMAC_DMA_INT_EN_RWE_E_DISD | 0x0 |
71899  * ALT_EMAC_DMA_INT_EN_RWE_E_END | 0x1 |
71900  *
71901  * Field Access Macros:
71902  *
71903  */
71904 /*
71905  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RWE
71906  *
71907  */
71908 #define ALT_EMAC_DMA_INT_EN_RWE_E_DISD 0x0
71909 /*
71910  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RWE
71911  *
71912  */
71913 #define ALT_EMAC_DMA_INT_EN_RWE_E_END 0x1
71914 
71915 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_RWE register field. */
71916 #define ALT_EMAC_DMA_INT_EN_RWE_LSB 9
71917 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_RWE register field. */
71918 #define ALT_EMAC_DMA_INT_EN_RWE_MSB 9
71919 /* The width in bits of the ALT_EMAC_DMA_INT_EN_RWE register field. */
71920 #define ALT_EMAC_DMA_INT_EN_RWE_WIDTH 1
71921 /* The mask used to set the ALT_EMAC_DMA_INT_EN_RWE register field value. */
71922 #define ALT_EMAC_DMA_INT_EN_RWE_SET_MSK 0x00000200
71923 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_RWE register field value. */
71924 #define ALT_EMAC_DMA_INT_EN_RWE_CLR_MSK 0xfffffdff
71925 /* The reset value of the ALT_EMAC_DMA_INT_EN_RWE register field. */
71926 #define ALT_EMAC_DMA_INT_EN_RWE_RESET 0x0
71927 /* Extracts the ALT_EMAC_DMA_INT_EN_RWE field value from a register. */
71928 #define ALT_EMAC_DMA_INT_EN_RWE_GET(value) (((value) & 0x00000200) >> 9)
71929 /* Produces a ALT_EMAC_DMA_INT_EN_RWE register field value suitable for setting the register. */
71930 #define ALT_EMAC_DMA_INT_EN_RWE_SET(value) (((value) << 9) & 0x00000200)
71931 
71932 /*
71933  * Field : ete
71934  *
71935  * Early Transmit Interrupt Enable
71936  *
71937  * When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the
71938  * Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit
71939  * Interrupt is disabled.
71940  *
71941  * Field Enumeration Values:
71942  *
71943  * Enum | Value | Description
71944  * :-------------------------------|:------|:------------
71945  * ALT_EMAC_DMA_INT_EN_ETE_E_DISD | 0x0 |
71946  * ALT_EMAC_DMA_INT_EN_ETE_E_END | 0x1 |
71947  *
71948  * Field Access Macros:
71949  *
71950  */
71951 /*
71952  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_ETE
71953  *
71954  */
71955 #define ALT_EMAC_DMA_INT_EN_ETE_E_DISD 0x0
71956 /*
71957  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_ETE
71958  *
71959  */
71960 #define ALT_EMAC_DMA_INT_EN_ETE_E_END 0x1
71961 
71962 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_ETE register field. */
71963 #define ALT_EMAC_DMA_INT_EN_ETE_LSB 10
71964 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_ETE register field. */
71965 #define ALT_EMAC_DMA_INT_EN_ETE_MSB 10
71966 /* The width in bits of the ALT_EMAC_DMA_INT_EN_ETE register field. */
71967 #define ALT_EMAC_DMA_INT_EN_ETE_WIDTH 1
71968 /* The mask used to set the ALT_EMAC_DMA_INT_EN_ETE register field value. */
71969 #define ALT_EMAC_DMA_INT_EN_ETE_SET_MSK 0x00000400
71970 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_ETE register field value. */
71971 #define ALT_EMAC_DMA_INT_EN_ETE_CLR_MSK 0xfffffbff
71972 /* The reset value of the ALT_EMAC_DMA_INT_EN_ETE register field. */
71973 #define ALT_EMAC_DMA_INT_EN_ETE_RESET 0x0
71974 /* Extracts the ALT_EMAC_DMA_INT_EN_ETE field value from a register. */
71975 #define ALT_EMAC_DMA_INT_EN_ETE_GET(value) (((value) & 0x00000400) >> 10)
71976 /* Produces a ALT_EMAC_DMA_INT_EN_ETE register field value suitable for setting the register. */
71977 #define ALT_EMAC_DMA_INT_EN_ETE_SET(value) (((value) << 10) & 0x00000400)
71978 
71979 /*
71980  * Field : reserved_12_11
71981  *
71982  * Reserved
71983  *
71984  * Field Access Macros:
71985  *
71986  */
71987 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_RSVD_12_11 register field. */
71988 #define ALT_EMAC_DMA_INT_EN_RSVD_12_11_LSB 11
71989 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_RSVD_12_11 register field. */
71990 #define ALT_EMAC_DMA_INT_EN_RSVD_12_11_MSB 12
71991 /* The width in bits of the ALT_EMAC_DMA_INT_EN_RSVD_12_11 register field. */
71992 #define ALT_EMAC_DMA_INT_EN_RSVD_12_11_WIDTH 2
71993 /* The mask used to set the ALT_EMAC_DMA_INT_EN_RSVD_12_11 register field value. */
71994 #define ALT_EMAC_DMA_INT_EN_RSVD_12_11_SET_MSK 0x00001800
71995 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_RSVD_12_11 register field value. */
71996 #define ALT_EMAC_DMA_INT_EN_RSVD_12_11_CLR_MSK 0xffffe7ff
71997 /* The reset value of the ALT_EMAC_DMA_INT_EN_RSVD_12_11 register field. */
71998 #define ALT_EMAC_DMA_INT_EN_RSVD_12_11_RESET 0x0
71999 /* Extracts the ALT_EMAC_DMA_INT_EN_RSVD_12_11 field value from a register. */
72000 #define ALT_EMAC_DMA_INT_EN_RSVD_12_11_GET(value) (((value) & 0x00001800) >> 11)
72001 /* Produces a ALT_EMAC_DMA_INT_EN_RSVD_12_11 register field value suitable for setting the register. */
72002 #define ALT_EMAC_DMA_INT_EN_RSVD_12_11_SET(value) (((value) << 11) & 0x00001800)
72003 
72004 /*
72005  * Field : fbe
72006  *
72007  * Fatal Bus Error Enable
72008  *
72009  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal
72010  * Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error
72011  * Enable Interrupt is disabled.
72012  *
72013  * Field Enumeration Values:
72014  *
72015  * Enum | Value | Description
72016  * :-------------------------------|:------|:------------
72017  * ALT_EMAC_DMA_INT_EN_FBE_E_DISD | 0x0 |
72018  * ALT_EMAC_DMA_INT_EN_FBE_E_END | 0x1 |
72019  *
72020  * Field Access Macros:
72021  *
72022  */
72023 /*
72024  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_FBE
72025  *
72026  */
72027 #define ALT_EMAC_DMA_INT_EN_FBE_E_DISD 0x0
72028 /*
72029  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_FBE
72030  *
72031  */
72032 #define ALT_EMAC_DMA_INT_EN_FBE_E_END 0x1
72033 
72034 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_FBE register field. */
72035 #define ALT_EMAC_DMA_INT_EN_FBE_LSB 13
72036 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_FBE register field. */
72037 #define ALT_EMAC_DMA_INT_EN_FBE_MSB 13
72038 /* The width in bits of the ALT_EMAC_DMA_INT_EN_FBE register field. */
72039 #define ALT_EMAC_DMA_INT_EN_FBE_WIDTH 1
72040 /* The mask used to set the ALT_EMAC_DMA_INT_EN_FBE register field value. */
72041 #define ALT_EMAC_DMA_INT_EN_FBE_SET_MSK 0x00002000
72042 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_FBE register field value. */
72043 #define ALT_EMAC_DMA_INT_EN_FBE_CLR_MSK 0xffffdfff
72044 /* The reset value of the ALT_EMAC_DMA_INT_EN_FBE register field. */
72045 #define ALT_EMAC_DMA_INT_EN_FBE_RESET 0x0
72046 /* Extracts the ALT_EMAC_DMA_INT_EN_FBE field value from a register. */
72047 #define ALT_EMAC_DMA_INT_EN_FBE_GET(value) (((value) & 0x00002000) >> 13)
72048 /* Produces a ALT_EMAC_DMA_INT_EN_FBE register field value suitable for setting the register. */
72049 #define ALT_EMAC_DMA_INT_EN_FBE_SET(value) (((value) << 13) & 0x00002000)
72050 
72051 /*
72052  * Field : ere
72053  *
72054  * Early Receive Interrupt Enable
72055  *
72056  * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early
72057  * Receive Interrupt is enabled. When this bit is reset, the Early Receive
72058  * Interrupt is disabled.
72059  *
72060  * Field Enumeration Values:
72061  *
72062  * Enum | Value | Description
72063  * :-------------------------------|:------|:------------
72064  * ALT_EMAC_DMA_INT_EN_ERE_E_DISD | 0x0 |
72065  * ALT_EMAC_DMA_INT_EN_ERE_E_END | 0x1 |
72066  *
72067  * Field Access Macros:
72068  *
72069  */
72070 /*
72071  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_ERE
72072  *
72073  */
72074 #define ALT_EMAC_DMA_INT_EN_ERE_E_DISD 0x0
72075 /*
72076  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_ERE
72077  *
72078  */
72079 #define ALT_EMAC_DMA_INT_EN_ERE_E_END 0x1
72080 
72081 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_ERE register field. */
72082 #define ALT_EMAC_DMA_INT_EN_ERE_LSB 14
72083 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_ERE register field. */
72084 #define ALT_EMAC_DMA_INT_EN_ERE_MSB 14
72085 /* The width in bits of the ALT_EMAC_DMA_INT_EN_ERE register field. */
72086 #define ALT_EMAC_DMA_INT_EN_ERE_WIDTH 1
72087 /* The mask used to set the ALT_EMAC_DMA_INT_EN_ERE register field value. */
72088 #define ALT_EMAC_DMA_INT_EN_ERE_SET_MSK 0x00004000
72089 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_ERE register field value. */
72090 #define ALT_EMAC_DMA_INT_EN_ERE_CLR_MSK 0xffffbfff
72091 /* The reset value of the ALT_EMAC_DMA_INT_EN_ERE register field. */
72092 #define ALT_EMAC_DMA_INT_EN_ERE_RESET 0x0
72093 /* Extracts the ALT_EMAC_DMA_INT_EN_ERE field value from a register. */
72094 #define ALT_EMAC_DMA_INT_EN_ERE_GET(value) (((value) & 0x00004000) >> 14)
72095 /* Produces a ALT_EMAC_DMA_INT_EN_ERE register field value suitable for setting the register. */
72096 #define ALT_EMAC_DMA_INT_EN_ERE_SET(value) (((value) << 14) & 0x00004000)
72097 
72098 /*
72099  * Field : aie
72100  *
72101  * Abnormal Interrupt Summary Enable
72102  *
72103  * When this bit is set, abnormal interrupt summary is enabled. When this bit is
72104  * reset, the abnormal interrupt summary is disabled. This bit enables the
72105  * following interrupts in Register 5 (Status Register):
72106  *
72107  * * Register 5[1]: Transmit Process Stopped
72108  *
72109  * * Register 5[3]: Transmit Jabber Timeout
72110  *
72111  * * Register 5[4]: Receive Overflow
72112  *
72113  * * Register 5[5]: Transmit Underflow
72114  *
72115  * * Register 5[7]: Receive Buffer Unavailable
72116  *
72117  * * Register 5[8]: Receive Process Stopped
72118  *
72119  * * Register 5[9]: Receive Watchdog Timeout
72120  *
72121  * * Register 5[10]: Early Transmit Interrupt
72122  *
72123  * * Register 5[13]: Fatal Bus Error
72124  *
72125  * Field Enumeration Values:
72126  *
72127  * Enum | Value | Description
72128  * :-------------------------------|:------|:------------
72129  * ALT_EMAC_DMA_INT_EN_AIE_E_DISD | 0x0 |
72130  * ALT_EMAC_DMA_INT_EN_AIE_E_END | 0x1 |
72131  *
72132  * Field Access Macros:
72133  *
72134  */
72135 /*
72136  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_AIE
72137  *
72138  */
72139 #define ALT_EMAC_DMA_INT_EN_AIE_E_DISD 0x0
72140 /*
72141  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_AIE
72142  *
72143  */
72144 #define ALT_EMAC_DMA_INT_EN_AIE_E_END 0x1
72145 
72146 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_AIE register field. */
72147 #define ALT_EMAC_DMA_INT_EN_AIE_LSB 15
72148 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_AIE register field. */
72149 #define ALT_EMAC_DMA_INT_EN_AIE_MSB 15
72150 /* The width in bits of the ALT_EMAC_DMA_INT_EN_AIE register field. */
72151 #define ALT_EMAC_DMA_INT_EN_AIE_WIDTH 1
72152 /* The mask used to set the ALT_EMAC_DMA_INT_EN_AIE register field value. */
72153 #define ALT_EMAC_DMA_INT_EN_AIE_SET_MSK 0x00008000
72154 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_AIE register field value. */
72155 #define ALT_EMAC_DMA_INT_EN_AIE_CLR_MSK 0xffff7fff
72156 /* The reset value of the ALT_EMAC_DMA_INT_EN_AIE register field. */
72157 #define ALT_EMAC_DMA_INT_EN_AIE_RESET 0x0
72158 /* Extracts the ALT_EMAC_DMA_INT_EN_AIE field value from a register. */
72159 #define ALT_EMAC_DMA_INT_EN_AIE_GET(value) (((value) & 0x00008000) >> 15)
72160 /* Produces a ALT_EMAC_DMA_INT_EN_AIE register field value suitable for setting the register. */
72161 #define ALT_EMAC_DMA_INT_EN_AIE_SET(value) (((value) << 15) & 0x00008000)
72162 
72163 /*
72164  * Field : nie
72165  *
72166  * Normal Interrupt Summary Enable
72167  *
72168  * When this bit is set, normal interrupt summary is enabled. When this bit is
72169  * reset, normal interrupt summary is disabled. This bit enables the following
72170  * interrupts in Register 5 (Status Register):
72171  *
72172  * * Register 5[0]: Transmit Interrupt
72173  *
72174  * * Register 5[2]: Transmit Buffer Unavailable
72175  *
72176  * * Register 5[6]: Receive Interrupt
72177  *
72178  * * Register 5[14]: Early Receive Interrupt
72179  *
72180  * Field Enumeration Values:
72181  *
72182  * Enum | Value | Description
72183  * :-------------------------------|:------|:------------
72184  * ALT_EMAC_DMA_INT_EN_NIE_E_DISD | 0x0 |
72185  * ALT_EMAC_DMA_INT_EN_NIE_E_END | 0x1 |
72186  *
72187  * Field Access Macros:
72188  *
72189  */
72190 /*
72191  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_NIE
72192  *
72193  */
72194 #define ALT_EMAC_DMA_INT_EN_NIE_E_DISD 0x0
72195 /*
72196  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_NIE
72197  *
72198  */
72199 #define ALT_EMAC_DMA_INT_EN_NIE_E_END 0x1
72200 
72201 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_NIE register field. */
72202 #define ALT_EMAC_DMA_INT_EN_NIE_LSB 16
72203 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_NIE register field. */
72204 #define ALT_EMAC_DMA_INT_EN_NIE_MSB 16
72205 /* The width in bits of the ALT_EMAC_DMA_INT_EN_NIE register field. */
72206 #define ALT_EMAC_DMA_INT_EN_NIE_WIDTH 1
72207 /* The mask used to set the ALT_EMAC_DMA_INT_EN_NIE register field value. */
72208 #define ALT_EMAC_DMA_INT_EN_NIE_SET_MSK 0x00010000
72209 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_NIE register field value. */
72210 #define ALT_EMAC_DMA_INT_EN_NIE_CLR_MSK 0xfffeffff
72211 /* The reset value of the ALT_EMAC_DMA_INT_EN_NIE register field. */
72212 #define ALT_EMAC_DMA_INT_EN_NIE_RESET 0x0
72213 /* Extracts the ALT_EMAC_DMA_INT_EN_NIE field value from a register. */
72214 #define ALT_EMAC_DMA_INT_EN_NIE_GET(value) (((value) & 0x00010000) >> 16)
72215 /* Produces a ALT_EMAC_DMA_INT_EN_NIE register field value suitable for setting the register. */
72216 #define ALT_EMAC_DMA_INT_EN_NIE_SET(value) (((value) << 16) & 0x00010000)
72217 
72218 /*
72219  * Field : reserved_31_17
72220  *
72221  * Reserved
72222  *
72223  * Field Access Macros:
72224  *
72225  */
72226 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_RSVD_31_17 register field. */
72227 #define ALT_EMAC_DMA_INT_EN_RSVD_31_17_LSB 17
72228 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_RSVD_31_17 register field. */
72229 #define ALT_EMAC_DMA_INT_EN_RSVD_31_17_MSB 31
72230 /* The width in bits of the ALT_EMAC_DMA_INT_EN_RSVD_31_17 register field. */
72231 #define ALT_EMAC_DMA_INT_EN_RSVD_31_17_WIDTH 15
72232 /* The mask used to set the ALT_EMAC_DMA_INT_EN_RSVD_31_17 register field value. */
72233 #define ALT_EMAC_DMA_INT_EN_RSVD_31_17_SET_MSK 0xfffe0000
72234 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_RSVD_31_17 register field value. */
72235 #define ALT_EMAC_DMA_INT_EN_RSVD_31_17_CLR_MSK 0x0001ffff
72236 /* The reset value of the ALT_EMAC_DMA_INT_EN_RSVD_31_17 register field. */
72237 #define ALT_EMAC_DMA_INT_EN_RSVD_31_17_RESET 0x0
72238 /* Extracts the ALT_EMAC_DMA_INT_EN_RSVD_31_17 field value from a register. */
72239 #define ALT_EMAC_DMA_INT_EN_RSVD_31_17_GET(value) (((value) & 0xfffe0000) >> 17)
72240 /* Produces a ALT_EMAC_DMA_INT_EN_RSVD_31_17 register field value suitable for setting the register. */
72241 #define ALT_EMAC_DMA_INT_EN_RSVD_31_17_SET(value) (((value) << 17) & 0xfffe0000)
72242 
72243 #ifndef __ASSEMBLY__
72244 /*
72245  * WARNING: The C register and register group struct declarations are provided for
72246  * convenience and illustrative purposes. They should, however, be used with
72247  * caution as the C language standard provides no guarantees about the alignment or
72248  * atomicity of device memory accesses. The recommended practice for writing
72249  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
72250  * alt_write_word() functions.
72251  *
72252  * The struct declaration for register ALT_EMAC_DMA_INT_EN.
72253  */
72254 struct ALT_EMAC_DMA_INT_EN_s
72255 {
72256  uint32_t tie : 1; /* ALT_EMAC_DMA_INT_EN_TIE */
72257  uint32_t tse : 1; /* ALT_EMAC_DMA_INT_EN_TSE */
72258  uint32_t tue : 1; /* ALT_EMAC_DMA_INT_EN_TUE */
72259  uint32_t tje : 1; /* ALT_EMAC_DMA_INT_EN_TJE */
72260  uint32_t ove : 1; /* ALT_EMAC_DMA_INT_EN_OVE */
72261  uint32_t une : 1; /* ALT_EMAC_DMA_INT_EN_UNE */
72262  uint32_t rie : 1; /* ALT_EMAC_DMA_INT_EN_RIE */
72263  uint32_t rue : 1; /* ALT_EMAC_DMA_INT_EN_RUE */
72264  uint32_t rse : 1; /* ALT_EMAC_DMA_INT_EN_RSE */
72265  uint32_t rwe : 1; /* ALT_EMAC_DMA_INT_EN_RWE */
72266  uint32_t ete : 1; /* ALT_EMAC_DMA_INT_EN_ETE */
72267  const uint32_t reserved_12_11 : 2; /* ALT_EMAC_DMA_INT_EN_RSVD_12_11 */
72268  uint32_t fbe : 1; /* ALT_EMAC_DMA_INT_EN_FBE */
72269  uint32_t ere : 1; /* ALT_EMAC_DMA_INT_EN_ERE */
72270  uint32_t aie : 1; /* ALT_EMAC_DMA_INT_EN_AIE */
72271  uint32_t nie : 1; /* ALT_EMAC_DMA_INT_EN_NIE */
72272  const uint32_t reserved_31_17 : 15; /* ALT_EMAC_DMA_INT_EN_RSVD_31_17 */
72273 };
72274 
72275 /* The typedef declaration for register ALT_EMAC_DMA_INT_EN. */
72276 typedef volatile struct ALT_EMAC_DMA_INT_EN_s ALT_EMAC_DMA_INT_EN_t;
72277 #endif /* __ASSEMBLY__ */
72278 
72279 /* The reset value of the ALT_EMAC_DMA_INT_EN register. */
72280 #define ALT_EMAC_DMA_INT_EN_RESET 0x00000000
72281 /* The byte offset of the ALT_EMAC_DMA_INT_EN register from the beginning of the component. */
72282 #define ALT_EMAC_DMA_INT_EN_OFST 0x101c
72283 /* The address of the ALT_EMAC_DMA_INT_EN register. */
72284 #define ALT_EMAC_DMA_INT_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_INT_EN_OFST))
72285 
72286 /*
72287  * Register : dmagrp_missed_frame_and_buffer_overflow_counter
72288  *
72289  * <b>Register 8 (Missed Frame and Buffer Overflow Counter Register) </b>
72290  *
72291  * The DMA maintains two counters to track the number of frames missed during
72292  * reception. This register reports the current value of the counter. The counter
72293  * is used for diagnostic purposes. Bits[15:0] indicate missed frames because of
72294  * the host buffer being unavailable. Bits[27:17] indicate missed frames because of
72295  * buffer overflow conditions (MTL and MAC) and runt frames (good frames of less
72296  * than 64 bytes) dropped by the MTL.
72297  *
72298  * Register Layout
72299  *
72300  * Bits | Access | Reset | Description
72301  * :--------|:-------|:------|:------------------------------------------
72302  * [15:0] | R | 0x0 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT
72303  * [16] | R | 0x0 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF
72304  * [27:17] | R | 0x0 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT
72305  * [28] | R | 0x0 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF
72306  * [31:29] | R | 0x0 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29
72307  *
72308  */
72309 /*
72310  * Field : misfrmcnt
72311  *
72312  * Missed Frame Counter
72313  *
72314  * This field indicates the number of frames missed by the controller because of
72315  * the Host Receive Buffer being unavailable. This counter is incremented each time
72316  * the DMA discards an incoming frame. The counter is cleared when this register is
72317  * read with mci_be_i[0] at 1'b1.
72318  *
72319  * Field Access Macros:
72320  *
72321  */
72322 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field. */
72323 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_LSB 0
72324 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field. */
72325 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_MSB 15
72326 /* The width in bits of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field. */
72327 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_WIDTH 16
72328 /* The mask used to set the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field value. */
72329 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_SET_MSK 0x0000ffff
72330 /* The mask used to clear the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field value. */
72331 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_CLR_MSK 0xffff0000
72332 /* The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field. */
72333 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_RESET 0x0
72334 /* Extracts the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT field value from a register. */
72335 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_GET(value) (((value) & 0x0000ffff) >> 0)
72336 /* Produces a ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field value suitable for setting the register. */
72337 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_SET(value) (((value) << 0) & 0x0000ffff)
72338 
72339 /*
72340  * Field : miscntovf
72341  *
72342  * Overflow Bit for Missed Frame Counter
72343  *
72344  * This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, that is,
72345  * the DMA discards an incoming frame because of the Host Receive Buffer being
72346  * unavailable with the missed frame counter at maximum value. In such a scenario,
72347  * the Missed frame counter is reset to all-zeros and this bit indicates that the
72348  * rollover happened.
72349  *
72350  * Field Access Macros:
72351  *
72352  */
72353 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field. */
72354 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_LSB 16
72355 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field. */
72356 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_MSB 16
72357 /* The width in bits of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field. */
72358 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_WIDTH 1
72359 /* The mask used to set the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field value. */
72360 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_SET_MSK 0x00010000
72361 /* The mask used to clear the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field value. */
72362 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_CLR_MSK 0xfffeffff
72363 /* The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field. */
72364 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_RESET 0x0
72365 /* Extracts the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF field value from a register. */
72366 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_GET(value) (((value) & 0x00010000) >> 16)
72367 /* Produces a ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field value suitable for setting the register. */
72368 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_SET(value) (((value) << 16) & 0x00010000)
72369 
72370 /*
72371  * Field : ovffrmcnt
72372  *
72373  * Overflow Frame Counter
72374  *
72375  * This field indicates the number of frames missed by the application. This
72376  * counter is incremented each time the MTL FIFO overflows. The counter is cleared
72377  * when this register is read with mci_be_i[2] at 1'b1.
72378  *
72379  * Field Access Macros:
72380  *
72381  */
72382 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field. */
72383 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_LSB 17
72384 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field. */
72385 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_MSB 27
72386 /* The width in bits of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field. */
72387 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_WIDTH 11
72388 /* The mask used to set the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field value. */
72389 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_SET_MSK 0x0ffe0000
72390 /* The mask used to clear the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field value. */
72391 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_CLR_MSK 0xf001ffff
72392 /* The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field. */
72393 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_RESET 0x0
72394 /* Extracts the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT field value from a register. */
72395 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_GET(value) (((value) & 0x0ffe0000) >> 17)
72396 /* Produces a ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field value suitable for setting the register. */
72397 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_SET(value) (((value) << 17) & 0x0ffe0000)
72398 
72399 /*
72400  * Field : ovfcntovf
72401  *
72402  * Overflow Bit for FIFO Overflow Counter
72403  *
72404  * This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows,
72405  * that is, the Rx FIFO overflows with the overflow frame counter at maximum value.
72406  * In such a scenario, the overflow frame counter is reset to all-zeros and this
72407  * bit indicates that the rollover happened.
72408  *
72409  * Field Access Macros:
72410  *
72411  */
72412 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field. */
72413 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_LSB 28
72414 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field. */
72415 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_MSB 28
72416 /* The width in bits of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field. */
72417 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_WIDTH 1
72418 /* The mask used to set the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field value. */
72419 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_SET_MSK 0x10000000
72420 /* The mask used to clear the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field value. */
72421 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_CLR_MSK 0xefffffff
72422 /* The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field. */
72423 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_RESET 0x0
72424 /* Extracts the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF field value from a register. */
72425 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_GET(value) (((value) & 0x10000000) >> 28)
72426 /* Produces a ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field value suitable for setting the register. */
72427 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_SET(value) (((value) << 28) & 0x10000000)
72428 
72429 /*
72430  * Field : reserved_31_29
72431  *
72432  * Reserved
72433  *
72434  * Field Access Macros:
72435  *
72436  */
72437 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29 register field. */
72438 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_LSB 29
72439 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29 register field. */
72440 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_MSB 31
72441 /* The width in bits of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29 register field. */
72442 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_WIDTH 3
72443 /* The mask used to set the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29 register field value. */
72444 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_SET_MSK 0xe0000000
72445 /* The mask used to clear the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29 register field value. */
72446 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_CLR_MSK 0x1fffffff
72447 /* The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29 register field. */
72448 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_RESET 0x0
72449 /* Extracts the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29 field value from a register. */
72450 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_GET(value) (((value) & 0xe0000000) >> 29)
72451 /* Produces a ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29 register field value suitable for setting the register. */
72452 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_SET(value) (((value) << 29) & 0xe0000000)
72453 
72454 #ifndef __ASSEMBLY__
72455 /*
72456  * WARNING: The C register and register group struct declarations are provided for
72457  * convenience and illustrative purposes. They should, however, be used with
72458  * caution as the C language standard provides no guarantees about the alignment or
72459  * atomicity of device memory accesses. The recommended practice for writing
72460  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
72461  * alt_write_word() functions.
72462  *
72463  * The struct declaration for register ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR.
72464  */
72465 struct ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_s
72466 {
72467  const uint32_t misfrmcnt : 16; /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT */
72468  const uint32_t miscntovf : 1; /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF */
72469  const uint32_t ovffrmcnt : 11; /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT */
72470  const uint32_t ovfcntovf : 1; /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF */
72471  const uint32_t reserved_31_29 : 3; /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29 */
72472 };
72473 
72474 /* The typedef declaration for register ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR. */
72475 typedef volatile struct ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_s ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_t;
72476 #endif /* __ASSEMBLY__ */
72477 
72478 /* The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR register. */
72479 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RESET 0x00000000
72480 /* The byte offset of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR register from the beginning of the component. */
72481 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OFST 0x1020
72482 /* The address of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR register. */
72483 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OFST))
72484 
72485 /*
72486  * Register : dmagrp_receive_interrupt_watchdog_timer
72487  *
72488  * <b> Register 9 (Receive Interrupt Watchdog Timer Register) </b>
72489  *
72490  * This register, when written with non-zero value, enables the watchdog timer for
72491  * the Receive Interrupt (Bit 6) of Register 5 (Status Register)
72492  *
72493  * Register Layout
72494  *
72495  * Bits | Access | Reset | Description
72496  * :-------|:-------|:------|:----------------------------------
72497  * [7:0] | RW | 0x0 | ALT_EMAC_DMA_RX_INT_WDT_RIWT
72498  * [31:8] | R | 0x0 | ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8
72499  *
72500  */
72501 /*
72502  * Field : riwt
72503  *
72504  * RI Watchdog Timer Count
72505  *
72506  * This bit indicates the number of system clock cycles multiplied by 256 for which
72507  * the watchdog timer is set. The watchdog timer gets triggered with the programmed
72508  * value after the Rx DMA completes the transfer of a frame for which the RI status
72509  * bit is not set because of the setting in the corresponding descriptor RDES1[31].
72510  * When the watchdog timer runs out, the RI bit is set and the timer is stopped.
72511  * The watchdog timer is reset when the RI bit is set high because of automatic
72512  * setting of RI as per RDES1[31] of any received frame.
72513  *
72514  * Field Access Macros:
72515  *
72516  */
72517 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field. */
72518 #define ALT_EMAC_DMA_RX_INT_WDT_RIWT_LSB 0
72519 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field. */
72520 #define ALT_EMAC_DMA_RX_INT_WDT_RIWT_MSB 7
72521 /* The width in bits of the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field. */
72522 #define ALT_EMAC_DMA_RX_INT_WDT_RIWT_WIDTH 8
72523 /* The mask used to set the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field value. */
72524 #define ALT_EMAC_DMA_RX_INT_WDT_RIWT_SET_MSK 0x000000ff
72525 /* The mask used to clear the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field value. */
72526 #define ALT_EMAC_DMA_RX_INT_WDT_RIWT_CLR_MSK 0xffffff00
72527 /* The reset value of the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field. */
72528 #define ALT_EMAC_DMA_RX_INT_WDT_RIWT_RESET 0x0
72529 /* Extracts the ALT_EMAC_DMA_RX_INT_WDT_RIWT field value from a register. */
72530 #define ALT_EMAC_DMA_RX_INT_WDT_RIWT_GET(value) (((value) & 0x000000ff) >> 0)
72531 /* Produces a ALT_EMAC_DMA_RX_INT_WDT_RIWT register field value suitable for setting the register. */
72532 #define ALT_EMAC_DMA_RX_INT_WDT_RIWT_SET(value) (((value) << 0) & 0x000000ff)
72533 
72534 /*
72535  * Field : reserved_31_8
72536  *
72537  * Reserved
72538  *
72539  * Field Access Macros:
72540  *
72541  */
72542 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8 register field. */
72543 #define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_LSB 8
72544 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8 register field. */
72545 #define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_MSB 31
72546 /* The width in bits of the ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8 register field. */
72547 #define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_WIDTH 24
72548 /* The mask used to set the ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8 register field value. */
72549 #define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_SET_MSK 0xffffff00
72550 /* The mask used to clear the ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8 register field value. */
72551 #define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_CLR_MSK 0x000000ff
72552 /* The reset value of the ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8 register field. */
72553 #define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_RESET 0x0
72554 /* Extracts the ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8 field value from a register. */
72555 #define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_GET(value) (((value) & 0xffffff00) >> 8)
72556 /* Produces a ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8 register field value suitable for setting the register. */
72557 #define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_SET(value) (((value) << 8) & 0xffffff00)
72558 
72559 #ifndef __ASSEMBLY__
72560 /*
72561  * WARNING: The C register and register group struct declarations are provided for
72562  * convenience and illustrative purposes. They should, however, be used with
72563  * caution as the C language standard provides no guarantees about the alignment or
72564  * atomicity of device memory accesses. The recommended practice for writing
72565  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
72566  * alt_write_word() functions.
72567  *
72568  * The struct declaration for register ALT_EMAC_DMA_RX_INT_WDT.
72569  */
72570 struct ALT_EMAC_DMA_RX_INT_WDT_s
72571 {
72572  uint32_t riwt : 8; /* ALT_EMAC_DMA_RX_INT_WDT_RIWT */
72573  const uint32_t reserved_31_8 : 24; /* ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8 */
72574 };
72575 
72576 /* The typedef declaration for register ALT_EMAC_DMA_RX_INT_WDT. */
72577 typedef volatile struct ALT_EMAC_DMA_RX_INT_WDT_s ALT_EMAC_DMA_RX_INT_WDT_t;
72578 #endif /* __ASSEMBLY__ */
72579 
72580 /* The reset value of the ALT_EMAC_DMA_RX_INT_WDT register. */
72581 #define ALT_EMAC_DMA_RX_INT_WDT_RESET 0x00000000
72582 /* The byte offset of the ALT_EMAC_DMA_RX_INT_WDT register from the beginning of the component. */
72583 #define ALT_EMAC_DMA_RX_INT_WDT_OFST 0x1024
72584 /* The address of the ALT_EMAC_DMA_RX_INT_WDT register. */
72585 #define ALT_EMAC_DMA_RX_INT_WDT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_RX_INT_WDT_OFST))
72586 
72587 /*
72588  * Register : Register 10 (AXI Bus Mode Register) - dmagrp_axi_bus_mode
72589  *
72590  * The AXI Bus Mode Register controls the behavior of the AXI master. It is mainly
72591  * used to control the burst splitting and the number of outstanding requests.
72592  *
72593  * Register Layout
72594  *
72595  * Bits | Access | Reset | Description
72596  * :--------|:-------|:------|:-------------------------------------------
72597  * [0] | R | 0x1 | AXI Undefined Burst Length
72598  * [1] | RW | 0x0 | AXI Burst Length 4
72599  * [2] | RW | 0x0 | AXI Burst Length 8
72600  * [3] | RW | 0x0 | AXI Burst Length 16
72601  * [11:4] | ??? | 0x0 | *UNDEFINED*
72602  * [12] | R | 0x0 | Address-Aligned Beats
72603  * [13] | RW | 0x0 | ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE
72604  * [15:14] | ??? | 0x0 | *UNDEFINED*
72605  * [19:16] | RW | 0x1 | AXI Maximum Read OutStanding Request Limit
72606  * [23:20] | RW | 0x1 | ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT
72607  * [29:24] | ??? | 0x0 | *UNDEFINED*
72608  * [30] | RW | 0x0 | ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM
72609  * [31] | RW | 0x0 | Enable Low Power Interface (LPI)
72610  *
72611  */
72612 /*
72613  * Field : AXI Undefined Burst Length - undefined
72614  *
72615  * This bit is read-only bit and indicates the complement (invert) value of Bit 16
72616  * (FB) in Register 0 (Bus Mode Register[16]).
72617  *
72618  * * When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length
72619  * equal to or below the maximum allowed burst length programmed in Bits[7:1].
72620  *
72621  * * When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst
72622  * lengths as indicated by BLEN16, BLEN8, or BLEN4, or a burst length of 1.
72623  *
72624  * Field Enumeration Values:
72625  *
72626  * Enum | Value | Description
72627  * :------------------------------------------|:------|:------------
72628  * ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_E_DISD | 0x0 |
72629  * ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_E_END | 0x1 |
72630  *
72631  * Field Access Macros:
72632  *
72633  */
72634 /*
72635  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED
72636  *
72637  */
72638 #define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_E_DISD 0x0
72639 /*
72640  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED
72641  *
72642  */
72643 #define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_E_END 0x1
72644 
72645 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field. */
72646 #define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_LSB 0
72647 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field. */
72648 #define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_MSB 0
72649 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field. */
72650 #define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_WIDTH 1
72651 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field value. */
72652 #define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_SET_MSK 0x00000001
72653 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field value. */
72654 #define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_CLR_MSK 0xfffffffe
72655 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field. */
72656 #define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_RESET 0x1
72657 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED field value from a register. */
72658 #define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_GET(value) (((value) & 0x00000001) >> 0)
72659 /* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field value suitable for setting the register. */
72660 #define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_SET(value) (((value) << 0) & 0x00000001)
72661 
72662 /*
72663  * Field : AXI Burst Length 4 - blen4
72664  *
72665  * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4
72666  * on the AXI Master interface.
72667  *
72668  * Setting this bit has no effect when UNDEFINED is set to 1.
72669  *
72670  * Field Enumeration Values:
72671  *
72672  * Enum | Value | Description
72673  * :--------------------------------------|:------|:------------
72674  * ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_E_DISD | 0x0 |
72675  * ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_E_END | 0x1 |
72676  *
72677  * Field Access Macros:
72678  *
72679  */
72680 /*
72681  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4
72682  *
72683  */
72684 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_E_DISD 0x0
72685 /*
72686  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4
72687  *
72688  */
72689 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_E_END 0x1
72690 
72691 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field. */
72692 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_LSB 1
72693 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field. */
72694 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_MSB 1
72695 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field. */
72696 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_WIDTH 1
72697 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field value. */
72698 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_SET_MSK 0x00000002
72699 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field value. */
72700 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_CLR_MSK 0xfffffffd
72701 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field. */
72702 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_RESET 0x0
72703 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 field value from a register. */
72704 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_GET(value) (((value) & 0x00000002) >> 1)
72705 /* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field value suitable for setting the register. */
72706 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_SET(value) (((value) << 1) & 0x00000002)
72707 
72708 /*
72709  * Field : AXI Burst Length 8 - blen8
72710  *
72711  * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8
72712  * on the AXI Master interface.
72713  *
72714  * Setting this bit has no effect when UNDEFINED is set to 1.
72715  *
72716  * Field Enumeration Values:
72717  *
72718  * Enum | Value | Description
72719  * :--------------------------------------|:------|:------------
72720  * ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_E_DISD | 0x0 |
72721  * ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_E_END | 0x1 |
72722  *
72723  * Field Access Macros:
72724  *
72725  */
72726 /*
72727  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8
72728  *
72729  */
72730 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_E_DISD 0x0
72731 /*
72732  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8
72733  *
72734  */
72735 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_E_END 0x1
72736 
72737 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field. */
72738 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_LSB 2
72739 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field. */
72740 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_MSB 2
72741 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field. */
72742 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_WIDTH 1
72743 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field value. */
72744 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_SET_MSK 0x00000004
72745 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field value. */
72746 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_CLR_MSK 0xfffffffb
72747 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field. */
72748 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_RESET 0x0
72749 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 field value from a register. */
72750 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_GET(value) (((value) & 0x00000004) >> 2)
72751 /* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field value suitable for setting the register. */
72752 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_SET(value) (((value) << 2) & 0x00000004)
72753 
72754 /*
72755  * Field : AXI Burst Length 16 - blen16
72756  *
72757  * When this bit is set to 1 or UNDEFINED is set to 1, the GMAC-AXI is allowed to
72758  * select a burst length of 16 on the AXI Master interface.
72759  *
72760  * Field Enumeration Values:
72761  *
72762  * Enum | Value | Description
72763  * :---------------------------------------|:------|:------------
72764  * ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_E_DISD | 0x0 |
72765  * ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_E_END | 0x1 |
72766  *
72767  * Field Access Macros:
72768  *
72769  */
72770 /*
72771  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16
72772  *
72773  */
72774 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_E_DISD 0x0
72775 /*
72776  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16
72777  *
72778  */
72779 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_E_END 0x1
72780 
72781 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field. */
72782 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_LSB 3
72783 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field. */
72784 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_MSB 3
72785 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field. */
72786 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_WIDTH 1
72787 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field value. */
72788 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_SET_MSK 0x00000008
72789 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field value. */
72790 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_CLR_MSK 0xfffffff7
72791 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field. */
72792 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_RESET 0x0
72793 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 field value from a register. */
72794 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_GET(value) (((value) & 0x00000008) >> 3)
72795 /* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field value suitable for setting the register. */
72796 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_SET(value) (((value) << 3) & 0x00000008)
72797 
72798 /*
72799  * Field : Address-Aligned Beats - axi_aal
72800  *
72801  * This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode
72802  * Register).
72803  *
72804  * When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers
72805  * on both read and write channels.
72806  *
72807  * Field Enumeration Values:
72808  *
72809  * Enum | Value | Description
72810  * :----------------------------------------|:------|:------------
72811  * ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_E_DISD | 0x0 |
72812  * ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_E_END | 0x1 |
72813  *
72814  * Field Access Macros:
72815  *
72816  */
72817 /*
72818  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL
72819  *
72820  */
72821 #define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_E_DISD 0x0
72822 /*
72823  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL
72824  *
72825  */
72826 #define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_E_END 0x1
72827 
72828 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field. */
72829 #define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_LSB 12
72830 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field. */
72831 #define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_MSB 12
72832 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field. */
72833 #define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_WIDTH 1
72834 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field value. */
72835 #define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_SET_MSK 0x00001000
72836 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field value. */
72837 #define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_CLR_MSK 0xffffefff
72838 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field. */
72839 #define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_RESET 0x0
72840 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL field value from a register. */
72841 #define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_GET(value) (((value) & 0x00001000) >> 12)
72842 /* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field value suitable for setting the register. */
72843 #define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_SET(value) (((value) << 12) & 0x00001000)
72844 
72845 /*
72846  * Field : onekbbe
72847  *
72848  * 1 KB Boundary Crossing Enable for the GMAC-AXI Master
72849  *
72850  * When set, the GMAC-AXI Master performs burst transfers that do not cross 1 KB
72851  * boundary. When reset, the GMAC-AXI Master performs burst transfers that do not
72852  * cross 4 KB boundary.
72853  *
72854  * Field Enumeration Values:
72855  *
72856  * Enum | Value | Description
72857  * :---------------------------------------------------|:------|:------------
72858  * ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_E_FOUR_K_BOUNDARY | 0x0 |
72859  * ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_E_ONE_K_BOUNDARY | 0x1 |
72860  *
72861  * Field Access Macros:
72862  *
72863  */
72864 /*
72865  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE
72866  *
72867  */
72868 #define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_E_FOUR_K_BOUNDARY 0x0
72869 /*
72870  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE
72871  *
72872  */
72873 #define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_E_ONE_K_BOUNDARY 0x1
72874 
72875 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field. */
72876 #define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_LSB 13
72877 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field. */
72878 #define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_MSB 13
72879 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field. */
72880 #define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_WIDTH 1
72881 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field value. */
72882 #define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_SET_MSK 0x00002000
72883 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field value. */
72884 #define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_CLR_MSK 0xffffdfff
72885 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field. */
72886 #define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_RESET 0x0
72887 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE field value from a register. */
72888 #define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_GET(value) (((value) & 0x00002000) >> 13)
72889 /* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field value suitable for setting the register. */
72890 #define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_SET(value) (((value) << 13) & 0x00002000)
72891 
72892 /*
72893  * Field : AXI Maximum Read OutStanding Request Limit - rd_osr_lmt
72894  *
72895  * This value limits the maximum outstanding request on the AXI read interface.
72896  *
72897  * Maximum outstanding requests = RD_OSR_LMT+1
72898  *
72899  * Field Access Macros:
72900  *
72901  */
72902 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field. */
72903 #define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_LSB 16
72904 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field. */
72905 #define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_MSB 19
72906 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field. */
72907 #define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_WIDTH 4
72908 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field value. */
72909 #define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_SET_MSK 0x000f0000
72910 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field value. */
72911 #define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_CLR_MSK 0xfff0ffff
72912 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field. */
72913 #define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_RESET 0x1
72914 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT field value from a register. */
72915 #define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_GET(value) (((value) & 0x000f0000) >> 16)
72916 /* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field value suitable for setting the register. */
72917 #define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_SET(value) (((value) << 16) & 0x000f0000)
72918 
72919 /*
72920  * Field : wr_osr_lmt
72921  *
72922  * AXI Maximum Write OutStanding Request Limit
72923  *
72924  * Field Access Macros:
72925  *
72926  */
72927 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field. */
72928 #define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_LSB 20
72929 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field. */
72930 #define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_MSB 23
72931 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field. */
72932 #define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_WIDTH 4
72933 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field value. */
72934 #define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_SET_MSK 0x00f00000
72935 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field value. */
72936 #define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_CLR_MSK 0xff0fffff
72937 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field. */
72938 #define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_RESET 0x1
72939 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT field value from a register. */
72940 #define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_GET(value) (((value) & 0x00f00000) >> 20)
72941 /* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field value suitable for setting the register. */
72942 #define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_SET(value) (((value) << 20) & 0x00f00000)
72943 
72944 /*
72945  * Field : lpi_xit_frm
72946  *
72947  * When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only
72948  * when the Magic Packet or Remote Wake Up Packet is received.
72949  *
72950  * When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any
72951  * frame is received.
72952  *
72953  * Field Enumeration Values:
72954  *
72955  * Enum | Value | Description
72956  * :--------------------------------------------|:------|:------------
72957  * ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_E_DISD | 0x0 |
72958  * ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_E_END | 0x1 |
72959  *
72960  * Field Access Macros:
72961  *
72962  */
72963 /*
72964  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM
72965  *
72966  */
72967 #define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_E_DISD 0x0
72968 /*
72969  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM
72970  *
72971  */
72972 #define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_E_END 0x1
72973 
72974 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field. */
72975 #define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_LSB 30
72976 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field. */
72977 #define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_MSB 30
72978 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field. */
72979 #define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_WIDTH 1
72980 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field value. */
72981 #define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_SET_MSK 0x40000000
72982 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field value. */
72983 #define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_CLR_MSK 0xbfffffff
72984 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field. */
72985 #define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_RESET 0x0
72986 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM field value from a register. */
72987 #define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_GET(value) (((value) & 0x40000000) >> 30)
72988 /* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field value suitable for setting the register. */
72989 #define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_SET(value) (((value) << 30) & 0x40000000)
72990 
72991 /*
72992  * Field : Enable Low Power Interface (LPI) - en_lpi
72993  *
72994  * When set to 1, this bit enables the LPI mode supported by the AXI master and
72995  * accepts the LPI request from the AXI System Clock controller.
72996  *
72997  * When set to 0, this bit disables the LPI mode and always denies the LPI request
72998  * from the AXI System Clock controller.
72999  *
73000  * Field Enumeration Values:
73001  *
73002  * Enum | Value | Description
73003  * :---------------------------------------|:------|:------------
73004  * ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_E_DISD | 0x0 |
73005  * ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_E_END | 0x1 |
73006  *
73007  * Field Access Macros:
73008  *
73009  */
73010 /*
73011  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI
73012  *
73013  */
73014 #define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_E_DISD 0x0
73015 /*
73016  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI
73017  *
73018  */
73019 #define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_E_END 0x1
73020 
73021 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field. */
73022 #define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_LSB 31
73023 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field. */
73024 #define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_MSB 31
73025 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field. */
73026 #define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_WIDTH 1
73027 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field value. */
73028 #define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_SET_MSK 0x80000000
73029 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field value. */
73030 #define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_CLR_MSK 0x7fffffff
73031 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field. */
73032 #define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_RESET 0x0
73033 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI field value from a register. */
73034 #define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_GET(value) (((value) & 0x80000000) >> 31)
73035 /* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field value suitable for setting the register. */
73036 #define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_SET(value) (((value) << 31) & 0x80000000)
73037 
73038 #ifndef __ASSEMBLY__
73039 /*
73040  * WARNING: The C register and register group struct declarations are provided for
73041  * convenience and illustrative purposes. They should, however, be used with
73042  * caution as the C language standard provides no guarantees about the alignment or
73043  * atomicity of device memory accesses. The recommended practice for writing
73044  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
73045  * alt_write_word() functions.
73046  *
73047  * The struct declaration for register ALT_EMAC_DMA_AXI_BUS_MOD.
73048  */
73049 struct ALT_EMAC_DMA_AXI_BUS_MOD_s
73050 {
73051  const uint32_t undefined : 1; /* AXI Undefined Burst Length */
73052  uint32_t blen4 : 1; /* AXI Burst Length 4 */
73053  uint32_t blen8 : 1; /* AXI Burst Length 8 */
73054  uint32_t blen16 : 1; /* AXI Burst Length 16 */
73055  uint32_t : 8; /* *UNDEFINED* */
73056  const uint32_t axi_aal : 1; /* Address-Aligned Beats */
73057  uint32_t onekbbe : 1; /* ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE */
73058  uint32_t : 2; /* *UNDEFINED* */
73059  uint32_t rd_osr_lmt : 4; /* AXI Maximum Read OutStanding Request Limit */
73060  uint32_t wr_osr_lmt : 4; /* ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT */
73061  uint32_t : 6; /* *UNDEFINED* */
73062  uint32_t lpi_xit_frm : 1; /* ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM */
73063  uint32_t en_lpi : 1; /* Enable Low Power Interface (LPI) */
73064 };
73065 
73066 /* The typedef declaration for register ALT_EMAC_DMA_AXI_BUS_MOD. */
73067 typedef volatile struct ALT_EMAC_DMA_AXI_BUS_MOD_s ALT_EMAC_DMA_AXI_BUS_MOD_t;
73068 #endif /* __ASSEMBLY__ */
73069 
73070 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD register. */
73071 #define ALT_EMAC_DMA_AXI_BUS_MOD_RESET 0x00110001
73072 /* The byte offset of the ALT_EMAC_DMA_AXI_BUS_MOD register from the beginning of the component. */
73073 #define ALT_EMAC_DMA_AXI_BUS_MOD_OFST 0x1028
73074 /* The address of the ALT_EMAC_DMA_AXI_BUS_MOD register. */
73075 #define ALT_EMAC_DMA_AXI_BUS_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_AXI_BUS_MOD_OFST))
73076 
73077 /*
73078  * Register : dmagrp_ahb_or_axi_status
73079  *
73080  * <b> Register 11 (AHB or AXI Status Register) </b>
73081  *
73082  * This register provides the active status of the AHB master interface or AXI
73083  * interface's read and write channels. This register is present and valid only in
73084  * the GMAC-AHB and GMAC-AXI configurations. This register is useful for debugging
73085  * purposes. In addition, this register is valid only in the Channel 0 DMA when
73086  * multiple channels are present in the AV mode.
73087  *
73088  * Register Layout
73089  *
73090  * Bits | Access | Reset | Description
73091  * :-------|:-------|:------|:---------------------------------------
73092  * [0] | R | 0x0 | ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS
73093  * [1] | R | 0x0 | ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS
73094  * [31:2] | R | 0x0 | ALT_EMAC_DMA_AHB_OR_AXI_STAT_RSVD_31_2
73095  *
73096  */
73097 /*
73098  * Field : axwhsts
73099  *
73100  * AXI Master Write Channel or AHB Master Status
73101  *
73102  * When high, it indicates that AXI Master's write channel is active and
73103  * transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration,
73104  * it indicates that the AHB master interface FSMs are in the non-idle state.
73105  *
73106  * Field Access Macros:
73107  *
73108  */
73109 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field. */
73110 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_LSB 0
73111 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field. */
73112 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_MSB 0
73113 /* The width in bits of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field. */
73114 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_WIDTH 1
73115 /* The mask used to set the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field value. */
73116 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_SET_MSK 0x00000001
73117 /* The mask used to clear the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field value. */
73118 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_CLR_MSK 0xfffffffe
73119 /* The reset value of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field. */
73120 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_RESET 0x0
73121 /* Extracts the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS field value from a register. */
73122 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_GET(value) (((value) & 0x00000001) >> 0)
73123 /* Produces a ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field value suitable for setting the register. */
73124 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_SET(value) (((value) << 0) & 0x00000001)
73125 
73126 /*
73127  * Field : axirdsts
73128  *
73129  * AXI Master Read Channel Status
73130  *
73131  * When high, it indicates that AXI Master's read channel is active and
73132  * transferring data.
73133  *
73134  * Field Access Macros:
73135  *
73136  */
73137 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field. */
73138 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_LSB 1
73139 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field. */
73140 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_MSB 1
73141 /* The width in bits of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field. */
73142 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_WIDTH 1
73143 /* The mask used to set the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field value. */
73144 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_SET_MSK 0x00000002
73145 /* The mask used to clear the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field value. */
73146 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_CLR_MSK 0xfffffffd
73147 /* The reset value of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field. */
73148 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_RESET 0x0
73149 /* Extracts the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS field value from a register. */
73150 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_GET(value) (((value) & 0x00000002) >> 1)
73151 /* Produces a ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field value suitable for setting the register. */
73152 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_SET(value) (((value) << 1) & 0x00000002)
73153 
73154 /*
73155  * Field : reserved_31_2
73156  *
73157  * Reserved
73158  *
73159  * Field Access Macros:
73160  *
73161  */
73162 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_RSVD_31_2 register field. */
73163 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_RSVD_31_2_LSB 2
73164 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_RSVD_31_2 register field. */
73165 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_RSVD_31_2_MSB 31
73166 /* The width in bits of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_RSVD_31_2 register field. */
73167 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_RSVD_31_2_WIDTH 30
73168 /* The mask used to set the ALT_EMAC_DMA_AHB_OR_AXI_STAT_RSVD_31_2 register field value. */
73169 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_RSVD_31_2_SET_MSK 0xfffffffc
73170 /* The mask used to clear the ALT_EMAC_DMA_AHB_OR_AXI_STAT_RSVD_31_2 register field value. */
73171 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_RSVD_31_2_CLR_MSK 0x00000003
73172 /* The reset value of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_RSVD_31_2 register field. */
73173 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_RSVD_31_2_RESET 0x0
73174 /* Extracts the ALT_EMAC_DMA_AHB_OR_AXI_STAT_RSVD_31_2 field value from a register. */
73175 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_RSVD_31_2_GET(value) (((value) & 0xfffffffc) >> 2)
73176 /* Produces a ALT_EMAC_DMA_AHB_OR_AXI_STAT_RSVD_31_2 register field value suitable for setting the register. */
73177 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_RSVD_31_2_SET(value) (((value) << 2) & 0xfffffffc)
73178 
73179 #ifndef __ASSEMBLY__
73180 /*
73181  * WARNING: The C register and register group struct declarations are provided for
73182  * convenience and illustrative purposes. They should, however, be used with
73183  * caution as the C language standard provides no guarantees about the alignment or
73184  * atomicity of device memory accesses. The recommended practice for writing
73185  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
73186  * alt_write_word() functions.
73187  *
73188  * The struct declaration for register ALT_EMAC_DMA_AHB_OR_AXI_STAT.
73189  */
73190 struct ALT_EMAC_DMA_AHB_OR_AXI_STAT_s
73191 {
73192  const uint32_t axwhsts : 1; /* ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS */
73193  const uint32_t axirdsts : 1; /* ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS */
73194  const uint32_t reserved_31_2 : 30; /* ALT_EMAC_DMA_AHB_OR_AXI_STAT_RSVD_31_2 */
73195 };
73196 
73197 /* The typedef declaration for register ALT_EMAC_DMA_AHB_OR_AXI_STAT. */
73198 typedef volatile struct ALT_EMAC_DMA_AHB_OR_AXI_STAT_s ALT_EMAC_DMA_AHB_OR_AXI_STAT_t;
73199 #endif /* __ASSEMBLY__ */
73200 
73201 /* The reset value of the ALT_EMAC_DMA_AHB_OR_AXI_STAT register. */
73202 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_RESET 0x00000000
73203 /* The byte offset of the ALT_EMAC_DMA_AHB_OR_AXI_STAT register from the beginning of the component. */
73204 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_OFST 0x102c
73205 /* The address of the ALT_EMAC_DMA_AHB_OR_AXI_STAT register. */
73206 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_AHB_OR_AXI_STAT_OFST))
73207 
73208 /*
73209  * Register : dmagrp_current_host_transmit_descriptor
73210  *
73211  * <b> Register 18 (Current Host Transmit Descriptor Register) </b>
73212  *
73213  * The Current Host Transmit Descriptor register points to the start address of the
73214  * current Transmit Descriptor read by the DMA.
73215  *
73216  * Register Layout
73217  *
73218  * Bits | Access | Reset | Description
73219  * :-------|:-------|:------|:------------------------------------------
73220  * [31:0] | R | 0x0 | ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR
73221  *
73222  */
73223 /*
73224  * Field : curtdesaptr
73225  *
73226  * Host Transmit Descriptor Address Pointer
73227  *
73228  * Cleared on Reset. Pointer updated by the DMA during operation.
73229  *
73230  * Field Access Macros:
73231  *
73232  */
73233 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field. */
73234 #define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_LSB 0
73235 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field. */
73236 #define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_MSB 31
73237 /* The width in bits of the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field. */
73238 #define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_WIDTH 32
73239 /* The mask used to set the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field value. */
73240 #define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_SET_MSK 0xffffffff
73241 /* The mask used to clear the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field value. */
73242 #define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_CLR_MSK 0x00000000
73243 /* The reset value of the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field. */
73244 #define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_RESET 0x0
73245 /* Extracts the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR field value from a register. */
73246 #define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_GET(value) (((value) & 0xffffffff) >> 0)
73247 /* Produces a ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field value suitable for setting the register. */
73248 #define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_SET(value) (((value) << 0) & 0xffffffff)
73249 
73250 #ifndef __ASSEMBLY__
73251 /*
73252  * WARNING: The C register and register group struct declarations are provided for
73253  * convenience and illustrative purposes. They should, however, be used with
73254  * caution as the C language standard provides no guarantees about the alignment or
73255  * atomicity of device memory accesses. The recommended practice for writing
73256  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
73257  * alt_write_word() functions.
73258  *
73259  * The struct declaration for register ALT_EMAC_DMA_CUR_HOST_TX_DESC.
73260  */
73261 struct ALT_EMAC_DMA_CUR_HOST_TX_DESC_s
73262 {
73263  const uint32_t curtdesaptr : 32; /* ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR */
73264 };
73265 
73266 /* The typedef declaration for register ALT_EMAC_DMA_CUR_HOST_TX_DESC. */
73267 typedef volatile struct ALT_EMAC_DMA_CUR_HOST_TX_DESC_s ALT_EMAC_DMA_CUR_HOST_TX_DESC_t;
73268 #endif /* __ASSEMBLY__ */
73269 
73270 /* The reset value of the ALT_EMAC_DMA_CUR_HOST_TX_DESC register. */
73271 #define ALT_EMAC_DMA_CUR_HOST_TX_DESC_RESET 0x00000000
73272 /* The byte offset of the ALT_EMAC_DMA_CUR_HOST_TX_DESC register from the beginning of the component. */
73273 #define ALT_EMAC_DMA_CUR_HOST_TX_DESC_OFST 0x1048
73274 /* The address of the ALT_EMAC_DMA_CUR_HOST_TX_DESC register. */
73275 #define ALT_EMAC_DMA_CUR_HOST_TX_DESC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CUR_HOST_TX_DESC_OFST))
73276 
73277 /*
73278  * Register : dmagrp_current_host_receive_descriptor
73279  *
73280  * <b> Register 19 (Current Host Receive Descriptor Register) </b>
73281  *
73282  * The Current Host Receive Descriptor register points to the start address of the
73283  * current Receive Descriptor read by the DMA.
73284  *
73285  * Register Layout
73286  *
73287  * Bits | Access | Reset | Description
73288  * :-------|:-------|:------|:------------------------------------------
73289  * [31:0] | R | 0x0 | ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR
73290  *
73291  */
73292 /*
73293  * Field : currdesaptr
73294  *
73295  * Host Receive Descriptor Address Pointer
73296  *
73297  * Cleared on Reset. Pointer updated by the DMA during operation.
73298  *
73299  * Field Access Macros:
73300  *
73301  */
73302 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field. */
73303 #define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_LSB 0
73304 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field. */
73305 #define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_MSB 31
73306 /* The width in bits of the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field. */
73307 #define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_WIDTH 32
73308 /* The mask used to set the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field value. */
73309 #define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_SET_MSK 0xffffffff
73310 /* The mask used to clear the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field value. */
73311 #define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_CLR_MSK 0x00000000
73312 /* The reset value of the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field. */
73313 #define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_RESET 0x0
73314 /* Extracts the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR field value from a register. */
73315 #define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_GET(value) (((value) & 0xffffffff) >> 0)
73316 /* Produces a ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field value suitable for setting the register. */
73317 #define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_SET(value) (((value) << 0) & 0xffffffff)
73318 
73319 #ifndef __ASSEMBLY__
73320 /*
73321  * WARNING: The C register and register group struct declarations are provided for
73322  * convenience and illustrative purposes. They should, however, be used with
73323  * caution as the C language standard provides no guarantees about the alignment or
73324  * atomicity of device memory accesses. The recommended practice for writing
73325  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
73326  * alt_write_word() functions.
73327  *
73328  * The struct declaration for register ALT_EMAC_DMA_CUR_HOST_RX_DESC.
73329  */
73330 struct ALT_EMAC_DMA_CUR_HOST_RX_DESC_s
73331 {
73332  const uint32_t currdesaptr : 32; /* ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR */
73333 };
73334 
73335 /* The typedef declaration for register ALT_EMAC_DMA_CUR_HOST_RX_DESC. */
73336 typedef volatile struct ALT_EMAC_DMA_CUR_HOST_RX_DESC_s ALT_EMAC_DMA_CUR_HOST_RX_DESC_t;
73337 #endif /* __ASSEMBLY__ */
73338 
73339 /* The reset value of the ALT_EMAC_DMA_CUR_HOST_RX_DESC register. */
73340 #define ALT_EMAC_DMA_CUR_HOST_RX_DESC_RESET 0x00000000
73341 /* The byte offset of the ALT_EMAC_DMA_CUR_HOST_RX_DESC register from the beginning of the component. */
73342 #define ALT_EMAC_DMA_CUR_HOST_RX_DESC_OFST 0x104c
73343 /* The address of the ALT_EMAC_DMA_CUR_HOST_RX_DESC register. */
73344 #define ALT_EMAC_DMA_CUR_HOST_RX_DESC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CUR_HOST_RX_DESC_OFST))
73345 
73346 /*
73347  * Register : dmagrp_current_host_transmit_buffer_address
73348  *
73349  * <b> Register 20 (Current Host Transmit Buffer Address Register) </b>
73350  *
73351  * The Current Host Transmit Buffer Address register points to the current Transmit
73352  * Buffer Address being read by the DMA.
73353  *
73354  * Register Layout
73355  *
73356  * Bits | Access | Reset | Description
73357  * :-------|:-------|:------|:----------------------------------------------
73358  * [31:0] | R | 0x0 | ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR
73359  *
73360  */
73361 /*
73362  * Field : curtbufaptr
73363  *
73364  * Host Transmit Buffer Address Pointer
73365  *
73366  * Cleared on Reset. Pointer updated by the DMA during operation.
73367  *
73368  * Field Access Macros:
73369  *
73370  */
73371 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field. */
73372 #define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_LSB 0
73373 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field. */
73374 #define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_MSB 31
73375 /* The width in bits of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field. */
73376 #define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_WIDTH 32
73377 /* The mask used to set the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field value. */
73378 #define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_SET_MSK 0xffffffff
73379 /* The mask used to clear the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field value. */
73380 #define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_CLR_MSK 0x00000000
73381 /* The reset value of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field. */
73382 #define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_RESET 0x0
73383 /* Extracts the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR field value from a register. */
73384 #define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_GET(value) (((value) & 0xffffffff) >> 0)
73385 /* Produces a ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field value suitable for setting the register. */
73386 #define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_SET(value) (((value) << 0) & 0xffffffff)
73387 
73388 #ifndef __ASSEMBLY__
73389 /*
73390  * WARNING: The C register and register group struct declarations are provided for
73391  * convenience and illustrative purposes. They should, however, be used with
73392  * caution as the C language standard provides no guarantees about the alignment or
73393  * atomicity of device memory accesses. The recommended practice for writing
73394  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
73395  * alt_write_word() functions.
73396  *
73397  * The struct declaration for register ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR.
73398  */
73399 struct ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_s
73400 {
73401  const uint32_t curtbufaptr : 32; /* ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR */
73402 };
73403 
73404 /* The typedef declaration for register ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR. */
73405 typedef volatile struct ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_s ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_t;
73406 #endif /* __ASSEMBLY__ */
73407 
73408 /* The reset value of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR register. */
73409 #define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_RESET 0x00000000
73410 /* The byte offset of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR register from the beginning of the component. */
73411 #define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_OFST 0x1050
73412 /* The address of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR register. */
73413 #define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_OFST))
73414 
73415 /*
73416  * Register : dmagrp_current_host_receive_buffer_address
73417  *
73418  * <b> Register 21 (Current Host Receive Buffer Address Register) </b>
73419  *
73420  * The Current Host Receive Buffer Address register points to the current Receive
73421  * Buffer address being read by the DMA.
73422  *
73423  * Register Layout
73424  *
73425  * Bits | Access | Reset | Description
73426  * :-------|:-------|:------|:----------------------------------------------
73427  * [31:0] | R | 0x0 | ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR
73428  *
73429  */
73430 /*
73431  * Field : currbufaptr
73432  *
73433  * Host Receive Buffer Address Pointer
73434  *
73435  * Cleared on Reset. Pointer updated by the DMA during operation.
73436  *
73437  * Field Access Macros:
73438  *
73439  */
73440 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field. */
73441 #define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_LSB 0
73442 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field. */
73443 #define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_MSB 31
73444 /* The width in bits of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field. */
73445 #define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_WIDTH 32
73446 /* The mask used to set the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field value. */
73447 #define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_SET_MSK 0xffffffff
73448 /* The mask used to clear the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field value. */
73449 #define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_CLR_MSK 0x00000000
73450 /* The reset value of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field. */
73451 #define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_RESET 0x0
73452 /* Extracts the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR field value from a register. */
73453 #define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_GET(value) (((value) & 0xffffffff) >> 0)
73454 /* Produces a ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field value suitable for setting the register. */
73455 #define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_SET(value) (((value) << 0) & 0xffffffff)
73456 
73457 #ifndef __ASSEMBLY__
73458 /*
73459  * WARNING: The C register and register group struct declarations are provided for
73460  * convenience and illustrative purposes. They should, however, be used with
73461  * caution as the C language standard provides no guarantees about the alignment or
73462  * atomicity of device memory accesses. The recommended practice for writing
73463  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
73464  * alt_write_word() functions.
73465  *
73466  * The struct declaration for register ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR.
73467  */
73468 struct ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_s
73469 {
73470  const uint32_t currbufaptr : 32; /* ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR */
73471 };
73472 
73473 /* The typedef declaration for register ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR. */
73474 typedef volatile struct ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_s ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_t;
73475 #endif /* __ASSEMBLY__ */
73476 
73477 /* The reset value of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR register. */
73478 #define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_RESET 0x00000000
73479 /* The byte offset of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR register from the beginning of the component. */
73480 #define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_OFST 0x1054
73481 /* The address of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR register. */
73482 #define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_OFST))
73483 
73484 /*
73485  * Register : dmagrp_hw_feature
73486  *
73487  * <b> Register 22 (HW Feature Register) </b>
73488  *
73489  * This register indicates the presence of the optional features or functions of
73490  * the DWC_gmac. The software driver can use this register to dynamically enable or
73491  * disable the programs related to the optional blocks.
73492  *
73493  * Note: All bits are set or reset as per the selection of features during the
73494  * DWC_gmac configuration.
73495  *
73496  * Register Layout
73497  *
73498  * Bits | Access | Reset | Description
73499  * :--------|:-------|:------|:-------------------------------------
73500  * [0] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_MIISEL
73501  * [1] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_GMIISEL
73502  * [2] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_HDSEL
73503  * [3] | R | 0x0 | ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN
73504  * [4] | R | 0x0 | ALT_EMAC_DMA_HW_FEATURE_HASHSEL
73505  * [5] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL
73506  * [6] | R | 0x0 | ALT_EMAC_DMA_HW_FEATURE_PCSSEL
73507  * [7] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN
73508  * [8] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_SMASEL
73509  * [9] | R | 0x0 | ALT_EMAC_DMA_HW_FEATURE_RWKSEL
73510  * [10] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_MGKSEL
73511  * [11] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_MMCSEL
73512  * [12] | R | 0x0 | ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL
73513  * [13] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL
73514  * [14] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_EEESEL
73515  * [15] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_AVSEL
73516  * [16] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_TXOESEL
73517  * [17] | R | 0x0 | ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE
73518  * [18] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE
73519  * [19] | R | 0x0 | ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE
73520  * [21:20] | R | 0x0 | ALT_EMAC_DMA_HW_FEATURE_RXCHCNT
73521  * [23:22] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_TXCHCNT
73522  * [24] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL
73523  * [25] | R | 0x0 | ALT_EMAC_DMA_HW_FEATURE_INTTSEN
73524  * [26] | R | 0x0 | ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN
73525  * [27] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_SAVLANINS
73526  * [30:28] | R | 0x0 | ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
73527  * [31] | R | 0x0 | ALT_EMAC_DMA_HW_FEATURE_RSVD_31
73528  *
73529  */
73530 /*
73531  * Field : miisel
73532  *
73533  * 10 or 100 Mbps support
73534  *
73535  * Field Enumeration Values:
73536  *
73537  * Enum | Value | Description
73538  * :--------------------------------------|:------|:------------
73539  * ALT_EMAC_DMA_HW_FEATURE_MIISEL_E_DISD | 0x0 |
73540  * ALT_EMAC_DMA_HW_FEATURE_MIISEL_E_END | 0x1 |
73541  *
73542  * Field Access Macros:
73543  *
73544  */
73545 /*
73546  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MIISEL
73547  *
73548  */
73549 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_E_DISD 0x0
73550 /*
73551  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MIISEL
73552  *
73553  */
73554 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_E_END 0x1
73555 
73556 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field. */
73557 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_LSB 0
73558 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field. */
73559 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_MSB 0
73560 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field. */
73561 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_WIDTH 1
73562 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field value. */
73563 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_SET_MSK 0x00000001
73564 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field value. */
73565 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_CLR_MSK 0xfffffffe
73566 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field. */
73567 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_RESET 0x1
73568 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_MIISEL field value from a register. */
73569 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_GET(value) (((value) & 0x00000001) >> 0)
73570 /* Produces a ALT_EMAC_DMA_HW_FEATURE_MIISEL register field value suitable for setting the register. */
73571 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_SET(value) (((value) << 0) & 0x00000001)
73572 
73573 /*
73574  * Field : gmiisel
73575  *
73576  * 1000 Mbps support
73577  *
73578  * Field Enumeration Values:
73579  *
73580  * Enum | Value | Description
73581  * :---------------------------------------|:------|:------------
73582  * ALT_EMAC_DMA_HW_FEATURE_GMIISEL_E_DISD | 0x0 |
73583  * ALT_EMAC_DMA_HW_FEATURE_GMIISEL_E_END | 0x1 |
73584  *
73585  * Field Access Macros:
73586  *
73587  */
73588 /*
73589  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_GMIISEL
73590  *
73591  */
73592 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_E_DISD 0x0
73593 /*
73594  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_GMIISEL
73595  *
73596  */
73597 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_E_END 0x1
73598 
73599 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field. */
73600 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_LSB 1
73601 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field. */
73602 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_MSB 1
73603 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field. */
73604 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_WIDTH 1
73605 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field value. */
73606 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_SET_MSK 0x00000002
73607 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field value. */
73608 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_CLR_MSK 0xfffffffd
73609 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field. */
73610 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_RESET 0x1
73611 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_GMIISEL field value from a register. */
73612 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_GET(value) (((value) & 0x00000002) >> 1)
73613 /* Produces a ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field value suitable for setting the register. */
73614 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_SET(value) (((value) << 1) & 0x00000002)
73615 
73616 /*
73617  * Field : hdsel
73618  *
73619  * Half-Duplex support
73620  *
73621  * Field Enumeration Values:
73622  *
73623  * Enum | Value | Description
73624  * :-------------------------------------|:------|:------------
73625  * ALT_EMAC_DMA_HW_FEATURE_HDSEL_E_DISD | 0x0 |
73626  * ALT_EMAC_DMA_HW_FEATURE_HDSEL_E_END | 0x1 |
73627  *
73628  * Field Access Macros:
73629  *
73630  */
73631 /*
73632  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_HDSEL
73633  *
73634  */
73635 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_E_DISD 0x0
73636 /*
73637  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_HDSEL
73638  *
73639  */
73640 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_E_END 0x1
73641 
73642 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field. */
73643 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_LSB 2
73644 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field. */
73645 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_MSB 2
73646 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field. */
73647 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_WIDTH 1
73648 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field value. */
73649 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_SET_MSK 0x00000004
73650 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field value. */
73651 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_CLR_MSK 0xfffffffb
73652 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field. */
73653 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_RESET 0x1
73654 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_HDSEL field value from a register. */
73655 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_GET(value) (((value) & 0x00000004) >> 2)
73656 /* Produces a ALT_EMAC_DMA_HW_FEATURE_HDSEL register field value suitable for setting the register. */
73657 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_SET(value) (((value) << 2) & 0x00000004)
73658 
73659 /*
73660  * Field : exthashen
73661  *
73662  * Expanded DA Hash Filter
73663  *
73664  * Field Access Macros:
73665  *
73666  */
73667 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN register field. */
73668 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_LSB 3
73669 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN register field. */
73670 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_MSB 3
73671 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN register field. */
73672 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_WIDTH 1
73673 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN register field value. */
73674 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_SET_MSK 0x00000008
73675 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN register field value. */
73676 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_CLR_MSK 0xfffffff7
73677 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN register field. */
73678 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_RESET 0x0
73679 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN field value from a register. */
73680 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_GET(value) (((value) & 0x00000008) >> 3)
73681 /* Produces a ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN register field value suitable for setting the register. */
73682 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_SET(value) (((value) << 3) & 0x00000008)
73683 
73684 /*
73685  * Field : hashsel
73686  *
73687  * HASH Filter
73688  *
73689  * Field Enumeration Values:
73690  *
73691  * Enum | Value | Description
73692  * :---------------------------------------|:------|:------------
73693  * ALT_EMAC_DMA_HW_FEATURE_HASHSEL_E_DISD | 0x0 |
73694  * ALT_EMAC_DMA_HW_FEATURE_HASHSEL_E_END | 0x1 |
73695  *
73696  * Field Access Macros:
73697  *
73698  */
73699 /*
73700  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_HASHSEL
73701  *
73702  */
73703 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_E_DISD 0x0
73704 /*
73705  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_HASHSEL
73706  *
73707  */
73708 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_E_END 0x1
73709 
73710 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field. */
73711 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_LSB 4
73712 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field. */
73713 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_MSB 4
73714 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field. */
73715 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_WIDTH 1
73716 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field value. */
73717 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_SET_MSK 0x00000010
73718 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field value. */
73719 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_CLR_MSK 0xffffffef
73720 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field. */
73721 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_RESET 0x0
73722 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_HASHSEL field value from a register. */
73723 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_GET(value) (((value) & 0x00000010) >> 4)
73724 /* Produces a ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field value suitable for setting the register. */
73725 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_SET(value) (((value) << 4) & 0x00000010)
73726 
73727 /*
73728  * Field : addmacadrsel
73729  *
73730  * Multiple MAC Address Registers
73731  *
73732  * Field Enumeration Values:
73733  *
73734  * Enum | Value | Description
73735  * :--------------------------------------------|:------|:------------
73736  * ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_E_DISD | 0x0 |
73737  * ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_E_END | 0x1 |
73738  *
73739  * Field Access Macros:
73740  *
73741  */
73742 /*
73743  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL
73744  *
73745  */
73746 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_E_DISD 0x0
73747 /*
73748  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL
73749  *
73750  */
73751 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_E_END 0x1
73752 
73753 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field. */
73754 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_LSB 5
73755 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field. */
73756 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_MSB 5
73757 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field. */
73758 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_WIDTH 1
73759 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field value. */
73760 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_SET_MSK 0x00000020
73761 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field value. */
73762 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_CLR_MSK 0xffffffdf
73763 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field. */
73764 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_RESET 0x1
73765 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL field value from a register. */
73766 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_GET(value) (((value) & 0x00000020) >> 5)
73767 /* Produces a ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field value suitable for setting the register. */
73768 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_SET(value) (((value) << 5) & 0x00000020)
73769 
73770 /*
73771  * Field : pcssel
73772  *
73773  * PCS registers (TBI, SGMII, or RTBI PHY interface)
73774  *
73775  * Field Enumeration Values:
73776  *
73777  * Enum | Value | Description
73778  * :--------------------------------------|:------|:------------
73779  * ALT_EMAC_DMA_HW_FEATURE_PCSSEL_E_DISD | 0x0 |
73780  * ALT_EMAC_DMA_HW_FEATURE_PCSSEL_E_END | 0x1 |
73781  *
73782  * Field Access Macros:
73783  *
73784  */
73785 /*
73786  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_PCSSEL
73787  *
73788  */
73789 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_E_DISD 0x0
73790 /*
73791  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_PCSSEL
73792  *
73793  */
73794 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_E_END 0x1
73795 
73796 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field. */
73797 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_LSB 6
73798 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field. */
73799 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_MSB 6
73800 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field. */
73801 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_WIDTH 1
73802 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field value. */
73803 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_SET_MSK 0x00000040
73804 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field value. */
73805 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_CLR_MSK 0xffffffbf
73806 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field. */
73807 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_RESET 0x0
73808 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_PCSSEL field value from a register. */
73809 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_GET(value) (((value) & 0x00000040) >> 6)
73810 /* Produces a ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field value suitable for setting the register. */
73811 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_SET(value) (((value) << 6) & 0x00000040)
73812 
73813 /*
73814  * Field : l3l4fltren
73815  *
73816  * Layer 3 and Layer 4 Filter Feature
73817  *
73818  * Field Access Macros:
73819  *
73820  */
73821 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN register field. */
73822 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_LSB 7
73823 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN register field. */
73824 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_MSB 7
73825 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN register field. */
73826 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_WIDTH 1
73827 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN register field value. */
73828 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_SET_MSK 0x00000080
73829 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN register field value. */
73830 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_CLR_MSK 0xffffff7f
73831 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN register field. */
73832 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_RESET 0x1
73833 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN field value from a register. */
73834 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_GET(value) (((value) & 0x00000080) >> 7)
73835 /* Produces a ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN register field value suitable for setting the register. */
73836 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_SET(value) (((value) << 7) & 0x00000080)
73837 
73838 /*
73839  * Field : smasel
73840  *
73841  * SMA (MDIO) Interface
73842  *
73843  * Field Enumeration Values:
73844  *
73845  * Enum | Value | Description
73846  * :--------------------------------------|:------|:------------
73847  * ALT_EMAC_DMA_HW_FEATURE_SMASEL_E_DISD | 0x0 |
73848  * ALT_EMAC_DMA_HW_FEATURE_SMASEL_E_END | 0x1 |
73849  *
73850  * Field Access Macros:
73851  *
73852  */
73853 /*
73854  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_SMASEL
73855  *
73856  */
73857 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_E_DISD 0x0
73858 /*
73859  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_SMASEL
73860  *
73861  */
73862 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_E_END 0x1
73863 
73864 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field. */
73865 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_LSB 8
73866 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field. */
73867 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_MSB 8
73868 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field. */
73869 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_WIDTH 1
73870 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field value. */
73871 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_SET_MSK 0x00000100
73872 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field value. */
73873 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_CLR_MSK 0xfffffeff
73874 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field. */
73875 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_RESET 0x1
73876 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_SMASEL field value from a register. */
73877 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_GET(value) (((value) & 0x00000100) >> 8)
73878 /* Produces a ALT_EMAC_DMA_HW_FEATURE_SMASEL register field value suitable for setting the register. */
73879 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_SET(value) (((value) << 8) & 0x00000100)
73880 
73881 /*
73882  * Field : rwksel
73883  *
73884  * PMT Remote Wakeup
73885  *
73886  * Field Enumeration Values:
73887  *
73888  * Enum | Value | Description
73889  * :--------------------------------------|:------|:------------
73890  * ALT_EMAC_DMA_HW_FEATURE_RWKSEL_E_DISD | 0x0 |
73891  * ALT_EMAC_DMA_HW_FEATURE_RWKSEL_E_END | 0x1 |
73892  *
73893  * Field Access Macros:
73894  *
73895  */
73896 /*
73897  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RWKSEL
73898  *
73899  */
73900 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_E_DISD 0x0
73901 /*
73902  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RWKSEL
73903  *
73904  */
73905 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_E_END 0x1
73906 
73907 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field. */
73908 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_LSB 9
73909 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field. */
73910 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_MSB 9
73911 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field. */
73912 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_WIDTH 1
73913 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field value. */
73914 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_SET_MSK 0x00000200
73915 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field value. */
73916 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_CLR_MSK 0xfffffdff
73917 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field. */
73918 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_RESET 0x0
73919 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_RWKSEL field value from a register. */
73920 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_GET(value) (((value) & 0x00000200) >> 9)
73921 /* Produces a ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field value suitable for setting the register. */
73922 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_SET(value) (((value) << 9) & 0x00000200)
73923 
73924 /*
73925  * Field : mgksel
73926  *
73927  * PMT Magic Packet
73928  *
73929  * Field Enumeration Values:
73930  *
73931  * Enum | Value | Description
73932  * :--------------------------------------|:------|:------------
73933  * ALT_EMAC_DMA_HW_FEATURE_MGKSEL_E_DISD | 0x0 |
73934  * ALT_EMAC_DMA_HW_FEATURE_MGKSEL_E_END | 0x1 |
73935  *
73936  * Field Access Macros:
73937  *
73938  */
73939 /*
73940  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MGKSEL
73941  *
73942  */
73943 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_E_DISD 0x0
73944 /*
73945  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MGKSEL
73946  *
73947  */
73948 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_E_END 0x1
73949 
73950 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field. */
73951 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_LSB 10
73952 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field. */
73953 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_MSB 10
73954 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field. */
73955 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_WIDTH 1
73956 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field value. */
73957 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_SET_MSK 0x00000400
73958 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field value. */
73959 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_CLR_MSK 0xfffffbff
73960 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field. */
73961 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_RESET 0x1
73962 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_MGKSEL field value from a register. */
73963 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_GET(value) (((value) & 0x00000400) >> 10)
73964 /* Produces a ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field value suitable for setting the register. */
73965 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_SET(value) (((value) << 10) & 0x00000400)
73966 
73967 /*
73968  * Field : mmcsel
73969  *
73970  * RMON Module
73971  *
73972  * Field Enumeration Values:
73973  *
73974  * Enum | Value | Description
73975  * :--------------------------------------|:------|:------------
73976  * ALT_EMAC_DMA_HW_FEATURE_MMCSEL_E_DISD | 0x0 |
73977  * ALT_EMAC_DMA_HW_FEATURE_MMCSEL_E_END | 0x1 |
73978  *
73979  * Field Access Macros:
73980  *
73981  */
73982 /*
73983  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MMCSEL
73984  *
73985  */
73986 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_E_DISD 0x0
73987 /*
73988  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MMCSEL
73989  *
73990  */
73991 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_E_END 0x1
73992 
73993 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field. */
73994 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_LSB 11
73995 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field. */
73996 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_MSB 11
73997 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field. */
73998 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_WIDTH 1
73999 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field value. */
74000 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_SET_MSK 0x00000800
74001 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field value. */
74002 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_CLR_MSK 0xfffff7ff
74003 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field. */
74004 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_RESET 0x1
74005 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_MMCSEL field value from a register. */
74006 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_GET(value) (((value) & 0x00000800) >> 11)
74007 /* Produces a ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field value suitable for setting the register. */
74008 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_SET(value) (((value) << 11) & 0x00000800)
74009 
74010 /*
74011  * Field : tsver1sel
74012  *
74013  * Only IEEE 1588-2002 Timestamp
74014  *
74015  * Field Enumeration Values:
74016  *
74017  * Enum | Value | Description
74018  * :-----------------------------------------|:------|:------------
74019  * ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_E_DISD | 0x0 |
74020  * ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_E_END | 0x1 |
74021  *
74022  * Field Access Macros:
74023  *
74024  */
74025 /*
74026  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL
74027  *
74028  */
74029 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_E_DISD 0x0
74030 /*
74031  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL
74032  *
74033  */
74034 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_E_END 0x1
74035 
74036 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field. */
74037 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_LSB 12
74038 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field. */
74039 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_MSB 12
74040 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field. */
74041 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_WIDTH 1
74042 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field value. */
74043 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_SET_MSK 0x00001000
74044 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field value. */
74045 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_CLR_MSK 0xffffefff
74046 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field. */
74047 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_RESET 0x0
74048 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL field value from a register. */
74049 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_GET(value) (((value) & 0x00001000) >> 12)
74050 /* Produces a ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field value suitable for setting the register. */
74051 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_SET(value) (((value) << 12) & 0x00001000)
74052 
74053 /*
74054  * Field : tsver2sel
74055  *
74056  * IEEE 1588-2008 Advanced Timestamp
74057  *
74058  * Field Enumeration Values:
74059  *
74060  * Enum | Value | Description
74061  * :-----------------------------------------|:------|:------------
74062  * ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_E_DISD | 0x0 |
74063  * ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_E_END | 0x1 |
74064  *
74065  * Field Access Macros:
74066  *
74067  */
74068 /*
74069  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL
74070  *
74071  */
74072 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_E_DISD 0x0
74073 /*
74074  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL
74075  *
74076  */
74077 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_E_END 0x1
74078 
74079 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field. */
74080 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_LSB 13
74081 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field. */
74082 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_MSB 13
74083 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field. */
74084 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_WIDTH 1
74085 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field value. */
74086 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_SET_MSK 0x00002000
74087 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field value. */
74088 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_CLR_MSK 0xffffdfff
74089 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field. */
74090 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_RESET 0x1
74091 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL field value from a register. */
74092 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_GET(value) (((value) & 0x00002000) >> 13)
74093 /* Produces a ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field value suitable for setting the register. */
74094 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_SET(value) (((value) << 13) & 0x00002000)
74095 
74096 /*
74097  * Field : eeesel
74098  *
74099  * Energy Efficient Ethernet
74100  *
74101  * Field Enumeration Values:
74102  *
74103  * Enum | Value | Description
74104  * :--------------------------------------|:------|:------------
74105  * ALT_EMAC_DMA_HW_FEATURE_EEESEL_E_DISD | 0x0 |
74106  * ALT_EMAC_DMA_HW_FEATURE_EEESEL_E_END | 0x1 |
74107  *
74108  * Field Access Macros:
74109  *
74110  */
74111 /*
74112  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_EEESEL
74113  *
74114  */
74115 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_E_DISD 0x0
74116 /*
74117  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_EEESEL
74118  *
74119  */
74120 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_E_END 0x1
74121 
74122 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field. */
74123 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_LSB 14
74124 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field. */
74125 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_MSB 14
74126 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field. */
74127 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_WIDTH 1
74128 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field value. */
74129 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_SET_MSK 0x00004000
74130 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field value. */
74131 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_CLR_MSK 0xffffbfff
74132 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field. */
74133 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_RESET 0x1
74134 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_EEESEL field value from a register. */
74135 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_GET(value) (((value) & 0x00004000) >> 14)
74136 /* Produces a ALT_EMAC_DMA_HW_FEATURE_EEESEL register field value suitable for setting the register. */
74137 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_SET(value) (((value) << 14) & 0x00004000)
74138 
74139 /*
74140  * Field : avsel
74141  *
74142  * AV Feature
74143  *
74144  * Field Enumeration Values:
74145  *
74146  * Enum | Value | Description
74147  * :-------------------------------------|:------|:------------
74148  * ALT_EMAC_DMA_HW_FEATURE_AVSEL_E_DISD | 0x0 |
74149  * ALT_EMAC_DMA_HW_FEATURE_AVSEL_E_END | 0x1 |
74150  *
74151  * Field Access Macros:
74152  *
74153  */
74154 /*
74155  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_AVSEL
74156  *
74157  */
74158 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_E_DISD 0x0
74159 /*
74160  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_AVSEL
74161  *
74162  */
74163 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_E_END 0x1
74164 
74165 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field. */
74166 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_LSB 15
74167 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field. */
74168 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_MSB 15
74169 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field. */
74170 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_WIDTH 1
74171 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field value. */
74172 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_SET_MSK 0x00008000
74173 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field value. */
74174 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_CLR_MSK 0xffff7fff
74175 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field. */
74176 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_RESET 0x1
74177 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_AVSEL field value from a register. */
74178 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_GET(value) (((value) & 0x00008000) >> 15)
74179 /* Produces a ALT_EMAC_DMA_HW_FEATURE_AVSEL register field value suitable for setting the register. */
74180 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_SET(value) (((value) << 15) & 0x00008000)
74181 
74182 /*
74183  * Field : txoesel
74184  *
74185  * Checksum Offload in Tx
74186  *
74187  * Field Enumeration Values:
74188  *
74189  * Enum | Value | Description
74190  * :---------------------------------------|:------|:------------
74191  * ALT_EMAC_DMA_HW_FEATURE_TXOESEL_E_DISD | 0x0 |
74192  * ALT_EMAC_DMA_HW_FEATURE_TXOESEL_E_END | 0x1 |
74193  *
74194  * Field Access Macros:
74195  *
74196  */
74197 /*
74198  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TXOESEL
74199  *
74200  */
74201 #define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_E_DISD 0x0
74202 /*
74203  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TXOESEL
74204  *
74205  */
74206 #define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_E_END 0x1
74207 
74208 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field. */
74209 #define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_LSB 16
74210 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field. */
74211 #define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_MSB 16
74212 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field. */
74213 #define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_WIDTH 1
74214 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field value. */
74215 #define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_SET_MSK 0x00010000
74216 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field value. */
74217 #define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_CLR_MSK 0xfffeffff
74218 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field. */
74219 #define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_RESET 0x1
74220 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_TXOESEL field value from a register. */
74221 #define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_GET(value) (((value) & 0x00010000) >> 16)
74222 /* Produces a ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field value suitable for setting the register. */
74223 #define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_SET(value) (((value) << 16) & 0x00010000)
74224 
74225 /*
74226  * Field : rxtyp1coe
74227  *
74228  * IP Checksum Offload (Type 1) in Rx
74229  *
74230  * Note: If IPCHKSUM_EN = Enabled and IPC_FULL_OFFLOAD = Enabled, then RXTYP1COE =
74231  * 0 and RXTYP2COE =1.
74232  *
74233  * Field Enumeration Values:
74234  *
74235  * Enum | Value | Description
74236  * :-----------------------------------------|:------|:------------
74237  * ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_E_DISD | 0x0 |
74238  * ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_E_END | 0x1 |
74239  *
74240  * Field Access Macros:
74241  *
74242  */
74243 /*
74244  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE
74245  *
74246  */
74247 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_E_DISD 0x0
74248 /*
74249  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE
74250  *
74251  */
74252 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_E_END 0x1
74253 
74254 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field. */
74255 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_LSB 17
74256 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field. */
74257 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_MSB 17
74258 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field. */
74259 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_WIDTH 1
74260 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field value. */
74261 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_SET_MSK 0x00020000
74262 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field value. */
74263 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_CLR_MSK 0xfffdffff
74264 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field. */
74265 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_RESET 0x0
74266 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE field value from a register. */
74267 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_GET(value) (((value) & 0x00020000) >> 17)
74268 /* Produces a ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field value suitable for setting the register. */
74269 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_SET(value) (((value) << 17) & 0x00020000)
74270 
74271 /*
74272  * Field : rxtyp2coe
74273  *
74274  * IP Checksum Offload (Type 2) in Rx
74275  *
74276  * Field Enumeration Values:
74277  *
74278  * Enum | Value | Description
74279  * :-----------------------------------------|:------|:------------
74280  * ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_E_DISD | 0x0 |
74281  * ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_E_END | 0x1 |
74282  *
74283  * Field Access Macros:
74284  *
74285  */
74286 /*
74287  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE
74288  *
74289  */
74290 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_E_DISD 0x0
74291 /*
74292  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE
74293  *
74294  */
74295 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_E_END 0x1
74296 
74297 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field. */
74298 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_LSB 18
74299 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field. */
74300 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_MSB 18
74301 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field. */
74302 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_WIDTH 1
74303 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field value. */
74304 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_SET_MSK 0x00040000
74305 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field value. */
74306 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_CLR_MSK 0xfffbffff
74307 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field. */
74308 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_RESET 0x1
74309 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE field value from a register. */
74310 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_GET(value) (((value) & 0x00040000) >> 18)
74311 /* Produces a ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field value suitable for setting the register. */
74312 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_SET(value) (((value) << 18) & 0x00040000)
74313 
74314 /*
74315  * Field : rxfifosize
74316  *
74317  * Rx FIFO > 2,048 Bytes
74318  *
74319  * Field Enumeration Values:
74320  *
74321  * Enum | Value | Description
74322  * :------------------------------------------|:------|:------------
74323  * ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_E_DISD | 0x0 |
74324  * ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_E_END | 0x1 |
74325  *
74326  * Field Access Macros:
74327  *
74328  */
74329 /*
74330  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE
74331  *
74332  */
74333 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_E_DISD 0x0
74334 /*
74335  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE
74336  *
74337  */
74338 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_E_END 0x1
74339 
74340 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field. */
74341 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_LSB 19
74342 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field. */
74343 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_MSB 19
74344 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field. */
74345 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_WIDTH 1
74346 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field value. */
74347 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_SET_MSK 0x00080000
74348 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field value. */
74349 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_CLR_MSK 0xfff7ffff
74350 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field. */
74351 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_RESET 0x0
74352 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE field value from a register. */
74353 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_GET(value) (((value) & 0x00080000) >> 19)
74354 /* Produces a ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field value suitable for setting the register. */
74355 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_SET(value) (((value) << 19) & 0x00080000)
74356 
74357 /*
74358  * Field : rxchcnt
74359  *
74360  * Number of additional Rx channels
74361  *
74362  * Field Enumeration Values:
74363  *
74364  * Enum | Value | Description
74365  * :---------------------------------------|:------|:------------
74366  * ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_E_DISD | 0x0 |
74367  * ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_E_END | 0x1 |
74368  *
74369  * Field Access Macros:
74370  *
74371  */
74372 /*
74373  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXCHCNT
74374  *
74375  */
74376 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_E_DISD 0x0
74377 /*
74378  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXCHCNT
74379  *
74380  */
74381 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_E_END 0x1
74382 
74383 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field. */
74384 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_LSB 20
74385 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field. */
74386 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_MSB 21
74387 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field. */
74388 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_WIDTH 2
74389 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field value. */
74390 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_SET_MSK 0x00300000
74391 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field value. */
74392 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_CLR_MSK 0xffcfffff
74393 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field. */
74394 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_RESET 0x0
74395 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT field value from a register. */
74396 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_GET(value) (((value) & 0x00300000) >> 20)
74397 /* Produces a ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field value suitable for setting the register. */
74398 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_SET(value) (((value) << 20) & 0x00300000)
74399 
74400 /*
74401  * Field : txchcnt
74402  *
74403  * Number of additional Tx channels
74404  *
74405  * Field Enumeration Values:
74406  *
74407  * Enum | Value | Description
74408  * :---------------------------------------|:------|:------------
74409  * ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_E_DISD | 0x0 |
74410  * ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_E_END | 0x1 |
74411  *
74412  * Field Access Macros:
74413  *
74414  */
74415 /*
74416  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TXCHCNT
74417  *
74418  */
74419 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_E_DISD 0x0
74420 /*
74421  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TXCHCNT
74422  *
74423  */
74424 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_E_END 0x1
74425 
74426 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field. */
74427 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_LSB 22
74428 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field. */
74429 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_MSB 23
74430 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field. */
74431 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_WIDTH 2
74432 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field value. */
74433 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_SET_MSK 0x00c00000
74434 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field value. */
74435 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_CLR_MSK 0xff3fffff
74436 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field. */
74437 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_RESET 0x1
74438 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT field value from a register. */
74439 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_GET(value) (((value) & 0x00c00000) >> 22)
74440 /* Produces a ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field value suitable for setting the register. */
74441 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_SET(value) (((value) << 22) & 0x00c00000)
74442 
74443 /*
74444  * Field : enhdessel
74445  *
74446  * Alternate (Enhanced Descriptor)
74447  *
74448  * Field Enumeration Values:
74449  *
74450  * Enum | Value | Description
74451  * :-----------------------------------------|:------|:------------
74452  * ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_E_DISD | 0x0 |
74453  * ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_E_END | 0x1 |
74454  *
74455  * Field Access Macros:
74456  *
74457  */
74458 /*
74459  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL
74460  *
74461  */
74462 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_E_DISD 0x0
74463 /*
74464  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL
74465  *
74466  */
74467 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_E_END 0x1
74468 
74469 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field. */
74470 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_LSB 24
74471 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field. */
74472 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_MSB 24
74473 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field. */
74474 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_WIDTH 1
74475 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field value. */
74476 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_SET_MSK 0x01000000
74477 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field value. */
74478 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_CLR_MSK 0xfeffffff
74479 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field. */
74480 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_RESET 0x1
74481 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL field value from a register. */
74482 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_GET(value) (((value) & 0x01000000) >> 24)
74483 /* Produces a ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field value suitable for setting the register. */
74484 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_SET(value) (((value) << 24) & 0x01000000)
74485 
74486 /*
74487  * Field : inttsen
74488  *
74489  * Timestamping with Internal System Time
74490  *
74491  * Field Access Macros:
74492  *
74493  */
74494 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_INTTSEN register field. */
74495 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_LSB 25
74496 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_INTTSEN register field. */
74497 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_MSB 25
74498 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_INTTSEN register field. */
74499 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_WIDTH 1
74500 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_INTTSEN register field value. */
74501 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_SET_MSK 0x02000000
74502 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_INTTSEN register field value. */
74503 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_CLR_MSK 0xfdffffff
74504 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_INTTSEN register field. */
74505 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_RESET 0x0
74506 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_INTTSEN field value from a register. */
74507 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_GET(value) (((value) & 0x02000000) >> 25)
74508 /* Produces a ALT_EMAC_DMA_HW_FEATURE_INTTSEN register field value suitable for setting the register. */
74509 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_SET(value) (((value) << 25) & 0x02000000)
74510 
74511 /*
74512  * Field : flexippsen
74513  *
74514  * Flexible Pulse-Per-Second Output
74515  *
74516  * Field Access Macros:
74517  *
74518  */
74519 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN register field. */
74520 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_LSB 26
74521 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN register field. */
74522 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_MSB 26
74523 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN register field. */
74524 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_WIDTH 1
74525 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN register field value. */
74526 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_SET_MSK 0x04000000
74527 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN register field value. */
74528 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_CLR_MSK 0xfbffffff
74529 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN register field. */
74530 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_RESET 0x0
74531 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN field value from a register. */
74532 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_GET(value) (((value) & 0x04000000) >> 26)
74533 /* Produces a ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN register field value suitable for setting the register. */
74534 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_SET(value) (((value) << 26) & 0x04000000)
74535 
74536 /*
74537  * Field : savlanins
74538  *
74539  * Source Address or VLAN Insertion
74540  *
74541  * Field Access Macros:
74542  *
74543  */
74544 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_SAVLANINS register field. */
74545 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_LSB 27
74546 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_SAVLANINS register field. */
74547 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_MSB 27
74548 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_SAVLANINS register field. */
74549 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_WIDTH 1
74550 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_SAVLANINS register field value. */
74551 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_SET_MSK 0x08000000
74552 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_SAVLANINS register field value. */
74553 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_CLR_MSK 0xf7ffffff
74554 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_SAVLANINS register field. */
74555 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_RESET 0x1
74556 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_SAVLANINS field value from a register. */
74557 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_GET(value) (((value) & 0x08000000) >> 27)
74558 /* Produces a ALT_EMAC_DMA_HW_FEATURE_SAVLANINS register field value suitable for setting the register. */
74559 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_SET(value) (((value) << 27) & 0x08000000)
74560 
74561 /*
74562  * Field : actphyif
74563  *
74564  * Active or Selected PHY interface
74565  *
74566  * When you have multiple PHY interfaces in your configuration, this field
74567  * indicates the sampled value of phy_intf_sel_i during reset de-assertion
74568  *
74569  * * 0000: GMII or MII
74570  *
74571  * * 0001: RGMII
74572  *
74573  * * 0010: SGMII
74574  *
74575  * * 0011: TBI
74576  *
74577  * * 0100: RMII
74578  *
74579  * * 0101: RTBI
74580  *
74581  * * 0110: SMII
74582  *
74583  * * 0111: RevMII
74584  *
74585  * * All Others: Reserved
74586  *
74587  * Field Enumeration Values:
74588  *
74589  * Enum | Value | Description
74590  * :--------------------------------------------|:------|:------------
74591  * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_GMIIMII0 | 0x0 |
74592  * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RGMII1 | 0x1 |
74593  * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_SGMII2 | 0x2 |
74594  * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_TBI3 | 0x3 |
74595  * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RMII4 | 0x4 |
74596  * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RTBI5 | 0x5 |
74597  * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_SMII6 | 0x6 |
74598  * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_REVMII7 | 0x7 |
74599  *
74600  * Field Access Macros:
74601  *
74602  */
74603 /*
74604  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
74605  *
74606  */
74607 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_GMIIMII0 0x0
74608 /*
74609  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
74610  *
74611  */
74612 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RGMII1 0x1
74613 /*
74614  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
74615  *
74616  */
74617 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_SGMII2 0x2
74618 /*
74619  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
74620  *
74621  */
74622 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_TBI3 0x3
74623 /*
74624  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
74625  *
74626  */
74627 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RMII4 0x4
74628 /*
74629  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
74630  *
74631  */
74632 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RTBI5 0x5
74633 /*
74634  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
74635  *
74636  */
74637 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_SMII6 0x6
74638 /*
74639  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
74640  *
74641  */
74642 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_REVMII7 0x7
74643 
74644 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field. */
74645 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_LSB 28
74646 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field. */
74647 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_MSB 30
74648 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field. */
74649 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_WIDTH 3
74650 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field value. */
74651 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_SET_MSK 0x70000000
74652 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field value. */
74653 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_CLR_MSK 0x8fffffff
74654 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field. */
74655 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_RESET 0x0
74656 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF field value from a register. */
74657 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_GET(value) (((value) & 0x70000000) >> 28)
74658 /* Produces a ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field value suitable for setting the register. */
74659 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_SET(value) (((value) << 28) & 0x70000000)
74660 
74661 /*
74662  * Field : reserved_31
74663  *
74664  * Reserved
74665  *
74666  * Field Access Macros:
74667  *
74668  */
74669 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RSVD_31 register field. */
74670 #define ALT_EMAC_DMA_HW_FEATURE_RSVD_31_LSB 31
74671 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RSVD_31 register field. */
74672 #define ALT_EMAC_DMA_HW_FEATURE_RSVD_31_MSB 31
74673 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RSVD_31 register field. */
74674 #define ALT_EMAC_DMA_HW_FEATURE_RSVD_31_WIDTH 1
74675 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RSVD_31 register field value. */
74676 #define ALT_EMAC_DMA_HW_FEATURE_RSVD_31_SET_MSK 0x80000000
74677 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RSVD_31 register field value. */
74678 #define ALT_EMAC_DMA_HW_FEATURE_RSVD_31_CLR_MSK 0x7fffffff
74679 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RSVD_31 register field. */
74680 #define ALT_EMAC_DMA_HW_FEATURE_RSVD_31_RESET 0x0
74681 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_RSVD_31 field value from a register. */
74682 #define ALT_EMAC_DMA_HW_FEATURE_RSVD_31_GET(value) (((value) & 0x80000000) >> 31)
74683 /* Produces a ALT_EMAC_DMA_HW_FEATURE_RSVD_31 register field value suitable for setting the register. */
74684 #define ALT_EMAC_DMA_HW_FEATURE_RSVD_31_SET(value) (((value) << 31) & 0x80000000)
74685 
74686 #ifndef __ASSEMBLY__
74687 /*
74688  * WARNING: The C register and register group struct declarations are provided for
74689  * convenience and illustrative purposes. They should, however, be used with
74690  * caution as the C language standard provides no guarantees about the alignment or
74691  * atomicity of device memory accesses. The recommended practice for writing
74692  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
74693  * alt_write_word() functions.
74694  *
74695  * The struct declaration for register ALT_EMAC_DMA_HW_FEATURE.
74696  */
74697 struct ALT_EMAC_DMA_HW_FEATURE_s
74698 {
74699  const uint32_t miisel : 1; /* ALT_EMAC_DMA_HW_FEATURE_MIISEL */
74700  const uint32_t gmiisel : 1; /* ALT_EMAC_DMA_HW_FEATURE_GMIISEL */
74701  const uint32_t hdsel : 1; /* ALT_EMAC_DMA_HW_FEATURE_HDSEL */
74702  const uint32_t exthashen : 1; /* ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN */
74703  const uint32_t hashsel : 1; /* ALT_EMAC_DMA_HW_FEATURE_HASHSEL */
74704  const uint32_t addmacadrsel : 1; /* ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL */
74705  const uint32_t pcssel : 1; /* ALT_EMAC_DMA_HW_FEATURE_PCSSEL */
74706  const uint32_t l3l4fltren : 1; /* ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN */
74707  const uint32_t smasel : 1; /* ALT_EMAC_DMA_HW_FEATURE_SMASEL */
74708  const uint32_t rwksel : 1; /* ALT_EMAC_DMA_HW_FEATURE_RWKSEL */
74709  const uint32_t mgksel : 1; /* ALT_EMAC_DMA_HW_FEATURE_MGKSEL */
74710  const uint32_t mmcsel : 1; /* ALT_EMAC_DMA_HW_FEATURE_MMCSEL */
74711  const uint32_t tsver1sel : 1; /* ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL */
74712  const uint32_t tsver2sel : 1; /* ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL */
74713  const uint32_t eeesel : 1; /* ALT_EMAC_DMA_HW_FEATURE_EEESEL */
74714  const uint32_t avsel : 1; /* ALT_EMAC_DMA_HW_FEATURE_AVSEL */
74715  const uint32_t txoesel : 1; /* ALT_EMAC_DMA_HW_FEATURE_TXOESEL */
74716  const uint32_t rxtyp1coe : 1; /* ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE */
74717  const uint32_t rxtyp2coe : 1; /* ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE */
74718  const uint32_t rxfifosize : 1; /* ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE */
74719  const uint32_t rxchcnt : 2; /* ALT_EMAC_DMA_HW_FEATURE_RXCHCNT */
74720  const uint32_t txchcnt : 2; /* ALT_EMAC_DMA_HW_FEATURE_TXCHCNT */
74721  const uint32_t enhdessel : 1; /* ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL */
74722  const uint32_t inttsen : 1; /* ALT_EMAC_DMA_HW_FEATURE_INTTSEN */
74723  const uint32_t flexippsen : 1; /* ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN */
74724  const uint32_t savlanins : 1; /* ALT_EMAC_DMA_HW_FEATURE_SAVLANINS */
74725  const uint32_t actphyif : 3; /* ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF */
74726  const uint32_t reserved_31 : 1; /* ALT_EMAC_DMA_HW_FEATURE_RSVD_31 */
74727 };
74728 
74729 /* The typedef declaration for register ALT_EMAC_DMA_HW_FEATURE. */
74730 typedef volatile struct ALT_EMAC_DMA_HW_FEATURE_s ALT_EMAC_DMA_HW_FEATURE_t;
74731 #endif /* __ASSEMBLY__ */
74732 
74733 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE register. */
74734 #define ALT_EMAC_DMA_HW_FEATURE_RESET 0x0945eda7
74735 /* The byte offset of the ALT_EMAC_DMA_HW_FEATURE register from the beginning of the component. */
74736 #define ALT_EMAC_DMA_HW_FEATURE_OFST 0x1058
74737 /* The address of the ALT_EMAC_DMA_HW_FEATURE register. */
74738 #define ALT_EMAC_DMA_HW_FEATURE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_HW_FEATURE_OFST))
74739 
74740 #ifndef __ASSEMBLY__
74741 /*
74742  * WARNING: The C register and register group struct declarations are provided for
74743  * convenience and illustrative purposes. They should, however, be used with
74744  * caution as the C language standard provides no guarantees about the alignment or
74745  * atomicity of device memory accesses. The recommended practice for writing
74746  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
74747  * alt_write_word() functions.
74748  *
74749  * The struct declaration for register group ALT_EMAC.
74750  */
74751 struct ALT_EMAC_s
74752 {
74753  ALT_EMAC_GMAC_MAC_CFG_t gmacgrp_mac_configuration; /* ALT_EMAC_GMAC_MAC_CFG */
74754  ALT_EMAC_GMAC_MAC_FRM_FLT_t gmacgrp_mac_frame_filter; /* ALT_EMAC_GMAC_MAC_FRM_FLT */
74755  volatile uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */
74756  ALT_EMAC_GMAC_GMII_ADDR_t gmacgrp_gmii_address; /* ALT_EMAC_GMAC_GMII_ADDR */
74757  ALT_EMAC_GMAC_GMII_DATA_t gmacgrp_gmii_data; /* ALT_EMAC_GMAC_GMII_DATA */
74758  ALT_EMAC_GMAC_FLOW_CTL_t gmacgrp_flow_control; /* ALT_EMAC_GMAC_FLOW_CTL */
74759  ALT_EMAC_GMAC_VLAN_TAG_t gmacgrp_vlan_tag; /* ALT_EMAC_GMAC_VLAN_TAG */
74760  ALT_EMAC_GMAC_VER_t gmacgrp_version; /* ALT_EMAC_GMAC_VER */
74761  ALT_EMAC_GMAC_DBG_t gmacgrp_debug; /* ALT_EMAC_GMAC_DBG */
74762  volatile uint32_t _pad_0x28_0x2f[2]; /* *UNDEFINED* */
74763  ALT_EMAC_GMAC_LPI_CTL_STAT_t gmacgrp_lpi_control_status; /* ALT_EMAC_GMAC_LPI_CTL_STAT */
74764  ALT_EMAC_GMAC_LPI_TMRS_CTL_t gmacgrp_lpi_timers_control; /* ALT_EMAC_GMAC_LPI_TMRS_CTL */
74765  ALT_EMAC_GMAC_INT_STAT_t gmacgrp_interrupt_status; /* ALT_EMAC_GMAC_INT_STAT */
74766  ALT_EMAC_GMAC_INT_MSK_t gmacgrp_interrupt_mask; /* ALT_EMAC_GMAC_INT_MSK */
74767  ALT_EMAC_GMAC_MAC_ADDR0_HIGH_t gmacgrp_mac_address0_high; /* ALT_EMAC_GMAC_MAC_ADDR0_HIGH */
74768  ALT_EMAC_GMAC_MAC_ADDR0_LOW_t gmacgrp_mac_address0_low; /* ALT_EMAC_GMAC_MAC_ADDR0_LOW */
74769  ALT_EMAC_GMAC_MAC_ADDR1_HIGH_t gmacgrp_mac_address1_high; /* ALT_EMAC_GMAC_MAC_ADDR1_HIGH */
74770  ALT_EMAC_GMAC_MAC_ADDR1_LOW_t gmacgrp_mac_address1_low; /* ALT_EMAC_GMAC_MAC_ADDR1_LOW */
74771  ALT_EMAC_GMAC_MAC_ADDR2_HIGH_t gmacgrp_mac_address2_high; /* ALT_EMAC_GMAC_MAC_ADDR2_HIGH */
74772  ALT_EMAC_GMAC_MAC_ADDR2_LOW_t gmacgrp_mac_address2_low; /* ALT_EMAC_GMAC_MAC_ADDR2_LOW */
74773  ALT_EMAC_GMAC_MAC_ADDR3_HIGH_t gmacgrp_mac_address3_high; /* ALT_EMAC_GMAC_MAC_ADDR3_HIGH */
74774  ALT_EMAC_GMAC_MAC_ADDR3_LOW_t gmacgrp_mac_address3_low; /* ALT_EMAC_GMAC_MAC_ADDR3_LOW */
74775  ALT_EMAC_GMAC_MAC_ADDR4_HIGH_t gmacgrp_mac_address4_high; /* ALT_EMAC_GMAC_MAC_ADDR4_HIGH */
74776  ALT_EMAC_GMAC_MAC_ADDR4_LOW_t gmacgrp_mac_address4_low; /* ALT_EMAC_GMAC_MAC_ADDR4_LOW */
74777  ALT_EMAC_GMAC_MAC_ADDR5_HIGH_t gmacgrp_mac_address5_high; /* ALT_EMAC_GMAC_MAC_ADDR5_HIGH */
74778  ALT_EMAC_GMAC_MAC_ADDR5_LOW_t gmacgrp_mac_address5_low; /* ALT_EMAC_GMAC_MAC_ADDR5_LOW */
74779  ALT_EMAC_GMAC_MAC_ADDR6_HIGH_t gmacgrp_mac_address6_high; /* ALT_EMAC_GMAC_MAC_ADDR6_HIGH */
74780  ALT_EMAC_GMAC_MAC_ADDR6_LOW_t gmacgrp_mac_address6_low; /* ALT_EMAC_GMAC_MAC_ADDR6_LOW */
74781  ALT_EMAC_GMAC_MAC_ADDR7_HIGH_t gmacgrp_mac_address7_high; /* ALT_EMAC_GMAC_MAC_ADDR7_HIGH */
74782  ALT_EMAC_GMAC_MAC_ADDR7_LOW_t gmacgrp_mac_address7_low; /* ALT_EMAC_GMAC_MAC_ADDR7_LOW */
74783  ALT_EMAC_GMAC_MAC_ADDR8_HIGH_t gmacgrp_mac_address8_high; /* ALT_EMAC_GMAC_MAC_ADDR8_HIGH */
74784  ALT_EMAC_GMAC_MAC_ADDR8_LOW_t gmacgrp_mac_address8_low; /* ALT_EMAC_GMAC_MAC_ADDR8_LOW */
74785  ALT_EMAC_GMAC_MAC_ADDR9_HIGH_t gmacgrp_mac_address9_high; /* ALT_EMAC_GMAC_MAC_ADDR9_HIGH */
74786  ALT_EMAC_GMAC_MAC_ADDR9_LOW_t gmacgrp_mac_address9_low; /* ALT_EMAC_GMAC_MAC_ADDR9_LOW */
74787  ALT_EMAC_GMAC_MAC_ADDR10_HIGH_t gmacgrp_mac_address10_high; /* ALT_EMAC_GMAC_MAC_ADDR10_HIGH */
74788  ALT_EMAC_GMAC_MAC_ADDR10_LOW_t gmacgrp_mac_address10_low; /* ALT_EMAC_GMAC_MAC_ADDR10_LOW */
74789  ALT_EMAC_GMAC_MAC_ADDR11_HIGH_t gmacgrp_mac_address11_high; /* ALT_EMAC_GMAC_MAC_ADDR11_HIGH */
74790  ALT_EMAC_GMAC_MAC_ADDR11_LOW_t gmacgrp_mac_address11_low; /* ALT_EMAC_GMAC_MAC_ADDR11_LOW */
74791  ALT_EMAC_GMAC_MAC_ADDR12_HIGH_t gmacgrp_mac_address12_high; /* ALT_EMAC_GMAC_MAC_ADDR12_HIGH */
74792  ALT_EMAC_GMAC_MAC_ADDR12_LOW_t gmacgrp_mac_address12_low; /* ALT_EMAC_GMAC_MAC_ADDR12_LOW */
74793  ALT_EMAC_GMAC_MAC_ADDR13_HIGH_t gmacgrp_mac_address13_high; /* ALT_EMAC_GMAC_MAC_ADDR13_HIGH */
74794  ALT_EMAC_GMAC_MAC_ADDR13_LOW_t gmacgrp_mac_address13_low; /* ALT_EMAC_GMAC_MAC_ADDR13_LOW */
74795  ALT_EMAC_GMAC_MAC_ADDR14_HIGH_t gmacgrp_mac_address14_high; /* ALT_EMAC_GMAC_MAC_ADDR14_HIGH */
74796  ALT_EMAC_GMAC_MAC_ADDR14_LOW_t gmacgrp_mac_address14_low; /* ALT_EMAC_GMAC_MAC_ADDR14_LOW */
74797  ALT_EMAC_GMAC_MAC_ADDR15_HIGH_t gmacgrp_mac_address15_high; /* ALT_EMAC_GMAC_MAC_ADDR15_HIGH */
74798  ALT_EMAC_GMAC_MAC_ADDR15_LOW_t gmacgrp_mac_address15_low; /* ALT_EMAC_GMAC_MAC_ADDR15_LOW */
74799  volatile uint32_t _pad_0xc0_0xd7[6]; /* *UNDEFINED* */
74800  ALT_EMAC_GMAC_MII_CTL_STAT_t gmacgrp_sgmii_rgmii_smii_control_status; /* ALT_EMAC_GMAC_MII_CTL_STAT */
74801  ALT_EMAC_GMAC_WDOG_TMO_t gmacgrp_wdog_timeout; /* ALT_EMAC_GMAC_WDOG_TMO */
74802  ALT_EMAC_GMAC_GENPIO_t gmacgrp_genpio; /* ALT_EMAC_GMAC_GENPIO */
74803  volatile uint32_t _pad_0xe4_0xff[7]; /* *UNDEFINED* */
74804  ALT_EMAC_GMAC_MMC_CTL_t gmacgrp_mmc_control; /* ALT_EMAC_GMAC_MMC_CTL */
74805  ALT_EMAC_GMAC_MMC_RX_INT_t gmacgrp_mmc_receive_interrupt; /* ALT_EMAC_GMAC_MMC_RX_INT */
74806  ALT_EMAC_GMAC_MMC_TX_INT_t gmacgrp_mmc_transmit_interrupt; /* ALT_EMAC_GMAC_MMC_TX_INT */
74807  ALT_EMAC_GMAC_MMC_RX_INT_MSK_t gmacgrp_mmc_receive_interrupt_mask; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK */
74808  ALT_EMAC_GMAC_MMC_TX_INT_MSK_t gmacgrp_mmc_transmit_interrupt_mask; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK */
74809  ALT_EMAC_GMAC_TXOCTETCOUNT_GB_t gmacgrp_txoctetcount_gb; /* ALT_EMAC_GMAC_TXOCTETCOUNT_GB */
74810  ALT_EMAC_GMAC_TXFRMCOUNT_GB_t gmacgrp_txframecount_gb; /* ALT_EMAC_GMAC_TXFRMCOUNT_GB */
74811  ALT_EMAC_GMAC_TXBCASTFRMS_G_t gmacgrp_txbroadcastframes_g; /* ALT_EMAC_GMAC_TXBCASTFRMS_G */
74812  ALT_EMAC_GMAC_TXMCASTFRMS_G_t gmacgrp_txmulticastframes_g; /* ALT_EMAC_GMAC_TXMCASTFRMS_G */
74813  ALT_EMAC_GMAC_TX64OCTETS_GB_t gmacgrp_tx64octets_gb; /* ALT_EMAC_GMAC_TX64OCTETS_GB */
74814  ALT_EMAC_GMAC_TX65TO127OCTETS_GB_t gmacgrp_tx65to127octets_gb; /* ALT_EMAC_GMAC_TX65TO127OCTETS_GB */
74815  ALT_EMAC_GMAC_TX128TO255OCTETS_GB_t gmacgrp_tx128to255octets_gb; /* ALT_EMAC_GMAC_TX128TO255OCTETS_GB */
74816  ALT_EMAC_GMAC_TX256TO511OCTETS_GB_t gmacgrp_tx256to511octets_gb; /* ALT_EMAC_GMAC_TX256TO511OCTETS_GB */
74817  ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_t gmacgrp_tx512to1023octets_gb; /* ALT_EMAC_GMAC_TX512TO1023OCTETS_GB */
74818  ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_t gmacgrp_tx1024tomaxoctets_gb; /* ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB */
74819  ALT_EMAC_GMAC_TXUNICASTFRMS_GB_t gmacgrp_txunicastframes_gb; /* ALT_EMAC_GMAC_TXUNICASTFRMS_GB */
74820  ALT_EMAC_GMAC_TXMCASTFRMS_GB_t gmacgrp_txmulticastframes_gb; /* ALT_EMAC_GMAC_TXMCASTFRMS_GB */
74821  ALT_EMAC_GMAC_TXBCASTFRMS_GB_t gmacgrp_txbroadcastframes_gb; /* ALT_EMAC_GMAC_TXBCASTFRMS_GB */
74822  ALT_EMAC_GMAC_TXUNDERFLOWERROR_t gmacgrp_txunderflowerror; /* ALT_EMAC_GMAC_TXUNDERFLOWERROR */
74823  ALT_EMAC_GMAC_TXSINGLECOL_G_t gmacgrp_txsinglecol_g; /* ALT_EMAC_GMAC_TXSINGLECOL_G */
74824  ALT_EMAC_GMAC_TXMULTICOL_G_t gmacgrp_txmulticol_g; /* ALT_EMAC_GMAC_TXMULTICOL_G */
74825  ALT_EMAC_GMAC_TXDEFERRED_t gmacgrp_txdeferred; /* ALT_EMAC_GMAC_TXDEFERRED */
74826  ALT_EMAC_GMAC_TXLATECOL_t gmacgrp_txlatecol; /* ALT_EMAC_GMAC_TXLATECOL */
74827  ALT_EMAC_GMAC_TXEXESSCOL_t gmacgrp_txexesscol; /* ALT_EMAC_GMAC_TXEXESSCOL */
74828  ALT_EMAC_GMAC_TXCARRIERERR_t gmacgrp_txcarriererr; /* ALT_EMAC_GMAC_TXCARRIERERR */
74829  ALT_EMAC_GMAC_TXOCTETCNT_t gmacgrp_txoctetcnt; /* ALT_EMAC_GMAC_TXOCTETCNT */
74830  ALT_EMAC_GMAC_TXFRMCOUNT_G_t gmacgrp_txframecount_g; /* ALT_EMAC_GMAC_TXFRMCOUNT_G */
74831  ALT_EMAC_GMAC_TXEXCESSDEF_t gmacgrp_txexcessdef; /* ALT_EMAC_GMAC_TXEXCESSDEF */
74832  ALT_EMAC_GMAC_TXPAUSEFRMS_t gmacgrp_txpauseframes; /* ALT_EMAC_GMAC_TXPAUSEFRMS */
74833  ALT_EMAC_GMAC_TXVLANFRMS_G_t gmacgrp_txvlanframes_g; /* ALT_EMAC_GMAC_TXVLANFRMS_G */
74834  ALT_EMAC_GMAC_TXOVERSIZE_G_t gmacgrp_txoversize_g; /* ALT_EMAC_GMAC_TXOVERSIZE_G */
74835  volatile uint32_t _pad_0x17c_0x17f; /* *UNDEFINED* */
74836  ALT_EMAC_GMAC_RXFRMCOUNT_GB_t gmacgrp_rxframecount_gb; /* ALT_EMAC_GMAC_RXFRMCOUNT_GB */
74837  ALT_EMAC_GMAC_RXOCTETCOUNT_GB_t gmacgrp_rxoctetcount_gb; /* ALT_EMAC_GMAC_RXOCTETCOUNT_GB */
74838  ALT_EMAC_GMAC_RXOCTETCOUNT_G_t gmacgrp_rxoctetcount_g; /* ALT_EMAC_GMAC_RXOCTETCOUNT_G */
74839  ALT_EMAC_GMAC_RXBCASTFRMS_G_t gmacgrp_rxbroadcastframes_g; /* ALT_EMAC_GMAC_RXBCASTFRMS_G */
74840  ALT_EMAC_GMAC_RXMCASTFRMS_G_t gmacgrp_rxmulticastframes_g; /* ALT_EMAC_GMAC_RXMCASTFRMS_G */
74841  ALT_EMAC_GMAC_RXCRCERROR_t gmacgrp_rxcrcerror; /* ALT_EMAC_GMAC_RXCRCERROR */
74842  ALT_EMAC_GMAC_RXALIGNMENTERROR_t gmacgrp_rxalignmenterror; /* ALT_EMAC_GMAC_RXALIGNMENTERROR */
74843  ALT_EMAC_GMAC_RXRUNTERROR_t gmacgrp_rxrunterror; /* ALT_EMAC_GMAC_RXRUNTERROR */
74844  ALT_EMAC_GMAC_RXJABBERERROR_t gmacgrp_rxjabbererror; /* ALT_EMAC_GMAC_RXJABBERERROR */
74845  ALT_EMAC_GMAC_RXUNDERSIZE_G_t gmacgrp_rxundersize_g; /* ALT_EMAC_GMAC_RXUNDERSIZE_G */
74846  ALT_EMAC_GMAC_RXOVERSIZE_G_t gmacgrp_rxoversize_g; /* ALT_EMAC_GMAC_RXOVERSIZE_G */
74847  ALT_EMAC_GMAC_RX64OCTETS_GB_t gmacgrp_rx64octets_gb; /* ALT_EMAC_GMAC_RX64OCTETS_GB */
74848  ALT_EMAC_GMAC_RX65TO127OCTETS_GB_t gmacgrp_rx65to127octets_gb; /* ALT_EMAC_GMAC_RX65TO127OCTETS_GB */
74849  ALT_EMAC_GMAC_RX128TO255OCTETS_GB_t gmacgrp_rx128to255octets_gb; /* ALT_EMAC_GMAC_RX128TO255OCTETS_GB */
74850  ALT_EMAC_GMAC_RX256TO511OCTETS_GB_t gmacgrp_rx256to511octets_gb; /* ALT_EMAC_GMAC_RX256TO511OCTETS_GB */
74851  ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_t gmacgrp_rx512to1023octets_gb; /* ALT_EMAC_GMAC_RX512TO1023OCTETS_GB */
74852  ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_t gmacgrp_rx1024tomaxoctets_gb; /* ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB */
74853  ALT_EMAC_GMAC_RXUNICASTFRMS_G_t gmacgrp_rxunicastframes_g; /* ALT_EMAC_GMAC_RXUNICASTFRMS_G */
74854  ALT_EMAC_GMAC_RXLENERROR_t gmacgrp_rxlengtherror; /* ALT_EMAC_GMAC_RXLENERROR */
74855  ALT_EMAC_GMAC_RXOUTOFRANGETYPE_t gmacgrp_rxoutofrangetype; /* ALT_EMAC_GMAC_RXOUTOFRANGETYPE */
74856  ALT_EMAC_GMAC_RXPAUSEFRMS_t gmacgrp_rxpauseframes; /* ALT_EMAC_GMAC_RXPAUSEFRMS */
74857  ALT_EMAC_GMAC_RXFIFOOVF_t gmacgrp_rxfifooverflow; /* ALT_EMAC_GMAC_RXFIFOOVF */
74858  ALT_EMAC_GMAC_RXVLANFRMS_GB_t gmacgrp_rxvlanframes_gb; /* ALT_EMAC_GMAC_RXVLANFRMS_GB */
74859  ALT_EMAC_GMAC_RXWDERROR_t gmacgrp_rxwatchdogerror; /* ALT_EMAC_GMAC_RXWDERROR */
74860  ALT_EMAC_GMAC_RXRCVERROR_t gmacgrp_rxrcverror; /* ALT_EMAC_GMAC_RXRCVERROR */
74861  ALT_EMAC_GMAC_RXCTLFRMS_G_t gmacgrp_rxctrlframes_g; /* ALT_EMAC_GMAC_RXCTLFRMS_G */
74862  volatile uint32_t _pad_0x1e8_0x1ff[6]; /* *UNDEFINED* */
74863  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_t gmacgrp_mmc_ipc_receive_interrupt_mask; /* ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK */
74864  volatile uint32_t _pad_0x204_0x207; /* *UNDEFINED* */
74865  ALT_EMAC_GMAC_MMC_IPC_RX_INT_t gmacgrp_mmc_ipc_receive_interrupt; /* ALT_EMAC_GMAC_MMC_IPC_RX_INT */
74866  volatile uint32_t _pad_0x20c_0x20f; /* *UNDEFINED* */
74867  ALT_EMAC_GMAC_RXIPV4_GD_FRMS_t gmacgrp_rxipv4_gd_frms; /* ALT_EMAC_GMAC_RXIPV4_GD_FRMS */
74868  ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_t gmacgrp_rxipv4_hdrerr_frms; /* ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS */
74869  ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_t gmacgrp_rxipv4_nopay_frms; /* ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS */
74870  ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_t gmacgrp_rxipv4_frag_frms; /* ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS */
74871  ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_t gmacgrp_rxipv4_udsbl_frms; /* ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS */
74872  ALT_EMAC_GMAC_RXIPV6_GD_FRMS_t gmacgrp_rxipv6_gd_frms; /* ALT_EMAC_GMAC_RXIPV6_GD_FRMS */
74873  ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_t gmacgrp_rxipv6_hdrerr_frms; /* ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS */
74874  ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_t gmacgrp_rxipv6_nopay_frms; /* ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS */
74875  ALT_EMAC_GMAC_RXUDP_GD_FRMS_t gmacgrp_rxudp_gd_frms; /* ALT_EMAC_GMAC_RXUDP_GD_FRMS */
74876  ALT_EMAC_GMAC_RXUDP_ERR_FRMS_t gmacgrp_rxudp_err_frms; /* ALT_EMAC_GMAC_RXUDP_ERR_FRMS */
74877  ALT_EMAC_GMAC_RXTCP_GD_FRMS_t gmacgrp_rxtcp_gd_frms; /* ALT_EMAC_GMAC_RXTCP_GD_FRMS */
74878  ALT_EMAC_GMAC_RXTCP_ERR_FRMS_t gmacgrp_rxtcp_err_frms; /* ALT_EMAC_GMAC_RXTCP_ERR_FRMS */
74879  ALT_EMAC_GMAC_RXICMP_GD_FRMS_t gmacgrp_rxicmp_gd_frms; /* ALT_EMAC_GMAC_RXICMP_GD_FRMS */
74880  ALT_EMAC_GMAC_RXICMP_ERR_FRMS_t gmacgrp_rxicmp_err_frms; /* ALT_EMAC_GMAC_RXICMP_ERR_FRMS */
74881  volatile uint32_t _pad_0x248_0x24f[2]; /* *UNDEFINED* */
74882  ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_t gmacgrp_rxipv4_gd_octets; /* ALT_EMAC_GMAC_RXIPV4_GD_OCTETS */
74883  ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_t gmacgrp_rxipv4_hdrerr_octets; /* ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS */
74884  ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_t gmacgrp_rxipv4_nopay_octets; /* ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS */
74885  ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_t gmacgrp_rxipv4_frag_octets; /* ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS */
74886  ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_t gmacgrp_rxipv4_udsbl_octets; /* ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS */
74887  ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_t gmacgrp_rxipv6_gd_octets; /* ALT_EMAC_GMAC_RXIPV6_GD_OCTETS */
74888  ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_t gmacgrp_rxipv6_hdrerr_octets; /* ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS */
74889  ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_t gmacgrp_rxipv6_nopay_octets; /* ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS */
74890  ALT_EMAC_GMAC_RXUDP_GD_OCTETS_t gmacgrp_rxudp_gd_octets; /* ALT_EMAC_GMAC_RXUDP_GD_OCTETS */
74891  ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_t gmacgrp_rxudp_err_octets; /* ALT_EMAC_GMAC_RXUDP_ERR_OCTETS */
74892  ALT_EMAC_GMAC_RXTCP_GD_OCTETS_t gmacgrp_rxtcp_gd_octets; /* ALT_EMAC_GMAC_RXTCP_GD_OCTETS */
74893  ALT_EMAC_GMAC_RXTCPERROCTETS_t gmacgrp_rxtcperroctets; /* ALT_EMAC_GMAC_RXTCPERROCTETS */
74894  ALT_EMAC_GMAC_RXICMP_GD_OCTETS_t gmacgrp_rxicmp_gd_octets; /* ALT_EMAC_GMAC_RXICMP_GD_OCTETS */
74895  ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_t gmacgrp_rxicmp_err_octets; /* ALT_EMAC_GMAC_RXICMP_ERR_OCTETS */
74896  volatile uint32_t _pad_0x288_0x3ff[94]; /* *UNDEFINED* */
74897  ALT_EMAC_GMAC_L3_L4_CTL0_t gmacgrp_l3_l4_control0; /* ALT_EMAC_GMAC_L3_L4_CTL0 */
74898  ALT_EMAC_GMAC_LYR4_ADDR0_t gmacgrp_layer4_address0; /* ALT_EMAC_GMAC_LYR4_ADDR0 */
74899  volatile uint32_t _pad_0x408_0x40f[2]; /* *UNDEFINED* */
74900  ALT_EMAC_GMAC_LYR3_ADDR0_REG0_t gmacgrp_layer3_addr0_reg0; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG0 */
74901  ALT_EMAC_GMAC_LYR3_ADDR1_REG0_t gmacgrp_layer3_addr1_reg0; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG0 */
74902  ALT_EMAC_GMAC_LYR3_ADDR2_REG0_t gmacgrp_layer3_addr2_reg0; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG0 */
74903  ALT_EMAC_GMAC_LYR3_ADDR3_REG0_t gmacgrp_layer3_addr3_reg0; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG0 */
74904  volatile uint32_t _pad_0x420_0x42f[4]; /* *UNDEFINED* */
74905  ALT_EMAC_GMAC_L3_L4_CTL1_t gmacgrp_l3_l4_control1; /* ALT_EMAC_GMAC_L3_L4_CTL1 */
74906  ALT_EMAC_GMAC_LYR4_ADDR1_t gmacgrp_layer4_address1; /* ALT_EMAC_GMAC_LYR4_ADDR1 */
74907  volatile uint32_t _pad_0x438_0x43f[2]; /* *UNDEFINED* */
74908  ALT_EMAC_GMAC_LYR3_ADDR0_REG1_t gmacgrp_layer3_addr0_reg1; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG1 */
74909  ALT_EMAC_GMAC_LYR3_ADDR1_REG1_t gmacgrp_layer3_addr1_reg1; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG1 */
74910  ALT_EMAC_GMAC_LYR3_ADDR2_REG1_t gmacgrp_layer3_addr2_reg1; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG1 */
74911  ALT_EMAC_GMAC_LYR3_ADDR3_REG1_t gmacgrp_layer3_addr3_reg1; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG1 */
74912  volatile uint32_t _pad_0x450_0x45f[4]; /* *UNDEFINED* */
74913  ALT_EMAC_GMAC_L3_L4_CTL2_t gmacgrp_l3_l4_control2; /* ALT_EMAC_GMAC_L3_L4_CTL2 */
74914  ALT_EMAC_GMAC_LYR4_ADDR2_t gmacgrp_layer4_address2; /* ALT_EMAC_GMAC_LYR4_ADDR2 */
74915  volatile uint32_t _pad_0x468_0x46f[2]; /* *UNDEFINED* */
74916  ALT_EMAC_GMAC_LYR3_ADDR0_REG2_t gmacgrp_layer3_addr0_reg2; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG2 */
74917  ALT_EMAC_GMAC_LYR3_ADDR1_REG2_t gmacgrp_layer3_addr1_reg2; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG2 */
74918  ALT_EMAC_GMAC_LYR3_ADDR2_REG2_t gmacgrp_layer3_addr2_reg2; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG2 */
74919  ALT_EMAC_GMAC_LYR3_ADDR3_REG2_t gmacgrp_layer3_addr3_reg2; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG2 */
74920  volatile uint32_t _pad_0x480_0x48f[4]; /* *UNDEFINED* */
74921  ALT_EMAC_GMAC_L3_L4_CTL3_t gmacgrp_l3_l4_control3; /* ALT_EMAC_GMAC_L3_L4_CTL3 */
74922  ALT_EMAC_GMAC_LYR4_ADDR3_t gmacgrp_layer4_address3; /* ALT_EMAC_GMAC_LYR4_ADDR3 */
74923  volatile uint32_t _pad_0x498_0x49f[2]; /* *UNDEFINED* */
74924  ALT_EMAC_GMAC_LYR3_ADDR0_REG3_t gmacgrp_layer3_addr0_reg3; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG3 */
74925  ALT_EMAC_GMAC_LYR3_ADDR1_REG3_t gmacgrp_layer3_addr1_reg3; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG3 */
74926  ALT_EMAC_GMAC_LYR3_ADDR2_REG3_t gmacgrp_layer3_addr2_reg3; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG3 */
74927  ALT_EMAC_GMAC_LYR3_ADDR3_REG3_t gmacgrp_layer3_addr3_reg3; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG3 */
74928  volatile uint32_t _pad_0x4b0_0x4ff[20]; /* *UNDEFINED* */
74929  ALT_EMAC_GMAC_HASH_TABLE_REG0_t gmacgrp_hash_table_reg0; /* ALT_EMAC_GMAC_HASH_TABLE_REG0 */
74930  ALT_EMAC_GMAC_HASH_TABLE_REG1_t gmacgrp_hash_table_reg1; /* ALT_EMAC_GMAC_HASH_TABLE_REG1 */
74931  ALT_EMAC_GMAC_HASH_TABLE_REG2_t gmacgrp_hash_table_reg2; /* ALT_EMAC_GMAC_HASH_TABLE_REG2 */
74932  ALT_EMAC_GMAC_HASH_TABLE_REG3_t gmacgrp_hash_table_reg3; /* ALT_EMAC_GMAC_HASH_TABLE_REG3 */
74933  ALT_EMAC_GMAC_HASH_TABLE_REG4_t gmacgrp_hash_table_reg4; /* ALT_EMAC_GMAC_HASH_TABLE_REG4 */
74934  ALT_EMAC_GMAC_HASH_TABLE_REG5_t gmacgrp_hash_table_reg5; /* ALT_EMAC_GMAC_HASH_TABLE_REG5 */
74935  ALT_EMAC_GMAC_HASH_TABLE_REG6_t gmacgrp_hash_table_reg6; /* ALT_EMAC_GMAC_HASH_TABLE_REG6 */
74936  ALT_EMAC_GMAC_HASH_TABLE_REG7_t gmacgrp_hash_table_reg7; /* ALT_EMAC_GMAC_HASH_TABLE_REG7 */
74937  volatile uint32_t _pad_0x520_0x583[25]; /* *UNDEFINED* */
74938  ALT_EMAC_GMAC_VLAN_INCL_REG_t gmacgrp_vlan_incl_reg; /* ALT_EMAC_GMAC_VLAN_INCL_REG */
74939  ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_t gmacgrp_vlan_hash_table_reg; /* ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG */
74940  volatile uint32_t _pad_0x58c_0x6ff[93]; /* *UNDEFINED* */
74941  ALT_EMAC_GMAC_TS_CTL_t gmacgrp_timestamp_control; /* ALT_EMAC_GMAC_TS_CTL */
74942  ALT_EMAC_GMAC_SUB_SEC_INCREMENT_t gmacgrp_sub_second_increment; /* ALT_EMAC_GMAC_SUB_SEC_INCREMENT */
74943  ALT_EMAC_GMAC_SYS_TIME_SECS_t gmacgrp_system_time_seconds; /* ALT_EMAC_GMAC_SYS_TIME_SECS */
74944  ALT_EMAC_GMAC_SYS_TIME_NANOSECS_t gmacgrp_system_time_nanoseconds; /* ALT_EMAC_GMAC_SYS_TIME_NANOSECS */
74945  ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_t gmacgrp_system_time_seconds_update; /* ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE */
74946  ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_t gmacgrp_system_time_nanoseconds_update; /* ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE */
74947  ALT_EMAC_GMAC_TS_ADDEND_t gmacgrp_timestamp_addend; /* ALT_EMAC_GMAC_TS_ADDEND */
74948  ALT_EMAC_GMAC_TGT_TIME_SECS_t gmacgrp_target_time_seconds; /* ALT_EMAC_GMAC_TGT_TIME_SECS */
74949  ALT_EMAC_GMAC_TGT_TIME_NANOSECS_t gmacgrp_target_time_nanoseconds; /* ALT_EMAC_GMAC_TGT_TIME_NANOSECS */
74950  ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_t gmacgrp_system_time_higher_word_seconds; /* ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS */
74951  ALT_EMAC_GMAC_TS_STAT_t gmacgrp_timestamp_status; /* ALT_EMAC_GMAC_TS_STAT */
74952  ALT_EMAC_GMAC_PPS_CTL_t gmacgrp_pps_control; /* ALT_EMAC_GMAC_PPS_CTL */
74953  ALT_EMAC_GMAC_AUX_TS_NANOSECS_t gmacgrp_auxiliary_timestamp_nanoseconds; /* ALT_EMAC_GMAC_AUX_TS_NANOSECS */
74954  ALT_EMAC_GMAC_AUX_TS_SECS_t gmacgrp_auxiliary_timestamp_seconds; /* ALT_EMAC_GMAC_AUX_TS_SECS */
74955  volatile uint32_t _pad_0x738_0x75f[10]; /* *UNDEFINED* */
74956  ALT_EMAC_GMAC_PPS0_INTERVAL_t gmacgrp_pps0_interval; /* ALT_EMAC_GMAC_PPS0_INTERVAL */
74957  ALT_EMAC_GMAC_PPS0_WIDTH_t gmacgrp_pps0_width; /* ALT_EMAC_GMAC_PPS0_WIDTH */
74958  volatile uint32_t _pad_0x768_0x7ff[38]; /* *UNDEFINED* */
74959  ALT_EMAC_GMAC_MAC_ADDR16_HIGH_t gmacgrp_mac_address16_high; /* ALT_EMAC_GMAC_MAC_ADDR16_HIGH */
74960  ALT_EMAC_GMAC_MAC_ADDR16_LOW_t gmacgrp_mac_address16_low; /* ALT_EMAC_GMAC_MAC_ADDR16_LOW */
74961  ALT_EMAC_GMAC_MAC_ADDR17_HIGH_t gmacgrp_mac_address17_high; /* ALT_EMAC_GMAC_MAC_ADDR17_HIGH */
74962  ALT_EMAC_GMAC_MAC_ADDR17_LOW_t gmacgrp_mac_address17_low; /* ALT_EMAC_GMAC_MAC_ADDR17_LOW */
74963  ALT_EMAC_GMAC_MAC_ADDR18_HIGH_t gmacgrp_mac_address18_high; /* ALT_EMAC_GMAC_MAC_ADDR18_HIGH */
74964  ALT_EMAC_GMAC_MAC_ADDR18_LOW_t gmacgrp_mac_address18_low; /* ALT_EMAC_GMAC_MAC_ADDR18_LOW */
74965  ALT_EMAC_GMAC_MAC_ADDR19_HIGH_t gmacgrp_mac_address19_high; /* ALT_EMAC_GMAC_MAC_ADDR19_HIGH */
74966  ALT_EMAC_GMAC_MAC_ADDR19_LOW_t gmacgrp_mac_address19_low; /* ALT_EMAC_GMAC_MAC_ADDR19_LOW */
74967  ALT_EMAC_GMAC_MAC_ADDR20_HIGH_t gmacgrp_mac_address20_high; /* ALT_EMAC_GMAC_MAC_ADDR20_HIGH */
74968  ALT_EMAC_GMAC_MAC_ADDR20_LOW_t gmacgrp_mac_address20_low; /* ALT_EMAC_GMAC_MAC_ADDR20_LOW */
74969  ALT_EMAC_GMAC_MAC_ADDR21_HIGH_t gmacgrp_mac_address21_high; /* ALT_EMAC_GMAC_MAC_ADDR21_HIGH */
74970  ALT_EMAC_GMAC_MAC_ADDR21_LOW_t gmacgrp_mac_address21_low; /* ALT_EMAC_GMAC_MAC_ADDR21_LOW */
74971  ALT_EMAC_GMAC_MAC_ADDR22_HIGH_t gmacgrp_mac_address22_high; /* ALT_EMAC_GMAC_MAC_ADDR22_HIGH */
74972  ALT_EMAC_GMAC_MAC_ADDR22_LOW_t gmacgrp_mac_address22_low; /* ALT_EMAC_GMAC_MAC_ADDR22_LOW */
74973  ALT_EMAC_GMAC_MAC_ADDR23_HIGH_t gmacgrp_mac_address23_high; /* ALT_EMAC_GMAC_MAC_ADDR23_HIGH */
74974  ALT_EMAC_GMAC_MAC_ADDR23_LOW_t gmacgrp_mac_address23_low; /* ALT_EMAC_GMAC_MAC_ADDR23_LOW */
74975  ALT_EMAC_GMAC_MAC_ADDR24_HIGH_t gmacgrp_mac_address24_high; /* ALT_EMAC_GMAC_MAC_ADDR24_HIGH */
74976  ALT_EMAC_GMAC_MAC_ADDR24_LOW_t gmacgrp_mac_address24_low; /* ALT_EMAC_GMAC_MAC_ADDR24_LOW */
74977  ALT_EMAC_GMAC_MAC_ADDR25_HIGH_t gmacgrp_mac_address25_high; /* ALT_EMAC_GMAC_MAC_ADDR25_HIGH */
74978  ALT_EMAC_GMAC_MAC_ADDR25_LOW_t gmacgrp_mac_address25_low; /* ALT_EMAC_GMAC_MAC_ADDR25_LOW */
74979  ALT_EMAC_GMAC_MAC_ADDR26_HIGH_t gmacgrp_mac_address26_high; /* ALT_EMAC_GMAC_MAC_ADDR26_HIGH */
74980  ALT_EMAC_GMAC_MAC_ADDR26_LOW_t gmacgrp_mac_address26_low; /* ALT_EMAC_GMAC_MAC_ADDR26_LOW */
74981  ALT_EMAC_GMAC_MAC_ADDR27_HIGH_t gmacgrp_mac_address27_high; /* ALT_EMAC_GMAC_MAC_ADDR27_HIGH */
74982  ALT_EMAC_GMAC_MAC_ADDR27_LOW_t gmacgrp_mac_address27_low; /* ALT_EMAC_GMAC_MAC_ADDR27_LOW */
74983  ALT_EMAC_GMAC_MAC_ADDR28_HIGH_t gmacgrp_mac_address28_high; /* ALT_EMAC_GMAC_MAC_ADDR28_HIGH */
74984  ALT_EMAC_GMAC_MAC_ADDR28_LOW_t gmacgrp_mac_address28_low; /* ALT_EMAC_GMAC_MAC_ADDR28_LOW */
74985  ALT_EMAC_GMAC_MAC_ADDR29_HIGH_t gmacgrp_mac_address29_high; /* ALT_EMAC_GMAC_MAC_ADDR29_HIGH */
74986  ALT_EMAC_GMAC_MAC_ADDR29_LOW_t gmacgrp_mac_address29_low; /* ALT_EMAC_GMAC_MAC_ADDR29_LOW */
74987  ALT_EMAC_GMAC_MAC_ADDR30_HIGH_t gmacgrp_mac_address30_high; /* ALT_EMAC_GMAC_MAC_ADDR30_HIGH */
74988  ALT_EMAC_GMAC_MAC_ADDR30_LOW_t gmacgrp_mac_address30_low; /* ALT_EMAC_GMAC_MAC_ADDR30_LOW */
74989  ALT_EMAC_GMAC_MAC_ADDR31_HIGH_t gmacgrp_mac_address31_high; /* ALT_EMAC_GMAC_MAC_ADDR31_HIGH */
74990  ALT_EMAC_GMAC_MAC_ADDR31_LOW_t gmacgrp_mac_address31_low; /* ALT_EMAC_GMAC_MAC_ADDR31_LOW */
74991  ALT_EMAC_GMAC_MAC_ADDR32_HIGH_t gmacgrp_mac_address32_high; /* ALT_EMAC_GMAC_MAC_ADDR32_HIGH */
74992  ALT_EMAC_GMAC_MAC_ADDR32_LOW_t gmacgrp_mac_address32_low; /* ALT_EMAC_GMAC_MAC_ADDR32_LOW */
74993  ALT_EMAC_GMAC_MAC_ADDR33_HIGH_t gmacgrp_mac_address33_high; /* ALT_EMAC_GMAC_MAC_ADDR33_HIGH */
74994  ALT_EMAC_GMAC_MAC_ADDR33_LOW_t gmacgrp_mac_address33_low; /* ALT_EMAC_GMAC_MAC_ADDR33_LOW */
74995  ALT_EMAC_GMAC_MAC_ADDR34_HIGH_t gmacgrp_mac_address34_high; /* ALT_EMAC_GMAC_MAC_ADDR34_HIGH */
74996  ALT_EMAC_GMAC_MAC_ADDR34_LOW_t gmacgrp_mac_address34_low; /* ALT_EMAC_GMAC_MAC_ADDR34_LOW */
74997  ALT_EMAC_GMAC_MAC_ADDR35_HIGH_t gmacgrp_mac_address35_high; /* ALT_EMAC_GMAC_MAC_ADDR35_HIGH */
74998  ALT_EMAC_GMAC_MAC_ADDR35_LOW_t gmacgrp_mac_address35_low; /* ALT_EMAC_GMAC_MAC_ADDR35_LOW */
74999  ALT_EMAC_GMAC_MAC_ADDR36_HIGH_t gmacgrp_mac_address36_high; /* ALT_EMAC_GMAC_MAC_ADDR36_HIGH */
75000  ALT_EMAC_GMAC_MAC_ADDR36_LOW_t gmacgrp_mac_address36_low; /* ALT_EMAC_GMAC_MAC_ADDR36_LOW */
75001  ALT_EMAC_GMAC_MAC_ADDR37_HIGH_t gmacgrp_mac_address37_high; /* ALT_EMAC_GMAC_MAC_ADDR37_HIGH */
75002  ALT_EMAC_GMAC_MAC_ADDR37_LOW_t gmacgrp_mac_address37_low; /* ALT_EMAC_GMAC_MAC_ADDR37_LOW */
75003  ALT_EMAC_GMAC_MAC_ADDR38_HIGH_t gmacgrp_mac_address38_high; /* ALT_EMAC_GMAC_MAC_ADDR38_HIGH */
75004  ALT_EMAC_GMAC_MAC_ADDR38_LOW_t gmacgrp_mac_address38_low; /* ALT_EMAC_GMAC_MAC_ADDR38_LOW */
75005  ALT_EMAC_GMAC_MAC_ADDR39_HIGH_t gmacgrp_mac_address39_high; /* ALT_EMAC_GMAC_MAC_ADDR39_HIGH */
75006  ALT_EMAC_GMAC_MAC_ADDR39_LOW_t gmacgrp_mac_address39_low; /* ALT_EMAC_GMAC_MAC_ADDR39_LOW */
75007  ALT_EMAC_GMAC_MAC_ADDR40_HIGH_t gmacgrp_mac_address40_high; /* ALT_EMAC_GMAC_MAC_ADDR40_HIGH */
75008  ALT_EMAC_GMAC_MAC_ADDR40_LOW_t gmacgrp_mac_address40_low; /* ALT_EMAC_GMAC_MAC_ADDR40_LOW */
75009  ALT_EMAC_GMAC_MAC_ADDR41_HIGH_t gmacgrp_mac_address41_high; /* ALT_EMAC_GMAC_MAC_ADDR41_HIGH */
75010  ALT_EMAC_GMAC_MAC_ADDR41_LOW_t gmacgrp_mac_address41_low; /* ALT_EMAC_GMAC_MAC_ADDR41_LOW */
75011  ALT_EMAC_GMAC_MAC_ADDR42_HIGH_t gmacgrp_mac_address42_high; /* ALT_EMAC_GMAC_MAC_ADDR42_HIGH */
75012  ALT_EMAC_GMAC_MAC_ADDR42_LOW_t gmacgrp_mac_address42_low; /* ALT_EMAC_GMAC_MAC_ADDR42_LOW */
75013  ALT_EMAC_GMAC_MAC_ADDR43_HIGH_t gmacgrp_mac_address43_high; /* ALT_EMAC_GMAC_MAC_ADDR43_HIGH */
75014  ALT_EMAC_GMAC_MAC_ADDR43_LOW_t gmacgrp_mac_address43_low; /* ALT_EMAC_GMAC_MAC_ADDR43_LOW */
75015  ALT_EMAC_GMAC_MAC_ADDR44_HIGH_t gmacgrp_mac_address44_high; /* ALT_EMAC_GMAC_MAC_ADDR44_HIGH */
75016  ALT_EMAC_GMAC_MAC_ADDR44_LOW_t gmacgrp_mac_address44_low; /* ALT_EMAC_GMAC_MAC_ADDR44_LOW */
75017  ALT_EMAC_GMAC_MAC_ADDR45_HIGH_t gmacgrp_mac_address45_high; /* ALT_EMAC_GMAC_MAC_ADDR45_HIGH */
75018  ALT_EMAC_GMAC_MAC_ADDR45_LOW_t gmacgrp_mac_address45_low; /* ALT_EMAC_GMAC_MAC_ADDR45_LOW */
75019  ALT_EMAC_GMAC_MAC_ADDR46_HIGH_t gmacgrp_mac_address46_high; /* ALT_EMAC_GMAC_MAC_ADDR46_HIGH */
75020  ALT_EMAC_GMAC_MAC_ADDR46_LOW_t gmacgrp_mac_address46_low; /* ALT_EMAC_GMAC_MAC_ADDR46_LOW */
75021  ALT_EMAC_GMAC_MAC_ADDR47_HIGH_t gmacgrp_mac_address47_high; /* ALT_EMAC_GMAC_MAC_ADDR47_HIGH */
75022  ALT_EMAC_GMAC_MAC_ADDR47_LOW_t gmacgrp_mac_address47_low; /* ALT_EMAC_GMAC_MAC_ADDR47_LOW */
75023  ALT_EMAC_GMAC_MAC_ADDR48_HIGH_t gmacgrp_mac_address48_high; /* ALT_EMAC_GMAC_MAC_ADDR48_HIGH */
75024  ALT_EMAC_GMAC_MAC_ADDR48_LOW_t gmacgrp_mac_address48_low; /* ALT_EMAC_GMAC_MAC_ADDR48_LOW */
75025  ALT_EMAC_GMAC_MAC_ADDR49_HIGH_t gmacgrp_mac_address49_high; /* ALT_EMAC_GMAC_MAC_ADDR49_HIGH */
75026  ALT_EMAC_GMAC_MAC_ADDR49_LOW_t gmacgrp_mac_address49_low; /* ALT_EMAC_GMAC_MAC_ADDR49_LOW */
75027  ALT_EMAC_GMAC_MAC_ADDR50_HIGH_t gmacgrp_mac_address50_high; /* ALT_EMAC_GMAC_MAC_ADDR50_HIGH */
75028  ALT_EMAC_GMAC_MAC_ADDR50_LOW_t gmacgrp_mac_address50_low; /* ALT_EMAC_GMAC_MAC_ADDR50_LOW */
75029  ALT_EMAC_GMAC_MAC_ADDR51_HIGH_t gmacgrp_mac_address51_high; /* ALT_EMAC_GMAC_MAC_ADDR51_HIGH */
75030  ALT_EMAC_GMAC_MAC_ADDR51_LOW_t gmacgrp_mac_address51_low; /* ALT_EMAC_GMAC_MAC_ADDR51_LOW */
75031  ALT_EMAC_GMAC_MAC_ADDR52_HIGH_t gmacgrp_mac_address52_high; /* ALT_EMAC_GMAC_MAC_ADDR52_HIGH */
75032  ALT_EMAC_GMAC_MAC_ADDR52_LOW_t gmacgrp_mac_address52_low; /* ALT_EMAC_GMAC_MAC_ADDR52_LOW */
75033  ALT_EMAC_GMAC_MAC_ADDR53_HIGH_t gmacgrp_mac_address53_high; /* ALT_EMAC_GMAC_MAC_ADDR53_HIGH */
75034  ALT_EMAC_GMAC_MAC_ADDR53_LOW_t gmacgrp_mac_address53_low; /* ALT_EMAC_GMAC_MAC_ADDR53_LOW */
75035  ALT_EMAC_GMAC_MAC_ADDR54_HIGH_t gmacgrp_mac_address54_high; /* ALT_EMAC_GMAC_MAC_ADDR54_HIGH */
75036  ALT_EMAC_GMAC_MAC_ADDR54_LOW_t gmacgrp_mac_address54_low; /* ALT_EMAC_GMAC_MAC_ADDR54_LOW */
75037  ALT_EMAC_GMAC_MAC_ADDR55_HIGH_t gmacgrp_mac_address55_high; /* ALT_EMAC_GMAC_MAC_ADDR55_HIGH */
75038  ALT_EMAC_GMAC_MAC_ADDR55_LOW_t gmacgrp_mac_address55_low; /* ALT_EMAC_GMAC_MAC_ADDR55_LOW */
75039  ALT_EMAC_GMAC_MAC_ADDR56_HIGH_t gmacgrp_mac_address56_high; /* ALT_EMAC_GMAC_MAC_ADDR56_HIGH */
75040  ALT_EMAC_GMAC_MAC_ADDR56_LOW_t gmacgrp_mac_address56_low; /* ALT_EMAC_GMAC_MAC_ADDR56_LOW */
75041  ALT_EMAC_GMAC_MAC_ADDR57_HIGH_t gmacgrp_mac_address57_high; /* ALT_EMAC_GMAC_MAC_ADDR57_HIGH */
75042  ALT_EMAC_GMAC_MAC_ADDR57_LOW_t gmacgrp_mac_address57_low; /* ALT_EMAC_GMAC_MAC_ADDR57_LOW */
75043  ALT_EMAC_GMAC_MAC_ADDR58_HIGH_t gmacgrp_mac_address58_high; /* ALT_EMAC_GMAC_MAC_ADDR58_HIGH */
75044  ALT_EMAC_GMAC_MAC_ADDR58_LOW_t gmacgrp_mac_address58_low; /* ALT_EMAC_GMAC_MAC_ADDR58_LOW */
75045  ALT_EMAC_GMAC_MAC_ADDR59_HIGH_t gmacgrp_mac_address59_high; /* ALT_EMAC_GMAC_MAC_ADDR59_HIGH */
75046  ALT_EMAC_GMAC_MAC_ADDR59_LOW_t gmacgrp_mac_address59_low; /* ALT_EMAC_GMAC_MAC_ADDR59_LOW */
75047  ALT_EMAC_GMAC_MAC_ADDR60_HIGH_t gmacgrp_mac_address60_high; /* ALT_EMAC_GMAC_MAC_ADDR60_HIGH */
75048  ALT_EMAC_GMAC_MAC_ADDR60_LOW_t gmacgrp_mac_address60_low; /* ALT_EMAC_GMAC_MAC_ADDR60_LOW */
75049  ALT_EMAC_GMAC_MAC_ADDR61_HIGH_t gmacgrp_mac_address61_high; /* ALT_EMAC_GMAC_MAC_ADDR61_HIGH */
75050  ALT_EMAC_GMAC_MAC_ADDR61_LOW_t gmacgrp_mac_address61_low; /* ALT_EMAC_GMAC_MAC_ADDR61_LOW */
75051  ALT_EMAC_GMAC_MAC_ADDR62_HIGH_t gmacgrp_mac_address62_high; /* ALT_EMAC_GMAC_MAC_ADDR62_HIGH */
75052  ALT_EMAC_GMAC_MAC_ADDR62_LOW_t gmacgrp_mac_address62_low; /* ALT_EMAC_GMAC_MAC_ADDR62_LOW */
75053  ALT_EMAC_GMAC_MAC_ADDR63_HIGH_t gmacgrp_mac_address63_high; /* ALT_EMAC_GMAC_MAC_ADDR63_HIGH */
75054  ALT_EMAC_GMAC_MAC_ADDR63_LOW_t gmacgrp_mac_address63_low; /* ALT_EMAC_GMAC_MAC_ADDR63_LOW */
75055  ALT_EMAC_GMAC_MAC_ADDR64_HIGH_t gmacgrp_mac_address64_high; /* ALT_EMAC_GMAC_MAC_ADDR64_HIGH */
75056  ALT_EMAC_GMAC_MAC_ADDR64_LOW_t gmacgrp_mac_address64_low; /* ALT_EMAC_GMAC_MAC_ADDR64_LOW */
75057  ALT_EMAC_GMAC_MAC_ADDR65_HIGH_t gmacgrp_mac_address65_high; /* ALT_EMAC_GMAC_MAC_ADDR65_HIGH */
75058  ALT_EMAC_GMAC_MAC_ADDR65_LOW_t gmacgrp_mac_address65_low; /* ALT_EMAC_GMAC_MAC_ADDR65_LOW */
75059  ALT_EMAC_GMAC_MAC_ADDR66_HIGH_t gmacgrp_mac_address66_high; /* ALT_EMAC_GMAC_MAC_ADDR66_HIGH */
75060  ALT_EMAC_GMAC_MAC_ADDR66_LOW_t gmacgrp_mac_address66_low; /* ALT_EMAC_GMAC_MAC_ADDR66_LOW */
75061  ALT_EMAC_GMAC_MAC_ADDR67_HIGH_t gmacgrp_mac_address67_high; /* ALT_EMAC_GMAC_MAC_ADDR67_HIGH */
75062  ALT_EMAC_GMAC_MAC_ADDR67_LOW_t gmacgrp_mac_address67_low; /* ALT_EMAC_GMAC_MAC_ADDR67_LOW */
75063  ALT_EMAC_GMAC_MAC_ADDR68_HIGH_t gmacgrp_mac_address68_high; /* ALT_EMAC_GMAC_MAC_ADDR68_HIGH */
75064  ALT_EMAC_GMAC_MAC_ADDR68_LOW_t gmacgrp_mac_address68_low; /* ALT_EMAC_GMAC_MAC_ADDR68_LOW */
75065  ALT_EMAC_GMAC_MAC_ADDR69_HIGH_t gmacgrp_mac_address69_high; /* ALT_EMAC_GMAC_MAC_ADDR69_HIGH */
75066  ALT_EMAC_GMAC_MAC_ADDR69_LOW_t gmacgrp_mac_address69_low; /* ALT_EMAC_GMAC_MAC_ADDR69_LOW */
75067  ALT_EMAC_GMAC_MAC_ADDR70_HIGH_t gmacgrp_mac_address70_high; /* ALT_EMAC_GMAC_MAC_ADDR70_HIGH */
75068  ALT_EMAC_GMAC_MAC_ADDR70_LOW_t gmacgrp_mac_address70_low; /* ALT_EMAC_GMAC_MAC_ADDR70_LOW */
75069  ALT_EMAC_GMAC_MAC_ADDR71_HIGH_t gmacgrp_mac_address71_high; /* ALT_EMAC_GMAC_MAC_ADDR71_HIGH */
75070  ALT_EMAC_GMAC_MAC_ADDR71_LOW_t gmacgrp_mac_address71_low; /* ALT_EMAC_GMAC_MAC_ADDR71_LOW */
75071  ALT_EMAC_GMAC_MAC_ADDR72_HIGH_t gmacgrp_mac_address72_high; /* ALT_EMAC_GMAC_MAC_ADDR72_HIGH */
75072  ALT_EMAC_GMAC_MAC_ADDR72_LOW_t gmacgrp_mac_address72_low; /* ALT_EMAC_GMAC_MAC_ADDR72_LOW */
75073  ALT_EMAC_GMAC_MAC_ADDR73_HIGH_t gmacgrp_mac_address73_high; /* ALT_EMAC_GMAC_MAC_ADDR73_HIGH */
75074  ALT_EMAC_GMAC_MAC_ADDR73_LOW_t gmacgrp_mac_address73_low; /* ALT_EMAC_GMAC_MAC_ADDR73_LOW */
75075  ALT_EMAC_GMAC_MAC_ADDR74_HIGH_t gmacgrp_mac_address74_high; /* ALT_EMAC_GMAC_MAC_ADDR74_HIGH */
75076  ALT_EMAC_GMAC_MAC_ADDR74_LOW_t gmacgrp_mac_address74_low; /* ALT_EMAC_GMAC_MAC_ADDR74_LOW */
75077  ALT_EMAC_GMAC_MAC_ADDR75_HIGH_t gmacgrp_mac_address75_high; /* ALT_EMAC_GMAC_MAC_ADDR75_HIGH */
75078  ALT_EMAC_GMAC_MAC_ADDR75_LOW_t gmacgrp_mac_address75_low; /* ALT_EMAC_GMAC_MAC_ADDR75_LOW */
75079  ALT_EMAC_GMAC_MAC_ADDR76_HIGH_t gmacgrp_mac_address76_high; /* ALT_EMAC_GMAC_MAC_ADDR76_HIGH */
75080  ALT_EMAC_GMAC_MAC_ADDR76_LOW_t gmacgrp_mac_address76_low; /* ALT_EMAC_GMAC_MAC_ADDR76_LOW */
75081  ALT_EMAC_GMAC_MAC_ADDR77_HIGH_t gmacgrp_mac_address77_high; /* ALT_EMAC_GMAC_MAC_ADDR77_HIGH */
75082  ALT_EMAC_GMAC_MAC_ADDR77_LOW_t gmacgrp_mac_address77_low; /* ALT_EMAC_GMAC_MAC_ADDR77_LOW */
75083  ALT_EMAC_GMAC_MAC_ADDR78_HIGH_t gmacgrp_mac_address78_high; /* ALT_EMAC_GMAC_MAC_ADDR78_HIGH */
75084  ALT_EMAC_GMAC_MAC_ADDR78_LOW_t gmacgrp_mac_address78_low; /* ALT_EMAC_GMAC_MAC_ADDR78_LOW */
75085  ALT_EMAC_GMAC_MAC_ADDR79_HIGH_t gmacgrp_mac_address79_high; /* ALT_EMAC_GMAC_MAC_ADDR79_HIGH */
75086  ALT_EMAC_GMAC_MAC_ADDR79_LOW_t gmacgrp_mac_address79_low; /* ALT_EMAC_GMAC_MAC_ADDR79_LOW */
75087  ALT_EMAC_GMAC_MAC_ADDR80_HIGH_t gmacgrp_mac_address80_high; /* ALT_EMAC_GMAC_MAC_ADDR80_HIGH */
75088  ALT_EMAC_GMAC_MAC_ADDR80_LOW_t gmacgrp_mac_address80_low; /* ALT_EMAC_GMAC_MAC_ADDR80_LOW */
75089  ALT_EMAC_GMAC_MAC_ADDR81_HIGH_t gmacgrp_mac_address81_high; /* ALT_EMAC_GMAC_MAC_ADDR81_HIGH */
75090  ALT_EMAC_GMAC_MAC_ADDR81_LOW_t gmacgrp_mac_address81_low; /* ALT_EMAC_GMAC_MAC_ADDR81_LOW */
75091  ALT_EMAC_GMAC_MAC_ADDR82_HIGH_t gmacgrp_mac_address82_high; /* ALT_EMAC_GMAC_MAC_ADDR82_HIGH */
75092  ALT_EMAC_GMAC_MAC_ADDR82_LOW_t gmacgrp_mac_address82_low; /* ALT_EMAC_GMAC_MAC_ADDR82_LOW */
75093  ALT_EMAC_GMAC_MAC_ADDR83_HIGH_t gmacgrp_mac_address83_high; /* ALT_EMAC_GMAC_MAC_ADDR83_HIGH */
75094  ALT_EMAC_GMAC_MAC_ADDR83_LOW_t gmacgrp_mac_address83_low; /* ALT_EMAC_GMAC_MAC_ADDR83_LOW */
75095  ALT_EMAC_GMAC_MAC_ADDR84_HIGH_t gmacgrp_mac_address84_high; /* ALT_EMAC_GMAC_MAC_ADDR84_HIGH */
75096  ALT_EMAC_GMAC_MAC_ADDR84_LOW_t gmacgrp_mac_address84_low; /* ALT_EMAC_GMAC_MAC_ADDR84_LOW */
75097  ALT_EMAC_GMAC_MAC_ADDR85_HIGH_t gmacgrp_mac_address85_high; /* ALT_EMAC_GMAC_MAC_ADDR85_HIGH */
75098  ALT_EMAC_GMAC_MAC_ADDR85_LOW_t gmacgrp_mac_address85_low; /* ALT_EMAC_GMAC_MAC_ADDR85_LOW */
75099  ALT_EMAC_GMAC_MAC_ADDR86_HIGH_t gmacgrp_mac_address86_high; /* ALT_EMAC_GMAC_MAC_ADDR86_HIGH */
75100  ALT_EMAC_GMAC_MAC_ADDR86_LOW_t gmacgrp_mac_address86_low; /* ALT_EMAC_GMAC_MAC_ADDR86_LOW */
75101  ALT_EMAC_GMAC_MAC_ADDR87_HIGH_t gmacgrp_mac_address87_high; /* ALT_EMAC_GMAC_MAC_ADDR87_HIGH */
75102  ALT_EMAC_GMAC_MAC_ADDR87_LOW_t gmacgrp_mac_address87_low; /* ALT_EMAC_GMAC_MAC_ADDR87_LOW */
75103  ALT_EMAC_GMAC_MAC_ADDR88_HIGH_t gmacgrp_mac_address88_high; /* ALT_EMAC_GMAC_MAC_ADDR88_HIGH */
75104  ALT_EMAC_GMAC_MAC_ADDR88_LOW_t gmacgrp_mac_address88_low; /* ALT_EMAC_GMAC_MAC_ADDR88_LOW */
75105  ALT_EMAC_GMAC_MAC_ADDR89_HIGH_t gmacgrp_mac_address89_high; /* ALT_EMAC_GMAC_MAC_ADDR89_HIGH */
75106  ALT_EMAC_GMAC_MAC_ADDR89_LOW_t gmacgrp_mac_address89_low; /* ALT_EMAC_GMAC_MAC_ADDR89_LOW */
75107  ALT_EMAC_GMAC_MAC_ADDR90_HIGH_t gmacgrp_mac_address90_high; /* ALT_EMAC_GMAC_MAC_ADDR90_HIGH */
75108  ALT_EMAC_GMAC_MAC_ADDR90_LOW_t gmacgrp_mac_address90_low; /* ALT_EMAC_GMAC_MAC_ADDR90_LOW */
75109  ALT_EMAC_GMAC_MAC_ADDR91_HIGH_t gmacgrp_mac_address91_high; /* ALT_EMAC_GMAC_MAC_ADDR91_HIGH */
75110  ALT_EMAC_GMAC_MAC_ADDR91_LOW_t gmacgrp_mac_address91_low; /* ALT_EMAC_GMAC_MAC_ADDR91_LOW */
75111  ALT_EMAC_GMAC_MAC_ADDR92_HIGH_t gmacgrp_mac_address92_high; /* ALT_EMAC_GMAC_MAC_ADDR92_HIGH */
75112  ALT_EMAC_GMAC_MAC_ADDR92_LOW_t gmacgrp_mac_address92_low; /* ALT_EMAC_GMAC_MAC_ADDR92_LOW */
75113  ALT_EMAC_GMAC_MAC_ADDR93_HIGH_t gmacgrp_mac_address93_high; /* ALT_EMAC_GMAC_MAC_ADDR93_HIGH */
75114  ALT_EMAC_GMAC_MAC_ADDR93_LOW_t gmacgrp_mac_address93_low; /* ALT_EMAC_GMAC_MAC_ADDR93_LOW */
75115  ALT_EMAC_GMAC_MAC_ADDR94_HIGH_t gmacgrp_mac_address94_high; /* ALT_EMAC_GMAC_MAC_ADDR94_HIGH */
75116  ALT_EMAC_GMAC_MAC_ADDR94_LOW_t gmacgrp_mac_address94_low; /* ALT_EMAC_GMAC_MAC_ADDR94_LOW */
75117  ALT_EMAC_GMAC_MAC_ADDR95_HIGH_t gmacgrp_mac_address95_high; /* ALT_EMAC_GMAC_MAC_ADDR95_HIGH */
75118  ALT_EMAC_GMAC_MAC_ADDR95_LOW_t gmacgrp_mac_address95_low; /* ALT_EMAC_GMAC_MAC_ADDR95_LOW */
75119  ALT_EMAC_GMAC_MAC_ADDR96_HIGH_t gmacgrp_mac_address96_high; /* ALT_EMAC_GMAC_MAC_ADDR96_HIGH */
75120  ALT_EMAC_GMAC_MAC_ADDR96_LOW_t gmacgrp_mac_address96_low; /* ALT_EMAC_GMAC_MAC_ADDR96_LOW */
75121  ALT_EMAC_GMAC_MAC_ADDR97_HIGH_t gmacgrp_mac_address97_high; /* ALT_EMAC_GMAC_MAC_ADDR97_HIGH */
75122  ALT_EMAC_GMAC_MAC_ADDR97_LOW_t gmacgrp_mac_address97_low; /* ALT_EMAC_GMAC_MAC_ADDR97_LOW */
75123  ALT_EMAC_GMAC_MAC_ADDR98_HIGH_t gmacgrp_mac_address98_high; /* ALT_EMAC_GMAC_MAC_ADDR98_HIGH */
75124  ALT_EMAC_GMAC_MAC_ADDR98_LOW_t gmacgrp_mac_address98_low; /* ALT_EMAC_GMAC_MAC_ADDR98_LOW */
75125  ALT_EMAC_GMAC_MAC_ADDR99_HIGH_t gmacgrp_mac_address99_high; /* ALT_EMAC_GMAC_MAC_ADDR99_HIGH */
75126  ALT_EMAC_GMAC_MAC_ADDR99_LOW_t gmacgrp_mac_address99_low; /* ALT_EMAC_GMAC_MAC_ADDR99_LOW */
75127  ALT_EMAC_GMAC_MAC_ADDR100_HIGH_t gmacgrp_mac_address100_high; /* ALT_EMAC_GMAC_MAC_ADDR100_HIGH */
75128  ALT_EMAC_GMAC_MAC_ADDR100_LOW_t gmacgrp_mac_address100_low; /* ALT_EMAC_GMAC_MAC_ADDR100_LOW */
75129  ALT_EMAC_GMAC_MAC_ADDR101_HIGH_t gmacgrp_mac_address101_high; /* ALT_EMAC_GMAC_MAC_ADDR101_HIGH */
75130  ALT_EMAC_GMAC_MAC_ADDR101_LOW_t gmacgrp_mac_address101_low; /* ALT_EMAC_GMAC_MAC_ADDR101_LOW */
75131  ALT_EMAC_GMAC_MAC_ADDR102_HIGH_t gmacgrp_mac_address102_high; /* ALT_EMAC_GMAC_MAC_ADDR102_HIGH */
75132  ALT_EMAC_GMAC_MAC_ADDR102_LOW_t gmacgrp_mac_address102_low; /* ALT_EMAC_GMAC_MAC_ADDR102_LOW */
75133  ALT_EMAC_GMAC_MAC_ADDR103_HIGH_t gmacgrp_mac_address103_high; /* ALT_EMAC_GMAC_MAC_ADDR103_HIGH */
75134  ALT_EMAC_GMAC_MAC_ADDR103_LOW_t gmacgrp_mac_address103_low; /* ALT_EMAC_GMAC_MAC_ADDR103_LOW */
75135  ALT_EMAC_GMAC_MAC_ADDR104_HIGH_t gmacgrp_mac_address104_high; /* ALT_EMAC_GMAC_MAC_ADDR104_HIGH */
75136  ALT_EMAC_GMAC_MAC_ADDR104_LOW_t gmacgrp_mac_address104_low; /* ALT_EMAC_GMAC_MAC_ADDR104_LOW */
75137  ALT_EMAC_GMAC_MAC_ADDR105_HIGH_t gmacgrp_mac_address105_high; /* ALT_EMAC_GMAC_MAC_ADDR105_HIGH */
75138  ALT_EMAC_GMAC_MAC_ADDR105_LOW_t gmacgrp_mac_address105_low; /* ALT_EMAC_GMAC_MAC_ADDR105_LOW */
75139  ALT_EMAC_GMAC_MAC_ADDR106_HIGH_t gmacgrp_mac_address106_high; /* ALT_EMAC_GMAC_MAC_ADDR106_HIGH */
75140  ALT_EMAC_GMAC_MAC_ADDR106_LOW_t gmacgrp_mac_address106_low; /* ALT_EMAC_GMAC_MAC_ADDR106_LOW */
75141  ALT_EMAC_GMAC_MAC_ADDR107_HIGH_t gmacgrp_mac_address107_high; /* ALT_EMAC_GMAC_MAC_ADDR107_HIGH */
75142  ALT_EMAC_GMAC_MAC_ADDR107_LOW_t gmacgrp_mac_address107_low; /* ALT_EMAC_GMAC_MAC_ADDR107_LOW */
75143  ALT_EMAC_GMAC_MAC_ADDR108_HIGH_t gmacgrp_mac_address108_high; /* ALT_EMAC_GMAC_MAC_ADDR108_HIGH */
75144  ALT_EMAC_GMAC_MAC_ADDR108_LOW_t gmacgrp_mac_address108_low; /* ALT_EMAC_GMAC_MAC_ADDR108_LOW */
75145  ALT_EMAC_GMAC_MAC_ADDR109_HIGH_t gmacgrp_mac_address109_high; /* ALT_EMAC_GMAC_MAC_ADDR109_HIGH */
75146  ALT_EMAC_GMAC_MAC_ADDR109_LOW_t gmacgrp_mac_address109_low; /* ALT_EMAC_GMAC_MAC_ADDR109_LOW */
75147  ALT_EMAC_GMAC_MAC_ADDR110_HIGH_t gmacgrp_mac_address110_high; /* ALT_EMAC_GMAC_MAC_ADDR110_HIGH */
75148  ALT_EMAC_GMAC_MAC_ADDR110_LOW_t gmacgrp_mac_address110_low; /* ALT_EMAC_GMAC_MAC_ADDR110_LOW */
75149  ALT_EMAC_GMAC_MAC_ADDR111_HIGH_t gmacgrp_mac_address111_high; /* ALT_EMAC_GMAC_MAC_ADDR111_HIGH */
75150  ALT_EMAC_GMAC_MAC_ADDR111_LOW_t gmacgrp_mac_address111_low; /* ALT_EMAC_GMAC_MAC_ADDR111_LOW */
75151  ALT_EMAC_GMAC_MAC_ADDR112_HIGH_t gmacgrp_mac_address112_high; /* ALT_EMAC_GMAC_MAC_ADDR112_HIGH */
75152  ALT_EMAC_GMAC_MAC_ADDR112_LOW_t gmacgrp_mac_address112_low; /* ALT_EMAC_GMAC_MAC_ADDR112_LOW */
75153  ALT_EMAC_GMAC_MAC_ADDR113_HIGH_t gmacgrp_mac_address113_high; /* ALT_EMAC_GMAC_MAC_ADDR113_HIGH */
75154  ALT_EMAC_GMAC_MAC_ADDR113_LOW_t gmacgrp_mac_address113_low; /* ALT_EMAC_GMAC_MAC_ADDR113_LOW */
75155  ALT_EMAC_GMAC_MAC_ADDR114_HIGH_t gmacgrp_mac_address114_high; /* ALT_EMAC_GMAC_MAC_ADDR114_HIGH */
75156  ALT_EMAC_GMAC_MAC_ADDR114_LOW_t gmacgrp_mac_address114_low; /* ALT_EMAC_GMAC_MAC_ADDR114_LOW */
75157  ALT_EMAC_GMAC_MAC_ADDR115_HIGH_t gmacgrp_mac_address115_high; /* ALT_EMAC_GMAC_MAC_ADDR115_HIGH */
75158  ALT_EMAC_GMAC_MAC_ADDR115_LOW_t gmacgrp_mac_address115_low; /* ALT_EMAC_GMAC_MAC_ADDR115_LOW */
75159  ALT_EMAC_GMAC_MAC_ADDR116_HIGH_t gmacgrp_mac_address116_high; /* ALT_EMAC_GMAC_MAC_ADDR116_HIGH */
75160  ALT_EMAC_GMAC_MAC_ADDR116_LOW_t gmacgrp_mac_address116_low; /* ALT_EMAC_GMAC_MAC_ADDR116_LOW */
75161  ALT_EMAC_GMAC_MAC_ADDR117_HIGH_t gmacgrp_mac_address117_high; /* ALT_EMAC_GMAC_MAC_ADDR117_HIGH */
75162  ALT_EMAC_GMAC_MAC_ADDR117_LOW_t gmacgrp_mac_address117_low; /* ALT_EMAC_GMAC_MAC_ADDR117_LOW */
75163  ALT_EMAC_GMAC_MAC_ADDR118_HIGH_t gmacgrp_mac_address118_high; /* ALT_EMAC_GMAC_MAC_ADDR118_HIGH */
75164  ALT_EMAC_GMAC_MAC_ADDR118_LOW_t gmacgrp_mac_address118_low; /* ALT_EMAC_GMAC_MAC_ADDR118_LOW */
75165  ALT_EMAC_GMAC_MAC_ADDR119_HIGH_t gmacgrp_mac_address119_high; /* ALT_EMAC_GMAC_MAC_ADDR119_HIGH */
75166  ALT_EMAC_GMAC_MAC_ADDR119_LOW_t gmacgrp_mac_address119_low; /* ALT_EMAC_GMAC_MAC_ADDR119_LOW */
75167  ALT_EMAC_GMAC_MAC_ADDR120_HIGH_t gmacgrp_mac_address120_high; /* ALT_EMAC_GMAC_MAC_ADDR120_HIGH */
75168  ALT_EMAC_GMAC_MAC_ADDR120_LOW_t gmacgrp_mac_address120_low; /* ALT_EMAC_GMAC_MAC_ADDR120_LOW */
75169  ALT_EMAC_GMAC_MAC_ADDR121_HIGH_t gmacgrp_mac_address121_high; /* ALT_EMAC_GMAC_MAC_ADDR121_HIGH */
75170  ALT_EMAC_GMAC_MAC_ADDR121_LOW_t gmacgrp_mac_address121_low; /* ALT_EMAC_GMAC_MAC_ADDR121_LOW */
75171  ALT_EMAC_GMAC_MAC_ADDR122_HIGH_t gmacgrp_mac_address122_high; /* ALT_EMAC_GMAC_MAC_ADDR122_HIGH */
75172  ALT_EMAC_GMAC_MAC_ADDR122_LOW_t gmacgrp_mac_address122_low; /* ALT_EMAC_GMAC_MAC_ADDR122_LOW */
75173  ALT_EMAC_GMAC_MAC_ADDR123_HIGH_t gmacgrp_mac_address123_high; /* ALT_EMAC_GMAC_MAC_ADDR123_HIGH */
75174  ALT_EMAC_GMAC_MAC_ADDR123_LOW_t gmacgrp_mac_address123_low; /* ALT_EMAC_GMAC_MAC_ADDR123_LOW */
75175  ALT_EMAC_GMAC_MAC_ADDR124_HIGH_t gmacgrp_mac_address124_high; /* ALT_EMAC_GMAC_MAC_ADDR124_HIGH */
75176  ALT_EMAC_GMAC_MAC_ADDR124_LOW_t gmacgrp_mac_address124_low; /* ALT_EMAC_GMAC_MAC_ADDR124_LOW */
75177  ALT_EMAC_GMAC_MAC_ADDR125_HIGH_t gmacgrp_mac_address125_high; /* ALT_EMAC_GMAC_MAC_ADDR125_HIGH */
75178  ALT_EMAC_GMAC_MAC_ADDR125_LOW_t gmacgrp_mac_address125_low; /* ALT_EMAC_GMAC_MAC_ADDR125_LOW */
75179  ALT_EMAC_GMAC_MAC_ADDR126_HIGH_t gmacgrp_mac_address126_high; /* ALT_EMAC_GMAC_MAC_ADDR126_HIGH */
75180  ALT_EMAC_GMAC_MAC_ADDR126_LOW_t gmacgrp_mac_address126_low; /* ALT_EMAC_GMAC_MAC_ADDR126_LOW */
75181  ALT_EMAC_GMAC_MAC_ADDR127_HIGH_t gmacgrp_mac_address127_high; /* ALT_EMAC_GMAC_MAC_ADDR127_HIGH */
75182  ALT_EMAC_GMAC_MAC_ADDR127_LOW_t gmacgrp_mac_address127_low; /* ALT_EMAC_GMAC_MAC_ADDR127_LOW */
75183  volatile uint32_t _pad_0xb80_0xfff[288]; /* *UNDEFINED* */
75184  ALT_EMAC_DMA_BUS_MOD_t dmagrp_bus_mode; /* ALT_EMAC_DMA_BUS_MOD */
75185  ALT_EMAC_DMA_TX_POLL_DEMAND_t dmagrp_transmit_poll_demand; /* ALT_EMAC_DMA_TX_POLL_DEMAND */
75186  ALT_EMAC_DMA_RX_POLL_DEMAND_t dmagrp_receive_poll_demand; /* ALT_EMAC_DMA_RX_POLL_DEMAND */
75187  ALT_EMAC_DMA_RX_DESC_LIST_ADDR_t dmagrp_receive_descriptor_list_address; /* ALT_EMAC_DMA_RX_DESC_LIST_ADDR */
75188  ALT_EMAC_DMA_TX_DESC_LIST_ADDR_t dmagrp_transmit_descriptor_list_address; /* ALT_EMAC_DMA_TX_DESC_LIST_ADDR */
75189  ALT_EMAC_DMA_STAT_t dmagrp_status; /* ALT_EMAC_DMA_STAT */
75190  ALT_EMAC_DMA_OP_MOD_t dmagrp_operation_mode; /* ALT_EMAC_DMA_OP_MOD */
75191  ALT_EMAC_DMA_INT_EN_t dmagrp_interrupt_enable; /* ALT_EMAC_DMA_INT_EN */
75192  ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_t dmagrp_missed_frame_and_buffer_overflow_counter; /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR */
75193  ALT_EMAC_DMA_RX_INT_WDT_t dmagrp_receive_interrupt_watchdog_timer; /* ALT_EMAC_DMA_RX_INT_WDT */
75194  ALT_EMAC_DMA_AXI_BUS_MOD_t dmagrp_axi_bus_mode; /* ALT_EMAC_DMA_AXI_BUS_MOD */
75195  ALT_EMAC_DMA_AHB_OR_AXI_STAT_t dmagrp_ahb_or_axi_status; /* ALT_EMAC_DMA_AHB_OR_AXI_STAT */
75196  volatile uint32_t _pad_0x1030_0x1047[6]; /* *UNDEFINED* */
75197  ALT_EMAC_DMA_CUR_HOST_TX_DESC_t dmagrp_current_host_transmit_descriptor; /* ALT_EMAC_DMA_CUR_HOST_TX_DESC */
75198  ALT_EMAC_DMA_CUR_HOST_RX_DESC_t dmagrp_current_host_receive_descriptor; /* ALT_EMAC_DMA_CUR_HOST_RX_DESC */
75199  ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_t dmagrp_current_host_transmit_buffer_address; /* ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR */
75200  ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_t dmagrp_current_host_receive_buffer_address; /* ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR */
75201  ALT_EMAC_DMA_HW_FEATURE_t dmagrp_hw_feature; /* ALT_EMAC_DMA_HW_FEATURE */
75202 };
75203 
75204 /* The typedef declaration for register group ALT_EMAC. */
75205 typedef volatile struct ALT_EMAC_s ALT_EMAC_t;
75206 /* The struct declaration for the raw register contents of register group ALT_EMAC. */
75207 struct ALT_EMAC_raw_s
75208 {
75209  volatile uint32_t gmacgrp_mac_configuration; /* ALT_EMAC_GMAC_MAC_CFG */
75210  volatile uint32_t gmacgrp_mac_frame_filter; /* ALT_EMAC_GMAC_MAC_FRM_FLT */
75211  uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */
75212  volatile uint32_t gmacgrp_gmii_address; /* ALT_EMAC_GMAC_GMII_ADDR */
75213  volatile uint32_t gmacgrp_gmii_data; /* ALT_EMAC_GMAC_GMII_DATA */
75214  volatile uint32_t gmacgrp_flow_control; /* ALT_EMAC_GMAC_FLOW_CTL */
75215  volatile uint32_t gmacgrp_vlan_tag; /* ALT_EMAC_GMAC_VLAN_TAG */
75216  volatile uint32_t gmacgrp_version; /* ALT_EMAC_GMAC_VER */
75217  volatile uint32_t gmacgrp_debug; /* ALT_EMAC_GMAC_DBG */
75218  uint32_t _pad_0x28_0x2f[2]; /* *UNDEFINED* */
75219  volatile uint32_t gmacgrp_lpi_control_status; /* ALT_EMAC_GMAC_LPI_CTL_STAT */
75220  volatile uint32_t gmacgrp_lpi_timers_control; /* ALT_EMAC_GMAC_LPI_TMRS_CTL */
75221  volatile uint32_t gmacgrp_interrupt_status; /* ALT_EMAC_GMAC_INT_STAT */
75222  volatile uint32_t gmacgrp_interrupt_mask; /* ALT_EMAC_GMAC_INT_MSK */
75223  volatile uint32_t gmacgrp_mac_address0_high; /* ALT_EMAC_GMAC_MAC_ADDR0_HIGH */
75224  volatile uint32_t gmacgrp_mac_address0_low; /* ALT_EMAC_GMAC_MAC_ADDR0_LOW */
75225  volatile uint32_t gmacgrp_mac_address1_high; /* ALT_EMAC_GMAC_MAC_ADDR1_HIGH */
75226  volatile uint32_t gmacgrp_mac_address1_low; /* ALT_EMAC_GMAC_MAC_ADDR1_LOW */
75227  volatile uint32_t gmacgrp_mac_address2_high; /* ALT_EMAC_GMAC_MAC_ADDR2_HIGH */
75228  volatile uint32_t gmacgrp_mac_address2_low; /* ALT_EMAC_GMAC_MAC_ADDR2_LOW */
75229  volatile uint32_t gmacgrp_mac_address3_high; /* ALT_EMAC_GMAC_MAC_ADDR3_HIGH */
75230  volatile uint32_t gmacgrp_mac_address3_low; /* ALT_EMAC_GMAC_MAC_ADDR3_LOW */
75231  volatile uint32_t gmacgrp_mac_address4_high; /* ALT_EMAC_GMAC_MAC_ADDR4_HIGH */
75232  volatile uint32_t gmacgrp_mac_address4_low; /* ALT_EMAC_GMAC_MAC_ADDR4_LOW */
75233  volatile uint32_t gmacgrp_mac_address5_high; /* ALT_EMAC_GMAC_MAC_ADDR5_HIGH */
75234  volatile uint32_t gmacgrp_mac_address5_low; /* ALT_EMAC_GMAC_MAC_ADDR5_LOW */
75235  volatile uint32_t gmacgrp_mac_address6_high; /* ALT_EMAC_GMAC_MAC_ADDR6_HIGH */
75236  volatile uint32_t gmacgrp_mac_address6_low; /* ALT_EMAC_GMAC_MAC_ADDR6_LOW */
75237  volatile uint32_t gmacgrp_mac_address7_high; /* ALT_EMAC_GMAC_MAC_ADDR7_HIGH */
75238  volatile uint32_t gmacgrp_mac_address7_low; /* ALT_EMAC_GMAC_MAC_ADDR7_LOW */
75239  volatile uint32_t gmacgrp_mac_address8_high; /* ALT_EMAC_GMAC_MAC_ADDR8_HIGH */
75240  volatile uint32_t gmacgrp_mac_address8_low; /* ALT_EMAC_GMAC_MAC_ADDR8_LOW */
75241  volatile uint32_t gmacgrp_mac_address9_high; /* ALT_EMAC_GMAC_MAC_ADDR9_HIGH */
75242  volatile uint32_t gmacgrp_mac_address9_low; /* ALT_EMAC_GMAC_MAC_ADDR9_LOW */
75243  volatile uint32_t gmacgrp_mac_address10_high; /* ALT_EMAC_GMAC_MAC_ADDR10_HIGH */
75244  volatile uint32_t gmacgrp_mac_address10_low; /* ALT_EMAC_GMAC_MAC_ADDR10_LOW */
75245  volatile uint32_t gmacgrp_mac_address11_high; /* ALT_EMAC_GMAC_MAC_ADDR11_HIGH */
75246  volatile uint32_t gmacgrp_mac_address11_low; /* ALT_EMAC_GMAC_MAC_ADDR11_LOW */
75247  volatile uint32_t gmacgrp_mac_address12_high; /* ALT_EMAC_GMAC_MAC_ADDR12_HIGH */
75248  volatile uint32_t gmacgrp_mac_address12_low; /* ALT_EMAC_GMAC_MAC_ADDR12_LOW */
75249  volatile uint32_t gmacgrp_mac_address13_high; /* ALT_EMAC_GMAC_MAC_ADDR13_HIGH */
75250  volatile uint32_t gmacgrp_mac_address13_low; /* ALT_EMAC_GMAC_MAC_ADDR13_LOW */
75251  volatile uint32_t gmacgrp_mac_address14_high; /* ALT_EMAC_GMAC_MAC_ADDR14_HIGH */
75252  volatile uint32_t gmacgrp_mac_address14_low; /* ALT_EMAC_GMAC_MAC_ADDR14_LOW */
75253  volatile uint32_t gmacgrp_mac_address15_high; /* ALT_EMAC_GMAC_MAC_ADDR15_HIGH */
75254  volatile uint32_t gmacgrp_mac_address15_low; /* ALT_EMAC_GMAC_MAC_ADDR15_LOW */
75255  uint32_t _pad_0xc0_0xd7[6]; /* *UNDEFINED* */
75256  volatile uint32_t gmacgrp_sgmii_rgmii_smii_control_status; /* ALT_EMAC_GMAC_MII_CTL_STAT */
75257  volatile uint32_t gmacgrp_wdog_timeout; /* ALT_EMAC_GMAC_WDOG_TMO */
75258  volatile uint32_t gmacgrp_genpio; /* ALT_EMAC_GMAC_GENPIO */
75259  uint32_t _pad_0xe4_0xff[7]; /* *UNDEFINED* */
75260  volatile uint32_t gmacgrp_mmc_control; /* ALT_EMAC_GMAC_MMC_CTL */
75261  volatile uint32_t gmacgrp_mmc_receive_interrupt; /* ALT_EMAC_GMAC_MMC_RX_INT */
75262  volatile uint32_t gmacgrp_mmc_transmit_interrupt; /* ALT_EMAC_GMAC_MMC_TX_INT */
75263  volatile uint32_t gmacgrp_mmc_receive_interrupt_mask; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK */
75264  volatile uint32_t gmacgrp_mmc_transmit_interrupt_mask; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK */
75265  volatile uint32_t gmacgrp_txoctetcount_gb; /* ALT_EMAC_GMAC_TXOCTETCOUNT_GB */
75266  volatile uint32_t gmacgrp_txframecount_gb; /* ALT_EMAC_GMAC_TXFRMCOUNT_GB */
75267  volatile uint32_t gmacgrp_txbroadcastframes_g; /* ALT_EMAC_GMAC_TXBCASTFRMS_G */
75268  volatile uint32_t gmacgrp_txmulticastframes_g; /* ALT_EMAC_GMAC_TXMCASTFRMS_G */
75269  volatile uint32_t gmacgrp_tx64octets_gb; /* ALT_EMAC_GMAC_TX64OCTETS_GB */
75270  volatile uint32_t gmacgrp_tx65to127octets_gb; /* ALT_EMAC_GMAC_TX65TO127OCTETS_GB */
75271  volatile uint32_t gmacgrp_tx128to255octets_gb; /* ALT_EMAC_GMAC_TX128TO255OCTETS_GB */
75272  volatile uint32_t gmacgrp_tx256to511octets_gb; /* ALT_EMAC_GMAC_TX256TO511OCTETS_GB */
75273  volatile uint32_t gmacgrp_tx512to1023octets_gb; /* ALT_EMAC_GMAC_TX512TO1023OCTETS_GB */
75274  volatile uint32_t gmacgrp_tx1024tomaxoctets_gb; /* ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB */
75275  volatile uint32_t gmacgrp_txunicastframes_gb; /* ALT_EMAC_GMAC_TXUNICASTFRMS_GB */
75276  volatile uint32_t gmacgrp_txmulticastframes_gb; /* ALT_EMAC_GMAC_TXMCASTFRMS_GB */
75277  volatile uint32_t gmacgrp_txbroadcastframes_gb; /* ALT_EMAC_GMAC_TXBCASTFRMS_GB */
75278  volatile uint32_t gmacgrp_txunderflowerror; /* ALT_EMAC_GMAC_TXUNDERFLOWERROR */
75279  volatile uint32_t gmacgrp_txsinglecol_g; /* ALT_EMAC_GMAC_TXSINGLECOL_G */
75280  volatile uint32_t gmacgrp_txmulticol_g; /* ALT_EMAC_GMAC_TXMULTICOL_G */
75281  volatile uint32_t gmacgrp_txdeferred; /* ALT_EMAC_GMAC_TXDEFERRED */
75282  volatile uint32_t gmacgrp_txlatecol; /* ALT_EMAC_GMAC_TXLATECOL */
75283  volatile uint32_t gmacgrp_txexesscol; /* ALT_EMAC_GMAC_TXEXESSCOL */
75284  volatile uint32_t gmacgrp_txcarriererr; /* ALT_EMAC_GMAC_TXCARRIERERR */
75285  volatile uint32_t gmacgrp_txoctetcnt; /* ALT_EMAC_GMAC_TXOCTETCNT */
75286  volatile uint32_t gmacgrp_txframecount_g; /* ALT_EMAC_GMAC_TXFRMCOUNT_G */
75287  volatile uint32_t gmacgrp_txexcessdef; /* ALT_EMAC_GMAC_TXEXCESSDEF */
75288  volatile uint32_t gmacgrp_txpauseframes; /* ALT_EMAC_GMAC_TXPAUSEFRMS */
75289  volatile uint32_t gmacgrp_txvlanframes_g; /* ALT_EMAC_GMAC_TXVLANFRMS_G */
75290  volatile uint32_t gmacgrp_txoversize_g; /* ALT_EMAC_GMAC_TXOVERSIZE_G */
75291  uint32_t _pad_0x17c_0x17f; /* *UNDEFINED* */
75292  volatile uint32_t gmacgrp_rxframecount_gb; /* ALT_EMAC_GMAC_RXFRMCOUNT_GB */
75293  volatile uint32_t gmacgrp_rxoctetcount_gb; /* ALT_EMAC_GMAC_RXOCTETCOUNT_GB */
75294  volatile uint32_t gmacgrp_rxoctetcount_g; /* ALT_EMAC_GMAC_RXOCTETCOUNT_G */
75295  volatile uint32_t gmacgrp_rxbroadcastframes_g; /* ALT_EMAC_GMAC_RXBCASTFRMS_G */
75296  volatile uint32_t gmacgrp_rxmulticastframes_g; /* ALT_EMAC_GMAC_RXMCASTFRMS_G */
75297  volatile uint32_t gmacgrp_rxcrcerror; /* ALT_EMAC_GMAC_RXCRCERROR */
75298  volatile uint32_t gmacgrp_rxalignmenterror; /* ALT_EMAC_GMAC_RXALIGNMENTERROR */
75299  volatile uint32_t gmacgrp_rxrunterror; /* ALT_EMAC_GMAC_RXRUNTERROR */
75300  volatile uint32_t gmacgrp_rxjabbererror; /* ALT_EMAC_GMAC_RXJABBERERROR */
75301  volatile uint32_t gmacgrp_rxundersize_g; /* ALT_EMAC_GMAC_RXUNDERSIZE_G */
75302  volatile uint32_t gmacgrp_rxoversize_g; /* ALT_EMAC_GMAC_RXOVERSIZE_G */
75303  volatile uint32_t gmacgrp_rx64octets_gb; /* ALT_EMAC_GMAC_RX64OCTETS_GB */
75304  volatile uint32_t gmacgrp_rx65to127octets_gb; /* ALT_EMAC_GMAC_RX65TO127OCTETS_GB */
75305  volatile uint32_t gmacgrp_rx128to255octets_gb; /* ALT_EMAC_GMAC_RX128TO255OCTETS_GB */
75306  volatile uint32_t gmacgrp_rx256to511octets_gb; /* ALT_EMAC_GMAC_RX256TO511OCTETS_GB */
75307  volatile uint32_t gmacgrp_rx512to1023octets_gb; /* ALT_EMAC_GMAC_RX512TO1023OCTETS_GB */
75308  volatile uint32_t gmacgrp_rx1024tomaxoctets_gb; /* ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB */
75309  volatile uint32_t gmacgrp_rxunicastframes_g; /* ALT_EMAC_GMAC_RXUNICASTFRMS_G */
75310  volatile uint32_t gmacgrp_rxlengtherror; /* ALT_EMAC_GMAC_RXLENERROR */
75311  volatile uint32_t gmacgrp_rxoutofrangetype; /* ALT_EMAC_GMAC_RXOUTOFRANGETYPE */
75312  volatile uint32_t gmacgrp_rxpauseframes; /* ALT_EMAC_GMAC_RXPAUSEFRMS */
75313  volatile uint32_t gmacgrp_rxfifooverflow; /* ALT_EMAC_GMAC_RXFIFOOVF */
75314  volatile uint32_t gmacgrp_rxvlanframes_gb; /* ALT_EMAC_GMAC_RXVLANFRMS_GB */
75315  volatile uint32_t gmacgrp_rxwatchdogerror; /* ALT_EMAC_GMAC_RXWDERROR */
75316  volatile uint32_t gmacgrp_rxrcverror; /* ALT_EMAC_GMAC_RXRCVERROR */
75317  volatile uint32_t gmacgrp_rxctrlframes_g; /* ALT_EMAC_GMAC_RXCTLFRMS_G */
75318  uint32_t _pad_0x1e8_0x1ff[6]; /* *UNDEFINED* */
75319  volatile uint32_t gmacgrp_mmc_ipc_receive_interrupt_mask; /* ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK */
75320  uint32_t _pad_0x204_0x207; /* *UNDEFINED* */
75321  volatile uint32_t gmacgrp_mmc_ipc_receive_interrupt; /* ALT_EMAC_GMAC_MMC_IPC_RX_INT */
75322  uint32_t _pad_0x20c_0x20f; /* *UNDEFINED* */
75323  volatile uint32_t gmacgrp_rxipv4_gd_frms; /* ALT_EMAC_GMAC_RXIPV4_GD_FRMS */
75324  volatile uint32_t gmacgrp_rxipv4_hdrerr_frms; /* ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS */
75325  volatile uint32_t gmacgrp_rxipv4_nopay_frms; /* ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS */
75326  volatile uint32_t gmacgrp_rxipv4_frag_frms; /* ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS */
75327  volatile uint32_t gmacgrp_rxipv4_udsbl_frms; /* ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS */
75328  volatile uint32_t gmacgrp_rxipv6_gd_frms; /* ALT_EMAC_GMAC_RXIPV6_GD_FRMS */
75329  volatile uint32_t gmacgrp_rxipv6_hdrerr_frms; /* ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS */
75330  volatile uint32_t gmacgrp_rxipv6_nopay_frms; /* ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS */
75331  volatile uint32_t gmacgrp_rxudp_gd_frms; /* ALT_EMAC_GMAC_RXUDP_GD_FRMS */
75332  volatile uint32_t gmacgrp_rxudp_err_frms; /* ALT_EMAC_GMAC_RXUDP_ERR_FRMS */
75333  volatile uint32_t gmacgrp_rxtcp_gd_frms; /* ALT_EMAC_GMAC_RXTCP_GD_FRMS */
75334  volatile uint32_t gmacgrp_rxtcp_err_frms; /* ALT_EMAC_GMAC_RXTCP_ERR_FRMS */
75335  volatile uint32_t gmacgrp_rxicmp_gd_frms; /* ALT_EMAC_GMAC_RXICMP_GD_FRMS */
75336  volatile uint32_t gmacgrp_rxicmp_err_frms; /* ALT_EMAC_GMAC_RXICMP_ERR_FRMS */
75337  uint32_t _pad_0x248_0x24f[2]; /* *UNDEFINED* */
75338  volatile uint32_t gmacgrp_rxipv4_gd_octets; /* ALT_EMAC_GMAC_RXIPV4_GD_OCTETS */
75339  volatile uint32_t gmacgrp_rxipv4_hdrerr_octets; /* ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS */
75340  volatile uint32_t gmacgrp_rxipv4_nopay_octets; /* ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS */
75341  volatile uint32_t gmacgrp_rxipv4_frag_octets; /* ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS */
75342  volatile uint32_t gmacgrp_rxipv4_udsbl_octets; /* ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS */
75343  volatile uint32_t gmacgrp_rxipv6_gd_octets; /* ALT_EMAC_GMAC_RXIPV6_GD_OCTETS */
75344  volatile uint32_t gmacgrp_rxipv6_hdrerr_octets; /* ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS */
75345  volatile uint32_t gmacgrp_rxipv6_nopay_octets; /* ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS */
75346  volatile uint32_t gmacgrp_rxudp_gd_octets; /* ALT_EMAC_GMAC_RXUDP_GD_OCTETS */
75347  volatile uint32_t gmacgrp_rxudp_err_octets; /* ALT_EMAC_GMAC_RXUDP_ERR_OCTETS */
75348  volatile uint32_t gmacgrp_rxtcp_gd_octets; /* ALT_EMAC_GMAC_RXTCP_GD_OCTETS */
75349  volatile uint32_t gmacgrp_rxtcperroctets; /* ALT_EMAC_GMAC_RXTCPERROCTETS */
75350  volatile uint32_t gmacgrp_rxicmp_gd_octets; /* ALT_EMAC_GMAC_RXICMP_GD_OCTETS */
75351  volatile uint32_t gmacgrp_rxicmp_err_octets; /* ALT_EMAC_GMAC_RXICMP_ERR_OCTETS */
75352  uint32_t _pad_0x288_0x3ff[94]; /* *UNDEFINED* */
75353  volatile uint32_t gmacgrp_l3_l4_control0; /* ALT_EMAC_GMAC_L3_L4_CTL0 */
75354  volatile uint32_t gmacgrp_layer4_address0; /* ALT_EMAC_GMAC_LYR4_ADDR0 */
75355  uint32_t _pad_0x408_0x40f[2]; /* *UNDEFINED* */
75356  volatile uint32_t gmacgrp_layer3_addr0_reg0; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG0 */
75357  volatile uint32_t gmacgrp_layer3_addr1_reg0; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG0 */
75358  volatile uint32_t gmacgrp_layer3_addr2_reg0; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG0 */
75359  volatile uint32_t gmacgrp_layer3_addr3_reg0; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG0 */
75360  uint32_t _pad_0x420_0x42f[4]; /* *UNDEFINED* */
75361  volatile uint32_t gmacgrp_l3_l4_control1; /* ALT_EMAC_GMAC_L3_L4_CTL1 */
75362  volatile uint32_t gmacgrp_layer4_address1; /* ALT_EMAC_GMAC_LYR4_ADDR1 */
75363  uint32_t _pad_0x438_0x43f[2]; /* *UNDEFINED* */
75364  volatile uint32_t gmacgrp_layer3_addr0_reg1; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG1 */
75365  volatile uint32_t gmacgrp_layer3_addr1_reg1; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG1 */
75366  volatile uint32_t gmacgrp_layer3_addr2_reg1; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG1 */
75367  volatile uint32_t gmacgrp_layer3_addr3_reg1; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG1 */
75368  uint32_t _pad_0x450_0x45f[4]; /* *UNDEFINED* */
75369  volatile uint32_t gmacgrp_l3_l4_control2; /* ALT_EMAC_GMAC_L3_L4_CTL2 */
75370  volatile uint32_t gmacgrp_layer4_address2; /* ALT_EMAC_GMAC_LYR4_ADDR2 */
75371  uint32_t _pad_0x468_0x46f[2]; /* *UNDEFINED* */
75372  volatile uint32_t gmacgrp_layer3_addr0_reg2; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG2 */
75373  volatile uint32_t gmacgrp_layer3_addr1_reg2; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG2 */
75374  volatile uint32_t gmacgrp_layer3_addr2_reg2; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG2 */
75375  volatile uint32_t gmacgrp_layer3_addr3_reg2; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG2 */
75376  uint32_t _pad_0x480_0x48f[4]; /* *UNDEFINED* */
75377  volatile uint32_t gmacgrp_l3_l4_control3; /* ALT_EMAC_GMAC_L3_L4_CTL3 */
75378  volatile uint32_t gmacgrp_layer4_address3; /* ALT_EMAC_GMAC_LYR4_ADDR3 */
75379  uint32_t _pad_0x498_0x49f[2]; /* *UNDEFINED* */
75380  volatile uint32_t gmacgrp_layer3_addr0_reg3; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG3 */
75381  volatile uint32_t gmacgrp_layer3_addr1_reg3; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG3 */
75382  volatile uint32_t gmacgrp_layer3_addr2_reg3; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG3 */
75383  volatile uint32_t gmacgrp_layer3_addr3_reg3; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG3 */
75384  uint32_t _pad_0x4b0_0x4ff[20]; /* *UNDEFINED* */
75385  volatile uint32_t gmacgrp_hash_table_reg0; /* ALT_EMAC_GMAC_HASH_TABLE_REG0 */
75386  volatile uint32_t gmacgrp_hash_table_reg1; /* ALT_EMAC_GMAC_HASH_TABLE_REG1 */
75387  volatile uint32_t gmacgrp_hash_table_reg2; /* ALT_EMAC_GMAC_HASH_TABLE_REG2 */
75388  volatile uint32_t gmacgrp_hash_table_reg3; /* ALT_EMAC_GMAC_HASH_TABLE_REG3 */
75389  volatile uint32_t gmacgrp_hash_table_reg4; /* ALT_EMAC_GMAC_HASH_TABLE_REG4 */
75390  volatile uint32_t gmacgrp_hash_table_reg5; /* ALT_EMAC_GMAC_HASH_TABLE_REG5 */
75391  volatile uint32_t gmacgrp_hash_table_reg6; /* ALT_EMAC_GMAC_HASH_TABLE_REG6 */
75392  volatile uint32_t gmacgrp_hash_table_reg7; /* ALT_EMAC_GMAC_HASH_TABLE_REG7 */
75393  uint32_t _pad_0x520_0x583[25]; /* *UNDEFINED* */
75394  volatile uint32_t gmacgrp_vlan_incl_reg; /* ALT_EMAC_GMAC_VLAN_INCL_REG */
75395  volatile uint32_t gmacgrp_vlan_hash_table_reg; /* ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG */
75396  uint32_t _pad_0x58c_0x6ff[93]; /* *UNDEFINED* */
75397  volatile uint32_t gmacgrp_timestamp_control; /* ALT_EMAC_GMAC_TS_CTL */
75398  volatile uint32_t gmacgrp_sub_second_increment; /* ALT_EMAC_GMAC_SUB_SEC_INCREMENT */
75399  volatile uint32_t gmacgrp_system_time_seconds; /* ALT_EMAC_GMAC_SYS_TIME_SECS */
75400  volatile uint32_t gmacgrp_system_time_nanoseconds; /* ALT_EMAC_GMAC_SYS_TIME_NANOSECS */
75401  volatile uint32_t gmacgrp_system_time_seconds_update; /* ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE */
75402  volatile uint32_t gmacgrp_system_time_nanoseconds_update; /* ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE */
75403  volatile uint32_t gmacgrp_timestamp_addend; /* ALT_EMAC_GMAC_TS_ADDEND */
75404  volatile uint32_t gmacgrp_target_time_seconds; /* ALT_EMAC_GMAC_TGT_TIME_SECS */
75405  volatile uint32_t gmacgrp_target_time_nanoseconds; /* ALT_EMAC_GMAC_TGT_TIME_NANOSECS */
75406  volatile uint32_t gmacgrp_system_time_higher_word_seconds; /* ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS */
75407  volatile uint32_t gmacgrp_timestamp_status; /* ALT_EMAC_GMAC_TS_STAT */
75408  volatile uint32_t gmacgrp_pps_control; /* ALT_EMAC_GMAC_PPS_CTL */
75409  volatile uint32_t gmacgrp_auxiliary_timestamp_nanoseconds; /* ALT_EMAC_GMAC_AUX_TS_NANOSECS */
75410  volatile uint32_t gmacgrp_auxiliary_timestamp_seconds; /* ALT_EMAC_GMAC_AUX_TS_SECS */
75411  uint32_t _pad_0x738_0x75f[10]; /* *UNDEFINED* */
75412  volatile uint32_t gmacgrp_pps0_interval; /* ALT_EMAC_GMAC_PPS0_INTERVAL */
75413  volatile uint32_t gmacgrp_pps0_width; /* ALT_EMAC_GMAC_PPS0_WIDTH */
75414  uint32_t _pad_0x768_0x7ff[38]; /* *UNDEFINED* */
75415  volatile uint32_t gmacgrp_mac_address16_high; /* ALT_EMAC_GMAC_MAC_ADDR16_HIGH */
75416  volatile uint32_t gmacgrp_mac_address16_low; /* ALT_EMAC_GMAC_MAC_ADDR16_LOW */
75417  volatile uint32_t gmacgrp_mac_address17_high; /* ALT_EMAC_GMAC_MAC_ADDR17_HIGH */
75418  volatile uint32_t gmacgrp_mac_address17_low; /* ALT_EMAC_GMAC_MAC_ADDR17_LOW */
75419  volatile uint32_t gmacgrp_mac_address18_high; /* ALT_EMAC_GMAC_MAC_ADDR18_HIGH */
75420  volatile uint32_t gmacgrp_mac_address18_low; /* ALT_EMAC_GMAC_MAC_ADDR18_LOW */
75421  volatile uint32_t gmacgrp_mac_address19_high; /* ALT_EMAC_GMAC_MAC_ADDR19_HIGH */
75422  volatile uint32_t gmacgrp_mac_address19_low; /* ALT_EMAC_GMAC_MAC_ADDR19_LOW */
75423  volatile uint32_t gmacgrp_mac_address20_high; /* ALT_EMAC_GMAC_MAC_ADDR20_HIGH */
75424  volatile uint32_t gmacgrp_mac_address20_low; /* ALT_EMAC_GMAC_MAC_ADDR20_LOW */
75425  volatile uint32_t gmacgrp_mac_address21_high; /* ALT_EMAC_GMAC_MAC_ADDR21_HIGH */
75426  volatile uint32_t gmacgrp_mac_address21_low; /* ALT_EMAC_GMAC_MAC_ADDR21_LOW */
75427  volatile uint32_t gmacgrp_mac_address22_high; /* ALT_EMAC_GMAC_MAC_ADDR22_HIGH */
75428  volatile uint32_t gmacgrp_mac_address22_low; /* ALT_EMAC_GMAC_MAC_ADDR22_LOW */
75429  volatile uint32_t gmacgrp_mac_address23_high; /* ALT_EMAC_GMAC_MAC_ADDR23_HIGH */
75430  volatile uint32_t gmacgrp_mac_address23_low; /* ALT_EMAC_GMAC_MAC_ADDR23_LOW */
75431  volatile uint32_t gmacgrp_mac_address24_high; /* ALT_EMAC_GMAC_MAC_ADDR24_HIGH */
75432  volatile uint32_t gmacgrp_mac_address24_low; /* ALT_EMAC_GMAC_MAC_ADDR24_LOW */
75433  volatile uint32_t gmacgrp_mac_address25_high; /* ALT_EMAC_GMAC_MAC_ADDR25_HIGH */
75434  volatile uint32_t gmacgrp_mac_address25_low; /* ALT_EMAC_GMAC_MAC_ADDR25_LOW */
75435  volatile uint32_t gmacgrp_mac_address26_high; /* ALT_EMAC_GMAC_MAC_ADDR26_HIGH */
75436  volatile uint32_t gmacgrp_mac_address26_low; /* ALT_EMAC_GMAC_MAC_ADDR26_LOW */
75437  volatile uint32_t gmacgrp_mac_address27_high; /* ALT_EMAC_GMAC_MAC_ADDR27_HIGH */
75438  volatile uint32_t gmacgrp_mac_address27_low; /* ALT_EMAC_GMAC_MAC_ADDR27_LOW */
75439  volatile uint32_t gmacgrp_mac_address28_high; /* ALT_EMAC_GMAC_MAC_ADDR28_HIGH */
75440  volatile uint32_t gmacgrp_mac_address28_low; /* ALT_EMAC_GMAC_MAC_ADDR28_LOW */
75441  volatile uint32_t gmacgrp_mac_address29_high; /* ALT_EMAC_GMAC_MAC_ADDR29_HIGH */
75442  volatile uint32_t gmacgrp_mac_address29_low; /* ALT_EMAC_GMAC_MAC_ADDR29_LOW */
75443  volatile uint32_t gmacgrp_mac_address30_high; /* ALT_EMAC_GMAC_MAC_ADDR30_HIGH */
75444  volatile uint32_t gmacgrp_mac_address30_low; /* ALT_EMAC_GMAC_MAC_ADDR30_LOW */
75445  volatile uint32_t gmacgrp_mac_address31_high; /* ALT_EMAC_GMAC_MAC_ADDR31_HIGH */
75446  volatile uint32_t gmacgrp_mac_address31_low; /* ALT_EMAC_GMAC_MAC_ADDR31_LOW */
75447  volatile uint32_t gmacgrp_mac_address32_high; /* ALT_EMAC_GMAC_MAC_ADDR32_HIGH */
75448  volatile uint32_t gmacgrp_mac_address32_low; /* ALT_EMAC_GMAC_MAC_ADDR32_LOW */
75449  volatile uint32_t gmacgrp_mac_address33_high; /* ALT_EMAC_GMAC_MAC_ADDR33_HIGH */
75450  volatile uint32_t gmacgrp_mac_address33_low; /* ALT_EMAC_GMAC_MAC_ADDR33_LOW */
75451  volatile uint32_t gmacgrp_mac_address34_high; /* ALT_EMAC_GMAC_MAC_ADDR34_HIGH */
75452  volatile uint32_t gmacgrp_mac_address34_low; /* ALT_EMAC_GMAC_MAC_ADDR34_LOW */
75453  volatile uint32_t gmacgrp_mac_address35_high; /* ALT_EMAC_GMAC_MAC_ADDR35_HIGH */
75454  volatile uint32_t gmacgrp_mac_address35_low; /* ALT_EMAC_GMAC_MAC_ADDR35_LOW */
75455  volatile uint32_t gmacgrp_mac_address36_high; /* ALT_EMAC_GMAC_MAC_ADDR36_HIGH */
75456  volatile uint32_t gmacgrp_mac_address36_low; /* ALT_EMAC_GMAC_MAC_ADDR36_LOW */
75457  volatile uint32_t gmacgrp_mac_address37_high; /* ALT_EMAC_GMAC_MAC_ADDR37_HIGH */
75458  volatile uint32_t gmacgrp_mac_address37_low; /* ALT_EMAC_GMAC_MAC_ADDR37_LOW */
75459  volatile uint32_t gmacgrp_mac_address38_high; /* ALT_EMAC_GMAC_MAC_ADDR38_HIGH */
75460  volatile uint32_t gmacgrp_mac_address38_low; /* ALT_EMAC_GMAC_MAC_ADDR38_LOW */
75461  volatile uint32_t gmacgrp_mac_address39_high; /* ALT_EMAC_GMAC_MAC_ADDR39_HIGH */
75462  volatile uint32_t gmacgrp_mac_address39_low; /* ALT_EMAC_GMAC_MAC_ADDR39_LOW */
75463  volatile uint32_t gmacgrp_mac_address40_high; /* ALT_EMAC_GMAC_MAC_ADDR40_HIGH */
75464  volatile uint32_t gmacgrp_mac_address40_low; /* ALT_EMAC_GMAC_MAC_ADDR40_LOW */
75465  volatile uint32_t gmacgrp_mac_address41_high; /* ALT_EMAC_GMAC_MAC_ADDR41_HIGH */
75466  volatile uint32_t gmacgrp_mac_address41_low; /* ALT_EMAC_GMAC_MAC_ADDR41_LOW */
75467  volatile uint32_t gmacgrp_mac_address42_high; /* ALT_EMAC_GMAC_MAC_ADDR42_HIGH */
75468  volatile uint32_t gmacgrp_mac_address42_low; /* ALT_EMAC_GMAC_MAC_ADDR42_LOW */
75469  volatile uint32_t gmacgrp_mac_address43_high; /* ALT_EMAC_GMAC_MAC_ADDR43_HIGH */
75470  volatile uint32_t gmacgrp_mac_address43_low; /* ALT_EMAC_GMAC_MAC_ADDR43_LOW */
75471  volatile uint32_t gmacgrp_mac_address44_high; /* ALT_EMAC_GMAC_MAC_ADDR44_HIGH */
75472  volatile uint32_t gmacgrp_mac_address44_low; /* ALT_EMAC_GMAC_MAC_ADDR44_LOW */
75473  volatile uint32_t gmacgrp_mac_address45_high; /* ALT_EMAC_GMAC_MAC_ADDR45_HIGH */
75474  volatile uint32_t gmacgrp_mac_address45_low; /* ALT_EMAC_GMAC_MAC_ADDR45_LOW */
75475  volatile uint32_t gmacgrp_mac_address46_high; /* ALT_EMAC_GMAC_MAC_ADDR46_HIGH */
75476  volatile uint32_t gmacgrp_mac_address46_low; /* ALT_EMAC_GMAC_MAC_ADDR46_LOW */
75477  volatile uint32_t gmacgrp_mac_address47_high; /* ALT_EMAC_GMAC_MAC_ADDR47_HIGH */
75478  volatile uint32_t gmacgrp_mac_address47_low; /* ALT_EMAC_GMAC_MAC_ADDR47_LOW */
75479  volatile uint32_t gmacgrp_mac_address48_high; /* ALT_EMAC_GMAC_MAC_ADDR48_HIGH */
75480  volatile uint32_t gmacgrp_mac_address48_low; /* ALT_EMAC_GMAC_MAC_ADDR48_LOW */
75481  volatile uint32_t gmacgrp_mac_address49_high; /* ALT_EMAC_GMAC_MAC_ADDR49_HIGH */
75482  volatile uint32_t gmacgrp_mac_address49_low; /* ALT_EMAC_GMAC_MAC_ADDR49_LOW */
75483  volatile uint32_t gmacgrp_mac_address50_high; /* ALT_EMAC_GMAC_MAC_ADDR50_HIGH */
75484  volatile uint32_t gmacgrp_mac_address50_low; /* ALT_EMAC_GMAC_MAC_ADDR50_LOW */
75485  volatile uint32_t gmacgrp_mac_address51_high; /* ALT_EMAC_GMAC_MAC_ADDR51_HIGH */
75486  volatile uint32_t gmacgrp_mac_address51_low; /* ALT_EMAC_GMAC_MAC_ADDR51_LOW */
75487  volatile uint32_t gmacgrp_mac_address52_high; /* ALT_EMAC_GMAC_MAC_ADDR52_HIGH */
75488  volatile uint32_t gmacgrp_mac_address52_low; /* ALT_EMAC_GMAC_MAC_ADDR52_LOW */
75489  volatile uint32_t gmacgrp_mac_address53_high; /* ALT_EMAC_GMAC_MAC_ADDR53_HIGH */
75490  volatile uint32_t gmacgrp_mac_address53_low; /* ALT_EMAC_GMAC_MAC_ADDR53_LOW */
75491  volatile uint32_t gmacgrp_mac_address54_high; /* ALT_EMAC_GMAC_MAC_ADDR54_HIGH */
75492  volatile uint32_t gmacgrp_mac_address54_low; /* ALT_EMAC_GMAC_MAC_ADDR54_LOW */
75493  volatile uint32_t gmacgrp_mac_address55_high; /* ALT_EMAC_GMAC_MAC_ADDR55_HIGH */
75494  volatile uint32_t gmacgrp_mac_address55_low; /* ALT_EMAC_GMAC_MAC_ADDR55_LOW */
75495  volatile uint32_t gmacgrp_mac_address56_high; /* ALT_EMAC_GMAC_MAC_ADDR56_HIGH */
75496  volatile uint32_t gmacgrp_mac_address56_low; /* ALT_EMAC_GMAC_MAC_ADDR56_LOW */
75497  volatile uint32_t gmacgrp_mac_address57_high; /* ALT_EMAC_GMAC_MAC_ADDR57_HIGH */
75498  volatile uint32_t gmacgrp_mac_address57_low; /* ALT_EMAC_GMAC_MAC_ADDR57_LOW */
75499  volatile uint32_t gmacgrp_mac_address58_high; /* ALT_EMAC_GMAC_MAC_ADDR58_HIGH */
75500  volatile uint32_t gmacgrp_mac_address58_low; /* ALT_EMAC_GMAC_MAC_ADDR58_LOW */
75501  volatile uint32_t gmacgrp_mac_address59_high; /* ALT_EMAC_GMAC_MAC_ADDR59_HIGH */
75502  volatile uint32_t gmacgrp_mac_address59_low; /* ALT_EMAC_GMAC_MAC_ADDR59_LOW */
75503  volatile uint32_t gmacgrp_mac_address60_high; /* ALT_EMAC_GMAC_MAC_ADDR60_HIGH */
75504  volatile uint32_t gmacgrp_mac_address60_low; /* ALT_EMAC_GMAC_MAC_ADDR60_LOW */
75505  volatile uint32_t gmacgrp_mac_address61_high; /* ALT_EMAC_GMAC_MAC_ADDR61_HIGH */
75506  volatile uint32_t gmacgrp_mac_address61_low; /* ALT_EMAC_GMAC_MAC_ADDR61_LOW */
75507  volatile uint32_t gmacgrp_mac_address62_high; /* ALT_EMAC_GMAC_MAC_ADDR62_HIGH */
75508  volatile uint32_t gmacgrp_mac_address62_low; /* ALT_EMAC_GMAC_MAC_ADDR62_LOW */
75509  volatile uint32_t gmacgrp_mac_address63_high; /* ALT_EMAC_GMAC_MAC_ADDR63_HIGH */
75510  volatile uint32_t gmacgrp_mac_address63_low; /* ALT_EMAC_GMAC_MAC_ADDR63_LOW */
75511  volatile uint32_t gmacgrp_mac_address64_high; /* ALT_EMAC_GMAC_MAC_ADDR64_HIGH */
75512  volatile uint32_t gmacgrp_mac_address64_low; /* ALT_EMAC_GMAC_MAC_ADDR64_LOW */
75513  volatile uint32_t gmacgrp_mac_address65_high; /* ALT_EMAC_GMAC_MAC_ADDR65_HIGH */
75514  volatile uint32_t gmacgrp_mac_address65_low; /* ALT_EMAC_GMAC_MAC_ADDR65_LOW */
75515  volatile uint32_t gmacgrp_mac_address66_high; /* ALT_EMAC_GMAC_MAC_ADDR66_HIGH */
75516  volatile uint32_t gmacgrp_mac_address66_low; /* ALT_EMAC_GMAC_MAC_ADDR66_LOW */
75517  volatile uint32_t gmacgrp_mac_address67_high; /* ALT_EMAC_GMAC_MAC_ADDR67_HIGH */
75518  volatile uint32_t gmacgrp_mac_address67_low; /* ALT_EMAC_GMAC_MAC_ADDR67_LOW */
75519  volatile uint32_t gmacgrp_mac_address68_high; /* ALT_EMAC_GMAC_MAC_ADDR68_HIGH */
75520  volatile uint32_t gmacgrp_mac_address68_low; /* ALT_EMAC_GMAC_MAC_ADDR68_LOW */
75521  volatile uint32_t gmacgrp_mac_address69_high; /* ALT_EMAC_GMAC_MAC_ADDR69_HIGH */
75522  volatile uint32_t gmacgrp_mac_address69_low; /* ALT_EMAC_GMAC_MAC_ADDR69_LOW */
75523  volatile uint32_t gmacgrp_mac_address70_high; /* ALT_EMAC_GMAC_MAC_ADDR70_HIGH */
75524  volatile uint32_t gmacgrp_mac_address70_low; /* ALT_EMAC_GMAC_MAC_ADDR70_LOW */
75525  volatile uint32_t gmacgrp_mac_address71_high; /* ALT_EMAC_GMAC_MAC_ADDR71_HIGH */
75526  volatile uint32_t gmacgrp_mac_address71_low; /* ALT_EMAC_GMAC_MAC_ADDR71_LOW */
75527  volatile uint32_t gmacgrp_mac_address72_high; /* ALT_EMAC_GMAC_MAC_ADDR72_HIGH */
75528  volatile uint32_t gmacgrp_mac_address72_low; /* ALT_EMAC_GMAC_MAC_ADDR72_LOW */
75529  volatile uint32_t gmacgrp_mac_address73_high; /* ALT_EMAC_GMAC_MAC_ADDR73_HIGH */
75530  volatile uint32_t gmacgrp_mac_address73_low; /* ALT_EMAC_GMAC_MAC_ADDR73_LOW */
75531  volatile uint32_t gmacgrp_mac_address74_high; /* ALT_EMAC_GMAC_MAC_ADDR74_HIGH */
75532  volatile uint32_t gmacgrp_mac_address74_low; /* ALT_EMAC_GMAC_MAC_ADDR74_LOW */
75533  volatile uint32_t gmacgrp_mac_address75_high; /* ALT_EMAC_GMAC_MAC_ADDR75_HIGH */
75534  volatile uint32_t gmacgrp_mac_address75_low; /* ALT_EMAC_GMAC_MAC_ADDR75_LOW */
75535  volatile uint32_t gmacgrp_mac_address76_high; /* ALT_EMAC_GMAC_MAC_ADDR76_HIGH */
75536  volatile uint32_t gmacgrp_mac_address76_low; /* ALT_EMAC_GMAC_MAC_ADDR76_LOW */
75537  volatile uint32_t gmacgrp_mac_address77_high; /* ALT_EMAC_GMAC_MAC_ADDR77_HIGH */
75538  volatile uint32_t gmacgrp_mac_address77_low; /* ALT_EMAC_GMAC_MAC_ADDR77_LOW */
75539  volatile uint32_t gmacgrp_mac_address78_high; /* ALT_EMAC_GMAC_MAC_ADDR78_HIGH */
75540  volatile uint32_t gmacgrp_mac_address78_low; /* ALT_EMAC_GMAC_MAC_ADDR78_LOW */
75541  volatile uint32_t gmacgrp_mac_address79_high; /* ALT_EMAC_GMAC_MAC_ADDR79_HIGH */
75542  volatile uint32_t gmacgrp_mac_address79_low; /* ALT_EMAC_GMAC_MAC_ADDR79_LOW */
75543  volatile uint32_t gmacgrp_mac_address80_high; /* ALT_EMAC_GMAC_MAC_ADDR80_HIGH */
75544  volatile uint32_t gmacgrp_mac_address80_low; /* ALT_EMAC_GMAC_MAC_ADDR80_LOW */
75545  volatile uint32_t gmacgrp_mac_address81_high; /* ALT_EMAC_GMAC_MAC_ADDR81_HIGH */
75546  volatile uint32_t gmacgrp_mac_address81_low; /* ALT_EMAC_GMAC_MAC_ADDR81_LOW */
75547  volatile uint32_t gmacgrp_mac_address82_high; /* ALT_EMAC_GMAC_MAC_ADDR82_HIGH */
75548  volatile uint32_t gmacgrp_mac_address82_low; /* ALT_EMAC_GMAC_MAC_ADDR82_LOW */
75549  volatile uint32_t gmacgrp_mac_address83_high; /* ALT_EMAC_GMAC_MAC_ADDR83_HIGH */
75550  volatile uint32_t gmacgrp_mac_address83_low; /* ALT_EMAC_GMAC_MAC_ADDR83_LOW */
75551  volatile uint32_t gmacgrp_mac_address84_high; /* ALT_EMAC_GMAC_MAC_ADDR84_HIGH */
75552  volatile uint32_t gmacgrp_mac_address84_low; /* ALT_EMAC_GMAC_MAC_ADDR84_LOW */
75553  volatile uint32_t gmacgrp_mac_address85_high; /* ALT_EMAC_GMAC_MAC_ADDR85_HIGH */
75554  volatile uint32_t gmacgrp_mac_address85_low; /* ALT_EMAC_GMAC_MAC_ADDR85_LOW */
75555  volatile uint32_t gmacgrp_mac_address86_high; /* ALT_EMAC_GMAC_MAC_ADDR86_HIGH */
75556  volatile uint32_t gmacgrp_mac_address86_low; /* ALT_EMAC_GMAC_MAC_ADDR86_LOW */
75557  volatile uint32_t gmacgrp_mac_address87_high; /* ALT_EMAC_GMAC_MAC_ADDR87_HIGH */
75558  volatile uint32_t gmacgrp_mac_address87_low; /* ALT_EMAC_GMAC_MAC_ADDR87_LOW */
75559  volatile uint32_t gmacgrp_mac_address88_high; /* ALT_EMAC_GMAC_MAC_ADDR88_HIGH */
75560  volatile uint32_t gmacgrp_mac_address88_low; /* ALT_EMAC_GMAC_MAC_ADDR88_LOW */
75561  volatile uint32_t gmacgrp_mac_address89_high; /* ALT_EMAC_GMAC_MAC_ADDR89_HIGH */
75562  volatile uint32_t gmacgrp_mac_address89_low; /* ALT_EMAC_GMAC_MAC_ADDR89_LOW */
75563  volatile uint32_t gmacgrp_mac_address90_high; /* ALT_EMAC_GMAC_MAC_ADDR90_HIGH */
75564  volatile uint32_t gmacgrp_mac_address90_low; /* ALT_EMAC_GMAC_MAC_ADDR90_LOW */
75565  volatile uint32_t gmacgrp_mac_address91_high; /* ALT_EMAC_GMAC_MAC_ADDR91_HIGH */
75566  volatile uint32_t gmacgrp_mac_address91_low; /* ALT_EMAC_GMAC_MAC_ADDR91_LOW */
75567  volatile uint32_t gmacgrp_mac_address92_high; /* ALT_EMAC_GMAC_MAC_ADDR92_HIGH */
75568  volatile uint32_t gmacgrp_mac_address92_low; /* ALT_EMAC_GMAC_MAC_ADDR92_LOW */
75569  volatile uint32_t gmacgrp_mac_address93_high; /* ALT_EMAC_GMAC_MAC_ADDR93_HIGH */
75570  volatile uint32_t gmacgrp_mac_address93_low; /* ALT_EMAC_GMAC_MAC_ADDR93_LOW */
75571  volatile uint32_t gmacgrp_mac_address94_high; /* ALT_EMAC_GMAC_MAC_ADDR94_HIGH */
75572  volatile uint32_t gmacgrp_mac_address94_low; /* ALT_EMAC_GMAC_MAC_ADDR94_LOW */
75573  volatile uint32_t gmacgrp_mac_address95_high; /* ALT_EMAC_GMAC_MAC_ADDR95_HIGH */
75574  volatile uint32_t gmacgrp_mac_address95_low; /* ALT_EMAC_GMAC_MAC_ADDR95_LOW */
75575  volatile uint32_t gmacgrp_mac_address96_high; /* ALT_EMAC_GMAC_MAC_ADDR96_HIGH */
75576  volatile uint32_t gmacgrp_mac_address96_low; /* ALT_EMAC_GMAC_MAC_ADDR96_LOW */
75577  volatile uint32_t gmacgrp_mac_address97_high; /* ALT_EMAC_GMAC_MAC_ADDR97_HIGH */
75578  volatile uint32_t gmacgrp_mac_address97_low; /* ALT_EMAC_GMAC_MAC_ADDR97_LOW */
75579  volatile uint32_t gmacgrp_mac_address98_high; /* ALT_EMAC_GMAC_MAC_ADDR98_HIGH */
75580  volatile uint32_t gmacgrp_mac_address98_low; /* ALT_EMAC_GMAC_MAC_ADDR98_LOW */
75581  volatile uint32_t gmacgrp_mac_address99_high; /* ALT_EMAC_GMAC_MAC_ADDR99_HIGH */
75582  volatile uint32_t gmacgrp_mac_address99_low; /* ALT_EMAC_GMAC_MAC_ADDR99_LOW */
75583  volatile uint32_t gmacgrp_mac_address100_high; /* ALT_EMAC_GMAC_MAC_ADDR100_HIGH */
75584  volatile uint32_t gmacgrp_mac_address100_low; /* ALT_EMAC_GMAC_MAC_ADDR100_LOW */
75585  volatile uint32_t gmacgrp_mac_address101_high; /* ALT_EMAC_GMAC_MAC_ADDR101_HIGH */
75586  volatile uint32_t gmacgrp_mac_address101_low; /* ALT_EMAC_GMAC_MAC_ADDR101_LOW */
75587  volatile uint32_t gmacgrp_mac_address102_high; /* ALT_EMAC_GMAC_MAC_ADDR102_HIGH */
75588  volatile uint32_t gmacgrp_mac_address102_low; /* ALT_EMAC_GMAC_MAC_ADDR102_LOW */
75589  volatile uint32_t gmacgrp_mac_address103_high; /* ALT_EMAC_GMAC_MAC_ADDR103_HIGH */
75590  volatile uint32_t gmacgrp_mac_address103_low; /* ALT_EMAC_GMAC_MAC_ADDR103_LOW */
75591  volatile uint32_t gmacgrp_mac_address104_high; /* ALT_EMAC_GMAC_MAC_ADDR104_HIGH */
75592  volatile uint32_t gmacgrp_mac_address104_low; /* ALT_EMAC_GMAC_MAC_ADDR104_LOW */
75593  volatile uint32_t gmacgrp_mac_address105_high; /* ALT_EMAC_GMAC_MAC_ADDR105_HIGH */
75594  volatile uint32_t gmacgrp_mac_address105_low; /* ALT_EMAC_GMAC_MAC_ADDR105_LOW */
75595  volatile uint32_t gmacgrp_mac_address106_high; /* ALT_EMAC_GMAC_MAC_ADDR106_HIGH */
75596  volatile uint32_t gmacgrp_mac_address106_low; /* ALT_EMAC_GMAC_MAC_ADDR106_LOW */
75597  volatile uint32_t gmacgrp_mac_address107_high; /* ALT_EMAC_GMAC_MAC_ADDR107_HIGH */
75598  volatile uint32_t gmacgrp_mac_address107_low; /* ALT_EMAC_GMAC_MAC_ADDR107_LOW */
75599  volatile uint32_t gmacgrp_mac_address108_high; /* ALT_EMAC_GMAC_MAC_ADDR108_HIGH */
75600  volatile uint32_t gmacgrp_mac_address108_low; /* ALT_EMAC_GMAC_MAC_ADDR108_LOW */
75601  volatile uint32_t gmacgrp_mac_address109_high; /* ALT_EMAC_GMAC_MAC_ADDR109_HIGH */
75602  volatile uint32_t gmacgrp_mac_address109_low; /* ALT_EMAC_GMAC_MAC_ADDR109_LOW */
75603  volatile uint32_t gmacgrp_mac_address110_high; /* ALT_EMAC_GMAC_MAC_ADDR110_HIGH */
75604  volatile uint32_t gmacgrp_mac_address110_low; /* ALT_EMAC_GMAC_MAC_ADDR110_LOW */
75605  volatile uint32_t gmacgrp_mac_address111_high; /* ALT_EMAC_GMAC_MAC_ADDR111_HIGH */
75606  volatile uint32_t gmacgrp_mac_address111_low; /* ALT_EMAC_GMAC_MAC_ADDR111_LOW */
75607  volatile uint32_t gmacgrp_mac_address112_high; /* ALT_EMAC_GMAC_MAC_ADDR112_HIGH */
75608  volatile uint32_t gmacgrp_mac_address112_low; /* ALT_EMAC_GMAC_MAC_ADDR112_LOW */
75609  volatile uint32_t gmacgrp_mac_address113_high; /* ALT_EMAC_GMAC_MAC_ADDR113_HIGH */
75610  volatile uint32_t gmacgrp_mac_address113_low; /* ALT_EMAC_GMAC_MAC_ADDR113_LOW */
75611  volatile uint32_t gmacgrp_mac_address114_high; /* ALT_EMAC_GMAC_MAC_ADDR114_HIGH */
75612  volatile uint32_t gmacgrp_mac_address114_low; /* ALT_EMAC_GMAC_MAC_ADDR114_LOW */
75613  volatile uint32_t gmacgrp_mac_address115_high; /* ALT_EMAC_GMAC_MAC_ADDR115_HIGH */
75614  volatile uint32_t gmacgrp_mac_address115_low; /* ALT_EMAC_GMAC_MAC_ADDR115_LOW */
75615  volatile uint32_t gmacgrp_mac_address116_high; /* ALT_EMAC_GMAC_MAC_ADDR116_HIGH */
75616  volatile uint32_t gmacgrp_mac_address116_low; /* ALT_EMAC_GMAC_MAC_ADDR116_LOW */
75617  volatile uint32_t gmacgrp_mac_address117_high; /* ALT_EMAC_GMAC_MAC_ADDR117_HIGH */
75618  volatile uint32_t gmacgrp_mac_address117_low; /* ALT_EMAC_GMAC_MAC_ADDR117_LOW */
75619  volatile uint32_t gmacgrp_mac_address118_high; /* ALT_EMAC_GMAC_MAC_ADDR118_HIGH */
75620  volatile uint32_t gmacgrp_mac_address118_low; /* ALT_EMAC_GMAC_MAC_ADDR118_LOW */
75621  volatile uint32_t gmacgrp_mac_address119_high; /* ALT_EMAC_GMAC_MAC_ADDR119_HIGH */
75622  volatile uint32_t gmacgrp_mac_address119_low; /* ALT_EMAC_GMAC_MAC_ADDR119_LOW */
75623  volatile uint32_t gmacgrp_mac_address120_high; /* ALT_EMAC_GMAC_MAC_ADDR120_HIGH */
75624  volatile uint32_t gmacgrp_mac_address120_low; /* ALT_EMAC_GMAC_MAC_ADDR120_LOW */
75625  volatile uint32_t gmacgrp_mac_address121_high; /* ALT_EMAC_GMAC_MAC_ADDR121_HIGH */
75626  volatile uint32_t gmacgrp_mac_address121_low; /* ALT_EMAC_GMAC_MAC_ADDR121_LOW */
75627  volatile uint32_t gmacgrp_mac_address122_high; /* ALT_EMAC_GMAC_MAC_ADDR122_HIGH */
75628  volatile uint32_t gmacgrp_mac_address122_low; /* ALT_EMAC_GMAC_MAC_ADDR122_LOW */
75629  volatile uint32_t gmacgrp_mac_address123_high; /* ALT_EMAC_GMAC_MAC_ADDR123_HIGH */
75630  volatile uint32_t gmacgrp_mac_address123_low; /* ALT_EMAC_GMAC_MAC_ADDR123_LOW */
75631  volatile uint32_t gmacgrp_mac_address124_high; /* ALT_EMAC_GMAC_MAC_ADDR124_HIGH */
75632  volatile uint32_t gmacgrp_mac_address124_low; /* ALT_EMAC_GMAC_MAC_ADDR124_LOW */
75633  volatile uint32_t gmacgrp_mac_address125_high; /* ALT_EMAC_GMAC_MAC_ADDR125_HIGH */
75634  volatile uint32_t gmacgrp_mac_address125_low; /* ALT_EMAC_GMAC_MAC_ADDR125_LOW */
75635  volatile uint32_t gmacgrp_mac_address126_high; /* ALT_EMAC_GMAC_MAC_ADDR126_HIGH */
75636  volatile uint32_t gmacgrp_mac_address126_low; /* ALT_EMAC_GMAC_MAC_ADDR126_LOW */
75637  volatile uint32_t gmacgrp_mac_address127_high; /* ALT_EMAC_GMAC_MAC_ADDR127_HIGH */
75638  volatile uint32_t gmacgrp_mac_address127_low; /* ALT_EMAC_GMAC_MAC_ADDR127_LOW */
75639  uint32_t _pad_0xb80_0xfff[288]; /* *UNDEFINED* */
75640  volatile uint32_t dmagrp_bus_mode; /* ALT_EMAC_DMA_BUS_MOD */
75641  volatile uint32_t dmagrp_transmit_poll_demand; /* ALT_EMAC_DMA_TX_POLL_DEMAND */
75642  volatile uint32_t dmagrp_receive_poll_demand; /* ALT_EMAC_DMA_RX_POLL_DEMAND */
75643  volatile uint32_t dmagrp_receive_descriptor_list_address; /* ALT_EMAC_DMA_RX_DESC_LIST_ADDR */
75644  volatile uint32_t dmagrp_transmit_descriptor_list_address; /* ALT_EMAC_DMA_TX_DESC_LIST_ADDR */
75645  volatile uint32_t dmagrp_status; /* ALT_EMAC_DMA_STAT */
75646  volatile uint32_t dmagrp_operation_mode; /* ALT_EMAC_DMA_OP_MOD */
75647  volatile uint32_t dmagrp_interrupt_enable; /* ALT_EMAC_DMA_INT_EN */
75648  volatile uint32_t dmagrp_missed_frame_and_buffer_overflow_counter; /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR */
75649  volatile uint32_t dmagrp_receive_interrupt_watchdog_timer; /* ALT_EMAC_DMA_RX_INT_WDT */
75650  volatile uint32_t dmagrp_axi_bus_mode; /* ALT_EMAC_DMA_AXI_BUS_MOD */
75651  volatile uint32_t dmagrp_ahb_or_axi_status; /* ALT_EMAC_DMA_AHB_OR_AXI_STAT */
75652  uint32_t _pad_0x1030_0x1047[6]; /* *UNDEFINED* */
75653  volatile uint32_t dmagrp_current_host_transmit_descriptor; /* ALT_EMAC_DMA_CUR_HOST_TX_DESC */
75654  volatile uint32_t dmagrp_current_host_receive_descriptor; /* ALT_EMAC_DMA_CUR_HOST_RX_DESC */
75655  volatile uint32_t dmagrp_current_host_transmit_buffer_address; /* ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR */
75656  volatile uint32_t dmagrp_current_host_receive_buffer_address; /* ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR */
75657  volatile uint32_t dmagrp_hw_feature; /* ALT_EMAC_DMA_HW_FEATURE */
75658 };
75659 
75660 /* The typedef declaration for the raw register contents of register group ALT_EMAC. */
75661 typedef volatile struct ALT_EMAC_raw_s ALT_EMAC_raw_t;
75662 #endif /* __ASSEMBLY__ */
75663 
75664 
75665 #ifdef __cplusplus
75666 }
75667 #endif /* __cplusplus */
75668 #endif /* __ALT_SOCAL_EMAC_H__ */
75669