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alt_noc_fw_l4_per_scr.h
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32 
33 /* Altera - ALT_NOC_FW_L4_PER_SCR */
34 
35 #ifndef __ALT_SOCAL_NOC_FW_L4_PER_SCR_H__
36 #define __ALT_SOCAL_NOC_FW_L4_PER_SCR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : NOC_FW_L4_PER_SCR
50  * L4_PER Security Control Registers (SCR)
51  *
52  */
53 /*
54  * Register : nand_register
55  *
56  * Per-Master Security bit for nand register
57  *
58  * Register Layout
59  *
60  * Bits | Access | Reset | Description
61  * :--------|:-------|:--------|:---------------------------------------------
62  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU
63  * [15:1] | ??? | Unknown | *UNDEFINED*
64  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC
65  * [23:17] | ??? | Unknown | *UNDEFINED*
66  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP
67  * [31:25] | ??? | Unknown | *UNDEFINED*
68  *
69  */
70 /*
71  * Field : mpu
72  *
73  * Security bit configuration for transactions from mpu to nand_register. When
74  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
75  * Non-Secure transactions are allowed.
76  *
77  * Field Access Macros:
78  *
79  */
80 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU register field. */
81 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU_LSB 0
82 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU register field. */
83 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU_MSB 0
84 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU register field. */
85 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU_WIDTH 1
86 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU register field value. */
87 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU_SET_MSK 0x00000001
88 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU register field value. */
89 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU_CLR_MSK 0xfffffffe
90 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU register field. */
91 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU_RESET 0x0
92 /* Extracts the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU field value from a register. */
93 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU_GET(value) (((value) & 0x00000001) >> 0)
94 /* Produces a ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU register field value suitable for setting the register. */
95 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU_SET(value) (((value) << 0) & 0x00000001)
96 
97 /*
98  * Field : fpga2soc
99  *
100  * Security bit configuration for transactions from fpga2soc to nand_register. When
101  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
102  * Non-Secure transactions are allowed.
103  *
104  * Field Access Macros:
105  *
106  */
107 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC register field. */
108 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC_LSB 16
109 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC register field. */
110 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC_MSB 16
111 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC register field. */
112 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC_WIDTH 1
113 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC register field value. */
114 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC_SET_MSK 0x00010000
115 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC register field value. */
116 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC_CLR_MSK 0xfffeffff
117 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC register field. */
118 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC_RESET 0x0
119 /* Extracts the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC field value from a register. */
120 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
121 /* Produces a ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC register field value suitable for setting the register. */
122 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
123 
124 /*
125  * Field : axi_ap
126  *
127  * Security bit configuration for transactions from axi_ap to nand_register. When
128  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
129  * Non-Secure transactions are allowed.
130  *
131  * Field Access Macros:
132  *
133  */
134 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP register field. */
135 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP_LSB 24
136 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP register field. */
137 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP_MSB 24
138 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP register field. */
139 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP_WIDTH 1
140 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP register field value. */
141 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP_SET_MSK 0x01000000
142 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP register field value. */
143 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP_CLR_MSK 0xfeffffff
144 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP register field. */
145 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP_RESET 0x0
146 /* Extracts the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP field value from a register. */
147 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
148 /* Produces a ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP register field value suitable for setting the register. */
149 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
150 
151 #ifndef __ASSEMBLY__
152 /*
153  * WARNING: The C register and register group struct declarations are provided for
154  * convenience and illustrative purposes. They should, however, be used with
155  * caution as the C language standard provides no guarantees about the alignment or
156  * atomicity of device memory accesses. The recommended practice for coding device
157  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
158  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
159  * alt_write_dword() functions for 64 bit registers.
160  *
161  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER.
162  */
163 struct ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_s
164 {
165  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU */
166  uint32_t : 15; /* *UNDEFINED* */
167  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC */
168  uint32_t : 7; /* *UNDEFINED* */
169  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP */
170  uint32_t : 7; /* *UNDEFINED* */
171 };
172 
173 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER. */
174 typedef struct ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_s ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_t;
175 #endif /* __ASSEMBLY__ */
176 
177 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER register. */
178 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_RESET 0x00000000
179 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER register from the beginning of the component. */
180 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_OFST 0x0
181 
182 /*
183  * Register : nand_data
184  *
185  * Per-Master Security bit for nand_data
186  *
187  * Register Layout
188  *
189  * Bits | Access | Reset | Description
190  * :--------|:-------|:--------|:-----------------------------------------
191  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU
192  * [15:1] | ??? | Unknown | *UNDEFINED*
193  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC
194  * [23:17] | ??? | Unknown | *UNDEFINED*
195  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP
196  * [31:25] | ??? | Unknown | *UNDEFINED*
197  *
198  */
199 /*
200  * Field : mpu
201  *
202  * Security bit configuration for transactions from mpu to nand_data. When cleared
203  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
204  * Secure transactions are allowed.
205  *
206  * Field Access Macros:
207  *
208  */
209 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU register field. */
210 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_LSB 0
211 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU register field. */
212 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_MSB 0
213 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU register field. */
214 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_WIDTH 1
215 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU register field value. */
216 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_SET_MSK 0x00000001
217 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU register field value. */
218 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_CLR_MSK 0xfffffffe
219 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU register field. */
220 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_RESET 0x0
221 /* Extracts the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU field value from a register. */
222 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_GET(value) (((value) & 0x00000001) >> 0)
223 /* Produces a ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU register field value suitable for setting the register. */
224 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_SET(value) (((value) << 0) & 0x00000001)
225 
226 /*
227  * Field : fpga2soc
228  *
229  * Security bit configuration for transactions from fpga2soc to nand_data. When
230  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
231  * Non-Secure transactions are allowed.
232  *
233  * Field Access Macros:
234  *
235  */
236 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC register field. */
237 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC_LSB 16
238 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC register field. */
239 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC_MSB 16
240 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC register field. */
241 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC_WIDTH 1
242 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC register field value. */
243 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC_SET_MSK 0x00010000
244 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC register field value. */
245 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC_CLR_MSK 0xfffeffff
246 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC register field. */
247 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC_RESET 0x0
248 /* Extracts the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC field value from a register. */
249 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
250 /* Produces a ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC register field value suitable for setting the register. */
251 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
252 
253 /*
254  * Field : axi_ap
255  *
256  * Security bit configuration for transactions from axi_ap to nand_data. When
257  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
258  * Non-Secure transactions are allowed.
259  *
260  * Field Access Macros:
261  *
262  */
263 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP register field. */
264 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP_LSB 24
265 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP register field. */
266 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP_MSB 24
267 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP register field. */
268 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP_WIDTH 1
269 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP register field value. */
270 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP_SET_MSK 0x01000000
271 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP register field value. */
272 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP_CLR_MSK 0xfeffffff
273 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP register field. */
274 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP_RESET 0x0
275 /* Extracts the ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP field value from a register. */
276 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
277 /* Produces a ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP register field value suitable for setting the register. */
278 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
279 
280 #ifndef __ASSEMBLY__
281 /*
282  * WARNING: The C register and register group struct declarations are provided for
283  * convenience and illustrative purposes. They should, however, be used with
284  * caution as the C language standard provides no guarantees about the alignment or
285  * atomicity of device memory accesses. The recommended practice for coding device
286  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
287  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
288  * alt_write_dword() functions for 64 bit registers.
289  *
290  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_NAND_DATA.
291  */
292 struct ALT_NOC_FW_L4_PER_SCR_NAND_DATA_s
293 {
294  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU */
295  uint32_t : 15; /* *UNDEFINED* */
296  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC */
297  uint32_t : 7; /* *UNDEFINED* */
298  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP */
299  uint32_t : 7; /* *UNDEFINED* */
300 };
301 
302 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_NAND_DATA. */
303 typedef struct ALT_NOC_FW_L4_PER_SCR_NAND_DATA_s ALT_NOC_FW_L4_PER_SCR_NAND_DATA_t;
304 #endif /* __ASSEMBLY__ */
305 
306 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA register. */
307 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_RESET 0x00000000
308 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_NAND_DATA register from the beginning of the component. */
309 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_OFST 0x4
310 
311 /*
312  * Register : usb0_register
313  *
314  * Per-Master Security bit for usb0_register
315  *
316  * Register Layout
317  *
318  * Bits | Access | Reset | Description
319  * :--------|:-------|:--------|:---------------------------------------------
320  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU
321  * [15:1] | ??? | Unknown | *UNDEFINED*
322  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC
323  * [23:17] | ??? | Unknown | *UNDEFINED*
324  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP
325  * [31:25] | ??? | Unknown | *UNDEFINED*
326  *
327  */
328 /*
329  * Field : mpu
330  *
331  * Security bit configuration for transactions from mpu to usb0_register. When
332  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
333  * Non-Secure transactions are allowed.
334  *
335  * Field Access Macros:
336  *
337  */
338 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU register field. */
339 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU_LSB 0
340 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU register field. */
341 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU_MSB 0
342 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU register field. */
343 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU_WIDTH 1
344 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU register field value. */
345 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU_SET_MSK 0x00000001
346 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU register field value. */
347 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU_CLR_MSK 0xfffffffe
348 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU register field. */
349 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU_RESET 0x0
350 /* Extracts the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU field value from a register. */
351 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU_GET(value) (((value) & 0x00000001) >> 0)
352 /* Produces a ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU register field value suitable for setting the register. */
353 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU_SET(value) (((value) << 0) & 0x00000001)
354 
355 /*
356  * Field : fpga2soc
357  *
358  * Security bit configuration for transactions from fpga2soc to usb0_register. When
359  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
360  * Non-Secure transactions are allowed.
361  *
362  * Field Access Macros:
363  *
364  */
365 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC register field. */
366 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC_LSB 16
367 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC register field. */
368 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC_MSB 16
369 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC register field. */
370 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC_WIDTH 1
371 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC register field value. */
372 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC_SET_MSK 0x00010000
373 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC register field value. */
374 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC_CLR_MSK 0xfffeffff
375 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC register field. */
376 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC_RESET 0x0
377 /* Extracts the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC field value from a register. */
378 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
379 /* Produces a ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC register field value suitable for setting the register. */
380 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
381 
382 /*
383  * Field : axi_ap
384  *
385  * Security bit configuration for transactions from axi_ap to usb0_register. When
386  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
387  * Non-Secure transactions are allowed.
388  *
389  * Field Access Macros:
390  *
391  */
392 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP register field. */
393 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP_LSB 24
394 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP register field. */
395 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP_MSB 24
396 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP register field. */
397 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP_WIDTH 1
398 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP register field value. */
399 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP_SET_MSK 0x01000000
400 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP register field value. */
401 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP_CLR_MSK 0xfeffffff
402 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP register field. */
403 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP_RESET 0x0
404 /* Extracts the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP field value from a register. */
405 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
406 /* Produces a ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP register field value suitable for setting the register. */
407 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
408 
409 #ifndef __ASSEMBLY__
410 /*
411  * WARNING: The C register and register group struct declarations are provided for
412  * convenience and illustrative purposes. They should, however, be used with
413  * caution as the C language standard provides no guarantees about the alignment or
414  * atomicity of device memory accesses. The recommended practice for coding device
415  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
416  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
417  * alt_write_dword() functions for 64 bit registers.
418  *
419  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER.
420  */
421 struct ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_s
422 {
423  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU */
424  uint32_t : 15; /* *UNDEFINED* */
425  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC */
426  uint32_t : 7; /* *UNDEFINED* */
427  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP */
428  uint32_t : 7; /* *UNDEFINED* */
429 };
430 
431 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER. */
432 typedef struct ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_s ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_t;
433 #endif /* __ASSEMBLY__ */
434 
435 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER register. */
436 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_RESET 0x00000000
437 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER register from the beginning of the component. */
438 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_OFST 0xc
439 
440 /*
441  * Register : usb1_register
442  *
443  * Per-Master Security bit for usb1_register
444  *
445  * Register Layout
446  *
447  * Bits | Access | Reset | Description
448  * :--------|:-------|:--------|:---------------------------------------------
449  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU
450  * [15:1] | ??? | Unknown | *UNDEFINED*
451  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC
452  * [23:17] | ??? | Unknown | *UNDEFINED*
453  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP
454  * [31:25] | ??? | Unknown | *UNDEFINED*
455  *
456  */
457 /*
458  * Field : mpu
459  *
460  * Security bit configuration for transactions from mpu to usb1_register. When
461  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
462  * Non-Secure transactions are allowed.
463  *
464  * Field Access Macros:
465  *
466  */
467 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU register field. */
468 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU_LSB 0
469 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU register field. */
470 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU_MSB 0
471 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU register field. */
472 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU_WIDTH 1
473 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU register field value. */
474 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU_SET_MSK 0x00000001
475 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU register field value. */
476 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU_CLR_MSK 0xfffffffe
477 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU register field. */
478 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU_RESET 0x0
479 /* Extracts the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU field value from a register. */
480 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU_GET(value) (((value) & 0x00000001) >> 0)
481 /* Produces a ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU register field value suitable for setting the register. */
482 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU_SET(value) (((value) << 0) & 0x00000001)
483 
484 /*
485  * Field : fpga2soc
486  *
487  * Security bit configuration for transactions from fpga2soc to usb1_register. When
488  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
489  * Non-Secure transactions are allowed.
490  *
491  * Field Access Macros:
492  *
493  */
494 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC register field. */
495 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC_LSB 16
496 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC register field. */
497 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC_MSB 16
498 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC register field. */
499 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC_WIDTH 1
500 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC register field value. */
501 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC_SET_MSK 0x00010000
502 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC register field value. */
503 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC_CLR_MSK 0xfffeffff
504 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC register field. */
505 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC_RESET 0x0
506 /* Extracts the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC field value from a register. */
507 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
508 /* Produces a ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC register field value suitable for setting the register. */
509 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
510 
511 /*
512  * Field : axi_ap
513  *
514  * Security bit configuration for transactions from axi_ap to usb1_register. When
515  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
516  * Non-Secure transactions are allowed.
517  *
518  * Field Access Macros:
519  *
520  */
521 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP register field. */
522 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP_LSB 24
523 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP register field. */
524 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP_MSB 24
525 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP register field. */
526 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP_WIDTH 1
527 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP register field value. */
528 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP_SET_MSK 0x01000000
529 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP register field value. */
530 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP_CLR_MSK 0xfeffffff
531 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP register field. */
532 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP_RESET 0x0
533 /* Extracts the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP field value from a register. */
534 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
535 /* Produces a ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP register field value suitable for setting the register. */
536 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
537 
538 #ifndef __ASSEMBLY__
539 /*
540  * WARNING: The C register and register group struct declarations are provided for
541  * convenience and illustrative purposes. They should, however, be used with
542  * caution as the C language standard provides no guarantees about the alignment or
543  * atomicity of device memory accesses. The recommended practice for coding device
544  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
545  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
546  * alt_write_dword() functions for 64 bit registers.
547  *
548  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER.
549  */
550 struct ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_s
551 {
552  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU */
553  uint32_t : 15; /* *UNDEFINED* */
554  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC */
555  uint32_t : 7; /* *UNDEFINED* */
556  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP */
557  uint32_t : 7; /* *UNDEFINED* */
558 };
559 
560 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER. */
561 typedef struct ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_s ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_t;
562 #endif /* __ASSEMBLY__ */
563 
564 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER register. */
565 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_RESET 0x00000000
566 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER register from the beginning of the component. */
567 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_OFST 0x10
568 
569 /*
570  * Register : spi_master0
571  *
572  * Per-Master Security bit for spi_master0
573  *
574  * Register Layout
575  *
576  * Bits | Access | Reset | Description
577  * :--------|:-------|:--------|:-------------------------------------------
578  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU
579  * [7:1] | ??? | Unknown | *UNDEFINED*
580  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA
581  * [15:9] | ??? | Unknown | *UNDEFINED*
582  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC
583  * [23:17] | ??? | Unknown | *UNDEFINED*
584  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP
585  * [31:25] | ??? | Unknown | *UNDEFINED*
586  *
587  */
588 /*
589  * Field : mpu
590  *
591  * Security bit configuration for transactions from mpu to spi_master0. When
592  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
593  * Non-Secure transactions are allowed.
594  *
595  * Field Access Macros:
596  *
597  */
598 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU register field. */
599 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU_LSB 0
600 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU register field. */
601 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU_MSB 0
602 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU register field. */
603 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU_WIDTH 1
604 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU register field value. */
605 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU_SET_MSK 0x00000001
606 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU register field value. */
607 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU_CLR_MSK 0xfffffffe
608 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU register field. */
609 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU_RESET 0x0
610 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU field value from a register. */
611 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU_GET(value) (((value) & 0x00000001) >> 0)
612 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU register field value suitable for setting the register. */
613 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU_SET(value) (((value) << 0) & 0x00000001)
614 
615 /*
616  * Field : dma
617  *
618  * Security bit configuration for transactions from dma to spi_master0. When
619  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
620  * Non-Secure transactions are allowed.
621  *
622  * Field Access Macros:
623  *
624  */
625 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA register field. */
626 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA_LSB 8
627 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA register field. */
628 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA_MSB 8
629 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA register field. */
630 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA_WIDTH 1
631 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA register field value. */
632 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA_SET_MSK 0x00000100
633 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA register field value. */
634 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA_CLR_MSK 0xfffffeff
635 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA register field. */
636 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA_RESET 0x0
637 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA field value from a register. */
638 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA_GET(value) (((value) & 0x00000100) >> 8)
639 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA register field value suitable for setting the register. */
640 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA_SET(value) (((value) << 8) & 0x00000100)
641 
642 /*
643  * Field : fpga2soc
644  *
645  * Security bit configuration for transactions from fpga2soc to spi_master0. When
646  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
647  * Non-Secure transactions are allowed.
648  *
649  * Field Access Macros:
650  *
651  */
652 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC register field. */
653 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC_LSB 16
654 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC register field. */
655 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC_MSB 16
656 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC register field. */
657 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC_WIDTH 1
658 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC register field value. */
659 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC_SET_MSK 0x00010000
660 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC register field value. */
661 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC_CLR_MSK 0xfffeffff
662 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC register field. */
663 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC_RESET 0x0
664 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC field value from a register. */
665 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
666 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC register field value suitable for setting the register. */
667 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
668 
669 /*
670  * Field : axi_ap
671  *
672  * Security bit configuration for transactions from axi_ap to spi_master0. When
673  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
674  * Non-Secure transactions are allowed.
675  *
676  * Field Access Macros:
677  *
678  */
679 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP register field. */
680 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP_LSB 24
681 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP register field. */
682 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP_MSB 24
683 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP register field. */
684 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP_WIDTH 1
685 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP register field value. */
686 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP_SET_MSK 0x01000000
687 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP register field value. */
688 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP_CLR_MSK 0xfeffffff
689 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP register field. */
690 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP_RESET 0x0
691 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP field value from a register. */
692 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
693 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP register field value suitable for setting the register. */
694 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
695 
696 #ifndef __ASSEMBLY__
697 /*
698  * WARNING: The C register and register group struct declarations are provided for
699  * convenience and illustrative purposes. They should, however, be used with
700  * caution as the C language standard provides no guarantees about the alignment or
701  * atomicity of device memory accesses. The recommended practice for coding device
702  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
703  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
704  * alt_write_dword() functions for 64 bit registers.
705  *
706  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0.
707  */
708 struct ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_s
709 {
710  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU */
711  uint32_t : 7; /* *UNDEFINED* */
712  volatile uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA */
713  uint32_t : 7; /* *UNDEFINED* */
714  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC */
715  uint32_t : 7; /* *UNDEFINED* */
716  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP */
717  uint32_t : 7; /* *UNDEFINED* */
718 };
719 
720 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0. */
721 typedef struct ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_s ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_t;
722 #endif /* __ASSEMBLY__ */
723 
724 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0 register. */
725 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_RESET 0x00000000
726 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0 register from the beginning of the component. */
727 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_OFST 0x1c
728 
729 /*
730  * Register : spi_master1
731  *
732  * Per-Master Security bit for spi_master1
733  *
734  * Register Layout
735  *
736  * Bits | Access | Reset | Description
737  * :--------|:-------|:--------|:-------------------------------------------
738  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU
739  * [7:1] | ??? | Unknown | *UNDEFINED*
740  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA
741  * [15:9] | ??? | Unknown | *UNDEFINED*
742  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC
743  * [23:17] | ??? | Unknown | *UNDEFINED*
744  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP
745  * [31:25] | ??? | Unknown | *UNDEFINED*
746  *
747  */
748 /*
749  * Field : mpu
750  *
751  * Security bit configuration for transactions from mpu to spi_master1. When
752  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
753  * Non-Secure transactions are allowed.
754  *
755  * Field Access Macros:
756  *
757  */
758 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU register field. */
759 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU_LSB 0
760 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU register field. */
761 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU_MSB 0
762 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU register field. */
763 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU_WIDTH 1
764 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU register field value. */
765 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU_SET_MSK 0x00000001
766 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU register field value. */
767 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU_CLR_MSK 0xfffffffe
768 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU register field. */
769 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU_RESET 0x0
770 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU field value from a register. */
771 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU_GET(value) (((value) & 0x00000001) >> 0)
772 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU register field value suitable for setting the register. */
773 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU_SET(value) (((value) << 0) & 0x00000001)
774 
775 /*
776  * Field : dma
777  *
778  * Security bit configuration for transactions from dma to spi_master1. When
779  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
780  * Non-Secure transactions are allowed.
781  *
782  * Field Access Macros:
783  *
784  */
785 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA register field. */
786 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA_LSB 8
787 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA register field. */
788 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA_MSB 8
789 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA register field. */
790 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA_WIDTH 1
791 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA register field value. */
792 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA_SET_MSK 0x00000100
793 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA register field value. */
794 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA_CLR_MSK 0xfffffeff
795 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA register field. */
796 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA_RESET 0x0
797 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA field value from a register. */
798 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA_GET(value) (((value) & 0x00000100) >> 8)
799 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA register field value suitable for setting the register. */
800 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA_SET(value) (((value) << 8) & 0x00000100)
801 
802 /*
803  * Field : fpga2soc
804  *
805  * Security bit configuration for transactions from fpga2soc to spi_master1. When
806  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
807  * Non-Secure transactions are allowed.
808  *
809  * Field Access Macros:
810  *
811  */
812 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC register field. */
813 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC_LSB 16
814 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC register field. */
815 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC_MSB 16
816 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC register field. */
817 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC_WIDTH 1
818 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC register field value. */
819 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC_SET_MSK 0x00010000
820 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC register field value. */
821 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC_CLR_MSK 0xfffeffff
822 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC register field. */
823 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC_RESET 0x0
824 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC field value from a register. */
825 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
826 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC register field value suitable for setting the register. */
827 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
828 
829 /*
830  * Field : axi_ap
831  *
832  * Security bit configuration for transactions from axi_ap to spi_master1. When
833  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
834  * Non-Secure transactions are allowed.
835  *
836  * Field Access Macros:
837  *
838  */
839 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP register field. */
840 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP_LSB 24
841 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP register field. */
842 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP_MSB 24
843 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP register field. */
844 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP_WIDTH 1
845 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP register field value. */
846 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP_SET_MSK 0x01000000
847 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP register field value. */
848 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP_CLR_MSK 0xfeffffff
849 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP register field. */
850 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP_RESET 0x0
851 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP field value from a register. */
852 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
853 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP register field value suitable for setting the register. */
854 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
855 
856 #ifndef __ASSEMBLY__
857 /*
858  * WARNING: The C register and register group struct declarations are provided for
859  * convenience and illustrative purposes. They should, however, be used with
860  * caution as the C language standard provides no guarantees about the alignment or
861  * atomicity of device memory accesses. The recommended practice for coding device
862  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
863  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
864  * alt_write_dword() functions for 64 bit registers.
865  *
866  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1.
867  */
868 struct ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_s
869 {
870  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU */
871  uint32_t : 7; /* *UNDEFINED* */
872  volatile uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA */
873  uint32_t : 7; /* *UNDEFINED* */
874  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC */
875  uint32_t : 7; /* *UNDEFINED* */
876  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP */
877  uint32_t : 7; /* *UNDEFINED* */
878 };
879 
880 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1. */
881 typedef struct ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_s ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_t;
882 #endif /* __ASSEMBLY__ */
883 
884 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1 register. */
885 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_RESET 0x00000000
886 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1 register from the beginning of the component. */
887 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_OFST 0x20
888 
889 /*
890  * Register : spi_slave0
891  *
892  * Per-Master Security bit for spi_slave0
893  *
894  * Register Layout
895  *
896  * Bits | Access | Reset | Description
897  * :--------|:-------|:--------|:------------------------------------------
898  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU
899  * [7:1] | ??? | Unknown | *UNDEFINED*
900  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA
901  * [15:9] | ??? | Unknown | *UNDEFINED*
902  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC
903  * [23:17] | ??? | Unknown | *UNDEFINED*
904  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP
905  * [31:25] | ??? | Unknown | *UNDEFINED*
906  *
907  */
908 /*
909  * Field : mpu
910  *
911  * Security bit configuration for transactions from mpu to spi_slave0. When cleared
912  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
913  * Secure transactions are allowed.
914  *
915  * Field Access Macros:
916  *
917  */
918 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU register field. */
919 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU_LSB 0
920 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU register field. */
921 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU_MSB 0
922 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU register field. */
923 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU_WIDTH 1
924 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU register field value. */
925 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU_SET_MSK 0x00000001
926 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU register field value. */
927 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU_CLR_MSK 0xfffffffe
928 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU register field. */
929 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU_RESET 0x0
930 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU field value from a register. */
931 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU_GET(value) (((value) & 0x00000001) >> 0)
932 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU register field value suitable for setting the register. */
933 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU_SET(value) (((value) << 0) & 0x00000001)
934 
935 /*
936  * Field : dma
937  *
938  * Security bit configuration for transactions from dma to spi_slave0. When cleared
939  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
940  * Secure transactions are allowed.
941  *
942  * Field Access Macros:
943  *
944  */
945 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA register field. */
946 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA_LSB 8
947 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA register field. */
948 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA_MSB 8
949 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA register field. */
950 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA_WIDTH 1
951 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA register field value. */
952 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA_SET_MSK 0x00000100
953 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA register field value. */
954 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA_CLR_MSK 0xfffffeff
955 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA register field. */
956 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA_RESET 0x0
957 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA field value from a register. */
958 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA_GET(value) (((value) & 0x00000100) >> 8)
959 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA register field value suitable for setting the register. */
960 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA_SET(value) (((value) << 8) & 0x00000100)
961 
962 /*
963  * Field : fpga2soc
964  *
965  * Security bit configuration for transactions from fpga2soc to spi_slave0. When
966  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
967  * Non-Secure transactions are allowed.
968  *
969  * Field Access Macros:
970  *
971  */
972 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC register field. */
973 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC_LSB 16
974 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC register field. */
975 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC_MSB 16
976 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC register field. */
977 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC_WIDTH 1
978 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC register field value. */
979 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC_SET_MSK 0x00010000
980 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC register field value. */
981 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC_CLR_MSK 0xfffeffff
982 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC register field. */
983 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC_RESET 0x0
984 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC field value from a register. */
985 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
986 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC register field value suitable for setting the register. */
987 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
988 
989 /*
990  * Field : axi_ap
991  *
992  * Security bit configuration for transactions from axi_ap to spi_slave0. When
993  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
994  * Non-Secure transactions are allowed.
995  *
996  * Field Access Macros:
997  *
998  */
999 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP register field. */
1000 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP_LSB 24
1001 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP register field. */
1002 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP_MSB 24
1003 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP register field. */
1004 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP_WIDTH 1
1005 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP register field value. */
1006 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP_SET_MSK 0x01000000
1007 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP register field value. */
1008 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP_CLR_MSK 0xfeffffff
1009 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP register field. */
1010 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP_RESET 0x0
1011 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP field value from a register. */
1012 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1013 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP register field value suitable for setting the register. */
1014 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1015 
1016 #ifndef __ASSEMBLY__
1017 /*
1018  * WARNING: The C register and register group struct declarations are provided for
1019  * convenience and illustrative purposes. They should, however, be used with
1020  * caution as the C language standard provides no guarantees about the alignment or
1021  * atomicity of device memory accesses. The recommended practice for coding device
1022  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1023  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1024  * alt_write_dword() functions for 64 bit registers.
1025  *
1026  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0.
1027  */
1028 struct ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_s
1029 {
1030  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU */
1031  uint32_t : 7; /* *UNDEFINED* */
1032  volatile uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA */
1033  uint32_t : 7; /* *UNDEFINED* */
1034  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC */
1035  uint32_t : 7; /* *UNDEFINED* */
1036  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP */
1037  uint32_t : 7; /* *UNDEFINED* */
1038 };
1039 
1040 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0. */
1041 typedef struct ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_s ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_t;
1042 #endif /* __ASSEMBLY__ */
1043 
1044 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0 register. */
1045 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_RESET 0x00000000
1046 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0 register from the beginning of the component. */
1047 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_OFST 0x24
1048 
1049 /*
1050  * Register : spi_slave1
1051  *
1052  * Per-Master Security bit for spi_slave1
1053  *
1054  * Register Layout
1055  *
1056  * Bits | Access | Reset | Description
1057  * :--------|:-------|:--------|:------------------------------------------
1058  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU
1059  * [7:1] | ??? | Unknown | *UNDEFINED*
1060  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA
1061  * [15:9] | ??? | Unknown | *UNDEFINED*
1062  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC
1063  * [23:17] | ??? | Unknown | *UNDEFINED*
1064  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP
1065  * [31:25] | ??? | Unknown | *UNDEFINED*
1066  *
1067  */
1068 /*
1069  * Field : mpu
1070  *
1071  * Security bit configuration for transactions from mpu to spi_slave1. When cleared
1072  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1073  * Secure transactions are allowed.
1074  *
1075  * Field Access Macros:
1076  *
1077  */
1078 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU register field. */
1079 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU_LSB 0
1080 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU register field. */
1081 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU_MSB 0
1082 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU register field. */
1083 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU_WIDTH 1
1084 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU register field value. */
1085 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU_SET_MSK 0x00000001
1086 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU register field value. */
1087 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU_CLR_MSK 0xfffffffe
1088 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU register field. */
1089 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU_RESET 0x0
1090 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU field value from a register. */
1091 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU_GET(value) (((value) & 0x00000001) >> 0)
1092 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU register field value suitable for setting the register. */
1093 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU_SET(value) (((value) << 0) & 0x00000001)
1094 
1095 /*
1096  * Field : dma
1097  *
1098  * Security bit configuration for transactions from dma to spi_slave1. When cleared
1099  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1100  * Secure transactions are allowed.
1101  *
1102  * Field Access Macros:
1103  *
1104  */
1105 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA register field. */
1106 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA_LSB 8
1107 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA register field. */
1108 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA_MSB 8
1109 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA register field. */
1110 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA_WIDTH 1
1111 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA register field value. */
1112 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA_SET_MSK 0x00000100
1113 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA register field value. */
1114 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA_CLR_MSK 0xfffffeff
1115 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA register field. */
1116 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA_RESET 0x0
1117 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA field value from a register. */
1118 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA_GET(value) (((value) & 0x00000100) >> 8)
1119 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA register field value suitable for setting the register. */
1120 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA_SET(value) (((value) << 8) & 0x00000100)
1121 
1122 /*
1123  * Field : fpga2soc
1124  *
1125  * Security bit configuration for transactions from fpga2soc to spi_slave1. When
1126  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1127  * Non-Secure transactions are allowed.
1128  *
1129  * Field Access Macros:
1130  *
1131  */
1132 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC register field. */
1133 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC_LSB 16
1134 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC register field. */
1135 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC_MSB 16
1136 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC register field. */
1137 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC_WIDTH 1
1138 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC register field value. */
1139 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC_SET_MSK 0x00010000
1140 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC register field value. */
1141 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC_CLR_MSK 0xfffeffff
1142 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC register field. */
1143 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC_RESET 0x0
1144 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC field value from a register. */
1145 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1146 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC register field value suitable for setting the register. */
1147 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1148 
1149 /*
1150  * Field : axi_ap
1151  *
1152  * Security bit configuration for transactions from axi_ap to spi_slave1. When
1153  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1154  * Non-Secure transactions are allowed.
1155  *
1156  * Field Access Macros:
1157  *
1158  */
1159 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP register field. */
1160 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP_LSB 24
1161 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP register field. */
1162 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP_MSB 24
1163 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP register field. */
1164 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP_WIDTH 1
1165 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP register field value. */
1166 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP_SET_MSK 0x01000000
1167 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP register field value. */
1168 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP_CLR_MSK 0xfeffffff
1169 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP register field. */
1170 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP_RESET 0x0
1171 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP field value from a register. */
1172 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1173 /* Produces a ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP register field value suitable for setting the register. */
1174 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1175 
1176 #ifndef __ASSEMBLY__
1177 /*
1178  * WARNING: The C register and register group struct declarations are provided for
1179  * convenience and illustrative purposes. They should, however, be used with
1180  * caution as the C language standard provides no guarantees about the alignment or
1181  * atomicity of device memory accesses. The recommended practice for coding device
1182  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1183  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1184  * alt_write_dword() functions for 64 bit registers.
1185  *
1186  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1.
1187  */
1188 struct ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_s
1189 {
1190  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU */
1191  uint32_t : 7; /* *UNDEFINED* */
1192  volatile uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA */
1193  uint32_t : 7; /* *UNDEFINED* */
1194  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC */
1195  uint32_t : 7; /* *UNDEFINED* */
1196  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP */
1197  uint32_t : 7; /* *UNDEFINED* */
1198 };
1199 
1200 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1. */
1201 typedef struct ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_s ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_t;
1202 #endif /* __ASSEMBLY__ */
1203 
1204 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1 register. */
1205 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_RESET 0x00000000
1206 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1 register from the beginning of the component. */
1207 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_OFST 0x28
1208 
1209 /*
1210  * Register : emac0
1211  *
1212  * Per-Master Security bit for emac0
1213  *
1214  * Register Layout
1215  *
1216  * Bits | Access | Reset | Description
1217  * :--------|:-------|:--------|:-------------------------------------
1218  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU
1219  * [15:1] | ??? | Unknown | *UNDEFINED*
1220  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC
1221  * [23:17] | ??? | Unknown | *UNDEFINED*
1222  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP
1223  * [31:25] | ??? | Unknown | *UNDEFINED*
1224  *
1225  */
1226 /*
1227  * Field : mpu
1228  *
1229  * Security bit configuration for transactions from mpu to emac0. When cleared (0),
1230  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
1231  * transactions are allowed.
1232  *
1233  * Field Access Macros:
1234  *
1235  */
1236 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU register field. */
1237 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_LSB 0
1238 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU register field. */
1239 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_MSB 0
1240 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU register field. */
1241 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_WIDTH 1
1242 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU register field value. */
1243 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_SET_MSK 0x00000001
1244 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU register field value. */
1245 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_CLR_MSK 0xfffffffe
1246 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU register field. */
1247 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_RESET 0x0
1248 /* Extracts the ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU field value from a register. */
1249 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_GET(value) (((value) & 0x00000001) >> 0)
1250 /* Produces a ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU register field value suitable for setting the register. */
1251 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_SET(value) (((value) << 0) & 0x00000001)
1252 
1253 /*
1254  * Field : fpga2soc
1255  *
1256  * Security bit configuration for transactions from fpga2soc to emac0. When cleared
1257  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1258  * Secure transactions are allowed.
1259  *
1260  * Field Access Macros:
1261  *
1262  */
1263 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC register field. */
1264 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC_LSB 16
1265 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC register field. */
1266 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC_MSB 16
1267 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC register field. */
1268 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC_WIDTH 1
1269 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC register field value. */
1270 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC_SET_MSK 0x00010000
1271 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC register field value. */
1272 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC_CLR_MSK 0xfffeffff
1273 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC register field. */
1274 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC_RESET 0x0
1275 /* Extracts the ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC field value from a register. */
1276 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1277 /* Produces a ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC register field value suitable for setting the register. */
1278 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1279 
1280 /*
1281  * Field : axi_ap
1282  *
1283  * Security bit configuration for transactions from axi_ap to emac0. When cleared
1284  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1285  * Secure transactions are allowed.
1286  *
1287  * Field Access Macros:
1288  *
1289  */
1290 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP register field. */
1291 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP_LSB 24
1292 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP register field. */
1293 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP_MSB 24
1294 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP register field. */
1295 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP_WIDTH 1
1296 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP register field value. */
1297 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP_SET_MSK 0x01000000
1298 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP register field value. */
1299 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP_CLR_MSK 0xfeffffff
1300 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP register field. */
1301 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP_RESET 0x0
1302 /* Extracts the ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP field value from a register. */
1303 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1304 /* Produces a ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP register field value suitable for setting the register. */
1305 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1306 
1307 #ifndef __ASSEMBLY__
1308 /*
1309  * WARNING: The C register and register group struct declarations are provided for
1310  * convenience and illustrative purposes. They should, however, be used with
1311  * caution as the C language standard provides no guarantees about the alignment or
1312  * atomicity of device memory accesses. The recommended practice for coding device
1313  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1314  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1315  * alt_write_dword() functions for 64 bit registers.
1316  *
1317  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_EMAC0.
1318  */
1319 struct ALT_NOC_FW_L4_PER_SCR_EMAC0_s
1320 {
1321  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU */
1322  uint32_t : 15; /* *UNDEFINED* */
1323  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC */
1324  uint32_t : 7; /* *UNDEFINED* */
1325  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP */
1326  uint32_t : 7; /* *UNDEFINED* */
1327 };
1328 
1329 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_EMAC0. */
1330 typedef struct ALT_NOC_FW_L4_PER_SCR_EMAC0_s ALT_NOC_FW_L4_PER_SCR_EMAC0_t;
1331 #endif /* __ASSEMBLY__ */
1332 
1333 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC0 register. */
1334 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_RESET 0x00000000
1335 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_EMAC0 register from the beginning of the component. */
1336 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_OFST 0x2c
1337 
1338 /*
1339  * Register : emac1
1340  *
1341  * Per-Master Security bit for emac1
1342  *
1343  * Register Layout
1344  *
1345  * Bits | Access | Reset | Description
1346  * :--------|:-------|:--------|:-------------------------------------
1347  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU
1348  * [15:1] | ??? | Unknown | *UNDEFINED*
1349  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC
1350  * [23:17] | ??? | Unknown | *UNDEFINED*
1351  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP
1352  * [31:25] | ??? | Unknown | *UNDEFINED*
1353  *
1354  */
1355 /*
1356  * Field : mpu
1357  *
1358  * Security bit configuration for transactions from mpu to emac1. When cleared (0),
1359  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
1360  * transactions are allowed.
1361  *
1362  * Field Access Macros:
1363  *
1364  */
1365 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU register field. */
1366 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_LSB 0
1367 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU register field. */
1368 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_MSB 0
1369 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU register field. */
1370 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_WIDTH 1
1371 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU register field value. */
1372 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_SET_MSK 0x00000001
1373 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU register field value. */
1374 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_CLR_MSK 0xfffffffe
1375 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU register field. */
1376 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_RESET 0x0
1377 /* Extracts the ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU field value from a register. */
1378 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_GET(value) (((value) & 0x00000001) >> 0)
1379 /* Produces a ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU register field value suitable for setting the register. */
1380 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_SET(value) (((value) << 0) & 0x00000001)
1381 
1382 /*
1383  * Field : fpga2soc
1384  *
1385  * Security bit configuration for transactions from fpga2soc to emac1. When cleared
1386  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1387  * Secure transactions are allowed.
1388  *
1389  * Field Access Macros:
1390  *
1391  */
1392 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC register field. */
1393 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC_LSB 16
1394 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC register field. */
1395 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC_MSB 16
1396 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC register field. */
1397 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC_WIDTH 1
1398 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC register field value. */
1399 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC_SET_MSK 0x00010000
1400 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC register field value. */
1401 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC_CLR_MSK 0xfffeffff
1402 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC register field. */
1403 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC_RESET 0x0
1404 /* Extracts the ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC field value from a register. */
1405 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1406 /* Produces a ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC register field value suitable for setting the register. */
1407 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1408 
1409 /*
1410  * Field : axi_ap
1411  *
1412  * Security bit configuration for transactions from axi_ap to emac1. When cleared
1413  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1414  * Secure transactions are allowed.
1415  *
1416  * Field Access Macros:
1417  *
1418  */
1419 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP register field. */
1420 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP_LSB 24
1421 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP register field. */
1422 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP_MSB 24
1423 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP register field. */
1424 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP_WIDTH 1
1425 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP register field value. */
1426 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP_SET_MSK 0x01000000
1427 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP register field value. */
1428 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP_CLR_MSK 0xfeffffff
1429 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP register field. */
1430 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP_RESET 0x0
1431 /* Extracts the ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP field value from a register. */
1432 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1433 /* Produces a ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP register field value suitable for setting the register. */
1434 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1435 
1436 #ifndef __ASSEMBLY__
1437 /*
1438  * WARNING: The C register and register group struct declarations are provided for
1439  * convenience and illustrative purposes. They should, however, be used with
1440  * caution as the C language standard provides no guarantees about the alignment or
1441  * atomicity of device memory accesses. The recommended practice for coding device
1442  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1443  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1444  * alt_write_dword() functions for 64 bit registers.
1445  *
1446  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_EMAC1.
1447  */
1448 struct ALT_NOC_FW_L4_PER_SCR_EMAC1_s
1449 {
1450  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU */
1451  uint32_t : 15; /* *UNDEFINED* */
1452  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC */
1453  uint32_t : 7; /* *UNDEFINED* */
1454  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP */
1455  uint32_t : 7; /* *UNDEFINED* */
1456 };
1457 
1458 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_EMAC1. */
1459 typedef struct ALT_NOC_FW_L4_PER_SCR_EMAC1_s ALT_NOC_FW_L4_PER_SCR_EMAC1_t;
1460 #endif /* __ASSEMBLY__ */
1461 
1462 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC1 register. */
1463 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_RESET 0x00000000
1464 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_EMAC1 register from the beginning of the component. */
1465 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_OFST 0x30
1466 
1467 /*
1468  * Register : emac2
1469  *
1470  * Per-Master Security bit for emac2
1471  *
1472  * Register Layout
1473  *
1474  * Bits | Access | Reset | Description
1475  * :--------|:-------|:--------|:-------------------------------------
1476  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU
1477  * [15:1] | ??? | Unknown | *UNDEFINED*
1478  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC
1479  * [23:17] | ??? | Unknown | *UNDEFINED*
1480  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP
1481  * [31:25] | ??? | Unknown | *UNDEFINED*
1482  *
1483  */
1484 /*
1485  * Field : mpu
1486  *
1487  * Security bit configuration for transactions from mpu to emac2. When cleared (0),
1488  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
1489  * transactions are allowed.
1490  *
1491  * Field Access Macros:
1492  *
1493  */
1494 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU register field. */
1495 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_LSB 0
1496 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU register field. */
1497 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_MSB 0
1498 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU register field. */
1499 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_WIDTH 1
1500 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU register field value. */
1501 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_SET_MSK 0x00000001
1502 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU register field value. */
1503 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_CLR_MSK 0xfffffffe
1504 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU register field. */
1505 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_RESET 0x0
1506 /* Extracts the ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU field value from a register. */
1507 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_GET(value) (((value) & 0x00000001) >> 0)
1508 /* Produces a ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU register field value suitable for setting the register. */
1509 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_SET(value) (((value) << 0) & 0x00000001)
1510 
1511 /*
1512  * Field : fpga2soc
1513  *
1514  * Security bit configuration for transactions from fpga2soc to emac2. When cleared
1515  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1516  * Secure transactions are allowed.
1517  *
1518  * Field Access Macros:
1519  *
1520  */
1521 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC register field. */
1522 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC_LSB 16
1523 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC register field. */
1524 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC_MSB 16
1525 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC register field. */
1526 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC_WIDTH 1
1527 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC register field value. */
1528 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC_SET_MSK 0x00010000
1529 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC register field value. */
1530 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC_CLR_MSK 0xfffeffff
1531 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC register field. */
1532 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC_RESET 0x0
1533 /* Extracts the ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC field value from a register. */
1534 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1535 /* Produces a ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC register field value suitable for setting the register. */
1536 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1537 
1538 /*
1539  * Field : axi_ap
1540  *
1541  * Security bit configuration for transactions from axi_ap to emac2. When cleared
1542  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1543  * Secure transactions are allowed.
1544  *
1545  * Field Access Macros:
1546  *
1547  */
1548 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP register field. */
1549 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP_LSB 24
1550 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP register field. */
1551 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP_MSB 24
1552 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP register field. */
1553 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP_WIDTH 1
1554 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP register field value. */
1555 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP_SET_MSK 0x01000000
1556 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP register field value. */
1557 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP_CLR_MSK 0xfeffffff
1558 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP register field. */
1559 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP_RESET 0x0
1560 /* Extracts the ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP field value from a register. */
1561 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1562 /* Produces a ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP register field value suitable for setting the register. */
1563 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1564 
1565 #ifndef __ASSEMBLY__
1566 /*
1567  * WARNING: The C register and register group struct declarations are provided for
1568  * convenience and illustrative purposes. They should, however, be used with
1569  * caution as the C language standard provides no guarantees about the alignment or
1570  * atomicity of device memory accesses. The recommended practice for coding device
1571  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1572  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1573  * alt_write_dword() functions for 64 bit registers.
1574  *
1575  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_EMAC2.
1576  */
1577 struct ALT_NOC_FW_L4_PER_SCR_EMAC2_s
1578 {
1579  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU */
1580  uint32_t : 15; /* *UNDEFINED* */
1581  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC */
1582  uint32_t : 7; /* *UNDEFINED* */
1583  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP */
1584  uint32_t : 7; /* *UNDEFINED* */
1585 };
1586 
1587 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_EMAC2. */
1588 typedef struct ALT_NOC_FW_L4_PER_SCR_EMAC2_s ALT_NOC_FW_L4_PER_SCR_EMAC2_t;
1589 #endif /* __ASSEMBLY__ */
1590 
1591 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_EMAC2 register. */
1592 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_RESET 0x00000000
1593 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_EMAC2 register from the beginning of the component. */
1594 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_OFST 0x34
1595 
1596 /*
1597  * Register : sdmmc
1598  *
1599  * Per-Master Security bit for sdmmc
1600  *
1601  * Register Layout
1602  *
1603  * Bits | Access | Reset | Description
1604  * :--------|:-------|:--------|:-------------------------------------
1605  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU
1606  * [15:1] | ??? | Unknown | *UNDEFINED*
1607  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC
1608  * [23:17] | ??? | Unknown | *UNDEFINED*
1609  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP
1610  * [31:25] | ??? | Unknown | *UNDEFINED*
1611  *
1612  */
1613 /*
1614  * Field : mpu
1615  *
1616  * Security bit configuration for transactions from mpu to sdmmc. When cleared (0),
1617  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
1618  * transactions are allowed.
1619  *
1620  * Field Access Macros:
1621  *
1622  */
1623 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU register field. */
1624 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_LSB 0
1625 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU register field. */
1626 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_MSB 0
1627 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU register field. */
1628 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_WIDTH 1
1629 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU register field value. */
1630 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_SET_MSK 0x00000001
1631 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU register field value. */
1632 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_CLR_MSK 0xfffffffe
1633 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU register field. */
1634 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_RESET 0x0
1635 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU field value from a register. */
1636 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_GET(value) (((value) & 0x00000001) >> 0)
1637 /* Produces a ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU register field value suitable for setting the register. */
1638 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_SET(value) (((value) << 0) & 0x00000001)
1639 
1640 /*
1641  * Field : fpga2soc
1642  *
1643  * Security bit configuration for transactions from fpga2soc to sdmmc. When cleared
1644  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1645  * Secure transactions are allowed.
1646  *
1647  * Field Access Macros:
1648  *
1649  */
1650 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC register field. */
1651 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC_LSB 16
1652 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC register field. */
1653 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC_MSB 16
1654 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC register field. */
1655 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC_WIDTH 1
1656 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC register field value. */
1657 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC_SET_MSK 0x00010000
1658 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC register field value. */
1659 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC_CLR_MSK 0xfffeffff
1660 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC register field. */
1661 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC_RESET 0x0
1662 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC field value from a register. */
1663 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1664 /* Produces a ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC register field value suitable for setting the register. */
1665 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1666 
1667 /*
1668  * Field : axi_ap
1669  *
1670  * Security bit configuration for transactions from axi_ap to sdmmc. When cleared
1671  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1672  * Secure transactions are allowed.
1673  *
1674  * Field Access Macros:
1675  *
1676  */
1677 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP register field. */
1678 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP_LSB 24
1679 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP register field. */
1680 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP_MSB 24
1681 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP register field. */
1682 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP_WIDTH 1
1683 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP register field value. */
1684 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP_SET_MSK 0x01000000
1685 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP register field value. */
1686 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP_CLR_MSK 0xfeffffff
1687 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP register field. */
1688 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP_RESET 0x0
1689 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP field value from a register. */
1690 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1691 /* Produces a ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP register field value suitable for setting the register. */
1692 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1693 
1694 #ifndef __ASSEMBLY__
1695 /*
1696  * WARNING: The C register and register group struct declarations are provided for
1697  * convenience and illustrative purposes. They should, however, be used with
1698  * caution as the C language standard provides no guarantees about the alignment or
1699  * atomicity of device memory accesses. The recommended practice for coding device
1700  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1701  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1702  * alt_write_dword() functions for 64 bit registers.
1703  *
1704  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_SDMMC.
1705  */
1706 struct ALT_NOC_FW_L4_PER_SCR_SDMMC_s
1707 {
1708  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU */
1709  uint32_t : 15; /* *UNDEFINED* */
1710  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC */
1711  uint32_t : 7; /* *UNDEFINED* */
1712  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP */
1713  uint32_t : 7; /* *UNDEFINED* */
1714 };
1715 
1716 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_SDMMC. */
1717 typedef struct ALT_NOC_FW_L4_PER_SCR_SDMMC_s ALT_NOC_FW_L4_PER_SCR_SDMMC_t;
1718 #endif /* __ASSEMBLY__ */
1719 
1720 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SDMMC register. */
1721 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_RESET 0x00000000
1722 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_SDMMC register from the beginning of the component. */
1723 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_OFST 0x40
1724 
1725 /*
1726  * Register : gpio0
1727  *
1728  * Per-Master Security bit for gpio0
1729  *
1730  * Register Layout
1731  *
1732  * Bits | Access | Reset | Description
1733  * :--------|:-------|:--------|:-------------------------------------
1734  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU
1735  * [7:1] | ??? | Unknown | *UNDEFINED*
1736  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA
1737  * [15:9] | ??? | Unknown | *UNDEFINED*
1738  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC
1739  * [23:17] | ??? | Unknown | *UNDEFINED*
1740  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP
1741  * [31:25] | ??? | Unknown | *UNDEFINED*
1742  *
1743  */
1744 /*
1745  * Field : mpu
1746  *
1747  * Security bit configuration for transactions from mpu to gpio0. When cleared (0),
1748  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
1749  * transactions are allowed.
1750  *
1751  * Field Access Macros:
1752  *
1753  */
1754 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU register field. */
1755 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_LSB 0
1756 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU register field. */
1757 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_MSB 0
1758 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU register field. */
1759 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_WIDTH 1
1760 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU register field value. */
1761 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_SET_MSK 0x00000001
1762 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU register field value. */
1763 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_CLR_MSK 0xfffffffe
1764 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU register field. */
1765 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_RESET 0x0
1766 /* Extracts the ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU field value from a register. */
1767 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_GET(value) (((value) & 0x00000001) >> 0)
1768 /* Produces a ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU register field value suitable for setting the register. */
1769 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_SET(value) (((value) << 0) & 0x00000001)
1770 
1771 /*
1772  * Field : dma
1773  *
1774  * Security bit configuration for transactions from dma to gpio0. When cleared (0),
1775  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
1776  * transactions are allowed.
1777  *
1778  * Field Access Macros:
1779  *
1780  */
1781 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA register field. */
1782 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_LSB 8
1783 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA register field. */
1784 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_MSB 8
1785 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA register field. */
1786 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_WIDTH 1
1787 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA register field value. */
1788 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_SET_MSK 0x00000100
1789 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA register field value. */
1790 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_CLR_MSK 0xfffffeff
1791 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA register field. */
1792 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_RESET 0x0
1793 /* Extracts the ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA field value from a register. */
1794 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_GET(value) (((value) & 0x00000100) >> 8)
1795 /* Produces a ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA register field value suitable for setting the register. */
1796 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_SET(value) (((value) << 8) & 0x00000100)
1797 
1798 /*
1799  * Field : fpga2soc
1800  *
1801  * Security bit configuration for transactions from fpga2soc to gpio0. When cleared
1802  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1803  * Secure transactions are allowed.
1804  *
1805  * Field Access Macros:
1806  *
1807  */
1808 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC register field. */
1809 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC_LSB 16
1810 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC register field. */
1811 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC_MSB 16
1812 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC register field. */
1813 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC_WIDTH 1
1814 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC register field value. */
1815 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC_SET_MSK 0x00010000
1816 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC register field value. */
1817 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC_CLR_MSK 0xfffeffff
1818 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC register field. */
1819 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC_RESET 0x0
1820 /* Extracts the ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC field value from a register. */
1821 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1822 /* Produces a ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC register field value suitable for setting the register. */
1823 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1824 
1825 /*
1826  * Field : axi_ap
1827  *
1828  * Security bit configuration for transactions from axi_ap to gpio0. When cleared
1829  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1830  * Secure transactions are allowed.
1831  *
1832  * Field Access Macros:
1833  *
1834  */
1835 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP register field. */
1836 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP_LSB 24
1837 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP register field. */
1838 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP_MSB 24
1839 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP register field. */
1840 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP_WIDTH 1
1841 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP register field value. */
1842 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP_SET_MSK 0x01000000
1843 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP register field value. */
1844 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP_CLR_MSK 0xfeffffff
1845 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP register field. */
1846 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP_RESET 0x0
1847 /* Extracts the ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP field value from a register. */
1848 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1849 /* Produces a ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP register field value suitable for setting the register. */
1850 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1851 
1852 #ifndef __ASSEMBLY__
1853 /*
1854  * WARNING: The C register and register group struct declarations are provided for
1855  * convenience and illustrative purposes. They should, however, be used with
1856  * caution as the C language standard provides no guarantees about the alignment or
1857  * atomicity of device memory accesses. The recommended practice for coding device
1858  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1859  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1860  * alt_write_dword() functions for 64 bit registers.
1861  *
1862  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_GPIO0.
1863  */
1864 struct ALT_NOC_FW_L4_PER_SCR_GPIO0_s
1865 {
1866  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU */
1867  uint32_t : 7; /* *UNDEFINED* */
1868  volatile uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA */
1869  uint32_t : 7; /* *UNDEFINED* */
1870  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC */
1871  uint32_t : 7; /* *UNDEFINED* */
1872  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP */
1873  uint32_t : 7; /* *UNDEFINED* */
1874 };
1875 
1876 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_GPIO0. */
1877 typedef struct ALT_NOC_FW_L4_PER_SCR_GPIO0_s ALT_NOC_FW_L4_PER_SCR_GPIO0_t;
1878 #endif /* __ASSEMBLY__ */
1879 
1880 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO0 register. */
1881 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_RESET 0x00000000
1882 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_GPIO0 register from the beginning of the component. */
1883 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_OFST 0x44
1884 
1885 /*
1886  * Register : gpio1
1887  *
1888  * Per-Master Security bit for gpio1
1889  *
1890  * Register Layout
1891  *
1892  * Bits | Access | Reset | Description
1893  * :--------|:-------|:--------|:-------------------------------------
1894  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU
1895  * [7:1] | ??? | Unknown | *UNDEFINED*
1896  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA
1897  * [15:9] | ??? | Unknown | *UNDEFINED*
1898  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC
1899  * [23:17] | ??? | Unknown | *UNDEFINED*
1900  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP
1901  * [31:25] | ??? | Unknown | *UNDEFINED*
1902  *
1903  */
1904 /*
1905  * Field : mpu
1906  *
1907  * Security bit configuration for transactions from mpu to gpio1. When cleared (0),
1908  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
1909  * transactions are allowed.
1910  *
1911  * Field Access Macros:
1912  *
1913  */
1914 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU register field. */
1915 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_LSB 0
1916 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU register field. */
1917 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_MSB 0
1918 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU register field. */
1919 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_WIDTH 1
1920 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU register field value. */
1921 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_SET_MSK 0x00000001
1922 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU register field value. */
1923 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_CLR_MSK 0xfffffffe
1924 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU register field. */
1925 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_RESET 0x0
1926 /* Extracts the ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU field value from a register. */
1927 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_GET(value) (((value) & 0x00000001) >> 0)
1928 /* Produces a ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU register field value suitable for setting the register. */
1929 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_SET(value) (((value) << 0) & 0x00000001)
1930 
1931 /*
1932  * Field : dma
1933  *
1934  * Security bit configuration for transactions from dma to gpio1. When cleared (0),
1935  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
1936  * transactions are allowed.
1937  *
1938  * Field Access Macros:
1939  *
1940  */
1941 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA register field. */
1942 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_LSB 8
1943 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA register field. */
1944 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_MSB 8
1945 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA register field. */
1946 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_WIDTH 1
1947 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA register field value. */
1948 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_SET_MSK 0x00000100
1949 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA register field value. */
1950 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_CLR_MSK 0xfffffeff
1951 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA register field. */
1952 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_RESET 0x0
1953 /* Extracts the ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA field value from a register. */
1954 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_GET(value) (((value) & 0x00000100) >> 8)
1955 /* Produces a ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA register field value suitable for setting the register. */
1956 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_SET(value) (((value) << 8) & 0x00000100)
1957 
1958 /*
1959  * Field : fpga2soc
1960  *
1961  * Security bit configuration for transactions from fpga2soc to gpio1. When cleared
1962  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1963  * Secure transactions are allowed.
1964  *
1965  * Field Access Macros:
1966  *
1967  */
1968 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC register field. */
1969 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC_LSB 16
1970 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC register field. */
1971 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC_MSB 16
1972 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC register field. */
1973 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC_WIDTH 1
1974 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC register field value. */
1975 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC_SET_MSK 0x00010000
1976 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC register field value. */
1977 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC_CLR_MSK 0xfffeffff
1978 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC register field. */
1979 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC_RESET 0x0
1980 /* Extracts the ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC field value from a register. */
1981 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1982 /* Produces a ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC register field value suitable for setting the register. */
1983 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1984 
1985 /*
1986  * Field : axi_ap
1987  *
1988  * Security bit configuration for transactions from axi_ap to gpio1. When cleared
1989  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1990  * Secure transactions are allowed.
1991  *
1992  * Field Access Macros:
1993  *
1994  */
1995 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP register field. */
1996 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP_LSB 24
1997 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP register field. */
1998 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP_MSB 24
1999 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP register field. */
2000 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP_WIDTH 1
2001 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP register field value. */
2002 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP_SET_MSK 0x01000000
2003 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP register field value. */
2004 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP_CLR_MSK 0xfeffffff
2005 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP register field. */
2006 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP_RESET 0x0
2007 /* Extracts the ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP field value from a register. */
2008 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2009 /* Produces a ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP register field value suitable for setting the register. */
2010 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2011 
2012 #ifndef __ASSEMBLY__
2013 /*
2014  * WARNING: The C register and register group struct declarations are provided for
2015  * convenience and illustrative purposes. They should, however, be used with
2016  * caution as the C language standard provides no guarantees about the alignment or
2017  * atomicity of device memory accesses. The recommended practice for coding device
2018  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2019  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2020  * alt_write_dword() functions for 64 bit registers.
2021  *
2022  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_GPIO1.
2023  */
2024 struct ALT_NOC_FW_L4_PER_SCR_GPIO1_s
2025 {
2026  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU */
2027  uint32_t : 7; /* *UNDEFINED* */
2028  volatile uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA */
2029  uint32_t : 7; /* *UNDEFINED* */
2030  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC */
2031  uint32_t : 7; /* *UNDEFINED* */
2032  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP */
2033  uint32_t : 7; /* *UNDEFINED* */
2034 };
2035 
2036 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_GPIO1. */
2037 typedef struct ALT_NOC_FW_L4_PER_SCR_GPIO1_s ALT_NOC_FW_L4_PER_SCR_GPIO1_t;
2038 #endif /* __ASSEMBLY__ */
2039 
2040 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_GPIO1 register. */
2041 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_RESET 0x00000000
2042 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_GPIO1 register from the beginning of the component. */
2043 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_OFST 0x48
2044 
2045 /*
2046  * Register : i2c0
2047  *
2048  * Per-Master Security bit for i2c0
2049  *
2050  * Register Layout
2051  *
2052  * Bits | Access | Reset | Description
2053  * :--------|:-------|:--------|:------------------------------------
2054  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C0_MPU
2055  * [7:1] | ??? | Unknown | *UNDEFINED*
2056  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C0_DMA
2057  * [15:9] | ??? | Unknown | *UNDEFINED*
2058  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC
2059  * [23:17] | ??? | Unknown | *UNDEFINED*
2060  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP
2061  * [31:25] | ??? | Unknown | *UNDEFINED*
2062  *
2063  */
2064 /*
2065  * Field : mpu
2066  *
2067  * Security bit configuration for transactions from mpu to i2c0. When cleared (0),
2068  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
2069  * transactions are allowed.
2070  *
2071  * Field Access Macros:
2072  *
2073  */
2074 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C0_MPU register field. */
2075 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_LSB 0
2076 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C0_MPU register field. */
2077 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_MSB 0
2078 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C0_MPU register field. */
2079 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_WIDTH 1
2080 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C0_MPU register field value. */
2081 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_SET_MSK 0x00000001
2082 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C0_MPU register field value. */
2083 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_CLR_MSK 0xfffffffe
2084 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C0_MPU register field. */
2085 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_RESET 0x0
2086 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C0_MPU field value from a register. */
2087 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_GET(value) (((value) & 0x00000001) >> 0)
2088 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C0_MPU register field value suitable for setting the register. */
2089 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_SET(value) (((value) << 0) & 0x00000001)
2090 
2091 /*
2092  * Field : dma
2093  *
2094  * Security bit configuration for transactions from dma to i2c0. When cleared (0),
2095  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
2096  * transactions are allowed.
2097  *
2098  * Field Access Macros:
2099  *
2100  */
2101 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C0_DMA register field. */
2102 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_LSB 8
2103 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C0_DMA register field. */
2104 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_MSB 8
2105 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C0_DMA register field. */
2106 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_WIDTH 1
2107 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C0_DMA register field value. */
2108 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_SET_MSK 0x00000100
2109 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C0_DMA register field value. */
2110 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_CLR_MSK 0xfffffeff
2111 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C0_DMA register field. */
2112 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_RESET 0x0
2113 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C0_DMA field value from a register. */
2114 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_GET(value) (((value) & 0x00000100) >> 8)
2115 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C0_DMA register field value suitable for setting the register. */
2116 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_SET(value) (((value) << 8) & 0x00000100)
2117 
2118 /*
2119  * Field : fpga2soc
2120  *
2121  * Security bit configuration for transactions from fpga2soc to i2c0. When cleared
2122  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2123  * Secure transactions are allowed.
2124  *
2125  * Field Access Macros:
2126  *
2127  */
2128 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC register field. */
2129 #define ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC_LSB 16
2130 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC register field. */
2131 #define ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC_MSB 16
2132 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC register field. */
2133 #define ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC_WIDTH 1
2134 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC register field value. */
2135 #define ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC_SET_MSK 0x00010000
2136 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC register field value. */
2137 #define ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC_CLR_MSK 0xfffeffff
2138 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC register field. */
2139 #define ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC_RESET 0x0
2140 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC field value from a register. */
2141 #define ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2142 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC register field value suitable for setting the register. */
2143 #define ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2144 
2145 /*
2146  * Field : axi_ap
2147  *
2148  * Security bit configuration for transactions from axi_ap to i2c0. When cleared
2149  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2150  * Secure transactions are allowed.
2151  *
2152  * Field Access Macros:
2153  *
2154  */
2155 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP register field. */
2156 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP_LSB 24
2157 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP register field. */
2158 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP_MSB 24
2159 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP register field. */
2160 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP_WIDTH 1
2161 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP register field value. */
2162 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP_SET_MSK 0x01000000
2163 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP register field value. */
2164 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP_CLR_MSK 0xfeffffff
2165 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP register field. */
2166 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP_RESET 0x0
2167 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP field value from a register. */
2168 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2169 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP register field value suitable for setting the register. */
2170 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2171 
2172 #ifndef __ASSEMBLY__
2173 /*
2174  * WARNING: The C register and register group struct declarations are provided for
2175  * convenience and illustrative purposes. They should, however, be used with
2176  * caution as the C language standard provides no guarantees about the alignment or
2177  * atomicity of device memory accesses. The recommended practice for coding device
2178  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2179  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2180  * alt_write_dword() functions for 64 bit registers.
2181  *
2182  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_I2C0.
2183  */
2184 struct ALT_NOC_FW_L4_PER_SCR_I2C0_s
2185 {
2186  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C0_MPU */
2187  uint32_t : 7; /* *UNDEFINED* */
2188  volatile uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C0_DMA */
2189  uint32_t : 7; /* *UNDEFINED* */
2190  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC */
2191  uint32_t : 7; /* *UNDEFINED* */
2192  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP */
2193  uint32_t : 7; /* *UNDEFINED* */
2194 };
2195 
2196 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_I2C0. */
2197 typedef struct ALT_NOC_FW_L4_PER_SCR_I2C0_s ALT_NOC_FW_L4_PER_SCR_I2C0_t;
2198 #endif /* __ASSEMBLY__ */
2199 
2200 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C0 register. */
2201 #define ALT_NOC_FW_L4_PER_SCR_I2C0_RESET 0x00000000
2202 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_I2C0 register from the beginning of the component. */
2203 #define ALT_NOC_FW_L4_PER_SCR_I2C0_OFST 0x50
2204 
2205 /*
2206  * Register : i2c1
2207  *
2208  * Per-Master Security bit for i2c1
2209  *
2210  * Register Layout
2211  *
2212  * Bits | Access | Reset | Description
2213  * :--------|:-------|:--------|:------------------------------------
2214  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C1_MPU
2215  * [7:1] | ??? | Unknown | *UNDEFINED*
2216  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C1_DMA
2217  * [15:9] | ??? | Unknown | *UNDEFINED*
2218  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC
2219  * [23:17] | ??? | Unknown | *UNDEFINED*
2220  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP
2221  * [31:25] | ??? | Unknown | *UNDEFINED*
2222  *
2223  */
2224 /*
2225  * Field : mpu
2226  *
2227  * Security bit configuration for transactions from mpu to i2c1. When cleared (0),
2228  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
2229  * transactions are allowed.
2230  *
2231  * Field Access Macros:
2232  *
2233  */
2234 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C1_MPU register field. */
2235 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_LSB 0
2236 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C1_MPU register field. */
2237 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_MSB 0
2238 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C1_MPU register field. */
2239 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_WIDTH 1
2240 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C1_MPU register field value. */
2241 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_SET_MSK 0x00000001
2242 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C1_MPU register field value. */
2243 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_CLR_MSK 0xfffffffe
2244 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C1_MPU register field. */
2245 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_RESET 0x0
2246 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C1_MPU field value from a register. */
2247 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_GET(value) (((value) & 0x00000001) >> 0)
2248 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C1_MPU register field value suitable for setting the register. */
2249 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_SET(value) (((value) << 0) & 0x00000001)
2250 
2251 /*
2252  * Field : dma
2253  *
2254  * Security bit configuration for transactions from dma to i2c1. When cleared (0),
2255  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
2256  * transactions are allowed.
2257  *
2258  * Field Access Macros:
2259  *
2260  */
2261 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C1_DMA register field. */
2262 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_LSB 8
2263 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C1_DMA register field. */
2264 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_MSB 8
2265 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C1_DMA register field. */
2266 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_WIDTH 1
2267 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C1_DMA register field value. */
2268 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_SET_MSK 0x00000100
2269 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C1_DMA register field value. */
2270 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_CLR_MSK 0xfffffeff
2271 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C1_DMA register field. */
2272 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_RESET 0x0
2273 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C1_DMA field value from a register. */
2274 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_GET(value) (((value) & 0x00000100) >> 8)
2275 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C1_DMA register field value suitable for setting the register. */
2276 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_SET(value) (((value) << 8) & 0x00000100)
2277 
2278 /*
2279  * Field : fpga2soc
2280  *
2281  * Security bit configuration for transactions from fpga2soc to i2c1. When cleared
2282  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2283  * Secure transactions are allowed.
2284  *
2285  * Field Access Macros:
2286  *
2287  */
2288 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC register field. */
2289 #define ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC_LSB 16
2290 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC register field. */
2291 #define ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC_MSB 16
2292 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC register field. */
2293 #define ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC_WIDTH 1
2294 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC register field value. */
2295 #define ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC_SET_MSK 0x00010000
2296 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC register field value. */
2297 #define ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC_CLR_MSK 0xfffeffff
2298 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC register field. */
2299 #define ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC_RESET 0x0
2300 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC field value from a register. */
2301 #define ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2302 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC register field value suitable for setting the register. */
2303 #define ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2304 
2305 /*
2306  * Field : axi_ap
2307  *
2308  * Security bit configuration for transactions from axi_ap to i2c1. When cleared
2309  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2310  * Secure transactions are allowed.
2311  *
2312  * Field Access Macros:
2313  *
2314  */
2315 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP register field. */
2316 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP_LSB 24
2317 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP register field. */
2318 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP_MSB 24
2319 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP register field. */
2320 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP_WIDTH 1
2321 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP register field value. */
2322 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP_SET_MSK 0x01000000
2323 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP register field value. */
2324 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP_CLR_MSK 0xfeffffff
2325 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP register field. */
2326 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP_RESET 0x0
2327 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP field value from a register. */
2328 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2329 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP register field value suitable for setting the register. */
2330 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2331 
2332 #ifndef __ASSEMBLY__
2333 /*
2334  * WARNING: The C register and register group struct declarations are provided for
2335  * convenience and illustrative purposes. They should, however, be used with
2336  * caution as the C language standard provides no guarantees about the alignment or
2337  * atomicity of device memory accesses. The recommended practice for coding device
2338  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2339  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2340  * alt_write_dword() functions for 64 bit registers.
2341  *
2342  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_I2C1.
2343  */
2344 struct ALT_NOC_FW_L4_PER_SCR_I2C1_s
2345 {
2346  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C1_MPU */
2347  uint32_t : 7; /* *UNDEFINED* */
2348  volatile uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C1_DMA */
2349  uint32_t : 7; /* *UNDEFINED* */
2350  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC */
2351  uint32_t : 7; /* *UNDEFINED* */
2352  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP */
2353  uint32_t : 7; /* *UNDEFINED* */
2354 };
2355 
2356 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_I2C1. */
2357 typedef struct ALT_NOC_FW_L4_PER_SCR_I2C1_s ALT_NOC_FW_L4_PER_SCR_I2C1_t;
2358 #endif /* __ASSEMBLY__ */
2359 
2360 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C1 register. */
2361 #define ALT_NOC_FW_L4_PER_SCR_I2C1_RESET 0x00000000
2362 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_I2C1 register from the beginning of the component. */
2363 #define ALT_NOC_FW_L4_PER_SCR_I2C1_OFST 0x54
2364 
2365 /*
2366  * Register : i2c2
2367  *
2368  * Per-Master Security bit for i2c2
2369  *
2370  * Register Layout
2371  *
2372  * Bits | Access | Reset | Description
2373  * :--------|:-------|:--------|:------------------------------------
2374  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C2_MPU
2375  * [7:1] | ??? | Unknown | *UNDEFINED*
2376  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C2_DMA
2377  * [15:9] | ??? | Unknown | *UNDEFINED*
2378  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC
2379  * [23:17] | ??? | Unknown | *UNDEFINED*
2380  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP
2381  * [31:25] | ??? | Unknown | *UNDEFINED*
2382  *
2383  */
2384 /*
2385  * Field : mpu
2386  *
2387  * Security bit configuration for transactions from mpu to i2c2. When cleared (0),
2388  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
2389  * transactions are allowed.
2390  *
2391  * Field Access Macros:
2392  *
2393  */
2394 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C2_MPU register field. */
2395 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_LSB 0
2396 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C2_MPU register field. */
2397 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_MSB 0
2398 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C2_MPU register field. */
2399 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_WIDTH 1
2400 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C2_MPU register field value. */
2401 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_SET_MSK 0x00000001
2402 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C2_MPU register field value. */
2403 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_CLR_MSK 0xfffffffe
2404 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C2_MPU register field. */
2405 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_RESET 0x0
2406 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C2_MPU field value from a register. */
2407 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_GET(value) (((value) & 0x00000001) >> 0)
2408 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C2_MPU register field value suitable for setting the register. */
2409 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_SET(value) (((value) << 0) & 0x00000001)
2410 
2411 /*
2412  * Field : dma
2413  *
2414  * Security bit configuration for transactions from dma to i2c2. When cleared (0),
2415  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
2416  * transactions are allowed.
2417  *
2418  * Field Access Macros:
2419  *
2420  */
2421 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C2_DMA register field. */
2422 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_LSB 8
2423 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C2_DMA register field. */
2424 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_MSB 8
2425 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C2_DMA register field. */
2426 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_WIDTH 1
2427 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C2_DMA register field value. */
2428 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_SET_MSK 0x00000100
2429 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C2_DMA register field value. */
2430 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_CLR_MSK 0xfffffeff
2431 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C2_DMA register field. */
2432 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_RESET 0x0
2433 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C2_DMA field value from a register. */
2434 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_GET(value) (((value) & 0x00000100) >> 8)
2435 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C2_DMA register field value suitable for setting the register. */
2436 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_SET(value) (((value) << 8) & 0x00000100)
2437 
2438 /*
2439  * Field : fpga2soc
2440  *
2441  * Security bit configuration for transactions from fpga2soc to i2c2. When cleared
2442  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2443  * Secure transactions are allowed.
2444  *
2445  * Field Access Macros:
2446  *
2447  */
2448 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC register field. */
2449 #define ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC_LSB 16
2450 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC register field. */
2451 #define ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC_MSB 16
2452 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC register field. */
2453 #define ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC_WIDTH 1
2454 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC register field value. */
2455 #define ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC_SET_MSK 0x00010000
2456 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC register field value. */
2457 #define ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC_CLR_MSK 0xfffeffff
2458 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC register field. */
2459 #define ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC_RESET 0x0
2460 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC field value from a register. */
2461 #define ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2462 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC register field value suitable for setting the register. */
2463 #define ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2464 
2465 /*
2466  * Field : axi_ap
2467  *
2468  * Security bit configuration for transactions from axi_ap to i2c2. When cleared
2469  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2470  * Secure transactions are allowed.
2471  *
2472  * Field Access Macros:
2473  *
2474  */
2475 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP register field. */
2476 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP_LSB 24
2477 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP register field. */
2478 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP_MSB 24
2479 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP register field. */
2480 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP_WIDTH 1
2481 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP register field value. */
2482 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP_SET_MSK 0x01000000
2483 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP register field value. */
2484 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP_CLR_MSK 0xfeffffff
2485 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP register field. */
2486 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP_RESET 0x0
2487 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP field value from a register. */
2488 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2489 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP register field value suitable for setting the register. */
2490 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2491 
2492 #ifndef __ASSEMBLY__
2493 /*
2494  * WARNING: The C register and register group struct declarations are provided for
2495  * convenience and illustrative purposes. They should, however, be used with
2496  * caution as the C language standard provides no guarantees about the alignment or
2497  * atomicity of device memory accesses. The recommended practice for coding device
2498  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2499  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2500  * alt_write_dword() functions for 64 bit registers.
2501  *
2502  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_I2C2.
2503  */
2504 struct ALT_NOC_FW_L4_PER_SCR_I2C2_s
2505 {
2506  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C2_MPU */
2507  uint32_t : 7; /* *UNDEFINED* */
2508  volatile uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C2_DMA */
2509  uint32_t : 7; /* *UNDEFINED* */
2510  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC */
2511  uint32_t : 7; /* *UNDEFINED* */
2512  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP */
2513  uint32_t : 7; /* *UNDEFINED* */
2514 };
2515 
2516 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_I2C2. */
2517 typedef struct ALT_NOC_FW_L4_PER_SCR_I2C2_s ALT_NOC_FW_L4_PER_SCR_I2C2_t;
2518 #endif /* __ASSEMBLY__ */
2519 
2520 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C2 register. */
2521 #define ALT_NOC_FW_L4_PER_SCR_I2C2_RESET 0x00000000
2522 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_I2C2 register from the beginning of the component. */
2523 #define ALT_NOC_FW_L4_PER_SCR_I2C2_OFST 0x58
2524 
2525 /*
2526  * Register : i2c3
2527  *
2528  * Per-Master Security bit for i2c3
2529  *
2530  * Register Layout
2531  *
2532  * Bits | Access | Reset | Description
2533  * :--------|:-------|:--------|:------------------------------------
2534  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C3_MPU
2535  * [7:1] | ??? | Unknown | *UNDEFINED*
2536  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C3_DMA
2537  * [15:9] | ??? | Unknown | *UNDEFINED*
2538  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC
2539  * [23:17] | ??? | Unknown | *UNDEFINED*
2540  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP
2541  * [31:25] | ??? | Unknown | *UNDEFINED*
2542  *
2543  */
2544 /*
2545  * Field : mpu
2546  *
2547  * Security bit configuration for transactions from mpu to i2c3. When cleared (0),
2548  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
2549  * transactions are allowed.
2550  *
2551  * Field Access Macros:
2552  *
2553  */
2554 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C3_MPU register field. */
2555 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_LSB 0
2556 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C3_MPU register field. */
2557 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_MSB 0
2558 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C3_MPU register field. */
2559 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_WIDTH 1
2560 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C3_MPU register field value. */
2561 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_SET_MSK 0x00000001
2562 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C3_MPU register field value. */
2563 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_CLR_MSK 0xfffffffe
2564 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C3_MPU register field. */
2565 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_RESET 0x0
2566 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C3_MPU field value from a register. */
2567 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_GET(value) (((value) & 0x00000001) >> 0)
2568 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C3_MPU register field value suitable for setting the register. */
2569 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_SET(value) (((value) << 0) & 0x00000001)
2570 
2571 /*
2572  * Field : dma
2573  *
2574  * Security bit configuration for transactions from dma to i2c3. When cleared (0),
2575  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
2576  * transactions are allowed.
2577  *
2578  * Field Access Macros:
2579  *
2580  */
2581 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C3_DMA register field. */
2582 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_LSB 8
2583 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C3_DMA register field. */
2584 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_MSB 8
2585 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C3_DMA register field. */
2586 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_WIDTH 1
2587 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C3_DMA register field value. */
2588 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_SET_MSK 0x00000100
2589 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C3_DMA register field value. */
2590 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_CLR_MSK 0xfffffeff
2591 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C3_DMA register field. */
2592 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_RESET 0x0
2593 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C3_DMA field value from a register. */
2594 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_GET(value) (((value) & 0x00000100) >> 8)
2595 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C3_DMA register field value suitable for setting the register. */
2596 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_SET(value) (((value) << 8) & 0x00000100)
2597 
2598 /*
2599  * Field : fpga2soc
2600  *
2601  * Security bit configuration for transactions from fpga2soc to i2c3. When cleared
2602  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2603  * Secure transactions are allowed.
2604  *
2605  * Field Access Macros:
2606  *
2607  */
2608 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC register field. */
2609 #define ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC_LSB 16
2610 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC register field. */
2611 #define ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC_MSB 16
2612 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC register field. */
2613 #define ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC_WIDTH 1
2614 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC register field value. */
2615 #define ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC_SET_MSK 0x00010000
2616 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC register field value. */
2617 #define ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC_CLR_MSK 0xfffeffff
2618 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC register field. */
2619 #define ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC_RESET 0x0
2620 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC field value from a register. */
2621 #define ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2622 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC register field value suitable for setting the register. */
2623 #define ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2624 
2625 /*
2626  * Field : axi_ap
2627  *
2628  * Security bit configuration for transactions from axi_ap to i2c3. When cleared
2629  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2630  * Secure transactions are allowed.
2631  *
2632  * Field Access Macros:
2633  *
2634  */
2635 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP register field. */
2636 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP_LSB 24
2637 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP register field. */
2638 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP_MSB 24
2639 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP register field. */
2640 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP_WIDTH 1
2641 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP register field value. */
2642 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP_SET_MSK 0x01000000
2643 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP register field value. */
2644 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP_CLR_MSK 0xfeffffff
2645 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP register field. */
2646 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP_RESET 0x0
2647 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP field value from a register. */
2648 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2649 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP register field value suitable for setting the register. */
2650 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2651 
2652 #ifndef __ASSEMBLY__
2653 /*
2654  * WARNING: The C register and register group struct declarations are provided for
2655  * convenience and illustrative purposes. They should, however, be used with
2656  * caution as the C language standard provides no guarantees about the alignment or
2657  * atomicity of device memory accesses. The recommended practice for coding device
2658  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2659  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2660  * alt_write_dword() functions for 64 bit registers.
2661  *
2662  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_I2C3.
2663  */
2664 struct ALT_NOC_FW_L4_PER_SCR_I2C3_s
2665 {
2666  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C3_MPU */
2667  uint32_t : 7; /* *UNDEFINED* */
2668  volatile uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C3_DMA */
2669  uint32_t : 7; /* *UNDEFINED* */
2670  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC */
2671  uint32_t : 7; /* *UNDEFINED* */
2672  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP */
2673  uint32_t : 7; /* *UNDEFINED* */
2674 };
2675 
2676 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_I2C3. */
2677 typedef struct ALT_NOC_FW_L4_PER_SCR_I2C3_s ALT_NOC_FW_L4_PER_SCR_I2C3_t;
2678 #endif /* __ASSEMBLY__ */
2679 
2680 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C3 register. */
2681 #define ALT_NOC_FW_L4_PER_SCR_I2C3_RESET 0x00000000
2682 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_I2C3 register from the beginning of the component. */
2683 #define ALT_NOC_FW_L4_PER_SCR_I2C3_OFST 0x5c
2684 
2685 /*
2686  * Register : i2c4
2687  *
2688  * Per-Master Security bit for i2c4
2689  *
2690  * Register Layout
2691  *
2692  * Bits | Access | Reset | Description
2693  * :--------|:-------|:--------|:------------------------------------
2694  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C4_MPU
2695  * [7:1] | ??? | Unknown | *UNDEFINED*
2696  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C4_DMA
2697  * [15:9] | ??? | Unknown | *UNDEFINED*
2698  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC
2699  * [23:17] | ??? | Unknown | *UNDEFINED*
2700  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP
2701  * [31:25] | ??? | Unknown | *UNDEFINED*
2702  *
2703  */
2704 /*
2705  * Field : mpu
2706  *
2707  * Security bit configuration for transactions from mpu to i2c4. When cleared (0),
2708  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
2709  * transactions are allowed.
2710  *
2711  * Field Access Macros:
2712  *
2713  */
2714 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C4_MPU register field. */
2715 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_LSB 0
2716 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C4_MPU register field. */
2717 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_MSB 0
2718 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C4_MPU register field. */
2719 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_WIDTH 1
2720 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C4_MPU register field value. */
2721 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_SET_MSK 0x00000001
2722 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C4_MPU register field value. */
2723 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_CLR_MSK 0xfffffffe
2724 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C4_MPU register field. */
2725 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_RESET 0x0
2726 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C4_MPU field value from a register. */
2727 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_GET(value) (((value) & 0x00000001) >> 0)
2728 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C4_MPU register field value suitable for setting the register. */
2729 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_SET(value) (((value) << 0) & 0x00000001)
2730 
2731 /*
2732  * Field : dma
2733  *
2734  * Security bit configuration for transactions from dma to i2c4. When cleared (0),
2735  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
2736  * transactions are allowed.
2737  *
2738  * Field Access Macros:
2739  *
2740  */
2741 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C4_DMA register field. */
2742 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_LSB 8
2743 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C4_DMA register field. */
2744 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_MSB 8
2745 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C4_DMA register field. */
2746 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_WIDTH 1
2747 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C4_DMA register field value. */
2748 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_SET_MSK 0x00000100
2749 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C4_DMA register field value. */
2750 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_CLR_MSK 0xfffffeff
2751 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C4_DMA register field. */
2752 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_RESET 0x0
2753 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C4_DMA field value from a register. */
2754 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_GET(value) (((value) & 0x00000100) >> 8)
2755 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C4_DMA register field value suitable for setting the register. */
2756 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_SET(value) (((value) << 8) & 0x00000100)
2757 
2758 /*
2759  * Field : fpga2soc
2760  *
2761  * Security bit configuration for transactions from fpga2soc to i2c4. When cleared
2762  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2763  * Secure transactions are allowed.
2764  *
2765  * Field Access Macros:
2766  *
2767  */
2768 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC register field. */
2769 #define ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC_LSB 16
2770 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC register field. */
2771 #define ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC_MSB 16
2772 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC register field. */
2773 #define ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC_WIDTH 1
2774 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC register field value. */
2775 #define ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC_SET_MSK 0x00010000
2776 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC register field value. */
2777 #define ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC_CLR_MSK 0xfffeffff
2778 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC register field. */
2779 #define ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC_RESET 0x0
2780 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC field value from a register. */
2781 #define ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2782 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC register field value suitable for setting the register. */
2783 #define ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2784 
2785 /*
2786  * Field : axi_ap
2787  *
2788  * Security bit configuration for transactions from axi_ap to. When cleared (0),
2789  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
2790  * transactions are allowed.
2791  *
2792  * Field Access Macros:
2793  *
2794  */
2795 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP register field. */
2796 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP_LSB 24
2797 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP register field. */
2798 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP_MSB 24
2799 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP register field. */
2800 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP_WIDTH 1
2801 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP register field value. */
2802 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP_SET_MSK 0x01000000
2803 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP register field value. */
2804 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP_CLR_MSK 0xfeffffff
2805 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP register field. */
2806 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP_RESET 0x0
2807 /* Extracts the ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP field value from a register. */
2808 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2809 /* Produces a ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP register field value suitable for setting the register. */
2810 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2811 
2812 #ifndef __ASSEMBLY__
2813 /*
2814  * WARNING: The C register and register group struct declarations are provided for
2815  * convenience and illustrative purposes. They should, however, be used with
2816  * caution as the C language standard provides no guarantees about the alignment or
2817  * atomicity of device memory accesses. The recommended practice for coding device
2818  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2819  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2820  * alt_write_dword() functions for 64 bit registers.
2821  *
2822  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_I2C4.
2823  */
2824 struct ALT_NOC_FW_L4_PER_SCR_I2C4_s
2825 {
2826  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C4_MPU */
2827  uint32_t : 7; /* *UNDEFINED* */
2828  volatile uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C4_DMA */
2829  uint32_t : 7; /* *UNDEFINED* */
2830  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC */
2831  uint32_t : 7; /* *UNDEFINED* */
2832  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP */
2833  uint32_t : 7; /* *UNDEFINED* */
2834 };
2835 
2836 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_I2C4. */
2837 typedef struct ALT_NOC_FW_L4_PER_SCR_I2C4_s ALT_NOC_FW_L4_PER_SCR_I2C4_t;
2838 #endif /* __ASSEMBLY__ */
2839 
2840 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_I2C4 register. */
2841 #define ALT_NOC_FW_L4_PER_SCR_I2C4_RESET 0x00000000
2842 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_I2C4 register from the beginning of the component. */
2843 #define ALT_NOC_FW_L4_PER_SCR_I2C4_OFST 0x60
2844 
2845 /*
2846  * Register : sp_timer0
2847  *
2848  * Per-Master Security bit for sp_timer0
2849  *
2850  * Register Layout
2851  *
2852  * Bits | Access | Reset | Description
2853  * :--------|:-------|:--------|:-----------------------------------------
2854  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU
2855  * [7:1] | ??? | Unknown | *UNDEFINED*
2856  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA
2857  * [15:9] | ??? | Unknown | *UNDEFINED*
2858  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC
2859  * [23:17] | ??? | Unknown | *UNDEFINED*
2860  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP
2861  * [31:25] | ??? | Unknown | *UNDEFINED*
2862  *
2863  */
2864 /*
2865  * Field : mpu
2866  *
2867  * Security bit configuration for transactions from mpu to sp_timer0. When cleared
2868  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2869  * Secure transactions are allowed.
2870  *
2871  * Field Access Macros:
2872  *
2873  */
2874 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU register field. */
2875 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU_LSB 0
2876 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU register field. */
2877 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU_MSB 0
2878 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU register field. */
2879 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU_WIDTH 1
2880 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU register field value. */
2881 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU_SET_MSK 0x00000001
2882 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU register field value. */
2883 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU_CLR_MSK 0xfffffffe
2884 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU register field. */
2885 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU_RESET 0x0
2886 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU field value from a register. */
2887 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU_GET(value) (((value) & 0x00000001) >> 0)
2888 /* Produces a ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU register field value suitable for setting the register. */
2889 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU_SET(value) (((value) << 0) & 0x00000001)
2890 
2891 /*
2892  * Field : dma
2893  *
2894  * Security bit configuration for transactions from dma to sp_timer0. When cleared
2895  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2896  * Secure transactions are allowed.
2897  *
2898  * Field Access Macros:
2899  *
2900  */
2901 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA register field. */
2902 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA_LSB 8
2903 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA register field. */
2904 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA_MSB 8
2905 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA register field. */
2906 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA_WIDTH 1
2907 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA register field value. */
2908 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA_SET_MSK 0x00000100
2909 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA register field value. */
2910 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA_CLR_MSK 0xfffffeff
2911 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA register field. */
2912 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA_RESET 0x0
2913 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA field value from a register. */
2914 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA_GET(value) (((value) & 0x00000100) >> 8)
2915 /* Produces a ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA register field value suitable for setting the register. */
2916 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA_SET(value) (((value) << 8) & 0x00000100)
2917 
2918 /*
2919  * Field : fpga2soc
2920  *
2921  * Security bit configuration for transactions from fpga2soc to sp_timer0. When
2922  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2923  * Non-Secure transactions are allowed.
2924  *
2925  * Field Access Macros:
2926  *
2927  */
2928 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC register field. */
2929 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC_LSB 16
2930 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC register field. */
2931 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC_MSB 16
2932 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC register field. */
2933 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC_WIDTH 1
2934 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC register field value. */
2935 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC_SET_MSK 0x00010000
2936 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC register field value. */
2937 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC_CLR_MSK 0xfffeffff
2938 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC register field. */
2939 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC_RESET 0x0
2940 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC field value from a register. */
2941 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2942 /* Produces a ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC register field value suitable for setting the register. */
2943 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2944 
2945 /*
2946  * Field : axi_ap
2947  *
2948  * Security bit configuration for transactions from axi_ap to sp_timer0. When
2949  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2950  * Non-Secure transactions are allowed.
2951  *
2952  * Field Access Macros:
2953  *
2954  */
2955 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP register field. */
2956 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP_LSB 24
2957 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP register field. */
2958 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP_MSB 24
2959 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP register field. */
2960 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP_WIDTH 1
2961 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP register field value. */
2962 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP_SET_MSK 0x01000000
2963 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP register field value. */
2964 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP_CLR_MSK 0xfeffffff
2965 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP register field. */
2966 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP_RESET 0x0
2967 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP field value from a register. */
2968 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2969 /* Produces a ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP register field value suitable for setting the register. */
2970 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2971 
2972 #ifndef __ASSEMBLY__
2973 /*
2974  * WARNING: The C register and register group struct declarations are provided for
2975  * convenience and illustrative purposes. They should, however, be used with
2976  * caution as the C language standard provides no guarantees about the alignment or
2977  * atomicity of device memory accesses. The recommended practice for coding device
2978  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2979  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2980  * alt_write_dword() functions for 64 bit registers.
2981  *
2982  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_SP_TIMER0.
2983  */
2984 struct ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_s
2985 {
2986  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU */
2987  uint32_t : 7; /* *UNDEFINED* */
2988  volatile uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA */
2989  uint32_t : 7; /* *UNDEFINED* */
2990  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC */
2991  uint32_t : 7; /* *UNDEFINED* */
2992  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP */
2993  uint32_t : 7; /* *UNDEFINED* */
2994 };
2995 
2996 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_SP_TIMER0. */
2997 typedef struct ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_s ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_t;
2998 #endif /* __ASSEMBLY__ */
2999 
3000 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0 register. */
3001 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_RESET 0x00000000
3002 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER0 register from the beginning of the component. */
3003 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_OFST 0x64
3004 
3005 /*
3006  * Register : sp_timer1
3007  *
3008  * Per-Master Security bit for sp_timer1
3009  *
3010  * Register Layout
3011  *
3012  * Bits | Access | Reset | Description
3013  * :--------|:-------|:--------|:-----------------------------------------
3014  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU
3015  * [7:1] | ??? | Unknown | *UNDEFINED*
3016  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA
3017  * [15:9] | ??? | Unknown | *UNDEFINED*
3018  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC
3019  * [23:17] | ??? | Unknown | *UNDEFINED*
3020  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP
3021  * [31:25] | ??? | Unknown | *UNDEFINED*
3022  *
3023  */
3024 /*
3025  * Field : mpu
3026  *
3027  * Security bit configuration for transactions from mpu to sp_timer1. When cleared
3028  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3029  * Secure transactions are allowed.
3030  *
3031  * Field Access Macros:
3032  *
3033  */
3034 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU register field. */
3035 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU_LSB 0
3036 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU register field. */
3037 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU_MSB 0
3038 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU register field. */
3039 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU_WIDTH 1
3040 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU register field value. */
3041 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU_SET_MSK 0x00000001
3042 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU register field value. */
3043 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU_CLR_MSK 0xfffffffe
3044 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU register field. */
3045 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU_RESET 0x0
3046 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU field value from a register. */
3047 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU_GET(value) (((value) & 0x00000001) >> 0)
3048 /* Produces a ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU register field value suitable for setting the register. */
3049 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU_SET(value) (((value) << 0) & 0x00000001)
3050 
3051 /*
3052  * Field : dma
3053  *
3054  * Security bit configuration for transactions from dma to sp_timer1. When cleared
3055  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3056  * Secure transactions are allowed.
3057  *
3058  * Field Access Macros:
3059  *
3060  */
3061 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA register field. */
3062 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA_LSB 8
3063 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA register field. */
3064 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA_MSB 8
3065 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA register field. */
3066 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA_WIDTH 1
3067 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA register field value. */
3068 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA_SET_MSK 0x00000100
3069 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA register field value. */
3070 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA_CLR_MSK 0xfffffeff
3071 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA register field. */
3072 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA_RESET 0x0
3073 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA field value from a register. */
3074 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA_GET(value) (((value) & 0x00000100) >> 8)
3075 /* Produces a ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA register field value suitable for setting the register. */
3076 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA_SET(value) (((value) << 8) & 0x00000100)
3077 
3078 /*
3079  * Field : fpga2soc
3080  *
3081  * Security bit configuration for transactions from fpga2soc to sp_timer1. When
3082  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3083  * Non-Secure transactions are allowed.
3084  *
3085  * Field Access Macros:
3086  *
3087  */
3088 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC register field. */
3089 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC_LSB 16
3090 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC register field. */
3091 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC_MSB 16
3092 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC register field. */
3093 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC_WIDTH 1
3094 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC register field value. */
3095 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC_SET_MSK 0x00010000
3096 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC register field value. */
3097 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC_CLR_MSK 0xfffeffff
3098 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC register field. */
3099 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC_RESET 0x0
3100 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC field value from a register. */
3101 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
3102 /* Produces a ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC register field value suitable for setting the register. */
3103 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
3104 
3105 /*
3106  * Field : axi_ap
3107  *
3108  * Security bit configuration for transactions from axi_ap to sp_timer1. When
3109  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3110  * Non-Secure transactions are allowed.
3111  *
3112  * Field Access Macros:
3113  *
3114  */
3115 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP register field. */
3116 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP_LSB 24
3117 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP register field. */
3118 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP_MSB 24
3119 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP register field. */
3120 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP_WIDTH 1
3121 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP register field value. */
3122 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP_SET_MSK 0x01000000
3123 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP register field value. */
3124 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP_CLR_MSK 0xfeffffff
3125 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP register field. */
3126 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP_RESET 0x0
3127 /* Extracts the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP field value from a register. */
3128 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
3129 /* Produces a ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP register field value suitable for setting the register. */
3130 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
3131 
3132 #ifndef __ASSEMBLY__
3133 /*
3134  * WARNING: The C register and register group struct declarations are provided for
3135  * convenience and illustrative purposes. They should, however, be used with
3136  * caution as the C language standard provides no guarantees about the alignment or
3137  * atomicity of device memory accesses. The recommended practice for coding device
3138  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3139  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3140  * alt_write_dword() functions for 64 bit registers.
3141  *
3142  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_SP_TIMER1.
3143  */
3144 struct ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_s
3145 {
3146  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU */
3147  uint32_t : 7; /* *UNDEFINED* */
3148  volatile uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA */
3149  uint32_t : 7; /* *UNDEFINED* */
3150  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC */
3151  uint32_t : 7; /* *UNDEFINED* */
3152  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP */
3153  uint32_t : 7; /* *UNDEFINED* */
3154 };
3155 
3156 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_SP_TIMER1. */
3157 typedef struct ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_s ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_t;
3158 #endif /* __ASSEMBLY__ */
3159 
3160 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1 register. */
3161 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_RESET 0x00000000
3162 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_SP_TIMER1 register from the beginning of the component. */
3163 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_OFST 0x68
3164 
3165 /*
3166  * Register : uart0
3167  *
3168  * Per-Master Security bit for uart0
3169  *
3170  * Register Layout
3171  *
3172  * Bits | Access | Reset | Description
3173  * :--------|:-------|:--------|:-------------------------------------
3174  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_UART0_MPU
3175  * [7:1] | ??? | Unknown | *UNDEFINED*
3176  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_UART0_DMA
3177  * [15:9] | ??? | Unknown | *UNDEFINED*
3178  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC
3179  * [23:17] | ??? | Unknown | *UNDEFINED*
3180  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP
3181  * [31:25] | ??? | Unknown | *UNDEFINED*
3182  *
3183  */
3184 /*
3185  * Field : mpu
3186  *
3187  * Security bit configuration for transactions from mpu to uart0. When cleared (0),
3188  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
3189  * transactions are allowed.
3190  *
3191  * Field Access Macros:
3192  *
3193  */
3194 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_UART0_MPU register field. */
3195 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_LSB 0
3196 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_UART0_MPU register field. */
3197 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_MSB 0
3198 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_UART0_MPU register field. */
3199 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_WIDTH 1
3200 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_UART0_MPU register field value. */
3201 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_SET_MSK 0x00000001
3202 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_UART0_MPU register field value. */
3203 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_CLR_MSK 0xfffffffe
3204 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_UART0_MPU register field. */
3205 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_RESET 0x0
3206 /* Extracts the ALT_NOC_FW_L4_PER_SCR_UART0_MPU field value from a register. */
3207 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_GET(value) (((value) & 0x00000001) >> 0)
3208 /* Produces a ALT_NOC_FW_L4_PER_SCR_UART0_MPU register field value suitable for setting the register. */
3209 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_SET(value) (((value) << 0) & 0x00000001)
3210 
3211 /*
3212  * Field : dma
3213  *
3214  * Security bit configuration for transactions from dma to uart0. When cleared (0),
3215  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
3216  * transactions are allowed.
3217  *
3218  * Field Access Macros:
3219  *
3220  */
3221 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_UART0_DMA register field. */
3222 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_LSB 8
3223 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_UART0_DMA register field. */
3224 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_MSB 8
3225 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_UART0_DMA register field. */
3226 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_WIDTH 1
3227 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_UART0_DMA register field value. */
3228 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_SET_MSK 0x00000100
3229 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_UART0_DMA register field value. */
3230 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_CLR_MSK 0xfffffeff
3231 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_UART0_DMA register field. */
3232 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_RESET 0x0
3233 /* Extracts the ALT_NOC_FW_L4_PER_SCR_UART0_DMA field value from a register. */
3234 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_GET(value) (((value) & 0x00000100) >> 8)
3235 /* Produces a ALT_NOC_FW_L4_PER_SCR_UART0_DMA register field value suitable for setting the register. */
3236 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_SET(value) (((value) << 8) & 0x00000100)
3237 
3238 /*
3239  * Field : fpga2soc
3240  *
3241  * Security bit configuration for transactions from fpga2soc to uart0. When cleared
3242  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3243  * Secure transactions are allowed.
3244  *
3245  * Field Access Macros:
3246  *
3247  */
3248 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC register field. */
3249 #define ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC_LSB 16
3250 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC register field. */
3251 #define ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC_MSB 16
3252 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC register field. */
3253 #define ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC_WIDTH 1
3254 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC register field value. */
3255 #define ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC_SET_MSK 0x00010000
3256 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC register field value. */
3257 #define ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC_CLR_MSK 0xfffeffff
3258 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC register field. */
3259 #define ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC_RESET 0x0
3260 /* Extracts the ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC field value from a register. */
3261 #define ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
3262 /* Produces a ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC register field value suitable for setting the register. */
3263 #define ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
3264 
3265 /*
3266  * Field : axi_ap
3267  *
3268  * Security bit configuration for transactions from axi_ap to uart0. When cleared
3269  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3270  * Secure transactions are allowed.
3271  *
3272  * Field Access Macros:
3273  *
3274  */
3275 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP register field. */
3276 #define ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP_LSB 24
3277 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP register field. */
3278 #define ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP_MSB 24
3279 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP register field. */
3280 #define ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP_WIDTH 1
3281 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP register field value. */
3282 #define ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP_SET_MSK 0x01000000
3283 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP register field value. */
3284 #define ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP_CLR_MSK 0xfeffffff
3285 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP register field. */
3286 #define ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP_RESET 0x0
3287 /* Extracts the ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP field value from a register. */
3288 #define ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
3289 /* Produces a ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP register field value suitable for setting the register. */
3290 #define ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
3291 
3292 #ifndef __ASSEMBLY__
3293 /*
3294  * WARNING: The C register and register group struct declarations are provided for
3295  * convenience and illustrative purposes. They should, however, be used with
3296  * caution as the C language standard provides no guarantees about the alignment or
3297  * atomicity of device memory accesses. The recommended practice for coding device
3298  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3299  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3300  * alt_write_dword() functions for 64 bit registers.
3301  *
3302  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_UART0.
3303  */
3304 struct ALT_NOC_FW_L4_PER_SCR_UART0_s
3305 {
3306  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_UART0_MPU */
3307  uint32_t : 7; /* *UNDEFINED* */
3308  volatile uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_UART0_DMA */
3309  uint32_t : 7; /* *UNDEFINED* */
3310  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC */
3311  uint32_t : 7; /* *UNDEFINED* */
3312  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP */
3313  uint32_t : 7; /* *UNDEFINED* */
3314 };
3315 
3316 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_UART0. */
3317 typedef struct ALT_NOC_FW_L4_PER_SCR_UART0_s ALT_NOC_FW_L4_PER_SCR_UART0_t;
3318 #endif /* __ASSEMBLY__ */
3319 
3320 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_UART0 register. */
3321 #define ALT_NOC_FW_L4_PER_SCR_UART0_RESET 0x00000000
3322 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_UART0 register from the beginning of the component. */
3323 #define ALT_NOC_FW_L4_PER_SCR_UART0_OFST 0x6c
3324 
3325 /*
3326  * Register : uart1
3327  *
3328  * Per-Master Security bit for uart1
3329  *
3330  * Register Layout
3331  *
3332  * Bits | Access | Reset | Description
3333  * :--------|:-------|:--------|:-------------------------------------
3334  * [0] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_UART1_MPU
3335  * [7:1] | ??? | Unknown | *UNDEFINED*
3336  * [8] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_UART1_DMA
3337  * [15:9] | ??? | Unknown | *UNDEFINED*
3338  * [16] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC
3339  * [23:17] | ??? | Unknown | *UNDEFINED*
3340  * [24] | RW | 0x0 | ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP
3341  * [31:25] | ??? | Unknown | *UNDEFINED*
3342  *
3343  */
3344 /*
3345  * Field : mpu
3346  *
3347  * Security bit configuration for transactions from mpu to uart1. When cleared (0),
3348  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
3349  * transactions are allowed.
3350  *
3351  * Field Access Macros:
3352  *
3353  */
3354 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_UART1_MPU register field. */
3355 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_LSB 0
3356 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_UART1_MPU register field. */
3357 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_MSB 0
3358 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_UART1_MPU register field. */
3359 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_WIDTH 1
3360 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_UART1_MPU register field value. */
3361 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_SET_MSK 0x00000001
3362 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_UART1_MPU register field value. */
3363 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_CLR_MSK 0xfffffffe
3364 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_UART1_MPU register field. */
3365 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_RESET 0x0
3366 /* Extracts the ALT_NOC_FW_L4_PER_SCR_UART1_MPU field value from a register. */
3367 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_GET(value) (((value) & 0x00000001) >> 0)
3368 /* Produces a ALT_NOC_FW_L4_PER_SCR_UART1_MPU register field value suitable for setting the register. */
3369 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_SET(value) (((value) << 0) & 0x00000001)
3370 
3371 /*
3372  * Field : dma
3373  *
3374  * Security bit configuration for transactions from dma to uart1. When cleared (0),
3375  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
3376  * transactions are allowed.
3377  *
3378  * Field Access Macros:
3379  *
3380  */
3381 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_UART1_DMA register field. */
3382 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_LSB 8
3383 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_UART1_DMA register field. */
3384 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_MSB 8
3385 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_UART1_DMA register field. */
3386 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_WIDTH 1
3387 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_UART1_DMA register field value. */
3388 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_SET_MSK 0x00000100
3389 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_UART1_DMA register field value. */
3390 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_CLR_MSK 0xfffffeff
3391 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_UART1_DMA register field. */
3392 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_RESET 0x0
3393 /* Extracts the ALT_NOC_FW_L4_PER_SCR_UART1_DMA field value from a register. */
3394 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_GET(value) (((value) & 0x00000100) >> 8)
3395 /* Produces a ALT_NOC_FW_L4_PER_SCR_UART1_DMA register field value suitable for setting the register. */
3396 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_SET(value) (((value) << 8) & 0x00000100)
3397 
3398 /*
3399  * Field : fpga2soc
3400  *
3401  * Security bit configuration for transactions from fpga2soc to uart1. When cleared
3402  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3403  * Secure transactions are allowed.
3404  *
3405  * Field Access Macros:
3406  *
3407  */
3408 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC register field. */
3409 #define ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC_LSB 16
3410 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC register field. */
3411 #define ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC_MSB 16
3412 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC register field. */
3413 #define ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC_WIDTH 1
3414 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC register field value. */
3415 #define ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC_SET_MSK 0x00010000
3416 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC register field value. */
3417 #define ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC_CLR_MSK 0xfffeffff
3418 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC register field. */
3419 #define ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC_RESET 0x0
3420 /* Extracts the ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC field value from a register. */
3421 #define ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
3422 /* Produces a ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC register field value suitable for setting the register. */
3423 #define ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
3424 
3425 /*
3426  * Field : axi_ap
3427  *
3428  * Security bit configuration for transactions from axi_ap to uart1. When cleared
3429  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3430  * Secure transactions are allowed.
3431  *
3432  * Field Access Macros:
3433  *
3434  */
3435 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP register field. */
3436 #define ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP_LSB 24
3437 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP register field. */
3438 #define ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP_MSB 24
3439 /* The width in bits of the ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP register field. */
3440 #define ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP_WIDTH 1
3441 /* The mask used to set the ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP register field value. */
3442 #define ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP_SET_MSK 0x01000000
3443 /* The mask used to clear the ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP register field value. */
3444 #define ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP_CLR_MSK 0xfeffffff
3445 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP register field. */
3446 #define ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP_RESET 0x0
3447 /* Extracts the ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP field value from a register. */
3448 #define ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
3449 /* Produces a ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP register field value suitable for setting the register. */
3450 #define ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
3451 
3452 #ifndef __ASSEMBLY__
3453 /*
3454  * WARNING: The C register and register group struct declarations are provided for
3455  * convenience and illustrative purposes. They should, however, be used with
3456  * caution as the C language standard provides no guarantees about the alignment or
3457  * atomicity of device memory accesses. The recommended practice for coding device
3458  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3459  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3460  * alt_write_dword() functions for 64 bit registers.
3461  *
3462  * The struct declaration for register ALT_NOC_FW_L4_PER_SCR_UART1.
3463  */
3464 struct ALT_NOC_FW_L4_PER_SCR_UART1_s
3465 {
3466  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_PER_SCR_UART1_MPU */
3467  uint32_t : 7; /* *UNDEFINED* */
3468  volatile uint32_t dma : 1; /* ALT_NOC_FW_L4_PER_SCR_UART1_DMA */
3469  uint32_t : 7; /* *UNDEFINED* */
3470  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC */
3471  uint32_t : 7; /* *UNDEFINED* */
3472  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP */
3473  uint32_t : 7; /* *UNDEFINED* */
3474 };
3475 
3476 /* The typedef declaration for register ALT_NOC_FW_L4_PER_SCR_UART1. */
3477 typedef struct ALT_NOC_FW_L4_PER_SCR_UART1_s ALT_NOC_FW_L4_PER_SCR_UART1_t;
3478 #endif /* __ASSEMBLY__ */
3479 
3480 /* The reset value of the ALT_NOC_FW_L4_PER_SCR_UART1 register. */
3481 #define ALT_NOC_FW_L4_PER_SCR_UART1_RESET 0x00000000
3482 /* The byte offset of the ALT_NOC_FW_L4_PER_SCR_UART1 register from the beginning of the component. */
3483 #define ALT_NOC_FW_L4_PER_SCR_UART1_OFST 0x70
3484 
3485 #ifndef __ASSEMBLY__
3486 /*
3487  * WARNING: The C register and register group struct declarations are provided for
3488  * convenience and illustrative purposes. They should, however, be used with
3489  * caution as the C language standard provides no guarantees about the alignment or
3490  * atomicity of device memory accesses. The recommended practice for coding device
3491  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3492  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3493  * alt_write_dword() functions for 64 bit registers.
3494  *
3495  * The struct declaration for register group ALT_NOC_FW_L4_PER_SCR.
3496  */
3497 struct ALT_NOC_FW_L4_PER_SCR_s
3498 {
3499  volatile ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_t nand_register; /* ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER */
3500  volatile ALT_NOC_FW_L4_PER_SCR_NAND_DATA_t nand_data; /* ALT_NOC_FW_L4_PER_SCR_NAND_DATA */
3501  volatile uint32_t _pad_0x8_0xb; /* *UNDEFINED* */
3502  volatile ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_t usb0_register; /* ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER */
3503  volatile ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_t usb1_register; /* ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER */
3504  volatile uint32_t _pad_0x14_0x1b[2]; /* *UNDEFINED* */
3505  volatile ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_t spi_master0; /* ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0 */
3506  volatile ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_t spi_master1; /* ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1 */
3507  volatile ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_t spi_slave0; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0 */
3508  volatile ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_t spi_slave1; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1 */
3509  volatile ALT_NOC_FW_L4_PER_SCR_EMAC0_t emac0; /* ALT_NOC_FW_L4_PER_SCR_EMAC0 */
3510  volatile ALT_NOC_FW_L4_PER_SCR_EMAC1_t emac1; /* ALT_NOC_FW_L4_PER_SCR_EMAC1 */
3511  volatile ALT_NOC_FW_L4_PER_SCR_EMAC2_t emac2; /* ALT_NOC_FW_L4_PER_SCR_EMAC2 */
3512  volatile uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */
3513  volatile ALT_NOC_FW_L4_PER_SCR_SDMMC_t sdmmc; /* ALT_NOC_FW_L4_PER_SCR_SDMMC */
3514  volatile ALT_NOC_FW_L4_PER_SCR_GPIO0_t gpio0; /* ALT_NOC_FW_L4_PER_SCR_GPIO0 */
3515  volatile ALT_NOC_FW_L4_PER_SCR_GPIO1_t gpio1; /* ALT_NOC_FW_L4_PER_SCR_GPIO1 */
3516  volatile uint32_t _pad_0x4c_0x4f; /* *UNDEFINED* */
3517  volatile ALT_NOC_FW_L4_PER_SCR_I2C0_t i2c0; /* ALT_NOC_FW_L4_PER_SCR_I2C0 */
3518  volatile ALT_NOC_FW_L4_PER_SCR_I2C1_t i2c1; /* ALT_NOC_FW_L4_PER_SCR_I2C1 */
3519  volatile ALT_NOC_FW_L4_PER_SCR_I2C2_t i2c2; /* ALT_NOC_FW_L4_PER_SCR_I2C2 */
3520  volatile ALT_NOC_FW_L4_PER_SCR_I2C3_t i2c3; /* ALT_NOC_FW_L4_PER_SCR_I2C3 */
3521  volatile ALT_NOC_FW_L4_PER_SCR_I2C4_t i2c4; /* ALT_NOC_FW_L4_PER_SCR_I2C4 */
3522  volatile ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_t sp_timer0; /* ALT_NOC_FW_L4_PER_SCR_SP_TIMER0 */
3523  volatile ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_t sp_timer1; /* ALT_NOC_FW_L4_PER_SCR_SP_TIMER1 */
3524  volatile ALT_NOC_FW_L4_PER_SCR_UART0_t uart0; /* ALT_NOC_FW_L4_PER_SCR_UART0 */
3525  volatile ALT_NOC_FW_L4_PER_SCR_UART1_t uart1; /* ALT_NOC_FW_L4_PER_SCR_UART1 */
3526  volatile uint32_t _pad_0x74_0x100[35]; /* *UNDEFINED* */
3527 };
3528 
3529 /* The typedef declaration for register group ALT_NOC_FW_L4_PER_SCR. */
3530 typedef struct ALT_NOC_FW_L4_PER_SCR_s ALT_NOC_FW_L4_PER_SCR_t;
3531 /* The struct declaration for the raw register contents of register group ALT_NOC_FW_L4_PER_SCR. */
3532 struct ALT_NOC_FW_L4_PER_SCR_raw_s
3533 {
3534  volatile uint32_t nand_register; /* ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER */
3535  volatile uint32_t nand_data; /* ALT_NOC_FW_L4_PER_SCR_NAND_DATA */
3536  volatile uint32_t _pad_0x8_0xb; /* *UNDEFINED* */
3537  volatile uint32_t usb0_register; /* ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER */
3538  volatile uint32_t usb1_register; /* ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER */
3539  volatile uint32_t _pad_0x14_0x1b[2]; /* *UNDEFINED* */
3540  volatile uint32_t spi_master0; /* ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0 */
3541  volatile uint32_t spi_master1; /* ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1 */
3542  volatile uint32_t spi_slave0; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0 */
3543  volatile uint32_t spi_slave1; /* ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1 */
3544  volatile uint32_t emac0; /* ALT_NOC_FW_L4_PER_SCR_EMAC0 */
3545  volatile uint32_t emac1; /* ALT_NOC_FW_L4_PER_SCR_EMAC1 */
3546  volatile uint32_t emac2; /* ALT_NOC_FW_L4_PER_SCR_EMAC2 */
3547  volatile uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */
3548  volatile uint32_t sdmmc; /* ALT_NOC_FW_L4_PER_SCR_SDMMC */
3549  volatile uint32_t gpio0; /* ALT_NOC_FW_L4_PER_SCR_GPIO0 */
3550  volatile uint32_t gpio1; /* ALT_NOC_FW_L4_PER_SCR_GPIO1 */
3551  volatile uint32_t _pad_0x4c_0x4f; /* *UNDEFINED* */
3552  volatile uint32_t i2c0; /* ALT_NOC_FW_L4_PER_SCR_I2C0 */
3553  volatile uint32_t i2c1; /* ALT_NOC_FW_L4_PER_SCR_I2C1 */
3554  volatile uint32_t i2c2; /* ALT_NOC_FW_L4_PER_SCR_I2C2 */
3555  volatile uint32_t i2c3; /* ALT_NOC_FW_L4_PER_SCR_I2C3 */
3556  volatile uint32_t i2c4; /* ALT_NOC_FW_L4_PER_SCR_I2C4 */
3557  volatile uint32_t sp_timer0; /* ALT_NOC_FW_L4_PER_SCR_SP_TIMER0 */
3558  volatile uint32_t sp_timer1; /* ALT_NOC_FW_L4_PER_SCR_SP_TIMER1 */
3559  volatile uint32_t uart0; /* ALT_NOC_FW_L4_PER_SCR_UART0 */
3560  volatile uint32_t uart1; /* ALT_NOC_FW_L4_PER_SCR_UART1 */
3561  volatile uint32_t _pad_0x74_0x100[35]; /* *UNDEFINED* */
3562 };
3563 
3564 /* The typedef declaration for the raw register contents of register group ALT_NOC_FW_L4_PER_SCR. */
3565 typedef struct ALT_NOC_FW_L4_PER_SCR_raw_s ALT_NOC_FW_L4_PER_SCR_raw_t;
3566 #endif /* __ASSEMBLY__ */
3567 
3568 
3569 #ifdef __cplusplus
3570 }
3571 #endif /* __cplusplus */
3572 #endif /* __ALT_SOCAL_NOC_FW_L4_PER_SCR_H__ */
3573