Hardware Libraries  20.1
Arria 10 SoC Abstration Layer
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alt_qspi.h
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32 
33 /* Altera - ALT_QSPI */
34 
35 #ifndef __ALT_SOCAL_QSPI_H__
36 #define __ALT_SOCAL_QSPI_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_QSPI
50  *
51  */
52 /*
53  * Register : QSPI Configuration Register - cfg
54  *
55  * Register Layout
56  *
57  * Bits | Access | Reset | Description
58  * :--------|:-------|:------|:-------------------------------------------
59  * [0] | RW | 0x0 | QSPI Enable
60  * [1] | RW | 0x0 | Clock polarity outside SPI word
61  * [2] | RW | 0x0 | Select Clock Phase
62  * [6:3] | R | 0x0 | Reserved
63  * [7] | RW | 0x0 | Enable Direct Access Controller
64  * [8] | RW | 0x0 | Legacy IP Mode Enable
65  * [9] | RW | 0x0 | Peripheral select decode
66  * [13:10] | RW | 0x0 | Peripheral Chip Select Lines
67  * [14] | RW | 0x0 | Write Protect Flash Pin
68  * [15] | RW | 0x0 | Enable DMA Peripheral Interface
69  * [16] | RW | 0x0 | Enable AHB Address Re-mapping
70  * [17] | RW | 0x0 | Enter XIP Mode on next READ
71  * [18] | RW | 0x0 | Enter XIP Mode immediately
72  * [22:19] | RW | 0xf | Master Mode Baud Rate Divisor
73  * [30:23] | R | 0x0 | Reserved
74  * [31] | R | 0x1 | Serial interface and QSPI pipeline is IDLE
75  *
76  */
77 /*
78  * Field : QSPI Enable - en
79  *
80  * 0 : disable the QSPI once current transfer of the data word (FF_W) is complete.
81  * 1 : enable the QSPI When spi_enable = 0, all output enables are inactive and all
82  * pins are set to input mode.
83  *
84  * Field Enumeration Values:
85  *
86  * Enum | Value | Description
87  * :----------------------|:------|:-----------------
88  * ALT_QSPI_CFG_EN_E_DIS | 0x0 | Disable the QSPI
89  * ALT_QSPI_CFG_EN_E_EN | 0x1 | Enable the QSPI
90  *
91  * Field Access Macros:
92  *
93  */
94 /*
95  * Enumerated value for register field ALT_QSPI_CFG_EN
96  *
97  * Disable the QSPI
98  */
99 #define ALT_QSPI_CFG_EN_E_DIS 0x0
100 /*
101  * Enumerated value for register field ALT_QSPI_CFG_EN
102  *
103  * Enable the QSPI
104  */
105 #define ALT_QSPI_CFG_EN_E_EN 0x1
106 
107 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_EN register field. */
108 #define ALT_QSPI_CFG_EN_LSB 0
109 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_EN register field. */
110 #define ALT_QSPI_CFG_EN_MSB 0
111 /* The width in bits of the ALT_QSPI_CFG_EN register field. */
112 #define ALT_QSPI_CFG_EN_WIDTH 1
113 /* The mask used to set the ALT_QSPI_CFG_EN register field value. */
114 #define ALT_QSPI_CFG_EN_SET_MSK 0x00000001
115 /* The mask used to clear the ALT_QSPI_CFG_EN register field value. */
116 #define ALT_QSPI_CFG_EN_CLR_MSK 0xfffffffe
117 /* The reset value of the ALT_QSPI_CFG_EN register field. */
118 #define ALT_QSPI_CFG_EN_RESET 0x0
119 /* Extracts the ALT_QSPI_CFG_EN field value from a register. */
120 #define ALT_QSPI_CFG_EN_GET(value) (((value) & 0x00000001) >> 0)
121 /* Produces a ALT_QSPI_CFG_EN register field value suitable for setting the register. */
122 #define ALT_QSPI_CFG_EN_SET(value) (((value) << 0) & 0x00000001)
123 
124 /*
125  * Field : Clock polarity outside SPI word - selclkpol
126  *
127  * 0 : the SPI clock is quiescent low 1 : the SPI clock is quiescent high
128  *
129  * Field Enumeration Values:
130  *
131  * Enum | Value | Description
132  * :------------------------------|:------|:----------------------------
133  * ALT_QSPI_CFG_SELCLKPOL_E_HIGH | 0x0 | SPI clock is quiescent high
134  * ALT_QSPI_CFG_SELCLKPOL_E_LOW | 0x1 | SPI clock is quiescent low
135  *
136  * Field Access Macros:
137  *
138  */
139 /*
140  * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL
141  *
142  * SPI clock is quiescent high
143  */
144 #define ALT_QSPI_CFG_SELCLKPOL_E_HIGH 0x0
145 /*
146  * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL
147  *
148  * SPI clock is quiescent low
149  */
150 #define ALT_QSPI_CFG_SELCLKPOL_E_LOW 0x1
151 
152 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */
153 #define ALT_QSPI_CFG_SELCLKPOL_LSB 1
154 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */
155 #define ALT_QSPI_CFG_SELCLKPOL_MSB 1
156 /* The width in bits of the ALT_QSPI_CFG_SELCLKPOL register field. */
157 #define ALT_QSPI_CFG_SELCLKPOL_WIDTH 1
158 /* The mask used to set the ALT_QSPI_CFG_SELCLKPOL register field value. */
159 #define ALT_QSPI_CFG_SELCLKPOL_SET_MSK 0x00000002
160 /* The mask used to clear the ALT_QSPI_CFG_SELCLKPOL register field value. */
161 #define ALT_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd
162 /* The reset value of the ALT_QSPI_CFG_SELCLKPOL register field. */
163 #define ALT_QSPI_CFG_SELCLKPOL_RESET 0x0
164 /* Extracts the ALT_QSPI_CFG_SELCLKPOL field value from a register. */
165 #define ALT_QSPI_CFG_SELCLKPOL_GET(value) (((value) & 0x00000002) >> 1)
166 /* Produces a ALT_QSPI_CFG_SELCLKPOL register field value suitable for setting the register. */
167 #define ALT_QSPI_CFG_SELCLKPOL_SET(value) (((value) << 1) & 0x00000002)
168 
169 /*
170  * Field : Select Clock Phase - selclkphase
171  *
172  * Selects whether the clock is in an active or inactive phase outside the SPI
173  * word. 0 : the SPI clock is active outside the word 1 : the SPI clock is inactive
174  * outside the word
175  *
176  * Field Enumeration Values:
177  *
178  * Enum | Value | Description
179  * :---------------------------------|:------|:---------------------------
180  * ALT_QSPI_CFG_SELCLKPHASE_E_ACT | 0x0 | SPI clock is quiescent low
181  * ALT_QSPI_CFG_SELCLKPHASE_E_INACT | 0x1 | Clock Inactive
182  *
183  * Field Access Macros:
184  *
185  */
186 /*
187  * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE
188  *
189  * SPI clock is quiescent low
190  */
191 #define ALT_QSPI_CFG_SELCLKPHASE_E_ACT 0x0
192 /*
193  * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE
194  *
195  * Clock Inactive
196  */
197 #define ALT_QSPI_CFG_SELCLKPHASE_E_INACT 0x1
198 
199 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */
200 #define ALT_QSPI_CFG_SELCLKPHASE_LSB 2
201 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */
202 #define ALT_QSPI_CFG_SELCLKPHASE_MSB 2
203 /* The width in bits of the ALT_QSPI_CFG_SELCLKPHASE register field. */
204 #define ALT_QSPI_CFG_SELCLKPHASE_WIDTH 1
205 /* The mask used to set the ALT_QSPI_CFG_SELCLKPHASE register field value. */
206 #define ALT_QSPI_CFG_SELCLKPHASE_SET_MSK 0x00000004
207 /* The mask used to clear the ALT_QSPI_CFG_SELCLKPHASE register field value. */
208 #define ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb
209 /* The reset value of the ALT_QSPI_CFG_SELCLKPHASE register field. */
210 #define ALT_QSPI_CFG_SELCLKPHASE_RESET 0x0
211 /* Extracts the ALT_QSPI_CFG_SELCLKPHASE field value from a register. */
212 #define ALT_QSPI_CFG_SELCLKPHASE_GET(value) (((value) & 0x00000004) >> 2)
213 /* Produces a ALT_QSPI_CFG_SELCLKPHASE register field value suitable for setting the register. */
214 #define ALT_QSPI_CFG_SELCLKPHASE_SET(value) (((value) << 2) & 0x00000004)
215 
216 /*
217  * Field : Reserved - config_resv1_fld
218  *
219  * Field Access Macros:
220  *
221  */
222 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_CFG_RESV1_FLD register field. */
223 #define ALT_QSPI_CFG_CFG_RESV1_FLD_LSB 3
224 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_CFG_RESV1_FLD register field. */
225 #define ALT_QSPI_CFG_CFG_RESV1_FLD_MSB 6
226 /* The width in bits of the ALT_QSPI_CFG_CFG_RESV1_FLD register field. */
227 #define ALT_QSPI_CFG_CFG_RESV1_FLD_WIDTH 4
228 /* The mask used to set the ALT_QSPI_CFG_CFG_RESV1_FLD register field value. */
229 #define ALT_QSPI_CFG_CFG_RESV1_FLD_SET_MSK 0x00000078
230 /* The mask used to clear the ALT_QSPI_CFG_CFG_RESV1_FLD register field value. */
231 #define ALT_QSPI_CFG_CFG_RESV1_FLD_CLR_MSK 0xffffff87
232 /* The reset value of the ALT_QSPI_CFG_CFG_RESV1_FLD register field. */
233 #define ALT_QSPI_CFG_CFG_RESV1_FLD_RESET 0x0
234 /* Extracts the ALT_QSPI_CFG_CFG_RESV1_FLD field value from a register. */
235 #define ALT_QSPI_CFG_CFG_RESV1_FLD_GET(value) (((value) & 0x00000078) >> 3)
236 /* Produces a ALT_QSPI_CFG_CFG_RESV1_FLD register field value suitable for setting the register. */
237 #define ALT_QSPI_CFG_CFG_RESV1_FLD_SET(value) (((value) << 3) & 0x00000078)
238 
239 /*
240  * Field : Enable Direct Access Controller - endiracc
241  *
242  * 0 : disable the Direct Access Controller once current transfer of the data word
243  * (FF_W) is complete. 1 : enable the Direct Access Controller When the Direct
244  * Access Controller and Indirect Access Controller are both disabled, all AHB
245  * requested are completed with an error response.
246  *
247  * Field Enumeration Values:
248  *
249  * Enum | Value | Description
250  * :----------------------------|:------|:---------------------------
251  * ALT_QSPI_CFG_ENDIRACC_E_DIS | 0x0 | Disable Direct Access Ctrl
252  * ALT_QSPI_CFG_ENDIRACC_E_EN | 0x1 | Enable Direct Access Ctrl
253  *
254  * Field Access Macros:
255  *
256  */
257 /*
258  * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC
259  *
260  * Disable Direct Access Ctrl
261  */
262 #define ALT_QSPI_CFG_ENDIRACC_E_DIS 0x0
263 /*
264  * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC
265  *
266  * Enable Direct Access Ctrl
267  */
268 #define ALT_QSPI_CFG_ENDIRACC_E_EN 0x1
269 
270 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */
271 #define ALT_QSPI_CFG_ENDIRACC_LSB 7
272 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */
273 #define ALT_QSPI_CFG_ENDIRACC_MSB 7
274 /* The width in bits of the ALT_QSPI_CFG_ENDIRACC register field. */
275 #define ALT_QSPI_CFG_ENDIRACC_WIDTH 1
276 /* The mask used to set the ALT_QSPI_CFG_ENDIRACC register field value. */
277 #define ALT_QSPI_CFG_ENDIRACC_SET_MSK 0x00000080
278 /* The mask used to clear the ALT_QSPI_CFG_ENDIRACC register field value. */
279 #define ALT_QSPI_CFG_ENDIRACC_CLR_MSK 0xffffff7f
280 /* The reset value of the ALT_QSPI_CFG_ENDIRACC register field. */
281 #define ALT_QSPI_CFG_ENDIRACC_RESET 0x0
282 /* Extracts the ALT_QSPI_CFG_ENDIRACC field value from a register. */
283 #define ALT_QSPI_CFG_ENDIRACC_GET(value) (((value) & 0x00000080) >> 7)
284 /* Produces a ALT_QSPI_CFG_ENDIRACC register field value suitable for setting the register. */
285 #define ALT_QSPI_CFG_ENDIRACC_SET(value) (((value) << 7) & 0x00000080)
286 
287 /*
288  * Field : Legacy IP Mode Enable - enlegacyip
289  *
290  * 0 : Use Direct Access Controller/Indirect Access Controller 1 : legacy Mode is
291  * enabled. In this mode, any write to the controller via the AHB interface is
292  * serialized and sent to the FLASH device. Any valid AHB read will pop the
293  * internal RX-FIFO, retrieving data that was forwarded by the external FLASH
294  * device on the SPI lines,4,2 or 1 byte transfers are permitted and controlled via
295  * the HSIZE input.
296  *
297  * Field Enumeration Values:
298  *
299  * Enum | Value | Description
300  * :---------------------------------|:------|:--------------------------------------
301  * ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD | 0x0 | Use Direct/Indirect Access Controller
302  * ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD | 0x1 | Legacy Mode
303  *
304  * Field Access Macros:
305  *
306  */
307 /*
308  * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP
309  *
310  * Use Direct/Indirect Access Controller
311  */
312 #define ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD 0x0
313 /*
314  * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP
315  *
316  * Legacy Mode
317  */
318 #define ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD 0x1
319 
320 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */
321 #define ALT_QSPI_CFG_ENLEGACYIP_LSB 8
322 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */
323 #define ALT_QSPI_CFG_ENLEGACYIP_MSB 8
324 /* The width in bits of the ALT_QSPI_CFG_ENLEGACYIP register field. */
325 #define ALT_QSPI_CFG_ENLEGACYIP_WIDTH 1
326 /* The mask used to set the ALT_QSPI_CFG_ENLEGACYIP register field value. */
327 #define ALT_QSPI_CFG_ENLEGACYIP_SET_MSK 0x00000100
328 /* The mask used to clear the ALT_QSPI_CFG_ENLEGACYIP register field value. */
329 #define ALT_QSPI_CFG_ENLEGACYIP_CLR_MSK 0xfffffeff
330 /* The reset value of the ALT_QSPI_CFG_ENLEGACYIP register field. */
331 #define ALT_QSPI_CFG_ENLEGACYIP_RESET 0x0
332 /* Extracts the ALT_QSPI_CFG_ENLEGACYIP field value from a register. */
333 #define ALT_QSPI_CFG_ENLEGACYIP_GET(value) (((value) & 0x00000100) >> 8)
334 /* Produces a ALT_QSPI_CFG_ENLEGACYIP register field value suitable for setting the register. */
335 #define ALT_QSPI_CFG_ENLEGACYIP_SET(value) (((value) << 8) & 0x00000100)
336 
337 /*
338  * Field : Peripheral select decode - perseldec
339  *
340  * 0 : only 1 of 4 selects n_ss_out[3:0] is active 1 : allow external 4-to-16
341  * decode (n_ss_out = ss)
342  *
343  * Field Enumeration Values:
344  *
345  * Enum | Value | Description
346  * :----------------------------------|:------|:----------------------------------
347  * ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 | 0x0 | Selects 1 of 4 qspi_n_ss_out[3:0]
348  * ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 | 0x1 | Select external 4-to-16 decode
349  *
350  * Field Access Macros:
351  *
352  */
353 /*
354  * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC
355  *
356  * Selects 1 of 4 qspi_n_ss_out[3:0]
357  */
358 #define ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 0x0
359 /*
360  * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC
361  *
362  * Select external 4-to-16 decode
363  */
364 #define ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 0x1
365 
366 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */
367 #define ALT_QSPI_CFG_PERSELDEC_LSB 9
368 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */
369 #define ALT_QSPI_CFG_PERSELDEC_MSB 9
370 /* The width in bits of the ALT_QSPI_CFG_PERSELDEC register field. */
371 #define ALT_QSPI_CFG_PERSELDEC_WIDTH 1
372 /* The mask used to set the ALT_QSPI_CFG_PERSELDEC register field value. */
373 #define ALT_QSPI_CFG_PERSELDEC_SET_MSK 0x00000200
374 /* The mask used to clear the ALT_QSPI_CFG_PERSELDEC register field value. */
375 #define ALT_QSPI_CFG_PERSELDEC_CLR_MSK 0xfffffdff
376 /* The reset value of the ALT_QSPI_CFG_PERSELDEC register field. */
377 #define ALT_QSPI_CFG_PERSELDEC_RESET 0x0
378 /* Extracts the ALT_QSPI_CFG_PERSELDEC field value from a register. */
379 #define ALT_QSPI_CFG_PERSELDEC_GET(value) (((value) & 0x00000200) >> 9)
380 /* Produces a ALT_QSPI_CFG_PERSELDEC register field value suitable for setting the register. */
381 #define ALT_QSPI_CFG_PERSELDEC_SET(value) (((value) << 9) & 0x00000200)
382 
383 /*
384  * Field : Peripheral Chip Select Lines - percslines
385  *
386  * Peripheral chip select lines If pdec = 0, ss[3:0] are output thus: ss[3:0]
387  * n_ss_out[3:0] xxx0 1110 xx01 1101 x011 1011 0111 0111 1111 1111 (no peripheral
388  * selected) else ss[3:0] directly drives n_ss_out[3:0]
389  *
390  * Field Access Macros:
391  *
392  */
393 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */
394 #define ALT_QSPI_CFG_PERCSLINES_LSB 10
395 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */
396 #define ALT_QSPI_CFG_PERCSLINES_MSB 13
397 /* The width in bits of the ALT_QSPI_CFG_PERCSLINES register field. */
398 #define ALT_QSPI_CFG_PERCSLINES_WIDTH 4
399 /* The mask used to set the ALT_QSPI_CFG_PERCSLINES register field value. */
400 #define ALT_QSPI_CFG_PERCSLINES_SET_MSK 0x00003c00
401 /* The mask used to clear the ALT_QSPI_CFG_PERCSLINES register field value. */
402 #define ALT_QSPI_CFG_PERCSLINES_CLR_MSK 0xffffc3ff
403 /* The reset value of the ALT_QSPI_CFG_PERCSLINES register field. */
404 #define ALT_QSPI_CFG_PERCSLINES_RESET 0x0
405 /* Extracts the ALT_QSPI_CFG_PERCSLINES field value from a register. */
406 #define ALT_QSPI_CFG_PERCSLINES_GET(value) (((value) & 0x00003c00) >> 10)
407 /* Produces a ALT_QSPI_CFG_PERCSLINES register field value suitable for setting the register. */
408 #define ALT_QSPI_CFG_PERCSLINES_SET(value) (((value) << 10) & 0x00003c00)
409 
410 /*
411  * Field : Write Protect Flash Pin - wp
412  *
413  * Set to drive the Write Protect pin of the FLASH device. This is resynchronized
414  * to the generated memory clock as necessary.
415  *
416  * Field Enumeration Values:
417  *
418  * Enum | Value | Description
419  * :-----------------------------|:------|:----------------------
420  * ALT_QSPI_CFG_WP_E_WRTPROTOFF | 0x0 | Disable Write Protect
421  * ALT_QSPI_CFG_WP_E_WRPROTON | 0x1 | Enable Write Protect
422  *
423  * Field Access Macros:
424  *
425  */
426 /*
427  * Enumerated value for register field ALT_QSPI_CFG_WP
428  *
429  * Disable Write Protect
430  */
431 #define ALT_QSPI_CFG_WP_E_WRTPROTOFF 0x0
432 /*
433  * Enumerated value for register field ALT_QSPI_CFG_WP
434  *
435  * Enable Write Protect
436  */
437 #define ALT_QSPI_CFG_WP_E_WRPROTON 0x1
438 
439 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_WP register field. */
440 #define ALT_QSPI_CFG_WP_LSB 14
441 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_WP register field. */
442 #define ALT_QSPI_CFG_WP_MSB 14
443 /* The width in bits of the ALT_QSPI_CFG_WP register field. */
444 #define ALT_QSPI_CFG_WP_WIDTH 1
445 /* The mask used to set the ALT_QSPI_CFG_WP register field value. */
446 #define ALT_QSPI_CFG_WP_SET_MSK 0x00004000
447 /* The mask used to clear the ALT_QSPI_CFG_WP register field value. */
448 #define ALT_QSPI_CFG_WP_CLR_MSK 0xffffbfff
449 /* The reset value of the ALT_QSPI_CFG_WP register field. */
450 #define ALT_QSPI_CFG_WP_RESET 0x0
451 /* Extracts the ALT_QSPI_CFG_WP field value from a register. */
452 #define ALT_QSPI_CFG_WP_GET(value) (((value) & 0x00004000) >> 14)
453 /* Produces a ALT_QSPI_CFG_WP register field value suitable for setting the register. */
454 #define ALT_QSPI_CFG_WP_SET(value) (((value) << 14) & 0x00004000)
455 
456 /*
457  * Field : Enable DMA Peripheral Interface - endma
458  *
459  * Set to 1 to enable the DMA handshaking logic. When enabled the QSPI will trigger
460  * DMA transfer requests via the DMA peripheral interface. Set to 0 to disable
461  *
462  * Field Enumeration Values:
463  *
464  * Enum | Value | Description
465  * :-------------------------|:------|:-----------------
466  * ALT_QSPI_CFG_ENDMA_E_DIS | 0x0 | Disable DMA Mode
467  * ALT_QSPI_CFG_ENDMA_E_EN | 0x1 | Enable DMA Mode
468  *
469  * Field Access Macros:
470  *
471  */
472 /*
473  * Enumerated value for register field ALT_QSPI_CFG_ENDMA
474  *
475  * Disable DMA Mode
476  */
477 #define ALT_QSPI_CFG_ENDMA_E_DIS 0x0
478 /*
479  * Enumerated value for register field ALT_QSPI_CFG_ENDMA
480  *
481  * Enable DMA Mode
482  */
483 #define ALT_QSPI_CFG_ENDMA_E_EN 0x1
484 
485 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDMA register field. */
486 #define ALT_QSPI_CFG_ENDMA_LSB 15
487 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDMA register field. */
488 #define ALT_QSPI_CFG_ENDMA_MSB 15
489 /* The width in bits of the ALT_QSPI_CFG_ENDMA register field. */
490 #define ALT_QSPI_CFG_ENDMA_WIDTH 1
491 /* The mask used to set the ALT_QSPI_CFG_ENDMA register field value. */
492 #define ALT_QSPI_CFG_ENDMA_SET_MSK 0x00008000
493 /* The mask used to clear the ALT_QSPI_CFG_ENDMA register field value. */
494 #define ALT_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff
495 /* The reset value of the ALT_QSPI_CFG_ENDMA register field. */
496 #define ALT_QSPI_CFG_ENDMA_RESET 0x0
497 /* Extracts the ALT_QSPI_CFG_ENDMA field value from a register. */
498 #define ALT_QSPI_CFG_ENDMA_GET(value) (((value) & 0x00008000) >> 15)
499 /* Produces a ALT_QSPI_CFG_ENDMA register field value suitable for setting the register. */
500 #define ALT_QSPI_CFG_ENDMA_SET(value) (((value) << 15) & 0x00008000)
501 
502 /*
503  * Field : Enable AHB Address Re-mapping - enahbremap
504  *
505  * (Direct Access Mode Only) When set to 1, the incoming AHB address will be
506  * adapted and sent to the FLASH device as (address + N), where N is the value
507  * stored in the remap address register.
508  *
509  * Field Enumeration Values:
510  *
511  * Enum | Value | Description
512  * :------------------------------|:------|:-----------------------
513  * ALT_QSPI_CFG_ENAHBREMAP_E_DIS | 0x0 | Disable AHB Re-mapping
514  * ALT_QSPI_CFG_ENAHBREMAP_E_EN | 0x1 | Enable AHB Re-mapping
515  *
516  * Field Access Macros:
517  *
518  */
519 /*
520  * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP
521  *
522  * Disable AHB Re-mapping
523  */
524 #define ALT_QSPI_CFG_ENAHBREMAP_E_DIS 0x0
525 /*
526  * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP
527  *
528  * Enable AHB Re-mapping
529  */
530 #define ALT_QSPI_CFG_ENAHBREMAP_E_EN 0x1
531 
532 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */
533 #define ALT_QSPI_CFG_ENAHBREMAP_LSB 16
534 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */
535 #define ALT_QSPI_CFG_ENAHBREMAP_MSB 16
536 /* The width in bits of the ALT_QSPI_CFG_ENAHBREMAP register field. */
537 #define ALT_QSPI_CFG_ENAHBREMAP_WIDTH 1
538 /* The mask used to set the ALT_QSPI_CFG_ENAHBREMAP register field value. */
539 #define ALT_QSPI_CFG_ENAHBREMAP_SET_MSK 0x00010000
540 /* The mask used to clear the ALT_QSPI_CFG_ENAHBREMAP register field value. */
541 #define ALT_QSPI_CFG_ENAHBREMAP_CLR_MSK 0xfffeffff
542 /* The reset value of the ALT_QSPI_CFG_ENAHBREMAP register field. */
543 #define ALT_QSPI_CFG_ENAHBREMAP_RESET 0x0
544 /* Extracts the ALT_QSPI_CFG_ENAHBREMAP field value from a register. */
545 #define ALT_QSPI_CFG_ENAHBREMAP_GET(value) (((value) & 0x00010000) >> 16)
546 /* Produces a ALT_QSPI_CFG_ENAHBREMAP register field value suitable for setting the register. */
547 #define ALT_QSPI_CFG_ENAHBREMAP_SET(value) (((value) << 16) & 0x00010000)
548 
549 /*
550  * Field : Enter XIP Mode on next READ - enterxipnextrd
551  *
552  * Value=0 : If XIP is enabled, then setting to 0 will cause the controller to exit
553  * XIP mode on the next READ instruction. Value=1 : If XIP is disabled, then
554  * setting to ?1? will inform the controller that the device is ready to enter XIP
555  * on the next READ instruction. The controller will therefore send the appropriate
556  * command sequence, including mode bits to cause the device to enter XIP mode. Use
557  * this register after the controller has ensured the FLASH device has been
558  * configured to be ready to enter XIP mode. Note : To exit XIP mode, this bit
559  * should be set to 0. This will take effect in the attached device only AFTER the
560  * next READ instruction is executed. Software should therefore ensure that at
561  * least one READ instruction is requested after resetting this bit before it can
562  * be sure XIP mode in the device is exited.
563  *
564  * Field Enumeration Values:
565  *
566  * Enum | Value | Description
567  * :----------------------------------|:------|:----------------------------------------
568  * ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS | 0x0 | Exit XIP Mode on next READ instruction
569  * ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN | 0x1 | Enter XIP Mode on next READ instruction
570  *
571  * Field Access Macros:
572  *
573  */
574 /*
575  * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD
576  *
577  * Exit XIP Mode on next READ instruction
578  */
579 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS 0x0
580 /*
581  * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD
582  *
583  * Enter XIP Mode on next READ instruction
584  */
585 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN 0x1
586 
587 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */
588 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_LSB 17
589 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */
590 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_MSB 17
591 /* The width in bits of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */
592 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_WIDTH 1
593 /* The mask used to set the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */
594 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET_MSK 0x00020000
595 /* The mask used to clear the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */
596 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_CLR_MSK 0xfffdffff
597 /* The reset value of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */
598 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_RESET 0x0
599 /* Extracts the ALT_QSPI_CFG_ENTERXIPNEXTRD field value from a register. */
600 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_GET(value) (((value) & 0x00020000) >> 17)
601 /* Produces a ALT_QSPI_CFG_ENTERXIPNEXTRD register field value suitable for setting the register. */
602 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET(value) (((value) << 17) & 0x00020000)
603 
604 /*
605  * Field : Enter XIP Mode immediately - enterxipimm
606  *
607  * Value=0 : If XIP is enabled, then setting to 0 will cause the controller to exit
608  * XIP mode on the next READ instruction. Value=1 : Operate the device in XIP mode
609  * immediately Use this register when the external device wakes up in XIP mode (as
610  * per the contents of its non- volatile configuration register). The controller
611  * will assume the next READ instruction will be passed to the device as an XIP
612  * instruction, and therefore will not require the READ opcode to be transferred.
613  * Note: To exit XIP mode, this bit should be set to 0. This will take effect in
614  * the attached device only after the next READ instruction is executed. Software
615  * therefore should ensure that at least one READ instruction is requested after
616  * resetting this bit in order to be sure that XIP mode is exited.
617  *
618  * Field Enumeration Values:
619  *
620  * Enum | Value | Description
621  * :-------------------------------|:------|:---------------------------------------
622  * ALT_QSPI_CFG_ENTERXIPIMM_E_DIS | 0x0 | Exit XIP Mode on next READ instruction
623  * ALT_QSPI_CFG_ENTERXIPIMM_E_EN | 0x1 | Enter XIP Mode immediately
624  *
625  * Field Access Macros:
626  *
627  */
628 /*
629  * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM
630  *
631  * Exit XIP Mode on next READ instruction
632  */
633 #define ALT_QSPI_CFG_ENTERXIPIMM_E_DIS 0x0
634 /*
635  * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM
636  *
637  * Enter XIP Mode immediately
638  */
639 #define ALT_QSPI_CFG_ENTERXIPIMM_E_EN 0x1
640 
641 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */
642 #define ALT_QSPI_CFG_ENTERXIPIMM_LSB 18
643 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */
644 #define ALT_QSPI_CFG_ENTERXIPIMM_MSB 18
645 /* The width in bits of the ALT_QSPI_CFG_ENTERXIPIMM register field. */
646 #define ALT_QSPI_CFG_ENTERXIPIMM_WIDTH 1
647 /* The mask used to set the ALT_QSPI_CFG_ENTERXIPIMM register field value. */
648 #define ALT_QSPI_CFG_ENTERXIPIMM_SET_MSK 0x00040000
649 /* The mask used to clear the ALT_QSPI_CFG_ENTERXIPIMM register field value. */
650 #define ALT_QSPI_CFG_ENTERXIPIMM_CLR_MSK 0xfffbffff
651 /* The reset value of the ALT_QSPI_CFG_ENTERXIPIMM register field. */
652 #define ALT_QSPI_CFG_ENTERXIPIMM_RESET 0x0
653 /* Extracts the ALT_QSPI_CFG_ENTERXIPIMM field value from a register. */
654 #define ALT_QSPI_CFG_ENTERXIPIMM_GET(value) (((value) & 0x00040000) >> 18)
655 /* Produces a ALT_QSPI_CFG_ENTERXIPIMM register field value suitable for setting the register. */
656 #define ALT_QSPI_CFG_ENTERXIPIMM_SET(value) (((value) << 18) & 0x00040000)
657 
658 /*
659  * Field : Master Mode Baud Rate Divisor - bauddiv
660  *
661  * SPI baud rae = (master reference clock) baud_rate_divisor
662  *
663  * Field Enumeration Values:
664  *
665  * Enum | Value | Description
666  * :------------------------------|:------|:-----------------
667  * ALT_QSPI_CFG_BAUDDIV_E_BAUD2 | 0x0 | Baud Rate Div/2
668  * ALT_QSPI_CFG_BAUDDIV_E_BAUD4 | 0x1 | Baud Rate Div/4
669  * ALT_QSPI_CFG_BAUDDIV_E_BAUD6 | 0x2 | Baud Rate Div/6
670  * ALT_QSPI_CFG_BAUDDIV_E_BAUD8 | 0x3 | Baud Rate Div/8
671  * ALT_QSPI_CFG_BAUDDIV_E_BAUD10 | 0x4 | Baud Rate Div/10
672  * ALT_QSPI_CFG_BAUDDIV_E_BAUD12 | 0x5 | Baud Rate Div/12
673  * ALT_QSPI_CFG_BAUDDIV_E_BAUD14 | 0x6 | Baud Rate Div/14
674  * ALT_QSPI_CFG_BAUDDIV_E_BAUD16 | 0x7 | Baud Rate Div/16
675  * ALT_QSPI_CFG_BAUDDIV_E_BAUD18 | 0x8 | Baud Rate Div/18
676  * ALT_QSPI_CFG_BAUDDIV_E_BAUD20 | 0x9 | Baud Rate Div/20
677  * ALT_QSPI_CFG_BAUDDIV_E_BAUD22 | 0xa | Baud Rate Div/22
678  * ALT_QSPI_CFG_BAUDDIV_E_BAUD24 | 0xb | Baud Rate Div/24
679  * ALT_QSPI_CFG_BAUDDIV_E_BAUD26 | 0xc | Baud Rate Div/26
680  * ALT_QSPI_CFG_BAUDDIV_E_BAUD28 | 0xd | Baud Rate Div/28
681  * ALT_QSPI_CFG_BAUDDIV_E_BAUD30 | 0xe | Baud Rate Div/30
682  * ALT_QSPI_CFG_BAUDDIV_E_BAUD32 | 0xf | Baud Rate Div/32
683  *
684  * Field Access Macros:
685  *
686  */
687 /*
688  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
689  *
690  * Baud Rate Div/2
691  */
692 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD2 0x0
693 /*
694  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
695  *
696  * Baud Rate Div/4
697  */
698 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD4 0x1
699 /*
700  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
701  *
702  * Baud Rate Div/6
703  */
704 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD6 0x2
705 /*
706  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
707  *
708  * Baud Rate Div/8
709  */
710 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD8 0x3
711 /*
712  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
713  *
714  * Baud Rate Div/10
715  */
716 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD10 0x4
717 /*
718  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
719  *
720  * Baud Rate Div/12
721  */
722 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD12 0x5
723 /*
724  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
725  *
726  * Baud Rate Div/14
727  */
728 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD14 0x6
729 /*
730  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
731  *
732  * Baud Rate Div/16
733  */
734 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD16 0x7
735 /*
736  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
737  *
738  * Baud Rate Div/18
739  */
740 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD18 0x8
741 /*
742  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
743  *
744  * Baud Rate Div/20
745  */
746 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD20 0x9
747 /*
748  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
749  *
750  * Baud Rate Div/22
751  */
752 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD22 0xa
753 /*
754  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
755  *
756  * Baud Rate Div/24
757  */
758 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD24 0xb
759 /*
760  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
761  *
762  * Baud Rate Div/26
763  */
764 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD26 0xc
765 /*
766  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
767  *
768  * Baud Rate Div/28
769  */
770 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD28 0xd
771 /*
772  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
773  *
774  * Baud Rate Div/30
775  */
776 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD30 0xe
777 /*
778  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
779  *
780  * Baud Rate Div/32
781  */
782 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD32 0xf
783 
784 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */
785 #define ALT_QSPI_CFG_BAUDDIV_LSB 19
786 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */
787 #define ALT_QSPI_CFG_BAUDDIV_MSB 22
788 /* The width in bits of the ALT_QSPI_CFG_BAUDDIV register field. */
789 #define ALT_QSPI_CFG_BAUDDIV_WIDTH 4
790 /* The mask used to set the ALT_QSPI_CFG_BAUDDIV register field value. */
791 #define ALT_QSPI_CFG_BAUDDIV_SET_MSK 0x00780000
792 /* The mask used to clear the ALT_QSPI_CFG_BAUDDIV register field value. */
793 #define ALT_QSPI_CFG_BAUDDIV_CLR_MSK 0xff87ffff
794 /* The reset value of the ALT_QSPI_CFG_BAUDDIV register field. */
795 #define ALT_QSPI_CFG_BAUDDIV_RESET 0xf
796 /* Extracts the ALT_QSPI_CFG_BAUDDIV field value from a register. */
797 #define ALT_QSPI_CFG_BAUDDIV_GET(value) (((value) & 0x00780000) >> 19)
798 /* Produces a ALT_QSPI_CFG_BAUDDIV register field value suitable for setting the register. */
799 #define ALT_QSPI_CFG_BAUDDIV_SET(value) (((value) << 19) & 0x00780000)
800 
801 /*
802  * Field : Reserved - config_resv2_fld
803  *
804  * Field Access Macros:
805  *
806  */
807 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_CFG_RESV2_FLD register field. */
808 #define ALT_QSPI_CFG_CFG_RESV2_FLD_LSB 23
809 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_CFG_RESV2_FLD register field. */
810 #define ALT_QSPI_CFG_CFG_RESV2_FLD_MSB 30
811 /* The width in bits of the ALT_QSPI_CFG_CFG_RESV2_FLD register field. */
812 #define ALT_QSPI_CFG_CFG_RESV2_FLD_WIDTH 8
813 /* The mask used to set the ALT_QSPI_CFG_CFG_RESV2_FLD register field value. */
814 #define ALT_QSPI_CFG_CFG_RESV2_FLD_SET_MSK 0x7f800000
815 /* The mask used to clear the ALT_QSPI_CFG_CFG_RESV2_FLD register field value. */
816 #define ALT_QSPI_CFG_CFG_RESV2_FLD_CLR_MSK 0x807fffff
817 /* The reset value of the ALT_QSPI_CFG_CFG_RESV2_FLD register field. */
818 #define ALT_QSPI_CFG_CFG_RESV2_FLD_RESET 0x0
819 /* Extracts the ALT_QSPI_CFG_CFG_RESV2_FLD field value from a register. */
820 #define ALT_QSPI_CFG_CFG_RESV2_FLD_GET(value) (((value) & 0x7f800000) >> 23)
821 /* Produces a ALT_QSPI_CFG_CFG_RESV2_FLD register field value suitable for setting the register. */
822 #define ALT_QSPI_CFG_CFG_RESV2_FLD_SET(value) (((value) << 23) & 0x7f800000)
823 
824 /*
825  * Field : Serial interface and QSPI pipeline is IDLE - idle
826  *
827  * This is a STATUS read-only bit. Note this is a retimed signal, so there will be
828  * some inherent delay on the generation of this status signal.
829  *
830  * Field Enumeration Values:
831  *
832  * Enum | Value | Description
833  * :---------------------------|:------|:--------------
834  * ALT_QSPI_CFG_IDLE_E_NOTSET | 0x0 | Non-Idle Mode
835  * ALT_QSPI_CFG_IDLE_E_SET | 0x1 | Idle Mode
836  *
837  * Field Access Macros:
838  *
839  */
840 /*
841  * Enumerated value for register field ALT_QSPI_CFG_IDLE
842  *
843  * Non-Idle Mode
844  */
845 #define ALT_QSPI_CFG_IDLE_E_NOTSET 0x0
846 /*
847  * Enumerated value for register field ALT_QSPI_CFG_IDLE
848  *
849  * Idle Mode
850  */
851 #define ALT_QSPI_CFG_IDLE_E_SET 0x1
852 
853 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_IDLE register field. */
854 #define ALT_QSPI_CFG_IDLE_LSB 31
855 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_IDLE register field. */
856 #define ALT_QSPI_CFG_IDLE_MSB 31
857 /* The width in bits of the ALT_QSPI_CFG_IDLE register field. */
858 #define ALT_QSPI_CFG_IDLE_WIDTH 1
859 /* The mask used to set the ALT_QSPI_CFG_IDLE register field value. */
860 #define ALT_QSPI_CFG_IDLE_SET_MSK 0x80000000
861 /* The mask used to clear the ALT_QSPI_CFG_IDLE register field value. */
862 #define ALT_QSPI_CFG_IDLE_CLR_MSK 0x7fffffff
863 /* The reset value of the ALT_QSPI_CFG_IDLE register field. */
864 #define ALT_QSPI_CFG_IDLE_RESET 0x1
865 /* Extracts the ALT_QSPI_CFG_IDLE field value from a register. */
866 #define ALT_QSPI_CFG_IDLE_GET(value) (((value) & 0x80000000) >> 31)
867 /* Produces a ALT_QSPI_CFG_IDLE register field value suitable for setting the register. */
868 #define ALT_QSPI_CFG_IDLE_SET(value) (((value) << 31) & 0x80000000)
869 
870 #ifndef __ASSEMBLY__
871 /*
872  * WARNING: The C register and register group struct declarations are provided for
873  * convenience and illustrative purposes. They should, however, be used with
874  * caution as the C language standard provides no guarantees about the alignment or
875  * atomicity of device memory accesses. The recommended practice for writing
876  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
877  * alt_write_word() functions.
878  *
879  * The struct declaration for register ALT_QSPI_CFG.
880  */
881 struct ALT_QSPI_CFG_s
882 {
883  uint32_t en : 1; /* QSPI Enable */
884  uint32_t selclkpol : 1; /* Clock polarity outside SPI word */
885  uint32_t selclkphase : 1; /* Select Clock Phase */
886  const uint32_t config_resv1_fld : 4; /* Reserved */
887  uint32_t endiracc : 1; /* Enable Direct Access Controller */
888  uint32_t enlegacyip : 1; /* Legacy IP Mode Enable */
889  uint32_t perseldec : 1; /* Peripheral select decode */
890  uint32_t percslines : 4; /* Peripheral Chip Select Lines */
891  uint32_t wp : 1; /* Write Protect Flash Pin */
892  uint32_t endma : 1; /* Enable DMA Peripheral Interface */
893  uint32_t enahbremap : 1; /* Enable AHB Address Re-mapping */
894  uint32_t enterxipnextrd : 1; /* Enter XIP Mode on next READ */
895  uint32_t enterxipimm : 1; /* Enter XIP Mode immediately */
896  uint32_t bauddiv : 4; /* Master Mode Baud Rate Divisor */
897  const uint32_t config_resv2_fld : 8; /* Reserved */
898  const uint32_t idle : 1; /* Serial interface and QSPI pipeline is IDLE */
899 };
900 
901 /* The typedef declaration for register ALT_QSPI_CFG. */
902 typedef volatile struct ALT_QSPI_CFG_s ALT_QSPI_CFG_t;
903 #endif /* __ASSEMBLY__ */
904 
905 /* The reset value of the ALT_QSPI_CFG register. */
906 #define ALT_QSPI_CFG_RESET 0x80780000
907 /* The byte offset of the ALT_QSPI_CFG register from the beginning of the component. */
908 #define ALT_QSPI_CFG_OFST 0x0
909 
910 /*
911  * Register : Device Read Instruction Configuration Register - devrd
912  *
913  * Register Layout
914  *
915  * Bits | Access | Reset | Description
916  * :--------|:-------|:------|:---------------------------------------------
917  * [7:0] | RW | 0x3 | Read Opcode in non-XIP mode
918  * [9:8] | RW | 0x0 | Instruction Type
919  * [11:10] | R | 0x0 | Reserved
920  * [13:12] | RW | 0x0 | Address Transfer Type for Standard SPI modes
921  * [15:14] | R | 0x0 | Reserved
922  * [17:16] | RW | 0x0 | Data Transfer Type for Standard SPI modes
923  * [19:18] | R | 0x0 | Reserved
924  * [20] | RW | 0x0 | Mode Bit Enable
925  * [23:21] | R | 0x0 | Reserved
926  * [28:24] | RW | 0x0 | Dummy Read Clock Cycles
927  * [31:29] | R | 0x0 | Reserved
928  *
929  */
930 /*
931  * Field : Read Opcode in non-XIP mode - rdopcode
932  *
933  * Read Opcode to use when not in XIP mode
934  *
935  * Field Enumeration Values:
936  *
937  * Enum | Value | Description
938  * :---------------------------------|:------|:----------------------------
939  * ALT_QSPI_DEVRD_RDOPCODE_E_RD | 0x3 | Read Opcode in Non-XIP mode
940  * ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD | 0xb | Fast Read in Non-XIP mode
941  *
942  * Field Access Macros:
943  *
944  */
945 /*
946  * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE
947  *
948  * Read Opcode in Non-XIP mode
949  */
950 #define ALT_QSPI_DEVRD_RDOPCODE_E_RD 0x3
951 /*
952  * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE
953  *
954  * Fast Read in Non-XIP mode
955  */
956 #define ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD 0xb
957 
958 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */
959 #define ALT_QSPI_DEVRD_RDOPCODE_LSB 0
960 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */
961 #define ALT_QSPI_DEVRD_RDOPCODE_MSB 7
962 /* The width in bits of the ALT_QSPI_DEVRD_RDOPCODE register field. */
963 #define ALT_QSPI_DEVRD_RDOPCODE_WIDTH 8
964 /* The mask used to set the ALT_QSPI_DEVRD_RDOPCODE register field value. */
965 #define ALT_QSPI_DEVRD_RDOPCODE_SET_MSK 0x000000ff
966 /* The mask used to clear the ALT_QSPI_DEVRD_RDOPCODE register field value. */
967 #define ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK 0xffffff00
968 /* The reset value of the ALT_QSPI_DEVRD_RDOPCODE register field. */
969 #define ALT_QSPI_DEVRD_RDOPCODE_RESET 0x3
970 /* Extracts the ALT_QSPI_DEVRD_RDOPCODE field value from a register. */
971 #define ALT_QSPI_DEVRD_RDOPCODE_GET(value) (((value) & 0x000000ff) >> 0)
972 /* Produces a ALT_QSPI_DEVRD_RDOPCODE register field value suitable for setting the register. */
973 #define ALT_QSPI_DEVRD_RDOPCODE_SET(value) (((value) << 0) & 0x000000ff)
974 
975 /*
976  * Field : Instruction Type - instwidth
977  *
978  * 0 : Use Standard SPI mode (instruction always shifted into the device on DQ0
979  * only) 1 : Use DIO-SPI mode (Instructions, Address and Data always sent on DQ0
980  * and DQ1) 2 : Use QIO-SPI mode (Instructions, Address and Data always sent on
981  * DQ0, DQ1, DQ2 and DDQ3)
982  *
983  * Field Enumeration Values:
984  *
985  * Enum | Value | Description
986  * :----------------------------------|:------|:-------------------------------------------------
987  * ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE | 0x0 | Instruction transferred on DQ0. Supported by all
988  * : | | SPI flash devices.
989  * ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL | 0x1 | Instruction transferred on DQ0 and DQ1.
990  * : | | Supported by all SPI flash devices that support
991  * : | | the Dual SP (DIO-SPI) Protocol.
992  * ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD | 0x2 | Instruction transferred on DQ0, DQ1, DQ2, and
993  * : | | DQ3. Supported by all SPI flash devices that
994  * : | | support the Quad SP (QIO-SPI) Protocol.
995  *
996  * Field Access Macros:
997  *
998  */
999 /*
1000  * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH
1001  *
1002  * Instruction transferred on DQ0. Supported by all SPI flash devices.
1003  */
1004 #define ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE 0x0
1005 /*
1006  * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH
1007  *
1008  * Instruction transferred on DQ0 and DQ1. Supported by all SPI flash devices that
1009  * support the Dual SP (DIO-SPI) Protocol.
1010  */
1011 #define ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL 0x1
1012 /*
1013  * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH
1014  *
1015  * Instruction transferred on DQ0, DQ1, DQ2, and DQ3. Supported by all SPI flash
1016  * devices that support the Quad SP (QIO-SPI) Protocol.
1017  */
1018 #define ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD 0x2
1019 
1020 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */
1021 #define ALT_QSPI_DEVRD_INSTWIDTH_LSB 8
1022 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */
1023 #define ALT_QSPI_DEVRD_INSTWIDTH_MSB 9
1024 /* The width in bits of the ALT_QSPI_DEVRD_INSTWIDTH register field. */
1025 #define ALT_QSPI_DEVRD_INSTWIDTH_WIDTH 2
1026 /* The mask used to set the ALT_QSPI_DEVRD_INSTWIDTH register field value. */
1027 #define ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK 0x00000300
1028 /* The mask used to clear the ALT_QSPI_DEVRD_INSTWIDTH register field value. */
1029 #define ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK 0xfffffcff
1030 /* The reset value of the ALT_QSPI_DEVRD_INSTWIDTH register field. */
1031 #define ALT_QSPI_DEVRD_INSTWIDTH_RESET 0x0
1032 /* Extracts the ALT_QSPI_DEVRD_INSTWIDTH field value from a register. */
1033 #define ALT_QSPI_DEVRD_INSTWIDTH_GET(value) (((value) & 0x00000300) >> 8)
1034 /* Produces a ALT_QSPI_DEVRD_INSTWIDTH register field value suitable for setting the register. */
1035 #define ALT_QSPI_DEVRD_INSTWIDTH_SET(value) (((value) << 8) & 0x00000300)
1036 
1037 /*
1038  * Field : Reserved - rd_instr_resv1_fld
1039  *
1040  * Field Access Macros:
1041  *
1042  */
1043 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD register field. */
1044 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_LSB 10
1045 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD register field. */
1046 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_MSB 11
1047 /* The width in bits of the ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD register field. */
1048 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_WIDTH 2
1049 /* The mask used to set the ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD register field value. */
1050 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_SET_MSK 0x00000c00
1051 /* The mask used to clear the ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD register field value. */
1052 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_CLR_MSK 0xfffff3ff
1053 /* The reset value of the ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD register field. */
1054 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_RESET 0x0
1055 /* Extracts the ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD field value from a register. */
1056 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_GET(value) (((value) & 0x00000c00) >> 10)
1057 /* Produces a ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD register field value suitable for setting the register. */
1058 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_SET(value) (((value) << 10) & 0x00000c00)
1059 
1060 /*
1061  * Field : Address Transfer Type for Standard SPI modes - addrwidth
1062  *
1063  * 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be
1064  * shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the
1065  * device on DQ0, DQ1, DQ2 and DQ3
1066  *
1067  * Field Enumeration Values:
1068  *
1069  * Enum | Value | Description
1070  * :----------------------------------|:------|:-------------------------------------------------
1071  * ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE | 0x0 | Read address transferred on DQ0. Supported by
1072  * : | | all SPI flash devices
1073  * ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL | 0x1 | Read address transferred on DQ0 and DQ1.
1074  * : | | Supported by some SPI flash devices that support
1075  * : | | the Extended SPI Protocol and by all SPI flash
1076  * : | | devices that support the Dual SP (DIO-SPI)
1077  * : | | Protocol.
1078  * ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD | 0x2 | Read address transferred on DQ0, DQ1, DQ2, and
1079  * : | | DQ3. Supported by some SPI flash devices that
1080  * : | | support the Extended SPI Protocol and by all SPI
1081  * : | | flash devices that support the Quad SP (QIO-SPI)
1082  * : | | Protocol.
1083  *
1084  * Field Access Macros:
1085  *
1086  */
1087 /*
1088  * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH
1089  *
1090  * Read address transferred on DQ0. Supported by all SPI flash devices
1091  */
1092 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE 0x0
1093 /*
1094  * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH
1095  *
1096  * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices
1097  * that support the Extended SPI Protocol and by all SPI flash devices that support
1098  * the Dual SP (DIO-SPI) Protocol.
1099  */
1100 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL 0x1
1101 /*
1102  * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH
1103  *
1104  * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash
1105  * devices that support the Extended SPI Protocol and by all SPI flash devices that
1106  * support the Quad SP (QIO-SPI) Protocol.
1107  */
1108 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD 0x2
1109 
1110 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */
1111 #define ALT_QSPI_DEVRD_ADDRWIDTH_LSB 12
1112 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */
1113 #define ALT_QSPI_DEVRD_ADDRWIDTH_MSB 13
1114 /* The width in bits of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */
1115 #define ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH 2
1116 /* The mask used to set the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */
1117 #define ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK 0x00003000
1118 /* The mask used to clear the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */
1119 #define ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK 0xffffcfff
1120 /* The reset value of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */
1121 #define ALT_QSPI_DEVRD_ADDRWIDTH_RESET 0x0
1122 /* Extracts the ALT_QSPI_DEVRD_ADDRWIDTH field value from a register. */
1123 #define ALT_QSPI_DEVRD_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)
1124 /* Produces a ALT_QSPI_DEVRD_ADDRWIDTH register field value suitable for setting the register. */
1125 #define ALT_QSPI_DEVRD_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)
1126 
1127 /*
1128  * Field : Reserved - rd_instr_resv2_fld
1129  *
1130  * Field Access Macros:
1131  *
1132  */
1133 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD register field. */
1134 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_LSB 14
1135 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD register field. */
1136 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_MSB 15
1137 /* The width in bits of the ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD register field. */
1138 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_WIDTH 2
1139 /* The mask used to set the ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD register field value. */
1140 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_SET_MSK 0x0000c000
1141 /* The mask used to clear the ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD register field value. */
1142 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_CLR_MSK 0xffff3fff
1143 /* The reset value of the ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD register field. */
1144 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_RESET 0x0
1145 /* Extracts the ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD field value from a register. */
1146 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_GET(value) (((value) & 0x0000c000) >> 14)
1147 /* Produces a ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD register field value suitable for setting the register. */
1148 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_SET(value) (((value) << 14) & 0x0000c000)
1149 
1150 /*
1151  * Field : Data Transfer Type for Standard SPI modes - datawidth
1152  *
1153  * 0 : SIO mode data is shifted to the device on DQ0 only and from the device on
1154  * DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers, DQ0
1155  * and DQ1 are used as both inputs and outputs. 2 : Used for Quad Input/Output
1156  * instructions. For data transfers, DQ0,DQ1,DQ2 and DQ3 are used as both inputs
1157  * and outputs.
1158  *
1159  * Field Enumeration Values:
1160  *
1161  * Enum | Value | Description
1162  * :----------------------------------|:------|:-------------------------------------------------
1163  * ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE | 0x0 | Read data transferred on DQ0. Supported by all
1164  * : | | SPI flash devices
1165  * ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL | 0x1 | Read data transferred on DQ0 and DQ1. Supported
1166  * : | | by some SPI flash devices that support the
1167  * : | | Extended SPI Protocol and by all SPI flash
1168  * : | | devices that support the Dual SP (DIO-SPI)
1169  * : | | Protocol.
1170  * ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD | 0x2 | Read data transferred on DQ0, DQ1, DQ2, and DQ3.
1171  * : | | Supported by some SPI flash devices that support
1172  * : | | the Extended SPI Protocol and by all SPI flash
1173  * : | | devices that support the Quad SP (QIO-SPI)
1174  * : | | Protocol.
1175  *
1176  * Field Access Macros:
1177  *
1178  */
1179 /*
1180  * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH
1181  *
1182  * Read data transferred on DQ0. Supported by all SPI flash devices
1183  */
1184 #define ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE 0x0
1185 /*
1186  * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH
1187  *
1188  * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that
1189  * support the Extended SPI Protocol and by all SPI flash devices that support the
1190  * Dual SP (DIO-SPI) Protocol.
1191  */
1192 #define ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL 0x1
1193 /*
1194  * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH
1195  *
1196  * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash
1197  * devices that support the Extended SPI Protocol and by all SPI flash devices that
1198  * support the Quad SP (QIO-SPI) Protocol.
1199  */
1200 #define ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD 0x2
1201 
1202 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */
1203 #define ALT_QSPI_DEVRD_DATAWIDTH_LSB 16
1204 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */
1205 #define ALT_QSPI_DEVRD_DATAWIDTH_MSB 17
1206 /* The width in bits of the ALT_QSPI_DEVRD_DATAWIDTH register field. */
1207 #define ALT_QSPI_DEVRD_DATAWIDTH_WIDTH 2
1208 /* The mask used to set the ALT_QSPI_DEVRD_DATAWIDTH register field value. */
1209 #define ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK 0x00030000
1210 /* The mask used to clear the ALT_QSPI_DEVRD_DATAWIDTH register field value. */
1211 #define ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK 0xfffcffff
1212 /* The reset value of the ALT_QSPI_DEVRD_DATAWIDTH register field. */
1213 #define ALT_QSPI_DEVRD_DATAWIDTH_RESET 0x0
1214 /* Extracts the ALT_QSPI_DEVRD_DATAWIDTH field value from a register. */
1215 #define ALT_QSPI_DEVRD_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)
1216 /* Produces a ALT_QSPI_DEVRD_DATAWIDTH register field value suitable for setting the register. */
1217 #define ALT_QSPI_DEVRD_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)
1218 
1219 /*
1220  * Field : Reserved - rd_instr_resv3_fld
1221  *
1222  * Field Access Macros:
1223  *
1224  */
1225 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD register field. */
1226 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_LSB 18
1227 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD register field. */
1228 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_MSB 19
1229 /* The width in bits of the ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD register field. */
1230 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_WIDTH 2
1231 /* The mask used to set the ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD register field value. */
1232 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_SET_MSK 0x000c0000
1233 /* The mask used to clear the ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD register field value. */
1234 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_CLR_MSK 0xfff3ffff
1235 /* The reset value of the ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD register field. */
1236 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_RESET 0x0
1237 /* Extracts the ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD field value from a register. */
1238 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_GET(value) (((value) & 0x000c0000) >> 18)
1239 /* Produces a ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD register field value suitable for setting the register. */
1240 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_SET(value) (((value) << 18) & 0x000c0000)
1241 
1242 /*
1243  * Field : Mode Bit Enable - enmodebits
1244  *
1245  * Set this field to 1 to ensure that the mode bits as defined in the Mode Bit
1246  * Configuration register are sent following the address bytes.
1247  *
1248  * Field Enumeration Values:
1249  *
1250  * Enum | Value | Description
1251  * :-----------------------------------|:------|:-------------------------------
1252  * ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER | 0x0 | No Order
1253  * ALT_QSPI_DEVRD_ENMODBITS_E_ORDER | 0x1 | Mode Bits follow address bytes
1254  *
1255  * Field Access Macros:
1256  *
1257  */
1258 /*
1259  * Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS
1260  *
1261  * No Order
1262  */
1263 #define ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER 0x0
1264 /*
1265  * Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS
1266  *
1267  * Mode Bits follow address bytes
1268  */
1269 #define ALT_QSPI_DEVRD_ENMODBITS_E_ORDER 0x1
1270 
1271 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field. */
1272 #define ALT_QSPI_DEVRD_ENMODBITS_LSB 20
1273 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field. */
1274 #define ALT_QSPI_DEVRD_ENMODBITS_MSB 20
1275 /* The width in bits of the ALT_QSPI_DEVRD_ENMODBITS register field. */
1276 #define ALT_QSPI_DEVRD_ENMODBITS_WIDTH 1
1277 /* The mask used to set the ALT_QSPI_DEVRD_ENMODBITS register field value. */
1278 #define ALT_QSPI_DEVRD_ENMODBITS_SET_MSK 0x00100000
1279 /* The mask used to clear the ALT_QSPI_DEVRD_ENMODBITS register field value. */
1280 #define ALT_QSPI_DEVRD_ENMODBITS_CLR_MSK 0xffefffff
1281 /* The reset value of the ALT_QSPI_DEVRD_ENMODBITS register field. */
1282 #define ALT_QSPI_DEVRD_ENMODBITS_RESET 0x0
1283 /* Extracts the ALT_QSPI_DEVRD_ENMODBITS field value from a register. */
1284 #define ALT_QSPI_DEVRD_ENMODBITS_GET(value) (((value) & 0x00100000) >> 20)
1285 /* Produces a ALT_QSPI_DEVRD_ENMODBITS register field value suitable for setting the register. */
1286 #define ALT_QSPI_DEVRD_ENMODBITS_SET(value) (((value) << 20) & 0x00100000)
1287 
1288 /*
1289  * Field : Reserved - rd_instr_resv4_fld
1290  *
1291  * Field Access Macros:
1292  *
1293  */
1294 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD register field. */
1295 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_LSB 21
1296 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD register field. */
1297 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_MSB 23
1298 /* The width in bits of the ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD register field. */
1299 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_WIDTH 3
1300 /* The mask used to set the ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD register field value. */
1301 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_SET_MSK 0x00e00000
1302 /* The mask used to clear the ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD register field value. */
1303 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_CLR_MSK 0xff1fffff
1304 /* The reset value of the ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD register field. */
1305 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_RESET 0x0
1306 /* Extracts the ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD field value from a register. */
1307 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_GET(value) (((value) & 0x00e00000) >> 21)
1308 /* Produces a ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD register field value suitable for setting the register. */
1309 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_SET(value) (((value) << 21) & 0x00e00000)
1310 
1311 /*
1312  * Field : Dummy Read Clock Cycles - dummyrdclks
1313  *
1314  * Number of dummy clock cycles required by device for read instruction.
1315  *
1316  * Field Access Macros:
1317  *
1318  */
1319 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */
1320 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB 24
1321 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */
1322 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB 28
1323 /* The width in bits of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */
1324 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH 5
1325 /* The mask used to set the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */
1326 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK 0x1f000000
1327 /* The mask used to clear the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */
1328 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK 0xe0ffffff
1329 /* The reset value of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */
1330 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET 0x0
1331 /* Extracts the ALT_QSPI_DEVRD_DUMMYRDCLKS field value from a register. */
1332 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(value) (((value) & 0x1f000000) >> 24)
1333 /* Produces a ALT_QSPI_DEVRD_DUMMYRDCLKS register field value suitable for setting the register. */
1334 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(value) (((value) << 24) & 0x1f000000)
1335 
1336 /*
1337  * Field : Reserved - rd_instr_resv5_fld
1338  *
1339  * Field Access Macros:
1340  *
1341  */
1342 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD register field. */
1343 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_LSB 29
1344 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD register field. */
1345 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_MSB 31
1346 /* The width in bits of the ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD register field. */
1347 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_WIDTH 3
1348 /* The mask used to set the ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD register field value. */
1349 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_SET_MSK 0xe0000000
1350 /* The mask used to clear the ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD register field value. */
1351 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_CLR_MSK 0x1fffffff
1352 /* The reset value of the ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD register field. */
1353 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_RESET 0x0
1354 /* Extracts the ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD field value from a register. */
1355 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_GET(value) (((value) & 0xe0000000) >> 29)
1356 /* Produces a ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD register field value suitable for setting the register. */
1357 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_SET(value) (((value) << 29) & 0xe0000000)
1358 
1359 #ifndef __ASSEMBLY__
1360 /*
1361  * WARNING: The C register and register group struct declarations are provided for
1362  * convenience and illustrative purposes. They should, however, be used with
1363  * caution as the C language standard provides no guarantees about the alignment or
1364  * atomicity of device memory accesses. The recommended practice for writing
1365  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1366  * alt_write_word() functions.
1367  *
1368  * The struct declaration for register ALT_QSPI_DEVRD.
1369  */
1370 struct ALT_QSPI_DEVRD_s
1371 {
1372  uint32_t rdopcode : 8; /* Read Opcode in non-XIP mode */
1373  uint32_t instwidth : 2; /* Instruction Type */
1374  const uint32_t rd_instr_resv1_fld : 2; /* Reserved */
1375  uint32_t addrwidth : 2; /* Address Transfer Type for Standard SPI modes */
1376  const uint32_t rd_instr_resv2_fld : 2; /* Reserved */
1377  uint32_t datawidth : 2; /* Data Transfer Type for Standard SPI modes */
1378  const uint32_t rd_instr_resv3_fld : 2; /* Reserved */
1379  uint32_t enmodebits : 1; /* Mode Bit Enable */
1380  const uint32_t rd_instr_resv4_fld : 3; /* Reserved */
1381  uint32_t dummyrdclks : 5; /* Dummy Read Clock Cycles */
1382  const uint32_t rd_instr_resv5_fld : 3; /* Reserved */
1383 };
1384 
1385 /* The typedef declaration for register ALT_QSPI_DEVRD. */
1386 typedef volatile struct ALT_QSPI_DEVRD_s ALT_QSPI_DEVRD_t;
1387 #endif /* __ASSEMBLY__ */
1388 
1389 /* The reset value of the ALT_QSPI_DEVRD register. */
1390 #define ALT_QSPI_DEVRD_RESET 0x00000003
1391 /* The byte offset of the ALT_QSPI_DEVRD register from the beginning of the component. */
1392 #define ALT_QSPI_DEVRD_OFST 0x4
1393 
1394 /*
1395  * Register : Device Write Instruction Configuration Register - devwr
1396  *
1397  * Register Layout
1398  *
1399  * Bits | Access | Reset | Description
1400  * :--------|:-------|:------|:---------------------------------------------
1401  * [7:0] | RW | 0x2 | Write Opcode
1402  * [11:8] | R | 0x0 | Reserved
1403  * [13:12] | RW | 0x0 | Address Transfer Type for Standard SPI modes
1404  * [15:14] | R | 0x0 | Reserved
1405  * [17:16] | RW | 0x0 | Data Transfer Type for Standard SPI modes
1406  * [23:18] | R | 0x0 | Reserved
1407  * [28:24] | RW | 0x0 | Dummy Write Clock Cycles
1408  * [31:29] | R | 0x0 | Reserved
1409  *
1410  */
1411 /*
1412  * Field : Write Opcode - wropcode
1413  *
1414  * Write Opcode
1415  *
1416  * Field Access Macros:
1417  *
1418  */
1419 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */
1420 #define ALT_QSPI_DEVWR_WROPCODE_LSB 0
1421 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */
1422 #define ALT_QSPI_DEVWR_WROPCODE_MSB 7
1423 /* The width in bits of the ALT_QSPI_DEVWR_WROPCODE register field. */
1424 #define ALT_QSPI_DEVWR_WROPCODE_WIDTH 8
1425 /* The mask used to set the ALT_QSPI_DEVWR_WROPCODE register field value. */
1426 #define ALT_QSPI_DEVWR_WROPCODE_SET_MSK 0x000000ff
1427 /* The mask used to clear the ALT_QSPI_DEVWR_WROPCODE register field value. */
1428 #define ALT_QSPI_DEVWR_WROPCODE_CLR_MSK 0xffffff00
1429 /* The reset value of the ALT_QSPI_DEVWR_WROPCODE register field. */
1430 #define ALT_QSPI_DEVWR_WROPCODE_RESET 0x2
1431 /* Extracts the ALT_QSPI_DEVWR_WROPCODE field value from a register. */
1432 #define ALT_QSPI_DEVWR_WROPCODE_GET(value) (((value) & 0x000000ff) >> 0)
1433 /* Produces a ALT_QSPI_DEVWR_WROPCODE register field value suitable for setting the register. */
1434 #define ALT_QSPI_DEVWR_WROPCODE_SET(value) (((value) << 0) & 0x000000ff)
1435 
1436 /*
1437  * Field : Reserved - wr_instr_resv1_fld
1438  *
1439  * Field Access Macros:
1440  *
1441  */
1442 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD register field. */
1443 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_LSB 8
1444 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD register field. */
1445 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_MSB 11
1446 /* The width in bits of the ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD register field. */
1447 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_WIDTH 4
1448 /* The mask used to set the ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD register field value. */
1449 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_SET_MSK 0x00000f00
1450 /* The mask used to clear the ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD register field value. */
1451 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_CLR_MSK 0xfffff0ff
1452 /* The reset value of the ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD register field. */
1453 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_RESET 0x0
1454 /* Extracts the ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD field value from a register. */
1455 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_GET(value) (((value) & 0x00000f00) >> 8)
1456 /* Produces a ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD register field value suitable for setting the register. */
1457 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_SET(value) (((value) << 8) & 0x00000f00)
1458 
1459 /*
1460  * Field : Address Transfer Type for Standard SPI modes - addrwidth
1461  *
1462  * 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be
1463  * shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the
1464  * device on DQ0, DQ1, DQ2 and DQ3
1465  *
1466  * Field Enumeration Values:
1467  *
1468  * Enum | Value | Description
1469  * :----------------------------------|:------|:-------------------------------------------------
1470  * ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE | 0x0 | Write address transferred on DQ0. Supported by
1471  * : | | all SPI flash devices
1472  * ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL | 0x1 | Read address transferred on DQ0 and DQ1.
1473  * : | | Supported by some SPI flash devices that support
1474  * : | | the Extended SPI Protocol and by all SPI flash
1475  * : | | devices that support the Dual SP (DIO-SPI)
1476  * : | | Protocol.
1477  * ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD | 0x2 | Read address transferred on DQ0, DQ1, DQ2, and
1478  * : | | DQ3. Supported by some SPI flash devices that
1479  * : | | support the Extended SPI Protocol and by all SPI
1480  * : | | flash devices that support the Quad SP (QIO-SPI)
1481  * : | | Protocol.
1482  *
1483  * Field Access Macros:
1484  *
1485  */
1486 /*
1487  * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH
1488  *
1489  * Write address transferred on DQ0. Supported by all SPI flash devices
1490  */
1491 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE 0x0
1492 /*
1493  * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH
1494  *
1495  * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices
1496  * that support the Extended SPI Protocol and by all SPI flash devices that support
1497  * the Dual SP (DIO-SPI) Protocol.
1498  */
1499 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL 0x1
1500 /*
1501  * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH
1502  *
1503  * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash
1504  * devices that support the Extended SPI Protocol and by all SPI flash devices that
1505  * support the Quad SP (QIO-SPI) Protocol.
1506  */
1507 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD 0x2
1508 
1509 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */
1510 #define ALT_QSPI_DEVWR_ADDRWIDTH_LSB 12
1511 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */
1512 #define ALT_QSPI_DEVWR_ADDRWIDTH_MSB 13
1513 /* The width in bits of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */
1514 #define ALT_QSPI_DEVWR_ADDRWIDTH_WIDTH 2
1515 /* The mask used to set the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */
1516 #define ALT_QSPI_DEVWR_ADDRWIDTH_SET_MSK 0x00003000
1517 /* The mask used to clear the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */
1518 #define ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK 0xffffcfff
1519 /* The reset value of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */
1520 #define ALT_QSPI_DEVWR_ADDRWIDTH_RESET 0x0
1521 /* Extracts the ALT_QSPI_DEVWR_ADDRWIDTH field value from a register. */
1522 #define ALT_QSPI_DEVWR_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)
1523 /* Produces a ALT_QSPI_DEVWR_ADDRWIDTH register field value suitable for setting the register. */
1524 #define ALT_QSPI_DEVWR_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)
1525 
1526 /*
1527  * Field : Reserved - wr_instr_resv2_fld
1528  *
1529  * Field Access Macros:
1530  *
1531  */
1532 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD register field. */
1533 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_LSB 14
1534 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD register field. */
1535 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_MSB 15
1536 /* The width in bits of the ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD register field. */
1537 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_WIDTH 2
1538 /* The mask used to set the ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD register field value. */
1539 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_SET_MSK 0x0000c000
1540 /* The mask used to clear the ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD register field value. */
1541 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_CLR_MSK 0xffff3fff
1542 /* The reset value of the ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD register field. */
1543 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_RESET 0x0
1544 /* Extracts the ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD field value from a register. */
1545 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_GET(value) (((value) & 0x0000c000) >> 14)
1546 /* Produces a ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD register field value suitable for setting the register. */
1547 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_SET(value) (((value) << 14) & 0x0000c000)
1548 
1549 /*
1550  * Field : Data Transfer Type for Standard SPI modes - datawidth
1551  *
1552  * 0 : SIO mode data is shifted to the device on DQ0 only and from the device on
1553  * DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers, DQ0
1554  * and DQ1 are used as both inputs and outputs. 2 : Used for Quad Input/Output
1555  * instructions. For data transfers, DQ0,DQ1,DQ2 and DQ3 are used as both inputs
1556  * and outputs.
1557  *
1558  * Field Enumeration Values:
1559  *
1560  * Enum | Value | Description
1561  * :----------------------------------|:------|:-------------------------------------------------
1562  * ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE | 0x0 | Write data transferred on DQ0. Supported by all
1563  * : | | SPI flash devices
1564  * ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL | 0x1 | Read data transferred on DQ0 and DQ1. Supported
1565  * : | | by some SPI flash devices that support the
1566  * : | | Extended SPI Protocol and by all SPI flash
1567  * : | | devices that support the Dual SP (DIO-SPI)
1568  * : | | Protocol.
1569  * ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD | 0x2 | Read data transferred on DQ0, DQ1, DQ2, and DQ3.
1570  * : | | Supported by some SPI flash devices that support
1571  * : | | the Extended SPI Protocol and by all SPI flash
1572  * : | | devices that support the Quad SP (QIO-SPI)
1573  * : | | Protocol.
1574  *
1575  * Field Access Macros:
1576  *
1577  */
1578 /*
1579  * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH
1580  *
1581  * Write data transferred on DQ0. Supported by all SPI flash devices
1582  */
1583 #define ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE 0x0
1584 /*
1585  * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH
1586  *
1587  * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that
1588  * support the Extended SPI Protocol and by all SPI flash devices that support the
1589  * Dual SP (DIO-SPI) Protocol.
1590  */
1591 #define ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL 0x1
1592 /*
1593  * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH
1594  *
1595  * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash
1596  * devices that support the Extended SPI Protocol and by all SPI flash devices that
1597  * support the Quad SP (QIO-SPI) Protocol.
1598  */
1599 #define ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD 0x2
1600 
1601 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */
1602 #define ALT_QSPI_DEVWR_DATAWIDTH_LSB 16
1603 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */
1604 #define ALT_QSPI_DEVWR_DATAWIDTH_MSB 17
1605 /* The width in bits of the ALT_QSPI_DEVWR_DATAWIDTH register field. */
1606 #define ALT_QSPI_DEVWR_DATAWIDTH_WIDTH 2
1607 /* The mask used to set the ALT_QSPI_DEVWR_DATAWIDTH register field value. */
1608 #define ALT_QSPI_DEVWR_DATAWIDTH_SET_MSK 0x00030000
1609 /* The mask used to clear the ALT_QSPI_DEVWR_DATAWIDTH register field value. */
1610 #define ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK 0xfffcffff
1611 /* The reset value of the ALT_QSPI_DEVWR_DATAWIDTH register field. */
1612 #define ALT_QSPI_DEVWR_DATAWIDTH_RESET 0x0
1613 /* Extracts the ALT_QSPI_DEVWR_DATAWIDTH field value from a register. */
1614 #define ALT_QSPI_DEVWR_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)
1615 /* Produces a ALT_QSPI_DEVWR_DATAWIDTH register field value suitable for setting the register. */
1616 #define ALT_QSPI_DEVWR_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)
1617 
1618 /*
1619  * Field : Reserved - wr_instr_resv3_fld
1620  *
1621  * Field Access Macros:
1622  *
1623  */
1624 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD register field. */
1625 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_LSB 18
1626 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD register field. */
1627 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_MSB 23
1628 /* The width in bits of the ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD register field. */
1629 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_WIDTH 6
1630 /* The mask used to set the ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD register field value. */
1631 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_SET_MSK 0x00fc0000
1632 /* The mask used to clear the ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD register field value. */
1633 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_CLR_MSK 0xff03ffff
1634 /* The reset value of the ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD register field. */
1635 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_RESET 0x0
1636 /* Extracts the ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD field value from a register. */
1637 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_GET(value) (((value) & 0x00fc0000) >> 18)
1638 /* Produces a ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD register field value suitable for setting the register. */
1639 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_SET(value) (((value) << 18) & 0x00fc0000)
1640 
1641 /*
1642  * Field : Dummy Write Clock Cycles - dummywrclks
1643  *
1644  * Number of dummy clock cycles required by device for write instruction.
1645  *
1646  * Field Access Macros:
1647  *
1648  */
1649 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */
1650 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_LSB 24
1651 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */
1652 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_MSB 28
1653 /* The width in bits of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */
1654 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH 5
1655 /* The mask used to set the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */
1656 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET_MSK 0x1f000000
1657 /* The mask used to clear the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */
1658 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK 0xe0ffffff
1659 /* The reset value of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */
1660 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_RESET 0x0
1661 /* Extracts the ALT_QSPI_DEVWR_DUMMYWRCLKS field value from a register. */
1662 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(value) (((value) & 0x1f000000) >> 24)
1663 /* Produces a ALT_QSPI_DEVWR_DUMMYWRCLKS register field value suitable for setting the register. */
1664 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(value) (((value) << 24) & 0x1f000000)
1665 
1666 /*
1667  * Field : Reserved - wr_instr_resv4_fld
1668  *
1669  * Field Access Macros:
1670  *
1671  */
1672 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD register field. */
1673 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_LSB 29
1674 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD register field. */
1675 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_MSB 31
1676 /* The width in bits of the ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD register field. */
1677 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_WIDTH 3
1678 /* The mask used to set the ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD register field value. */
1679 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_SET_MSK 0xe0000000
1680 /* The mask used to clear the ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD register field value. */
1681 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_CLR_MSK 0x1fffffff
1682 /* The reset value of the ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD register field. */
1683 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_RESET 0x0
1684 /* Extracts the ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD field value from a register. */
1685 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_GET(value) (((value) & 0xe0000000) >> 29)
1686 /* Produces a ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD register field value suitable for setting the register. */
1687 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_SET(value) (((value) << 29) & 0xe0000000)
1688 
1689 #ifndef __ASSEMBLY__
1690 /*
1691  * WARNING: The C register and register group struct declarations are provided for
1692  * convenience and illustrative purposes. They should, however, be used with
1693  * caution as the C language standard provides no guarantees about the alignment or
1694  * atomicity of device memory accesses. The recommended practice for writing
1695  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1696  * alt_write_word() functions.
1697  *
1698  * The struct declaration for register ALT_QSPI_DEVWR.
1699  */
1700 struct ALT_QSPI_DEVWR_s
1701 {
1702  uint32_t wropcode : 8; /* Write Opcode */
1703  const uint32_t wr_instr_resv1_fld : 4; /* Reserved */
1704  uint32_t addrwidth : 2; /* Address Transfer Type for Standard SPI modes */
1705  const uint32_t wr_instr_resv2_fld : 2; /* Reserved */
1706  uint32_t datawidth : 2; /* Data Transfer Type for Standard SPI modes */
1707  const uint32_t wr_instr_resv3_fld : 6; /* Reserved */
1708  uint32_t dummywrclks : 5; /* Dummy Write Clock Cycles */
1709  const uint32_t wr_instr_resv4_fld : 3; /* Reserved */
1710 };
1711 
1712 /* The typedef declaration for register ALT_QSPI_DEVWR. */
1713 typedef volatile struct ALT_QSPI_DEVWR_s ALT_QSPI_DEVWR_t;
1714 #endif /* __ASSEMBLY__ */
1715 
1716 /* The reset value of the ALT_QSPI_DEVWR register. */
1717 #define ALT_QSPI_DEVWR_RESET 0x00000002
1718 /* The byte offset of the ALT_QSPI_DEVWR register from the beginning of the component. */
1719 #define ALT_QSPI_DEVWR_OFST 0x8
1720 
1721 /*
1722  * Register : QSPI Device Delay Register - delay
1723  *
1724  * This register is used to introduce relative delays into the generation of the
1725  * master output signals. All timings are defined in cycles of the SPI REFERENCE
1726  * CLOCK/ext_clk, defined in this table as SPI master ref clock.
1727  *
1728  * Register Layout
1729  *
1730  * Bits | Access | Reset | Description
1731  * :--------|:-------|:------|:-----------------------------------------
1732  * [7:0] | RW | 0x0 | Clock Delay with n_ss_out
1733  * [15:8] | RW | 0x0 | Clock Delay for Last Transaction Bit
1734  * [23:16] | RW | 0x0 | Clock Delay for Chip Select Deactivation
1735  * [31:24] | RW | 0x0 | Clock Delay for Chip Select Deassert
1736  *
1737  */
1738 /*
1739  * Field : Clock Delay with n_ss_out - init
1740  *
1741  * Delay in master reference clocks between setting n_ss_out low and first bit
1742  * transfer.
1743  *
1744  * Field Access Macros:
1745  *
1746  */
1747 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_INIT register field. */
1748 #define ALT_QSPI_DELAY_INIT_LSB 0
1749 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_INIT register field. */
1750 #define ALT_QSPI_DELAY_INIT_MSB 7
1751 /* The width in bits of the ALT_QSPI_DELAY_INIT register field. */
1752 #define ALT_QSPI_DELAY_INIT_WIDTH 8
1753 /* The mask used to set the ALT_QSPI_DELAY_INIT register field value. */
1754 #define ALT_QSPI_DELAY_INIT_SET_MSK 0x000000ff
1755 /* The mask used to clear the ALT_QSPI_DELAY_INIT register field value. */
1756 #define ALT_QSPI_DELAY_INIT_CLR_MSK 0xffffff00
1757 /* The reset value of the ALT_QSPI_DELAY_INIT register field. */
1758 #define ALT_QSPI_DELAY_INIT_RESET 0x0
1759 /* Extracts the ALT_QSPI_DELAY_INIT field value from a register. */
1760 #define ALT_QSPI_DELAY_INIT_GET(value) (((value) & 0x000000ff) >> 0)
1761 /* Produces a ALT_QSPI_DELAY_INIT register field value suitable for setting the register. */
1762 #define ALT_QSPI_DELAY_INIT_SET(value) (((value) << 0) & 0x000000ff)
1763 
1764 /*
1765  * Field : Clock Delay for Last Transaction Bit - after
1766  *
1767  * Delay in master reference clocks between last bit of current transaction and
1768  * deasserting the device chip select (n_ss_out). By default, the chip select will
1769  * be deasserted on the cycle following the completion of the current transaction.
1770  *
1771  * Field Access Macros:
1772  *
1773  */
1774 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_AFTER register field. */
1775 #define ALT_QSPI_DELAY_AFTER_LSB 8
1776 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_AFTER register field. */
1777 #define ALT_QSPI_DELAY_AFTER_MSB 15
1778 /* The width in bits of the ALT_QSPI_DELAY_AFTER register field. */
1779 #define ALT_QSPI_DELAY_AFTER_WIDTH 8
1780 /* The mask used to set the ALT_QSPI_DELAY_AFTER register field value. */
1781 #define ALT_QSPI_DELAY_AFTER_SET_MSK 0x0000ff00
1782 /* The mask used to clear the ALT_QSPI_DELAY_AFTER register field value. */
1783 #define ALT_QSPI_DELAY_AFTER_CLR_MSK 0xffff00ff
1784 /* The reset value of the ALT_QSPI_DELAY_AFTER register field. */
1785 #define ALT_QSPI_DELAY_AFTER_RESET 0x0
1786 /* Extracts the ALT_QSPI_DELAY_AFTER field value from a register. */
1787 #define ALT_QSPI_DELAY_AFTER_GET(value) (((value) & 0x0000ff00) >> 8)
1788 /* Produces a ALT_QSPI_DELAY_AFTER register field value suitable for setting the register. */
1789 #define ALT_QSPI_DELAY_AFTER_SET(value) (((value) << 8) & 0x0000ff00)
1790 
1791 /*
1792  * Field : Clock Delay for Chip Select Deactivation - btwn
1793  *
1794  * Delay in master reference clocks between one chip select being de-activated and
1795  * the activation of another. This is used to ensure a quiet period between the
1796  * selection of two different slaves and requires the transmit FIFO to be empty.
1797  *
1798  * Field Access Macros:
1799  *
1800  */
1801 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_BTWN register field. */
1802 #define ALT_QSPI_DELAY_BTWN_LSB 16
1803 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_BTWN register field. */
1804 #define ALT_QSPI_DELAY_BTWN_MSB 23
1805 /* The width in bits of the ALT_QSPI_DELAY_BTWN register field. */
1806 #define ALT_QSPI_DELAY_BTWN_WIDTH 8
1807 /* The mask used to set the ALT_QSPI_DELAY_BTWN register field value. */
1808 #define ALT_QSPI_DELAY_BTWN_SET_MSK 0x00ff0000
1809 /* The mask used to clear the ALT_QSPI_DELAY_BTWN register field value. */
1810 #define ALT_QSPI_DELAY_BTWN_CLR_MSK 0xff00ffff
1811 /* The reset value of the ALT_QSPI_DELAY_BTWN register field. */
1812 #define ALT_QSPI_DELAY_BTWN_RESET 0x0
1813 /* Extracts the ALT_QSPI_DELAY_BTWN field value from a register. */
1814 #define ALT_QSPI_DELAY_BTWN_GET(value) (((value) & 0x00ff0000) >> 16)
1815 /* Produces a ALT_QSPI_DELAY_BTWN register field value suitable for setting the register. */
1816 #define ALT_QSPI_DELAY_BTWN_SET(value) (((value) << 16) & 0x00ff0000)
1817 
1818 /*
1819  * Field : Clock Delay for Chip Select Deassert - nss
1820  *
1821  * Delay in master reference clocks for the length that the master mode chip select
1822  * outputs are de-asserted between transactions. The minimum delay is always SCLK
1823  * period to ensure the chip select is never re-asserted within an SCLK period.
1824  *
1825  * Field Access Macros:
1826  *
1827  */
1828 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_NSS register field. */
1829 #define ALT_QSPI_DELAY_NSS_LSB 24
1830 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_NSS register field. */
1831 #define ALT_QSPI_DELAY_NSS_MSB 31
1832 /* The width in bits of the ALT_QSPI_DELAY_NSS register field. */
1833 #define ALT_QSPI_DELAY_NSS_WIDTH 8
1834 /* The mask used to set the ALT_QSPI_DELAY_NSS register field value. */
1835 #define ALT_QSPI_DELAY_NSS_SET_MSK 0xff000000
1836 /* The mask used to clear the ALT_QSPI_DELAY_NSS register field value. */
1837 #define ALT_QSPI_DELAY_NSS_CLR_MSK 0x00ffffff
1838 /* The reset value of the ALT_QSPI_DELAY_NSS register field. */
1839 #define ALT_QSPI_DELAY_NSS_RESET 0x0
1840 /* Extracts the ALT_QSPI_DELAY_NSS field value from a register. */
1841 #define ALT_QSPI_DELAY_NSS_GET(value) (((value) & 0xff000000) >> 24)
1842 /* Produces a ALT_QSPI_DELAY_NSS register field value suitable for setting the register. */
1843 #define ALT_QSPI_DELAY_NSS_SET(value) (((value) << 24) & 0xff000000)
1844 
1845 #ifndef __ASSEMBLY__
1846 /*
1847  * WARNING: The C register and register group struct declarations are provided for
1848  * convenience and illustrative purposes. They should, however, be used with
1849  * caution as the C language standard provides no guarantees about the alignment or
1850  * atomicity of device memory accesses. The recommended practice for writing
1851  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1852  * alt_write_word() functions.
1853  *
1854  * The struct declaration for register ALT_QSPI_DELAY.
1855  */
1856 struct ALT_QSPI_DELAY_s
1857 {
1858  uint32_t init : 8; /* Clock Delay with n_ss_out */
1859  uint32_t after : 8; /* Clock Delay for Last Transaction Bit */
1860  uint32_t btwn : 8; /* Clock Delay for Chip Select Deactivation */
1861  uint32_t nss : 8; /* Clock Delay for Chip Select Deassert */
1862 };
1863 
1864 /* The typedef declaration for register ALT_QSPI_DELAY. */
1865 typedef volatile struct ALT_QSPI_DELAY_s ALT_QSPI_DELAY_t;
1866 #endif /* __ASSEMBLY__ */
1867 
1868 /* The reset value of the ALT_QSPI_DELAY register. */
1869 #define ALT_QSPI_DELAY_RESET 0x00000000
1870 /* The byte offset of the ALT_QSPI_DELAY register from the beginning of the component. */
1871 #define ALT_QSPI_DELAY_OFST 0xc
1872 
1873 /*
1874  * Register : Read Data Capture Register - rddatacap
1875  *
1876  * Register Layout
1877  *
1878  * Bits | Access | Reset | Description
1879  * :-------|:-------|:------|:------------
1880  * [0] | RW | 0x1 | Bypass
1881  * [4:1] | RW | 0x0 | Read Delay
1882  * [31:5] | R | 0x0 | Reserved
1883  *
1884  */
1885 /*
1886  * Field : Bypass - byp
1887  *
1888  * Bypass the adapted loopback clock circuit
1889  *
1890  * Field Enumeration Values:
1891  *
1892  * Enum | Value | Description
1893  * :----------------------------------|:------|:------------------------------
1894  * ALT_QSPI_RDDATACAP_BYP_E_BYPASS | 0x0 | Bypass loopback clock circuit
1895  * ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS | 0x1 | No Bypass
1896  *
1897  * Field Access Macros:
1898  *
1899  */
1900 /*
1901  * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP
1902  *
1903  * Bypass loopback clock circuit
1904  */
1905 #define ALT_QSPI_RDDATACAP_BYP_E_BYPASS 0x0
1906 /*
1907  * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP
1908  *
1909  * No Bypass
1910  */
1911 #define ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS 0x1
1912 
1913 /* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */
1914 #define ALT_QSPI_RDDATACAP_BYP_LSB 0
1915 /* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */
1916 #define ALT_QSPI_RDDATACAP_BYP_MSB 0
1917 /* The width in bits of the ALT_QSPI_RDDATACAP_BYP register field. */
1918 #define ALT_QSPI_RDDATACAP_BYP_WIDTH 1
1919 /* The mask used to set the ALT_QSPI_RDDATACAP_BYP register field value. */
1920 #define ALT_QSPI_RDDATACAP_BYP_SET_MSK 0x00000001
1921 /* The mask used to clear the ALT_QSPI_RDDATACAP_BYP register field value. */
1922 #define ALT_QSPI_RDDATACAP_BYP_CLR_MSK 0xfffffffe
1923 /* The reset value of the ALT_QSPI_RDDATACAP_BYP register field. */
1924 #define ALT_QSPI_RDDATACAP_BYP_RESET 0x1
1925 /* Extracts the ALT_QSPI_RDDATACAP_BYP field value from a register. */
1926 #define ALT_QSPI_RDDATACAP_BYP_GET(value) (((value) & 0x00000001) >> 0)
1927 /* Produces a ALT_QSPI_RDDATACAP_BYP register field value suitable for setting the register. */
1928 #define ALT_QSPI_RDDATACAP_BYP_SET(value) (((value) << 0) & 0x00000001)
1929 
1930 /*
1931  * Field : Read Delay - delay
1932  *
1933  * Delay the read data capturing logic by the programmed number of ref_clk cycles
1934  *
1935  * Field Access Macros:
1936  *
1937  */
1938 /* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */
1939 #define ALT_QSPI_RDDATACAP_DELAY_LSB 1
1940 /* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */
1941 #define ALT_QSPI_RDDATACAP_DELAY_MSB 4
1942 /* The width in bits of the ALT_QSPI_RDDATACAP_DELAY register field. */
1943 #define ALT_QSPI_RDDATACAP_DELAY_WIDTH 4
1944 /* The mask used to set the ALT_QSPI_RDDATACAP_DELAY register field value. */
1945 #define ALT_QSPI_RDDATACAP_DELAY_SET_MSK 0x0000001e
1946 /* The mask used to clear the ALT_QSPI_RDDATACAP_DELAY register field value. */
1947 #define ALT_QSPI_RDDATACAP_DELAY_CLR_MSK 0xffffffe1
1948 /* The reset value of the ALT_QSPI_RDDATACAP_DELAY register field. */
1949 #define ALT_QSPI_RDDATACAP_DELAY_RESET 0x0
1950 /* Extracts the ALT_QSPI_RDDATACAP_DELAY field value from a register. */
1951 #define ALT_QSPI_RDDATACAP_DELAY_GET(value) (((value) & 0x0000001e) >> 1)
1952 /* Produces a ALT_QSPI_RDDATACAP_DELAY register field value suitable for setting the register. */
1953 #define ALT_QSPI_RDDATACAP_DELAY_SET(value) (((value) << 1) & 0x0000001e)
1954 
1955 /*
1956  * Field : Reserved - rd_data_resv_fld
1957  *
1958  * Field Access Macros:
1959  *
1960  */
1961 /* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD register field. */
1962 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_LSB 5
1963 /* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD register field. */
1964 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_MSB 31
1965 /* The width in bits of the ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD register field. */
1966 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_WIDTH 27
1967 /* The mask used to set the ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD register field value. */
1968 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_SET_MSK 0xffffffe0
1969 /* The mask used to clear the ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD register field value. */
1970 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_CLR_MSK 0x0000001f
1971 /* The reset value of the ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD register field. */
1972 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_RESET 0x0
1973 /* Extracts the ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD field value from a register. */
1974 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_GET(value) (((value) & 0xffffffe0) >> 5)
1975 /* Produces a ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD register field value suitable for setting the register. */
1976 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_SET(value) (((value) << 5) & 0xffffffe0)
1977 
1978 #ifndef __ASSEMBLY__
1979 /*
1980  * WARNING: The C register and register group struct declarations are provided for
1981  * convenience and illustrative purposes. They should, however, be used with
1982  * caution as the C language standard provides no guarantees about the alignment or
1983  * atomicity of device memory accesses. The recommended practice for writing
1984  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1985  * alt_write_word() functions.
1986  *
1987  * The struct declaration for register ALT_QSPI_RDDATACAP.
1988  */
1989 struct ALT_QSPI_RDDATACAP_s
1990 {
1991  uint32_t byp : 1; /* Bypass */
1992  uint32_t delay : 4; /* Read Delay */
1993  const uint32_t rd_data_resv_fld : 27; /* Reserved */
1994 };
1995 
1996 /* The typedef declaration for register ALT_QSPI_RDDATACAP. */
1997 typedef volatile struct ALT_QSPI_RDDATACAP_s ALT_QSPI_RDDATACAP_t;
1998 #endif /* __ASSEMBLY__ */
1999 
2000 /* The reset value of the ALT_QSPI_RDDATACAP register. */
2001 #define ALT_QSPI_RDDATACAP_RESET 0x00000001
2002 /* The byte offset of the ALT_QSPI_RDDATACAP register from the beginning of the component. */
2003 #define ALT_QSPI_RDDATACAP_OFST 0x10
2004 
2005 /*
2006  * Register : Device Size Configuration Register - devsz
2007  *
2008  * Register Layout
2009  *
2010  * Bits | Access | Reset | Description
2011  * :--------|:-------|:------|:--------------------------------
2012  * [3:0] | RW | 0x2 | Number of address Bytes
2013  * [15:4] | RW | 0x100 | Number of Bytes per Device Page
2014  * [20:16] | RW | 0x10 | Number of Bytes per Block
2015  * [31:21] | R | 0x0 | Reserved
2016  *
2017  */
2018 /*
2019  * Field : Number of address Bytes - numaddrbytes
2020  *
2021  * Number of address bytes. A value of 0 indicates 1 byte.
2022  *
2023  * Field Access Macros:
2024  *
2025  */
2026 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */
2027 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_LSB 0
2028 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */
2029 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_MSB 3
2030 /* The width in bits of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */
2031 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_WIDTH 4
2032 /* The mask used to set the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */
2033 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET_MSK 0x0000000f
2034 /* The mask used to clear the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */
2035 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_CLR_MSK 0xfffffff0
2036 /* The reset value of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */
2037 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_RESET 0x2
2038 /* Extracts the ALT_QSPI_DEVSZ_NUMADDRBYTES field value from a register. */
2039 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_GET(value) (((value) & 0x0000000f) >> 0)
2040 /* Produces a ALT_QSPI_DEVSZ_NUMADDRBYTES register field value suitable for setting the register. */
2041 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET(value) (((value) << 0) & 0x0000000f)
2042 
2043 /*
2044  * Field : Number of Bytes per Device Page - bytesperdevicepage
2045  *
2046  * Number of bytes per device page. This is required by the controller for
2047  * performing FLASH writes up to and across page boundaries.
2048  *
2049  * Field Access Macros:
2050  *
2051  */
2052 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */
2053 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_LSB 4
2054 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */
2055 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_MSB 15
2056 /* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */
2057 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_WIDTH 12
2058 /* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */
2059 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET_MSK 0x0000fff0
2060 /* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */
2061 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_CLR_MSK 0xffff000f
2062 /* The reset value of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */
2063 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_RESET 0x100
2064 /* Extracts the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE field value from a register. */
2065 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_GET(value) (((value) & 0x0000fff0) >> 4)
2066 /* Produces a ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value suitable for setting the register. */
2067 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET(value) (((value) << 4) & 0x0000fff0)
2068 
2069 /*
2070  * Field : Number of Bytes per Block - bytespersubsector
2071  *
2072  * Number of bytes per Block. This is required by the controller for performing the
2073  * write protection logic. The number of bytes per block must be a power of 2
2074  * number.
2075  *
2076  * Field Access Macros:
2077  *
2078  */
2079 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */
2080 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_LSB 16
2081 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */
2082 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_MSB 20
2083 /* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */
2084 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_WIDTH 5
2085 /* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */
2086 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET_MSK 0x001f0000
2087 /* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */
2088 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_CLR_MSK 0xffe0ffff
2089 /* The reset value of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */
2090 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_RESET 0x10
2091 /* Extracts the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR field value from a register. */
2092 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_GET(value) (((value) & 0x001f0000) >> 16)
2093 /* Produces a ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value suitable for setting the register. */
2094 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET(value) (((value) << 16) & 0x001f0000)
2095 
2096 /*
2097  * Field : Reserved - dev_size_resv_fld
2098  *
2099  * Field Access Macros:
2100  *
2101  */
2102 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD register field. */
2103 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_LSB 21
2104 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD register field. */
2105 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_MSB 31
2106 /* The width in bits of the ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD register field. */
2107 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_WIDTH 11
2108 /* The mask used to set the ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD register field value. */
2109 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_SET_MSK 0xffe00000
2110 /* The mask used to clear the ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD register field value. */
2111 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_CLR_MSK 0x001fffff
2112 /* The reset value of the ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD register field. */
2113 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_RESET 0x0
2114 /* Extracts the ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD field value from a register. */
2115 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_GET(value) (((value) & 0xffe00000) >> 21)
2116 /* Produces a ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD register field value suitable for setting the register. */
2117 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_SET(value) (((value) << 21) & 0xffe00000)
2118 
2119 #ifndef __ASSEMBLY__
2120 /*
2121  * WARNING: The C register and register group struct declarations are provided for
2122  * convenience and illustrative purposes. They should, however, be used with
2123  * caution as the C language standard provides no guarantees about the alignment or
2124  * atomicity of device memory accesses. The recommended practice for writing
2125  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2126  * alt_write_word() functions.
2127  *
2128  * The struct declaration for register ALT_QSPI_DEVSZ.
2129  */
2130 struct ALT_QSPI_DEVSZ_s
2131 {
2132  uint32_t numaddrbytes : 4; /* Number of address Bytes */
2133  uint32_t bytesperdevicepage : 12; /* Number of Bytes per Device Page */
2134  uint32_t bytespersubsector : 5; /* Number of Bytes per Block */
2135  const uint32_t dev_size_resv_fld : 11; /* Reserved */
2136 };
2137 
2138 /* The typedef declaration for register ALT_QSPI_DEVSZ. */
2139 typedef volatile struct ALT_QSPI_DEVSZ_s ALT_QSPI_DEVSZ_t;
2140 #endif /* __ASSEMBLY__ */
2141 
2142 /* The reset value of the ALT_QSPI_DEVSZ register. */
2143 #define ALT_QSPI_DEVSZ_RESET 0x00101002
2144 /* The byte offset of the ALT_QSPI_DEVSZ register from the beginning of the component. */
2145 #define ALT_QSPI_DEVSZ_OFST 0x14
2146 
2147 /*
2148  * Register : SRAM Partition Configuration Register - srampart
2149  *
2150  * Register Layout
2151  *
2152  * Bits | Access | Reset | Description
2153  * :-------|:-------|:------|:-----------------------------
2154  * [7:0] | RW | 0x80 | Indirect Read Partition Size
2155  * [31:8] | R | 0x0 | Reserved
2156  *
2157  */
2158 /*
2159  * Field : Indirect Read Partition Size - addr
2160  *
2161  * Defines the size of the indirect read partition in the SRAM, in units of SRAM
2162  * locations. By default, half of the SRAM is reserved for indirect read operation,
2163  * and half for indirect write. The size of this register will scale with the depth
2164  * of the SRAM.
2165  *
2166  * Field Access Macros:
2167  *
2168  */
2169 /* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */
2170 #define ALT_QSPI_SRAMPART_ADDR_LSB 0
2171 /* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */
2172 #define ALT_QSPI_SRAMPART_ADDR_MSB 7
2173 /* The width in bits of the ALT_QSPI_SRAMPART_ADDR register field. */
2174 #define ALT_QSPI_SRAMPART_ADDR_WIDTH 8
2175 /* The mask used to set the ALT_QSPI_SRAMPART_ADDR register field value. */
2176 #define ALT_QSPI_SRAMPART_ADDR_SET_MSK 0x000000ff
2177 /* The mask used to clear the ALT_QSPI_SRAMPART_ADDR register field value. */
2178 #define ALT_QSPI_SRAMPART_ADDR_CLR_MSK 0xffffff00
2179 /* The reset value of the ALT_QSPI_SRAMPART_ADDR register field. */
2180 #define ALT_QSPI_SRAMPART_ADDR_RESET 0x80
2181 /* Extracts the ALT_QSPI_SRAMPART_ADDR field value from a register. */
2182 #define ALT_QSPI_SRAMPART_ADDR_GET(value) (((value) & 0x000000ff) >> 0)
2183 /* Produces a ALT_QSPI_SRAMPART_ADDR register field value suitable for setting the register. */
2184 #define ALT_QSPI_SRAMPART_ADDR_SET(value) (((value) << 0) & 0x000000ff)
2185 
2186 /*
2187  * Field : Reserved - resv_fld
2188  *
2189  * Field Access Macros:
2190  *
2191  */
2192 /* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMPART_RESV_FLD register field. */
2193 #define ALT_QSPI_SRAMPART_RESV_FLD_LSB 8
2194 /* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMPART_RESV_FLD register field. */
2195 #define ALT_QSPI_SRAMPART_RESV_FLD_MSB 31
2196 /* The width in bits of the ALT_QSPI_SRAMPART_RESV_FLD register field. */
2197 #define ALT_QSPI_SRAMPART_RESV_FLD_WIDTH 24
2198 /* The mask used to set the ALT_QSPI_SRAMPART_RESV_FLD register field value. */
2199 #define ALT_QSPI_SRAMPART_RESV_FLD_SET_MSK 0xffffff00
2200 /* The mask used to clear the ALT_QSPI_SRAMPART_RESV_FLD register field value. */
2201 #define ALT_QSPI_SRAMPART_RESV_FLD_CLR_MSK 0x000000ff
2202 /* The reset value of the ALT_QSPI_SRAMPART_RESV_FLD register field. */
2203 #define ALT_QSPI_SRAMPART_RESV_FLD_RESET 0x0
2204 /* Extracts the ALT_QSPI_SRAMPART_RESV_FLD field value from a register. */
2205 #define ALT_QSPI_SRAMPART_RESV_FLD_GET(value) (((value) & 0xffffff00) >> 8)
2206 /* Produces a ALT_QSPI_SRAMPART_RESV_FLD register field value suitable for setting the register. */
2207 #define ALT_QSPI_SRAMPART_RESV_FLD_SET(value) (((value) << 8) & 0xffffff00)
2208 
2209 #ifndef __ASSEMBLY__
2210 /*
2211  * WARNING: The C register and register group struct declarations are provided for
2212  * convenience and illustrative purposes. They should, however, be used with
2213  * caution as the C language standard provides no guarantees about the alignment or
2214  * atomicity of device memory accesses. The recommended practice for writing
2215  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2216  * alt_write_word() functions.
2217  *
2218  * The struct declaration for register ALT_QSPI_SRAMPART.
2219  */
2220 struct ALT_QSPI_SRAMPART_s
2221 {
2222  uint32_t addr : 8; /* Indirect Read Partition Size */
2223  const uint32_t resv_fld : 24; /* Reserved */
2224 };
2225 
2226 /* The typedef declaration for register ALT_QSPI_SRAMPART. */
2227 typedef volatile struct ALT_QSPI_SRAMPART_s ALT_QSPI_SRAMPART_t;
2228 #endif /* __ASSEMBLY__ */
2229 
2230 /* The reset value of the ALT_QSPI_SRAMPART register. */
2231 #define ALT_QSPI_SRAMPART_RESET 0x00000080
2232 /* The byte offset of the ALT_QSPI_SRAMPART register from the beginning of the component. */
2233 #define ALT_QSPI_SRAMPART_OFST 0x18
2234 
2235 /*
2236  * Register : Indirect AHB Address Trigger Register - indaddrtrig
2237  *
2238  * Register Layout
2239  *
2240  * Bits | Access | Reset | Description
2241  * :-------|:-------|:------|:----------------
2242  * [31:0] | RW | 0x0 | Trigger Address
2243  *
2244  */
2245 /*
2246  * Field : Trigger Address - addr
2247  *
2248  * This is the base address that will be used by the AHB controller. When the
2249  * incoming AHB read access address matches a range of addresses from this trigger
2250  * address to the trigger address + 15, then the AHB request will be completed by
2251  * fetching data from the Indirect Controllers SRAM.
2252  *
2253  * Field Access Macros:
2254  *
2255  */
2256 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */
2257 #define ALT_QSPI_INDADDRTRIG_ADDR_LSB 0
2258 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */
2259 #define ALT_QSPI_INDADDRTRIG_ADDR_MSB 31
2260 /* The width in bits of the ALT_QSPI_INDADDRTRIG_ADDR register field. */
2261 #define ALT_QSPI_INDADDRTRIG_ADDR_WIDTH 32
2262 /* The mask used to set the ALT_QSPI_INDADDRTRIG_ADDR register field value. */
2263 #define ALT_QSPI_INDADDRTRIG_ADDR_SET_MSK 0xffffffff
2264 /* The mask used to clear the ALT_QSPI_INDADDRTRIG_ADDR register field value. */
2265 #define ALT_QSPI_INDADDRTRIG_ADDR_CLR_MSK 0x00000000
2266 /* The reset value of the ALT_QSPI_INDADDRTRIG_ADDR register field. */
2267 #define ALT_QSPI_INDADDRTRIG_ADDR_RESET 0x0
2268 /* Extracts the ALT_QSPI_INDADDRTRIG_ADDR field value from a register. */
2269 #define ALT_QSPI_INDADDRTRIG_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
2270 /* Produces a ALT_QSPI_INDADDRTRIG_ADDR register field value suitable for setting the register. */
2271 #define ALT_QSPI_INDADDRTRIG_ADDR_SET(value) (((value) << 0) & 0xffffffff)
2272 
2273 #ifndef __ASSEMBLY__
2274 /*
2275  * WARNING: The C register and register group struct declarations are provided for
2276  * convenience and illustrative purposes. They should, however, be used with
2277  * caution as the C language standard provides no guarantees about the alignment or
2278  * atomicity of device memory accesses. The recommended practice for writing
2279  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2280  * alt_write_word() functions.
2281  *
2282  * The struct declaration for register ALT_QSPI_INDADDRTRIG.
2283  */
2284 struct ALT_QSPI_INDADDRTRIG_s
2285 {
2286  uint32_t addr : 32; /* Trigger Address */
2287 };
2288 
2289 /* The typedef declaration for register ALT_QSPI_INDADDRTRIG. */
2290 typedef volatile struct ALT_QSPI_INDADDRTRIG_s ALT_QSPI_INDADDRTRIG_t;
2291 #endif /* __ASSEMBLY__ */
2292 
2293 /* The reset value of the ALT_QSPI_INDADDRTRIG register. */
2294 #define ALT_QSPI_INDADDRTRIG_RESET 0x00000000
2295 /* The byte offset of the ALT_QSPI_INDADDRTRIG register from the beginning of the component. */
2296 #define ALT_QSPI_INDADDRTRIG_OFST 0x1c
2297 
2298 /*
2299  * Register : DMA Peripheral Configuration Register - dmaper
2300  *
2301  * Register Layout
2302  *
2303  * Bits | Access | Reset | Description
2304  * :--------|:-------|:------|:-----------------------
2305  * [3:0] | RW | 0x0 | Number of Single Bytes
2306  * [7:4] | R | 0x0 | Reserved
2307  * [11:8] | RW | 0x0 | Number of Burst Bytes
2308  * [31:12] | R | 0x0 | Reserved
2309  *
2310  */
2311 /*
2312  * Field : Number of Single Bytes - numsglreqbytes
2313  *
2314  * Number of bytes in a single type request on the DMA peripheral request. A
2315  * programmed value of 0 represents a single byte. This should be setup before
2316  * starting the indirect read or write operation. The actual number of bytes used
2317  * is 2**(value in this register) which will simplify implementation.
2318  *
2319  * Field Access Macros:
2320  *
2321  */
2322 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */
2323 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_LSB 0
2324 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */
2325 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_MSB 3
2326 /* The width in bits of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */
2327 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_WIDTH 4
2328 /* The mask used to set the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */
2329 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET_MSK 0x0000000f
2330 /* The mask used to clear the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */
2331 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_CLR_MSK 0xfffffff0
2332 /* The reset value of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */
2333 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_RESET 0x0
2334 /* Extracts the ALT_QSPI_DMAPER_NUMSGLREQBYTES field value from a register. */
2335 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(value) (((value) & 0x0000000f) >> 0)
2336 /* Produces a ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value suitable for setting the register. */
2337 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET(value) (((value) << 0) & 0x0000000f)
2338 
2339 /*
2340  * Field : Reserved - dma_periph_resv1_fld
2341  *
2342  * Field Access Macros:
2343  *
2344  */
2345 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD register field. */
2346 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_LSB 4
2347 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD register field. */
2348 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_MSB 7
2349 /* The width in bits of the ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD register field. */
2350 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_WIDTH 4
2351 /* The mask used to set the ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD register field value. */
2352 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_SET_MSK 0x000000f0
2353 /* The mask used to clear the ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD register field value. */
2354 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_CLR_MSK 0xffffff0f
2355 /* The reset value of the ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD register field. */
2356 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_RESET 0x0
2357 /* Extracts the ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD field value from a register. */
2358 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_GET(value) (((value) & 0x000000f0) >> 4)
2359 /* Produces a ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD register field value suitable for setting the register. */
2360 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_SET(value) (((value) << 4) & 0x000000f0)
2361 
2362 /*
2363  * Field : Number of Burst Bytes - numburstreqbytes
2364  *
2365  * Number of bytes in a burst type request on the DMA peripheral request. A
2366  * programmed value of 0 represents a single byte. This should be setup before
2367  * starting the indirect read or write operation. The actual number of bytes used
2368  * is 2**(value in this register) which will simplify implementation.
2369  *
2370  * Field Access Macros:
2371  *
2372  */
2373 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */
2374 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_LSB 8
2375 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */
2376 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_MSB 11
2377 /* The width in bits of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */
2378 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_WIDTH 4
2379 /* The mask used to set the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */
2380 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET_MSK 0x00000f00
2381 /* The mask used to clear the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */
2382 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_CLR_MSK 0xfffff0ff
2383 /* The reset value of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */
2384 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_RESET 0x0
2385 /* Extracts the ALT_QSPI_DMAPER_NUMBURSTREQBYTES field value from a register. */
2386 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(value) (((value) & 0x00000f00) >> 8)
2387 /* Produces a ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value suitable for setting the register. */
2388 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET(value) (((value) << 8) & 0x00000f00)
2389 
2390 /*
2391  * Field : Reserved - dma_periph_resv2_fld
2392  *
2393  * Field Access Macros:
2394  *
2395  */
2396 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD register field. */
2397 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_LSB 12
2398 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD register field. */
2399 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_MSB 31
2400 /* The width in bits of the ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD register field. */
2401 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_WIDTH 20
2402 /* The mask used to set the ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD register field value. */
2403 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_SET_MSK 0xfffff000
2404 /* The mask used to clear the ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD register field value. */
2405 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_CLR_MSK 0x00000fff
2406 /* The reset value of the ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD register field. */
2407 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_RESET 0x0
2408 /* Extracts the ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD field value from a register. */
2409 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_GET(value) (((value) & 0xfffff000) >> 12)
2410 /* Produces a ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD register field value suitable for setting the register. */
2411 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_SET(value) (((value) << 12) & 0xfffff000)
2412 
2413 #ifndef __ASSEMBLY__
2414 /*
2415  * WARNING: The C register and register group struct declarations are provided for
2416  * convenience and illustrative purposes. They should, however, be used with
2417  * caution as the C language standard provides no guarantees about the alignment or
2418  * atomicity of device memory accesses. The recommended practice for writing
2419  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2420  * alt_write_word() functions.
2421  *
2422  * The struct declaration for register ALT_QSPI_DMAPER.
2423  */
2424 struct ALT_QSPI_DMAPER_s
2425 {
2426  uint32_t numsglreqbytes : 4; /* Number of Single Bytes */
2427  const uint32_t dma_periph_resv1_fld : 4; /* Reserved */
2428  uint32_t numburstreqbytes : 4; /* Number of Burst Bytes */
2429  const uint32_t dma_periph_resv2_fld : 20; /* Reserved */
2430 };
2431 
2432 /* The typedef declaration for register ALT_QSPI_DMAPER. */
2433 typedef volatile struct ALT_QSPI_DMAPER_s ALT_QSPI_DMAPER_t;
2434 #endif /* __ASSEMBLY__ */
2435 
2436 /* The reset value of the ALT_QSPI_DMAPER register. */
2437 #define ALT_QSPI_DMAPER_RESET 0x00000000
2438 /* The byte offset of the ALT_QSPI_DMAPER register from the beginning of the component. */
2439 #define ALT_QSPI_DMAPER_OFST 0x20
2440 
2441 /*
2442  * Register : Remap Address Register - remapaddr
2443  *
2444  * Register Layout
2445  *
2446  * Bits | Access | Reset | Description
2447  * :-------|:-------|:------|:-----------------------
2448  * [31:0] | RW | 0x0 | Remap Address Register
2449  *
2450  */
2451 /*
2452  * Field : Remap Address Register - value
2453  *
2454  * This register is used to remap an incoming AHB address to a different address
2455  * used by the FLASH device.
2456  *
2457  * Field Access Macros:
2458  *
2459  */
2460 /* The Least Significant Bit (LSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */
2461 #define ALT_QSPI_REMAPADDR_VALUE_LSB 0
2462 /* The Most Significant Bit (MSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */
2463 #define ALT_QSPI_REMAPADDR_VALUE_MSB 31
2464 /* The width in bits of the ALT_QSPI_REMAPADDR_VALUE register field. */
2465 #define ALT_QSPI_REMAPADDR_VALUE_WIDTH 32
2466 /* The mask used to set the ALT_QSPI_REMAPADDR_VALUE register field value. */
2467 #define ALT_QSPI_REMAPADDR_VALUE_SET_MSK 0xffffffff
2468 /* The mask used to clear the ALT_QSPI_REMAPADDR_VALUE register field value. */
2469 #define ALT_QSPI_REMAPADDR_VALUE_CLR_MSK 0x00000000
2470 /* The reset value of the ALT_QSPI_REMAPADDR_VALUE register field. */
2471 #define ALT_QSPI_REMAPADDR_VALUE_RESET 0x0
2472 /* Extracts the ALT_QSPI_REMAPADDR_VALUE field value from a register. */
2473 #define ALT_QSPI_REMAPADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
2474 /* Produces a ALT_QSPI_REMAPADDR_VALUE register field value suitable for setting the register. */
2475 #define ALT_QSPI_REMAPADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff)
2476 
2477 #ifndef __ASSEMBLY__
2478 /*
2479  * WARNING: The C register and register group struct declarations are provided for
2480  * convenience and illustrative purposes. They should, however, be used with
2481  * caution as the C language standard provides no guarantees about the alignment or
2482  * atomicity of device memory accesses. The recommended practice for writing
2483  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2484  * alt_write_word() functions.
2485  *
2486  * The struct declaration for register ALT_QSPI_REMAPADDR.
2487  */
2488 struct ALT_QSPI_REMAPADDR_s
2489 {
2490  uint32_t value : 32; /* Remap Address Register */
2491 };
2492 
2493 /* The typedef declaration for register ALT_QSPI_REMAPADDR. */
2494 typedef volatile struct ALT_QSPI_REMAPADDR_s ALT_QSPI_REMAPADDR_t;
2495 #endif /* __ASSEMBLY__ */
2496 
2497 /* The reset value of the ALT_QSPI_REMAPADDR register. */
2498 #define ALT_QSPI_REMAPADDR_RESET 0x00000000
2499 /* The byte offset of the ALT_QSPI_REMAPADDR register from the beginning of the component. */
2500 #define ALT_QSPI_REMAPADDR_OFST 0x24
2501 
2502 /*
2503  * Register : Mode Bit Configuration Register - modebit
2504  *
2505  * Register Layout
2506  *
2507  * Bits | Access | Reset | Description
2508  * :-------|:-------|:------|:------------
2509  * [7:0] | RW | 0x0 | Mode
2510  * [31:8] | R | 0x0 | Reserved
2511  *
2512  */
2513 /*
2514  * Field : Mode - mode
2515  *
2516  * These are the 8 mode bits that are sent to the device following the address
2517  * bytes if mode bit transmission has been enabled.
2518  *
2519  * Field Access Macros:
2520  *
2521  */
2522 /* The Least Significant Bit (LSB) position of the ALT_QSPI_MODBIT_MOD register field. */
2523 #define ALT_QSPI_MODBIT_MOD_LSB 0
2524 /* The Most Significant Bit (MSB) position of the ALT_QSPI_MODBIT_MOD register field. */
2525 #define ALT_QSPI_MODBIT_MOD_MSB 7
2526 /* The width in bits of the ALT_QSPI_MODBIT_MOD register field. */
2527 #define ALT_QSPI_MODBIT_MOD_WIDTH 8
2528 /* The mask used to set the ALT_QSPI_MODBIT_MOD register field value. */
2529 #define ALT_QSPI_MODBIT_MOD_SET_MSK 0x000000ff
2530 /* The mask used to clear the ALT_QSPI_MODBIT_MOD register field value. */
2531 #define ALT_QSPI_MODBIT_MOD_CLR_MSK 0xffffff00
2532 /* The reset value of the ALT_QSPI_MODBIT_MOD register field. */
2533 #define ALT_QSPI_MODBIT_MOD_RESET 0x0
2534 /* Extracts the ALT_QSPI_MODBIT_MOD field value from a register. */
2535 #define ALT_QSPI_MODBIT_MOD_GET(value) (((value) & 0x000000ff) >> 0)
2536 /* Produces a ALT_QSPI_MODBIT_MOD register field value suitable for setting the register. */
2537 #define ALT_QSPI_MODBIT_MOD_SET(value) (((value) << 0) & 0x000000ff)
2538 
2539 /*
2540  * Field : Reserved - mode_resv_fld
2541  *
2542  * Field Access Macros:
2543  *
2544  */
2545 /* The Least Significant Bit (LSB) position of the ALT_QSPI_MODBIT_MOD_RESV_FLD register field. */
2546 #define ALT_QSPI_MODBIT_MOD_RESV_FLD_LSB 8
2547 /* The Most Significant Bit (MSB) position of the ALT_QSPI_MODBIT_MOD_RESV_FLD register field. */
2548 #define ALT_QSPI_MODBIT_MOD_RESV_FLD_MSB 31
2549 /* The width in bits of the ALT_QSPI_MODBIT_MOD_RESV_FLD register field. */
2550 #define ALT_QSPI_MODBIT_MOD_RESV_FLD_WIDTH 24
2551 /* The mask used to set the ALT_QSPI_MODBIT_MOD_RESV_FLD register field value. */
2552 #define ALT_QSPI_MODBIT_MOD_RESV_FLD_SET_MSK 0xffffff00
2553 /* The mask used to clear the ALT_QSPI_MODBIT_MOD_RESV_FLD register field value. */
2554 #define ALT_QSPI_MODBIT_MOD_RESV_FLD_CLR_MSK 0x000000ff
2555 /* The reset value of the ALT_QSPI_MODBIT_MOD_RESV_FLD register field. */
2556 #define ALT_QSPI_MODBIT_MOD_RESV_FLD_RESET 0x0
2557 /* Extracts the ALT_QSPI_MODBIT_MOD_RESV_FLD field value from a register. */
2558 #define ALT_QSPI_MODBIT_MOD_RESV_FLD_GET(value) (((value) & 0xffffff00) >> 8)
2559 /* Produces a ALT_QSPI_MODBIT_MOD_RESV_FLD register field value suitable for setting the register. */
2560 #define ALT_QSPI_MODBIT_MOD_RESV_FLD_SET(value) (((value) << 8) & 0xffffff00)
2561 
2562 #ifndef __ASSEMBLY__
2563 /*
2564  * WARNING: The C register and register group struct declarations are provided for
2565  * convenience and illustrative purposes. They should, however, be used with
2566  * caution as the C language standard provides no guarantees about the alignment or
2567  * atomicity of device memory accesses. The recommended practice for writing
2568  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2569  * alt_write_word() functions.
2570  *
2571  * The struct declaration for register ALT_QSPI_MODBIT.
2572  */
2573 struct ALT_QSPI_MODBIT_s
2574 {
2575  uint32_t mode : 8; /* Mode */
2576  const uint32_t mode_resv_fld : 24; /* Reserved */
2577 };
2578 
2579 /* The typedef declaration for register ALT_QSPI_MODBIT. */
2580 typedef volatile struct ALT_QSPI_MODBIT_s ALT_QSPI_MODBIT_t;
2581 #endif /* __ASSEMBLY__ */
2582 
2583 /* The reset value of the ALT_QSPI_MODBIT register. */
2584 #define ALT_QSPI_MODBIT_RESET 0x00000000
2585 /* The byte offset of the ALT_QSPI_MODBIT register from the beginning of the component. */
2586 #define ALT_QSPI_MODBIT_OFST 0x28
2587 
2588 /*
2589  * Register : SRAM Fill Register - sramfill
2590  *
2591  * Register Layout
2592  *
2593  * Bits | Access | Reset | Description
2594  * :--------|:-------|:------|:-------------------------------------------
2595  * [15:0] | R | 0x0 | SRAM Fill Level (Indirect Read Partition)
2596  * [31:16] | R | 0x0 | SRAM Fill Level (Indirect Write Partition)
2597  *
2598  */
2599 /*
2600  * Field : SRAM Fill Level (Indirect Read Partition) - indrdpart
2601  *
2602  * Identifies the current fill level of the SRAM Indirect Read partition
2603  *
2604  * Field Access Macros:
2605  *
2606  */
2607 /* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */
2608 #define ALT_QSPI_SRAMFILL_INDRDPART_LSB 0
2609 /* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */
2610 #define ALT_QSPI_SRAMFILL_INDRDPART_MSB 15
2611 /* The width in bits of the ALT_QSPI_SRAMFILL_INDRDPART register field. */
2612 #define ALT_QSPI_SRAMFILL_INDRDPART_WIDTH 16
2613 /* The mask used to set the ALT_QSPI_SRAMFILL_INDRDPART register field value. */
2614 #define ALT_QSPI_SRAMFILL_INDRDPART_SET_MSK 0x0000ffff
2615 /* The mask used to clear the ALT_QSPI_SRAMFILL_INDRDPART register field value. */
2616 #define ALT_QSPI_SRAMFILL_INDRDPART_CLR_MSK 0xffff0000
2617 /* The reset value of the ALT_QSPI_SRAMFILL_INDRDPART register field. */
2618 #define ALT_QSPI_SRAMFILL_INDRDPART_RESET 0x0
2619 /* Extracts the ALT_QSPI_SRAMFILL_INDRDPART field value from a register. */
2620 #define ALT_QSPI_SRAMFILL_INDRDPART_GET(value) (((value) & 0x0000ffff) >> 0)
2621 /* Produces a ALT_QSPI_SRAMFILL_INDRDPART register field value suitable for setting the register. */
2622 #define ALT_QSPI_SRAMFILL_INDRDPART_SET(value) (((value) << 0) & 0x0000ffff)
2623 
2624 /*
2625  * Field : SRAM Fill Level (Indirect Write Partition) - indwrpart
2626  *
2627  * Identifies the current fill level of the SRAM Indirect Write partition
2628  *
2629  * Field Access Macros:
2630  *
2631  */
2632 /* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */
2633 #define ALT_QSPI_SRAMFILL_INDWRPART_LSB 16
2634 /* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */
2635 #define ALT_QSPI_SRAMFILL_INDWRPART_MSB 31
2636 /* The width in bits of the ALT_QSPI_SRAMFILL_INDWRPART register field. */
2637 #define ALT_QSPI_SRAMFILL_INDWRPART_WIDTH 16
2638 /* The mask used to set the ALT_QSPI_SRAMFILL_INDWRPART register field value. */
2639 #define ALT_QSPI_SRAMFILL_INDWRPART_SET_MSK 0xffff0000
2640 /* The mask used to clear the ALT_QSPI_SRAMFILL_INDWRPART register field value. */
2641 #define ALT_QSPI_SRAMFILL_INDWRPART_CLR_MSK 0x0000ffff
2642 /* The reset value of the ALT_QSPI_SRAMFILL_INDWRPART register field. */
2643 #define ALT_QSPI_SRAMFILL_INDWRPART_RESET 0x0
2644 /* Extracts the ALT_QSPI_SRAMFILL_INDWRPART field value from a register. */
2645 #define ALT_QSPI_SRAMFILL_INDWRPART_GET(value) (((value) & 0xffff0000) >> 16)
2646 /* Produces a ALT_QSPI_SRAMFILL_INDWRPART register field value suitable for setting the register. */
2647 #define ALT_QSPI_SRAMFILL_INDWRPART_SET(value) (((value) << 16) & 0xffff0000)
2648 
2649 #ifndef __ASSEMBLY__
2650 /*
2651  * WARNING: The C register and register group struct declarations are provided for
2652  * convenience and illustrative purposes. They should, however, be used with
2653  * caution as the C language standard provides no guarantees about the alignment or
2654  * atomicity of device memory accesses. The recommended practice for writing
2655  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2656  * alt_write_word() functions.
2657  *
2658  * The struct declaration for register ALT_QSPI_SRAMFILL.
2659  */
2660 struct ALT_QSPI_SRAMFILL_s
2661 {
2662  const uint32_t indrdpart : 16; /* SRAM Fill Level (Indirect Read Partition) */
2663  const uint32_t indwrpart : 16; /* SRAM Fill Level (Indirect Write Partition) */
2664 };
2665 
2666 /* The typedef declaration for register ALT_QSPI_SRAMFILL. */
2667 typedef volatile struct ALT_QSPI_SRAMFILL_s ALT_QSPI_SRAMFILL_t;
2668 #endif /* __ASSEMBLY__ */
2669 
2670 /* The reset value of the ALT_QSPI_SRAMFILL register. */
2671 #define ALT_QSPI_SRAMFILL_RESET 0x00000000
2672 /* The byte offset of the ALT_QSPI_SRAMFILL register from the beginning of the component. */
2673 #define ALT_QSPI_SRAMFILL_OFST 0x2c
2674 
2675 /*
2676  * Register : TX Threshold Register - txthresh
2677  *
2678  * Register Layout
2679  *
2680  * Bits | Access | Reset | Description
2681  * :-------|:-------|:------|:------------
2682  * [3:0] | RW | 0x1 | Level
2683  * [31:4] | R | 0x0 | Reserved
2684  *
2685  */
2686 /*
2687  * Field : Level - level
2688  *
2689  * Defines the level at which the small TX FIFO not full interrupt is generated
2690  *
2691  * Field Access Macros:
2692  *
2693  */
2694 /* The Least Significant Bit (LSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */
2695 #define ALT_QSPI_TXTHRESH_LEVEL_LSB 0
2696 /* The Most Significant Bit (MSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */
2697 #define ALT_QSPI_TXTHRESH_LEVEL_MSB 3
2698 /* The width in bits of the ALT_QSPI_TXTHRESH_LEVEL register field. */
2699 #define ALT_QSPI_TXTHRESH_LEVEL_WIDTH 4
2700 /* The mask used to set the ALT_QSPI_TXTHRESH_LEVEL register field value. */
2701 #define ALT_QSPI_TXTHRESH_LEVEL_SET_MSK 0x0000000f
2702 /* The mask used to clear the ALT_QSPI_TXTHRESH_LEVEL register field value. */
2703 #define ALT_QSPI_TXTHRESH_LEVEL_CLR_MSK 0xfffffff0
2704 /* The reset value of the ALT_QSPI_TXTHRESH_LEVEL register field. */
2705 #define ALT_QSPI_TXTHRESH_LEVEL_RESET 0x1
2706 /* Extracts the ALT_QSPI_TXTHRESH_LEVEL field value from a register. */
2707 #define ALT_QSPI_TXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
2708 /* Produces a ALT_QSPI_TXTHRESH_LEVEL register field value suitable for setting the register. */
2709 #define ALT_QSPI_TXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
2710 
2711 /*
2712  * Field : Reserved - tx_thresh_resv_fld
2713  *
2714  * Field Access Macros:
2715  *
2716  */
2717 /* The Least Significant Bit (LSB) position of the ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD register field. */
2718 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_LSB 4
2719 /* The Most Significant Bit (MSB) position of the ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD register field. */
2720 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_MSB 31
2721 /* The width in bits of the ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD register field. */
2722 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_WIDTH 28
2723 /* The mask used to set the ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD register field value. */
2724 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_SET_MSK 0xfffffff0
2725 /* The mask used to clear the ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD register field value. */
2726 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_CLR_MSK 0x0000000f
2727 /* The reset value of the ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD register field. */
2728 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_RESET 0x0
2729 /* Extracts the ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD field value from a register. */
2730 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_GET(value) (((value) & 0xfffffff0) >> 4)
2731 /* Produces a ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD register field value suitable for setting the register. */
2732 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_SET(value) (((value) << 4) & 0xfffffff0)
2733 
2734 #ifndef __ASSEMBLY__
2735 /*
2736  * WARNING: The C register and register group struct declarations are provided for
2737  * convenience and illustrative purposes. They should, however, be used with
2738  * caution as the C language standard provides no guarantees about the alignment or
2739  * atomicity of device memory accesses. The recommended practice for writing
2740  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2741  * alt_write_word() functions.
2742  *
2743  * The struct declaration for register ALT_QSPI_TXTHRESH.
2744  */
2745 struct ALT_QSPI_TXTHRESH_s
2746 {
2747  uint32_t level : 4; /* Level */
2748  const uint32_t tx_thresh_resv_fld : 28; /* Reserved */
2749 };
2750 
2751 /* The typedef declaration for register ALT_QSPI_TXTHRESH. */
2752 typedef volatile struct ALT_QSPI_TXTHRESH_s ALT_QSPI_TXTHRESH_t;
2753 #endif /* __ASSEMBLY__ */
2754 
2755 /* The reset value of the ALT_QSPI_TXTHRESH register. */
2756 #define ALT_QSPI_TXTHRESH_RESET 0x00000001
2757 /* The byte offset of the ALT_QSPI_TXTHRESH register from the beginning of the component. */
2758 #define ALT_QSPI_TXTHRESH_OFST 0x30
2759 
2760 /*
2761  * Register : RX Threshold Register - rxthresh
2762  *
2763  * Device Instruction Configuration Register
2764  *
2765  * Register Layout
2766  *
2767  * Bits | Access | Reset | Description
2768  * :-------|:-------|:------|:------------
2769  * [3:0] | RW | 0x1 | Level
2770  * [31:4] | R | 0x0 | Reserved
2771  *
2772  */
2773 /*
2774  * Field : Level - level
2775  *
2776  * Defines the level at which the small RX FIFO not empty interrupt is generated
2777  *
2778  * Field Access Macros:
2779  *
2780  */
2781 /* The Least Significant Bit (LSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */
2782 #define ALT_QSPI_RXTHRESH_LEVEL_LSB 0
2783 /* The Most Significant Bit (MSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */
2784 #define ALT_QSPI_RXTHRESH_LEVEL_MSB 3
2785 /* The width in bits of the ALT_QSPI_RXTHRESH_LEVEL register field. */
2786 #define ALT_QSPI_RXTHRESH_LEVEL_WIDTH 4
2787 /* The mask used to set the ALT_QSPI_RXTHRESH_LEVEL register field value. */
2788 #define ALT_QSPI_RXTHRESH_LEVEL_SET_MSK 0x0000000f
2789 /* The mask used to clear the ALT_QSPI_RXTHRESH_LEVEL register field value. */
2790 #define ALT_QSPI_RXTHRESH_LEVEL_CLR_MSK 0xfffffff0
2791 /* The reset value of the ALT_QSPI_RXTHRESH_LEVEL register field. */
2792 #define ALT_QSPI_RXTHRESH_LEVEL_RESET 0x1
2793 /* Extracts the ALT_QSPI_RXTHRESH_LEVEL field value from a register. */
2794 #define ALT_QSPI_RXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
2795 /* Produces a ALT_QSPI_RXTHRESH_LEVEL register field value suitable for setting the register. */
2796 #define ALT_QSPI_RXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
2797 
2798 /*
2799  * Field : Reserved - rx_thresh_resv_fld
2800  *
2801  * Field Access Macros:
2802  *
2803  */
2804 /* The Least Significant Bit (LSB) position of the ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD register field. */
2805 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_LSB 4
2806 /* The Most Significant Bit (MSB) position of the ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD register field. */
2807 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_MSB 31
2808 /* The width in bits of the ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD register field. */
2809 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_WIDTH 28
2810 /* The mask used to set the ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD register field value. */
2811 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_SET_MSK 0xfffffff0
2812 /* The mask used to clear the ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD register field value. */
2813 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_CLR_MSK 0x0000000f
2814 /* The reset value of the ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD register field. */
2815 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_RESET 0x0
2816 /* Extracts the ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD field value from a register. */
2817 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_GET(value) (((value) & 0xfffffff0) >> 4)
2818 /* Produces a ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD register field value suitable for setting the register. */
2819 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_SET(value) (((value) << 4) & 0xfffffff0)
2820 
2821 #ifndef __ASSEMBLY__
2822 /*
2823  * WARNING: The C register and register group struct declarations are provided for
2824  * convenience and illustrative purposes. They should, however, be used with
2825  * caution as the C language standard provides no guarantees about the alignment or
2826  * atomicity of device memory accesses. The recommended practice for writing
2827  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2828  * alt_write_word() functions.
2829  *
2830  * The struct declaration for register ALT_QSPI_RXTHRESH.
2831  */
2832 struct ALT_QSPI_RXTHRESH_s
2833 {
2834  uint32_t level : 4; /* Level */
2835  const uint32_t rx_thresh_resv_fld : 28; /* Reserved */
2836 };
2837 
2838 /* The typedef declaration for register ALT_QSPI_RXTHRESH. */
2839 typedef volatile struct ALT_QSPI_RXTHRESH_s ALT_QSPI_RXTHRESH_t;
2840 #endif /* __ASSEMBLY__ */
2841 
2842 /* The reset value of the ALT_QSPI_RXTHRESH register. */
2843 #define ALT_QSPI_RXTHRESH_RESET 0x00000001
2844 /* The byte offset of the ALT_QSPI_RXTHRESH register from the beginning of the component. */
2845 #define ALT_QSPI_RXTHRESH_OFST 0x34
2846 
2847 /*
2848  * Register : Interrupt Status Register - irqstat
2849  *
2850  * The status fields in this register are set when the described event occurs and
2851  * the interrupt is enabled in the mask register. When any of these bit fields are
2852  * set, the interrupt output is asserted high. The fields are each cleared by
2853  * writing a 1 to the field. Note that bit fields 6 thru 10 are only valid when
2854  * legacy SPI mode is active.
2855  *
2856  * Register Layout
2857  *
2858  * Bits | Access | Reset | Description
2859  * :--------|:-------|:------|:---------------------------------
2860  * [0] | RW | 0x0 | Mode M Failure
2861  * [1] | RW | 0x0 | Underflow Detected
2862  * [2] | RW | 0x0 | Indirect Operation Complete
2863  * [3] | RW | 0x0 | Indirect Read Reject
2864  * [4] | RW | 0x0 | Protected Area Write Attempt
2865  * [5] | RW | 0x0 | Illegal AHB Access Detected
2866  * [6] | RW | 0x0 | Transfer Watermark Breach
2867  * [7] | RW | 0x0 | Receive Overflow
2868  * [8] | RW | 0x1 | Small TX FIFO not full
2869  * [9] | RW | 0x0 | Small TX FIFO full
2870  * [10] | RW | 0x0 | Small RX FIFO not empty
2871  * [11] | RW | 0x0 | Small RX FIFO full
2872  * [12] | RW | 0x0 | Indirect Read Partition overflow
2873  * [31:13] | R | 0x0 | Reserved
2874  *
2875  */
2876 /*
2877  * Field : Mode M Failure - mode_m_fail_fld
2878  *
2879  * Mode M failure indicates the voltage on pin n_ss_in is inconsistent with the SPI
2880  * mode. Set =1 if n_ss_in is low in master mode (multi-master contention). These
2881  * conditions will clear the spi_enable bit and disable the SPI. This bit is reset
2882  * only by a system reset and cleared only when this register is read. 0 : no mode
2883  * fault has been detected 1 : a mode fault has occurred
2884  *
2885  * Field Access Macros:
2886  *
2887  */
2888 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD register field. */
2889 #define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_LSB 0
2890 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD register field. */
2891 #define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_MSB 0
2892 /* The width in bits of the ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD register field. */
2893 #define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_WIDTH 1
2894 /* The mask used to set the ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD register field value. */
2895 #define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_SET_MSK 0x00000001
2896 /* The mask used to clear the ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD register field value. */
2897 #define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_CLR_MSK 0xfffffffe
2898 /* The reset value of the ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD register field. */
2899 #define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_RESET 0x0
2900 /* Extracts the ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD field value from a register. */
2901 #define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_GET(value) (((value) & 0x00000001) >> 0)
2902 /* Produces a ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD register field value suitable for setting the register. */
2903 #define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_SET(value) (((value) << 0) & 0x00000001)
2904 
2905 /*
2906  * Field : Underflow Detected - underflowdet
2907  *
2908  * 0 : no underflow has been detected 1 : underflow is detected and an attempt to
2909  * transfer data is made when the small TX FIFO is empty. This may occur when AHB
2910  * write data is being supplied too slowly to keep up with the requested write
2911  * operation This bit is reset only by a system reset and cleared only when the
2912  * register is read.
2913  *
2914  * Field Enumeration Values:
2915  *
2916  * Enum | Value | Description
2917  * :--------------------------------------------|:------|:-------------
2918  * ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW | 0x0 | No Underflow
2919  * ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW | 0x1 | Underflow
2920  *
2921  * Field Access Macros:
2922  *
2923  */
2924 /*
2925  * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET
2926  *
2927  * No Underflow
2928  */
2929 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW 0x0
2930 /*
2931  * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET
2932  *
2933  * Underflow
2934  */
2935 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW 0x1
2936 
2937 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */
2938 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_LSB 1
2939 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */
2940 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_MSB 1
2941 /* The width in bits of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */
2942 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_WIDTH 1
2943 /* The mask used to set the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */
2944 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET_MSK 0x00000002
2945 /* The mask used to clear the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */
2946 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_CLR_MSK 0xfffffffd
2947 /* The reset value of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */
2948 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_RESET 0x0
2949 /* Extracts the ALT_QSPI_IRQSTAT_UNDERFLOWDET field value from a register. */
2950 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)
2951 /* Produces a ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value suitable for setting the register. */
2952 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)
2953 
2954 /*
2955  * Field : Indirect Operation Complete - indopdone
2956  *
2957  * Controller has completed last triggered indirect operation
2958  *
2959  * Field Enumeration Values:
2960  *
2961  * Enum | Value | Description
2962  * :------------------------------------------|:------|:-----------------------------
2963  * ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP | 0x0 | No Indirect Operation
2964  * ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP | 0x1 | Completed Indirect Operation
2965  *
2966  * Field Access Macros:
2967  *
2968  */
2969 /*
2970  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE
2971  *
2972  * No Indirect Operation
2973  */
2974 #define ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP 0x0
2975 /*
2976  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE
2977  *
2978  * Completed Indirect Operation
2979  */
2980 #define ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP 0x1
2981 
2982 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */
2983 #define ALT_QSPI_IRQSTAT_INDOPDONE_LSB 2
2984 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */
2985 #define ALT_QSPI_IRQSTAT_INDOPDONE_MSB 2
2986 /* The width in bits of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */
2987 #define ALT_QSPI_IRQSTAT_INDOPDONE_WIDTH 1
2988 /* The mask used to set the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */
2989 #define ALT_QSPI_IRQSTAT_INDOPDONE_SET_MSK 0x00000004
2990 /* The mask used to clear the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */
2991 #define ALT_QSPI_IRQSTAT_INDOPDONE_CLR_MSK 0xfffffffb
2992 /* The reset value of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */
2993 #define ALT_QSPI_IRQSTAT_INDOPDONE_RESET 0x0
2994 /* Extracts the ALT_QSPI_IRQSTAT_INDOPDONE field value from a register. */
2995 #define ALT_QSPI_IRQSTAT_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)
2996 /* Produces a ALT_QSPI_IRQSTAT_INDOPDONE register field value suitable for setting the register. */
2997 #define ALT_QSPI_IRQSTAT_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)
2998 
2999 /*
3000  * Field : Indirect Read Reject - indrdreject
3001  *
3002  * Indirect operation was requested but could not be accepted. Two indirect
3003  * operations already in storage.
3004  *
3005  * Field Enumeration Values:
3006  *
3007  * Enum | Value | Description
3008  * :---------------------------------------------|:------|:-----------------------------
3009  * ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ | 0x0 | No Indirect Operation
3010  * ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ | 0x1 | Indirect Operation Requested
3011  *
3012  * Field Access Macros:
3013  *
3014  */
3015 /*
3016  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT
3017  *
3018  * No Indirect Operation
3019  */
3020 #define ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ 0x0
3021 /*
3022  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT
3023  *
3024  * Indirect Operation Requested
3025  */
3026 #define ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ 0x1
3027 
3028 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */
3029 #define ALT_QSPI_IRQSTAT_INDRDREJECT_LSB 3
3030 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */
3031 #define ALT_QSPI_IRQSTAT_INDRDREJECT_MSB 3
3032 /* The width in bits of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */
3033 #define ALT_QSPI_IRQSTAT_INDRDREJECT_WIDTH 1
3034 /* The mask used to set the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */
3035 #define ALT_QSPI_IRQSTAT_INDRDREJECT_SET_MSK 0x00000008
3036 /* The mask used to clear the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */
3037 #define ALT_QSPI_IRQSTAT_INDRDREJECT_CLR_MSK 0xfffffff7
3038 /* The reset value of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */
3039 #define ALT_QSPI_IRQSTAT_INDRDREJECT_RESET 0x0
3040 /* Extracts the ALT_QSPI_IRQSTAT_INDRDREJECT field value from a register. */
3041 #define ALT_QSPI_IRQSTAT_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)
3042 /* Produces a ALT_QSPI_IRQSTAT_INDRDREJECT register field value suitable for setting the register. */
3043 #define ALT_QSPI_IRQSTAT_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)
3044 
3045 /*
3046  * Field : Protected Area Write Attempt - protwrattempt
3047  *
3048  * Write to protected area was attempted and rejected.
3049  *
3050  * Field Enumeration Values:
3051  *
3052  * Enum | Value | Description
3053  * :------------------------------------------|:------|:--------------------------------
3054  * ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT | 0x0 | No Write Attempt
3055  * ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT | 0x1 | Write Attempt to protected area
3056  *
3057  * Field Access Macros:
3058  *
3059  */
3060 /*
3061  * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT
3062  *
3063  * No Write Attempt
3064  */
3065 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT 0x0
3066 /*
3067  * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT
3068  *
3069  * Write Attempt to protected area
3070  */
3071 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT 0x1
3072 
3073 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */
3074 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_LSB 4
3075 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */
3076 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_MSB 4
3077 /* The width in bits of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */
3078 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_WIDTH 1
3079 /* The mask used to set the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */
3080 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET_MSK 0x00000010
3081 /* The mask used to clear the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */
3082 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_CLR_MSK 0xffffffef
3083 /* The reset value of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */
3084 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_RESET 0x0
3085 /* Extracts the ALT_QSPI_IRQSTAT_PROTWRATTEMPT field value from a register. */
3086 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)
3087 /* Produces a ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value suitable for setting the register. */
3088 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)
3089 
3090 /*
3091  * Field : Illegal AHB Access Detected - illegalacc
3092  *
3093  * Illegal AHB access has been detected. AHB wrapping bursts and the use of
3094  * SPLIT/RETRY accesses will cause this error interrupt to trigger.
3095  *
3096  * Field Enumeration Values:
3097  *
3098  * Enum | Value | Description
3099  * :-------------------------------------------|:------|:-----------------------
3100  * ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB | 0x0 | No Illegal AHB attempt
3101  * ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB | 0x1 | Illegal AHB attempt
3102  *
3103  * Field Access Macros:
3104  *
3105  */
3106 /*
3107  * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC
3108  *
3109  * No Illegal AHB attempt
3110  */
3111 #define ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB 0x0
3112 /*
3113  * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC
3114  *
3115  * Illegal AHB attempt
3116  */
3117 #define ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB 0x1
3118 
3119 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */
3120 #define ALT_QSPI_IRQSTAT_ILLEGALACC_LSB 5
3121 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */
3122 #define ALT_QSPI_IRQSTAT_ILLEGALACC_MSB 5
3123 /* The width in bits of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */
3124 #define ALT_QSPI_IRQSTAT_ILLEGALACC_WIDTH 1
3125 /* The mask used to set the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */
3126 #define ALT_QSPI_IRQSTAT_ILLEGALACC_SET_MSK 0x00000020
3127 /* The mask used to clear the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */
3128 #define ALT_QSPI_IRQSTAT_ILLEGALACC_CLR_MSK 0xffffffdf
3129 /* The reset value of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */
3130 #define ALT_QSPI_IRQSTAT_ILLEGALACC_RESET 0x0
3131 /* Extracts the ALT_QSPI_IRQSTAT_ILLEGALACC field value from a register. */
3132 #define ALT_QSPI_IRQSTAT_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)
3133 /* Produces a ALT_QSPI_IRQSTAT_ILLEGALACC register field value suitable for setting the register. */
3134 #define ALT_QSPI_IRQSTAT_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)
3135 
3136 /*
3137  * Field : Transfer Watermark Breach - indxfrlvl
3138  *
3139  * Indirect Transfer Watermark Level Breached
3140  *
3141  * Field Enumeration Values:
3142  *
3143  * Enum | Value | Description
3144  * :----------------------------------------|:------|:-----------------------
3145  * ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL | 0x0 | No water level reached
3146  * ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL | 0x1 | Water level reached
3147  *
3148  * Field Access Macros:
3149  *
3150  */
3151 /*
3152  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL
3153  *
3154  * No water level reached
3155  */
3156 #define ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL 0x0
3157 /*
3158  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL
3159  *
3160  * Water level reached
3161  */
3162 #define ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL 0x1
3163 
3164 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */
3165 #define ALT_QSPI_IRQSTAT_INDXFRLVL_LSB 6
3166 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */
3167 #define ALT_QSPI_IRQSTAT_INDXFRLVL_MSB 6
3168 /* The width in bits of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */
3169 #define ALT_QSPI_IRQSTAT_INDXFRLVL_WIDTH 1
3170 /* The mask used to set the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */
3171 #define ALT_QSPI_IRQSTAT_INDXFRLVL_SET_MSK 0x00000040
3172 /* The mask used to clear the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */
3173 #define ALT_QSPI_IRQSTAT_INDXFRLVL_CLR_MSK 0xffffffbf
3174 /* The reset value of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */
3175 #define ALT_QSPI_IRQSTAT_INDXFRLVL_RESET 0x0
3176 /* Extracts the ALT_QSPI_IRQSTAT_INDXFRLVL field value from a register. */
3177 #define ALT_QSPI_IRQSTAT_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)
3178 /* Produces a ALT_QSPI_IRQSTAT_INDXFRLVL register field value suitable for setting the register. */
3179 #define ALT_QSPI_IRQSTAT_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)
3180 
3181 /*
3182  * Field : Receive Overflow - rxover
3183  *
3184  * This should only occur in Legacy SPI mode. Set if an attempt is made to push the
3185  * RX FIFO when it is full. This bit is reset only by a system reset and cleared
3186  * only when this register is read. If a new push to the RX FIFO occurs coincident
3187  * with a register read this flag will remain set. 0 : no overflow has been
3188  * detected. 1 : an overflow has occurred.
3189  *
3190  * Field Enumeration Values:
3191  *
3192  * Enum | Value | Description
3193  * :------------------------------------|:------|:--------------------
3194  * ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER | 0x0 | No Receive Overflow
3195  * ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER | 0x1 | Receive Overflow
3196  *
3197  * Field Access Macros:
3198  *
3199  */
3200 /*
3201  * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER
3202  *
3203  * No Receive Overflow
3204  */
3205 #define ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER 0x0
3206 /*
3207  * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER
3208  *
3209  * Receive Overflow
3210  */
3211 #define ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER 0x1
3212 
3213 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */
3214 #define ALT_QSPI_IRQSTAT_RXOVER_LSB 7
3215 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */
3216 #define ALT_QSPI_IRQSTAT_RXOVER_MSB 7
3217 /* The width in bits of the ALT_QSPI_IRQSTAT_RXOVER register field. */
3218 #define ALT_QSPI_IRQSTAT_RXOVER_WIDTH 1
3219 /* The mask used to set the ALT_QSPI_IRQSTAT_RXOVER register field value. */
3220 #define ALT_QSPI_IRQSTAT_RXOVER_SET_MSK 0x00000080
3221 /* The mask used to clear the ALT_QSPI_IRQSTAT_RXOVER register field value. */
3222 #define ALT_QSPI_IRQSTAT_RXOVER_CLR_MSK 0xffffff7f
3223 /* The reset value of the ALT_QSPI_IRQSTAT_RXOVER register field. */
3224 #define ALT_QSPI_IRQSTAT_RXOVER_RESET 0x0
3225 /* Extracts the ALT_QSPI_IRQSTAT_RXOVER field value from a register. */
3226 #define ALT_QSPI_IRQSTAT_RXOVER_GET(value) (((value) & 0x00000080) >> 7)
3227 /* Produces a ALT_QSPI_IRQSTAT_RXOVER register field value suitable for setting the register. */
3228 #define ALT_QSPI_IRQSTAT_RXOVER_SET(value) (((value) << 7) & 0x00000080)
3229 
3230 /*
3231  * Field : Small TX FIFO not full - txthreshcmp
3232  *
3233  * Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has >=
3234  * THRESHOLD entries, 1 : FIFO has less than THRESHOLD entries
3235  *
3236  * Field Enumeration Values:
3237  *
3238  * Enum | Value | Description
3239  * :----------------------------------|:------|:-----------------------------
3240  * ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT | 0x0 | FIFO has > TXTHRESH entries
3241  * ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE | 0x1 | FIFO has <= TXTHRESH entries
3242  *
3243  * Field Access Macros:
3244  *
3245  */
3246 /*
3247  * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP
3248  *
3249  * FIFO has > TXTHRESH entries
3250  */
3251 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT 0x0
3252 /*
3253  * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP
3254  *
3255  * FIFO has <= TXTHRESH entries
3256  */
3257 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE 0x1
3258 
3259 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */
3260 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_LSB 8
3261 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */
3262 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_MSB 8
3263 /* The width in bits of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */
3264 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_WIDTH 1
3265 /* The mask used to set the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */
3266 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET_MSK 0x00000100
3267 /* The mask used to clear the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */
3268 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_CLR_MSK 0xfffffeff
3269 /* The reset value of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */
3270 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_RESET 0x1
3271 /* Extracts the ALT_QSPI_IRQSTAT_TXTHRESHCMP field value from a register. */
3272 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)
3273 /* Produces a ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value suitable for setting the register. */
3274 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)
3275 
3276 /*
3277  * Field : Small TX FIFO full - txfull
3278  *
3279  * Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full,
3280  * 1 : FIFO is full
3281  *
3282  * Field Enumeration Values:
3283  *
3284  * Enum | Value | Description
3285  * :----------------------------------|:------|:-----------------------
3286  * ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL | 0x0 | Transmit FIFO Not Full
3287  * ALT_QSPI_IRQSTAT_TXFULL_E_FULL | 0x1 | Transmit FIFO Full
3288  *
3289  * Field Access Macros:
3290  *
3291  */
3292 /*
3293  * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL
3294  *
3295  * Transmit FIFO Not Full
3296  */
3297 #define ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL 0x0
3298 /*
3299  * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL
3300  *
3301  * Transmit FIFO Full
3302  */
3303 #define ALT_QSPI_IRQSTAT_TXFULL_E_FULL 0x1
3304 
3305 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */
3306 #define ALT_QSPI_IRQSTAT_TXFULL_LSB 9
3307 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */
3308 #define ALT_QSPI_IRQSTAT_TXFULL_MSB 9
3309 /* The width in bits of the ALT_QSPI_IRQSTAT_TXFULL register field. */
3310 #define ALT_QSPI_IRQSTAT_TXFULL_WIDTH 1
3311 /* The mask used to set the ALT_QSPI_IRQSTAT_TXFULL register field value. */
3312 #define ALT_QSPI_IRQSTAT_TXFULL_SET_MSK 0x00000200
3313 /* The mask used to clear the ALT_QSPI_IRQSTAT_TXFULL register field value. */
3314 #define ALT_QSPI_IRQSTAT_TXFULL_CLR_MSK 0xfffffdff
3315 /* The reset value of the ALT_QSPI_IRQSTAT_TXFULL register field. */
3316 #define ALT_QSPI_IRQSTAT_TXFULL_RESET 0x0
3317 /* Extracts the ALT_QSPI_IRQSTAT_TXFULL field value from a register. */
3318 #define ALT_QSPI_IRQSTAT_TXFULL_GET(value) (((value) & 0x00000200) >> 9)
3319 /* Produces a ALT_QSPI_IRQSTAT_TXFULL register field value suitable for setting the register. */
3320 #define ALT_QSPI_IRQSTAT_TXFULL_SET(value) (((value) << 9) & 0x00000200)
3321 
3322 /*
3323  * Field : Small RX FIFO not empty - rxthreshcmp
3324  *
3325  * Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has less than
3326  * RX THRESHOLD entries, 1 : FIFO has >= THRESHOLD entries
3327  *
3328  * Field Enumeration Values:
3329  *
3330  * Enum | Value | Description
3331  * :----------------------------------|:------|:-----------------------------
3332  * ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE | 0x0 | FIFO has <= RXTHRESH entries
3333  * ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT | 0x1 | FIFO has > RXTHRESH entries
3334  *
3335  * Field Access Macros:
3336  *
3337  */
3338 /*
3339  * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP
3340  *
3341  * FIFO has <= RXTHRESH entries
3342  */
3343 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE 0x0
3344 /*
3345  * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP
3346  *
3347  * FIFO has > RXTHRESH entries
3348  */
3349 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT 0x1
3350 
3351 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */
3352 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_LSB 10
3353 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */
3354 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_MSB 10
3355 /* The width in bits of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */
3356 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_WIDTH 1
3357 /* The mask used to set the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */
3358 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET_MSK 0x00000400
3359 /* The mask used to clear the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */
3360 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_CLR_MSK 0xfffffbff
3361 /* The reset value of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */
3362 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_RESET 0x0
3363 /* Extracts the ALT_QSPI_IRQSTAT_RXTHRESHCMP field value from a register. */
3364 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)
3365 /* Produces a ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value suitable for setting the register. */
3366 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)
3367 
3368 /*
3369  * Field : Small RX FIFO full - rxfull
3370  *
3371  * Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full 1
3372  * : FIFO is full
3373  *
3374  * Field Enumeration Values:
3375  *
3376  * Enum | Value | Description
3377  * :----------------------------------|:------|:----------------------
3378  * ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL | 0x0 | Receive FIFO Not Full
3379  * ALT_QSPI_IRQSTAT_RXFULL_E_FULL | 0x1 | Receive FIFO Full
3380  *
3381  * Field Access Macros:
3382  *
3383  */
3384 /*
3385  * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL
3386  *
3387  * Receive FIFO Not Full
3388  */
3389 #define ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL 0x0
3390 /*
3391  * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL
3392  *
3393  * Receive FIFO Full
3394  */
3395 #define ALT_QSPI_IRQSTAT_RXFULL_E_FULL 0x1
3396 
3397 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */
3398 #define ALT_QSPI_IRQSTAT_RXFULL_LSB 11
3399 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */
3400 #define ALT_QSPI_IRQSTAT_RXFULL_MSB 11
3401 /* The width in bits of the ALT_QSPI_IRQSTAT_RXFULL register field. */
3402 #define ALT_QSPI_IRQSTAT_RXFULL_WIDTH 1
3403 /* The mask used to set the ALT_QSPI_IRQSTAT_RXFULL register field value. */
3404 #define ALT_QSPI_IRQSTAT_RXFULL_SET_MSK 0x00000800
3405 /* The mask used to clear the ALT_QSPI_IRQSTAT_RXFULL register field value. */
3406 #define ALT_QSPI_IRQSTAT_RXFULL_CLR_MSK 0xfffff7ff
3407 /* The reset value of the ALT_QSPI_IRQSTAT_RXFULL register field. */
3408 #define ALT_QSPI_IRQSTAT_RXFULL_RESET 0x0
3409 /* Extracts the ALT_QSPI_IRQSTAT_RXFULL field value from a register. */
3410 #define ALT_QSPI_IRQSTAT_RXFULL_GET(value) (((value) & 0x00000800) >> 11)
3411 /* Produces a ALT_QSPI_IRQSTAT_RXFULL register field value suitable for setting the register. */
3412 #define ALT_QSPI_IRQSTAT_RXFULL_SET(value) (((value) << 11) & 0x00000800)
3413 
3414 /*
3415  * Field : Indirect Read Partition overflow - indsramfull
3416  *
3417  * Indirect Read Partition of SRAM is full and unable to immediately complete
3418  * indirect operation
3419  *
3420  * Field Enumeration Values:
3421  *
3422  * Enum | Value | Description
3423  * :---------------------------------------------|:------|:-----------------
3424  * ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL | 0x0 | SRAM is not full
3425  * ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL | 0x1 | SRAM is full
3426  *
3427  * Field Access Macros:
3428  *
3429  */
3430 /*
3431  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL
3432  *
3433  * SRAM is not full
3434  */
3435 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL 0x0
3436 /*
3437  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL
3438  *
3439  * SRAM is full
3440  */
3441 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL 0x1
3442 
3443 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */
3444 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_LSB 12
3445 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */
3446 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_MSB 12
3447 /* The width in bits of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */
3448 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_WIDTH 1
3449 /* The mask used to set the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */
3450 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET_MSK 0x00001000
3451 /* The mask used to clear the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */
3452 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_CLR_MSK 0xffffefff
3453 /* The reset value of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */
3454 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_RESET 0x0
3455 /* Extracts the ALT_QSPI_IRQSTAT_INDSRAMFULL field value from a register. */
3456 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)
3457 /* Produces a ALT_QSPI_IRQSTAT_INDSRAMFULL register field value suitable for setting the register. */
3458 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)
3459 
3460 /*
3461  * Field : Reserved - irq_stat_resv_fld
3462  *
3463  * Field Access Macros:
3464  *
3465  */
3466 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD register field. */
3467 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_LSB 13
3468 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD register field. */
3469 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_MSB 31
3470 /* The width in bits of the ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD register field. */
3471 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_WIDTH 19
3472 /* The mask used to set the ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD register field value. */
3473 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_SET_MSK 0xffffe000
3474 /* The mask used to clear the ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD register field value. */
3475 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_CLR_MSK 0x00001fff
3476 /* The reset value of the ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD register field. */
3477 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_RESET 0x0
3478 /* Extracts the ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD field value from a register. */
3479 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_GET(value) (((value) & 0xffffe000) >> 13)
3480 /* Produces a ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD register field value suitable for setting the register. */
3481 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_SET(value) (((value) << 13) & 0xffffe000)
3482 
3483 #ifndef __ASSEMBLY__
3484 /*
3485  * WARNING: The C register and register group struct declarations are provided for
3486  * convenience and illustrative purposes. They should, however, be used with
3487  * caution as the C language standard provides no guarantees about the alignment or
3488  * atomicity of device memory accesses. The recommended practice for writing
3489  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3490  * alt_write_word() functions.
3491  *
3492  * The struct declaration for register ALT_QSPI_IRQSTAT.
3493  */
3494 struct ALT_QSPI_IRQSTAT_s
3495 {
3496  uint32_t mode_m_fail_fld : 1; /* Mode M Failure */
3497  uint32_t underflowdet : 1; /* Underflow Detected */
3498  uint32_t indopdone : 1; /* Indirect Operation Complete */
3499  uint32_t indrdreject : 1; /* Indirect Read Reject */
3500  uint32_t protwrattempt : 1; /* Protected Area Write Attempt */
3501  uint32_t illegalacc : 1; /* Illegal AHB Access Detected */
3502  uint32_t indxfrlvl : 1; /* Transfer Watermark Breach */
3503  uint32_t rxover : 1; /* Receive Overflow */
3504  uint32_t txthreshcmp : 1; /* Small TX FIFO not full */
3505  uint32_t txfull : 1; /* Small TX FIFO full */
3506  uint32_t rxthreshcmp : 1; /* Small RX FIFO not empty */
3507  uint32_t rxfull : 1; /* Small RX FIFO full */
3508  uint32_t indsramfull : 1; /* Indirect Read Partition overflow */
3509  const uint32_t irq_stat_resv_fld : 19; /* Reserved */
3510 };
3511 
3512 /* The typedef declaration for register ALT_QSPI_IRQSTAT. */
3513 typedef volatile struct ALT_QSPI_IRQSTAT_s ALT_QSPI_IRQSTAT_t;
3514 #endif /* __ASSEMBLY__ */
3515 
3516 /* The reset value of the ALT_QSPI_IRQSTAT register. */
3517 #define ALT_QSPI_IRQSTAT_RESET 0x00000100
3518 /* The byte offset of the ALT_QSPI_IRQSTAT register from the beginning of the component. */
3519 #define ALT_QSPI_IRQSTAT_OFST 0x40
3520 
3521 /*
3522  * Register : Interrupt Mask - irqmask
3523  *
3524  * 0 : the interrupt for the corresponding interrupt status register bit is
3525  * disabled. 1 : the interrupt for the corresponding interrupt status register bit
3526  * is enabled.
3527  *
3528  * Register Layout
3529  *
3530  * Bits | Access | Reset | Description
3531  * :--------|:-------|:------|:--------------------------------------
3532  * [0] | RW | 0x0 | Mode M Failure Mask
3533  * [1] | RW | 0x0 | Underflow Detected Mask
3534  * [2] | RW | 0x0 | Indirect Complete Mask
3535  * [3] | RW | 0x0 | Indirect Read Reject Mask
3536  * [4] | RW | 0x0 | Protected Area Write Attempt Mask
3537  * [5] | RW | 0x0 | Illegal Access Detected Mask
3538  * [6] | RW | 0x0 | Transfer Watermark Breach Mask
3539  * [7] | RW | 0x0 | Receive Overflow Mask
3540  * [8] | RW | 0x0 | Small TX FIFO not full Mask
3541  * [9] | RW | 0x0 | Small TX FIFO full Mask
3542  * [10] | RW | 0x0 | Small RX FIFO not empty Mask
3543  * [11] | RW | 0x0 | Small RX FIFO full Mask
3544  * [12] | RW | 0x0 | Indirect Read Partition overflow mask
3545  * [31:13] | R | 0x0 | Reserved
3546  *
3547  */
3548 /*
3549  * Field : Mode M Failure Mask - mode_m_fail_mask_fld
3550  *
3551  * Field Access Macros:
3552  *
3553  */
3554 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD register field. */
3555 #define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_LSB 0
3556 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD register field. */
3557 #define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_MSB 0
3558 /* The width in bits of the ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD register field. */
3559 #define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_WIDTH 1
3560 /* The mask used to set the ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD register field value. */
3561 #define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_SET_MSK 0x00000001
3562 /* The mask used to clear the ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD register field value. */
3563 #define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_CLR_MSK 0xfffffffe
3564 /* The reset value of the ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD register field. */
3565 #define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_RESET 0x0
3566 /* Extracts the ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD field value from a register. */
3567 #define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_GET(value) (((value) & 0x00000001) >> 0)
3568 /* Produces a ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD register field value suitable for setting the register. */
3569 #define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_SET(value) (((value) << 0) & 0x00000001)
3570 
3571 /*
3572  * Field : Underflow Detected Mask - underflowdet
3573  *
3574  * Field Enumeration Values:
3575  *
3576  * Enum | Value | Description
3577  * :------------------------------------|:------|:-----------------------------
3578  * ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD | 0x0 | Disable Interrupt by Masking
3579  * ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END | 0x1 | Enable Interrupt
3580  *
3581  * Field Access Macros:
3582  *
3583  */
3584 /*
3585  * Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET
3586  *
3587  * Disable Interrupt by Masking
3588  */
3589 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD 0x0
3590 /*
3591  * Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET
3592  *
3593  * Enable Interrupt
3594  */
3595 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END 0x1
3596 
3597 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */
3598 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_LSB 1
3599 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */
3600 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_MSB 1
3601 /* The width in bits of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */
3602 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_WIDTH 1
3603 /* The mask used to set the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value. */
3604 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET_MSK 0x00000002
3605 /* The mask used to clear the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value. */
3606 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_CLR_MSK 0xfffffffd
3607 /* The reset value of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */
3608 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_RESET 0x0
3609 /* Extracts the ALT_QSPI_IRQMSK_UNDERFLOWDET field value from a register. */
3610 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)
3611 /* Produces a ALT_QSPI_IRQMSK_UNDERFLOWDET register field value suitable for setting the register. */
3612 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)
3613 
3614 /*
3615  * Field : Indirect Complete Mask - indopdone
3616  *
3617  * Field Enumeration Values:
3618  *
3619  * Enum | Value | Description
3620  * :---------------------------------|:------|:-----------------------------
3621  * ALT_QSPI_IRQMSK_INDOPDONE_E_DISD | 0x0 | Disable Interrupt by Masking
3622  * ALT_QSPI_IRQMSK_INDOPDONE_E_END | 0x1 | Enable Interrupt
3623  *
3624  * Field Access Macros:
3625  *
3626  */
3627 /*
3628  * Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE
3629  *
3630  * Disable Interrupt by Masking
3631  */
3632 #define ALT_QSPI_IRQMSK_INDOPDONE_E_DISD 0x0
3633 /*
3634  * Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE
3635  *
3636  * Enable Interrupt
3637  */
3638 #define ALT_QSPI_IRQMSK_INDOPDONE_E_END 0x1
3639 
3640 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field. */
3641 #define ALT_QSPI_IRQMSK_INDOPDONE_LSB 2
3642 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field. */
3643 #define ALT_QSPI_IRQMSK_INDOPDONE_MSB 2
3644 /* The width in bits of the ALT_QSPI_IRQMSK_INDOPDONE register field. */
3645 #define ALT_QSPI_IRQMSK_INDOPDONE_WIDTH 1
3646 /* The mask used to set the ALT_QSPI_IRQMSK_INDOPDONE register field value. */
3647 #define ALT_QSPI_IRQMSK_INDOPDONE_SET_MSK 0x00000004
3648 /* The mask used to clear the ALT_QSPI_IRQMSK_INDOPDONE register field value. */
3649 #define ALT_QSPI_IRQMSK_INDOPDONE_CLR_MSK 0xfffffffb
3650 /* The reset value of the ALT_QSPI_IRQMSK_INDOPDONE register field. */
3651 #define ALT_QSPI_IRQMSK_INDOPDONE_RESET 0x0
3652 /* Extracts the ALT_QSPI_IRQMSK_INDOPDONE field value from a register. */
3653 #define ALT_QSPI_IRQMSK_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)
3654 /* Produces a ALT_QSPI_IRQMSK_INDOPDONE register field value suitable for setting the register. */
3655 #define ALT_QSPI_IRQMSK_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)
3656 
3657 /*
3658  * Field : Indirect Read Reject Mask - indrdreject
3659  *
3660  * Field Enumeration Values:
3661  *
3662  * Enum | Value | Description
3663  * :-----------------------------------|:------|:-----------------------------
3664  * ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD | 0x0 | Disable Interrupt by Masking
3665  * ALT_QSPI_IRQMSK_INDRDREJECT_E_END | 0x1 | Enable Interrupt
3666  *
3667  * Field Access Macros:
3668  *
3669  */
3670 /*
3671  * Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT
3672  *
3673  * Disable Interrupt by Masking
3674  */
3675 #define ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD 0x0
3676 /*
3677  * Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT
3678  *
3679  * Enable Interrupt
3680  */
3681 #define ALT_QSPI_IRQMSK_INDRDREJECT_E_END 0x1
3682 
3683 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */
3684 #define ALT_QSPI_IRQMSK_INDRDREJECT_LSB 3
3685 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */
3686 #define ALT_QSPI_IRQMSK_INDRDREJECT_MSB 3
3687 /* The width in bits of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */
3688 #define ALT_QSPI_IRQMSK_INDRDREJECT_WIDTH 1
3689 /* The mask used to set the ALT_QSPI_IRQMSK_INDRDREJECT register field value. */
3690 #define ALT_QSPI_IRQMSK_INDRDREJECT_SET_MSK 0x00000008
3691 /* The mask used to clear the ALT_QSPI_IRQMSK_INDRDREJECT register field value. */
3692 #define ALT_QSPI_IRQMSK_INDRDREJECT_CLR_MSK 0xfffffff7
3693 /* The reset value of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */
3694 #define ALT_QSPI_IRQMSK_INDRDREJECT_RESET 0x0
3695 /* Extracts the ALT_QSPI_IRQMSK_INDRDREJECT field value from a register. */
3696 #define ALT_QSPI_IRQMSK_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)
3697 /* Produces a ALT_QSPI_IRQMSK_INDRDREJECT register field value suitable for setting the register. */
3698 #define ALT_QSPI_IRQMSK_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)
3699 
3700 /*
3701  * Field : Protected Area Write Attempt Mask - protwrattempt
3702  *
3703  * Field Enumeration Values:
3704  *
3705  * Enum | Value | Description
3706  * :-------------------------------------|:------|:-----------------------------
3707  * ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD | 0x0 | Disable Interrupt by Masking
3708  * ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END | 0x1 | Enable Interrupt
3709  *
3710  * Field Access Macros:
3711  *
3712  */
3713 /*
3714  * Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT
3715  *
3716  * Disable Interrupt by Masking
3717  */
3718 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD 0x0
3719 /*
3720  * Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT
3721  *
3722  * Enable Interrupt
3723  */
3724 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END 0x1
3725 
3726 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */
3727 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_LSB 4
3728 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */
3729 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_MSB 4
3730 /* The width in bits of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */
3731 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_WIDTH 1
3732 /* The mask used to set the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value. */
3733 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET_MSK 0x00000010
3734 /* The mask used to clear the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value. */
3735 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_CLR_MSK 0xffffffef
3736 /* The reset value of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */
3737 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_RESET 0x0
3738 /* Extracts the ALT_QSPI_IRQMSK_PROTWRATTEMPT field value from a register. */
3739 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)
3740 /* Produces a ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value suitable for setting the register. */
3741 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)
3742 
3743 /*
3744  * Field : Illegal Access Detected Mask - illegalacc
3745  *
3746  * Field Enumeration Values:
3747  *
3748  * Enum | Value | Description
3749  * :----------------------------------|:------|:-----------------------------
3750  * ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD | 0x0 | Disable Interrupt by Masking
3751  * ALT_QSPI_IRQMSK_ILLEGALACC_E_END | 0x1 | Enable Interrupt
3752  *
3753  * Field Access Macros:
3754  *
3755  */
3756 /*
3757  * Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC
3758  *
3759  * Disable Interrupt by Masking
3760  */
3761 #define ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD 0x0
3762 /*
3763  * Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC
3764  *
3765  * Enable Interrupt
3766  */
3767 #define ALT_QSPI_IRQMSK_ILLEGALACC_E_END 0x1
3768 
3769 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */
3770 #define ALT_QSPI_IRQMSK_ILLEGALACC_LSB 5
3771 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */
3772 #define ALT_QSPI_IRQMSK_ILLEGALACC_MSB 5
3773 /* The width in bits of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */
3774 #define ALT_QSPI_IRQMSK_ILLEGALACC_WIDTH 1
3775 /* The mask used to set the ALT_QSPI_IRQMSK_ILLEGALACC register field value. */
3776 #define ALT_QSPI_IRQMSK_ILLEGALACC_SET_MSK 0x00000020
3777 /* The mask used to clear the ALT_QSPI_IRQMSK_ILLEGALACC register field value. */
3778 #define ALT_QSPI_IRQMSK_ILLEGALACC_CLR_MSK 0xffffffdf
3779 /* The reset value of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */
3780 #define ALT_QSPI_IRQMSK_ILLEGALACC_RESET 0x0
3781 /* Extracts the ALT_QSPI_IRQMSK_ILLEGALACC field value from a register. */
3782 #define ALT_QSPI_IRQMSK_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)
3783 /* Produces a ALT_QSPI_IRQMSK_ILLEGALACC register field value suitable for setting the register. */
3784 #define ALT_QSPI_IRQMSK_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)
3785 
3786 /*
3787  * Field : Transfer Watermark Breach Mask - indxfrlvl
3788  *
3789  * Field Enumeration Values:
3790  *
3791  * Enum | Value | Description
3792  * :---------------------------------|:------|:-----------------------------
3793  * ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD | 0x0 | Disable Interrupt by Masking
3794  * ALT_QSPI_IRQMSK_INDXFRLVL_E_END | 0x1 | Enable Interrupt
3795  *
3796  * Field Access Macros:
3797  *
3798  */
3799 /*
3800  * Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL
3801  *
3802  * Disable Interrupt by Masking
3803  */
3804 #define ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD 0x0
3805 /*
3806  * Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL
3807  *
3808  * Enable Interrupt
3809  */
3810 #define ALT_QSPI_IRQMSK_INDXFRLVL_E_END 0x1
3811 
3812 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */
3813 #define ALT_QSPI_IRQMSK_INDXFRLVL_LSB 6
3814 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */
3815 #define ALT_QSPI_IRQMSK_INDXFRLVL_MSB 6
3816 /* The width in bits of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */
3817 #define ALT_QSPI_IRQMSK_INDXFRLVL_WIDTH 1
3818 /* The mask used to set the ALT_QSPI_IRQMSK_INDXFRLVL register field value. */
3819 #define ALT_QSPI_IRQMSK_INDXFRLVL_SET_MSK 0x00000040
3820 /* The mask used to clear the ALT_QSPI_IRQMSK_INDXFRLVL register field value. */
3821 #define ALT_QSPI_IRQMSK_INDXFRLVL_CLR_MSK 0xffffffbf
3822 /* The reset value of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */
3823 #define ALT_QSPI_IRQMSK_INDXFRLVL_RESET 0x0
3824 /* Extracts the ALT_QSPI_IRQMSK_INDXFRLVL field value from a register. */
3825 #define ALT_QSPI_IRQMSK_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)
3826 /* Produces a ALT_QSPI_IRQMSK_INDXFRLVL register field value suitable for setting the register. */
3827 #define ALT_QSPI_IRQMSK_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)
3828 
3829 /*
3830  * Field : Receive Overflow Mask - rxover
3831  *
3832  * Field Enumeration Values:
3833  *
3834  * Enum | Value | Description
3835  * :------------------------------|:------|:-----------------------------
3836  * ALT_QSPI_IRQMSK_RXOVER_E_DISD | 0x0 | Disable Interrupt by Masking
3837  * ALT_QSPI_IRQMSK_RXOVER_E_END | 0x1 | Enable Interrupt
3838  *
3839  * Field Access Macros:
3840  *
3841  */
3842 /*
3843  * Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER
3844  *
3845  * Disable Interrupt by Masking
3846  */
3847 #define ALT_QSPI_IRQMSK_RXOVER_E_DISD 0x0
3848 /*
3849  * Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER
3850  *
3851  * Enable Interrupt
3852  */
3853 #define ALT_QSPI_IRQMSK_RXOVER_E_END 0x1
3854 
3855 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXOVER register field. */
3856 #define ALT_QSPI_IRQMSK_RXOVER_LSB 7
3857 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXOVER register field. */
3858 #define ALT_QSPI_IRQMSK_RXOVER_MSB 7
3859 /* The width in bits of the ALT_QSPI_IRQMSK_RXOVER register field. */
3860 #define ALT_QSPI_IRQMSK_RXOVER_WIDTH 1
3861 /* The mask used to set the ALT_QSPI_IRQMSK_RXOVER register field value. */
3862 #define ALT_QSPI_IRQMSK_RXOVER_SET_MSK 0x00000080
3863 /* The mask used to clear the ALT_QSPI_IRQMSK_RXOVER register field value. */
3864 #define ALT_QSPI_IRQMSK_RXOVER_CLR_MSK 0xffffff7f
3865 /* The reset value of the ALT_QSPI_IRQMSK_RXOVER register field. */
3866 #define ALT_QSPI_IRQMSK_RXOVER_RESET 0x0
3867 /* Extracts the ALT_QSPI_IRQMSK_RXOVER field value from a register. */
3868 #define ALT_QSPI_IRQMSK_RXOVER_GET(value) (((value) & 0x00000080) >> 7)
3869 /* Produces a ALT_QSPI_IRQMSK_RXOVER register field value suitable for setting the register. */
3870 #define ALT_QSPI_IRQMSK_RXOVER_SET(value) (((value) << 7) & 0x00000080)
3871 
3872 /*
3873  * Field : Small TX FIFO not full Mask - txthreshcmp
3874  *
3875  * Field Enumeration Values:
3876  *
3877  * Enum | Value | Description
3878  * :-----------------------------------|:------|:-----------------------------
3879  * ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD | 0x0 | Disable Interrupt by Masking
3880  * ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END | 0x1 | Enable Interrupt
3881  *
3882  * Field Access Macros:
3883  *
3884  */
3885 /*
3886  * Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP
3887  *
3888  * Disable Interrupt by Masking
3889  */
3890 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD 0x0
3891 /*
3892  * Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP
3893  *
3894  * Enable Interrupt
3895  */
3896 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END 0x1
3897 
3898 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */
3899 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_LSB 8
3900 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */
3901 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_MSB 8
3902 /* The width in bits of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */
3903 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_WIDTH 1
3904 /* The mask used to set the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value. */
3905 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET_MSK 0x00000100
3906 /* The mask used to clear the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value. */
3907 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_CLR_MSK 0xfffffeff
3908 /* The reset value of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */
3909 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_RESET 0x0
3910 /* Extracts the ALT_QSPI_IRQMSK_TXTHRESHCMP field value from a register. */
3911 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)
3912 /* Produces a ALT_QSPI_IRQMSK_TXTHRESHCMP register field value suitable for setting the register. */
3913 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)
3914 
3915 /*
3916  * Field : Small TX FIFO full Mask - txfull
3917  *
3918  * Field Enumeration Values:
3919  *
3920  * Enum | Value | Description
3921  * :------------------------------|:------|:-----------------------------
3922  * ALT_QSPI_IRQMSK_TXFULL_E_DISD | 0x0 | Disable Interrupt by Masking
3923  * ALT_QSPI_IRQMSK_TXFULL_E_END | 0x1 | Enable Interrupt
3924  *
3925  * Field Access Macros:
3926  *
3927  */
3928 /*
3929  * Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL
3930  *
3931  * Disable Interrupt by Masking
3932  */
3933 #define ALT_QSPI_IRQMSK_TXFULL_E_DISD 0x0
3934 /*
3935  * Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL
3936  *
3937  * Enable Interrupt
3938  */
3939 #define ALT_QSPI_IRQMSK_TXFULL_E_END 0x1
3940 
3941 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXFULL register field. */
3942 #define ALT_QSPI_IRQMSK_TXFULL_LSB 9
3943 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXFULL register field. */
3944 #define ALT_QSPI_IRQMSK_TXFULL_MSB 9
3945 /* The width in bits of the ALT_QSPI_IRQMSK_TXFULL register field. */
3946 #define ALT_QSPI_IRQMSK_TXFULL_WIDTH 1
3947 /* The mask used to set the ALT_QSPI_IRQMSK_TXFULL register field value. */
3948 #define ALT_QSPI_IRQMSK_TXFULL_SET_MSK 0x00000200
3949 /* The mask used to clear the ALT_QSPI_IRQMSK_TXFULL register field value. */
3950 #define ALT_QSPI_IRQMSK_TXFULL_CLR_MSK 0xfffffdff
3951 /* The reset value of the ALT_QSPI_IRQMSK_TXFULL register field. */
3952 #define ALT_QSPI_IRQMSK_TXFULL_RESET 0x0
3953 /* Extracts the ALT_QSPI_IRQMSK_TXFULL field value from a register. */
3954 #define ALT_QSPI_IRQMSK_TXFULL_GET(value) (((value) & 0x00000200) >> 9)
3955 /* Produces a ALT_QSPI_IRQMSK_TXFULL register field value suitable for setting the register. */
3956 #define ALT_QSPI_IRQMSK_TXFULL_SET(value) (((value) << 9) & 0x00000200)
3957 
3958 /*
3959  * Field : Small RX FIFO not empty Mask - rxthreshcmp
3960  *
3961  * Field Enumeration Values:
3962  *
3963  * Enum | Value | Description
3964  * :-----------------------------------|:------|:-----------------------------
3965  * ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD | 0x0 | Disable Interrupt by Masking
3966  * ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END | 0x1 | Enable Interrupt
3967  *
3968  * Field Access Macros:
3969  *
3970  */
3971 /*
3972  * Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP
3973  *
3974  * Disable Interrupt by Masking
3975  */
3976 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD 0x0
3977 /*
3978  * Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP
3979  *
3980  * Enable Interrupt
3981  */
3982 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END 0x1
3983 
3984 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */
3985 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_LSB 10
3986 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */
3987 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_MSB 10
3988 /* The width in bits of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */
3989 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_WIDTH 1
3990 /* The mask used to set the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value. */
3991 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET_MSK 0x00000400
3992 /* The mask used to clear the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value. */
3993 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_CLR_MSK 0xfffffbff
3994 /* The reset value of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */
3995 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_RESET 0x0
3996 /* Extracts the ALT_QSPI_IRQMSK_RXTHRESHCMP field value from a register. */
3997 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)
3998 /* Produces a ALT_QSPI_IRQMSK_RXTHRESHCMP register field value suitable for setting the register. */
3999 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)
4000 
4001 /*
4002  * Field : Small RX FIFO full Mask - rxfull
4003  *
4004  * Field Enumeration Values:
4005  *
4006  * Enum | Value | Description
4007  * :------------------------------|:------|:-----------------------------
4008  * ALT_QSPI_IRQMSK_RXFULL_E_DISD | 0x0 | Disable Interrupt by Masking
4009  * ALT_QSPI_IRQMSK_RXFULL_E_END | 0x1 | Enable Interrupt
4010  *
4011  * Field Access Macros:
4012  *
4013  */
4014 /*
4015  * Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL
4016  *
4017  * Disable Interrupt by Masking
4018  */
4019 #define ALT_QSPI_IRQMSK_RXFULL_E_DISD 0x0
4020 /*
4021  * Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL
4022  *
4023  * Enable Interrupt
4024  */
4025 #define ALT_QSPI_IRQMSK_RXFULL_E_END 0x1
4026 
4027 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXFULL register field. */
4028 #define ALT_QSPI_IRQMSK_RXFULL_LSB 11
4029 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXFULL register field. */
4030 #define ALT_QSPI_IRQMSK_RXFULL_MSB 11
4031 /* The width in bits of the ALT_QSPI_IRQMSK_RXFULL register field. */
4032 #define ALT_QSPI_IRQMSK_RXFULL_WIDTH 1
4033 /* The mask used to set the ALT_QSPI_IRQMSK_RXFULL register field value. */
4034 #define ALT_QSPI_IRQMSK_RXFULL_SET_MSK 0x00000800
4035 /* The mask used to clear the ALT_QSPI_IRQMSK_RXFULL register field value. */
4036 #define ALT_QSPI_IRQMSK_RXFULL_CLR_MSK 0xfffff7ff
4037 /* The reset value of the ALT_QSPI_IRQMSK_RXFULL register field. */
4038 #define ALT_QSPI_IRQMSK_RXFULL_RESET 0x0
4039 /* Extracts the ALT_QSPI_IRQMSK_RXFULL field value from a register. */
4040 #define ALT_QSPI_IRQMSK_RXFULL_GET(value) (((value) & 0x00000800) >> 11)
4041 /* Produces a ALT_QSPI_IRQMSK_RXFULL register field value suitable for setting the register. */
4042 #define ALT_QSPI_IRQMSK_RXFULL_SET(value) (((value) << 11) & 0x00000800)
4043 
4044 /*
4045  * Field : Indirect Read Partition overflow mask - indsramfull
4046  *
4047  * Field Enumeration Values:
4048  *
4049  * Enum | Value | Description
4050  * :-----------------------------------|:------|:-----------------------------
4051  * ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD | 0x0 | Disable Interrupt by Masking
4052  * ALT_QSPI_IRQMSK_INDSRAMFULL_E_END | 0x1 | Enable Interrupt
4053  *
4054  * Field Access Macros:
4055  *
4056  */
4057 /*
4058  * Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL
4059  *
4060  * Disable Interrupt by Masking
4061  */
4062 #define ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD 0x0
4063 /*
4064  * Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL
4065  *
4066  * Enable Interrupt
4067  */
4068 #define ALT_QSPI_IRQMSK_INDSRAMFULL_E_END 0x1
4069 
4070 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */
4071 #define ALT_QSPI_IRQMSK_INDSRAMFULL_LSB 12
4072 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */
4073 #define ALT_QSPI_IRQMSK_INDSRAMFULL_MSB 12
4074 /* The width in bits of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */
4075 #define ALT_QSPI_IRQMSK_INDSRAMFULL_WIDTH 1
4076 /* The mask used to set the ALT_QSPI_IRQMSK_INDSRAMFULL register field value. */
4077 #define ALT_QSPI_IRQMSK_INDSRAMFULL_SET_MSK 0x00001000
4078 /* The mask used to clear the ALT_QSPI_IRQMSK_INDSRAMFULL register field value. */
4079 #define ALT_QSPI_IRQMSK_INDSRAMFULL_CLR_MSK 0xffffefff
4080 /* The reset value of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */
4081 #define ALT_QSPI_IRQMSK_INDSRAMFULL_RESET 0x0
4082 /* Extracts the ALT_QSPI_IRQMSK_INDSRAMFULL field value from a register. */
4083 #define ALT_QSPI_IRQMSK_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)
4084 /* Produces a ALT_QSPI_IRQMSK_INDSRAMFULL register field value suitable for setting the register. */
4085 #define ALT_QSPI_IRQMSK_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)
4086 
4087 /*
4088  * Field : Reserved - irq_mask_resv_fld
4089  *
4090  * Field Access Macros:
4091  *
4092  */
4093 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD register field. */
4094 #define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_LSB 13
4095 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD register field. */
4096 #define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_MSB 31
4097 /* The width in bits of the ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD register field. */
4098 #define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_WIDTH 19
4099 /* The mask used to set the ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD register field value. */
4100 #define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_SET_MSK 0xffffe000
4101 /* The mask used to clear the ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD register field value. */
4102 #define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_CLR_MSK 0x00001fff
4103 /* The reset value of the ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD register field. */
4104 #define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_RESET 0x0
4105 /* Extracts the ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD field value from a register. */
4106 #define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_GET(value) (((value) & 0xffffe000) >> 13)
4107 /* Produces a ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD register field value suitable for setting the register. */
4108 #define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_SET(value) (((value) << 13) & 0xffffe000)
4109 
4110 #ifndef __ASSEMBLY__
4111 /*
4112  * WARNING: The C register and register group struct declarations are provided for
4113  * convenience and illustrative purposes. They should, however, be used with
4114  * caution as the C language standard provides no guarantees about the alignment or
4115  * atomicity of device memory accesses. The recommended practice for writing
4116  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4117  * alt_write_word() functions.
4118  *
4119  * The struct declaration for register ALT_QSPI_IRQMSK.
4120  */
4121 struct ALT_QSPI_IRQMSK_s
4122 {
4123  uint32_t mode_m_fail_mask_fld : 1; /* Mode M Failure Mask */
4124  uint32_t underflowdet : 1; /* Underflow Detected Mask */
4125  uint32_t indopdone : 1; /* Indirect Complete Mask */
4126  uint32_t indrdreject : 1; /* Indirect Read Reject Mask */
4127  uint32_t protwrattempt : 1; /* Protected Area Write Attempt Mask */
4128  uint32_t illegalacc : 1; /* Illegal Access Detected Mask */
4129  uint32_t indxfrlvl : 1; /* Transfer Watermark Breach Mask */
4130  uint32_t rxover : 1; /* Receive Overflow Mask */
4131  uint32_t txthreshcmp : 1; /* Small TX FIFO not full Mask */
4132  uint32_t txfull : 1; /* Small TX FIFO full Mask */
4133  uint32_t rxthreshcmp : 1; /* Small RX FIFO not empty Mask */
4134  uint32_t rxfull : 1; /* Small RX FIFO full Mask */
4135  uint32_t indsramfull : 1; /* Indirect Read Partition overflow mask */
4136  const uint32_t irq_mask_resv_fld : 19; /* Reserved */
4137 };
4138 
4139 /* The typedef declaration for register ALT_QSPI_IRQMSK. */
4140 typedef volatile struct ALT_QSPI_IRQMSK_s ALT_QSPI_IRQMSK_t;
4141 #endif /* __ASSEMBLY__ */
4142 
4143 /* The reset value of the ALT_QSPI_IRQMSK register. */
4144 #define ALT_QSPI_IRQMSK_RESET 0x00000000
4145 /* The byte offset of the ALT_QSPI_IRQMSK register from the beginning of the component. */
4146 #define ALT_QSPI_IRQMSK_OFST 0x44
4147 
4148 /*
4149  * Register : Lower Write Protection Register - lowwrprot
4150  *
4151  * Register Layout
4152  *
4153  * Bits | Access | Reset | Description
4154  * :-------|:-------|:------|:-------------
4155  * [31:0] | RW | 0x0 | Block Number
4156  *
4157  */
4158 /*
4159  * Field : Block Number - subsector
4160  *
4161  * The block number that defines the lower block in the range of blocks that is to
4162  * be locked from writing. The definition of a block in terms of number of bytes is
4163  * programmable via the Device Size Configuration register.
4164  *
4165  * Field Access Macros:
4166  *
4167  */
4168 /* The Least Significant Bit (LSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */
4169 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_LSB 0
4170 /* The Most Significant Bit (MSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */
4171 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_MSB 31
4172 /* The width in bits of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */
4173 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_WIDTH 32
4174 /* The mask used to set the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */
4175 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET_MSK 0xffffffff
4176 /* The mask used to clear the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */
4177 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_CLR_MSK 0x00000000
4178 /* The reset value of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */
4179 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_RESET 0x0
4180 /* Extracts the ALT_QSPI_LOWWRPROT_SUBSECTOR field value from a register. */
4181 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)
4182 /* Produces a ALT_QSPI_LOWWRPROT_SUBSECTOR register field value suitable for setting the register. */
4183 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)
4184 
4185 #ifndef __ASSEMBLY__
4186 /*
4187  * WARNING: The C register and register group struct declarations are provided for
4188  * convenience and illustrative purposes. They should, however, be used with
4189  * caution as the C language standard provides no guarantees about the alignment or
4190  * atomicity of device memory accesses. The recommended practice for writing
4191  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4192  * alt_write_word() functions.
4193  *
4194  * The struct declaration for register ALT_QSPI_LOWWRPROT.
4195  */
4196 struct ALT_QSPI_LOWWRPROT_s
4197 {
4198  uint32_t subsector : 32; /* Block Number */
4199 };
4200 
4201 /* The typedef declaration for register ALT_QSPI_LOWWRPROT. */
4202 typedef volatile struct ALT_QSPI_LOWWRPROT_s ALT_QSPI_LOWWRPROT_t;
4203 #endif /* __ASSEMBLY__ */
4204 
4205 /* The reset value of the ALT_QSPI_LOWWRPROT register. */
4206 #define ALT_QSPI_LOWWRPROT_RESET 0x00000000
4207 /* The byte offset of the ALT_QSPI_LOWWRPROT register from the beginning of the component. */
4208 #define ALT_QSPI_LOWWRPROT_OFST 0x50
4209 
4210 /*
4211  * Register : Upper Write Protection Register - uppwrprot
4212  *
4213  * Register Layout
4214  *
4215  * Bits | Access | Reset | Description
4216  * :-------|:-------|:------|:-------------
4217  * [31:0] | RW | 0x0 | Block Number
4218  *
4219  */
4220 /*
4221  * Field : Block Number - subsector
4222  *
4223  * The block number that defines the upper block in the range of blocks that is to
4224  * be locked from writing. The definition of a block in terms of number of bytes is
4225  * programmable via the Device Size Configuration register.
4226  *
4227  * Field Access Macros:
4228  *
4229  */
4230 /* The Least Significant Bit (LSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */
4231 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_LSB 0
4232 /* The Most Significant Bit (MSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */
4233 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_MSB 31
4234 /* The width in bits of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */
4235 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_WIDTH 32
4236 /* The mask used to set the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */
4237 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET_MSK 0xffffffff
4238 /* The mask used to clear the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */
4239 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_CLR_MSK 0x00000000
4240 /* The reset value of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */
4241 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_RESET 0x0
4242 /* Extracts the ALT_QSPI_UPPWRPROT_SUBSECTOR field value from a register. */
4243 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)
4244 /* Produces a ALT_QSPI_UPPWRPROT_SUBSECTOR register field value suitable for setting the register. */
4245 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)
4246 
4247 #ifndef __ASSEMBLY__
4248 /*
4249  * WARNING: The C register and register group struct declarations are provided for
4250  * convenience and illustrative purposes. They should, however, be used with
4251  * caution as the C language standard provides no guarantees about the alignment or
4252  * atomicity of device memory accesses. The recommended practice for writing
4253  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4254  * alt_write_word() functions.
4255  *
4256  * The struct declaration for register ALT_QSPI_UPPWRPROT.
4257  */
4258 struct ALT_QSPI_UPPWRPROT_s
4259 {
4260  uint32_t subsector : 32; /* Block Number */
4261 };
4262 
4263 /* The typedef declaration for register ALT_QSPI_UPPWRPROT. */
4264 typedef volatile struct ALT_QSPI_UPPWRPROT_s ALT_QSPI_UPPWRPROT_t;
4265 #endif /* __ASSEMBLY__ */
4266 
4267 /* The reset value of the ALT_QSPI_UPPWRPROT register. */
4268 #define ALT_QSPI_UPPWRPROT_RESET 0x00000000
4269 /* The byte offset of the ALT_QSPI_UPPWRPROT register from the beginning of the component. */
4270 #define ALT_QSPI_UPPWRPROT_OFST 0x54
4271 
4272 /*
4273  * Register : Write Protection Control Register - wrprot
4274  *
4275  * Register Layout
4276  *
4277  * Bits | Access | Reset | Description
4278  * :-------|:-------|:------|:-------------------------------
4279  * [0] | RW | 0x0 | Write Protection Inversion Bit
4280  * [1] | RW | 0x0 | Write Protection Enable Bit
4281  * [31:2] | R | 0x0 | Reserved
4282  *
4283  */
4284 /*
4285  * Field : Write Protection Inversion Bit - inv
4286  *
4287  * When set to 1, the protection region defined in the lower and upper write
4288  * protection registers is inverted meaning it is the region that the system is
4289  * permitted to write to. When set to 0, the protection region defined in the lower
4290  * and upper write protection registers is the region that the system is not
4291  * permitted to write to.
4292  *
4293  * Field Enumeration Values:
4294  *
4295  * Enum | Value | Description
4296  * :--------------------------|:------|:-------------------------
4297  * ALT_QSPI_WRPROT_INV_E_DIS | 0x0 | Write Region not allowed
4298  * ALT_QSPI_WRPROT_INV_E_EN | 0x1 | Write Region allowed
4299  *
4300  * Field Access Macros:
4301  *
4302  */
4303 /*
4304  * Enumerated value for register field ALT_QSPI_WRPROT_INV
4305  *
4306  * Write Region not allowed
4307  */
4308 #define ALT_QSPI_WRPROT_INV_E_DIS 0x0
4309 /*
4310  * Enumerated value for register field ALT_QSPI_WRPROT_INV
4311  *
4312  * Write Region allowed
4313  */
4314 #define ALT_QSPI_WRPROT_INV_E_EN 0x1
4315 
4316 /* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_INV register field. */
4317 #define ALT_QSPI_WRPROT_INV_LSB 0
4318 /* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_INV register field. */
4319 #define ALT_QSPI_WRPROT_INV_MSB 0
4320 /* The width in bits of the ALT_QSPI_WRPROT_INV register field. */
4321 #define ALT_QSPI_WRPROT_INV_WIDTH 1
4322 /* The mask used to set the ALT_QSPI_WRPROT_INV register field value. */
4323 #define ALT_QSPI_WRPROT_INV_SET_MSK 0x00000001
4324 /* The mask used to clear the ALT_QSPI_WRPROT_INV register field value. */
4325 #define ALT_QSPI_WRPROT_INV_CLR_MSK 0xfffffffe
4326 /* The reset value of the ALT_QSPI_WRPROT_INV register field. */
4327 #define ALT_QSPI_WRPROT_INV_RESET 0x0
4328 /* Extracts the ALT_QSPI_WRPROT_INV field value from a register. */
4329 #define ALT_QSPI_WRPROT_INV_GET(value) (((value) & 0x00000001) >> 0)
4330 /* Produces a ALT_QSPI_WRPROT_INV register field value suitable for setting the register. */
4331 #define ALT_QSPI_WRPROT_INV_SET(value) (((value) << 0) & 0x00000001)
4332 
4333 /*
4334  * Field : Write Protection Enable Bit - en
4335  *
4336  * When set to 1, any AHB write access with an address within the protection region
4337  * defined in the lower and upper write protection registers is rejected. An AHB
4338  * error response is generated and an interrupt source triggered. When set to 0,
4339  * the protection region is disabled.
4340  *
4341  * Field Enumeration Values:
4342  *
4343  * Enum | Value | Description
4344  * :-------------------------|:------|:---------------------------
4345  * ALT_QSPI_WRPROT_EN_E_DIS | 0x0 | Protection Region Disabled
4346  * ALT_QSPI_WRPROT_EN_E_EN | 0x1 | AHB Write Access rejected
4347  *
4348  * Field Access Macros:
4349  *
4350  */
4351 /*
4352  * Enumerated value for register field ALT_QSPI_WRPROT_EN
4353  *
4354  * Protection Region Disabled
4355  */
4356 #define ALT_QSPI_WRPROT_EN_E_DIS 0x0
4357 /*
4358  * Enumerated value for register field ALT_QSPI_WRPROT_EN
4359  *
4360  * AHB Write Access rejected
4361  */
4362 #define ALT_QSPI_WRPROT_EN_E_EN 0x1
4363 
4364 /* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_EN register field. */
4365 #define ALT_QSPI_WRPROT_EN_LSB 1
4366 /* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_EN register field. */
4367 #define ALT_QSPI_WRPROT_EN_MSB 1
4368 /* The width in bits of the ALT_QSPI_WRPROT_EN register field. */
4369 #define ALT_QSPI_WRPROT_EN_WIDTH 1
4370 /* The mask used to set the ALT_QSPI_WRPROT_EN register field value. */
4371 #define ALT_QSPI_WRPROT_EN_SET_MSK 0x00000002
4372 /* The mask used to clear the ALT_QSPI_WRPROT_EN register field value. */
4373 #define ALT_QSPI_WRPROT_EN_CLR_MSK 0xfffffffd
4374 /* The reset value of the ALT_QSPI_WRPROT_EN register field. */
4375 #define ALT_QSPI_WRPROT_EN_RESET 0x0
4376 /* Extracts the ALT_QSPI_WRPROT_EN field value from a register. */
4377 #define ALT_QSPI_WRPROT_EN_GET(value) (((value) & 0x00000002) >> 1)
4378 /* Produces a ALT_QSPI_WRPROT_EN register field value suitable for setting the register. */
4379 #define ALT_QSPI_WRPROT_EN_SET(value) (((value) << 1) & 0x00000002)
4380 
4381 /*
4382  * Field : Reserved - wr_prot_ctrl_resv_fld
4383  *
4384  * Field Access Macros:
4385  *
4386  */
4387 /* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD register field. */
4388 #define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_LSB 2
4389 /* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD register field. */
4390 #define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_MSB 31
4391 /* The width in bits of the ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD register field. */
4392 #define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_WIDTH 30
4393 /* The mask used to set the ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD register field value. */
4394 #define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_SET_MSK 0xfffffffc
4395 /* The mask used to clear the ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD register field value. */
4396 #define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_CLR_MSK 0x00000003
4397 /* The reset value of the ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD register field. */
4398 #define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_RESET 0x0
4399 /* Extracts the ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD field value from a register. */
4400 #define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_GET(value) (((value) & 0xfffffffc) >> 2)
4401 /* Produces a ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD register field value suitable for setting the register. */
4402 #define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_SET(value) (((value) << 2) & 0xfffffffc)
4403 
4404 #ifndef __ASSEMBLY__
4405 /*
4406  * WARNING: The C register and register group struct declarations are provided for
4407  * convenience and illustrative purposes. They should, however, be used with
4408  * caution as the C language standard provides no guarantees about the alignment or
4409  * atomicity of device memory accesses. The recommended practice for writing
4410  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4411  * alt_write_word() functions.
4412  *
4413  * The struct declaration for register ALT_QSPI_WRPROT.
4414  */
4415 struct ALT_QSPI_WRPROT_s
4416 {
4417  uint32_t inv : 1; /* Write Protection Inversion Bit */
4418  uint32_t en : 1; /* Write Protection Enable Bit */
4419  const uint32_t wr_prot_ctrl_resv_fld : 30; /* Reserved */
4420 };
4421 
4422 /* The typedef declaration for register ALT_QSPI_WRPROT. */
4423 typedef volatile struct ALT_QSPI_WRPROT_s ALT_QSPI_WRPROT_t;
4424 #endif /* __ASSEMBLY__ */
4425 
4426 /* The reset value of the ALT_QSPI_WRPROT register. */
4427 #define ALT_QSPI_WRPROT_RESET 0x00000000
4428 /* The byte offset of the ALT_QSPI_WRPROT register from the beginning of the component. */
4429 #define ALT_QSPI_WRPROT_OFST 0x58
4430 
4431 /*
4432  * Register : Indirect Read Transfer Control Register - indrd
4433  *
4434  * Register Layout
4435  *
4436  * Bits | Access | Reset | Description
4437  * :-------|:-------|:------|:--------------------------------
4438  * [0] | W | 0x0 | Start Indirect Read
4439  * [1] | W | 0x0 | Cancel Indirect Read
4440  * [2] | R | 0x0 | Indirect Read Status
4441  * [3] | RW | 0x0 | SRAM Full
4442  * [4] | R | 0x0 | Queued Indirect Read Operations
4443  * [5] | RW | 0x0 | Indirect Completion Status
4444  * [7:6] | R | 0x0 | Completed Indirect Operations
4445  * [31:8] | R | 0x0 | Reserved
4446  *
4447  */
4448 /*
4449  * Field : Start Indirect Read - start
4450  *
4451  * Writing a 1 to this bit will trigger an indirect read operation. The assumption
4452  * is that the indirect start address and the indirect number of bytes register is
4453  * setup before triggering the indirect read operation.
4454  *
4455  * Field Enumeration Values:
4456  *
4457  * Enum | Value | Description
4458  * :----------------------------|:------|:----------------------
4459  * ALT_QSPI_INDRD_START_E_DISD | 0x0 | No Indirect Read
4460  * ALT_QSPI_INDRD_START_E_END | 0x1 | Trigger Indirect Read
4461  *
4462  * Field Access Macros:
4463  *
4464  */
4465 /*
4466  * Enumerated value for register field ALT_QSPI_INDRD_START
4467  *
4468  * No Indirect Read
4469  */
4470 #define ALT_QSPI_INDRD_START_E_DISD 0x0
4471 /*
4472  * Enumerated value for register field ALT_QSPI_INDRD_START
4473  *
4474  * Trigger Indirect Read
4475  */
4476 #define ALT_QSPI_INDRD_START_E_END 0x1
4477 
4478 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_START register field. */
4479 #define ALT_QSPI_INDRD_START_LSB 0
4480 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_START register field. */
4481 #define ALT_QSPI_INDRD_START_MSB 0
4482 /* The width in bits of the ALT_QSPI_INDRD_START register field. */
4483 #define ALT_QSPI_INDRD_START_WIDTH 1
4484 /* The mask used to set the ALT_QSPI_INDRD_START register field value. */
4485 #define ALT_QSPI_INDRD_START_SET_MSK 0x00000001
4486 /* The mask used to clear the ALT_QSPI_INDRD_START register field value. */
4487 #define ALT_QSPI_INDRD_START_CLR_MSK 0xfffffffe
4488 /* The reset value of the ALT_QSPI_INDRD_START register field. */
4489 #define ALT_QSPI_INDRD_START_RESET 0x0
4490 /* Extracts the ALT_QSPI_INDRD_START field value from a register. */
4491 #define ALT_QSPI_INDRD_START_GET(value) (((value) & 0x00000001) >> 0)
4492 /* Produces a ALT_QSPI_INDRD_START register field value suitable for setting the register. */
4493 #define ALT_QSPI_INDRD_START_SET(value) (((value) << 0) & 0x00000001)
4494 
4495 /*
4496  * Field : Cancel Indirect Read - cancel
4497  *
4498  * Writing a 1 to this bit will cancel all ongoing indirect read operations.
4499  *
4500  * Field Enumeration Values:
4501  *
4502  * Enum | Value | Description
4503  * :---------------------------------|:------|:----------------------------
4504  * ALT_QSPI_INDRD_CANCEL_E_NOACTION | 0x0 | Do Not Cancel Indirect Read
4505  * ALT_QSPI_INDRD_CANCEL_E_CANCEL | 0x1 | Cancel Indirect Read
4506  *
4507  * Field Access Macros:
4508  *
4509  */
4510 /*
4511  * Enumerated value for register field ALT_QSPI_INDRD_CANCEL
4512  *
4513  * Do Not Cancel Indirect Read
4514  */
4515 #define ALT_QSPI_INDRD_CANCEL_E_NOACTION 0x0
4516 /*
4517  * Enumerated value for register field ALT_QSPI_INDRD_CANCEL
4518  *
4519  * Cancel Indirect Read
4520  */
4521 #define ALT_QSPI_INDRD_CANCEL_E_CANCEL 0x1
4522 
4523 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_CANCEL register field. */
4524 #define ALT_QSPI_INDRD_CANCEL_LSB 1
4525 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_CANCEL register field. */
4526 #define ALT_QSPI_INDRD_CANCEL_MSB 1
4527 /* The width in bits of the ALT_QSPI_INDRD_CANCEL register field. */
4528 #define ALT_QSPI_INDRD_CANCEL_WIDTH 1
4529 /* The mask used to set the ALT_QSPI_INDRD_CANCEL register field value. */
4530 #define ALT_QSPI_INDRD_CANCEL_SET_MSK 0x00000002
4531 /* The mask used to clear the ALT_QSPI_INDRD_CANCEL register field value. */
4532 #define ALT_QSPI_INDRD_CANCEL_CLR_MSK 0xfffffffd
4533 /* The reset value of the ALT_QSPI_INDRD_CANCEL register field. */
4534 #define ALT_QSPI_INDRD_CANCEL_RESET 0x0
4535 /* Extracts the ALT_QSPI_INDRD_CANCEL field value from a register. */
4536 #define ALT_QSPI_INDRD_CANCEL_GET(value) (((value) & 0x00000002) >> 1)
4537 /* Produces a ALT_QSPI_INDRD_CANCEL register field value suitable for setting the register. */
4538 #define ALT_QSPI_INDRD_CANCEL_SET(value) (((value) << 1) & 0x00000002)
4539 
4540 /*
4541  * Field : Indirect Read Status - rd_status
4542  *
4543  * Indirect read operation in progress (status)
4544  *
4545  * Field Enumeration Values:
4546  *
4547  * Enum | Value | Description
4548  * :----------------------------------|:------|:------------------------------
4549  * ALT_QSPI_INDRD_RD_STAT_E_NOACTION | 0x0 | No read operation in progress
4550  * ALT_QSPI_INDRD_RD_STAT_E_RDOP | 0x1 | Read Operation in progress
4551  *
4552  * Field Access Macros:
4553  *
4554  */
4555 /*
4556  * Enumerated value for register field ALT_QSPI_INDRD_RD_STAT
4557  *
4558  * No read operation in progress
4559  */
4560 #define ALT_QSPI_INDRD_RD_STAT_E_NOACTION 0x0
4561 /*
4562  * Enumerated value for register field ALT_QSPI_INDRD_RD_STAT
4563  *
4564  * Read Operation in progress
4565  */
4566 #define ALT_QSPI_INDRD_RD_STAT_E_RDOP 0x1
4567 
4568 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_STAT register field. */
4569 #define ALT_QSPI_INDRD_RD_STAT_LSB 2
4570 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_STAT register field. */
4571 #define ALT_QSPI_INDRD_RD_STAT_MSB 2
4572 /* The width in bits of the ALT_QSPI_INDRD_RD_STAT register field. */
4573 #define ALT_QSPI_INDRD_RD_STAT_WIDTH 1
4574 /* The mask used to set the ALT_QSPI_INDRD_RD_STAT register field value. */
4575 #define ALT_QSPI_INDRD_RD_STAT_SET_MSK 0x00000004
4576 /* The mask used to clear the ALT_QSPI_INDRD_RD_STAT register field value. */
4577 #define ALT_QSPI_INDRD_RD_STAT_CLR_MSK 0xfffffffb
4578 /* The reset value of the ALT_QSPI_INDRD_RD_STAT register field. */
4579 #define ALT_QSPI_INDRD_RD_STAT_RESET 0x0
4580 /* Extracts the ALT_QSPI_INDRD_RD_STAT field value from a register. */
4581 #define ALT_QSPI_INDRD_RD_STAT_GET(value) (((value) & 0x00000004) >> 2)
4582 /* Produces a ALT_QSPI_INDRD_RD_STAT register field value suitable for setting the register. */
4583 #define ALT_QSPI_INDRD_RD_STAT_SET(value) (((value) << 2) & 0x00000004)
4584 
4585 /*
4586  * Field : SRAM Full - sram_full
4587  *
4588  * SRAM full and unable to immediately complete an indirect operation. Write a 1 to
4589  * this field to clear it."; indirect operation (status)
4590  *
4591  * Field Enumeration Values:
4592  *
4593  * Enum | Value | Description
4594  * :------------------------------------|:------|:-----------------------------------
4595  * ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION | 0x0 | SRram Not Full
4596  * ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL | 0x1 | Sram Full- Cant complete operation
4597  *
4598  * Field Access Macros:
4599  *
4600  */
4601 /*
4602  * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL
4603  *
4604  * SRram Not Full
4605  */
4606 #define ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION 0x0
4607 /*
4608  * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL
4609  *
4610  * Sram Full- Cant complete operation
4611  */
4612 #define ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL 0x1
4613 
4614 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */
4615 #define ALT_QSPI_INDRD_SRAM_FULL_LSB 3
4616 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */
4617 #define ALT_QSPI_INDRD_SRAM_FULL_MSB 3
4618 /* The width in bits of the ALT_QSPI_INDRD_SRAM_FULL register field. */
4619 #define ALT_QSPI_INDRD_SRAM_FULL_WIDTH 1
4620 /* The mask used to set the ALT_QSPI_INDRD_SRAM_FULL register field value. */
4621 #define ALT_QSPI_INDRD_SRAM_FULL_SET_MSK 0x00000008
4622 /* The mask used to clear the ALT_QSPI_INDRD_SRAM_FULL register field value. */
4623 #define ALT_QSPI_INDRD_SRAM_FULL_CLR_MSK 0xfffffff7
4624 /* The reset value of the ALT_QSPI_INDRD_SRAM_FULL register field. */
4625 #define ALT_QSPI_INDRD_SRAM_FULL_RESET 0x0
4626 /* Extracts the ALT_QSPI_INDRD_SRAM_FULL field value from a register. */
4627 #define ALT_QSPI_INDRD_SRAM_FULL_GET(value) (((value) & 0x00000008) >> 3)
4628 /* Produces a ALT_QSPI_INDRD_SRAM_FULL register field value suitable for setting the register. */
4629 #define ALT_QSPI_INDRD_SRAM_FULL_SET(value) (((value) << 3) & 0x00000008)
4630 
4631 /*
4632  * Field : Queued Indirect Read Operations - rd_queued
4633  *
4634  * Two indirect read operations have been queued
4635  *
4636  * Field Enumeration Values:
4637  *
4638  * Enum | Value | Description
4639  * :----------------------------------------|:------|:---------------------
4640  * ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION | 0x0 | No Queued Read
4641  * ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD | 0x1 | Queued Indirect Read
4642  *
4643  * Field Access Macros:
4644  *
4645  */
4646 /*
4647  * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED
4648  *
4649  * No Queued Read
4650  */
4651 #define ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION 0x0
4652 /*
4653  * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED
4654  *
4655  * Queued Indirect Read
4656  */
4657 #define ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD 0x1
4658 
4659 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */
4660 #define ALT_QSPI_INDRD_RD_QUEUED_LSB 4
4661 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */
4662 #define ALT_QSPI_INDRD_RD_QUEUED_MSB 4
4663 /* The width in bits of the ALT_QSPI_INDRD_RD_QUEUED register field. */
4664 #define ALT_QSPI_INDRD_RD_QUEUED_WIDTH 1
4665 /* The mask used to set the ALT_QSPI_INDRD_RD_QUEUED register field value. */
4666 #define ALT_QSPI_INDRD_RD_QUEUED_SET_MSK 0x00000010
4667 /* The mask used to clear the ALT_QSPI_INDRD_RD_QUEUED register field value. */
4668 #define ALT_QSPI_INDRD_RD_QUEUED_CLR_MSK 0xffffffef
4669 /* The reset value of the ALT_QSPI_INDRD_RD_QUEUED register field. */
4670 #define ALT_QSPI_INDRD_RD_QUEUED_RESET 0x0
4671 /* Extracts the ALT_QSPI_INDRD_RD_QUEUED field value from a register. */
4672 #define ALT_QSPI_INDRD_RD_QUEUED_GET(value) (((value) & 0x00000010) >> 4)
4673 /* Produces a ALT_QSPI_INDRD_RD_QUEUED register field value suitable for setting the register. */
4674 #define ALT_QSPI_INDRD_RD_QUEUED_SET(value) (((value) << 4) & 0x00000010)
4675 
4676 /*
4677  * Field : Indirect Completion Status - ind_ops_done_status
4678  *
4679  * This field is set to 1 when an indirect operation has completed. Write a 1 to
4680  * this field to clear it.
4681  *
4682  * Field Enumeration Values:
4683  *
4684  * Enum | Value | Description
4685  * :--------------------------------------------|:------|:-------------------------------
4686  * ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION | 0x0 | Indirect Op Not Complete
4687  * ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP | 0x1 | Indirect Op Complete operation
4688  *
4689  * Field Access Macros:
4690  *
4691  */
4692 /*
4693  * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT
4694  *
4695  * Indirect Op Not Complete
4696  */
4697 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION 0x0
4698 /*
4699  * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT
4700  *
4701  * Indirect Op Complete operation
4702  */
4703 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP 0x1
4704 
4705 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */
4706 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_LSB 5
4707 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */
4708 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_MSB 5
4709 /* The width in bits of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */
4710 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_WIDTH 1
4711 /* The mask used to set the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value. */
4712 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK 0x00000020
4713 /* The mask used to clear the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value. */
4714 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_CLR_MSK 0xffffffdf
4715 /* The reset value of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */
4716 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_RESET 0x0
4717 /* Extracts the ALT_QSPI_INDRD_IND_OPS_DONE_STAT field value from a register. */
4718 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_GET(value) (((value) & 0x00000020) >> 5)
4719 /* Produces a ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value suitable for setting the register. */
4720 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET(value) (((value) << 5) & 0x00000020)
4721 
4722 /*
4723  * Field : Completed Indirect Operations - num_ind_ops_done
4724  *
4725  * This field contains the number of indirect operations which have been completed.
4726  * This is used in conjunction with the indirect completion status field (bit 5).
4727  * It is incremented by hardware when an indirect operation has completed. Write a
4728  * 1 to bit 5 of this register to decrement it.
4729  *
4730  * Field Access Macros:
4731  *
4732  */
4733 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */
4734 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_LSB 6
4735 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */
4736 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_MSB 7
4737 /* The width in bits of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */
4738 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_WIDTH 2
4739 /* The mask used to set the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */
4740 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET_MSK 0x000000c0
4741 /* The mask used to clear the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */
4742 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_CLR_MSK 0xffffff3f
4743 /* The reset value of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */
4744 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_RESET 0x0
4745 /* Extracts the ALT_QSPI_INDRD_NUM_IND_OPS_DONE field value from a register. */
4746 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_GET(value) (((value) & 0x000000c0) >> 6)
4747 /* Produces a ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value suitable for setting the register. */
4748 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET(value) (((value) << 6) & 0x000000c0)
4749 
4750 /*
4751  * Field : Reserved - indir_rd_xfer_resv_fld
4752  *
4753  * Field Access Macros:
4754  *
4755  */
4756 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD register field. */
4757 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_LSB 8
4758 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD register field. */
4759 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_MSB 31
4760 /* The width in bits of the ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD register field. */
4761 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_WIDTH 24
4762 /* The mask used to set the ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD register field value. */
4763 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_SET_MSK 0xffffff00
4764 /* The mask used to clear the ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD register field value. */
4765 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_CLR_MSK 0x000000ff
4766 /* The reset value of the ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD register field. */
4767 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_RESET 0x0
4768 /* Extracts the ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD field value from a register. */
4769 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_GET(value) (((value) & 0xffffff00) >> 8)
4770 /* Produces a ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD register field value suitable for setting the register. */
4771 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_SET(value) (((value) << 8) & 0xffffff00)
4772 
4773 #ifndef __ASSEMBLY__
4774 /*
4775  * WARNING: The C register and register group struct declarations are provided for
4776  * convenience and illustrative purposes. They should, however, be used with
4777  * caution as the C language standard provides no guarantees about the alignment or
4778  * atomicity of device memory accesses. The recommended practice for writing
4779  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4780  * alt_write_word() functions.
4781  *
4782  * The struct declaration for register ALT_QSPI_INDRD.
4783  */
4784 struct ALT_QSPI_INDRD_s
4785 {
4786  uint32_t start : 1; /* Start Indirect Read */
4787  uint32_t cancel : 1; /* Cancel Indirect Read */
4788  const uint32_t rd_status : 1; /* Indirect Read Status */
4789  uint32_t sram_full : 1; /* SRAM Full */
4790  const uint32_t rd_queued : 1; /* Queued Indirect Read Operations */
4791  uint32_t ind_ops_done_status : 1; /* Indirect Completion Status */
4792  const uint32_t num_ind_ops_done : 2; /* Completed Indirect Operations */
4793  const uint32_t indir_rd_xfer_resv_fld : 24; /* Reserved */
4794 };
4795 
4796 /* The typedef declaration for register ALT_QSPI_INDRD. */
4797 typedef volatile struct ALT_QSPI_INDRD_s ALT_QSPI_INDRD_t;
4798 #endif /* __ASSEMBLY__ */
4799 
4800 /* The reset value of the ALT_QSPI_INDRD register. */
4801 #define ALT_QSPI_INDRD_RESET 0x00000000
4802 /* The byte offset of the ALT_QSPI_INDRD register from the beginning of the component. */
4803 #define ALT_QSPI_INDRD_OFST 0x60
4804 
4805 /*
4806  * Register : Indirect Read Transfer Watermark Register - indrdwater
4807  *
4808  * Register Layout
4809  *
4810  * Bits | Access | Reset | Description
4811  * :-------|:-------|:------|:----------------
4812  * [31:0] | RW | 0x0 | Watermark Value
4813  *
4814  */
4815 /*
4816  * Field : Watermark Value - level
4817  *
4818  * This represents the minimum fill level of the SRAM before a DMA peripheral
4819  * access is permitted. When the SRAM fill level passes the watermark, an interrupt
4820  * is also generated. This field can be disabled by writing a value of all zeroes.
4821  *
4822  * Field Access Macros:
4823  *
4824  */
4825 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */
4826 #define ALT_QSPI_INDRDWATER_LEVEL_LSB 0
4827 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */
4828 #define ALT_QSPI_INDRDWATER_LEVEL_MSB 31
4829 /* The width in bits of the ALT_QSPI_INDRDWATER_LEVEL register field. */
4830 #define ALT_QSPI_INDRDWATER_LEVEL_WIDTH 32
4831 /* The mask used to set the ALT_QSPI_INDRDWATER_LEVEL register field value. */
4832 #define ALT_QSPI_INDRDWATER_LEVEL_SET_MSK 0xffffffff
4833 /* The mask used to clear the ALT_QSPI_INDRDWATER_LEVEL register field value. */
4834 #define ALT_QSPI_INDRDWATER_LEVEL_CLR_MSK 0x00000000
4835 /* The reset value of the ALT_QSPI_INDRDWATER_LEVEL register field. */
4836 #define ALT_QSPI_INDRDWATER_LEVEL_RESET 0x0
4837 /* Extracts the ALT_QSPI_INDRDWATER_LEVEL field value from a register. */
4838 #define ALT_QSPI_INDRDWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
4839 /* Produces a ALT_QSPI_INDRDWATER_LEVEL register field value suitable for setting the register. */
4840 #define ALT_QSPI_INDRDWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
4841 
4842 #ifndef __ASSEMBLY__
4843 /*
4844  * WARNING: The C register and register group struct declarations are provided for
4845  * convenience and illustrative purposes. They should, however, be used with
4846  * caution as the C language standard provides no guarantees about the alignment or
4847  * atomicity of device memory accesses. The recommended practice for writing
4848  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4849  * alt_write_word() functions.
4850  *
4851  * The struct declaration for register ALT_QSPI_INDRDWATER.
4852  */
4853 struct ALT_QSPI_INDRDWATER_s
4854 {
4855  uint32_t level : 32; /* Watermark Value */
4856 };
4857 
4858 /* The typedef declaration for register ALT_QSPI_INDRDWATER. */
4859 typedef volatile struct ALT_QSPI_INDRDWATER_s ALT_QSPI_INDRDWATER_t;
4860 #endif /* __ASSEMBLY__ */
4861 
4862 /* The reset value of the ALT_QSPI_INDRDWATER register. */
4863 #define ALT_QSPI_INDRDWATER_RESET 0x00000000
4864 /* The byte offset of the ALT_QSPI_INDRDWATER register from the beginning of the component. */
4865 #define ALT_QSPI_INDRDWATER_OFST 0x64
4866 
4867 /*
4868  * Register : Indirect Read Transfer Start Address Register - indrdstaddr
4869  *
4870  * Register Layout
4871  *
4872  * Bits | Access | Reset | Description
4873  * :-------|:-------|:------|:-------------------------
4874  * [31:0] | RW | 0x0 | Start of Indirect Access
4875  *
4876  */
4877 /*
4878  * Field : Start of Indirect Access - addr
4879  *
4880  * This is the start address from which the indirect access will commence its READ
4881  * operation.
4882  *
4883  * Field Access Macros:
4884  *
4885  */
4886 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */
4887 #define ALT_QSPI_INDRDSTADDR_ADDR_LSB 0
4888 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */
4889 #define ALT_QSPI_INDRDSTADDR_ADDR_MSB 31
4890 /* The width in bits of the ALT_QSPI_INDRDSTADDR_ADDR register field. */
4891 #define ALT_QSPI_INDRDSTADDR_ADDR_WIDTH 32
4892 /* The mask used to set the ALT_QSPI_INDRDSTADDR_ADDR register field value. */
4893 #define ALT_QSPI_INDRDSTADDR_ADDR_SET_MSK 0xffffffff
4894 /* The mask used to clear the ALT_QSPI_INDRDSTADDR_ADDR register field value. */
4895 #define ALT_QSPI_INDRDSTADDR_ADDR_CLR_MSK 0x00000000
4896 /* The reset value of the ALT_QSPI_INDRDSTADDR_ADDR register field. */
4897 #define ALT_QSPI_INDRDSTADDR_ADDR_RESET 0x0
4898 /* Extracts the ALT_QSPI_INDRDSTADDR_ADDR field value from a register. */
4899 #define ALT_QSPI_INDRDSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4900 /* Produces a ALT_QSPI_INDRDSTADDR_ADDR register field value suitable for setting the register. */
4901 #define ALT_QSPI_INDRDSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4902 
4903 #ifndef __ASSEMBLY__
4904 /*
4905  * WARNING: The C register and register group struct declarations are provided for
4906  * convenience and illustrative purposes. They should, however, be used with
4907  * caution as the C language standard provides no guarantees about the alignment or
4908  * atomicity of device memory accesses. The recommended practice for writing
4909  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4910  * alt_write_word() functions.
4911  *
4912  * The struct declaration for register ALT_QSPI_INDRDSTADDR.
4913  */
4914 struct ALT_QSPI_INDRDSTADDR_s
4915 {
4916  uint32_t addr : 32; /* Start of Indirect Access */
4917 };
4918 
4919 /* The typedef declaration for register ALT_QSPI_INDRDSTADDR. */
4920 typedef volatile struct ALT_QSPI_INDRDSTADDR_s ALT_QSPI_INDRDSTADDR_t;
4921 #endif /* __ASSEMBLY__ */
4922 
4923 /* The reset value of the ALT_QSPI_INDRDSTADDR register. */
4924 #define ALT_QSPI_INDRDSTADDR_RESET 0x00000000
4925 /* The byte offset of the ALT_QSPI_INDRDSTADDR register from the beginning of the component. */
4926 #define ALT_QSPI_INDRDSTADDR_OFST 0x68
4927 
4928 /*
4929  * Register : Indirect Read Transfer Number Bytes Register - indrdcnt
4930  *
4931  * Register Layout
4932  *
4933  * Bits | Access | Reset | Description
4934  * :-------|:-------|:------|:-------------------------
4935  * [31:0] | RW | 0x0 | Indirect Number of Bytes
4936  *
4937  */
4938 /*
4939  * Field : Indirect Number of Bytes - value
4940  *
4941  * This is the number of bytes that the indirect access will consume. This can be
4942  * bigger than the configured size of SRAM.
4943  *
4944  * Field Access Macros:
4945  *
4946  */
4947 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */
4948 #define ALT_QSPI_INDRDCNT_VALUE_LSB 0
4949 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */
4950 #define ALT_QSPI_INDRDCNT_VALUE_MSB 31
4951 /* The width in bits of the ALT_QSPI_INDRDCNT_VALUE register field. */
4952 #define ALT_QSPI_INDRDCNT_VALUE_WIDTH 32
4953 /* The mask used to set the ALT_QSPI_INDRDCNT_VALUE register field value. */
4954 #define ALT_QSPI_INDRDCNT_VALUE_SET_MSK 0xffffffff
4955 /* The mask used to clear the ALT_QSPI_INDRDCNT_VALUE register field value. */
4956 #define ALT_QSPI_INDRDCNT_VALUE_CLR_MSK 0x00000000
4957 /* The reset value of the ALT_QSPI_INDRDCNT_VALUE register field. */
4958 #define ALT_QSPI_INDRDCNT_VALUE_RESET 0x0
4959 /* Extracts the ALT_QSPI_INDRDCNT_VALUE field value from a register. */
4960 #define ALT_QSPI_INDRDCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
4961 /* Produces a ALT_QSPI_INDRDCNT_VALUE register field value suitable for setting the register. */
4962 #define ALT_QSPI_INDRDCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)
4963 
4964 #ifndef __ASSEMBLY__
4965 /*
4966  * WARNING: The C register and register group struct declarations are provided for
4967  * convenience and illustrative purposes. They should, however, be used with
4968  * caution as the C language standard provides no guarantees about the alignment or
4969  * atomicity of device memory accesses. The recommended practice for writing
4970  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4971  * alt_write_word() functions.
4972  *
4973  * The struct declaration for register ALT_QSPI_INDRDCNT.
4974  */
4975 struct ALT_QSPI_INDRDCNT_s
4976 {
4977  uint32_t value : 32; /* Indirect Number of Bytes */
4978 };
4979 
4980 /* The typedef declaration for register ALT_QSPI_INDRDCNT. */
4981 typedef volatile struct ALT_QSPI_INDRDCNT_s ALT_QSPI_INDRDCNT_t;
4982 #endif /* __ASSEMBLY__ */
4983 
4984 /* The reset value of the ALT_QSPI_INDRDCNT register. */
4985 #define ALT_QSPI_INDRDCNT_RESET 0x00000000
4986 /* The byte offset of the ALT_QSPI_INDRDCNT register from the beginning of the component. */
4987 #define ALT_QSPI_INDRDCNT_OFST 0x6c
4988 
4989 /*
4990  * Register : Indirect Write Transfer Control Register - indwr
4991  *
4992  * Register Layout
4993  *
4994  * Bits | Access | Reset | Description
4995  * :-------|:-------|:------|:---------------------------------
4996  * [0] | W | 0x0 | Start Indirect Write
4997  * [1] | W | 0x0 | Cancel Indirect Write
4998  * [2] | R | 0x0 | Indirect Write Status
4999  * [3] | R | 0x0 | Reserved
5000  * [4] | R | 0x0 | Queued Indirect Write Operations
5001  * [5] | RW | 0x0 | Indirect Completion Status
5002  * [7:6] | R | 0x0 | Completed Indirect Operations
5003  * [31:8] | R | 0x0 | Reserved
5004  *
5005  */
5006 /*
5007  * Field : Start Indirect Write - start
5008  *
5009  * Writing a 1 to this bit will trigger an indirect write operation. The assumption
5010  * is that the indirect start address and the indirect number of bytes register is
5011  * setup before triggering the indirect write operation.
5012  *
5013  * Field Enumeration Values:
5014  *
5015  * Enum | Value | Description
5016  * :----------------------------|:------|:---------------------------------
5017  * ALT_QSPI_INDWR_START_E_DISD | 0x0 | No Action
5018  * ALT_QSPI_INDWR_START_E_END | 0x1 | Trigger indirect write operation
5019  *
5020  * Field Access Macros:
5021  *
5022  */
5023 /*
5024  * Enumerated value for register field ALT_QSPI_INDWR_START
5025  *
5026  * No Action
5027  */
5028 #define ALT_QSPI_INDWR_START_E_DISD 0x0
5029 /*
5030  * Enumerated value for register field ALT_QSPI_INDWR_START
5031  *
5032  * Trigger indirect write operation
5033  */
5034 #define ALT_QSPI_INDWR_START_E_END 0x1
5035 
5036 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_START register field. */
5037 #define ALT_QSPI_INDWR_START_LSB 0
5038 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_START register field. */
5039 #define ALT_QSPI_INDWR_START_MSB 0
5040 /* The width in bits of the ALT_QSPI_INDWR_START register field. */
5041 #define ALT_QSPI_INDWR_START_WIDTH 1
5042 /* The mask used to set the ALT_QSPI_INDWR_START register field value. */
5043 #define ALT_QSPI_INDWR_START_SET_MSK 0x00000001
5044 /* The mask used to clear the ALT_QSPI_INDWR_START register field value. */
5045 #define ALT_QSPI_INDWR_START_CLR_MSK 0xfffffffe
5046 /* The reset value of the ALT_QSPI_INDWR_START register field. */
5047 #define ALT_QSPI_INDWR_START_RESET 0x0
5048 /* Extracts the ALT_QSPI_INDWR_START field value from a register. */
5049 #define ALT_QSPI_INDWR_START_GET(value) (((value) & 0x00000001) >> 0)
5050 /* Produces a ALT_QSPI_INDWR_START register field value suitable for setting the register. */
5051 #define ALT_QSPI_INDWR_START_SET(value) (((value) << 0) & 0x00000001)
5052 
5053 /*
5054  * Field : Cancel Indirect Write - cancel
5055  *
5056  * Writing a 1 to this bit will cancel all ongoing indirect write operations.
5057  *
5058  * Field Enumeration Values:
5059  *
5060  * Enum | Value | Description
5061  * :-----------------------------------|:------|:--------------------------------
5062  * ALT_QSPI_INDWR_CANCEL_E_NOACTION | 0x0 | No Action
5063  * ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR | 0x1 | Cancel Indirect write operation
5064  *
5065  * Field Access Macros:
5066  *
5067  */
5068 /*
5069  * Enumerated value for register field ALT_QSPI_INDWR_CANCEL
5070  *
5071  * No Action
5072  */
5073 #define ALT_QSPI_INDWR_CANCEL_E_NOACTION 0x0
5074 /*
5075  * Enumerated value for register field ALT_QSPI_INDWR_CANCEL
5076  *
5077  * Cancel Indirect write operation
5078  */
5079 #define ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR 0x1
5080 
5081 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_CANCEL register field. */
5082 #define ALT_QSPI_INDWR_CANCEL_LSB 1
5083 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_CANCEL register field. */
5084 #define ALT_QSPI_INDWR_CANCEL_MSB 1
5085 /* The width in bits of the ALT_QSPI_INDWR_CANCEL register field. */
5086 #define ALT_QSPI_INDWR_CANCEL_WIDTH 1
5087 /* The mask used to set the ALT_QSPI_INDWR_CANCEL register field value. */
5088 #define ALT_QSPI_INDWR_CANCEL_SET_MSK 0x00000002
5089 /* The mask used to clear the ALT_QSPI_INDWR_CANCEL register field value. */
5090 #define ALT_QSPI_INDWR_CANCEL_CLR_MSK 0xfffffffd
5091 /* The reset value of the ALT_QSPI_INDWR_CANCEL register field. */
5092 #define ALT_QSPI_INDWR_CANCEL_RESET 0x0
5093 /* Extracts the ALT_QSPI_INDWR_CANCEL field value from a register. */
5094 #define ALT_QSPI_INDWR_CANCEL_GET(value) (((value) & 0x00000002) >> 1)
5095 /* Produces a ALT_QSPI_INDWR_CANCEL register field value suitable for setting the register. */
5096 #define ALT_QSPI_INDWR_CANCEL_SET(value) (((value) << 1) & 0x00000002)
5097 
5098 /*
5099  * Field : Indirect Write Status - rdstat
5100  *
5101  * Indirect write operation in progress (status)
5102  *
5103  * Field Enumeration Values:
5104  *
5105  * Enum | Value | Description
5106  * :----------------------------------|:------|:-------------------------
5107  * ALT_QSPI_INDWR_RDSTAT_E_NOACTION | 0x0 | No Action
5108  * ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT | 0x1 | Indirect write operation
5109  *
5110  * Field Access Macros:
5111  *
5112  */
5113 /*
5114  * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT
5115  *
5116  * No Action
5117  */
5118 #define ALT_QSPI_INDWR_RDSTAT_E_NOACTION 0x0
5119 /*
5120  * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT
5121  *
5122  * Indirect write operation
5123  */
5124 #define ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT 0x1
5125 
5126 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */
5127 #define ALT_QSPI_INDWR_RDSTAT_LSB 2
5128 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */
5129 #define ALT_QSPI_INDWR_RDSTAT_MSB 2
5130 /* The width in bits of the ALT_QSPI_INDWR_RDSTAT register field. */
5131 #define ALT_QSPI_INDWR_RDSTAT_WIDTH 1
5132 /* The mask used to set the ALT_QSPI_INDWR_RDSTAT register field value. */
5133 #define ALT_QSPI_INDWR_RDSTAT_SET_MSK 0x00000004
5134 /* The mask used to clear the ALT_QSPI_INDWR_RDSTAT register field value. */
5135 #define ALT_QSPI_INDWR_RDSTAT_CLR_MSK 0xfffffffb
5136 /* The reset value of the ALT_QSPI_INDWR_RDSTAT register field. */
5137 #define ALT_QSPI_INDWR_RDSTAT_RESET 0x0
5138 /* Extracts the ALT_QSPI_INDWR_RDSTAT field value from a register. */
5139 #define ALT_QSPI_INDWR_RDSTAT_GET(value) (((value) & 0x00000004) >> 2)
5140 /* Produces a ALT_QSPI_INDWR_RDSTAT register field value suitable for setting the register. */
5141 #define ALT_QSPI_INDWR_RDSTAT_SET(value) (((value) << 2) & 0x00000004)
5142 
5143 /*
5144  * Field : Reserved - indir_wr_rsvd_fld
5145  *
5146  * Field Access Macros:
5147  *
5148  */
5149 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD register field. */
5150 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_LSB 3
5151 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD register field. */
5152 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_MSB 3
5153 /* The width in bits of the ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD register field. */
5154 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_WIDTH 1
5155 /* The mask used to set the ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD register field value. */
5156 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_SET_MSK 0x00000008
5157 /* The mask used to clear the ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD register field value. */
5158 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_CLR_MSK 0xfffffff7
5159 /* The reset value of the ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD register field. */
5160 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_RESET 0x0
5161 /* Extracts the ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD field value from a register. */
5162 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_GET(value) (((value) & 0x00000008) >> 3)
5163 /* Produces a ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD register field value suitable for setting the register. */
5164 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_SET(value) (((value) << 3) & 0x00000008)
5165 
5166 /*
5167  * Field : Queued Indirect Write Operations - rdqueued
5168  *
5169  * Two indirect write operations have been queued
5170  *
5171  * Field Enumeration Values:
5172  *
5173  * Enum | Value | Description
5174  * :-----------------------------------|:------|:-----------------------------
5175  * ALT_QSPI_INDWR_RDQUEUED_E_NOACTION | 0x0 | No Action
5176  * ALT_QSPI_INDWR_RDQUEUED_E_INDWROP | 0x1 | Two Indirect write operation
5177  *
5178  * Field Access Macros:
5179  *
5180  */
5181 /*
5182  * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED
5183  *
5184  * No Action
5185  */
5186 #define ALT_QSPI_INDWR_RDQUEUED_E_NOACTION 0x0
5187 /*
5188  * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED
5189  *
5190  * Two Indirect write operation
5191  */
5192 #define ALT_QSPI_INDWR_RDQUEUED_E_INDWROP 0x1
5193 
5194 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */
5195 #define ALT_QSPI_INDWR_RDQUEUED_LSB 4
5196 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */
5197 #define ALT_QSPI_INDWR_RDQUEUED_MSB 4
5198 /* The width in bits of the ALT_QSPI_INDWR_RDQUEUED register field. */
5199 #define ALT_QSPI_INDWR_RDQUEUED_WIDTH 1
5200 /* The mask used to set the ALT_QSPI_INDWR_RDQUEUED register field value. */
5201 #define ALT_QSPI_INDWR_RDQUEUED_SET_MSK 0x00000010
5202 /* The mask used to clear the ALT_QSPI_INDWR_RDQUEUED register field value. */
5203 #define ALT_QSPI_INDWR_RDQUEUED_CLR_MSK 0xffffffef
5204 /* The reset value of the ALT_QSPI_INDWR_RDQUEUED register field. */
5205 #define ALT_QSPI_INDWR_RDQUEUED_RESET 0x0
5206 /* Extracts the ALT_QSPI_INDWR_RDQUEUED field value from a register. */
5207 #define ALT_QSPI_INDWR_RDQUEUED_GET(value) (((value) & 0x00000010) >> 4)
5208 /* Produces a ALT_QSPI_INDWR_RDQUEUED register field value suitable for setting the register. */
5209 #define ALT_QSPI_INDWR_RDQUEUED_SET(value) (((value) << 4) & 0x00000010)
5210 
5211 /*
5212  * Field : Indirect Completion Status - inddone
5213  *
5214  * This field is set to 1 when an indirect operation has completed. Write a 1 to
5215  * this field to clear it.
5216  *
5217  * Field Enumeration Values:
5218  *
5219  * Enum | Value | Description
5220  * :-----------------------------------|:------|:-----------------------------
5221  * ALT_QSPI_INDWR_INDDONE_E_NOACTION | 0x0 | No Action
5222  * ALT_QSPI_INDWR_INDDONE_E_INDCOMPST | 0x1 | Indirect operation completed
5223  *
5224  * Field Access Macros:
5225  *
5226  */
5227 /*
5228  * Enumerated value for register field ALT_QSPI_INDWR_INDDONE
5229  *
5230  * No Action
5231  */
5232 #define ALT_QSPI_INDWR_INDDONE_E_NOACTION 0x0
5233 /*
5234  * Enumerated value for register field ALT_QSPI_INDWR_INDDONE
5235  *
5236  * Indirect operation completed
5237  */
5238 #define ALT_QSPI_INDWR_INDDONE_E_INDCOMPST 0x1
5239 
5240 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDDONE register field. */
5241 #define ALT_QSPI_INDWR_INDDONE_LSB 5
5242 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDDONE register field. */
5243 #define ALT_QSPI_INDWR_INDDONE_MSB 5
5244 /* The width in bits of the ALT_QSPI_INDWR_INDDONE register field. */
5245 #define ALT_QSPI_INDWR_INDDONE_WIDTH 1
5246 /* The mask used to set the ALT_QSPI_INDWR_INDDONE register field value. */
5247 #define ALT_QSPI_INDWR_INDDONE_SET_MSK 0x00000020
5248 /* The mask used to clear the ALT_QSPI_INDWR_INDDONE register field value. */
5249 #define ALT_QSPI_INDWR_INDDONE_CLR_MSK 0xffffffdf
5250 /* The reset value of the ALT_QSPI_INDWR_INDDONE register field. */
5251 #define ALT_QSPI_INDWR_INDDONE_RESET 0x0
5252 /* Extracts the ALT_QSPI_INDWR_INDDONE field value from a register. */
5253 #define ALT_QSPI_INDWR_INDDONE_GET(value) (((value) & 0x00000020) >> 5)
5254 /* Produces a ALT_QSPI_INDWR_INDDONE register field value suitable for setting the register. */
5255 #define ALT_QSPI_INDWR_INDDONE_SET(value) (((value) << 5) & 0x00000020)
5256 
5257 /*
5258  * Field : Completed Indirect Operations - indcnt
5259  *
5260  * This field contains the number of indirect operations which have been completed.
5261  * This is used in conjunction with the indirect completion status field (bit 5).
5262  * It is incremented by hardware when an indirect operation has completed. Write a
5263  * 1 to bit 5 of this register to decrement it.
5264  *
5265  * Field Access Macros:
5266  *
5267  */
5268 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDCNT register field. */
5269 #define ALT_QSPI_INDWR_INDCNT_LSB 6
5270 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDCNT register field. */
5271 #define ALT_QSPI_INDWR_INDCNT_MSB 7
5272 /* The width in bits of the ALT_QSPI_INDWR_INDCNT register field. */
5273 #define ALT_QSPI_INDWR_INDCNT_WIDTH 2
5274 /* The mask used to set the ALT_QSPI_INDWR_INDCNT register field value. */
5275 #define ALT_QSPI_INDWR_INDCNT_SET_MSK 0x000000c0
5276 /* The mask used to clear the ALT_QSPI_INDWR_INDCNT register field value. */
5277 #define ALT_QSPI_INDWR_INDCNT_CLR_MSK 0xffffff3f
5278 /* The reset value of the ALT_QSPI_INDWR_INDCNT register field. */
5279 #define ALT_QSPI_INDWR_INDCNT_RESET 0x0
5280 /* Extracts the ALT_QSPI_INDWR_INDCNT field value from a register. */
5281 #define ALT_QSPI_INDWR_INDCNT_GET(value) (((value) & 0x000000c0) >> 6)
5282 /* Produces a ALT_QSPI_INDWR_INDCNT register field value suitable for setting the register. */
5283 #define ALT_QSPI_INDWR_INDCNT_SET(value) (((value) << 6) & 0x000000c0)
5284 
5285 /*
5286  * Field : Reserved - indir_wr_xfer_resv2_fld
5287  *
5288  * Field Access Macros:
5289  *
5290  */
5291 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD register field. */
5292 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_LSB 8
5293 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD register field. */
5294 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_MSB 31
5295 /* The width in bits of the ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD register field. */
5296 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_WIDTH 24
5297 /* The mask used to set the ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD register field value. */
5298 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_SET_MSK 0xffffff00
5299 /* The mask used to clear the ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD register field value. */
5300 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_CLR_MSK 0x000000ff
5301 /* The reset value of the ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD register field. */
5302 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_RESET 0x0
5303 /* Extracts the ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD field value from a register. */
5304 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_GET(value) (((value) & 0xffffff00) >> 8)
5305 /* Produces a ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD register field value suitable for setting the register. */
5306 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_SET(value) (((value) << 8) & 0xffffff00)
5307 
5308 #ifndef __ASSEMBLY__
5309 /*
5310  * WARNING: The C register and register group struct declarations are provided for
5311  * convenience and illustrative purposes. They should, however, be used with
5312  * caution as the C language standard provides no guarantees about the alignment or
5313  * atomicity of device memory accesses. The recommended practice for writing
5314  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5315  * alt_write_word() functions.
5316  *
5317  * The struct declaration for register ALT_QSPI_INDWR.
5318  */
5319 struct ALT_QSPI_INDWR_s
5320 {
5321  uint32_t start : 1; /* Start Indirect Write */
5322  uint32_t cancel : 1; /* Cancel Indirect Write */
5323  const uint32_t rdstat : 1; /* Indirect Write Status */
5324  const uint32_t indir_wr_rsvd_fld : 1; /* Reserved */
5325  const uint32_t rdqueued : 1; /* Queued Indirect Write Operations */
5326  uint32_t inddone : 1; /* Indirect Completion Status */
5327  const uint32_t indcnt : 2; /* Completed Indirect Operations */
5328  const uint32_t indir_wr_xfer_resv2_fld : 24; /* Reserved */
5329 };
5330 
5331 /* The typedef declaration for register ALT_QSPI_INDWR. */
5332 typedef volatile struct ALT_QSPI_INDWR_s ALT_QSPI_INDWR_t;
5333 #endif /* __ASSEMBLY__ */
5334 
5335 /* The reset value of the ALT_QSPI_INDWR register. */
5336 #define ALT_QSPI_INDWR_RESET 0x00000000
5337 /* The byte offset of the ALT_QSPI_INDWR register from the beginning of the component. */
5338 #define ALT_QSPI_INDWR_OFST 0x70
5339 
5340 /*
5341  * Register : Indirect Write Transfer Watermark Register - indwrwater
5342  *
5343  * Register Layout
5344  *
5345  * Bits | Access | Reset | Description
5346  * :-------|:-------|:-----------|:----------------
5347  * [31:0] | RW | 0xffffffff | Watermark Value
5348  *
5349  */
5350 /*
5351  * Field : Watermark Value - level
5352  *
5353  * This represents the maximum fill level of the SRAM before a DMA peripheral
5354  * access is permitted. When the SRAM fill level falls below the watermark, an
5355  * interrupt is also generated. This field can be disabled by writing a value of
5356  * all ones.
5357  *
5358  * Field Access Macros:
5359  *
5360  */
5361 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */
5362 #define ALT_QSPI_INDWRWATER_LEVEL_LSB 0
5363 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */
5364 #define ALT_QSPI_INDWRWATER_LEVEL_MSB 31
5365 /* The width in bits of the ALT_QSPI_INDWRWATER_LEVEL register field. */
5366 #define ALT_QSPI_INDWRWATER_LEVEL_WIDTH 32
5367 /* The mask used to set the ALT_QSPI_INDWRWATER_LEVEL register field value. */
5368 #define ALT_QSPI_INDWRWATER_LEVEL_SET_MSK 0xffffffff
5369 /* The mask used to clear the ALT_QSPI_INDWRWATER_LEVEL register field value. */
5370 #define ALT_QSPI_INDWRWATER_LEVEL_CLR_MSK 0x00000000
5371 /* The reset value of the ALT_QSPI_INDWRWATER_LEVEL register field. */
5372 #define ALT_QSPI_INDWRWATER_LEVEL_RESET 0xffffffff
5373 /* Extracts the ALT_QSPI_INDWRWATER_LEVEL field value from a register. */
5374 #define ALT_QSPI_INDWRWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
5375 /* Produces a ALT_QSPI_INDWRWATER_LEVEL register field value suitable for setting the register. */
5376 #define ALT_QSPI_INDWRWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
5377 
5378 #ifndef __ASSEMBLY__
5379 /*
5380  * WARNING: The C register and register group struct declarations are provided for
5381  * convenience and illustrative purposes. They should, however, be used with
5382  * caution as the C language standard provides no guarantees about the alignment or
5383  * atomicity of device memory accesses. The recommended practice for writing
5384  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5385  * alt_write_word() functions.
5386  *
5387  * The struct declaration for register ALT_QSPI_INDWRWATER.
5388  */
5389 struct ALT_QSPI_INDWRWATER_s
5390 {
5391  uint32_t level : 32; /* Watermark Value */
5392 };
5393 
5394 /* The typedef declaration for register ALT_QSPI_INDWRWATER. */
5395 typedef volatile struct ALT_QSPI_INDWRWATER_s ALT_QSPI_INDWRWATER_t;
5396 #endif /* __ASSEMBLY__ */
5397 
5398 /* The reset value of the ALT_QSPI_INDWRWATER register. */
5399 #define ALT_QSPI_INDWRWATER_RESET 0xffffffff
5400 /* The byte offset of the ALT_QSPI_INDWRWATER register from the beginning of the component. */
5401 #define ALT_QSPI_INDWRWATER_OFST 0x74
5402 
5403 /*
5404  * Register : Indirect Write Transfer Start Address Register - indwrstaddr
5405  *
5406  * Register Layout
5407  *
5408  * Bits | Access | Reset | Description
5409  * :-------|:-------|:------|:-------------------------
5410  * [31:0] | RW | 0x0 | Start of Indirect Access
5411  *
5412  */
5413 /*
5414  * Field : Start of Indirect Access - addr
5415  *
5416  * This is the start address from which the indirect access will commence its READ
5417  * operation.
5418  *
5419  * Field Access Macros:
5420  *
5421  */
5422 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */
5423 #define ALT_QSPI_INDWRSTADDR_ADDR_LSB 0
5424 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */
5425 #define ALT_QSPI_INDWRSTADDR_ADDR_MSB 31
5426 /* The width in bits of the ALT_QSPI_INDWRSTADDR_ADDR register field. */
5427 #define ALT_QSPI_INDWRSTADDR_ADDR_WIDTH 32
5428 /* The mask used to set the ALT_QSPI_INDWRSTADDR_ADDR register field value. */
5429 #define ALT_QSPI_INDWRSTADDR_ADDR_SET_MSK 0xffffffff
5430 /* The mask used to clear the ALT_QSPI_INDWRSTADDR_ADDR register field value. */
5431 #define ALT_QSPI_INDWRSTADDR_ADDR_CLR_MSK 0x00000000
5432 /* The reset value of the ALT_QSPI_INDWRSTADDR_ADDR register field. */
5433 #define ALT_QSPI_INDWRSTADDR_ADDR_RESET 0x0
5434 /* Extracts the ALT_QSPI_INDWRSTADDR_ADDR field value from a register. */
5435 #define ALT_QSPI_INDWRSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
5436 /* Produces a ALT_QSPI_INDWRSTADDR_ADDR register field value suitable for setting the register. */
5437 #define ALT_QSPI_INDWRSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
5438 
5439 #ifndef __ASSEMBLY__
5440 /*
5441  * WARNING: The C register and register group struct declarations are provided for
5442  * convenience and illustrative purposes. They should, however, be used with
5443  * caution as the C language standard provides no guarantees about the alignment or
5444  * atomicity of device memory accesses. The recommended practice for writing
5445  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5446  * alt_write_word() functions.
5447  *
5448  * The struct declaration for register ALT_QSPI_INDWRSTADDR.
5449  */
5450 struct ALT_QSPI_INDWRSTADDR_s
5451 {
5452  uint32_t addr : 32; /* Start of Indirect Access */
5453 };
5454 
5455 /* The typedef declaration for register ALT_QSPI_INDWRSTADDR. */
5456 typedef volatile struct ALT_QSPI_INDWRSTADDR_s ALT_QSPI_INDWRSTADDR_t;
5457 #endif /* __ASSEMBLY__ */
5458 
5459 /* The reset value of the ALT_QSPI_INDWRSTADDR register. */
5460 #define ALT_QSPI_INDWRSTADDR_RESET 0x00000000
5461 /* The byte offset of the ALT_QSPI_INDWRSTADDR register from the beginning of the component. */
5462 #define ALT_QSPI_INDWRSTADDR_OFST 0x78
5463 
5464 /*
5465  * Register : Indirect Write Transfer Number Bytes Register - indwrcnt
5466  *
5467  * Register Layout
5468  *
5469  * Bits | Access | Reset | Description
5470  * :-------|:-------|:------|:-------------------------
5471  * [31:0] | RW | 0x0 | Indirect Number of Bytes
5472  *
5473  */
5474 /*
5475  * Field : Indirect Number of Bytes - value
5476  *
5477  * This is the number of bytes that the indirect access will consume. This can be
5478  * bigger than the configured size of SRAM.
5479  *
5480  * Field Access Macros:
5481  *
5482  */
5483 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */
5484 #define ALT_QSPI_INDWRCNT_VALUE_LSB 0
5485 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */
5486 #define ALT_QSPI_INDWRCNT_VALUE_MSB 31
5487 /* The width in bits of the ALT_QSPI_INDWRCNT_VALUE register field. */
5488 #define ALT_QSPI_INDWRCNT_VALUE_WIDTH 32
5489 /* The mask used to set the ALT_QSPI_INDWRCNT_VALUE register field value. */
5490 #define ALT_QSPI_INDWRCNT_VALUE_SET_MSK 0xffffffff
5491 /* The mask used to clear the ALT_QSPI_INDWRCNT_VALUE register field value. */
5492 #define ALT_QSPI_INDWRCNT_VALUE_CLR_MSK 0x00000000
5493 /* The reset value of the ALT_QSPI_INDWRCNT_VALUE register field. */
5494 #define ALT_QSPI_INDWRCNT_VALUE_RESET 0x0
5495 /* Extracts the ALT_QSPI_INDWRCNT_VALUE field value from a register. */
5496 #define ALT_QSPI_INDWRCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
5497 /* Produces a ALT_QSPI_INDWRCNT_VALUE register field value suitable for setting the register. */
5498 #define ALT_QSPI_INDWRCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)
5499 
5500 #ifndef __ASSEMBLY__
5501 /*
5502  * WARNING: The C register and register group struct declarations are provided for
5503  * convenience and illustrative purposes. They should, however, be used with
5504  * caution as the C language standard provides no guarantees about the alignment or
5505  * atomicity of device memory accesses. The recommended practice for writing
5506  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5507  * alt_write_word() functions.
5508  *
5509  * The struct declaration for register ALT_QSPI_INDWRCNT.
5510  */
5511 struct ALT_QSPI_INDWRCNT_s
5512 {
5513  uint32_t value : 32; /* Indirect Number of Bytes */
5514 };
5515 
5516 /* The typedef declaration for register ALT_QSPI_INDWRCNT. */
5517 typedef volatile struct ALT_QSPI_INDWRCNT_s ALT_QSPI_INDWRCNT_t;
5518 #endif /* __ASSEMBLY__ */
5519 
5520 /* The reset value of the ALT_QSPI_INDWRCNT register. */
5521 #define ALT_QSPI_INDWRCNT_RESET 0x00000000
5522 /* The byte offset of the ALT_QSPI_INDWRCNT register from the beginning of the component. */
5523 #define ALT_QSPI_INDWRCNT_OFST 0x7c
5524 
5525 /*
5526  * Register : Flash Command Control Register - flashcmd
5527  *
5528  * Register Layout
5529  *
5530  * Bits | Access | Reset | Description
5531  * :--------|:-------|:------|:---------------------------
5532  * [0] | W | 0x0 | Execute Command
5533  * [1] | R | 0x0 | Command Execution Status
5534  * [6:2] | R | 0x0 | Reserved
5535  * [11:7] | RW | 0x0 | Number of Dummy Bytes
5536  * [14:12] | RW | 0x0 | Number of Write Data Bytes
5537  * [15] | RW | 0x0 | Write Data Enable
5538  * [17:16] | RW | 0x0 | Number of Address Bytes
5539  * [18] | RW | 0x0 | Mode Bit Enable
5540  * [19] | RW | 0x0 | Command Address Enable
5541  * [22:20] | RW | 0x0 | Number of Read Data Bytes
5542  * [23] | RW | 0x0 | Read Data Enable
5543  * [31:24] | RW | 0x0 | Command Opcode
5544  *
5545  */
5546 /*
5547  * Field : Execute Command - execcmd
5548  *
5549  * Execute the command.
5550  *
5551  * Field Enumeration Values:
5552  *
5553  * Enum | Value | Description
5554  * :------------------------------------|:------|:----------------
5555  * ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION | 0x0 | No Action
5556  * ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE | 0x1 | Execute Command
5557  *
5558  * Field Access Macros:
5559  *
5560  */
5561 /*
5562  * Enumerated value for register field ALT_QSPI_FLSHCMD_EXECCMD
5563  *
5564  * No Action
5565  */
5566 #define ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION 0x0
5567 /*
5568  * Enumerated value for register field ALT_QSPI_FLSHCMD_EXECCMD
5569  *
5570  * Execute Command
5571  */
5572 #define ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE 0x1
5573 
5574 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_EXECCMD register field. */
5575 #define ALT_QSPI_FLSHCMD_EXECCMD_LSB 0
5576 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_EXECCMD register field. */
5577 #define ALT_QSPI_FLSHCMD_EXECCMD_MSB 0
5578 /* The width in bits of the ALT_QSPI_FLSHCMD_EXECCMD register field. */
5579 #define ALT_QSPI_FLSHCMD_EXECCMD_WIDTH 1
5580 /* The mask used to set the ALT_QSPI_FLSHCMD_EXECCMD register field value. */
5581 #define ALT_QSPI_FLSHCMD_EXECCMD_SET_MSK 0x00000001
5582 /* The mask used to clear the ALT_QSPI_FLSHCMD_EXECCMD register field value. */
5583 #define ALT_QSPI_FLSHCMD_EXECCMD_CLR_MSK 0xfffffffe
5584 /* The reset value of the ALT_QSPI_FLSHCMD_EXECCMD register field. */
5585 #define ALT_QSPI_FLSHCMD_EXECCMD_RESET 0x0
5586 /* Extracts the ALT_QSPI_FLSHCMD_EXECCMD field value from a register. */
5587 #define ALT_QSPI_FLSHCMD_EXECCMD_GET(value) (((value) & 0x00000001) >> 0)
5588 /* Produces a ALT_QSPI_FLSHCMD_EXECCMD register field value suitable for setting the register. */
5589 #define ALT_QSPI_FLSHCMD_EXECCMD_SET(value) (((value) << 0) & 0x00000001)
5590 
5591 /*
5592  * Field : Command Execution Status - cmdexecstat
5593  *
5594  * Command execution in progress.
5595  *
5596  * Field Enumeration Values:
5597  *
5598  * Enum | Value | Description
5599  * :-------------------------------------------|:------|:-------------------------
5600  * ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION | 0x0 | No Action
5601  * ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT | 0x1 | Command Execution Status
5602  *
5603  * Field Access Macros:
5604  *
5605  */
5606 /*
5607  * Enumerated value for register field ALT_QSPI_FLSHCMD_CMDEXECSTAT
5608  *
5609  * No Action
5610  */
5611 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION 0x0
5612 /*
5613  * Enumerated value for register field ALT_QSPI_FLSHCMD_CMDEXECSTAT
5614  *
5615  * Command Execution Status
5616  */
5617 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT 0x1
5618 
5619 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */
5620 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_LSB 1
5621 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */
5622 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_MSB 1
5623 /* The width in bits of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */
5624 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_WIDTH 1
5625 /* The mask used to set the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value. */
5626 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET_MSK 0x00000002
5627 /* The mask used to clear the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value. */
5628 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_CLR_MSK 0xfffffffd
5629 /* The reset value of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */
5630 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_RESET 0x0
5631 /* Extracts the ALT_QSPI_FLSHCMD_CMDEXECSTAT field value from a register. */
5632 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_GET(value) (((value) & 0x00000002) >> 1)
5633 /* Produces a ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value suitable for setting the register. */
5634 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET(value) (((value) << 1) & 0x00000002)
5635 
5636 /*
5637  * Field : Reserved - flash_cmd_cntrl_resv1_fld
5638  *
5639  * Field Access Macros:
5640  *
5641  */
5642 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD register field. */
5643 #define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_LSB 2
5644 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD register field. */
5645 #define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_MSB 6
5646 /* The width in bits of the ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD register field. */
5647 #define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_WIDTH 5
5648 /* The mask used to set the ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD register field value. */
5649 #define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_SET_MSK 0x0000007c
5650 /* The mask used to clear the ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD register field value. */
5651 #define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_CLR_MSK 0xffffff83
5652 /* The reset value of the ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD register field. */
5653 #define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_RESET 0x0
5654 /* Extracts the ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD field value from a register. */
5655 #define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_GET(value) (((value) & 0x0000007c) >> 2)
5656 /* Produces a ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD register field value suitable for setting the register. */
5657 #define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_SET(value) (((value) << 2) & 0x0000007c)
5658 
5659 /*
5660  * Field : Number of Dummy Bytes - numdummybytes
5661  *
5662  * Set to the number of dummy bytes required This should be setup before triggering
5663  * the command via the execute field of this register.
5664  *
5665  * Field Access Macros:
5666  *
5667  */
5668 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */
5669 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_LSB 7
5670 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */
5671 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_MSB 11
5672 /* The width in bits of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */
5673 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH 5
5674 /* The mask used to set the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value. */
5675 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET_MSK 0x00000f80
5676 /* The mask used to clear the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value. */
5677 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_CLR_MSK 0xfffff07f
5678 /* The reset value of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */
5679 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_RESET 0x0
5680 /* Extracts the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES field value from a register. */
5681 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_GET(value) (((value) & 0x00000f80) >> 7)
5682 /* Produces a ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value suitable for setting the register. */
5683 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(value) (((value) << 7) & 0x00000f80)
5684 
5685 /*
5686  * Field : Number of Write Data Bytes - numwrdatabytes
5687  *
5688  * Up to 8 Data bytes may be written using this command Set to 0 for 1 byte, 7 for
5689  * 8 bytes.
5690  *
5691  * Field Enumeration Values:
5692  *
5693  * Enum | Value | Description
5694  * :------------------------------------------|:------|:-------------
5695  * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 | 0x0 | Write 1 Byte
5696  * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 | 0x1 | Write 2 Byte
5697  * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 | 0x2 | Write 3 Byte
5698  * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 | 0x3 | Write 4 Byte
5699  * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 | 0x4 | Write 5 Byte
5700  * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 | 0x5 | Write 6 Byte
5701  * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 | 0x6 | Write 7 Byte
5702  * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 | 0x7 | Write 8 Byte
5703  *
5704  * Field Access Macros:
5705  *
5706  */
5707 /*
5708  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5709  *
5710  * Write 1 Byte
5711  */
5712 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 0x0
5713 /*
5714  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5715  *
5716  * Write 2 Byte
5717  */
5718 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 0x1
5719 /*
5720  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5721  *
5722  * Write 3 Byte
5723  */
5724 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 0x2
5725 /*
5726  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5727  *
5728  * Write 4 Byte
5729  */
5730 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 0x3
5731 /*
5732  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5733  *
5734  * Write 5 Byte
5735  */
5736 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 0x4
5737 /*
5738  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5739  *
5740  * Write 6 Byte
5741  */
5742 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 0x5
5743 /*
5744  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5745  *
5746  * Write 7 Byte
5747  */
5748 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 0x6
5749 /*
5750  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
5751  *
5752  * Write 8 Byte
5753  */
5754 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 0x7
5755 
5756 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */
5757 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_LSB 12
5758 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */
5759 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_MSB 14
5760 /* The width in bits of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */
5761 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_WIDTH 3
5762 /* The mask used to set the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value. */
5763 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET_MSK 0x00007000
5764 /* The mask used to clear the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value. */
5765 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_CLR_MSK 0xffff8fff
5766 /* The reset value of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */
5767 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_RESET 0x0
5768 /* Extracts the ALT_QSPI_FLSHCMD_NUMWRDATABYTES field value from a register. */
5769 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_GET(value) (((value) & 0x00007000) >> 12)
5770 /* Produces a ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value suitable for setting the register. */
5771 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(value) (((value) << 12) & 0x00007000)
5772 
5773 /*
5774  * Field : Write Data Enable - enwrdata
5775  *
5776  * Set to 1 if the command specified in the command opcode field requires write
5777  * data bytes to be sent to the device.
5778  *
5779  * Field Enumeration Values:
5780  *
5781  * Enum | Value | Description
5782  * :----------------------------------------|:------|:----------------------------------
5783  * ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION | 0x0 | No Action
5784  * ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES | 0x1 | Command requires write data bytes
5785  *
5786  * Field Access Macros:
5787  *
5788  */
5789 /*
5790  * Enumerated value for register field ALT_QSPI_FLSHCMD_ENWRDATA
5791  *
5792  * No Action
5793  */
5794 #define ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION 0x0
5795 /*
5796  * Enumerated value for register field ALT_QSPI_FLSHCMD_ENWRDATA
5797  *
5798  * Command requires write data bytes
5799  */
5800 #define ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES 0x1
5801 
5802 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */
5803 #define ALT_QSPI_FLSHCMD_ENWRDATA_LSB 15
5804 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */
5805 #define ALT_QSPI_FLSHCMD_ENWRDATA_MSB 15
5806 /* The width in bits of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */
5807 #define ALT_QSPI_FLSHCMD_ENWRDATA_WIDTH 1
5808 /* The mask used to set the ALT_QSPI_FLSHCMD_ENWRDATA register field value. */
5809 #define ALT_QSPI_FLSHCMD_ENWRDATA_SET_MSK 0x00008000
5810 /* The mask used to clear the ALT_QSPI_FLSHCMD_ENWRDATA register field value. */
5811 #define ALT_QSPI_FLSHCMD_ENWRDATA_CLR_MSK 0xffff7fff
5812 /* The reset value of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */
5813 #define ALT_QSPI_FLSHCMD_ENWRDATA_RESET 0x0
5814 /* Extracts the ALT_QSPI_FLSHCMD_ENWRDATA field value from a register. */
5815 #define ALT_QSPI_FLSHCMD_ENWRDATA_GET(value) (((value) & 0x00008000) >> 15)
5816 /* Produces a ALT_QSPI_FLSHCMD_ENWRDATA register field value suitable for setting the register. */
5817 #define ALT_QSPI_FLSHCMD_ENWRDATA_SET(value) (((value) << 15) & 0x00008000)
5818 
5819 /*
5820  * Field : Number of Address Bytes - numaddrbytes
5821  *
5822  * Set to the number of address bytes required (the address itself is programmed in
5823  * the FLASH COMMAND ADDRESS REGISTERS). This should be setup before triggering the
5824  * command via bit 0 of this register. 2'b00 : 1 address byte 2'b01 : 2 address
5825  * bytes 2'b10 : 3 address bytes 2'b11 : 4 address bytes
5826  *
5827  * Field Enumeration Values:
5828  *
5829  * Enum | Value | Description
5830  * :------------------------------------------|:------|:----------------------
5831  * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 | 0x0 | Write 1 Address Byte
5832  * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 | 0x1 | Write 2 Address Bytes
5833  * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 | 0x2 | Write 3 Address Bytes
5834  * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 | 0x3 | Write 4 Address Bytes
5835  *
5836  * Field Access Macros:
5837  *
5838  */
5839 /*
5840  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES
5841  *
5842  * Write 1 Address Byte
5843  */
5844 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 0x0
5845 /*
5846  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES
5847  *
5848  * Write 2 Address Bytes
5849  */
5850 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 0x1
5851 /*
5852  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES
5853  *
5854  * Write 3 Address Bytes
5855  */
5856 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 0x2
5857 /*
5858  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES
5859  *
5860  * Write 4 Address Bytes
5861  */
5862 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 0x3
5863 
5864 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */
5865 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_LSB 16
5866 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */
5867 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_MSB 17
5868 /* The width in bits of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */
5869 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_WIDTH 2
5870 /* The mask used to set the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value. */
5871 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET_MSK 0x00030000
5872 /* The mask used to clear the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value. */
5873 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_CLR_MSK 0xfffcffff
5874 /* The reset value of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */
5875 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_RESET 0x0
5876 /* Extracts the ALT_QSPI_FLSHCMD_NUMADDRBYTES field value from a register. */
5877 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_GET(value) (((value) & 0x00030000) >> 16)
5878 /* Produces a ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value suitable for setting the register. */
5879 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(value) (((value) << 16) & 0x00030000)
5880 
5881 /*
5882  * Field : Mode Bit Enable - enmodebit
5883  *
5884  * Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration
5885  * register are sent following the address bytes.
5886  *
5887  * Field Enumeration Values:
5888  *
5889  * Enum | Value | Description
5890  * :---------------------------------|:------|:-------------------------------
5891  * ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD | 0x0 | No Action
5892  * ALT_QSPI_FLSHCMD_ENMODBIT_E_END | 0x1 | Mode Bit follows address bytes
5893  *
5894  * Field Access Macros:
5895  *
5896  */
5897 /*
5898  * Enumerated value for register field ALT_QSPI_FLSHCMD_ENMODBIT
5899  *
5900  * No Action
5901  */
5902 #define ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD 0x0
5903 /*
5904  * Enumerated value for register field ALT_QSPI_FLSHCMD_ENMODBIT
5905  *
5906  * Mode Bit follows address bytes
5907  */
5908 #define ALT_QSPI_FLSHCMD_ENMODBIT_E_END 0x1
5909 
5910 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */
5911 #define ALT_QSPI_FLSHCMD_ENMODBIT_LSB 18
5912 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */
5913 #define ALT_QSPI_FLSHCMD_ENMODBIT_MSB 18
5914 /* The width in bits of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */
5915 #define ALT_QSPI_FLSHCMD_ENMODBIT_WIDTH 1
5916 /* The mask used to set the ALT_QSPI_FLSHCMD_ENMODBIT register field value. */
5917 #define ALT_QSPI_FLSHCMD_ENMODBIT_SET_MSK 0x00040000
5918 /* The mask used to clear the ALT_QSPI_FLSHCMD_ENMODBIT register field value. */
5919 #define ALT_QSPI_FLSHCMD_ENMODBIT_CLR_MSK 0xfffbffff
5920 /* The reset value of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */
5921 #define ALT_QSPI_FLSHCMD_ENMODBIT_RESET 0x0
5922 /* Extracts the ALT_QSPI_FLSHCMD_ENMODBIT field value from a register. */
5923 #define ALT_QSPI_FLSHCMD_ENMODBIT_GET(value) (((value) & 0x00040000) >> 18)
5924 /* Produces a ALT_QSPI_FLSHCMD_ENMODBIT register field value suitable for setting the register. */
5925 #define ALT_QSPI_FLSHCMD_ENMODBIT_SET(value) (((value) << 18) & 0x00040000)
5926 
5927 /*
5928  * Field : Command Address Enable - encmdaddr
5929  *
5930  * Set to 1 if the command specified in bits 31:24 requires an address. This should
5931  * be setup before triggering the command via writing a 1 to the execute field.
5932  *
5933  * Field Enumeration Values:
5934  *
5935  * Enum | Value | Description
5936  * :----------------------------------|:------|:---------------------------------------
5937  * ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD | 0x0 | No Action
5938  * ALT_QSPI_FLSHCMD_ENCMDADDR_E_END | 0x1 | Command in bits 31:24 requires address
5939  *
5940  * Field Access Macros:
5941  *
5942  */
5943 /*
5944  * Enumerated value for register field ALT_QSPI_FLSHCMD_ENCMDADDR
5945  *
5946  * No Action
5947  */
5948 #define ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD 0x0
5949 /*
5950  * Enumerated value for register field ALT_QSPI_FLSHCMD_ENCMDADDR
5951  *
5952  * Command in bits 31:24 requires address
5953  */
5954 #define ALT_QSPI_FLSHCMD_ENCMDADDR_E_END 0x1
5955 
5956 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */
5957 #define ALT_QSPI_FLSHCMD_ENCMDADDR_LSB 19
5958 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */
5959 #define ALT_QSPI_FLSHCMD_ENCMDADDR_MSB 19
5960 /* The width in bits of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */
5961 #define ALT_QSPI_FLSHCMD_ENCMDADDR_WIDTH 1
5962 /* The mask used to set the ALT_QSPI_FLSHCMD_ENCMDADDR register field value. */
5963 #define ALT_QSPI_FLSHCMD_ENCMDADDR_SET_MSK 0x00080000
5964 /* The mask used to clear the ALT_QSPI_FLSHCMD_ENCMDADDR register field value. */
5965 #define ALT_QSPI_FLSHCMD_ENCMDADDR_CLR_MSK 0xfff7ffff
5966 /* The reset value of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */
5967 #define ALT_QSPI_FLSHCMD_ENCMDADDR_RESET 0x0
5968 /* Extracts the ALT_QSPI_FLSHCMD_ENCMDADDR field value from a register. */
5969 #define ALT_QSPI_FLSHCMD_ENCMDADDR_GET(value) (((value) & 0x00080000) >> 19)
5970 /* Produces a ALT_QSPI_FLSHCMD_ENCMDADDR register field value suitable for setting the register. */
5971 #define ALT_QSPI_FLSHCMD_ENCMDADDR_SET(value) (((value) << 19) & 0x00080000)
5972 
5973 /*
5974  * Field : Number of Read Data Bytes - numrddatabytes
5975  *
5976  * Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for
5977  * 8 bytes.
5978  *
5979  * Field Enumeration Values:
5980  *
5981  * Enum | Value | Description
5982  * :------------------------------------------|:------|:------------
5983  * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 | 0x0 | Read 1 Byte
5984  * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 | 0x1 | Read 2 Byte
5985  * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 | 0x2 | Read 3 Byte
5986  * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 | 0x3 | Read 4 Byte
5987  * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 | 0x4 | Read 5 Byte
5988  * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 | 0x5 | Read 6 Byte
5989  * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 | 0x6 | Read 7 Byte
5990  * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 | 0x7 | Read 8 Byte
5991  *
5992  * Field Access Macros:
5993  *
5994  */
5995 /*
5996  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
5997  *
5998  * Read 1 Byte
5999  */
6000 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 0x0
6001 /*
6002  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
6003  *
6004  * Read 2 Byte
6005  */
6006 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 0x1
6007 /*
6008  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
6009  *
6010  * Read 3 Byte
6011  */
6012 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 0x2
6013 /*
6014  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
6015  *
6016  * Read 4 Byte
6017  */
6018 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 0x3
6019 /*
6020  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
6021  *
6022  * Read 5 Byte
6023  */
6024 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 0x4
6025 /*
6026  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
6027  *
6028  * Read 6 Byte
6029  */
6030 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 0x5
6031 /*
6032  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
6033  *
6034  * Read 7 Byte
6035  */
6036 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 0x6
6037 /*
6038  * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
6039  *
6040  * Read 8 Byte
6041  */
6042 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 0x7
6043 
6044 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */
6045 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_LSB 20
6046 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */
6047 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_MSB 22
6048 /* The width in bits of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */
6049 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_WIDTH 3
6050 /* The mask used to set the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value. */
6051 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET_MSK 0x00700000
6052 /* The mask used to clear the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value. */
6053 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_CLR_MSK 0xff8fffff
6054 /* The reset value of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */
6055 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_RESET 0x0
6056 /* Extracts the ALT_QSPI_FLSHCMD_NUMRDDATABYTES field value from a register. */
6057 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_GET(value) (((value) & 0x00700000) >> 20)
6058 /* Produces a ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value suitable for setting the register. */
6059 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(value) (((value) << 20) & 0x00700000)
6060 
6061 /*
6062  * Field : Read Data Enable - enrddata
6063  *
6064  * Set to 1 if the command specified in the command opcode field (bits 31:24)
6065  * requires read data bytes to be received from the device.
6066  *
6067  * Field Enumeration Values:
6068  *
6069  * Enum | Value | Description
6070  * :-------------------------------------|:------|:---------------------------
6071  * ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION | 0x0 | No Action
6072  * ALT_QSPI_FLSHCMD_ENRDDATA_E_EN | 0x1 | Command Requires read data
6073  *
6074  * Field Access Macros:
6075  *
6076  */
6077 /*
6078  * Enumerated value for register field ALT_QSPI_FLSHCMD_ENRDDATA
6079  *
6080  * No Action
6081  */
6082 #define ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION 0x0
6083 /*
6084  * Enumerated value for register field ALT_QSPI_FLSHCMD_ENRDDATA
6085  *
6086  * Command Requires read data
6087  */
6088 #define ALT_QSPI_FLSHCMD_ENRDDATA_E_EN 0x1
6089 
6090 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */
6091 #define ALT_QSPI_FLSHCMD_ENRDDATA_LSB 23
6092 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */
6093 #define ALT_QSPI_FLSHCMD_ENRDDATA_MSB 23
6094 /* The width in bits of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */
6095 #define ALT_QSPI_FLSHCMD_ENRDDATA_WIDTH 1
6096 /* The mask used to set the ALT_QSPI_FLSHCMD_ENRDDATA register field value. */
6097 #define ALT_QSPI_FLSHCMD_ENRDDATA_SET_MSK 0x00800000
6098 /* The mask used to clear the ALT_QSPI_FLSHCMD_ENRDDATA register field value. */
6099 #define ALT_QSPI_FLSHCMD_ENRDDATA_CLR_MSK 0xff7fffff
6100 /* The reset value of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */
6101 #define ALT_QSPI_FLSHCMD_ENRDDATA_RESET 0x0
6102 /* Extracts the ALT_QSPI_FLSHCMD_ENRDDATA field value from a register. */
6103 #define ALT_QSPI_FLSHCMD_ENRDDATA_GET(value) (((value) & 0x00800000) >> 23)
6104 /* Produces a ALT_QSPI_FLSHCMD_ENRDDATA register field value suitable for setting the register. */
6105 #define ALT_QSPI_FLSHCMD_ENRDDATA_SET(value) (((value) << 23) & 0x00800000)
6106 
6107 /*
6108  * Field : Command Opcode - cmdopcode
6109  *
6110  * The command opcode field should be setup before triggering the command. For
6111  * example, 0x20 maps to SubSector Erase. Writeing to the execute field (bit 0) of
6112  * this register launches the command. NOTE : Using this approach to issue commands
6113  * to the device will make use of the instruction type of the device instruction
6114  * configuration register. If this field is set to 2'b00, then the command opcode,
6115  * command address, command dummy bytes and command data will all be transferred in
6116  * a serial fashion. If this field is set to 2'b01, then the command opcode,
6117  * command address, command dummy bytes and command data will all be transferred in
6118  * parallel using DQ0 and DQ1 pins. If this field is set to 2'b10, then the command
6119  * opcode, command address, command dummy bytes and command data will all be
6120  * transferred in parallel using DQ0, DQ1, DQ2 and DQ3 pins.
6121  *
6122  * Field Access Macros:
6123  *
6124  */
6125 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */
6126 #define ALT_QSPI_FLSHCMD_CMDOPCODE_LSB 24
6127 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */
6128 #define ALT_QSPI_FLSHCMD_CMDOPCODE_MSB 31
6129 /* The width in bits of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */
6130 #define ALT_QSPI_FLSHCMD_CMDOPCODE_WIDTH 8
6131 /* The mask used to set the ALT_QSPI_FLSHCMD_CMDOPCODE register field value. */
6132 #define ALT_QSPI_FLSHCMD_CMDOPCODE_SET_MSK 0xff000000
6133 /* The mask used to clear the ALT_QSPI_FLSHCMD_CMDOPCODE register field value. */
6134 #define ALT_QSPI_FLSHCMD_CMDOPCODE_CLR_MSK 0x00ffffff
6135 /* The reset value of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */
6136 #define ALT_QSPI_FLSHCMD_CMDOPCODE_RESET 0x0
6137 /* Extracts the ALT_QSPI_FLSHCMD_CMDOPCODE field value from a register. */
6138 #define ALT_QSPI_FLSHCMD_CMDOPCODE_GET(value) (((value) & 0xff000000) >> 24)
6139 /* Produces a ALT_QSPI_FLSHCMD_CMDOPCODE register field value suitable for setting the register. */
6140 #define ALT_QSPI_FLSHCMD_CMDOPCODE_SET(value) (((value) << 24) & 0xff000000)
6141 
6142 #ifndef __ASSEMBLY__
6143 /*
6144  * WARNING: The C register and register group struct declarations are provided for
6145  * convenience and illustrative purposes. They should, however, be used with
6146  * caution as the C language standard provides no guarantees about the alignment or
6147  * atomicity of device memory accesses. The recommended practice for writing
6148  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6149  * alt_write_word() functions.
6150  *
6151  * The struct declaration for register ALT_QSPI_FLSHCMD.
6152  */
6153 struct ALT_QSPI_FLSHCMD_s
6154 {
6155  uint32_t execcmd : 1; /* Execute Command */
6156  const uint32_t cmdexecstat : 1; /* Command Execution Status */
6157  const uint32_t flash_cmd_cntrl_resv1_fld : 5; /* Reserved */
6158  uint32_t numdummybytes : 5; /* Number of Dummy Bytes */
6159  uint32_t numwrdatabytes : 3; /* Number of Write Data Bytes */
6160  uint32_t enwrdata : 1; /* Write Data Enable */
6161  uint32_t numaddrbytes : 2; /* Number of Address Bytes */
6162  uint32_t enmodebit : 1; /* Mode Bit Enable */
6163  uint32_t encmdaddr : 1; /* Command Address Enable */
6164  uint32_t numrddatabytes : 3; /* Number of Read Data Bytes */
6165  uint32_t enrddata : 1; /* Read Data Enable */
6166  uint32_t cmdopcode : 8; /* Command Opcode */
6167 };
6168 
6169 /* The typedef declaration for register ALT_QSPI_FLSHCMD. */
6170 typedef volatile struct ALT_QSPI_FLSHCMD_s ALT_QSPI_FLSHCMD_t;
6171 #endif /* __ASSEMBLY__ */
6172 
6173 /* The reset value of the ALT_QSPI_FLSHCMD register. */
6174 #define ALT_QSPI_FLSHCMD_RESET 0x00000000
6175 /* The byte offset of the ALT_QSPI_FLSHCMD register from the beginning of the component. */
6176 #define ALT_QSPI_FLSHCMD_OFST 0x90
6177 
6178 /*
6179  * Register : Flash Command Address Registers - flashcmdaddr
6180  *
6181  * Register Layout
6182  *
6183  * Bits | Access | Reset | Description
6184  * :-------|:-------|:------|:----------------
6185  * [31:0] | RW | 0x0 | Command Address
6186  *
6187  */
6188 /*
6189  * Field : Command Address - addr
6190  *
6191  * This should be setup before triggering the command with execute field (bit 0) of
6192  * the Flash Command Control register. It is the address used by the command
6193  * specified in the opcode field (bits 31:24) of the Flash Command Control
6194  * register.
6195  *
6196  * Field Access Macros:
6197  *
6198  */
6199 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */
6200 #define ALT_QSPI_FLSHCMDADDR_ADDR_LSB 0
6201 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */
6202 #define ALT_QSPI_FLSHCMDADDR_ADDR_MSB 31
6203 /* The width in bits of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */
6204 #define ALT_QSPI_FLSHCMDADDR_ADDR_WIDTH 32
6205 /* The mask used to set the ALT_QSPI_FLSHCMDADDR_ADDR register field value. */
6206 #define ALT_QSPI_FLSHCMDADDR_ADDR_SET_MSK 0xffffffff
6207 /* The mask used to clear the ALT_QSPI_FLSHCMDADDR_ADDR register field value. */
6208 #define ALT_QSPI_FLSHCMDADDR_ADDR_CLR_MSK 0x00000000
6209 /* The reset value of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */
6210 #define ALT_QSPI_FLSHCMDADDR_ADDR_RESET 0x0
6211 /* Extracts the ALT_QSPI_FLSHCMDADDR_ADDR field value from a register. */
6212 #define ALT_QSPI_FLSHCMDADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
6213 /* Produces a ALT_QSPI_FLSHCMDADDR_ADDR register field value suitable for setting the register. */
6214 #define ALT_QSPI_FLSHCMDADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
6215 
6216 #ifndef __ASSEMBLY__
6217 /*
6218  * WARNING: The C register and register group struct declarations are provided for
6219  * convenience and illustrative purposes. They should, however, be used with
6220  * caution as the C language standard provides no guarantees about the alignment or
6221  * atomicity of device memory accesses. The recommended practice for writing
6222  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6223  * alt_write_word() functions.
6224  *
6225  * The struct declaration for register ALT_QSPI_FLSHCMDADDR.
6226  */
6227 struct ALT_QSPI_FLSHCMDADDR_s
6228 {
6229  uint32_t addr : 32; /* Command Address */
6230 };
6231 
6232 /* The typedef declaration for register ALT_QSPI_FLSHCMDADDR. */
6233 typedef volatile struct ALT_QSPI_FLSHCMDADDR_s ALT_QSPI_FLSHCMDADDR_t;
6234 #endif /* __ASSEMBLY__ */
6235 
6236 /* The reset value of the ALT_QSPI_FLSHCMDADDR register. */
6237 #define ALT_QSPI_FLSHCMDADDR_RESET 0x00000000
6238 /* The byte offset of the ALT_QSPI_FLSHCMDADDR register from the beginning of the component. */
6239 #define ALT_QSPI_FLSHCMDADDR_OFST 0x94
6240 
6241 /*
6242  * Register : Flash Command Read Data Register (Lower) - flashcmdrddatalo
6243  *
6244  * Register Layout
6245  *
6246  * Bits | Access | Reset | Description
6247  * :-------|:-------|:------|:-------------------------------
6248  * [31:0] | RW | 0x0 | Command Read Data (Lower byte)
6249  *
6250  */
6251 /*
6252  * Field : Command Read Data (Lower byte) - data
6253  *
6254  * This is the data that is returned by the flash device for any status or
6255  * configuration read operation carried out by triggering the event in the control
6256  * register. The register will be valid when the polling bit in the control
6257  * register is low.
6258  *
6259  * Field Access Macros:
6260  *
6261  */
6262 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */
6263 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_LSB 0
6264 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */
6265 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_MSB 31
6266 /* The width in bits of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */
6267 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_WIDTH 32
6268 /* The mask used to set the ALT_QSPI_FLSHCMDRDDATALO_DATA register field value. */
6269 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET_MSK 0xffffffff
6270 /* The mask used to clear the ALT_QSPI_FLSHCMDRDDATALO_DATA register field value. */
6271 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_CLR_MSK 0x00000000
6272 /* The reset value of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */
6273 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_RESET 0x0
6274 /* Extracts the ALT_QSPI_FLSHCMDRDDATALO_DATA field value from a register. */
6275 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)
6276 /* Produces a ALT_QSPI_FLSHCMDRDDATALO_DATA register field value suitable for setting the register. */
6277 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)
6278 
6279 #ifndef __ASSEMBLY__
6280 /*
6281  * WARNING: The C register and register group struct declarations are provided for
6282  * convenience and illustrative purposes. They should, however, be used with
6283  * caution as the C language standard provides no guarantees about the alignment or
6284  * atomicity of device memory accesses. The recommended practice for writing
6285  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6286  * alt_write_word() functions.
6287  *
6288  * The struct declaration for register ALT_QSPI_FLSHCMDRDDATALO.
6289  */
6290 struct ALT_QSPI_FLSHCMDRDDATALO_s
6291 {
6292  uint32_t data : 32; /* Command Read Data (Lower byte) */
6293 };
6294 
6295 /* The typedef declaration for register ALT_QSPI_FLSHCMDRDDATALO. */
6296 typedef volatile struct ALT_QSPI_FLSHCMDRDDATALO_s ALT_QSPI_FLSHCMDRDDATALO_t;
6297 #endif /* __ASSEMBLY__ */
6298 
6299 /* The reset value of the ALT_QSPI_FLSHCMDRDDATALO register. */
6300 #define ALT_QSPI_FLSHCMDRDDATALO_RESET 0x00000000
6301 /* The byte offset of the ALT_QSPI_FLSHCMDRDDATALO register from the beginning of the component. */
6302 #define ALT_QSPI_FLSHCMDRDDATALO_OFST 0xa0
6303 
6304 /*
6305  * Register : Flash Command Read Data Register (Upper) - flashcmdrddataup
6306  *
6307  * Device Instruction Configuration Register
6308  *
6309  * Register Layout
6310  *
6311  * Bits | Access | Reset | Description
6312  * :-------|:-------|:------|:-------------------------------
6313  * [31:0] | RW | 0x0 | Command Read Data (Upper byte)
6314  *
6315  */
6316 /*
6317  * Field : Command Read Data (Upper byte) - data
6318  *
6319  * This is the data that is returned by the FLASH device for any status or
6320  * configuration read operation carried out by triggering the event in the control
6321  * register. The register will be valid when the polling bit in the control
6322  * register is low.
6323  *
6324  * Field Access Macros:
6325  *
6326  */
6327 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */
6328 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_LSB 0
6329 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */
6330 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_MSB 31
6331 /* The width in bits of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */
6332 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_WIDTH 32
6333 /* The mask used to set the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value. */
6334 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET_MSK 0xffffffff
6335 /* The mask used to clear the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value. */
6336 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_CLR_MSK 0x00000000
6337 /* The reset value of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */
6338 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_RESET 0x0
6339 /* Extracts the ALT_QSPI_FLSHCMDRDDATAUP_DATA field value from a register. */
6340 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)
6341 /* Produces a ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value suitable for setting the register. */
6342 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)
6343 
6344 #ifndef __ASSEMBLY__
6345 /*
6346  * WARNING: The C register and register group struct declarations are provided for
6347  * convenience and illustrative purposes. They should, however, be used with
6348  * caution as the C language standard provides no guarantees about the alignment or
6349  * atomicity of device memory accesses. The recommended practice for writing
6350  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6351  * alt_write_word() functions.
6352  *
6353  * The struct declaration for register ALT_QSPI_FLSHCMDRDDATAUP.
6354  */
6355 struct ALT_QSPI_FLSHCMDRDDATAUP_s
6356 {
6357  uint32_t data : 32; /* Command Read Data (Upper byte) */
6358 };
6359 
6360 /* The typedef declaration for register ALT_QSPI_FLSHCMDRDDATAUP. */
6361 typedef volatile struct ALT_QSPI_FLSHCMDRDDATAUP_s ALT_QSPI_FLSHCMDRDDATAUP_t;
6362 #endif /* __ASSEMBLY__ */
6363 
6364 /* The reset value of the ALT_QSPI_FLSHCMDRDDATAUP register. */
6365 #define ALT_QSPI_FLSHCMDRDDATAUP_RESET 0x00000000
6366 /* The byte offset of the ALT_QSPI_FLSHCMDRDDATAUP register from the beginning of the component. */
6367 #define ALT_QSPI_FLSHCMDRDDATAUP_OFST 0xa4
6368 
6369 /*
6370  * Register : Flash Command Write Data Register (Lower) - flashcmdwrdatalo
6371  *
6372  * Register Layout
6373  *
6374  * Bits | Access | Reset | Description
6375  * :-------|:-------|:------|:------------------------------
6376  * [31:0] | RW | 0x0 | Command Write Data Lower Byte
6377  *
6378  */
6379 /*
6380  * Field : Command Write Data Lower Byte - data
6381  *
6382  * This is the command write data lower byte. This should be setup before
6383  * triggering the command with execute field (bit 0) of the Flash Command Control
6384  * register. It is the data that is to be written to the flash for any status or
6385  * configuration write operation carried out by triggering the event in the Flash
6386  * Command Control register.
6387  *
6388  * Field Access Macros:
6389  *
6390  */
6391 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */
6392 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_LSB 0
6393 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */
6394 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_MSB 31
6395 /* The width in bits of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */
6396 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_WIDTH 32
6397 /* The mask used to set the ALT_QSPI_FLSHCMDWRDATALO_DATA register field value. */
6398 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET_MSK 0xffffffff
6399 /* The mask used to clear the ALT_QSPI_FLSHCMDWRDATALO_DATA register field value. */
6400 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_CLR_MSK 0x00000000
6401 /* The reset value of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */
6402 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_RESET 0x0
6403 /* Extracts the ALT_QSPI_FLSHCMDWRDATALO_DATA field value from a register. */
6404 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)
6405 /* Produces a ALT_QSPI_FLSHCMDWRDATALO_DATA register field value suitable for setting the register. */
6406 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)
6407 
6408 #ifndef __ASSEMBLY__
6409 /*
6410  * WARNING: The C register and register group struct declarations are provided for
6411  * convenience and illustrative purposes. They should, however, be used with
6412  * caution as the C language standard provides no guarantees about the alignment or
6413  * atomicity of device memory accesses. The recommended practice for writing
6414  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6415  * alt_write_word() functions.
6416  *
6417  * The struct declaration for register ALT_QSPI_FLSHCMDWRDATALO.
6418  */
6419 struct ALT_QSPI_FLSHCMDWRDATALO_s
6420 {
6421  uint32_t data : 32; /* Command Write Data Lower Byte */
6422 };
6423 
6424 /* The typedef declaration for register ALT_QSPI_FLSHCMDWRDATALO. */
6425 typedef volatile struct ALT_QSPI_FLSHCMDWRDATALO_s ALT_QSPI_FLSHCMDWRDATALO_t;
6426 #endif /* __ASSEMBLY__ */
6427 
6428 /* The reset value of the ALT_QSPI_FLSHCMDWRDATALO register. */
6429 #define ALT_QSPI_FLSHCMDWRDATALO_RESET 0x00000000
6430 /* The byte offset of the ALT_QSPI_FLSHCMDWRDATALO register from the beginning of the component. */
6431 #define ALT_QSPI_FLSHCMDWRDATALO_OFST 0xa8
6432 
6433 /*
6434  * Register : Flash Command Write Data Register (Upper) - flashcmdwrdataup
6435  *
6436  * Register Layout
6437  *
6438  * Bits | Access | Reset | Description
6439  * :-------|:-------|:------|:------------------------------
6440  * [31:0] | RW | 0x0 | Command Write Data Upper Byte
6441  *
6442  */
6443 /*
6444  * Field : Command Write Data Upper Byte - data
6445  *
6446  * This is the command write data upper byte. This should be setup before
6447  * triggering the command with execute field (bit 0) of the Flash Command Control
6448  * register. It is the data that is to be written to the flash for any status or
6449  * configuration write operation carried out by triggering the event in the Flash
6450  * Command Control register.
6451  *
6452  * Field Access Macros:
6453  *
6454  */
6455 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */
6456 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_LSB 0
6457 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */
6458 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_MSB 31
6459 /* The width in bits of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */
6460 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_WIDTH 32
6461 /* The mask used to set the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value. */
6462 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET_MSK 0xffffffff
6463 /* The mask used to clear the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value. */
6464 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_CLR_MSK 0x00000000
6465 /* The reset value of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */
6466 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_RESET 0x0
6467 /* Extracts the ALT_QSPI_FLSHCMDWRDATAUP_DATA field value from a register. */
6468 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)
6469 /* Produces a ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value suitable for setting the register. */
6470 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)
6471 
6472 #ifndef __ASSEMBLY__
6473 /*
6474  * WARNING: The C register and register group struct declarations are provided for
6475  * convenience and illustrative purposes. They should, however, be used with
6476  * caution as the C language standard provides no guarantees about the alignment or
6477  * atomicity of device memory accesses. The recommended practice for writing
6478  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6479  * alt_write_word() functions.
6480  *
6481  * The struct declaration for register ALT_QSPI_FLSHCMDWRDATAUP.
6482  */
6483 struct ALT_QSPI_FLSHCMDWRDATAUP_s
6484 {
6485  uint32_t data : 32; /* Command Write Data Upper Byte */
6486 };
6487 
6488 /* The typedef declaration for register ALT_QSPI_FLSHCMDWRDATAUP. */
6489 typedef volatile struct ALT_QSPI_FLSHCMDWRDATAUP_s ALT_QSPI_FLSHCMDWRDATAUP_t;
6490 #endif /* __ASSEMBLY__ */
6491 
6492 /* The reset value of the ALT_QSPI_FLSHCMDWRDATAUP register. */
6493 #define ALT_QSPI_FLSHCMDWRDATAUP_RESET 0x00000000
6494 /* The byte offset of the ALT_QSPI_FLSHCMDWRDATAUP register from the beginning of the component. */
6495 #define ALT_QSPI_FLSHCMDWRDATAUP_OFST 0xac
6496 
6497 /*
6498  * Register : Module ID Register - moduleid
6499  *
6500  * Register Layout
6501  *
6502  * Bits | Access | Reset | Description
6503  * :--------|:-------|:-------|:-----------------
6504  * [24:0] | R | 0x1001 | Module ID number
6505  * [31:25] | R | 0x0 | Reserved
6506  *
6507  */
6508 /*
6509  * Field : Module ID number - value
6510  *
6511  * Field Access Macros:
6512  *
6513  */
6514 /* The Least Significant Bit (LSB) position of the ALT_QSPI_MODULEID_VALUE register field. */
6515 #define ALT_QSPI_MODULEID_VALUE_LSB 0
6516 /* The Most Significant Bit (MSB) position of the ALT_QSPI_MODULEID_VALUE register field. */
6517 #define ALT_QSPI_MODULEID_VALUE_MSB 24
6518 /* The width in bits of the ALT_QSPI_MODULEID_VALUE register field. */
6519 #define ALT_QSPI_MODULEID_VALUE_WIDTH 25
6520 /* The mask used to set the ALT_QSPI_MODULEID_VALUE register field value. */
6521 #define ALT_QSPI_MODULEID_VALUE_SET_MSK 0x01ffffff
6522 /* The mask used to clear the ALT_QSPI_MODULEID_VALUE register field value. */
6523 #define ALT_QSPI_MODULEID_VALUE_CLR_MSK 0xfe000000
6524 /* The reset value of the ALT_QSPI_MODULEID_VALUE register field. */
6525 #define ALT_QSPI_MODULEID_VALUE_RESET 0x1001
6526 /* Extracts the ALT_QSPI_MODULEID_VALUE field value from a register. */
6527 #define ALT_QSPI_MODULEID_VALUE_GET(value) (((value) & 0x01ffffff) >> 0)
6528 /* Produces a ALT_QSPI_MODULEID_VALUE register field value suitable for setting the register. */
6529 #define ALT_QSPI_MODULEID_VALUE_SET(value) (((value) << 0) & 0x01ffffff)
6530 
6531 /*
6532  * Field : Reserved - mod_id_resv_fld
6533  *
6534  * Field Access Macros:
6535  *
6536  */
6537 /* The Least Significant Bit (LSB) position of the ALT_QSPI_MODULEID_MOD_ID_RESV_FLD register field. */
6538 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_LSB 25
6539 /* The Most Significant Bit (MSB) position of the ALT_QSPI_MODULEID_MOD_ID_RESV_FLD register field. */
6540 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_MSB 31
6541 /* The width in bits of the ALT_QSPI_MODULEID_MOD_ID_RESV_FLD register field. */
6542 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_WIDTH 7
6543 /* The mask used to set the ALT_QSPI_MODULEID_MOD_ID_RESV_FLD register field value. */
6544 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_SET_MSK 0xfe000000
6545 /* The mask used to clear the ALT_QSPI_MODULEID_MOD_ID_RESV_FLD register field value. */
6546 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_CLR_MSK 0x01ffffff
6547 /* The reset value of the ALT_QSPI_MODULEID_MOD_ID_RESV_FLD register field. */
6548 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_RESET 0x0
6549 /* Extracts the ALT_QSPI_MODULEID_MOD_ID_RESV_FLD field value from a register. */
6550 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_GET(value) (((value) & 0xfe000000) >> 25)
6551 /* Produces a ALT_QSPI_MODULEID_MOD_ID_RESV_FLD register field value suitable for setting the register. */
6552 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_SET(value) (((value) << 25) & 0xfe000000)
6553 
6554 #ifndef __ASSEMBLY__
6555 /*
6556  * WARNING: The C register and register group struct declarations are provided for
6557  * convenience and illustrative purposes. They should, however, be used with
6558  * caution as the C language standard provides no guarantees about the alignment or
6559  * atomicity of device memory accesses. The recommended practice for writing
6560  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6561  * alt_write_word() functions.
6562  *
6563  * The struct declaration for register ALT_QSPI_MODULEID.
6564  */
6565 struct ALT_QSPI_MODULEID_s
6566 {
6567  const uint32_t value : 25; /* Module ID number */
6568  const uint32_t mod_id_resv_fld : 7; /* Reserved */
6569 };
6570 
6571 /* The typedef declaration for register ALT_QSPI_MODULEID. */
6572 typedef volatile struct ALT_QSPI_MODULEID_s ALT_QSPI_MODULEID_t;
6573 #endif /* __ASSEMBLY__ */
6574 
6575 /* The reset value of the ALT_QSPI_MODULEID register. */
6576 #define ALT_QSPI_MODULEID_RESET 0x00001001
6577 /* The byte offset of the ALT_QSPI_MODULEID register from the beginning of the component. */
6578 #define ALT_QSPI_MODULEID_OFST 0xfc
6579 
6580 #ifndef __ASSEMBLY__
6581 /*
6582  * WARNING: The C register and register group struct declarations are provided for
6583  * convenience and illustrative purposes. They should, however, be used with
6584  * caution as the C language standard provides no guarantees about the alignment or
6585  * atomicity of device memory accesses. The recommended practice for writing
6586  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6587  * alt_write_word() functions.
6588  *
6589  * The struct declaration for register group ALT_QSPI.
6590  */
6591 struct ALT_QSPI_s
6592 {
6593  ALT_QSPI_CFG_t cfg; /* ALT_QSPI_CFG */
6594  ALT_QSPI_DEVRD_t devrd; /* ALT_QSPI_DEVRD */
6595  ALT_QSPI_DEVWR_t devwr; /* ALT_QSPI_DEVWR */
6596  ALT_QSPI_DELAY_t delay; /* ALT_QSPI_DELAY */
6597  ALT_QSPI_RDDATACAP_t rddatacap; /* ALT_QSPI_RDDATACAP */
6598  ALT_QSPI_DEVSZ_t devsz; /* ALT_QSPI_DEVSZ */
6599  ALT_QSPI_SRAMPART_t srampart; /* ALT_QSPI_SRAMPART */
6600  ALT_QSPI_INDADDRTRIG_t indaddrtrig; /* ALT_QSPI_INDADDRTRIG */
6601  ALT_QSPI_DMAPER_t dmaper; /* ALT_QSPI_DMAPER */
6602  ALT_QSPI_REMAPADDR_t remapaddr; /* ALT_QSPI_REMAPADDR */
6603  ALT_QSPI_MODBIT_t modebit; /* ALT_QSPI_MODBIT */
6604  ALT_QSPI_SRAMFILL_t sramfill; /* ALT_QSPI_SRAMFILL */
6605  ALT_QSPI_TXTHRESH_t txthresh; /* ALT_QSPI_TXTHRESH */
6606  ALT_QSPI_RXTHRESH_t rxthresh; /* ALT_QSPI_RXTHRESH */
6607  volatile uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */
6608  ALT_QSPI_IRQSTAT_t irqstat; /* ALT_QSPI_IRQSTAT */
6609  ALT_QSPI_IRQMSK_t irqmask; /* ALT_QSPI_IRQMSK */
6610  volatile uint32_t _pad_0x48_0x4f[2]; /* *UNDEFINED* */
6611  ALT_QSPI_LOWWRPROT_t lowwrprot; /* ALT_QSPI_LOWWRPROT */
6612  ALT_QSPI_UPPWRPROT_t uppwrprot; /* ALT_QSPI_UPPWRPROT */
6613  ALT_QSPI_WRPROT_t wrprot; /* ALT_QSPI_WRPROT */
6614  volatile uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */
6615  ALT_QSPI_INDRD_t indrd; /* ALT_QSPI_INDRD */
6616  ALT_QSPI_INDRDWATER_t indrdwater; /* ALT_QSPI_INDRDWATER */
6617  ALT_QSPI_INDRDSTADDR_t indrdstaddr; /* ALT_QSPI_INDRDSTADDR */
6618  ALT_QSPI_INDRDCNT_t indrdcnt; /* ALT_QSPI_INDRDCNT */
6619  ALT_QSPI_INDWR_t indwr; /* ALT_QSPI_INDWR */
6620  ALT_QSPI_INDWRWATER_t indwrwater; /* ALT_QSPI_INDWRWATER */
6621  ALT_QSPI_INDWRSTADDR_t indwrstaddr; /* ALT_QSPI_INDWRSTADDR */
6622  ALT_QSPI_INDWRCNT_t indwrcnt; /* ALT_QSPI_INDWRCNT */
6623  volatile uint32_t _pad_0x80_0x8f[4]; /* *UNDEFINED* */
6624  ALT_QSPI_FLSHCMD_t flashcmd; /* ALT_QSPI_FLSHCMD */
6625  ALT_QSPI_FLSHCMDADDR_t flashcmdaddr; /* ALT_QSPI_FLSHCMDADDR */
6626  volatile uint32_t _pad_0x98_0x9f[2]; /* *UNDEFINED* */
6627  ALT_QSPI_FLSHCMDRDDATALO_t flashcmdrddatalo; /* ALT_QSPI_FLSHCMDRDDATALO */
6628  ALT_QSPI_FLSHCMDRDDATAUP_t flashcmdrddataup; /* ALT_QSPI_FLSHCMDRDDATAUP */
6629  ALT_QSPI_FLSHCMDWRDATALO_t flashcmdwrdatalo; /* ALT_QSPI_FLSHCMDWRDATALO */
6630  ALT_QSPI_FLSHCMDWRDATAUP_t flashcmdwrdataup; /* ALT_QSPI_FLSHCMDWRDATAUP */
6631  volatile uint32_t _pad_0xb0_0xfb[19]; /* *UNDEFINED* */
6632  ALT_QSPI_MODULEID_t moduleid; /* ALT_QSPI_MODULEID */
6633 };
6634 
6635 /* The typedef declaration for register group ALT_QSPI. */
6636 typedef volatile struct ALT_QSPI_s ALT_QSPI_t;
6637 /* The struct declaration for the raw register contents of register group ALT_QSPI. */
6638 struct ALT_QSPI_raw_s
6639 {
6640  volatile uint32_t cfg; /* ALT_QSPI_CFG */
6641  volatile uint32_t devrd; /* ALT_QSPI_DEVRD */
6642  volatile uint32_t devwr; /* ALT_QSPI_DEVWR */
6643  volatile uint32_t delay; /* ALT_QSPI_DELAY */
6644  volatile uint32_t rddatacap; /* ALT_QSPI_RDDATACAP */
6645  volatile uint32_t devsz; /* ALT_QSPI_DEVSZ */
6646  volatile uint32_t srampart; /* ALT_QSPI_SRAMPART */
6647  volatile uint32_t indaddrtrig; /* ALT_QSPI_INDADDRTRIG */
6648  volatile uint32_t dmaper; /* ALT_QSPI_DMAPER */
6649  volatile uint32_t remapaddr; /* ALT_QSPI_REMAPADDR */
6650  volatile uint32_t modebit; /* ALT_QSPI_MODBIT */
6651  volatile uint32_t sramfill; /* ALT_QSPI_SRAMFILL */
6652  volatile uint32_t txthresh; /* ALT_QSPI_TXTHRESH */
6653  volatile uint32_t rxthresh; /* ALT_QSPI_RXTHRESH */
6654  uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */
6655  volatile uint32_t irqstat; /* ALT_QSPI_IRQSTAT */
6656  volatile uint32_t irqmask; /* ALT_QSPI_IRQMSK */
6657  uint32_t _pad_0x48_0x4f[2]; /* *UNDEFINED* */
6658  volatile uint32_t lowwrprot; /* ALT_QSPI_LOWWRPROT */
6659  volatile uint32_t uppwrprot; /* ALT_QSPI_UPPWRPROT */
6660  volatile uint32_t wrprot; /* ALT_QSPI_WRPROT */
6661  uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */
6662  volatile uint32_t indrd; /* ALT_QSPI_INDRD */
6663  volatile uint32_t indrdwater; /* ALT_QSPI_INDRDWATER */
6664  volatile uint32_t indrdstaddr; /* ALT_QSPI_INDRDSTADDR */
6665  volatile uint32_t indrdcnt; /* ALT_QSPI_INDRDCNT */
6666  volatile uint32_t indwr; /* ALT_QSPI_INDWR */
6667  volatile uint32_t indwrwater; /* ALT_QSPI_INDWRWATER */
6668  volatile uint32_t indwrstaddr; /* ALT_QSPI_INDWRSTADDR */
6669  volatile uint32_t indwrcnt; /* ALT_QSPI_INDWRCNT */
6670  uint32_t _pad_0x80_0x8f[4]; /* *UNDEFINED* */
6671  volatile uint32_t flashcmd; /* ALT_QSPI_FLSHCMD */
6672  volatile uint32_t flashcmdaddr; /* ALT_QSPI_FLSHCMDADDR */
6673  uint32_t _pad_0x98_0x9f[2]; /* *UNDEFINED* */
6674  volatile uint32_t flashcmdrddatalo; /* ALT_QSPI_FLSHCMDRDDATALO */
6675  volatile uint32_t flashcmdrddataup; /* ALT_QSPI_FLSHCMDRDDATAUP */
6676  volatile uint32_t flashcmdwrdatalo; /* ALT_QSPI_FLSHCMDWRDATALO */
6677  volatile uint32_t flashcmdwrdataup; /* ALT_QSPI_FLSHCMDWRDATAUP */
6678  uint32_t _pad_0xb0_0xfb[19]; /* *UNDEFINED* */
6679  volatile uint32_t moduleid; /* ALT_QSPI_MODULEID */
6680 };
6681 
6682 /* The typedef declaration for the raw register contents of register group ALT_QSPI. */
6683 typedef volatile struct ALT_QSPI_raw_s ALT_QSPI_raw_t;
6684 #endif /* __ASSEMBLY__ */
6685 
6686 
6687 #ifdef __cplusplus
6688 }
6689 #endif /* __cplusplus */
6690 #endif /* __ALT_SOCAL_QSPI_H__ */
6691