Hardware Libraries  20.1
Arria 10 SoC Abstration Layer
 All Groups
alt_noc_fw_l4_sys_scr.h
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32 
33 /* Altera - ALT_NOC_FW_L4_SYS_SCR */
34 
35 #ifndef __ALT_SOCAL_NOC_FW_L4_SYS_SCR_H__
36 #define __ALT_SOCAL_NOC_FW_L4_SYS_SCR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_NOC_FW_L4_SYS_SCR
50  *
51  */
52 /*
53  * Register : can0_ecc
54  *
55  * Per-Master Security bit for can0_ecc
56  *
57  * Register Layout
58  *
59  * Bits | Access | Reset | Description
60  * :-------|:-------|:------|:------------------------------------
61  * [31:0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD
62  *
63  */
64 /*
65  * Field : Reserved
66  *
67  * Field Access Macros:
68  *
69  */
70 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD register field. */
71 #define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_LSB 0
72 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD register field. */
73 #define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_MSB 31
74 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD register field. */
75 #define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_WIDTH 32
76 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD register field value. */
77 #define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_SET_MSK 0xffffffff
78 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD register field value. */
79 #define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_CLR_MSK 0x00000000
80 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD register field. */
81 #define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_RESET 0x0
82 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD field value from a register. */
83 #define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
84 /* Produces a ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD register field value suitable for setting the register. */
85 #define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_SET(value) (((value) << 0) & 0xffffffff)
86 
87 #ifndef __ASSEMBLY__
88 /*
89  * WARNING: The C register and register group struct declarations are provided for
90  * convenience and illustrative purposes. They should, however, be used with
91  * caution as the C language standard provides no guarantees about the alignment or
92  * atomicity of device memory accesses. The recommended practice for writing
93  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
94  * alt_write_word() functions.
95  *
96  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC.
97  */
98 struct ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_s
99 {
100  uint32_t Reserved : 32; /* ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD */
101 };
102 
103 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC. */
104 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_s ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_t;
105 #endif /* __ASSEMBLY__ */
106 
107 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC register. */
108 #define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RESET 0x00000000
109 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC register from the beginning of the component. */
110 #define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_OFST 0x0
111 
112 /*
113  * Register : can1_ecc
114  *
115  * Per-Master Security bit for can1_ecc
116  *
117  * Register Layout
118  *
119  * Bits | Access | Reset | Description
120  * :-------|:-------|:------|:------------------------------------
121  * [31:0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD
122  *
123  */
124 /*
125  * Field : Reserved
126  *
127  * Field Access Macros:
128  *
129  */
130 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD register field. */
131 #define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_LSB 0
132 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD register field. */
133 #define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_MSB 31
134 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD register field. */
135 #define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_WIDTH 32
136 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD register field value. */
137 #define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_SET_MSK 0xffffffff
138 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD register field value. */
139 #define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_CLR_MSK 0x00000000
140 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD register field. */
141 #define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_RESET 0x0
142 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD field value from a register. */
143 #define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
144 /* Produces a ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD register field value suitable for setting the register. */
145 #define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_SET(value) (((value) << 0) & 0xffffffff)
146 
147 #ifndef __ASSEMBLY__
148 /*
149  * WARNING: The C register and register group struct declarations are provided for
150  * convenience and illustrative purposes. They should, however, be used with
151  * caution as the C language standard provides no guarantees about the alignment or
152  * atomicity of device memory accesses. The recommended practice for writing
153  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
154  * alt_write_word() functions.
155  *
156  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC.
157  */
158 struct ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_s
159 {
160  uint32_t Reserved : 32; /* ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD */
161 };
162 
163 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC. */
164 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_s ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_t;
165 #endif /* __ASSEMBLY__ */
166 
167 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC register. */
168 #define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RESET 0x00000000
169 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC register from the beginning of the component. */
170 #define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_OFST 0x4
171 
172 /*
173  * Register : dma_ecc
174  *
175  * Per-Master Security bit for dma_ecc
176  *
177  * Register Layout
178  *
179  * Bits | Access | Reset | Description
180  * :--------|:-------|:--------|:-------------------------------------
181  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0
182  * [15:1] | ??? | Unknown | *UNDEFINED*
183  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H
184  * [23:17] | ??? | Unknown | *UNDEFINED*
185  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP
186  * [31:25] | ??? | Unknown | *UNDEFINED*
187  *
188  */
189 /*
190  * Field : mpu_m0
191  *
192  * Security bit configuration for transactions from mpu_m0 to dma_ecc. When cleared
193  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
194  * Secure transactions are allowed.
195  *
196  * Field Access Macros:
197  *
198  */
199 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0 register field. */
200 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_LSB 0
201 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0 register field. */
202 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_MSB 0
203 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0 register field. */
204 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_WIDTH 1
205 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0 register field value. */
206 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_SET_MSK 0x00000001
207 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0 register field value. */
208 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_CLR_MSK 0xfffffffe
209 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0 register field. */
210 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_RESET 0x0
211 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0 field value from a register. */
212 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
213 /* Produces a ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0 register field value suitable for setting the register. */
214 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
215 
216 /*
217  * Field : fpga2soc
218  *
219  * Security bit configuration for transactions from fpga2soc to dma_ecc. When
220  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
221  * Non-Secure transactions are allowed.
222  *
223  * Field Access Macros:
224  *
225  */
226 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H register field. */
227 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_LSB 16
228 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H register field. */
229 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_MSB 16
230 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H register field. */
231 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_WIDTH 1
232 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H register field value. */
233 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_SET_MSK 0x00010000
234 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H register field value. */
235 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_CLR_MSK 0xfffeffff
236 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H register field. */
237 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_RESET 0x0
238 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H field value from a register. */
239 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
240 /* Produces a ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H register field value suitable for setting the register. */
241 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
242 
243 /*
244  * Field : ahb_ap
245  *
246  * Security bit configuration for transactions from ahb_ap to dma_ecc. When cleared
247  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
248  * Secure transactions are allowed.
249  *
250  * Field Access Macros:
251  *
252  */
253 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP register field. */
254 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_LSB 24
255 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP register field. */
256 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_MSB 24
257 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP register field. */
258 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_WIDTH 1
259 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP register field value. */
260 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_SET_MSK 0x01000000
261 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP register field value. */
262 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_CLR_MSK 0xfeffffff
263 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP register field. */
264 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_RESET 0x0
265 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP field value from a register. */
266 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
267 /* Produces a ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP register field value suitable for setting the register. */
268 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
269 
270 #ifndef __ASSEMBLY__
271 /*
272  * WARNING: The C register and register group struct declarations are provided for
273  * convenience and illustrative purposes. They should, however, be used with
274  * caution as the C language standard provides no guarantees about the alignment or
275  * atomicity of device memory accesses. The recommended practice for writing
276  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
277  * alt_write_word() functions.
278  *
279  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_DMA_ECC.
280  */
281 struct ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_s
282 {
283  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0 */
284  uint32_t : 15; /* *UNDEFINED* */
285  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H */
286  uint32_t : 7; /* *UNDEFINED* */
287  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP */
288  uint32_t : 7; /* *UNDEFINED* */
289 };
290 
291 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_DMA_ECC. */
292 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_s ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_t;
293 #endif /* __ASSEMBLY__ */
294 
295 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC register. */
296 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_RESET 0x00000000
297 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC register from the beginning of the component. */
298 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_OFST 0x8
299 
300 /*
301  * Register : emac0rx_ecc
302  *
303  * Per-Master Security bit for emac0rx_ecc
304  *
305  * Register Layout
306  *
307  * Bits | Access | Reset | Description
308  * :--------|:-------|:--------|:-----------------------------------------
309  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0
310  * [15:1] | ??? | Unknown | *UNDEFINED*
311  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H
312  * [23:17] | ??? | Unknown | *UNDEFINED*
313  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP
314  * [31:25] | ??? | Unknown | *UNDEFINED*
315  *
316  */
317 /*
318  * Field : mpu_m0
319  *
320  * Security bit configuration for transactions from mpu_m0 to emac0rx_ecc. When
321  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
322  * Non-Secure transactions are allowed.
323  *
324  * Field Access Macros:
325  *
326  */
327 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0 register field. */
328 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_LSB 0
329 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0 register field. */
330 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_MSB 0
331 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0 register field. */
332 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_WIDTH 1
333 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0 register field value. */
334 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_SET_MSK 0x00000001
335 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0 register field value. */
336 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_CLR_MSK 0xfffffffe
337 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0 register field. */
338 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_RESET 0x0
339 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0 field value from a register. */
340 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
341 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0 register field value suitable for setting the register. */
342 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
343 
344 /*
345  * Field : fpga2soc
346  *
347  * Security bit configuration for transactions from fpga2soc to emac0rx_ecc. When
348  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
349  * Non-Secure transactions are allowed.
350  *
351  * Field Access Macros:
352  *
353  */
354 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H register field. */
355 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_LSB 16
356 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H register field. */
357 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_MSB 16
358 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H register field. */
359 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_WIDTH 1
360 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H register field value. */
361 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_SET_MSK 0x00010000
362 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H register field value. */
363 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_CLR_MSK 0xfffeffff
364 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H register field. */
365 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_RESET 0x0
366 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H field value from a register. */
367 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
368 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H register field value suitable for setting the register. */
369 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
370 
371 /*
372  * Field : ahb_ap
373  *
374  * Security bit configuration for transactions from ahb_ap to emac0rx_ecc. When
375  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
376  * Non-Secure transactions are allowed.
377  *
378  * Field Access Macros:
379  *
380  */
381 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP register field. */
382 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_LSB 24
383 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP register field. */
384 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_MSB 24
385 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP register field. */
386 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_WIDTH 1
387 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP register field value. */
388 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_SET_MSK 0x01000000
389 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP register field value. */
390 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_CLR_MSK 0xfeffffff
391 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP register field. */
392 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_RESET 0x0
393 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP field value from a register. */
394 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
395 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP register field value suitable for setting the register. */
396 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
397 
398 #ifndef __ASSEMBLY__
399 /*
400  * WARNING: The C register and register group struct declarations are provided for
401  * convenience and illustrative purposes. They should, however, be used with
402  * caution as the C language standard provides no guarantees about the alignment or
403  * atomicity of device memory accesses. The recommended practice for writing
404  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
405  * alt_write_word() functions.
406  *
407  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC.
408  */
409 struct ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_s
410 {
411  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0 */
412  uint32_t : 15; /* *UNDEFINED* */
413  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H */
414  uint32_t : 7; /* *UNDEFINED* */
415  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP */
416  uint32_t : 7; /* *UNDEFINED* */
417 };
418 
419 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC. */
420 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_t;
421 #endif /* __ASSEMBLY__ */
422 
423 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC register. */
424 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_RESET 0x00000000
425 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC register from the beginning of the component. */
426 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_OFST 0xc
427 
428 /*
429  * Register : emac0tx_ecc
430  *
431  * Per-Master Security bit for emac0tx_ecc
432  *
433  * Register Layout
434  *
435  * Bits | Access | Reset | Description
436  * :--------|:-------|:--------|:-----------------------------------------
437  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0
438  * [15:1] | ??? | Unknown | *UNDEFINED*
439  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H
440  * [23:17] | ??? | Unknown | *UNDEFINED*
441  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP
442  * [31:25] | ??? | Unknown | *UNDEFINED*
443  *
444  */
445 /*
446  * Field : mpu_m0
447  *
448  * Security bit configuration for transactions from mpu_m0 to emac0tx_ecc. When
449  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
450  * Non-Secure transactions are allowed.
451  *
452  * Field Access Macros:
453  *
454  */
455 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0 register field. */
456 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_LSB 0
457 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0 register field. */
458 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_MSB 0
459 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0 register field. */
460 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_WIDTH 1
461 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0 register field value. */
462 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_SET_MSK 0x00000001
463 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0 register field value. */
464 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_CLR_MSK 0xfffffffe
465 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0 register field. */
466 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_RESET 0x0
467 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0 field value from a register. */
468 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
469 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0 register field value suitable for setting the register. */
470 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
471 
472 /*
473  * Field : fpga2soc
474  *
475  * Security bit configuration for transactions from fpga2soc to emac0tx_ecc. When
476  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
477  * Non-Secure transactions are allowed.
478  *
479  * Field Access Macros:
480  *
481  */
482 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H register field. */
483 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_LSB 16
484 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H register field. */
485 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_MSB 16
486 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H register field. */
487 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_WIDTH 1
488 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H register field value. */
489 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_SET_MSK 0x00010000
490 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H register field value. */
491 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_CLR_MSK 0xfffeffff
492 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H register field. */
493 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_RESET 0x0
494 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H field value from a register. */
495 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
496 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H register field value suitable for setting the register. */
497 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
498 
499 /*
500  * Field : ahb_ap
501  *
502  * Security bit configuration for transactions from ahb_ap to emac0tx_ecc. When
503  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
504  * Non-Secure transactions are allowed.
505  *
506  * Field Access Macros:
507  *
508  */
509 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP register field. */
510 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_LSB 24
511 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP register field. */
512 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_MSB 24
513 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP register field. */
514 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_WIDTH 1
515 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP register field value. */
516 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_SET_MSK 0x01000000
517 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP register field value. */
518 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_CLR_MSK 0xfeffffff
519 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP register field. */
520 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_RESET 0x0
521 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP field value from a register. */
522 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
523 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP register field value suitable for setting the register. */
524 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
525 
526 #ifndef __ASSEMBLY__
527 /*
528  * WARNING: The C register and register group struct declarations are provided for
529  * convenience and illustrative purposes. They should, however, be used with
530  * caution as the C language standard provides no guarantees about the alignment or
531  * atomicity of device memory accesses. The recommended practice for writing
532  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
533  * alt_write_word() functions.
534  *
535  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC.
536  */
537 struct ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_s
538 {
539  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0 */
540  uint32_t : 15; /* *UNDEFINED* */
541  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H */
542  uint32_t : 7; /* *UNDEFINED* */
543  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP */
544  uint32_t : 7; /* *UNDEFINED* */
545 };
546 
547 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC. */
548 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_t;
549 #endif /* __ASSEMBLY__ */
550 
551 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC register. */
552 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_RESET 0x00000000
553 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC register from the beginning of the component. */
554 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_OFST 0x10
555 
556 /*
557  * Register : emac1rx_ecc
558  *
559  * Per-Master Security bit for emac1rx_ecc
560  *
561  * Register Layout
562  *
563  * Bits | Access | Reset | Description
564  * :--------|:-------|:--------|:-----------------------------------------
565  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0
566  * [15:1] | ??? | Unknown | *UNDEFINED*
567  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H
568  * [23:17] | ??? | Unknown | *UNDEFINED*
569  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP
570  * [31:25] | ??? | Unknown | *UNDEFINED*
571  *
572  */
573 /*
574  * Field : mpu_m0
575  *
576  * Security bit configuration for transactions from mpu_m0 to emac1rx_ecc. When
577  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
578  * Non-Secure transactions are allowed.
579  *
580  * Field Access Macros:
581  *
582  */
583 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0 register field. */
584 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_LSB 0
585 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0 register field. */
586 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_MSB 0
587 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0 register field. */
588 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_WIDTH 1
589 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0 register field value. */
590 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_SET_MSK 0x00000001
591 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0 register field value. */
592 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_CLR_MSK 0xfffffffe
593 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0 register field. */
594 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_RESET 0x0
595 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0 field value from a register. */
596 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
597 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0 register field value suitable for setting the register. */
598 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
599 
600 /*
601  * Field : fpga2soc
602  *
603  * Security bit configuration for transactions from fpga2soc to emac1rx_ecc. When
604  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
605  * Non-Secure transactions are allowed.
606  *
607  * Field Access Macros:
608  *
609  */
610 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H register field. */
611 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_LSB 16
612 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H register field. */
613 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_MSB 16
614 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H register field. */
615 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_WIDTH 1
616 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H register field value. */
617 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_SET_MSK 0x00010000
618 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H register field value. */
619 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_CLR_MSK 0xfffeffff
620 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H register field. */
621 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_RESET 0x0
622 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H field value from a register. */
623 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
624 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H register field value suitable for setting the register. */
625 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
626 
627 /*
628  * Field : ahb_ap
629  *
630  * Security bit configuration for transactions from ahb_ap to emac1rx_ecc. When
631  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
632  * Non-Secure transactions are allowed.
633  *
634  * Field Access Macros:
635  *
636  */
637 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP register field. */
638 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_LSB 24
639 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP register field. */
640 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_MSB 24
641 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP register field. */
642 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_WIDTH 1
643 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP register field value. */
644 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_SET_MSK 0x01000000
645 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP register field value. */
646 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_CLR_MSK 0xfeffffff
647 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP register field. */
648 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_RESET 0x0
649 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP field value from a register. */
650 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
651 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP register field value suitable for setting the register. */
652 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
653 
654 #ifndef __ASSEMBLY__
655 /*
656  * WARNING: The C register and register group struct declarations are provided for
657  * convenience and illustrative purposes. They should, however, be used with
658  * caution as the C language standard provides no guarantees about the alignment or
659  * atomicity of device memory accesses. The recommended practice for writing
660  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
661  * alt_write_word() functions.
662  *
663  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC.
664  */
665 struct ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_s
666 {
667  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0 */
668  uint32_t : 15; /* *UNDEFINED* */
669  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H */
670  uint32_t : 7; /* *UNDEFINED* */
671  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP */
672  uint32_t : 7; /* *UNDEFINED* */
673 };
674 
675 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC. */
676 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_t;
677 #endif /* __ASSEMBLY__ */
678 
679 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC register. */
680 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_RESET 0x00000000
681 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC register from the beginning of the component. */
682 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_OFST 0x14
683 
684 /*
685  * Register : emac1tx_ecc
686  *
687  * Per-Master Security bit for emac1tx_ecc
688  *
689  * Register Layout
690  *
691  * Bits | Access | Reset | Description
692  * :--------|:-------|:--------|:-----------------------------------------
693  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0
694  * [15:1] | ??? | Unknown | *UNDEFINED*
695  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H
696  * [23:17] | ??? | Unknown | *UNDEFINED*
697  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP
698  * [31:25] | ??? | Unknown | *UNDEFINED*
699  *
700  */
701 /*
702  * Field : mpu_m0
703  *
704  * Security bit configuration for transactions from mpu_m0 to emac1tx_ecc. When
705  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
706  * Non-Secure transactions are allowed.
707  *
708  * Field Access Macros:
709  *
710  */
711 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0 register field. */
712 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_LSB 0
713 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0 register field. */
714 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_MSB 0
715 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0 register field. */
716 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_WIDTH 1
717 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0 register field value. */
718 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_SET_MSK 0x00000001
719 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0 register field value. */
720 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_CLR_MSK 0xfffffffe
721 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0 register field. */
722 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_RESET 0x0
723 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0 field value from a register. */
724 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
725 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0 register field value suitable for setting the register. */
726 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
727 
728 /*
729  * Field : fpga2soc
730  *
731  * Security bit configuration for transactions from fpga2soc to emac1tx_ecc. When
732  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
733  * Non-Secure transactions are allowed.
734  *
735  * Field Access Macros:
736  *
737  */
738 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H register field. */
739 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_LSB 16
740 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H register field. */
741 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_MSB 16
742 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H register field. */
743 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_WIDTH 1
744 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H register field value. */
745 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_SET_MSK 0x00010000
746 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H register field value. */
747 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_CLR_MSK 0xfffeffff
748 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H register field. */
749 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_RESET 0x0
750 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H field value from a register. */
751 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
752 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H register field value suitable for setting the register. */
753 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
754 
755 /*
756  * Field : ahb_ap
757  *
758  * Security bit configuration for transactions from ahb_ap to emac1tx_ecc. When
759  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
760  * Non-Secure transactions are allowed.
761  *
762  * Field Access Macros:
763  *
764  */
765 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP register field. */
766 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_LSB 24
767 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP register field. */
768 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_MSB 24
769 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP register field. */
770 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_WIDTH 1
771 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP register field value. */
772 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_SET_MSK 0x01000000
773 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP register field value. */
774 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_CLR_MSK 0xfeffffff
775 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP register field. */
776 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_RESET 0x0
777 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP field value from a register. */
778 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
779 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP register field value suitable for setting the register. */
780 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
781 
782 #ifndef __ASSEMBLY__
783 /*
784  * WARNING: The C register and register group struct declarations are provided for
785  * convenience and illustrative purposes. They should, however, be used with
786  * caution as the C language standard provides no guarantees about the alignment or
787  * atomicity of device memory accesses. The recommended practice for writing
788  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
789  * alt_write_word() functions.
790  *
791  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC.
792  */
793 struct ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_s
794 {
795  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0 */
796  uint32_t : 15; /* *UNDEFINED* */
797  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H */
798  uint32_t : 7; /* *UNDEFINED* */
799  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP */
800  uint32_t : 7; /* *UNDEFINED* */
801 };
802 
803 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC. */
804 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_t;
805 #endif /* __ASSEMBLY__ */
806 
807 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC register. */
808 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_RESET 0x00000000
809 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC register from the beginning of the component. */
810 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_OFST 0x18
811 
812 /*
813  * Register : emac2rx_ecc
814  *
815  * Per-Master Security bit for emac2rx_ecc
816  *
817  * Register Layout
818  *
819  * Bits | Access | Reset | Description
820  * :--------|:-------|:--------|:-----------------------------------------
821  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0
822  * [15:1] | ??? | Unknown | *UNDEFINED*
823  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H
824  * [23:17] | ??? | Unknown | *UNDEFINED*
825  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP
826  * [31:25] | ??? | Unknown | *UNDEFINED*
827  *
828  */
829 /*
830  * Field : mpu_m0
831  *
832  * Security bit configuration for transactions from mpu_m0 to emac2rx_ecc. When
833  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
834  * Non-Secure transactions are allowed.
835  *
836  * Field Access Macros:
837  *
838  */
839 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0 register field. */
840 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_LSB 0
841 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0 register field. */
842 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_MSB 0
843 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0 register field. */
844 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_WIDTH 1
845 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0 register field value. */
846 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_SET_MSK 0x00000001
847 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0 register field value. */
848 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_CLR_MSK 0xfffffffe
849 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0 register field. */
850 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_RESET 0x0
851 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0 field value from a register. */
852 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
853 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0 register field value suitable for setting the register. */
854 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
855 
856 /*
857  * Field : fpga2soc
858  *
859  * Security bit configuration for transactions from fpga2soc to emac2rx_ecc. When
860  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
861  * Non-Secure transactions are allowed.
862  *
863  * Field Access Macros:
864  *
865  */
866 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H register field. */
867 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_LSB 16
868 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H register field. */
869 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_MSB 16
870 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H register field. */
871 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_WIDTH 1
872 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H register field value. */
873 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_SET_MSK 0x00010000
874 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H register field value. */
875 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_CLR_MSK 0xfffeffff
876 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H register field. */
877 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_RESET 0x0
878 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H field value from a register. */
879 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
880 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H register field value suitable for setting the register. */
881 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
882 
883 /*
884  * Field : ahb_ap
885  *
886  * Security bit configuration for transactions from ahb_ap to emac2rx_ecc. When
887  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
888  * Non-Secure transactions are allowed.
889  *
890  * Field Access Macros:
891  *
892  */
893 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP register field. */
894 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_LSB 24
895 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP register field. */
896 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_MSB 24
897 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP register field. */
898 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_WIDTH 1
899 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP register field value. */
900 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_SET_MSK 0x01000000
901 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP register field value. */
902 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_CLR_MSK 0xfeffffff
903 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP register field. */
904 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_RESET 0x0
905 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP field value from a register. */
906 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
907 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP register field value suitable for setting the register. */
908 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
909 
910 #ifndef __ASSEMBLY__
911 /*
912  * WARNING: The C register and register group struct declarations are provided for
913  * convenience and illustrative purposes. They should, however, be used with
914  * caution as the C language standard provides no guarantees about the alignment or
915  * atomicity of device memory accesses. The recommended practice for writing
916  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
917  * alt_write_word() functions.
918  *
919  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC.
920  */
921 struct ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_s
922 {
923  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0 */
924  uint32_t : 15; /* *UNDEFINED* */
925  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H */
926  uint32_t : 7; /* *UNDEFINED* */
927  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP */
928  uint32_t : 7; /* *UNDEFINED* */
929 };
930 
931 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC. */
932 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_t;
933 #endif /* __ASSEMBLY__ */
934 
935 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC register. */
936 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_RESET 0x00000000
937 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC register from the beginning of the component. */
938 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_OFST 0x1c
939 
940 /*
941  * Register : emac2tx_ecc
942  *
943  * Per-Master Security bit for emac2tx_ecc
944  *
945  * Register Layout
946  *
947  * Bits | Access | Reset | Description
948  * :--------|:-------|:--------|:-----------------------------------------
949  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0
950  * [15:1] | ??? | Unknown | *UNDEFINED*
951  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H
952  * [23:17] | ??? | Unknown | *UNDEFINED*
953  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP
954  * [31:25] | ??? | Unknown | *UNDEFINED*
955  *
956  */
957 /*
958  * Field : mpu_m0
959  *
960  * Security bit configuration for transactions from mpu_m0 to emac2tx_ecc. When
961  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
962  * Non-Secure transactions are allowed.
963  *
964  * Field Access Macros:
965  *
966  */
967 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0 register field. */
968 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_LSB 0
969 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0 register field. */
970 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_MSB 0
971 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0 register field. */
972 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_WIDTH 1
973 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0 register field value. */
974 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_SET_MSK 0x00000001
975 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0 register field value. */
976 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_CLR_MSK 0xfffffffe
977 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0 register field. */
978 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_RESET 0x0
979 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0 field value from a register. */
980 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
981 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0 register field value suitable for setting the register. */
982 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
983 
984 /*
985  * Field : fpga2soc
986  *
987  * Security bit configuration for transactions from fpga2soc to emac2tx_ecc. When
988  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
989  * Non-Secure transactions are allowed.
990  *
991  * Field Access Macros:
992  *
993  */
994 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H register field. */
995 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_LSB 16
996 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H register field. */
997 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_MSB 16
998 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H register field. */
999 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_WIDTH 1
1000 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H register field value. */
1001 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_SET_MSK 0x00010000
1002 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H register field value. */
1003 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_CLR_MSK 0xfffeffff
1004 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H register field. */
1005 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_RESET 0x0
1006 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H field value from a register. */
1007 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
1008 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H register field value suitable for setting the register. */
1009 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
1010 
1011 /*
1012  * Field : ahb_ap
1013  *
1014  * Security bit configuration for transactions from ahb_ap to emac2tx_ecc. When
1015  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1016  * Non-Secure transactions are allowed.
1017  *
1018  * Field Access Macros:
1019  *
1020  */
1021 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP register field. */
1022 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_LSB 24
1023 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP register field. */
1024 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_MSB 24
1025 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP register field. */
1026 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_WIDTH 1
1027 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP register field value. */
1028 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_SET_MSK 0x01000000
1029 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP register field value. */
1030 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_CLR_MSK 0xfeffffff
1031 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP register field. */
1032 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_RESET 0x0
1033 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP field value from a register. */
1034 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1035 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP register field value suitable for setting the register. */
1036 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1037 
1038 #ifndef __ASSEMBLY__
1039 /*
1040  * WARNING: The C register and register group struct declarations are provided for
1041  * convenience and illustrative purposes. They should, however, be used with
1042  * caution as the C language standard provides no guarantees about the alignment or
1043  * atomicity of device memory accesses. The recommended practice for writing
1044  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1045  * alt_write_word() functions.
1046  *
1047  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC.
1048  */
1049 struct ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_s
1050 {
1051  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0 */
1052  uint32_t : 15; /* *UNDEFINED* */
1053  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H */
1054  uint32_t : 7; /* *UNDEFINED* */
1055  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP */
1056  uint32_t : 7; /* *UNDEFINED* */
1057 };
1058 
1059 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC. */
1060 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_t;
1061 #endif /* __ASSEMBLY__ */
1062 
1063 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC register. */
1064 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_RESET 0x00000000
1065 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC register from the beginning of the component. */
1066 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_OFST 0x20
1067 
1068 /*
1069  * Register : emac3rx_ecc
1070  *
1071  * Per-Master Security bit for emac3rx_ecc
1072  *
1073  * Register Layout
1074  *
1075  * Bits | Access | Reset | Description
1076  * :-------|:-------|:------|:---------------------------------------
1077  * [31:0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD
1078  *
1079  */
1080 /*
1081  * Field : Reserved
1082  *
1083  * Field Access Macros:
1084  *
1085  */
1086 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD register field. */
1087 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_LSB 0
1088 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD register field. */
1089 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_MSB 31
1090 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD register field. */
1091 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_WIDTH 32
1092 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD register field value. */
1093 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_SET_MSK 0xffffffff
1094 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD register field value. */
1095 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_CLR_MSK 0x00000000
1096 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD register field. */
1097 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_RESET 0x0
1098 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD field value from a register. */
1099 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
1100 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD register field value suitable for setting the register. */
1101 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_SET(value) (((value) << 0) & 0xffffffff)
1102 
1103 #ifndef __ASSEMBLY__
1104 /*
1105  * WARNING: The C register and register group struct declarations are provided for
1106  * convenience and illustrative purposes. They should, however, be used with
1107  * caution as the C language standard provides no guarantees about the alignment or
1108  * atomicity of device memory accesses. The recommended practice for writing
1109  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1110  * alt_write_word() functions.
1111  *
1112  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC.
1113  */
1114 struct ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_s
1115 {
1116  uint32_t Reserved : 32; /* ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD */
1117 };
1118 
1119 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC. */
1120 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_t;
1121 #endif /* __ASSEMBLY__ */
1122 
1123 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC register. */
1124 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RESET 0x00000000
1125 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC register from the beginning of the component. */
1126 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_OFST 0x24
1127 
1128 /*
1129  * Register : emac3tx_ecc
1130  *
1131  * Per-Master Security bit for emac3tx_ecc
1132  *
1133  * Register Layout
1134  *
1135  * Bits | Access | Reset | Description
1136  * :-------|:-------|:------|:---------------------------------------
1137  * [31:0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD
1138  *
1139  */
1140 /*
1141  * Field : Reserved
1142  *
1143  * Field Access Macros:
1144  *
1145  */
1146 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD register field. */
1147 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_LSB 0
1148 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD register field. */
1149 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_MSB 31
1150 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD register field. */
1151 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_WIDTH 32
1152 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD register field value. */
1153 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_SET_MSK 0xffffffff
1154 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD register field value. */
1155 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_CLR_MSK 0x00000000
1156 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD register field. */
1157 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_RESET 0x0
1158 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD field value from a register. */
1159 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
1160 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD register field value suitable for setting the register. */
1161 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_SET(value) (((value) << 0) & 0xffffffff)
1162 
1163 #ifndef __ASSEMBLY__
1164 /*
1165  * WARNING: The C register and register group struct declarations are provided for
1166  * convenience and illustrative purposes. They should, however, be used with
1167  * caution as the C language standard provides no guarantees about the alignment or
1168  * atomicity of device memory accesses. The recommended practice for writing
1169  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1170  * alt_write_word() functions.
1171  *
1172  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC.
1173  */
1174 struct ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_s
1175 {
1176  uint32_t Reserved : 32; /* ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD */
1177 };
1178 
1179 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC. */
1180 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_t;
1181 #endif /* __ASSEMBLY__ */
1182 
1183 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC register. */
1184 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RESET 0x00000000
1185 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC register from the beginning of the component. */
1186 #define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_OFST 0x28
1187 
1188 /*
1189  * Register : nand_ecc
1190  *
1191  * Per-Master Security bit for nand_ecc
1192  *
1193  * Register Layout
1194  *
1195  * Bits | Access | Reset | Description
1196  * :--------|:-------|:--------|:--------------------------------------
1197  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0
1198  * [15:1] | ??? | Unknown | *UNDEFINED*
1199  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H
1200  * [23:17] | ??? | Unknown | *UNDEFINED*
1201  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP
1202  * [31:25] | ??? | Unknown | *UNDEFINED*
1203  *
1204  */
1205 /*
1206  * Field : mpu_m0
1207  *
1208  * Security bit configuration for transactions from mpu_m0 to nand_ecc. When
1209  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1210  * Non-Secure transactions are allowed.
1211  *
1212  * Field Access Macros:
1213  *
1214  */
1215 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0 register field. */
1216 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_LSB 0
1217 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0 register field. */
1218 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_MSB 0
1219 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0 register field. */
1220 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_WIDTH 1
1221 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0 register field value. */
1222 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_SET_MSK 0x00000001
1223 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0 register field value. */
1224 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_CLR_MSK 0xfffffffe
1225 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0 register field. */
1226 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_RESET 0x0
1227 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0 field value from a register. */
1228 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1229 /* Produces a ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0 register field value suitable for setting the register. */
1230 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1231 
1232 /*
1233  * Field : fpga2soc
1234  *
1235  * Security bit configuration for transactions from fpga2soc to nand_ecc. When
1236  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1237  * Non-Secure transactions are allowed.
1238  *
1239  * Field Access Macros:
1240  *
1241  */
1242 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H register field. */
1243 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_LSB 16
1244 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H register field. */
1245 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_MSB 16
1246 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H register field. */
1247 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_WIDTH 1
1248 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H register field value. */
1249 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_SET_MSK 0x00010000
1250 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H register field value. */
1251 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_CLR_MSK 0xfffeffff
1252 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H register field. */
1253 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_RESET 0x0
1254 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H field value from a register. */
1255 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
1256 /* Produces a ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H register field value suitable for setting the register. */
1257 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
1258 
1259 /*
1260  * Field : ahb_ap
1261  *
1262  * Security bit configuration for transactions from ahb_ap to nand_ecc. When
1263  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1264  * Non-Secure transactions are allowed.
1265  *
1266  * Field Access Macros:
1267  *
1268  */
1269 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP register field. */
1270 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_LSB 24
1271 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP register field. */
1272 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_MSB 24
1273 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP register field. */
1274 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_WIDTH 1
1275 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP register field value. */
1276 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_SET_MSK 0x01000000
1277 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP register field value. */
1278 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_CLR_MSK 0xfeffffff
1279 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP register field. */
1280 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_RESET 0x0
1281 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP field value from a register. */
1282 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1283 /* Produces a ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP register field value suitable for setting the register. */
1284 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1285 
1286 #ifndef __ASSEMBLY__
1287 /*
1288  * WARNING: The C register and register group struct declarations are provided for
1289  * convenience and illustrative purposes. They should, however, be used with
1290  * caution as the C language standard provides no guarantees about the alignment or
1291  * atomicity of device memory accesses. The recommended practice for writing
1292  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1293  * alt_write_word() functions.
1294  *
1295  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_NAND_ECC.
1296  */
1297 struct ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_s
1298 {
1299  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0 */
1300  uint32_t : 15; /* *UNDEFINED* */
1301  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H */
1302  uint32_t : 7; /* *UNDEFINED* */
1303  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP */
1304  uint32_t : 7; /* *UNDEFINED* */
1305 };
1306 
1307 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_NAND_ECC. */
1308 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_s ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_t;
1309 #endif /* __ASSEMBLY__ */
1310 
1311 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC register. */
1312 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_RESET 0x00000000
1313 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC register from the beginning of the component. */
1314 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_OFST 0x2c
1315 
1316 /*
1317  * Register : nand_read_ecc
1318  *
1319  * Per-Master Security bit for nand_read_ecc
1320  *
1321  * Register Layout
1322  *
1323  * Bits | Access | Reset | Description
1324  * :--------|:-------|:--------|:-----------------------------------------
1325  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0
1326  * [15:1] | ??? | Unknown | *UNDEFINED*
1327  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H
1328  * [23:17] | ??? | Unknown | *UNDEFINED*
1329  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP
1330  * [31:25] | ??? | Unknown | *UNDEFINED*
1331  *
1332  */
1333 /*
1334  * Field : mpu_m0
1335  *
1336  * Security bit configuration for transactions from mpu_m0 to nand_read_ecc. When
1337  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1338  * Non-Secure transactions are allowed.
1339  *
1340  * Field Access Macros:
1341  *
1342  */
1343 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0 register field. */
1344 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_LSB 0
1345 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0 register field. */
1346 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_MSB 0
1347 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0 register field. */
1348 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_WIDTH 1
1349 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0 register field value. */
1350 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_SET_MSK 0x00000001
1351 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0 register field value. */
1352 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_CLR_MSK 0xfffffffe
1353 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0 register field. */
1354 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_RESET 0x0
1355 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0 field value from a register. */
1356 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1357 /* Produces a ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0 register field value suitable for setting the register. */
1358 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1359 
1360 /*
1361  * Field : fpga2soc
1362  *
1363  * Security bit configuration for transactions from fpga2soc to nand_read_ecc. When
1364  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1365  * Non-Secure transactions are allowed.
1366  *
1367  * Field Access Macros:
1368  *
1369  */
1370 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H register field. */
1371 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_LSB 16
1372 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H register field. */
1373 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_MSB 16
1374 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H register field. */
1375 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_WIDTH 1
1376 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H register field value. */
1377 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_SET_MSK 0x00010000
1378 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H register field value. */
1379 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_CLR_MSK 0xfffeffff
1380 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H register field. */
1381 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_RESET 0x0
1382 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H field value from a register. */
1383 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
1384 /* Produces a ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H register field value suitable for setting the register. */
1385 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
1386 
1387 /*
1388  * Field : ahb_ap
1389  *
1390  * Security bit configuration for transactions from ahb_ap to nand_read_ecc. When
1391  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1392  * Non-Secure transactions are allowed.
1393  *
1394  * Field Access Macros:
1395  *
1396  */
1397 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP register field. */
1398 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_LSB 24
1399 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP register field. */
1400 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_MSB 24
1401 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP register field. */
1402 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_WIDTH 1
1403 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP register field value. */
1404 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_SET_MSK 0x01000000
1405 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP register field value. */
1406 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_CLR_MSK 0xfeffffff
1407 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP register field. */
1408 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_RESET 0x0
1409 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP field value from a register. */
1410 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1411 /* Produces a ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP register field value suitable for setting the register. */
1412 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1413 
1414 #ifndef __ASSEMBLY__
1415 /*
1416  * WARNING: The C register and register group struct declarations are provided for
1417  * convenience and illustrative purposes. They should, however, be used with
1418  * caution as the C language standard provides no guarantees about the alignment or
1419  * atomicity of device memory accesses. The recommended practice for writing
1420  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1421  * alt_write_word() functions.
1422  *
1423  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC.
1424  */
1425 struct ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_s
1426 {
1427  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0 */
1428  uint32_t : 15; /* *UNDEFINED* */
1429  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H */
1430  uint32_t : 7; /* *UNDEFINED* */
1431  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP */
1432  uint32_t : 7; /* *UNDEFINED* */
1433 };
1434 
1435 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC. */
1436 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_s ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_t;
1437 #endif /* __ASSEMBLY__ */
1438 
1439 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC register. */
1440 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_RESET 0x00000000
1441 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC register from the beginning of the component. */
1442 #define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_OFST 0x30
1443 
1444 /*
1445  * Register : nand_write_ecc
1446  *
1447  * Per-Master Security bit for nand_write_ecc
1448  *
1449  * Register Layout
1450  *
1451  * Bits | Access | Reset | Description
1452  * :--------|:-------|:--------|:-----------------------------------------
1453  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0
1454  * [15:1] | ??? | Unknown | *UNDEFINED*
1455  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H
1456  * [23:17] | ??? | Unknown | *UNDEFINED*
1457  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP
1458  * [31:25] | ??? | Unknown | *UNDEFINED*
1459  *
1460  */
1461 /*
1462  * Field : mpu_m0
1463  *
1464  * Security bit configuration for transactions from mpu_m0 to nand_write_ecc. When
1465  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1466  * Non-Secure transactions are allowed.
1467  *
1468  * Field Access Macros:
1469  *
1470  */
1471 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0 register field. */
1472 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_LSB 0
1473 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0 register field. */
1474 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_MSB 0
1475 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0 register field. */
1476 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_WIDTH 1
1477 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0 register field value. */
1478 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_SET_MSK 0x00000001
1479 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0 register field value. */
1480 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_CLR_MSK 0xfffffffe
1481 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0 register field. */
1482 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_RESET 0x0
1483 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0 field value from a register. */
1484 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1485 /* Produces a ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0 register field value suitable for setting the register. */
1486 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1487 
1488 /*
1489  * Field : fpga2soc
1490  *
1491  * Security bit configuration for transactions from fpga2soc to nand_write_ecc.
1492  * When cleared (0), only Secure transactions are allowed. When set (1), both
1493  * Secure and Non-Secure transactions are allowed.
1494  *
1495  * Field Access Macros:
1496  *
1497  */
1498 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H register field. */
1499 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_LSB 16
1500 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H register field. */
1501 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_MSB 16
1502 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H register field. */
1503 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_WIDTH 1
1504 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H register field value. */
1505 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_SET_MSK 0x00010000
1506 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H register field value. */
1507 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_CLR_MSK 0xfffeffff
1508 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H register field. */
1509 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_RESET 0x0
1510 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H field value from a register. */
1511 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
1512 /* Produces a ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H register field value suitable for setting the register. */
1513 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
1514 
1515 /*
1516  * Field : ahb_ap
1517  *
1518  * Security bit configuration for transactions from ahb_ap to nand_write_ecc. When
1519  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1520  * Non-Secure transactions are allowed.
1521  *
1522  * Field Access Macros:
1523  *
1524  */
1525 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP register field. */
1526 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_LSB 24
1527 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP register field. */
1528 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_MSB 24
1529 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP register field. */
1530 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_WIDTH 1
1531 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP register field value. */
1532 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_SET_MSK 0x01000000
1533 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP register field value. */
1534 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_CLR_MSK 0xfeffffff
1535 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP register field. */
1536 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_RESET 0x0
1537 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP field value from a register. */
1538 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1539 /* Produces a ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP register field value suitable for setting the register. */
1540 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1541 
1542 #ifndef __ASSEMBLY__
1543 /*
1544  * WARNING: The C register and register group struct declarations are provided for
1545  * convenience and illustrative purposes. They should, however, be used with
1546  * caution as the C language standard provides no guarantees about the alignment or
1547  * atomicity of device memory accesses. The recommended practice for writing
1548  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1549  * alt_write_word() functions.
1550  *
1551  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC.
1552  */
1553 struct ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_s
1554 {
1555  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0 */
1556  uint32_t : 15; /* *UNDEFINED* */
1557  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H */
1558  uint32_t : 7; /* *UNDEFINED* */
1559  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP */
1560  uint32_t : 7; /* *UNDEFINED* */
1561 };
1562 
1563 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC. */
1564 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_s ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_t;
1565 #endif /* __ASSEMBLY__ */
1566 
1567 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC register. */
1568 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_RESET 0x00000000
1569 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC register from the beginning of the component. */
1570 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_OFST 0x34
1571 
1572 /*
1573  * Register : onchipram_ecc
1574  *
1575  * Per-Master Security bit for onchipram_ecc
1576  *
1577  * Register Layout
1578  *
1579  * Bits | Access | Reset | Description
1580  * :--------|:-------|:--------|:-------------------------------------------
1581  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0
1582  * [15:1] | ??? | Unknown | *UNDEFINED*
1583  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H
1584  * [23:17] | ??? | Unknown | *UNDEFINED*
1585  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP
1586  * [31:25] | ??? | Unknown | *UNDEFINED*
1587  *
1588  */
1589 /*
1590  * Field : mpu_m0
1591  *
1592  * Security bit configuration for transactions from mpu_m0 to onchipram_ecc. When
1593  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1594  * Non-Secure transactions are allowed.
1595  *
1596  * Field Access Macros:
1597  *
1598  */
1599 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0 register field. */
1600 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_LSB 0
1601 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0 register field. */
1602 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_MSB 0
1603 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0 register field. */
1604 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_WIDTH 1
1605 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0 register field value. */
1606 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_SET_MSK 0x00000001
1607 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0 register field value. */
1608 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_CLR_MSK 0xfffffffe
1609 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0 register field. */
1610 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_RESET 0x0
1611 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0 field value from a register. */
1612 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1613 /* Produces a ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0 register field value suitable for setting the register. */
1614 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1615 
1616 /*
1617  * Field : fpga2soc
1618  *
1619  * Security bit configuration for transactions from fpga2soc to onchipram_ecc. When
1620  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1621  * Non-Secure transactions are allowed.
1622  *
1623  * Field Access Macros:
1624  *
1625  */
1626 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H register field. */
1627 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_LSB 16
1628 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H register field. */
1629 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_MSB 16
1630 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H register field. */
1631 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_WIDTH 1
1632 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H register field value. */
1633 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_SET_MSK 0x00010000
1634 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H register field value. */
1635 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_CLR_MSK 0xfffeffff
1636 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H register field. */
1637 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_RESET 0x0
1638 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H field value from a register. */
1639 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
1640 /* Produces a ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H register field value suitable for setting the register. */
1641 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
1642 
1643 /*
1644  * Field : ahb_ap
1645  *
1646  * Security bit configuration for transactions from ahb_ap to onchipram_ecc. When
1647  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1648  * Non-Secure transactions are allowed.
1649  *
1650  * Field Access Macros:
1651  *
1652  */
1653 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP register field. */
1654 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_LSB 24
1655 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP register field. */
1656 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_MSB 24
1657 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP register field. */
1658 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_WIDTH 1
1659 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP register field value. */
1660 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_SET_MSK 0x01000000
1661 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP register field value. */
1662 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_CLR_MSK 0xfeffffff
1663 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP register field. */
1664 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_RESET 0x0
1665 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP field value from a register. */
1666 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1667 /* Produces a ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP register field value suitable for setting the register. */
1668 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1669 
1670 #ifndef __ASSEMBLY__
1671 /*
1672  * WARNING: The C register and register group struct declarations are provided for
1673  * convenience and illustrative purposes. They should, however, be used with
1674  * caution as the C language standard provides no guarantees about the alignment or
1675  * atomicity of device memory accesses. The recommended practice for writing
1676  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1677  * alt_write_word() functions.
1678  *
1679  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC.
1680  */
1681 struct ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_s
1682 {
1683  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0 */
1684  uint32_t : 15; /* *UNDEFINED* */
1685  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H */
1686  uint32_t : 7; /* *UNDEFINED* */
1687  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP */
1688  uint32_t : 7; /* *UNDEFINED* */
1689 };
1690 
1691 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC. */
1692 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_s ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_t;
1693 #endif /* __ASSEMBLY__ */
1694 
1695 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC register. */
1696 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_RESET 0x00000000
1697 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC register from the beginning of the component. */
1698 #define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_OFST 0x38
1699 
1700 /*
1701  * Register : qspi_ecc
1702  *
1703  * Per-Master Security bit for qspi_ecc
1704  *
1705  * Register Layout
1706  *
1707  * Bits | Access | Reset | Description
1708  * :--------|:-------|:--------|:--------------------------------------
1709  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0
1710  * [15:1] | ??? | Unknown | *UNDEFINED*
1711  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H
1712  * [23:17] | ??? | Unknown | *UNDEFINED*
1713  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP
1714  * [31:25] | ??? | Unknown | *UNDEFINED*
1715  *
1716  */
1717 /*
1718  * Field : mpu_m0
1719  *
1720  * Security bit configuration for transactions from mpu_m0 to qspi_ecc. When
1721  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1722  * Non-Secure transactions are allowed.
1723  *
1724  * Field Access Macros:
1725  *
1726  */
1727 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0 register field. */
1728 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_LSB 0
1729 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0 register field. */
1730 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_MSB 0
1731 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0 register field. */
1732 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_WIDTH 1
1733 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0 register field value. */
1734 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_SET_MSK 0x00000001
1735 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0 register field value. */
1736 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_CLR_MSK 0xfffffffe
1737 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0 register field. */
1738 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_RESET 0x0
1739 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0 field value from a register. */
1740 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1741 /* Produces a ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0 register field value suitable for setting the register. */
1742 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1743 
1744 /*
1745  * Field : fpga2soc
1746  *
1747  * Security bit configuration for transactions from fpga2soc to qspi_ecc. When
1748  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1749  * Non-Secure transactions are allowed.
1750  *
1751  * Field Access Macros:
1752  *
1753  */
1754 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H register field. */
1755 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_LSB 16
1756 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H register field. */
1757 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_MSB 16
1758 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H register field. */
1759 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_WIDTH 1
1760 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H register field value. */
1761 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_SET_MSK 0x00010000
1762 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H register field value. */
1763 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_CLR_MSK 0xfffeffff
1764 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H register field. */
1765 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_RESET 0x0
1766 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H field value from a register. */
1767 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
1768 /* Produces a ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H register field value suitable for setting the register. */
1769 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
1770 
1771 /*
1772  * Field : ahb_ap
1773  *
1774  * Security bit configuration for transactions from ahb_ap to qspi_ecc. When
1775  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1776  * Non-Secure transactions are allowed.
1777  *
1778  * Field Access Macros:
1779  *
1780  */
1781 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP register field. */
1782 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_LSB 24
1783 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP register field. */
1784 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_MSB 24
1785 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP register field. */
1786 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_WIDTH 1
1787 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP register field value. */
1788 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_SET_MSK 0x01000000
1789 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP register field value. */
1790 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_CLR_MSK 0xfeffffff
1791 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP register field. */
1792 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_RESET 0x0
1793 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP field value from a register. */
1794 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1795 /* Produces a ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP register field value suitable for setting the register. */
1796 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1797 
1798 #ifndef __ASSEMBLY__
1799 /*
1800  * WARNING: The C register and register group struct declarations are provided for
1801  * convenience and illustrative purposes. They should, however, be used with
1802  * caution as the C language standard provides no guarantees about the alignment or
1803  * atomicity of device memory accesses. The recommended practice for writing
1804  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1805  * alt_write_word() functions.
1806  *
1807  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC.
1808  */
1809 struct ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_s
1810 {
1811  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0 */
1812  uint32_t : 15; /* *UNDEFINED* */
1813  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H */
1814  uint32_t : 7; /* *UNDEFINED* */
1815  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP */
1816  uint32_t : 7; /* *UNDEFINED* */
1817 };
1818 
1819 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC. */
1820 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_s ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_t;
1821 #endif /* __ASSEMBLY__ */
1822 
1823 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC register. */
1824 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_RESET 0x00000000
1825 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC register from the beginning of the component. */
1826 #define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_OFST 0x3c
1827 
1828 /*
1829  * Register : sdmmc_ecc
1830  *
1831  * Per-Master Security bit for sdmmc_ecc
1832  *
1833  * Register Layout
1834  *
1835  * Bits | Access | Reset | Description
1836  * :--------|:-------|:--------|:---------------------------------------
1837  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0
1838  * [15:1] | ??? | Unknown | *UNDEFINED*
1839  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H
1840  * [23:17] | ??? | Unknown | *UNDEFINED*
1841  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP
1842  * [31:25] | ??? | Unknown | *UNDEFINED*
1843  *
1844  */
1845 /*
1846  * Field : mpu_m0
1847  *
1848  * Security bit configuration for transactions from mpu_m0 to sdmmc_ecc. When
1849  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1850  * Non-Secure transactions are allowed.
1851  *
1852  * Field Access Macros:
1853  *
1854  */
1855 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0 register field. */
1856 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_LSB 0
1857 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0 register field. */
1858 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_MSB 0
1859 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0 register field. */
1860 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_WIDTH 1
1861 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0 register field value. */
1862 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_SET_MSK 0x00000001
1863 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0 register field value. */
1864 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_CLR_MSK 0xfffffffe
1865 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0 register field. */
1866 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_RESET 0x0
1867 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0 field value from a register. */
1868 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1869 /* Produces a ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0 register field value suitable for setting the register. */
1870 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1871 
1872 /*
1873  * Field : fpga2soc
1874  *
1875  * Security bit configuration for transactions from fpga2soc to sdmmc_ecc. When
1876  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1877  * Non-Secure transactions are allowed.
1878  *
1879  * Field Access Macros:
1880  *
1881  */
1882 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H register field. */
1883 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_LSB 16
1884 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H register field. */
1885 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_MSB 16
1886 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H register field. */
1887 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_WIDTH 1
1888 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H register field value. */
1889 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_SET_MSK 0x00010000
1890 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H register field value. */
1891 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_CLR_MSK 0xfffeffff
1892 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H register field. */
1893 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_RESET 0x0
1894 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H field value from a register. */
1895 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
1896 /* Produces a ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H register field value suitable for setting the register. */
1897 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
1898 
1899 /*
1900  * Field : ahb_ap
1901  *
1902  * Security bit configuration for transactions from ahb_ap to sdmmc_ecc. When
1903  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1904  * Non-Secure transactions are allowed.
1905  *
1906  * Field Access Macros:
1907  *
1908  */
1909 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP register field. */
1910 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_LSB 24
1911 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP register field. */
1912 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_MSB 24
1913 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP register field. */
1914 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_WIDTH 1
1915 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP register field value. */
1916 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_SET_MSK 0x01000000
1917 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP register field value. */
1918 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_CLR_MSK 0xfeffffff
1919 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP register field. */
1920 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_RESET 0x0
1921 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP field value from a register. */
1922 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1923 /* Produces a ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP register field value suitable for setting the register. */
1924 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1925 
1926 #ifndef __ASSEMBLY__
1927 /*
1928  * WARNING: The C register and register group struct declarations are provided for
1929  * convenience and illustrative purposes. They should, however, be used with
1930  * caution as the C language standard provides no guarantees about the alignment or
1931  * atomicity of device memory accesses. The recommended practice for writing
1932  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1933  * alt_write_word() functions.
1934  *
1935  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC.
1936  */
1937 struct ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_s
1938 {
1939  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0 */
1940  uint32_t : 15; /* *UNDEFINED* */
1941  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H */
1942  uint32_t : 7; /* *UNDEFINED* */
1943  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP */
1944  uint32_t : 7; /* *UNDEFINED* */
1945 };
1946 
1947 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC. */
1948 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_s ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_t;
1949 #endif /* __ASSEMBLY__ */
1950 
1951 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC register. */
1952 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_RESET 0x00000000
1953 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC register from the beginning of the component. */
1954 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_OFST 0x40
1955 
1956 /*
1957  * Register : usb0_ecc
1958  *
1959  * Per-Master Security bit for usb0_ecc
1960  *
1961  * Register Layout
1962  *
1963  * Bits | Access | Reset | Description
1964  * :--------|:-------|:--------|:--------------------------------------
1965  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0
1966  * [15:1] | ??? | Unknown | *UNDEFINED*
1967  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H
1968  * [23:17] | ??? | Unknown | *UNDEFINED*
1969  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP
1970  * [31:25] | ??? | Unknown | *UNDEFINED*
1971  *
1972  */
1973 /*
1974  * Field : mpu_m0
1975  *
1976  * Security bit configuration for transactions from mpu_m0 to usb0_ecc. When
1977  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1978  * Non-Secure transactions are allowed.
1979  *
1980  * Field Access Macros:
1981  *
1982  */
1983 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0 register field. */
1984 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_LSB 0
1985 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0 register field. */
1986 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_MSB 0
1987 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0 register field. */
1988 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_WIDTH 1
1989 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0 register field value. */
1990 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_SET_MSK 0x00000001
1991 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0 register field value. */
1992 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_CLR_MSK 0xfffffffe
1993 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0 register field. */
1994 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_RESET 0x0
1995 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0 field value from a register. */
1996 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1997 /* Produces a ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0 register field value suitable for setting the register. */
1998 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1999 
2000 /*
2001  * Field : fpga2soc
2002  *
2003  * Security bit configuration for transactions from fpga2soc to usb0_ecc. When
2004  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2005  * Non-Secure transactions are allowed.
2006  *
2007  * Field Access Macros:
2008  *
2009  */
2010 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H register field. */
2011 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_LSB 16
2012 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H register field. */
2013 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_MSB 16
2014 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H register field. */
2015 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_WIDTH 1
2016 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H register field value. */
2017 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_SET_MSK 0x00010000
2018 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H register field value. */
2019 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_CLR_MSK 0xfffeffff
2020 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H register field. */
2021 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_RESET 0x0
2022 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H field value from a register. */
2023 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
2024 /* Produces a ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H register field value suitable for setting the register. */
2025 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
2026 
2027 /*
2028  * Field : ahb_ap
2029  *
2030  * Security bit configuration for transactions from ahb_ap to usb0_ecc. When
2031  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2032  * Non-Secure transactions are allowed.
2033  *
2034  * Field Access Macros:
2035  *
2036  */
2037 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP register field. */
2038 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_LSB 24
2039 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP register field. */
2040 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_MSB 24
2041 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP register field. */
2042 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_WIDTH 1
2043 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP register field value. */
2044 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_SET_MSK 0x01000000
2045 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP register field value. */
2046 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_CLR_MSK 0xfeffffff
2047 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP register field. */
2048 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_RESET 0x0
2049 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP field value from a register. */
2050 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2051 /* Produces a ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP register field value suitable for setting the register. */
2052 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2053 
2054 #ifndef __ASSEMBLY__
2055 /*
2056  * WARNING: The C register and register group struct declarations are provided for
2057  * convenience and illustrative purposes. They should, however, be used with
2058  * caution as the C language standard provides no guarantees about the alignment or
2059  * atomicity of device memory accesses. The recommended practice for writing
2060  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2061  * alt_write_word() functions.
2062  *
2063  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_USB0_ECC.
2064  */
2065 struct ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_s
2066 {
2067  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0 */
2068  uint32_t : 15; /* *UNDEFINED* */
2069  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H */
2070  uint32_t : 7; /* *UNDEFINED* */
2071  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP */
2072  uint32_t : 7; /* *UNDEFINED* */
2073 };
2074 
2075 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_USB0_ECC. */
2076 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_s ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_t;
2077 #endif /* __ASSEMBLY__ */
2078 
2079 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC register. */
2080 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_RESET 0x00000000
2081 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC register from the beginning of the component. */
2082 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_OFST 0x44
2083 
2084 /*
2085  * Register : usb1_ecc
2086  *
2087  * Per-Master Security bit for usb1_ecc
2088  *
2089  * Register Layout
2090  *
2091  * Bits | Access | Reset | Description
2092  * :--------|:-------|:--------|:--------------------------------------
2093  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0
2094  * [15:1] | ??? | Unknown | *UNDEFINED*
2095  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H
2096  * [23:17] | ??? | Unknown | *UNDEFINED*
2097  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP
2098  * [31:25] | ??? | Unknown | *UNDEFINED*
2099  *
2100  */
2101 /*
2102  * Field : mpu_m0
2103  *
2104  * Security bit configuration for transactions from mpu_m0 to usb1_ecc. When
2105  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2106  * Non-Secure transactions are allowed.
2107  *
2108  * Field Access Macros:
2109  *
2110  */
2111 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0 register field. */
2112 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_LSB 0
2113 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0 register field. */
2114 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_MSB 0
2115 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0 register field. */
2116 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_WIDTH 1
2117 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0 register field value. */
2118 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_SET_MSK 0x00000001
2119 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0 register field value. */
2120 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_CLR_MSK 0xfffffffe
2121 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0 register field. */
2122 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_RESET 0x0
2123 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0 field value from a register. */
2124 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2125 /* Produces a ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0 register field value suitable for setting the register. */
2126 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2127 
2128 /*
2129  * Field : fpga2soc
2130  *
2131  * Security bit configuration for transactions from fpga2soc to usb1_ecc. When
2132  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2133  * Non-Secure transactions are allowed.
2134  *
2135  * Field Access Macros:
2136  *
2137  */
2138 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H register field. */
2139 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_LSB 16
2140 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H register field. */
2141 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_MSB 16
2142 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H register field. */
2143 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_WIDTH 1
2144 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H register field value. */
2145 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_SET_MSK 0x00010000
2146 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H register field value. */
2147 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_CLR_MSK 0xfffeffff
2148 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H register field. */
2149 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_RESET 0x0
2150 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H field value from a register. */
2151 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
2152 /* Produces a ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H register field value suitable for setting the register. */
2153 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
2154 
2155 /*
2156  * Field : ahb_ap
2157  *
2158  * Security bit configuration for transactions from ahb_ap to usb1_ecc. When
2159  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2160  * Non-Secure transactions are allowed.
2161  *
2162  * Field Access Macros:
2163  *
2164  */
2165 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP register field. */
2166 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_LSB 24
2167 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP register field. */
2168 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_MSB 24
2169 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP register field. */
2170 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_WIDTH 1
2171 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP register field value. */
2172 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_SET_MSK 0x01000000
2173 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP register field value. */
2174 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_CLR_MSK 0xfeffffff
2175 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP register field. */
2176 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_RESET 0x0
2177 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP field value from a register. */
2178 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2179 /* Produces a ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP register field value suitable for setting the register. */
2180 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2181 
2182 #ifndef __ASSEMBLY__
2183 /*
2184  * WARNING: The C register and register group struct declarations are provided for
2185  * convenience and illustrative purposes. They should, however, be used with
2186  * caution as the C language standard provides no guarantees about the alignment or
2187  * atomicity of device memory accesses. The recommended practice for writing
2188  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2189  * alt_write_word() functions.
2190  *
2191  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_USB1_ECC.
2192  */
2193 struct ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_s
2194 {
2195  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0 */
2196  uint32_t : 15; /* *UNDEFINED* */
2197  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H */
2198  uint32_t : 7; /* *UNDEFINED* */
2199  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP */
2200  uint32_t : 7; /* *UNDEFINED* */
2201 };
2202 
2203 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_USB1_ECC. */
2204 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_s ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_t;
2205 #endif /* __ASSEMBLY__ */
2206 
2207 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC register. */
2208 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_RESET 0x00000000
2209 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC register from the beginning of the component. */
2210 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_OFST 0x48
2211 
2212 /*
2213  * Register : clock_manager
2214  *
2215  * Per-Master Security bit for clock_manager
2216  *
2217  * Register Layout
2218  *
2219  * Bits | Access | Reset | Description
2220  * :--------|:-------|:--------|:-----------------------------------------
2221  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0
2222  * [7:1] | ??? | Unknown | *UNDEFINED*
2223  * [8] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA
2224  * [15:9] | ??? | Unknown | *UNDEFINED*
2225  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H
2226  * [23:17] | ??? | Unknown | *UNDEFINED*
2227  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP
2228  * [31:25] | ??? | Unknown | *UNDEFINED*
2229  *
2230  */
2231 /*
2232  * Field : mpu_m0
2233  *
2234  * Security bit configuration for transactions from mpu_m0 to clock_manager. When
2235  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2236  * Non-Secure transactions are allowed.
2237  *
2238  * Field Access Macros:
2239  *
2240  */
2241 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0 register field. */
2242 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_LSB 0
2243 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0 register field. */
2244 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_MSB 0
2245 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0 register field. */
2246 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_WIDTH 1
2247 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0 register field value. */
2248 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_SET_MSK 0x00000001
2249 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0 register field value. */
2250 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_CLR_MSK 0xfffffffe
2251 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0 register field. */
2252 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_RESET 0x0
2253 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0 field value from a register. */
2254 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2255 /* Produces a ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0 register field value suitable for setting the register. */
2256 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2257 
2258 /*
2259  * Field : dma
2260  *
2261  * Security bit configuration for transactions from dma to clock_manager. When
2262  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2263  * Non-Secure transactions are allowed.
2264  *
2265  * Field Access Macros:
2266  *
2267  */
2268 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA register field. */
2269 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_LSB 8
2270 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA register field. */
2271 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_MSB 8
2272 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA register field. */
2273 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_WIDTH 1
2274 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA register field value. */
2275 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_SET_MSK 0x00000100
2276 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA register field value. */
2277 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_CLR_MSK 0xfffffeff
2278 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA register field. */
2279 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_RESET 0x0
2280 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA field value from a register. */
2281 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_GET(value) (((value) & 0x00000100) >> 8)
2282 /* Produces a ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA register field value suitable for setting the register. */
2283 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_SET(value) (((value) << 8) & 0x00000100)
2284 
2285 /*
2286  * Field : fpga2soc
2287  *
2288  * Security bit configuration for transactions from fpga2soc to clock_manager. When
2289  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2290  * Non-Secure transactions are allowed.
2291  *
2292  * Field Access Macros:
2293  *
2294  */
2295 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H register field. */
2296 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_LSB 16
2297 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H register field. */
2298 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_MSB 16
2299 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H register field. */
2300 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_WIDTH 1
2301 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H register field value. */
2302 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_SET_MSK 0x00010000
2303 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H register field value. */
2304 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_CLR_MSK 0xfffeffff
2305 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H register field. */
2306 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_RESET 0x0
2307 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H field value from a register. */
2308 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_GET(value) (((value) & 0x00010000) >> 16)
2309 /* Produces a ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H register field value suitable for setting the register. */
2310 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_SET(value) (((value) << 16) & 0x00010000)
2311 
2312 /*
2313  * Field : ahb_ap
2314  *
2315  * Security bit configuration for transactions from ahb_ap to clock_manager. When
2316  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2317  * Non-Secure transactions are allowed.
2318  *
2319  * Field Access Macros:
2320  *
2321  */
2322 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP register field. */
2323 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_LSB 24
2324 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP register field. */
2325 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_MSB 24
2326 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP register field. */
2327 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_WIDTH 1
2328 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP register field value. */
2329 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_SET_MSK 0x01000000
2330 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP register field value. */
2331 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_CLR_MSK 0xfeffffff
2332 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP register field. */
2333 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_RESET 0x0
2334 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP field value from a register. */
2335 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2336 /* Produces a ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP register field value suitable for setting the register. */
2337 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2338 
2339 #ifndef __ASSEMBLY__
2340 /*
2341  * WARNING: The C register and register group struct declarations are provided for
2342  * convenience and illustrative purposes. They should, however, be used with
2343  * caution as the C language standard provides no guarantees about the alignment or
2344  * atomicity of device memory accesses. The recommended practice for writing
2345  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2346  * alt_write_word() functions.
2347  *
2348  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER.
2349  */
2350 struct ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_s
2351 {
2352  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0 */
2353  uint32_t : 7; /* *UNDEFINED* */
2354  uint32_t dma : 1; /* ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA */
2355  uint32_t : 7; /* *UNDEFINED* */
2356  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H */
2357  uint32_t : 7; /* *UNDEFINED* */
2358  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP */
2359  uint32_t : 7; /* *UNDEFINED* */
2360 };
2361 
2362 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER. */
2363 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_s ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_t;
2364 #endif /* __ASSEMBLY__ */
2365 
2366 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER register. */
2367 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_RESET 0x00000000
2368 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER register from the beginning of the component. */
2369 #define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_OFST 0x4c
2370 
2371 /*
2372  * Register : fpga_manager_register
2373  *
2374  * Per-Master Security bit for fpga_manager
2375  *
2376  * Register Layout
2377  *
2378  * Bits | Access | Reset | Description
2379  * :--------|:-------|:--------|:----------------------------------------------
2380  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0
2381  * [7:1] | ??? | Unknown | *UNDEFINED*
2382  * [8] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA
2383  * [23:9] | ??? | Unknown | *UNDEFINED*
2384  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP
2385  * [31:25] | ??? | Unknown | *UNDEFINED*
2386  *
2387  */
2388 /*
2389  * Field : mpu_m0
2390  *
2391  * Security bit configuration for transactions from mpu_m0 to fpga_manager. When
2392  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2393  * Non-Secure transactions are allowed.
2394  *
2395  * Field Access Macros:
2396  *
2397  */
2398 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0 register field. */
2399 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_LSB 0
2400 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0 register field. */
2401 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_MSB 0
2402 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0 register field. */
2403 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_WIDTH 1
2404 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0 register field value. */
2405 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_SET_MSK 0x00000001
2406 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0 register field value. */
2407 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_CLR_MSK 0xfffffffe
2408 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0 register field. */
2409 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_RESET 0x0
2410 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0 field value from a register. */
2411 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2412 /* Produces a ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0 register field value suitable for setting the register. */
2413 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2414 
2415 /*
2416  * Field : dma
2417  *
2418  * Security bit configuration for transactions from dma to fpga_manager. When
2419  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2420  * Non-Secure transactions are allowed.
2421  *
2422  * Field Access Macros:
2423  *
2424  */
2425 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA register field. */
2426 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_LSB 8
2427 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA register field. */
2428 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_MSB 8
2429 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA register field. */
2430 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_WIDTH 1
2431 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA register field value. */
2432 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_SET_MSK 0x00000100
2433 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA register field value. */
2434 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_CLR_MSK 0xfffffeff
2435 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA register field. */
2436 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_RESET 0x0
2437 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA field value from a register. */
2438 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_GET(value) (((value) & 0x00000100) >> 8)
2439 /* Produces a ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA register field value suitable for setting the register. */
2440 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_SET(value) (((value) << 8) & 0x00000100)
2441 
2442 /*
2443  * Field : ahb_ap
2444  *
2445  * Security bit configuration for transactions from ahb_ap to fpga_manager. When
2446  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2447  * Non-Secure transactions are allowed.
2448  *
2449  * Field Access Macros:
2450  *
2451  */
2452 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP register field. */
2453 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_LSB 24
2454 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP register field. */
2455 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_MSB 24
2456 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP register field. */
2457 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_WIDTH 1
2458 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP register field value. */
2459 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_SET_MSK 0x01000000
2460 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP register field value. */
2461 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_CLR_MSK 0xfeffffff
2462 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP register field. */
2463 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_RESET 0x0
2464 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP field value from a register. */
2465 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2466 /* Produces a ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP register field value suitable for setting the register. */
2467 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2468 
2469 #ifndef __ASSEMBLY__
2470 /*
2471  * WARNING: The C register and register group struct declarations are provided for
2472  * convenience and illustrative purposes. They should, however, be used with
2473  * caution as the C language standard provides no guarantees about the alignment or
2474  * atomicity of device memory accesses. The recommended practice for writing
2475  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2476  * alt_write_word() functions.
2477  *
2478  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG.
2479  */
2480 struct ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_s
2481 {
2482  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0 */
2483  uint32_t : 7; /* *UNDEFINED* */
2484  uint32_t dma : 1; /* ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA */
2485  uint32_t : 15; /* *UNDEFINED* */
2486  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP */
2487  uint32_t : 7; /* *UNDEFINED* */
2488 };
2489 
2490 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG. */
2491 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_s ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_t;
2492 #endif /* __ASSEMBLY__ */
2493 
2494 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG register. */
2495 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_RESET 0x00000000
2496 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG register from the beginning of the component. */
2497 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_OFST 0x50
2498 
2499 /*
2500  * Register : pin_mux_register
2501  *
2502  * Per-Master Security bit for pin_mux_register
2503  *
2504  * Register Layout
2505  *
2506  * Bits | Access | Reset | Description
2507  * :--------|:-------|:--------|:-----------------------------------------
2508  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0
2509  * [7:1] | ??? | Unknown | *UNDEFINED*
2510  * [8] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA
2511  * [15:9] | ??? | Unknown | *UNDEFINED*
2512  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H
2513  * [23:17] | ??? | Unknown | *UNDEFINED*
2514  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP
2515  * [31:25] | ??? | Unknown | *UNDEFINED*
2516  *
2517  */
2518 /*
2519  * Field : mpu_m0
2520  *
2521  * Security bit configuration for transactions from mpu_m0 to pin_mux_register.
2522  * When cleared (0), only Secure transactions are allowed. When set (1), both
2523  * Secure and Non-Secure transactions are allowed.
2524  *
2525  * Field Access Macros:
2526  *
2527  */
2528 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0 register field. */
2529 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_LSB 0
2530 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0 register field. */
2531 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_MSB 0
2532 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0 register field. */
2533 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_WIDTH 1
2534 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0 register field value. */
2535 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_SET_MSK 0x00000001
2536 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0 register field value. */
2537 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_CLR_MSK 0xfffffffe
2538 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0 register field. */
2539 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_RESET 0x0
2540 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0 field value from a register. */
2541 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2542 /* Produces a ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0 register field value suitable for setting the register. */
2543 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2544 
2545 /*
2546  * Field : dma
2547  *
2548  * Security bit configuration for transactions from dma to pin_mux_register. When
2549  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2550  * Non-Secure transactions are allowed.
2551  *
2552  * Field Access Macros:
2553  *
2554  */
2555 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA register field. */
2556 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_LSB 8
2557 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA register field. */
2558 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_MSB 8
2559 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA register field. */
2560 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_WIDTH 1
2561 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA register field value. */
2562 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_SET_MSK 0x00000100
2563 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA register field value. */
2564 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_CLR_MSK 0xfffffeff
2565 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA register field. */
2566 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_RESET 0x0
2567 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA field value from a register. */
2568 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_GET(value) (((value) & 0x00000100) >> 8)
2569 /* Produces a ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA register field value suitable for setting the register. */
2570 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_SET(value) (((value) << 8) & 0x00000100)
2571 
2572 /*
2573  * Field : fpga2soc
2574  *
2575  * Security bit configuration for transactions from fpga2soc to pin_mux_register.
2576  * When cleared (0), only Secure transactions are allowed. When set (1), both
2577  * Secure and Non-Secure transactions are allowed.
2578  *
2579  * Field Access Macros:
2580  *
2581  */
2582 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H register field. */
2583 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_LSB 16
2584 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H register field. */
2585 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_MSB 16
2586 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H register field. */
2587 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_WIDTH 1
2588 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H register field value. */
2589 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_SET_MSK 0x00010000
2590 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H register field value. */
2591 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_CLR_MSK 0xfffeffff
2592 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H register field. */
2593 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_RESET 0x0
2594 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H field value from a register. */
2595 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
2596 /* Produces a ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H register field value suitable for setting the register. */
2597 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
2598 
2599 /*
2600  * Field : ahb_ap
2601  *
2602  * Security bit configuration for transactions from ahb_ap to pin_mux_register.
2603  * When cleared (0), only Secure transactions are allowed. When set (1), both
2604  * Secure and Non-Secure transactions are allowed.
2605  *
2606  * Field Access Macros:
2607  *
2608  */
2609 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP register field. */
2610 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_LSB 24
2611 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP register field. */
2612 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_MSB 24
2613 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP register field. */
2614 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_WIDTH 1
2615 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP register field value. */
2616 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_SET_MSK 0x01000000
2617 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP register field value. */
2618 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_CLR_MSK 0xfeffffff
2619 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP register field. */
2620 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_RESET 0x0
2621 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP field value from a register. */
2622 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2623 /* Produces a ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP register field value suitable for setting the register. */
2624 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2625 
2626 #ifndef __ASSEMBLY__
2627 /*
2628  * WARNING: The C register and register group struct declarations are provided for
2629  * convenience and illustrative purposes. They should, however, be used with
2630  * caution as the C language standard provides no guarantees about the alignment or
2631  * atomicity of device memory accesses. The recommended practice for writing
2632  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2633  * alt_write_word() functions.
2634  *
2635  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG.
2636  */
2637 struct ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_s
2638 {
2639  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0 */
2640  uint32_t : 7; /* *UNDEFINED* */
2641  uint32_t dma : 1; /* ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA */
2642  uint32_t : 7; /* *UNDEFINED* */
2643  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H */
2644  uint32_t : 7; /* *UNDEFINED* */
2645  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP */
2646  uint32_t : 7; /* *UNDEFINED* */
2647 };
2648 
2649 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG. */
2650 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_s ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_t;
2651 #endif /* __ASSEMBLY__ */
2652 
2653 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG register. */
2654 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_RESET 0x00000000
2655 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG register from the beginning of the component. */
2656 #define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_OFST 0x54
2657 
2658 /*
2659  * Register : reset_manager
2660  *
2661  * Per-Master Security bit for reset_manager
2662  *
2663  * Register Layout
2664  *
2665  * Bits | Access | Reset | Description
2666  * :--------|:-------|:--------|:-----------------------------------------
2667  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0
2668  * [7:1] | ??? | Unknown | *UNDEFINED*
2669  * [8] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA
2670  * [15:9] | ??? | Unknown | *UNDEFINED*
2671  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H
2672  * [23:17] | ??? | Unknown | *UNDEFINED*
2673  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP
2674  * [31:25] | ??? | Unknown | *UNDEFINED*
2675  *
2676  */
2677 /*
2678  * Field : mpu_m0
2679  *
2680  * Security bit configuration for transactions from mpu_m0 to reset_manager. When
2681  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2682  * Non-Secure transactions are allowed.
2683  *
2684  * Field Access Macros:
2685  *
2686  */
2687 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0 register field. */
2688 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_LSB 0
2689 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0 register field. */
2690 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_MSB 0
2691 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0 register field. */
2692 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_WIDTH 1
2693 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0 register field value. */
2694 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_SET_MSK 0x00000001
2695 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0 register field value. */
2696 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_CLR_MSK 0xfffffffe
2697 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0 register field. */
2698 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_RESET 0x0
2699 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0 field value from a register. */
2700 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2701 /* Produces a ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0 register field value suitable for setting the register. */
2702 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2703 
2704 /*
2705  * Field : dma
2706  *
2707  * Security bit configuration for transactions from dma to reset_manager. When
2708  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2709  * Non-Secure transactions are allowed.
2710  *
2711  * Field Access Macros:
2712  *
2713  */
2714 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA register field. */
2715 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_LSB 8
2716 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA register field. */
2717 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_MSB 8
2718 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA register field. */
2719 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_WIDTH 1
2720 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA register field value. */
2721 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_SET_MSK 0x00000100
2722 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA register field value. */
2723 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_CLR_MSK 0xfffffeff
2724 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA register field. */
2725 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_RESET 0x0
2726 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA field value from a register. */
2727 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_GET(value) (((value) & 0x00000100) >> 8)
2728 /* Produces a ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA register field value suitable for setting the register. */
2729 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_SET(value) (((value) << 8) & 0x00000100)
2730 
2731 /*
2732  * Field : fpga2soc
2733  *
2734  * Security bit configuration for transactions from fpga2soc to reset_manager. When
2735  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2736  * Non-Secure transactions are allowed.
2737  *
2738  * Field Access Macros:
2739  *
2740  */
2741 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H register field. */
2742 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_LSB 16
2743 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H register field. */
2744 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_MSB 16
2745 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H register field. */
2746 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_WIDTH 1
2747 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H register field value. */
2748 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_SET_MSK 0x00010000
2749 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H register field value. */
2750 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_CLR_MSK 0xfffeffff
2751 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H register field. */
2752 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_RESET 0x0
2753 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H field value from a register. */
2754 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_GET(value) (((value) & 0x00010000) >> 16)
2755 /* Produces a ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H register field value suitable for setting the register. */
2756 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_SET(value) (((value) << 16) & 0x00010000)
2757 
2758 /*
2759  * Field : ahb_ap
2760  *
2761  * Security bit configuration for transactions from ahb_ap to reset_manager. When
2762  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2763  * Non-Secure transactions are allowed.
2764  *
2765  * Field Access Macros:
2766  *
2767  */
2768 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP register field. */
2769 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_LSB 24
2770 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP register field. */
2771 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_MSB 24
2772 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP register field. */
2773 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_WIDTH 1
2774 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP register field value. */
2775 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_SET_MSK 0x01000000
2776 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP register field value. */
2777 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_CLR_MSK 0xfeffffff
2778 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP register field. */
2779 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_RESET 0x0
2780 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP field value from a register. */
2781 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2782 /* Produces a ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP register field value suitable for setting the register. */
2783 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2784 
2785 #ifndef __ASSEMBLY__
2786 /*
2787  * WARNING: The C register and register group struct declarations are provided for
2788  * convenience and illustrative purposes. They should, however, be used with
2789  * caution as the C language standard provides no guarantees about the alignment or
2790  * atomicity of device memory accesses. The recommended practice for writing
2791  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2792  * alt_write_word() functions.
2793  *
2794  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER.
2795  */
2796 struct ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_s
2797 {
2798  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0 */
2799  uint32_t : 7; /* *UNDEFINED* */
2800  uint32_t dma : 1; /* ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA */
2801  uint32_t : 7; /* *UNDEFINED* */
2802  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H */
2803  uint32_t : 7; /* *UNDEFINED* */
2804  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP */
2805  uint32_t : 7; /* *UNDEFINED* */
2806 };
2807 
2808 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER. */
2809 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_s ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_t;
2810 #endif /* __ASSEMBLY__ */
2811 
2812 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER register. */
2813 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_RESET 0x00000000
2814 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER register from the beginning of the component. */
2815 #define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_OFST 0x58
2816 
2817 /*
2818  * Register : system_manager
2819  *
2820  * Per-Master Security bit for system_manager
2821  *
2822  * Register Layout
2823  *
2824  * Bits | Access | Reset | Description
2825  * :--------|:-------|:--------|:-----------------------------------------
2826  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0
2827  * [7:1] | ??? | Unknown | *UNDEFINED*
2828  * [8] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA
2829  * [15:9] | ??? | Unknown | *UNDEFINED*
2830  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H
2831  * [23:17] | ??? | Unknown | *UNDEFINED*
2832  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP
2833  * [31:25] | ??? | Unknown | *UNDEFINED*
2834  *
2835  */
2836 /*
2837  * Field : mpu_m0
2838  *
2839  * Security bit configuration for transactions from mpu_m0 to system_manager. When
2840  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2841  * Non-Secure transactions are allowed.
2842  *
2843  * Field Access Macros:
2844  *
2845  */
2846 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0 register field. */
2847 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_LSB 0
2848 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0 register field. */
2849 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_MSB 0
2850 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0 register field. */
2851 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_WIDTH 1
2852 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0 register field value. */
2853 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_SET_MSK 0x00000001
2854 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0 register field value. */
2855 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_CLR_MSK 0xfffffffe
2856 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0 register field. */
2857 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_RESET 0x0
2858 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0 field value from a register. */
2859 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2860 /* Produces a ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0 register field value suitable for setting the register. */
2861 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2862 
2863 /*
2864  * Field : dma
2865  *
2866  * Security bit configuration for transactions from dma to system_manager. When
2867  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2868  * Non-Secure transactions are allowed.
2869  *
2870  * Field Access Macros:
2871  *
2872  */
2873 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA register field. */
2874 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_LSB 8
2875 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA register field. */
2876 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_MSB 8
2877 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA register field. */
2878 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_WIDTH 1
2879 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA register field value. */
2880 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_SET_MSK 0x00000100
2881 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA register field value. */
2882 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_CLR_MSK 0xfffffeff
2883 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA register field. */
2884 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_RESET 0x0
2885 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA field value from a register. */
2886 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_GET(value) (((value) & 0x00000100) >> 8)
2887 /* Produces a ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA register field value suitable for setting the register. */
2888 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_SET(value) (((value) << 8) & 0x00000100)
2889 
2890 /*
2891  * Field : fpga2soc
2892  *
2893  * Security bit configuration for transactions from fpga2soc to system_manager.
2894  * When cleared (0), only Secure transactions are allowed. When set (1), both
2895  * Secure and Non-Secure transactions are allowed.
2896  *
2897  * Field Access Macros:
2898  *
2899  */
2900 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H register field. */
2901 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_LSB 16
2902 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H register field. */
2903 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_MSB 16
2904 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H register field. */
2905 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_WIDTH 1
2906 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H register field value. */
2907 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_SET_MSK 0x00010000
2908 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H register field value. */
2909 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_CLR_MSK 0xfffeffff
2910 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H register field. */
2911 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_RESET 0x0
2912 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H field value from a register. */
2913 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_GET(value) (((value) & 0x00010000) >> 16)
2914 /* Produces a ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H register field value suitable for setting the register. */
2915 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_SET(value) (((value) << 16) & 0x00010000)
2916 
2917 /*
2918  * Field : ahb_ap
2919  *
2920  * Security bit configuration for transactions from ahb_ap to system_manager. When
2921  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2922  * Non-Secure transactions are allowed.
2923  *
2924  * Field Access Macros:
2925  *
2926  */
2927 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP register field. */
2928 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_LSB 24
2929 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP register field. */
2930 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_MSB 24
2931 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP register field. */
2932 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_WIDTH 1
2933 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP register field value. */
2934 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_SET_MSK 0x01000000
2935 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP register field value. */
2936 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_CLR_MSK 0xfeffffff
2937 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP register field. */
2938 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_RESET 0x0
2939 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP field value from a register. */
2940 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2941 /* Produces a ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP register field value suitable for setting the register. */
2942 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2943 
2944 #ifndef __ASSEMBLY__
2945 /*
2946  * WARNING: The C register and register group struct declarations are provided for
2947  * convenience and illustrative purposes. They should, however, be used with
2948  * caution as the C language standard provides no guarantees about the alignment or
2949  * atomicity of device memory accesses. The recommended practice for writing
2950  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2951  * alt_write_word() functions.
2952  *
2953  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER.
2954  */
2955 struct ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_s
2956 {
2957  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0 */
2958  uint32_t : 7; /* *UNDEFINED* */
2959  uint32_t dma : 1; /* ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA */
2960  uint32_t : 7; /* *UNDEFINED* */
2961  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H */
2962  uint32_t : 7; /* *UNDEFINED* */
2963  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP */
2964  uint32_t : 7; /* *UNDEFINED* */
2965 };
2966 
2967 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER. */
2968 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_s ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_t;
2969 #endif /* __ASSEMBLY__ */
2970 
2971 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER register. */
2972 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_RESET 0x00000000
2973 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER register from the beginning of the component. */
2974 #define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_OFST 0x5c
2975 
2976 /*
2977  * Register : osc0_timer
2978  *
2979  * Per-Master Security bit for osc0_timer
2980  *
2981  * Register Layout
2982  *
2983  * Bits | Access | Reset | Description
2984  * :--------|:-------|:--------|:--------------------------------------
2985  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0
2986  * [7:1] | ??? | Unknown | *UNDEFINED*
2987  * [8] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA
2988  * [15:9] | ??? | Unknown | *UNDEFINED*
2989  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H
2990  * [23:17] | ??? | Unknown | *UNDEFINED*
2991  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP
2992  * [31:25] | ??? | Unknown | *UNDEFINED*
2993  *
2994  */
2995 /*
2996  * Field : mpu_m0
2997  *
2998  * Security bit configuration for transactions from mpu_m0 to osc0_timer. When
2999  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3000  * Non-Secure transactions are allowed.
3001  *
3002  * Field Access Macros:
3003  *
3004  */
3005 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0 register field. */
3006 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_LSB 0
3007 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0 register field. */
3008 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_MSB 0
3009 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0 register field. */
3010 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_WIDTH 1
3011 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0 register field value. */
3012 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_SET_MSK 0x00000001
3013 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0 register field value. */
3014 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_CLR_MSK 0xfffffffe
3015 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0 register field. */
3016 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_RESET 0x0
3017 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0 field value from a register. */
3018 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3019 /* Produces a ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0 register field value suitable for setting the register. */
3020 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3021 
3022 /*
3023  * Field : dma
3024  *
3025  * Security bit configuration for transactions from dma to osc0_timer. When cleared
3026  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3027  * Secure transactions are allowed.
3028  *
3029  * Field Access Macros:
3030  *
3031  */
3032 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA register field. */
3033 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_LSB 8
3034 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA register field. */
3035 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_MSB 8
3036 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA register field. */
3037 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_WIDTH 1
3038 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA register field value. */
3039 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_SET_MSK 0x00000100
3040 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA register field value. */
3041 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_CLR_MSK 0xfffffeff
3042 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA register field. */
3043 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_RESET 0x0
3044 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA field value from a register. */
3045 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_GET(value) (((value) & 0x00000100) >> 8)
3046 /* Produces a ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA register field value suitable for setting the register. */
3047 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_SET(value) (((value) << 8) & 0x00000100)
3048 
3049 /*
3050  * Field : fpga2soc
3051  *
3052  * Security bit configuration for transactions from fpga2soc to osc0_timer. When
3053  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3054  * Non-Secure transactions are allowed.
3055  *
3056  * Field Access Macros:
3057  *
3058  */
3059 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H register field. */
3060 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_LSB 16
3061 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H register field. */
3062 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_MSB 16
3063 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H register field. */
3064 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_WIDTH 1
3065 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H register field value. */
3066 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_SET_MSK 0x00010000
3067 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H register field value. */
3068 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_CLR_MSK 0xfffeffff
3069 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H register field. */
3070 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_RESET 0x0
3071 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H field value from a register. */
3072 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_GET(value) (((value) & 0x00010000) >> 16)
3073 /* Produces a ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H register field value suitable for setting the register. */
3074 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_SET(value) (((value) << 16) & 0x00010000)
3075 
3076 /*
3077  * Field : ahb_ap
3078  *
3079  * Security bit configuration for transactions from ahb_ap to osc0_timer. When
3080  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3081  * Non-Secure transactions are allowed.
3082  *
3083  * Field Access Macros:
3084  *
3085  */
3086 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP register field. */
3087 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_LSB 24
3088 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP register field. */
3089 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_MSB 24
3090 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP register field. */
3091 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_WIDTH 1
3092 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP register field value. */
3093 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_SET_MSK 0x01000000
3094 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP register field value. */
3095 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_CLR_MSK 0xfeffffff
3096 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP register field. */
3097 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_RESET 0x0
3098 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP field value from a register. */
3099 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3100 /* Produces a ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP register field value suitable for setting the register. */
3101 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3102 
3103 #ifndef __ASSEMBLY__
3104 /*
3105  * WARNING: The C register and register group struct declarations are provided for
3106  * convenience and illustrative purposes. They should, however, be used with
3107  * caution as the C language standard provides no guarantees about the alignment or
3108  * atomicity of device memory accesses. The recommended practice for writing
3109  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3110  * alt_write_word() functions.
3111  *
3112  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR.
3113  */
3114 struct ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_s
3115 {
3116  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0 */
3117  uint32_t : 7; /* *UNDEFINED* */
3118  uint32_t dma : 1; /* ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA */
3119  uint32_t : 7; /* *UNDEFINED* */
3120  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H */
3121  uint32_t : 7; /* *UNDEFINED* */
3122  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP */
3123  uint32_t : 7; /* *UNDEFINED* */
3124 };
3125 
3126 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR. */
3127 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_s ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_t;
3128 #endif /* __ASSEMBLY__ */
3129 
3130 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR register. */
3131 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_RESET 0x00000000
3132 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR register from the beginning of the component. */
3133 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_OFST 0x60
3134 
3135 /*
3136  * Register : osc1_timer
3137  *
3138  * Per-Master Security bit for osc1_timer
3139  *
3140  * Register Layout
3141  *
3142  * Bits | Access | Reset | Description
3143  * :--------|:-------|:--------|:--------------------------------------
3144  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0
3145  * [7:1] | ??? | Unknown | *UNDEFINED*
3146  * [8] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA
3147  * [15:9] | ??? | Unknown | *UNDEFINED*
3148  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H
3149  * [23:17] | ??? | Unknown | *UNDEFINED*
3150  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP
3151  * [31:25] | ??? | Unknown | *UNDEFINED*
3152  *
3153  */
3154 /*
3155  * Field : mpu_m0
3156  *
3157  * Security bit configuration for transactions from mpu_m0 to osc1_timer. When
3158  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3159  * Non-Secure transactions are allowed.
3160  *
3161  * Field Access Macros:
3162  *
3163  */
3164 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0 register field. */
3165 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_LSB 0
3166 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0 register field. */
3167 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_MSB 0
3168 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0 register field. */
3169 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_WIDTH 1
3170 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0 register field value. */
3171 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_SET_MSK 0x00000001
3172 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0 register field value. */
3173 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_CLR_MSK 0xfffffffe
3174 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0 register field. */
3175 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_RESET 0x0
3176 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0 field value from a register. */
3177 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3178 /* Produces a ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0 register field value suitable for setting the register. */
3179 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3180 
3181 /*
3182  * Field : dma
3183  *
3184  * Security bit configuration for transactions from dma to osc1_timer. When cleared
3185  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3186  * Secure transactions are allowed.
3187  *
3188  * Field Access Macros:
3189  *
3190  */
3191 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA register field. */
3192 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_LSB 8
3193 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA register field. */
3194 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_MSB 8
3195 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA register field. */
3196 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_WIDTH 1
3197 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA register field value. */
3198 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_SET_MSK 0x00000100
3199 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA register field value. */
3200 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_CLR_MSK 0xfffffeff
3201 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA register field. */
3202 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_RESET 0x0
3203 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA field value from a register. */
3204 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_GET(value) (((value) & 0x00000100) >> 8)
3205 /* Produces a ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA register field value suitable for setting the register. */
3206 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_SET(value) (((value) << 8) & 0x00000100)
3207 
3208 /*
3209  * Field : fpga2soc
3210  *
3211  * Security bit configuration for transactions from fpga2soc to osc1_timer. When
3212  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3213  * Non-Secure transactions are allowed.
3214  *
3215  * Field Access Macros:
3216  *
3217  */
3218 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H register field. */
3219 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_LSB 16
3220 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H register field. */
3221 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_MSB 16
3222 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H register field. */
3223 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_WIDTH 1
3224 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H register field value. */
3225 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_SET_MSK 0x00010000
3226 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H register field value. */
3227 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_CLR_MSK 0xfffeffff
3228 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H register field. */
3229 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_RESET 0x0
3230 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H field value from a register. */
3231 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_GET(value) (((value) & 0x00010000) >> 16)
3232 /* Produces a ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H register field value suitable for setting the register. */
3233 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_SET(value) (((value) << 16) & 0x00010000)
3234 
3235 /*
3236  * Field : ahb_ap
3237  *
3238  * Security bit configuration for transactions from ahb_ap to osc1_timer. When
3239  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3240  * Non-Secure transactions are allowed.
3241  *
3242  * Field Access Macros:
3243  *
3244  */
3245 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP register field. */
3246 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_LSB 24
3247 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP register field. */
3248 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_MSB 24
3249 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP register field. */
3250 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_WIDTH 1
3251 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP register field value. */
3252 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_SET_MSK 0x01000000
3253 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP register field value. */
3254 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_CLR_MSK 0xfeffffff
3255 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP register field. */
3256 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_RESET 0x0
3257 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP field value from a register. */
3258 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3259 /* Produces a ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP register field value suitable for setting the register. */
3260 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3261 
3262 #ifndef __ASSEMBLY__
3263 /*
3264  * WARNING: The C register and register group struct declarations are provided for
3265  * convenience and illustrative purposes. They should, however, be used with
3266  * caution as the C language standard provides no guarantees about the alignment or
3267  * atomicity of device memory accesses. The recommended practice for writing
3268  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3269  * alt_write_word() functions.
3270  *
3271  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR.
3272  */
3273 struct ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_s
3274 {
3275  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0 */
3276  uint32_t : 7; /* *UNDEFINED* */
3277  uint32_t dma : 1; /* ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA */
3278  uint32_t : 7; /* *UNDEFINED* */
3279  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H */
3280  uint32_t : 7; /* *UNDEFINED* */
3281  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP */
3282  uint32_t : 7; /* *UNDEFINED* */
3283 };
3284 
3285 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR. */
3286 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_s ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_t;
3287 #endif /* __ASSEMBLY__ */
3288 
3289 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR register. */
3290 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_RESET 0x00000000
3291 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR register from the beginning of the component. */
3292 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_OFST 0x64
3293 
3294 /*
3295  * Register : watchdog0
3296  *
3297  * Per-Master Security bit for watchdog0
3298  *
3299  * Register Layout
3300  *
3301  * Bits | Access | Reset | Description
3302  * :--------|:-------|:--------|:---------------------------------
3303  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0
3304  * [7:1] | ??? | Unknown | *UNDEFINED*
3305  * [8] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WD0_DMA
3306  * [15:9] | ??? | Unknown | *UNDEFINED*
3307  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WD0_F2H
3308  * [23:17] | ??? | Unknown | *UNDEFINED*
3309  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP
3310  * [31:25] | ??? | Unknown | *UNDEFINED*
3311  *
3312  */
3313 /*
3314  * Field : mpu_m0
3315  *
3316  * Security bit configuration for transactions from mpu_m0 to watchdog0. When
3317  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3318  * Non-Secure transactions are allowed.
3319  *
3320  * Field Access Macros:
3321  *
3322  */
3323 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0 register field. */
3324 #define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_LSB 0
3325 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0 register field. */
3326 #define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_MSB 0
3327 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0 register field. */
3328 #define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_WIDTH 1
3329 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0 register field value. */
3330 #define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_SET_MSK 0x00000001
3331 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0 register field value. */
3332 #define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_CLR_MSK 0xfffffffe
3333 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0 register field. */
3334 #define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_RESET 0x0
3335 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0 field value from a register. */
3336 #define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3337 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0 register field value suitable for setting the register. */
3338 #define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3339 
3340 /*
3341  * Field : dma
3342  *
3343  * Security bit configuration for transactions from dma to watchdog0. When cleared
3344  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3345  * Secure transactions are allowed.
3346  *
3347  * Field Access Macros:
3348  *
3349  */
3350 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WD0_DMA register field. */
3351 #define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_LSB 8
3352 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WD0_DMA register field. */
3353 #define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_MSB 8
3354 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WD0_DMA register field. */
3355 #define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_WIDTH 1
3356 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WD0_DMA register field value. */
3357 #define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_SET_MSK 0x00000100
3358 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WD0_DMA register field value. */
3359 #define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_CLR_MSK 0xfffffeff
3360 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WD0_DMA register field. */
3361 #define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_RESET 0x0
3362 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WD0_DMA field value from a register. */
3363 #define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_GET(value) (((value) & 0x00000100) >> 8)
3364 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WD0_DMA register field value suitable for setting the register. */
3365 #define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_SET(value) (((value) << 8) & 0x00000100)
3366 
3367 /*
3368  * Field : fpga2soc
3369  *
3370  * Security bit configuration for transactions from fpga2soc to watchdog0. When
3371  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3372  * Non-Secure transactions are allowed.
3373  *
3374  * Field Access Macros:
3375  *
3376  */
3377 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WD0_F2H register field. */
3378 #define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_LSB 16
3379 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WD0_F2H register field. */
3380 #define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_MSB 16
3381 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WD0_F2H register field. */
3382 #define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_WIDTH 1
3383 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WD0_F2H register field value. */
3384 #define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_SET_MSK 0x00010000
3385 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WD0_F2H register field value. */
3386 #define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_CLR_MSK 0xfffeffff
3387 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WD0_F2H register field. */
3388 #define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_RESET 0x0
3389 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WD0_F2H field value from a register. */
3390 #define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_GET(value) (((value) & 0x00010000) >> 16)
3391 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WD0_F2H register field value suitable for setting the register. */
3392 #define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_SET(value) (((value) << 16) & 0x00010000)
3393 
3394 /*
3395  * Field : ahb_ap
3396  *
3397  * Security bit configuration for transactions from ahb_ap to watchdog0. When
3398  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3399  * Non-Secure transactions are allowed.
3400  *
3401  * Field Access Macros:
3402  *
3403  */
3404 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP register field. */
3405 #define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_LSB 24
3406 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP register field. */
3407 #define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_MSB 24
3408 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP register field. */
3409 #define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_WIDTH 1
3410 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP register field value. */
3411 #define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_SET_MSK 0x01000000
3412 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP register field value. */
3413 #define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_CLR_MSK 0xfeffffff
3414 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP register field. */
3415 #define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_RESET 0x0
3416 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP field value from a register. */
3417 #define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3418 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP register field value suitable for setting the register. */
3419 #define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3420 
3421 #ifndef __ASSEMBLY__
3422 /*
3423  * WARNING: The C register and register group struct declarations are provided for
3424  * convenience and illustrative purposes. They should, however, be used with
3425  * caution as the C language standard provides no guarantees about the alignment or
3426  * atomicity of device memory accesses. The recommended practice for writing
3427  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3428  * alt_write_word() functions.
3429  *
3430  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_WD0.
3431  */
3432 struct ALT_NOC_FW_L4_SYS_SCR_WD0_s
3433 {
3434  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0 */
3435  uint32_t : 7; /* *UNDEFINED* */
3436  uint32_t dma : 1; /* ALT_NOC_FW_L4_SYS_SCR_WD0_DMA */
3437  uint32_t : 7; /* *UNDEFINED* */
3438  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_WD0_F2H */
3439  uint32_t : 7; /* *UNDEFINED* */
3440  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP */
3441  uint32_t : 7; /* *UNDEFINED* */
3442 };
3443 
3444 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_WD0. */
3445 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_WD0_s ALT_NOC_FW_L4_SYS_SCR_WD0_t;
3446 #endif /* __ASSEMBLY__ */
3447 
3448 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WD0 register. */
3449 #define ALT_NOC_FW_L4_SYS_SCR_WD0_RESET 0x00000000
3450 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_WD0 register from the beginning of the component. */
3451 #define ALT_NOC_FW_L4_SYS_SCR_WD0_OFST 0x68
3452 
3453 /*
3454  * Register : watchdog1
3455  *
3456  * Per-Master Security bit for watchdog1
3457  *
3458  * Register Layout
3459  *
3460  * Bits | Access | Reset | Description
3461  * :--------|:-------|:--------|:---------------------------------
3462  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0
3463  * [7:1] | ??? | Unknown | *UNDEFINED*
3464  * [8] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WD1_DMA
3465  * [15:9] | ??? | Unknown | *UNDEFINED*
3466  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WD1_F2H
3467  * [23:17] | ??? | Unknown | *UNDEFINED*
3468  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP
3469  * [31:25] | ??? | Unknown | *UNDEFINED*
3470  *
3471  */
3472 /*
3473  * Field : mpu_m0
3474  *
3475  * Security bit configuration for transactions from mpu_m0 to watchdog1. When
3476  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3477  * Non-Secure transactions are allowed.
3478  *
3479  * Field Access Macros:
3480  *
3481  */
3482 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0 register field. */
3483 #define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_LSB 0
3484 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0 register field. */
3485 #define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_MSB 0
3486 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0 register field. */
3487 #define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_WIDTH 1
3488 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0 register field value. */
3489 #define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_SET_MSK 0x00000001
3490 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0 register field value. */
3491 #define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_CLR_MSK 0xfffffffe
3492 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0 register field. */
3493 #define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_RESET 0x0
3494 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0 field value from a register. */
3495 #define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3496 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0 register field value suitable for setting the register. */
3497 #define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3498 
3499 /*
3500  * Field : dma
3501  *
3502  * Security bit configuration for transactions from dma to watchdog1. When cleared
3503  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3504  * Secure transactions are allowed.
3505  *
3506  * Field Access Macros:
3507  *
3508  */
3509 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WD1_DMA register field. */
3510 #define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_LSB 8
3511 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WD1_DMA register field. */
3512 #define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_MSB 8
3513 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WD1_DMA register field. */
3514 #define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_WIDTH 1
3515 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WD1_DMA register field value. */
3516 #define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_SET_MSK 0x00000100
3517 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WD1_DMA register field value. */
3518 #define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_CLR_MSK 0xfffffeff
3519 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WD1_DMA register field. */
3520 #define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_RESET 0x0
3521 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WD1_DMA field value from a register. */
3522 #define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_GET(value) (((value) & 0x00000100) >> 8)
3523 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WD1_DMA register field value suitable for setting the register. */
3524 #define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_SET(value) (((value) << 8) & 0x00000100)
3525 
3526 /*
3527  * Field : fpga2soc
3528  *
3529  * Security bit configuration for transactions from fpga2soc to watchdog1. When
3530  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3531  * Non-Secure transactions are allowed.
3532  *
3533  * Field Access Macros:
3534  *
3535  */
3536 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WD1_F2H register field. */
3537 #define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_LSB 16
3538 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WD1_F2H register field. */
3539 #define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_MSB 16
3540 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WD1_F2H register field. */
3541 #define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_WIDTH 1
3542 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WD1_F2H register field value. */
3543 #define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_SET_MSK 0x00010000
3544 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WD1_F2H register field value. */
3545 #define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_CLR_MSK 0xfffeffff
3546 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WD1_F2H register field. */
3547 #define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_RESET 0x0
3548 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WD1_F2H field value from a register. */
3549 #define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_GET(value) (((value) & 0x00010000) >> 16)
3550 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WD1_F2H register field value suitable for setting the register. */
3551 #define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_SET(value) (((value) << 16) & 0x00010000)
3552 
3553 /*
3554  * Field : ahb_ap
3555  *
3556  * Security bit configuration for transactions from ahb_ap to watchdog1. When
3557  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3558  * Non-Secure transactions are allowed.
3559  *
3560  * Field Access Macros:
3561  *
3562  */
3563 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP register field. */
3564 #define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_LSB 24
3565 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP register field. */
3566 #define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_MSB 24
3567 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP register field. */
3568 #define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_WIDTH 1
3569 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP register field value. */
3570 #define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_SET_MSK 0x01000000
3571 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP register field value. */
3572 #define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_CLR_MSK 0xfeffffff
3573 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP register field. */
3574 #define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_RESET 0x0
3575 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP field value from a register. */
3576 #define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3577 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP register field value suitable for setting the register. */
3578 #define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3579 
3580 #ifndef __ASSEMBLY__
3581 /*
3582  * WARNING: The C register and register group struct declarations are provided for
3583  * convenience and illustrative purposes. They should, however, be used with
3584  * caution as the C language standard provides no guarantees about the alignment or
3585  * atomicity of device memory accesses. The recommended practice for writing
3586  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3587  * alt_write_word() functions.
3588  *
3589  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_WD1.
3590  */
3591 struct ALT_NOC_FW_L4_SYS_SCR_WD1_s
3592 {
3593  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0 */
3594  uint32_t : 7; /* *UNDEFINED* */
3595  uint32_t dma : 1; /* ALT_NOC_FW_L4_SYS_SCR_WD1_DMA */
3596  uint32_t : 7; /* *UNDEFINED* */
3597  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_WD1_F2H */
3598  uint32_t : 7; /* *UNDEFINED* */
3599  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP */
3600  uint32_t : 7; /* *UNDEFINED* */
3601 };
3602 
3603 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_WD1. */
3604 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_WD1_s ALT_NOC_FW_L4_SYS_SCR_WD1_t;
3605 #endif /* __ASSEMBLY__ */
3606 
3607 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WD1 register. */
3608 #define ALT_NOC_FW_L4_SYS_SCR_WD1_RESET 0x00000000
3609 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_WD1 register from the beginning of the component. */
3610 #define ALT_NOC_FW_L4_SYS_SCR_WD1_OFST 0x6c
3611 
3612 /*
3613  * Register : dap
3614  *
3615  * Per-Master Security bit for dap
3616  *
3617  * Register Layout
3618  *
3619  * Bits | Access | Reset | Description
3620  * :--------|:-------|:--------|:---------------------------------
3621  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0
3622  * [7:1] | ??? | Unknown | *UNDEFINED*
3623  * [8] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_DAP_DMA
3624  * [15:9] | ??? | Unknown | *UNDEFINED*
3625  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_DAP_F2H
3626  * [23:17] | ??? | Unknown | *UNDEFINED*
3627  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP
3628  * [25] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_DAP_ETR
3629  * [31:26] | ??? | Unknown | *UNDEFINED*
3630  *
3631  */
3632 /*
3633  * Field : mpu_m0
3634  *
3635  * Security bit configuration for transactions from mpu_m0 to dap. When cleared
3636  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3637  * Secure transactions are allowed.
3638  *
3639  * Field Access Macros:
3640  *
3641  */
3642 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0 register field. */
3643 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_LSB 0
3644 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0 register field. */
3645 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_MSB 0
3646 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0 register field. */
3647 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_WIDTH 1
3648 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0 register field value. */
3649 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_SET_MSK 0x00000001
3650 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0 register field value. */
3651 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_CLR_MSK 0xfffffffe
3652 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0 register field. */
3653 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_RESET 0x0
3654 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0 field value from a register. */
3655 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3656 /* Produces a ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0 register field value suitable for setting the register. */
3657 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3658 
3659 /*
3660  * Field : dma
3661  *
3662  * Security bit configuration for transactions from dma to dap. When cleared (0),
3663  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
3664  * transactions are allowed.
3665  *
3666  * Field Access Macros:
3667  *
3668  */
3669 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_DAP_DMA register field. */
3670 #define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_LSB 8
3671 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_DAP_DMA register field. */
3672 #define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_MSB 8
3673 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_DAP_DMA register field. */
3674 #define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_WIDTH 1
3675 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_DAP_DMA register field value. */
3676 #define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_SET_MSK 0x00000100
3677 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_DAP_DMA register field value. */
3678 #define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_CLR_MSK 0xfffffeff
3679 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DAP_DMA register field. */
3680 #define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_RESET 0x0
3681 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_DAP_DMA field value from a register. */
3682 #define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_GET(value) (((value) & 0x00000100) >> 8)
3683 /* Produces a ALT_NOC_FW_L4_SYS_SCR_DAP_DMA register field value suitable for setting the register. */
3684 #define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_SET(value) (((value) << 8) & 0x00000100)
3685 
3686 /*
3687  * Field : fpga2soc
3688  *
3689  * Security bit configuration for transactions from fpga2soc to dap. When cleared
3690  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3691  * Secure transactions are allowed.
3692  *
3693  * Field Access Macros:
3694  *
3695  */
3696 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_DAP_F2H register field. */
3697 #define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_LSB 16
3698 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_DAP_F2H register field. */
3699 #define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_MSB 16
3700 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_DAP_F2H register field. */
3701 #define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_WIDTH 1
3702 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_DAP_F2H register field value. */
3703 #define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_SET_MSK 0x00010000
3704 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_DAP_F2H register field value. */
3705 #define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_CLR_MSK 0xfffeffff
3706 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DAP_F2H register field. */
3707 #define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_RESET 0x0
3708 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_DAP_F2H field value from a register. */
3709 #define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_GET(value) (((value) & 0x00010000) >> 16)
3710 /* Produces a ALT_NOC_FW_L4_SYS_SCR_DAP_F2H register field value suitable for setting the register. */
3711 #define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_SET(value) (((value) << 16) & 0x00010000)
3712 
3713 /*
3714  * Field : ahb_ap
3715  *
3716  * Security bit configuration for transactions from ahb_ap to dap. When cleared
3717  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3718  * Secure transactions are allowed.
3719  *
3720  * Field Access Macros:
3721  *
3722  */
3723 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP register field. */
3724 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_LSB 24
3725 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP register field. */
3726 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_MSB 24
3727 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP register field. */
3728 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_WIDTH 1
3729 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP register field value. */
3730 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_SET_MSK 0x01000000
3731 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP register field value. */
3732 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_CLR_MSK 0xfeffffff
3733 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP register field. */
3734 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_RESET 0x0
3735 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP field value from a register. */
3736 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3737 /* Produces a ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP register field value suitable for setting the register. */
3738 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3739 
3740 /*
3741  * Field : etr
3742  *
3743  * Security bit configuration for transactions from etr to dap. When cleared (0),
3744  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
3745  * transactions are allowed.
3746  *
3747  * Field Access Macros:
3748  *
3749  */
3750 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_DAP_ETR register field. */
3751 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_LSB 25
3752 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_DAP_ETR register field. */
3753 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_MSB 25
3754 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_DAP_ETR register field. */
3755 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_WIDTH 1
3756 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_DAP_ETR register field value. */
3757 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_SET_MSK 0x02000000
3758 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_DAP_ETR register field value. */
3759 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_CLR_MSK 0xfdffffff
3760 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DAP_ETR register field. */
3761 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_RESET 0x0
3762 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_DAP_ETR field value from a register. */
3763 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_GET(value) (((value) & 0x02000000) >> 25)
3764 /* Produces a ALT_NOC_FW_L4_SYS_SCR_DAP_ETR register field value suitable for setting the register. */
3765 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_SET(value) (((value) << 25) & 0x02000000)
3766 
3767 #ifndef __ASSEMBLY__
3768 /*
3769  * WARNING: The C register and register group struct declarations are provided for
3770  * convenience and illustrative purposes. They should, however, be used with
3771  * caution as the C language standard provides no guarantees about the alignment or
3772  * atomicity of device memory accesses. The recommended practice for writing
3773  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3774  * alt_write_word() functions.
3775  *
3776  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_DAP.
3777  */
3778 struct ALT_NOC_FW_L4_SYS_SCR_DAP_s
3779 {
3780  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0 */
3781  uint32_t : 7; /* *UNDEFINED* */
3782  uint32_t dma : 1; /* ALT_NOC_FW_L4_SYS_SCR_DAP_DMA */
3783  uint32_t : 7; /* *UNDEFINED* */
3784  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_DAP_F2H */
3785  uint32_t : 7; /* *UNDEFINED* */
3786  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP */
3787  uint32_t etr : 1; /* ALT_NOC_FW_L4_SYS_SCR_DAP_ETR */
3788  uint32_t : 6; /* *UNDEFINED* */
3789 };
3790 
3791 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_DAP. */
3792 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_DAP_s ALT_NOC_FW_L4_SYS_SCR_DAP_t;
3793 #endif /* __ASSEMBLY__ */
3794 
3795 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DAP register. */
3796 #define ALT_NOC_FW_L4_SYS_SCR_DAP_RESET 0x00000000
3797 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_DAP register from the beginning of the component. */
3798 #define ALT_NOC_FW_L4_SYS_SCR_DAP_OFST 0x70
3799 
3800 /*
3801  * Register : fpga_manager_streaming
3802  *
3803  * Per-Master Security bit for fpga_manager_streaming
3804  *
3805  * Register Layout
3806  *
3807  * Bits | Access | Reset | Description
3808  * :--------|:-------|:--------|:----------------------------------------------------
3809  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0
3810  * [7:1] | ??? | Unknown | *UNDEFINED*
3811  * [8] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA
3812  * [23:9] | ??? | Unknown | *UNDEFINED*
3813  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP
3814  * [31:25] | ??? | Unknown | *UNDEFINED*
3815  *
3816  */
3817 /*
3818  * Field : mpu_m0
3819  *
3820  * Security bit configuration for transactions from mpu_m0 to
3821  * fpga_manager_streaming. When cleared (0), only Secure transactions are allowed.
3822  * When set (1), both Secure and Non-Secure transactions are allowed.
3823  *
3824  * Field Access Macros:
3825  *
3826  */
3827 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0 register field. */
3828 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_LSB 0
3829 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0 register field. */
3830 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_MSB 0
3831 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0 register field. */
3832 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_WIDTH 1
3833 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0 register field value. */
3834 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_SET_MSK 0x00000001
3835 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0 register field value. */
3836 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_CLR_MSK 0xfffffffe
3837 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0 register field. */
3838 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_RESET 0x0
3839 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0 field value from a register. */
3840 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3841 /* Produces a ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0 register field value suitable for setting the register. */
3842 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3843 
3844 /*
3845  * Field : dma
3846  *
3847  * Security bit configuration for transactions from dma to fpga_manager_streaming.
3848  * When cleared (0), only Secure transactions are allowed. When set (1), both
3849  * Secure and Non-Secure transactions are allowed.
3850  *
3851  * Field Access Macros:
3852  *
3853  */
3854 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA register field. */
3855 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_LSB 8
3856 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA register field. */
3857 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_MSB 8
3858 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA register field. */
3859 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_WIDTH 1
3860 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA register field value. */
3861 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_SET_MSK 0x00000100
3862 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA register field value. */
3863 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_CLR_MSK 0xfffffeff
3864 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA register field. */
3865 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_RESET 0x0
3866 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA field value from a register. */
3867 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_GET(value) (((value) & 0x00000100) >> 8)
3868 /* Produces a ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA register field value suitable for setting the register. */
3869 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_SET(value) (((value) << 8) & 0x00000100)
3870 
3871 /*
3872  * Field : ahb_ap
3873  *
3874  * Security bit configuration for transactions from ahb_ap to
3875  * fpga_manager_streaming. When cleared (0), only Secure transactions are allowed.
3876  * When set (1), both Secure and Non-Secure transactions are allowed.
3877  *
3878  * Field Access Macros:
3879  *
3880  */
3881 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP register field. */
3882 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_LSB 24
3883 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP register field. */
3884 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_MSB 24
3885 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP register field. */
3886 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_WIDTH 1
3887 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP register field value. */
3888 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_SET_MSK 0x01000000
3889 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP register field value. */
3890 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_CLR_MSK 0xfeffffff
3891 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP register field. */
3892 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_RESET 0x0
3893 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP field value from a register. */
3894 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3895 /* Produces a ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP register field value suitable for setting the register. */
3896 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3897 
3898 #ifndef __ASSEMBLY__
3899 /*
3900  * WARNING: The C register and register group struct declarations are provided for
3901  * convenience and illustrative purposes. They should, however, be used with
3902  * caution as the C language standard provides no guarantees about the alignment or
3903  * atomicity of device memory accesses. The recommended practice for writing
3904  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3905  * alt_write_word() functions.
3906  *
3907  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING.
3908  */
3909 struct ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_s
3910 {
3911  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0 */
3912  uint32_t : 7; /* *UNDEFINED* */
3913  uint32_t dma : 1; /* ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA */
3914  uint32_t : 15; /* *UNDEFINED* */
3915  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP */
3916  uint32_t : 7; /* *UNDEFINED* */
3917 };
3918 
3919 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING. */
3920 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_s ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_t;
3921 #endif /* __ASSEMBLY__ */
3922 
3923 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING register. */
3924 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_RESET 0x00000000
3925 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING register from the beginning of the component. */
3926 #define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_OFST 0x74
3927 
3928 /*
3929  * Register : security_manager_streaming
3930  *
3931  * Per-Master Security bit for security_manager_streaming
3932  *
3933  * Register Layout
3934  *
3935  * Bits | Access | Reset | Description
3936  * :--------|:-------|:--------|:-----------------------------------------------
3937  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0
3938  * [7:1] | ??? | Unknown | *UNDEFINED*
3939  * [8] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA
3940  * [23:9] | ??? | Unknown | *UNDEFINED*
3941  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP
3942  * [31:25] | ??? | Unknown | *UNDEFINED*
3943  *
3944  */
3945 /*
3946  * Field : mpu_m0
3947  *
3948  * Security bit configuration for transactions from mpu_m0 to
3949  * security_manager_streaming. When cleared (0), only Secure transactions are
3950  * allowed. When set (1), both Secure and Non-Secure transactions are allowed.
3951  *
3952  * Field Access Macros:
3953  *
3954  */
3955 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0 register field. */
3956 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_LSB 0
3957 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0 register field. */
3958 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_MSB 0
3959 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0 register field. */
3960 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_WIDTH 1
3961 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0 register field value. */
3962 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_SET_MSK 0x00000001
3963 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0 register field value. */
3964 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_CLR_MSK 0xfffffffe
3965 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0 register field. */
3966 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_RESET 0x0
3967 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0 field value from a register. */
3968 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3969 /* Produces a ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0 register field value suitable for setting the register. */
3970 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3971 
3972 /*
3973  * Field : dma
3974  *
3975  * Security bit configuration for transactions from dma to
3976  * security_manager_streaming. When cleared (0), only Secure transactions are
3977  * allowed. When set (1), both Secure and Non-Secure transactions are allowed.
3978  *
3979  * Field Access Macros:
3980  *
3981  */
3982 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA register field. */
3983 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_LSB 8
3984 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA register field. */
3985 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_MSB 8
3986 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA register field. */
3987 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_WIDTH 1
3988 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA register field value. */
3989 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_SET_MSK 0x00000100
3990 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA register field value. */
3991 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_CLR_MSK 0xfffffeff
3992 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA register field. */
3993 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_RESET 0x0
3994 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA field value from a register. */
3995 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_GET(value) (((value) & 0x00000100) >> 8)
3996 /* Produces a ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA register field value suitable for setting the register. */
3997 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_SET(value) (((value) << 8) & 0x00000100)
3998 
3999 /*
4000  * Field : ahb_ap
4001  *
4002  * Security bit configuration for transactions from ahb_ap to
4003  * security_manager_streaming. When cleared (0), only Secure transactions are
4004  * allowed. When set (1), both Secure and Non-Secure transactions are allowed.
4005  *
4006  * Field Access Macros:
4007  *
4008  */
4009 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP register field. */
4010 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_LSB 24
4011 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP register field. */
4012 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_MSB 24
4013 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP register field. */
4014 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_WIDTH 1
4015 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP register field value. */
4016 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_SET_MSK 0x01000000
4017 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP register field value. */
4018 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_CLR_MSK 0xfeffffff
4019 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP register field. */
4020 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_RESET 0x0
4021 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP field value from a register. */
4022 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4023 /* Produces a ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP register field value suitable for setting the register. */
4024 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4025 
4026 #ifndef __ASSEMBLY__
4027 /*
4028  * WARNING: The C register and register group struct declarations are provided for
4029  * convenience and illustrative purposes. They should, however, be used with
4030  * caution as the C language standard provides no guarantees about the alignment or
4031  * atomicity of device memory accesses. The recommended practice for writing
4032  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4033  * alt_write_word() functions.
4034  *
4035  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING.
4036  */
4037 struct ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_s
4038 {
4039  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0 */
4040  uint32_t : 7; /* *UNDEFINED* */
4041  uint32_t dma : 1; /* ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA */
4042  uint32_t : 15; /* *UNDEFINED* */
4043  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP */
4044  uint32_t : 7; /* *UNDEFINED* */
4045 };
4046 
4047 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING. */
4048 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_s ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_t;
4049 #endif /* __ASSEMBLY__ */
4050 
4051 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING register. */
4052 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_RESET 0x00000000
4053 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING register from the beginning of the component. */
4054 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_OFST 0x78
4055 /* The address of the ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING register. */
4056 #define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_OFST))
4057 
4058 /*
4059  * Register : hmc_register
4060  *
4061  * Per-Master Security bit for hmc_register
4062  *
4063  * Register Layout
4064  *
4065  * Bits | Access | Reset | Description
4066  * :--------|:-------|:--------|:-------------------------------------
4067  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0
4068  * [7:1] | ??? | Unknown | *UNDEFINED*
4069  * [8] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA
4070  * [15:9] | ??? | Unknown | *UNDEFINED*
4071  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H
4072  * [23:17] | ??? | Unknown | *UNDEFINED*
4073  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP
4074  * [31:25] | ??? | Unknown | *UNDEFINED*
4075  *
4076  */
4077 /*
4078  * Field : mpu_m0
4079  *
4080  * Security bit configuration for transactions from mpu_m0 to hmc_register. When
4081  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
4082  * Non-Secure transactions are allowed.
4083  *
4084  * Field Access Macros:
4085  *
4086  */
4087 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0 register field. */
4088 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_LSB 0
4089 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0 register field. */
4090 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_MSB 0
4091 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0 register field. */
4092 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_WIDTH 1
4093 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0 register field value. */
4094 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_SET_MSK 0x00000001
4095 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0 register field value. */
4096 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_CLR_MSK 0xfffffffe
4097 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0 register field. */
4098 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_RESET 0x0
4099 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0 field value from a register. */
4100 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4101 /* Produces a ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0 register field value suitable for setting the register. */
4102 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4103 
4104 /*
4105  * Field : dma
4106  *
4107  * Security bit configuration for transactions from dma to hmc_register. When
4108  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
4109  * Non-Secure transactions are allowed.
4110  *
4111  * Field Access Macros:
4112  *
4113  */
4114 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA register field. */
4115 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_LSB 8
4116 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA register field. */
4117 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_MSB 8
4118 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA register field. */
4119 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_WIDTH 1
4120 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA register field value. */
4121 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_SET_MSK 0x00000100
4122 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA register field value. */
4123 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_CLR_MSK 0xfffffeff
4124 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA register field. */
4125 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_RESET 0x0
4126 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA field value from a register. */
4127 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_GET(value) (((value) & 0x00000100) >> 8)
4128 /* Produces a ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA register field value suitable for setting the register. */
4129 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_SET(value) (((value) << 8) & 0x00000100)
4130 
4131 /*
4132  * Field : fpga2soc
4133  *
4134  * Security bit configuration for transactions from fpga2soc to hmc_register. When
4135  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
4136  * Non-Secure transactions are allowed.
4137  *
4138  * Field Access Macros:
4139  *
4140  */
4141 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H register field. */
4142 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_LSB 16
4143 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H register field. */
4144 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_MSB 16
4145 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H register field. */
4146 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_WIDTH 1
4147 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H register field value. */
4148 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_SET_MSK 0x00010000
4149 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H register field value. */
4150 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_CLR_MSK 0xfffeffff
4151 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H register field. */
4152 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_RESET 0x0
4153 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H field value from a register. */
4154 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
4155 /* Produces a ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H register field value suitable for setting the register. */
4156 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
4157 
4158 /*
4159  * Field : ahb_ap
4160  *
4161  * Security bit configuration for transactions from ahb_ap to hmc_register. When
4162  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
4163  * Non-Secure transactions are allowed.
4164  *
4165  * Field Access Macros:
4166  *
4167  */
4168 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP register field. */
4169 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_LSB 24
4170 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP register field. */
4171 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_MSB 24
4172 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP register field. */
4173 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_WIDTH 1
4174 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP register field value. */
4175 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_SET_MSK 0x01000000
4176 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP register field value. */
4177 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_CLR_MSK 0xfeffffff
4178 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP register field. */
4179 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_RESET 0x0
4180 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP field value from a register. */
4181 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4182 /* Produces a ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP register field value suitable for setting the register. */
4183 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4184 
4185 #ifndef __ASSEMBLY__
4186 /*
4187  * WARNING: The C register and register group struct declarations are provided for
4188  * convenience and illustrative purposes. They should, however, be used with
4189  * caution as the C language standard provides no guarantees about the alignment or
4190  * atomicity of device memory accesses. The recommended practice for writing
4191  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4192  * alt_write_word() functions.
4193  *
4194  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_HMC_REG.
4195  */
4196 struct ALT_NOC_FW_L4_SYS_SCR_HMC_REG_s
4197 {
4198  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0 */
4199  uint32_t : 7; /* *UNDEFINED* */
4200  uint32_t dma : 1; /* ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA */
4201  uint32_t : 7; /* *UNDEFINED* */
4202  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H */
4203  uint32_t : 7; /* *UNDEFINED* */
4204  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP */
4205  uint32_t : 7; /* *UNDEFINED* */
4206 };
4207 
4208 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_HMC_REG. */
4209 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_HMC_REG_s ALT_NOC_FW_L4_SYS_SCR_HMC_REG_t;
4210 #endif /* __ASSEMBLY__ */
4211 
4212 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_HMC_REG register. */
4213 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_RESET 0x00000000
4214 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_HMC_REG register from the beginning of the component. */
4215 #define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_OFST 0x7c
4216 
4217 /*
4218  * Register : hmc_adaptor_register
4219  *
4220  * Per-Master Security bit for hmc_adaptor_register
4221  *
4222  * Register Layout
4223  *
4224  * Bits | Access | Reset | Description
4225  * :--------|:-------|:--------|:---------------------------------------------
4226  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0
4227  * [7:1] | ??? | Unknown | *UNDEFINED*
4228  * [8] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA
4229  * [15:9] | ??? | Unknown | *UNDEFINED*
4230  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H
4231  * [23:17] | ??? | Unknown | *UNDEFINED*
4232  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP
4233  * [31:25] | ??? | Unknown | *UNDEFINED*
4234  *
4235  */
4236 /*
4237  * Field : mpu_m0
4238  *
4239  * Security bit configuration for transactions from mpu_m0 to hmc_adaptor_register.
4240  * When cleared (0), only Secure transactions are allowed. When set (1), both
4241  * Secure and Non-Secure transactions are allowed.
4242  *
4243  * Field Access Macros:
4244  *
4245  */
4246 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0 register field. */
4247 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_LSB 0
4248 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0 register field. */
4249 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_MSB 0
4250 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0 register field. */
4251 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_WIDTH 1
4252 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0 register field value. */
4253 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_SET_MSK 0x00000001
4254 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0 register field value. */
4255 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_CLR_MSK 0xfffffffe
4256 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0 register field. */
4257 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_RESET 0x0
4258 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0 field value from a register. */
4259 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4260 /* Produces a ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0 register field value suitable for setting the register. */
4261 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4262 
4263 /*
4264  * Field : dma
4265  *
4266  * Security bit configuration for transactions from dma to hmc_adaptor_register.
4267  * When cleared (0), only Secure transactions are allowed. When set (1), both
4268  * Secure and Non-Secure transactions are allowed.
4269  *
4270  * Field Access Macros:
4271  *
4272  */
4273 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA register field. */
4274 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_LSB 8
4275 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA register field. */
4276 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_MSB 8
4277 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA register field. */
4278 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_WIDTH 1
4279 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA register field value. */
4280 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_SET_MSK 0x00000100
4281 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA register field value. */
4282 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_CLR_MSK 0xfffffeff
4283 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA register field. */
4284 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_RESET 0x0
4285 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA field value from a register. */
4286 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_GET(value) (((value) & 0x00000100) >> 8)
4287 /* Produces a ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA register field value suitable for setting the register. */
4288 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_SET(value) (((value) << 8) & 0x00000100)
4289 
4290 /*
4291  * Field : fpga2soc
4292  *
4293  * Security bit configuration for transactions from fpga2soc to
4294  * hmc_adaptor_register. When cleared (0), only Secure transactions are allowed.
4295  * When set (1), both Secure and Non-Secure transactions are allowed.
4296  *
4297  * Field Access Macros:
4298  *
4299  */
4300 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H register field. */
4301 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_LSB 16
4302 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H register field. */
4303 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_MSB 16
4304 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H register field. */
4305 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_WIDTH 1
4306 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H register field value. */
4307 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_SET_MSK 0x00010000
4308 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H register field value. */
4309 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_CLR_MSK 0xfffeffff
4310 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H register field. */
4311 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_RESET 0x0
4312 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H field value from a register. */
4313 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
4314 /* Produces a ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H register field value suitable for setting the register. */
4315 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
4316 
4317 /*
4318  * Field : ahb_ap
4319  *
4320  * Security bit configuration for transactions from ahb_ap to hmc_adaptor_register.
4321  * When cleared (0), only Secure transactions are allowed. When set (1), both
4322  * Secure and Non-Secure transactions are allowed.
4323  *
4324  * Field Access Macros:
4325  *
4326  */
4327 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP register field. */
4328 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_LSB 24
4329 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP register field. */
4330 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_MSB 24
4331 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP register field. */
4332 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_WIDTH 1
4333 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP register field value. */
4334 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_SET_MSK 0x01000000
4335 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP register field value. */
4336 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_CLR_MSK 0xfeffffff
4337 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP register field. */
4338 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_RESET 0x0
4339 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP field value from a register. */
4340 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4341 /* Produces a ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP register field value suitable for setting the register. */
4342 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4343 
4344 #ifndef __ASSEMBLY__
4345 /*
4346  * WARNING: The C register and register group struct declarations are provided for
4347  * convenience and illustrative purposes. They should, however, be used with
4348  * caution as the C language standard provides no guarantees about the alignment or
4349  * atomicity of device memory accesses. The recommended practice for writing
4350  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4351  * alt_write_word() functions.
4352  *
4353  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG.
4354  */
4355 struct ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_s
4356 {
4357  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0 */
4358  uint32_t : 7; /* *UNDEFINED* */
4359  uint32_t dma : 1; /* ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA */
4360  uint32_t : 7; /* *UNDEFINED* */
4361  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H */
4362  uint32_t : 7; /* *UNDEFINED* */
4363  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP */
4364  uint32_t : 7; /* *UNDEFINED* */
4365 };
4366 
4367 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG. */
4368 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_s ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_t;
4369 #endif /* __ASSEMBLY__ */
4370 
4371 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG register. */
4372 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_RESET 0x00000000
4373 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG register from the beginning of the component. */
4374 #define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_OFST 0x80
4375 
4376 /*
4377  * Register : l3_interconnect_register
4378  *
4379  * Per-Master Security bit for ddr_scheduler_register
4380  *
4381  * Register Layout
4382  *
4383  * Bits | Access | Reset | Description
4384  * :--------|:-------|:--------|:-------------------------------------------------
4385  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0
4386  * [15:1] | ??? | Unknown | *UNDEFINED*
4387  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H
4388  * [23:17] | ??? | Unknown | *UNDEFINED*
4389  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP
4390  * [31:25] | ??? | Unknown | *UNDEFINED*
4391  *
4392  */
4393 /*
4394  * Field : mpu_m0
4395  *
4396  * Security bit configuration for transactions from mpu_m0 to
4397  * ddr_scheduler_register. When cleared (0), only Secure transactions are allowed.
4398  * When set (1), both Secure and Non-Secure transactions are allowed.
4399  *
4400  * Field Access Macros:
4401  *
4402  */
4403 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0 register field. */
4404 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_LSB 0
4405 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0 register field. */
4406 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_MSB 0
4407 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0 register field. */
4408 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_WIDTH 1
4409 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0 register field value. */
4410 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_SET_MSK 0x00000001
4411 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0 register field value. */
4412 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_CLR_MSK 0xfffffffe
4413 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0 register field. */
4414 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_RESET 0x0
4415 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0 field value from a register. */
4416 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4417 /* Produces a ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0 register field value suitable for setting the register. */
4418 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4419 
4420 /*
4421  * Field : fpga2soc
4422  *
4423  * Security bit configuration for transactions from fpga2soc to
4424  * ddr_scheduler_register. When cleared (0), only Secure transactions are allowed.
4425  * When set (1), both Secure and Non-Secure transactions are allowed.
4426  *
4427  * Field Access Macros:
4428  *
4429  */
4430 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H register field. */
4431 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_LSB 16
4432 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H register field. */
4433 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_MSB 16
4434 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H register field. */
4435 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_WIDTH 1
4436 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H register field value. */
4437 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_SET_MSK 0x00010000
4438 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H register field value. */
4439 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_CLR_MSK 0xfffeffff
4440 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H register field. */
4441 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_RESET 0x0
4442 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H field value from a register. */
4443 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
4444 /* Produces a ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H register field value suitable for setting the register. */
4445 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
4446 
4447 /*
4448  * Field : ahb_ap
4449  *
4450  * Security bit configuration for transactions from ahb_ap to
4451  * ddr_schedule_register. When cleared (0), only Secure transactions are allowed.
4452  * When set (1), both Secure and Non-Secure transactions are allowed.
4453  *
4454  * Field Access Macros:
4455  *
4456  */
4457 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP register field. */
4458 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_LSB 24
4459 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP register field. */
4460 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_MSB 24
4461 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP register field. */
4462 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_WIDTH 1
4463 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP register field value. */
4464 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_SET_MSK 0x01000000
4465 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP register field value. */
4466 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_CLR_MSK 0xfeffffff
4467 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP register field. */
4468 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_RESET 0x0
4469 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP field value from a register. */
4470 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4471 /* Produces a ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP register field value suitable for setting the register. */
4472 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4473 
4474 #ifndef __ASSEMBLY__
4475 /*
4476  * WARNING: The C register and register group struct declarations are provided for
4477  * convenience and illustrative purposes. They should, however, be used with
4478  * caution as the C language standard provides no guarantees about the alignment or
4479  * atomicity of device memory accesses. The recommended practice for writing
4480  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4481  * alt_write_word() functions.
4482  *
4483  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG.
4484  */
4485 struct ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_s
4486 {
4487  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0 */
4488  uint32_t : 15; /* *UNDEFINED* */
4489  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H */
4490  uint32_t : 7; /* *UNDEFINED* */
4491  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP */
4492  uint32_t : 7; /* *UNDEFINED* */
4493 };
4494 
4495 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG. */
4496 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_s ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_t;
4497 #endif /* __ASSEMBLY__ */
4498 
4499 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG register. */
4500 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_RESET 0x00000000
4501 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG register from the beginning of the component. */
4502 #define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_OFST 0x84
4503 
4504 /*
4505  * Register : ddr_scheduler_register
4506  *
4507  * Per-Master Security bit for ddr_scheduler_register
4508  *
4509  * Register Layout
4510  *
4511  * Bits | Access | Reset | Description
4512  * :--------|:-------|:--------|:-------------------------------------------
4513  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0
4514  * [15:1] | ??? | Unknown | *UNDEFINED*
4515  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H
4516  * [23:17] | ??? | Unknown | *UNDEFINED*
4517  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP
4518  * [31:25] | ??? | Unknown | *UNDEFINED*
4519  *
4520  */
4521 /*
4522  * Field : mpu_m0
4523  *
4524  * Security bit configuration for transactions from mpu_m0 to
4525  * ddr_scheduler_register. When cleared (0), only Secure transactions are allowed.
4526  * When set (1), both Secure and Non-Secure transactions are allowed.
4527  *
4528  * Field Access Macros:
4529  *
4530  */
4531 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0 register field. */
4532 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_LSB 0
4533 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0 register field. */
4534 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_MSB 0
4535 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0 register field. */
4536 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_WIDTH 1
4537 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0 register field value. */
4538 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_SET_MSK 0x00000001
4539 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0 register field value. */
4540 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_CLR_MSK 0xfffffffe
4541 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0 register field. */
4542 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_RESET 0x0
4543 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0 field value from a register. */
4544 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4545 /* Produces a ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0 register field value suitable for setting the register. */
4546 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4547 
4548 /*
4549  * Field : fpga2soc
4550  *
4551  * Security bit configuration for transactions from fpga2soc to
4552  * ddr_scheduler_register. When cleared (0), only Secure transactions are allowed.
4553  * When set (1), both Secure and Non-Secure transactions are allowed.
4554  *
4555  * Field Access Macros:
4556  *
4557  */
4558 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H register field. */
4559 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_LSB 16
4560 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H register field. */
4561 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_MSB 16
4562 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H register field. */
4563 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_WIDTH 1
4564 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H register field value. */
4565 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_SET_MSK 0x00010000
4566 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H register field value. */
4567 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_CLR_MSK 0xfffeffff
4568 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H register field. */
4569 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_RESET 0x0
4570 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H field value from a register. */
4571 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
4572 /* Produces a ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H register field value suitable for setting the register. */
4573 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
4574 
4575 /*
4576  * Field : ahb_ap
4577  *
4578  * Security bit configuration for transactions from ahb_ap to
4579  * ddr_schedule_register. When cleared (0), only Secure transactions are allowed.
4580  * When set (1), both Secure and Non-Secure transactions are allowed.
4581  *
4582  * Field Access Macros:
4583  *
4584  */
4585 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP register field. */
4586 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_LSB 24
4587 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP register field. */
4588 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_MSB 24
4589 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP register field. */
4590 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_WIDTH 1
4591 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP register field value. */
4592 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_SET_MSK 0x01000000
4593 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP register field value. */
4594 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_CLR_MSK 0xfeffffff
4595 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP register field. */
4596 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_RESET 0x0
4597 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP field value from a register. */
4598 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4599 /* Produces a ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP register field value suitable for setting the register. */
4600 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4601 
4602 #ifndef __ASSEMBLY__
4603 /*
4604  * WARNING: The C register and register group struct declarations are provided for
4605  * convenience and illustrative purposes. They should, however, be used with
4606  * caution as the C language standard provides no guarantees about the alignment or
4607  * atomicity of device memory accesses. The recommended practice for writing
4608  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4609  * alt_write_word() functions.
4610  *
4611  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG.
4612  */
4613 struct ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_s
4614 {
4615  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0 */
4616  uint32_t : 15; /* *UNDEFINED* */
4617  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H */
4618  uint32_t : 7; /* *UNDEFINED* */
4619  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP */
4620  uint32_t : 7; /* *UNDEFINED* */
4621 };
4622 
4623 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG. */
4624 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_s ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_t;
4625 #endif /* __ASSEMBLY__ */
4626 
4627 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG register. */
4628 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_RESET 0x00000000
4629 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG register from the beginning of the component. */
4630 #define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_OFST 0x88
4631 
4632 /*
4633  * Register : l4_interconnect_firewall_csr
4634  *
4635  * Per-Master Security bit for noc_firewall_scr
4636  *
4637  * Register Layout
4638  *
4639  * Bits | Access | Reset | Description
4640  * :--------|:-------|:--------|:----------------------------------------------------
4641  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0
4642  * [15:1] | ??? | Unknown | *UNDEFINED*
4643  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H
4644  * [23:17] | ??? | Unknown | *UNDEFINED*
4645  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP
4646  * [31:25] | ??? | Unknown | *UNDEFINED*
4647  *
4648  */
4649 /*
4650  * Field : mpu_m0
4651  *
4652  * Security bit configuration for transactions from mpu_m0 to noc_firewall_scr.
4653  * When cleared (0), only Secure transactions are allowed. When set (1), both
4654  * Secure and Non-Secure transactions are allowed.
4655  *
4656  * Field Access Macros:
4657  *
4658  */
4659 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0 register field. */
4660 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_LSB 0
4661 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0 register field. */
4662 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_MSB 0
4663 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0 register field. */
4664 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_WIDTH 1
4665 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0 register field value. */
4666 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_SET_MSK 0x00000001
4667 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0 register field value. */
4668 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_CLR_MSK 0xfffffffe
4669 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0 register field. */
4670 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_RESET 0x0
4671 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0 field value from a register. */
4672 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4673 /* Produces a ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0 register field value suitable for setting the register. */
4674 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4675 
4676 /*
4677  * Field : fpga2soc
4678  *
4679  * Security bit configuration for transactions from fpga2soc to noc_firewall_scr.
4680  * When cleared (0), only Secure transactions are allowed. When set (1), both
4681  * Secure and Non-Secure transactions are allowed.
4682  *
4683  * Field Access Macros:
4684  *
4685  */
4686 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H register field. */
4687 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_LSB 16
4688 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H register field. */
4689 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_MSB 16
4690 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H register field. */
4691 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_WIDTH 1
4692 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H register field value. */
4693 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_SET_MSK 0x00010000
4694 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H register field value. */
4695 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_CLR_MSK 0xfffeffff
4696 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H register field. */
4697 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_RESET 0x0
4698 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H field value from a register. */
4699 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_GET(value) (((value) & 0x00010000) >> 16)
4700 /* Produces a ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H register field value suitable for setting the register. */
4701 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_SET(value) (((value) << 16) & 0x00010000)
4702 
4703 /*
4704  * Field : ahb_ap
4705  *
4706  * Security bit configuration for transactions from ahb_ap to noc_firewall_scr.
4707  * When cleared (0), only Secure transactions are allowed. When set (1), both
4708  * Secure and Non-Secure transactions are allowed.
4709  *
4710  * Field Access Macros:
4711  *
4712  */
4713 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP register field. */
4714 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_LSB 24
4715 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP register field. */
4716 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_MSB 24
4717 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP register field. */
4718 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_WIDTH 1
4719 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP register field value. */
4720 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_SET_MSK 0x01000000
4721 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP register field value. */
4722 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_CLR_MSK 0xfeffffff
4723 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP register field. */
4724 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_RESET 0x0
4725 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP field value from a register. */
4726 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4727 /* Produces a ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP register field value suitable for setting the register. */
4728 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4729 
4730 #ifndef __ASSEMBLY__
4731 /*
4732  * WARNING: The C register and register group struct declarations are provided for
4733  * convenience and illustrative purposes. They should, however, be used with
4734  * caution as the C language standard provides no guarantees about the alignment or
4735  * atomicity of device memory accesses. The recommended practice for writing
4736  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4737  * alt_write_word() functions.
4738  *
4739  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR.
4740  */
4741 struct ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_s
4742 {
4743  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0 */
4744  uint32_t : 15; /* *UNDEFINED* */
4745  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H */
4746  uint32_t : 7; /* *UNDEFINED* */
4747  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP */
4748  uint32_t : 7; /* *UNDEFINED* */
4749 };
4750 
4751 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR. */
4752 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_s ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_t;
4753 #endif /* __ASSEMBLY__ */
4754 
4755 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR register. */
4756 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_RESET 0x00000000
4757 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR register from the beginning of the component. */
4758 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_OFST 0x8c
4759 
4760 /*
4761  * Register : l4_interconnect_probes_csr
4762  *
4763  * Per-Master Security bit for noc_probes_register
4764  *
4765  * Register Layout
4766  *
4767  * Bits | Access | Reset | Description
4768  * :--------|:-------|:--------|:------------------------------------------------------
4769  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0
4770  * [15:1] | ??? | Unknown | *UNDEFINED*
4771  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H
4772  * [23:17] | ??? | Unknown | *UNDEFINED*
4773  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP
4774  * [31:25] | ??? | Unknown | *UNDEFINED*
4775  *
4776  */
4777 /*
4778  * Field : mpu_m0
4779  *
4780  * Security bit configuration for transactions from mpu_m0 to noc_probes_register.
4781  * When cleared (0), only Secure transactions are allowed. When set (1), both
4782  * Secure and Non-Secure transactions are allowed.
4783  *
4784  * Field Access Macros:
4785  *
4786  */
4787 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0 register field. */
4788 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_LSB 0
4789 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0 register field. */
4790 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_MSB 0
4791 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0 register field. */
4792 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_WIDTH 1
4793 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0 register field value. */
4794 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_SET_MSK 0x00000001
4795 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0 register field value. */
4796 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_CLR_MSK 0xfffffffe
4797 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0 register field. */
4798 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_RESET 0x0
4799 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0 field value from a register. */
4800 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4801 /* Produces a ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0 register field value suitable for setting the register. */
4802 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4803 
4804 /*
4805  * Field : fpga2soc
4806  *
4807  * Security bit configuration for transactions from fpga2soc to
4808  * noc_probes_register. When cleared (0), only Secure transactions are allowed.
4809  * When set (1), both Secure and Non-Secure transactions are allowed.
4810  *
4811  * Field Access Macros:
4812  *
4813  */
4814 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H register field. */
4815 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_LSB 16
4816 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H register field. */
4817 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_MSB 16
4818 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H register field. */
4819 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_WIDTH 1
4820 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H register field value. */
4821 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_SET_MSK 0x00010000
4822 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H register field value. */
4823 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_CLR_MSK 0xfffeffff
4824 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H register field. */
4825 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_RESET 0x0
4826 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H field value from a register. */
4827 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_GET(value) (((value) & 0x00010000) >> 16)
4828 /* Produces a ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H register field value suitable for setting the register. */
4829 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_SET(value) (((value) << 16) & 0x00010000)
4830 
4831 /*
4832  * Field : ahb_ap
4833  *
4834  * Security bit configuration for transactions from ahb_ap to noc_probes_register.
4835  * When cleared (0), only Secure transactions are allowed. When set (1), both
4836  * Secure and Non-Secure transactions are allowed.
4837  *
4838  * Field Access Macros:
4839  *
4840  */
4841 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP register field. */
4842 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_LSB 24
4843 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP register field. */
4844 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_MSB 24
4845 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP register field. */
4846 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_WIDTH 1
4847 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP register field value. */
4848 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_SET_MSK 0x01000000
4849 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP register field value. */
4850 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_CLR_MSK 0xfeffffff
4851 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP register field. */
4852 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_RESET 0x0
4853 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP field value from a register. */
4854 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4855 /* Produces a ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP register field value suitable for setting the register. */
4856 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4857 
4858 #ifndef __ASSEMBLY__
4859 /*
4860  * WARNING: The C register and register group struct declarations are provided for
4861  * convenience and illustrative purposes. They should, however, be used with
4862  * caution as the C language standard provides no guarantees about the alignment or
4863  * atomicity of device memory accesses. The recommended practice for writing
4864  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4865  * alt_write_word() functions.
4866  *
4867  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR.
4868  */
4869 struct ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_s
4870 {
4871  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0 */
4872  uint32_t : 15; /* *UNDEFINED* */
4873  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H */
4874  uint32_t : 7; /* *UNDEFINED* */
4875  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP */
4876  uint32_t : 7; /* *UNDEFINED* */
4877 };
4878 
4879 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR. */
4880 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_s ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_t;
4881 #endif /* __ASSEMBLY__ */
4882 
4883 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR register. */
4884 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_RESET 0x00000000
4885 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR register from the beginning of the component. */
4886 #define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_OFST 0x90
4887 
4888 /*
4889  * Register : l4_qos_csr
4890  *
4891  * Per-Master Security bit for noc_probes_register
4892  *
4893  * Register Layout
4894  *
4895  * Bits | Access | Reset | Description
4896  * :--------|:-------|:--------|:----------------------------------------
4897  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0
4898  * [15:1] | ??? | Unknown | *UNDEFINED*
4899  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H
4900  * [23:17] | ??? | Unknown | *UNDEFINED*
4901  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP
4902  * [31:25] | ??? | Unknown | *UNDEFINED*
4903  *
4904  */
4905 /*
4906  * Field : mpu_m0
4907  *
4908  * Security bit configuration for transactions from mpu_m0 to noc_probes_register.
4909  * When cleared (0), only Secure transactions are allowed. When set (1), both
4910  * Secure and Non-Secure transactions are allowed.
4911  *
4912  * Field Access Macros:
4913  *
4914  */
4915 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0 register field. */
4916 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_LSB 0
4917 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0 register field. */
4918 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_MSB 0
4919 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0 register field. */
4920 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_WIDTH 1
4921 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0 register field value. */
4922 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_SET_MSK 0x00000001
4923 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0 register field value. */
4924 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_CLR_MSK 0xfffffffe
4925 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0 register field. */
4926 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_RESET 0x0
4927 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0 field value from a register. */
4928 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4929 /* Produces a ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0 register field value suitable for setting the register. */
4930 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4931 
4932 /*
4933  * Field : fpga2soc
4934  *
4935  * Security bit configuration for transactions from fpga2soc to
4936  * noc_probes_register. When cleared (0), only Secure transactions are allowed.
4937  * When set (1), both Secure and Non-Secure transactions are allowed.
4938  *
4939  * Field Access Macros:
4940  *
4941  */
4942 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H register field. */
4943 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_LSB 16
4944 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H register field. */
4945 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_MSB 16
4946 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H register field. */
4947 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_WIDTH 1
4948 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H register field value. */
4949 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_SET_MSK 0x00010000
4950 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H register field value. */
4951 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_CLR_MSK 0xfffeffff
4952 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H register field. */
4953 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_RESET 0x0
4954 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H field value from a register. */
4955 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_GET(value) (((value) & 0x00010000) >> 16)
4956 /* Produces a ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H register field value suitable for setting the register. */
4957 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_SET(value) (((value) << 16) & 0x00010000)
4958 
4959 /*
4960  * Field : ahb_ap
4961  *
4962  * Security bit configuration for transactions from ahb_ap to noc_probes_register.
4963  * When cleared (0), only Secure transactions are allowed. When set (1), both
4964  * Secure and Non-Secure transactions are allowed.
4965  *
4966  * Field Access Macros:
4967  *
4968  */
4969 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP register field. */
4970 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_LSB 24
4971 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP register field. */
4972 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_MSB 24
4973 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP register field. */
4974 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_WIDTH 1
4975 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP register field value. */
4976 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_SET_MSK 0x01000000
4977 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP register field value. */
4978 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_CLR_MSK 0xfeffffff
4979 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP register field. */
4980 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_RESET 0x0
4981 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP field value from a register. */
4982 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4983 /* Produces a ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP register field value suitable for setting the register. */
4984 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4985 
4986 #ifndef __ASSEMBLY__
4987 /*
4988  * WARNING: The C register and register group struct declarations are provided for
4989  * convenience and illustrative purposes. They should, however, be used with
4990  * caution as the C language standard provides no guarantees about the alignment or
4991  * atomicity of device memory accesses. The recommended practice for writing
4992  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4993  * alt_write_word() functions.
4994  *
4995  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR.
4996  */
4997 struct ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_s
4998 {
4999  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0 */
5000  uint32_t : 15; /* *UNDEFINED* */
5001  uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H */
5002  uint32_t : 7; /* *UNDEFINED* */
5003  uint32_t ahb_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP */
5004  uint32_t : 7; /* *UNDEFINED* */
5005 };
5006 
5007 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR. */
5008 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_s ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_t;
5009 #endif /* __ASSEMBLY__ */
5010 
5011 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR register. */
5012 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_RESET 0x00000000
5013 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR register from the beginning of the component. */
5014 #define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_OFST 0x94
5015 
5016 #ifndef __ASSEMBLY__
5017 /*
5018  * WARNING: The C register and register group struct declarations are provided for
5019  * convenience and illustrative purposes. They should, however, be used with
5020  * caution as the C language standard provides no guarantees about the alignment or
5021  * atomicity of device memory accesses. The recommended practice for writing
5022  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5023  * alt_write_word() functions.
5024  *
5025  * The struct declaration for register group ALT_NOC_FW_L4_SYS_SCR.
5026  */
5027 struct ALT_NOC_FW_L4_SYS_SCR_s
5028 {
5029  ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_t can0_ecc; /* ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC */
5030  ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_t can1_ecc; /* ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC */
5031  ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_t dma_ecc; /* ALT_NOC_FW_L4_SYS_SCR_DMA_ECC */
5032  ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_t emac0rx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC */
5033  ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_t emac0tx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC */
5034  ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_t emac1rx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC */
5035  ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_t emac1tx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC */
5036  ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_t emac2rx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC */
5037  ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_t emac2tx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC */
5038  ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_t emac3rx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC */
5039  ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_t emac3tx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC */
5040  ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_t nand_ecc; /* ALT_NOC_FW_L4_SYS_SCR_NAND_ECC */
5041  ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_t nand_read_ecc; /* ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC */
5042  ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_t nand_write_ecc; /* ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC */
5043  ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_t onchipram_ecc; /* ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC */
5044  ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_t qspi_ecc; /* ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC */
5045  ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_t sdmmc_ecc; /* ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC */
5046  ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_t usb0_ecc; /* ALT_NOC_FW_L4_SYS_SCR_USB0_ECC */
5047  ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_t usb1_ecc; /* ALT_NOC_FW_L4_SYS_SCR_USB1_ECC */
5048  ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_t clock_manager; /* ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER */
5049  ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_t fpga_manager_register; /* ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG */
5050  ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_t pin_mux_register; /* ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG */
5051  ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_t reset_manager; /* ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER */
5052  ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_t system_manager; /* ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER */
5053  ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_t osc0_timer; /* ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR */
5054  ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_t osc1_timer; /* ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR */
5055  ALT_NOC_FW_L4_SYS_SCR_WD0_t watchdog0; /* ALT_NOC_FW_L4_SYS_SCR_WD0 */
5056  ALT_NOC_FW_L4_SYS_SCR_WD1_t watchdog1; /* ALT_NOC_FW_L4_SYS_SCR_WD1 */
5057  ALT_NOC_FW_L4_SYS_SCR_DAP_t dap; /* ALT_NOC_FW_L4_SYS_SCR_DAP */
5058  ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_t fpga_manager_streaming; /* ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING */
5059  ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_t security_manager_streaming; /* ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING */
5060  ALT_NOC_FW_L4_SYS_SCR_HMC_REG_t hmc_register; /* ALT_NOC_FW_L4_SYS_SCR_HMC_REG */
5061  ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_t hmc_adaptor_register; /* ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG */
5062  ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_t l3_interconnect_register; /* ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG */
5063  ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_t ddr_scheduler_register; /* ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG */
5064  ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_t l4_interconnect_firewall_csr; /* ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR */
5065  ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_t l4_interconnect_probes_csr; /* ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR */
5066  ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_t l4_qos_csr; /* ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR */
5067  volatile uint32_t _pad_0x98_0x100[26]; /* *UNDEFINED* */
5068 };
5069 
5070 /* The typedef declaration for register group ALT_NOC_FW_L4_SYS_SCR. */
5071 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_s ALT_NOC_FW_L4_SYS_SCR_t;
5072 /* The struct declaration for the raw register contents of register group ALT_NOC_FW_L4_SYS_SCR. */
5073 struct ALT_NOC_FW_L4_SYS_SCR_raw_s
5074 {
5075  volatile uint32_t can0_ecc; /* ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC */
5076  volatile uint32_t can1_ecc; /* ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC */
5077  volatile uint32_t dma_ecc; /* ALT_NOC_FW_L4_SYS_SCR_DMA_ECC */
5078  volatile uint32_t emac0rx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC */
5079  volatile uint32_t emac0tx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC */
5080  volatile uint32_t emac1rx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC */
5081  volatile uint32_t emac1tx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC */
5082  volatile uint32_t emac2rx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC */
5083  volatile uint32_t emac2tx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC */
5084  volatile uint32_t emac3rx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC */
5085  volatile uint32_t emac3tx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC */
5086  volatile uint32_t nand_ecc; /* ALT_NOC_FW_L4_SYS_SCR_NAND_ECC */
5087  volatile uint32_t nand_read_ecc; /* ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC */
5088  volatile uint32_t nand_write_ecc; /* ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC */
5089  volatile uint32_t onchipram_ecc; /* ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC */
5090  volatile uint32_t qspi_ecc; /* ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC */
5091  volatile uint32_t sdmmc_ecc; /* ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC */
5092  volatile uint32_t usb0_ecc; /* ALT_NOC_FW_L4_SYS_SCR_USB0_ECC */
5093  volatile uint32_t usb1_ecc; /* ALT_NOC_FW_L4_SYS_SCR_USB1_ECC */
5094  volatile uint32_t clock_manager; /* ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER */
5095  volatile uint32_t fpga_manager_register; /* ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG */
5096  volatile uint32_t pin_mux_register; /* ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG */
5097  volatile uint32_t reset_manager; /* ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER */
5098  volatile uint32_t system_manager; /* ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER */
5099  volatile uint32_t osc0_timer; /* ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR */
5100  volatile uint32_t osc1_timer; /* ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR */
5101  volatile uint32_t watchdog0; /* ALT_NOC_FW_L4_SYS_SCR_WD0 */
5102  volatile uint32_t watchdog1; /* ALT_NOC_FW_L4_SYS_SCR_WD1 */
5103  volatile uint32_t dap; /* ALT_NOC_FW_L4_SYS_SCR_DAP */
5104  volatile uint32_t fpga_manager_streaming; /* ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING */
5105  volatile uint32_t security_manager_streaming; /* ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING */
5106  volatile uint32_t hmc_register; /* ALT_NOC_FW_L4_SYS_SCR_HMC_REG */
5107  volatile uint32_t hmc_adaptor_register; /* ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG */
5108  volatile uint32_t l3_interconnect_register; /* ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG */
5109  volatile uint32_t ddr_scheduler_register; /* ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG */
5110  volatile uint32_t l4_interconnect_firewall_csr; /* ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR */
5111  volatile uint32_t l4_interconnect_probes_csr; /* ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR */
5112  volatile uint32_t l4_qos_csr; /* ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR */
5113  uint32_t _pad_0x98_0x100[26]; /* *UNDEFINED* */
5114 };
5115 
5116 /* The typedef declaration for the raw register contents of register group ALT_NOC_FW_L4_SYS_SCR. */
5117 typedef volatile struct ALT_NOC_FW_L4_SYS_SCR_raw_s ALT_NOC_FW_L4_SYS_SCR_raw_t;
5118 #endif /* __ASSEMBLY__ */
5119 
5120 
5121 #ifdef __cplusplus
5122 }
5123 #endif /* __cplusplus */
5124 #endif /* __ALT_SOCAL_NOC_FW_L4_SYS_SCR_H__ */
5125