35 #ifndef __ALT_SOCAL_NOC_MPU_M1TODDRRESP_MAIN_RATE_H__
36 #define __ALT_SOCAL_NOC_MPU_M1TODDRRESP_MAIN_RATE_H__
72 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID_LSB 0
74 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID_MSB 7
76 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID_WIDTH 8
78 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID_SET_MSK 0x000000ff
80 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID_CLR_MSK 0xffffff00
82 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID_RESET 0x1
84 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID_GET(value) (((value) & 0x000000ff) >> 0)
86 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID_SET(value) (((value) << 0) & 0x000000ff)
97 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM_LSB 8
99 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM_MSB 31
101 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM_WIDTH 24
103 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM_SET_MSK 0xffffff00
105 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM_CLR_MSK 0x000000ff
107 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM_RESET 0xc8a2b3
109 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
111 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
124 struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_s
126 const uint32_t CORETYPEID : 8;
127 const uint32_t CORECHECKSUM : 24;
131 typedef volatile struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_s ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_t;
135 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_RESET 0xc8a2b301
137 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_OFST 0x0
159 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID_LSB 0
161 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID_MSB 7
163 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID_WIDTH 8
165 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID_SET_MSK 0x000000ff
167 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID_CLR_MSK 0xffffff00
169 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID_RESET 0x0
171 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID_GET(value) (((value) & 0x000000ff) >> 0)
173 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID_SET(value) (((value) << 0) & 0x000000ff)
185 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID_LSB 8
187 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID_MSB 31
189 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID_WIDTH 24
191 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID_SET_MSK 0xffffff00
193 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID_CLR_MSK 0x000000ff
195 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID_RESET 0x129ff
197 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
199 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
212 struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_s
214 const uint32_t USERID : 8;
215 const uint32_t FLEXNOCID : 24;
219 typedef volatile struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_s ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_t;
223 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_RESET 0x0129ff00
225 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_OFST 0x4
255 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE_LSB 0
257 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE_MSB 9
259 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE_WIDTH 10
261 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE_SET_MSK 0x000003ff
263 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE_CLR_MSK 0xfffffc00
265 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE_RESET 0x0
267 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE_GET(value) (((value) & 0x000003ff) >> 0)
269 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE_SET(value) (((value) << 0) & 0x000003ff)
282 struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_s
289 typedef volatile struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_s ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_t;
293 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RESET 0x00000000
295 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_OFST 0x8
321 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS_LSB 0
323 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS_MSB 0
325 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS_WIDTH 1
327 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS_SET_MSK 0x00000001
329 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS_CLR_MSK 0xfffffffe
331 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS_RESET 0x0
333 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS_GET(value) (((value) & 0x00000001) >> 0)
335 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS_SET(value) (((value) << 0) & 0x00000001)
348 struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_s
355 typedef volatile struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_s ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_t;
359 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_RESET 0x00000000
361 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_OFST 0xc
374 struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_s
376 ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_t MPU_M1toDDRResp_main_RateAdapter_Id_CoreId;
377 ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_t MPU_M1toDDRResp_main_RateAdapter_Id_RevisionId;
378 ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_t MPU_M1toDDRResp_main_RateAdapter_Rate;
379 ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_t MPU_M1toDDRResp_main_RateAdapter_Bypass;
380 volatile uint32_t _pad_0x10_0x80[28];
384 typedef volatile struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_s ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_t;
386 struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_raw_s
388 volatile uint32_t MPU_M1toDDRResp_main_RateAdapter_Id_CoreId;
389 volatile uint32_t MPU_M1toDDRResp_main_RateAdapter_Id_RevisionId;
390 volatile uint32_t MPU_M1toDDRResp_main_RateAdapter_Rate;
391 volatile uint32_t MPU_M1toDDRResp_main_RateAdapter_Bypass;
392 uint32_t _pad_0x10_0x80[28];
396 typedef volatile struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_raw_s ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_raw_t;