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alt_ethernet.h
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1 /******************************************************************************
2  *
3  * Copyright 2017 Altera Corporation. All Rights Reserved.
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6  * modification, are permitted provided that the following conditions are met:
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37 #ifndef __ALT_ETHERNET_H__
38 #define __ALT_ETHERNET_H__
39 
40 #include "hwlib.h"
41 #include "socal/hps.h"
42 #include "socal/alt_emac.h"
43 #include "alt_interrupt.h"
44 
45 #ifdef __cplusplus
46 extern "C"
47 {
48 #endif /* __cplusplus */
49 
50 #define ETH_RESET_DELAY ((uint32_t)0x000FFFFF)
51 #define NUMBER_OF_TX_DESCRIPTORS 32
52 #define NUMBER_OF_RX_DESCRIPTORS 32
53 #define ETH_BUFFER_SIZE 1536
54 
55 typedef enum
56 {
57  ALT_ETH_RESET = 0,
58  ALT_ETH_SET = 1
59 } alt_eth_set_reset_state_t;
60 
61 typedef enum {
62  ALT_ETH_DISABLE = 0,
63  ALT_ETH_ENABLE = 1
64 } alt_eth_enable_disable_state_t;
65 
66 #ifdef SIMICS
67 #define USE_ALTERNATE_DESCRIPTOR_SIZE
68 #else
69 /* Uncomment the line below when using time stamping and/or IPv4 checksum offload */
70 /*#define USE_ALTERNATE_DESCRIPTOR_SIZE*/
71 #endif
72 
73 /* NOTE: this must be defined for A10 and S10 */
74 #define USE_ENHANCED_DMA_DESCRIPTORS
75 
84 typedef struct
85 {
86  uint32_t status;
88  uint32_t buffer1_addr;
90 #ifdef USE_ALTERNATE_DESCRIPTOR_SIZE
91  uint32_t extended_status; /* Extended status for PTP receive desc */
92  uint32_t reserved1; /* Reserved */
93  uint32_t time_stamp_low; /* Time Stamp Low value for transmit and receive */
94  uint32_t time_stamp_high; /* Time Stamp High value for transmit and receive */
95 #endif
97 
98 #ifdef USE_ENHANCED_DMA_DESCRIPTORS
99 
100 /* Ethernet DMA descriptors registers bits definition */
119 #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000)
120 #define ETH_DMATXDESC_IC ((uint32_t)0x40000000)
121 #define ETH_DMATXDESC_LS ((uint32_t)0x20000000)
122 #define ETH_DMATXDESC_FS ((uint32_t)0x10000000)
123 #define ETH_DMATXDESC_DC ((uint32_t)0x08000000)
124 #define ETH_DMATXDESC_DP ((uint32_t)0x04000000)
125 #define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000)
126 #define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000)
127 #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000)
128 #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000)
129 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000)
130 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000)
131 #define ETH_DMATXDESC_TER ((uint32_t)0x00200000)
132 #define ETH_DMATXDESC_TCH ((uint32_t)0x00100000)
133 #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000)
134 #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000)
135 #define ETH_DMATXDESC_ES ((uint32_t)0x00008000)
136 #define ETH_DMATXDESC_JT ((uint32_t)0x00004000)
137 #define ETH_DMATXDESC_FF ((uint32_t)0x00002000)
138 #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000)
139 #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800)
140 #define ETH_DMATXDESC_NC ((uint32_t)0x00000400)
141 #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200)
142 #define ETH_DMATXDESC_EC ((uint32_t)0x00000100)
143 #define ETH_DMATXDESC_VF ((uint32_t)0x00000080)
144 #define ETH_DMATXDESC_CC ((uint32_t)0x00000078)
145 #define ETH_DMATXDESC_ED ((uint32_t)0x00000004)
146 #define ETH_DMATXDESC_UF ((uint32_t)0x00000002)
147 #define ETH_DMATXDESC_DB ((uint32_t)0x00000001)
150 /* Bit definition of TDES1 register */
151 #define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000)
152 #define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF)
154 /* Bit definition of TDES2 register */
155 #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF)
157 /* Bit definition of TDES3 register */
158 #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF)
160  /*---------------------------------------------------------------------------------------------
161  TDES6 | Transmit Time Stamp Low [31:0] |
162  -----------------------------------------------------------------------------------------------
163  TDES7 | Transmit Time Stamp High [31:0] |
164  ----------------------------------------------------------------------------------------------*/
165 
166 /* Bit definition of TDES6 register */
167  #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
168 
169 /* Bit definition of TDES7 register */
170  #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
171 
185 /* Bit definition of RDES0 register: DMA Rx descriptor status register */
186 #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000)
187 #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000)
188 #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000)
189 #define ETH_DMARXDESC_ES ((uint32_t)0x00008000)
190 #define ETH_DMARXDESC_DE ((uint32_t)0x00004000)
191 #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000)
192 #define ETH_DMARXDESC_LE ((uint32_t)0x00001000)
193 #define ETH_DMARXDESC_OE ((uint32_t)0x00000800)
194 #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400)
195 #define ETH_DMARXDESC_FS ((uint32_t)0x00000200)
196 #define ETH_DMARXDESC_LS ((uint32_t)0x00000100)
197 #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080)
198 #define ETH_DMARXDESC_LC ((uint32_t)0x00000040)
199 #define ETH_DMARXDESC_FT ((uint32_t)0x00000020)
200 #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010)
201 #define ETH_DMARXDESC_RE ((uint32_t)0x00000008)
202 #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004)
203 #define ETH_DMARXDESC_CE ((uint32_t)0x00000002)
204 #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001)
206 /* Bit definition of RDES1 register */
207 #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000)
208 #define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000)
209 #define ETH_DMARXDESC_RER ((uint32_t)0x00008000)
210 #define ETH_DMARXDESC_RCH ((uint32_t)0x00004000)
211 #define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF)
213 /* Bit definition of RDES2 register */
214 #define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF)
216 /* Bit definition of RDES3 register */
217 #define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF)
219 /*---------------------------------------------------------------------------------------------------------------------
220  RDES4 | Reserved[31:15] | Extended Status [14:0] |
221  ---------------------------------------------------------------------------------------------------------------------
222  RDES5 | Reserved[31:0] |
223  ---------------------------------------------------------------------------------------------------------------------
224  RDES6 | Receive Time Stamp Low [31:0] |
225  ---------------------------------------------------------------------------------------------------------------------
226  RDES7 | Receive Time Stamp High [31:0] |
227  --------------------------------------------------------------------------------------------------------------------*/
228 
229 /* Bit definition of RDES4 register */
230 #define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
231 #define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
232 #define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
233 #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
234 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
235 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
236 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
237 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
238 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_MANAGE ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
239 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
240 #define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
241 #define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
242 #define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
243 #define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
244 #define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
245 #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
246 #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
247 #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
248 
249 /* Bit definition of RDES6 register */
250 #define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
251 
252 /* Bit definition of RDES7 register */
253 #define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
254 
255 
256 #else
259 /* Ethernet DMA descriptors registers bits definition */
260 
275 /* Bit definition of TDES0 register: DMA Tx descriptor status register */
276 #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000)
277 #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000)
278 #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000)
279 #define ETH_DMATXDESC_ES ((uint32_t)0x00008000)
280 #define ETH_DMATXDESC_JT ((uint32_t)0x00004000)
281 #define ETH_DMATXDESC_FF ((uint32_t)0x00002000)
282 #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000)
283 #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800)
284 #define ETH_DMATXDESC_NC ((uint32_t)0x00000400)
285 #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200)
286 #define ETH_DMATXDESC_EC ((uint32_t)0x00000100)
287 #define ETH_DMATXDESC_VF ((uint32_t)0x00000080)
288 #define ETH_DMATXDESC_CC ((uint32_t)0x00000078)
289 #define ETH_DMATXDESC_ED ((uint32_t)0x00000004)
290 #define ETH_DMATXDESC_UF ((uint32_t)0x00000002)
291 #define ETH_DMATXDESC_DB ((uint32_t)0x00000001)
293 /* Bit definition of TDES1 register: DMA Tx descriptor control-size register */
294 #define ETH_DMATXDESC_IC ((uint32_t)0x80000000)
295 #define ETH_DMATXDESC_LS ((uint32_t)0x40000000)
296 #define ETH_DMATXDESC_FS ((uint32_t)0x20000000)
297 #define ETH_DMATXDESC_CIC ((uint32_t)0x18000000)
298 #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000)
299 #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x08000000)
300 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x10000000)
301 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x18000000)
302 #define ETH_DMATXDESC_DC ((uint32_t)0x04000000)
303 #define ETH_DMATXDESC_TER ((uint32_t)0x02000000)
304 #define ETH_DMATXDESC_TCH ((uint32_t)0x01000000)
305 #define ETH_DMATXDESC_DP ((uint32_t)0x00800000)
306 #define ETH_DMATXDESC_TTSE ((uint32_t)0x00400000)
307 #define ETH_DMATXDESC_TBS2 ((uint32_t)0x003FF800)
308 #define ETH_DMATXDESC_TBS1 ((uint32_t)0x000007FF)
310 /* Bit definition of TDES2 register */
311 #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF)
313 /* Bit definition of TDES3 register */
314 #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF)
329 /* Bit definition of RDES0 register: DMA Rx descriptor status register */
330 #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000)
331 #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000)
332 #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000)
333 #define ETH_DMARXDESC_ES ((uint32_t)0x00008000)
334 #define ETH_DMARXDESC_DE ((uint32_t)0x00004000)
335 #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000)
336 #define ETH_DMARXDESC_LE ((uint32_t)0x00001000)
337 #define ETH_DMARXDESC_OE ((uint32_t)0x00000800)
338 #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400)
339 #define ETH_DMARXDESC_FS ((uint32_t)0x00000200)
340 #define ETH_DMARXDESC_LS ((uint32_t)0x00000100)
341 #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080)
342 #define ETH_DMARXDESC_LC ((uint32_t)0x00000040)
343 #define ETH_DMARXDESC_FT ((uint32_t)0x00000020)
344 #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010)
345 #define ETH_DMARXDESC_RE ((uint32_t)0x00000008)
346 #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004)
347 #define ETH_DMARXDESC_CE ((uint32_t)0x00000002)
348 #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001)
350 /* Bit definition of RDES1 register */
351 #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000)
352 #define ETH_DMARXDESC_RER ((uint32_t)0x02000000)
353 #define ETH_DMARXDESC_RCH ((uint32_t)0x01000000)
354 #define ETH_DMARXDESC_RBS2 ((uint32_t)0x003FF800)
355 #define ETH_DMARXDESC_RBS1 ((uint32_t)0x000007FF)
357 /* Bit definition of RDES2 register */
358 #define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF)
360 /* Bit definition of RDES3 register */
361 #define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF)
364 #endif /*#ifdef USE_ENHANCED_DMA_DESCRIPTORS*/
365 
366 
367 #ifdef USE_ENHANCED_DMA_DESCRIPTORS
368 
369  /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
370  #define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16
371 
372  /* ETHERNET DMA Rx descriptors Frame Length Shift */
373  #define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16
374 
375  /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
376  #define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16
377 
378 #else
379 
380  /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
381  #define ETH_DMATXDESC_BUFFER2_SIZESHIFT 11
382 
383  /* ETHERNET DMA Rx descriptors Frame Length Shift */
384  #define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16
385 
386  /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
387  #define ETH_DMARXDESC_BUFFER2_SIZESHIFT 11
388 
389 #endif
390 
391 /******************************************************************************/
403 {
404  uint32_t instance; /* This specifies the EMAC to use */
405  uint32_t tx_current_desc_number;
406  uint32_t rx_current_desc_number;
407  uint32_t rx_processed_desc_number;
408 
409  ALT_INT_INTERRUPT_t irqnum;
410  uint32_t interrupt_mask;
411  uint32_t rxints;
412  uint32_t txints;
413 
414  /* Ethernet packet buffers */
415  uint8_t rx_buf[ETH_BUFFER_SIZE * NUMBER_OF_RX_DESCRIPTORS];
416  uint8_t tx_buf[ETH_BUFFER_SIZE * NUMBER_OF_TX_DESCRIPTORS];
417 
418  /* Descriptor rings */
419  alt_eth_dma_desc_t tx_desc_ring[NUMBER_OF_TX_DESCRIPTORS];
420  alt_eth_dma_desc_t rx_desc_ring[NUMBER_OF_RX_DESCRIPTORS];
422 
423 
424 /******************************************************************************/
432 void alt_eth_delay(volatile uint32_t delay);
433 
434 /******************************************************************************/
442 void alt_eth_reset_mac(uint32_t instance);
443 
444 /******************************************************************************/
453 
454 /******************************************************************************/
463 
464 /******************************************************************************/
477 ALT_STATUS_CODE alt_eth_irq_init(alt_eth_emac_instance_t * emac, alt_int_callback_t callback);
478 
479 /******************************************************************************/
495 void alt_eth_irq_callback(uint32_t icciar, void * context);
496 
497 /******************************************************************************/
508 ALT_STATUS_CODE alt_eth_software_reset(uint32_t instance);
509 
510 /******************************************************************************/
519 void alt_eth_start(uint32_t instance);
520 
521 /******************************************************************************/
530 void alt_eth_stop(uint32_t instance);
531 
532 /******************************************************************************/
551 ALT_STATUS_CODE alt_eth_dma_mac_config(alt_eth_emac_instance_t * emac);
552 
553 /******************************************************************************/
572 ALT_STATUS_CODE alt_eth_send_packet(uint8_t * pkt, uint32_t len, uint32_t first, uint32_t last, alt_eth_emac_instance_t * emac);
573 
574 /******************************************************************************/
591 ALT_STATUS_CODE alt_eth_get_packet(uint8_t * pkt, uint32_t * len, alt_eth_emac_instance_t * emac);
592 
593 /******************************************************************************/
604 void alt_eth_mac_set_tx_state(alt_eth_enable_disable_state_t new_state, uint32_t instance);
605 
606 /******************************************************************************/
617 void alt_eth_mac_set_rx_state(alt_eth_enable_disable_state_t new_state, uint32_t instance);
618 
619 /******************************************************************************/
632 void alt_eth_mac_set_bpa_state(alt_eth_enable_disable_state_t new_state, uint32_t instance);
633 
634 /******************************************************************************/
646 alt_eth_enable_disable_state_t alt_eth_mac_get_bpa_state(uint32_t instance);
647 
648 /******************************************************************************/
661 void alt_eth_mac_set_irq_reg(uint32_t mac_irq_mask, alt_eth_enable_disable_state_t new_state, uint32_t instance);
662 
663 
664 /******************************************************************************/
676 alt_eth_set_reset_state_t alt_eth_mac_get_mii_link_state(uint32_t instance);
677 
678 /******************************************************************************/
692 alt_eth_set_reset_state_t alt_eth_mac_check_status_reg(uint32_t mac_bit_mask, uint32_t instance);
693 
694 /******************************************************************************/
705 uint32_t alt_eth_mac_get_irq_status_reg(uint32_t instance);
706 
707 /******************************************************************************/
717 void alt_eth_mac_pause_ctrl_frame(uint32_t instance);
718 
719 /******************************************************************************/
731 void alt_eth_mac_set_mac_addr(uint8_t *address, uint32_t instance);
732 
733 /******************************************************************************/
745 void alt_eth_mac_get_mac_addr(uint8_t *address, uint32_t instance);
746 
747 /******************************************************************************/
756 void alt_eth_mac_check_mii_link_status(uint32_t instance);
757 
758 /******************************************************************************/
769 uint32_t alt_eth_dma_get_status_reg(uint32_t instance);
770 
771 /******************************************************************************/
785 alt_eth_set_reset_state_t alt_eth_dma_check_status_reg(uint32_t dma_bit_mask, uint32_t instance);
786 
787 /******************************************************************************/
801 void alt_eth_dma_clear_status_bits(uint32_t dma_bit_mask, uint32_t instance);
802 
803 /******************************************************************************/
813 void alt_eth_dma_flush_tx_fifo(uint32_t instance);
814 
815 /******************************************************************************/
826 alt_eth_set_reset_state_t alt_eth_dma_get_tx_fifo_flush_state(uint32_t instance);
827 
828 /******************************************************************************/
839 void alt_eth_dma_set_tx_state(alt_eth_enable_disable_state_t new_state, uint32_t instance);
840 
841 /******************************************************************************/
852 void alt_eth_dma_set_rx_state(alt_eth_enable_disable_state_t new_state, uint32_t instance);
853 
854 /******************************************************************************/
867 void alt_eth_dma_set_irq_reg(uint32_t dma_irq_mask, alt_eth_enable_disable_state_t new_state, uint32_t instance);
868 
869 /******************************************************************************/
881 alt_eth_set_reset_state_t alt_eth_dma_check_overflow_counter_reg(uint32_t dma_overflow_mask, uint32_t instance);
882 
883 /******************************************************************************/
892 uint32_t alt_eth_dma_get_curr_tx_desc_addr(uint32_t instance);
893 
894 /******************************************************************************/
903 uint32_t alt_eth_dma_get_curr_rx_desc_addr(uint32_t instance);
904 
905 /******************************************************************************/
914 uint32_t alt_eth_dma_get_curr_tx_buff_addr(uint32_t instance);
915 
916 /******************************************************************************/
925 uint32_t alt_eth_dma_get_curr_rx_buff_addr(uint32_t instance);
926 
927 /******************************************************************************/
936 void alt_eth_dma_set_tx_desc_addr(uint32_t tx_desc_list_addr, uint32_t instance);
937 
938 /******************************************************************************/
947 void alt_eth_dma_set_rx_desc_addr(uint32_t rx_desc_list_addr, uint32_t instance);
948 
949 /******************************************************************************/
957 void alt_eth_dma_resume_dma_tx(uint32_t instance);
958 
959 /******************************************************************************/
967 void alt_eth_dma_resume_dma_rx(uint32_t instance);
968 
969 
971 /* PHY Specific Function Prototypes. */
974 /******************************************************************************/
991 ALT_STATUS_CODE alt_eth_phy_config(uint32_t instance);
992 
993 /******************************************************************************/
1009 ALT_STATUS_CODE alt_eth_phy_reset(uint32_t instance);
1010 
1011 /******************************************************************************/
1034 ALT_STATUS_CODE alt_eth_phy_get_duplex_and_speed(uint32_t * phy_duplex_status, uint32_t * phy_speed, uint32_t instance);
1035 
1036 
1037 #ifdef __cplusplus
1038 }
1039 #endif /* __cplusplus */
1040 
1041 #endif /* __ALT_ETHERNET_H__ */