Altera SoCAL  20.1
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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alt_spis.h
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32 
33 /* Altera - ALT_SPIS */
34 
35 #ifndef __ALTERA_ALT_SPIS_H__
36 #define __ALTERA_ALT_SPIS_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
43 /*
44  * Component : SPI Slave Module - ALT_SPIS
45  * SPI Slave Module
46  *
47  * Registers in the SPI Slave module
48  *
49  */
50 /*
51  * Register : Control Register 0 - ctrlr0
52  *
53  * This register controls the serial data transfer. It is impossible to write to
54  * this register when the SPI Slave is enabled. The SPI Slave is enabled and
55  * disabled by writing to the SPIENR register.
56  *
57  * Register Layout
58  *
59  * Bits | Access | Reset | Description
60  * :--------|:-------|:------|:----------------------
61  * [3:0] | RW | 0x7 | Data Frame Size
62  * [5:4] | RW | 0x0 | Frame Format
63  * [6] | RW | 0x0 | Serial Clock Phase
64  * [7] | RW | 0x0 | Serial Clock Polarity
65  * [9:8] | RW | 0x0 | Transfer Mode
66  * [10] | RW | 0x0 | Slave Output Enable
67  * [11] | RW | 0x0 | Shift Register Loop
68  * [15:12] | RW | 0x0 | Control Frame Size
69  * [31:16] | ??? | 0x0 | *UNDEFINED*
70  *
71  */
72 /*
73  * Field : Data Frame Size - dfs
74  *
75  * Selects the data frame length. When the data frame size is programmed to be less
76  * than 16 bits, the receive data are automatically right-justified by the receive
77  * logic, with the upper bits of the receiver FIFO zero-padded. You must right-
78  * justify transmit data before writing into the transmit FIFO. The transmit logic
79  * ignores the upper unused bits when transmitting the data.
80  *
81  * Field Enumeration Values:
82  *
83  * Enum | Value | Description
84  * :--------------------------------|:------|:----------------------------
85  * ALT_SPIS_CTLR0_DFS_E_WIDTH4BIT | 0x3 | 4-bit serial data transfer
86  * ALT_SPIS_CTLR0_DFS_E_WIDTH5BIT | 0x4 | 5-bit serial data transfer
87  * ALT_SPIS_CTLR0_DFS_E_WIDTH6BIT | 0x5 | 6-bit serial data transfer
88  * ALT_SPIS_CTLR0_DFS_E_WIDTH7BIT | 0x6 | 7-bit serial data transfer
89  * ALT_SPIS_CTLR0_DFS_E_WIDTH8BIT | 0x7 | 8-bit serial data transfer
90  * ALT_SPIS_CTLR0_DFS_E_WIDTH9BIT | 0x8 | 9-bit serial data transfer
91  * ALT_SPIS_CTLR0_DFS_E_WIDTH10BIT | 0x9 | 10-bit serial data transfer
92  *
93  * Field Access Macros:
94  *
95  */
96 /*
97  * Enumerated value for register field ALT_SPIS_CTLR0_DFS
98  *
99  * 4-bit serial data transfer
100  */
101 #define ALT_SPIS_CTLR0_DFS_E_WIDTH4BIT 0x3
102 /*
103  * Enumerated value for register field ALT_SPIS_CTLR0_DFS
104  *
105  * 5-bit serial data transfer
106  */
107 #define ALT_SPIS_CTLR0_DFS_E_WIDTH5BIT 0x4
108 /*
109  * Enumerated value for register field ALT_SPIS_CTLR0_DFS
110  *
111  * 6-bit serial data transfer
112  */
113 #define ALT_SPIS_CTLR0_DFS_E_WIDTH6BIT 0x5
114 /*
115  * Enumerated value for register field ALT_SPIS_CTLR0_DFS
116  *
117  * 7-bit serial data transfer
118  */
119 #define ALT_SPIS_CTLR0_DFS_E_WIDTH7BIT 0x6
120 /*
121  * Enumerated value for register field ALT_SPIS_CTLR0_DFS
122  *
123  * 8-bit serial data transfer
124  */
125 #define ALT_SPIS_CTLR0_DFS_E_WIDTH8BIT 0x7
126 /*
127  * Enumerated value for register field ALT_SPIS_CTLR0_DFS
128  *
129  * 9-bit serial data transfer
130  */
131 #define ALT_SPIS_CTLR0_DFS_E_WIDTH9BIT 0x8
132 /*
133  * Enumerated value for register field ALT_SPIS_CTLR0_DFS
134  *
135  * 10-bit serial data transfer
136  */
137 #define ALT_SPIS_CTLR0_DFS_E_WIDTH10BIT 0x9
138 
139 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_DFS register field. */
140 #define ALT_SPIS_CTLR0_DFS_LSB 0
141 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_DFS register field. */
142 #define ALT_SPIS_CTLR0_DFS_MSB 3
143 /* The width in bits of the ALT_SPIS_CTLR0_DFS register field. */
144 #define ALT_SPIS_CTLR0_DFS_WIDTH 4
145 /* The mask used to set the ALT_SPIS_CTLR0_DFS register field value. */
146 #define ALT_SPIS_CTLR0_DFS_SET_MSK 0x0000000f
147 /* The mask used to clear the ALT_SPIS_CTLR0_DFS register field value. */
148 #define ALT_SPIS_CTLR0_DFS_CLR_MSK 0xfffffff0
149 /* The reset value of the ALT_SPIS_CTLR0_DFS register field. */
150 #define ALT_SPIS_CTLR0_DFS_RESET 0x7
151 /* Extracts the ALT_SPIS_CTLR0_DFS field value from a register. */
152 #define ALT_SPIS_CTLR0_DFS_GET(value) (((value) & 0x0000000f) >> 0)
153 /* Produces a ALT_SPIS_CTLR0_DFS register field value suitable for setting the register. */
154 #define ALT_SPIS_CTLR0_DFS_SET(value) (((value) << 0) & 0x0000000f)
155 
156 /*
157  * Field : Frame Format - frf
158  *
159  * Selects which serial protocol transfers the data.
160  *
161  * Field Enumeration Values:
162  *
163  * Enum | Value | Description
164  * :----------------------------|:------|:------------------------
165  * ALT_SPIS_CTLR0_FRF_E_MOTSPI | 0x0 | Motorola SPI
166  * ALT_SPIS_CTLR0_FRF_E_TISSP | 0x1 | Texas instruments SSP
167  * ALT_SPIS_CTLR0_FRF_E_NATMW | 0x2 | National Semi Microwire
168  *
169  * Field Access Macros:
170  *
171  */
172 /*
173  * Enumerated value for register field ALT_SPIS_CTLR0_FRF
174  *
175  * Motorola SPI
176  */
177 #define ALT_SPIS_CTLR0_FRF_E_MOTSPI 0x0
178 /*
179  * Enumerated value for register field ALT_SPIS_CTLR0_FRF
180  *
181  * Texas instruments SSP
182  */
183 #define ALT_SPIS_CTLR0_FRF_E_TISSP 0x1
184 /*
185  * Enumerated value for register field ALT_SPIS_CTLR0_FRF
186  *
187  * National Semi Microwire
188  */
189 #define ALT_SPIS_CTLR0_FRF_E_NATMW 0x2
190 
191 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_FRF register field. */
192 #define ALT_SPIS_CTLR0_FRF_LSB 4
193 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_FRF register field. */
194 #define ALT_SPIS_CTLR0_FRF_MSB 5
195 /* The width in bits of the ALT_SPIS_CTLR0_FRF register field. */
196 #define ALT_SPIS_CTLR0_FRF_WIDTH 2
197 /* The mask used to set the ALT_SPIS_CTLR0_FRF register field value. */
198 #define ALT_SPIS_CTLR0_FRF_SET_MSK 0x00000030
199 /* The mask used to clear the ALT_SPIS_CTLR0_FRF register field value. */
200 #define ALT_SPIS_CTLR0_FRF_CLR_MSK 0xffffffcf
201 /* The reset value of the ALT_SPIS_CTLR0_FRF register field. */
202 #define ALT_SPIS_CTLR0_FRF_RESET 0x0
203 /* Extracts the ALT_SPIS_CTLR0_FRF field value from a register. */
204 #define ALT_SPIS_CTLR0_FRF_GET(value) (((value) & 0x00000030) >> 4)
205 /* Produces a ALT_SPIS_CTLR0_FRF register field value suitable for setting the register. */
206 #define ALT_SPIS_CTLR0_FRF_SET(value) (((value) << 4) & 0x00000030)
207 
208 /*
209  * Field : Serial Clock Phase - scph
210  *
211  * Valid when the frame format (FRF) is set to Motorola SPI. The serial clock phase
212  * selects the relationship of the serial clock with the slave select signal. When
213  * SCPH = 0, data are captured on the first edge of the serial clock. When SCPH =
214  * 1, the serial clock starts toggling one cycle after the slave select line is
215  * activated, and data are captured on the second edge of the serial clock.
216  *
217  * Field Enumeration Values:
218  *
219  * Enum | Value | Description
220  * :--------------------------------|:------|:---------------------------------------
221  * ALT_SPIS_CTLR0_SCPH_E_INACTLOW | 0x0 | Inactive state of serial clock is low
222  * ALT_SPIS_CTLR0_SCPH_E_INACTHIGH | 0x1 | Inactive state of serial clock is high
223  *
224  * Field Access Macros:
225  *
226  */
227 /*
228  * Enumerated value for register field ALT_SPIS_CTLR0_SCPH
229  *
230  * Inactive state of serial clock is low
231  */
232 #define ALT_SPIS_CTLR0_SCPH_E_INACTLOW 0x0
233 /*
234  * Enumerated value for register field ALT_SPIS_CTLR0_SCPH
235  *
236  * Inactive state of serial clock is high
237  */
238 #define ALT_SPIS_CTLR0_SCPH_E_INACTHIGH 0x1
239 
240 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_SCPH register field. */
241 #define ALT_SPIS_CTLR0_SCPH_LSB 6
242 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_SCPH register field. */
243 #define ALT_SPIS_CTLR0_SCPH_MSB 6
244 /* The width in bits of the ALT_SPIS_CTLR0_SCPH register field. */
245 #define ALT_SPIS_CTLR0_SCPH_WIDTH 1
246 /* The mask used to set the ALT_SPIS_CTLR0_SCPH register field value. */
247 #define ALT_SPIS_CTLR0_SCPH_SET_MSK 0x00000040
248 /* The mask used to clear the ALT_SPIS_CTLR0_SCPH register field value. */
249 #define ALT_SPIS_CTLR0_SCPH_CLR_MSK 0xffffffbf
250 /* The reset value of the ALT_SPIS_CTLR0_SCPH register field. */
251 #define ALT_SPIS_CTLR0_SCPH_RESET 0x0
252 /* Extracts the ALT_SPIS_CTLR0_SCPH field value from a register. */
253 #define ALT_SPIS_CTLR0_SCPH_GET(value) (((value) & 0x00000040) >> 6)
254 /* Produces a ALT_SPIS_CTLR0_SCPH register field value suitable for setting the register. */
255 #define ALT_SPIS_CTLR0_SCPH_SET(value) (((value) << 6) & 0x00000040)
256 
257 /*
258  * Field : Serial Clock Polarity - scpol
259  *
260  * Valid when the frame format (FRF) is set to Motorola SPI. Used to select the
261  * polarity of the inactive serial clock, which is held inactive when the spi
262  * master is not actively transferring data on the serial bus.
263  *
264  * Field Enumeration Values:
265  *
266  * Enum | Value | Description
267  * :--------------------------------|:------|:-------------------------------------------------
268  * ALT_SPIS_CTLR0_SCPOL_E_MIDBIT | 0x0 | Serial clock toggles in middle of first data bit
269  * ALT_SPIS_CTLR0_SCPOL_E_STARTBIT | 0x1 | Serial clock toggles at start of first data bit
270  *
271  * Field Access Macros:
272  *
273  */
274 /*
275  * Enumerated value for register field ALT_SPIS_CTLR0_SCPOL
276  *
277  * Serial clock toggles in middle of first data bit
278  */
279 #define ALT_SPIS_CTLR0_SCPOL_E_MIDBIT 0x0
280 /*
281  * Enumerated value for register field ALT_SPIS_CTLR0_SCPOL
282  *
283  * Serial clock toggles at start of first data bit
284  */
285 #define ALT_SPIS_CTLR0_SCPOL_E_STARTBIT 0x1
286 
287 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_SCPOL register field. */
288 #define ALT_SPIS_CTLR0_SCPOL_LSB 7
289 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_SCPOL register field. */
290 #define ALT_SPIS_CTLR0_SCPOL_MSB 7
291 /* The width in bits of the ALT_SPIS_CTLR0_SCPOL register field. */
292 #define ALT_SPIS_CTLR0_SCPOL_WIDTH 1
293 /* The mask used to set the ALT_SPIS_CTLR0_SCPOL register field value. */
294 #define ALT_SPIS_CTLR0_SCPOL_SET_MSK 0x00000080
295 /* The mask used to clear the ALT_SPIS_CTLR0_SCPOL register field value. */
296 #define ALT_SPIS_CTLR0_SCPOL_CLR_MSK 0xffffff7f
297 /* The reset value of the ALT_SPIS_CTLR0_SCPOL register field. */
298 #define ALT_SPIS_CTLR0_SCPOL_RESET 0x0
299 /* Extracts the ALT_SPIS_CTLR0_SCPOL field value from a register. */
300 #define ALT_SPIS_CTLR0_SCPOL_GET(value) (((value) & 0x00000080) >> 7)
301 /* Produces a ALT_SPIS_CTLR0_SCPOL register field value suitable for setting the register. */
302 #define ALT_SPIS_CTLR0_SCPOL_SET(value) (((value) << 7) & 0x00000080)
303 
304 /*
305  * Field : Transfer Mode - tmod
306  *
307  * Selects the mode of transfer for serial communication. This field does not
308  * affect the transfer duplicity. Only indicates whether the receive or transmit
309  * data are valid. In transmit-only mode, data received from the external device is
310  * not valid and is not stored in the receive FIFO memory; it is overwritten on the
311  * next transfer. In receive-only mode, transmitted data are not valid. After the
312  * first write to the transmit FIFO, the same word is retransmitted for the
313  * duration of the transfer. In transmit-and-receive mode, both transmit and
314  * receive data are valid. The transfer continues until the transmit FIFO is empty.
315  * Data received from the external device are stored into the receive FIFO memory
316  *
317  * Field Enumeration Values:
318  *
319  * Enum | Value | Description
320  * :-----------------------------|:------|:-----------------------
321  * ALT_SPIS_CTLR0_TMOD_E_TXRX | 0x0 | Transmit & and Receive
322  * ALT_SPIS_CTLR0_TMOD_E_TXONLY | 0x1 | Transmit Only
323  * ALT_SPIS_CTLR0_TMOD_E_RXONLY | 0x2 | Receive Only
324  *
325  * Field Access Macros:
326  *
327  */
328 /*
329  * Enumerated value for register field ALT_SPIS_CTLR0_TMOD
330  *
331  * Transmit & and Receive
332  */
333 #define ALT_SPIS_CTLR0_TMOD_E_TXRX 0x0
334 /*
335  * Enumerated value for register field ALT_SPIS_CTLR0_TMOD
336  *
337  * Transmit Only
338  */
339 #define ALT_SPIS_CTLR0_TMOD_E_TXONLY 0x1
340 /*
341  * Enumerated value for register field ALT_SPIS_CTLR0_TMOD
342  *
343  * Receive Only
344  */
345 #define ALT_SPIS_CTLR0_TMOD_E_RXONLY 0x2
346 
347 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_TMOD register field. */
348 #define ALT_SPIS_CTLR0_TMOD_LSB 8
349 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_TMOD register field. */
350 #define ALT_SPIS_CTLR0_TMOD_MSB 9
351 /* The width in bits of the ALT_SPIS_CTLR0_TMOD register field. */
352 #define ALT_SPIS_CTLR0_TMOD_WIDTH 2
353 /* The mask used to set the ALT_SPIS_CTLR0_TMOD register field value. */
354 #define ALT_SPIS_CTLR0_TMOD_SET_MSK 0x00000300
355 /* The mask used to clear the ALT_SPIS_CTLR0_TMOD register field value. */
356 #define ALT_SPIS_CTLR0_TMOD_CLR_MSK 0xfffffcff
357 /* The reset value of the ALT_SPIS_CTLR0_TMOD register field. */
358 #define ALT_SPIS_CTLR0_TMOD_RESET 0x0
359 /* Extracts the ALT_SPIS_CTLR0_TMOD field value from a register. */
360 #define ALT_SPIS_CTLR0_TMOD_GET(value) (((value) & 0x00000300) >> 8)
361 /* Produces a ALT_SPIS_CTLR0_TMOD register field value suitable for setting the register. */
362 #define ALT_SPIS_CTLR0_TMOD_SET(value) (((value) << 8) & 0x00000300)
363 
364 /*
365  * Field : Slave Output Enable - slv_oe
366  *
367  * This bit enables or disables the setting of the spis0_ssi_oe_n output from the
368  * SPI Slave. When SLV_OE = 1, the spis0_ssi_oe_n output can never be active. When
369  * the spis0_ssi_oe_n output controls the tri-state buffer on the txd output from
370  * the slave, a high impedance state is always present on the slave spis0_txd
371  * output when SLV_OE = 1. This is useful when the master transmits in broadcast
372  * mode (master transmits data to all slave devices). Only one slave may respond
373  * with data on the master spis0_rxd line. This bit is enabled after reset and must
374  * be disabled by software (when broadcast mode is used), if you do not want this
375  * device to respond with data.
376  *
377  * Field Enumeration Values:
378  *
379  * Enum | Value | Description
380  * :-----------------------------|:------|:----------------------
381  * ALT_SPIS_CTLR0_SLV_OE_E_END | 0x0 | Slave txd is enabled
382  * ALT_SPIS_CTLR0_SLV_OE_E_DISD | 0x1 | Slave txd is disabled
383  *
384  * Field Access Macros:
385  *
386  */
387 /*
388  * Enumerated value for register field ALT_SPIS_CTLR0_SLV_OE
389  *
390  * Slave txd is enabled
391  */
392 #define ALT_SPIS_CTLR0_SLV_OE_E_END 0x0
393 /*
394  * Enumerated value for register field ALT_SPIS_CTLR0_SLV_OE
395  *
396  * Slave txd is disabled
397  */
398 #define ALT_SPIS_CTLR0_SLV_OE_E_DISD 0x1
399 
400 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_SLV_OE register field. */
401 #define ALT_SPIS_CTLR0_SLV_OE_LSB 10
402 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_SLV_OE register field. */
403 #define ALT_SPIS_CTLR0_SLV_OE_MSB 10
404 /* The width in bits of the ALT_SPIS_CTLR0_SLV_OE register field. */
405 #define ALT_SPIS_CTLR0_SLV_OE_WIDTH 1
406 /* The mask used to set the ALT_SPIS_CTLR0_SLV_OE register field value. */
407 #define ALT_SPIS_CTLR0_SLV_OE_SET_MSK 0x00000400
408 /* The mask used to clear the ALT_SPIS_CTLR0_SLV_OE register field value. */
409 #define ALT_SPIS_CTLR0_SLV_OE_CLR_MSK 0xfffffbff
410 /* The reset value of the ALT_SPIS_CTLR0_SLV_OE register field. */
411 #define ALT_SPIS_CTLR0_SLV_OE_RESET 0x0
412 /* Extracts the ALT_SPIS_CTLR0_SLV_OE field value from a register. */
413 #define ALT_SPIS_CTLR0_SLV_OE_GET(value) (((value) & 0x00000400) >> 10)
414 /* Produces a ALT_SPIS_CTLR0_SLV_OE register field value suitable for setting the register. */
415 #define ALT_SPIS_CTLR0_SLV_OE_SET(value) (((value) << 10) & 0x00000400)
416 
417 /*
418  * Field : Shift Register Loop - srl
419  *
420  * Used for testing purposes only. When internally active, connects the transmit
421  * shift register output to the receive shift register input.
422  *
423  * Field Enumeration Values:
424  *
425  * Enum | Value | Description
426  * :-----------------------------|:------|:----------------------
427  * ALT_SPIS_CTLR0_SRL_E_NORMMOD | 0x0 | Normal Mode Operation
428  * ALT_SPIS_CTLR0_SRL_E_TESTMOD | 0x1 | Test Mode Operation
429  *
430  * Field Access Macros:
431  *
432  */
433 /*
434  * Enumerated value for register field ALT_SPIS_CTLR0_SRL
435  *
436  * Normal Mode Operation
437  */
438 #define ALT_SPIS_CTLR0_SRL_E_NORMMOD 0x0
439 /*
440  * Enumerated value for register field ALT_SPIS_CTLR0_SRL
441  *
442  * Test Mode Operation
443  */
444 #define ALT_SPIS_CTLR0_SRL_E_TESTMOD 0x1
445 
446 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_SRL register field. */
447 #define ALT_SPIS_CTLR0_SRL_LSB 11
448 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_SRL register field. */
449 #define ALT_SPIS_CTLR0_SRL_MSB 11
450 /* The width in bits of the ALT_SPIS_CTLR0_SRL register field. */
451 #define ALT_SPIS_CTLR0_SRL_WIDTH 1
452 /* The mask used to set the ALT_SPIS_CTLR0_SRL register field value. */
453 #define ALT_SPIS_CTLR0_SRL_SET_MSK 0x00000800
454 /* The mask used to clear the ALT_SPIS_CTLR0_SRL register field value. */
455 #define ALT_SPIS_CTLR0_SRL_CLR_MSK 0xfffff7ff
456 /* The reset value of the ALT_SPIS_CTLR0_SRL register field. */
457 #define ALT_SPIS_CTLR0_SRL_RESET 0x0
458 /* Extracts the ALT_SPIS_CTLR0_SRL field value from a register. */
459 #define ALT_SPIS_CTLR0_SRL_GET(value) (((value) & 0x00000800) >> 11)
460 /* Produces a ALT_SPIS_CTLR0_SRL register field value suitable for setting the register. */
461 #define ALT_SPIS_CTLR0_SRL_SET(value) (((value) << 11) & 0x00000800)
462 
463 /*
464  * Field : Control Frame Size - cfs
465  *
466  * Selects the length of the control word for the Microwire frame format. The
467  * length (in bits) is the value of this field plus 1.
468  *
469  * Field Access Macros:
470  *
471  */
472 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_CFS register field. */
473 #define ALT_SPIS_CTLR0_CFS_LSB 12
474 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_CFS register field. */
475 #define ALT_SPIS_CTLR0_CFS_MSB 15
476 /* The width in bits of the ALT_SPIS_CTLR0_CFS register field. */
477 #define ALT_SPIS_CTLR0_CFS_WIDTH 4
478 /* The mask used to set the ALT_SPIS_CTLR0_CFS register field value. */
479 #define ALT_SPIS_CTLR0_CFS_SET_MSK 0x0000f000
480 /* The mask used to clear the ALT_SPIS_CTLR0_CFS register field value. */
481 #define ALT_SPIS_CTLR0_CFS_CLR_MSK 0xffff0fff
482 /* The reset value of the ALT_SPIS_CTLR0_CFS register field. */
483 #define ALT_SPIS_CTLR0_CFS_RESET 0x0
484 /* Extracts the ALT_SPIS_CTLR0_CFS field value from a register. */
485 #define ALT_SPIS_CTLR0_CFS_GET(value) (((value) & 0x0000f000) >> 12)
486 /* Produces a ALT_SPIS_CTLR0_CFS register field value suitable for setting the register. */
487 #define ALT_SPIS_CTLR0_CFS_SET(value) (((value) << 12) & 0x0000f000)
488 
489 #ifndef __ASSEMBLY__
490 /*
491  * WARNING: The C register and register group struct declarations are provided for
492  * convenience and illustrative purposes. They should, however, be used with
493  * caution as the C language standard provides no guarantees about the alignment or
494  * atomicity of device memory accesses. The recommended practice for writing
495  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
496  * alt_write_word() functions.
497  *
498  * The struct declaration for register ALT_SPIS_CTLR0.
499  */
500 struct ALT_SPIS_CTLR0_s
501 {
502  uint32_t dfs : 4; /* Data Frame Size */
503  uint32_t frf : 2; /* Frame Format */
504  uint32_t scph : 1; /* Serial Clock Phase */
505  uint32_t scpol : 1; /* Serial Clock Polarity */
506  uint32_t tmod : 2; /* Transfer Mode */
507  uint32_t slv_oe : 1; /* Slave Output Enable */
508  uint32_t srl : 1; /* Shift Register Loop */
509  uint32_t cfs : 4; /* Control Frame Size */
510  uint32_t : 16; /* *UNDEFINED* */
511 };
512 
513 /* The typedef declaration for register ALT_SPIS_CTLR0. */
514 typedef volatile struct ALT_SPIS_CTLR0_s ALT_SPIS_CTLR0_t;
515 #endif /* __ASSEMBLY__ */
516 
517 /* The byte offset of the ALT_SPIS_CTLR0 register from the beginning of the component. */
518 #define ALT_SPIS_CTLR0_OFST 0x0
519 /* The address of the ALT_SPIS_CTLR0 register. */
520 #define ALT_SPIS_CTLR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_CTLR0_OFST))
521 
522 /*
523  * Register : Enable Register - spienr
524  *
525  * Enables and disables all SPI operations.
526  *
527  * Register Layout
528  *
529  * Bits | Access | Reset | Description
530  * :-------|:-------|:------|:------------
531  * [0] | RW | 0x0 | Enable
532  * [31:1] | ??? | 0x0 | *UNDEFINED*
533  *
534  */
535 /*
536  * Field : Enable - spi_en
537  *
538  * When disabled, all serial transfers are halted immediately. Transmit and receive
539  * FIFO buffers are cleared when the device is disabled. It is impossible to
540  * program some of the SPI Slave control registers when enabled.
541  *
542  * Field Enumeration Values:
543  *
544  * Enum | Value | Description
545  * :------------------------------|:------|:------------------------------------
546  * ALT_SPIS_SPIENR_SPI_EN_E_DISD | 0x0 | Disables serial transfer operations
547  * ALT_SPIS_SPIENR_SPI_EN_E_END | 0x1 | Enables serial transfer operations
548  *
549  * Field Access Macros:
550  *
551  */
552 /*
553  * Enumerated value for register field ALT_SPIS_SPIENR_SPI_EN
554  *
555  * Disables serial transfer operations
556  */
557 #define ALT_SPIS_SPIENR_SPI_EN_E_DISD 0x0
558 /*
559  * Enumerated value for register field ALT_SPIS_SPIENR_SPI_EN
560  *
561  * Enables serial transfer operations
562  */
563 #define ALT_SPIS_SPIENR_SPI_EN_E_END 0x1
564 
565 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SPIENR_SPI_EN register field. */
566 #define ALT_SPIS_SPIENR_SPI_EN_LSB 0
567 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SPIENR_SPI_EN register field. */
568 #define ALT_SPIS_SPIENR_SPI_EN_MSB 0
569 /* The width in bits of the ALT_SPIS_SPIENR_SPI_EN register field. */
570 #define ALT_SPIS_SPIENR_SPI_EN_WIDTH 1
571 /* The mask used to set the ALT_SPIS_SPIENR_SPI_EN register field value. */
572 #define ALT_SPIS_SPIENR_SPI_EN_SET_MSK 0x00000001
573 /* The mask used to clear the ALT_SPIS_SPIENR_SPI_EN register field value. */
574 #define ALT_SPIS_SPIENR_SPI_EN_CLR_MSK 0xfffffffe
575 /* The reset value of the ALT_SPIS_SPIENR_SPI_EN register field. */
576 #define ALT_SPIS_SPIENR_SPI_EN_RESET 0x0
577 /* Extracts the ALT_SPIS_SPIENR_SPI_EN field value from a register. */
578 #define ALT_SPIS_SPIENR_SPI_EN_GET(value) (((value) & 0x00000001) >> 0)
579 /* Produces a ALT_SPIS_SPIENR_SPI_EN register field value suitable for setting the register. */
580 #define ALT_SPIS_SPIENR_SPI_EN_SET(value) (((value) << 0) & 0x00000001)
581 
582 #ifndef __ASSEMBLY__
583 /*
584  * WARNING: The C register and register group struct declarations are provided for
585  * convenience and illustrative purposes. They should, however, be used with
586  * caution as the C language standard provides no guarantees about the alignment or
587  * atomicity of device memory accesses. The recommended practice for writing
588  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
589  * alt_write_word() functions.
590  *
591  * The struct declaration for register ALT_SPIS_SPIENR.
592  */
593 struct ALT_SPIS_SPIENR_s
594 {
595  uint32_t spi_en : 1; /* Enable */
596  uint32_t : 31; /* *UNDEFINED* */
597 };
598 
599 /* The typedef declaration for register ALT_SPIS_SPIENR. */
600 typedef volatile struct ALT_SPIS_SPIENR_s ALT_SPIS_SPIENR_t;
601 #endif /* __ASSEMBLY__ */
602 
603 /* The byte offset of the ALT_SPIS_SPIENR register from the beginning of the component. */
604 #define ALT_SPIS_SPIENR_OFST 0x8
605 /* The address of the ALT_SPIS_SPIENR register. */
606 #define ALT_SPIS_SPIENR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SPIENR_OFST))
607 
608 /*
609  * Register : Microwire Control Register - mwcr
610  *
611  * This register controls the direction of the data word for the half-duplex
612  * Microwire serial protocol. It is impossible to write to this register when the
613  * SPI Slave is enabled. The SPI Slave is enabled and disabled by writing to the
614  * SPIENR register.
615  *
616  * Register Layout
617  *
618  * Bits | Access | Reset | Description
619  * :-------|:-------|:------|:------------------------
620  * [0] | RW | 0x0 | Microwire Transfer Mode
621  * [1] | RW | 0x0 | Microwire Control
622  * [31:2] | ??? | 0x0 | *UNDEFINED*
623  *
624  */
625 /*
626  * Field : Microwire Transfer Mode - mwmod
627  *
628  * Defines whether the Microwire transfer is sequential or non-sequential. When
629  * sequential mode is used, only one control word is needed to transmit or receive
630  * a block of data words. When non-sequential mode is used, there must be a control
631  * word for each data word that is transmitted or received.
632  *
633  * Field Enumeration Values:
634  *
635  * Enum | Value | Description
636  * :-----------------------------|:------|:------------------------
637  * ALT_SPIS_MWCR_MWMOD_E_NONSEQ | 0x0 | non-sequential transfer
638  * ALT_SPIS_MWCR_MWMOD_E_SEQ | 0x1 | sequential transfer
639  *
640  * Field Access Macros:
641  *
642  */
643 /*
644  * Enumerated value for register field ALT_SPIS_MWCR_MWMOD
645  *
646  * non-sequential transfer
647  */
648 #define ALT_SPIS_MWCR_MWMOD_E_NONSEQ 0x0
649 /*
650  * Enumerated value for register field ALT_SPIS_MWCR_MWMOD
651  *
652  * sequential transfer
653  */
654 #define ALT_SPIS_MWCR_MWMOD_E_SEQ 0x1
655 
656 /* The Least Significant Bit (LSB) position of the ALT_SPIS_MWCR_MWMOD register field. */
657 #define ALT_SPIS_MWCR_MWMOD_LSB 0
658 /* The Most Significant Bit (MSB) position of the ALT_SPIS_MWCR_MWMOD register field. */
659 #define ALT_SPIS_MWCR_MWMOD_MSB 0
660 /* The width in bits of the ALT_SPIS_MWCR_MWMOD register field. */
661 #define ALT_SPIS_MWCR_MWMOD_WIDTH 1
662 /* The mask used to set the ALT_SPIS_MWCR_MWMOD register field value. */
663 #define ALT_SPIS_MWCR_MWMOD_SET_MSK 0x00000001
664 /* The mask used to clear the ALT_SPIS_MWCR_MWMOD register field value. */
665 #define ALT_SPIS_MWCR_MWMOD_CLR_MSK 0xfffffffe
666 /* The reset value of the ALT_SPIS_MWCR_MWMOD register field. */
667 #define ALT_SPIS_MWCR_MWMOD_RESET 0x0
668 /* Extracts the ALT_SPIS_MWCR_MWMOD field value from a register. */
669 #define ALT_SPIS_MWCR_MWMOD_GET(value) (((value) & 0x00000001) >> 0)
670 /* Produces a ALT_SPIS_MWCR_MWMOD register field value suitable for setting the register. */
671 #define ALT_SPIS_MWCR_MWMOD_SET(value) (((value) << 0) & 0x00000001)
672 
673 /*
674  * Field : Microwire Control - mdd
675  *
676  * Defines the direction of the data word when the Microwire serial protocol is
677  * used.
678  *
679  * Field Enumeration Values:
680  *
681  * Enum | Value | Description
682  * :--------------------------|:------|:-------------------------
683  * ALT_SPIS_MWCR_MDD_E_RXMOD | 0x0 | SPI Slave receives data
684  * ALT_SPIS_MWCR_MDD_E_TXMOD | 0x1 | SPI Slave transmits data
685  *
686  * Field Access Macros:
687  *
688  */
689 /*
690  * Enumerated value for register field ALT_SPIS_MWCR_MDD
691  *
692  * SPI Slave receives data
693  */
694 #define ALT_SPIS_MWCR_MDD_E_RXMOD 0x0
695 /*
696  * Enumerated value for register field ALT_SPIS_MWCR_MDD
697  *
698  * SPI Slave transmits data
699  */
700 #define ALT_SPIS_MWCR_MDD_E_TXMOD 0x1
701 
702 /* The Least Significant Bit (LSB) position of the ALT_SPIS_MWCR_MDD register field. */
703 #define ALT_SPIS_MWCR_MDD_LSB 1
704 /* The Most Significant Bit (MSB) position of the ALT_SPIS_MWCR_MDD register field. */
705 #define ALT_SPIS_MWCR_MDD_MSB 1
706 /* The width in bits of the ALT_SPIS_MWCR_MDD register field. */
707 #define ALT_SPIS_MWCR_MDD_WIDTH 1
708 /* The mask used to set the ALT_SPIS_MWCR_MDD register field value. */
709 #define ALT_SPIS_MWCR_MDD_SET_MSK 0x00000002
710 /* The mask used to clear the ALT_SPIS_MWCR_MDD register field value. */
711 #define ALT_SPIS_MWCR_MDD_CLR_MSK 0xfffffffd
712 /* The reset value of the ALT_SPIS_MWCR_MDD register field. */
713 #define ALT_SPIS_MWCR_MDD_RESET 0x0
714 /* Extracts the ALT_SPIS_MWCR_MDD field value from a register. */
715 #define ALT_SPIS_MWCR_MDD_GET(value) (((value) & 0x00000002) >> 1)
716 /* Produces a ALT_SPIS_MWCR_MDD register field value suitable for setting the register. */
717 #define ALT_SPIS_MWCR_MDD_SET(value) (((value) << 1) & 0x00000002)
718 
719 #ifndef __ASSEMBLY__
720 /*
721  * WARNING: The C register and register group struct declarations are provided for
722  * convenience and illustrative purposes. They should, however, be used with
723  * caution as the C language standard provides no guarantees about the alignment or
724  * atomicity of device memory accesses. The recommended practice for writing
725  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
726  * alt_write_word() functions.
727  *
728  * The struct declaration for register ALT_SPIS_MWCR.
729  */
730 struct ALT_SPIS_MWCR_s
731 {
732  uint32_t mwmod : 1; /* Microwire Transfer Mode */
733  uint32_t mdd : 1; /* Microwire Control */
734  uint32_t : 30; /* *UNDEFINED* */
735 };
736 
737 /* The typedef declaration for register ALT_SPIS_MWCR. */
738 typedef volatile struct ALT_SPIS_MWCR_s ALT_SPIS_MWCR_t;
739 #endif /* __ASSEMBLY__ */
740 
741 /* The byte offset of the ALT_SPIS_MWCR register from the beginning of the component. */
742 #define ALT_SPIS_MWCR_OFST 0xc
743 /* The address of the ALT_SPIS_MWCR register. */
744 #define ALT_SPIS_MWCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_MWCR_OFST))
745 
746 /*
747  * Register : Transmit FIFO Threshold Level Register - txftlr
748  *
749  * This register controls the threshold value for the transmit FIFO memory. It is
750  * impossible to write to this register when the SPI Slave is enabled. The SPI
751  * Slave is enabled and disabled by writing to the SPIENR register.
752  *
753  * Register Layout
754  *
755  * Bits | Access | Reset | Description
756  * :-------|:-------|:------|:------------------------
757  * [7:0] | RW | 0x0 | Transmit FIFO Threshold
758  * [31:8] | ??? | 0x0 | *UNDEFINED*
759  *
760  */
761 /*
762  * Field : Transmit FIFO Threshold - tft
763  *
764  * Controls the level of entries (or below) at which the transmit FIFO controller
765  * triggers an interrupt. When the number of transmit FIFO entries is less than or
766  * equal to this value, the transmit FIFO empty interrupt is triggered.
767  *
768  * Field Access Macros:
769  *
770  */
771 /* The Least Significant Bit (LSB) position of the ALT_SPIS_TXFTLR_TFT register field. */
772 #define ALT_SPIS_TXFTLR_TFT_LSB 0
773 /* The Most Significant Bit (MSB) position of the ALT_SPIS_TXFTLR_TFT register field. */
774 #define ALT_SPIS_TXFTLR_TFT_MSB 7
775 /* The width in bits of the ALT_SPIS_TXFTLR_TFT register field. */
776 #define ALT_SPIS_TXFTLR_TFT_WIDTH 8
777 /* The mask used to set the ALT_SPIS_TXFTLR_TFT register field value. */
778 #define ALT_SPIS_TXFTLR_TFT_SET_MSK 0x000000ff
779 /* The mask used to clear the ALT_SPIS_TXFTLR_TFT register field value. */
780 #define ALT_SPIS_TXFTLR_TFT_CLR_MSK 0xffffff00
781 /* The reset value of the ALT_SPIS_TXFTLR_TFT register field. */
782 #define ALT_SPIS_TXFTLR_TFT_RESET 0x0
783 /* Extracts the ALT_SPIS_TXFTLR_TFT field value from a register. */
784 #define ALT_SPIS_TXFTLR_TFT_GET(value) (((value) & 0x000000ff) >> 0)
785 /* Produces a ALT_SPIS_TXFTLR_TFT register field value suitable for setting the register. */
786 #define ALT_SPIS_TXFTLR_TFT_SET(value) (((value) << 0) & 0x000000ff)
787 
788 #ifndef __ASSEMBLY__
789 /*
790  * WARNING: The C register and register group struct declarations are provided for
791  * convenience and illustrative purposes. They should, however, be used with
792  * caution as the C language standard provides no guarantees about the alignment or
793  * atomicity of device memory accesses. The recommended practice for writing
794  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
795  * alt_write_word() functions.
796  *
797  * The struct declaration for register ALT_SPIS_TXFTLR.
798  */
799 struct ALT_SPIS_TXFTLR_s
800 {
801  uint32_t tft : 8; /* Transmit FIFO Threshold */
802  uint32_t : 24; /* *UNDEFINED* */
803 };
804 
805 /* The typedef declaration for register ALT_SPIS_TXFTLR. */
806 typedef volatile struct ALT_SPIS_TXFTLR_s ALT_SPIS_TXFTLR_t;
807 #endif /* __ASSEMBLY__ */
808 
809 /* The byte offset of the ALT_SPIS_TXFTLR register from the beginning of the component. */
810 #define ALT_SPIS_TXFTLR_OFST 0x18
811 /* The address of the ALT_SPIS_TXFTLR register. */
812 #define ALT_SPIS_TXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXFTLR_OFST))
813 
814 /*
815  * Register : Receive FIFO Threshold Level Register - rxftlr
816  *
817  * This register controls the threshold value for the receive FIFO memory. It is
818  * impossible to write to this register when the SPI Slave is enabled. The SPI
819  * Slave is enabled and disabled by writing to the SPIENR register.
820  *
821  * Register Layout
822  *
823  * Bits | Access | Reset | Description
824  * :-------|:-------|:------|:-----------------------
825  * [7:0] | RW | 0x0 | Receive FIFO Threshold
826  * [31:8] | ??? | 0x0 | *UNDEFINED*
827  *
828  */
829 /*
830  * Field : Receive FIFO Threshold - rft
831  *
832  * Controls the level of entries (or above) at which the receive FIFO controller
833  * triggers an interrupt. When the number of receive FIFO entries is greater than
834  * or equal to this value + 1, the receive FIFO full interrupt is triggered.
835  *
836  * Field Access Macros:
837  *
838  */
839 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RXFTLR_RFT register field. */
840 #define ALT_SPIS_RXFTLR_RFT_LSB 0
841 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RXFTLR_RFT register field. */
842 #define ALT_SPIS_RXFTLR_RFT_MSB 7
843 /* The width in bits of the ALT_SPIS_RXFTLR_RFT register field. */
844 #define ALT_SPIS_RXFTLR_RFT_WIDTH 8
845 /* The mask used to set the ALT_SPIS_RXFTLR_RFT register field value. */
846 #define ALT_SPIS_RXFTLR_RFT_SET_MSK 0x000000ff
847 /* The mask used to clear the ALT_SPIS_RXFTLR_RFT register field value. */
848 #define ALT_SPIS_RXFTLR_RFT_CLR_MSK 0xffffff00
849 /* The reset value of the ALT_SPIS_RXFTLR_RFT register field. */
850 #define ALT_SPIS_RXFTLR_RFT_RESET 0x0
851 /* Extracts the ALT_SPIS_RXFTLR_RFT field value from a register. */
852 #define ALT_SPIS_RXFTLR_RFT_GET(value) (((value) & 0x000000ff) >> 0)
853 /* Produces a ALT_SPIS_RXFTLR_RFT register field value suitable for setting the register. */
854 #define ALT_SPIS_RXFTLR_RFT_SET(value) (((value) << 0) & 0x000000ff)
855 
856 #ifndef __ASSEMBLY__
857 /*
858  * WARNING: The C register and register group struct declarations are provided for
859  * convenience and illustrative purposes. They should, however, be used with
860  * caution as the C language standard provides no guarantees about the alignment or
861  * atomicity of device memory accesses. The recommended practice for writing
862  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
863  * alt_write_word() functions.
864  *
865  * The struct declaration for register ALT_SPIS_RXFTLR.
866  */
867 struct ALT_SPIS_RXFTLR_s
868 {
869  uint32_t rft : 8; /* Receive FIFO Threshold */
870  uint32_t : 24; /* *UNDEFINED* */
871 };
872 
873 /* The typedef declaration for register ALT_SPIS_RXFTLR. */
874 typedef volatile struct ALT_SPIS_RXFTLR_s ALT_SPIS_RXFTLR_t;
875 #endif /* __ASSEMBLY__ */
876 
877 /* The byte offset of the ALT_SPIS_RXFTLR register from the beginning of the component. */
878 #define ALT_SPIS_RXFTLR_OFST 0x1c
879 /* The address of the ALT_SPIS_RXFTLR register. */
880 #define ALT_SPIS_RXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXFTLR_OFST))
881 
882 /*
883  * Register : Transmit FIFO Level Register - txflr
884  *
885  * This register contains the number of valid data entries in the transmit FIFO
886  * memory. Ranges from 0 to 256.
887  *
888  * Register Layout
889  *
890  * Bits | Access | Reset | Description
891  * :-------|:-------|:------|:--------------------
892  * [8:0] | R | 0x0 | Transmit FIFO Level
893  * [31:9] | ??? | 0x0 | *UNDEFINED*
894  *
895  */
896 /*
897  * Field : Transmit FIFO Level - txtfl
898  *
899  * Contains the number of valid data entries in the transmit FIFO.
900  *
901  * Field Access Macros:
902  *
903  */
904 /* The Least Significant Bit (LSB) position of the ALT_SPIS_TXFLR_TXTFL register field. */
905 #define ALT_SPIS_TXFLR_TXTFL_LSB 0
906 /* The Most Significant Bit (MSB) position of the ALT_SPIS_TXFLR_TXTFL register field. */
907 #define ALT_SPIS_TXFLR_TXTFL_MSB 8
908 /* The width in bits of the ALT_SPIS_TXFLR_TXTFL register field. */
909 #define ALT_SPIS_TXFLR_TXTFL_WIDTH 9
910 /* The mask used to set the ALT_SPIS_TXFLR_TXTFL register field value. */
911 #define ALT_SPIS_TXFLR_TXTFL_SET_MSK 0x000001ff
912 /* The mask used to clear the ALT_SPIS_TXFLR_TXTFL register field value. */
913 #define ALT_SPIS_TXFLR_TXTFL_CLR_MSK 0xfffffe00
914 /* The reset value of the ALT_SPIS_TXFLR_TXTFL register field. */
915 #define ALT_SPIS_TXFLR_TXTFL_RESET 0x0
916 /* Extracts the ALT_SPIS_TXFLR_TXTFL field value from a register. */
917 #define ALT_SPIS_TXFLR_TXTFL_GET(value) (((value) & 0x000001ff) >> 0)
918 /* Produces a ALT_SPIS_TXFLR_TXTFL register field value suitable for setting the register. */
919 #define ALT_SPIS_TXFLR_TXTFL_SET(value) (((value) << 0) & 0x000001ff)
920 
921 #ifndef __ASSEMBLY__
922 /*
923  * WARNING: The C register and register group struct declarations are provided for
924  * convenience and illustrative purposes. They should, however, be used with
925  * caution as the C language standard provides no guarantees about the alignment or
926  * atomicity of device memory accesses. The recommended practice for writing
927  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
928  * alt_write_word() functions.
929  *
930  * The struct declaration for register ALT_SPIS_TXFLR.
931  */
932 struct ALT_SPIS_TXFLR_s
933 {
934  const uint32_t txtfl : 9; /* Transmit FIFO Level */
935  uint32_t : 23; /* *UNDEFINED* */
936 };
937 
938 /* The typedef declaration for register ALT_SPIS_TXFLR. */
939 typedef volatile struct ALT_SPIS_TXFLR_s ALT_SPIS_TXFLR_t;
940 #endif /* __ASSEMBLY__ */
941 
942 /* The byte offset of the ALT_SPIS_TXFLR register from the beginning of the component. */
943 #define ALT_SPIS_TXFLR_OFST 0x20
944 /* The address of the ALT_SPIS_TXFLR register. */
945 #define ALT_SPIS_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXFLR_OFST))
946 
947 /*
948  * Register : Receive FIFO Level Register - rxflr
949  *
950  * This register contains the number of valid data entriesin the receive FIFO
951  * memory. This register can be read at any time. Ranges from 0 to 256.
952  *
953  * Register Layout
954  *
955  * Bits | Access | Reset | Description
956  * :-------|:-------|:------|:-------------------
957  * [8:0] | R | 0x0 | Receive FIFO Level
958  * [31:9] | ??? | 0x0 | *UNDEFINED*
959  *
960  */
961 /*
962  * Field : Receive FIFO Level - rxtfl
963  *
964  * Contains the number of valid data entries in the receive FIFO.
965  *
966  * Field Access Macros:
967  *
968  */
969 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RXFLR_RXTFL register field. */
970 #define ALT_SPIS_RXFLR_RXTFL_LSB 0
971 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RXFLR_RXTFL register field. */
972 #define ALT_SPIS_RXFLR_RXTFL_MSB 8
973 /* The width in bits of the ALT_SPIS_RXFLR_RXTFL register field. */
974 #define ALT_SPIS_RXFLR_RXTFL_WIDTH 9
975 /* The mask used to set the ALT_SPIS_RXFLR_RXTFL register field value. */
976 #define ALT_SPIS_RXFLR_RXTFL_SET_MSK 0x000001ff
977 /* The mask used to clear the ALT_SPIS_RXFLR_RXTFL register field value. */
978 #define ALT_SPIS_RXFLR_RXTFL_CLR_MSK 0xfffffe00
979 /* The reset value of the ALT_SPIS_RXFLR_RXTFL register field. */
980 #define ALT_SPIS_RXFLR_RXTFL_RESET 0x0
981 /* Extracts the ALT_SPIS_RXFLR_RXTFL field value from a register. */
982 #define ALT_SPIS_RXFLR_RXTFL_GET(value) (((value) & 0x000001ff) >> 0)
983 /* Produces a ALT_SPIS_RXFLR_RXTFL register field value suitable for setting the register. */
984 #define ALT_SPIS_RXFLR_RXTFL_SET(value) (((value) << 0) & 0x000001ff)
985 
986 #ifndef __ASSEMBLY__
987 /*
988  * WARNING: The C register and register group struct declarations are provided for
989  * convenience and illustrative purposes. They should, however, be used with
990  * caution as the C language standard provides no guarantees about the alignment or
991  * atomicity of device memory accesses. The recommended practice for writing
992  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
993  * alt_write_word() functions.
994  *
995  * The struct declaration for register ALT_SPIS_RXFLR.
996  */
997 struct ALT_SPIS_RXFLR_s
998 {
999  const uint32_t rxtfl : 9; /* Receive FIFO Level */
1000  uint32_t : 23; /* *UNDEFINED* */
1001 };
1002 
1003 /* The typedef declaration for register ALT_SPIS_RXFLR. */
1004 typedef volatile struct ALT_SPIS_RXFLR_s ALT_SPIS_RXFLR_t;
1005 #endif /* __ASSEMBLY__ */
1006 
1007 /* The byte offset of the ALT_SPIS_RXFLR register from the beginning of the component. */
1008 #define ALT_SPIS_RXFLR_OFST 0x24
1009 /* The address of the ALT_SPIS_RXFLR register. */
1010 #define ALT_SPIS_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXFLR_OFST))
1011 
1012 /*
1013  * Register : Status Register - sr
1014  *
1015  * Reports FIFO transfer status, and any transmission/reception errors that may
1016  * have occurred. The status register may be read at any time. None of the bits in
1017  * this register request an interrupt.
1018  *
1019  * Register Layout
1020  *
1021  * Bits | Access | Reset | Description
1022  * :-------|:-------|:------|:-----------------------
1023  * [0] | R | 0x0 | SPI Busy Flag
1024  * [1] | R | 0x1 | Transmit FIFO Not Full
1025  * [2] | R | 0x1 | Transmit FIFO Empty
1026  * [3] | R | 0x0 | Receive FIFO Not Empty
1027  * [4] | R | 0x0 | Receive FIFO Full
1028  * [5] | R | 0x0 | Transmission Error
1029  * [31:6] | ??? | 0x0 | *UNDEFINED*
1030  *
1031  */
1032 /*
1033  * Field : SPI Busy Flag - busy
1034  *
1035  * Reports the status of a serial transfer
1036  *
1037  * Field Enumeration Values:
1038  *
1039  * Enum | Value | Description
1040  * :-------------------------|:------|:-----------------------------------------
1041  * ALT_SPIS_SR_BUSY_E_INACT | 0x0 | SPI Slave is inactive (idle or disabled)
1042  * ALT_SPIS_SR_BUSY_E_ACT | 0x1 | SPI Slave is actively transferring data
1043  *
1044  * Field Access Macros:
1045  *
1046  */
1047 /*
1048  * Enumerated value for register field ALT_SPIS_SR_BUSY
1049  *
1050  * SPI Slave is inactive (idle or disabled)
1051  */
1052 #define ALT_SPIS_SR_BUSY_E_INACT 0x0
1053 /*
1054  * Enumerated value for register field ALT_SPIS_SR_BUSY
1055  *
1056  * SPI Slave is actively transferring data
1057  */
1058 #define ALT_SPIS_SR_BUSY_E_ACT 0x1
1059 
1060 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_BUSY register field. */
1061 #define ALT_SPIS_SR_BUSY_LSB 0
1062 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_BUSY register field. */
1063 #define ALT_SPIS_SR_BUSY_MSB 0
1064 /* The width in bits of the ALT_SPIS_SR_BUSY register field. */
1065 #define ALT_SPIS_SR_BUSY_WIDTH 1
1066 /* The mask used to set the ALT_SPIS_SR_BUSY register field value. */
1067 #define ALT_SPIS_SR_BUSY_SET_MSK 0x00000001
1068 /* The mask used to clear the ALT_SPIS_SR_BUSY register field value. */
1069 #define ALT_SPIS_SR_BUSY_CLR_MSK 0xfffffffe
1070 /* The reset value of the ALT_SPIS_SR_BUSY register field. */
1071 #define ALT_SPIS_SR_BUSY_RESET 0x0
1072 /* Extracts the ALT_SPIS_SR_BUSY field value from a register. */
1073 #define ALT_SPIS_SR_BUSY_GET(value) (((value) & 0x00000001) >> 0)
1074 /* Produces a ALT_SPIS_SR_BUSY register field value suitable for setting the register. */
1075 #define ALT_SPIS_SR_BUSY_SET(value) (((value) << 0) & 0x00000001)
1076 
1077 /*
1078  * Field : Transmit FIFO Not Full - tfnf
1079  *
1080  * Reports the status of the transmit FIFO.
1081  *
1082  * Field Enumeration Values:
1083  *
1084  * Enum | Value | Description
1085  * :---------------------------|:------|:--------------------------
1086  * ALT_SPIS_SR_TFNF_E_FULL | 0x0 | Transmit FIFO is full
1087  * ALT_SPIS_SR_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full
1088  *
1089  * Field Access Macros:
1090  *
1091  */
1092 /*
1093  * Enumerated value for register field ALT_SPIS_SR_TFNF
1094  *
1095  * Transmit FIFO is full
1096  */
1097 #define ALT_SPIS_SR_TFNF_E_FULL 0x0
1098 /*
1099  * Enumerated value for register field ALT_SPIS_SR_TFNF
1100  *
1101  * Transmit FIFO is not full
1102  */
1103 #define ALT_SPIS_SR_TFNF_E_NOTFULL 0x1
1104 
1105 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_TFNF register field. */
1106 #define ALT_SPIS_SR_TFNF_LSB 1
1107 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_TFNF register field. */
1108 #define ALT_SPIS_SR_TFNF_MSB 1
1109 /* The width in bits of the ALT_SPIS_SR_TFNF register field. */
1110 #define ALT_SPIS_SR_TFNF_WIDTH 1
1111 /* The mask used to set the ALT_SPIS_SR_TFNF register field value. */
1112 #define ALT_SPIS_SR_TFNF_SET_MSK 0x00000002
1113 /* The mask used to clear the ALT_SPIS_SR_TFNF register field value. */
1114 #define ALT_SPIS_SR_TFNF_CLR_MSK 0xfffffffd
1115 /* The reset value of the ALT_SPIS_SR_TFNF register field. */
1116 #define ALT_SPIS_SR_TFNF_RESET 0x1
1117 /* Extracts the ALT_SPIS_SR_TFNF field value from a register. */
1118 #define ALT_SPIS_SR_TFNF_GET(value) (((value) & 0x00000002) >> 1)
1119 /* Produces a ALT_SPIS_SR_TFNF register field value suitable for setting the register. */
1120 #define ALT_SPIS_SR_TFNF_SET(value) (((value) << 1) & 0x00000002)
1121 
1122 /*
1123  * Field : Transmit FIFO Empty - tfe
1124  *
1125  * Reports the status of transmit FIFO empty. This bit field does not request an
1126  * interrupt.
1127  *
1128  * Field Enumeration Values:
1129  *
1130  * Enum | Value | Description
1131  * :---------------------------|:------|:---------------------------
1132  * ALT_SPIS_SR_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty
1133  * ALT_SPIS_SR_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty
1134  *
1135  * Field Access Macros:
1136  *
1137  */
1138 /*
1139  * Enumerated value for register field ALT_SPIS_SR_TFE
1140  *
1141  * Transmit FIFO is empty
1142  */
1143 #define ALT_SPIS_SR_TFE_E_EMPTY 0x1
1144 /*
1145  * Enumerated value for register field ALT_SPIS_SR_TFE
1146  *
1147  * Transmit FIFO is not empty
1148  */
1149 #define ALT_SPIS_SR_TFE_E_NOTEMPTY 0x0
1150 
1151 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_TFE register field. */
1152 #define ALT_SPIS_SR_TFE_LSB 2
1153 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_TFE register field. */
1154 #define ALT_SPIS_SR_TFE_MSB 2
1155 /* The width in bits of the ALT_SPIS_SR_TFE register field. */
1156 #define ALT_SPIS_SR_TFE_WIDTH 1
1157 /* The mask used to set the ALT_SPIS_SR_TFE register field value. */
1158 #define ALT_SPIS_SR_TFE_SET_MSK 0x00000004
1159 /* The mask used to clear the ALT_SPIS_SR_TFE register field value. */
1160 #define ALT_SPIS_SR_TFE_CLR_MSK 0xfffffffb
1161 /* The reset value of the ALT_SPIS_SR_TFE register field. */
1162 #define ALT_SPIS_SR_TFE_RESET 0x1
1163 /* Extracts the ALT_SPIS_SR_TFE field value from a register. */
1164 #define ALT_SPIS_SR_TFE_GET(value) (((value) & 0x00000004) >> 2)
1165 /* Produces a ALT_SPIS_SR_TFE register field value suitable for setting the register. */
1166 #define ALT_SPIS_SR_TFE_SET(value) (((value) << 2) & 0x00000004)
1167 
1168 /*
1169  * Field : Receive FIFO Not Empty - rfne
1170  *
1171  * Reports the status of receive FIFO empty.
1172  *
1173  * Field Enumeration Values:
1174  *
1175  * Enum | Value | Description
1176  * :----------------------------|:------|:--------------------------
1177  * ALT_SPIS_SR_RFNE_E_EMPTY | 0x0 | Receive FIFO is empty
1178  * ALT_SPIS_SR_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty
1179  *
1180  * Field Access Macros:
1181  *
1182  */
1183 /*
1184  * Enumerated value for register field ALT_SPIS_SR_RFNE
1185  *
1186  * Receive FIFO is empty
1187  */
1188 #define ALT_SPIS_SR_RFNE_E_EMPTY 0x0
1189 /*
1190  * Enumerated value for register field ALT_SPIS_SR_RFNE
1191  *
1192  * Receive FIFO is not empty
1193  */
1194 #define ALT_SPIS_SR_RFNE_E_NOTEMPTY 0x1
1195 
1196 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_RFNE register field. */
1197 #define ALT_SPIS_SR_RFNE_LSB 3
1198 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_RFNE register field. */
1199 #define ALT_SPIS_SR_RFNE_MSB 3
1200 /* The width in bits of the ALT_SPIS_SR_RFNE register field. */
1201 #define ALT_SPIS_SR_RFNE_WIDTH 1
1202 /* The mask used to set the ALT_SPIS_SR_RFNE register field value. */
1203 #define ALT_SPIS_SR_RFNE_SET_MSK 0x00000008
1204 /* The mask used to clear the ALT_SPIS_SR_RFNE register field value. */
1205 #define ALT_SPIS_SR_RFNE_CLR_MSK 0xfffffff7
1206 /* The reset value of the ALT_SPIS_SR_RFNE register field. */
1207 #define ALT_SPIS_SR_RFNE_RESET 0x0
1208 /* Extracts the ALT_SPIS_SR_RFNE field value from a register. */
1209 #define ALT_SPIS_SR_RFNE_GET(value) (((value) & 0x00000008) >> 3)
1210 /* Produces a ALT_SPIS_SR_RFNE register field value suitable for setting the register. */
1211 #define ALT_SPIS_SR_RFNE_SET(value) (((value) << 3) & 0x00000008)
1212 
1213 /*
1214  * Field : Receive FIFO Full - rff
1215  *
1216  * Reports the status of receive FIFO Full
1217  *
1218  * Field Enumeration Values:
1219  *
1220  * Enum | Value | Description
1221  * :--------------------------|:------|:-------------------------
1222  * ALT_SPIS_SR_RFF_E_NOTFULL | 0x0 | Receive FIFO is not full
1223  * ALT_SPIS_SR_RFF_E_FULL | 0x1 | Receive FIFO is full
1224  *
1225  * Field Access Macros:
1226  *
1227  */
1228 /*
1229  * Enumerated value for register field ALT_SPIS_SR_RFF
1230  *
1231  * Receive FIFO is not full
1232  */
1233 #define ALT_SPIS_SR_RFF_E_NOTFULL 0x0
1234 /*
1235  * Enumerated value for register field ALT_SPIS_SR_RFF
1236  *
1237  * Receive FIFO is full
1238  */
1239 #define ALT_SPIS_SR_RFF_E_FULL 0x1
1240 
1241 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_RFF register field. */
1242 #define ALT_SPIS_SR_RFF_LSB 4
1243 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_RFF register field. */
1244 #define ALT_SPIS_SR_RFF_MSB 4
1245 /* The width in bits of the ALT_SPIS_SR_RFF register field. */
1246 #define ALT_SPIS_SR_RFF_WIDTH 1
1247 /* The mask used to set the ALT_SPIS_SR_RFF register field value. */
1248 #define ALT_SPIS_SR_RFF_SET_MSK 0x00000010
1249 /* The mask used to clear the ALT_SPIS_SR_RFF register field value. */
1250 #define ALT_SPIS_SR_RFF_CLR_MSK 0xffffffef
1251 /* The reset value of the ALT_SPIS_SR_RFF register field. */
1252 #define ALT_SPIS_SR_RFF_RESET 0x0
1253 /* Extracts the ALT_SPIS_SR_RFF field value from a register. */
1254 #define ALT_SPIS_SR_RFF_GET(value) (((value) & 0x00000010) >> 4)
1255 /* Produces a ALT_SPIS_SR_RFF register field value suitable for setting the register. */
1256 #define ALT_SPIS_SR_RFF_SET(value) (((value) << 4) & 0x00000010)
1257 
1258 /*
1259  * Field : Transmission Error - txe
1260  *
1261  * Data from the previous transmission is resent on the txd line. This bit is
1262  * cleared when read.
1263  *
1264  * Field Enumeration Values:
1265  *
1266  * Enum | Value | Description
1267  * :--------------------------|:------|:-------------------
1268  * ALT_SPIS_SR_TXE_E_NOERROR | 0x0 | No Error
1269  * ALT_SPIS_SR_TXE_E_ERROR | 0x1 | Transmission Error
1270  *
1271  * Field Access Macros:
1272  *
1273  */
1274 /*
1275  * Enumerated value for register field ALT_SPIS_SR_TXE
1276  *
1277  * No Error
1278  */
1279 #define ALT_SPIS_SR_TXE_E_NOERROR 0x0
1280 /*
1281  * Enumerated value for register field ALT_SPIS_SR_TXE
1282  *
1283  * Transmission Error
1284  */
1285 #define ALT_SPIS_SR_TXE_E_ERROR 0x1
1286 
1287 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_TXE register field. */
1288 #define ALT_SPIS_SR_TXE_LSB 5
1289 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_TXE register field. */
1290 #define ALT_SPIS_SR_TXE_MSB 5
1291 /* The width in bits of the ALT_SPIS_SR_TXE register field. */
1292 #define ALT_SPIS_SR_TXE_WIDTH 1
1293 /* The mask used to set the ALT_SPIS_SR_TXE register field value. */
1294 #define ALT_SPIS_SR_TXE_SET_MSK 0x00000020
1295 /* The mask used to clear the ALT_SPIS_SR_TXE register field value. */
1296 #define ALT_SPIS_SR_TXE_CLR_MSK 0xffffffdf
1297 /* The reset value of the ALT_SPIS_SR_TXE register field. */
1298 #define ALT_SPIS_SR_TXE_RESET 0x0
1299 /* Extracts the ALT_SPIS_SR_TXE field value from a register. */
1300 #define ALT_SPIS_SR_TXE_GET(value) (((value) & 0x00000020) >> 5)
1301 /* Produces a ALT_SPIS_SR_TXE register field value suitable for setting the register. */
1302 #define ALT_SPIS_SR_TXE_SET(value) (((value) << 5) & 0x00000020)
1303 
1304 #ifndef __ASSEMBLY__
1305 /*
1306  * WARNING: The C register and register group struct declarations are provided for
1307  * convenience and illustrative purposes. They should, however, be used with
1308  * caution as the C language standard provides no guarantees about the alignment or
1309  * atomicity of device memory accesses. The recommended practice for writing
1310  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1311  * alt_write_word() functions.
1312  *
1313  * The struct declaration for register ALT_SPIS_SR.
1314  */
1315 struct ALT_SPIS_SR_s
1316 {
1317  const uint32_t busy : 1; /* SPI Busy Flag */
1318  const uint32_t tfnf : 1; /* Transmit FIFO Not Full */
1319  const uint32_t tfe : 1; /* Transmit FIFO Empty */
1320  const uint32_t rfne : 1; /* Receive FIFO Not Empty */
1321  const uint32_t rff : 1; /* Receive FIFO Full */
1322  const uint32_t txe : 1; /* Transmission Error */
1323  uint32_t : 26; /* *UNDEFINED* */
1324 };
1325 
1326 /* The typedef declaration for register ALT_SPIS_SR. */
1327 typedef volatile struct ALT_SPIS_SR_s ALT_SPIS_SR_t;
1328 #endif /* __ASSEMBLY__ */
1329 
1330 /* The byte offset of the ALT_SPIS_SR register from the beginning of the component. */
1331 #define ALT_SPIS_SR_OFST 0x28
1332 /* The address of the ALT_SPIS_SR register. */
1333 #define ALT_SPIS_SR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SR_OFST))
1334 
1335 /*
1336  * Register : Interrupt Mask Register - imr
1337  *
1338  * This register masks or enables all interrupts generated by the SPI Slave.
1339  *
1340  * Register Layout
1341  *
1342  * Bits | Access | Reset | Description
1343  * :-------|:-------|:------|:--------------------------------------
1344  * [0] | RW | 0x1 | Transmit FIFO Empty Interrupt Mask
1345  * [1] | RW | 0x1 | Transmit FIFO Overflow Interrupt Mask
1346  * [2] | RW | 0x1 | Receive FIFO Underflow Interrupt Mask
1347  * [3] | RW | 0x1 | Receive FIFO Overflow Interrupt Mask
1348  * [4] | RW | 0x1 | Receive FIFO Full Interrupt Mask
1349  * [31:5] | ??? | 0x0 | *UNDEFINED*
1350  *
1351  */
1352 /*
1353  * Field : Transmit FIFO Empty Interrupt Mask - txeim
1354  *
1355  * Empty mask.
1356  *
1357  * Field Enumeration Values:
1358  *
1359  * Enum | Value | Description
1360  * :---------------------------|:------|:--------------------------------------------
1361  * ALT_SPIS_IMR_TXEIM_E_MSKED | 0x0 | spi_txe_intr interrupt is masked (disabled)
1362  * ALT_SPIS_IMR_TXEIM_E_END | 0x1 | spi_txe_intr interrupt is enabled
1363  *
1364  * Field Access Macros:
1365  *
1366  */
1367 /*
1368  * Enumerated value for register field ALT_SPIS_IMR_TXEIM
1369  *
1370  * spi_txe_intr interrupt is masked (disabled)
1371  */
1372 #define ALT_SPIS_IMR_TXEIM_E_MSKED 0x0
1373 /*
1374  * Enumerated value for register field ALT_SPIS_IMR_TXEIM
1375  *
1376  * spi_txe_intr interrupt is enabled
1377  */
1378 #define ALT_SPIS_IMR_TXEIM_E_END 0x1
1379 
1380 /* The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_TXEIM register field. */
1381 #define ALT_SPIS_IMR_TXEIM_LSB 0
1382 /* The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_TXEIM register field. */
1383 #define ALT_SPIS_IMR_TXEIM_MSB 0
1384 /* The width in bits of the ALT_SPIS_IMR_TXEIM register field. */
1385 #define ALT_SPIS_IMR_TXEIM_WIDTH 1
1386 /* The mask used to set the ALT_SPIS_IMR_TXEIM register field value. */
1387 #define ALT_SPIS_IMR_TXEIM_SET_MSK 0x00000001
1388 /* The mask used to clear the ALT_SPIS_IMR_TXEIM register field value. */
1389 #define ALT_SPIS_IMR_TXEIM_CLR_MSK 0xfffffffe
1390 /* The reset value of the ALT_SPIS_IMR_TXEIM register field. */
1391 #define ALT_SPIS_IMR_TXEIM_RESET 0x1
1392 /* Extracts the ALT_SPIS_IMR_TXEIM field value from a register. */
1393 #define ALT_SPIS_IMR_TXEIM_GET(value) (((value) & 0x00000001) >> 0)
1394 /* Produces a ALT_SPIS_IMR_TXEIM register field value suitable for setting the register. */
1395 #define ALT_SPIS_IMR_TXEIM_SET(value) (((value) << 0) & 0x00000001)
1396 
1397 /*
1398  * Field : Transmit FIFO Overflow Interrupt Mask - txoim
1399  *
1400  * Overflow mask.
1401  *
1402  * Field Enumeration Values:
1403  *
1404  * Enum | Value | Description
1405  * :---------------------------|:------|:--------------------------------------------
1406  * ALT_SPIS_IMR_TXOIM_E_MSKED | 0x0 | spi_txo_intr interrupt is masked (disabled)
1407  * ALT_SPIS_IMR_TXOIM_E_END | 0x1 | spi_txo_intr interrupt is enabled
1408  *
1409  * Field Access Macros:
1410  *
1411  */
1412 /*
1413  * Enumerated value for register field ALT_SPIS_IMR_TXOIM
1414  *
1415  * spi_txo_intr interrupt is masked (disabled)
1416  */
1417 #define ALT_SPIS_IMR_TXOIM_E_MSKED 0x0
1418 /*
1419  * Enumerated value for register field ALT_SPIS_IMR_TXOIM
1420  *
1421  * spi_txo_intr interrupt is enabled
1422  */
1423 #define ALT_SPIS_IMR_TXOIM_E_END 0x1
1424 
1425 /* The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_TXOIM register field. */
1426 #define ALT_SPIS_IMR_TXOIM_LSB 1
1427 /* The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_TXOIM register field. */
1428 #define ALT_SPIS_IMR_TXOIM_MSB 1
1429 /* The width in bits of the ALT_SPIS_IMR_TXOIM register field. */
1430 #define ALT_SPIS_IMR_TXOIM_WIDTH 1
1431 /* The mask used to set the ALT_SPIS_IMR_TXOIM register field value. */
1432 #define ALT_SPIS_IMR_TXOIM_SET_MSK 0x00000002
1433 /* The mask used to clear the ALT_SPIS_IMR_TXOIM register field value. */
1434 #define ALT_SPIS_IMR_TXOIM_CLR_MSK 0xfffffffd
1435 /* The reset value of the ALT_SPIS_IMR_TXOIM register field. */
1436 #define ALT_SPIS_IMR_TXOIM_RESET 0x1
1437 /* Extracts the ALT_SPIS_IMR_TXOIM field value from a register. */
1438 #define ALT_SPIS_IMR_TXOIM_GET(value) (((value) & 0x00000002) >> 1)
1439 /* Produces a ALT_SPIS_IMR_TXOIM register field value suitable for setting the register. */
1440 #define ALT_SPIS_IMR_TXOIM_SET(value) (((value) << 1) & 0x00000002)
1441 
1442 /*
1443  * Field : Receive FIFO Underflow Interrupt Mask - rxuim
1444  *
1445  * Underfow Mask
1446  *
1447  * Field Enumeration Values:
1448  *
1449  * Enum | Value | Description
1450  * :---------------------------|:------|:--------------------------------------------
1451  * ALT_SPIS_IMR_RXUIM_E_MSKED | 0x0 | spi_rxu_intr interrupt is masked (disabled)
1452  * ALT_SPIS_IMR_RXUIM_E_END | 0x1 | spi_rxu_intr interrupt is enabled
1453  *
1454  * Field Access Macros:
1455  *
1456  */
1457 /*
1458  * Enumerated value for register field ALT_SPIS_IMR_RXUIM
1459  *
1460  * spi_rxu_intr interrupt is masked (disabled)
1461  */
1462 #define ALT_SPIS_IMR_RXUIM_E_MSKED 0x0
1463 /*
1464  * Enumerated value for register field ALT_SPIS_IMR_RXUIM
1465  *
1466  * spi_rxu_intr interrupt is enabled
1467  */
1468 #define ALT_SPIS_IMR_RXUIM_E_END 0x1
1469 
1470 /* The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_RXUIM register field. */
1471 #define ALT_SPIS_IMR_RXUIM_LSB 2
1472 /* The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_RXUIM register field. */
1473 #define ALT_SPIS_IMR_RXUIM_MSB 2
1474 /* The width in bits of the ALT_SPIS_IMR_RXUIM register field. */
1475 #define ALT_SPIS_IMR_RXUIM_WIDTH 1
1476 /* The mask used to set the ALT_SPIS_IMR_RXUIM register field value. */
1477 #define ALT_SPIS_IMR_RXUIM_SET_MSK 0x00000004
1478 /* The mask used to clear the ALT_SPIS_IMR_RXUIM register field value. */
1479 #define ALT_SPIS_IMR_RXUIM_CLR_MSK 0xfffffffb
1480 /* The reset value of the ALT_SPIS_IMR_RXUIM register field. */
1481 #define ALT_SPIS_IMR_RXUIM_RESET 0x1
1482 /* Extracts the ALT_SPIS_IMR_RXUIM field value from a register. */
1483 #define ALT_SPIS_IMR_RXUIM_GET(value) (((value) & 0x00000004) >> 2)
1484 /* Produces a ALT_SPIS_IMR_RXUIM register field value suitable for setting the register. */
1485 #define ALT_SPIS_IMR_RXUIM_SET(value) (((value) << 2) & 0x00000004)
1486 
1487 /*
1488  * Field : Receive FIFO Overflow Interrupt Mask - rxoim
1489  *
1490  * Overflow Mask.
1491  *
1492  * Field Enumeration Values:
1493  *
1494  * Enum | Value | Description
1495  * :---------------------------|:------|:--------------------------------------------
1496  * ALT_SPIS_IMR_RXOIM_E_MSKED | 0x0 | spi_rxo_intr interrupt is masked (disabled)
1497  * ALT_SPIS_IMR_RXOIM_E_END | 0x1 | spi_rxo_intr interrupt is enabled
1498  *
1499  * Field Access Macros:
1500  *
1501  */
1502 /*
1503  * Enumerated value for register field ALT_SPIS_IMR_RXOIM
1504  *
1505  * spi_rxo_intr interrupt is masked (disabled)
1506  */
1507 #define ALT_SPIS_IMR_RXOIM_E_MSKED 0x0
1508 /*
1509  * Enumerated value for register field ALT_SPIS_IMR_RXOIM
1510  *
1511  * spi_rxo_intr interrupt is enabled
1512  */
1513 #define ALT_SPIS_IMR_RXOIM_E_END 0x1
1514 
1515 /* The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_RXOIM register field. */
1516 #define ALT_SPIS_IMR_RXOIM_LSB 3
1517 /* The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_RXOIM register field. */
1518 #define ALT_SPIS_IMR_RXOIM_MSB 3
1519 /* The width in bits of the ALT_SPIS_IMR_RXOIM register field. */
1520 #define ALT_SPIS_IMR_RXOIM_WIDTH 1
1521 /* The mask used to set the ALT_SPIS_IMR_RXOIM register field value. */
1522 #define ALT_SPIS_IMR_RXOIM_SET_MSK 0x00000008
1523 /* The mask used to clear the ALT_SPIS_IMR_RXOIM register field value. */
1524 #define ALT_SPIS_IMR_RXOIM_CLR_MSK 0xfffffff7
1525 /* The reset value of the ALT_SPIS_IMR_RXOIM register field. */
1526 #define ALT_SPIS_IMR_RXOIM_RESET 0x1
1527 /* Extracts the ALT_SPIS_IMR_RXOIM field value from a register. */
1528 #define ALT_SPIS_IMR_RXOIM_GET(value) (((value) & 0x00000008) >> 3)
1529 /* Produces a ALT_SPIS_IMR_RXOIM register field value suitable for setting the register. */
1530 #define ALT_SPIS_IMR_RXOIM_SET(value) (((value) << 3) & 0x00000008)
1531 
1532 /*
1533  * Field : Receive FIFO Full Interrupt Mask - rxfim
1534  *
1535  * FIFO Full Mask.
1536  *
1537  * Field Enumeration Values:
1538  *
1539  * Enum | Value | Description
1540  * :---------------------------|:------|:--------------------------------------------
1541  * ALT_SPIS_IMR_RXFIM_E_MSKED | 0x0 | spi_rxf_intr interrupt is masked (disabled)
1542  * ALT_SPIS_IMR_RXFIM_E_END | 0x1 | spi_rxf_intr interrupt is enabled
1543  *
1544  * Field Access Macros:
1545  *
1546  */
1547 /*
1548  * Enumerated value for register field ALT_SPIS_IMR_RXFIM
1549  *
1550  * spi_rxf_intr interrupt is masked (disabled)
1551  */
1552 #define ALT_SPIS_IMR_RXFIM_E_MSKED 0x0
1553 /*
1554  * Enumerated value for register field ALT_SPIS_IMR_RXFIM
1555  *
1556  * spi_rxf_intr interrupt is enabled
1557  */
1558 #define ALT_SPIS_IMR_RXFIM_E_END 0x1
1559 
1560 /* The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_RXFIM register field. */
1561 #define ALT_SPIS_IMR_RXFIM_LSB 4
1562 /* The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_RXFIM register field. */
1563 #define ALT_SPIS_IMR_RXFIM_MSB 4
1564 /* The width in bits of the ALT_SPIS_IMR_RXFIM register field. */
1565 #define ALT_SPIS_IMR_RXFIM_WIDTH 1
1566 /* The mask used to set the ALT_SPIS_IMR_RXFIM register field value. */
1567 #define ALT_SPIS_IMR_RXFIM_SET_MSK 0x00000010
1568 /* The mask used to clear the ALT_SPIS_IMR_RXFIM register field value. */
1569 #define ALT_SPIS_IMR_RXFIM_CLR_MSK 0xffffffef
1570 /* The reset value of the ALT_SPIS_IMR_RXFIM register field. */
1571 #define ALT_SPIS_IMR_RXFIM_RESET 0x1
1572 /* Extracts the ALT_SPIS_IMR_RXFIM field value from a register. */
1573 #define ALT_SPIS_IMR_RXFIM_GET(value) (((value) & 0x00000010) >> 4)
1574 /* Produces a ALT_SPIS_IMR_RXFIM register field value suitable for setting the register. */
1575 #define ALT_SPIS_IMR_RXFIM_SET(value) (((value) << 4) & 0x00000010)
1576 
1577 #ifndef __ASSEMBLY__
1578 /*
1579  * WARNING: The C register and register group struct declarations are provided for
1580  * convenience and illustrative purposes. They should, however, be used with
1581  * caution as the C language standard provides no guarantees about the alignment or
1582  * atomicity of device memory accesses. The recommended practice for writing
1583  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1584  * alt_write_word() functions.
1585  *
1586  * The struct declaration for register ALT_SPIS_IMR.
1587  */
1588 struct ALT_SPIS_IMR_s
1589 {
1590  uint32_t txeim : 1; /* Transmit FIFO Empty Interrupt Mask */
1591  uint32_t txoim : 1; /* Transmit FIFO Overflow Interrupt Mask */
1592  uint32_t rxuim : 1; /* Receive FIFO Underflow Interrupt Mask */
1593  uint32_t rxoim : 1; /* Receive FIFO Overflow Interrupt Mask */
1594  uint32_t rxfim : 1; /* Receive FIFO Full Interrupt Mask */
1595  uint32_t : 27; /* *UNDEFINED* */
1596 };
1597 
1598 /* The typedef declaration for register ALT_SPIS_IMR. */
1599 typedef volatile struct ALT_SPIS_IMR_s ALT_SPIS_IMR_t;
1600 #endif /* __ASSEMBLY__ */
1601 
1602 /* The byte offset of the ALT_SPIS_IMR register from the beginning of the component. */
1603 #define ALT_SPIS_IMR_OFST 0x2c
1604 /* The address of the ALT_SPIS_IMR register. */
1605 #define ALT_SPIS_IMR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_IMR_OFST))
1606 
1607 /*
1608  * Register : Interrupt Status Register - isr
1609  *
1610  * This register reports the status of the SPI Slave interrupts after they have
1611  * been masked.
1612  *
1613  * Register Layout
1614  *
1615  * Bits | Access | Reset | Description
1616  * :-------|:-------|:------|:----------------------------------------
1617  * [0] | R | 0x0 | Transmit FIFO Empty Interrupt Status
1618  * [1] | R | 0x0 | Transmit FIFO Overflow Interrupt Status
1619  * [2] | R | 0x0 | Receive FIFO Underflow Interrupt Status
1620  * [3] | R | 0x0 | Receive FIFO Overflow Interrupt Status
1621  * [4] | R | 0x0 | Receive FIFO Full Interrupt Status
1622  * [31:5] | ??? | 0x0 | *UNDEFINED*
1623  *
1624  */
1625 /*
1626  * Field : Transmit FIFO Empty Interrupt Status - txeis
1627  *
1628  * Empty Status.
1629  *
1630  * Field Enumeration Values:
1631  *
1632  * Enum | Value | Description
1633  * :---------------------------|:------|:-----------------------------------------------
1634  * ALT_SPIS_ISR_TXEIS_E_INACT | 0x0 | spi_txe_intr interrupt is not active after
1635  * : | | masking
1636  * ALT_SPIS_ISR_TXEIS_E_ACT | 0x1 | spi_txe_intr interrupt is active after masking
1637  *
1638  * Field Access Macros:
1639  *
1640  */
1641 /*
1642  * Enumerated value for register field ALT_SPIS_ISR_TXEIS
1643  *
1644  * spi_txe_intr interrupt is not active after masking
1645  */
1646 #define ALT_SPIS_ISR_TXEIS_E_INACT 0x0
1647 /*
1648  * Enumerated value for register field ALT_SPIS_ISR_TXEIS
1649  *
1650  * spi_txe_intr interrupt is active after masking
1651  */
1652 #define ALT_SPIS_ISR_TXEIS_E_ACT 0x1
1653 
1654 /* The Least Significant Bit (LSB) position of the ALT_SPIS_ISR_TXEIS register field. */
1655 #define ALT_SPIS_ISR_TXEIS_LSB 0
1656 /* The Most Significant Bit (MSB) position of the ALT_SPIS_ISR_TXEIS register field. */
1657 #define ALT_SPIS_ISR_TXEIS_MSB 0
1658 /* The width in bits of the ALT_SPIS_ISR_TXEIS register field. */
1659 #define ALT_SPIS_ISR_TXEIS_WIDTH 1
1660 /* The mask used to set the ALT_SPIS_ISR_TXEIS register field value. */
1661 #define ALT_SPIS_ISR_TXEIS_SET_MSK 0x00000001
1662 /* The mask used to clear the ALT_SPIS_ISR_TXEIS register field value. */
1663 #define ALT_SPIS_ISR_TXEIS_CLR_MSK 0xfffffffe
1664 /* The reset value of the ALT_SPIS_ISR_TXEIS register field. */
1665 #define ALT_SPIS_ISR_TXEIS_RESET 0x0
1666 /* Extracts the ALT_SPIS_ISR_TXEIS field value from a register. */
1667 #define ALT_SPIS_ISR_TXEIS_GET(value) (((value) & 0x00000001) >> 0)
1668 /* Produces a ALT_SPIS_ISR_TXEIS register field value suitable for setting the register. */
1669 #define ALT_SPIS_ISR_TXEIS_SET(value) (((value) << 0) & 0x00000001)
1670 
1671 /*
1672  * Field : Transmit FIFO Overflow Interrupt Status - txois
1673  *
1674  * Overflow Status.
1675  *
1676  * Field Enumeration Values:
1677  *
1678  * Enum | Value | Description
1679  * :---------------------------|:------|:-----------------------------------------------
1680  * ALT_SPIS_ISR_TXOIS_E_INACT | 0x0 | spi_txo_intr interrupt is not active after
1681  * : | | masking
1682  * ALT_SPIS_ISR_TXOIS_E_ACT | 0x1 | spi_txo_intr interrupt is active after masking
1683  *
1684  * Field Access Macros:
1685  *
1686  */
1687 /*
1688  * Enumerated value for register field ALT_SPIS_ISR_TXOIS
1689  *
1690  * spi_txo_intr interrupt is not active after masking
1691  */
1692 #define ALT_SPIS_ISR_TXOIS_E_INACT 0x0
1693 /*
1694  * Enumerated value for register field ALT_SPIS_ISR_TXOIS
1695  *
1696  * spi_txo_intr interrupt is active after masking
1697  */
1698 #define ALT_SPIS_ISR_TXOIS_E_ACT 0x1
1699 
1700 /* The Least Significant Bit (LSB) position of the ALT_SPIS_ISR_TXOIS register field. */
1701 #define ALT_SPIS_ISR_TXOIS_LSB 1
1702 /* The Most Significant Bit (MSB) position of the ALT_SPIS_ISR_TXOIS register field. */
1703 #define ALT_SPIS_ISR_TXOIS_MSB 1
1704 /* The width in bits of the ALT_SPIS_ISR_TXOIS register field. */
1705 #define ALT_SPIS_ISR_TXOIS_WIDTH 1
1706 /* The mask used to set the ALT_SPIS_ISR_TXOIS register field value. */
1707 #define ALT_SPIS_ISR_TXOIS_SET_MSK 0x00000002
1708 /* The mask used to clear the ALT_SPIS_ISR_TXOIS register field value. */
1709 #define ALT_SPIS_ISR_TXOIS_CLR_MSK 0xfffffffd
1710 /* The reset value of the ALT_SPIS_ISR_TXOIS register field. */
1711 #define ALT_SPIS_ISR_TXOIS_RESET 0x0
1712 /* Extracts the ALT_SPIS_ISR_TXOIS field value from a register. */
1713 #define ALT_SPIS_ISR_TXOIS_GET(value) (((value) & 0x00000002) >> 1)
1714 /* Produces a ALT_SPIS_ISR_TXOIS register field value suitable for setting the register. */
1715 #define ALT_SPIS_ISR_TXOIS_SET(value) (((value) << 1) & 0x00000002)
1716 
1717 /*
1718  * Field : Receive FIFO Underflow Interrupt Status - rxuis
1719  *
1720  * Underflow Status.
1721  *
1722  * Field Enumeration Values:
1723  *
1724  * Enum | Value | Description
1725  * :---------------------------|:------|:-----------------------------------------------
1726  * ALT_SPIS_ISR_RXUIS_E_INACT | 0x0 | spi_rxu_intr interrupt is not active after
1727  * : | | masking
1728  * ALT_SPIS_ISR_RXUIS_E_ACT | 0x1 | spi_rxu_intr interrupt is active after masking
1729  *
1730  * Field Access Macros:
1731  *
1732  */
1733 /*
1734  * Enumerated value for register field ALT_SPIS_ISR_RXUIS
1735  *
1736  * spi_rxu_intr interrupt is not active after masking
1737  */
1738 #define ALT_SPIS_ISR_RXUIS_E_INACT 0x0
1739 /*
1740  * Enumerated value for register field ALT_SPIS_ISR_RXUIS
1741  *
1742  * spi_rxu_intr interrupt is active after masking
1743  */
1744 #define ALT_SPIS_ISR_RXUIS_E_ACT 0x1
1745 
1746 /* The Least Significant Bit (LSB) position of the ALT_SPIS_ISR_RXUIS register field. */
1747 #define ALT_SPIS_ISR_RXUIS_LSB 2
1748 /* The Most Significant Bit (MSB) position of the ALT_SPIS_ISR_RXUIS register field. */
1749 #define ALT_SPIS_ISR_RXUIS_MSB 2
1750 /* The width in bits of the ALT_SPIS_ISR_RXUIS register field. */
1751 #define ALT_SPIS_ISR_RXUIS_WIDTH 1
1752 /* The mask used to set the ALT_SPIS_ISR_RXUIS register field value. */
1753 #define ALT_SPIS_ISR_RXUIS_SET_MSK 0x00000004
1754 /* The mask used to clear the ALT_SPIS_ISR_RXUIS register field value. */
1755 #define ALT_SPIS_ISR_RXUIS_CLR_MSK 0xfffffffb
1756 /* The reset value of the ALT_SPIS_ISR_RXUIS register field. */
1757 #define ALT_SPIS_ISR_RXUIS_RESET 0x0
1758 /* Extracts the ALT_SPIS_ISR_RXUIS field value from a register. */
1759 #define ALT_SPIS_ISR_RXUIS_GET(value) (((value) & 0x00000004) >> 2)
1760 /* Produces a ALT_SPIS_ISR_RXUIS register field value suitable for setting the register. */
1761 #define ALT_SPIS_ISR_RXUIS_SET(value) (((value) << 2) & 0x00000004)
1762 
1763 /*
1764  * Field : Receive FIFO Overflow Interrupt Status - rxois
1765  *
1766  * Overflow Status.
1767  *
1768  * Field Enumeration Values:
1769  *
1770  * Enum | Value | Description
1771  * :---------------------------|:------|:-----------------------------------------------
1772  * ALT_SPIS_ISR_RXOIS_E_INACT | 0x0 | spi_rxo_intr interrupt is not active after
1773  * : | | masking
1774  * ALT_SPIS_ISR_RXOIS_E_ACT | 0x1 | spi_rxo_intr interrupt is active after masking
1775  *
1776  * Field Access Macros:
1777  *
1778  */
1779 /*
1780  * Enumerated value for register field ALT_SPIS_ISR_RXOIS
1781  *
1782  * spi_rxo_intr interrupt is not active after masking
1783  */
1784 #define ALT_SPIS_ISR_RXOIS_E_INACT 0x0
1785 /*
1786  * Enumerated value for register field ALT_SPIS_ISR_RXOIS
1787  *
1788  * spi_rxo_intr interrupt is active after masking
1789  */
1790 #define ALT_SPIS_ISR_RXOIS_E_ACT 0x1
1791 
1792 /* The Least Significant Bit (LSB) position of the ALT_SPIS_ISR_RXOIS register field. */
1793 #define ALT_SPIS_ISR_RXOIS_LSB 3
1794 /* The Most Significant Bit (MSB) position of the ALT_SPIS_ISR_RXOIS register field. */
1795 #define ALT_SPIS_ISR_RXOIS_MSB 3
1796 /* The width in bits of the ALT_SPIS_ISR_RXOIS register field. */
1797 #define ALT_SPIS_ISR_RXOIS_WIDTH 1
1798 /* The mask used to set the ALT_SPIS_ISR_RXOIS register field value. */
1799 #define ALT_SPIS_ISR_RXOIS_SET_MSK 0x00000008
1800 /* The mask used to clear the ALT_SPIS_ISR_RXOIS register field value. */
1801 #define ALT_SPIS_ISR_RXOIS_CLR_MSK 0xfffffff7
1802 /* The reset value of the ALT_SPIS_ISR_RXOIS register field. */
1803 #define ALT_SPIS_ISR_RXOIS_RESET 0x0
1804 /* Extracts the ALT_SPIS_ISR_RXOIS field value from a register. */
1805 #define ALT_SPIS_ISR_RXOIS_GET(value) (((value) & 0x00000008) >> 3)
1806 /* Produces a ALT_SPIS_ISR_RXOIS register field value suitable for setting the register. */
1807 #define ALT_SPIS_ISR_RXOIS_SET(value) (((value) << 3) & 0x00000008)
1808 
1809 /*
1810  * Field : Receive FIFO Full Interrupt Status - rxfis
1811  *
1812  * Full Status
1813  *
1814  * Field Enumeration Values:
1815  *
1816  * Enum | Value | Description
1817  * :---------------------------|:------|:---------------------------------------------
1818  * ALT_SPIS_ISR_RXFIS_E_INACT | 0x0 | spi_rxf_intr interrupt is not active after
1819  * : | | masking
1820  * ALT_SPIS_ISR_RXFIS_E_ACT | 0x1 | spi_rxf_intr interrupt is full after masking
1821  *
1822  * Field Access Macros:
1823  *
1824  */
1825 /*
1826  * Enumerated value for register field ALT_SPIS_ISR_RXFIS
1827  *
1828  * spi_rxf_intr interrupt is not active after masking
1829  */
1830 #define ALT_SPIS_ISR_RXFIS_E_INACT 0x0
1831 /*
1832  * Enumerated value for register field ALT_SPIS_ISR_RXFIS
1833  *
1834  * spi_rxf_intr interrupt is full after masking
1835  */
1836 #define ALT_SPIS_ISR_RXFIS_E_ACT 0x1
1837 
1838 /* The Least Significant Bit (LSB) position of the ALT_SPIS_ISR_RXFIS register field. */
1839 #define ALT_SPIS_ISR_RXFIS_LSB 4
1840 /* The Most Significant Bit (MSB) position of the ALT_SPIS_ISR_RXFIS register field. */
1841 #define ALT_SPIS_ISR_RXFIS_MSB 4
1842 /* The width in bits of the ALT_SPIS_ISR_RXFIS register field. */
1843 #define ALT_SPIS_ISR_RXFIS_WIDTH 1
1844 /* The mask used to set the ALT_SPIS_ISR_RXFIS register field value. */
1845 #define ALT_SPIS_ISR_RXFIS_SET_MSK 0x00000010
1846 /* The mask used to clear the ALT_SPIS_ISR_RXFIS register field value. */
1847 #define ALT_SPIS_ISR_RXFIS_CLR_MSK 0xffffffef
1848 /* The reset value of the ALT_SPIS_ISR_RXFIS register field. */
1849 #define ALT_SPIS_ISR_RXFIS_RESET 0x0
1850 /* Extracts the ALT_SPIS_ISR_RXFIS field value from a register. */
1851 #define ALT_SPIS_ISR_RXFIS_GET(value) (((value) & 0x00000010) >> 4)
1852 /* Produces a ALT_SPIS_ISR_RXFIS register field value suitable for setting the register. */
1853 #define ALT_SPIS_ISR_RXFIS_SET(value) (((value) << 4) & 0x00000010)
1854 
1855 #ifndef __ASSEMBLY__
1856 /*
1857  * WARNING: The C register and register group struct declarations are provided for
1858  * convenience and illustrative purposes. They should, however, be used with
1859  * caution as the C language standard provides no guarantees about the alignment or
1860  * atomicity of device memory accesses. The recommended practice for writing
1861  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1862  * alt_write_word() functions.
1863  *
1864  * The struct declaration for register ALT_SPIS_ISR.
1865  */
1866 struct ALT_SPIS_ISR_s
1867 {
1868  const uint32_t txeis : 1; /* Transmit FIFO Empty Interrupt Status */
1869  const uint32_t txois : 1; /* Transmit FIFO Overflow Interrupt Status */
1870  const uint32_t rxuis : 1; /* Receive FIFO Underflow Interrupt Status */
1871  const uint32_t rxois : 1; /* Receive FIFO Overflow Interrupt Status */
1872  const uint32_t rxfis : 1; /* Receive FIFO Full Interrupt Status */
1873  uint32_t : 27; /* *UNDEFINED* */
1874 };
1875 
1876 /* The typedef declaration for register ALT_SPIS_ISR. */
1877 typedef volatile struct ALT_SPIS_ISR_s ALT_SPIS_ISR_t;
1878 #endif /* __ASSEMBLY__ */
1879 
1880 /* The byte offset of the ALT_SPIS_ISR register from the beginning of the component. */
1881 #define ALT_SPIS_ISR_OFST 0x30
1882 /* The address of the ALT_SPIS_ISR register. */
1883 #define ALT_SPIS_ISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_ISR_OFST))
1884 
1885 /*
1886  * Register : Raw Interrupt Status Register - risr
1887  *
1888  * This register reports the status of the SPI Slave interrupts prior to masking.
1889  *
1890  * Register Layout
1891  *
1892  * Bits | Access | Reset | Description
1893  * :-------|:-------|:------|:--------------------------------------------
1894  * [0] | R | 0x0 | Transmit FIFO Empty Raw Interrupt Status
1895  * [1] | R | 0x0 | Transmit FIFO Overflow Raw Interrupt Status
1896  * [2] | R | 0x0 | Receive FIFO Underflow Raw Interrupt Status
1897  * [3] | R | 0x0 | Receive FIFO Overflow Raw Interrupt Status
1898  * [4] | R | 0x0 | Receive FIFO Full Raw Interrupt Status
1899  * [31:5] | ??? | 0x0 | *UNDEFINED*
1900  *
1901  */
1902 /*
1903  * Field : Transmit FIFO Empty Raw Interrupt Status - txeir
1904  *
1905  * The interrupt is active or inactive prior to masking.
1906  *
1907  * Field Enumeration Values:
1908  *
1909  * Enum | Value | Description
1910  * :----------------------------|:------|:-----------------------------------------------
1911  * ALT_SPIS_RISR_TXEIR_E_INACT | 0x0 | spi_txe_intr interrupt is not active prior to
1912  * : | | masking
1913  * ALT_SPIS_RISR_TXEIR_E_ACT | 0x1 | spi_txe_intr interrupt is active prior masking
1914  *
1915  * Field Access Macros:
1916  *
1917  */
1918 /*
1919  * Enumerated value for register field ALT_SPIS_RISR_TXEIR
1920  *
1921  * spi_txe_intr interrupt is not active prior to masking
1922  */
1923 #define ALT_SPIS_RISR_TXEIR_E_INACT 0x0
1924 /*
1925  * Enumerated value for register field ALT_SPIS_RISR_TXEIR
1926  *
1927  * spi_txe_intr interrupt is active prior masking
1928  */
1929 #define ALT_SPIS_RISR_TXEIR_E_ACT 0x1
1930 
1931 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_TXEIR register field. */
1932 #define ALT_SPIS_RISR_TXEIR_LSB 0
1933 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_TXEIR register field. */
1934 #define ALT_SPIS_RISR_TXEIR_MSB 0
1935 /* The width in bits of the ALT_SPIS_RISR_TXEIR register field. */
1936 #define ALT_SPIS_RISR_TXEIR_WIDTH 1
1937 /* The mask used to set the ALT_SPIS_RISR_TXEIR register field value. */
1938 #define ALT_SPIS_RISR_TXEIR_SET_MSK 0x00000001
1939 /* The mask used to clear the ALT_SPIS_RISR_TXEIR register field value. */
1940 #define ALT_SPIS_RISR_TXEIR_CLR_MSK 0xfffffffe
1941 /* The reset value of the ALT_SPIS_RISR_TXEIR register field. */
1942 #define ALT_SPIS_RISR_TXEIR_RESET 0x0
1943 /* Extracts the ALT_SPIS_RISR_TXEIR field value from a register. */
1944 #define ALT_SPIS_RISR_TXEIR_GET(value) (((value) & 0x00000001) >> 0)
1945 /* Produces a ALT_SPIS_RISR_TXEIR register field value suitable for setting the register. */
1946 #define ALT_SPIS_RISR_TXEIR_SET(value) (((value) << 0) & 0x00000001)
1947 
1948 /*
1949  * Field : Transmit FIFO Overflow Raw Interrupt Status - txoir
1950  *
1951  * The interrupt is active or inactive prior to masking.
1952  *
1953  * Field Enumeration Values:
1954  *
1955  * Enum | Value | Description
1956  * :----------------------------|:------|:-----------------------------------------------
1957  * ALT_SPIS_RISR_TXOIR_E_INACT | 0x0 | spi_txo_intr interrupt is not active prior to
1958  * : | | masking
1959  * ALT_SPIS_RISR_TXOIR_E_ACT | 0x1 | spi_txo_intr interrupt is active prior masking
1960  *
1961  * Field Access Macros:
1962  *
1963  */
1964 /*
1965  * Enumerated value for register field ALT_SPIS_RISR_TXOIR
1966  *
1967  * spi_txo_intr interrupt is not active prior to masking
1968  */
1969 #define ALT_SPIS_RISR_TXOIR_E_INACT 0x0
1970 /*
1971  * Enumerated value for register field ALT_SPIS_RISR_TXOIR
1972  *
1973  * spi_txo_intr interrupt is active prior masking
1974  */
1975 #define ALT_SPIS_RISR_TXOIR_E_ACT 0x1
1976 
1977 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_TXOIR register field. */
1978 #define ALT_SPIS_RISR_TXOIR_LSB 1
1979 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_TXOIR register field. */
1980 #define ALT_SPIS_RISR_TXOIR_MSB 1
1981 /* The width in bits of the ALT_SPIS_RISR_TXOIR register field. */
1982 #define ALT_SPIS_RISR_TXOIR_WIDTH 1
1983 /* The mask used to set the ALT_SPIS_RISR_TXOIR register field value. */
1984 #define ALT_SPIS_RISR_TXOIR_SET_MSK 0x00000002
1985 /* The mask used to clear the ALT_SPIS_RISR_TXOIR register field value. */
1986 #define ALT_SPIS_RISR_TXOIR_CLR_MSK 0xfffffffd
1987 /* The reset value of the ALT_SPIS_RISR_TXOIR register field. */
1988 #define ALT_SPIS_RISR_TXOIR_RESET 0x0
1989 /* Extracts the ALT_SPIS_RISR_TXOIR field value from a register. */
1990 #define ALT_SPIS_RISR_TXOIR_GET(value) (((value) & 0x00000002) >> 1)
1991 /* Produces a ALT_SPIS_RISR_TXOIR register field value suitable for setting the register. */
1992 #define ALT_SPIS_RISR_TXOIR_SET(value) (((value) << 1) & 0x00000002)
1993 
1994 /*
1995  * Field : Receive FIFO Underflow Raw Interrupt Status - rxuir
1996  *
1997  * The interrupt is active or inactive prior to masking.
1998  *
1999  * Field Enumeration Values:
2000  *
2001  * Enum | Value | Description
2002  * :----------------------------|:------|:----------------------------------------------
2003  * ALT_SPIS_RISR_RXUIR_E_INACT | 0x0 | spi_rxu_intr interrupt is not active prior to
2004  * : | | masking
2005  * ALT_SPIS_RISR_RXUIR_E_ACT | 0x1 | spi_rxu_intr interrupt is active prior to
2006  * : | | masking
2007  *
2008  * Field Access Macros:
2009  *
2010  */
2011 /*
2012  * Enumerated value for register field ALT_SPIS_RISR_RXUIR
2013  *
2014  * spi_rxu_intr interrupt is not active prior to masking
2015  */
2016 #define ALT_SPIS_RISR_RXUIR_E_INACT 0x0
2017 /*
2018  * Enumerated value for register field ALT_SPIS_RISR_RXUIR
2019  *
2020  * spi_rxu_intr interrupt is active prior to masking
2021  */
2022 #define ALT_SPIS_RISR_RXUIR_E_ACT 0x1
2023 
2024 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_RXUIR register field. */
2025 #define ALT_SPIS_RISR_RXUIR_LSB 2
2026 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_RXUIR register field. */
2027 #define ALT_SPIS_RISR_RXUIR_MSB 2
2028 /* The width in bits of the ALT_SPIS_RISR_RXUIR register field. */
2029 #define ALT_SPIS_RISR_RXUIR_WIDTH 1
2030 /* The mask used to set the ALT_SPIS_RISR_RXUIR register field value. */
2031 #define ALT_SPIS_RISR_RXUIR_SET_MSK 0x00000004
2032 /* The mask used to clear the ALT_SPIS_RISR_RXUIR register field value. */
2033 #define ALT_SPIS_RISR_RXUIR_CLR_MSK 0xfffffffb
2034 /* The reset value of the ALT_SPIS_RISR_RXUIR register field. */
2035 #define ALT_SPIS_RISR_RXUIR_RESET 0x0
2036 /* Extracts the ALT_SPIS_RISR_RXUIR field value from a register. */
2037 #define ALT_SPIS_RISR_RXUIR_GET(value) (((value) & 0x00000004) >> 2)
2038 /* Produces a ALT_SPIS_RISR_RXUIR register field value suitable for setting the register. */
2039 #define ALT_SPIS_RISR_RXUIR_SET(value) (((value) << 2) & 0x00000004)
2040 
2041 /*
2042  * Field : Receive FIFO Overflow Raw Interrupt Status - rxoir
2043  *
2044  * The interrupt is active or inactive prior to masking.
2045  *
2046  * Field Enumeration Values:
2047  *
2048  * Enum | Value | Description
2049  * :----------------------------|:------|:-----------------------------------------------
2050  * ALT_SPIS_RISR_RXOIR_E_INACT | 0x0 | spi_rxo_intr interrupt is not active prior to
2051  * : | | masking
2052  * ALT_SPIS_RISR_RXOIR_E_ACT | 0x1 | spi_rxo_intr interrupt is active prior masking
2053  *
2054  * Field Access Macros:
2055  *
2056  */
2057 /*
2058  * Enumerated value for register field ALT_SPIS_RISR_RXOIR
2059  *
2060  * spi_rxo_intr interrupt is not active prior to masking
2061  */
2062 #define ALT_SPIS_RISR_RXOIR_E_INACT 0x0
2063 /*
2064  * Enumerated value for register field ALT_SPIS_RISR_RXOIR
2065  *
2066  * spi_rxo_intr interrupt is active prior masking
2067  */
2068 #define ALT_SPIS_RISR_RXOIR_E_ACT 0x1
2069 
2070 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_RXOIR register field. */
2071 #define ALT_SPIS_RISR_RXOIR_LSB 3
2072 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_RXOIR register field. */
2073 #define ALT_SPIS_RISR_RXOIR_MSB 3
2074 /* The width in bits of the ALT_SPIS_RISR_RXOIR register field. */
2075 #define ALT_SPIS_RISR_RXOIR_WIDTH 1
2076 /* The mask used to set the ALT_SPIS_RISR_RXOIR register field value. */
2077 #define ALT_SPIS_RISR_RXOIR_SET_MSK 0x00000008
2078 /* The mask used to clear the ALT_SPIS_RISR_RXOIR register field value. */
2079 #define ALT_SPIS_RISR_RXOIR_CLR_MSK 0xfffffff7
2080 /* The reset value of the ALT_SPIS_RISR_RXOIR register field. */
2081 #define ALT_SPIS_RISR_RXOIR_RESET 0x0
2082 /* Extracts the ALT_SPIS_RISR_RXOIR field value from a register. */
2083 #define ALT_SPIS_RISR_RXOIR_GET(value) (((value) & 0x00000008) >> 3)
2084 /* Produces a ALT_SPIS_RISR_RXOIR register field value suitable for setting the register. */
2085 #define ALT_SPIS_RISR_RXOIR_SET(value) (((value) << 3) & 0x00000008)
2086 
2087 /*
2088  * Field : Receive FIFO Full Raw Interrupt Status - rxfir
2089  *
2090  * The interrupt is active or inactive prior to masking.
2091  *
2092  * Field Enumeration Values:
2093  *
2094  * Enum | Value | Description
2095  * :----------------------------|:------|:----------------------------------------------
2096  * ALT_SPIS_RISR_RXFIR_E_INACT | 0x0 | spi_rxf_intr interrupt is not active prior to
2097  * : | | masking
2098  * ALT_SPIS_RISR_RXFIR_E_ACT | 0x1 | spi_rxf_intr interrupt is active prior to
2099  * : | | masking
2100  *
2101  * Field Access Macros:
2102  *
2103  */
2104 /*
2105  * Enumerated value for register field ALT_SPIS_RISR_RXFIR
2106  *
2107  * spi_rxf_intr interrupt is not active prior to masking
2108  */
2109 #define ALT_SPIS_RISR_RXFIR_E_INACT 0x0
2110 /*
2111  * Enumerated value for register field ALT_SPIS_RISR_RXFIR
2112  *
2113  * spi_rxf_intr interrupt is active prior to masking
2114  */
2115 #define ALT_SPIS_RISR_RXFIR_E_ACT 0x1
2116 
2117 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_RXFIR register field. */
2118 #define ALT_SPIS_RISR_RXFIR_LSB 4
2119 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_RXFIR register field. */
2120 #define ALT_SPIS_RISR_RXFIR_MSB 4
2121 /* The width in bits of the ALT_SPIS_RISR_RXFIR register field. */
2122 #define ALT_SPIS_RISR_RXFIR_WIDTH 1
2123 /* The mask used to set the ALT_SPIS_RISR_RXFIR register field value. */
2124 #define ALT_SPIS_RISR_RXFIR_SET_MSK 0x00000010
2125 /* The mask used to clear the ALT_SPIS_RISR_RXFIR register field value. */
2126 #define ALT_SPIS_RISR_RXFIR_CLR_MSK 0xffffffef
2127 /* The reset value of the ALT_SPIS_RISR_RXFIR register field. */
2128 #define ALT_SPIS_RISR_RXFIR_RESET 0x0
2129 /* Extracts the ALT_SPIS_RISR_RXFIR field value from a register. */
2130 #define ALT_SPIS_RISR_RXFIR_GET(value) (((value) & 0x00000010) >> 4)
2131 /* Produces a ALT_SPIS_RISR_RXFIR register field value suitable for setting the register. */
2132 #define ALT_SPIS_RISR_RXFIR_SET(value) (((value) << 4) & 0x00000010)
2133 
2134 #ifndef __ASSEMBLY__
2135 /*
2136  * WARNING: The C register and register group struct declarations are provided for
2137  * convenience and illustrative purposes. They should, however, be used with
2138  * caution as the C language standard provides no guarantees about the alignment or
2139  * atomicity of device memory accesses. The recommended practice for writing
2140  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2141  * alt_write_word() functions.
2142  *
2143  * The struct declaration for register ALT_SPIS_RISR.
2144  */
2145 struct ALT_SPIS_RISR_s
2146 {
2147  const uint32_t txeir : 1; /* Transmit FIFO Empty Raw Interrupt Status */
2148  const uint32_t txoir : 1; /* Transmit FIFO Overflow Raw Interrupt Status */
2149  const uint32_t rxuir : 1; /* Receive FIFO Underflow Raw Interrupt Status */
2150  const uint32_t rxoir : 1; /* Receive FIFO Overflow Raw Interrupt Status */
2151  const uint32_t rxfir : 1; /* Receive FIFO Full Raw Interrupt Status */
2152  uint32_t : 27; /* *UNDEFINED* */
2153 };
2154 
2155 /* The typedef declaration for register ALT_SPIS_RISR. */
2156 typedef volatile struct ALT_SPIS_RISR_s ALT_SPIS_RISR_t;
2157 #endif /* __ASSEMBLY__ */
2158 
2159 /* The byte offset of the ALT_SPIS_RISR register from the beginning of the component. */
2160 #define ALT_SPIS_RISR_OFST 0x34
2161 /* The address of the ALT_SPIS_RISR register. */
2162 #define ALT_SPIS_RISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RISR_OFST))
2163 
2164 /*
2165  * Register : Transmit FIFO Overflow Interrupt Clear Register - txoicr
2166  *
2167  * Register Layout
2168  *
2169  * Bits | Access | Reset | Description
2170  * :-------|:-------|:------|:---------------------------------------
2171  * [0] | R | 0x0 | Clear Transmit FIFO Overflow Interrupt
2172  * [31:1] | ??? | 0x0 | *UNDEFINED*
2173  *
2174  */
2175 /*
2176  * Field : Clear Transmit FIFO Overflow Interrupt - txoicr
2177  *
2178  * This register reflects the status of the interrupt. A read from this register
2179  * clears the ssi_txo_intr interrupt; writing has no effect.
2180  *
2181  * Field Access Macros:
2182  *
2183  */
2184 /* The Least Significant Bit (LSB) position of the ALT_SPIS_TXOICR_TXOICR register field. */
2185 #define ALT_SPIS_TXOICR_TXOICR_LSB 0
2186 /* The Most Significant Bit (MSB) position of the ALT_SPIS_TXOICR_TXOICR register field. */
2187 #define ALT_SPIS_TXOICR_TXOICR_MSB 0
2188 /* The width in bits of the ALT_SPIS_TXOICR_TXOICR register field. */
2189 #define ALT_SPIS_TXOICR_TXOICR_WIDTH 1
2190 /* The mask used to set the ALT_SPIS_TXOICR_TXOICR register field value. */
2191 #define ALT_SPIS_TXOICR_TXOICR_SET_MSK 0x00000001
2192 /* The mask used to clear the ALT_SPIS_TXOICR_TXOICR register field value. */
2193 #define ALT_SPIS_TXOICR_TXOICR_CLR_MSK 0xfffffffe
2194 /* The reset value of the ALT_SPIS_TXOICR_TXOICR register field. */
2195 #define ALT_SPIS_TXOICR_TXOICR_RESET 0x0
2196 /* Extracts the ALT_SPIS_TXOICR_TXOICR field value from a register. */
2197 #define ALT_SPIS_TXOICR_TXOICR_GET(value) (((value) & 0x00000001) >> 0)
2198 /* Produces a ALT_SPIS_TXOICR_TXOICR register field value suitable for setting the register. */
2199 #define ALT_SPIS_TXOICR_TXOICR_SET(value) (((value) << 0) & 0x00000001)
2200 
2201 #ifndef __ASSEMBLY__
2202 /*
2203  * WARNING: The C register and register group struct declarations are provided for
2204  * convenience and illustrative purposes. They should, however, be used with
2205  * caution as the C language standard provides no guarantees about the alignment or
2206  * atomicity of device memory accesses. The recommended practice for writing
2207  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2208  * alt_write_word() functions.
2209  *
2210  * The struct declaration for register ALT_SPIS_TXOICR.
2211  */
2212 struct ALT_SPIS_TXOICR_s
2213 {
2214  const uint32_t txoicr : 1; /* Clear Transmit FIFO Overflow Interrupt */
2215  uint32_t : 31; /* *UNDEFINED* */
2216 };
2217 
2218 /* The typedef declaration for register ALT_SPIS_TXOICR. */
2219 typedef volatile struct ALT_SPIS_TXOICR_s ALT_SPIS_TXOICR_t;
2220 #endif /* __ASSEMBLY__ */
2221 
2222 /* The byte offset of the ALT_SPIS_TXOICR register from the beginning of the component. */
2223 #define ALT_SPIS_TXOICR_OFST 0x38
2224 /* The address of the ALT_SPIS_TXOICR register. */
2225 #define ALT_SPIS_TXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXOICR_OFST))
2226 
2227 /*
2228  * Register : Receive FIFO Overflow Interrupt Clear Register - rxoicr
2229  *
2230  * Register Layout
2231  *
2232  * Bits | Access | Reset | Description
2233  * :-------|:-------|:------|:--------------------------------------
2234  * [0] | R | 0x0 | Clear Receive FIFO Overflow Interrupt
2235  * [31:1] | ??? | 0x0 | *UNDEFINED*
2236  *
2237  */
2238 /*
2239  * Field : Clear Receive FIFO Overflow Interrupt - rxoicr
2240  *
2241  * This register reflects the status of the interrupt. A read from this register
2242  * clears the ssi_rxo_intr interrupt; writing has no effect.
2243  *
2244  * Field Access Macros:
2245  *
2246  */
2247 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RXOICR_RXOICR register field. */
2248 #define ALT_SPIS_RXOICR_RXOICR_LSB 0
2249 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RXOICR_RXOICR register field. */
2250 #define ALT_SPIS_RXOICR_RXOICR_MSB 0
2251 /* The width in bits of the ALT_SPIS_RXOICR_RXOICR register field. */
2252 #define ALT_SPIS_RXOICR_RXOICR_WIDTH 1
2253 /* The mask used to set the ALT_SPIS_RXOICR_RXOICR register field value. */
2254 #define ALT_SPIS_RXOICR_RXOICR_SET_MSK 0x00000001
2255 /* The mask used to clear the ALT_SPIS_RXOICR_RXOICR register field value. */
2256 #define ALT_SPIS_RXOICR_RXOICR_CLR_MSK 0xfffffffe
2257 /* The reset value of the ALT_SPIS_RXOICR_RXOICR register field. */
2258 #define ALT_SPIS_RXOICR_RXOICR_RESET 0x0
2259 /* Extracts the ALT_SPIS_RXOICR_RXOICR field value from a register. */
2260 #define ALT_SPIS_RXOICR_RXOICR_GET(value) (((value) & 0x00000001) >> 0)
2261 /* Produces a ALT_SPIS_RXOICR_RXOICR register field value suitable for setting the register. */
2262 #define ALT_SPIS_RXOICR_RXOICR_SET(value) (((value) << 0) & 0x00000001)
2263 
2264 #ifndef __ASSEMBLY__
2265 /*
2266  * WARNING: The C register and register group struct declarations are provided for
2267  * convenience and illustrative purposes. They should, however, be used with
2268  * caution as the C language standard provides no guarantees about the alignment or
2269  * atomicity of device memory accesses. The recommended practice for writing
2270  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2271  * alt_write_word() functions.
2272  *
2273  * The struct declaration for register ALT_SPIS_RXOICR.
2274  */
2275 struct ALT_SPIS_RXOICR_s
2276 {
2277  const uint32_t rxoicr : 1; /* Clear Receive FIFO Overflow Interrupt */
2278  uint32_t : 31; /* *UNDEFINED* */
2279 };
2280 
2281 /* The typedef declaration for register ALT_SPIS_RXOICR. */
2282 typedef volatile struct ALT_SPIS_RXOICR_s ALT_SPIS_RXOICR_t;
2283 #endif /* __ASSEMBLY__ */
2284 
2285 /* The byte offset of the ALT_SPIS_RXOICR register from the beginning of the component. */
2286 #define ALT_SPIS_RXOICR_OFST 0x3c
2287 /* The address of the ALT_SPIS_RXOICR register. */
2288 #define ALT_SPIS_RXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXOICR_OFST))
2289 
2290 /*
2291  * Register : Receive FIFO Underflow Interrupt Clear Register - rxuicr
2292  *
2293  * Register Layout
2294  *
2295  * Bits | Access | Reset | Description
2296  * :-------|:-------|:------|:---------------------------------------
2297  * [0] | R | 0x0 | Clear Receive FIFO Underflow Interrupt
2298  * [31:1] | ??? | 0x0 | *UNDEFINED*
2299  *
2300  */
2301 /*
2302  * Field : Clear Receive FIFO Underflow Interrupt - rxuicr
2303  *
2304  * This register reflects the status of the interrupt. A read from this register
2305  * clears the ssi_rxu_intr interrupt; writing has no effect.
2306  *
2307  * Field Access Macros:
2308  *
2309  */
2310 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RXUICR_RXUICR register field. */
2311 #define ALT_SPIS_RXUICR_RXUICR_LSB 0
2312 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RXUICR_RXUICR register field. */
2313 #define ALT_SPIS_RXUICR_RXUICR_MSB 0
2314 /* The width in bits of the ALT_SPIS_RXUICR_RXUICR register field. */
2315 #define ALT_SPIS_RXUICR_RXUICR_WIDTH 1
2316 /* The mask used to set the ALT_SPIS_RXUICR_RXUICR register field value. */
2317 #define ALT_SPIS_RXUICR_RXUICR_SET_MSK 0x00000001
2318 /* The mask used to clear the ALT_SPIS_RXUICR_RXUICR register field value. */
2319 #define ALT_SPIS_RXUICR_RXUICR_CLR_MSK 0xfffffffe
2320 /* The reset value of the ALT_SPIS_RXUICR_RXUICR register field. */
2321 #define ALT_SPIS_RXUICR_RXUICR_RESET 0x0
2322 /* Extracts the ALT_SPIS_RXUICR_RXUICR field value from a register. */
2323 #define ALT_SPIS_RXUICR_RXUICR_GET(value) (((value) & 0x00000001) >> 0)
2324 /* Produces a ALT_SPIS_RXUICR_RXUICR register field value suitable for setting the register. */
2325 #define ALT_SPIS_RXUICR_RXUICR_SET(value) (((value) << 0) & 0x00000001)
2326 
2327 #ifndef __ASSEMBLY__
2328 /*
2329  * WARNING: The C register and register group struct declarations are provided for
2330  * convenience and illustrative purposes. They should, however, be used with
2331  * caution as the C language standard provides no guarantees about the alignment or
2332  * atomicity of device memory accesses. The recommended practice for writing
2333  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2334  * alt_write_word() functions.
2335  *
2336  * The struct declaration for register ALT_SPIS_RXUICR.
2337  */
2338 struct ALT_SPIS_RXUICR_s
2339 {
2340  const uint32_t rxuicr : 1; /* Clear Receive FIFO Underflow Interrupt */
2341  uint32_t : 31; /* *UNDEFINED* */
2342 };
2343 
2344 /* The typedef declaration for register ALT_SPIS_RXUICR. */
2345 typedef volatile struct ALT_SPIS_RXUICR_s ALT_SPIS_RXUICR_t;
2346 #endif /* __ASSEMBLY__ */
2347 
2348 /* The byte offset of the ALT_SPIS_RXUICR register from the beginning of the component. */
2349 #define ALT_SPIS_RXUICR_OFST 0x40
2350 /* The address of the ALT_SPIS_RXUICR register. */
2351 #define ALT_SPIS_RXUICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXUICR_OFST))
2352 
2353 /*
2354  * Register : Interrupt Clear Register - icr
2355  *
2356  * Register Layout
2357  *
2358  * Bits | Access | Reset | Description
2359  * :-------|:-------|:------|:-----------------
2360  * [0] | R | 0x0 | Clear Interrupts
2361  * [31:1] | ??? | 0x0 | *UNDEFINED*
2362  *
2363  */
2364 /*
2365  * Field : Clear Interrupts - icr
2366  *
2367  * This register is set if any of the interrupts below are active. A read clears
2368  * the ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and the ssi_mst_intr interrupts.
2369  * Writing to this register has no effect.
2370  *
2371  * Field Access Macros:
2372  *
2373  */
2374 /* The Least Significant Bit (LSB) position of the ALT_SPIS_ICR_ICR register field. */
2375 #define ALT_SPIS_ICR_ICR_LSB 0
2376 /* The Most Significant Bit (MSB) position of the ALT_SPIS_ICR_ICR register field. */
2377 #define ALT_SPIS_ICR_ICR_MSB 0
2378 /* The width in bits of the ALT_SPIS_ICR_ICR register field. */
2379 #define ALT_SPIS_ICR_ICR_WIDTH 1
2380 /* The mask used to set the ALT_SPIS_ICR_ICR register field value. */
2381 #define ALT_SPIS_ICR_ICR_SET_MSK 0x00000001
2382 /* The mask used to clear the ALT_SPIS_ICR_ICR register field value. */
2383 #define ALT_SPIS_ICR_ICR_CLR_MSK 0xfffffffe
2384 /* The reset value of the ALT_SPIS_ICR_ICR register field. */
2385 #define ALT_SPIS_ICR_ICR_RESET 0x0
2386 /* Extracts the ALT_SPIS_ICR_ICR field value from a register. */
2387 #define ALT_SPIS_ICR_ICR_GET(value) (((value) & 0x00000001) >> 0)
2388 /* Produces a ALT_SPIS_ICR_ICR register field value suitable for setting the register. */
2389 #define ALT_SPIS_ICR_ICR_SET(value) (((value) << 0) & 0x00000001)
2390 
2391 #ifndef __ASSEMBLY__
2392 /*
2393  * WARNING: The C register and register group struct declarations are provided for
2394  * convenience and illustrative purposes. They should, however, be used with
2395  * caution as the C language standard provides no guarantees about the alignment or
2396  * atomicity of device memory accesses. The recommended practice for writing
2397  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2398  * alt_write_word() functions.
2399  *
2400  * The struct declaration for register ALT_SPIS_ICR.
2401  */
2402 struct ALT_SPIS_ICR_s
2403 {
2404  const uint32_t icr : 1; /* Clear Interrupts */
2405  uint32_t : 31; /* *UNDEFINED* */
2406 };
2407 
2408 /* The typedef declaration for register ALT_SPIS_ICR. */
2409 typedef volatile struct ALT_SPIS_ICR_s ALT_SPIS_ICR_t;
2410 #endif /* __ASSEMBLY__ */
2411 
2412 /* The byte offset of the ALT_SPIS_ICR register from the beginning of the component. */
2413 #define ALT_SPIS_ICR_OFST 0x48
2414 /* The address of the ALT_SPIS_ICR register. */
2415 #define ALT_SPIS_ICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_ICR_OFST))
2416 
2417 /*
2418  * Register : DMA Control Register - dmacr
2419  *
2420  * The register is used to enable the DMA Controller interface operation.
2421  *
2422  * Register Layout
2423  *
2424  * Bits | Access | Reset | Description
2425  * :-------|:-------|:------|:--------------------
2426  * [0] | RW | 0x0 | Receive DMA Enable
2427  * [1] | RW | 0x0 | Transmit DMA Enable
2428  * [31:2] | ??? | 0x0 | *UNDEFINED*
2429  *
2430  */
2431 /*
2432  * Field : Receive DMA Enable - rdmae
2433  *
2434  * This bit enables/disables the receive FIFO DMA channel
2435  *
2436  * Field Enumeration Values:
2437  *
2438  * Enum | Value | Description
2439  * :----------------------------|:------|:---------------------
2440  * ALT_SPIS_DMACR_RDMAE_E_DISD | 0x0 | Receive DMA disabled
2441  * ALT_SPIS_DMACR_RDMAE_E_END | 0x1 | Receive DMA enabled
2442  *
2443  * Field Access Macros:
2444  *
2445  */
2446 /*
2447  * Enumerated value for register field ALT_SPIS_DMACR_RDMAE
2448  *
2449  * Receive DMA disabled
2450  */
2451 #define ALT_SPIS_DMACR_RDMAE_E_DISD 0x0
2452 /*
2453  * Enumerated value for register field ALT_SPIS_DMACR_RDMAE
2454  *
2455  * Receive DMA enabled
2456  */
2457 #define ALT_SPIS_DMACR_RDMAE_E_END 0x1
2458 
2459 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DMACR_RDMAE register field. */
2460 #define ALT_SPIS_DMACR_RDMAE_LSB 0
2461 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DMACR_RDMAE register field. */
2462 #define ALT_SPIS_DMACR_RDMAE_MSB 0
2463 /* The width in bits of the ALT_SPIS_DMACR_RDMAE register field. */
2464 #define ALT_SPIS_DMACR_RDMAE_WIDTH 1
2465 /* The mask used to set the ALT_SPIS_DMACR_RDMAE register field value. */
2466 #define ALT_SPIS_DMACR_RDMAE_SET_MSK 0x00000001
2467 /* The mask used to clear the ALT_SPIS_DMACR_RDMAE register field value. */
2468 #define ALT_SPIS_DMACR_RDMAE_CLR_MSK 0xfffffffe
2469 /* The reset value of the ALT_SPIS_DMACR_RDMAE register field. */
2470 #define ALT_SPIS_DMACR_RDMAE_RESET 0x0
2471 /* Extracts the ALT_SPIS_DMACR_RDMAE field value from a register. */
2472 #define ALT_SPIS_DMACR_RDMAE_GET(value) (((value) & 0x00000001) >> 0)
2473 /* Produces a ALT_SPIS_DMACR_RDMAE register field value suitable for setting the register. */
2474 #define ALT_SPIS_DMACR_RDMAE_SET(value) (((value) << 0) & 0x00000001)
2475 
2476 /*
2477  * Field : Transmit DMA Enable - tdmae
2478  *
2479  * This bit enables/disables the transmit FIFO DMA channel.
2480  *
2481  * Field Enumeration Values:
2482  *
2483  * Enum | Value | Description
2484  * :----------------------------|:------|:----------------------
2485  * ALT_SPIS_DMACR_TDMAE_E_DISD | 0x0 | Transmit DMA disabled
2486  * ALT_SPIS_DMACR_TDMAE_E_END | 0x1 | Transmit DMA enabled
2487  *
2488  * Field Access Macros:
2489  *
2490  */
2491 /*
2492  * Enumerated value for register field ALT_SPIS_DMACR_TDMAE
2493  *
2494  * Transmit DMA disabled
2495  */
2496 #define ALT_SPIS_DMACR_TDMAE_E_DISD 0x0
2497 /*
2498  * Enumerated value for register field ALT_SPIS_DMACR_TDMAE
2499  *
2500  * Transmit DMA enabled
2501  */
2502 #define ALT_SPIS_DMACR_TDMAE_E_END 0x1
2503 
2504 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DMACR_TDMAE register field. */
2505 #define ALT_SPIS_DMACR_TDMAE_LSB 1
2506 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DMACR_TDMAE register field. */
2507 #define ALT_SPIS_DMACR_TDMAE_MSB 1
2508 /* The width in bits of the ALT_SPIS_DMACR_TDMAE register field. */
2509 #define ALT_SPIS_DMACR_TDMAE_WIDTH 1
2510 /* The mask used to set the ALT_SPIS_DMACR_TDMAE register field value. */
2511 #define ALT_SPIS_DMACR_TDMAE_SET_MSK 0x00000002
2512 /* The mask used to clear the ALT_SPIS_DMACR_TDMAE register field value. */
2513 #define ALT_SPIS_DMACR_TDMAE_CLR_MSK 0xfffffffd
2514 /* The reset value of the ALT_SPIS_DMACR_TDMAE register field. */
2515 #define ALT_SPIS_DMACR_TDMAE_RESET 0x0
2516 /* Extracts the ALT_SPIS_DMACR_TDMAE field value from a register. */
2517 #define ALT_SPIS_DMACR_TDMAE_GET(value) (((value) & 0x00000002) >> 1)
2518 /* Produces a ALT_SPIS_DMACR_TDMAE register field value suitable for setting the register. */
2519 #define ALT_SPIS_DMACR_TDMAE_SET(value) (((value) << 1) & 0x00000002)
2520 
2521 #ifndef __ASSEMBLY__
2522 /*
2523  * WARNING: The C register and register group struct declarations are provided for
2524  * convenience and illustrative purposes. They should, however, be used with
2525  * caution as the C language standard provides no guarantees about the alignment or
2526  * atomicity of device memory accesses. The recommended practice for writing
2527  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2528  * alt_write_word() functions.
2529  *
2530  * The struct declaration for register ALT_SPIS_DMACR.
2531  */
2532 struct ALT_SPIS_DMACR_s
2533 {
2534  uint32_t rdmae : 1; /* Receive DMA Enable */
2535  uint32_t tdmae : 1; /* Transmit DMA Enable */
2536  uint32_t : 30; /* *UNDEFINED* */
2537 };
2538 
2539 /* The typedef declaration for register ALT_SPIS_DMACR. */
2540 typedef volatile struct ALT_SPIS_DMACR_s ALT_SPIS_DMACR_t;
2541 #endif /* __ASSEMBLY__ */
2542 
2543 /* The byte offset of the ALT_SPIS_DMACR register from the beginning of the component. */
2544 #define ALT_SPIS_DMACR_OFST 0x4c
2545 /* The address of the ALT_SPIS_DMACR register. */
2546 #define ALT_SPIS_DMACR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMACR_OFST))
2547 
2548 /*
2549  * Register : DMA Transmit Data Level Regoster - dmatdlr
2550  *
2551  * Controls DMA Transmit FIFO Threshold
2552  *
2553  * Register Layout
2554  *
2555  * Bits | Access | Reset | Description
2556  * :-------|:-------|:------|:--------------------
2557  * [7:0] | RW | 0x0 | Transmit Data Level
2558  * [31:8] | ??? | 0x0 | *UNDEFINED*
2559  *
2560  */
2561 /*
2562  * Field : Transmit Data Level - dmatdl
2563  *
2564  * This bit field controls the level at which a DMA request is made by the transmit
2565  * logic. It is equal to the watermark level; that is, the dma_tx_req signal is
2566  * generated when the number of valid data entries in the transmit FIFO is equal to
2567  * or below this field value, and TDMAE = 1.
2568  *
2569  * Field Access Macros:
2570  *
2571  */
2572 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DMATDLR_DMATDL register field. */
2573 #define ALT_SPIS_DMATDLR_DMATDL_LSB 0
2574 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DMATDLR_DMATDL register field. */
2575 #define ALT_SPIS_DMATDLR_DMATDL_MSB 7
2576 /* The width in bits of the ALT_SPIS_DMATDLR_DMATDL register field. */
2577 #define ALT_SPIS_DMATDLR_DMATDL_WIDTH 8
2578 /* The mask used to set the ALT_SPIS_DMATDLR_DMATDL register field value. */
2579 #define ALT_SPIS_DMATDLR_DMATDL_SET_MSK 0x000000ff
2580 /* The mask used to clear the ALT_SPIS_DMATDLR_DMATDL register field value. */
2581 #define ALT_SPIS_DMATDLR_DMATDL_CLR_MSK 0xffffff00
2582 /* The reset value of the ALT_SPIS_DMATDLR_DMATDL register field. */
2583 #define ALT_SPIS_DMATDLR_DMATDL_RESET 0x0
2584 /* Extracts the ALT_SPIS_DMATDLR_DMATDL field value from a register. */
2585 #define ALT_SPIS_DMATDLR_DMATDL_GET(value) (((value) & 0x000000ff) >> 0)
2586 /* Produces a ALT_SPIS_DMATDLR_DMATDL register field value suitable for setting the register. */
2587 #define ALT_SPIS_DMATDLR_DMATDL_SET(value) (((value) << 0) & 0x000000ff)
2588 
2589 #ifndef __ASSEMBLY__
2590 /*
2591  * WARNING: The C register and register group struct declarations are provided for
2592  * convenience and illustrative purposes. They should, however, be used with
2593  * caution as the C language standard provides no guarantees about the alignment or
2594  * atomicity of device memory accesses. The recommended practice for writing
2595  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2596  * alt_write_word() functions.
2597  *
2598  * The struct declaration for register ALT_SPIS_DMATDLR.
2599  */
2600 struct ALT_SPIS_DMATDLR_s
2601 {
2602  uint32_t dmatdl : 8; /* Transmit Data Level */
2603  uint32_t : 24; /* *UNDEFINED* */
2604 };
2605 
2606 /* The typedef declaration for register ALT_SPIS_DMATDLR. */
2607 typedef volatile struct ALT_SPIS_DMATDLR_s ALT_SPIS_DMATDLR_t;
2608 #endif /* __ASSEMBLY__ */
2609 
2610 /* The byte offset of the ALT_SPIS_DMATDLR register from the beginning of the component. */
2611 #define ALT_SPIS_DMATDLR_OFST 0x50
2612 /* The address of the ALT_SPIS_DMATDLR register. */
2613 #define ALT_SPIS_DMATDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMATDLR_OFST))
2614 
2615 /*
2616  * Register : DMA Receive Data Level Register - dmardlr
2617  *
2618  * Controls DMA Receive FIFO Threshold
2619  *
2620  * Register Layout
2621  *
2622  * Bits | Access | Reset | Description
2623  * :-------|:-------|:------|:-------------------
2624  * [7:0] | RW | 0x0 | Receive Data Level
2625  * [31:8] | ??? | 0x0 | *UNDEFINED*
2626  *
2627  */
2628 /*
2629  * Field : Receive Data Level - dmardl
2630  *
2631  * This bit field controls the level at which a DMA request is made by the receive
2632  * logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the
2633  * number of valid data entries in the receive FIFO is equal to or above this field
2634  * value + 1, and RDMAE=1.
2635  *
2636  * Field Access Macros:
2637  *
2638  */
2639 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DMARDLR_DMARDL register field. */
2640 #define ALT_SPIS_DMARDLR_DMARDL_LSB 0
2641 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DMARDLR_DMARDL register field. */
2642 #define ALT_SPIS_DMARDLR_DMARDL_MSB 7
2643 /* The width in bits of the ALT_SPIS_DMARDLR_DMARDL register field. */
2644 #define ALT_SPIS_DMARDLR_DMARDL_WIDTH 8
2645 /* The mask used to set the ALT_SPIS_DMARDLR_DMARDL register field value. */
2646 #define ALT_SPIS_DMARDLR_DMARDL_SET_MSK 0x000000ff
2647 /* The mask used to clear the ALT_SPIS_DMARDLR_DMARDL register field value. */
2648 #define ALT_SPIS_DMARDLR_DMARDL_CLR_MSK 0xffffff00
2649 /* The reset value of the ALT_SPIS_DMARDLR_DMARDL register field. */
2650 #define ALT_SPIS_DMARDLR_DMARDL_RESET 0x0
2651 /* Extracts the ALT_SPIS_DMARDLR_DMARDL field value from a register. */
2652 #define ALT_SPIS_DMARDLR_DMARDL_GET(value) (((value) & 0x000000ff) >> 0)
2653 /* Produces a ALT_SPIS_DMARDLR_DMARDL register field value suitable for setting the register. */
2654 #define ALT_SPIS_DMARDLR_DMARDL_SET(value) (((value) << 0) & 0x000000ff)
2655 
2656 #ifndef __ASSEMBLY__
2657 /*
2658  * WARNING: The C register and register group struct declarations are provided for
2659  * convenience and illustrative purposes. They should, however, be used with
2660  * caution as the C language standard provides no guarantees about the alignment or
2661  * atomicity of device memory accesses. The recommended practice for writing
2662  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2663  * alt_write_word() functions.
2664  *
2665  * The struct declaration for register ALT_SPIS_DMARDLR.
2666  */
2667 struct ALT_SPIS_DMARDLR_s
2668 {
2669  uint32_t dmardl : 8; /* Receive Data Level */
2670  uint32_t : 24; /* *UNDEFINED* */
2671 };
2672 
2673 /* The typedef declaration for register ALT_SPIS_DMARDLR. */
2674 typedef volatile struct ALT_SPIS_DMARDLR_s ALT_SPIS_DMARDLR_t;
2675 #endif /* __ASSEMBLY__ */
2676 
2677 /* The byte offset of the ALT_SPIS_DMARDLR register from the beginning of the component. */
2678 #define ALT_SPIS_DMARDLR_OFST 0x54
2679 /* The address of the ALT_SPIS_DMARDLR register. */
2680 #define ALT_SPIS_DMARDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMARDLR_OFST))
2681 
2682 /*
2683  * Register : Identification Register - idr
2684  *
2685  * This register stores a peripheral identification code
2686  *
2687  * Register Layout
2688  *
2689  * Bits | Access | Reset | Description
2690  * :-------|:-------|:----------|:--------------------
2691  * [31:0] | R | 0x5510005 | Identification Code
2692  *
2693  */
2694 /*
2695  * Field : Identification Code - idr
2696  *
2697  * This filed contains the peripherals identification code, 0x05510005.
2698  *
2699  * Field Access Macros:
2700  *
2701  */
2702 /* The Least Significant Bit (LSB) position of the ALT_SPIS_IDR_IDR register field. */
2703 #define ALT_SPIS_IDR_IDR_LSB 0
2704 /* The Most Significant Bit (MSB) position of the ALT_SPIS_IDR_IDR register field. */
2705 #define ALT_SPIS_IDR_IDR_MSB 31
2706 /* The width in bits of the ALT_SPIS_IDR_IDR register field. */
2707 #define ALT_SPIS_IDR_IDR_WIDTH 32
2708 /* The mask used to set the ALT_SPIS_IDR_IDR register field value. */
2709 #define ALT_SPIS_IDR_IDR_SET_MSK 0xffffffff
2710 /* The mask used to clear the ALT_SPIS_IDR_IDR register field value. */
2711 #define ALT_SPIS_IDR_IDR_CLR_MSK 0x00000000
2712 /* The reset value of the ALT_SPIS_IDR_IDR register field. */
2713 #define ALT_SPIS_IDR_IDR_RESET 0x5510005
2714 /* Extracts the ALT_SPIS_IDR_IDR field value from a register. */
2715 #define ALT_SPIS_IDR_IDR_GET(value) (((value) & 0xffffffff) >> 0)
2716 /* Produces a ALT_SPIS_IDR_IDR register field value suitable for setting the register. */
2717 #define ALT_SPIS_IDR_IDR_SET(value) (((value) << 0) & 0xffffffff)
2718 
2719 #ifndef __ASSEMBLY__
2720 /*
2721  * WARNING: The C register and register group struct declarations are provided for
2722  * convenience and illustrative purposes. They should, however, be used with
2723  * caution as the C language standard provides no guarantees about the alignment or
2724  * atomicity of device memory accesses. The recommended practice for writing
2725  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2726  * alt_write_word() functions.
2727  *
2728  * The struct declaration for register ALT_SPIS_IDR.
2729  */
2730 struct ALT_SPIS_IDR_s
2731 {
2732  const uint32_t idr : 32; /* Identification Code */
2733 };
2734 
2735 /* The typedef declaration for register ALT_SPIS_IDR. */
2736 typedef volatile struct ALT_SPIS_IDR_s ALT_SPIS_IDR_t;
2737 #endif /* __ASSEMBLY__ */
2738 
2739 /* The byte offset of the ALT_SPIS_IDR register from the beginning of the component. */
2740 #define ALT_SPIS_IDR_OFST 0x58
2741 /* The address of the ALT_SPIS_IDR register. */
2742 #define ALT_SPIS_IDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_IDR_OFST))
2743 
2744 /*
2745  * Register : Component Version Register - spi_version_id
2746  *
2747  * This read-only register stores the specific SPI Slave component version.
2748  *
2749  * Register Layout
2750  *
2751  * Bits | Access | Reset | Description
2752  * :-------|:-------|:-----------|:------------------
2753  * [31:0] | RW | 0x3332302a | Component Version
2754  *
2755  */
2756 /*
2757  * Field : Component Version - spi_version_id
2758  *
2759  * Contains the hex representation of the Synopsys component version. Consists of
2760  * ASCII value for each number in the version.
2761  *
2762  * Field Access Macros:
2763  *
2764  */
2765 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SPI_VER_ID_SPI_VER_ID register field. */
2766 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_LSB 0
2767 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SPI_VER_ID_SPI_VER_ID register field. */
2768 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_MSB 31
2769 /* The width in bits of the ALT_SPIS_SPI_VER_ID_SPI_VER_ID register field. */
2770 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_WIDTH 32
2771 /* The mask used to set the ALT_SPIS_SPI_VER_ID_SPI_VER_ID register field value. */
2772 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_SET_MSK 0xffffffff
2773 /* The mask used to clear the ALT_SPIS_SPI_VER_ID_SPI_VER_ID register field value. */
2774 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_CLR_MSK 0x00000000
2775 /* The reset value of the ALT_SPIS_SPI_VER_ID_SPI_VER_ID register field. */
2776 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_RESET 0x3332302a
2777 /* Extracts the ALT_SPIS_SPI_VER_ID_SPI_VER_ID field value from a register. */
2778 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_GET(value) (((value) & 0xffffffff) >> 0)
2779 /* Produces a ALT_SPIS_SPI_VER_ID_SPI_VER_ID register field value suitable for setting the register. */
2780 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_SET(value) (((value) << 0) & 0xffffffff)
2781 
2782 #ifndef __ASSEMBLY__
2783 /*
2784  * WARNING: The C register and register group struct declarations are provided for
2785  * convenience and illustrative purposes. They should, however, be used with
2786  * caution as the C language standard provides no guarantees about the alignment or
2787  * atomicity of device memory accesses. The recommended practice for writing
2788  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2789  * alt_write_word() functions.
2790  *
2791  * The struct declaration for register ALT_SPIS_SPI_VER_ID.
2792  */
2793 struct ALT_SPIS_SPI_VER_ID_s
2794 {
2795  uint32_t spi_version_id : 32; /* Component Version */
2796 };
2797 
2798 /* The typedef declaration for register ALT_SPIS_SPI_VER_ID. */
2799 typedef volatile struct ALT_SPIS_SPI_VER_ID_s ALT_SPIS_SPI_VER_ID_t;
2800 #endif /* __ASSEMBLY__ */
2801 
2802 /* The byte offset of the ALT_SPIS_SPI_VER_ID register from the beginning of the component. */
2803 #define ALT_SPIS_SPI_VER_ID_OFST 0x5c
2804 /* The address of the ALT_SPIS_SPI_VER_ID register. */
2805 #define ALT_SPIS_SPI_VER_ID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SPI_VER_ID_OFST))
2806 
2807 /*
2808  * Register : Data Register - dr
2809  *
2810  * The data register is a 16-bit read/write buffer for the transmit/receive FIFOs.
2811  * When the register is read, data in the receive FIFO buffer is accessed. When it
2812  * is written to, data are moved into the transmit FIFO buffer; a write can occur
2813  * only when SPI_EN = 1. FIFOs are reset when SPI_EN = 0.
2814  *
2815  * Register Layout
2816  *
2817  * Bits | Access | Reset | Description
2818  * :--------|:-------|:------|:------------
2819  * [15:0] | RW | 0x0 | Data
2820  * [31:16] | ??? | 0x0 | *UNDEFINED*
2821  *
2822  */
2823 /*
2824  * Field : Data - dr
2825  *
2826  * When writing to this register, you must right-justify the data. Read data are
2827  * automatically right-justified.
2828  *
2829  * Read = Receive FIFO buffer
2830  *
2831  * Write = Transmit FIFO buffer
2832  *
2833  * Field Access Macros:
2834  *
2835  */
2836 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR_DR register field. */
2837 #define ALT_SPIS_DR_DR_LSB 0
2838 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR_DR register field. */
2839 #define ALT_SPIS_DR_DR_MSB 15
2840 /* The width in bits of the ALT_SPIS_DR_DR register field. */
2841 #define ALT_SPIS_DR_DR_WIDTH 16
2842 /* The mask used to set the ALT_SPIS_DR_DR register field value. */
2843 #define ALT_SPIS_DR_DR_SET_MSK 0x0000ffff
2844 /* The mask used to clear the ALT_SPIS_DR_DR register field value. */
2845 #define ALT_SPIS_DR_DR_CLR_MSK 0xffff0000
2846 /* The reset value of the ALT_SPIS_DR_DR register field. */
2847 #define ALT_SPIS_DR_DR_RESET 0x0
2848 /* Extracts the ALT_SPIS_DR_DR field value from a register. */
2849 #define ALT_SPIS_DR_DR_GET(value) (((value) & 0x0000ffff) >> 0)
2850 /* Produces a ALT_SPIS_DR_DR register field value suitable for setting the register. */
2851 #define ALT_SPIS_DR_DR_SET(value) (((value) << 0) & 0x0000ffff)
2852 
2853 #ifndef __ASSEMBLY__
2854 /*
2855  * WARNING: The C register and register group struct declarations are provided for
2856  * convenience and illustrative purposes. They should, however, be used with
2857  * caution as the C language standard provides no guarantees about the alignment or
2858  * atomicity of device memory accesses. The recommended practice for writing
2859  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2860  * alt_write_word() functions.
2861  *
2862  * The struct declaration for register ALT_SPIS_DR.
2863  */
2864 struct ALT_SPIS_DR_s
2865 {
2866  uint32_t dr : 16; /* Data */
2867  uint32_t : 16; /* *UNDEFINED* */
2868 };
2869 
2870 /* The typedef declaration for register ALT_SPIS_DR. */
2871 typedef volatile struct ALT_SPIS_DR_s ALT_SPIS_DR_t;
2872 #endif /* __ASSEMBLY__ */
2873 
2874 /* The byte offset of the ALT_SPIS_DR register from the beginning of the component. */
2875 #define ALT_SPIS_DR_OFST 0x60
2876 /* The address of the ALT_SPIS_DR register. */
2877 #define ALT_SPIS_DR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR_OFST))
2878 
2879 #ifndef __ASSEMBLY__
2880 /*
2881  * WARNING: The C register and register group struct declarations are provided for
2882  * convenience and illustrative purposes. They should, however, be used with
2883  * caution as the C language standard provides no guarantees about the alignment or
2884  * atomicity of device memory accesses. The recommended practice for writing
2885  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2886  * alt_write_word() functions.
2887  *
2888  * The struct declaration for register group ALT_SPIS.
2889  */
2890 struct ALT_SPIS_s
2891 {
2892  ALT_SPIS_CTLR0_t ctrlr0; /* ALT_SPIS_CTLR0 */
2893  volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */
2894  ALT_SPIS_SPIENR_t spienr; /* ALT_SPIS_SPIENR */
2895  ALT_SPIS_MWCR_t mwcr; /* ALT_SPIS_MWCR */
2896  volatile uint32_t _pad_0x10_0x17[2]; /* *UNDEFINED* */
2897  ALT_SPIS_TXFTLR_t txftlr; /* ALT_SPIS_TXFTLR */
2898  ALT_SPIS_RXFTLR_t rxftlr; /* ALT_SPIS_RXFTLR */
2899  ALT_SPIS_TXFLR_t txflr; /* ALT_SPIS_TXFLR */
2900  ALT_SPIS_RXFLR_t rxflr; /* ALT_SPIS_RXFLR */
2901  ALT_SPIS_SR_t sr; /* ALT_SPIS_SR */
2902  ALT_SPIS_IMR_t imr; /* ALT_SPIS_IMR */
2903  ALT_SPIS_ISR_t isr; /* ALT_SPIS_ISR */
2904  ALT_SPIS_RISR_t risr; /* ALT_SPIS_RISR */
2905  ALT_SPIS_TXOICR_t txoicr; /* ALT_SPIS_TXOICR */
2906  ALT_SPIS_RXOICR_t rxoicr; /* ALT_SPIS_RXOICR */
2907  ALT_SPIS_RXUICR_t rxuicr; /* ALT_SPIS_RXUICR */
2908  volatile uint32_t _pad_0x44_0x47; /* *UNDEFINED* */
2909  ALT_SPIS_ICR_t icr; /* ALT_SPIS_ICR */
2910  ALT_SPIS_DMACR_t dmacr; /* ALT_SPIS_DMACR */
2911  ALT_SPIS_DMATDLR_t dmatdlr; /* ALT_SPIS_DMATDLR */
2912  ALT_SPIS_DMARDLR_t dmardlr; /* ALT_SPIS_DMARDLR */
2913  ALT_SPIS_IDR_t idr; /* ALT_SPIS_IDR */
2914  ALT_SPIS_SPI_VER_ID_t spi_version_id; /* ALT_SPIS_SPI_VER_ID */
2915  ALT_SPIS_DR_t dr; /* ALT_SPIS_DR */
2916  volatile uint32_t _pad_0x64_0x80[7]; /* *UNDEFINED* */
2917 };
2918 
2919 /* The typedef declaration for register group ALT_SPIS. */
2920 typedef volatile struct ALT_SPIS_s ALT_SPIS_t;
2921 /* The struct declaration for the raw register contents of register group ALT_SPIS. */
2922 struct ALT_SPIS_raw_s
2923 {
2924  volatile uint32_t ctrlr0; /* ALT_SPIS_CTLR0 */
2925  uint32_t _pad_0x4_0x7; /* *UNDEFINED* */
2926  volatile uint32_t spienr; /* ALT_SPIS_SPIENR */
2927  volatile uint32_t mwcr; /* ALT_SPIS_MWCR */
2928  uint32_t _pad_0x10_0x17[2]; /* *UNDEFINED* */
2929  volatile uint32_t txftlr; /* ALT_SPIS_TXFTLR */
2930  volatile uint32_t rxftlr; /* ALT_SPIS_RXFTLR */
2931  volatile uint32_t txflr; /* ALT_SPIS_TXFLR */
2932  volatile uint32_t rxflr; /* ALT_SPIS_RXFLR */
2933  volatile uint32_t sr; /* ALT_SPIS_SR */
2934  volatile uint32_t imr; /* ALT_SPIS_IMR */
2935  volatile uint32_t isr; /* ALT_SPIS_ISR */
2936  volatile uint32_t risr; /* ALT_SPIS_RISR */
2937  volatile uint32_t txoicr; /* ALT_SPIS_TXOICR */
2938  volatile uint32_t rxoicr; /* ALT_SPIS_RXOICR */
2939  volatile uint32_t rxuicr; /* ALT_SPIS_RXUICR */
2940  uint32_t _pad_0x44_0x47; /* *UNDEFINED* */
2941  volatile uint32_t icr; /* ALT_SPIS_ICR */
2942  volatile uint32_t dmacr; /* ALT_SPIS_DMACR */
2943  volatile uint32_t dmatdlr; /* ALT_SPIS_DMATDLR */
2944  volatile uint32_t dmardlr; /* ALT_SPIS_DMARDLR */
2945  volatile uint32_t idr; /* ALT_SPIS_IDR */
2946  volatile uint32_t spi_version_id; /* ALT_SPIS_SPI_VER_ID */
2947  volatile uint32_t dr; /* ALT_SPIS_DR */
2948  uint32_t _pad_0x64_0x80[7]; /* *UNDEFINED* */
2949 };
2950 
2951 /* The typedef declaration for the raw register contents of register group ALT_SPIS. */
2952 typedef volatile struct ALT_SPIS_raw_s ALT_SPIS_raw_t;
2953 #endif /* __ASSEMBLY__ */
2954 
2955 
2956 #ifdef __cplusplus
2957 }
2958 #endif /* __cplusplus */
2959 #endif /* __ALTERA_ALT_SPIS_H__ */
2960