35 #ifndef __ALT_SOCAL_FPGAMGR_H__
36 #define __ALT_SOCAL_FPGAMGR_H__
98 #define ALT_FPGAMGR_DCLKCNT_CNT_LSB 0
100 #define ALT_FPGAMGR_DCLKCNT_CNT_MSB 31
102 #define ALT_FPGAMGR_DCLKCNT_CNT_WIDTH 32
104 #define ALT_FPGAMGR_DCLKCNT_CNT_SET_MSK 0xffffffff
106 #define ALT_FPGAMGR_DCLKCNT_CNT_CLR_MSK 0x00000000
108 #define ALT_FPGAMGR_DCLKCNT_CNT_RESET 0x0
110 #define ALT_FPGAMGR_DCLKCNT_CNT_GET(value) (((value) & 0xffffffff) >> 0)
112 #define ALT_FPGAMGR_DCLKCNT_CNT_SET(value) (((value) << 0) & 0xffffffff)
125 struct ALT_FPGAMGR_DCLKCNT_s
131 typedef volatile struct ALT_FPGAMGR_DCLKCNT_s ALT_FPGAMGR_DCLKCNT_t;
135 #define ALT_FPGAMGR_DCLKCNT_RESET 0x00000000
137 #define ALT_FPGAMGR_DCLKCNT_OFST 0x8
176 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_E_NOTDONE 0x0
182 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_E_DONE 0x1
185 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_LSB 0
187 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_MSB 0
189 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_WIDTH 1
191 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_SET_MSK 0x00000001
193 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_CLR_MSK 0xfffffffe
195 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_RESET 0x0
197 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_GET(value) (((value) & 0x00000001) >> 0)
199 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_SET(value) (((value) << 0) & 0x00000001)
212 struct ALT_FPGAMGR_DCLKSTAT_s
214 uint32_t dcntdone : 1;
219 typedef volatile struct ALT_FPGAMGR_DCLKSTAT_s ALT_FPGAMGR_DCLKSTAT_t;
223 #define ALT_FPGAMGR_DCLKSTAT_RESET 0x00000000
225 #define ALT_FPGAMGR_DCLKSTAT_OFST 0xc
250 #define ALT_FPGAMGR_GPO_VALUE_LSB 0
252 #define ALT_FPGAMGR_GPO_VALUE_MSB 31
254 #define ALT_FPGAMGR_GPO_VALUE_WIDTH 32
256 #define ALT_FPGAMGR_GPO_VALUE_SET_MSK 0xffffffff
258 #define ALT_FPGAMGR_GPO_VALUE_CLR_MSK 0x00000000
260 #define ALT_FPGAMGR_GPO_VALUE_RESET 0x0
262 #define ALT_FPGAMGR_GPO_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
264 #define ALT_FPGAMGR_GPO_VALUE_SET(value) (((value) << 0) & 0xffffffff)
277 struct ALT_FPGAMGR_GPO_s
283 typedef volatile struct ALT_FPGAMGR_GPO_s ALT_FPGAMGR_GPO_t;
287 #define ALT_FPGAMGR_GPO_RESET 0x00000000
289 #define ALT_FPGAMGR_GPO_OFST 0x10
314 #define ALT_FPGAMGR_GPI_VALUE_LSB 0
316 #define ALT_FPGAMGR_GPI_VALUE_MSB 31
318 #define ALT_FPGAMGR_GPI_VALUE_WIDTH 32
320 #define ALT_FPGAMGR_GPI_VALUE_SET_MSK 0xffffffff
322 #define ALT_FPGAMGR_GPI_VALUE_CLR_MSK 0x00000000
324 #define ALT_FPGAMGR_GPI_VALUE_RESET 0x0
326 #define ALT_FPGAMGR_GPI_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
328 #define ALT_FPGAMGR_GPI_VALUE_SET(value) (((value) << 0) & 0xffffffff)
341 struct ALT_FPGAMGR_GPI_s
343 const uint32_t value : 32;
347 typedef volatile struct ALT_FPGAMGR_GPI_s ALT_FPGAMGR_GPI_t;
351 #define ALT_FPGAMGR_GPI_RESET 0x00000000
353 #define ALT_FPGAMGR_GPI_OFST 0x14
384 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_LSB 0
386 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_MSB 0
388 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_WIDTH 1
390 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_SET_MSK 0x00000001
392 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_CLR_MSK 0xfffffffe
394 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_RESET 0x0
396 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_GET(value) (((value) & 0x00000001) >> 0)
398 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_SET(value) (((value) << 0) & 0x00000001)
414 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_LSB 1
416 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_MSB 1
418 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_WIDTH 1
420 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_SET_MSK 0x00000002
422 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_CLR_MSK 0xfffffffd
424 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_RESET 0x0
426 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_GET(value) (((value) & 0x00000002) >> 1)
428 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_SET(value) (((value) << 1) & 0x00000002)
441 struct ALT_FPGAMGR_MISCI_s
443 const uint32_t bootFPGAfail : 1;
444 const uint32_t bootFPGArdy : 1;
449 typedef volatile struct ALT_FPGAMGR_MISCI_s ALT_FPGAMGR_MISCI_t;
453 #define ALT_FPGAMGR_MISCI_RESET 0x00000000
455 #define ALT_FPGAMGR_MISCI_OFST 0x18
478 #define ALT_FPGAMGR_EMR_DATA0_VALUE_LSB 0
480 #define ALT_FPGAMGR_EMR_DATA0_VALUE_MSB 31
482 #define ALT_FPGAMGR_EMR_DATA0_VALUE_WIDTH 32
484 #define ALT_FPGAMGR_EMR_DATA0_VALUE_SET_MSK 0xffffffff
486 #define ALT_FPGAMGR_EMR_DATA0_VALUE_CLR_MSK 0x00000000
488 #define ALT_FPGAMGR_EMR_DATA0_VALUE_RESET 0x0
490 #define ALT_FPGAMGR_EMR_DATA0_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
492 #define ALT_FPGAMGR_EMR_DATA0_VALUE_SET(value) (((value) << 0) & 0xffffffff)
505 struct ALT_FPGAMGR_EMR_DATA0_s
507 const uint32_t value : 32;
511 typedef volatile struct ALT_FPGAMGR_EMR_DATA0_s ALT_FPGAMGR_EMR_DATA0_t;
515 #define ALT_FPGAMGR_EMR_DATA0_RESET 0x00000000
517 #define ALT_FPGAMGR_EMR_DATA0_OFST 0x30
540 #define ALT_FPGAMGR_EMR_DATA1_VALUE_LSB 0
542 #define ALT_FPGAMGR_EMR_DATA1_VALUE_MSB 31
544 #define ALT_FPGAMGR_EMR_DATA1_VALUE_WIDTH 32
546 #define ALT_FPGAMGR_EMR_DATA1_VALUE_SET_MSK 0xffffffff
548 #define ALT_FPGAMGR_EMR_DATA1_VALUE_CLR_MSK 0x00000000
550 #define ALT_FPGAMGR_EMR_DATA1_VALUE_RESET 0x0
552 #define ALT_FPGAMGR_EMR_DATA1_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
554 #define ALT_FPGAMGR_EMR_DATA1_VALUE_SET(value) (((value) << 0) & 0xffffffff)
567 struct ALT_FPGAMGR_EMR_DATA1_s
569 const uint32_t value : 32;
573 typedef volatile struct ALT_FPGAMGR_EMR_DATA1_s ALT_FPGAMGR_EMR_DATA1_t;
577 #define ALT_FPGAMGR_EMR_DATA1_RESET 0x00000000
579 #define ALT_FPGAMGR_EMR_DATA1_OFST 0x34
602 #define ALT_FPGAMGR_EMR_DATA2_VALUE_LSB 0
604 #define ALT_FPGAMGR_EMR_DATA2_VALUE_MSB 31
606 #define ALT_FPGAMGR_EMR_DATA2_VALUE_WIDTH 32
608 #define ALT_FPGAMGR_EMR_DATA2_VALUE_SET_MSK 0xffffffff
610 #define ALT_FPGAMGR_EMR_DATA2_VALUE_CLR_MSK 0x00000000
612 #define ALT_FPGAMGR_EMR_DATA2_VALUE_RESET 0x0
614 #define ALT_FPGAMGR_EMR_DATA2_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
616 #define ALT_FPGAMGR_EMR_DATA2_VALUE_SET(value) (((value) << 0) & 0xffffffff)
629 struct ALT_FPGAMGR_EMR_DATA2_s
631 const uint32_t value : 32;
635 typedef volatile struct ALT_FPGAMGR_EMR_DATA2_s ALT_FPGAMGR_EMR_DATA2_t;
639 #define ALT_FPGAMGR_EMR_DATA2_RESET 0x00000000
641 #define ALT_FPGAMGR_EMR_DATA2_OFST 0x38
664 #define ALT_FPGAMGR_EMR_DATA3_VALUE_LSB 0
666 #define ALT_FPGAMGR_EMR_DATA3_VALUE_MSB 31
668 #define ALT_FPGAMGR_EMR_DATA3_VALUE_WIDTH 32
670 #define ALT_FPGAMGR_EMR_DATA3_VALUE_SET_MSK 0xffffffff
672 #define ALT_FPGAMGR_EMR_DATA3_VALUE_CLR_MSK 0x00000000
674 #define ALT_FPGAMGR_EMR_DATA3_VALUE_RESET 0x0
676 #define ALT_FPGAMGR_EMR_DATA3_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
678 #define ALT_FPGAMGR_EMR_DATA3_VALUE_SET(value) (((value) << 0) & 0xffffffff)
691 struct ALT_FPGAMGR_EMR_DATA3_s
693 const uint32_t value : 32;
697 typedef volatile struct ALT_FPGAMGR_EMR_DATA3_s ALT_FPGAMGR_EMR_DATA3_t;
701 #define ALT_FPGAMGR_EMR_DATA3_RESET 0x00000000
703 #define ALT_FPGAMGR_EMR_DATA3_OFST 0x3c
726 #define ALT_FPGAMGR_EMR_DATA4_VALUE_LSB 0
728 #define ALT_FPGAMGR_EMR_DATA4_VALUE_MSB 31
730 #define ALT_FPGAMGR_EMR_DATA4_VALUE_WIDTH 32
732 #define ALT_FPGAMGR_EMR_DATA4_VALUE_SET_MSK 0xffffffff
734 #define ALT_FPGAMGR_EMR_DATA4_VALUE_CLR_MSK 0x00000000
736 #define ALT_FPGAMGR_EMR_DATA4_VALUE_RESET 0x0
738 #define ALT_FPGAMGR_EMR_DATA4_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
740 #define ALT_FPGAMGR_EMR_DATA4_VALUE_SET(value) (((value) << 0) & 0xffffffff)
753 struct ALT_FPGAMGR_EMR_DATA4_s
755 const uint32_t value : 32;
759 typedef volatile struct ALT_FPGAMGR_EMR_DATA4_s ALT_FPGAMGR_EMR_DATA4_t;
763 #define ALT_FPGAMGR_EMR_DATA4_RESET 0x00000000
765 #define ALT_FPGAMGR_EMR_DATA4_OFST 0x40
788 #define ALT_FPGAMGR_EMR_DATA5_VALUE_LSB 0
790 #define ALT_FPGAMGR_EMR_DATA5_VALUE_MSB 31
792 #define ALT_FPGAMGR_EMR_DATA5_VALUE_WIDTH 32
794 #define ALT_FPGAMGR_EMR_DATA5_VALUE_SET_MSK 0xffffffff
796 #define ALT_FPGAMGR_EMR_DATA5_VALUE_CLR_MSK 0x00000000
798 #define ALT_FPGAMGR_EMR_DATA5_VALUE_RESET 0x0
800 #define ALT_FPGAMGR_EMR_DATA5_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
802 #define ALT_FPGAMGR_EMR_DATA5_VALUE_SET(value) (((value) << 0) & 0xffffffff)
815 struct ALT_FPGAMGR_EMR_DATA5_s
817 const uint32_t value : 32;
821 typedef volatile struct ALT_FPGAMGR_EMR_DATA5_s ALT_FPGAMGR_EMR_DATA5_t;
825 #define ALT_FPGAMGR_EMR_DATA5_RESET 0x00000000
827 #define ALT_FPGAMGR_EMR_DATA5_OFST 0x44
847 #define ALT_FPGAMGR_EMR_VALID_VLD_LSB 0
849 #define ALT_FPGAMGR_EMR_VALID_VLD_MSB 0
851 #define ALT_FPGAMGR_EMR_VALID_VLD_WIDTH 1
853 #define ALT_FPGAMGR_EMR_VALID_VLD_SET_MSK 0x00000001
855 #define ALT_FPGAMGR_EMR_VALID_VLD_CLR_MSK 0xfffffffe
857 #define ALT_FPGAMGR_EMR_VALID_VLD_RESET 0x0
859 #define ALT_FPGAMGR_EMR_VALID_VLD_GET(value) (((value) & 0x00000001) >> 0)
861 #define ALT_FPGAMGR_EMR_VALID_VLD_SET(value) (((value) << 0) & 0x00000001)
874 struct ALT_FPGAMGR_EMR_VALID_s
881 typedef volatile struct ALT_FPGAMGR_EMR_VALID_s ALT_FPGAMGR_EMR_VALID_t;
885 #define ALT_FPGAMGR_EMR_VALID_RESET 0x00000000
887 #define ALT_FPGAMGR_EMR_VALID_OFST 0x48
909 #define ALT_FPGAMGR_EMR_EN_EN_LSB 0
911 #define ALT_FPGAMGR_EMR_EN_EN_MSB 0
913 #define ALT_FPGAMGR_EMR_EN_EN_WIDTH 1
915 #define ALT_FPGAMGR_EMR_EN_EN_SET_MSK 0x00000001
917 #define ALT_FPGAMGR_EMR_EN_EN_CLR_MSK 0xfffffffe
919 #define ALT_FPGAMGR_EMR_EN_EN_RESET 0x0
921 #define ALT_FPGAMGR_EMR_EN_EN_GET(value) (((value) & 0x00000001) >> 0)
923 #define ALT_FPGAMGR_EMR_EN_EN_SET(value) (((value) << 0) & 0x00000001)
936 struct ALT_FPGAMGR_EMR_EN_s
943 typedef volatile struct ALT_FPGAMGR_EMR_EN_s ALT_FPGAMGR_EMR_EN_t;
947 #define ALT_FPGAMGR_EMR_EN_RESET 0x77000000
949 #define ALT_FPGAMGR_EMR_EN_OFST 0x4c
998 #define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_E_DIS 0x0
1004 #define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_E_EN 0x1
1007 #define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_LSB 0
1009 #define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_MSB 0
1011 #define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_WIDTH 1
1013 #define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_SET_MSK 0x00000001
1015 #define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_CLR_MSK 0xfffffffe
1017 #define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_RESET 0x0
1019 #define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_GET(value) (((value) & 0x00000001) >> 0)
1021 #define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_SET(value) (((value) << 0) & 0x00000001)
1046 #define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_E_DIS 0x0
1052 #define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_E_EN 0x1
1055 #define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_LSB 1
1057 #define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_MSB 1
1059 #define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_WIDTH 1
1061 #define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_SET_MSK 0x00000002
1063 #define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_CLR_MSK 0xfffffffd
1065 #define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_RESET 0x0
1067 #define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_GET(value) (((value) & 0x00000002) >> 1)
1069 #define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_SET(value) (((value) << 1) & 0x00000002)
1094 #define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_E_DIS 0x0
1100 #define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_E_EN 0x1
1103 #define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_LSB 2
1105 #define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_MSB 2
1107 #define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_WIDTH 1
1109 #define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_SET_MSK 0x00000004
1111 #define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_CLR_MSK 0xfffffffb
1113 #define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_RESET 0x0
1115 #define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_GET(value) (((value) & 0x00000004) >> 2)
1117 #define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_SET(value) (((value) << 2) & 0x00000004)
1133 #define ALT_FPGAMGR_JTAG_CFG_TRSTEN_LSB 4
1135 #define ALT_FPGAMGR_JTAG_CFG_TRSTEN_MSB 4
1137 #define ALT_FPGAMGR_JTAG_CFG_TRSTEN_WIDTH 1
1139 #define ALT_FPGAMGR_JTAG_CFG_TRSTEN_SET_MSK 0x00000010
1141 #define ALT_FPGAMGR_JTAG_CFG_TRSTEN_CLR_MSK 0xffffffef
1143 #define ALT_FPGAMGR_JTAG_CFG_TRSTEN_RESET 0x0
1145 #define ALT_FPGAMGR_JTAG_CFG_TRSTEN_GET(value) (((value) & 0x00000010) >> 4)
1147 #define ALT_FPGAMGR_JTAG_CFG_TRSTEN_SET(value) (((value) << 4) & 0x00000010)
1166 #define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_LSB 8
1168 #define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_MSB 15
1170 #define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_WIDTH 8
1172 #define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_SET_MSK 0x0000ff00
1174 #define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_CLR_MSK 0xffff00ff
1176 #define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_RESET 0x14
1178 #define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_GET(value) (((value) & 0x0000ff00) >> 8)
1180 #define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_SET(value) (((value) << 8) & 0x0000ff00)
1211 #define ALT_FPGAMGR_JTAG_CFG_TXSIZE_LSB 16
1213 #define ALT_FPGAMGR_JTAG_CFG_TXSIZE_MSB 31
1215 #define ALT_FPGAMGR_JTAG_CFG_TXSIZE_WIDTH 16
1217 #define ALT_FPGAMGR_JTAG_CFG_TXSIZE_SET_MSK 0xffff0000
1219 #define ALT_FPGAMGR_JTAG_CFG_TXSIZE_CLR_MSK 0x0000ffff
1221 #define ALT_FPGAMGR_JTAG_CFG_TXSIZE_RESET 0x0
1223 #define ALT_FPGAMGR_JTAG_CFG_TXSIZE_GET(value) (((value) & 0xffff0000) >> 16)
1225 #define ALT_FPGAMGR_JTAG_CFG_TXSIZE_SET(value) (((value) << 16) & 0xffff0000)
1227 #ifndef __ASSEMBLY__
1238 struct ALT_FPGAMGR_JTAG_CFG_s
1240 uint32_t JtagHostEn : 1;
1241 uint32_t jtagPortEn : 1;
1242 uint32_t loopBackEn : 1;
1244 uint32_t trstEn : 1;
1246 uint32_t tckRatio : 8;
1247 uint32_t txSize : 16;
1251 typedef volatile struct ALT_FPGAMGR_JTAG_CFG_s ALT_FPGAMGR_JTAG_CFG_t;
1255 #define ALT_FPGAMGR_JTAG_CFG_RESET 0x00001400
1257 #define ALT_FPGAMGR_JTAG_CFG_OFST 0x50
1290 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_LSB 0
1292 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_MSB 3
1294 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_WIDTH 4
1296 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_SET_MSK 0x0000000f
1298 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_CLR_MSK 0xfffffff0
1300 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_RESET 0x0
1302 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_GET(value) (((value) & 0x0000000f) >> 0)
1304 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_SET(value) (((value) << 0) & 0x0000000f)
1317 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_LSB 4
1319 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_MSB 7
1321 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_WIDTH 4
1323 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_SET_MSK 0x000000f0
1325 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_CLR_MSK 0xffffff0f
1327 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_RESET 0x0
1329 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_GET(value) (((value) & 0x000000f0) >> 4)
1331 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_SET(value) (((value) << 4) & 0x000000f0)
1346 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_LSB 8
1348 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_MSB 8
1350 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_WIDTH 1
1352 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_SET_MSK 0x00000100
1354 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_CLR_MSK 0xfffffeff
1356 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_RESET 0x1
1358 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_GET(value) (((value) & 0x00000100) >> 8)
1360 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_SET(value) (((value) << 8) & 0x00000100)
1375 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_LSB 9
1377 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_MSB 9
1379 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_WIDTH 1
1381 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_SET_MSK 0x00000200
1383 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_CLR_MSK 0xfffffdff
1385 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_RESET 0x0
1387 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_GET(value) (((value) & 0x00000200) >> 9)
1389 #define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_SET(value) (((value) << 9) & 0x00000200)
1404 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_LSB 10
1406 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_MSB 10
1408 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_WIDTH 1
1410 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_SET_MSK 0x00000400
1412 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_CLR_MSK 0xfffffbff
1414 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_RESET 0x1
1416 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_GET(value) (((value) & 0x00000400) >> 10)
1418 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_SET(value) (((value) << 10) & 0x00000400)
1433 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_LSB 11
1435 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_MSB 11
1437 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_WIDTH 1
1439 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_SET_MSK 0x00000800
1441 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_CLR_MSK 0xfffff7ff
1443 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_RESET 0x0
1445 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_GET(value) (((value) & 0x00000800) >> 11)
1447 #define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_SET(value) (((value) << 11) & 0x00000800)
1471 #define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_E_DIS 0x0
1477 #define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_E_EN 0x1
1480 #define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_LSB 15
1482 #define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_MSB 15
1484 #define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_WIDTH 1
1486 #define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_SET_MSK 0x00008000
1488 #define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_CLR_MSK 0xffff7fff
1490 #define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_RESET 0x0
1492 #define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_GET(value) (((value) & 0x00008000) >> 15)
1494 #define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_SET(value) (((value) << 15) & 0x00008000)
1514 #define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_LSB 16
1516 #define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_MSB 31
1518 #define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_WIDTH 16
1520 #define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_SET_MSK 0xffff0000
1522 #define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_CLR_MSK 0x0000ffff
1524 #define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_RESET 0x0
1526 #define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_GET(value) (((value) & 0xffff0000) >> 16)
1528 #define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_SET(value) (((value) << 16) & 0xffff0000)
1530 #ifndef __ASSEMBLY__
1541 struct ALT_FPGAMGR_JTAG_STAT_s
1543 uint32_t txFifoLevel : 4;
1544 uint32_t rxFifoLevel : 4;
1545 uint32_t txFifoEmpty : 1;
1546 uint32_t txFifoFull : 1;
1547 uint32_t rxFifoEmpty : 1;
1548 uint32_t rxFifoFull : 1;
1550 uint32_t SessionStatus : 1;
1551 uint32_t txDoneSize : 16;
1555 typedef volatile struct ALT_FPGAMGR_JTAG_STAT_s ALT_FPGAMGR_JTAG_STAT_t;
1559 #define ALT_FPGAMGR_JTAG_STAT_RESET 0x00000500
1561 #define ALT_FPGAMGR_JTAG_STAT_OFST 0x54
1594 #define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_LSB 0
1596 #define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_MSB 0
1598 #define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_WIDTH 1
1600 #define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_SET_MSK 0x00000001
1602 #define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_CLR_MSK 0xfffffffe
1604 #define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_RESET 0x0
1606 #define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_GET(value) (((value) & 0x00000001) >> 0)
1608 #define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_SET(value) (((value) << 0) & 0x00000001)
1624 #define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_LSB 1
1626 #define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_MSB 1
1628 #define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_WIDTH 1
1630 #define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_SET_MSK 0x00000002
1632 #define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_CLR_MSK 0xfffffffd
1634 #define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_RESET 0x0
1636 #define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_GET(value) (((value) & 0x00000002) >> 1)
1638 #define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_SET(value) (((value) << 1) & 0x00000002)
1649 #define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_LSB 2
1651 #define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_MSB 2
1653 #define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_WIDTH 1
1655 #define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_SET_MSK 0x00000004
1657 #define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_CLR_MSK 0xfffffffb
1659 #define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_RESET 0x0
1661 #define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_GET(value) (((value) & 0x00000004) >> 2)
1663 #define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_SET(value) (((value) << 2) & 0x00000004)
1674 #define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_LSB 3
1676 #define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_MSB 3
1678 #define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_WIDTH 1
1680 #define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_SET_MSK 0x00000008
1682 #define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_CLR_MSK 0xfffffff7
1684 #define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_RESET 0x0
1686 #define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_GET(value) (((value) & 0x00000008) >> 3)
1688 #define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_SET(value) (((value) << 3) & 0x00000008)
1690 #ifndef __ASSEMBLY__
1701 struct ALT_FPGAMGR_JTAG_KICK_s
1703 uint32_t startSession : 1;
1704 uint32_t stopSession : 1;
1705 uint32_t clearTxFifo : 1;
1706 uint32_t clearRxFifo : 1;
1711 typedef volatile struct ALT_FPGAMGR_JTAG_KICK_s ALT_FPGAMGR_JTAG_KICK_t;
1715 #define ALT_FPGAMGR_JTAG_KICK_RESET 0x00000000
1717 #define ALT_FPGAMGR_JTAG_KICK_OFST 0x58
1758 #define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_LSB 0
1760 #define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_MSB 15
1762 #define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_WIDTH 16
1764 #define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_SET_MSK 0x0000ffff
1766 #define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_CLR_MSK 0xffff0000
1768 #define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_RESET 0x0
1770 #define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_GET(value) (((value) & 0x0000ffff) >> 0)
1772 #define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_SET(value) (((value) << 0) & 0x0000ffff)
1783 #define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_LSB 16
1785 #define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_MSB 31
1787 #define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_WIDTH 16
1789 #define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_SET_MSK 0xffff0000
1791 #define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_CLR_MSK 0x0000ffff
1793 #define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_RESET 0x0
1795 #define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_GET(value) (((value) & 0xffff0000) >> 16)
1797 #define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_SET(value) (((value) << 16) & 0xffff0000)
1799 #ifndef __ASSEMBLY__
1810 struct ALT_FPGAMGR_JTAG_DATA_W_s
1812 uint32_t tdiData : 16;
1813 uint32_t tmsData : 16;
1817 typedef volatile struct ALT_FPGAMGR_JTAG_DATA_W_s ALT_FPGAMGR_JTAG_DATA_W_t;
1821 #define ALT_FPGAMGR_JTAG_DATA_W_RESET 0x00000000
1823 #define ALT_FPGAMGR_JTAG_DATA_W_OFST 0x60
1862 #define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_LSB 0
1864 #define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_MSB 15
1866 #define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_WIDTH 16
1868 #define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_SET_MSK 0x0000ffff
1870 #define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_CLR_MSK 0xffff0000
1872 #define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_RESET 0x0
1874 #define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_GET(value) (((value) & 0x0000ffff) >> 0)
1876 #define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_SET(value) (((value) << 0) & 0x0000ffff)
1885 #define ALT_FPGAMGR_JTAG_DATA_R_RSVD_LSB 16
1887 #define ALT_FPGAMGR_JTAG_DATA_R_RSVD_MSB 31
1889 #define ALT_FPGAMGR_JTAG_DATA_R_RSVD_WIDTH 16
1891 #define ALT_FPGAMGR_JTAG_DATA_R_RSVD_SET_MSK 0xffff0000
1893 #define ALT_FPGAMGR_JTAG_DATA_R_RSVD_CLR_MSK 0x0000ffff
1895 #define ALT_FPGAMGR_JTAG_DATA_R_RSVD_RESET 0x0
1897 #define ALT_FPGAMGR_JTAG_DATA_R_RSVD_GET(value) (((value) & 0xffff0000) >> 16)
1899 #define ALT_FPGAMGR_JTAG_DATA_R_RSVD_SET(value) (((value) << 16) & 0xffff0000)
1901 #ifndef __ASSEMBLY__
1912 struct ALT_FPGAMGR_JTAG_DATA_R_s
1914 uint32_t tdiData : 16;
1915 uint32_t Reserved : 16;
1919 typedef volatile struct ALT_FPGAMGR_JTAG_DATA_R_s ALT_FPGAMGR_JTAG_DATA_R_t;
1923 #define ALT_FPGAMGR_JTAG_DATA_R_RESET 0x00000000
1925 #define ALT_FPGAMGR_JTAG_DATA_R_OFST 0x64
1959 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_LSB 0
1961 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_MSB 0
1963 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_WIDTH 1
1965 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_SET_MSK 0x00000001
1967 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_CLR_MSK 0xfffffffe
1969 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_RESET 0x1
1971 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_GET(value) (((value) & 0x00000001) >> 0)
1973 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_SET(value) (((value) << 0) & 0x00000001)
1988 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_LSB 1
1990 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_MSB 1
1992 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_WIDTH 1
1994 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_SET_MSK 0x00000002
1996 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_CLR_MSK 0xfffffffd
1998 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_RESET 0x1
2000 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_GET(value) (((value) & 0x00000002) >> 1)
2002 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_SET(value) (((value) << 1) & 0x00000002)
2017 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_LSB 2
2019 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_MSB 2
2021 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_WIDTH 1
2023 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_SET_MSK 0x00000004
2025 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_CLR_MSK 0xfffffffb
2027 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_RESET 0x1
2029 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_GET(value) (((value) & 0x00000004) >> 2)
2031 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_SET(value) (((value) << 2) & 0x00000004)
2050 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_LSB 8
2052 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_MSB 8
2054 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_WIDTH 1
2056 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_SET_MSK 0x00000100
2058 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_CLR_MSK 0xfffffeff
2060 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_RESET 0x1
2062 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_GET(value) (((value) & 0x00000100) >> 8)
2064 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_SET(value) (((value) << 8) & 0x00000100)
2086 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_LSB 16
2088 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_MSB 16
2090 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_WIDTH 1
2092 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_SET_MSK 0x00010000
2094 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_CLR_MSK 0xfffeffff
2096 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_RESET 0x0
2098 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_GET(value) (((value) & 0x00010000) >> 16)
2100 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_SET(value) (((value) << 16) & 0x00010000)
2117 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_LSB 24
2119 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_MSB 24
2121 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_WIDTH 1
2123 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK 0x01000000
2125 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_CLR_MSK 0xfeffffff
2127 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_RESET 0x0
2129 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_GET(value) (((value) & 0x01000000) >> 24)
2131 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET(value) (((value) << 24) & 0x01000000)
2133 #ifndef __ASSEMBLY__
2144 struct ALT_FPGAMGR_IMGCFG_CTL_00_s
2146 uint32_t s2f_nenable_nconfig : 1;
2147 uint32_t s2f_nenable_nstatus : 1;
2148 uint32_t s2f_nenable_condone : 1;
2150 uint32_t s2f_nconfig : 1;
2152 uint32_t s2f_nstatus_oe : 1;
2154 uint32_t s2f_condone_oe : 1;
2159 typedef volatile struct ALT_FPGAMGR_IMGCFG_CTL_00_s ALT_FPGAMGR_IMGCFG_CTL_00_t;
2163 #define ALT_FPGAMGR_IMGCFG_CTL_00_RESET 0x00000107
2165 #define ALT_FPGAMGR_IMGCFG_CTL_00_OFST 0x70
2195 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_LSB 0
2197 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_MSB 0
2199 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_WIDTH 1
2201 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_SET_MSK 0x00000001
2203 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_CLR_MSK 0xfffffffe
2205 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_RESET 0x1
2207 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_GET(value) (((value) & 0x00000001) >> 0)
2209 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_SET(value) (((value) << 0) & 0x00000001)
2220 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_LSB 16
2222 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_MSB 16
2224 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_WIDTH 1
2226 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK 0x00010000
2228 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_CLR_MSK 0xfffeffff
2230 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_RESET 0x0
2232 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_GET(value) (((value) & 0x00010000) >> 16)
2234 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET(value) (((value) << 16) & 0x00010000)
2245 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_LSB 24
2247 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_MSB 24
2249 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_WIDTH 1
2251 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK 0x01000000
2253 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_CLR_MSK 0xfeffffff
2255 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_RESET 0x1
2257 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_GET(value) (((value) & 0x01000000) >> 24)
2259 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET(value) (((value) << 24) & 0x01000000)
2261 #ifndef __ASSEMBLY__
2272 struct ALT_FPGAMGR_IMGCFG_CTL_01_s
2274 uint32_t s2f_nenable_config : 1;
2276 uint32_t s2f_pr_request : 1;
2278 uint32_t s2f_nce : 1;
2283 typedef volatile struct ALT_FPGAMGR_IMGCFG_CTL_01_s ALT_FPGAMGR_IMGCFG_CTL_01_t;
2287 #define ALT_FPGAMGR_IMGCFG_CTL_01_RESET 0x01000001
2289 #define ALT_FPGAMGR_IMGCFG_CTL_01_OFST 0x74
2337 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_LSB 0
2339 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_MSB 0
2341 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_WIDTH 1
2343 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_SET_MSK 0x00000001
2345 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_CLR_MSK 0xfffffffe
2347 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_RESET 0x0
2349 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_GET(value) (((value) & 0x00000001) >> 0)
2351 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_SET(value) (((value) << 0) & 0x00000001)
2362 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_LSB 8
2364 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_MSB 8
2366 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_WIDTH 1
2368 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK 0x00000100
2370 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_CLR_MSK 0xfffffeff
2372 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_RESET 0x0
2374 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_GET(value) (((value) & 0x00000100) >> 8)
2376 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET(value) (((value) << 8) & 0x00000100)
2407 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X1 0x0
2413 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X2 0x1
2419 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X4 0x2
2425 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X8 0x3
2428 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
2430 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_MSB 17
2432 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_WIDTH 2
2434 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000
2436 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_CLR_MSK 0xfffcffff
2438 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_RESET 0x0
2440 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_GET(value) (((value) & 0x00030000) >> 16)
2442 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET(value) (((value) << 16) & 0x00030000)
2472 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_E_PPX16 0x0
2478 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_E_PPX32 0x1
2481 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_LSB 24
2483 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_MSB 24
2485 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_WIDTH 1
2487 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK 0x01000000
2489 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_CLR_MSK 0xfeffffff
2491 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_RESET 0x0
2493 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_GET(value) (((value) & 0x01000000) >> 24)
2495 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET(value) (((value) << 24) & 0x01000000)
2497 #ifndef __ASSEMBLY__
2508 struct ALT_FPGAMGR_IMGCFG_CTL_02_s
2510 uint32_t en_cfg_ctrl : 1;
2512 uint32_t en_cfg_data : 1;
2514 uint32_t cdratio : 2;
2516 uint32_t cfgwidth : 1;
2521 typedef volatile struct ALT_FPGAMGR_IMGCFG_CTL_02_s ALT_FPGAMGR_IMGCFG_CTL_02_t;
2525 #define ALT_FPGAMGR_IMGCFG_CTL_02_RESET 0x00000200
2527 #define ALT_FPGAMGR_IMGCFG_CTL_02_OFST 0x78
2575 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_LSB 0
2577 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_MSB 0
2579 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_WIDTH 1
2581 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK 0x00000001
2583 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_CLR_MSK 0xfffffffe
2585 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_RESET 0x0
2587 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_GET(value) (((value) & 0x00000001) >> 0)
2589 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET(value) (((value) << 0) & 0x00000001)
2598 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_LSB 1
2600 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_MSB 1
2602 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_WIDTH 1
2604 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_SET_MSK 0x00000002
2606 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_CLR_MSK 0xfffffffd
2608 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_RESET 0x0
2610 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_GET(value) (((value) & 0x00000002) >> 1)
2612 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_SET(value) (((value) << 1) & 0x00000002)
2621 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_LSB 2
2623 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_MSB 2
2625 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_WIDTH 1
2627 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_SET_MSK 0x00000004
2629 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_CLR_MSK 0xfffffffb
2631 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_RESET 0x0
2633 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_GET(value) (((value) & 0x00000004) >> 2)
2635 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_SET(value) (((value) << 2) & 0x00000004)
2644 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_LSB 3
2646 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_MSB 3
2648 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_WIDTH 1
2650 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK 0x00000008
2652 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_CLR_MSK 0xfffffff7
2654 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_RESET 0x0
2656 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_GET(value) (((value) & 0x00000008) >> 3)
2658 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET(value) (((value) << 3) & 0x00000008)
2667 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_LSB 4
2669 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_MSB 4
2671 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_WIDTH 1
2673 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_SET_MSK 0x00000010
2675 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_CLR_MSK 0xffffffef
2677 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_RESET 0x0
2679 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_GET(value) (((value) & 0x00000010) >> 4)
2681 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_SET(value) (((value) << 4) & 0x00000010)
2690 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_LSB 5
2692 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_MSB 5
2694 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_WIDTH 1
2696 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_SET_MSK 0x00000020
2698 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_CLR_MSK 0xffffffdf
2700 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_RESET 0x0
2702 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_GET(value) (((value) & 0x00000020) >> 5)
2704 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_SET(value) (((value) << 5) & 0x00000020)
2713 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_LSB 6
2715 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_MSB 6
2717 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_WIDTH 1
2719 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK 0x00000040
2721 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_CLR_MSK 0xffffffbf
2723 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_RESET 0x0
2725 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_GET(value) (((value) & 0x00000040) >> 6)
2727 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET(value) (((value) << 6) & 0x00000040)
2736 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_LSB 7
2738 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_MSB 7
2740 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_WIDTH 1
2742 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK 0x00000080
2744 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_CLR_MSK 0xffffff7f
2746 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_RESET 0x0
2748 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_GET(value) (((value) & 0x00000080) >> 7)
2750 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET(value) (((value) << 7) & 0x00000080)
2759 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_LSB 8
2761 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_MSB 8
2763 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_WIDTH 1
2765 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK 0x00000100
2767 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_CLR_MSK 0xfffffeff
2769 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_RESET 0x0
2771 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_GET(value) (((value) & 0x00000100) >> 8)
2773 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET(value) (((value) << 8) & 0x00000100)
2782 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_LSB 9
2784 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_MSB 9
2786 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_WIDTH 1
2788 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_SET_MSK 0x00000200
2790 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_CLR_MSK 0xfffffdff
2792 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_RESET 0x0
2794 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_GET(value) (((value) & 0x00000200) >> 9)
2796 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_SET(value) (((value) << 9) & 0x00000200)
2805 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_LSB 10
2807 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_MSB 10
2809 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_WIDTH 1
2811 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK 0x00000400
2813 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_CLR_MSK 0xfffffbff
2815 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_RESET 0x0
2817 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_GET(value) (((value) & 0x00000400) >> 10)
2819 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET(value) (((value) << 10) & 0x00000400)
2828 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_LSB 11
2830 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_MSB 11
2832 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_WIDTH 1
2834 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK 0x00000800
2836 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_CLR_MSK 0xfffff7ff
2838 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_RESET 0x0
2840 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_GET(value) (((value) & 0x00000800) >> 11)
2842 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET(value) (((value) << 11) & 0x00000800)
2851 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_LSB 12
2853 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_MSB 12
2855 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_WIDTH 1
2857 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_SET_MSK 0x00001000
2859 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_CLR_MSK 0xffffefff
2861 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_RESET 0x0
2863 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_GET(value) (((value) & 0x00001000) >> 12)
2865 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_SET(value) (((value) << 12) & 0x00001000)
2874 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_LSB 13
2876 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_MSB 13
2878 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_WIDTH 1
2880 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK 0x00002000
2882 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_CLR_MSK 0xffffdfff
2884 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_RESET 0x0
2886 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_GET(value) (((value) & 0x00002000) >> 13)
2888 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET(value) (((value) << 13) & 0x00002000)
2905 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16
2907 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_MSB 16
2909 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_WIDTH 1
2911 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK 0x00010000
2913 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_CLR_MSK 0xfffeffff
2915 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_RESET 0x0
2917 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_GET(value) (((value) & 0x00010000) >> 16)
2919 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET(value) (((value) << 16) & 0x00010000)
2936 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_LSB 17
2938 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_MSB 17
2940 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_WIDTH 1
2942 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK 0x00020000
2944 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_CLR_MSK 0xfffdffff
2946 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_RESET 0x0
2948 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_GET(value) (((value) & 0x00020000) >> 17)
2950 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET(value) (((value) << 17) & 0x00020000)
2967 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_LSB 18
2969 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_MSB 18
2971 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_WIDTH 1
2973 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK 0x00040000
2975 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_CLR_MSK 0xfffbffff
2977 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_RESET 0x0
2979 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_GET(value) (((value) & 0x00040000) >> 18)
2981 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET(value) (((value) << 18) & 0x00040000)
2992 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_LSB 24
2994 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_MSB 24
2996 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_WIDTH 1
2998 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_SET_MSK 0x01000000
3000 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_CLR_MSK 0xfeffffff
3002 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_RESET 0x1
3004 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_GET(value) (((value) & 0x01000000) >> 24)
3006 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_SET(value) (((value) << 24) & 0x01000000)
3017 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_LSB 25
3019 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_MSB 25
3021 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_WIDTH 1
3023 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_SET_MSK 0x02000000
3025 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_CLR_MSK 0xfdffffff
3027 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_RESET 0x0
3029 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_GET(value) (((value) & 0x02000000) >> 25)
3031 #define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_SET(value) (((value) << 25) & 0x02000000)
3042 #define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_LSB 28
3044 #define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_MSB 28
3046 #define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_WIDTH 1
3048 #define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_SET_MSK 0x10000000
3050 #define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_CLR_MSK 0xefffffff
3052 #define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_RESET 0x0
3054 #define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_GET(value) (((value) & 0x10000000) >> 28)
3056 #define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_SET(value) (((value) << 28) & 0x10000000)
3067 #define ALT_FPGAMGR_IMGCFG_STAT_EMR_LSB 29
3069 #define ALT_FPGAMGR_IMGCFG_STAT_EMR_MSB 29
3071 #define ALT_FPGAMGR_IMGCFG_STAT_EMR_WIDTH 1
3073 #define ALT_FPGAMGR_IMGCFG_STAT_EMR_SET_MSK 0x20000000
3075 #define ALT_FPGAMGR_IMGCFG_STAT_EMR_CLR_MSK 0xdfffffff
3077 #define ALT_FPGAMGR_IMGCFG_STAT_EMR_RESET 0x0
3079 #define ALT_FPGAMGR_IMGCFG_STAT_EMR_GET(value) (((value) & 0x20000000) >> 29)
3081 #define ALT_FPGAMGR_IMGCFG_STAT_EMR_SET(value) (((value) << 29) & 0x20000000)
3083 #ifndef __ASSEMBLY__
3094 struct ALT_FPGAMGR_IMGCFG_STAT_s
3096 const uint32_t f2s_crc_error : 1;
3097 const uint32_t f2s_early_usermode : 1;
3098 const uint32_t f2s_usermode : 1;
3099 const uint32_t f2s_initdone_oe : 1;
3100 const uint32_t f2s_nstatus_pin : 1;
3101 const uint32_t f2s_nstatus_oe : 1;
3102 const uint32_t f2s_condone_pin : 1;
3103 const uint32_t f2s_condone_oe : 1;
3104 const uint32_t f2s_cvp_conf_done : 1;
3105 const uint32_t f2s_pr_ready : 1;
3106 const uint32_t f2s_pr_done : 1;
3107 const uint32_t f2s_pr_error : 1;
3108 const uint32_t f2s_nconfig_pin : 1;
3109 const uint32_t f2s_nceo_oe : 1;
3111 const uint32_t f2s_msel0 : 1;
3112 const uint32_t f2s_msel1 : 1;
3113 const uint32_t f2s_msel2 : 1;
3115 const uint32_t imgcfg_FifoEmpty : 1;
3116 const uint32_t imgcfg_FifoFull : 1;
3118 const uint32_t jtagm : 1;
3119 const uint32_t emr : 1;
3124 typedef volatile struct ALT_FPGAMGR_IMGCFG_STAT_s ALT_FPGAMGR_IMGCFG_STAT_t;
3128 #define ALT_FPGAMGR_IMGCFG_STAT_RESET 0x01000000
3130 #define ALT_FPGAMGR_IMGCFG_STAT_OFST 0x80
3179 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_LSB 0
3181 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_MSB 0
3183 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_WIDTH 1
3185 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_SET_MSK 0x00000001
3187 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_CLR_MSK 0xfffffffe
3189 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_RESET 0x0
3191 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_GET(value) (((value) & 0x00000001) >> 0)
3193 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_SET(value) (((value) << 0) & 0x00000001)
3202 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_LSB 1
3204 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_MSB 1
3206 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_WIDTH 1
3208 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_SET_MSK 0x00000002
3210 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_CLR_MSK 0xfffffffd
3212 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_RESET 0x0
3214 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_GET(value) (((value) & 0x00000002) >> 1)
3216 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_SET(value) (((value) << 1) & 0x00000002)
3225 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_LSB 2
3227 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_MSB 2
3229 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_WIDTH 1
3231 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_SET_MSK 0x00000004
3233 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_CLR_MSK 0xfffffffb
3235 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_RESET 0x0
3237 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_GET(value) (((value) & 0x00000004) >> 2)
3239 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_SET(value) (((value) << 2) & 0x00000004)
3248 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_LSB 3
3250 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_MSB 3
3252 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_WIDTH 1
3254 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_SET_MSK 0x00000008
3256 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_CLR_MSK 0xfffffff7
3258 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_RESET 0x0
3260 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_GET(value) (((value) & 0x00000008) >> 3)
3262 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_SET(value) (((value) << 3) & 0x00000008)
3271 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_LSB 4
3273 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_MSB 4
3275 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_WIDTH 1
3277 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_SET_MSK 0x00000010
3279 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_CLR_MSK 0xffffffef
3281 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_RESET 0x0
3283 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_GET(value) (((value) & 0x00000010) >> 4)
3285 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_SET(value) (((value) << 4) & 0x00000010)
3294 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_LSB 5
3296 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_MSB 5
3298 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_WIDTH 1
3300 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_SET_MSK 0x00000020
3302 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_CLR_MSK 0xffffffdf
3304 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_RESET 0x0
3306 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_GET(value) (((value) & 0x00000020) >> 5)
3308 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_SET(value) (((value) << 5) & 0x00000020)
3317 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_LSB 6
3319 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_MSB 6
3321 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_WIDTH 1
3323 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_SET_MSK 0x00000040
3325 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_CLR_MSK 0xffffffbf
3327 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_RESET 0x0
3329 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_GET(value) (((value) & 0x00000040) >> 6)
3331 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_SET(value) (((value) << 6) & 0x00000040)
3340 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_LSB 7
3342 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_MSB 7
3344 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_WIDTH 1
3346 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_SET_MSK 0x00000080
3348 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_CLR_MSK 0xffffff7f
3350 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_RESET 0x0
3352 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_GET(value) (((value) & 0x00000080) >> 7)
3354 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_SET(value) (((value) << 7) & 0x00000080)
3363 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_LSB 8
3365 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_MSB 8
3367 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_WIDTH 1
3369 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_SET_MSK 0x00000100
3371 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_CLR_MSK 0xfffffeff
3373 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_RESET 0x0
3375 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_GET(value) (((value) & 0x00000100) >> 8)
3377 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_SET(value) (((value) << 8) & 0x00000100)
3386 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_LSB 9
3388 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_MSB 9
3390 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_WIDTH 1
3392 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_SET_MSK 0x00000200
3394 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_CLR_MSK 0xfffffdff
3396 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_RESET 0x0
3398 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_GET(value) (((value) & 0x00000200) >> 9)
3400 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_SET(value) (((value) << 9) & 0x00000200)
3409 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_LSB 10
3411 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_MSB 10
3413 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_WIDTH 1
3415 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_SET_MSK 0x00000400
3417 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_CLR_MSK 0xfffffbff
3419 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_RESET 0x0
3421 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_GET(value) (((value) & 0x00000400) >> 10)
3423 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_SET(value) (((value) << 10) & 0x00000400)
3432 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_LSB 11
3434 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_MSB 11
3436 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_WIDTH 1
3438 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_SET_MSK 0x00000800
3440 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_CLR_MSK 0xfffff7ff
3442 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_RESET 0x0
3444 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_GET(value) (((value) & 0x00000800) >> 11)
3446 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_SET(value) (((value) << 11) & 0x00000800)
3455 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_LSB 12
3457 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_MSB 12
3459 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_WIDTH 1
3461 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_SET_MSK 0x00001000
3463 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_CLR_MSK 0xffffefff
3465 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_RESET 0x0
3467 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_GET(value) (((value) & 0x00001000) >> 12)
3469 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_SET(value) (((value) << 12) & 0x00001000)
3478 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_LSB 13
3480 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_MSB 13
3482 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_WIDTH 1
3484 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_SET_MSK 0x00002000
3486 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_CLR_MSK 0xffffdfff
3488 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_RESET 0x0
3490 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_GET(value) (((value) & 0x00002000) >> 13)
3492 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_SET(value) (((value) << 13) & 0x00002000)
3501 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_LSB 16
3503 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_MSB 16
3505 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_WIDTH 1
3507 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_SET_MSK 0x00010000
3509 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_CLR_MSK 0xfffeffff
3511 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_RESET 0x0
3513 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_GET(value) (((value) & 0x00010000) >> 16)
3515 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_SET(value) (((value) << 16) & 0x00010000)
3524 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_LSB 17
3526 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_MSB 17
3528 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_WIDTH 1
3530 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_SET_MSK 0x00020000
3532 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_CLR_MSK 0xfffdffff
3534 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_RESET 0x0
3536 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_GET(value) (((value) & 0x00020000) >> 17)
3538 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_SET(value) (((value) << 17) & 0x00020000)
3547 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_LSB 18
3549 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_MSB 18
3551 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_WIDTH 1
3553 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_SET_MSK 0x00040000
3555 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_CLR_MSK 0xfffbffff
3557 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_RESET 0x0
3559 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_GET(value) (((value) & 0x00040000) >> 18)
3561 #define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_SET(value) (((value) << 18) & 0x00040000)
3572 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_LSB 24
3574 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_MSB 24
3576 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_WIDTH 1
3578 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_SET_MSK 0x01000000
3580 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_CLR_MSK 0xfeffffff
3582 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_RESET 0x0
3584 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_GET(value) (((value) & 0x01000000) >> 24)
3586 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_SET(value) (((value) << 24) & 0x01000000)
3597 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_LSB 25
3599 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_MSB 25
3601 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_WIDTH 1
3603 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_SET_MSK 0x02000000
3605 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_CLR_MSK 0xfdffffff
3607 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_RESET 0x0
3609 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_GET(value) (((value) & 0x02000000) >> 25)
3611 #define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_SET(value) (((value) << 25) & 0x02000000)
3622 #define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_LSB 28
3624 #define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_MSB 28
3626 #define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_WIDTH 1
3628 #define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_SET_MSK 0x10000000
3630 #define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_CLR_MSK 0xefffffff
3632 #define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_RESET 0x0
3634 #define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_GET(value) (((value) & 0x10000000) >> 28)
3636 #define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_SET(value) (((value) << 28) & 0x10000000)
3647 #define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_LSB 29
3649 #define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_MSB 29
3651 #define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_WIDTH 1
3653 #define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_SET_MSK 0x20000000
3655 #define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_CLR_MSK 0xdfffffff
3657 #define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_RESET 0x0
3659 #define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_GET(value) (((value) & 0x20000000) >> 29)
3661 #define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_SET(value) (((value) << 29) & 0x20000000)
3663 #ifndef __ASSEMBLY__
3674 struct ALT_FPGAMGR_INTR_MSKED_STAT_s
3676 uint32_t f2s_crc_error : 1;
3677 uint32_t f2s_early_usermode : 1;
3678 uint32_t f2s_usermode : 1;
3679 uint32_t f2s_initdone_oe : 1;
3680 uint32_t f2s_nstatus_pin : 1;
3681 uint32_t f2s_nstatus_oe : 1;
3682 uint32_t f2s_condone_pin : 1;
3683 uint32_t f2s_condone_oe : 1;
3684 uint32_t f2s_cvp_conf_done : 1;
3685 uint32_t f2s_pr_ready : 1;
3686 uint32_t f2s_pr_done : 1;
3687 uint32_t f2s_pr_error : 1;
3688 uint32_t f2s_nconfig_pin : 1;
3689 uint32_t f2s_nceo_oe : 1;
3691 uint32_t f2s_msel0 : 1;
3692 uint32_t f2s_msel1 : 1;
3693 uint32_t f2s_msel2 : 1;
3695 uint32_t imgcfg_FifoEmpty : 1;
3696 uint32_t imgcfg_FifoFull : 1;
3704 typedef volatile struct ALT_FPGAMGR_INTR_MSKED_STAT_s ALT_FPGAMGR_INTR_MSKED_STAT_t;
3708 #define ALT_FPGAMGR_INTR_MSKED_STAT_RESET 0x00000000
3710 #define ALT_FPGAMGR_INTR_MSKED_STAT_OFST 0x84
3756 #define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_LSB 0
3758 #define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_MSB 0
3760 #define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_WIDTH 1
3762 #define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_SET_MSK 0x00000001
3764 #define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_CLR_MSK 0xfffffffe
3766 #define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_RESET 0x1
3768 #define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_GET(value) (((value) & 0x00000001) >> 0)
3770 #define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_SET(value) (((value) << 0) & 0x00000001)
3779 #define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_LSB 1
3781 #define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_MSB 1
3783 #define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_WIDTH 1
3785 #define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_SET_MSK 0x00000002
3787 #define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_CLR_MSK 0xfffffffd
3789 #define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_RESET 0x1
3791 #define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_GET(value) (((value) & 0x00000002) >> 1)
3793 #define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_SET(value) (((value) << 1) & 0x00000002)
3802 #define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_LSB 2
3804 #define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_MSB 2
3806 #define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_WIDTH 1
3808 #define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_SET_MSK 0x00000004
3810 #define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_CLR_MSK 0xfffffffb
3812 #define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_RESET 0x1
3814 #define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_GET(value) (((value) & 0x00000004) >> 2)
3816 #define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_SET(value) (((value) << 2) & 0x00000004)
3825 #define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_LSB 3
3827 #define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_MSB 3
3829 #define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_WIDTH 1
3831 #define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_SET_MSK 0x00000008
3833 #define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_CLR_MSK 0xfffffff7
3835 #define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_RESET 0x1
3837 #define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_GET(value) (((value) & 0x00000008) >> 3)
3839 #define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_SET(value) (((value) << 3) & 0x00000008)
3848 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_LSB 4
3850 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_MSB 4
3852 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_WIDTH 1
3854 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_SET_MSK 0x00000010
3856 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_CLR_MSK 0xffffffef
3858 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_RESET 0x1
3860 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_GET(value) (((value) & 0x00000010) >> 4)
3862 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_SET(value) (((value) << 4) & 0x00000010)
3871 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_LSB 5
3873 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_MSB 5
3875 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_WIDTH 1
3877 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_SET_MSK 0x00000020
3879 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_CLR_MSK 0xffffffdf
3881 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_RESET 0x1
3883 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_GET(value) (((value) & 0x00000020) >> 5)
3885 #define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_SET(value) (((value) << 5) & 0x00000020)
3894 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_LSB 6
3896 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_MSB 6
3898 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_WIDTH 1
3900 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_SET_MSK 0x00000040
3902 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_CLR_MSK 0xffffffbf
3904 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_RESET 0x1
3906 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_GET(value) (((value) & 0x00000040) >> 6)
3908 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_SET(value) (((value) << 6) & 0x00000040)
3917 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_LSB 7
3919 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_MSB 7
3921 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_WIDTH 1
3923 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_SET_MSK 0x00000080
3925 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_CLR_MSK 0xffffff7f
3927 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_RESET 0x1
3929 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_GET(value) (((value) & 0x00000080) >> 7)
3931 #define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_SET(value) (((value) << 7) & 0x00000080)
3940 #define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_LSB 8
3942 #define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_MSB 8
3944 #define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_WIDTH 1
3946 #define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_SET_MSK 0x00000100
3948 #define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_CLR_MSK 0xfffffeff
3950 #define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_RESET 0x1
3952 #define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_GET(value) (((value) & 0x00000100) >> 8)
3954 #define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_SET(value) (((value) << 8) & 0x00000100)
3963 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_LSB 9
3965 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_MSB 9
3967 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_WIDTH 1
3969 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_SET_MSK 0x00000200
3971 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_CLR_MSK 0xfffffdff
3973 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_RESET 0x1
3975 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_GET(value) (((value) & 0x00000200) >> 9)
3977 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_SET(value) (((value) << 9) & 0x00000200)
3986 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_LSB 10
3988 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_MSB 10
3990 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_WIDTH 1
3992 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_SET_MSK 0x00000400
3994 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_CLR_MSK 0xfffffbff
3996 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_RESET 0x1
3998 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_GET(value) (((value) & 0x00000400) >> 10)
4000 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_SET(value) (((value) << 10) & 0x00000400)
4009 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_LSB 11
4011 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_MSB 11
4013 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_WIDTH 1
4015 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_SET_MSK 0x00000800
4017 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_CLR_MSK 0xfffff7ff
4019 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_RESET 0x1
4021 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_GET(value) (((value) & 0x00000800) >> 11)
4023 #define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_SET(value) (((value) << 11) & 0x00000800)
4032 #define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_LSB 12
4034 #define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_MSB 12
4036 #define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_WIDTH 1
4038 #define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_SET_MSK 0x00001000
4040 #define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_CLR_MSK 0xffffefff
4042 #define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_RESET 0x1
4044 #define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_GET(value) (((value) & 0x00001000) >> 12)
4046 #define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_SET(value) (((value) << 12) & 0x00001000)
4055 #define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_LSB 13
4057 #define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_MSB 13
4059 #define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_WIDTH 1
4061 #define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_SET_MSK 0x00002000
4063 #define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_CLR_MSK 0xffffdfff
4065 #define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_RESET 0x1
4067 #define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_GET(value) (((value) & 0x00002000) >> 13)
4069 #define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_SET(value) (((value) << 13) & 0x00002000)
4078 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_LSB 16
4080 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_MSB 16
4082 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_WIDTH 1
4084 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_SET_MSK 0x00010000
4086 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_CLR_MSK 0xfffeffff
4088 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_RESET 0x1
4090 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_GET(value) (((value) & 0x00010000) >> 16)
4092 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_SET(value) (((value) << 16) & 0x00010000)
4101 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_LSB 17
4103 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_MSB 17
4105 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_WIDTH 1
4107 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_SET_MSK 0x00020000
4109 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_CLR_MSK 0xfffdffff
4111 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_RESET 0x1
4113 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_GET(value) (((value) & 0x00020000) >> 17)
4115 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_SET(value) (((value) << 17) & 0x00020000)
4124 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_LSB 18
4126 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_MSB 18
4128 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_WIDTH 1
4130 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_SET_MSK 0x00040000
4132 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_CLR_MSK 0xfffbffff
4134 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_RESET 0x1
4136 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_GET(value) (((value) & 0x00040000) >> 18)
4138 #define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_SET(value) (((value) << 18) & 0x00040000)
4149 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_LSB 24
4151 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_MSB 24
4153 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_WIDTH 1
4155 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_SET_MSK 0x01000000
4157 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_CLR_MSK 0xfeffffff
4159 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_RESET 0x1
4161 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_GET(value) (((value) & 0x01000000) >> 24)
4163 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_SET(value) (((value) << 24) & 0x01000000)
4174 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_LSB 25
4176 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_MSB 25
4178 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_WIDTH 1
4180 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_SET_MSK 0x02000000
4182 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_CLR_MSK 0xfdffffff
4184 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_RESET 0x1
4186 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_GET(value) (((value) & 0x02000000) >> 25)
4188 #define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_SET(value) (((value) << 25) & 0x02000000)
4199 #define ALT_FPGAMGR_INTR_MSK_JTAGM_LSB 28
4201 #define ALT_FPGAMGR_INTR_MSK_JTAGM_MSB 28
4203 #define ALT_FPGAMGR_INTR_MSK_JTAGM_WIDTH 1
4205 #define ALT_FPGAMGR_INTR_MSK_JTAGM_SET_MSK 0x10000000
4207 #define ALT_FPGAMGR_INTR_MSK_JTAGM_CLR_MSK 0xefffffff
4209 #define ALT_FPGAMGR_INTR_MSK_JTAGM_RESET 0x1
4211 #define ALT_FPGAMGR_INTR_MSK_JTAGM_GET(value) (((value) & 0x10000000) >> 28)
4213 #define ALT_FPGAMGR_INTR_MSK_JTAGM_SET(value) (((value) << 28) & 0x10000000)
4224 #define ALT_FPGAMGR_INTR_MSK_EMR_LSB 29
4226 #define ALT_FPGAMGR_INTR_MSK_EMR_MSB 29
4228 #define ALT_FPGAMGR_INTR_MSK_EMR_WIDTH 1
4230 #define ALT_FPGAMGR_INTR_MSK_EMR_SET_MSK 0x20000000
4232 #define ALT_FPGAMGR_INTR_MSK_EMR_CLR_MSK 0xdfffffff
4234 #define ALT_FPGAMGR_INTR_MSK_EMR_RESET 0x1
4236 #define ALT_FPGAMGR_INTR_MSK_EMR_GET(value) (((value) & 0x20000000) >> 29)
4238 #define ALT_FPGAMGR_INTR_MSK_EMR_SET(value) (((value) << 29) & 0x20000000)
4240 #ifndef __ASSEMBLY__
4251 struct ALT_FPGAMGR_INTR_MSK_s
4253 uint32_t f2s_crc_error : 1;
4254 uint32_t f2s_early_usermode : 1;
4255 uint32_t f2s_usermode : 1;
4256 uint32_t f2s_initdone_oe : 1;
4257 uint32_t f2s_nstatus_pin : 1;
4258 uint32_t f2s_nstatus_oe : 1;
4259 uint32_t f2s_condone_pin : 1;
4260 uint32_t f2s_condone_oe : 1;
4261 uint32_t f2s_cvp_conf_done : 1;
4262 uint32_t f2s_pr_ready : 1;
4263 uint32_t f2s_pr_done : 1;
4264 uint32_t f2s_pr_error : 1;
4265 uint32_t f2s_nconfig_pin : 1;
4266 uint32_t f2s_nceo_oe : 1;
4268 uint32_t f2s_msel0 : 1;
4269 uint32_t f2s_msel1 : 1;
4270 uint32_t f2s_msel2 : 1;
4272 uint32_t imgcfg_FifoEmpty : 1;
4273 uint32_t imgcfg_FifoFull : 1;
4281 typedef volatile struct ALT_FPGAMGR_INTR_MSK_s ALT_FPGAMGR_INTR_MSK_t;
4285 #define ALT_FPGAMGR_INTR_MSK_RESET 0x33073fff
4287 #define ALT_FPGAMGR_INTR_MSK_OFST 0x88
4338 #define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_LSB 0
4340 #define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_MSB 0
4342 #define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_WIDTH 1
4344 #define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_SET_MSK 0x00000001
4346 #define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_CLR_MSK 0xfffffffe
4348 #define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_RESET 0x1
4350 #define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_GET(value) (((value) & 0x00000001) >> 0)
4352 #define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_SET(value) (((value) << 0) & 0x00000001)
4361 #define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_LSB 1
4363 #define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_MSB 1
4365 #define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_WIDTH 1
4367 #define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_SET_MSK 0x00000002
4369 #define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_CLR_MSK 0xfffffffd
4371 #define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_RESET 0x1
4373 #define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_GET(value) (((value) & 0x00000002) >> 1)
4375 #define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_SET(value) (((value) << 1) & 0x00000002)
4384 #define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_LSB 2
4386 #define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_MSB 2
4388 #define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_WIDTH 1
4390 #define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_SET_MSK 0x00000004
4392 #define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_CLR_MSK 0xfffffffb
4394 #define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_RESET 0x1
4396 #define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_GET(value) (((value) & 0x00000004) >> 2)
4398 #define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_SET(value) (((value) << 2) & 0x00000004)
4407 #define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_LSB 3
4409 #define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_MSB 3
4411 #define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_WIDTH 1
4413 #define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_SET_MSK 0x00000008
4415 #define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_CLR_MSK 0xfffffff7
4417 #define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_RESET 0x1
4419 #define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_GET(value) (((value) & 0x00000008) >> 3)
4421 #define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_SET(value) (((value) << 3) & 0x00000008)
4430 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_LSB 4
4432 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_MSB 4
4434 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_WIDTH 1
4436 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_SET_MSK 0x00000010
4438 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_CLR_MSK 0xffffffef
4440 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_RESET 0x1
4442 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_GET(value) (((value) & 0x00000010) >> 4)
4444 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_SET(value) (((value) << 4) & 0x00000010)
4453 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_LSB 5
4455 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_MSB 5
4457 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_WIDTH 1
4459 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_SET_MSK 0x00000020
4461 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_CLR_MSK 0xffffffdf
4463 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_RESET 0x1
4465 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_GET(value) (((value) & 0x00000020) >> 5)
4467 #define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_SET(value) (((value) << 5) & 0x00000020)
4476 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_LSB 6
4478 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_MSB 6
4480 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_WIDTH 1
4482 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_SET_MSK 0x00000040
4484 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_CLR_MSK 0xffffffbf
4486 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_RESET 0x1
4488 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_GET(value) (((value) & 0x00000040) >> 6)
4490 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_SET(value) (((value) << 6) & 0x00000040)
4499 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_LSB 7
4501 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_MSB 7
4503 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_WIDTH 1
4505 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_SET_MSK 0x00000080
4507 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_CLR_MSK 0xffffff7f
4509 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_RESET 0x1
4511 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_GET(value) (((value) & 0x00000080) >> 7)
4513 #define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_SET(value) (((value) << 7) & 0x00000080)
4522 #define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_LSB 8
4524 #define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_MSB 8
4526 #define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_WIDTH 1
4528 #define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_SET_MSK 0x00000100
4530 #define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_CLR_MSK 0xfffffeff
4532 #define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_RESET 0x1
4534 #define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_GET(value) (((value) & 0x00000100) >> 8)
4536 #define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_SET(value) (((value) << 8) & 0x00000100)
4545 #define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_LSB 9
4547 #define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_MSB 9
4549 #define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_WIDTH 1
4551 #define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_SET_MSK 0x00000200
4553 #define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_CLR_MSK 0xfffffdff
4555 #define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_RESET 0x1
4557 #define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_GET(value) (((value) & 0x00000200) >> 9)
4559 #define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_SET(value) (((value) << 9) & 0x00000200)
4568 #define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_LSB 10
4570 #define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_MSB 10
4572 #define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_WIDTH 1
4574 #define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_SET_MSK 0x00000400
4576 #define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_CLR_MSK 0xfffffbff
4578 #define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_RESET 0x1
4580 #define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_GET(value) (((value) & 0x00000400) >> 10)
4582 #define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_SET(value) (((value) << 10) & 0x00000400)
4591 #define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_LSB 11
4593 #define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_MSB 11
4595 #define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_WIDTH 1
4597 #define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_SET_MSK 0x00000800
4599 #define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_CLR_MSK 0xfffff7ff
4601 #define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_RESET 0x1
4603 #define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_GET(value) (((value) & 0x00000800) >> 11)
4605 #define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_SET(value) (((value) << 11) & 0x00000800)
4614 #define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_LSB 12
4616 #define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_MSB 12
4618 #define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_WIDTH 1
4620 #define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_SET_MSK 0x00001000
4622 #define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_CLR_MSK 0xffffefff
4624 #define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_RESET 0x1
4626 #define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_GET(value) (((value) & 0x00001000) >> 12)
4628 #define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_SET(value) (((value) << 12) & 0x00001000)
4637 #define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_LSB 13
4639 #define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_MSB 13
4641 #define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_WIDTH 1
4643 #define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_SET_MSK 0x00002000
4645 #define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_CLR_MSK 0xffffdfff
4647 #define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_RESET 0x1
4649 #define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_GET(value) (((value) & 0x00002000) >> 13)
4651 #define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_SET(value) (((value) << 13) & 0x00002000)
4660 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_LSB 16
4662 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_MSB 16
4664 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_WIDTH 1
4666 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_SET_MSK 0x00010000
4668 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_CLR_MSK 0xfffeffff
4670 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_RESET 0x1
4672 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_GET(value) (((value) & 0x00010000) >> 16)
4674 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_SET(value) (((value) << 16) & 0x00010000)
4683 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_LSB 17
4685 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_MSB 17
4687 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_WIDTH 1
4689 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_SET_MSK 0x00020000
4691 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_CLR_MSK 0xfffdffff
4693 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_RESET 0x1
4695 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_GET(value) (((value) & 0x00020000) >> 17)
4697 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_SET(value) (((value) << 17) & 0x00020000)
4706 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_LSB 18
4708 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_MSB 18
4710 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_WIDTH 1
4712 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_SET_MSK 0x00040000
4714 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_CLR_MSK 0xfffbffff
4716 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_RESET 0x1
4718 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_GET(value) (((value) & 0x00040000) >> 18)
4720 #define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_SET(value) (((value) << 18) & 0x00040000)
4731 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_LSB 24
4733 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_MSB 24
4735 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_WIDTH 1
4737 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_SET_MSK 0x01000000
4739 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_CLR_MSK 0xfeffffff
4741 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_RESET 0x1
4743 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_GET(value) (((value) & 0x01000000) >> 24)
4745 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_SET(value) (((value) << 24) & 0x01000000)
4756 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_LSB 25
4758 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_MSB 25
4760 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_WIDTH 1
4762 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_SET_MSK 0x02000000
4764 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_CLR_MSK 0xfdffffff
4766 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_RESET 0x1
4768 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_GET(value) (((value) & 0x02000000) >> 25)
4770 #define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_SET(value) (((value) << 25) & 0x02000000)
4781 #define ALT_FPGAMGR_INTR_POL_JTAGM_LSB 28
4783 #define ALT_FPGAMGR_INTR_POL_JTAGM_MSB 28
4785 #define ALT_FPGAMGR_INTR_POL_JTAGM_WIDTH 1
4787 #define ALT_FPGAMGR_INTR_POL_JTAGM_SET_MSK 0x10000000
4789 #define ALT_FPGAMGR_INTR_POL_JTAGM_CLR_MSK 0xefffffff
4791 #define ALT_FPGAMGR_INTR_POL_JTAGM_RESET 0x1
4793 #define ALT_FPGAMGR_INTR_POL_JTAGM_GET(value) (((value) & 0x10000000) >> 28)
4795 #define ALT_FPGAMGR_INTR_POL_JTAGM_SET(value) (((value) << 28) & 0x10000000)
4806 #define ALT_FPGAMGR_INTR_POL_EMR_LSB 29
4808 #define ALT_FPGAMGR_INTR_POL_EMR_MSB 29
4810 #define ALT_FPGAMGR_INTR_POL_EMR_WIDTH 1
4812 #define ALT_FPGAMGR_INTR_POL_EMR_SET_MSK 0x20000000
4814 #define ALT_FPGAMGR_INTR_POL_EMR_CLR_MSK 0xdfffffff
4816 #define ALT_FPGAMGR_INTR_POL_EMR_RESET 0x1
4818 #define ALT_FPGAMGR_INTR_POL_EMR_GET(value) (((value) & 0x20000000) >> 29)
4820 #define ALT_FPGAMGR_INTR_POL_EMR_SET(value) (((value) << 29) & 0x20000000)
4822 #ifndef __ASSEMBLY__
4833 struct ALT_FPGAMGR_INTR_POL_s
4835 uint32_t f2s_crc_error : 1;
4836 uint32_t f2s_early_usermode : 1;
4837 uint32_t f2s_usermode : 1;
4838 uint32_t f2s_initdone_oe : 1;
4839 uint32_t f2s_nstatus_pin : 1;
4840 uint32_t f2s_nstatus_oe : 1;
4841 uint32_t f2s_condone_pin : 1;
4842 uint32_t f2s_condone_oe : 1;
4843 uint32_t f2s_cvp_conf_done : 1;
4844 uint32_t f2s_pr_ready : 1;
4845 uint32_t f2s_pr_done : 1;
4846 uint32_t f2s_pr_error : 1;
4847 uint32_t f2s_nconfig_pin : 1;
4848 uint32_t f2s_nceo_oe : 1;
4850 uint32_t f2s_msel0 : 1;
4851 uint32_t f2s_msel1 : 1;
4852 uint32_t f2s_msel2 : 1;
4854 uint32_t imgcfg_FifoEmpty : 1;
4855 uint32_t imgcfg_FifoFull : 1;
4863 typedef volatile struct ALT_FPGAMGR_INTR_POL_s ALT_FPGAMGR_INTR_POL_t;
4867 #define ALT_FPGAMGR_INTR_POL_RESET 0x33073fff
4869 #define ALT_FPGAMGR_INTR_POL_OFST 0x8c
4896 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_LSB 0
4898 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_MSB 7
4900 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_WIDTH 8
4902 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_SET_MSK 0x000000ff
4904 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_CLR_MSK 0xffffff00
4906 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_RESET 0x0
4908 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_GET(value) (((value) & 0x000000ff) >> 0)
4910 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_SET(value) (((value) << 0) & 0x000000ff)
4934 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_E_DIS 0x0
4940 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_E_EN 0x1
4943 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_LSB 8
4945 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_MSB 8
4947 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_WIDTH 1
4949 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_SET_MSK 0x00000100
4951 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_CLR_MSK 0xfffffeff
4953 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_RESET 0x0
4955 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_GET(value) (((value) & 0x00000100) >> 8)
4957 #define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_SET(value) (((value) << 8) & 0x00000100)
4968 #define ALT_FPGAMGR_DMA_CFG_CLRFIFO_LSB 16
4970 #define ALT_FPGAMGR_DMA_CFG_CLRFIFO_MSB 16
4972 #define ALT_FPGAMGR_DMA_CFG_CLRFIFO_WIDTH 1
4974 #define ALT_FPGAMGR_DMA_CFG_CLRFIFO_SET_MSK 0x00010000
4976 #define ALT_FPGAMGR_DMA_CFG_CLRFIFO_CLR_MSK 0xfffeffff
4978 #define ALT_FPGAMGR_DMA_CFG_CLRFIFO_RESET 0x0
4980 #define ALT_FPGAMGR_DMA_CFG_CLRFIFO_GET(value) (((value) & 0x00010000) >> 16)
4982 #define ALT_FPGAMGR_DMA_CFG_CLRFIFO_SET(value) (((value) << 16) & 0x00010000)
4984 #ifndef __ASSEMBLY__
4995 struct ALT_FPGAMGR_DMA_CFG_s
4997 uint32_t dmareq_level : 8;
4998 uint32_t dmareq_enable : 1;
5000 uint32_t clearFifo : 1;
5005 typedef volatile struct ALT_FPGAMGR_DMA_CFG_s ALT_FPGAMGR_DMA_CFG_t;
5009 #define ALT_FPGAMGR_DMA_CFG_RESET 0x00000000
5011 #define ALT_FPGAMGR_DMA_CFG_OFST 0x90
5039 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_LSB 0
5041 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_MSB 7
5043 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_WIDTH 8
5045 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_SET_MSK 0x000000ff
5047 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_CLR_MSK 0xffffff00
5049 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_RESET 0x0
5051 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_GET(value) (((value) & 0x000000ff) >> 0)
5053 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_SET(value) (((value) << 0) & 0x000000ff)
5068 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_LSB 8
5070 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_MSB 8
5072 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_WIDTH 1
5074 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_SET_MSK 0x00000100
5076 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_CLR_MSK 0xfffffeff
5078 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_RESET 0x0
5080 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_GET(value) (((value) & 0x00000100) >> 8)
5082 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_SET(value) (((value) << 8) & 0x00000100)
5097 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_LSB 9
5099 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_MSB 9
5101 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_WIDTH 1
5103 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_SET_MSK 0x00000200
5105 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_CLR_MSK 0xfffffdff
5107 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_RESET 0x1
5109 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_GET(value) (((value) & 0x00000200) >> 9)
5111 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_SET(value) (((value) << 9) & 0x00000200)
5113 #ifndef __ASSEMBLY__
5124 struct ALT_FPGAMGR_IMGCFG_FIFO_STAT_s
5126 uint32_t FifoLevel : 8;
5127 uint32_t FifoFull : 1;
5128 uint32_t FifoEmpty : 1;
5133 typedef volatile struct ALT_FPGAMGR_IMGCFG_FIFO_STAT_s ALT_FPGAMGR_IMGCFG_FIFO_STAT_t;
5137 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_RESET 0x00000200
5139 #define ALT_FPGAMGR_IMGCFG_FIFO_STAT_OFST 0x94
5141 #ifndef __ASSEMBLY__
5152 struct ALT_FPGAMGR_s
5154 volatile uint32_t _pad_0x0_0x7[2];
5155 ALT_FPGAMGR_DCLKCNT_t dclkcnt;
5156 ALT_FPGAMGR_DCLKSTAT_t dclkstat;
5157 ALT_FPGAMGR_GPO_t gpo;
5158 ALT_FPGAMGR_GPI_t gpi;
5159 ALT_FPGAMGR_MISCI_t misci;
5160 volatile uint32_t _pad_0x1c_0x2f[5];
5161 ALT_FPGAMGR_EMR_DATA0_t emr_data0;
5162 ALT_FPGAMGR_EMR_DATA1_t emr_data1;
5163 ALT_FPGAMGR_EMR_DATA2_t emr_data2;
5164 ALT_FPGAMGR_EMR_DATA3_t emr_data3;
5165 ALT_FPGAMGR_EMR_DATA4_t emr_data4;
5166 ALT_FPGAMGR_EMR_DATA5_t emr_data5;
5167 ALT_FPGAMGR_EMR_VALID_t emr_valid;
5168 ALT_FPGAMGR_EMR_EN_t emr_en;
5169 ALT_FPGAMGR_JTAG_CFG_t jtag_config;
5170 ALT_FPGAMGR_JTAG_STAT_t jtag_status;
5171 ALT_FPGAMGR_JTAG_KICK_t jtag_kick;
5172 volatile uint32_t _pad_0x5c_0x5f;
5173 ALT_FPGAMGR_JTAG_DATA_W_t jtag_data_w;
5174 ALT_FPGAMGR_JTAG_DATA_R_t jtag_data_r;
5175 volatile uint32_t _pad_0x68_0x6f[2];
5176 ALT_FPGAMGR_IMGCFG_CTL_00_t imgcfg_ctrl_00;
5177 ALT_FPGAMGR_IMGCFG_CTL_01_t imgcfg_ctrl_01;
5178 ALT_FPGAMGR_IMGCFG_CTL_02_t imgcfg_ctrl_02;
5179 volatile uint32_t _pad_0x7c_0x7f;
5180 ALT_FPGAMGR_IMGCFG_STAT_t imgcfg_stat;
5181 ALT_FPGAMGR_INTR_MSKED_STAT_t intr_masked_status;
5182 ALT_FPGAMGR_INTR_MSK_t intr_mask;
5183 ALT_FPGAMGR_INTR_POL_t intr_polarity;
5184 ALT_FPGAMGR_DMA_CFG_t dma_config;
5185 ALT_FPGAMGR_IMGCFG_FIFO_STAT_t imgcfg_fifo_status;
5186 volatile uint32_t _pad_0x98_0x1000[986];
5190 typedef volatile struct ALT_FPGAMGR_s ALT_FPGAMGR_t;
5192 struct ALT_FPGAMGR_raw_s
5194 uint32_t _pad_0x0_0x7[2];
5195 volatile uint32_t dclkcnt;
5196 volatile uint32_t dclkstat;
5197 volatile uint32_t gpo;
5198 volatile uint32_t gpi;
5199 volatile uint32_t misci;
5200 uint32_t _pad_0x1c_0x2f[5];
5201 volatile uint32_t emr_data0;
5202 volatile uint32_t emr_data1;
5203 volatile uint32_t emr_data2;
5204 volatile uint32_t emr_data3;
5205 volatile uint32_t emr_data4;
5206 volatile uint32_t emr_data5;
5207 volatile uint32_t emr_valid;
5208 volatile uint32_t emr_en;
5209 volatile uint32_t jtag_config;
5210 volatile uint32_t jtag_status;
5211 volatile uint32_t jtag_kick;
5212 uint32_t _pad_0x5c_0x5f;
5213 volatile uint32_t jtag_data_w;
5214 volatile uint32_t jtag_data_r;
5215 uint32_t _pad_0x68_0x6f[2];
5216 volatile uint32_t imgcfg_ctrl_00;
5217 volatile uint32_t imgcfg_ctrl_01;
5218 volatile uint32_t imgcfg_ctrl_02;
5219 uint32_t _pad_0x7c_0x7f;
5220 volatile uint32_t imgcfg_stat;
5221 volatile uint32_t intr_masked_status;
5222 volatile uint32_t intr_mask;
5223 volatile uint32_t intr_polarity;
5224 volatile uint32_t dma_config;
5225 volatile uint32_t imgcfg_fifo_status;
5226 uint32_t _pad_0x98_0x1000[986];
5230 typedef volatile struct ALT_FPGAMGR_raw_s ALT_FPGAMGR_raw_t;