35 #ifndef __ALT_SOCAL_SYSMGR_H__
36 #define __ALT_SOCAL_SYSMGR_H__
85 #define ALT_SYSMGR_SILICONID1_REV_E_REV1 0x3
88 #define ALT_SYSMGR_SILICONID1_REV_LSB 0
90 #define ALT_SYSMGR_SILICONID1_REV_MSB 15
92 #define ALT_SYSMGR_SILICONID1_REV_WIDTH 16
94 #define ALT_SYSMGR_SILICONID1_REV_SET_MSK 0x0000ffff
96 #define ALT_SYSMGR_SILICONID1_REV_CLR_MSK 0xffff0000
98 #define ALT_SYSMGR_SILICONID1_REV_RESET 0x1
100 #define ALT_SYSMGR_SILICONID1_REV_GET(value) (((value) & 0x0000ffff) >> 0)
102 #define ALT_SYSMGR_SILICONID1_REV_SET(value) (((value) << 0) & 0x0000ffff)
122 #define ALT_SYSMGR_SILICONID1_ID_E_NIGHTFURY 0x3
125 #define ALT_SYSMGR_SILICONID1_ID_LSB 16
127 #define ALT_SYSMGR_SILICONID1_ID_MSB 31
129 #define ALT_SYSMGR_SILICONID1_ID_WIDTH 16
131 #define ALT_SYSMGR_SILICONID1_ID_SET_MSK 0xffff0000
133 #define ALT_SYSMGR_SILICONID1_ID_CLR_MSK 0x0000ffff
135 #define ALT_SYSMGR_SILICONID1_ID_RESET 0x1
137 #define ALT_SYSMGR_SILICONID1_ID_GET(value) (((value) & 0xffff0000) >> 16)
139 #define ALT_SYSMGR_SILICONID1_ID_SET(value) (((value) << 16) & 0xffff0000)
152 struct ALT_SYSMGR_SILICONID1_s
154 const uint32_t rev : 16;
155 const uint32_t
id : 16;
159 typedef volatile struct ALT_SYSMGR_SILICONID1_s ALT_SYSMGR_SILICONID1_t;
163 #define ALT_SYSMGR_SILICONID1_RESET 0x00010001
165 #define ALT_SYSMGR_SILICONID1_OFST 0x0
190 #define ALT_SYSMGR_SILICONID2_RSV_LSB 0
192 #define ALT_SYSMGR_SILICONID2_RSV_MSB 31
194 #define ALT_SYSMGR_SILICONID2_RSV_WIDTH 32
196 #define ALT_SYSMGR_SILICONID2_RSV_SET_MSK 0xffffffff
198 #define ALT_SYSMGR_SILICONID2_RSV_CLR_MSK 0x00000000
200 #define ALT_SYSMGR_SILICONID2_RSV_RESET 0x0
202 #define ALT_SYSMGR_SILICONID2_RSV_GET(value) (((value) & 0xffffffff) >> 0)
204 #define ALT_SYSMGR_SILICONID2_RSV_SET(value) (((value) << 0) & 0xffffffff)
217 struct ALT_SYSMGR_SILICONID2_s
219 const uint32_t rsv : 32;
223 typedef volatile struct ALT_SYSMGR_SILICONID2_s ALT_SYSMGR_SILICONID2_t;
227 #define ALT_SYSMGR_SILICONID2_RESET 0x00000000
229 #define ALT_SYSMGR_SILICONID2_OFST 0x4
270 #define ALT_SYSMGR_WDDBG_MOD_0_E_CONTINUE 0x0
275 #define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU0 0x1
280 #define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU1 0x2
285 #define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSEEITHER 0x3
288 #define ALT_SYSMGR_WDDBG_MOD_0_LSB 0
290 #define ALT_SYSMGR_WDDBG_MOD_0_MSB 1
292 #define ALT_SYSMGR_WDDBG_MOD_0_WIDTH 2
294 #define ALT_SYSMGR_WDDBG_MOD_0_SET_MSK 0x00000003
296 #define ALT_SYSMGR_WDDBG_MOD_0_CLR_MSK 0xfffffffc
298 #define ALT_SYSMGR_WDDBG_MOD_0_RESET 0x3
300 #define ALT_SYSMGR_WDDBG_MOD_0_GET(value) (((value) & 0x00000003) >> 0)
302 #define ALT_SYSMGR_WDDBG_MOD_0_SET(value) (((value) << 0) & 0x00000003)
326 #define ALT_SYSMGR_WDDBG_MOD_1_E_CONTINUE 0x0
331 #define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU0 0x1
336 #define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU1 0x2
341 #define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSEEITHER 0x3
344 #define ALT_SYSMGR_WDDBG_MOD_1_LSB 2
346 #define ALT_SYSMGR_WDDBG_MOD_1_MSB 3
348 #define ALT_SYSMGR_WDDBG_MOD_1_WIDTH 2
350 #define ALT_SYSMGR_WDDBG_MOD_1_SET_MSK 0x0000000c
352 #define ALT_SYSMGR_WDDBG_MOD_1_CLR_MSK 0xfffffff3
354 #define ALT_SYSMGR_WDDBG_MOD_1_RESET 0x3
356 #define ALT_SYSMGR_WDDBG_MOD_1_GET(value) (((value) & 0x0000000c) >> 2)
358 #define ALT_SYSMGR_WDDBG_MOD_1_SET(value) (((value) << 2) & 0x0000000c)
371 struct ALT_SYSMGR_WDDBG_s
379 typedef volatile struct ALT_SYSMGR_WDDBG_s ALT_SYSMGR_WDDBG_t;
383 #define ALT_SYSMGR_WDDBG_RESET 0x0000000f
385 #define ALT_SYSMGR_WDDBG_OFST 0x8
426 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_LSB 0
428 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_MSB 0
430 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_WIDTH 1
432 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_SET_MSK 0x00000001
434 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_CLR_MSK 0xfffffffe
436 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_RESET 0x0
438 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_GET(value) (((value) & 0x00000001) >> 0)
440 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_SET(value) (((value) << 0) & 0x00000001)
475 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_RSVDX 0x0
480 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_FPGA 0x1
485 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_NAND_FLSH_1_8V 0x2
490 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_NAND_FLSH_3_0V 0x3
495 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V 0x4
500 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V 0x5
505 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_QSPI_FLSH_1_8V 0x6
510 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_QSPI_FLSH_3_0V 0x7
513 #define ALT_SYSMGR_BOOT_FPGA_BSEL_LSB 4
515 #define ALT_SYSMGR_BOOT_FPGA_BSEL_MSB 6
517 #define ALT_SYSMGR_BOOT_FPGA_BSEL_WIDTH 3
519 #define ALT_SYSMGR_BOOT_FPGA_BSEL_SET_MSK 0x00000070
521 #define ALT_SYSMGR_BOOT_FPGA_BSEL_CLR_MSK 0xffffff8f
523 #define ALT_SYSMGR_BOOT_FPGA_BSEL_RESET 0x0
525 #define ALT_SYSMGR_BOOT_FPGA_BSEL_GET(value) (((value) & 0x00000070) >> 4)
527 #define ALT_SYSMGR_BOOT_FPGA_BSEL_SET(value) (((value) << 4) & 0x00000070)
555 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_RSVDX 0x0
560 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_FPGA 0x1
565 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_NAND_FLSH_1_8V 0x2
570 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_NAND_FLSH_3_0V 0x3
575 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V 0x4
580 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V 0x5
585 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_QSPI_FLSH_1_8V 0x6
590 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_QSPI_FLSH_3_0V 0x7
593 #define ALT_SYSMGR_BOOT_PIN_BSEL_LSB 8
595 #define ALT_SYSMGR_BOOT_PIN_BSEL_MSB 10
597 #define ALT_SYSMGR_BOOT_PIN_BSEL_WIDTH 3
599 #define ALT_SYSMGR_BOOT_PIN_BSEL_SET_MSK 0x00000700
601 #define ALT_SYSMGR_BOOT_PIN_BSEL_CLR_MSK 0xfffff8ff
603 #define ALT_SYSMGR_BOOT_PIN_BSEL_RESET 0x0
605 #define ALT_SYSMGR_BOOT_PIN_BSEL_GET(value) (((value) & 0x00000700) >> 8)
607 #define ALT_SYSMGR_BOOT_PIN_BSEL_SET(value) (((value) << 8) & 0x00000700)
634 #define ALT_SYSMGR_BOOT_BSEL_E_RSVDX 0x0
639 #define ALT_SYSMGR_BOOT_BSEL_E_FPGA 0x1
644 #define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V 0x2
649 #define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V 0x3
654 #define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V 0x4
659 #define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V 0x5
664 #define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V 0x6
669 #define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V 0x7
672 #define ALT_SYSMGR_BOOT_BSEL_LSB 12
674 #define ALT_SYSMGR_BOOT_BSEL_MSB 14
676 #define ALT_SYSMGR_BOOT_BSEL_WIDTH 3
678 #define ALT_SYSMGR_BOOT_BSEL_SET_MSK 0x00007000
680 #define ALT_SYSMGR_BOOT_BSEL_CLR_MSK 0xffff8fff
682 #define ALT_SYSMGR_BOOT_BSEL_RESET 0x0
684 #define ALT_SYSMGR_BOOT_BSEL_GET(value) (((value) & 0x00007000) >> 12)
686 #define ALT_SYSMGR_BOOT_BSEL_SET(value) (((value) << 12) & 0x00007000)
699 struct ALT_SYSMGR_BOOT_s
701 const uint32_t fpga_bsel_en : 1;
703 const uint32_t fpga_bsel : 3;
705 const uint32_t pin_bsel : 3;
707 const uint32_t bsel : 3;
712 typedef volatile struct ALT_SYSMGR_BOOT_s ALT_SYSMGR_BOOT_t;
716 #define ALT_SYSMGR_BOOT_RESET 0x00000000
718 #define ALT_SYSMGR_BOOT_OFST 0xc
756 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_LSB 0
758 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_MSB 0
760 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_WIDTH 1
762 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_SET_MSK 0x00000001
764 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_CLR_MSK 0xfffffffe
766 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_RESET 0x0
768 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
770 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
786 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_LSB 8
788 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_MSB 8
790 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_WIDTH 1
792 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_SET_MSK 0x00000100
794 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_CLR_MSK 0xfffffeff
796 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_RESET 0x0
798 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_GET(value) (((value) & 0x00000100) >> 8)
800 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_SET(value) (((value) << 8) & 0x00000100)
822 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_E_SINGLE_BIT 0x0
827 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_E_DOUBLE_BIT 0x1
830 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_LSB 16
832 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_MSB 16
834 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_WIDTH 1
836 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_SET_MSK 0x00010000
838 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_CLR_MSK 0xfffeffff
840 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_RESET 0x0
842 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_GET(value) (((value) & 0x00010000) >> 16)
844 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_SET(value) (((value) << 16) & 0x00010000)
857 struct ALT_SYSMGR_MPU_CTL_L2_ECC_s
863 uint32_t inj_type : 1;
868 typedef volatile struct ALT_SYSMGR_MPU_CTL_L2_ECC_s ALT_SYSMGR_MPU_CTL_L2_ECC_t;
872 #define ALT_SYSMGR_MPU_CTL_L2_ECC_RESET 0x00000000
874 #define ALT_SYSMGR_MPU_CTL_L2_ECC_OFST 0x10
921 #define ALT_SYSMGR_DMA_CHANSEL_0_E_FPGA 0x0
926 #define ALT_SYSMGR_DMA_CHANSEL_0_E_I2C4_TX 0x1
929 #define ALT_SYSMGR_DMA_CHANSEL_0_LSB 0
931 #define ALT_SYSMGR_DMA_CHANSEL_0_MSB 0
933 #define ALT_SYSMGR_DMA_CHANSEL_0_WIDTH 1
935 #define ALT_SYSMGR_DMA_CHANSEL_0_SET_MSK 0x00000001
937 #define ALT_SYSMGR_DMA_CHANSEL_0_CLR_MSK 0xfffffffe
939 #define ALT_SYSMGR_DMA_CHANSEL_0_RESET 0x0
941 #define ALT_SYSMGR_DMA_CHANSEL_0_GET(value) (((value) & 0x00000001) >> 0)
943 #define ALT_SYSMGR_DMA_CHANSEL_0_SET(value) (((value) << 0) & 0x00000001)
965 #define ALT_SYSMGR_DMA_CHANSEL_1_E_FPGA 0x0
970 #define ALT_SYSMGR_DMA_CHANSEL_1_E_I2C4_RX 0x1
973 #define ALT_SYSMGR_DMA_CHANSEL_1_LSB 4
975 #define ALT_SYSMGR_DMA_CHANSEL_1_MSB 4
977 #define ALT_SYSMGR_DMA_CHANSEL_1_WIDTH 1
979 #define ALT_SYSMGR_DMA_CHANSEL_1_SET_MSK 0x00000010
981 #define ALT_SYSMGR_DMA_CHANSEL_1_CLR_MSK 0xffffffef
983 #define ALT_SYSMGR_DMA_CHANSEL_1_RESET 0x0
985 #define ALT_SYSMGR_DMA_CHANSEL_1_GET(value) (((value) & 0x00000010) >> 4)
987 #define ALT_SYSMGR_DMA_CHANSEL_1_SET(value) (((value) << 4) & 0x00000010)
1009 #define ALT_SYSMGR_DMA_CHANSEL_2_E_FPGA 0x0
1014 #define ALT_SYSMGR_DMA_CHANSEL_2_E_SECMGR 0x1
1017 #define ALT_SYSMGR_DMA_CHANSEL_2_LSB 8
1019 #define ALT_SYSMGR_DMA_CHANSEL_2_MSB 8
1021 #define ALT_SYSMGR_DMA_CHANSEL_2_WIDTH 1
1023 #define ALT_SYSMGR_DMA_CHANSEL_2_SET_MSK 0x00000100
1025 #define ALT_SYSMGR_DMA_CHANSEL_2_CLR_MSK 0xfffffeff
1027 #define ALT_SYSMGR_DMA_CHANSEL_2_RESET 0x1
1029 #define ALT_SYSMGR_DMA_CHANSEL_2_GET(value) (((value) & 0x00000100) >> 8)
1031 #define ALT_SYSMGR_DMA_CHANSEL_2_SET(value) (((value) << 8) & 0x00000100)
1048 #define ALT_SYSMGR_DMA_MGR_NS_LSB 16
1050 #define ALT_SYSMGR_DMA_MGR_NS_MSB 16
1052 #define ALT_SYSMGR_DMA_MGR_NS_WIDTH 1
1054 #define ALT_SYSMGR_DMA_MGR_NS_SET_MSK 0x00010000
1056 #define ALT_SYSMGR_DMA_MGR_NS_CLR_MSK 0xfffeffff
1058 #define ALT_SYSMGR_DMA_MGR_NS_RESET 0x0
1060 #define ALT_SYSMGR_DMA_MGR_NS_GET(value) (((value) & 0x00010000) >> 16)
1062 #define ALT_SYSMGR_DMA_MGR_NS_SET(value) (((value) << 16) & 0x00010000)
1078 #define ALT_SYSMGR_DMA_IRQ_NS_LSB 24
1080 #define ALT_SYSMGR_DMA_IRQ_NS_MSB 31
1082 #define ALT_SYSMGR_DMA_IRQ_NS_WIDTH 8
1084 #define ALT_SYSMGR_DMA_IRQ_NS_SET_MSK 0xff000000
1086 #define ALT_SYSMGR_DMA_IRQ_NS_CLR_MSK 0x00ffffff
1088 #define ALT_SYSMGR_DMA_IRQ_NS_RESET 0x0
1090 #define ALT_SYSMGR_DMA_IRQ_NS_GET(value) (((value) & 0xff000000) >> 24)
1092 #define ALT_SYSMGR_DMA_IRQ_NS_SET(value) (((value) << 24) & 0xff000000)
1094 #ifndef __ASSEMBLY__
1105 struct ALT_SYSMGR_DMA_s
1107 uint32_t chansel_0 : 1;
1109 uint32_t chansel_1 : 1;
1111 uint32_t chansel_2 : 1;
1113 uint32_t mgr_ns : 1;
1115 uint32_t irq_ns : 8;
1119 typedef volatile struct ALT_SYSMGR_DMA_s ALT_SYSMGR_DMA_t;
1123 #define ALT_SYSMGR_DMA_RESET 0x00000100
1125 #define ALT_SYSMGR_DMA_OFST 0x20
1159 #define ALT_SYSMGR_DMA_PERIPH_NS_LSB 0
1161 #define ALT_SYSMGR_DMA_PERIPH_NS_MSB 31
1163 #define ALT_SYSMGR_DMA_PERIPH_NS_WIDTH 32
1165 #define ALT_SYSMGR_DMA_PERIPH_NS_SET_MSK 0xffffffff
1167 #define ALT_SYSMGR_DMA_PERIPH_NS_CLR_MSK 0x00000000
1169 #define ALT_SYSMGR_DMA_PERIPH_NS_RESET 0x0
1171 #define ALT_SYSMGR_DMA_PERIPH_NS_GET(value) (((value) & 0xffffffff) >> 0)
1173 #define ALT_SYSMGR_DMA_PERIPH_NS_SET(value) (((value) << 0) & 0xffffffff)
1175 #ifndef __ASSEMBLY__
1186 struct ALT_SYSMGR_DMA_PERIPH_s
1192 typedef volatile struct ALT_SYSMGR_DMA_PERIPH_s ALT_SYSMGR_DMA_PERIPH_t;
1196 #define ALT_SYSMGR_DMA_PERIPH_RESET 0x00000000
1198 #define ALT_SYSMGR_DMA_PERIPH_OFST 0x24
1241 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES0 0x0
1246 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES45 0x1
1251 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES90 0x2
1256 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES135 0x3
1261 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES180 0x4
1266 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES225 0x5
1271 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES270 0x6
1276 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES315 0x7
1279 #define ALT_SYSMGR_SDMMC_DRVSEL_LSB 0
1281 #define ALT_SYSMGR_SDMMC_DRVSEL_MSB 2
1283 #define ALT_SYSMGR_SDMMC_DRVSEL_WIDTH 3
1285 #define ALT_SYSMGR_SDMMC_DRVSEL_SET_MSK 0x00000007
1287 #define ALT_SYSMGR_SDMMC_DRVSEL_CLR_MSK 0xfffffff8
1289 #define ALT_SYSMGR_SDMMC_DRVSEL_RESET 0x0
1291 #define ALT_SYSMGR_SDMMC_DRVSEL_GET(value) (((value) & 0x00000007) >> 0)
1293 #define ALT_SYSMGR_SDMMC_DRVSEL_SET(value) (((value) << 0) & 0x00000007)
1320 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES0 0x0
1325 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES45 0x1
1330 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES90 0x2
1335 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES135 0x3
1340 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES180 0x4
1345 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES225 0x5
1350 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES270 0x6
1355 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES315 0x7
1358 #define ALT_SYSMGR_SDMMC_SMPLSEL_LSB 4
1360 #define ALT_SYSMGR_SDMMC_SMPLSEL_MSB 6
1362 #define ALT_SYSMGR_SDMMC_SMPLSEL_WIDTH 3
1364 #define ALT_SYSMGR_SDMMC_SMPLSEL_SET_MSK 0x00000070
1366 #define ALT_SYSMGR_SDMMC_SMPLSEL_CLR_MSK 0xffffff8f
1368 #define ALT_SYSMGR_SDMMC_SMPLSEL_RESET 0x0
1370 #define ALT_SYSMGR_SDMMC_SMPLSEL_GET(value) (((value) & 0x00000070) >> 4)
1372 #define ALT_SYSMGR_SDMMC_SMPLSEL_SET(value) (((value) << 4) & 0x00000070)
1374 #ifndef __ASSEMBLY__
1385 struct ALT_SYSMGR_SDMMC_s
1387 uint32_t drvsel : 3;
1389 uint32_t smplsel : 3;
1394 typedef volatile struct ALT_SYSMGR_SDMMC_s ALT_SYSMGR_SDMMC_t;
1398 #define ALT_SYSMGR_SDMMC_RESET 0x00000000
1400 #define ALT_SYSMGR_SDMMC_OFST 0x28
1505 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_LSB 0
1507 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_MSB 4
1509 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_WIDTH 5
1511 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_SET_MSK 0x0000001f
1513 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_CLR_MSK 0xffffffe0
1515 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_RESET 0x3
1517 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_GET(value) (((value) & 0x0000001f) >> 0)
1519 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_SET(value) (((value) << 0) & 0x0000001f)
1521 #ifndef __ASSEMBLY__
1532 struct ALT_SYSMGR_SDMMC_L3MST_s
1539 typedef volatile struct ALT_SYSMGR_SDMMC_L3MST_s ALT_SYSMGR_SDMMC_L3MST_t;
1543 #define ALT_SYSMGR_SDMMC_L3MST_RESET 0x00000003
1545 #define ALT_SYSMGR_SDMMC_L3MST_OFST 0x2c
1581 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_LSB 0
1583 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_MSB 0
1585 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_WIDTH 1
1587 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET_MSK 0x00000001
1589 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_CLR_MSK 0xfffffffe
1591 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_RESET 0x0
1593 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_GET(value) (((value) & 0x00000001) >> 0)
1595 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET(value) (((value) << 0) & 0x00000001)
1607 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_LSB 8
1609 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_MSB 8
1611 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_WIDTH 1
1613 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET_MSK 0x00000100
1615 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_CLR_MSK 0xfffffeff
1617 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_RESET 0x0
1619 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_GET(value) (((value) & 0x00000100) >> 8)
1621 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET(value) (((value) << 8) & 0x00000100)
1633 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_LSB 16
1635 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_MSB 16
1637 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_WIDTH 1
1639 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET_MSK 0x00010000
1641 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_CLR_MSK 0xfffeffff
1643 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_RESET 0x0
1645 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_GET(value) (((value) & 0x00010000) >> 16)
1647 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET(value) (((value) << 16) & 0x00010000)
1658 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_LSB 24
1660 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_MSB 24
1662 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_WIDTH 1
1664 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET_MSK 0x01000000
1666 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_CLR_MSK 0xfeffffff
1668 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_RESET 0x0
1670 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_GET(value) (((value) & 0x01000000) >> 24)
1672 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET(value) (((value) << 24) & 0x01000000)
1689 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_LSB 28
1691 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_MSB 28
1693 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_WIDTH 1
1695 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_SET_MSK 0x10000000
1697 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_CLR_MSK 0xefffffff
1699 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_RESET 0x0
1701 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_GET(value) (((value) & 0x10000000) >> 28)
1703 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_SET(value) (((value) << 28) & 0x10000000)
1705 #ifndef __ASSEMBLY__
1716 struct ALT_SYSMGR_NAND_BOOTSTRAP_s
1718 uint32_t noinit : 1;
1720 uint32_t noloadb0p0 : 1;
1722 uint32_t tworowaddr : 1;
1724 uint32_t page512 : 1;
1726 uint32_t page512_x16 : 1;
1731 typedef volatile struct ALT_SYSMGR_NAND_BOOTSTRAP_s ALT_SYSMGR_NAND_BOOTSTRAP_t;
1735 #define ALT_SYSMGR_NAND_BOOTSTRAP_RESET 0x00000000
1737 #define ALT_SYSMGR_NAND_BOOTSTRAP_OFST 0x30
1792 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF 0x0
1797 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_BUFF 0x1
1802 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_NONALLOC 0x2
1807 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
1812 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD1 0x4
1817 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD2 0x5
1822 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
1827 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
1832 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD3 0x8
1837 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD4 0x9
1842 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
1847 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
1852 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD5 0xc
1857 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD6 0xd
1862 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
1867 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
1870 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_LSB 0
1872 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_MSB 3
1874 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_WIDTH 4
1876 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_SET_MSK 0x0000000f
1878 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_CLR_MSK 0xfffffff0
1880 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_RESET 0x0
1882 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_GET(value) (((value) & 0x0000000f) >> 0)
1884 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_SET(value) (((value) << 0) & 0x0000000f)
1919 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF 0x0
1924 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_BUFF 0x1
1929 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_NONALLOC 0x2
1934 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
1939 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD1 0x4
1944 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD2 0x5
1949 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
1954 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
1959 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD3 0x8
1964 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD4 0x9
1969 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
1974 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
1979 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD5 0xc
1984 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD6 0xd
1989 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
1994 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
1997 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_LSB 4
1999 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_MSB 7
2001 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_WIDTH 4
2003 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_SET_MSK 0x000000f0
2005 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_CLR_MSK 0xffffff0f
2007 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_RESET 0x0
2009 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_GET(value) (((value) & 0x000000f0) >> 4)
2011 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_SET(value) (((value) << 4) & 0x000000f0)
2013 #ifndef __ASSEMBLY__
2024 struct ALT_SYSMGR_NAND_L3MST_s
2026 uint32_t arcache_0 : 4;
2027 uint32_t awcache_0 : 4;
2032 typedef volatile struct ALT_SYSMGR_NAND_L3MST_s ALT_SYSMGR_NAND_L3MST_t;
2036 #define ALT_SYSMGR_NAND_L3MST_RESET 0x00000000
2038 #define ALT_SYSMGR_NAND_L3MST_OFST 0x34
2102 #define ALT_SYSMGR_USB0_L3MST_HPROT_LSB 0
2104 #define ALT_SYSMGR_USB0_L3MST_HPROT_MSB 3
2106 #define ALT_SYSMGR_USB0_L3MST_HPROT_WIDTH 4
2108 #define ALT_SYSMGR_USB0_L3MST_HPROT_SET_MSK 0x0000000f
2110 #define ALT_SYSMGR_USB0_L3MST_HPROT_CLR_MSK 0xfffffff0
2112 #define ALT_SYSMGR_USB0_L3MST_HPROT_RESET 0x1
2114 #define ALT_SYSMGR_USB0_L3MST_HPROT_GET(value) (((value) & 0x0000000f) >> 0)
2116 #define ALT_SYSMGR_USB0_L3MST_HPROT_SET(value) (((value) << 0) & 0x0000000f)
2118 #ifndef __ASSEMBLY__
2129 struct ALT_SYSMGR_USB0_L3MST_s
2136 typedef volatile struct ALT_SYSMGR_USB0_L3MST_s ALT_SYSMGR_USB0_L3MST_t;
2140 #define ALT_SYSMGR_USB0_L3MST_RESET 0x00000001
2142 #define ALT_SYSMGR_USB0_L3MST_OFST 0x38
2206 #define ALT_SYSMGR_USB1_L3MST_HPROT_LSB 0
2208 #define ALT_SYSMGR_USB1_L3MST_HPROT_MSB 3
2210 #define ALT_SYSMGR_USB1_L3MST_HPROT_WIDTH 4
2212 #define ALT_SYSMGR_USB1_L3MST_HPROT_SET_MSK 0x0000000f
2214 #define ALT_SYSMGR_USB1_L3MST_HPROT_CLR_MSK 0xfffffff0
2216 #define ALT_SYSMGR_USB1_L3MST_HPROT_RESET 0x1
2218 #define ALT_SYSMGR_USB1_L3MST_HPROT_GET(value) (((value) & 0x0000000f) >> 0)
2220 #define ALT_SYSMGR_USB1_L3MST_HPROT_SET(value) (((value) << 0) & 0x0000000f)
2222 #ifndef __ASSEMBLY__
2233 struct ALT_SYSMGR_USB1_L3MST_s
2240 typedef volatile struct ALT_SYSMGR_USB1_L3MST_s ALT_SYSMGR_USB1_L3MST_t;
2244 #define ALT_SYSMGR_USB1_L3MST_RESET 0x00000001
2246 #define ALT_SYSMGR_USB1_L3MST_OFST 0x3c
2287 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_E_EMAC_PTP_CLK 0x0
2292 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_E_F2S_PTP_REF_CLK 0x1
2295 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_LSB 0
2297 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_MSB 0
2299 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_WIDTH 1
2301 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_SET_MSK 0x00000001
2303 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_CLR_MSK 0xfffffffe
2305 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_RESET 0x0
2307 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_GET(value) (((value) & 0x00000001) >> 0)
2309 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_SET(value) (((value) << 0) & 0x00000001)
2311 #ifndef __ASSEMBLY__
2322 struct ALT_SYSMGR_EMAC_GLOB_s
2324 uint32_t ptp_clk_sel : 1;
2329 typedef volatile struct ALT_SYSMGR_EMAC_GLOB_s ALT_SYSMGR_EMAC_GLOB_t;
2333 #define ALT_SYSMGR_EMAC_GLOB_RESET 0x00000000
2335 #define ALT_SYSMGR_EMAC_GLOB_OFST 0x40
2390 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_E_GMII_MII 0x0
2395 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_E_RGMII 0x1
2400 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_E_RMII 0x2
2405 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_E_RST 0x3
2408 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_LSB 0
2410 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_MSB 1
2412 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_WIDTH 2
2414 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_SET_MSK 0x00000003
2416 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_CLR_MSK 0xfffffffc
2418 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_RESET 0x3
2420 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_GET(value) (((value) & 0x00000003) >> 0)
2422 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_SET(value) (((value) << 0) & 0x00000003)
2446 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_E_INTERNAL 0x0
2451 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_E_EXTERNAL 0x1
2454 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_LSB 8
2456 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_MSB 8
2458 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_WIDTH 1
2460 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_SET_MSK 0x00000100
2462 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_CLR_MSK 0xfffffeff
2464 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_RESET 0x0
2466 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_GET(value) (((value) & 0x00000100) >> 8)
2468 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_SET(value) (((value) << 8) & 0x00000100)
2491 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_E_L4_MP_CLK 0x0
2496 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_E_F2S_AP_CLK 0x1
2499 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_LSB 12
2501 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_MSB 12
2503 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_WIDTH 1
2505 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_SET_MSK 0x00001000
2507 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_CLR_MSK 0xffffefff
2509 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_RESET 0x0
2511 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_GET(value) (((value) & 0x00001000) >> 12)
2513 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_SET(value) (((value) << 12) & 0x00001000)
2550 #define ALT_SYSMGR_EMAC0_ARCACHE_E_NONCACHE_NONBUFF 0x0
2555 #define ALT_SYSMGR_EMAC0_ARCACHE_E_BUFF 0x1
2560 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_NONALLOC 0x2
2565 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_BUFF_NONALLOC 0x3
2570 #define ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD1 0x4
2575 #define ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD2 0x5
2580 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
2585 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRBACK_RDALLOC 0x7
2590 #define ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD3 0x8
2595 #define ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD4 0x9
2600 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
2605 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRBACK_WRALLOC 0xb
2610 #define ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD5 0xc
2615 #define ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD6 0xd
2620 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRTHRU_ALLOC 0xe
2625 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRBACK_ALLOC 0xf
2628 #define ALT_SYSMGR_EMAC0_ARCACHE_LSB 16
2630 #define ALT_SYSMGR_EMAC0_ARCACHE_MSB 19
2632 #define ALT_SYSMGR_EMAC0_ARCACHE_WIDTH 4
2634 #define ALT_SYSMGR_EMAC0_ARCACHE_SET_MSK 0x000f0000
2636 #define ALT_SYSMGR_EMAC0_ARCACHE_CLR_MSK 0xfff0ffff
2638 #define ALT_SYSMGR_EMAC0_ARCACHE_RESET 0x0
2640 #define ALT_SYSMGR_EMAC0_ARCACHE_GET(value) (((value) & 0x000f0000) >> 16)
2642 #define ALT_SYSMGR_EMAC0_ARCACHE_SET(value) (((value) << 16) & 0x000f0000)
2679 #define ALT_SYSMGR_EMAC0_AWCACHE_E_NONCACHE_NONBUFF 0x0
2684 #define ALT_SYSMGR_EMAC0_AWCACHE_E_BUFF 0x1
2689 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_NONALLOC 0x2
2694 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_BUFF_NONALLOC 0x3
2699 #define ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD1 0x4
2704 #define ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD2 0x5
2709 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
2714 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRBACK_RDALLOC 0x7
2719 #define ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD3 0x8
2724 #define ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD4 0x9
2729 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
2734 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRBACK_WRALLOC 0xb
2739 #define ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD5 0xc
2744 #define ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD6 0xd
2749 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRTHRU_ALLOC 0xe
2754 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRBACK_ALLOC 0xf
2757 #define ALT_SYSMGR_EMAC0_AWCACHE_LSB 20
2759 #define ALT_SYSMGR_EMAC0_AWCACHE_MSB 23
2761 #define ALT_SYSMGR_EMAC0_AWCACHE_WIDTH 4
2763 #define ALT_SYSMGR_EMAC0_AWCACHE_SET_MSK 0x00f00000
2765 #define ALT_SYSMGR_EMAC0_AWCACHE_CLR_MSK 0xff0fffff
2767 #define ALT_SYSMGR_EMAC0_AWCACHE_RESET 0x0
2769 #define ALT_SYSMGR_EMAC0_AWCACHE_GET(value) (((value) & 0x00f00000) >> 20)
2771 #define ALT_SYSMGR_EMAC0_AWCACHE_SET(value) (((value) << 20) & 0x00f00000)
2813 #define ALT_SYSMGR_EMAC0_ARPROT_E_SECURE_NORMAL 0x0
2819 #define ALT_SYSMGR_EMAC0_ARPROT_E_SECURE_PRIVILEGED 0x1
2825 #define ALT_SYSMGR_EMAC0_ARPROT_E_NONSECURE_NORMAL 0x2
2831 #define ALT_SYSMGR_EMAC0_ARPROT_E_NONSECURE_PRIVILEGED 0x3
2834 #define ALT_SYSMGR_EMAC0_ARPROT_LSB 24
2836 #define ALT_SYSMGR_EMAC0_ARPROT_MSB 25
2838 #define ALT_SYSMGR_EMAC0_ARPROT_WIDTH 2
2840 #define ALT_SYSMGR_EMAC0_ARPROT_SET_MSK 0x03000000
2842 #define ALT_SYSMGR_EMAC0_ARPROT_CLR_MSK 0xfcffffff
2844 #define ALT_SYSMGR_EMAC0_ARPROT_RESET 0x2
2846 #define ALT_SYSMGR_EMAC0_ARPROT_GET(value) (((value) & 0x03000000) >> 24)
2848 #define ALT_SYSMGR_EMAC0_ARPROT_SET(value) (((value) << 24) & 0x03000000)
2890 #define ALT_SYSMGR_EMAC0_AWPROT_E_SECURE_NORMAL 0x0
2896 #define ALT_SYSMGR_EMAC0_AWPROT_E_SECURE_PRIVILEGED 0x1
2902 #define ALT_SYSMGR_EMAC0_AWPROT_E_NONSECURE_NORMAL 0x2
2908 #define ALT_SYSMGR_EMAC0_AWPROT_E_NONSECURE_PRIVILEGED 0x3
2911 #define ALT_SYSMGR_EMAC0_AWPROT_LSB 27
2913 #define ALT_SYSMGR_EMAC0_AWPROT_MSB 28
2915 #define ALT_SYSMGR_EMAC0_AWPROT_WIDTH 2
2917 #define ALT_SYSMGR_EMAC0_AWPROT_SET_MSK 0x18000000
2919 #define ALT_SYSMGR_EMAC0_AWPROT_CLR_MSK 0xe7ffffff
2921 #define ALT_SYSMGR_EMAC0_AWPROT_RESET 0x2
2923 #define ALT_SYSMGR_EMAC0_AWPROT_GET(value) (((value) & 0x18000000) >> 27)
2925 #define ALT_SYSMGR_EMAC0_AWPROT_SET(value) (((value) << 27) & 0x18000000)
2948 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN 0x0
2953 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN 0x1
2956 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_LSB 30
2958 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_MSB 30
2960 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_WIDTH 1
2962 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_SET_MSK 0x40000000
2964 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_CLR_MSK 0xbfffffff
2966 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_RESET 0x0
2968 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_GET(value) (((value) & 0x40000000) >> 30)
2970 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_SET(value) (((value) << 30) & 0x40000000)
2981 #define ALT_SYSMGR_EMAC0_AXI_DIS_LSB 31
2983 #define ALT_SYSMGR_EMAC0_AXI_DIS_MSB 31
2985 #define ALT_SYSMGR_EMAC0_AXI_DIS_WIDTH 1
2987 #define ALT_SYSMGR_EMAC0_AXI_DIS_SET_MSK 0x80000000
2989 #define ALT_SYSMGR_EMAC0_AXI_DIS_CLR_MSK 0x7fffffff
2991 #define ALT_SYSMGR_EMAC0_AXI_DIS_RESET 0x0
2993 #define ALT_SYSMGR_EMAC0_AXI_DIS_GET(value) (((value) & 0x80000000) >> 31)
2995 #define ALT_SYSMGR_EMAC0_AXI_DIS_SET(value) (((value) << 31) & 0x80000000)
2997 #ifndef __ASSEMBLY__
3008 struct ALT_SYSMGR_EMAC0_s
3010 uint32_t phy_intf_sel : 2;
3012 uint32_t ptp_ref_sel : 1;
3014 uint32_t app_clk_sel : 1;
3016 uint32_t arcache : 4;
3017 uint32_t awcache : 4;
3018 uint32_t arprot : 2;
3020 uint32_t awprot : 2;
3022 uint32_t sbd_data_endianness : 1;
3023 uint32_t axi_disable : 1;
3027 typedef volatile struct ALT_SYSMGR_EMAC0_s ALT_SYSMGR_EMAC0_t;
3031 #define ALT_SYSMGR_EMAC0_RESET 0x12000003
3033 #define ALT_SYSMGR_EMAC0_OFST 0x44
3088 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_E_GMII_MII 0x0
3093 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_E_RGMII 0x1
3098 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_E_RMII 0x2
3103 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_E_RST 0x3
3106 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_LSB 0
3108 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_MSB 1
3110 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_WIDTH 2
3112 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_SET_MSK 0x00000003
3114 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_CLR_MSK 0xfffffffc
3116 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_RESET 0x3
3118 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_GET(value) (((value) & 0x00000003) >> 0)
3120 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_SET(value) (((value) << 0) & 0x00000003)
3144 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_E_INTERNAL 0x0
3149 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_E_EXTERNAL 0x1
3152 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_LSB 8
3154 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_MSB 8
3156 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_WIDTH 1
3158 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_SET_MSK 0x00000100
3160 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_CLR_MSK 0xfffffeff
3162 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_RESET 0x0
3164 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_GET(value) (((value) & 0x00000100) >> 8)
3166 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_SET(value) (((value) << 8) & 0x00000100)
3189 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_E_L4_MP_CLK 0x0
3194 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_E_F2S_AP_CLK 0x1
3197 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_LSB 12
3199 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_MSB 12
3201 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_WIDTH 1
3203 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_SET_MSK 0x00001000
3205 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_CLR_MSK 0xffffefff
3207 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_RESET 0x0
3209 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_GET(value) (((value) & 0x00001000) >> 12)
3211 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_SET(value) (((value) << 12) & 0x00001000)
3248 #define ALT_SYSMGR_EMAC1_ARCACHE_E_NONCACHE_NONBUFF 0x0
3253 #define ALT_SYSMGR_EMAC1_ARCACHE_E_BUFF 0x1
3258 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_NONALLOC 0x2
3263 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_BUFF_NONALLOC 0x3
3268 #define ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD1 0x4
3273 #define ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD2 0x5
3278 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
3283 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRBACK_RDALLOC 0x7
3288 #define ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD3 0x8
3293 #define ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD4 0x9
3298 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
3303 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRBACK_WRALLOC 0xb
3308 #define ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD5 0xc
3313 #define ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD6 0xd
3318 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRTHRU_ALLOC 0xe
3323 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRBACK_ALLOC 0xf
3326 #define ALT_SYSMGR_EMAC1_ARCACHE_LSB 16
3328 #define ALT_SYSMGR_EMAC1_ARCACHE_MSB 19
3330 #define ALT_SYSMGR_EMAC1_ARCACHE_WIDTH 4
3332 #define ALT_SYSMGR_EMAC1_ARCACHE_SET_MSK 0x000f0000
3334 #define ALT_SYSMGR_EMAC1_ARCACHE_CLR_MSK 0xfff0ffff
3336 #define ALT_SYSMGR_EMAC1_ARCACHE_RESET 0x0
3338 #define ALT_SYSMGR_EMAC1_ARCACHE_GET(value) (((value) & 0x000f0000) >> 16)
3340 #define ALT_SYSMGR_EMAC1_ARCACHE_SET(value) (((value) << 16) & 0x000f0000)
3377 #define ALT_SYSMGR_EMAC1_AWCACHE_E_NONCACHE_NONBUFF 0x0
3382 #define ALT_SYSMGR_EMAC1_AWCACHE_E_BUFF 0x1
3387 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_NONALLOC 0x2
3392 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_BUFF_NONALLOC 0x3
3397 #define ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD1 0x4
3402 #define ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD2 0x5
3407 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
3412 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRBACK_RDALLOC 0x7
3417 #define ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD3 0x8
3422 #define ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD4 0x9
3427 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
3432 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRBACK_WRALLOC 0xb
3437 #define ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD5 0xc
3442 #define ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD6 0xd
3447 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRTHRU_ALLOC 0xe
3452 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRBACK_ALLOC 0xf
3455 #define ALT_SYSMGR_EMAC1_AWCACHE_LSB 20
3457 #define ALT_SYSMGR_EMAC1_AWCACHE_MSB 23
3459 #define ALT_SYSMGR_EMAC1_AWCACHE_WIDTH 4
3461 #define ALT_SYSMGR_EMAC1_AWCACHE_SET_MSK 0x00f00000
3463 #define ALT_SYSMGR_EMAC1_AWCACHE_CLR_MSK 0xff0fffff
3465 #define ALT_SYSMGR_EMAC1_AWCACHE_RESET 0x0
3467 #define ALT_SYSMGR_EMAC1_AWCACHE_GET(value) (((value) & 0x00f00000) >> 20)
3469 #define ALT_SYSMGR_EMAC1_AWCACHE_SET(value) (((value) << 20) & 0x00f00000)
3511 #define ALT_SYSMGR_EMAC1_ARPROT_E_SECURE_NORMAL 0x0
3517 #define ALT_SYSMGR_EMAC1_ARPROT_E_SECURE_PRIVILEGED 0x1
3523 #define ALT_SYSMGR_EMAC1_ARPROT_E_NONSECURE_NORMAL 0x2
3529 #define ALT_SYSMGR_EMAC1_ARPROT_E_NONSECURE_PRIVILEGED 0x3
3532 #define ALT_SYSMGR_EMAC1_ARPROT_LSB 24
3534 #define ALT_SYSMGR_EMAC1_ARPROT_MSB 25
3536 #define ALT_SYSMGR_EMAC1_ARPROT_WIDTH 2
3538 #define ALT_SYSMGR_EMAC1_ARPROT_SET_MSK 0x03000000
3540 #define ALT_SYSMGR_EMAC1_ARPROT_CLR_MSK 0xfcffffff
3542 #define ALT_SYSMGR_EMAC1_ARPROT_RESET 0x2
3544 #define ALT_SYSMGR_EMAC1_ARPROT_GET(value) (((value) & 0x03000000) >> 24)
3546 #define ALT_SYSMGR_EMAC1_ARPROT_SET(value) (((value) << 24) & 0x03000000)
3588 #define ALT_SYSMGR_EMAC1_AWPROT_E_SECURE_NORMAL 0x0
3594 #define ALT_SYSMGR_EMAC1_AWPROT_E_SECURE_PRIVILEGED 0x1
3600 #define ALT_SYSMGR_EMAC1_AWPROT_E_NONSECURE_NORMAL 0x2
3606 #define ALT_SYSMGR_EMAC1_AWPROT_E_NONSECURE_PRIVILEGED 0x3
3609 #define ALT_SYSMGR_EMAC1_AWPROT_LSB 27
3611 #define ALT_SYSMGR_EMAC1_AWPROT_MSB 28
3613 #define ALT_SYSMGR_EMAC1_AWPROT_WIDTH 2
3615 #define ALT_SYSMGR_EMAC1_AWPROT_SET_MSK 0x18000000
3617 #define ALT_SYSMGR_EMAC1_AWPROT_CLR_MSK 0xe7ffffff
3619 #define ALT_SYSMGR_EMAC1_AWPROT_RESET 0x2
3621 #define ALT_SYSMGR_EMAC1_AWPROT_GET(value) (((value) & 0x18000000) >> 27)
3623 #define ALT_SYSMGR_EMAC1_AWPROT_SET(value) (((value) << 27) & 0x18000000)
3646 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN 0x0
3651 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN 0x1
3654 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_LSB 30
3656 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_MSB 30
3658 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_WIDTH 1
3660 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_SET_MSK 0x40000000
3662 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_CLR_MSK 0xbfffffff
3664 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_RESET 0x0
3666 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_GET(value) (((value) & 0x40000000) >> 30)
3668 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_SET(value) (((value) << 30) & 0x40000000)
3679 #define ALT_SYSMGR_EMAC1_AXI_DIS_LSB 31
3681 #define ALT_SYSMGR_EMAC1_AXI_DIS_MSB 31
3683 #define ALT_SYSMGR_EMAC1_AXI_DIS_WIDTH 1
3685 #define ALT_SYSMGR_EMAC1_AXI_DIS_SET_MSK 0x80000000
3687 #define ALT_SYSMGR_EMAC1_AXI_DIS_CLR_MSK 0x7fffffff
3689 #define ALT_SYSMGR_EMAC1_AXI_DIS_RESET 0x0
3691 #define ALT_SYSMGR_EMAC1_AXI_DIS_GET(value) (((value) & 0x80000000) >> 31)
3693 #define ALT_SYSMGR_EMAC1_AXI_DIS_SET(value) (((value) << 31) & 0x80000000)
3695 #ifndef __ASSEMBLY__
3706 struct ALT_SYSMGR_EMAC1_s
3708 uint32_t phy_intf_sel : 2;
3710 uint32_t ptp_ref_sel : 1;
3712 uint32_t app_clk_sel : 1;
3714 uint32_t arcache : 4;
3715 uint32_t awcache : 4;
3716 uint32_t arprot : 2;
3718 uint32_t awprot : 2;
3720 uint32_t sbd_data_endianness : 1;
3721 uint32_t axi_disable : 1;
3725 typedef volatile struct ALT_SYSMGR_EMAC1_s ALT_SYSMGR_EMAC1_t;
3729 #define ALT_SYSMGR_EMAC1_RESET 0x12000003
3731 #define ALT_SYSMGR_EMAC1_OFST 0x48
3786 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_GMII_MII 0x0
3791 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_RGMII 0x1
3796 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_RMII 0x2
3801 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_RST 0x3
3804 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_LSB 0
3806 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_MSB 1
3808 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_WIDTH 2
3810 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_SET_MSK 0x00000003
3812 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_CLR_MSK 0xfffffffc
3814 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_RESET 0x3
3816 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_GET(value) (((value) & 0x00000003) >> 0)
3818 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_SET(value) (((value) << 0) & 0x00000003)
3842 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_E_INTERNAL 0x0
3847 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_E_EXTERNAL 0x1
3850 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_LSB 8
3852 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_MSB 8
3854 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_WIDTH 1
3856 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_SET_MSK 0x00000100
3858 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_CLR_MSK 0xfffffeff
3860 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_RESET 0x0
3862 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_GET(value) (((value) & 0x00000100) >> 8)
3864 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_SET(value) (((value) << 8) & 0x00000100)
3887 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_E_L4_MP_CLK 0x0
3892 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_E_F2S_AP_CLK 0x1
3895 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_LSB 12
3897 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_MSB 12
3899 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_WIDTH 1
3901 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_SET_MSK 0x00001000
3903 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_CLR_MSK 0xffffefff
3905 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_RESET 0x0
3907 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_GET(value) (((value) & 0x00001000) >> 12)
3909 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_SET(value) (((value) << 12) & 0x00001000)
3946 #define ALT_SYSMGR_EMAC2_ARCACHE_E_NONCACHE_NONBUFF 0x0
3951 #define ALT_SYSMGR_EMAC2_ARCACHE_E_BUFF 0x1
3956 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_NONALLOC 0x2
3961 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_BUFF_NONALLOC 0x3
3966 #define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD1 0x4
3971 #define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD2 0x5
3976 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
3981 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRBACK_RDALLOC 0x7
3986 #define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD3 0x8
3991 #define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD4 0x9
3996 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
4001 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRBACK_WRALLOC 0xb
4006 #define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD5 0xc
4011 #define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD6 0xd
4016 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRTHRU_ALLOC 0xe
4021 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRBACK_ALLOC 0xf
4024 #define ALT_SYSMGR_EMAC2_ARCACHE_LSB 16
4026 #define ALT_SYSMGR_EMAC2_ARCACHE_MSB 19
4028 #define ALT_SYSMGR_EMAC2_ARCACHE_WIDTH 4
4030 #define ALT_SYSMGR_EMAC2_ARCACHE_SET_MSK 0x000f0000
4032 #define ALT_SYSMGR_EMAC2_ARCACHE_CLR_MSK 0xfff0ffff
4034 #define ALT_SYSMGR_EMAC2_ARCACHE_RESET 0x0
4036 #define ALT_SYSMGR_EMAC2_ARCACHE_GET(value) (((value) & 0x000f0000) >> 16)
4038 #define ALT_SYSMGR_EMAC2_ARCACHE_SET(value) (((value) << 16) & 0x000f0000)
4075 #define ALT_SYSMGR_EMAC2_AWCACHE_E_NONCACHE_NONBUFF 0x0
4080 #define ALT_SYSMGR_EMAC2_AWCACHE_E_BUFF 0x1
4085 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_NONALLOC 0x2
4090 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_BUFF_NONALLOC 0x3
4095 #define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD1 0x4
4100 #define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD2 0x5
4105 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
4110 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRBACK_RDALLOC 0x7
4115 #define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD3 0x8
4120 #define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD4 0x9
4125 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
4130 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRBACK_WRALLOC 0xb
4135 #define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD5 0xc
4140 #define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD6 0xd
4145 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRTHRU_ALLOC 0xe
4150 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRBACK_ALLOC 0xf
4153 #define ALT_SYSMGR_EMAC2_AWCACHE_LSB 20
4155 #define ALT_SYSMGR_EMAC2_AWCACHE_MSB 23
4157 #define ALT_SYSMGR_EMAC2_AWCACHE_WIDTH 4
4159 #define ALT_SYSMGR_EMAC2_AWCACHE_SET_MSK 0x00f00000
4161 #define ALT_SYSMGR_EMAC2_AWCACHE_CLR_MSK 0xff0fffff
4163 #define ALT_SYSMGR_EMAC2_AWCACHE_RESET 0x0
4165 #define ALT_SYSMGR_EMAC2_AWCACHE_GET(value) (((value) & 0x00f00000) >> 20)
4167 #define ALT_SYSMGR_EMAC2_AWCACHE_SET(value) (((value) << 20) & 0x00f00000)
4209 #define ALT_SYSMGR_EMAC2_ARPROT_E_SECURE_NORMAL 0x0
4215 #define ALT_SYSMGR_EMAC2_ARPROT_E_SECURE_PRIVILEGED 0x1
4221 #define ALT_SYSMGR_EMAC2_ARPROT_E_NONSECURE_NORMAL 0x2
4227 #define ALT_SYSMGR_EMAC2_ARPROT_E_NONSECURE_PRIVILEGED 0x3
4230 #define ALT_SYSMGR_EMAC2_ARPROT_LSB 24
4232 #define ALT_SYSMGR_EMAC2_ARPROT_MSB 25
4234 #define ALT_SYSMGR_EMAC2_ARPROT_WIDTH 2
4236 #define ALT_SYSMGR_EMAC2_ARPROT_SET_MSK 0x03000000
4238 #define ALT_SYSMGR_EMAC2_ARPROT_CLR_MSK 0xfcffffff
4240 #define ALT_SYSMGR_EMAC2_ARPROT_RESET 0x2
4242 #define ALT_SYSMGR_EMAC2_ARPROT_GET(value) (((value) & 0x03000000) >> 24)
4244 #define ALT_SYSMGR_EMAC2_ARPROT_SET(value) (((value) << 24) & 0x03000000)
4286 #define ALT_SYSMGR_EMAC2_AWPROT_E_SECURE_NORMAL 0x0
4292 #define ALT_SYSMGR_EMAC2_AWPROT_E_SECURE_PRIVILEGED 0x1
4298 #define ALT_SYSMGR_EMAC2_AWPROT_E_NONSECURE_NORMAL 0x2
4304 #define ALT_SYSMGR_EMAC2_AWPROT_E_NONSECURE_PRIVILEGED 0x3
4307 #define ALT_SYSMGR_EMAC2_AWPROT_LSB 27
4309 #define ALT_SYSMGR_EMAC2_AWPROT_MSB 28
4311 #define ALT_SYSMGR_EMAC2_AWPROT_WIDTH 2
4313 #define ALT_SYSMGR_EMAC2_AWPROT_SET_MSK 0x18000000
4315 #define ALT_SYSMGR_EMAC2_AWPROT_CLR_MSK 0xe7ffffff
4317 #define ALT_SYSMGR_EMAC2_AWPROT_RESET 0x2
4319 #define ALT_SYSMGR_EMAC2_AWPROT_GET(value) (((value) & 0x18000000) >> 27)
4321 #define ALT_SYSMGR_EMAC2_AWPROT_SET(value) (((value) << 27) & 0x18000000)
4344 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN 0x0
4349 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN 0x1
4352 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_LSB 30
4354 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_MSB 30
4356 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_WIDTH 1
4358 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_SET_MSK 0x40000000
4360 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_CLR_MSK 0xbfffffff
4362 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_RESET 0x0
4364 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_GET(value) (((value) & 0x40000000) >> 30)
4366 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_SET(value) (((value) << 30) & 0x40000000)
4377 #define ALT_SYSMGR_EMAC2_AXI_DIS_LSB 31
4379 #define ALT_SYSMGR_EMAC2_AXI_DIS_MSB 31
4381 #define ALT_SYSMGR_EMAC2_AXI_DIS_WIDTH 1
4383 #define ALT_SYSMGR_EMAC2_AXI_DIS_SET_MSK 0x80000000
4385 #define ALT_SYSMGR_EMAC2_AXI_DIS_CLR_MSK 0x7fffffff
4387 #define ALT_SYSMGR_EMAC2_AXI_DIS_RESET 0x0
4389 #define ALT_SYSMGR_EMAC2_AXI_DIS_GET(value) (((value) & 0x80000000) >> 31)
4391 #define ALT_SYSMGR_EMAC2_AXI_DIS_SET(value) (((value) << 31) & 0x80000000)
4393 #ifndef __ASSEMBLY__
4404 struct ALT_SYSMGR_EMAC2_s
4406 uint32_t phy_intf_sel : 2;
4408 uint32_t ptp_ref_sel : 1;
4410 uint32_t app_clk_sel : 1;
4412 uint32_t arcache : 4;
4413 uint32_t awcache : 4;
4414 uint32_t arprot : 2;
4416 uint32_t awprot : 2;
4418 uint32_t sbd_data_endianness : 1;
4419 uint32_t axi_disable : 1;
4423 typedef volatile struct ALT_SYSMGR_EMAC2_s ALT_SYSMGR_EMAC2_t;
4427 #define ALT_SYSMGR_EMAC2_RESET 0x12000003
4429 #define ALT_SYSMGR_EMAC2_OFST 0x4c
4466 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_E_DIS 0x0
4471 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_E_EN 0x1
4474 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_LSB 0
4476 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_MSB 0
4478 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_WIDTH 1
4480 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_SET_MSK 0x00000001
4482 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_CLR_MSK 0xfffffffe
4484 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_RESET 0x1
4486 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_GET(value) (((value) & 0x00000001) >> 0)
4488 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_SET(value) (((value) << 0) & 0x00000001)
4490 #ifndef __ASSEMBLY__
4501 struct ALT_SYSMGR_FPGAINTF_EN_GLOB_s
4508 typedef volatile struct ALT_SYSMGR_FPGAINTF_EN_GLOB_s ALT_SYSMGR_FPGAINTF_EN_GLOB_t;
4512 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_RESET 0x00000001
4514 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_OFST 0x60
4558 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_E_DIS 0x0
4563 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_E_EN 0x1
4566 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_LSB 0
4568 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_MSB 0
4570 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_WIDTH 1
4572 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_SET_MSK 0x00000001
4574 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_CLR_MSK 0xfffffffe
4576 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_RESET 0x1
4578 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_GET(value) (((value) & 0x00000001) >> 0)
4580 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_SET(value) (((value) << 0) & 0x00000001)
4605 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_E_DIS 0x0
4610 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_E_EN 0x1
4613 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_LSB 8
4615 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_MSB 8
4617 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_WIDTH 1
4619 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_SET_MSK 0x00000100
4621 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_CLR_MSK 0xfffffeff
4623 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_RESET 0x1
4625 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_GET(value) (((value) & 0x00000100) >> 8)
4627 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_SET(value) (((value) << 8) & 0x00000100)
4651 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_E_DIS 0x0
4656 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_E_EN 0x1
4659 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_LSB 16
4661 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_MSB 16
4663 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_WIDTH 1
4665 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_SET_MSK 0x00010000
4667 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_CLR_MSK 0xfffeffff
4669 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_RESET 0x1
4671 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_GET(value) (((value) & 0x00010000) >> 16)
4673 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_SET(value) (((value) << 16) & 0x00010000)
4675 #ifndef __ASSEMBLY__
4686 struct ALT_SYSMGR_FPGAINTF_EN_0_s
4688 uint32_t rstreq : 1;
4697 typedef volatile struct ALT_SYSMGR_FPGAINTF_EN_0_s ALT_SYSMGR_FPGAINTF_EN_0_t;
4701 #define ALT_SYSMGR_FPGAINTF_EN_0_RESET 0xffffffff
4703 #define ALT_SYSMGR_FPGAINTF_EN_0_OFST 0x64
4747 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_E_DIS 0x0
4752 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_E_EN 0x1
4755 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_LSB 4
4757 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_MSB 4
4759 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_WIDTH 1
4761 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_SET_MSK 0x00000010
4763 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_CLR_MSK 0xffffffef
4765 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_RESET 0x1
4767 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_GET(value) (((value) & 0x00000010) >> 4)
4769 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_SET(value) (((value) << 4) & 0x00000010)
4791 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_E_DIS 0x0
4796 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_E_EN 0x1
4799 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_LSB 8
4801 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_MSB 8
4803 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_WIDTH 1
4805 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_SET_MSK 0x00000100
4807 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_CLR_MSK 0xfffffeff
4809 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_RESET 0x1
4811 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_GET(value) (((value) & 0x00000100) >> 8)
4813 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_SET(value) (((value) << 8) & 0x00000100)
4835 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_E_DIS 0x0
4840 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_E_EN 0x1
4843 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_LSB 16
4845 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_MSB 16
4847 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_WIDTH 1
4849 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_SET_MSK 0x00010000
4851 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_CLR_MSK 0xfffeffff
4853 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_RESET 0x1
4855 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_GET(value) (((value) & 0x00010000) >> 16)
4857 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_SET(value) (((value) << 16) & 0x00010000)
4880 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_E_DIS 0x0
4885 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_E_EN 0x1
4888 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_LSB 24
4890 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_MSB 24
4892 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_WIDTH 1
4894 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_SET_MSK 0x01000000
4896 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_CLR_MSK 0xfeffffff
4898 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_RESET 0x1
4900 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_GET(value) (((value) & 0x01000000) >> 24)
4902 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_SET(value) (((value) << 24) & 0x01000000)
4904 #ifndef __ASSEMBLY__
4915 struct ALT_SYSMGR_FPGAINTF_EN_1_s
4920 uint32_t dbgapb : 1;
4922 uint32_t stmevent : 1;
4924 uint32_t ctmtrigger : 1;
4929 typedef volatile struct ALT_SYSMGR_FPGAINTF_EN_1_s ALT_SYSMGR_FPGAINTF_EN_1_t;
4933 #define ALT_SYSMGR_FPGAINTF_EN_1_RESET 0xffffffff
4935 #define ALT_SYSMGR_FPGAINTF_EN_1_OFST 0x68
4979 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_E_DIS 0x0
4984 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_E_EN 0x1
4987 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_LSB 4
4989 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_MSB 4
4991 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_WIDTH 1
4993 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_SET_MSK 0x00000010
4995 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_CLR_MSK 0xffffffef
4997 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_RESET 0x0
4999 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_GET(value) (((value) & 0x00000010) >> 4)
5001 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_SET(value) (((value) << 4) & 0x00000010)
5023 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_E_DIS 0x0
5028 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_E_EN 0x1
5031 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_LSB 8
5033 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_MSB 8
5035 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_WIDTH 1
5037 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_SET_MSK 0x00000100
5039 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_CLR_MSK 0xfffffeff
5041 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_RESET 0x0
5043 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_GET(value) (((value) & 0x00000100) >> 8)
5045 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_SET(value) (((value) << 8) & 0x00000100)
5069 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_E_DIS 0x0
5074 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_E_EN 0x1
5077 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_LSB 16
5079 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_MSB 16
5081 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_WIDTH 1
5083 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_SET_MSK 0x00010000
5085 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_CLR_MSK 0xfffeffff
5087 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_RESET 0x0
5089 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_GET(value) (((value) & 0x00010000) >> 16)
5091 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_SET(value) (((value) << 16) & 0x00010000)
5115 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_E_DIS 0x0
5120 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_E_EN 0x1
5123 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_LSB 24
5125 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_MSB 24
5127 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_WIDTH 1
5129 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_SET_MSK 0x01000000
5131 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_CLR_MSK 0xfeffffff
5133 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_RESET 0x0
5135 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_GET(value) (((value) & 0x01000000) >> 24)
5137 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_SET(value) (((value) << 24) & 0x01000000)
5139 #ifndef __ASSEMBLY__
5150 struct ALT_SYSMGR_FPGAINTF_EN_2_s
5157 uint32_t spim_0 : 1;
5159 uint32_t spim_1 : 1;
5164 typedef volatile struct ALT_SYSMGR_FPGAINTF_EN_2_s ALT_SYSMGR_FPGAINTF_EN_2_t;
5168 #define ALT_SYSMGR_FPGAINTF_EN_2_RESET 0x00000000
5170 #define ALT_SYSMGR_FPGAINTF_EN_2_OFST 0x6c
5219 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_E_DIS 0x0
5224 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_E_EN 0x1
5227 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_LSB 0
5229 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_MSB 0
5231 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_WIDTH 1
5233 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SET_MSK 0x00000001
5235 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_CLR_MSK 0xfffffffe
5237 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_RESET 0x0
5239 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_GET(value) (((value) & 0x00000001) >> 0)
5241 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SET(value) (((value) << 0) & 0x00000001)
5262 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_E_DIS 0x0
5267 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_E_EN 0x1
5270 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_LSB 4
5272 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_MSB 4
5274 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_WIDTH 1
5276 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_SET_MSK 0x00000010
5278 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_CLR_MSK 0xffffffef
5280 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_RESET 0x0
5282 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_GET(value) (((value) & 0x00000010) >> 4)
5284 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_SET(value) (((value) << 4) & 0x00000010)
5308 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_E_DIS 0x0
5313 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_E_EN 0x1
5316 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_LSB 8
5318 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_MSB 8
5320 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_WIDTH 1
5322 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SET_MSK 0x00000100
5324 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_CLR_MSK 0xfffffeff
5326 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_RESET 0x0
5328 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_GET(value) (((value) & 0x00000100) >> 8)
5330 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SET(value) (((value) << 8) & 0x00000100)
5351 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_E_DIS 0x0
5356 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_E_EN 0x1
5359 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_LSB 12
5361 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_MSB 12
5363 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_WIDTH 1
5365 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_SET_MSK 0x00001000
5367 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_CLR_MSK 0xffffefff
5369 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_RESET 0x0
5371 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_GET(value) (((value) & 0x00001000) >> 12)
5373 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_SET(value) (((value) << 12) & 0x00001000)
5397 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_E_DIS 0x0
5402 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_E_EN 0x1
5405 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_LSB 16
5407 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_MSB 16
5409 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_WIDTH 1
5411 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SET_MSK 0x00010000
5413 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_CLR_MSK 0xfffeffff
5415 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_RESET 0x0
5417 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_GET(value) (((value) & 0x00010000) >> 16)
5419 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SET(value) (((value) << 16) & 0x00010000)
5440 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_E_DIS 0x0
5445 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_E_EN 0x1
5448 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_LSB 20
5450 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_MSB 20
5452 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_WIDTH 1
5454 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_SET_MSK 0x00100000
5456 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_CLR_MSK 0xffefffff
5458 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_RESET 0x0
5460 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_GET(value) (((value) & 0x00100000) >> 20)
5462 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_SET(value) (((value) << 20) & 0x00100000)
5464 #ifndef __ASSEMBLY__
5475 struct ALT_SYSMGR_FPGAINTF_EN_3_s
5477 uint32_t emac_0 : 1;
5479 uint32_t emac_0_switch : 1;
5481 uint32_t emac_1 : 1;
5483 uint32_t emac_1_switch : 1;
5485 uint32_t emac_2 : 1;
5487 uint32_t emac_2_switch : 1;
5492 typedef volatile struct ALT_SYSMGR_FPGAINTF_EN_3_s ALT_SYSMGR_FPGAINTF_EN_3_t;
5496 #define ALT_SYSMGR_FPGAINTF_EN_3_RESET 0x00000000
5498 #define ALT_SYSMGR_FPGAINTF_EN_3_OFST 0x70
5533 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_LSB 0
5535 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_MSB 0
5537 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_WIDTH 1
5539 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_SET_MSK 0x00000001
5541 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_CLR_MSK 0xfffffffe
5543 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_RESET 0x0
5545 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_GET(value) (((value) & 0x00000001) >> 0)
5547 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_SET(value) (((value) << 0) & 0x00000001)
5567 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_LSB 1
5569 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_MSB 1
5571 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_WIDTH 1
5573 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_SET_MSK 0x00000002
5575 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_CLR_MSK 0xfffffffd
5577 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_RESET 0x0
5579 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_GET(value) (((value) & 0x00000002) >> 1)
5581 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_SET(value) (((value) << 1) & 0x00000002)
5583 #ifndef __ASSEMBLY__
5594 struct ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_s
5596 uint32_t remap0 : 1;
5597 uint32_t remap1 : 1;
5602 typedef volatile struct ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_s ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_t;
5606 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_RESET 0x00000000
5608 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_OFST 0x80
5636 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_LSB 0
5638 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_MSB 0
5640 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_WIDTH 1
5642 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_SET_MSK 0x00000001
5644 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_CLR_MSK 0xfffffffe
5646 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_RESET 0x0
5648 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_GET(value) (((value) & 0x00000001) >> 0)
5650 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_SET(value) (((value) << 0) & 0x00000001)
5659 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_LSB 1
5661 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_MSB 1
5663 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_WIDTH 1
5665 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_SET_MSK 0x00000002
5667 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_CLR_MSK 0xfffffffd
5669 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_RESET 0x0
5671 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_GET(value) (((value) & 0x00000002) >> 1)
5673 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_SET(value) (((value) << 1) & 0x00000002)
5675 #ifndef __ASSEMBLY__
5686 struct ALT_SYSMGR_NOC_ADDR_REMAP_SET_s
5688 uint32_t remap0 : 1;
5689 uint32_t remap1 : 1;
5694 typedef volatile struct ALT_SYSMGR_NOC_ADDR_REMAP_SET_s ALT_SYSMGR_NOC_ADDR_REMAP_SET_t;
5698 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_RESET 0x00000000
5700 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_OFST 0x84
5728 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_LSB 0
5730 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_MSB 0
5732 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_WIDTH 1
5734 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_SET_MSK 0x00000001
5736 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_CLR_MSK 0xfffffffe
5738 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_RESET 0x0
5740 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_GET(value) (((value) & 0x00000001) >> 0)
5742 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_SET(value) (((value) << 0) & 0x00000001)
5751 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_LSB 1
5753 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_MSB 1
5755 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_WIDTH 1
5757 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_SET_MSK 0x00000002
5759 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_CLR_MSK 0xfffffffd
5761 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_RESET 0x0
5763 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_GET(value) (((value) & 0x00000002) >> 1)
5765 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_SET(value) (((value) << 1) & 0x00000002)
5767 #ifndef __ASSEMBLY__
5778 struct ALT_SYSMGR_NOC_ADDR_REMAP_CLR_s
5780 uint32_t remap0 : 1;
5781 uint32_t remap1 : 1;
5786 typedef volatile struct ALT_SYSMGR_NOC_ADDR_REMAP_CLR_s ALT_SYSMGR_NOC_ADDR_REMAP_CLR_t;
5790 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_RESET 0x00000000
5792 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_OFST 0x88
5834 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_LSB 0
5836 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_MSB 0
5838 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_WIDTH 1
5840 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_SET_MSK 0x00000001
5842 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_CLR_MSK 0xfffffffe
5844 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_RESET 0x0
5846 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_GET(value) (((value) & 0x00000001) >> 0)
5848 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_SET(value) (((value) << 0) & 0x00000001)
5857 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_LSB 1
5859 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_MSB 1
5861 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_WIDTH 1
5863 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_SET_MSK 0x00000002
5865 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_CLR_MSK 0xfffffffd
5867 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_RESET 0x0
5869 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
5871 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_SET(value) (((value) << 1) & 0x00000002)
5880 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_LSB 2
5882 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_MSB 2
5884 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_WIDTH 1
5886 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_SET_MSK 0x00000004
5888 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_CLR_MSK 0xfffffffb
5890 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_RESET 0x0
5892 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_GET(value) (((value) & 0x00000004) >> 2)
5894 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_SET(value) (((value) << 2) & 0x00000004)
5903 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_LSB 3
5905 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_MSB 3
5907 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_WIDTH 1
5909 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_SET_MSK 0x00000008
5911 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_CLR_MSK 0xfffffff7
5913 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_RESET 0x0
5915 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_GET(value) (((value) & 0x00000008) >> 3)
5917 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_SET(value) (((value) << 3) & 0x00000008)
5926 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_LSB 4
5928 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_MSB 4
5930 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_WIDTH 1
5932 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_SET_MSK 0x00000010
5934 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_CLR_MSK 0xffffffef
5936 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_RESET 0x0
5938 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
5940 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
5949 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_LSB 5
5951 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_MSB 5
5953 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_WIDTH 1
5955 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_SET_MSK 0x00000020
5957 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_CLR_MSK 0xffffffdf
5959 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_RESET 0x0
5961 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
5963 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
5972 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_LSB 6
5974 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_MSB 6
5976 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_WIDTH 1
5978 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_SET_MSK 0x00000040
5980 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_CLR_MSK 0xffffffbf
5982 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_RESET 0x0
5984 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
5986 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
5995 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_LSB 7
5997 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_MSB 7
5999 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_WIDTH 1
6001 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_SET_MSK 0x00000080
6003 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_CLR_MSK 0xffffff7f
6005 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_RESET 0x0
6007 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
6009 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
6018 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_LSB 8
6020 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_MSB 8
6022 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_WIDTH 1
6024 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_SET_MSK 0x00000100
6026 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_CLR_MSK 0xfffffeff
6028 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_RESET 0x0
6030 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
6032 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
6041 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_LSB 9
6043 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_MSB 9
6045 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_WIDTH 1
6047 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_SET_MSK 0x00000200
6049 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_CLR_MSK 0xfffffdff
6051 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_RESET 0x0
6053 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
6055 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
6064 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_LSB 10
6066 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_MSB 10
6068 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_WIDTH 1
6070 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_SET_MSK 0x00000400
6072 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_CLR_MSK 0xfffffbff
6074 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_RESET 0x0
6076 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_GET(value) (((value) & 0x00000400) >> 10)
6078 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_SET(value) (((value) << 10) & 0x00000400)
6087 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_LSB 11
6089 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_MSB 11
6091 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_WIDTH 1
6093 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_SET_MSK 0x00000800
6095 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_CLR_MSK 0xfffff7ff
6097 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_RESET 0x0
6099 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
6101 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
6110 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_LSB 12
6112 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_MSB 12
6114 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_WIDTH 1
6116 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_SET_MSK 0x00001000
6118 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_CLR_MSK 0xffffefff
6120 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_RESET 0x0
6122 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
6124 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
6133 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_LSB 13
6135 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_MSB 13
6137 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_WIDTH 1
6139 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_SET_MSK 0x00002000
6141 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_CLR_MSK 0xffffdfff
6143 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_RESET 0x0
6145 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
6147 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
6156 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_LSB 14
6158 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_MSB 14
6160 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_WIDTH 1
6162 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_SET_MSK 0x00004000
6164 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_CLR_MSK 0xffffbfff
6166 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_RESET 0x0
6168 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_GET(value) (((value) & 0x00004000) >> 14)
6170 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_SET(value) (((value) << 14) & 0x00004000)
6179 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_LSB 15
6181 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_MSB 15
6183 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_WIDTH 1
6185 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_SET_MSK 0x00008000
6187 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_CLR_MSK 0xffff7fff
6189 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_RESET 0x0
6191 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_GET(value) (((value) & 0x00008000) >> 15)
6193 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_SET(value) (((value) << 15) & 0x00008000)
6202 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_LSB 16
6204 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_MSB 16
6206 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_WIDTH 1
6208 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_SET_MSK 0x00010000
6210 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_CLR_MSK 0xfffeffff
6212 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_RESET 0x0
6214 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_GET(value) (((value) & 0x00010000) >> 16)
6216 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_SET(value) (((value) << 16) & 0x00010000)
6225 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_LSB 17
6227 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_MSB 17
6229 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_WIDTH 1
6231 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_SET_MSK 0x00020000
6233 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_CLR_MSK 0xfffdffff
6235 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_RESET 0x0
6237 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_GET(value) (((value) & 0x00020000) >> 17)
6239 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_SET(value) (((value) << 17) & 0x00020000)
6248 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_LSB 18
6250 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_MSB 18
6252 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_WIDTH 1
6254 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_SET_MSK 0x00040000
6256 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_CLR_MSK 0xfffbffff
6258 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_RESET 0x0
6260 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_GET(value) (((value) & 0x00040000) >> 18)
6262 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_SET(value) (((value) << 18) & 0x00040000)
6264 #ifndef __ASSEMBLY__
6275 struct ALT_SYSMGR_ECC_INTMSK_VALUE_s
6281 uint32_t emac0_rx : 1;
6282 uint32_t emac0_tx : 1;
6283 uint32_t emac1_rx : 1;
6284 uint32_t emac1_tx : 1;
6285 uint32_t emac2_rx : 1;
6286 uint32_t emac2_tx : 1;
6288 uint32_t nand_buf : 1;
6289 uint32_t nand_wr : 1;
6290 uint32_t nand_rd : 1;
6292 uint32_t sdmmca : 1;
6293 uint32_t sdmmcb : 1;
6300 typedef volatile struct ALT_SYSMGR_ECC_INTMSK_VALUE_s ALT_SYSMGR_ECC_INTMSK_VALUE_t;
6304 #define ALT_SYSMGR_ECC_INTMSK_VALUE_RESET 0x00000000
6306 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OFST 0x90
6348 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_LSB 0
6350 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_MSB 0
6352 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_WIDTH 1
6354 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_SET_MSK 0x00000001
6356 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_CLR_MSK 0xfffffffe
6358 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_RESET 0x0
6360 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_GET(value) (((value) & 0x00000001) >> 0)
6362 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_SET(value) (((value) << 0) & 0x00000001)
6371 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_LSB 1
6373 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_MSB 1
6375 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_WIDTH 1
6377 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_SET_MSK 0x00000002
6379 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_CLR_MSK 0xfffffffd
6381 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_RESET 0x0
6383 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
6385 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_SET(value) (((value) << 1) & 0x00000002)
6394 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_LSB 2
6396 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_MSB 2
6398 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_WIDTH 1
6400 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_SET_MSK 0x00000004
6402 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_CLR_MSK 0xfffffffb
6404 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_RESET 0x0
6406 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_GET(value) (((value) & 0x00000004) >> 2)
6408 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_SET(value) (((value) << 2) & 0x00000004)
6417 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_LSB 3
6419 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_MSB 3
6421 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_WIDTH 1
6423 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_SET_MSK 0x00000008
6425 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_CLR_MSK 0xfffffff7
6427 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_RESET 0x0
6429 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_GET(value) (((value) & 0x00000008) >> 3)
6431 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_SET(value) (((value) << 3) & 0x00000008)
6440 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_LSB 4
6442 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_MSB 4
6444 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_WIDTH 1
6446 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_SET_MSK 0x00000010
6448 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_CLR_MSK 0xffffffef
6450 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_RESET 0x0
6452 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
6454 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
6463 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_LSB 5
6465 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_MSB 5
6467 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_WIDTH 1
6469 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_SET_MSK 0x00000020
6471 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_CLR_MSK 0xffffffdf
6473 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_RESET 0x0
6475 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
6477 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
6486 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_LSB 6
6488 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_MSB 6
6490 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_WIDTH 1
6492 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_SET_MSK 0x00000040
6494 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_CLR_MSK 0xffffffbf
6496 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_RESET 0x0
6498 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
6500 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
6509 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_LSB 7
6511 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_MSB 7
6513 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_WIDTH 1
6515 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_SET_MSK 0x00000080
6517 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_CLR_MSK 0xffffff7f
6519 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_RESET 0x0
6521 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
6523 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
6532 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_LSB 8
6534 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_MSB 8
6536 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_WIDTH 1
6538 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_SET_MSK 0x00000100
6540 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_CLR_MSK 0xfffffeff
6542 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_RESET 0x0
6544 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
6546 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
6555 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_LSB 9
6557 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_MSB 9
6559 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_WIDTH 1
6561 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_SET_MSK 0x00000200
6563 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_CLR_MSK 0xfffffdff
6565 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_RESET 0x0
6567 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
6569 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
6578 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_LSB 10
6580 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_MSB 10
6582 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_WIDTH 1
6584 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_SET_MSK 0x00000400
6586 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_CLR_MSK 0xfffffbff
6588 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_RESET 0x0
6590 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_GET(value) (((value) & 0x00000400) >> 10)
6592 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_SET(value) (((value) << 10) & 0x00000400)
6601 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_LSB 11
6603 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_MSB 11
6605 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_WIDTH 1
6607 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_SET_MSK 0x00000800
6609 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_CLR_MSK 0xfffff7ff
6611 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_RESET 0x0
6613 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
6615 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
6624 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_LSB 12
6626 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_MSB 12
6628 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_WIDTH 1
6630 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_SET_MSK 0x00001000
6632 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_CLR_MSK 0xffffefff
6634 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_RESET 0x0
6636 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
6638 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
6647 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_LSB 13
6649 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_MSB 13
6651 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_WIDTH 1
6653 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_SET_MSK 0x00002000
6655 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_CLR_MSK 0xffffdfff
6657 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_RESET 0x0
6659 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
6661 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
6670 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_LSB 14
6672 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_MSB 14
6674 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_WIDTH 1
6676 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_SET_MSK 0x00004000
6678 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_CLR_MSK 0xffffbfff
6680 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_RESET 0x0
6682 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_GET(value) (((value) & 0x00004000) >> 14)
6684 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_SET(value) (((value) << 14) & 0x00004000)
6693 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_LSB 15
6695 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_MSB 15
6697 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_WIDTH 1
6699 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_SET_MSK 0x00008000
6701 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_CLR_MSK 0xffff7fff
6703 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_RESET 0x0
6705 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_GET(value) (((value) & 0x00008000) >> 15)
6707 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_SET(value) (((value) << 15) & 0x00008000)
6716 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_LSB 16
6718 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_MSB 16
6720 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_WIDTH 1
6722 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_SET_MSK 0x00010000
6724 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_CLR_MSK 0xfffeffff
6726 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_RESET 0x0
6728 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_GET(value) (((value) & 0x00010000) >> 16)
6730 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_SET(value) (((value) << 16) & 0x00010000)
6739 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_LSB 17
6741 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_MSB 17
6743 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_WIDTH 1
6745 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_SET_MSK 0x00020000
6747 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_CLR_MSK 0xfffdffff
6749 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_RESET 0x0
6751 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_GET(value) (((value) & 0x00020000) >> 17)
6753 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_SET(value) (((value) << 17) & 0x00020000)
6762 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_LSB 18
6764 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_MSB 18
6766 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_WIDTH 1
6768 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_SET_MSK 0x00040000
6770 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_CLR_MSK 0xfffbffff
6772 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_RESET 0x0
6774 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_GET(value) (((value) & 0x00040000) >> 18)
6776 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_SET(value) (((value) << 18) & 0x00040000)
6778 #ifndef __ASSEMBLY__
6789 struct ALT_SYSMGR_ECC_INTMSK_SET_s
6795 uint32_t emac0_rx : 1;
6796 uint32_t emac0_tx : 1;
6797 uint32_t emac1_rx : 1;
6798 uint32_t emac1_tx : 1;
6799 uint32_t emac2_rx : 1;
6800 uint32_t emac2_tx : 1;
6802 uint32_t nand_buf : 1;
6803 uint32_t nand_wr : 1;
6804 uint32_t nand_rd : 1;
6806 uint32_t sdmmca : 1;
6807 uint32_t sdmmcb : 1;
6814 typedef volatile struct ALT_SYSMGR_ECC_INTMSK_SET_s ALT_SYSMGR_ECC_INTMSK_SET_t;
6818 #define ALT_SYSMGR_ECC_INTMSK_SET_RESET 0x00000000
6820 #define ALT_SYSMGR_ECC_INTMSK_SET_OFST 0x94
6862 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_LSB 0
6864 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_MSB 0
6866 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_WIDTH 1
6868 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_SET_MSK 0x00000001
6870 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_CLR_MSK 0xfffffffe
6872 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_RESET 0x0
6874 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_GET(value) (((value) & 0x00000001) >> 0)
6876 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_SET(value) (((value) << 0) & 0x00000001)
6885 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_LSB 1
6887 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_MSB 1
6889 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_WIDTH 1
6891 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_SET_MSK 0x00000002
6893 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_CLR_MSK 0xfffffffd
6895 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_RESET 0x0
6897 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
6899 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_SET(value) (((value) << 1) & 0x00000002)
6908 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_LSB 2
6910 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_MSB 2
6912 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_WIDTH 1
6914 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_SET_MSK 0x00000004
6916 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_CLR_MSK 0xfffffffb
6918 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_RESET 0x0
6920 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_GET(value) (((value) & 0x00000004) >> 2)
6922 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_SET(value) (((value) << 2) & 0x00000004)
6931 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_LSB 3
6933 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_MSB 3
6935 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_WIDTH 1
6937 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_SET_MSK 0x00000008
6939 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_CLR_MSK 0xfffffff7
6941 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_RESET 0x0
6943 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_GET(value) (((value) & 0x00000008) >> 3)
6945 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_SET(value) (((value) << 3) & 0x00000008)
6954 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_LSB 4
6956 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_MSB 4
6958 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_WIDTH 1
6960 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_SET_MSK 0x00000010
6962 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_CLR_MSK 0xffffffef
6964 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_RESET 0x0
6966 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
6968 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
6977 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_LSB 5
6979 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_MSB 5
6981 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_WIDTH 1
6983 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_SET_MSK 0x00000020
6985 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_CLR_MSK 0xffffffdf
6987 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_RESET 0x0
6989 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
6991 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
7000 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_LSB 6
7002 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_MSB 6
7004 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_WIDTH 1
7006 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_SET_MSK 0x00000040
7008 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_CLR_MSK 0xffffffbf
7010 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_RESET 0x0
7012 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
7014 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
7023 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_LSB 7
7025 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_MSB 7
7027 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_WIDTH 1
7029 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_SET_MSK 0x00000080
7031 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_CLR_MSK 0xffffff7f
7033 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_RESET 0x0
7035 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
7037 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
7046 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_LSB 8
7048 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_MSB 8
7050 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_WIDTH 1
7052 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_SET_MSK 0x00000100
7054 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_CLR_MSK 0xfffffeff
7056 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_RESET 0x0
7058 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
7060 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
7069 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_LSB 9
7071 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_MSB 9
7073 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_WIDTH 1
7075 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_SET_MSK 0x00000200
7077 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_CLR_MSK 0xfffffdff
7079 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_RESET 0x0
7081 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
7083 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
7092 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_LSB 10
7094 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_MSB 10
7096 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_WIDTH 1
7098 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_SET_MSK 0x00000400
7100 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_CLR_MSK 0xfffffbff
7102 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_RESET 0x0
7104 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_GET(value) (((value) & 0x00000400) >> 10)
7106 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_SET(value) (((value) << 10) & 0x00000400)
7115 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_LSB 11
7117 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_MSB 11
7119 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_WIDTH 1
7121 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_SET_MSK 0x00000800
7123 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_CLR_MSK 0xfffff7ff
7125 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_RESET 0x0
7127 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
7129 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
7138 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_LSB 12
7140 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_MSB 12
7142 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_WIDTH 1
7144 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_SET_MSK 0x00001000
7146 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_CLR_MSK 0xffffefff
7148 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_RESET 0x0
7150 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
7152 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
7161 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_LSB 13
7163 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_MSB 13
7165 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_WIDTH 1
7167 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_SET_MSK 0x00002000
7169 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_CLR_MSK 0xffffdfff
7171 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_RESET 0x0
7173 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
7175 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
7184 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_LSB 14
7186 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_MSB 14
7188 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_WIDTH 1
7190 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_SET_MSK 0x00004000
7192 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_CLR_MSK 0xffffbfff
7194 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_RESET 0x0
7196 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_GET(value) (((value) & 0x00004000) >> 14)
7198 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_SET(value) (((value) << 14) & 0x00004000)
7207 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_LSB 15
7209 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_MSB 15
7211 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_WIDTH 1
7213 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_SET_MSK 0x00008000
7215 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_CLR_MSK 0xffff7fff
7217 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_RESET 0x0
7219 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_GET(value) (((value) & 0x00008000) >> 15)
7221 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_SET(value) (((value) << 15) & 0x00008000)
7230 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_LSB 16
7232 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_MSB 16
7234 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_WIDTH 1
7236 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_SET_MSK 0x00010000
7238 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_CLR_MSK 0xfffeffff
7240 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_RESET 0x0
7242 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_GET(value) (((value) & 0x00010000) >> 16)
7244 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_SET(value) (((value) << 16) & 0x00010000)
7253 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_LSB 17
7255 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_MSB 17
7257 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_WIDTH 1
7259 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_SET_MSK 0x00020000
7261 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_CLR_MSK 0xfffdffff
7263 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_RESET 0x0
7265 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_GET(value) (((value) & 0x00020000) >> 17)
7267 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_SET(value) (((value) << 17) & 0x00020000)
7276 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_LSB 18
7278 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_MSB 18
7280 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_WIDTH 1
7282 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_SET_MSK 0x00040000
7284 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_CLR_MSK 0xfffbffff
7286 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_RESET 0x0
7288 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_GET(value) (((value) & 0x00040000) >> 18)
7290 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_SET(value) (((value) << 18) & 0x00040000)
7292 #ifndef __ASSEMBLY__
7303 struct ALT_SYSMGR_ECC_INTMSK_CLR_s
7309 uint32_t emac0_rx : 1;
7310 uint32_t emac0_tx : 1;
7311 uint32_t emac1_rx : 1;
7312 uint32_t emac1_tx : 1;
7313 uint32_t emac2_rx : 1;
7314 uint32_t emac2_tx : 1;
7316 uint32_t nand_buf : 1;
7317 uint32_t nand_wr : 1;
7318 uint32_t nand_rd : 1;
7320 uint32_t sdmmca : 1;
7321 uint32_t sdmmcb : 1;
7328 typedef volatile struct ALT_SYSMGR_ECC_INTMSK_CLR_s ALT_SYSMGR_ECC_INTMSK_CLR_t;
7332 #define ALT_SYSMGR_ECC_INTMSK_CLR_RESET 0x00000000
7334 #define ALT_SYSMGR_ECC_INTMSK_CLR_OFST 0x98
7376 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_LSB 0
7378 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_MSB 0
7380 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_WIDTH 1
7382 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_SET_MSK 0x00000001
7384 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_CLR_MSK 0xfffffffe
7386 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_RESET 0x0
7388 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_GET(value) (((value) & 0x00000001) >> 0)
7390 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_SET(value) (((value) << 0) & 0x00000001)
7399 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_LSB 1
7401 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_MSB 1
7403 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_WIDTH 1
7405 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK 0x00000002
7407 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_CLR_MSK 0xfffffffd
7409 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_RESET 0x0
7411 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
7413 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET(value) (((value) << 1) & 0x00000002)
7422 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_LSB 2
7424 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_MSB 2
7426 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_WIDTH 1
7428 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_SET_MSK 0x00000004
7430 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_CLR_MSK 0xfffffffb
7432 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_RESET 0x0
7434 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_GET(value) (((value) & 0x00000004) >> 2)
7436 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_SET(value) (((value) << 2) & 0x00000004)
7445 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_LSB 3
7447 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_MSB 3
7449 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_WIDTH 1
7451 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_SET_MSK 0x00000008
7453 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_CLR_MSK 0xfffffff7
7455 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_RESET 0x0
7457 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_GET(value) (((value) & 0x00000008) >> 3)
7459 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_SET(value) (((value) << 3) & 0x00000008)
7468 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_LSB 4
7470 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_MSB 4
7472 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_WIDTH 1
7474 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_SET_MSK 0x00000010
7476 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_CLR_MSK 0xffffffef
7478 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_RESET 0x0
7480 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
7482 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
7491 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_LSB 5
7493 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_MSB 5
7495 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_WIDTH 1
7497 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_SET_MSK 0x00000020
7499 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_CLR_MSK 0xffffffdf
7501 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_RESET 0x0
7503 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
7505 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
7514 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_LSB 6
7516 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_MSB 6
7518 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_WIDTH 1
7520 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_SET_MSK 0x00000040
7522 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_CLR_MSK 0xffffffbf
7524 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_RESET 0x0
7526 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
7528 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
7537 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_LSB 7
7539 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_MSB 7
7541 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_WIDTH 1
7543 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_SET_MSK 0x00000080
7545 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_CLR_MSK 0xffffff7f
7547 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_RESET 0x0
7549 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
7551 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
7560 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_LSB 8
7562 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_MSB 8
7564 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_WIDTH 1
7566 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_SET_MSK 0x00000100
7568 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_CLR_MSK 0xfffffeff
7570 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_RESET 0x0
7572 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
7574 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
7583 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_LSB 9
7585 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_MSB 9
7587 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_WIDTH 1
7589 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_SET_MSK 0x00000200
7591 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_CLR_MSK 0xfffffdff
7593 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_RESET 0x0
7595 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
7597 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
7606 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_LSB 10
7608 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_MSB 10
7610 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_WIDTH 1
7612 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_SET_MSK 0x00000400
7614 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_CLR_MSK 0xfffffbff
7616 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_RESET 0x0
7618 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_GET(value) (((value) & 0x00000400) >> 10)
7620 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_SET(value) (((value) << 10) & 0x00000400)
7629 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_LSB 11
7631 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_MSB 11
7633 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_WIDTH 1
7635 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_SET_MSK 0x00000800
7637 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_CLR_MSK 0xfffff7ff
7639 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_RESET 0x0
7641 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
7643 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
7652 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_LSB 12
7654 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_MSB 12
7656 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_WIDTH 1
7658 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_SET_MSK 0x00001000
7660 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_CLR_MSK 0xffffefff
7662 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_RESET 0x0
7664 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
7666 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
7675 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_LSB 13
7677 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_MSB 13
7679 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_WIDTH 1
7681 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_SET_MSK 0x00002000
7683 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_CLR_MSK 0xffffdfff
7685 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_RESET 0x0
7687 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
7689 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
7698 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_LSB 14
7700 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_MSB 14
7702 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_WIDTH 1
7704 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_SET_MSK 0x00004000
7706 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_CLR_MSK 0xffffbfff
7708 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_RESET 0x0
7710 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_GET(value) (((value) & 0x00004000) >> 14)
7712 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_SET(value) (((value) << 14) & 0x00004000)
7721 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_LSB 15
7723 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_MSB 15
7725 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_WIDTH 1
7727 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_SET_MSK 0x00008000
7729 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_CLR_MSK 0xffff7fff
7731 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_RESET 0x0
7733 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_GET(value) (((value) & 0x00008000) >> 15)
7735 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_SET(value) (((value) << 15) & 0x00008000)
7744 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_LSB 16
7746 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_MSB 16
7748 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_WIDTH 1
7750 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_SET_MSK 0x00010000
7752 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_CLR_MSK 0xfffeffff
7754 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_RESET 0x0
7756 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_GET(value) (((value) & 0x00010000) >> 16)
7758 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_SET(value) (((value) << 16) & 0x00010000)
7767 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_LSB 17
7769 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_MSB 17
7771 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_WIDTH 1
7773 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_SET_MSK 0x00020000
7775 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_CLR_MSK 0xfffdffff
7777 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_RESET 0x0
7779 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_GET(value) (((value) & 0x00020000) >> 17)
7781 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_SET(value) (((value) << 17) & 0x00020000)
7790 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_LSB 18
7792 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_MSB 18
7794 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_WIDTH 1
7796 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_SET_MSK 0x00040000
7798 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_CLR_MSK 0xfffbffff
7800 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_RESET 0x0
7802 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_GET(value) (((value) & 0x00040000) >> 18)
7804 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_SET(value) (((value) << 18) & 0x00040000)
7806 #ifndef __ASSEMBLY__
7817 struct ALT_SYSMGR_ECC_INTSTAT_SERR_s
7823 uint32_t emac0_rx : 1;
7824 uint32_t emac0_tx : 1;
7825 uint32_t emac1_rx : 1;
7826 uint32_t emac1_tx : 1;
7827 uint32_t emac2_rx : 1;
7828 uint32_t emac2_tx : 1;
7830 uint32_t nand_buf : 1;
7831 uint32_t nand_wr : 1;
7832 uint32_t nand_rd : 1;
7834 uint32_t sdmmca : 1;
7835 uint32_t sdmmcb : 1;
7842 typedef volatile struct ALT_SYSMGR_ECC_INTSTAT_SERR_s ALT_SYSMGR_ECC_INTSTAT_SERR_t;
7846 #define ALT_SYSMGR_ECC_INTSTAT_SERR_RESET 0x00000000
7848 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OFST 0x9c
7890 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_LSB 0
7892 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_MSB 0
7894 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_WIDTH 1
7896 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_SET_MSK 0x00000001
7898 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_CLR_MSK 0xfffffffe
7900 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_RESET 0x0
7902 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_GET(value) (((value) & 0x00000001) >> 0)
7904 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_SET(value) (((value) << 0) & 0x00000001)
7913 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_LSB 1
7915 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_MSB 1
7917 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_WIDTH 1
7919 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK 0x00000002
7921 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_CLR_MSK 0xfffffffd
7923 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_RESET 0x0
7925 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
7927 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET(value) (((value) << 1) & 0x00000002)
7936 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_LSB 2
7938 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_MSB 2
7940 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_WIDTH 1
7942 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_SET_MSK 0x00000004
7944 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_CLR_MSK 0xfffffffb
7946 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_RESET 0x0
7948 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_GET(value) (((value) & 0x00000004) >> 2)
7950 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_SET(value) (((value) << 2) & 0x00000004)
7959 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_LSB 3
7961 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_MSB 3
7963 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_WIDTH 1
7965 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_SET_MSK 0x00000008
7967 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_CLR_MSK 0xfffffff7
7969 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_RESET 0x0
7971 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_GET(value) (((value) & 0x00000008) >> 3)
7973 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_SET(value) (((value) << 3) & 0x00000008)
7982 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_LSB 4
7984 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_MSB 4
7986 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_WIDTH 1
7988 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_SET_MSK 0x00000010
7990 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_CLR_MSK 0xffffffef
7992 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_RESET 0x0
7994 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
7996 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
8005 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_LSB 5
8007 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_MSB 5
8009 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_WIDTH 1
8011 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_SET_MSK 0x00000020
8013 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_CLR_MSK 0xffffffdf
8015 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_RESET 0x0
8017 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
8019 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
8028 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_LSB 6
8030 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_MSB 6
8032 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_WIDTH 1
8034 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_SET_MSK 0x00000040
8036 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_CLR_MSK 0xffffffbf
8038 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_RESET 0x0
8040 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
8042 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
8051 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_LSB 7
8053 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_MSB 7
8055 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_WIDTH 1
8057 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_SET_MSK 0x00000080
8059 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_CLR_MSK 0xffffff7f
8061 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_RESET 0x0
8063 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
8065 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
8074 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_LSB 8
8076 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_MSB 8
8078 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_WIDTH 1
8080 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_SET_MSK 0x00000100
8082 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_CLR_MSK 0xfffffeff
8084 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_RESET 0x0
8086 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
8088 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
8097 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_LSB 9
8099 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_MSB 9
8101 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_WIDTH 1
8103 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_SET_MSK 0x00000200
8105 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_CLR_MSK 0xfffffdff
8107 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_RESET 0x0
8109 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
8111 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
8120 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_LSB 10
8122 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_MSB 10
8124 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_WIDTH 1
8126 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_SET_MSK 0x00000400
8128 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_CLR_MSK 0xfffffbff
8130 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_RESET 0x0
8132 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_GET(value) (((value) & 0x00000400) >> 10)
8134 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_SET(value) (((value) << 10) & 0x00000400)
8143 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_LSB 11
8145 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_MSB 11
8147 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_WIDTH 1
8149 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_SET_MSK 0x00000800
8151 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_CLR_MSK 0xfffff7ff
8153 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_RESET 0x0
8155 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
8157 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
8166 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_LSB 12
8168 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_MSB 12
8170 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_WIDTH 1
8172 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_SET_MSK 0x00001000
8174 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_CLR_MSK 0xffffefff
8176 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_RESET 0x0
8178 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
8180 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
8189 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_LSB 13
8191 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_MSB 13
8193 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_WIDTH 1
8195 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_SET_MSK 0x00002000
8197 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_CLR_MSK 0xffffdfff
8199 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_RESET 0x0
8201 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
8203 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
8212 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_LSB 14
8214 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_MSB 14
8216 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_WIDTH 1
8218 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_SET_MSK 0x00004000
8220 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_CLR_MSK 0xffffbfff
8222 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_RESET 0x0
8224 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_GET(value) (((value) & 0x00004000) >> 14)
8226 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_SET(value) (((value) << 14) & 0x00004000)
8235 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_LSB 15
8237 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_MSB 15
8239 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_WIDTH 1
8241 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_SET_MSK 0x00008000
8243 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_CLR_MSK 0xffff7fff
8245 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_RESET 0x0
8247 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_GET(value) (((value) & 0x00008000) >> 15)
8249 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_SET(value) (((value) << 15) & 0x00008000)
8258 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_LSB 16
8260 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_MSB 16
8262 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_WIDTH 1
8264 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_SET_MSK 0x00010000
8266 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_CLR_MSK 0xfffeffff
8268 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_RESET 0x0
8270 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_GET(value) (((value) & 0x00010000) >> 16)
8272 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_SET(value) (((value) << 16) & 0x00010000)
8281 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_LSB 17
8283 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_MSB 17
8285 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_WIDTH 1
8287 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_SET_MSK 0x00020000
8289 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_CLR_MSK 0xfffdffff
8291 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_RESET 0x0
8293 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_GET(value) (((value) & 0x00020000) >> 17)
8295 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_SET(value) (((value) << 17) & 0x00020000)
8304 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_LSB 18
8306 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_MSB 18
8308 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_WIDTH 1
8310 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_SET_MSK 0x00040000
8312 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_CLR_MSK 0xfffbffff
8314 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_RESET 0x0
8316 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_GET(value) (((value) & 0x00040000) >> 18)
8318 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_SET(value) (((value) << 18) & 0x00040000)
8320 #ifndef __ASSEMBLY__
8331 struct ALT_SYSMGR_ECC_INTSTAT_DERR_s
8337 uint32_t emac0_rx : 1;
8338 uint32_t emac0_tx : 1;
8339 uint32_t emac1_rx : 1;
8340 uint32_t emac1_tx : 1;
8341 uint32_t emac2_rx : 1;
8342 uint32_t emac2_tx : 1;
8344 uint32_t nand_buf : 1;
8345 uint32_t nand_wr : 1;
8346 uint32_t nand_rd : 1;
8348 uint32_t sdmmca : 1;
8349 uint32_t sdmmcb : 1;
8356 typedef volatile struct ALT_SYSMGR_ECC_INTSTAT_DERR_s ALT_SYSMGR_ECC_INTSTAT_DERR_t;
8360 #define ALT_SYSMGR_ECC_INTSTAT_DERR_RESET 0x00000000
8362 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OFST 0xa0
8395 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_LSB 0
8397 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_MSB 11
8399 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_WIDTH 12
8401 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_SET_MSK 0x00000fff
8403 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_CLR_MSK 0xfffff000
8405 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_RESET 0x0
8407 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_GET(value) (((value) & 0x00000fff) >> 0)
8409 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_SET(value) (((value) << 0) & 0x00000fff)
8420 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_LSB 15
8422 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_MSB 15
8424 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_WIDTH 1
8426 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_SET_MSK 0x00008000
8428 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_CLR_MSK 0xffff7fff
8430 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_RESET 0x0
8432 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_GET(value) (((value) & 0x00008000) >> 15)
8434 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_SET(value) (((value) << 15) & 0x00008000)
8447 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_LSB 16
8449 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_MSB 27
8451 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_WIDTH 12
8453 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_SET_MSK 0x0fff0000
8455 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_CLR_MSK 0xf000ffff
8457 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_RESET 0x0
8459 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_GET(value) (((value) & 0x0fff0000) >> 16)
8461 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_SET(value) (((value) << 16) & 0x0fff0000)
8472 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_LSB 31
8474 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_MSB 31
8476 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_WIDTH 1
8478 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_SET_MSK 0x80000000
8480 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_CLR_MSK 0x7fffffff
8482 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_RESET 0x0
8484 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_GET(value) (((value) & 0x80000000) >> 31)
8486 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_SET(value) (((value) << 31) & 0x80000000)
8488 #ifndef __ASSEMBLY__
8499 struct ALT_SYSMGR_MPU_STAT_L2_ECC_s
8501 uint32_t serr_info : 12;
8503 uint32_t serr_pending : 1;
8504 uint32_t merr_info : 12;
8506 uint32_t merr_pending : 1;
8510 typedef volatile struct ALT_SYSMGR_MPU_STAT_L2_ECC_s ALT_SYSMGR_MPU_STAT_L2_ECC_t;
8514 #define ALT_SYSMGR_MPU_STAT_L2_ECC_RESET 0x00000000
8516 #define ALT_SYSMGR_MPU_STAT_L2_ECC_OFST 0xa4
8546 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_LSB 15
8548 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_MSB 15
8550 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_WIDTH 1
8552 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_SET_MSK 0x00008000
8554 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_CLR_MSK 0xffff7fff
8556 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_RESET 0x0
8558 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_GET(value) (((value) & 0x00008000) >> 15)
8560 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_SET(value) (((value) << 15) & 0x00008000)
8572 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_LSB 31
8574 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_MSB 31
8576 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_WIDTH 1
8578 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_SET_MSK 0x80000000
8580 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_CLR_MSK 0x7fffffff
8582 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_RESET 0x0
8584 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_GET(value) (((value) & 0x80000000) >> 31)
8586 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_SET(value) (((value) << 31) & 0x80000000)
8588 #ifndef __ASSEMBLY__
8599 struct ALT_SYSMGR_MPU_CLR_L2_ECC_s
8608 typedef volatile struct ALT_SYSMGR_MPU_CLR_L2_ECC_s ALT_SYSMGR_MPU_CLR_L2_ECC_t;
8612 #define ALT_SYSMGR_MPU_CLR_L2_ECC_RESET 0x00000000
8614 #define ALT_SYSMGR_MPU_CLR_L2_ECC_OFST 0xa8
8678 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_LSB 0
8680 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_MSB 7
8682 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_WIDTH 8
8684 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_SET_MSK 0x000000ff
8686 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_CLR_MSK 0xffffff00
8688 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_RESET 0x0
8690 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_GET(value) (((value) & 0x000000ff) >> 0)
8692 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_SET(value) (((value) << 0) & 0x000000ff)
8703 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_LSB 8
8705 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_MSB 15
8707 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_WIDTH 8
8709 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_SET_MSK 0x0000ff00
8711 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_CLR_MSK 0xffff00ff
8713 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_RESET 0x0
8715 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_GET(value) (((value) & 0x0000ff00) >> 8)
8717 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_SET(value) (((value) << 8) & 0x0000ff00)
8728 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_LSB 16
8730 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_MSB 17
8732 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_WIDTH 2
8734 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_SET_MSK 0x00030000
8736 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_CLR_MSK 0xfffcffff
8738 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_RESET 0x0
8740 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_GET(value) (((value) & 0x00030000) >> 16)
8742 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_SET(value) (((value) << 16) & 0x00030000)
8744 #ifndef __ASSEMBLY__
8755 struct ALT_SYSMGR_MPU_STAT_L1_PARITY_s
8764 typedef volatile struct ALT_SYSMGR_MPU_STAT_L1_PARITY_s ALT_SYSMGR_MPU_STAT_L1_PARITY_t;
8768 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_RESET 0x00000000
8770 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_OFST 0xac
8837 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_LSB 0
8839 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_MSB 7
8841 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_WIDTH 8
8843 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_SET_MSK 0x000000ff
8845 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_CLR_MSK 0xffffff00
8847 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_RESET 0x0
8849 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_GET(value) (((value) & 0x000000ff) >> 0)
8851 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_SET(value) (((value) << 0) & 0x000000ff)
8862 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_LSB 8
8864 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_MSB 15
8866 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_WIDTH 8
8868 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_SET_MSK 0x0000ff00
8870 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_CLR_MSK 0xffff00ff
8872 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_RESET 0x0
8874 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_GET(value) (((value) & 0x0000ff00) >> 8)
8876 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_SET(value) (((value) << 8) & 0x0000ff00)
8887 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_LSB 16
8889 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_MSB 17
8891 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_WIDTH 2
8893 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_SET_MSK 0x00030000
8895 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_CLR_MSK 0xfffcffff
8897 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_RESET 0x0
8899 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_GET(value) (((value) & 0x00030000) >> 16)
8901 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_SET(value) (((value) << 16) & 0x00030000)
8903 #ifndef __ASSEMBLY__
8914 struct ALT_SYSMGR_MPU_CLR_L1_PARITY_s
8923 typedef volatile struct ALT_SYSMGR_MPU_CLR_L1_PARITY_s ALT_SYSMGR_MPU_CLR_L1_PARITY_t;
8927 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_RESET 0x00000000
8929 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_OFST 0xb0
8998 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_LSB 0
9000 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_MSB 7
9002 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_WIDTH 8
9004 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_SET_MSK 0x000000ff
9006 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_CLR_MSK 0xffffff00
9008 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_RESET 0x0
9010 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_GET(value) (((value) & 0x000000ff) >> 0)
9012 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_SET(value) (((value) << 0) & 0x000000ff)
9023 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_LSB 8
9025 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_MSB 15
9027 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_WIDTH 8
9029 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_SET_MSK 0x0000ff00
9031 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_CLR_MSK 0xffff00ff
9033 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_RESET 0x0
9035 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_GET(value) (((value) & 0x0000ff00) >> 8)
9037 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_SET(value) (((value) << 8) & 0x0000ff00)
9048 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_LSB 16
9050 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_MSB 17
9052 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_WIDTH 2
9054 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_SET_MSK 0x00030000
9056 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_CLR_MSK 0xfffcffff
9058 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_RESET 0x0
9060 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_GET(value) (((value) & 0x00030000) >> 16)
9062 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_SET(value) (((value) << 16) & 0x00030000)
9064 #ifndef __ASSEMBLY__
9075 struct ALT_SYSMGR_MPU_SET_L1_PARITY_s
9084 typedef volatile struct ALT_SYSMGR_MPU_SET_L1_PARITY_s ALT_SYSMGR_MPU_SET_L1_PARITY_t;
9088 #define ALT_SYSMGR_MPU_SET_L1_PARITY_RESET 0x00000000
9090 #define ALT_SYSMGR_MPU_SET_L1_PARITY_OFST 0xb4
9112 #define ALT_SYSMGR_NOC_TMO_EN_LSB 0
9114 #define ALT_SYSMGR_NOC_TMO_EN_MSB 0
9116 #define ALT_SYSMGR_NOC_TMO_EN_WIDTH 1
9118 #define ALT_SYSMGR_NOC_TMO_EN_SET_MSK 0x00000001
9120 #define ALT_SYSMGR_NOC_TMO_EN_CLR_MSK 0xfffffffe
9122 #define ALT_SYSMGR_NOC_TMO_EN_RESET 0x0
9124 #define ALT_SYSMGR_NOC_TMO_EN_GET(value) (((value) & 0x00000001) >> 0)
9126 #define ALT_SYSMGR_NOC_TMO_EN_SET(value) (((value) << 0) & 0x00000001)
9128 #ifndef __ASSEMBLY__
9139 struct ALT_SYSMGR_NOC_TMO_s
9146 typedef volatile struct ALT_SYSMGR_NOC_TMO_s ALT_SYSMGR_NOC_TMO_t;
9150 #define ALT_SYSMGR_NOC_TMO_RESET 0x00000000
9152 #define ALT_SYSMGR_NOC_TMO_OFST 0xc0
9184 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_LSB 0
9186 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_MSB 0
9188 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_WIDTH 1
9190 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_SET_MSK 0x00000001
9192 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_CLR_MSK 0xfffffffe
9194 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_RESET 0x0
9196 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_GET(value) (((value) & 0x00000001) >> 0)
9198 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_SET(value) (((value) << 0) & 0x00000001)
9207 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_LSB 4
9209 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_MSB 4
9211 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_WIDTH 1
9213 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_SET_MSK 0x00000010
9215 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_CLR_MSK 0xffffffef
9217 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_RESET 0x0
9219 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_GET(value) (((value) & 0x00000010) >> 4)
9221 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_SET(value) (((value) << 4) & 0x00000010)
9230 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_LSB 8
9232 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_MSB 8
9234 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_WIDTH 1
9236 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_SET_MSK 0x00000100
9238 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_CLR_MSK 0xfffffeff
9240 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_RESET 0x0
9242 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_GET(value) (((value) & 0x00000100) >> 8)
9244 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_SET(value) (((value) << 8) & 0x00000100)
9253 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_LSB 16
9255 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_MSB 16
9257 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_WIDTH 1
9259 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_SET_MSK 0x00010000
9261 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_CLR_MSK 0xfffeffff
9263 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_RESET 0x0
9265 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_GET(value) (((value) & 0x00010000) >> 16)
9267 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_SET(value) (((value) << 16) & 0x00010000)
9276 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_LSB 20
9278 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_MSB 20
9280 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_WIDTH 1
9282 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_SET_MSK 0x00100000
9284 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_CLR_MSK 0xffefffff
9286 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_RESET 0x0
9288 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_GET(value) (((value) & 0x00100000) >> 20)
9290 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_SET(value) (((value) << 20) & 0x00100000)
9299 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_LSB 24
9301 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_MSB 24
9303 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_WIDTH 1
9305 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_SET_MSK 0x01000000
9307 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_CLR_MSK 0xfeffffff
9309 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_RESET 0x0
9311 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_GET(value) (((value) & 0x01000000) >> 24)
9313 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_SET(value) (((value) << 24) & 0x01000000)
9315 #ifndef __ASSEMBLY__
9326 struct ALT_SYSMGR_NOC_IDLEREQ_SET_s
9328 uint32_t soc2fpga : 1;
9330 uint32_t lwsoc2fpga : 1;
9332 uint32_t fpga2soc : 1;
9334 uint32_t fpga2sdram0 : 1;
9336 uint32_t fpga2sdram1 : 1;
9338 uint32_t fpga2sdram2 : 1;
9343 typedef volatile struct ALT_SYSMGR_NOC_IDLEREQ_SET_s ALT_SYSMGR_NOC_IDLEREQ_SET_t;
9347 #define ALT_SYSMGR_NOC_IDLEREQ_SET_RESET 0x00000000
9349 #define ALT_SYSMGR_NOC_IDLEREQ_SET_OFST 0xc4
9381 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_LSB 0
9383 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_MSB 0
9385 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_WIDTH 1
9387 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_SET_MSK 0x00000001
9389 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_CLR_MSK 0xfffffffe
9391 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_RESET 0x0
9393 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_GET(value) (((value) & 0x00000001) >> 0)
9395 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_SET(value) (((value) << 0) & 0x00000001)
9404 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_LSB 4
9406 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_MSB 4
9408 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_WIDTH 1
9410 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_SET_MSK 0x00000010
9412 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_CLR_MSK 0xffffffef
9414 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_RESET 0x0
9416 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_GET(value) (((value) & 0x00000010) >> 4)
9418 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_SET(value) (((value) << 4) & 0x00000010)
9427 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_LSB 8
9429 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_MSB 8
9431 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_WIDTH 1
9433 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_SET_MSK 0x00000100
9435 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_CLR_MSK 0xfffffeff
9437 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_RESET 0x0
9439 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_GET(value) (((value) & 0x00000100) >> 8)
9441 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_SET(value) (((value) << 8) & 0x00000100)
9450 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_LSB 16
9452 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_MSB 16
9454 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_WIDTH 1
9456 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_SET_MSK 0x00010000
9458 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_CLR_MSK 0xfffeffff
9460 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_RESET 0x0
9462 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_GET(value) (((value) & 0x00010000) >> 16)
9464 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_SET(value) (((value) << 16) & 0x00010000)
9473 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_LSB 20
9475 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_MSB 20
9477 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_WIDTH 1
9479 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_SET_MSK 0x00100000
9481 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_CLR_MSK 0xffefffff
9483 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_RESET 0x0
9485 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_GET(value) (((value) & 0x00100000) >> 20)
9487 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_SET(value) (((value) << 20) & 0x00100000)
9496 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_LSB 24
9498 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_MSB 24
9500 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_WIDTH 1
9502 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_SET_MSK 0x01000000
9504 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_CLR_MSK 0xfeffffff
9506 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_RESET 0x0
9508 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_GET(value) (((value) & 0x01000000) >> 24)
9510 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_SET(value) (((value) << 24) & 0x01000000)
9512 #ifndef __ASSEMBLY__
9523 struct ALT_SYSMGR_NOC_IDLEREQ_CLR_s
9525 uint32_t soc2fpga : 1;
9527 uint32_t lwsoc2fpga : 1;
9529 uint32_t fpga2soc : 1;
9531 uint32_t fpga2sdram0 : 1;
9533 uint32_t fpga2sdram1 : 1;
9535 uint32_t fpga2sdram2 : 1;
9540 typedef volatile struct ALT_SYSMGR_NOC_IDLEREQ_CLR_s ALT_SYSMGR_NOC_IDLEREQ_CLR_t;
9544 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_RESET 0x00000000
9546 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_OFST 0xc8
9584 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_LSB 0
9586 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_MSB 0
9588 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_WIDTH 1
9590 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_SET_MSK 0x00000001
9592 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_CLR_MSK 0xfffffffe
9594 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_RESET 0x0
9596 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_GET(value) (((value) & 0x00000001) >> 0)
9598 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_SET(value) (((value) << 0) & 0x00000001)
9607 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_LSB 4
9609 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_MSB 4
9611 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_WIDTH 1
9613 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_SET_MSK 0x00000010
9615 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_CLR_MSK 0xffffffef
9617 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_RESET 0x0
9619 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_GET(value) (((value) & 0x00000010) >> 4)
9621 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_SET(value) (((value) << 4) & 0x00000010)
9630 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_LSB 8
9632 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_MSB 8
9634 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_WIDTH 1
9636 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_SET_MSK 0x00000100
9638 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_CLR_MSK 0xfffffeff
9640 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_RESET 0x0
9642 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_GET(value) (((value) & 0x00000100) >> 8)
9644 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_SET(value) (((value) << 8) & 0x00000100)
9653 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_LSB 16
9655 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_MSB 16
9657 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_WIDTH 1
9659 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_SET_MSK 0x00010000
9661 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_CLR_MSK 0xfffeffff
9663 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_RESET 0x0
9665 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_GET(value) (((value) & 0x00010000) >> 16)
9667 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_SET(value) (((value) << 16) & 0x00010000)
9676 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_LSB 20
9678 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_MSB 20
9680 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_WIDTH 1
9682 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_SET_MSK 0x00100000
9684 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_CLR_MSK 0xffefffff
9686 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_RESET 0x0
9688 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_GET(value) (((value) & 0x00100000) >> 20)
9690 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_SET(value) (((value) << 20) & 0x00100000)
9699 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_LSB 24
9701 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_MSB 24
9703 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_WIDTH 1
9705 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_SET_MSK 0x01000000
9707 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_CLR_MSK 0xfeffffff
9709 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_RESET 0x0
9711 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_GET(value) (((value) & 0x01000000) >> 24)
9713 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_SET(value) (((value) << 24) & 0x01000000)
9715 #ifndef __ASSEMBLY__
9726 struct ALT_SYSMGR_NOC_IDLEREQ_VALUE_s
9728 uint32_t soc2fpga : 1;
9730 uint32_t lwsoc2fpga : 1;
9732 uint32_t fpga2soc : 1;
9734 uint32_t fpga2sdram0 : 1;
9736 uint32_t fpga2sdram1 : 1;
9738 uint32_t fpga2sdram2 : 1;
9743 typedef volatile struct ALT_SYSMGR_NOC_IDLEREQ_VALUE_s ALT_SYSMGR_NOC_IDLEREQ_VALUE_t;
9747 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_RESET 0x00000000
9749 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_OFST 0xcc
9782 #define ALT_SYSMGR_NOC_IDLEACK_H2F_LSB 0
9784 #define ALT_SYSMGR_NOC_IDLEACK_H2F_MSB 0
9786 #define ALT_SYSMGR_NOC_IDLEACK_H2F_WIDTH 1
9788 #define ALT_SYSMGR_NOC_IDLEACK_H2F_SET_MSK 0x00000001
9790 #define ALT_SYSMGR_NOC_IDLEACK_H2F_CLR_MSK 0xfffffffe
9792 #define ALT_SYSMGR_NOC_IDLEACK_H2F_RESET 0x0
9794 #define ALT_SYSMGR_NOC_IDLEACK_H2F_GET(value) (((value) & 0x00000001) >> 0)
9796 #define ALT_SYSMGR_NOC_IDLEACK_H2F_SET(value) (((value) << 0) & 0x00000001)
9805 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_LSB 4
9807 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_MSB 4
9809 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_WIDTH 1
9811 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_SET_MSK 0x00000010
9813 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_CLR_MSK 0xffffffef
9815 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_RESET 0x0
9817 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_GET(value) (((value) & 0x00000010) >> 4)
9819 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_SET(value) (((value) << 4) & 0x00000010)
9828 #define ALT_SYSMGR_NOC_IDLEACK_F2H_LSB 8
9830 #define ALT_SYSMGR_NOC_IDLEACK_F2H_MSB 8
9832 #define ALT_SYSMGR_NOC_IDLEACK_F2H_WIDTH 1
9834 #define ALT_SYSMGR_NOC_IDLEACK_F2H_SET_MSK 0x00000100
9836 #define ALT_SYSMGR_NOC_IDLEACK_F2H_CLR_MSK 0xfffffeff
9838 #define ALT_SYSMGR_NOC_IDLEACK_F2H_RESET 0x0
9840 #define ALT_SYSMGR_NOC_IDLEACK_F2H_GET(value) (((value) & 0x00000100) >> 8)
9842 #define ALT_SYSMGR_NOC_IDLEACK_F2H_SET(value) (((value) << 8) & 0x00000100)
9851 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_LSB 16
9853 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_MSB 16
9855 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_WIDTH 1
9857 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_SET_MSK 0x00010000
9859 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_CLR_MSK 0xfffeffff
9861 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_RESET 0x0
9863 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_GET(value) (((value) & 0x00010000) >> 16)
9865 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_SET(value) (((value) << 16) & 0x00010000)
9874 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_LSB 20
9876 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_MSB 20
9878 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_WIDTH 1
9880 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_SET_MSK 0x00100000
9882 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_CLR_MSK 0xffefffff
9884 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_RESET 0x0
9886 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_GET(value) (((value) & 0x00100000) >> 20)
9888 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_SET(value) (((value) << 20) & 0x00100000)
9897 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_LSB 24
9899 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_MSB 24
9901 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_WIDTH 1
9903 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_SET_MSK 0x01000000
9905 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_CLR_MSK 0xfeffffff
9907 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_RESET 0x0
9909 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_GET(value) (((value) & 0x01000000) >> 24)
9911 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_SET(value) (((value) << 24) & 0x01000000)
9913 #ifndef __ASSEMBLY__
9924 struct ALT_SYSMGR_NOC_IDLEACK_s
9926 uint32_t soc2fpga : 1;
9928 uint32_t lwsoc2fpga : 1;
9930 uint32_t fpga2soc : 1;
9932 uint32_t fpga2sdram0 : 1;
9934 uint32_t fpga2sdram1 : 1;
9936 uint32_t fpga2sdram2 : 1;
9941 typedef volatile struct ALT_SYSMGR_NOC_IDLEACK_s ALT_SYSMGR_NOC_IDLEACK_t;
9945 #define ALT_SYSMGR_NOC_IDLEACK_RESET 0x00000000
9947 #define ALT_SYSMGR_NOC_IDLEACK_OFST 0xd0
9980 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_LSB 0
9982 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_MSB 0
9984 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_WIDTH 1
9986 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_SET_MSK 0x00000001
9988 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_CLR_MSK 0xfffffffe
9990 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_RESET 0x0
9992 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_GET(value) (((value) & 0x00000001) >> 0)
9994 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_SET(value) (((value) << 0) & 0x00000001)
10003 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_LSB 4
10005 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_MSB 4
10007 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_WIDTH 1
10009 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_SET_MSK 0x00000010
10011 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_CLR_MSK 0xffffffef
10013 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_RESET 0x0
10015 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_GET(value) (((value) & 0x00000010) >> 4)
10017 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_SET(value) (((value) << 4) & 0x00000010)
10026 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_LSB 8
10028 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_MSB 8
10030 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_WIDTH 1
10032 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_SET_MSK 0x00000100
10034 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_CLR_MSK 0xfffffeff
10036 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_RESET 0x0
10038 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_GET(value) (((value) & 0x00000100) >> 8)
10040 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_SET(value) (((value) << 8) & 0x00000100)
10049 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_LSB 16
10051 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_MSB 16
10053 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_WIDTH 1
10055 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_SET_MSK 0x00010000
10057 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_CLR_MSK 0xfffeffff
10059 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_RESET 0x0
10061 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_GET(value) (((value) & 0x00010000) >> 16)
10063 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_SET(value) (((value) << 16) & 0x00010000)
10072 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_LSB 20
10074 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_MSB 20
10076 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_WIDTH 1
10078 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_SET_MSK 0x00100000
10080 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_CLR_MSK 0xffefffff
10082 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_RESET 0x0
10084 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_GET(value) (((value) & 0x00100000) >> 20)
10086 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_SET(value) (((value) << 20) & 0x00100000)
10095 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_LSB 24
10097 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_MSB 24
10099 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_WIDTH 1
10101 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_SET_MSK 0x01000000
10103 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_CLR_MSK 0xfeffffff
10105 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_RESET 0x0
10107 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_GET(value) (((value) & 0x01000000) >> 24)
10109 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_SET(value) (((value) << 24) & 0x01000000)
10111 #ifndef __ASSEMBLY__
10122 struct ALT_SYSMGR_NOC_IDLESTAT_s
10124 uint32_t soc2fpga : 1;
10126 uint32_t lwsoc2fpga : 1;
10128 uint32_t fpga2soc : 1;
10130 uint32_t fpga2sdram0 : 1;
10132 uint32_t fpga2sdram1 : 1;
10134 uint32_t fpga2sdram2 : 1;
10139 typedef volatile struct ALT_SYSMGR_NOC_IDLESTAT_s ALT_SYSMGR_NOC_IDLESTAT_t;
10143 #define ALT_SYSMGR_NOC_IDLESTAT_RESET 0x00000000
10145 #define ALT_SYSMGR_NOC_IDLESTAT_OFST 0xd4
10169 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_LSB 0
10171 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_MSB 0
10173 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_WIDTH 1
10175 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_SET_MSK 0x00000001
10177 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_CLR_MSK 0xfffffffe
10179 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_RESET 0x0
10181 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_GET(value) (((value) & 0x00000001) >> 0)
10183 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_SET(value) (((value) << 0) & 0x00000001)
10185 #ifndef __ASSEMBLY__
10196 struct ALT_SYSMGR_F2H_CTL_s
10198 uint32_t allow_secure : 1;
10203 typedef volatile struct ALT_SYSMGR_F2H_CTL_s ALT_SYSMGR_F2H_CTL_t;
10207 #define ALT_SYSMGR_F2H_CTL_RESET 0x00000000
10209 #define ALT_SYSMGR_F2H_CTL_OFST 0xd8
10241 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_LSB 0
10243 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_MSB 1
10245 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_WIDTH 2
10247 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_SET_MSK 0x00000003
10249 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_CLR_MSK 0xfffffffc
10251 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_RESET 0x1
10253 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_GET(value) (((value) & 0x00000003) >> 0)
10255 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_SET(value) (((value) << 0) & 0x00000003)
10264 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_LSB 4
10266 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_MSB 5
10268 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_WIDTH 2
10270 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_SET_MSK 0x00000030
10272 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_CLR_MSK 0xffffffcf
10274 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_RESET 0x1
10276 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_GET(value) (((value) & 0x00000030) >> 4)
10278 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_SET(value) (((value) << 4) & 0x00000030)
10287 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_LSB 8
10289 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_MSB 9
10291 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_WIDTH 2
10293 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_SET_MSK 0x00000300
10295 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_CLR_MSK 0xfffffcff
10297 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_RESET 0x1
10299 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_GET(value) (((value) & 0x00000300) >> 8)
10301 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_SET(value) (((value) << 8) & 0x00000300)
10310 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_LSB 16
10312 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_MSB 17
10314 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_WIDTH 2
10316 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_SET_MSK 0x00030000
10318 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_CLR_MSK 0xfffcffff
10320 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_RESET 0x0
10322 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_GET(value) (((value) & 0x00030000) >> 16)
10324 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_SET(value) (((value) << 16) & 0x00030000)
10333 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_LSB 20
10335 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_MSB 21
10337 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_WIDTH 2
10339 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_SET_MSK 0x00300000
10341 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_CLR_MSK 0xffcfffff
10343 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_RESET 0x0
10345 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_GET(value) (((value) & 0x00300000) >> 20)
10347 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_SET(value) (((value) << 20) & 0x00300000)
10356 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_LSB 24
10358 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_MSB 26
10360 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_WIDTH 3
10362 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_SET_MSK 0x07000000
10364 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_CLR_MSK 0xf8ffffff
10366 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_RESET 0x0
10368 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_GET(value) (((value) & 0x07000000) >> 24)
10370 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_SET(value) (((value) << 24) & 0x07000000)
10379 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_LSB 28
10381 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_MSB 29
10383 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_WIDTH 2
10385 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_SET_MSK 0x30000000
10387 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_CLR_MSK 0xcfffffff
10389 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_RESET 0x1
10391 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_GET(value) (((value) & 0x30000000) >> 28)
10393 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_SET(value) (((value) << 28) & 0x30000000)
10395 #ifndef __ASSEMBLY__
10406 struct ALT_SYSMGR_TSMC_TSEL_0_s
10408 uint32_t rom_rtsel : 2;
10410 uint32_t rom_ptsel : 2;
10412 uint32_t rom_trb : 2;
10414 uint32_t mpul1_mcw : 2;
10416 uint32_t mpul1_mcr : 2;
10418 uint32_t mpul2_wtsel : 3;
10420 uint32_t mpul2_rtsel : 2;
10425 typedef volatile struct ALT_SYSMGR_TSMC_TSEL_0_s ALT_SYSMGR_TSMC_TSEL_0_t;
10429 #define ALT_SYSMGR_TSMC_TSEL_0_RESET 0x10000111
10431 #define ALT_SYSMGR_TSMC_TSEL_0_OFST 0x100
10465 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_LSB 0
10467 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_MSB 2
10469 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_WIDTH 3
10471 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_SET_MSK 0x00000007
10473 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_CLR_MSK 0xfffffff8
10475 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_RESET 0x0
10477 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_GET(value) (((value) & 0x00000007) >> 0)
10479 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_SET(value) (((value) << 0) & 0x00000007)
10488 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_LSB 4
10490 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_MSB 5
10492 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_WIDTH 2
10494 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_SET_MSK 0x00000030
10496 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_CLR_MSK 0xffffffcf
10498 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_RESET 0x1
10500 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_GET(value) (((value) & 0x00000030) >> 4)
10502 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_SET(value) (((value) << 4) & 0x00000030)
10511 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_LSB 8
10513 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_MSB 10
10515 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_WIDTH 3
10517 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_SET_MSK 0x00000700
10519 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_CLR_MSK 0xfffff8ff
10521 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_RESET 0x0
10523 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_GET(value) (((value) & 0x00000700) >> 8)
10525 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_SET(value) (((value) << 8) & 0x00000700)
10534 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_LSB 12
10536 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_MSB 13
10538 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_WIDTH 2
10540 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_SET_MSK 0x00003000
10542 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_CLR_MSK 0xffffcfff
10544 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_RESET 0x1
10546 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_GET(value) (((value) & 0x00003000) >> 12)
10548 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_SET(value) (((value) << 12) & 0x00003000)
10557 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_LSB 16
10559 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_MSB 18
10561 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_WIDTH 3
10563 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_SET_MSK 0x00070000
10565 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_CLR_MSK 0xfff8ffff
10567 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_RESET 0x0
10569 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_GET(value) (((value) & 0x00070000) >> 16)
10571 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_SET(value) (((value) << 16) & 0x00070000)
10580 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_LSB 20
10582 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_MSB 21
10584 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_WIDTH 2
10586 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_SET_MSK 0x00300000
10588 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_CLR_MSK 0xffcfffff
10590 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_RESET 0x1
10592 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_GET(value) (((value) & 0x00300000) >> 20)
10594 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_SET(value) (((value) << 20) & 0x00300000)
10603 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_LSB 24
10605 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_MSB 26
10607 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_WIDTH 3
10609 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_SET_MSK 0x07000000
10611 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_CLR_MSK 0xf8ffffff
10613 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_RESET 0x0
10615 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_GET(value) (((value) & 0x07000000) >> 24)
10617 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_SET(value) (((value) << 24) & 0x07000000)
10626 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_LSB 28
10628 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_MSB 29
10630 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_WIDTH 2
10632 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_SET_MSK 0x30000000
10634 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_CLR_MSK 0xcfffffff
10636 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_RESET 0x1
10638 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_GET(value) (((value) & 0x30000000) >> 28)
10640 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_SET(value) (((value) << 28) & 0x30000000)
10642 #ifndef __ASSEMBLY__
10653 struct ALT_SYSMGR_TSMC_TSEL_1_s
10655 uint32_t ocram_wtsel : 3;
10657 uint32_t ocram_rtsel : 2;
10659 uint32_t otg_wtsel : 3;
10661 uint32_t otg_rtsel : 2;
10663 uint32_t qspi_wtsel : 3;
10665 uint32_t qspi_rtsel : 2;
10667 uint32_t etf_wtsel : 3;
10669 uint32_t etf_rtsel : 2;
10674 typedef volatile struct ALT_SYSMGR_TSMC_TSEL_1_s ALT_SYSMGR_TSMC_TSEL_1_t;
10678 #define ALT_SYSMGR_TSMC_TSEL_1_RESET 0x10101010
10680 #define ALT_SYSMGR_TSMC_TSEL_1_OFST 0x104
10714 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_LSB 0
10716 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_MSB 1
10718 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_WIDTH 2
10720 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_SET_MSK 0x00000003
10722 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_CLR_MSK 0xfffffffc
10724 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_RESET 0x2
10726 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_GET(value) (((value) & 0x00000003) >> 0)
10728 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_SET(value) (((value) << 0) & 0x00000003)
10737 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_LSB 2
10739 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_MSB 3
10741 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_WIDTH 2
10743 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_SET_MSK 0x0000000c
10745 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_CLR_MSK 0xfffffff3
10747 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_RESET 0x2
10749 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_GET(value) (((value) & 0x0000000c) >> 2)
10751 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_SET(value) (((value) << 2) & 0x0000000c)
10760 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_LSB 4
10762 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_MSB 6
10764 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_WIDTH 3
10766 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_SET_MSK 0x00000070
10768 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_CLR_MSK 0xffffff8f
10770 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_RESET 0x4
10772 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_GET(value) (((value) & 0x00000070) >> 4)
10774 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_SET(value) (((value) << 4) & 0x00000070)
10783 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_LSB 7
10785 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_MSB 7
10787 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_WIDTH 1
10789 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_SET_MSK 0x00000080
10791 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_CLR_MSK 0xffffff7f
10793 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_RESET 0x0
10795 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_GET(value) (((value) & 0x00000080) >> 7)
10797 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_SET(value) (((value) << 7) & 0x00000080)
10806 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_LSB 8
10808 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_MSB 9
10810 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_WIDTH 2
10812 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_SET_MSK 0x00000300
10814 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_CLR_MSK 0xfffffcff
10816 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_RESET 0x2
10818 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_GET(value) (((value) & 0x00000300) >> 8)
10820 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_SET(value) (((value) << 8) & 0x00000300)
10829 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_LSB 10
10831 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_MSB 11
10833 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_WIDTH 2
10835 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_SET_MSK 0x00000c00
10837 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_CLR_MSK 0xfffff3ff
10839 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_RESET 0x2
10841 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_GET(value) (((value) & 0x00000c00) >> 10)
10843 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_SET(value) (((value) << 10) & 0x00000c00)
10852 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_LSB 12
10854 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_MSB 14
10856 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_WIDTH 3
10858 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_SET_MSK 0x00007000
10860 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_CLR_MSK 0xffff8fff
10862 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_RESET 0x4
10864 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_GET(value) (((value) & 0x00007000) >> 12)
10866 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_SET(value) (((value) << 12) & 0x00007000)
10875 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_LSB 15
10877 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_MSB 15
10879 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_WIDTH 1
10881 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_SET_MSK 0x00008000
10883 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_CLR_MSK 0xffff7fff
10885 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_RESET 0x0
10887 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_GET(value) (((value) & 0x00008000) >> 15)
10889 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_SET(value) (((value) << 15) & 0x00008000)
10898 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_LSB 16
10900 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_MSB 17
10902 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_WIDTH 2
10904 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_SET_MSK 0x00030000
10906 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_CLR_MSK 0xfffcffff
10908 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_RESET 0x2
10910 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_GET(value) (((value) & 0x00030000) >> 16)
10912 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_SET(value) (((value) << 16) & 0x00030000)
10921 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_LSB 18
10923 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_MSB 19
10925 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_WIDTH 2
10927 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_SET_MSK 0x000c0000
10929 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_CLR_MSK 0xfff3ffff
10931 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_RESET 0x2
10933 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_GET(value) (((value) & 0x000c0000) >> 18)
10935 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_SET(value) (((value) << 18) & 0x000c0000)
10944 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_LSB 20
10946 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_MSB 22
10948 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_WIDTH 3
10950 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_SET_MSK 0x00700000
10952 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_CLR_MSK 0xff8fffff
10954 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_RESET 0x4
10956 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_GET(value) (((value) & 0x00700000) >> 20)
10958 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_SET(value) (((value) << 20) & 0x00700000)
10967 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_LSB 23
10969 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_MSB 23
10971 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_WIDTH 1
10973 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_SET_MSK 0x00800000
10975 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_CLR_MSK 0xff7fffff
10977 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_RESET 0x0
10979 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_GET(value) (((value) & 0x00800000) >> 23)
10981 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_SET(value) (((value) << 23) & 0x00800000)
10990 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_LSB 24
10992 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_MSB 25
10994 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_WIDTH 2
10996 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_SET_MSK 0x03000000
10998 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_CLR_MSK 0xfcffffff
11000 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_RESET 0x2
11002 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_GET(value) (((value) & 0x03000000) >> 24)
11004 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_SET(value) (((value) << 24) & 0x03000000)
11013 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_LSB 26
11015 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_MSB 27
11017 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_WIDTH 2
11019 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_SET_MSK 0x0c000000
11021 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_CLR_MSK 0xf3ffffff
11023 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_RESET 0x2
11025 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_GET(value) (((value) & 0x0c000000) >> 26)
11027 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_SET(value) (((value) << 26) & 0x0c000000)
11036 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_LSB 28
11038 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_MSB 30
11040 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_WIDTH 3
11042 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_SET_MSK 0x70000000
11044 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_CLR_MSK 0x8fffffff
11046 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_RESET 0x4
11048 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_GET(value) (((value) & 0x70000000) >> 28)
11050 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_SET(value) (((value) << 28) & 0x70000000)
11059 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_LSB 31
11061 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_MSB 31
11063 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_WIDTH 1
11065 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_SET_MSK 0x80000000
11067 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_CLR_MSK 0x7fffffff
11069 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_RESET 0x0
11071 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_GET(value) (((value) & 0x80000000) >> 31)
11073 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_SET(value) (((value) << 31) & 0x80000000)
11075 #ifndef __ASSEMBLY__
11086 struct ALT_SYSMGR_TSMC_TSEL_2_s
11088 uint32_t nandecc_wct : 2;
11089 uint32_t nandecc_rct : 2;
11090 uint32_t nandecc_kp : 3;
11091 uint32_t nandecc_tm : 1;
11092 uint32_t nandwr_wct : 2;
11093 uint32_t nandwr_rct : 2;
11094 uint32_t nandwr_kp : 3;
11095 uint32_t nandwr_tm : 1;
11096 uint32_t nandrd_wct : 2;
11097 uint32_t nandrd_rct : 2;
11098 uint32_t nandrd_kp : 3;
11099 uint32_t nandrd_tm : 1;
11100 uint32_t sdmmc_wct : 2;
11101 uint32_t sdmmc_rct : 2;
11102 uint32_t sdmmc_kp : 3;
11103 uint32_t sdmmc_tm : 1;
11107 typedef volatile struct ALT_SYSMGR_TSMC_TSEL_2_s ALT_SYSMGR_TSMC_TSEL_2_t;
11111 #define ALT_SYSMGR_TSMC_TSEL_2_RESET 0x4a4a4a4a
11113 #define ALT_SYSMGR_TSMC_TSEL_2_OFST 0x108
11144 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_LSB 0
11146 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_MSB 1
11148 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_WIDTH 2
11150 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_SET_MSK 0x00000003
11152 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_CLR_MSK 0xfffffffc
11154 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_RESET 0x2
11156 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_GET(value) (((value) & 0x00000003) >> 0)
11158 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_SET(value) (((value) << 0) & 0x00000003)
11167 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_LSB 2
11169 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_MSB 3
11171 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_WIDTH 2
11173 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_SET_MSK 0x0000000c
11175 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_CLR_MSK 0xfffffff3
11177 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_RESET 0x2
11179 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_GET(value) (((value) & 0x0000000c) >> 2)
11181 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_SET(value) (((value) << 2) & 0x0000000c)
11190 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_LSB 4
11192 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_MSB 6
11194 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_WIDTH 3
11196 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_SET_MSK 0x00000070
11198 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_CLR_MSK 0xffffff8f
11200 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_RESET 0x4
11202 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_GET(value) (((value) & 0x00000070) >> 4)
11204 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_SET(value) (((value) << 4) & 0x00000070)
11213 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_LSB 7
11215 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_MSB 7
11217 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_WIDTH 1
11219 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_SET_MSK 0x00000080
11221 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_CLR_MSK 0xffffff7f
11223 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_RESET 0x0
11225 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_GET(value) (((value) & 0x00000080) >> 7)
11227 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_SET(value) (((value) << 7) & 0x00000080)
11236 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_LSB 8
11238 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_MSB 9
11240 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_WIDTH 2
11242 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_SET_MSK 0x00000300
11244 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_CLR_MSK 0xfffffcff
11246 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_RESET 0x2
11248 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_GET(value) (((value) & 0x00000300) >> 8)
11250 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_SET(value) (((value) << 8) & 0x00000300)
11259 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_LSB 10
11261 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_MSB 11
11263 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_WIDTH 2
11265 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_SET_MSK 0x00000c00
11267 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_CLR_MSK 0xfffff3ff
11269 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_RESET 0x2
11271 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_GET(value) (((value) & 0x00000c00) >> 10)
11273 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_SET(value) (((value) << 10) & 0x00000c00)
11282 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_LSB 12
11284 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_MSB 14
11286 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_WIDTH 3
11288 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_SET_MSK 0x00007000
11290 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_CLR_MSK 0xffff8fff
11292 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_RESET 0x4
11294 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_GET(value) (((value) & 0x00007000) >> 12)
11296 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_SET(value) (((value) << 12) & 0x00007000)
11305 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_LSB 15
11307 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_MSB 15
11309 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_WIDTH 1
11311 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_SET_MSK 0x00008000
11313 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_CLR_MSK 0xffff7fff
11315 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_RESET 0x0
11317 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_GET(value) (((value) & 0x00008000) >> 15)
11319 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_SET(value) (((value) << 15) & 0x00008000)
11328 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_LSB 16
11330 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_MSB 17
11332 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_WIDTH 2
11334 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_SET_MSK 0x00030000
11336 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_CLR_MSK 0xfffcffff
11338 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_RESET 0x2
11340 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_GET(value) (((value) & 0x00030000) >> 16)
11342 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_SET(value) (((value) << 16) & 0x00030000)
11351 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_LSB 18
11353 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_MSB 19
11355 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_WIDTH 2
11357 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_SET_MSK 0x000c0000
11359 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_CLR_MSK 0xfff3ffff
11361 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_RESET 0x2
11363 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_GET(value) (((value) & 0x000c0000) >> 18)
11365 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_SET(value) (((value) << 18) & 0x000c0000)
11374 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_LSB 20
11376 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_MSB 22
11378 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_WIDTH 3
11380 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_SET_MSK 0x00700000
11382 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_CLR_MSK 0xff8fffff
11384 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_RESET 0x4
11386 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_GET(value) (((value) & 0x00700000) >> 20)
11388 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_SET(value) (((value) << 20) & 0x00700000)
11397 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_LSB 23
11399 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_MSB 23
11401 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_WIDTH 1
11403 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_SET_MSK 0x00800000
11405 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_CLR_MSK 0xff7fffff
11407 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_RESET 0x0
11409 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_GET(value) (((value) & 0x00800000) >> 23)
11411 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_SET(value) (((value) << 23) & 0x00800000)
11413 #ifndef __ASSEMBLY__
11424 struct ALT_SYSMGR_TSMC_TSEL_3_s
11426 uint32_t emacrx_wct : 2;
11427 uint32_t emacrx_rct : 2;
11428 uint32_t emacrx_kp : 3;
11429 uint32_t emacrx_tm : 1;
11430 uint32_t emactx_wct : 2;
11431 uint32_t emactx_rct : 2;
11432 uint32_t emactx_kp : 3;
11433 uint32_t emactx_tm : 1;
11434 uint32_t dmac_wct : 2;
11435 uint32_t dmac_rct : 2;
11436 uint32_t dmac_kp : 3;
11437 uint32_t dmac_tm : 1;
11442 typedef volatile struct ALT_SYSMGR_TSMC_TSEL_3_s ALT_SYSMGR_TSMC_TSEL_3_t;
11446 #define ALT_SYSMGR_TSMC_TSEL_3_RESET 0x004a4a4a
11448 #define ALT_SYSMGR_TSMC_TSEL_3_OFST 0x10c
11450 #ifndef __ASSEMBLY__
11461 struct ALT_SYSMGR_s
11463 ALT_SYSMGR_SILICONID1_t siliconid1;
11464 ALT_SYSMGR_SILICONID2_t siliconid2;
11465 ALT_SYSMGR_WDDBG_t wddbg;
11466 ALT_SYSMGR_BOOT_t bootinfo;
11467 ALT_SYSMGR_MPU_CTL_L2_ECC_t mpu_ctrl_l2_ecc;
11468 volatile uint32_t _pad_0x14_0x1f[3];
11469 ALT_SYSMGR_DMA_t dma;
11470 ALT_SYSMGR_DMA_PERIPH_t dma_periph;
11471 ALT_SYSMGR_SDMMC_t sdmmc;
11472 ALT_SYSMGR_SDMMC_L3MST_t sdmmc_l3master;
11473 ALT_SYSMGR_NAND_BOOTSTRAP_t nand_bootstrap;
11474 ALT_SYSMGR_NAND_L3MST_t nand_l3master;
11475 ALT_SYSMGR_USB0_L3MST_t usb0_l3master;
11476 ALT_SYSMGR_USB1_L3MST_t usb1_l3master;
11477 ALT_SYSMGR_EMAC_GLOB_t emac_global;
11478 ALT_SYSMGR_EMAC0_t emac0;
11479 ALT_SYSMGR_EMAC1_t emac1;
11480 ALT_SYSMGR_EMAC2_t emac2;
11481 volatile uint32_t _pad_0x50_0x5f[4];
11482 ALT_SYSMGR_FPGAINTF_EN_GLOB_t fpgaintf_en_global;
11483 ALT_SYSMGR_FPGAINTF_EN_0_t fpgaintf_en_0;
11484 ALT_SYSMGR_FPGAINTF_EN_1_t fpgaintf_en_1;
11485 ALT_SYSMGR_FPGAINTF_EN_2_t fpgaintf_en_2;
11486 ALT_SYSMGR_FPGAINTF_EN_3_t fpgaintf_en_3;
11487 volatile uint32_t _pad_0x74_0x7f[3];
11488 ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_t noc_addr_remap_value;
11489 ALT_SYSMGR_NOC_ADDR_REMAP_SET_t noc_addr_remap_set;
11490 ALT_SYSMGR_NOC_ADDR_REMAP_CLR_t noc_addr_remap_clear;
11491 volatile uint32_t _pad_0x8c_0x8f;
11492 ALT_SYSMGR_ECC_INTMSK_VALUE_t ecc_intmask_value;
11493 ALT_SYSMGR_ECC_INTMSK_SET_t ecc_intmask_set;
11494 ALT_SYSMGR_ECC_INTMSK_CLR_t ecc_intmask_clr;
11495 ALT_SYSMGR_ECC_INTSTAT_SERR_t ecc_intstatus_serr;
11496 ALT_SYSMGR_ECC_INTSTAT_DERR_t ecc_intstatus_derr;
11497 ALT_SYSMGR_MPU_STAT_L2_ECC_t mpu_status_l2_ecc;
11498 ALT_SYSMGR_MPU_CLR_L2_ECC_t mpu_clear_l2_ecc;
11499 ALT_SYSMGR_MPU_STAT_L1_PARITY_t mpu_status_l1_parity;
11500 ALT_SYSMGR_MPU_CLR_L1_PARITY_t mpu_clear_l1_parity;
11501 ALT_SYSMGR_MPU_SET_L1_PARITY_t mpu_set_l1_parity;
11502 volatile uint32_t _pad_0xb8_0xbf[2];
11503 ALT_SYSMGR_NOC_TMO_t noc_timeout;
11504 ALT_SYSMGR_NOC_IDLEREQ_SET_t noc_idlereq_set;
11505 ALT_SYSMGR_NOC_IDLEREQ_CLR_t noc_idlereq_clr;
11506 ALT_SYSMGR_NOC_IDLEREQ_VALUE_t noc_idlereq_value;
11507 ALT_SYSMGR_NOC_IDLEACK_t noc_idleack;
11508 ALT_SYSMGR_NOC_IDLESTAT_t noc_idlestatus;
11509 ALT_SYSMGR_F2H_CTL_t fpga2soc_ctrl;
11510 volatile uint32_t _pad_0xdc_0xff[9];
11511 ALT_SYSMGR_TSMC_TSEL_0_t tsmc_tsel_0;
11512 ALT_SYSMGR_TSMC_TSEL_1_t tsmc_tsel_1;
11513 ALT_SYSMGR_TSMC_TSEL_2_t tsmc_tsel_2;
11514 ALT_SYSMGR_TSMC_TSEL_3_t tsmc_tsel_3;
11515 volatile uint32_t _pad_0x110_0x200[60];
11519 typedef volatile struct ALT_SYSMGR_s ALT_SYSMGR_t;
11521 struct ALT_SYSMGR_raw_s
11523 volatile uint32_t siliconid1;
11524 volatile uint32_t siliconid2;
11525 volatile uint32_t wddbg;
11526 volatile uint32_t bootinfo;
11527 volatile uint32_t mpu_ctrl_l2_ecc;
11528 uint32_t _pad_0x14_0x1f[3];
11529 volatile uint32_t dma;
11530 volatile uint32_t dma_periph;
11531 volatile uint32_t sdmmc;
11532 volatile uint32_t sdmmc_l3master;
11533 volatile uint32_t nand_bootstrap;
11534 volatile uint32_t nand_l3master;
11535 volatile uint32_t usb0_l3master;
11536 volatile uint32_t usb1_l3master;
11537 volatile uint32_t emac_global;
11538 volatile uint32_t emac0;
11539 volatile uint32_t emac1;
11540 volatile uint32_t emac2;
11541 uint32_t _pad_0x50_0x5f[4];
11542 volatile uint32_t fpgaintf_en_global;
11543 volatile uint32_t fpgaintf_en_0;
11544 volatile uint32_t fpgaintf_en_1;
11545 volatile uint32_t fpgaintf_en_2;
11546 volatile uint32_t fpgaintf_en_3;
11547 uint32_t _pad_0x74_0x7f[3];
11548 volatile uint32_t noc_addr_remap_value;
11549 volatile uint32_t noc_addr_remap_set;
11550 volatile uint32_t noc_addr_remap_clear;
11551 uint32_t _pad_0x8c_0x8f;
11552 volatile uint32_t ecc_intmask_value;
11553 volatile uint32_t ecc_intmask_set;
11554 volatile uint32_t ecc_intmask_clr;
11555 volatile uint32_t ecc_intstatus_serr;
11556 volatile uint32_t ecc_intstatus_derr;
11557 volatile uint32_t mpu_status_l2_ecc;
11558 volatile uint32_t mpu_clear_l2_ecc;
11559 volatile uint32_t mpu_status_l1_parity;
11560 volatile uint32_t mpu_clear_l1_parity;
11561 volatile uint32_t mpu_set_l1_parity;
11562 uint32_t _pad_0xb8_0xbf[2];
11563 volatile uint32_t noc_timeout;
11564 volatile uint32_t noc_idlereq_set;
11565 volatile uint32_t noc_idlereq_clr;
11566 volatile uint32_t noc_idlereq_value;
11567 volatile uint32_t noc_idleack;
11568 volatile uint32_t noc_idlestatus;
11569 volatile uint32_t fpga2soc_ctrl;
11570 uint32_t _pad_0xdc_0xff[9];
11571 volatile uint32_t tsmc_tsel_0;
11572 volatile uint32_t tsmc_tsel_1;
11573 volatile uint32_t tsmc_tsel_2;
11574 volatile uint32_t tsmc_tsel_3;
11575 uint32_t _pad_0x110_0x200[60];
11579 typedef volatile struct ALT_SYSMGR_raw_s ALT_SYSMGR_raw_t;
11624 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_E_DIS 0x0
11629 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_E_EN 0x1
11632 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_LSB 0
11634 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_MSB 0
11636 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_WIDTH 1
11638 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_SET_MSK 0x00000001
11640 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_CLR_MSK 0xfffffffe
11642 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_RESET 0x0
11644 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_GET(value) (((value) & 0x00000001) >> 0)
11646 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_SET(value) (((value) << 0) & 0x00000001)
11648 #ifndef __ASSEMBLY__
11659 struct ALT_SYSMGR_ROM_ROMHW_CTL_s
11661 uint32_t waitstate : 1;
11666 typedef volatile struct ALT_SYSMGR_ROM_ROMHW_CTL_s ALT_SYSMGR_ROM_ROMHW_CTL_t;
11670 #define ALT_SYSMGR_ROM_ROMHW_CTL_RESET 0x00000100
11672 #define ALT_SYSMGR_ROM_ROMHW_CTL_OFST 0x0
11713 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_E_DISD 0x0
11718 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_E_END 0x1
11721 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_LSB 0
11723 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_MSB 0
11725 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_WIDTH 1
11727 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_SET_MSK 0x00000001
11729 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_CLR_MSK 0xfffffffe
11731 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_RESET 0x0
11733 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_GET(value) (((value) & 0x00000001) >> 0)
11735 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_SET(value) (((value) << 0) & 0x00000001)
11760 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_E_DISD 0x0
11765 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_E_END 0x1
11768 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_LSB 1
11770 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_MSB 1
11772 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_WIDTH 1
11774 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_SET_MSK 0x00000002
11776 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_CLR_MSK 0xfffffffd
11778 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_RESET 0x0
11780 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_GET(value) (((value) & 0x00000002) >> 1)
11782 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_SET(value) (((value) << 1) & 0x00000002)
11784 #ifndef __ASSEMBLY__
11795 struct ALT_SYSMGR_ROM_ROMCODE_CTL_s
11797 uint32_t warmrstcfgpinmux : 1;
11798 uint32_t warmrstcfgio : 1;
11803 typedef volatile struct ALT_SYSMGR_ROM_ROMCODE_CTL_s ALT_SYSMGR_ROM_ROMCODE_CTL_t;
11807 #define ALT_SYSMGR_ROM_ROMCODE_CTL_RESET 0x00000000
11809 #define ALT_SYSMGR_ROM_ROMCODE_CTL_OFST 0x4
11852 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_LSB 0
11854 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_MSB 31
11856 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_WIDTH 32
11858 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_SET_MSK 0xffffffff
11860 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_CLR_MSK 0x00000000
11862 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_RESET 0x0
11864 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
11866 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_SET(value) (((value) << 0) & 0xffffffff)
11868 #ifndef __ASSEMBLY__
11879 struct ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_s
11881 uint32_t value : 32;
11885 typedef volatile struct ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_s ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_t;
11889 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_RESET 0x00000000
11891 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_OFST 0x8
11927 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_E_INVALID 0x0
11932 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_E_VALID 0x49535756
11935 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_LSB 0
11937 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_MSB 31
11939 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_WIDTH 32
11941 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_SET_MSK 0xffffffff
11943 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_CLR_MSK 0x00000000
11945 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_RESET 0x0
11947 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
11949 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_SET(value) (((value) << 0) & 0xffffffff)
11951 #ifndef __ASSEMBLY__
11962 struct ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_s
11964 uint32_t value : 32;
11968 typedef volatile struct ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_s ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_t;
11972 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_RESET 0x00000000
11974 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_OFST 0xc
12001 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_LSB 0
12003 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_MSB 1
12005 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_WIDTH 2
12007 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_SET_MSK 0x00000003
12009 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_CLR_MSK 0xfffffffc
12011 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_RESET 0x0
12013 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_GET(value) (((value) & 0x00000003) >> 0)
12015 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_SET(value) (((value) << 0) & 0x00000003)
12017 #ifndef __ASSEMBLY__
12028 struct ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_s
12030 uint32_t index : 2;
12035 typedef volatile struct ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_s ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_t;
12039 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_RESET 0x00000000
12041 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_OFST 0x10
12080 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_E_DISD 0x0
12085 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_E_END 0xae9efebc
12088 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_LSB 0
12090 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_MSB 31
12092 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_WIDTH 32
12094 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_SET_MSK 0xffffffff
12096 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_CLR_MSK 0x00000000
12098 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_RESET 0x0
12100 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_GET(value) (((value) & 0xffffffff) >> 0)
12102 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_SET(value) (((value) << 0) & 0xffffffff)
12104 #ifndef __ASSEMBLY__
12115 struct ALT_SYSMGR_ROM_WARMRAM_EN_s
12117 uint32_t magic : 32;
12121 typedef volatile struct ALT_SYSMGR_ROM_WARMRAM_EN_s ALT_SYSMGR_ROM_WARMRAM_EN_t;
12125 #define ALT_SYSMGR_ROM_WARMRAM_EN_RESET 0x00000000
12127 #define ALT_SYSMGR_ROM_WARMRAM_EN_OFST 0x18
12155 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_LSB 0
12157 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_MSB 31
12159 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_WIDTH 32
12161 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_SET_MSK 0xffffffff
12163 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_CLR_MSK 0x00000000
12165 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_RESET 0x0
12167 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_GET(value) (((value) & 0xffffffff) >> 0)
12169 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_SET(value) (((value) << 0) & 0xffffffff)
12171 #ifndef __ASSEMBLY__
12182 struct ALT_SYSMGR_ROM_WARMRAM_DATASTART_s
12184 uint32_t offset : 32;
12188 typedef volatile struct ALT_SYSMGR_ROM_WARMRAM_DATASTART_s ALT_SYSMGR_ROM_WARMRAM_DATASTART_t;
12192 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_RESET 0x00000000
12194 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFST 0x1c
12230 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_LSB 0
12232 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_MSB 31
12234 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_WIDTH 32
12236 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_SET_MSK 0xffffffff
12238 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_CLR_MSK 0x00000000
12240 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_RESET 0x0
12242 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_GET(value) (((value) & 0xffffffff) >> 0)
12244 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_SET(value) (((value) << 0) & 0xffffffff)
12246 #ifndef __ASSEMBLY__
12257 struct ALT_SYSMGR_ROM_WARMRAM_LEN_s
12259 uint32_t size : 32;
12263 typedef volatile struct ALT_SYSMGR_ROM_WARMRAM_LEN_s ALT_SYSMGR_ROM_WARMRAM_LEN_t;
12267 #define ALT_SYSMGR_ROM_WARMRAM_LEN_RESET 0x00000000
12269 #define ALT_SYSMGR_ROM_WARMRAM_LEN_OFST 0x20
12297 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_LSB 0
12299 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_MSB 31
12301 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_WIDTH 32
12303 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_SET_MSK 0xffffffff
12305 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_CLR_MSK 0x00000000
12307 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_RESET 0x0
12309 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_GET(value) (((value) & 0xffffffff) >> 0)
12311 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_SET(value) (((value) << 0) & 0xffffffff)
12313 #ifndef __ASSEMBLY__
12324 struct ALT_SYSMGR_ROM_WARMRAM_EXECUTION_s
12326 uint32_t offset : 32;
12330 typedef volatile struct ALT_SYSMGR_ROM_WARMRAM_EXECUTION_s ALT_SYSMGR_ROM_WARMRAM_EXECUTION_t;
12334 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_RESET 0x00000000
12336 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFST 0x24
12376 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_LSB 0
12378 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_MSB 31
12380 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_WIDTH 32
12382 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_SET_MSK 0xffffffff
12384 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_CLR_MSK 0x00000000
12386 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_RESET 0x0
12388 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_GET(value) (((value) & 0xffffffff) >> 0)
12390 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_SET(value) (((value) << 0) & 0xffffffff)
12392 #ifndef __ASSEMBLY__
12403 struct ALT_SYSMGR_ROM_WARMRAM_CRC_s
12405 uint32_t expected : 32;
12409 typedef volatile struct ALT_SYSMGR_ROM_WARMRAM_CRC_s ALT_SYSMGR_ROM_WARMRAM_CRC_t;
12413 #define ALT_SYSMGR_ROM_WARMRAM_CRC_RESET 0x00000000
12415 #define ALT_SYSMGR_ROM_WARMRAM_CRC_OFST 0x28
12442 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_LSB 0
12444 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_MSB 31
12446 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_WIDTH 32
12448 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_SET_MSK 0xffffffff
12450 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_CLR_MSK 0x00000000
12452 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_RESET 0x0
12454 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_GET(value) (((value) & 0xffffffff) >> 0)
12456 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_SET(value) (((value) << 0) & 0xffffffff)
12458 #ifndef __ASSEMBLY__
12469 struct ALT_SYSMGR_ROM_ISW_HANDOFF_s
12471 uint32_t isw_handoff : 32;
12475 typedef volatile struct ALT_SYSMGR_ROM_ISW_HANDOFF_s ALT_SYSMGR_ROM_ISW_HANDOFF_t;
12479 #define ALT_SYSMGR_ROM_ISW_HANDOFF_RESET 0x00000000
12481 #define ALT_SYSMGR_ROM_ISW_HANDOFF_OFST 0x30
12505 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_LSB 0
12507 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_MSB 31
12509 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_WIDTH 32
12511 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_SET_MSK 0xffffffff
12513 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_CLR_MSK 0x00000000
12515 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_RESET 0x0
12517 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
12519 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_SET(value) (((value) << 0) & 0xffffffff)
12521 #ifndef __ASSEMBLY__
12532 struct ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_s
12534 uint32_t value : 32;
12538 typedef volatile struct ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_s ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_t;
12542 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_RESET 0x00000000
12544 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_OFST 0x50
12569 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_LSB 0
12571 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_MSB 31
12573 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_WIDTH 32
12575 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_SET_MSK 0xffffffff
12577 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_CLR_MSK 0x00000000
12579 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_RESET 0x0
12581 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
12583 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_SET(value) (((value) << 0) & 0xffffffff)
12585 #ifndef __ASSEMBLY__
12596 struct ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_s
12598 uint32_t value : 32;
12602 typedef volatile struct ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_s ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_t;
12606 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_RESET 0x00000000
12608 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_OFST 0x70
12633 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_LSB 0
12635 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_MSB 31
12637 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_WIDTH 32
12639 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_SET_MSK 0xffffffff
12641 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_CLR_MSK 0x00000000
12643 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_RESET 0x0
12645 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
12647 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_SET(value) (((value) << 0) & 0xffffffff)
12649 #ifndef __ASSEMBLY__
12660 struct ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_s
12662 uint32_t value : 32;
12666 typedef volatile struct ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_s ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_t;
12670 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_RESET 0x00000000
12672 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_OFST 0x74
12674 #ifndef __ASSEMBLY__
12685 struct ALT_SYSMGR_ROM_s
12687 ALT_SYSMGR_ROM_ROMHW_CTL_t romhw_ctrl;
12688 ALT_SYSMGR_ROM_ROMCODE_CTL_t romcode_ctrl;
12689 ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_t romcode_qspi_reset_command;
12690 ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_t romcode_initswstate;
12691 ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_t romcode_initswlastld;
12692 volatile uint32_t _pad_0x14_0x17;
12693 ALT_SYSMGR_ROM_WARMRAM_EN_t warmram_enable;
12694 ALT_SYSMGR_ROM_WARMRAM_DATASTART_t warmram_datastart;
12695 ALT_SYSMGR_ROM_WARMRAM_LEN_t warmram_length;
12696 ALT_SYSMGR_ROM_WARMRAM_EXECUTION_t warmram_execution;
12697 ALT_SYSMGR_ROM_WARMRAM_CRC_t warmram_crc;
12698 volatile uint32_t _pad_0x2c_0x2f;
12699 ALT_SYSMGR_ROM_ISW_HANDOFF_t isw_handoff[8];
12700 ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_t romcode_bootromswstate[8];
12701 ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_t romcode_stickyset_warmclr;
12702 ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_t romcode_stickyset_coldclr;
12703 volatile uint32_t _pad_0x78_0x100[34];
12707 typedef volatile struct ALT_SYSMGR_ROM_s ALT_SYSMGR_ROM_t;
12709 struct ALT_SYSMGR_ROM_raw_s
12711 volatile uint32_t romhw_ctrl;
12712 volatile uint32_t romcode_ctrl;
12713 volatile uint32_t romcode_qspi_reset_command;
12714 volatile uint32_t romcode_initswstate;
12715 volatile uint32_t romcode_initswlastld;
12716 uint32_t _pad_0x14_0x17;
12717 volatile uint32_t warmram_enable;
12718 volatile uint32_t warmram_datastart;
12719 volatile uint32_t warmram_length;
12720 volatile uint32_t warmram_execution;
12721 volatile uint32_t warmram_crc;
12722 uint32_t _pad_0x2c_0x2f;
12723 volatile uint32_t isw_handoff[8];
12724 volatile uint32_t romcode_bootromswstate[8];
12725 volatile uint32_t romcode_stickyset_warmclr;
12726 volatile uint32_t romcode_stickyset_coldclr;
12727 uint32_t _pad_0x78_0x100[34];
12731 typedef volatile struct ALT_SYSMGR_ROM_raw_s ALT_SYSMGR_ROM_raw_t;