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alt_noc_mpu_emac0.h
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32 
33 /* Altera - ALT_NOC_MPU_EMAC0_M_QOS */
34 
35 #ifndef __ALT_SOCAL_NOC_MPU_EMAC0_H__
36 #define __ALT_SOCAL_NOC_MPU_EMAC0_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_NOC_MPU_EMAC0_M_QOS
50  *
51  */
52 /*
53  * Register : emac0_m_I_main_QosGenerator_Id_CoreId
54  *
55  * Register Layout
56  *
57  * Bits | Access | Reset | Description
58  * :-------|:-------|:---------|:----------------------------------------
59  * [7:0] | R | 0x4 | ALT_NOC_MPU_EMAC0_M_QOS_COREID_TYPEID
60  * [31:8] | R | 0x7d4821 | ALT_NOC_MPU_EMAC0_M_QOS_COREID_CHECKSUM
61  *
62  */
63 /*
64  * Field : CORETYPEID
65  *
66  * Field identifying the type of IP.
67  *
68  * Field Access Macros:
69  *
70  */
71 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_COREID_TYPEID register field. */
72 #define ALT_NOC_MPU_EMAC0_M_QOS_COREID_TYPEID_LSB 0
73 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_COREID_TYPEID register field. */
74 #define ALT_NOC_MPU_EMAC0_M_QOS_COREID_TYPEID_MSB 7
75 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_QOS_COREID_TYPEID register field. */
76 #define ALT_NOC_MPU_EMAC0_M_QOS_COREID_TYPEID_WIDTH 8
77 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_QOS_COREID_TYPEID register field value. */
78 #define ALT_NOC_MPU_EMAC0_M_QOS_COREID_TYPEID_SET_MSK 0x000000ff
79 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_QOS_COREID_TYPEID register field value. */
80 #define ALT_NOC_MPU_EMAC0_M_QOS_COREID_TYPEID_CLR_MSK 0xffffff00
81 /* The reset value of the ALT_NOC_MPU_EMAC0_M_QOS_COREID_TYPEID register field. */
82 #define ALT_NOC_MPU_EMAC0_M_QOS_COREID_TYPEID_RESET 0x4
83 /* Extracts the ALT_NOC_MPU_EMAC0_M_QOS_COREID_TYPEID field value from a register. */
84 #define ALT_NOC_MPU_EMAC0_M_QOS_COREID_TYPEID_GET(value) (((value) & 0x000000ff) >> 0)
85 /* Produces a ALT_NOC_MPU_EMAC0_M_QOS_COREID_TYPEID register field value suitable for setting the register. */
86 #define ALT_NOC_MPU_EMAC0_M_QOS_COREID_TYPEID_SET(value) (((value) << 0) & 0x000000ff)
87 
88 /*
89  * Field : CORECHECKSUM
90  *
91  * Field containing a checksum of the parameters of the IP.
92  *
93  * Field Access Macros:
94  *
95  */
96 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_COREID_CHECKSUM register field. */
97 #define ALT_NOC_MPU_EMAC0_M_QOS_COREID_CHECKSUM_LSB 8
98 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_COREID_CHECKSUM register field. */
99 #define ALT_NOC_MPU_EMAC0_M_QOS_COREID_CHECKSUM_MSB 31
100 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_QOS_COREID_CHECKSUM register field. */
101 #define ALT_NOC_MPU_EMAC0_M_QOS_COREID_CHECKSUM_WIDTH 24
102 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_QOS_COREID_CHECKSUM register field value. */
103 #define ALT_NOC_MPU_EMAC0_M_QOS_COREID_CHECKSUM_SET_MSK 0xffffff00
104 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_QOS_COREID_CHECKSUM register field value. */
105 #define ALT_NOC_MPU_EMAC0_M_QOS_COREID_CHECKSUM_CLR_MSK 0x000000ff
106 /* The reset value of the ALT_NOC_MPU_EMAC0_M_QOS_COREID_CHECKSUM register field. */
107 #define ALT_NOC_MPU_EMAC0_M_QOS_COREID_CHECKSUM_RESET 0x7d4821
108 /* Extracts the ALT_NOC_MPU_EMAC0_M_QOS_COREID_CHECKSUM field value from a register. */
109 #define ALT_NOC_MPU_EMAC0_M_QOS_COREID_CHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
110 /* Produces a ALT_NOC_MPU_EMAC0_M_QOS_COREID_CHECKSUM register field value suitable for setting the register. */
111 #define ALT_NOC_MPU_EMAC0_M_QOS_COREID_CHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
112 
113 #ifndef __ASSEMBLY__
114 /*
115  * WARNING: The C register and register group struct declarations are provided for
116  * convenience and illustrative purposes. They should, however, be used with
117  * caution as the C language standard provides no guarantees about the alignment or
118  * atomicity of device memory accesses. The recommended practice for writing
119  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
120  * alt_write_word() functions.
121  *
122  * The struct declaration for register ALT_NOC_MPU_EMAC0_M_QOS_COREID.
123  */
124 struct ALT_NOC_MPU_EMAC0_M_QOS_COREID_s
125 {
126  const uint32_t CORETYPEID : 8; /* ALT_NOC_MPU_EMAC0_M_QOS_COREID_TYPEID */
127  const uint32_t CORECHECKSUM : 24; /* ALT_NOC_MPU_EMAC0_M_QOS_COREID_CHECKSUM */
128 };
129 
130 /* The typedef declaration for register ALT_NOC_MPU_EMAC0_M_QOS_COREID. */
131 typedef volatile struct ALT_NOC_MPU_EMAC0_M_QOS_COREID_s ALT_NOC_MPU_EMAC0_M_QOS_COREID_t;
132 #endif /* __ASSEMBLY__ */
133 
134 /* The reset value of the ALT_NOC_MPU_EMAC0_M_QOS_COREID register. */
135 #define ALT_NOC_MPU_EMAC0_M_QOS_COREID_RESET 0x7d482104
136 /* The byte offset of the ALT_NOC_MPU_EMAC0_M_QOS_COREID register from the beginning of the component. */
137 #define ALT_NOC_MPU_EMAC0_M_QOS_COREID_OFST 0x0
138 
139 /*
140  * Register : emac0_m_I_main_QosGenerator_Id_RevisionId
141  *
142  * Register Layout
143  *
144  * Bits | Access | Reset | Description
145  * :-------|:-------|:--------|:----------------------------------------
146  * [7:0] | R | 0x0 | ALT_NOC_MPU_EMAC0_M_QOS_REVID_UID
147  * [31:8] | R | 0x129ff | ALT_NOC_MPU_EMAC0_M_QOS_REVID_FLEXNOCID
148  *
149  */
150 /*
151  * Field : USERID
152  *
153  * Field containing a user defined value, not used anywhere inside the IP itself.
154  *
155  * Field Access Macros:
156  *
157  */
158 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_REVID_UID register field. */
159 #define ALT_NOC_MPU_EMAC0_M_QOS_REVID_UID_LSB 0
160 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_REVID_UID register field. */
161 #define ALT_NOC_MPU_EMAC0_M_QOS_REVID_UID_MSB 7
162 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_QOS_REVID_UID register field. */
163 #define ALT_NOC_MPU_EMAC0_M_QOS_REVID_UID_WIDTH 8
164 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_QOS_REVID_UID register field value. */
165 #define ALT_NOC_MPU_EMAC0_M_QOS_REVID_UID_SET_MSK 0x000000ff
166 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_QOS_REVID_UID register field value. */
167 #define ALT_NOC_MPU_EMAC0_M_QOS_REVID_UID_CLR_MSK 0xffffff00
168 /* The reset value of the ALT_NOC_MPU_EMAC0_M_QOS_REVID_UID register field. */
169 #define ALT_NOC_MPU_EMAC0_M_QOS_REVID_UID_RESET 0x0
170 /* Extracts the ALT_NOC_MPU_EMAC0_M_QOS_REVID_UID field value from a register. */
171 #define ALT_NOC_MPU_EMAC0_M_QOS_REVID_UID_GET(value) (((value) & 0x000000ff) >> 0)
172 /* Produces a ALT_NOC_MPU_EMAC0_M_QOS_REVID_UID register field value suitable for setting the register. */
173 #define ALT_NOC_MPU_EMAC0_M_QOS_REVID_UID_SET(value) (((value) << 0) & 0x000000ff)
174 
175 /*
176  * Field : FLEXNOCID
177  *
178  * Field containing the build revision of the software used to generate the IP HDL
179  * code.
180  *
181  * Field Access Macros:
182  *
183  */
184 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_REVID_FLEXNOCID register field. */
185 #define ALT_NOC_MPU_EMAC0_M_QOS_REVID_FLEXNOCID_LSB 8
186 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_REVID_FLEXNOCID register field. */
187 #define ALT_NOC_MPU_EMAC0_M_QOS_REVID_FLEXNOCID_MSB 31
188 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_QOS_REVID_FLEXNOCID register field. */
189 #define ALT_NOC_MPU_EMAC0_M_QOS_REVID_FLEXNOCID_WIDTH 24
190 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_QOS_REVID_FLEXNOCID register field value. */
191 #define ALT_NOC_MPU_EMAC0_M_QOS_REVID_FLEXNOCID_SET_MSK 0xffffff00
192 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_QOS_REVID_FLEXNOCID register field value. */
193 #define ALT_NOC_MPU_EMAC0_M_QOS_REVID_FLEXNOCID_CLR_MSK 0x000000ff
194 /* The reset value of the ALT_NOC_MPU_EMAC0_M_QOS_REVID_FLEXNOCID register field. */
195 #define ALT_NOC_MPU_EMAC0_M_QOS_REVID_FLEXNOCID_RESET 0x129ff
196 /* Extracts the ALT_NOC_MPU_EMAC0_M_QOS_REVID_FLEXNOCID field value from a register. */
197 #define ALT_NOC_MPU_EMAC0_M_QOS_REVID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
198 /* Produces a ALT_NOC_MPU_EMAC0_M_QOS_REVID_FLEXNOCID register field value suitable for setting the register. */
199 #define ALT_NOC_MPU_EMAC0_M_QOS_REVID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
200 
201 #ifndef __ASSEMBLY__
202 /*
203  * WARNING: The C register and register group struct declarations are provided for
204  * convenience and illustrative purposes. They should, however, be used with
205  * caution as the C language standard provides no guarantees about the alignment or
206  * atomicity of device memory accesses. The recommended practice for writing
207  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
208  * alt_write_word() functions.
209  *
210  * The struct declaration for register ALT_NOC_MPU_EMAC0_M_QOS_REVID.
211  */
212 struct ALT_NOC_MPU_EMAC0_M_QOS_REVID_s
213 {
214  const uint32_t USERID : 8; /* ALT_NOC_MPU_EMAC0_M_QOS_REVID_UID */
215  const uint32_t FLEXNOCID : 24; /* ALT_NOC_MPU_EMAC0_M_QOS_REVID_FLEXNOCID */
216 };
217 
218 /* The typedef declaration for register ALT_NOC_MPU_EMAC0_M_QOS_REVID. */
219 typedef volatile struct ALT_NOC_MPU_EMAC0_M_QOS_REVID_s ALT_NOC_MPU_EMAC0_M_QOS_REVID_t;
220 #endif /* __ASSEMBLY__ */
221 
222 /* The reset value of the ALT_NOC_MPU_EMAC0_M_QOS_REVID register. */
223 #define ALT_NOC_MPU_EMAC0_M_QOS_REVID_RESET 0x0129ff00
224 /* The byte offset of the ALT_NOC_MPU_EMAC0_M_QOS_REVID register from the beginning of the component. */
225 #define ALT_NOC_MPU_EMAC0_M_QOS_REVID_OFST 0x4
226 
227 /*
228  * Register : emac0_m_I_main_QosGenerator_Priority
229  *
230  * Priority register.
231  *
232  * Register Layout
233  *
234  * Bits | Access | Reset | Description
235  * :--------|:-------|:--------|:---------------------------------
236  * [1:0] | RW | 0x0 | ALT_NOC_MPU_EMAC0_M_QOS_PRI_P0
237  * [7:2] | ??? | Unknown | *UNDEFINED*
238  * [9:8] | RW | 0x1 | ALT_NOC_MPU_EMAC0_M_QOS_PRI_P1
239  * [30:10] | ??? | Unknown | *UNDEFINED*
240  * [31] | R | 0x1 | ALT_NOC_MPU_EMAC0_M_QOS_PRI_MARK
241  *
242  */
243 /*
244  * Field : P0
245  *
246  * In Programmable or Bandwidth Limiter mode, the priority level for write
247  * transactions. In Bandwidth Regulator mode, the priority level when the used
248  * throughput is above the threshold. In Bandwidth Regulator mode, P0 should have a
249  * value equal or lower than P1.
250  *
251  * Field Access Macros:
252  *
253  */
254 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_PRI_P0 register field. */
255 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_P0_LSB 0
256 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_PRI_P0 register field. */
257 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_P0_MSB 1
258 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_QOS_PRI_P0 register field. */
259 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_P0_WIDTH 2
260 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_QOS_PRI_P0 register field value. */
261 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_P0_SET_MSK 0x00000003
262 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_QOS_PRI_P0 register field value. */
263 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_P0_CLR_MSK 0xfffffffc
264 /* The reset value of the ALT_NOC_MPU_EMAC0_M_QOS_PRI_P0 register field. */
265 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_P0_RESET 0x0
266 /* Extracts the ALT_NOC_MPU_EMAC0_M_QOS_PRI_P0 field value from a register. */
267 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_P0_GET(value) (((value) & 0x00000003) >> 0)
268 /* Produces a ALT_NOC_MPU_EMAC0_M_QOS_PRI_P0 register field value suitable for setting the register. */
269 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_P0_SET(value) (((value) << 0) & 0x00000003)
270 
271 /*
272  * Field : P1
273  *
274  * In Programmable or Bandwidth Limiter mode, the priority level for read
275  * transactions. In Bandwidth regulator mode, the priority level when the used
276  * throughput is below the threshold. In Bandwidth Regulator mode, P1 should have a
277  * value equal or greater than P0.
278  *
279  * Field Access Macros:
280  *
281  */
282 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_PRI_P1 register field. */
283 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_P1_LSB 8
284 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_PRI_P1 register field. */
285 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_P1_MSB 9
286 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_QOS_PRI_P1 register field. */
287 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_P1_WIDTH 2
288 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_QOS_PRI_P1 register field value. */
289 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_P1_SET_MSK 0x00000300
290 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_QOS_PRI_P1 register field value. */
291 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_P1_CLR_MSK 0xfffffcff
292 /* The reset value of the ALT_NOC_MPU_EMAC0_M_QOS_PRI_P1 register field. */
293 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_P1_RESET 0x1
294 /* Extracts the ALT_NOC_MPU_EMAC0_M_QOS_PRI_P1 field value from a register. */
295 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_P1_GET(value) (((value) & 0x00000300) >> 8)
296 /* Produces a ALT_NOC_MPU_EMAC0_M_QOS_PRI_P1 register field value suitable for setting the register. */
297 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_P1_SET(value) (((value) << 8) & 0x00000300)
298 
299 /*
300  * Field : MARK
301  *
302  * Backward compatibility marker when 0.
303  *
304  * Field Access Macros:
305  *
306  */
307 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_PRI_MARK register field. */
308 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_MARK_LSB 31
309 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_PRI_MARK register field. */
310 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_MARK_MSB 31
311 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_QOS_PRI_MARK register field. */
312 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_MARK_WIDTH 1
313 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_QOS_PRI_MARK register field value. */
314 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_MARK_SET_MSK 0x80000000
315 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_QOS_PRI_MARK register field value. */
316 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_MARK_CLR_MSK 0x7fffffff
317 /* The reset value of the ALT_NOC_MPU_EMAC0_M_QOS_PRI_MARK register field. */
318 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_MARK_RESET 0x1
319 /* Extracts the ALT_NOC_MPU_EMAC0_M_QOS_PRI_MARK field value from a register. */
320 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_MARK_GET(value) (((value) & 0x80000000) >> 31)
321 /* Produces a ALT_NOC_MPU_EMAC0_M_QOS_PRI_MARK register field value suitable for setting the register. */
322 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_MARK_SET(value) (((value) << 31) & 0x80000000)
323 
324 #ifndef __ASSEMBLY__
325 /*
326  * WARNING: The C register and register group struct declarations are provided for
327  * convenience and illustrative purposes. They should, however, be used with
328  * caution as the C language standard provides no guarantees about the alignment or
329  * atomicity of device memory accesses. The recommended practice for writing
330  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
331  * alt_write_word() functions.
332  *
333  * The struct declaration for register ALT_NOC_MPU_EMAC0_M_QOS_PRI.
334  */
335 struct ALT_NOC_MPU_EMAC0_M_QOS_PRI_s
336 {
337  uint32_t P0 : 2; /* ALT_NOC_MPU_EMAC0_M_QOS_PRI_P0 */
338  uint32_t : 6; /* *UNDEFINED* */
339  uint32_t P1 : 2; /* ALT_NOC_MPU_EMAC0_M_QOS_PRI_P1 */
340  uint32_t : 21; /* *UNDEFINED* */
341  const uint32_t MARK : 1; /* ALT_NOC_MPU_EMAC0_M_QOS_PRI_MARK */
342 };
343 
344 /* The typedef declaration for register ALT_NOC_MPU_EMAC0_M_QOS_PRI. */
345 typedef volatile struct ALT_NOC_MPU_EMAC0_M_QOS_PRI_s ALT_NOC_MPU_EMAC0_M_QOS_PRI_t;
346 #endif /* __ASSEMBLY__ */
347 
348 /* The reset value of the ALT_NOC_MPU_EMAC0_M_QOS_PRI register. */
349 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_RESET 0x80000100
350 /* The byte offset of the ALT_NOC_MPU_EMAC0_M_QOS_PRI register from the beginning of the component. */
351 #define ALT_NOC_MPU_EMAC0_M_QOS_PRI_OFST 0x8
352 
353 /*
354  * Register : emac0_m_I_main_QosGenerator_Mode
355  *
356  *
357  * Register Layout
358  *
359  * Bits | Access | Reset | Description
360  * :-------|:-------|:--------|:--------------------------------
361  * [1:0] | RW | 0x3 | ALT_NOC_MPU_EMAC0_M_QOS_MOD_MOD
362  * [31:2] | ??? | Unknown | *UNDEFINED*
363  *
364  */
365 /*
366  * Field : MODE
367  *
368  * 0 = Programmable mode: a programmed priority is assigned to each read or write,
369  * 1 = Bandwidth Limiter Mode: a hard limit restricts throughput, 2 = Bypass mode:
370  * (<See SoC-specific QoS generator documentation>), 3 = Bandwidth Regulator mode:
371  * priority decreases when throughput exceeds a threshold.
372  *
373  * Field Access Macros:
374  *
375  */
376 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_MOD_MOD register field. */
377 #define ALT_NOC_MPU_EMAC0_M_QOS_MOD_MOD_LSB 0
378 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_MOD_MOD register field. */
379 #define ALT_NOC_MPU_EMAC0_M_QOS_MOD_MOD_MSB 1
380 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_QOS_MOD_MOD register field. */
381 #define ALT_NOC_MPU_EMAC0_M_QOS_MOD_MOD_WIDTH 2
382 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_QOS_MOD_MOD register field value. */
383 #define ALT_NOC_MPU_EMAC0_M_QOS_MOD_MOD_SET_MSK 0x00000003
384 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_QOS_MOD_MOD register field value. */
385 #define ALT_NOC_MPU_EMAC0_M_QOS_MOD_MOD_CLR_MSK 0xfffffffc
386 /* The reset value of the ALT_NOC_MPU_EMAC0_M_QOS_MOD_MOD register field. */
387 #define ALT_NOC_MPU_EMAC0_M_QOS_MOD_MOD_RESET 0x3
388 /* Extracts the ALT_NOC_MPU_EMAC0_M_QOS_MOD_MOD field value from a register. */
389 #define ALT_NOC_MPU_EMAC0_M_QOS_MOD_MOD_GET(value) (((value) & 0x00000003) >> 0)
390 /* Produces a ALT_NOC_MPU_EMAC0_M_QOS_MOD_MOD register field value suitable for setting the register. */
391 #define ALT_NOC_MPU_EMAC0_M_QOS_MOD_MOD_SET(value) (((value) << 0) & 0x00000003)
392 
393 #ifndef __ASSEMBLY__
394 /*
395  * WARNING: The C register and register group struct declarations are provided for
396  * convenience and illustrative purposes. They should, however, be used with
397  * caution as the C language standard provides no guarantees about the alignment or
398  * atomicity of device memory accesses. The recommended practice for writing
399  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
400  * alt_write_word() functions.
401  *
402  * The struct declaration for register ALT_NOC_MPU_EMAC0_M_QOS_MOD.
403  */
404 struct ALT_NOC_MPU_EMAC0_M_QOS_MOD_s
405 {
406  uint32_t MODE : 2; /* ALT_NOC_MPU_EMAC0_M_QOS_MOD_MOD */
407  uint32_t : 30; /* *UNDEFINED* */
408 };
409 
410 /* The typedef declaration for register ALT_NOC_MPU_EMAC0_M_QOS_MOD. */
411 typedef volatile struct ALT_NOC_MPU_EMAC0_M_QOS_MOD_s ALT_NOC_MPU_EMAC0_M_QOS_MOD_t;
412 #endif /* __ASSEMBLY__ */
413 
414 /* The reset value of the ALT_NOC_MPU_EMAC0_M_QOS_MOD register. */
415 #define ALT_NOC_MPU_EMAC0_M_QOS_MOD_RESET 0x00000003
416 /* The byte offset of the ALT_NOC_MPU_EMAC0_M_QOS_MOD register from the beginning of the component. */
417 #define ALT_NOC_MPU_EMAC0_M_QOS_MOD_OFST 0xc
418 
419 /*
420  * Register : emac0_m_I_main_QosGenerator_Bandwidth
421  *
422  *
423  * Register Layout
424  *
425  * Bits | Access | Reset | Description
426  * :--------|:-------|:--------|:----------------------------------------
427  * [10:0] | RW | 0x100 | ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_BANDWIDTH
428  * [31:11] | ??? | Unknown | *UNDEFINED*
429  *
430  */
431 /*
432  * Field : BANDWIDTH
433  *
434  * In Bandwidth Limiter or Bandwidth Regulator mode, the bandwidth threshold in
435  * units of 1/256th bytes per cycle. For example, 80 MBps on a 250 MHz interface is
436  * value 0x0052.
437  *
438  * Field Access Macros:
439  *
440  */
441 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_BANDWIDTH register field. */
442 #define ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_BANDWIDTH_LSB 0
443 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_BANDWIDTH register field. */
444 #define ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_BANDWIDTH_MSB 10
445 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_BANDWIDTH register field. */
446 #define ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_BANDWIDTH_WIDTH 11
447 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_BANDWIDTH register field value. */
448 #define ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_BANDWIDTH_SET_MSK 0x000007ff
449 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_BANDWIDTH register field value. */
450 #define ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_BANDWIDTH_CLR_MSK 0xfffff800
451 /* The reset value of the ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_BANDWIDTH register field. */
452 #define ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_BANDWIDTH_RESET 0x100
453 /* Extracts the ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_BANDWIDTH field value from a register. */
454 #define ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_BANDWIDTH_GET(value) (((value) & 0x000007ff) >> 0)
455 /* Produces a ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_BANDWIDTH register field value suitable for setting the register. */
456 #define ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x000007ff)
457 
458 #ifndef __ASSEMBLY__
459 /*
460  * WARNING: The C register and register group struct declarations are provided for
461  * convenience and illustrative purposes. They should, however, be used with
462  * caution as the C language standard provides no guarantees about the alignment or
463  * atomicity of device memory accesses. The recommended practice for writing
464  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
465  * alt_write_word() functions.
466  *
467  * The struct declaration for register ALT_NOC_MPU_EMAC0_M_QOS_BWDTH.
468  */
469 struct ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_s
470 {
471  uint32_t BANDWIDTH : 11; /* ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_BANDWIDTH */
472  uint32_t : 21; /* *UNDEFINED* */
473 };
474 
475 /* The typedef declaration for register ALT_NOC_MPU_EMAC0_M_QOS_BWDTH. */
476 typedef volatile struct ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_s ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_t;
477 #endif /* __ASSEMBLY__ */
478 
479 /* The reset value of the ALT_NOC_MPU_EMAC0_M_QOS_BWDTH register. */
480 #define ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_RESET 0x00000100
481 /* The byte offset of the ALT_NOC_MPU_EMAC0_M_QOS_BWDTH register from the beginning of the component. */
482 #define ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_OFST 0x10
483 
484 /*
485  * Register : emac0_m_I_main_QosGenerator_Saturation
486  *
487  *
488  * Register Layout
489  *
490  * Bits | Access | Reset | Description
491  * :--------|:-------|:--------|:---------------------------------------
492  * [9:0] | RW | 0x4 | ALT_NOC_MPU_EMAC0_M_QOS_SAT_SATURATION
493  * [31:10] | ??? | Unknown | *UNDEFINED*
494  *
495  */
496 /*
497  * Field : SATURATION
498  *
499  * In Bandwidth Limiter or Bandwidth Regulator mode, the maximum data count value,
500  * in units of 16 bytes. This determines the window of time over which bandwidth is
501  * measured. For example, to measure bandwidth within a 1000 cycle window on a
502  * 64-bit interface is value 0x1F4.
503  *
504  * Field Access Macros:
505  *
506  */
507 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_SAT_SATURATION register field. */
508 #define ALT_NOC_MPU_EMAC0_M_QOS_SAT_SATURATION_LSB 0
509 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_SAT_SATURATION register field. */
510 #define ALT_NOC_MPU_EMAC0_M_QOS_SAT_SATURATION_MSB 9
511 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_QOS_SAT_SATURATION register field. */
512 #define ALT_NOC_MPU_EMAC0_M_QOS_SAT_SATURATION_WIDTH 10
513 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_QOS_SAT_SATURATION register field value. */
514 #define ALT_NOC_MPU_EMAC0_M_QOS_SAT_SATURATION_SET_MSK 0x000003ff
515 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_QOS_SAT_SATURATION register field value. */
516 #define ALT_NOC_MPU_EMAC0_M_QOS_SAT_SATURATION_CLR_MSK 0xfffffc00
517 /* The reset value of the ALT_NOC_MPU_EMAC0_M_QOS_SAT_SATURATION register field. */
518 #define ALT_NOC_MPU_EMAC0_M_QOS_SAT_SATURATION_RESET 0x4
519 /* Extracts the ALT_NOC_MPU_EMAC0_M_QOS_SAT_SATURATION field value from a register. */
520 #define ALT_NOC_MPU_EMAC0_M_QOS_SAT_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
521 /* Produces a ALT_NOC_MPU_EMAC0_M_QOS_SAT_SATURATION register field value suitable for setting the register. */
522 #define ALT_NOC_MPU_EMAC0_M_QOS_SAT_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
523 
524 #ifndef __ASSEMBLY__
525 /*
526  * WARNING: The C register and register group struct declarations are provided for
527  * convenience and illustrative purposes. They should, however, be used with
528  * caution as the C language standard provides no guarantees about the alignment or
529  * atomicity of device memory accesses. The recommended practice for writing
530  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
531  * alt_write_word() functions.
532  *
533  * The struct declaration for register ALT_NOC_MPU_EMAC0_M_QOS_SAT.
534  */
535 struct ALT_NOC_MPU_EMAC0_M_QOS_SAT_s
536 {
537  uint32_t SATURATION : 10; /* ALT_NOC_MPU_EMAC0_M_QOS_SAT_SATURATION */
538  uint32_t : 22; /* *UNDEFINED* */
539 };
540 
541 /* The typedef declaration for register ALT_NOC_MPU_EMAC0_M_QOS_SAT. */
542 typedef volatile struct ALT_NOC_MPU_EMAC0_M_QOS_SAT_s ALT_NOC_MPU_EMAC0_M_QOS_SAT_t;
543 #endif /* __ASSEMBLY__ */
544 
545 /* The reset value of the ALT_NOC_MPU_EMAC0_M_QOS_SAT register. */
546 #define ALT_NOC_MPU_EMAC0_M_QOS_SAT_RESET 0x00000004
547 /* The byte offset of the ALT_NOC_MPU_EMAC0_M_QOS_SAT register from the beginning of the component. */
548 #define ALT_NOC_MPU_EMAC0_M_QOS_SAT_OFST 0x14
549 
550 /*
551  * Register : emac0_m_I_main_QosGenerator_ExtControl
552  *
553  * External inputs control.
554  *
555  * Register Layout
556  *
557  * Bits | Access | Reset | Description
558  * :-------|:-------|:--------|:-------------------------------------------
559  * [0] | RW | 0x0 | ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_SOCKETQOSEN
560  * [1] | RW | 0x0 | ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_EXTTHREN
561  * [2] | RW | 0x0 | ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_INTCLKEN
562  * [31:3] | ??? | Unknown | *UNDEFINED*
563  *
564  */
565 /*
566  * Field : SOCKETQOSEN
567  *
568  * n/a
569  *
570  * Field Access Macros:
571  *
572  */
573 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_SOCKETQOSEN register field. */
574 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_SOCKETQOSEN_LSB 0
575 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_SOCKETQOSEN register field. */
576 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_SOCKETQOSEN_MSB 0
577 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_SOCKETQOSEN register field. */
578 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_SOCKETQOSEN_WIDTH 1
579 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_SOCKETQOSEN register field value. */
580 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_SOCKETQOSEN_SET_MSK 0x00000001
581 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_SOCKETQOSEN register field value. */
582 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_SOCKETQOSEN_CLR_MSK 0xfffffffe
583 /* The reset value of the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_SOCKETQOSEN register field. */
584 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_SOCKETQOSEN_RESET 0x0
585 /* Extracts the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_SOCKETQOSEN field value from a register. */
586 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
587 /* Produces a ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_SOCKETQOSEN register field value suitable for setting the register. */
588 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
589 
590 /*
591  * Field : EXTTHREN
592  *
593  * n/a
594  *
595  * Field Access Macros:
596  *
597  */
598 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_EXTTHREN register field. */
599 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_EXTTHREN_LSB 1
600 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_EXTTHREN register field. */
601 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_EXTTHREN_MSB 1
602 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_EXTTHREN register field. */
603 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_EXTTHREN_WIDTH 1
604 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_EXTTHREN register field value. */
605 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_EXTTHREN_SET_MSK 0x00000002
606 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_EXTTHREN register field value. */
607 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_EXTTHREN_CLR_MSK 0xfffffffd
608 /* The reset value of the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_EXTTHREN register field. */
609 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_EXTTHREN_RESET 0x0
610 /* Extracts the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_EXTTHREN field value from a register. */
611 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
612 /* Produces a ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_EXTTHREN register field value suitable for setting the register. */
613 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
614 
615 /*
616  * Field : INTCLKEN
617  *
618  * n/a
619  *
620  * Field Access Macros:
621  *
622  */
623 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_INTCLKEN register field. */
624 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_INTCLKEN_LSB 2
625 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_INTCLKEN register field. */
626 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_INTCLKEN_MSB 2
627 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_INTCLKEN register field. */
628 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_INTCLKEN_WIDTH 1
629 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_INTCLKEN register field value. */
630 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_INTCLKEN_SET_MSK 0x00000004
631 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_INTCLKEN register field value. */
632 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_INTCLKEN_CLR_MSK 0xfffffffb
633 /* The reset value of the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_INTCLKEN register field. */
634 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_INTCLKEN_RESET 0x0
635 /* Extracts the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_INTCLKEN field value from a register. */
636 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
637 /* Produces a ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_INTCLKEN register field value suitable for setting the register. */
638 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
639 
640 #ifndef __ASSEMBLY__
641 /*
642  * WARNING: The C register and register group struct declarations are provided for
643  * convenience and illustrative purposes. They should, however, be used with
644  * caution as the C language standard provides no guarantees about the alignment or
645  * atomicity of device memory accesses. The recommended practice for writing
646  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
647  * alt_write_word() functions.
648  *
649  * The struct declaration for register ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL.
650  */
651 struct ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_s
652 {
653  uint32_t SOCKETQOSEN : 1; /* ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_SOCKETQOSEN */
654  uint32_t EXTTHREN : 1; /* ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_EXTTHREN */
655  uint32_t INTCLKEN : 1; /* ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_INTCLKEN */
656  uint32_t : 29; /* *UNDEFINED* */
657 };
658 
659 /* The typedef declaration for register ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL. */
660 typedef volatile struct ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_s ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_t;
661 #endif /* __ASSEMBLY__ */
662 
663 /* The reset value of the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL register. */
664 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_RESET 0x00000000
665 /* The byte offset of the ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL register from the beginning of the component. */
666 #define ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_OFST 0x18
667 
668 #ifndef __ASSEMBLY__
669 /*
670  * WARNING: The C register and register group struct declarations are provided for
671  * convenience and illustrative purposes. They should, however, be used with
672  * caution as the C language standard provides no guarantees about the alignment or
673  * atomicity of device memory accesses. The recommended practice for writing
674  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
675  * alt_write_word() functions.
676  *
677  * The struct declaration for register group ALT_NOC_MPU_EMAC0_M_QOS.
678  */
679 struct ALT_NOC_MPU_EMAC0_M_QOS_s
680 {
681  ALT_NOC_MPU_EMAC0_M_QOS_COREID_t emac0_m_I_main_QosGenerator_Id_CoreId; /* ALT_NOC_MPU_EMAC0_M_QOS_COREID */
682  ALT_NOC_MPU_EMAC0_M_QOS_REVID_t emac0_m_I_main_QosGenerator_Id_RevisionId; /* ALT_NOC_MPU_EMAC0_M_QOS_REVID */
683  ALT_NOC_MPU_EMAC0_M_QOS_PRI_t emac0_m_I_main_QosGenerator_Priority; /* ALT_NOC_MPU_EMAC0_M_QOS_PRI */
684  ALT_NOC_MPU_EMAC0_M_QOS_MOD_t emac0_m_I_main_QosGenerator_Mode; /* ALT_NOC_MPU_EMAC0_M_QOS_MOD */
685  ALT_NOC_MPU_EMAC0_M_QOS_BWDTH_t emac0_m_I_main_QosGenerator_Bandwidth; /* ALT_NOC_MPU_EMAC0_M_QOS_BWDTH */
686  ALT_NOC_MPU_EMAC0_M_QOS_SAT_t emac0_m_I_main_QosGenerator_Saturation; /* ALT_NOC_MPU_EMAC0_M_QOS_SAT */
687  ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL_t emac0_m_I_main_QosGenerator_ExtControl; /* ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL */
688  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
689 };
690 
691 /* The typedef declaration for register group ALT_NOC_MPU_EMAC0_M_QOS. */
692 typedef volatile struct ALT_NOC_MPU_EMAC0_M_QOS_s ALT_NOC_MPU_EMAC0_M_QOS_t;
693 /* The struct declaration for the raw register contents of register group ALT_NOC_MPU_EMAC0_M_QOS. */
694 struct ALT_NOC_MPU_EMAC0_M_QOS_raw_s
695 {
696  volatile uint32_t emac0_m_I_main_QosGenerator_Id_CoreId; /* ALT_NOC_MPU_EMAC0_M_QOS_COREID */
697  volatile uint32_t emac0_m_I_main_QosGenerator_Id_RevisionId; /* ALT_NOC_MPU_EMAC0_M_QOS_REVID */
698  volatile uint32_t emac0_m_I_main_QosGenerator_Priority; /* ALT_NOC_MPU_EMAC0_M_QOS_PRI */
699  volatile uint32_t emac0_m_I_main_QosGenerator_Mode; /* ALT_NOC_MPU_EMAC0_M_QOS_MOD */
700  volatile uint32_t emac0_m_I_main_QosGenerator_Bandwidth; /* ALT_NOC_MPU_EMAC0_M_QOS_BWDTH */
701  volatile uint32_t emac0_m_I_main_QosGenerator_Saturation; /* ALT_NOC_MPU_EMAC0_M_QOS_SAT */
702  volatile uint32_t emac0_m_I_main_QosGenerator_ExtControl; /* ALT_NOC_MPU_EMAC0_M_QOS_EXTCTL */
703  uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
704 };
705 
706 /* The typedef declaration for the raw register contents of register group ALT_NOC_MPU_EMAC0_M_QOS. */
707 typedef volatile struct ALT_NOC_MPU_EMAC0_M_QOS_raw_s ALT_NOC_MPU_EMAC0_M_QOS_raw_t;
708 #endif /* __ASSEMBLY__ */
709 
710 
711 /*
712  * Component : ALT_NOC_MPU_EMAC0_M_XACTSTATFLT
713  *
714  */
715 /*
716  * Register : emac0_m_I_main_TransactionStatFilter_Id_CoreId
717  *
718  * Register Layout
719  *
720  * Bits | Access | Reset | Description
721  * :-------|:-------|:---------|:------------------------------------------------
722  * [7:0] | R | 0x9 | ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_TYPEID
723  * [31:8] | R | 0xc284d3 | ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_CHECKSUM
724  *
725  */
726 /*
727  * Field : CORETYPEID
728  *
729  * Field identifying the type of IP.
730  *
731  * Field Access Macros:
732  *
733  */
734 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_TYPEID register field. */
735 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_TYPEID_LSB 0
736 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_TYPEID register field. */
737 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_TYPEID_MSB 7
738 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_TYPEID register field. */
739 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_TYPEID_WIDTH 8
740 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_TYPEID register field value. */
741 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_TYPEID_SET_MSK 0x000000ff
742 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_TYPEID register field value. */
743 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_TYPEID_CLR_MSK 0xffffff00
744 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_TYPEID register field. */
745 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_TYPEID_RESET 0x9
746 /* Extracts the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_TYPEID field value from a register. */
747 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_TYPEID_GET(value) (((value) & 0x000000ff) >> 0)
748 /* Produces a ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_TYPEID register field value suitable for setting the register. */
749 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_TYPEID_SET(value) (((value) << 0) & 0x000000ff)
750 
751 /*
752  * Field : CORECHECKSUM
753  *
754  * Field containing a checksum of the parameters of the IP.
755  *
756  * Field Access Macros:
757  *
758  */
759 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_CHECKSUM register field. */
760 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_CHECKSUM_LSB 8
761 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_CHECKSUM register field. */
762 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_CHECKSUM_MSB 31
763 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_CHECKSUM register field. */
764 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_CHECKSUM_WIDTH 24
765 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_CHECKSUM register field value. */
766 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_CHECKSUM_SET_MSK 0xffffff00
767 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_CHECKSUM register field value. */
768 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_CHECKSUM_CLR_MSK 0x000000ff
769 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_CHECKSUM register field. */
770 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_CHECKSUM_RESET 0xc284d3
771 /* Extracts the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_CHECKSUM field value from a register. */
772 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_CHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
773 /* Produces a ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_CHECKSUM register field value suitable for setting the register. */
774 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_CHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
775 
776 #ifndef __ASSEMBLY__
777 /*
778  * WARNING: The C register and register group struct declarations are provided for
779  * convenience and illustrative purposes. They should, however, be used with
780  * caution as the C language standard provides no guarantees about the alignment or
781  * atomicity of device memory accesses. The recommended practice for writing
782  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
783  * alt_write_word() functions.
784  *
785  * The struct declaration for register ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID.
786  */
787 struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_s
788 {
789  const uint32_t CORETYPEID : 8; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_TYPEID */
790  const uint32_t CORECHECKSUM : 24; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_CHECKSUM */
791 };
792 
793 /* The typedef declaration for register ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID. */
794 typedef volatile struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_s ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_t;
795 #endif /* __ASSEMBLY__ */
796 
797 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID register. */
798 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_RESET 0xc284d309
799 /* The byte offset of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID register from the beginning of the component. */
800 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_OFST 0x0
801 
802 /*
803  * Register : emac0_m_I_main_TransactionStatFilter_Id_RevisionId
804  *
805  * Register Layout
806  *
807  * Bits | Access | Reset | Description
808  * :-------|:-------|:--------|:------------------------------------------------
809  * [7:0] | R | 0x0 | ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_UID
810  * [31:8] | R | 0x129ff | ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_FLEXNOCID
811  *
812  */
813 /*
814  * Field : USERID
815  *
816  * Field containing a user defined value, not used anywhere inside the IP itself.
817  *
818  * Field Access Macros:
819  *
820  */
821 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_UID register field. */
822 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_UID_LSB 0
823 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_UID register field. */
824 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_UID_MSB 7
825 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_UID register field. */
826 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_UID_WIDTH 8
827 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_UID register field value. */
828 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_UID_SET_MSK 0x000000ff
829 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_UID register field value. */
830 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_UID_CLR_MSK 0xffffff00
831 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_UID register field. */
832 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_UID_RESET 0x0
833 /* Extracts the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_UID field value from a register. */
834 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_UID_GET(value) (((value) & 0x000000ff) >> 0)
835 /* Produces a ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_UID register field value suitable for setting the register. */
836 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_UID_SET(value) (((value) << 0) & 0x000000ff)
837 
838 /*
839  * Field : FLEXNOCID
840  *
841  * Field containing the build revision of the software used to generate the IP HDL
842  * code.
843  *
844  * Field Access Macros:
845  *
846  */
847 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_FLEXNOCID register field. */
848 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_FLEXNOCID_LSB 8
849 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_FLEXNOCID register field. */
850 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_FLEXNOCID_MSB 31
851 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_FLEXNOCID register field. */
852 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_FLEXNOCID_WIDTH 24
853 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_FLEXNOCID register field value. */
854 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_FLEXNOCID_SET_MSK 0xffffff00
855 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_FLEXNOCID register field value. */
856 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_FLEXNOCID_CLR_MSK 0x000000ff
857 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_FLEXNOCID register field. */
858 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_FLEXNOCID_RESET 0x129ff
859 /* Extracts the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_FLEXNOCID field value from a register. */
860 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
861 /* Produces a ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_FLEXNOCID register field value suitable for setting the register. */
862 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
863 
864 #ifndef __ASSEMBLY__
865 /*
866  * WARNING: The C register and register group struct declarations are provided for
867  * convenience and illustrative purposes. They should, however, be used with
868  * caution as the C language standard provides no guarantees about the alignment or
869  * atomicity of device memory accesses. The recommended practice for writing
870  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
871  * alt_write_word() functions.
872  *
873  * The struct declaration for register ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID.
874  */
875 struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_s
876 {
877  const uint32_t USERID : 8; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_UID */
878  const uint32_t FLEXNOCID : 24; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_FLEXNOCID */
879 };
880 
881 /* The typedef declaration for register ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID. */
882 typedef volatile struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_s ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_t;
883 #endif /* __ASSEMBLY__ */
884 
885 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID register. */
886 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_RESET 0x0129ff00
887 /* The byte offset of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID register from the beginning of the component. */
888 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_OFST 0x4
889 
890 /*
891  * Register : emac0_m_I_main_TransactionStatFilter_Mode
892  *
893  *
894  * Register Layout
895  *
896  * Bits | Access | Reset | Description
897  * :-------|:-------|:--------|:----------------------------------------
898  * [0] | RW | 0x0 | ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_MOD
899  * [31:1] | ??? | Unknown | *UNDEFINED*
900  *
901  */
902 /*
903  * Field : MODE
904  *
905  * Register Mode is a 1-bit register that sets the filtering mode as follows:
906  * handshake Mode = 0 or latency Mode = 1.
907  *
908  * Field Access Macros:
909  *
910  */
911 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_MOD register field. */
912 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_MOD_LSB 0
913 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_MOD register field. */
914 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_MOD_MSB 0
915 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_MOD register field. */
916 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_MOD_WIDTH 1
917 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_MOD register field value. */
918 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_MOD_SET_MSK 0x00000001
919 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_MOD register field value. */
920 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_MOD_CLR_MSK 0xfffffffe
921 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_MOD register field. */
922 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_MOD_RESET 0x0
923 /* Extracts the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_MOD field value from a register. */
924 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_MOD_GET(value) (((value) & 0x00000001) >> 0)
925 /* Produces a ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_MOD register field value suitable for setting the register. */
926 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_MOD_SET(value) (((value) << 0) & 0x00000001)
927 
928 #ifndef __ASSEMBLY__
929 /*
930  * WARNING: The C register and register group struct declarations are provided for
931  * convenience and illustrative purposes. They should, however, be used with
932  * caution as the C language standard provides no guarantees about the alignment or
933  * atomicity of device memory accesses. The recommended practice for writing
934  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
935  * alt_write_word() functions.
936  *
937  * The struct declaration for register ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD.
938  */
939 struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_s
940 {
941  uint32_t MODE : 1; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_MOD */
942  uint32_t : 31; /* *UNDEFINED* */
943 };
944 
945 /* The typedef declaration for register ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD. */
946 typedef volatile struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_s ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_t;
947 #endif /* __ASSEMBLY__ */
948 
949 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD register. */
950 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_RESET 0x00000000
951 /* The byte offset of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD register from the beginning of the component. */
952 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_OFST 0x8
953 
954 /*
955  * Register : emac0_m_I_main_TransactionStatFilter_AddrBase_Low
956  *
957  *
958  * Register Layout
959  *
960  * Bits | Access | Reset | Description
961  * :-------|:-------|:------|:----------------------------------------------------------
962  * [31:0] | RW | 0x0 | ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_ADDRBASE_LOW
963  *
964  */
965 /*
966  * Field : ADDRBASE_LOW
967  *
968  * Address base LSB register.
969  *
970  * Field Access Macros:
971  *
972  */
973 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_ADDRBASE_LOW register field. */
974 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_ADDRBASE_LOW_LSB 0
975 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_ADDRBASE_LOW register field. */
976 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_ADDRBASE_LOW_MSB 31
977 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_ADDRBASE_LOW register field. */
978 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_ADDRBASE_LOW_WIDTH 32
979 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_ADDRBASE_LOW register field value. */
980 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_ADDRBASE_LOW_SET_MSK 0xffffffff
981 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_ADDRBASE_LOW register field value. */
982 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_ADDRBASE_LOW_CLR_MSK 0x00000000
983 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_ADDRBASE_LOW register field. */
984 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_ADDRBASE_LOW_RESET 0x0
985 /* Extracts the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_ADDRBASE_LOW field value from a register. */
986 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
987 /* Produces a ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_ADDRBASE_LOW register field value suitable for setting the register. */
988 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
989 
990 #ifndef __ASSEMBLY__
991 /*
992  * WARNING: The C register and register group struct declarations are provided for
993  * convenience and illustrative purposes. They should, however, be used with
994  * caution as the C language standard provides no guarantees about the alignment or
995  * atomicity of device memory accesses. The recommended practice for writing
996  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
997  * alt_write_word() functions.
998  *
999  * The struct declaration for register ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW.
1000  */
1001 struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_s
1002 {
1003  uint32_t ADDRBASE_LOW : 32; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_ADDRBASE_LOW */
1004 };
1005 
1006 /* The typedef declaration for register ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW. */
1007 typedef volatile struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_s ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_t;
1008 #endif /* __ASSEMBLY__ */
1009 
1010 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW register. */
1011 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_RESET 0x00000000
1012 /* The byte offset of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW register from the beginning of the component. */
1013 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_OFST 0xc
1014 
1015 /*
1016  * Register : emac0_m_I_main_TransactionStatFilter_AddrBase_High
1017  *
1018  *
1019  * Register Layout
1020  *
1021  * Bits | Access | Reset | Description
1022  * :-------|:-------|:--------|:------------------------------------------------------------
1023  * [0] | RW | 0x0 | ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_ADDRBASE_HIGH
1024  * [31:1] | ??? | Unknown | *UNDEFINED*
1025  *
1026  */
1027 /*
1028  * Field : ADDRBASE_HIGH
1029  *
1030  * Address base MSB register.
1031  *
1032  * Field Access Macros:
1033  *
1034  */
1035 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_ADDRBASE_HIGH register field. */
1036 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_ADDRBASE_HIGH_LSB 0
1037 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_ADDRBASE_HIGH register field. */
1038 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_ADDRBASE_HIGH_MSB 0
1039 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_ADDRBASE_HIGH register field. */
1040 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_ADDRBASE_HIGH_WIDTH 1
1041 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_ADDRBASE_HIGH register field value. */
1042 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_ADDRBASE_HIGH_SET_MSK 0x00000001
1043 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_ADDRBASE_HIGH register field value. */
1044 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_ADDRBASE_HIGH_CLR_MSK 0xfffffffe
1045 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_ADDRBASE_HIGH register field. */
1046 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_ADDRBASE_HIGH_RESET 0x0
1047 /* Extracts the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_ADDRBASE_HIGH field value from a register. */
1048 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_ADDRBASE_HIGH_GET(value) (((value) & 0x00000001) >> 0)
1049 /* Produces a ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_ADDRBASE_HIGH register field value suitable for setting the register. */
1050 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_ADDRBASE_HIGH_SET(value) (((value) << 0) & 0x00000001)
1051 
1052 #ifndef __ASSEMBLY__
1053 /*
1054  * WARNING: The C register and register group struct declarations are provided for
1055  * convenience and illustrative purposes. They should, however, be used with
1056  * caution as the C language standard provides no guarantees about the alignment or
1057  * atomicity of device memory accesses. The recommended practice for writing
1058  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1059  * alt_write_word() functions.
1060  *
1061  * The struct declaration for register ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH.
1062  */
1063 struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_s
1064 {
1065  uint32_t ADDRBASE_HIGH : 1; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_ADDRBASE_HIGH */
1066  uint32_t : 31; /* *UNDEFINED* */
1067 };
1068 
1069 /* The typedef declaration for register ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH. */
1070 typedef volatile struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_s ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_t;
1071 #endif /* __ASSEMBLY__ */
1072 
1073 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH register. */
1074 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_RESET 0x00000000
1075 /* The byte offset of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH register from the beginning of the component. */
1076 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_OFST 0x10
1077 
1078 /*
1079  * Register : emac0_m_I_main_TransactionStatFilter_AddrWindowSize
1080  *
1081  *
1082  * Register Layout
1083  *
1084  * Bits | Access | Reset | Description
1085  * :-------|:-------|:--------|:--------------------------------------------------------------
1086  * [5:0] | RW | 0x0 | ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_ADDRWINDOWSIZE
1087  * [31:6] | ??? | Unknown | *UNDEFINED*
1088  *
1089  */
1090 /*
1091  * Field : ADDRWINDOWSIZE
1092  *
1093  * Register AddrWindowSize contains the encoded address mask used to filter
1094  * packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet
1095  * is a candidate when ReqInfo.Addr & AddrMask = AddrBase & AddrMask.
1096  *
1097  * Field Access Macros:
1098  *
1099  */
1100 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_ADDRWINDOWSIZE register field. */
1101 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_LSB 0
1102 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_ADDRWINDOWSIZE register field. */
1103 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MSB 5
1104 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_ADDRWINDOWSIZE register field. */
1105 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_WIDTH 6
1106 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_ADDRWINDOWSIZE register field value. */
1107 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SET_MSK 0x0000003f
1108 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_ADDRWINDOWSIZE register field value. */
1109 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_CLR_MSK 0xffffffc0
1110 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_ADDRWINDOWSIZE register field. */
1111 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_RESET 0x0
1112 /* Extracts the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_ADDRWINDOWSIZE field value from a register. */
1113 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
1114 /* Produces a ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_ADDRWINDOWSIZE register field value suitable for setting the register. */
1115 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
1116 
1117 #ifndef __ASSEMBLY__
1118 /*
1119  * WARNING: The C register and register group struct declarations are provided for
1120  * convenience and illustrative purposes. They should, however, be used with
1121  * caution as the C language standard provides no guarantees about the alignment or
1122  * atomicity of device memory accesses. The recommended practice for writing
1123  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1124  * alt_write_word() functions.
1125  *
1126  * The struct declaration for register ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE.
1127  */
1128 struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_s
1129 {
1130  uint32_t ADDRWINDOWSIZE : 6; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_ADDRWINDOWSIZE */
1131  uint32_t : 26; /* *UNDEFINED* */
1132 };
1133 
1134 /* The typedef declaration for register ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE. */
1135 typedef volatile struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_s ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_t;
1136 #endif /* __ASSEMBLY__ */
1137 
1138 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE register. */
1139 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_RESET 0x00000000
1140 /* The byte offset of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE register from the beginning of the component. */
1141 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_OFST 0x14
1142 
1143 /*
1144  * Register : emac0_m_I_main_TransactionStatFilter_Opcode
1145  *
1146  * This register selects candidate packets based on packet opcodes. (0 disables the
1147  * filter):
1148  *
1149  * Register Layout
1150  *
1151  * Bits | Access | Reset | Description
1152  * :-------|:-------|:--------|:--------------------------------------------
1153  * [0] | RW | 0x0 | ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_RDEN
1154  * [1] | RW | 0x0 | ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_WREN
1155  * [31:2] | ??? | Unknown | *UNDEFINED*
1156  *
1157  */
1158 /*
1159  * Field : RDEN
1160  *
1161  * When set to 1, selects RD requests.
1162  *
1163  * Field Access Macros:
1164  *
1165  */
1166 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_RDEN register field. */
1167 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_RDEN_LSB 0
1168 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_RDEN register field. */
1169 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_RDEN_MSB 0
1170 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_RDEN register field. */
1171 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_RDEN_WIDTH 1
1172 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_RDEN register field value. */
1173 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_RDEN_SET_MSK 0x00000001
1174 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_RDEN register field value. */
1175 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_RDEN_CLR_MSK 0xfffffffe
1176 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_RDEN register field. */
1177 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_RDEN_RESET 0x0
1178 /* Extracts the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_RDEN field value from a register. */
1179 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
1180 /* Produces a ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_RDEN register field value suitable for setting the register. */
1181 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
1182 
1183 /*
1184  * Field : WREN
1185  *
1186  * When set to 1, selects WR requests.
1187  *
1188  * Field Access Macros:
1189  *
1190  */
1191 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_WREN register field. */
1192 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_WREN_LSB 1
1193 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_WREN register field. */
1194 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_WREN_MSB 1
1195 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_WREN register field. */
1196 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_WREN_WIDTH 1
1197 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_WREN register field value. */
1198 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_WREN_SET_MSK 0x00000002
1199 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_WREN register field value. */
1200 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_WREN_CLR_MSK 0xfffffffd
1201 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_WREN register field. */
1202 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_WREN_RESET 0x0
1203 /* Extracts the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_WREN field value from a register. */
1204 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
1205 /* Produces a ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_WREN register field value suitable for setting the register. */
1206 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
1207 
1208 #ifndef __ASSEMBLY__
1209 /*
1210  * WARNING: The C register and register group struct declarations are provided for
1211  * convenience and illustrative purposes. They should, however, be used with
1212  * caution as the C language standard provides no guarantees about the alignment or
1213  * atomicity of device memory accesses. The recommended practice for writing
1214  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1215  * alt_write_word() functions.
1216  *
1217  * The struct declaration for register ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE.
1218  */
1219 struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_s
1220 {
1221  uint32_t RDEN : 1; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_RDEN */
1222  uint32_t WREN : 1; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_WREN */
1223  uint32_t : 30; /* *UNDEFINED* */
1224 };
1225 
1226 /* The typedef declaration for register ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE. */
1227 typedef volatile struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_s ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_t;
1228 #endif /* __ASSEMBLY__ */
1229 
1230 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE register. */
1231 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_RESET 0x00000000
1232 /* The byte offset of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE register from the beginning of the component. */
1233 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_OFST 0x20
1234 
1235 /*
1236  * Register : emac0_m_I_main_TransactionStatFilter_UserBase
1237  *
1238  *
1239  * Register Layout
1240  *
1241  * Bits | Access | Reset | Description
1242  * :--------|:-------|:--------|:--------------------------------------------------
1243  * [10:0] | RW | 0x0 | ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_USERBASE
1244  * [31:11] | ??? | Unknown | *UNDEFINED*
1245  *
1246  */
1247 /*
1248  * Field : USERBASE
1249  *
1250  * This register contains the User base used to filter requests.
1251  *
1252  * Field Access Macros:
1253  *
1254  */
1255 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_USERBASE register field. */
1256 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_USERBASE_LSB 0
1257 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_USERBASE register field. */
1258 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_USERBASE_MSB 10
1259 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_USERBASE register field. */
1260 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_USERBASE_WIDTH 11
1261 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_USERBASE register field value. */
1262 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_USERBASE_SET_MSK 0x000007ff
1263 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_USERBASE register field value. */
1264 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_USERBASE_CLR_MSK 0xfffff800
1265 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_USERBASE register field. */
1266 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_USERBASE_RESET 0x0
1267 /* Extracts the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_USERBASE field value from a register. */
1268 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_USERBASE_GET(value) (((value) & 0x000007ff) >> 0)
1269 /* Produces a ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_USERBASE register field value suitable for setting the register. */
1270 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_USERBASE_SET(value) (((value) << 0) & 0x000007ff)
1271 
1272 #ifndef __ASSEMBLY__
1273 /*
1274  * WARNING: The C register and register group struct declarations are provided for
1275  * convenience and illustrative purposes. They should, however, be used with
1276  * caution as the C language standard provides no guarantees about the alignment or
1277  * atomicity of device memory accesses. The recommended practice for writing
1278  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1279  * alt_write_word() functions.
1280  *
1281  * The struct declaration for register ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE.
1282  */
1283 struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_s
1284 {
1285  uint32_t USERBASE : 11; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_USERBASE */
1286  uint32_t : 21; /* *UNDEFINED* */
1287 };
1288 
1289 /* The typedef declaration for register ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE. */
1290 typedef volatile struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_s ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_t;
1291 #endif /* __ASSEMBLY__ */
1292 
1293 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE register. */
1294 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_RESET 0x00000000
1295 /* The byte offset of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE register from the beginning of the component. */
1296 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_OFST 0x24
1297 
1298 /*
1299  * Register : emac0_m_I_main_TransactionStatFilter_UserMask
1300  *
1301  *
1302  * Register Layout
1303  *
1304  * Bits | Access | Reset | Description
1305  * :--------|:-------|:--------|:------------------------------------------------
1306  * [10:0] | RW | 0x0 | ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_USERMSK
1307  * [31:11] | ??? | Unknown | *UNDEFINED*
1308  *
1309  */
1310 /*
1311  * Field : USERMASK
1312  *
1313  * This register contains the User mask used to filter requests.
1314  *
1315  * Field Access Macros:
1316  *
1317  */
1318 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_USERMSK register field. */
1319 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_USERMSK_LSB 0
1320 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_USERMSK register field. */
1321 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_USERMSK_MSB 10
1322 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_USERMSK register field. */
1323 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_USERMSK_WIDTH 11
1324 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_USERMSK register field value. */
1325 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_USERMSK_SET_MSK 0x000007ff
1326 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_USERMSK register field value. */
1327 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_USERMSK_CLR_MSK 0xfffff800
1328 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_USERMSK register field. */
1329 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_USERMSK_RESET 0x0
1330 /* Extracts the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_USERMSK field value from a register. */
1331 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_USERMSK_GET(value) (((value) & 0x000007ff) >> 0)
1332 /* Produces a ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_USERMSK register field value suitable for setting the register. */
1333 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_USERMSK_SET(value) (((value) << 0) & 0x000007ff)
1334 
1335 #ifndef __ASSEMBLY__
1336 /*
1337  * WARNING: The C register and register group struct declarations are provided for
1338  * convenience and illustrative purposes. They should, however, be used with
1339  * caution as the C language standard provides no guarantees about the alignment or
1340  * atomicity of device memory accesses. The recommended practice for writing
1341  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1342  * alt_write_word() functions.
1343  *
1344  * The struct declaration for register ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK.
1345  */
1346 struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_s
1347 {
1348  uint32_t USERMASK : 11; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_USERMSK */
1349  uint32_t : 21; /* *UNDEFINED* */
1350 };
1351 
1352 /* The typedef declaration for register ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK. */
1353 typedef volatile struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_s ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_t;
1354 #endif /* __ASSEMBLY__ */
1355 
1356 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK register. */
1357 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_RESET 0x00000000
1358 /* The byte offset of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK register from the beginning of the component. */
1359 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_OFST 0x28
1360 
1361 /*
1362  * Register : emac0_m_I_main_TransactionStatFilter_SecurityBase
1363  *
1364  *
1365  * Register Layout
1366  *
1367  * Bits | Access | Reset | Description
1368  * :-------|:-------|:--------|:----------------------------------------------------------
1369  * [2:0] | RW | 0x0 | ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_SECURITYBASE
1370  * [31:3] | ??? | Unknown | *UNDEFINED*
1371  *
1372  */
1373 /*
1374  * Field : SECURITYBASE
1375  *
1376  * This register contains the Security base used to filter requests.
1377  *
1378  * Field Access Macros:
1379  *
1380  */
1381 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_SECURITYBASE register field. */
1382 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_SECURITYBASE_LSB 0
1383 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_SECURITYBASE register field. */
1384 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_SECURITYBASE_MSB 2
1385 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_SECURITYBASE register field. */
1386 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_SECURITYBASE_WIDTH 3
1387 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_SECURITYBASE register field value. */
1388 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_SECURITYBASE_SET_MSK 0x00000007
1389 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_SECURITYBASE register field value. */
1390 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_SECURITYBASE_CLR_MSK 0xfffffff8
1391 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_SECURITYBASE register field. */
1392 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_SECURITYBASE_RESET 0x0
1393 /* Extracts the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_SECURITYBASE field value from a register. */
1394 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
1395 /* Produces a ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_SECURITYBASE register field value suitable for setting the register. */
1396 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
1397 
1398 #ifndef __ASSEMBLY__
1399 /*
1400  * WARNING: The C register and register group struct declarations are provided for
1401  * convenience and illustrative purposes. They should, however, be used with
1402  * caution as the C language standard provides no guarantees about the alignment or
1403  * atomicity of device memory accesses. The recommended practice for writing
1404  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1405  * alt_write_word() functions.
1406  *
1407  * The struct declaration for register ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE.
1408  */
1409 struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_s
1410 {
1411  uint32_t SECURITYBASE : 3; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_SECURITYBASE */
1412  uint32_t : 29; /* *UNDEFINED* */
1413 };
1414 
1415 /* The typedef declaration for register ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE. */
1416 typedef volatile struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_s ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_t;
1417 #endif /* __ASSEMBLY__ */
1418 
1419 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE register. */
1420 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_RESET 0x00000000
1421 /* The byte offset of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE register from the beginning of the component. */
1422 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_OFST 0x2c
1423 
1424 /*
1425  * Register : emac0_m_I_main_TransactionStatFilter_SecurityMask
1426  *
1427  *
1428  * Register Layout
1429  *
1430  * Bits | Access | Reset | Description
1431  * :-------|:-------|:--------|:--------------------------------------------------------
1432  * [2:0] | RW | 0x0 | ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_SECURITYMSK
1433  * [31:3] | ??? | Unknown | *UNDEFINED*
1434  *
1435  */
1436 /*
1437  * Field : SECURITYMASK
1438  *
1439  * This register contains the Security mask used to filter requests.
1440  *
1441  * Field Access Macros:
1442  *
1443  */
1444 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_SECURITYMSK register field. */
1445 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_SECURITYMSK_LSB 0
1446 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_SECURITYMSK register field. */
1447 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_SECURITYMSK_MSB 2
1448 /* The width in bits of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_SECURITYMSK register field. */
1449 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_SECURITYMSK_WIDTH 3
1450 /* The mask used to set the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_SECURITYMSK register field value. */
1451 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_SECURITYMSK_SET_MSK 0x00000007
1452 /* The mask used to clear the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_SECURITYMSK register field value. */
1453 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_SECURITYMSK_CLR_MSK 0xfffffff8
1454 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_SECURITYMSK register field. */
1455 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_SECURITYMSK_RESET 0x0
1456 /* Extracts the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_SECURITYMSK field value from a register. */
1457 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
1458 /* Produces a ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_SECURITYMSK register field value suitable for setting the register. */
1459 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
1460 
1461 #ifndef __ASSEMBLY__
1462 /*
1463  * WARNING: The C register and register group struct declarations are provided for
1464  * convenience and illustrative purposes. They should, however, be used with
1465  * caution as the C language standard provides no guarantees about the alignment or
1466  * atomicity of device memory accesses. The recommended practice for writing
1467  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1468  * alt_write_word() functions.
1469  *
1470  * The struct declaration for register ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK.
1471  */
1472 struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_s
1473 {
1474  uint32_t SECURITYMASK : 3; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_SECURITYMSK */
1475  uint32_t : 29; /* *UNDEFINED* */
1476 };
1477 
1478 /* The typedef declaration for register ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK. */
1479 typedef volatile struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_s ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_t;
1480 #endif /* __ASSEMBLY__ */
1481 
1482 /* The reset value of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK register. */
1483 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_RESET 0x00000000
1484 /* The byte offset of the ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK register from the beginning of the component. */
1485 #define ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_OFST 0x30
1486 
1487 #ifndef __ASSEMBLY__
1488 /*
1489  * WARNING: The C register and register group struct declarations are provided for
1490  * convenience and illustrative purposes. They should, however, be used with
1491  * caution as the C language standard provides no guarantees about the alignment or
1492  * atomicity of device memory accesses. The recommended practice for writing
1493  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1494  * alt_write_word() functions.
1495  *
1496  * The struct declaration for register group ALT_NOC_MPU_EMAC0_M_XACTSTATFLT.
1497  */
1498 struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_s
1499 {
1500  ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID_t emac0_m_I_main_TransactionStatFilter_Id_CoreId; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID */
1501  ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID_t emac0_m_I_main_TransactionStatFilter_Id_RevisionId; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID */
1502  ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD_t emac0_m_I_main_TransactionStatFilter_Mode; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD */
1503  ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW_t emac0_m_I_main_TransactionStatFilter_AddrBase_Low; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW */
1504  ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH_t emac0_m_I_main_TransactionStatFilter_AddrBase_High; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH */
1505  ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE_t emac0_m_I_main_TransactionStatFilter_AddrWindowSize; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE */
1506  volatile uint32_t _pad_0x18_0x1f[2]; /* *UNDEFINED* */
1507  ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE_t emac0_m_I_main_TransactionStatFilter_Opcode; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE */
1508  ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE_t emac0_m_I_main_TransactionStatFilter_UserBase; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE */
1509  ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK_t emac0_m_I_main_TransactionStatFilter_UserMask; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK */
1510  ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE_t emac0_m_I_main_TransactionStatFilter_SecurityBase; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE */
1511  ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK_t emac0_m_I_main_TransactionStatFilter_SecurityMask; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK */
1512  volatile uint32_t _pad_0x34_0x80[19]; /* *UNDEFINED* */
1513 };
1514 
1515 /* The typedef declaration for register group ALT_NOC_MPU_EMAC0_M_XACTSTATFLT. */
1516 typedef volatile struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_s ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_t;
1517 /* The struct declaration for the raw register contents of register group ALT_NOC_MPU_EMAC0_M_XACTSTATFLT. */
1518 struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_raw_s
1519 {
1520  volatile uint32_t emac0_m_I_main_TransactionStatFilter_Id_CoreId; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_COREID */
1521  volatile uint32_t emac0_m_I_main_TransactionStatFilter_Id_RevisionId; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_REVID */
1522  volatile uint32_t emac0_m_I_main_TransactionStatFilter_Mode; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_MOD */
1523  volatile uint32_t emac0_m_I_main_TransactionStatFilter_AddrBase_Low; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_LOW */
1524  volatile uint32_t emac0_m_I_main_TransactionStatFilter_AddrBase_High; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRBASE_HIGH */
1525  volatile uint32_t emac0_m_I_main_TransactionStatFilter_AddrWindowSize; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_ADDRWINDOWSIZE */
1526  uint32_t _pad_0x18_0x1f[2]; /* *UNDEFINED* */
1527  volatile uint32_t emac0_m_I_main_TransactionStatFilter_Opcode; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_OPCODE */
1528  volatile uint32_t emac0_m_I_main_TransactionStatFilter_UserBase; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERBASE */
1529  volatile uint32_t emac0_m_I_main_TransactionStatFilter_UserMask; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_USERMSK */
1530  volatile uint32_t emac0_m_I_main_TransactionStatFilter_SecurityBase; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYBASE */
1531  volatile uint32_t emac0_m_I_main_TransactionStatFilter_SecurityMask; /* ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_SECURITYMSK */
1532  uint32_t _pad_0x34_0x80[19]; /* *UNDEFINED* */
1533 };
1534 
1535 /* The typedef declaration for the raw register contents of register group ALT_NOC_MPU_EMAC0_M_XACTSTATFLT. */
1536 typedef volatile struct ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_raw_s ALT_NOC_MPU_EMAC0_M_XACTSTATFLT_raw_t;
1537 #endif /* __ASSEMBLY__ */
1538 
1539 
1540 #ifdef __cplusplus
1541 }
1542 #endif /* __cplusplus */
1543 #endif /* __ALT_SOCAL_NOC_MPU_EMAC0_H__ */
1544