35 #ifndef __ALT_SOCAL_NOC_FW_L4_PER_SCR_H__
36 #define __ALT_SOCAL_NOC_FW_L4_PER_SCR_H__
82 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_LSB 0
84 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_MSB 0
86 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_WIDTH 1
88 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_SET_MSK 0x00000001
90 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_CLR_MSK 0xfffffffe
92 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_RESET 0x0
94 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
96 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
109 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_LSB 8
111 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_MSB 8
113 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_WIDTH 1
115 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_SET_MSK 0x00000100
117 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_CLR_MSK 0xfffffeff
119 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_RESET 0x0
121 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_GET(value) (((value) & 0x00000100) >> 8)
123 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_SET(value) (((value) << 8) & 0x00000100)
136 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_LSB 16
138 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_MSB 16
140 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_WIDTH 1
142 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_SET_MSK 0x00010000
144 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_CLR_MSK 0xfffeffff
146 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_RESET 0x0
148 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
150 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
163 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_LSB 24
165 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_MSB 24
167 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_WIDTH 1
169 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_SET_MSK 0x01000000
171 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_CLR_MSK 0xfeffffff
173 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_RESET 0x0
175 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
177 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
190 struct ALT_NOC_FW_L4_PER_SCR_NAND_REG_s
196 uint32_t fpga2soc : 1;
203 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_NAND_REG_s ALT_NOC_FW_L4_PER_SCR_NAND_REG_t;
207 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_RESET 0x00000000
209 #define ALT_NOC_FW_L4_PER_SCR_NAND_REG_OFST 0x0
241 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_LSB 0
243 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_MSB 0
245 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_WIDTH 1
247 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_SET_MSK 0x00000001
249 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_CLR_MSK 0xfffffffe
251 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_RESET 0x0
253 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
255 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
268 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_LSB 8
270 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_MSB 8
272 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_WIDTH 1
274 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_SET_MSK 0x00000100
276 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_CLR_MSK 0xfffffeff
278 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_RESET 0x0
280 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_GET(value) (((value) & 0x00000100) >> 8)
282 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_SET(value) (((value) << 8) & 0x00000100)
295 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_LSB 16
297 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_MSB 16
299 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_WIDTH 1
301 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_SET_MSK 0x00010000
303 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_CLR_MSK 0xfffeffff
305 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_RESET 0x0
307 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_GET(value) (((value) & 0x00010000) >> 16)
309 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_SET(value) (((value) << 16) & 0x00010000)
322 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_LSB 24
324 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_MSB 24
326 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_WIDTH 1
328 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_SET_MSK 0x01000000
330 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_CLR_MSK 0xfeffffff
332 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_RESET 0x0
334 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
336 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
349 struct ALT_NOC_FW_L4_PER_SCR_NAND_DATA_s
355 uint32_t fpga2soc : 1;
362 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_NAND_DATA_s ALT_NOC_FW_L4_PER_SCR_NAND_DATA_t;
366 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_RESET 0x00000000
368 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_OFST 0x4
400 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_LSB 0
402 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_MSB 0
404 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_WIDTH 1
406 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_SET_MSK 0x00000001
408 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_CLR_MSK 0xfffffffe
410 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_RESET 0x0
412 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
414 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
427 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_LSB 8
429 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_MSB 8
431 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_WIDTH 1
433 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_SET_MSK 0x00000100
435 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_CLR_MSK 0xfffffeff
437 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_RESET 0x0
439 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_GET(value) (((value) & 0x00000100) >> 8)
441 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_SET(value) (((value) << 8) & 0x00000100)
454 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_LSB 16
456 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_MSB 16
458 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_WIDTH 1
460 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_SET_MSK 0x00010000
462 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_CLR_MSK 0xfffeffff
464 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_RESET 0x0
466 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_GET(value) (((value) & 0x00010000) >> 16)
468 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_SET(value) (((value) << 16) & 0x00010000)
481 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_LSB 24
483 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_MSB 24
485 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_WIDTH 1
487 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_SET_MSK 0x01000000
489 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_CLR_MSK 0xfeffffff
491 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_RESET 0x0
493 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
495 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
508 struct ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_s
514 uint32_t fpga2soc : 1;
521 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_s ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_t;
525 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_RESET 0x00000000
527 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_OFST 0x8
559 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_LSB 0
561 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_MSB 0
563 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_WIDTH 1
565 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_SET_MSK 0x00000001
567 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_CLR_MSK 0xfffffffe
569 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_RESET 0x0
571 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
573 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
586 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_LSB 8
588 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_MSB 8
590 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_WIDTH 1
592 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_SET_MSK 0x00000100
594 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_CLR_MSK 0xfffffeff
596 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_RESET 0x0
598 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_GET(value) (((value) & 0x00000100) >> 8)
600 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_SET(value) (((value) << 8) & 0x00000100)
613 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_LSB 16
615 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_MSB 16
617 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_WIDTH 1
619 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_SET_MSK 0x00010000
621 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_CLR_MSK 0xfffeffff
623 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_RESET 0x0
625 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
627 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
640 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_LSB 24
642 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_MSB 24
644 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_WIDTH 1
646 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_SET_MSK 0x01000000
648 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_CLR_MSK 0xfeffffff
650 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_RESET 0x0
652 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
654 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
667 struct ALT_NOC_FW_L4_PER_SCR_USB0_REG_s
673 uint32_t fpga2soc : 1;
680 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_USB0_REG_s ALT_NOC_FW_L4_PER_SCR_USB0_REG_t;
684 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_RESET 0x00000000
686 #define ALT_NOC_FW_L4_PER_SCR_USB0_REG_OFST 0xc
718 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_LSB 0
720 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_MSB 0
722 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_WIDTH 1
724 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_SET_MSK 0x00000001
726 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_CLR_MSK 0xfffffffe
728 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_RESET 0x0
730 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
732 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
745 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_LSB 8
747 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_MSB 8
749 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_WIDTH 1
751 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_SET_MSK 0x00000100
753 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_CLR_MSK 0xfffffeff
755 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_RESET 0x0
757 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_GET(value) (((value) & 0x00000100) >> 8)
759 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_SET(value) (((value) << 8) & 0x00000100)
772 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_LSB 16
774 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_MSB 16
776 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_WIDTH 1
778 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_SET_MSK 0x00010000
780 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_CLR_MSK 0xfffeffff
782 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_RESET 0x0
784 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
786 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
799 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_LSB 24
801 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_MSB 24
803 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_WIDTH 1
805 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_SET_MSK 0x01000000
807 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_CLR_MSK 0xfeffffff
809 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_RESET 0x0
811 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
813 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
826 struct ALT_NOC_FW_L4_PER_SCR_USB1_REG_s
832 uint32_t fpga2soc : 1;
839 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_USB1_REG_s ALT_NOC_FW_L4_PER_SCR_USB1_REG_t;
843 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_RESET 0x00000000
845 #define ALT_NOC_FW_L4_PER_SCR_USB1_REG_OFST 0x10
866 #define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_LSB 0
868 #define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_MSB 31
870 #define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_WIDTH 32
872 #define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_SET_MSK 0xffffffff
874 #define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_CLR_MSK 0x00000000
876 #define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_RESET 0x1
878 #define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
880 #define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_SET(value) (((value) << 0) & 0xffffffff)
893 struct ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_s
895 uint32_t Reserved : 32;
899 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_s ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_t;
903 #define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RESET 0x00000001
905 #define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_OFST 0x14
926 #define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_LSB 0
928 #define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_MSB 31
930 #define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_WIDTH 32
932 #define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_SET_MSK 0xffffffff
934 #define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_CLR_MSK 0x00000000
936 #define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_RESET 0x0
938 #define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
940 #define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_SET(value) (((value) << 0) & 0xffffffff)
953 struct ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_s
955 uint32_t Reserved : 32;
959 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_s ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_t;
963 #define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RESET 0x00000000
965 #define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_OFST 0x18
997 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_LSB 0
999 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_MSB 0
1001 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_WIDTH 1
1003 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_SET_MSK 0x00000001
1005 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_CLR_MSK 0xfffffffe
1007 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_RESET 0x0
1009 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1011 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1024 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_LSB 8
1026 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_MSB 8
1028 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_WIDTH 1
1030 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_SET_MSK 0x00000100
1032 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_CLR_MSK 0xfffffeff
1034 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_RESET 0x0
1036 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_GET(value) (((value) & 0x00000100) >> 8)
1038 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_SET(value) (((value) << 8) & 0x00000100)
1051 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_LSB 16
1053 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_MSB 16
1055 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_WIDTH 1
1057 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_SET_MSK 0x00010000
1059 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_CLR_MSK 0xfffeffff
1061 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_RESET 0x0
1063 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_GET(value) (((value) & 0x00010000) >> 16)
1065 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_SET(value) (((value) << 16) & 0x00010000)
1078 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_LSB 24
1080 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_MSB 24
1082 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_WIDTH 1
1084 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_SET_MSK 0x01000000
1086 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_CLR_MSK 0xfeffffff
1088 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_RESET 0x0
1090 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1092 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1094 #ifndef __ASSEMBLY__
1105 struct ALT_NOC_FW_L4_PER_SCR_SPI_MST0_s
1107 uint32_t mpu_m0 : 1;
1111 uint32_t fpga2soc : 1;
1113 uint32_t ahb_ap : 1;
1118 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_SPI_MST0_s ALT_NOC_FW_L4_PER_SCR_SPI_MST0_t;
1122 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_RESET 0x00000000
1124 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_OFST 0x1c
1156 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_LSB 0
1158 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_MSB 0
1160 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_WIDTH 1
1162 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_SET_MSK 0x00000001
1164 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_CLR_MSK 0xfffffffe
1166 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_RESET 0x0
1168 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1170 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1183 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_LSB 8
1185 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_MSB 8
1187 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_WIDTH 1
1189 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_SET_MSK 0x00000100
1191 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_CLR_MSK 0xfffffeff
1193 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_RESET 0x0
1195 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_GET(value) (((value) & 0x00000100) >> 8)
1197 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_SET(value) (((value) << 8) & 0x00000100)
1210 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_LSB 16
1212 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_MSB 16
1214 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_WIDTH 1
1216 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_SET_MSK 0x00010000
1218 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_CLR_MSK 0xfffeffff
1220 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_RESET 0x0
1222 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_GET(value) (((value) & 0x00010000) >> 16)
1224 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_SET(value) (((value) << 16) & 0x00010000)
1237 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_LSB 24
1239 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_MSB 24
1241 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_WIDTH 1
1243 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_SET_MSK 0x01000000
1245 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_CLR_MSK 0xfeffffff
1247 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_RESET 0x0
1249 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1251 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1253 #ifndef __ASSEMBLY__
1264 struct ALT_NOC_FW_L4_PER_SCR_SPI_MST1_s
1266 uint32_t mpu_m0 : 1;
1270 uint32_t fpga2soc : 1;
1272 uint32_t ahb_ap : 1;
1277 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_SPI_MST1_s ALT_NOC_FW_L4_PER_SCR_SPI_MST1_t;
1281 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_RESET 0x00000000
1283 #define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_OFST 0x20
1315 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_LSB 0
1317 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_MSB 0
1319 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_WIDTH 1
1321 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_SET_MSK 0x00000001
1323 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_CLR_MSK 0xfffffffe
1325 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_RESET 0x0
1327 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1329 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1342 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_LSB 8
1344 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_MSB 8
1346 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_WIDTH 1
1348 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_SET_MSK 0x00000100
1350 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_CLR_MSK 0xfffffeff
1352 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_RESET 0x0
1354 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_GET(value) (((value) & 0x00000100) >> 8)
1356 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_SET(value) (((value) << 8) & 0x00000100)
1369 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_LSB 16
1371 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_MSB 16
1373 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_WIDTH 1
1375 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_SET_MSK 0x00010000
1377 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_CLR_MSK 0xfffeffff
1379 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_RESET 0x0
1381 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_GET(value) (((value) & 0x00010000) >> 16)
1383 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_SET(value) (((value) << 16) & 0x00010000)
1396 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_LSB 24
1398 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_MSB 24
1400 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_WIDTH 1
1402 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_SET_MSK 0x01000000
1404 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_CLR_MSK 0xfeffffff
1406 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_RESET 0x0
1408 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1410 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1412 #ifndef __ASSEMBLY__
1423 struct ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_s
1425 uint32_t mpu_m0 : 1;
1429 uint32_t fpga2soc : 1;
1431 uint32_t ahb_ap : 1;
1436 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_s ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_t;
1440 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_RESET 0x00000000
1442 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_OFST 0x24
1474 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_LSB 0
1476 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_MSB 0
1478 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_WIDTH 1
1480 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_SET_MSK 0x00000001
1482 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_CLR_MSK 0xfffffffe
1484 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_RESET 0x0
1486 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1488 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1501 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_LSB 8
1503 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_MSB 8
1505 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_WIDTH 1
1507 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_SET_MSK 0x00000100
1509 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_CLR_MSK 0xfffffeff
1511 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_RESET 0x0
1513 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_GET(value) (((value) & 0x00000100) >> 8)
1515 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_SET(value) (((value) << 8) & 0x00000100)
1528 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_LSB 16
1530 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_MSB 16
1532 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_WIDTH 1
1534 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_SET_MSK 0x00010000
1536 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_CLR_MSK 0xfffeffff
1538 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_RESET 0x0
1540 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_GET(value) (((value) & 0x00010000) >> 16)
1542 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_SET(value) (((value) << 16) & 0x00010000)
1555 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_LSB 24
1557 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_MSB 24
1559 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_WIDTH 1
1561 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_SET_MSK 0x01000000
1563 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_CLR_MSK 0xfeffffff
1565 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_RESET 0x0
1567 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1569 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1571 #ifndef __ASSEMBLY__
1582 struct ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_s
1584 uint32_t mpu_m0 : 1;
1588 uint32_t fpga2soc : 1;
1590 uint32_t ahb_ap : 1;
1595 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_s ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_t;
1599 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_RESET 0x00000000
1601 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_OFST 0x28
1633 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_LSB 0
1635 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_MSB 0
1637 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_WIDTH 1
1639 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_SET_MSK 0x00000001
1641 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_CLR_MSK 0xfffffffe
1643 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_RESET 0x0
1645 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1647 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1660 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_LSB 8
1662 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_MSB 8
1664 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_WIDTH 1
1666 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_SET_MSK 0x00000100
1668 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_CLR_MSK 0xfffffeff
1670 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_RESET 0x0
1672 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_GET(value) (((value) & 0x00000100) >> 8)
1674 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_SET(value) (((value) << 8) & 0x00000100)
1687 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_LSB 16
1689 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_MSB 16
1691 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_WIDTH 1
1693 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_SET_MSK 0x00010000
1695 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_CLR_MSK 0xfffeffff
1697 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_RESET 0x0
1699 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_GET(value) (((value) & 0x00010000) >> 16)
1701 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_SET(value) (((value) << 16) & 0x00010000)
1714 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_LSB 24
1716 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_MSB 24
1718 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_WIDTH 1
1720 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_SET_MSK 0x01000000
1722 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_CLR_MSK 0xfeffffff
1724 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_RESET 0x0
1726 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1728 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1730 #ifndef __ASSEMBLY__
1741 struct ALT_NOC_FW_L4_PER_SCR_EMAC0_s
1743 uint32_t mpu_m0 : 1;
1747 uint32_t fpga2soc : 1;
1749 uint32_t ahb_ap : 1;
1754 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_EMAC0_s ALT_NOC_FW_L4_PER_SCR_EMAC0_t;
1758 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_RESET 0x00000000
1760 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_OFST 0x2c
1792 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_LSB 0
1794 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_MSB 0
1796 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_WIDTH 1
1798 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_SET_MSK 0x00000001
1800 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_CLR_MSK 0xfffffffe
1802 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_RESET 0x0
1804 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1806 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1819 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_LSB 8
1821 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_MSB 8
1823 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_WIDTH 1
1825 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_SET_MSK 0x00000100
1827 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_CLR_MSK 0xfffffeff
1829 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_RESET 0x0
1831 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_GET(value) (((value) & 0x00000100) >> 8)
1833 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_SET(value) (((value) << 8) & 0x00000100)
1846 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_LSB 16
1848 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_MSB 16
1850 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_WIDTH 1
1852 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_SET_MSK 0x00010000
1854 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_CLR_MSK 0xfffeffff
1856 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_RESET 0x0
1858 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_GET(value) (((value) & 0x00010000) >> 16)
1860 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_SET(value) (((value) << 16) & 0x00010000)
1873 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_LSB 24
1875 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_MSB 24
1877 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_WIDTH 1
1879 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_SET_MSK 0x01000000
1881 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_CLR_MSK 0xfeffffff
1883 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_RESET 0x0
1885 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1887 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1889 #ifndef __ASSEMBLY__
1900 struct ALT_NOC_FW_L4_PER_SCR_EMAC1_s
1902 uint32_t mpu_m0 : 1;
1906 uint32_t fpga2soc : 1;
1908 uint32_t ahb_ap : 1;
1913 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_EMAC1_s ALT_NOC_FW_L4_PER_SCR_EMAC1_t;
1917 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_RESET 0x00000000
1919 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_OFST 0x30
1951 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_LSB 0
1953 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_MSB 0
1955 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_WIDTH 1
1957 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_SET_MSK 0x00000001
1959 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_CLR_MSK 0xfffffffe
1961 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_RESET 0x0
1963 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1965 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1978 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_LSB 8
1980 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_MSB 8
1982 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_WIDTH 1
1984 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_SET_MSK 0x00000100
1986 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_CLR_MSK 0xfffffeff
1988 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_RESET 0x0
1990 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_GET(value) (((value) & 0x00000100) >> 8)
1992 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_SET(value) (((value) << 8) & 0x00000100)
2005 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_LSB 16
2007 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_MSB 16
2009 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_WIDTH 1
2011 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_SET_MSK 0x00010000
2013 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_CLR_MSK 0xfffeffff
2015 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_RESET 0x0
2017 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_GET(value) (((value) & 0x00010000) >> 16)
2019 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_SET(value) (((value) << 16) & 0x00010000)
2032 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_LSB 24
2034 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_MSB 24
2036 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_WIDTH 1
2038 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_SET_MSK 0x01000000
2040 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_CLR_MSK 0xfeffffff
2042 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_RESET 0x0
2044 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2046 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2048 #ifndef __ASSEMBLY__
2059 struct ALT_NOC_FW_L4_PER_SCR_EMAC2_s
2061 uint32_t mpu_m0 : 1;
2065 uint32_t fpga2soc : 1;
2067 uint32_t ahb_ap : 1;
2072 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_EMAC2_s ALT_NOC_FW_L4_PER_SCR_EMAC2_t;
2076 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_RESET 0x00000000
2078 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_OFST 0x34
2099 #define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_LSB 0
2101 #define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_MSB 31
2103 #define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_WIDTH 32
2105 #define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_SET_MSK 0xffffffff
2107 #define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_CLR_MSK 0x00000000
2109 #define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_RESET 0x0
2111 #define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
2113 #define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_SET(value) (((value) << 0) & 0xffffffff)
2115 #ifndef __ASSEMBLY__
2126 struct ALT_NOC_FW_L4_PER_SCR_EMAC3_s
2128 uint32_t Reserved : 32;
2132 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_EMAC3_s ALT_NOC_FW_L4_PER_SCR_EMAC3_t;
2136 #define ALT_NOC_FW_L4_PER_SCR_EMAC3_RESET 0x00000000
2138 #define ALT_NOC_FW_L4_PER_SCR_EMAC3_OFST 0x38
2170 #define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_LSB 0
2172 #define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_MSB 0
2174 #define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_WIDTH 1
2176 #define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_SET_MSK 0x00000001
2178 #define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_CLR_MSK 0xfffffffe
2180 #define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_RESET 0x0
2182 #define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2184 #define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2197 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_LSB 8
2199 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_MSB 8
2201 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_WIDTH 1
2203 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_SET_MSK 0x00000100
2205 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_CLR_MSK 0xfffffeff
2207 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_RESET 0x0
2209 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_GET(value) (((value) & 0x00000100) >> 8)
2211 #define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_SET(value) (((value) << 8) & 0x00000100)
2224 #define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_LSB 16
2226 #define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_MSB 16
2228 #define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_WIDTH 1
2230 #define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_SET_MSK 0x00010000
2232 #define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_CLR_MSK 0xfffeffff
2234 #define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_RESET 0x0
2236 #define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_GET(value) (((value) & 0x00010000) >> 16)
2238 #define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_SET(value) (((value) << 16) & 0x00010000)
2251 #define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_LSB 24
2253 #define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_MSB 24
2255 #define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_WIDTH 1
2257 #define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_SET_MSK 0x01000000
2259 #define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_CLR_MSK 0xfeffffff
2261 #define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_RESET 0x0
2263 #define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2265 #define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2267 #ifndef __ASSEMBLY__
2278 struct ALT_NOC_FW_L4_PER_SCR_QSPI_s
2280 uint32_t mpu_m0 : 1;
2284 uint32_t fpga2soc : 1;
2286 uint32_t ahb_ap : 1;
2291 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_QSPI_s ALT_NOC_FW_L4_PER_SCR_QSPI_t;
2295 #define ALT_NOC_FW_L4_PER_SCR_QSPI_RESET 0x00000000
2297 #define ALT_NOC_FW_L4_PER_SCR_QSPI_OFST 0x3c
2329 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_LSB 0
2331 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_MSB 0
2333 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_WIDTH 1
2335 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_SET_MSK 0x00000001
2337 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_CLR_MSK 0xfffffffe
2339 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_RESET 0x0
2341 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2343 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2356 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_LSB 8
2358 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_MSB 8
2360 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_WIDTH 1
2362 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_SET_MSK 0x00000100
2364 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_CLR_MSK 0xfffffeff
2366 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_RESET 0x0
2368 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_GET(value) (((value) & 0x00000100) >> 8)
2370 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_SET(value) (((value) << 8) & 0x00000100)
2383 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_LSB 16
2385 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_MSB 16
2387 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_WIDTH 1
2389 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_SET_MSK 0x00010000
2391 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_CLR_MSK 0xfffeffff
2393 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_RESET 0x0
2395 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_GET(value) (((value) & 0x00010000) >> 16)
2397 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_SET(value) (((value) << 16) & 0x00010000)
2410 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_LSB 24
2412 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_MSB 24
2414 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_WIDTH 1
2416 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_SET_MSK 0x01000000
2418 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_CLR_MSK 0xfeffffff
2420 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_RESET 0x0
2422 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2424 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2426 #ifndef __ASSEMBLY__
2437 struct ALT_NOC_FW_L4_PER_SCR_SDMMC_s
2439 uint32_t mpu_m0 : 1;
2443 uint32_t fpga2soc : 1;
2445 uint32_t ahb_ap : 1;
2450 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_SDMMC_s ALT_NOC_FW_L4_PER_SCR_SDMMC_t;
2454 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_RESET 0x00000000
2456 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_OFST 0x40
2488 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_LSB 0
2490 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_MSB 0
2492 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_WIDTH 1
2494 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_SET_MSK 0x00000001
2496 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_CLR_MSK 0xfffffffe
2498 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_RESET 0x0
2500 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2502 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2515 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_LSB 8
2517 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_MSB 8
2519 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_WIDTH 1
2521 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_SET_MSK 0x00000100
2523 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_CLR_MSK 0xfffffeff
2525 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_RESET 0x0
2527 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_GET(value) (((value) & 0x00000100) >> 8)
2529 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_SET(value) (((value) << 8) & 0x00000100)
2542 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_LSB 16
2544 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_MSB 16
2546 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_WIDTH 1
2548 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_SET_MSK 0x00010000
2550 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_CLR_MSK 0xfffeffff
2552 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_RESET 0x0
2554 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_GET(value) (((value) & 0x00010000) >> 16)
2556 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_SET(value) (((value) << 16) & 0x00010000)
2569 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_LSB 24
2571 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_MSB 24
2573 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_WIDTH 1
2575 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_SET_MSK 0x01000000
2577 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_CLR_MSK 0xfeffffff
2579 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_RESET 0x0
2581 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2583 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2585 #ifndef __ASSEMBLY__
2596 struct ALT_NOC_FW_L4_PER_SCR_GPIO0_s
2598 uint32_t mpu_m0 : 1;
2602 uint32_t fpga2soc : 1;
2604 uint32_t ahb_ap : 1;
2609 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_GPIO0_s ALT_NOC_FW_L4_PER_SCR_GPIO0_t;
2613 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_RESET 0x00000000
2615 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_OFST 0x44
2647 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_LSB 0
2649 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_MSB 0
2651 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_WIDTH 1
2653 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_SET_MSK 0x00000001
2655 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_CLR_MSK 0xfffffffe
2657 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_RESET 0x0
2659 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2661 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2674 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_LSB 8
2676 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_MSB 8
2678 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_WIDTH 1
2680 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_SET_MSK 0x00000100
2682 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_CLR_MSK 0xfffffeff
2684 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_RESET 0x0
2686 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_GET(value) (((value) & 0x00000100) >> 8)
2688 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_SET(value) (((value) << 8) & 0x00000100)
2701 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_LSB 16
2703 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_MSB 16
2705 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_WIDTH 1
2707 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_SET_MSK 0x00010000
2709 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_CLR_MSK 0xfffeffff
2711 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_RESET 0x0
2713 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_GET(value) (((value) & 0x00010000) >> 16)
2715 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_SET(value) (((value) << 16) & 0x00010000)
2728 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_LSB 24
2730 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_MSB 24
2732 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_WIDTH 1
2734 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_SET_MSK 0x01000000
2736 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_CLR_MSK 0xfeffffff
2738 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_RESET 0x0
2740 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2742 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2744 #ifndef __ASSEMBLY__
2755 struct ALT_NOC_FW_L4_PER_SCR_GPIO1_s
2757 uint32_t mpu_m0 : 1;
2761 uint32_t fpga2soc : 1;
2763 uint32_t ahb_ap : 1;
2768 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_GPIO1_s ALT_NOC_FW_L4_PER_SCR_GPIO1_t;
2772 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_RESET 0x00000000
2774 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_OFST 0x48
2806 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_LSB 0
2808 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_MSB 0
2810 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_WIDTH 1
2812 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_SET_MSK 0x00000001
2814 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_CLR_MSK 0xfffffffe
2816 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_RESET 0x0
2818 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2820 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2833 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_LSB 8
2835 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_MSB 8
2837 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_WIDTH 1
2839 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_SET_MSK 0x00000100
2841 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_CLR_MSK 0xfffffeff
2843 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_RESET 0x0
2845 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_GET(value) (((value) & 0x00000100) >> 8)
2847 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_SET(value) (((value) << 8) & 0x00000100)
2860 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_LSB 16
2862 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_MSB 16
2864 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_WIDTH 1
2866 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_SET_MSK 0x00010000
2868 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_CLR_MSK 0xfffeffff
2870 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_RESET 0x0
2872 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_GET(value) (((value) & 0x00010000) >> 16)
2874 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_SET(value) (((value) << 16) & 0x00010000)
2887 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_LSB 24
2889 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_MSB 24
2891 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_WIDTH 1
2893 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_SET_MSK 0x01000000
2895 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_CLR_MSK 0xfeffffff
2897 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_RESET 0x0
2899 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2901 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2903 #ifndef __ASSEMBLY__
2914 struct ALT_NOC_FW_L4_PER_SCR_GPIO2_s
2916 uint32_t mpu_m0 : 1;
2920 uint32_t fpga2soc : 1;
2922 uint32_t ahb_ap : 1;
2927 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_GPIO2_s ALT_NOC_FW_L4_PER_SCR_GPIO2_t;
2931 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_RESET 0x00000000
2933 #define ALT_NOC_FW_L4_PER_SCR_GPIO2_OFST 0x4c
2965 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_LSB 0
2967 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_MSB 0
2969 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_WIDTH 1
2971 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_SET_MSK 0x00000001
2973 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_CLR_MSK 0xfffffffe
2975 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_RESET 0x0
2977 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2979 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2992 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_LSB 8
2994 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_MSB 8
2996 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_WIDTH 1
2998 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_SET_MSK 0x00000100
3000 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_CLR_MSK 0xfffffeff
3002 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_RESET 0x0
3004 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_GET(value) (((value) & 0x00000100) >> 8)
3006 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_SET(value) (((value) << 8) & 0x00000100)
3019 #define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_LSB 16
3021 #define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_MSB 16
3023 #define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_WIDTH 1
3025 #define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_SET_MSK 0x00010000
3027 #define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_CLR_MSK 0xfffeffff
3029 #define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_RESET 0x0
3031 #define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_GET(value) (((value) & 0x00010000) >> 16)
3033 #define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_SET(value) (((value) << 16) & 0x00010000)
3046 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_LSB 24
3048 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_MSB 24
3050 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_WIDTH 1
3052 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_SET_MSK 0x01000000
3054 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_CLR_MSK 0xfeffffff
3056 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_RESET 0x0
3058 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3060 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3062 #ifndef __ASSEMBLY__
3073 struct ALT_NOC_FW_L4_PER_SCR_I2C0_s
3075 uint32_t mpu_m0 : 1;
3079 uint32_t fpga2soc : 1;
3081 uint32_t ahb_ap : 1;
3086 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_I2C0_s ALT_NOC_FW_L4_PER_SCR_I2C0_t;
3090 #define ALT_NOC_FW_L4_PER_SCR_I2C0_RESET 0x00000000
3092 #define ALT_NOC_FW_L4_PER_SCR_I2C0_OFST 0x50
3124 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_LSB 0
3126 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_MSB 0
3128 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_WIDTH 1
3130 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_SET_MSK 0x00000001
3132 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_CLR_MSK 0xfffffffe
3134 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_RESET 0x0
3136 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3138 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3151 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_LSB 8
3153 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_MSB 8
3155 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_WIDTH 1
3157 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_SET_MSK 0x00000100
3159 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_CLR_MSK 0xfffffeff
3161 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_RESET 0x0
3163 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_GET(value) (((value) & 0x00000100) >> 8)
3165 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_SET(value) (((value) << 8) & 0x00000100)
3178 #define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_LSB 16
3180 #define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_MSB 16
3182 #define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_WIDTH 1
3184 #define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_SET_MSK 0x00010000
3186 #define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_CLR_MSK 0xfffeffff
3188 #define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_RESET 0x0
3190 #define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_GET(value) (((value) & 0x00010000) >> 16)
3192 #define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_SET(value) (((value) << 16) & 0x00010000)
3205 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_LSB 24
3207 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_MSB 24
3209 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_WIDTH 1
3211 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_SET_MSK 0x01000000
3213 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_CLR_MSK 0xfeffffff
3215 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_RESET 0x0
3217 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3219 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3221 #ifndef __ASSEMBLY__
3232 struct ALT_NOC_FW_L4_PER_SCR_I2C1_s
3234 uint32_t mpu_m0 : 1;
3238 uint32_t fpga2soc : 1;
3240 uint32_t ahb_ap : 1;
3245 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_I2C1_s ALT_NOC_FW_L4_PER_SCR_I2C1_t;
3249 #define ALT_NOC_FW_L4_PER_SCR_I2C1_RESET 0x00000000
3251 #define ALT_NOC_FW_L4_PER_SCR_I2C1_OFST 0x54
3283 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_LSB 0
3285 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_MSB 0
3287 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_WIDTH 1
3289 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_SET_MSK 0x00000001
3291 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_CLR_MSK 0xfffffffe
3293 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_RESET 0x0
3295 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3297 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3310 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_LSB 8
3312 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_MSB 8
3314 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_WIDTH 1
3316 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_SET_MSK 0x00000100
3318 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_CLR_MSK 0xfffffeff
3320 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_RESET 0x0
3322 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_GET(value) (((value) & 0x00000100) >> 8)
3324 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_SET(value) (((value) << 8) & 0x00000100)
3337 #define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_LSB 16
3339 #define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_MSB 16
3341 #define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_WIDTH 1
3343 #define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_SET_MSK 0x00010000
3345 #define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_CLR_MSK 0xfffeffff
3347 #define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_RESET 0x0
3349 #define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_GET(value) (((value) & 0x00010000) >> 16)
3351 #define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_SET(value) (((value) << 16) & 0x00010000)
3364 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_LSB 24
3366 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_MSB 24
3368 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_WIDTH 1
3370 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_SET_MSK 0x01000000
3372 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_CLR_MSK 0xfeffffff
3374 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_RESET 0x0
3376 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3378 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3380 #ifndef __ASSEMBLY__
3391 struct ALT_NOC_FW_L4_PER_SCR_I2C2_s
3393 uint32_t mpu_m0 : 1;
3397 uint32_t fpga2soc : 1;
3399 uint32_t ahb_ap : 1;
3404 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_I2C2_s ALT_NOC_FW_L4_PER_SCR_I2C2_t;
3408 #define ALT_NOC_FW_L4_PER_SCR_I2C2_RESET 0x00000000
3410 #define ALT_NOC_FW_L4_PER_SCR_I2C2_OFST 0x58
3442 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_LSB 0
3444 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_MSB 0
3446 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_WIDTH 1
3448 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_SET_MSK 0x00000001
3450 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_CLR_MSK 0xfffffffe
3452 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_RESET 0x0
3454 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3456 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3469 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_LSB 8
3471 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_MSB 8
3473 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_WIDTH 1
3475 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_SET_MSK 0x00000100
3477 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_CLR_MSK 0xfffffeff
3479 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_RESET 0x0
3481 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_GET(value) (((value) & 0x00000100) >> 8)
3483 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_SET(value) (((value) << 8) & 0x00000100)
3496 #define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_LSB 16
3498 #define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_MSB 16
3500 #define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_WIDTH 1
3502 #define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_SET_MSK 0x00010000
3504 #define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_CLR_MSK 0xfffeffff
3506 #define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_RESET 0x0
3508 #define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_GET(value) (((value) & 0x00010000) >> 16)
3510 #define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_SET(value) (((value) << 16) & 0x00010000)
3523 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_LSB 24
3525 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_MSB 24
3527 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_WIDTH 1
3529 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_SET_MSK 0x01000000
3531 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_CLR_MSK 0xfeffffff
3533 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_RESET 0x0
3535 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3537 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3539 #ifndef __ASSEMBLY__
3550 struct ALT_NOC_FW_L4_PER_SCR_I2C3_s
3552 uint32_t mpu_m0 : 1;
3556 uint32_t fpga2soc : 1;
3558 uint32_t ahb_ap : 1;
3563 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_I2C3_s ALT_NOC_FW_L4_PER_SCR_I2C3_t;
3567 #define ALT_NOC_FW_L4_PER_SCR_I2C3_RESET 0x00000000
3569 #define ALT_NOC_FW_L4_PER_SCR_I2C3_OFST 0x5c
3601 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_LSB 0
3603 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_MSB 0
3605 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_WIDTH 1
3607 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_SET_MSK 0x00000001
3609 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_CLR_MSK 0xfffffffe
3611 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_RESET 0x0
3613 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3615 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3628 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_LSB 8
3630 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_MSB 8
3632 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_WIDTH 1
3634 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_SET_MSK 0x00000100
3636 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_CLR_MSK 0xfffffeff
3638 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_RESET 0x0
3640 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_GET(value) (((value) & 0x00000100) >> 8)
3642 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_SET(value) (((value) << 8) & 0x00000100)
3655 #define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_LSB 16
3657 #define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_MSB 16
3659 #define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_WIDTH 1
3661 #define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_SET_MSK 0x00010000
3663 #define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_CLR_MSK 0xfffeffff
3665 #define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_RESET 0x0
3667 #define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_GET(value) (((value) & 0x00010000) >> 16)
3669 #define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_SET(value) (((value) << 16) & 0x00010000)
3682 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_LSB 24
3684 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_MSB 24
3686 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_WIDTH 1
3688 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_SET_MSK 0x01000000
3690 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_CLR_MSK 0xfeffffff
3692 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_RESET 0x0
3694 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3696 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3698 #ifndef __ASSEMBLY__
3709 struct ALT_NOC_FW_L4_PER_SCR_I2C4_s
3711 uint32_t mpu_m0 : 1;
3715 uint32_t fpga2soc : 1;
3717 uint32_t ahb_ap : 1;
3722 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_I2C4_s ALT_NOC_FW_L4_PER_SCR_I2C4_t;
3726 #define ALT_NOC_FW_L4_PER_SCR_I2C4_RESET 0x00000000
3728 #define ALT_NOC_FW_L4_PER_SCR_I2C4_OFST 0x60
3760 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_LSB 0
3762 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_MSB 0
3764 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_WIDTH 1
3766 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_SET_MSK 0x00000001
3768 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_CLR_MSK 0xfffffffe
3770 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_RESET 0x0
3772 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3774 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3787 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_LSB 8
3789 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_MSB 8
3791 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_WIDTH 1
3793 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_SET_MSK 0x00000100
3795 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_CLR_MSK 0xfffffeff
3797 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_RESET 0x0
3799 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_GET(value) (((value) & 0x00000100) >> 8)
3801 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_SET(value) (((value) << 8) & 0x00000100)
3814 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_LSB 16
3816 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_MSB 16
3818 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_WIDTH 1
3820 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_SET_MSK 0x00010000
3822 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_CLR_MSK 0xfffeffff
3824 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_RESET 0x0
3826 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_GET(value) (((value) & 0x00010000) >> 16)
3828 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_SET(value) (((value) << 16) & 0x00010000)
3841 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_LSB 24
3843 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_MSB 24
3845 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_WIDTH 1
3847 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_SET_MSK 0x01000000
3849 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_CLR_MSK 0xfeffffff
3851 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_RESET 0x0
3853 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3855 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3857 #ifndef __ASSEMBLY__
3868 struct ALT_NOC_FW_L4_PER_SCR_SP_TMR0_s
3870 uint32_t mpu_m0 : 1;
3874 uint32_t fpga2soc : 1;
3876 uint32_t ahb_ap : 1;
3881 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_SP_TMR0_s ALT_NOC_FW_L4_PER_SCR_SP_TMR0_t;
3885 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_RESET 0x00000000
3887 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_OFST 0x64
3919 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_LSB 0
3921 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_MSB 0
3923 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_WIDTH 1
3925 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_SET_MSK 0x00000001
3927 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_CLR_MSK 0xfffffffe
3929 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_RESET 0x0
3931 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3933 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3946 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_LSB 8
3948 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_MSB 8
3950 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_WIDTH 1
3952 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_SET_MSK 0x00000100
3954 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_CLR_MSK 0xfffffeff
3956 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_RESET 0x0
3958 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_GET(value) (((value) & 0x00000100) >> 8)
3960 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_SET(value) (((value) << 8) & 0x00000100)
3973 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_LSB 16
3975 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_MSB 16
3977 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_WIDTH 1
3979 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_SET_MSK 0x00010000
3981 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_CLR_MSK 0xfffeffff
3983 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_RESET 0x0
3985 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_GET(value) (((value) & 0x00010000) >> 16)
3987 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_SET(value) (((value) << 16) & 0x00010000)
4000 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_LSB 24
4002 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_MSB 24
4004 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_WIDTH 1
4006 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_SET_MSK 0x01000000
4008 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_CLR_MSK 0xfeffffff
4010 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_RESET 0x0
4012 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4014 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4016 #ifndef __ASSEMBLY__
4027 struct ALT_NOC_FW_L4_PER_SCR_SP_TMR1_s
4029 uint32_t mpu_m0 : 1;
4033 uint32_t fpga2soc : 1;
4035 uint32_t ahb_ap : 1;
4040 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_SP_TMR1_s ALT_NOC_FW_L4_PER_SCR_SP_TMR1_t;
4044 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_RESET 0x00000000
4046 #define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_OFST 0x68
4078 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_LSB 0
4080 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_MSB 0
4082 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_WIDTH 1
4084 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_SET_MSK 0x00000001
4086 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_CLR_MSK 0xfffffffe
4088 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_RESET 0x0
4090 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4092 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4105 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_LSB 8
4107 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_MSB 8
4109 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_WIDTH 1
4111 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_SET_MSK 0x00000100
4113 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_CLR_MSK 0xfffffeff
4115 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_RESET 0x0
4117 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_GET(value) (((value) & 0x00000100) >> 8)
4119 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_SET(value) (((value) << 8) & 0x00000100)
4132 #define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_LSB 16
4134 #define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_MSB 16
4136 #define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_WIDTH 1
4138 #define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_SET_MSK 0x00010000
4140 #define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_CLR_MSK 0xfffeffff
4142 #define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_RESET 0x0
4144 #define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_GET(value) (((value) & 0x00010000) >> 16)
4146 #define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_SET(value) (((value) << 16) & 0x00010000)
4159 #define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_LSB 24
4161 #define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_MSB 24
4163 #define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_WIDTH 1
4165 #define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_SET_MSK 0x01000000
4167 #define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_CLR_MSK 0xfeffffff
4169 #define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_RESET 0x0
4171 #define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4173 #define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4175 #ifndef __ASSEMBLY__
4186 struct ALT_NOC_FW_L4_PER_SCR_UART0_s
4188 uint32_t mpu_m0 : 1;
4192 uint32_t fpga2soc : 1;
4194 uint32_t ahb_ap : 1;
4199 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_UART0_s ALT_NOC_FW_L4_PER_SCR_UART0_t;
4203 #define ALT_NOC_FW_L4_PER_SCR_UART0_RESET 0x00000000
4205 #define ALT_NOC_FW_L4_PER_SCR_UART0_OFST 0x6c
4237 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_LSB 0
4239 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_MSB 0
4241 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_WIDTH 1
4243 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_SET_MSK 0x00000001
4245 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_CLR_MSK 0xfffffffe
4247 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_RESET 0x0
4249 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4251 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4264 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_LSB 8
4266 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_MSB 8
4268 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_WIDTH 1
4270 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_SET_MSK 0x00000100
4272 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_CLR_MSK 0xfffffeff
4274 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_RESET 0x0
4276 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_GET(value) (((value) & 0x00000100) >> 8)
4278 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_SET(value) (((value) << 8) & 0x00000100)
4291 #define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_LSB 16
4293 #define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_MSB 16
4295 #define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_WIDTH 1
4297 #define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_SET_MSK 0x00010000
4299 #define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_CLR_MSK 0xfffeffff
4301 #define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_RESET 0x0
4303 #define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_GET(value) (((value) & 0x00010000) >> 16)
4305 #define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_SET(value) (((value) << 16) & 0x00010000)
4318 #define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_LSB 24
4320 #define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_MSB 24
4322 #define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_WIDTH 1
4324 #define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_SET_MSK 0x01000000
4326 #define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_CLR_MSK 0xfeffffff
4328 #define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_RESET 0x0
4330 #define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4332 #define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4334 #ifndef __ASSEMBLY__
4345 struct ALT_NOC_FW_L4_PER_SCR_UART1_s
4347 uint32_t mpu_m0 : 1;
4351 uint32_t fpga2soc : 1;
4353 uint32_t ahb_ap : 1;
4358 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_UART1_s ALT_NOC_FW_L4_PER_SCR_UART1_t;
4362 #define ALT_NOC_FW_L4_PER_SCR_UART1_RESET 0x00000000
4364 #define ALT_NOC_FW_L4_PER_SCR_UART1_OFST 0x70
4366 #ifndef __ASSEMBLY__
4377 struct ALT_NOC_FW_L4_PER_SCR_s
4379 ALT_NOC_FW_L4_PER_SCR_NAND_REG_t nand_register;
4380 ALT_NOC_FW_L4_PER_SCR_NAND_DATA_t nand_data;
4381 ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_t qspi_data;
4382 ALT_NOC_FW_L4_PER_SCR_USB0_REG_t usb0_register;
4383 ALT_NOC_FW_L4_PER_SCR_USB1_REG_t usb1_register;
4384 ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_t dma_nonsecure;
4385 ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_t dma_secure;
4386 ALT_NOC_FW_L4_PER_SCR_SPI_MST0_t spi_master0;
4387 ALT_NOC_FW_L4_PER_SCR_SPI_MST1_t spi_master1;
4388 ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_t spi_slave0;
4389 ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_t spi_slave1;
4390 ALT_NOC_FW_L4_PER_SCR_EMAC0_t emac0;
4391 ALT_NOC_FW_L4_PER_SCR_EMAC1_t emac1;
4392 ALT_NOC_FW_L4_PER_SCR_EMAC2_t emac2;
4393 ALT_NOC_FW_L4_PER_SCR_EMAC3_t emac3;
4394 ALT_NOC_FW_L4_PER_SCR_QSPI_t qspi;
4395 ALT_NOC_FW_L4_PER_SCR_SDMMC_t sdmmc;
4396 ALT_NOC_FW_L4_PER_SCR_GPIO0_t gpio0;
4397 ALT_NOC_FW_L4_PER_SCR_GPIO1_t gpio1;
4398 ALT_NOC_FW_L4_PER_SCR_GPIO2_t gpio2;
4399 ALT_NOC_FW_L4_PER_SCR_I2C0_t i2c0;
4400 ALT_NOC_FW_L4_PER_SCR_I2C1_t i2c1;
4401 ALT_NOC_FW_L4_PER_SCR_I2C2_t i2c2;
4402 ALT_NOC_FW_L4_PER_SCR_I2C3_t i2c3;
4403 ALT_NOC_FW_L4_PER_SCR_I2C4_t i2c4;
4404 ALT_NOC_FW_L4_PER_SCR_SP_TMR0_t sp_timer0;
4405 ALT_NOC_FW_L4_PER_SCR_SP_TMR1_t sp_timer1;
4406 ALT_NOC_FW_L4_PER_SCR_UART0_t uart0;
4407 ALT_NOC_FW_L4_PER_SCR_UART1_t uart1;
4408 volatile uint32_t _pad_0x74_0x100[35];
4412 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_s ALT_NOC_FW_L4_PER_SCR_t;
4414 struct ALT_NOC_FW_L4_PER_SCR_raw_s
4416 volatile uint32_t nand_register;
4417 volatile uint32_t nand_data;
4418 volatile uint32_t qspi_data;
4419 volatile uint32_t usb0_register;
4420 volatile uint32_t usb1_register;
4421 volatile uint32_t dma_nonsecure;
4422 volatile uint32_t dma_secure;
4423 volatile uint32_t spi_master0;
4424 volatile uint32_t spi_master1;
4425 volatile uint32_t spi_slave0;
4426 volatile uint32_t spi_slave1;
4427 volatile uint32_t emac0;
4428 volatile uint32_t emac1;
4429 volatile uint32_t emac2;
4430 volatile uint32_t emac3;
4431 volatile uint32_t qspi;
4432 volatile uint32_t sdmmc;
4433 volatile uint32_t gpio0;
4434 volatile uint32_t gpio1;
4435 volatile uint32_t gpio2;
4436 volatile uint32_t i2c0;
4437 volatile uint32_t i2c1;
4438 volatile uint32_t i2c2;
4439 volatile uint32_t i2c3;
4440 volatile uint32_t i2c4;
4441 volatile uint32_t sp_timer0;
4442 volatile uint32_t sp_timer1;
4443 volatile uint32_t uart0;
4444 volatile uint32_t uart1;
4445 uint32_t _pad_0x74_0x100[35];
4449 typedef volatile struct ALT_NOC_FW_L4_PER_SCR_raw_s ALT_NOC_FW_L4_PER_SCR_raw_t;