Hardware Libraries  20.1
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alt_noc_fw_h2f_scr.h
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32 
33 /* Altera - ALT_NOC_FW_H2F_SCR */
34 
35 #ifndef __ALT_SOCAL_NOC_FW_H2F_SCR_H__
36 #define __ALT_SOCAL_NOC_FW_H2F_SCR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_NOC_FW_H2F_SCR
50  *
51  */
52 /*
53  * Register : lwsoc2fpga
54  *
55  * Per-Master Security bit for Lightweight SOC2FPGA
56  *
57  * Register Layout
58  *
59  * Bits | Access | Reset | Description
60  * :--------|:-------|:------|:--------------------------------
61  * [0] | RW | 0x0 | ALT_NOC_FW_H2F_SCR_LWH2F_MPU_M0
62  * [7:1] | ??? | 0x0 | *UNDEFINED*
63  * [8] | RW | 0x0 | ALT_NOC_FW_H2F_SCR_LWH2F_DMA
64  * [16:9] | ??? | 0x0 | *UNDEFINED*
65  * [17] | RW | 0x0 | ALT_NOC_FW_H2F_SCR_LWH2F_EMAC0
66  * [18] | RW | 0x0 | ALT_NOC_FW_H2F_SCR_LWH2F_EMAC1
67  * [19] | RW | 0x0 | ALT_NOC_FW_H2F_SCR_LWH2F_EMAC2
68  * [20] | RW | 0x0 | ALT_NOC_FW_H2F_SCR_LWH2F_USB0
69  * [21] | RW | 0x0 | ALT_NOC_FW_H2F_SCR_LWH2F_USB1
70  * [22] | RW | 0x0 | ALT_NOC_FW_H2F_SCR_LWH2F_SDMMC
71  * [23] | RW | 0x0 | ALT_NOC_FW_H2F_SCR_LWH2F_NAND
72  * [24] | RW | 0x0 | ALT_NOC_FW_H2F_SCR_LWH2F_AHB_AP
73  * [25] | RW | 0x0 | ALT_NOC_FW_H2F_SCR_LWH2F_ETR
74  * [31:26] | ??? | 0x0 | *UNDEFINED*
75  *
76  */
77 /*
78  * Field : mpu_m0
79  *
80  * Security bit configuration for transactions from mpu0 to lwsoc2fpga. When
81  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
82  * Non-Secure transactions are allowed.
83  *
84  * Field Access Macros:
85  *
86  */
87 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_H2F_SCR_LWH2F_MPU_M0 register field. */
88 #define ALT_NOC_FW_H2F_SCR_LWH2F_MPU_M0_LSB 0
89 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_H2F_SCR_LWH2F_MPU_M0 register field. */
90 #define ALT_NOC_FW_H2F_SCR_LWH2F_MPU_M0_MSB 0
91 /* The width in bits of the ALT_NOC_FW_H2F_SCR_LWH2F_MPU_M0 register field. */
92 #define ALT_NOC_FW_H2F_SCR_LWH2F_MPU_M0_WIDTH 1
93 /* The mask used to set the ALT_NOC_FW_H2F_SCR_LWH2F_MPU_M0 register field value. */
94 #define ALT_NOC_FW_H2F_SCR_LWH2F_MPU_M0_SET_MSK 0x00000001
95 /* The mask used to clear the ALT_NOC_FW_H2F_SCR_LWH2F_MPU_M0 register field value. */
96 #define ALT_NOC_FW_H2F_SCR_LWH2F_MPU_M0_CLR_MSK 0xfffffffe
97 /* The reset value of the ALT_NOC_FW_H2F_SCR_LWH2F_MPU_M0 register field. */
98 #define ALT_NOC_FW_H2F_SCR_LWH2F_MPU_M0_RESET 0x0
99 /* Extracts the ALT_NOC_FW_H2F_SCR_LWH2F_MPU_M0 field value from a register. */
100 #define ALT_NOC_FW_H2F_SCR_LWH2F_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
101 /* Produces a ALT_NOC_FW_H2F_SCR_LWH2F_MPU_M0 register field value suitable for setting the register. */
102 #define ALT_NOC_FW_H2F_SCR_LWH2F_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
103 
104 /*
105  * Field : dma
106  *
107  * Security bit configuration for transactions from dma to lwsoc2fpga. When cleared
108  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
109  * Secure transactions are allowed.
110  *
111  * Field Access Macros:
112  *
113  */
114 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_H2F_SCR_LWH2F_DMA register field. */
115 #define ALT_NOC_FW_H2F_SCR_LWH2F_DMA_LSB 8
116 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_H2F_SCR_LWH2F_DMA register field. */
117 #define ALT_NOC_FW_H2F_SCR_LWH2F_DMA_MSB 8
118 /* The width in bits of the ALT_NOC_FW_H2F_SCR_LWH2F_DMA register field. */
119 #define ALT_NOC_FW_H2F_SCR_LWH2F_DMA_WIDTH 1
120 /* The mask used to set the ALT_NOC_FW_H2F_SCR_LWH2F_DMA register field value. */
121 #define ALT_NOC_FW_H2F_SCR_LWH2F_DMA_SET_MSK 0x00000100
122 /* The mask used to clear the ALT_NOC_FW_H2F_SCR_LWH2F_DMA register field value. */
123 #define ALT_NOC_FW_H2F_SCR_LWH2F_DMA_CLR_MSK 0xfffffeff
124 /* The reset value of the ALT_NOC_FW_H2F_SCR_LWH2F_DMA register field. */
125 #define ALT_NOC_FW_H2F_SCR_LWH2F_DMA_RESET 0x0
126 /* Extracts the ALT_NOC_FW_H2F_SCR_LWH2F_DMA field value from a register. */
127 #define ALT_NOC_FW_H2F_SCR_LWH2F_DMA_GET(value) (((value) & 0x00000100) >> 8)
128 /* Produces a ALT_NOC_FW_H2F_SCR_LWH2F_DMA register field value suitable for setting the register. */
129 #define ALT_NOC_FW_H2F_SCR_LWH2F_DMA_SET(value) (((value) << 8) & 0x00000100)
130 
131 /*
132  * Field : emac0
133  *
134  * Security bit configuration for transactions from emac0 to lwsoc2fpga. When
135  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
136  * Non-Secure transactions are allowed.
137  *
138  * Field Access Macros:
139  *
140  */
141 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_H2F_SCR_LWH2F_EMAC0 register field. */
142 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC0_LSB 17
143 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_H2F_SCR_LWH2F_EMAC0 register field. */
144 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC0_MSB 17
145 /* The width in bits of the ALT_NOC_FW_H2F_SCR_LWH2F_EMAC0 register field. */
146 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC0_WIDTH 1
147 /* The mask used to set the ALT_NOC_FW_H2F_SCR_LWH2F_EMAC0 register field value. */
148 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC0_SET_MSK 0x00020000
149 /* The mask used to clear the ALT_NOC_FW_H2F_SCR_LWH2F_EMAC0 register field value. */
150 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC0_CLR_MSK 0xfffdffff
151 /* The reset value of the ALT_NOC_FW_H2F_SCR_LWH2F_EMAC0 register field. */
152 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC0_RESET 0x0
153 /* Extracts the ALT_NOC_FW_H2F_SCR_LWH2F_EMAC0 field value from a register. */
154 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC0_GET(value) (((value) & 0x00020000) >> 17)
155 /* Produces a ALT_NOC_FW_H2F_SCR_LWH2F_EMAC0 register field value suitable for setting the register. */
156 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC0_SET(value) (((value) << 17) & 0x00020000)
157 
158 /*
159  * Field : emac1
160  *
161  * Security bit configuration for transactions from emac1 to lwsoc2fpga. When
162  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
163  * Non-Secure transactions are allowed.
164  *
165  * Field Access Macros:
166  *
167  */
168 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_H2F_SCR_LWH2F_EMAC1 register field. */
169 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC1_LSB 18
170 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_H2F_SCR_LWH2F_EMAC1 register field. */
171 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC1_MSB 18
172 /* The width in bits of the ALT_NOC_FW_H2F_SCR_LWH2F_EMAC1 register field. */
173 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC1_WIDTH 1
174 /* The mask used to set the ALT_NOC_FW_H2F_SCR_LWH2F_EMAC1 register field value. */
175 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC1_SET_MSK 0x00040000
176 /* The mask used to clear the ALT_NOC_FW_H2F_SCR_LWH2F_EMAC1 register field value. */
177 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC1_CLR_MSK 0xfffbffff
178 /* The reset value of the ALT_NOC_FW_H2F_SCR_LWH2F_EMAC1 register field. */
179 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC1_RESET 0x0
180 /* Extracts the ALT_NOC_FW_H2F_SCR_LWH2F_EMAC1 field value from a register. */
181 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC1_GET(value) (((value) & 0x00040000) >> 18)
182 /* Produces a ALT_NOC_FW_H2F_SCR_LWH2F_EMAC1 register field value suitable for setting the register. */
183 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC1_SET(value) (((value) << 18) & 0x00040000)
184 
185 /*
186  * Field : emac2
187  *
188  * Security bit configuration for transactions from emac2 to lwsoc2fpga. When
189  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
190  * Non-Secure transactions are allowed.
191  *
192  * Field Access Macros:
193  *
194  */
195 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_H2F_SCR_LWH2F_EMAC2 register field. */
196 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC2_LSB 19
197 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_H2F_SCR_LWH2F_EMAC2 register field. */
198 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC2_MSB 19
199 /* The width in bits of the ALT_NOC_FW_H2F_SCR_LWH2F_EMAC2 register field. */
200 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC2_WIDTH 1
201 /* The mask used to set the ALT_NOC_FW_H2F_SCR_LWH2F_EMAC2 register field value. */
202 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC2_SET_MSK 0x00080000
203 /* The mask used to clear the ALT_NOC_FW_H2F_SCR_LWH2F_EMAC2 register field value. */
204 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC2_CLR_MSK 0xfff7ffff
205 /* The reset value of the ALT_NOC_FW_H2F_SCR_LWH2F_EMAC2 register field. */
206 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC2_RESET 0x0
207 /* Extracts the ALT_NOC_FW_H2F_SCR_LWH2F_EMAC2 field value from a register. */
208 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC2_GET(value) (((value) & 0x00080000) >> 19)
209 /* Produces a ALT_NOC_FW_H2F_SCR_LWH2F_EMAC2 register field value suitable for setting the register. */
210 #define ALT_NOC_FW_H2F_SCR_LWH2F_EMAC2_SET(value) (((value) << 19) & 0x00080000)
211 
212 /*
213  * Field : usb0
214  *
215  * Security bit configuration for transactions from usb0 to lwsoc2fpga. When
216  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
217  * Non-Secure transactions are allowed.
218  *
219  * Field Access Macros:
220  *
221  */
222 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_H2F_SCR_LWH2F_USB0 register field. */
223 #define ALT_NOC_FW_H2F_SCR_LWH2F_USB0_LSB 20
224 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_H2F_SCR_LWH2F_USB0 register field. */
225 #define ALT_NOC_FW_H2F_SCR_LWH2F_USB0_MSB 20
226 /* The width in bits of the ALT_NOC_FW_H2F_SCR_LWH2F_USB0 register field. */
227 #define ALT_NOC_FW_H2F_SCR_LWH2F_USB0_WIDTH 1
228 /* The mask used to set the ALT_NOC_FW_H2F_SCR_LWH2F_USB0 register field value. */
229 #define ALT_NOC_FW_H2F_SCR_LWH2F_USB0_SET_MSK 0x00100000
230 /* The mask used to clear the ALT_NOC_FW_H2F_SCR_LWH2F_USB0 register field value. */
231 #define ALT_NOC_FW_H2F_SCR_LWH2F_USB0_CLR_MSK 0xffefffff
232 /* The reset value of the ALT_NOC_FW_H2F_SCR_LWH2F_USB0 register field. */
233 #define ALT_NOC_FW_H2F_SCR_LWH2F_USB0_RESET 0x0
234 /* Extracts the ALT_NOC_FW_H2F_SCR_LWH2F_USB0 field value from a register. */
235 #define ALT_NOC_FW_H2F_SCR_LWH2F_USB0_GET(value) (((value) & 0x00100000) >> 20)
236 /* Produces a ALT_NOC_FW_H2F_SCR_LWH2F_USB0 register field value suitable for setting the register. */
237 #define ALT_NOC_FW_H2F_SCR_LWH2F_USB0_SET(value) (((value) << 20) & 0x00100000)
238 
239 /*
240  * Field : usb1
241  *
242  * Security bit configuration for transactions from usb1 to lwsoc2fpga. When
243  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
244  * Non-Secure transactions are allowed.
245  *
246  * Field Access Macros:
247  *
248  */
249 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_H2F_SCR_LWH2F_USB1 register field. */
250 #define ALT_NOC_FW_H2F_SCR_LWH2F_USB1_LSB 21
251 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_H2F_SCR_LWH2F_USB1 register field. */
252 #define ALT_NOC_FW_H2F_SCR_LWH2F_USB1_MSB 21
253 /* The width in bits of the ALT_NOC_FW_H2F_SCR_LWH2F_USB1 register field. */
254 #define ALT_NOC_FW_H2F_SCR_LWH2F_USB1_WIDTH 1
255 /* The mask used to set the ALT_NOC_FW_H2F_SCR_LWH2F_USB1 register field value. */
256 #define ALT_NOC_FW_H2F_SCR_LWH2F_USB1_SET_MSK 0x00200000
257 /* The mask used to clear the ALT_NOC_FW_H2F_SCR_LWH2F_USB1 register field value. */
258 #define ALT_NOC_FW_H2F_SCR_LWH2F_USB1_CLR_MSK 0xffdfffff
259 /* The reset value of the ALT_NOC_FW_H2F_SCR_LWH2F_USB1 register field. */
260 #define ALT_NOC_FW_H2F_SCR_LWH2F_USB1_RESET 0x0
261 /* Extracts the ALT_NOC_FW_H2F_SCR_LWH2F_USB1 field value from a register. */
262 #define ALT_NOC_FW_H2F_SCR_LWH2F_USB1_GET(value) (((value) & 0x00200000) >> 21)
263 /* Produces a ALT_NOC_FW_H2F_SCR_LWH2F_USB1 register field value suitable for setting the register. */
264 #define ALT_NOC_FW_H2F_SCR_LWH2F_USB1_SET(value) (((value) << 21) & 0x00200000)
265 
266 /*
267  * Field : sdmmc
268  *
269  * Security bit configuration for transactions from sdmmc to lwsoc2fpga. When
270  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
271  * Non-Secure transactions are allowed.
272  *
273  * Field Access Macros:
274  *
275  */
276 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_H2F_SCR_LWH2F_SDMMC register field. */
277 #define ALT_NOC_FW_H2F_SCR_LWH2F_SDMMC_LSB 22
278 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_H2F_SCR_LWH2F_SDMMC register field. */
279 #define ALT_NOC_FW_H2F_SCR_LWH2F_SDMMC_MSB 22
280 /* The width in bits of the ALT_NOC_FW_H2F_SCR_LWH2F_SDMMC register field. */
281 #define ALT_NOC_FW_H2F_SCR_LWH2F_SDMMC_WIDTH 1
282 /* The mask used to set the ALT_NOC_FW_H2F_SCR_LWH2F_SDMMC register field value. */
283 #define ALT_NOC_FW_H2F_SCR_LWH2F_SDMMC_SET_MSK 0x00400000
284 /* The mask used to clear the ALT_NOC_FW_H2F_SCR_LWH2F_SDMMC register field value. */
285 #define ALT_NOC_FW_H2F_SCR_LWH2F_SDMMC_CLR_MSK 0xffbfffff
286 /* The reset value of the ALT_NOC_FW_H2F_SCR_LWH2F_SDMMC register field. */
287 #define ALT_NOC_FW_H2F_SCR_LWH2F_SDMMC_RESET 0x0
288 /* Extracts the ALT_NOC_FW_H2F_SCR_LWH2F_SDMMC field value from a register. */
289 #define ALT_NOC_FW_H2F_SCR_LWH2F_SDMMC_GET(value) (((value) & 0x00400000) >> 22)
290 /* Produces a ALT_NOC_FW_H2F_SCR_LWH2F_SDMMC register field value suitable for setting the register. */
291 #define ALT_NOC_FW_H2F_SCR_LWH2F_SDMMC_SET(value) (((value) << 22) & 0x00400000)
292 
293 /*
294  * Field : nand
295  *
296  * Security bit configuration for transactions from nand to lwsoc2fpga. When
297  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
298  * Non-Secure transactions are allowed.
299  *
300  * Field Access Macros:
301  *
302  */
303 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_H2F_SCR_LWH2F_NAND register field. */
304 #define ALT_NOC_FW_H2F_SCR_LWH2F_NAND_LSB 23
305 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_H2F_SCR_LWH2F_NAND register field. */
306 #define ALT_NOC_FW_H2F_SCR_LWH2F_NAND_MSB 23
307 /* The width in bits of the ALT_NOC_FW_H2F_SCR_LWH2F_NAND register field. */
308 #define ALT_NOC_FW_H2F_SCR_LWH2F_NAND_WIDTH 1
309 /* The mask used to set the ALT_NOC_FW_H2F_SCR_LWH2F_NAND register field value. */
310 #define ALT_NOC_FW_H2F_SCR_LWH2F_NAND_SET_MSK 0x00800000
311 /* The mask used to clear the ALT_NOC_FW_H2F_SCR_LWH2F_NAND register field value. */
312 #define ALT_NOC_FW_H2F_SCR_LWH2F_NAND_CLR_MSK 0xff7fffff
313 /* The reset value of the ALT_NOC_FW_H2F_SCR_LWH2F_NAND register field. */
314 #define ALT_NOC_FW_H2F_SCR_LWH2F_NAND_RESET 0x0
315 /* Extracts the ALT_NOC_FW_H2F_SCR_LWH2F_NAND field value from a register. */
316 #define ALT_NOC_FW_H2F_SCR_LWH2F_NAND_GET(value) (((value) & 0x00800000) >> 23)
317 /* Produces a ALT_NOC_FW_H2F_SCR_LWH2F_NAND register field value suitable for setting the register. */
318 #define ALT_NOC_FW_H2F_SCR_LWH2F_NAND_SET(value) (((value) << 23) & 0x00800000)
319 
320 /*
321  * Field : ahb_ap
322  *
323  * Security bit configuration for transactions from ahb_ap to lwsoc2fpga. When
324  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
325  * Non-Secure transactions are allowed.
326  *
327  * Field Access Macros:
328  *
329  */
330 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_H2F_SCR_LWH2F_AHB_AP register field. */
331 #define ALT_NOC_FW_H2F_SCR_LWH2F_AHB_AP_LSB 24
332 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_H2F_SCR_LWH2F_AHB_AP register field. */
333 #define ALT_NOC_FW_H2F_SCR_LWH2F_AHB_AP_MSB 24
334 /* The width in bits of the ALT_NOC_FW_H2F_SCR_LWH2F_AHB_AP register field. */
335 #define ALT_NOC_FW_H2F_SCR_LWH2F_AHB_AP_WIDTH 1
336 /* The mask used to set the ALT_NOC_FW_H2F_SCR_LWH2F_AHB_AP register field value. */
337 #define ALT_NOC_FW_H2F_SCR_LWH2F_AHB_AP_SET_MSK 0x01000000
338 /* The mask used to clear the ALT_NOC_FW_H2F_SCR_LWH2F_AHB_AP register field value. */
339 #define ALT_NOC_FW_H2F_SCR_LWH2F_AHB_AP_CLR_MSK 0xfeffffff
340 /* The reset value of the ALT_NOC_FW_H2F_SCR_LWH2F_AHB_AP register field. */
341 #define ALT_NOC_FW_H2F_SCR_LWH2F_AHB_AP_RESET 0x0
342 /* Extracts the ALT_NOC_FW_H2F_SCR_LWH2F_AHB_AP field value from a register. */
343 #define ALT_NOC_FW_H2F_SCR_LWH2F_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
344 /* Produces a ALT_NOC_FW_H2F_SCR_LWH2F_AHB_AP register field value suitable for setting the register. */
345 #define ALT_NOC_FW_H2F_SCR_LWH2F_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
346 
347 /*
348  * Field : etr
349  *
350  * Security bit configuration for transactions from etr to lwsoc2fpga. When cleared
351  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
352  * Secure transactions are allowed.
353  *
354  * Field Access Macros:
355  *
356  */
357 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_H2F_SCR_LWH2F_ETR register field. */
358 #define ALT_NOC_FW_H2F_SCR_LWH2F_ETR_LSB 25
359 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_H2F_SCR_LWH2F_ETR register field. */
360 #define ALT_NOC_FW_H2F_SCR_LWH2F_ETR_MSB 25
361 /* The width in bits of the ALT_NOC_FW_H2F_SCR_LWH2F_ETR register field. */
362 #define ALT_NOC_FW_H2F_SCR_LWH2F_ETR_WIDTH 1
363 /* The mask used to set the ALT_NOC_FW_H2F_SCR_LWH2F_ETR register field value. */
364 #define ALT_NOC_FW_H2F_SCR_LWH2F_ETR_SET_MSK 0x02000000
365 /* The mask used to clear the ALT_NOC_FW_H2F_SCR_LWH2F_ETR register field value. */
366 #define ALT_NOC_FW_H2F_SCR_LWH2F_ETR_CLR_MSK 0xfdffffff
367 /* The reset value of the ALT_NOC_FW_H2F_SCR_LWH2F_ETR register field. */
368 #define ALT_NOC_FW_H2F_SCR_LWH2F_ETR_RESET 0x0
369 /* Extracts the ALT_NOC_FW_H2F_SCR_LWH2F_ETR field value from a register. */
370 #define ALT_NOC_FW_H2F_SCR_LWH2F_ETR_GET(value) (((value) & 0x02000000) >> 25)
371 /* Produces a ALT_NOC_FW_H2F_SCR_LWH2F_ETR register field value suitable for setting the register. */
372 #define ALT_NOC_FW_H2F_SCR_LWH2F_ETR_SET(value) (((value) << 25) & 0x02000000)
373 
374 #ifndef __ASSEMBLY__
375 /*
376  * WARNING: The C register and register group struct declarations are provided for
377  * convenience and illustrative purposes. They should, however, be used with
378  * caution as the C language standard provides no guarantees about the alignment or
379  * atomicity of device memory accesses. The recommended practice for writing
380  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
381  * alt_write_word() functions.
382  *
383  * The struct declaration for register ALT_NOC_FW_H2F_SCR_LWH2F.
384  */
385 struct ALT_NOC_FW_H2F_SCR_LWH2F_s
386 {
387  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_H2F_SCR_LWH2F_MPU_M0 */
388  uint32_t : 7; /* *UNDEFINED* */
389  uint32_t dma : 1; /* ALT_NOC_FW_H2F_SCR_LWH2F_DMA */
390  uint32_t : 8; /* *UNDEFINED* */
391  uint32_t emac0 : 1; /* ALT_NOC_FW_H2F_SCR_LWH2F_EMAC0 */
392  uint32_t emac1 : 1; /* ALT_NOC_FW_H2F_SCR_LWH2F_EMAC1 */
393  uint32_t emac2 : 1; /* ALT_NOC_FW_H2F_SCR_LWH2F_EMAC2 */
394  uint32_t usb0 : 1; /* ALT_NOC_FW_H2F_SCR_LWH2F_USB0 */
395  uint32_t usb1 : 1; /* ALT_NOC_FW_H2F_SCR_LWH2F_USB1 */
396  uint32_t sdmmc : 1; /* ALT_NOC_FW_H2F_SCR_LWH2F_SDMMC */
397  uint32_t nand : 1; /* ALT_NOC_FW_H2F_SCR_LWH2F_NAND */
398  uint32_t ahb_ap : 1; /* ALT_NOC_FW_H2F_SCR_LWH2F_AHB_AP */
399  uint32_t etr : 1; /* ALT_NOC_FW_H2F_SCR_LWH2F_ETR */
400  uint32_t : 6; /* *UNDEFINED* */
401 };
402 
403 /* The typedef declaration for register ALT_NOC_FW_H2F_SCR_LWH2F. */
404 typedef volatile struct ALT_NOC_FW_H2F_SCR_LWH2F_s ALT_NOC_FW_H2F_SCR_LWH2F_t;
405 #endif /* __ASSEMBLY__ */
406 
407 /* The reset value of the ALT_NOC_FW_H2F_SCR_LWH2F register. */
408 #define ALT_NOC_FW_H2F_SCR_LWH2F_RESET 0x00000000
409 /* The byte offset of the ALT_NOC_FW_H2F_SCR_LWH2F register from the beginning of the component. */
410 #define ALT_NOC_FW_H2F_SCR_LWH2F_OFST 0x0
411 
412 /*
413  * Register : soc2fpga
414  *
415  * Per-Master Security bit for SOC2FPGA
416  *
417  * Register Layout
418  *
419  * Bits | Access | Reset | Description
420  * :--------|:-------|:------|:------------------------------
421  * [0] | RW | 0x0 | ALT_NOC_FW_H2F_SCR_H2F_MPU_M0
422  * [7:1] | ??? | 0x0 | *UNDEFINED*
423  * [8] | RW | 0x0 | ALT_NOC_FW_H2F_SCR_H2F_DMA
424  * [16:9] | ??? | 0x0 | *UNDEFINED*
425  * [17] | RW | 0x0 | ALT_NOC_FW_H2F_SCR_H2F_EMAC0
426  * [18] | RW | 0x0 | ALT_NOC_FW_H2F_SCR_H2F_EMAC1
427  * [19] | RW | 0x0 | ALT_NOC_FW_H2F_SCR_H2F_EMAC2
428  * [20] | RW | 0x0 | ALT_NOC_FW_H2F_SCR_H2F_USB0
429  * [21] | RW | 0x0 | ALT_NOC_FW_H2F_SCR_H2F_USB1
430  * [22] | RW | 0x0 | ALT_NOC_FW_H2F_SCR_H2F_SDMMC
431  * [23] | RW | 0x0 | ALT_NOC_FW_H2F_SCR_H2F_NAND
432  * [24] | RW | 0x0 | ALT_NOC_FW_H2F_SCR_H2F_AHB_AP
433  * [25] | RW | 0x0 | ALT_NOC_FW_H2F_SCR_H2F_ETR
434  * [31:26] | ??? | 0x0 | *UNDEFINED*
435  *
436  */
437 /*
438  * Field : mpu_m0
439  *
440  * Security bit configuration for transactions from mpu0 to soc2fpga. When cleared
441  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
442  * Secure transactions are allowed.
443  *
444  * Field Access Macros:
445  *
446  */
447 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_H2F_SCR_H2F_MPU_M0 register field. */
448 #define ALT_NOC_FW_H2F_SCR_H2F_MPU_M0_LSB 0
449 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_H2F_SCR_H2F_MPU_M0 register field. */
450 #define ALT_NOC_FW_H2F_SCR_H2F_MPU_M0_MSB 0
451 /* The width in bits of the ALT_NOC_FW_H2F_SCR_H2F_MPU_M0 register field. */
452 #define ALT_NOC_FW_H2F_SCR_H2F_MPU_M0_WIDTH 1
453 /* The mask used to set the ALT_NOC_FW_H2F_SCR_H2F_MPU_M0 register field value. */
454 #define ALT_NOC_FW_H2F_SCR_H2F_MPU_M0_SET_MSK 0x00000001
455 /* The mask used to clear the ALT_NOC_FW_H2F_SCR_H2F_MPU_M0 register field value. */
456 #define ALT_NOC_FW_H2F_SCR_H2F_MPU_M0_CLR_MSK 0xfffffffe
457 /* The reset value of the ALT_NOC_FW_H2F_SCR_H2F_MPU_M0 register field. */
458 #define ALT_NOC_FW_H2F_SCR_H2F_MPU_M0_RESET 0x0
459 /* Extracts the ALT_NOC_FW_H2F_SCR_H2F_MPU_M0 field value from a register. */
460 #define ALT_NOC_FW_H2F_SCR_H2F_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
461 /* Produces a ALT_NOC_FW_H2F_SCR_H2F_MPU_M0 register field value suitable for setting the register. */
462 #define ALT_NOC_FW_H2F_SCR_H2F_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
463 
464 /*
465  * Field : dma
466  *
467  * Security bit configuration for transactions from dma to soc2fpga. When cleared
468  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
469  * Secure transactions are allowed.
470  *
471  * Field Access Macros:
472  *
473  */
474 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_H2F_SCR_H2F_DMA register field. */
475 #define ALT_NOC_FW_H2F_SCR_H2F_DMA_LSB 8
476 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_H2F_SCR_H2F_DMA register field. */
477 #define ALT_NOC_FW_H2F_SCR_H2F_DMA_MSB 8
478 /* The width in bits of the ALT_NOC_FW_H2F_SCR_H2F_DMA register field. */
479 #define ALT_NOC_FW_H2F_SCR_H2F_DMA_WIDTH 1
480 /* The mask used to set the ALT_NOC_FW_H2F_SCR_H2F_DMA register field value. */
481 #define ALT_NOC_FW_H2F_SCR_H2F_DMA_SET_MSK 0x00000100
482 /* The mask used to clear the ALT_NOC_FW_H2F_SCR_H2F_DMA register field value. */
483 #define ALT_NOC_FW_H2F_SCR_H2F_DMA_CLR_MSK 0xfffffeff
484 /* The reset value of the ALT_NOC_FW_H2F_SCR_H2F_DMA register field. */
485 #define ALT_NOC_FW_H2F_SCR_H2F_DMA_RESET 0x0
486 /* Extracts the ALT_NOC_FW_H2F_SCR_H2F_DMA field value from a register. */
487 #define ALT_NOC_FW_H2F_SCR_H2F_DMA_GET(value) (((value) & 0x00000100) >> 8)
488 /* Produces a ALT_NOC_FW_H2F_SCR_H2F_DMA register field value suitable for setting the register. */
489 #define ALT_NOC_FW_H2F_SCR_H2F_DMA_SET(value) (((value) << 8) & 0x00000100)
490 
491 /*
492  * Field : emac0
493  *
494  * Security bit configuration for transactions from emac0 to soc2fpga. When cleared
495  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
496  * Secure transactions are allowed.
497  *
498  * Field Access Macros:
499  *
500  */
501 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_H2F_SCR_H2F_EMAC0 register field. */
502 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC0_LSB 17
503 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_H2F_SCR_H2F_EMAC0 register field. */
504 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC0_MSB 17
505 /* The width in bits of the ALT_NOC_FW_H2F_SCR_H2F_EMAC0 register field. */
506 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC0_WIDTH 1
507 /* The mask used to set the ALT_NOC_FW_H2F_SCR_H2F_EMAC0 register field value. */
508 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC0_SET_MSK 0x00020000
509 /* The mask used to clear the ALT_NOC_FW_H2F_SCR_H2F_EMAC0 register field value. */
510 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC0_CLR_MSK 0xfffdffff
511 /* The reset value of the ALT_NOC_FW_H2F_SCR_H2F_EMAC0 register field. */
512 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC0_RESET 0x0
513 /* Extracts the ALT_NOC_FW_H2F_SCR_H2F_EMAC0 field value from a register. */
514 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC0_GET(value) (((value) & 0x00020000) >> 17)
515 /* Produces a ALT_NOC_FW_H2F_SCR_H2F_EMAC0 register field value suitable for setting the register. */
516 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC0_SET(value) (((value) << 17) & 0x00020000)
517 
518 /*
519  * Field : emac1
520  *
521  * Security bit configuration for transactions from emac1 to soc2fpga. When cleared
522  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
523  * Secure transactions are allowed.
524  *
525  * Field Access Macros:
526  *
527  */
528 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_H2F_SCR_H2F_EMAC1 register field. */
529 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC1_LSB 18
530 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_H2F_SCR_H2F_EMAC1 register field. */
531 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC1_MSB 18
532 /* The width in bits of the ALT_NOC_FW_H2F_SCR_H2F_EMAC1 register field. */
533 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC1_WIDTH 1
534 /* The mask used to set the ALT_NOC_FW_H2F_SCR_H2F_EMAC1 register field value. */
535 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC1_SET_MSK 0x00040000
536 /* The mask used to clear the ALT_NOC_FW_H2F_SCR_H2F_EMAC1 register field value. */
537 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC1_CLR_MSK 0xfffbffff
538 /* The reset value of the ALT_NOC_FW_H2F_SCR_H2F_EMAC1 register field. */
539 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC1_RESET 0x0
540 /* Extracts the ALT_NOC_FW_H2F_SCR_H2F_EMAC1 field value from a register. */
541 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC1_GET(value) (((value) & 0x00040000) >> 18)
542 /* Produces a ALT_NOC_FW_H2F_SCR_H2F_EMAC1 register field value suitable for setting the register. */
543 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC1_SET(value) (((value) << 18) & 0x00040000)
544 
545 /*
546  * Field : emac2
547  *
548  * Security bit configuration for transactions from emac2 to soc2fpga. When cleared
549  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
550  * Secure transactions are allowed.
551  *
552  * Field Access Macros:
553  *
554  */
555 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_H2F_SCR_H2F_EMAC2 register field. */
556 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC2_LSB 19
557 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_H2F_SCR_H2F_EMAC2 register field. */
558 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC2_MSB 19
559 /* The width in bits of the ALT_NOC_FW_H2F_SCR_H2F_EMAC2 register field. */
560 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC2_WIDTH 1
561 /* The mask used to set the ALT_NOC_FW_H2F_SCR_H2F_EMAC2 register field value. */
562 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC2_SET_MSK 0x00080000
563 /* The mask used to clear the ALT_NOC_FW_H2F_SCR_H2F_EMAC2 register field value. */
564 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC2_CLR_MSK 0xfff7ffff
565 /* The reset value of the ALT_NOC_FW_H2F_SCR_H2F_EMAC2 register field. */
566 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC2_RESET 0x0
567 /* Extracts the ALT_NOC_FW_H2F_SCR_H2F_EMAC2 field value from a register. */
568 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC2_GET(value) (((value) & 0x00080000) >> 19)
569 /* Produces a ALT_NOC_FW_H2F_SCR_H2F_EMAC2 register field value suitable for setting the register. */
570 #define ALT_NOC_FW_H2F_SCR_H2F_EMAC2_SET(value) (((value) << 19) & 0x00080000)
571 
572 /*
573  * Field : usb0
574  *
575  * Security bit configuration for transactions from usb0 to soc2fpga. When cleared
576  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
577  * Secure transactions are allowed.
578  *
579  * Field Access Macros:
580  *
581  */
582 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_H2F_SCR_H2F_USB0 register field. */
583 #define ALT_NOC_FW_H2F_SCR_H2F_USB0_LSB 20
584 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_H2F_SCR_H2F_USB0 register field. */
585 #define ALT_NOC_FW_H2F_SCR_H2F_USB0_MSB 20
586 /* The width in bits of the ALT_NOC_FW_H2F_SCR_H2F_USB0 register field. */
587 #define ALT_NOC_FW_H2F_SCR_H2F_USB0_WIDTH 1
588 /* The mask used to set the ALT_NOC_FW_H2F_SCR_H2F_USB0 register field value. */
589 #define ALT_NOC_FW_H2F_SCR_H2F_USB0_SET_MSK 0x00100000
590 /* The mask used to clear the ALT_NOC_FW_H2F_SCR_H2F_USB0 register field value. */
591 #define ALT_NOC_FW_H2F_SCR_H2F_USB0_CLR_MSK 0xffefffff
592 /* The reset value of the ALT_NOC_FW_H2F_SCR_H2F_USB0 register field. */
593 #define ALT_NOC_FW_H2F_SCR_H2F_USB0_RESET 0x0
594 /* Extracts the ALT_NOC_FW_H2F_SCR_H2F_USB0 field value from a register. */
595 #define ALT_NOC_FW_H2F_SCR_H2F_USB0_GET(value) (((value) & 0x00100000) >> 20)
596 /* Produces a ALT_NOC_FW_H2F_SCR_H2F_USB0 register field value suitable for setting the register. */
597 #define ALT_NOC_FW_H2F_SCR_H2F_USB0_SET(value) (((value) << 20) & 0x00100000)
598 
599 /*
600  * Field : usb1
601  *
602  * Security bit configuration for transactions from usb1 to soc2fpga. When cleared
603  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
604  * Secure transactions are allowed.
605  *
606  * Field Access Macros:
607  *
608  */
609 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_H2F_SCR_H2F_USB1 register field. */
610 #define ALT_NOC_FW_H2F_SCR_H2F_USB1_LSB 21
611 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_H2F_SCR_H2F_USB1 register field. */
612 #define ALT_NOC_FW_H2F_SCR_H2F_USB1_MSB 21
613 /* The width in bits of the ALT_NOC_FW_H2F_SCR_H2F_USB1 register field. */
614 #define ALT_NOC_FW_H2F_SCR_H2F_USB1_WIDTH 1
615 /* The mask used to set the ALT_NOC_FW_H2F_SCR_H2F_USB1 register field value. */
616 #define ALT_NOC_FW_H2F_SCR_H2F_USB1_SET_MSK 0x00200000
617 /* The mask used to clear the ALT_NOC_FW_H2F_SCR_H2F_USB1 register field value. */
618 #define ALT_NOC_FW_H2F_SCR_H2F_USB1_CLR_MSK 0xffdfffff
619 /* The reset value of the ALT_NOC_FW_H2F_SCR_H2F_USB1 register field. */
620 #define ALT_NOC_FW_H2F_SCR_H2F_USB1_RESET 0x0
621 /* Extracts the ALT_NOC_FW_H2F_SCR_H2F_USB1 field value from a register. */
622 #define ALT_NOC_FW_H2F_SCR_H2F_USB1_GET(value) (((value) & 0x00200000) >> 21)
623 /* Produces a ALT_NOC_FW_H2F_SCR_H2F_USB1 register field value suitable for setting the register. */
624 #define ALT_NOC_FW_H2F_SCR_H2F_USB1_SET(value) (((value) << 21) & 0x00200000)
625 
626 /*
627  * Field : sdmmc
628  *
629  * Security bit configuration for transactions from sdmmc to soc2fpga. When cleared
630  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
631  * Secure transactions are allowed.
632  *
633  * Field Access Macros:
634  *
635  */
636 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_H2F_SCR_H2F_SDMMC register field. */
637 #define ALT_NOC_FW_H2F_SCR_H2F_SDMMC_LSB 22
638 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_H2F_SCR_H2F_SDMMC register field. */
639 #define ALT_NOC_FW_H2F_SCR_H2F_SDMMC_MSB 22
640 /* The width in bits of the ALT_NOC_FW_H2F_SCR_H2F_SDMMC register field. */
641 #define ALT_NOC_FW_H2F_SCR_H2F_SDMMC_WIDTH 1
642 /* The mask used to set the ALT_NOC_FW_H2F_SCR_H2F_SDMMC register field value. */
643 #define ALT_NOC_FW_H2F_SCR_H2F_SDMMC_SET_MSK 0x00400000
644 /* The mask used to clear the ALT_NOC_FW_H2F_SCR_H2F_SDMMC register field value. */
645 #define ALT_NOC_FW_H2F_SCR_H2F_SDMMC_CLR_MSK 0xffbfffff
646 /* The reset value of the ALT_NOC_FW_H2F_SCR_H2F_SDMMC register field. */
647 #define ALT_NOC_FW_H2F_SCR_H2F_SDMMC_RESET 0x0
648 /* Extracts the ALT_NOC_FW_H2F_SCR_H2F_SDMMC field value from a register. */
649 #define ALT_NOC_FW_H2F_SCR_H2F_SDMMC_GET(value) (((value) & 0x00400000) >> 22)
650 /* Produces a ALT_NOC_FW_H2F_SCR_H2F_SDMMC register field value suitable for setting the register. */
651 #define ALT_NOC_FW_H2F_SCR_H2F_SDMMC_SET(value) (((value) << 22) & 0x00400000)
652 
653 /*
654  * Field : nand
655  *
656  * Security bit configuration for transactions from nand to soc2fpga. When cleared
657  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
658  * Secure transactions are allowed.
659  *
660  * Field Access Macros:
661  *
662  */
663 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_H2F_SCR_H2F_NAND register field. */
664 #define ALT_NOC_FW_H2F_SCR_H2F_NAND_LSB 23
665 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_H2F_SCR_H2F_NAND register field. */
666 #define ALT_NOC_FW_H2F_SCR_H2F_NAND_MSB 23
667 /* The width in bits of the ALT_NOC_FW_H2F_SCR_H2F_NAND register field. */
668 #define ALT_NOC_FW_H2F_SCR_H2F_NAND_WIDTH 1
669 /* The mask used to set the ALT_NOC_FW_H2F_SCR_H2F_NAND register field value. */
670 #define ALT_NOC_FW_H2F_SCR_H2F_NAND_SET_MSK 0x00800000
671 /* The mask used to clear the ALT_NOC_FW_H2F_SCR_H2F_NAND register field value. */
672 #define ALT_NOC_FW_H2F_SCR_H2F_NAND_CLR_MSK 0xff7fffff
673 /* The reset value of the ALT_NOC_FW_H2F_SCR_H2F_NAND register field. */
674 #define ALT_NOC_FW_H2F_SCR_H2F_NAND_RESET 0x0
675 /* Extracts the ALT_NOC_FW_H2F_SCR_H2F_NAND field value from a register. */
676 #define ALT_NOC_FW_H2F_SCR_H2F_NAND_GET(value) (((value) & 0x00800000) >> 23)
677 /* Produces a ALT_NOC_FW_H2F_SCR_H2F_NAND register field value suitable for setting the register. */
678 #define ALT_NOC_FW_H2F_SCR_H2F_NAND_SET(value) (((value) << 23) & 0x00800000)
679 
680 /*
681  * Field : ahb_ap
682  *
683  * Security bit configuration for transactions from ahb_ap to soc2fpga. When
684  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
685  * Non-Secure transactions are allowed.
686  *
687  * Field Access Macros:
688  *
689  */
690 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_H2F_SCR_H2F_AHB_AP register field. */
691 #define ALT_NOC_FW_H2F_SCR_H2F_AHB_AP_LSB 24
692 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_H2F_SCR_H2F_AHB_AP register field. */
693 #define ALT_NOC_FW_H2F_SCR_H2F_AHB_AP_MSB 24
694 /* The width in bits of the ALT_NOC_FW_H2F_SCR_H2F_AHB_AP register field. */
695 #define ALT_NOC_FW_H2F_SCR_H2F_AHB_AP_WIDTH 1
696 /* The mask used to set the ALT_NOC_FW_H2F_SCR_H2F_AHB_AP register field value. */
697 #define ALT_NOC_FW_H2F_SCR_H2F_AHB_AP_SET_MSK 0x01000000
698 /* The mask used to clear the ALT_NOC_FW_H2F_SCR_H2F_AHB_AP register field value. */
699 #define ALT_NOC_FW_H2F_SCR_H2F_AHB_AP_CLR_MSK 0xfeffffff
700 /* The reset value of the ALT_NOC_FW_H2F_SCR_H2F_AHB_AP register field. */
701 #define ALT_NOC_FW_H2F_SCR_H2F_AHB_AP_RESET 0x0
702 /* Extracts the ALT_NOC_FW_H2F_SCR_H2F_AHB_AP field value from a register. */
703 #define ALT_NOC_FW_H2F_SCR_H2F_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
704 /* Produces a ALT_NOC_FW_H2F_SCR_H2F_AHB_AP register field value suitable for setting the register. */
705 #define ALT_NOC_FW_H2F_SCR_H2F_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
706 
707 /*
708  * Field : etr
709  *
710  * Security bit configuration for transactions from etr to soc2fpga. When cleared
711  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
712  * Secure transactions are allowed.
713  *
714  * Field Access Macros:
715  *
716  */
717 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_H2F_SCR_H2F_ETR register field. */
718 #define ALT_NOC_FW_H2F_SCR_H2F_ETR_LSB 25
719 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_H2F_SCR_H2F_ETR register field. */
720 #define ALT_NOC_FW_H2F_SCR_H2F_ETR_MSB 25
721 /* The width in bits of the ALT_NOC_FW_H2F_SCR_H2F_ETR register field. */
722 #define ALT_NOC_FW_H2F_SCR_H2F_ETR_WIDTH 1
723 /* The mask used to set the ALT_NOC_FW_H2F_SCR_H2F_ETR register field value. */
724 #define ALT_NOC_FW_H2F_SCR_H2F_ETR_SET_MSK 0x02000000
725 /* The mask used to clear the ALT_NOC_FW_H2F_SCR_H2F_ETR register field value. */
726 #define ALT_NOC_FW_H2F_SCR_H2F_ETR_CLR_MSK 0xfdffffff
727 /* The reset value of the ALT_NOC_FW_H2F_SCR_H2F_ETR register field. */
728 #define ALT_NOC_FW_H2F_SCR_H2F_ETR_RESET 0x0
729 /* Extracts the ALT_NOC_FW_H2F_SCR_H2F_ETR field value from a register. */
730 #define ALT_NOC_FW_H2F_SCR_H2F_ETR_GET(value) (((value) & 0x02000000) >> 25)
731 /* Produces a ALT_NOC_FW_H2F_SCR_H2F_ETR register field value suitable for setting the register. */
732 #define ALT_NOC_FW_H2F_SCR_H2F_ETR_SET(value) (((value) << 25) & 0x02000000)
733 
734 #ifndef __ASSEMBLY__
735 /*
736  * WARNING: The C register and register group struct declarations are provided for
737  * convenience and illustrative purposes. They should, however, be used with
738  * caution as the C language standard provides no guarantees about the alignment or
739  * atomicity of device memory accesses. The recommended practice for writing
740  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
741  * alt_write_word() functions.
742  *
743  * The struct declaration for register ALT_NOC_FW_H2F_SCR_H2F.
744  */
745 struct ALT_NOC_FW_H2F_SCR_H2F_s
746 {
747  uint32_t mpu_m0 : 1; /* ALT_NOC_FW_H2F_SCR_H2F_MPU_M0 */
748  uint32_t : 7; /* *UNDEFINED* */
749  uint32_t dma : 1; /* ALT_NOC_FW_H2F_SCR_H2F_DMA */
750  uint32_t : 8; /* *UNDEFINED* */
751  uint32_t emac0 : 1; /* ALT_NOC_FW_H2F_SCR_H2F_EMAC0 */
752  uint32_t emac1 : 1; /* ALT_NOC_FW_H2F_SCR_H2F_EMAC1 */
753  uint32_t emac2 : 1; /* ALT_NOC_FW_H2F_SCR_H2F_EMAC2 */
754  uint32_t usb0 : 1; /* ALT_NOC_FW_H2F_SCR_H2F_USB0 */
755  uint32_t usb1 : 1; /* ALT_NOC_FW_H2F_SCR_H2F_USB1 */
756  uint32_t sdmmc : 1; /* ALT_NOC_FW_H2F_SCR_H2F_SDMMC */
757  uint32_t nand : 1; /* ALT_NOC_FW_H2F_SCR_H2F_NAND */
758  uint32_t ahb_ap : 1; /* ALT_NOC_FW_H2F_SCR_H2F_AHB_AP */
759  uint32_t etr : 1; /* ALT_NOC_FW_H2F_SCR_H2F_ETR */
760  uint32_t : 6; /* *UNDEFINED* */
761 };
762 
763 /* The typedef declaration for register ALT_NOC_FW_H2F_SCR_H2F. */
764 typedef volatile struct ALT_NOC_FW_H2F_SCR_H2F_s ALT_NOC_FW_H2F_SCR_H2F_t;
765 #endif /* __ASSEMBLY__ */
766 
767 /* The reset value of the ALT_NOC_FW_H2F_SCR_H2F register. */
768 #define ALT_NOC_FW_H2F_SCR_H2F_RESET 0x00000000
769 /* The byte offset of the ALT_NOC_FW_H2F_SCR_H2F register from the beginning of the component. */
770 #define ALT_NOC_FW_H2F_SCR_H2F_OFST 0x4
771 
772 #ifndef __ASSEMBLY__
773 /*
774  * WARNING: The C register and register group struct declarations are provided for
775  * convenience and illustrative purposes. They should, however, be used with
776  * caution as the C language standard provides no guarantees about the alignment or
777  * atomicity of device memory accesses. The recommended practice for writing
778  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
779  * alt_write_word() functions.
780  *
781  * The struct declaration for register group ALT_NOC_FW_H2F_SCR.
782  */
783 struct ALT_NOC_FW_H2F_SCR_s
784 {
785  ALT_NOC_FW_H2F_SCR_LWH2F_t lwsoc2fpga; /* ALT_NOC_FW_H2F_SCR_LWH2F */
786  ALT_NOC_FW_H2F_SCR_H2F_t soc2fpga; /* ALT_NOC_FW_H2F_SCR_H2F */
787  volatile uint32_t _pad_0x8_0x100[62]; /* *UNDEFINED* */
788 };
789 
790 /* The typedef declaration for register group ALT_NOC_FW_H2F_SCR. */
791 typedef volatile struct ALT_NOC_FW_H2F_SCR_s ALT_NOC_FW_H2F_SCR_t;
792 /* The struct declaration for the raw register contents of register group ALT_NOC_FW_H2F_SCR. */
793 struct ALT_NOC_FW_H2F_SCR_raw_s
794 {
795  volatile uint32_t lwsoc2fpga; /* ALT_NOC_FW_H2F_SCR_LWH2F */
796  volatile uint32_t soc2fpga; /* ALT_NOC_FW_H2F_SCR_H2F */
797  uint32_t _pad_0x8_0x100[62]; /* *UNDEFINED* */
798 };
799 
800 /* The typedef declaration for the raw register contents of register group ALT_NOC_FW_H2F_SCR. */
801 typedef volatile struct ALT_NOC_FW_H2F_SCR_raw_s ALT_NOC_FW_H2F_SCR_raw_t;
802 #endif /* __ASSEMBLY__ */
803 
804 
805 #ifdef __cplusplus
806 }
807 #endif /* __cplusplus */
808 #endif /* __ALT_SOCAL_NOC_FW_H2F_SCR_H__ */
809