Hardware Libraries  20.1
Arria 10 SoC Hardware Manager
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Groups
alt_l2_p310.h
Go to the documentation of this file.
1 /******************************************************************************
2 *
3 * Copyright 2013 Altera Corporation. All Rights Reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its contributors
16 * may be used to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 ******************************************************************************/
32 
33 /*
34  * $Id: //acds/rel/20.1/embedded/ip/hps/altera_hps/hwlib/include/alt_l2_p310.h#1 $
35  */
36 
41 #ifndef __ALT_L2_P310_H__
42 #define __ALT_L2_P310_H__
43 
44 #include <stdbool.h>
45 #include "socal/hps.h"
46 
47 #ifdef soc_a10
48 #define ALT_MPUL2_OFST ALT_L2_REGS_L2TYPE_ADDR
49 #endif
50 
51 #ifdef __cplusplus
52 extern "C"
53 {
54 #endif /* __cplusplus */
55 
56 /*****************************************************************************
57 / ARM Level 2 Cache Controller L2C-310 Register Interface
58 / These definitions should match the values given in DDI0246H_l2c310_r3p3_trm.pdf
59 / provided by ARM
60 *****************************************************************************/
61 
62 
63 /* Cache ID Register
64  * The Cache ID Registers is a read only register
65  * Bits Field Description
66  * :-------|:--------------------------|:-----------------------------------------
67  * [31:24] | Implementer | ID of IP provider. Should be 0x41 (ARM)
68  * [23:16] | Reserved | SBZ/RAZ
69  * [15:10] | Cache ID |
70  * [9:6] | Part Number |
71  * [5:0] | RTL release |
72  * Cache ID Register Address */
73 
74 #define ALT_L2_CACHE_ID_OFST 0x000
75 #define ALT_L2_CACHE_ID_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_ID_OFST)
76 /* Cache ID Register - Implementer Mask */
77 #define ALT_L2_CACHE_ID_IMPLEMENTER_MASK 0xFF000000
78 /* Cache ID Register - Cache ID Mask */
79 #define ALT_L2_CACHE_ID_CACHE_ID_MASK 0x0000FC00
80 /* Cache ID Register - Part Number Mask */
81 #define ALT_L2_CACHE_ID_PART_NUMBER_MASK 0x000003C0
82 /* Cache ID Register - RTL Relase Mask */
83 #define ALT_L2_CACHE_ID_RTL_RELEASE_MASK 0x0000003F
84 
85 #define ALT_L2_CACHE_TYPE_OFST 0x004
86 #define ALT_L2_CACHE_TYPE_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_ID_OFST)
87 
88 /* The Cache Control Register is a read and write register
89  * Bits Field Description
90  * :-------|:--------------------------|:-----------------------------------------
91  * [31:1] | Reservered | SBZ/RAZ
92  * [0] | L2 Cache Enable | */
93 
94 /* Cache Control Register Address */
95 #define ALT_L2_CACHE_REG1_CNTRL_OFST 0x100
96 #define ALT_L2_CACHE_REG1_CNTRL_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_CNTRL_OFST)
97 /* Cache Control Register - Enable */
98 #define ALT_L2_CACHE_REG1_CNTRL_DISABLE 0x0
99 #define ALT_L2_CACHE_REG1_CNTRL_ENABLE 0x1
100 #define ALT_L2_CACHE_REG1_CNTRL_ENABLE_MASK 0x1
101 
102 /* Aux Cache Control Register
103  * The Aux Cache Control Register is a read and write register
104  * Bits Field Description
105  * :-------|:--------------------------|:-----------------------------------------
106  * [31] | Reservered | SBZ/RAZ
107  * [30] | Early BRESP Enabled |
108  * [29] | Inst Prefetch Enable |
109  * [28] | Data Prefetch Enable |
110  * [27] | N/S Int Access Cntrl |
111  * [26] | N/S Lockdown Enable |
112  * [25] | Cache Replacement Policy |
113  * [24:23] | Force Write Allocate |
114  * [22] | Shared Attr Override En |
115  * [21] | Parity Enable |
116  * [20] | Event Monitor Bus Enable |
117  * [19:17] | Way Size |
118  * [16] | Associativity |
119  * [15:14] | Reserved |
120  * [13] | Shared Attribute Inv En |
121  * [12] | Exclusive Cache Config |
122  * [11] | Store Buffer Dev Limit En |
123  * [10] | High Priority for SO En |
124  * [9:1] | Reserved |
125  * [0] | Full Line of Zero En | */
126 
127 /* Aux Cache Control Register Address */
128 #define ALT_L2_CACHE_REG1_AUX_CNTRL_OFST 0x104
129 #define ALT_L2_CACHE_REG1_AUX_CNTRL_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_AUX_CNTRL_OFST)
130 #define ALT_L2_CACHE_REG1_AUX_CNTRL_EARLY_BRESP_EN_MASK 0x40000000
131 #define ALT_L2_CACHE_REG1_AUX_CNTRL_EARLY_BRESP_ENABLE 0x40000000
132 #define ALT_L2_CACHE_REG1_AUX_CNTRL_EARLY_BRESP_DISABLE 0
133 #define ALT_L2_CACHE_REG1_AUX_CNTRL_INST_PREFETCH_EN_MASK 0x20000000
134 #define ALT_L2_CACHE_REG1_AUX_CNTRL_INST_PREFETCH_ENABLE 0x20000000
135 #define ALT_L2_CACHE_REG1_AUX_CNTRL_INST_PREFETCH_DISABLE 0
136 #define ALT_L2_CACHE_REG1_AUX_CNTRL_DATA_PREFETCH_EN_MASK 0x10000000
137 #define ALT_L2_CACHE_REG1_AUX_CNTRL_DATA_PREFETCH_ENABLE 0x10000000
138 #define ALT_L2_CACHE_REG1_AUX_CNTRL_DATA_PREFETCH_DISABLE 0
139 #define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_INT_ACC_CNTRL_MASK 0x08000000
140 #define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_INT_ACC_CNTRL_ENABLE 0x08000000
141 #define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_INT_ACC_CNTRL_DISABLE 0
142 #define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_LOCKDOWN_EN_MASK 0x04000000
143 #define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_LOCKDOWN_ENABLE 0x04000000
144 #define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_LOCKDOWN_DISABLE 0
145 #define ALT_L2_CACHE_REG1_AUX_CNTRL_CACHE_REPL_POL_MASK 0x02000000
146 #define ALT_L2_CACHE_REG1_AUX_CNTRL_CACHE_REPL_POL_RANDOM 0
147 #define ALT_L2_CACHE_REG1_AUX_CNTRL_CACHE_REPL_POL_RR 0x02000000
148 #define ALT_L2_CACHE_REG1_AUX_CNTRL_FORCE_WRITE_ALLOC_MASK 0x01800000
149 #define ALT_L2_CACHE_REG1_AUX_CNTRL_FORCE_WRITE_ALLOC_AWCACHE 0
150 #define ALT_L2_CACHE_REG1_AUX_CNTRL_FORCE_WRITE_ALLOC_WA0 0x00800000
151 #define ALT_L2_CACHE_REG1_AUX_CNTRL_FORCE_WRITE_ALLOC_WA1 0x01000000
152 #define ALT_L2_CACHE_REG1_AUX_CNTRL_FORCE_WRITE_ALLOC_00 0x01800000
153 #define ALT_L2_CACHE_REG1_AUX_CNTRL_SHARED_ATTR_OVERRIDE_EN_MASK 0x00400000
154 #define ALT_L2_CACHE_REG1_AUX_CNTRL_SHARED_ATTR_OVERRIDE_ENABLE 0x00400000
155 #define ALT_L2_CACHE_REG1_AUX_CNTRL_SHARED_ATTR_OVERRIDE_DISABLE 0
156 #define ALT_L2_CACHE_REG1_AUX_CNTRL_PARITY_EN_MASK 0x00200000
157 #define ALT_L2_CACHE_REG1_AUX_CNTRL_PARITY_ENABLE 0x00200000
158 #define ALT_L2_CACHE_REG1_AUX_CNTRL_PARITY_DISABLE 0
159 #define ALT_L2_CACHE_REG1_AUX_CNTRL_EVENT_MNTR_BUS_EN_MASK 0x00100000
160 #define ALT_L2_CACHE_REG1_AUX_CNTRL_EVENT_MNTR_BUS_ENABLE 0x00100000
161 #define ALT_L2_CACHE_REG1_AUX_CNTRL_EVENT_MNTR_BUS_DISABLE 0
162 #define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_MASK 0x000E0000
163 #define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_16KB 0x00020000
164 #define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_32KB 0x00040000
165 #define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_64KB 0x00060000
166 #define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_128KB 0x00080000
167 #define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_256B 0x000A0000
168 #define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_512KB 0x000C0000
169 #define ALT_L2_CACHE_REG1_AUX_CNTRL_ASSOCIATIVITY_MASK 0x00010000
170 #define ALT_L2_CACHE_REG1_AUX_CNTRL_ASSOCIATIVITY_8WAY 0
171 #define ALT_L2_CACHE_REG1_AUX_CNTRL_ASSOCIATIVITY_16WAY 0x00010000
172 #define ALT_L2_CACHE_REG1_AUX_CNTRL_SHAR_ATTR_INV_EN_MASK 0x00002000
173 #define ALT_L2_CACHE_REG1_AUX_CNTRL_SHAR_ATTR_INV_ENABLE 0x00002000
174 #define ALT_L2_CACHE_REG1_AUX_CNTRL_SHAR_ATTR_INV_DISABLE 0
175 #define ALT_L2_CACHE_REG1_AUX_CNTRL_EXCL_CACHE_CFG_MASK 0x00001000
176 #define ALT_L2_CACHE_REG1_AUX_CNTRL_EXCL_CACHE_CFG_ENABLE 0x00001000
177 #define ALT_L2_CACHE_REG1_AUX_CNTRL_EXCL_CACHE_CFG_DISABLE 0
178 #define ALT_L2_CACHE_REG1_AUX_CNTRL_STOR_BUFF_DEV_LIM_EN_MASK 0x00000800
179 #define ALT_L2_CACHE_REG1_AUX_CNTRL_STOR_BUFF_DEV_LIM_ENABLE 0x00000800
180 #define ALT_L2_CACHE_REG1_AUX_CNTRL_STOR_BUFF_DEV_LIM_DISABLE 0
181 #define ALT_L2_CACHE_REG1_AUX_CNTRL_H_PRI_SO_DEV_RD_EN_MASK 0x00000400
182 #define ALT_L2_CACHE_REG1_AUX_CNTRL_H_PRI_SO_DEV_RD_ENABLE 0x00000400
183 #define ALT_L2_CACHE_REG1_AUX_CNTRL_H_PRI_SO_DEV_RD_DISABLE 0
184 #define ALT_L2_CACHE_REG1_AUX_CNTRL_FULL_LINE_0_EN_MASK 0x1
185 #define ALT_L2_CACHE_REG1_AUX_CNTRL_FULL_LINE_0_ENABLE 0x1
186 #define ALT_L2_CACHE_REG1_AUX_CNTRL_FULL_LINE_0_DISABLE 0
187 
188 /* Tag and Data RAM Latency Control Register
189  * The Tag and Data RAM Latency Control Register is a read and write register
190  * Bits Field Description
191  * :-------|:--------------------------|:-----------------------------------------
192  * [31:11] | Reservered | SBZ/RAZ
193  * [10:8] | RAM Write Access Latency |
194  * [7] | Reserved |
195  * [10:8] | RAM Read Access Latency |
196  * [3] | Reserved |
197  * [2:0] | RAM Setup Latency | */
198 
199 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_OFST 0x108
200 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_OFST)
201 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_MASK 0x00000700
202 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_1 0x00000000
203 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_2 0x00000100
204 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_3 0x00000200
205 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_4 0x00000300
206 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_5 0x00000400
207 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_6 0x00000500
208 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_7 0x00000600
209 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_8 0x00000700
210 
211 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_MASK 0x00000070
212 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_1 0x00000000
213 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_2 0x00000010
214 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_3 0x00000020
215 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_4 0x00000030
216 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_5 0x00000040
217 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_6 0x00000050
218 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_7 0x00000060
219 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_8 0x00000070
220 
221 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_MASK 0x00000007
222 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_1 0x00000000
223 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_2 0x00000001
224 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_3 0x00000002
225 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_4 0x00000003
226 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_5 0x00000004
227 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_6 0x00000005
228 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_7 0x00000006
229 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_8 0x00000007
230 
231 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_LSB 8
232 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_LSB 4
233 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_LSB 0
234 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_1 0x00000000
235 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_2 0x00000001
236 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_3 0x00000002
237 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_4 0x00000003
238 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_5 0x00000004
239 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_6 0x00000005
240 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_7 0x00000006
241 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_8 0x00000007
242 
243 #define ALT_L2_CACHE_REG1_DATA_RAM_CNTRL_OFST 0x10C
244 #define ALT_L2_CACHE_REG1_DATA_RAM_CNTRL_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_DATA_RAM_CNTRL_OFST)
245 
246 /* Event Counter Control Register
247  * Bits Field Description
248  * :-------|:--------------------------|:-----------------------------------------
249  * [31:3] | Reservered | SBZ/RAZ
250  * [2:1] | Counter Reset |
251  * [0] | Event Counter Enable | */
252 
253 #define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_OFST 0x200
254 #define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_EV_CNT_CNTRL_OFST)
255 
256 #define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_RESET_MASK 0x00000006
257 #define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_RESET_0 0x00000002
258 #define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_RESET_1 0x00000004
259 #define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_EN_MASK 1
260 /* Enable Counter */
261 #define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_ENABLE 1
262 #define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_DISABLE 0
263 
264 
265 /* Event Counter Configuration Registers
266  * Bits Field Description
267  * :-------|:--------------------------|:-----------------------------------------
268  * [31:6] | Reservered | SBZ/RAZ
269  * [5:2] | Counter Event Source |
270  * [1:0] | Event Counter Interupt En | */
271 
272 /* Event Counter Configuration Register Addresses */
273 #define ALT_L2_CACHE_REG2_EV_CNT1_CFG_OFST 0x204
274 #define ALT_L2_CACHE_REG2_EV_CNT1_CFG_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_EV_CNT1_CFG_OFST)
275 #define ALT_L2_CACHE_REG2_EV_CNT0_CFG_OFST 0x208
276 #define ALT_L2_CACHE_REG2_EV_CNT0_CFG_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_EV_CNT0_CFG_OFST)
277 
278 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_MASK 0x0000003C
279 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DISABLE 0x00000000
280 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_CO 0x00000004
281 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DRHIT 0x00000008
282 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DRREQ 0x0000000C
283 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DWHIT 0x00000010
284 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DWREQ 0x00000014
285 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DWTREQ 0x00000018
286 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_IRHIT 0x0000001C
287 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_IRREQ 0x00000020
288 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_WA 0x00000024
289 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_IPFALLOC 0x00000028
290 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_EPFHIT 0x0000002C
291 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_EPFALLOC 0x00000030
292 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_SRRCVD 0x00000034
293 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_SRCONF 0x00000038
294 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_EPFRCVD 0x0000003C
295 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_INT_MASK 0x3
296 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_INT_DISABLED 0
297 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_INT_ENABLE_INC 0x00000001
298 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_INT_ENABLE_OF 0x00000002
299 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_INT_GEN_DIS 0x00000003
300 
301 
302 /* Event Counter Registers */
303 #define ALT_L2_CACHE_REG2_EV_CNT1_OFST 0x20C
304 #define ALT_L2_CACHE_REG2_EV_CNT1_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_EV_CNT1_OFST)
305 #define ALT_L2_CACHE_REG2_EV_CNT0_OFST 0x210
306 #define ALT_L2_CACHE_REG2_EV_CNT0_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_EV_CNT0_OFST)
307 
308 /* Interrupt Registers. The following defines are used for the next several registers
309  * Bits Field Description
310  * :-------|:--------------------------|:-----------------------------------------
311  * [31:9] | Reservered | SBZ/RAZ
312  * [8] | DECERR |
313  * [7] | SLVERR |
314  * [6] | ERRRD |
315  * [5] | ERRRT |
316  * [4] | ERRWD |
317  * [3] | ERRWT |
318  * [2] | PARRD |
319  * [1] | PARRT |
320  * [0] | ECNTR | */
321 
322 #define ALT_L2_CACHE_REG2_INT_DECERR 0x100
323 #define ALT_L2_CACHE_REG2_INT_SLVERR 0x080
324 #define ALT_L2_CACHE_REG2_INT_ERRRD 0x040
325 #define ALT_L2_CACHE_REG2_INT_ERRRT 0x020
326 #define ALT_L2_CACHE_REG2_INT_ERRWD 0x010
327 #define ALT_L2_CACHE_REG2_INT_ERRWT 0x008
328 #define ALT_L2_CACHE_REG2_INT_PARRD 0x004
329 #define ALT_L2_CACHE_REG2_INT_PARRT 0x002
330 #define ALT_L2_CACHE_REG2_INT_ECNTR 0x001
331 
332 /* Interrupt Enable Mask Register
333  * See "Interrupt Registers" above */
334 #define ALT_L2_CACHE_REG2_INT_MASK_OFST 0x214
335 #define ALT_L2_CACHE_REG2_INT_MASK_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_INT_MASK_OFST)
336 
337 /* Interrupt Status Register (Should be RAW_STATUS & INT_MASK
338  * See "Interrupt Registers" above */
339 #define ALT_L2_CACHE_REG2_INT_MASK_STATUS_OFST 0x218
340 #define ALT_L2_CACHE_REG2_INT_MASK_STATUS_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_INT_MASK_STATUS_OFST)
341 
342 /* Interrupt Raw Status Register (Excludes Masks)
343  * See "Interrupt Registers" above */
344 #define ALT_L2_CACHE_REG2_INT_RAW_STATUS_OFST 0x21C
345 #define ALT_L2_CACHE_REG2_INT_RAW_STATUS_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_INT_RAW_STATUS_OFST)
346 
347 /* Interrupt Clear Status Register
348  * See "Interrupt Registers" above */
349 #define ALT_L2_CACHE_REG2_INT_CLEAR_OFST 0x220
350 #define ALT_L2_CACHE_REG2_INT_CLEAR_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_INT_CLEAR_OFST)
351 
352 /* PA Format
353  * Bits Field Description
354  * :-------|:--------------------------|:-----------------------------------------
355  * [31:12] | Tag |
356  * [11:5] | Index |
357  * [4:1] | Reserved |
358  * [0] | Complete | */
359 
360 /* Index or Way Format
361  * Bits Field Description
362  * :-------|:--------------------------|:-----------------------------------------
363  * [31:28] | Way |
364  * [27:12] | Reserved |
365  * [11:5] | Index |
366  * [4:1] | Reserved |
367  * [0] | Complete | */
368 
369 /* Way Format
370  * Bits Field Description
371  * :-------|:--------------------------|:-----------------------------------------
372  * [31:16] | Reserved |
373  * [15:0] | Way Bits | */
374 
375 /* Cache Sync Register
376  * Bits Field Description
377  * :-------|:--------------------------|:-----------------------------------------
378  * [31:1] | Reserved |
379  * [0] | Complete | */
380 #define ALT_L2_CACHE_REG7_CACHE_SYNC_OFST 0x730
381 #define ALT_L2_CACHE_REG7_CACHE_SYNC_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CACHE_SYNC_OFST)
382 
383 /* Invalidate Line by Physical Address
384  * See the "PA Format" above for description of the fields of this register */
385 #define ALT_L2_CACHE_REG7_INV_PA_OFST 0x770
386 #define ALT_L2_CACHE_REG7_INV_PA_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_INV_PA_OFST)
387 
388 /* Invalidate Line by Way
389  * See the "Way Format" above for description of the fields of this register */
390 #define ALT_L2_CACHE_REG7_INV_WAY_OFST 0x77C
391 #define ALT_L2_CACHE_REG7_INV_WAY_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_INV_WAY_OFST)
392 
393 /* Clean Line by Physical Address
394  * See the "PA Format" above for description of the fields of this register */
395 #define ALT_L2_CACHE_REG7_CLEAN_PA_OFST 0x7B0
396 #define ALT_L2_CACHE_REG7_CLEAN_PA_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_PA_OFST)
397 
398 /* Clean Line by Set/Way
399  * See the "Index or Way Format" above for a description of the fields of this register */
400 #define ALT_L2_CACHE_REG7_CLEAN_INDEX_OFST 0x7B8
401 #define ALT_L2_CACHE_REG7_CLEAN_INDEX_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_INDEX_OFST)
402 
403 /* Invalidate Line by Way
404  * See the "Way Format" above for description of the fields of this register */
405 #define ALT_L2_CACHE_REG7_CLEAN_WAY_OFST 0x7BC
406 #define ALT_L2_CACHE_REG7_CLEAN_WAY_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_WAY_OFST)
407 
408 /* Clean and Invalidate Line by Physical Address
409  * See the "PA Format" above for description of the fields of this register */
410 #define ALT_L2_CACHE_REG7_CLEAN_INV_PA_OFST 0x7F0
411 #define ALT_L2_CACHE_REG7_CLEAN_INV_PA_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_INV_PA_OFST)
412 
413 /* Clean and Invalidate Line by Set/Way
414  * See the "Index or Way Format" above for a description of the fields of this register */
415 #define ALT_L2_CACHE_REG7_CLEAN_INV_INDEX_OFST 0x7F8
416 #define ALT_L2_CACHE_REG7_CLEAN_INV_INDEX_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_INV_INDEX_OFST)
417 
418 /* Invalidate Line by Way
419  * See the "Way Format" above for description of the fields of this register */
420 #define ALT_L2_CACHE_REG7_CLEAN_INV_WAY_OFST 0x7FC
421 #define ALT_L2_CACHE_REG7_CLEAN_INV_WAY_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_INV_WAY_OFST)
422 
423 /* Lockdown Registers
424  * The format for each of these lockdown registers is the same
425  * Bits Field Description
426  * :-------|:--------------------------|:-----------------------------------------
427  * [31:16] | Reserved |
428  * [15:0] | Way Bits | */
429 
430 
431 #define ALT_L2_CACHE_REG9_D_LOCKDOWN_OFST(X) (0x900 + (X)*0x10)
432 #define ALT_L2_CACHE_REG9_D_LOCKDOWN_ADDR(X) (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN_OFST(X))
433 
434 #define ALT_L2_CACHE_REG9_I_LOCKDOWN_OFST(X) (0x904 + (X)*0x10)
435 #define ALT_L2_CACHE_REG9_I_LOCKDOWN_ADDR(X) (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN_OFST(X))
436 
437 #define ALT_L2_CACHE_REG9_D_LOCKDOWN0_OFST 0x900
438 #define ALT_L2_CACHE_REG9_D_LOCKDOWN0_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN0_OFST)
439 
440 #define ALT_L2_CACHE_REG9_I_LOCKDOWN0_OFST 0x904
441 #define ALT_L2_CACHE_REG9_I_LOCKDOWN0_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN0_OFST)
442 
443 #define ALT_L2_CACHE_REG9_D_LOCKDOWN1_OFST 0x908
444 #define ALT_L2_CACHE_REG9_D_LOCKDOWN1_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN1_OFST)
445 
446 #define ALT_L2_CACHE_REG9_I_LOCKDOWN1_OFST 0x90C
447 #define ALT_L2_CACHE_REG9_I_LOCKDOWN1_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN1_OFST)
448 
449 #define ALT_L2_CACHE_REG9_D_LOCKDOWN2_OFST 0x910
450 #define ALT_L2_CACHE_REG9_D_LOCKDOWN2_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN2_OFST)
451 
452 #define ALT_L2_CACHE_REG9_I_LOCKDOWN2_OFST 0x914
453 #define ALT_L2_CACHE_REG9_I_LOCKDOWN2_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN2_OFST)
454 
455 #define ALT_L2_CACHE_REG9_D_LOCKDOWN3_OFST 0x918
456 #define ALT_L2_CACHE_REG9_D_LOCKDOWN3_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN3_OFST)
457 
458 #define ALT_L2_CACHE_REG9_I_LOCKDOWN3_OFST 0x91C
459 #define ALT_L2_CACHE_REG9_I_LOCKDOWN3_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN3_OFST)
460 
461 #define ALT_L2_CACHE_REG9_D_LOCKDOWN4_OFST 0x920
462 #define ALT_L2_CACHE_REG9_D_LOCKDOWN4_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN4_OFST)
463 
464 #define ALT_L2_CACHE_REG9_I_LOCKDOWN4_OFST 0x924
465 #define ALT_L2_CACHE_REG9_I_LOCKDOWN4_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN4_OFST)
466 
467 #define ALT_L2_CACHE_REG9_D_LOCKDOWN5_OFST 0x928
468 #define ALT_L2_CACHE_REG9_D_LOCKDOWN5_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN5_OFST)
469 
470 #define ALT_L2_CACHE_REG9_I_LOCKDOWN5_OFST 0x92C
471 #define ALT_L2_CACHE_REG9_I_LOCKDOWN5_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN5_OFST)
472 
473 #define ALT_L2_CACHE_REG9_D_LOCKDOWN6_OFST 0x930
474 #define ALT_L2_CACHE_REG9_D_LOCKDOWN6_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN6_OFST)
475 
476 #define ALT_L2_CACHE_REG9_I_LOCKDOWN6_OFST 0x934
477 #define ALT_L2_CACHE_REG9_I_LOCKDOWN6_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN6_OFST)
478 
479 #define ALT_L2_CACHE_REG9_D_LOCKDOWN7_OFST 0x938
480 #define ALT_L2_CACHE_REG9_D_LOCKDOWN7_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN7_OFST)
481 
482 #define ALT_L2_CACHE_REG9_I_LOCKDOWN7_OFST 0x93C
483 #define ALT_L2_CACHE_REG9_I_LOCKDOWN7_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN7_OFST)
484 
485 /* Lockdown by Line Enable
486  * Bits Field Description
487  * :-------|:--------------------------|:-----------------------------------------
488  * [31:1] | Reserved |
489  * [0] | Enable | */
490 
491 #define ALT_L2_CACHE_REG9_LOCK_LINE_EN_OFST 0x950
492 #define ALT_L2_CACHE_REG9_LOCK_LINE_EN_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_LOCK_LINE_EN_OFST)
493 #define ALT_L2_CACHE_REG9_LOCK_LINE_EN_MASK 0x00000001
494 #define ALT_L2_CACHE_REG9_LOCK_LINE_ENABLE 0x00000001
495 #define ALT_L2_CACHE_REG9_LOCK_LINE_DISABLE 0
496 
497 #define ALT_L2_CACHE_REG9_UNLOCK_WAY_OFST 0x954
498 #define ALT_L2_CACHE_REG9_UNLOCK_WAY_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_UNLOCK_WAY_OFST)
499 
500 /* Address Filtering Start Register
501  * The Address Filtering Start Register is a read and write register.
502  * Bits Field Description
503  * :-------|:--------------------------|:-----------------------------------------
504  * [31:20] | address_filtering_start | Address filtering start address for
505  * | | bits [31:20] of the filtering address.
506  * [19:1] | Reserved | SBZ/RAZ
507  * [0] | address_filtering_enable | 0 - address filtering disabled
508  * | | 1 - address filtering enabled. */
509 
510 /* Address Filtering Start Register Address */
511 #define ALT_L2_CACHE_ADDR_FILTERING_START_OFST 0xC00
512 #define ALT_L2_CACHE_ADDR_FILTERING_START_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_OFST) + ALT_L2_CACHE_ADDR_FILTERING_START_OFST))
513 /* Address Filtering Start Register - Start Value Mask */
514 #define ALT_L2_CACHE_ADDR_FILTERING_START_ADDR_MASK 0xFFF00000
515 /* Address Filtering Start Register - Reset Start Address Value (1 MB) */
516 #define ALT_L2_CACHE_ADDR_FILTERING_START_RESET 0x100000
517 /* Address Filtering Start Register - Enable Flag Mask */
518 #define ALT_L2_CACHE_ADDR_FILTERING_ENABLE_MASK 0x00000001
519 /* Address Filtering Start Register - Reset Enable Flag Value (Enabled) */
520 #define ALT_L2_CACHE_ADDR_FILTERING_ENABLE_RESET 0x1
521 
522 /* Address Filtering End Register
523  * The Address Filtering End Register is a read and write register.
524  * Bits Field Description
525  * :-------|:--------------------------|:-----------------------------------------
526  * [31:20] | address_filtering_end | Address filtering end address for bits
527  * | | [31:20] of the filtering address.
528  * [19:0] | Reserved | SBZ/RAZ */
529 
530 /* Address Filtering End Register Address */
531 #define ALT_L2_CACHE_ADDR_FILTERING_END_OFST 0xC04
532 #define ALT_L2_CACHE_ADDR_FILTERING_END_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_OFST) + ALT_L2_CACHE_ADDR_FILTERING_END_OFST))
533 /* Address Filtering End Register - End Value Mask */
534 #define ALT_L2_CACHE_ADDR_FILTERING_END_ADDR_MASK 0xFFF00000
535 /* Address Filtering End Register - Reset End Address Value (3 GiB) */
536 #define ALT_L2_CACHE_ADDR_FILTERING_END_RESET 0xC0000000
537 
538 #ifdef __cplusplus
539 }
540 #endif /* __cplusplus */
541 #endif /* __ALT_L2_P310_H__ */