Hardware Libraries  20.1
Arria 10 SoC Abstration Layer
 All Groups
alt_l4wd.h
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32 
33 /* Altera - ALT_L4WD */
34 
35 #ifndef __ALT_SOCAL_L4WD_H__
36 #define __ALT_SOCAL_L4WD_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_L4WD
50  *
51  */
52 /*
53  * Register : wdt_cr
54  *
55  * Control Register
56  *
57  * Register Layout
58  *
59  * Bits | Access | Reset | Description
60  * :-------|:-------|:------|:-------------------
61  * [0] | RW | 0x0 | ALT_L4WD_CR_WDT_EN
62  * [1] | RW | 0x0 | ALT_L4WD_CR_RMOD
63  * [4:2] | RW | 0x0 | ALT_L4WD_CR_RPL
64  * [31:5] | ??? | 0x0 | *UNDEFINED*
65  *
66  */
67 /*
68  * Field : wdt_en
69  *
70  * WDT enable. Writable when the configuration parameter
71  *
72  * WDT_ALWAYS_EN = 0, otherwise, it is readable. This bit is
73  *
74  * used to enable and disable the DW_apb_wdt. When disabled, the
75  *
76  * counter does not decrement. Thus, no interrupts or system resets
77  *
78  * are generated. Once this bit has been enabled, it can be cleared
79  *
80  * only by a system reset.
81  *
82  * 0 = WDT disabled.
83  *
84  * 1 = WDT enabled.
85  *
86  * Field Enumeration Values:
87  *
88  * Enum | Value | Description
89  * :--------------------------|:------|:------------------
90  * ALT_L4WD_CR_WDT_EN_E_DISD | 0x0 | Watchdog disabled
91  * ALT_L4WD_CR_WDT_EN_E_END | 0x1 | Watchdog enabled
92  *
93  * Field Access Macros:
94  *
95  */
96 /*
97  * Enumerated value for register field ALT_L4WD_CR_WDT_EN
98  *
99  * Watchdog disabled
100  */
101 #define ALT_L4WD_CR_WDT_EN_E_DISD 0x0
102 /*
103  * Enumerated value for register field ALT_L4WD_CR_WDT_EN
104  *
105  * Watchdog enabled
106  */
107 #define ALT_L4WD_CR_WDT_EN_E_END 0x1
108 
109 /* The Least Significant Bit (LSB) position of the ALT_L4WD_CR_WDT_EN register field. */
110 #define ALT_L4WD_CR_WDT_EN_LSB 0
111 /* The Most Significant Bit (MSB) position of the ALT_L4WD_CR_WDT_EN register field. */
112 #define ALT_L4WD_CR_WDT_EN_MSB 0
113 /* The width in bits of the ALT_L4WD_CR_WDT_EN register field. */
114 #define ALT_L4WD_CR_WDT_EN_WIDTH 1
115 /* The mask used to set the ALT_L4WD_CR_WDT_EN register field value. */
116 #define ALT_L4WD_CR_WDT_EN_SET_MSK 0x00000001
117 /* The mask used to clear the ALT_L4WD_CR_WDT_EN register field value. */
118 #define ALT_L4WD_CR_WDT_EN_CLR_MSK 0xfffffffe
119 /* The reset value of the ALT_L4WD_CR_WDT_EN register field. */
120 #define ALT_L4WD_CR_WDT_EN_RESET 0x0
121 /* Extracts the ALT_L4WD_CR_WDT_EN field value from a register. */
122 #define ALT_L4WD_CR_WDT_EN_GET(value) (((value) & 0x00000001) >> 0)
123 /* Produces a ALT_L4WD_CR_WDT_EN register field value suitable for setting the register. */
124 #define ALT_L4WD_CR_WDT_EN_SET(value) (((value) << 0) & 0x00000001)
125 
126 /*
127  * Field : rmod
128  *
129  * Response mode. Writes have no effect when the parameter
130  *
131  * WDT_HC_RMOD = 1, thus this register becomes read-only.
132  *
133  * Selects the output response generated to a timeout.
134  *
135  * 0 = Generate a system reset.
136  *
137  * 1 = First generate an interrupt and if it is not cleared by the time
138  *
139  * a second timeout occurs then generate a system reset.
140  *
141  * Field Enumeration Values:
142  *
143  * Enum | Value | Description
144  * :--------------------------|:------|:----------------------------------------------
145  * ALT_L4WD_CR_RMOD_E_RST | 0x0 | Generate a warm reset request
146  * ALT_L4WD_CR_RMOD_E_IRQRST | 0x1 | First generate an interrupt, and if it is not
147  * : | | cleared by the time a second timeout occurs,
148  * : | | then generate a warm reset request.
149  *
150  * Field Access Macros:
151  *
152  */
153 /*
154  * Enumerated value for register field ALT_L4WD_CR_RMOD
155  *
156  * Generate a warm reset request
157  */
158 #define ALT_L4WD_CR_RMOD_E_RST 0x0
159 /*
160  * Enumerated value for register field ALT_L4WD_CR_RMOD
161  *
162  * First generate an interrupt, and if it is not cleared by the time a second
163  * timeout occurs, then generate a warm reset request.
164  */
165 #define ALT_L4WD_CR_RMOD_E_IRQRST 0x1
166 
167 /* The Least Significant Bit (LSB) position of the ALT_L4WD_CR_RMOD register field. */
168 #define ALT_L4WD_CR_RMOD_LSB 1
169 /* The Most Significant Bit (MSB) position of the ALT_L4WD_CR_RMOD register field. */
170 #define ALT_L4WD_CR_RMOD_MSB 1
171 /* The width in bits of the ALT_L4WD_CR_RMOD register field. */
172 #define ALT_L4WD_CR_RMOD_WIDTH 1
173 /* The mask used to set the ALT_L4WD_CR_RMOD register field value. */
174 #define ALT_L4WD_CR_RMOD_SET_MSK 0x00000002
175 /* The mask used to clear the ALT_L4WD_CR_RMOD register field value. */
176 #define ALT_L4WD_CR_RMOD_CLR_MSK 0xfffffffd
177 /* The reset value of the ALT_L4WD_CR_RMOD register field. */
178 #define ALT_L4WD_CR_RMOD_RESET 0x0
179 /* Extracts the ALT_L4WD_CR_RMOD field value from a register. */
180 #define ALT_L4WD_CR_RMOD_GET(value) (((value) & 0x00000002) >> 1)
181 /* Produces a ALT_L4WD_CR_RMOD register field value suitable for setting the register. */
182 #define ALT_L4WD_CR_RMOD_SET(value) (((value) << 1) & 0x00000002)
183 
184 /*
185  * Field : rpl
186  *
187  * Reset pulse length. Writes have no effect when the configuration parameter
188  *
189  * WDT_HC_RPL is 1, making the register bits read-only. This is used to select
190  *
191  * the number of pclk cycles for which the system reset stays asserted. The
192  *
193  * range of values available is 2 to 256 pclk cycles.
194  *
195  * 000 - 2 pclk cycles
196  *
197  * 001 - 4 pclk cycles
198  *
199  * 010 - 8 pclk cycles
200  *
201  * 011 - 16 pclk cycles
202  *
203  * 100 - 32 pclk cycles
204  *
205  * 101 - 64 pclk cycles
206  *
207  * 110 - 128 pclk cycles
208  *
209  * 111 - 256 pclk cycles
210  *
211  * Field Access Macros:
212  *
213  */
214 /* The Least Significant Bit (LSB) position of the ALT_L4WD_CR_RPL register field. */
215 #define ALT_L4WD_CR_RPL_LSB 2
216 /* The Most Significant Bit (MSB) position of the ALT_L4WD_CR_RPL register field. */
217 #define ALT_L4WD_CR_RPL_MSB 4
218 /* The width in bits of the ALT_L4WD_CR_RPL register field. */
219 #define ALT_L4WD_CR_RPL_WIDTH 3
220 /* The mask used to set the ALT_L4WD_CR_RPL register field value. */
221 #define ALT_L4WD_CR_RPL_SET_MSK 0x0000001c
222 /* The mask used to clear the ALT_L4WD_CR_RPL register field value. */
223 #define ALT_L4WD_CR_RPL_CLR_MSK 0xffffffe3
224 /* The reset value of the ALT_L4WD_CR_RPL register field. */
225 #define ALT_L4WD_CR_RPL_RESET 0x0
226 /* Extracts the ALT_L4WD_CR_RPL field value from a register. */
227 #define ALT_L4WD_CR_RPL_GET(value) (((value) & 0x0000001c) >> 2)
228 /* Produces a ALT_L4WD_CR_RPL register field value suitable for setting the register. */
229 #define ALT_L4WD_CR_RPL_SET(value) (((value) << 2) & 0x0000001c)
230 
231 #ifndef __ASSEMBLY__
232 /*
233  * WARNING: The C register and register group struct declarations are provided for
234  * convenience and illustrative purposes. They should, however, be used with
235  * caution as the C language standard provides no guarantees about the alignment or
236  * atomicity of device memory accesses. The recommended practice for writing
237  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
238  * alt_write_word() functions.
239  *
240  * The struct declaration for register ALT_L4WD_CR.
241  */
242 struct ALT_L4WD_CR_s
243 {
244  uint32_t wdt_en : 1; /* ALT_L4WD_CR_WDT_EN */
245  uint32_t rmod : 1; /* ALT_L4WD_CR_RMOD */
246  uint32_t rpl : 3; /* ALT_L4WD_CR_RPL */
247  uint32_t : 27; /* *UNDEFINED* */
248 };
249 
250 /* The typedef declaration for register ALT_L4WD_CR. */
251 typedef volatile struct ALT_L4WD_CR_s ALT_L4WD_CR_t;
252 #endif /* __ASSEMBLY__ */
253 
254 /* The reset value of the ALT_L4WD_CR register. */
255 #define ALT_L4WD_CR_RESET 0x00000000
256 /* The byte offset of the ALT_L4WD_CR register from the beginning of the component. */
257 #define ALT_L4WD_CR_OFST 0x0
258 /* The address of the ALT_L4WD_CR register. */
259 #define ALT_L4WD_CR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CR_OFST))
260 
261 /*
262  * Register : wdt_torr
263  *
264  * Timeout Range Register
265  *
266  * Register Layout
267  *
268  * Bits | Access | Reset | Description
269  * :-------|:-------|:------|:-----------------------
270  * [3:0] | RW | 0xf | ALT_L4WD_TORR_TOP
271  * [7:4] | RW | 0xf | ALT_L4WD_TORR_TOP_INIT
272  * [31:8] | R | 0x0 | ALT_L4WD_TORR_RSVD
273  *
274  */
275 /*
276  * Field : top
277  *
278  * Timeout period. Writes have no effect when the configuration parameter
279  *
280  * WDT_HC_TOP = 1, thus making this register read-only. This field is used
281  *
282  * to select the timeout period from which the watchdog counter restarts.
283  *
284  * A change of the timeout period takes effect only after the next counter
285  *
286  * restart (kick). The range of values is limited by the WDT_CNT_WIDTH. If
287  *
288  * TOP is programmed to select a range that is greater than the counter width,
289  *
290  * the timeout period is truncated to fit to the counter width. This affects
291  *
292  * only the non-user specified values as users are limited to these boundaries
293  *
294  * during configuration. The range of values available for a 32-bit watchdog
295  *
296  * counter are:
297  *
298  * Where i = TOP and
299  *
300  * t = timeout period
301  *
302  * For i = 0 to 15
303  *
304  * if WDT_USE_FIX_TOP==1
305  *
306  * t = 2(16 + i)
307  *
308  * else
309  *
310  * t = WDT_USER_TOP_(i)
311  *
312  * Field Enumeration Values:
313  *
314  * Enum | Value | Description
315  * :----------------------------|:------|:------------------------------
316  * ALT_L4WD_TORR_TOP_E_TMO64K | 0x0 | Timeout = 65536 osc1_clk
317  * ALT_L4WD_TORR_TOP_E_TMO128K | 0x1 | Timeout = 131072 osc1_clk
318  * ALT_L4WD_TORR_TOP_E_TMO256K | 0x2 | Timeout = 262144 osc1_clk
319  * ALT_L4WD_TORR_TOP_E_TMO512K | 0x3 | Timeout = 524288 osc1_clk
320  * ALT_L4WD_TORR_TOP_E_TMO1M | 0x4 | Timeout = 1048576 osc1_clk
321  * ALT_L4WD_TORR_TOP_E_TMO2M | 0x5 | Timeout = 2097152 osc1_clk
322  * ALT_L4WD_TORR_TOP_E_TMO4M | 0x6 | Timeout = 4194304 osc1_clk
323  * ALT_L4WD_TORR_TOP_E_TMO8M | 0x7 | Timeout = 8388608 osc1_clk
324  * ALT_L4WD_TORR_TOP_E_TMO16M | 0x8 | Timeout = 16777216 osc1_clk
325  * ALT_L4WD_TORR_TOP_E_TMO32M | 0x9 | Timeout = 33554432 osc1_clk
326  * ALT_L4WD_TORR_TOP_E_TMO64M | 0xa | Timeout = 67108864 osc1_clk
327  * ALT_L4WD_TORR_TOP_E_TMO128M | 0xb | Timeout = 134217728 osc1_clk
328  * ALT_L4WD_TORR_TOP_E_TMO256M | 0xc | Timeout = 268435456 osc1_clk
329  * ALT_L4WD_TORR_TOP_E_TMO512M | 0xd | Timeout = 536870912 osc1_clk
330  * ALT_L4WD_TORR_TOP_E_TMO1G | 0xe | Timeout = 1073741824 osc1_clk
331  * ALT_L4WD_TORR_TOP_E_TMO2G | 0xf | Timeout = 2147483648 osc1_clk
332  *
333  * Field Access Macros:
334  *
335  */
336 /*
337  * Enumerated value for register field ALT_L4WD_TORR_TOP
338  *
339  * Timeout = 65536 osc1_clk
340  */
341 #define ALT_L4WD_TORR_TOP_E_TMO64K 0x0
342 /*
343  * Enumerated value for register field ALT_L4WD_TORR_TOP
344  *
345  * Timeout = 131072 osc1_clk
346  */
347 #define ALT_L4WD_TORR_TOP_E_TMO128K 0x1
348 /*
349  * Enumerated value for register field ALT_L4WD_TORR_TOP
350  *
351  * Timeout = 262144 osc1_clk
352  */
353 #define ALT_L4WD_TORR_TOP_E_TMO256K 0x2
354 /*
355  * Enumerated value for register field ALT_L4WD_TORR_TOP
356  *
357  * Timeout = 524288 osc1_clk
358  */
359 #define ALT_L4WD_TORR_TOP_E_TMO512K 0x3
360 /*
361  * Enumerated value for register field ALT_L4WD_TORR_TOP
362  *
363  * Timeout = 1048576 osc1_clk
364  */
365 #define ALT_L4WD_TORR_TOP_E_TMO1M 0x4
366 /*
367  * Enumerated value for register field ALT_L4WD_TORR_TOP
368  *
369  * Timeout = 2097152 osc1_clk
370  */
371 #define ALT_L4WD_TORR_TOP_E_TMO2M 0x5
372 /*
373  * Enumerated value for register field ALT_L4WD_TORR_TOP
374  *
375  * Timeout = 4194304 osc1_clk
376  */
377 #define ALT_L4WD_TORR_TOP_E_TMO4M 0x6
378 /*
379  * Enumerated value for register field ALT_L4WD_TORR_TOP
380  *
381  * Timeout = 8388608 osc1_clk
382  */
383 #define ALT_L4WD_TORR_TOP_E_TMO8M 0x7
384 /*
385  * Enumerated value for register field ALT_L4WD_TORR_TOP
386  *
387  * Timeout = 16777216 osc1_clk
388  */
389 #define ALT_L4WD_TORR_TOP_E_TMO16M 0x8
390 /*
391  * Enumerated value for register field ALT_L4WD_TORR_TOP
392  *
393  * Timeout = 33554432 osc1_clk
394  */
395 #define ALT_L4WD_TORR_TOP_E_TMO32M 0x9
396 /*
397  * Enumerated value for register field ALT_L4WD_TORR_TOP
398  *
399  * Timeout = 67108864 osc1_clk
400  */
401 #define ALT_L4WD_TORR_TOP_E_TMO64M 0xa
402 /*
403  * Enumerated value for register field ALT_L4WD_TORR_TOP
404  *
405  * Timeout = 134217728 osc1_clk
406  */
407 #define ALT_L4WD_TORR_TOP_E_TMO128M 0xb
408 /*
409  * Enumerated value for register field ALT_L4WD_TORR_TOP
410  *
411  * Timeout = 268435456 osc1_clk
412  */
413 #define ALT_L4WD_TORR_TOP_E_TMO256M 0xc
414 /*
415  * Enumerated value for register field ALT_L4WD_TORR_TOP
416  *
417  * Timeout = 536870912 osc1_clk
418  */
419 #define ALT_L4WD_TORR_TOP_E_TMO512M 0xd
420 /*
421  * Enumerated value for register field ALT_L4WD_TORR_TOP
422  *
423  * Timeout = 1073741824 osc1_clk
424  */
425 #define ALT_L4WD_TORR_TOP_E_TMO1G 0xe
426 /*
427  * Enumerated value for register field ALT_L4WD_TORR_TOP
428  *
429  * Timeout = 2147483648 osc1_clk
430  */
431 #define ALT_L4WD_TORR_TOP_E_TMO2G 0xf
432 
433 /* The Least Significant Bit (LSB) position of the ALT_L4WD_TORR_TOP register field. */
434 #define ALT_L4WD_TORR_TOP_LSB 0
435 /* The Most Significant Bit (MSB) position of the ALT_L4WD_TORR_TOP register field. */
436 #define ALT_L4WD_TORR_TOP_MSB 3
437 /* The width in bits of the ALT_L4WD_TORR_TOP register field. */
438 #define ALT_L4WD_TORR_TOP_WIDTH 4
439 /* The mask used to set the ALT_L4WD_TORR_TOP register field value. */
440 #define ALT_L4WD_TORR_TOP_SET_MSK 0x0000000f
441 /* The mask used to clear the ALT_L4WD_TORR_TOP register field value. */
442 #define ALT_L4WD_TORR_TOP_CLR_MSK 0xfffffff0
443 /* The reset value of the ALT_L4WD_TORR_TOP register field. */
444 #define ALT_L4WD_TORR_TOP_RESET 0xf
445 /* Extracts the ALT_L4WD_TORR_TOP field value from a register. */
446 #define ALT_L4WD_TORR_TOP_GET(value) (((value) & 0x0000000f) >> 0)
447 /* Produces a ALT_L4WD_TORR_TOP register field value suitable for setting the register. */
448 #define ALT_L4WD_TORR_TOP_SET(value) (((value) << 0) & 0x0000000f)
449 
450 /*
451  * Field : top_init
452  *
453  * Timeout period for initialization.
454  *
455  * Writes to these register bits have no effect when the configuration
456  *
457  * parameter WDT_HC_TOP = 1 or WDT_ALWAYS_EN = 1. Used to
458  *
459  * select the timeout period that the watchdog counter restarts from for
460  *
461  * the first counter restart (kick). This register should be written after
462  *
463  * reset and before the WDT is enabled.
464  *
465  * A change of the TOP_INIT is seen only once the WDT has been
466  *
467  * enabled, and any change after the first kick is not seen as subsequent
468  *
469  * kicks use the period specified by the TOP bits.
470  *
471  * The range of values is limited by the WDT_CNT_WIDTH. If
472  *
473  * TOP_INIT is programmed to select a range that is greater than the
474  *
475  * counter width, the timeout period is truncated to fit to the counter
476  *
477  * width. This affects only the non-user specified values as users are
478  *
479  * limited to these boundaries during configuration.
480  *
481  * The range of values available for a 32-bit watchdog counter are:
482  *
483  * Where i = TOP_INIT and
484  *
485  * t = timeout period
486  *
487  * For i = 0 to 15
488  *
489  * if WDT_USE_FIX_TOP==1
490  *
491  * t = 2(16 + i)
492  *
493  * else
494  *
495  * t = WDT_USER_TOP_INIT_(i)
496  *
497  * NOTE: These bits exist only when the configuration parameter
498  *
499  * WDT_DUAL_TOP = 1, otherwise, they are fixed at zero.
500  *
501  * Field Enumeration Values:
502  *
503  * Enum | Value | Description
504  * :---------------------------------|:------|:------------------------------
505  * ALT_L4WD_TORR_TOP_INIT_E_TMO64K | 0x0 | Timeout = 65536 osc1_clk
506  * ALT_L4WD_TORR_TOP_INIT_E_TMO128K | 0x1 | Timeout = 131072 osc1_clk
507  * ALT_L4WD_TORR_TOP_INIT_E_TMO256K | 0x2 | Timeout = 262144 osc1_clk
508  * ALT_L4WD_TORR_TOP_INIT_E_TMO512K | 0x3 | Timeout = 524288 osc1_clk
509  * ALT_L4WD_TORR_TOP_INIT_E_TMO1M | 0x4 | Timeout = 1048576 osc1_clk
510  * ALT_L4WD_TORR_TOP_INIT_E_TMO2M | 0x5 | Timeout = 2097152 osc1_clk
511  * ALT_L4WD_TORR_TOP_INIT_E_TMO4M | 0x6 | Timeout = 4194304 osc1_clk
512  * ALT_L4WD_TORR_TOP_INIT_E_TMO8M | 0x7 | Timeout = 8388608 osc1_clk
513  * ALT_L4WD_TORR_TOP_INIT_E_TMO16M | 0x8 | Timeout = 16777216 osc1_clk
514  * ALT_L4WD_TORR_TOP_INIT_E_TMO32M | 0x9 | Timeout = 33554432 osc1_clk
515  * ALT_L4WD_TORR_TOP_INIT_E_TMO64M | 0xa | Timeout = 67108864 osc1_clk
516  * ALT_L4WD_TORR_TOP_INIT_E_TMO128M | 0xb | Timeout = 134217728 osc1_clk
517  * ALT_L4WD_TORR_TOP_INIT_E_TMO256M | 0xc | Timeout = 268435456 osc1_clk
518  * ALT_L4WD_TORR_TOP_INIT_E_TMO512M | 0xd | Timeout = 536870912 osc1_clk
519  * ALT_L4WD_TORR_TOP_INIT_E_TMO1G | 0xe | Timeout = 1073741824 osc1_clk
520  * ALT_L4WD_TORR_TOP_INIT_E_TMO2G | 0xf | Timeout = 2147483648 osc1_clk
521  *
522  * Field Access Macros:
523  *
524  */
525 /*
526  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
527  *
528  * Timeout = 65536 osc1_clk
529  */
530 #define ALT_L4WD_TORR_TOP_INIT_E_TMO64K 0x0
531 /*
532  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
533  *
534  * Timeout = 131072 osc1_clk
535  */
536 #define ALT_L4WD_TORR_TOP_INIT_E_TMO128K 0x1
537 /*
538  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
539  *
540  * Timeout = 262144 osc1_clk
541  */
542 #define ALT_L4WD_TORR_TOP_INIT_E_TMO256K 0x2
543 /*
544  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
545  *
546  * Timeout = 524288 osc1_clk
547  */
548 #define ALT_L4WD_TORR_TOP_INIT_E_TMO512K 0x3
549 /*
550  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
551  *
552  * Timeout = 1048576 osc1_clk
553  */
554 #define ALT_L4WD_TORR_TOP_INIT_E_TMO1M 0x4
555 /*
556  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
557  *
558  * Timeout = 2097152 osc1_clk
559  */
560 #define ALT_L4WD_TORR_TOP_INIT_E_TMO2M 0x5
561 /*
562  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
563  *
564  * Timeout = 4194304 osc1_clk
565  */
566 #define ALT_L4WD_TORR_TOP_INIT_E_TMO4M 0x6
567 /*
568  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
569  *
570  * Timeout = 8388608 osc1_clk
571  */
572 #define ALT_L4WD_TORR_TOP_INIT_E_TMO8M 0x7
573 /*
574  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
575  *
576  * Timeout = 16777216 osc1_clk
577  */
578 #define ALT_L4WD_TORR_TOP_INIT_E_TMO16M 0x8
579 /*
580  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
581  *
582  * Timeout = 33554432 osc1_clk
583  */
584 #define ALT_L4WD_TORR_TOP_INIT_E_TMO32M 0x9
585 /*
586  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
587  *
588  * Timeout = 67108864 osc1_clk
589  */
590 #define ALT_L4WD_TORR_TOP_INIT_E_TMO64M 0xa
591 /*
592  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
593  *
594  * Timeout = 134217728 osc1_clk
595  */
596 #define ALT_L4WD_TORR_TOP_INIT_E_TMO128M 0xb
597 /*
598  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
599  *
600  * Timeout = 268435456 osc1_clk
601  */
602 #define ALT_L4WD_TORR_TOP_INIT_E_TMO256M 0xc
603 /*
604  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
605  *
606  * Timeout = 536870912 osc1_clk
607  */
608 #define ALT_L4WD_TORR_TOP_INIT_E_TMO512M 0xd
609 /*
610  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
611  *
612  * Timeout = 1073741824 osc1_clk
613  */
614 #define ALT_L4WD_TORR_TOP_INIT_E_TMO1G 0xe
615 /*
616  * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT
617  *
618  * Timeout = 2147483648 osc1_clk
619  */
620 #define ALT_L4WD_TORR_TOP_INIT_E_TMO2G 0xf
621 
622 /* The Least Significant Bit (LSB) position of the ALT_L4WD_TORR_TOP_INIT register field. */
623 #define ALT_L4WD_TORR_TOP_INIT_LSB 4
624 /* The Most Significant Bit (MSB) position of the ALT_L4WD_TORR_TOP_INIT register field. */
625 #define ALT_L4WD_TORR_TOP_INIT_MSB 7
626 /* The width in bits of the ALT_L4WD_TORR_TOP_INIT register field. */
627 #define ALT_L4WD_TORR_TOP_INIT_WIDTH 4
628 /* The mask used to set the ALT_L4WD_TORR_TOP_INIT register field value. */
629 #define ALT_L4WD_TORR_TOP_INIT_SET_MSK 0x000000f0
630 /* The mask used to clear the ALT_L4WD_TORR_TOP_INIT register field value. */
631 #define ALT_L4WD_TORR_TOP_INIT_CLR_MSK 0xffffff0f
632 /* The reset value of the ALT_L4WD_TORR_TOP_INIT register field. */
633 #define ALT_L4WD_TORR_TOP_INIT_RESET 0xf
634 /* Extracts the ALT_L4WD_TORR_TOP_INIT field value from a register. */
635 #define ALT_L4WD_TORR_TOP_INIT_GET(value) (((value) & 0x000000f0) >> 4)
636 /* Produces a ALT_L4WD_TORR_TOP_INIT register field value suitable for setting the register. */
637 #define ALT_L4WD_TORR_TOP_INIT_SET(value) (((value) << 4) & 0x000000f0)
638 
639 /*
640  * Field : reserved
641  *
642  * Reserved and read as 0.
643  *
644  * Field Access Macros:
645  *
646  */
647 /* The Least Significant Bit (LSB) position of the ALT_L4WD_TORR_RSVD register field. */
648 #define ALT_L4WD_TORR_RSVD_LSB 8
649 /* The Most Significant Bit (MSB) position of the ALT_L4WD_TORR_RSVD register field. */
650 #define ALT_L4WD_TORR_RSVD_MSB 31
651 /* The width in bits of the ALT_L4WD_TORR_RSVD register field. */
652 #define ALT_L4WD_TORR_RSVD_WIDTH 24
653 /* The mask used to set the ALT_L4WD_TORR_RSVD register field value. */
654 #define ALT_L4WD_TORR_RSVD_SET_MSK 0xffffff00
655 /* The mask used to clear the ALT_L4WD_TORR_RSVD register field value. */
656 #define ALT_L4WD_TORR_RSVD_CLR_MSK 0x000000ff
657 /* The reset value of the ALT_L4WD_TORR_RSVD register field. */
658 #define ALT_L4WD_TORR_RSVD_RESET 0x0
659 /* Extracts the ALT_L4WD_TORR_RSVD field value from a register. */
660 #define ALT_L4WD_TORR_RSVD_GET(value) (((value) & 0xffffff00) >> 8)
661 /* Produces a ALT_L4WD_TORR_RSVD register field value suitable for setting the register. */
662 #define ALT_L4WD_TORR_RSVD_SET(value) (((value) << 8) & 0xffffff00)
663 
664 #ifndef __ASSEMBLY__
665 /*
666  * WARNING: The C register and register group struct declarations are provided for
667  * convenience and illustrative purposes. They should, however, be used with
668  * caution as the C language standard provides no guarantees about the alignment or
669  * atomicity of device memory accesses. The recommended practice for writing
670  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
671  * alt_write_word() functions.
672  *
673  * The struct declaration for register ALT_L4WD_TORR.
674  */
675 struct ALT_L4WD_TORR_s
676 {
677  uint32_t top : 4; /* ALT_L4WD_TORR_TOP */
678  uint32_t top_init : 4; /* ALT_L4WD_TORR_TOP_INIT */
679  const uint32_t reserved : 24; /* ALT_L4WD_TORR_RSVD */
680 };
681 
682 /* The typedef declaration for register ALT_L4WD_TORR. */
683 typedef volatile struct ALT_L4WD_TORR_s ALT_L4WD_TORR_t;
684 #endif /* __ASSEMBLY__ */
685 
686 /* The reset value of the ALT_L4WD_TORR register. */
687 #define ALT_L4WD_TORR_RESET 0x000000ff
688 /* The byte offset of the ALT_L4WD_TORR register from the beginning of the component. */
689 #define ALT_L4WD_TORR_OFST 0x4
690 /* The address of the ALT_L4WD_TORR register. */
691 #define ALT_L4WD_TORR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_TORR_OFST))
692 
693 /*
694  * Register : wdt_ccvr
695  *
696  * Current Counter Value Register.
697  *
698  * Register Layout
699  *
700  * Bits | Access | Reset | Description
701  * :-------|:-------|:-----------|:-----------------------
702  * [31:0] | R | 0x7fffffff | ALT_L4WD_CCVR_WDT_CCVR
703  *
704  */
705 /*
706  * Field : wdt_ccvr
707  *
708  * This register, when read, is the current value of the internal
709  *
710  * counter. This value is read coherently when ever it is read,
711  *
712  * which is relevant when the APB_DATA_WIDTH is less than the
713  *
714  * counter width.
715  *
716  * Field Access Macros:
717  *
718  */
719 /* The Least Significant Bit (LSB) position of the ALT_L4WD_CCVR_WDT_CCVR register field. */
720 #define ALT_L4WD_CCVR_WDT_CCVR_LSB 0
721 /* The Most Significant Bit (MSB) position of the ALT_L4WD_CCVR_WDT_CCVR register field. */
722 #define ALT_L4WD_CCVR_WDT_CCVR_MSB 31
723 /* The width in bits of the ALT_L4WD_CCVR_WDT_CCVR register field. */
724 #define ALT_L4WD_CCVR_WDT_CCVR_WIDTH 32
725 /* The mask used to set the ALT_L4WD_CCVR_WDT_CCVR register field value. */
726 #define ALT_L4WD_CCVR_WDT_CCVR_SET_MSK 0xffffffff
727 /* The mask used to clear the ALT_L4WD_CCVR_WDT_CCVR register field value. */
728 #define ALT_L4WD_CCVR_WDT_CCVR_CLR_MSK 0x00000000
729 /* The reset value of the ALT_L4WD_CCVR_WDT_CCVR register field. */
730 #define ALT_L4WD_CCVR_WDT_CCVR_RESET 0x7fffffff
731 /* Extracts the ALT_L4WD_CCVR_WDT_CCVR field value from a register. */
732 #define ALT_L4WD_CCVR_WDT_CCVR_GET(value) (((value) & 0xffffffff) >> 0)
733 /* Produces a ALT_L4WD_CCVR_WDT_CCVR register field value suitable for setting the register. */
734 #define ALT_L4WD_CCVR_WDT_CCVR_SET(value) (((value) << 0) & 0xffffffff)
735 
736 #ifndef __ASSEMBLY__
737 /*
738  * WARNING: The C register and register group struct declarations are provided for
739  * convenience and illustrative purposes. They should, however, be used with
740  * caution as the C language standard provides no guarantees about the alignment or
741  * atomicity of device memory accesses. The recommended practice for writing
742  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
743  * alt_write_word() functions.
744  *
745  * The struct declaration for register ALT_L4WD_CCVR.
746  */
747 struct ALT_L4WD_CCVR_s
748 {
749  const uint32_t wdt_ccvr : 32; /* ALT_L4WD_CCVR_WDT_CCVR */
750 };
751 
752 /* The typedef declaration for register ALT_L4WD_CCVR. */
753 typedef volatile struct ALT_L4WD_CCVR_s ALT_L4WD_CCVR_t;
754 #endif /* __ASSEMBLY__ */
755 
756 /* The reset value of the ALT_L4WD_CCVR register. */
757 #define ALT_L4WD_CCVR_RESET 0x7fffffff
758 /* The byte offset of the ALT_L4WD_CCVR register from the beginning of the component. */
759 #define ALT_L4WD_CCVR_OFST 0x8
760 /* The address of the ALT_L4WD_CCVR register. */
761 #define ALT_L4WD_CCVR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CCVR_OFST))
762 
763 /*
764  * Register : wdt_crr
765  *
766  * Counter Restart Register.
767  *
768  * Register Layout
769  *
770  * Bits | Access | Reset | Description
771  * :-------|:-------|:------|:---------------------
772  * [7:0] | W | 0x0 | ALT_L4WD_CRR_WDT_CRR
773  * [31:8] | ??? | 0x0 | *UNDEFINED*
774  *
775  */
776 /*
777  * Field : wdt_crr
778  *
779  * This register is used to restart the WDT counter. As a safety feature to
780  *
781  * prevent accidental restarts, the value 0x76 must be written. A restart also
782  *
783  * clears the WDT interrupt. Reading this register returns zero.
784  *
785  * Field Enumeration Values:
786  *
787  * Enum | Value | Description
788  * :----------------------------|:------|:-----------------------------------------
789  * ALT_L4WD_CRR_WDT_CRR_E_KICK | 0x76 | Value to write to restart watchdog timer
790  *
791  * Field Access Macros:
792  *
793  */
794 /*
795  * Enumerated value for register field ALT_L4WD_CRR_WDT_CRR
796  *
797  * Value to write to restart watchdog timer
798  */
799 #define ALT_L4WD_CRR_WDT_CRR_E_KICK 0x76
800 
801 /* The Least Significant Bit (LSB) position of the ALT_L4WD_CRR_WDT_CRR register field. */
802 #define ALT_L4WD_CRR_WDT_CRR_LSB 0
803 /* The Most Significant Bit (MSB) position of the ALT_L4WD_CRR_WDT_CRR register field. */
804 #define ALT_L4WD_CRR_WDT_CRR_MSB 7
805 /* The width in bits of the ALT_L4WD_CRR_WDT_CRR register field. */
806 #define ALT_L4WD_CRR_WDT_CRR_WIDTH 8
807 /* The mask used to set the ALT_L4WD_CRR_WDT_CRR register field value. */
808 #define ALT_L4WD_CRR_WDT_CRR_SET_MSK 0x000000ff
809 /* The mask used to clear the ALT_L4WD_CRR_WDT_CRR register field value. */
810 #define ALT_L4WD_CRR_WDT_CRR_CLR_MSK 0xffffff00
811 /* The reset value of the ALT_L4WD_CRR_WDT_CRR register field. */
812 #define ALT_L4WD_CRR_WDT_CRR_RESET 0x0
813 /* Extracts the ALT_L4WD_CRR_WDT_CRR field value from a register. */
814 #define ALT_L4WD_CRR_WDT_CRR_GET(value) (((value) & 0x000000ff) >> 0)
815 /* Produces a ALT_L4WD_CRR_WDT_CRR register field value suitable for setting the register. */
816 #define ALT_L4WD_CRR_WDT_CRR_SET(value) (((value) << 0) & 0x000000ff)
817 
818 #ifndef __ASSEMBLY__
819 /*
820  * WARNING: The C register and register group struct declarations are provided for
821  * convenience and illustrative purposes. They should, however, be used with
822  * caution as the C language standard provides no guarantees about the alignment or
823  * atomicity of device memory accesses. The recommended practice for writing
824  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
825  * alt_write_word() functions.
826  *
827  * The struct declaration for register ALT_L4WD_CRR.
828  */
829 struct ALT_L4WD_CRR_s
830 {
831  uint32_t wdt_crr : 8; /* ALT_L4WD_CRR_WDT_CRR */
832  uint32_t : 24; /* *UNDEFINED* */
833 };
834 
835 /* The typedef declaration for register ALT_L4WD_CRR. */
836 typedef volatile struct ALT_L4WD_CRR_s ALT_L4WD_CRR_t;
837 #endif /* __ASSEMBLY__ */
838 
839 /* The reset value of the ALT_L4WD_CRR register. */
840 #define ALT_L4WD_CRR_RESET 0x00000000
841 /* The byte offset of the ALT_L4WD_CRR register from the beginning of the component. */
842 #define ALT_L4WD_CRR_OFST 0xc
843 /* The address of the ALT_L4WD_CRR register. */
844 #define ALT_L4WD_CRR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CRR_OFST))
845 
846 /*
847  * Register : wdt_stat
848  *
849  * Interrupt Status Register.
850  *
851  * Register Layout
852  *
853  * Bits | Access | Reset | Description
854  * :-------|:-------|:------|:-----------------------
855  * [0] | R | 0x0 | ALT_L4WD_STAT_WDT_STAT
856  * [31:1] | ??? | 0x0 | *UNDEFINED*
857  *
858  */
859 /*
860  * Field : wdt_stat
861  *
862  * This register shows the interrupt status of the WDT.
863  *
864  * 1 = Interrupt is active regardless of polarity.
865  *
866  * 0 = Interrupt is inactive.
867  *
868  * Field Enumeration Values:
869  *
870  * Enum | Value | Description
871  * :-------------------------------|:------|:----------------------
872  * ALT_L4WD_STAT_WDT_STAT_E_INACT | 0x0 | Interrupt is inactive
873  * ALT_L4WD_STAT_WDT_STAT_E_ACT | 0x1 | Interrupt is active
874  *
875  * Field Access Macros:
876  *
877  */
878 /*
879  * Enumerated value for register field ALT_L4WD_STAT_WDT_STAT
880  *
881  * Interrupt is inactive
882  */
883 #define ALT_L4WD_STAT_WDT_STAT_E_INACT 0x0
884 /*
885  * Enumerated value for register field ALT_L4WD_STAT_WDT_STAT
886  *
887  * Interrupt is active
888  */
889 #define ALT_L4WD_STAT_WDT_STAT_E_ACT 0x1
890 
891 /* The Least Significant Bit (LSB) position of the ALT_L4WD_STAT_WDT_STAT register field. */
892 #define ALT_L4WD_STAT_WDT_STAT_LSB 0
893 /* The Most Significant Bit (MSB) position of the ALT_L4WD_STAT_WDT_STAT register field. */
894 #define ALT_L4WD_STAT_WDT_STAT_MSB 0
895 /* The width in bits of the ALT_L4WD_STAT_WDT_STAT register field. */
896 #define ALT_L4WD_STAT_WDT_STAT_WIDTH 1
897 /* The mask used to set the ALT_L4WD_STAT_WDT_STAT register field value. */
898 #define ALT_L4WD_STAT_WDT_STAT_SET_MSK 0x00000001
899 /* The mask used to clear the ALT_L4WD_STAT_WDT_STAT register field value. */
900 #define ALT_L4WD_STAT_WDT_STAT_CLR_MSK 0xfffffffe
901 /* The reset value of the ALT_L4WD_STAT_WDT_STAT register field. */
902 #define ALT_L4WD_STAT_WDT_STAT_RESET 0x0
903 /* Extracts the ALT_L4WD_STAT_WDT_STAT field value from a register. */
904 #define ALT_L4WD_STAT_WDT_STAT_GET(value) (((value) & 0x00000001) >> 0)
905 /* Produces a ALT_L4WD_STAT_WDT_STAT register field value suitable for setting the register. */
906 #define ALT_L4WD_STAT_WDT_STAT_SET(value) (((value) << 0) & 0x00000001)
907 
908 #ifndef __ASSEMBLY__
909 /*
910  * WARNING: The C register and register group struct declarations are provided for
911  * convenience and illustrative purposes. They should, however, be used with
912  * caution as the C language standard provides no guarantees about the alignment or
913  * atomicity of device memory accesses. The recommended practice for writing
914  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
915  * alt_write_word() functions.
916  *
917  * The struct declaration for register ALT_L4WD_STAT.
918  */
919 struct ALT_L4WD_STAT_s
920 {
921  const uint32_t wdt_stat : 1; /* ALT_L4WD_STAT_WDT_STAT */
922  uint32_t : 31; /* *UNDEFINED* */
923 };
924 
925 /* The typedef declaration for register ALT_L4WD_STAT. */
926 typedef volatile struct ALT_L4WD_STAT_s ALT_L4WD_STAT_t;
927 #endif /* __ASSEMBLY__ */
928 
929 /* The reset value of the ALT_L4WD_STAT register. */
930 #define ALT_L4WD_STAT_RESET 0x00000000
931 /* The byte offset of the ALT_L4WD_STAT register from the beginning of the component. */
932 #define ALT_L4WD_STAT_OFST 0x10
933 /* The address of the ALT_L4WD_STAT register. */
934 #define ALT_L4WD_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_STAT_OFST))
935 
936 /*
937  * Register : wdt_eoi
938  *
939  * Interrupt Clear Register.
940  *
941  * Register Layout
942  *
943  * Bits | Access | Reset | Description
944  * :-------|:-------|:------|:---------------------
945  * [0] | R | 0x0 | ALT_L4WD_EOI_WDT_EOI
946  * [31:1] | ??? | 0x0 | *UNDEFINED*
947  *
948  */
949 /*
950  * Field : wdt_eoi
951  *
952  * Clears the watchdog interrupt. This can be used to clear the interrupt
953  *
954  * without restarting the watchdog counter.
955  *
956  * Field Access Macros:
957  *
958  */
959 /* The Least Significant Bit (LSB) position of the ALT_L4WD_EOI_WDT_EOI register field. */
960 #define ALT_L4WD_EOI_WDT_EOI_LSB 0
961 /* The Most Significant Bit (MSB) position of the ALT_L4WD_EOI_WDT_EOI register field. */
962 #define ALT_L4WD_EOI_WDT_EOI_MSB 0
963 /* The width in bits of the ALT_L4WD_EOI_WDT_EOI register field. */
964 #define ALT_L4WD_EOI_WDT_EOI_WIDTH 1
965 /* The mask used to set the ALT_L4WD_EOI_WDT_EOI register field value. */
966 #define ALT_L4WD_EOI_WDT_EOI_SET_MSK 0x00000001
967 /* The mask used to clear the ALT_L4WD_EOI_WDT_EOI register field value. */
968 #define ALT_L4WD_EOI_WDT_EOI_CLR_MSK 0xfffffffe
969 /* The reset value of the ALT_L4WD_EOI_WDT_EOI register field. */
970 #define ALT_L4WD_EOI_WDT_EOI_RESET 0x0
971 /* Extracts the ALT_L4WD_EOI_WDT_EOI field value from a register. */
972 #define ALT_L4WD_EOI_WDT_EOI_GET(value) (((value) & 0x00000001) >> 0)
973 /* Produces a ALT_L4WD_EOI_WDT_EOI register field value suitable for setting the register. */
974 #define ALT_L4WD_EOI_WDT_EOI_SET(value) (((value) << 0) & 0x00000001)
975 
976 #ifndef __ASSEMBLY__
977 /*
978  * WARNING: The C register and register group struct declarations are provided for
979  * convenience and illustrative purposes. They should, however, be used with
980  * caution as the C language standard provides no guarantees about the alignment or
981  * atomicity of device memory accesses. The recommended practice for writing
982  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
983  * alt_write_word() functions.
984  *
985  * The struct declaration for register ALT_L4WD_EOI.
986  */
987 struct ALT_L4WD_EOI_s
988 {
989  const uint32_t wdt_eoi : 1; /* ALT_L4WD_EOI_WDT_EOI */
990  uint32_t : 31; /* *UNDEFINED* */
991 };
992 
993 /* The typedef declaration for register ALT_L4WD_EOI. */
994 typedef volatile struct ALT_L4WD_EOI_s ALT_L4WD_EOI_t;
995 #endif /* __ASSEMBLY__ */
996 
997 /* The reset value of the ALT_L4WD_EOI register. */
998 #define ALT_L4WD_EOI_RESET 0x00000000
999 /* The byte offset of the ALT_L4WD_EOI register from the beginning of the component. */
1000 #define ALT_L4WD_EOI_OFST 0x14
1001 /* The address of the ALT_L4WD_EOI register. */
1002 #define ALT_L4WD_EOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_EOI_OFST))
1003 
1004 /*
1005  * Register : cp_wdt_user_top_max
1006  *
1007  * Component Parameters Register 5
1008  *
1009  * Register Layout
1010  *
1011  * Bits | Access | Reset | Description
1012  * :-------|:-------|:------|:-----------------------
1013  * [31:0] | R | 0x0 | Component Parameters 5
1014  *
1015  */
1016 /*
1017  * Field : Component Parameters 5 - cp_wdt_user_top_max
1018  *
1019  * Upper limit of Timeout Period parameters.
1020  *
1021  * Field Access Macros:
1022  *
1023  */
1024 /* The Least Significant Bit (LSB) position of the ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL register field. */
1025 #define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_LSB 0
1026 /* The Most Significant Bit (MSB) position of the ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL register field. */
1027 #define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_MSB 31
1028 /* The width in bits of the ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL register field. */
1029 #define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_WIDTH 32
1030 /* The mask used to set the ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL register field value. */
1031 #define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_SET_MSK 0xffffffff
1032 /* The mask used to clear the ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL register field value. */
1033 #define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_CLR_MSK 0x00000000
1034 /* The reset value of the ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL register field. */
1035 #define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_RESET 0x0
1036 /* Extracts the ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL field value from a register. */
1037 #define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_GET(value) (((value) & 0xffffffff) >> 0)
1038 /* Produces a ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL register field value suitable for setting the register. */
1039 #define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_SET(value) (((value) << 0) & 0xffffffff)
1040 
1041 #ifndef __ASSEMBLY__
1042 /*
1043  * WARNING: The C register and register group struct declarations are provided for
1044  * convenience and illustrative purposes. They should, however, be used with
1045  * caution as the C language standard provides no guarantees about the alignment or
1046  * atomicity of device memory accesses. The recommended practice for writing
1047  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1048  * alt_write_word() functions.
1049  *
1050  * The struct declaration for register ALT_L4WD_CP_WDT_USER_TOP_MAX.
1051  */
1052 struct ALT_L4WD_CP_WDT_USER_TOP_MAX_s
1053 {
1054  const uint32_t cp_wdt_user_top_max : 32; /* Component Parameters 5 */
1055 };
1056 
1057 /* The typedef declaration for register ALT_L4WD_CP_WDT_USER_TOP_MAX. */
1058 typedef volatile struct ALT_L4WD_CP_WDT_USER_TOP_MAX_s ALT_L4WD_CP_WDT_USER_TOP_MAX_t;
1059 #endif /* __ASSEMBLY__ */
1060 
1061 /* The reset value of the ALT_L4WD_CP_WDT_USER_TOP_MAX register. */
1062 #define ALT_L4WD_CP_WDT_USER_TOP_MAX_RESET 0x00000000
1063 /* The byte offset of the ALT_L4WD_CP_WDT_USER_TOP_MAX register from the beginning of the component. */
1064 #define ALT_L4WD_CP_WDT_USER_TOP_MAX_OFST 0xe4
1065 /* The address of the ALT_L4WD_CP_WDT_USER_TOP_MAX register. */
1066 #define ALT_L4WD_CP_WDT_USER_TOP_MAX_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CP_WDT_USER_TOP_MAX_OFST))
1067 
1068 /*
1069  * Register : cp_wdt_user_top_init_max
1070  *
1071  * Component Parameters Register 4
1072  *
1073  * Register Layout
1074  *
1075  * Bits | Access | Reset | Description
1076  * :-------|:-------|:------|:-----------------------
1077  * [31:0] | R | 0x0 | Component Parameters 4
1078  *
1079  */
1080 /*
1081  * Field : Component Parameters 4 - cp_wdt_user_top_init_max
1082  *
1083  * Upper limit of Initial Timeout Period parameters.
1084  *
1085  * Field Access Macros:
1086  *
1087  */
1088 /* The Least Significant Bit (LSB) position of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL register field. */
1089 #define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_LSB 0
1090 /* The Most Significant Bit (MSB) position of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL register field. */
1091 #define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_MSB 31
1092 /* The width in bits of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL register field. */
1093 #define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_WIDTH 32
1094 /* The mask used to set the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL register field value. */
1095 #define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_SET_MSK 0xffffffff
1096 /* The mask used to clear the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL register field value. */
1097 #define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_CLR_MSK 0x00000000
1098 /* The reset value of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL register field. */
1099 #define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_RESET 0x0
1100 /* Extracts the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL field value from a register. */
1101 #define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_GET(value) (((value) & 0xffffffff) >> 0)
1102 /* Produces a ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL register field value suitable for setting the register. */
1103 #define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_SET(value) (((value) << 0) & 0xffffffff)
1104 
1105 #ifndef __ASSEMBLY__
1106 /*
1107  * WARNING: The C register and register group struct declarations are provided for
1108  * convenience and illustrative purposes. They should, however, be used with
1109  * caution as the C language standard provides no guarantees about the alignment or
1110  * atomicity of device memory accesses. The recommended practice for writing
1111  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1112  * alt_write_word() functions.
1113  *
1114  * The struct declaration for register ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX.
1115  */
1116 struct ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_s
1117 {
1118  const uint32_t cp_wdt_user_top_init_max : 32; /* Component Parameters 4 */
1119 };
1120 
1121 /* The typedef declaration for register ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX. */
1122 typedef volatile struct ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_s ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_t;
1123 #endif /* __ASSEMBLY__ */
1124 
1125 /* The reset value of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX register. */
1126 #define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_RESET 0x00000000
1127 /* The byte offset of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX register from the beginning of the component. */
1128 #define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_OFST 0xe8
1129 /* The address of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX register. */
1130 #define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_OFST))
1131 
1132 /*
1133  * Register : cd_wdt_top_rst
1134  *
1135  * Component Parameters Register 3
1136  *
1137  * Register Layout
1138  *
1139  * Bits | Access | Reset | Description
1140  * :-------|:-------|:------|:------------------------
1141  * [31:0] | R | 0xff | Component Parameters 3
1142  *
1143  */
1144 /*
1145  * Field : Component Parameters 3 - cd_wdt_top_rst
1146  *
1147  * Contains the reset value of the WDT_TORR register.
1148  *
1149  * Field Access Macros:
1150  *
1151  */
1152 /* The Least Significant Bit (LSB) position of the ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST register field. */
1153 #define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_LSB 0
1154 /* The Most Significant Bit (MSB) position of the ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST register field. */
1155 #define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_MSB 31
1156 /* The width in bits of the ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST register field. */
1157 #define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_WIDTH 32
1158 /* The mask used to set the ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST register field value. */
1159 #define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_SET_MSK 0xffffffff
1160 /* The mask used to clear the ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST register field value. */
1161 #define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_CLR_MSK 0x00000000
1162 /* The reset value of the ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST register field. */
1163 #define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_RESET 0xff
1164 /* Extracts the ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST field value from a register. */
1165 #define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_GET(value) (((value) & 0xffffffff) >> 0)
1166 /* Produces a ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST register field value suitable for setting the register. */
1167 #define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_SET(value) (((value) << 0) & 0xffffffff)
1168 
1169 #ifndef __ASSEMBLY__
1170 /*
1171  * WARNING: The C register and register group struct declarations are provided for
1172  * convenience and illustrative purposes. They should, however, be used with
1173  * caution as the C language standard provides no guarantees about the alignment or
1174  * atomicity of device memory accesses. The recommended practice for writing
1175  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1176  * alt_write_word() functions.
1177  *
1178  * The struct declaration for register ALT_L4WD_CD_WDT_TOP_RST.
1179  */
1180 struct ALT_L4WD_CD_WDT_TOP_RST_s
1181 {
1182  const uint32_t cd_wdt_top_rst : 32; /* Component Parameters 3 */
1183 };
1184 
1185 /* The typedef declaration for register ALT_L4WD_CD_WDT_TOP_RST. */
1186 typedef volatile struct ALT_L4WD_CD_WDT_TOP_RST_s ALT_L4WD_CD_WDT_TOP_RST_t;
1187 #endif /* __ASSEMBLY__ */
1188 
1189 /* The reset value of the ALT_L4WD_CD_WDT_TOP_RST register. */
1190 #define ALT_L4WD_CD_WDT_TOP_RST_RESET 0x000000ff
1191 /* The byte offset of the ALT_L4WD_CD_WDT_TOP_RST register from the beginning of the component. */
1192 #define ALT_L4WD_CD_WDT_TOP_RST_OFST 0xec
1193 /* The address of the ALT_L4WD_CD_WDT_TOP_RST register. */
1194 #define ALT_L4WD_CD_WDT_TOP_RST_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CD_WDT_TOP_RST_OFST))
1195 
1196 /*
1197  * Register : cp_wdt_cnt_rst
1198  *
1199  * Component Parameters Register 2
1200  *
1201  * Register Layout
1202  *
1203  * Bits | Access | Reset | Description
1204  * :-------|:-------|:-----------|:------------------------
1205  * [31:0] | R | 0x7fffffff | Component Parameters 2
1206  *
1207  */
1208 /*
1209  * Field : Component Parameters 2 - cp_wdt_cnt_rst
1210  *
1211  * The timeout period range is fixed. The range increments by the power of 2 from 2
1212  * to the 16 to 2 to the 31.
1213  *
1214  * Field Access Macros:
1215  *
1216  */
1217 /* The Least Significant Bit (LSB) position of the ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST register field. */
1218 #define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_LSB 0
1219 /* The Most Significant Bit (MSB) position of the ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST register field. */
1220 #define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_MSB 31
1221 /* The width in bits of the ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST register field. */
1222 #define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_WIDTH 32
1223 /* The mask used to set the ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST register field value. */
1224 #define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_SET_MSK 0xffffffff
1225 /* The mask used to clear the ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST register field value. */
1226 #define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_CLR_MSK 0x00000000
1227 /* The reset value of the ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST register field. */
1228 #define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_RESET 0x7fffffff
1229 /* Extracts the ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST field value from a register. */
1230 #define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_GET(value) (((value) & 0xffffffff) >> 0)
1231 /* Produces a ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST register field value suitable for setting the register. */
1232 #define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_SET(value) (((value) << 0) & 0xffffffff)
1233 
1234 #ifndef __ASSEMBLY__
1235 /*
1236  * WARNING: The C register and register group struct declarations are provided for
1237  * convenience and illustrative purposes. They should, however, be used with
1238  * caution as the C language standard provides no guarantees about the alignment or
1239  * atomicity of device memory accesses. The recommended practice for writing
1240  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1241  * alt_write_word() functions.
1242  *
1243  * The struct declaration for register ALT_L4WD_CP_WDT_CNT_RST.
1244  */
1245 struct ALT_L4WD_CP_WDT_CNT_RST_s
1246 {
1247  const uint32_t cp_wdt_cnt_rst : 32; /* Component Parameters 2 */
1248 };
1249 
1250 /* The typedef declaration for register ALT_L4WD_CP_WDT_CNT_RST. */
1251 typedef volatile struct ALT_L4WD_CP_WDT_CNT_RST_s ALT_L4WD_CP_WDT_CNT_RST_t;
1252 #endif /* __ASSEMBLY__ */
1253 
1254 /* The reset value of the ALT_L4WD_CP_WDT_CNT_RST register. */
1255 #define ALT_L4WD_CP_WDT_CNT_RST_RESET 0x7fffffff
1256 /* The byte offset of the ALT_L4WD_CP_WDT_CNT_RST register from the beginning of the component. */
1257 #define ALT_L4WD_CP_WDT_CNT_RST_OFST 0xf0
1258 /* The address of the ALT_L4WD_CP_WDT_CNT_RST register. */
1259 #define ALT_L4WD_CP_WDT_CNT_RST_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CP_WDT_CNT_RST_OFST))
1260 
1261 /*
1262  * Register : wdt_comp_param_1
1263  *
1264  * Component Parameters Register 1
1265  *
1266  * Register Layout
1267  *
1268  * Bits | Access | Reset | Description
1269  * :--------|:-------|:------|:--------------------------------------------
1270  * [0] | R | 0x0 | ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN
1271  * [1] | R | 0x0 | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD
1272  * [2] | R | 0x1 | ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP
1273  * [3] | R | 0x0 | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD
1274  * [4] | R | 0x1 | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL
1275  * [5] | R | 0x0 | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP
1276  * [6] | R | 0x1 | ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP
1277  * [7] | R | 0x0 | ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE
1278  * [9:8] | R | 0x2 | ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH
1279  * [12:10] | R | 0x0 | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL
1280  * [15:13] | R | 0x0 | ALT_L4WD_COMP_PARAM_1_RSVD_15_13
1281  * [19:16] | R | 0xf | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP
1282  * [23:20] | R | 0xf | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT
1283  * [28:24] | R | 0x10 | ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH
1284  * [31:29] | R | 0x0 | ALT_L4WD_COMP_PARAM_1_RSVD_31_29
1285  *
1286  */
1287 /*
1288  * Field : cp_wdt_always_en
1289  *
1290  * Field Enumeration Values:
1291  *
1292  * Enum | Value | Description
1293  * :----------------------------------------------|:------|:---------------------------
1294  * ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_E_DISD | 0x0 | Watchdog disabled on reset
1295  *
1296  * Field Access Macros:
1297  *
1298  */
1299 /*
1300  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN
1301  *
1302  * Watchdog disabled on reset
1303  */
1304 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_E_DISD 0x0
1305 
1306 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field. */
1307 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_LSB 0
1308 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field. */
1309 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_MSB 0
1310 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field. */
1311 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_WIDTH 1
1312 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field value. */
1313 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_SET_MSK 0x00000001
1314 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field value. */
1315 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_CLR_MSK 0xfffffffe
1316 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field. */
1317 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_RESET 0x0
1318 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN field value from a register. */
1319 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_GET(value) (((value) & 0x00000001) >> 0)
1320 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field value suitable for setting the register. */
1321 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_SET(value) (((value) << 0) & 0x00000001)
1322 
1323 /*
1324  * Field : cp_wdt_dflt_rmod
1325  *
1326  * Field Enumeration Values:
1327  *
1328  * Enum | Value | Description
1329  * :------------------------------------------------|:------|:-------------------------------------------------
1330  * ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_E_RSTREQ | 0x0 | Generate a warm reset request (don't generate an
1331  * : | | interrupt first)
1332  *
1333  * Field Access Macros:
1334  *
1335  */
1336 /*
1337  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD
1338  *
1339  * Generate a warm reset request (don't generate an interrupt first)
1340  */
1341 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_E_RSTREQ 0x0
1342 
1343 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field. */
1344 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_LSB 1
1345 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field. */
1346 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_MSB 1
1347 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field. */
1348 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_WIDTH 1
1349 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field value. */
1350 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_SET_MSK 0x00000002
1351 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field value. */
1352 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_CLR_MSK 0xfffffffd
1353 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field. */
1354 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_RESET 0x0
1355 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD field value from a register. */
1356 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_GET(value) (((value) & 0x00000002) >> 1)
1357 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field value suitable for setting the register. */
1358 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_SET(value) (((value) << 1) & 0x00000002)
1359 
1360 /*
1361  * Field : cp_wdt_dual_top
1362  *
1363  * Field Enumeration Values:
1364  *
1365  * Enum | Value | Description
1366  * :------------------------------------------------|:------|:---------------------------------
1367  * ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_E_DUALTOP | 0x1 | Second timeout period is present
1368  *
1369  * Field Access Macros:
1370  *
1371  */
1372 /*
1373  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP
1374  *
1375  * Second timeout period is present
1376  */
1377 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_E_DUALTOP 0x1
1378 
1379 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field. */
1380 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_LSB 2
1381 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field. */
1382 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_MSB 2
1383 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field. */
1384 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_WIDTH 1
1385 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field value. */
1386 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_SET_MSK 0x00000004
1387 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field value. */
1388 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_CLR_MSK 0xfffffffb
1389 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field. */
1390 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_RESET 0x1
1391 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP field value from a register. */
1392 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_GET(value) (((value) & 0x00000004) >> 2)
1393 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field value suitable for setting the register. */
1394 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_SET(value) (((value) << 2) & 0x00000004)
1395 
1396 /*
1397  * Field : cp_wdt_hc_rmod
1398  *
1399  * Field Enumeration Values:
1400  *
1401  * Enum | Value | Description
1402  * :--------------------------------------------|:------|:--------------------------------------
1403  * ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_E_PGML | 0x0 | Output response mode is programmable.
1404  *
1405  * Field Access Macros:
1406  *
1407  */
1408 /*
1409  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD
1410  *
1411  * Output response mode is programmable.
1412  */
1413 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_E_PGML 0x0
1414 
1415 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field. */
1416 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_LSB 3
1417 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field. */
1418 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_MSB 3
1419 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field. */
1420 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_WIDTH 1
1421 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field value. */
1422 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_SET_MSK 0x00000008
1423 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field value. */
1424 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_CLR_MSK 0xfffffff7
1425 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field. */
1426 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_RESET 0x0
1427 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD field value from a register. */
1428 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_GET(value) (((value) & 0x00000008) >> 3)
1429 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field value suitable for setting the register. */
1430 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_SET(value) (((value) << 3) & 0x00000008)
1431 
1432 /*
1433  * Field : cp_wdt_hc_rpl
1434  *
1435  * Field Enumeration Values:
1436  *
1437  * Enum | Value | Description
1438  * :------------------------------------------------|:------|:---------------------------------
1439  * ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_E_HARDCODED | 0x1 | Reset pulse length is hardcoded.
1440  *
1441  * Field Access Macros:
1442  *
1443  */
1444 /*
1445  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL
1446  *
1447  * Reset pulse length is hardcoded.
1448  */
1449 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_E_HARDCODED 0x1
1450 
1451 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field. */
1452 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_LSB 4
1453 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field. */
1454 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_MSB 4
1455 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field. */
1456 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_WIDTH 1
1457 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field value. */
1458 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_SET_MSK 0x00000010
1459 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field value. */
1460 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_CLR_MSK 0xffffffef
1461 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field. */
1462 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_RESET 0x1
1463 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL field value from a register. */
1464 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_GET(value) (((value) & 0x00000010) >> 4)
1465 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field value suitable for setting the register. */
1466 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_SET(value) (((value) << 4) & 0x00000010)
1467 
1468 /*
1469  * Field : cp_wdt_hc_top
1470  *
1471  * Field Enumeration Values:
1472  *
1473  * Enum | Value | Description
1474  * :-------------------------------------------|:------|:--------------------------------
1475  * ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_E_PGML | 0x0 | Timeout period is programmable.
1476  *
1477  * Field Access Macros:
1478  *
1479  */
1480 /*
1481  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP
1482  *
1483  * Timeout period is programmable.
1484  */
1485 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_E_PGML 0x0
1486 
1487 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field. */
1488 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_LSB 5
1489 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field. */
1490 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_MSB 5
1491 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field. */
1492 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_WIDTH 1
1493 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field value. */
1494 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_SET_MSK 0x00000020
1495 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field value. */
1496 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_CLR_MSK 0xffffffdf
1497 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field. */
1498 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_RESET 0x0
1499 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP field value from a register. */
1500 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_GET(value) (((value) & 0x00000020) >> 5)
1501 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field value suitable for setting the register. */
1502 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_SET(value) (((value) << 5) & 0x00000020)
1503 
1504 /*
1505  * Field : cp_wdt_use_fix_top
1506  *
1507  * Field Enumeration Values:
1508  *
1509  * Enum | Value | Description
1510  * :------------------------------------------------------|:------|:----------------------------------------------
1511  * ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_E_PREDEFINED | 0x1 | Use pre-defined (fixed) timeout values (range
1512  * : | | from 2**16 to 2**31)
1513  *
1514  * Field Access Macros:
1515  *
1516  */
1517 /*
1518  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP
1519  *
1520  * Use pre-defined (fixed) timeout values (range from 2**16 to 2**31)
1521  */
1522 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_E_PREDEFINED 0x1
1523 
1524 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field. */
1525 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_LSB 6
1526 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field. */
1527 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_MSB 6
1528 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field. */
1529 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_WIDTH 1
1530 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field value. */
1531 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_SET_MSK 0x00000040
1532 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field value. */
1533 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_CLR_MSK 0xffffffbf
1534 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field. */
1535 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_RESET 0x1
1536 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP field value from a register. */
1537 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_GET(value) (((value) & 0x00000040) >> 6)
1538 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field value suitable for setting the register. */
1539 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_SET(value) (((value) << 6) & 0x00000040)
1540 
1541 /*
1542  * Field : cp_wdt_pause
1543  *
1544  * Field Access Macros:
1545  *
1546  */
1547 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field. */
1548 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_LSB 7
1549 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field. */
1550 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_MSB 7
1551 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field. */
1552 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_WIDTH 1
1553 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field value. */
1554 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_SET_MSK 0x00000080
1555 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field value. */
1556 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_CLR_MSK 0xffffff7f
1557 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field. */
1558 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_RESET 0x0
1559 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE field value from a register. */
1560 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_GET(value) (((value) & 0x00000080) >> 7)
1561 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field value suitable for setting the register. */
1562 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_SET(value) (((value) << 7) & 0x00000080)
1563 
1564 /*
1565  * Field : cp_wdt_apb_data_width
1566  *
1567  * Field Enumeration Values:
1568  *
1569  * Enum | Value | Description
1570  * :----------------------------------------------------------|:------|:--------------------------
1571  * ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_E_WIDTH32BITS | 0x2 | APB Data Width is 32 Bits
1572  *
1573  * Field Access Macros:
1574  *
1575  */
1576 /*
1577  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH
1578  *
1579  * APB Data Width is 32 Bits
1580  */
1581 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_E_WIDTH32BITS 0x2
1582 
1583 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field. */
1584 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_LSB 8
1585 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field. */
1586 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_MSB 9
1587 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field. */
1588 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_WIDTH 2
1589 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field value. */
1590 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_SET_MSK 0x00000300
1591 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field value. */
1592 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_CLR_MSK 0xfffffcff
1593 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field. */
1594 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_RESET 0x2
1595 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH field value from a register. */
1596 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_GET(value) (((value) & 0x00000300) >> 8)
1597 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field value suitable for setting the register. */
1598 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_SET(value) (((value) << 8) & 0x00000300)
1599 
1600 /*
1601  * Field : cp_wdt_dflt_rpl
1602  *
1603  * Field Enumeration Values:
1604  *
1605  * Enum | Value | Description
1606  * :-----------------------------------------------------|:------|:--------------------------------
1607  * ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_E_PULSE2CYCLES | 0x0 | Reset pulse length of 2 cycles.
1608  *
1609  * Field Access Macros:
1610  *
1611  */
1612 /*
1613  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL
1614  *
1615  * Reset pulse length of 2 cycles.
1616  */
1617 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_E_PULSE2CYCLES 0x0
1618 
1619 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field. */
1620 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_LSB 10
1621 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field. */
1622 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_MSB 12
1623 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field. */
1624 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_WIDTH 3
1625 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field value. */
1626 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_SET_MSK 0x00001c00
1627 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field value. */
1628 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_CLR_MSK 0xffffe3ff
1629 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field. */
1630 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_RESET 0x0
1631 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL field value from a register. */
1632 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_GET(value) (((value) & 0x00001c00) >> 10)
1633 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field value suitable for setting the register. */
1634 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_SET(value) (((value) << 10) & 0x00001c00)
1635 
1636 /*
1637  * Field : rsvd_15_13
1638  *
1639  * Field Access Macros:
1640  *
1641  */
1642 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_RSVD_15_13 register field. */
1643 #define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_LSB 13
1644 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_RSVD_15_13 register field. */
1645 #define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_MSB 15
1646 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_RSVD_15_13 register field. */
1647 #define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_WIDTH 3
1648 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_RSVD_15_13 register field value. */
1649 #define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_SET_MSK 0x0000e000
1650 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_RSVD_15_13 register field value. */
1651 #define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_CLR_MSK 0xffff1fff
1652 /* The reset value of the ALT_L4WD_COMP_PARAM_1_RSVD_15_13 register field. */
1653 #define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_RESET 0x0
1654 /* Extracts the ALT_L4WD_COMP_PARAM_1_RSVD_15_13 field value from a register. */
1655 #define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_GET(value) (((value) & 0x0000e000) >> 13)
1656 /* Produces a ALT_L4WD_COMP_PARAM_1_RSVD_15_13 register field value suitable for setting the register. */
1657 #define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_SET(value) (((value) << 13) & 0x0000e000)
1658 
1659 /*
1660  * Field : cp_wdt_dflt_top
1661  *
1662  * Field Enumeration Values:
1663  *
1664  * Enum | Value | Description
1665  * :----------------------------------------------|:------|:-------------------------------------
1666  * ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_E_TMO15 | 0xf | Timeout period is 15 (2**31 cycles).
1667  *
1668  * Field Access Macros:
1669  *
1670  */
1671 /*
1672  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP
1673  *
1674  * Timeout period is 15 (2**31 cycles).
1675  */
1676 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_E_TMO15 0xf
1677 
1678 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field. */
1679 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_LSB 16
1680 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field. */
1681 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_MSB 19
1682 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field. */
1683 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_WIDTH 4
1684 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field value. */
1685 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_SET_MSK 0x000f0000
1686 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field value. */
1687 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_CLR_MSK 0xfff0ffff
1688 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field. */
1689 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_RESET 0xf
1690 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP field value from a register. */
1691 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_GET(value) (((value) & 0x000f0000) >> 16)
1692 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field value suitable for setting the register. */
1693 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_SET(value) (((value) << 16) & 0x000f0000)
1694 
1695 /*
1696  * Field : cp_wdt_dflt_top_init
1697  *
1698  * Field Enumeration Values:
1699  *
1700  * Enum | Value | Description
1701  * :---------------------------------------------------|:------|:---------------------------------------------
1702  * ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_E_TMO15 | 0xf | Initial timeout period is 15 (2**31 cycles).
1703  *
1704  * Field Access Macros:
1705  *
1706  */
1707 /*
1708  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT
1709  *
1710  * Initial timeout period is 15 (2**31 cycles).
1711  */
1712 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_E_TMO15 0xf
1713 
1714 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field. */
1715 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_LSB 20
1716 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field. */
1717 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_MSB 23
1718 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field. */
1719 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_WIDTH 4
1720 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field value. */
1721 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_SET_MSK 0x00f00000
1722 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field value. */
1723 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_CLR_MSK 0xff0fffff
1724 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field. */
1725 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_RESET 0xf
1726 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT field value from a register. */
1727 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_GET(value) (((value) & 0x00f00000) >> 20)
1728 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field value suitable for setting the register. */
1729 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_SET(value) (((value) << 20) & 0x00f00000)
1730 
1731 /*
1732  * Field : cp_wdt_cnt_width
1733  *
1734  * Field Enumeration Values:
1735  *
1736  * Enum | Value | Description
1737  * :-----------------------------------------------------|:------|:-------------------------
1738  * ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_E_WIDTH32BITS | 0x10 | Counter width is 32 bits
1739  *
1740  * Field Access Macros:
1741  *
1742  */
1743 /*
1744  * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH
1745  *
1746  * Counter width is 32 bits
1747  */
1748 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_E_WIDTH32BITS 0x10
1749 
1750 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field. */
1751 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_LSB 24
1752 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field. */
1753 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_MSB 28
1754 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field. */
1755 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_WIDTH 5
1756 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field value. */
1757 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_SET_MSK 0x1f000000
1758 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field value. */
1759 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_CLR_MSK 0xe0ffffff
1760 /* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field. */
1761 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_RESET 0x10
1762 /* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH field value from a register. */
1763 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_GET(value) (((value) & 0x1f000000) >> 24)
1764 /* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field value suitable for setting the register. */
1765 #define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_SET(value) (((value) << 24) & 0x1f000000)
1766 
1767 /*
1768  * Field : rsvd_31_29
1769  *
1770  * Field Access Macros:
1771  *
1772  */
1773 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_RSVD_31_29 register field. */
1774 #define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_LSB 29
1775 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_RSVD_31_29 register field. */
1776 #define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_MSB 31
1777 /* The width in bits of the ALT_L4WD_COMP_PARAM_1_RSVD_31_29 register field. */
1778 #define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_WIDTH 3
1779 /* The mask used to set the ALT_L4WD_COMP_PARAM_1_RSVD_31_29 register field value. */
1780 #define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_SET_MSK 0xe0000000
1781 /* The mask used to clear the ALT_L4WD_COMP_PARAM_1_RSVD_31_29 register field value. */
1782 #define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_CLR_MSK 0x1fffffff
1783 /* The reset value of the ALT_L4WD_COMP_PARAM_1_RSVD_31_29 register field. */
1784 #define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_RESET 0x0
1785 /* Extracts the ALT_L4WD_COMP_PARAM_1_RSVD_31_29 field value from a register. */
1786 #define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_GET(value) (((value) & 0xe0000000) >> 29)
1787 /* Produces a ALT_L4WD_COMP_PARAM_1_RSVD_31_29 register field value suitable for setting the register. */
1788 #define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_SET(value) (((value) << 29) & 0xe0000000)
1789 
1790 #ifndef __ASSEMBLY__
1791 /*
1792  * WARNING: The C register and register group struct declarations are provided for
1793  * convenience and illustrative purposes. They should, however, be used with
1794  * caution as the C language standard provides no guarantees about the alignment or
1795  * atomicity of device memory accesses. The recommended practice for writing
1796  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1797  * alt_write_word() functions.
1798  *
1799  * The struct declaration for register ALT_L4WD_COMP_PARAM_1.
1800  */
1801 struct ALT_L4WD_COMP_PARAM_1_s
1802 {
1803  const uint32_t cp_wdt_always_en : 1; /* ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN */
1804  const uint32_t cp_wdt_dflt_rmod : 1; /* ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD */
1805  const uint32_t cp_wdt_dual_top : 1; /* ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP */
1806  const uint32_t cp_wdt_hc_rmod : 1; /* ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD */
1807  const uint32_t cp_wdt_hc_rpl : 1; /* ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL */
1808  const uint32_t cp_wdt_hc_top : 1; /* ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP */
1809  const uint32_t cp_wdt_use_fix_top : 1; /* ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP */
1810  const uint32_t cp_wdt_pause : 1; /* ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE */
1811  const uint32_t cp_wdt_apb_data_width : 2; /* ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH */
1812  const uint32_t cp_wdt_dflt_rpl : 3; /* ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL */
1813  const uint32_t rsvd_15_13 : 3; /* ALT_L4WD_COMP_PARAM_1_RSVD_15_13 */
1814  const uint32_t cp_wdt_dflt_top : 4; /* ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP */
1815  const uint32_t cp_wdt_dflt_top_init : 4; /* ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT */
1816  const uint32_t cp_wdt_cnt_width : 5; /* ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH */
1817  const uint32_t rsvd_31_29 : 3; /* ALT_L4WD_COMP_PARAM_1_RSVD_31_29 */
1818 };
1819 
1820 /* The typedef declaration for register ALT_L4WD_COMP_PARAM_1. */
1821 typedef volatile struct ALT_L4WD_COMP_PARAM_1_s ALT_L4WD_COMP_PARAM_1_t;
1822 #endif /* __ASSEMBLY__ */
1823 
1824 /* The reset value of the ALT_L4WD_COMP_PARAM_1 register. */
1825 #define ALT_L4WD_COMP_PARAM_1_RESET 0x10ff0254
1826 /* The byte offset of the ALT_L4WD_COMP_PARAM_1 register from the beginning of the component. */
1827 #define ALT_L4WD_COMP_PARAM_1_OFST 0xf4
1828 /* The address of the ALT_L4WD_COMP_PARAM_1 register. */
1829 #define ALT_L4WD_COMP_PARAM_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_COMP_PARAM_1_OFST))
1830 
1831 /*
1832  * Register : wdt_comp_version
1833  *
1834  * Component Version Register
1835  *
1836  * Register Layout
1837  *
1838  * Bits | Access | Reset | Description
1839  * :-------|:-------|:-----------|:-------------------------------
1840  * [31:0] | R | 0x3130372a | ALT_L4WD_COMP_VER_WDT_COMP_VER
1841  *
1842  */
1843 /*
1844  * Field : wdt_comp_version
1845  *
1846  * ASCII value for each number in the version, followed by *. For example,
1847  *
1848  * 32_30_31_2A represents the version 2.01*. Reset Value: See the Releases
1849  *
1850  * table in the DW_apb_rtc Release Notes.
1851  *
1852  * Field Access Macros:
1853  *
1854  */
1855 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_VER_WDT_COMP_VER register field. */
1856 #define ALT_L4WD_COMP_VER_WDT_COMP_VER_LSB 0
1857 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_VER_WDT_COMP_VER register field. */
1858 #define ALT_L4WD_COMP_VER_WDT_COMP_VER_MSB 31
1859 /* The width in bits of the ALT_L4WD_COMP_VER_WDT_COMP_VER register field. */
1860 #define ALT_L4WD_COMP_VER_WDT_COMP_VER_WIDTH 32
1861 /* The mask used to set the ALT_L4WD_COMP_VER_WDT_COMP_VER register field value. */
1862 #define ALT_L4WD_COMP_VER_WDT_COMP_VER_SET_MSK 0xffffffff
1863 /* The mask used to clear the ALT_L4WD_COMP_VER_WDT_COMP_VER register field value. */
1864 #define ALT_L4WD_COMP_VER_WDT_COMP_VER_CLR_MSK 0x00000000
1865 /* The reset value of the ALT_L4WD_COMP_VER_WDT_COMP_VER register field. */
1866 #define ALT_L4WD_COMP_VER_WDT_COMP_VER_RESET 0x3130372a
1867 /* Extracts the ALT_L4WD_COMP_VER_WDT_COMP_VER field value from a register. */
1868 #define ALT_L4WD_COMP_VER_WDT_COMP_VER_GET(value) (((value) & 0xffffffff) >> 0)
1869 /* Produces a ALT_L4WD_COMP_VER_WDT_COMP_VER register field value suitable for setting the register. */
1870 #define ALT_L4WD_COMP_VER_WDT_COMP_VER_SET(value) (((value) << 0) & 0xffffffff)
1871 
1872 #ifndef __ASSEMBLY__
1873 /*
1874  * WARNING: The C register and register group struct declarations are provided for
1875  * convenience and illustrative purposes. They should, however, be used with
1876  * caution as the C language standard provides no guarantees about the alignment or
1877  * atomicity of device memory accesses. The recommended practice for writing
1878  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1879  * alt_write_word() functions.
1880  *
1881  * The struct declaration for register ALT_L4WD_COMP_VER.
1882  */
1883 struct ALT_L4WD_COMP_VER_s
1884 {
1885  const uint32_t wdt_comp_version : 32; /* ALT_L4WD_COMP_VER_WDT_COMP_VER */
1886 };
1887 
1888 /* The typedef declaration for register ALT_L4WD_COMP_VER. */
1889 typedef volatile struct ALT_L4WD_COMP_VER_s ALT_L4WD_COMP_VER_t;
1890 #endif /* __ASSEMBLY__ */
1891 
1892 /* The reset value of the ALT_L4WD_COMP_VER register. */
1893 #define ALT_L4WD_COMP_VER_RESET 0x3130372a
1894 /* The byte offset of the ALT_L4WD_COMP_VER register from the beginning of the component. */
1895 #define ALT_L4WD_COMP_VER_OFST 0xf8
1896 /* The address of the ALT_L4WD_COMP_VER register. */
1897 #define ALT_L4WD_COMP_VER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_COMP_VER_OFST))
1898 
1899 /*
1900  * Register : wdt_comp_type
1901  *
1902  * Component Type Register
1903  *
1904  * Register Layout
1905  *
1906  * Bits | Access | Reset | Description
1907  * :-------|:-------|:-----------|:---------------------------------
1908  * [31:0] | R | 0x44570120 | ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE
1909  *
1910  */
1911 /*
1912  * Field : wdt_comp_type
1913  *
1914  * Component Type Register
1915  *
1916  * Field Access Macros:
1917  *
1918  */
1919 /* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE register field. */
1920 #define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_LSB 0
1921 /* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE register field. */
1922 #define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_MSB 31
1923 /* The width in bits of the ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE register field. */
1924 #define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_WIDTH 32
1925 /* The mask used to set the ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE register field value. */
1926 #define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_SET_MSK 0xffffffff
1927 /* The mask used to clear the ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE register field value. */
1928 #define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_CLR_MSK 0x00000000
1929 /* The reset value of the ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE register field. */
1930 #define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_RESET 0x44570120
1931 /* Extracts the ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE field value from a register. */
1932 #define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_GET(value) (((value) & 0xffffffff) >> 0)
1933 /* Produces a ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE register field value suitable for setting the register. */
1934 #define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_SET(value) (((value) << 0) & 0xffffffff)
1935 
1936 #ifndef __ASSEMBLY__
1937 /*
1938  * WARNING: The C register and register group struct declarations are provided for
1939  * convenience and illustrative purposes. They should, however, be used with
1940  * caution as the C language standard provides no guarantees about the alignment or
1941  * atomicity of device memory accesses. The recommended practice for writing
1942  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1943  * alt_write_word() functions.
1944  *
1945  * The struct declaration for register ALT_L4WD_COMP_TYPE.
1946  */
1947 struct ALT_L4WD_COMP_TYPE_s
1948 {
1949  const uint32_t wdt_comp_type : 32; /* ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE */
1950 };
1951 
1952 /* The typedef declaration for register ALT_L4WD_COMP_TYPE. */
1953 typedef volatile struct ALT_L4WD_COMP_TYPE_s ALT_L4WD_COMP_TYPE_t;
1954 #endif /* __ASSEMBLY__ */
1955 
1956 /* The reset value of the ALT_L4WD_COMP_TYPE register. */
1957 #define ALT_L4WD_COMP_TYPE_RESET 0x44570120
1958 /* The byte offset of the ALT_L4WD_COMP_TYPE register from the beginning of the component. */
1959 #define ALT_L4WD_COMP_TYPE_OFST 0xfc
1960 /* The address of the ALT_L4WD_COMP_TYPE register. */
1961 #define ALT_L4WD_COMP_TYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_COMP_TYPE_OFST))
1962 
1963 #ifndef __ASSEMBLY__
1964 /*
1965  * WARNING: The C register and register group struct declarations are provided for
1966  * convenience and illustrative purposes. They should, however, be used with
1967  * caution as the C language standard provides no guarantees about the alignment or
1968  * atomicity of device memory accesses. The recommended practice for writing
1969  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1970  * alt_write_word() functions.
1971  *
1972  * The struct declaration for register group ALT_L4WD.
1973  */
1974 struct ALT_L4WD_s
1975 {
1976  ALT_L4WD_CR_t wdt_cr; /* ALT_L4WD_CR */
1977  ALT_L4WD_TORR_t wdt_torr; /* ALT_L4WD_TORR */
1978  ALT_L4WD_CCVR_t wdt_ccvr; /* ALT_L4WD_CCVR */
1979  ALT_L4WD_CRR_t wdt_crr; /* ALT_L4WD_CRR */
1980  ALT_L4WD_STAT_t wdt_stat; /* ALT_L4WD_STAT */
1981  ALT_L4WD_EOI_t wdt_eoi; /* ALT_L4WD_EOI */
1982  volatile uint32_t _pad_0x18_0xe3[51]; /* *UNDEFINED* */
1983  ALT_L4WD_CP_WDT_USER_TOP_MAX_t cp_wdt_user_top_max; /* ALT_L4WD_CP_WDT_USER_TOP_MAX */
1984  ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_t cp_wdt_user_top_init_max; /* ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX */
1985  ALT_L4WD_CD_WDT_TOP_RST_t cd_wdt_top_rst; /* ALT_L4WD_CD_WDT_TOP_RST */
1986  ALT_L4WD_CP_WDT_CNT_RST_t cp_wdt_cnt_rst; /* ALT_L4WD_CP_WDT_CNT_RST */
1987  ALT_L4WD_COMP_PARAM_1_t wdt_comp_param_1; /* ALT_L4WD_COMP_PARAM_1 */
1988  ALT_L4WD_COMP_VER_t wdt_comp_version; /* ALT_L4WD_COMP_VER */
1989  ALT_L4WD_COMP_TYPE_t wdt_comp_type; /* ALT_L4WD_COMP_TYPE */
1990 };
1991 
1992 /* The typedef declaration for register group ALT_L4WD. */
1993 typedef volatile struct ALT_L4WD_s ALT_L4WD_t;
1994 /* The struct declaration for the raw register contents of register group ALT_L4WD. */
1995 struct ALT_L4WD_raw_s
1996 {
1997  volatile uint32_t wdt_cr; /* ALT_L4WD_CR */
1998  volatile uint32_t wdt_torr; /* ALT_L4WD_TORR */
1999  volatile uint32_t wdt_ccvr; /* ALT_L4WD_CCVR */
2000  volatile uint32_t wdt_crr; /* ALT_L4WD_CRR */
2001  volatile uint32_t wdt_stat; /* ALT_L4WD_STAT */
2002  volatile uint32_t wdt_eoi; /* ALT_L4WD_EOI */
2003  uint32_t _pad_0x18_0xe3[51]; /* *UNDEFINED* */
2004  volatile uint32_t cp_wdt_user_top_max; /* ALT_L4WD_CP_WDT_USER_TOP_MAX */
2005  volatile uint32_t cp_wdt_user_top_init_max; /* ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX */
2006  volatile uint32_t cd_wdt_top_rst; /* ALT_L4WD_CD_WDT_TOP_RST */
2007  volatile uint32_t cp_wdt_cnt_rst; /* ALT_L4WD_CP_WDT_CNT_RST */
2008  volatile uint32_t wdt_comp_param_1; /* ALT_L4WD_COMP_PARAM_1 */
2009  volatile uint32_t wdt_comp_version; /* ALT_L4WD_COMP_VER */
2010  volatile uint32_t wdt_comp_type; /* ALT_L4WD_COMP_TYPE */
2011 };
2012 
2013 /* The typedef declaration for the raw register contents of register group ALT_L4WD. */
2014 typedef volatile struct ALT_L4WD_raw_s ALT_L4WD_raw_t;
2015 #endif /* __ASSEMBLY__ */
2016 
2017 
2018 #ifdef __cplusplus
2019 }
2020 #endif /* __cplusplus */
2021 #endif /* __ALT_SOCAL_L4WD_H__ */
2022