Hardware Libraries  20.1
Arria 10 SoC Hardware Manager
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alt_clkmgr.h
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32 
33 /* Altera - ALT_CLKMGR */
34 
35 #ifndef __ALTERA_ALT_CLKMGR_H__
36 #define __ALTERA_ALT_CLKMGR_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
43 /*
44  * Component : Clock Manager Module - ALT_CLKMGR
45  * Clock Manager Module
46  *
47  * Registers in the Clock Manager module
48  *
49  */
50 /*
51  * Register : Control Register - ctrl
52  *
53  * Contains fields that control the entire Clock Manager.
54  *
55  * Register Layout
56  *
57  * Bits | Access | Reset | Description
58  * :-------|:-------|:------|:------------------------------
59  * [0] | RW | 0x1 | Safe Mode
60  * [1] | ??? | 0x0 | *UNDEFINED*
61  * [2] | RW | 0x1 | Enable SafeMode on Warm Reset
62  * [31:3] | ??? | 0x0 | *UNDEFINED*
63  *
64  */
65 /*
66  * Field : Safe Mode - safemode
67  *
68  * When set the Clock Manager is in Safe Mode.
69  *
70  * In Safe Mode Clock Manager register settings defining clock behavior are ignored
71  * and clocks are set to a Safe Mode state.In Safe Mode all clocks with the
72  * optional exception of debug clocks, are directly generated from the EOSC1 clock
73  * input, all PLLs are bypassed, all programmable dividers are set to 1 and all
74  * clocks are enabled.
75  *
76  * This bit should only be cleared when clocks have been correctly configured
77  *
78  * This field is set on a cold reset and optionally on a warm reset and may not be
79  * set by SW.
80  *
81  * Field Access Macros:
82  *
83  */
84 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CTL_SAFEMOD register field. */
85 #define ALT_CLKMGR_CTL_SAFEMOD_LSB 0
86 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CTL_SAFEMOD register field. */
87 #define ALT_CLKMGR_CTL_SAFEMOD_MSB 0
88 /* The width in bits of the ALT_CLKMGR_CTL_SAFEMOD register field. */
89 #define ALT_CLKMGR_CTL_SAFEMOD_WIDTH 1
90 /* The mask used to set the ALT_CLKMGR_CTL_SAFEMOD register field value. */
91 #define ALT_CLKMGR_CTL_SAFEMOD_SET_MSK 0x00000001
92 /* The mask used to clear the ALT_CLKMGR_CTL_SAFEMOD register field value. */
93 #define ALT_CLKMGR_CTL_SAFEMOD_CLR_MSK 0xfffffffe
94 /* The reset value of the ALT_CLKMGR_CTL_SAFEMOD register field. */
95 #define ALT_CLKMGR_CTL_SAFEMOD_RESET 0x1
96 /* Extracts the ALT_CLKMGR_CTL_SAFEMOD field value from a register. */
97 #define ALT_CLKMGR_CTL_SAFEMOD_GET(value) (((value) & 0x00000001) >> 0)
98 /* Produces a ALT_CLKMGR_CTL_SAFEMOD register field value suitable for setting the register. */
99 #define ALT_CLKMGR_CTL_SAFEMOD_SET(value) (((value) << 0) & 0x00000001)
100 
101 /*
102  * Field : Enable SafeMode on Warm Reset - ensfmdwr
103  *
104  * When set the Clock Manager will respond to a Safe Mode request from the Reset
105  * Manager on a warm reset by setting the Safe Mode bit. When clear the clock
106  * manager will not set the the Safe Mode bit on a warm reset This bit is cleared
107  * on a cold reset. Warm reset has no affect on this bit.
108  *
109  * Field Access Macros:
110  *
111  */
112 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CTL_ENSFMDWR register field. */
113 #define ALT_CLKMGR_CTL_ENSFMDWR_LSB 2
114 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CTL_ENSFMDWR register field. */
115 #define ALT_CLKMGR_CTL_ENSFMDWR_MSB 2
116 /* The width in bits of the ALT_CLKMGR_CTL_ENSFMDWR register field. */
117 #define ALT_CLKMGR_CTL_ENSFMDWR_WIDTH 1
118 /* The mask used to set the ALT_CLKMGR_CTL_ENSFMDWR register field value. */
119 #define ALT_CLKMGR_CTL_ENSFMDWR_SET_MSK 0x00000004
120 /* The mask used to clear the ALT_CLKMGR_CTL_ENSFMDWR register field value. */
121 #define ALT_CLKMGR_CTL_ENSFMDWR_CLR_MSK 0xfffffffb
122 /* The reset value of the ALT_CLKMGR_CTL_ENSFMDWR register field. */
123 #define ALT_CLKMGR_CTL_ENSFMDWR_RESET 0x1
124 /* Extracts the ALT_CLKMGR_CTL_ENSFMDWR field value from a register. */
125 #define ALT_CLKMGR_CTL_ENSFMDWR_GET(value) (((value) & 0x00000004) >> 2)
126 /* Produces a ALT_CLKMGR_CTL_ENSFMDWR register field value suitable for setting the register. */
127 #define ALT_CLKMGR_CTL_ENSFMDWR_SET(value) (((value) << 2) & 0x00000004)
128 
129 #ifndef __ASSEMBLY__
130 /*
131  * WARNING: The C register and register group struct declarations are provided for
132  * convenience and illustrative purposes. They should, however, be used with
133  * caution as the C language standard provides no guarantees about the alignment or
134  * atomicity of device memory accesses. The recommended practice for writing
135  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
136  * alt_write_word() functions.
137  *
138  * The struct declaration for register ALT_CLKMGR_CTL.
139  */
140 struct ALT_CLKMGR_CTL_s
141 {
142  uint32_t safemode : 1; /* Safe Mode */
143  uint32_t : 1; /* *UNDEFINED* */
144  uint32_t ensfmdwr : 1; /* Enable SafeMode on Warm Reset */
145  uint32_t : 29; /* *UNDEFINED* */
146 };
147 
148 /* The typedef declaration for register ALT_CLKMGR_CTL. */
149 typedef volatile struct ALT_CLKMGR_CTL_s ALT_CLKMGR_CTL_t;
150 #endif /* __ASSEMBLY__ */
151 
152 /* The byte offset of the ALT_CLKMGR_CTL register from the beginning of the component. */
153 #define ALT_CLKMGR_CTL_OFST 0x0
154 
155 /*
156  * Register : PLL Bypass Register - bypass
157  *
158  * Contains fields that control bypassing each PLL.
159  *
160  * Register Layout
161  *
162  * Bits | Access | Reset | Description
163  * :-------|:-------|:------|:-----------------------------
164  * [0] | RW | 0x1 | Main PLL Bypass
165  * [1] | RW | 0x1 | SDRAM PLL Bypass
166  * [2] | RW | 0x0 | SDRAM PLL Bypass Source
167  * [3] | RW | 0x1 | Peripheral PLL Bypass
168  * [4] | RW | 0x0 | Peripheral PLL Bypass Source
169  * [31:5] | ??? | 0x0 | *UNDEFINED*
170  *
171  */
172 /*
173  * Field : Main PLL Bypass - mainpll
174  *
175  * When set, causes the Main PLL VCO and counters to be bypassed so that all clocks
176  * generated by the Main PLL are directly driven from the Main PLL input clock. The
177  * bypass source for Main PLL is the external eosc1_clk.
178  *
179  * The reset value for this bit is applied on a cold reset. Warm reset has no
180  * affect on this bit.
181  *
182  * Field Access Macros:
183  *
184  */
185 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_MAINPLL register field. */
186 #define ALT_CLKMGR_BYPASS_MAINPLL_LSB 0
187 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_MAINPLL register field. */
188 #define ALT_CLKMGR_BYPASS_MAINPLL_MSB 0
189 /* The width in bits of the ALT_CLKMGR_BYPASS_MAINPLL register field. */
190 #define ALT_CLKMGR_BYPASS_MAINPLL_WIDTH 1
191 /* The mask used to set the ALT_CLKMGR_BYPASS_MAINPLL register field value. */
192 #define ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK 0x00000001
193 /* The mask used to clear the ALT_CLKMGR_BYPASS_MAINPLL register field value. */
194 #define ALT_CLKMGR_BYPASS_MAINPLL_CLR_MSK 0xfffffffe
195 /* The reset value of the ALT_CLKMGR_BYPASS_MAINPLL register field. */
196 #define ALT_CLKMGR_BYPASS_MAINPLL_RESET 0x1
197 /* Extracts the ALT_CLKMGR_BYPASS_MAINPLL field value from a register. */
198 #define ALT_CLKMGR_BYPASS_MAINPLL_GET(value) (((value) & 0x00000001) >> 0)
199 /* Produces a ALT_CLKMGR_BYPASS_MAINPLL register field value suitable for setting the register. */
200 #define ALT_CLKMGR_BYPASS_MAINPLL_SET(value) (((value) << 0) & 0x00000001)
201 
202 /*
203  * Field : SDRAM PLL Bypass - sdrpll
204  *
205  * When set, causes the SDRAM PLL VCO and counters to be bypassed so that all
206  * clocks generated by the SDRAM PLL are directly driven from either eosc1_clk or
207  * the SDRAM PLL input clock.
208  *
209  * The bypass clock source for SDRAM PLL is determined by the SDRAM PLL Bypass
210  * Source Register bit.
211  *
212  * The reset value for this bit is applied on a cold reset. Warm reset has no
213  * affect on this bit.
214  *
215  * Field Access Macros:
216  *
217  */
218 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_SDRPLL register field. */
219 #define ALT_CLKMGR_BYPASS_SDRPLL_LSB 1
220 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_SDRPLL register field. */
221 #define ALT_CLKMGR_BYPASS_SDRPLL_MSB 1
222 /* The width in bits of the ALT_CLKMGR_BYPASS_SDRPLL register field. */
223 #define ALT_CLKMGR_BYPASS_SDRPLL_WIDTH 1
224 /* The mask used to set the ALT_CLKMGR_BYPASS_SDRPLL register field value. */
225 #define ALT_CLKMGR_BYPASS_SDRPLL_SET_MSK 0x00000002
226 /* The mask used to clear the ALT_CLKMGR_BYPASS_SDRPLL register field value. */
227 #define ALT_CLKMGR_BYPASS_SDRPLL_CLR_MSK 0xfffffffd
228 /* The reset value of the ALT_CLKMGR_BYPASS_SDRPLL register field. */
229 #define ALT_CLKMGR_BYPASS_SDRPLL_RESET 0x1
230 /* Extracts the ALT_CLKMGR_BYPASS_SDRPLL field value from a register. */
231 #define ALT_CLKMGR_BYPASS_SDRPLL_GET(value) (((value) & 0x00000002) >> 1)
232 /* Produces a ALT_CLKMGR_BYPASS_SDRPLL register field value suitable for setting the register. */
233 #define ALT_CLKMGR_BYPASS_SDRPLL_SET(value) (((value) << 1) & 0x00000002)
234 
235 /*
236  * Field : SDRAM PLL Bypass Source - sdrpllsrc
237  *
238  * This bit defines the bypass source forSDRAM PLL.
239  *
240  * When changing fields that affect VCO lock the PLL must be bypassed and this bit
241  * must be set to OSC1_CLK.
242  *
243  * The reset value for this bit is applied on a cold reset. Warm reset has no
244  * affect on this bit.
245  *
246  * Field Enumeration Values:
247  *
248  * Enum | Value | Description
249  * :-----------------------------------------------|:------|:---------------------
250  * ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_EOSC1 | 0x0 | Select EOSC1
251  * ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_INPUT_MUX | 0x1 | Select PLL Input Mux
252  *
253  * Field Access Macros:
254  *
255  */
256 /*
257  * Enumerated value for register field ALT_CLKMGR_BYPASS_SDRPLLSRC
258  *
259  * Select EOSC1
260  */
261 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_EOSC1 0x0
262 /*
263  * Enumerated value for register field ALT_CLKMGR_BYPASS_SDRPLLSRC
264  *
265  * Select PLL Input Mux
266  */
267 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_INPUT_MUX 0x1
268 
269 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */
270 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_LSB 2
271 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */
272 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_MSB 2
273 /* The width in bits of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */
274 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_WIDTH 1
275 /* The mask used to set the ALT_CLKMGR_BYPASS_SDRPLLSRC register field value. */
276 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_SET_MSK 0x00000004
277 /* The mask used to clear the ALT_CLKMGR_BYPASS_SDRPLLSRC register field value. */
278 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_CLR_MSK 0xfffffffb
279 /* The reset value of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */
280 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_RESET 0x0
281 /* Extracts the ALT_CLKMGR_BYPASS_SDRPLLSRC field value from a register. */
282 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_GET(value) (((value) & 0x00000004) >> 2)
283 /* Produces a ALT_CLKMGR_BYPASS_SDRPLLSRC register field value suitable for setting the register. */
284 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_SET(value) (((value) << 2) & 0x00000004)
285 
286 /*
287  * Field : Peripheral PLL Bypass - perpll
288  *
289  * When set, causes the Peripheral PLL VCO and counters to be bypassed so that all
290  * clocks generated by the Peripheral PLL are directly driven from either eosc1_clk
291  * or the Peripheral PLL input clock.
292  *
293  * The bypass clock source for Peripheral PLL is determined by the Peripheral PLL
294  * Bypass Source Register bit.
295  *
296  * The reset value for this bit is applied on a cold reset. Warm reset has no
297  * affect on this bit.
298  *
299  * Field Access Macros:
300  *
301  */
302 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_PERPLL register field. */
303 #define ALT_CLKMGR_BYPASS_PERPLL_LSB 3
304 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_PERPLL register field. */
305 #define ALT_CLKMGR_BYPASS_PERPLL_MSB 3
306 /* The width in bits of the ALT_CLKMGR_BYPASS_PERPLL register field. */
307 #define ALT_CLKMGR_BYPASS_PERPLL_WIDTH 1
308 /* The mask used to set the ALT_CLKMGR_BYPASS_PERPLL register field value. */
309 #define ALT_CLKMGR_BYPASS_PERPLL_SET_MSK 0x00000008
310 /* The mask used to clear the ALT_CLKMGR_BYPASS_PERPLL register field value. */
311 #define ALT_CLKMGR_BYPASS_PERPLL_CLR_MSK 0xfffffff7
312 /* The reset value of the ALT_CLKMGR_BYPASS_PERPLL register field. */
313 #define ALT_CLKMGR_BYPASS_PERPLL_RESET 0x1
314 /* Extracts the ALT_CLKMGR_BYPASS_PERPLL field value from a register. */
315 #define ALT_CLKMGR_BYPASS_PERPLL_GET(value) (((value) & 0x00000008) >> 3)
316 /* Produces a ALT_CLKMGR_BYPASS_PERPLL register field value suitable for setting the register. */
317 #define ALT_CLKMGR_BYPASS_PERPLL_SET(value) (((value) << 3) & 0x00000008)
318 
319 /*
320  * Field : Peripheral PLL Bypass Source - perpllsrc
321  *
322  * This bit defines the bypass source forPeripheral PLL.
323  *
324  * When changing fields that affect VCO lock the PLL must be bypassed and this bit
325  * must be set to OSC1_CLK.
326  *
327  * The reset value for this bit is applied on a cold reset. Warm reset has no
328  * affect on this bit.
329  *
330  * Field Enumeration Values:
331  *
332  * Enum | Value | Description
333  * :-----------------------------------------------|:------|:---------------------
334  * ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_EOSC1 | 0x0 | Select EOSC1
335  * ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_INPUT_MUX | 0x1 | Select PLL Input Mux
336  *
337  * Field Access Macros:
338  *
339  */
340 /*
341  * Enumerated value for register field ALT_CLKMGR_BYPASS_PERPLLSRC
342  *
343  * Select EOSC1
344  */
345 #define ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_EOSC1 0x0
346 /*
347  * Enumerated value for register field ALT_CLKMGR_BYPASS_PERPLLSRC
348  *
349  * Select PLL Input Mux
350  */
351 #define ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_INPUT_MUX 0x1
352 
353 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */
354 #define ALT_CLKMGR_BYPASS_PERPLLSRC_LSB 4
355 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */
356 #define ALT_CLKMGR_BYPASS_PERPLLSRC_MSB 4
357 /* The width in bits of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */
358 #define ALT_CLKMGR_BYPASS_PERPLLSRC_WIDTH 1
359 /* The mask used to set the ALT_CLKMGR_BYPASS_PERPLLSRC register field value. */
360 #define ALT_CLKMGR_BYPASS_PERPLLSRC_SET_MSK 0x00000010
361 /* The mask used to clear the ALT_CLKMGR_BYPASS_PERPLLSRC register field value. */
362 #define ALT_CLKMGR_BYPASS_PERPLLSRC_CLR_MSK 0xffffffef
363 /* The reset value of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */
364 #define ALT_CLKMGR_BYPASS_PERPLLSRC_RESET 0x0
365 /* Extracts the ALT_CLKMGR_BYPASS_PERPLLSRC field value from a register. */
366 #define ALT_CLKMGR_BYPASS_PERPLLSRC_GET(value) (((value) & 0x00000010) >> 4)
367 /* Produces a ALT_CLKMGR_BYPASS_PERPLLSRC register field value suitable for setting the register. */
368 #define ALT_CLKMGR_BYPASS_PERPLLSRC_SET(value) (((value) << 4) & 0x00000010)
369 
370 #ifndef __ASSEMBLY__
371 /*
372  * WARNING: The C register and register group struct declarations are provided for
373  * convenience and illustrative purposes. They should, however, be used with
374  * caution as the C language standard provides no guarantees about the alignment or
375  * atomicity of device memory accesses. The recommended practice for writing
376  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
377  * alt_write_word() functions.
378  *
379  * The struct declaration for register ALT_CLKMGR_BYPASS.
380  */
381 struct ALT_CLKMGR_BYPASS_s
382 {
383  uint32_t mainpll : 1; /* Main PLL Bypass */
384  uint32_t sdrpll : 1; /* SDRAM PLL Bypass */
385  uint32_t sdrpllsrc : 1; /* SDRAM PLL Bypass Source */
386  uint32_t perpll : 1; /* Peripheral PLL Bypass */
387  uint32_t perpllsrc : 1; /* Peripheral PLL Bypass Source */
388  uint32_t : 27; /* *UNDEFINED* */
389 };
390 
391 /* The typedef declaration for register ALT_CLKMGR_BYPASS. */
392 typedef volatile struct ALT_CLKMGR_BYPASS_s ALT_CLKMGR_BYPASS_t;
393 #endif /* __ASSEMBLY__ */
394 
395 /* The byte offset of the ALT_CLKMGR_BYPASS register from the beginning of the component. */
396 #define ALT_CLKMGR_BYPASS_OFST 0x4
397 
398 /*
399  * Register : Interrupt Status Register - inter
400  *
401  * Contains fields that indicate the PLL lock status.
402  *
403  * Fields are only reset by a cold reset.
404  *
405  * Register Layout
406  *
407  * Bits | Access | Reset | Description
408  * :-------|:-------|:--------|:-----------------------------------
409  * [0] | RW | 0x0 | Main PLL Achieved Lock
410  * [1] | RW | 0x0 | Peripheral PLL Achieved Lock
411  * [2] | RW | 0x0 | SDRAM PLL Achieved Lock
412  * [3] | RW | 0x0 | Main PLL Lost Lock
413  * [4] | RW | 0x0 | Peripheral PLL Lost Lock
414  * [5] | RW | 0x0 | SDRAM PLL Lost Lock
415  * [6] | R | Unknown | Main PLL Current Lock Status
416  * [7] | R | Unknown | Peripheral PLL Current Lock Status
417  * [8] | R | Unknown | SDRAM PLL Current Lock Status
418  * [31:9] | ??? | 0x0 | *UNDEFINED*
419  *
420  */
421 /*
422  * Field : Main PLL Achieved Lock - mainpllachieved
423  *
424  * If 1, the Main PLL has achieved lock at least once since this bit was cleared.
425  * If 0, the Main PLL has not achieved lock since this bit was cleared.
426  *
427  * Field Access Macros:
428  *
429  */
430 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */
431 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_LSB 0
432 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */
433 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_MSB 0
434 /* The width in bits of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */
435 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_WIDTH 1
436 /* The mask used to set the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field value. */
437 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET_MSK 0x00000001
438 /* The mask used to clear the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field value. */
439 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_CLR_MSK 0xfffffffe
440 /* The reset value of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */
441 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_RESET 0x0
442 /* Extracts the ALT_CLKMGR_INTER_MAINPLLACHIEVED field value from a register. */
443 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
444 /* Produces a ALT_CLKMGR_INTER_MAINPLLACHIEVED register field value suitable for setting the register. */
445 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001)
446 
447 /*
448  * Field : Peripheral PLL Achieved Lock - perpllachieved
449  *
450  * If 1, the Peripheral PLL has achieved lock at least once since this bit was
451  * cleared. If 0, the Peripheral PLL has not achieved lock since this bit was
452  * cleared.
453  *
454  * Field Access Macros:
455  *
456  */
457 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */
458 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_LSB 1
459 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */
460 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_MSB 1
461 /* The width in bits of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */
462 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_WIDTH 1
463 /* The mask used to set the ALT_CLKMGR_INTER_PERPLLACHIEVED register field value. */
464 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_SET_MSK 0x00000002
465 /* The mask used to clear the ALT_CLKMGR_INTER_PERPLLACHIEVED register field value. */
466 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_CLR_MSK 0xfffffffd
467 /* The reset value of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */
468 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_RESET 0x0
469 /* Extracts the ALT_CLKMGR_INTER_PERPLLACHIEVED field value from a register. */
470 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
471 /* Produces a ALT_CLKMGR_INTER_PERPLLACHIEVED register field value suitable for setting the register. */
472 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002)
473 
474 /*
475  * Field : SDRAM PLL Achieved Lock - sdrpllachieved
476  *
477  * If 1, the SDRAM PLL has achieved lock at least once since this bit was cleared.
478  * If 0, the SDRAM PLL has not achieved lock since this bit was cleared.
479  *
480  * Field Access Macros:
481  *
482  */
483 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */
484 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_LSB 2
485 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */
486 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_MSB 2
487 /* The width in bits of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */
488 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_WIDTH 1
489 /* The mask used to set the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field value. */
490 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET_MSK 0x00000004
491 /* The mask used to clear the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field value. */
492 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_CLR_MSK 0xfffffffb
493 /* The reset value of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */
494 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_RESET 0x0
495 /* Extracts the ALT_CLKMGR_INTER_SDRPLLACHIEVED field value from a register. */
496 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_GET(value) (((value) & 0x00000004) >> 2)
497 /* Produces a ALT_CLKMGR_INTER_SDRPLLACHIEVED register field value suitable for setting the register. */
498 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET(value) (((value) << 2) & 0x00000004)
499 
500 /*
501  * Field : Main PLL Lost Lock - mainplllost
502  *
503  * If 1, the Main PLL has lost lock at least once since this bit was cleared. If 0,
504  * the Main PLL has not lost lock since this bit was cleared.
505  *
506  * Field Access Macros:
507  *
508  */
509 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */
510 #define ALT_CLKMGR_INTER_MAINPLLLOST_LSB 3
511 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */
512 #define ALT_CLKMGR_INTER_MAINPLLLOST_MSB 3
513 /* The width in bits of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */
514 #define ALT_CLKMGR_INTER_MAINPLLLOST_WIDTH 1
515 /* The mask used to set the ALT_CLKMGR_INTER_MAINPLLLOST register field value. */
516 #define ALT_CLKMGR_INTER_MAINPLLLOST_SET_MSK 0x00000008
517 /* The mask used to clear the ALT_CLKMGR_INTER_MAINPLLLOST register field value. */
518 #define ALT_CLKMGR_INTER_MAINPLLLOST_CLR_MSK 0xfffffff7
519 /* The reset value of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */
520 #define ALT_CLKMGR_INTER_MAINPLLLOST_RESET 0x0
521 /* Extracts the ALT_CLKMGR_INTER_MAINPLLLOST field value from a register. */
522 #define ALT_CLKMGR_INTER_MAINPLLLOST_GET(value) (((value) & 0x00000008) >> 3)
523 /* Produces a ALT_CLKMGR_INTER_MAINPLLLOST register field value suitable for setting the register. */
524 #define ALT_CLKMGR_INTER_MAINPLLLOST_SET(value) (((value) << 3) & 0x00000008)
525 
526 /*
527  * Field : Peripheral PLL Lost Lock - perplllost
528  *
529  * If 1, the Peripheral PLL has lost lock at least once since this bit was cleared.
530  * If 0, the Peripheral PLL has not lost lock since this bit was cleared.
531  *
532  * Field Access Macros:
533  *
534  */
535 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_PERPLLLOST register field. */
536 #define ALT_CLKMGR_INTER_PERPLLLOST_LSB 4
537 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_PERPLLLOST register field. */
538 #define ALT_CLKMGR_INTER_PERPLLLOST_MSB 4
539 /* The width in bits of the ALT_CLKMGR_INTER_PERPLLLOST register field. */
540 #define ALT_CLKMGR_INTER_PERPLLLOST_WIDTH 1
541 /* The mask used to set the ALT_CLKMGR_INTER_PERPLLLOST register field value. */
542 #define ALT_CLKMGR_INTER_PERPLLLOST_SET_MSK 0x00000010
543 /* The mask used to clear the ALT_CLKMGR_INTER_PERPLLLOST register field value. */
544 #define ALT_CLKMGR_INTER_PERPLLLOST_CLR_MSK 0xffffffef
545 /* The reset value of the ALT_CLKMGR_INTER_PERPLLLOST register field. */
546 #define ALT_CLKMGR_INTER_PERPLLLOST_RESET 0x0
547 /* Extracts the ALT_CLKMGR_INTER_PERPLLLOST field value from a register. */
548 #define ALT_CLKMGR_INTER_PERPLLLOST_GET(value) (((value) & 0x00000010) >> 4)
549 /* Produces a ALT_CLKMGR_INTER_PERPLLLOST register field value suitable for setting the register. */
550 #define ALT_CLKMGR_INTER_PERPLLLOST_SET(value) (((value) << 4) & 0x00000010)
551 
552 /*
553  * Field : SDRAM PLL Lost Lock - sdrplllost
554  *
555  * If 1, the SDRAM PLL has lost lock at least once since this bit was cleared. If
556  * 0, the SDRAM PLL has not lost lock since this bit was cleared.
557  *
558  * Field Access Macros:
559  *
560  */
561 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */
562 #define ALT_CLKMGR_INTER_SDRPLLLOST_LSB 5
563 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */
564 #define ALT_CLKMGR_INTER_SDRPLLLOST_MSB 5
565 /* The width in bits of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */
566 #define ALT_CLKMGR_INTER_SDRPLLLOST_WIDTH 1
567 /* The mask used to set the ALT_CLKMGR_INTER_SDRPLLLOST register field value. */
568 #define ALT_CLKMGR_INTER_SDRPLLLOST_SET_MSK 0x00000020
569 /* The mask used to clear the ALT_CLKMGR_INTER_SDRPLLLOST register field value. */
570 #define ALT_CLKMGR_INTER_SDRPLLLOST_CLR_MSK 0xffffffdf
571 /* The reset value of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */
572 #define ALT_CLKMGR_INTER_SDRPLLLOST_RESET 0x0
573 /* Extracts the ALT_CLKMGR_INTER_SDRPLLLOST field value from a register. */
574 #define ALT_CLKMGR_INTER_SDRPLLLOST_GET(value) (((value) & 0x00000020) >> 5)
575 /* Produces a ALT_CLKMGR_INTER_SDRPLLLOST register field value suitable for setting the register. */
576 #define ALT_CLKMGR_INTER_SDRPLLLOST_SET(value) (((value) << 5) & 0x00000020)
577 
578 /*
579  * Field : Main PLL Current Lock Status - mainplllocked
580  *
581  * If 1, the Main PLL is currently locked. If 0, the Main PLL is currently not
582  * locked.
583  *
584  * Field Access Macros:
585  *
586  */
587 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field. */
588 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_LSB 6
589 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field. */
590 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_MSB 6
591 /* The width in bits of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field. */
592 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_WIDTH 1
593 /* The mask used to set the ALT_CLKMGR_INTER_MAINPLLLOCKED register field value. */
594 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK 0x00000040
595 /* The mask used to clear the ALT_CLKMGR_INTER_MAINPLLLOCKED register field value. */
596 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_CLR_MSK 0xffffffbf
597 /* The reset value of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field is UNKNOWN. */
598 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_RESET 0x0
599 /* Extracts the ALT_CLKMGR_INTER_MAINPLLLOCKED field value from a register. */
600 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_GET(value) (((value) & 0x00000040) >> 6)
601 /* Produces a ALT_CLKMGR_INTER_MAINPLLLOCKED register field value suitable for setting the register. */
602 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_SET(value) (((value) << 6) & 0x00000040)
603 
604 /*
605  * Field : Peripheral PLL Current Lock Status - perplllocked
606  *
607  * If 1, the Peripheral PLL is currently locked. If 0, the Peripheral PLL is
608  * currently not locked.
609  *
610  * Field Access Macros:
611  *
612  */
613 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_PERPLLLOCKED register field. */
614 #define ALT_CLKMGR_INTER_PERPLLLOCKED_LSB 7
615 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_PERPLLLOCKED register field. */
616 #define ALT_CLKMGR_INTER_PERPLLLOCKED_MSB 7
617 /* The width in bits of the ALT_CLKMGR_INTER_PERPLLLOCKED register field. */
618 #define ALT_CLKMGR_INTER_PERPLLLOCKED_WIDTH 1
619 /* The mask used to set the ALT_CLKMGR_INTER_PERPLLLOCKED register field value. */
620 #define ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK 0x00000080
621 /* The mask used to clear the ALT_CLKMGR_INTER_PERPLLLOCKED register field value. */
622 #define ALT_CLKMGR_INTER_PERPLLLOCKED_CLR_MSK 0xffffff7f
623 /* The reset value of the ALT_CLKMGR_INTER_PERPLLLOCKED register field is UNKNOWN. */
624 #define ALT_CLKMGR_INTER_PERPLLLOCKED_RESET 0x0
625 /* Extracts the ALT_CLKMGR_INTER_PERPLLLOCKED field value from a register. */
626 #define ALT_CLKMGR_INTER_PERPLLLOCKED_GET(value) (((value) & 0x00000080) >> 7)
627 /* Produces a ALT_CLKMGR_INTER_PERPLLLOCKED register field value suitable for setting the register. */
628 #define ALT_CLKMGR_INTER_PERPLLLOCKED_SET(value) (((value) << 7) & 0x00000080)
629 
630 /*
631  * Field : SDRAM PLL Current Lock Status - sdrplllocked
632  *
633  * If 1, the SDRAM PLL is currently locked. If 0, the SDRAM PLL is currently not
634  * locked.
635  *
636  * Field Access Macros:
637  *
638  */
639 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field. */
640 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_LSB 8
641 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field. */
642 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_MSB 8
643 /* The width in bits of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field. */
644 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_WIDTH 1
645 /* The mask used to set the ALT_CLKMGR_INTER_SDRPLLLOCKED register field value. */
646 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK 0x00000100
647 /* The mask used to clear the ALT_CLKMGR_INTER_SDRPLLLOCKED register field value. */
648 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_CLR_MSK 0xfffffeff
649 /* The reset value of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field is UNKNOWN. */
650 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_RESET 0x0
651 /* Extracts the ALT_CLKMGR_INTER_SDRPLLLOCKED field value from a register. */
652 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_GET(value) (((value) & 0x00000100) >> 8)
653 /* Produces a ALT_CLKMGR_INTER_SDRPLLLOCKED register field value suitable for setting the register. */
654 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_SET(value) (((value) << 8) & 0x00000100)
655 
656 #ifndef __ASSEMBLY__
657 /*
658  * WARNING: The C register and register group struct declarations are provided for
659  * convenience and illustrative purposes. They should, however, be used with
660  * caution as the C language standard provides no guarantees about the alignment or
661  * atomicity of device memory accesses. The recommended practice for writing
662  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
663  * alt_write_word() functions.
664  *
665  * The struct declaration for register ALT_CLKMGR_INTER.
666  */
667 struct ALT_CLKMGR_INTER_s
668 {
669  uint32_t mainpllachieved : 1; /* Main PLL Achieved Lock */
670  uint32_t perpllachieved : 1; /* Peripheral PLL Achieved Lock */
671  uint32_t sdrpllachieved : 1; /* SDRAM PLL Achieved Lock */
672  uint32_t mainplllost : 1; /* Main PLL Lost Lock */
673  uint32_t perplllost : 1; /* Peripheral PLL Lost Lock */
674  uint32_t sdrplllost : 1; /* SDRAM PLL Lost Lock */
675  const uint32_t mainplllocked : 1; /* Main PLL Current Lock Status */
676  const uint32_t perplllocked : 1; /* Peripheral PLL Current Lock Status */
677  const uint32_t sdrplllocked : 1; /* SDRAM PLL Current Lock Status */
678  uint32_t : 23; /* *UNDEFINED* */
679 };
680 
681 /* The typedef declaration for register ALT_CLKMGR_INTER. */
682 typedef volatile struct ALT_CLKMGR_INTER_s ALT_CLKMGR_INTER_t;
683 #endif /* __ASSEMBLY__ */
684 
685 /* The byte offset of the ALT_CLKMGR_INTER register from the beginning of the component. */
686 #define ALT_CLKMGR_INTER_OFST 0x8
687 
688 /*
689  * Register : Interrupt Enable Register - intren
690  *
691  * Contain fields that enable the interrupt.
692  *
693  * Fields are only reset by a cold reset.
694  *
695  * Register Layout
696  *
697  * Bits | Access | Reset | Description
698  * :-------|:-------|:------|:----------------------------------------------
699  * [0] | RW | 0x0 | Main PLL Achieved Lock Interrupt Enable
700  * [1] | RW | 0x0 | Peripheral PLL Achieved Lock Interrupt Enable
701  * [2] | RW | 0x0 | SDRAM PLL Achieved Lock Interrupt Enable
702  * [3] | RW | 0x0 | Main PLL Achieved Lock Interrupt Enable
703  * [4] | RW | 0x0 | Peripheral PLL Achieved Lock Interrupt Enable
704  * [5] | RW | 0x0 | SDRAM PLL Achieved Lock Interrupt Enable
705  * [31:6] | ??? | 0x0 | *UNDEFINED*
706  *
707  */
708 /*
709  * Field : Main PLL Achieved Lock Interrupt Enable - mainpllachieved
710  *
711  * When set to 1, the Main PLL achieved lock bit is ORed into the Clock Manager
712  * interrupt output. When set to 0 the Main PLL achieved lock bit is not ORed into
713  * the Clock Manager interrupt output.
714  *
715  * Field Access Macros:
716  *
717  */
718 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */
719 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_LSB 0
720 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */
721 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_MSB 0
722 /* The width in bits of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */
723 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_WIDTH 1
724 /* The mask used to set the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field value. */
725 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_SET_MSK 0x00000001
726 /* The mask used to clear the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field value. */
727 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_CLR_MSK 0xfffffffe
728 /* The reset value of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */
729 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_RESET 0x0
730 /* Extracts the ALT_CLKMGR_INTREN_MAINPLLACHIEVED field value from a register. */
731 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
732 /* Produces a ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field value suitable for setting the register. */
733 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001)
734 
735 /*
736  * Field : Peripheral PLL Achieved Lock Interrupt Enable - perpllachieved
737  *
738  * When set to 1, the Peripheral PLL achieved lock bit is ORed into the Clock
739  * Manager interrupt output. When set to 0 the Peripheral PLL achieved lock bit is
740  * not ORed into the Clock Manager interrupt output.
741  *
742  * Field Access Macros:
743  *
744  */
745 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */
746 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_LSB 1
747 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */
748 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_MSB 1
749 /* The width in bits of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */
750 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_WIDTH 1
751 /* The mask used to set the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field value. */
752 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_SET_MSK 0x00000002
753 /* The mask used to clear the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field value. */
754 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_CLR_MSK 0xfffffffd
755 /* The reset value of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */
756 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_RESET 0x0
757 /* Extracts the ALT_CLKMGR_INTREN_PERPLLACHIEVED field value from a register. */
758 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
759 /* Produces a ALT_CLKMGR_INTREN_PERPLLACHIEVED register field value suitable for setting the register. */
760 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002)
761 
762 /*
763  * Field : SDRAM PLL Achieved Lock Interrupt Enable - sdrpllachieved
764  *
765  * When set to 1, the SDRAM PLL achieved lock bit is ORed into the Clock Manager
766  * interrupt output. When set to 0 the SDRAM PLL achieved lock bit is not ORed
767  * into the Clock Manager interrupt output.
768  *
769  * Field Access Macros:
770  *
771  */
772 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */
773 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_LSB 2
774 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */
775 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_MSB 2
776 /* The width in bits of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */
777 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_WIDTH 1
778 /* The mask used to set the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field value. */
779 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_SET_MSK 0x00000004
780 /* The mask used to clear the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field value. */
781 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_CLR_MSK 0xfffffffb
782 /* The reset value of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */
783 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_RESET 0x0
784 /* Extracts the ALT_CLKMGR_INTREN_SDRPLLACHIEVED field value from a register. */
785 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_GET(value) (((value) & 0x00000004) >> 2)
786 /* Produces a ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field value suitable for setting the register. */
787 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_SET(value) (((value) << 2) & 0x00000004)
788 
789 /*
790  * Field : Main PLL Achieved Lock Interrupt Enable - mainplllost
791  *
792  * When set to 1, the Main PLL lost lock bit is ORed into the Clock Manager
793  * interrupt output. When set to 0 the Main PLL lost lock bit is not ORed into the
794  * Clock Manager interrupt output.
795  *
796  * Field Access Macros:
797  *
798  */
799 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */
800 #define ALT_CLKMGR_INTREN_MAINPLLLOST_LSB 3
801 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */
802 #define ALT_CLKMGR_INTREN_MAINPLLLOST_MSB 3
803 /* The width in bits of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */
804 #define ALT_CLKMGR_INTREN_MAINPLLLOST_WIDTH 1
805 /* The mask used to set the ALT_CLKMGR_INTREN_MAINPLLLOST register field value. */
806 #define ALT_CLKMGR_INTREN_MAINPLLLOST_SET_MSK 0x00000008
807 /* The mask used to clear the ALT_CLKMGR_INTREN_MAINPLLLOST register field value. */
808 #define ALT_CLKMGR_INTREN_MAINPLLLOST_CLR_MSK 0xfffffff7
809 /* The reset value of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */
810 #define ALT_CLKMGR_INTREN_MAINPLLLOST_RESET 0x0
811 /* Extracts the ALT_CLKMGR_INTREN_MAINPLLLOST field value from a register. */
812 #define ALT_CLKMGR_INTREN_MAINPLLLOST_GET(value) (((value) & 0x00000008) >> 3)
813 /* Produces a ALT_CLKMGR_INTREN_MAINPLLLOST register field value suitable for setting the register. */
814 #define ALT_CLKMGR_INTREN_MAINPLLLOST_SET(value) (((value) << 3) & 0x00000008)
815 
816 /*
817  * Field : Peripheral PLL Achieved Lock Interrupt Enable - perplllost
818  *
819  * When set to 1, the Peripheral PLL lost lock bit is ORed into the Clock Manager
820  * interrupt output. When set to 0 the Peripheral PLL lost lock bit is not ORed
821  * into the Clock Manager interrupt output.
822  *
823  * Field Access Macros:
824  *
825  */
826 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */
827 #define ALT_CLKMGR_INTREN_PERPLLLOST_LSB 4
828 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */
829 #define ALT_CLKMGR_INTREN_PERPLLLOST_MSB 4
830 /* The width in bits of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */
831 #define ALT_CLKMGR_INTREN_PERPLLLOST_WIDTH 1
832 /* The mask used to set the ALT_CLKMGR_INTREN_PERPLLLOST register field value. */
833 #define ALT_CLKMGR_INTREN_PERPLLLOST_SET_MSK 0x00000010
834 /* The mask used to clear the ALT_CLKMGR_INTREN_PERPLLLOST register field value. */
835 #define ALT_CLKMGR_INTREN_PERPLLLOST_CLR_MSK 0xffffffef
836 /* The reset value of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */
837 #define ALT_CLKMGR_INTREN_PERPLLLOST_RESET 0x0
838 /* Extracts the ALT_CLKMGR_INTREN_PERPLLLOST field value from a register. */
839 #define ALT_CLKMGR_INTREN_PERPLLLOST_GET(value) (((value) & 0x00000010) >> 4)
840 /* Produces a ALT_CLKMGR_INTREN_PERPLLLOST register field value suitable for setting the register. */
841 #define ALT_CLKMGR_INTREN_PERPLLLOST_SET(value) (((value) << 4) & 0x00000010)
842 
843 /*
844  * Field : SDRAM PLL Achieved Lock Interrupt Enable - sdrplllost
845  *
846  * When set to 1, the SDRAM PLL lost lock bit is ORed into the Clock Manager
847  * interrupt output. When set to 0 the SDRAM PLL lost lock bit is not ORed into
848  * the Clock Manager interrupt output.
849  *
850  * Field Access Macros:
851  *
852  */
853 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */
854 #define ALT_CLKMGR_INTREN_SDRPLLLOST_LSB 5
855 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */
856 #define ALT_CLKMGR_INTREN_SDRPLLLOST_MSB 5
857 /* The width in bits of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */
858 #define ALT_CLKMGR_INTREN_SDRPLLLOST_WIDTH 1
859 /* The mask used to set the ALT_CLKMGR_INTREN_SDRPLLLOST register field value. */
860 #define ALT_CLKMGR_INTREN_SDRPLLLOST_SET_MSK 0x00000020
861 /* The mask used to clear the ALT_CLKMGR_INTREN_SDRPLLLOST register field value. */
862 #define ALT_CLKMGR_INTREN_SDRPLLLOST_CLR_MSK 0xffffffdf
863 /* The reset value of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */
864 #define ALT_CLKMGR_INTREN_SDRPLLLOST_RESET 0x0
865 /* Extracts the ALT_CLKMGR_INTREN_SDRPLLLOST field value from a register. */
866 #define ALT_CLKMGR_INTREN_SDRPLLLOST_GET(value) (((value) & 0x00000020) >> 5)
867 /* Produces a ALT_CLKMGR_INTREN_SDRPLLLOST register field value suitable for setting the register. */
868 #define ALT_CLKMGR_INTREN_SDRPLLLOST_SET(value) (((value) << 5) & 0x00000020)
869 
870 #ifndef __ASSEMBLY__
871 /*
872  * WARNING: The C register and register group struct declarations are provided for
873  * convenience and illustrative purposes. They should, however, be used with
874  * caution as the C language standard provides no guarantees about the alignment or
875  * atomicity of device memory accesses. The recommended practice for writing
876  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
877  * alt_write_word() functions.
878  *
879  * The struct declaration for register ALT_CLKMGR_INTREN.
880  */
881 struct ALT_CLKMGR_INTREN_s
882 {
883  uint32_t mainpllachieved : 1; /* Main PLL Achieved Lock Interrupt Enable */
884  uint32_t perpllachieved : 1; /* Peripheral PLL Achieved Lock Interrupt Enable */
885  uint32_t sdrpllachieved : 1; /* SDRAM PLL Achieved Lock Interrupt Enable */
886  uint32_t mainplllost : 1; /* Main PLL Achieved Lock Interrupt Enable */
887  uint32_t perplllost : 1; /* Peripheral PLL Achieved Lock Interrupt Enable */
888  uint32_t sdrplllost : 1; /* SDRAM PLL Achieved Lock Interrupt Enable */
889  uint32_t : 26; /* *UNDEFINED* */
890 };
891 
892 /* The typedef declaration for register ALT_CLKMGR_INTREN. */
893 typedef volatile struct ALT_CLKMGR_INTREN_s ALT_CLKMGR_INTREN_t;
894 #endif /* __ASSEMBLY__ */
895 
896 /* The byte offset of the ALT_CLKMGR_INTREN register from the beginning of the component. */
897 #define ALT_CLKMGR_INTREN_OFST 0xc
898 
899 /*
900  * Register : Debug clock Control Register - dbctrl
901  *
902  * Contains fields that control the debug clocks.
903  *
904  * Register Layout
905  *
906  * Bits | Access | Reset | Description
907  * :-------|:-------|:------|:-------------------------------
908  * [0] | RW | 0x1 | Debug Clocks Stay on EOSC1_CLK
909  * [1] | RW | 0x1 | Debug Clocks Enable Safe Mode
910  * [31:2] | ??? | 0x0 | *UNDEFINED*
911  *
912  */
913 /*
914  * Field : Debug Clocks Stay on EOSC1_CLK - stayosc1
915  *
916  * When this bit is set the debug root clock (Main PLL C2 output) will always be
917  * bypassed to the EOSC1_clk independent of any other clock manager settings.
918  * When clear the debug source will be a function of register settings in the clock
919  * manager. Clocks affected by this bit are dbg_at_clk, dbg_clk, dbg_trace_clk,
920  * and dbg_timer_clk.
921  *
922  * The reset value for this bit is applied on a cold reset. Warm reset has no
923  * affect on this bit.
924  *
925  * Field Access Macros:
926  *
927  */
928 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */
929 #define ALT_CLKMGR_DBCTL_STAYOSC1_LSB 0
930 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */
931 #define ALT_CLKMGR_DBCTL_STAYOSC1_MSB 0
932 /* The width in bits of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */
933 #define ALT_CLKMGR_DBCTL_STAYOSC1_WIDTH 1
934 /* The mask used to set the ALT_CLKMGR_DBCTL_STAYOSC1 register field value. */
935 #define ALT_CLKMGR_DBCTL_STAYOSC1_SET_MSK 0x00000001
936 /* The mask used to clear the ALT_CLKMGR_DBCTL_STAYOSC1 register field value. */
937 #define ALT_CLKMGR_DBCTL_STAYOSC1_CLR_MSK 0xfffffffe
938 /* The reset value of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */
939 #define ALT_CLKMGR_DBCTL_STAYOSC1_RESET 0x1
940 /* Extracts the ALT_CLKMGR_DBCTL_STAYOSC1 field value from a register. */
941 #define ALT_CLKMGR_DBCTL_STAYOSC1_GET(value) (((value) & 0x00000001) >> 0)
942 /* Produces a ALT_CLKMGR_DBCTL_STAYOSC1 register field value suitable for setting the register. */
943 #define ALT_CLKMGR_DBCTL_STAYOSC1_SET(value) (((value) << 0) & 0x00000001)
944 
945 /*
946  * Field : Debug Clocks Enable Safe Mode - ensfmdwr
947  *
948  * When this bit is set the debug clocks will be affected by the assertion of Safe
949  * Mode on a warm reset if Stay OSC1 is not set.
950  *
951  * When this bit is clear the debug clocks will not be affected by the assertion of
952  * Safe Mode on a warm reset.
953  *
954  * If Debug Clocks are in Safe Mode they are taken out of Safe Mode when the Safe
955  * Mode bit is cleared independent of this bit.The reset value of this bit is
956  * applied on a cold reset; warm reset has no affect on this bit.
957  *
958  * Field Access Macros:
959  *
960  */
961 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */
962 #define ALT_CLKMGR_DBCTL_ENSFMDWR_LSB 1
963 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */
964 #define ALT_CLKMGR_DBCTL_ENSFMDWR_MSB 1
965 /* The width in bits of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */
966 #define ALT_CLKMGR_DBCTL_ENSFMDWR_WIDTH 1
967 /* The mask used to set the ALT_CLKMGR_DBCTL_ENSFMDWR register field value. */
968 #define ALT_CLKMGR_DBCTL_ENSFMDWR_SET_MSK 0x00000002
969 /* The mask used to clear the ALT_CLKMGR_DBCTL_ENSFMDWR register field value. */
970 #define ALT_CLKMGR_DBCTL_ENSFMDWR_CLR_MSK 0xfffffffd
971 /* The reset value of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */
972 #define ALT_CLKMGR_DBCTL_ENSFMDWR_RESET 0x1
973 /* Extracts the ALT_CLKMGR_DBCTL_ENSFMDWR field value from a register. */
974 #define ALT_CLKMGR_DBCTL_ENSFMDWR_GET(value) (((value) & 0x00000002) >> 1)
975 /* Produces a ALT_CLKMGR_DBCTL_ENSFMDWR register field value suitable for setting the register. */
976 #define ALT_CLKMGR_DBCTL_ENSFMDWR_SET(value) (((value) << 1) & 0x00000002)
977 
978 #ifndef __ASSEMBLY__
979 /*
980  * WARNING: The C register and register group struct declarations are provided for
981  * convenience and illustrative purposes. They should, however, be used with
982  * caution as the C language standard provides no guarantees about the alignment or
983  * atomicity of device memory accesses. The recommended practice for writing
984  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
985  * alt_write_word() functions.
986  *
987  * The struct declaration for register ALT_CLKMGR_DBCTL.
988  */
989 struct ALT_CLKMGR_DBCTL_s
990 {
991  uint32_t stayosc1 : 1; /* Debug Clocks Stay on EOSC1_CLK */
992  uint32_t ensfmdwr : 1; /* Debug Clocks Enable Safe Mode */
993  uint32_t : 30; /* *UNDEFINED* */
994 };
995 
996 /* The typedef declaration for register ALT_CLKMGR_DBCTL. */
997 typedef volatile struct ALT_CLKMGR_DBCTL_s ALT_CLKMGR_DBCTL_t;
998 #endif /* __ASSEMBLY__ */
999 
1000 /* The byte offset of the ALT_CLKMGR_DBCTL register from the beginning of the component. */
1001 #define ALT_CLKMGR_DBCTL_OFST 0x10
1002 
1003 /*
1004  * Register : Status Register - stat
1005  *
1006  * Provides status of Hardware Managed Clock transition State Machine.
1007  *
1008  * Register Layout
1009  *
1010  * Bits | Access | Reset | Description
1011  * :-------|:-------|:------|:-----------------------
1012  * [0] | R | 0x0 | HW Managed Clocks BUSY
1013  * [31:1] | ??? | 0x0 | *UNDEFINED*
1014  *
1015  */
1016 /*
1017  * Field : HW Managed Clocks BUSY - busy
1018  *
1019  * This read only bit indicates that the Hardware Managed clock's state machine is
1020  * active. If the state machine is active, then the clocks are in transition.
1021  * Software should poll this bit after changing the source of internal clocks when
1022  * writing to the BYPASS, CTRL or DBCTRL registers. Immediately following writes
1023  * to any of these registers, SW should wait until this bit is IDLE before
1024  * proceeding with any other register writes in the Clock Manager.
1025  *
1026  * The reset value of this bit is applied on a cold reset; warm reset has no affect
1027  * on this bit.
1028  *
1029  * Field Enumeration Values:
1030  *
1031  * Enum | Value | Description
1032  * :----------------------------|:------|:---------------------
1033  * ALT_CLKMGR_STAT_BUSY_E_IDLE | 0x0 | Clocks stable
1034  * ALT_CLKMGR_STAT_BUSY_E_BUSY | 0x1 | Clocks in transition
1035  *
1036  * Field Access Macros:
1037  *
1038  */
1039 /*
1040  * Enumerated value for register field ALT_CLKMGR_STAT_BUSY
1041  *
1042  * Clocks stable
1043  */
1044 #define ALT_CLKMGR_STAT_BUSY_E_IDLE 0x0
1045 /*
1046  * Enumerated value for register field ALT_CLKMGR_STAT_BUSY
1047  *
1048  * Clocks in transition
1049  */
1050 #define ALT_CLKMGR_STAT_BUSY_E_BUSY 0x1
1051 
1052 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_STAT_BUSY register field. */
1053 #define ALT_CLKMGR_STAT_BUSY_LSB 0
1054 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_STAT_BUSY register field. */
1055 #define ALT_CLKMGR_STAT_BUSY_MSB 0
1056 /* The width in bits of the ALT_CLKMGR_STAT_BUSY register field. */
1057 #define ALT_CLKMGR_STAT_BUSY_WIDTH 1
1058 /* The mask used to set the ALT_CLKMGR_STAT_BUSY register field value. */
1059 #define ALT_CLKMGR_STAT_BUSY_SET_MSK 0x00000001
1060 /* The mask used to clear the ALT_CLKMGR_STAT_BUSY register field value. */
1061 #define ALT_CLKMGR_STAT_BUSY_CLR_MSK 0xfffffffe
1062 /* The reset value of the ALT_CLKMGR_STAT_BUSY register field. */
1063 #define ALT_CLKMGR_STAT_BUSY_RESET 0x0
1064 /* Extracts the ALT_CLKMGR_STAT_BUSY field value from a register. */
1065 #define ALT_CLKMGR_STAT_BUSY_GET(value) (((value) & 0x00000001) >> 0)
1066 /* Produces a ALT_CLKMGR_STAT_BUSY register field value suitable for setting the register. */
1067 #define ALT_CLKMGR_STAT_BUSY_SET(value) (((value) << 0) & 0x00000001)
1068 
1069 #ifndef __ASSEMBLY__
1070 /*
1071  * WARNING: The C register and register group struct declarations are provided for
1072  * convenience and illustrative purposes. They should, however, be used with
1073  * caution as the C language standard provides no guarantees about the alignment or
1074  * atomicity of device memory accesses. The recommended practice for writing
1075  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1076  * alt_write_word() functions.
1077  *
1078  * The struct declaration for register ALT_CLKMGR_STAT.
1079  */
1080 struct ALT_CLKMGR_STAT_s
1081 {
1082  const uint32_t busy : 1; /* HW Managed Clocks BUSY */
1083  uint32_t : 31; /* *UNDEFINED* */
1084 };
1085 
1086 /* The typedef declaration for register ALT_CLKMGR_STAT. */
1087 typedef volatile struct ALT_CLKMGR_STAT_s ALT_CLKMGR_STAT_t;
1088 #endif /* __ASSEMBLY__ */
1089 
1090 /* The byte offset of the ALT_CLKMGR_STAT register from the beginning of the component. */
1091 #define ALT_CLKMGR_STAT_OFST 0x14
1092 
1093 /*
1094  * Register Group : Main PLL Group - ALT_CLKMGR_MAINPLL
1095  * Main PLL Group
1096  *
1097  * Contains registers with settings for the Main PLL.
1098  *
1099  */
1100 /*
1101  * Register : Main PLL VCO Control Register - vco
1102  *
1103  * Contains settings that control the Main PLL VCO. The VCO output frequency is the
1104  * input frequency multiplied by the numerator (M+1) and divided by the denominator
1105  * (N+1). The VCO input clock source is always eosc1_clk.
1106  *
1107  * Fields are only reset by a cold reset.
1108  *
1109  * Register Layout
1110  *
1111  * Bits | Access | Reset | Description
1112  * :--------|:-------|:------|:--------------------------------
1113  * [0] | RW | 0x1 | BG PWRDN
1114  * [1] | RW | 0x0 | Enable
1115  * [2] | RW | 0x1 | Power down
1116  * [15:3] | RW | 0x1 | Numerator (M)
1117  * [21:16] | RW | 0x1 | Denominator (N)
1118  * [23:22] | ??? | 0x0 | *UNDEFINED*
1119  * [24] | RW | 0x0 | All Output Counter Reset
1120  * [30:25] | RW | 0x0 | Output Counter Reset
1121  * [31] | RW | 0x1 | External Regulator Input Select
1122  *
1123  */
1124 /*
1125  * Field : BG PWRDN - bgpwrdn
1126  *
1127  * If '1', powers down bandgap. If '0', bandgap is not power down.
1128  *
1129  * Field Access Macros:
1130  *
1131  */
1132 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */
1133 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_LSB 0
1134 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */
1135 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_MSB 0
1136 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */
1137 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_WIDTH 1
1138 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field value. */
1139 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_SET_MSK 0x00000001
1140 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field value. */
1141 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe
1142 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */
1143 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_RESET 0x1
1144 /* Extracts the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN field value from a register. */
1145 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0)
1146 /* Produces a ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field value suitable for setting the register. */
1147 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001)
1148 
1149 /*
1150  * Field : Enable - en
1151  *
1152  * If '1', VCO is enabled. If '0', VCO is in reset.
1153  *
1154  * Field Access Macros:
1155  *
1156  */
1157 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */
1158 #define ALT_CLKMGR_MAINPLL_VCO_EN_LSB 1
1159 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */
1160 #define ALT_CLKMGR_MAINPLL_VCO_EN_MSB 1
1161 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */
1162 #define ALT_CLKMGR_MAINPLL_VCO_EN_WIDTH 1
1163 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_EN register field value. */
1164 #define ALT_CLKMGR_MAINPLL_VCO_EN_SET_MSK 0x00000002
1165 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_EN register field value. */
1166 #define ALT_CLKMGR_MAINPLL_VCO_EN_CLR_MSK 0xfffffffd
1167 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */
1168 #define ALT_CLKMGR_MAINPLL_VCO_EN_RESET 0x0
1169 /* Extracts the ALT_CLKMGR_MAINPLL_VCO_EN field value from a register. */
1170 #define ALT_CLKMGR_MAINPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1)
1171 /* Produces a ALT_CLKMGR_MAINPLL_VCO_EN register field value suitable for setting the register. */
1172 #define ALT_CLKMGR_MAINPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002)
1173 
1174 /*
1175  * Field : Power down - pwrdn
1176  *
1177  * If '1', power down analog circuitry. If '0', analog circuitry not powered down.
1178  *
1179  * Field Access Macros:
1180  *
1181  */
1182 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */
1183 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_LSB 2
1184 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */
1185 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_MSB 2
1186 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */
1187 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_WIDTH 1
1188 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field value. */
1189 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_SET_MSK 0x00000004
1190 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field value. */
1191 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_CLR_MSK 0xfffffffb
1192 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */
1193 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_RESET 0x1
1194 /* Extracts the ALT_CLKMGR_MAINPLL_VCO_PWRDN field value from a register. */
1195 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2)
1196 /* Produces a ALT_CLKMGR_MAINPLL_VCO_PWRDN register field value suitable for setting the register. */
1197 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004)
1198 
1199 /*
1200  * Field : Numerator (M) - numer
1201  *
1202  * Numerator in VCO output frequency equation. For incremental frequency change, if
1203  * the new value lead to less than 20% of the frequency change, this value can be
1204  * changed without resetting the PLL. The Numerator and Denominator can not be
1205  * changed at the same time for incremental frequency changed.
1206  *
1207  * Field Access Macros:
1208  *
1209  */
1210 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */
1211 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_LSB 3
1212 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */
1213 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_MSB 15
1214 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */
1215 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_WIDTH 13
1216 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_NUMER register field value. */
1217 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_SET_MSK 0x0000fff8
1218 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_NUMER register field value. */
1219 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_CLR_MSK 0xffff0007
1220 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */
1221 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_RESET 0x1
1222 /* Extracts the ALT_CLKMGR_MAINPLL_VCO_NUMER field value from a register. */
1223 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3)
1224 /* Produces a ALT_CLKMGR_MAINPLL_VCO_NUMER register field value suitable for setting the register. */
1225 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8)
1226 
1227 /*
1228  * Field : Denominator (N) - denom
1229  *
1230  * Denominator in VCO output frequency equation. For incremental frequency change,
1231  * if the new value lead to less than 20% of the frequency change, this value can
1232  * be changed without resetting the PLL. The Numerator and Denominator can not be
1233  * changed at the same time for incremental frequency changed.
1234  *
1235  * Field Access Macros:
1236  *
1237  */
1238 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */
1239 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_LSB 16
1240 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */
1241 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_MSB 21
1242 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */
1243 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_WIDTH 6
1244 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_DENOM register field value. */
1245 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_SET_MSK 0x003f0000
1246 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_DENOM register field value. */
1247 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_CLR_MSK 0xffc0ffff
1248 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */
1249 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_RESET 0x1
1250 /* Extracts the ALT_CLKMGR_MAINPLL_VCO_DENOM field value from a register. */
1251 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16)
1252 /* Produces a ALT_CLKMGR_MAINPLL_VCO_DENOM register field value suitable for setting the register. */
1253 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000)
1254 
1255 /*
1256  * Field : All Output Counter Reset - outresetall
1257  *
1258  * Before releasing Bypass, All Output Counter Reset must be set and cleared by
1259  * software for correct clock operation.
1260  *
1261  * If '1', Reset phase multiplexer and all output counter state. So that after the
1262  * assertion all the clocks output are start from rising edge align.
1263  *
1264  * If '0', phase multiplexer and output counter state not reset and no change to
1265  * the phase of the clock outputs.
1266  *
1267  * Field Access Macros:
1268  *
1269  */
1270 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */
1271 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_LSB 24
1272 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */
1273 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_MSB 24
1274 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */
1275 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_WIDTH 1
1276 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field value. */
1277 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET_MSK 0x01000000
1278 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field value. */
1279 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff
1280 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */
1281 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_RESET 0x0
1282 /* Extracts the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL field value from a register. */
1283 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24)
1284 /* Produces a ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field value suitable for setting the register. */
1285 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000)
1286 
1287 /*
1288  * Field : Output Counter Reset - outreset
1289  *
1290  * Resets the individual PLL output counter.
1291  *
1292  * For software to change the PLL output counter without producing glitches on the
1293  * respective clock, SW must set the VCO register respective Output Counter Reset
1294  * bit. Software then polls the respective Output Counter Reset Acknowledge bit in
1295  * the Output Counter Reset Ack Status Register. Software then writes the
1296  * appropriate counter register, and then clears the respective VCO register Output
1297  * Counter Reset bit.
1298  *
1299  * LSB 'outreset[0]' corresponds to PLL output clock C0, etc.
1300  *
1301  * If set to '1', reset output divider, no clock output from counter.
1302  *
1303  * If set to '0', counter is not reset.
1304  *
1305  * The reset value of this bit is applied on a cold reset; warm reset has no affect
1306  * on this bit.
1307  *
1308  * Field Access Macros:
1309  *
1310  */
1311 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */
1312 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB 25
1313 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */
1314 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_MSB 30
1315 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */
1316 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_WIDTH 6
1317 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field value. */
1318 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_SET_MSK 0x7e000000
1319 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field value. */
1320 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_CLR_MSK 0x81ffffff
1321 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */
1322 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_RESET 0x0
1323 /* Extracts the ALT_CLKMGR_MAINPLL_VCO_OUTRST field value from a register. */
1324 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25)
1325 /* Produces a ALT_CLKMGR_MAINPLL_VCO_OUTRST register field value suitable for setting the register. */
1326 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000)
1327 
1328 /*
1329  * Field : External Regulator Input Select - regextsel
1330  *
1331  * If set to '1', the external regulator is selected for the PLL.
1332  *
1333  * If set to '0', the internal regulator is slected.
1334  *
1335  * It is strongly recommended to select the external regulator while the PLL is not
1336  * enabled (in reset), and then disable the external regulater once the PLL
1337  * becomes enabled. Software should simulateously update the 'Enable' bit and the
1338  * 'External Regulator Input Select' in the same write access to the VCO register.
1339  * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be
1340  * set, and vice versa.
1341  *
1342  * The reset value of this bit is applied on a cold reset; warm reset has no affect
1343  * on this bit.
1344  *
1345  * Field Access Macros:
1346  *
1347  */
1348 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */
1349 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_LSB 31
1350 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */
1351 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_MSB 31
1352 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */
1353 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_WIDTH 1
1354 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field value. */
1355 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_SET_MSK 0x80000000
1356 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field value. */
1357 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff
1358 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */
1359 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_RESET 0x1
1360 /* Extracts the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL field value from a register. */
1361 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31)
1362 /* Produces a ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field value suitable for setting the register. */
1363 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000)
1364 
1365 #ifndef __ASSEMBLY__
1366 /*
1367  * WARNING: The C register and register group struct declarations are provided for
1368  * convenience and illustrative purposes. They should, however, be used with
1369  * caution as the C language standard provides no guarantees about the alignment or
1370  * atomicity of device memory accesses. The recommended practice for writing
1371  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1372  * alt_write_word() functions.
1373  *
1374  * The struct declaration for register ALT_CLKMGR_MAINPLL_VCO.
1375  */
1376 struct ALT_CLKMGR_MAINPLL_VCO_s
1377 {
1378  uint32_t bgpwrdn : 1; /* BG PWRDN */
1379  uint32_t en : 1; /* Enable */
1380  uint32_t pwrdn : 1; /* Power down */
1381  uint32_t numer : 13; /* Numerator (M) */
1382  uint32_t denom : 6; /* Denominator (N) */
1383  uint32_t : 2; /* *UNDEFINED* */
1384  uint32_t outresetall : 1; /* All Output Counter Reset */
1385  uint32_t outreset : 6; /* Output Counter Reset */
1386  uint32_t regextsel : 1; /* External Regulator Input Select */
1387 };
1388 
1389 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_VCO. */
1390 typedef volatile struct ALT_CLKMGR_MAINPLL_VCO_s ALT_CLKMGR_MAINPLL_VCO_t;
1391 #endif /* __ASSEMBLY__ */
1392 
1393 /* The byte offset of the ALT_CLKMGR_MAINPLL_VCO register from the beginning of the component. */
1394 #define ALT_CLKMGR_MAINPLL_VCO_OFST 0x0
1395 
1396 /*
1397  * Register : Main PLL VCO Advanced Control Register - misc
1398  *
1399  * Contains VCO control signals and other PLL control signals need to be
1400  * controllable through register.
1401  *
1402  * Fields are only reset by a cold reset.
1403  *
1404  * Register Layout
1405  *
1406  * Bits | Access | Reset | Description
1407  * :--------|:-------|:------|:------------------------------
1408  * [0] | RW | 0x0 | Loop Bandwidth Adjust Enabled
1409  * [12:1] | RW | 0x1 | Loop Bandwidth Adjust
1410  * [13] | RW | 0x0 | Fast Locking Enable
1411  * [14] | RW | 0x1 | Saturation Enable
1412  * [31:15] | ??? | 0x0 | *UNDEFINED*
1413  *
1414  */
1415 /*
1416  * Field : Loop Bandwidth Adjust Enabled - bwadjen
1417  *
1418  * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth
1419  * Adjust field.
1420  *
1421  * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2
1422  * value of the VCO Control Register. The M divided by 2 is the upper 12 bits
1423  * (12:1) of the M field in the VCO register.
1424  *
1425  * Field Access Macros:
1426  *
1427  */
1428 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */
1429 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_LSB 0
1430 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */
1431 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_MSB 0
1432 /* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */
1433 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_WIDTH 1
1434 /* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field value. */
1435 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_SET_MSK 0x00000001
1436 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field value. */
1437 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_CLR_MSK 0xfffffffe
1438 /* The reset value of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */
1439 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_RESET 0x0
1440 /* Extracts the ALT_CLKMGR_MAINPLL_MISC_BWADJEN field value from a register. */
1441 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_GET(value) (((value) & 0x00000001) >> 0)
1442 /* Produces a ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field value suitable for setting the register. */
1443 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_SET(value) (((value) << 0) & 0x00000001)
1444 
1445 /*
1446  * Field : Loop Bandwidth Adjust - bwadj
1447  *
1448  * Provides Loop Bandwidth Adjust value.
1449  *
1450  * Field Access Macros:
1451  *
1452  */
1453 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */
1454 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_LSB 1
1455 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */
1456 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_MSB 12
1457 /* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */
1458 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_WIDTH 12
1459 /* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field value. */
1460 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_SET_MSK 0x00001ffe
1461 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field value. */
1462 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_CLR_MSK 0xffffe001
1463 /* The reset value of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */
1464 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_RESET 0x1
1465 /* Extracts the ALT_CLKMGR_MAINPLL_MISC_BWADJ field value from a register. */
1466 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1)
1467 /* Produces a ALT_CLKMGR_MAINPLL_MISC_BWADJ register field value suitable for setting the register. */
1468 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_SET(value) (((value) << 1) & 0x00001ffe)
1469 
1470 /*
1471  * Field : Fast Locking Enable - fasten
1472  *
1473  * Enables fast locking circuit.
1474  *
1475  * Field Access Macros:
1476  *
1477  */
1478 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */
1479 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_LSB 13
1480 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */
1481 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_MSB 13
1482 /* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */
1483 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_WIDTH 1
1484 /* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field value. */
1485 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_SET_MSK 0x00002000
1486 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field value. */
1487 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_CLR_MSK 0xffffdfff
1488 /* The reset value of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */
1489 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_RESET 0x0
1490 /* Extracts the ALT_CLKMGR_MAINPLL_MISC_FASTEN field value from a register. */
1491 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_GET(value) (((value) & 0x00002000) >> 13)
1492 /* Produces a ALT_CLKMGR_MAINPLL_MISC_FASTEN register field value suitable for setting the register. */
1493 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_SET(value) (((value) << 13) & 0x00002000)
1494 
1495 /*
1496  * Field : Saturation Enable - saten
1497  *
1498  * Enables saturation behavior.
1499  *
1500  * Field Access Macros:
1501  *
1502  */
1503 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */
1504 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_LSB 14
1505 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */
1506 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_MSB 14
1507 /* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */
1508 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_WIDTH 1
1509 /* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_SATEN register field value. */
1510 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_SET_MSK 0x00004000
1511 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_SATEN register field value. */
1512 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_CLR_MSK 0xffffbfff
1513 /* The reset value of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */
1514 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_RESET 0x1
1515 /* Extracts the ALT_CLKMGR_MAINPLL_MISC_SATEN field value from a register. */
1516 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_GET(value) (((value) & 0x00004000) >> 14)
1517 /* Produces a ALT_CLKMGR_MAINPLL_MISC_SATEN register field value suitable for setting the register. */
1518 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_SET(value) (((value) << 14) & 0x00004000)
1519 
1520 #ifndef __ASSEMBLY__
1521 /*
1522  * WARNING: The C register and register group struct declarations are provided for
1523  * convenience and illustrative purposes. They should, however, be used with
1524  * caution as the C language standard provides no guarantees about the alignment or
1525  * atomicity of device memory accesses. The recommended practice for writing
1526  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1527  * alt_write_word() functions.
1528  *
1529  * The struct declaration for register ALT_CLKMGR_MAINPLL_MISC.
1530  */
1531 struct ALT_CLKMGR_MAINPLL_MISC_s
1532 {
1533  uint32_t bwadjen : 1; /* Loop Bandwidth Adjust Enabled */
1534  uint32_t bwadj : 12; /* Loop Bandwidth Adjust */
1535  uint32_t fasten : 1; /* Fast Locking Enable */
1536  uint32_t saten : 1; /* Saturation Enable */
1537  uint32_t : 17; /* *UNDEFINED* */
1538 };
1539 
1540 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_MISC. */
1541 typedef volatile struct ALT_CLKMGR_MAINPLL_MISC_s ALT_CLKMGR_MAINPLL_MISC_t;
1542 #endif /* __ASSEMBLY__ */
1543 
1544 /* The byte offset of the ALT_CLKMGR_MAINPLL_MISC register from the beginning of the component. */
1545 #define ALT_CLKMGR_MAINPLL_MISC_OFST 0x4
1546 
1547 /*
1548  * Register : Main PLL C0 Control Register for Clock mpu_clk - mpuclk
1549  *
1550  * Contains settings that control clock mpu_clk generated from the C0 output of the
1551  * Main PLL.
1552  *
1553  * Only reset by a cold reset.
1554  *
1555  * Register Layout
1556  *
1557  * Bits | Access | Reset | Description
1558  * :-------|:-------|:------|:------------
1559  * [8:0] | RW | 0x0 | Counter
1560  * [31:9] | ??? | 0x0 | *UNDEFINED*
1561  *
1562  */
1563 /*
1564  * Field : Counter - cnt
1565  *
1566  * Divides the VCO/2 frequency by the value+1 in this field.
1567  *
1568  * Field Access Macros:
1569  *
1570  */
1571 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */
1572 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_LSB 0
1573 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */
1574 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_MSB 8
1575 /* The width in bits of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */
1576 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_WIDTH 9
1577 /* The mask used to set the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value. */
1578 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET_MSK 0x000001ff
1579 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value. */
1580 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_CLR_MSK 0xfffffe00
1581 /* The reset value of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */
1582 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_RESET 0x0
1583 /* Extracts the ALT_CLKMGR_MAINPLL_MPUCLK_CNT field value from a register. */
1584 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1585 /* Produces a ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value suitable for setting the register. */
1586 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1587 
1588 #ifndef __ASSEMBLY__
1589 /*
1590  * WARNING: The C register and register group struct declarations are provided for
1591  * convenience and illustrative purposes. They should, however, be used with
1592  * caution as the C language standard provides no guarantees about the alignment or
1593  * atomicity of device memory accesses. The recommended practice for writing
1594  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1595  * alt_write_word() functions.
1596  *
1597  * The struct declaration for register ALT_CLKMGR_MAINPLL_MPUCLK.
1598  */
1599 struct ALT_CLKMGR_MAINPLL_MPUCLK_s
1600 {
1601  uint32_t cnt : 9; /* Counter */
1602  uint32_t : 23; /* *UNDEFINED* */
1603 };
1604 
1605 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_MPUCLK. */
1606 typedef volatile struct ALT_CLKMGR_MAINPLL_MPUCLK_s ALT_CLKMGR_MAINPLL_MPUCLK_t;
1607 #endif /* __ASSEMBLY__ */
1608 
1609 /* The byte offset of the ALT_CLKMGR_MAINPLL_MPUCLK register from the beginning of the component. */
1610 #define ALT_CLKMGR_MAINPLL_MPUCLK_OFST 0x8
1611 
1612 /*
1613  * Register : Main PLL C1 Control Register for Clock main_clk - mainclk
1614  *
1615  * Contains settings that control clock main_clk generated from the C1 output of
1616  * the Main PLL.
1617  *
1618  * Only reset by a cold reset.
1619  *
1620  * Register Layout
1621  *
1622  * Bits | Access | Reset | Description
1623  * :-------|:-------|:------|:------------
1624  * [8:0] | RW | 0x0 | Counter
1625  * [31:9] | ??? | 0x0 | *UNDEFINED*
1626  *
1627  */
1628 /*
1629  * Field : Counter - cnt
1630  *
1631  * Divides the VCO/4 frequency by the value+1 in this field.
1632  *
1633  * Field Access Macros:
1634  *
1635  */
1636 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */
1637 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_LSB 0
1638 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */
1639 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_MSB 8
1640 /* The width in bits of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */
1641 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_WIDTH 9
1642 /* The mask used to set the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field value. */
1643 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET_MSK 0x000001ff
1644 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field value. */
1645 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_CLR_MSK 0xfffffe00
1646 /* The reset value of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */
1647 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_RESET 0x0
1648 /* Extracts the ALT_CLKMGR_MAINPLL_MAINCLK_CNT field value from a register. */
1649 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1650 /* Produces a ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field value suitable for setting the register. */
1651 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1652 
1653 #ifndef __ASSEMBLY__
1654 /*
1655  * WARNING: The C register and register group struct declarations are provided for
1656  * convenience and illustrative purposes. They should, however, be used with
1657  * caution as the C language standard provides no guarantees about the alignment or
1658  * atomicity of device memory accesses. The recommended practice for writing
1659  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1660  * alt_write_word() functions.
1661  *
1662  * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINCLK.
1663  */
1664 struct ALT_CLKMGR_MAINPLL_MAINCLK_s
1665 {
1666  uint32_t cnt : 9; /* Counter */
1667  uint32_t : 23; /* *UNDEFINED* */
1668 };
1669 
1670 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINCLK. */
1671 typedef volatile struct ALT_CLKMGR_MAINPLL_MAINCLK_s ALT_CLKMGR_MAINPLL_MAINCLK_t;
1672 #endif /* __ASSEMBLY__ */
1673 
1674 /* The byte offset of the ALT_CLKMGR_MAINPLL_MAINCLK register from the beginning of the component. */
1675 #define ALT_CLKMGR_MAINPLL_MAINCLK_OFST 0xc
1676 
1677 /*
1678  * Register : Main PLL C2 Control Register for Clock dbg_base_clk - dbgatclk
1679  *
1680  * Contains settings that control clock dbg_base_clk generated from the C2 output
1681  * of the Main PLL.
1682  *
1683  * Only reset by a cold reset.
1684  *
1685  * Register Layout
1686  *
1687  * Bits | Access | Reset | Description
1688  * :-------|:-------|:------|:------------
1689  * [8:0] | RW | 0x0 | Counter
1690  * [31:9] | ??? | 0x0 | *UNDEFINED*
1691  *
1692  */
1693 /*
1694  * Field : Counter - cnt
1695  *
1696  * Divides the VCO/4 frequency by the value+1 in this field.
1697  *
1698  * Field Access Macros:
1699  *
1700  */
1701 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */
1702 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_LSB 0
1703 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */
1704 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_MSB 8
1705 /* The width in bits of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */
1706 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_WIDTH 9
1707 /* The mask used to set the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field value. */
1708 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET_MSK 0x000001ff
1709 /* The mask used to clear the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field value. */
1710 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_CLR_MSK 0xfffffe00
1711 /* The reset value of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */
1712 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_RESET 0x0
1713 /* Extracts the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT field value from a register. */
1714 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1715 /* Produces a ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field value suitable for setting the register. */
1716 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1717 
1718 #ifndef __ASSEMBLY__
1719 /*
1720  * WARNING: The C register and register group struct declarations are provided for
1721  * convenience and illustrative purposes. They should, however, be used with
1722  * caution as the C language standard provides no guarantees about the alignment or
1723  * atomicity of device memory accesses. The recommended practice for writing
1724  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1725  * alt_write_word() functions.
1726  *
1727  * The struct declaration for register ALT_CLKMGR_MAINPLL_DBGATCLK.
1728  */
1729 struct ALT_CLKMGR_MAINPLL_DBGATCLK_s
1730 {
1731  uint32_t cnt : 9; /* Counter */
1732  uint32_t : 23; /* *UNDEFINED* */
1733 };
1734 
1735 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_DBGATCLK. */
1736 typedef volatile struct ALT_CLKMGR_MAINPLL_DBGATCLK_s ALT_CLKMGR_MAINPLL_DBGATCLK_t;
1737 #endif /* __ASSEMBLY__ */
1738 
1739 /* The byte offset of the ALT_CLKMGR_MAINPLL_DBGATCLK register from the beginning of the component. */
1740 #define ALT_CLKMGR_MAINPLL_DBGATCLK_OFST 0x10
1741 
1742 /*
1743  * Register : Main PLL C3 Control Register for Clock main_qspi_clk - mainqspiclk
1744  *
1745  * Contains settings that control clock main_qspi_clk generated from the C3 output
1746  * of the Main PLL.
1747  *
1748  * Only reset by a cold reset.
1749  *
1750  * Register Layout
1751  *
1752  * Bits | Access | Reset | Description
1753  * :-------|:-------|:------|:------------
1754  * [8:0] | RW | 0x3 | Counter
1755  * [31:9] | ??? | 0x0 | *UNDEFINED*
1756  *
1757  */
1758 /*
1759  * Field : Counter - cnt
1760  *
1761  * Divides the VCO frequency by the value+1 in this field.
1762  *
1763  * Field Access Macros:
1764  *
1765  */
1766 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */
1767 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_LSB 0
1768 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */
1769 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_MSB 8
1770 /* The width in bits of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */
1771 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_WIDTH 9
1772 /* The mask used to set the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field value. */
1773 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK 0x000001ff
1774 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field value. */
1775 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_CLR_MSK 0xfffffe00
1776 /* The reset value of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */
1777 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_RESET 0x3
1778 /* Extracts the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT field value from a register. */
1779 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1780 /* Produces a ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field value suitable for setting the register. */
1781 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1782 
1783 #ifndef __ASSEMBLY__
1784 /*
1785  * WARNING: The C register and register group struct declarations are provided for
1786  * convenience and illustrative purposes. They should, however, be used with
1787  * caution as the C language standard provides no guarantees about the alignment or
1788  * atomicity of device memory accesses. The recommended practice for writing
1789  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1790  * alt_write_word() functions.
1791  *
1792  * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINQSPICLK.
1793  */
1794 struct ALT_CLKMGR_MAINPLL_MAINQSPICLK_s
1795 {
1796  uint32_t cnt : 9; /* Counter */
1797  uint32_t : 23; /* *UNDEFINED* */
1798 };
1799 
1800 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINQSPICLK. */
1801 typedef volatile struct ALT_CLKMGR_MAINPLL_MAINQSPICLK_s ALT_CLKMGR_MAINPLL_MAINQSPICLK_t;
1802 #endif /* __ASSEMBLY__ */
1803 
1804 /* The byte offset of the ALT_CLKMGR_MAINPLL_MAINQSPICLK register from the beginning of the component. */
1805 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_OFST 0x14
1806 
1807 /*
1808  * Register : Main PLL C4 Control Register for Clock main_nand_sdmmc_clk - mainnandsdmmcclk
1809  *
1810  * Contains settings that control clock main_nand_sdmmc_clk generated from the C4
1811  * output of the Main PLL.
1812  *
1813  * Only reset by a cold reset.
1814  *
1815  * Register Layout
1816  *
1817  * Bits | Access | Reset | Description
1818  * :-------|:-------|:------|:------------
1819  * [8:0] | RW | 0x3 | Counter
1820  * [31:9] | ??? | 0x0 | *UNDEFINED*
1821  *
1822  */
1823 /*
1824  * Field : Counter - cnt
1825  *
1826  * Divides the VCO frequency by the value+1 in this field.
1827  *
1828  * Field Access Macros:
1829  *
1830  */
1831 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */
1832 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_LSB 0
1833 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */
1834 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_MSB 8
1835 /* The width in bits of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */
1836 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_WIDTH 9
1837 /* The mask used to set the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field value. */
1838 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET_MSK 0x000001ff
1839 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field value. */
1840 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_CLR_MSK 0xfffffe00
1841 /* The reset value of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */
1842 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_RESET 0x3
1843 /* Extracts the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT field value from a register. */
1844 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1845 /* Produces a ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field value suitable for setting the register. */
1846 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1847 
1848 #ifndef __ASSEMBLY__
1849 /*
1850  * WARNING: The C register and register group struct declarations are provided for
1851  * convenience and illustrative purposes. They should, however, be used with
1852  * caution as the C language standard provides no guarantees about the alignment or
1853  * atomicity of device memory accesses. The recommended practice for writing
1854  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1855  * alt_write_word() functions.
1856  *
1857  * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK.
1858  */
1859 struct ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_s
1860 {
1861  uint32_t cnt : 9; /* Counter */
1862  uint32_t : 23; /* *UNDEFINED* */
1863 };
1864 
1865 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK. */
1866 typedef volatile struct ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_s ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_t;
1867 #endif /* __ASSEMBLY__ */
1868 
1869 /* The byte offset of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK register from the beginning of the component. */
1870 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_OFST 0x18
1871 
1872 /*
1873  * Register : Main PLL C5 Control Register for Clock cfg_s2f_user0_clk - cfgs2fuser0clk
1874  *
1875  * Contains settings that control clock cfg_s2f_user0_clk generated from the C5
1876  * output of the Main PLL.
1877  *
1878  * Qsys and user documenation refer to cfg_s2f_user0_clk as cfg_h2f_user0_clk.
1879  *
1880  * Only reset by a cold reset.
1881  *
1882  * Register Layout
1883  *
1884  * Bits | Access | Reset | Description
1885  * :-------|:-------|:------|:------------
1886  * [8:0] | RW | 0xf | Counter
1887  * [31:9] | ??? | 0x0 | *UNDEFINED*
1888  *
1889  */
1890 /*
1891  * Field : Counter - cnt
1892  *
1893  * Divides the VCO frequency by the value+1 in this field.
1894  *
1895  * Field Access Macros:
1896  *
1897  */
1898 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */
1899 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_LSB 0
1900 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */
1901 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_MSB 8
1902 /* The width in bits of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */
1903 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_WIDTH 9
1904 /* The mask used to set the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field value. */
1905 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET_MSK 0x000001ff
1906 /* The mask used to clear the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field value. */
1907 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_CLR_MSK 0xfffffe00
1908 /* The reset value of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */
1909 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_RESET 0xf
1910 /* Extracts the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT field value from a register. */
1911 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1912 /* Produces a ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field value suitable for setting the register. */
1913 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1914 
1915 #ifndef __ASSEMBLY__
1916 /*
1917  * WARNING: The C register and register group struct declarations are provided for
1918  * convenience and illustrative purposes. They should, however, be used with
1919  * caution as the C language standard provides no guarantees about the alignment or
1920  * atomicity of device memory accesses. The recommended practice for writing
1921  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1922  * alt_write_word() functions.
1923  *
1924  * The struct declaration for register ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK.
1925  */
1926 struct ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_s
1927 {
1928  uint32_t cnt : 9; /* Counter */
1929  uint32_t : 23; /* *UNDEFINED* */
1930 };
1931 
1932 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK. */
1933 typedef volatile struct ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_s ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_t;
1934 #endif /* __ASSEMBLY__ */
1935 
1936 /* The byte offset of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK register from the beginning of the component. */
1937 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_OFST 0x1c
1938 
1939 /*
1940  * Register : Enable Register - en
1941  *
1942  * Contains fields that control clock enables for clocks derived from the Main PLL.
1943  *
1944  * 1: The clock is enabled.
1945  *
1946  * 0: The clock is disabled.
1947  *
1948  * Fields are only reset by a cold reset.
1949  *
1950  * Register Layout
1951  *
1952  * Bits | Access | Reset | Description
1953  * :--------|:-------|:------|:---------------------
1954  * [0] | RW | 0x1 | l4_main_clk Enable
1955  * [1] | RW | 0x1 | l3_mp_clk Enable
1956  * [2] | RW | 0x1 | l4_mp_clk Enable
1957  * [3] | RW | 0x1 | l4_sp_clk Enable
1958  * [4] | RW | 0x1 | dbg_at_clk Enable
1959  * [5] | RW | 0x1 | dbg_clk Enable
1960  * [6] | RW | 0x1 | dbg_trace_clk Enable
1961  * [7] | RW | 0x1 | dbg_timer_clk Enable
1962  * [8] | RW | 0x1 | cfg_clk Enable
1963  * [9] | RW | 0x1 | s2f_user0_clk Enable
1964  * [31:10] | ??? | 0x0 | *UNDEFINED*
1965  *
1966  */
1967 /*
1968  * Field : l4_main_clk Enable - l4mainclk
1969  *
1970  * Enables clock l4_main_clk output
1971  *
1972  * Field Access Macros:
1973  *
1974  */
1975 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */
1976 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_LSB 0
1977 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */
1978 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_MSB 0
1979 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */
1980 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_WIDTH 1
1981 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value. */
1982 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK 0x00000001
1983 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value. */
1984 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_CLR_MSK 0xfffffffe
1985 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */
1986 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_RESET 0x1
1987 /* Extracts the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK field value from a register. */
1988 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_GET(value) (((value) & 0x00000001) >> 0)
1989 /* Produces a ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value suitable for setting the register. */
1990 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET(value) (((value) << 0) & 0x00000001)
1991 
1992 /*
1993  * Field : l3_mp_clk Enable - l3mpclk
1994  *
1995  * Enables clock l3_mp_clk output
1996  *
1997  * Field Access Macros:
1998  *
1999  */
2000 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */
2001 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_LSB 1
2002 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */
2003 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_MSB 1
2004 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */
2005 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_WIDTH 1
2006 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value. */
2007 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK 0x00000002
2008 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value. */
2009 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_CLR_MSK 0xfffffffd
2010 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */
2011 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_RESET 0x1
2012 /* Extracts the ALT_CLKMGR_MAINPLL_EN_L3MPCLK field value from a register. */
2013 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_GET(value) (((value) & 0x00000002) >> 1)
2014 /* Produces a ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value suitable for setting the register. */
2015 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET(value) (((value) << 1) & 0x00000002)
2016 
2017 /*
2018  * Field : l4_mp_clk Enable - l4mpclk
2019  *
2020  * Enables clock l4_mp_clk output
2021  *
2022  * Field Access Macros:
2023  *
2024  */
2025 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */
2026 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_LSB 2
2027 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */
2028 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_MSB 2
2029 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */
2030 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_WIDTH 1
2031 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value. */
2032 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK 0x00000004
2033 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value. */
2034 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK 0xfffffffb
2035 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */
2036 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_RESET 0x1
2037 /* Extracts the ALT_CLKMGR_MAINPLL_EN_L4MPCLK field value from a register. */
2038 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_GET(value) (((value) & 0x00000004) >> 2)
2039 /* Produces a ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value suitable for setting the register. */
2040 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET(value) (((value) << 2) & 0x00000004)
2041 
2042 /*
2043  * Field : l4_sp_clk Enable - l4spclk
2044  *
2045  * Enables clock l4_sp_clk output
2046  *
2047  * Field Access Macros:
2048  *
2049  */
2050 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */
2051 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_LSB 3
2052 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */
2053 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_MSB 3
2054 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */
2055 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_WIDTH 1
2056 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value. */
2057 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK 0x00000008
2058 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value. */
2059 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK 0xfffffff7
2060 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */
2061 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_RESET 0x1
2062 /* Extracts the ALT_CLKMGR_MAINPLL_EN_L4SPCLK field value from a register. */
2063 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_GET(value) (((value) & 0x00000008) >> 3)
2064 /* Produces a ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value suitable for setting the register. */
2065 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET(value) (((value) << 3) & 0x00000008)
2066 
2067 /*
2068  * Field : dbg_at_clk Enable - dbgatclk
2069  *
2070  * Enables clock dbg_at_clk output
2071  *
2072  * Field Access Macros:
2073  *
2074  */
2075 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */
2076 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_LSB 4
2077 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */
2078 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_MSB 4
2079 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */
2080 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_WIDTH 1
2081 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value. */
2082 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK 0x00000010
2083 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value. */
2084 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_CLR_MSK 0xffffffef
2085 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */
2086 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_RESET 0x1
2087 /* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGATCLK field value from a register. */
2088 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_GET(value) (((value) & 0x00000010) >> 4)
2089 /* Produces a ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value suitable for setting the register. */
2090 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET(value) (((value) << 4) & 0x00000010)
2091 
2092 /*
2093  * Field : dbg_clk Enable - dbgclk
2094  *
2095  * Enables clock dbg_clk output
2096  *
2097  * Field Access Macros:
2098  *
2099  */
2100 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */
2101 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_LSB 5
2102 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */
2103 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_MSB 5
2104 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */
2105 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_WIDTH 1
2106 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value. */
2107 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK 0x00000020
2108 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value. */
2109 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_CLR_MSK 0xffffffdf
2110 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */
2111 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_RESET 0x1
2112 /* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGCLK field value from a register. */
2113 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_GET(value) (((value) & 0x00000020) >> 5)
2114 /* Produces a ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value suitable for setting the register. */
2115 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET(value) (((value) << 5) & 0x00000020)
2116 
2117 /*
2118  * Field : dbg_trace_clk Enable - dbgtraceclk
2119  *
2120  * Enables clock dbg_trace_clk output
2121  *
2122  * Field Access Macros:
2123  *
2124  */
2125 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */
2126 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_LSB 6
2127 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */
2128 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_MSB 6
2129 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */
2130 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_WIDTH 1
2131 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value. */
2132 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK 0x00000040
2133 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value. */
2134 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_CLR_MSK 0xffffffbf
2135 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */
2136 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_RESET 0x1
2137 /* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK field value from a register. */
2138 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_GET(value) (((value) & 0x00000040) >> 6)
2139 /* Produces a ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value suitable for setting the register. */
2140 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET(value) (((value) << 6) & 0x00000040)
2141 
2142 /*
2143  * Field : dbg_timer_clk Enable - dbgtimerclk
2144  *
2145  * Enables clock dbg_timer_clk output
2146  *
2147  * Field Access Macros:
2148  *
2149  */
2150 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */
2151 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_LSB 7
2152 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */
2153 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_MSB 7
2154 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */
2155 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_WIDTH 1
2156 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value. */
2157 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK 0x00000080
2158 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value. */
2159 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_CLR_MSK 0xffffff7f
2160 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */
2161 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_RESET 0x1
2162 /* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK field value from a register. */
2163 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_GET(value) (((value) & 0x00000080) >> 7)
2164 /* Produces a ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value suitable for setting the register. */
2165 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET(value) (((value) << 7) & 0x00000080)
2166 
2167 /*
2168  * Field : cfg_clk Enable - cfgclk
2169  *
2170  * Enables clock cfg_clk output
2171  *
2172  * Field Access Macros:
2173  *
2174  */
2175 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */
2176 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_LSB 8
2177 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */
2178 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_MSB 8
2179 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */
2180 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_WIDTH 1
2181 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value. */
2182 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK 0x00000100
2183 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value. */
2184 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_CLR_MSK 0xfffffeff
2185 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */
2186 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_RESET 0x1
2187 /* Extracts the ALT_CLKMGR_MAINPLL_EN_CFGCLK field value from a register. */
2188 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_GET(value) (((value) & 0x00000100) >> 8)
2189 /* Produces a ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value suitable for setting the register. */
2190 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET(value) (((value) << 8) & 0x00000100)
2191 
2192 /*
2193  * Field : s2f_user0_clk Enable - s2fuser0clk
2194  *
2195  * Enables clock s2f_user0_clk output.
2196  *
2197  * Qsys and user documenation refer to s2f_user0_clk as h2f_user0_clk.
2198  *
2199  * Field Access Macros:
2200  *
2201  */
2202 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */
2203 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_LSB 9
2204 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */
2205 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_MSB 9
2206 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */
2207 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_WIDTH 1
2208 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value. */
2209 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK 0x00000200
2210 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value. */
2211 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_CLR_MSK 0xfffffdff
2212 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */
2213 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_RESET 0x1
2214 /* Extracts the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK field value from a register. */
2215 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_GET(value) (((value) & 0x00000200) >> 9)
2216 /* Produces a ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value suitable for setting the register. */
2217 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET(value) (((value) << 9) & 0x00000200)
2218 
2219 #ifndef __ASSEMBLY__
2220 /*
2221  * WARNING: The C register and register group struct declarations are provided for
2222  * convenience and illustrative purposes. They should, however, be used with
2223  * caution as the C language standard provides no guarantees about the alignment or
2224  * atomicity of device memory accesses. The recommended practice for writing
2225  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2226  * alt_write_word() functions.
2227  *
2228  * The struct declaration for register ALT_CLKMGR_MAINPLL_EN.
2229  */
2230 struct ALT_CLKMGR_MAINPLL_EN_s
2231 {
2232  uint32_t l4mainclk : 1; /* l4_main_clk Enable */
2233  uint32_t l3mpclk : 1; /* l3_mp_clk Enable */
2234  uint32_t l4mpclk : 1; /* l4_mp_clk Enable */
2235  uint32_t l4spclk : 1; /* l4_sp_clk Enable */
2236  uint32_t dbgatclk : 1; /* dbg_at_clk Enable */
2237  uint32_t dbgclk : 1; /* dbg_clk Enable */
2238  uint32_t dbgtraceclk : 1; /* dbg_trace_clk Enable */
2239  uint32_t dbgtimerclk : 1; /* dbg_timer_clk Enable */
2240  uint32_t cfgclk : 1; /* cfg_clk Enable */
2241  uint32_t s2fuser0clk : 1; /* s2f_user0_clk Enable */
2242  uint32_t : 22; /* *UNDEFINED* */
2243 };
2244 
2245 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_EN. */
2246 typedef volatile struct ALT_CLKMGR_MAINPLL_EN_s ALT_CLKMGR_MAINPLL_EN_t;
2247 #endif /* __ASSEMBLY__ */
2248 
2249 /* The byte offset of the ALT_CLKMGR_MAINPLL_EN register from the beginning of the component. */
2250 #define ALT_CLKMGR_MAINPLL_EN_OFST 0x20
2251 
2252 /*
2253  * Register : Main Divide Register - maindiv
2254  *
2255  * Contains fields that control clock dividers for main clocks derived from the
2256  * Main PLL
2257  *
2258  * Fields are only reset by a cold reset.
2259  *
2260  * Register Layout
2261  *
2262  * Bits | Access | Reset | Description
2263  * :--------|:-------|:------|:--------------------
2264  * [1:0] | RW | 0x0 | L3 MP Clock Divider
2265  * [3:2] | RW | 0x0 | L3 SP Clock Divider
2266  * [6:4] | RW | 0x0 | L4 MP Clock Divider
2267  * [9:7] | RW | 0x0 | L4 SP Clock Divider
2268  * [31:10] | ??? | 0x0 | *UNDEFINED*
2269  *
2270  */
2271 /*
2272  * Field : L3 MP Clock Divider - l3mpclk
2273  *
2274  * The l3_mp_clk is divided down from the l3_main_clk by the value specified in
2275  * this field.
2276  *
2277  * Field Enumeration Values:
2278  *
2279  * Enum | Value | Description
2280  * :------------------------------------------|:------|:------------
2281  * ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1 | 0x0 | Divide by 1
2282  * ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2 | 0x1 | Divide by 2
2283  *
2284  * Field Access Macros:
2285  *
2286  */
2287 /*
2288  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK
2289  *
2290  * Divide by 1
2291  */
2292 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1 0x0
2293 /*
2294  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK
2295  *
2296  * Divide by 2
2297  */
2298 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2 0x1
2299 
2300 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */
2301 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_LSB 0
2302 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */
2303 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_MSB 1
2304 /* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */
2305 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_WIDTH 2
2306 /* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value. */
2307 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET_MSK 0x00000003
2308 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value. */
2309 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_CLR_MSK 0xfffffffc
2310 /* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */
2311 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_RESET 0x0
2312 /* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK field value from a register. */
2313 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_GET(value) (((value) & 0x00000003) >> 0)
2314 /* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value suitable for setting the register. */
2315 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET(value) (((value) << 0) & 0x00000003)
2316 
2317 /*
2318  * Field : L3 SP Clock Divider - l3spclk
2319  *
2320  * The l3_sp_clk is divided down from the l3_mp_clk by the value specified in this
2321  * field.
2322  *
2323  * Field Enumeration Values:
2324  *
2325  * Enum | Value | Description
2326  * :------------------------------------------|:------|:------------
2327  * ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1 | 0x0 | Divide by 1
2328  * ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2 | 0x1 | Divide by 2
2329  *
2330  * Field Access Macros:
2331  *
2332  */
2333 /*
2334  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK
2335  *
2336  * Divide by 1
2337  */
2338 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1 0x0
2339 /*
2340  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK
2341  *
2342  * Divide by 2
2343  */
2344 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2 0x1
2345 
2346 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */
2347 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_LSB 2
2348 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */
2349 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_MSB 3
2350 /* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */
2351 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_WIDTH 2
2352 /* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value. */
2353 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET_MSK 0x0000000c
2354 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value. */
2355 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_CLR_MSK 0xfffffff3
2356 /* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */
2357 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_RESET 0x0
2358 /* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK field value from a register. */
2359 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_GET(value) (((value) & 0x0000000c) >> 2)
2360 /* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value suitable for setting the register. */
2361 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET(value) (((value) << 2) & 0x0000000c)
2362 
2363 /*
2364  * Field : L4 MP Clock Divider - l4mpclk
2365  *
2366  * The l4_mp_clk is divided down from the periph_base_clk by the value specified in
2367  * this field.
2368  *
2369  * Field Enumeration Values:
2370  *
2371  * Enum | Value | Description
2372  * :--------------------------------------------|:------|:-------------
2373  * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1 | 0x0 | Divide By 1
2374  * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2 | 0x1 | Divide By 2
2375  * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4 | 0x2 | Divide By 4
2376  * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8 | 0x3 | Divide By 8
2377  * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16 | 0x4 | Divide By 16
2378  * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_1 | 0x5 | Reserved
2379  * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_2 | 0x6 | Reserved
2380  * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_3 | 0x7 | Reserved
2381  *
2382  * Field Access Macros:
2383  *
2384  */
2385 /*
2386  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
2387  *
2388  * Divide By 1
2389  */
2390 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1 0x0
2391 /*
2392  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
2393  *
2394  * Divide By 2
2395  */
2396 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2 0x1
2397 /*
2398  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
2399  *
2400  * Divide By 4
2401  */
2402 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4 0x2
2403 /*
2404  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
2405  *
2406  * Divide By 8
2407  */
2408 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8 0x3
2409 /*
2410  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
2411  *
2412  * Divide By 16
2413  */
2414 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16 0x4
2415 /*
2416  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
2417  *
2418  * Reserved
2419  */
2420 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_1 0x5
2421 /*
2422  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
2423  *
2424  * Reserved
2425  */
2426 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_2 0x6
2427 /*
2428  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
2429  *
2430  * Reserved
2431  */
2432 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_3 0x7
2433 
2434 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */
2435 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_LSB 4
2436 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */
2437 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_MSB 6
2438 /* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */
2439 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_WIDTH 3
2440 /* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value. */
2441 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET_MSK 0x00000070
2442 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value. */
2443 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_CLR_MSK 0xffffff8f
2444 /* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */
2445 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_RESET 0x0
2446 /* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK field value from a register. */
2447 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_GET(value) (((value) & 0x00000070) >> 4)
2448 /* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value suitable for setting the register. */
2449 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET(value) (((value) << 4) & 0x00000070)
2450 
2451 /*
2452  * Field : L4 SP Clock Divider - l4spclk
2453  *
2454  * The l4_sp_clk is divided down from the periph_base_clk by the value specified in
2455  * this field.
2456  *
2457  * Field Enumeration Values:
2458  *
2459  * Enum | Value | Description
2460  * :--------------------------------------------|:------|:-------------
2461  * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1 | 0x0 | Divide By 1
2462  * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2 | 0x1 | Divide By 2
2463  * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4 | 0x2 | Divide By 4
2464  * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8 | 0x3 | Divide By 8
2465  * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16 | 0x4 | Divide By 16
2466  * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_1 | 0x5 | Reserved
2467  * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_2 | 0x6 | Reserved
2468  * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_3 | 0x7 | Reserved
2469  *
2470  * Field Access Macros:
2471  *
2472  */
2473 /*
2474  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
2475  *
2476  * Divide By 1
2477  */
2478 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1 0x0
2479 /*
2480  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
2481  *
2482  * Divide By 2
2483  */
2484 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2 0x1
2485 /*
2486  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
2487  *
2488  * Divide By 4
2489  */
2490 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4 0x2
2491 /*
2492  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
2493  *
2494  * Divide By 8
2495  */
2496 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8 0x3
2497 /*
2498  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
2499  *
2500  * Divide By 16
2501  */
2502 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16 0x4
2503 /*
2504  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
2505  *
2506  * Reserved
2507  */
2508 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_1 0x5
2509 /*
2510  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
2511  *
2512  * Reserved
2513  */
2514 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_2 0x6
2515 /*
2516  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
2517  *
2518  * Reserved
2519  */
2520 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_3 0x7
2521 
2522 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */
2523 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_LSB 7
2524 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */
2525 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_MSB 9
2526 /* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */
2527 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_WIDTH 3
2528 /* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value. */
2529 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET_MSK 0x00000380
2530 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value. */
2531 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_CLR_MSK 0xfffffc7f
2532 /* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */
2533 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_RESET 0x0
2534 /* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK field value from a register. */
2535 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_GET(value) (((value) & 0x00000380) >> 7)
2536 /* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value suitable for setting the register. */
2537 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET(value) (((value) << 7) & 0x00000380)
2538 
2539 #ifndef __ASSEMBLY__
2540 /*
2541  * WARNING: The C register and register group struct declarations are provided for
2542  * convenience and illustrative purposes. They should, however, be used with
2543  * caution as the C language standard provides no guarantees about the alignment or
2544  * atomicity of device memory accesses. The recommended practice for writing
2545  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2546  * alt_write_word() functions.
2547  *
2548  * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINDIV.
2549  */
2550 struct ALT_CLKMGR_MAINPLL_MAINDIV_s
2551 {
2552  uint32_t l3mpclk : 2; /* L3 MP Clock Divider */
2553  uint32_t l3spclk : 2; /* L3 SP Clock Divider */
2554  uint32_t l4mpclk : 3; /* L4 MP Clock Divider */
2555  uint32_t l4spclk : 3; /* L4 SP Clock Divider */
2556  uint32_t : 22; /* *UNDEFINED* */
2557 };
2558 
2559 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINDIV. */
2560 typedef volatile struct ALT_CLKMGR_MAINPLL_MAINDIV_s ALT_CLKMGR_MAINPLL_MAINDIV_t;
2561 #endif /* __ASSEMBLY__ */
2562 
2563 /* The byte offset of the ALT_CLKMGR_MAINPLL_MAINDIV register from the beginning of the component. */
2564 #define ALT_CLKMGR_MAINPLL_MAINDIV_OFST 0x24
2565 
2566 /*
2567  * Register : Debug Divide Register - dbgdiv
2568  *
2569  * Contains fields that control clock dividers for debug clocks derived from the
2570  * Main PLL
2571  *
2572  * Fields are only reset by a cold reset.
2573  *
2574  * Register Layout
2575  *
2576  * Bits | Access | Reset | Description
2577  * :-------|:-------|:------|:-----------------------
2578  * [1:0] | RW | 0x0 | Debug AT Clock Divider
2579  * [3:2] | RW | 0x1 | Debug Clock Divider
2580  * [31:4] | ??? | 0x0 | *UNDEFINED*
2581  *
2582  */
2583 /*
2584  * Field : Debug AT Clock Divider - dbgatclk
2585  *
2586  * The dbg_at_clk is divided down from the C2 output of the Main PLL by the value
2587  * specified in this field.
2588  *
2589  * Field Enumeration Values:
2590  *
2591  * Enum | Value | Description
2592  * :------------------------------------------|:------|:------------
2593  * ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1 | 0x0 | Divide by 1
2594  * ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2 | 0x1 | Divide by 2
2595  * ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4 | 0x2 | Divide by 4
2596  *
2597  * Field Access Macros:
2598  *
2599  */
2600 /*
2601  * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK
2602  *
2603  * Divide by 1
2604  */
2605 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1 0x0
2606 /*
2607  * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK
2608  *
2609  * Divide by 2
2610  */
2611 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2 0x1
2612 /*
2613  * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK
2614  *
2615  * Divide by 4
2616  */
2617 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4 0x2
2618 
2619 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */
2620 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_LSB 0
2621 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */
2622 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_MSB 1
2623 /* The width in bits of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */
2624 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_WIDTH 2
2625 /* The mask used to set the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value. */
2626 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET_MSK 0x00000003
2627 /* The mask used to clear the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value. */
2628 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_CLR_MSK 0xfffffffc
2629 /* The reset value of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */
2630 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_RESET 0x0
2631 /* Extracts the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK field value from a register. */
2632 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_GET(value) (((value) & 0x00000003) >> 0)
2633 /* Produces a ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value suitable for setting the register. */
2634 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET(value) (((value) << 0) & 0x00000003)
2635 
2636 /*
2637  * Field : Debug Clock Divider - dbgclk
2638  *
2639  * The dbg_clk is divided down from the dbg_at_clk by the value specified in this
2640  * field.
2641  *
2642  * Field Enumeration Values:
2643  *
2644  * Enum | Value | Description
2645  * :----------------------------------------|:------|:------------
2646  * ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2 | 0x1 | Divide by 2
2647  * ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4 | 0x2 | Divide by 4
2648  *
2649  * Field Access Macros:
2650  *
2651  */
2652 /*
2653  * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK
2654  *
2655  * Divide by 2
2656  */
2657 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2 0x1
2658 /*
2659  * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK
2660  *
2661  * Divide by 4
2662  */
2663 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4 0x2
2664 
2665 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */
2666 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_LSB 2
2667 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */
2668 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_MSB 3
2669 /* The width in bits of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */
2670 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_WIDTH 2
2671 /* The mask used to set the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value. */
2672 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET_MSK 0x0000000c
2673 /* The mask used to clear the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value. */
2674 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_CLR_MSK 0xfffffff3
2675 /* The reset value of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */
2676 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_RESET 0x1
2677 /* Extracts the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK field value from a register. */
2678 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_GET(value) (((value) & 0x0000000c) >> 2)
2679 /* Produces a ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value suitable for setting the register. */
2680 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET(value) (((value) << 2) & 0x0000000c)
2681 
2682 #ifndef __ASSEMBLY__
2683 /*
2684  * WARNING: The C register and register group struct declarations are provided for
2685  * convenience and illustrative purposes. They should, however, be used with
2686  * caution as the C language standard provides no guarantees about the alignment or
2687  * atomicity of device memory accesses. The recommended practice for writing
2688  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2689  * alt_write_word() functions.
2690  *
2691  * The struct declaration for register ALT_CLKMGR_MAINPLL_DBGDIV.
2692  */
2693 struct ALT_CLKMGR_MAINPLL_DBGDIV_s
2694 {
2695  uint32_t dbgatclk : 2; /* Debug AT Clock Divider */
2696  uint32_t dbgclk : 2; /* Debug Clock Divider */
2697  uint32_t : 28; /* *UNDEFINED* */
2698 };
2699 
2700 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_DBGDIV. */
2701 typedef volatile struct ALT_CLKMGR_MAINPLL_DBGDIV_s ALT_CLKMGR_MAINPLL_DBGDIV_t;
2702 #endif /* __ASSEMBLY__ */
2703 
2704 /* The byte offset of the ALT_CLKMGR_MAINPLL_DBGDIV register from the beginning of the component. */
2705 #define ALT_CLKMGR_MAINPLL_DBGDIV_OFST 0x28
2706 
2707 /*
2708  * Register : Debug Trace Divide Register - tracediv
2709  *
2710  * Contains a field that controls the clock divider for the debug trace clock
2711  * derived from the Main PLL
2712  *
2713  * Only reset by a cold reset.
2714  *
2715  * Register Layout
2716  *
2717  * Bits | Access | Reset | Description
2718  * :-------|:-------|:------|:--------------------------
2719  * [2:0] | RW | 0x0 | Debug Trace Clock Divider
2720  * [31:3] | ??? | 0x0 | *UNDEFINED*
2721  *
2722  */
2723 /*
2724  * Field : Debug Trace Clock Divider - traceclk
2725  *
2726  * The dbg_trace_clk is divided down from the C2 output of the Main PLL by the
2727  * value specified in this field.
2728  *
2729  * Field Enumeration Values:
2730  *
2731  * Enum | Value | Description
2732  * :----------------------------------------------|:------|:-------------
2733  * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1 | 0x0 | Divide By 1
2734  * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2 | 0x1 | Divide By 2
2735  * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4 | 0x2 | Divide By 4
2736  * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8 | 0x3 | Divide By 8
2737  * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16 | 0x4 | Divide By 16
2738  * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_1 | 0x5 | Reserved
2739  * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_2 | 0x6 | Reserved
2740  * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_3 | 0x7 | Reserved
2741  *
2742  * Field Access Macros:
2743  *
2744  */
2745 /*
2746  * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
2747  *
2748  * Divide By 1
2749  */
2750 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1 0x0
2751 /*
2752  * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
2753  *
2754  * Divide By 2
2755  */
2756 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2 0x1
2757 /*
2758  * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
2759  *
2760  * Divide By 4
2761  */
2762 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4 0x2
2763 /*
2764  * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
2765  *
2766  * Divide By 8
2767  */
2768 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8 0x3
2769 /*
2770  * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
2771  *
2772  * Divide By 16
2773  */
2774 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16 0x4
2775 /*
2776  * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
2777  *
2778  * Reserved
2779  */
2780 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_1 0x5
2781 /*
2782  * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
2783  *
2784  * Reserved
2785  */
2786 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_2 0x6
2787 /*
2788  * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK
2789  *
2790  * Reserved
2791  */
2792 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_3 0x7
2793 
2794 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */
2795 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_LSB 0
2796 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */
2797 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_MSB 2
2798 /* The width in bits of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */
2799 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_WIDTH 3
2800 /* The mask used to set the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value. */
2801 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET_MSK 0x00000007
2802 /* The mask used to clear the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value. */
2803 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_CLR_MSK 0xfffffff8
2804 /* The reset value of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */
2805 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_RESET 0x0
2806 /* Extracts the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK field value from a register. */
2807 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_GET(value) (((value) & 0x00000007) >> 0)
2808 /* Produces a ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value suitable for setting the register. */
2809 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET(value) (((value) << 0) & 0x00000007)
2810 
2811 #ifndef __ASSEMBLY__
2812 /*
2813  * WARNING: The C register and register group struct declarations are provided for
2814  * convenience and illustrative purposes. They should, however, be used with
2815  * caution as the C language standard provides no guarantees about the alignment or
2816  * atomicity of device memory accesses. The recommended practice for writing
2817  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2818  * alt_write_word() functions.
2819  *
2820  * The struct declaration for register ALT_CLKMGR_MAINPLL_TRACEDIV.
2821  */
2822 struct ALT_CLKMGR_MAINPLL_TRACEDIV_s
2823 {
2824  uint32_t traceclk : 3; /* Debug Trace Clock Divider */
2825  uint32_t : 29; /* *UNDEFINED* */
2826 };
2827 
2828 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_TRACEDIV. */
2829 typedef volatile struct ALT_CLKMGR_MAINPLL_TRACEDIV_s ALT_CLKMGR_MAINPLL_TRACEDIV_t;
2830 #endif /* __ASSEMBLY__ */
2831 
2832 /* The byte offset of the ALT_CLKMGR_MAINPLL_TRACEDIV register from the beginning of the component. */
2833 #define ALT_CLKMGR_MAINPLL_TRACEDIV_OFST 0x2c
2834 
2835 /*
2836  * Register : L4 MP SP APB Clock Source - l4src
2837  *
2838  * Contains fields that select the clock source for L4 MP and SP APB interconnect
2839  *
2840  * Fields are only reset by a cold reset.
2841  *
2842  * Register Layout
2843  *
2844  * Bits | Access | Reset | Description
2845  * :-------|:-------|:------|:-----------------
2846  * [0] | RW | 0x0 | l4_mp_clk Source
2847  * [1] | RW | 0x0 | l4_sp_clk Source
2848  * [31:2] | ??? | 0x0 | *UNDEFINED*
2849  *
2850  */
2851 /*
2852  * Field : l4_mp_clk Source - l4mp
2853  *
2854  * Selects the source for l4_mp_clk
2855  *
2856  * Field Enumeration Values:
2857  *
2858  * Enum | Value | Description
2859  * :------------------------------------------|:------|:----------------
2860  * ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL | 0x0 | main_clk
2861  * ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL | 0x1 | periph_base_clk
2862  *
2863  * Field Access Macros:
2864  *
2865  */
2866 /*
2867  * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4MP
2868  *
2869  * main_clk
2870  */
2871 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL 0x0
2872 /*
2873  * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4MP
2874  *
2875  * periph_base_clk
2876  */
2877 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL 0x1
2878 
2879 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */
2880 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_LSB 0
2881 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */
2882 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_MSB 0
2883 /* The width in bits of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */
2884 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_WIDTH 1
2885 /* The mask used to set the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value. */
2886 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK 0x00000001
2887 /* The mask used to clear the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value. */
2888 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_CLR_MSK 0xfffffffe
2889 /* The reset value of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */
2890 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_RESET 0x0
2891 /* Extracts the ALT_CLKMGR_MAINPLL_L4SRC_L4MP field value from a register. */
2892 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(value) (((value) & 0x00000001) >> 0)
2893 /* Produces a ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value suitable for setting the register. */
2894 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET(value) (((value) << 0) & 0x00000001)
2895 
2896 /*
2897  * Field : l4_sp_clk Source - l4sp
2898  *
2899  * Selects the source for l4_sp_clk
2900  *
2901  * Field Enumeration Values:
2902  *
2903  * Enum | Value | Description
2904  * :------------------------------------------|:------|:----------------
2905  * ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL | 0x0 | main_clk
2906  * ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL | 0x1 | periph_base_clk
2907  *
2908  * Field Access Macros:
2909  *
2910  */
2911 /*
2912  * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4SP
2913  *
2914  * main_clk
2915  */
2916 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL 0x0
2917 /*
2918  * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4SP
2919  *
2920  * periph_base_clk
2921  */
2922 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL 0x1
2923 
2924 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */
2925 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_LSB 1
2926 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */
2927 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_MSB 1
2928 /* The width in bits of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */
2929 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_WIDTH 1
2930 /* The mask used to set the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value. */
2931 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK 0x00000002
2932 /* The mask used to clear the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value. */
2933 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_CLR_MSK 0xfffffffd
2934 /* The reset value of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */
2935 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_RESET 0x0
2936 /* Extracts the ALT_CLKMGR_MAINPLL_L4SRC_L4SP field value from a register. */
2937 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(value) (((value) & 0x00000002) >> 1)
2938 /* Produces a ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value suitable for setting the register. */
2939 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET(value) (((value) << 1) & 0x00000002)
2940 
2941 #ifndef __ASSEMBLY__
2942 /*
2943  * WARNING: The C register and register group struct declarations are provided for
2944  * convenience and illustrative purposes. They should, however, be used with
2945  * caution as the C language standard provides no guarantees about the alignment or
2946  * atomicity of device memory accesses. The recommended practice for writing
2947  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2948  * alt_write_word() functions.
2949  *
2950  * The struct declaration for register ALT_CLKMGR_MAINPLL_L4SRC.
2951  */
2952 struct ALT_CLKMGR_MAINPLL_L4SRC_s
2953 {
2954  uint32_t l4mp : 1; /* l4_mp_clk Source */
2955  uint32_t l4sp : 1; /* l4_sp_clk Source */
2956  uint32_t : 30; /* *UNDEFINED* */
2957 };
2958 
2959 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_L4SRC. */
2960 typedef volatile struct ALT_CLKMGR_MAINPLL_L4SRC_s ALT_CLKMGR_MAINPLL_L4SRC_t;
2961 #endif /* __ASSEMBLY__ */
2962 
2963 /* The byte offset of the ALT_CLKMGR_MAINPLL_L4SRC register from the beginning of the component. */
2964 #define ALT_CLKMGR_MAINPLL_L4SRC_OFST 0x30
2965 
2966 /*
2967  * Register : Main PLL Output Counter Reset Ack Status Register - stat
2968  *
2969  * Contains Output Clock Counter Reset acknowledge status.
2970  *
2971  * Register Layout
2972  *
2973  * Bits | Access | Reset | Description
2974  * :-------|:-------|:------|:---------------------------------
2975  * [5:0] | R | 0x0 | Output Counter Reset Acknowledge
2976  * [31:6] | ??? | 0x0 | *UNDEFINED*
2977  *
2978  */
2979 /*
2980  * Field : Output Counter Reset Acknowledge - outresetack
2981  *
2982  * These read only bits per PLL output indicate that the PLL has received the
2983  * Output Reset Counter request and has gracefully stopped the respective PLL
2984  * output clock.
2985  *
2986  * For software to change the PLL output counter without producing glitches on the
2987  * respective clock, SW must set the VCO register respective Output Counter Reset
2988  * bit. Software then polls the respective Output Counter Reset Acknowledge bit in
2989  * the Output Counter Reset Ack Status Register. Software then writes the
2990  * appropriate counter register, and then clears the respective VCO register Output
2991  * Counter Reset bit.
2992  *
2993  * The reset value of this bit is applied on a cold reset; warm reset has no affect
2994  * on this bit.
2995  *
2996  * Field Enumeration Values:
2997  *
2998  * Enum | Value | Description
2999  * :--------------------------------------------|:------|:-------------------------------------
3000  * ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_IDLE | 0x0 | Idle
3001  * ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_ACK_RXD | 0x1 | Output Counter Acknowledge received.
3002  *
3003  * Field Access Macros:
3004  *
3005  */
3006 /*
3007  * Enumerated value for register field ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK
3008  *
3009  * Idle
3010  */
3011 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_IDLE 0x0
3012 /*
3013  * Enumerated value for register field ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK
3014  *
3015  * Output Counter Acknowledge received.
3016  */
3017 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1
3018 
3019 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */
3020 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_LSB 0
3021 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */
3022 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_MSB 5
3023 /* The width in bits of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */
3024 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_WIDTH 6
3025 /* The mask used to set the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field value. */
3026 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f
3027 /* The mask used to clear the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field value. */
3028 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0
3029 /* The reset value of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */
3030 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_RESET 0x0
3031 /* Extracts the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK field value from a register. */
3032 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0)
3033 /* Produces a ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field value suitable for setting the register. */
3034 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f)
3035 
3036 #ifndef __ASSEMBLY__
3037 /*
3038  * WARNING: The C register and register group struct declarations are provided for
3039  * convenience and illustrative purposes. They should, however, be used with
3040  * caution as the C language standard provides no guarantees about the alignment or
3041  * atomicity of device memory accesses. The recommended practice for writing
3042  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3043  * alt_write_word() functions.
3044  *
3045  * The struct declaration for register ALT_CLKMGR_MAINPLL_STAT.
3046  */
3047 struct ALT_CLKMGR_MAINPLL_STAT_s
3048 {
3049  const uint32_t outresetack : 6; /* Output Counter Reset Acknowledge */
3050  uint32_t : 26; /* *UNDEFINED* */
3051 };
3052 
3053 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_STAT. */
3054 typedef volatile struct ALT_CLKMGR_MAINPLL_STAT_s ALT_CLKMGR_MAINPLL_STAT_t;
3055 #endif /* __ASSEMBLY__ */
3056 
3057 /* The byte offset of the ALT_CLKMGR_MAINPLL_STAT register from the beginning of the component. */
3058 #define ALT_CLKMGR_MAINPLL_STAT_OFST 0x34
3059 
3060 #ifndef __ASSEMBLY__
3061 /*
3062  * WARNING: The C register and register group struct declarations are provided for
3063  * convenience and illustrative purposes. They should, however, be used with
3064  * caution as the C language standard provides no guarantees about the alignment or
3065  * atomicity of device memory accesses. The recommended practice for writing
3066  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3067  * alt_write_word() functions.
3068  *
3069  * The struct declaration for register group ALT_CLKMGR_MAINPLL.
3070  */
3071 struct ALT_CLKMGR_MAINPLL_s
3072 {
3073  ALT_CLKMGR_MAINPLL_VCO_t vco; /* ALT_CLKMGR_MAINPLL_VCO */
3074  ALT_CLKMGR_MAINPLL_MISC_t misc; /* ALT_CLKMGR_MAINPLL_MISC */
3075  ALT_CLKMGR_MAINPLL_MPUCLK_t mpuclk; /* ALT_CLKMGR_MAINPLL_MPUCLK */
3076  ALT_CLKMGR_MAINPLL_MAINCLK_t mainclk; /* ALT_CLKMGR_MAINPLL_MAINCLK */
3077  ALT_CLKMGR_MAINPLL_DBGATCLK_t dbgatclk; /* ALT_CLKMGR_MAINPLL_DBGATCLK */
3078  ALT_CLKMGR_MAINPLL_MAINQSPICLK_t mainqspiclk; /* ALT_CLKMGR_MAINPLL_MAINQSPICLK */
3079  ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_t mainnandsdmmcclk; /* ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK */
3080  ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_t cfgs2fuser0clk; /* ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK */
3081  ALT_CLKMGR_MAINPLL_EN_t en; /* ALT_CLKMGR_MAINPLL_EN */
3082  ALT_CLKMGR_MAINPLL_MAINDIV_t maindiv; /* ALT_CLKMGR_MAINPLL_MAINDIV */
3083  ALT_CLKMGR_MAINPLL_DBGDIV_t dbgdiv; /* ALT_CLKMGR_MAINPLL_DBGDIV */
3084  ALT_CLKMGR_MAINPLL_TRACEDIV_t tracediv; /* ALT_CLKMGR_MAINPLL_TRACEDIV */
3085  ALT_CLKMGR_MAINPLL_L4SRC_t l4src; /* ALT_CLKMGR_MAINPLL_L4SRC */
3086  ALT_CLKMGR_MAINPLL_STAT_t stat; /* ALT_CLKMGR_MAINPLL_STAT */
3087  volatile uint32_t _pad_0x38_0x40[2]; /* *UNDEFINED* */
3088 };
3089 
3090 /* The typedef declaration for register group ALT_CLKMGR_MAINPLL. */
3091 typedef volatile struct ALT_CLKMGR_MAINPLL_s ALT_CLKMGR_MAINPLL_t;
3092 /* The struct declaration for the raw register contents of register group ALT_CLKMGR_MAINPLL. */
3093 struct ALT_CLKMGR_MAINPLL_raw_s
3094 {
3095  volatile uint32_t vco; /* ALT_CLKMGR_MAINPLL_VCO */
3096  volatile uint32_t misc; /* ALT_CLKMGR_MAINPLL_MISC */
3097  volatile uint32_t mpuclk; /* ALT_CLKMGR_MAINPLL_MPUCLK */
3098  volatile uint32_t mainclk; /* ALT_CLKMGR_MAINPLL_MAINCLK */
3099  volatile uint32_t dbgatclk; /* ALT_CLKMGR_MAINPLL_DBGATCLK */
3100  volatile uint32_t mainqspiclk; /* ALT_CLKMGR_MAINPLL_MAINQSPICLK */
3101  volatile uint32_t mainnandsdmmcclk; /* ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK */
3102  volatile uint32_t cfgs2fuser0clk; /* ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK */
3103  volatile uint32_t en; /* ALT_CLKMGR_MAINPLL_EN */
3104  volatile uint32_t maindiv; /* ALT_CLKMGR_MAINPLL_MAINDIV */
3105  volatile uint32_t dbgdiv; /* ALT_CLKMGR_MAINPLL_DBGDIV */
3106  volatile uint32_t tracediv; /* ALT_CLKMGR_MAINPLL_TRACEDIV */
3107  volatile uint32_t l4src; /* ALT_CLKMGR_MAINPLL_L4SRC */
3108  volatile uint32_t stat; /* ALT_CLKMGR_MAINPLL_STAT */
3109  uint32_t _pad_0x38_0x40[2]; /* *UNDEFINED* */
3110 };
3111 
3112 /* The typedef declaration for the raw register contents of register group ALT_CLKMGR_MAINPLL. */
3113 typedef volatile struct ALT_CLKMGR_MAINPLL_raw_s ALT_CLKMGR_MAINPLL_raw_t;
3114 #endif /* __ASSEMBLY__ */
3115 
3116 
3117 /*
3118  * Register Group : Peripheral PLL Group - ALT_CLKMGR_PERPLL
3119  * Peripheral PLL Group
3120  *
3121  * Contains registers with settings for the Peripheral PLL.
3122  *
3123  */
3124 /*
3125  * Register : Peripheral PLL VCO Control Register - vco
3126  *
3127  * Contains settings that control the Peripheral PLL VCO. The VCO output frequency
3128  * is the input frequency multiplied by the numerator (M+1) and divided by the
3129  * denominator (N+1).
3130  *
3131  * Fields are only reset by a cold reset.
3132  *
3133  * Register Layout
3134  *
3135  * Bits | Access | Reset | Description
3136  * :--------|:-------|:------|:--------------------------------
3137  * [0] | RW | 0x1 | BG PWRDN
3138  * [1] | RW | 0x0 | Enable
3139  * [2] | RW | 0x1 | Power down
3140  * [15:3] | RW | 0x1 | Numerator (M)
3141  * [21:16] | RW | 0x1 | Denominator (N)
3142  * [23:22] | RW | 0x0 | Clock Source
3143  * [24] | RW | 0x0 | All Output Counter Reset
3144  * [30:25] | RW | 0x0 | Output Counter Reset
3145  * [31] | RW | 0x1 | External Regulator Input Select
3146  *
3147  */
3148 /*
3149  * Field : BG PWRDN - bgpwrdn
3150  *
3151  * If '1', powers down bandgap. If '0', bandgap is not power down.
3152  *
3153  * Field Access Macros:
3154  *
3155  */
3156 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */
3157 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_LSB 0
3158 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */
3159 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_MSB 0
3160 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */
3161 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_WIDTH 1
3162 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field value. */
3163 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_SET_MSK 0x00000001
3164 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field value. */
3165 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe
3166 /* The reset value of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */
3167 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_RESET 0x1
3168 /* Extracts the ALT_CLKMGR_PERPLL_VCO_BGPWRDN field value from a register. */
3169 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0)
3170 /* Produces a ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field value suitable for setting the register. */
3171 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001)
3172 
3173 /*
3174  * Field : Enable - en
3175  *
3176  * If '1', VCO is enabled. If '0', VCO is in reset.
3177  *
3178  * Field Access Macros:
3179  *
3180  */
3181 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_EN register field. */
3182 #define ALT_CLKMGR_PERPLL_VCO_EN_LSB 1
3183 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_EN register field. */
3184 #define ALT_CLKMGR_PERPLL_VCO_EN_MSB 1
3185 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO_EN register field. */
3186 #define ALT_CLKMGR_PERPLL_VCO_EN_WIDTH 1
3187 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO_EN register field value. */
3188 #define ALT_CLKMGR_PERPLL_VCO_EN_SET_MSK 0x00000002
3189 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_EN register field value. */
3190 #define ALT_CLKMGR_PERPLL_VCO_EN_CLR_MSK 0xfffffffd
3191 /* The reset value of the ALT_CLKMGR_PERPLL_VCO_EN register field. */
3192 #define ALT_CLKMGR_PERPLL_VCO_EN_RESET 0x0
3193 /* Extracts the ALT_CLKMGR_PERPLL_VCO_EN field value from a register. */
3194 #define ALT_CLKMGR_PERPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1)
3195 /* Produces a ALT_CLKMGR_PERPLL_VCO_EN register field value suitable for setting the register. */
3196 #define ALT_CLKMGR_PERPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002)
3197 
3198 /*
3199  * Field : Power down - pwrdn
3200  *
3201  * If '1', power down analog circuitry. If '0', analog circuitry not powered down.
3202  *
3203  * Field Access Macros:
3204  *
3205  */
3206 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */
3207 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_LSB 2
3208 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */
3209 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_MSB 2
3210 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */
3211 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_WIDTH 1
3212 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO_PWRDN register field value. */
3213 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_SET_MSK 0x00000004
3214 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_PWRDN register field value. */
3215 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_CLR_MSK 0xfffffffb
3216 /* The reset value of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */
3217 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_RESET 0x1
3218 /* Extracts the ALT_CLKMGR_PERPLL_VCO_PWRDN field value from a register. */
3219 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2)
3220 /* Produces a ALT_CLKMGR_PERPLL_VCO_PWRDN register field value suitable for setting the register. */
3221 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004)
3222 
3223 /*
3224  * Field : Numerator (M) - numer
3225  *
3226  * Numerator in VCO output frequency equation. For incremental frequency change, if
3227  * the new value lead to less than 20% of the frequency change, this value can be
3228  * changed without resetting the PLL. The Numerator and Denominator can not be
3229  * changed at the same time for incremental frequency changed.
3230  *
3231  * Field Access Macros:
3232  *
3233  */
3234 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */
3235 #define ALT_CLKMGR_PERPLL_VCO_NUMER_LSB 3
3236 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */
3237 #define ALT_CLKMGR_PERPLL_VCO_NUMER_MSB 15
3238 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */
3239 #define ALT_CLKMGR_PERPLL_VCO_NUMER_WIDTH 13
3240 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO_NUMER register field value. */
3241 #define ALT_CLKMGR_PERPLL_VCO_NUMER_SET_MSK 0x0000fff8
3242 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_NUMER register field value. */
3243 #define ALT_CLKMGR_PERPLL_VCO_NUMER_CLR_MSK 0xffff0007
3244 /* The reset value of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */
3245 #define ALT_CLKMGR_PERPLL_VCO_NUMER_RESET 0x1
3246 /* Extracts the ALT_CLKMGR_PERPLL_VCO_NUMER field value from a register. */
3247 #define ALT_CLKMGR_PERPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3)
3248 /* Produces a ALT_CLKMGR_PERPLL_VCO_NUMER register field value suitable for setting the register. */
3249 #define ALT_CLKMGR_PERPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8)
3250 
3251 /*
3252  * Field : Denominator (N) - denom
3253  *
3254  * Denominator in VCO output frequency equation. For incremental frequency change,
3255  * if the new value lead to less than 20% of the frequency change, this value can
3256  * be changed without resetting the PLL. The Numerator and Denominator can not be
3257  * changed at the same time for incremental frequency changed.
3258  *
3259  * Field Access Macros:
3260  *
3261  */
3262 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */
3263 #define ALT_CLKMGR_PERPLL_VCO_DENOM_LSB 16
3264 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */
3265 #define ALT_CLKMGR_PERPLL_VCO_DENOM_MSB 21
3266 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */
3267 #define ALT_CLKMGR_PERPLL_VCO_DENOM_WIDTH 6
3268 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO_DENOM register field value. */
3269 #define ALT_CLKMGR_PERPLL_VCO_DENOM_SET_MSK 0x003f0000
3270 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_DENOM register field value. */
3271 #define ALT_CLKMGR_PERPLL_VCO_DENOM_CLR_MSK 0xffc0ffff
3272 /* The reset value of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */
3273 #define ALT_CLKMGR_PERPLL_VCO_DENOM_RESET 0x1
3274 /* Extracts the ALT_CLKMGR_PERPLL_VCO_DENOM field value from a register. */
3275 #define ALT_CLKMGR_PERPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16)
3276 /* Produces a ALT_CLKMGR_PERPLL_VCO_DENOM register field value suitable for setting the register. */
3277 #define ALT_CLKMGR_PERPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000)
3278 
3279 /*
3280  * Field : Clock Source - psrc
3281  *
3282  * Controls the VCO input clock source.
3283  *
3284  * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk.
3285  *
3286  * Field Enumeration Values:
3287  *
3288  * Enum | Value | Description
3289  * :--------------------------------------------|:------|:-------------------
3290  * ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1 | 0x0 | eosc1_clk
3291  * ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2 | 0x1 | eosc2_clk
3292  * ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF | 0x2 | f2s_periph_ref_clk
3293  *
3294  * Field Access Macros:
3295  *
3296  */
3297 /*
3298  * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO_PSRC
3299  *
3300  * eosc1_clk
3301  */
3302 #define ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1 0x0
3303 /*
3304  * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO_PSRC
3305  *
3306  * eosc2_clk
3307  */
3308 #define ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2 0x1
3309 /*
3310  * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO_PSRC
3311  *
3312  * f2s_periph_ref_clk
3313  */
3314 #define ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF 0x2
3315 
3316 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */
3317 #define ALT_CLKMGR_PERPLL_VCO_PSRC_LSB 22
3318 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */
3319 #define ALT_CLKMGR_PERPLL_VCO_PSRC_MSB 23
3320 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */
3321 #define ALT_CLKMGR_PERPLL_VCO_PSRC_WIDTH 2
3322 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO_PSRC register field value. */
3323 #define ALT_CLKMGR_PERPLL_VCO_PSRC_SET_MSK 0x00c00000
3324 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_PSRC register field value. */
3325 #define ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK 0xff3fffff
3326 /* The reset value of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */
3327 #define ALT_CLKMGR_PERPLL_VCO_PSRC_RESET 0x0
3328 /* Extracts the ALT_CLKMGR_PERPLL_VCO_PSRC field value from a register. */
3329 #define ALT_CLKMGR_PERPLL_VCO_PSRC_GET(value) (((value) & 0x00c00000) >> 22)
3330 /* Produces a ALT_CLKMGR_PERPLL_VCO_PSRC register field value suitable for setting the register. */
3331 #define ALT_CLKMGR_PERPLL_VCO_PSRC_SET(value) (((value) << 22) & 0x00c00000)
3332 
3333 /*
3334  * Field : All Output Counter Reset - outresetall
3335  *
3336  * Before releasing Bypass, All Output Counter Reset must be set and cleared by
3337  * software for correct clock operation.
3338  *
3339  * If '1', Reset phase multiplexer and all output counter state. So that after the
3340  * assertion all the clocks output are start from rising edge align.
3341  *
3342  * If '0', phase multiplexer and output counter state not reset and no change to
3343  * the phase of the clock outputs.
3344  *
3345  * Field Access Macros:
3346  *
3347  */
3348 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */
3349 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_LSB 24
3350 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */
3351 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_MSB 24
3352 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */
3353 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_WIDTH 1
3354 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field value. */
3355 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_SET_MSK 0x01000000
3356 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field value. */
3357 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff
3358 /* The reset value of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */
3359 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_RESET 0x0
3360 /* Extracts the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL field value from a register. */
3361 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24)
3362 /* Produces a ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field value suitable for setting the register. */
3363 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000)
3364 
3365 /*
3366  * Field : Output Counter Reset - outreset
3367  *
3368  * Resets the individual PLL output counter.
3369  *
3370  * For software to change the PLL output counter without producing glitches on the
3371  * respective clock, SW must set the VCO register respective Output Counter Reset
3372  * bit. Software then polls the respective Output Counter Reset Acknowledge bit in
3373  * the Output Counter Reset Ack Status Register. Software then writes the
3374  * appropriate counter register, and then clears the respective VCO register Output
3375  * Counter Reset bit.
3376  *
3377  * LSB 'outreset[0]' corresponds to PLL output clock C0, etc.
3378  *
3379  * If set to '1', reset output divider, no clock output from counter.
3380  *
3381  * If set to '0', counter is not reset.
3382  *
3383  * The reset value of this bit is applied on a cold reset; warm reset has no affect
3384  * on this bit.
3385  *
3386  * Field Access Macros:
3387  *
3388  */
3389 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */
3390 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB 25
3391 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */
3392 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_MSB 30
3393 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */
3394 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_WIDTH 6
3395 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO_OUTRST register field value. */
3396 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_SET_MSK 0x7e000000
3397 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_OUTRST register field value. */
3398 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_CLR_MSK 0x81ffffff
3399 /* The reset value of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */
3400 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_RESET 0x0
3401 /* Extracts the ALT_CLKMGR_PERPLL_VCO_OUTRST field value from a register. */
3402 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25)
3403 /* Produces a ALT_CLKMGR_PERPLL_VCO_OUTRST register field value suitable for setting the register. */
3404 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000)
3405 
3406 /*
3407  * Field : External Regulator Input Select - regextsel
3408  *
3409  * If set to '1', the external regulator is selected for the PLL.
3410  *
3411  * If set to '0', the internal regulator is slected.
3412  *
3413  * It is strongly recommended to select the external regulator while the PLL is not
3414  * enabled (in reset), and then disable the external regulater once the PLL
3415  * becomes enabled. Software should simulateously update the 'Enable' bit and the
3416  * 'External Regulator Input Select' in the same write access to the VCO register.
3417  * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be
3418  * set, and vice versa.
3419  *
3420  * The reset value of this bit is applied on a cold reset; warm reset has no affect
3421  * on this bit.
3422  *
3423  * Field Access Macros:
3424  *
3425  */
3426 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */
3427 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_LSB 31
3428 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */
3429 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_MSB 31
3430 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */
3431 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_WIDTH 1
3432 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field value. */
3433 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_SET_MSK 0x80000000
3434 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field value. */
3435 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff
3436 /* The reset value of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */
3437 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_RESET 0x1
3438 /* Extracts the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL field value from a register. */
3439 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31)
3440 /* Produces a ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field value suitable for setting the register. */
3441 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000)
3442 
3443 #ifndef __ASSEMBLY__
3444 /*
3445  * WARNING: The C register and register group struct declarations are provided for
3446  * convenience and illustrative purposes. They should, however, be used with
3447  * caution as the C language standard provides no guarantees about the alignment or
3448  * atomicity of device memory accesses. The recommended practice for writing
3449  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3450  * alt_write_word() functions.
3451  *
3452  * The struct declaration for register ALT_CLKMGR_PERPLL_VCO.
3453  */
3454 struct ALT_CLKMGR_PERPLL_VCO_s
3455 {
3456  uint32_t bgpwrdn : 1; /* BG PWRDN */
3457  uint32_t en : 1; /* Enable */
3458  uint32_t pwrdn : 1; /* Power down */
3459  uint32_t numer : 13; /* Numerator (M) */
3460  uint32_t denom : 6; /* Denominator (N) */
3461  uint32_t psrc : 2; /* Clock Source */
3462  uint32_t outresetall : 1; /* All Output Counter Reset */
3463  uint32_t outreset : 6; /* Output Counter Reset */
3464  uint32_t regextsel : 1; /* External Regulator Input Select */
3465 };
3466 
3467 /* The typedef declaration for register ALT_CLKMGR_PERPLL_VCO. */
3468 typedef volatile struct ALT_CLKMGR_PERPLL_VCO_s ALT_CLKMGR_PERPLL_VCO_t;
3469 #endif /* __ASSEMBLY__ */
3470 
3471 /* The byte offset of the ALT_CLKMGR_PERPLL_VCO register from the beginning of the component. */
3472 #define ALT_CLKMGR_PERPLL_VCO_OFST 0x0
3473 
3474 /*
3475  * Register : Peripheral PLL VCO Advanced Control Register - misc
3476  *
3477  * Contains VCO control signals and other PLL control signals need to be
3478  * controllable through register.
3479  *
3480  * Fields are only reset by a cold reset.
3481  *
3482  * Register Layout
3483  *
3484  * Bits | Access | Reset | Description
3485  * :--------|:-------|:------|:------------------------------
3486  * [0] | RW | 0x0 | Loop Bandwidth Adjust Enabled
3487  * [12:1] | RW | 0x1 | Loop Bandwidth Adjust
3488  * [13] | RW | 0x0 | Fast Locking Enable
3489  * [14] | RW | 0x1 | Saturation Enable
3490  * [31:15] | ??? | 0x0 | *UNDEFINED*
3491  *
3492  */
3493 /*
3494  * Field : Loop Bandwidth Adjust Enabled - bwadjen
3495  *
3496  * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth
3497  * Adjust field.
3498  *
3499  * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2
3500  * value of the VCO Control Register. The M divided by 2 is the upper 12 bits
3501  * (12:1) of the M field in the VCO register.
3502  *
3503  * Field Access Macros:
3504  *
3505  */
3506 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */
3507 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_LSB 0
3508 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */
3509 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_MSB 0
3510 /* The width in bits of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */
3511 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_WIDTH 1
3512 /* The mask used to set the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field value. */
3513 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_SET_MSK 0x00000001
3514 /* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field value. */
3515 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_CLR_MSK 0xfffffffe
3516 /* The reset value of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */
3517 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_RESET 0x0
3518 /* Extracts the ALT_CLKMGR_PERPLL_MISC_BWADJEN field value from a register. */
3519 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_GET(value) (((value) & 0x00000001) >> 0)
3520 /* Produces a ALT_CLKMGR_PERPLL_MISC_BWADJEN register field value suitable for setting the register. */
3521 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_SET(value) (((value) << 0) & 0x00000001)
3522 
3523 /*
3524  * Field : Loop Bandwidth Adjust - bwadj
3525  *
3526  * Provides Loop Bandwidth Adjust value.
3527  *
3528  * Field Access Macros:
3529  *
3530  */
3531 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */
3532 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_LSB 1
3533 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */
3534 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_MSB 12
3535 /* The width in bits of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */
3536 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_WIDTH 12
3537 /* The mask used to set the ALT_CLKMGR_PERPLL_MISC_BWADJ register field value. */
3538 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_SET_MSK 0x00001ffe
3539 /* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_BWADJ register field value. */
3540 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_CLR_MSK 0xffffe001
3541 /* The reset value of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */
3542 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_RESET 0x1
3543 /* Extracts the ALT_CLKMGR_PERPLL_MISC_BWADJ field value from a register. */
3544 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1)
3545 /* Produces a ALT_CLKMGR_PERPLL_MISC_BWADJ register field value suitable for setting the register. */
3546 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_SET(value) (((value) << 1) & 0x00001ffe)
3547 
3548 /*
3549  * Field : Fast Locking Enable - fasten
3550  *
3551  * Enables fast locking circuit.
3552  *
3553  * Field Access Macros:
3554  *
3555  */
3556 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */
3557 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_LSB 13
3558 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */
3559 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_MSB 13
3560 /* The width in bits of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */
3561 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_WIDTH 1
3562 /* The mask used to set the ALT_CLKMGR_PERPLL_MISC_FASTEN register field value. */
3563 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_SET_MSK 0x00002000
3564 /* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_FASTEN register field value. */
3565 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_CLR_MSK 0xffffdfff
3566 /* The reset value of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */
3567 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_RESET 0x0
3568 /* Extracts the ALT_CLKMGR_PERPLL_MISC_FASTEN field value from a register. */
3569 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_GET(value) (((value) & 0x00002000) >> 13)
3570 /* Produces a ALT_CLKMGR_PERPLL_MISC_FASTEN register field value suitable for setting the register. */
3571 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_SET(value) (((value) << 13) & 0x00002000)
3572 
3573 /*
3574  * Field : Saturation Enable - saten
3575  *
3576  * Enables saturation behavior.
3577  *
3578  * Field Access Macros:
3579  *
3580  */
3581 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */
3582 #define ALT_CLKMGR_PERPLL_MISC_SATEN_LSB 14
3583 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */
3584 #define ALT_CLKMGR_PERPLL_MISC_SATEN_MSB 14
3585 /* The width in bits of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */
3586 #define ALT_CLKMGR_PERPLL_MISC_SATEN_WIDTH 1
3587 /* The mask used to set the ALT_CLKMGR_PERPLL_MISC_SATEN register field value. */
3588 #define ALT_CLKMGR_PERPLL_MISC_SATEN_SET_MSK 0x00004000
3589 /* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_SATEN register field value. */
3590 #define ALT_CLKMGR_PERPLL_MISC_SATEN_CLR_MSK 0xffffbfff
3591 /* The reset value of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */
3592 #define ALT_CLKMGR_PERPLL_MISC_SATEN_RESET 0x1
3593 /* Extracts the ALT_CLKMGR_PERPLL_MISC_SATEN field value from a register. */
3594 #define ALT_CLKMGR_PERPLL_MISC_SATEN_GET(value) (((value) & 0x00004000) >> 14)
3595 /* Produces a ALT_CLKMGR_PERPLL_MISC_SATEN register field value suitable for setting the register. */
3596 #define ALT_CLKMGR_PERPLL_MISC_SATEN_SET(value) (((value) << 14) & 0x00004000)
3597 
3598 #ifndef __ASSEMBLY__
3599 /*
3600  * WARNING: The C register and register group struct declarations are provided for
3601  * convenience and illustrative purposes. They should, however, be used with
3602  * caution as the C language standard provides no guarantees about the alignment or
3603  * atomicity of device memory accesses. The recommended practice for writing
3604  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3605  * alt_write_word() functions.
3606  *
3607  * The struct declaration for register ALT_CLKMGR_PERPLL_MISC.
3608  */
3609 struct ALT_CLKMGR_PERPLL_MISC_s
3610 {
3611  uint32_t bwadjen : 1; /* Loop Bandwidth Adjust Enabled */
3612  uint32_t bwadj : 12; /* Loop Bandwidth Adjust */
3613  uint32_t fasten : 1; /* Fast Locking Enable */
3614  uint32_t saten : 1; /* Saturation Enable */
3615  uint32_t : 17; /* *UNDEFINED* */
3616 };
3617 
3618 /* The typedef declaration for register ALT_CLKMGR_PERPLL_MISC. */
3619 typedef volatile struct ALT_CLKMGR_PERPLL_MISC_s ALT_CLKMGR_PERPLL_MISC_t;
3620 #endif /* __ASSEMBLY__ */
3621 
3622 /* The byte offset of the ALT_CLKMGR_PERPLL_MISC register from the beginning of the component. */
3623 #define ALT_CLKMGR_PERPLL_MISC_OFST 0x4
3624 
3625 /*
3626  * Register : Peripheral PLL C0 Control Register for Clock emac0_clk - emac0clk
3627  *
3628  * Contains settings that control clock emac0_clk generated from the C0 output of
3629  * the Peripheral PLL.
3630  *
3631  * Only reset by a cold reset.
3632  *
3633  * Register Layout
3634  *
3635  * Bits | Access | Reset | Description
3636  * :-------|:-------|:------|:------------
3637  * [8:0] | RW | 0x1 | Counter
3638  * [31:9] | ??? | 0x0 | *UNDEFINED*
3639  *
3640  */
3641 /*
3642  * Field : Counter - cnt
3643  *
3644  * Divides the VCO frequency by the value+1 in this field.
3645  *
3646  * Field Access Macros:
3647  *
3648  */
3649 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */
3650 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_LSB 0
3651 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */
3652 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_MSB 8
3653 /* The width in bits of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */
3654 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_WIDTH 9
3655 /* The mask used to set the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value. */
3656 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET_MSK 0x000001ff
3657 /* The mask used to clear the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value. */
3658 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_CLR_MSK 0xfffffe00
3659 /* The reset value of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */
3660 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_RESET 0x1
3661 /* Extracts the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT field value from a register. */
3662 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3663 /* Produces a ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value suitable for setting the register. */
3664 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3665 
3666 #ifndef __ASSEMBLY__
3667 /*
3668  * WARNING: The C register and register group struct declarations are provided for
3669  * convenience and illustrative purposes. They should, however, be used with
3670  * caution as the C language standard provides no guarantees about the alignment or
3671  * atomicity of device memory accesses. The recommended practice for writing
3672  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3673  * alt_write_word() functions.
3674  *
3675  * The struct declaration for register ALT_CLKMGR_PERPLL_EMAC0CLK.
3676  */
3677 struct ALT_CLKMGR_PERPLL_EMAC0CLK_s
3678 {
3679  uint32_t cnt : 9; /* Counter */
3680  uint32_t : 23; /* *UNDEFINED* */
3681 };
3682 
3683 /* The typedef declaration for register ALT_CLKMGR_PERPLL_EMAC0CLK. */
3684 typedef volatile struct ALT_CLKMGR_PERPLL_EMAC0CLK_s ALT_CLKMGR_PERPLL_EMAC0CLK_t;
3685 #endif /* __ASSEMBLY__ */
3686 
3687 /* The byte offset of the ALT_CLKMGR_PERPLL_EMAC0CLK register from the beginning of the component. */
3688 #define ALT_CLKMGR_PERPLL_EMAC0CLK_OFST 0x8
3689 
3690 /*
3691  * Register : Peripheral PLL C1 Control Register for Clock emac1_clk - emac1clk
3692  *
3693  * Contains settings that control clock emac1_clk generated from the C1 output of
3694  * the Peripheral PLL.
3695  *
3696  * Only reset by a cold reset.
3697  *
3698  * Register Layout
3699  *
3700  * Bits | Access | Reset | Description
3701  * :-------|:-------|:------|:------------
3702  * [8:0] | RW | 0x1 | Counter
3703  * [31:9] | ??? | 0x0 | *UNDEFINED*
3704  *
3705  */
3706 /*
3707  * Field : Counter - cnt
3708  *
3709  * Divides the VCO frequency by the value+1 in this field.
3710  *
3711  * Field Access Macros:
3712  *
3713  */
3714 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */
3715 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_LSB 0
3716 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */
3717 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_MSB 8
3718 /* The width in bits of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */
3719 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_WIDTH 9
3720 /* The mask used to set the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field value. */
3721 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET_MSK 0x000001ff
3722 /* The mask used to clear the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field value. */
3723 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_CLR_MSK 0xfffffe00
3724 /* The reset value of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */
3725 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_RESET 0x1
3726 /* Extracts the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT field value from a register. */
3727 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3728 /* Produces a ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field value suitable for setting the register. */
3729 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3730 
3731 #ifndef __ASSEMBLY__
3732 /*
3733  * WARNING: The C register and register group struct declarations are provided for
3734  * convenience and illustrative purposes. They should, however, be used with
3735  * caution as the C language standard provides no guarantees about the alignment or
3736  * atomicity of device memory accesses. The recommended practice for writing
3737  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3738  * alt_write_word() functions.
3739  *
3740  * The struct declaration for register ALT_CLKMGR_PERPLL_EMAC1CLK.
3741  */
3742 struct ALT_CLKMGR_PERPLL_EMAC1CLK_s
3743 {
3744  uint32_t cnt : 9; /* Counter */
3745  uint32_t : 23; /* *UNDEFINED* */
3746 };
3747 
3748 /* The typedef declaration for register ALT_CLKMGR_PERPLL_EMAC1CLK. */
3749 typedef volatile struct ALT_CLKMGR_PERPLL_EMAC1CLK_s ALT_CLKMGR_PERPLL_EMAC1CLK_t;
3750 #endif /* __ASSEMBLY__ */
3751 
3752 /* The byte offset of the ALT_CLKMGR_PERPLL_EMAC1CLK register from the beginning of the component. */
3753 #define ALT_CLKMGR_PERPLL_EMAC1CLK_OFST 0xc
3754 
3755 /*
3756  * Register : Peripheral PLL C2 Control Register for Clock periph_qspi_clk - perqspiclk
3757  *
3758  * Contains settings that control clock periph_qspi_clk generated from the C2
3759  * output of the Peripheral PLL.
3760  *
3761  * Only reset by a cold reset.
3762  *
3763  * Register Layout
3764  *
3765  * Bits | Access | Reset | Description
3766  * :-------|:-------|:------|:------------
3767  * [8:0] | RW | 0x1 | Counter
3768  * [31:9] | ??? | 0x0 | *UNDEFINED*
3769  *
3770  */
3771 /*
3772  * Field : Counter - cnt
3773  *
3774  * Divides the VCO frequency by the value+1 in this field.
3775  *
3776  * Field Access Macros:
3777  *
3778  */
3779 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */
3780 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_LSB 0
3781 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */
3782 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_MSB 8
3783 /* The width in bits of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */
3784 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_WIDTH 9
3785 /* The mask used to set the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field value. */
3786 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK 0x000001ff
3787 /* The mask used to clear the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field value. */
3788 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_CLR_MSK 0xfffffe00
3789 /* The reset value of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */
3790 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_RESET 0x1
3791 /* Extracts the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT field value from a register. */
3792 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3793 /* Produces a ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field value suitable for setting the register. */
3794 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3795 
3796 #ifndef __ASSEMBLY__
3797 /*
3798  * WARNING: The C register and register group struct declarations are provided for
3799  * convenience and illustrative purposes. They should, however, be used with
3800  * caution as the C language standard provides no guarantees about the alignment or
3801  * atomicity of device memory accesses. The recommended practice for writing
3802  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3803  * alt_write_word() functions.
3804  *
3805  * The struct declaration for register ALT_CLKMGR_PERPLL_PERQSPICLK.
3806  */
3807 struct ALT_CLKMGR_PERPLL_PERQSPICLK_s
3808 {
3809  uint32_t cnt : 9; /* Counter */
3810  uint32_t : 23; /* *UNDEFINED* */
3811 };
3812 
3813 /* The typedef declaration for register ALT_CLKMGR_PERPLL_PERQSPICLK. */
3814 typedef volatile struct ALT_CLKMGR_PERPLL_PERQSPICLK_s ALT_CLKMGR_PERPLL_PERQSPICLK_t;
3815 #endif /* __ASSEMBLY__ */
3816 
3817 /* The byte offset of the ALT_CLKMGR_PERPLL_PERQSPICLK register from the beginning of the component. */
3818 #define ALT_CLKMGR_PERPLL_PERQSPICLK_OFST 0x10
3819 
3820 /*
3821  * Register : Peripheral PLL C3 Control Register for Clock periph_nand_sdmmc_clk - pernandsdmmcclk
3822  *
3823  * Contains settings that control clock periph_nand_sdmmc_clk generated from the C3
3824  * output of the Peripheral PLL.
3825  *
3826  * Only reset by a cold reset.
3827  *
3828  * Register Layout
3829  *
3830  * Bits | Access | Reset | Description
3831  * :-------|:-------|:------|:------------
3832  * [8:0] | RW | 0x1 | Counter
3833  * [31:9] | ??? | 0x0 | *UNDEFINED*
3834  *
3835  */
3836 /*
3837  * Field : Counter - cnt
3838  *
3839  * Divides the VCO frequency by the value+1 in this field.
3840  *
3841  * Field Access Macros:
3842  *
3843  */
3844 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */
3845 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_LSB 0
3846 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */
3847 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_MSB 8
3848 /* The width in bits of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */
3849 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_WIDTH 9
3850 /* The mask used to set the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field value. */
3851 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET_MSK 0x000001ff
3852 /* The mask used to clear the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field value. */
3853 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_CLR_MSK 0xfffffe00
3854 /* The reset value of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */
3855 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_RESET 0x1
3856 /* Extracts the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT field value from a register. */
3857 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3858 /* Produces a ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field value suitable for setting the register. */
3859 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3860 
3861 #ifndef __ASSEMBLY__
3862 /*
3863  * WARNING: The C register and register group struct declarations are provided for
3864  * convenience and illustrative purposes. They should, however, be used with
3865  * caution as the C language standard provides no guarantees about the alignment or
3866  * atomicity of device memory accesses. The recommended practice for writing
3867  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3868  * alt_write_word() functions.
3869  *
3870  * The struct declaration for register ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK.
3871  */
3872 struct ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_s
3873 {
3874  uint32_t cnt : 9; /* Counter */
3875  uint32_t : 23; /* *UNDEFINED* */
3876 };
3877 
3878 /* The typedef declaration for register ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK. */
3879 typedef volatile struct ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_s ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_t;
3880 #endif /* __ASSEMBLY__ */
3881 
3882 /* The byte offset of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK register from the beginning of the component. */
3883 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_OFST 0x14
3884 
3885 /*
3886  * Register : Peripheral PLL C4 Control Register for Clock periph_base_clk - perbaseclk
3887  *
3888  * Contains settings that control clock periph_base_clk generated from the C4
3889  * output of the Peripheral PLL.
3890  *
3891  * Only reset by a cold reset.
3892  *
3893  * Register Layout
3894  *
3895  * Bits | Access | Reset | Description
3896  * :-------|:-------|:------|:------------
3897  * [8:0] | RW | 0x1 | Counter
3898  * [31:9] | ??? | 0x0 | *UNDEFINED*
3899  *
3900  */
3901 /*
3902  * Field : Counter - cnt
3903  *
3904  * Divides the VCO frequency by the value+1 in this field.
3905  *
3906  * Field Access Macros:
3907  *
3908  */
3909 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */
3910 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_LSB 0
3911 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */
3912 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_MSB 8
3913 /* The width in bits of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */
3914 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_WIDTH 9
3915 /* The mask used to set the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field value. */
3916 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET_MSK 0x000001ff
3917 /* The mask used to clear the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field value. */
3918 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_CLR_MSK 0xfffffe00
3919 /* The reset value of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */
3920 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_RESET 0x1
3921 /* Extracts the ALT_CLKMGR_PERPLL_PERBASECLK_CNT field value from a register. */
3922 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3923 /* Produces a ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field value suitable for setting the register. */
3924 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3925 
3926 #ifndef __ASSEMBLY__
3927 /*
3928  * WARNING: The C register and register group struct declarations are provided for
3929  * convenience and illustrative purposes. They should, however, be used with
3930  * caution as the C language standard provides no guarantees about the alignment or
3931  * atomicity of device memory accesses. The recommended practice for writing
3932  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3933  * alt_write_word() functions.
3934  *
3935  * The struct declaration for register ALT_CLKMGR_PERPLL_PERBASECLK.
3936  */
3937 struct ALT_CLKMGR_PERPLL_PERBASECLK_s
3938 {
3939  uint32_t cnt : 9; /* Counter */
3940  uint32_t : 23; /* *UNDEFINED* */
3941 };
3942 
3943 /* The typedef declaration for register ALT_CLKMGR_PERPLL_PERBASECLK. */
3944 typedef volatile struct ALT_CLKMGR_PERPLL_PERBASECLK_s ALT_CLKMGR_PERPLL_PERBASECLK_t;
3945 #endif /* __ASSEMBLY__ */
3946 
3947 /* The byte offset of the ALT_CLKMGR_PERPLL_PERBASECLK register from the beginning of the component. */
3948 #define ALT_CLKMGR_PERPLL_PERBASECLK_OFST 0x18
3949 
3950 /*
3951  * Register : Peripheral PLL C5 Control Register for Clock s2f_user1_clk - s2fuser1clk
3952  *
3953  * Contains settings that control clock s2f_user1_clk generated from the C5 output
3954  * of the Peripheral PLL.
3955  *
3956  * Qsys and user documenation refer to s2f_user1_clk as h2f_user1_clk.
3957  *
3958  * Only reset by a cold reset.
3959  *
3960  * Register Layout
3961  *
3962  * Bits | Access | Reset | Description
3963  * :-------|:-------|:------|:------------
3964  * [8:0] | RW | 0x1 | Counter
3965  * [31:9] | ??? | 0x0 | *UNDEFINED*
3966  *
3967  */
3968 /*
3969  * Field : Counter - cnt
3970  *
3971  * Divides the VCO frequency by the value+1 in this field.
3972  *
3973  * Field Access Macros:
3974  *
3975  */
3976 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */
3977 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_LSB 0
3978 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */
3979 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_MSB 8
3980 /* The width in bits of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */
3981 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_WIDTH 9
3982 /* The mask used to set the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field value. */
3983 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET_MSK 0x000001ff
3984 /* The mask used to clear the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field value. */
3985 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_CLR_MSK 0xfffffe00
3986 /* The reset value of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */
3987 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_RESET 0x1
3988 /* Extracts the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT field value from a register. */
3989 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3990 /* Produces a ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field value suitable for setting the register. */
3991 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3992 
3993 #ifndef __ASSEMBLY__
3994 /*
3995  * WARNING: The C register and register group struct declarations are provided for
3996  * convenience and illustrative purposes. They should, however, be used with
3997  * caution as the C language standard provides no guarantees about the alignment or
3998  * atomicity of device memory accesses. The recommended practice for writing
3999  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4000  * alt_write_word() functions.
4001  *
4002  * The struct declaration for register ALT_CLKMGR_PERPLL_S2FUSER1CLK.
4003  */
4004 struct ALT_CLKMGR_PERPLL_S2FUSER1CLK_s
4005 {
4006  uint32_t cnt : 9; /* Counter */
4007  uint32_t : 23; /* *UNDEFINED* */
4008 };
4009 
4010 /* The typedef declaration for register ALT_CLKMGR_PERPLL_S2FUSER1CLK. */
4011 typedef volatile struct ALT_CLKMGR_PERPLL_S2FUSER1CLK_s ALT_CLKMGR_PERPLL_S2FUSER1CLK_t;
4012 #endif /* __ASSEMBLY__ */
4013 
4014 /* The byte offset of the ALT_CLKMGR_PERPLL_S2FUSER1CLK register from the beginning of the component. */
4015 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_OFST 0x1c
4016 
4017 /*
4018  * Register : Enable Register - en
4019  *
4020  * Contains fields that control clock enables for clocks derived from the
4021  * Peripheral PLL
4022  *
4023  * 1: The clock is enabled.
4024  *
4025  * 0: The clock is disabled.
4026  *
4027  * Fields are only reset by a cold reset.
4028  *
4029  * Register Layout
4030  *
4031  * Bits | Access | Reset | Description
4032  * :--------|:-------|:------|:---------------------
4033  * [0] | RW | 0x1 | emac0_clk Enable
4034  * [1] | RW | 0x1 | emac1_clk Enable
4035  * [2] | RW | 0x1 | usb_mp_clk Enable
4036  * [3] | RW | 0x1 | spi_m_clk Enable
4037  * [4] | RW | 0x1 | can0_clk Enable
4038  * [5] | RW | 0x1 | can1_clk Enable
4039  * [6] | RW | 0x1 | gpio_clk Enable
4040  * [7] | RW | 0x1 | s2f_user1_clk Enable
4041  * [8] | RW | 0x1 | sdmmc_clk Enable
4042  * [9] | RW | 0x1 | nand_x_clk Enable
4043  * [10] | RW | 0x1 | nand_clk Enable
4044  * [11] | RW | 0x1 | qspi_clk Enable
4045  * [31:12] | ??? | 0x0 | *UNDEFINED*
4046  *
4047  */
4048 /*
4049  * Field : emac0_clk Enable - emac0clk
4050  *
4051  * Enables clock emac0_clk output
4052  *
4053  * Field Access Macros:
4054  *
4055  */
4056 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */
4057 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_LSB 0
4058 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */
4059 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_MSB 0
4060 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */
4061 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_WIDTH 1
4062 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value. */
4063 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK 0x00000001
4064 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value. */
4065 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_CLR_MSK 0xfffffffe
4066 /* The reset value of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */
4067 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_RESET 0x1
4068 /* Extracts the ALT_CLKMGR_PERPLL_EN_EMAC0CLK field value from a register. */
4069 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_GET(value) (((value) & 0x00000001) >> 0)
4070 /* Produces a ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value suitable for setting the register. */
4071 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET(value) (((value) << 0) & 0x00000001)
4072 
4073 /*
4074  * Field : emac1_clk Enable - emac1clk
4075  *
4076  * Enables clock emac1_clk output
4077  *
4078  * Field Access Macros:
4079  *
4080  */
4081 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */
4082 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_LSB 1
4083 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */
4084 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_MSB 1
4085 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */
4086 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_WIDTH 1
4087 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value. */
4088 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK 0x00000002
4089 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value. */
4090 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_CLR_MSK 0xfffffffd
4091 /* The reset value of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */
4092 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_RESET 0x1
4093 /* Extracts the ALT_CLKMGR_PERPLL_EN_EMAC1CLK field value from a register. */
4094 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_GET(value) (((value) & 0x00000002) >> 1)
4095 /* Produces a ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value suitable for setting the register. */
4096 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET(value) (((value) << 1) & 0x00000002)
4097 
4098 /*
4099  * Field : usb_mp_clk Enable - usbclk
4100  *
4101  * Enables clock usb_mp_clk output
4102  *
4103  * Field Access Macros:
4104  *
4105  */
4106 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */
4107 #define ALT_CLKMGR_PERPLL_EN_USBCLK_LSB 2
4108 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */
4109 #define ALT_CLKMGR_PERPLL_EN_USBCLK_MSB 2
4110 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */
4111 #define ALT_CLKMGR_PERPLL_EN_USBCLK_WIDTH 1
4112 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_USBCLK register field value. */
4113 #define ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK 0x00000004
4114 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_USBCLK register field value. */
4115 #define ALT_CLKMGR_PERPLL_EN_USBCLK_CLR_MSK 0xfffffffb
4116 /* The reset value of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */
4117 #define ALT_CLKMGR_PERPLL_EN_USBCLK_RESET 0x1
4118 /* Extracts the ALT_CLKMGR_PERPLL_EN_USBCLK field value from a register. */
4119 #define ALT_CLKMGR_PERPLL_EN_USBCLK_GET(value) (((value) & 0x00000004) >> 2)
4120 /* Produces a ALT_CLKMGR_PERPLL_EN_USBCLK register field value suitable for setting the register. */
4121 #define ALT_CLKMGR_PERPLL_EN_USBCLK_SET(value) (((value) << 2) & 0x00000004)
4122 
4123 /*
4124  * Field : spi_m_clk Enable - spimclk
4125  *
4126  * Enables clock spi_m_clk output
4127  *
4128  * Field Access Macros:
4129  *
4130  */
4131 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */
4132 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_LSB 3
4133 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */
4134 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_MSB 3
4135 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */
4136 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_WIDTH 1
4137 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value. */
4138 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK 0x00000008
4139 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value. */
4140 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_CLR_MSK 0xfffffff7
4141 /* The reset value of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */
4142 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_RESET 0x1
4143 /* Extracts the ALT_CLKMGR_PERPLL_EN_SPIMCLK field value from a register. */
4144 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_GET(value) (((value) & 0x00000008) >> 3)
4145 /* Produces a ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value suitable for setting the register. */
4146 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET(value) (((value) << 3) & 0x00000008)
4147 
4148 /*
4149  * Field : can0_clk Enable - can0clk
4150  *
4151  * Enables clock can0_clk output
4152  *
4153  * Field Access Macros:
4154  *
4155  */
4156 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */
4157 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_LSB 4
4158 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */
4159 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_MSB 4
4160 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */
4161 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_WIDTH 1
4162 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value. */
4163 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK 0x00000010
4164 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value. */
4165 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_CLR_MSK 0xffffffef
4166 /* The reset value of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */
4167 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_RESET 0x1
4168 /* Extracts the ALT_CLKMGR_PERPLL_EN_CAN0CLK field value from a register. */
4169 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_GET(value) (((value) & 0x00000010) >> 4)
4170 /* Produces a ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value suitable for setting the register. */
4171 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET(value) (((value) << 4) & 0x00000010)
4172 
4173 /*
4174  * Field : can1_clk Enable - can1clk
4175  *
4176  * Enables clock can1_clk output
4177  *
4178  * Field Access Macros:
4179  *
4180  */
4181 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */
4182 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_LSB 5
4183 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */
4184 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_MSB 5
4185 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */
4186 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_WIDTH 1
4187 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value. */
4188 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK 0x00000020
4189 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value. */
4190 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_CLR_MSK 0xffffffdf
4191 /* The reset value of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */
4192 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_RESET 0x1
4193 /* Extracts the ALT_CLKMGR_PERPLL_EN_CAN1CLK field value from a register. */
4194 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_GET(value) (((value) & 0x00000020) >> 5)
4195 /* Produces a ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value suitable for setting the register. */
4196 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET(value) (((value) << 5) & 0x00000020)
4197 
4198 /*
4199  * Field : gpio_clk Enable - gpioclk
4200  *
4201  * Enables clock gpio_clk output
4202  *
4203  * Field Access Macros:
4204  *
4205  */
4206 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */
4207 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_LSB 6
4208 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */
4209 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_MSB 6
4210 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */
4211 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_WIDTH 1
4212 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value. */
4213 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK 0x00000040
4214 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value. */
4215 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_CLR_MSK 0xffffffbf
4216 /* The reset value of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */
4217 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_RESET 0x1
4218 /* Extracts the ALT_CLKMGR_PERPLL_EN_GPIOCLK field value from a register. */
4219 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_GET(value) (((value) & 0x00000040) >> 6)
4220 /* Produces a ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value suitable for setting the register. */
4221 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET(value) (((value) << 6) & 0x00000040)
4222 
4223 /*
4224  * Field : s2f_user1_clk Enable - s2fuser1clk
4225  *
4226  * Enables clock s2f_user1_clk output.
4227  *
4228  * Qsys and user documenation refer to s2f_user1_clk as h2f_user1_clk.
4229  *
4230  * Field Access Macros:
4231  *
4232  */
4233 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */
4234 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_LSB 7
4235 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */
4236 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_MSB 7
4237 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */
4238 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_WIDTH 1
4239 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value. */
4240 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK 0x00000080
4241 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value. */
4242 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_CLR_MSK 0xffffff7f
4243 /* The reset value of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */
4244 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_RESET 0x1
4245 /* Extracts the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK field value from a register. */
4246 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_GET(value) (((value) & 0x00000080) >> 7)
4247 /* Produces a ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value suitable for setting the register. */
4248 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET(value) (((value) << 7) & 0x00000080)
4249 
4250 /*
4251  * Field : sdmmc_clk Enable - sdmmcclk
4252  *
4253  * Enables clock sdmmc_clk output
4254  *
4255  * Field Access Macros:
4256  *
4257  */
4258 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */
4259 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_LSB 8
4260 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */
4261 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_MSB 8
4262 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */
4263 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_WIDTH 1
4264 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value. */
4265 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK 0x00000100
4266 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value. */
4267 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK 0xfffffeff
4268 /* The reset value of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */
4269 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_RESET 0x1
4270 /* Extracts the ALT_CLKMGR_PERPLL_EN_SDMMCCLK field value from a register. */
4271 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_GET(value) (((value) & 0x00000100) >> 8)
4272 /* Produces a ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value suitable for setting the register. */
4273 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET(value) (((value) << 8) & 0x00000100)
4274 
4275 /*
4276  * Field : nand_x_clk Enable - nandxclk
4277  *
4278  * Enables clock nand_x_clk output
4279  *
4280  * nand_clk Enable should always be de-asserted before the nand_x_clk Enable, and
4281  * the nand_x_clk Enable should always be asserted before the nand_clk Enable is
4282  * asserted. A brief delay is also required between switching the enables (8 *
4283  * nand_clk period).
4284  *
4285  * Field Access Macros:
4286  *
4287  */
4288 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */
4289 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_LSB 9
4290 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */
4291 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_MSB 9
4292 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */
4293 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_WIDTH 1
4294 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value. */
4295 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK 0x00000200
4296 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value. */
4297 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK 0xfffffdff
4298 /* The reset value of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */
4299 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_RESET 0x1
4300 /* Extracts the ALT_CLKMGR_PERPLL_EN_NANDXCLK field value from a register. */
4301 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_GET(value) (((value) & 0x00000200) >> 9)
4302 /* Produces a ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value suitable for setting the register. */
4303 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET(value) (((value) << 9) & 0x00000200)
4304 
4305 /*
4306  * Field : nand_clk Enable - nandclk
4307  *
4308  * Enables clock nand_clk output
4309  *
4310  * nand_clk Enable should always be de-asserted before the nand_x_clk Enable, and
4311  * the nand_x_clk Enable should always be asserted before the nand_clk Enable is
4312  * asserted. A brief delay is also required between switching the enables (8 *
4313  * nand_clk period).
4314  *
4315  * Field Access Macros:
4316  *
4317  */
4318 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */
4319 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_LSB 10
4320 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */
4321 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_MSB 10
4322 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */
4323 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_WIDTH 1
4324 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_NANDCLK register field value. */
4325 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK 0x00000400
4326 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_NANDCLK register field value. */
4327 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK 0xfffffbff
4328 /* The reset value of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */
4329 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_RESET 0x1
4330 /* Extracts the ALT_CLKMGR_PERPLL_EN_NANDCLK field value from a register. */
4331 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_GET(value) (((value) & 0x00000400) >> 10)
4332 /* Produces a ALT_CLKMGR_PERPLL_EN_NANDCLK register field value suitable for setting the register. */
4333 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_SET(value) (((value) << 10) & 0x00000400)
4334 
4335 /*
4336  * Field : qspi_clk Enable - qspiclk
4337  *
4338  * Enables clock qspi_clk output
4339  *
4340  * Field Access Macros:
4341  *
4342  */
4343 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */
4344 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_LSB 11
4345 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */
4346 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_MSB 11
4347 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */
4348 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_WIDTH 1
4349 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_QSPICLK register field value. */
4350 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK 0x00000800
4351 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_QSPICLK register field value. */
4352 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK 0xfffff7ff
4353 /* The reset value of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */
4354 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_RESET 0x1
4355 /* Extracts the ALT_CLKMGR_PERPLL_EN_QSPICLK field value from a register. */
4356 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_GET(value) (((value) & 0x00000800) >> 11)
4357 /* Produces a ALT_CLKMGR_PERPLL_EN_QSPICLK register field value suitable for setting the register. */
4358 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_SET(value) (((value) << 11) & 0x00000800)
4359 
4360 #ifndef __ASSEMBLY__
4361 /*
4362  * WARNING: The C register and register group struct declarations are provided for
4363  * convenience and illustrative purposes. They should, however, be used with
4364  * caution as the C language standard provides no guarantees about the alignment or
4365  * atomicity of device memory accesses. The recommended practice for writing
4366  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4367  * alt_write_word() functions.
4368  *
4369  * The struct declaration for register ALT_CLKMGR_PERPLL_EN.
4370  */
4371 struct ALT_CLKMGR_PERPLL_EN_s
4372 {
4373  uint32_t emac0clk : 1; /* emac0_clk Enable */
4374  uint32_t emac1clk : 1; /* emac1_clk Enable */
4375  uint32_t usbclk : 1; /* usb_mp_clk Enable */
4376  uint32_t spimclk : 1; /* spi_m_clk Enable */
4377  uint32_t can0clk : 1; /* can0_clk Enable */
4378  uint32_t can1clk : 1; /* can1_clk Enable */
4379  uint32_t gpioclk : 1; /* gpio_clk Enable */
4380  uint32_t s2fuser1clk : 1; /* s2f_user1_clk Enable */
4381  uint32_t sdmmcclk : 1; /* sdmmc_clk Enable */
4382  uint32_t nandxclk : 1; /* nand_x_clk Enable */
4383  uint32_t nandclk : 1; /* nand_clk Enable */
4384  uint32_t qspiclk : 1; /* qspi_clk Enable */
4385  uint32_t : 20; /* *UNDEFINED* */
4386 };
4387 
4388 /* The typedef declaration for register ALT_CLKMGR_PERPLL_EN. */
4389 typedef volatile struct ALT_CLKMGR_PERPLL_EN_s ALT_CLKMGR_PERPLL_EN_t;
4390 #endif /* __ASSEMBLY__ */
4391 
4392 /* The byte offset of the ALT_CLKMGR_PERPLL_EN register from the beginning of the component. */
4393 #define ALT_CLKMGR_PERPLL_EN_OFST 0x20
4394 
4395 /*
4396  * Register : Divide Register - div
4397  *
4398  * Contains fields that control clock dividers for clocks derived from the
4399  * Peripheral PLL
4400  *
4401  * Fields are only reset by a cold reset.
4402  *
4403  * Register Layout
4404  *
4405  * Bits | Access | Reset | Description
4406  * :--------|:-------|:------|:-------------------------
4407  * [2:0] | RW | 0x0 | USB Clock Divider
4408  * [5:3] | RW | 0x0 | SPI Master Clock Divider
4409  * [8:6] | RW | 0x0 | CAN0 Clock Divider
4410  * [11:9] | RW | 0x0 | CAN1 Clock Divider
4411  * [31:12] | ??? | 0x0 | *UNDEFINED*
4412  *
4413  */
4414 /*
4415  * Field : USB Clock Divider - usbclk
4416  *
4417  * The usb_mp_clk is divided down from the periph_base_clk by the value specified
4418  * in this field.
4419  *
4420  * Field Enumeration Values:
4421  *
4422  * Enum | Value | Description
4423  * :--------------------------------------|:------|:-------------
4424  * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1 | 0x0 | Divide By 1
4425  * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2 | 0x1 | Divide By 2
4426  * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4 | 0x2 | Divide By 4
4427  * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8 | 0x3 | Divide By 8
4428  * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16 | 0x4 | Divide By 16
4429  * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_1 | 0x5 | Reserved
4430  * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_2 | 0x6 | Reserved
4431  * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_3 | 0x7 | Reserved
4432  *
4433  * Field Access Macros:
4434  *
4435  */
4436 /*
4437  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
4438  *
4439  * Divide By 1
4440  */
4441 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1 0x0
4442 /*
4443  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
4444  *
4445  * Divide By 2
4446  */
4447 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2 0x1
4448 /*
4449  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
4450  *
4451  * Divide By 4
4452  */
4453 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4 0x2
4454 /*
4455  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
4456  *
4457  * Divide By 8
4458  */
4459 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8 0x3
4460 /*
4461  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
4462  *
4463  * Divide By 16
4464  */
4465 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16 0x4
4466 /*
4467  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
4468  *
4469  * Reserved
4470  */
4471 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_1 0x5
4472 /*
4473  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
4474  *
4475  * Reserved
4476  */
4477 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_2 0x6
4478 /*
4479  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
4480  *
4481  * Reserved
4482  */
4483 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_3 0x7
4484 
4485 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */
4486 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_LSB 0
4487 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */
4488 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_MSB 2
4489 /* The width in bits of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */
4490 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_WIDTH 3
4491 /* The mask used to set the ALT_CLKMGR_PERPLL_DIV_USBCLK register field value. */
4492 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_SET_MSK 0x00000007
4493 /* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_USBCLK register field value. */
4494 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_CLR_MSK 0xfffffff8
4495 /* The reset value of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */
4496 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_RESET 0x0
4497 /* Extracts the ALT_CLKMGR_PERPLL_DIV_USBCLK field value from a register. */
4498 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_GET(value) (((value) & 0x00000007) >> 0)
4499 /* Produces a ALT_CLKMGR_PERPLL_DIV_USBCLK register field value suitable for setting the register. */
4500 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_SET(value) (((value) << 0) & 0x00000007)
4501 
4502 /*
4503  * Field : SPI Master Clock Divider - spimclk
4504  *
4505  * The spi_m_clk is divided down from the periph_base_clk by the value specified in
4506  * this field.
4507  *
4508  * Field Enumeration Values:
4509  *
4510  * Enum | Value | Description
4511  * :---------------------------------------|:------|:-------------
4512  * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1 | 0x0 | Divide By 1
4513  * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2 | 0x1 | Divide By 2
4514  * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4 | 0x2 | Divide By 4
4515  * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8 | 0x3 | Divide By 8
4516  * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16 | 0x4 | Divide By 16
4517  * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_1 | 0x5 | Reserved
4518  * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_2 | 0x6 | Reserved
4519  * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_3 | 0x7 | Reserved
4520  *
4521  * Field Access Macros:
4522  *
4523  */
4524 /*
4525  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
4526  *
4527  * Divide By 1
4528  */
4529 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1 0x0
4530 /*
4531  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
4532  *
4533  * Divide By 2
4534  */
4535 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2 0x1
4536 /*
4537  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
4538  *
4539  * Divide By 4
4540  */
4541 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4 0x2
4542 /*
4543  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
4544  *
4545  * Divide By 8
4546  */
4547 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8 0x3
4548 /*
4549  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
4550  *
4551  * Divide By 16
4552  */
4553 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16 0x4
4554 /*
4555  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
4556  *
4557  * Reserved
4558  */
4559 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_1 0x5
4560 /*
4561  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
4562  *
4563  * Reserved
4564  */
4565 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_2 0x6
4566 /*
4567  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
4568  *
4569  * Reserved
4570  */
4571 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_3 0x7
4572 
4573 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */
4574 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_LSB 3
4575 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */
4576 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_MSB 5
4577 /* The width in bits of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */
4578 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_WIDTH 3
4579 /* The mask used to set the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value. */
4580 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET_MSK 0x00000038
4581 /* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value. */
4582 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_CLR_MSK 0xffffffc7
4583 /* The reset value of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */
4584 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_RESET 0x0
4585 /* Extracts the ALT_CLKMGR_PERPLL_DIV_SPIMCLK field value from a register. */
4586 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_GET(value) (((value) & 0x00000038) >> 3)
4587 /* Produces a ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value suitable for setting the register. */
4588 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET(value) (((value) << 3) & 0x00000038)
4589 
4590 /*
4591  * Field : CAN0 Clock Divider - can0clk
4592  *
4593  * The can0_clk is divided down from the periph_base_clk by the value specified in
4594  * this field.
4595  *
4596  * Field Enumeration Values:
4597  *
4598  * Enum | Value | Description
4599  * :---------------------------------------|:------|:-------------
4600  * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1 | 0x0 | Divide By 1
4601  * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2 | 0x1 | Divide By 2
4602  * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4 | 0x2 | Divide By 4
4603  * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8 | 0x3 | Divide By 8
4604  * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16 | 0x4 | Divide By 16
4605  * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_1 | 0x5 | Reserved
4606  * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_2 | 0x6 | Reserved
4607  * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_3 | 0x7 | Reserved
4608  *
4609  * Field Access Macros:
4610  *
4611  */
4612 /*
4613  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
4614  *
4615  * Divide By 1
4616  */
4617 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1 0x0
4618 /*
4619  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
4620  *
4621  * Divide By 2
4622  */
4623 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2 0x1
4624 /*
4625  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
4626  *
4627  * Divide By 4
4628  */
4629 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4 0x2
4630 /*
4631  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
4632  *
4633  * Divide By 8
4634  */
4635 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8 0x3
4636 /*
4637  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
4638  *
4639  * Divide By 16
4640  */
4641 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16 0x4
4642 /*
4643  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
4644  *
4645  * Reserved
4646  */
4647 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_1 0x5
4648 /*
4649  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
4650  *
4651  * Reserved
4652  */
4653 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_2 0x6
4654 /*
4655  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
4656  *
4657  * Reserved
4658  */
4659 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_3 0x7
4660 
4661 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */
4662 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_LSB 6
4663 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */
4664 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_MSB 8
4665 /* The width in bits of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */
4666 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_WIDTH 3
4667 /* The mask used to set the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value. */
4668 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET_MSK 0x000001c0
4669 /* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value. */
4670 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_CLR_MSK 0xfffffe3f
4671 /* The reset value of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */
4672 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_RESET 0x0
4673 /* Extracts the ALT_CLKMGR_PERPLL_DIV_CAN0CLK field value from a register. */
4674 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_GET(value) (((value) & 0x000001c0) >> 6)
4675 /* Produces a ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value suitable for setting the register. */
4676 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET(value) (((value) << 6) & 0x000001c0)
4677 
4678 /*
4679  * Field : CAN1 Clock Divider - can1clk
4680  *
4681  * The can1_clk is divided down from the periph_base_clk by the value specified in
4682  * this field.
4683  *
4684  * Field Enumeration Values:
4685  *
4686  * Enum | Value | Description
4687  * :---------------------------------------|:------|:-------------
4688  * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1 | 0x0 | Divide By 1
4689  * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2 | 0x1 | Divide By 2
4690  * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4 | 0x2 | Divide By 4
4691  * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8 | 0x3 | Divide By 8
4692  * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16 | 0x4 | Divide By 16
4693  * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_1 | 0x5 | Reserved
4694  * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_2 | 0x6 | Reserved
4695  * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_3 | 0x7 | Reserved
4696  *
4697  * Field Access Macros:
4698  *
4699  */
4700 /*
4701  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
4702  *
4703  * Divide By 1
4704  */
4705 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1 0x0
4706 /*
4707  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
4708  *
4709  * Divide By 2
4710  */
4711 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2 0x1
4712 /*
4713  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
4714  *
4715  * Divide By 4
4716  */
4717 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4 0x2
4718 /*
4719  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
4720  *
4721  * Divide By 8
4722  */
4723 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8 0x3
4724 /*
4725  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
4726  *
4727  * Divide By 16
4728  */
4729 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16 0x4
4730 /*
4731  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
4732  *
4733  * Reserved
4734  */
4735 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_1 0x5
4736 /*
4737  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
4738  *
4739  * Reserved
4740  */
4741 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_2 0x6
4742 /*
4743  * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
4744  *
4745  * Reserved
4746  */
4747 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_3 0x7
4748 
4749 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */
4750 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_LSB 9
4751 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */
4752 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_MSB 11
4753 /* The width in bits of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */
4754 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_WIDTH 3
4755 /* The mask used to set the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value. */
4756 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET_MSK 0x00000e00
4757 /* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value. */
4758 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_CLR_MSK 0xfffff1ff
4759 /* The reset value of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */
4760 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_RESET 0x0
4761 /* Extracts the ALT_CLKMGR_PERPLL_DIV_CAN1CLK field value from a register. */
4762 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_GET(value) (((value) & 0x00000e00) >> 9)
4763 /* Produces a ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value suitable for setting the register. */
4764 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET(value) (((value) << 9) & 0x00000e00)
4765 
4766 #ifndef __ASSEMBLY__
4767 /*
4768  * WARNING: The C register and register group struct declarations are provided for
4769  * convenience and illustrative purposes. They should, however, be used with
4770  * caution as the C language standard provides no guarantees about the alignment or
4771  * atomicity of device memory accesses. The recommended practice for writing
4772  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4773  * alt_write_word() functions.
4774  *
4775  * The struct declaration for register ALT_CLKMGR_PERPLL_DIV.
4776  */
4777 struct ALT_CLKMGR_PERPLL_DIV_s
4778 {
4779  uint32_t usbclk : 3; /* USB Clock Divider */
4780  uint32_t spimclk : 3; /* SPI Master Clock Divider */
4781  uint32_t can0clk : 3; /* CAN0 Clock Divider */
4782  uint32_t can1clk : 3; /* CAN1 Clock Divider */
4783  uint32_t : 20; /* *UNDEFINED* */
4784 };
4785 
4786 /* The typedef declaration for register ALT_CLKMGR_PERPLL_DIV. */
4787 typedef volatile struct ALT_CLKMGR_PERPLL_DIV_s ALT_CLKMGR_PERPLL_DIV_t;
4788 #endif /* __ASSEMBLY__ */
4789 
4790 /* The byte offset of the ALT_CLKMGR_PERPLL_DIV register from the beginning of the component. */
4791 #define ALT_CLKMGR_PERPLL_DIV_OFST 0x24
4792 
4793 /*
4794  * Register : GPIO Divide Register - gpiodiv
4795  *
4796  * Contains a field that controls the clock divider for the GPIO De-bounce clock.
4797  *
4798  * Only reset by a cold reset.
4799  *
4800  * Register Layout
4801  *
4802  * Bits | Access | Reset | Description
4803  * :--------|:-------|:------|:-----------------------------
4804  * [23:0] | RW | 0x1 | GPIO De-bounce Clock Divider
4805  * [31:24] | ??? | 0x0 | *UNDEFINED*
4806  *
4807  */
4808 /*
4809  * Field : GPIO De-bounce Clock Divider - gpiodbclk
4810  *
4811  * The gpio_db_clk is divided down from the periph_base_clk by the value plus one
4812  * specified in this field. The value 0 (divide by 1) is illegal. A value of 1
4813  * indicates divide by 2, 2 divide by 3, etc.
4814  *
4815  * Field Access Macros:
4816  *
4817  */
4818 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */
4819 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB 0
4820 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */
4821 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_MSB 23
4822 /* The width in bits of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */
4823 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_WIDTH 24
4824 /* The mask used to set the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value. */
4825 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK 0x00ffffff
4826 /* The mask used to clear the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value. */
4827 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_CLR_MSK 0xff000000
4828 /* The reset value of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */
4829 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_RESET 0x1
4830 /* Extracts the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK field value from a register. */
4831 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET(value) (((value) & 0x00ffffff) >> 0)
4832 /* Produces a ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value suitable for setting the register. */
4833 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(value) (((value) << 0) & 0x00ffffff)
4834 
4835 #ifndef __ASSEMBLY__
4836 /*
4837  * WARNING: The C register and register group struct declarations are provided for
4838  * convenience and illustrative purposes. They should, however, be used with
4839  * caution as the C language standard provides no guarantees about the alignment or
4840  * atomicity of device memory accesses. The recommended practice for writing
4841  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4842  * alt_write_word() functions.
4843  *
4844  * The struct declaration for register ALT_CLKMGR_PERPLL_GPIODIV.
4845  */
4846 struct ALT_CLKMGR_PERPLL_GPIODIV_s
4847 {
4848  uint32_t gpiodbclk : 24; /* GPIO De-bounce Clock Divider */
4849  uint32_t : 8; /* *UNDEFINED* */
4850 };
4851 
4852 /* The typedef declaration for register ALT_CLKMGR_PERPLL_GPIODIV. */
4853 typedef volatile struct ALT_CLKMGR_PERPLL_GPIODIV_s ALT_CLKMGR_PERPLL_GPIODIV_t;
4854 #endif /* __ASSEMBLY__ */
4855 
4856 /* The byte offset of the ALT_CLKMGR_PERPLL_GPIODIV register from the beginning of the component. */
4857 #define ALT_CLKMGR_PERPLL_GPIODIV_OFST 0x28
4858 
4859 /*
4860  * Register : Flash Clock Source Register - src
4861  *
4862  * Contains fields that select the source clocks for the flash controllers.
4863  *
4864  * Fields are only reset by a cold reset.
4865  *
4866  * Register Layout
4867  *
4868  * Bits | Access | Reset | Description
4869  * :-------|:-------|:------|:-------------------
4870  * [1:0] | RW | 0x1 | SDMMC Clock Source
4871  * [3:2] | RW | 0x1 | NAND Clock Source
4872  * [5:4] | RW | 0x1 | QSPI Clock Source
4873  * [31:6] | ??? | 0x0 | *UNDEFINED*
4874  *
4875  */
4876 /*
4877  * Field : SDMMC Clock Source - sdmmc
4878  *
4879  * Selects the source clock for the SDMMC.
4880  *
4881  * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk.
4882  *
4883  * Field Enumeration Values:
4884  *
4885  * Enum | Value | Description
4886  * :-------------------------------------------------|:------|:----------------------
4887  * ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK | 0x0 | f2s_periph_ref_clk
4888  * ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK | 0x1 | main_nand_sdmmc_clk
4889  * ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK | 0x2 | periph_nand_sdmmc_clk
4890  *
4891  * Field Access Macros:
4892  *
4893  */
4894 /*
4895  * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC
4896  *
4897  * f2s_periph_ref_clk
4898  */
4899 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK 0x0
4900 /*
4901  * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC
4902  *
4903  * main_nand_sdmmc_clk
4904  */
4905 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK 0x1
4906 /*
4907  * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC
4908  *
4909  * periph_nand_sdmmc_clk
4910  */
4911 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK 0x2
4912 
4913 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */
4914 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_LSB 0
4915 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */
4916 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_MSB 1
4917 /* The width in bits of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */
4918 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_WIDTH 2
4919 /* The mask used to set the ALT_CLKMGR_PERPLL_SRC_SDMMC register field value. */
4920 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET_MSK 0x00000003
4921 /* The mask used to clear the ALT_CLKMGR_PERPLL_SRC_SDMMC register field value. */
4922 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_CLR_MSK 0xfffffffc
4923 /* The reset value of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */
4924 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_RESET 0x1
4925 /* Extracts the ALT_CLKMGR_PERPLL_SRC_SDMMC field value from a register. */
4926 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(value) (((value) & 0x00000003) >> 0)
4927 /* Produces a ALT_CLKMGR_PERPLL_SRC_SDMMC register field value suitable for setting the register. */
4928 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(value) (((value) << 0) & 0x00000003)
4929 
4930 /*
4931  * Field : NAND Clock Source - nand
4932  *
4933  * Selects the source clock for the NAND.
4934  *
4935  * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk.
4936  *
4937  * Field Enumeration Values:
4938  *
4939  * Enum | Value | Description
4940  * :------------------------------------------------|:------|:----------------------
4941  * ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK | 0x0 | f2s_periph_ref_clk
4942  * ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK | 0x1 | main_nand_sdmmc_clk
4943  * ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK | 0x2 | periph_nand_sdmmc_clk
4944  *
4945  * Field Access Macros:
4946  *
4947  */
4948 /*
4949  * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND
4950  *
4951  * f2s_periph_ref_clk
4952  */
4953 #define ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK 0x0
4954 /*
4955  * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND
4956  *
4957  * main_nand_sdmmc_clk
4958  */
4959 #define ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK 0x1
4960 /*
4961  * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND
4962  *
4963  * periph_nand_sdmmc_clk
4964  */
4965 #define ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK 0x2
4966 
4967 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */
4968 #define ALT_CLKMGR_PERPLL_SRC_NAND_LSB 2
4969 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */
4970 #define ALT_CLKMGR_PERPLL_SRC_NAND_MSB 3
4971 /* The width in bits of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */
4972 #define ALT_CLKMGR_PERPLL_SRC_NAND_WIDTH 2
4973 /* The mask used to set the ALT_CLKMGR_PERPLL_SRC_NAND register field value. */
4974 #define ALT_CLKMGR_PERPLL_SRC_NAND_SET_MSK 0x0000000c
4975 /* The mask used to clear the ALT_CLKMGR_PERPLL_SRC_NAND register field value. */
4976 #define ALT_CLKMGR_PERPLL_SRC_NAND_CLR_MSK 0xfffffff3
4977 /* The reset value of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */
4978 #define ALT_CLKMGR_PERPLL_SRC_NAND_RESET 0x1
4979 /* Extracts the ALT_CLKMGR_PERPLL_SRC_NAND field value from a register. */
4980 #define ALT_CLKMGR_PERPLL_SRC_NAND_GET(value) (((value) & 0x0000000c) >> 2)
4981 /* Produces a ALT_CLKMGR_PERPLL_SRC_NAND register field value suitable for setting the register. */
4982 #define ALT_CLKMGR_PERPLL_SRC_NAND_SET(value) (((value) << 2) & 0x0000000c)
4983 
4984 /*
4985  * Field : QSPI Clock Source - qspi
4986  *
4987  * Selects the source clock for the QSPI.
4988  *
4989  * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk.
4990  *
4991  * Field Enumeration Values:
4992  *
4993  * Enum | Value | Description
4994  * :------------------------------------------------|:------|:-------------------
4995  * ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK | 0x0 | f2s_periph_ref_clk
4996  * ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK | 0x1 | main_qspi_clk
4997  * ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK | 0x2 | periph_qspi_clk
4998  *
4999  * Field Access Macros:
5000  *
5001  */
5002 /*
5003  * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI
5004  *
5005  * f2s_periph_ref_clk
5006  */
5007 #define ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK 0x0
5008 /*
5009  * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI
5010  *
5011  * main_qspi_clk
5012  */
5013 #define ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK 0x1
5014 /*
5015  * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI
5016  *
5017  * periph_qspi_clk
5018  */
5019 #define ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK 0x2
5020 
5021 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */
5022 #define ALT_CLKMGR_PERPLL_SRC_QSPI_LSB 4
5023 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */
5024 #define ALT_CLKMGR_PERPLL_SRC_QSPI_MSB 5
5025 /* The width in bits of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */
5026 #define ALT_CLKMGR_PERPLL_SRC_QSPI_WIDTH 2
5027 /* The mask used to set the ALT_CLKMGR_PERPLL_SRC_QSPI register field value. */
5028 #define ALT_CLKMGR_PERPLL_SRC_QSPI_SET_MSK 0x00000030
5029 /* The mask used to clear the ALT_CLKMGR_PERPLL_SRC_QSPI register field value. */
5030 #define ALT_CLKMGR_PERPLL_SRC_QSPI_CLR_MSK 0xffffffcf
5031 /* The reset value of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */
5032 #define ALT_CLKMGR_PERPLL_SRC_QSPI_RESET 0x1
5033 /* Extracts the ALT_CLKMGR_PERPLL_SRC_QSPI field value from a register. */
5034 #define ALT_CLKMGR_PERPLL_SRC_QSPI_GET(value) (((value) & 0x00000030) >> 4)
5035 /* Produces a ALT_CLKMGR_PERPLL_SRC_QSPI register field value suitable for setting the register. */
5036 #define ALT_CLKMGR_PERPLL_SRC_QSPI_SET(value) (((value) << 4) & 0x00000030)
5037 
5038 #ifndef __ASSEMBLY__
5039 /*
5040  * WARNING: The C register and register group struct declarations are provided for
5041  * convenience and illustrative purposes. They should, however, be used with
5042  * caution as the C language standard provides no guarantees about the alignment or
5043  * atomicity of device memory accesses. The recommended practice for writing
5044  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5045  * alt_write_word() functions.
5046  *
5047  * The struct declaration for register ALT_CLKMGR_PERPLL_SRC.
5048  */
5049 struct ALT_CLKMGR_PERPLL_SRC_s
5050 {
5051  uint32_t sdmmc : 2; /* SDMMC Clock Source */
5052  uint32_t nand : 2; /* NAND Clock Source */
5053  uint32_t qspi : 2; /* QSPI Clock Source */
5054  uint32_t : 26; /* *UNDEFINED* */
5055 };
5056 
5057 /* The typedef declaration for register ALT_CLKMGR_PERPLL_SRC. */
5058 typedef volatile struct ALT_CLKMGR_PERPLL_SRC_s ALT_CLKMGR_PERPLL_SRC_t;
5059 #endif /* __ASSEMBLY__ */
5060 
5061 /* The byte offset of the ALT_CLKMGR_PERPLL_SRC register from the beginning of the component. */
5062 #define ALT_CLKMGR_PERPLL_SRC_OFST 0x2c
5063 
5064 /*
5065  * Register : Peripheral PLL Output Counter Reset Ack Status Register - stat
5066  *
5067  * Contains Output Clock Counter Reset acknowledge status.
5068  *
5069  * Register Layout
5070  *
5071  * Bits | Access | Reset | Description
5072  * :-------|:-------|:------|:---------------------------------
5073  * [5:0] | R | 0x0 | Output Counter Reset Acknowledge
5074  * [31:6] | ??? | 0x0 | *UNDEFINED*
5075  *
5076  */
5077 /*
5078  * Field : Output Counter Reset Acknowledge - outresetack
5079  *
5080  * These read only bits per PLL output indicate that the PLL has received the
5081  * Output Reset Counter request and has gracefully stopped the respective PLL
5082  * output clock.
5083  *
5084  * For software to change the PLL output counter without producing glitches on the
5085  * respective clock, SW must set the VCO register respective Output Counter Reset
5086  * bit. Software then polls the respective Output Counter Reset Acknowledge bit in
5087  * the Output Counter Reset Ack Status Register. Software then writes the
5088  * appropriate counter register, and then clears the respective VCO register Output
5089  * Counter Reset bit.
5090  *
5091  * The reset value of this bit is applied on a cold reset; warm reset has no affect
5092  * on this bit.
5093  *
5094  * Field Enumeration Values:
5095  *
5096  * Enum | Value | Description
5097  * :-------------------------------------------|:------|:-------------------------------------
5098  * ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_IDLE | 0x0 | Idle
5099  * ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_ACK_RXD | 0x1 | Output Counter Acknowledge received.
5100  *
5101  * Field Access Macros:
5102  *
5103  */
5104 /*
5105  * Enumerated value for register field ALT_CLKMGR_PERPLL_STAT_OUTRSTACK
5106  *
5107  * Idle
5108  */
5109 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_IDLE 0x0
5110 /*
5111  * Enumerated value for register field ALT_CLKMGR_PERPLL_STAT_OUTRSTACK
5112  *
5113  * Output Counter Acknowledge received.
5114  */
5115 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1
5116 
5117 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */
5118 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_LSB 0
5119 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */
5120 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_MSB 5
5121 /* The width in bits of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */
5122 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_WIDTH 6
5123 /* The mask used to set the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field value. */
5124 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f
5125 /* The mask used to clear the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field value. */
5126 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0
5127 /* The reset value of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */
5128 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_RESET 0x0
5129 /* Extracts the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK field value from a register. */
5130 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0)
5131 /* Produces a ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field value suitable for setting the register. */
5132 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f)
5133 
5134 #ifndef __ASSEMBLY__
5135 /*
5136  * WARNING: The C register and register group struct declarations are provided for
5137  * convenience and illustrative purposes. They should, however, be used with
5138  * caution as the C language standard provides no guarantees about the alignment or
5139  * atomicity of device memory accesses. The recommended practice for writing
5140  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5141  * alt_write_word() functions.
5142  *
5143  * The struct declaration for register ALT_CLKMGR_PERPLL_STAT.
5144  */
5145 struct ALT_CLKMGR_PERPLL_STAT_s
5146 {
5147  const uint32_t outresetack : 6; /* Output Counter Reset Acknowledge */
5148  uint32_t : 26; /* *UNDEFINED* */
5149 };
5150 
5151 /* The typedef declaration for register ALT_CLKMGR_PERPLL_STAT. */
5152 typedef volatile struct ALT_CLKMGR_PERPLL_STAT_s ALT_CLKMGR_PERPLL_STAT_t;
5153 #endif /* __ASSEMBLY__ */
5154 
5155 /* The byte offset of the ALT_CLKMGR_PERPLL_STAT register from the beginning of the component. */
5156 #define ALT_CLKMGR_PERPLL_STAT_OFST 0x30
5157 
5158 #ifndef __ASSEMBLY__
5159 /*
5160  * WARNING: The C register and register group struct declarations are provided for
5161  * convenience and illustrative purposes. They should, however, be used with
5162  * caution as the C language standard provides no guarantees about the alignment or
5163  * atomicity of device memory accesses. The recommended practice for writing
5164  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5165  * alt_write_word() functions.
5166  *
5167  * The struct declaration for register group ALT_CLKMGR_PERPLL.
5168  */
5169 struct ALT_CLKMGR_PERPLL_s
5170 {
5171  ALT_CLKMGR_PERPLL_VCO_t vco; /* ALT_CLKMGR_PERPLL_VCO */
5172  ALT_CLKMGR_PERPLL_MISC_t misc; /* ALT_CLKMGR_PERPLL_MISC */
5173  ALT_CLKMGR_PERPLL_EMAC0CLK_t emac0clk; /* ALT_CLKMGR_PERPLL_EMAC0CLK */
5174  ALT_CLKMGR_PERPLL_EMAC1CLK_t emac1clk; /* ALT_CLKMGR_PERPLL_EMAC1CLK */
5175  ALT_CLKMGR_PERPLL_PERQSPICLK_t perqspiclk; /* ALT_CLKMGR_PERPLL_PERQSPICLK */
5176  ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_t pernandsdmmcclk; /* ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK */
5177  ALT_CLKMGR_PERPLL_PERBASECLK_t perbaseclk; /* ALT_CLKMGR_PERPLL_PERBASECLK */
5178  ALT_CLKMGR_PERPLL_S2FUSER1CLK_t s2fuser1clk; /* ALT_CLKMGR_PERPLL_S2FUSER1CLK */
5179  ALT_CLKMGR_PERPLL_EN_t en; /* ALT_CLKMGR_PERPLL_EN */
5180  ALT_CLKMGR_PERPLL_DIV_t div; /* ALT_CLKMGR_PERPLL_DIV */
5181  ALT_CLKMGR_PERPLL_GPIODIV_t gpiodiv; /* ALT_CLKMGR_PERPLL_GPIODIV */
5182  ALT_CLKMGR_PERPLL_SRC_t src; /* ALT_CLKMGR_PERPLL_SRC */
5183  ALT_CLKMGR_PERPLL_STAT_t stat; /* ALT_CLKMGR_PERPLL_STAT */
5184  volatile uint32_t _pad_0x34_0x40[3]; /* *UNDEFINED* */
5185 };
5186 
5187 /* The typedef declaration for register group ALT_CLKMGR_PERPLL. */
5188 typedef volatile struct ALT_CLKMGR_PERPLL_s ALT_CLKMGR_PERPLL_t;
5189 /* The struct declaration for the raw register contents of register group ALT_CLKMGR_PERPLL. */
5190 struct ALT_CLKMGR_PERPLL_raw_s
5191 {
5192  volatile uint32_t vco; /* ALT_CLKMGR_PERPLL_VCO */
5193  volatile uint32_t misc; /* ALT_CLKMGR_PERPLL_MISC */
5194  volatile uint32_t emac0clk; /* ALT_CLKMGR_PERPLL_EMAC0CLK */
5195  volatile uint32_t emac1clk; /* ALT_CLKMGR_PERPLL_EMAC1CLK */
5196  volatile uint32_t perqspiclk; /* ALT_CLKMGR_PERPLL_PERQSPICLK */
5197  volatile uint32_t pernandsdmmcclk; /* ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK */
5198  volatile uint32_t perbaseclk; /* ALT_CLKMGR_PERPLL_PERBASECLK */
5199  volatile uint32_t s2fuser1clk; /* ALT_CLKMGR_PERPLL_S2FUSER1CLK */
5200  volatile uint32_t en; /* ALT_CLKMGR_PERPLL_EN */
5201  volatile uint32_t div; /* ALT_CLKMGR_PERPLL_DIV */
5202  volatile uint32_t gpiodiv; /* ALT_CLKMGR_PERPLL_GPIODIV */
5203  volatile uint32_t src; /* ALT_CLKMGR_PERPLL_SRC */
5204  volatile uint32_t stat; /* ALT_CLKMGR_PERPLL_STAT */
5205  uint32_t _pad_0x34_0x40[3]; /* *UNDEFINED* */
5206 };
5207 
5208 /* The typedef declaration for the raw register contents of register group ALT_CLKMGR_PERPLL. */
5209 typedef volatile struct ALT_CLKMGR_PERPLL_raw_s ALT_CLKMGR_PERPLL_raw_t;
5210 #endif /* __ASSEMBLY__ */
5211 
5212 
5213 /*
5214  * Register Group : SDRAM PLL Group - ALT_CLKMGR_SDRPLL
5215  * SDRAM PLL Group
5216  *
5217  * Contains registers with settings for the SDRAM PLL.
5218  *
5219  */
5220 /*
5221  * Register : SDRAM PLL VCO Control Register - vco
5222  *
5223  * Contains settings that control the SDRAM PLL VCO. The VCO output frequency is
5224  * the input frequency multiplied by the numerator (M+1) and divided by the
5225  * denominator (N+1).
5226  *
5227  * Fields are only reset by a cold reset.
5228  *
5229  * Register Layout
5230  *
5231  * Bits | Access | Reset | Description
5232  * :--------|:-------|:------|:--------------------------------
5233  * [0] | RW | 0x1 | BG PWRDN
5234  * [1] | RW | 0x0 | Enable
5235  * [2] | RW | 0x1 | Power down
5236  * [15:3] | RW | 0x1 | Numerator (M)
5237  * [21:16] | RW | 0x1 | Denominator (N)
5238  * [23:22] | RW | 0x0 | Clock Source
5239  * [24] | RW | 0x0 | SDRAM All Output Counter Reset
5240  * [30:25] | RW | 0x0 | Output Counter Reset
5241  * [31] | RW | 0x1 | External Regulator Input Select
5242  *
5243  */
5244 /*
5245  * Field : BG PWRDN - bgpwrdn
5246  *
5247  * If '1', powers down bandgap. If '0', bandgap is not power down.
5248  *
5249  * Field Access Macros:
5250  *
5251  */
5252 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */
5253 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_LSB 0
5254 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */
5255 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_MSB 0
5256 /* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */
5257 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_WIDTH 1
5258 /* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value. */
5259 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET_MSK 0x00000001
5260 /* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value. */
5261 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe
5262 /* The reset value of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */
5263 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_RESET 0x1
5264 /* Extracts the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN field value from a register. */
5265 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0)
5266 /* Produces a ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value suitable for setting the register. */
5267 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001)
5268 
5269 /*
5270  * Field : Enable - en
5271  *
5272  * If '1', VCO is enabled. If '0', VCO is in reset.
5273  *
5274  * Field Access Macros:
5275  *
5276  */
5277 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */
5278 #define ALT_CLKMGR_SDRPLL_VCO_EN_LSB 1
5279 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */
5280 #define ALT_CLKMGR_SDRPLL_VCO_EN_MSB 1
5281 /* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */
5282 #define ALT_CLKMGR_SDRPLL_VCO_EN_WIDTH 1
5283 /* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_EN register field value. */
5284 #define ALT_CLKMGR_SDRPLL_VCO_EN_SET_MSK 0x00000002
5285 /* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_EN register field value. */
5286 #define ALT_CLKMGR_SDRPLL_VCO_EN_CLR_MSK 0xfffffffd
5287 /* The reset value of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */
5288 #define ALT_CLKMGR_SDRPLL_VCO_EN_RESET 0x0
5289 /* Extracts the ALT_CLKMGR_SDRPLL_VCO_EN field value from a register. */
5290 #define ALT_CLKMGR_SDRPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1)
5291 /* Produces a ALT_CLKMGR_SDRPLL_VCO_EN register field value suitable for setting the register. */
5292 #define ALT_CLKMGR_SDRPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002)
5293 
5294 /*
5295  * Field : Power down - pwrdn
5296  *
5297  * If '1', power down analog circuitry. If '0', analog circuitry not powered down.
5298  *
5299  * Field Access Macros:
5300  *
5301  */
5302 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */
5303 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_LSB 2
5304 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */
5305 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_MSB 2
5306 /* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */
5307 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_WIDTH 1
5308 /* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value. */
5309 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET_MSK 0x00000004
5310 /* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value. */
5311 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_CLR_MSK 0xfffffffb
5312 /* The reset value of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */
5313 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_RESET 0x1
5314 /* Extracts the ALT_CLKMGR_SDRPLL_VCO_PWRDN field value from a register. */
5315 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2)
5316 /* Produces a ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value suitable for setting the register. */
5317 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004)
5318 
5319 /*
5320  * Field : Numerator (M) - numer
5321  *
5322  * Numerator in VCO output frequency equation. For incremental frequency change, if
5323  * the new value lead to less than 20% of the frequency change, this value can be
5324  * changed without resetting the PLL. The Numerator and Denominator can not be
5325  * changed at the same time for incremental frequency changed.
5326  *
5327  * Field Access Macros:
5328  *
5329  */
5330 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */
5331 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_LSB 3
5332 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */
5333 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_MSB 15
5334 /* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */
5335 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_WIDTH 13
5336 /* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_NUMER register field value. */
5337 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_SET_MSK 0x0000fff8
5338 /* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_NUMER register field value. */
5339 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_CLR_MSK 0xffff0007
5340 /* The reset value of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */
5341 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_RESET 0x1
5342 /* Extracts the ALT_CLKMGR_SDRPLL_VCO_NUMER field value from a register. */
5343 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3)
5344 /* Produces a ALT_CLKMGR_SDRPLL_VCO_NUMER register field value suitable for setting the register. */
5345 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8)
5346 
5347 /*
5348  * Field : Denominator (N) - denom
5349  *
5350  * Denominator in VCO output frequency equation. For incremental frequency change,
5351  * if the new value lead to less than 20% of the frequency change, this value can
5352  * be changed without resetting the PLL. The Numerator and Denominator can not be
5353  * changed at the same time for incremental frequency changed.
5354  *
5355  * Field Access Macros:
5356  *
5357  */
5358 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */
5359 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_LSB 16
5360 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */
5361 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_MSB 21
5362 /* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */
5363 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_WIDTH 6
5364 /* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_DENOM register field value. */
5365 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_SET_MSK 0x003f0000
5366 /* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_DENOM register field value. */
5367 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_CLR_MSK 0xffc0ffff
5368 /* The reset value of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */
5369 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_RESET 0x1
5370 /* Extracts the ALT_CLKMGR_SDRPLL_VCO_DENOM field value from a register. */
5371 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16)
5372 /* Produces a ALT_CLKMGR_SDRPLL_VCO_DENOM register field value suitable for setting the register. */
5373 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000)
5374 
5375 /*
5376  * Field : Clock Source - ssrc
5377  *
5378  * Controls the VCO input clock source. The PLL must by bypassed to eosc1_clk
5379  * before changing this field.
5380  *
5381  * Qsys and user documenation refer to f2s_sdram_ref_clk as f2h_sdram_ref_clk.
5382  *
5383  * Field Enumeration Values:
5384  *
5385  * Enum | Value | Description
5386  * :-------------------------------------------|:------|:------------------
5387  * ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1 | 0x0 | eosc1_clk
5388  * ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2 | 0x1 | eosc2_clk
5389  * ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF | 0x2 | f2s_sdram_ref_clk
5390  *
5391  * Field Access Macros:
5392  *
5393  */
5394 /*
5395  * Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC
5396  *
5397  * eosc1_clk
5398  */
5399 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1 0x0
5400 /*
5401  * Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC
5402  *
5403  * eosc2_clk
5404  */
5405 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2 0x1
5406 /*
5407  * Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC
5408  *
5409  * f2s_sdram_ref_clk
5410  */
5411 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF 0x2
5412 
5413 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */
5414 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_LSB 22
5415 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */
5416 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_MSB 23
5417 /* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */
5418 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_WIDTH 2
5419 /* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_SSRC register field value. */
5420 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_SET_MSK 0x00c00000
5421 /* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_SSRC register field value. */
5422 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK 0xff3fffff
5423 /* The reset value of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */
5424 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_RESET 0x0
5425 /* Extracts the ALT_CLKMGR_SDRPLL_VCO_SSRC field value from a register. */
5426 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(value) (((value) & 0x00c00000) >> 22)
5427 /* Produces a ALT_CLKMGR_SDRPLL_VCO_SSRC register field value suitable for setting the register. */
5428 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(value) (((value) << 22) & 0x00c00000)
5429 
5430 /*
5431  * Field : SDRAM All Output Counter Reset - outresetall
5432  *
5433  * Before releasing Bypass, All Output Counter Reset must be set and cleared by
5434  * software for correct clock operation.
5435  *
5436  * If '1', Reset phase multiplexer and output counter state. So that after the
5437  * assertion all the clocks output are start from rising edge align.
5438  *
5439  * If '0', phase multiplexer and output counter state not reset and no change to
5440  * the phase of the clock outputs.
5441  *
5442  * Field Access Macros:
5443  *
5444  */
5445 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */
5446 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_LSB 24
5447 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */
5448 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_MSB 24
5449 /* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */
5450 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_WIDTH 1
5451 /* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value. */
5452 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK 0x01000000
5453 /* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value. */
5454 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff
5455 /* The reset value of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */
5456 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_RESET 0x0
5457 /* Extracts the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL field value from a register. */
5458 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24)
5459 /* Produces a ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value suitable for setting the register. */
5460 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000)
5461 
5462 /*
5463  * Field : Output Counter Reset - outreset
5464  *
5465  * Resets the individual PLL output counter.
5466  *
5467  * For software to change the PLL output counter without producing glitches on the
5468  * respective clock, SW must set the VCO register respective Output Counter Reset
5469  * bit. Software then polls the respective Output Counter Reset Acknowledge bit in
5470  * the Output Counter Reset Ack Status Register. Software then writes the
5471  * appropriate counter register, and then clears the respective VCO register Output
5472  * Counter Reset bit.
5473  *
5474  * LSB 'outreset[0]' corresponds to PLL output clock C0, etc.
5475  *
5476  * If set to '1', reset output divider, no clock output from counter.
5477  *
5478  * If set to '0', counter is not reset.
5479  *
5480  * The reset value of this bit is applied on a cold reset; warm reset has no affect
5481  * on this bit.
5482  *
5483  * Field Access Macros:
5484  *
5485  */
5486 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */
5487 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB 25
5488 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */
5489 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_MSB 30
5490 /* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */
5491 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_WIDTH 6
5492 /* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value. */
5493 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET_MSK 0x7e000000
5494 /* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value. */
5495 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_CLR_MSK 0x81ffffff
5496 /* The reset value of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */
5497 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_RESET 0x0
5498 /* Extracts the ALT_CLKMGR_SDRPLL_VCO_OUTRST field value from a register. */
5499 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25)
5500 /* Produces a ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value suitable for setting the register. */
5501 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000)
5502 
5503 /*
5504  * Field : External Regulator Input Select - regextsel
5505  *
5506  * If set to '1', the external regulator is selected for the PLL.
5507  *
5508  * If set to '0', the internal regulator is slected.
5509  *
5510  * It is strongly recommended to select the external regulator while the PLL is not
5511  * enabled (in reset), and then disable the external regulater once the PLL
5512  * becomes enabled. Software should simulateously update the 'Enable' bit and the
5513  * 'External Regulator Input Select' in the same write access to the VCO register.
5514  * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be
5515  * set, and vice versa.
5516  *
5517  * The reset value of this bit is applied on a cold reset; warm reset has no affect
5518  * on this bit.
5519  *
5520  * Field Access Macros:
5521  *
5522  */
5523 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */
5524 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_LSB 31
5525 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */
5526 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_MSB 31
5527 /* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */
5528 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_WIDTH 1
5529 /* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value. */
5530 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET_MSK 0x80000000
5531 /* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value. */
5532 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff
5533 /* The reset value of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */
5534 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_RESET 0x1
5535 /* Extracts the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL field value from a register. */
5536 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31)
5537 /* Produces a ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value suitable for setting the register. */
5538 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000)
5539 
5540 #ifndef __ASSEMBLY__
5541 /*
5542  * WARNING: The C register and register group struct declarations are provided for
5543  * convenience and illustrative purposes. They should, however, be used with
5544  * caution as the C language standard provides no guarantees about the alignment or
5545  * atomicity of device memory accesses. The recommended practice for writing
5546  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5547  * alt_write_word() functions.
5548  *
5549  * The struct declaration for register ALT_CLKMGR_SDRPLL_VCO.
5550  */
5551 struct ALT_CLKMGR_SDRPLL_VCO_s
5552 {
5553  uint32_t bgpwrdn : 1; /* BG PWRDN */
5554  uint32_t en : 1; /* Enable */
5555  uint32_t pwrdn : 1; /* Power down */
5556  uint32_t numer : 13; /* Numerator (M) */
5557  uint32_t denom : 6; /* Denominator (N) */
5558  uint32_t ssrc : 2; /* Clock Source */
5559  uint32_t outresetall : 1; /* SDRAM All Output Counter Reset */
5560  uint32_t outreset : 6; /* Output Counter Reset */
5561  uint32_t regextsel : 1; /* External Regulator Input Select */
5562 };
5563 
5564 /* The typedef declaration for register ALT_CLKMGR_SDRPLL_VCO. */
5565 typedef volatile struct ALT_CLKMGR_SDRPLL_VCO_s ALT_CLKMGR_SDRPLL_VCO_t;
5566 #endif /* __ASSEMBLY__ */
5567 
5568 /* The byte offset of the ALT_CLKMGR_SDRPLL_VCO register from the beginning of the component. */
5569 #define ALT_CLKMGR_SDRPLL_VCO_OFST 0x0
5570 
5571 /*
5572  * Register : SDRAM PLL VCO Advanced Control Register - ctrl
5573  *
5574  * Contains VCO control signals and other PLL control signals need to be
5575  * controllable through register.
5576  *
5577  * Fields are only reset by a cold reset.
5578  *
5579  * Register Layout
5580  *
5581  * Bits | Access | Reset | Description
5582  * :--------|:-------|:------|:------------------------------
5583  * [0] | RW | 0x0 | Loop Bandwidth Adjust Enabled
5584  * [12:1] | RW | 0x1 | Loop Bandwidth Adjust
5585  * [13] | RW | 0x0 | Fast Locking Enable
5586  * [14] | RW | 0x1 | Saturation Enable
5587  * [31:15] | ??? | 0x0 | *UNDEFINED*
5588  *
5589  */
5590 /*
5591  * Field : Loop Bandwidth Adjust Enabled - bwadjen
5592  *
5593  * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth
5594  * Adjust field.
5595  *
5596  * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2
5597  * value of the VCO Control Register. The M divided by 2 is the upper 12 bits
5598  * (12:1) of the M field in the VCO register.
5599  *
5600  * Field Access Macros:
5601  *
5602  */
5603 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */
5604 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_LSB 0
5605 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */
5606 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_MSB 0
5607 /* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */
5608 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_WIDTH 1
5609 /* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field value. */
5610 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_SET_MSK 0x00000001
5611 /* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field value. */
5612 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_CLR_MSK 0xfffffffe
5613 /* The reset value of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */
5614 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_RESET 0x0
5615 /* Extracts the ALT_CLKMGR_SDRPLL_CTL_BWADJEN field value from a register. */
5616 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_GET(value) (((value) & 0x00000001) >> 0)
5617 /* Produces a ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field value suitable for setting the register. */
5618 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_SET(value) (((value) << 0) & 0x00000001)
5619 
5620 /*
5621  * Field : Loop Bandwidth Adjust - bwadj
5622  *
5623  * Provides Loop Bandwidth Adjust value.
5624  *
5625  * Field Access Macros:
5626  *
5627  */
5628 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */
5629 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_LSB 1
5630 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */
5631 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_MSB 12
5632 /* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */
5633 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_WIDTH 12
5634 /* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field value. */
5635 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_SET_MSK 0x00001ffe
5636 /* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field value. */
5637 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_CLR_MSK 0xffffe001
5638 /* The reset value of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */
5639 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_RESET 0x1
5640 /* Extracts the ALT_CLKMGR_SDRPLL_CTL_BWADJ field value from a register. */
5641 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1)
5642 /* Produces a ALT_CLKMGR_SDRPLL_CTL_BWADJ register field value suitable for setting the register. */
5643 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_SET(value) (((value) << 1) & 0x00001ffe)
5644 
5645 /*
5646  * Field : Fast Locking Enable - fasten
5647  *
5648  * Enables fast locking circuit.
5649  *
5650  * Field Access Macros:
5651  *
5652  */
5653 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */
5654 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_LSB 13
5655 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */
5656 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_MSB 13
5657 /* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */
5658 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_WIDTH 1
5659 /* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field value. */
5660 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_SET_MSK 0x00002000
5661 /* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field value. */
5662 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_CLR_MSK 0xffffdfff
5663 /* The reset value of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */
5664 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_RESET 0x0
5665 /* Extracts the ALT_CLKMGR_SDRPLL_CTL_FASTEN field value from a register. */
5666 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_GET(value) (((value) & 0x00002000) >> 13)
5667 /* Produces a ALT_CLKMGR_SDRPLL_CTL_FASTEN register field value suitable for setting the register. */
5668 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_SET(value) (((value) << 13) & 0x00002000)
5669 
5670 /*
5671  * Field : Saturation Enable - saten
5672  *
5673  * Enables saturation behavior.
5674  *
5675  * Field Access Macros:
5676  *
5677  */
5678 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */
5679 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_LSB 14
5680 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */
5681 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_MSB 14
5682 /* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */
5683 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_WIDTH 1
5684 /* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_SATEN register field value. */
5685 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_SET_MSK 0x00004000
5686 /* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_SATEN register field value. */
5687 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_CLR_MSK 0xffffbfff
5688 /* The reset value of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */
5689 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_RESET 0x1
5690 /* Extracts the ALT_CLKMGR_SDRPLL_CTL_SATEN field value from a register. */
5691 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_GET(value) (((value) & 0x00004000) >> 14)
5692 /* Produces a ALT_CLKMGR_SDRPLL_CTL_SATEN register field value suitable for setting the register. */
5693 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_SET(value) (((value) << 14) & 0x00004000)
5694 
5695 #ifndef __ASSEMBLY__
5696 /*
5697  * WARNING: The C register and register group struct declarations are provided for
5698  * convenience and illustrative purposes. They should, however, be used with
5699  * caution as the C language standard provides no guarantees about the alignment or
5700  * atomicity of device memory accesses. The recommended practice for writing
5701  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5702  * alt_write_word() functions.
5703  *
5704  * The struct declaration for register ALT_CLKMGR_SDRPLL_CTL.
5705  */
5706 struct ALT_CLKMGR_SDRPLL_CTL_s
5707 {
5708  uint32_t bwadjen : 1; /* Loop Bandwidth Adjust Enabled */
5709  uint32_t bwadj : 12; /* Loop Bandwidth Adjust */
5710  uint32_t fasten : 1; /* Fast Locking Enable */
5711  uint32_t saten : 1; /* Saturation Enable */
5712  uint32_t : 17; /* *UNDEFINED* */
5713 };
5714 
5715 /* The typedef declaration for register ALT_CLKMGR_SDRPLL_CTL. */
5716 typedef volatile struct ALT_CLKMGR_SDRPLL_CTL_s ALT_CLKMGR_SDRPLL_CTL_t;
5717 #endif /* __ASSEMBLY__ */
5718 
5719 /* The byte offset of the ALT_CLKMGR_SDRPLL_CTL register from the beginning of the component. */
5720 #define ALT_CLKMGR_SDRPLL_CTL_OFST 0x4
5721 
5722 /*
5723  * Register : SDRAM PLL C0 Control Register for Clock ddr_dqs_clk - ddrdqsclk
5724  *
5725  * Contains settings that control clock ddr_dqs_clk generated from the C0 output of
5726  * the SDRAM PLL.
5727  *
5728  * Fields are only reset by a cold reset.
5729  *
5730  * Register Layout
5731  *
5732  * Bits | Access | Reset | Description
5733  * :--------|:-------|:------|:------------
5734  * [8:0] | RW | 0x1 | Counter
5735  * [20:9] | RW | 0x0 | Phase Shift
5736  * [31:21] | ??? | 0x0 | *UNDEFINED*
5737  *
5738  */
5739 /*
5740  * Field : Counter - cnt
5741  *
5742  * Divides the VCO frequency by the value+1 in this field.
5743  *
5744  * Field Access Macros:
5745  *
5746  */
5747 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */
5748 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB 0
5749 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */
5750 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_MSB 8
5751 /* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */
5752 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_WIDTH 9
5753 /* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field value. */
5754 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK 0x000001ff
5755 /* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field value. */
5756 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_CLR_MSK 0xfffffe00
5757 /* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */
5758 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_RESET 0x1
5759 /* Extracts the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT field value from a register. */
5760 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
5761 /* Produces a ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field value suitable for setting the register. */
5762 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
5763 
5764 /*
5765  * Field : Phase Shift - phase
5766  *
5767  * Increment the phase of the VCO output by the value in this field multiplied by
5768  * 45 degrees. The accumulated phase shift is the total shifted amount since the
5769  * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco
5770  * control register. In order to guarantee the phase shift to a known value, 'SDRAM
5771  * clocks output phase align' bit should be asserted before programming this field.
5772  *
5773  * This field is only writeable by SW when it is zero. HW updates this field in
5774  * real time as the phase adjustment is being made. SW may poll this field
5775  * waiting for zero indicating the phase adjustment has completed by HW.
5776  *
5777  * Field Access Macros:
5778  *
5779  */
5780 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */
5781 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_LSB 9
5782 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */
5783 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_MSB 20
5784 /* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */
5785 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_WIDTH 12
5786 /* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field value. */
5787 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET_MSK 0x001ffe00
5788 /* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field value. */
5789 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_CLR_MSK 0xffe001ff
5790 /* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */
5791 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_RESET 0x0
5792 /* Extracts the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE field value from a register. */
5793 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9)
5794 /* Produces a ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field value suitable for setting the register. */
5795 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00)
5796 
5797 #ifndef __ASSEMBLY__
5798 /*
5799  * WARNING: The C register and register group struct declarations are provided for
5800  * convenience and illustrative purposes. They should, however, be used with
5801  * caution as the C language standard provides no guarantees about the alignment or
5802  * atomicity of device memory accesses. The recommended practice for writing
5803  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5804  * alt_write_word() functions.
5805  *
5806  * The struct declaration for register ALT_CLKMGR_SDRPLL_DDRDQSCLK.
5807  */
5808 struct ALT_CLKMGR_SDRPLL_DDRDQSCLK_s
5809 {
5810  uint32_t cnt : 9; /* Counter */
5811  uint32_t phase : 12; /* Phase Shift */
5812  uint32_t : 11; /* *UNDEFINED* */
5813 };
5814 
5815 /* The typedef declaration for register ALT_CLKMGR_SDRPLL_DDRDQSCLK. */
5816 typedef volatile struct ALT_CLKMGR_SDRPLL_DDRDQSCLK_s ALT_CLKMGR_SDRPLL_DDRDQSCLK_t;
5817 #endif /* __ASSEMBLY__ */
5818 
5819 /* The byte offset of the ALT_CLKMGR_SDRPLL_DDRDQSCLK register from the beginning of the component. */
5820 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_OFST 0x8
5821 
5822 /*
5823  * Register : SDRAM PLL C1 Control Register for Clock ddr_2x_dqs_clk - ddr2xdqsclk
5824  *
5825  * Contains settings that control clock ddr_2x_dqs_clk generated from the C1 output
5826  * of the SDRAM PLL.
5827  *
5828  * Fields are only reset by a cold reset.
5829  *
5830  * Register Layout
5831  *
5832  * Bits | Access | Reset | Description
5833  * :--------|:-------|:------|:------------
5834  * [8:0] | RW | 0x1 | Counter
5835  * [20:9] | RW | 0x0 | Phase Shift
5836  * [31:21] | ??? | 0x0 | *UNDEFINED*
5837  *
5838  */
5839 /*
5840  * Field : Counter - cnt
5841  *
5842  * Divides the VCO frequency by the value+1 in this field.
5843  *
5844  * Field Access Macros:
5845  *
5846  */
5847 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */
5848 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_LSB 0
5849 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */
5850 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_MSB 8
5851 /* The width in bits of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */
5852 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_WIDTH 9
5853 /* The mask used to set the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field value. */
5854 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK 0x000001ff
5855 /* The mask used to clear the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field value. */
5856 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_CLR_MSK 0xfffffe00
5857 /* The reset value of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */
5858 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_RESET 0x1
5859 /* Extracts the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT field value from a register. */
5860 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
5861 /* Produces a ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field value suitable for setting the register. */
5862 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
5863 
5864 /*
5865  * Field : Phase Shift - phase
5866  *
5867  * Increment the phase of the VCO output by the value in this field multiplied by
5868  * 45 degrees. The accumulated phase shift is the total shifted amount since the
5869  * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco
5870  * control register. In order to guarantee the phase shift to a known value, 'SDRAM
5871  * clocks output phase align' bit should be asserted before programming this field.
5872  *
5873  * This field is only writeable by SW when it is zero. HW updates this field in
5874  * real time as the phase adjustment is being made. SW may poll this field
5875  * waiting for zero indicating the phase adjustment has completed by HW.
5876  *
5877  * Field Access Macros:
5878  *
5879  */
5880 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */
5881 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_LSB 9
5882 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */
5883 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_MSB 20
5884 /* The width in bits of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */
5885 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_WIDTH 12
5886 /* The mask used to set the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field value. */
5887 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET_MSK 0x001ffe00
5888 /* The mask used to clear the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field value. */
5889 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_CLR_MSK 0xffe001ff
5890 /* The reset value of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */
5891 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_RESET 0x0
5892 /* Extracts the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE field value from a register. */
5893 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9)
5894 /* Produces a ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field value suitable for setting the register. */
5895 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00)
5896 
5897 #ifndef __ASSEMBLY__
5898 /*
5899  * WARNING: The C register and register group struct declarations are provided for
5900  * convenience and illustrative purposes. They should, however, be used with
5901  * caution as the C language standard provides no guarantees about the alignment or
5902  * atomicity of device memory accesses. The recommended practice for writing
5903  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5904  * alt_write_word() functions.
5905  *
5906  * The struct declaration for register ALT_CLKMGR_SDRPLL_DDR2XDQSCLK.
5907  */
5908 struct ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_s
5909 {
5910  uint32_t cnt : 9; /* Counter */
5911  uint32_t phase : 12; /* Phase Shift */
5912  uint32_t : 11; /* *UNDEFINED* */
5913 };
5914 
5915 /* The typedef declaration for register ALT_CLKMGR_SDRPLL_DDR2XDQSCLK. */
5916 typedef volatile struct ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_s ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_t;
5917 #endif /* __ASSEMBLY__ */
5918 
5919 /* The byte offset of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK register from the beginning of the component. */
5920 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_OFST 0xc
5921 
5922 /*
5923  * Register : SDRAM PLL C2 Control Register for Clock ddr_dq_clk - ddrdqclk
5924  *
5925  * Contains settings that control clock ddr_dq_clk generated from the C2 output of
5926  * the SDRAM PLL.
5927  *
5928  * Fields are only reset by a cold reset.
5929  *
5930  * Register Layout
5931  *
5932  * Bits | Access | Reset | Description
5933  * :--------|:-------|:------|:------------
5934  * [8:0] | RW | 0x1 | Counter
5935  * [20:9] | RW | 0x0 | Phase Shift
5936  * [31:21] | ??? | 0x0 | *UNDEFINED*
5937  *
5938  */
5939 /*
5940  * Field : Counter - cnt
5941  *
5942  * Divides the VCO frequency by the value+1 in this field.
5943  *
5944  * Field Access Macros:
5945  *
5946  */
5947 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */
5948 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_LSB 0
5949 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */
5950 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_MSB 8
5951 /* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */
5952 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_WIDTH 9
5953 /* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value. */
5954 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK 0x000001ff
5955 /* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value. */
5956 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_CLR_MSK 0xfffffe00
5957 /* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */
5958 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_RESET 0x1
5959 /* Extracts the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT field value from a register. */
5960 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
5961 /* Produces a ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value suitable for setting the register. */
5962 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
5963 
5964 /*
5965  * Field : Phase Shift - phase
5966  *
5967  * Increment the phase of the VCO output by the value in this field multiplied by
5968  * 45 degrees. The accumulated phase shift is the total shifted amount since the
5969  * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco
5970  * control register. In order to guarantee the phase shift to a known value, 'SDRAM
5971  * clocks output phase align' bit should be asserted before programming this field.
5972  *
5973  * This field is only writeable by SW when it is zero. HW updates this field in
5974  * real time as the phase adjustment is being made. SW may poll this field
5975  * waiting for zero indicating the phase adjustment has completed by HW.
5976  *
5977  * Field Access Macros:
5978  *
5979  */
5980 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */
5981 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_LSB 9
5982 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */
5983 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_MSB 20
5984 /* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */
5985 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_WIDTH 12
5986 /* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value. */
5987 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET_MSK 0x001ffe00
5988 /* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value. */
5989 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_CLR_MSK 0xffe001ff
5990 /* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */
5991 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_RESET 0x0
5992 /* Extracts the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE field value from a register. */
5993 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9)
5994 /* Produces a ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value suitable for setting the register. */
5995 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00)
5996 
5997 #ifndef __ASSEMBLY__
5998 /*
5999  * WARNING: The C register and register group struct declarations are provided for
6000  * convenience and illustrative purposes. They should, however, be used with
6001  * caution as the C language standard provides no guarantees about the alignment or
6002  * atomicity of device memory accesses. The recommended practice for writing
6003  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6004  * alt_write_word() functions.
6005  *
6006  * The struct declaration for register ALT_CLKMGR_SDRPLL_DDRDQCLK.
6007  */
6008 struct ALT_CLKMGR_SDRPLL_DDRDQCLK_s
6009 {
6010  uint32_t cnt : 9; /* Counter */
6011  uint32_t phase : 12; /* Phase Shift */
6012  uint32_t : 11; /* *UNDEFINED* */
6013 };
6014 
6015 /* The typedef declaration for register ALT_CLKMGR_SDRPLL_DDRDQCLK. */
6016 typedef volatile struct ALT_CLKMGR_SDRPLL_DDRDQCLK_s ALT_CLKMGR_SDRPLL_DDRDQCLK_t;
6017 #endif /* __ASSEMBLY__ */
6018 
6019 /* The byte offset of the ALT_CLKMGR_SDRPLL_DDRDQCLK register from the beginning of the component. */
6020 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_OFST 0x10
6021 
6022 /*
6023  * Register : SDRAM PLL C5 Control Register for Clock s2f_user2_clk - s2fuser2clk
6024  *
6025  * Contains settings that control clock s2f_user2_clk generated from the C5 output
6026  * of the SDRAM PLL.
6027  *
6028  * Qsys and user documenation refer to s2f_user2_clk as h2f_user2_clk
6029  *
6030  * Fields are only reset by a cold reset.
6031  *
6032  * Register Layout
6033  *
6034  * Bits | Access | Reset | Description
6035  * :--------|:-------|:------|:------------
6036  * [8:0] | RW | 0x1 | Counter
6037  * [20:9] | RW | 0x0 | Phase Shift
6038  * [31:21] | ??? | 0x0 | *UNDEFINED*
6039  *
6040  */
6041 /*
6042  * Field : Counter - cnt
6043  *
6044  * Divides the VCO frequency by the value+1 in this field.
6045  *
6046  * Field Access Macros:
6047  *
6048  */
6049 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */
6050 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_LSB 0
6051 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */
6052 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_MSB 8
6053 /* The width in bits of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */
6054 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_WIDTH 9
6055 /* The mask used to set the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field value. */
6056 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK 0x000001ff
6057 /* The mask used to clear the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field value. */
6058 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_CLR_MSK 0xfffffe00
6059 /* The reset value of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */
6060 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_RESET 0x1
6061 /* Extracts the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT field value from a register. */
6062 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
6063 /* Produces a ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field value suitable for setting the register. */
6064 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
6065 
6066 /*
6067  * Field : Phase Shift - phase
6068  *
6069  * Increment the phase of the VCO output by the value in this field multiplied by
6070  * 45 degrees. The accumulated phase shift is the total shifted amount since the
6071  * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco
6072  * control register. In order to guarantee the phase shift to a known value, 'SDRAM
6073  * clocks output phase align' bit should be asserted before programming this field.
6074  *
6075  * This field is only writeable by SW when it is zero. HW updates this field in
6076  * real time as the phase adjustment is being made. SW may poll this field
6077  * waiting for zero indicating the phase adjustment has completed by HW.
6078  *
6079  * Field Access Macros:
6080  *
6081  */
6082 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */
6083 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_LSB 9
6084 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */
6085 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_MSB 20
6086 /* The width in bits of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */
6087 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_WIDTH 12
6088 /* The mask used to set the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field value. */
6089 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET_MSK 0x001ffe00
6090 /* The mask used to clear the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field value. */
6091 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_CLR_MSK 0xffe001ff
6092 /* The reset value of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */
6093 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_RESET 0x0
6094 /* Extracts the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE field value from a register. */
6095 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9)
6096 /* Produces a ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field value suitable for setting the register. */
6097 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00)
6098 
6099 #ifndef __ASSEMBLY__
6100 /*
6101  * WARNING: The C register and register group struct declarations are provided for
6102  * convenience and illustrative purposes. They should, however, be used with
6103  * caution as the C language standard provides no guarantees about the alignment or
6104  * atomicity of device memory accesses. The recommended practice for writing
6105  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6106  * alt_write_word() functions.
6107  *
6108  * The struct declaration for register ALT_CLKMGR_SDRPLL_S2FUSER2CLK.
6109  */
6110 struct ALT_CLKMGR_SDRPLL_S2FUSER2CLK_s
6111 {
6112  uint32_t cnt : 9; /* Counter */
6113  uint32_t phase : 12; /* Phase Shift */
6114  uint32_t : 11; /* *UNDEFINED* */
6115 };
6116 
6117 /* The typedef declaration for register ALT_CLKMGR_SDRPLL_S2FUSER2CLK. */
6118 typedef volatile struct ALT_CLKMGR_SDRPLL_S2FUSER2CLK_s ALT_CLKMGR_SDRPLL_S2FUSER2CLK_t;
6119 #endif /* __ASSEMBLY__ */
6120 
6121 /* The byte offset of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK register from the beginning of the component. */
6122 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_OFST 0x14
6123 
6124 /*
6125  * Register : Enable Register - en
6126  *
6127  * Contains fields that control the SDRAM Clock Group enables generated from the
6128  * SDRAM PLL clock outputs.
6129  *
6130  * 1: The clock is enabled.
6131  *
6132  * 0: The clock is disabled.
6133  *
6134  * Fields are only reset by a cold reset.
6135  *
6136  * Register Layout
6137  *
6138  * Bits | Access | Reset | Description
6139  * :-------|:-------|:------|:----------------------
6140  * [0] | RW | 0x1 | ddr_dqs_clk Enable
6141  * [1] | RW | 0x1 | ddr_2x_dqs_clk Enable
6142  * [2] | RW | 0x1 | ddr_dq_clk Enable
6143  * [3] | RW | 0x1 | s2f_user2_clk Enable
6144  * [31:4] | ??? | 0x0 | *UNDEFINED*
6145  *
6146  */
6147 /*
6148  * Field : ddr_dqs_clk Enable - ddrdqsclk
6149  *
6150  * Enables clock ddr_dqs_clk output
6151  *
6152  * Field Access Macros:
6153  *
6154  */
6155 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */
6156 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_LSB 0
6157 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */
6158 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_MSB 0
6159 /* The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */
6160 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_WIDTH 1
6161 /* The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value. */
6162 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK 0x00000001
6163 /* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value. */
6164 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_CLR_MSK 0xfffffffe
6165 /* The reset value of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */
6166 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_RESET 0x1
6167 /* Extracts the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK field value from a register. */
6168 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_GET(value) (((value) & 0x00000001) >> 0)
6169 /* Produces a ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value suitable for setting the register. */
6170 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET(value) (((value) << 0) & 0x00000001)
6171 
6172 /*
6173  * Field : ddr_2x_dqs_clk Enable - ddr2xdqsclk
6174  *
6175  * Enables clock ddr_2x_dqs_clk output
6176  *
6177  * Field Access Macros:
6178  *
6179  */
6180 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */
6181 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_LSB 1
6182 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */
6183 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_MSB 1
6184 /* The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */
6185 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_WIDTH 1
6186 /* The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value. */
6187 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK 0x00000002
6188 /* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value. */
6189 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_CLR_MSK 0xfffffffd
6190 /* The reset value of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */
6191 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_RESET 0x1
6192 /* Extracts the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK field value from a register. */
6193 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_GET(value) (((value) & 0x00000002) >> 1)
6194 /* Produces a ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value suitable for setting the register. */
6195 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET(value) (((value) << 1) & 0x00000002)
6196 
6197 /*
6198  * Field : ddr_dq_clk Enable - ddrdqclk
6199  *
6200  * Enables clock ddr_dq_clk output
6201  *
6202  * Field Access Macros:
6203  *
6204  */
6205 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */
6206 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_LSB 2
6207 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */
6208 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_MSB 2
6209 /* The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */
6210 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_WIDTH 1
6211 /* The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value. */
6212 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK 0x00000004
6213 /* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value. */
6214 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_CLR_MSK 0xfffffffb
6215 /* The reset value of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */
6216 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_RESET 0x1
6217 /* Extracts the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK field value from a register. */
6218 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_GET(value) (((value) & 0x00000004) >> 2)
6219 /* Produces a ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value suitable for setting the register. */
6220 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET(value) (((value) << 2) & 0x00000004)
6221 
6222 /*
6223  * Field : s2f_user2_clk Enable - s2fuser2clk
6224  *
6225  * Enables clock s2f_user2_clk output.
6226  *
6227  * Qsys and user documenation refer to s2f_user2_clk as h2f_user2_clk.
6228  *
6229  * Field Access Macros:
6230  *
6231  */
6232 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */
6233 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_LSB 3
6234 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */
6235 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_MSB 3
6236 /* The width in bits of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */
6237 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_WIDTH 1
6238 /* The mask used to set the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value. */
6239 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK 0x00000008
6240 /* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value. */
6241 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_CLR_MSK 0xfffffff7
6242 /* The reset value of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */
6243 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_RESET 0x1
6244 /* Extracts the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK field value from a register. */
6245 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_GET(value) (((value) & 0x00000008) >> 3)
6246 /* Produces a ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value suitable for setting the register. */
6247 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET(value) (((value) << 3) & 0x00000008)
6248 
6249 #ifndef __ASSEMBLY__
6250 /*
6251  * WARNING: The C register and register group struct declarations are provided for
6252  * convenience and illustrative purposes. They should, however, be used with
6253  * caution as the C language standard provides no guarantees about the alignment or
6254  * atomicity of device memory accesses. The recommended practice for writing
6255  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6256  * alt_write_word() functions.
6257  *
6258  * The struct declaration for register ALT_CLKMGR_SDRPLL_EN.
6259  */
6260 struct ALT_CLKMGR_SDRPLL_EN_s
6261 {
6262  uint32_t ddrdqsclk : 1; /* ddr_dqs_clk Enable */
6263  uint32_t ddr2xdqsclk : 1; /* ddr_2x_dqs_clk Enable */
6264  uint32_t ddrdqclk : 1; /* ddr_dq_clk Enable */
6265  uint32_t s2fuser2clk : 1; /* s2f_user2_clk Enable */
6266  uint32_t : 28; /* *UNDEFINED* */
6267 };
6268 
6269 /* The typedef declaration for register ALT_CLKMGR_SDRPLL_EN. */
6270 typedef volatile struct ALT_CLKMGR_SDRPLL_EN_s ALT_CLKMGR_SDRPLL_EN_t;
6271 #endif /* __ASSEMBLY__ */
6272 
6273 /* The byte offset of the ALT_CLKMGR_SDRPLL_EN register from the beginning of the component. */
6274 #define ALT_CLKMGR_SDRPLL_EN_OFST 0x18
6275 
6276 /*
6277  * Register : SDRAM PLL Output Counter Reset Ack Status Register - stat
6278  *
6279  * Contains Output Clock Counter Reset acknowledge status.
6280  *
6281  * Register Layout
6282  *
6283  * Bits | Access | Reset | Description
6284  * :-------|:-------|:------|:---------------------------------
6285  * [5:0] | R | 0x0 | Output Counter Reset Acknowledge
6286  * [31:6] | ??? | 0x0 | *UNDEFINED*
6287  *
6288  */
6289 /*
6290  * Field : Output Counter Reset Acknowledge - outresetack
6291  *
6292  * These read only bits per PLL output indicate that the PLL has received the
6293  * Output Reset Counter request and has gracefully stopped the respective PLL
6294  * output clock.
6295  *
6296  * For software to change the PLL output counter without producing glitches on the
6297  * respective clock, SW must set the VCO register respective Output Counter Reset
6298  * bit. Software then polls the respective Output Counter Reset Acknowledge bit in
6299  * the Output Counter Reset Ack Status Register. Software then writes the
6300  * appropriate counter register, and then clears the respective VCO register Output
6301  * Counter Reset bit.
6302  *
6303  * The reset value of this bit is applied on a cold reset; warm reset has no affect
6304  * on this bit.
6305  *
6306  * Field Enumeration Values:
6307  *
6308  * Enum | Value | Description
6309  * :-------------------------------------------|:------|:-------------------------------------
6310  * ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_IDLE | 0x0 | Idle
6311  * ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_ACK_RXD | 0x1 | Output Counter Acknowledge received.
6312  *
6313  * Field Access Macros:
6314  *
6315  */
6316 /*
6317  * Enumerated value for register field ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK
6318  *
6319  * Idle
6320  */
6321 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_IDLE 0x0
6322 /*
6323  * Enumerated value for register field ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK
6324  *
6325  * Output Counter Acknowledge received.
6326  */
6327 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1
6328 
6329 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */
6330 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_LSB 0
6331 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */
6332 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_MSB 5
6333 /* The width in bits of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */
6334 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_WIDTH 6
6335 /* The mask used to set the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field value. */
6336 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f
6337 /* The mask used to clear the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field value. */
6338 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0
6339 /* The reset value of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */
6340 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_RESET 0x0
6341 /* Extracts the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK field value from a register. */
6342 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0)
6343 /* Produces a ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field value suitable for setting the register. */
6344 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f)
6345 
6346 #ifndef __ASSEMBLY__
6347 /*
6348  * WARNING: The C register and register group struct declarations are provided for
6349  * convenience and illustrative purposes. They should, however, be used with
6350  * caution as the C language standard provides no guarantees about the alignment or
6351  * atomicity of device memory accesses. The recommended practice for writing
6352  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6353  * alt_write_word() functions.
6354  *
6355  * The struct declaration for register ALT_CLKMGR_SDRPLL_STAT.
6356  */
6357 struct ALT_CLKMGR_SDRPLL_STAT_s
6358 {
6359  const uint32_t outresetack : 6; /* Output Counter Reset Acknowledge */
6360  uint32_t : 26; /* *UNDEFINED* */
6361 };
6362 
6363 /* The typedef declaration for register ALT_CLKMGR_SDRPLL_STAT. */
6364 typedef volatile struct ALT_CLKMGR_SDRPLL_STAT_s ALT_CLKMGR_SDRPLL_STAT_t;
6365 #endif /* __ASSEMBLY__ */
6366 
6367 /* The byte offset of the ALT_CLKMGR_SDRPLL_STAT register from the beginning of the component. */
6368 #define ALT_CLKMGR_SDRPLL_STAT_OFST 0x1c
6369 
6370 #ifndef __ASSEMBLY__
6371 /*
6372  * WARNING: The C register and register group struct declarations are provided for
6373  * convenience and illustrative purposes. They should, however, be used with
6374  * caution as the C language standard provides no guarantees about the alignment or
6375  * atomicity of device memory accesses. The recommended practice for writing
6376  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6377  * alt_write_word() functions.
6378  *
6379  * The struct declaration for register group ALT_CLKMGR_SDRPLL.
6380  */
6381 struct ALT_CLKMGR_SDRPLL_s
6382 {
6383  ALT_CLKMGR_SDRPLL_VCO_t vco; /* ALT_CLKMGR_SDRPLL_VCO */
6384  ALT_CLKMGR_SDRPLL_CTL_t ctrl; /* ALT_CLKMGR_SDRPLL_CTL */
6385  ALT_CLKMGR_SDRPLL_DDRDQSCLK_t ddrdqsclk; /* ALT_CLKMGR_SDRPLL_DDRDQSCLK */
6386  ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_t ddr2xdqsclk; /* ALT_CLKMGR_SDRPLL_DDR2XDQSCLK */
6387  ALT_CLKMGR_SDRPLL_DDRDQCLK_t ddrdqclk; /* ALT_CLKMGR_SDRPLL_DDRDQCLK */
6388  ALT_CLKMGR_SDRPLL_S2FUSER2CLK_t s2fuser2clk; /* ALT_CLKMGR_SDRPLL_S2FUSER2CLK */
6389  ALT_CLKMGR_SDRPLL_EN_t en; /* ALT_CLKMGR_SDRPLL_EN */
6390  ALT_CLKMGR_SDRPLL_STAT_t stat; /* ALT_CLKMGR_SDRPLL_STAT */
6391 };
6392 
6393 /* The typedef declaration for register group ALT_CLKMGR_SDRPLL. */
6394 typedef volatile struct ALT_CLKMGR_SDRPLL_s ALT_CLKMGR_SDRPLL_t;
6395 /* The struct declaration for the raw register contents of register group ALT_CLKMGR_SDRPLL. */
6396 struct ALT_CLKMGR_SDRPLL_raw_s
6397 {
6398  volatile uint32_t vco; /* ALT_CLKMGR_SDRPLL_VCO */
6399  volatile uint32_t ctrl; /* ALT_CLKMGR_SDRPLL_CTL */
6400  volatile uint32_t ddrdqsclk; /* ALT_CLKMGR_SDRPLL_DDRDQSCLK */
6401  volatile uint32_t ddr2xdqsclk; /* ALT_CLKMGR_SDRPLL_DDR2XDQSCLK */
6402  volatile uint32_t ddrdqclk; /* ALT_CLKMGR_SDRPLL_DDRDQCLK */
6403  volatile uint32_t s2fuser2clk; /* ALT_CLKMGR_SDRPLL_S2FUSER2CLK */
6404  volatile uint32_t en; /* ALT_CLKMGR_SDRPLL_EN */
6405  volatile uint32_t stat; /* ALT_CLKMGR_SDRPLL_STAT */
6406 };
6407 
6408 /* The typedef declaration for the raw register contents of register group ALT_CLKMGR_SDRPLL. */
6409 typedef volatile struct ALT_CLKMGR_SDRPLL_raw_s ALT_CLKMGR_SDRPLL_raw_t;
6410 #endif /* __ASSEMBLY__ */
6411 
6412 
6413 /*
6414  * Register Group : Miscellaneous settings registers Group - ALT_CLKMGR_MISCGRP
6415  * Miscellaneous settings registers Group
6416  *
6417  * Contains registers with miscellaneous settings.
6418  *
6419  */
6420 /*
6421  * Register : Main PLL C0 Control Register for Clock mpu_clk - mpuclk
6422  *
6423  * Contains settings that control clock mpu_clk generated from the C0 output of the
6424  * Main PLL.
6425  *
6426  * Only reset by a cold reset.
6427  *
6428  * Register Layout
6429  *
6430  * Bits | Access | Reset | Description
6431  * :-------|:-------|:------|:------------
6432  * [8:0] | RW | 0x1 | Counter
6433  * [31:9] | ??? | 0x0 | *UNDEFINED*
6434  *
6435  */
6436 /*
6437  * Field : Counter - cnt
6438  *
6439  * Divides the VCO frequency by the value+1 in this field.
6440  *
6441  * Field Access Macros:
6442  *
6443  */
6444 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MISC_MPUCLK_CNT register field. */
6445 #define ALT_CLKMGR_MISC_MPUCLK_CNT_LSB 0
6446 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MISC_MPUCLK_CNT register field. */
6447 #define ALT_CLKMGR_MISC_MPUCLK_CNT_MSB 8
6448 /* The width in bits of the ALT_CLKMGR_MISC_MPUCLK_CNT register field. */
6449 #define ALT_CLKMGR_MISC_MPUCLK_CNT_WIDTH 9
6450 /* The mask used to set the ALT_CLKMGR_MISC_MPUCLK_CNT register field value. */
6451 #define ALT_CLKMGR_MISC_MPUCLK_CNT_SET_MSK 0x000001ff
6452 /* The mask used to clear the ALT_CLKMGR_MISC_MPUCLK_CNT register field value. */
6453 #define ALT_CLKMGR_MISC_MPUCLK_CNT_CLR_MSK 0xfffffe00
6454 /* The reset value of the ALT_CLKMGR_MISC_MPUCLK_CNT register field. */
6455 #define ALT_CLKMGR_MISC_MPUCLK_CNT_RESET 0x1
6456 /* Extracts the ALT_CLKMGR_MISC_MPUCLK_CNT field value from a register. */
6457 #define ALT_CLKMGR_MISC_MPUCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
6458 /* Produces a ALT_CLKMGR_MISC_MPUCLK_CNT register field value suitable for setting the register. */
6459 #define ALT_CLKMGR_MISC_MPUCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
6460 
6461 #ifndef __ASSEMBLY__
6462 /*
6463  * WARNING: The C register and register group struct declarations are provided for
6464  * convenience and illustrative purposes. They should, however, be used with
6465  * caution as the C language standard provides no guarantees about the alignment or
6466  * atomicity of device memory accesses. The recommended practice for writing
6467  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6468  * alt_write_word() functions.
6469  *
6470  * The struct declaration for register ALT_CLKMGR_MISC_MPUCLK.
6471  */
6472 struct ALT_CLKMGR_MISC_MPUCLK_s
6473 {
6474  uint32_t cnt : 9; /* Counter */
6475  uint32_t : 23; /* *UNDEFINED* */
6476 };
6477 
6478 /* The typedef declaration for register ALT_CLKMGR_MISC_MPUCLK. */
6479 typedef volatile struct ALT_CLKMGR_MISC_MPUCLK_s ALT_CLKMGR_MISC_MPUCLK_t;
6480 #endif /* __ASSEMBLY__ */
6481 
6482 /* The byte offset of the ALT_CLKMGR_MISC_MPUCLK register from the beginning of the component. */
6483 #define ALT_CLKMGR_MISC_MPUCLK_OFST 0x0
6484 
6485 /*
6486  * Register : Main PLL C1 Control Register for Clock main_clk - mainclk
6487  *
6488  * Contains settings that control clock main_clk generated from the C1 output of
6489  * the Main PLL.
6490  *
6491  * Only reset by a cold reset.
6492  *
6493  * Register Layout
6494  *
6495  * Bits | Access | Reset | Description
6496  * :-------|:-------|:------|:------------
6497  * [8:0] | RW | 0x3 | Counter
6498  * [31:9] | ??? | 0x0 | *UNDEFINED*
6499  *
6500  */
6501 /*
6502  * Field : Counter - cnt
6503  *
6504  * Divides the VCO frequency by the value+1 in this field.
6505  *
6506  * Field Access Macros:
6507  *
6508  */
6509 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MISC_MAINCLK_CNT register field. */
6510 #define ALT_CLKMGR_MISC_MAINCLK_CNT_LSB 0
6511 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MISC_MAINCLK_CNT register field. */
6512 #define ALT_CLKMGR_MISC_MAINCLK_CNT_MSB 8
6513 /* The width in bits of the ALT_CLKMGR_MISC_MAINCLK_CNT register field. */
6514 #define ALT_CLKMGR_MISC_MAINCLK_CNT_WIDTH 9
6515 /* The mask used to set the ALT_CLKMGR_MISC_MAINCLK_CNT register field value. */
6516 #define ALT_CLKMGR_MISC_MAINCLK_CNT_SET_MSK 0x000001ff
6517 /* The mask used to clear the ALT_CLKMGR_MISC_MAINCLK_CNT register field value. */
6518 #define ALT_CLKMGR_MISC_MAINCLK_CNT_CLR_MSK 0xfffffe00
6519 /* The reset value of the ALT_CLKMGR_MISC_MAINCLK_CNT register field. */
6520 #define ALT_CLKMGR_MISC_MAINCLK_CNT_RESET 0x3
6521 /* Extracts the ALT_CLKMGR_MISC_MAINCLK_CNT field value from a register. */
6522 #define ALT_CLKMGR_MISC_MAINCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
6523 /* Produces a ALT_CLKMGR_MISC_MAINCLK_CNT register field value suitable for setting the register. */
6524 #define ALT_CLKMGR_MISC_MAINCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
6525 
6526 #ifndef __ASSEMBLY__
6527 /*
6528  * WARNING: The C register and register group struct declarations are provided for
6529  * convenience and illustrative purposes. They should, however, be used with
6530  * caution as the C language standard provides no guarantees about the alignment or
6531  * atomicity of device memory accesses. The recommended practice for writing
6532  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6533  * alt_write_word() functions.
6534  *
6535  * The struct declaration for register ALT_CLKMGR_MISC_MAINCLK.
6536  */
6537 struct ALT_CLKMGR_MISC_MAINCLK_s
6538 {
6539  uint32_t cnt : 9; /* Counter */
6540  uint32_t : 23; /* *UNDEFINED* */
6541 };
6542 
6543 /* The typedef declaration for register ALT_CLKMGR_MISC_MAINCLK. */
6544 typedef volatile struct ALT_CLKMGR_MISC_MAINCLK_s ALT_CLKMGR_MISC_MAINCLK_t;
6545 #endif /* __ASSEMBLY__ */
6546 
6547 /* The byte offset of the ALT_CLKMGR_MISC_MAINCLK register from the beginning of the component. */
6548 #define ALT_CLKMGR_MISC_MAINCLK_OFST 0x4
6549 
6550 /*
6551  * Register : Main PLL C2 Control Register for Clock dbg_at_clk - dbgatclk
6552  *
6553  * Contains settings that control clock dbg_at_clk generated from the C2 output of
6554  * the Main PLL.
6555  *
6556  * Only reset by a cold reset.
6557  *
6558  * Register Layout
6559  *
6560  * Bits | Access | Reset | Description
6561  * :-------|:-------|:------|:------------
6562  * [8:0] | RW | 0x3 | Counter
6563  * [31:9] | ??? | 0x0 | *UNDEFINED*
6564  *
6565  */
6566 /*
6567  * Field : Counter - cnt
6568  *
6569  * Divides the VCO frequency by the value+1 in this field.
6570  *
6571  * Field Access Macros:
6572  *
6573  */
6574 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MISC_DBGATCLK_CNT register field. */
6575 #define ALT_CLKMGR_MISC_DBGATCLK_CNT_LSB 0
6576 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MISC_DBGATCLK_CNT register field. */
6577 #define ALT_CLKMGR_MISC_DBGATCLK_CNT_MSB 8
6578 /* The width in bits of the ALT_CLKMGR_MISC_DBGATCLK_CNT register field. */
6579 #define ALT_CLKMGR_MISC_DBGATCLK_CNT_WIDTH 9
6580 /* The mask used to set the ALT_CLKMGR_MISC_DBGATCLK_CNT register field value. */
6581 #define ALT_CLKMGR_MISC_DBGATCLK_CNT_SET_MSK 0x000001ff
6582 /* The mask used to clear the ALT_CLKMGR_MISC_DBGATCLK_CNT register field value. */
6583 #define ALT_CLKMGR_MISC_DBGATCLK_CNT_CLR_MSK 0xfffffe00
6584 /* The reset value of the ALT_CLKMGR_MISC_DBGATCLK_CNT register field. */
6585 #define ALT_CLKMGR_MISC_DBGATCLK_CNT_RESET 0x3
6586 /* Extracts the ALT_CLKMGR_MISC_DBGATCLK_CNT field value from a register. */
6587 #define ALT_CLKMGR_MISC_DBGATCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
6588 /* Produces a ALT_CLKMGR_MISC_DBGATCLK_CNT register field value suitable for setting the register. */
6589 #define ALT_CLKMGR_MISC_DBGATCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
6590 
6591 #ifndef __ASSEMBLY__
6592 /*
6593  * WARNING: The C register and register group struct declarations are provided for
6594  * convenience and illustrative purposes. They should, however, be used with
6595  * caution as the C language standard provides no guarantees about the alignment or
6596  * atomicity of device memory accesses. The recommended practice for writing
6597  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6598  * alt_write_word() functions.
6599  *
6600  * The struct declaration for register ALT_CLKMGR_MISC_DBGATCLK.
6601  */
6602 struct ALT_CLKMGR_MISC_DBGATCLK_s
6603 {
6604  uint32_t cnt : 9; /* Counter */
6605  uint32_t : 23; /* *UNDEFINED* */
6606 };
6607 
6608 /* The typedef declaration for register ALT_CLKMGR_MISC_DBGATCLK. */
6609 typedef volatile struct ALT_CLKMGR_MISC_DBGATCLK_s ALT_CLKMGR_MISC_DBGATCLK_t;
6610 #endif /* __ASSEMBLY__ */
6611 
6612 /* The byte offset of the ALT_CLKMGR_MISC_DBGATCLK register from the beginning of the component. */
6613 #define ALT_CLKMGR_MISC_DBGATCLK_OFST 0x8
6614 
6615 #ifndef __ASSEMBLY__
6616 /*
6617  * WARNING: The C register and register group struct declarations are provided for
6618  * convenience and illustrative purposes. They should, however, be used with
6619  * caution as the C language standard provides no guarantees about the alignment or
6620  * atomicity of device memory accesses. The recommended practice for writing
6621  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6622  * alt_write_word() functions.
6623  *
6624  * The struct declaration for register group ALT_CLKMGR_MISCGRP.
6625  */
6626 struct ALT_CLKMGR_MISCGRP_s
6627 {
6628  ALT_CLKMGR_MISC_MPUCLK_t mpuclk; /* ALT_CLKMGR_MISC_MPUCLK */
6629  ALT_CLKMGR_MISC_MAINCLK_t mainclk; /* ALT_CLKMGR_MISC_MAINCLK */
6630  ALT_CLKMGR_MISC_DBGATCLK_t dbgatclk; /* ALT_CLKMGR_MISC_DBGATCLK */
6631  volatile uint32_t _pad_0xc_0x20[5]; /* *UNDEFINED* */
6632 };
6633 
6634 /* The typedef declaration for register group ALT_CLKMGR_MISCGRP. */
6635 typedef volatile struct ALT_CLKMGR_MISCGRP_s ALT_CLKMGR_MISCGRP_t;
6636 /* The struct declaration for the raw register contents of register group ALT_CLKMGR_MISCGRP. */
6637 struct ALT_CLKMGR_MISCGRP_raw_s
6638 {
6639  volatile uint32_t mpuclk; /* ALT_CLKMGR_MISC_MPUCLK */
6640  volatile uint32_t mainclk; /* ALT_CLKMGR_MISC_MAINCLK */
6641  volatile uint32_t dbgatclk; /* ALT_CLKMGR_MISC_DBGATCLK */
6642  uint32_t _pad_0xc_0x20[5]; /* *UNDEFINED* */
6643 };
6644 
6645 /* The typedef declaration for the raw register contents of register group ALT_CLKMGR_MISCGRP. */
6646 typedef volatile struct ALT_CLKMGR_MISCGRP_raw_s ALT_CLKMGR_MISCGRP_raw_t;
6647 #endif /* __ASSEMBLY__ */
6648 
6649 
6650 #ifndef __ASSEMBLY__
6651 /*
6652  * WARNING: The C register and register group struct declarations are provided for
6653  * convenience and illustrative purposes. They should, however, be used with
6654  * caution as the C language standard provides no guarantees about the alignment or
6655  * atomicity of device memory accesses. The recommended practice for writing
6656  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6657  * alt_write_word() functions.
6658  *
6659  * The struct declaration for register group ALT_CLKMGR.
6660  */
6661 struct ALT_CLKMGR_s
6662 {
6663  ALT_CLKMGR_CTL_t ctrl; /* ALT_CLKMGR_CTL */
6664  ALT_CLKMGR_BYPASS_t bypass; /* ALT_CLKMGR_BYPASS */
6665  ALT_CLKMGR_INTER_t inter; /* ALT_CLKMGR_INTER */
6666  ALT_CLKMGR_INTREN_t intren; /* ALT_CLKMGR_INTREN */
6667  ALT_CLKMGR_DBCTL_t dbctrl; /* ALT_CLKMGR_DBCTL */
6668  ALT_CLKMGR_STAT_t stat; /* ALT_CLKMGR_STAT */
6669  volatile uint32_t _pad_0x18_0x3f[10]; /* *UNDEFINED* */
6670  ALT_CLKMGR_MAINPLL_t mainpllgrp; /* ALT_CLKMGR_MAINPLL */
6671  ALT_CLKMGR_PERPLL_t perpllgrp; /* ALT_CLKMGR_PERPLL */
6672  ALT_CLKMGR_SDRPLL_t sdrpllgrp; /* ALT_CLKMGR_SDRPLL */
6673  ALT_CLKMGR_MISCGRP_t miscgrp; /* ALT_CLKMGR_MISCGRP */
6674  volatile uint32_t _pad_0x100_0x200[64]; /* *UNDEFINED* */
6675 };
6676 
6677 /* The typedef declaration for register group ALT_CLKMGR. */
6678 typedef volatile struct ALT_CLKMGR_s ALT_CLKMGR_t;
6679 /* The struct declaration for the raw register contents of register group ALT_CLKMGR. */
6680 struct ALT_CLKMGR_raw_s
6681 {
6682  volatile uint32_t ctrl; /* ALT_CLKMGR_CTL */
6683  volatile uint32_t bypass; /* ALT_CLKMGR_BYPASS */
6684  volatile uint32_t inter; /* ALT_CLKMGR_INTER */
6685  volatile uint32_t intren; /* ALT_CLKMGR_INTREN */
6686  volatile uint32_t dbctrl; /* ALT_CLKMGR_DBCTL */
6687  volatile uint32_t stat; /* ALT_CLKMGR_STAT */
6688  uint32_t _pad_0x18_0x3f[10]; /* *UNDEFINED* */
6689  ALT_CLKMGR_MAINPLL_raw_t mainpllgrp; /* ALT_CLKMGR_MAINPLL */
6690  ALT_CLKMGR_PERPLL_raw_t perpllgrp; /* ALT_CLKMGR_PERPLL */
6691  ALT_CLKMGR_SDRPLL_raw_t sdrpllgrp; /* ALT_CLKMGR_SDRPLL */
6692  ALT_CLKMGR_MISCGRP_raw_t miscgrp; /* ALT_CLKMGR_MISCGRP */
6693  uint32_t _pad_0x100_0x200[64]; /* *UNDEFINED* */
6694 };
6695 
6696 /* The typedef declaration for the raw register contents of register group ALT_CLKMGR. */
6697 typedef volatile struct ALT_CLKMGR_raw_s ALT_CLKMGR_raw_t;
6698 #endif /* __ASSEMBLY__ */
6699 
6700 
6701 #ifdef __cplusplus
6702 }
6703 #endif /* __cplusplus */
6704 #endif /* __ALTERA_ALT_CLKMGR_H__ */
6705