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alt_soc_noc_fw_ddr_scr.h
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32 
33 /* Altera - ALT_SOC_NOC_FW_DDR_SCR */
34 
35 #ifndef __ALT_SOCAL_SOC_NOC_FW_DDR_SCR_H__
36 #define __ALT_SOCAL_SOC_NOC_FW_DDR_SCR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : SOC_NOC_FW_DDR_SCR
50  * DDR Security Control Registers (SCR)
51  *
52  */
53 /*
54  * Register : enable
55  *
56  * Enable
57  *
58  * Register Layout
59  *
60  * Bits | Access | Reset | Description
61  * :--------|:-------|:------|:--------------------------------------------------
62  * [0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE
63  * [1] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE
64  * [2] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE
65  * [3] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE
66  * [4] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE
67  * [5] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE
68  * [6] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE
69  * [7] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE
70  * [8] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE
71  * [9] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE
72  * [10] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE
73  * [11] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE
74  * [12] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE
75  * [13] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE
76  * [14] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE
77  * [15] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE
78  * [31:16] | ??? | 0x0 | *UNDEFINED*
79  *
80  */
81 /*
82  * Field : mpuregion0enable
83  *
84  * MPU Region 0 Enable. Value of 1 means region is enabled, Value of 0 means region
85  * is disabled
86  *
87  * Field Access Macros:
88  *
89  */
90 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE register field. */
91 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE_LSB 0
92 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE register field. */
93 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE_MSB 0
94 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE register field. */
95 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE_WIDTH 1
96 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE register field value. */
97 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE_SET_MSK 0x00000001
98 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE register field value. */
99 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE_CLR_MSK 0xfffffffe
100 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE register field. */
101 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE_RESET 0x0
102 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE field value from a register. */
103 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE_GET(value) (((value) & 0x00000001) >> 0)
104 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE register field value suitable for setting the register. */
105 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE_SET(value) (((value) << 0) & 0x00000001)
106 
107 /*
108  * Field : mpuregion1enable
109  *
110  * MPU Region 1 Enable. Value of 1 means region is enabled, Value of 0 means region
111  * is disabled
112  *
113  * Field Access Macros:
114  *
115  */
116 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE register field. */
117 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE_LSB 1
118 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE register field. */
119 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE_MSB 1
120 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE register field. */
121 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE_WIDTH 1
122 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE register field value. */
123 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE_SET_MSK 0x00000002
124 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE register field value. */
125 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE_CLR_MSK 0xfffffffd
126 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE register field. */
127 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE_RESET 0x0
128 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE field value from a register. */
129 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE_GET(value) (((value) & 0x00000002) >> 1)
130 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE register field value suitable for setting the register. */
131 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE_SET(value) (((value) << 1) & 0x00000002)
132 
133 /*
134  * Field : mpuregion2enable
135  *
136  * MPU Region 2 Enable. Value of 1 means region is enabled, Value of 0 means region
137  * is disabled
138  *
139  * Field Access Macros:
140  *
141  */
142 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE register field. */
143 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE_LSB 2
144 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE register field. */
145 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE_MSB 2
146 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE register field. */
147 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE_WIDTH 1
148 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE register field value. */
149 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE_SET_MSK 0x00000004
150 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE register field value. */
151 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE_CLR_MSK 0xfffffffb
152 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE register field. */
153 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE_RESET 0x0
154 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE field value from a register. */
155 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE_GET(value) (((value) & 0x00000004) >> 2)
156 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE register field value suitable for setting the register. */
157 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE_SET(value) (((value) << 2) & 0x00000004)
158 
159 /*
160  * Field : mpuregion3enable
161  *
162  * MPU Region 3 Enable. Value of 1 means region is enabled, Value of 0 means region
163  * is disabled
164  *
165  * Field Access Macros:
166  *
167  */
168 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE register field. */
169 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE_LSB 3
170 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE register field. */
171 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE_MSB 3
172 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE register field. */
173 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE_WIDTH 1
174 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE register field value. */
175 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE_SET_MSK 0x00000008
176 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE register field value. */
177 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE_CLR_MSK 0xfffffff7
178 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE register field. */
179 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE_RESET 0x0
180 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE field value from a register. */
181 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE_GET(value) (((value) & 0x00000008) >> 3)
182 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE register field value suitable for setting the register. */
183 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE_SET(value) (((value) << 3) & 0x00000008)
184 
185 /*
186  * Field : mpuregion4enable
187  *
188  * MPURegion 4 Enable. Value of 1 means region is enabled, Value of 0 means region
189  * is disabled
190  *
191  * Field Access Macros:
192  *
193  */
194 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE register field. */
195 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE_LSB 4
196 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE register field. */
197 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE_MSB 4
198 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE register field. */
199 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE_WIDTH 1
200 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE register field value. */
201 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE_SET_MSK 0x00000010
202 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE register field value. */
203 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE_CLR_MSK 0xffffffef
204 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE register field. */
205 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE_RESET 0x0
206 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE field value from a register. */
207 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE_GET(value) (((value) & 0x00000010) >> 4)
208 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE register field value suitable for setting the register. */
209 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE_SET(value) (((value) << 4) & 0x00000010)
210 
211 /*
212  * Field : mpuregion5enable
213  *
214  * MPURegion 5 Enable. Value of 1 means region is enabled, Value of 0 means region
215  * is disabled
216  *
217  * Field Access Macros:
218  *
219  */
220 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE register field. */
221 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE_LSB 5
222 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE register field. */
223 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE_MSB 5
224 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE register field. */
225 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE_WIDTH 1
226 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE register field value. */
227 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE_SET_MSK 0x00000020
228 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE register field value. */
229 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE_CLR_MSK 0xffffffdf
230 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE register field. */
231 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE_RESET 0x0
232 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE field value from a register. */
233 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE_GET(value) (((value) & 0x00000020) >> 5)
234 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE register field value suitable for setting the register. */
235 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE_SET(value) (((value) << 5) & 0x00000020)
236 
237 /*
238  * Field : mpuregion6enable
239  *
240  * MPU Region 6 Enable. Value of 1 means region is enabled, Value of 0 means region
241  * is disabled
242  *
243  * Field Access Macros:
244  *
245  */
246 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE register field. */
247 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE_LSB 6
248 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE register field. */
249 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE_MSB 6
250 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE register field. */
251 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE_WIDTH 1
252 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE register field value. */
253 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE_SET_MSK 0x00000040
254 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE register field value. */
255 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE_CLR_MSK 0xffffffbf
256 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE register field. */
257 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE_RESET 0x0
258 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE field value from a register. */
259 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE_GET(value) (((value) & 0x00000040) >> 6)
260 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE register field value suitable for setting the register. */
261 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE_SET(value) (((value) << 6) & 0x00000040)
262 
263 /*
264  * Field : mpuregion7enable
265  *
266  * MPU Region 7 Enable. Value of 1 means region is enabled, Value of 0 means region
267  * is disabled
268  *
269  * Field Access Macros:
270  *
271  */
272 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE register field. */
273 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE_LSB 7
274 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE register field. */
275 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE_MSB 7
276 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE register field. */
277 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE_WIDTH 1
278 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE register field value. */
279 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE_SET_MSK 0x00000080
280 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE register field value. */
281 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE_CLR_MSK 0xffffff7f
282 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE register field. */
283 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE_RESET 0x0
284 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE field value from a register. */
285 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE_GET(value) (((value) & 0x00000080) >> 7)
286 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE register field value suitable for setting the register. */
287 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE_SET(value) (((value) << 7) & 0x00000080)
288 
289 /*
290  * Field : nonmpuregion0enable
291  *
292  * non MPU Region 0 Enable. Value of 1 means region is enabled, Value of 0 means
293  * region is disabled
294  *
295  * Field Access Macros:
296  *
297  */
298 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE register field. */
299 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE_LSB 8
300 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE register field. */
301 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE_MSB 8
302 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE register field. */
303 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE_WIDTH 1
304 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE register field value. */
305 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE_SET_MSK 0x00000100
306 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE register field value. */
307 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE_CLR_MSK 0xfffffeff
308 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE register field. */
309 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE_RESET 0x0
310 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE field value from a register. */
311 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE_GET(value) (((value) & 0x00000100) >> 8)
312 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE register field value suitable for setting the register. */
313 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE_SET(value) (((value) << 8) & 0x00000100)
314 
315 /*
316  * Field : nonmpuregion1enable
317  *
318  * non MPU Region 1 Enable. Value of 1 means region is enabled, Value of 0 means
319  * region is disabled
320  *
321  * Field Access Macros:
322  *
323  */
324 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE register field. */
325 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE_LSB 9
326 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE register field. */
327 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE_MSB 9
328 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE register field. */
329 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE_WIDTH 1
330 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE register field value. */
331 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE_SET_MSK 0x00000200
332 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE register field value. */
333 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE_CLR_MSK 0xfffffdff
334 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE register field. */
335 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE_RESET 0x0
336 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE field value from a register. */
337 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE_GET(value) (((value) & 0x00000200) >> 9)
338 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE register field value suitable for setting the register. */
339 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE_SET(value) (((value) << 9) & 0x00000200)
340 
341 /*
342  * Field : nonmpuregion2enable
343  *
344  * non MPU Region 2 Enable. Value of 1 means region is enabled, Value of 0 means
345  * region is disabled
346  *
347  * Field Access Macros:
348  *
349  */
350 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE register field. */
351 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE_LSB 10
352 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE register field. */
353 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE_MSB 10
354 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE register field. */
355 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE_WIDTH 1
356 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE register field value. */
357 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE_SET_MSK 0x00000400
358 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE register field value. */
359 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE_CLR_MSK 0xfffffbff
360 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE register field. */
361 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE_RESET 0x0
362 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE field value from a register. */
363 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE_GET(value) (((value) & 0x00000400) >> 10)
364 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE register field value suitable for setting the register. */
365 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE_SET(value) (((value) << 10) & 0x00000400)
366 
367 /*
368  * Field : nonmpuregion3enable
369  *
370  * non MPU Region 3 Enable. Value of 1 means region is enabled, Value of 0 means
371  * region is disabled
372  *
373  * Field Access Macros:
374  *
375  */
376 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE register field. */
377 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE_LSB 11
378 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE register field. */
379 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE_MSB 11
380 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE register field. */
381 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE_WIDTH 1
382 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE register field value. */
383 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE_SET_MSK 0x00000800
384 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE register field value. */
385 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE_CLR_MSK 0xfffff7ff
386 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE register field. */
387 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE_RESET 0x0
388 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE field value from a register. */
389 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE_GET(value) (((value) & 0x00000800) >> 11)
390 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE register field value suitable for setting the register. */
391 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE_SET(value) (((value) << 11) & 0x00000800)
392 
393 /*
394  * Field : nonmpuregion4enable
395  *
396  * non MPU Region 4 Enable. Value of 1 means region is enabled, Value of 0 means
397  * region is disabled
398  *
399  * Field Access Macros:
400  *
401  */
402 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE register field. */
403 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE_LSB 12
404 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE register field. */
405 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE_MSB 12
406 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE register field. */
407 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE_WIDTH 1
408 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE register field value. */
409 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE_SET_MSK 0x00001000
410 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE register field value. */
411 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE_CLR_MSK 0xffffefff
412 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE register field. */
413 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE_RESET 0x0
414 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE field value from a register. */
415 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE_GET(value) (((value) & 0x00001000) >> 12)
416 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE register field value suitable for setting the register. */
417 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE_SET(value) (((value) << 12) & 0x00001000)
418 
419 /*
420  * Field : nonmpuregion5enable
421  *
422  * non MPU Region 5 Enable. Value of 1 means region is enabled, Value of 0 means
423  * region is disabled
424  *
425  * Field Access Macros:
426  *
427  */
428 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE register field. */
429 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE_LSB 13
430 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE register field. */
431 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE_MSB 13
432 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE register field. */
433 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE_WIDTH 1
434 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE register field value. */
435 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE_SET_MSK 0x00002000
436 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE register field value. */
437 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE_CLR_MSK 0xffffdfff
438 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE register field. */
439 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE_RESET 0x0
440 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE field value from a register. */
441 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE_GET(value) (((value) & 0x00002000) >> 13)
442 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE register field value suitable for setting the register. */
443 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE_SET(value) (((value) << 13) & 0x00002000)
444 
445 /*
446  * Field : nonmpuregion6enable
447  *
448  * non MPU Region 6 Enable. Value of 1 means region is enabled, Value of 0 means
449  * region is disabled
450  *
451  * Field Access Macros:
452  *
453  */
454 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE register field. */
455 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE_LSB 14
456 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE register field. */
457 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE_MSB 14
458 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE register field. */
459 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE_WIDTH 1
460 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE register field value. */
461 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE_SET_MSK 0x00004000
462 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE register field value. */
463 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE_CLR_MSK 0xffffbfff
464 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE register field. */
465 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE_RESET 0x0
466 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE field value from a register. */
467 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE_GET(value) (((value) & 0x00004000) >> 14)
468 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE register field value suitable for setting the register. */
469 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE_SET(value) (((value) << 14) & 0x00004000)
470 
471 /*
472  * Field : nonmpuregion7enable
473  *
474  * non MPU Region 7 Enable. Value of 1 means region is enabled, Value of 0 means
475  * region is disabled
476  *
477  * Field Access Macros:
478  *
479  */
480 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE register field. */
481 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE_LSB 15
482 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE register field. */
483 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE_MSB 15
484 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE register field. */
485 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE_WIDTH 1
486 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE register field value. */
487 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE_SET_MSK 0x00008000
488 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE register field value. */
489 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE_CLR_MSK 0xffff7fff
490 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE register field. */
491 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE_RESET 0x0
492 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE field value from a register. */
493 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE_GET(value) (((value) & 0x00008000) >> 15)
494 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE register field value suitable for setting the register. */
495 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE_SET(value) (((value) << 15) & 0x00008000)
496 
497 #ifndef __ASSEMBLY__
498 /*
499  * WARNING: The C register and register group struct declarations are provided for
500  * convenience and illustrative purposes. They should, however, be used with
501  * caution as the C language standard provides no guarantees about the alignment or
502  * atomicity of device memory accesses. The recommended practice for coding device
503  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
504  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
505  * alt_write_dword() functions for 64 bit registers.
506  *
507  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_ENABLE.
508  */
509 struct ALT_SOC_NOC_FW_DDR_SCR_ENABLE_s
510 {
511  volatile uint32_t mpuregion0enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE */
512  volatile uint32_t mpuregion1enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE */
513  volatile uint32_t mpuregion2enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE */
514  volatile uint32_t mpuregion3enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE */
515  volatile uint32_t mpuregion4enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE */
516  volatile uint32_t mpuregion5enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE */
517  volatile uint32_t mpuregion6enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE */
518  volatile uint32_t mpuregion7enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE */
519  volatile uint32_t nonmpuregion0enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE */
520  volatile uint32_t nonmpuregion1enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE */
521  volatile uint32_t nonmpuregion2enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE */
522  volatile uint32_t nonmpuregion3enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE */
523  volatile uint32_t nonmpuregion4enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE */
524  volatile uint32_t nonmpuregion5enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE */
525  volatile uint32_t nonmpuregion6enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE */
526  volatile uint32_t nonmpuregion7enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE */
527  uint32_t : 16; /* *UNDEFINED* */
528 };
529 
530 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_ENABLE. */
531 typedef struct ALT_SOC_NOC_FW_DDR_SCR_ENABLE_s ALT_SOC_NOC_FW_DDR_SCR_ENABLE_t;
532 #endif /* __ASSEMBLY__ */
533 
534 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE register. */
535 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_RESET 0x00000000
536 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE register from the beginning of the component. */
537 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_OFST 0x0
538 
539 /*
540  * Register : enable_set
541  *
542  * Sets Master Region Enable field when written with 1
543  *
544  * Register Layout
545  *
546  * Bits | Access | Reset | Description
547  * :--------|:-------|:------|:------------------------------------------------------
548  * [0] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE
549  * [1] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE
550  * [2] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE
551  * [3] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE
552  * [4] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE
553  * [5] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE
554  * [6] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE
555  * [7] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE
556  * [8] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE
557  * [9] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE
558  * [10] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE
559  * [11] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE
560  * [12] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE
561  * [13] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE
562  * [14] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE
563  * [15] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE
564  * [31:16] | ??? | 0x0 | *UNDEFINED*
565  *
566  */
567 /*
568  * Field : mpuregion0enable
569  *
570  * MPU Region 0 Enable Set.
571  *
572  * Writing zero has no effect
573  *
574  * Writing one will set the region0enable bit to one
575  *
576  * Field Access Macros:
577  *
578  */
579 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE register field. */
580 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE_LSB 0
581 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE register field. */
582 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE_MSB 0
583 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE register field. */
584 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE_WIDTH 1
585 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE register field value. */
586 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE_SET_MSK 0x00000001
587 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE register field value. */
588 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE_CLR_MSK 0xfffffffe
589 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE register field. */
590 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE_RESET 0x0
591 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE field value from a register. */
592 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE_GET(value) (((value) & 0x00000001) >> 0)
593 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE register field value suitable for setting the register. */
594 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE_SET(value) (((value) << 0) & 0x00000001)
595 
596 /*
597  * Field : mpuregion1enable
598  *
599  * MPU Region 1 Enable Set.
600  *
601  * Writing zero has no effect
602  *
603  * Writing one will set the region1enable bit to one
604  *
605  * Field Access Macros:
606  *
607  */
608 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE register field. */
609 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE_LSB 1
610 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE register field. */
611 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE_MSB 1
612 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE register field. */
613 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE_WIDTH 1
614 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE register field value. */
615 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE_SET_MSK 0x00000002
616 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE register field value. */
617 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE_CLR_MSK 0xfffffffd
618 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE register field. */
619 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE_RESET 0x0
620 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE field value from a register. */
621 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE_GET(value) (((value) & 0x00000002) >> 1)
622 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE register field value suitable for setting the register. */
623 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE_SET(value) (((value) << 1) & 0x00000002)
624 
625 /*
626  * Field : mpuregion2enable
627  *
628  * MPU Region 2 Enable Set.
629  *
630  * Writing zero has no effect
631  *
632  * Writing one will set the region2enable bit to one
633  *
634  * Field Access Macros:
635  *
636  */
637 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE register field. */
638 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE_LSB 2
639 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE register field. */
640 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE_MSB 2
641 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE register field. */
642 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE_WIDTH 1
643 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE register field value. */
644 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE_SET_MSK 0x00000004
645 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE register field value. */
646 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE_CLR_MSK 0xfffffffb
647 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE register field. */
648 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE_RESET 0x0
649 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE field value from a register. */
650 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE_GET(value) (((value) & 0x00000004) >> 2)
651 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE register field value suitable for setting the register. */
652 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE_SET(value) (((value) << 2) & 0x00000004)
653 
654 /*
655  * Field : mpuregion3enable
656  *
657  * MPU Region 3 Enable Set.
658  *
659  * Writing zero has no effect
660  *
661  * Writing one will set the region3enable bit to one
662  *
663  * Field Access Macros:
664  *
665  */
666 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE register field. */
667 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE_LSB 3
668 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE register field. */
669 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE_MSB 3
670 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE register field. */
671 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE_WIDTH 1
672 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE register field value. */
673 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE_SET_MSK 0x00000008
674 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE register field value. */
675 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE_CLR_MSK 0xfffffff7
676 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE register field. */
677 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE_RESET 0x0
678 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE field value from a register. */
679 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE_GET(value) (((value) & 0x00000008) >> 3)
680 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE register field value suitable for setting the register. */
681 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE_SET(value) (((value) << 3) & 0x00000008)
682 
683 /*
684  * Field : mpuregion4enable
685  *
686  * MPU Region 4 Enable Set.
687  *
688  * Writing zero has no effect
689  *
690  * Writing one will set the region4enable bit to one
691  *
692  * Field Access Macros:
693  *
694  */
695 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE register field. */
696 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE_LSB 4
697 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE register field. */
698 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE_MSB 4
699 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE register field. */
700 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE_WIDTH 1
701 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE register field value. */
702 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE_SET_MSK 0x00000010
703 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE register field value. */
704 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE_CLR_MSK 0xffffffef
705 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE register field. */
706 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE_RESET 0x0
707 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE field value from a register. */
708 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE_GET(value) (((value) & 0x00000010) >> 4)
709 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE register field value suitable for setting the register. */
710 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE_SET(value) (((value) << 4) & 0x00000010)
711 
712 /*
713  * Field : mpuregion5enable
714  *
715  * MPU Region 5 Enable Set.
716  *
717  * Writing zero has no effect
718  *
719  * Writing one will set the region5enable bit to one
720  *
721  * Field Access Macros:
722  *
723  */
724 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE register field. */
725 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE_LSB 5
726 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE register field. */
727 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE_MSB 5
728 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE register field. */
729 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE_WIDTH 1
730 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE register field value. */
731 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE_SET_MSK 0x00000020
732 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE register field value. */
733 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE_CLR_MSK 0xffffffdf
734 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE register field. */
735 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE_RESET 0x0
736 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE field value from a register. */
737 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE_GET(value) (((value) & 0x00000020) >> 5)
738 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE register field value suitable for setting the register. */
739 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE_SET(value) (((value) << 5) & 0x00000020)
740 
741 /*
742  * Field : mpuregion6enable
743  *
744  * MPU Region 6 Enable Set.
745  *
746  * Writing zero has no effect
747  *
748  * Writing one will set the region6enable bit to one
749  *
750  * Field Access Macros:
751  *
752  */
753 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE register field. */
754 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE_LSB 6
755 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE register field. */
756 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE_MSB 6
757 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE register field. */
758 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE_WIDTH 1
759 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE register field value. */
760 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE_SET_MSK 0x00000040
761 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE register field value. */
762 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE_CLR_MSK 0xffffffbf
763 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE register field. */
764 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE_RESET 0x0
765 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE field value from a register. */
766 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE_GET(value) (((value) & 0x00000040) >> 6)
767 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE register field value suitable for setting the register. */
768 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE_SET(value) (((value) << 6) & 0x00000040)
769 
770 /*
771  * Field : mpuregion7enable
772  *
773  * MPU Region 7 Enable Set.
774  *
775  * Writing zero has no effect
776  *
777  * Writing one will set the region7enable bit to one
778  *
779  * Field Access Macros:
780  *
781  */
782 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE register field. */
783 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE_LSB 7
784 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE register field. */
785 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE_MSB 7
786 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE register field. */
787 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE_WIDTH 1
788 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE register field value. */
789 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE_SET_MSK 0x00000080
790 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE register field value. */
791 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE_CLR_MSK 0xffffff7f
792 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE register field. */
793 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE_RESET 0x0
794 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE field value from a register. */
795 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE_GET(value) (((value) & 0x00000080) >> 7)
796 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE register field value suitable for setting the register. */
797 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE_SET(value) (((value) << 7) & 0x00000080)
798 
799 /*
800  * Field : nonmpuregion0enable
801  *
802  * non MPU Region 0 Enable Set.
803  *
804  * Writing zero has no effect
805  *
806  * Writing one will set the region7enable bit to one
807  *
808  * Field Access Macros:
809  *
810  */
811 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE register field. */
812 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE_LSB 8
813 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE register field. */
814 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE_MSB 8
815 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE register field. */
816 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE_WIDTH 1
817 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE register field value. */
818 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE_SET_MSK 0x00000100
819 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE register field value. */
820 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE_CLR_MSK 0xfffffeff
821 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE register field. */
822 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE_RESET 0x0
823 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE field value from a register. */
824 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE_GET(value) (((value) & 0x00000100) >> 8)
825 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE register field value suitable for setting the register. */
826 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE_SET(value) (((value) << 8) & 0x00000100)
827 
828 /*
829  * Field : nonmpuregion1enable
830  *
831  * non MPU Region 1 Enable Set.
832  *
833  * Writing zero has no effect
834  *
835  * Writing one will set the region7enable bit to one
836  *
837  * Field Access Macros:
838  *
839  */
840 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE register field. */
841 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE_LSB 9
842 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE register field. */
843 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE_MSB 9
844 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE register field. */
845 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE_WIDTH 1
846 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE register field value. */
847 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE_SET_MSK 0x00000200
848 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE register field value. */
849 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE_CLR_MSK 0xfffffdff
850 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE register field. */
851 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE_RESET 0x0
852 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE field value from a register. */
853 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE_GET(value) (((value) & 0x00000200) >> 9)
854 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE register field value suitable for setting the register. */
855 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE_SET(value) (((value) << 9) & 0x00000200)
856 
857 /*
858  * Field : nonmpuregion2enable
859  *
860  * non MPU Region 2 Enable Set.
861  *
862  * Writing zero has no effect
863  *
864  * Writing one will set the region7enable bit to one
865  *
866  * Field Access Macros:
867  *
868  */
869 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE register field. */
870 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE_LSB 10
871 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE register field. */
872 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE_MSB 10
873 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE register field. */
874 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE_WIDTH 1
875 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE register field value. */
876 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE_SET_MSK 0x00000400
877 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE register field value. */
878 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE_CLR_MSK 0xfffffbff
879 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE register field. */
880 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE_RESET 0x0
881 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE field value from a register. */
882 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE_GET(value) (((value) & 0x00000400) >> 10)
883 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE register field value suitable for setting the register. */
884 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE_SET(value) (((value) << 10) & 0x00000400)
885 
886 /*
887  * Field : nonmpuregion3enable
888  *
889  * non MPU Region 3 Enable Set.
890  *
891  * Writing zero has no effect
892  *
893  * Writing one will set the region7enable bit to one
894  *
895  * Field Access Macros:
896  *
897  */
898 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE register field. */
899 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE_LSB 11
900 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE register field. */
901 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE_MSB 11
902 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE register field. */
903 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE_WIDTH 1
904 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE register field value. */
905 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE_SET_MSK 0x00000800
906 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE register field value. */
907 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE_CLR_MSK 0xfffff7ff
908 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE register field. */
909 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE_RESET 0x0
910 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE field value from a register. */
911 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE_GET(value) (((value) & 0x00000800) >> 11)
912 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE register field value suitable for setting the register. */
913 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE_SET(value) (((value) << 11) & 0x00000800)
914 
915 /*
916  * Field : nonmpuregion4enable
917  *
918  * non MPU Region 4 Enable Set.
919  *
920  * Writing zero has no effect
921  *
922  * Writing one will set the region7enable bit to one
923  *
924  * Field Access Macros:
925  *
926  */
927 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE register field. */
928 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE_LSB 12
929 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE register field. */
930 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE_MSB 12
931 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE register field. */
932 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE_WIDTH 1
933 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE register field value. */
934 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE_SET_MSK 0x00001000
935 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE register field value. */
936 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE_CLR_MSK 0xffffefff
937 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE register field. */
938 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE_RESET 0x0
939 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE field value from a register. */
940 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE_GET(value) (((value) & 0x00001000) >> 12)
941 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE register field value suitable for setting the register. */
942 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE_SET(value) (((value) << 12) & 0x00001000)
943 
944 /*
945  * Field : nonmpuregion5enable
946  *
947  * non MPU Region 5 Enable Set.
948  *
949  * Writing zero has no effect
950  *
951  * Writing one will set the region7enable bit to one
952  *
953  * Field Access Macros:
954  *
955  */
956 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE register field. */
957 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE_LSB 13
958 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE register field. */
959 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE_MSB 13
960 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE register field. */
961 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE_WIDTH 1
962 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE register field value. */
963 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE_SET_MSK 0x00002000
964 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE register field value. */
965 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE_CLR_MSK 0xffffdfff
966 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE register field. */
967 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE_RESET 0x0
968 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE field value from a register. */
969 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE_GET(value) (((value) & 0x00002000) >> 13)
970 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE register field value suitable for setting the register. */
971 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE_SET(value) (((value) << 13) & 0x00002000)
972 
973 /*
974  * Field : nonmpuregion6enable
975  *
976  * non MPU Region 6 Enable Set.
977  *
978  * Writing zero has no effect
979  *
980  * Writing one will set the region7enable bit to one
981  *
982  * Field Access Macros:
983  *
984  */
985 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE register field. */
986 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE_LSB 14
987 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE register field. */
988 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE_MSB 14
989 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE register field. */
990 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE_WIDTH 1
991 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE register field value. */
992 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE_SET_MSK 0x00004000
993 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE register field value. */
994 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE_CLR_MSK 0xffffbfff
995 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE register field. */
996 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE_RESET 0x0
997 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE field value from a register. */
998 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE_GET(value) (((value) & 0x00004000) >> 14)
999 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE register field value suitable for setting the register. */
1000 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE_SET(value) (((value) << 14) & 0x00004000)
1001 
1002 /*
1003  * Field : nonmpuregion7enable
1004  *
1005  * non MPU Region 7 Enable Set.
1006  *
1007  * Writing zero has no effect
1008  *
1009  * Writing one will set the region7enable bit to one
1010  *
1011  * Field Access Macros:
1012  *
1013  */
1014 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE register field. */
1015 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE_LSB 15
1016 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE register field. */
1017 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE_MSB 15
1018 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE register field. */
1019 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE_WIDTH 1
1020 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE register field value. */
1021 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE_SET_MSK 0x00008000
1022 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE register field value. */
1023 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE_CLR_MSK 0xffff7fff
1024 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE register field. */
1025 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE_RESET 0x0
1026 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE field value from a register. */
1027 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE_GET(value) (((value) & 0x00008000) >> 15)
1028 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE register field value suitable for setting the register. */
1029 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE_SET(value) (((value) << 15) & 0x00008000)
1030 
1031 #ifndef __ASSEMBLY__
1032 /*
1033  * WARNING: The C register and register group struct declarations are provided for
1034  * convenience and illustrative purposes. They should, however, be used with
1035  * caution as the C language standard provides no guarantees about the alignment or
1036  * atomicity of device memory accesses. The recommended practice for coding device
1037  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1038  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1039  * alt_write_dword() functions for 64 bit registers.
1040  *
1041  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET.
1042  */
1043 struct ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_s
1044 {
1045  volatile uint32_t mpuregion0enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE */
1046  volatile uint32_t mpuregion1enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE */
1047  volatile uint32_t mpuregion2enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE */
1048  volatile uint32_t mpuregion3enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE */
1049  volatile uint32_t mpuregion4enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE */
1050  volatile uint32_t mpuregion5enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE */
1051  volatile uint32_t mpuregion6enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE */
1052  volatile uint32_t mpuregion7enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE */
1053  volatile uint32_t nonmpuregion0enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE */
1054  volatile uint32_t nonmpuregion1enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE */
1055  volatile uint32_t nonmpuregion2enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE */
1056  volatile uint32_t nonmpuregion3enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE */
1057  volatile uint32_t nonmpuregion4enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE */
1058  volatile uint32_t nonmpuregion5enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE */
1059  volatile uint32_t nonmpuregion6enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE */
1060  volatile uint32_t nonmpuregion7enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE */
1061  uint32_t : 16; /* *UNDEFINED* */
1062 };
1063 
1064 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET. */
1065 typedef struct ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_s ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_t;
1066 #endif /* __ASSEMBLY__ */
1067 
1068 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET register. */
1069 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_RESET 0x00000000
1070 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET register from the beginning of the component. */
1071 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_OFST 0x4
1072 
1073 /*
1074  * Register : enable_clear
1075  *
1076  * Clears Master Region Enable field when written with 1
1077  *
1078  * Register Layout
1079  *
1080  * Bits | Access | Reset | Description
1081  * :--------|:-------|:------|:--------------------------------------------------------
1082  * [0] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE
1083  * [1] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE
1084  * [2] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE
1085  * [3] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE
1086  * [4] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE
1087  * [5] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE
1088  * [6] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE
1089  * [7] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE
1090  * [8] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE
1091  * [9] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE
1092  * [10] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE
1093  * [11] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE
1094  * [12] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE
1095  * [13] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE
1096  * [14] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE
1097  * [15] | W | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE
1098  * [31:16] | ??? | 0x0 | *UNDEFINED*
1099  *
1100  */
1101 /*
1102  * Field : mpuregion0enable
1103  *
1104  * MPU Region 0 Enable Clear.
1105  *
1106  * Writing zero has no effect
1107  *
1108  * Writing one will clear the region0enable bit to zero
1109  *
1110  * Field Access Macros:
1111  *
1112  */
1113 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE register field. */
1114 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE_LSB 0
1115 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE register field. */
1116 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE_MSB 0
1117 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE register field. */
1118 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE_WIDTH 1
1119 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE register field value. */
1120 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE_SET_MSK 0x00000001
1121 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE register field value. */
1122 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE_CLR_MSK 0xfffffffe
1123 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE register field. */
1124 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE_RESET 0x0
1125 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE field value from a register. */
1126 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE_GET(value) (((value) & 0x00000001) >> 0)
1127 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE register field value suitable for setting the register. */
1128 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE_SET(value) (((value) << 0) & 0x00000001)
1129 
1130 /*
1131  * Field : mpuregion1enable
1132  *
1133  * MPU Region 1 Enable Clear.
1134  *
1135  * Writing zero has no effect
1136  *
1137  * Writing one will clear the region1enable bit to zero
1138  *
1139  * Field Access Macros:
1140  *
1141  */
1142 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE register field. */
1143 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE_LSB 1
1144 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE register field. */
1145 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE_MSB 1
1146 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE register field. */
1147 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE_WIDTH 1
1148 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE register field value. */
1149 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE_SET_MSK 0x00000002
1150 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE register field value. */
1151 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE_CLR_MSK 0xfffffffd
1152 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE register field. */
1153 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE_RESET 0x0
1154 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE field value from a register. */
1155 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE_GET(value) (((value) & 0x00000002) >> 1)
1156 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE register field value suitable for setting the register. */
1157 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE_SET(value) (((value) << 1) & 0x00000002)
1158 
1159 /*
1160  * Field : mpuregion2enable
1161  *
1162  * MPU Region 2 Enable Clear.
1163  *
1164  * Writing zero has no effect
1165  *
1166  * Writing one will clear the region2enable bit to zero
1167  *
1168  * Field Access Macros:
1169  *
1170  */
1171 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE register field. */
1172 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE_LSB 2
1173 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE register field. */
1174 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE_MSB 2
1175 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE register field. */
1176 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE_WIDTH 1
1177 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE register field value. */
1178 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE_SET_MSK 0x00000004
1179 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE register field value. */
1180 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE_CLR_MSK 0xfffffffb
1181 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE register field. */
1182 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE_RESET 0x0
1183 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE field value from a register. */
1184 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE_GET(value) (((value) & 0x00000004) >> 2)
1185 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE register field value suitable for setting the register. */
1186 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE_SET(value) (((value) << 2) & 0x00000004)
1187 
1188 /*
1189  * Field : mpuregion3enable
1190  *
1191  * MPU Region 3 Enable Clear.
1192  *
1193  * Writing zero has no effect
1194  *
1195  * Writing one will clear the region3enable bit to zero
1196  *
1197  * Field Access Macros:
1198  *
1199  */
1200 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE register field. */
1201 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE_LSB 3
1202 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE register field. */
1203 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE_MSB 3
1204 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE register field. */
1205 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE_WIDTH 1
1206 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE register field value. */
1207 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE_SET_MSK 0x00000008
1208 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE register field value. */
1209 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE_CLR_MSK 0xfffffff7
1210 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE register field. */
1211 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE_RESET 0x0
1212 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE field value from a register. */
1213 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE_GET(value) (((value) & 0x00000008) >> 3)
1214 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE register field value suitable for setting the register. */
1215 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE_SET(value) (((value) << 3) & 0x00000008)
1216 
1217 /*
1218  * Field : mpuregion4enable
1219  *
1220  * MPU Region 4 Enable Clear.
1221  *
1222  * Writing zero has no effect
1223  *
1224  * Writing one will clear the region4enable bit to zero
1225  *
1226  * Field Access Macros:
1227  *
1228  */
1229 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE register field. */
1230 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE_LSB 4
1231 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE register field. */
1232 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE_MSB 4
1233 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE register field. */
1234 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE_WIDTH 1
1235 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE register field value. */
1236 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE_SET_MSK 0x00000010
1237 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE register field value. */
1238 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE_CLR_MSK 0xffffffef
1239 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE register field. */
1240 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE_RESET 0x0
1241 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE field value from a register. */
1242 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE_GET(value) (((value) & 0x00000010) >> 4)
1243 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE register field value suitable for setting the register. */
1244 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE_SET(value) (((value) << 4) & 0x00000010)
1245 
1246 /*
1247  * Field : mpuregion5enable
1248  *
1249  * MPU Region 5 Enable Clear.
1250  *
1251  * Writing zero has no effect
1252  *
1253  * Writing one will clear the region5enable bit to zero
1254  *
1255  * Field Access Macros:
1256  *
1257  */
1258 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE register field. */
1259 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE_LSB 5
1260 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE register field. */
1261 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE_MSB 5
1262 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE register field. */
1263 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE_WIDTH 1
1264 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE register field value. */
1265 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE_SET_MSK 0x00000020
1266 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE register field value. */
1267 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE_CLR_MSK 0xffffffdf
1268 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE register field. */
1269 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE_RESET 0x0
1270 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE field value from a register. */
1271 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE_GET(value) (((value) & 0x00000020) >> 5)
1272 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE register field value suitable for setting the register. */
1273 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE_SET(value) (((value) << 5) & 0x00000020)
1274 
1275 /*
1276  * Field : mpuregion6enable
1277  *
1278  * MPU Region 6 Enable Clear.
1279  *
1280  * Writing zero has no effect
1281  *
1282  * Writing one will clear the region6enable bit to zero
1283  *
1284  * Field Access Macros:
1285  *
1286  */
1287 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE register field. */
1288 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE_LSB 6
1289 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE register field. */
1290 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE_MSB 6
1291 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE register field. */
1292 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE_WIDTH 1
1293 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE register field value. */
1294 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE_SET_MSK 0x00000040
1295 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE register field value. */
1296 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE_CLR_MSK 0xffffffbf
1297 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE register field. */
1298 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE_RESET 0x0
1299 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE field value from a register. */
1300 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE_GET(value) (((value) & 0x00000040) >> 6)
1301 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE register field value suitable for setting the register. */
1302 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE_SET(value) (((value) << 6) & 0x00000040)
1303 
1304 /*
1305  * Field : mpuregion7enable
1306  *
1307  * MPU Region 7 Enable Clear.
1308  *
1309  * Writing zero has no effect
1310  *
1311  * Writing one will clear the region7enable bit to zero
1312  *
1313  * Field Access Macros:
1314  *
1315  */
1316 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE register field. */
1317 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE_LSB 7
1318 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE register field. */
1319 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE_MSB 7
1320 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE register field. */
1321 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE_WIDTH 1
1322 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE register field value. */
1323 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE_SET_MSK 0x00000080
1324 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE register field value. */
1325 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE_CLR_MSK 0xffffff7f
1326 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE register field. */
1327 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE_RESET 0x0
1328 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE field value from a register. */
1329 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE_GET(value) (((value) & 0x00000080) >> 7)
1330 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE register field value suitable for setting the register. */
1331 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE_SET(value) (((value) << 7) & 0x00000080)
1332 
1333 /*
1334  * Field : nonmpuregion0enable
1335  *
1336  * non MPU Region 0 Enable Clear.
1337  *
1338  * Writing zero has no effect
1339  *
1340  * Writing one will clear the region7enable bit to zero
1341  *
1342  * Field Access Macros:
1343  *
1344  */
1345 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE register field. */
1346 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE_LSB 8
1347 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE register field. */
1348 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE_MSB 8
1349 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE register field. */
1350 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE_WIDTH 1
1351 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE register field value. */
1352 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE_SET_MSK 0x00000100
1353 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE register field value. */
1354 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE_CLR_MSK 0xfffffeff
1355 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE register field. */
1356 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE_RESET 0x0
1357 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE field value from a register. */
1358 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE_GET(value) (((value) & 0x00000100) >> 8)
1359 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE register field value suitable for setting the register. */
1360 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE_SET(value) (((value) << 8) & 0x00000100)
1361 
1362 /*
1363  * Field : nonmpuregion1enable
1364  *
1365  * non MPU Region 1 Enable Clear.
1366  *
1367  * Writing zero has no effect
1368  *
1369  * Writing one will clear the region7enable bit to zero
1370  *
1371  * Field Access Macros:
1372  *
1373  */
1374 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE register field. */
1375 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE_LSB 9
1376 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE register field. */
1377 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE_MSB 9
1378 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE register field. */
1379 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE_WIDTH 1
1380 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE register field value. */
1381 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE_SET_MSK 0x00000200
1382 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE register field value. */
1383 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE_CLR_MSK 0xfffffdff
1384 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE register field. */
1385 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE_RESET 0x0
1386 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE field value from a register. */
1387 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE_GET(value) (((value) & 0x00000200) >> 9)
1388 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE register field value suitable for setting the register. */
1389 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE_SET(value) (((value) << 9) & 0x00000200)
1390 
1391 /*
1392  * Field : nonmpuregion2enable
1393  *
1394  * non MPU Region 2 Enable Clear.
1395  *
1396  * Writing zero has no effect
1397  *
1398  * Writing one will clear the region7enable bit to zero
1399  *
1400  * Field Access Macros:
1401  *
1402  */
1403 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE register field. */
1404 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE_LSB 10
1405 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE register field. */
1406 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE_MSB 10
1407 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE register field. */
1408 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE_WIDTH 1
1409 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE register field value. */
1410 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE_SET_MSK 0x00000400
1411 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE register field value. */
1412 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE_CLR_MSK 0xfffffbff
1413 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE register field. */
1414 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE_RESET 0x0
1415 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE field value from a register. */
1416 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE_GET(value) (((value) & 0x00000400) >> 10)
1417 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE register field value suitable for setting the register. */
1418 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE_SET(value) (((value) << 10) & 0x00000400)
1419 
1420 /*
1421  * Field : nonmpuregion3enable
1422  *
1423  * non MPU Region 3 Enable Clear.
1424  *
1425  * Writing zero has no effect
1426  *
1427  * Writing one will clear the region7enable bit to zero
1428  *
1429  * Field Access Macros:
1430  *
1431  */
1432 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE register field. */
1433 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE_LSB 11
1434 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE register field. */
1435 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE_MSB 11
1436 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE register field. */
1437 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE_WIDTH 1
1438 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE register field value. */
1439 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE_SET_MSK 0x00000800
1440 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE register field value. */
1441 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE_CLR_MSK 0xfffff7ff
1442 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE register field. */
1443 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE_RESET 0x0
1444 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE field value from a register. */
1445 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE_GET(value) (((value) & 0x00000800) >> 11)
1446 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE register field value suitable for setting the register. */
1447 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE_SET(value) (((value) << 11) & 0x00000800)
1448 
1449 /*
1450  * Field : nonmpuregion4enable
1451  *
1452  * non MPU Region 4 Enable Clear.
1453  *
1454  * Writing zero has no effect
1455  *
1456  * Writing one will clear the region7enable bit to zero
1457  *
1458  * Field Access Macros:
1459  *
1460  */
1461 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE register field. */
1462 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE_LSB 12
1463 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE register field. */
1464 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE_MSB 12
1465 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE register field. */
1466 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE_WIDTH 1
1467 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE register field value. */
1468 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE_SET_MSK 0x00001000
1469 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE register field value. */
1470 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE_CLR_MSK 0xffffefff
1471 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE register field. */
1472 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE_RESET 0x0
1473 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE field value from a register. */
1474 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE_GET(value) (((value) & 0x00001000) >> 12)
1475 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE register field value suitable for setting the register. */
1476 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE_SET(value) (((value) << 12) & 0x00001000)
1477 
1478 /*
1479  * Field : nonmpuregion5enable
1480  *
1481  * non MPU Region 5 Enable Clear.
1482  *
1483  * Writing zero has no effect
1484  *
1485  * Writing one will clear the region7enable bit to zero
1486  *
1487  * Field Access Macros:
1488  *
1489  */
1490 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE register field. */
1491 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE_LSB 13
1492 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE register field. */
1493 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE_MSB 13
1494 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE register field. */
1495 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE_WIDTH 1
1496 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE register field value. */
1497 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE_SET_MSK 0x00002000
1498 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE register field value. */
1499 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE_CLR_MSK 0xffffdfff
1500 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE register field. */
1501 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE_RESET 0x0
1502 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE field value from a register. */
1503 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE_GET(value) (((value) & 0x00002000) >> 13)
1504 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE register field value suitable for setting the register. */
1505 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE_SET(value) (((value) << 13) & 0x00002000)
1506 
1507 /*
1508  * Field : nonmpuregion6enable
1509  *
1510  * non MPU Region 6 Enable Clear.
1511  *
1512  * Writing zero has no effect
1513  *
1514  * Writing one will clear the region7enable bit to zero
1515  *
1516  * Field Access Macros:
1517  *
1518  */
1519 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE register field. */
1520 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE_LSB 14
1521 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE register field. */
1522 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE_MSB 14
1523 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE register field. */
1524 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE_WIDTH 1
1525 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE register field value. */
1526 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE_SET_MSK 0x00004000
1527 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE register field value. */
1528 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE_CLR_MSK 0xffffbfff
1529 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE register field. */
1530 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE_RESET 0x0
1531 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE field value from a register. */
1532 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE_GET(value) (((value) & 0x00004000) >> 14)
1533 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE register field value suitable for setting the register. */
1534 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE_SET(value) (((value) << 14) & 0x00004000)
1535 
1536 /*
1537  * Field : nonmpuregion7enable
1538  *
1539  * non MPU Region 7 Enable Clear.
1540  *
1541  * Writing zero has no effect
1542  *
1543  * Writing one will clear the region7enable bit to zero
1544  *
1545  * Field Access Macros:
1546  *
1547  */
1548 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE register field. */
1549 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE_LSB 15
1550 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE register field. */
1551 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE_MSB 15
1552 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE register field. */
1553 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE_WIDTH 1
1554 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE register field value. */
1555 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE_SET_MSK 0x00008000
1556 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE register field value. */
1557 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE_CLR_MSK 0xffff7fff
1558 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE register field. */
1559 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE_RESET 0x0
1560 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE field value from a register. */
1561 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE_GET(value) (((value) & 0x00008000) >> 15)
1562 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE register field value suitable for setting the register. */
1563 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE_SET(value) (((value) << 15) & 0x00008000)
1564 
1565 #ifndef __ASSEMBLY__
1566 /*
1567  * WARNING: The C register and register group struct declarations are provided for
1568  * convenience and illustrative purposes. They should, however, be used with
1569  * caution as the C language standard provides no guarantees about the alignment or
1570  * atomicity of device memory accesses. The recommended practice for coding device
1571  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1572  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1573  * alt_write_dword() functions for 64 bit registers.
1574  *
1575  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR.
1576  */
1577 struct ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_s
1578 {
1579  volatile uint32_t mpuregion0enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE */
1580  volatile uint32_t mpuregion1enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE */
1581  volatile uint32_t mpuregion2enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE */
1582  volatile uint32_t mpuregion3enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE */
1583  volatile uint32_t mpuregion4enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE */
1584  volatile uint32_t mpuregion5enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE */
1585  volatile uint32_t mpuregion6enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE */
1586  volatile uint32_t mpuregion7enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE */
1587  volatile uint32_t nonmpuregion0enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE */
1588  volatile uint32_t nonmpuregion1enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE */
1589  volatile uint32_t nonmpuregion2enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE */
1590  volatile uint32_t nonmpuregion3enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE */
1591  volatile uint32_t nonmpuregion4enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE */
1592  volatile uint32_t nonmpuregion5enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE */
1593  volatile uint32_t nonmpuregion6enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE */
1594  volatile uint32_t nonmpuregion7enable : 1; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE */
1595  uint32_t : 16; /* *UNDEFINED* */
1596 };
1597 
1598 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR. */
1599 typedef struct ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_s ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_t;
1600 #endif /* __ASSEMBLY__ */
1601 
1602 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR register. */
1603 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_RESET 0x00000000
1604 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR register from the beginning of the component. */
1605 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_OFST 0x8
1606 
1607 /*
1608  * Register : mpuregion0addr_base
1609  *
1610  * Base definition for MPU Region 0
1611  *
1612  * Register Layout
1613  *
1614  * Bits | Access | Reset | Description
1615  * :--------|:-------|:------|:------------------------------------------------
1616  * [15:0] | R | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW
1617  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH
1618  *
1619  */
1620 /*
1621  * Field : low
1622  *
1623  * LSB field is all zeros. Region start address is {baseext,base, 16'h000}
1624  *
1625  * Field Access Macros:
1626  *
1627  */
1628 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW register field. */
1629 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW_LSB 0
1630 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW register field. */
1631 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW_MSB 15
1632 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW register field. */
1633 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW_WIDTH 16
1634 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW register field value. */
1635 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW_SET_MSK 0x0000ffff
1636 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW register field value. */
1637 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW_CLR_MSK 0xffff0000
1638 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW register field. */
1639 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW_RESET 0x0
1640 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW field value from a register. */
1641 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
1642 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW register field value suitable for setting the register. */
1643 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
1644 
1645 /*
1646  * Field : high
1647  *
1648  * defines the 16 bit MSB of the base address field.
1649  *
1650  * Field Access Macros:
1651  *
1652  */
1653 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH register field. */
1654 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH_LSB 16
1655 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH register field. */
1656 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH_MSB 31
1657 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH register field. */
1658 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH_WIDTH 16
1659 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH register field value. */
1660 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH_SET_MSK 0xffff0000
1661 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH register field value. */
1662 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
1663 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH register field. */
1664 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH_RESET 0x0
1665 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH field value from a register. */
1666 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
1667 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH register field value suitable for setting the register. */
1668 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
1669 
1670 #ifndef __ASSEMBLY__
1671 /*
1672  * WARNING: The C register and register group struct declarations are provided for
1673  * convenience and illustrative purposes. They should, however, be used with
1674  * caution as the C language standard provides no guarantees about the alignment or
1675  * atomicity of device memory accesses. The recommended practice for coding device
1676  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1677  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1678  * alt_write_dword() functions for 64 bit registers.
1679  *
1680  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE.
1681  */
1682 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_s
1683 {
1684  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW */
1685  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH */
1686 };
1687 
1688 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE. */
1689 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_t;
1690 #endif /* __ASSEMBLY__ */
1691 
1692 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE register. */
1693 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_RESET 0x00000000
1694 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE register from the beginning of the component. */
1695 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_OFST 0x10
1696 
1697 /*
1698  * Register : mpuregion0addr_baseext
1699  *
1700  * base extended definition for MPU Region 0
1701  *
1702  * Register Layout
1703  *
1704  * Bits | Access | Reset | Description
1705  * :-------|:-------|:------|:--------------------------------------------------
1706  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW
1707  * [31:5] | ??? | 0x0 | *UNDEFINED*
1708  *
1709  */
1710 /*
1711  * Field : low
1712  *
1713  * defines the 5 bit LSB of the base extended address field.
1714  *
1715  * Field Access Macros:
1716  *
1717  */
1718 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW register field. */
1719 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW_LSB 0
1720 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW register field. */
1721 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW_MSB 4
1722 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW register field. */
1723 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW_WIDTH 5
1724 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW register field value. */
1725 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
1726 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW register field value. */
1727 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
1728 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW register field. */
1729 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW_RESET 0x0
1730 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW field value from a register. */
1731 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
1732 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW register field value suitable for setting the register. */
1733 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
1734 
1735 #ifndef __ASSEMBLY__
1736 /*
1737  * WARNING: The C register and register group struct declarations are provided for
1738  * convenience and illustrative purposes. They should, however, be used with
1739  * caution as the C language standard provides no guarantees about the alignment or
1740  * atomicity of device memory accesses. The recommended practice for coding device
1741  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1742  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1743  * alt_write_dword() functions for 64 bit registers.
1744  *
1745  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT.
1746  */
1747 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_s
1748 {
1749  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW */
1750  uint32_t : 27; /* *UNDEFINED* */
1751 };
1752 
1753 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT. */
1754 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_t;
1755 #endif /* __ASSEMBLY__ */
1756 
1757 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT register. */
1758 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_RESET 0x00000000
1759 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT register from the beginning of the component. */
1760 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_OFST 0x14
1761 
1762 /*
1763  * Register : mpuregion0addr_limit
1764  *
1765  * Limit definition for MPU Region 0
1766  *
1767  * Register Layout
1768  *
1769  * Bits | Access | Reset | Description
1770  * :--------|:-------|:-------|:-------------------------------------------------
1771  * [15:0] | R | 0xffff | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW
1772  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH
1773  *
1774  */
1775 /*
1776  * Field : low
1777  *
1778  * LSB field is all one. Region end address is {limitext,limit, 16'hFFFF}
1779  *
1780  * Field Access Macros:
1781  *
1782  */
1783 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW register field. */
1784 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW_LSB 0
1785 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW register field. */
1786 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW_MSB 15
1787 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW register field. */
1788 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW_WIDTH 16
1789 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW register field value. */
1790 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
1791 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW register field value. */
1792 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
1793 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW register field. */
1794 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW_RESET 0xffff
1795 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW field value from a register. */
1796 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
1797 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW register field value suitable for setting the register. */
1798 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
1799 
1800 /*
1801  * Field : high
1802  *
1803  * defines the 16 bit MSB of the limit address field.
1804  *
1805  * Field Access Macros:
1806  *
1807  */
1808 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH register field. */
1809 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH_LSB 16
1810 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH register field. */
1811 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH_MSB 31
1812 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH register field. */
1813 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH_WIDTH 16
1814 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH register field value. */
1815 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
1816 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH register field value. */
1817 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
1818 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH register field. */
1819 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH_RESET 0x0
1820 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH field value from a register. */
1821 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
1822 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH register field value suitable for setting the register. */
1823 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
1824 
1825 #ifndef __ASSEMBLY__
1826 /*
1827  * WARNING: The C register and register group struct declarations are provided for
1828  * convenience and illustrative purposes. They should, however, be used with
1829  * caution as the C language standard provides no guarantees about the alignment or
1830  * atomicity of device memory accesses. The recommended practice for coding device
1831  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1832  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1833  * alt_write_dword() functions for 64 bit registers.
1834  *
1835  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT.
1836  */
1837 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_s
1838 {
1839  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW */
1840  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH */
1841 };
1842 
1843 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT. */
1844 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_t;
1845 #endif /* __ASSEMBLY__ */
1846 
1847 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT register. */
1848 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_RESET 0x0000ffff
1849 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT register from the beginning of the component. */
1850 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_OFST 0x18
1851 
1852 /*
1853  * Register : mpuregion0addr_limitext
1854  *
1855  * limit extended definition for MPU Region 0
1856  *
1857  * Register Layout
1858  *
1859  * Bits | Access | Reset | Description
1860  * :-------|:-------|:------|:---------------------------------------------------
1861  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW
1862  * [31:5] | ??? | 0x0 | *UNDEFINED*
1863  *
1864  */
1865 /*
1866  * Field : low
1867  *
1868  * defines the 5 bit LSB of the limit extended address field.
1869  *
1870  * Field Access Macros:
1871  *
1872  */
1873 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW register field. */
1874 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW_LSB 0
1875 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW register field. */
1876 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW_MSB 4
1877 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW register field. */
1878 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW_WIDTH 5
1879 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW register field value. */
1880 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
1881 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW register field value. */
1882 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
1883 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW register field. */
1884 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW_RESET 0x0
1885 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW field value from a register. */
1886 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
1887 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW register field value suitable for setting the register. */
1888 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
1889 
1890 #ifndef __ASSEMBLY__
1891 /*
1892  * WARNING: The C register and register group struct declarations are provided for
1893  * convenience and illustrative purposes. They should, however, be used with
1894  * caution as the C language standard provides no guarantees about the alignment or
1895  * atomicity of device memory accesses. The recommended practice for coding device
1896  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1897  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1898  * alt_write_dword() functions for 64 bit registers.
1899  *
1900  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT.
1901  */
1902 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_s
1903 {
1904  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW */
1905  uint32_t : 27; /* *UNDEFINED* */
1906 };
1907 
1908 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT. */
1909 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_t;
1910 #endif /* __ASSEMBLY__ */
1911 
1912 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT register. */
1913 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_RESET 0x00000000
1914 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT register from the beginning of the component. */
1915 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_OFST 0x1c
1916 
1917 /*
1918  * Register : mpuregion1addr_base
1919  *
1920  * Base definition for MPU Region 1
1921  *
1922  * Register Layout
1923  *
1924  * Bits | Access | Reset | Description
1925  * :--------|:-------|:------|:------------------------------------------------
1926  * [15:0] | R | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW
1927  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH
1928  *
1929  */
1930 /*
1931  * Field : low
1932  *
1933  * LSB field is all zeros. Region start address is {baseext,base, 16'h000}
1934  *
1935  * Field Access Macros:
1936  *
1937  */
1938 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW register field. */
1939 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW_LSB 0
1940 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW register field. */
1941 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW_MSB 15
1942 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW register field. */
1943 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW_WIDTH 16
1944 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW register field value. */
1945 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW_SET_MSK 0x0000ffff
1946 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW register field value. */
1947 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW_CLR_MSK 0xffff0000
1948 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW register field. */
1949 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW_RESET 0x0
1950 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW field value from a register. */
1951 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
1952 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW register field value suitable for setting the register. */
1953 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
1954 
1955 /*
1956  * Field : high
1957  *
1958  * defines the 16 bit MSB of the base address field.
1959  *
1960  * Field Access Macros:
1961  *
1962  */
1963 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH register field. */
1964 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH_LSB 16
1965 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH register field. */
1966 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH_MSB 31
1967 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH register field. */
1968 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH_WIDTH 16
1969 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH register field value. */
1970 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH_SET_MSK 0xffff0000
1971 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH register field value. */
1972 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
1973 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH register field. */
1974 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH_RESET 0x0
1975 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH field value from a register. */
1976 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
1977 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH register field value suitable for setting the register. */
1978 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
1979 
1980 #ifndef __ASSEMBLY__
1981 /*
1982  * WARNING: The C register and register group struct declarations are provided for
1983  * convenience and illustrative purposes. They should, however, be used with
1984  * caution as the C language standard provides no guarantees about the alignment or
1985  * atomicity of device memory accesses. The recommended practice for coding device
1986  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1987  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1988  * alt_write_dword() functions for 64 bit registers.
1989  *
1990  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE.
1991  */
1992 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_s
1993 {
1994  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW */
1995  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH */
1996 };
1997 
1998 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE. */
1999 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_t;
2000 #endif /* __ASSEMBLY__ */
2001 
2002 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE register. */
2003 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_RESET 0x00000000
2004 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE register from the beginning of the component. */
2005 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_OFST 0x20
2006 
2007 /*
2008  * Register : mpuregion1addr_baseext
2009  *
2010  * base extended definition for MPU Region 1
2011  *
2012  * Register Layout
2013  *
2014  * Bits | Access | Reset | Description
2015  * :-------|:-------|:------|:--------------------------------------------------
2016  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW
2017  * [31:5] | ??? | 0x0 | *UNDEFINED*
2018  *
2019  */
2020 /*
2021  * Field : low
2022  *
2023  * defines the 5 bit LSB of the base extended address field.
2024  *
2025  * Field Access Macros:
2026  *
2027  */
2028 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW register field. */
2029 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW_LSB 0
2030 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW register field. */
2031 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW_MSB 4
2032 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW register field. */
2033 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW_WIDTH 5
2034 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW register field value. */
2035 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
2036 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW register field value. */
2037 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
2038 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW register field. */
2039 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW_RESET 0x0
2040 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW field value from a register. */
2041 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
2042 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW register field value suitable for setting the register. */
2043 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
2044 
2045 #ifndef __ASSEMBLY__
2046 /*
2047  * WARNING: The C register and register group struct declarations are provided for
2048  * convenience and illustrative purposes. They should, however, be used with
2049  * caution as the C language standard provides no guarantees about the alignment or
2050  * atomicity of device memory accesses. The recommended practice for coding device
2051  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2052  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2053  * alt_write_dword() functions for 64 bit registers.
2054  *
2055  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT.
2056  */
2057 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_s
2058 {
2059  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW */
2060  uint32_t : 27; /* *UNDEFINED* */
2061 };
2062 
2063 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT. */
2064 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_t;
2065 #endif /* __ASSEMBLY__ */
2066 
2067 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT register. */
2068 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_RESET 0x00000000
2069 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT register from the beginning of the component. */
2070 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_OFST 0x24
2071 
2072 /*
2073  * Register : mpuregion1addr_limit
2074  *
2075  * Limit definition for MPU Region 1
2076  *
2077  * Register Layout
2078  *
2079  * Bits | Access | Reset | Description
2080  * :--------|:-------|:-------|:-------------------------------------------------
2081  * [15:0] | R | 0xffff | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW
2082  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH
2083  *
2084  */
2085 /*
2086  * Field : low
2087  *
2088  * LSB field is all one. Region end address is {limitext,limit, 16'hFFFF}
2089  *
2090  * Field Access Macros:
2091  *
2092  */
2093 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW register field. */
2094 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW_LSB 0
2095 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW register field. */
2096 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW_MSB 15
2097 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW register field. */
2098 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW_WIDTH 16
2099 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW register field value. */
2100 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
2101 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW register field value. */
2102 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
2103 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW register field. */
2104 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW_RESET 0xffff
2105 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW field value from a register. */
2106 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
2107 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW register field value suitable for setting the register. */
2108 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
2109 
2110 /*
2111  * Field : high
2112  *
2113  * defines the 16 bit MSB of the limit address field.
2114  *
2115  * Field Access Macros:
2116  *
2117  */
2118 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH register field. */
2119 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH_LSB 16
2120 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH register field. */
2121 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH_MSB 31
2122 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH register field. */
2123 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH_WIDTH 16
2124 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH register field value. */
2125 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
2126 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH register field value. */
2127 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
2128 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH register field. */
2129 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH_RESET 0x0
2130 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH field value from a register. */
2131 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
2132 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH register field value suitable for setting the register. */
2133 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
2134 
2135 #ifndef __ASSEMBLY__
2136 /*
2137  * WARNING: The C register and register group struct declarations are provided for
2138  * convenience and illustrative purposes. They should, however, be used with
2139  * caution as the C language standard provides no guarantees about the alignment or
2140  * atomicity of device memory accesses. The recommended practice for coding device
2141  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2142  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2143  * alt_write_dword() functions for 64 bit registers.
2144  *
2145  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT.
2146  */
2147 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_s
2148 {
2149  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW */
2150  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH */
2151 };
2152 
2153 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT. */
2154 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_t;
2155 #endif /* __ASSEMBLY__ */
2156 
2157 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT register. */
2158 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_RESET 0x0000ffff
2159 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT register from the beginning of the component. */
2160 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_OFST 0x28
2161 
2162 /*
2163  * Register : mpuregion1addr_limitext
2164  *
2165  * limit extended definition for MPU Region 1
2166  *
2167  * Register Layout
2168  *
2169  * Bits | Access | Reset | Description
2170  * :-------|:-------|:------|:---------------------------------------------------
2171  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW
2172  * [31:5] | ??? | 0x0 | *UNDEFINED*
2173  *
2174  */
2175 /*
2176  * Field : low
2177  *
2178  * defines the 5 bit LSB of the limit extended address field.
2179  *
2180  * Field Access Macros:
2181  *
2182  */
2183 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW register field. */
2184 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW_LSB 0
2185 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW register field. */
2186 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW_MSB 4
2187 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW register field. */
2188 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW_WIDTH 5
2189 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW register field value. */
2190 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
2191 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW register field value. */
2192 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
2193 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW register field. */
2194 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW_RESET 0x0
2195 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW field value from a register. */
2196 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
2197 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW register field value suitable for setting the register. */
2198 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
2199 
2200 #ifndef __ASSEMBLY__
2201 /*
2202  * WARNING: The C register and register group struct declarations are provided for
2203  * convenience and illustrative purposes. They should, however, be used with
2204  * caution as the C language standard provides no guarantees about the alignment or
2205  * atomicity of device memory accesses. The recommended practice for coding device
2206  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2207  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2208  * alt_write_dword() functions for 64 bit registers.
2209  *
2210  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT.
2211  */
2212 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_s
2213 {
2214  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW */
2215  uint32_t : 27; /* *UNDEFINED* */
2216 };
2217 
2218 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT. */
2219 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_t;
2220 #endif /* __ASSEMBLY__ */
2221 
2222 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT register. */
2223 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_RESET 0x00000000
2224 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT register from the beginning of the component. */
2225 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_OFST 0x2c
2226 
2227 /*
2228  * Register : mpuregion2addr_base
2229  *
2230  * Base definition for MPU Region 2
2231  *
2232  * Register Layout
2233  *
2234  * Bits | Access | Reset | Description
2235  * :--------|:-------|:------|:------------------------------------------------
2236  * [15:0] | R | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW
2237  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH
2238  *
2239  */
2240 /*
2241  * Field : low
2242  *
2243  * LSB field is all zeros. Region start address is {baseext,base, 16'h000}
2244  *
2245  * Field Access Macros:
2246  *
2247  */
2248 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW register field. */
2249 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW_LSB 0
2250 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW register field. */
2251 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW_MSB 15
2252 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW register field. */
2253 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW_WIDTH 16
2254 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW register field value. */
2255 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW_SET_MSK 0x0000ffff
2256 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW register field value. */
2257 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW_CLR_MSK 0xffff0000
2258 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW register field. */
2259 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW_RESET 0x0
2260 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW field value from a register. */
2261 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
2262 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW register field value suitable for setting the register. */
2263 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
2264 
2265 /*
2266  * Field : high
2267  *
2268  * defines the 16 bit MSB of the base address field.
2269  *
2270  * Field Access Macros:
2271  *
2272  */
2273 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH register field. */
2274 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH_LSB 16
2275 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH register field. */
2276 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH_MSB 31
2277 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH register field. */
2278 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH_WIDTH 16
2279 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH register field value. */
2280 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH_SET_MSK 0xffff0000
2281 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH register field value. */
2282 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
2283 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH register field. */
2284 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH_RESET 0x0
2285 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH field value from a register. */
2286 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
2287 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH register field value suitable for setting the register. */
2288 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
2289 
2290 #ifndef __ASSEMBLY__
2291 /*
2292  * WARNING: The C register and register group struct declarations are provided for
2293  * convenience and illustrative purposes. They should, however, be used with
2294  * caution as the C language standard provides no guarantees about the alignment or
2295  * atomicity of device memory accesses. The recommended practice for coding device
2296  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2297  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2298  * alt_write_dword() functions for 64 bit registers.
2299  *
2300  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE.
2301  */
2302 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_s
2303 {
2304  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW */
2305  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH */
2306 };
2307 
2308 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE. */
2309 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_t;
2310 #endif /* __ASSEMBLY__ */
2311 
2312 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE register. */
2313 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_RESET 0x00000000
2314 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE register from the beginning of the component. */
2315 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_OFST 0x30
2316 
2317 /*
2318  * Register : mpuregion2addr_baseext
2319  *
2320  * base extended definition for MPU Region 2
2321  *
2322  * Register Layout
2323  *
2324  * Bits | Access | Reset | Description
2325  * :-------|:-------|:------|:--------------------------------------------------
2326  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW
2327  * [31:5] | ??? | 0x0 | *UNDEFINED*
2328  *
2329  */
2330 /*
2331  * Field : low
2332  *
2333  * defines the 5 bit LSB of the base extended address field.
2334  *
2335  * Field Access Macros:
2336  *
2337  */
2338 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW register field. */
2339 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW_LSB 0
2340 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW register field. */
2341 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW_MSB 4
2342 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW register field. */
2343 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW_WIDTH 5
2344 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW register field value. */
2345 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
2346 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW register field value. */
2347 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
2348 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW register field. */
2349 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW_RESET 0x0
2350 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW field value from a register. */
2351 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
2352 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW register field value suitable for setting the register. */
2353 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
2354 
2355 #ifndef __ASSEMBLY__
2356 /*
2357  * WARNING: The C register and register group struct declarations are provided for
2358  * convenience and illustrative purposes. They should, however, be used with
2359  * caution as the C language standard provides no guarantees about the alignment or
2360  * atomicity of device memory accesses. The recommended practice for coding device
2361  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2362  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2363  * alt_write_dword() functions for 64 bit registers.
2364  *
2365  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT.
2366  */
2367 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_s
2368 {
2369  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW */
2370  uint32_t : 27; /* *UNDEFINED* */
2371 };
2372 
2373 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT. */
2374 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_t;
2375 #endif /* __ASSEMBLY__ */
2376 
2377 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT register. */
2378 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_RESET 0x00000000
2379 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT register from the beginning of the component. */
2380 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_OFST 0x34
2381 
2382 /*
2383  * Register : mpuregion2addr_limit
2384  *
2385  * Limit definition for MPU Region 2
2386  *
2387  * Register Layout
2388  *
2389  * Bits | Access | Reset | Description
2390  * :--------|:-------|:-------|:-------------------------------------------------
2391  * [15:0] | R | 0xffff | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW
2392  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH
2393  *
2394  */
2395 /*
2396  * Field : low
2397  *
2398  * LSB field is all one. Region end address is {limitext,limit, 16'hFFFF}
2399  *
2400  * Field Access Macros:
2401  *
2402  */
2403 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW register field. */
2404 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW_LSB 0
2405 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW register field. */
2406 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW_MSB 15
2407 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW register field. */
2408 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW_WIDTH 16
2409 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW register field value. */
2410 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
2411 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW register field value. */
2412 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
2413 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW register field. */
2414 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW_RESET 0xffff
2415 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW field value from a register. */
2416 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
2417 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW register field value suitable for setting the register. */
2418 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
2419 
2420 /*
2421  * Field : high
2422  *
2423  * defines the 16 bit MSB of the limit address field.
2424  *
2425  * Field Access Macros:
2426  *
2427  */
2428 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH register field. */
2429 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH_LSB 16
2430 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH register field. */
2431 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH_MSB 31
2432 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH register field. */
2433 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH_WIDTH 16
2434 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH register field value. */
2435 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
2436 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH register field value. */
2437 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
2438 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH register field. */
2439 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH_RESET 0x0
2440 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH field value from a register. */
2441 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
2442 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH register field value suitable for setting the register. */
2443 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
2444 
2445 #ifndef __ASSEMBLY__
2446 /*
2447  * WARNING: The C register and register group struct declarations are provided for
2448  * convenience and illustrative purposes. They should, however, be used with
2449  * caution as the C language standard provides no guarantees about the alignment or
2450  * atomicity of device memory accesses. The recommended practice for coding device
2451  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2452  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2453  * alt_write_dword() functions for 64 bit registers.
2454  *
2455  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT.
2456  */
2457 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_s
2458 {
2459  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW */
2460  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH */
2461 };
2462 
2463 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT. */
2464 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_t;
2465 #endif /* __ASSEMBLY__ */
2466 
2467 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT register. */
2468 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_RESET 0x0000ffff
2469 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT register from the beginning of the component. */
2470 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_OFST 0x38
2471 
2472 /*
2473  * Register : mpuregion2addr_limitext
2474  *
2475  * limit extended definition for MPU Region 2
2476  *
2477  * Register Layout
2478  *
2479  * Bits | Access | Reset | Description
2480  * :-------|:-------|:------|:---------------------------------------------------
2481  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW
2482  * [31:5] | ??? | 0x0 | *UNDEFINED*
2483  *
2484  */
2485 /*
2486  * Field : low
2487  *
2488  * defines the 5 bit LSB of the limit extended address field.
2489  *
2490  * Field Access Macros:
2491  *
2492  */
2493 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW register field. */
2494 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW_LSB 0
2495 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW register field. */
2496 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW_MSB 4
2497 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW register field. */
2498 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW_WIDTH 5
2499 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW register field value. */
2500 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
2501 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW register field value. */
2502 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
2503 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW register field. */
2504 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW_RESET 0x0
2505 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW field value from a register. */
2506 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
2507 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW register field value suitable for setting the register. */
2508 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
2509 
2510 #ifndef __ASSEMBLY__
2511 /*
2512  * WARNING: The C register and register group struct declarations are provided for
2513  * convenience and illustrative purposes. They should, however, be used with
2514  * caution as the C language standard provides no guarantees about the alignment or
2515  * atomicity of device memory accesses. The recommended practice for coding device
2516  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2517  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2518  * alt_write_dword() functions for 64 bit registers.
2519  *
2520  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT.
2521  */
2522 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_s
2523 {
2524  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW */
2525  uint32_t : 27; /* *UNDEFINED* */
2526 };
2527 
2528 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT. */
2529 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_t;
2530 #endif /* __ASSEMBLY__ */
2531 
2532 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT register. */
2533 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_RESET 0x00000000
2534 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT register from the beginning of the component. */
2535 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_OFST 0x3c
2536 
2537 /*
2538  * Register : mpuregion3addr_base
2539  *
2540  * Base definition for MPU Region 3
2541  *
2542  * Register Layout
2543  *
2544  * Bits | Access | Reset | Description
2545  * :--------|:-------|:------|:------------------------------------------------
2546  * [15:0] | R | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW
2547  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH
2548  *
2549  */
2550 /*
2551  * Field : low
2552  *
2553  * LSB field is all zeros. Region start address is {baseext,base, 16'h000}
2554  *
2555  * Field Access Macros:
2556  *
2557  */
2558 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW register field. */
2559 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW_LSB 0
2560 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW register field. */
2561 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW_MSB 15
2562 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW register field. */
2563 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW_WIDTH 16
2564 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW register field value. */
2565 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW_SET_MSK 0x0000ffff
2566 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW register field value. */
2567 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW_CLR_MSK 0xffff0000
2568 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW register field. */
2569 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW_RESET 0x0
2570 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW field value from a register. */
2571 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
2572 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW register field value suitable for setting the register. */
2573 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
2574 
2575 /*
2576  * Field : high
2577  *
2578  * defines the 16 bit MSB of the base address field.
2579  *
2580  * Field Access Macros:
2581  *
2582  */
2583 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH register field. */
2584 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH_LSB 16
2585 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH register field. */
2586 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH_MSB 31
2587 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH register field. */
2588 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH_WIDTH 16
2589 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH register field value. */
2590 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH_SET_MSK 0xffff0000
2591 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH register field value. */
2592 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
2593 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH register field. */
2594 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH_RESET 0x0
2595 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH field value from a register. */
2596 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
2597 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH register field value suitable for setting the register. */
2598 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
2599 
2600 #ifndef __ASSEMBLY__
2601 /*
2602  * WARNING: The C register and register group struct declarations are provided for
2603  * convenience and illustrative purposes. They should, however, be used with
2604  * caution as the C language standard provides no guarantees about the alignment or
2605  * atomicity of device memory accesses. The recommended practice for coding device
2606  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2607  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2608  * alt_write_dword() functions for 64 bit registers.
2609  *
2610  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE.
2611  */
2612 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_s
2613 {
2614  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW */
2615  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH */
2616 };
2617 
2618 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE. */
2619 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_t;
2620 #endif /* __ASSEMBLY__ */
2621 
2622 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE register. */
2623 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_RESET 0x00000000
2624 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE register from the beginning of the component. */
2625 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_OFST 0x40
2626 
2627 /*
2628  * Register : mpuregion3addr_baseext
2629  *
2630  * base extended definition for MPU Region 3
2631  *
2632  * Register Layout
2633  *
2634  * Bits | Access | Reset | Description
2635  * :-------|:-------|:------|:--------------------------------------------------
2636  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW
2637  * [31:5] | ??? | 0x0 | *UNDEFINED*
2638  *
2639  */
2640 /*
2641  * Field : low
2642  *
2643  * defines the 5 bit LSB of the base extended address field.
2644  *
2645  * Field Access Macros:
2646  *
2647  */
2648 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW register field. */
2649 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW_LSB 0
2650 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW register field. */
2651 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW_MSB 4
2652 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW register field. */
2653 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW_WIDTH 5
2654 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW register field value. */
2655 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
2656 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW register field value. */
2657 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
2658 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW register field. */
2659 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW_RESET 0x0
2660 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW field value from a register. */
2661 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
2662 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW register field value suitable for setting the register. */
2663 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
2664 
2665 #ifndef __ASSEMBLY__
2666 /*
2667  * WARNING: The C register and register group struct declarations are provided for
2668  * convenience and illustrative purposes. They should, however, be used with
2669  * caution as the C language standard provides no guarantees about the alignment or
2670  * atomicity of device memory accesses. The recommended practice for coding device
2671  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2672  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2673  * alt_write_dword() functions for 64 bit registers.
2674  *
2675  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT.
2676  */
2677 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_s
2678 {
2679  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW */
2680  uint32_t : 27; /* *UNDEFINED* */
2681 };
2682 
2683 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT. */
2684 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_t;
2685 #endif /* __ASSEMBLY__ */
2686 
2687 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT register. */
2688 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_RESET 0x00000000
2689 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT register from the beginning of the component. */
2690 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_OFST 0x44
2691 
2692 /*
2693  * Register : mpuregion3addr_limit
2694  *
2695  * Limit definition for MPU Region 3
2696  *
2697  * Register Layout
2698  *
2699  * Bits | Access | Reset | Description
2700  * :--------|:-------|:-------|:-------------------------------------------------
2701  * [15:0] | R | 0xffff | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW
2702  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH
2703  *
2704  */
2705 /*
2706  * Field : low
2707  *
2708  * LSB field is all one. Region end address is {limitext,limit, 16'hFFFF}
2709  *
2710  * Field Access Macros:
2711  *
2712  */
2713 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW register field. */
2714 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW_LSB 0
2715 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW register field. */
2716 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW_MSB 15
2717 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW register field. */
2718 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW_WIDTH 16
2719 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW register field value. */
2720 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
2721 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW register field value. */
2722 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
2723 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW register field. */
2724 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW_RESET 0xffff
2725 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW field value from a register. */
2726 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
2727 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW register field value suitable for setting the register. */
2728 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
2729 
2730 /*
2731  * Field : high
2732  *
2733  * defines the 16 bit MSB of the limit address field.
2734  *
2735  * Field Access Macros:
2736  *
2737  */
2738 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH register field. */
2739 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH_LSB 16
2740 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH register field. */
2741 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH_MSB 31
2742 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH register field. */
2743 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH_WIDTH 16
2744 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH register field value. */
2745 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
2746 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH register field value. */
2747 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
2748 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH register field. */
2749 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH_RESET 0x0
2750 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH field value from a register. */
2751 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
2752 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH register field value suitable for setting the register. */
2753 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
2754 
2755 #ifndef __ASSEMBLY__
2756 /*
2757  * WARNING: The C register and register group struct declarations are provided for
2758  * convenience and illustrative purposes. They should, however, be used with
2759  * caution as the C language standard provides no guarantees about the alignment or
2760  * atomicity of device memory accesses. The recommended practice for coding device
2761  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2762  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2763  * alt_write_dword() functions for 64 bit registers.
2764  *
2765  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT.
2766  */
2767 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_s
2768 {
2769  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW */
2770  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH */
2771 };
2772 
2773 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT. */
2774 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_t;
2775 #endif /* __ASSEMBLY__ */
2776 
2777 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT register. */
2778 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_RESET 0x0000ffff
2779 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT register from the beginning of the component. */
2780 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_OFST 0x48
2781 
2782 /*
2783  * Register : mpuregion3addr_limitext
2784  *
2785  * limit extended definition for MPU Region 3
2786  *
2787  * Register Layout
2788  *
2789  * Bits | Access | Reset | Description
2790  * :-------|:-------|:------|:---------------------------------------------------
2791  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW
2792  * [31:5] | ??? | 0x0 | *UNDEFINED*
2793  *
2794  */
2795 /*
2796  * Field : low
2797  *
2798  * defines the 5 bit LSB of the limit extended address field.
2799  *
2800  * Field Access Macros:
2801  *
2802  */
2803 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW register field. */
2804 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW_LSB 0
2805 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW register field. */
2806 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW_MSB 4
2807 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW register field. */
2808 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW_WIDTH 5
2809 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW register field value. */
2810 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
2811 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW register field value. */
2812 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
2813 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW register field. */
2814 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW_RESET 0x0
2815 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW field value from a register. */
2816 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
2817 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW register field value suitable for setting the register. */
2818 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
2819 
2820 #ifndef __ASSEMBLY__
2821 /*
2822  * WARNING: The C register and register group struct declarations are provided for
2823  * convenience and illustrative purposes. They should, however, be used with
2824  * caution as the C language standard provides no guarantees about the alignment or
2825  * atomicity of device memory accesses. The recommended practice for coding device
2826  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2827  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2828  * alt_write_dword() functions for 64 bit registers.
2829  *
2830  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT.
2831  */
2832 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_s
2833 {
2834  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW */
2835  uint32_t : 27; /* *UNDEFINED* */
2836 };
2837 
2838 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT. */
2839 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_t;
2840 #endif /* __ASSEMBLY__ */
2841 
2842 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT register. */
2843 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_RESET 0x00000000
2844 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT register from the beginning of the component. */
2845 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_OFST 0x4c
2846 
2847 /*
2848  * Register : mpuregion4addr_base
2849  *
2850  * Base definition for MPU Region 4
2851  *
2852  * Register Layout
2853  *
2854  * Bits | Access | Reset | Description
2855  * :--------|:-------|:------|:------------------------------------------------
2856  * [15:0] | R | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW
2857  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH
2858  *
2859  */
2860 /*
2861  * Field : low
2862  *
2863  * LSB field is all zeros. Region start address is {baseext,base, 16'h000}
2864  *
2865  * Field Access Macros:
2866  *
2867  */
2868 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW register field. */
2869 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW_LSB 0
2870 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW register field. */
2871 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW_MSB 15
2872 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW register field. */
2873 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW_WIDTH 16
2874 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW register field value. */
2875 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW_SET_MSK 0x0000ffff
2876 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW register field value. */
2877 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW_CLR_MSK 0xffff0000
2878 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW register field. */
2879 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW_RESET 0x0
2880 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW field value from a register. */
2881 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
2882 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW register field value suitable for setting the register. */
2883 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
2884 
2885 /*
2886  * Field : high
2887  *
2888  * defines the 16 bit MSB of the base address field.
2889  *
2890  * Field Access Macros:
2891  *
2892  */
2893 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH register field. */
2894 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH_LSB 16
2895 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH register field. */
2896 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH_MSB 31
2897 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH register field. */
2898 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH_WIDTH 16
2899 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH register field value. */
2900 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH_SET_MSK 0xffff0000
2901 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH register field value. */
2902 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
2903 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH register field. */
2904 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH_RESET 0x0
2905 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH field value from a register. */
2906 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
2907 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH register field value suitable for setting the register. */
2908 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
2909 
2910 #ifndef __ASSEMBLY__
2911 /*
2912  * WARNING: The C register and register group struct declarations are provided for
2913  * convenience and illustrative purposes. They should, however, be used with
2914  * caution as the C language standard provides no guarantees about the alignment or
2915  * atomicity of device memory accesses. The recommended practice for coding device
2916  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2917  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2918  * alt_write_dword() functions for 64 bit registers.
2919  *
2920  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE.
2921  */
2922 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_s
2923 {
2924  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW */
2925  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH */
2926 };
2927 
2928 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE. */
2929 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_t;
2930 #endif /* __ASSEMBLY__ */
2931 
2932 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE register. */
2933 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_RESET 0x00000000
2934 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE register from the beginning of the component. */
2935 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_OFST 0x50
2936 
2937 /*
2938  * Register : mpuregion4addr_baseext
2939  *
2940  * base extended definition for MPU Region 4
2941  *
2942  * Register Layout
2943  *
2944  * Bits | Access | Reset | Description
2945  * :-------|:-------|:------|:--------------------------------------------------
2946  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW
2947  * [31:5] | ??? | 0x0 | *UNDEFINED*
2948  *
2949  */
2950 /*
2951  * Field : low
2952  *
2953  * defines the 5 bit LSB of the base extended address field.
2954  *
2955  * Field Access Macros:
2956  *
2957  */
2958 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW register field. */
2959 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW_LSB 0
2960 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW register field. */
2961 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW_MSB 4
2962 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW register field. */
2963 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW_WIDTH 5
2964 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW register field value. */
2965 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
2966 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW register field value. */
2967 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
2968 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW register field. */
2969 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW_RESET 0x0
2970 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW field value from a register. */
2971 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
2972 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW register field value suitable for setting the register. */
2973 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
2974 
2975 #ifndef __ASSEMBLY__
2976 /*
2977  * WARNING: The C register and register group struct declarations are provided for
2978  * convenience and illustrative purposes. They should, however, be used with
2979  * caution as the C language standard provides no guarantees about the alignment or
2980  * atomicity of device memory accesses. The recommended practice for coding device
2981  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2982  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2983  * alt_write_dword() functions for 64 bit registers.
2984  *
2985  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT.
2986  */
2987 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_s
2988 {
2989  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW */
2990  uint32_t : 27; /* *UNDEFINED* */
2991 };
2992 
2993 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT. */
2994 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_t;
2995 #endif /* __ASSEMBLY__ */
2996 
2997 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT register. */
2998 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_RESET 0x00000000
2999 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT register from the beginning of the component. */
3000 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_OFST 0x54
3001 
3002 /*
3003  * Register : mpuregion4addr_limit
3004  *
3005  * Limit definition for MPU Region 4
3006  *
3007  * Register Layout
3008  *
3009  * Bits | Access | Reset | Description
3010  * :--------|:-------|:-------|:-------------------------------------------------
3011  * [15:0] | R | 0xffff | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW
3012  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH
3013  *
3014  */
3015 /*
3016  * Field : low
3017  *
3018  * LSB field is all one. Region end address is {limitext,limit, 16'hFFFF}
3019  *
3020  * Field Access Macros:
3021  *
3022  */
3023 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW register field. */
3024 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW_LSB 0
3025 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW register field. */
3026 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW_MSB 15
3027 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW register field. */
3028 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW_WIDTH 16
3029 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW register field value. */
3030 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
3031 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW register field value. */
3032 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
3033 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW register field. */
3034 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW_RESET 0xffff
3035 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW field value from a register. */
3036 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
3037 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW register field value suitable for setting the register. */
3038 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
3039 
3040 /*
3041  * Field : high
3042  *
3043  * defines the 16 bit MSB of the limit address field.
3044  *
3045  * Field Access Macros:
3046  *
3047  */
3048 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH register field. */
3049 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH_LSB 16
3050 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH register field. */
3051 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH_MSB 31
3052 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH register field. */
3053 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH_WIDTH 16
3054 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH register field value. */
3055 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
3056 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH register field value. */
3057 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
3058 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH register field. */
3059 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH_RESET 0x0
3060 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH field value from a register. */
3061 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
3062 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH register field value suitable for setting the register. */
3063 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
3064 
3065 #ifndef __ASSEMBLY__
3066 /*
3067  * WARNING: The C register and register group struct declarations are provided for
3068  * convenience and illustrative purposes. They should, however, be used with
3069  * caution as the C language standard provides no guarantees about the alignment or
3070  * atomicity of device memory accesses. The recommended practice for coding device
3071  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3072  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3073  * alt_write_dword() functions for 64 bit registers.
3074  *
3075  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT.
3076  */
3077 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_s
3078 {
3079  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW */
3080  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH */
3081 };
3082 
3083 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT. */
3084 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_t;
3085 #endif /* __ASSEMBLY__ */
3086 
3087 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT register. */
3088 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_RESET 0x0000ffff
3089 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT register from the beginning of the component. */
3090 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_OFST 0x58
3091 
3092 /*
3093  * Register : mpuregion4addr_limitext
3094  *
3095  * limit extended definition for MPU Region 4
3096  *
3097  * Register Layout
3098  *
3099  * Bits | Access | Reset | Description
3100  * :-------|:-------|:------|:---------------------------------------------------
3101  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW
3102  * [31:5] | ??? | 0x0 | *UNDEFINED*
3103  *
3104  */
3105 /*
3106  * Field : low
3107  *
3108  * defines the 5 bit LSB of the limit extended address field.
3109  *
3110  * Field Access Macros:
3111  *
3112  */
3113 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW register field. */
3114 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW_LSB 0
3115 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW register field. */
3116 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW_MSB 4
3117 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW register field. */
3118 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW_WIDTH 5
3119 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW register field value. */
3120 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
3121 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW register field value. */
3122 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
3123 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW register field. */
3124 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW_RESET 0x0
3125 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW field value from a register. */
3126 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
3127 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW register field value suitable for setting the register. */
3128 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
3129 
3130 #ifndef __ASSEMBLY__
3131 /*
3132  * WARNING: The C register and register group struct declarations are provided for
3133  * convenience and illustrative purposes. They should, however, be used with
3134  * caution as the C language standard provides no guarantees about the alignment or
3135  * atomicity of device memory accesses. The recommended practice for coding device
3136  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3137  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3138  * alt_write_dword() functions for 64 bit registers.
3139  *
3140  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT.
3141  */
3142 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_s
3143 {
3144  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW */
3145  uint32_t : 27; /* *UNDEFINED* */
3146 };
3147 
3148 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT. */
3149 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_t;
3150 #endif /* __ASSEMBLY__ */
3151 
3152 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT register. */
3153 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_RESET 0x00000000
3154 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT register from the beginning of the component. */
3155 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_OFST 0x5c
3156 
3157 /*
3158  * Register : mpuregion5addr_base
3159  *
3160  * Base definition for MPU Region 5
3161  *
3162  * Register Layout
3163  *
3164  * Bits | Access | Reset | Description
3165  * :--------|:-------|:------|:------------------------------------------------
3166  * [15:0] | R | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW
3167  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH
3168  *
3169  */
3170 /*
3171  * Field : low
3172  *
3173  * LSB field is all zeros. Region start address is {baseext,base, 16'h000}
3174  *
3175  * Field Access Macros:
3176  *
3177  */
3178 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW register field. */
3179 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW_LSB 0
3180 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW register field. */
3181 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW_MSB 15
3182 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW register field. */
3183 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW_WIDTH 16
3184 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW register field value. */
3185 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW_SET_MSK 0x0000ffff
3186 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW register field value. */
3187 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW_CLR_MSK 0xffff0000
3188 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW register field. */
3189 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW_RESET 0x0
3190 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW field value from a register. */
3191 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
3192 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW register field value suitable for setting the register. */
3193 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
3194 
3195 /*
3196  * Field : high
3197  *
3198  * defines the 16 bit MSB of the base address field.
3199  *
3200  * Field Access Macros:
3201  *
3202  */
3203 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH register field. */
3204 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH_LSB 16
3205 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH register field. */
3206 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH_MSB 31
3207 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH register field. */
3208 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH_WIDTH 16
3209 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH register field value. */
3210 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH_SET_MSK 0xffff0000
3211 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH register field value. */
3212 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
3213 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH register field. */
3214 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH_RESET 0x0
3215 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH field value from a register. */
3216 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
3217 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH register field value suitable for setting the register. */
3218 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
3219 
3220 #ifndef __ASSEMBLY__
3221 /*
3222  * WARNING: The C register and register group struct declarations are provided for
3223  * convenience and illustrative purposes. They should, however, be used with
3224  * caution as the C language standard provides no guarantees about the alignment or
3225  * atomicity of device memory accesses. The recommended practice for coding device
3226  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3227  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3228  * alt_write_dword() functions for 64 bit registers.
3229  *
3230  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE.
3231  */
3232 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_s
3233 {
3234  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW */
3235  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH */
3236 };
3237 
3238 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE. */
3239 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_t;
3240 #endif /* __ASSEMBLY__ */
3241 
3242 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE register. */
3243 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_RESET 0x00000000
3244 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE register from the beginning of the component. */
3245 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_OFST 0x60
3246 
3247 /*
3248  * Register : mpuregion5addr_baseext
3249  *
3250  * base extended definition for MPU Region 5
3251  *
3252  * Register Layout
3253  *
3254  * Bits | Access | Reset | Description
3255  * :-------|:-------|:------|:--------------------------------------------------
3256  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW
3257  * [31:5] | ??? | 0x0 | *UNDEFINED*
3258  *
3259  */
3260 /*
3261  * Field : low
3262  *
3263  * defines the 5 bit LSB of the base extended address field.
3264  *
3265  * Field Access Macros:
3266  *
3267  */
3268 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW register field. */
3269 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW_LSB 0
3270 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW register field. */
3271 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW_MSB 4
3272 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW register field. */
3273 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW_WIDTH 5
3274 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW register field value. */
3275 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
3276 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW register field value. */
3277 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
3278 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW register field. */
3279 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW_RESET 0x0
3280 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW field value from a register. */
3281 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
3282 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW register field value suitable for setting the register. */
3283 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
3284 
3285 #ifndef __ASSEMBLY__
3286 /*
3287  * WARNING: The C register and register group struct declarations are provided for
3288  * convenience and illustrative purposes. They should, however, be used with
3289  * caution as the C language standard provides no guarantees about the alignment or
3290  * atomicity of device memory accesses. The recommended practice for coding device
3291  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3292  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3293  * alt_write_dword() functions for 64 bit registers.
3294  *
3295  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT.
3296  */
3297 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_s
3298 {
3299  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW */
3300  uint32_t : 27; /* *UNDEFINED* */
3301 };
3302 
3303 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT. */
3304 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_t;
3305 #endif /* __ASSEMBLY__ */
3306 
3307 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT register. */
3308 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_RESET 0x00000000
3309 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT register from the beginning of the component. */
3310 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_OFST 0x64
3311 
3312 /*
3313  * Register : mpuregion5addr_limit
3314  *
3315  * Limit definition for MPU Region 5
3316  *
3317  * Register Layout
3318  *
3319  * Bits | Access | Reset | Description
3320  * :--------|:-------|:-------|:-------------------------------------------------
3321  * [15:0] | R | 0xffff | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW
3322  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH
3323  *
3324  */
3325 /*
3326  * Field : low
3327  *
3328  * LSB field is all one. Region end address is {limitext,limit, 16'hFFFF}
3329  *
3330  * Field Access Macros:
3331  *
3332  */
3333 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW register field. */
3334 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW_LSB 0
3335 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW register field. */
3336 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW_MSB 15
3337 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW register field. */
3338 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW_WIDTH 16
3339 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW register field value. */
3340 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
3341 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW register field value. */
3342 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
3343 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW register field. */
3344 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW_RESET 0xffff
3345 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW field value from a register. */
3346 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
3347 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW register field value suitable for setting the register. */
3348 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
3349 
3350 /*
3351  * Field : high
3352  *
3353  * defines the 16 bit MSB of the limit address field.
3354  *
3355  * Field Access Macros:
3356  *
3357  */
3358 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH register field. */
3359 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH_LSB 16
3360 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH register field. */
3361 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH_MSB 31
3362 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH register field. */
3363 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH_WIDTH 16
3364 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH register field value. */
3365 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
3366 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH register field value. */
3367 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
3368 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH register field. */
3369 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH_RESET 0x0
3370 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH field value from a register. */
3371 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
3372 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH register field value suitable for setting the register. */
3373 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
3374 
3375 #ifndef __ASSEMBLY__
3376 /*
3377  * WARNING: The C register and register group struct declarations are provided for
3378  * convenience and illustrative purposes. They should, however, be used with
3379  * caution as the C language standard provides no guarantees about the alignment or
3380  * atomicity of device memory accesses. The recommended practice for coding device
3381  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3382  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3383  * alt_write_dword() functions for 64 bit registers.
3384  *
3385  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT.
3386  */
3387 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_s
3388 {
3389  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW */
3390  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH */
3391 };
3392 
3393 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT. */
3394 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_t;
3395 #endif /* __ASSEMBLY__ */
3396 
3397 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT register. */
3398 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_RESET 0x0000ffff
3399 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT register from the beginning of the component. */
3400 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_OFST 0x68
3401 
3402 /*
3403  * Register : mpuregion5addr_limitext
3404  *
3405  * limit extended definition for MPU Region 5
3406  *
3407  * Register Layout
3408  *
3409  * Bits | Access | Reset | Description
3410  * :-------|:-------|:------|:---------------------------------------------------
3411  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW
3412  * [31:5] | ??? | 0x0 | *UNDEFINED*
3413  *
3414  */
3415 /*
3416  * Field : low
3417  *
3418  * defines the 5 bit LSB of the limit extended address field.
3419  *
3420  * Field Access Macros:
3421  *
3422  */
3423 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW register field. */
3424 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW_LSB 0
3425 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW register field. */
3426 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW_MSB 4
3427 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW register field. */
3428 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW_WIDTH 5
3429 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW register field value. */
3430 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
3431 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW register field value. */
3432 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
3433 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW register field. */
3434 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW_RESET 0x0
3435 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW field value from a register. */
3436 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
3437 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW register field value suitable for setting the register. */
3438 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
3439 
3440 #ifndef __ASSEMBLY__
3441 /*
3442  * WARNING: The C register and register group struct declarations are provided for
3443  * convenience and illustrative purposes. They should, however, be used with
3444  * caution as the C language standard provides no guarantees about the alignment or
3445  * atomicity of device memory accesses. The recommended practice for coding device
3446  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3447  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3448  * alt_write_dword() functions for 64 bit registers.
3449  *
3450  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT.
3451  */
3452 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_s
3453 {
3454  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW */
3455  uint32_t : 27; /* *UNDEFINED* */
3456 };
3457 
3458 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT. */
3459 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_t;
3460 #endif /* __ASSEMBLY__ */
3461 
3462 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT register. */
3463 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_RESET 0x00000000
3464 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT register from the beginning of the component. */
3465 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_OFST 0x6c
3466 
3467 /*
3468  * Register : mpuregion6addr_base
3469  *
3470  * Base definition for MPU Region 6
3471  *
3472  * Register Layout
3473  *
3474  * Bits | Access | Reset | Description
3475  * :--------|:-------|:------|:------------------------------------------------
3476  * [15:0] | R | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW
3477  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH
3478  *
3479  */
3480 /*
3481  * Field : low
3482  *
3483  * LSB field is all zeros. Region start address is {baseext,base, 16'h000}
3484  *
3485  * Field Access Macros:
3486  *
3487  */
3488 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW register field. */
3489 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW_LSB 0
3490 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW register field. */
3491 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW_MSB 15
3492 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW register field. */
3493 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW_WIDTH 16
3494 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW register field value. */
3495 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW_SET_MSK 0x0000ffff
3496 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW register field value. */
3497 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW_CLR_MSK 0xffff0000
3498 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW register field. */
3499 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW_RESET 0x0
3500 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW field value from a register. */
3501 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
3502 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW register field value suitable for setting the register. */
3503 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
3504 
3505 /*
3506  * Field : high
3507  *
3508  * defines the 16 bit MSB of the base address field.
3509  *
3510  * Field Access Macros:
3511  *
3512  */
3513 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH register field. */
3514 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH_LSB 16
3515 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH register field. */
3516 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH_MSB 31
3517 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH register field. */
3518 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH_WIDTH 16
3519 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH register field value. */
3520 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH_SET_MSK 0xffff0000
3521 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH register field value. */
3522 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
3523 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH register field. */
3524 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH_RESET 0x0
3525 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH field value from a register. */
3526 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
3527 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH register field value suitable for setting the register. */
3528 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
3529 
3530 #ifndef __ASSEMBLY__
3531 /*
3532  * WARNING: The C register and register group struct declarations are provided for
3533  * convenience and illustrative purposes. They should, however, be used with
3534  * caution as the C language standard provides no guarantees about the alignment or
3535  * atomicity of device memory accesses. The recommended practice for coding device
3536  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3537  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3538  * alt_write_dword() functions for 64 bit registers.
3539  *
3540  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE.
3541  */
3542 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_s
3543 {
3544  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW */
3545  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH */
3546 };
3547 
3548 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE. */
3549 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_t;
3550 #endif /* __ASSEMBLY__ */
3551 
3552 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE register. */
3553 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_RESET 0x00000000
3554 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE register from the beginning of the component. */
3555 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_OFST 0x70
3556 
3557 /*
3558  * Register : mpuregion6addr_baseext
3559  *
3560  * base extended definition for MPU Region 6
3561  *
3562  * Register Layout
3563  *
3564  * Bits | Access | Reset | Description
3565  * :-------|:-------|:------|:--------------------------------------------------
3566  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW
3567  * [31:5] | ??? | 0x0 | *UNDEFINED*
3568  *
3569  */
3570 /*
3571  * Field : low
3572  *
3573  * defines the 5 bit LSB of the base extended address field.
3574  *
3575  * Field Access Macros:
3576  *
3577  */
3578 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW register field. */
3579 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW_LSB 0
3580 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW register field. */
3581 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW_MSB 4
3582 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW register field. */
3583 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW_WIDTH 5
3584 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW register field value. */
3585 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
3586 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW register field value. */
3587 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
3588 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW register field. */
3589 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW_RESET 0x0
3590 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW field value from a register. */
3591 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
3592 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW register field value suitable for setting the register. */
3593 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
3594 
3595 #ifndef __ASSEMBLY__
3596 /*
3597  * WARNING: The C register and register group struct declarations are provided for
3598  * convenience and illustrative purposes. They should, however, be used with
3599  * caution as the C language standard provides no guarantees about the alignment or
3600  * atomicity of device memory accesses. The recommended practice for coding device
3601  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3602  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3603  * alt_write_dword() functions for 64 bit registers.
3604  *
3605  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT.
3606  */
3607 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_s
3608 {
3609  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW */
3610  uint32_t : 27; /* *UNDEFINED* */
3611 };
3612 
3613 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT. */
3614 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_t;
3615 #endif /* __ASSEMBLY__ */
3616 
3617 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT register. */
3618 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_RESET 0x00000000
3619 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT register from the beginning of the component. */
3620 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_OFST 0x74
3621 
3622 /*
3623  * Register : mpuregion6addr_limit
3624  *
3625  * Limit definition for MPU Region 6
3626  *
3627  * Register Layout
3628  *
3629  * Bits | Access | Reset | Description
3630  * :--------|:-------|:-------|:-------------------------------------------------
3631  * [15:0] | R | 0xffff | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW
3632  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH
3633  *
3634  */
3635 /*
3636  * Field : low
3637  *
3638  * LSB field is all one. Region end address is {limitext,limit, 16'hFFFF}
3639  *
3640  * Field Access Macros:
3641  *
3642  */
3643 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW register field. */
3644 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW_LSB 0
3645 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW register field. */
3646 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW_MSB 15
3647 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW register field. */
3648 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW_WIDTH 16
3649 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW register field value. */
3650 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
3651 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW register field value. */
3652 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
3653 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW register field. */
3654 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW_RESET 0xffff
3655 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW field value from a register. */
3656 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
3657 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW register field value suitable for setting the register. */
3658 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
3659 
3660 /*
3661  * Field : high
3662  *
3663  * defines the 16 bit MSB of the limit address field.
3664  *
3665  * Field Access Macros:
3666  *
3667  */
3668 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH register field. */
3669 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH_LSB 16
3670 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH register field. */
3671 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH_MSB 31
3672 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH register field. */
3673 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH_WIDTH 16
3674 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH register field value. */
3675 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
3676 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH register field value. */
3677 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
3678 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH register field. */
3679 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH_RESET 0x0
3680 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH field value from a register. */
3681 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
3682 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH register field value suitable for setting the register. */
3683 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
3684 
3685 #ifndef __ASSEMBLY__
3686 /*
3687  * WARNING: The C register and register group struct declarations are provided for
3688  * convenience and illustrative purposes. They should, however, be used with
3689  * caution as the C language standard provides no guarantees about the alignment or
3690  * atomicity of device memory accesses. The recommended practice for coding device
3691  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3692  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3693  * alt_write_dword() functions for 64 bit registers.
3694  *
3695  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT.
3696  */
3697 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_s
3698 {
3699  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW */
3700  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH */
3701 };
3702 
3703 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT. */
3704 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_t;
3705 #endif /* __ASSEMBLY__ */
3706 
3707 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT register. */
3708 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_RESET 0x0000ffff
3709 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT register from the beginning of the component. */
3710 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_OFST 0x78
3711 
3712 /*
3713  * Register : mpuregion6addr_limitext
3714  *
3715  * limit extended definition for MPU Region 6
3716  *
3717  * Register Layout
3718  *
3719  * Bits | Access | Reset | Description
3720  * :-------|:-------|:------|:---------------------------------------------------
3721  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW
3722  * [31:5] | ??? | 0x0 | *UNDEFINED*
3723  *
3724  */
3725 /*
3726  * Field : low
3727  *
3728  * defines the 5 bit LSB of the limit extended address field.
3729  *
3730  * Field Access Macros:
3731  *
3732  */
3733 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW register field. */
3734 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW_LSB 0
3735 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW register field. */
3736 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW_MSB 4
3737 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW register field. */
3738 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW_WIDTH 5
3739 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW register field value. */
3740 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
3741 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW register field value. */
3742 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
3743 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW register field. */
3744 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW_RESET 0x0
3745 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW field value from a register. */
3746 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
3747 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW register field value suitable for setting the register. */
3748 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
3749 
3750 #ifndef __ASSEMBLY__
3751 /*
3752  * WARNING: The C register and register group struct declarations are provided for
3753  * convenience and illustrative purposes. They should, however, be used with
3754  * caution as the C language standard provides no guarantees about the alignment or
3755  * atomicity of device memory accesses. The recommended practice for coding device
3756  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3757  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3758  * alt_write_dword() functions for 64 bit registers.
3759  *
3760  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT.
3761  */
3762 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_s
3763 {
3764  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW */
3765  uint32_t : 27; /* *UNDEFINED* */
3766 };
3767 
3768 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT. */
3769 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_t;
3770 #endif /* __ASSEMBLY__ */
3771 
3772 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT register. */
3773 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_RESET 0x00000000
3774 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT register from the beginning of the component. */
3775 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_OFST 0x7c
3776 
3777 /*
3778  * Register : mpuregion7addr_base
3779  *
3780  * Base definition for MPU Region 7
3781  *
3782  * Register Layout
3783  *
3784  * Bits | Access | Reset | Description
3785  * :--------|:-------|:------|:------------------------------------------------
3786  * [15:0] | R | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW
3787  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH
3788  *
3789  */
3790 /*
3791  * Field : low
3792  *
3793  * LSB field is all zeros. Region start address is {baseext,base, 16'h000}
3794  *
3795  * Field Access Macros:
3796  *
3797  */
3798 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW register field. */
3799 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW_LSB 0
3800 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW register field. */
3801 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW_MSB 15
3802 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW register field. */
3803 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW_WIDTH 16
3804 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW register field value. */
3805 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW_SET_MSK 0x0000ffff
3806 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW register field value. */
3807 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW_CLR_MSK 0xffff0000
3808 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW register field. */
3809 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW_RESET 0x0
3810 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW field value from a register. */
3811 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
3812 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW register field value suitable for setting the register. */
3813 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
3814 
3815 /*
3816  * Field : high
3817  *
3818  * defines the 16 bit MSB of the base address field.
3819  *
3820  * Field Access Macros:
3821  *
3822  */
3823 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH register field. */
3824 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH_LSB 16
3825 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH register field. */
3826 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH_MSB 31
3827 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH register field. */
3828 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH_WIDTH 16
3829 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH register field value. */
3830 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH_SET_MSK 0xffff0000
3831 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH register field value. */
3832 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
3833 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH register field. */
3834 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH_RESET 0x0
3835 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH field value from a register. */
3836 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
3837 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH register field value suitable for setting the register. */
3838 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
3839 
3840 #ifndef __ASSEMBLY__
3841 /*
3842  * WARNING: The C register and register group struct declarations are provided for
3843  * convenience and illustrative purposes. They should, however, be used with
3844  * caution as the C language standard provides no guarantees about the alignment or
3845  * atomicity of device memory accesses. The recommended practice for coding device
3846  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3847  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3848  * alt_write_dword() functions for 64 bit registers.
3849  *
3850  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE.
3851  */
3852 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_s
3853 {
3854  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW */
3855  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH */
3856 };
3857 
3858 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE. */
3859 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_t;
3860 #endif /* __ASSEMBLY__ */
3861 
3862 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE register. */
3863 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_RESET 0x00000000
3864 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE register from the beginning of the component. */
3865 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_OFST 0x80
3866 
3867 /*
3868  * Register : mpuregion7addr_baseext
3869  *
3870  * base extended definition for MPU Region 7
3871  *
3872  * Register Layout
3873  *
3874  * Bits | Access | Reset | Description
3875  * :-------|:-------|:------|:--------------------------------------------------
3876  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW
3877  * [31:5] | ??? | 0x0 | *UNDEFINED*
3878  *
3879  */
3880 /*
3881  * Field : low
3882  *
3883  * defines the 5 bit LSB of the base extended address field.
3884  *
3885  * Field Access Macros:
3886  *
3887  */
3888 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW register field. */
3889 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW_LSB 0
3890 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW register field. */
3891 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW_MSB 4
3892 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW register field. */
3893 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW_WIDTH 5
3894 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW register field value. */
3895 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
3896 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW register field value. */
3897 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
3898 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW register field. */
3899 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW_RESET 0x0
3900 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW field value from a register. */
3901 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
3902 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW register field value suitable for setting the register. */
3903 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
3904 
3905 #ifndef __ASSEMBLY__
3906 /*
3907  * WARNING: The C register and register group struct declarations are provided for
3908  * convenience and illustrative purposes. They should, however, be used with
3909  * caution as the C language standard provides no guarantees about the alignment or
3910  * atomicity of device memory accesses. The recommended practice for coding device
3911  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3912  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3913  * alt_write_dword() functions for 64 bit registers.
3914  *
3915  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT.
3916  */
3917 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_s
3918 {
3919  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW */
3920  uint32_t : 27; /* *UNDEFINED* */
3921 };
3922 
3923 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT. */
3924 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_t;
3925 #endif /* __ASSEMBLY__ */
3926 
3927 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT register. */
3928 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_RESET 0x00000000
3929 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT register from the beginning of the component. */
3930 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_OFST 0x84
3931 
3932 /*
3933  * Register : mpuregion7addr_limit
3934  *
3935  * Limit definition for MPU Region 7
3936  *
3937  * Register Layout
3938  *
3939  * Bits | Access | Reset | Description
3940  * :--------|:-------|:-------|:-------------------------------------------------
3941  * [15:0] | R | 0xffff | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW
3942  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH
3943  *
3944  */
3945 /*
3946  * Field : low
3947  *
3948  * LSB field is all one. Region end address is {limitext,limit, 16'hFFFF}
3949  *
3950  * Field Access Macros:
3951  *
3952  */
3953 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW register field. */
3954 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW_LSB 0
3955 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW register field. */
3956 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW_MSB 15
3957 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW register field. */
3958 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW_WIDTH 16
3959 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW register field value. */
3960 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
3961 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW register field value. */
3962 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
3963 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW register field. */
3964 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW_RESET 0xffff
3965 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW field value from a register. */
3966 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
3967 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW register field value suitable for setting the register. */
3968 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
3969 
3970 /*
3971  * Field : high
3972  *
3973  * defines the 16 bit MSB of the limit address field.
3974  *
3975  * Field Access Macros:
3976  *
3977  */
3978 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH register field. */
3979 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH_LSB 16
3980 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH register field. */
3981 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH_MSB 31
3982 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH register field. */
3983 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH_WIDTH 16
3984 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH register field value. */
3985 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
3986 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH register field value. */
3987 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
3988 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH register field. */
3989 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH_RESET 0x0
3990 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH field value from a register. */
3991 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
3992 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH register field value suitable for setting the register. */
3993 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
3994 
3995 #ifndef __ASSEMBLY__
3996 /*
3997  * WARNING: The C register and register group struct declarations are provided for
3998  * convenience and illustrative purposes. They should, however, be used with
3999  * caution as the C language standard provides no guarantees about the alignment or
4000  * atomicity of device memory accesses. The recommended practice for coding device
4001  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4002  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4003  * alt_write_dword() functions for 64 bit registers.
4004  *
4005  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT.
4006  */
4007 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_s
4008 {
4009  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW */
4010  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH */
4011 };
4012 
4013 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT. */
4014 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_t;
4015 #endif /* __ASSEMBLY__ */
4016 
4017 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT register. */
4018 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_RESET 0x0000ffff
4019 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT register from the beginning of the component. */
4020 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_OFST 0x88
4021 
4022 /*
4023  * Register : mpuregion7addr_limitext
4024  *
4025  * limit extended definition for MPU Region 7
4026  *
4027  * Register Layout
4028  *
4029  * Bits | Access | Reset | Description
4030  * :-------|:-------|:------|:---------------------------------------------------
4031  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW
4032  * [31:5] | ??? | 0x0 | *UNDEFINED*
4033  *
4034  */
4035 /*
4036  * Field : low
4037  *
4038  * defines the 5 bit LSB of the limit extended address field.
4039  *
4040  * Field Access Macros:
4041  *
4042  */
4043 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW register field. */
4044 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW_LSB 0
4045 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW register field. */
4046 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW_MSB 4
4047 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW register field. */
4048 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW_WIDTH 5
4049 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW register field value. */
4050 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
4051 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW register field value. */
4052 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
4053 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW register field. */
4054 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW_RESET 0x0
4055 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW field value from a register. */
4056 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
4057 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW register field value suitable for setting the register. */
4058 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
4059 
4060 #ifndef __ASSEMBLY__
4061 /*
4062  * WARNING: The C register and register group struct declarations are provided for
4063  * convenience and illustrative purposes. They should, however, be used with
4064  * caution as the C language standard provides no guarantees about the alignment or
4065  * atomicity of device memory accesses. The recommended practice for coding device
4066  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4067  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4068  * alt_write_dword() functions for 64 bit registers.
4069  *
4070  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT.
4071  */
4072 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_s
4073 {
4074  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW */
4075  uint32_t : 27; /* *UNDEFINED* */
4076 };
4077 
4078 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT. */
4079 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_t;
4080 #endif /* __ASSEMBLY__ */
4081 
4082 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT register. */
4083 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_RESET 0x00000000
4084 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT register from the beginning of the component. */
4085 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_OFST 0x8c
4086 
4087 /*
4088  * Register : nonmpuregion0addr_base
4089  *
4090  * Base definition for non MPU Region 0
4091  *
4092  * Register Layout
4093  *
4094  * Bits | Access | Reset | Description
4095  * :--------|:-------|:------|:---------------------------------------------------
4096  * [15:0] | R | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW
4097  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH
4098  *
4099  */
4100 /*
4101  * Field : low
4102  *
4103  * LSB field is all zeros. Region start address is {baseext,base, 16'h000}
4104  *
4105  * Field Access Macros:
4106  *
4107  */
4108 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW register field. */
4109 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW_LSB 0
4110 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW register field. */
4111 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW_MSB 15
4112 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW register field. */
4113 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW_WIDTH 16
4114 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW register field value. */
4115 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW_SET_MSK 0x0000ffff
4116 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW register field value. */
4117 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW_CLR_MSK 0xffff0000
4118 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW register field. */
4119 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW_RESET 0x0
4120 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW field value from a register. */
4121 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
4122 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW register field value suitable for setting the register. */
4123 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
4124 
4125 /*
4126  * Field : high
4127  *
4128  * defines the 16 bit MSB of the base address field.
4129  *
4130  * Field Access Macros:
4131  *
4132  */
4133 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH register field. */
4134 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH_LSB 16
4135 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH register field. */
4136 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH_MSB 31
4137 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH register field. */
4138 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH_WIDTH 16
4139 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH register field value. */
4140 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH_SET_MSK 0xffff0000
4141 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH register field value. */
4142 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
4143 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH register field. */
4144 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH_RESET 0x0
4145 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH field value from a register. */
4146 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
4147 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH register field value suitable for setting the register. */
4148 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
4149 
4150 #ifndef __ASSEMBLY__
4151 /*
4152  * WARNING: The C register and register group struct declarations are provided for
4153  * convenience and illustrative purposes. They should, however, be used with
4154  * caution as the C language standard provides no guarantees about the alignment or
4155  * atomicity of device memory accesses. The recommended practice for coding device
4156  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4157  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4158  * alt_write_dword() functions for 64 bit registers.
4159  *
4160  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE.
4161  */
4162 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_s
4163 {
4164  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW */
4165  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH */
4166 };
4167 
4168 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE. */
4169 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_t;
4170 #endif /* __ASSEMBLY__ */
4171 
4172 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE register. */
4173 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_RESET 0x00000000
4174 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE register from the beginning of the component. */
4175 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_OFST 0x90
4176 
4177 /*
4178  * Register : nonmpuregion0addr_baseext
4179  *
4180  * base extended definition for non MPU Region 0
4181  *
4182  * Register Layout
4183  *
4184  * Bits | Access | Reset | Description
4185  * :-------|:-------|:------|:-----------------------------------------------------
4186  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW
4187  * [31:5] | ??? | 0x0 | *UNDEFINED*
4188  *
4189  */
4190 /*
4191  * Field : low
4192  *
4193  * defines the 5 bit LSB of the base extended address field.
4194  *
4195  * Field Access Macros:
4196  *
4197  */
4198 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW register field. */
4199 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW_LSB 0
4200 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW register field. */
4201 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW_MSB 4
4202 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW register field. */
4203 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW_WIDTH 5
4204 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW register field value. */
4205 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
4206 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW register field value. */
4207 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
4208 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW register field. */
4209 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW_RESET 0x0
4210 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW field value from a register. */
4211 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
4212 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW register field value suitable for setting the register. */
4213 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
4214 
4215 #ifndef __ASSEMBLY__
4216 /*
4217  * WARNING: The C register and register group struct declarations are provided for
4218  * convenience and illustrative purposes. They should, however, be used with
4219  * caution as the C language standard provides no guarantees about the alignment or
4220  * atomicity of device memory accesses. The recommended practice for coding device
4221  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4222  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4223  * alt_write_dword() functions for 64 bit registers.
4224  *
4225  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT.
4226  */
4227 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_s
4228 {
4229  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW */
4230  uint32_t : 27; /* *UNDEFINED* */
4231 };
4232 
4233 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT. */
4234 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_t;
4235 #endif /* __ASSEMBLY__ */
4236 
4237 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT register. */
4238 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_RESET 0x00000000
4239 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT register from the beginning of the component. */
4240 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_OFST 0x94
4241 
4242 /*
4243  * Register : nonmpuregion0addr_limit
4244  *
4245  * Limit definition for non MPU Region 0
4246  *
4247  * Register Layout
4248  *
4249  * Bits | Access | Reset | Description
4250  * :--------|:-------|:-------|:----------------------------------------------------
4251  * [15:0] | R | 0xffff | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW
4252  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH
4253  *
4254  */
4255 /*
4256  * Field : low
4257  *
4258  * LSB field is all one. Region end address is {limitext,limit, 16'hFFFF}
4259  *
4260  * Field Access Macros:
4261  *
4262  */
4263 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW register field. */
4264 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW_LSB 0
4265 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW register field. */
4266 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW_MSB 15
4267 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW register field. */
4268 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW_WIDTH 16
4269 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW register field value. */
4270 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
4271 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW register field value. */
4272 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
4273 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW register field. */
4274 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW_RESET 0xffff
4275 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW field value from a register. */
4276 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
4277 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW register field value suitable for setting the register. */
4278 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
4279 
4280 /*
4281  * Field : high
4282  *
4283  * defines the 16 bit MSB of the limit address field.
4284  *
4285  * Field Access Macros:
4286  *
4287  */
4288 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH register field. */
4289 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH_LSB 16
4290 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH register field. */
4291 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH_MSB 31
4292 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH register field. */
4293 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH_WIDTH 16
4294 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH register field value. */
4295 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
4296 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH register field value. */
4297 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
4298 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH register field. */
4299 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH_RESET 0x0
4300 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH field value from a register. */
4301 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
4302 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH register field value suitable for setting the register. */
4303 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
4304 
4305 #ifndef __ASSEMBLY__
4306 /*
4307  * WARNING: The C register and register group struct declarations are provided for
4308  * convenience and illustrative purposes. They should, however, be used with
4309  * caution as the C language standard provides no guarantees about the alignment or
4310  * atomicity of device memory accesses. The recommended practice for coding device
4311  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4312  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4313  * alt_write_dword() functions for 64 bit registers.
4314  *
4315  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT.
4316  */
4317 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_s
4318 {
4319  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW */
4320  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH */
4321 };
4322 
4323 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT. */
4324 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_t;
4325 #endif /* __ASSEMBLY__ */
4326 
4327 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT register. */
4328 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_RESET 0x0000ffff
4329 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT register from the beginning of the component. */
4330 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_OFST 0x98
4331 
4332 /*
4333  * Register : nonmpuregion0addr_limitext
4334  *
4335  * limit extended definition for non MPU Region 0
4336  *
4337  * Register Layout
4338  *
4339  * Bits | Access | Reset | Description
4340  * :-------|:-------|:------|:------------------------------------------------------
4341  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW
4342  * [31:5] | ??? | 0x0 | *UNDEFINED*
4343  *
4344  */
4345 /*
4346  * Field : low
4347  *
4348  * defines the 5 bit LSB of the limit extended address field.
4349  *
4350  * Field Access Macros:
4351  *
4352  */
4353 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW register field. */
4354 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW_LSB 0
4355 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW register field. */
4356 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW_MSB 4
4357 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW register field. */
4358 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW_WIDTH 5
4359 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW register field value. */
4360 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
4361 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW register field value. */
4362 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
4363 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW register field. */
4364 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW_RESET 0x0
4365 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW field value from a register. */
4366 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
4367 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW register field value suitable for setting the register. */
4368 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
4369 
4370 #ifndef __ASSEMBLY__
4371 /*
4372  * WARNING: The C register and register group struct declarations are provided for
4373  * convenience and illustrative purposes. They should, however, be used with
4374  * caution as the C language standard provides no guarantees about the alignment or
4375  * atomicity of device memory accesses. The recommended practice for coding device
4376  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4377  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4378  * alt_write_dword() functions for 64 bit registers.
4379  *
4380  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT.
4381  */
4382 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_s
4383 {
4384  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW */
4385  uint32_t : 27; /* *UNDEFINED* */
4386 };
4387 
4388 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT. */
4389 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_t;
4390 #endif /* __ASSEMBLY__ */
4391 
4392 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT register. */
4393 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_RESET 0x00000000
4394 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT register from the beginning of the component. */
4395 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_OFST 0x9c
4396 
4397 /*
4398  * Register : nonmpuregion1addr_base
4399  *
4400  * Base definition for non MPU Region 1
4401  *
4402  * Register Layout
4403  *
4404  * Bits | Access | Reset | Description
4405  * :--------|:-------|:------|:---------------------------------------------------
4406  * [15:0] | R | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW
4407  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH
4408  *
4409  */
4410 /*
4411  * Field : low
4412  *
4413  * LSB field is all zeros. Region start address is {baseext,base, 16'h000}
4414  *
4415  * Field Access Macros:
4416  *
4417  */
4418 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW register field. */
4419 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW_LSB 0
4420 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW register field. */
4421 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW_MSB 15
4422 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW register field. */
4423 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW_WIDTH 16
4424 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW register field value. */
4425 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW_SET_MSK 0x0000ffff
4426 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW register field value. */
4427 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW_CLR_MSK 0xffff0000
4428 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW register field. */
4429 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW_RESET 0x0
4430 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW field value from a register. */
4431 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
4432 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW register field value suitable for setting the register. */
4433 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
4434 
4435 /*
4436  * Field : high
4437  *
4438  * defines the 16 bit MSB of the base address field.
4439  *
4440  * Field Access Macros:
4441  *
4442  */
4443 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH register field. */
4444 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH_LSB 16
4445 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH register field. */
4446 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH_MSB 31
4447 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH register field. */
4448 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH_WIDTH 16
4449 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH register field value. */
4450 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH_SET_MSK 0xffff0000
4451 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH register field value. */
4452 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
4453 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH register field. */
4454 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH_RESET 0x0
4455 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH field value from a register. */
4456 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
4457 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH register field value suitable for setting the register. */
4458 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
4459 
4460 #ifndef __ASSEMBLY__
4461 /*
4462  * WARNING: The C register and register group struct declarations are provided for
4463  * convenience and illustrative purposes. They should, however, be used with
4464  * caution as the C language standard provides no guarantees about the alignment or
4465  * atomicity of device memory accesses. The recommended practice for coding device
4466  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4467  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4468  * alt_write_dword() functions for 64 bit registers.
4469  *
4470  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE.
4471  */
4472 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_s
4473 {
4474  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW */
4475  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH */
4476 };
4477 
4478 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE. */
4479 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_t;
4480 #endif /* __ASSEMBLY__ */
4481 
4482 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE register. */
4483 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_RESET 0x00000000
4484 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE register from the beginning of the component. */
4485 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_OFST 0xa0
4486 
4487 /*
4488  * Register : nonmpuregion1addr_baseext
4489  *
4490  * base extended definition for non MPU Region 1
4491  *
4492  * Register Layout
4493  *
4494  * Bits | Access | Reset | Description
4495  * :-------|:-------|:------|:-----------------------------------------------------
4496  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW
4497  * [31:5] | ??? | 0x0 | *UNDEFINED*
4498  *
4499  */
4500 /*
4501  * Field : low
4502  *
4503  * defines the 5 bit LSB of the base extended address field.
4504  *
4505  * Field Access Macros:
4506  *
4507  */
4508 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW register field. */
4509 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW_LSB 0
4510 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW register field. */
4511 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW_MSB 4
4512 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW register field. */
4513 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW_WIDTH 5
4514 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW register field value. */
4515 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
4516 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW register field value. */
4517 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
4518 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW register field. */
4519 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW_RESET 0x0
4520 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW field value from a register. */
4521 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
4522 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW register field value suitable for setting the register. */
4523 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
4524 
4525 #ifndef __ASSEMBLY__
4526 /*
4527  * WARNING: The C register and register group struct declarations are provided for
4528  * convenience and illustrative purposes. They should, however, be used with
4529  * caution as the C language standard provides no guarantees about the alignment or
4530  * atomicity of device memory accesses. The recommended practice for coding device
4531  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4532  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4533  * alt_write_dword() functions for 64 bit registers.
4534  *
4535  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT.
4536  */
4537 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_s
4538 {
4539  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW */
4540  uint32_t : 27; /* *UNDEFINED* */
4541 };
4542 
4543 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT. */
4544 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_t;
4545 #endif /* __ASSEMBLY__ */
4546 
4547 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT register. */
4548 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_RESET 0x00000000
4549 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT register from the beginning of the component. */
4550 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_OFST 0xa4
4551 
4552 /*
4553  * Register : nonmpuregion1addr_limit
4554  *
4555  * Limit definition for non MPU Region 1
4556  *
4557  * Register Layout
4558  *
4559  * Bits | Access | Reset | Description
4560  * :--------|:-------|:-------|:----------------------------------------------------
4561  * [15:0] | R | 0xffff | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW
4562  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH
4563  *
4564  */
4565 /*
4566  * Field : low
4567  *
4568  * LSB field is all one. Region end address is {limitext,limit, 16'hFFFF}
4569  *
4570  * Field Access Macros:
4571  *
4572  */
4573 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW register field. */
4574 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW_LSB 0
4575 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW register field. */
4576 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW_MSB 15
4577 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW register field. */
4578 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW_WIDTH 16
4579 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW register field value. */
4580 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
4581 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW register field value. */
4582 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
4583 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW register field. */
4584 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW_RESET 0xffff
4585 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW field value from a register. */
4586 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
4587 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW register field value suitable for setting the register. */
4588 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
4589 
4590 /*
4591  * Field : high
4592  *
4593  * defines the 16 bit MSB of the limit address field.
4594  *
4595  * Field Access Macros:
4596  *
4597  */
4598 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH register field. */
4599 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH_LSB 16
4600 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH register field. */
4601 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH_MSB 31
4602 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH register field. */
4603 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH_WIDTH 16
4604 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH register field value. */
4605 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
4606 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH register field value. */
4607 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
4608 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH register field. */
4609 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH_RESET 0x0
4610 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH field value from a register. */
4611 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
4612 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH register field value suitable for setting the register. */
4613 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
4614 
4615 #ifndef __ASSEMBLY__
4616 /*
4617  * WARNING: The C register and register group struct declarations are provided for
4618  * convenience and illustrative purposes. They should, however, be used with
4619  * caution as the C language standard provides no guarantees about the alignment or
4620  * atomicity of device memory accesses. The recommended practice for coding device
4621  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4622  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4623  * alt_write_dword() functions for 64 bit registers.
4624  *
4625  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT.
4626  */
4627 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_s
4628 {
4629  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW */
4630  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH */
4631 };
4632 
4633 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT. */
4634 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_t;
4635 #endif /* __ASSEMBLY__ */
4636 
4637 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT register. */
4638 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_RESET 0x0000ffff
4639 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT register from the beginning of the component. */
4640 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_OFST 0xa8
4641 
4642 /*
4643  * Register : nonmpuregion1addr_limitext
4644  *
4645  * limit extended definition for non MPU Region 1
4646  *
4647  * Register Layout
4648  *
4649  * Bits | Access | Reset | Description
4650  * :-------|:-------|:------|:------------------------------------------------------
4651  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW
4652  * [31:5] | ??? | 0x0 | *UNDEFINED*
4653  *
4654  */
4655 /*
4656  * Field : low
4657  *
4658  * defines the 5 bit LSB of the limit extended address field.
4659  *
4660  * Field Access Macros:
4661  *
4662  */
4663 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW register field. */
4664 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW_LSB 0
4665 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW register field. */
4666 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW_MSB 4
4667 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW register field. */
4668 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW_WIDTH 5
4669 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW register field value. */
4670 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
4671 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW register field value. */
4672 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
4673 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW register field. */
4674 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW_RESET 0x0
4675 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW field value from a register. */
4676 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
4677 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW register field value suitable for setting the register. */
4678 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
4679 
4680 #ifndef __ASSEMBLY__
4681 /*
4682  * WARNING: The C register and register group struct declarations are provided for
4683  * convenience and illustrative purposes. They should, however, be used with
4684  * caution as the C language standard provides no guarantees about the alignment or
4685  * atomicity of device memory accesses. The recommended practice for coding device
4686  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4687  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4688  * alt_write_dword() functions for 64 bit registers.
4689  *
4690  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT.
4691  */
4692 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_s
4693 {
4694  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW */
4695  uint32_t : 27; /* *UNDEFINED* */
4696 };
4697 
4698 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT. */
4699 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_t;
4700 #endif /* __ASSEMBLY__ */
4701 
4702 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT register. */
4703 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_RESET 0x00000000
4704 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT register from the beginning of the component. */
4705 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_OFST 0xac
4706 
4707 /*
4708  * Register : nonmpuregion2addr_base
4709  *
4710  * Base definition for non MPU Region 2
4711  *
4712  * Register Layout
4713  *
4714  * Bits | Access | Reset | Description
4715  * :--------|:-------|:------|:---------------------------------------------------
4716  * [15:0] | R | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW
4717  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH
4718  *
4719  */
4720 /*
4721  * Field : low
4722  *
4723  * LSB field is all zeros. Region start address is {baseext,base, 16'h000}
4724  *
4725  * Field Access Macros:
4726  *
4727  */
4728 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW register field. */
4729 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW_LSB 0
4730 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW register field. */
4731 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW_MSB 15
4732 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW register field. */
4733 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW_WIDTH 16
4734 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW register field value. */
4735 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW_SET_MSK 0x0000ffff
4736 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW register field value. */
4737 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW_CLR_MSK 0xffff0000
4738 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW register field. */
4739 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW_RESET 0x0
4740 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW field value from a register. */
4741 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
4742 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW register field value suitable for setting the register. */
4743 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
4744 
4745 /*
4746  * Field : high
4747  *
4748  * defines the 16 bit MSB of the base address field.
4749  *
4750  * Field Access Macros:
4751  *
4752  */
4753 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH register field. */
4754 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH_LSB 16
4755 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH register field. */
4756 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH_MSB 31
4757 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH register field. */
4758 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH_WIDTH 16
4759 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH register field value. */
4760 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH_SET_MSK 0xffff0000
4761 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH register field value. */
4762 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
4763 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH register field. */
4764 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH_RESET 0x0
4765 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH field value from a register. */
4766 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
4767 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH register field value suitable for setting the register. */
4768 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
4769 
4770 #ifndef __ASSEMBLY__
4771 /*
4772  * WARNING: The C register and register group struct declarations are provided for
4773  * convenience and illustrative purposes. They should, however, be used with
4774  * caution as the C language standard provides no guarantees about the alignment or
4775  * atomicity of device memory accesses. The recommended practice for coding device
4776  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4777  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4778  * alt_write_dword() functions for 64 bit registers.
4779  *
4780  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE.
4781  */
4782 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_s
4783 {
4784  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW */
4785  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH */
4786 };
4787 
4788 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE. */
4789 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_t;
4790 #endif /* __ASSEMBLY__ */
4791 
4792 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE register. */
4793 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_RESET 0x00000000
4794 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE register from the beginning of the component. */
4795 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_OFST 0xb0
4796 
4797 /*
4798  * Register : nonmpuregion2addr_baseext
4799  *
4800  * base extended definition for non MPU Region 2
4801  *
4802  * Register Layout
4803  *
4804  * Bits | Access | Reset | Description
4805  * :-------|:-------|:------|:-----------------------------------------------------
4806  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW
4807  * [31:5] | ??? | 0x0 | *UNDEFINED*
4808  *
4809  */
4810 /*
4811  * Field : low
4812  *
4813  * defines the 5 bit LSB of the base extended address field.
4814  *
4815  * Field Access Macros:
4816  *
4817  */
4818 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW register field. */
4819 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW_LSB 0
4820 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW register field. */
4821 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW_MSB 4
4822 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW register field. */
4823 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW_WIDTH 5
4824 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW register field value. */
4825 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
4826 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW register field value. */
4827 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
4828 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW register field. */
4829 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW_RESET 0x0
4830 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW field value from a register. */
4831 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
4832 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW register field value suitable for setting the register. */
4833 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
4834 
4835 #ifndef __ASSEMBLY__
4836 /*
4837  * WARNING: The C register and register group struct declarations are provided for
4838  * convenience and illustrative purposes. They should, however, be used with
4839  * caution as the C language standard provides no guarantees about the alignment or
4840  * atomicity of device memory accesses. The recommended practice for coding device
4841  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4842  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4843  * alt_write_dword() functions for 64 bit registers.
4844  *
4845  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT.
4846  */
4847 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_s
4848 {
4849  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW */
4850  uint32_t : 27; /* *UNDEFINED* */
4851 };
4852 
4853 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT. */
4854 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_t;
4855 #endif /* __ASSEMBLY__ */
4856 
4857 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT register. */
4858 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_RESET 0x00000000
4859 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT register from the beginning of the component. */
4860 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_OFST 0xb4
4861 
4862 /*
4863  * Register : nonmpuregion2addr_limit
4864  *
4865  * Limit definition for non MPU Region 2
4866  *
4867  * Register Layout
4868  *
4869  * Bits | Access | Reset | Description
4870  * :--------|:-------|:-------|:----------------------------------------------------
4871  * [15:0] | R | 0xffff | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW
4872  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH
4873  *
4874  */
4875 /*
4876  * Field : low
4877  *
4878  * LSB field is all one. Region end address is {limitext,limit, 16'hFFFF}
4879  *
4880  * Field Access Macros:
4881  *
4882  */
4883 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW register field. */
4884 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW_LSB 0
4885 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW register field. */
4886 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW_MSB 15
4887 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW register field. */
4888 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW_WIDTH 16
4889 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW register field value. */
4890 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
4891 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW register field value. */
4892 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
4893 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW register field. */
4894 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW_RESET 0xffff
4895 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW field value from a register. */
4896 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
4897 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW register field value suitable for setting the register. */
4898 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
4899 
4900 /*
4901  * Field : high
4902  *
4903  * defines the 16 bit MSB of the limit address field.
4904  *
4905  * Field Access Macros:
4906  *
4907  */
4908 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH register field. */
4909 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH_LSB 16
4910 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH register field. */
4911 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH_MSB 31
4912 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH register field. */
4913 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH_WIDTH 16
4914 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH register field value. */
4915 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
4916 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH register field value. */
4917 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
4918 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH register field. */
4919 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH_RESET 0x0
4920 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH field value from a register. */
4921 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
4922 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH register field value suitable for setting the register. */
4923 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
4924 
4925 #ifndef __ASSEMBLY__
4926 /*
4927  * WARNING: The C register and register group struct declarations are provided for
4928  * convenience and illustrative purposes. They should, however, be used with
4929  * caution as the C language standard provides no guarantees about the alignment or
4930  * atomicity of device memory accesses. The recommended practice for coding device
4931  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4932  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4933  * alt_write_dword() functions for 64 bit registers.
4934  *
4935  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT.
4936  */
4937 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_s
4938 {
4939  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW */
4940  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH */
4941 };
4942 
4943 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT. */
4944 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_t;
4945 #endif /* __ASSEMBLY__ */
4946 
4947 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT register. */
4948 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_RESET 0x0000ffff
4949 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT register from the beginning of the component. */
4950 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_OFST 0xb8
4951 
4952 /*
4953  * Register : nonmpuregion2addr_limitext
4954  *
4955  * limit extended definition for non MPU Region 2
4956  *
4957  * Register Layout
4958  *
4959  * Bits | Access | Reset | Description
4960  * :-------|:-------|:------|:------------------------------------------------------
4961  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW
4962  * [31:5] | ??? | 0x0 | *UNDEFINED*
4963  *
4964  */
4965 /*
4966  * Field : low
4967  *
4968  * defines the 5 bit LSB of the limit extended address field.
4969  *
4970  * Field Access Macros:
4971  *
4972  */
4973 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW register field. */
4974 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW_LSB 0
4975 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW register field. */
4976 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW_MSB 4
4977 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW register field. */
4978 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW_WIDTH 5
4979 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW register field value. */
4980 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
4981 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW register field value. */
4982 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
4983 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW register field. */
4984 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW_RESET 0x0
4985 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW field value from a register. */
4986 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
4987 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW register field value suitable for setting the register. */
4988 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
4989 
4990 #ifndef __ASSEMBLY__
4991 /*
4992  * WARNING: The C register and register group struct declarations are provided for
4993  * convenience and illustrative purposes. They should, however, be used with
4994  * caution as the C language standard provides no guarantees about the alignment or
4995  * atomicity of device memory accesses. The recommended practice for coding device
4996  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4997  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4998  * alt_write_dword() functions for 64 bit registers.
4999  *
5000  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT.
5001  */
5002 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_s
5003 {
5004  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW */
5005  uint32_t : 27; /* *UNDEFINED* */
5006 };
5007 
5008 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT. */
5009 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_t;
5010 #endif /* __ASSEMBLY__ */
5011 
5012 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT register. */
5013 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_RESET 0x00000000
5014 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT register from the beginning of the component. */
5015 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_OFST 0xbc
5016 
5017 /*
5018  * Register : nonmpuregion3addr_base
5019  *
5020  * Base definition for non MPU Region 3
5021  *
5022  * Register Layout
5023  *
5024  * Bits | Access | Reset | Description
5025  * :--------|:-------|:------|:---------------------------------------------------
5026  * [15:0] | R | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW
5027  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH
5028  *
5029  */
5030 /*
5031  * Field : low
5032  *
5033  * LSB field is all zeros. Region start address is {baseext,base, 16'h000}
5034  *
5035  * Field Access Macros:
5036  *
5037  */
5038 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW register field. */
5039 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW_LSB 0
5040 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW register field. */
5041 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW_MSB 15
5042 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW register field. */
5043 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW_WIDTH 16
5044 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW register field value. */
5045 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW_SET_MSK 0x0000ffff
5046 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW register field value. */
5047 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW_CLR_MSK 0xffff0000
5048 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW register field. */
5049 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW_RESET 0x0
5050 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW field value from a register. */
5051 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
5052 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW register field value suitable for setting the register. */
5053 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
5054 
5055 /*
5056  * Field : high
5057  *
5058  * defines the 16 bit MSB of the base address field.
5059  *
5060  * Field Access Macros:
5061  *
5062  */
5063 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH register field. */
5064 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH_LSB 16
5065 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH register field. */
5066 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH_MSB 31
5067 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH register field. */
5068 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH_WIDTH 16
5069 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH register field value. */
5070 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH_SET_MSK 0xffff0000
5071 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH register field value. */
5072 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
5073 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH register field. */
5074 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH_RESET 0x0
5075 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH field value from a register. */
5076 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
5077 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH register field value suitable for setting the register. */
5078 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
5079 
5080 #ifndef __ASSEMBLY__
5081 /*
5082  * WARNING: The C register and register group struct declarations are provided for
5083  * convenience and illustrative purposes. They should, however, be used with
5084  * caution as the C language standard provides no guarantees about the alignment or
5085  * atomicity of device memory accesses. The recommended practice for coding device
5086  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5087  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5088  * alt_write_dword() functions for 64 bit registers.
5089  *
5090  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE.
5091  */
5092 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_s
5093 {
5094  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW */
5095  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH */
5096 };
5097 
5098 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE. */
5099 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_t;
5100 #endif /* __ASSEMBLY__ */
5101 
5102 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE register. */
5103 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_RESET 0x00000000
5104 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE register from the beginning of the component. */
5105 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_OFST 0xc0
5106 
5107 /*
5108  * Register : nonmpuregion3addr_baseext
5109  *
5110  * base extended definition for non MPU Region 3
5111  *
5112  * Register Layout
5113  *
5114  * Bits | Access | Reset | Description
5115  * :-------|:-------|:------|:-----------------------------------------------------
5116  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW
5117  * [31:5] | ??? | 0x0 | *UNDEFINED*
5118  *
5119  */
5120 /*
5121  * Field : low
5122  *
5123  * defines the 5 bit LSB of the base extended address field.
5124  *
5125  * Field Access Macros:
5126  *
5127  */
5128 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW register field. */
5129 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW_LSB 0
5130 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW register field. */
5131 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW_MSB 4
5132 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW register field. */
5133 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW_WIDTH 5
5134 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW register field value. */
5135 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
5136 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW register field value. */
5137 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
5138 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW register field. */
5139 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW_RESET 0x0
5140 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW field value from a register. */
5141 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
5142 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW register field value suitable for setting the register. */
5143 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
5144 
5145 #ifndef __ASSEMBLY__
5146 /*
5147  * WARNING: The C register and register group struct declarations are provided for
5148  * convenience and illustrative purposes. They should, however, be used with
5149  * caution as the C language standard provides no guarantees about the alignment or
5150  * atomicity of device memory accesses. The recommended practice for coding device
5151  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5152  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5153  * alt_write_dword() functions for 64 bit registers.
5154  *
5155  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT.
5156  */
5157 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_s
5158 {
5159  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW */
5160  uint32_t : 27; /* *UNDEFINED* */
5161 };
5162 
5163 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT. */
5164 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_t;
5165 #endif /* __ASSEMBLY__ */
5166 
5167 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT register. */
5168 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_RESET 0x00000000
5169 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT register from the beginning of the component. */
5170 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_OFST 0xc4
5171 
5172 /*
5173  * Register : nonmpuregion3addr_limit
5174  *
5175  * Limit definition for non MPU Region 3
5176  *
5177  * Register Layout
5178  *
5179  * Bits | Access | Reset | Description
5180  * :--------|:-------|:-------|:----------------------------------------------------
5181  * [15:0] | R | 0xffff | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW
5182  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH
5183  *
5184  */
5185 /*
5186  * Field : low
5187  *
5188  * LSB field is all one. Region end address is {limitext,limit, 16'hFFFF}
5189  *
5190  * Field Access Macros:
5191  *
5192  */
5193 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW register field. */
5194 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW_LSB 0
5195 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW register field. */
5196 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW_MSB 15
5197 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW register field. */
5198 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW_WIDTH 16
5199 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW register field value. */
5200 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
5201 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW register field value. */
5202 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
5203 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW register field. */
5204 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW_RESET 0xffff
5205 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW field value from a register. */
5206 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
5207 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW register field value suitable for setting the register. */
5208 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
5209 
5210 /*
5211  * Field : high
5212  *
5213  * defines the 16 bit MSB of the limit address field.
5214  *
5215  * Field Access Macros:
5216  *
5217  */
5218 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH register field. */
5219 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH_LSB 16
5220 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH register field. */
5221 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH_MSB 31
5222 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH register field. */
5223 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH_WIDTH 16
5224 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH register field value. */
5225 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
5226 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH register field value. */
5227 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
5228 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH register field. */
5229 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH_RESET 0x0
5230 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH field value from a register. */
5231 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
5232 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH register field value suitable for setting the register. */
5233 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
5234 
5235 #ifndef __ASSEMBLY__
5236 /*
5237  * WARNING: The C register and register group struct declarations are provided for
5238  * convenience and illustrative purposes. They should, however, be used with
5239  * caution as the C language standard provides no guarantees about the alignment or
5240  * atomicity of device memory accesses. The recommended practice for coding device
5241  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5242  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5243  * alt_write_dword() functions for 64 bit registers.
5244  *
5245  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT.
5246  */
5247 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_s
5248 {
5249  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW */
5250  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH */
5251 };
5252 
5253 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT. */
5254 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_t;
5255 #endif /* __ASSEMBLY__ */
5256 
5257 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT register. */
5258 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_RESET 0x0000ffff
5259 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT register from the beginning of the component. */
5260 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_OFST 0xc8
5261 
5262 /*
5263  * Register : nonmpuregion3addr_limitext
5264  *
5265  * limit extended definition for non MPU Region 3
5266  *
5267  * Register Layout
5268  *
5269  * Bits | Access | Reset | Description
5270  * :-------|:-------|:------|:------------------------------------------------------
5271  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW
5272  * [31:5] | ??? | 0x0 | *UNDEFINED*
5273  *
5274  */
5275 /*
5276  * Field : low
5277  *
5278  * defines the 5 bit LSB of the limit extended address field.
5279  *
5280  * Field Access Macros:
5281  *
5282  */
5283 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW register field. */
5284 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW_LSB 0
5285 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW register field. */
5286 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW_MSB 4
5287 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW register field. */
5288 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW_WIDTH 5
5289 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW register field value. */
5290 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
5291 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW register field value. */
5292 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
5293 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW register field. */
5294 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW_RESET 0x0
5295 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW field value from a register. */
5296 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
5297 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW register field value suitable for setting the register. */
5298 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
5299 
5300 #ifndef __ASSEMBLY__
5301 /*
5302  * WARNING: The C register and register group struct declarations are provided for
5303  * convenience and illustrative purposes. They should, however, be used with
5304  * caution as the C language standard provides no guarantees about the alignment or
5305  * atomicity of device memory accesses. The recommended practice for coding device
5306  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5307  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5308  * alt_write_dword() functions for 64 bit registers.
5309  *
5310  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT.
5311  */
5312 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_s
5313 {
5314  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW */
5315  uint32_t : 27; /* *UNDEFINED* */
5316 };
5317 
5318 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT. */
5319 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_t;
5320 #endif /* __ASSEMBLY__ */
5321 
5322 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT register. */
5323 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_RESET 0x00000000
5324 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT register from the beginning of the component. */
5325 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_OFST 0xcc
5326 
5327 /*
5328  * Register : nonmpuregion4addr_base
5329  *
5330  * Base definition for non MPU Region 4
5331  *
5332  * Register Layout
5333  *
5334  * Bits | Access | Reset | Description
5335  * :--------|:-------|:------|:---------------------------------------------------
5336  * [15:0] | R | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW
5337  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH
5338  *
5339  */
5340 /*
5341  * Field : low
5342  *
5343  * LSB field is all zeros. Region start address is {baseext,base, 16'h000}
5344  *
5345  * Field Access Macros:
5346  *
5347  */
5348 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW register field. */
5349 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW_LSB 0
5350 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW register field. */
5351 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW_MSB 15
5352 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW register field. */
5353 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW_WIDTH 16
5354 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW register field value. */
5355 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW_SET_MSK 0x0000ffff
5356 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW register field value. */
5357 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW_CLR_MSK 0xffff0000
5358 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW register field. */
5359 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW_RESET 0x0
5360 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW field value from a register. */
5361 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
5362 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW register field value suitable for setting the register. */
5363 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
5364 
5365 /*
5366  * Field : high
5367  *
5368  * defines the 16 bit MSB of the base address field.
5369  *
5370  * Field Access Macros:
5371  *
5372  */
5373 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH register field. */
5374 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH_LSB 16
5375 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH register field. */
5376 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH_MSB 31
5377 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH register field. */
5378 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH_WIDTH 16
5379 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH register field value. */
5380 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH_SET_MSK 0xffff0000
5381 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH register field value. */
5382 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
5383 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH register field. */
5384 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH_RESET 0x0
5385 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH field value from a register. */
5386 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
5387 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH register field value suitable for setting the register. */
5388 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
5389 
5390 #ifndef __ASSEMBLY__
5391 /*
5392  * WARNING: The C register and register group struct declarations are provided for
5393  * convenience and illustrative purposes. They should, however, be used with
5394  * caution as the C language standard provides no guarantees about the alignment or
5395  * atomicity of device memory accesses. The recommended practice for coding device
5396  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5397  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5398  * alt_write_dword() functions for 64 bit registers.
5399  *
5400  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE.
5401  */
5402 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_s
5403 {
5404  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW */
5405  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH */
5406 };
5407 
5408 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE. */
5409 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_t;
5410 #endif /* __ASSEMBLY__ */
5411 
5412 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE register. */
5413 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_RESET 0x00000000
5414 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE register from the beginning of the component. */
5415 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_OFST 0xd0
5416 
5417 /*
5418  * Register : nonmpuregion4addr_baseext
5419  *
5420  * base extended definition for non MPU Region 4
5421  *
5422  * Register Layout
5423  *
5424  * Bits | Access | Reset | Description
5425  * :-------|:-------|:------|:-----------------------------------------------------
5426  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW
5427  * [31:5] | ??? | 0x0 | *UNDEFINED*
5428  *
5429  */
5430 /*
5431  * Field : low
5432  *
5433  * defines the 5 bit LSB of the base extended address field.
5434  *
5435  * Field Access Macros:
5436  *
5437  */
5438 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW register field. */
5439 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW_LSB 0
5440 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW register field. */
5441 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW_MSB 4
5442 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW register field. */
5443 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW_WIDTH 5
5444 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW register field value. */
5445 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
5446 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW register field value. */
5447 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
5448 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW register field. */
5449 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW_RESET 0x0
5450 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW field value from a register. */
5451 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
5452 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW register field value suitable for setting the register. */
5453 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
5454 
5455 #ifndef __ASSEMBLY__
5456 /*
5457  * WARNING: The C register and register group struct declarations are provided for
5458  * convenience and illustrative purposes. They should, however, be used with
5459  * caution as the C language standard provides no guarantees about the alignment or
5460  * atomicity of device memory accesses. The recommended practice for coding device
5461  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5462  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5463  * alt_write_dword() functions for 64 bit registers.
5464  *
5465  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT.
5466  */
5467 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_s
5468 {
5469  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW */
5470  uint32_t : 27; /* *UNDEFINED* */
5471 };
5472 
5473 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT. */
5474 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_t;
5475 #endif /* __ASSEMBLY__ */
5476 
5477 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT register. */
5478 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_RESET 0x00000000
5479 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT register from the beginning of the component. */
5480 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_OFST 0xd4
5481 
5482 /*
5483  * Register : nonmpuregion4addr_limit
5484  *
5485  * Limit definition for non MPU Region 4
5486  *
5487  * Register Layout
5488  *
5489  * Bits | Access | Reset | Description
5490  * :--------|:-------|:-------|:----------------------------------------------------
5491  * [15:0] | R | 0xffff | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW
5492  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH
5493  *
5494  */
5495 /*
5496  * Field : low
5497  *
5498  * LSB field is all one. Region end address is {limitext,limit, 16'hFFFF}
5499  *
5500  * Field Access Macros:
5501  *
5502  */
5503 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW register field. */
5504 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW_LSB 0
5505 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW register field. */
5506 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW_MSB 15
5507 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW register field. */
5508 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW_WIDTH 16
5509 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW register field value. */
5510 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
5511 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW register field value. */
5512 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
5513 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW register field. */
5514 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW_RESET 0xffff
5515 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW field value from a register. */
5516 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
5517 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW register field value suitable for setting the register. */
5518 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
5519 
5520 /*
5521  * Field : high
5522  *
5523  * defines the 16 bit MSB of the limit address field.
5524  *
5525  * Field Access Macros:
5526  *
5527  */
5528 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH register field. */
5529 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH_LSB 16
5530 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH register field. */
5531 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH_MSB 31
5532 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH register field. */
5533 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH_WIDTH 16
5534 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH register field value. */
5535 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
5536 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH register field value. */
5537 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
5538 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH register field. */
5539 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH_RESET 0x0
5540 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH field value from a register. */
5541 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
5542 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH register field value suitable for setting the register. */
5543 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
5544 
5545 #ifndef __ASSEMBLY__
5546 /*
5547  * WARNING: The C register and register group struct declarations are provided for
5548  * convenience and illustrative purposes. They should, however, be used with
5549  * caution as the C language standard provides no guarantees about the alignment or
5550  * atomicity of device memory accesses. The recommended practice for coding device
5551  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5552  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5553  * alt_write_dword() functions for 64 bit registers.
5554  *
5555  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT.
5556  */
5557 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_s
5558 {
5559  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW */
5560  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH */
5561 };
5562 
5563 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT. */
5564 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_t;
5565 #endif /* __ASSEMBLY__ */
5566 
5567 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT register. */
5568 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_RESET 0x0000ffff
5569 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT register from the beginning of the component. */
5570 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_OFST 0xd8
5571 
5572 /*
5573  * Register : nonmpuregion4addr_limitext
5574  *
5575  * limit extended definition for non MPU Region 4
5576  *
5577  * Register Layout
5578  *
5579  * Bits | Access | Reset | Description
5580  * :-------|:-------|:------|:------------------------------------------------------
5581  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW
5582  * [31:5] | ??? | 0x0 | *UNDEFINED*
5583  *
5584  */
5585 /*
5586  * Field : low
5587  *
5588  * defines the 5 bit LSB of the limit extended address field.
5589  *
5590  * Field Access Macros:
5591  *
5592  */
5593 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW register field. */
5594 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW_LSB 0
5595 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW register field. */
5596 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW_MSB 4
5597 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW register field. */
5598 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW_WIDTH 5
5599 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW register field value. */
5600 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
5601 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW register field value. */
5602 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
5603 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW register field. */
5604 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW_RESET 0x0
5605 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW field value from a register. */
5606 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
5607 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW register field value suitable for setting the register. */
5608 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
5609 
5610 #ifndef __ASSEMBLY__
5611 /*
5612  * WARNING: The C register and register group struct declarations are provided for
5613  * convenience and illustrative purposes. They should, however, be used with
5614  * caution as the C language standard provides no guarantees about the alignment or
5615  * atomicity of device memory accesses. The recommended practice for coding device
5616  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5617  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5618  * alt_write_dword() functions for 64 bit registers.
5619  *
5620  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT.
5621  */
5622 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_s
5623 {
5624  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW */
5625  uint32_t : 27; /* *UNDEFINED* */
5626 };
5627 
5628 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT. */
5629 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_t;
5630 #endif /* __ASSEMBLY__ */
5631 
5632 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT register. */
5633 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_RESET 0x00000000
5634 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT register from the beginning of the component. */
5635 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_OFST 0xdc
5636 
5637 /*
5638  * Register : nonmpuregion5addr_base
5639  *
5640  * Base definition for non MPU Region 5
5641  *
5642  * Register Layout
5643  *
5644  * Bits | Access | Reset | Description
5645  * :--------|:-------|:------|:---------------------------------------------------
5646  * [15:0] | R | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW
5647  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH
5648  *
5649  */
5650 /*
5651  * Field : low
5652  *
5653  * LSB field is all zeros. Region start address is {baseext,base, 16'h000}
5654  *
5655  * Field Access Macros:
5656  *
5657  */
5658 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW register field. */
5659 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW_LSB 0
5660 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW register field. */
5661 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW_MSB 15
5662 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW register field. */
5663 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW_WIDTH 16
5664 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW register field value. */
5665 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW_SET_MSK 0x0000ffff
5666 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW register field value. */
5667 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW_CLR_MSK 0xffff0000
5668 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW register field. */
5669 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW_RESET 0x0
5670 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW field value from a register. */
5671 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
5672 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW register field value suitable for setting the register. */
5673 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
5674 
5675 /*
5676  * Field : high
5677  *
5678  * defines the 16 bit MSB of the base address field.
5679  *
5680  * Field Access Macros:
5681  *
5682  */
5683 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH register field. */
5684 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH_LSB 16
5685 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH register field. */
5686 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH_MSB 31
5687 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH register field. */
5688 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH_WIDTH 16
5689 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH register field value. */
5690 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH_SET_MSK 0xffff0000
5691 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH register field value. */
5692 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
5693 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH register field. */
5694 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH_RESET 0x0
5695 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH field value from a register. */
5696 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
5697 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH register field value suitable for setting the register. */
5698 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
5699 
5700 #ifndef __ASSEMBLY__
5701 /*
5702  * WARNING: The C register and register group struct declarations are provided for
5703  * convenience and illustrative purposes. They should, however, be used with
5704  * caution as the C language standard provides no guarantees about the alignment or
5705  * atomicity of device memory accesses. The recommended practice for coding device
5706  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5707  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5708  * alt_write_dword() functions for 64 bit registers.
5709  *
5710  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE.
5711  */
5712 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_s
5713 {
5714  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW */
5715  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH */
5716 };
5717 
5718 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE. */
5719 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_t;
5720 #endif /* __ASSEMBLY__ */
5721 
5722 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE register. */
5723 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_RESET 0x00000000
5724 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE register from the beginning of the component. */
5725 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_OFST 0xe0
5726 
5727 /*
5728  * Register : nonmpuregion5addr_baseext
5729  *
5730  * base extended definition for non MPU Region 5
5731  *
5732  * Register Layout
5733  *
5734  * Bits | Access | Reset | Description
5735  * :-------|:-------|:------|:-----------------------------------------------------
5736  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW
5737  * [31:5] | ??? | 0x0 | *UNDEFINED*
5738  *
5739  */
5740 /*
5741  * Field : low
5742  *
5743  * defines the 5 bit LSB of the base extended address field.
5744  *
5745  * Field Access Macros:
5746  *
5747  */
5748 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW register field. */
5749 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW_LSB 0
5750 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW register field. */
5751 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW_MSB 4
5752 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW register field. */
5753 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW_WIDTH 5
5754 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW register field value. */
5755 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
5756 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW register field value. */
5757 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
5758 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW register field. */
5759 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW_RESET 0x0
5760 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW field value from a register. */
5761 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
5762 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW register field value suitable for setting the register. */
5763 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
5764 
5765 #ifndef __ASSEMBLY__
5766 /*
5767  * WARNING: The C register and register group struct declarations are provided for
5768  * convenience and illustrative purposes. They should, however, be used with
5769  * caution as the C language standard provides no guarantees about the alignment or
5770  * atomicity of device memory accesses. The recommended practice for coding device
5771  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5772  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5773  * alt_write_dword() functions for 64 bit registers.
5774  *
5775  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT.
5776  */
5777 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_s
5778 {
5779  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW */
5780  uint32_t : 27; /* *UNDEFINED* */
5781 };
5782 
5783 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT. */
5784 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_t;
5785 #endif /* __ASSEMBLY__ */
5786 
5787 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT register. */
5788 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_RESET 0x00000000
5789 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT register from the beginning of the component. */
5790 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_OFST 0xe4
5791 
5792 /*
5793  * Register : nonmpuregion5addr_limit
5794  *
5795  * Limit definition for non MPU Region 5
5796  *
5797  * Register Layout
5798  *
5799  * Bits | Access | Reset | Description
5800  * :--------|:-------|:-------|:----------------------------------------------------
5801  * [15:0] | R | 0xffff | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW
5802  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH
5803  *
5804  */
5805 /*
5806  * Field : low
5807  *
5808  * LSB field is all one. Region end address is {limitext,limit, 16'hFFFF}
5809  *
5810  * Field Access Macros:
5811  *
5812  */
5813 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW register field. */
5814 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW_LSB 0
5815 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW register field. */
5816 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW_MSB 15
5817 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW register field. */
5818 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW_WIDTH 16
5819 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW register field value. */
5820 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
5821 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW register field value. */
5822 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
5823 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW register field. */
5824 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW_RESET 0xffff
5825 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW field value from a register. */
5826 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
5827 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW register field value suitable for setting the register. */
5828 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
5829 
5830 /*
5831  * Field : high
5832  *
5833  * defines the 16 bit MSB of the limit address field.
5834  *
5835  * Field Access Macros:
5836  *
5837  */
5838 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH register field. */
5839 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH_LSB 16
5840 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH register field. */
5841 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH_MSB 31
5842 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH register field. */
5843 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH_WIDTH 16
5844 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH register field value. */
5845 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
5846 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH register field value. */
5847 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
5848 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH register field. */
5849 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH_RESET 0x0
5850 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH field value from a register. */
5851 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
5852 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH register field value suitable for setting the register. */
5853 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
5854 
5855 #ifndef __ASSEMBLY__
5856 /*
5857  * WARNING: The C register and register group struct declarations are provided for
5858  * convenience and illustrative purposes. They should, however, be used with
5859  * caution as the C language standard provides no guarantees about the alignment or
5860  * atomicity of device memory accesses. The recommended practice for coding device
5861  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5862  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5863  * alt_write_dword() functions for 64 bit registers.
5864  *
5865  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT.
5866  */
5867 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_s
5868 {
5869  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW */
5870  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH */
5871 };
5872 
5873 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT. */
5874 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_t;
5875 #endif /* __ASSEMBLY__ */
5876 
5877 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT register. */
5878 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_RESET 0x0000ffff
5879 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT register from the beginning of the component. */
5880 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_OFST 0xe8
5881 
5882 /*
5883  * Register : nonmpuregion5addr_limitext
5884  *
5885  * limit extended definition for non MPU Region 5
5886  *
5887  * Register Layout
5888  *
5889  * Bits | Access | Reset | Description
5890  * :-------|:-------|:------|:------------------------------------------------------
5891  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW
5892  * [31:5] | ??? | 0x0 | *UNDEFINED*
5893  *
5894  */
5895 /*
5896  * Field : low
5897  *
5898  * defines the 5 bit LSB of the limit extended address field.
5899  *
5900  * Field Access Macros:
5901  *
5902  */
5903 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW register field. */
5904 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW_LSB 0
5905 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW register field. */
5906 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW_MSB 4
5907 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW register field. */
5908 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW_WIDTH 5
5909 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW register field value. */
5910 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
5911 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW register field value. */
5912 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
5913 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW register field. */
5914 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW_RESET 0x0
5915 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW field value from a register. */
5916 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
5917 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW register field value suitable for setting the register. */
5918 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
5919 
5920 #ifndef __ASSEMBLY__
5921 /*
5922  * WARNING: The C register and register group struct declarations are provided for
5923  * convenience and illustrative purposes. They should, however, be used with
5924  * caution as the C language standard provides no guarantees about the alignment or
5925  * atomicity of device memory accesses. The recommended practice for coding device
5926  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5927  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5928  * alt_write_dword() functions for 64 bit registers.
5929  *
5930  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT.
5931  */
5932 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_s
5933 {
5934  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW */
5935  uint32_t : 27; /* *UNDEFINED* */
5936 };
5937 
5938 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT. */
5939 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_t;
5940 #endif /* __ASSEMBLY__ */
5941 
5942 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT register. */
5943 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_RESET 0x00000000
5944 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT register from the beginning of the component. */
5945 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_OFST 0xec
5946 
5947 /*
5948  * Register : nonmpuregion6addr_base
5949  *
5950  * Base definition for non MPU Region 6
5951  *
5952  * Register Layout
5953  *
5954  * Bits | Access | Reset | Description
5955  * :--------|:-------|:------|:---------------------------------------------------
5956  * [15:0] | R | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW
5957  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH
5958  *
5959  */
5960 /*
5961  * Field : low
5962  *
5963  * LSB field is all zeros. Region start address is {baseext,base, 16'h000}
5964  *
5965  * Field Access Macros:
5966  *
5967  */
5968 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW register field. */
5969 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW_LSB 0
5970 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW register field. */
5971 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW_MSB 15
5972 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW register field. */
5973 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW_WIDTH 16
5974 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW register field value. */
5975 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW_SET_MSK 0x0000ffff
5976 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW register field value. */
5977 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW_CLR_MSK 0xffff0000
5978 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW register field. */
5979 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW_RESET 0x0
5980 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW field value from a register. */
5981 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
5982 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW register field value suitable for setting the register. */
5983 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
5984 
5985 /*
5986  * Field : high
5987  *
5988  * defines the 16 bit MSB of the base address field.
5989  *
5990  * Field Access Macros:
5991  *
5992  */
5993 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH register field. */
5994 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH_LSB 16
5995 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH register field. */
5996 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH_MSB 31
5997 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH register field. */
5998 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH_WIDTH 16
5999 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH register field value. */
6000 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH_SET_MSK 0xffff0000
6001 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH register field value. */
6002 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
6003 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH register field. */
6004 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH_RESET 0x0
6005 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH field value from a register. */
6006 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
6007 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH register field value suitable for setting the register. */
6008 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
6009 
6010 #ifndef __ASSEMBLY__
6011 /*
6012  * WARNING: The C register and register group struct declarations are provided for
6013  * convenience and illustrative purposes. They should, however, be used with
6014  * caution as the C language standard provides no guarantees about the alignment or
6015  * atomicity of device memory accesses. The recommended practice for coding device
6016  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6017  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6018  * alt_write_dword() functions for 64 bit registers.
6019  *
6020  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE.
6021  */
6022 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_s
6023 {
6024  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW */
6025  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH */
6026 };
6027 
6028 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE. */
6029 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_t;
6030 #endif /* __ASSEMBLY__ */
6031 
6032 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE register. */
6033 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_RESET 0x00000000
6034 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE register from the beginning of the component. */
6035 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_OFST 0xf0
6036 
6037 /*
6038  * Register : nonmpuregion6addr_baseext
6039  *
6040  * base extended definition for non MPU Region 6
6041  *
6042  * Register Layout
6043  *
6044  * Bits | Access | Reset | Description
6045  * :-------|:-------|:------|:-----------------------------------------------------
6046  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW
6047  * [31:5] | ??? | 0x0 | *UNDEFINED*
6048  *
6049  */
6050 /*
6051  * Field : low
6052  *
6053  * defines the 5 bit LSB of the base extended address field.
6054  *
6055  * Field Access Macros:
6056  *
6057  */
6058 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW register field. */
6059 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW_LSB 0
6060 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW register field. */
6061 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW_MSB 4
6062 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW register field. */
6063 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW_WIDTH 5
6064 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW register field value. */
6065 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
6066 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW register field value. */
6067 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
6068 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW register field. */
6069 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW_RESET 0x0
6070 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW field value from a register. */
6071 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
6072 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW register field value suitable for setting the register. */
6073 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
6074 
6075 #ifndef __ASSEMBLY__
6076 /*
6077  * WARNING: The C register and register group struct declarations are provided for
6078  * convenience and illustrative purposes. They should, however, be used with
6079  * caution as the C language standard provides no guarantees about the alignment or
6080  * atomicity of device memory accesses. The recommended practice for coding device
6081  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6082  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6083  * alt_write_dword() functions for 64 bit registers.
6084  *
6085  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT.
6086  */
6087 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_s
6088 {
6089  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW */
6090  uint32_t : 27; /* *UNDEFINED* */
6091 };
6092 
6093 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT. */
6094 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_t;
6095 #endif /* __ASSEMBLY__ */
6096 
6097 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT register. */
6098 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_RESET 0x00000000
6099 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT register from the beginning of the component. */
6100 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_OFST 0xf4
6101 
6102 /*
6103  * Register : nonmpuregion6addr_limit
6104  *
6105  * Limit definition for non MPU Region 6
6106  *
6107  * Register Layout
6108  *
6109  * Bits | Access | Reset | Description
6110  * :--------|:-------|:-------|:----------------------------------------------------
6111  * [15:0] | R | 0xffff | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW
6112  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH
6113  *
6114  */
6115 /*
6116  * Field : low
6117  *
6118  * LSB field is all one. Region end address is {limitext,limit, 16'hFFFF}
6119  *
6120  * Field Access Macros:
6121  *
6122  */
6123 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW register field. */
6124 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW_LSB 0
6125 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW register field. */
6126 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW_MSB 15
6127 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW register field. */
6128 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW_WIDTH 16
6129 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW register field value. */
6130 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
6131 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW register field value. */
6132 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
6133 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW register field. */
6134 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW_RESET 0xffff
6135 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW field value from a register. */
6136 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
6137 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW register field value suitable for setting the register. */
6138 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
6139 
6140 /*
6141  * Field : high
6142  *
6143  * defines the 16 bit MSB of the limit address field.
6144  *
6145  * Field Access Macros:
6146  *
6147  */
6148 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH register field. */
6149 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH_LSB 16
6150 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH register field. */
6151 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH_MSB 31
6152 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH register field. */
6153 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH_WIDTH 16
6154 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH register field value. */
6155 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
6156 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH register field value. */
6157 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
6158 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH register field. */
6159 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH_RESET 0x0
6160 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH field value from a register. */
6161 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
6162 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH register field value suitable for setting the register. */
6163 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
6164 
6165 #ifndef __ASSEMBLY__
6166 /*
6167  * WARNING: The C register and register group struct declarations are provided for
6168  * convenience and illustrative purposes. They should, however, be used with
6169  * caution as the C language standard provides no guarantees about the alignment or
6170  * atomicity of device memory accesses. The recommended practice for coding device
6171  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6172  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6173  * alt_write_dword() functions for 64 bit registers.
6174  *
6175  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT.
6176  */
6177 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_s
6178 {
6179  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW */
6180  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH */
6181 };
6182 
6183 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT. */
6184 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_t;
6185 #endif /* __ASSEMBLY__ */
6186 
6187 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT register. */
6188 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_RESET 0x0000ffff
6189 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT register from the beginning of the component. */
6190 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_OFST 0xf8
6191 
6192 /*
6193  * Register : nonmpuregion6addr_limitext
6194  *
6195  * limit extended definition for non MPU Region 6
6196  *
6197  * Register Layout
6198  *
6199  * Bits | Access | Reset | Description
6200  * :-------|:-------|:------|:------------------------------------------------------
6201  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW
6202  * [31:5] | ??? | 0x0 | *UNDEFINED*
6203  *
6204  */
6205 /*
6206  * Field : low
6207  *
6208  * defines the 5 bit LSB of the limit extended address field.
6209  *
6210  * Field Access Macros:
6211  *
6212  */
6213 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW register field. */
6214 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW_LSB 0
6215 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW register field. */
6216 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW_MSB 4
6217 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW register field. */
6218 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW_WIDTH 5
6219 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW register field value. */
6220 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
6221 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW register field value. */
6222 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
6223 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW register field. */
6224 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW_RESET 0x0
6225 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW field value from a register. */
6226 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
6227 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW register field value suitable for setting the register. */
6228 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
6229 
6230 #ifndef __ASSEMBLY__
6231 /*
6232  * WARNING: The C register and register group struct declarations are provided for
6233  * convenience and illustrative purposes. They should, however, be used with
6234  * caution as the C language standard provides no guarantees about the alignment or
6235  * atomicity of device memory accesses. The recommended practice for coding device
6236  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6237  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6238  * alt_write_dword() functions for 64 bit registers.
6239  *
6240  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT.
6241  */
6242 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_s
6243 {
6244  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW */
6245  uint32_t : 27; /* *UNDEFINED* */
6246 };
6247 
6248 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT. */
6249 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_t;
6250 #endif /* __ASSEMBLY__ */
6251 
6252 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT register. */
6253 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_RESET 0x00000000
6254 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT register from the beginning of the component. */
6255 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_OFST 0xfc
6256 
6257 /*
6258  * Register : nonmpuregion7addr_base
6259  *
6260  * Base definition for non MPU Region 7
6261  *
6262  * Register Layout
6263  *
6264  * Bits | Access | Reset | Description
6265  * :--------|:-------|:------|:---------------------------------------------------
6266  * [15:0] | R | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW
6267  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH
6268  *
6269  */
6270 /*
6271  * Field : low
6272  *
6273  * LSB field is all zeros. Region start address is {baseext,base, 16'h000}
6274  *
6275  * Field Access Macros:
6276  *
6277  */
6278 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW register field. */
6279 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW_LSB 0
6280 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW register field. */
6281 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW_MSB 15
6282 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW register field. */
6283 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW_WIDTH 16
6284 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW register field value. */
6285 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW_SET_MSK 0x0000ffff
6286 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW register field value. */
6287 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW_CLR_MSK 0xffff0000
6288 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW register field. */
6289 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW_RESET 0x0
6290 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW field value from a register. */
6291 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
6292 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW register field value suitable for setting the register. */
6293 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
6294 
6295 /*
6296  * Field : high
6297  *
6298  * defines the 16 bit MSB of the base address field.
6299  *
6300  * Field Access Macros:
6301  *
6302  */
6303 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH register field. */
6304 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH_LSB 16
6305 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH register field. */
6306 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH_MSB 31
6307 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH register field. */
6308 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH_WIDTH 16
6309 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH register field value. */
6310 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH_SET_MSK 0xffff0000
6311 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH register field value. */
6312 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
6313 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH register field. */
6314 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH_RESET 0x0
6315 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH field value from a register. */
6316 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
6317 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH register field value suitable for setting the register. */
6318 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
6319 
6320 #ifndef __ASSEMBLY__
6321 /*
6322  * WARNING: The C register and register group struct declarations are provided for
6323  * convenience and illustrative purposes. They should, however, be used with
6324  * caution as the C language standard provides no guarantees about the alignment or
6325  * atomicity of device memory accesses. The recommended practice for coding device
6326  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6327  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6328  * alt_write_dword() functions for 64 bit registers.
6329  *
6330  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE.
6331  */
6332 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_s
6333 {
6334  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW */
6335  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH */
6336 };
6337 
6338 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE. */
6339 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_t;
6340 #endif /* __ASSEMBLY__ */
6341 
6342 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE register. */
6343 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_RESET 0x00000000
6344 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE register from the beginning of the component. */
6345 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_OFST 0x100
6346 
6347 /*
6348  * Register : nonmpuregion7addr_baseext
6349  *
6350  * base extended definition for non MPU Region 7
6351  *
6352  * Register Layout
6353  *
6354  * Bits | Access | Reset | Description
6355  * :-------|:-------|:------|:-----------------------------------------------------
6356  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW
6357  * [31:5] | ??? | 0x0 | *UNDEFINED*
6358  *
6359  */
6360 /*
6361  * Field : low
6362  *
6363  * defines the 5 bit LSB of the base extended address field.
6364  *
6365  * Field Access Macros:
6366  *
6367  */
6368 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW register field. */
6369 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW_LSB 0
6370 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW register field. */
6371 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW_MSB 4
6372 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW register field. */
6373 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW_WIDTH 5
6374 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW register field value. */
6375 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
6376 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW register field value. */
6377 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
6378 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW register field. */
6379 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW_RESET 0x0
6380 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW field value from a register. */
6381 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
6382 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW register field value suitable for setting the register. */
6383 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
6384 
6385 #ifndef __ASSEMBLY__
6386 /*
6387  * WARNING: The C register and register group struct declarations are provided for
6388  * convenience and illustrative purposes. They should, however, be used with
6389  * caution as the C language standard provides no guarantees about the alignment or
6390  * atomicity of device memory accesses. The recommended practice for coding device
6391  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6392  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6393  * alt_write_dword() functions for 64 bit registers.
6394  *
6395  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT.
6396  */
6397 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_s
6398 {
6399  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW */
6400  uint32_t : 27; /* *UNDEFINED* */
6401 };
6402 
6403 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT. */
6404 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_t;
6405 #endif /* __ASSEMBLY__ */
6406 
6407 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT register. */
6408 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_RESET 0x00000000
6409 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT register from the beginning of the component. */
6410 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_OFST 0x104
6411 
6412 /*
6413  * Register : nonmpuregion7addr_limit
6414  *
6415  * Limit definition for non MPU Region 7
6416  *
6417  * Register Layout
6418  *
6419  * Bits | Access | Reset | Description
6420  * :--------|:-------|:-------|:----------------------------------------------------
6421  * [15:0] | R | 0xffff | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW
6422  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH
6423  *
6424  */
6425 /*
6426  * Field : low
6427  *
6428  * LSB field is all one. Region end address is {limitext,limit, 16'hFFFF}
6429  *
6430  * Field Access Macros:
6431  *
6432  */
6433 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW register field. */
6434 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW_LSB 0
6435 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW register field. */
6436 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW_MSB 15
6437 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW register field. */
6438 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW_WIDTH 16
6439 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW register field value. */
6440 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
6441 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW register field value. */
6442 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
6443 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW register field. */
6444 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW_RESET 0xffff
6445 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW field value from a register. */
6446 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
6447 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW register field value suitable for setting the register. */
6448 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
6449 
6450 /*
6451  * Field : high
6452  *
6453  * defines the 16 bit MSB of the limit address field.
6454  *
6455  * Field Access Macros:
6456  *
6457  */
6458 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH register field. */
6459 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH_LSB 16
6460 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH register field. */
6461 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH_MSB 31
6462 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH register field. */
6463 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH_WIDTH 16
6464 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH register field value. */
6465 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
6466 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH register field value. */
6467 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
6468 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH register field. */
6469 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH_RESET 0x0
6470 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH field value from a register. */
6471 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
6472 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH register field value suitable for setting the register. */
6473 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
6474 
6475 #ifndef __ASSEMBLY__
6476 /*
6477  * WARNING: The C register and register group struct declarations are provided for
6478  * convenience and illustrative purposes. They should, however, be used with
6479  * caution as the C language standard provides no guarantees about the alignment or
6480  * atomicity of device memory accesses. The recommended practice for coding device
6481  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6482  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6483  * alt_write_dword() functions for 64 bit registers.
6484  *
6485  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT.
6486  */
6487 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_s
6488 {
6489  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW */
6490  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH */
6491 };
6492 
6493 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT. */
6494 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_t;
6495 #endif /* __ASSEMBLY__ */
6496 
6497 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT register. */
6498 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_RESET 0x0000ffff
6499 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT register from the beginning of the component. */
6500 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_OFST 0x108
6501 
6502 /*
6503  * Register : nonmpuregion7addr_limitext
6504  *
6505  * limit extended definition for non MPU Region 7
6506  *
6507  * Register Layout
6508  *
6509  * Bits | Access | Reset | Description
6510  * :-------|:-------|:------|:------------------------------------------------------
6511  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW
6512  * [31:5] | ??? | 0x0 | *UNDEFINED*
6513  *
6514  */
6515 /*
6516  * Field : low
6517  *
6518  * defines the 5 bit LSB of the limit extended address field.
6519  *
6520  * Field Access Macros:
6521  *
6522  */
6523 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW register field. */
6524 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW_LSB 0
6525 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW register field. */
6526 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW_MSB 4
6527 /* The width in bits of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW register field. */
6528 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW_WIDTH 5
6529 /* The mask used to set the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW register field value. */
6530 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
6531 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW register field value. */
6532 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
6533 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW register field. */
6534 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW_RESET 0x0
6535 /* Extracts the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW field value from a register. */
6536 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
6537 /* Produces a ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW register field value suitable for setting the register. */
6538 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
6539 
6540 #ifndef __ASSEMBLY__
6541 /*
6542  * WARNING: The C register and register group struct declarations are provided for
6543  * convenience and illustrative purposes. They should, however, be used with
6544  * caution as the C language standard provides no guarantees about the alignment or
6545  * atomicity of device memory accesses. The recommended practice for coding device
6546  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6547  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6548  * alt_write_dword() functions for 64 bit registers.
6549  *
6550  * The struct declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT.
6551  */
6552 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_s
6553 {
6554  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW */
6555  uint32_t : 27; /* *UNDEFINED* */
6556 };
6557 
6558 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT. */
6559 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_t;
6560 #endif /* __ASSEMBLY__ */
6561 
6562 /* The reset value of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT register. */
6563 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_RESET 0x00000000
6564 /* The byte offset of the ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT register from the beginning of the component. */
6565 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_OFST 0x10c
6566 
6567 #ifndef __ASSEMBLY__
6568 /*
6569  * WARNING: The C register and register group struct declarations are provided for
6570  * convenience and illustrative purposes. They should, however, be used with
6571  * caution as the C language standard provides no guarantees about the alignment or
6572  * atomicity of device memory accesses. The recommended practice for coding device
6573  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6574  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6575  * alt_write_dword() functions for 64 bit registers.
6576  *
6577  * The struct declaration for register group ALT_SOC_NOC_FW_DDR_SCR.
6578  */
6579 struct ALT_SOC_NOC_FW_DDR_SCR_s
6580 {
6581  volatile ALT_SOC_NOC_FW_DDR_SCR_ENABLE_t enable; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE */
6582  volatile ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_t enable_set; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET */
6583  volatile ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_t enable_clear; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR */
6584  volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
6585  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_t mpuregion0addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE */
6586  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_t mpuregion0addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT */
6587  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_t mpuregion0addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT */
6588  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_t mpuregion0addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT */
6589  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_t mpuregion1addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE */
6590  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_t mpuregion1addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT */
6591  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_t mpuregion1addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT */
6592  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_t mpuregion1addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT */
6593  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_t mpuregion2addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE */
6594  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_t mpuregion2addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT */
6595  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_t mpuregion2addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT */
6596  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_t mpuregion2addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT */
6597  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_t mpuregion3addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE */
6598  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_t mpuregion3addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT */
6599  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_t mpuregion3addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT */
6600  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_t mpuregion3addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT */
6601  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_t mpuregion4addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE */
6602  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_t mpuregion4addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT */
6603  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_t mpuregion4addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT */
6604  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_t mpuregion4addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT */
6605  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_t mpuregion5addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE */
6606  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_t mpuregion5addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT */
6607  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_t mpuregion5addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT */
6608  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_t mpuregion5addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT */
6609  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_t mpuregion6addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE */
6610  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_t mpuregion6addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT */
6611  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_t mpuregion6addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT */
6612  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_t mpuregion6addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT */
6613  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_t mpuregion7addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE */
6614  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_t mpuregion7addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT */
6615  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_t mpuregion7addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT */
6616  volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_t mpuregion7addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT */
6617  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_t nonmpuregion0addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE */
6618  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_t nonmpuregion0addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT */
6619  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_t nonmpuregion0addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT */
6620  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_t nonmpuregion0addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT */
6621  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_t nonmpuregion1addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE */
6622  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_t nonmpuregion1addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT */
6623  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_t nonmpuregion1addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT */
6624  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_t nonmpuregion1addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT */
6625  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_t nonmpuregion2addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE */
6626  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_t nonmpuregion2addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT */
6627  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_t nonmpuregion2addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT */
6628  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_t nonmpuregion2addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT */
6629  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_t nonmpuregion3addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE */
6630  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_t nonmpuregion3addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT */
6631  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_t nonmpuregion3addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT */
6632  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_t nonmpuregion3addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT */
6633  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_t nonmpuregion4addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE */
6634  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_t nonmpuregion4addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT */
6635  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_t nonmpuregion4addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT */
6636  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_t nonmpuregion4addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT */
6637  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_t nonmpuregion5addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE */
6638  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_t nonmpuregion5addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT */
6639  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_t nonmpuregion5addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT */
6640  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_t nonmpuregion5addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT */
6641  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_t nonmpuregion6addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE */
6642  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_t nonmpuregion6addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT */
6643  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_t nonmpuregion6addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT */
6644  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_t nonmpuregion6addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT */
6645  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_t nonmpuregion7addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE */
6646  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_t nonmpuregion7addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT */
6647  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_t nonmpuregion7addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT */
6648  volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_t nonmpuregion7addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT */
6649  volatile uint32_t _pad_0x110_0x100; /* *UNDEFINED* */
6650 };
6651 
6652 /* The typedef declaration for register group ALT_SOC_NOC_FW_DDR_SCR. */
6653 typedef struct ALT_SOC_NOC_FW_DDR_SCR_s ALT_SOC_NOC_FW_DDR_SCR_t;
6654 /* The struct declaration for the raw register contents of register group ALT_SOC_NOC_FW_DDR_SCR. */
6655 struct ALT_SOC_NOC_FW_DDR_SCR_raw_s
6656 {
6657  volatile uint32_t enable; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE */
6658  volatile uint32_t enable_set; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET */
6659  volatile uint32_t enable_clear; /* ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR */
6660  volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
6661  volatile uint32_t mpuregion0addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE */
6662  volatile uint32_t mpuregion0addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT */
6663  volatile uint32_t mpuregion0addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT */
6664  volatile uint32_t mpuregion0addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT */
6665  volatile uint32_t mpuregion1addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE */
6666  volatile uint32_t mpuregion1addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT */
6667  volatile uint32_t mpuregion1addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT */
6668  volatile uint32_t mpuregion1addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT */
6669  volatile uint32_t mpuregion2addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE */
6670  volatile uint32_t mpuregion2addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT */
6671  volatile uint32_t mpuregion2addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT */
6672  volatile uint32_t mpuregion2addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT */
6673  volatile uint32_t mpuregion3addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE */
6674  volatile uint32_t mpuregion3addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT */
6675  volatile uint32_t mpuregion3addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT */
6676  volatile uint32_t mpuregion3addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT */
6677  volatile uint32_t mpuregion4addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE */
6678  volatile uint32_t mpuregion4addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT */
6679  volatile uint32_t mpuregion4addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT */
6680  volatile uint32_t mpuregion4addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT */
6681  volatile uint32_t mpuregion5addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE */
6682  volatile uint32_t mpuregion5addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT */
6683  volatile uint32_t mpuregion5addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT */
6684  volatile uint32_t mpuregion5addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT */
6685  volatile uint32_t mpuregion6addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE */
6686  volatile uint32_t mpuregion6addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT */
6687  volatile uint32_t mpuregion6addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT */
6688  volatile uint32_t mpuregion6addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT */
6689  volatile uint32_t mpuregion7addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE */
6690  volatile uint32_t mpuregion7addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT */
6691  volatile uint32_t mpuregion7addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT */
6692  volatile uint32_t mpuregion7addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT */
6693  volatile uint32_t nonmpuregion0addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE */
6694  volatile uint32_t nonmpuregion0addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT */
6695  volatile uint32_t nonmpuregion0addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT */
6696  volatile uint32_t nonmpuregion0addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT */
6697  volatile uint32_t nonmpuregion1addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE */
6698  volatile uint32_t nonmpuregion1addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT */
6699  volatile uint32_t nonmpuregion1addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT */
6700  volatile uint32_t nonmpuregion1addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT */
6701  volatile uint32_t nonmpuregion2addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE */
6702  volatile uint32_t nonmpuregion2addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT */
6703  volatile uint32_t nonmpuregion2addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT */
6704  volatile uint32_t nonmpuregion2addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT */
6705  volatile uint32_t nonmpuregion3addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE */
6706  volatile uint32_t nonmpuregion3addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT */
6707  volatile uint32_t nonmpuregion3addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT */
6708  volatile uint32_t nonmpuregion3addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT */
6709  volatile uint32_t nonmpuregion4addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE */
6710  volatile uint32_t nonmpuregion4addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT */
6711  volatile uint32_t nonmpuregion4addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT */
6712  volatile uint32_t nonmpuregion4addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT */
6713  volatile uint32_t nonmpuregion5addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE */
6714  volatile uint32_t nonmpuregion5addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT */
6715  volatile uint32_t nonmpuregion5addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT */
6716  volatile uint32_t nonmpuregion5addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT */
6717  volatile uint32_t nonmpuregion6addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE */
6718  volatile uint32_t nonmpuregion6addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT */
6719  volatile uint32_t nonmpuregion6addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT */
6720  volatile uint32_t nonmpuregion6addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT */
6721  volatile uint32_t nonmpuregion7addr_base; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE */
6722  volatile uint32_t nonmpuregion7addr_baseext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT */
6723  volatile uint32_t nonmpuregion7addr_limit; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT */
6724  volatile uint32_t nonmpuregion7addr_limitext; /* ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT */
6725  volatile uint32_t _pad_0x110_0x100; /* *UNDEFINED* */
6726 };
6727 
6728 /* The typedef declaration for the raw register contents of register group ALT_SOC_NOC_FW_DDR_SCR. */
6729 typedef struct ALT_SOC_NOC_FW_DDR_SCR_raw_s ALT_SOC_NOC_FW_DDR_SCR_raw_t;
6730 #endif /* __ASSEMBLY__ */
6731 
6732 
6733 #ifdef __cplusplus
6734 }
6735 #endif /* __cplusplus */
6736 #endif /* __ALT_SOCAL_SOC_NOC_FW_DDR_SCR_H__ */
6737