Hardware Libraries  20.1
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alt_uart.h
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32 
33 /* Altera - ALT_UART */
34 
35 #ifndef __ALTERA_ALT_UART_H__
36 #define __ALTERA_ALT_UART_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
43 /*
44  * Component : UART Module - ALT_UART
45  * UART Module
46  *
47  * Registers in the UART module
48  *
49  */
50 /*
51  * Register : Rx Buffer, Tx Holding, and Divisor Latch Low - rbr_thr_dll
52  *
53  * This is a multi-function register. This register holds receives and transmit
54  * data and controls the least-signficant 8 bits of the baud rate divisor.
55  *
56  * Register Layout
57  *
58  * Bits | Access | Reset | Description
59  * :-------|:-------|:------|:------------
60  * [7:0] | RW | 0x0 | Value
61  * [31:8] | ??? | 0x0 | *UNDEFINED*
62  *
63  */
64 /*
65  * Field : Value - value
66  *
67  * Receive Buffer Register:
68  *
69  * This register contains the data byte received on the serial input port
70  * (uart_rxd). The data in this register is valid only if the Data Ready ( bit [0]
71  * in the Line Status Register(LSR)) is set to 1. If FIFOs are disabled(bit[0] of
72  * Register FCR is set to 0) the data in the RBR must be read before the next data
73  * arrives, otherwise it will be overwritten, resulting in an overrun error. If
74  * FIFOs are enabled(bit [0] of Register FCR is set to 1) this register accesses
75  * the head of the receive FIFO. If the receive FIFO is full, and this register is
76  * not read before the next data character arrives, then the data already in the
77  * FIFO will be preserved but any incoming data will be lost. An overrun error will
78  * also occur.
79  *
80  * Transmit Holding Register:
81  *
82  * This register contains data to be transmitted on the serial output port. Data
83  * should only be written to the THR when the THR Empty bit [5] of the LSR Register
84  * is set to 1. If FIFOs are disabled (bit [0] of Register FCR) is set to 0 and
85  * THRE is set to 1, writing a single character to the THR clears the THRE. Any
86  * additional writes to the THR before the THRE is set again causes the THR data to
87  * be overwritten. If FIFO's are enabled bit [0] of Register FCR is set to 1 and
88  * THRE is set up to 128 characters of data may be written to the THR before the
89  * FIFO is full. Any attempt to write data when the FIFO is full results in the
90  * write data being lost.
91  *
92  * Divisor Latch Low:
93  *
94  * This register makes up the lower 8-bits of a 16-bit, Read/write, Divisor Latch
95  * register that contains the baud rate divisor for the UART. This register may
96  * only be accessed when the DLAB bit [7] of the LCR Register is set to 1. The
97  * output baud rate is equal to the serial clock l4_sp_clk frequency divided by
98  * sixteen times the value of the baud rate divisor, as follows:
99  *
100  * baud rate = (serial clock freq) / (16 * divisor)
101  *
102  * Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud
103  * clock is disabled and no serial communications will occur. Also, once the DLL is
104  * set, at least 8 l4_sp_clk clock cycles should be allowed to pass before
105  * transmitting or receiving data.
106  *
107  * Field Access Macros:
108  *
109  */
110 /* The Least Significant Bit (LSB) position of the ALT_UART_RBR_THR_DLL_VALUE register field. */
111 #define ALT_UART_RBR_THR_DLL_VALUE_LSB 0
112 /* The Most Significant Bit (MSB) position of the ALT_UART_RBR_THR_DLL_VALUE register field. */
113 #define ALT_UART_RBR_THR_DLL_VALUE_MSB 7
114 /* The width in bits of the ALT_UART_RBR_THR_DLL_VALUE register field. */
115 #define ALT_UART_RBR_THR_DLL_VALUE_WIDTH 8
116 /* The mask used to set the ALT_UART_RBR_THR_DLL_VALUE register field value. */
117 #define ALT_UART_RBR_THR_DLL_VALUE_SET_MSK 0x000000ff
118 /* The mask used to clear the ALT_UART_RBR_THR_DLL_VALUE register field value. */
119 #define ALT_UART_RBR_THR_DLL_VALUE_CLR_MSK 0xffffff00
120 /* The reset value of the ALT_UART_RBR_THR_DLL_VALUE register field. */
121 #define ALT_UART_RBR_THR_DLL_VALUE_RESET 0x0
122 /* Extracts the ALT_UART_RBR_THR_DLL_VALUE field value from a register. */
123 #define ALT_UART_RBR_THR_DLL_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
124 /* Produces a ALT_UART_RBR_THR_DLL_VALUE register field value suitable for setting the register. */
125 #define ALT_UART_RBR_THR_DLL_VALUE_SET(value) (((value) << 0) & 0x000000ff)
126 
127 #ifndef __ASSEMBLY__
128 /*
129  * WARNING: The C register and register group struct declarations are provided for
130  * convenience and illustrative purposes. They should, however, be used with
131  * caution as the C language standard provides no guarantees about the alignment or
132  * atomicity of device memory accesses. The recommended practice for writing
133  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
134  * alt_write_word() functions.
135  *
136  * The struct declaration for register ALT_UART_RBR_THR_DLL.
137  */
138 struct ALT_UART_RBR_THR_DLL_s
139 {
140  uint32_t value : 8; /* Value */
141  uint32_t : 24; /* *UNDEFINED* */
142 };
143 
144 /* The typedef declaration for register ALT_UART_RBR_THR_DLL. */
145 typedef volatile struct ALT_UART_RBR_THR_DLL_s ALT_UART_RBR_THR_DLL_t;
146 #endif /* __ASSEMBLY__ */
147 
148 /* The byte offset of the ALT_UART_RBR_THR_DLL register from the beginning of the component. */
149 #define ALT_UART_RBR_THR_DLL_OFST 0x0
150 /* The address of the ALT_UART_RBR_THR_DLL register. */
151 #define ALT_UART_RBR_THR_DLL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RBR_THR_DLL_OFST))
152 
153 /*
154  * Register : Interrupt Enable and Divisor Latch High - ier_dlh
155  *
156  * This is a multi-function register. This register enables/disables receive and
157  * transmit interrupts and also controls the most-significant 8-bits of the baud
158  * rate divisor.
159  *
160  * Divisor Latch High Register:
161  *
162  * This register is accessed when the DLAB bit [7] of the LCR Register is set to
163  * 1.Bits[7:0] contain the high order 8-bits of the baud rate divisor.The output
164  * baud rate is equal to the serial clock l4_sp_clk frequency divided by sixteen
165  * times the value of the baud rate divisor, as follows:
166  *
167  * baud rate = (serial clock freq) / (16 * divisor):
168  *
169  * Note that with the Divisor Latch Registers (DLLand DLH) set to zero, the baud
170  * clock is disabled and no serial communications will occur. Also, once the DLL is
171  * set, at least 8 l4_sp_clk clock cycles should be allowed to pass before
172  * transmitting or receiving data.
173  *
174  * Interrupt Enable Register:
175  *
176  * This register may only be accessed when the DLAB bit [7] of the LCR Register is
177  * set to 0.Allows control of the Interrupt Enables for transmit and receive
178  * functions.
179  *
180  * Register Layout
181  *
182  * Bits | Access | Reset | Description
183  * :-------|:-------|:------|:--------------------------------------------
184  * [0] | RW | 0x0 | DLH[0] and Receive Data Interrupt Enable
185  * [1] | RW | 0x0 | DLH[1] and Transmit Data Interrupt Control
186  * [2] | RW | 0x0 | DLH[2] and Enable Receiver Line Status
187  * [3] | RW | 0x0 | DLH[3] and Enable Modem Status Interrupt
188  * [4] | RW | 0x0 | DLH[4]
189  * [5] | RW | 0x0 | DLH[5]
190  * [6] | RW | 0x0 | DLH[6]
191  * [7] | RW | 0x0 | DLH[7] and PTIME THRE Interrupt Mode Enable
192  * [31:8] | ??? | 0x0 | *UNDEFINED*
193  *
194  */
195 /*
196  * Field : DLH[0] and Receive Data Interrupt Enable - erbfi_dlh0
197  *
198  * Divisor Latch High Register:
199  *
200  * Bit 0 of DLH value.
201  *
202  * Interrupt Enable Register:
203  *
204  * Used to enable/disable the generation of the Receive Data Available Interrupt
205  * and the Character Timeout Interrupt(if FIFO's enabled). These are the second
206  * highest priority interrupts.
207  *
208  * Field Enumeration Values:
209  *
210  * Enum | Value | Description
211  * :-----------------------------------|:------|:------------------
212  * ALT_UART_IER_DLH_ERBFI_DLH0_E_DISD | 0x0 | Interrupt Disable
213  * ALT_UART_IER_DLH_ERBFI_DLH0_E_END | 0x1 | Interrupt Enable
214  *
215  * Field Access Macros:
216  *
217  */
218 /*
219  * Enumerated value for register field ALT_UART_IER_DLH_ERBFI_DLH0
220  *
221  * Interrupt Disable
222  */
223 #define ALT_UART_IER_DLH_ERBFI_DLH0_E_DISD 0x0
224 /*
225  * Enumerated value for register field ALT_UART_IER_DLH_ERBFI_DLH0
226  *
227  * Interrupt Enable
228  */
229 #define ALT_UART_IER_DLH_ERBFI_DLH0_E_END 0x1
230 
231 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */
232 #define ALT_UART_IER_DLH_ERBFI_DLH0_LSB 0
233 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */
234 #define ALT_UART_IER_DLH_ERBFI_DLH0_MSB 0
235 /* The width in bits of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */
236 #define ALT_UART_IER_DLH_ERBFI_DLH0_WIDTH 1
237 /* The mask used to set the ALT_UART_IER_DLH_ERBFI_DLH0 register field value. */
238 #define ALT_UART_IER_DLH_ERBFI_DLH0_SET_MSK 0x00000001
239 /* The mask used to clear the ALT_UART_IER_DLH_ERBFI_DLH0 register field value. */
240 #define ALT_UART_IER_DLH_ERBFI_DLH0_CLR_MSK 0xfffffffe
241 /* The reset value of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */
242 #define ALT_UART_IER_DLH_ERBFI_DLH0_RESET 0x0
243 /* Extracts the ALT_UART_IER_DLH_ERBFI_DLH0 field value from a register. */
244 #define ALT_UART_IER_DLH_ERBFI_DLH0_GET(value) (((value) & 0x00000001) >> 0)
245 /* Produces a ALT_UART_IER_DLH_ERBFI_DLH0 register field value suitable for setting the register. */
246 #define ALT_UART_IER_DLH_ERBFI_DLH0_SET(value) (((value) << 0) & 0x00000001)
247 
248 /*
249  * Field : DLH[1] and Transmit Data Interrupt Control - etbei_dlhl
250  *
251  * Divisor Latch High Register:
252  *
253  * Bit 1 of DLH value.
254  *
255  * Interrupt Enable Register:
256  *
257  * Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable
258  * the generation of Transmitter Holding Register Empty Interrupt. This is the
259  * third highest priority interrupt.
260  *
261  * Field Enumeration Values:
262  *
263  * Enum | Value | Description
264  * :-----------------------------------|:------|:------------
265  * ALT_UART_IER_DLH_ETBEI_DLHL_E_DISD | 0x0 | Tx disable
266  * ALT_UART_IER_DLH_ETBEI_DLHL_E_END | 0x1 | Tx enable
267  *
268  * Field Access Macros:
269  *
270  */
271 /*
272  * Enumerated value for register field ALT_UART_IER_DLH_ETBEI_DLHL
273  *
274  * Tx disable
275  */
276 #define ALT_UART_IER_DLH_ETBEI_DLHL_E_DISD 0x0
277 /*
278  * Enumerated value for register field ALT_UART_IER_DLH_ETBEI_DLHL
279  *
280  * Tx enable
281  */
282 #define ALT_UART_IER_DLH_ETBEI_DLHL_E_END 0x1
283 
284 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */
285 #define ALT_UART_IER_DLH_ETBEI_DLHL_LSB 1
286 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */
287 #define ALT_UART_IER_DLH_ETBEI_DLHL_MSB 1
288 /* The width in bits of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */
289 #define ALT_UART_IER_DLH_ETBEI_DLHL_WIDTH 1
290 /* The mask used to set the ALT_UART_IER_DLH_ETBEI_DLHL register field value. */
291 #define ALT_UART_IER_DLH_ETBEI_DLHL_SET_MSK 0x00000002
292 /* The mask used to clear the ALT_UART_IER_DLH_ETBEI_DLHL register field value. */
293 #define ALT_UART_IER_DLH_ETBEI_DLHL_CLR_MSK 0xfffffffd
294 /* The reset value of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */
295 #define ALT_UART_IER_DLH_ETBEI_DLHL_RESET 0x0
296 /* Extracts the ALT_UART_IER_DLH_ETBEI_DLHL field value from a register. */
297 #define ALT_UART_IER_DLH_ETBEI_DLHL_GET(value) (((value) & 0x00000002) >> 1)
298 /* Produces a ALT_UART_IER_DLH_ETBEI_DLHL register field value suitable for setting the register. */
299 #define ALT_UART_IER_DLH_ETBEI_DLHL_SET(value) (((value) << 1) & 0x00000002)
300 
301 /*
302  * Field : DLH[2] and Enable Receiver Line Status - elsi_dhl2
303  *
304  * Divisor Latch High Register:
305  *
306  * Bit 2 of DLH value.
307  *
308  * Interrupt Enable Register:
309  *
310  * This is used to enable/disable the generation of Receiver Line Status Interrupt.
311  * This is the highest priority interrupt.
312  *
313  * Field Enumeration Values:
314  *
315  * Enum | Value | Description
316  * :----------------------------------|:------|:----------------------------
317  * ALT_UART_IER_DLH_ELSI_DHL2_E_DISD | 0x0 | Disable interrupt line stat
318  * ALT_UART_IER_DLH_ELSI_DHL2_E_END | 0x1 | Enable interrupt line stat
319  *
320  * Field Access Macros:
321  *
322  */
323 /*
324  * Enumerated value for register field ALT_UART_IER_DLH_ELSI_DHL2
325  *
326  * Disable interrupt line stat
327  */
328 #define ALT_UART_IER_DLH_ELSI_DHL2_E_DISD 0x0
329 /*
330  * Enumerated value for register field ALT_UART_IER_DLH_ELSI_DHL2
331  *
332  * Enable interrupt line stat
333  */
334 #define ALT_UART_IER_DLH_ELSI_DHL2_E_END 0x1
335 
336 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */
337 #define ALT_UART_IER_DLH_ELSI_DHL2_LSB 2
338 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */
339 #define ALT_UART_IER_DLH_ELSI_DHL2_MSB 2
340 /* The width in bits of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */
341 #define ALT_UART_IER_DLH_ELSI_DHL2_WIDTH 1
342 /* The mask used to set the ALT_UART_IER_DLH_ELSI_DHL2 register field value. */
343 #define ALT_UART_IER_DLH_ELSI_DHL2_SET_MSK 0x00000004
344 /* The mask used to clear the ALT_UART_IER_DLH_ELSI_DHL2 register field value. */
345 #define ALT_UART_IER_DLH_ELSI_DHL2_CLR_MSK 0xfffffffb
346 /* The reset value of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */
347 #define ALT_UART_IER_DLH_ELSI_DHL2_RESET 0x0
348 /* Extracts the ALT_UART_IER_DLH_ELSI_DHL2 field value from a register. */
349 #define ALT_UART_IER_DLH_ELSI_DHL2_GET(value) (((value) & 0x00000004) >> 2)
350 /* Produces a ALT_UART_IER_DLH_ELSI_DHL2 register field value suitable for setting the register. */
351 #define ALT_UART_IER_DLH_ELSI_DHL2_SET(value) (((value) << 2) & 0x00000004)
352 
353 /*
354  * Field : DLH[3] and Enable Modem Status Interrupt - edssi_dhl3
355  *
356  * Divisor Latch High Register:
357  *
358  * Bit 3 of DLH value.
359  *
360  * Interrupt Enable Register:
361  *
362  * This is used to enable/disable the generation of Modem Status Interrupts. This
363  * is the fourth highest priority interrupt.
364  *
365  * Field Enumeration Values:
366  *
367  * Enum | Value | Description
368  * :-----------------------------------|:------|:-------------------------------
369  * ALT_UART_IER_DLH_EDSSI_DHL3_E_DISD | 0x0 | disable modem status interrupt
370  * ALT_UART_IER_DLH_EDSSI_DHL3_E_END | 0x1 | enable modem status interrupt
371  *
372  * Field Access Macros:
373  *
374  */
375 /*
376  * Enumerated value for register field ALT_UART_IER_DLH_EDSSI_DHL3
377  *
378  * disable modem status interrupt
379  */
380 #define ALT_UART_IER_DLH_EDSSI_DHL3_E_DISD 0x0
381 /*
382  * Enumerated value for register field ALT_UART_IER_DLH_EDSSI_DHL3
383  *
384  * enable modem status interrupt
385  */
386 #define ALT_UART_IER_DLH_EDSSI_DHL3_E_END 0x1
387 
388 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */
389 #define ALT_UART_IER_DLH_EDSSI_DHL3_LSB 3
390 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */
391 #define ALT_UART_IER_DLH_EDSSI_DHL3_MSB 3
392 /* The width in bits of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */
393 #define ALT_UART_IER_DLH_EDSSI_DHL3_WIDTH 1
394 /* The mask used to set the ALT_UART_IER_DLH_EDSSI_DHL3 register field value. */
395 #define ALT_UART_IER_DLH_EDSSI_DHL3_SET_MSK 0x00000008
396 /* The mask used to clear the ALT_UART_IER_DLH_EDSSI_DHL3 register field value. */
397 #define ALT_UART_IER_DLH_EDSSI_DHL3_CLR_MSK 0xfffffff7
398 /* The reset value of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */
399 #define ALT_UART_IER_DLH_EDSSI_DHL3_RESET 0x0
400 /* Extracts the ALT_UART_IER_DLH_EDSSI_DHL3 field value from a register. */
401 #define ALT_UART_IER_DLH_EDSSI_DHL3_GET(value) (((value) & 0x00000008) >> 3)
402 /* Produces a ALT_UART_IER_DLH_EDSSI_DHL3 register field value suitable for setting the register. */
403 #define ALT_UART_IER_DLH_EDSSI_DHL3_SET(value) (((value) << 3) & 0x00000008)
404 
405 /*
406  * Field : DLH[4] - dlh4
407  *
408  * Bit 4 of DLH value.
409  *
410  * Field Access Macros:
411  *
412  */
413 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH4 register field. */
414 #define ALT_UART_IER_DLH_DLH4_LSB 4
415 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH4 register field. */
416 #define ALT_UART_IER_DLH_DLH4_MSB 4
417 /* The width in bits of the ALT_UART_IER_DLH_DLH4 register field. */
418 #define ALT_UART_IER_DLH_DLH4_WIDTH 1
419 /* The mask used to set the ALT_UART_IER_DLH_DLH4 register field value. */
420 #define ALT_UART_IER_DLH_DLH4_SET_MSK 0x00000010
421 /* The mask used to clear the ALT_UART_IER_DLH_DLH4 register field value. */
422 #define ALT_UART_IER_DLH_DLH4_CLR_MSK 0xffffffef
423 /* The reset value of the ALT_UART_IER_DLH_DLH4 register field. */
424 #define ALT_UART_IER_DLH_DLH4_RESET 0x0
425 /* Extracts the ALT_UART_IER_DLH_DLH4 field value from a register. */
426 #define ALT_UART_IER_DLH_DLH4_GET(value) (((value) & 0x00000010) >> 4)
427 /* Produces a ALT_UART_IER_DLH_DLH4 register field value suitable for setting the register. */
428 #define ALT_UART_IER_DLH_DLH4_SET(value) (((value) << 4) & 0x00000010)
429 
430 /*
431  * Field : DLH[5] - dlh5
432  *
433  * Bit 5 of DLH value.
434  *
435  * Field Access Macros:
436  *
437  */
438 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH5 register field. */
439 #define ALT_UART_IER_DLH_DLH5_LSB 5
440 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH5 register field. */
441 #define ALT_UART_IER_DLH_DLH5_MSB 5
442 /* The width in bits of the ALT_UART_IER_DLH_DLH5 register field. */
443 #define ALT_UART_IER_DLH_DLH5_WIDTH 1
444 /* The mask used to set the ALT_UART_IER_DLH_DLH5 register field value. */
445 #define ALT_UART_IER_DLH_DLH5_SET_MSK 0x00000020
446 /* The mask used to clear the ALT_UART_IER_DLH_DLH5 register field value. */
447 #define ALT_UART_IER_DLH_DLH5_CLR_MSK 0xffffffdf
448 /* The reset value of the ALT_UART_IER_DLH_DLH5 register field. */
449 #define ALT_UART_IER_DLH_DLH5_RESET 0x0
450 /* Extracts the ALT_UART_IER_DLH_DLH5 field value from a register. */
451 #define ALT_UART_IER_DLH_DLH5_GET(value) (((value) & 0x00000020) >> 5)
452 /* Produces a ALT_UART_IER_DLH_DLH5 register field value suitable for setting the register. */
453 #define ALT_UART_IER_DLH_DLH5_SET(value) (((value) << 5) & 0x00000020)
454 
455 /*
456  * Field : DLH[6] - dlh6
457  *
458  * Bit 6 of DLH value.
459  *
460  * Field Access Macros:
461  *
462  */
463 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH6 register field. */
464 #define ALT_UART_IER_DLH_DLH6_LSB 6
465 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH6 register field. */
466 #define ALT_UART_IER_DLH_DLH6_MSB 6
467 /* The width in bits of the ALT_UART_IER_DLH_DLH6 register field. */
468 #define ALT_UART_IER_DLH_DLH6_WIDTH 1
469 /* The mask used to set the ALT_UART_IER_DLH_DLH6 register field value. */
470 #define ALT_UART_IER_DLH_DLH6_SET_MSK 0x00000040
471 /* The mask used to clear the ALT_UART_IER_DLH_DLH6 register field value. */
472 #define ALT_UART_IER_DLH_DLH6_CLR_MSK 0xffffffbf
473 /* The reset value of the ALT_UART_IER_DLH_DLH6 register field. */
474 #define ALT_UART_IER_DLH_DLH6_RESET 0x0
475 /* Extracts the ALT_UART_IER_DLH_DLH6 field value from a register. */
476 #define ALT_UART_IER_DLH_DLH6_GET(value) (((value) & 0x00000040) >> 6)
477 /* Produces a ALT_UART_IER_DLH_DLH6 register field value suitable for setting the register. */
478 #define ALT_UART_IER_DLH_DLH6_SET(value) (((value) << 6) & 0x00000040)
479 
480 /*
481  * Field : DLH[7] and PTIME THRE Interrupt Mode Enable - ptime_dlh7
482  *
483  * Divisor Latch High Register:
484  *
485  * Bit 7 of DLH value.
486  *
487  * Interrupt Enable Register:
488  *
489  * This is used to enable/disable the generation of THRE Interrupt.
490  *
491  * Field Enumeration Values:
492  *
493  * Enum | Value | Description
494  * :-----------------------------------|:------|:------------------------------------
495  * ALT_UART_IER_DLH_PTIME_DLH7_E_DISD | 0x0 | disable tx-hold-reg-empty interrupt
496  * ALT_UART_IER_DLH_PTIME_DLH7_E_END | 0x1 | enable tx-hold-reg-empty interrupt
497  *
498  * Field Access Macros:
499  *
500  */
501 /*
502  * Enumerated value for register field ALT_UART_IER_DLH_PTIME_DLH7
503  *
504  * disable tx-hold-reg-empty interrupt
505  */
506 #define ALT_UART_IER_DLH_PTIME_DLH7_E_DISD 0x0
507 /*
508  * Enumerated value for register field ALT_UART_IER_DLH_PTIME_DLH7
509  *
510  * enable tx-hold-reg-empty interrupt
511  */
512 #define ALT_UART_IER_DLH_PTIME_DLH7_E_END 0x1
513 
514 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */
515 #define ALT_UART_IER_DLH_PTIME_DLH7_LSB 7
516 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */
517 #define ALT_UART_IER_DLH_PTIME_DLH7_MSB 7
518 /* The width in bits of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */
519 #define ALT_UART_IER_DLH_PTIME_DLH7_WIDTH 1
520 /* The mask used to set the ALT_UART_IER_DLH_PTIME_DLH7 register field value. */
521 #define ALT_UART_IER_DLH_PTIME_DLH7_SET_MSK 0x00000080
522 /* The mask used to clear the ALT_UART_IER_DLH_PTIME_DLH7 register field value. */
523 #define ALT_UART_IER_DLH_PTIME_DLH7_CLR_MSK 0xffffff7f
524 /* The reset value of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */
525 #define ALT_UART_IER_DLH_PTIME_DLH7_RESET 0x0
526 /* Extracts the ALT_UART_IER_DLH_PTIME_DLH7 field value from a register. */
527 #define ALT_UART_IER_DLH_PTIME_DLH7_GET(value) (((value) & 0x00000080) >> 7)
528 /* Produces a ALT_UART_IER_DLH_PTIME_DLH7 register field value suitable for setting the register. */
529 #define ALT_UART_IER_DLH_PTIME_DLH7_SET(value) (((value) << 7) & 0x00000080)
530 
531 #ifndef __ASSEMBLY__
532 /*
533  * WARNING: The C register and register group struct declarations are provided for
534  * convenience and illustrative purposes. They should, however, be used with
535  * caution as the C language standard provides no guarantees about the alignment or
536  * atomicity of device memory accesses. The recommended practice for writing
537  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
538  * alt_write_word() functions.
539  *
540  * The struct declaration for register ALT_UART_IER_DLH.
541  */
542 struct ALT_UART_IER_DLH_s
543 {
544  uint32_t erbfi_dlh0 : 1; /* DLH[0] and Receive Data Interrupt Enable */
545  uint32_t etbei_dlhl : 1; /* DLH[1] and Transmit Data Interrupt Control */
546  uint32_t elsi_dhl2 : 1; /* DLH[2] and Enable Receiver Line Status */
547  uint32_t edssi_dhl3 : 1; /* DLH[3] and Enable Modem Status Interrupt */
548  uint32_t dlh4 : 1; /* DLH[4] */
549  uint32_t dlh5 : 1; /* DLH[5] */
550  uint32_t dlh6 : 1; /* DLH[6] */
551  uint32_t ptime_dlh7 : 1; /* DLH[7] and PTIME THRE Interrupt Mode Enable */
552  uint32_t : 24; /* *UNDEFINED* */
553 };
554 
555 /* The typedef declaration for register ALT_UART_IER_DLH. */
556 typedef volatile struct ALT_UART_IER_DLH_s ALT_UART_IER_DLH_t;
557 #endif /* __ASSEMBLY__ */
558 
559 /* The byte offset of the ALT_UART_IER_DLH register from the beginning of the component. */
560 #define ALT_UART_IER_DLH_OFST 0x4
561 /* The address of the ALT_UART_IER_DLH register. */
562 #define ALT_UART_IER_DLH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_IER_DLH_OFST))
563 
564 /*
565  * Register : Interrupt Identity Register (when read) - iir
566  *
567  * Returns interrupt identification and FIFO enable/disable when read.
568  *
569  * Register Layout
570  *
571  * Bits | Access | Reset | Description
572  * :-------|:-------|:------|:-------------
573  * [3:0] | R | 0x1 | Interrupt ID
574  * [5:4] | ??? | 0x0 | *UNDEFINED*
575  * [7:6] | R | 0x0 | FIFO Enabled
576  * [31:8] | ??? | 0x0 | *UNDEFINED*
577  *
578  */
579 /*
580  * Field : Interrupt ID - id
581  *
582  * This indicates the highest priority pending interrupt.
583  *
584  * Field Enumeration Values:
585  *
586  * Enum | Value | Description
587  * :---------------------------------|:------|:-----------------------
588  * ALT_UART_IIR_ID_E_MODMSTAT | 0x0 | Modem status
589  * ALT_UART_IIR_ID_E_NOINTRPENDING | 0x1 | No Interrupt pending
590  * ALT_UART_IIR_ID_E_THREMPTY | 0x2 | THR empty
591  * ALT_UART_IIR_ID_E_RXDATAVAILABLE | 0x4 | Receive data available
592  * ALT_UART_IIR_ID_E_RXLINESTAT | 0x6 | Receive line status
593  * ALT_UART_IIR_ID_E_CHARTMO | 0xc | Character timeout
594  *
595  * Field Access Macros:
596  *
597  */
598 /*
599  * Enumerated value for register field ALT_UART_IIR_ID
600  *
601  * Modem status
602  */
603 #define ALT_UART_IIR_ID_E_MODMSTAT 0x0
604 /*
605  * Enumerated value for register field ALT_UART_IIR_ID
606  *
607  * No Interrupt pending
608  */
609 #define ALT_UART_IIR_ID_E_NOINTRPENDING 0x1
610 /*
611  * Enumerated value for register field ALT_UART_IIR_ID
612  *
613  * THR empty
614  */
615 #define ALT_UART_IIR_ID_E_THREMPTY 0x2
616 /*
617  * Enumerated value for register field ALT_UART_IIR_ID
618  *
619  * Receive data available
620  */
621 #define ALT_UART_IIR_ID_E_RXDATAVAILABLE 0x4
622 /*
623  * Enumerated value for register field ALT_UART_IIR_ID
624  *
625  * Receive line status
626  */
627 #define ALT_UART_IIR_ID_E_RXLINESTAT 0x6
628 /*
629  * Enumerated value for register field ALT_UART_IIR_ID
630  *
631  * Character timeout
632  */
633 #define ALT_UART_IIR_ID_E_CHARTMO 0xc
634 
635 /* The Least Significant Bit (LSB) position of the ALT_UART_IIR_ID register field. */
636 #define ALT_UART_IIR_ID_LSB 0
637 /* The Most Significant Bit (MSB) position of the ALT_UART_IIR_ID register field. */
638 #define ALT_UART_IIR_ID_MSB 3
639 /* The width in bits of the ALT_UART_IIR_ID register field. */
640 #define ALT_UART_IIR_ID_WIDTH 4
641 /* The mask used to set the ALT_UART_IIR_ID register field value. */
642 #define ALT_UART_IIR_ID_SET_MSK 0x0000000f
643 /* The mask used to clear the ALT_UART_IIR_ID register field value. */
644 #define ALT_UART_IIR_ID_CLR_MSK 0xfffffff0
645 /* The reset value of the ALT_UART_IIR_ID register field. */
646 #define ALT_UART_IIR_ID_RESET 0x1
647 /* Extracts the ALT_UART_IIR_ID field value from a register. */
648 #define ALT_UART_IIR_ID_GET(value) (((value) & 0x0000000f) >> 0)
649 /* Produces a ALT_UART_IIR_ID register field value suitable for setting the register. */
650 #define ALT_UART_IIR_ID_SET(value) (((value) << 0) & 0x0000000f)
651 
652 /*
653  * Field : FIFO Enabled - fifoen
654  *
655  * This is used to indicate whether the FIFO's are enabled or disabled.
656  *
657  * Field Enumeration Values:
658  *
659  * Enum | Value | Description
660  * :---------------------------|:------|:--------------
661  * ALT_UART_IIR_FIFOEN_E_DISD | 0x0 | FIFO disabled
662  * ALT_UART_IIR_FIFOEN_E_END | 0x3 | FIFO enabled
663  *
664  * Field Access Macros:
665  *
666  */
667 /*
668  * Enumerated value for register field ALT_UART_IIR_FIFOEN
669  *
670  * FIFO disabled
671  */
672 #define ALT_UART_IIR_FIFOEN_E_DISD 0x0
673 /*
674  * Enumerated value for register field ALT_UART_IIR_FIFOEN
675  *
676  * FIFO enabled
677  */
678 #define ALT_UART_IIR_FIFOEN_E_END 0x3
679 
680 /* The Least Significant Bit (LSB) position of the ALT_UART_IIR_FIFOEN register field. */
681 #define ALT_UART_IIR_FIFOEN_LSB 6
682 /* The Most Significant Bit (MSB) position of the ALT_UART_IIR_FIFOEN register field. */
683 #define ALT_UART_IIR_FIFOEN_MSB 7
684 /* The width in bits of the ALT_UART_IIR_FIFOEN register field. */
685 #define ALT_UART_IIR_FIFOEN_WIDTH 2
686 /* The mask used to set the ALT_UART_IIR_FIFOEN register field value. */
687 #define ALT_UART_IIR_FIFOEN_SET_MSK 0x000000c0
688 /* The mask used to clear the ALT_UART_IIR_FIFOEN register field value. */
689 #define ALT_UART_IIR_FIFOEN_CLR_MSK 0xffffff3f
690 /* The reset value of the ALT_UART_IIR_FIFOEN register field. */
691 #define ALT_UART_IIR_FIFOEN_RESET 0x0
692 /* Extracts the ALT_UART_IIR_FIFOEN field value from a register. */
693 #define ALT_UART_IIR_FIFOEN_GET(value) (((value) & 0x000000c0) >> 6)
694 /* Produces a ALT_UART_IIR_FIFOEN register field value suitable for setting the register. */
695 #define ALT_UART_IIR_FIFOEN_SET(value) (((value) << 6) & 0x000000c0)
696 
697 #ifndef __ASSEMBLY__
698 /*
699  * WARNING: The C register and register group struct declarations are provided for
700  * convenience and illustrative purposes. They should, however, be used with
701  * caution as the C language standard provides no guarantees about the alignment or
702  * atomicity of device memory accesses. The recommended practice for writing
703  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
704  * alt_write_word() functions.
705  *
706  * The struct declaration for register ALT_UART_IIR.
707  */
708 struct ALT_UART_IIR_s
709 {
710  const uint32_t id : 4; /* Interrupt ID */
711  uint32_t : 2; /* *UNDEFINED* */
712  const uint32_t fifoen : 2; /* FIFO Enabled */
713  uint32_t : 24; /* *UNDEFINED* */
714 };
715 
716 /* The typedef declaration for register ALT_UART_IIR. */
717 typedef volatile struct ALT_UART_IIR_s ALT_UART_IIR_t;
718 #endif /* __ASSEMBLY__ */
719 
720 /* The byte offset of the ALT_UART_IIR register from the beginning of the component. */
721 #define ALT_UART_IIR_OFST 0x8
722 /* The address of the ALT_UART_IIR register. */
723 #define ALT_UART_IIR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_IIR_OFST))
724 
725 /*
726  * Register : FIFO Control (when written) - fcr
727  *
728  * Controls FIFO Operations when written.
729  *
730  * Register Layout
731  *
732  * Bits | Access | Reset | Description
733  * :-------|:-------|:--------|:-----------------------
734  * [0] | W | Unknown | FIFO Enable
735  * [1] | W | Unknown | Rx FIFO Reset
736  * [2] | W | Unknown | Tx FIFO Reset
737  * [3] | W | Unknown | DMA Mode
738  * [5:4] | W | Unknown | Tx Empty Trigger Level
739  * [7:6] | W | Unknown | Rx Trigger Level
740  * [31:8] | ??? | 0x0 | *UNDEFINED*
741  *
742  */
743 /*
744  * Field : FIFO Enable - fifoe
745  *
746  * Enables/disables the transmit (Tx) and receive (Rx ) FIFO's. Whenever the value
747  * of this bit is changed both the Tx and Rx controller portion of FIFO's will be
748  * reset.
749  *
750  * Field Enumeration Values:
751  *
752  * Enum | Value | Description
753  * :--------------------------|:------|:---------------
754  * ALT_UART_FCR_FIFOE_E_DISD | 0x0 | FIFOs disabled
755  * ALT_UART_FCR_FIFOE_E_END | 0x1 | FIFOs enabled
756  *
757  * Field Access Macros:
758  *
759  */
760 /*
761  * Enumerated value for register field ALT_UART_FCR_FIFOE
762  *
763  * FIFOs disabled
764  */
765 #define ALT_UART_FCR_FIFOE_E_DISD 0x0
766 /*
767  * Enumerated value for register field ALT_UART_FCR_FIFOE
768  *
769  * FIFOs enabled
770  */
771 #define ALT_UART_FCR_FIFOE_E_END 0x1
772 
773 /* The Least Significant Bit (LSB) position of the ALT_UART_FCR_FIFOE register field. */
774 #define ALT_UART_FCR_FIFOE_LSB 0
775 /* The Most Significant Bit (MSB) position of the ALT_UART_FCR_FIFOE register field. */
776 #define ALT_UART_FCR_FIFOE_MSB 0
777 /* The width in bits of the ALT_UART_FCR_FIFOE register field. */
778 #define ALT_UART_FCR_FIFOE_WIDTH 1
779 /* The mask used to set the ALT_UART_FCR_FIFOE register field value. */
780 #define ALT_UART_FCR_FIFOE_SET_MSK 0x00000001
781 /* The mask used to clear the ALT_UART_FCR_FIFOE register field value. */
782 #define ALT_UART_FCR_FIFOE_CLR_MSK 0xfffffffe
783 /* The reset value of the ALT_UART_FCR_FIFOE register field is UNKNOWN. */
784 #define ALT_UART_FCR_FIFOE_RESET 0x0
785 /* Extracts the ALT_UART_FCR_FIFOE field value from a register. */
786 #define ALT_UART_FCR_FIFOE_GET(value) (((value) & 0x00000001) >> 0)
787 /* Produces a ALT_UART_FCR_FIFOE register field value suitable for setting the register. */
788 #define ALT_UART_FCR_FIFOE_SET(value) (((value) << 0) & 0x00000001)
789 
790 /*
791  * Field : Rx FIFO Reset - rfifor
792  *
793  * Resets the control portion of the receive FIFO and treats the FIFO as empty.
794  * This will also de-assert the DMA Rxrequest and single signals. Note that this
795  * bit is self-clearing' and it is not necessary to clear this bit.
796  *
797  * Field Enumeration Values:
798  *
799  * Enum | Value | Description
800  * :----------------------------|:------|:----------------------------
801  * ALT_UART_FCR_RFIFOR_E_NORST | 0x0 | No Reset of Rx FIFO Control
802  * ALT_UART_FCR_RFIFOR_E_RST | 0x1 | Resets of Rx FIFO Control
803  *
804  * Field Access Macros:
805  *
806  */
807 /*
808  * Enumerated value for register field ALT_UART_FCR_RFIFOR
809  *
810  * No Reset of Rx FIFO Control
811  */
812 #define ALT_UART_FCR_RFIFOR_E_NORST 0x0
813 /*
814  * Enumerated value for register field ALT_UART_FCR_RFIFOR
815  *
816  * Resets of Rx FIFO Control
817  */
818 #define ALT_UART_FCR_RFIFOR_E_RST 0x1
819 
820 /* The Least Significant Bit (LSB) position of the ALT_UART_FCR_RFIFOR register field. */
821 #define ALT_UART_FCR_RFIFOR_LSB 1
822 /* The Most Significant Bit (MSB) position of the ALT_UART_FCR_RFIFOR register field. */
823 #define ALT_UART_FCR_RFIFOR_MSB 1
824 /* The width in bits of the ALT_UART_FCR_RFIFOR register field. */
825 #define ALT_UART_FCR_RFIFOR_WIDTH 1
826 /* The mask used to set the ALT_UART_FCR_RFIFOR register field value. */
827 #define ALT_UART_FCR_RFIFOR_SET_MSK 0x00000002
828 /* The mask used to clear the ALT_UART_FCR_RFIFOR register field value. */
829 #define ALT_UART_FCR_RFIFOR_CLR_MSK 0xfffffffd
830 /* The reset value of the ALT_UART_FCR_RFIFOR register field is UNKNOWN. */
831 #define ALT_UART_FCR_RFIFOR_RESET 0x0
832 /* Extracts the ALT_UART_FCR_RFIFOR field value from a register. */
833 #define ALT_UART_FCR_RFIFOR_GET(value) (((value) & 0x00000002) >> 1)
834 /* Produces a ALT_UART_FCR_RFIFOR register field value suitable for setting the register. */
835 #define ALT_UART_FCR_RFIFOR_SET(value) (((value) << 1) & 0x00000002)
836 
837 /*
838  * Field : Tx FIFO Reset - xfifor
839  *
840  * Resets the control portion of the transmit FIFO and treats the FIFO as empty.
841  * This will also de-assert the DMA Tx request and single signals when additional
842  * DMA handshaking is used.
843  *
844  * Note that this bit is 'self-clearing' and it is not necessary to clear this bit.
845  *
846  * Field Enumeration Values:
847  *
848  * Enum | Value | Description
849  * :----------------------------|:------|:----------------------------
850  * ALT_UART_FCR_XFIFOR_E_NORST | 0x0 | No Reset of Tx FIFO Control
851  * ALT_UART_FCR_XFIFOR_E_RST | 0x1 | Resets Tx FIFO Control
852  *
853  * Field Access Macros:
854  *
855  */
856 /*
857  * Enumerated value for register field ALT_UART_FCR_XFIFOR
858  *
859  * No Reset of Tx FIFO Control
860  */
861 #define ALT_UART_FCR_XFIFOR_E_NORST 0x0
862 /*
863  * Enumerated value for register field ALT_UART_FCR_XFIFOR
864  *
865  * Resets Tx FIFO Control
866  */
867 #define ALT_UART_FCR_XFIFOR_E_RST 0x1
868 
869 /* The Least Significant Bit (LSB) position of the ALT_UART_FCR_XFIFOR register field. */
870 #define ALT_UART_FCR_XFIFOR_LSB 2
871 /* The Most Significant Bit (MSB) position of the ALT_UART_FCR_XFIFOR register field. */
872 #define ALT_UART_FCR_XFIFOR_MSB 2
873 /* The width in bits of the ALT_UART_FCR_XFIFOR register field. */
874 #define ALT_UART_FCR_XFIFOR_WIDTH 1
875 /* The mask used to set the ALT_UART_FCR_XFIFOR register field value. */
876 #define ALT_UART_FCR_XFIFOR_SET_MSK 0x00000004
877 /* The mask used to clear the ALT_UART_FCR_XFIFOR register field value. */
878 #define ALT_UART_FCR_XFIFOR_CLR_MSK 0xfffffffb
879 /* The reset value of the ALT_UART_FCR_XFIFOR register field is UNKNOWN. */
880 #define ALT_UART_FCR_XFIFOR_RESET 0x0
881 /* Extracts the ALT_UART_FCR_XFIFOR field value from a register. */
882 #define ALT_UART_FCR_XFIFOR_GET(value) (((value) & 0x00000004) >> 2)
883 /* Produces a ALT_UART_FCR_XFIFOR register field value suitable for setting the register. */
884 #define ALT_UART_FCR_XFIFOR_SET(value) (((value) << 2) & 0x00000004)
885 
886 /*
887  * Field : DMA Mode - dmam
888  *
889  * This determines the DMA signalling mode used for the uart_dma_tx_req_n and
890  * uart_dma_rx_req_n output signals when additional DMA handshaking signals are not
891  * selected. DMA mode 0 supports single DMA data transfers at a time. In mode 0,
892  * the uart_dma_tx_req_n signal goes active low under the following conditions:
893  *
894  * * When the Transmitter Holding Register is empty in non-FIFO mode.
895  *
896  * * When the transmitter FIFO is empty in FIFO mode with Programmable THRE
897  * interrupt mode disabled.
898  *
899  * * When the transmitter FIFO is at or below the programmed threshold with
900  * Programmable THRE interrupt mode enabled.
901  *
902  * It goes inactive under the following conditions
903  *
904  * * When a single character has been written into the Transmitter Holding
905  * Register or transmitter FIFO with Programmable THRE interrupt mode disabled.
906  *
907  * * When the transmitter FIFO is above the threshold with Programmable THRE
908  * interrupt mode enabled.
909  *
910  * DMA mode 1 supports multi-DMA data transfers, where multiple transfers are made
911  * continuously until the receiver FIFO has been emptied or the transmit FIFO has
912  * been filled. In mode 1 the uart_dma_tx_req_n signal is asserted under the
913  * following conditions:
914  *
915  * * When the transmitter FIFO is empty with Programmable THRE interrupt mode
916  * disabled.
917  *
918  * * When the transmitter FIFO is at or below the programmed threshold with
919  * Programmable THRE interrupt mode enabled.
920  *
921  * Field Enumeration Values:
922  *
923  * Enum | Value | Description
924  * :---------------------------|:------|:---------------------------
925  * ALT_UART_FCR_DMAM_E_SINGLE | 0x0 | Single DMA Transfer Mode
926  * ALT_UART_FCR_DMAM_E_MULT | 0x1 | Multiple DMA Transfer Mode
927  *
928  * Field Access Macros:
929  *
930  */
931 /*
932  * Enumerated value for register field ALT_UART_FCR_DMAM
933  *
934  * Single DMA Transfer Mode
935  */
936 #define ALT_UART_FCR_DMAM_E_SINGLE 0x0
937 /*
938  * Enumerated value for register field ALT_UART_FCR_DMAM
939  *
940  * Multiple DMA Transfer Mode
941  */
942 #define ALT_UART_FCR_DMAM_E_MULT 0x1
943 
944 /* The Least Significant Bit (LSB) position of the ALT_UART_FCR_DMAM register field. */
945 #define ALT_UART_FCR_DMAM_LSB 3
946 /* The Most Significant Bit (MSB) position of the ALT_UART_FCR_DMAM register field. */
947 #define ALT_UART_FCR_DMAM_MSB 3
948 /* The width in bits of the ALT_UART_FCR_DMAM register field. */
949 #define ALT_UART_FCR_DMAM_WIDTH 1
950 /* The mask used to set the ALT_UART_FCR_DMAM register field value. */
951 #define ALT_UART_FCR_DMAM_SET_MSK 0x00000008
952 /* The mask used to clear the ALT_UART_FCR_DMAM register field value. */
953 #define ALT_UART_FCR_DMAM_CLR_MSK 0xfffffff7
954 /* The reset value of the ALT_UART_FCR_DMAM register field is UNKNOWN. */
955 #define ALT_UART_FCR_DMAM_RESET 0x0
956 /* Extracts the ALT_UART_FCR_DMAM field value from a register. */
957 #define ALT_UART_FCR_DMAM_GET(value) (((value) & 0x00000008) >> 3)
958 /* Produces a ALT_UART_FCR_DMAM register field value suitable for setting the register. */
959 #define ALT_UART_FCR_DMAM_SET(value) (((value) << 3) & 0x00000008)
960 
961 /*
962  * Field : Tx Empty Trigger Level - tet
963  *
964  * This is used to select the empty threshold level at which the THRE Interrupts
965  * will be generated when the mode is active. It also determines when the uart DMA
966  * transmit request signal uart_dma_tx_req_n will be asserted when in certain modes
967  * of operation.
968  *
969  * Field Enumeration Values:
970  *
971  * Enum | Value | Description
972  * :-------------------------------|:------|:-----------------------
973  * ALT_UART_FCR_TET_E_FIFOEMPTY | 0x0 | FIFO empty
974  * ALT_UART_FCR_TET_E_TWOCHARS | 0x1 | Two characters in FIFO
975  * ALT_UART_FCR_TET_E_QUARTERFULL | 0x2 | FIFO 1/4 full
976  * ALT_UART_FCR_TET_E_HALFFULL | 0x3 | FIFO 1/2 full
977  *
978  * Field Access Macros:
979  *
980  */
981 /*
982  * Enumerated value for register field ALT_UART_FCR_TET
983  *
984  * FIFO empty
985  */
986 #define ALT_UART_FCR_TET_E_FIFOEMPTY 0x0
987 /*
988  * Enumerated value for register field ALT_UART_FCR_TET
989  *
990  * Two characters in FIFO
991  */
992 #define ALT_UART_FCR_TET_E_TWOCHARS 0x1
993 /*
994  * Enumerated value for register field ALT_UART_FCR_TET
995  *
996  * FIFO 1/4 full
997  */
998 #define ALT_UART_FCR_TET_E_QUARTERFULL 0x2
999 /*
1000  * Enumerated value for register field ALT_UART_FCR_TET
1001  *
1002  * FIFO 1/2 full
1003  */
1004 #define ALT_UART_FCR_TET_E_HALFFULL 0x3
1005 
1006 /* The Least Significant Bit (LSB) position of the ALT_UART_FCR_TET register field. */
1007 #define ALT_UART_FCR_TET_LSB 4
1008 /* The Most Significant Bit (MSB) position of the ALT_UART_FCR_TET register field. */
1009 #define ALT_UART_FCR_TET_MSB 5
1010 /* The width in bits of the ALT_UART_FCR_TET register field. */
1011 #define ALT_UART_FCR_TET_WIDTH 2
1012 /* The mask used to set the ALT_UART_FCR_TET register field value. */
1013 #define ALT_UART_FCR_TET_SET_MSK 0x00000030
1014 /* The mask used to clear the ALT_UART_FCR_TET register field value. */
1015 #define ALT_UART_FCR_TET_CLR_MSK 0xffffffcf
1016 /* The reset value of the ALT_UART_FCR_TET register field is UNKNOWN. */
1017 #define ALT_UART_FCR_TET_RESET 0x0
1018 /* Extracts the ALT_UART_FCR_TET field value from a register. */
1019 #define ALT_UART_FCR_TET_GET(value) (((value) & 0x00000030) >> 4)
1020 /* Produces a ALT_UART_FCR_TET register field value suitable for setting the register. */
1021 #define ALT_UART_FCR_TET_SET(value) (((value) << 4) & 0x00000030)
1022 
1023 /*
1024  * Field : Rx Trigger Level - rt
1025  *
1026  * This register is configured to implement FIFOs. Bits[7:6], Rx Trigger (or RT):
1027  * This is used to select the trigger level in the receiver FIFO at which the
1028  * Received Data Available Interrupt will be generated. In auto flow control mode
1029  * it is used to determine when the uart_rts_n signal will be de-asserted. It also
1030  * determines when the uart_dma_rx_req_n signal will be asserted when in certain
1031  * modes of operation.
1032  *
1033  * Field Enumeration Values:
1034  *
1035  * Enum | Value | Description
1036  * :------------------------------|:------|:----------------------
1037  * ALT_UART_FCR_RT_E_ONECHAR | 0x0 | one character in fifo
1038  * ALT_UART_FCR_RT_E_QUARTERFULL | 0x1 | FIFO 1/4 full
1039  * ALT_UART_FCR_RT_E_HALFFULL | 0x2 | FIFO 1/2 full
1040  * ALT_UART_FCR_RT_E_FULLLESS2 | 0x3 | FIFO 2 less than full
1041  *
1042  * Field Access Macros:
1043  *
1044  */
1045 /*
1046  * Enumerated value for register field ALT_UART_FCR_RT
1047  *
1048  * one character in fifo
1049  */
1050 #define ALT_UART_FCR_RT_E_ONECHAR 0x0
1051 /*
1052  * Enumerated value for register field ALT_UART_FCR_RT
1053  *
1054  * FIFO 1/4 full
1055  */
1056 #define ALT_UART_FCR_RT_E_QUARTERFULL 0x1
1057 /*
1058  * Enumerated value for register field ALT_UART_FCR_RT
1059  *
1060  * FIFO 1/2 full
1061  */
1062 #define ALT_UART_FCR_RT_E_HALFFULL 0x2
1063 /*
1064  * Enumerated value for register field ALT_UART_FCR_RT
1065  *
1066  * FIFO 2 less than full
1067  */
1068 #define ALT_UART_FCR_RT_E_FULLLESS2 0x3
1069 
1070 /* The Least Significant Bit (LSB) position of the ALT_UART_FCR_RT register field. */
1071 #define ALT_UART_FCR_RT_LSB 6
1072 /* The Most Significant Bit (MSB) position of the ALT_UART_FCR_RT register field. */
1073 #define ALT_UART_FCR_RT_MSB 7
1074 /* The width in bits of the ALT_UART_FCR_RT register field. */
1075 #define ALT_UART_FCR_RT_WIDTH 2
1076 /* The mask used to set the ALT_UART_FCR_RT register field value. */
1077 #define ALT_UART_FCR_RT_SET_MSK 0x000000c0
1078 /* The mask used to clear the ALT_UART_FCR_RT register field value. */
1079 #define ALT_UART_FCR_RT_CLR_MSK 0xffffff3f
1080 /* The reset value of the ALT_UART_FCR_RT register field is UNKNOWN. */
1081 #define ALT_UART_FCR_RT_RESET 0x0
1082 /* Extracts the ALT_UART_FCR_RT field value from a register. */
1083 #define ALT_UART_FCR_RT_GET(value) (((value) & 0x000000c0) >> 6)
1084 /* Produces a ALT_UART_FCR_RT register field value suitable for setting the register. */
1085 #define ALT_UART_FCR_RT_SET(value) (((value) << 6) & 0x000000c0)
1086 
1087 #ifndef __ASSEMBLY__
1088 /*
1089  * WARNING: The C register and register group struct declarations are provided for
1090  * convenience and illustrative purposes. They should, however, be used with
1091  * caution as the C language standard provides no guarantees about the alignment or
1092  * atomicity of device memory accesses. The recommended practice for writing
1093  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1094  * alt_write_word() functions.
1095  *
1096  * The struct declaration for register ALT_UART_FCR.
1097  */
1098 struct ALT_UART_FCR_s
1099 {
1100  uint32_t fifoe : 1; /* FIFO Enable */
1101  uint32_t rfifor : 1; /* Rx FIFO Reset */
1102  uint32_t xfifor : 1; /* Tx FIFO Reset */
1103  uint32_t dmam : 1; /* DMA Mode */
1104  uint32_t tet : 2; /* Tx Empty Trigger Level */
1105  uint32_t rt : 2; /* Rx Trigger Level */
1106  uint32_t : 24; /* *UNDEFINED* */
1107 };
1108 
1109 /* The typedef declaration for register ALT_UART_FCR. */
1110 typedef volatile struct ALT_UART_FCR_s ALT_UART_FCR_t;
1111 #endif /* __ASSEMBLY__ */
1112 
1113 /* The byte offset of the ALT_UART_FCR register from the beginning of the component. */
1114 #define ALT_UART_FCR_OFST 0x8
1115 /* The address of the ALT_UART_FCR register. */
1116 #define ALT_UART_FCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_FCR_OFST))
1117 
1118 /*
1119  * Register : Line Control Register (When Written) - lcr
1120  *
1121  * Formats serial data.
1122  *
1123  * Register Layout
1124  *
1125  * Bits | Access | Reset | Description
1126  * :-------|:-------|:------|:-------------------------
1127  * [1:0] | RW | 0x0 | Data Length Select
1128  * [2] | RW | 0x0 | Stop Bits
1129  * [3] | RW | 0x0 | Parity Enable
1130  * [4] | RW | 0x0 | Even Parity Select
1131  * [5] | ??? | 0x0 | *UNDEFINED*
1132  * [6] | RW | 0x0 | Break Control Bit
1133  * [7] | RW | 0x0 | Divisor Latch Access Bit
1134  * [31:8] | ??? | 0x0 | *UNDEFINED*
1135  *
1136  */
1137 /*
1138  * Field : Data Length Select - dls
1139  *
1140  * Data Length Select.Selects the number of data bits per character that the
1141  * peripheral will transmit and receive.
1142  *
1143  * Field Enumeration Values:
1144  *
1145  * Enum | Value | Description
1146  * :------------------------|:------|:------------
1147  * ALT_UART_LCR_DLS_E_LEN5 | 0x0 | 5 bits
1148  * ALT_UART_LCR_DLS_E_LEN6 | 0x1 | 6 bits
1149  * ALT_UART_LCR_DLS_E_LEN7 | 0x2 | 7 bits
1150  * ALT_UART_LCR_DLS_E_LEN8 | 0x3 | 8 bits
1151  *
1152  * Field Access Macros:
1153  *
1154  */
1155 /*
1156  * Enumerated value for register field ALT_UART_LCR_DLS
1157  *
1158  * 5 bits
1159  */
1160 #define ALT_UART_LCR_DLS_E_LEN5 0x0
1161 /*
1162  * Enumerated value for register field ALT_UART_LCR_DLS
1163  *
1164  * 6 bits
1165  */
1166 #define ALT_UART_LCR_DLS_E_LEN6 0x1
1167 /*
1168  * Enumerated value for register field ALT_UART_LCR_DLS
1169  *
1170  * 7 bits
1171  */
1172 #define ALT_UART_LCR_DLS_E_LEN7 0x2
1173 /*
1174  * Enumerated value for register field ALT_UART_LCR_DLS
1175  *
1176  * 8 bits
1177  */
1178 #define ALT_UART_LCR_DLS_E_LEN8 0x3
1179 
1180 /* The Least Significant Bit (LSB) position of the ALT_UART_LCR_DLS register field. */
1181 #define ALT_UART_LCR_DLS_LSB 0
1182 /* The Most Significant Bit (MSB) position of the ALT_UART_LCR_DLS register field. */
1183 #define ALT_UART_LCR_DLS_MSB 1
1184 /* The width in bits of the ALT_UART_LCR_DLS register field. */
1185 #define ALT_UART_LCR_DLS_WIDTH 2
1186 /* The mask used to set the ALT_UART_LCR_DLS register field value. */
1187 #define ALT_UART_LCR_DLS_SET_MSK 0x00000003
1188 /* The mask used to clear the ALT_UART_LCR_DLS register field value. */
1189 #define ALT_UART_LCR_DLS_CLR_MSK 0xfffffffc
1190 /* The reset value of the ALT_UART_LCR_DLS register field. */
1191 #define ALT_UART_LCR_DLS_RESET 0x0
1192 /* Extracts the ALT_UART_LCR_DLS field value from a register. */
1193 #define ALT_UART_LCR_DLS_GET(value) (((value) & 0x00000003) >> 0)
1194 /* Produces a ALT_UART_LCR_DLS register field value suitable for setting the register. */
1195 #define ALT_UART_LCR_DLS_SET(value) (((value) << 0) & 0x00000003)
1196 
1197 /*
1198  * Field : Stop Bits - stop
1199  *
1200  * Number of stop bits. Used to select the number of stop bits per character that
1201  * the peripheral will transmit and receive.Note that regardless of the number of
1202  * stop bits selected the receiver will only check the first stop bit.
1203  *
1204  * Field Enumeration Values:
1205  *
1206  * Enum | Value | Description
1207  * :----------------------------------|:------|:------------------------------------------
1208  * ALT_UART_LCR_STOP_E_ONESTOP | 0x0 | one stop bit
1209  * ALT_UART_LCR_STOP_E_ONEPOINT5STOP | 0x1 | 1.5 stop bits when DLS (LCR[1:0]) is zero
1210  *
1211  * Field Access Macros:
1212  *
1213  */
1214 /*
1215  * Enumerated value for register field ALT_UART_LCR_STOP
1216  *
1217  * one stop bit
1218  */
1219 #define ALT_UART_LCR_STOP_E_ONESTOP 0x0
1220 /*
1221  * Enumerated value for register field ALT_UART_LCR_STOP
1222  *
1223  * 1.5 stop bits when DLS (LCR[1:0]) is zero
1224  */
1225 #define ALT_UART_LCR_STOP_E_ONEPOINT5STOP 0x1
1226 
1227 /* The Least Significant Bit (LSB) position of the ALT_UART_LCR_STOP register field. */
1228 #define ALT_UART_LCR_STOP_LSB 2
1229 /* The Most Significant Bit (MSB) position of the ALT_UART_LCR_STOP register field. */
1230 #define ALT_UART_LCR_STOP_MSB 2
1231 /* The width in bits of the ALT_UART_LCR_STOP register field. */
1232 #define ALT_UART_LCR_STOP_WIDTH 1
1233 /* The mask used to set the ALT_UART_LCR_STOP register field value. */
1234 #define ALT_UART_LCR_STOP_SET_MSK 0x00000004
1235 /* The mask used to clear the ALT_UART_LCR_STOP register field value. */
1236 #define ALT_UART_LCR_STOP_CLR_MSK 0xfffffffb
1237 /* The reset value of the ALT_UART_LCR_STOP register field. */
1238 #define ALT_UART_LCR_STOP_RESET 0x0
1239 /* Extracts the ALT_UART_LCR_STOP field value from a register. */
1240 #define ALT_UART_LCR_STOP_GET(value) (((value) & 0x00000004) >> 2)
1241 /* Produces a ALT_UART_LCR_STOP register field value suitable for setting the register. */
1242 #define ALT_UART_LCR_STOP_SET(value) (((value) << 2) & 0x00000004)
1243 
1244 /*
1245  * Field : Parity Enable - pen
1246  *
1247  * This bit is used to enable and disable parity generation and detection in a
1248  * transmitted and received data character.
1249  *
1250  * Field Enumeration Values:
1251  *
1252  * Enum | Value | Description
1253  * :------------------------|:------|:----------------
1254  * ALT_UART_LCR_PEN_E_DISD | 0x0 | parity disabled
1255  * ALT_UART_LCR_PEN_E_END | 0x1 | parity enabled
1256  *
1257  * Field Access Macros:
1258  *
1259  */
1260 /*
1261  * Enumerated value for register field ALT_UART_LCR_PEN
1262  *
1263  * parity disabled
1264  */
1265 #define ALT_UART_LCR_PEN_E_DISD 0x0
1266 /*
1267  * Enumerated value for register field ALT_UART_LCR_PEN
1268  *
1269  * parity enabled
1270  */
1271 #define ALT_UART_LCR_PEN_E_END 0x1
1272 
1273 /* The Least Significant Bit (LSB) position of the ALT_UART_LCR_PEN register field. */
1274 #define ALT_UART_LCR_PEN_LSB 3
1275 /* The Most Significant Bit (MSB) position of the ALT_UART_LCR_PEN register field. */
1276 #define ALT_UART_LCR_PEN_MSB 3
1277 /* The width in bits of the ALT_UART_LCR_PEN register field. */
1278 #define ALT_UART_LCR_PEN_WIDTH 1
1279 /* The mask used to set the ALT_UART_LCR_PEN register field value. */
1280 #define ALT_UART_LCR_PEN_SET_MSK 0x00000008
1281 /* The mask used to clear the ALT_UART_LCR_PEN register field value. */
1282 #define ALT_UART_LCR_PEN_CLR_MSK 0xfffffff7
1283 /* The reset value of the ALT_UART_LCR_PEN register field. */
1284 #define ALT_UART_LCR_PEN_RESET 0x0
1285 /* Extracts the ALT_UART_LCR_PEN field value from a register. */
1286 #define ALT_UART_LCR_PEN_GET(value) (((value) & 0x00000008) >> 3)
1287 /* Produces a ALT_UART_LCR_PEN register field value suitable for setting the register. */
1288 #define ALT_UART_LCR_PEN_SET(value) (((value) << 3) & 0x00000008)
1289 
1290 /*
1291  * Field : Even Parity Select - eps
1292  *
1293  * This is used to select between even and odd parity, when parity is enabled (PEN
1294  * set to one). If set to one, an even number of logic '1's is transmitted or
1295  * checked. If set to zero, an odd number of logic '1's is transmitted or checked.
1296  *
1297  * Field Enumeration Values:
1298  *
1299  * Enum | Value | Description
1300  * :---------------------------|:------|:------------
1301  * ALT_UART_LCR_EPS_E_ODDPAR | 0x0 | odd parity
1302  * ALT_UART_LCR_EPS_E_EVENPAR | 0x1 | even parity
1303  *
1304  * Field Access Macros:
1305  *
1306  */
1307 /*
1308  * Enumerated value for register field ALT_UART_LCR_EPS
1309  *
1310  * odd parity
1311  */
1312 #define ALT_UART_LCR_EPS_E_ODDPAR 0x0
1313 /*
1314  * Enumerated value for register field ALT_UART_LCR_EPS
1315  *
1316  * even parity
1317  */
1318 #define ALT_UART_LCR_EPS_E_EVENPAR 0x1
1319 
1320 /* The Least Significant Bit (LSB) position of the ALT_UART_LCR_EPS register field. */
1321 #define ALT_UART_LCR_EPS_LSB 4
1322 /* The Most Significant Bit (MSB) position of the ALT_UART_LCR_EPS register field. */
1323 #define ALT_UART_LCR_EPS_MSB 4
1324 /* The width in bits of the ALT_UART_LCR_EPS register field. */
1325 #define ALT_UART_LCR_EPS_WIDTH 1
1326 /* The mask used to set the ALT_UART_LCR_EPS register field value. */
1327 #define ALT_UART_LCR_EPS_SET_MSK 0x00000010
1328 /* The mask used to clear the ALT_UART_LCR_EPS register field value. */
1329 #define ALT_UART_LCR_EPS_CLR_MSK 0xffffffef
1330 /* The reset value of the ALT_UART_LCR_EPS register field. */
1331 #define ALT_UART_LCR_EPS_RESET 0x0
1332 /* Extracts the ALT_UART_LCR_EPS field value from a register. */
1333 #define ALT_UART_LCR_EPS_GET(value) (((value) & 0x00000010) >> 4)
1334 /* Produces a ALT_UART_LCR_EPS register field value suitable for setting the register. */
1335 #define ALT_UART_LCR_EPS_SET(value) (((value) << 4) & 0x00000010)
1336 
1337 /*
1338  * Field : Break Control Bit - break
1339  *
1340  * This is used to cause a break condition to be transmitted to the receiving
1341  * device. If set to one the serial output is forced to the spacing (logic 0)
1342  * state. When not in Loopback Mode, as determined by MCR[4], the sout line is
1343  * forced low until the Break bit is cleared. When in Loopback Mode, the break
1344  * condition is internally looped back to the receiver and the sir_out_n line is
1345  * forced low.
1346  *
1347  * Field Access Macros:
1348  *
1349  */
1350 /* The Least Significant Bit (LSB) position of the ALT_UART_LCR_BREAK register field. */
1351 #define ALT_UART_LCR_BREAK_LSB 6
1352 /* The Most Significant Bit (MSB) position of the ALT_UART_LCR_BREAK register field. */
1353 #define ALT_UART_LCR_BREAK_MSB 6
1354 /* The width in bits of the ALT_UART_LCR_BREAK register field. */
1355 #define ALT_UART_LCR_BREAK_WIDTH 1
1356 /* The mask used to set the ALT_UART_LCR_BREAK register field value. */
1357 #define ALT_UART_LCR_BREAK_SET_MSK 0x00000040
1358 /* The mask used to clear the ALT_UART_LCR_BREAK register field value. */
1359 #define ALT_UART_LCR_BREAK_CLR_MSK 0xffffffbf
1360 /* The reset value of the ALT_UART_LCR_BREAK register field. */
1361 #define ALT_UART_LCR_BREAK_RESET 0x0
1362 /* Extracts the ALT_UART_LCR_BREAK field value from a register. */
1363 #define ALT_UART_LCR_BREAK_GET(value) (((value) & 0x00000040) >> 6)
1364 /* Produces a ALT_UART_LCR_BREAK register field value suitable for setting the register. */
1365 #define ALT_UART_LCR_BREAK_SET(value) (((value) << 6) & 0x00000040)
1366 
1367 /*
1368  * Field : Divisor Latch Access Bit - dlab
1369  *
1370  * Used to enable reading and writing of the Divisor Latch register (DLL and DLH)
1371  * to set the baud rate of the UART. This bit must be cleared after initial baud
1372  * rate setup in order to access other registers.
1373  *
1374  * Field Access Macros:
1375  *
1376  */
1377 /* The Least Significant Bit (LSB) position of the ALT_UART_LCR_DLAB register field. */
1378 #define ALT_UART_LCR_DLAB_LSB 7
1379 /* The Most Significant Bit (MSB) position of the ALT_UART_LCR_DLAB register field. */
1380 #define ALT_UART_LCR_DLAB_MSB 7
1381 /* The width in bits of the ALT_UART_LCR_DLAB register field. */
1382 #define ALT_UART_LCR_DLAB_WIDTH 1
1383 /* The mask used to set the ALT_UART_LCR_DLAB register field value. */
1384 #define ALT_UART_LCR_DLAB_SET_MSK 0x00000080
1385 /* The mask used to clear the ALT_UART_LCR_DLAB register field value. */
1386 #define ALT_UART_LCR_DLAB_CLR_MSK 0xffffff7f
1387 /* The reset value of the ALT_UART_LCR_DLAB register field. */
1388 #define ALT_UART_LCR_DLAB_RESET 0x0
1389 /* Extracts the ALT_UART_LCR_DLAB field value from a register. */
1390 #define ALT_UART_LCR_DLAB_GET(value) (((value) & 0x00000080) >> 7)
1391 /* Produces a ALT_UART_LCR_DLAB register field value suitable for setting the register. */
1392 #define ALT_UART_LCR_DLAB_SET(value) (((value) << 7) & 0x00000080)
1393 
1394 #ifndef __ASSEMBLY__
1395 /*
1396  * WARNING: The C register and register group struct declarations are provided for
1397  * convenience and illustrative purposes. They should, however, be used with
1398  * caution as the C language standard provides no guarantees about the alignment or
1399  * atomicity of device memory accesses. The recommended practice for writing
1400  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1401  * alt_write_word() functions.
1402  *
1403  * The struct declaration for register ALT_UART_LCR.
1404  */
1405 struct ALT_UART_LCR_s
1406 {
1407  uint32_t dls : 2; /* Data Length Select */
1408  uint32_t stop : 1; /* Stop Bits */
1409  uint32_t pen : 1; /* Parity Enable */
1410  uint32_t eps : 1; /* Even Parity Select */
1411  uint32_t : 1; /* *UNDEFINED* */
1412  uint32_t break_ : 1; /* Break Control Bit */
1413  uint32_t dlab : 1; /* Divisor Latch Access Bit */
1414  uint32_t : 24; /* *UNDEFINED* */
1415 };
1416 
1417 /* The typedef declaration for register ALT_UART_LCR. */
1418 typedef volatile struct ALT_UART_LCR_s ALT_UART_LCR_t;
1419 #endif /* __ASSEMBLY__ */
1420 
1421 /* The byte offset of the ALT_UART_LCR register from the beginning of the component. */
1422 #define ALT_UART_LCR_OFST 0xc
1423 /* The address of the ALT_UART_LCR register. */
1424 #define ALT_UART_LCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_LCR_OFST))
1425 
1426 /*
1427  * Register : Modem Control Register - mcr
1428  *
1429  * Reports various operations of the modem signals
1430  *
1431  * Register Layout
1432  *
1433  * Bits | Access | Reset | Description
1434  * :-------|:-------|:------|:-------------------------
1435  * [0] | RW | 0x0 | Data Terminal Ready
1436  * [1] | RW | 0x0 | Request to Send
1437  * [2] | RW | 0x0 | Out1
1438  * [3] | RW | 0x0 | out2
1439  * [4] | RW | 0x0 | LoopBack Bit
1440  * [5] | RW | 0x0 | Auto Flow Control Enable
1441  * [31:6] | ??? | 0x0 | *UNDEFINED*
1442  *
1443  */
1444 /*
1445  * Field : Data Terminal Ready - dtr
1446  *
1447  * This is used to directly control the Data Terminal Ready output. The value
1448  * written to this location is inverted and driven out on uart_dtr_n, that is: The
1449  * Data Terminal Ready output is used to inform the modem or data set that the UART
1450  * is ready to establish communications.
1451  *
1452  * Note that Loopback mode bit [4] of MCR is set to one, the uart_dtr_n output is
1453  * held inactive high while the value of this location is internally looped back
1454  * to an input.
1455  *
1456  * Field Enumeration Values:
1457  *
1458  * Enum | Value | Description
1459  * :--------------------------|:------|:---------------------------------
1460  * ALT_UART_MCR_DTR_E_LOGIC1 | 0x0 | uart_dtr_n de-asserted (logic 1)
1461  * ALT_UART_MCR_DTR_E_LOGIC0 | 0x1 | uart_dtr_n asserted (logic 0)
1462  *
1463  * Field Access Macros:
1464  *
1465  */
1466 /*
1467  * Enumerated value for register field ALT_UART_MCR_DTR
1468  *
1469  * uart_dtr_n de-asserted (logic 1)
1470  */
1471 #define ALT_UART_MCR_DTR_E_LOGIC1 0x0
1472 /*
1473  * Enumerated value for register field ALT_UART_MCR_DTR
1474  *
1475  * uart_dtr_n asserted (logic 0)
1476  */
1477 #define ALT_UART_MCR_DTR_E_LOGIC0 0x1
1478 
1479 /* The Least Significant Bit (LSB) position of the ALT_UART_MCR_DTR register field. */
1480 #define ALT_UART_MCR_DTR_LSB 0
1481 /* The Most Significant Bit (MSB) position of the ALT_UART_MCR_DTR register field. */
1482 #define ALT_UART_MCR_DTR_MSB 0
1483 /* The width in bits of the ALT_UART_MCR_DTR register field. */
1484 #define ALT_UART_MCR_DTR_WIDTH 1
1485 /* The mask used to set the ALT_UART_MCR_DTR register field value. */
1486 #define ALT_UART_MCR_DTR_SET_MSK 0x00000001
1487 /* The mask used to clear the ALT_UART_MCR_DTR register field value. */
1488 #define ALT_UART_MCR_DTR_CLR_MSK 0xfffffffe
1489 /* The reset value of the ALT_UART_MCR_DTR register field. */
1490 #define ALT_UART_MCR_DTR_RESET 0x0
1491 /* Extracts the ALT_UART_MCR_DTR field value from a register. */
1492 #define ALT_UART_MCR_DTR_GET(value) (((value) & 0x00000001) >> 0)
1493 /* Produces a ALT_UART_MCR_DTR register field value suitable for setting the register. */
1494 #define ALT_UART_MCR_DTR_SET(value) (((value) << 0) & 0x00000001)
1495 
1496 /*
1497  * Field : Request to Send - rts
1498  *
1499  * This is used to directly control the Request to Send (uart_rts_n) output. The
1500  * Request to Send (uart_rts_n) output is used to inform the modem or data set that
1501  * the UART is ready to exchange data. When Auto RTS Flow Control is not enabled
1502  * (MCR[5] set to zero), the uart_rts_n signal is set low by programming MCR[1]
1503  * (RTS) to a high. If Auto Flow Control is active (MCR[5] set to one) and FIFO's
1504  * enable (FCR[0] set to one), the uart_rts_n output is controlled in the same way,
1505  * but is also gated with the receiver FIFO threshold trigger (uart_rts_n is
1506  * inactive high when above the threshold). The uart_rts_n signal will be de-
1507  * asserted when MCR[1] is set low.
1508  *
1509  * Note that in Loopback mode (MCR[4] set to one), the uart_rts_n output is held
1510  * inactive high while the value of this location is internally looped back to an
1511  * input.
1512  *
1513  * Field Enumeration Values:
1514  *
1515  * Enum | Value | Description
1516  * :--------------------------|:------|:---------------------------------
1517  * ALT_UART_MCR_RTS_E_LOGIC1 | 0x0 | uart_rts_n de-asserted (logic 1)
1518  * ALT_UART_MCR_RTS_E_LOGIC0 | 0x1 | uart_rts_n asserted (logic 0)
1519  *
1520  * Field Access Macros:
1521  *
1522  */
1523 /*
1524  * Enumerated value for register field ALT_UART_MCR_RTS
1525  *
1526  * uart_rts_n de-asserted (logic 1)
1527  */
1528 #define ALT_UART_MCR_RTS_E_LOGIC1 0x0
1529 /*
1530  * Enumerated value for register field ALT_UART_MCR_RTS
1531  *
1532  * uart_rts_n asserted (logic 0)
1533  */
1534 #define ALT_UART_MCR_RTS_E_LOGIC0 0x1
1535 
1536 /* The Least Significant Bit (LSB) position of the ALT_UART_MCR_RTS register field. */
1537 #define ALT_UART_MCR_RTS_LSB 1
1538 /* The Most Significant Bit (MSB) position of the ALT_UART_MCR_RTS register field. */
1539 #define ALT_UART_MCR_RTS_MSB 1
1540 /* The width in bits of the ALT_UART_MCR_RTS register field. */
1541 #define ALT_UART_MCR_RTS_WIDTH 1
1542 /* The mask used to set the ALT_UART_MCR_RTS register field value. */
1543 #define ALT_UART_MCR_RTS_SET_MSK 0x00000002
1544 /* The mask used to clear the ALT_UART_MCR_RTS register field value. */
1545 #define ALT_UART_MCR_RTS_CLR_MSK 0xfffffffd
1546 /* The reset value of the ALT_UART_MCR_RTS register field. */
1547 #define ALT_UART_MCR_RTS_RESET 0x0
1548 /* Extracts the ALT_UART_MCR_RTS field value from a register. */
1549 #define ALT_UART_MCR_RTS_GET(value) (((value) & 0x00000002) >> 1)
1550 /* Produces a ALT_UART_MCR_RTS register field value suitable for setting the register. */
1551 #define ALT_UART_MCR_RTS_SET(value) (((value) << 1) & 0x00000002)
1552 
1553 /*
1554  * Field : Out1 - out1
1555  *
1556  * The value written to this location is inverted and driven out on uart_out1_n
1557  * pin.
1558  *
1559  * Note that in Loopback mode (MCR[4] set to one), the uart_out1_n output is held
1560  * inactive high while the value of this location is internally looped back to an
1561  * input.
1562  *
1563  * Field Enumeration Values:
1564  *
1565  * Enum | Value | Description
1566  * :---------------------------|:------|:----------------------------------
1567  * ALT_UART_MCR_OUT1_E_LOGIC1 | 0x0 | uart_out1_n de-asserted (logic 1)
1568  * ALT_UART_MCR_OUT1_E_LOGIC0 | 0x1 | uart_out1_n asserted (logic 0)
1569  *
1570  * Field Access Macros:
1571  *
1572  */
1573 /*
1574  * Enumerated value for register field ALT_UART_MCR_OUT1
1575  *
1576  * uart_out1_n de-asserted (logic 1)
1577  */
1578 #define ALT_UART_MCR_OUT1_E_LOGIC1 0x0
1579 /*
1580  * Enumerated value for register field ALT_UART_MCR_OUT1
1581  *
1582  * uart_out1_n asserted (logic 0)
1583  */
1584 #define ALT_UART_MCR_OUT1_E_LOGIC0 0x1
1585 
1586 /* The Least Significant Bit (LSB) position of the ALT_UART_MCR_OUT1 register field. */
1587 #define ALT_UART_MCR_OUT1_LSB 2
1588 /* The Most Significant Bit (MSB) position of the ALT_UART_MCR_OUT1 register field. */
1589 #define ALT_UART_MCR_OUT1_MSB 2
1590 /* The width in bits of the ALT_UART_MCR_OUT1 register field. */
1591 #define ALT_UART_MCR_OUT1_WIDTH 1
1592 /* The mask used to set the ALT_UART_MCR_OUT1 register field value. */
1593 #define ALT_UART_MCR_OUT1_SET_MSK 0x00000004
1594 /* The mask used to clear the ALT_UART_MCR_OUT1 register field value. */
1595 #define ALT_UART_MCR_OUT1_CLR_MSK 0xfffffffb
1596 /* The reset value of the ALT_UART_MCR_OUT1 register field. */
1597 #define ALT_UART_MCR_OUT1_RESET 0x0
1598 /* Extracts the ALT_UART_MCR_OUT1 field value from a register. */
1599 #define ALT_UART_MCR_OUT1_GET(value) (((value) & 0x00000004) >> 2)
1600 /* Produces a ALT_UART_MCR_OUT1 register field value suitable for setting the register. */
1601 #define ALT_UART_MCR_OUT1_SET(value) (((value) << 2) & 0x00000004)
1602 
1603 /*
1604  * Field : out2 - out2
1605  *
1606  * This is used to directly control the user-designated uart_out2_n output. The
1607  * value written to this location is inverted and driven out on uart_out2_n
1608  *
1609  * Note: In Loopback mode bit 4 of the modem control register (MCR) is set to one,
1610  * the uart_out2_n output is held inactive high while the value of this location is
1611  * internally looped back to an input.
1612  *
1613  * Field Enumeration Values:
1614  *
1615  * Enum | Value | Description
1616  * :---------------------------|:------|:----------------------------------
1617  * ALT_UART_MCR_OUT2_E_LOGIC1 | 0x0 | uart_out2_n de-asserted (logic 1)
1618  * ALT_UART_MCR_OUT2_E_LOGIC0 | 0x1 | uart_out2_n asserted (logic 0)
1619  *
1620  * Field Access Macros:
1621  *
1622  */
1623 /*
1624  * Enumerated value for register field ALT_UART_MCR_OUT2
1625  *
1626  * uart_out2_n de-asserted (logic 1)
1627  */
1628 #define ALT_UART_MCR_OUT2_E_LOGIC1 0x0
1629 /*
1630  * Enumerated value for register field ALT_UART_MCR_OUT2
1631  *
1632  * uart_out2_n asserted (logic 0)
1633  */
1634 #define ALT_UART_MCR_OUT2_E_LOGIC0 0x1
1635 
1636 /* The Least Significant Bit (LSB) position of the ALT_UART_MCR_OUT2 register field. */
1637 #define ALT_UART_MCR_OUT2_LSB 3
1638 /* The Most Significant Bit (MSB) position of the ALT_UART_MCR_OUT2 register field. */
1639 #define ALT_UART_MCR_OUT2_MSB 3
1640 /* The width in bits of the ALT_UART_MCR_OUT2 register field. */
1641 #define ALT_UART_MCR_OUT2_WIDTH 1
1642 /* The mask used to set the ALT_UART_MCR_OUT2 register field value. */
1643 #define ALT_UART_MCR_OUT2_SET_MSK 0x00000008
1644 /* The mask used to clear the ALT_UART_MCR_OUT2 register field value. */
1645 #define ALT_UART_MCR_OUT2_CLR_MSK 0xfffffff7
1646 /* The reset value of the ALT_UART_MCR_OUT2 register field. */
1647 #define ALT_UART_MCR_OUT2_RESET 0x0
1648 /* Extracts the ALT_UART_MCR_OUT2 field value from a register. */
1649 #define ALT_UART_MCR_OUT2_GET(value) (((value) & 0x00000008) >> 3)
1650 /* Produces a ALT_UART_MCR_OUT2 register field value suitable for setting the register. */
1651 #define ALT_UART_MCR_OUT2_SET(value) (((value) << 3) & 0x00000008)
1652 
1653 /*
1654  * Field : LoopBack Bit - loopback
1655  *
1656  * This is used to put the UART into a diagnostic mode for test purposes. If UART
1657  * mode is NOT active, bit [6] of the modem control register MCR is set to zero,
1658  * data on the sout line is held high, while serial data output is looped back to
1659  * the sin line, internally. In this mode all the interrupts are fully functional.
1660  * Also, in loopback mode, the modem control inputs (uart_dsr_n, uart_cts_n,
1661  * uart_ri_n, uart_dcd_n) are disconnected and the modem control outputs
1662  * (uart_dtr_n, uart_rts_n, uart_out1_n, uart_out2_n) are loopedback to the inputs,
1663  * internally.
1664  *
1665  * Field Access Macros:
1666  *
1667  */
1668 /* The Least Significant Bit (LSB) position of the ALT_UART_MCR_LOOPBACK register field. */
1669 #define ALT_UART_MCR_LOOPBACK_LSB 4
1670 /* The Most Significant Bit (MSB) position of the ALT_UART_MCR_LOOPBACK register field. */
1671 #define ALT_UART_MCR_LOOPBACK_MSB 4
1672 /* The width in bits of the ALT_UART_MCR_LOOPBACK register field. */
1673 #define ALT_UART_MCR_LOOPBACK_WIDTH 1
1674 /* The mask used to set the ALT_UART_MCR_LOOPBACK register field value. */
1675 #define ALT_UART_MCR_LOOPBACK_SET_MSK 0x00000010
1676 /* The mask used to clear the ALT_UART_MCR_LOOPBACK register field value. */
1677 #define ALT_UART_MCR_LOOPBACK_CLR_MSK 0xffffffef
1678 /* The reset value of the ALT_UART_MCR_LOOPBACK register field. */
1679 #define ALT_UART_MCR_LOOPBACK_RESET 0x0
1680 /* Extracts the ALT_UART_MCR_LOOPBACK field value from a register. */
1681 #define ALT_UART_MCR_LOOPBACK_GET(value) (((value) & 0x00000010) >> 4)
1682 /* Produces a ALT_UART_MCR_LOOPBACK register field value suitable for setting the register. */
1683 #define ALT_UART_MCR_LOOPBACK_SET(value) (((value) << 4) & 0x00000010)
1684 
1685 /*
1686  * Field : Auto Flow Control Enable - afce
1687  *
1688  * When FIFOs are enabled, the Auto Flow Control enable bits are active.
1689  *
1690  * Field Enumeration Values:
1691  *
1692  * Enum | Value | Description
1693  * :-------------------------|:------|:--------------------------------
1694  * ALT_UART_MCR_AFCE_E_DISD | 0x0 | Auto Flow Control Mode disabled
1695  * ALT_UART_MCR_AFCE_E_END | 0x1 | Auto Flow Control Mode enabled
1696  *
1697  * Field Access Macros:
1698  *
1699  */
1700 /*
1701  * Enumerated value for register field ALT_UART_MCR_AFCE
1702  *
1703  * Auto Flow Control Mode disabled
1704  */
1705 #define ALT_UART_MCR_AFCE_E_DISD 0x0
1706 /*
1707  * Enumerated value for register field ALT_UART_MCR_AFCE
1708  *
1709  * Auto Flow Control Mode enabled
1710  */
1711 #define ALT_UART_MCR_AFCE_E_END 0x1
1712 
1713 /* The Least Significant Bit (LSB) position of the ALT_UART_MCR_AFCE register field. */
1714 #define ALT_UART_MCR_AFCE_LSB 5
1715 /* The Most Significant Bit (MSB) position of the ALT_UART_MCR_AFCE register field. */
1716 #define ALT_UART_MCR_AFCE_MSB 5
1717 /* The width in bits of the ALT_UART_MCR_AFCE register field. */
1718 #define ALT_UART_MCR_AFCE_WIDTH 1
1719 /* The mask used to set the ALT_UART_MCR_AFCE register field value. */
1720 #define ALT_UART_MCR_AFCE_SET_MSK 0x00000020
1721 /* The mask used to clear the ALT_UART_MCR_AFCE register field value. */
1722 #define ALT_UART_MCR_AFCE_CLR_MSK 0xffffffdf
1723 /* The reset value of the ALT_UART_MCR_AFCE register field. */
1724 #define ALT_UART_MCR_AFCE_RESET 0x0
1725 /* Extracts the ALT_UART_MCR_AFCE field value from a register. */
1726 #define ALT_UART_MCR_AFCE_GET(value) (((value) & 0x00000020) >> 5)
1727 /* Produces a ALT_UART_MCR_AFCE register field value suitable for setting the register. */
1728 #define ALT_UART_MCR_AFCE_SET(value) (((value) << 5) & 0x00000020)
1729 
1730 #ifndef __ASSEMBLY__
1731 /*
1732  * WARNING: The C register and register group struct declarations are provided for
1733  * convenience and illustrative purposes. They should, however, be used with
1734  * caution as the C language standard provides no guarantees about the alignment or
1735  * atomicity of device memory accesses. The recommended practice for writing
1736  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1737  * alt_write_word() functions.
1738  *
1739  * The struct declaration for register ALT_UART_MCR.
1740  */
1741 struct ALT_UART_MCR_s
1742 {
1743  uint32_t dtr : 1; /* Data Terminal Ready */
1744  uint32_t rts : 1; /* Request to Send */
1745  uint32_t out1 : 1; /* Out1 */
1746  uint32_t out2 : 1; /* out2 */
1747  uint32_t loopback : 1; /* LoopBack Bit */
1748  uint32_t afce : 1; /* Auto Flow Control Enable */
1749  uint32_t : 26; /* *UNDEFINED* */
1750 };
1751 
1752 /* The typedef declaration for register ALT_UART_MCR. */
1753 typedef volatile struct ALT_UART_MCR_s ALT_UART_MCR_t;
1754 #endif /* __ASSEMBLY__ */
1755 
1756 /* The byte offset of the ALT_UART_MCR register from the beginning of the component. */
1757 #define ALT_UART_MCR_OFST 0x10
1758 /* The address of the ALT_UART_MCR register. */
1759 #define ALT_UART_MCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_MCR_OFST))
1760 
1761 /*
1762  * Register : Line Status Register - lsr
1763  *
1764  * Reports status of transmit and receive.
1765  *
1766  * Register Layout
1767  *
1768  * Bits | Access | Reset | Description
1769  * :-------|:-------|:------|:------------------------------------
1770  * [0] | R | 0x0 | Data Ready bit
1771  * [1] | R | 0x0 | Overrun error
1772  * [2] | R | 0x0 | Parity Error
1773  * [3] | R | 0x0 | Framing Error
1774  * [4] | R | 0x0 | Break Interrupt
1775  * [5] | R | 0x1 | Transmit Holding Register Empty bit
1776  * [6] | R | 0x1 | Transmitter Empty bit
1777  * [7] | R | 0x0 | Receiver FIFO Error bit
1778  * [31:8] | ??? | 0x0 | *UNDEFINED*
1779  *
1780  */
1781 /*
1782  * Field : Data Ready bit - dr
1783  *
1784  * This is used to indicate that the receiver contains at least one character in
1785  * the RBR or the receiver FIFO. This bit is cleared when the RBR is read in the
1786  * non-FIFO mode, or when the receiver FIFO is empty, in the FIFO mode.
1787  *
1788  * Field Enumeration Values:
1789  *
1790  * Enum | Value | Description
1791  * :----------------------------|:------|:--------------
1792  * ALT_UART_LSR_DR_E_NODATARDY | 0x0 | no data ready
1793  * ALT_UART_LSR_DR_E_DATARDY | 0x1 | data ready
1794  *
1795  * Field Access Macros:
1796  *
1797  */
1798 /*
1799  * Enumerated value for register field ALT_UART_LSR_DR
1800  *
1801  * no data ready
1802  */
1803 #define ALT_UART_LSR_DR_E_NODATARDY 0x0
1804 /*
1805  * Enumerated value for register field ALT_UART_LSR_DR
1806  *
1807  * data ready
1808  */
1809 #define ALT_UART_LSR_DR_E_DATARDY 0x1
1810 
1811 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_DR register field. */
1812 #define ALT_UART_LSR_DR_LSB 0
1813 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_DR register field. */
1814 #define ALT_UART_LSR_DR_MSB 0
1815 /* The width in bits of the ALT_UART_LSR_DR register field. */
1816 #define ALT_UART_LSR_DR_WIDTH 1
1817 /* The mask used to set the ALT_UART_LSR_DR register field value. */
1818 #define ALT_UART_LSR_DR_SET_MSK 0x00000001
1819 /* The mask used to clear the ALT_UART_LSR_DR register field value. */
1820 #define ALT_UART_LSR_DR_CLR_MSK 0xfffffffe
1821 /* The reset value of the ALT_UART_LSR_DR register field. */
1822 #define ALT_UART_LSR_DR_RESET 0x0
1823 /* Extracts the ALT_UART_LSR_DR field value from a register. */
1824 #define ALT_UART_LSR_DR_GET(value) (((value) & 0x00000001) >> 0)
1825 /* Produces a ALT_UART_LSR_DR register field value suitable for setting the register. */
1826 #define ALT_UART_LSR_DR_SET(value) (((value) << 0) & 0x00000001)
1827 
1828 /*
1829  * Field : Overrun error - oe
1830  *
1831  * This is used to indicate the occurrence of an overrun error. This occurs if a
1832  * new data character was received before the previous data was read. In the non-
1833  * FIFO mode, the OE bit is set when a new character arrives in the receiver before
1834  * the previous character was read from the RBR. When this happens, the data in the
1835  * RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is
1836  * full and new character arrives at the receiver. The data in the FIFO is retained
1837  * and the data in the receive shift register is lost.Reading the LSR clears the OE
1838  * bit.
1839  *
1840  * Field Enumeration Values:
1841  *
1842  * Enum | Value | Description
1843  * :----------------------------|:------|:-----------------
1844  * ALT_UART_LSR_OE_E_NOOVERRUN | 0x0 | no overrun error
1845  * ALT_UART_LSR_OE_E_OVERRUN | 0x1 | overrun error
1846  *
1847  * Field Access Macros:
1848  *
1849  */
1850 /*
1851  * Enumerated value for register field ALT_UART_LSR_OE
1852  *
1853  * no overrun error
1854  */
1855 #define ALT_UART_LSR_OE_E_NOOVERRUN 0x0
1856 /*
1857  * Enumerated value for register field ALT_UART_LSR_OE
1858  *
1859  * overrun error
1860  */
1861 #define ALT_UART_LSR_OE_E_OVERRUN 0x1
1862 
1863 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_OE register field. */
1864 #define ALT_UART_LSR_OE_LSB 1
1865 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_OE register field. */
1866 #define ALT_UART_LSR_OE_MSB 1
1867 /* The width in bits of the ALT_UART_LSR_OE register field. */
1868 #define ALT_UART_LSR_OE_WIDTH 1
1869 /* The mask used to set the ALT_UART_LSR_OE register field value. */
1870 #define ALT_UART_LSR_OE_SET_MSK 0x00000002
1871 /* The mask used to clear the ALT_UART_LSR_OE register field value. */
1872 #define ALT_UART_LSR_OE_CLR_MSK 0xfffffffd
1873 /* The reset value of the ALT_UART_LSR_OE register field. */
1874 #define ALT_UART_LSR_OE_RESET 0x0
1875 /* Extracts the ALT_UART_LSR_OE field value from a register. */
1876 #define ALT_UART_LSR_OE_GET(value) (((value) & 0x00000002) >> 1)
1877 /* Produces a ALT_UART_LSR_OE register field value suitable for setting the register. */
1878 #define ALT_UART_LSR_OE_SET(value) (((value) << 1) & 0x00000002)
1879 
1880 /*
1881  * Field : Parity Error - pe
1882  *
1883  * This is used to indicate the occurrence of a parity error in the receiver if the
1884  * Parity Enable (PEN) bit (LCR[3]) is set. Since the parity error is associated
1885  * with a character received, it is revealed when the character with the parity
1886  * error arrives at the top of the FIFO. It should be noted that the Parity Error
1887  * (PE) bit (LSR[2]) will be set if a break interrupt has occurred, as indicated by
1888  * Break Interrupt (BI) bit (LSR[4]). Reading the LSR clears the PE bit.
1889  *
1890  * Field Enumeration Values:
1891  *
1892  * Enum | Value | Description
1893  * :------------------------------|:------|:----------------
1894  * ALT_UART_LSR_PE_E_NOPARITYERR | 0x0 | no parity error
1895  * ALT_UART_LSR_PE_E_PARITYERR | 0x1 | no parity error
1896  *
1897  * Field Access Macros:
1898  *
1899  */
1900 /*
1901  * Enumerated value for register field ALT_UART_LSR_PE
1902  *
1903  * no parity error
1904  */
1905 #define ALT_UART_LSR_PE_E_NOPARITYERR 0x0
1906 /*
1907  * Enumerated value for register field ALT_UART_LSR_PE
1908  *
1909  * no parity error
1910  */
1911 #define ALT_UART_LSR_PE_E_PARITYERR 0x1
1912 
1913 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_PE register field. */
1914 #define ALT_UART_LSR_PE_LSB 2
1915 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_PE register field. */
1916 #define ALT_UART_LSR_PE_MSB 2
1917 /* The width in bits of the ALT_UART_LSR_PE register field. */
1918 #define ALT_UART_LSR_PE_WIDTH 1
1919 /* The mask used to set the ALT_UART_LSR_PE register field value. */
1920 #define ALT_UART_LSR_PE_SET_MSK 0x00000004
1921 /* The mask used to clear the ALT_UART_LSR_PE register field value. */
1922 #define ALT_UART_LSR_PE_CLR_MSK 0xfffffffb
1923 /* The reset value of the ALT_UART_LSR_PE register field. */
1924 #define ALT_UART_LSR_PE_RESET 0x0
1925 /* Extracts the ALT_UART_LSR_PE field value from a register. */
1926 #define ALT_UART_LSR_PE_GET(value) (((value) & 0x00000004) >> 2)
1927 /* Produces a ALT_UART_LSR_PE register field value suitable for setting the register. */
1928 #define ALT_UART_LSR_PE_SET(value) (((value) << 2) & 0x00000004)
1929 
1930 /*
1931  * Field : Framing Error - fe
1932  *
1933  * This is used to indicate the occurrence of a framing error in the receiver. A
1934  * framing error occurs when the receiver does not detect a valid STOP bit in the
1935  * received data. In the FIFO mode, since the framing error is associated with a
1936  * character received, it is revealed when the character with the framing error is
1937  * at the top of the FIFO. When a framing error occurs the UART will try to
1938  * resynchronize. It does this by assuming that the error was due to the start bit
1939  * of the next character and then continues receiving the other bit i.e. data,
1940  * and/or parity and stop. It should be noted that the Framing Error (FE)
1941  * bit(LSR[3]) will be set if a break interrupt has occurred, as indicated by a
1942  * Break Interrupt BIT bit (LSR[4]). Reading the LSR clears the FE bit.
1943  *
1944  * Field Enumeration Values:
1945  *
1946  * Enum | Value | Description
1947  * :---------------------------|:------|:-----------------
1948  * ALT_UART_LSR_FE_E_NOFRMERR | 0x0 | no framing error
1949  * ALT_UART_LSR_FE_E_FRMERR | 0x1 | framing error
1950  *
1951  * Field Access Macros:
1952  *
1953  */
1954 /*
1955  * Enumerated value for register field ALT_UART_LSR_FE
1956  *
1957  * no framing error
1958  */
1959 #define ALT_UART_LSR_FE_E_NOFRMERR 0x0
1960 /*
1961  * Enumerated value for register field ALT_UART_LSR_FE
1962  *
1963  * framing error
1964  */
1965 #define ALT_UART_LSR_FE_E_FRMERR 0x1
1966 
1967 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_FE register field. */
1968 #define ALT_UART_LSR_FE_LSB 3
1969 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_FE register field. */
1970 #define ALT_UART_LSR_FE_MSB 3
1971 /* The width in bits of the ALT_UART_LSR_FE register field. */
1972 #define ALT_UART_LSR_FE_WIDTH 1
1973 /* The mask used to set the ALT_UART_LSR_FE register field value. */
1974 #define ALT_UART_LSR_FE_SET_MSK 0x00000008
1975 /* The mask used to clear the ALT_UART_LSR_FE register field value. */
1976 #define ALT_UART_LSR_FE_CLR_MSK 0xfffffff7
1977 /* The reset value of the ALT_UART_LSR_FE register field. */
1978 #define ALT_UART_LSR_FE_RESET 0x0
1979 /* Extracts the ALT_UART_LSR_FE field value from a register. */
1980 #define ALT_UART_LSR_FE_GET(value) (((value) & 0x00000008) >> 3)
1981 /* Produces a ALT_UART_LSR_FE register field value suitable for setting the register. */
1982 #define ALT_UART_LSR_FE_SET(value) (((value) << 3) & 0x00000008)
1983 
1984 /*
1985  * Field : Break Interrupt - bi
1986  *
1987  * This is used to indicate the detection of a break sequence on the serial input
1988  * data. Set whenever the serial input, sin, is held in a logic 0 state for longer
1989  * than the sum of start time + data bits + parity + stop bits. A break condition
1990  * on serial input causes one and only one character, consisting of all zeros, to
1991  * be received by the UART. The character associated with the break condition is
1992  * carried through the FIFO and is revealed when the character is at the top of the
1993  * FIFO. Reading the LSR clears the BI bit.
1994  *
1995  * Field Access Macros:
1996  *
1997  */
1998 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_BI register field. */
1999 #define ALT_UART_LSR_BI_LSB 4
2000 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_BI register field. */
2001 #define ALT_UART_LSR_BI_MSB 4
2002 /* The width in bits of the ALT_UART_LSR_BI register field. */
2003 #define ALT_UART_LSR_BI_WIDTH 1
2004 /* The mask used to set the ALT_UART_LSR_BI register field value. */
2005 #define ALT_UART_LSR_BI_SET_MSK 0x00000010
2006 /* The mask used to clear the ALT_UART_LSR_BI register field value. */
2007 #define ALT_UART_LSR_BI_CLR_MSK 0xffffffef
2008 /* The reset value of the ALT_UART_LSR_BI register field. */
2009 #define ALT_UART_LSR_BI_RESET 0x0
2010 /* Extracts the ALT_UART_LSR_BI field value from a register. */
2011 #define ALT_UART_LSR_BI_GET(value) (((value) & 0x00000010) >> 4)
2012 /* Produces a ALT_UART_LSR_BI register field value suitable for setting the register. */
2013 #define ALT_UART_LSR_BI_SET(value) (((value) << 4) & 0x00000010)
2014 
2015 /*
2016  * Field : Transmit Holding Register Empty bit - thre
2017  *
2018  * If THRE mode is disabled (IER[7] set to zero) this bit indicates that the THR or
2019  * Tx FIFO is empty. This bit is set whenever data is transferred from the THR or
2020  * Tx FIFO to the transmitter shift register and no new data has been written to
2021  * the THR or Tx FIFO. This also causes a THRE Interrupt to occur, if the THRE
2022  * Interrupt is enabled. If both THRE and FIFOs are enabled, both (IER[7] set to
2023  * one and FCR[0] set to one respectively), the functionality will indicate the
2024  * transmitter FIFO is full, and no longer controls THRE interrupts, which are then
2025  * controlled by the FCR[5:4] thresholdsetting.
2026  *
2027  * Field Access Macros:
2028  *
2029  */
2030 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_THRE register field. */
2031 #define ALT_UART_LSR_THRE_LSB 5
2032 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_THRE register field. */
2033 #define ALT_UART_LSR_THRE_MSB 5
2034 /* The width in bits of the ALT_UART_LSR_THRE register field. */
2035 #define ALT_UART_LSR_THRE_WIDTH 1
2036 /* The mask used to set the ALT_UART_LSR_THRE register field value. */
2037 #define ALT_UART_LSR_THRE_SET_MSK 0x00000020
2038 /* The mask used to clear the ALT_UART_LSR_THRE register field value. */
2039 #define ALT_UART_LSR_THRE_CLR_MSK 0xffffffdf
2040 /* The reset value of the ALT_UART_LSR_THRE register field. */
2041 #define ALT_UART_LSR_THRE_RESET 0x1
2042 /* Extracts the ALT_UART_LSR_THRE field value from a register. */
2043 #define ALT_UART_LSR_THRE_GET(value) (((value) & 0x00000020) >> 5)
2044 /* Produces a ALT_UART_LSR_THRE register field value suitable for setting the register. */
2045 #define ALT_UART_LSR_THRE_SET(value) (((value) << 5) & 0x00000020)
2046 
2047 /*
2048  * Field : Transmitter Empty bit - temt
2049  *
2050  * If in FIFO mode and FIFO's enabled (FCR[0] set to one), this bit is set whenever
2051  * the Transmitter Shift Register and the FIFO are both empty. If FIFO's are
2052  * disabled, this bit is set whenever the Transmitter Holding Register and the
2053  * Transmitter Shift Register are both empty.
2054  *
2055  * Field Enumeration Values:
2056  *
2057  * Enum | Value | Description
2058  * :-----------------------------|:------|:-----------------------
2059  * ALT_UART_LSR_TEMT_E_NOTEMPTY | 0x0 | Transmit Empty not set
2060  * ALT_UART_LSR_TEMT_E_EMPTY | 0x1 | Transmit Empty set
2061  *
2062  * Field Access Macros:
2063  *
2064  */
2065 /*
2066  * Enumerated value for register field ALT_UART_LSR_TEMT
2067  *
2068  * Transmit Empty not set
2069  */
2070 #define ALT_UART_LSR_TEMT_E_NOTEMPTY 0x0
2071 /*
2072  * Enumerated value for register field ALT_UART_LSR_TEMT
2073  *
2074  * Transmit Empty set
2075  */
2076 #define ALT_UART_LSR_TEMT_E_EMPTY 0x1
2077 
2078 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_TEMT register field. */
2079 #define ALT_UART_LSR_TEMT_LSB 6
2080 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_TEMT register field. */
2081 #define ALT_UART_LSR_TEMT_MSB 6
2082 /* The width in bits of the ALT_UART_LSR_TEMT register field. */
2083 #define ALT_UART_LSR_TEMT_WIDTH 1
2084 /* The mask used to set the ALT_UART_LSR_TEMT register field value. */
2085 #define ALT_UART_LSR_TEMT_SET_MSK 0x00000040
2086 /* The mask used to clear the ALT_UART_LSR_TEMT register field value. */
2087 #define ALT_UART_LSR_TEMT_CLR_MSK 0xffffffbf
2088 /* The reset value of the ALT_UART_LSR_TEMT register field. */
2089 #define ALT_UART_LSR_TEMT_RESET 0x1
2090 /* Extracts the ALT_UART_LSR_TEMT field value from a register. */
2091 #define ALT_UART_LSR_TEMT_GET(value) (((value) & 0x00000040) >> 6)
2092 /* Produces a ALT_UART_LSR_TEMT register field value suitable for setting the register. */
2093 #define ALT_UART_LSR_TEMT_SET(value) (((value) << 6) & 0x00000040)
2094 
2095 /*
2096  * Field : Receiver FIFO Error bit - rfe
2097  *
2098  * This bit is only relevant when FIFO's are enabled (FCR[0] set to one). This is
2099  * used to indicate if there is at least one parity error, framing error, or break
2100  * indication in the FIFO. This bit is cleared when the LSR is read and the
2101  * character with the error is at the top of the receiver FIFO and there are no
2102  * subsequent errors in the FIFO.
2103  *
2104  * Field Enumeration Values:
2105  *
2106  * Enum | Value | Description
2107  * :-------------------------|:------|:--------------------
2108  * ALT_UART_LSR_RFE_E_NOERR | 0x0 | no error in Rx FIFO
2109  * ALT_UART_LSR_RFE_E_ERR | 0x1 | error in Rx FIFO
2110  *
2111  * Field Access Macros:
2112  *
2113  */
2114 /*
2115  * Enumerated value for register field ALT_UART_LSR_RFE
2116  *
2117  * no error in Rx FIFO
2118  */
2119 #define ALT_UART_LSR_RFE_E_NOERR 0x0
2120 /*
2121  * Enumerated value for register field ALT_UART_LSR_RFE
2122  *
2123  * error in Rx FIFO
2124  */
2125 #define ALT_UART_LSR_RFE_E_ERR 0x1
2126 
2127 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_RFE register field. */
2128 #define ALT_UART_LSR_RFE_LSB 7
2129 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_RFE register field. */
2130 #define ALT_UART_LSR_RFE_MSB 7
2131 /* The width in bits of the ALT_UART_LSR_RFE register field. */
2132 #define ALT_UART_LSR_RFE_WIDTH 1
2133 /* The mask used to set the ALT_UART_LSR_RFE register field value. */
2134 #define ALT_UART_LSR_RFE_SET_MSK 0x00000080
2135 /* The mask used to clear the ALT_UART_LSR_RFE register field value. */
2136 #define ALT_UART_LSR_RFE_CLR_MSK 0xffffff7f
2137 /* The reset value of the ALT_UART_LSR_RFE register field. */
2138 #define ALT_UART_LSR_RFE_RESET 0x0
2139 /* Extracts the ALT_UART_LSR_RFE field value from a register. */
2140 #define ALT_UART_LSR_RFE_GET(value) (((value) & 0x00000080) >> 7)
2141 /* Produces a ALT_UART_LSR_RFE register field value suitable for setting the register. */
2142 #define ALT_UART_LSR_RFE_SET(value) (((value) << 7) & 0x00000080)
2143 
2144 #ifndef __ASSEMBLY__
2145 /*
2146  * WARNING: The C register and register group struct declarations are provided for
2147  * convenience and illustrative purposes. They should, however, be used with
2148  * caution as the C language standard provides no guarantees about the alignment or
2149  * atomicity of device memory accesses. The recommended practice for writing
2150  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2151  * alt_write_word() functions.
2152  *
2153  * The struct declaration for register ALT_UART_LSR.
2154  */
2155 struct ALT_UART_LSR_s
2156 {
2157  const uint32_t dr : 1; /* Data Ready bit */
2158  const uint32_t oe : 1; /* Overrun error */
2159  const uint32_t pe : 1; /* Parity Error */
2160  const uint32_t fe : 1; /* Framing Error */
2161  const uint32_t bi : 1; /* Break Interrupt */
2162  const uint32_t thre : 1; /* Transmit Holding Register Empty bit */
2163  const uint32_t temt : 1; /* Transmitter Empty bit */
2164  const uint32_t rfe : 1; /* Receiver FIFO Error bit */
2165  uint32_t : 24; /* *UNDEFINED* */
2166 };
2167 
2168 /* The typedef declaration for register ALT_UART_LSR. */
2169 typedef volatile struct ALT_UART_LSR_s ALT_UART_LSR_t;
2170 #endif /* __ASSEMBLY__ */
2171 
2172 /* The byte offset of the ALT_UART_LSR register from the beginning of the component. */
2173 #define ALT_UART_LSR_OFST 0x14
2174 /* The address of the ALT_UART_LSR register. */
2175 #define ALT_UART_LSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_LSR_OFST))
2176 
2177 /*
2178  * Register : Modem Status Register - msr
2179  *
2180  * It should be noted that whenever bits 0, 1, 2 or 3 are set to logic one, to
2181  * indicate a change on the modem control inputs, a modem status interrupt will be
2182  * generated if enabled via the IER regardless of when the change occurred. Since
2183  * the delta bits (bits 0, 1, 3) can get set after a reset if their respective
2184  * modem signals are active (see individual bits for details), a read of the MSR
2185  * after reset can be performed to prevent unwanted interrupts.
2186  *
2187  * Register Layout
2188  *
2189  * Bits | Access | Reset | Description
2190  * :-------|:-------|:------|:--------------------------------
2191  * [0] | R | 0x0 | Delta Clear to Send
2192  * [1] | R | 0x0 | Delta Data Set Ready
2193  * [2] | R | 0x0 | Trailing Edge of Ring Indicator
2194  * [3] | R | 0x0 | Delta Data Carrier Detect
2195  * [4] | R | 0x0 | Clear to Send
2196  * [5] | R | 0x0 | Data Set Ready
2197  * [6] | R | 0x0 | Ring Indicator
2198  * [7] | R | 0x0 | Data Carrier Detect
2199  * [31:8] | ??? | 0x0 | *UNDEFINED*
2200  *
2201  */
2202 /*
2203  * Field : Delta Clear to Send - dcts
2204  *
2205  * This is used to indicate that the modem control line uart_cts_n has changed
2206  * since the last time the MSR was read. That is: Reading the MSR clears the DCTS
2207  * bit. In Loopback Mode bit [4] of MCR set to one, DCTS reflects changes on bit
2208  * [1] RTS of register MCR.
2209  *
2210  * Note: If the DCTS bit is not set and the uart_cts_n signal is asserted (low) and
2211  * a reset occurs (software or otherwise), then the DCTS bit will get set when the
2212  * reset is removed if the uart_cts_n signal remains asserted.
2213  *
2214  * Field Enumeration Values:
2215  *
2216  * Enum | Value | Description
2217  * :--------------------------|:------|:-----------------------------------------------
2218  * ALT_UART_MSR_DCTS_E_NOCHG | 0x0 | no change on uart_cts_n since last read of MSR
2219  * ALT_UART_MSR_DCTS_E_CHG | 0x1 | change on uart_cts_n since last read of MSR
2220  *
2221  * Field Access Macros:
2222  *
2223  */
2224 /*
2225  * Enumerated value for register field ALT_UART_MSR_DCTS
2226  *
2227  * no change on uart_cts_n since last read of MSR
2228  */
2229 #define ALT_UART_MSR_DCTS_E_NOCHG 0x0
2230 /*
2231  * Enumerated value for register field ALT_UART_MSR_DCTS
2232  *
2233  * change on uart_cts_n since last read of MSR
2234  */
2235 #define ALT_UART_MSR_DCTS_E_CHG 0x1
2236 
2237 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DCTS register field. */
2238 #define ALT_UART_MSR_DCTS_LSB 0
2239 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DCTS register field. */
2240 #define ALT_UART_MSR_DCTS_MSB 0
2241 /* The width in bits of the ALT_UART_MSR_DCTS register field. */
2242 #define ALT_UART_MSR_DCTS_WIDTH 1
2243 /* The mask used to set the ALT_UART_MSR_DCTS register field value. */
2244 #define ALT_UART_MSR_DCTS_SET_MSK 0x00000001
2245 /* The mask used to clear the ALT_UART_MSR_DCTS register field value. */
2246 #define ALT_UART_MSR_DCTS_CLR_MSK 0xfffffffe
2247 /* The reset value of the ALT_UART_MSR_DCTS register field. */
2248 #define ALT_UART_MSR_DCTS_RESET 0x0
2249 /* Extracts the ALT_UART_MSR_DCTS field value from a register. */
2250 #define ALT_UART_MSR_DCTS_GET(value) (((value) & 0x00000001) >> 0)
2251 /* Produces a ALT_UART_MSR_DCTS register field value suitable for setting the register. */
2252 #define ALT_UART_MSR_DCTS_SET(value) (((value) << 0) & 0x00000001)
2253 
2254 /*
2255  * Field : Delta Data Set Ready - ddsr
2256  *
2257  * This is used to indicate that the modem control line uart_dsr_n has changed
2258  * since the last time the MSR was read. Reading the MSR clears the DDSR bit.In
2259  * Loopback Mode (MCR[4] set to one), DDSR reflects changes on bit [0] DTR of
2260  * register MCR .
2261  *
2262  * Note, if the DDSR bit is not set and the uart_dsr_n signal is asserted (low) and
2263  * a reset occurs (software or otherwise), then the DDSR bit will get set when the
2264  * reset is removed if the uart_dsr_n signal remains asserted.
2265  *
2266  * Field Enumeration Values:
2267  *
2268  * Enum | Value | Description
2269  * :--------------------------|:------|:-----------------------------------------------
2270  * ALT_UART_MSR_DDSR_E_NOCHG | 0x0 | no change on uart_dsr_n since last read of MSR
2271  * ALT_UART_MSR_DDSR_E_CHG | 0x1 | change on uart_dsr_n since last read of MSR
2272  *
2273  * Field Access Macros:
2274  *
2275  */
2276 /*
2277  * Enumerated value for register field ALT_UART_MSR_DDSR
2278  *
2279  * no change on uart_dsr_n since last read of MSR
2280  */
2281 #define ALT_UART_MSR_DDSR_E_NOCHG 0x0
2282 /*
2283  * Enumerated value for register field ALT_UART_MSR_DDSR
2284  *
2285  * change on uart_dsr_n since last read of MSR
2286  */
2287 #define ALT_UART_MSR_DDSR_E_CHG 0x1
2288 
2289 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DDSR register field. */
2290 #define ALT_UART_MSR_DDSR_LSB 1
2291 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DDSR register field. */
2292 #define ALT_UART_MSR_DDSR_MSB 1
2293 /* The width in bits of the ALT_UART_MSR_DDSR register field. */
2294 #define ALT_UART_MSR_DDSR_WIDTH 1
2295 /* The mask used to set the ALT_UART_MSR_DDSR register field value. */
2296 #define ALT_UART_MSR_DDSR_SET_MSK 0x00000002
2297 /* The mask used to clear the ALT_UART_MSR_DDSR register field value. */
2298 #define ALT_UART_MSR_DDSR_CLR_MSK 0xfffffffd
2299 /* The reset value of the ALT_UART_MSR_DDSR register field. */
2300 #define ALT_UART_MSR_DDSR_RESET 0x0
2301 /* Extracts the ALT_UART_MSR_DDSR field value from a register. */
2302 #define ALT_UART_MSR_DDSR_GET(value) (((value) & 0x00000002) >> 1)
2303 /* Produces a ALT_UART_MSR_DDSR register field value suitable for setting the register. */
2304 #define ALT_UART_MSR_DDSR_SET(value) (((value) << 1) & 0x00000002)
2305 
2306 /*
2307  * Field : Trailing Edge of Ring Indicator - teri
2308  *
2309  * This is used to indicate that a change on the input uart_ri_n (from an active
2310  * low, to an inactive high state) has occurred since the last time the MSR was
2311  * read. Reading the MSR clears the TERI bit. In Loopback Mode bit [4] of register
2312  * MCR is set to one, TERI reflects when bit [2] of register MCR has changed state
2313  * from a high to a low.
2314  *
2315  * Field Enumeration Values:
2316  *
2317  * Enum | Value | Description
2318  * :--------------------------|:------|:----------------------------------------------
2319  * ALT_UART_MSR_TERI_E_NOCHG | 0x0 | no change on uart_ri_n since last read of MSR
2320  * ALT_UART_MSR_TERI_E_CHG | 0x1 | change on uart_ri_n since last read of MSR
2321  *
2322  * Field Access Macros:
2323  *
2324  */
2325 /*
2326  * Enumerated value for register field ALT_UART_MSR_TERI
2327  *
2328  * no change on uart_ri_n since last read of MSR
2329  */
2330 #define ALT_UART_MSR_TERI_E_NOCHG 0x0
2331 /*
2332  * Enumerated value for register field ALT_UART_MSR_TERI
2333  *
2334  * change on uart_ri_n since last read of MSR
2335  */
2336 #define ALT_UART_MSR_TERI_E_CHG 0x1
2337 
2338 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_TERI register field. */
2339 #define ALT_UART_MSR_TERI_LSB 2
2340 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_TERI register field. */
2341 #define ALT_UART_MSR_TERI_MSB 2
2342 /* The width in bits of the ALT_UART_MSR_TERI register field. */
2343 #define ALT_UART_MSR_TERI_WIDTH 1
2344 /* The mask used to set the ALT_UART_MSR_TERI register field value. */
2345 #define ALT_UART_MSR_TERI_SET_MSK 0x00000004
2346 /* The mask used to clear the ALT_UART_MSR_TERI register field value. */
2347 #define ALT_UART_MSR_TERI_CLR_MSK 0xfffffffb
2348 /* The reset value of the ALT_UART_MSR_TERI register field. */
2349 #define ALT_UART_MSR_TERI_RESET 0x0
2350 /* Extracts the ALT_UART_MSR_TERI field value from a register. */
2351 #define ALT_UART_MSR_TERI_GET(value) (((value) & 0x00000004) >> 2)
2352 /* Produces a ALT_UART_MSR_TERI register field value suitable for setting the register. */
2353 #define ALT_UART_MSR_TERI_SET(value) (((value) << 2) & 0x00000004)
2354 
2355 /*
2356  * Field : Delta Data Carrier Detect - ddcd
2357  *
2358  * This is used to indicate that the modem control line dcd_n has changed since the
2359  * last time the MSR was read. Reading the MSR clears the DDCD bit. In Loopback
2360  * Mode bit [4] of register MCR is set to one, DDCD reflects changes bit [3]
2361  * uart_out2 of register MCR.
2362  *
2363  * Note: If the DDCD bit is not set and the uart_dcd_n signal is asserted (low) and
2364  * a reset occurs (software or otherwise), then the DDCD bit will get set when the
2365  * reset is removed if the uart_dcd_n signal remains asserted.
2366  *
2367  * Field Enumeration Values:
2368  *
2369  * Enum | Value | Description
2370  * :--------------------------|:------|:-----------------------------------------------
2371  * ALT_UART_MSR_DDCD_E_NOCHG | 0x0 | no change on uart_dcd_n since last read of MSR
2372  * ALT_UART_MSR_DDCD_E_CHG | 0x1 | change on uart_dcd_n since last read of MSR
2373  *
2374  * Field Access Macros:
2375  *
2376  */
2377 /*
2378  * Enumerated value for register field ALT_UART_MSR_DDCD
2379  *
2380  * no change on uart_dcd_n since last read of MSR
2381  */
2382 #define ALT_UART_MSR_DDCD_E_NOCHG 0x0
2383 /*
2384  * Enumerated value for register field ALT_UART_MSR_DDCD
2385  *
2386  * change on uart_dcd_n since last read of MSR
2387  */
2388 #define ALT_UART_MSR_DDCD_E_CHG 0x1
2389 
2390 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DDCD register field. */
2391 #define ALT_UART_MSR_DDCD_LSB 3
2392 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DDCD register field. */
2393 #define ALT_UART_MSR_DDCD_MSB 3
2394 /* The width in bits of the ALT_UART_MSR_DDCD register field. */
2395 #define ALT_UART_MSR_DDCD_WIDTH 1
2396 /* The mask used to set the ALT_UART_MSR_DDCD register field value. */
2397 #define ALT_UART_MSR_DDCD_SET_MSK 0x00000008
2398 /* The mask used to clear the ALT_UART_MSR_DDCD register field value. */
2399 #define ALT_UART_MSR_DDCD_CLR_MSK 0xfffffff7
2400 /* The reset value of the ALT_UART_MSR_DDCD register field. */
2401 #define ALT_UART_MSR_DDCD_RESET 0x0
2402 /* Extracts the ALT_UART_MSR_DDCD field value from a register. */
2403 #define ALT_UART_MSR_DDCD_GET(value) (((value) & 0x00000008) >> 3)
2404 /* Produces a ALT_UART_MSR_DDCD register field value suitable for setting the register. */
2405 #define ALT_UART_MSR_DDCD_SET(value) (((value) << 3) & 0x00000008)
2406 
2407 /*
2408  * Field : Clear to Send - cts
2409  *
2410  * This is used to indicate the current state of the modem control line uart_cts_n.
2411  * That is, this bit is the complement uart_cts_n. When the Clear to Send input
2412  * (uart_cts_n) is asserted it is an indication that the modem or data set is ready
2413  * to exchange data with the uart. In Loopback Mode bit [4] of register MCR is set
2414  * to one, CTS is the same as bit [1] RTS of register MCR.
2415  *
2416  * Field Enumeration Values:
2417  *
2418  * Enum | Value | Description
2419  * :--------------------------|:------|:------------------------------------------
2420  * ALT_UART_MSR_CTS_E_LOGIC1 | 0x0 | uart_cts_n input is de-asserted (logic 1)
2421  * ALT_UART_MSR_CTS_E_LOGIC0 | 0x1 | uart_cts_n input is asserted (logic 0)
2422  *
2423  * Field Access Macros:
2424  *
2425  */
2426 /*
2427  * Enumerated value for register field ALT_UART_MSR_CTS
2428  *
2429  * uart_cts_n input is de-asserted (logic 1)
2430  */
2431 #define ALT_UART_MSR_CTS_E_LOGIC1 0x0
2432 /*
2433  * Enumerated value for register field ALT_UART_MSR_CTS
2434  *
2435  * uart_cts_n input is asserted (logic 0)
2436  */
2437 #define ALT_UART_MSR_CTS_E_LOGIC0 0x1
2438 
2439 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_CTS register field. */
2440 #define ALT_UART_MSR_CTS_LSB 4
2441 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_CTS register field. */
2442 #define ALT_UART_MSR_CTS_MSB 4
2443 /* The width in bits of the ALT_UART_MSR_CTS register field. */
2444 #define ALT_UART_MSR_CTS_WIDTH 1
2445 /* The mask used to set the ALT_UART_MSR_CTS register field value. */
2446 #define ALT_UART_MSR_CTS_SET_MSK 0x00000010
2447 /* The mask used to clear the ALT_UART_MSR_CTS register field value. */
2448 #define ALT_UART_MSR_CTS_CLR_MSK 0xffffffef
2449 /* The reset value of the ALT_UART_MSR_CTS register field. */
2450 #define ALT_UART_MSR_CTS_RESET 0x0
2451 /* Extracts the ALT_UART_MSR_CTS field value from a register. */
2452 #define ALT_UART_MSR_CTS_GET(value) (((value) & 0x00000010) >> 4)
2453 /* Produces a ALT_UART_MSR_CTS register field value suitable for setting the register. */
2454 #define ALT_UART_MSR_CTS_SET(value) (((value) << 4) & 0x00000010)
2455 
2456 /*
2457  * Field : Data Set Ready - dsr
2458  *
2459  * This is used to indicate the current state of the modem control line uart_dsr_n.
2460  * That is this bit is the complement f uart_dsr_n. When the Data Set Ready input
2461  * (uart_dsr_n) is asserted it is an indication that the modem or data set is ready
2462  * to establish communications with the uart. In Loopback Mode bit [4] of register
2463  * MCR is set to one, DSR is the same as bit [0] (DTR) of register MCR.
2464  *
2465  * Field Enumeration Values:
2466  *
2467  * Enum | Value | Description
2468  * :--------------------------|:------|:------------------------------------------
2469  * ALT_UART_MSR_DSR_E_LOGIC1 | 0x0 | uart_dsr_n input is de-asserted (logic 1)
2470  * ALT_UART_MSR_DSR_E_LOGIC0 | 0x1 | uart_dsr_n input is asserted (logic 0)
2471  *
2472  * Field Access Macros:
2473  *
2474  */
2475 /*
2476  * Enumerated value for register field ALT_UART_MSR_DSR
2477  *
2478  * uart_dsr_n input is de-asserted (logic 1)
2479  */
2480 #define ALT_UART_MSR_DSR_E_LOGIC1 0x0
2481 /*
2482  * Enumerated value for register field ALT_UART_MSR_DSR
2483  *
2484  * uart_dsr_n input is asserted (logic 0)
2485  */
2486 #define ALT_UART_MSR_DSR_E_LOGIC0 0x1
2487 
2488 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DSR register field. */
2489 #define ALT_UART_MSR_DSR_LSB 5
2490 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DSR register field. */
2491 #define ALT_UART_MSR_DSR_MSB 5
2492 /* The width in bits of the ALT_UART_MSR_DSR register field. */
2493 #define ALT_UART_MSR_DSR_WIDTH 1
2494 /* The mask used to set the ALT_UART_MSR_DSR register field value. */
2495 #define ALT_UART_MSR_DSR_SET_MSK 0x00000020
2496 /* The mask used to clear the ALT_UART_MSR_DSR register field value. */
2497 #define ALT_UART_MSR_DSR_CLR_MSK 0xffffffdf
2498 /* The reset value of the ALT_UART_MSR_DSR register field. */
2499 #define ALT_UART_MSR_DSR_RESET 0x0
2500 /* Extracts the ALT_UART_MSR_DSR field value from a register. */
2501 #define ALT_UART_MSR_DSR_GET(value) (((value) & 0x00000020) >> 5)
2502 /* Produces a ALT_UART_MSR_DSR register field value suitable for setting the register. */
2503 #define ALT_UART_MSR_DSR_SET(value) (((value) << 5) & 0x00000020)
2504 
2505 /*
2506  * Field : Ring Indicator - ri
2507  *
2508  * This bit is used to indicate the current state of the modem control line
2509  * uart_ri_n. That is this bit is the complement uart_ri_n. When the Ring Indicator
2510  * input (uart_ri_n) is asserted it is an indication that a telephone ringing
2511  * signal has been received by the modem or data set. In Loopback Mode bit [4] of
2512  * register MCR set to one, RI is the same as bit [2] uart_out1_n of register MCR.
2513  *
2514  * Field Enumeration Values:
2515  *
2516  * Enum | Value | Description
2517  * :-------------------------|:------|:-----------------------------------------
2518  * ALT_UART_MSR_RI_E_LOGIC1 | 0x0 | uart_ri_n input is de-asserted (logic 1)
2519  * ALT_UART_MSR_RI_E_LOGIC0 | 0x1 | uart_ri_n input is asserted (logic 0)
2520  *
2521  * Field Access Macros:
2522  *
2523  */
2524 /*
2525  * Enumerated value for register field ALT_UART_MSR_RI
2526  *
2527  * uart_ri_n input is de-asserted (logic 1)
2528  */
2529 #define ALT_UART_MSR_RI_E_LOGIC1 0x0
2530 /*
2531  * Enumerated value for register field ALT_UART_MSR_RI
2532  *
2533  * uart_ri_n input is asserted (logic 0)
2534  */
2535 #define ALT_UART_MSR_RI_E_LOGIC0 0x1
2536 
2537 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_RI register field. */
2538 #define ALT_UART_MSR_RI_LSB 6
2539 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_RI register field. */
2540 #define ALT_UART_MSR_RI_MSB 6
2541 /* The width in bits of the ALT_UART_MSR_RI register field. */
2542 #define ALT_UART_MSR_RI_WIDTH 1
2543 /* The mask used to set the ALT_UART_MSR_RI register field value. */
2544 #define ALT_UART_MSR_RI_SET_MSK 0x00000040
2545 /* The mask used to clear the ALT_UART_MSR_RI register field value. */
2546 #define ALT_UART_MSR_RI_CLR_MSK 0xffffffbf
2547 /* The reset value of the ALT_UART_MSR_RI register field. */
2548 #define ALT_UART_MSR_RI_RESET 0x0
2549 /* Extracts the ALT_UART_MSR_RI field value from a register. */
2550 #define ALT_UART_MSR_RI_GET(value) (((value) & 0x00000040) >> 6)
2551 /* Produces a ALT_UART_MSR_RI register field value suitable for setting the register. */
2552 #define ALT_UART_MSR_RI_SET(value) (((value) << 6) & 0x00000040)
2553 
2554 /*
2555  * Field : Data Carrier Detect - dcd
2556  *
2557  * This is used to indicate the current state of the modem control line uart_dcd_n.
2558  * That is this bit is the complement uart_dcd_n. When the Data Carrier Detect
2559  * input (uart_dcd_n) is asserted it is an indication that the carrier has been
2560  * detected by the modem or data set. In Loopback Mode (MCR[4] set to one), DCD is
2561  * the same as MCR[3] (uart_out2).
2562  *
2563  * Field Enumeration Values:
2564  *
2565  * Enum | Value | Description
2566  * :--------------------------|:------|:------------------------------------------
2567  * ALT_UART_MSR_DCD_E_LOGIC1 | 0x0 | uart_dcd_n input is de-asserted (logic 1)
2568  * ALT_UART_MSR_DCD_E_LOGIC0 | 0x1 | uart_dcd_n input is asserted (logic 0)
2569  *
2570  * Field Access Macros:
2571  *
2572  */
2573 /*
2574  * Enumerated value for register field ALT_UART_MSR_DCD
2575  *
2576  * uart_dcd_n input is de-asserted (logic 1)
2577  */
2578 #define ALT_UART_MSR_DCD_E_LOGIC1 0x0
2579 /*
2580  * Enumerated value for register field ALT_UART_MSR_DCD
2581  *
2582  * uart_dcd_n input is asserted (logic 0)
2583  */
2584 #define ALT_UART_MSR_DCD_E_LOGIC0 0x1
2585 
2586 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DCD register field. */
2587 #define ALT_UART_MSR_DCD_LSB 7
2588 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DCD register field. */
2589 #define ALT_UART_MSR_DCD_MSB 7
2590 /* The width in bits of the ALT_UART_MSR_DCD register field. */
2591 #define ALT_UART_MSR_DCD_WIDTH 1
2592 /* The mask used to set the ALT_UART_MSR_DCD register field value. */
2593 #define ALT_UART_MSR_DCD_SET_MSK 0x00000080
2594 /* The mask used to clear the ALT_UART_MSR_DCD register field value. */
2595 #define ALT_UART_MSR_DCD_CLR_MSK 0xffffff7f
2596 /* The reset value of the ALT_UART_MSR_DCD register field. */
2597 #define ALT_UART_MSR_DCD_RESET 0x0
2598 /* Extracts the ALT_UART_MSR_DCD field value from a register. */
2599 #define ALT_UART_MSR_DCD_GET(value) (((value) & 0x00000080) >> 7)
2600 /* Produces a ALT_UART_MSR_DCD register field value suitable for setting the register. */
2601 #define ALT_UART_MSR_DCD_SET(value) (((value) << 7) & 0x00000080)
2602 
2603 #ifndef __ASSEMBLY__
2604 /*
2605  * WARNING: The C register and register group struct declarations are provided for
2606  * convenience and illustrative purposes. They should, however, be used with
2607  * caution as the C language standard provides no guarantees about the alignment or
2608  * atomicity of device memory accesses. The recommended practice for writing
2609  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2610  * alt_write_word() functions.
2611  *
2612  * The struct declaration for register ALT_UART_MSR.
2613  */
2614 struct ALT_UART_MSR_s
2615 {
2616  const uint32_t dcts : 1; /* Delta Clear to Send */
2617  const uint32_t ddsr : 1; /* Delta Data Set Ready */
2618  const uint32_t teri : 1; /* Trailing Edge of Ring Indicator */
2619  const uint32_t ddcd : 1; /* Delta Data Carrier Detect */
2620  const uint32_t cts : 1; /* Clear to Send */
2621  const uint32_t dsr : 1; /* Data Set Ready */
2622  const uint32_t ri : 1; /* Ring Indicator */
2623  const uint32_t dcd : 1; /* Data Carrier Detect */
2624  uint32_t : 24; /* *UNDEFINED* */
2625 };
2626 
2627 /* The typedef declaration for register ALT_UART_MSR. */
2628 typedef volatile struct ALT_UART_MSR_s ALT_UART_MSR_t;
2629 #endif /* __ASSEMBLY__ */
2630 
2631 /* The byte offset of the ALT_UART_MSR register from the beginning of the component. */
2632 #define ALT_UART_MSR_OFST 0x18
2633 /* The address of the ALT_UART_MSR register. */
2634 #define ALT_UART_MSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_MSR_OFST))
2635 
2636 /*
2637  * Register : Scratchpad Register - scr
2638  *
2639  * Scratchpad Register
2640  *
2641  * Register Layout
2642  *
2643  * Bits | Access | Reset | Description
2644  * :-------|:-------|:------|:--------------------
2645  * [7:0] | RW | 0x0 | Scratchpad Register
2646  * [31:8] | ??? | 0x0 | *UNDEFINED*
2647  *
2648  */
2649 /*
2650  * Field : Scratchpad Register - scr
2651  *
2652  * This register is for programmers to use as a temporary storage space.
2653  *
2654  * Field Access Macros:
2655  *
2656  */
2657 /* The Least Significant Bit (LSB) position of the ALT_UART_SCR_SCR register field. */
2658 #define ALT_UART_SCR_SCR_LSB 0
2659 /* The Most Significant Bit (MSB) position of the ALT_UART_SCR_SCR register field. */
2660 #define ALT_UART_SCR_SCR_MSB 7
2661 /* The width in bits of the ALT_UART_SCR_SCR register field. */
2662 #define ALT_UART_SCR_SCR_WIDTH 8
2663 /* The mask used to set the ALT_UART_SCR_SCR register field value. */
2664 #define ALT_UART_SCR_SCR_SET_MSK 0x000000ff
2665 /* The mask used to clear the ALT_UART_SCR_SCR register field value. */
2666 #define ALT_UART_SCR_SCR_CLR_MSK 0xffffff00
2667 /* The reset value of the ALT_UART_SCR_SCR register field. */
2668 #define ALT_UART_SCR_SCR_RESET 0x0
2669 /* Extracts the ALT_UART_SCR_SCR field value from a register. */
2670 #define ALT_UART_SCR_SCR_GET(value) (((value) & 0x000000ff) >> 0)
2671 /* Produces a ALT_UART_SCR_SCR register field value suitable for setting the register. */
2672 #define ALT_UART_SCR_SCR_SET(value) (((value) << 0) & 0x000000ff)
2673 
2674 #ifndef __ASSEMBLY__
2675 /*
2676  * WARNING: The C register and register group struct declarations are provided for
2677  * convenience and illustrative purposes. They should, however, be used with
2678  * caution as the C language standard provides no guarantees about the alignment or
2679  * atomicity of device memory accesses. The recommended practice for writing
2680  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2681  * alt_write_word() functions.
2682  *
2683  * The struct declaration for register ALT_UART_SCR.
2684  */
2685 struct ALT_UART_SCR_s
2686 {
2687  uint32_t scr : 8; /* Scratchpad Register */
2688  uint32_t : 24; /* *UNDEFINED* */
2689 };
2690 
2691 /* The typedef declaration for register ALT_UART_SCR. */
2692 typedef volatile struct ALT_UART_SCR_s ALT_UART_SCR_t;
2693 #endif /* __ASSEMBLY__ */
2694 
2695 /* The byte offset of the ALT_UART_SCR register from the beginning of the component. */
2696 #define ALT_UART_SCR_OFST 0x1c
2697 /* The address of the ALT_UART_SCR register. */
2698 #define ALT_UART_SCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SCR_OFST))
2699 
2700 /*
2701  * Register : Shadow Receive Buffer Register - srbr
2702  *
2703  * Used to accomadate burst accesses from the master.
2704  *
2705  * Register Layout
2706  *
2707  * Bits | Access | Reset | Description
2708  * :-------|:-------|:------|:----------------------
2709  * [7:0] | RW | 0x0 | Shadow Receive Buffer
2710  * [31:8] | ??? | 0x0 | *UNDEFINED*
2711  *
2712  */
2713 /*
2714  * Field : Shadow Receive Buffer - srbr
2715  *
2716  * This is a shadow register for the RBR and has been allocated one 32-bit location
2717  * so as to accommodate burst accesses from the master.This register contains the
2718  * data byte received on the serial input port (sin). The data in this register is
2719  * valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set.
2720  * If FIFOs are disabled, bit [0] of register FCR set to zero, the data in the RBR
2721  * must be read before the next data arrives, otherwise it will be overwritten,
2722  * resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this
2723  * register accesses the head of the receive FIFO. If the receive FIFO is full and
2724  * this register is not read before the next data character arrives, then the data
2725  * already in the FIFO will be preserved but any incoming data will be lost. An
2726  * overrun error will also occur.
2727  *
2728  * Field Access Macros:
2729  *
2730  */
2731 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_SRBR register field. */
2732 #define ALT_UART_SRBR_SRBR_LSB 0
2733 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_SRBR register field. */
2734 #define ALT_UART_SRBR_SRBR_MSB 7
2735 /* The width in bits of the ALT_UART_SRBR_SRBR register field. */
2736 #define ALT_UART_SRBR_SRBR_WIDTH 8
2737 /* The mask used to set the ALT_UART_SRBR_SRBR register field value. */
2738 #define ALT_UART_SRBR_SRBR_SET_MSK 0x000000ff
2739 /* The mask used to clear the ALT_UART_SRBR_SRBR register field value. */
2740 #define ALT_UART_SRBR_SRBR_CLR_MSK 0xffffff00
2741 /* The reset value of the ALT_UART_SRBR_SRBR register field. */
2742 #define ALT_UART_SRBR_SRBR_RESET 0x0
2743 /* Extracts the ALT_UART_SRBR_SRBR field value from a register. */
2744 #define ALT_UART_SRBR_SRBR_GET(value) (((value) & 0x000000ff) >> 0)
2745 /* Produces a ALT_UART_SRBR_SRBR register field value suitable for setting the register. */
2746 #define ALT_UART_SRBR_SRBR_SET(value) (((value) << 0) & 0x000000ff)
2747 
2748 #ifndef __ASSEMBLY__
2749 /*
2750  * WARNING: The C register and register group struct declarations are provided for
2751  * convenience and illustrative purposes. They should, however, be used with
2752  * caution as the C language standard provides no guarantees about the alignment or
2753  * atomicity of device memory accesses. The recommended practice for writing
2754  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2755  * alt_write_word() functions.
2756  *
2757  * The struct declaration for register ALT_UART_SRBR.
2758  */
2759 struct ALT_UART_SRBR_s
2760 {
2761  uint32_t srbr : 8; /* Shadow Receive Buffer */
2762  uint32_t : 24; /* *UNDEFINED* */
2763 };
2764 
2765 /* The typedef declaration for register ALT_UART_SRBR. */
2766 typedef volatile struct ALT_UART_SRBR_s ALT_UART_SRBR_t;
2767 #endif /* __ASSEMBLY__ */
2768 
2769 /* The byte offset of the ALT_UART_SRBR register from the beginning of the component. */
2770 #define ALT_UART_SRBR_OFST 0x30
2771 /* The address of the ALT_UART_SRBR register. */
2772 #define ALT_UART_SRBR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_OFST))
2773 
2774 /*
2775  * Register : Shadow Transmit Buffer Register - sthr
2776  *
2777  * Used to accomadate burst accesses from the master.
2778  *
2779  * Register Layout
2780  *
2781  * Bits | Access | Reset | Description
2782  * :-------|:-------|:------|:-----------------------
2783  * [7:0] | RW | 0x0 | Shadow Transmit Buffer
2784  * [31:8] | ??? | 0x0 | *UNDEFINED*
2785  *
2786  */
2787 /*
2788  * Field : Shadow Transmit Buffer - sthr
2789  *
2790  * This is a shadow register for the THR and has been allocated sixteen 32-bit
2791  * locations so as to accommodate burst accesses from the master. This register
2792  * contains data to be transmitted on the serial output port (sout). Data should
2793  * only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If
2794  * FIFO's are disabled bit [0] of register FCR set to zero and THRE is set, writing
2795  * a single character to the THR clears the THRE. Any additional writes to the THR
2796  * before the THRE is set again causes the THR data to be overwritten. If FIFO's
2797  * are enabled bit [0] of register FCR set to one and THRE is set, 128 characters
2798  * of data may be written to the THR before the FIFO is full. The UART FIFO depth
2799  * is configured for 128 characters. Any attempt to write data when the FIFO is
2800  * full results in the write data being lost.
2801  *
2802  * Field Access Macros:
2803  *
2804  */
2805 /* The Least Significant Bit (LSB) position of the ALT_UART_STHR_STHR register field. */
2806 #define ALT_UART_STHR_STHR_LSB 0
2807 /* The Most Significant Bit (MSB) position of the ALT_UART_STHR_STHR register field. */
2808 #define ALT_UART_STHR_STHR_MSB 7
2809 /* The width in bits of the ALT_UART_STHR_STHR register field. */
2810 #define ALT_UART_STHR_STHR_WIDTH 8
2811 /* The mask used to set the ALT_UART_STHR_STHR register field value. */
2812 #define ALT_UART_STHR_STHR_SET_MSK 0x000000ff
2813 /* The mask used to clear the ALT_UART_STHR_STHR register field value. */
2814 #define ALT_UART_STHR_STHR_CLR_MSK 0xffffff00
2815 /* The reset value of the ALT_UART_STHR_STHR register field. */
2816 #define ALT_UART_STHR_STHR_RESET 0x0
2817 /* Extracts the ALT_UART_STHR_STHR field value from a register. */
2818 #define ALT_UART_STHR_STHR_GET(value) (((value) & 0x000000ff) >> 0)
2819 /* Produces a ALT_UART_STHR_STHR register field value suitable for setting the register. */
2820 #define ALT_UART_STHR_STHR_SET(value) (((value) << 0) & 0x000000ff)
2821 
2822 #ifndef __ASSEMBLY__
2823 /*
2824  * WARNING: The C register and register group struct declarations are provided for
2825  * convenience and illustrative purposes. They should, however, be used with
2826  * caution as the C language standard provides no guarantees about the alignment or
2827  * atomicity of device memory accesses. The recommended practice for writing
2828  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2829  * alt_write_word() functions.
2830  *
2831  * The struct declaration for register ALT_UART_STHR.
2832  */
2833 struct ALT_UART_STHR_s
2834 {
2835  uint32_t sthr : 8; /* Shadow Transmit Buffer */
2836  uint32_t : 24; /* *UNDEFINED* */
2837 };
2838 
2839 /* The typedef declaration for register ALT_UART_STHR. */
2840 typedef volatile struct ALT_UART_STHR_s ALT_UART_STHR_t;
2841 #endif /* __ASSEMBLY__ */
2842 
2843 /* The byte offset of the ALT_UART_STHR register from the beginning of the component. */
2844 #define ALT_UART_STHR_OFST 0x34
2845 /* The address of the ALT_UART_STHR register. */
2846 #define ALT_UART_STHR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_STHR_OFST))
2847 
2848 /*
2849  * Register : FIFO Access Register - far
2850  *
2851  * This register is used in FIFO access testing.
2852  *
2853  * Register Layout
2854  *
2855  * Bits | Access | Reset | Description
2856  * :-------|:-------|:------|:----------------
2857  * [0] | RW | 0x0 | FIFO ACCESS Bit
2858  * [31:1] | ??? | 0x0 | *UNDEFINED*
2859  *
2860  */
2861 /*
2862  * Field : FIFO ACCESS Bit - srbr_sthr
2863  *
2864  * This register is used to enable a FIFO access mode for testing, so that the
2865  * receive FIFO can be written by the master and the transmit FIFO can be read by
2866  * the master when FIFO's are enabled. When FIFO's are not enabled it allows the
2867  * RBR to be written by the master and the THR to be read by the master
2868  *
2869  * Note: That when the FIFO access mode is enabled/disabled, the control portion of
2870  * the receive FIFO and transmit FIFO is reset and the FIFO's are treated as empty.
2871  *
2872  * Field Enumeration Values:
2873  *
2874  * Enum | Value | Description
2875  * :------------------------------|:------|:--------------------------
2876  * ALT_UART_FAR_SRBR_STHR_E_DISD | 0x0 | FIFO access mode disabled
2877  * ALT_UART_FAR_SRBR_STHR_E_END | 0x1 | FIFO access mode enabled
2878  *
2879  * Field Access Macros:
2880  *
2881  */
2882 /*
2883  * Enumerated value for register field ALT_UART_FAR_SRBR_STHR
2884  *
2885  * FIFO access mode disabled
2886  */
2887 #define ALT_UART_FAR_SRBR_STHR_E_DISD 0x0
2888 /*
2889  * Enumerated value for register field ALT_UART_FAR_SRBR_STHR
2890  *
2891  * FIFO access mode enabled
2892  */
2893 #define ALT_UART_FAR_SRBR_STHR_E_END 0x1
2894 
2895 /* The Least Significant Bit (LSB) position of the ALT_UART_FAR_SRBR_STHR register field. */
2896 #define ALT_UART_FAR_SRBR_STHR_LSB 0
2897 /* The Most Significant Bit (MSB) position of the ALT_UART_FAR_SRBR_STHR register field. */
2898 #define ALT_UART_FAR_SRBR_STHR_MSB 0
2899 /* The width in bits of the ALT_UART_FAR_SRBR_STHR register field. */
2900 #define ALT_UART_FAR_SRBR_STHR_WIDTH 1
2901 /* The mask used to set the ALT_UART_FAR_SRBR_STHR register field value. */
2902 #define ALT_UART_FAR_SRBR_STHR_SET_MSK 0x00000001
2903 /* The mask used to clear the ALT_UART_FAR_SRBR_STHR register field value. */
2904 #define ALT_UART_FAR_SRBR_STHR_CLR_MSK 0xfffffffe
2905 /* The reset value of the ALT_UART_FAR_SRBR_STHR register field. */
2906 #define ALT_UART_FAR_SRBR_STHR_RESET 0x0
2907 /* Extracts the ALT_UART_FAR_SRBR_STHR field value from a register. */
2908 #define ALT_UART_FAR_SRBR_STHR_GET(value) (((value) & 0x00000001) >> 0)
2909 /* Produces a ALT_UART_FAR_SRBR_STHR register field value suitable for setting the register. */
2910 #define ALT_UART_FAR_SRBR_STHR_SET(value) (((value) << 0) & 0x00000001)
2911 
2912 #ifndef __ASSEMBLY__
2913 /*
2914  * WARNING: The C register and register group struct declarations are provided for
2915  * convenience and illustrative purposes. They should, however, be used with
2916  * caution as the C language standard provides no guarantees about the alignment or
2917  * atomicity of device memory accesses. The recommended practice for writing
2918  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2919  * alt_write_word() functions.
2920  *
2921  * The struct declaration for register ALT_UART_FAR.
2922  */
2923 struct ALT_UART_FAR_s
2924 {
2925  uint32_t srbr_sthr : 1; /* FIFO ACCESS Bit */
2926  uint32_t : 31; /* *UNDEFINED* */
2927 };
2928 
2929 /* The typedef declaration for register ALT_UART_FAR. */
2930 typedef volatile struct ALT_UART_FAR_s ALT_UART_FAR_t;
2931 #endif /* __ASSEMBLY__ */
2932 
2933 /* The byte offset of the ALT_UART_FAR register from the beginning of the component. */
2934 #define ALT_UART_FAR_OFST 0x70
2935 /* The address of the ALT_UART_FAR register. */
2936 #define ALT_UART_FAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_FAR_OFST))
2937 
2938 /*
2939  * Register : Transmit FIFO Read Register - tfr
2940  *
2941  * Used in FIFO Access test mode.
2942  *
2943  * Register Layout
2944  *
2945  * Bits | Access | Reset | Description
2946  * :-------|:-------|:------|:-------------------
2947  * [7:0] | R | 0x0 | Transmit FIFO Read
2948  * [31:8] | ??? | 0x0 | *UNDEFINED*
2949  *
2950  */
2951 /*
2952  * Field : Transmit FIFO Read - tfr
2953  *
2954  * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to
2955  * one). When FIFO's are enabled, reading this register gives the data at the top
2956  * of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the
2957  * next data value that is currently at the top of the FIFO. When FIFO's are not
2958  * enabled, reading this register gives the data in the THR.
2959  *
2960  * Field Access Macros:
2961  *
2962  */
2963 /* The Least Significant Bit (LSB) position of the ALT_UART_TFR_TFR register field. */
2964 #define ALT_UART_TFR_TFR_LSB 0
2965 /* The Most Significant Bit (MSB) position of the ALT_UART_TFR_TFR register field. */
2966 #define ALT_UART_TFR_TFR_MSB 7
2967 /* The width in bits of the ALT_UART_TFR_TFR register field. */
2968 #define ALT_UART_TFR_TFR_WIDTH 8
2969 /* The mask used to set the ALT_UART_TFR_TFR register field value. */
2970 #define ALT_UART_TFR_TFR_SET_MSK 0x000000ff
2971 /* The mask used to clear the ALT_UART_TFR_TFR register field value. */
2972 #define ALT_UART_TFR_TFR_CLR_MSK 0xffffff00
2973 /* The reset value of the ALT_UART_TFR_TFR register field. */
2974 #define ALT_UART_TFR_TFR_RESET 0x0
2975 /* Extracts the ALT_UART_TFR_TFR field value from a register. */
2976 #define ALT_UART_TFR_TFR_GET(value) (((value) & 0x000000ff) >> 0)
2977 /* Produces a ALT_UART_TFR_TFR register field value suitable for setting the register. */
2978 #define ALT_UART_TFR_TFR_SET(value) (((value) << 0) & 0x000000ff)
2979 
2980 #ifndef __ASSEMBLY__
2981 /*
2982  * WARNING: The C register and register group struct declarations are provided for
2983  * convenience and illustrative purposes. They should, however, be used with
2984  * caution as the C language standard provides no guarantees about the alignment or
2985  * atomicity of device memory accesses. The recommended practice for writing
2986  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2987  * alt_write_word() functions.
2988  *
2989  * The struct declaration for register ALT_UART_TFR.
2990  */
2991 struct ALT_UART_TFR_s
2992 {
2993  const uint32_t tfr : 8; /* Transmit FIFO Read */
2994  uint32_t : 24; /* *UNDEFINED* */
2995 };
2996 
2997 /* The typedef declaration for register ALT_UART_TFR. */
2998 typedef volatile struct ALT_UART_TFR_s ALT_UART_TFR_t;
2999 #endif /* __ASSEMBLY__ */
3000 
3001 /* The byte offset of the ALT_UART_TFR register from the beginning of the component. */
3002 #define ALT_UART_TFR_OFST 0x74
3003 /* The address of the ALT_UART_TFR register. */
3004 #define ALT_UART_TFR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_TFR_OFST))
3005 
3006 /*
3007  * Register : Receive FIFO Write - RFW
3008  *
3009  * Used only with FIFO access test mode.
3010  *
3011  * Register Layout
3012  *
3013  * Bits | Access | Reset | Description
3014  * :--------|:-------|:------|:---------------------------
3015  * [7:0] | W | 0x0 | Receive FIFO Write Field
3016  * [8] | W | 0x0 | Receive FIFO Parity Error
3017  * [9] | W | 0x0 | Receive FIFO Framing Error
3018  * [31:10] | ??? | 0x0 | *UNDEFINED*
3019  *
3020  */
3021 /*
3022  * Field : Receive FIFO Write Field - rfwd
3023  *
3024  * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to
3025  * one). When FIFO's are enabled, the data that is written to the RFWD is pushed
3026  * into the receive FIFO. Each consecutive write pushes the new data to the next
3027  * write location in the receive FIFO. When FIFO's are not enabled, the data that
3028  * is written to the RFWD is pushed into the RBR.
3029  *
3030  * Field Access Macros:
3031  *
3032  */
3033 /* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFWD register field. */
3034 #define ALT_UART_RFW_RFWD_LSB 0
3035 /* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFWD register field. */
3036 #define ALT_UART_RFW_RFWD_MSB 7
3037 /* The width in bits of the ALT_UART_RFW_RFWD register field. */
3038 #define ALT_UART_RFW_RFWD_WIDTH 8
3039 /* The mask used to set the ALT_UART_RFW_RFWD register field value. */
3040 #define ALT_UART_RFW_RFWD_SET_MSK 0x000000ff
3041 /* The mask used to clear the ALT_UART_RFW_RFWD register field value. */
3042 #define ALT_UART_RFW_RFWD_CLR_MSK 0xffffff00
3043 /* The reset value of the ALT_UART_RFW_RFWD register field. */
3044 #define ALT_UART_RFW_RFWD_RESET 0x0
3045 /* Extracts the ALT_UART_RFW_RFWD field value from a register. */
3046 #define ALT_UART_RFW_RFWD_GET(value) (((value) & 0x000000ff) >> 0)
3047 /* Produces a ALT_UART_RFW_RFWD register field value suitable for setting the register. */
3048 #define ALT_UART_RFW_RFWD_SET(value) (((value) << 0) & 0x000000ff)
3049 
3050 /*
3051  * Field : Receive FIFO Parity Error - rfpe
3052  *
3053  * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to
3054  * one). When FIFO's are enabled, this bit is used to write parity error detection
3055  * information to the receive FIFO. When FIFO's are not enabled, this bit is used
3056  * to write parity error detection information to the RBR.
3057  *
3058  * Field Access Macros:
3059  *
3060  */
3061 /* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFPE register field. */
3062 #define ALT_UART_RFW_RFPE_LSB 8
3063 /* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFPE register field. */
3064 #define ALT_UART_RFW_RFPE_MSB 8
3065 /* The width in bits of the ALT_UART_RFW_RFPE register field. */
3066 #define ALT_UART_RFW_RFPE_WIDTH 1
3067 /* The mask used to set the ALT_UART_RFW_RFPE register field value. */
3068 #define ALT_UART_RFW_RFPE_SET_MSK 0x00000100
3069 /* The mask used to clear the ALT_UART_RFW_RFPE register field value. */
3070 #define ALT_UART_RFW_RFPE_CLR_MSK 0xfffffeff
3071 /* The reset value of the ALT_UART_RFW_RFPE register field. */
3072 #define ALT_UART_RFW_RFPE_RESET 0x0
3073 /* Extracts the ALT_UART_RFW_RFPE field value from a register. */
3074 #define ALT_UART_RFW_RFPE_GET(value) (((value) & 0x00000100) >> 8)
3075 /* Produces a ALT_UART_RFW_RFPE register field value suitable for setting the register. */
3076 #define ALT_UART_RFW_RFPE_SET(value) (((value) << 8) & 0x00000100)
3077 
3078 /*
3079  * Field : Receive FIFO Framing Error - RFFE
3080  *
3081  * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to
3082  * one). When FIFO's are enabled, this bit is used to write framing error detection
3083  * information to the receive FIFO. When FIFO's are not enabled, this bit is used
3084  * to write framing error detection information to the RBR.
3085  *
3086  * Field Access Macros:
3087  *
3088  */
3089 /* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFFE register field. */
3090 #define ALT_UART_RFW_RFFE_LSB 9
3091 /* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFFE register field. */
3092 #define ALT_UART_RFW_RFFE_MSB 9
3093 /* The width in bits of the ALT_UART_RFW_RFFE register field. */
3094 #define ALT_UART_RFW_RFFE_WIDTH 1
3095 /* The mask used to set the ALT_UART_RFW_RFFE register field value. */
3096 #define ALT_UART_RFW_RFFE_SET_MSK 0x00000200
3097 /* The mask used to clear the ALT_UART_RFW_RFFE register field value. */
3098 #define ALT_UART_RFW_RFFE_CLR_MSK 0xfffffdff
3099 /* The reset value of the ALT_UART_RFW_RFFE register field. */
3100 #define ALT_UART_RFW_RFFE_RESET 0x0
3101 /* Extracts the ALT_UART_RFW_RFFE field value from a register. */
3102 #define ALT_UART_RFW_RFFE_GET(value) (((value) & 0x00000200) >> 9)
3103 /* Produces a ALT_UART_RFW_RFFE register field value suitable for setting the register. */
3104 #define ALT_UART_RFW_RFFE_SET(value) (((value) << 9) & 0x00000200)
3105 
3106 #ifndef __ASSEMBLY__
3107 /*
3108  * WARNING: The C register and register group struct declarations are provided for
3109  * convenience and illustrative purposes. They should, however, be used with
3110  * caution as the C language standard provides no guarantees about the alignment or
3111  * atomicity of device memory accesses. The recommended practice for writing
3112  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3113  * alt_write_word() functions.
3114  *
3115  * The struct declaration for register ALT_UART_RFW.
3116  */
3117 struct ALT_UART_RFW_s
3118 {
3119  uint32_t rfwd : 8; /* Receive FIFO Write Field */
3120  uint32_t rfpe : 1; /* Receive FIFO Parity Error */
3121  uint32_t RFFE : 1; /* Receive FIFO Framing Error */
3122  uint32_t : 22; /* *UNDEFINED* */
3123 };
3124 
3125 /* The typedef declaration for register ALT_UART_RFW. */
3126 typedef volatile struct ALT_UART_RFW_s ALT_UART_RFW_t;
3127 #endif /* __ASSEMBLY__ */
3128 
3129 /* The byte offset of the ALT_UART_RFW register from the beginning of the component. */
3130 #define ALT_UART_RFW_OFST 0x78
3131 /* The address of the ALT_UART_RFW register. */
3132 #define ALT_UART_RFW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RFW_OFST))
3133 
3134 /*
3135  * Register : UART Status Register - usr
3136  *
3137  * Status of FIFO Operations.
3138  *
3139  * Register Layout
3140  *
3141  * Bits | Access | Reset | Description
3142  * :-------|:-------|:------|:-----------------------
3143  * [0] | ??? | 0x0 | *UNDEFINED*
3144  * [1] | R | 0x1 | Transmit FIFO Not Full
3145  * [2] | R | 0x1 | Transmit FIFO Empty
3146  * [3] | R | 0x0 | Receive FIFO Not Empty
3147  * [4] | R | 0x0 | Receive FIFO Full
3148  * [31:5] | ??? | 0x0 | *UNDEFINED*
3149  *
3150  */
3151 /*
3152  * Field : Transmit FIFO Not Full - tfnf
3153  *
3154  * This Bit is used to indicate that the transmit FIFO in not full. This bit is
3155  * cleared when the Tx FIFO is full.
3156  *
3157  * Field Enumeration Values:
3158  *
3159  * Enum | Value | Description
3160  * :----------------------------|:------|:--------------------------
3161  * ALT_UART_USR_TFNF_E_FULL | 0x0 | Transmit FIFO is full
3162  * ALT_UART_USR_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full
3163  *
3164  * Field Access Macros:
3165  *
3166  */
3167 /*
3168  * Enumerated value for register field ALT_UART_USR_TFNF
3169  *
3170  * Transmit FIFO is full
3171  */
3172 #define ALT_UART_USR_TFNF_E_FULL 0x0
3173 /*
3174  * Enumerated value for register field ALT_UART_USR_TFNF
3175  *
3176  * Transmit FIFO is not full
3177  */
3178 #define ALT_UART_USR_TFNF_E_NOTFULL 0x1
3179 
3180 /* The Least Significant Bit (LSB) position of the ALT_UART_USR_TFNF register field. */
3181 #define ALT_UART_USR_TFNF_LSB 1
3182 /* The Most Significant Bit (MSB) position of the ALT_UART_USR_TFNF register field. */
3183 #define ALT_UART_USR_TFNF_MSB 1
3184 /* The width in bits of the ALT_UART_USR_TFNF register field. */
3185 #define ALT_UART_USR_TFNF_WIDTH 1
3186 /* The mask used to set the ALT_UART_USR_TFNF register field value. */
3187 #define ALT_UART_USR_TFNF_SET_MSK 0x00000002
3188 /* The mask used to clear the ALT_UART_USR_TFNF register field value. */
3189 #define ALT_UART_USR_TFNF_CLR_MSK 0xfffffffd
3190 /* The reset value of the ALT_UART_USR_TFNF register field. */
3191 #define ALT_UART_USR_TFNF_RESET 0x1
3192 /* Extracts the ALT_UART_USR_TFNF field value from a register. */
3193 #define ALT_UART_USR_TFNF_GET(value) (((value) & 0x00000002) >> 1)
3194 /* Produces a ALT_UART_USR_TFNF register field value suitable for setting the register. */
3195 #define ALT_UART_USR_TFNF_SET(value) (((value) << 1) & 0x00000002)
3196 
3197 /*
3198  * Field : Transmit FIFO Empty - tfe
3199  *
3200  * This is used to indicate that the transmit FIFO is completely empty. This bit is
3201  * cleared when the Tx FIFO is no longer empty.
3202  *
3203  * Field Enumeration Values:
3204  *
3205  * Enum | Value | Description
3206  * :----------------------------|:------|:---------------------------
3207  * ALT_UART_USR_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty
3208  * ALT_UART_USR_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty
3209  *
3210  * Field Access Macros:
3211  *
3212  */
3213 /*
3214  * Enumerated value for register field ALT_UART_USR_TFE
3215  *
3216  * Transmit FIFO is not empty
3217  */
3218 #define ALT_UART_USR_TFE_E_NOTEMPTY 0x0
3219 /*
3220  * Enumerated value for register field ALT_UART_USR_TFE
3221  *
3222  * Transmit FIFO is empty
3223  */
3224 #define ALT_UART_USR_TFE_E_EMPTY 0x1
3225 
3226 /* The Least Significant Bit (LSB) position of the ALT_UART_USR_TFE register field. */
3227 #define ALT_UART_USR_TFE_LSB 2
3228 /* The Most Significant Bit (MSB) position of the ALT_UART_USR_TFE register field. */
3229 #define ALT_UART_USR_TFE_MSB 2
3230 /* The width in bits of the ALT_UART_USR_TFE register field. */
3231 #define ALT_UART_USR_TFE_WIDTH 1
3232 /* The mask used to set the ALT_UART_USR_TFE register field value. */
3233 #define ALT_UART_USR_TFE_SET_MSK 0x00000004
3234 /* The mask used to clear the ALT_UART_USR_TFE register field value. */
3235 #define ALT_UART_USR_TFE_CLR_MSK 0xfffffffb
3236 /* The reset value of the ALT_UART_USR_TFE register field. */
3237 #define ALT_UART_USR_TFE_RESET 0x1
3238 /* Extracts the ALT_UART_USR_TFE field value from a register. */
3239 #define ALT_UART_USR_TFE_GET(value) (((value) & 0x00000004) >> 2)
3240 /* Produces a ALT_UART_USR_TFE register field value suitable for setting the register. */
3241 #define ALT_UART_USR_TFE_SET(value) (((value) << 2) & 0x00000004)
3242 
3243 /*
3244  * Field : Receive FIFO Not Empty - rfne
3245  *
3246  * This Bit is used to indicate that the receive FIFO contains one or more entries.
3247  * This bit is cleared when the Rx FIFO is empty.
3248  *
3249  * Field Enumeration Values:
3250  *
3251  * Enum | Value | Description
3252  * :-----------------------------|:------|:--------------------------
3253  * ALT_UART_USR_RFNE_E_EMPTY | 0x0 | Receiive FIFO is empty
3254  * ALT_UART_USR_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty
3255  *
3256  * Field Access Macros:
3257  *
3258  */
3259 /*
3260  * Enumerated value for register field ALT_UART_USR_RFNE
3261  *
3262  * Receiive FIFO is empty
3263  */
3264 #define ALT_UART_USR_RFNE_E_EMPTY 0x0
3265 /*
3266  * Enumerated value for register field ALT_UART_USR_RFNE
3267  *
3268  * Receive FIFO is not empty
3269  */
3270 #define ALT_UART_USR_RFNE_E_NOTEMPTY 0x1
3271 
3272 /* The Least Significant Bit (LSB) position of the ALT_UART_USR_RFNE register field. */
3273 #define ALT_UART_USR_RFNE_LSB 3
3274 /* The Most Significant Bit (MSB) position of the ALT_UART_USR_RFNE register field. */
3275 #define ALT_UART_USR_RFNE_MSB 3
3276 /* The width in bits of the ALT_UART_USR_RFNE register field. */
3277 #define ALT_UART_USR_RFNE_WIDTH 1
3278 /* The mask used to set the ALT_UART_USR_RFNE register field value. */
3279 #define ALT_UART_USR_RFNE_SET_MSK 0x00000008
3280 /* The mask used to clear the ALT_UART_USR_RFNE register field value. */
3281 #define ALT_UART_USR_RFNE_CLR_MSK 0xfffffff7
3282 /* The reset value of the ALT_UART_USR_RFNE register field. */
3283 #define ALT_UART_USR_RFNE_RESET 0x0
3284 /* Extracts the ALT_UART_USR_RFNE field value from a register. */
3285 #define ALT_UART_USR_RFNE_GET(value) (((value) & 0x00000008) >> 3)
3286 /* Produces a ALT_UART_USR_RFNE register field value suitable for setting the register. */
3287 #define ALT_UART_USR_RFNE_SET(value) (((value) << 3) & 0x00000008)
3288 
3289 /*
3290  * Field : Receive FIFO Full - rff
3291  *
3292  * This Bit is used to indicate that the receive FIFO is completely full. This bit
3293  * is cleared when the Rx FIFO is no longer full.
3294  *
3295  * Field Enumeration Values:
3296  *
3297  * Enum | Value | Description
3298  * :---------------------------|:------|:-----------------------
3299  * ALT_UART_USR_RFF_E_NOTFULL | 0x0 | Receiive FIFO not full
3300  * ALT_UART_USR_RFF_E_FULL | 0x1 | Transmit FIFO is full
3301  *
3302  * Field Access Macros:
3303  *
3304  */
3305 /*
3306  * Enumerated value for register field ALT_UART_USR_RFF
3307  *
3308  * Receiive FIFO not full
3309  */
3310 #define ALT_UART_USR_RFF_E_NOTFULL 0x0
3311 /*
3312  * Enumerated value for register field ALT_UART_USR_RFF
3313  *
3314  * Transmit FIFO is full
3315  */
3316 #define ALT_UART_USR_RFF_E_FULL 0x1
3317 
3318 /* The Least Significant Bit (LSB) position of the ALT_UART_USR_RFF register field. */
3319 #define ALT_UART_USR_RFF_LSB 4
3320 /* The Most Significant Bit (MSB) position of the ALT_UART_USR_RFF register field. */
3321 #define ALT_UART_USR_RFF_MSB 4
3322 /* The width in bits of the ALT_UART_USR_RFF register field. */
3323 #define ALT_UART_USR_RFF_WIDTH 1
3324 /* The mask used to set the ALT_UART_USR_RFF register field value. */
3325 #define ALT_UART_USR_RFF_SET_MSK 0x00000010
3326 /* The mask used to clear the ALT_UART_USR_RFF register field value. */
3327 #define ALT_UART_USR_RFF_CLR_MSK 0xffffffef
3328 /* The reset value of the ALT_UART_USR_RFF register field. */
3329 #define ALT_UART_USR_RFF_RESET 0x0
3330 /* Extracts the ALT_UART_USR_RFF field value from a register. */
3331 #define ALT_UART_USR_RFF_GET(value) (((value) & 0x00000010) >> 4)
3332 /* Produces a ALT_UART_USR_RFF register field value suitable for setting the register. */
3333 #define ALT_UART_USR_RFF_SET(value) (((value) << 4) & 0x00000010)
3334 
3335 #ifndef __ASSEMBLY__
3336 /*
3337  * WARNING: The C register and register group struct declarations are provided for
3338  * convenience and illustrative purposes. They should, however, be used with
3339  * caution as the C language standard provides no guarantees about the alignment or
3340  * atomicity of device memory accesses. The recommended practice for writing
3341  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3342  * alt_write_word() functions.
3343  *
3344  * The struct declaration for register ALT_UART_USR.
3345  */
3346 struct ALT_UART_USR_s
3347 {
3348  uint32_t : 1; /* *UNDEFINED* */
3349  const uint32_t tfnf : 1; /* Transmit FIFO Not Full */
3350  const uint32_t tfe : 1; /* Transmit FIFO Empty */
3351  const uint32_t rfne : 1; /* Receive FIFO Not Empty */
3352  const uint32_t rff : 1; /* Receive FIFO Full */
3353  uint32_t : 27; /* *UNDEFINED* */
3354 };
3355 
3356 /* The typedef declaration for register ALT_UART_USR. */
3357 typedef volatile struct ALT_UART_USR_s ALT_UART_USR_t;
3358 #endif /* __ASSEMBLY__ */
3359 
3360 /* The byte offset of the ALT_UART_USR register from the beginning of the component. */
3361 #define ALT_UART_USR_OFST 0x7c
3362 /* The address of the ALT_UART_USR register. */
3363 #define ALT_UART_USR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_USR_OFST))
3364 
3365 /*
3366  * Register : Transmit FIFO Level - tfl
3367  *
3368  * This register is used to specify the number of data entries in the Tx FIFO.
3369  * Status Bits in USR register monitor the FIFO state.
3370  *
3371  * Register Layout
3372  *
3373  * Bits | Access | Reset | Description
3374  * :-------|:-------|:------|:--------------------
3375  * [4:0] | R | 0x0 | Transmit FIFO Level
3376  * [31:5] | ??? | 0x0 | *UNDEFINED*
3377  *
3378  */
3379 /*
3380  * Field : Transmit FIFO Level - tfl
3381  *
3382  * This indicates the number of data entries in the transmit FIFO.
3383  *
3384  * Field Access Macros:
3385  *
3386  */
3387 /* The Least Significant Bit (LSB) position of the ALT_UART_TFL_TFL register field. */
3388 #define ALT_UART_TFL_TFL_LSB 0
3389 /* The Most Significant Bit (MSB) position of the ALT_UART_TFL_TFL register field. */
3390 #define ALT_UART_TFL_TFL_MSB 4
3391 /* The width in bits of the ALT_UART_TFL_TFL register field. */
3392 #define ALT_UART_TFL_TFL_WIDTH 5
3393 /* The mask used to set the ALT_UART_TFL_TFL register field value. */
3394 #define ALT_UART_TFL_TFL_SET_MSK 0x0000001f
3395 /* The mask used to clear the ALT_UART_TFL_TFL register field value. */
3396 #define ALT_UART_TFL_TFL_CLR_MSK 0xffffffe0
3397 /* The reset value of the ALT_UART_TFL_TFL register field. */
3398 #define ALT_UART_TFL_TFL_RESET 0x0
3399 /* Extracts the ALT_UART_TFL_TFL field value from a register. */
3400 #define ALT_UART_TFL_TFL_GET(value) (((value) & 0x0000001f) >> 0)
3401 /* Produces a ALT_UART_TFL_TFL register field value suitable for setting the register. */
3402 #define ALT_UART_TFL_TFL_SET(value) (((value) << 0) & 0x0000001f)
3403 
3404 #ifndef __ASSEMBLY__
3405 /*
3406  * WARNING: The C register and register group struct declarations are provided for
3407  * convenience and illustrative purposes. They should, however, be used with
3408  * caution as the C language standard provides no guarantees about the alignment or
3409  * atomicity of device memory accesses. The recommended practice for writing
3410  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3411  * alt_write_word() functions.
3412  *
3413  * The struct declaration for register ALT_UART_TFL.
3414  */
3415 struct ALT_UART_TFL_s
3416 {
3417  const uint32_t tfl : 5; /* Transmit FIFO Level */
3418  uint32_t : 27; /* *UNDEFINED* */
3419 };
3420 
3421 /* The typedef declaration for register ALT_UART_TFL. */
3422 typedef volatile struct ALT_UART_TFL_s ALT_UART_TFL_t;
3423 #endif /* __ASSEMBLY__ */
3424 
3425 /* The byte offset of the ALT_UART_TFL register from the beginning of the component. */
3426 #define ALT_UART_TFL_OFST 0x80
3427 /* The address of the ALT_UART_TFL register. */
3428 #define ALT_UART_TFL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_TFL_OFST))
3429 
3430 /*
3431  * Register : Receive FIFO Level Write - rfl
3432  *
3433  * This register is used to specify the number of data entries in the Tx FIFO.
3434  * Status Bits in USR register monitor the FIFO state.
3435  *
3436  * Register Layout
3437  *
3438  * Bits | Access | Reset | Description
3439  * :-------|:-------|:------|:--------------------------
3440  * [4:0] | R | 0x0 | Receive FIFO Level Status
3441  * [31:5] | ??? | 0x0 | *UNDEFINED*
3442  *
3443  */
3444 /*
3445  * Field : Receive FIFO Level Status - rfl
3446  *
3447  * This indicates the number of data entries in the receive FIFO.
3448  *
3449  * Field Access Macros:
3450  *
3451  */
3452 /* The Least Significant Bit (LSB) position of the ALT_UART_RFL_RFL register field. */
3453 #define ALT_UART_RFL_RFL_LSB 0
3454 /* The Most Significant Bit (MSB) position of the ALT_UART_RFL_RFL register field. */
3455 #define ALT_UART_RFL_RFL_MSB 4
3456 /* The width in bits of the ALT_UART_RFL_RFL register field. */
3457 #define ALT_UART_RFL_RFL_WIDTH 5
3458 /* The mask used to set the ALT_UART_RFL_RFL register field value. */
3459 #define ALT_UART_RFL_RFL_SET_MSK 0x0000001f
3460 /* The mask used to clear the ALT_UART_RFL_RFL register field value. */
3461 #define ALT_UART_RFL_RFL_CLR_MSK 0xffffffe0
3462 /* The reset value of the ALT_UART_RFL_RFL register field. */
3463 #define ALT_UART_RFL_RFL_RESET 0x0
3464 /* Extracts the ALT_UART_RFL_RFL field value from a register. */
3465 #define ALT_UART_RFL_RFL_GET(value) (((value) & 0x0000001f) >> 0)
3466 /* Produces a ALT_UART_RFL_RFL register field value suitable for setting the register. */
3467 #define ALT_UART_RFL_RFL_SET(value) (((value) << 0) & 0x0000001f)
3468 
3469 #ifndef __ASSEMBLY__
3470 /*
3471  * WARNING: The C register and register group struct declarations are provided for
3472  * convenience and illustrative purposes. They should, however, be used with
3473  * caution as the C language standard provides no guarantees about the alignment or
3474  * atomicity of device memory accesses. The recommended practice for writing
3475  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3476  * alt_write_word() functions.
3477  *
3478  * The struct declaration for register ALT_UART_RFL.
3479  */
3480 struct ALT_UART_RFL_s
3481 {
3482  const uint32_t rfl : 5; /* Receive FIFO Level Status */
3483  uint32_t : 27; /* *UNDEFINED* */
3484 };
3485 
3486 /* The typedef declaration for register ALT_UART_RFL. */
3487 typedef volatile struct ALT_UART_RFL_s ALT_UART_RFL_t;
3488 #endif /* __ASSEMBLY__ */
3489 
3490 /* The byte offset of the ALT_UART_RFL register from the beginning of the component. */
3491 #define ALT_UART_RFL_OFST 0x84
3492 /* The address of the ALT_UART_RFL register. */
3493 #define ALT_UART_RFL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RFL_OFST))
3494 
3495 /*
3496  * Register : Software Reset Register - srr
3497  *
3498  * Provides Software Resets for Tx/Rx FIFO's and the uart.
3499  *
3500  * Register Layout
3501  *
3502  * Bits | Access | Reset | Description
3503  * :-------|:-------|:------|:--------------
3504  * [0] | W | 0x0 | UART Reset
3505  * [1] | W | 0x0 | Rx FIFO Reset
3506  * [2] | W | 0x0 | Tx FIFO Reset
3507  * [31:3] | ??? | 0x0 | *UNDEFINED*
3508  *
3509  */
3510 /*
3511  * Field : UART Reset - ur
3512  *
3513  * This asynchronously resets the UART and synchronously removes the reset
3514  * assertion.
3515  *
3516  * Field Enumeration Values:
3517  *
3518  * Enum | Value | Description
3519  * :------------------------|:------|:--------------
3520  * ALT_UART_SRR_UR_E_NORST | 0x0 | No reset Uart
3521  * ALT_UART_SRR_UR_E_RST | 0x1 | Reset Uart
3522  *
3523  * Field Access Macros:
3524  *
3525  */
3526 /*
3527  * Enumerated value for register field ALT_UART_SRR_UR
3528  *
3529  * No reset Uart
3530  */
3531 #define ALT_UART_SRR_UR_E_NORST 0x0
3532 /*
3533  * Enumerated value for register field ALT_UART_SRR_UR
3534  *
3535  * Reset Uart
3536  */
3537 #define ALT_UART_SRR_UR_E_RST 0x1
3538 
3539 /* The Least Significant Bit (LSB) position of the ALT_UART_SRR_UR register field. */
3540 #define ALT_UART_SRR_UR_LSB 0
3541 /* The Most Significant Bit (MSB) position of the ALT_UART_SRR_UR register field. */
3542 #define ALT_UART_SRR_UR_MSB 0
3543 /* The width in bits of the ALT_UART_SRR_UR register field. */
3544 #define ALT_UART_SRR_UR_WIDTH 1
3545 /* The mask used to set the ALT_UART_SRR_UR register field value. */
3546 #define ALT_UART_SRR_UR_SET_MSK 0x00000001
3547 /* The mask used to clear the ALT_UART_SRR_UR register field value. */
3548 #define ALT_UART_SRR_UR_CLR_MSK 0xfffffffe
3549 /* The reset value of the ALT_UART_SRR_UR register field. */
3550 #define ALT_UART_SRR_UR_RESET 0x0
3551 /* Extracts the ALT_UART_SRR_UR field value from a register. */
3552 #define ALT_UART_SRR_UR_GET(value) (((value) & 0x00000001) >> 0)
3553 /* Produces a ALT_UART_SRR_UR register field value suitable for setting the register. */
3554 #define ALT_UART_SRR_UR_SET(value) (((value) << 0) & 0x00000001)
3555 
3556 /*
3557  * Field : Rx FIFO Reset - rfr
3558  *
3559  * This is a shadow register for the Rx FIFO Reset bit (FCR[1]). This can be used
3560  * to remove the burden on software having to store previously written FCR values
3561  * (which are pretty static) just to reset the receive FIFO. This resets the
3562  * control portion of the receive FIFO and treats the FIFO as empty. This will also
3563  * de-assert the DMA Rx request and single signals. Note that this bit is 'self-
3564  * clearing' and it is not necessary to clear this bit.
3565  *
3566  * Field Enumeration Values:
3567  *
3568  * Enum | Value | Description
3569  * :-------------------------|:------|:-----------------
3570  * ALT_UART_SRR_RFR_E_NORST | 0x0 | No reset Rx FIFO
3571  * ALT_UART_SRR_RFR_E_RST | 0x1 | Reset Rx FIFO
3572  *
3573  * Field Access Macros:
3574  *
3575  */
3576 /*
3577  * Enumerated value for register field ALT_UART_SRR_RFR
3578  *
3579  * No reset Rx FIFO
3580  */
3581 #define ALT_UART_SRR_RFR_E_NORST 0x0
3582 /*
3583  * Enumerated value for register field ALT_UART_SRR_RFR
3584  *
3585  * Reset Rx FIFO
3586  */
3587 #define ALT_UART_SRR_RFR_E_RST 0x1
3588 
3589 /* The Least Significant Bit (LSB) position of the ALT_UART_SRR_RFR register field. */
3590 #define ALT_UART_SRR_RFR_LSB 1
3591 /* The Most Significant Bit (MSB) position of the ALT_UART_SRR_RFR register field. */
3592 #define ALT_UART_SRR_RFR_MSB 1
3593 /* The width in bits of the ALT_UART_SRR_RFR register field. */
3594 #define ALT_UART_SRR_RFR_WIDTH 1
3595 /* The mask used to set the ALT_UART_SRR_RFR register field value. */
3596 #define ALT_UART_SRR_RFR_SET_MSK 0x00000002
3597 /* The mask used to clear the ALT_UART_SRR_RFR register field value. */
3598 #define ALT_UART_SRR_RFR_CLR_MSK 0xfffffffd
3599 /* The reset value of the ALT_UART_SRR_RFR register field. */
3600 #define ALT_UART_SRR_RFR_RESET 0x0
3601 /* Extracts the ALT_UART_SRR_RFR field value from a register. */
3602 #define ALT_UART_SRR_RFR_GET(value) (((value) & 0x00000002) >> 1)
3603 /* Produces a ALT_UART_SRR_RFR register field value suitable for setting the register. */
3604 #define ALT_UART_SRR_RFR_SET(value) (((value) << 1) & 0x00000002)
3605 
3606 /*
3607  * Field : Tx FIFO Reset - xfr
3608  *
3609  * This is a shadow register forthe Tx FIFO Reset bit (FCR[2]). This can be used
3610  * to remove the burden on software having to store previously written FCR values
3611  * (which are pretty static) just to reset the transmit FIFO.This resets the
3612  * control portion of the transmit FIFO and treats the FIFO as empty. This will
3613  * also de-assert the DMA Tx request and single signals.
3614  *
3615  * Field Enumeration Values:
3616  *
3617  * Enum | Value | Description
3618  * :-------------------------|:------|:-----------------
3619  * ALT_UART_SRR_XFR_E_NORST | 0x0 | No reset Tx FIFO
3620  * ALT_UART_SRR_XFR_E_RST | 0x1 | Reset Tx FIFO
3621  *
3622  * Field Access Macros:
3623  *
3624  */
3625 /*
3626  * Enumerated value for register field ALT_UART_SRR_XFR
3627  *
3628  * No reset Tx FIFO
3629  */
3630 #define ALT_UART_SRR_XFR_E_NORST 0x0
3631 /*
3632  * Enumerated value for register field ALT_UART_SRR_XFR
3633  *
3634  * Reset Tx FIFO
3635  */
3636 #define ALT_UART_SRR_XFR_E_RST 0x1
3637 
3638 /* The Least Significant Bit (LSB) position of the ALT_UART_SRR_XFR register field. */
3639 #define ALT_UART_SRR_XFR_LSB 2
3640 /* The Most Significant Bit (MSB) position of the ALT_UART_SRR_XFR register field. */
3641 #define ALT_UART_SRR_XFR_MSB 2
3642 /* The width in bits of the ALT_UART_SRR_XFR register field. */
3643 #define ALT_UART_SRR_XFR_WIDTH 1
3644 /* The mask used to set the ALT_UART_SRR_XFR register field value. */
3645 #define ALT_UART_SRR_XFR_SET_MSK 0x00000004
3646 /* The mask used to clear the ALT_UART_SRR_XFR register field value. */
3647 #define ALT_UART_SRR_XFR_CLR_MSK 0xfffffffb
3648 /* The reset value of the ALT_UART_SRR_XFR register field. */
3649 #define ALT_UART_SRR_XFR_RESET 0x0
3650 /* Extracts the ALT_UART_SRR_XFR field value from a register. */
3651 #define ALT_UART_SRR_XFR_GET(value) (((value) & 0x00000004) >> 2)
3652 /* Produces a ALT_UART_SRR_XFR register field value suitable for setting the register. */
3653 #define ALT_UART_SRR_XFR_SET(value) (((value) << 2) & 0x00000004)
3654 
3655 #ifndef __ASSEMBLY__
3656 /*
3657  * WARNING: The C register and register group struct declarations are provided for
3658  * convenience and illustrative purposes. They should, however, be used with
3659  * caution as the C language standard provides no guarantees about the alignment or
3660  * atomicity of device memory accesses. The recommended practice for writing
3661  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3662  * alt_write_word() functions.
3663  *
3664  * The struct declaration for register ALT_UART_SRR.
3665  */
3666 struct ALT_UART_SRR_s
3667 {
3668  uint32_t ur : 1; /* UART Reset */
3669  uint32_t rfr : 1; /* Rx FIFO Reset */
3670  uint32_t xfr : 1; /* Tx FIFO Reset */
3671  uint32_t : 29; /* *UNDEFINED* */
3672 };
3673 
3674 /* The typedef declaration for register ALT_UART_SRR. */
3675 typedef volatile struct ALT_UART_SRR_s ALT_UART_SRR_t;
3676 #endif /* __ASSEMBLY__ */
3677 
3678 /* The byte offset of the ALT_UART_SRR register from the beginning of the component. */
3679 #define ALT_UART_SRR_OFST 0x88
3680 /* The address of the ALT_UART_SRR register. */
3681 #define ALT_UART_SRR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRR_OFST))
3682 
3683 /*
3684  * Register : Shadow Request to Send - srts
3685  *
3686  * This is a shadow register for the RTS status (MCR[1]), this can be used to
3687  * remove the burden of having to performing a read modify write on the MCR.
3688  *
3689  * Register Layout
3690  *
3691  * Bits | Access | Reset | Description
3692  * :-------|:-------|:------|:-----------------------
3693  * [0] | RW | 0x0 | Shadow Request to Send
3694  * [31:1] | ??? | 0x0 | *UNDEFINED*
3695  *
3696  */
3697 /*
3698  * Field : Shadow Request to Send - srts
3699  *
3700  * This is used to directly control the Request to Send (uart_rts_n) output. The
3701  * Request to Send (uart_rts_n) output is used to inform the modem or data set that
3702  * the UART is read to exchange data. The uart_rts_n signal is set low by
3703  * programming MCR[1] (RTS) to a high. In Auto Flow Control, (MCR[5] set to one)
3704  * and FIFO's are enabled (FCR[0] set to one), the uart_rts_n output is controlled
3705  * in the same way, but is also gated with the receiver FIFO threshold trigger
3706  * (uart_rts_n is inactive high when above the threshold).
3707  *
3708  * Note that in Loopback mode (MCR[4] set to one), the uart_rts_n output is held
3709  * inactive high while the value of this location is internally looped back to an
3710  * input.
3711  *
3712  * Field Enumeration Values:
3713  *
3714  * Enum | Value | Description
3715  * :----------------------------|:------|:------------------
3716  * ALT_UART_SRTS_SRTS_E_LOGIC0 | 0x1 | uart_rts_n logic0
3717  * ALT_UART_SRTS_SRTS_E_LOGIC1 | 0x0 | uart_rts_n logic1
3718  *
3719  * Field Access Macros:
3720  *
3721  */
3722 /*
3723  * Enumerated value for register field ALT_UART_SRTS_SRTS
3724  *
3725  * uart_rts_n logic0
3726  */
3727 #define ALT_UART_SRTS_SRTS_E_LOGIC0 0x1
3728 /*
3729  * Enumerated value for register field ALT_UART_SRTS_SRTS
3730  *
3731  * uart_rts_n logic1
3732  */
3733 #define ALT_UART_SRTS_SRTS_E_LOGIC1 0x0
3734 
3735 /* The Least Significant Bit (LSB) position of the ALT_UART_SRTS_SRTS register field. */
3736 #define ALT_UART_SRTS_SRTS_LSB 0
3737 /* The Most Significant Bit (MSB) position of the ALT_UART_SRTS_SRTS register field. */
3738 #define ALT_UART_SRTS_SRTS_MSB 0
3739 /* The width in bits of the ALT_UART_SRTS_SRTS register field. */
3740 #define ALT_UART_SRTS_SRTS_WIDTH 1
3741 /* The mask used to set the ALT_UART_SRTS_SRTS register field value. */
3742 #define ALT_UART_SRTS_SRTS_SET_MSK 0x00000001
3743 /* The mask used to clear the ALT_UART_SRTS_SRTS register field value. */
3744 #define ALT_UART_SRTS_SRTS_CLR_MSK 0xfffffffe
3745 /* The reset value of the ALT_UART_SRTS_SRTS register field. */
3746 #define ALT_UART_SRTS_SRTS_RESET 0x0
3747 /* Extracts the ALT_UART_SRTS_SRTS field value from a register. */
3748 #define ALT_UART_SRTS_SRTS_GET(value) (((value) & 0x00000001) >> 0)
3749 /* Produces a ALT_UART_SRTS_SRTS register field value suitable for setting the register. */
3750 #define ALT_UART_SRTS_SRTS_SET(value) (((value) << 0) & 0x00000001)
3751 
3752 #ifndef __ASSEMBLY__
3753 /*
3754  * WARNING: The C register and register group struct declarations are provided for
3755  * convenience and illustrative purposes. They should, however, be used with
3756  * caution as the C language standard provides no guarantees about the alignment or
3757  * atomicity of device memory accesses. The recommended practice for writing
3758  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3759  * alt_write_word() functions.
3760  *
3761  * The struct declaration for register ALT_UART_SRTS.
3762  */
3763 struct ALT_UART_SRTS_s
3764 {
3765  uint32_t srts : 1; /* Shadow Request to Send */
3766  uint32_t : 31; /* *UNDEFINED* */
3767 };
3768 
3769 /* The typedef declaration for register ALT_UART_SRTS. */
3770 typedef volatile struct ALT_UART_SRTS_s ALT_UART_SRTS_t;
3771 #endif /* __ASSEMBLY__ */
3772 
3773 /* The byte offset of the ALT_UART_SRTS register from the beginning of the component. */
3774 #define ALT_UART_SRTS_OFST 0x8c
3775 /* The address of the ALT_UART_SRTS register. */
3776 #define ALT_UART_SRTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRTS_OFST))
3777 
3778 /*
3779  * Register : Shadow Break Control Register - sbcr
3780  *
3781  * This is a shadow register for the Break bit [6] of the register LCR. This can be
3782  * used to remove the burden of having to performing a read modify write on the
3783  * LCR.
3784  *
3785  * Register Layout
3786  *
3787  * Bits | Access | Reset | Description
3788  * :-------|:-------|:------|:---------------------
3789  * [0] | RW | 0x0 | Shadow Break Control
3790  * [31:1] | ??? | 0x0 | *UNDEFINED*
3791  *
3792  */
3793 /*
3794  * Field : Shadow Break Control - sbcr
3795  *
3796  * This is used to cause a break condition to be transmitted to the receiving
3797  * device. If set to one the serial output is forced to the spacing (logic 0)
3798  * state. When not in Loopback Mode, as determined by MCR[4], the uart_txd line is
3799  * forced low until the Break bit is cleared. When in Loopback Mode, the break
3800  * condition is internally looped back to the receiver.
3801  *
3802  * Field Enumeration Values:
3803  *
3804  * Enum | Value | Description
3805  * :--------------------------|:------|:----------------------------
3806  * ALT_UART_SBCR_SBCR_E_DISD | 0x0 | no break
3807  * ALT_UART_SBCR_SBCR_E_END | 0x1 | break serial output spacing
3808  *
3809  * Field Access Macros:
3810  *
3811  */
3812 /*
3813  * Enumerated value for register field ALT_UART_SBCR_SBCR
3814  *
3815  * no break
3816  */
3817 #define ALT_UART_SBCR_SBCR_E_DISD 0x0
3818 /*
3819  * Enumerated value for register field ALT_UART_SBCR_SBCR
3820  *
3821  * break serial output spacing
3822  */
3823 #define ALT_UART_SBCR_SBCR_E_END 0x1
3824 
3825 /* The Least Significant Bit (LSB) position of the ALT_UART_SBCR_SBCR register field. */
3826 #define ALT_UART_SBCR_SBCR_LSB 0
3827 /* The Most Significant Bit (MSB) position of the ALT_UART_SBCR_SBCR register field. */
3828 #define ALT_UART_SBCR_SBCR_MSB 0
3829 /* The width in bits of the ALT_UART_SBCR_SBCR register field. */
3830 #define ALT_UART_SBCR_SBCR_WIDTH 1
3831 /* The mask used to set the ALT_UART_SBCR_SBCR register field value. */
3832 #define ALT_UART_SBCR_SBCR_SET_MSK 0x00000001
3833 /* The mask used to clear the ALT_UART_SBCR_SBCR register field value. */
3834 #define ALT_UART_SBCR_SBCR_CLR_MSK 0xfffffffe
3835 /* The reset value of the ALT_UART_SBCR_SBCR register field. */
3836 #define ALT_UART_SBCR_SBCR_RESET 0x0
3837 /* Extracts the ALT_UART_SBCR_SBCR field value from a register. */
3838 #define ALT_UART_SBCR_SBCR_GET(value) (((value) & 0x00000001) >> 0)
3839 /* Produces a ALT_UART_SBCR_SBCR register field value suitable for setting the register. */
3840 #define ALT_UART_SBCR_SBCR_SET(value) (((value) << 0) & 0x00000001)
3841 
3842 #ifndef __ASSEMBLY__
3843 /*
3844  * WARNING: The C register and register group struct declarations are provided for
3845  * convenience and illustrative purposes. They should, however, be used with
3846  * caution as the C language standard provides no guarantees about the alignment or
3847  * atomicity of device memory accesses. The recommended practice for writing
3848  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3849  * alt_write_word() functions.
3850  *
3851  * The struct declaration for register ALT_UART_SBCR.
3852  */
3853 struct ALT_UART_SBCR_s
3854 {
3855  uint32_t sbcr : 1; /* Shadow Break Control */
3856  uint32_t : 31; /* *UNDEFINED* */
3857 };
3858 
3859 /* The typedef declaration for register ALT_UART_SBCR. */
3860 typedef volatile struct ALT_UART_SBCR_s ALT_UART_SBCR_t;
3861 #endif /* __ASSEMBLY__ */
3862 
3863 /* The byte offset of the ALT_UART_SBCR register from the beginning of the component. */
3864 #define ALT_UART_SBCR_OFST 0x90
3865 /* The address of the ALT_UART_SBCR register. */
3866 #define ALT_UART_SBCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SBCR_OFST))
3867 
3868 /*
3869  * Register : Shadow DMA Mode - sdmam
3870  *
3871  * This is a shadow register for the DMA mode bit (FCR[3]).
3872  *
3873  * Register Layout
3874  *
3875  * Bits | Access | Reset | Description
3876  * :-------|:-------|:------|:----------------
3877  * [0] | RW | 0x0 | Shadow DMA Mode
3878  * [31:1] | ??? | 0x0 | *UNDEFINED*
3879  *
3880  */
3881 /*
3882  * Field : Shadow DMA Mode - sdmam
3883  *
3884  * This can be used to remove the burden of having to store the previously written
3885  * value to the FCR in memory and having to mask this value so that only the DMA
3886  * Mode bit gets updated.
3887  *
3888  * Field Enumeration Values:
3889  *
3890  * Enum | Value | Description
3891  * :------------------------------|:------|:---------------------------
3892  * ALT_UART_SDMAM_SDMAM_E_SINGLE | 0x0 | Single DMA Transfer Mode
3893  * ALT_UART_SDMAM_SDMAM_E_MULT | 0x1 | Multiple DMA Transfer Mode
3894  *
3895  * Field Access Macros:
3896  *
3897  */
3898 /*
3899  * Enumerated value for register field ALT_UART_SDMAM_SDMAM
3900  *
3901  * Single DMA Transfer Mode
3902  */
3903 #define ALT_UART_SDMAM_SDMAM_E_SINGLE 0x0
3904 /*
3905  * Enumerated value for register field ALT_UART_SDMAM_SDMAM
3906  *
3907  * Multiple DMA Transfer Mode
3908  */
3909 #define ALT_UART_SDMAM_SDMAM_E_MULT 0x1
3910 
3911 /* The Least Significant Bit (LSB) position of the ALT_UART_SDMAM_SDMAM register field. */
3912 #define ALT_UART_SDMAM_SDMAM_LSB 0
3913 /* The Most Significant Bit (MSB) position of the ALT_UART_SDMAM_SDMAM register field. */
3914 #define ALT_UART_SDMAM_SDMAM_MSB 0
3915 /* The width in bits of the ALT_UART_SDMAM_SDMAM register field. */
3916 #define ALT_UART_SDMAM_SDMAM_WIDTH 1
3917 /* The mask used to set the ALT_UART_SDMAM_SDMAM register field value. */
3918 #define ALT_UART_SDMAM_SDMAM_SET_MSK 0x00000001
3919 /* The mask used to clear the ALT_UART_SDMAM_SDMAM register field value. */
3920 #define ALT_UART_SDMAM_SDMAM_CLR_MSK 0xfffffffe
3921 /* The reset value of the ALT_UART_SDMAM_SDMAM register field. */
3922 #define ALT_UART_SDMAM_SDMAM_RESET 0x0
3923 /* Extracts the ALT_UART_SDMAM_SDMAM field value from a register. */
3924 #define ALT_UART_SDMAM_SDMAM_GET(value) (((value) & 0x00000001) >> 0)
3925 /* Produces a ALT_UART_SDMAM_SDMAM register field value suitable for setting the register. */
3926 #define ALT_UART_SDMAM_SDMAM_SET(value) (((value) << 0) & 0x00000001)
3927 
3928 #ifndef __ASSEMBLY__
3929 /*
3930  * WARNING: The C register and register group struct declarations are provided for
3931  * convenience and illustrative purposes. They should, however, be used with
3932  * caution as the C language standard provides no guarantees about the alignment or
3933  * atomicity of device memory accesses. The recommended practice for writing
3934  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3935  * alt_write_word() functions.
3936  *
3937  * The struct declaration for register ALT_UART_SDMAM.
3938  */
3939 struct ALT_UART_SDMAM_s
3940 {
3941  uint32_t sdmam : 1; /* Shadow DMA Mode */
3942  uint32_t : 31; /* *UNDEFINED* */
3943 };
3944 
3945 /* The typedef declaration for register ALT_UART_SDMAM. */
3946 typedef volatile struct ALT_UART_SDMAM_s ALT_UART_SDMAM_t;
3947 #endif /* __ASSEMBLY__ */
3948 
3949 /* The byte offset of the ALT_UART_SDMAM register from the beginning of the component. */
3950 #define ALT_UART_SDMAM_OFST 0x94
3951 /* The address of the ALT_UART_SDMAM register. */
3952 #define ALT_UART_SDMAM_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SDMAM_OFST))
3953 
3954 /*
3955  * Register : Shadow FIFO Enable - sfe
3956  *
3957  * This is a shadow register for the FIFO enable bit [0] of register FCR.
3958  *
3959  * Register Layout
3960  *
3961  * Bits | Access | Reset | Description
3962  * :-------|:-------|:------|:-------------------
3963  * [0] | RW | 0x0 | Shadow FIFO Enable
3964  * [31:1] | ??? | 0x0 | *UNDEFINED*
3965  *
3966  */
3967 /*
3968  * Field : Shadow FIFO Enable - sfe
3969  *
3970  * This can be used to remove the burden of having to store the previously written
3971  * value to the FCR in memory and having to mask this value so that only the FIFO
3972  * enable bit gets updated. This enables/disables the transmit (Tx) and receive (Rx
3973  * ) FIFO's. If this bit is set to zero (disabled) after being enabled then both
3974  * the Tx and Rx controller portion of FIFO's will be reset.
3975  *
3976  * Field Enumeration Values:
3977  *
3978  * Enum | Value | Description
3979  * :------------------------|:------|:--------------
3980  * ALT_UART_SFE_SFE_E_DISD | 0x0 | Disable Rx/Tx
3981  * ALT_UART_SFE_SFE_E_END | 0x1 | Enable Rx/Tx
3982  *
3983  * Field Access Macros:
3984  *
3985  */
3986 /*
3987  * Enumerated value for register field ALT_UART_SFE_SFE
3988  *
3989  * Disable Rx/Tx
3990  */
3991 #define ALT_UART_SFE_SFE_E_DISD 0x0
3992 /*
3993  * Enumerated value for register field ALT_UART_SFE_SFE
3994  *
3995  * Enable Rx/Tx
3996  */
3997 #define ALT_UART_SFE_SFE_E_END 0x1
3998 
3999 /* The Least Significant Bit (LSB) position of the ALT_UART_SFE_SFE register field. */
4000 #define ALT_UART_SFE_SFE_LSB 0
4001 /* The Most Significant Bit (MSB) position of the ALT_UART_SFE_SFE register field. */
4002 #define ALT_UART_SFE_SFE_MSB 0
4003 /* The width in bits of the ALT_UART_SFE_SFE register field. */
4004 #define ALT_UART_SFE_SFE_WIDTH 1
4005 /* The mask used to set the ALT_UART_SFE_SFE register field value. */
4006 #define ALT_UART_SFE_SFE_SET_MSK 0x00000001
4007 /* The mask used to clear the ALT_UART_SFE_SFE register field value. */
4008 #define ALT_UART_SFE_SFE_CLR_MSK 0xfffffffe
4009 /* The reset value of the ALT_UART_SFE_SFE register field. */
4010 #define ALT_UART_SFE_SFE_RESET 0x0
4011 /* Extracts the ALT_UART_SFE_SFE field value from a register. */
4012 #define ALT_UART_SFE_SFE_GET(value) (((value) & 0x00000001) >> 0)
4013 /* Produces a ALT_UART_SFE_SFE register field value suitable for setting the register. */
4014 #define ALT_UART_SFE_SFE_SET(value) (((value) << 0) & 0x00000001)
4015 
4016 #ifndef __ASSEMBLY__
4017 /*
4018  * WARNING: The C register and register group struct declarations are provided for
4019  * convenience and illustrative purposes. They should, however, be used with
4020  * caution as the C language standard provides no guarantees about the alignment or
4021  * atomicity of device memory accesses. The recommended practice for writing
4022  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4023  * alt_write_word() functions.
4024  *
4025  * The struct declaration for register ALT_UART_SFE.
4026  */
4027 struct ALT_UART_SFE_s
4028 {
4029  uint32_t sfe : 1; /* Shadow FIFO Enable */
4030  uint32_t : 31; /* *UNDEFINED* */
4031 };
4032 
4033 /* The typedef declaration for register ALT_UART_SFE. */
4034 typedef volatile struct ALT_UART_SFE_s ALT_UART_SFE_t;
4035 #endif /* __ASSEMBLY__ */
4036 
4037 /* The byte offset of the ALT_UART_SFE register from the beginning of the component. */
4038 #define ALT_UART_SFE_OFST 0x98
4039 /* The address of the ALT_UART_SFE register. */
4040 #define ALT_UART_SFE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SFE_OFST))
4041 
4042 /*
4043  * Register : Shadow Rx Trigger - srt
4044  *
4045  * This is a shadow register for the Rx trigger bits (FCR[7:6]).
4046  *
4047  * Register Layout
4048  *
4049  * Bits | Access | Reset | Description
4050  * :-------|:-------|:------|:------------------------
4051  * [1:0] | RW | 0x0 | Shadow Rx Trigger Bits
4052  * [31:2] | ??? | 0x0 | *UNDEFINED*
4053  *
4054  */
4055 /*
4056  * Field : Shadow Rx Trigger Bits - srt
4057  *
4058  * This can be used to remove the burden of having to store the previously written
4059  * value to the FCR in memory and having to mask this value so that only the Rx
4060  * trigger bit gets updated. This is used to select the trigger level in the
4061  * receiver FIFO at which the Received Data Available Interrupt will be generated.
4062  * It also determines when the uart_dma_rx_req_n signal will be asserted when DMA
4063  * Mode (FCR[3]) is set to one. The enum below shows trigger levels that are
4064  * supported.
4065  *
4066  * Field Enumeration Values:
4067  *
4068  * Enum | Value | Description
4069  * :-------------------------------|:------|:----------------------
4070  * ALT_UART_SRT_SRT_E_ONECHAR | 0x0 | one character in fifo
4071  * ALT_UART_SRT_SRT_E_QUARTERFULL | 0x1 | FIFO 1/4 full
4072  * ALT_UART_SRT_SRT_E_HALFFULL | 0x2 | FIFO 1/2 full
4073  * ALT_UART_SRT_SRT_E_FULLLESS2 | 0x3 | FIFO 2 less than full
4074  *
4075  * Field Access Macros:
4076  *
4077  */
4078 /*
4079  * Enumerated value for register field ALT_UART_SRT_SRT
4080  *
4081  * one character in fifo
4082  */
4083 #define ALT_UART_SRT_SRT_E_ONECHAR 0x0
4084 /*
4085  * Enumerated value for register field ALT_UART_SRT_SRT
4086  *
4087  * FIFO 1/4 full
4088  */
4089 #define ALT_UART_SRT_SRT_E_QUARTERFULL 0x1
4090 /*
4091  * Enumerated value for register field ALT_UART_SRT_SRT
4092  *
4093  * FIFO 1/2 full
4094  */
4095 #define ALT_UART_SRT_SRT_E_HALFFULL 0x2
4096 /*
4097  * Enumerated value for register field ALT_UART_SRT_SRT
4098  *
4099  * FIFO 2 less than full
4100  */
4101 #define ALT_UART_SRT_SRT_E_FULLLESS2 0x3
4102 
4103 /* The Least Significant Bit (LSB) position of the ALT_UART_SRT_SRT register field. */
4104 #define ALT_UART_SRT_SRT_LSB 0
4105 /* The Most Significant Bit (MSB) position of the ALT_UART_SRT_SRT register field. */
4106 #define ALT_UART_SRT_SRT_MSB 1
4107 /* The width in bits of the ALT_UART_SRT_SRT register field. */
4108 #define ALT_UART_SRT_SRT_WIDTH 2
4109 /* The mask used to set the ALT_UART_SRT_SRT register field value. */
4110 #define ALT_UART_SRT_SRT_SET_MSK 0x00000003
4111 /* The mask used to clear the ALT_UART_SRT_SRT register field value. */
4112 #define ALT_UART_SRT_SRT_CLR_MSK 0xfffffffc
4113 /* The reset value of the ALT_UART_SRT_SRT register field. */
4114 #define ALT_UART_SRT_SRT_RESET 0x0
4115 /* Extracts the ALT_UART_SRT_SRT field value from a register. */
4116 #define ALT_UART_SRT_SRT_GET(value) (((value) & 0x00000003) >> 0)
4117 /* Produces a ALT_UART_SRT_SRT register field value suitable for setting the register. */
4118 #define ALT_UART_SRT_SRT_SET(value) (((value) << 0) & 0x00000003)
4119 
4120 #ifndef __ASSEMBLY__
4121 /*
4122  * WARNING: The C register and register group struct declarations are provided for
4123  * convenience and illustrative purposes. They should, however, be used with
4124  * caution as the C language standard provides no guarantees about the alignment or
4125  * atomicity of device memory accesses. The recommended practice for writing
4126  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4127  * alt_write_word() functions.
4128  *
4129  * The struct declaration for register ALT_UART_SRT.
4130  */
4131 struct ALT_UART_SRT_s
4132 {
4133  uint32_t srt : 2; /* Shadow Rx Trigger Bits */
4134  uint32_t : 30; /* *UNDEFINED* */
4135 };
4136 
4137 /* The typedef declaration for register ALT_UART_SRT. */
4138 typedef volatile struct ALT_UART_SRT_s ALT_UART_SRT_t;
4139 #endif /* __ASSEMBLY__ */
4140 
4141 /* The byte offset of the ALT_UART_SRT register from the beginning of the component. */
4142 #define ALT_UART_SRT_OFST 0x9c
4143 /* The address of the ALT_UART_SRT register. */
4144 #define ALT_UART_SRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRT_OFST))
4145 
4146 /*
4147  * Register : Shadow Tx Empty Trigger - stet
4148  *
4149  * This is a shadow register for the Tx empty trigger bits (FCR[5:4]).
4150  *
4151  * Register Layout
4152  *
4153  * Bits | Access | Reset | Description
4154  * :-------|:-------|:------|:-----------------------------
4155  * [1:0] | RW | 0x0 | Shadow Tx Empty Trigger Bits
4156  * [31:2] | ??? | 0x0 | *UNDEFINED*
4157  *
4158  */
4159 /*
4160  * Field : Shadow Tx Empty Trigger Bits - stet
4161  *
4162  * This can be used to remove the burden of having to store the previously written
4163  * value to the FCR in memory and having to mask this value so that only the Tx
4164  * empty trigger bit gets updated. This is used to select the empty threshold level
4165  * at which the THRE Interrupts will be generated when the mode is active. These
4166  * threshold levels are also described in. The enum trigger levels are supported.
4167  *
4168  * Field Enumeration Values:
4169  *
4170  * Enum | Value | Description
4171  * :---------------------------------|:------|:-----------------------
4172  * ALT_UART_STET_STET_E_FIFOEMPTY | 0x0 | FIFO empty
4173  * ALT_UART_STET_STET_E_TWOCHARS | 0x1 | Two characters in FIFO
4174  * ALT_UART_STET_STET_E_QUARTERFULL | 0x2 | FIFO quarter full
4175  * ALT_UART_STET_STET_E_HALFFULL | 0x3 | FIFO half full
4176  *
4177  * Field Access Macros:
4178  *
4179  */
4180 /*
4181  * Enumerated value for register field ALT_UART_STET_STET
4182  *
4183  * FIFO empty
4184  */
4185 #define ALT_UART_STET_STET_E_FIFOEMPTY 0x0
4186 /*
4187  * Enumerated value for register field ALT_UART_STET_STET
4188  *
4189  * Two characters in FIFO
4190  */
4191 #define ALT_UART_STET_STET_E_TWOCHARS 0x1
4192 /*
4193  * Enumerated value for register field ALT_UART_STET_STET
4194  *
4195  * FIFO quarter full
4196  */
4197 #define ALT_UART_STET_STET_E_QUARTERFULL 0x2
4198 /*
4199  * Enumerated value for register field ALT_UART_STET_STET
4200  *
4201  * FIFO half full
4202  */
4203 #define ALT_UART_STET_STET_E_HALFFULL 0x3
4204 
4205 /* The Least Significant Bit (LSB) position of the ALT_UART_STET_STET register field. */
4206 #define ALT_UART_STET_STET_LSB 0
4207 /* The Most Significant Bit (MSB) position of the ALT_UART_STET_STET register field. */
4208 #define ALT_UART_STET_STET_MSB 1
4209 /* The width in bits of the ALT_UART_STET_STET register field. */
4210 #define ALT_UART_STET_STET_WIDTH 2
4211 /* The mask used to set the ALT_UART_STET_STET register field value. */
4212 #define ALT_UART_STET_STET_SET_MSK 0x00000003
4213 /* The mask used to clear the ALT_UART_STET_STET register field value. */
4214 #define ALT_UART_STET_STET_CLR_MSK 0xfffffffc
4215 /* The reset value of the ALT_UART_STET_STET register field. */
4216 #define ALT_UART_STET_STET_RESET 0x0
4217 /* Extracts the ALT_UART_STET_STET field value from a register. */
4218 #define ALT_UART_STET_STET_GET(value) (((value) & 0x00000003) >> 0)
4219 /* Produces a ALT_UART_STET_STET register field value suitable for setting the register. */
4220 #define ALT_UART_STET_STET_SET(value) (((value) << 0) & 0x00000003)
4221 
4222 #ifndef __ASSEMBLY__
4223 /*
4224  * WARNING: The C register and register group struct declarations are provided for
4225  * convenience and illustrative purposes. They should, however, be used with
4226  * caution as the C language standard provides no guarantees about the alignment or
4227  * atomicity of device memory accesses. The recommended practice for writing
4228  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4229  * alt_write_word() functions.
4230  *
4231  * The struct declaration for register ALT_UART_STET.
4232  */
4233 struct ALT_UART_STET_s
4234 {
4235  uint32_t stet : 2; /* Shadow Tx Empty Trigger Bits */
4236  uint32_t : 30; /* *UNDEFINED* */
4237 };
4238 
4239 /* The typedef declaration for register ALT_UART_STET. */
4240 typedef volatile struct ALT_UART_STET_s ALT_UART_STET_t;
4241 #endif /* __ASSEMBLY__ */
4242 
4243 /* The byte offset of the ALT_UART_STET register from the beginning of the component. */
4244 #define ALT_UART_STET_OFST 0xa0
4245 /* The address of the ALT_UART_STET register. */
4246 #define ALT_UART_STET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_STET_OFST))
4247 
4248 /*
4249  * Register : Halt Tx - htx
4250  *
4251  * Used to halt transmission for testing.
4252  *
4253  * Register Layout
4254  *
4255  * Bits | Access | Reset | Description
4256  * :-------|:-------|:------|:-------------
4257  * [0] | RW | 0x0 | Halt Tx Bits
4258  * [31:1] | ??? | 0x0 | *UNDEFINED*
4259  *
4260  */
4261 /*
4262  * Field : Halt Tx Bits - htx
4263  *
4264  * This register is use to halt transmissions for testing, so that the transmit
4265  * FIFO can be filled by the master when FIFO's are enabled.
4266  *
4267  * Note, if FIFO's are not enabled, the setting of the halt Tx register will have
4268  * no effect on operation.
4269  *
4270  * Field Enumeration Values:
4271  *
4272  * Enum | Value | Description
4273  * :------------------------|:------|:-----------------
4274  * ALT_UART_HTX_HTX_E_DISD | 0x0 | Halt Tx disabled
4275  * ALT_UART_HTX_HTX_E_END | 0x1 | Halt Tx enabled
4276  *
4277  * Field Access Macros:
4278  *
4279  */
4280 /*
4281  * Enumerated value for register field ALT_UART_HTX_HTX
4282  *
4283  * Halt Tx disabled
4284  */
4285 #define ALT_UART_HTX_HTX_E_DISD 0x0
4286 /*
4287  * Enumerated value for register field ALT_UART_HTX_HTX
4288  *
4289  * Halt Tx enabled
4290  */
4291 #define ALT_UART_HTX_HTX_E_END 0x1
4292 
4293 /* The Least Significant Bit (LSB) position of the ALT_UART_HTX_HTX register field. */
4294 #define ALT_UART_HTX_HTX_LSB 0
4295 /* The Most Significant Bit (MSB) position of the ALT_UART_HTX_HTX register field. */
4296 #define ALT_UART_HTX_HTX_MSB 0
4297 /* The width in bits of the ALT_UART_HTX_HTX register field. */
4298 #define ALT_UART_HTX_HTX_WIDTH 1
4299 /* The mask used to set the ALT_UART_HTX_HTX register field value. */
4300 #define ALT_UART_HTX_HTX_SET_MSK 0x00000001
4301 /* The mask used to clear the ALT_UART_HTX_HTX register field value. */
4302 #define ALT_UART_HTX_HTX_CLR_MSK 0xfffffffe
4303 /* The reset value of the ALT_UART_HTX_HTX register field. */
4304 #define ALT_UART_HTX_HTX_RESET 0x0
4305 /* Extracts the ALT_UART_HTX_HTX field value from a register. */
4306 #define ALT_UART_HTX_HTX_GET(value) (((value) & 0x00000001) >> 0)
4307 /* Produces a ALT_UART_HTX_HTX register field value suitable for setting the register. */
4308 #define ALT_UART_HTX_HTX_SET(value) (((value) << 0) & 0x00000001)
4309 
4310 #ifndef __ASSEMBLY__
4311 /*
4312  * WARNING: The C register and register group struct declarations are provided for
4313  * convenience and illustrative purposes. They should, however, be used with
4314  * caution as the C language standard provides no guarantees about the alignment or
4315  * atomicity of device memory accesses. The recommended practice for writing
4316  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4317  * alt_write_word() functions.
4318  *
4319  * The struct declaration for register ALT_UART_HTX.
4320  */
4321 struct ALT_UART_HTX_s
4322 {
4323  uint32_t htx : 1; /* Halt Tx Bits */
4324  uint32_t : 31; /* *UNDEFINED* */
4325 };
4326 
4327 /* The typedef declaration for register ALT_UART_HTX. */
4328 typedef volatile struct ALT_UART_HTX_s ALT_UART_HTX_t;
4329 #endif /* __ASSEMBLY__ */
4330 
4331 /* The byte offset of the ALT_UART_HTX register from the beginning of the component. */
4332 #define ALT_UART_HTX_OFST 0xa4
4333 /* The address of the ALT_UART_HTX register. */
4334 #define ALT_UART_HTX_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_HTX_OFST))
4335 
4336 /*
4337  * Register : DMA Software Acknowledge - dmasa
4338  *
4339  * DMA Operation Control
4340  *
4341  * Register Layout
4342  *
4343  * Bits | Access | Reset | Description
4344  * :-------|:-------|:------|:------------------------------
4345  * [0] | W | 0x0 | DMA Software Acknowledge Bits
4346  * [31:1] | ??? | 0x0 | *UNDEFINED*
4347  *
4348  */
4349 /*
4350  * Field : DMA Software Acknowledge Bits - dmasa
4351  *
4352  * This register is used to perform DMA software acknowledge if a transfer needs to
4353  * be terminated due to an error condition. For example, if the DMA disables the
4354  * channel, then the uart should clear its request. This will cause the Tx request,
4355  * Tx single, Rx request and Rx single signals to de-assert. Note that this bit is
4356  * 'self-clearing' and it is not necessary to clear this bit.
4357  *
4358  * Field Access Macros:
4359  *
4360  */
4361 /* The Least Significant Bit (LSB) position of the ALT_UART_DMASA_DMASA register field. */
4362 #define ALT_UART_DMASA_DMASA_LSB 0
4363 /* The Most Significant Bit (MSB) position of the ALT_UART_DMASA_DMASA register field. */
4364 #define ALT_UART_DMASA_DMASA_MSB 0
4365 /* The width in bits of the ALT_UART_DMASA_DMASA register field. */
4366 #define ALT_UART_DMASA_DMASA_WIDTH 1
4367 /* The mask used to set the ALT_UART_DMASA_DMASA register field value. */
4368 #define ALT_UART_DMASA_DMASA_SET_MSK 0x00000001
4369 /* The mask used to clear the ALT_UART_DMASA_DMASA register field value. */
4370 #define ALT_UART_DMASA_DMASA_CLR_MSK 0xfffffffe
4371 /* The reset value of the ALT_UART_DMASA_DMASA register field. */
4372 #define ALT_UART_DMASA_DMASA_RESET 0x0
4373 /* Extracts the ALT_UART_DMASA_DMASA field value from a register. */
4374 #define ALT_UART_DMASA_DMASA_GET(value) (((value) & 0x00000001) >> 0)
4375 /* Produces a ALT_UART_DMASA_DMASA register field value suitable for setting the register. */
4376 #define ALT_UART_DMASA_DMASA_SET(value) (((value) << 0) & 0x00000001)
4377 
4378 #ifndef __ASSEMBLY__
4379 /*
4380  * WARNING: The C register and register group struct declarations are provided for
4381  * convenience and illustrative purposes. They should, however, be used with
4382  * caution as the C language standard provides no guarantees about the alignment or
4383  * atomicity of device memory accesses. The recommended practice for writing
4384  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4385  * alt_write_word() functions.
4386  *
4387  * The struct declaration for register ALT_UART_DMASA.
4388  */
4389 struct ALT_UART_DMASA_s
4390 {
4391  uint32_t dmasa : 1; /* DMA Software Acknowledge Bits */
4392  uint32_t : 31; /* *UNDEFINED* */
4393 };
4394 
4395 /* The typedef declaration for register ALT_UART_DMASA. */
4396 typedef volatile struct ALT_UART_DMASA_s ALT_UART_DMASA_t;
4397 #endif /* __ASSEMBLY__ */
4398 
4399 /* The byte offset of the ALT_UART_DMASA register from the beginning of the component. */
4400 #define ALT_UART_DMASA_OFST 0xa8
4401 /* The address of the ALT_UART_DMASA register. */
4402 #define ALT_UART_DMASA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_DMASA_OFST))
4403 
4404 /*
4405  * Register : Component Parameter Register - cpr
4406  *
4407  * Describes various fixed hardware setups states.
4408  *
4409  * Register Layout
4410  *
4411  * Bits | Access | Reset | Description
4412  * :--------|:-------|:------|:----------------------------------
4413  * [1:0] | R | 0x2 | APB DATA WIDTH
4414  * [3:2] | ??? | 0x0 | *UNDEFINED*
4415  * [4] | R | 0x1 | Auto Flow Control
4416  * [5] | R | 0x1 | THRE MODE
4417  * [6] | R | 0x0 | SIR MODE Unsupported
4418  * [7] | R | 0x0 | SIR LP MODE Unsupported
4419  * [8] | R | 0x1 | ADDITIONAL FEATURES Supported
4420  * [9] | R | 0x1 | FIFO ACCESS Supported
4421  * [10] | R | 0x1 | FIFO STAT Supported
4422  * [11] | R | 0x1 | SHADOW Supported
4423  * [12] | R | 0x1 | Configuartion ID Register Present
4424  * [13] | R | 0x1 | DMA EXTRA Supported
4425  * [15:14] | ??? | 0x0 | *UNDEFINED*
4426  * [23:16] | R | 0x37 | FIFO Depth
4427  * [31:24] | ??? | 0x0 | *UNDEFINED*
4428  *
4429  */
4430 /*
4431  * Field : APB DATA WIDTH - apbdatawidth
4432  *
4433  * Fixed to support an ABP data bus width of 32-bits.
4434  *
4435  * Field Enumeration Values:
4436  *
4437  * Enum | Value | Description
4438  * :----------------------------------------|:------|:-------------------------
4439  * ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS | 0x2 | APB Data Width = 32-bits
4440  *
4441  * Field Access Macros:
4442  *
4443  */
4444 /*
4445  * Enumerated value for register field ALT_UART_CPR_APBDATAWIDTH
4446  *
4447  * APB Data Width = 32-bits
4448  */
4449 #define ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS 0x2
4450 
4451 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_APBDATAWIDTH register field. */
4452 #define ALT_UART_CPR_APBDATAWIDTH_LSB 0
4453 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_APBDATAWIDTH register field. */
4454 #define ALT_UART_CPR_APBDATAWIDTH_MSB 1
4455 /* The width in bits of the ALT_UART_CPR_APBDATAWIDTH register field. */
4456 #define ALT_UART_CPR_APBDATAWIDTH_WIDTH 2
4457 /* The mask used to set the ALT_UART_CPR_APBDATAWIDTH register field value. */
4458 #define ALT_UART_CPR_APBDATAWIDTH_SET_MSK 0x00000003
4459 /* The mask used to clear the ALT_UART_CPR_APBDATAWIDTH register field value. */
4460 #define ALT_UART_CPR_APBDATAWIDTH_CLR_MSK 0xfffffffc
4461 /* The reset value of the ALT_UART_CPR_APBDATAWIDTH register field. */
4462 #define ALT_UART_CPR_APBDATAWIDTH_RESET 0x2
4463 /* Extracts the ALT_UART_CPR_APBDATAWIDTH field value from a register. */
4464 #define ALT_UART_CPR_APBDATAWIDTH_GET(value) (((value) & 0x00000003) >> 0)
4465 /* Produces a ALT_UART_CPR_APBDATAWIDTH register field value suitable for setting the register. */
4466 #define ALT_UART_CPR_APBDATAWIDTH_SET(value) (((value) << 0) & 0x00000003)
4467 
4468 /*
4469  * Field : Auto Flow Control - afce_mode
4470  *
4471  * Allows auto flow control.
4472  *
4473  * Field Enumeration Values:
4474  *
4475  * Enum | Value | Description
4476  * :----------------------------|:------|:------------
4477  * ALT_UART_CPR_AFCE_MOD_E_END | 0x1 | Auto Flow
4478  *
4479  * Field Access Macros:
4480  *
4481  */
4482 /*
4483  * Enumerated value for register field ALT_UART_CPR_AFCE_MOD
4484  *
4485  * Auto Flow
4486  */
4487 #define ALT_UART_CPR_AFCE_MOD_E_END 0x1
4488 
4489 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_AFCE_MOD register field. */
4490 #define ALT_UART_CPR_AFCE_MOD_LSB 4
4491 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_AFCE_MOD register field. */
4492 #define ALT_UART_CPR_AFCE_MOD_MSB 4
4493 /* The width in bits of the ALT_UART_CPR_AFCE_MOD register field. */
4494 #define ALT_UART_CPR_AFCE_MOD_WIDTH 1
4495 /* The mask used to set the ALT_UART_CPR_AFCE_MOD register field value. */
4496 #define ALT_UART_CPR_AFCE_MOD_SET_MSK 0x00000010
4497 /* The mask used to clear the ALT_UART_CPR_AFCE_MOD register field value. */
4498 #define ALT_UART_CPR_AFCE_MOD_CLR_MSK 0xffffffef
4499 /* The reset value of the ALT_UART_CPR_AFCE_MOD register field. */
4500 #define ALT_UART_CPR_AFCE_MOD_RESET 0x1
4501 /* Extracts the ALT_UART_CPR_AFCE_MOD field value from a register. */
4502 #define ALT_UART_CPR_AFCE_MOD_GET(value) (((value) & 0x00000010) >> 4)
4503 /* Produces a ALT_UART_CPR_AFCE_MOD register field value suitable for setting the register. */
4504 #define ALT_UART_CPR_AFCE_MOD_SET(value) (((value) << 4) & 0x00000010)
4505 
4506 /*
4507  * Field : THRE MODE - thre_mode
4508  *
4509  * Programmable Transmitter Hold Register Empty interrupt
4510  *
4511  * Field Enumeration Values:
4512  *
4513  * Enum | Value | Description
4514  * :----------------------------|:------|:------------------------------------------
4515  * ALT_UART_CPR_THRE_MOD_E_END | 0x1 | Programmable Tx Hold Reg. Empty interrupt
4516  * : | | present
4517  *
4518  * Field Access Macros:
4519  *
4520  */
4521 /*
4522  * Enumerated value for register field ALT_UART_CPR_THRE_MOD
4523  *
4524  * Programmable Tx Hold Reg. Empty interrupt present
4525  */
4526 #define ALT_UART_CPR_THRE_MOD_E_END 0x1
4527 
4528 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_THRE_MOD register field. */
4529 #define ALT_UART_CPR_THRE_MOD_LSB 5
4530 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_THRE_MOD register field. */
4531 #define ALT_UART_CPR_THRE_MOD_MSB 5
4532 /* The width in bits of the ALT_UART_CPR_THRE_MOD register field. */
4533 #define ALT_UART_CPR_THRE_MOD_WIDTH 1
4534 /* The mask used to set the ALT_UART_CPR_THRE_MOD register field value. */
4535 #define ALT_UART_CPR_THRE_MOD_SET_MSK 0x00000020
4536 /* The mask used to clear the ALT_UART_CPR_THRE_MOD register field value. */
4537 #define ALT_UART_CPR_THRE_MOD_CLR_MSK 0xffffffdf
4538 /* The reset value of the ALT_UART_CPR_THRE_MOD register field. */
4539 #define ALT_UART_CPR_THRE_MOD_RESET 0x1
4540 /* Extracts the ALT_UART_CPR_THRE_MOD field value from a register. */
4541 #define ALT_UART_CPR_THRE_MOD_GET(value) (((value) & 0x00000020) >> 5)
4542 /* Produces a ALT_UART_CPR_THRE_MOD register field value suitable for setting the register. */
4543 #define ALT_UART_CPR_THRE_MOD_SET(value) (((value) << 5) & 0x00000020)
4544 
4545 /*
4546  * Field : SIR MODE Unsupported - sir_mode
4547  *
4548  * Sir mode not used in this application.
4549  *
4550  * Field Enumeration Values:
4551  *
4552  * Enum | Value | Description
4553  * :----------------------------|:------|:-----------------------
4554  * ALT_UART_CPR_SIR_MOD_E_DISD | 0x0 | Sir Mode Not Supported
4555  *
4556  * Field Access Macros:
4557  *
4558  */
4559 /*
4560  * Enumerated value for register field ALT_UART_CPR_SIR_MOD
4561  *
4562  * Sir Mode Not Supported
4563  */
4564 #define ALT_UART_CPR_SIR_MOD_E_DISD 0x0
4565 
4566 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_MOD register field. */
4567 #define ALT_UART_CPR_SIR_MOD_LSB 6
4568 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_MOD register field. */
4569 #define ALT_UART_CPR_SIR_MOD_MSB 6
4570 /* The width in bits of the ALT_UART_CPR_SIR_MOD register field. */
4571 #define ALT_UART_CPR_SIR_MOD_WIDTH 1
4572 /* The mask used to set the ALT_UART_CPR_SIR_MOD register field value. */
4573 #define ALT_UART_CPR_SIR_MOD_SET_MSK 0x00000040
4574 /* The mask used to clear the ALT_UART_CPR_SIR_MOD register field value. */
4575 #define ALT_UART_CPR_SIR_MOD_CLR_MSK 0xffffffbf
4576 /* The reset value of the ALT_UART_CPR_SIR_MOD register field. */
4577 #define ALT_UART_CPR_SIR_MOD_RESET 0x0
4578 /* Extracts the ALT_UART_CPR_SIR_MOD field value from a register. */
4579 #define ALT_UART_CPR_SIR_MOD_GET(value) (((value) & 0x00000040) >> 6)
4580 /* Produces a ALT_UART_CPR_SIR_MOD register field value suitable for setting the register. */
4581 #define ALT_UART_CPR_SIR_MOD_SET(value) (((value) << 6) & 0x00000040)
4582 
4583 /*
4584  * Field : SIR LP MODE Unsupported - sir_lp_mode
4585  *
4586  * LP Sir Mode not used in this application.
4587  *
4588  * Field Enumeration Values:
4589  *
4590  * Enum | Value | Description
4591  * :-------------------------------|:------|:--------------------------
4592  * ALT_UART_CPR_SIR_LP_MOD_E_DISD | 0x0 | LP Sir Mode Not Supported
4593  *
4594  * Field Access Macros:
4595  *
4596  */
4597 /*
4598  * Enumerated value for register field ALT_UART_CPR_SIR_LP_MOD
4599  *
4600  * LP Sir Mode Not Supported
4601  */
4602 #define ALT_UART_CPR_SIR_LP_MOD_E_DISD 0x0
4603 
4604 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_LP_MOD register field. */
4605 #define ALT_UART_CPR_SIR_LP_MOD_LSB 7
4606 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_LP_MOD register field. */
4607 #define ALT_UART_CPR_SIR_LP_MOD_MSB 7
4608 /* The width in bits of the ALT_UART_CPR_SIR_LP_MOD register field. */
4609 #define ALT_UART_CPR_SIR_LP_MOD_WIDTH 1
4610 /* The mask used to set the ALT_UART_CPR_SIR_LP_MOD register field value. */
4611 #define ALT_UART_CPR_SIR_LP_MOD_SET_MSK 0x00000080
4612 /* The mask used to clear the ALT_UART_CPR_SIR_LP_MOD register field value. */
4613 #define ALT_UART_CPR_SIR_LP_MOD_CLR_MSK 0xffffff7f
4614 /* The reset value of the ALT_UART_CPR_SIR_LP_MOD register field. */
4615 #define ALT_UART_CPR_SIR_LP_MOD_RESET 0x0
4616 /* Extracts the ALT_UART_CPR_SIR_LP_MOD field value from a register. */
4617 #define ALT_UART_CPR_SIR_LP_MOD_GET(value) (((value) & 0x00000080) >> 7)
4618 /* Produces a ALT_UART_CPR_SIR_LP_MOD register field value suitable for setting the register. */
4619 #define ALT_UART_CPR_SIR_LP_MOD_SET(value) (((value) << 7) & 0x00000080)
4620 
4621 /*
4622  * Field : ADDITIONAL FEATURES Supported - additional_feat
4623  *
4624  * Configures the uart to include fifo status register, shadow registers and
4625  * encoded parameter register.
4626  *
4627  * Field Enumeration Values:
4628  *
4629  * Enum | Value | Description
4630  * :-----------------------------------|:------|:------------------------------
4631  * ALT_UART_CPR_ADDITIONAL_FEAT_E_END | 0x1 | Additional Features Supported
4632  *
4633  * Field Access Macros:
4634  *
4635  */
4636 /*
4637  * Enumerated value for register field ALT_UART_CPR_ADDITIONAL_FEAT
4638  *
4639  * Additional Features Supported
4640  */
4641 #define ALT_UART_CPR_ADDITIONAL_FEAT_E_END 0x1
4642 
4643 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */
4644 #define ALT_UART_CPR_ADDITIONAL_FEAT_LSB 8
4645 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */
4646 #define ALT_UART_CPR_ADDITIONAL_FEAT_MSB 8
4647 /* The width in bits of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */
4648 #define ALT_UART_CPR_ADDITIONAL_FEAT_WIDTH 1
4649 /* The mask used to set the ALT_UART_CPR_ADDITIONAL_FEAT register field value. */
4650 #define ALT_UART_CPR_ADDITIONAL_FEAT_SET_MSK 0x00000100
4651 /* The mask used to clear the ALT_UART_CPR_ADDITIONAL_FEAT register field value. */
4652 #define ALT_UART_CPR_ADDITIONAL_FEAT_CLR_MSK 0xfffffeff
4653 /* The reset value of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */
4654 #define ALT_UART_CPR_ADDITIONAL_FEAT_RESET 0x1
4655 /* Extracts the ALT_UART_CPR_ADDITIONAL_FEAT field value from a register. */
4656 #define ALT_UART_CPR_ADDITIONAL_FEAT_GET(value) (((value) & 0x00000100) >> 8)
4657 /* Produces a ALT_UART_CPR_ADDITIONAL_FEAT register field value suitable for setting the register. */
4658 #define ALT_UART_CPR_ADDITIONAL_FEAT_SET(value) (((value) << 8) & 0x00000100)
4659 
4660 /*
4661  * Field : FIFO ACCESS Supported - fifo_access
4662  *
4663  * Configures the peripheral to have a programmable FIFO access mode. This is used
4664  * for test purposes, to allow the receiver FIFO to be written and the transmit
4665  * FIFO to be read when FIFOs are implemented and enabled.
4666  *
4667  * Field Enumeration Values:
4668  *
4669  * Enum | Value | Description
4670  * :-------------------------------|:------|:----------------------
4671  * ALT_UART_CPR_FIFO_ACCESS_E_END | 0x1 | FIFO Access Supported
4672  *
4673  * Field Access Macros:
4674  *
4675  */
4676 /*
4677  * Enumerated value for register field ALT_UART_CPR_FIFO_ACCESS
4678  *
4679  * FIFO Access Supported
4680  */
4681 #define ALT_UART_CPR_FIFO_ACCESS_E_END 0x1
4682 
4683 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_ACCESS register field. */
4684 #define ALT_UART_CPR_FIFO_ACCESS_LSB 9
4685 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_ACCESS register field. */
4686 #define ALT_UART_CPR_FIFO_ACCESS_MSB 9
4687 /* The width in bits of the ALT_UART_CPR_FIFO_ACCESS register field. */
4688 #define ALT_UART_CPR_FIFO_ACCESS_WIDTH 1
4689 /* The mask used to set the ALT_UART_CPR_FIFO_ACCESS register field value. */
4690 #define ALT_UART_CPR_FIFO_ACCESS_SET_MSK 0x00000200
4691 /* The mask used to clear the ALT_UART_CPR_FIFO_ACCESS register field value. */
4692 #define ALT_UART_CPR_FIFO_ACCESS_CLR_MSK 0xfffffdff
4693 /* The reset value of the ALT_UART_CPR_FIFO_ACCESS register field. */
4694 #define ALT_UART_CPR_FIFO_ACCESS_RESET 0x1
4695 /* Extracts the ALT_UART_CPR_FIFO_ACCESS field value from a register. */
4696 #define ALT_UART_CPR_FIFO_ACCESS_GET(value) (((value) & 0x00000200) >> 9)
4697 /* Produces a ALT_UART_CPR_FIFO_ACCESS register field value suitable for setting the register. */
4698 #define ALT_UART_CPR_FIFO_ACCESS_SET(value) (((value) << 9) & 0x00000200)
4699 
4700 /*
4701  * Field : FIFO STAT Supported - fifo_stat
4702  *
4703  * Configures the peripheral to have three additional FIFO status registers.
4704  *
4705  * Field Enumeration Values:
4706  *
4707  * Enum | Value | Description
4708  * :-----------------------------|:------|:--------------------
4709  * ALT_UART_CPR_FIFO_STAT_E_END | 0x1 | FIFO Stat Supported
4710  *
4711  * Field Access Macros:
4712  *
4713  */
4714 /*
4715  * Enumerated value for register field ALT_UART_CPR_FIFO_STAT
4716  *
4717  * FIFO Stat Supported
4718  */
4719 #define ALT_UART_CPR_FIFO_STAT_E_END 0x1
4720 
4721 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_STAT register field. */
4722 #define ALT_UART_CPR_FIFO_STAT_LSB 10
4723 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_STAT register field. */
4724 #define ALT_UART_CPR_FIFO_STAT_MSB 10
4725 /* The width in bits of the ALT_UART_CPR_FIFO_STAT register field. */
4726 #define ALT_UART_CPR_FIFO_STAT_WIDTH 1
4727 /* The mask used to set the ALT_UART_CPR_FIFO_STAT register field value. */
4728 #define ALT_UART_CPR_FIFO_STAT_SET_MSK 0x00000400
4729 /* The mask used to clear the ALT_UART_CPR_FIFO_STAT register field value. */
4730 #define ALT_UART_CPR_FIFO_STAT_CLR_MSK 0xfffffbff
4731 /* The reset value of the ALT_UART_CPR_FIFO_STAT register field. */
4732 #define ALT_UART_CPR_FIFO_STAT_RESET 0x1
4733 /* Extracts the ALT_UART_CPR_FIFO_STAT field value from a register. */
4734 #define ALT_UART_CPR_FIFO_STAT_GET(value) (((value) & 0x00000400) >> 10)
4735 /* Produces a ALT_UART_CPR_FIFO_STAT register field value suitable for setting the register. */
4736 #define ALT_UART_CPR_FIFO_STAT_SET(value) (((value) << 10) & 0x00000400)
4737 
4738 /*
4739  * Field : SHADOW Supported - shadow
4740  *
4741  * Configures the peripheral to have seven additional registers that shadow some of
4742  * the existing register bits that are regularly modified by software. These can be
4743  * used to reduce the software overhead that is introduced by having to perform
4744  * read-modify writes.
4745  *
4746  * Field Enumeration Values:
4747  *
4748  * Enum | Value | Description
4749  * :--------------------------|:------|:-----------------
4750  * ALT_UART_CPR_SHADOW_E_END | 0x1 | Shadow Supported
4751  *
4752  * Field Access Macros:
4753  *
4754  */
4755 /*
4756  * Enumerated value for register field ALT_UART_CPR_SHADOW
4757  *
4758  * Shadow Supported
4759  */
4760 #define ALT_UART_CPR_SHADOW_E_END 0x1
4761 
4762 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SHADOW register field. */
4763 #define ALT_UART_CPR_SHADOW_LSB 11
4764 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SHADOW register field. */
4765 #define ALT_UART_CPR_SHADOW_MSB 11
4766 /* The width in bits of the ALT_UART_CPR_SHADOW register field. */
4767 #define ALT_UART_CPR_SHADOW_WIDTH 1
4768 /* The mask used to set the ALT_UART_CPR_SHADOW register field value. */
4769 #define ALT_UART_CPR_SHADOW_SET_MSK 0x00000800
4770 /* The mask used to clear the ALT_UART_CPR_SHADOW register field value. */
4771 #define ALT_UART_CPR_SHADOW_CLR_MSK 0xfffff7ff
4772 /* The reset value of the ALT_UART_CPR_SHADOW register field. */
4773 #define ALT_UART_CPR_SHADOW_RESET 0x1
4774 /* Extracts the ALT_UART_CPR_SHADOW field value from a register. */
4775 #define ALT_UART_CPR_SHADOW_GET(value) (((value) & 0x00000800) >> 11)
4776 /* Produces a ALT_UART_CPR_SHADOW register field value suitable for setting the register. */
4777 #define ALT_UART_CPR_SHADOW_SET(value) (((value) << 11) & 0x00000800)
4778 
4779 /*
4780  * Field : Configuartion ID Register Present - uart_add_encoded_param
4781  *
4782  * Configures the peripheral to have a configuration identification register.
4783  *
4784  * Field Enumeration Values:
4785  *
4786  * Enum | Value | Description
4787  * :--------------------------------------|:------|:--------------------
4788  * ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END | 0x1 | ID register present
4789  *
4790  * Field Access Macros:
4791  *
4792  */
4793 /*
4794  * Enumerated value for register field ALT_UART_CPR_UART_ADD_ENC_PARAM
4795  *
4796  * ID register present
4797  */
4798 #define ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END 0x1
4799 
4800 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */
4801 #define ALT_UART_CPR_UART_ADD_ENC_PARAM_LSB 12
4802 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */
4803 #define ALT_UART_CPR_UART_ADD_ENC_PARAM_MSB 12
4804 /* The width in bits of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */
4805 #define ALT_UART_CPR_UART_ADD_ENC_PARAM_WIDTH 1
4806 /* The mask used to set the ALT_UART_CPR_UART_ADD_ENC_PARAM register field value. */
4807 #define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET_MSK 0x00001000
4808 /* The mask used to clear the ALT_UART_CPR_UART_ADD_ENC_PARAM register field value. */
4809 #define ALT_UART_CPR_UART_ADD_ENC_PARAM_CLR_MSK 0xffffefff
4810 /* The reset value of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */
4811 #define ALT_UART_CPR_UART_ADD_ENC_PARAM_RESET 0x1
4812 /* Extracts the ALT_UART_CPR_UART_ADD_ENC_PARAM field value from a register. */
4813 #define ALT_UART_CPR_UART_ADD_ENC_PARAM_GET(value) (((value) & 0x00001000) >> 12)
4814 /* Produces a ALT_UART_CPR_UART_ADD_ENC_PARAM register field value suitable for setting the register. */
4815 #define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET(value) (((value) << 12) & 0x00001000)
4816 
4817 /*
4818  * Field : DMA EXTRA Supported - dma_extra
4819  *
4820  * Configures the peripheral to have four additional DMA signals on the interface.
4821  *
4822  * Field Enumeration Values:
4823  *
4824  * Enum | Value | Description
4825  * :-----------------------------|:------|:--------------------
4826  * ALT_UART_CPR_DMA_EXTRA_E_END | 0x1 | DMA Extra Supported
4827  *
4828  * Field Access Macros:
4829  *
4830  */
4831 /*
4832  * Enumerated value for register field ALT_UART_CPR_DMA_EXTRA
4833  *
4834  * DMA Extra Supported
4835  */
4836 #define ALT_UART_CPR_DMA_EXTRA_E_END 0x1
4837 
4838 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_DMA_EXTRA register field. */
4839 #define ALT_UART_CPR_DMA_EXTRA_LSB 13
4840 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_DMA_EXTRA register field. */
4841 #define ALT_UART_CPR_DMA_EXTRA_MSB 13
4842 /* The width in bits of the ALT_UART_CPR_DMA_EXTRA register field. */
4843 #define ALT_UART_CPR_DMA_EXTRA_WIDTH 1
4844 /* The mask used to set the ALT_UART_CPR_DMA_EXTRA register field value. */
4845 #define ALT_UART_CPR_DMA_EXTRA_SET_MSK 0x00002000
4846 /* The mask used to clear the ALT_UART_CPR_DMA_EXTRA register field value. */
4847 #define ALT_UART_CPR_DMA_EXTRA_CLR_MSK 0xffffdfff
4848 /* The reset value of the ALT_UART_CPR_DMA_EXTRA register field. */
4849 #define ALT_UART_CPR_DMA_EXTRA_RESET 0x1
4850 /* Extracts the ALT_UART_CPR_DMA_EXTRA field value from a register. */
4851 #define ALT_UART_CPR_DMA_EXTRA_GET(value) (((value) & 0x00002000) >> 13)
4852 /* Produces a ALT_UART_CPR_DMA_EXTRA register field value suitable for setting the register. */
4853 #define ALT_UART_CPR_DMA_EXTRA_SET(value) (((value) << 13) & 0x00002000)
4854 
4855 /*
4856  * Field : FIFO Depth - fifo_mode
4857  *
4858  * Receiver and Transmitter FIFO depth in bytes.
4859  *
4860  * Field Enumeration Values:
4861  *
4862  * Enum | Value | Description
4863  * :-------------------------------------|:------|:---------------------
4864  * ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES | 0x80 | FIFO Depth 128 bytes
4865  *
4866  * Field Access Macros:
4867  *
4868  */
4869 /*
4870  * Enumerated value for register field ALT_UART_CPR_FIFO_MOD
4871  *
4872  * FIFO Depth 128 bytes
4873  */
4874 #define ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES 0x80
4875 
4876 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_MOD register field. */
4877 #define ALT_UART_CPR_FIFO_MOD_LSB 16
4878 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_MOD register field. */
4879 #define ALT_UART_CPR_FIFO_MOD_MSB 23
4880 /* The width in bits of the ALT_UART_CPR_FIFO_MOD register field. */
4881 #define ALT_UART_CPR_FIFO_MOD_WIDTH 8
4882 /* The mask used to set the ALT_UART_CPR_FIFO_MOD register field value. */
4883 #define ALT_UART_CPR_FIFO_MOD_SET_MSK 0x00ff0000
4884 /* The mask used to clear the ALT_UART_CPR_FIFO_MOD register field value. */
4885 #define ALT_UART_CPR_FIFO_MOD_CLR_MSK 0xff00ffff
4886 /* The reset value of the ALT_UART_CPR_FIFO_MOD register field. */
4887 #define ALT_UART_CPR_FIFO_MOD_RESET 0x37
4888 /* Extracts the ALT_UART_CPR_FIFO_MOD field value from a register. */
4889 #define ALT_UART_CPR_FIFO_MOD_GET(value) (((value) & 0x00ff0000) >> 16)
4890 /* Produces a ALT_UART_CPR_FIFO_MOD register field value suitable for setting the register. */
4891 #define ALT_UART_CPR_FIFO_MOD_SET(value) (((value) << 16) & 0x00ff0000)
4892 
4893 #ifndef __ASSEMBLY__
4894 /*
4895  * WARNING: The C register and register group struct declarations are provided for
4896  * convenience and illustrative purposes. They should, however, be used with
4897  * caution as the C language standard provides no guarantees about the alignment or
4898  * atomicity of device memory accesses. The recommended practice for writing
4899  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4900  * alt_write_word() functions.
4901  *
4902  * The struct declaration for register ALT_UART_CPR.
4903  */
4904 struct ALT_UART_CPR_s
4905 {
4906  const uint32_t apbdatawidth : 2; /* APB DATA WIDTH */
4907  uint32_t : 2; /* *UNDEFINED* */
4908  const uint32_t afce_mode : 1; /* Auto Flow Control */
4909  const uint32_t thre_mode : 1; /* THRE MODE */
4910  const uint32_t sir_mode : 1; /* SIR MODE Unsupported */
4911  const uint32_t sir_lp_mode : 1; /* SIR LP MODE Unsupported */
4912  const uint32_t additional_feat : 1; /* ADDITIONAL FEATURES Supported */
4913  const uint32_t fifo_access : 1; /* FIFO ACCESS Supported */
4914  const uint32_t fifo_stat : 1; /* FIFO STAT Supported */
4915  const uint32_t shadow : 1; /* SHADOW Supported */
4916  const uint32_t uart_add_encoded_param : 1; /* Configuartion ID Register Present */
4917  const uint32_t dma_extra : 1; /* DMA EXTRA Supported */
4918  uint32_t : 2; /* *UNDEFINED* */
4919  const uint32_t fifo_mode : 8; /* FIFO Depth */
4920  uint32_t : 8; /* *UNDEFINED* */
4921 };
4922 
4923 /* The typedef declaration for register ALT_UART_CPR. */
4924 typedef volatile struct ALT_UART_CPR_s ALT_UART_CPR_t;
4925 #endif /* __ASSEMBLY__ */
4926 
4927 /* The byte offset of the ALT_UART_CPR register from the beginning of the component. */
4928 #define ALT_UART_CPR_OFST 0xf4
4929 /* The address of the ALT_UART_CPR register. */
4930 #define ALT_UART_CPR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_CPR_OFST))
4931 
4932 /*
4933  * Register : Component Version - ucv
4934  *
4935  * Used only with Additional Features
4936  *
4937  * Register Layout
4938  *
4939  * Bits | Access | Reset | Description
4940  * :-------|:-------|:-----------|:--------------
4941  * [31:0] | R | 0x3331312a | ASCII version
4942  *
4943  */
4944 /*
4945  * Field : ASCII version - uart_component_version
4946  *
4947  * ASCII value for each number in the version, followed by *For example 32_30_31_2A
4948  * represents the version 2.01a
4949  *
4950  * Field Access Macros:
4951  *
4952  */
4953 /* The Least Significant Bit (LSB) position of the ALT_UART_UCV_UART_COMPONENT_VER register field. */
4954 #define ALT_UART_UCV_UART_COMPONENT_VER_LSB 0
4955 /* The Most Significant Bit (MSB) position of the ALT_UART_UCV_UART_COMPONENT_VER register field. */
4956 #define ALT_UART_UCV_UART_COMPONENT_VER_MSB 31
4957 /* The width in bits of the ALT_UART_UCV_UART_COMPONENT_VER register field. */
4958 #define ALT_UART_UCV_UART_COMPONENT_VER_WIDTH 32
4959 /* The mask used to set the ALT_UART_UCV_UART_COMPONENT_VER register field value. */
4960 #define ALT_UART_UCV_UART_COMPONENT_VER_SET_MSK 0xffffffff
4961 /* The mask used to clear the ALT_UART_UCV_UART_COMPONENT_VER register field value. */
4962 #define ALT_UART_UCV_UART_COMPONENT_VER_CLR_MSK 0x00000000
4963 /* The reset value of the ALT_UART_UCV_UART_COMPONENT_VER register field. */
4964 #define ALT_UART_UCV_UART_COMPONENT_VER_RESET 0x3331312a
4965 /* Extracts the ALT_UART_UCV_UART_COMPONENT_VER field value from a register. */
4966 #define ALT_UART_UCV_UART_COMPONENT_VER_GET(value) (((value) & 0xffffffff) >> 0)
4967 /* Produces a ALT_UART_UCV_UART_COMPONENT_VER register field value suitable for setting the register. */
4968 #define ALT_UART_UCV_UART_COMPONENT_VER_SET(value) (((value) << 0) & 0xffffffff)
4969 
4970 #ifndef __ASSEMBLY__
4971 /*
4972  * WARNING: The C register and register group struct declarations are provided for
4973  * convenience and illustrative purposes. They should, however, be used with
4974  * caution as the C language standard provides no guarantees about the alignment or
4975  * atomicity of device memory accesses. The recommended practice for writing
4976  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4977  * alt_write_word() functions.
4978  *
4979  * The struct declaration for register ALT_UART_UCV.
4980  */
4981 struct ALT_UART_UCV_s
4982 {
4983  const uint32_t uart_component_version : 32; /* ASCII version */
4984 };
4985 
4986 /* The typedef declaration for register ALT_UART_UCV. */
4987 typedef volatile struct ALT_UART_UCV_s ALT_UART_UCV_t;
4988 #endif /* __ASSEMBLY__ */
4989 
4990 /* The byte offset of the ALT_UART_UCV register from the beginning of the component. */
4991 #define ALT_UART_UCV_OFST 0xf8
4992 /* The address of the ALT_UART_UCV register. */
4993 #define ALT_UART_UCV_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_UCV_OFST))
4994 
4995 /*
4996  * Register : Component Type Register - ctr
4997  *
4998  * Describes a hex value associated with the component.
4999  *
5000  * Register Layout
5001  *
5002  * Bits | Access | Reset | Description
5003  * :-------|:-------|:-----------|:--------------
5004  * [31:0] | R | 0x44570110 | Peripheral ID
5005  *
5006  */
5007 /*
5008  * Field : Peripheral ID - peripheral_id
5009  *
5010  * This register contains the peripherals identification code.
5011  *
5012  * Field Access Macros:
5013  *
5014  */
5015 /* The Least Significant Bit (LSB) position of the ALT_UART_CTR_PERIPHERAL_ID register field. */
5016 #define ALT_UART_CTR_PERIPHERAL_ID_LSB 0
5017 /* The Most Significant Bit (MSB) position of the ALT_UART_CTR_PERIPHERAL_ID register field. */
5018 #define ALT_UART_CTR_PERIPHERAL_ID_MSB 31
5019 /* The width in bits of the ALT_UART_CTR_PERIPHERAL_ID register field. */
5020 #define ALT_UART_CTR_PERIPHERAL_ID_WIDTH 32
5021 /* The mask used to set the ALT_UART_CTR_PERIPHERAL_ID register field value. */
5022 #define ALT_UART_CTR_PERIPHERAL_ID_SET_MSK 0xffffffff
5023 /* The mask used to clear the ALT_UART_CTR_PERIPHERAL_ID register field value. */
5024 #define ALT_UART_CTR_PERIPHERAL_ID_CLR_MSK 0x00000000
5025 /* The reset value of the ALT_UART_CTR_PERIPHERAL_ID register field. */
5026 #define ALT_UART_CTR_PERIPHERAL_ID_RESET 0x44570110
5027 /* Extracts the ALT_UART_CTR_PERIPHERAL_ID field value from a register. */
5028 #define ALT_UART_CTR_PERIPHERAL_ID_GET(value) (((value) & 0xffffffff) >> 0)
5029 /* Produces a ALT_UART_CTR_PERIPHERAL_ID register field value suitable for setting the register. */
5030 #define ALT_UART_CTR_PERIPHERAL_ID_SET(value) (((value) << 0) & 0xffffffff)
5031 
5032 #ifndef __ASSEMBLY__
5033 /*
5034  * WARNING: The C register and register group struct declarations are provided for
5035  * convenience and illustrative purposes. They should, however, be used with
5036  * caution as the C language standard provides no guarantees about the alignment or
5037  * atomicity of device memory accesses. The recommended practice for writing
5038  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5039  * alt_write_word() functions.
5040  *
5041  * The struct declaration for register ALT_UART_CTR.
5042  */
5043 struct ALT_UART_CTR_s
5044 {
5045  const uint32_t peripheral_id : 32; /* Peripheral ID */
5046 };
5047 
5048 /* The typedef declaration for register ALT_UART_CTR. */
5049 typedef volatile struct ALT_UART_CTR_s ALT_UART_CTR_t;
5050 #endif /* __ASSEMBLY__ */
5051 
5052 /* The byte offset of the ALT_UART_CTR register from the beginning of the component. */
5053 #define ALT_UART_CTR_OFST 0xfc
5054 /* The address of the ALT_UART_CTR register. */
5055 #define ALT_UART_CTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_CTR_OFST))
5056 
5057 #ifndef __ASSEMBLY__
5058 /*
5059  * WARNING: The C register and register group struct declarations are provided for
5060  * convenience and illustrative purposes. They should, however, be used with
5061  * caution as the C language standard provides no guarantees about the alignment or
5062  * atomicity of device memory accesses. The recommended practice for writing
5063  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5064  * alt_write_word() functions.
5065  *
5066  * The struct declaration for register group ALT_UART.
5067  */
5068 struct ALT_UART_s
5069 {
5070  ALT_UART_RBR_THR_DLL_t rbr_thr_dll; /* ALT_UART_RBR_THR_DLL */
5071  ALT_UART_IER_DLH_t ier_dlh; /* ALT_UART_IER_DLH */
5072  /* Union for registers colocated at base address offset #0x. */
5073  union
5074  {
5075  ALT_UART_IIR_t iir; /* ALT_UART_IIR */
5076  ALT_UART_FCR_t fcr; /* ALT_UART_FCR */
5077  } _u_0x8;
5078  ALT_UART_LCR_t lcr; /* ALT_UART_LCR */
5079  ALT_UART_MCR_t mcr; /* ALT_UART_MCR */
5080  ALT_UART_LSR_t lsr; /* ALT_UART_LSR */
5081  ALT_UART_MSR_t msr; /* ALT_UART_MSR */
5082  ALT_UART_SCR_t scr; /* ALT_UART_SCR */
5083  volatile uint32_t _pad_0x20_0x2f[4]; /* *UNDEFINED* */
5084  ALT_UART_SRBR_t srbr; /* ALT_UART_SRBR */
5085  ALT_UART_STHR_t sthr; /* ALT_UART_STHR */
5086  volatile uint32_t _pad_0x38_0x6f[14]; /* *UNDEFINED* */
5087  ALT_UART_FAR_t far; /* ALT_UART_FAR */
5088  ALT_UART_TFR_t tfr; /* ALT_UART_TFR */
5089  ALT_UART_RFW_t RFW; /* ALT_UART_RFW */
5090  ALT_UART_USR_t usr; /* ALT_UART_USR */
5091  ALT_UART_TFL_t tfl; /* ALT_UART_TFL */
5092  ALT_UART_RFL_t rfl; /* ALT_UART_RFL */
5093  ALT_UART_SRR_t srr; /* ALT_UART_SRR */
5094  ALT_UART_SRTS_t srts; /* ALT_UART_SRTS */
5095  ALT_UART_SBCR_t sbcr; /* ALT_UART_SBCR */
5096  ALT_UART_SDMAM_t sdmam; /* ALT_UART_SDMAM */
5097  ALT_UART_SFE_t sfe; /* ALT_UART_SFE */
5098  ALT_UART_SRT_t srt; /* ALT_UART_SRT */
5099  ALT_UART_STET_t stet; /* ALT_UART_STET */
5100  ALT_UART_HTX_t htx; /* ALT_UART_HTX */
5101  ALT_UART_DMASA_t dmasa; /* ALT_UART_DMASA */
5102  volatile uint32_t _pad_0xac_0xf3[18]; /* *UNDEFINED* */
5103  ALT_UART_CPR_t cpr; /* ALT_UART_CPR */
5104  ALT_UART_UCV_t ucv; /* ALT_UART_UCV */
5105  ALT_UART_CTR_t ctr; /* ALT_UART_CTR */
5106 };
5107 
5108 /* The typedef declaration for register group ALT_UART. */
5109 typedef volatile struct ALT_UART_s ALT_UART_t;
5110 /* The struct declaration for the raw register contents of register group ALT_UART. */
5111 struct ALT_UART_raw_s
5112 {
5113  volatile uint32_t rbr_thr_dll; /* ALT_UART_RBR_THR_DLL */
5114  volatile uint32_t ier_dlh; /* ALT_UART_IER_DLH */
5115  /* Union for registers colocated at base address offset #0x. */
5116  union
5117  {
5118  volatile uint32_t iir; /* ALT_UART_IIR */
5119  volatile uint32_t fcr; /* ALT_UART_FCR */
5120  } _u_0x8;
5121  volatile uint32_t lcr; /* ALT_UART_LCR */
5122  volatile uint32_t mcr; /* ALT_UART_MCR */
5123  volatile uint32_t lsr; /* ALT_UART_LSR */
5124  volatile uint32_t msr; /* ALT_UART_MSR */
5125  volatile uint32_t scr; /* ALT_UART_SCR */
5126  uint32_t _pad_0x20_0x2f[4]; /* *UNDEFINED* */
5127  volatile uint32_t srbr; /* ALT_UART_SRBR */
5128  volatile uint32_t sthr; /* ALT_UART_STHR */
5129  uint32_t _pad_0x38_0x6f[14]; /* *UNDEFINED* */
5130  volatile uint32_t far; /* ALT_UART_FAR */
5131  volatile uint32_t tfr; /* ALT_UART_TFR */
5132  volatile uint32_t RFW; /* ALT_UART_RFW */
5133  volatile uint32_t usr; /* ALT_UART_USR */
5134  volatile uint32_t tfl; /* ALT_UART_TFL */
5135  volatile uint32_t rfl; /* ALT_UART_RFL */
5136  volatile uint32_t srr; /* ALT_UART_SRR */
5137  volatile uint32_t srts; /* ALT_UART_SRTS */
5138  volatile uint32_t sbcr; /* ALT_UART_SBCR */
5139  volatile uint32_t sdmam; /* ALT_UART_SDMAM */
5140  volatile uint32_t sfe; /* ALT_UART_SFE */
5141  volatile uint32_t srt; /* ALT_UART_SRT */
5142  volatile uint32_t stet; /* ALT_UART_STET */
5143  volatile uint32_t htx; /* ALT_UART_HTX */
5144  volatile uint32_t dmasa; /* ALT_UART_DMASA */
5145  uint32_t _pad_0xac_0xf3[18]; /* *UNDEFINED* */
5146  volatile uint32_t cpr; /* ALT_UART_CPR */
5147  volatile uint32_t ucv; /* ALT_UART_UCV */
5148  volatile uint32_t ctr; /* ALT_UART_CTR */
5149 };
5150 
5151 /* The typedef declaration for the raw register contents of register group ALT_UART. */
5152 typedef volatile struct ALT_UART_raw_s ALT_UART_raw_t;
5153 #endif /* __ASSEMBLY__ */
5154 
5155 
5156 #ifdef __cplusplus
5157 }
5158 #endif /* __cplusplus */
5159 #endif /* __ALTERA_ALT_UART_H__ */
5160