Hardware Libraries  20.1
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alt_emac_dma.h
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32 
33 /* Altera - ALT_EMAC_DMA */
34 
35 #ifndef __ALT_SOCAL_EMAC_DMA_H__
36 #define __ALT_SOCAL_EMAC_DMA_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : EMAC_DMA
50  * The address block DMA contains 23 Registers : Bus_Mode to HW_Feature
51  *
52  */
53 /*
54  * Register : Bus_Mode
55  *
56  * <b> Register 0 (Bus Mode Register) </b>
57  *
58  * The Bus Mode register establishes the bus operating modes for the DMA.
59  *
60  * Register Layout
61  *
62  * Bits | Access | Reset | Description
63  * :--------|:-------|:------|:----------------------------------
64  * [0] | RW | 0x1 | ALT_EMAC_DMA_BUS_MODE_SWR
65  * [1] | R | 0x0 | ALT_EMAC_DMA_BUS_MODE_DA
66  * [6:2] | RW | 0x0 | ALT_EMAC_DMA_BUS_MODE_DSL
67  * [7] | RW | 0x0 | ALT_EMAC_DMA_BUS_MODE_ATDS
68  * [13:8] | RW | 0x1 | ALT_EMAC_DMA_BUS_MODE_PBL
69  * [15:14] | R | 0x0 | ALT_EMAC_DMA_BUS_MODE_PR
70  * [16] | RW | 0x0 | ALT_EMAC_DMA_BUS_MODE_FB
71  * [22:17] | RW | 0x1 | ALT_EMAC_DMA_BUS_MODE_RPBL
72  * [23] | RW | 0x0 | ALT_EMAC_DMA_BUS_MODE_USP
73  * [24] | RW | 0x0 | ALT_EMAC_DMA_BUS_MODE_PBLX8
74  * [25] | RW | 0x0 | ALT_EMAC_DMA_BUS_MODE_AAL
75  * [26] | R | 0x0 | ALT_EMAC_DMA_BUS_MODE_MB
76  * [27] | R | 0x0 | ALT_EMAC_DMA_BUS_MODE_TXPR
77  * [29:28] | R | 0x0 | ALT_EMAC_DMA_BUS_MODE_PRWG
78  * [30] | R | 0x0 | ALT_EMAC_DMA_BUS_MODE_RESERVED_30
79  * [31] | R | 0x0 | ALT_EMAC_DMA_BUS_MODE_RIB
80  *
81  */
82 /*
83  * Field : SWR
84  *
85  * Software Reset
86  *
87  * When this bit is set, the MAC DMA Controller resets the logic and all internal
88  * registers of the MAC. It is cleared automatically after the reset operation has
89  * completed in all of the DWC_gmac clock domains. Before reprogramming any
90  * register of the DWC_gmac, you should read a zero (0) value in this bit .
91  *
92  * <b> Note: </b><br>
93  *
94  * * The Software reset function is driven only by this bit. Bit 0 of Register 64
95  * (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register)
96  * has no impact on the Software reset function.
97  *
98  * * The reset operation is completed only when all resets in all active clock
99  * domains are de-asserted. Therefore, it is essential that all the PHY inputs
100  * clocks (applicable for the selected PHY interface) are present for the
101  * software reset completion.
102  *
103  * Field Access Macros:
104  *
105  */
106 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MODE_SWR register field. */
107 #define ALT_EMAC_DMA_BUS_MODE_SWR_LSB 0
108 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MODE_SWR register field. */
109 #define ALT_EMAC_DMA_BUS_MODE_SWR_MSB 0
110 /* The width in bits of the ALT_EMAC_DMA_BUS_MODE_SWR register field. */
111 #define ALT_EMAC_DMA_BUS_MODE_SWR_WIDTH 1
112 /* The mask used to set the ALT_EMAC_DMA_BUS_MODE_SWR register field value. */
113 #define ALT_EMAC_DMA_BUS_MODE_SWR_SET_MSK 0x00000001
114 /* The mask used to clear the ALT_EMAC_DMA_BUS_MODE_SWR register field value. */
115 #define ALT_EMAC_DMA_BUS_MODE_SWR_CLR_MSK 0xfffffffe
116 /* The reset value of the ALT_EMAC_DMA_BUS_MODE_SWR register field. */
117 #define ALT_EMAC_DMA_BUS_MODE_SWR_RESET 0x1
118 /* Extracts the ALT_EMAC_DMA_BUS_MODE_SWR field value from a register. */
119 #define ALT_EMAC_DMA_BUS_MODE_SWR_GET(value) (((value) & 0x00000001) >> 0)
120 /* Produces a ALT_EMAC_DMA_BUS_MODE_SWR register field value suitable for setting the register. */
121 #define ALT_EMAC_DMA_BUS_MODE_SWR_SET(value) (((value) << 0) & 0x00000001)
122 
123 /*
124  * Field : DA
125  *
126  * DMA Arbitration Scheme
127  *
128  * This bit specifies the arbitration scheme between the transmit and receive paths
129  * of Channel 0.
130  *
131  * * 0: Weighted round-robin with Rx:Tx or Tx:Rx
132  *
133  * The priority between the paths is according to the priority specified in bits
134  * 15:14 (PR) and priority weights specified in Bit 27 (TXPR).
135  *
136  * * 1: Fixed priority
137  *
138  * The transmit path has priority over receive path when Bit 27 (TXPR) is set.
139  * Otherwise, receive path has priority over the transmit path.
140  *
141  * In the GMAC-AXI configuration, these bits are reserved and read-only (RO).
142  *
143  * Field Access Macros:
144  *
145  */
146 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MODE_DA register field. */
147 #define ALT_EMAC_DMA_BUS_MODE_DA_LSB 1
148 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MODE_DA register field. */
149 #define ALT_EMAC_DMA_BUS_MODE_DA_MSB 1
150 /* The width in bits of the ALT_EMAC_DMA_BUS_MODE_DA register field. */
151 #define ALT_EMAC_DMA_BUS_MODE_DA_WIDTH 1
152 /* The mask used to set the ALT_EMAC_DMA_BUS_MODE_DA register field value. */
153 #define ALT_EMAC_DMA_BUS_MODE_DA_SET_MSK 0x00000002
154 /* The mask used to clear the ALT_EMAC_DMA_BUS_MODE_DA register field value. */
155 #define ALT_EMAC_DMA_BUS_MODE_DA_CLR_MSK 0xfffffffd
156 /* The reset value of the ALT_EMAC_DMA_BUS_MODE_DA register field. */
157 #define ALT_EMAC_DMA_BUS_MODE_DA_RESET 0x0
158 /* Extracts the ALT_EMAC_DMA_BUS_MODE_DA field value from a register. */
159 #define ALT_EMAC_DMA_BUS_MODE_DA_GET(value) (((value) & 0x00000002) >> 1)
160 /* Produces a ALT_EMAC_DMA_BUS_MODE_DA register field value suitable for setting the register. */
161 #define ALT_EMAC_DMA_BUS_MODE_DA_SET(value) (((value) << 1) & 0x00000002)
162 
163 /*
164  * Field : DSL
165  *
166  * Descriptor Skip Length
167  *
168  * This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit,
169  * 64-bit, or 128-bit bus) to skip between two unchained descriptors. The address
170  * skipping starts from the end of current descriptor to the start of next
171  * descriptor. When the DSL value is equal to zero, the descriptor table is taken
172  * as contiguous by the DMA in Ring mode.
173  *
174  * Field Access Macros:
175  *
176  */
177 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MODE_DSL register field. */
178 #define ALT_EMAC_DMA_BUS_MODE_DSL_LSB 2
179 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MODE_DSL register field. */
180 #define ALT_EMAC_DMA_BUS_MODE_DSL_MSB 6
181 /* The width in bits of the ALT_EMAC_DMA_BUS_MODE_DSL register field. */
182 #define ALT_EMAC_DMA_BUS_MODE_DSL_WIDTH 5
183 /* The mask used to set the ALT_EMAC_DMA_BUS_MODE_DSL register field value. */
184 #define ALT_EMAC_DMA_BUS_MODE_DSL_SET_MSK 0x0000007c
185 /* The mask used to clear the ALT_EMAC_DMA_BUS_MODE_DSL register field value. */
186 #define ALT_EMAC_DMA_BUS_MODE_DSL_CLR_MSK 0xffffff83
187 /* The reset value of the ALT_EMAC_DMA_BUS_MODE_DSL register field. */
188 #define ALT_EMAC_DMA_BUS_MODE_DSL_RESET 0x0
189 /* Extracts the ALT_EMAC_DMA_BUS_MODE_DSL field value from a register. */
190 #define ALT_EMAC_DMA_BUS_MODE_DSL_GET(value) (((value) & 0x0000007c) >> 2)
191 /* Produces a ALT_EMAC_DMA_BUS_MODE_DSL register field value suitable for setting the register. */
192 #define ALT_EMAC_DMA_BUS_MODE_DSL_SET(value) (((value) << 2) & 0x0000007c)
193 
194 /*
195  * Field : ATDS
196  *
197  * Alternate Descriptor Size
198  *
199  * When set, the size of the alternate descriptor increases to 32 bytes (8 DWORDS).
200  * This is required when the Advanced Timestamp feature or the IPC Full Offload
201  * Engine (Type 2) is enabled in the receiver. The enhanced descriptor is not
202  * required if the Advanced Timestamp and IPC Full Checksum Offload (Type 2)
203  * features are not enabled. In such cases, you can use the 16 bytes descriptor to
204  * save 4 bytes of memory.
205  *
206  * This bit is present only when you select the Alternate Descriptor feature and
207  * any one of the following features during core configuration:
208  *
209  * * Advanced Timestamp feature
210  *
211  * * IPC Full Checksum Offload Engine (Type 2) feature
212  *
213  * Otherwise, this bit is reserved and read-only.
214  *
215  * When reset, the descriptor size reverts back to 4 DWORDs (16 bytes).
216  *
217  * This bit preserves the backward compatibility for the descriptor size. In
218  * versions prior to 3.50a, the descriptor size is 16 bytes for both normal and
219  * enhanced descriptor. In version 3.50a, descriptor size is increased to 32 bytes
220  * because of the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2)
221  * features.
222  *
223  * Field Access Macros:
224  *
225  */
226 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MODE_ATDS register field. */
227 #define ALT_EMAC_DMA_BUS_MODE_ATDS_LSB 7
228 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MODE_ATDS register field. */
229 #define ALT_EMAC_DMA_BUS_MODE_ATDS_MSB 7
230 /* The width in bits of the ALT_EMAC_DMA_BUS_MODE_ATDS register field. */
231 #define ALT_EMAC_DMA_BUS_MODE_ATDS_WIDTH 1
232 /* The mask used to set the ALT_EMAC_DMA_BUS_MODE_ATDS register field value. */
233 #define ALT_EMAC_DMA_BUS_MODE_ATDS_SET_MSK 0x00000080
234 /* The mask used to clear the ALT_EMAC_DMA_BUS_MODE_ATDS register field value. */
235 #define ALT_EMAC_DMA_BUS_MODE_ATDS_CLR_MSK 0xffffff7f
236 /* The reset value of the ALT_EMAC_DMA_BUS_MODE_ATDS register field. */
237 #define ALT_EMAC_DMA_BUS_MODE_ATDS_RESET 0x0
238 /* Extracts the ALT_EMAC_DMA_BUS_MODE_ATDS field value from a register. */
239 #define ALT_EMAC_DMA_BUS_MODE_ATDS_GET(value) (((value) & 0x00000080) >> 7)
240 /* Produces a ALT_EMAC_DMA_BUS_MODE_ATDS register field value suitable for setting the register. */
241 #define ALT_EMAC_DMA_BUS_MODE_ATDS_SET(value) (((value) << 7) & 0x00000080)
242 
243 /*
244  * Field : PBL
245  *
246  * Programmable Burst Length
247  *
248  * These bits indicate the maximum number of beats to be transferred in one DMA
249  * transaction. This is the maximum value that is used in a single block Read or
250  * Write. The DMA always attempts to burst as specified in PBL each time it starts
251  * a Burst transfer on the host bus. PBL can be programmed with permissible values
252  * of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. When
253  * USP is set high, this PBL value is applicable only for Tx DMA transactions.
254  *
255  * If the number of beats to be transferred is more than 32, then perform the
256  * following steps:
257  *
258  * 1. Set the PBLx8 mode. <br>
259  *
260  * 2. Set the PBL. <br>
261  *
262  * For example, if the maximum number of beats to be transferred is 64, then first
263  * set PBLx8 to 1 and then set PBL to 8. The PBL values have the following
264  * limitation: The maximum number of possible beats (PBL) is limited by the size of
265  * the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The
266  * FIFO has a constraint that the maximum beat supported is half the depth of the
267  * FIFO, except when specified.
268  *
269  * For different data bus widths and FIFO sizes, the valid PBL range (including x8
270  * mode) is provided in the following list. If the PBL is common for both transmit
271  * and receive DMA, the minimum Rx FIFO and Tx FIFO depths must be considered.
272  *
273  * Note: In the half-duplex mode, the valid PBL range specified in the following
274  * list is applicable only for Tx FIFO.
275  *
276  * * 32-Bit Data Bus Width
277  *
278  * - 128 Bytes FIFO Depth: In the full-duplex mode, the valid PBL range is 16
279  * or less. In the half-duplex mode, the valid PBL range is 8 or less for the
280  * 10 or 100 Mbps mode.
281  *
282  * - 256 Bytes FIFO Depth: In the full-duplex mode and the half-duplex (10 or
283  * 100 Mbps) modes, the valid PBL range is 32 or less.
284  *
285  * - 512 Bytes FIFO Depth: In the full-duplex mode and the half-duplex (10 or
286  * 100 Mbps) modes, the valid PBL range is 64 or less.
287  *
288  * - 1 KB FIFO Depth: In the full-duplex mode, the valid PBL range is 128 or
289  * less. In the half-duplex mode, the valid PBL range is 128 or less in the
290  * 10 or 100 Mbps mode and 64 or less in the 1000 Mbps mode.
291  *
292  * - 2 KB and Higher FIFO Depth: All PBL values are supported in the full-
293  * duplex mode and half-duplex modes.
294  *
295  * * 64-Bit Data Bus Width
296  *
297  * - 128 Bytes FIFO Depth: In the full-duplex mode, the valid PBL range is 8 or
298  * less. In the half-duplex mode, the valid PBL range is 4 or less for the 10
299  * or 100 Mbps mode.
300  *
301  * - 256 Bytes FIFO Depth: In the full-duplex mode and the half-duplex (10 or
302  * 100 Mbps) modes, the valid PBL range is 16 or less.
303  *
304  * - 512 Bytes FIFO Depth: In the full-duplex mode and the half-duplex (10 or
305  * 100 Mbps) modes, the valid PBL range is 32 or less.
306  *
307  * - 1 KB FIFO Depth: In the full-duplex mode, the valid PBL range is 64 or
308  * less. In the half-duplex mode, the valid PBL range is 64 or less in the 10
309  * or 100 Mbps mode and 32 or less in the 1000-Mbps mode.
310  *
311  * - 2 KB FIFO Depth: In the full-duplex mode and the half-duplex (10 or 100
312  * Mbps) modes, the valid PBL range is 128 or less.
313  *
314  * - 4 KB and Higher FIFO Depth: All PBL values are supported in the full-
315  * duplex and half-duplex modes.
316  *
317  * * 128-Bit Data Bus Width
318  *
319  * - 128 Bytes FIFO Depth: In the full-duplex mode, the valid PBL range is 4 or
320  * less. In the half-duplex mode, the valid PBL range is 2 or less for the 10
321  * or 100 Mbps mode.
322  *
323  * - 256 Bytes FIFO Depth: In the full-duplex mode and the half-duplex (10 or
324  * 100 Mbps) modes, the valid PBL range is 8 or less.
325  *
326  * - 512 Bytes FIFO Depth: In the full-duplex mode and the half-duplex (10 or
327  * 100 Mbps) modes, the valid PBL range is 16 or less.
328  *
329  * - 1 KB FIFO Depth: In the full-duplex mode, the valid PBL range is 32 or
330  * less. In the half-duplex mode, the valid PBL range is 32 or less in the 10
331  * or 100 Mbps mode and 16 or less in the 1000-Mbps mode.
332  *
333  * - 2 KB FIFO Depth: In the full-duplex mode and the half-duplex (10 or 100
334  * Mbps) modes, the valid PBL range is 64 or less.
335  *
336  * - 4 KB FIFO Depth: In the full-duplex mode and the half-duplex (10 or 100
337  * Mbps) modes, the valid PBL range is 128 or less.
338  *
339  * - 8 KB and Higher FIFO Depth: All PBL values are supported in the full-
340  * duplex and half-duplex modes.
341  *
342  * Field Access Macros:
343  *
344  */
345 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MODE_PBL register field. */
346 #define ALT_EMAC_DMA_BUS_MODE_PBL_LSB 8
347 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MODE_PBL register field. */
348 #define ALT_EMAC_DMA_BUS_MODE_PBL_MSB 13
349 /* The width in bits of the ALT_EMAC_DMA_BUS_MODE_PBL register field. */
350 #define ALT_EMAC_DMA_BUS_MODE_PBL_WIDTH 6
351 /* The mask used to set the ALT_EMAC_DMA_BUS_MODE_PBL register field value. */
352 #define ALT_EMAC_DMA_BUS_MODE_PBL_SET_MSK 0x00003f00
353 /* The mask used to clear the ALT_EMAC_DMA_BUS_MODE_PBL register field value. */
354 #define ALT_EMAC_DMA_BUS_MODE_PBL_CLR_MSK 0xffffc0ff
355 /* The reset value of the ALT_EMAC_DMA_BUS_MODE_PBL register field. */
356 #define ALT_EMAC_DMA_BUS_MODE_PBL_RESET 0x1
357 /* Extracts the ALT_EMAC_DMA_BUS_MODE_PBL field value from a register. */
358 #define ALT_EMAC_DMA_BUS_MODE_PBL_GET(value) (((value) & 0x00003f00) >> 8)
359 /* Produces a ALT_EMAC_DMA_BUS_MODE_PBL register field value suitable for setting the register. */
360 #define ALT_EMAC_DMA_BUS_MODE_PBL_SET(value) (((value) << 8) & 0x00003f00)
361 
362 /*
363  * Field : PR
364  *
365  * Priority Ratio
366  *
367  * These bits control the priority ratio in the weighted round-robin arbitration
368  * between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is
369  * reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR)
370  * is reset or set.
371  *
372  * * 00: The Priority Ratio is 1:1.
373  *
374  * * 01: The Priority Ratio is 2:1.
375  *
376  * * 10: The Priority Ratio is 3:1.
377  *
378  * * 11: The Priority Ratio is 4:1.
379  *
380  * In the GMAC-AXI configuration, these bits are reserved and read-only (RO).
381  *
382  * Field Access Macros:
383  *
384  */
385 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MODE_PR register field. */
386 #define ALT_EMAC_DMA_BUS_MODE_PR_LSB 14
387 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MODE_PR register field. */
388 #define ALT_EMAC_DMA_BUS_MODE_PR_MSB 15
389 /* The width in bits of the ALT_EMAC_DMA_BUS_MODE_PR register field. */
390 #define ALT_EMAC_DMA_BUS_MODE_PR_WIDTH 2
391 /* The mask used to set the ALT_EMAC_DMA_BUS_MODE_PR register field value. */
392 #define ALT_EMAC_DMA_BUS_MODE_PR_SET_MSK 0x0000c000
393 /* The mask used to clear the ALT_EMAC_DMA_BUS_MODE_PR register field value. */
394 #define ALT_EMAC_DMA_BUS_MODE_PR_CLR_MSK 0xffff3fff
395 /* The reset value of the ALT_EMAC_DMA_BUS_MODE_PR register field. */
396 #define ALT_EMAC_DMA_BUS_MODE_PR_RESET 0x0
397 /* Extracts the ALT_EMAC_DMA_BUS_MODE_PR field value from a register. */
398 #define ALT_EMAC_DMA_BUS_MODE_PR_GET(value) (((value) & 0x0000c000) >> 14)
399 /* Produces a ALT_EMAC_DMA_BUS_MODE_PR register field value suitable for setting the register. */
400 #define ALT_EMAC_DMA_BUS_MODE_PR_SET(value) (((value) << 14) & 0x0000c000)
401 
402 /*
403  * Field : FB
404  *
405  * Fixed Burst
406  *
407  * This bit controls whether the AHB or AXI Master interface performs fixed burst
408  * transfers or not. When set, the AHB interface uses only SINGLE, INCR4, INCR8, or
409  * INCR16 during start of the normal burst transfers. When reset, the AHB or AXI
410  * interface uses SINGLE and INCR burst transfer operations.
411  *
412  * For more information, see Bit 0 (UNDEF) of the AXI Bus Mode register in the
413  * GMAC-AXI configuration.
414  *
415  * Field Access Macros:
416  *
417  */
418 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MODE_FB register field. */
419 #define ALT_EMAC_DMA_BUS_MODE_FB_LSB 16
420 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MODE_FB register field. */
421 #define ALT_EMAC_DMA_BUS_MODE_FB_MSB 16
422 /* The width in bits of the ALT_EMAC_DMA_BUS_MODE_FB register field. */
423 #define ALT_EMAC_DMA_BUS_MODE_FB_WIDTH 1
424 /* The mask used to set the ALT_EMAC_DMA_BUS_MODE_FB register field value. */
425 #define ALT_EMAC_DMA_BUS_MODE_FB_SET_MSK 0x00010000
426 /* The mask used to clear the ALT_EMAC_DMA_BUS_MODE_FB register field value. */
427 #define ALT_EMAC_DMA_BUS_MODE_FB_CLR_MSK 0xfffeffff
428 /* The reset value of the ALT_EMAC_DMA_BUS_MODE_FB register field. */
429 #define ALT_EMAC_DMA_BUS_MODE_FB_RESET 0x0
430 /* Extracts the ALT_EMAC_DMA_BUS_MODE_FB field value from a register. */
431 #define ALT_EMAC_DMA_BUS_MODE_FB_GET(value) (((value) & 0x00010000) >> 16)
432 /* Produces a ALT_EMAC_DMA_BUS_MODE_FB register field value suitable for setting the register. */
433 #define ALT_EMAC_DMA_BUS_MODE_FB_SET(value) (((value) << 16) & 0x00010000)
434 
435 /*
436  * Field : RPBL
437  *
438  * Rx DMA PBL
439  *
440  * This field indicates the maximum number of beats to be transferred in one Rx DMA
441  * transaction. This is the maximum value that is used in a single block Read or
442  * Write.
443  *
444  * The Rx DMA always attempts to burst as specified in the RPBL bit each time it
445  * starts a Burst transfer on the host bus. You can program RPBL with values of 1,
446  * 2, 4, 8, 16, and 32. Any other value results in undefined behavior.
447  *
448  * This field is valid and applicable only when USP is set high.
449  *
450  * Field Access Macros:
451  *
452  */
453 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MODE_RPBL register field. */
454 #define ALT_EMAC_DMA_BUS_MODE_RPBL_LSB 17
455 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MODE_RPBL register field. */
456 #define ALT_EMAC_DMA_BUS_MODE_RPBL_MSB 22
457 /* The width in bits of the ALT_EMAC_DMA_BUS_MODE_RPBL register field. */
458 #define ALT_EMAC_DMA_BUS_MODE_RPBL_WIDTH 6
459 /* The mask used to set the ALT_EMAC_DMA_BUS_MODE_RPBL register field value. */
460 #define ALT_EMAC_DMA_BUS_MODE_RPBL_SET_MSK 0x007e0000
461 /* The mask used to clear the ALT_EMAC_DMA_BUS_MODE_RPBL register field value. */
462 #define ALT_EMAC_DMA_BUS_MODE_RPBL_CLR_MSK 0xff81ffff
463 /* The reset value of the ALT_EMAC_DMA_BUS_MODE_RPBL register field. */
464 #define ALT_EMAC_DMA_BUS_MODE_RPBL_RESET 0x1
465 /* Extracts the ALT_EMAC_DMA_BUS_MODE_RPBL field value from a register. */
466 #define ALT_EMAC_DMA_BUS_MODE_RPBL_GET(value) (((value) & 0x007e0000) >> 17)
467 /* Produces a ALT_EMAC_DMA_BUS_MODE_RPBL register field value suitable for setting the register. */
468 #define ALT_EMAC_DMA_BUS_MODE_RPBL_SET(value) (((value) << 17) & 0x007e0000)
469 
470 /*
471  * Field : USP
472  *
473  * Use Seperate PBL
474  *
475  * When set high, this bit configures the Rx DMA to use the value configured in
476  * Bits[22:17] as PBL. The PBL value in Bits[13:8] is applicable only to the Tx DMA
477  * operations.
478  *
479  * When reset to low, the PBL value in Bits[13:8] is applicable for both DMA
480  * engines.
481  *
482  * Field Access Macros:
483  *
484  */
485 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MODE_USP register field. */
486 #define ALT_EMAC_DMA_BUS_MODE_USP_LSB 23
487 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MODE_USP register field. */
488 #define ALT_EMAC_DMA_BUS_MODE_USP_MSB 23
489 /* The width in bits of the ALT_EMAC_DMA_BUS_MODE_USP register field. */
490 #define ALT_EMAC_DMA_BUS_MODE_USP_WIDTH 1
491 /* The mask used to set the ALT_EMAC_DMA_BUS_MODE_USP register field value. */
492 #define ALT_EMAC_DMA_BUS_MODE_USP_SET_MSK 0x00800000
493 /* The mask used to clear the ALT_EMAC_DMA_BUS_MODE_USP register field value. */
494 #define ALT_EMAC_DMA_BUS_MODE_USP_CLR_MSK 0xff7fffff
495 /* The reset value of the ALT_EMAC_DMA_BUS_MODE_USP register field. */
496 #define ALT_EMAC_DMA_BUS_MODE_USP_RESET 0x0
497 /* Extracts the ALT_EMAC_DMA_BUS_MODE_USP field value from a register. */
498 #define ALT_EMAC_DMA_BUS_MODE_USP_GET(value) (((value) & 0x00800000) >> 23)
499 /* Produces a ALT_EMAC_DMA_BUS_MODE_USP register field value suitable for setting the register. */
500 #define ALT_EMAC_DMA_BUS_MODE_USP_SET(value) (((value) << 23) & 0x00800000)
501 
502 /*
503  * Field : PBLx8
504  *
505  * PBLx8 Mode
506  *
507  * When set high, this bit multiplies the programmed PBL value (Bits[22:17] and
508  * Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64,
509  * 128, and 256 beats depending on the PBL value.
510  *
511  * Note: This bit function is not backward compatible. Before release 3.50a, this
512  * bit was 4xPBL.
513  *
514  * Field Access Macros:
515  *
516  */
517 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MODE_PBLX8 register field. */
518 #define ALT_EMAC_DMA_BUS_MODE_PBLX8_LSB 24
519 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MODE_PBLX8 register field. */
520 #define ALT_EMAC_DMA_BUS_MODE_PBLX8_MSB 24
521 /* The width in bits of the ALT_EMAC_DMA_BUS_MODE_PBLX8 register field. */
522 #define ALT_EMAC_DMA_BUS_MODE_PBLX8_WIDTH 1
523 /* The mask used to set the ALT_EMAC_DMA_BUS_MODE_PBLX8 register field value. */
524 #define ALT_EMAC_DMA_BUS_MODE_PBLX8_SET_MSK 0x01000000
525 /* The mask used to clear the ALT_EMAC_DMA_BUS_MODE_PBLX8 register field value. */
526 #define ALT_EMAC_DMA_BUS_MODE_PBLX8_CLR_MSK 0xfeffffff
527 /* The reset value of the ALT_EMAC_DMA_BUS_MODE_PBLX8 register field. */
528 #define ALT_EMAC_DMA_BUS_MODE_PBLX8_RESET 0x0
529 /* Extracts the ALT_EMAC_DMA_BUS_MODE_PBLX8 field value from a register. */
530 #define ALT_EMAC_DMA_BUS_MODE_PBLX8_GET(value) (((value) & 0x01000000) >> 24)
531 /* Produces a ALT_EMAC_DMA_BUS_MODE_PBLX8 register field value suitable for setting the register. */
532 #define ALT_EMAC_DMA_BUS_MODE_PBLX8_SET(value) (((value) << 24) & 0x01000000)
533 
534 /*
535  * Field : AAL
536  *
537  * Address Aligned Beats
538  *
539  * When this bit is set high and the FB bit is equal to 1, the AHB or AXI interface
540  * generates all bursts aligned to the start address LS bits. If the FB bit is
541  * equal to 0, the first burst (accessing the data buffer's start address) is not
542  * aligned, but subsequent bursts are aligned to the address.
543  *
544  * This bit is valid only in the GMAC-AHB and GMAC-AXI configuration and is
545  * reserved (RO with default value 0) in all other configurations.
546  *
547  * Field Access Macros:
548  *
549  */
550 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MODE_AAL register field. */
551 #define ALT_EMAC_DMA_BUS_MODE_AAL_LSB 25
552 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MODE_AAL register field. */
553 #define ALT_EMAC_DMA_BUS_MODE_AAL_MSB 25
554 /* The width in bits of the ALT_EMAC_DMA_BUS_MODE_AAL register field. */
555 #define ALT_EMAC_DMA_BUS_MODE_AAL_WIDTH 1
556 /* The mask used to set the ALT_EMAC_DMA_BUS_MODE_AAL register field value. */
557 #define ALT_EMAC_DMA_BUS_MODE_AAL_SET_MSK 0x02000000
558 /* The mask used to clear the ALT_EMAC_DMA_BUS_MODE_AAL register field value. */
559 #define ALT_EMAC_DMA_BUS_MODE_AAL_CLR_MSK 0xfdffffff
560 /* The reset value of the ALT_EMAC_DMA_BUS_MODE_AAL register field. */
561 #define ALT_EMAC_DMA_BUS_MODE_AAL_RESET 0x0
562 /* Extracts the ALT_EMAC_DMA_BUS_MODE_AAL field value from a register. */
563 #define ALT_EMAC_DMA_BUS_MODE_AAL_GET(value) (((value) & 0x02000000) >> 25)
564 /* Produces a ALT_EMAC_DMA_BUS_MODE_AAL register field value suitable for setting the register. */
565 #define ALT_EMAC_DMA_BUS_MODE_AAL_SET(value) (((value) << 25) & 0x02000000)
566 
567 /*
568  * Field : MB
569  *
570  * Mixed Burst
571  *
572  * When this bit is set high and the FB bit is low, the AHB Master interface starts
573  * all bursts of length more than 16 with INCR (undefined burst) whereas it reverts
574  * to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less.
575  *
576  * This bit is valid only in the GMAC-AHB configuration and reserved in all other
577  * configuration.
578  *
579  * Field Access Macros:
580  *
581  */
582 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MODE_MB register field. */
583 #define ALT_EMAC_DMA_BUS_MODE_MB_LSB 26
584 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MODE_MB register field. */
585 #define ALT_EMAC_DMA_BUS_MODE_MB_MSB 26
586 /* The width in bits of the ALT_EMAC_DMA_BUS_MODE_MB register field. */
587 #define ALT_EMAC_DMA_BUS_MODE_MB_WIDTH 1
588 /* The mask used to set the ALT_EMAC_DMA_BUS_MODE_MB register field value. */
589 #define ALT_EMAC_DMA_BUS_MODE_MB_SET_MSK 0x04000000
590 /* The mask used to clear the ALT_EMAC_DMA_BUS_MODE_MB register field value. */
591 #define ALT_EMAC_DMA_BUS_MODE_MB_CLR_MSK 0xfbffffff
592 /* The reset value of the ALT_EMAC_DMA_BUS_MODE_MB register field. */
593 #define ALT_EMAC_DMA_BUS_MODE_MB_RESET 0x0
594 /* Extracts the ALT_EMAC_DMA_BUS_MODE_MB field value from a register. */
595 #define ALT_EMAC_DMA_BUS_MODE_MB_GET(value) (((value) & 0x04000000) >> 26)
596 /* Produces a ALT_EMAC_DMA_BUS_MODE_MB register field value suitable for setting the register. */
597 #define ALT_EMAC_DMA_BUS_MODE_MB_SET(value) (((value) << 26) & 0x04000000)
598 
599 /*
600  * Field : TXPR
601  *
602  * Transmit Priority
603  *
604  * When set, this bit indicates that the transmit DMA has higher priority than the
605  * receive DMA during arbitration for the system-side bus. In the GMAC-AXI
606  * configuration, this bit is reserved and read-only (RO).
607  *
608  * Field Access Macros:
609  *
610  */
611 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MODE_TXPR register field. */
612 #define ALT_EMAC_DMA_BUS_MODE_TXPR_LSB 27
613 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MODE_TXPR register field. */
614 #define ALT_EMAC_DMA_BUS_MODE_TXPR_MSB 27
615 /* The width in bits of the ALT_EMAC_DMA_BUS_MODE_TXPR register field. */
616 #define ALT_EMAC_DMA_BUS_MODE_TXPR_WIDTH 1
617 /* The mask used to set the ALT_EMAC_DMA_BUS_MODE_TXPR register field value. */
618 #define ALT_EMAC_DMA_BUS_MODE_TXPR_SET_MSK 0x08000000
619 /* The mask used to clear the ALT_EMAC_DMA_BUS_MODE_TXPR register field value. */
620 #define ALT_EMAC_DMA_BUS_MODE_TXPR_CLR_MSK 0xf7ffffff
621 /* The reset value of the ALT_EMAC_DMA_BUS_MODE_TXPR register field. */
622 #define ALT_EMAC_DMA_BUS_MODE_TXPR_RESET 0x0
623 /* Extracts the ALT_EMAC_DMA_BUS_MODE_TXPR field value from a register. */
624 #define ALT_EMAC_DMA_BUS_MODE_TXPR_GET(value) (((value) & 0x08000000) >> 27)
625 /* Produces a ALT_EMAC_DMA_BUS_MODE_TXPR register field value suitable for setting the register. */
626 #define ALT_EMAC_DMA_BUS_MODE_TXPR_SET(value) (((value) << 27) & 0x08000000)
627 
628 /*
629  * Field : PRWG
630  *
631  * Channel Priority Weights
632  *
633  * This field sets the priority weights for Channel 0 during the round-robin
634  * arbitration between the DMA channels for the system bus.
635  *
636  * * 00: The priority weight is 1.
637  *
638  * * 01: The priority weight is 2.
639  *
640  * * 10: The priority weight is 3.
641  *
642  * * 11: The priority weight is 4.
643  *
644  * This field is present in all DWC_gmac configurations except GMAC-AXI when you
645  * select the AV feature. Otherwise, this field is reserved and read-only (RO).
646  *
647  * Field Access Macros:
648  *
649  */
650 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MODE_PRWG register field. */
651 #define ALT_EMAC_DMA_BUS_MODE_PRWG_LSB 28
652 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MODE_PRWG register field. */
653 #define ALT_EMAC_DMA_BUS_MODE_PRWG_MSB 29
654 /* The width in bits of the ALT_EMAC_DMA_BUS_MODE_PRWG register field. */
655 #define ALT_EMAC_DMA_BUS_MODE_PRWG_WIDTH 2
656 /* The mask used to set the ALT_EMAC_DMA_BUS_MODE_PRWG register field value. */
657 #define ALT_EMAC_DMA_BUS_MODE_PRWG_SET_MSK 0x30000000
658 /* The mask used to clear the ALT_EMAC_DMA_BUS_MODE_PRWG register field value. */
659 #define ALT_EMAC_DMA_BUS_MODE_PRWG_CLR_MSK 0xcfffffff
660 /* The reset value of the ALT_EMAC_DMA_BUS_MODE_PRWG register field. */
661 #define ALT_EMAC_DMA_BUS_MODE_PRWG_RESET 0x0
662 /* Extracts the ALT_EMAC_DMA_BUS_MODE_PRWG field value from a register. */
663 #define ALT_EMAC_DMA_BUS_MODE_PRWG_GET(value) (((value) & 0x30000000) >> 28)
664 /* Produces a ALT_EMAC_DMA_BUS_MODE_PRWG register field value suitable for setting the register. */
665 #define ALT_EMAC_DMA_BUS_MODE_PRWG_SET(value) (((value) << 28) & 0x30000000)
666 
667 /*
668  * Field : Reserved_30
669  *
670  * Reserved
671  *
672  * Field Access Macros:
673  *
674  */
675 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MODE_RESERVED_30 register field. */
676 #define ALT_EMAC_DMA_BUS_MODE_RESERVED_30_LSB 30
677 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MODE_RESERVED_30 register field. */
678 #define ALT_EMAC_DMA_BUS_MODE_RESERVED_30_MSB 30
679 /* The width in bits of the ALT_EMAC_DMA_BUS_MODE_RESERVED_30 register field. */
680 #define ALT_EMAC_DMA_BUS_MODE_RESERVED_30_WIDTH 1
681 /* The mask used to set the ALT_EMAC_DMA_BUS_MODE_RESERVED_30 register field value. */
682 #define ALT_EMAC_DMA_BUS_MODE_RESERVED_30_SET_MSK 0x40000000
683 /* The mask used to clear the ALT_EMAC_DMA_BUS_MODE_RESERVED_30 register field value. */
684 #define ALT_EMAC_DMA_BUS_MODE_RESERVED_30_CLR_MSK 0xbfffffff
685 /* The reset value of the ALT_EMAC_DMA_BUS_MODE_RESERVED_30 register field. */
686 #define ALT_EMAC_DMA_BUS_MODE_RESERVED_30_RESET 0x0
687 /* Extracts the ALT_EMAC_DMA_BUS_MODE_RESERVED_30 field value from a register. */
688 #define ALT_EMAC_DMA_BUS_MODE_RESERVED_30_GET(value) (((value) & 0x40000000) >> 30)
689 /* Produces a ALT_EMAC_DMA_BUS_MODE_RESERVED_30 register field value suitable for setting the register. */
690 #define ALT_EMAC_DMA_BUS_MODE_RESERVED_30_SET(value) (((value) << 30) & 0x40000000)
691 
692 /*
693  * Field : RIB
694  *
695  * Rebuild INCRx Burst
696  *
697  * When this bit is set high and the AHB master gets an EBT (Retry, Split, or
698  * Losing bus grant), the AHB master interface rebuilds the pending beats of any
699  * burst transfer initiated with INCRx. The AHB master interface rebuilds the beats
700  * with a combination of specified bursts with INCRx and SINGLE. By default, the
701  * AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR)
702  * burst.
703  *
704  * This bit is valid only in the GMAC-AHB configuration. It is reserved in all
705  * other configuration.
706  *
707  * Field Access Macros:
708  *
709  */
710 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MODE_RIB register field. */
711 #define ALT_EMAC_DMA_BUS_MODE_RIB_LSB 31
712 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MODE_RIB register field. */
713 #define ALT_EMAC_DMA_BUS_MODE_RIB_MSB 31
714 /* The width in bits of the ALT_EMAC_DMA_BUS_MODE_RIB register field. */
715 #define ALT_EMAC_DMA_BUS_MODE_RIB_WIDTH 1
716 /* The mask used to set the ALT_EMAC_DMA_BUS_MODE_RIB register field value. */
717 #define ALT_EMAC_DMA_BUS_MODE_RIB_SET_MSK 0x80000000
718 /* The mask used to clear the ALT_EMAC_DMA_BUS_MODE_RIB register field value. */
719 #define ALT_EMAC_DMA_BUS_MODE_RIB_CLR_MSK 0x7fffffff
720 /* The reset value of the ALT_EMAC_DMA_BUS_MODE_RIB register field. */
721 #define ALT_EMAC_DMA_BUS_MODE_RIB_RESET 0x0
722 /* Extracts the ALT_EMAC_DMA_BUS_MODE_RIB field value from a register. */
723 #define ALT_EMAC_DMA_BUS_MODE_RIB_GET(value) (((value) & 0x80000000) >> 31)
724 /* Produces a ALT_EMAC_DMA_BUS_MODE_RIB register field value suitable for setting the register. */
725 #define ALT_EMAC_DMA_BUS_MODE_RIB_SET(value) (((value) << 31) & 0x80000000)
726 
727 #ifndef __ASSEMBLY__
728 /*
729  * WARNING: The C register and register group struct declarations are provided for
730  * convenience and illustrative purposes. They should, however, be used with
731  * caution as the C language standard provides no guarantees about the alignment or
732  * atomicity of device memory accesses. The recommended practice for writing
733  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
734  * alt_write_word() functions.
735  *
736  * The struct declaration for register ALT_EMAC_DMA_BUS_MODE.
737  */
738 struct ALT_EMAC_DMA_BUS_MODE_s
739 {
740  volatile uint32_t SWR : 1; /* ALT_EMAC_DMA_BUS_MODE_SWR */
741  const volatile uint32_t DA : 1; /* ALT_EMAC_DMA_BUS_MODE_DA */
742  volatile uint32_t DSL : 5; /* ALT_EMAC_DMA_BUS_MODE_DSL */
743  volatile uint32_t ATDS : 1; /* ALT_EMAC_DMA_BUS_MODE_ATDS */
744  volatile uint32_t PBL : 6; /* ALT_EMAC_DMA_BUS_MODE_PBL */
745  const volatile uint32_t PR : 2; /* ALT_EMAC_DMA_BUS_MODE_PR */
746  volatile uint32_t FB : 1; /* ALT_EMAC_DMA_BUS_MODE_FB */
747  volatile uint32_t RPBL : 6; /* ALT_EMAC_DMA_BUS_MODE_RPBL */
748  volatile uint32_t USP : 1; /* ALT_EMAC_DMA_BUS_MODE_USP */
749  volatile uint32_t PBLx8 : 1; /* ALT_EMAC_DMA_BUS_MODE_PBLX8 */
750  volatile uint32_t AAL : 1; /* ALT_EMAC_DMA_BUS_MODE_AAL */
751  const volatile uint32_t MB : 1; /* ALT_EMAC_DMA_BUS_MODE_MB */
752  const volatile uint32_t TXPR : 1; /* ALT_EMAC_DMA_BUS_MODE_TXPR */
753  const volatile uint32_t PRWG : 2; /* ALT_EMAC_DMA_BUS_MODE_PRWG */
754  const volatile uint32_t Reserved_30 : 1; /* ALT_EMAC_DMA_BUS_MODE_RESERVED_30 */
755  const volatile uint32_t RIB : 1; /* ALT_EMAC_DMA_BUS_MODE_RIB */
756 };
757 
758 /* The typedef declaration for register ALT_EMAC_DMA_BUS_MODE. */
759 typedef struct ALT_EMAC_DMA_BUS_MODE_s ALT_EMAC_DMA_BUS_MODE_t;
760 #endif /* __ASSEMBLY__ */
761 
762 /* The reset value of the ALT_EMAC_DMA_BUS_MODE register. */
763 #define ALT_EMAC_DMA_BUS_MODE_RESET 0x00020101
764 /* The byte offset of the ALT_EMAC_DMA_BUS_MODE register from the beginning of the component. */
765 #define ALT_EMAC_DMA_BUS_MODE_OFST 0x0
766 /* The address of the ALT_EMAC_DMA_BUS_MODE register. */
767 #define ALT_EMAC_DMA_BUS_MODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_BUS_MODE_OFST))
768 
769 /*
770  * Register : Transmit_Poll_Demand
771  *
772  * <b> Register 1 (Transmit Poll Demand Register) </b>
773  *
774  * The Transmit Poll Demand register enables the Tx DMA to check whether or not the
775  * DMA owns the current descriptor. The Transmit Poll Demand command is given to
776  * wake up the Tx DMA if it is in the Suspend mode. The Tx DMA can go into the
777  * Suspend mode because of an Underflow error in a transmitted frame or the
778  * unavailability of descriptors owned by it. You can give this command anytime and
779  * the Tx DMA resets this command when it again starts fetching the current
780  * descriptor from host memory. When this register is read, it always returns zero.
781  *
782  * Register Layout
783  *
784  * Bits | Access | Reset | Description
785  * :-------|:-------|:------|:--------------------------------------
786  * [31:0] | RW | 0x0 | ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD
787  *
788  */
789 /*
790  * Field : TPD
791  *
792  * Transmit Poll Demand
793  *
794  * When these bits are written with any value, the DMA reads the current descriptor
795  * pointed to by Register 18 (Current Host Transmit Descriptor Register). If that
796  * descriptor is not available (owned by the Host), the transmission returns to the
797  * Suspend state and the Bit 2 (TU) of Register 5 (Status Register) is asserted. If
798  * the descriptor is available, the transmission resumes.
799  *
800  * Field Access Macros:
801  *
802  */
803 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD register field. */
804 #define ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD_LSB 0
805 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD register field. */
806 #define ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD_MSB 31
807 /* The width in bits of the ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD register field. */
808 #define ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD_WIDTH 32
809 /* The mask used to set the ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD register field value. */
810 #define ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD_SET_MSK 0xffffffff
811 /* The mask used to clear the ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD register field value. */
812 #define ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD_CLR_MSK 0x00000000
813 /* The reset value of the ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD register field. */
814 #define ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD_RESET 0x0
815 /* Extracts the ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD field value from a register. */
816 #define ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD_GET(value) (((value) & 0xffffffff) >> 0)
817 /* Produces a ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD register field value suitable for setting the register. */
818 #define ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD_SET(value) (((value) << 0) & 0xffffffff)
819 
820 #ifndef __ASSEMBLY__
821 /*
822  * WARNING: The C register and register group struct declarations are provided for
823  * convenience and illustrative purposes. They should, however, be used with
824  * caution as the C language standard provides no guarantees about the alignment or
825  * atomicity of device memory accesses. The recommended practice for writing
826  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
827  * alt_write_word() functions.
828  *
829  * The struct declaration for register ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND.
830  */
831 struct ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_s
832 {
833  volatile uint32_t TPD : 32; /* ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD */
834 };
835 
836 /* The typedef declaration for register ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND. */
837 typedef struct ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_s ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_t;
838 #endif /* __ASSEMBLY__ */
839 
840 /* The reset value of the ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND register. */
841 #define ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_RESET 0x00000000
842 /* The byte offset of the ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND register from the beginning of the component. */
843 #define ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_OFST 0x4
844 /* The address of the ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND register. */
845 #define ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_OFST))
846 
847 /*
848  * Register : Receive_Poll_Demand
849  *
850  * <b>Register 2 (Receive Poll Demand Register) </b>
851  *
852  * The Receive Poll Demand register enables the receive DMA to check for new
853  * descriptors. This command is used to wake up the Rx DMA from the SUSPEND state.
854  * The RxDMA can go into the SUSPEND state only because of the unavailability of
855  * descriptors it owns. When this register is read, it always returns zero.
856  *
857  * Register Layout
858  *
859  * Bits | Access | Reset | Description
860  * :-------|:-------|:------|:-------------------------------------
861  * [31:0] | RW | 0x0 | ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD
862  *
863  */
864 /*
865  * Field : RPD
866  *
867  * Receive Poll Demand
868  *
869  * When these bits are written with any value, the DMA reads the current descriptor
870  * pointed to by Register 19 (Current Host Receive Descriptor Register). If that
871  * descriptor is not available (owned by the Host), the reception returns to the
872  * Suspended state and the Bit 7 (RU) of Register 5 (Status Register) is not
873  * asserted. If the descriptor is available, the Rx DMA returns to the active
874  * state.
875  *
876  * Field Access Macros:
877  *
878  */
879 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD register field. */
880 #define ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD_LSB 0
881 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD register field. */
882 #define ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD_MSB 31
883 /* The width in bits of the ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD register field. */
884 #define ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD_WIDTH 32
885 /* The mask used to set the ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD register field value. */
886 #define ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD_SET_MSK 0xffffffff
887 /* The mask used to clear the ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD register field value. */
888 #define ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD_CLR_MSK 0x00000000
889 /* The reset value of the ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD register field. */
890 #define ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD_RESET 0x0
891 /* Extracts the ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD field value from a register. */
892 #define ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD_GET(value) (((value) & 0xffffffff) >> 0)
893 /* Produces a ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD register field value suitable for setting the register. */
894 #define ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD_SET(value) (((value) << 0) & 0xffffffff)
895 
896 #ifndef __ASSEMBLY__
897 /*
898  * WARNING: The C register and register group struct declarations are provided for
899  * convenience and illustrative purposes. They should, however, be used with
900  * caution as the C language standard provides no guarantees about the alignment or
901  * atomicity of device memory accesses. The recommended practice for writing
902  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
903  * alt_write_word() functions.
904  *
905  * The struct declaration for register ALT_EMAC_DMA_RECEIVE_POLL_DEMAND.
906  */
907 struct ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_s
908 {
909  volatile uint32_t RPD : 32; /* ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD */
910 };
911 
912 /* The typedef declaration for register ALT_EMAC_DMA_RECEIVE_POLL_DEMAND. */
913 typedef struct ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_s ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_t;
914 #endif /* __ASSEMBLY__ */
915 
916 /* The reset value of the ALT_EMAC_DMA_RECEIVE_POLL_DEMAND register. */
917 #define ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RESET 0x00000000
918 /* The byte offset of the ALT_EMAC_DMA_RECEIVE_POLL_DEMAND register from the beginning of the component. */
919 #define ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_OFST 0x8
920 /* The address of the ALT_EMAC_DMA_RECEIVE_POLL_DEMAND register. */
921 #define ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_OFST))
922 
923 /*
924  * Register : Receive_Descriptor_List_Address
925  *
926  * <b>Register 3 (Receive Descriptor List Address Register) </b>
927  *
928  * The Receive Descriptor List Address register points to the start of the Receive
929  * Descriptor List. The descriptor lists reside in the host's physical memory space
930  * and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or 128-bit data
931  * bus). The DMA internally converts it to bus width aligned address by making the
932  * corresponding LS bits low. Writing to this register is permitted only when
933  * reception is stopped. When stopped, this register must be written to before the
934  * receive Start command is given.
935  *
936  * You can write to this register only when Rx DMA has stopped, that is, Bit 1 (SR)
937  * is set to zero in Register 6 (Operation Mode Register). When stopped, this
938  * register can be written with a new descriptor list address. When you set the SR
939  * bit to 1, the DMA takes the newly programmed descriptor base address.
940  *
941  * If this register is not changed when the SR bit is set to 0, then the DMA takes
942  * the descriptor address where it was stopped earlier.
943  *
944  * Register Layout
945  *
946  * Bits | Access | Reset | Description
947  * :-------|:-------|:------|:----------------------------------------------------------
948  * [1:0] | R | 0x0 | ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0
949  * [31:2] | RW | 0x0 | ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT
950  *
951  */
952 /*
953  * Field : Reserved_1_0
954  *
955  * Reserved
956  *
957  * Field Access Macros:
958  *
959  */
960 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0 register field. */
961 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_LSB 0
962 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0 register field. */
963 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_MSB 1
964 /* The width in bits of the ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0 register field. */
965 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_WIDTH 2
966 /* The mask used to set the ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0 register field value. */
967 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_SET_MSK 0x00000003
968 /* The mask used to clear the ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0 register field value. */
969 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_CLR_MSK 0xfffffffc
970 /* The reset value of the ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0 register field. */
971 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_RESET 0x0
972 /* Extracts the ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0 field value from a register. */
973 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_GET(value) (((value) & 0x00000003) >> 0)
974 /* Produces a ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0 register field value suitable for setting the register. */
975 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_SET(value) (((value) << 0) & 0x00000003)
976 
977 /*
978  * Field : RDESLA_32bit
979  *
980  * Start of Receive List
981  *
982  * This field contains the base address of the first descriptor in the Receive
983  * Descriptor list. The LSB bits (1:0) for 32-bit bus width are ignored and
984  * internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only
985  * (RO).
986  *
987  * Field Access Macros:
988  *
989  */
990 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT register field. */
991 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT_LSB 2
992 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT register field. */
993 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT_MSB 31
994 /* The width in bits of the ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT register field. */
995 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT_WIDTH 30
996 /* The mask used to set the ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT register field value. */
997 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT_SET_MSK 0xfffffffc
998 /* The mask used to clear the ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT register field value. */
999 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT_CLR_MSK 0x00000003
1000 /* The reset value of the ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT register field. */
1001 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT_RESET 0x0
1002 /* Extracts the ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT field value from a register. */
1003 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT_GET(value) (((value) & 0xfffffffc) >> 2)
1004 /* Produces a ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT register field value suitable for setting the register. */
1005 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT_SET(value) (((value) << 2) & 0xfffffffc)
1006 
1007 #ifndef __ASSEMBLY__
1008 /*
1009  * WARNING: The C register and register group struct declarations are provided for
1010  * convenience and illustrative purposes. They should, however, be used with
1011  * caution as the C language standard provides no guarantees about the alignment or
1012  * atomicity of device memory accesses. The recommended practice for writing
1013  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1014  * alt_write_word() functions.
1015  *
1016  * The struct declaration for register ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS.
1017  */
1018 struct ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_s
1019 {
1020  const volatile uint32_t Reserved_1_0 : 2; /* ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0 */
1021  volatile uint32_t RDESLA_32bit : 30; /* ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT */
1022 };
1023 
1024 /* The typedef declaration for register ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS. */
1025 typedef struct ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_s ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_t;
1026 #endif /* __ASSEMBLY__ */
1027 
1028 /* The reset value of the ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS register. */
1029 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESET 0x00000000
1030 /* The byte offset of the ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS register from the beginning of the component. */
1031 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_OFST 0xc
1032 /* The address of the ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS register. */
1033 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_OFST))
1034 
1035 /*
1036  * Register : Transmit_Descriptor_List_Address
1037  *
1038  * <b>Register 4 (Transmit Descriptor List Address Register)</b>
1039  *
1040  * The Transmit Descriptor List Address register points to the start of the
1041  * Transmit Descriptor List. The descriptor lists reside in the host's physical
1042  * memory space and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or
1043  * 128-bit data bus). The DMA internally converts it to bus width aligned address
1044  * by making the corresponding LSB to low.
1045  *
1046  * You can write to this register only when the Tx DMA has stopped, that is, Bit 13
1047  * (ST) is set to zero in Register 6 (Operation Mode Register). When stopped, this
1048  * register can be written with a new descriptor list address. When you set the ST
1049  * bit to 1, the DMA takes the newly programmed descriptor base address.
1050  *
1051  * If this register is not changed when the ST bit is set to 0, then the DMA takes
1052  * the descriptor address where it was stopped earlier.
1053  *
1054  * Register Layout
1055  *
1056  * Bits | Access | Reset | Description
1057  * :-------|:-------|:------|:-----------------------------------------------------------
1058  * [1:0] | R | 0x0 | ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0
1059  * [31:2] | RW | 0x0 | ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT
1060  *
1061  */
1062 /*
1063  * Field : Reserved_1_0
1064  *
1065  * Reserved
1066  *
1067  * Field Access Macros:
1068  *
1069  */
1070 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0 register field. */
1071 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_LSB 0
1072 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0 register field. */
1073 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_MSB 1
1074 /* The width in bits of the ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0 register field. */
1075 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_WIDTH 2
1076 /* The mask used to set the ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0 register field value. */
1077 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_SET_MSK 0x00000003
1078 /* The mask used to clear the ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0 register field value. */
1079 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_CLR_MSK 0xfffffffc
1080 /* The reset value of the ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0 register field. */
1081 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_RESET 0x0
1082 /* Extracts the ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0 field value from a register. */
1083 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_GET(value) (((value) & 0x00000003) >> 0)
1084 /* Produces a ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0 register field value suitable for setting the register. */
1085 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_SET(value) (((value) << 0) & 0x00000003)
1086 
1087 /*
1088  * Field : TDESLA_32bit
1089  *
1090  * Start of Transmit List
1091  *
1092  * This field contains the base address of the first descriptor in the Transmit
1093  * Descriptor list. The LSB bits (1:0) for 32-bit bus width are ignored and are
1094  * internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only
1095  * (RO).
1096  *
1097  * Field Access Macros:
1098  *
1099  */
1100 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT register field. */
1101 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT_LSB 2
1102 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT register field. */
1103 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT_MSB 31
1104 /* The width in bits of the ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT register field. */
1105 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT_WIDTH 30
1106 /* The mask used to set the ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT register field value. */
1107 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT_SET_MSK 0xfffffffc
1108 /* The mask used to clear the ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT register field value. */
1109 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT_CLR_MSK 0x00000003
1110 /* The reset value of the ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT register field. */
1111 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT_RESET 0x0
1112 /* Extracts the ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT field value from a register. */
1113 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT_GET(value) (((value) & 0xfffffffc) >> 2)
1114 /* Produces a ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT register field value suitable for setting the register. */
1115 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT_SET(value) (((value) << 2) & 0xfffffffc)
1116 
1117 #ifndef __ASSEMBLY__
1118 /*
1119  * WARNING: The C register and register group struct declarations are provided for
1120  * convenience and illustrative purposes. They should, however, be used with
1121  * caution as the C language standard provides no guarantees about the alignment or
1122  * atomicity of device memory accesses. The recommended practice for writing
1123  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1124  * alt_write_word() functions.
1125  *
1126  * The struct declaration for register ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS.
1127  */
1128 struct ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_s
1129 {
1130  const volatile uint32_t Reserved_1_0 : 2; /* ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0 */
1131  volatile uint32_t TDESLA_32bit : 30; /* ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT */
1132 };
1133 
1134 /* The typedef declaration for register ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS. */
1135 typedef struct ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_s ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_t;
1136 #endif /* __ASSEMBLY__ */
1137 
1138 /* The reset value of the ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS register. */
1139 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESET 0x00000000
1140 /* The byte offset of the ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS register from the beginning of the component. */
1141 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_OFST 0x10
1142 /* The address of the ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS register. */
1143 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_OFST))
1144 
1145 /*
1146  * Register : Status
1147  *
1148  * <b>Register 5 (Status Register) </b>
1149  *
1150  * The Status register contains all status bits that the DMA reports to the host.
1151  * The Software driver reads this register during an interrupt service routine or
1152  * polling. Most of the fields in this register cause the host to be interrupted.
1153  * The bits of this register are not cleared when read. Writing 1'b1 to
1154  * (unreserved) Bits[16:0] of this register clears these bits and writing 1'b0 has
1155  * no effect. Each field (Bits[16:0]) can be masked by masking the appropriate bit
1156  * in Register 7 (Interrupt Enable Register).
1157  *
1158  * Register Layout
1159  *
1160  * Bits | Access | Reset | Description
1161  * :--------|:-------|:------|:-----------------------------------
1162  * [0] | RW | 0x0 | ALT_EMAC_DMA_STATUS_TI
1163  * [1] | RW | 0x0 | ALT_EMAC_DMA_STATUS_TPS
1164  * [2] | RW | 0x0 | ALT_EMAC_DMA_STATUS_TU
1165  * [3] | RW | 0x0 | ALT_EMAC_DMA_STATUS_TJT
1166  * [4] | RW | 0x0 | ALT_EMAC_DMA_STATUS_OVF
1167  * [5] | RW | 0x0 | ALT_EMAC_DMA_STATUS_UNF
1168  * [6] | RW | 0x0 | ALT_EMAC_DMA_STATUS_RI
1169  * [7] | RW | 0x0 | ALT_EMAC_DMA_STATUS_RU
1170  * [8] | RW | 0x0 | ALT_EMAC_DMA_STATUS_RPS
1171  * [9] | RW | 0x0 | ALT_EMAC_DMA_STATUS_RWT
1172  * [10] | RW | 0x0 | ALT_EMAC_DMA_STATUS_ETI
1173  * [12:11] | R | 0x0 | ALT_EMAC_DMA_STATUS_RESERVED_12_11
1174  * [13] | RW | 0x0 | ALT_EMAC_DMA_STATUS_FBI
1175  * [14] | RW | 0x0 | ALT_EMAC_DMA_STATUS_ERI
1176  * [15] | RW | 0x0 | ALT_EMAC_DMA_STATUS_AIS
1177  * [16] | RW | 0x0 | ALT_EMAC_DMA_STATUS_NIS
1178  * [19:17] | R | 0x0 | ALT_EMAC_DMA_STATUS_RS
1179  * [22:20] | R | 0x0 | ALT_EMAC_DMA_STATUS_TS
1180  * [25:23] | R | 0x0 | ALT_EMAC_DMA_STATUS_EB
1181  * [26] | R | 0x0 | ALT_EMAC_DMA_STATUS_GLI
1182  * [27] | R | 0x0 | ALT_EMAC_DMA_STATUS_GMI
1183  * [28] | R | 0x0 | ALT_EMAC_DMA_STATUS_GPI
1184  * [29] | R | 0x0 | ALT_EMAC_DMA_STATUS_TTI
1185  * [30] | R | 0x0 | ALT_EMAC_DMA_STATUS_GLPII
1186  * [31] | R | 0x0 | ALT_EMAC_DMA_STATUS_RESERVED_31
1187  *
1188  */
1189 /*
1190  * Field : TI
1191  *
1192  * Transmit Interrupt
1193  *
1194  * This bit indicates that the frame transmission is complete. When transmission is
1195  * complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status
1196  * information is updated in the descriptor.
1197  *
1198  * Field Access Macros:
1199  *
1200  */
1201 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_TI register field. */
1202 #define ALT_EMAC_DMA_STATUS_TI_LSB 0
1203 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_TI register field. */
1204 #define ALT_EMAC_DMA_STATUS_TI_MSB 0
1205 /* The width in bits of the ALT_EMAC_DMA_STATUS_TI register field. */
1206 #define ALT_EMAC_DMA_STATUS_TI_WIDTH 1
1207 /* The mask used to set the ALT_EMAC_DMA_STATUS_TI register field value. */
1208 #define ALT_EMAC_DMA_STATUS_TI_SET_MSK 0x00000001
1209 /* The mask used to clear the ALT_EMAC_DMA_STATUS_TI register field value. */
1210 #define ALT_EMAC_DMA_STATUS_TI_CLR_MSK 0xfffffffe
1211 /* The reset value of the ALT_EMAC_DMA_STATUS_TI register field. */
1212 #define ALT_EMAC_DMA_STATUS_TI_RESET 0x0
1213 /* Extracts the ALT_EMAC_DMA_STATUS_TI field value from a register. */
1214 #define ALT_EMAC_DMA_STATUS_TI_GET(value) (((value) & 0x00000001) >> 0)
1215 /* Produces a ALT_EMAC_DMA_STATUS_TI register field value suitable for setting the register. */
1216 #define ALT_EMAC_DMA_STATUS_TI_SET(value) (((value) << 0) & 0x00000001)
1217 
1218 /*
1219  * Field : TPS
1220  *
1221  * Transmit Process Stopped
1222  *
1223  * This bit is set when the transmission is stopped.
1224  *
1225  * Field Access Macros:
1226  *
1227  */
1228 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_TPS register field. */
1229 #define ALT_EMAC_DMA_STATUS_TPS_LSB 1
1230 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_TPS register field. */
1231 #define ALT_EMAC_DMA_STATUS_TPS_MSB 1
1232 /* The width in bits of the ALT_EMAC_DMA_STATUS_TPS register field. */
1233 #define ALT_EMAC_DMA_STATUS_TPS_WIDTH 1
1234 /* The mask used to set the ALT_EMAC_DMA_STATUS_TPS register field value. */
1235 #define ALT_EMAC_DMA_STATUS_TPS_SET_MSK 0x00000002
1236 /* The mask used to clear the ALT_EMAC_DMA_STATUS_TPS register field value. */
1237 #define ALT_EMAC_DMA_STATUS_TPS_CLR_MSK 0xfffffffd
1238 /* The reset value of the ALT_EMAC_DMA_STATUS_TPS register field. */
1239 #define ALT_EMAC_DMA_STATUS_TPS_RESET 0x0
1240 /* Extracts the ALT_EMAC_DMA_STATUS_TPS field value from a register. */
1241 #define ALT_EMAC_DMA_STATUS_TPS_GET(value) (((value) & 0x00000002) >> 1)
1242 /* Produces a ALT_EMAC_DMA_STATUS_TPS register field value suitable for setting the register. */
1243 #define ALT_EMAC_DMA_STATUS_TPS_SET(value) (((value) << 1) & 0x00000002)
1244 
1245 /*
1246  * Field : TU
1247  *
1248  * Transmit Buffer Unavailable
1249  *
1250  * This bit indicates that the host owns the Next Descriptor in the Transmit List
1251  * and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain
1252  * the Transmit Process state transitions.
1253  *
1254  * To resume processing Transmit descriptors, the host should change the ownership
1255  * of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand
1256  * command.
1257  *
1258  * Field Access Macros:
1259  *
1260  */
1261 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_TU register field. */
1262 #define ALT_EMAC_DMA_STATUS_TU_LSB 2
1263 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_TU register field. */
1264 #define ALT_EMAC_DMA_STATUS_TU_MSB 2
1265 /* The width in bits of the ALT_EMAC_DMA_STATUS_TU register field. */
1266 #define ALT_EMAC_DMA_STATUS_TU_WIDTH 1
1267 /* The mask used to set the ALT_EMAC_DMA_STATUS_TU register field value. */
1268 #define ALT_EMAC_DMA_STATUS_TU_SET_MSK 0x00000004
1269 /* The mask used to clear the ALT_EMAC_DMA_STATUS_TU register field value. */
1270 #define ALT_EMAC_DMA_STATUS_TU_CLR_MSK 0xfffffffb
1271 /* The reset value of the ALT_EMAC_DMA_STATUS_TU register field. */
1272 #define ALT_EMAC_DMA_STATUS_TU_RESET 0x0
1273 /* Extracts the ALT_EMAC_DMA_STATUS_TU field value from a register. */
1274 #define ALT_EMAC_DMA_STATUS_TU_GET(value) (((value) & 0x00000004) >> 2)
1275 /* Produces a ALT_EMAC_DMA_STATUS_TU register field value suitable for setting the register. */
1276 #define ALT_EMAC_DMA_STATUS_TU_SET(value) (((value) << 2) & 0x00000004)
1277 
1278 /*
1279  * Field : TJT
1280  *
1281  * Transmit Jabber Timeout
1282  *
1283  * This bit indicates that the Transmit Jabber Timer expired, which happens when
1284  * the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled).
1285  * When the Jabber Timeout occurs, the transmission process is aborted and placed
1286  * in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to
1287  * assert.
1288  *
1289  * Field Access Macros:
1290  *
1291  */
1292 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_TJT register field. */
1293 #define ALT_EMAC_DMA_STATUS_TJT_LSB 3
1294 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_TJT register field. */
1295 #define ALT_EMAC_DMA_STATUS_TJT_MSB 3
1296 /* The width in bits of the ALT_EMAC_DMA_STATUS_TJT register field. */
1297 #define ALT_EMAC_DMA_STATUS_TJT_WIDTH 1
1298 /* The mask used to set the ALT_EMAC_DMA_STATUS_TJT register field value. */
1299 #define ALT_EMAC_DMA_STATUS_TJT_SET_MSK 0x00000008
1300 /* The mask used to clear the ALT_EMAC_DMA_STATUS_TJT register field value. */
1301 #define ALT_EMAC_DMA_STATUS_TJT_CLR_MSK 0xfffffff7
1302 /* The reset value of the ALT_EMAC_DMA_STATUS_TJT register field. */
1303 #define ALT_EMAC_DMA_STATUS_TJT_RESET 0x0
1304 /* Extracts the ALT_EMAC_DMA_STATUS_TJT field value from a register. */
1305 #define ALT_EMAC_DMA_STATUS_TJT_GET(value) (((value) & 0x00000008) >> 3)
1306 /* Produces a ALT_EMAC_DMA_STATUS_TJT register field value suitable for setting the register. */
1307 #define ALT_EMAC_DMA_STATUS_TJT_SET(value) (((value) << 3) & 0x00000008)
1308 
1309 /*
1310  * Field : OVF
1311  *
1312  * Receive Overflow
1313  *
1314  * This bit indicates that the Receive Buffer had an Overflow during frame
1315  * reception. If the partial frame is transferred to the application, the overflow
1316  * status is set in RDES0[11].
1317  *
1318  * Field Access Macros:
1319  *
1320  */
1321 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_OVF register field. */
1322 #define ALT_EMAC_DMA_STATUS_OVF_LSB 4
1323 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_OVF register field. */
1324 #define ALT_EMAC_DMA_STATUS_OVF_MSB 4
1325 /* The width in bits of the ALT_EMAC_DMA_STATUS_OVF register field. */
1326 #define ALT_EMAC_DMA_STATUS_OVF_WIDTH 1
1327 /* The mask used to set the ALT_EMAC_DMA_STATUS_OVF register field value. */
1328 #define ALT_EMAC_DMA_STATUS_OVF_SET_MSK 0x00000010
1329 /* The mask used to clear the ALT_EMAC_DMA_STATUS_OVF register field value. */
1330 #define ALT_EMAC_DMA_STATUS_OVF_CLR_MSK 0xffffffef
1331 /* The reset value of the ALT_EMAC_DMA_STATUS_OVF register field. */
1332 #define ALT_EMAC_DMA_STATUS_OVF_RESET 0x0
1333 /* Extracts the ALT_EMAC_DMA_STATUS_OVF field value from a register. */
1334 #define ALT_EMAC_DMA_STATUS_OVF_GET(value) (((value) & 0x00000010) >> 4)
1335 /* Produces a ALT_EMAC_DMA_STATUS_OVF register field value suitable for setting the register. */
1336 #define ALT_EMAC_DMA_STATUS_OVF_SET(value) (((value) << 4) & 0x00000010)
1337 
1338 /*
1339  * Field : UNF
1340  *
1341  * Transmit Underflow
1342  *
1343  * This bit indicates that the Transmit Buffer had an Underflow during frame
1344  * transmission. Transmission is suspended and an Underflow Error TDES0[1] is set.
1345  *
1346  * Field Access Macros:
1347  *
1348  */
1349 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_UNF register field. */
1350 #define ALT_EMAC_DMA_STATUS_UNF_LSB 5
1351 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_UNF register field. */
1352 #define ALT_EMAC_DMA_STATUS_UNF_MSB 5
1353 /* The width in bits of the ALT_EMAC_DMA_STATUS_UNF register field. */
1354 #define ALT_EMAC_DMA_STATUS_UNF_WIDTH 1
1355 /* The mask used to set the ALT_EMAC_DMA_STATUS_UNF register field value. */
1356 #define ALT_EMAC_DMA_STATUS_UNF_SET_MSK 0x00000020
1357 /* The mask used to clear the ALT_EMAC_DMA_STATUS_UNF register field value. */
1358 #define ALT_EMAC_DMA_STATUS_UNF_CLR_MSK 0xffffffdf
1359 /* The reset value of the ALT_EMAC_DMA_STATUS_UNF register field. */
1360 #define ALT_EMAC_DMA_STATUS_UNF_RESET 0x0
1361 /* Extracts the ALT_EMAC_DMA_STATUS_UNF field value from a register. */
1362 #define ALT_EMAC_DMA_STATUS_UNF_GET(value) (((value) & 0x00000020) >> 5)
1363 /* Produces a ALT_EMAC_DMA_STATUS_UNF register field value suitable for setting the register. */
1364 #define ALT_EMAC_DMA_STATUS_UNF_SET(value) (((value) << 5) & 0x00000020)
1365 
1366 /*
1367  * Field : RI
1368  *
1369  * Receive Interrupt
1370  *
1371  * This bit indicates that the frame reception is complete. When reception is
1372  * complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the
1373  * last Descriptor, and the specific frame status information is updated in the
1374  * descriptor.
1375  *
1376  * The reception remains in the Running state.
1377  *
1378  * Field Access Macros:
1379  *
1380  */
1381 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_RI register field. */
1382 #define ALT_EMAC_DMA_STATUS_RI_LSB 6
1383 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_RI register field. */
1384 #define ALT_EMAC_DMA_STATUS_RI_MSB 6
1385 /* The width in bits of the ALT_EMAC_DMA_STATUS_RI register field. */
1386 #define ALT_EMAC_DMA_STATUS_RI_WIDTH 1
1387 /* The mask used to set the ALT_EMAC_DMA_STATUS_RI register field value. */
1388 #define ALT_EMAC_DMA_STATUS_RI_SET_MSK 0x00000040
1389 /* The mask used to clear the ALT_EMAC_DMA_STATUS_RI register field value. */
1390 #define ALT_EMAC_DMA_STATUS_RI_CLR_MSK 0xffffffbf
1391 /* The reset value of the ALT_EMAC_DMA_STATUS_RI register field. */
1392 #define ALT_EMAC_DMA_STATUS_RI_RESET 0x0
1393 /* Extracts the ALT_EMAC_DMA_STATUS_RI field value from a register. */
1394 #define ALT_EMAC_DMA_STATUS_RI_GET(value) (((value) & 0x00000040) >> 6)
1395 /* Produces a ALT_EMAC_DMA_STATUS_RI register field value suitable for setting the register. */
1396 #define ALT_EMAC_DMA_STATUS_RI_SET(value) (((value) << 6) & 0x00000040)
1397 
1398 /*
1399  * Field : RU
1400  *
1401  * Receive Buffer Unavailable
1402  *
1403  * This bit indicates that the host owns the Next Descriptor in the Receive List
1404  * and the DMA cannot acquire it. The Receive Process is suspended. To resume
1405  * processing Receive descriptors, the host should change the ownership of the
1406  * descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is
1407  * issued, the Receive Process resumes when the next recognized incoming frame is
1408  * received. This bit is set only when the previous Receive Descriptor is owned by
1409  * the DMA.
1410  *
1411  * Field Access Macros:
1412  *
1413  */
1414 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_RU register field. */
1415 #define ALT_EMAC_DMA_STATUS_RU_LSB 7
1416 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_RU register field. */
1417 #define ALT_EMAC_DMA_STATUS_RU_MSB 7
1418 /* The width in bits of the ALT_EMAC_DMA_STATUS_RU register field. */
1419 #define ALT_EMAC_DMA_STATUS_RU_WIDTH 1
1420 /* The mask used to set the ALT_EMAC_DMA_STATUS_RU register field value. */
1421 #define ALT_EMAC_DMA_STATUS_RU_SET_MSK 0x00000080
1422 /* The mask used to clear the ALT_EMAC_DMA_STATUS_RU register field value. */
1423 #define ALT_EMAC_DMA_STATUS_RU_CLR_MSK 0xffffff7f
1424 /* The reset value of the ALT_EMAC_DMA_STATUS_RU register field. */
1425 #define ALT_EMAC_DMA_STATUS_RU_RESET 0x0
1426 /* Extracts the ALT_EMAC_DMA_STATUS_RU field value from a register. */
1427 #define ALT_EMAC_DMA_STATUS_RU_GET(value) (((value) & 0x00000080) >> 7)
1428 /* Produces a ALT_EMAC_DMA_STATUS_RU register field value suitable for setting the register. */
1429 #define ALT_EMAC_DMA_STATUS_RU_SET(value) (((value) << 7) & 0x00000080)
1430 
1431 /*
1432  * Field : RPS
1433  *
1434  * Receive Process Stopped
1435  *
1436  * This bit is asserted when the Receive Process enters the Stopped state.
1437  *
1438  * Field Access Macros:
1439  *
1440  */
1441 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_RPS register field. */
1442 #define ALT_EMAC_DMA_STATUS_RPS_LSB 8
1443 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_RPS register field. */
1444 #define ALT_EMAC_DMA_STATUS_RPS_MSB 8
1445 /* The width in bits of the ALT_EMAC_DMA_STATUS_RPS register field. */
1446 #define ALT_EMAC_DMA_STATUS_RPS_WIDTH 1
1447 /* The mask used to set the ALT_EMAC_DMA_STATUS_RPS register field value. */
1448 #define ALT_EMAC_DMA_STATUS_RPS_SET_MSK 0x00000100
1449 /* The mask used to clear the ALT_EMAC_DMA_STATUS_RPS register field value. */
1450 #define ALT_EMAC_DMA_STATUS_RPS_CLR_MSK 0xfffffeff
1451 /* The reset value of the ALT_EMAC_DMA_STATUS_RPS register field. */
1452 #define ALT_EMAC_DMA_STATUS_RPS_RESET 0x0
1453 /* Extracts the ALT_EMAC_DMA_STATUS_RPS field value from a register. */
1454 #define ALT_EMAC_DMA_STATUS_RPS_GET(value) (((value) & 0x00000100) >> 8)
1455 /* Produces a ALT_EMAC_DMA_STATUS_RPS register field value suitable for setting the register. */
1456 #define ALT_EMAC_DMA_STATUS_RPS_SET(value) (((value) << 8) & 0x00000100)
1457 
1458 /*
1459  * Field : RWT
1460  *
1461  * Receive Watchdog Timeout
1462  *
1463  * When set, this bit indicates that the Receive Watchdog Timer expired while
1464  * receiving the current frame and the current frame is truncated after the
1465  * watchdog timeout.
1466  *
1467  * Field Access Macros:
1468  *
1469  */
1470 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_RWT register field. */
1471 #define ALT_EMAC_DMA_STATUS_RWT_LSB 9
1472 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_RWT register field. */
1473 #define ALT_EMAC_DMA_STATUS_RWT_MSB 9
1474 /* The width in bits of the ALT_EMAC_DMA_STATUS_RWT register field. */
1475 #define ALT_EMAC_DMA_STATUS_RWT_WIDTH 1
1476 /* The mask used to set the ALT_EMAC_DMA_STATUS_RWT register field value. */
1477 #define ALT_EMAC_DMA_STATUS_RWT_SET_MSK 0x00000200
1478 /* The mask used to clear the ALT_EMAC_DMA_STATUS_RWT register field value. */
1479 #define ALT_EMAC_DMA_STATUS_RWT_CLR_MSK 0xfffffdff
1480 /* The reset value of the ALT_EMAC_DMA_STATUS_RWT register field. */
1481 #define ALT_EMAC_DMA_STATUS_RWT_RESET 0x0
1482 /* Extracts the ALT_EMAC_DMA_STATUS_RWT field value from a register. */
1483 #define ALT_EMAC_DMA_STATUS_RWT_GET(value) (((value) & 0x00000200) >> 9)
1484 /* Produces a ALT_EMAC_DMA_STATUS_RWT register field value suitable for setting the register. */
1485 #define ALT_EMAC_DMA_STATUS_RWT_SET(value) (((value) << 9) & 0x00000200)
1486 
1487 /*
1488  * Field : ETI
1489  *
1490  * Early Transmit Interrupt
1491  *
1492  * This bit indicates that the frame to be transmitted is fully transferred to the
1493  * MTL Transmit FIFO.
1494  *
1495  * Field Access Macros:
1496  *
1497  */
1498 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_ETI register field. */
1499 #define ALT_EMAC_DMA_STATUS_ETI_LSB 10
1500 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_ETI register field. */
1501 #define ALT_EMAC_DMA_STATUS_ETI_MSB 10
1502 /* The width in bits of the ALT_EMAC_DMA_STATUS_ETI register field. */
1503 #define ALT_EMAC_DMA_STATUS_ETI_WIDTH 1
1504 /* The mask used to set the ALT_EMAC_DMA_STATUS_ETI register field value. */
1505 #define ALT_EMAC_DMA_STATUS_ETI_SET_MSK 0x00000400
1506 /* The mask used to clear the ALT_EMAC_DMA_STATUS_ETI register field value. */
1507 #define ALT_EMAC_DMA_STATUS_ETI_CLR_MSK 0xfffffbff
1508 /* The reset value of the ALT_EMAC_DMA_STATUS_ETI register field. */
1509 #define ALT_EMAC_DMA_STATUS_ETI_RESET 0x0
1510 /* Extracts the ALT_EMAC_DMA_STATUS_ETI field value from a register. */
1511 #define ALT_EMAC_DMA_STATUS_ETI_GET(value) (((value) & 0x00000400) >> 10)
1512 /* Produces a ALT_EMAC_DMA_STATUS_ETI register field value suitable for setting the register. */
1513 #define ALT_EMAC_DMA_STATUS_ETI_SET(value) (((value) << 10) & 0x00000400)
1514 
1515 /*
1516  * Field : Reserved_12_11
1517  *
1518  * Reserved
1519  *
1520  * Field Access Macros:
1521  *
1522  */
1523 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_RESERVED_12_11 register field. */
1524 #define ALT_EMAC_DMA_STATUS_RESERVED_12_11_LSB 11
1525 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_RESERVED_12_11 register field. */
1526 #define ALT_EMAC_DMA_STATUS_RESERVED_12_11_MSB 12
1527 /* The width in bits of the ALT_EMAC_DMA_STATUS_RESERVED_12_11 register field. */
1528 #define ALT_EMAC_DMA_STATUS_RESERVED_12_11_WIDTH 2
1529 /* The mask used to set the ALT_EMAC_DMA_STATUS_RESERVED_12_11 register field value. */
1530 #define ALT_EMAC_DMA_STATUS_RESERVED_12_11_SET_MSK 0x00001800
1531 /* The mask used to clear the ALT_EMAC_DMA_STATUS_RESERVED_12_11 register field value. */
1532 #define ALT_EMAC_DMA_STATUS_RESERVED_12_11_CLR_MSK 0xffffe7ff
1533 /* The reset value of the ALT_EMAC_DMA_STATUS_RESERVED_12_11 register field. */
1534 #define ALT_EMAC_DMA_STATUS_RESERVED_12_11_RESET 0x0
1535 /* Extracts the ALT_EMAC_DMA_STATUS_RESERVED_12_11 field value from a register. */
1536 #define ALT_EMAC_DMA_STATUS_RESERVED_12_11_GET(value) (((value) & 0x00001800) >> 11)
1537 /* Produces a ALT_EMAC_DMA_STATUS_RESERVED_12_11 register field value suitable for setting the register. */
1538 #define ALT_EMAC_DMA_STATUS_RESERVED_12_11_SET(value) (((value) << 11) & 0x00001800)
1539 
1540 /*
1541  * Field : FBI
1542  *
1543  * Fatal Bus Error Interrupt
1544  *
1545  * This bit indicates that a bus error occurred, as described in Bits[25:23]. When
1546  * this bit is set, the corresponding DMA engine disables all of its bus accesses.
1547  *
1548  * Field Access Macros:
1549  *
1550  */
1551 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_FBI register field. */
1552 #define ALT_EMAC_DMA_STATUS_FBI_LSB 13
1553 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_FBI register field. */
1554 #define ALT_EMAC_DMA_STATUS_FBI_MSB 13
1555 /* The width in bits of the ALT_EMAC_DMA_STATUS_FBI register field. */
1556 #define ALT_EMAC_DMA_STATUS_FBI_WIDTH 1
1557 /* The mask used to set the ALT_EMAC_DMA_STATUS_FBI register field value. */
1558 #define ALT_EMAC_DMA_STATUS_FBI_SET_MSK 0x00002000
1559 /* The mask used to clear the ALT_EMAC_DMA_STATUS_FBI register field value. */
1560 #define ALT_EMAC_DMA_STATUS_FBI_CLR_MSK 0xffffdfff
1561 /* The reset value of the ALT_EMAC_DMA_STATUS_FBI register field. */
1562 #define ALT_EMAC_DMA_STATUS_FBI_RESET 0x0
1563 /* Extracts the ALT_EMAC_DMA_STATUS_FBI field value from a register. */
1564 #define ALT_EMAC_DMA_STATUS_FBI_GET(value) (((value) & 0x00002000) >> 13)
1565 /* Produces a ALT_EMAC_DMA_STATUS_FBI register field value suitable for setting the register. */
1566 #define ALT_EMAC_DMA_STATUS_FBI_SET(value) (((value) << 13) & 0x00002000)
1567 
1568 /*
1569  * Field : ERI
1570  *
1571  * Early Receive Interrupt
1572  *
1573  * This bit indicates that the DMA filled the first data buffer of the packet. This
1574  * bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this
1575  * register is set (whichever occurs earlier).
1576  *
1577  * Field Access Macros:
1578  *
1579  */
1580 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_ERI register field. */
1581 #define ALT_EMAC_DMA_STATUS_ERI_LSB 14
1582 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_ERI register field. */
1583 #define ALT_EMAC_DMA_STATUS_ERI_MSB 14
1584 /* The width in bits of the ALT_EMAC_DMA_STATUS_ERI register field. */
1585 #define ALT_EMAC_DMA_STATUS_ERI_WIDTH 1
1586 /* The mask used to set the ALT_EMAC_DMA_STATUS_ERI register field value. */
1587 #define ALT_EMAC_DMA_STATUS_ERI_SET_MSK 0x00004000
1588 /* The mask used to clear the ALT_EMAC_DMA_STATUS_ERI register field value. */
1589 #define ALT_EMAC_DMA_STATUS_ERI_CLR_MSK 0xffffbfff
1590 /* The reset value of the ALT_EMAC_DMA_STATUS_ERI register field. */
1591 #define ALT_EMAC_DMA_STATUS_ERI_RESET 0x0
1592 /* Extracts the ALT_EMAC_DMA_STATUS_ERI field value from a register. */
1593 #define ALT_EMAC_DMA_STATUS_ERI_GET(value) (((value) & 0x00004000) >> 14)
1594 /* Produces a ALT_EMAC_DMA_STATUS_ERI register field value suitable for setting the register. */
1595 #define ALT_EMAC_DMA_STATUS_ERI_SET(value) (((value) << 14) & 0x00004000)
1596 
1597 /*
1598  * Field : AIS
1599  *
1600  * Abnormal Interrupt Summary
1601  *
1602  * Abnormal Interrupt Summary bit value is the logical OR of the following when the
1603  * corresponding interrupt bits are enabled in Register 7 (Interrupt Enable
1604  * Register):
1605  *
1606  * * Register 5[1]: Transmit Process Stopped
1607  *
1608  * * Register 5[3]: Transmit Jabber Timeout
1609  *
1610  * * Register 5[4]: Receive FIFO Overflow
1611  *
1612  * * Register 5[5]: Transmit Underflow
1613  *
1614  * * Register 5[7]: Receive Buffer Unavailable
1615  *
1616  * * Register 5[8]: Receive Process Stopped
1617  *
1618  * * Register 5[9]: Receive Watchdog Timeout
1619  *
1620  * * Register 5[10]: Early Transmit Interrupt
1621  *
1622  * * Register 5[13]: Fatal Bus Error
1623  *
1624  * Only unmasked bits affect the Abnormal Interrupt Summary bit.
1625  *
1626  * This is a sticky bit and must be cleared each time a corresponding bit, which
1627  * causes AIS to be set, is cleared.
1628  *
1629  * Field Access Macros:
1630  *
1631  */
1632 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_AIS register field. */
1633 #define ALT_EMAC_DMA_STATUS_AIS_LSB 15
1634 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_AIS register field. */
1635 #define ALT_EMAC_DMA_STATUS_AIS_MSB 15
1636 /* The width in bits of the ALT_EMAC_DMA_STATUS_AIS register field. */
1637 #define ALT_EMAC_DMA_STATUS_AIS_WIDTH 1
1638 /* The mask used to set the ALT_EMAC_DMA_STATUS_AIS register field value. */
1639 #define ALT_EMAC_DMA_STATUS_AIS_SET_MSK 0x00008000
1640 /* The mask used to clear the ALT_EMAC_DMA_STATUS_AIS register field value. */
1641 #define ALT_EMAC_DMA_STATUS_AIS_CLR_MSK 0xffff7fff
1642 /* The reset value of the ALT_EMAC_DMA_STATUS_AIS register field. */
1643 #define ALT_EMAC_DMA_STATUS_AIS_RESET 0x0
1644 /* Extracts the ALT_EMAC_DMA_STATUS_AIS field value from a register. */
1645 #define ALT_EMAC_DMA_STATUS_AIS_GET(value) (((value) & 0x00008000) >> 15)
1646 /* Produces a ALT_EMAC_DMA_STATUS_AIS register field value suitable for setting the register. */
1647 #define ALT_EMAC_DMA_STATUS_AIS_SET(value) (((value) << 15) & 0x00008000)
1648 
1649 /*
1650  * Field : NIS
1651  *
1652  * Normal Interrupt Summary
1653  *
1654  * Normal Interrupt Summary bit value is the logical OR of the following when the
1655  * corresponding interrupt bits are enabled in Register 7 (Interrupt Enable
1656  * Register):
1657  *
1658  * * Register 5[0]: Transmit Interrupt
1659  *
1660  * * Register 5[2]: Transmit Buffer Unavailable
1661  *
1662  * * Register 5[6]: Receive Interrupt
1663  *
1664  * * Register 5[14]: Early Receive Interrupt
1665  *
1666  * Only unmasked bits (interrupts for which interrupt enable is set in Register 7)
1667  * affect the Normal Interrupt Summary bit.
1668  *
1669  * This is a sticky bit and must be cleared (by writing 1 to this bit) each time a
1670  * corresponding bit, which causes NIS to be set, is cleared.
1671  *
1672  * Field Access Macros:
1673  *
1674  */
1675 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_NIS register field. */
1676 #define ALT_EMAC_DMA_STATUS_NIS_LSB 16
1677 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_NIS register field. */
1678 #define ALT_EMAC_DMA_STATUS_NIS_MSB 16
1679 /* The width in bits of the ALT_EMAC_DMA_STATUS_NIS register field. */
1680 #define ALT_EMAC_DMA_STATUS_NIS_WIDTH 1
1681 /* The mask used to set the ALT_EMAC_DMA_STATUS_NIS register field value. */
1682 #define ALT_EMAC_DMA_STATUS_NIS_SET_MSK 0x00010000
1683 /* The mask used to clear the ALT_EMAC_DMA_STATUS_NIS register field value. */
1684 #define ALT_EMAC_DMA_STATUS_NIS_CLR_MSK 0xfffeffff
1685 /* The reset value of the ALT_EMAC_DMA_STATUS_NIS register field. */
1686 #define ALT_EMAC_DMA_STATUS_NIS_RESET 0x0
1687 /* Extracts the ALT_EMAC_DMA_STATUS_NIS field value from a register. */
1688 #define ALT_EMAC_DMA_STATUS_NIS_GET(value) (((value) & 0x00010000) >> 16)
1689 /* Produces a ALT_EMAC_DMA_STATUS_NIS register field value suitable for setting the register. */
1690 #define ALT_EMAC_DMA_STATUS_NIS_SET(value) (((value) << 16) & 0x00010000)
1691 
1692 /*
1693  * Field : RS
1694  *
1695  * Received Process State
1696  *
1697  * This field indicates the Receive DMA FSM state. This field does not generate an
1698  * interrupt.
1699  *
1700  * * 3'b000: Stopped: Reset or Stop Receive Command issued
1701  *
1702  * * 3'b001: Running: Fetching Receive Transfer Descriptor
1703  *
1704  * * 3'b010: Reserved for future use
1705  *
1706  * * 3'b011: Running: Waiting for receive packet
1707  *
1708  * * 3'b100: Suspended: Receive Descriptor Unavailable
1709  *
1710  * * 3'b101: Running: Closing Receive Descriptor
1711  *
1712  * * 3'b110: TIME_STAMP write state
1713  *
1714  * * 3'b111: Running: Transferring the receive packet data from receive buffer to
1715  * host memory
1716  *
1717  * Field Access Macros:
1718  *
1719  */
1720 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_RS register field. */
1721 #define ALT_EMAC_DMA_STATUS_RS_LSB 17
1722 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_RS register field. */
1723 #define ALT_EMAC_DMA_STATUS_RS_MSB 19
1724 /* The width in bits of the ALT_EMAC_DMA_STATUS_RS register field. */
1725 #define ALT_EMAC_DMA_STATUS_RS_WIDTH 3
1726 /* The mask used to set the ALT_EMAC_DMA_STATUS_RS register field value. */
1727 #define ALT_EMAC_DMA_STATUS_RS_SET_MSK 0x000e0000
1728 /* The mask used to clear the ALT_EMAC_DMA_STATUS_RS register field value. */
1729 #define ALT_EMAC_DMA_STATUS_RS_CLR_MSK 0xfff1ffff
1730 /* The reset value of the ALT_EMAC_DMA_STATUS_RS register field. */
1731 #define ALT_EMAC_DMA_STATUS_RS_RESET 0x0
1732 /* Extracts the ALT_EMAC_DMA_STATUS_RS field value from a register. */
1733 #define ALT_EMAC_DMA_STATUS_RS_GET(value) (((value) & 0x000e0000) >> 17)
1734 /* Produces a ALT_EMAC_DMA_STATUS_RS register field value suitable for setting the register. */
1735 #define ALT_EMAC_DMA_STATUS_RS_SET(value) (((value) << 17) & 0x000e0000)
1736 
1737 /*
1738  * Field : TS
1739  *
1740  * Transmit Process State
1741  *
1742  * This field indicates the Transmit DMA FSM state. This field does not generate an
1743  * interrupt.
1744  *
1745  * * 3'b000: Stopped; Reset or Stop Transmit Command issued
1746  *
1747  * * 3'b001: Running; Fetching Transmit Transfer Descriptor
1748  *
1749  * * 3'b010: Running; Waiting for status
1750  *
1751  * * 3'b011: Running; Reading Data from host memory buffer and queuing it to
1752  * transmit buffer (Tx FIFO)
1753  *
1754  * * 3'b100: TIME_STAMP write state
1755  *
1756  * * 3'b101: Reserved for future use
1757  *
1758  * * 3'b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer
1759  * Underflow
1760  *
1761  * * 3'b111: Running; Closing Transmit Descriptor
1762  *
1763  * Field Access Macros:
1764  *
1765  */
1766 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_TS register field. */
1767 #define ALT_EMAC_DMA_STATUS_TS_LSB 20
1768 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_TS register field. */
1769 #define ALT_EMAC_DMA_STATUS_TS_MSB 22
1770 /* The width in bits of the ALT_EMAC_DMA_STATUS_TS register field. */
1771 #define ALT_EMAC_DMA_STATUS_TS_WIDTH 3
1772 /* The mask used to set the ALT_EMAC_DMA_STATUS_TS register field value. */
1773 #define ALT_EMAC_DMA_STATUS_TS_SET_MSK 0x00700000
1774 /* The mask used to clear the ALT_EMAC_DMA_STATUS_TS register field value. */
1775 #define ALT_EMAC_DMA_STATUS_TS_CLR_MSK 0xff8fffff
1776 /* The reset value of the ALT_EMAC_DMA_STATUS_TS register field. */
1777 #define ALT_EMAC_DMA_STATUS_TS_RESET 0x0
1778 /* Extracts the ALT_EMAC_DMA_STATUS_TS field value from a register. */
1779 #define ALT_EMAC_DMA_STATUS_TS_GET(value) (((value) & 0x00700000) >> 20)
1780 /* Produces a ALT_EMAC_DMA_STATUS_TS register field value suitable for setting the register. */
1781 #define ALT_EMAC_DMA_STATUS_TS_SET(value) (((value) << 20) & 0x00700000)
1782 
1783 /*
1784  * Field : EB
1785  *
1786  * Error Bits
1787  *
1788  * This field indicates the type of error that caused a Bus Error, for example,
1789  * error response on the AHB or AXI interface. This field is valid only when Bit 13
1790  * (FBI) is set. This field does not generate an interrupt.
1791  *
1792  * * 0 0 0: Error during Rx DMA Write Data Transfer
1793  *
1794  * * 0 1 1: Error during Tx DMA Read Data Transfer
1795  *
1796  * * 1 0 0: Error during Rx DMA Descriptor Write Access
1797  *
1798  * * 1 0 1: Error during Tx DMA Descriptor Write Access
1799  *
1800  * * 1 1 0: Error during Rx DMA Descriptor Read Access
1801  *
1802  * * 1 1 1: Error during Tx DMA Descriptor Read Access
1803  *
1804  * Note: 001 and 010 are reserved.
1805  *
1806  * Field Access Macros:
1807  *
1808  */
1809 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_EB register field. */
1810 #define ALT_EMAC_DMA_STATUS_EB_LSB 23
1811 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_EB register field. */
1812 #define ALT_EMAC_DMA_STATUS_EB_MSB 25
1813 /* The width in bits of the ALT_EMAC_DMA_STATUS_EB register field. */
1814 #define ALT_EMAC_DMA_STATUS_EB_WIDTH 3
1815 /* The mask used to set the ALT_EMAC_DMA_STATUS_EB register field value. */
1816 #define ALT_EMAC_DMA_STATUS_EB_SET_MSK 0x03800000
1817 /* The mask used to clear the ALT_EMAC_DMA_STATUS_EB register field value. */
1818 #define ALT_EMAC_DMA_STATUS_EB_CLR_MSK 0xfc7fffff
1819 /* The reset value of the ALT_EMAC_DMA_STATUS_EB register field. */
1820 #define ALT_EMAC_DMA_STATUS_EB_RESET 0x0
1821 /* Extracts the ALT_EMAC_DMA_STATUS_EB field value from a register. */
1822 #define ALT_EMAC_DMA_STATUS_EB_GET(value) (((value) & 0x03800000) >> 23)
1823 /* Produces a ALT_EMAC_DMA_STATUS_EB register field value suitable for setting the register. */
1824 #define ALT_EMAC_DMA_STATUS_EB_SET(value) (((value) << 23) & 0x03800000)
1825 
1826 /*
1827  * Field : GLI
1828  *
1829  * GMAC Line interface Interrupt
1830  *
1831  * When set, this bit reflects any of the following interrupt events in the
1832  * DWC_gmac
1833  *
1834  * interfaces (if present and enabled in your configuration):
1835  *
1836  * * PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event
1837  *
1838  * * SMII or RGMII: Link change event
1839  *
1840  * * General Purpose Input Status (GPIS): Any LL or LH event on the gpi_i input
1841  * ports
1842  *
1843  * To identify the exact cause of the interrupt, the software must first read Bit
1844  * 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear
1845  * the source of interrupt (which also clears the GLI interrupt), read any of the
1846  * following corresponding registers:
1847  *
1848  * * PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register)
1849  *
1850  * * SMII or RGMII: Register 54 (SGMII/RGMII/SMII Status Register)
1851  *
1852  * * General Purpose Input (GPI): Register 56 (General Purpose IO Register)
1853  *
1854  * The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this
1855  * bit is high.
1856  *
1857  * Field Access Macros:
1858  *
1859  */
1860 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_GLI register field. */
1861 #define ALT_EMAC_DMA_STATUS_GLI_LSB 26
1862 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_GLI register field. */
1863 #define ALT_EMAC_DMA_STATUS_GLI_MSB 26
1864 /* The width in bits of the ALT_EMAC_DMA_STATUS_GLI register field. */
1865 #define ALT_EMAC_DMA_STATUS_GLI_WIDTH 1
1866 /* The mask used to set the ALT_EMAC_DMA_STATUS_GLI register field value. */
1867 #define ALT_EMAC_DMA_STATUS_GLI_SET_MSK 0x04000000
1868 /* The mask used to clear the ALT_EMAC_DMA_STATUS_GLI register field value. */
1869 #define ALT_EMAC_DMA_STATUS_GLI_CLR_MSK 0xfbffffff
1870 /* The reset value of the ALT_EMAC_DMA_STATUS_GLI register field. */
1871 #define ALT_EMAC_DMA_STATUS_GLI_RESET 0x0
1872 /* Extracts the ALT_EMAC_DMA_STATUS_GLI field value from a register. */
1873 #define ALT_EMAC_DMA_STATUS_GLI_GET(value) (((value) & 0x04000000) >> 26)
1874 /* Produces a ALT_EMAC_DMA_STATUS_GLI register field value suitable for setting the register. */
1875 #define ALT_EMAC_DMA_STATUS_GLI_SET(value) (((value) << 26) & 0x04000000)
1876 
1877 /*
1878  * Field : GMI
1879  *
1880  * GMAC MMC Interrupt
1881  *
1882  * This bit reflects an interrupt event in the MMC module of the DWC_gmac. The
1883  * software must read the corresponding registers in the DWC_gmac to get the exact
1884  * cause of interrupt and clear the source of interrupt to make this bit as 1'b0.
1885  * The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this
1886  * bit is high.
1887  *
1888  * This bit is applicable only when the MAC Management Counters (MMC) are enabled.
1889  * Otherwise, this bit is reserved.
1890  *
1891  * Field Access Macros:
1892  *
1893  */
1894 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_GMI register field. */
1895 #define ALT_EMAC_DMA_STATUS_GMI_LSB 27
1896 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_GMI register field. */
1897 #define ALT_EMAC_DMA_STATUS_GMI_MSB 27
1898 /* The width in bits of the ALT_EMAC_DMA_STATUS_GMI register field. */
1899 #define ALT_EMAC_DMA_STATUS_GMI_WIDTH 1
1900 /* The mask used to set the ALT_EMAC_DMA_STATUS_GMI register field value. */
1901 #define ALT_EMAC_DMA_STATUS_GMI_SET_MSK 0x08000000
1902 /* The mask used to clear the ALT_EMAC_DMA_STATUS_GMI register field value. */
1903 #define ALT_EMAC_DMA_STATUS_GMI_CLR_MSK 0xf7ffffff
1904 /* The reset value of the ALT_EMAC_DMA_STATUS_GMI register field. */
1905 #define ALT_EMAC_DMA_STATUS_GMI_RESET 0x0
1906 /* Extracts the ALT_EMAC_DMA_STATUS_GMI field value from a register. */
1907 #define ALT_EMAC_DMA_STATUS_GMI_GET(value) (((value) & 0x08000000) >> 27)
1908 /* Produces a ALT_EMAC_DMA_STATUS_GMI register field value suitable for setting the register. */
1909 #define ALT_EMAC_DMA_STATUS_GMI_SET(value) (((value) << 27) & 0x08000000)
1910 
1911 /*
1912  * Field : GPI
1913  *
1914  * GMAC PMT Interrupt
1915  *
1916  * This bit indicates an interrupt event in the PMT module of the DWC_gmac. The
1917  * software must read the PMT Control and Status Register in the MAC to get the
1918  * exact cause of interrupt and clear its source to reset this bit to 1'b0. The
1919  * interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit
1920  * is high.
1921  *
1922  * This bit is applicable only when the Power Management feature is enabled.
1923  * Otherwise, this bit is reserved.
1924  *
1925  * Note: The GPI and pmt_intr_o interrupts are generated in different clock
1926  * domains.
1927  *
1928  * Field Access Macros:
1929  *
1930  */
1931 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_GPI register field. */
1932 #define ALT_EMAC_DMA_STATUS_GPI_LSB 28
1933 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_GPI register field. */
1934 #define ALT_EMAC_DMA_STATUS_GPI_MSB 28
1935 /* The width in bits of the ALT_EMAC_DMA_STATUS_GPI register field. */
1936 #define ALT_EMAC_DMA_STATUS_GPI_WIDTH 1
1937 /* The mask used to set the ALT_EMAC_DMA_STATUS_GPI register field value. */
1938 #define ALT_EMAC_DMA_STATUS_GPI_SET_MSK 0x10000000
1939 /* The mask used to clear the ALT_EMAC_DMA_STATUS_GPI register field value. */
1940 #define ALT_EMAC_DMA_STATUS_GPI_CLR_MSK 0xefffffff
1941 /* The reset value of the ALT_EMAC_DMA_STATUS_GPI register field. */
1942 #define ALT_EMAC_DMA_STATUS_GPI_RESET 0x0
1943 /* Extracts the ALT_EMAC_DMA_STATUS_GPI field value from a register. */
1944 #define ALT_EMAC_DMA_STATUS_GPI_GET(value) (((value) & 0x10000000) >> 28)
1945 /* Produces a ALT_EMAC_DMA_STATUS_GPI register field value suitable for setting the register. */
1946 #define ALT_EMAC_DMA_STATUS_GPI_SET(value) (((value) << 28) & 0x10000000)
1947 
1948 /*
1949  * Field : TTI
1950  *
1951  * Timestamp Trigger Interrupt
1952  *
1953  * This bit indicates an interrupt event in the Timestamp Generator block of
1954  * DWC_gmac. The software must read the corresponding registers in the DWC_gmac to
1955  * get the exact cause of interrupt and clear its source to reset this bit to 1'b0.
1956  * When this bit is high, the interrupt signal from the DWC_gmac subsystem
1957  * (sbd_intr_o) is high.
1958  *
1959  * This bit is applicable only when the IEEE 1588 Timestamp feature is enabled.
1960  * Otherwise, this bit is reserved.
1961  *
1962  * Field Access Macros:
1963  *
1964  */
1965 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_TTI register field. */
1966 #define ALT_EMAC_DMA_STATUS_TTI_LSB 29
1967 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_TTI register field. */
1968 #define ALT_EMAC_DMA_STATUS_TTI_MSB 29
1969 /* The width in bits of the ALT_EMAC_DMA_STATUS_TTI register field. */
1970 #define ALT_EMAC_DMA_STATUS_TTI_WIDTH 1
1971 /* The mask used to set the ALT_EMAC_DMA_STATUS_TTI register field value. */
1972 #define ALT_EMAC_DMA_STATUS_TTI_SET_MSK 0x20000000
1973 /* The mask used to clear the ALT_EMAC_DMA_STATUS_TTI register field value. */
1974 #define ALT_EMAC_DMA_STATUS_TTI_CLR_MSK 0xdfffffff
1975 /* The reset value of the ALT_EMAC_DMA_STATUS_TTI register field. */
1976 #define ALT_EMAC_DMA_STATUS_TTI_RESET 0x0
1977 /* Extracts the ALT_EMAC_DMA_STATUS_TTI field value from a register. */
1978 #define ALT_EMAC_DMA_STATUS_TTI_GET(value) (((value) & 0x20000000) >> 29)
1979 /* Produces a ALT_EMAC_DMA_STATUS_TTI register field value suitable for setting the register. */
1980 #define ALT_EMAC_DMA_STATUS_TTI_SET(value) (((value) << 29) & 0x20000000)
1981 
1982 /*
1983  * Field : GLPII
1984  *
1985  * GMAC LPI Interrupt (for Channel 0)
1986  *
1987  * This bit indicates an interrupt event in the LPI logic of the DWC_gmac. To reset
1988  * this bit to 1'b0, the software must read the corresponding registers in the
1989  * DWC_gmac to get the exact cause of the interrupt and clear its source.
1990  *
1991  * Note: GLPII status is given only in Channel 0 DMA register and is applicable
1992  * only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit
1993  * is reserved.When this bit is high, the interrupt signal from the MAC
1994  * (sbd_intr_o) is high.
1995  *
1996  * Field Access Macros:
1997  *
1998  */
1999 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_GLPII register field. */
2000 #define ALT_EMAC_DMA_STATUS_GLPII_LSB 30
2001 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_GLPII register field. */
2002 #define ALT_EMAC_DMA_STATUS_GLPII_MSB 30
2003 /* The width in bits of the ALT_EMAC_DMA_STATUS_GLPII register field. */
2004 #define ALT_EMAC_DMA_STATUS_GLPII_WIDTH 1
2005 /* The mask used to set the ALT_EMAC_DMA_STATUS_GLPII register field value. */
2006 #define ALT_EMAC_DMA_STATUS_GLPII_SET_MSK 0x40000000
2007 /* The mask used to clear the ALT_EMAC_DMA_STATUS_GLPII register field value. */
2008 #define ALT_EMAC_DMA_STATUS_GLPII_CLR_MSK 0xbfffffff
2009 /* The reset value of the ALT_EMAC_DMA_STATUS_GLPII register field. */
2010 #define ALT_EMAC_DMA_STATUS_GLPII_RESET 0x0
2011 /* Extracts the ALT_EMAC_DMA_STATUS_GLPII field value from a register. */
2012 #define ALT_EMAC_DMA_STATUS_GLPII_GET(value) (((value) & 0x40000000) >> 30)
2013 /* Produces a ALT_EMAC_DMA_STATUS_GLPII register field value suitable for setting the register. */
2014 #define ALT_EMAC_DMA_STATUS_GLPII_SET(value) (((value) << 30) & 0x40000000)
2015 
2016 /*
2017  * Field : Reserved_31
2018  *
2019  * Reserved
2020  *
2021  * Field Access Macros:
2022  *
2023  */
2024 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STATUS_RESERVED_31 register field. */
2025 #define ALT_EMAC_DMA_STATUS_RESERVED_31_LSB 31
2026 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STATUS_RESERVED_31 register field. */
2027 #define ALT_EMAC_DMA_STATUS_RESERVED_31_MSB 31
2028 /* The width in bits of the ALT_EMAC_DMA_STATUS_RESERVED_31 register field. */
2029 #define ALT_EMAC_DMA_STATUS_RESERVED_31_WIDTH 1
2030 /* The mask used to set the ALT_EMAC_DMA_STATUS_RESERVED_31 register field value. */
2031 #define ALT_EMAC_DMA_STATUS_RESERVED_31_SET_MSK 0x80000000
2032 /* The mask used to clear the ALT_EMAC_DMA_STATUS_RESERVED_31 register field value. */
2033 #define ALT_EMAC_DMA_STATUS_RESERVED_31_CLR_MSK 0x7fffffff
2034 /* The reset value of the ALT_EMAC_DMA_STATUS_RESERVED_31 register field. */
2035 #define ALT_EMAC_DMA_STATUS_RESERVED_31_RESET 0x0
2036 /* Extracts the ALT_EMAC_DMA_STATUS_RESERVED_31 field value from a register. */
2037 #define ALT_EMAC_DMA_STATUS_RESERVED_31_GET(value) (((value) & 0x80000000) >> 31)
2038 /* Produces a ALT_EMAC_DMA_STATUS_RESERVED_31 register field value suitable for setting the register. */
2039 #define ALT_EMAC_DMA_STATUS_RESERVED_31_SET(value) (((value) << 31) & 0x80000000)
2040 
2041 #ifndef __ASSEMBLY__
2042 /*
2043  * WARNING: The C register and register group struct declarations are provided for
2044  * convenience and illustrative purposes. They should, however, be used with
2045  * caution as the C language standard provides no guarantees about the alignment or
2046  * atomicity of device memory accesses. The recommended practice for writing
2047  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2048  * alt_write_word() functions.
2049  *
2050  * The struct declaration for register ALT_EMAC_DMA_STATUS.
2051  */
2052 struct ALT_EMAC_DMA_STATUS_s
2053 {
2054  volatile uint32_t TI : 1; /* ALT_EMAC_DMA_STATUS_TI */
2055  volatile uint32_t TPS : 1; /* ALT_EMAC_DMA_STATUS_TPS */
2056  volatile uint32_t TU : 1; /* ALT_EMAC_DMA_STATUS_TU */
2057  volatile uint32_t TJT : 1; /* ALT_EMAC_DMA_STATUS_TJT */
2058  volatile uint32_t OVF : 1; /* ALT_EMAC_DMA_STATUS_OVF */
2059  volatile uint32_t UNF : 1; /* ALT_EMAC_DMA_STATUS_UNF */
2060  volatile uint32_t RI : 1; /* ALT_EMAC_DMA_STATUS_RI */
2061  volatile uint32_t RU : 1; /* ALT_EMAC_DMA_STATUS_RU */
2062  volatile uint32_t RPS : 1; /* ALT_EMAC_DMA_STATUS_RPS */
2063  volatile uint32_t RWT : 1; /* ALT_EMAC_DMA_STATUS_RWT */
2064  volatile uint32_t ETI : 1; /* ALT_EMAC_DMA_STATUS_ETI */
2065  const volatile uint32_t Reserved_12_11 : 2; /* ALT_EMAC_DMA_STATUS_RESERVED_12_11 */
2066  volatile uint32_t FBI : 1; /* ALT_EMAC_DMA_STATUS_FBI */
2067  volatile uint32_t ERI : 1; /* ALT_EMAC_DMA_STATUS_ERI */
2068  volatile uint32_t AIS : 1; /* ALT_EMAC_DMA_STATUS_AIS */
2069  volatile uint32_t NIS : 1; /* ALT_EMAC_DMA_STATUS_NIS */
2070  const volatile uint32_t RS : 3; /* ALT_EMAC_DMA_STATUS_RS */
2071  const volatile uint32_t TS : 3; /* ALT_EMAC_DMA_STATUS_TS */
2072  const volatile uint32_t EB : 3; /* ALT_EMAC_DMA_STATUS_EB */
2073  const volatile uint32_t GLI : 1; /* ALT_EMAC_DMA_STATUS_GLI */
2074  const volatile uint32_t GMI : 1; /* ALT_EMAC_DMA_STATUS_GMI */
2075  const volatile uint32_t GPI : 1; /* ALT_EMAC_DMA_STATUS_GPI */
2076  const volatile uint32_t TTI : 1; /* ALT_EMAC_DMA_STATUS_TTI */
2077  const volatile uint32_t GLPII : 1; /* ALT_EMAC_DMA_STATUS_GLPII */
2078  const volatile uint32_t Reserved_31 : 1; /* ALT_EMAC_DMA_STATUS_RESERVED_31 */
2079 };
2080 
2081 /* The typedef declaration for register ALT_EMAC_DMA_STATUS. */
2082 typedef struct ALT_EMAC_DMA_STATUS_s ALT_EMAC_DMA_STATUS_t;
2083 #endif /* __ASSEMBLY__ */
2084 
2085 /* The reset value of the ALT_EMAC_DMA_STATUS register. */
2086 #define ALT_EMAC_DMA_STATUS_RESET 0x00000000
2087 /* The byte offset of the ALT_EMAC_DMA_STATUS register from the beginning of the component. */
2088 #define ALT_EMAC_DMA_STATUS_OFST 0x14
2089 /* The address of the ALT_EMAC_DMA_STATUS register. */
2090 #define ALT_EMAC_DMA_STATUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_STATUS_OFST))
2091 
2092 /*
2093  * Register : Operation_Mode
2094  *
2095  * <b> Register 6 (Operation Mode Register) </b>
2096  *
2097  * The Operation Mode register establishes the Transmit and Receive operating modes
2098  * and commands. This register should be the last CSR to be written as part of the
2099  * DMA initialization. This register is also present in the GMAC-MTL configuration
2100  * with unused and reserved bits 24, 13, 2, and 1.
2101  *
2102  * Register Layout
2103  *
2104  * Bits | Access | Reset | Description
2105  * :--------|:-------|:------|:-------------------------------------------
2106  * [0] | R | 0x0 | ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0
2107  * [1] | RW | 0x0 | ALT_EMAC_DMA_OPERATION_MODE_SR
2108  * [2] | RW | 0x0 | ALT_EMAC_DMA_OPERATION_MODE_OSF
2109  * [4:3] | RW | 0x0 | ALT_EMAC_DMA_OPERATION_MODE_RTC
2110  * [5] | RW | 0x0 | ALT_EMAC_DMA_OPERATION_MODE_DGF
2111  * [6] | RW | 0x0 | ALT_EMAC_DMA_OPERATION_MODE_FUF
2112  * [7] | RW | 0x0 | ALT_EMAC_DMA_OPERATION_MODE_FEF
2113  * [8] | RW | 0x0 | ALT_EMAC_DMA_OPERATION_MODE_EFC
2114  * [10:9] | RW | 0x0 | ALT_EMAC_DMA_OPERATION_MODE_RFA
2115  * [12:11] | RW | 0x0 | ALT_EMAC_DMA_OPERATION_MODE_RFD
2116  * [13] | RW | 0x0 | ALT_EMAC_DMA_OPERATION_MODE_ST
2117  * [16:14] | RW | 0x0 | ALT_EMAC_DMA_OPERATION_MODE_TTC
2118  * [19:17] | R | 0x0 | ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17
2119  * [20] | RW | 0x0 | ALT_EMAC_DMA_OPERATION_MODE_FTF
2120  * [21] | RW | 0x0 | ALT_EMAC_DMA_OPERATION_MODE_TSF
2121  * [22] | RW | 0x0 | ALT_EMAC_DMA_OPERATION_MODE_RFD_2
2122  * [23] | RW | 0x0 | ALT_EMAC_DMA_OPERATION_MODE_RFA_2
2123  * [24] | RW | 0x0 | ALT_EMAC_DMA_OPERATION_MODE_DFF
2124  * [25] | RW | 0x0 | ALT_EMAC_DMA_OPERATION_MODE_RSF
2125  * [26] | RW | 0x0 | ALT_EMAC_DMA_OPERATION_MODE_DT
2126  * [31:27] | R | 0x0 | ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27
2127  *
2128  */
2129 /*
2130  * Field : Reserved_0
2131  *
2132  * Reserved
2133  *
2134  * Field Access Macros:
2135  *
2136  */
2137 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0 register field. */
2138 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0_LSB 0
2139 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0 register field. */
2140 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0_MSB 0
2141 /* The width in bits of the ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0 register field. */
2142 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0_WIDTH 1
2143 /* The mask used to set the ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0 register field value. */
2144 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0_SET_MSK 0x00000001
2145 /* The mask used to clear the ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0 register field value. */
2146 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0_CLR_MSK 0xfffffffe
2147 /* The reset value of the ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0 register field. */
2148 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0_RESET 0x0
2149 /* Extracts the ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0 field value from a register. */
2150 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0_GET(value) (((value) & 0x00000001) >> 0)
2151 /* Produces a ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0 register field value suitable for setting the register. */
2152 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0_SET(value) (((value) << 0) & 0x00000001)
2153 
2154 /*
2155  * Field : SR
2156  *
2157  * Start or Stop Receive
2158  *
2159  * When this bit is set, the Receive process is placed in the Running state. The
2160  * DMA attempts to acquire the descriptor from the Receive list and processes the
2161  * incoming frames. The descriptor acquisition is attempted from the current
2162  * position in the list, which is the address set by Register 3 (Receive Descriptor
2163  * List Address Register) or the position retained when the Receive process was
2164  * previously stopped. If the DMA does not own the descriptor, reception is
2165  * suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register)
2166  * is set. The Start Receive command is effective only when the reception has
2167  * stopped. If the command is issued before setting Register 3 (Receive Descriptor
2168  * List Address Register), the DMA behavior is unpredictable.
2169  *
2170  * When this bit is cleared, the Rx DMA operation is stopped after the transfer of
2171  * the current frame. The next descriptor position in the Receive list is saved and
2172  * becomes the current position after the Receive process is restarted. The Stop
2173  * Receive command is effective only when the Receive process is in either the
2174  * Running (waiting for receive packet) or in the Suspended state.
2175  *
2176  * Field Access Macros:
2177  *
2178  */
2179 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OPERATION_MODE_SR register field. */
2180 #define ALT_EMAC_DMA_OPERATION_MODE_SR_LSB 1
2181 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OPERATION_MODE_SR register field. */
2182 #define ALT_EMAC_DMA_OPERATION_MODE_SR_MSB 1
2183 /* The width in bits of the ALT_EMAC_DMA_OPERATION_MODE_SR register field. */
2184 #define ALT_EMAC_DMA_OPERATION_MODE_SR_WIDTH 1
2185 /* The mask used to set the ALT_EMAC_DMA_OPERATION_MODE_SR register field value. */
2186 #define ALT_EMAC_DMA_OPERATION_MODE_SR_SET_MSK 0x00000002
2187 /* The mask used to clear the ALT_EMAC_DMA_OPERATION_MODE_SR register field value. */
2188 #define ALT_EMAC_DMA_OPERATION_MODE_SR_CLR_MSK 0xfffffffd
2189 /* The reset value of the ALT_EMAC_DMA_OPERATION_MODE_SR register field. */
2190 #define ALT_EMAC_DMA_OPERATION_MODE_SR_RESET 0x0
2191 /* Extracts the ALT_EMAC_DMA_OPERATION_MODE_SR field value from a register. */
2192 #define ALT_EMAC_DMA_OPERATION_MODE_SR_GET(value) (((value) & 0x00000002) >> 1)
2193 /* Produces a ALT_EMAC_DMA_OPERATION_MODE_SR register field value suitable for setting the register. */
2194 #define ALT_EMAC_DMA_OPERATION_MODE_SR_SET(value) (((value) << 1) & 0x00000002)
2195 
2196 /*
2197  * Field : OSF
2198  *
2199  * Operate on Second Frame
2200  *
2201  * When this bit is set, it instructs the DMA to process the second frame of the
2202  * Transmit data even before the status for the first frame is obtained.
2203  *
2204  * Field Access Macros:
2205  *
2206  */
2207 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OPERATION_MODE_OSF register field. */
2208 #define ALT_EMAC_DMA_OPERATION_MODE_OSF_LSB 2
2209 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OPERATION_MODE_OSF register field. */
2210 #define ALT_EMAC_DMA_OPERATION_MODE_OSF_MSB 2
2211 /* The width in bits of the ALT_EMAC_DMA_OPERATION_MODE_OSF register field. */
2212 #define ALT_EMAC_DMA_OPERATION_MODE_OSF_WIDTH 1
2213 /* The mask used to set the ALT_EMAC_DMA_OPERATION_MODE_OSF register field value. */
2214 #define ALT_EMAC_DMA_OPERATION_MODE_OSF_SET_MSK 0x00000004
2215 /* The mask used to clear the ALT_EMAC_DMA_OPERATION_MODE_OSF register field value. */
2216 #define ALT_EMAC_DMA_OPERATION_MODE_OSF_CLR_MSK 0xfffffffb
2217 /* The reset value of the ALT_EMAC_DMA_OPERATION_MODE_OSF register field. */
2218 #define ALT_EMAC_DMA_OPERATION_MODE_OSF_RESET 0x0
2219 /* Extracts the ALT_EMAC_DMA_OPERATION_MODE_OSF field value from a register. */
2220 #define ALT_EMAC_DMA_OPERATION_MODE_OSF_GET(value) (((value) & 0x00000004) >> 2)
2221 /* Produces a ALT_EMAC_DMA_OPERATION_MODE_OSF register field value suitable for setting the register. */
2222 #define ALT_EMAC_DMA_OPERATION_MODE_OSF_SET(value) (((value) << 2) & 0x00000004)
2223 
2224 /*
2225  * Field : RTC
2226  *
2227  * Receive Threshold Control
2228  *
2229  * These two bits control the threshold level of the MTL Receive FIFO. Transfer
2230  * (request) to DMA starts when the frame size within the MTL Receive FIFO is
2231  * larger than the threshold. In addition, full frames with length less than the
2232  * threshold are transferred automatically.
2233  *
2234  * The value of 11 is not applicable if the configured Receive FIFO size is 128
2235  * bytes. These bits are valid only when the RSF bit is zero, and are ignored when
2236  * the RSF bit is set to 1.
2237  *
2238  * * 00: 64
2239  *
2240  * * 01: 32
2241  *
2242  * * 10: 96
2243  *
2244  * * 11: 128
2245  *
2246  * Field Access Macros:
2247  *
2248  */
2249 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OPERATION_MODE_RTC register field. */
2250 #define ALT_EMAC_DMA_OPERATION_MODE_RTC_LSB 3
2251 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OPERATION_MODE_RTC register field. */
2252 #define ALT_EMAC_DMA_OPERATION_MODE_RTC_MSB 4
2253 /* The width in bits of the ALT_EMAC_DMA_OPERATION_MODE_RTC register field. */
2254 #define ALT_EMAC_DMA_OPERATION_MODE_RTC_WIDTH 2
2255 /* The mask used to set the ALT_EMAC_DMA_OPERATION_MODE_RTC register field value. */
2256 #define ALT_EMAC_DMA_OPERATION_MODE_RTC_SET_MSK 0x00000018
2257 /* The mask used to clear the ALT_EMAC_DMA_OPERATION_MODE_RTC register field value. */
2258 #define ALT_EMAC_DMA_OPERATION_MODE_RTC_CLR_MSK 0xffffffe7
2259 /* The reset value of the ALT_EMAC_DMA_OPERATION_MODE_RTC register field. */
2260 #define ALT_EMAC_DMA_OPERATION_MODE_RTC_RESET 0x0
2261 /* Extracts the ALT_EMAC_DMA_OPERATION_MODE_RTC field value from a register. */
2262 #define ALT_EMAC_DMA_OPERATION_MODE_RTC_GET(value) (((value) & 0x00000018) >> 3)
2263 /* Produces a ALT_EMAC_DMA_OPERATION_MODE_RTC register field value suitable for setting the register. */
2264 #define ALT_EMAC_DMA_OPERATION_MODE_RTC_SET(value) (((value) << 3) & 0x00000018)
2265 
2266 /*
2267  * Field : DGF
2268  *
2269  * Drop Giant Frames
2270  *
2271  * When set, the MAC drops the received giant frames in the Rx FIFO, that is,
2272  * frames that are larger than the computed giant frame limit. When reset, the MAC
2273  * does not drop the giant frames in the Rx FIFO.
2274  *
2275  * Note: This bit is available in the following configurations in which the giant
2276  * frame status is not provided in Rx status and giant frames are not dropped by
2277  * default:
2278  *
2279  * * Configurations in which IP Checksum Offload (Type 1) is selected in Rx
2280  *
2281  * * Configurations in which the IPC Full Checksum Offload Engine (Type 2) is
2282  * selected in Rx with normal descriptor format
2283  *
2284  * * Configurations in which the Advanced Timestamp feature is selected
2285  *
2286  * In all other configurations, this bit is not used (reserved and always reset).
2287  *
2288  * Field Access Macros:
2289  *
2290  */
2291 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OPERATION_MODE_DGF register field. */
2292 #define ALT_EMAC_DMA_OPERATION_MODE_DGF_LSB 5
2293 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OPERATION_MODE_DGF register field. */
2294 #define ALT_EMAC_DMA_OPERATION_MODE_DGF_MSB 5
2295 /* The width in bits of the ALT_EMAC_DMA_OPERATION_MODE_DGF register field. */
2296 #define ALT_EMAC_DMA_OPERATION_MODE_DGF_WIDTH 1
2297 /* The mask used to set the ALT_EMAC_DMA_OPERATION_MODE_DGF register field value. */
2298 #define ALT_EMAC_DMA_OPERATION_MODE_DGF_SET_MSK 0x00000020
2299 /* The mask used to clear the ALT_EMAC_DMA_OPERATION_MODE_DGF register field value. */
2300 #define ALT_EMAC_DMA_OPERATION_MODE_DGF_CLR_MSK 0xffffffdf
2301 /* The reset value of the ALT_EMAC_DMA_OPERATION_MODE_DGF register field. */
2302 #define ALT_EMAC_DMA_OPERATION_MODE_DGF_RESET 0x0
2303 /* Extracts the ALT_EMAC_DMA_OPERATION_MODE_DGF field value from a register. */
2304 #define ALT_EMAC_DMA_OPERATION_MODE_DGF_GET(value) (((value) & 0x00000020) >> 5)
2305 /* Produces a ALT_EMAC_DMA_OPERATION_MODE_DGF register field value suitable for setting the register. */
2306 #define ALT_EMAC_DMA_OPERATION_MODE_DGF_SET(value) (((value) << 5) & 0x00000020)
2307 
2308 /*
2309  * Field : FUF
2310  *
2311  * Forward Undersized Good Frames
2312  *
2313  * When set, the Rx FIFO forwards Undersized frames (frames with no Error and
2314  * length less than 64 bytes) including pad-bytes and CRC.
2315  *
2316  * When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame
2317  * is already transferred because of the lower value of Receive Threshold, for
2318  * example, RTC = 01.
2319  *
2320  * Field Access Macros:
2321  *
2322  */
2323 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OPERATION_MODE_FUF register field. */
2324 #define ALT_EMAC_DMA_OPERATION_MODE_FUF_LSB 6
2325 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OPERATION_MODE_FUF register field. */
2326 #define ALT_EMAC_DMA_OPERATION_MODE_FUF_MSB 6
2327 /* The width in bits of the ALT_EMAC_DMA_OPERATION_MODE_FUF register field. */
2328 #define ALT_EMAC_DMA_OPERATION_MODE_FUF_WIDTH 1
2329 /* The mask used to set the ALT_EMAC_DMA_OPERATION_MODE_FUF register field value. */
2330 #define ALT_EMAC_DMA_OPERATION_MODE_FUF_SET_MSK 0x00000040
2331 /* The mask used to clear the ALT_EMAC_DMA_OPERATION_MODE_FUF register field value. */
2332 #define ALT_EMAC_DMA_OPERATION_MODE_FUF_CLR_MSK 0xffffffbf
2333 /* The reset value of the ALT_EMAC_DMA_OPERATION_MODE_FUF register field. */
2334 #define ALT_EMAC_DMA_OPERATION_MODE_FUF_RESET 0x0
2335 /* Extracts the ALT_EMAC_DMA_OPERATION_MODE_FUF field value from a register. */
2336 #define ALT_EMAC_DMA_OPERATION_MODE_FUF_GET(value) (((value) & 0x00000040) >> 6)
2337 /* Produces a ALT_EMAC_DMA_OPERATION_MODE_FUF register field value suitable for setting the register. */
2338 #define ALT_EMAC_DMA_OPERATION_MODE_FUF_SET(value) (((value) << 6) & 0x00000040)
2339 
2340 /*
2341  * Field : FEF
2342  *
2343  * Forward Error Frames
2344  *
2345  * When this bit is reset, the Rx FIFO drops frames with error status (CRC error,
2346  * collision error, GMII_ER, giant frame, watchdog timeout, or overflow). However,
2347  * if the start byte (write) pointer of a frame is already transferred to the read
2348  * controller side (in Threshold mode), then the frame is not dropped.
2349  *
2350  * In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled
2351  * during core configuration, the Rx FIFO drops the error frames if that frame's
2352  * start byte is not transferred (output) on the ARI bus.
2353  *
2354  * When the FEF bit is set, all frames except runt error frames are forwarded to
2355  * the DMA. If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial
2356  * frame is written, then the frame is dropped irrespective of the FEF bit setting.
2357  * However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial
2358  * frame is
2359  *
2360  * written, then a partial frame may be forwarded to the DMA.
2361  *
2362  * Note: When FEF bit is reset, the giant frames are dropped if the giant frame
2363  * status is given in Rx Status in the following configurations:
2364  *
2365  * * The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are
2366  * not selected.
2367  *
2368  * * The advanced timestamp feature is not selected but the extended status is
2369  * selected. The extended status is available with the following features:
2370  *
2371  * - L3-L4 filter in GMAC-CORE or GMAC-MTL configurations
2372  *
2373  * - Full checksum offload engine (Type 2) with enhanced descriptor format in
2374  * the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations.
2375  *
2376  * Field Access Macros:
2377  *
2378  */
2379 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OPERATION_MODE_FEF register field. */
2380 #define ALT_EMAC_DMA_OPERATION_MODE_FEF_LSB 7
2381 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OPERATION_MODE_FEF register field. */
2382 #define ALT_EMAC_DMA_OPERATION_MODE_FEF_MSB 7
2383 /* The width in bits of the ALT_EMAC_DMA_OPERATION_MODE_FEF register field. */
2384 #define ALT_EMAC_DMA_OPERATION_MODE_FEF_WIDTH 1
2385 /* The mask used to set the ALT_EMAC_DMA_OPERATION_MODE_FEF register field value. */
2386 #define ALT_EMAC_DMA_OPERATION_MODE_FEF_SET_MSK 0x00000080
2387 /* The mask used to clear the ALT_EMAC_DMA_OPERATION_MODE_FEF register field value. */
2388 #define ALT_EMAC_DMA_OPERATION_MODE_FEF_CLR_MSK 0xffffff7f
2389 /* The reset value of the ALT_EMAC_DMA_OPERATION_MODE_FEF register field. */
2390 #define ALT_EMAC_DMA_OPERATION_MODE_FEF_RESET 0x0
2391 /* Extracts the ALT_EMAC_DMA_OPERATION_MODE_FEF field value from a register. */
2392 #define ALT_EMAC_DMA_OPERATION_MODE_FEF_GET(value) (((value) & 0x00000080) >> 7)
2393 /* Produces a ALT_EMAC_DMA_OPERATION_MODE_FEF register field value suitable for setting the register. */
2394 #define ALT_EMAC_DMA_OPERATION_MODE_FEF_SET(value) (((value) << 7) & 0x00000080)
2395 
2396 /*
2397  * Field : EFC
2398  *
2399  * Enable HW Flow Control
2400  *
2401  * When this bit is set, the flow control signal operation based on the fill-level
2402  * of Rx FIFO is enabled. When reset, the flow control operation is disabled. This
2403  * bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB.
2404  *
2405  * Field Access Macros:
2406  *
2407  */
2408 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OPERATION_MODE_EFC register field. */
2409 #define ALT_EMAC_DMA_OPERATION_MODE_EFC_LSB 8
2410 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OPERATION_MODE_EFC register field. */
2411 #define ALT_EMAC_DMA_OPERATION_MODE_EFC_MSB 8
2412 /* The width in bits of the ALT_EMAC_DMA_OPERATION_MODE_EFC register field. */
2413 #define ALT_EMAC_DMA_OPERATION_MODE_EFC_WIDTH 1
2414 /* The mask used to set the ALT_EMAC_DMA_OPERATION_MODE_EFC register field value. */
2415 #define ALT_EMAC_DMA_OPERATION_MODE_EFC_SET_MSK 0x00000100
2416 /* The mask used to clear the ALT_EMAC_DMA_OPERATION_MODE_EFC register field value. */
2417 #define ALT_EMAC_DMA_OPERATION_MODE_EFC_CLR_MSK 0xfffffeff
2418 /* The reset value of the ALT_EMAC_DMA_OPERATION_MODE_EFC register field. */
2419 #define ALT_EMAC_DMA_OPERATION_MODE_EFC_RESET 0x0
2420 /* Extracts the ALT_EMAC_DMA_OPERATION_MODE_EFC field value from a register. */
2421 #define ALT_EMAC_DMA_OPERATION_MODE_EFC_GET(value) (((value) & 0x00000100) >> 8)
2422 /* Produces a ALT_EMAC_DMA_OPERATION_MODE_EFC register field value suitable for setting the register. */
2423 #define ALT_EMAC_DMA_OPERATION_MODE_EFC_SET(value) (((value) << 8) & 0x00000100)
2424 
2425 /*
2426  * Field : RFA
2427  *
2428  * Threshold for Activating Flow Control (in half-duplex and full-duplex)
2429  *
2430  * These bits control the threshold (Fill level of Rx FIFO) at which the flow
2431  * control is activated.
2432  *
2433  * * 00: Full minus 1 KB, that is, FULL - 1KB
2434  *
2435  * * 01: Full minus 2 KB, that is, FULL - 2KB
2436  *
2437  * * 10: Full minus 3 KB, that is, FULL - 3KB
2438  *
2439  * * 11: Full minus 4 KB, that is, FULL - 4KB
2440  *
2441  * These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8
2442  * (EFC) is set high. If the Rx FIFO is 8 KB or more, an additional Bit (RFA_2) is
2443  * used for more threshold levels as described in Bit 23. These bits are reserved
2444  * and read-only when the depth of Rx FIFO is less than 4 KB.
2445  *
2446  * Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to
2447  * program the value of these bits to 11, the software should not program these
2448  * bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition.
2449  *
2450  * Field Access Macros:
2451  *
2452  */
2453 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OPERATION_MODE_RFA register field. */
2454 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_LSB 9
2455 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OPERATION_MODE_RFA register field. */
2456 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_MSB 10
2457 /* The width in bits of the ALT_EMAC_DMA_OPERATION_MODE_RFA register field. */
2458 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_WIDTH 2
2459 /* The mask used to set the ALT_EMAC_DMA_OPERATION_MODE_RFA register field value. */
2460 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_SET_MSK 0x00000600
2461 /* The mask used to clear the ALT_EMAC_DMA_OPERATION_MODE_RFA register field value. */
2462 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_CLR_MSK 0xfffff9ff
2463 /* The reset value of the ALT_EMAC_DMA_OPERATION_MODE_RFA register field. */
2464 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_RESET 0x0
2465 /* Extracts the ALT_EMAC_DMA_OPERATION_MODE_RFA field value from a register. */
2466 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_GET(value) (((value) & 0x00000600) >> 9)
2467 /* Produces a ALT_EMAC_DMA_OPERATION_MODE_RFA register field value suitable for setting the register. */
2468 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_SET(value) (((value) << 9) & 0x00000600)
2469 
2470 /*
2471  * Field : RFD
2472  *
2473  * Threshold for Deactivating Flow Control (in half-duplex and full-duplex)
2474  *
2475  * These bits control the threshold (Fill-level of Rx FIFO) at which the flow
2476  * control is de-asserted after activation.
2477  *
2478  * * 00: Full minus 1 KB, that is, FULL - 1KB
2479  *
2480  * * 01: Full minus 2 KB, that is, FULL - 2KB
2481  *
2482  * * 10: Full minus 3 KB, that is, FULL - 3KB
2483  *
2484  * * 11: Full minus 4 KB, that is, FULL - 4KB
2485  *
2486  * The de-assertion is effective only after flow control is asserted. If the Rx
2487  * FIFO is 8 KB or more, an additional bit (RFD_2) is used for more threshold
2488  * levels as described in Bit 22. These bits are reserved and read-only when the Rx
2489  * FIFO depth is less than 4 KB.
2490  *
2491  * Note: For proper flow control, the value programmed in the "RFD_2, RFD" fields
2492  * should be equal to or more than the value programmed in the "RFA_2, RFA" fields.
2493  *
2494  * Field Access Macros:
2495  *
2496  */
2497 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OPERATION_MODE_RFD register field. */
2498 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_LSB 11
2499 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OPERATION_MODE_RFD register field. */
2500 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_MSB 12
2501 /* The width in bits of the ALT_EMAC_DMA_OPERATION_MODE_RFD register field. */
2502 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_WIDTH 2
2503 /* The mask used to set the ALT_EMAC_DMA_OPERATION_MODE_RFD register field value. */
2504 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_SET_MSK 0x00001800
2505 /* The mask used to clear the ALT_EMAC_DMA_OPERATION_MODE_RFD register field value. */
2506 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_CLR_MSK 0xffffe7ff
2507 /* The reset value of the ALT_EMAC_DMA_OPERATION_MODE_RFD register field. */
2508 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_RESET 0x0
2509 /* Extracts the ALT_EMAC_DMA_OPERATION_MODE_RFD field value from a register. */
2510 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_GET(value) (((value) & 0x00001800) >> 11)
2511 /* Produces a ALT_EMAC_DMA_OPERATION_MODE_RFD register field value suitable for setting the register. */
2512 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_SET(value) (((value) << 11) & 0x00001800)
2513 
2514 /*
2515  * Field : ST
2516  *
2517  * Start or Stop Transmission Command
2518  *
2519  * When this bit is set, transmission is placed in the Running state, and the DMA
2520  * checks the Transmit List at the current position for a frame to be transmitted.
2521  * Descriptor acquisition is attempted either from the current position in the
2522  * list, which is the Transmit List Base Address set by Register 4 (Transmit
2523  * Descriptor List Address Register), or from the position retained when
2524  * transmission was stopped previously. If the DMA does not own the current
2525  * descriptor, transmission enters the Suspended state and Bit 2 (Transmit Buffer
2526  * Unavailable) of Register 5 (Status Register) is set. The Start Transmission
2527  * command is effective only when transmission is stopped. If the command is issued
2528  * before setting Register 4 (Transmit Descriptor List Address Register), then the
2529  * DMA behavior is unpredictable.
2530  *
2531  * When this bit is reset, the transmission process is placed in the Stopped state
2532  * after completing the transmission of the current frame. The Next Descriptor
2533  * position in the Transmit List is saved, and it becomes the current position when
2534  * transmission is restarted. To change the list address, you need to program
2535  * Register 4 (Transmit Descriptor List Address Register) with a new value when
2536  * this bit is reset. The new value is considered when this bit is set again. The
2537  * stop transmission command is effective only when the transmission of the current
2538  * frame is complete or the transmission is in the Suspended state.
2539  *
2540  * Field Access Macros:
2541  *
2542  */
2543 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OPERATION_MODE_ST register field. */
2544 #define ALT_EMAC_DMA_OPERATION_MODE_ST_LSB 13
2545 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OPERATION_MODE_ST register field. */
2546 #define ALT_EMAC_DMA_OPERATION_MODE_ST_MSB 13
2547 /* The width in bits of the ALT_EMAC_DMA_OPERATION_MODE_ST register field. */
2548 #define ALT_EMAC_DMA_OPERATION_MODE_ST_WIDTH 1
2549 /* The mask used to set the ALT_EMAC_DMA_OPERATION_MODE_ST register field value. */
2550 #define ALT_EMAC_DMA_OPERATION_MODE_ST_SET_MSK 0x00002000
2551 /* The mask used to clear the ALT_EMAC_DMA_OPERATION_MODE_ST register field value. */
2552 #define ALT_EMAC_DMA_OPERATION_MODE_ST_CLR_MSK 0xffffdfff
2553 /* The reset value of the ALT_EMAC_DMA_OPERATION_MODE_ST register field. */
2554 #define ALT_EMAC_DMA_OPERATION_MODE_ST_RESET 0x0
2555 /* Extracts the ALT_EMAC_DMA_OPERATION_MODE_ST field value from a register. */
2556 #define ALT_EMAC_DMA_OPERATION_MODE_ST_GET(value) (((value) & 0x00002000) >> 13)
2557 /* Produces a ALT_EMAC_DMA_OPERATION_MODE_ST register field value suitable for setting the register. */
2558 #define ALT_EMAC_DMA_OPERATION_MODE_ST_SET(value) (((value) << 13) & 0x00002000)
2559 
2560 /*
2561  * Field : TTC
2562  *
2563  * Transmit Threshold Control
2564  *
2565  * These bits control the threshold level of the MTL Transmit FIFO. Transmission
2566  * starts when the frame size within the MTL Transmit FIFO is larger than the
2567  * threshold. In addition, full frames with a length less than the threshold are
2568  * also transmitted. These bits are used only when Bit 21 (TSF) is reset.
2569  *
2570  * * 000: 64
2571  *
2572  * * 001: 128
2573  *
2574  * * 010: 192
2575  *
2576  * * 011: 256
2577  *
2578  * * 100: 40
2579  *
2580  * * 101: 32
2581  *
2582  * * 110: 24
2583  *
2584  * * 111: 16
2585  *
2586  * Field Access Macros:
2587  *
2588  */
2589 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OPERATION_MODE_TTC register field. */
2590 #define ALT_EMAC_DMA_OPERATION_MODE_TTC_LSB 14
2591 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OPERATION_MODE_TTC register field. */
2592 #define ALT_EMAC_DMA_OPERATION_MODE_TTC_MSB 16
2593 /* The width in bits of the ALT_EMAC_DMA_OPERATION_MODE_TTC register field. */
2594 #define ALT_EMAC_DMA_OPERATION_MODE_TTC_WIDTH 3
2595 /* The mask used to set the ALT_EMAC_DMA_OPERATION_MODE_TTC register field value. */
2596 #define ALT_EMAC_DMA_OPERATION_MODE_TTC_SET_MSK 0x0001c000
2597 /* The mask used to clear the ALT_EMAC_DMA_OPERATION_MODE_TTC register field value. */
2598 #define ALT_EMAC_DMA_OPERATION_MODE_TTC_CLR_MSK 0xfffe3fff
2599 /* The reset value of the ALT_EMAC_DMA_OPERATION_MODE_TTC register field. */
2600 #define ALT_EMAC_DMA_OPERATION_MODE_TTC_RESET 0x0
2601 /* Extracts the ALT_EMAC_DMA_OPERATION_MODE_TTC field value from a register. */
2602 #define ALT_EMAC_DMA_OPERATION_MODE_TTC_GET(value) (((value) & 0x0001c000) >> 14)
2603 /* Produces a ALT_EMAC_DMA_OPERATION_MODE_TTC register field value suitable for setting the register. */
2604 #define ALT_EMAC_DMA_OPERATION_MODE_TTC_SET(value) (((value) << 14) & 0x0001c000)
2605 
2606 /*
2607  * Field : Reserved_19_17
2608  *
2609  * Reserved
2610  *
2611  * Field Access Macros:
2612  *
2613  */
2614 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17 register field. */
2615 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17_LSB 17
2616 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17 register field. */
2617 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17_MSB 19
2618 /* The width in bits of the ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17 register field. */
2619 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17_WIDTH 3
2620 /* The mask used to set the ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17 register field value. */
2621 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17_SET_MSK 0x000e0000
2622 /* The mask used to clear the ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17 register field value. */
2623 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17_CLR_MSK 0xfff1ffff
2624 /* The reset value of the ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17 register field. */
2625 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17_RESET 0x0
2626 /* Extracts the ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17 field value from a register. */
2627 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17_GET(value) (((value) & 0x000e0000) >> 17)
2628 /* Produces a ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17 register field value suitable for setting the register. */
2629 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17_SET(value) (((value) << 17) & 0x000e0000)
2630 
2631 /*
2632  * Field : FTF
2633  *
2634  * Flush Transmit FIFO
2635  *
2636  * When this bit is set, the transmit FIFO controller logic is reset to its default
2637  * values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared
2638  * internally when the flushing operation is completed. The Operation Mode register
2639  * should not be written to until this bit is cleared. The data which is already
2640  * accepted by the MAC transmitter is not flushed. It is scheduled for transmission
2641  * and results in underflow and runt frame transmission.
2642  *
2643  * Note: The flush operation is complete only when the Tx FIFO is emptied of its
2644  * contents and all the pending Transmit Status of the transmitted frames are
2645  * accepted by the host. To complete this flush operation, the PHY transmit clock
2646  * (clk_tx_i) is required to be active.
2647  *
2648  * Field Access Macros:
2649  *
2650  */
2651 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OPERATION_MODE_FTF register field. */
2652 #define ALT_EMAC_DMA_OPERATION_MODE_FTF_LSB 20
2653 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OPERATION_MODE_FTF register field. */
2654 #define ALT_EMAC_DMA_OPERATION_MODE_FTF_MSB 20
2655 /* The width in bits of the ALT_EMAC_DMA_OPERATION_MODE_FTF register field. */
2656 #define ALT_EMAC_DMA_OPERATION_MODE_FTF_WIDTH 1
2657 /* The mask used to set the ALT_EMAC_DMA_OPERATION_MODE_FTF register field value. */
2658 #define ALT_EMAC_DMA_OPERATION_MODE_FTF_SET_MSK 0x00100000
2659 /* The mask used to clear the ALT_EMAC_DMA_OPERATION_MODE_FTF register field value. */
2660 #define ALT_EMAC_DMA_OPERATION_MODE_FTF_CLR_MSK 0xffefffff
2661 /* The reset value of the ALT_EMAC_DMA_OPERATION_MODE_FTF register field. */
2662 #define ALT_EMAC_DMA_OPERATION_MODE_FTF_RESET 0x0
2663 /* Extracts the ALT_EMAC_DMA_OPERATION_MODE_FTF field value from a register. */
2664 #define ALT_EMAC_DMA_OPERATION_MODE_FTF_GET(value) (((value) & 0x00100000) >> 20)
2665 /* Produces a ALT_EMAC_DMA_OPERATION_MODE_FTF register field value suitable for setting the register. */
2666 #define ALT_EMAC_DMA_OPERATION_MODE_FTF_SET(value) (((value) << 20) & 0x00100000)
2667 
2668 /*
2669  * Field : TSF
2670  *
2671  * Transmit Store and Forward
2672  *
2673  * When this bit is set, transmission starts when a full frame resides in the MTL
2674  * Transmit FIFO. When this bit is set, the TTC values specified in Bits[16:14] are
2675  * ignored. This bit should be changed only when the transmission is stopped.
2676  *
2677  * Field Access Macros:
2678  *
2679  */
2680 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OPERATION_MODE_TSF register field. */
2681 #define ALT_EMAC_DMA_OPERATION_MODE_TSF_LSB 21
2682 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OPERATION_MODE_TSF register field. */
2683 #define ALT_EMAC_DMA_OPERATION_MODE_TSF_MSB 21
2684 /* The width in bits of the ALT_EMAC_DMA_OPERATION_MODE_TSF register field. */
2685 #define ALT_EMAC_DMA_OPERATION_MODE_TSF_WIDTH 1
2686 /* The mask used to set the ALT_EMAC_DMA_OPERATION_MODE_TSF register field value. */
2687 #define ALT_EMAC_DMA_OPERATION_MODE_TSF_SET_MSK 0x00200000
2688 /* The mask used to clear the ALT_EMAC_DMA_OPERATION_MODE_TSF register field value. */
2689 #define ALT_EMAC_DMA_OPERATION_MODE_TSF_CLR_MSK 0xffdfffff
2690 /* The reset value of the ALT_EMAC_DMA_OPERATION_MODE_TSF register field. */
2691 #define ALT_EMAC_DMA_OPERATION_MODE_TSF_RESET 0x0
2692 /* Extracts the ALT_EMAC_DMA_OPERATION_MODE_TSF field value from a register. */
2693 #define ALT_EMAC_DMA_OPERATION_MODE_TSF_GET(value) (((value) & 0x00200000) >> 21)
2694 /* Produces a ALT_EMAC_DMA_OPERATION_MODE_TSF register field value suitable for setting the register. */
2695 #define ALT_EMAC_DMA_OPERATION_MODE_TSF_SET(value) (((value) << 21) & 0x00200000)
2696 
2697 /*
2698  * Field : RFD_2
2699  *
2700  * MSB of Threshold for Deactivating Flow Control
2701  *
2702  * If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, this bit (when
2703  * set) provides additional threshold levels for deactivating the flow control in
2704  * both half-duplex and full-duplex modes. This bit (as Most Significant Bit) along
2705  * with the RFD (Bits[12:11]) gives the following thresholds for deactivating flow
2706  * control:
2707  *
2708  * * 100: Full minus 5 KB, that is, FULL - 5KB
2709  *
2710  * * 101: Full minus 6 KB, that is, FULL - 6KB
2711  *
2712  * * 110: Full minus 7 KB, that is, FULL - 7KB
2713  *
2714  * * 111: Reserved
2715  *
2716  * This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep.
2717  *
2718  * Field Access Macros:
2719  *
2720  */
2721 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OPERATION_MODE_RFD_2 register field. */
2722 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_2_LSB 22
2723 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OPERATION_MODE_RFD_2 register field. */
2724 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_2_MSB 22
2725 /* The width in bits of the ALT_EMAC_DMA_OPERATION_MODE_RFD_2 register field. */
2726 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_2_WIDTH 1
2727 /* The mask used to set the ALT_EMAC_DMA_OPERATION_MODE_RFD_2 register field value. */
2728 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_2_SET_MSK 0x00400000
2729 /* The mask used to clear the ALT_EMAC_DMA_OPERATION_MODE_RFD_2 register field value. */
2730 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_2_CLR_MSK 0xffbfffff
2731 /* The reset value of the ALT_EMAC_DMA_OPERATION_MODE_RFD_2 register field. */
2732 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_2_RESET 0x0
2733 /* Extracts the ALT_EMAC_DMA_OPERATION_MODE_RFD_2 field value from a register. */
2734 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_2_GET(value) (((value) & 0x00400000) >> 22)
2735 /* Produces a ALT_EMAC_DMA_OPERATION_MODE_RFD_2 register field value suitable for setting the register. */
2736 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_2_SET(value) (((value) << 22) & 0x00400000)
2737 
2738 /*
2739  * Field : RFA_2
2740  *
2741  * MSB of Threshold for Activating Flow Control
2742  *
2743  * If the DWC_gmac is configured for an Rx FIFO depth of 8 KB or more, this bit
2744  * (when set) provides additional threshold levels for activating the flow control
2745  * in both half-duplex and full-duplex modes. This bit (as Most Significant Bit)
2746  * along with the RFA (Bits[10:9]) gives the following thresholds for activating
2747  * flow control:
2748  *
2749  * * 100: Full minus 5 KB, that is, FULL - 5KB
2750  *
2751  * * 101: Full minus 6 KB, that is, FULL - 6KB
2752  *
2753  * * 110: Full minus 7 KB, that is, FULL - 7KB
2754  *
2755  * * 111: Reserved
2756  *
2757  * This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep.
2758  *
2759  * Field Access Macros:
2760  *
2761  */
2762 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OPERATION_MODE_RFA_2 register field. */
2763 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_2_LSB 23
2764 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OPERATION_MODE_RFA_2 register field. */
2765 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_2_MSB 23
2766 /* The width in bits of the ALT_EMAC_DMA_OPERATION_MODE_RFA_2 register field. */
2767 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_2_WIDTH 1
2768 /* The mask used to set the ALT_EMAC_DMA_OPERATION_MODE_RFA_2 register field value. */
2769 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_2_SET_MSK 0x00800000
2770 /* The mask used to clear the ALT_EMAC_DMA_OPERATION_MODE_RFA_2 register field value. */
2771 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_2_CLR_MSK 0xff7fffff
2772 /* The reset value of the ALT_EMAC_DMA_OPERATION_MODE_RFA_2 register field. */
2773 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_2_RESET 0x0
2774 /* Extracts the ALT_EMAC_DMA_OPERATION_MODE_RFA_2 field value from a register. */
2775 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_2_GET(value) (((value) & 0x00800000) >> 23)
2776 /* Produces a ALT_EMAC_DMA_OPERATION_MODE_RFA_2 register field value suitable for setting the register. */
2777 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_2_SET(value) (((value) << 23) & 0x00800000)
2778 
2779 /*
2780  * Field : DFF
2781  *
2782  * Disable Flushing of Received Frames
2783  *
2784  * When this bit is set, the Rx DMA does not flush any frames because of the
2785  * unavailability of receive descriptors or buffers as it does normally when this
2786  * bit is reset.
2787  *
2788  * This bit is reserved (and RO) in the GMAC-MTL configuration.
2789  *
2790  * Field Access Macros:
2791  *
2792  */
2793 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OPERATION_MODE_DFF register field. */
2794 #define ALT_EMAC_DMA_OPERATION_MODE_DFF_LSB 24
2795 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OPERATION_MODE_DFF register field. */
2796 #define ALT_EMAC_DMA_OPERATION_MODE_DFF_MSB 24
2797 /* The width in bits of the ALT_EMAC_DMA_OPERATION_MODE_DFF register field. */
2798 #define ALT_EMAC_DMA_OPERATION_MODE_DFF_WIDTH 1
2799 /* The mask used to set the ALT_EMAC_DMA_OPERATION_MODE_DFF register field value. */
2800 #define ALT_EMAC_DMA_OPERATION_MODE_DFF_SET_MSK 0x01000000
2801 /* The mask used to clear the ALT_EMAC_DMA_OPERATION_MODE_DFF register field value. */
2802 #define ALT_EMAC_DMA_OPERATION_MODE_DFF_CLR_MSK 0xfeffffff
2803 /* The reset value of the ALT_EMAC_DMA_OPERATION_MODE_DFF register field. */
2804 #define ALT_EMAC_DMA_OPERATION_MODE_DFF_RESET 0x0
2805 /* Extracts the ALT_EMAC_DMA_OPERATION_MODE_DFF field value from a register. */
2806 #define ALT_EMAC_DMA_OPERATION_MODE_DFF_GET(value) (((value) & 0x01000000) >> 24)
2807 /* Produces a ALT_EMAC_DMA_OPERATION_MODE_DFF register field value suitable for setting the register. */
2808 #define ALT_EMAC_DMA_OPERATION_MODE_DFF_SET(value) (((value) << 24) & 0x01000000)
2809 
2810 /*
2811  * Field : RSF
2812  *
2813  * Receive Store and Forward
2814  *
2815  * When this bit is set, the MTL reads a frame from the Rx FIFO only after the
2816  * complete frame has been written to it, ignoring the RTC bits. When this bit is
2817  * reset, the Rx FIFO operates in the cut-through mode, subject to the threshold
2818  * specified by the RTC bits.
2819  *
2820  * Field Access Macros:
2821  *
2822  */
2823 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OPERATION_MODE_RSF register field. */
2824 #define ALT_EMAC_DMA_OPERATION_MODE_RSF_LSB 25
2825 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OPERATION_MODE_RSF register field. */
2826 #define ALT_EMAC_DMA_OPERATION_MODE_RSF_MSB 25
2827 /* The width in bits of the ALT_EMAC_DMA_OPERATION_MODE_RSF register field. */
2828 #define ALT_EMAC_DMA_OPERATION_MODE_RSF_WIDTH 1
2829 /* The mask used to set the ALT_EMAC_DMA_OPERATION_MODE_RSF register field value. */
2830 #define ALT_EMAC_DMA_OPERATION_MODE_RSF_SET_MSK 0x02000000
2831 /* The mask used to clear the ALT_EMAC_DMA_OPERATION_MODE_RSF register field value. */
2832 #define ALT_EMAC_DMA_OPERATION_MODE_RSF_CLR_MSK 0xfdffffff
2833 /* The reset value of the ALT_EMAC_DMA_OPERATION_MODE_RSF register field. */
2834 #define ALT_EMAC_DMA_OPERATION_MODE_RSF_RESET 0x0
2835 /* Extracts the ALT_EMAC_DMA_OPERATION_MODE_RSF field value from a register. */
2836 #define ALT_EMAC_DMA_OPERATION_MODE_RSF_GET(value) (((value) & 0x02000000) >> 25)
2837 /* Produces a ALT_EMAC_DMA_OPERATION_MODE_RSF register field value suitable for setting the register. */
2838 #define ALT_EMAC_DMA_OPERATION_MODE_RSF_SET(value) (((value) << 25) & 0x02000000)
2839 
2840 /*
2841  * Field : DT
2842  *
2843  * Disable Dropping of TCP/IP Checksum Error Frames
2844  *
2845  * When this bit is set, the MAC does not drop the frames which only have errors
2846  * detected by the Receive Checksum Offload engine. Such frames do not have any
2847  * errors (including FCS error) in the Ethernet frame received by the MAC but have
2848  * errors only in the encapsulated payload. When this bit is reset, all error
2849  * frames are dropped if the FEF bit is reset.
2850  *
2851  * If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is
2852  * reserved (RO with value 1'b0).
2853  *
2854  * Field Access Macros:
2855  *
2856  */
2857 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OPERATION_MODE_DT register field. */
2858 #define ALT_EMAC_DMA_OPERATION_MODE_DT_LSB 26
2859 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OPERATION_MODE_DT register field. */
2860 #define ALT_EMAC_DMA_OPERATION_MODE_DT_MSB 26
2861 /* The width in bits of the ALT_EMAC_DMA_OPERATION_MODE_DT register field. */
2862 #define ALT_EMAC_DMA_OPERATION_MODE_DT_WIDTH 1
2863 /* The mask used to set the ALT_EMAC_DMA_OPERATION_MODE_DT register field value. */
2864 #define ALT_EMAC_DMA_OPERATION_MODE_DT_SET_MSK 0x04000000
2865 /* The mask used to clear the ALT_EMAC_DMA_OPERATION_MODE_DT register field value. */
2866 #define ALT_EMAC_DMA_OPERATION_MODE_DT_CLR_MSK 0xfbffffff
2867 /* The reset value of the ALT_EMAC_DMA_OPERATION_MODE_DT register field. */
2868 #define ALT_EMAC_DMA_OPERATION_MODE_DT_RESET 0x0
2869 /* Extracts the ALT_EMAC_DMA_OPERATION_MODE_DT field value from a register. */
2870 #define ALT_EMAC_DMA_OPERATION_MODE_DT_GET(value) (((value) & 0x04000000) >> 26)
2871 /* Produces a ALT_EMAC_DMA_OPERATION_MODE_DT register field value suitable for setting the register. */
2872 #define ALT_EMAC_DMA_OPERATION_MODE_DT_SET(value) (((value) << 26) & 0x04000000)
2873 
2874 /*
2875  * Field : Reserved_31_27
2876  *
2877  * Reserved
2878  *
2879  * Field Access Macros:
2880  *
2881  */
2882 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27 register field. */
2883 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27_LSB 27
2884 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27 register field. */
2885 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27_MSB 31
2886 /* The width in bits of the ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27 register field. */
2887 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27_WIDTH 5
2888 /* The mask used to set the ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27 register field value. */
2889 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27_SET_MSK 0xf8000000
2890 /* The mask used to clear the ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27 register field value. */
2891 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27_CLR_MSK 0x07ffffff
2892 /* The reset value of the ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27 register field. */
2893 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27_RESET 0x0
2894 /* Extracts the ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27 field value from a register. */
2895 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27_GET(value) (((value) & 0xf8000000) >> 27)
2896 /* Produces a ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27 register field value suitable for setting the register. */
2897 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27_SET(value) (((value) << 27) & 0xf8000000)
2898 
2899 #ifndef __ASSEMBLY__
2900 /*
2901  * WARNING: The C register and register group struct declarations are provided for
2902  * convenience and illustrative purposes. They should, however, be used with
2903  * caution as the C language standard provides no guarantees about the alignment or
2904  * atomicity of device memory accesses. The recommended practice for writing
2905  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2906  * alt_write_word() functions.
2907  *
2908  * The struct declaration for register ALT_EMAC_DMA_OPERATION_MODE.
2909  */
2910 struct ALT_EMAC_DMA_OPERATION_MODE_s
2911 {
2912  const volatile uint32_t Reserved_0 : 1; /* ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0 */
2913  volatile uint32_t SR : 1; /* ALT_EMAC_DMA_OPERATION_MODE_SR */
2914  volatile uint32_t OSF : 1; /* ALT_EMAC_DMA_OPERATION_MODE_OSF */
2915  volatile uint32_t RTC : 2; /* ALT_EMAC_DMA_OPERATION_MODE_RTC */
2916  volatile uint32_t DGF : 1; /* ALT_EMAC_DMA_OPERATION_MODE_DGF */
2917  volatile uint32_t FUF : 1; /* ALT_EMAC_DMA_OPERATION_MODE_FUF */
2918  volatile uint32_t FEF : 1; /* ALT_EMAC_DMA_OPERATION_MODE_FEF */
2919  volatile uint32_t EFC : 1; /* ALT_EMAC_DMA_OPERATION_MODE_EFC */
2920  volatile uint32_t RFA : 2; /* ALT_EMAC_DMA_OPERATION_MODE_RFA */
2921  volatile uint32_t RFD : 2; /* ALT_EMAC_DMA_OPERATION_MODE_RFD */
2922  volatile uint32_t ST : 1; /* ALT_EMAC_DMA_OPERATION_MODE_ST */
2923  volatile uint32_t TTC : 3; /* ALT_EMAC_DMA_OPERATION_MODE_TTC */
2924  const volatile uint32_t Reserved_19_17 : 3; /* ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17 */
2925  volatile uint32_t FTF : 1; /* ALT_EMAC_DMA_OPERATION_MODE_FTF */
2926  volatile uint32_t TSF : 1; /* ALT_EMAC_DMA_OPERATION_MODE_TSF */
2927  volatile uint32_t RFD_2 : 1; /* ALT_EMAC_DMA_OPERATION_MODE_RFD_2 */
2928  volatile uint32_t RFA_2 : 1; /* ALT_EMAC_DMA_OPERATION_MODE_RFA_2 */
2929  volatile uint32_t DFF : 1; /* ALT_EMAC_DMA_OPERATION_MODE_DFF */
2930  volatile uint32_t RSF : 1; /* ALT_EMAC_DMA_OPERATION_MODE_RSF */
2931  volatile uint32_t DT : 1; /* ALT_EMAC_DMA_OPERATION_MODE_DT */
2932  const volatile uint32_t Reserved_31_27 : 5; /* ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27 */
2933 };
2934 
2935 /* The typedef declaration for register ALT_EMAC_DMA_OPERATION_MODE. */
2936 typedef struct ALT_EMAC_DMA_OPERATION_MODE_s ALT_EMAC_DMA_OPERATION_MODE_t;
2937 #endif /* __ASSEMBLY__ */
2938 
2939 /* The reset value of the ALT_EMAC_DMA_OPERATION_MODE register. */
2940 #define ALT_EMAC_DMA_OPERATION_MODE_RESET 0x00000000
2941 /* The byte offset of the ALT_EMAC_DMA_OPERATION_MODE register from the beginning of the component. */
2942 #define ALT_EMAC_DMA_OPERATION_MODE_OFST 0x18
2943 /* The address of the ALT_EMAC_DMA_OPERATION_MODE register. */
2944 #define ALT_EMAC_DMA_OPERATION_MODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_OPERATION_MODE_OFST))
2945 
2946 /*
2947  * Register : Interrupt_Enable
2948  *
2949  * <b> Register 7 (Interrupt Enable Register) </b>
2950  *
2951  * The Interrupt Enable register enables the interrupts reported by Register 5
2952  * (Status Register). Setting a bit to 1'b1 enables a corresponding interrupt.
2953  * After a hardware or software reset, all interrupts are disabled.
2954  *
2955  * Register Layout
2956  *
2957  * Bits | Access | Reset | Description
2958  * :--------|:-------|:------|:---------------------------------------------
2959  * [0] | RW | 0x0 | ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE
2960  * [1] | RW | 0x0 | ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE
2961  * [2] | RW | 0x0 | ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE
2962  * [3] | RW | 0x0 | ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE
2963  * [4] | RW | 0x0 | ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE
2964  * [5] | RW | 0x0 | ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE
2965  * [6] | RW | 0x0 | ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE
2966  * [7] | RW | 0x0 | ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE
2967  * [8] | RW | 0x0 | ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE
2968  * [9] | RW | 0x0 | ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE
2969  * [10] | RW | 0x0 | ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE
2970  * [12:11] | R | 0x0 | ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11
2971  * [13] | RW | 0x0 | ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE
2972  * [14] | RW | 0x0 | ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE
2973  * [15] | RW | 0x0 | ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE
2974  * [16] | RW | 0x0 | ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE
2975  * [31:17] | R | 0x0 | ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17
2976  *
2977  */
2978 /*
2979  * Field : TIE
2980  *
2981  * Transmit Interrupt Enable
2982  *
2983  * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit
2984  * Interrupt is enabled. When this bit is reset, the Transmit Interrupt is
2985  * disabled.
2986  *
2987  * Field Access Macros:
2988  *
2989  */
2990 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE register field. */
2991 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE_LSB 0
2992 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE register field. */
2993 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE_MSB 0
2994 /* The width in bits of the ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE register field. */
2995 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE_WIDTH 1
2996 /* The mask used to set the ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE register field value. */
2997 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE_SET_MSK 0x00000001
2998 /* The mask used to clear the ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE register field value. */
2999 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE_CLR_MSK 0xfffffffe
3000 /* The reset value of the ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE register field. */
3001 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE_RESET 0x0
3002 /* Extracts the ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE field value from a register. */
3003 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE_GET(value) (((value) & 0x00000001) >> 0)
3004 /* Produces a ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE register field value suitable for setting the register. */
3005 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE_SET(value) (((value) << 0) & 0x00000001)
3006 
3007 /*
3008  * Field : TSE
3009  *
3010  * Transmit Stopped Enable
3011  *
3012  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
3013  * Transmission Stopped Interrupt is enabled. When this bit is reset, the
3014  * Transmission Stopped Interrupt is disabled.
3015  *
3016  * Field Access Macros:
3017  *
3018  */
3019 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE register field. */
3020 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE_LSB 1
3021 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE register field. */
3022 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE_MSB 1
3023 /* The width in bits of the ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE register field. */
3024 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE_WIDTH 1
3025 /* The mask used to set the ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE register field value. */
3026 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE_SET_MSK 0x00000002
3027 /* The mask used to clear the ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE register field value. */
3028 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE_CLR_MSK 0xfffffffd
3029 /* The reset value of the ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE register field. */
3030 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE_RESET 0x0
3031 /* Extracts the ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE field value from a register. */
3032 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE_GET(value) (((value) & 0x00000002) >> 1)
3033 /* Produces a ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE register field value suitable for setting the register. */
3034 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE_SET(value) (((value) << 1) & 0x00000002)
3035 
3036 /*
3037  * Field : TUE
3038  *
3039  * Transmit Buffer Unavailable Enable
3040  *
3041  * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit
3042  * Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit
3043  * Buffer Unavailable Interrupt is disabled.
3044  *
3045  * Field Access Macros:
3046  *
3047  */
3048 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE register field. */
3049 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE_LSB 2
3050 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE register field. */
3051 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE_MSB 2
3052 /* The width in bits of the ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE register field. */
3053 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE_WIDTH 1
3054 /* The mask used to set the ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE register field value. */
3055 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE_SET_MSK 0x00000004
3056 /* The mask used to clear the ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE register field value. */
3057 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE_CLR_MSK 0xfffffffb
3058 /* The reset value of the ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE register field. */
3059 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE_RESET 0x0
3060 /* Extracts the ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE field value from a register. */
3061 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE_GET(value) (((value) & 0x00000004) >> 2)
3062 /* Produces a ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE register field value suitable for setting the register. */
3063 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE_SET(value) (((value) << 2) & 0x00000004)
3064 
3065 /*
3066  * Field : TJE
3067  *
3068  * Transmit Jabber Timeout Enable
3069  *
3070  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
3071  * Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the
3072  * Transmit Jabber Timeout Interrupt is disabled.
3073  *
3074  * Field Access Macros:
3075  *
3076  */
3077 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE register field. */
3078 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE_LSB 3
3079 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE register field. */
3080 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE_MSB 3
3081 /* The width in bits of the ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE register field. */
3082 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE_WIDTH 1
3083 /* The mask used to set the ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE register field value. */
3084 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE_SET_MSK 0x00000008
3085 /* The mask used to clear the ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE register field value. */
3086 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE_CLR_MSK 0xfffffff7
3087 /* The reset value of the ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE register field. */
3088 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE_RESET 0x0
3089 /* Extracts the ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE field value from a register. */
3090 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE_GET(value) (((value) & 0x00000008) >> 3)
3091 /* Produces a ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE register field value suitable for setting the register. */
3092 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE_SET(value) (((value) << 3) & 0x00000008)
3093 
3094 /*
3095  * Field : OVE
3096  *
3097  * Overflow Interrupt Enable
3098  *
3099  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
3100  * Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow
3101  * Interrupt is disabled.
3102  *
3103  * Field Access Macros:
3104  *
3105  */
3106 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE register field. */
3107 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE_LSB 4
3108 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE register field. */
3109 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE_MSB 4
3110 /* The width in bits of the ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE register field. */
3111 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE_WIDTH 1
3112 /* The mask used to set the ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE register field value. */
3113 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE_SET_MSK 0x00000010
3114 /* The mask used to clear the ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE register field value. */
3115 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE_CLR_MSK 0xffffffef
3116 /* The reset value of the ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE register field. */
3117 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE_RESET 0x0
3118 /* Extracts the ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE field value from a register. */
3119 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE_GET(value) (((value) & 0x00000010) >> 4)
3120 /* Produces a ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE register field value suitable for setting the register. */
3121 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE_SET(value) (((value) << 4) & 0x00000010)
3122 
3123 /*
3124  * Field : UNE
3125  *
3126  * Underflow Interrupt Enable
3127  *
3128  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
3129  * Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow
3130  * Interrupt is disabled.
3131  *
3132  * Field Access Macros:
3133  *
3134  */
3135 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE register field. */
3136 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE_LSB 5
3137 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE register field. */
3138 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE_MSB 5
3139 /* The width in bits of the ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE register field. */
3140 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE_WIDTH 1
3141 /* The mask used to set the ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE register field value. */
3142 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE_SET_MSK 0x00000020
3143 /* The mask used to clear the ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE register field value. */
3144 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE_CLR_MSK 0xffffffdf
3145 /* The reset value of the ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE register field. */
3146 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE_RESET 0x0
3147 /* Extracts the ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE field value from a register. */
3148 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE_GET(value) (((value) & 0x00000020) >> 5)
3149 /* Produces a ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE register field value suitable for setting the register. */
3150 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE_SET(value) (((value) << 5) & 0x00000020)
3151 
3152 /*
3153  * Field : RIE
3154  *
3155  * Receive Interrupt Enable
3156  *
3157  * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive
3158  * Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled.
3159  *
3160  * Field Access Macros:
3161  *
3162  */
3163 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE register field. */
3164 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE_LSB 6
3165 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE register field. */
3166 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE_MSB 6
3167 /* The width in bits of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE register field. */
3168 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE_WIDTH 1
3169 /* The mask used to set the ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE register field value. */
3170 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE_SET_MSK 0x00000040
3171 /* The mask used to clear the ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE register field value. */
3172 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE_CLR_MSK 0xffffffbf
3173 /* The reset value of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE register field. */
3174 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE_RESET 0x0
3175 /* Extracts the ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE field value from a register. */
3176 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE_GET(value) (((value) & 0x00000040) >> 6)
3177 /* Produces a ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE register field value suitable for setting the register. */
3178 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE_SET(value) (((value) << 6) & 0x00000040)
3179 
3180 /*
3181  * Field : RUE
3182  *
3183  * Receive Buffer Unavailable Enable
3184  *
3185  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
3186  * Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the
3187  * Receive Buffer Unavailable Interrupt is disabled.
3188  *
3189  * Field Access Macros:
3190  *
3191  */
3192 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE register field. */
3193 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE_LSB 7
3194 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE register field. */
3195 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE_MSB 7
3196 /* The width in bits of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE register field. */
3197 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE_WIDTH 1
3198 /* The mask used to set the ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE register field value. */
3199 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE_SET_MSK 0x00000080
3200 /* The mask used to clear the ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE register field value. */
3201 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE_CLR_MSK 0xffffff7f
3202 /* The reset value of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE register field. */
3203 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE_RESET 0x0
3204 /* Extracts the ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE field value from a register. */
3205 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE_GET(value) (((value) & 0x00000080) >> 7)
3206 /* Produces a ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE register field value suitable for setting the register. */
3207 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE_SET(value) (((value) << 7) & 0x00000080)
3208 
3209 /*
3210  * Field : RSE
3211  *
3212  * Receive Stopped Enable
3213  *
3214  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
3215  * Receive Stopped Interrupt is enabled. When this bit is reset, the Receive
3216  * Stopped Interrupt is disabled.
3217  *
3218  * Field Access Macros:
3219  *
3220  */
3221 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE register field. */
3222 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE_LSB 8
3223 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE register field. */
3224 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE_MSB 8
3225 /* The width in bits of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE register field. */
3226 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE_WIDTH 1
3227 /* The mask used to set the ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE register field value. */
3228 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE_SET_MSK 0x00000100
3229 /* The mask used to clear the ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE register field value. */
3230 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE_CLR_MSK 0xfffffeff
3231 /* The reset value of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE register field. */
3232 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE_RESET 0x0
3233 /* Extracts the ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE field value from a register. */
3234 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE_GET(value) (((value) & 0x00000100) >> 8)
3235 /* Produces a ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE register field value suitable for setting the register. */
3236 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE_SET(value) (((value) << 8) & 0x00000100)
3237 
3238 /*
3239  * Field : RWE
3240  *
3241  * Receive Watchdog Timeout Enable
3242  *
3243  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
3244  * Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the
3245  * Receive Watchdog Timeout Interrupt is disabled.
3246  *
3247  * Field Access Macros:
3248  *
3249  */
3250 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE register field. */
3251 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE_LSB 9
3252 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE register field. */
3253 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE_MSB 9
3254 /* The width in bits of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE register field. */
3255 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE_WIDTH 1
3256 /* The mask used to set the ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE register field value. */
3257 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE_SET_MSK 0x00000200
3258 /* The mask used to clear the ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE register field value. */
3259 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE_CLR_MSK 0xfffffdff
3260 /* The reset value of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE register field. */
3261 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE_RESET 0x0
3262 /* Extracts the ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE field value from a register. */
3263 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE_GET(value) (((value) & 0x00000200) >> 9)
3264 /* Produces a ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE register field value suitable for setting the register. */
3265 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE_SET(value) (((value) << 9) & 0x00000200)
3266 
3267 /*
3268  * Field : ETE
3269  *
3270  * Early Transmit Interrupt Enable
3271  *
3272  * When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the
3273  * Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit
3274  * Interrupt is disabled.
3275  *
3276  * Field Access Macros:
3277  *
3278  */
3279 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE register field. */
3280 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE_LSB 10
3281 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE register field. */
3282 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE_MSB 10
3283 /* The width in bits of the ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE register field. */
3284 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE_WIDTH 1
3285 /* The mask used to set the ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE register field value. */
3286 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE_SET_MSK 0x00000400
3287 /* The mask used to clear the ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE register field value. */
3288 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE_CLR_MSK 0xfffffbff
3289 /* The reset value of the ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE register field. */
3290 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE_RESET 0x0
3291 /* Extracts the ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE field value from a register. */
3292 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE_GET(value) (((value) & 0x00000400) >> 10)
3293 /* Produces a ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE register field value suitable for setting the register. */
3294 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE_SET(value) (((value) << 10) & 0x00000400)
3295 
3296 /*
3297  * Field : Reserved_12_11
3298  *
3299  * Reserved
3300  *
3301  * Field Access Macros:
3302  *
3303  */
3304 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11 register field. */
3305 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11_LSB 11
3306 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11 register field. */
3307 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11_MSB 12
3308 /* The width in bits of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11 register field. */
3309 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11_WIDTH 2
3310 /* The mask used to set the ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11 register field value. */
3311 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11_SET_MSK 0x00001800
3312 /* The mask used to clear the ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11 register field value. */
3313 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11_CLR_MSK 0xffffe7ff
3314 /* The reset value of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11 register field. */
3315 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11_RESET 0x0
3316 /* Extracts the ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11 field value from a register. */
3317 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11_GET(value) (((value) & 0x00001800) >> 11)
3318 /* Produces a ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11 register field value suitable for setting the register. */
3319 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11_SET(value) (((value) << 11) & 0x00001800)
3320 
3321 /*
3322  * Field : FBE
3323  *
3324  * Fatal Bus Error Enable
3325  *
3326  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal
3327  * Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error
3328  * Enable Interrupt is disabled.
3329  *
3330  * Field Access Macros:
3331  *
3332  */
3333 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE register field. */
3334 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE_LSB 13
3335 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE register field. */
3336 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE_MSB 13
3337 /* The width in bits of the ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE register field. */
3338 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE_WIDTH 1
3339 /* The mask used to set the ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE register field value. */
3340 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE_SET_MSK 0x00002000
3341 /* The mask used to clear the ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE register field value. */
3342 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE_CLR_MSK 0xffffdfff
3343 /* The reset value of the ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE register field. */
3344 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE_RESET 0x0
3345 /* Extracts the ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE field value from a register. */
3346 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE_GET(value) (((value) & 0x00002000) >> 13)
3347 /* Produces a ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE register field value suitable for setting the register. */
3348 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE_SET(value) (((value) << 13) & 0x00002000)
3349 
3350 /*
3351  * Field : ERE
3352  *
3353  * Early Receive Interrupt Enable
3354  *
3355  * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early
3356  * Receive Interrupt is enabled. When this bit is reset, the Early Receive
3357  * Interrupt is disabled.
3358  *
3359  * Field Access Macros:
3360  *
3361  */
3362 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE register field. */
3363 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE_LSB 14
3364 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE register field. */
3365 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE_MSB 14
3366 /* The width in bits of the ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE register field. */
3367 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE_WIDTH 1
3368 /* The mask used to set the ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE register field value. */
3369 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE_SET_MSK 0x00004000
3370 /* The mask used to clear the ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE register field value. */
3371 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE_CLR_MSK 0xffffbfff
3372 /* The reset value of the ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE register field. */
3373 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE_RESET 0x0
3374 /* Extracts the ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE field value from a register. */
3375 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE_GET(value) (((value) & 0x00004000) >> 14)
3376 /* Produces a ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE register field value suitable for setting the register. */
3377 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE_SET(value) (((value) << 14) & 0x00004000)
3378 
3379 /*
3380  * Field : AIE
3381  *
3382  * Abnormal Interrupt Summary Enable
3383  *
3384  * When this bit is set, abnormal interrupt summary is enabled. When this bit is
3385  * reset, the abnormal interrupt summary is disabled. This bit enables the
3386  * following interrupts in Register 5 (Status Register):
3387  *
3388  * * Register 5[1]: Transmit Process Stopped
3389  *
3390  * * Register 5[3]: Transmit Jabber Timeout
3391  *
3392  * * Register 5[4]: Receive Overflow
3393  *
3394  * * Register 5[5]: Transmit Underflow
3395  *
3396  * * Register 5[7]: Receive Buffer Unavailable
3397  *
3398  * * Register 5[8]: Receive Process Stopped
3399  *
3400  * * Register 5[9]: Receive Watchdog Timeout
3401  *
3402  * * Register 5[10]: Early Transmit Interrupt
3403  *
3404  * * Register 5[13]: Fatal Bus Error
3405  *
3406  * Field Access Macros:
3407  *
3408  */
3409 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE register field. */
3410 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE_LSB 15
3411 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE register field. */
3412 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE_MSB 15
3413 /* The width in bits of the ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE register field. */
3414 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE_WIDTH 1
3415 /* The mask used to set the ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE register field value. */
3416 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE_SET_MSK 0x00008000
3417 /* The mask used to clear the ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE register field value. */
3418 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE_CLR_MSK 0xffff7fff
3419 /* The reset value of the ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE register field. */
3420 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE_RESET 0x0
3421 /* Extracts the ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE field value from a register. */
3422 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE_GET(value) (((value) & 0x00008000) >> 15)
3423 /* Produces a ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE register field value suitable for setting the register. */
3424 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE_SET(value) (((value) << 15) & 0x00008000)
3425 
3426 /*
3427  * Field : NIE
3428  *
3429  * Normal Interrupt Summary Enable
3430  *
3431  * When this bit is set, normal interrupt summary is enabled. When this bit is
3432  * reset, normal interrupt summary is disabled. This bit enables the following
3433  * interrupts in Register 5 (Status Register):
3434  *
3435  * * Register 5[0]: Transmit Interrupt
3436  *
3437  * * Register 5[2]: Transmit Buffer Unavailable
3438  *
3439  * * Register 5[6]: Receive Interrupt
3440  *
3441  * * Register 5[14]: Early Receive Interrupt
3442  *
3443  * Field Access Macros:
3444  *
3445  */
3446 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE register field. */
3447 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE_LSB 16
3448 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE register field. */
3449 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE_MSB 16
3450 /* The width in bits of the ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE register field. */
3451 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE_WIDTH 1
3452 /* The mask used to set the ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE register field value. */
3453 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE_SET_MSK 0x00010000
3454 /* The mask used to clear the ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE register field value. */
3455 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE_CLR_MSK 0xfffeffff
3456 /* The reset value of the ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE register field. */
3457 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE_RESET 0x0
3458 /* Extracts the ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE field value from a register. */
3459 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE_GET(value) (((value) & 0x00010000) >> 16)
3460 /* Produces a ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE register field value suitable for setting the register. */
3461 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE_SET(value) (((value) << 16) & 0x00010000)
3462 
3463 /*
3464  * Field : Reserved_31_17
3465  *
3466  * Reserved
3467  *
3468  * Field Access Macros:
3469  *
3470  */
3471 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17 register field. */
3472 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17_LSB 17
3473 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17 register field. */
3474 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17_MSB 31
3475 /* The width in bits of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17 register field. */
3476 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17_WIDTH 15
3477 /* The mask used to set the ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17 register field value. */
3478 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17_SET_MSK 0xfffe0000
3479 /* The mask used to clear the ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17 register field value. */
3480 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17_CLR_MSK 0x0001ffff
3481 /* The reset value of the ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17 register field. */
3482 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17_RESET 0x0
3483 /* Extracts the ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17 field value from a register. */
3484 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17_GET(value) (((value) & 0xfffe0000) >> 17)
3485 /* Produces a ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17 register field value suitable for setting the register. */
3486 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17_SET(value) (((value) << 17) & 0xfffe0000)
3487 
3488 #ifndef __ASSEMBLY__
3489 /*
3490  * WARNING: The C register and register group struct declarations are provided for
3491  * convenience and illustrative purposes. They should, however, be used with
3492  * caution as the C language standard provides no guarantees about the alignment or
3493  * atomicity of device memory accesses. The recommended practice for writing
3494  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3495  * alt_write_word() functions.
3496  *
3497  * The struct declaration for register ALT_EMAC_DMA_INTERRUPT_ENABLE.
3498  */
3499 struct ALT_EMAC_DMA_INTERRUPT_ENABLE_s
3500 {
3501  volatile uint32_t TIE : 1; /* ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE */
3502  volatile uint32_t TSE : 1; /* ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE */
3503  volatile uint32_t TUE : 1; /* ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE */
3504  volatile uint32_t TJE : 1; /* ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE */
3505  volatile uint32_t OVE : 1; /* ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE */
3506  volatile uint32_t UNE : 1; /* ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE */
3507  volatile uint32_t RIE : 1; /* ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE */
3508  volatile uint32_t RUE : 1; /* ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE */
3509  volatile uint32_t RSE : 1; /* ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE */
3510  volatile uint32_t RWE : 1; /* ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE */
3511  volatile uint32_t ETE : 1; /* ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE */
3512  const volatile uint32_t Reserved_12_11 : 2; /* ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11 */
3513  volatile uint32_t FBE : 1; /* ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE */
3514  volatile uint32_t ERE : 1; /* ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE */
3515  volatile uint32_t AIE : 1; /* ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE */
3516  volatile uint32_t NIE : 1; /* ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE */
3517  const volatile uint32_t Reserved_31_17 : 15; /* ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17 */
3518 };
3519 
3520 /* The typedef declaration for register ALT_EMAC_DMA_INTERRUPT_ENABLE. */
3521 typedef struct ALT_EMAC_DMA_INTERRUPT_ENABLE_s ALT_EMAC_DMA_INTERRUPT_ENABLE_t;
3522 #endif /* __ASSEMBLY__ */
3523 
3524 /* The reset value of the ALT_EMAC_DMA_INTERRUPT_ENABLE register. */
3525 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESET 0x00000000
3526 /* The byte offset of the ALT_EMAC_DMA_INTERRUPT_ENABLE register from the beginning of the component. */
3527 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_OFST 0x1c
3528 /* The address of the ALT_EMAC_DMA_INTERRUPT_ENABLE register. */
3529 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_INTERRUPT_ENABLE_OFST))
3530 
3531 /*
3532  * Register : Missed_Frame_And_Buffer_Overflow_Counter
3533  *
3534  * <b>Register 8 (Missed Frame and Buffer Overflow Counter Register) </b>
3535  *
3536  * The DMA maintains two counters to track the number of frames missed during
3537  * reception. This register reports the current value of the counter. The counter
3538  * is used for diagnostic purposes. Bits[15:0] indicate missed frames because of
3539  * the host buffer being unavailable. Bits[27:17] indicate missed frames because of
3540  * buffer overflow conditions (MTL and MAC) and runt frames (good frames of less
3541  * than 64 bytes) dropped by the MTL.
3542  *
3543  * Register Layout
3544  *
3545  * Bits | Access | Reset | Description
3546  * :--------|:-------|:------|:---------------------------------------------------------------------
3547  * [15:0] | R | 0x0 | ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT
3548  * [16] | R | 0x0 | ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF
3549  * [27:17] | R | 0x0 | ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT
3550  * [28] | R | 0x0 | ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF
3551  * [31:29] | R | 0x0 | ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29
3552  *
3553  */
3554 /*
3555  * Field : MISFRMCNT
3556  *
3557  * Missed Frame Counter
3558  *
3559  * This field indicates the number of frames missed by the controller because of
3560  * the Host Receive Buffer being unavailable. This counter is incremented each time
3561  * the DMA discards an incoming frame. The counter is cleared when this register is
3562  * read with mci_be_i[0] at 1'b1.
3563  *
3564  * Field Access Macros:
3565  *
3566  */
3567 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT register field. */
3568 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_LSB 0
3569 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT register field. */
3570 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_MSB 15
3571 /* The width in bits of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT register field. */
3572 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_WIDTH 16
3573 /* The mask used to set the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT register field value. */
3574 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_SET_MSK 0x0000ffff
3575 /* The mask used to clear the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT register field value. */
3576 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_CLR_MSK 0xffff0000
3577 /* The reset value of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT register field. */
3578 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_RESET 0x0
3579 /* Extracts the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT field value from a register. */
3580 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_GET(value) (((value) & 0x0000ffff) >> 0)
3581 /* Produces a ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT register field value suitable for setting the register. */
3582 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_SET(value) (((value) << 0) & 0x0000ffff)
3583 
3584 /*
3585  * Field : MISCNTOVF
3586  *
3587  * Overflow Bit for Missed Frame Counter
3588  *
3589  * This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, that is,
3590  * the DMA discards an incoming frame because of the Host Receive Buffer being
3591  * unavailable with the missed frame counter at maximum value. In such a scenario,
3592  * the Missed frame counter is reset to all-zeros and this bit indicates that the
3593  * rollover happened.
3594  *
3595  * Field Access Macros:
3596  *
3597  */
3598 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF register field. */
3599 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_LSB 16
3600 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF register field. */
3601 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_MSB 16
3602 /* The width in bits of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF register field. */
3603 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_WIDTH 1
3604 /* The mask used to set the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF register field value. */
3605 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_SET_MSK 0x00010000
3606 /* The mask used to clear the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF register field value. */
3607 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_CLR_MSK 0xfffeffff
3608 /* The reset value of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF register field. */
3609 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_RESET 0x0
3610 /* Extracts the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF field value from a register. */
3611 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_GET(value) (((value) & 0x00010000) >> 16)
3612 /* Produces a ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF register field value suitable for setting the register. */
3613 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_SET(value) (((value) << 16) & 0x00010000)
3614 
3615 /*
3616  * Field : OVFFRMCNT
3617  *
3618  * Overflow Frame Counter
3619  *
3620  * This field indicates the number of frames missed by the application. This
3621  * counter is incremented each time the MTL FIFO overflows. The counter is cleared
3622  * when this register is read with mci_be_i[2] at 1'b1.
3623  *
3624  * Field Access Macros:
3625  *
3626  */
3627 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT register field. */
3628 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_LSB 17
3629 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT register field. */
3630 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_MSB 27
3631 /* The width in bits of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT register field. */
3632 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_WIDTH 11
3633 /* The mask used to set the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT register field value. */
3634 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_SET_MSK 0x0ffe0000
3635 /* The mask used to clear the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT register field value. */
3636 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_CLR_MSK 0xf001ffff
3637 /* The reset value of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT register field. */
3638 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_RESET 0x0
3639 /* Extracts the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT field value from a register. */
3640 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_GET(value) (((value) & 0x0ffe0000) >> 17)
3641 /* Produces a ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT register field value suitable for setting the register. */
3642 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_SET(value) (((value) << 17) & 0x0ffe0000)
3643 
3644 /*
3645  * Field : OVFCNTOVF
3646  *
3647  * Overflow Bit for FIFO Overflow Counter
3648  *
3649  * This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows,
3650  * that is, the Rx FIFO overflows with the overflow frame counter at maximum value.
3651  * In such a scenario, the overflow frame counter is reset to all-zeros and this
3652  * bit indicates that the rollover happened.
3653  *
3654  * Field Access Macros:
3655  *
3656  */
3657 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF register field. */
3658 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_LSB 28
3659 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF register field. */
3660 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_MSB 28
3661 /* The width in bits of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF register field. */
3662 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_WIDTH 1
3663 /* The mask used to set the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF register field value. */
3664 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_SET_MSK 0x10000000
3665 /* The mask used to clear the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF register field value. */
3666 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_CLR_MSK 0xefffffff
3667 /* The reset value of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF register field. */
3668 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_RESET 0x0
3669 /* Extracts the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF field value from a register. */
3670 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_GET(value) (((value) & 0x10000000) >> 28)
3671 /* Produces a ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF register field value suitable for setting the register. */
3672 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_SET(value) (((value) << 28) & 0x10000000)
3673 
3674 /*
3675  * Field : Reserved_31_29
3676  *
3677  * Reserved
3678  *
3679  * Field Access Macros:
3680  *
3681  */
3682 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29 register field. */
3683 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29_LSB 29
3684 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29 register field. */
3685 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29_MSB 31
3686 /* The width in bits of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29 register field. */
3687 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29_WIDTH 3
3688 /* The mask used to set the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29 register field value. */
3689 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29_SET_MSK 0xe0000000
3690 /* The mask used to clear the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29 register field value. */
3691 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29_CLR_MSK 0x1fffffff
3692 /* The reset value of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29 register field. */
3693 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29_RESET 0x0
3694 /* Extracts the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29 field value from a register. */
3695 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29_GET(value) (((value) & 0xe0000000) >> 29)
3696 /* Produces a ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29 register field value suitable for setting the register. */
3697 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29_SET(value) (((value) << 29) & 0xe0000000)
3698 
3699 #ifndef __ASSEMBLY__
3700 /*
3701  * WARNING: The C register and register group struct declarations are provided for
3702  * convenience and illustrative purposes. They should, however, be used with
3703  * caution as the C language standard provides no guarantees about the alignment or
3704  * atomicity of device memory accesses. The recommended practice for writing
3705  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3706  * alt_write_word() functions.
3707  *
3708  * The struct declaration for register ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER.
3709  */
3710 struct ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_s
3711 {
3712  const volatile uint32_t MISFRMCNT : 16; /* ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT */
3713  const volatile uint32_t MISCNTOVF : 1; /* ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF */
3714  const volatile uint32_t OVFFRMCNT : 11; /* ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT */
3715  const volatile uint32_t OVFCNTOVF : 1; /* ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF */
3716  const volatile uint32_t Reserved_31_29 : 3; /* ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29 */
3717 };
3718 
3719 /* The typedef declaration for register ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER. */
3720 typedef struct ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_s ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_t;
3721 #endif /* __ASSEMBLY__ */
3722 
3723 /* The reset value of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER register. */
3724 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESET 0x00000000
3725 /* The byte offset of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER register from the beginning of the component. */
3726 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OFST 0x20
3727 /* The address of the ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER register. */
3728 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OFST))
3729 
3730 /*
3731  * Register : Receive_Interrupt_Watchdog_Timer
3732  *
3733  * <b> Register 9 (Receive Interrupt Watchdog Timer Register) </b>
3734  *
3735  * This register, when written with non-zero value, enables the watchdog timer for
3736  * the Receive Interrupt (Bit 6) of Register 5 (Status Register)
3737  *
3738  * Register Layout
3739  *
3740  * Bits | Access | Reset | Description
3741  * :-------|:-------|:------|:------------------------------------------------------------
3742  * [7:0] | RW | 0x0 | ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT
3743  * [31:8] | R | 0x0 | ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8
3744  *
3745  */
3746 /*
3747  * Field : RIWT
3748  *
3749  * RI Watchdog Timer Count
3750  *
3751  * This bit indicates the number of system clock cycles multiplied by 256 for which
3752  * the watchdog timer is set. The watchdog timer gets triggered with the programmed
3753  * value after the Rx DMA completes the transfer of a frame for which the RI status
3754  * bit is not set because of the setting in the corresponding descriptor RDES1[31].
3755  * When the watchdog timer runs out, the RI bit is set and the timer is stopped.
3756  * The watchdog timer is reset when the RI bit is set high because of automatic
3757  * setting of RI as per RDES1[31] of any received frame.
3758  *
3759  * Field Access Macros:
3760  *
3761  */
3762 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT register field. */
3763 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_LSB 0
3764 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT register field. */
3765 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_MSB 7
3766 /* The width in bits of the ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT register field. */
3767 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_WIDTH 8
3768 /* The mask used to set the ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT register field value. */
3769 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_SET_MSK 0x000000ff
3770 /* The mask used to clear the ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT register field value. */
3771 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_CLR_MSK 0xffffff00
3772 /* The reset value of the ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT register field. */
3773 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_RESET 0x0
3774 /* Extracts the ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT field value from a register. */
3775 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_GET(value) (((value) & 0x000000ff) >> 0)
3776 /* Produces a ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT register field value suitable for setting the register. */
3777 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_SET(value) (((value) << 0) & 0x000000ff)
3778 
3779 /*
3780  * Field : Reserved_31_8
3781  *
3782  * Reserved
3783  *
3784  * Field Access Macros:
3785  *
3786  */
3787 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8 register field. */
3788 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8_LSB 8
3789 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8 register field. */
3790 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8_MSB 31
3791 /* The width in bits of the ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8 register field. */
3792 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8_WIDTH 24
3793 /* The mask used to set the ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8 register field value. */
3794 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8_SET_MSK 0xffffff00
3795 /* The mask used to clear the ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8 register field value. */
3796 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8_CLR_MSK 0x000000ff
3797 /* The reset value of the ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8 register field. */
3798 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8_RESET 0x0
3799 /* Extracts the ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8 field value from a register. */
3800 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8_GET(value) (((value) & 0xffffff00) >> 8)
3801 /* Produces a ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8 register field value suitable for setting the register. */
3802 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8_SET(value) (((value) << 8) & 0xffffff00)
3803 
3804 #ifndef __ASSEMBLY__
3805 /*
3806  * WARNING: The C register and register group struct declarations are provided for
3807  * convenience and illustrative purposes. They should, however, be used with
3808  * caution as the C language standard provides no guarantees about the alignment or
3809  * atomicity of device memory accesses. The recommended practice for writing
3810  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3811  * alt_write_word() functions.
3812  *
3813  * The struct declaration for register ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER.
3814  */
3815 struct ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_s
3816 {
3817  volatile uint32_t RIWT : 8; /* ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT */
3818  const volatile uint32_t Reserved_31_8 : 24; /* ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8 */
3819 };
3820 
3821 /* The typedef declaration for register ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER. */
3822 typedef struct ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_s ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_t;
3823 #endif /* __ASSEMBLY__ */
3824 
3825 /* The reset value of the ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER register. */
3826 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESET 0x00000000
3827 /* The byte offset of the ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER register from the beginning of the component. */
3828 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_OFST 0x24
3829 /* The address of the ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER register. */
3830 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_OFST))
3831 
3832 /*
3833  * Register : AXI_Bus_Mode
3834  *
3835  * <b> Register 10 (AXI Bus Mode Register) </b>
3836  *
3837  * The AXI Bus Mode Register controls the behavior of the AXI master. It is mainly
3838  * used to control the burst splitting and the number of outstanding requests. This
3839  * register is present and valid only in the GMAC-AXI configuration. In addition,
3840  * this register is valid only in the Channel 0 DMA when multiple channels are
3841  * present in the AV mode.
3842  *
3843  * Register Layout
3844  *
3845  * Bits | Access | Reset | Description
3846  * :--------|:-------|:------|:-----------------------------------------
3847  * [0] | R | 0x1 | ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF
3848  * [1] | RW | 0x0 | ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4
3849  * [2] | RW | 0x0 | ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8
3850  * [3] | RW | 0x0 | ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16
3851  * [4] | R | 0x0 | ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32
3852  * [5] | R | 0x0 | ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64
3853  * [6] | R | 0x0 | ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128
3854  * [7] | R | 0x0 | ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256
3855  * [11:8] | R | 0x0 | ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8
3856  * [12] | R | 0x0 | ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL
3857  * [13] | RW | 0x0 | ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE
3858  * [15:14] | R | 0x0 | ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14
3859  * [17:16] | RW | 0x1 | ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT
3860  * [18] | RW | 0x0 | ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4
3861  * [19] | RW | 0x0 | ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8
3862  * [21:20] | RW | 0x1 | ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT
3863  * [22] | RW | 0x0 | ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4
3864  * [23] | RW | 0x0 | ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8
3865  * [29:24] | R | 0x0 | ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24
3866  * [30] | RW | 0x0 | ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM
3867  * [31] | RW | 0x0 | ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI
3868  *
3869  */
3870 /*
3871  * Field : UNDEF
3872  *
3873  * AXI Undefined Burst Length
3874  *
3875  * This bit is read-only bit and indicates the complement (invert) value of Bit 16
3876  * (FB) in Register 0 (Bus Mode Register[16]).
3877  *
3878  * * When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length
3879  * equal to or below the maximum allowed burst length programmed in Bits[7:1].
3880  *
3881  * * When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst
3882  * lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or
3883  * BLEN4, or a burst length of 1.
3884  *
3885  * Field Access Macros:
3886  *
3887  */
3888 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF register field. */
3889 #define ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF_LSB 0
3890 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF register field. */
3891 #define ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF_MSB 0
3892 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF register field. */
3893 #define ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF_WIDTH 1
3894 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF register field value. */
3895 #define ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF_SET_MSK 0x00000001
3896 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF register field value. */
3897 #define ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF_CLR_MSK 0xfffffffe
3898 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF register field. */
3899 #define ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF_RESET 0x1
3900 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF field value from a register. */
3901 #define ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF_GET(value) (((value) & 0x00000001) >> 0)
3902 /* Produces a ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF register field value suitable for setting the register. */
3903 #define ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF_SET(value) (((value) << 0) & 0x00000001)
3904 
3905 /*
3906  * Field : BLEN4
3907  *
3908  * AXI Burst Length 4
3909  *
3910  * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4
3911  * on the AXI Master interface.
3912  *
3913  * Setting this bit has no effect when UNDEF is set to 1.
3914  *
3915  * Field Access Macros:
3916  *
3917  */
3918 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4 register field. */
3919 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4_LSB 1
3920 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4 register field. */
3921 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4_MSB 1
3922 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4 register field. */
3923 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4_WIDTH 1
3924 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4 register field value. */
3925 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4_SET_MSK 0x00000002
3926 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4 register field value. */
3927 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4_CLR_MSK 0xfffffffd
3928 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4 register field. */
3929 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4_RESET 0x0
3930 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4 field value from a register. */
3931 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4_GET(value) (((value) & 0x00000002) >> 1)
3932 /* Produces a ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4 register field value suitable for setting the register. */
3933 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4_SET(value) (((value) << 1) & 0x00000002)
3934 
3935 /*
3936  * Field : BLEN8
3937  *
3938  * AXI Burst Length 8
3939  *
3940  * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8
3941  * on the AXI Master interface.
3942  *
3943  * Setting this bit has no effect when UNDEF is set to 1.
3944  *
3945  * Field Access Macros:
3946  *
3947  */
3948 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8 register field. */
3949 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8_LSB 2
3950 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8 register field. */
3951 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8_MSB 2
3952 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8 register field. */
3953 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8_WIDTH 1
3954 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8 register field value. */
3955 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8_SET_MSK 0x00000004
3956 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8 register field value. */
3957 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8_CLR_MSK 0xfffffffb
3958 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8 register field. */
3959 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8_RESET 0x0
3960 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8 field value from a register. */
3961 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8_GET(value) (((value) & 0x00000004) >> 2)
3962 /* Produces a ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8 register field value suitable for setting the register. */
3963 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8_SET(value) (((value) << 2) & 0x00000004)
3964 
3965 /*
3966  * Field : BLEN16
3967  *
3968  * AXI Burst Length 16
3969  *
3970  * When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to
3971  * select a burst length of 16 on the AXI Master interface.
3972  *
3973  * Field Access Macros:
3974  *
3975  */
3976 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16 register field. */
3977 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16_LSB 3
3978 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16 register field. */
3979 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16_MSB 3
3980 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16 register field. */
3981 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16_WIDTH 1
3982 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16 register field value. */
3983 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16_SET_MSK 0x00000008
3984 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16 register field value. */
3985 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16_CLR_MSK 0xfffffff7
3986 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16 register field. */
3987 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16_RESET 0x0
3988 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16 field value from a register. */
3989 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16_GET(value) (((value) & 0x00000008) >> 3)
3990 /* Produces a ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16 register field value suitable for setting the register. */
3991 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16_SET(value) (((value) << 3) & 0x00000008)
3992 
3993 /*
3994  * Field : BLEN32
3995  *
3996  * AXI Burst Length 32
3997  *
3998  * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of
3999  * 32 on the AXI Master interface.
4000  *
4001  * This bit is present only when the configuration parameter AXI_BL is set to 32 or
4002  * more. Otherwise, this bit is reserved and is read-only (RO).
4003  *
4004  * Field Access Macros:
4005  *
4006  */
4007 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32 register field. */
4008 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32_LSB 4
4009 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32 register field. */
4010 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32_MSB 4
4011 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32 register field. */
4012 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32_WIDTH 1
4013 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32 register field value. */
4014 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32_SET_MSK 0x00000010
4015 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32 register field value. */
4016 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32_CLR_MSK 0xffffffef
4017 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32 register field. */
4018 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32_RESET 0x0
4019 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32 field value from a register. */
4020 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32_GET(value) (((value) & 0x00000010) >> 4)
4021 /* Produces a ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32 register field value suitable for setting the register. */
4022 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32_SET(value) (((value) << 4) & 0x00000010)
4023 
4024 /*
4025  * Field : BLEN64
4026  *
4027  * AXI Burst Length 64
4028  *
4029  * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of
4030  * 64 on the AXI Master interface.
4031  *
4032  * This bit is present only when the configuration parameter AXI_BL is set to 64 or
4033  * more. Otherwise, this bit is reserved and is read-only (RO).
4034  *
4035  * Field Access Macros:
4036  *
4037  */
4038 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64 register field. */
4039 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64_LSB 5
4040 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64 register field. */
4041 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64_MSB 5
4042 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64 register field. */
4043 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64_WIDTH 1
4044 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64 register field value. */
4045 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64_SET_MSK 0x00000020
4046 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64 register field value. */
4047 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64_CLR_MSK 0xffffffdf
4048 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64 register field. */
4049 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64_RESET 0x0
4050 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64 field value from a register. */
4051 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64_GET(value) (((value) & 0x00000020) >> 5)
4052 /* Produces a ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64 register field value suitable for setting the register. */
4053 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64_SET(value) (((value) << 5) & 0x00000020)
4054 
4055 /*
4056  * Field : BLEN128
4057  *
4058  * AXI Burst Length 128
4059  *
4060  * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of
4061  * 128 on the AXI Master interface.
4062  *
4063  * This bit is present only when the configuration parameter AXI_BL is set to 128
4064  * or more. Otherwise, this bit is reserved and is read-only (RO).
4065  *
4066  * Field Access Macros:
4067  *
4068  */
4069 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128 register field. */
4070 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128_LSB 6
4071 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128 register field. */
4072 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128_MSB 6
4073 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128 register field. */
4074 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128_WIDTH 1
4075 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128 register field value. */
4076 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128_SET_MSK 0x00000040
4077 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128 register field value. */
4078 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128_CLR_MSK 0xffffffbf
4079 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128 register field. */
4080 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128_RESET 0x0
4081 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128 field value from a register. */
4082 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128_GET(value) (((value) & 0x00000040) >> 6)
4083 /* Produces a ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128 register field value suitable for setting the register. */
4084 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128_SET(value) (((value) << 6) & 0x00000040)
4085 
4086 /*
4087  * Field : BLEN256
4088  *
4089  * AXI Burst Length 256
4090  *
4091  * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of
4092  * 256 on the AXI Master Interface.
4093  *
4094  * This bit is present only when the configuration parameter AXI_BL is set to 256.
4095  * Otherwise, this bit is reserved and is read-only (RO).
4096  *
4097  * Field Access Macros:
4098  *
4099  */
4100 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256 register field. */
4101 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256_LSB 7
4102 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256 register field. */
4103 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256_MSB 7
4104 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256 register field. */
4105 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256_WIDTH 1
4106 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256 register field value. */
4107 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256_SET_MSK 0x00000080
4108 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256 register field value. */
4109 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256_CLR_MSK 0xffffff7f
4110 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256 register field. */
4111 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256_RESET 0x0
4112 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256 field value from a register. */
4113 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256_GET(value) (((value) & 0x00000080) >> 7)
4114 /* Produces a ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256 register field value suitable for setting the register. */
4115 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256_SET(value) (((value) << 7) & 0x00000080)
4116 
4117 /*
4118  * Field : Reserved_11_8
4119  *
4120  * Reserved
4121  *
4122  * Field Access Macros:
4123  *
4124  */
4125 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8 register field. */
4126 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8_LSB 8
4127 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8 register field. */
4128 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8_MSB 11
4129 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8 register field. */
4130 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8_WIDTH 4
4131 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8 register field value. */
4132 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8_SET_MSK 0x00000f00
4133 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8 register field value. */
4134 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8_CLR_MSK 0xfffff0ff
4135 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8 register field. */
4136 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8_RESET 0x0
4137 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8 field value from a register. */
4138 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8_GET(value) (((value) & 0x00000f00) >> 8)
4139 /* Produces a ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8 register field value suitable for setting the register. */
4140 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8_SET(value) (((value) << 8) & 0x00000f00)
4141 
4142 /*
4143  * Field : AXI_AAL
4144  *
4145  * Address-Aligned Beats
4146  *
4147  * This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode
4148  * Register).
4149  *
4150  * When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers
4151  * on both read and write channels.
4152  *
4153  * Field Access Macros:
4154  *
4155  */
4156 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL register field. */
4157 #define ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL_LSB 12
4158 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL register field. */
4159 #define ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL_MSB 12
4160 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL register field. */
4161 #define ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL_WIDTH 1
4162 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL register field value. */
4163 #define ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL_SET_MSK 0x00001000
4164 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL register field value. */
4165 #define ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL_CLR_MSK 0xffffefff
4166 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL register field. */
4167 #define ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL_RESET 0x0
4168 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL field value from a register. */
4169 #define ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL_GET(value) (((value) & 0x00001000) >> 12)
4170 /* Produces a ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL register field value suitable for setting the register. */
4171 #define ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL_SET(value) (((value) << 12) & 0x00001000)
4172 
4173 /*
4174  * Field : ONEKBBE
4175  *
4176  * 1 KB Boundary Crossing Enable for the GMAC-AXI Master
4177  *
4178  * When set, the GMAC-AXI Master performs burst transfers that do not cross 1 KB
4179  * boundary. When reset, the GMAC-AXI Master performs burst transfers that do not
4180  * cross 4 KB boundary.
4181  *
4182  * Field Access Macros:
4183  *
4184  */
4185 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE register field. */
4186 #define ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE_LSB 13
4187 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE register field. */
4188 #define ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE_MSB 13
4189 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE register field. */
4190 #define ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE_WIDTH 1
4191 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE register field value. */
4192 #define ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE_SET_MSK 0x00002000
4193 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE register field value. */
4194 #define ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE_CLR_MSK 0xffffdfff
4195 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE register field. */
4196 #define ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE_RESET 0x0
4197 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE field value from a register. */
4198 #define ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE_GET(value) (((value) & 0x00002000) >> 13)
4199 /* Produces a ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE register field value suitable for setting the register. */
4200 #define ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE_SET(value) (((value) << 13) & 0x00002000)
4201 
4202 /*
4203  * Field : Reserved_15_14
4204  *
4205  * Reserved
4206  *
4207  * Field Access Macros:
4208  *
4209  */
4210 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14 register field. */
4211 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14_LSB 14
4212 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14 register field. */
4213 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14_MSB 15
4214 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14 register field. */
4215 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14_WIDTH 2
4216 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14 register field value. */
4217 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14_SET_MSK 0x0000c000
4218 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14 register field value. */
4219 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14_CLR_MSK 0xffff3fff
4220 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14 register field. */
4221 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14_RESET 0x0
4222 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14 field value from a register. */
4223 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14_GET(value) (((value) & 0x0000c000) >> 14)
4224 /* Produces a ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14 register field value suitable for setting the register. */
4225 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14_SET(value) (((value) << 14) & 0x0000c000)
4226 
4227 /*
4228  * Field : RD_OSR_LMT
4229  *
4230  * AXI Maximum Read OutStanding Request Limit
4231  *
4232  * This value limits the maximum outstanding request on the AXI read interface.
4233  *
4234  * Maximum outstanding requests = RD_OSR_LMT+1
4235  *
4236  * Note:
4237  *
4238  * The Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4.
4239  *
4240  * The Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16.
4241  *
4242  * Field Access Macros:
4243  *
4244  */
4245 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT register field. */
4246 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_LSB 16
4247 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT register field. */
4248 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_MSB 17
4249 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT register field. */
4250 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_WIDTH 2
4251 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT register field value. */
4252 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_SET_MSK 0x00030000
4253 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT register field value. */
4254 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_CLR_MSK 0xfffcffff
4255 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT register field. */
4256 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_RESET 0x1
4257 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT field value from a register. */
4258 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GET(value) (((value) & 0x00030000) >> 16)
4259 /* Produces a ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT register field value suitable for setting the register. */
4260 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_SET(value) (((value) << 16) & 0x00030000)
4261 
4262 /*
4263  * Field : RD_OSR_LMT_GT4
4264  *
4265  * RD_OSR_LMT: AXI Maximum Read OutStanding Request Limit
4266  *
4267  * Field Access Macros:
4268  *
4269  */
4270 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4 register field. */
4271 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4_LSB 18
4272 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4 register field. */
4273 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4_MSB 18
4274 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4 register field. */
4275 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4_WIDTH 1
4276 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4 register field value. */
4277 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4_SET_MSK 0x00040000
4278 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4 register field value. */
4279 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4_CLR_MSK 0xfffbffff
4280 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4 register field. */
4281 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4_RESET 0x0
4282 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4 field value from a register. */
4283 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4_GET(value) (((value) & 0x00040000) >> 18)
4284 /* Produces a ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4 register field value suitable for setting the register. */
4285 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4_SET(value) (((value) << 18) & 0x00040000)
4286 
4287 /*
4288  * Field : RD_OSR_LMT_GT8
4289  *
4290  * RD_OSR_LMT: AXI Maximum Read OutStanding Request Limit
4291  *
4292  * Field Access Macros:
4293  *
4294  */
4295 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8 register field. */
4296 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8_LSB 19
4297 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8 register field. */
4298 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8_MSB 19
4299 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8 register field. */
4300 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8_WIDTH 1
4301 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8 register field value. */
4302 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8_SET_MSK 0x00080000
4303 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8 register field value. */
4304 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8_CLR_MSK 0xfff7ffff
4305 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8 register field. */
4306 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8_RESET 0x0
4307 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8 field value from a register. */
4308 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8_GET(value) (((value) & 0x00080000) >> 19)
4309 /* Produces a ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8 register field value suitable for setting the register. */
4310 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8_SET(value) (((value) << 19) & 0x00080000)
4311 
4312 /*
4313  * Field : WR_OSR_LMT
4314  *
4315  * AXI Maximum Write OutStanding Request Limit
4316  *
4317  * Field Access Macros:
4318  *
4319  */
4320 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT register field. */
4321 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_LSB 20
4322 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT register field. */
4323 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_MSB 21
4324 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT register field. */
4325 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_WIDTH 2
4326 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT register field value. */
4327 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_SET_MSK 0x00300000
4328 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT register field value. */
4329 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_CLR_MSK 0xffcfffff
4330 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT register field. */
4331 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_RESET 0x1
4332 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT field value from a register. */
4333 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GET(value) (((value) & 0x00300000) >> 20)
4334 /* Produces a ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT register field value suitable for setting the register. */
4335 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_SET(value) (((value) << 20) & 0x00300000)
4336 
4337 /*
4338  * Field : WR_OSR_LMT_GT4
4339  *
4340  * WR_OSR_LMT: AXI Maximum Write Out Standing Request Limit
4341  *
4342  * Field Access Macros:
4343  *
4344  */
4345 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4 register field. */
4346 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4_LSB 22
4347 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4 register field. */
4348 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4_MSB 22
4349 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4 register field. */
4350 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4_WIDTH 1
4351 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4 register field value. */
4352 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4_SET_MSK 0x00400000
4353 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4 register field value. */
4354 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4_CLR_MSK 0xffbfffff
4355 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4 register field. */
4356 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4_RESET 0x0
4357 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4 field value from a register. */
4358 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4_GET(value) (((value) & 0x00400000) >> 22)
4359 /* Produces a ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4 register field value suitable for setting the register. */
4360 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4_SET(value) (((value) << 22) & 0x00400000)
4361 
4362 /*
4363  * Field : WR_OSR_LMT_GT8
4364  *
4365  * WR_OSR_LMT: AXI Maximum Write OutStanding Request Limit
4366  *
4367  * Field Access Macros:
4368  *
4369  */
4370 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8 register field. */
4371 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8_LSB 23
4372 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8 register field. */
4373 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8_MSB 23
4374 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8 register field. */
4375 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8_WIDTH 1
4376 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8 register field value. */
4377 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8_SET_MSK 0x00800000
4378 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8 register field value. */
4379 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8_CLR_MSK 0xff7fffff
4380 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8 register field. */
4381 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8_RESET 0x0
4382 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8 field value from a register. */
4383 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8_GET(value) (((value) & 0x00800000) >> 23)
4384 /* Produces a ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8 register field value suitable for setting the register. */
4385 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8_SET(value) (((value) << 23) & 0x00800000)
4386 
4387 /*
4388  * Field : Reserved_29_24
4389  *
4390  * Reserved
4391  *
4392  * Field Access Macros:
4393  *
4394  */
4395 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24 register field. */
4396 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24_LSB 24
4397 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24 register field. */
4398 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24_MSB 29
4399 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24 register field. */
4400 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24_WIDTH 6
4401 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24 register field value. */
4402 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24_SET_MSK 0x3f000000
4403 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24 register field value. */
4404 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24_CLR_MSK 0xc0ffffff
4405 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24 register field. */
4406 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24_RESET 0x0
4407 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24 field value from a register. */
4408 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24_GET(value) (((value) & 0x3f000000) >> 24)
4409 /* Produces a ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24 register field value suitable for setting the register. */
4410 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24_SET(value) (((value) << 24) & 0x3f000000)
4411 
4412 /*
4413  * Field : LPI_XIT_FRM
4414  *
4415  * Unlock on Magic Packet or Remote Wake Up
4416  *
4417  * When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only
4418  * when the Magic Packet or Remote Wake Up Packet is received.
4419  *
4420  * When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any
4421  * frame is received.
4422  *
4423  * Field Access Macros:
4424  *
4425  */
4426 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM register field. */
4427 #define ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM_LSB 30
4428 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM register field. */
4429 #define ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM_MSB 30
4430 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM register field. */
4431 #define ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM_WIDTH 1
4432 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM register field value. */
4433 #define ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM_SET_MSK 0x40000000
4434 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM register field value. */
4435 #define ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM_CLR_MSK 0xbfffffff
4436 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM register field. */
4437 #define ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM_RESET 0x0
4438 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM field value from a register. */
4439 #define ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM_GET(value) (((value) & 0x40000000) >> 30)
4440 /* Produces a ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM register field value suitable for setting the register. */
4441 #define ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM_SET(value) (((value) << 30) & 0x40000000)
4442 
4443 /*
4444  * Field : EN_LPI
4445  *
4446  * Enable Low Power Interface (LPI)
4447  *
4448  * When set to 1, this bit enables the LPI mode supported by the GMAC-AXI
4449  * configuration and accepts the LPI request from the AXI System Clock controller.
4450  *
4451  * When set to 0, this bit disables the LPI mode and always denies the LPI request
4452  * from the AXI System Clock controller.
4453  *
4454  * Field Access Macros:
4455  *
4456  */
4457 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI register field. */
4458 #define ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI_LSB 31
4459 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI register field. */
4460 #define ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI_MSB 31
4461 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI register field. */
4462 #define ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI_WIDTH 1
4463 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI register field value. */
4464 #define ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI_SET_MSK 0x80000000
4465 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI register field value. */
4466 #define ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI_CLR_MSK 0x7fffffff
4467 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI register field. */
4468 #define ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI_RESET 0x0
4469 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI field value from a register. */
4470 #define ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI_GET(value) (((value) & 0x80000000) >> 31)
4471 /* Produces a ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI register field value suitable for setting the register. */
4472 #define ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI_SET(value) (((value) << 31) & 0x80000000)
4473 
4474 #ifndef __ASSEMBLY__
4475 /*
4476  * WARNING: The C register and register group struct declarations are provided for
4477  * convenience and illustrative purposes. They should, however, be used with
4478  * caution as the C language standard provides no guarantees about the alignment or
4479  * atomicity of device memory accesses. The recommended practice for writing
4480  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4481  * alt_write_word() functions.
4482  *
4483  * The struct declaration for register ALT_EMAC_DMA_AXI_BUS_MODE.
4484  */
4485 struct ALT_EMAC_DMA_AXI_BUS_MODE_s
4486 {
4487  const volatile uint32_t UNDEF : 1; /* ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF */
4488  volatile uint32_t BLEN4 : 1; /* ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4 */
4489  volatile uint32_t BLEN8 : 1; /* ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8 */
4490  volatile uint32_t BLEN16 : 1; /* ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16 */
4491  const volatile uint32_t BLEN32 : 1; /* ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32 */
4492  const volatile uint32_t BLEN64 : 1; /* ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64 */
4493  const volatile uint32_t BLEN128 : 1; /* ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128 */
4494  const volatile uint32_t BLEN256 : 1; /* ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256 */
4495  const volatile uint32_t Reserved_11_8 : 4; /* ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8 */
4496  const volatile uint32_t AXI_AAL : 1; /* ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL */
4497  volatile uint32_t ONEKBBE : 1; /* ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE */
4498  const volatile uint32_t Reserved_15_14 : 2; /* ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14 */
4499  volatile uint32_t RD_OSR_LMT : 2; /* ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT */
4500  volatile uint32_t RD_OSR_LMT_GT4 : 1; /* ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4 */
4501  volatile uint32_t RD_OSR_LMT_GT8 : 1; /* ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8 */
4502  volatile uint32_t WR_OSR_LMT : 2; /* ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT */
4503  volatile uint32_t WR_OSR_LMT_GT4 : 1; /* ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4 */
4504  volatile uint32_t WR_OSR_LMT_GT8 : 1; /* ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8 */
4505  const volatile uint32_t Reserved_29_24 : 6; /* ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24 */
4506  volatile uint32_t LPI_XIT_FRM : 1; /* ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM */
4507  volatile uint32_t EN_LPI : 1; /* ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI */
4508 };
4509 
4510 /* The typedef declaration for register ALT_EMAC_DMA_AXI_BUS_MODE. */
4511 typedef struct ALT_EMAC_DMA_AXI_BUS_MODE_s ALT_EMAC_DMA_AXI_BUS_MODE_t;
4512 #endif /* __ASSEMBLY__ */
4513 
4514 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MODE register. */
4515 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESET 0x00110001
4516 /* The byte offset of the ALT_EMAC_DMA_AXI_BUS_MODE register from the beginning of the component. */
4517 #define ALT_EMAC_DMA_AXI_BUS_MODE_OFST 0x28
4518 /* The address of the ALT_EMAC_DMA_AXI_BUS_MODE register. */
4519 #define ALT_EMAC_DMA_AXI_BUS_MODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_AXI_BUS_MODE_OFST))
4520 
4521 /*
4522  * Register : AHB_or_AXI_Status
4523  *
4524  * <b> Register 11 (AHB or AXI Status Register) </b>
4525  *
4526  * This register provides the active status of the AHB master interface or AXI
4527  * interface's read and write channels. This register is present and valid only in
4528  * the GMAC-AHB and GMAC-AXI configurations. This register is useful for debugging
4529  * purposes. In addition, this register is valid only in the Channel 0 DMA when
4530  * multiple channels are present in the AV mode.
4531  *
4532  * Register Layout
4533  *
4534  * Bits | Access | Reset | Description
4535  * :-------|:-------|:------|:---------------------------------------------
4536  * [0] | R | 0x0 | ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS
4537  * [1] | R | 0x0 | ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS
4538  * [31:2] | R | 0x0 | ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2
4539  *
4540  */
4541 /*
4542  * Field : AXWHSTS
4543  *
4544  * AXI Master Write Channel or AHB Master Status
4545  *
4546  * When high, it indicates that AXI Master's write channel is active and
4547  * transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration,
4548  * it indicates that the AHB master interface FSMs are in the non-idle state.
4549  *
4550  * Field Access Macros:
4551  *
4552  */
4553 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS register field. */
4554 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS_LSB 0
4555 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS register field. */
4556 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS_MSB 0
4557 /* The width in bits of the ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS register field. */
4558 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS_WIDTH 1
4559 /* The mask used to set the ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS register field value. */
4560 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS_SET_MSK 0x00000001
4561 /* The mask used to clear the ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS register field value. */
4562 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS_CLR_MSK 0xfffffffe
4563 /* The reset value of the ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS register field. */
4564 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS_RESET 0x0
4565 /* Extracts the ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS field value from a register. */
4566 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS_GET(value) (((value) & 0x00000001) >> 0)
4567 /* Produces a ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS register field value suitable for setting the register. */
4568 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS_SET(value) (((value) << 0) & 0x00000001)
4569 
4570 /*
4571  * Field : AXIRDSTS
4572  *
4573  * AXI Master Read Channel Status
4574  *
4575  * When high, it indicates that AXI Master's read channel is active and
4576  * transferring data.
4577  *
4578  * Field Access Macros:
4579  *
4580  */
4581 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS register field. */
4582 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS_LSB 1
4583 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS register field. */
4584 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS_MSB 1
4585 /* The width in bits of the ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS register field. */
4586 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS_WIDTH 1
4587 /* The mask used to set the ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS register field value. */
4588 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS_SET_MSK 0x00000002
4589 /* The mask used to clear the ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS register field value. */
4590 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS_CLR_MSK 0xfffffffd
4591 /* The reset value of the ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS register field. */
4592 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS_RESET 0x0
4593 /* Extracts the ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS field value from a register. */
4594 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS_GET(value) (((value) & 0x00000002) >> 1)
4595 /* Produces a ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS register field value suitable for setting the register. */
4596 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS_SET(value) (((value) << 1) & 0x00000002)
4597 
4598 /*
4599  * Field : Reserved_31_2
4600  *
4601  * Reserved
4602  *
4603  * Field Access Macros:
4604  *
4605  */
4606 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2 register field. */
4607 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2_LSB 2
4608 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2 register field. */
4609 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2_MSB 31
4610 /* The width in bits of the ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2 register field. */
4611 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2_WIDTH 30
4612 /* The mask used to set the ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2 register field value. */
4613 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2_SET_MSK 0xfffffffc
4614 /* The mask used to clear the ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2 register field value. */
4615 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2_CLR_MSK 0x00000003
4616 /* The reset value of the ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2 register field. */
4617 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2_RESET 0x0
4618 /* Extracts the ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2 field value from a register. */
4619 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2_GET(value) (((value) & 0xfffffffc) >> 2)
4620 /* Produces a ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2 register field value suitable for setting the register. */
4621 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2_SET(value) (((value) << 2) & 0xfffffffc)
4622 
4623 #ifndef __ASSEMBLY__
4624 /*
4625  * WARNING: The C register and register group struct declarations are provided for
4626  * convenience and illustrative purposes. They should, however, be used with
4627  * caution as the C language standard provides no guarantees about the alignment or
4628  * atomicity of device memory accesses. The recommended practice for writing
4629  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4630  * alt_write_word() functions.
4631  *
4632  * The struct declaration for register ALT_EMAC_DMA_AHB_OR_AXI_STATUS.
4633  */
4634 struct ALT_EMAC_DMA_AHB_OR_AXI_STATUS_s
4635 {
4636  const volatile uint32_t AXWHSTS : 1; /* ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS */
4637  const volatile uint32_t AXIRDSTS : 1; /* ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS */
4638  const volatile uint32_t Reserved_31_2 : 30; /* ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2 */
4639 };
4640 
4641 /* The typedef declaration for register ALT_EMAC_DMA_AHB_OR_AXI_STATUS. */
4642 typedef struct ALT_EMAC_DMA_AHB_OR_AXI_STATUS_s ALT_EMAC_DMA_AHB_OR_AXI_STATUS_t;
4643 #endif /* __ASSEMBLY__ */
4644 
4645 /* The reset value of the ALT_EMAC_DMA_AHB_OR_AXI_STATUS register. */
4646 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESET 0x00000000
4647 /* The byte offset of the ALT_EMAC_DMA_AHB_OR_AXI_STATUS register from the beginning of the component. */
4648 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_OFST 0x2c
4649 /* The address of the ALT_EMAC_DMA_AHB_OR_AXI_STATUS register. */
4650 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_AHB_OR_AXI_STATUS_OFST))
4651 
4652 /*
4653  * Register : Current_Host_Transmit_Descriptor
4654  *
4655  * <b> Register 18 (Current Host Transmit Descriptor Register) </b>
4656  *
4657  * The Current Host Transmit Descriptor register points to the start address of the
4658  * current Transmit Descriptor read by the DMA.
4659  *
4660  * Register Layout
4661  *
4662  * Bits | Access | Reset | Description
4663  * :-------|:-------|:------|:----------------------------------------------------------
4664  * [31:0] | R | 0x0 | ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR
4665  *
4666  */
4667 /*
4668  * Field : CURTDESAPTR
4669  *
4670  * Host Transmit Descriptor Address Pointer
4671  *
4672  * Cleared on Reset. Pointer updated by the DMA during operation.
4673  *
4674  * Field Access Macros:
4675  *
4676  */
4677 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR register field. */
4678 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_LSB 0
4679 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR register field. */
4680 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_MSB 31
4681 /* The width in bits of the ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR register field. */
4682 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_WIDTH 32
4683 /* The mask used to set the ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR register field value. */
4684 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_SET_MSK 0xffffffff
4685 /* The mask used to clear the ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR register field value. */
4686 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_CLR_MSK 0x00000000
4687 /* The reset value of the ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR register field. */
4688 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_RESET 0x0
4689 /* Extracts the ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR field value from a register. */
4690 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_GET(value) (((value) & 0xffffffff) >> 0)
4691 /* Produces a ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR register field value suitable for setting the register. */
4692 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_SET(value) (((value) << 0) & 0xffffffff)
4693 
4694 #ifndef __ASSEMBLY__
4695 /*
4696  * WARNING: The C register and register group struct declarations are provided for
4697  * convenience and illustrative purposes. They should, however, be used with
4698  * caution as the C language standard provides no guarantees about the alignment or
4699  * atomicity of device memory accesses. The recommended practice for writing
4700  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4701  * alt_write_word() functions.
4702  *
4703  * The struct declaration for register ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR.
4704  */
4705 struct ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_s
4706 {
4707  const volatile uint32_t CURTDESAPTR : 32; /* ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR */
4708 };
4709 
4710 /* The typedef declaration for register ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR. */
4711 typedef struct ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_s ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_t;
4712 #endif /* __ASSEMBLY__ */
4713 
4714 /* The reset value of the ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR register. */
4715 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_RESET 0x00000000
4716 /* The byte offset of the ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR register from the beginning of the component. */
4717 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_OFST 0x48
4718 /* The address of the ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR register. */
4719 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_OFST))
4720 
4721 /*
4722  * Register : Current_Host_Receive_Descriptor
4723  *
4724  * <b> Register 19 (Current Host Receive Descriptor Register) </b>
4725  *
4726  * The Current Host Receive Descriptor register points to the start address of the
4727  * current Receive Descriptor read by the DMA.
4728  *
4729  * Register Layout
4730  *
4731  * Bits | Access | Reset | Description
4732  * :-------|:-------|:------|:---------------------------------------------------------
4733  * [31:0] | R | 0x0 | ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR
4734  *
4735  */
4736 /*
4737  * Field : CURRDESAPTR
4738  *
4739  * Host Receive Descriptor Address Pointer
4740  *
4741  * Cleared on Reset. Pointer updated by the DMA during operation.
4742  *
4743  * Field Access Macros:
4744  *
4745  */
4746 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR register field. */
4747 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_LSB 0
4748 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR register field. */
4749 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_MSB 31
4750 /* The width in bits of the ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR register field. */
4751 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_WIDTH 32
4752 /* The mask used to set the ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR register field value. */
4753 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_SET_MSK 0xffffffff
4754 /* The mask used to clear the ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR register field value. */
4755 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_CLR_MSK 0x00000000
4756 /* The reset value of the ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR register field. */
4757 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_RESET 0x0
4758 /* Extracts the ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR field value from a register. */
4759 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_GET(value) (((value) & 0xffffffff) >> 0)
4760 /* Produces a ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR register field value suitable for setting the register. */
4761 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_SET(value) (((value) << 0) & 0xffffffff)
4762 
4763 #ifndef __ASSEMBLY__
4764 /*
4765  * WARNING: The C register and register group struct declarations are provided for
4766  * convenience and illustrative purposes. They should, however, be used with
4767  * caution as the C language standard provides no guarantees about the alignment or
4768  * atomicity of device memory accesses. The recommended practice for writing
4769  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4770  * alt_write_word() functions.
4771  *
4772  * The struct declaration for register ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR.
4773  */
4774 struct ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_s
4775 {
4776  const volatile uint32_t CURRDESAPTR : 32; /* ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR */
4777 };
4778 
4779 /* The typedef declaration for register ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR. */
4780 typedef struct ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_s ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_t;
4781 #endif /* __ASSEMBLY__ */
4782 
4783 /* The reset value of the ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR register. */
4784 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_RESET 0x00000000
4785 /* The byte offset of the ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR register from the beginning of the component. */
4786 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_OFST 0x4c
4787 /* The address of the ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR register. */
4788 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_OFST))
4789 
4790 /*
4791  * Register : Current_Host_Transmit_Buffer_Address
4792  *
4793  * <b> Register 20 (Current Host Transmit Buffer Address Register) </b>
4794  *
4795  * The Current Host Transmit Buffer Address register points to the current Transmit
4796  * Buffer Address being read by the DMA.
4797  *
4798  * Register Layout
4799  *
4800  * Bits | Access | Reset | Description
4801  * :-------|:-------|:------|:--------------------------------------------------------------
4802  * [31:0] | R | 0x0 | ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR
4803  *
4804  */
4805 /*
4806  * Field : CURTBUFAPTR
4807  *
4808  * Host Transmit Buffer Address Pointer
4809  *
4810  * Cleared on Reset. Pointer updated by the DMA during operation.
4811  *
4812  * Field Access Macros:
4813  *
4814  */
4815 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR register field. */
4816 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_LSB 0
4817 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR register field. */
4818 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_MSB 31
4819 /* The width in bits of the ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR register field. */
4820 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_WIDTH 32
4821 /* The mask used to set the ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR register field value. */
4822 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_SET_MSK 0xffffffff
4823 /* The mask used to clear the ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR register field value. */
4824 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_CLR_MSK 0x00000000
4825 /* The reset value of the ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR register field. */
4826 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_RESET 0x0
4827 /* Extracts the ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR field value from a register. */
4828 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_GET(value) (((value) & 0xffffffff) >> 0)
4829 /* Produces a ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR register field value suitable for setting the register. */
4830 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_SET(value) (((value) << 0) & 0xffffffff)
4831 
4832 #ifndef __ASSEMBLY__
4833 /*
4834  * WARNING: The C register and register group struct declarations are provided for
4835  * convenience and illustrative purposes. They should, however, be used with
4836  * caution as the C language standard provides no guarantees about the alignment or
4837  * atomicity of device memory accesses. The recommended practice for writing
4838  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4839  * alt_write_word() functions.
4840  *
4841  * The struct declaration for register ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS.
4842  */
4843 struct ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_s
4844 {
4845  const volatile uint32_t CURTBUFAPTR : 32; /* ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR */
4846 };
4847 
4848 /* The typedef declaration for register ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS. */
4849 typedef struct ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_s ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_t;
4850 #endif /* __ASSEMBLY__ */
4851 
4852 /* The reset value of the ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS register. */
4853 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_RESET 0x00000000
4854 /* The byte offset of the ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS register from the beginning of the component. */
4855 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_OFST 0x50
4856 /* The address of the ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS register. */
4857 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_OFST))
4858 
4859 /*
4860  * Register : Current_Host_Receive_Buffer_Address
4861  *
4862  * <b> Register 21 (Current Host Receive Buffer Address Register) </b>
4863  *
4864  * The Current Host Receive Buffer Address register points to the current Receive
4865  * Buffer address being read by the DMA.
4866  *
4867  * Register Layout
4868  *
4869  * Bits | Access | Reset | Description
4870  * :-------|:-------|:------|:-------------------------------------------------------------
4871  * [31:0] | R | 0x0 | ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR
4872  *
4873  */
4874 /*
4875  * Field : CURRBUFAPTR
4876  *
4877  * Host Receive Buffer Address Pointer
4878  *
4879  * Cleared on Reset. Pointer updated by the DMA during operation.
4880  *
4881  * Field Access Macros:
4882  *
4883  */
4884 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR register field. */
4885 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_LSB 0
4886 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR register field. */
4887 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_MSB 31
4888 /* The width in bits of the ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR register field. */
4889 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_WIDTH 32
4890 /* The mask used to set the ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR register field value. */
4891 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_SET_MSK 0xffffffff
4892 /* The mask used to clear the ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR register field value. */
4893 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_CLR_MSK 0x00000000
4894 /* The reset value of the ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR register field. */
4895 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_RESET 0x0
4896 /* Extracts the ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR field value from a register. */
4897 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_GET(value) (((value) & 0xffffffff) >> 0)
4898 /* Produces a ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR register field value suitable for setting the register. */
4899 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_SET(value) (((value) << 0) & 0xffffffff)
4900 
4901 #ifndef __ASSEMBLY__
4902 /*
4903  * WARNING: The C register and register group struct declarations are provided for
4904  * convenience and illustrative purposes. They should, however, be used with
4905  * caution as the C language standard provides no guarantees about the alignment or
4906  * atomicity of device memory accesses. The recommended practice for writing
4907  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4908  * alt_write_word() functions.
4909  *
4910  * The struct declaration for register ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS.
4911  */
4912 struct ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_s
4913 {
4914  const volatile uint32_t CURRBUFAPTR : 32; /* ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR */
4915 };
4916 
4917 /* The typedef declaration for register ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS. */
4918 typedef struct ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_s ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_t;
4919 #endif /* __ASSEMBLY__ */
4920 
4921 /* The reset value of the ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS register. */
4922 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_RESET 0x00000000
4923 /* The byte offset of the ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS register from the beginning of the component. */
4924 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_OFST 0x54
4925 /* The address of the ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS register. */
4926 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_OFST))
4927 
4928 /*
4929  * Register : HW_Feature
4930  *
4931  * <b> Register 22 (HW Feature Register) </b>
4932  *
4933  * This register indicates the presence of the optional features or functions of
4934  * the DWC_gmac. The software driver can use this register to dynamically enable or
4935  * disable the programs related to the optional blocks.
4936  *
4937  * Note: All bits are set or reset as per the selection of features during the
4938  * DWC_gmac configuration.
4939  *
4940  * Register Layout
4941  *
4942  * Bits | Access | Reset | Description
4943  * :--------|:-------|:------|:-------------------------------------
4944  * [0] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_MIISEL
4945  * [1] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_GMIISEL
4946  * [2] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_HDSEL
4947  * [3] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN
4948  * [4] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_HASHSEL
4949  * [5] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL
4950  * [6] | R | 0x0 | ALT_EMAC_DMA_HW_FEATURE_PCSSEL
4951  * [7] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN
4952  * [8] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_SMASEL
4953  * [9] | R | 0x0 | ALT_EMAC_DMA_HW_FEATURE_RWKSEL
4954  * [10] | R | 0x0 | ALT_EMAC_DMA_HW_FEATURE_MGKSEL
4955  * [11] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_MMCSEL
4956  * [12] | R | 0x0 | ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL
4957  * [13] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL
4958  * [14] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_EEESEL
4959  * [15] | R | 0x0 | ALT_EMAC_DMA_HW_FEATURE_AVSEL
4960  * [16] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_TXCOESEL
4961  * [17] | R | 0x0 | ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE
4962  * [18] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE
4963  * [19] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE
4964  * [21:20] | R | 0x0 | ALT_EMAC_DMA_HW_FEATURE_RXCHCNT
4965  * [23:22] | R | 0x0 | ALT_EMAC_DMA_HW_FEATURE_TXCHCNT
4966  * [24] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL
4967  * [25] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_INTTSEN
4968  * [26] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN
4969  * [27] | R | 0x1 | ALT_EMAC_DMA_HW_FEATURE_SAVLANINS
4970  * [30:28] | R | 0x0 | ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
4971  * [31] | R | 0x0 | ALT_EMAC_DMA_HW_FEATURE_RESERVED_31
4972  *
4973  */
4974 /*
4975  * Field : MIISEL
4976  *
4977  * 10 or 100 Mbps support
4978  *
4979  * Field Access Macros:
4980  *
4981  */
4982 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field. */
4983 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_LSB 0
4984 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field. */
4985 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_MSB 0
4986 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field. */
4987 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_WIDTH 1
4988 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field value. */
4989 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_SET_MSK 0x00000001
4990 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field value. */
4991 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_CLR_MSK 0xfffffffe
4992 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field. */
4993 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_RESET 0x1
4994 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_MIISEL field value from a register. */
4995 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_GET(value) (((value) & 0x00000001) >> 0)
4996 /* Produces a ALT_EMAC_DMA_HW_FEATURE_MIISEL register field value suitable for setting the register. */
4997 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_SET(value) (((value) << 0) & 0x00000001)
4998 
4999 /*
5000  * Field : GMIISEL
5001  *
5002  * 1000 Mbps support
5003  *
5004  * Field Access Macros:
5005  *
5006  */
5007 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field. */
5008 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_LSB 1
5009 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field. */
5010 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_MSB 1
5011 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field. */
5012 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_WIDTH 1
5013 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field value. */
5014 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_SET_MSK 0x00000002
5015 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field value. */
5016 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_CLR_MSK 0xfffffffd
5017 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field. */
5018 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_RESET 0x1
5019 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_GMIISEL field value from a register. */
5020 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_GET(value) (((value) & 0x00000002) >> 1)
5021 /* Produces a ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field value suitable for setting the register. */
5022 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_SET(value) (((value) << 1) & 0x00000002)
5023 
5024 /*
5025  * Field : HDSEL
5026  *
5027  * Half-Duplex support
5028  *
5029  * Field Access Macros:
5030  *
5031  */
5032 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field. */
5033 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_LSB 2
5034 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field. */
5035 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_MSB 2
5036 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field. */
5037 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_WIDTH 1
5038 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field value. */
5039 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_SET_MSK 0x00000004
5040 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field value. */
5041 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_CLR_MSK 0xfffffffb
5042 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field. */
5043 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_RESET 0x1
5044 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_HDSEL field value from a register. */
5045 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_GET(value) (((value) & 0x00000004) >> 2)
5046 /* Produces a ALT_EMAC_DMA_HW_FEATURE_HDSEL register field value suitable for setting the register. */
5047 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_SET(value) (((value) << 2) & 0x00000004)
5048 
5049 /*
5050  * Field : EXTHASHEN
5051  *
5052  * Expanded DA Hash Filter
5053  *
5054  * Field Access Macros:
5055  *
5056  */
5057 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN register field. */
5058 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_LSB 3
5059 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN register field. */
5060 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_MSB 3
5061 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN register field. */
5062 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_WIDTH 1
5063 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN register field value. */
5064 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_SET_MSK 0x00000008
5065 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN register field value. */
5066 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_CLR_MSK 0xfffffff7
5067 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN register field. */
5068 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_RESET 0x1
5069 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN field value from a register. */
5070 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_GET(value) (((value) & 0x00000008) >> 3)
5071 /* Produces a ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN register field value suitable for setting the register. */
5072 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_SET(value) (((value) << 3) & 0x00000008)
5073 
5074 /*
5075  * Field : HASHSEL
5076  *
5077  * HASH Filter
5078  *
5079  * Field Access Macros:
5080  *
5081  */
5082 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field. */
5083 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_LSB 4
5084 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field. */
5085 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_MSB 4
5086 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field. */
5087 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_WIDTH 1
5088 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field value. */
5089 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_SET_MSK 0x00000010
5090 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field value. */
5091 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_CLR_MSK 0xffffffef
5092 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field. */
5093 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_RESET 0x1
5094 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_HASHSEL field value from a register. */
5095 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_GET(value) (((value) & 0x00000010) >> 4)
5096 /* Produces a ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field value suitable for setting the register. */
5097 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_SET(value) (((value) << 4) & 0x00000010)
5098 
5099 /*
5100  * Field : ADDMACADRSEL
5101  *
5102  * Multiple MAC Address Registers
5103  *
5104  * Field Access Macros:
5105  *
5106  */
5107 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field. */
5108 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_LSB 5
5109 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field. */
5110 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_MSB 5
5111 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field. */
5112 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_WIDTH 1
5113 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field value. */
5114 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_SET_MSK 0x00000020
5115 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field value. */
5116 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_CLR_MSK 0xffffffdf
5117 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field. */
5118 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_RESET 0x1
5119 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL field value from a register. */
5120 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_GET(value) (((value) & 0x00000020) >> 5)
5121 /* Produces a ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field value suitable for setting the register. */
5122 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_SET(value) (((value) << 5) & 0x00000020)
5123 
5124 /*
5125  * Field : PCSSEL
5126  *
5127  * PCS registers (TBI, SGMII, or RTBI PHY interface)
5128  *
5129  * Field Access Macros:
5130  *
5131  */
5132 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field. */
5133 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_LSB 6
5134 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field. */
5135 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_MSB 6
5136 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field. */
5137 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_WIDTH 1
5138 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field value. */
5139 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_SET_MSK 0x00000040
5140 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field value. */
5141 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_CLR_MSK 0xffffffbf
5142 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field. */
5143 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_RESET 0x0
5144 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_PCSSEL field value from a register. */
5145 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_GET(value) (((value) & 0x00000040) >> 6)
5146 /* Produces a ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field value suitable for setting the register. */
5147 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_SET(value) (((value) << 6) & 0x00000040)
5148 
5149 /*
5150  * Field : L3L4FLTREN
5151  *
5152  * Layer 3 and Layer 4 Filter Feature
5153  *
5154  * Field Access Macros:
5155  *
5156  */
5157 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN register field. */
5158 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_LSB 7
5159 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN register field. */
5160 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_MSB 7
5161 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN register field. */
5162 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_WIDTH 1
5163 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN register field value. */
5164 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_SET_MSK 0x00000080
5165 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN register field value. */
5166 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_CLR_MSK 0xffffff7f
5167 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN register field. */
5168 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_RESET 0x1
5169 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN field value from a register. */
5170 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_GET(value) (((value) & 0x00000080) >> 7)
5171 /* Produces a ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN register field value suitable for setting the register. */
5172 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_SET(value) (((value) << 7) & 0x00000080)
5173 
5174 /*
5175  * Field : SMASEL
5176  *
5177  * SMA (MDIO) Interface
5178  *
5179  * Field Access Macros:
5180  *
5181  */
5182 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field. */
5183 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_LSB 8
5184 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field. */
5185 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_MSB 8
5186 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field. */
5187 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_WIDTH 1
5188 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field value. */
5189 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_SET_MSK 0x00000100
5190 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field value. */
5191 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_CLR_MSK 0xfffffeff
5192 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field. */
5193 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_RESET 0x1
5194 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_SMASEL field value from a register. */
5195 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_GET(value) (((value) & 0x00000100) >> 8)
5196 /* Produces a ALT_EMAC_DMA_HW_FEATURE_SMASEL register field value suitable for setting the register. */
5197 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_SET(value) (((value) << 8) & 0x00000100)
5198 
5199 /*
5200  * Field : RWKSEL
5201  *
5202  * PMT Remote Wakeup
5203  *
5204  * Field Access Macros:
5205  *
5206  */
5207 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field. */
5208 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_LSB 9
5209 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field. */
5210 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_MSB 9
5211 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field. */
5212 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_WIDTH 1
5213 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field value. */
5214 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_SET_MSK 0x00000200
5215 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field value. */
5216 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_CLR_MSK 0xfffffdff
5217 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field. */
5218 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_RESET 0x0
5219 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_RWKSEL field value from a register. */
5220 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_GET(value) (((value) & 0x00000200) >> 9)
5221 /* Produces a ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field value suitable for setting the register. */
5222 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_SET(value) (((value) << 9) & 0x00000200)
5223 
5224 /*
5225  * Field : MGKSEL
5226  *
5227  * PMT Magic Packet
5228  *
5229  * Field Access Macros:
5230  *
5231  */
5232 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field. */
5233 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_LSB 10
5234 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field. */
5235 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_MSB 10
5236 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field. */
5237 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_WIDTH 1
5238 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field value. */
5239 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_SET_MSK 0x00000400
5240 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field value. */
5241 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_CLR_MSK 0xfffffbff
5242 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field. */
5243 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_RESET 0x0
5244 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_MGKSEL field value from a register. */
5245 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_GET(value) (((value) & 0x00000400) >> 10)
5246 /* Produces a ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field value suitable for setting the register. */
5247 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_SET(value) (((value) << 10) & 0x00000400)
5248 
5249 /*
5250  * Field : MMCSEL
5251  *
5252  * RMON Module
5253  *
5254  * Field Access Macros:
5255  *
5256  */
5257 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field. */
5258 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_LSB 11
5259 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field. */
5260 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_MSB 11
5261 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field. */
5262 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_WIDTH 1
5263 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field value. */
5264 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_SET_MSK 0x00000800
5265 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field value. */
5266 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_CLR_MSK 0xfffff7ff
5267 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field. */
5268 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_RESET 0x1
5269 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_MMCSEL field value from a register. */
5270 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_GET(value) (((value) & 0x00000800) >> 11)
5271 /* Produces a ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field value suitable for setting the register. */
5272 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_SET(value) (((value) << 11) & 0x00000800)
5273 
5274 /*
5275  * Field : TSVER1SEL
5276  *
5277  * Only IEEE 1588-2002 Timestamp
5278  *
5279  * Field Access Macros:
5280  *
5281  */
5282 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field. */
5283 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_LSB 12
5284 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field. */
5285 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_MSB 12
5286 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field. */
5287 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_WIDTH 1
5288 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field value. */
5289 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_SET_MSK 0x00001000
5290 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field value. */
5291 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_CLR_MSK 0xffffefff
5292 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field. */
5293 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_RESET 0x0
5294 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL field value from a register. */
5295 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_GET(value) (((value) & 0x00001000) >> 12)
5296 /* Produces a ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field value suitable for setting the register. */
5297 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_SET(value) (((value) << 12) & 0x00001000)
5298 
5299 /*
5300  * Field : TSVER2SEL
5301  *
5302  * IEEE 1588-2008 Advanced Timestamp
5303  *
5304  * Field Access Macros:
5305  *
5306  */
5307 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field. */
5308 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_LSB 13
5309 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field. */
5310 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_MSB 13
5311 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field. */
5312 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_WIDTH 1
5313 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field value. */
5314 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_SET_MSK 0x00002000
5315 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field value. */
5316 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_CLR_MSK 0xffffdfff
5317 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field. */
5318 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_RESET 0x1
5319 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL field value from a register. */
5320 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_GET(value) (((value) & 0x00002000) >> 13)
5321 /* Produces a ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field value suitable for setting the register. */
5322 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_SET(value) (((value) << 13) & 0x00002000)
5323 
5324 /*
5325  * Field : EEESEL
5326  *
5327  * Energy Efficient Ethernet
5328  *
5329  * Field Access Macros:
5330  *
5331  */
5332 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field. */
5333 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_LSB 14
5334 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field. */
5335 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_MSB 14
5336 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field. */
5337 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_WIDTH 1
5338 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field value. */
5339 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_SET_MSK 0x00004000
5340 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field value. */
5341 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_CLR_MSK 0xffffbfff
5342 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field. */
5343 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_RESET 0x1
5344 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_EEESEL field value from a register. */
5345 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_GET(value) (((value) & 0x00004000) >> 14)
5346 /* Produces a ALT_EMAC_DMA_HW_FEATURE_EEESEL register field value suitable for setting the register. */
5347 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_SET(value) (((value) << 14) & 0x00004000)
5348 
5349 /*
5350  * Field : AVSEL
5351  *
5352  * AV Feature
5353  *
5354  * Field Access Macros:
5355  *
5356  */
5357 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field. */
5358 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_LSB 15
5359 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field. */
5360 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_MSB 15
5361 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field. */
5362 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_WIDTH 1
5363 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field value. */
5364 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_SET_MSK 0x00008000
5365 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field value. */
5366 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_CLR_MSK 0xffff7fff
5367 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field. */
5368 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_RESET 0x0
5369 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_AVSEL field value from a register. */
5370 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_GET(value) (((value) & 0x00008000) >> 15)
5371 /* Produces a ALT_EMAC_DMA_HW_FEATURE_AVSEL register field value suitable for setting the register. */
5372 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_SET(value) (((value) << 15) & 0x00008000)
5373 
5374 /*
5375  * Field : TXCOESEL
5376  *
5377  * Checksum Offload in Tx
5378  *
5379  * Field Access Macros:
5380  *
5381  */
5382 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXCOESEL register field. */
5383 #define ALT_EMAC_DMA_HW_FEATURE_TXCOESEL_LSB 16
5384 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXCOESEL register field. */
5385 #define ALT_EMAC_DMA_HW_FEATURE_TXCOESEL_MSB 16
5386 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TXCOESEL register field. */
5387 #define ALT_EMAC_DMA_HW_FEATURE_TXCOESEL_WIDTH 1
5388 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TXCOESEL register field value. */
5389 #define ALT_EMAC_DMA_HW_FEATURE_TXCOESEL_SET_MSK 0x00010000
5390 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TXCOESEL register field value. */
5391 #define ALT_EMAC_DMA_HW_FEATURE_TXCOESEL_CLR_MSK 0xfffeffff
5392 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_TXCOESEL register field. */
5393 #define ALT_EMAC_DMA_HW_FEATURE_TXCOESEL_RESET 0x1
5394 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_TXCOESEL field value from a register. */
5395 #define ALT_EMAC_DMA_HW_FEATURE_TXCOESEL_GET(value) (((value) & 0x00010000) >> 16)
5396 /* Produces a ALT_EMAC_DMA_HW_FEATURE_TXCOESEL register field value suitable for setting the register. */
5397 #define ALT_EMAC_DMA_HW_FEATURE_TXCOESEL_SET(value) (((value) << 16) & 0x00010000)
5398 
5399 /*
5400  * Field : RXTYP1COE
5401  *
5402  * IP Checksum Offload (Type 1) in Rx
5403  *
5404  * Note: If IPCHKSUM_EN = Enabled and IPC_FULL_OFFLOAD = Enabled, then RXTYP1COE =
5405  * 0 and RXTYP2COE =1.
5406  *
5407  * Field Access Macros:
5408  *
5409  */
5410 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field. */
5411 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_LSB 17
5412 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field. */
5413 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_MSB 17
5414 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field. */
5415 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_WIDTH 1
5416 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field value. */
5417 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_SET_MSK 0x00020000
5418 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field value. */
5419 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_CLR_MSK 0xfffdffff
5420 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field. */
5421 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_RESET 0x0
5422 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE field value from a register. */
5423 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_GET(value) (((value) & 0x00020000) >> 17)
5424 /* Produces a ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field value suitable for setting the register. */
5425 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_SET(value) (((value) << 17) & 0x00020000)
5426 
5427 /*
5428  * Field : RXTYP2COE
5429  *
5430  * IP Checksum Offload (Type 2) in Rx
5431  *
5432  * Field Access Macros:
5433  *
5434  */
5435 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field. */
5436 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_LSB 18
5437 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field. */
5438 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_MSB 18
5439 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field. */
5440 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_WIDTH 1
5441 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field value. */
5442 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_SET_MSK 0x00040000
5443 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field value. */
5444 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_CLR_MSK 0xfffbffff
5445 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field. */
5446 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_RESET 0x1
5447 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE field value from a register. */
5448 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_GET(value) (((value) & 0x00040000) >> 18)
5449 /* Produces a ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field value suitable for setting the register. */
5450 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_SET(value) (((value) << 18) & 0x00040000)
5451 
5452 /*
5453  * Field : RXFIFOSIZE
5454  *
5455  * Rx FIFO > 2,048 Bytes
5456  *
5457  * Field Access Macros:
5458  *
5459  */
5460 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field. */
5461 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_LSB 19
5462 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field. */
5463 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_MSB 19
5464 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field. */
5465 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_WIDTH 1
5466 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field value. */
5467 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_SET_MSK 0x00080000
5468 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field value. */
5469 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_CLR_MSK 0xfff7ffff
5470 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field. */
5471 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_RESET 0x1
5472 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE field value from a register. */
5473 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_GET(value) (((value) & 0x00080000) >> 19)
5474 /* Produces a ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field value suitable for setting the register. */
5475 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_SET(value) (((value) << 19) & 0x00080000)
5476 
5477 /*
5478  * Field : RXCHCNT
5479  *
5480  * Number of additional Rx channels
5481  *
5482  * Field Access Macros:
5483  *
5484  */
5485 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field. */
5486 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_LSB 20
5487 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field. */
5488 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_MSB 21
5489 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field. */
5490 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_WIDTH 2
5491 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field value. */
5492 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_SET_MSK 0x00300000
5493 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field value. */
5494 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_CLR_MSK 0xffcfffff
5495 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field. */
5496 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_RESET 0x0
5497 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT field value from a register. */
5498 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_GET(value) (((value) & 0x00300000) >> 20)
5499 /* Produces a ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field value suitable for setting the register. */
5500 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_SET(value) (((value) << 20) & 0x00300000)
5501 
5502 /*
5503  * Field : TXCHCNT
5504  *
5505  * Number of additional Tx channels
5506  *
5507  * Field Access Macros:
5508  *
5509  */
5510 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field. */
5511 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_LSB 22
5512 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field. */
5513 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_MSB 23
5514 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field. */
5515 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_WIDTH 2
5516 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field value. */
5517 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_SET_MSK 0x00c00000
5518 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field value. */
5519 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_CLR_MSK 0xff3fffff
5520 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field. */
5521 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_RESET 0x0
5522 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT field value from a register. */
5523 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_GET(value) (((value) & 0x00c00000) >> 22)
5524 /* Produces a ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field value suitable for setting the register. */
5525 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_SET(value) (((value) << 22) & 0x00c00000)
5526 
5527 /*
5528  * Field : ENHDESSEL
5529  *
5530  * Alternate (Enhanced Descriptor)
5531  *
5532  * Field Access Macros:
5533  *
5534  */
5535 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field. */
5536 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_LSB 24
5537 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field. */
5538 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_MSB 24
5539 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field. */
5540 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_WIDTH 1
5541 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field value. */
5542 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_SET_MSK 0x01000000
5543 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field value. */
5544 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_CLR_MSK 0xfeffffff
5545 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field. */
5546 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_RESET 0x1
5547 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL field value from a register. */
5548 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_GET(value) (((value) & 0x01000000) >> 24)
5549 /* Produces a ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field value suitable for setting the register. */
5550 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_SET(value) (((value) << 24) & 0x01000000)
5551 
5552 /*
5553  * Field : INTTSEN
5554  *
5555  * Timestamping with Internal System Time
5556  *
5557  * Field Access Macros:
5558  *
5559  */
5560 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_INTTSEN register field. */
5561 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_LSB 25
5562 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_INTTSEN register field. */
5563 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_MSB 25
5564 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_INTTSEN register field. */
5565 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_WIDTH 1
5566 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_INTTSEN register field value. */
5567 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_SET_MSK 0x02000000
5568 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_INTTSEN register field value. */
5569 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_CLR_MSK 0xfdffffff
5570 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_INTTSEN register field. */
5571 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_RESET 0x1
5572 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_INTTSEN field value from a register. */
5573 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_GET(value) (((value) & 0x02000000) >> 25)
5574 /* Produces a ALT_EMAC_DMA_HW_FEATURE_INTTSEN register field value suitable for setting the register. */
5575 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_SET(value) (((value) << 25) & 0x02000000)
5576 
5577 /*
5578  * Field : FLEXIPPSEN
5579  *
5580  * Flexible Pulse-Per-Second Output
5581  *
5582  * Field Access Macros:
5583  *
5584  */
5585 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN register field. */
5586 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_LSB 26
5587 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN register field. */
5588 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_MSB 26
5589 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN register field. */
5590 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_WIDTH 1
5591 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN register field value. */
5592 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_SET_MSK 0x04000000
5593 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN register field value. */
5594 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_CLR_MSK 0xfbffffff
5595 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN register field. */
5596 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_RESET 0x1
5597 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN field value from a register. */
5598 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_GET(value) (((value) & 0x04000000) >> 26)
5599 /* Produces a ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN register field value suitable for setting the register. */
5600 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_SET(value) (((value) << 26) & 0x04000000)
5601 
5602 /*
5603  * Field : SAVLANINS
5604  *
5605  * Source Address or VLAN Insertion
5606  *
5607  * Field Access Macros:
5608  *
5609  */
5610 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_SAVLANINS register field. */
5611 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_LSB 27
5612 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_SAVLANINS register field. */
5613 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_MSB 27
5614 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_SAVLANINS register field. */
5615 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_WIDTH 1
5616 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_SAVLANINS register field value. */
5617 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_SET_MSK 0x08000000
5618 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_SAVLANINS register field value. */
5619 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_CLR_MSK 0xf7ffffff
5620 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_SAVLANINS register field. */
5621 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_RESET 0x1
5622 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_SAVLANINS field value from a register. */
5623 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_GET(value) (((value) & 0x08000000) >> 27)
5624 /* Produces a ALT_EMAC_DMA_HW_FEATURE_SAVLANINS register field value suitable for setting the register. */
5625 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_SET(value) (((value) << 27) & 0x08000000)
5626 
5627 /*
5628  * Field : ACTPHYIF
5629  *
5630  * Active or Selected PHY interface
5631  *
5632  * When you have multiple PHY interfaces in your configuration, this field
5633  * indicates the sampled value of phy_intf_sel_i during reset de-assertion
5634  *
5635  * * 0000: GMII or MII
5636  *
5637  * * 0001: RGMII
5638  *
5639  * * 0010: SGMII
5640  *
5641  * * 0011: TBI
5642  *
5643  * * 0100: RMII
5644  *
5645  * * 0101: RTBI
5646  *
5647  * * 0110: SMII
5648  *
5649  * * 0111: RevMII
5650  *
5651  * * All Others: Reserved
5652  *
5653  * Field Access Macros:
5654  *
5655  */
5656 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field. */
5657 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_LSB 28
5658 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field. */
5659 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_MSB 30
5660 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field. */
5661 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_WIDTH 3
5662 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field value. */
5663 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_SET_MSK 0x70000000
5664 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field value. */
5665 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_CLR_MSK 0x8fffffff
5666 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field. */
5667 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_RESET 0x0
5668 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF field value from a register. */
5669 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_GET(value) (((value) & 0x70000000) >> 28)
5670 /* Produces a ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field value suitable for setting the register. */
5671 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_SET(value) (((value) << 28) & 0x70000000)
5672 
5673 /*
5674  * Field : Reserved_31
5675  *
5676  * Reserved
5677  *
5678  * Field Access Macros:
5679  *
5680  */
5681 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RESERVED_31 register field. */
5682 #define ALT_EMAC_DMA_HW_FEATURE_RESERVED_31_LSB 31
5683 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RESERVED_31 register field. */
5684 #define ALT_EMAC_DMA_HW_FEATURE_RESERVED_31_MSB 31
5685 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RESERVED_31 register field. */
5686 #define ALT_EMAC_DMA_HW_FEATURE_RESERVED_31_WIDTH 1
5687 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RESERVED_31 register field value. */
5688 #define ALT_EMAC_DMA_HW_FEATURE_RESERVED_31_SET_MSK 0x80000000
5689 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RESERVED_31 register field value. */
5690 #define ALT_EMAC_DMA_HW_FEATURE_RESERVED_31_CLR_MSK 0x7fffffff
5691 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RESERVED_31 register field. */
5692 #define ALT_EMAC_DMA_HW_FEATURE_RESERVED_31_RESET 0x0
5693 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_RESERVED_31 field value from a register. */
5694 #define ALT_EMAC_DMA_HW_FEATURE_RESERVED_31_GET(value) (((value) & 0x80000000) >> 31)
5695 /* Produces a ALT_EMAC_DMA_HW_FEATURE_RESERVED_31 register field value suitable for setting the register. */
5696 #define ALT_EMAC_DMA_HW_FEATURE_RESERVED_31_SET(value) (((value) << 31) & 0x80000000)
5697 
5698 #ifndef __ASSEMBLY__
5699 /*
5700  * WARNING: The C register and register group struct declarations are provided for
5701  * convenience and illustrative purposes. They should, however, be used with
5702  * caution as the C language standard provides no guarantees about the alignment or
5703  * atomicity of device memory accesses. The recommended practice for writing
5704  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5705  * alt_write_word() functions.
5706  *
5707  * The struct declaration for register ALT_EMAC_DMA_HW_FEATURE.
5708  */
5709 struct ALT_EMAC_DMA_HW_FEATURE_s
5710 {
5711  const volatile uint32_t MIISEL : 1; /* ALT_EMAC_DMA_HW_FEATURE_MIISEL */
5712  const volatile uint32_t GMIISEL : 1; /* ALT_EMAC_DMA_HW_FEATURE_GMIISEL */
5713  const volatile uint32_t HDSEL : 1; /* ALT_EMAC_DMA_HW_FEATURE_HDSEL */
5714  const volatile uint32_t EXTHASHEN : 1; /* ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN */
5715  const volatile uint32_t HASHSEL : 1; /* ALT_EMAC_DMA_HW_FEATURE_HASHSEL */
5716  const volatile uint32_t ADDMACADRSEL : 1; /* ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL */
5717  const volatile uint32_t PCSSEL : 1; /* ALT_EMAC_DMA_HW_FEATURE_PCSSEL */
5718  const volatile uint32_t L3L4FLTREN : 1; /* ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN */
5719  const volatile uint32_t SMASEL : 1; /* ALT_EMAC_DMA_HW_FEATURE_SMASEL */
5720  const volatile uint32_t RWKSEL : 1; /* ALT_EMAC_DMA_HW_FEATURE_RWKSEL */
5721  const volatile uint32_t MGKSEL : 1; /* ALT_EMAC_DMA_HW_FEATURE_MGKSEL */
5722  const volatile uint32_t MMCSEL : 1; /* ALT_EMAC_DMA_HW_FEATURE_MMCSEL */
5723  const volatile uint32_t TSVER1SEL : 1; /* ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL */
5724  const volatile uint32_t TSVER2SEL : 1; /* ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL */
5725  const volatile uint32_t EEESEL : 1; /* ALT_EMAC_DMA_HW_FEATURE_EEESEL */
5726  const volatile uint32_t AVSEL : 1; /* ALT_EMAC_DMA_HW_FEATURE_AVSEL */
5727  const volatile uint32_t TXCOESEL : 1; /* ALT_EMAC_DMA_HW_FEATURE_TXCOESEL */
5728  const volatile uint32_t RXTYP1COE : 1; /* ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE */
5729  const volatile uint32_t RXTYP2COE : 1; /* ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE */
5730  const volatile uint32_t RXFIFOSIZE : 1; /* ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE */
5731  const volatile uint32_t RXCHCNT : 2; /* ALT_EMAC_DMA_HW_FEATURE_RXCHCNT */
5732  const volatile uint32_t TXCHCNT : 2; /* ALT_EMAC_DMA_HW_FEATURE_TXCHCNT */
5733  const volatile uint32_t ENHDESSEL : 1; /* ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL */
5734  const volatile uint32_t INTTSEN : 1; /* ALT_EMAC_DMA_HW_FEATURE_INTTSEN */
5735  const volatile uint32_t FLEXIPPSEN : 1; /* ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN */
5736  const volatile uint32_t SAVLANINS : 1; /* ALT_EMAC_DMA_HW_FEATURE_SAVLANINS */
5737  const volatile uint32_t ACTPHYIF : 3; /* ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF */
5738  const volatile uint32_t Reserved_31 : 1; /* ALT_EMAC_DMA_HW_FEATURE_RESERVED_31 */
5739 };
5740 
5741 /* The typedef declaration for register ALT_EMAC_DMA_HW_FEATURE. */
5742 typedef struct ALT_EMAC_DMA_HW_FEATURE_s ALT_EMAC_DMA_HW_FEATURE_t;
5743 #endif /* __ASSEMBLY__ */
5744 
5745 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE register. */
5746 #define ALT_EMAC_DMA_HW_FEATURE_RESET 0x0f0d69bf
5747 /* The byte offset of the ALT_EMAC_DMA_HW_FEATURE register from the beginning of the component. */
5748 #define ALT_EMAC_DMA_HW_FEATURE_OFST 0x58
5749 /* The address of the ALT_EMAC_DMA_HW_FEATURE register. */
5750 #define ALT_EMAC_DMA_HW_FEATURE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_HW_FEATURE_OFST))
5751 
5752 #ifndef __ASSEMBLY__
5753 /*
5754  * WARNING: The C register and register group struct declarations are provided for
5755  * convenience and illustrative purposes. They should, however, be used with
5756  * caution as the C language standard provides no guarantees about the alignment or
5757  * atomicity of device memory accesses. The recommended practice for writing
5758  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5759  * alt_write_word() functions.
5760  *
5761  * The struct declaration for register group ALT_EMAC_DMA.
5762  */
5763 struct ALT_EMAC_DMA_s
5764 {
5765  volatile ALT_EMAC_DMA_BUS_MODE_t Bus_Mode; /* ALT_EMAC_DMA_BUS_MODE */
5766  volatile ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_t Transmit_Poll_Demand; /* ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND */
5767  volatile ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_t Receive_Poll_Demand; /* ALT_EMAC_DMA_RECEIVE_POLL_DEMAND */
5768  volatile ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_t Receive_Descriptor_List_Address; /* ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS */
5769  volatile ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_t Transmit_Descriptor_List_Address; /* ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS */
5770  volatile ALT_EMAC_DMA_STATUS_t Status; /* ALT_EMAC_DMA_STATUS */
5771  volatile ALT_EMAC_DMA_OPERATION_MODE_t Operation_Mode; /* ALT_EMAC_DMA_OPERATION_MODE */
5772  volatile ALT_EMAC_DMA_INTERRUPT_ENABLE_t Interrupt_Enable; /* ALT_EMAC_DMA_INTERRUPT_ENABLE */
5773  volatile ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_t Missed_Frame_And_Buffer_Overflow_Counter; /* ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER */
5774  volatile ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_t Receive_Interrupt_Watchdog_Timer; /* ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER */
5775  volatile ALT_EMAC_DMA_AXI_BUS_MODE_t AXI_Bus_Mode; /* ALT_EMAC_DMA_AXI_BUS_MODE */
5776  volatile ALT_EMAC_DMA_AHB_OR_AXI_STATUS_t AHB_or_AXI_Status; /* ALT_EMAC_DMA_AHB_OR_AXI_STATUS */
5777  volatile uint32_t _pad_0x30_0x47[6]; /* *UNDEFINED* */
5778  volatile ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_t Current_Host_Transmit_Descriptor; /* ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR */
5779  volatile ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_t Current_Host_Receive_Descriptor; /* ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR */
5780  volatile ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_t Current_Host_Transmit_Buffer_Address; /* ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS */
5781  volatile ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_t Current_Host_Receive_Buffer_Address; /* ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS */
5782  volatile ALT_EMAC_DMA_HW_FEATURE_t HW_Feature; /* ALT_EMAC_DMA_HW_FEATURE */
5783  volatile uint32_t _pad_0x5c_0x100[41]; /* *UNDEFINED* */
5784 };
5785 
5786 /* The typedef declaration for register group ALT_EMAC_DMA. */
5787 typedef struct ALT_EMAC_DMA_s ALT_EMAC_DMA_t;
5788 /* The struct declaration for the raw register contents of register group ALT_EMAC_DMA. */
5789 struct ALT_EMAC_DMA_raw_s
5790 {
5791  volatile uint32_t Bus_Mode; /* ALT_EMAC_DMA_BUS_MODE */
5792  volatile uint32_t Transmit_Poll_Demand; /* ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND */
5793  volatile uint32_t Receive_Poll_Demand; /* ALT_EMAC_DMA_RECEIVE_POLL_DEMAND */
5794  volatile uint32_t Receive_Descriptor_List_Address; /* ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS */
5795  volatile uint32_t Transmit_Descriptor_List_Address; /* ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS */
5796  volatile uint32_t Status; /* ALT_EMAC_DMA_STATUS */
5797  volatile uint32_t Operation_Mode; /* ALT_EMAC_DMA_OPERATION_MODE */
5798  volatile uint32_t Interrupt_Enable; /* ALT_EMAC_DMA_INTERRUPT_ENABLE */
5799  volatile uint32_t Missed_Frame_And_Buffer_Overflow_Counter; /* ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER */
5800  volatile uint32_t Receive_Interrupt_Watchdog_Timer; /* ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER */
5801  volatile uint32_t AXI_Bus_Mode; /* ALT_EMAC_DMA_AXI_BUS_MODE */
5802  volatile uint32_t AHB_or_AXI_Status; /* ALT_EMAC_DMA_AHB_OR_AXI_STATUS */
5803  volatile uint32_t _pad_0x30_0x47[6]; /* *UNDEFINED* */
5804  volatile uint32_t Current_Host_Transmit_Descriptor; /* ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR */
5805  volatile uint32_t Current_Host_Receive_Descriptor; /* ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR */
5806  volatile uint32_t Current_Host_Transmit_Buffer_Address; /* ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS */
5807  volatile uint32_t Current_Host_Receive_Buffer_Address; /* ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS */
5808  volatile uint32_t HW_Feature; /* ALT_EMAC_DMA_HW_FEATURE */
5809  volatile uint32_t _pad_0x5c_0x100[41]; /* *UNDEFINED* */
5810 };
5811 
5812 /* The typedef declaration for the raw register contents of register group ALT_EMAC_DMA. */
5813 typedef struct ALT_EMAC_DMA_raw_s ALT_EMAC_DMA_raw_t;
5814 #endif /* __ASSEMBLY__ */
5815 
5816 
5817 #ifdef __cplusplus
5818 }
5819 #endif /* __cplusplus */
5820 #endif /* __ALT_SOCAL_EMAC_DMA_H__ */
5821