35 #ifndef __ALT_SOCAL_ECC_SDMMC_H__
36 #define __ALT_SOCAL_ECC_SDMMC_H__
74 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_LSB 0
76 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_MSB 15
78 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_WIDTH 16
80 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_SET_MSK 0x0000ffff
82 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_CLR_MSK 0xffff0000
84 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_RESET 0x0
86 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_GET(value) (((value) & 0x0000ffff) >> 0)
88 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_SET(value) (((value) << 0) & 0x0000ffff)
101 struct ALT_ECC_SDMMC_IP_REV_ID_s
103 const uint32_t SIREV : 16;
108 typedef volatile struct ALT_ECC_SDMMC_IP_REV_ID_s ALT_ECC_SDMMC_IP_REV_ID_t;
112 #define ALT_ECC_SDMMC_IP_REV_ID_RESET 0x00000000
114 #define ALT_ECC_SDMMC_IP_REV_ID_OFST 0x0
145 #define ALT_ECC_SDMMC_CTL_ECC_EN_LSB 0
147 #define ALT_ECC_SDMMC_CTL_ECC_EN_MSB 0
149 #define ALT_ECC_SDMMC_CTL_ECC_EN_WIDTH 1
151 #define ALT_ECC_SDMMC_CTL_ECC_EN_SET_MSK 0x00000001
153 #define ALT_ECC_SDMMC_CTL_ECC_EN_CLR_MSK 0xfffffffe
155 #define ALT_ECC_SDMMC_CTL_ECC_EN_RESET 0x0
157 #define ALT_ECC_SDMMC_CTL_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
159 #define ALT_ECC_SDMMC_CTL_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
170 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_LSB 8
172 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_MSB 8
174 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_WIDTH 1
176 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_SET_MSK 0x00000100
178 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_CLR_MSK 0xfffffeff
180 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_RESET 0x0
182 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_GET(value) (((value) & 0x00000100) >> 8)
184 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_SET(value) (((value) << 8) & 0x00000100)
195 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_LSB 9
197 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_MSB 9
199 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_WIDTH 1
201 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_SET_MSK 0x00000200
203 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_CLR_MSK 0xfffffdff
205 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_RESET 0x0
207 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_GET(value) (((value) & 0x00000200) >> 9)
209 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_SET(value) (((value) << 9) & 0x00000200)
220 #define ALT_ECC_SDMMC_CTL_INITA_LSB 16
222 #define ALT_ECC_SDMMC_CTL_INITA_MSB 16
224 #define ALT_ECC_SDMMC_CTL_INITA_WIDTH 1
226 #define ALT_ECC_SDMMC_CTL_INITA_SET_MSK 0x00010000
228 #define ALT_ECC_SDMMC_CTL_INITA_CLR_MSK 0xfffeffff
230 #define ALT_ECC_SDMMC_CTL_INITA_RESET 0x0
232 #define ALT_ECC_SDMMC_CTL_INITA_GET(value) (((value) & 0x00010000) >> 16)
234 #define ALT_ECC_SDMMC_CTL_INITA_SET(value) (((value) << 16) & 0x00010000)
245 #define ALT_ECC_SDMMC_CTL_INITB_LSB 24
247 #define ALT_ECC_SDMMC_CTL_INITB_MSB 24
249 #define ALT_ECC_SDMMC_CTL_INITB_WIDTH 1
251 #define ALT_ECC_SDMMC_CTL_INITB_SET_MSK 0x01000000
253 #define ALT_ECC_SDMMC_CTL_INITB_CLR_MSK 0xfeffffff
255 #define ALT_ECC_SDMMC_CTL_INITB_RESET 0x0
257 #define ALT_ECC_SDMMC_CTL_INITB_GET(value) (((value) & 0x01000000) >> 24)
259 #define ALT_ECC_SDMMC_CTL_INITB_SET(value) (((value) << 24) & 0x01000000)
272 struct ALT_ECC_SDMMC_CTL_s
276 uint32_t CNT_RSTA : 1;
277 uint32_t CNT_RSTB : 1;
286 typedef volatile struct ALT_ECC_SDMMC_CTL_s ALT_ECC_SDMMC_CTL_t;
290 #define ALT_ECC_SDMMC_CTL_RESET 0x00000000
292 #define ALT_ECC_SDMMC_CTL_OFST 0x8
319 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_LSB 0
321 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_MSB 0
323 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_WIDTH 1
325 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_SET_MSK 0x00000001
327 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_CLR_MSK 0xfffffffe
329 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_RESET 0x0
331 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_GET(value) (((value) & 0x00000001) >> 0)
333 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_SET(value) (((value) << 0) & 0x00000001)
345 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_LSB 8
347 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_MSB 8
349 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_WIDTH 1
351 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_SET_MSK 0x00000100
353 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_CLR_MSK 0xfffffeff
355 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_RESET 0x0
357 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_GET(value) (((value) & 0x00000100) >> 8)
359 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_SET(value) (((value) << 8) & 0x00000100)
372 struct ALT_ECC_SDMMC_INITSTAT_s
374 uint32_t INITCOMPLETEA : 1;
376 uint32_t INITCOMPLETEB : 1;
381 typedef volatile struct ALT_ECC_SDMMC_INITSTAT_s ALT_ECC_SDMMC_INITSTAT_t;
385 #define ALT_ECC_SDMMC_INITSTAT_RESET 0x00000000
387 #define ALT_ECC_SDMMC_INITSTAT_OFST 0xc
411 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_LSB 0
413 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_MSB 0
415 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_WIDTH 1
417 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_SET_MSK 0x00000001
419 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_CLR_MSK 0xfffffffe
421 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_RESET 0x0
423 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_GET(value) (((value) & 0x00000001) >> 0)
425 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_SET(value) (((value) << 0) & 0x00000001)
438 struct ALT_ECC_SDMMC_ERRINTEN_s
440 uint32_t SERRINTEN : 1;
445 typedef volatile struct ALT_ECC_SDMMC_ERRINTEN_s ALT_ECC_SDMMC_ERRINTEN_t;
449 #define ALT_ECC_SDMMC_ERRINTEN_RESET 0x00000000
451 #define ALT_ECC_SDMMC_ERRINTEN_OFST 0x10
475 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_LSB 0
477 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_MSB 0
479 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_WIDTH 1
481 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_SET_MSK 0x00000001
483 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_CLR_MSK 0xfffffffe
485 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_RESET 0x0
487 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_GET(value) (((value) & 0x00000001) >> 0)
489 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_SET(value) (((value) << 0) & 0x00000001)
502 struct ALT_ECC_SDMMC_ERRINTENS_s
504 uint32_t SERRINTS : 1;
509 typedef volatile struct ALT_ECC_SDMMC_ERRINTENS_s ALT_ECC_SDMMC_ERRINTENS_t;
513 #define ALT_ECC_SDMMC_ERRINTENS_RESET 0x00000000
515 #define ALT_ECC_SDMMC_ERRINTENS_OFST 0x14
546 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_LSB 0
548 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_MSB 0
550 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_WIDTH 1
552 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_SET_MSK 0x00000001
554 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_CLR_MSK 0xfffffffe
556 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_RESET 0x0
558 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_GET(value) (((value) & 0x00000001) >> 0)
560 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_SET(value) (((value) << 0) & 0x00000001)
573 struct ALT_ECC_SDMMC_ERRINTENR_s
575 uint32_t SERRINTR : 1;
580 typedef volatile struct ALT_ECC_SDMMC_ERRINTENR_s ALT_ECC_SDMMC_ERRINTENR_t;
584 #define ALT_ECC_SDMMC_ERRINTENR_RESET 0x00000000
586 #define ALT_ECC_SDMMC_ERRINTENR_OFST 0x18
614 #define ALT_ECC_SDMMC_INTMOD_INTMOD_LSB 0
616 #define ALT_ECC_SDMMC_INTMOD_INTMOD_MSB 0
618 #define ALT_ECC_SDMMC_INTMOD_INTMOD_WIDTH 1
620 #define ALT_ECC_SDMMC_INTMOD_INTMOD_SET_MSK 0x00000001
622 #define ALT_ECC_SDMMC_INTMOD_INTMOD_CLR_MSK 0xfffffffe
624 #define ALT_ECC_SDMMC_INTMOD_INTMOD_RESET 0x0
626 #define ALT_ECC_SDMMC_INTMOD_INTMOD_GET(value) (((value) & 0x00000001) >> 0)
628 #define ALT_ECC_SDMMC_INTMOD_INTMOD_SET(value) (((value) << 0) & 0x00000001)
639 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_LSB 8
641 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_MSB 8
643 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_WIDTH 1
645 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_SET_MSK 0x00000100
647 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_CLR_MSK 0xfffffeff
649 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_RESET 0x0
651 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_GET(value) (((value) & 0x00000100) >> 8)
653 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_SET(value) (((value) << 8) & 0x00000100)
664 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_LSB 16
666 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_MSB 16
668 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_WIDTH 1
670 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_SET_MSK 0x00010000
672 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_CLR_MSK 0xfffeffff
674 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_RESET 0x0
676 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_GET(value) (((value) & 0x00010000) >> 16)
678 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_SET(value) (((value) << 16) & 0x00010000)
691 struct ALT_ECC_SDMMC_INTMOD_s
693 uint32_t INTMODE : 1;
695 uint32_t INTONOVF : 1;
697 uint32_t INTONCMP : 1;
702 typedef volatile struct ALT_ECC_SDMMC_INTMOD_s ALT_ECC_SDMMC_INTMOD_t;
706 #define ALT_ECC_SDMMC_INTMOD_RESET 0x00000000
708 #define ALT_ECC_SDMMC_INTMOD_OFST 0x1c
740 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_LSB 0
742 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_MSB 0
744 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_WIDTH 1
746 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_SET_MSK 0x00000001
748 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_CLR_MSK 0xfffffffe
750 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_RESET 0x0
752 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_GET(value) (((value) & 0x00000001) >> 0)
754 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_SET(value) (((value) << 0) & 0x00000001)
765 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_LSB 8
767 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_MSB 8
769 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_WIDTH 1
771 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_SET_MSK 0x00000100
773 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_CLR_MSK 0xfffffeff
775 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_RESET 0x0
777 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_GET(value) (((value) & 0x00000100) >> 8)
779 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_SET(value) (((value) << 8) & 0x00000100)
790 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_LSB 16
792 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_MSB 16
794 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_WIDTH 1
796 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_SET_MSK 0x00010000
798 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_CLR_MSK 0xfffeffff
800 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_RESET 0x0
802 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_GET(value) (((value) & 0x00010000) >> 16)
804 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_SET(value) (((value) << 16) & 0x00010000)
815 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_LSB 24
817 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_MSB 24
819 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_WIDTH 1
821 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_SET_MSK 0x01000000
823 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_CLR_MSK 0xfeffffff
825 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_RESET 0x0
827 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_GET(value) (((value) & 0x01000000) >> 24)
829 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_SET(value) (((value) << 24) & 0x01000000)
842 struct ALT_ECC_SDMMC_INTSTAT_s
844 uint32_t SERRPENA : 1;
846 uint32_t DERRPENA : 1;
848 uint32_t SERRPENB : 1;
850 uint32_t DERRPENB : 1;
855 typedef volatile struct ALT_ECC_SDMMC_INTSTAT_s ALT_ECC_SDMMC_INTSTAT_t;
859 #define ALT_ECC_SDMMC_INTSTAT_RESET 0x00000000
861 #define ALT_ECC_SDMMC_INTSTAT_OFST 0x20
891 #define ALT_ECC_SDMMC_INTTEST_TSERRA_LSB 0
893 #define ALT_ECC_SDMMC_INTTEST_TSERRA_MSB 0
895 #define ALT_ECC_SDMMC_INTTEST_TSERRA_WIDTH 1
897 #define ALT_ECC_SDMMC_INTTEST_TSERRA_SET_MSK 0x00000001
899 #define ALT_ECC_SDMMC_INTTEST_TSERRA_CLR_MSK 0xfffffffe
901 #define ALT_ECC_SDMMC_INTTEST_TSERRA_RESET 0x0
903 #define ALT_ECC_SDMMC_INTTEST_TSERRA_GET(value) (((value) & 0x00000001) >> 0)
905 #define ALT_ECC_SDMMC_INTTEST_TSERRA_SET(value) (((value) << 0) & 0x00000001)
916 #define ALT_ECC_SDMMC_INTTEST_TDERRA_LSB 8
918 #define ALT_ECC_SDMMC_INTTEST_TDERRA_MSB 8
920 #define ALT_ECC_SDMMC_INTTEST_TDERRA_WIDTH 1
922 #define ALT_ECC_SDMMC_INTTEST_TDERRA_SET_MSK 0x00000100
924 #define ALT_ECC_SDMMC_INTTEST_TDERRA_CLR_MSK 0xfffffeff
926 #define ALT_ECC_SDMMC_INTTEST_TDERRA_RESET 0x0
928 #define ALT_ECC_SDMMC_INTTEST_TDERRA_GET(value) (((value) & 0x00000100) >> 8)
930 #define ALT_ECC_SDMMC_INTTEST_TDERRA_SET(value) (((value) << 8) & 0x00000100)
941 #define ALT_ECC_SDMMC_INTTEST_TSERRB_LSB 16
943 #define ALT_ECC_SDMMC_INTTEST_TSERRB_MSB 16
945 #define ALT_ECC_SDMMC_INTTEST_TSERRB_WIDTH 1
947 #define ALT_ECC_SDMMC_INTTEST_TSERRB_SET_MSK 0x00010000
949 #define ALT_ECC_SDMMC_INTTEST_TSERRB_CLR_MSK 0xfffeffff
951 #define ALT_ECC_SDMMC_INTTEST_TSERRB_RESET 0x0
953 #define ALT_ECC_SDMMC_INTTEST_TSERRB_GET(value) (((value) & 0x00010000) >> 16)
955 #define ALT_ECC_SDMMC_INTTEST_TSERRB_SET(value) (((value) << 16) & 0x00010000)
966 #define ALT_ECC_SDMMC_INTTEST_TDERRB_LSB 24
968 #define ALT_ECC_SDMMC_INTTEST_TDERRB_MSB 24
970 #define ALT_ECC_SDMMC_INTTEST_TDERRB_WIDTH 1
972 #define ALT_ECC_SDMMC_INTTEST_TDERRB_SET_MSK 0x01000000
974 #define ALT_ECC_SDMMC_INTTEST_TDERRB_CLR_MSK 0xfeffffff
976 #define ALT_ECC_SDMMC_INTTEST_TDERRB_RESET 0x0
978 #define ALT_ECC_SDMMC_INTTEST_TDERRB_GET(value) (((value) & 0x01000000) >> 24)
980 #define ALT_ECC_SDMMC_INTTEST_TDERRB_SET(value) (((value) << 24) & 0x01000000)
993 struct ALT_ECC_SDMMC_INTTEST_s
1001 uint32_t TDERRB : 1;
1006 typedef volatile struct ALT_ECC_SDMMC_INTTEST_s ALT_ECC_SDMMC_INTTEST_t;
1010 #define ALT_ECC_SDMMC_INTTEST_RESET 0x00000000
1012 #define ALT_ECC_SDMMC_INTTEST_OFST 0x24
1037 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_LSB 0
1039 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_MSB 0
1041 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_WIDTH 1
1043 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_SET_MSK 0x00000001
1045 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_CLR_MSK 0xfffffffe
1047 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_RESET 0x0
1049 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_GET(value) (((value) & 0x00000001) >> 0)
1051 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_SET(value) (((value) << 0) & 0x00000001)
1062 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_LSB 1
1064 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_MSB 1
1066 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_WIDTH 1
1068 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_SET_MSK 0x00000002
1070 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_CLR_MSK 0xfffffffd
1072 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_RESET 0x0
1074 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_GET(value) (((value) & 0x00000002) >> 1)
1076 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_SET(value) (((value) << 1) & 0x00000002)
1078 #ifndef __ASSEMBLY__
1089 struct ALT_ECC_SDMMC_MODSTAT_s
1091 uint32_t CMPFLGA : 1;
1092 uint32_t CMPFLGB : 1;
1097 typedef volatile struct ALT_ECC_SDMMC_MODSTAT_s ALT_ECC_SDMMC_MODSTAT_t;
1101 #define ALT_ECC_SDMMC_MODSTAT_RESET 0x00000000
1103 #define ALT_ECC_SDMMC_MODSTAT_OFST 0x28
1128 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_LSB 0
1130 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_MSB 9
1132 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_WIDTH 10
1134 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_SET_MSK 0x000003ff
1136 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_CLR_MSK 0xfffffc00
1138 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_RESET 0x0
1140 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
1142 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_SET(value) (((value) << 0) & 0x000003ff)
1144 #ifndef __ASSEMBLY__
1155 struct ALT_ECC_SDMMC_DERRADDRA_s
1157 uint32_t Address : 10;
1162 typedef volatile struct ALT_ECC_SDMMC_DERRADDRA_s ALT_ECC_SDMMC_DERRADDRA_t;
1166 #define ALT_ECC_SDMMC_DERRADDRA_RESET 0x00000000
1168 #define ALT_ECC_SDMMC_DERRADDRA_OFST 0x2c
1193 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_LSB 0
1195 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_MSB 9
1197 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_WIDTH 10
1199 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_SET_MSK 0x000003ff
1201 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_CLR_MSK 0xfffffc00
1203 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_RESET 0x0
1205 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
1207 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_SET(value) (((value) << 0) & 0x000003ff)
1209 #ifndef __ASSEMBLY__
1220 struct ALT_ECC_SDMMC_SERRADDRA_s
1222 uint32_t Address : 10;
1227 typedef volatile struct ALT_ECC_SDMMC_SERRADDRA_s ALT_ECC_SDMMC_SERRADDRA_t;
1231 #define ALT_ECC_SDMMC_SERRADDRA_RESET 0x00000000
1233 #define ALT_ECC_SDMMC_SERRADDRA_OFST 0x30
1258 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_LSB 0
1260 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_MSB 9
1262 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_WIDTH 10
1264 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_SET_MSK 0x000003ff
1266 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_CLR_MSK 0xfffffc00
1268 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_RESET 0x0
1270 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
1272 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_SET(value) (((value) << 0) & 0x000003ff)
1274 #ifndef __ASSEMBLY__
1285 struct ALT_ECC_SDMMC_DERRADDRB_s
1287 uint32_t Address : 10;
1292 typedef volatile struct ALT_ECC_SDMMC_DERRADDRB_s ALT_ECC_SDMMC_DERRADDRB_t;
1296 #define ALT_ECC_SDMMC_DERRADDRB_RESET 0x00000000
1298 #define ALT_ECC_SDMMC_DERRADDRB_OFST 0x34
1323 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_LSB 0
1325 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_MSB 9
1327 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_WIDTH 10
1329 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_SET_MSK 0x000003ff
1331 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_CLR_MSK 0xfffffc00
1333 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_RESET 0x0
1335 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
1337 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_SET(value) (((value) << 0) & 0x000003ff)
1339 #ifndef __ASSEMBLY__
1350 struct ALT_ECC_SDMMC_SERRADDRB_s
1352 uint32_t Address : 10;
1357 typedef volatile struct ALT_ECC_SDMMC_SERRADDRB_s ALT_ECC_SDMMC_SERRADDRB_t;
1361 #define ALT_ECC_SDMMC_SERRADDRB_RESET 0x00000000
1363 #define ALT_ECC_SDMMC_SERRADDRB_OFST 0x38
1386 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_LSB 0
1388 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_MSB 31
1390 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_WIDTH 32
1392 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_SET_MSK 0xffffffff
1394 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_CLR_MSK 0x00000000
1396 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_RESET 0x0
1398 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_GET(value) (((value) & 0xffffffff) >> 0)
1400 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_SET(value) (((value) << 0) & 0xffffffff)
1402 #ifndef __ASSEMBLY__
1413 struct ALT_ECC_SDMMC_SERRCNTREG_s
1415 uint32_t SERRCNT : 32;
1419 typedef volatile struct ALT_ECC_SDMMC_SERRCNTREG_s ALT_ECC_SDMMC_SERRCNTREG_t;
1423 #define ALT_ECC_SDMMC_SERRCNTREG_RESET 0x00000000
1425 #define ALT_ECC_SDMMC_SERRCNTREG_OFST 0x3c
1450 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_LSB 0
1452 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_MSB 9
1454 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_WIDTH 10
1456 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_SET_MSK 0x000003ff
1458 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_CLR_MSK 0xfffffc00
1460 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_RESET 0x0
1462 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_GET(value) (((value) & 0x000003ff) >> 0)
1464 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_SET(value) (((value) << 0) & 0x000003ff)
1466 #ifndef __ASSEMBLY__
1477 struct ALT_ECC_SDMMC_ADDRBUS_s
1479 uint32_t ECC_AddrBUS : 10;
1484 typedef volatile struct ALT_ECC_SDMMC_ADDRBUS_s ALT_ECC_SDMMC_ADDRBUS_t;
1488 #define ALT_ECC_SDMMC_ADDRBUS_RESET 0x00000000
1490 #define ALT_ECC_SDMMC_ADDRBUS_OFST 0x40
1492 #define ALT_ECC_SDMMC_ADDRBUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_ADDRBUS_OFST))
1515 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_LSB 0
1517 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_MSB 31
1519 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_WIDTH 32
1521 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1523 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1525 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_RESET 0x0
1527 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1529 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1531 #ifndef __ASSEMBLY__
1542 struct ALT_ECC_SDMMC_RDATA0BUS_s
1544 uint32_t ECC_RDataBUS : 32;
1548 typedef volatile struct ALT_ECC_SDMMC_RDATA0BUS_s ALT_ECC_SDMMC_RDATA0BUS_t;
1552 #define ALT_ECC_SDMMC_RDATA0BUS_RESET 0x00000000
1554 #define ALT_ECC_SDMMC_RDATA0BUS_OFST 0x44
1556 #define ALT_ECC_SDMMC_RDATA0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_RDATA0BUS_OFST))
1579 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_LSB 0
1581 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_MSB 31
1583 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_WIDTH 32
1585 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1587 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1589 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_RESET 0x0
1591 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1593 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1595 #ifndef __ASSEMBLY__
1606 struct ALT_ECC_SDMMC_RDATA1BUS_s
1608 uint32_t ECC_RDataBUS : 32;
1612 typedef volatile struct ALT_ECC_SDMMC_RDATA1BUS_s ALT_ECC_SDMMC_RDATA1BUS_t;
1616 #define ALT_ECC_SDMMC_RDATA1BUS_RESET 0x00000000
1618 #define ALT_ECC_SDMMC_RDATA1BUS_OFST 0x48
1620 #define ALT_ECC_SDMMC_RDATA1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_RDATA1BUS_OFST))
1643 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_LSB 0
1645 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_MSB 31
1647 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_WIDTH 32
1649 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1651 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1653 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_RESET 0x0
1655 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1657 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1659 #ifndef __ASSEMBLY__
1670 struct ALT_ECC_SDMMC_RDATA2BUS_s
1672 uint32_t ECC_RDataBUS : 32;
1676 typedef volatile struct ALT_ECC_SDMMC_RDATA2BUS_s ALT_ECC_SDMMC_RDATA2BUS_t;
1680 #define ALT_ECC_SDMMC_RDATA2BUS_RESET 0x00000000
1682 #define ALT_ECC_SDMMC_RDATA2BUS_OFST 0x4c
1684 #define ALT_ECC_SDMMC_RDATA2BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_RDATA2BUS_OFST))
1707 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_LSB 0
1709 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_MSB 31
1711 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_WIDTH 32
1713 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1715 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1717 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_RESET 0x0
1719 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1721 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1723 #ifndef __ASSEMBLY__
1734 struct ALT_ECC_SDMMC_RDATA3BUS_s
1736 uint32_t ECC_RDataBUS : 32;
1740 typedef volatile struct ALT_ECC_SDMMC_RDATA3BUS_s ALT_ECC_SDMMC_RDATA3BUS_t;
1744 #define ALT_ECC_SDMMC_RDATA3BUS_RESET 0x00000000
1746 #define ALT_ECC_SDMMC_RDATA3BUS_OFST 0x50
1748 #define ALT_ECC_SDMMC_RDATA3BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_RDATA3BUS_OFST))
1771 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_LSB 0
1773 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_MSB 31
1775 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_WIDTH 32
1777 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1779 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1781 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_RESET 0x0
1783 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1785 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1787 #ifndef __ASSEMBLY__
1798 struct ALT_ECC_SDMMC_WDATA0BUS_s
1800 uint32_t ECC_WDataBUS : 32;
1804 typedef volatile struct ALT_ECC_SDMMC_WDATA0BUS_s ALT_ECC_SDMMC_WDATA0BUS_t;
1808 #define ALT_ECC_SDMMC_WDATA0BUS_RESET 0x00000000
1810 #define ALT_ECC_SDMMC_WDATA0BUS_OFST 0x54
1812 #define ALT_ECC_SDMMC_WDATA0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_WDATA0BUS_OFST))
1835 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_LSB 0
1837 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_MSB 31
1839 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_WIDTH 32
1841 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1843 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1845 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_RESET 0x0
1847 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1849 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1851 #ifndef __ASSEMBLY__
1862 struct ALT_ECC_SDMMC_WDATA1BUS_s
1864 uint32_t ECC_WDataBUS : 32;
1868 typedef volatile struct ALT_ECC_SDMMC_WDATA1BUS_s ALT_ECC_SDMMC_WDATA1BUS_t;
1872 #define ALT_ECC_SDMMC_WDATA1BUS_RESET 0x00000000
1874 #define ALT_ECC_SDMMC_WDATA1BUS_OFST 0x58
1876 #define ALT_ECC_SDMMC_WDATA1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_WDATA1BUS_OFST))
1899 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_LSB 0
1901 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_MSB 31
1903 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_WIDTH 32
1905 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1907 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1909 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_RESET 0x0
1911 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1913 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1915 #ifndef __ASSEMBLY__
1926 struct ALT_ECC_SDMMC_WDATA2BUS_s
1928 uint32_t ECC_WDataBUS : 32;
1932 typedef volatile struct ALT_ECC_SDMMC_WDATA2BUS_s ALT_ECC_SDMMC_WDATA2BUS_t;
1936 #define ALT_ECC_SDMMC_WDATA2BUS_RESET 0x00000000
1938 #define ALT_ECC_SDMMC_WDATA2BUS_OFST 0x5c
1940 #define ALT_ECC_SDMMC_WDATA2BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_WDATA2BUS_OFST))
1963 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_LSB 0
1965 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_MSB 31
1967 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_WIDTH 32
1969 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1971 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1973 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_RESET 0x0
1975 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1977 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1979 #ifndef __ASSEMBLY__
1990 struct ALT_ECC_SDMMC_WDATA3BUS_s
1992 uint32_t ECC_WDataBUS : 32;
1996 typedef volatile struct ALT_ECC_SDMMC_WDATA3BUS_s ALT_ECC_SDMMC_WDATA3BUS_t;
2000 #define ALT_ECC_SDMMC_WDATA3BUS_RESET 0x00000000
2002 #define ALT_ECC_SDMMC_WDATA3BUS_OFST 0x60
2004 #define ALT_ECC_SDMMC_WDATA3BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_WDATA3BUS_OFST))
2035 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_LSB 0
2037 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_MSB 6
2039 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_WIDTH 7
2041 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET_MSK 0x0000007f
2043 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_CLR_MSK 0xffffff80
2045 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_RESET 0x0
2047 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_GET(value) (((value) & 0x0000007f) >> 0)
2049 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET(value) (((value) << 0) & 0x0000007f)
2060 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_LSB 8
2062 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_MSB 14
2064 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_WIDTH 7
2066 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET_MSK 0x00007f00
2068 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_CLR_MSK 0xffff80ff
2070 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_RESET 0x0
2072 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_GET(value) (((value) & 0x00007f00) >> 8)
2074 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET(value) (((value) << 8) & 0x00007f00)
2085 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_LSB 16
2087 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_MSB 22
2089 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_WIDTH 7
2091 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET_MSK 0x007f0000
2093 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_CLR_MSK 0xff80ffff
2095 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_RESET 0x0
2097 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_GET(value) (((value) & 0x007f0000) >> 16)
2099 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET(value) (((value) << 16) & 0x007f0000)
2110 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_LSB 24
2112 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_MSB 30
2114 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_WIDTH 7
2116 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET_MSK 0x7f000000
2118 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_CLR_MSK 0x80ffffff
2120 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_RESET 0x0
2122 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_GET(value) (((value) & 0x7f000000) >> 24)
2124 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET(value) (((value) << 24) & 0x7f000000)
2126 #ifndef __ASSEMBLY__
2137 struct ALT_ECC_SDMMC_RDATAECC0BUS_s
2139 uint32_t ECC_RDataecc0BUS : 7;
2141 uint32_t ECC_RDataecc1BUS : 7;
2143 uint32_t ECC_RDataecc2BUS : 7;
2145 uint32_t ECC_RDataecc3BUS : 7;
2150 typedef volatile struct ALT_ECC_SDMMC_RDATAECC0BUS_s ALT_ECC_SDMMC_RDATAECC0BUS_t;
2154 #define ALT_ECC_SDMMC_RDATAECC0BUS_RESET 0x00000000
2156 #define ALT_ECC_SDMMC_RDATAECC0BUS_OFST 0x64
2158 #define ALT_ECC_SDMMC_RDATAECC0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_RDATAECC0BUS_OFST))
2189 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_LSB 0
2191 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_MSB 6
2193 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_WIDTH 7
2195 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET_MSK 0x0000007f
2197 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_CLR_MSK 0xffffff80
2199 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_RESET 0x0
2201 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_GET(value) (((value) & 0x0000007f) >> 0)
2203 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET(value) (((value) << 0) & 0x0000007f)
2214 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_LSB 8
2216 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_MSB 14
2218 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_WIDTH 7
2220 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET_MSK 0x00007f00
2222 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_CLR_MSK 0xffff80ff
2224 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_RESET 0x0
2226 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_GET(value) (((value) & 0x00007f00) >> 8)
2228 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET(value) (((value) << 8) & 0x00007f00)
2239 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_LSB 16
2241 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_MSB 22
2243 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_WIDTH 7
2245 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET_MSK 0x007f0000
2247 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_CLR_MSK 0xff80ffff
2249 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_RESET 0x0
2251 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_GET(value) (((value) & 0x007f0000) >> 16)
2253 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET(value) (((value) << 16) & 0x007f0000)
2264 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_LSB 24
2266 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_MSB 30
2268 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_WIDTH 7
2270 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET_MSK 0x7f000000
2272 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_CLR_MSK 0x80ffffff
2274 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_RESET 0x0
2276 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_GET(value) (((value) & 0x7f000000) >> 24)
2278 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET(value) (((value) << 24) & 0x7f000000)
2280 #ifndef __ASSEMBLY__
2291 struct ALT_ECC_SDMMC_RDATAECC1BUS_s
2293 uint32_t ECC_RDataecc4BUS : 7;
2295 uint32_t ECC_RDataecc5BUS : 7;
2297 uint32_t ECC_RDataecc6BUS : 7;
2299 uint32_t ECC_RDataecc7BUS : 7;
2304 typedef volatile struct ALT_ECC_SDMMC_RDATAECC1BUS_s ALT_ECC_SDMMC_RDATAECC1BUS_t;
2308 #define ALT_ECC_SDMMC_RDATAECC1BUS_RESET 0x00000000
2310 #define ALT_ECC_SDMMC_RDATAECC1BUS_OFST 0x68
2312 #define ALT_ECC_SDMMC_RDATAECC1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_RDATAECC1BUS_OFST))
2343 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_LSB 0
2345 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_MSB 6
2347 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_WIDTH 7
2349 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET_MSK 0x0000007f
2351 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_CLR_MSK 0xffffff80
2353 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_RESET 0x0
2355 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_GET(value) (((value) & 0x0000007f) >> 0)
2357 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET(value) (((value) << 0) & 0x0000007f)
2368 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_LSB 8
2370 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_MSB 14
2372 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_WIDTH 7
2374 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET_MSK 0x00007f00
2376 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_CLR_MSK 0xffff80ff
2378 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_RESET 0x0
2380 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_GET(value) (((value) & 0x00007f00) >> 8)
2382 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET(value) (((value) << 8) & 0x00007f00)
2393 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_LSB 16
2395 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_MSB 22
2397 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_WIDTH 7
2399 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET_MSK 0x007f0000
2401 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_CLR_MSK 0xff80ffff
2403 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_RESET 0x0
2405 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_GET(value) (((value) & 0x007f0000) >> 16)
2407 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET(value) (((value) << 16) & 0x007f0000)
2418 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_LSB 24
2420 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_MSB 30
2422 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_WIDTH 7
2424 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET_MSK 0x7f000000
2426 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_CLR_MSK 0x80ffffff
2428 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_RESET 0x0
2430 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_GET(value) (((value) & 0x7f000000) >> 24)
2432 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET(value) (((value) << 24) & 0x7f000000)
2434 #ifndef __ASSEMBLY__
2445 struct ALT_ECC_SDMMC_WDATAECC0BUS_s
2447 uint32_t ECC_WDataecc0BUS : 7;
2449 uint32_t ECC_WDataecc1BUS : 7;
2451 uint32_t ECC_WDataecc2BUS : 7;
2453 uint32_t ECC_WDataecc3BUS : 7;
2458 typedef volatile struct ALT_ECC_SDMMC_WDATAECC0BUS_s ALT_ECC_SDMMC_WDATAECC0BUS_t;
2462 #define ALT_ECC_SDMMC_WDATAECC0BUS_RESET 0x00000000
2464 #define ALT_ECC_SDMMC_WDATAECC0BUS_OFST 0x6c
2466 #define ALT_ECC_SDMMC_WDATAECC0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_WDATAECC0BUS_OFST))
2497 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_LSB 0
2499 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_MSB 6
2501 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_WIDTH 7
2503 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET_MSK 0x0000007f
2505 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_CLR_MSK 0xffffff80
2507 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_RESET 0x0
2509 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_GET(value) (((value) & 0x0000007f) >> 0)
2511 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET(value) (((value) << 0) & 0x0000007f)
2522 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_LSB 8
2524 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_MSB 14
2526 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_WIDTH 7
2528 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET_MSK 0x00007f00
2530 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_CLR_MSK 0xffff80ff
2532 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_RESET 0x0
2534 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_GET(value) (((value) & 0x00007f00) >> 8)
2536 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET(value) (((value) << 8) & 0x00007f00)
2547 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_LSB 16
2549 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_MSB 22
2551 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_WIDTH 7
2553 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET_MSK 0x007f0000
2555 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_CLR_MSK 0xff80ffff
2557 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_RESET 0x0
2559 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_GET(value) (((value) & 0x007f0000) >> 16)
2561 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET(value) (((value) << 16) & 0x007f0000)
2572 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_LSB 24
2574 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_MSB 30
2576 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_WIDTH 7
2578 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET_MSK 0x7f000000
2580 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_CLR_MSK 0x80ffffff
2582 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_RESET 0x0
2584 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_GET(value) (((value) & 0x7f000000) >> 24)
2586 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET(value) (((value) << 24) & 0x7f000000)
2588 #ifndef __ASSEMBLY__
2599 struct ALT_ECC_SDMMC_WDATAECC1BUS_s
2601 uint32_t ECC_WDataecc4BUS : 7;
2603 uint32_t ECC_WDataecc5BUS : 7;
2605 uint32_t ECC_WDataecc6BUS : 7;
2607 uint32_t ECC_WDataecc7BUS : 7;
2612 typedef volatile struct ALT_ECC_SDMMC_WDATAECC1BUS_s ALT_ECC_SDMMC_WDATAECC1BUS_t;
2616 #define ALT_ECC_SDMMC_WDATAECC1BUS_RESET 0x00000000
2618 #define ALT_ECC_SDMMC_WDATAECC1BUS_OFST 0x70
2620 #define ALT_ECC_SDMMC_WDATAECC1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_WDATAECC1BUS_OFST))
2644 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_LSB 0
2646 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_MSB 0
2648 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_WIDTH 1
2650 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_SET_MSK 0x00000001
2652 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_CLR_MSK 0xfffffffe
2654 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_RESET 0x0
2656 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_GET(value) (((value) & 0x00000001) >> 0)
2658 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_SET(value) (((value) << 0) & 0x00000001)
2660 #ifndef __ASSEMBLY__
2671 struct ALT_ECC_SDMMC_DBYTECTL_s
2678 typedef volatile struct ALT_ECC_SDMMC_DBYTECTL_s ALT_ECC_SDMMC_DBYTECTL_t;
2682 #define ALT_ECC_SDMMC_DBYTECTL_RESET 0x00000000
2684 #define ALT_ECC_SDMMC_DBYTECTL_OFST 0x74
2686 #define ALT_ECC_SDMMC_DBYTECTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_DBYTECTL_OFST))
2718 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_LSB 0
2720 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_MSB 0
2722 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_WIDTH 1
2724 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_SET_MSK 0x00000001
2726 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_CLR_MSK 0xfffffffe
2728 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_RESET 0x0
2730 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_GET(value) (((value) & 0x00000001) >> 0)
2732 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_SET(value) (((value) << 0) & 0x00000001)
2743 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_LSB 1
2745 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_MSB 1
2747 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_WIDTH 1
2749 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_SET_MSK 0x00000002
2751 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_CLR_MSK 0xfffffffd
2753 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_RESET 0x0
2755 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_GET(value) (((value) & 0x00000002) >> 1)
2757 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_SET(value) (((value) << 1) & 0x00000002)
2768 #define ALT_ECC_SDMMC_ACCCTL_RDWR_LSB 8
2770 #define ALT_ECC_SDMMC_ACCCTL_RDWR_MSB 8
2772 #define ALT_ECC_SDMMC_ACCCTL_RDWR_WIDTH 1
2774 #define ALT_ECC_SDMMC_ACCCTL_RDWR_SET_MSK 0x00000100
2776 #define ALT_ECC_SDMMC_ACCCTL_RDWR_CLR_MSK 0xfffffeff
2778 #define ALT_ECC_SDMMC_ACCCTL_RDWR_RESET 0x0
2780 #define ALT_ECC_SDMMC_ACCCTL_RDWR_GET(value) (((value) & 0x00000100) >> 8)
2782 #define ALT_ECC_SDMMC_ACCCTL_RDWR_SET(value) (((value) << 8) & 0x00000100)
2784 #ifndef __ASSEMBLY__
2795 struct ALT_ECC_SDMMC_ACCCTL_s
2797 uint32_t DATAOVR : 1;
2798 uint32_t ECCOVR : 1;
2805 typedef volatile struct ALT_ECC_SDMMC_ACCCTL_s ALT_ECC_SDMMC_ACCCTL_t;
2809 #define ALT_ECC_SDMMC_ACCCTL_RESET 0x00000000
2811 #define ALT_ECC_SDMMC_ACCCTL_OFST 0x78
2813 #define ALT_ECC_SDMMC_ACCCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_ACCCTL_OFST))
2839 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_LSB 0
2841 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_MSB 0
2843 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_WIDTH 1
2845 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_SET_MSK 0x00000001
2847 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_CLR_MSK 0xfffffffe
2849 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_RESET 0x0
2851 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_GET(value) (((value) & 0x00000001) >> 0)
2853 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_SET(value) (((value) << 0) & 0x00000001)
2864 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_LSB 16
2866 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_MSB 16
2868 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_WIDTH 1
2870 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_SET_MSK 0x00010000
2872 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_CLR_MSK 0xfffeffff
2874 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_RESET 0x0
2876 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_GET(value) (((value) & 0x00010000) >> 16)
2878 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_SET(value) (((value) << 16) & 0x00010000)
2880 #ifndef __ASSEMBLY__
2891 struct ALT_ECC_SDMMC_STARTACC_s
2893 uint32_t ENBUSB : 1;
2895 uint32_t ENBUSA : 1;
2900 typedef volatile struct ALT_ECC_SDMMC_STARTACC_s ALT_ECC_SDMMC_STARTACC_t;
2904 #define ALT_ECC_SDMMC_STARTACC_RESET 0x00000000
2906 #define ALT_ECC_SDMMC_STARTACC_OFST 0x7c
2908 #define ALT_ECC_SDMMC_STARTACC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_STARTACC_OFST))
2932 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_LSB 0
2934 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_MSB 0
2936 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_WIDTH 1
2938 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_SET_MSK 0x00000001
2940 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_CLR_MSK 0xfffffffe
2942 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_RESET 0x0
2944 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_GET(value) (((value) & 0x00000001) >> 0)
2946 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_SET(value) (((value) << 0) & 0x00000001)
2948 #ifndef __ASSEMBLY__
2959 struct ALT_ECC_SDMMC_WDCTL_s
2961 uint32_t WDEN_RAM : 1;
2966 typedef volatile struct ALT_ECC_SDMMC_WDCTL_s ALT_ECC_SDMMC_WDCTL_t;
2970 #define ALT_ECC_SDMMC_WDCTL_RESET 0x00000000
2972 #define ALT_ECC_SDMMC_WDCTL_OFST 0x80
2974 #define ALT_ECC_SDMMC_WDCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_WDCTL_OFST))
3003 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_LSB 0
3005 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_MSB 9
3007 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_WIDTH 10
3009 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_SET_MSK 0x000003ff
3011 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_CLR_MSK 0xfffffc00
3013 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_RESET 0x0
3015 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
3017 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_SET(value) (((value) << 0) & 0x000003ff)
3029 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_LSB 31
3031 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_MSB 31
3033 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_WIDTH 1
3035 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_SET_MSK 0x80000000
3037 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_CLR_MSK 0x7fffffff
3039 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_RESET 0x0
3041 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_GET(value) (((value) & 0x80000000) >> 31)
3043 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_SET(value) (((value) << 31) & 0x80000000)
3045 #ifndef __ASSEMBLY__
3056 struct ALT_ECC_SDMMC_SERRLKUPA0_s
3058 const uint32_t Address : 10;
3064 typedef volatile struct ALT_ECC_SDMMC_SERRLKUPA0_s ALT_ECC_SDMMC_SERRLKUPA0_t;
3068 #define ALT_ECC_SDMMC_SERRLKUPA0_RESET 0x00000000
3070 #define ALT_ECC_SDMMC_SERRLKUPA0_OFST 0x90
3099 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_LSB 0
3101 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_MSB 9
3103 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_WIDTH 10
3105 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_SET_MSK 0x000003ff
3107 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_CLR_MSK 0xfffffc00
3109 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_RESET 0x0
3111 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
3113 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_SET(value) (((value) << 0) & 0x000003ff)
3125 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_LSB 31
3127 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_MSB 31
3129 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_WIDTH 1
3131 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_SET_MSK 0x80000000
3133 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_CLR_MSK 0x7fffffff
3135 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_RESET 0x0
3137 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_GET(value) (((value) & 0x80000000) >> 31)
3139 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_SET(value) (((value) << 31) & 0x80000000)
3141 #ifndef __ASSEMBLY__
3152 struct ALT_ECC_SDMMC_SERRLKUPB0_s
3154 const uint32_t Address : 10;
3160 typedef volatile struct ALT_ECC_SDMMC_SERRLKUPB0_s ALT_ECC_SDMMC_SERRLKUPB0_t;
3164 #define ALT_ECC_SDMMC_SERRLKUPB0_RESET 0x00000000
3166 #define ALT_ECC_SDMMC_SERRLKUPB0_OFST 0xd0
3168 #ifndef __ASSEMBLY__
3179 struct ALT_ECC_SDMMC_s
3181 ALT_ECC_SDMMC_IP_REV_ID_t IP_REV_ID;
3182 volatile uint32_t _pad_0x4_0x7;
3183 ALT_ECC_SDMMC_CTL_t CTRL;
3184 ALT_ECC_SDMMC_INITSTAT_t INITSTAT;
3185 ALT_ECC_SDMMC_ERRINTEN_t ERRINTEN;
3186 ALT_ECC_SDMMC_ERRINTENS_t ERRINTENS;
3187 ALT_ECC_SDMMC_ERRINTENR_t ERRINTENR;
3188 ALT_ECC_SDMMC_INTMOD_t INTMODE;
3189 ALT_ECC_SDMMC_INTSTAT_t INTSTAT;
3190 ALT_ECC_SDMMC_INTTEST_t INTTEST;
3191 ALT_ECC_SDMMC_MODSTAT_t MODSTAT;
3192 ALT_ECC_SDMMC_DERRADDRA_t DERRADDRA;
3193 ALT_ECC_SDMMC_SERRADDRA_t SERRADDRA;
3194 ALT_ECC_SDMMC_DERRADDRB_t DERRADDRB;
3195 ALT_ECC_SDMMC_SERRADDRB_t SERRADDRB;
3196 ALT_ECC_SDMMC_SERRCNTREG_t SERRCNTREG;
3197 ALT_ECC_SDMMC_ADDRBUS_t ECC_Addrbus;
3198 ALT_ECC_SDMMC_RDATA0BUS_t ECC_RData0bus;
3199 ALT_ECC_SDMMC_RDATA1BUS_t ECC_RData1bus;
3200 ALT_ECC_SDMMC_RDATA2BUS_t ECC_RData2bus;
3201 ALT_ECC_SDMMC_RDATA3BUS_t ECC_RData3bus;
3202 ALT_ECC_SDMMC_WDATA0BUS_t ECC_WData0bus;
3203 ALT_ECC_SDMMC_WDATA1BUS_t ECC_WData1bus;
3204 ALT_ECC_SDMMC_WDATA2BUS_t ECC_WData2bus;
3205 ALT_ECC_SDMMC_WDATA3BUS_t ECC_WData3bus;
3206 ALT_ECC_SDMMC_RDATAECC0BUS_t ECC_RDataecc0bus;
3207 ALT_ECC_SDMMC_RDATAECC1BUS_t ECC_RDataecc1bus;
3208 ALT_ECC_SDMMC_WDATAECC0BUS_t ECC_WDataecc0bus;
3209 ALT_ECC_SDMMC_WDATAECC1BUS_t ECC_WDataecc1bus;
3210 ALT_ECC_SDMMC_DBYTECTL_t ECC_dbytectrl;
3211 ALT_ECC_SDMMC_ACCCTL_t ECC_accctrl;
3212 ALT_ECC_SDMMC_STARTACC_t ECC_startacc;
3213 ALT_ECC_SDMMC_WDCTL_t ECC_wdctrl;
3214 volatile uint32_t _pad_0x84_0x8f[3];
3215 ALT_ECC_SDMMC_SERRLKUPA0_t SERRLKUPA0;
3216 volatile uint32_t _pad_0x94_0xcf[15];
3217 ALT_ECC_SDMMC_SERRLKUPB0_t SERRLKUPB0;
3218 volatile uint32_t _pad_0xd4_0x400[203];
3222 typedef volatile struct ALT_ECC_SDMMC_s ALT_ECC_SDMMC_t;
3224 struct ALT_ECC_SDMMC_raw_s
3226 volatile uint32_t IP_REV_ID;
3227 uint32_t _pad_0x4_0x7;
3228 volatile uint32_t CTRL;
3229 volatile uint32_t INITSTAT;
3230 volatile uint32_t ERRINTEN;
3231 volatile uint32_t ERRINTENS;
3232 volatile uint32_t ERRINTENR;
3233 volatile uint32_t INTMODE;
3234 volatile uint32_t INTSTAT;
3235 volatile uint32_t INTTEST;
3236 volatile uint32_t MODSTAT;
3237 volatile uint32_t DERRADDRA;
3238 volatile uint32_t SERRADDRA;
3239 volatile uint32_t DERRADDRB;
3240 volatile uint32_t SERRADDRB;
3241 volatile uint32_t SERRCNTREG;
3242 volatile uint32_t ECC_Addrbus;
3243 volatile uint32_t ECC_RData0bus;
3244 volatile uint32_t ECC_RData1bus;
3245 volatile uint32_t ECC_RData2bus;
3246 volatile uint32_t ECC_RData3bus;
3247 volatile uint32_t ECC_WData0bus;
3248 volatile uint32_t ECC_WData1bus;
3249 volatile uint32_t ECC_WData2bus;
3250 volatile uint32_t ECC_WData3bus;
3251 volatile uint32_t ECC_RDataecc0bus;
3252 volatile uint32_t ECC_RDataecc1bus;
3253 volatile uint32_t ECC_WDataecc0bus;
3254 volatile uint32_t ECC_WDataecc1bus;
3255 volatile uint32_t ECC_dbytectrl;
3256 volatile uint32_t ECC_accctrl;
3257 volatile uint32_t ECC_startacc;
3258 volatile uint32_t ECC_wdctrl;
3259 uint32_t _pad_0x84_0x8f[3];
3260 volatile uint32_t SERRLKUPA0;
3261 uint32_t _pad_0x94_0xcf[15];
3262 volatile uint32_t SERRLKUPB0;
3263 uint32_t _pad_0xd4_0x400[203];
3267 typedef volatile struct ALT_ECC_SDMMC_raw_s ALT_ECC_SDMMC_raw_t;