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alt_noc_ccu_l4_link_rate_adptr.h
1 /***********************************************************************************
2 * *
3 * Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
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31 ***********************************************************************************/
32 
33 /* Altera - ALT_NOC_CCU_L4_LINK_RATE_ADPTR */
34 
35 #ifndef __ALT_SOCAL_NOC_CCU_L4_LINK_RATE_ADPTR_H__
36 #define __ALT_SOCAL_NOC_CCU_L4_LINK_RATE_ADPTR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : NOC_CCU_L4_LINK_RATE_ADPTR
50  *
51  */
52 /*
53  * Register : l4_linkResp_main_RateAdapter_Id_CoreId
54  *
55  * Register Layout
56  *
57  * Bits | Access | Reset | Description
58  * :-------|:-------|:---------|:-----------------------------------------------------------------------------------
59  * [7:0] | R | 0x1 | ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORETYPEID
60  * [31:8] | R | 0x955e1a | ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORECHECKSUM
61  *
62  */
63 /*
64  * Field : CORETYPEID
65  *
66  * Field identifying the type of IP.
67  *
68  * Field Access Macros:
69  *
70  */
71 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORETYPEID register field. */
72 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORETYPEID_LSB 0
73 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORETYPEID register field. */
74 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORETYPEID_MSB 7
75 /* The width in bits of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORETYPEID register field. */
76 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORETYPEID_WIDTH 8
77 /* The mask used to set the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORETYPEID register field value. */
78 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
79 /* The mask used to clear the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORETYPEID register field value. */
80 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
81 /* The reset value of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORETYPEID register field. */
82 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORETYPEID_RESET 0x1
83 /* Extracts the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORETYPEID field value from a register. */
84 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
85 /* Produces a ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORETYPEID register field value suitable for setting the register. */
86 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
87 
88 /*
89  * Field : CORECHECKSUM
90  *
91  * Field containing a checksum of the parameters of the IP.
92  *
93  * Field Access Macros:
94  *
95  */
96 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORECHECKSUM register field. */
97 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORECHECKSUM_LSB 8
98 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORECHECKSUM register field. */
99 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORECHECKSUM_MSB 31
100 /* The width in bits of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORECHECKSUM register field. */
101 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORECHECKSUM_WIDTH 24
102 /* The mask used to set the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORECHECKSUM register field value. */
103 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
104 /* The mask used to clear the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORECHECKSUM register field value. */
105 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
106 /* The reset value of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORECHECKSUM register field. */
107 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORECHECKSUM_RESET 0x955e1a
108 /* Extracts the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORECHECKSUM field value from a register. */
109 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
110 /* Produces a ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORECHECKSUM register field value suitable for setting the register. */
111 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
112 
113 #ifndef __ASSEMBLY__
114 /*
115  * WARNING: The C register and register group struct declarations are provided for
116  * convenience and illustrative purposes. They should, however, be used with
117  * caution as the C language standard provides no guarantees about the alignment or
118  * atomicity of device memory accesses. The recommended practice for coding device
119  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
120  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
121  * alt_write_dword() functions for 64 bit registers.
122  *
123  * The struct declaration for register ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID.
124  */
125 struct ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_s
126 {
127  const volatile uint32_t CORETYPEID : 8; /* ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORETYPEID */
128  const volatile uint32_t CORECHECKSUM : 24; /* ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_CORECHECKSUM */
129 };
130 
131 /* The typedef declaration for register ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID. */
132 typedef struct ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_s ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_t;
133 #endif /* __ASSEMBLY__ */
134 
135 /* The reset value of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID register. */
136 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_RESET 0x955e1a01
137 /* The byte offset of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID register from the beginning of the component. */
138 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_OFST 0x0
139 
140 /*
141  * Register : l4_linkResp_main_RateAdapter_Id_RevisionId
142  *
143  * Register Layout
144  *
145  * Bits | Access | Reset | Description
146  * :-------|:-------|:------|:------------------------------------------------------------------------------------
147  * [7:0] | R | 0x0 | ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_USERID
148  * [31:8] | R | 0x148 | ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_FLEXNOCID
149  *
150  */
151 /*
152  * Field : USERID
153  *
154  * Field containing a user defined value, not used anywhere inside the IP itself.
155  *
156  * Field Access Macros:
157  *
158  */
159 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_USERID register field. */
160 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_USERID_LSB 0
161 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_USERID register field. */
162 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_USERID_MSB 7
163 /* The width in bits of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_USERID register field. */
164 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_USERID_WIDTH 8
165 /* The mask used to set the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_USERID register field value. */
166 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_USERID_SET_MSK 0x000000ff
167 /* The mask used to clear the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_USERID register field value. */
168 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
169 /* The reset value of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_USERID register field. */
170 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_USERID_RESET 0x0
171 /* Extracts the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_USERID field value from a register. */
172 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
173 /* Produces a ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_USERID register field value suitable for setting the register. */
174 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
175 
176 /*
177  * Field : FLEXNOCID
178  *
179  * Field containing the build revision of the software used to generate the IP HDL
180  * code.
181  *
182  * Field Access Macros:
183  *
184  */
185 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_FLEXNOCID register field. */
186 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_FLEXNOCID_LSB 8
187 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_FLEXNOCID register field. */
188 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_FLEXNOCID_MSB 31
189 /* The width in bits of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_FLEXNOCID register field. */
190 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_FLEXNOCID_WIDTH 24
191 /* The mask used to set the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_FLEXNOCID register field value. */
192 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
193 /* The mask used to clear the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_FLEXNOCID register field value. */
194 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
195 /* The reset value of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_FLEXNOCID register field. */
196 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_FLEXNOCID_RESET 0x148
197 /* Extracts the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_FLEXNOCID field value from a register. */
198 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
199 /* Produces a ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_FLEXNOCID register field value suitable for setting the register. */
200 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
201 
202 #ifndef __ASSEMBLY__
203 /*
204  * WARNING: The C register and register group struct declarations are provided for
205  * convenience and illustrative purposes. They should, however, be used with
206  * caution as the C language standard provides no guarantees about the alignment or
207  * atomicity of device memory accesses. The recommended practice for coding device
208  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
209  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
210  * alt_write_dword() functions for 64 bit registers.
211  *
212  * The struct declaration for register ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID.
213  */
214 struct ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_s
215 {
216  const volatile uint32_t USERID : 8; /* ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_USERID */
217  const volatile uint32_t FLEXNOCID : 24; /* ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_FLEXNOCID */
218 };
219 
220 /* The typedef declaration for register ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID. */
221 typedef struct ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_s ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_t;
222 #endif /* __ASSEMBLY__ */
223 
224 /* The reset value of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID register. */
225 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_RESET 0x00014800
226 /* The byte offset of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID register from the beginning of the component. */
227 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_OFST 0x4
228 
229 /*
230  * Register : l4_linkResp_main_RateAdapter_Rate
231  *
232  * Register Layout
233  *
234  * Bits | Access | Reset | Description
235  * :--------|:-------|:--------|:----------------------------------------------------------------------
236  * [9:0] | RW | 0x0 | ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_RATE
237  * [31:10] | ??? | Unknown | *UNDEFINED*
238  *
239  */
240 /*
241  * Field : RATE
242  *
243  * The ratio of outgoing to incoming throughput. This value determines what portion
244  * of a received packet will be stored before its head is transmitted. An optimal
245  * setting avoids transmitting bubbles, while adding no delay to packets. The ratio
246  * is expressed as 256 / (ratio - 1). For example, a 3:1 ratio of outgoing to
247  * incoming throughput would be indicated by value 0x06E. Note that throughput is
248  * the product of clock frequency x data bus width. A value of 0x000 causes the
249  * rate adapter to store a packet until either the entire packet is received or the
250  * buffer becomes full.
251  *
252  * Field Access Macros:
253  *
254  */
255 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_RATE register field. */
256 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_RATE_LSB 0
257 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_RATE register field. */
258 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_RATE_MSB 9
259 /* The width in bits of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_RATE register field. */
260 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_RATE_WIDTH 10
261 /* The mask used to set the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_RATE register field value. */
262 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_RATE_SET_MSK 0x000003ff
263 /* The mask used to clear the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_RATE register field value. */
264 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_RATE_CLR_MSK 0xfffffc00
265 /* The reset value of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_RATE register field. */
266 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_RATE_RESET 0x0
267 /* Extracts the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_RATE field value from a register. */
268 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_RATE_GET(value) (((value) & 0x000003ff) >> 0)
269 /* Produces a ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_RATE register field value suitable for setting the register. */
270 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_RATE_SET(value) (((value) << 0) & 0x000003ff)
271 
272 #ifndef __ASSEMBLY__
273 /*
274  * WARNING: The C register and register group struct declarations are provided for
275  * convenience and illustrative purposes. They should, however, be used with
276  * caution as the C language standard provides no guarantees about the alignment or
277  * atomicity of device memory accesses. The recommended practice for coding device
278  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
279  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
280  * alt_write_dword() functions for 64 bit registers.
281  *
282  * The struct declaration for register ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE.
283  */
284 struct ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_s
285 {
286  volatile uint32_t RATE : 10; /* ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_RATE */
287  uint32_t : 22; /* *UNDEFINED* */
288 };
289 
290 /* The typedef declaration for register ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE. */
291 typedef struct ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_s ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_t;
292 #endif /* __ASSEMBLY__ */
293 
294 /* The reset value of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE register. */
295 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_RESET 0x00000000
296 /* The byte offset of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE register from the beginning of the component. */
297 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_OFST 0x8
298 
299 /*
300  * Register : l4_linkResp_main_RateAdapter_Bypass
301  *
302  * Register Layout
303  *
304  * Bits | Access | Reset | Description
305  * :-------|:-------|:--------|:--------------------------------------------------------------------------
306  * [0] | RW | 0x0 | ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_BYPASS
307  * [31:1] | ??? | Unknown | *UNDEFINED*
308  *
309  */
310 /*
311  * Field : BYPASS
312  *
313  * Disable the rate adaptation capability. This causes the rate adapter to act as a
314  * FIFO by transmitting received words, without delay, as soon as they can be
315  * transmitted. This setting is useful when the incoming throughput is equal to or
316  * greater than the downstream throughput.
317  *
318  * Field Access Macros:
319  *
320  */
321 /* The Least Significant Bit (LSB) position of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_BYPASS register field. */
322 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_BYPASS_LSB 0
323 /* The Most Significant Bit (MSB) position of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_BYPASS register field. */
324 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_BYPASS_MSB 0
325 /* The width in bits of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_BYPASS register field. */
326 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_BYPASS_WIDTH 1
327 /* The mask used to set the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_BYPASS register field value. */
328 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_BYPASS_SET_MSK 0x00000001
329 /* The mask used to clear the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_BYPASS register field value. */
330 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_BYPASS_CLR_MSK 0xfffffffe
331 /* The reset value of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_BYPASS register field. */
332 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_BYPASS_RESET 0x0
333 /* Extracts the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_BYPASS field value from a register. */
334 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_BYPASS_GET(value) (((value) & 0x00000001) >> 0)
335 /* Produces a ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_BYPASS register field value suitable for setting the register. */
336 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_BYPASS_SET(value) (((value) << 0) & 0x00000001)
337 
338 #ifndef __ASSEMBLY__
339 /*
340  * WARNING: The C register and register group struct declarations are provided for
341  * convenience and illustrative purposes. They should, however, be used with
342  * caution as the C language standard provides no guarantees about the alignment or
343  * atomicity of device memory accesses. The recommended practice for coding device
344  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
345  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
346  * alt_write_dword() functions for 64 bit registers.
347  *
348  * The struct declaration for register ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS.
349  */
350 struct ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_s
351 {
352  volatile uint32_t BYPASS : 1; /* ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_BYPASS */
353  uint32_t : 31; /* *UNDEFINED* */
354 };
355 
356 /* The typedef declaration for register ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS. */
357 typedef struct ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_s ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_t;
358 #endif /* __ASSEMBLY__ */
359 
360 /* The reset value of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS register. */
361 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_RESET 0x00000000
362 /* The byte offset of the ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS register from the beginning of the component. */
363 #define ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_OFST 0xc
364 
365 #ifndef __ASSEMBLY__
366 /*
367  * WARNING: The C register and register group struct declarations are provided for
368  * convenience and illustrative purposes. They should, however, be used with
369  * caution as the C language standard provides no guarantees about the alignment or
370  * atomicity of device memory accesses. The recommended practice for coding device
371  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
372  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
373  * alt_write_dword() functions for 64 bit registers.
374  *
375  * The struct declaration for register group ALT_NOC_CCU_L4_LINK_RATE_ADPTR.
376  */
377 struct ALT_NOC_CCU_L4_LINK_RATE_ADPTR_s
378 {
379  volatile ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID_t l4_linkResp_main_RateAdapter_Id_CoreId; /* ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID */
380  volatile ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID_t l4_linkResp_main_RateAdapter_Id_RevisionId; /* ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID */
381  volatile ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE_t l4_linkResp_main_RateAdapter_Rate; /* ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE */
382  volatile ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS_t l4_linkResp_main_RateAdapter_Bypass; /* ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS */
383  volatile uint32_t _pad_0x10_0x80[28]; /* *UNDEFINED* */
384 };
385 
386 /* The typedef declaration for register group ALT_NOC_CCU_L4_LINK_RATE_ADPTR. */
387 typedef struct ALT_NOC_CCU_L4_LINK_RATE_ADPTR_s ALT_NOC_CCU_L4_LINK_RATE_ADPTR_t;
388 /* The struct declaration for the raw register contents of register group ALT_NOC_CCU_L4_LINK_RATE_ADPTR. */
389 struct ALT_NOC_CCU_L4_LINK_RATE_ADPTR_raw_s
390 {
391  volatile uint32_t l4_linkResp_main_RateAdapter_Id_CoreId; /* ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_COREID */
392  volatile uint32_t l4_linkResp_main_RateAdapter_Id_RevisionId; /* ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_ID_REVISIONID */
393  volatile uint32_t l4_linkResp_main_RateAdapter_Rate; /* ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_RATE */
394  volatile uint32_t l4_linkResp_main_RateAdapter_Bypass; /* ALT_NOC_CCU_L4_LINK_RATE_ADPTR_L4_LINKRESP_MAIN_RATEADAPTER_BYPASS */
395  volatile uint32_t _pad_0x10_0x80[28]; /* *UNDEFINED* */
396 };
397 
398 /* The typedef declaration for the raw register contents of register group ALT_NOC_CCU_L4_LINK_RATE_ADPTR. */
399 typedef struct ALT_NOC_CCU_L4_LINK_RATE_ADPTR_raw_s ALT_NOC_CCU_L4_LINK_RATE_ADPTR_raw_t;
400 #endif /* __ASSEMBLY__ */
401 
402 
403 #ifdef __cplusplus
404 }
405 #endif /* __cplusplus */
406 #endif /* __ALT_SOCAL_NOC_CCU_L4_LINK_RATE_ADPTR_H__ */
407