Hardware Libraries  20.1
Arria 10 SoC Hardware Manager
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alt_scanmgr.h
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32 
33 /* Altera - ALT_SCANMGR */
34 
35 #ifndef __ALTERA_ALT_SCANMGR_H__
36 #define __ALTERA_ALT_SCANMGR_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
43 /*
44  * Component : Scan Manager Module Registers - ALT_SCANMGR
45  * Scan Manager Module Registers
46  *
47  * Registers in the Scan Manager module.
48  *
49  * These registers are implemented by an ARM JTAG-AP module from the ARM DAP. Some
50  * register and field names have been changed to match the usage in the Scan
51  * Manager. If modified, the corresponding names from the ARM documentation are
52  * provided. Only registers and fields that are relevant to the JTAG-AP use in the
53  * Scan Manager are listed.
54  *
55  */
56 /*
57  * Register : Control/Status Word Register - stat
58  *
59  * Consist of control bit and status information.
60  *
61  * Register Layout
62  *
63  * Bits | Access | Reset | Description
64  * :--------|:-------|:--------|:-------------------------------------
65  * [0] | ??? | 0x0 | *UNDEFINED*
66  * [1] | RW | 0x0 | Reset output to the FPGA JTAG
67  * [2] | ??? | 0x0 | *UNDEFINED*
68  * [3] | R | Unknown | Ignore
69  * [23:4] | ??? | 0x0 | *UNDEFINED*
70  * [26:24] | R | 0x0 | Response FIFO Outstanding Byte Count
71  * [27] | ??? | 0x0 | *UNDEFINED*
72  * [30:28] | R | 0x0 | Command FIFO Outstanding Byte Count
73  * [31] | R | 0x0 | Scan-Chain Engine Active
74  *
75  */
76 /*
77  * Field : Reset output to the FPGA JTAG - trst
78  *
79  * Specifies the value of the nTRST signal driven to the FPGA JTAG only. The FPGA
80  * JTAG scan-chain must be enabled via the EN register to drive the value specified
81  * in this field. The nTRST signal is driven with the inverted value of this
82  * field.The nTRST signal is active low so, when this bit is set to 1, FPGA JTAG is
83  * reset.
84  *
85  * The name of this field in ARM documentation is TRST_OUT.
86  *
87  * Field Enumeration Values:
88  *
89  * Enum | Value | Description
90  * :-------------------------------------------|:------|:-------------------------------------------------
91  * ALT_SCANMGR_STAT_TRST_E_DONT_RST_FPGA_JTAG | 0x0 | Don't reset FPGA JTAG.
92  * ALT_SCANMGR_STAT_TRST_E_RST_FPGA_JTAG | 0x1 | Reset FPGA JTAG. Must have the FPGA JTAG scan-
93  * : | | chain enabled in the EN register to take effect.
94  *
95  * Field Access Macros:
96  *
97  */
98 /*
99  * Enumerated value for register field ALT_SCANMGR_STAT_TRST
100  *
101  * Don't reset FPGA JTAG.
102  */
103 #define ALT_SCANMGR_STAT_TRST_E_DONT_RST_FPGA_JTAG 0x0
104 /*
105  * Enumerated value for register field ALT_SCANMGR_STAT_TRST
106  *
107  * Reset FPGA JTAG. Must have the FPGA JTAG scan-chain enabled in the EN register
108  * to take effect.
109  */
110 #define ALT_SCANMGR_STAT_TRST_E_RST_FPGA_JTAG 0x1
111 
112 /* The Least Significant Bit (LSB) position of the ALT_SCANMGR_STAT_TRST register field. */
113 #define ALT_SCANMGR_STAT_TRST_LSB 1
114 /* The Most Significant Bit (MSB) position of the ALT_SCANMGR_STAT_TRST register field. */
115 #define ALT_SCANMGR_STAT_TRST_MSB 1
116 /* The width in bits of the ALT_SCANMGR_STAT_TRST register field. */
117 #define ALT_SCANMGR_STAT_TRST_WIDTH 1
118 /* The mask used to set the ALT_SCANMGR_STAT_TRST register field value. */
119 #define ALT_SCANMGR_STAT_TRST_SET_MSK 0x00000002
120 /* The mask used to clear the ALT_SCANMGR_STAT_TRST register field value. */
121 #define ALT_SCANMGR_STAT_TRST_CLR_MSK 0xfffffffd
122 /* The reset value of the ALT_SCANMGR_STAT_TRST register field. */
123 #define ALT_SCANMGR_STAT_TRST_RESET 0x0
124 /* Extracts the ALT_SCANMGR_STAT_TRST field value from a register. */
125 #define ALT_SCANMGR_STAT_TRST_GET(value) (((value) & 0x00000002) >> 1)
126 /* Produces a ALT_SCANMGR_STAT_TRST register field value suitable for setting the register. */
127 #define ALT_SCANMGR_STAT_TRST_SET(value) (((value) << 1) & 0x00000002)
128 
129 /*
130  * Field : Ignore - ignore
131  *
132  * Ignore this field. Its value is undefined (may be 0 or 1).
133  *
134  * The name of this field in ARM documentation is PORTCONNECTED.
135  *
136  * Field Access Macros:
137  *
138  */
139 /* The Least Significant Bit (LSB) position of the ALT_SCANMGR_STAT_IGNORE register field. */
140 #define ALT_SCANMGR_STAT_IGNORE_LSB 3
141 /* The Most Significant Bit (MSB) position of the ALT_SCANMGR_STAT_IGNORE register field. */
142 #define ALT_SCANMGR_STAT_IGNORE_MSB 3
143 /* The width in bits of the ALT_SCANMGR_STAT_IGNORE register field. */
144 #define ALT_SCANMGR_STAT_IGNORE_WIDTH 1
145 /* The mask used to set the ALT_SCANMGR_STAT_IGNORE register field value. */
146 #define ALT_SCANMGR_STAT_IGNORE_SET_MSK 0x00000008
147 /* The mask used to clear the ALT_SCANMGR_STAT_IGNORE register field value. */
148 #define ALT_SCANMGR_STAT_IGNORE_CLR_MSK 0xfffffff7
149 /* The reset value of the ALT_SCANMGR_STAT_IGNORE register field is UNKNOWN. */
150 #define ALT_SCANMGR_STAT_IGNORE_RESET 0x0
151 /* Extracts the ALT_SCANMGR_STAT_IGNORE field value from a register. */
152 #define ALT_SCANMGR_STAT_IGNORE_GET(value) (((value) & 0x00000008) >> 3)
153 /* Produces a ALT_SCANMGR_STAT_IGNORE register field value suitable for setting the register. */
154 #define ALT_SCANMGR_STAT_IGNORE_SET(value) (((value) << 3) & 0x00000008)
155 
156 /*
157  * Field : Response FIFO Outstanding Byte Count - rfifocnt
158  *
159  * Response FIFO outstanding byte count. Returns the number of bytes of response
160  * data available in the Response FIFO.
161  *
162  * Field Access Macros:
163  *
164  */
165 /* The Least Significant Bit (LSB) position of the ALT_SCANMGR_STAT_RFIFOCNT register field. */
166 #define ALT_SCANMGR_STAT_RFIFOCNT_LSB 24
167 /* The Most Significant Bit (MSB) position of the ALT_SCANMGR_STAT_RFIFOCNT register field. */
168 #define ALT_SCANMGR_STAT_RFIFOCNT_MSB 26
169 /* The width in bits of the ALT_SCANMGR_STAT_RFIFOCNT register field. */
170 #define ALT_SCANMGR_STAT_RFIFOCNT_WIDTH 3
171 /* The mask used to set the ALT_SCANMGR_STAT_RFIFOCNT register field value. */
172 #define ALT_SCANMGR_STAT_RFIFOCNT_SET_MSK 0x07000000
173 /* The mask used to clear the ALT_SCANMGR_STAT_RFIFOCNT register field value. */
174 #define ALT_SCANMGR_STAT_RFIFOCNT_CLR_MSK 0xf8ffffff
175 /* The reset value of the ALT_SCANMGR_STAT_RFIFOCNT register field. */
176 #define ALT_SCANMGR_STAT_RFIFOCNT_RESET 0x0
177 /* Extracts the ALT_SCANMGR_STAT_RFIFOCNT field value from a register. */
178 #define ALT_SCANMGR_STAT_RFIFOCNT_GET(value) (((value) & 0x07000000) >> 24)
179 /* Produces a ALT_SCANMGR_STAT_RFIFOCNT register field value suitable for setting the register. */
180 #define ALT_SCANMGR_STAT_RFIFOCNT_SET(value) (((value) << 24) & 0x07000000)
181 
182 /*
183  * Field : Command FIFO Outstanding Byte Count - wfifocnt
184  *
185  * Command FIFO outstanding byte count. Returns the number of command bytes held in
186  * the Command FIFO that have yet to be processed by the Scan-Chain Engine.
187  *
188  * Field Access Macros:
189  *
190  */
191 /* The Least Significant Bit (LSB) position of the ALT_SCANMGR_STAT_WFIFOCNT register field. */
192 #define ALT_SCANMGR_STAT_WFIFOCNT_LSB 28
193 /* The Most Significant Bit (MSB) position of the ALT_SCANMGR_STAT_WFIFOCNT register field. */
194 #define ALT_SCANMGR_STAT_WFIFOCNT_MSB 30
195 /* The width in bits of the ALT_SCANMGR_STAT_WFIFOCNT register field. */
196 #define ALT_SCANMGR_STAT_WFIFOCNT_WIDTH 3
197 /* The mask used to set the ALT_SCANMGR_STAT_WFIFOCNT register field value. */
198 #define ALT_SCANMGR_STAT_WFIFOCNT_SET_MSK 0x70000000
199 /* The mask used to clear the ALT_SCANMGR_STAT_WFIFOCNT register field value. */
200 #define ALT_SCANMGR_STAT_WFIFOCNT_CLR_MSK 0x8fffffff
201 /* The reset value of the ALT_SCANMGR_STAT_WFIFOCNT register field. */
202 #define ALT_SCANMGR_STAT_WFIFOCNT_RESET 0x0
203 /* Extracts the ALT_SCANMGR_STAT_WFIFOCNT field value from a register. */
204 #define ALT_SCANMGR_STAT_WFIFOCNT_GET(value) (((value) & 0x70000000) >> 28)
205 /* Produces a ALT_SCANMGR_STAT_WFIFOCNT register field value suitable for setting the register. */
206 #define ALT_SCANMGR_STAT_WFIFOCNT_SET(value) (((value) << 28) & 0x70000000)
207 
208 /*
209  * Field : Scan-Chain Engine Active - active
210  *
211  * Indicates if the Scan-Chain Engine is processing commands from the Command FIFO
212  * or not.
213  *
214  * The Scan-Chain Engine is only guaranteed to be inactive if both the ACTIVE and
215  * WFIFOCNT fields are zero.
216  *
217  * The name of this field in ARM documentation is SERACTV.
218  *
219  * Field Enumeration Values:
220  *
221  * Enum | Value | Description
222  * :--------------------------------------|:------|:-----------------------------------------------
223  * ALT_SCANMGR_STAT_ACT_E_POSSIBLY_INACT | 0x0 | The Scan-Chain Engine may or may not be
224  * : | | processing commands from the Command FIFO. The
225  * : | | Scan-Chain Engine is only guaranteed to be
226  * : | | inactive if both this ACTIVE field and the
227  * : | | WFIFOCNT fields are both zero.
228  * ALT_SCANMGR_STAT_ACT_E_ACT | 0x1 | The Scan-Chain Engine is processing commands
229  * : | | from the Command FIFO.
230  *
231  * Field Access Macros:
232  *
233  */
234 /*
235  * Enumerated value for register field ALT_SCANMGR_STAT_ACT
236  *
237  * The Scan-Chain Engine may or may not be processing commands from the Command
238  * FIFO. The Scan-Chain Engine is only guaranteed to be inactive if both this
239  * ACTIVE field and the WFIFOCNT fields are both zero.
240  */
241 #define ALT_SCANMGR_STAT_ACT_E_POSSIBLY_INACT 0x0
242 /*
243  * Enumerated value for register field ALT_SCANMGR_STAT_ACT
244  *
245  * The Scan-Chain Engine is processing commands from the Command FIFO.
246  */
247 #define ALT_SCANMGR_STAT_ACT_E_ACT 0x1
248 
249 /* The Least Significant Bit (LSB) position of the ALT_SCANMGR_STAT_ACT register field. */
250 #define ALT_SCANMGR_STAT_ACT_LSB 31
251 /* The Most Significant Bit (MSB) position of the ALT_SCANMGR_STAT_ACT register field. */
252 #define ALT_SCANMGR_STAT_ACT_MSB 31
253 /* The width in bits of the ALT_SCANMGR_STAT_ACT register field. */
254 #define ALT_SCANMGR_STAT_ACT_WIDTH 1
255 /* The mask used to set the ALT_SCANMGR_STAT_ACT register field value. */
256 #define ALT_SCANMGR_STAT_ACT_SET_MSK 0x80000000
257 /* The mask used to clear the ALT_SCANMGR_STAT_ACT register field value. */
258 #define ALT_SCANMGR_STAT_ACT_CLR_MSK 0x7fffffff
259 /* The reset value of the ALT_SCANMGR_STAT_ACT register field. */
260 #define ALT_SCANMGR_STAT_ACT_RESET 0x0
261 /* Extracts the ALT_SCANMGR_STAT_ACT field value from a register. */
262 #define ALT_SCANMGR_STAT_ACT_GET(value) (((value) & 0x80000000) >> 31)
263 /* Produces a ALT_SCANMGR_STAT_ACT register field value suitable for setting the register. */
264 #define ALT_SCANMGR_STAT_ACT_SET(value) (((value) << 31) & 0x80000000)
265 
266 #ifndef __ASSEMBLY__
267 /*
268  * WARNING: The C register and register group struct declarations are provided for
269  * convenience and illustrative purposes. They should, however, be used with
270  * caution as the C language standard provides no guarantees about the alignment or
271  * atomicity of device memory accesses. The recommended practice for writing
272  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
273  * alt_write_word() functions.
274  *
275  * The struct declaration for register ALT_SCANMGR_STAT.
276  */
277 struct ALT_SCANMGR_STAT_s
278 {
279  uint32_t : 1; /* *UNDEFINED* */
280  uint32_t trst : 1; /* Reset output to the FPGA JTAG */
281  uint32_t : 1; /* *UNDEFINED* */
282  const uint32_t ignore : 1; /* Ignore */
283  uint32_t : 20; /* *UNDEFINED* */
284  const uint32_t rfifocnt : 3; /* Response FIFO Outstanding Byte Count */
285  uint32_t : 1; /* *UNDEFINED* */
286  const uint32_t wfifocnt : 3; /* Command FIFO Outstanding Byte Count */
287  const uint32_t active : 1; /* Scan-Chain Engine Active */
288 };
289 
290 /* The typedef declaration for register ALT_SCANMGR_STAT. */
291 typedef volatile struct ALT_SCANMGR_STAT_s ALT_SCANMGR_STAT_t;
292 #endif /* __ASSEMBLY__ */
293 
294 /* The byte offset of the ALT_SCANMGR_STAT register from the beginning of the component. */
295 #define ALT_SCANMGR_STAT_OFST 0x0
296 
297 /*
298  * Register : Scan-Chain Enable Register - en
299  *
300  * This register is used to enable one of the 5 scan-chains (0-3 and 7). Only one
301  * scan-chain must be enabled at a time. A scan-chain is enabled by writing its
302  * corresponding enable field.
303  *
304  * Software must use the System Manager to put the corresponding I/O scan-chain
305  * into the frozen state before attempting to send I/O configuration data to the
306  * I/O scan-chain.
307  *
308  * Software must only write to this register when the Scan-Chain Engine is
309  * inactive.Writing this field at any other time has unpredictable results. This
310  * means that before writing to this field, software must read the STAT register
311  * and check that the ACTIVE and WFIFOCNT fields are both zero.
312  *
313  * The name of this register in ARM documentation is PSEL.
314  *
315  * Register Layout
316  *
317  * Bits | Access | Reset | Description
318  * :-------|:-------|:------|:----------------------------
319  * [0] | RW | 0x0 | I/O Scan-Chain 0 Enable
320  * [1] | RW | 0x0 | I/O Scan-Chain 1 Enable
321  * [2] | RW | 0x0 | I/O Scan-Chain 2 Enable
322  * [3] | RW | 0x0 | I/O Scan-Chain 3 Enable
323  * [6:4] | ??? | 0x0 | *UNDEFINED*
324  * [7] | RW | 0x0 | FPGA JTAG Scan-Chain Enable
325  * [31:8] | ??? | 0x0 | *UNDEFINED*
326  *
327  */
328 /*
329  * Field : I/O Scan-Chain 0 Enable - ioscanchain0
330  *
331  * Used to enable or disable I/O Scan-Chain 0
332  *
333  * The name of this field in ARM documentation is PSEL0.
334  *
335  * Field Enumeration Values:
336  *
337  * Enum | Value | Description
338  * :----------------------------------|:------|:-------------------
339  * ALT_SCANMGR_EN_IOSCANCHAIN0_E_DIS | 0x0 | Disable scan-chain
340  * ALT_SCANMGR_EN_IOSCANCHAIN0_E_EN | 0x1 | Enable scan-chain
341  *
342  * Field Access Macros:
343  *
344  */
345 /*
346  * Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN0
347  *
348  * Disable scan-chain
349  */
350 #define ALT_SCANMGR_EN_IOSCANCHAIN0_E_DIS 0x0
351 /*
352  * Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN0
353  *
354  * Enable scan-chain
355  */
356 #define ALT_SCANMGR_EN_IOSCANCHAIN0_E_EN 0x1
357 
358 /* The Least Significant Bit (LSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN0 register field. */
359 #define ALT_SCANMGR_EN_IOSCANCHAIN0_LSB 0
360 /* The Most Significant Bit (MSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN0 register field. */
361 #define ALT_SCANMGR_EN_IOSCANCHAIN0_MSB 0
362 /* The width in bits of the ALT_SCANMGR_EN_IOSCANCHAIN0 register field. */
363 #define ALT_SCANMGR_EN_IOSCANCHAIN0_WIDTH 1
364 /* The mask used to set the ALT_SCANMGR_EN_IOSCANCHAIN0 register field value. */
365 #define ALT_SCANMGR_EN_IOSCANCHAIN0_SET_MSK 0x00000001
366 /* The mask used to clear the ALT_SCANMGR_EN_IOSCANCHAIN0 register field value. */
367 #define ALT_SCANMGR_EN_IOSCANCHAIN0_CLR_MSK 0xfffffffe
368 /* The reset value of the ALT_SCANMGR_EN_IOSCANCHAIN0 register field. */
369 #define ALT_SCANMGR_EN_IOSCANCHAIN0_RESET 0x0
370 /* Extracts the ALT_SCANMGR_EN_IOSCANCHAIN0 field value from a register. */
371 #define ALT_SCANMGR_EN_IOSCANCHAIN0_GET(value) (((value) & 0x00000001) >> 0)
372 /* Produces a ALT_SCANMGR_EN_IOSCANCHAIN0 register field value suitable for setting the register. */
373 #define ALT_SCANMGR_EN_IOSCANCHAIN0_SET(value) (((value) << 0) & 0x00000001)
374 
375 /*
376  * Field : I/O Scan-Chain 1 Enable - ioscanchain1
377  *
378  * Used to enable or disable I/O Scan-Chain 1
379  *
380  * The name of this field in ARM documentation is PSEL1.
381  *
382  * Field Enumeration Values:
383  *
384  * Enum | Value | Description
385  * :----------------------------------|:------|:-------------------
386  * ALT_SCANMGR_EN_IOSCANCHAIN1_E_DIS | 0x0 | Disable scan-chain
387  * ALT_SCANMGR_EN_IOSCANCHAIN1_E_EN | 0x1 | Enable scan-chain
388  *
389  * Field Access Macros:
390  *
391  */
392 /*
393  * Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN1
394  *
395  * Disable scan-chain
396  */
397 #define ALT_SCANMGR_EN_IOSCANCHAIN1_E_DIS 0x0
398 /*
399  * Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN1
400  *
401  * Enable scan-chain
402  */
403 #define ALT_SCANMGR_EN_IOSCANCHAIN1_E_EN 0x1
404 
405 /* The Least Significant Bit (LSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN1 register field. */
406 #define ALT_SCANMGR_EN_IOSCANCHAIN1_LSB 1
407 /* The Most Significant Bit (MSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN1 register field. */
408 #define ALT_SCANMGR_EN_IOSCANCHAIN1_MSB 1
409 /* The width in bits of the ALT_SCANMGR_EN_IOSCANCHAIN1 register field. */
410 #define ALT_SCANMGR_EN_IOSCANCHAIN1_WIDTH 1
411 /* The mask used to set the ALT_SCANMGR_EN_IOSCANCHAIN1 register field value. */
412 #define ALT_SCANMGR_EN_IOSCANCHAIN1_SET_MSK 0x00000002
413 /* The mask used to clear the ALT_SCANMGR_EN_IOSCANCHAIN1 register field value. */
414 #define ALT_SCANMGR_EN_IOSCANCHAIN1_CLR_MSK 0xfffffffd
415 /* The reset value of the ALT_SCANMGR_EN_IOSCANCHAIN1 register field. */
416 #define ALT_SCANMGR_EN_IOSCANCHAIN1_RESET 0x0
417 /* Extracts the ALT_SCANMGR_EN_IOSCANCHAIN1 field value from a register. */
418 #define ALT_SCANMGR_EN_IOSCANCHAIN1_GET(value) (((value) & 0x00000002) >> 1)
419 /* Produces a ALT_SCANMGR_EN_IOSCANCHAIN1 register field value suitable for setting the register. */
420 #define ALT_SCANMGR_EN_IOSCANCHAIN1_SET(value) (((value) << 1) & 0x00000002)
421 
422 /*
423  * Field : I/O Scan-Chain 2 Enable - ioscanchain2
424  *
425  * Used to enable or disable I/O Scan-Chain 2
426  *
427  * The name of this field in ARM documentation is PSEL2.
428  *
429  * Field Enumeration Values:
430  *
431  * Enum | Value | Description
432  * :----------------------------------|:------|:-------------------
433  * ALT_SCANMGR_EN_IOSCANCHAIN2_E_DIS | 0x0 | Disable scan-chain
434  * ALT_SCANMGR_EN_IOSCANCHAIN2_E_EN | 0x1 | Enable scan-chain
435  *
436  * Field Access Macros:
437  *
438  */
439 /*
440  * Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN2
441  *
442  * Disable scan-chain
443  */
444 #define ALT_SCANMGR_EN_IOSCANCHAIN2_E_DIS 0x0
445 /*
446  * Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN2
447  *
448  * Enable scan-chain
449  */
450 #define ALT_SCANMGR_EN_IOSCANCHAIN2_E_EN 0x1
451 
452 /* The Least Significant Bit (LSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN2 register field. */
453 #define ALT_SCANMGR_EN_IOSCANCHAIN2_LSB 2
454 /* The Most Significant Bit (MSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN2 register field. */
455 #define ALT_SCANMGR_EN_IOSCANCHAIN2_MSB 2
456 /* The width in bits of the ALT_SCANMGR_EN_IOSCANCHAIN2 register field. */
457 #define ALT_SCANMGR_EN_IOSCANCHAIN2_WIDTH 1
458 /* The mask used to set the ALT_SCANMGR_EN_IOSCANCHAIN2 register field value. */
459 #define ALT_SCANMGR_EN_IOSCANCHAIN2_SET_MSK 0x00000004
460 /* The mask used to clear the ALT_SCANMGR_EN_IOSCANCHAIN2 register field value. */
461 #define ALT_SCANMGR_EN_IOSCANCHAIN2_CLR_MSK 0xfffffffb
462 /* The reset value of the ALT_SCANMGR_EN_IOSCANCHAIN2 register field. */
463 #define ALT_SCANMGR_EN_IOSCANCHAIN2_RESET 0x0
464 /* Extracts the ALT_SCANMGR_EN_IOSCANCHAIN2 field value from a register. */
465 #define ALT_SCANMGR_EN_IOSCANCHAIN2_GET(value) (((value) & 0x00000004) >> 2)
466 /* Produces a ALT_SCANMGR_EN_IOSCANCHAIN2 register field value suitable for setting the register. */
467 #define ALT_SCANMGR_EN_IOSCANCHAIN2_SET(value) (((value) << 2) & 0x00000004)
468 
469 /*
470  * Field : I/O Scan-Chain 3 Enable - ioscanchain3
471  *
472  * Used to enable or disable I/O Scan-Chain 3
473  *
474  * The name of this field in ARM documentation is PSEL3.
475  *
476  * Field Enumeration Values:
477  *
478  * Enum | Value | Description
479  * :----------------------------------|:------|:-------------------
480  * ALT_SCANMGR_EN_IOSCANCHAIN3_E_DIS | 0x0 | Disable scan-chain
481  * ALT_SCANMGR_EN_IOSCANCHAIN3_E_EN | 0x1 | Enable scan-chain
482  *
483  * Field Access Macros:
484  *
485  */
486 /*
487  * Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN3
488  *
489  * Disable scan-chain
490  */
491 #define ALT_SCANMGR_EN_IOSCANCHAIN3_E_DIS 0x0
492 /*
493  * Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN3
494  *
495  * Enable scan-chain
496  */
497 #define ALT_SCANMGR_EN_IOSCANCHAIN3_E_EN 0x1
498 
499 /* The Least Significant Bit (LSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN3 register field. */
500 #define ALT_SCANMGR_EN_IOSCANCHAIN3_LSB 3
501 /* The Most Significant Bit (MSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN3 register field. */
502 #define ALT_SCANMGR_EN_IOSCANCHAIN3_MSB 3
503 /* The width in bits of the ALT_SCANMGR_EN_IOSCANCHAIN3 register field. */
504 #define ALT_SCANMGR_EN_IOSCANCHAIN3_WIDTH 1
505 /* The mask used to set the ALT_SCANMGR_EN_IOSCANCHAIN3 register field value. */
506 #define ALT_SCANMGR_EN_IOSCANCHAIN3_SET_MSK 0x00000008
507 /* The mask used to clear the ALT_SCANMGR_EN_IOSCANCHAIN3 register field value. */
508 #define ALT_SCANMGR_EN_IOSCANCHAIN3_CLR_MSK 0xfffffff7
509 /* The reset value of the ALT_SCANMGR_EN_IOSCANCHAIN3 register field. */
510 #define ALT_SCANMGR_EN_IOSCANCHAIN3_RESET 0x0
511 /* Extracts the ALT_SCANMGR_EN_IOSCANCHAIN3 field value from a register. */
512 #define ALT_SCANMGR_EN_IOSCANCHAIN3_GET(value) (((value) & 0x00000008) >> 3)
513 /* Produces a ALT_SCANMGR_EN_IOSCANCHAIN3 register field value suitable for setting the register. */
514 #define ALT_SCANMGR_EN_IOSCANCHAIN3_SET(value) (((value) << 3) & 0x00000008)
515 
516 /*
517  * Field : FPGA JTAG Scan-Chain Enable - fpgajtag
518  *
519  * Used to enable or disable FPGA JTAG scan-chain.Software must use the System
520  * Manager to enable the Scan Manager to drive the FPGA JTAG before attempting to
521  * communicate with the FPGA JTAG via the Scan Manager.
522  *
523  * The name of this field in ARM documentation is PSEL7.
524  *
525  * Field Enumeration Values:
526  *
527  * Enum | Value | Description
528  * :------------------------------|:------|:-------------------
529  * ALT_SCANMGR_EN_FPGAJTAG_E_DIS | 0x0 | Disable scan-chain
530  * ALT_SCANMGR_EN_FPGAJTAG_E_EN | 0x1 | Enable scan-chain
531  *
532  * Field Access Macros:
533  *
534  */
535 /*
536  * Enumerated value for register field ALT_SCANMGR_EN_FPGAJTAG
537  *
538  * Disable scan-chain
539  */
540 #define ALT_SCANMGR_EN_FPGAJTAG_E_DIS 0x0
541 /*
542  * Enumerated value for register field ALT_SCANMGR_EN_FPGAJTAG
543  *
544  * Enable scan-chain
545  */
546 #define ALT_SCANMGR_EN_FPGAJTAG_E_EN 0x1
547 
548 /* The Least Significant Bit (LSB) position of the ALT_SCANMGR_EN_FPGAJTAG register field. */
549 #define ALT_SCANMGR_EN_FPGAJTAG_LSB 7
550 /* The Most Significant Bit (MSB) position of the ALT_SCANMGR_EN_FPGAJTAG register field. */
551 #define ALT_SCANMGR_EN_FPGAJTAG_MSB 7
552 /* The width in bits of the ALT_SCANMGR_EN_FPGAJTAG register field. */
553 #define ALT_SCANMGR_EN_FPGAJTAG_WIDTH 1
554 /* The mask used to set the ALT_SCANMGR_EN_FPGAJTAG register field value. */
555 #define ALT_SCANMGR_EN_FPGAJTAG_SET_MSK 0x00000080
556 /* The mask used to clear the ALT_SCANMGR_EN_FPGAJTAG register field value. */
557 #define ALT_SCANMGR_EN_FPGAJTAG_CLR_MSK 0xffffff7f
558 /* The reset value of the ALT_SCANMGR_EN_FPGAJTAG register field. */
559 #define ALT_SCANMGR_EN_FPGAJTAG_RESET 0x0
560 /* Extracts the ALT_SCANMGR_EN_FPGAJTAG field value from a register. */
561 #define ALT_SCANMGR_EN_FPGAJTAG_GET(value) (((value) & 0x00000080) >> 7)
562 /* Produces a ALT_SCANMGR_EN_FPGAJTAG register field value suitable for setting the register. */
563 #define ALT_SCANMGR_EN_FPGAJTAG_SET(value) (((value) << 7) & 0x00000080)
564 
565 #ifndef __ASSEMBLY__
566 /*
567  * WARNING: The C register and register group struct declarations are provided for
568  * convenience and illustrative purposes. They should, however, be used with
569  * caution as the C language standard provides no guarantees about the alignment or
570  * atomicity of device memory accesses. The recommended practice for writing
571  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
572  * alt_write_word() functions.
573  *
574  * The struct declaration for register ALT_SCANMGR_EN.
575  */
576 struct ALT_SCANMGR_EN_s
577 {
578  uint32_t ioscanchain0 : 1; /* I/O Scan-Chain 0 Enable */
579  uint32_t ioscanchain1 : 1; /* I/O Scan-Chain 1 Enable */
580  uint32_t ioscanchain2 : 1; /* I/O Scan-Chain 2 Enable */
581  uint32_t ioscanchain3 : 1; /* I/O Scan-Chain 3 Enable */
582  uint32_t : 3; /* *UNDEFINED* */
583  uint32_t fpgajtag : 1; /* FPGA JTAG Scan-Chain Enable */
584  uint32_t : 24; /* *UNDEFINED* */
585 };
586 
587 /* The typedef declaration for register ALT_SCANMGR_EN. */
588 typedef volatile struct ALT_SCANMGR_EN_s ALT_SCANMGR_EN_t;
589 #endif /* __ASSEMBLY__ */
590 
591 /* The byte offset of the ALT_SCANMGR_EN register from the beginning of the component. */
592 #define ALT_SCANMGR_EN_OFST 0x4
593 
594 /*
595  * Register : FIFO Single Byte Register - fifosinglebyte
596  *
597  * Writes to the FIFO Single Byte Register write a single byte value to the command
598  * FIFO. If the command FIFO is full, the APB write operation is stalled until the
599  * command FIFO is not full.
600  *
601  * Reads from the Single Byte FIFO Register read a single byte value from the
602  * command FIFO. If the command FIFO is empty, the APB read operation is stalled
603  * until the command FIFO is not empty.
604  *
605  * See the ARM documentation for a description of the read and write values.
606  *
607  * The name of this register in ARM documentation is BWFIFO1 for writes and BRFIFO1
608  * for reads.
609  *
610  * Register Layout
611  *
612  * Bits | Access | Reset | Description
613  * :-------|:-------|:--------|:------------------
614  * [7:0] | RW | Unknown | Single Byte Value
615  * [31:8] | ??? | 0x0 | *UNDEFINED*
616  *
617  */
618 /*
619  * Field : Single Byte Value - value
620  *
621  * Transfers single byte value to/from command FIFO
622  *
623  * Field Access Macros:
624  *
625  */
626 /* The Least Significant Bit (LSB) position of the ALT_SCANMGR_FIFOSINGLEBYTE_VALUE register field. */
627 #define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_LSB 0
628 /* The Most Significant Bit (MSB) position of the ALT_SCANMGR_FIFOSINGLEBYTE_VALUE register field. */
629 #define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_MSB 7
630 /* The width in bits of the ALT_SCANMGR_FIFOSINGLEBYTE_VALUE register field. */
631 #define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_WIDTH 8
632 /* The mask used to set the ALT_SCANMGR_FIFOSINGLEBYTE_VALUE register field value. */
633 #define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_SET_MSK 0x000000ff
634 /* The mask used to clear the ALT_SCANMGR_FIFOSINGLEBYTE_VALUE register field value. */
635 #define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_CLR_MSK 0xffffff00
636 /* The reset value of the ALT_SCANMGR_FIFOSINGLEBYTE_VALUE register field is UNKNOWN. */
637 #define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_RESET 0x0
638 /* Extracts the ALT_SCANMGR_FIFOSINGLEBYTE_VALUE field value from a register. */
639 #define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
640 /* Produces a ALT_SCANMGR_FIFOSINGLEBYTE_VALUE register field value suitable for setting the register. */
641 #define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_SET(value) (((value) << 0) & 0x000000ff)
642 
643 #ifndef __ASSEMBLY__
644 /*
645  * WARNING: The C register and register group struct declarations are provided for
646  * convenience and illustrative purposes. They should, however, be used with
647  * caution as the C language standard provides no guarantees about the alignment or
648  * atomicity of device memory accesses. The recommended practice for writing
649  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
650  * alt_write_word() functions.
651  *
652  * The struct declaration for register ALT_SCANMGR_FIFOSINGLEBYTE.
653  */
654 struct ALT_SCANMGR_FIFOSINGLEBYTE_s
655 {
656  uint32_t value : 8; /* Single Byte Value */
657  uint32_t : 24; /* *UNDEFINED* */
658 };
659 
660 /* The typedef declaration for register ALT_SCANMGR_FIFOSINGLEBYTE. */
661 typedef volatile struct ALT_SCANMGR_FIFOSINGLEBYTE_s ALT_SCANMGR_FIFOSINGLEBYTE_t;
662 #endif /* __ASSEMBLY__ */
663 
664 /* The byte offset of the ALT_SCANMGR_FIFOSINGLEBYTE register from the beginning of the component. */
665 #define ALT_SCANMGR_FIFOSINGLEBYTE_OFST 0x10
666 
667 /*
668  * Register : FIFO Double Byte Register - fifodoublebyte
669  *
670  * Writes to the FIFO Double Byte Register write a double byte value to the command
671  * FIFO. If the command FIFO is full, the APB write operation is stalled until the
672  * command FIFO is not full.
673  *
674  * Reads from the Double Byte FIFO Register read a double byte value from the
675  * command FIFO. If the command FIFO is empty, the APB read operation is stalled
676  * until the command FIFO is not empty.
677  *
678  * See the ARM documentation for a description of the read and write values.
679  *
680  * The name of this register in ARM documentation is BWFIFO2 for writes and BRFIFO2
681  * for reads.
682  *
683  * Register Layout
684  *
685  * Bits | Access | Reset | Description
686  * :--------|:-------|:--------|:------------------
687  * [15:0] | RW | Unknown | Double Byte Value
688  * [31:16] | ??? | 0x0 | *UNDEFINED*
689  *
690  */
691 /*
692  * Field : Double Byte Value - value
693  *
694  * Transfers double byte value to/from command FIFO
695  *
696  * Field Access Macros:
697  *
698  */
699 /* The Least Significant Bit (LSB) position of the ALT_SCANMGR_FIFODOUBLEBYTE_VALUE register field. */
700 #define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_LSB 0
701 /* The Most Significant Bit (MSB) position of the ALT_SCANMGR_FIFODOUBLEBYTE_VALUE register field. */
702 #define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_MSB 15
703 /* The width in bits of the ALT_SCANMGR_FIFODOUBLEBYTE_VALUE register field. */
704 #define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_WIDTH 16
705 /* The mask used to set the ALT_SCANMGR_FIFODOUBLEBYTE_VALUE register field value. */
706 #define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_SET_MSK 0x0000ffff
707 /* The mask used to clear the ALT_SCANMGR_FIFODOUBLEBYTE_VALUE register field value. */
708 #define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_CLR_MSK 0xffff0000
709 /* The reset value of the ALT_SCANMGR_FIFODOUBLEBYTE_VALUE register field is UNKNOWN. */
710 #define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_RESET 0x0
711 /* Extracts the ALT_SCANMGR_FIFODOUBLEBYTE_VALUE field value from a register. */
712 #define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
713 /* Produces a ALT_SCANMGR_FIFODOUBLEBYTE_VALUE register field value suitable for setting the register. */
714 #define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
715 
716 #ifndef __ASSEMBLY__
717 /*
718  * WARNING: The C register and register group struct declarations are provided for
719  * convenience and illustrative purposes. They should, however, be used with
720  * caution as the C language standard provides no guarantees about the alignment or
721  * atomicity of device memory accesses. The recommended practice for writing
722  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
723  * alt_write_word() functions.
724  *
725  * The struct declaration for register ALT_SCANMGR_FIFODOUBLEBYTE.
726  */
727 struct ALT_SCANMGR_FIFODOUBLEBYTE_s
728 {
729  uint32_t value : 16; /* Double Byte Value */
730  uint32_t : 16; /* *UNDEFINED* */
731 };
732 
733 /* The typedef declaration for register ALT_SCANMGR_FIFODOUBLEBYTE. */
734 typedef volatile struct ALT_SCANMGR_FIFODOUBLEBYTE_s ALT_SCANMGR_FIFODOUBLEBYTE_t;
735 #endif /* __ASSEMBLY__ */
736 
737 /* The byte offset of the ALT_SCANMGR_FIFODOUBLEBYTE register from the beginning of the component. */
738 #define ALT_SCANMGR_FIFODOUBLEBYTE_OFST 0x14
739 
740 /*
741  * Register : FIFO Triple Byte Register - fifotriplebyte
742  *
743  * Writes to the FIFO Triple Byte Register write a triple byte value to the command
744  * FIFO. If the command FIFO is full, the APB write operation is stalled until the
745  * command FIFO is not full.
746  *
747  * Reads from the Triple Byte FIFO Register read a triple byte value from the
748  * command FIFO. If the command FIFO is empty, the APB read operation is stalled
749  * until the command FIFO is not empty.
750  *
751  * See the ARM documentation for a description of the read and write values.
752  *
753  * The name of this register in ARM documentation is BWFIFO3 for writes and BRFIFO3
754  * for reads.
755  *
756  * Register Layout
757  *
758  * Bits | Access | Reset | Description
759  * :--------|:-------|:--------|:------------------
760  * [23:0] | RW | Unknown | Triple Byte Value
761  * [31:24] | ??? | 0x0 | *UNDEFINED*
762  *
763  */
764 /*
765  * Field : Triple Byte Value - value
766  *
767  * Transfers triple byte value to/from command FIFO
768  *
769  * Field Access Macros:
770  *
771  */
772 /* The Least Significant Bit (LSB) position of the ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE register field. */
773 #define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_LSB 0
774 /* The Most Significant Bit (MSB) position of the ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE register field. */
775 #define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_MSB 23
776 /* The width in bits of the ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE register field. */
777 #define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_WIDTH 24
778 /* The mask used to set the ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE register field value. */
779 #define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_SET_MSK 0x00ffffff
780 /* The mask used to clear the ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE register field value. */
781 #define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_CLR_MSK 0xff000000
782 /* The reset value of the ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE register field is UNKNOWN. */
783 #define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_RESET 0x0
784 /* Extracts the ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE field value from a register. */
785 #define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_GET(value) (((value) & 0x00ffffff) >> 0)
786 /* Produces a ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE register field value suitable for setting the register. */
787 #define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_SET(value) (((value) << 0) & 0x00ffffff)
788 
789 #ifndef __ASSEMBLY__
790 /*
791  * WARNING: The C register and register group struct declarations are provided for
792  * convenience and illustrative purposes. They should, however, be used with
793  * caution as the C language standard provides no guarantees about the alignment or
794  * atomicity of device memory accesses. The recommended practice for writing
795  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
796  * alt_write_word() functions.
797  *
798  * The struct declaration for register ALT_SCANMGR_FIFOTRIPLEBYTE.
799  */
800 struct ALT_SCANMGR_FIFOTRIPLEBYTE_s
801 {
802  uint32_t value : 24; /* Triple Byte Value */
803  uint32_t : 8; /* *UNDEFINED* */
804 };
805 
806 /* The typedef declaration for register ALT_SCANMGR_FIFOTRIPLEBYTE. */
807 typedef volatile struct ALT_SCANMGR_FIFOTRIPLEBYTE_s ALT_SCANMGR_FIFOTRIPLEBYTE_t;
808 #endif /* __ASSEMBLY__ */
809 
810 /* The byte offset of the ALT_SCANMGR_FIFOTRIPLEBYTE register from the beginning of the component. */
811 #define ALT_SCANMGR_FIFOTRIPLEBYTE_OFST 0x18
812 
813 /*
814  * Register : FIFO Quad Byte Register - fifoquadbyte
815  *
816  * Writes to the FIFO Quad Byte Register write a quad byte value to the command
817  * FIFO. If the command FIFO is full, the APB write operation is stalled until the
818  * command FIFO is not full.
819  *
820  * Reads from the Quad Byte FIFO Register read a quad byte value from the command
821  * FIFO. If the command FIFO is empty, the APB read operation is stalled until the
822  * command FIFO is not empty.
823  *
824  * See the ARM documentation for a description of the read and write values.
825  *
826  * The name of this register in ARM documentation is BWFIFO4 for writes and BRFIFO4
827  * for reads.
828  *
829  * Register Layout
830  *
831  * Bits | Access | Reset | Description
832  * :-------|:-------|:--------|:----------------
833  * [31:0] | RW | Unknown | Quad Byte Value
834  *
835  */
836 /*
837  * Field : Quad Byte Value - value
838  *
839  * Transfers quad byte value to/from command FIFO
840  *
841  * Field Access Macros:
842  *
843  */
844 /* The Least Significant Bit (LSB) position of the ALT_SCANMGR_FIFOQUADBYTE_VALUE register field. */
845 #define ALT_SCANMGR_FIFOQUADBYTE_VALUE_LSB 0
846 /* The Most Significant Bit (MSB) position of the ALT_SCANMGR_FIFOQUADBYTE_VALUE register field. */
847 #define ALT_SCANMGR_FIFOQUADBYTE_VALUE_MSB 31
848 /* The width in bits of the ALT_SCANMGR_FIFOQUADBYTE_VALUE register field. */
849 #define ALT_SCANMGR_FIFOQUADBYTE_VALUE_WIDTH 32
850 /* The mask used to set the ALT_SCANMGR_FIFOQUADBYTE_VALUE register field value. */
851 #define ALT_SCANMGR_FIFOQUADBYTE_VALUE_SET_MSK 0xffffffff
852 /* The mask used to clear the ALT_SCANMGR_FIFOQUADBYTE_VALUE register field value. */
853 #define ALT_SCANMGR_FIFOQUADBYTE_VALUE_CLR_MSK 0x00000000
854 /* The reset value of the ALT_SCANMGR_FIFOQUADBYTE_VALUE register field is UNKNOWN. */
855 #define ALT_SCANMGR_FIFOQUADBYTE_VALUE_RESET 0x0
856 /* Extracts the ALT_SCANMGR_FIFOQUADBYTE_VALUE field value from a register. */
857 #define ALT_SCANMGR_FIFOQUADBYTE_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
858 /* Produces a ALT_SCANMGR_FIFOQUADBYTE_VALUE register field value suitable for setting the register. */
859 #define ALT_SCANMGR_FIFOQUADBYTE_VALUE_SET(value) (((value) << 0) & 0xffffffff)
860 
861 #ifndef __ASSEMBLY__
862 /*
863  * WARNING: The C register and register group struct declarations are provided for
864  * convenience and illustrative purposes. They should, however, be used with
865  * caution as the C language standard provides no guarantees about the alignment or
866  * atomicity of device memory accesses. The recommended practice for writing
867  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
868  * alt_write_word() functions.
869  *
870  * The struct declaration for register ALT_SCANMGR_FIFOQUADBYTE.
871  */
872 struct ALT_SCANMGR_FIFOQUADBYTE_s
873 {
874  uint32_t value : 32; /* Quad Byte Value */
875 };
876 
877 /* The typedef declaration for register ALT_SCANMGR_FIFOQUADBYTE. */
878 typedef volatile struct ALT_SCANMGR_FIFOQUADBYTE_s ALT_SCANMGR_FIFOQUADBYTE_t;
879 #endif /* __ASSEMBLY__ */
880 
881 /* The byte offset of the ALT_SCANMGR_FIFOQUADBYTE register from the beginning of the component. */
882 #define ALT_SCANMGR_FIFOQUADBYTE_OFST 0x1c
883 
884 #ifndef __ASSEMBLY__
885 /*
886  * WARNING: The C register and register group struct declarations are provided for
887  * convenience and illustrative purposes. They should, however, be used with
888  * caution as the C language standard provides no guarantees about the alignment or
889  * atomicity of device memory accesses. The recommended practice for writing
890  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
891  * alt_write_word() functions.
892  *
893  * The struct declaration for register group ALT_SCANMGR.
894  */
895 struct ALT_SCANMGR_s
896 {
897  ALT_SCANMGR_STAT_t stat; /* ALT_SCANMGR_STAT */
898  ALT_SCANMGR_EN_t en; /* ALT_SCANMGR_EN */
899  volatile uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */
900  ALT_SCANMGR_FIFOSINGLEBYTE_t fifosinglebyte; /* ALT_SCANMGR_FIFOSINGLEBYTE */
901  ALT_SCANMGR_FIFODOUBLEBYTE_t fifodoublebyte; /* ALT_SCANMGR_FIFODOUBLEBYTE */
902  ALT_SCANMGR_FIFOTRIPLEBYTE_t fifotriplebyte; /* ALT_SCANMGR_FIFOTRIPLEBYTE */
903  ALT_SCANMGR_FIFOQUADBYTE_t fifoquadbyte; /* ALT_SCANMGR_FIFOQUADBYTE */
904 };
905 
906 /* The typedef declaration for register group ALT_SCANMGR. */
907 typedef volatile struct ALT_SCANMGR_s ALT_SCANMGR_t;
908 /* The struct declaration for the raw register contents of register group ALT_SCANMGR. */
909 struct ALT_SCANMGR_raw_s
910 {
911  volatile uint32_t stat; /* ALT_SCANMGR_STAT */
912  volatile uint32_t en; /* ALT_SCANMGR_EN */
913  uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */
914  volatile uint32_t fifosinglebyte; /* ALT_SCANMGR_FIFOSINGLEBYTE */
915  volatile uint32_t fifodoublebyte; /* ALT_SCANMGR_FIFODOUBLEBYTE */
916  volatile uint32_t fifotriplebyte; /* ALT_SCANMGR_FIFOTRIPLEBYTE */
917  volatile uint32_t fifoquadbyte; /* ALT_SCANMGR_FIFOQUADBYTE */
918 };
919 
920 /* The typedef declaration for the raw register contents of register group ALT_SCANMGR. */
921 typedef volatile struct ALT_SCANMGR_raw_s ALT_SCANMGR_raw_t;
922 #endif /* __ASSEMBLY__ */
923 
924 
925 #ifdef __cplusplus
926 }
927 #endif /* __cplusplus */
928 #endif /* __ALTERA_ALT_SCANMGR_H__ */
929