Hardware Libraries  20.1
Arria 10 SoC Abstration Layer
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alt_noc_mpu_ddr.h
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32 
33 /* Altera - ALT_NOC_MPU_DDR_T_PRB */
34 
35 #ifndef __ALT_SOCAL_NOC_MPU_DDR_H__
36 #define __ALT_SOCAL_NOC_MPU_DDR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_NOC_MPU_DDR_T_PRB
50  *
51  */
52 /*
53  * Register : ddr_T_main_Probe_Id_CoreId
54  *
55  * Register Layout
56  *
57  * Bits | Access | Reset | Description
58  * :-------|:-------|:---------|:--------------------------------------
59  * [7:0] | R | 0x6 | ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID
60  * [31:8] | R | 0xfa9ecc | ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM
61  *
62  */
63 /*
64  * Field : CORETYPEID
65  *
66  * Field identifying the type of IP.
67  *
68  * Field Access Macros:
69  *
70  */
71 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID register field. */
72 #define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_LSB 0
73 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID register field. */
74 #define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_MSB 7
75 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID register field. */
76 #define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_WIDTH 8
77 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID register field value. */
78 #define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_SET_MSK 0x000000ff
79 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID register field value. */
80 #define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_CLR_MSK 0xffffff00
81 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID register field. */
82 #define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_RESET 0x6
83 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID field value from a register. */
84 #define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_GET(value) (((value) & 0x000000ff) >> 0)
85 /* Produces a ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID register field value suitable for setting the register. */
86 #define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_SET(value) (((value) << 0) & 0x000000ff)
87 
88 /*
89  * Field : CORECHECKSUM
90  *
91  * Field containing a checksum of the parameters of the IP.
92  *
93  * Field Access Macros:
94  *
95  */
96 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM register field. */
97 #define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_LSB 8
98 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM register field. */
99 #define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_MSB 31
100 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM register field. */
101 #define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_WIDTH 24
102 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM register field value. */
103 #define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_SET_MSK 0xffffff00
104 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM register field value. */
105 #define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_CLR_MSK 0x000000ff
106 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM register field. */
107 #define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_RESET 0xfa9ecc
108 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM field value from a register. */
109 #define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
110 /* Produces a ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM register field value suitable for setting the register. */
111 #define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
112 
113 #ifndef __ASSEMBLY__
114 /*
115  * WARNING: The C register and register group struct declarations are provided for
116  * convenience and illustrative purposes. They should, however, be used with
117  * caution as the C language standard provides no guarantees about the alignment or
118  * atomicity of device memory accesses. The recommended practice for writing
119  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
120  * alt_write_word() functions.
121  *
122  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_COREID.
123  */
124 struct ALT_NOC_MPU_DDR_T_PRB_COREID_s
125 {
126  const uint32_t CORETYPEID : 8; /* ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID */
127  const uint32_t CORECHECKSUM : 24; /* ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM */
128 };
129 
130 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_COREID. */
131 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_COREID_s ALT_NOC_MPU_DDR_T_PRB_COREID_t;
132 #endif /* __ASSEMBLY__ */
133 
134 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_COREID register. */
135 #define ALT_NOC_MPU_DDR_T_PRB_COREID_RESET 0xfa9ecc06
136 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_COREID register from the beginning of the component. */
137 #define ALT_NOC_MPU_DDR_T_PRB_COREID_OFST 0x0
138 
139 /*
140  * Register : ddr_T_main_Probe_Id_RevisionId
141  *
142  * Register Layout
143  *
144  * Bits | Access | Reset | Description
145  * :-------|:-------|:--------|:--------------------------------------
146  * [7:0] | R | 0x0 | ALT_NOC_MPU_DDR_T_PRB_REVID_UID
147  * [31:8] | R | 0x129ff | ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID
148  *
149  */
150 /*
151  * Field : USERID
152  *
153  * Field containing a user defined value, not used anywhere inside the IP itself.
154  *
155  * Field Access Macros:
156  *
157  */
158 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_REVID_UID register field. */
159 #define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_LSB 0
160 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_REVID_UID register field. */
161 #define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_MSB 7
162 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_REVID_UID register field. */
163 #define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_WIDTH 8
164 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_REVID_UID register field value. */
165 #define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_SET_MSK 0x000000ff
166 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_REVID_UID register field value. */
167 #define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_CLR_MSK 0xffffff00
168 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_REVID_UID register field. */
169 #define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_RESET 0x0
170 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_REVID_UID field value from a register. */
171 #define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_GET(value) (((value) & 0x000000ff) >> 0)
172 /* Produces a ALT_NOC_MPU_DDR_T_PRB_REVID_UID register field value suitable for setting the register. */
173 #define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_SET(value) (((value) << 0) & 0x000000ff)
174 
175 /*
176  * Field : FLEXNOCID
177  *
178  * Field containing the build revision of the software used to generate the IP HDL
179  * code.
180  *
181  * Field Access Macros:
182  *
183  */
184 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID register field. */
185 #define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_LSB 8
186 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID register field. */
187 #define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_MSB 31
188 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID register field. */
189 #define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_WIDTH 24
190 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID register field value. */
191 #define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_SET_MSK 0xffffff00
192 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID register field value. */
193 #define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_CLR_MSK 0x000000ff
194 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID register field. */
195 #define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_RESET 0x129ff
196 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID field value from a register. */
197 #define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
198 /* Produces a ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID register field value suitable for setting the register. */
199 #define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
200 
201 #ifndef __ASSEMBLY__
202 /*
203  * WARNING: The C register and register group struct declarations are provided for
204  * convenience and illustrative purposes. They should, however, be used with
205  * caution as the C language standard provides no guarantees about the alignment or
206  * atomicity of device memory accesses. The recommended practice for writing
207  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
208  * alt_write_word() functions.
209  *
210  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_REVID.
211  */
212 struct ALT_NOC_MPU_DDR_T_PRB_REVID_s
213 {
214  const uint32_t USERID : 8; /* ALT_NOC_MPU_DDR_T_PRB_REVID_UID */
215  const uint32_t FLEXNOCID : 24; /* ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID */
216 };
217 
218 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_REVID. */
219 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_REVID_s ALT_NOC_MPU_DDR_T_PRB_REVID_t;
220 #endif /* __ASSEMBLY__ */
221 
222 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_REVID register. */
223 #define ALT_NOC_MPU_DDR_T_PRB_REVID_RESET 0x0129ff00
224 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_REVID register from the beginning of the component. */
225 #define ALT_NOC_MPU_DDR_T_PRB_REVID_OFST 0x4
226 
227 /*
228  * Register : ddr_T_main_Probe_MainCtl
229  *
230  * Register MainCtl contains probe global control bits. The register has seven bit
231  * fields:
232  *
233  * Register Layout
234  *
235  * Bits | Access | Reset | Description
236  * :-------|:-------|:--------|:--------------------------------------------------------
237  * [0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN
238  * [1] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN
239  * [2] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN
240  * [3] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN
241  * [4] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN
242  * [5] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP
243  * [6] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD
244  * [7] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN
245  * [31:8] | ??? | Unknown | *UNDEFINED*
246  *
247  */
248 /*
249  * Field : ERREN
250  *
251  * Register field ErrEn enables the probe to send on the ObsTx output any packet
252  * with Error status, independently of filtering mechanisms, thus constituting a
253  * simple supplementary global filter.
254  *
255  * Field Access Macros:
256  *
257  */
258 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN register field. */
259 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_LSB 0
260 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN register field. */
261 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_MSB 0
262 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN register field. */
263 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_WIDTH 1
264 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN register field value. */
265 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_SET_MSK 0x00000001
266 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN register field value. */
267 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_CLR_MSK 0xfffffffe
268 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN register field. */
269 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_RESET 0x0
270 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN field value from a register. */
271 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_GET(value) (((value) & 0x00000001) >> 0)
272 /* Produces a ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN register field value suitable for setting the register. */
273 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_SET(value) (((value) << 0) & 0x00000001)
274 
275 /*
276  * Field : TRACEEN
277  *
278  * Register field TraceEn enables the probe to send filtered packets (Trace) on the
279  * ObsTx observation output.
280  *
281  * Field Access Macros:
282  *
283  */
284 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN register field. */
285 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_LSB 1
286 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN register field. */
287 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_MSB 1
288 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN register field. */
289 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_WIDTH 1
290 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN register field value. */
291 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_SET_MSK 0x00000002
292 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN register field value. */
293 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_CLR_MSK 0xfffffffd
294 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN register field. */
295 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_RESET 0x0
296 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN field value from a register. */
297 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_GET(value) (((value) & 0x00000002) >> 1)
298 /* Produces a ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN register field value suitable for setting the register. */
299 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_SET(value) (((value) << 1) & 0x00000002)
300 
301 /*
302  * Field : PAYLOADEN
303  *
304  * Register field PayloadEn, when set to 1, enables traces to contain headers and
305  * payload. When set ot 0, only headers are reported.
306  *
307  * Field Access Macros:
308  *
309  */
310 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN register field. */
311 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_LSB 2
312 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN register field. */
313 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_MSB 2
314 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN register field. */
315 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_WIDTH 1
316 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN register field value. */
317 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_SET_MSK 0x00000004
318 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN register field value. */
319 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_CLR_MSK 0xfffffffb
320 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN register field. */
321 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_RESET 0x0
322 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN field value from a register. */
323 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_GET(value) (((value) & 0x00000004) >> 2)
324 /* Produces a ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN register field value suitable for setting the register. */
325 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_SET(value) (((value) << 2) & 0x00000004)
326 
327 /*
328  * Field : STATEN
329  *
330  * When set to 1, register field StatEn enables statistics profiling. The probe
331  * sendS statistics results to the output for signal ObsTx. All statistics counters
332  * are cleared when the StatEn bit goes from 0 to 1. When set to 0, counters are
333  * disabled.
334  *
335  * Field Access Macros:
336  *
337  */
338 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN register field. */
339 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_LSB 3
340 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN register field. */
341 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_MSB 3
342 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN register field. */
343 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_WIDTH 1
344 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN register field value. */
345 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_SET_MSK 0x00000008
346 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN register field value. */
347 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_CLR_MSK 0xfffffff7
348 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN register field. */
349 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_RESET 0x0
350 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN field value from a register. */
351 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_GET(value) (((value) & 0x00000008) >> 3)
352 /* Produces a ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN register field value suitable for setting the register. */
353 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_SET(value) (((value) << 3) & 0x00000008)
354 
355 /*
356  * Field : ALARMEN
357  *
358  * When set, register field AlarmEn enables the probe to collect alarm-related
359  * information. When the register field bit is null, both TraceAlarm and StatAlarm
360  * outputs are driven to 0.
361  *
362  * Field Access Macros:
363  *
364  */
365 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN register field. */
366 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_LSB 4
367 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN register field. */
368 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_MSB 4
369 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN register field. */
370 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_WIDTH 1
371 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN register field value. */
372 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_SET_MSK 0x00000010
373 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN register field value. */
374 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_CLR_MSK 0xffffffef
375 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN register field. */
376 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_RESET 0x0
377 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN field value from a register. */
378 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_GET(value) (((value) & 0x00000010) >> 4)
379 /* Produces a ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN register field value suitable for setting the register. */
380 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_SET(value) (((value) << 4) & 0x00000010)
381 
382 /*
383  * Field : STATCONDDUMP
384  *
385  * When set, register field StatCondDump enables the dump of a statistics frame to
386  * the range of counter values set for registers StatAlarmMin, StatAlarmMax, and
387  * AlarmMode. This field also renders register StatAlarmStatus inoperative. When
388  * parameter statisticsCounterAlarm is set to False, the StatCondDump register bit
389  * is reserved.
390  *
391  * Field Access Macros:
392  *
393  */
394 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP register field. */
395 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_LSB 5
396 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP register field. */
397 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_MSB 5
398 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP register field. */
399 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_WIDTH 1
400 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP register field value. */
401 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_SET_MSK 0x00000020
402 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP register field value. */
403 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_CLR_MSK 0xffffffdf
404 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP register field. */
405 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_RESET 0x0
406 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP field value from a register. */
407 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_GET(value) (((value) & 0x00000020) >> 5)
408 /* Produces a ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP register field value suitable for setting the register. */
409 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_SET(value) (((value) << 5) & 0x00000020)
410 
411 /*
412  * Field : INTRUSIVEMODE
413  *
414  * When set to 1, register field IntrusiveMode enables trace operation in Intrusive
415  * flow-control mode. When set to 0, the register enables trace operation in
416  * Overflow flow-control mode
417  *
418  * Field Access Macros:
419  *
420  */
421 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD register field. */
422 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_LSB 6
423 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD register field. */
424 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_MSB 6
425 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD register field. */
426 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_WIDTH 1
427 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD register field value. */
428 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_SET_MSK 0x00000040
429 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD register field value. */
430 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_CLR_MSK 0xffffffbf
431 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD register field. */
432 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_RESET 0x0
433 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD field value from a register. */
434 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_GET(value) (((value) & 0x00000040) >> 6)
435 /* Produces a ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD register field value suitable for setting the register. */
436 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_SET(value) (((value) << 6) & 0x00000040)
437 
438 /*
439  * Field : FILTBYTEALWAYSCHAINABLEEN
440  *
441  * When set to 0, filters are mapped to all statistic counters when counting bytes
442  * or enabled bytes. Therefore, only filter events mapped to even counters can be
443  * counted using a pair of chained counters.When set to 1, filters are mapped only
444  * to even statistic counters when counting bytes or enabled bytes. Thus events
445  * from any filter can be counted using a pair of chained counters.
446  *
447  * Field Access Macros:
448  *
449  */
450 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
451 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_LSB 7
452 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
453 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MSB 7
454 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
455 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_WIDTH 1
456 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field value. */
457 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET_MSK 0x00000080
458 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field value. */
459 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_CLR_MSK 0xffffff7f
460 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
461 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_RESET 0x0
462 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN field value from a register. */
463 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_GET(value) (((value) & 0x00000080) >> 7)
464 /* Produces a ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field value suitable for setting the register. */
465 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET(value) (((value) << 7) & 0x00000080)
466 
467 #ifndef __ASSEMBLY__
468 /*
469  * WARNING: The C register and register group struct declarations are provided for
470  * convenience and illustrative purposes. They should, however, be used with
471  * caution as the C language standard provides no guarantees about the alignment or
472  * atomicity of device memory accesses. The recommended practice for writing
473  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
474  * alt_write_word() functions.
475  *
476  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_MAINCTL.
477  */
478 struct ALT_NOC_MPU_DDR_T_PRB_MAINCTL_s
479 {
480  uint32_t ERREN : 1; /* ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN */
481  uint32_t TRACEEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN */
482  uint32_t PAYLOADEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN */
483  uint32_t STATEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN */
484  uint32_t ALARMEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN */
485  uint32_t STATCONDDUMP : 1; /* ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP */
486  uint32_t INTRUSIVEMODE : 1; /* ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD */
487  uint32_t FILTBYTEALWAYSCHAINABLEEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN */
488  uint32_t : 24; /* *UNDEFINED* */
489 };
490 
491 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_MAINCTL. */
492 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_MAINCTL_s ALT_NOC_MPU_DDR_T_PRB_MAINCTL_t;
493 #endif /* __ASSEMBLY__ */
494 
495 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL register. */
496 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_RESET 0x00000000
497 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_MAINCTL register from the beginning of the component. */
498 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_OFST 0x8
499 
500 /*
501  * Register : ddr_T_main_Probe_CfgCtl
502  *
503  * Register Layout
504  *
505  * Bits | Access | Reset | Description
506  * :-------|:-------|:--------|:------------------------------------
507  * [0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN
508  * [1] | R | 0x0 | ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT
509  * [31:2] | ??? | Unknown | *UNDEFINED*
510  *
511  */
512 /*
513  * Field : GLOBALEN
514  *
515  *
516  * Field Access Macros:
517  *
518  */
519 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN register field. */
520 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_LSB 0
521 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN register field. */
522 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_MSB 0
523 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN register field. */
524 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_WIDTH 1
525 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN register field value. */
526 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_SET_MSK 0x00000001
527 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN register field value. */
528 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_CLR_MSK 0xfffffffe
529 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN register field. */
530 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_RESET 0x0
531 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN field value from a register. */
532 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_GET(value) (((value) & 0x00000001) >> 0)
533 /* Produces a ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN register field value suitable for setting the register. */
534 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_SET(value) (((value) << 0) & 0x00000001)
535 
536 /*
537  * Field : ACTIVE
538  *
539  *
540  * Field Access Macros:
541  *
542  */
543 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT register field. */
544 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_LSB 1
545 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT register field. */
546 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_MSB 1
547 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT register field. */
548 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_WIDTH 1
549 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT register field value. */
550 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_SET_MSK 0x00000002
551 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT register field value. */
552 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_CLR_MSK 0xfffffffd
553 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT register field. */
554 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_RESET 0x0
555 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT field value from a register. */
556 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_GET(value) (((value) & 0x00000002) >> 1)
557 /* Produces a ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT register field value suitable for setting the register. */
558 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_SET(value) (((value) << 1) & 0x00000002)
559 
560 #ifndef __ASSEMBLY__
561 /*
562  * WARNING: The C register and register group struct declarations are provided for
563  * convenience and illustrative purposes. They should, however, be used with
564  * caution as the C language standard provides no guarantees about the alignment or
565  * atomicity of device memory accesses. The recommended practice for writing
566  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
567  * alt_write_word() functions.
568  *
569  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_CFGCTL.
570  */
571 struct ALT_NOC_MPU_DDR_T_PRB_CFGCTL_s
572 {
573  uint32_t GLOBALEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN */
574  const uint32_t ACTIVE : 1; /* ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT */
575  uint32_t : 30; /* *UNDEFINED* */
576 };
577 
578 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_CFGCTL. */
579 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_CFGCTL_s ALT_NOC_MPU_DDR_T_PRB_CFGCTL_t;
580 #endif /* __ASSEMBLY__ */
581 
582 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_CFGCTL register. */
583 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_RESET 0x00000000
584 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_CFGCTL register from the beginning of the component. */
585 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_OFST 0xc
586 
587 /*
588  * Register : ddr_T_main_Probe_FilterLut
589  *
590  *
591  * Register Layout
592  *
593  * Bits | Access | Reset | Description
594  * :--------|:-------|:--------|:------------------------------------
595  * [15:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT
596  * [31:16] | ??? | Unknown | *UNDEFINED*
597  *
598  */
599 /*
600  * Field : FILTERLUT
601  *
602  * Register FilterLut contains a look-up table that is used to combine filter
603  * outputs in order to trace packets. Packet tracing is enabled when the FilterLut
604  * bit of index (FNout ... F0out) is equal to 1.The number of bits in register
605  * FilterLut is determined by the setting for parameter nFilter, calculated as
606  * 2**nFilter.When parameter nFilter is set to None, FilterLut is reserved.
607  *
608  * Field Access Macros:
609  *
610  */
611 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT register field. */
612 #define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_LSB 0
613 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT register field. */
614 #define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_MSB 15
615 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT register field. */
616 #define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_WIDTH 16
617 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT register field value. */
618 #define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_SET_MSK 0x0000ffff
619 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT register field value. */
620 #define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_CLR_MSK 0xffff0000
621 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT register field. */
622 #define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_RESET 0x0
623 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT field value from a register. */
624 #define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_GET(value) (((value) & 0x0000ffff) >> 0)
625 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT register field value suitable for setting the register. */
626 #define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_SET(value) (((value) << 0) & 0x0000ffff)
627 
628 #ifndef __ASSEMBLY__
629 /*
630  * WARNING: The C register and register group struct declarations are provided for
631  * convenience and illustrative purposes. They should, however, be used with
632  * caution as the C language standard provides no guarantees about the alignment or
633  * atomicity of device memory accesses. The recommended practice for writing
634  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
635  * alt_write_word() functions.
636  *
637  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTLUT.
638  */
639 struct ALT_NOC_MPU_DDR_T_PRB_FLTLUT_s
640 {
641  uint32_t FILTERLUT : 16; /* ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT */
642  uint32_t : 16; /* *UNDEFINED* */
643 };
644 
645 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTLUT. */
646 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTLUT_s ALT_NOC_MPU_DDR_T_PRB_FLTLUT_t;
647 #endif /* __ASSEMBLY__ */
648 
649 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTLUT register. */
650 #define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_RESET 0x00000000
651 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTLUT register from the beginning of the component. */
652 #define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_OFST 0x14
653 
654 /*
655  * Register : ddr_T_main_Probe_TraceAlarmEn
656  *
657  *
658  * Register Layout
659  *
660  * Bits | Access | Reset | Description
661  * :-------|:-------|:--------|:------------------------------------------------
662  * [4:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN
663  * [31:5] | ??? | Unknown | *UNDEFINED*
664  *
665  */
666 /*
667  * Field : TRACEALARMEN
668  *
669  * Register TraceAlarmEn controls which lookup table or filter can set the
670  * TraceAlarm signal output once the trace alarm status is set. The number of bits
671  * in register TraceAlarmEn is determined by the value set for parameter nFilter +
672  * 1.Bit nFilter controls the lookup table output, and bits nFilter:0 control the
673  * corresponding filter output. When parameter nFilter is set to None, TraceAlarmEn
674  * is reserved.
675  *
676  * Field Access Macros:
677  *
678  */
679 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN register field. */
680 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_LSB 0
681 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN register field. */
682 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_MSB 4
683 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN register field. */
684 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_WIDTH 5
685 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN register field value. */
686 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_SET_MSK 0x0000001f
687 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN register field value. */
688 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_CLR_MSK 0xffffffe0
689 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN register field. */
690 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_RESET 0x0
691 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN field value from a register. */
692 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_GET(value) (((value) & 0x0000001f) >> 0)
693 /* Produces a ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN register field value suitable for setting the register. */
694 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_SET(value) (((value) << 0) & 0x0000001f)
695 
696 #ifndef __ASSEMBLY__
697 /*
698  * WARNING: The C register and register group struct declarations are provided for
699  * convenience and illustrative purposes. They should, however, be used with
700  * caution as the C language standard provides no guarantees about the alignment or
701  * atomicity of device memory accesses. The recommended practice for writing
702  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
703  * alt_write_word() functions.
704  *
705  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN.
706  */
707 struct ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_s
708 {
709  uint32_t TRACEALARMEN : 5; /* ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN */
710  uint32_t : 27; /* *UNDEFINED* */
711 };
712 
713 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN. */
714 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_s ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_t;
715 #endif /* __ASSEMBLY__ */
716 
717 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN register. */
718 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_RESET 0x00000000
719 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN register from the beginning of the component. */
720 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_OFST 0x18
721 
722 /*
723  * Register : ddr_T_main_Probe_TraceAlarmStatus
724  *
725  *
726  * Register Layout
727  *
728  * Bits | Access | Reset | Description
729  * :-------|:-------|:--------|:----------------------------------------------------
730  * [4:0] | R | 0x0 | ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT
731  * [31:5] | ??? | Unknown | *UNDEFINED*
732  *
733  */
734 /*
735  * Field : TRACEALARMSTATUS
736  *
737  * Register TraceAlarmStatus is a read-only register that indicates which lookup
738  * table or filter has been matched by a packet, independently of register
739  * TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is
740  * determined by the value set for parameter nFilter + 1.When nFilter is set to
741  * None, TraceAlarmStatus is reserved.
742  *
743  * Field Access Macros:
744  *
745  */
746 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT register field. */
747 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_LSB 0
748 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT register field. */
749 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_MSB 4
750 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT register field. */
751 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_WIDTH 5
752 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT register field value. */
753 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_SET_MSK 0x0000001f
754 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT register field value. */
755 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_CLR_MSK 0xffffffe0
756 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT register field. */
757 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_RESET 0x0
758 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT field value from a register. */
759 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_GET(value) (((value) & 0x0000001f) >> 0)
760 /* Produces a ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT register field value suitable for setting the register. */
761 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_SET(value) (((value) << 0) & 0x0000001f)
762 
763 #ifndef __ASSEMBLY__
764 /*
765  * WARNING: The C register and register group struct declarations are provided for
766  * convenience and illustrative purposes. They should, however, be used with
767  * caution as the C language standard provides no guarantees about the alignment or
768  * atomicity of device memory accesses. The recommended practice for writing
769  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
770  * alt_write_word() functions.
771  *
772  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT.
773  */
774 struct ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_s
775 {
776  const uint32_t TRACEALARMSTATUS : 5; /* ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT */
777  uint32_t : 27; /* *UNDEFINED* */
778 };
779 
780 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT. */
781 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_s ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_t;
782 #endif /* __ASSEMBLY__ */
783 
784 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT register. */
785 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_RESET 0x00000000
786 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT register from the beginning of the component. */
787 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_OFST 0x1c
788 
789 /*
790  * Register : ddr_T_main_Probe_TraceAlarmClr
791  *
792  *
793  * Register Layout
794  *
795  * Bits | Access | Reset | Description
796  * :-------|:-------|:--------|:--------------------------------------------------
797  * [4:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR
798  * [31:5] | ??? | Unknown | *UNDEFINED*
799  *
800  */
801 /*
802  * Field : TRACEALARMCLR
803  *
804  * Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in
805  * register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal
806  * to (nFilter + 1). When nFilter is set to 0, TraceAlarmClr is reserved.NOTE The
807  * written value is not stored in TraceAlarmClr. A read always returns 0.
808  *
809  * Field Access Macros:
810  *
811  */
812 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR register field. */
813 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_LSB 0
814 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR register field. */
815 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_MSB 4
816 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR register field. */
817 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_WIDTH 5
818 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR register field value. */
819 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_SET_MSK 0x0000001f
820 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR register field value. */
821 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_CLR_MSK 0xffffffe0
822 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR register field. */
823 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_RESET 0x0
824 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR field value from a register. */
825 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_GET(value) (((value) & 0x0000001f) >> 0)
826 /* Produces a ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR register field value suitable for setting the register. */
827 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_SET(value) (((value) << 0) & 0x0000001f)
828 
829 #ifndef __ASSEMBLY__
830 /*
831  * WARNING: The C register and register group struct declarations are provided for
832  * convenience and illustrative purposes. They should, however, be used with
833  * caution as the C language standard provides no guarantees about the alignment or
834  * atomicity of device memory accesses. The recommended practice for writing
835  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
836  * alt_write_word() functions.
837  *
838  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR.
839  */
840 struct ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_s
841 {
842  uint32_t TRACEALARMCLR : 5; /* ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR */
843  uint32_t : 27; /* *UNDEFINED* */
844 };
845 
846 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR. */
847 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_s ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_t;
848 #endif /* __ASSEMBLY__ */
849 
850 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR register. */
851 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_RESET 0x00000000
852 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR register from the beginning of the component. */
853 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_OFST 0x20
854 
855 /*
856  * Register : ddr_T_main_Probe_StatPeriod
857  *
858  *
859  * Register Layout
860  *
861  * Bits | Access | Reset | Description
862  * :-------|:-------|:--------|:--------------------------------------------
863  * [4:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD
864  * [31:5] | ??? | Unknown | *UNDEFINED*
865  *
866  */
867 /*
868  * Field : STATPERIOD
869  *
870  * Register StatPeriod is a 5-bit register that sets a period, within a range of 2
871  * cycles to 2 gigacycles, during which statistics are collected before being
872  * dumped automatically. Setting the register implicitly enables automatic mode
873  * operation for statistics collection. The period is calculated with the formula:
874  * N_Cycle = 2**StatPeriodWhen register StatPeriod is set to its default value 0,
875  * automatic dump mode is disabled, and register StatGo is activated for manual
876  * mode operation. Note: When parameter statisticsCollection is set to False,
877  * StatPeriod is reserved.
878  *
879  * Field Access Macros:
880  *
881  */
882 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD register field. */
883 #define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_LSB 0
884 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD register field. */
885 #define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_MSB 4
886 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD register field. */
887 #define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_WIDTH 5
888 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD register field value. */
889 #define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_SET_MSK 0x0000001f
890 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD register field value. */
891 #define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_CLR_MSK 0xffffffe0
892 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD register field. */
893 #define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_RESET 0x0
894 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD field value from a register. */
895 #define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_GET(value) (((value) & 0x0000001f) >> 0)
896 /* Produces a ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD register field value suitable for setting the register. */
897 #define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_SET(value) (((value) << 0) & 0x0000001f)
898 
899 #ifndef __ASSEMBLY__
900 /*
901  * WARNING: The C register and register group struct declarations are provided for
902  * convenience and illustrative purposes. They should, however, be used with
903  * caution as the C language standard provides no guarantees about the alignment or
904  * atomicity of device memory accesses. The recommended practice for writing
905  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
906  * alt_write_word() functions.
907  *
908  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_STATPERIOD.
909  */
910 struct ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_s
911 {
912  uint32_t STATPERIOD : 5; /* ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD */
913  uint32_t : 27; /* *UNDEFINED* */
914 };
915 
916 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_STATPERIOD. */
917 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_s ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_t;
918 #endif /* __ASSEMBLY__ */
919 
920 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_STATPERIOD register. */
921 #define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_RESET 0x00000000
922 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_STATPERIOD register from the beginning of the component. */
923 #define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_OFST 0x24
924 
925 /*
926  * Register : ddr_T_main_Probe_StatGo
927  *
928  *
929  * Register Layout
930  *
931  * Bits | Access | Reset | Description
932  * :-------|:-------|:--------|:------------------------------------
933  * [0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO
934  * [31:1] | ??? | Unknown | *UNDEFINED*
935  *
936  */
937 /*
938  * Field : STATGO
939  *
940  * Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The
941  * register is active when statistics collection operates in manual mode, that is,
942  * when register StatPeriod is set to 0.NOTE The written value is not stored in
943  * StatGo. A read always returns 0.
944  *
945  * Field Access Macros:
946  *
947  */
948 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO register field. */
949 #define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_LSB 0
950 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO register field. */
951 #define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_MSB 0
952 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO register field. */
953 #define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_WIDTH 1
954 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO register field value. */
955 #define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_SET_MSK 0x00000001
956 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO register field value. */
957 #define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_CLR_MSK 0xfffffffe
958 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO register field. */
959 #define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_RESET 0x0
960 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO field value from a register. */
961 #define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_GET(value) (((value) & 0x00000001) >> 0)
962 /* Produces a ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO register field value suitable for setting the register. */
963 #define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_SET(value) (((value) << 0) & 0x00000001)
964 
965 #ifndef __ASSEMBLY__
966 /*
967  * WARNING: The C register and register group struct declarations are provided for
968  * convenience and illustrative purposes. They should, however, be used with
969  * caution as the C language standard provides no guarantees about the alignment or
970  * atomicity of device memory accesses. The recommended practice for writing
971  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
972  * alt_write_word() functions.
973  *
974  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_STATGO.
975  */
976 struct ALT_NOC_MPU_DDR_T_PRB_STATGO_s
977 {
978  uint32_t STATGO : 1; /* ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO */
979  uint32_t : 31; /* *UNDEFINED* */
980 };
981 
982 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_STATGO. */
983 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_STATGO_s ALT_NOC_MPU_DDR_T_PRB_STATGO_t;
984 #endif /* __ASSEMBLY__ */
985 
986 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_STATGO register. */
987 #define ALT_NOC_MPU_DDR_T_PRB_STATGO_RESET 0x00000000
988 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_STATGO register from the beginning of the component. */
989 #define ALT_NOC_MPU_DDR_T_PRB_STATGO_OFST 0x28
990 
991 /*
992  * Register : ddr_T_main_Probe_StatAlarmMin
993  *
994  *
995  * Register Layout
996  *
997  * Bits | Access | Reset | Description
998  * :-------|:-------|:------|:------------------------------------------------
999  * [31:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN
1000  *
1001  */
1002 /*
1003  * Field : STATALARMMIN
1004  *
1005  * Register StatAlarmMin contains the minimum count value used in statistics alarm
1006  * comparisons. The number of bits is equal to twice the value set forparameter
1007  * wStatisticsCounter. When parameter statisticsCounterAlarm is set to False,
1008  * StatAlarmMin is reserved.
1009  *
1010  * Field Access Macros:
1011  *
1012  */
1013 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN register field. */
1014 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_LSB 0
1015 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN register field. */
1016 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_MSB 31
1017 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN register field. */
1018 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_WIDTH 32
1019 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN register field value. */
1020 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_SET_MSK 0xffffffff
1021 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN register field value. */
1022 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_CLR_MSK 0x00000000
1023 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN register field. */
1024 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_RESET 0x0
1025 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN field value from a register. */
1026 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_GET(value) (((value) & 0xffffffff) >> 0)
1027 /* Produces a ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN register field value suitable for setting the register. */
1028 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_SET(value) (((value) << 0) & 0xffffffff)
1029 
1030 #ifndef __ASSEMBLY__
1031 /*
1032  * WARNING: The C register and register group struct declarations are provided for
1033  * convenience and illustrative purposes. They should, however, be used with
1034  * caution as the C language standard provides no guarantees about the alignment or
1035  * atomicity of device memory accesses. The recommended practice for writing
1036  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1037  * alt_write_word() functions.
1038  *
1039  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN.
1040  */
1041 struct ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_s
1042 {
1043  uint32_t STATALARMMIN : 32; /* ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN */
1044 };
1045 
1046 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN. */
1047 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_s ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_t;
1048 #endif /* __ASSEMBLY__ */
1049 
1050 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN register. */
1051 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_RESET 0x00000000
1052 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN register from the beginning of the component. */
1053 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_OFST 0x2c
1054 
1055 /*
1056  * Register : ddr_T_main_Probe_StatAlarmMax
1057  *
1058  *
1059  * Register Layout
1060  *
1061  * Bits | Access | Reset | Description
1062  * :-------|:-------|:------|:------------------------------------------------
1063  * [31:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX
1064  *
1065  */
1066 /*
1067  * Field : STATALARMMAX
1068  *
1069  * Register StatAlarmMax contains the maximum count value used in statistics alarm
1070  * comparisons.The number of bits is equal to twice the value set for parameter
1071  * wStatisticsCounter. When parameter statisticsCounterAlarm is set to False,
1072  * StatAlarmMax is reserved.
1073  *
1074  * Field Access Macros:
1075  *
1076  */
1077 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX register field. */
1078 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_LSB 0
1079 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX register field. */
1080 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_MSB 31
1081 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX register field. */
1082 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_WIDTH 32
1083 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX register field value. */
1084 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_SET_MSK 0xffffffff
1085 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX register field value. */
1086 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_CLR_MSK 0x00000000
1087 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX register field. */
1088 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_RESET 0x0
1089 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX field value from a register. */
1090 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_GET(value) (((value) & 0xffffffff) >> 0)
1091 /* Produces a ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX register field value suitable for setting the register. */
1092 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_SET(value) (((value) << 0) & 0xffffffff)
1093 
1094 #ifndef __ASSEMBLY__
1095 /*
1096  * WARNING: The C register and register group struct declarations are provided for
1097  * convenience and illustrative purposes. They should, however, be used with
1098  * caution as the C language standard provides no guarantees about the alignment or
1099  * atomicity of device memory accesses. The recommended practice for writing
1100  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1101  * alt_write_word() functions.
1102  *
1103  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX.
1104  */
1105 struct ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_s
1106 {
1107  uint32_t STATALARMMAX : 32; /* ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX */
1108 };
1109 
1110 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX. */
1111 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_s ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_t;
1112 #endif /* __ASSEMBLY__ */
1113 
1114 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX register. */
1115 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_RESET 0x00000000
1116 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX register from the beginning of the component. */
1117 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_OFST 0x30
1118 
1119 /*
1120  * Register : ddr_T_main_Probe_StatAlarmStatus
1121  *
1122  *
1123  * Register Layout
1124  *
1125  * Bits | Access | Reset | Description
1126  * :-------|:-------|:--------|:--------------------------------------------------
1127  * [0] | R | 0x0 | ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT
1128  * [31:1] | ??? | Unknown | *UNDEFINED*
1129  *
1130  */
1131 /*
1132  * Field : STATALARMSTATUS
1133  *
1134  * Register StatAlarmStatus is a read-only 1-bit register indicating that at least
1135  * one statistics counter has exceeded the programmed values for registers
1136  * StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values
1137  * stored in register MainCtl fields StatAlarmStatus and AlarmEn. When parameter
1138  * statisticsCounterAlarm is set to False, StatAlarmStatus is reserved.
1139  *
1140  * Field Access Macros:
1141  *
1142  */
1143 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT register field. */
1144 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_LSB 0
1145 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT register field. */
1146 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_MSB 0
1147 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT register field. */
1148 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_WIDTH 1
1149 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT register field value. */
1150 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_SET_MSK 0x00000001
1151 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT register field value. */
1152 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_CLR_MSK 0xfffffffe
1153 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT register field. */
1154 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_RESET 0x0
1155 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT field value from a register. */
1156 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_GET(value) (((value) & 0x00000001) >> 0)
1157 /* Produces a ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT register field value suitable for setting the register. */
1158 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_SET(value) (((value) << 0) & 0x00000001)
1159 
1160 #ifndef __ASSEMBLY__
1161 /*
1162  * WARNING: The C register and register group struct declarations are provided for
1163  * convenience and illustrative purposes. They should, however, be used with
1164  * caution as the C language standard provides no guarantees about the alignment or
1165  * atomicity of device memory accesses. The recommended practice for writing
1166  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1167  * alt_write_word() functions.
1168  *
1169  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT.
1170  */
1171 struct ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_s
1172 {
1173  const uint32_t STATALARMSTATUS : 1; /* ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT */
1174  uint32_t : 31; /* *UNDEFINED* */
1175 };
1176 
1177 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT. */
1178 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_s ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_t;
1179 #endif /* __ASSEMBLY__ */
1180 
1181 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT register. */
1182 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_RESET 0x00000000
1183 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT register from the beginning of the component. */
1184 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_OFST 0x34
1185 
1186 /*
1187  * Register : ddr_T_main_Probe_StatAlarmClr
1188  *
1189  *
1190  * Register Layout
1191  *
1192  * Bits | Access | Reset | Description
1193  * :-------|:-------|:--------|:------------------------------------------------
1194  * [0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR
1195  * [31:1] | ??? | Unknown | *UNDEFINED*
1196  *
1197  */
1198 /*
1199  * Field : STATALARMCLR
1200  *
1201  * Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears
1202  * the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to
1203  * False, StatAlarmClr is reserved.NOTE The written value is not stored in
1204  * StatAlarmClr. A read always returns 0.
1205  *
1206  * Field Access Macros:
1207  *
1208  */
1209 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR register field. */
1210 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_LSB 0
1211 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR register field. */
1212 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_MSB 0
1213 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR register field. */
1214 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_WIDTH 1
1215 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR register field value. */
1216 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_SET_MSK 0x00000001
1217 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR register field value. */
1218 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_CLR_MSK 0xfffffffe
1219 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR register field. */
1220 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_RESET 0x0
1221 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR field value from a register. */
1222 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_GET(value) (((value) & 0x00000001) >> 0)
1223 /* Produces a ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR register field value suitable for setting the register. */
1224 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_SET(value) (((value) << 0) & 0x00000001)
1225 
1226 #ifndef __ASSEMBLY__
1227 /*
1228  * WARNING: The C register and register group struct declarations are provided for
1229  * convenience and illustrative purposes. They should, however, be used with
1230  * caution as the C language standard provides no guarantees about the alignment or
1231  * atomicity of device memory accesses. The recommended practice for writing
1232  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1233  * alt_write_word() functions.
1234  *
1235  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR.
1236  */
1237 struct ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_s
1238 {
1239  uint32_t STATALARMCLR : 1; /* ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR */
1240  uint32_t : 31; /* *UNDEFINED* */
1241 };
1242 
1243 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR. */
1244 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_s ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_t;
1245 #endif /* __ASSEMBLY__ */
1246 
1247 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR register. */
1248 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_RESET 0x00000000
1249 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR register from the beginning of the component. */
1250 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_OFST 0x38
1251 
1252 /*
1253  * Register : ddr_T_main_Probe_StatAlarmEn
1254  *
1255  *
1256  * Register Layout
1257  *
1258  * Bits | Access | Reset | Description
1259  * :-------|:-------|:--------|:----------------------------------------------
1260  * [0] | RW | 0x1 | ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN
1261  * [31:1] | ??? | Unknown | *UNDEFINED*
1262  *
1263  */
1264 /*
1265  * Field : STATALARMEN
1266  *
1267  * Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and
1268  * CtiTrigOut(1) signal interrupts.
1269  *
1270  * Field Access Macros:
1271  *
1272  */
1273 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN register field. */
1274 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_LSB 0
1275 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN register field. */
1276 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_MSB 0
1277 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN register field. */
1278 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_WIDTH 1
1279 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN register field value. */
1280 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_SET_MSK 0x00000001
1281 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN register field value. */
1282 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_CLR_MSK 0xfffffffe
1283 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN register field. */
1284 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_RESET 0x1
1285 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN field value from a register. */
1286 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_GET(value) (((value) & 0x00000001) >> 0)
1287 /* Produces a ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN register field value suitable for setting the register. */
1288 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_SET(value) (((value) << 0) & 0x00000001)
1289 
1290 #ifndef __ASSEMBLY__
1291 /*
1292  * WARNING: The C register and register group struct declarations are provided for
1293  * convenience and illustrative purposes. They should, however, be used with
1294  * caution as the C language standard provides no guarantees about the alignment or
1295  * atomicity of device memory accesses. The recommended practice for writing
1296  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1297  * alt_write_word() functions.
1298  *
1299  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_STATALARMEN.
1300  */
1301 struct ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_s
1302 {
1303  uint32_t STATALARMEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN */
1304  uint32_t : 31; /* *UNDEFINED* */
1305 };
1306 
1307 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_STATALARMEN. */
1308 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_s ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_t;
1309 #endif /* __ASSEMBLY__ */
1310 
1311 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_STATALARMEN register. */
1312 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_RESET 0x00000001
1313 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_STATALARMEN register from the beginning of the component. */
1314 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_OFST 0x3c
1315 
1316 /*
1317  * Register : ddr_T_main_Probe_Filters_0_RouteIdBase
1318  *
1319  *
1320  * Register Layout
1321  *
1322  * Bits | Access | Reset | Description
1323  * :--------|:-------|:--------|:------------------------------------------------------------
1324  * [18:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE
1325  * [31:19] | ??? | Unknown | *UNDEFINED*
1326  *
1327  */
1328 /*
1329  * Field : FILTERS_0_ROUTEIDBASE
1330  *
1331  * Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to
1332  * filter packets.
1333  *
1334  * Field Access Macros:
1335  *
1336  */
1337 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field. */
1338 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_LSB 0
1339 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field. */
1340 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_MSB 18
1341 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field. */
1342 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_WIDTH 19
1343 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field value. */
1344 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_SET_MSK 0x0007ffff
1345 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field value. */
1346 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_CLR_MSK 0xfff80000
1347 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field. */
1348 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_RESET 0x0
1349 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE field value from a register. */
1350 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_GET(value) (((value) & 0x0007ffff) >> 0)
1351 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field value suitable for setting the register. */
1352 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_SET(value) (((value) << 0) & 0x0007ffff)
1353 
1354 #ifndef __ASSEMBLY__
1355 /*
1356  * WARNING: The C register and register group struct declarations are provided for
1357  * convenience and illustrative purposes. They should, however, be used with
1358  * caution as the C language standard provides no guarantees about the alignment or
1359  * atomicity of device memory accesses. The recommended practice for writing
1360  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1361  * alt_write_word() functions.
1362  *
1363  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE.
1364  */
1365 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_s
1366 {
1367  uint32_t FILTERS_0_ROUTEIDBASE : 19; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE */
1368  uint32_t : 13; /* *UNDEFINED* */
1369 };
1370 
1371 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE. */
1372 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_t;
1373 #endif /* __ASSEMBLY__ */
1374 
1375 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE register. */
1376 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_RESET 0x00000000
1377 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE register from the beginning of the component. */
1378 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_OFST 0x44
1379 
1380 /*
1381  * Register : ddr_T_main_Probe_Filters_0_RouteIdMask
1382  *
1383  *
1384  * Register Layout
1385  *
1386  * Bits | Access | Reset | Description
1387  * :--------|:-------|:--------|:----------------------------------------------------------
1388  * [18:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK
1389  * [31:19] | ??? | Unknown | *UNDEFINED*
1390  *
1391  */
1392 /*
1393  * Field : FILTERS_0_ROUTEIDMASK
1394  *
1395  * Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter
1396  * packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &
1397  * RouteIdMask = RouteIdBase & RouteIdMask.
1398  *
1399  * Field Access Macros:
1400  *
1401  */
1402 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field. */
1403 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_LSB 0
1404 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field. */
1405 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_MSB 18
1406 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field. */
1407 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_WIDTH 19
1408 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field value. */
1409 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_SET_MSK 0x0007ffff
1410 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field value. */
1411 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_CLR_MSK 0xfff80000
1412 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field. */
1413 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_RESET 0x0
1414 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK field value from a register. */
1415 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_GET(value) (((value) & 0x0007ffff) >> 0)
1416 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field value suitable for setting the register. */
1417 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_SET(value) (((value) << 0) & 0x0007ffff)
1418 
1419 #ifndef __ASSEMBLY__
1420 /*
1421  * WARNING: The C register and register group struct declarations are provided for
1422  * convenience and illustrative purposes. They should, however, be used with
1423  * caution as the C language standard provides no guarantees about the alignment or
1424  * atomicity of device memory accesses. The recommended practice for writing
1425  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1426  * alt_write_word() functions.
1427  *
1428  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK.
1429  */
1430 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_s
1431 {
1432  uint32_t FILTERS_0_ROUTEIDMASK : 19; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK */
1433  uint32_t : 13; /* *UNDEFINED* */
1434 };
1435 
1436 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK. */
1437 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_s ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_t;
1438 #endif /* __ASSEMBLY__ */
1439 
1440 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK register. */
1441 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_RESET 0x00000000
1442 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK register from the beginning of the component. */
1443 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_OFST 0x48
1444 
1445 /*
1446  * Register : ddr_T_main_Probe_Filters_0_AddrBase_Low
1447  *
1448  *
1449  * Register Layout
1450  *
1451  * Bits | Access | Reset | Description
1452  * :-------|:-------|:------|:--------------------------------------------------------------
1453  * [31:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW
1454  *
1455  */
1456 /*
1457  * Field : FILTERS_0_ADDRBASE_LOW
1458  *
1459  * Address LSB register.
1460  *
1461  * Field Access Macros:
1462  *
1463  */
1464 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field. */
1465 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_LSB 0
1466 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field. */
1467 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_MSB 31
1468 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field. */
1469 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_WIDTH 32
1470 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field value. */
1471 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_SET_MSK 0xffffffff
1472 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field value. */
1473 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_CLR_MSK 0x00000000
1474 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field. */
1475 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_RESET 0x0
1476 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW field value from a register. */
1477 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
1478 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field value suitable for setting the register. */
1479 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
1480 
1481 #ifndef __ASSEMBLY__
1482 /*
1483  * WARNING: The C register and register group struct declarations are provided for
1484  * convenience and illustrative purposes. They should, however, be used with
1485  * caution as the C language standard provides no guarantees about the alignment or
1486  * atomicity of device memory accesses. The recommended practice for writing
1487  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1488  * alt_write_word() functions.
1489  *
1490  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW.
1491  */
1492 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_s
1493 {
1494  uint32_t FILTERS_0_ADDRBASE_LOW : 32; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW */
1495 };
1496 
1497 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW. */
1498 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_s ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_t;
1499 #endif /* __ASSEMBLY__ */
1500 
1501 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW register. */
1502 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_RESET 0x00000000
1503 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW register from the beginning of the component. */
1504 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_OFST 0x4c
1505 
1506 /*
1507  * Register : ddr_T_main_Probe_Filters_0_WindowSize
1508  *
1509  *
1510  * Register Layout
1511  *
1512  * Bits | Access | Reset | Description
1513  * :-------|:-------|:--------|:----------------------------------------------------------
1514  * [5:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE
1515  * [31:6] | ??? | Unknown | *UNDEFINED*
1516  *
1517  */
1518 /*
1519  * Field : FILTERS_0_WINDOWSIZE
1520  *
1521  * Register WindowSize contains the encoded address mask used to filter packets.
1522  * The effective Mask value is equal to ~(2max(WindowSize, packet.Len) - 1). A
1523  * packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows
1524  * filteringof packets having an intersection with the AddrBase/WindowSize burst
1525  * aligned region, even if the region is smaller than the packet.
1526  *
1527  * Field Access Macros:
1528  *
1529  */
1530 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field. */
1531 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_LSB 0
1532 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field. */
1533 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_MSB 5
1534 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field. */
1535 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_WIDTH 6
1536 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field value. */
1537 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_SET_MSK 0x0000003f
1538 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field value. */
1539 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_CLR_MSK 0xffffffc0
1540 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field. */
1541 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_RESET 0x0
1542 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE field value from a register. */
1543 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
1544 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field value suitable for setting the register. */
1545 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
1546 
1547 #ifndef __ASSEMBLY__
1548 /*
1549  * WARNING: The C register and register group struct declarations are provided for
1550  * convenience and illustrative purposes. They should, however, be used with
1551  * caution as the C language standard provides no guarantees about the alignment or
1552  * atomicity of device memory accesses. The recommended practice for writing
1553  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1554  * alt_write_word() functions.
1555  *
1556  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE.
1557  */
1558 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_s
1559 {
1560  uint32_t FILTERS_0_WINDOWSIZE : 6; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE */
1561  uint32_t : 26; /* *UNDEFINED* */
1562 };
1563 
1564 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE. */
1565 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_t;
1566 #endif /* __ASSEMBLY__ */
1567 
1568 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE register. */
1569 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_RESET 0x00000000
1570 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE register from the beginning of the component. */
1571 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_OFST 0x54
1572 
1573 /*
1574  * Register : ddr_T_main_Probe_Filters_0_SecurityBase
1575  *
1576  *
1577  * Register Layout
1578  *
1579  * Bits | Access | Reset | Description
1580  * :-------|:-------|:--------|:--------------------------------------------------------------
1581  * [2:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE
1582  * [31:3] | ??? | Unknown | *UNDEFINED*
1583  *
1584  */
1585 /*
1586  * Field : FILTERS_0_SECURITYBASE
1587  *
1588  * Register SecurityBase contains the security base used to filter packets.
1589  *
1590  * Field Access Macros:
1591  *
1592  */
1593 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field. */
1594 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_LSB 0
1595 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field. */
1596 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_MSB 2
1597 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field. */
1598 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_WIDTH 3
1599 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field value. */
1600 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_SET_MSK 0x00000007
1601 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field value. */
1602 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_CLR_MSK 0xfffffff8
1603 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field. */
1604 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_RESET 0x0
1605 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE field value from a register. */
1606 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
1607 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field value suitable for setting the register. */
1608 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
1609 
1610 #ifndef __ASSEMBLY__
1611 /*
1612  * WARNING: The C register and register group struct declarations are provided for
1613  * convenience and illustrative purposes. They should, however, be used with
1614  * caution as the C language standard provides no guarantees about the alignment or
1615  * atomicity of device memory accesses. The recommended practice for writing
1616  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1617  * alt_write_word() functions.
1618  *
1619  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE.
1620  */
1621 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_s
1622 {
1623  uint32_t FILTERS_0_SECURITYBASE : 3; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE */
1624  uint32_t : 29; /* *UNDEFINED* */
1625 };
1626 
1627 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE. */
1628 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_t;
1629 #endif /* __ASSEMBLY__ */
1630 
1631 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE register. */
1632 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_RESET 0x00000000
1633 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE register from the beginning of the component. */
1634 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_OFST 0x58
1635 
1636 /*
1637  * Register : ddr_T_main_Probe_Filters_0_SecurityMask
1638  *
1639  *
1640  * Register Layout
1641  *
1642  * Bits | Access | Reset | Description
1643  * :-------|:-------|:--------|:------------------------------------------------------------
1644  * [2:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK
1645  * [31:3] | ??? | Unknown | *UNDEFINED*
1646  *
1647  */
1648 /*
1649  * Field : FILTERS_0_SECURITYMASK
1650  *
1651  * Register SecurityMask is contains the security mask used to filter packets. A
1652  * packet is a candidate when: packet.Security & SecurityMask = SecurityBase &
1653  * SecurityMasks.
1654  *
1655  * Field Access Macros:
1656  *
1657  */
1658 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field. */
1659 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_LSB 0
1660 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field. */
1661 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_MSB 2
1662 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field. */
1663 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_WIDTH 3
1664 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field value. */
1665 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_SET_MSK 0x00000007
1666 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field value. */
1667 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_CLR_MSK 0xfffffff8
1668 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field. */
1669 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_RESET 0x0
1670 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK field value from a register. */
1671 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
1672 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field value suitable for setting the register. */
1673 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
1674 
1675 #ifndef __ASSEMBLY__
1676 /*
1677  * WARNING: The C register and register group struct declarations are provided for
1678  * convenience and illustrative purposes. They should, however, be used with
1679  * caution as the C language standard provides no guarantees about the alignment or
1680  * atomicity of device memory accesses. The recommended practice for writing
1681  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1682  * alt_write_word() functions.
1683  *
1684  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK.
1685  */
1686 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_s
1687 {
1688  uint32_t FILTERS_0_SECURITYMASK : 3; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK */
1689  uint32_t : 29; /* *UNDEFINED* */
1690 };
1691 
1692 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK. */
1693 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_s ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_t;
1694 #endif /* __ASSEMBLY__ */
1695 
1696 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK register. */
1697 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_RESET 0x00000000
1698 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK register from the beginning of the component. */
1699 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_OFST 0x5c
1700 
1701 /*
1702  * Register : ddr_T_main_Probe_Filters_0_Opcode
1703  *
1704  * Packet Probe register Opcode is a 4-bit register that selects candidate packets
1705  * based on packet opcodes (0 disables the filter):
1706  *
1707  * Register Layout
1708  *
1709  * Bits | Access | Reset | Description
1710  * :-------|:-------|:--------|:-------------------------------------------
1711  * [0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN
1712  * [1] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN
1713  * [2] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN
1714  * [3] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN
1715  * [31:4] | ??? | Unknown | *UNDEFINED*
1716  *
1717  */
1718 /*
1719  * Field : RDEN
1720  *
1721  * Selects RD packets.
1722  *
1723  * Field Access Macros:
1724  *
1725  */
1726 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN register field. */
1727 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_LSB 0
1728 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN register field. */
1729 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_MSB 0
1730 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN register field. */
1731 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_WIDTH 1
1732 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN register field value. */
1733 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_SET_MSK 0x00000001
1734 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN register field value. */
1735 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_CLR_MSK 0xfffffffe
1736 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN register field. */
1737 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_RESET 0x0
1738 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN field value from a register. */
1739 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
1740 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN register field value suitable for setting the register. */
1741 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
1742 
1743 /*
1744  * Field : WREN
1745  *
1746  * Selects WR packets.
1747  *
1748  * Field Access Macros:
1749  *
1750  */
1751 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN register field. */
1752 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_LSB 1
1753 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN register field. */
1754 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_MSB 1
1755 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN register field. */
1756 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_WIDTH 1
1757 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN register field value. */
1758 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_SET_MSK 0x00000002
1759 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN register field value. */
1760 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_CLR_MSK 0xfffffffd
1761 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN register field. */
1762 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_RESET 0x0
1763 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN field value from a register. */
1764 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
1765 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN register field value suitable for setting the register. */
1766 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
1767 
1768 /*
1769  * Field : LOCKEN
1770  *
1771  * Selects RDX-WR, RDL, WRC and Linked sequence.
1772  *
1773  * Field Access Macros:
1774  *
1775  */
1776 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN register field. */
1777 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_LSB 2
1778 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN register field. */
1779 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_MSB 2
1780 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN register field. */
1781 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_WIDTH 1
1782 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN register field value. */
1783 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_SET_MSK 0x00000004
1784 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN register field value. */
1785 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
1786 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN register field. */
1787 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_RESET 0x0
1788 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN field value from a register. */
1789 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
1790 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN register field value suitable for setting the register. */
1791 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
1792 
1793 /*
1794  * Field : URGEN
1795  *
1796  * Selects URG packets (urgency).
1797  *
1798  * Field Access Macros:
1799  *
1800  */
1801 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN register field. */
1802 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_LSB 3
1803 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN register field. */
1804 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_MSB 3
1805 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN register field. */
1806 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_WIDTH 1
1807 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN register field value. */
1808 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_SET_MSK 0x00000008
1809 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN register field value. */
1810 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_CLR_MSK 0xfffffff7
1811 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN register field. */
1812 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_RESET 0x0
1813 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN field value from a register. */
1814 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
1815 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN register field value suitable for setting the register. */
1816 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
1817 
1818 #ifndef __ASSEMBLY__
1819 /*
1820  * WARNING: The C register and register group struct declarations are provided for
1821  * convenience and illustrative purposes. They should, however, be used with
1822  * caution as the C language standard provides no guarantees about the alignment or
1823  * atomicity of device memory accesses. The recommended practice for writing
1824  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1825  * alt_write_word() functions.
1826  *
1827  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE.
1828  */
1829 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_s
1830 {
1831  uint32_t RDEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN */
1832  uint32_t WREN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN */
1833  uint32_t LOCKEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN */
1834  uint32_t URGEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN */
1835  uint32_t : 28; /* *UNDEFINED* */
1836 };
1837 
1838 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE. */
1839 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_t;
1840 #endif /* __ASSEMBLY__ */
1841 
1842 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE register. */
1843 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RESET 0x00000000
1844 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE register from the beginning of the component. */
1845 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_OFST 0x60
1846 
1847 /*
1848  * Register : ddr_T_main_Probe_Filters_0_Status
1849  *
1850  * Register Status is 2-bit register that selects candidate packets based on packet
1851  * status.
1852  *
1853  * Register Layout
1854  *
1855  * Bits | Access | Reset | Description
1856  * :-------|:-------|:--------|:----------------------------------------
1857  * [0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN
1858  * [1] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN
1859  * [31:2] | ??? | Unknown | *UNDEFINED*
1860  *
1861  */
1862 /*
1863  * Field : REQEN
1864  *
1865  * Selects REQ status packets.
1866  *
1867  * Field Access Macros:
1868  *
1869  */
1870 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN register field. */
1871 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_LSB 0
1872 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN register field. */
1873 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_MSB 0
1874 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN register field. */
1875 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_WIDTH 1
1876 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN register field value. */
1877 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_SET_MSK 0x00000001
1878 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN register field value. */
1879 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_CLR_MSK 0xfffffffe
1880 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN register field. */
1881 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_RESET 0x0
1882 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN field value from a register. */
1883 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_GET(value) (((value) & 0x00000001) >> 0)
1884 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN register field value suitable for setting the register. */
1885 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_SET(value) (((value) << 0) & 0x00000001)
1886 
1887 /*
1888  * Field : RSPEN
1889  *
1890  * Selects RSP and FAIL-CONT status packets.
1891  *
1892  * Field Access Macros:
1893  *
1894  */
1895 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN register field. */
1896 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_LSB 1
1897 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN register field. */
1898 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_MSB 1
1899 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN register field. */
1900 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_WIDTH 1
1901 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN register field value. */
1902 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_SET_MSK 0x00000002
1903 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN register field value. */
1904 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_CLR_MSK 0xfffffffd
1905 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN register field. */
1906 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_RESET 0x0
1907 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN field value from a register. */
1908 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
1909 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN register field value suitable for setting the register. */
1910 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_SET(value) (((value) << 1) & 0x00000002)
1911 
1912 #ifndef __ASSEMBLY__
1913 /*
1914  * WARNING: The C register and register group struct declarations are provided for
1915  * convenience and illustrative purposes. They should, however, be used with
1916  * caution as the C language standard provides no guarantees about the alignment or
1917  * atomicity of device memory accesses. The recommended practice for writing
1918  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1919  * alt_write_word() functions.
1920  *
1921  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT.
1922  */
1923 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_s
1924 {
1925  uint32_t REQEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN */
1926  uint32_t RSPEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN */
1927  uint32_t : 30; /* *UNDEFINED* */
1928 };
1929 
1930 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT. */
1931 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_s ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_t;
1932 #endif /* __ASSEMBLY__ */
1933 
1934 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT register. */
1935 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RESET 0x00000000
1936 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT register from the beginning of the component. */
1937 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_OFST 0x64
1938 
1939 /*
1940  * Register : ddr_T_main_Probe_Filters_0_Length
1941  *
1942  *
1943  * Register Layout
1944  *
1945  * Bits | Access | Reset | Description
1946  * :-------|:-------|:--------|:--------------------------------------------
1947  * [3:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN
1948  * [31:4] | ??? | Unknown | *UNDEFINED*
1949  *
1950  */
1951 /*
1952  * Field : FILTERS_0_LENGTH
1953  *
1954  * Register Length is 4-bit register that selects candidate packets if their number
1955  * of bytes is less than or equal to 2**Length.
1956  *
1957  * Field Access Macros:
1958  *
1959  */
1960 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN register field. */
1961 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_LSB 0
1962 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN register field. */
1963 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_MSB 3
1964 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN register field. */
1965 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_WIDTH 4
1966 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN register field value. */
1967 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_SET_MSK 0x0000000f
1968 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN register field value. */
1969 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_CLR_MSK 0xfffffff0
1970 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN register field. */
1971 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_RESET 0x0
1972 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN field value from a register. */
1973 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_GET(value) (((value) & 0x0000000f) >> 0)
1974 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN register field value suitable for setting the register. */
1975 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_SET(value) (((value) << 0) & 0x0000000f)
1976 
1977 #ifndef __ASSEMBLY__
1978 /*
1979  * WARNING: The C register and register group struct declarations are provided for
1980  * convenience and illustrative purposes. They should, however, be used with
1981  * caution as the C language standard provides no guarantees about the alignment or
1982  * atomicity of device memory accesses. The recommended practice for writing
1983  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1984  * alt_write_word() functions.
1985  *
1986  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN.
1987  */
1988 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_s
1989 {
1990  uint32_t FILTERS_0_LENGTH : 4; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN */
1991  uint32_t : 28; /* *UNDEFINED* */
1992 };
1993 
1994 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN. */
1995 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_s ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_t;
1996 #endif /* __ASSEMBLY__ */
1997 
1998 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN register. */
1999 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_RESET 0x00000000
2000 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN register from the beginning of the component. */
2001 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_OFST 0x68
2002 
2003 /*
2004  * Register : ddr_T_main_Probe_Filters_0_Urgency
2005  *
2006  *
2007  * Register Layout
2008  *
2009  * Bits | Access | Reset | Description
2010  * :-------|:-------|:--------|:----------------------------------------------------
2011  * [1:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY
2012  * [31:2] | ??? | Unknown | *UNDEFINED*
2013  *
2014  */
2015 /*
2016  * Field : FILTERS_0_URGENCY
2017  *
2018  * Register Urgency contains the minimum urgency level used to filter packets. A
2019  * packet is a candidate when its socket urgency is greater than or equal to the
2020  * urgency specified in the register.
2021  *
2022  * Field Access Macros:
2023  *
2024  */
2025 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY register field. */
2026 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_LSB 0
2027 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY register field. */
2028 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_MSB 1
2029 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY register field. */
2030 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_WIDTH 2
2031 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY register field value. */
2032 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_SET_MSK 0x00000003
2033 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY register field value. */
2034 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_CLR_MSK 0xfffffffc
2035 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY register field. */
2036 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_RESET 0x0
2037 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY field value from a register. */
2038 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
2039 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY register field value suitable for setting the register. */
2040 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_SET(value) (((value) << 0) & 0x00000003)
2041 
2042 #ifndef __ASSEMBLY__
2043 /*
2044  * WARNING: The C register and register group struct declarations are provided for
2045  * convenience and illustrative purposes. They should, however, be used with
2046  * caution as the C language standard provides no guarantees about the alignment or
2047  * atomicity of device memory accesses. The recommended practice for writing
2048  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2049  * alt_write_word() functions.
2050  *
2051  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY.
2052  */
2053 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_s
2054 {
2055  uint32_t FILTERS_0_URGENCY : 2; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY */
2056  uint32_t : 30; /* *UNDEFINED* */
2057 };
2058 
2059 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY. */
2060 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_s ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_t;
2061 #endif /* __ASSEMBLY__ */
2062 
2063 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY register. */
2064 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_RESET 0x00000000
2065 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY register from the beginning of the component. */
2066 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_OFST 0x6c
2067 
2068 /*
2069  * Register : ddr_T_main_Probe_Filters_1_RouteIdBase
2070  *
2071  *
2072  * Register Layout
2073  *
2074  * Bits | Access | Reset | Description
2075  * :--------|:-------|:--------|:------------------------------------------------------------
2076  * [18:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE
2077  * [31:19] | ??? | Unknown | *UNDEFINED*
2078  *
2079  */
2080 /*
2081  * Field : FILTERS_1_ROUTEIDBASE
2082  *
2083  * Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to
2084  * filter packets.
2085  *
2086  * Field Access Macros:
2087  *
2088  */
2089 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE register field. */
2090 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_LSB 0
2091 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE register field. */
2092 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_MSB 18
2093 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE register field. */
2094 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_WIDTH 19
2095 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE register field value. */
2096 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_SET_MSK 0x0007ffff
2097 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE register field value. */
2098 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_CLR_MSK 0xfff80000
2099 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE register field. */
2100 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_RESET 0x0
2101 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE field value from a register. */
2102 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_GET(value) (((value) & 0x0007ffff) >> 0)
2103 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE register field value suitable for setting the register. */
2104 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_SET(value) (((value) << 0) & 0x0007ffff)
2105 
2106 #ifndef __ASSEMBLY__
2107 /*
2108  * WARNING: The C register and register group struct declarations are provided for
2109  * convenience and illustrative purposes. They should, however, be used with
2110  * caution as the C language standard provides no guarantees about the alignment or
2111  * atomicity of device memory accesses. The recommended practice for writing
2112  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2113  * alt_write_word() functions.
2114  *
2115  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE.
2116  */
2117 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_s
2118 {
2119  uint32_t FILTERS_1_ROUTEIDBASE : 19; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE */
2120  uint32_t : 13; /* *UNDEFINED* */
2121 };
2122 
2123 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE. */
2124 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_t;
2125 #endif /* __ASSEMBLY__ */
2126 
2127 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE register. */
2128 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_RESET 0x00000000
2129 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE register from the beginning of the component. */
2130 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_OFST 0x80
2131 
2132 /*
2133  * Register : ddr_T_main_Probe_Filters_1_RouteIdMask
2134  *
2135  *
2136  * Register Layout
2137  *
2138  * Bits | Access | Reset | Description
2139  * :--------|:-------|:--------|:----------------------------------------------------------
2140  * [18:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK
2141  * [31:19] | ??? | Unknown | *UNDEFINED*
2142  *
2143  */
2144 /*
2145  * Field : FILTERS_1_ROUTEIDMASK
2146  *
2147  * Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter
2148  * packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &
2149  * RouteIdMask = RouteIdBase & RouteIdMask.
2150  *
2151  * Field Access Macros:
2152  *
2153  */
2154 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK register field. */
2155 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_LSB 0
2156 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK register field. */
2157 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_MSB 18
2158 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK register field. */
2159 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_WIDTH 19
2160 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK register field value. */
2161 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_SET_MSK 0x0007ffff
2162 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK register field value. */
2163 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_CLR_MSK 0xfff80000
2164 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK register field. */
2165 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_RESET 0x0
2166 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK field value from a register. */
2167 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_GET(value) (((value) & 0x0007ffff) >> 0)
2168 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK register field value suitable for setting the register. */
2169 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_SET(value) (((value) << 0) & 0x0007ffff)
2170 
2171 #ifndef __ASSEMBLY__
2172 /*
2173  * WARNING: The C register and register group struct declarations are provided for
2174  * convenience and illustrative purposes. They should, however, be used with
2175  * caution as the C language standard provides no guarantees about the alignment or
2176  * atomicity of device memory accesses. The recommended practice for writing
2177  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2178  * alt_write_word() functions.
2179  *
2180  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK.
2181  */
2182 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_s
2183 {
2184  uint32_t FILTERS_1_ROUTEIDMASK : 19; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK */
2185  uint32_t : 13; /* *UNDEFINED* */
2186 };
2187 
2188 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK. */
2189 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_s ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_t;
2190 #endif /* __ASSEMBLY__ */
2191 
2192 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK register. */
2193 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_RESET 0x00000000
2194 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK register from the beginning of the component. */
2195 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_OFST 0x84
2196 
2197 /*
2198  * Register : ddr_T_main_Probe_Filters_1_AddrBase_Low
2199  *
2200  *
2201  * Register Layout
2202  *
2203  * Bits | Access | Reset | Description
2204  * :-------|:-------|:------|:--------------------------------------------------------------
2205  * [31:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW
2206  *
2207  */
2208 /*
2209  * Field : FILTERS_1_ADDRBASE_LOW
2210  *
2211  * Address LSB register.
2212  *
2213  * Field Access Macros:
2214  *
2215  */
2216 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW register field. */
2217 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_LSB 0
2218 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW register field. */
2219 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_MSB 31
2220 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW register field. */
2221 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_WIDTH 32
2222 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW register field value. */
2223 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_SET_MSK 0xffffffff
2224 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW register field value. */
2225 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_CLR_MSK 0x00000000
2226 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW register field. */
2227 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_RESET 0x0
2228 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW field value from a register. */
2229 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
2230 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW register field value suitable for setting the register. */
2231 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
2232 
2233 #ifndef __ASSEMBLY__
2234 /*
2235  * WARNING: The C register and register group struct declarations are provided for
2236  * convenience and illustrative purposes. They should, however, be used with
2237  * caution as the C language standard provides no guarantees about the alignment or
2238  * atomicity of device memory accesses. The recommended practice for writing
2239  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2240  * alt_write_word() functions.
2241  *
2242  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW.
2243  */
2244 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_s
2245 {
2246  uint32_t FILTERS_1_ADDRBASE_LOW : 32; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW */
2247 };
2248 
2249 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW. */
2250 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_s ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_t;
2251 #endif /* __ASSEMBLY__ */
2252 
2253 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW register. */
2254 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_RESET 0x00000000
2255 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW register from the beginning of the component. */
2256 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_OFST 0x88
2257 
2258 /*
2259  * Register : ddr_T_main_Probe_Filters_1_WindowSize
2260  *
2261  *
2262  * Register Layout
2263  *
2264  * Bits | Access | Reset | Description
2265  * :-------|:-------|:--------|:----------------------------------------------------------
2266  * [5:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE
2267  * [31:6] | ??? | Unknown | *UNDEFINED*
2268  *
2269  */
2270 /*
2271  * Field : FILTERS_1_WINDOWSIZE
2272  *
2273  * Register WindowSize contains the encoded address mask used to filter packets.
2274  * The effective Mask value is equal to ~(2max(WindowSize, packet.Len) - 1). A
2275  * packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows
2276  * filteringof packets having an intersection with the AddrBase/WindowSize burst
2277  * aligned region, even if the region is smaller than the packet.
2278  *
2279  * Field Access Macros:
2280  *
2281  */
2282 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE register field. */
2283 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_LSB 0
2284 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE register field. */
2285 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_MSB 5
2286 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE register field. */
2287 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_WIDTH 6
2288 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE register field value. */
2289 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_SET_MSK 0x0000003f
2290 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE register field value. */
2291 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_CLR_MSK 0xffffffc0
2292 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE register field. */
2293 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_RESET 0x0
2294 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE field value from a register. */
2295 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
2296 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE register field value suitable for setting the register. */
2297 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
2298 
2299 #ifndef __ASSEMBLY__
2300 /*
2301  * WARNING: The C register and register group struct declarations are provided for
2302  * convenience and illustrative purposes. They should, however, be used with
2303  * caution as the C language standard provides no guarantees about the alignment or
2304  * atomicity of device memory accesses. The recommended practice for writing
2305  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2306  * alt_write_word() functions.
2307  *
2308  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE.
2309  */
2310 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_s
2311 {
2312  uint32_t FILTERS_1_WINDOWSIZE : 6; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE */
2313  uint32_t : 26; /* *UNDEFINED* */
2314 };
2315 
2316 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE. */
2317 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_t;
2318 #endif /* __ASSEMBLY__ */
2319 
2320 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE register. */
2321 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_RESET 0x00000000
2322 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE register from the beginning of the component. */
2323 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_OFST 0x90
2324 
2325 /*
2326  * Register : ddr_T_main_Probe_Filters_1_SecurityBase
2327  *
2328  *
2329  * Register Layout
2330  *
2331  * Bits | Access | Reset | Description
2332  * :-------|:-------|:--------|:--------------------------------------------------------------
2333  * [2:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE
2334  * [31:3] | ??? | Unknown | *UNDEFINED*
2335  *
2336  */
2337 /*
2338  * Field : FILTERS_1_SECURITYBASE
2339  *
2340  * Register SecurityBase contains the security base used to filter packets.
2341  *
2342  * Field Access Macros:
2343  *
2344  */
2345 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE register field. */
2346 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_LSB 0
2347 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE register field. */
2348 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_MSB 2
2349 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE register field. */
2350 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_WIDTH 3
2351 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE register field value. */
2352 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_SET_MSK 0x00000007
2353 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE register field value. */
2354 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_CLR_MSK 0xfffffff8
2355 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE register field. */
2356 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_RESET 0x0
2357 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE field value from a register. */
2358 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
2359 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE register field value suitable for setting the register. */
2360 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
2361 
2362 #ifndef __ASSEMBLY__
2363 /*
2364  * WARNING: The C register and register group struct declarations are provided for
2365  * convenience and illustrative purposes. They should, however, be used with
2366  * caution as the C language standard provides no guarantees about the alignment or
2367  * atomicity of device memory accesses. The recommended practice for writing
2368  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2369  * alt_write_word() functions.
2370  *
2371  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE.
2372  */
2373 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_s
2374 {
2375  uint32_t FILTERS_1_SECURITYBASE : 3; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE */
2376  uint32_t : 29; /* *UNDEFINED* */
2377 };
2378 
2379 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE. */
2380 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_t;
2381 #endif /* __ASSEMBLY__ */
2382 
2383 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE register. */
2384 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_RESET 0x00000000
2385 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE register from the beginning of the component. */
2386 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_OFST 0x94
2387 
2388 /*
2389  * Register : ddr_T_main_Probe_Filters_1_SecurityMask
2390  *
2391  *
2392  * Register Layout
2393  *
2394  * Bits | Access | Reset | Description
2395  * :-------|:-------|:--------|:------------------------------------------------------------
2396  * [2:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK
2397  * [31:3] | ??? | Unknown | *UNDEFINED*
2398  *
2399  */
2400 /*
2401  * Field : FILTERS_1_SECURITYMASK
2402  *
2403  * Register SecurityMask is contains the security mask used to filter packets. A
2404  * packet is a candidate when: packet.Security & SecurityMask = SecurityBase &
2405  * SecurityMasks.
2406  *
2407  * Field Access Macros:
2408  *
2409  */
2410 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK register field. */
2411 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_LSB 0
2412 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK register field. */
2413 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_MSB 2
2414 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK register field. */
2415 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_WIDTH 3
2416 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK register field value. */
2417 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_SET_MSK 0x00000007
2418 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK register field value. */
2419 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_CLR_MSK 0xfffffff8
2420 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK register field. */
2421 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_RESET 0x0
2422 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK field value from a register. */
2423 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
2424 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK register field value suitable for setting the register. */
2425 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
2426 
2427 #ifndef __ASSEMBLY__
2428 /*
2429  * WARNING: The C register and register group struct declarations are provided for
2430  * convenience and illustrative purposes. They should, however, be used with
2431  * caution as the C language standard provides no guarantees about the alignment or
2432  * atomicity of device memory accesses. The recommended practice for writing
2433  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2434  * alt_write_word() functions.
2435  *
2436  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK.
2437  */
2438 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_s
2439 {
2440  uint32_t FILTERS_1_SECURITYMASK : 3; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK */
2441  uint32_t : 29; /* *UNDEFINED* */
2442 };
2443 
2444 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK. */
2445 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_s ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_t;
2446 #endif /* __ASSEMBLY__ */
2447 
2448 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK register. */
2449 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_RESET 0x00000000
2450 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK register from the beginning of the component. */
2451 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_OFST 0x98
2452 
2453 /*
2454  * Register : ddr_T_main_Probe_Filters_1_Opcode
2455  *
2456  * Packet Probe register Opcode is a 4-bit register that selects candidate packets
2457  * based on packet opcodes (0 disables the filter):
2458  *
2459  * Register Layout
2460  *
2461  * Bits | Access | Reset | Description
2462  * :-------|:-------|:--------|:-------------------------------------------
2463  * [0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN
2464  * [1] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN
2465  * [2] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN
2466  * [3] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN
2467  * [31:4] | ??? | Unknown | *UNDEFINED*
2468  *
2469  */
2470 /*
2471  * Field : RDEN
2472  *
2473  * Selects RD packets.
2474  *
2475  * Field Access Macros:
2476  *
2477  */
2478 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN register field. */
2479 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_LSB 0
2480 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN register field. */
2481 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_MSB 0
2482 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN register field. */
2483 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_WIDTH 1
2484 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN register field value. */
2485 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_SET_MSK 0x00000001
2486 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN register field value. */
2487 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_CLR_MSK 0xfffffffe
2488 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN register field. */
2489 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_RESET 0x0
2490 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN field value from a register. */
2491 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
2492 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN register field value suitable for setting the register. */
2493 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
2494 
2495 /*
2496  * Field : WREN
2497  *
2498  * Selects WR packets.
2499  *
2500  * Field Access Macros:
2501  *
2502  */
2503 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN register field. */
2504 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_LSB 1
2505 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN register field. */
2506 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_MSB 1
2507 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN register field. */
2508 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_WIDTH 1
2509 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN register field value. */
2510 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_SET_MSK 0x00000002
2511 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN register field value. */
2512 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_CLR_MSK 0xfffffffd
2513 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN register field. */
2514 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_RESET 0x0
2515 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN field value from a register. */
2516 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
2517 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN register field value suitable for setting the register. */
2518 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
2519 
2520 /*
2521  * Field : LOCKEN
2522  *
2523  * Selects RDX-WR, RDL, WRC and Linked sequence.
2524  *
2525  * Field Access Macros:
2526  *
2527  */
2528 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN register field. */
2529 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_LSB 2
2530 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN register field. */
2531 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_MSB 2
2532 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN register field. */
2533 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_WIDTH 1
2534 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN register field value. */
2535 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_SET_MSK 0x00000004
2536 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN register field value. */
2537 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
2538 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN register field. */
2539 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_RESET 0x0
2540 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN field value from a register. */
2541 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
2542 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN register field value suitable for setting the register. */
2543 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
2544 
2545 /*
2546  * Field : URGEN
2547  *
2548  * Selects URG packets (urgency).
2549  *
2550  * Field Access Macros:
2551  *
2552  */
2553 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN register field. */
2554 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_LSB 3
2555 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN register field. */
2556 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_MSB 3
2557 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN register field. */
2558 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_WIDTH 1
2559 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN register field value. */
2560 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_SET_MSK 0x00000008
2561 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN register field value. */
2562 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_CLR_MSK 0xfffffff7
2563 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN register field. */
2564 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_RESET 0x0
2565 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN field value from a register. */
2566 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
2567 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN register field value suitable for setting the register. */
2568 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
2569 
2570 #ifndef __ASSEMBLY__
2571 /*
2572  * WARNING: The C register and register group struct declarations are provided for
2573  * convenience and illustrative purposes. They should, however, be used with
2574  * caution as the C language standard provides no guarantees about the alignment or
2575  * atomicity of device memory accesses. The recommended practice for writing
2576  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2577  * alt_write_word() functions.
2578  *
2579  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE.
2580  */
2581 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_s
2582 {
2583  uint32_t RDEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN */
2584  uint32_t WREN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN */
2585  uint32_t LOCKEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN */
2586  uint32_t URGEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN */
2587  uint32_t : 28; /* *UNDEFINED* */
2588 };
2589 
2590 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE. */
2591 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_t;
2592 #endif /* __ASSEMBLY__ */
2593 
2594 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE register. */
2595 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RESET 0x00000000
2596 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE register from the beginning of the component. */
2597 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_OFST 0x9c
2598 
2599 /*
2600  * Register : ddr_T_main_Probe_Filters_1_Status
2601  *
2602  * Register Status is 2-bit register that selects candidate packets based on packet
2603  * status.
2604  *
2605  * Register Layout
2606  *
2607  * Bits | Access | Reset | Description
2608  * :-------|:-------|:--------|:----------------------------------------
2609  * [0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN
2610  * [1] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN
2611  * [31:2] | ??? | Unknown | *UNDEFINED*
2612  *
2613  */
2614 /*
2615  * Field : REQEN
2616  *
2617  * Selects REQ status packets.
2618  *
2619  * Field Access Macros:
2620  *
2621  */
2622 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN register field. */
2623 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_LSB 0
2624 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN register field. */
2625 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_MSB 0
2626 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN register field. */
2627 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_WIDTH 1
2628 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN register field value. */
2629 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_SET_MSK 0x00000001
2630 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN register field value. */
2631 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_CLR_MSK 0xfffffffe
2632 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN register field. */
2633 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_RESET 0x0
2634 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN field value from a register. */
2635 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_GET(value) (((value) & 0x00000001) >> 0)
2636 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN register field value suitable for setting the register. */
2637 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_SET(value) (((value) << 0) & 0x00000001)
2638 
2639 /*
2640  * Field : RSPEN
2641  *
2642  * Selects RSP and FAIL-CONT status packets.
2643  *
2644  * Field Access Macros:
2645  *
2646  */
2647 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN register field. */
2648 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_LSB 1
2649 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN register field. */
2650 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_MSB 1
2651 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN register field. */
2652 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_WIDTH 1
2653 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN register field value. */
2654 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_SET_MSK 0x00000002
2655 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN register field value. */
2656 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_CLR_MSK 0xfffffffd
2657 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN register field. */
2658 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_RESET 0x0
2659 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN field value from a register. */
2660 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
2661 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN register field value suitable for setting the register. */
2662 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_SET(value) (((value) << 1) & 0x00000002)
2663 
2664 #ifndef __ASSEMBLY__
2665 /*
2666  * WARNING: The C register and register group struct declarations are provided for
2667  * convenience and illustrative purposes. They should, however, be used with
2668  * caution as the C language standard provides no guarantees about the alignment or
2669  * atomicity of device memory accesses. The recommended practice for writing
2670  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2671  * alt_write_word() functions.
2672  *
2673  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT.
2674  */
2675 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_s
2676 {
2677  uint32_t REQEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN */
2678  uint32_t RSPEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN */
2679  uint32_t : 30; /* *UNDEFINED* */
2680 };
2681 
2682 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT. */
2683 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_s ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_t;
2684 #endif /* __ASSEMBLY__ */
2685 
2686 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT register. */
2687 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RESET 0x00000000
2688 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT register from the beginning of the component. */
2689 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_OFST 0xa0
2690 
2691 /*
2692  * Register : ddr_T_main_Probe_Filters_1_Length
2693  *
2694  *
2695  * Register Layout
2696  *
2697  * Bits | Access | Reset | Description
2698  * :-------|:-------|:--------|:--------------------------------------------
2699  * [3:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN
2700  * [31:4] | ??? | Unknown | *UNDEFINED*
2701  *
2702  */
2703 /*
2704  * Field : FILTERS_1_LENGTH
2705  *
2706  * Register Length is 4-bit register that selects candidate packets if their number
2707  * of bytes is less than or equal to 2**Length.
2708  *
2709  * Field Access Macros:
2710  *
2711  */
2712 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN register field. */
2713 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_LSB 0
2714 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN register field. */
2715 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_MSB 3
2716 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN register field. */
2717 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_WIDTH 4
2718 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN register field value. */
2719 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_SET_MSK 0x0000000f
2720 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN register field value. */
2721 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_CLR_MSK 0xfffffff0
2722 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN register field. */
2723 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_RESET 0x0
2724 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN field value from a register. */
2725 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_GET(value) (((value) & 0x0000000f) >> 0)
2726 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN register field value suitable for setting the register. */
2727 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_SET(value) (((value) << 0) & 0x0000000f)
2728 
2729 #ifndef __ASSEMBLY__
2730 /*
2731  * WARNING: The C register and register group struct declarations are provided for
2732  * convenience and illustrative purposes. They should, however, be used with
2733  * caution as the C language standard provides no guarantees about the alignment or
2734  * atomicity of device memory accesses. The recommended practice for writing
2735  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2736  * alt_write_word() functions.
2737  *
2738  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN.
2739  */
2740 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_s
2741 {
2742  uint32_t FILTERS_1_LENGTH : 4; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN */
2743  uint32_t : 28; /* *UNDEFINED* */
2744 };
2745 
2746 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN. */
2747 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_s ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_t;
2748 #endif /* __ASSEMBLY__ */
2749 
2750 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN register. */
2751 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_RESET 0x00000000
2752 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN register from the beginning of the component. */
2753 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_OFST 0xa4
2754 
2755 /*
2756  * Register : ddr_T_main_Probe_Filters_1_Urgency
2757  *
2758  *
2759  * Register Layout
2760  *
2761  * Bits | Access | Reset | Description
2762  * :-------|:-------|:--------|:----------------------------------------------------
2763  * [1:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY
2764  * [31:2] | ??? | Unknown | *UNDEFINED*
2765  *
2766  */
2767 /*
2768  * Field : FILTERS_1_URGENCY
2769  *
2770  * Register Urgency contains the minimum urgency level used to filter packets. A
2771  * packet is a candidate when its socket urgency is greater than or equal to the
2772  * urgency specified in the register.
2773  *
2774  * Field Access Macros:
2775  *
2776  */
2777 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY register field. */
2778 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_LSB 0
2779 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY register field. */
2780 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_MSB 1
2781 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY register field. */
2782 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_WIDTH 2
2783 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY register field value. */
2784 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_SET_MSK 0x00000003
2785 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY register field value. */
2786 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_CLR_MSK 0xfffffffc
2787 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY register field. */
2788 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_RESET 0x0
2789 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY field value from a register. */
2790 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
2791 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY register field value suitable for setting the register. */
2792 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_SET(value) (((value) << 0) & 0x00000003)
2793 
2794 #ifndef __ASSEMBLY__
2795 /*
2796  * WARNING: The C register and register group struct declarations are provided for
2797  * convenience and illustrative purposes. They should, however, be used with
2798  * caution as the C language standard provides no guarantees about the alignment or
2799  * atomicity of device memory accesses. The recommended practice for writing
2800  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2801  * alt_write_word() functions.
2802  *
2803  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY.
2804  */
2805 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_s
2806 {
2807  uint32_t FILTERS_1_URGENCY : 2; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY */
2808  uint32_t : 30; /* *UNDEFINED* */
2809 };
2810 
2811 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY. */
2812 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_s ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_t;
2813 #endif /* __ASSEMBLY__ */
2814 
2815 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY register. */
2816 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_RESET 0x00000000
2817 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY register from the beginning of the component. */
2818 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_OFST 0xa8
2819 
2820 /*
2821  * Register : ddr_T_main_Probe_Filters_2_RouteIdBase
2822  *
2823  *
2824  * Register Layout
2825  *
2826  * Bits | Access | Reset | Description
2827  * :--------|:-------|:--------|:------------------------------------------------------------
2828  * [18:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE
2829  * [31:19] | ??? | Unknown | *UNDEFINED*
2830  *
2831  */
2832 /*
2833  * Field : FILTERS_2_ROUTEIDBASE
2834  *
2835  * Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to
2836  * filter packets.
2837  *
2838  * Field Access Macros:
2839  *
2840  */
2841 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE register field. */
2842 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_LSB 0
2843 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE register field. */
2844 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_MSB 18
2845 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE register field. */
2846 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_WIDTH 19
2847 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE register field value. */
2848 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_SET_MSK 0x0007ffff
2849 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE register field value. */
2850 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_CLR_MSK 0xfff80000
2851 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE register field. */
2852 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_RESET 0x0
2853 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE field value from a register. */
2854 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_GET(value) (((value) & 0x0007ffff) >> 0)
2855 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE register field value suitable for setting the register. */
2856 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_SET(value) (((value) << 0) & 0x0007ffff)
2857 
2858 #ifndef __ASSEMBLY__
2859 /*
2860  * WARNING: The C register and register group struct declarations are provided for
2861  * convenience and illustrative purposes. They should, however, be used with
2862  * caution as the C language standard provides no guarantees about the alignment or
2863  * atomicity of device memory accesses. The recommended practice for writing
2864  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2865  * alt_write_word() functions.
2866  *
2867  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE.
2868  */
2869 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_s
2870 {
2871  uint32_t FILTERS_2_ROUTEIDBASE : 19; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE */
2872  uint32_t : 13; /* *UNDEFINED* */
2873 };
2874 
2875 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE. */
2876 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_t;
2877 #endif /* __ASSEMBLY__ */
2878 
2879 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE register. */
2880 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_RESET 0x00000000
2881 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE register from the beginning of the component. */
2882 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_OFST 0xbc
2883 
2884 /*
2885  * Register : ddr_T_main_Probe_Filters_2_RouteIdMask
2886  *
2887  *
2888  * Register Layout
2889  *
2890  * Bits | Access | Reset | Description
2891  * :--------|:-------|:--------|:----------------------------------------------------------
2892  * [18:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK
2893  * [31:19] | ??? | Unknown | *UNDEFINED*
2894  *
2895  */
2896 /*
2897  * Field : FILTERS_2_ROUTEIDMASK
2898  *
2899  * Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter
2900  * packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &
2901  * RouteIdMask = RouteIdBase & RouteIdMask.
2902  *
2903  * Field Access Macros:
2904  *
2905  */
2906 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK register field. */
2907 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_LSB 0
2908 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK register field. */
2909 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_MSB 18
2910 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK register field. */
2911 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_WIDTH 19
2912 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK register field value. */
2913 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_SET_MSK 0x0007ffff
2914 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK register field value. */
2915 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_CLR_MSK 0xfff80000
2916 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK register field. */
2917 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_RESET 0x0
2918 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK field value from a register. */
2919 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_GET(value) (((value) & 0x0007ffff) >> 0)
2920 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK register field value suitable for setting the register. */
2921 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_SET(value) (((value) << 0) & 0x0007ffff)
2922 
2923 #ifndef __ASSEMBLY__
2924 /*
2925  * WARNING: The C register and register group struct declarations are provided for
2926  * convenience and illustrative purposes. They should, however, be used with
2927  * caution as the C language standard provides no guarantees about the alignment or
2928  * atomicity of device memory accesses. The recommended practice for writing
2929  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2930  * alt_write_word() functions.
2931  *
2932  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK.
2933  */
2934 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_s
2935 {
2936  uint32_t FILTERS_2_ROUTEIDMASK : 19; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK */
2937  uint32_t : 13; /* *UNDEFINED* */
2938 };
2939 
2940 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK. */
2941 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_s ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_t;
2942 #endif /* __ASSEMBLY__ */
2943 
2944 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK register. */
2945 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_RESET 0x00000000
2946 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK register from the beginning of the component. */
2947 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_OFST 0xc0
2948 
2949 /*
2950  * Register : ddr_T_main_Probe_Filters_2_AddrBase_Low
2951  *
2952  *
2953  * Register Layout
2954  *
2955  * Bits | Access | Reset | Description
2956  * :-------|:-------|:------|:--------------------------------------------------------------
2957  * [31:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW
2958  *
2959  */
2960 /*
2961  * Field : FILTERS_2_ADDRBASE_LOW
2962  *
2963  * Address LSB register.
2964  *
2965  * Field Access Macros:
2966  *
2967  */
2968 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW register field. */
2969 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_LSB 0
2970 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW register field. */
2971 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_MSB 31
2972 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW register field. */
2973 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_WIDTH 32
2974 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW register field value. */
2975 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_SET_MSK 0xffffffff
2976 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW register field value. */
2977 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_CLR_MSK 0x00000000
2978 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW register field. */
2979 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_RESET 0x0
2980 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW field value from a register. */
2981 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
2982 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW register field value suitable for setting the register. */
2983 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
2984 
2985 #ifndef __ASSEMBLY__
2986 /*
2987  * WARNING: The C register and register group struct declarations are provided for
2988  * convenience and illustrative purposes. They should, however, be used with
2989  * caution as the C language standard provides no guarantees about the alignment or
2990  * atomicity of device memory accesses. The recommended practice for writing
2991  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2992  * alt_write_word() functions.
2993  *
2994  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW.
2995  */
2996 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_s
2997 {
2998  uint32_t FILTERS_2_ADDRBASE_LOW : 32; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW */
2999 };
3000 
3001 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW. */
3002 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_s ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_t;
3003 #endif /* __ASSEMBLY__ */
3004 
3005 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW register. */
3006 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_RESET 0x00000000
3007 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW register from the beginning of the component. */
3008 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_OFST 0xc4
3009 
3010 /*
3011  * Register : ddr_T_main_Probe_Filters_2_WindowSize
3012  *
3013  *
3014  * Register Layout
3015  *
3016  * Bits | Access | Reset | Description
3017  * :-------|:-------|:--------|:----------------------------------------------------------
3018  * [5:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE
3019  * [31:6] | ??? | Unknown | *UNDEFINED*
3020  *
3021  */
3022 /*
3023  * Field : FILTERS_2_WINDOWSIZE
3024  *
3025  * Register WindowSize contains the encoded address mask used to filter packets.
3026  * The effective Mask value is equal to ~(2max(WindowSize, packet.Len) - 1). A
3027  * packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows
3028  * filteringof packets having an intersection with the AddrBase/WindowSize burst
3029  * aligned region, even if the region is smaller than the packet.
3030  *
3031  * Field Access Macros:
3032  *
3033  */
3034 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE register field. */
3035 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_LSB 0
3036 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE register field. */
3037 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_MSB 5
3038 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE register field. */
3039 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_WIDTH 6
3040 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE register field value. */
3041 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_SET_MSK 0x0000003f
3042 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE register field value. */
3043 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_CLR_MSK 0xffffffc0
3044 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE register field. */
3045 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_RESET 0x0
3046 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE field value from a register. */
3047 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
3048 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE register field value suitable for setting the register. */
3049 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
3050 
3051 #ifndef __ASSEMBLY__
3052 /*
3053  * WARNING: The C register and register group struct declarations are provided for
3054  * convenience and illustrative purposes. They should, however, be used with
3055  * caution as the C language standard provides no guarantees about the alignment or
3056  * atomicity of device memory accesses. The recommended practice for writing
3057  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3058  * alt_write_word() functions.
3059  *
3060  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE.
3061  */
3062 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_s
3063 {
3064  uint32_t FILTERS_2_WINDOWSIZE : 6; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE */
3065  uint32_t : 26; /* *UNDEFINED* */
3066 };
3067 
3068 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE. */
3069 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_t;
3070 #endif /* __ASSEMBLY__ */
3071 
3072 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE register. */
3073 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_RESET 0x00000000
3074 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE register from the beginning of the component. */
3075 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_OFST 0xcc
3076 
3077 /*
3078  * Register : ddr_T_main_Probe_Filters_2_SecurityBase
3079  *
3080  *
3081  * Register Layout
3082  *
3083  * Bits | Access | Reset | Description
3084  * :-------|:-------|:--------|:--------------------------------------------------------------
3085  * [2:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE
3086  * [31:3] | ??? | Unknown | *UNDEFINED*
3087  *
3088  */
3089 /*
3090  * Field : FILTERS_2_SECURITYBASE
3091  *
3092  * Register SecurityBase contains the security base used to filter packets.
3093  *
3094  * Field Access Macros:
3095  *
3096  */
3097 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE register field. */
3098 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_LSB 0
3099 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE register field. */
3100 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_MSB 2
3101 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE register field. */
3102 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_WIDTH 3
3103 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE register field value. */
3104 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_SET_MSK 0x00000007
3105 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE register field value. */
3106 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_CLR_MSK 0xfffffff8
3107 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE register field. */
3108 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_RESET 0x0
3109 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE field value from a register. */
3110 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
3111 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE register field value suitable for setting the register. */
3112 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
3113 
3114 #ifndef __ASSEMBLY__
3115 /*
3116  * WARNING: The C register and register group struct declarations are provided for
3117  * convenience and illustrative purposes. They should, however, be used with
3118  * caution as the C language standard provides no guarantees about the alignment or
3119  * atomicity of device memory accesses. The recommended practice for writing
3120  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3121  * alt_write_word() functions.
3122  *
3123  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE.
3124  */
3125 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_s
3126 {
3127  uint32_t FILTERS_2_SECURITYBASE : 3; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE */
3128  uint32_t : 29; /* *UNDEFINED* */
3129 };
3130 
3131 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE. */
3132 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_t;
3133 #endif /* __ASSEMBLY__ */
3134 
3135 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE register. */
3136 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_RESET 0x00000000
3137 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE register from the beginning of the component. */
3138 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_OFST 0xd0
3139 
3140 /*
3141  * Register : ddr_T_main_Probe_Filters_2_SecurityMask
3142  *
3143  *
3144  * Register Layout
3145  *
3146  * Bits | Access | Reset | Description
3147  * :-------|:-------|:--------|:------------------------------------------------------------
3148  * [2:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK
3149  * [31:3] | ??? | Unknown | *UNDEFINED*
3150  *
3151  */
3152 /*
3153  * Field : FILTERS_2_SECURITYMASK
3154  *
3155  * Register SecurityMask is contains the security mask used to filter packets. A
3156  * packet is a candidate when: packet.Security & SecurityMask = SecurityBase &
3157  * SecurityMasks.
3158  *
3159  * Field Access Macros:
3160  *
3161  */
3162 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK register field. */
3163 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_LSB 0
3164 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK register field. */
3165 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_MSB 2
3166 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK register field. */
3167 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_WIDTH 3
3168 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK register field value. */
3169 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_SET_MSK 0x00000007
3170 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK register field value. */
3171 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_CLR_MSK 0xfffffff8
3172 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK register field. */
3173 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_RESET 0x0
3174 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK field value from a register. */
3175 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
3176 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK register field value suitable for setting the register. */
3177 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
3178 
3179 #ifndef __ASSEMBLY__
3180 /*
3181  * WARNING: The C register and register group struct declarations are provided for
3182  * convenience and illustrative purposes. They should, however, be used with
3183  * caution as the C language standard provides no guarantees about the alignment or
3184  * atomicity of device memory accesses. The recommended practice for writing
3185  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3186  * alt_write_word() functions.
3187  *
3188  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK.
3189  */
3190 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_s
3191 {
3192  uint32_t FILTERS_2_SECURITYMASK : 3; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK */
3193  uint32_t : 29; /* *UNDEFINED* */
3194 };
3195 
3196 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK. */
3197 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_s ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_t;
3198 #endif /* __ASSEMBLY__ */
3199 
3200 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK register. */
3201 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_RESET 0x00000000
3202 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK register from the beginning of the component. */
3203 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_OFST 0xd4
3204 
3205 /*
3206  * Register : ddr_T_main_Probe_Filters_2_Opcode
3207  *
3208  * Packet Probe register Opcode is a 4-bit register that selects candidate packets
3209  * based on packet opcodes (0 disables the filter):
3210  *
3211  * Register Layout
3212  *
3213  * Bits | Access | Reset | Description
3214  * :-------|:-------|:--------|:-------------------------------------------
3215  * [0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN
3216  * [1] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN
3217  * [2] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN
3218  * [3] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN
3219  * [31:4] | ??? | Unknown | *UNDEFINED*
3220  *
3221  */
3222 /*
3223  * Field : RDEN
3224  *
3225  * Selects RD packets.
3226  *
3227  * Field Access Macros:
3228  *
3229  */
3230 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN register field. */
3231 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_LSB 0
3232 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN register field. */
3233 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_MSB 0
3234 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN register field. */
3235 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_WIDTH 1
3236 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN register field value. */
3237 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_SET_MSK 0x00000001
3238 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN register field value. */
3239 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_CLR_MSK 0xfffffffe
3240 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN register field. */
3241 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_RESET 0x0
3242 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN field value from a register. */
3243 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
3244 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN register field value suitable for setting the register. */
3245 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
3246 
3247 /*
3248  * Field : WREN
3249  *
3250  * Selects WR packets.
3251  *
3252  * Field Access Macros:
3253  *
3254  */
3255 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN register field. */
3256 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_LSB 1
3257 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN register field. */
3258 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_MSB 1
3259 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN register field. */
3260 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_WIDTH 1
3261 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN register field value. */
3262 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_SET_MSK 0x00000002
3263 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN register field value. */
3264 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_CLR_MSK 0xfffffffd
3265 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN register field. */
3266 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_RESET 0x0
3267 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN field value from a register. */
3268 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
3269 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN register field value suitable for setting the register. */
3270 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
3271 
3272 /*
3273  * Field : LOCKEN
3274  *
3275  * Selects RDX-WR, RDL, WRC and Linked sequence.
3276  *
3277  * Field Access Macros:
3278  *
3279  */
3280 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN register field. */
3281 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_LSB 2
3282 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN register field. */
3283 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_MSB 2
3284 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN register field. */
3285 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_WIDTH 1
3286 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN register field value. */
3287 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_SET_MSK 0x00000004
3288 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN register field value. */
3289 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
3290 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN register field. */
3291 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_RESET 0x0
3292 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN field value from a register. */
3293 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
3294 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN register field value suitable for setting the register. */
3295 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
3296 
3297 /*
3298  * Field : URGEN
3299  *
3300  * Selects URG packets (urgency).
3301  *
3302  * Field Access Macros:
3303  *
3304  */
3305 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN register field. */
3306 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_LSB 3
3307 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN register field. */
3308 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_MSB 3
3309 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN register field. */
3310 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_WIDTH 1
3311 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN register field value. */
3312 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_SET_MSK 0x00000008
3313 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN register field value. */
3314 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_CLR_MSK 0xfffffff7
3315 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN register field. */
3316 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_RESET 0x0
3317 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN field value from a register. */
3318 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
3319 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN register field value suitable for setting the register. */
3320 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
3321 
3322 #ifndef __ASSEMBLY__
3323 /*
3324  * WARNING: The C register and register group struct declarations are provided for
3325  * convenience and illustrative purposes. They should, however, be used with
3326  * caution as the C language standard provides no guarantees about the alignment or
3327  * atomicity of device memory accesses. The recommended practice for writing
3328  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3329  * alt_write_word() functions.
3330  *
3331  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE.
3332  */
3333 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_s
3334 {
3335  uint32_t RDEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN */
3336  uint32_t WREN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN */
3337  uint32_t LOCKEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN */
3338  uint32_t URGEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN */
3339  uint32_t : 28; /* *UNDEFINED* */
3340 };
3341 
3342 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE. */
3343 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_t;
3344 #endif /* __ASSEMBLY__ */
3345 
3346 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE register. */
3347 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RESET 0x00000000
3348 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE register from the beginning of the component. */
3349 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_OFST 0xd8
3350 
3351 /*
3352  * Register : ddr_T_main_Probe_Filters_2_Status
3353  *
3354  * Register Status is 2-bit register that selects candidate packets based on packet
3355  * status.
3356  *
3357  * Register Layout
3358  *
3359  * Bits | Access | Reset | Description
3360  * :-------|:-------|:--------|:----------------------------------------
3361  * [0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN
3362  * [1] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN
3363  * [31:2] | ??? | Unknown | *UNDEFINED*
3364  *
3365  */
3366 /*
3367  * Field : REQEN
3368  *
3369  * Selects REQ status packets.
3370  *
3371  * Field Access Macros:
3372  *
3373  */
3374 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN register field. */
3375 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_LSB 0
3376 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN register field. */
3377 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_MSB 0
3378 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN register field. */
3379 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_WIDTH 1
3380 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN register field value. */
3381 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_SET_MSK 0x00000001
3382 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN register field value. */
3383 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_CLR_MSK 0xfffffffe
3384 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN register field. */
3385 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_RESET 0x0
3386 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN field value from a register. */
3387 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_GET(value) (((value) & 0x00000001) >> 0)
3388 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN register field value suitable for setting the register. */
3389 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_SET(value) (((value) << 0) & 0x00000001)
3390 
3391 /*
3392  * Field : RSPEN
3393  *
3394  * Selects RSP and FAIL-CONT status packets.
3395  *
3396  * Field Access Macros:
3397  *
3398  */
3399 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN register field. */
3400 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_LSB 1
3401 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN register field. */
3402 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_MSB 1
3403 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN register field. */
3404 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_WIDTH 1
3405 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN register field value. */
3406 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_SET_MSK 0x00000002
3407 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN register field value. */
3408 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_CLR_MSK 0xfffffffd
3409 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN register field. */
3410 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_RESET 0x0
3411 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN field value from a register. */
3412 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
3413 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN register field value suitable for setting the register. */
3414 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_SET(value) (((value) << 1) & 0x00000002)
3415 
3416 #ifndef __ASSEMBLY__
3417 /*
3418  * WARNING: The C register and register group struct declarations are provided for
3419  * convenience and illustrative purposes. They should, however, be used with
3420  * caution as the C language standard provides no guarantees about the alignment or
3421  * atomicity of device memory accesses. The recommended practice for writing
3422  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3423  * alt_write_word() functions.
3424  *
3425  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT.
3426  */
3427 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_s
3428 {
3429  uint32_t REQEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN */
3430  uint32_t RSPEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN */
3431  uint32_t : 30; /* *UNDEFINED* */
3432 };
3433 
3434 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT. */
3435 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_s ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_t;
3436 #endif /* __ASSEMBLY__ */
3437 
3438 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT register. */
3439 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RESET 0x00000000
3440 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT register from the beginning of the component. */
3441 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_OFST 0xdc
3442 
3443 /*
3444  * Register : ddr_T_main_Probe_Filters_2_Length
3445  *
3446  *
3447  * Register Layout
3448  *
3449  * Bits | Access | Reset | Description
3450  * :-------|:-------|:--------|:--------------------------------------------
3451  * [3:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN
3452  * [31:4] | ??? | Unknown | *UNDEFINED*
3453  *
3454  */
3455 /*
3456  * Field : FILTERS_2_LENGTH
3457  *
3458  * Register Length is 4-bit register that selects candidate packets if their number
3459  * of bytes is less than or equal to 2**Length.
3460  *
3461  * Field Access Macros:
3462  *
3463  */
3464 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN register field. */
3465 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_LSB 0
3466 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN register field. */
3467 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_MSB 3
3468 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN register field. */
3469 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_WIDTH 4
3470 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN register field value. */
3471 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_SET_MSK 0x0000000f
3472 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN register field value. */
3473 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_CLR_MSK 0xfffffff0
3474 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN register field. */
3475 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_RESET 0x0
3476 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN field value from a register. */
3477 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_GET(value) (((value) & 0x0000000f) >> 0)
3478 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN register field value suitable for setting the register. */
3479 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_SET(value) (((value) << 0) & 0x0000000f)
3480 
3481 #ifndef __ASSEMBLY__
3482 /*
3483  * WARNING: The C register and register group struct declarations are provided for
3484  * convenience and illustrative purposes. They should, however, be used with
3485  * caution as the C language standard provides no guarantees about the alignment or
3486  * atomicity of device memory accesses. The recommended practice for writing
3487  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3488  * alt_write_word() functions.
3489  *
3490  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN.
3491  */
3492 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_s
3493 {
3494  uint32_t FILTERS_2_LENGTH : 4; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN */
3495  uint32_t : 28; /* *UNDEFINED* */
3496 };
3497 
3498 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN. */
3499 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_s ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_t;
3500 #endif /* __ASSEMBLY__ */
3501 
3502 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN register. */
3503 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_RESET 0x00000000
3504 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN register from the beginning of the component. */
3505 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_OFST 0xe0
3506 
3507 /*
3508  * Register : ddr_T_main_Probe_Filters_2_Urgency
3509  *
3510  *
3511  * Register Layout
3512  *
3513  * Bits | Access | Reset | Description
3514  * :-------|:-------|:--------|:----------------------------------------------------
3515  * [1:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY
3516  * [31:2] | ??? | Unknown | *UNDEFINED*
3517  *
3518  */
3519 /*
3520  * Field : FILTERS_2_URGENCY
3521  *
3522  * Register Urgency contains the minimum urgency level used to filter packets. A
3523  * packet is a candidate when its socket urgency is greater than or equal to the
3524  * urgency specified in the register.
3525  *
3526  * Field Access Macros:
3527  *
3528  */
3529 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY register field. */
3530 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_LSB 0
3531 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY register field. */
3532 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_MSB 1
3533 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY register field. */
3534 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_WIDTH 2
3535 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY register field value. */
3536 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_SET_MSK 0x00000003
3537 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY register field value. */
3538 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_CLR_MSK 0xfffffffc
3539 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY register field. */
3540 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_RESET 0x0
3541 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY field value from a register. */
3542 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
3543 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY register field value suitable for setting the register. */
3544 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_SET(value) (((value) << 0) & 0x00000003)
3545 
3546 #ifndef __ASSEMBLY__
3547 /*
3548  * WARNING: The C register and register group struct declarations are provided for
3549  * convenience and illustrative purposes. They should, however, be used with
3550  * caution as the C language standard provides no guarantees about the alignment or
3551  * atomicity of device memory accesses. The recommended practice for writing
3552  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3553  * alt_write_word() functions.
3554  *
3555  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY.
3556  */
3557 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_s
3558 {
3559  uint32_t FILTERS_2_URGENCY : 2; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY */
3560  uint32_t : 30; /* *UNDEFINED* */
3561 };
3562 
3563 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY. */
3564 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_s ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_t;
3565 #endif /* __ASSEMBLY__ */
3566 
3567 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY register. */
3568 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_RESET 0x00000000
3569 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY register from the beginning of the component. */
3570 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_OFST 0xe4
3571 
3572 /*
3573  * Register : ddr_T_main_Probe_Filters_3_RouteIdBase
3574  *
3575  *
3576  * Register Layout
3577  *
3578  * Bits | Access | Reset | Description
3579  * :--------|:-------|:--------|:------------------------------------------------------------
3580  * [18:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE
3581  * [31:19] | ??? | Unknown | *UNDEFINED*
3582  *
3583  */
3584 /*
3585  * Field : FILTERS_3_ROUTEIDBASE
3586  *
3587  * Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to
3588  * filter packets.
3589  *
3590  * Field Access Macros:
3591  *
3592  */
3593 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE register field. */
3594 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_LSB 0
3595 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE register field. */
3596 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_MSB 18
3597 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE register field. */
3598 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_WIDTH 19
3599 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE register field value. */
3600 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_SET_MSK 0x0007ffff
3601 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE register field value. */
3602 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_CLR_MSK 0xfff80000
3603 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE register field. */
3604 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_RESET 0x0
3605 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE field value from a register. */
3606 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_GET(value) (((value) & 0x0007ffff) >> 0)
3607 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE register field value suitable for setting the register. */
3608 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_SET(value) (((value) << 0) & 0x0007ffff)
3609 
3610 #ifndef __ASSEMBLY__
3611 /*
3612  * WARNING: The C register and register group struct declarations are provided for
3613  * convenience and illustrative purposes. They should, however, be used with
3614  * caution as the C language standard provides no guarantees about the alignment or
3615  * atomicity of device memory accesses. The recommended practice for writing
3616  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3617  * alt_write_word() functions.
3618  *
3619  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE.
3620  */
3621 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_s
3622 {
3623  uint32_t FILTERS_3_ROUTEIDBASE : 19; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE */
3624  uint32_t : 13; /* *UNDEFINED* */
3625 };
3626 
3627 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE. */
3628 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_t;
3629 #endif /* __ASSEMBLY__ */
3630 
3631 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE register. */
3632 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_RESET 0x00000000
3633 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE register from the beginning of the component. */
3634 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_OFST 0xf8
3635 
3636 /*
3637  * Register : ddr_T_main_Probe_Filters_3_RouteIdMask
3638  *
3639  *
3640  * Register Layout
3641  *
3642  * Bits | Access | Reset | Description
3643  * :--------|:-------|:--------|:----------------------------------------------------------
3644  * [18:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK
3645  * [31:19] | ??? | Unknown | *UNDEFINED*
3646  *
3647  */
3648 /*
3649  * Field : FILTERS_3_ROUTEIDMASK
3650  *
3651  * Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter
3652  * packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &
3653  * RouteIdMask = RouteIdBase & RouteIdMask.
3654  *
3655  * Field Access Macros:
3656  *
3657  */
3658 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK register field. */
3659 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_LSB 0
3660 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK register field. */
3661 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_MSB 18
3662 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK register field. */
3663 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_WIDTH 19
3664 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK register field value. */
3665 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_SET_MSK 0x0007ffff
3666 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK register field value. */
3667 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_CLR_MSK 0xfff80000
3668 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK register field. */
3669 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_RESET 0x0
3670 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK field value from a register. */
3671 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_GET(value) (((value) & 0x0007ffff) >> 0)
3672 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK register field value suitable for setting the register. */
3673 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_SET(value) (((value) << 0) & 0x0007ffff)
3674 
3675 #ifndef __ASSEMBLY__
3676 /*
3677  * WARNING: The C register and register group struct declarations are provided for
3678  * convenience and illustrative purposes. They should, however, be used with
3679  * caution as the C language standard provides no guarantees about the alignment or
3680  * atomicity of device memory accesses. The recommended practice for writing
3681  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3682  * alt_write_word() functions.
3683  *
3684  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK.
3685  */
3686 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_s
3687 {
3688  uint32_t FILTERS_3_ROUTEIDMASK : 19; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK */
3689  uint32_t : 13; /* *UNDEFINED* */
3690 };
3691 
3692 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK. */
3693 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_s ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_t;
3694 #endif /* __ASSEMBLY__ */
3695 
3696 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK register. */
3697 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_RESET 0x00000000
3698 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK register from the beginning of the component. */
3699 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_OFST 0xfc
3700 
3701 /*
3702  * Register : ddr_T_main_Probe_Filters_3_AddrBase_Low
3703  *
3704  *
3705  * Register Layout
3706  *
3707  * Bits | Access | Reset | Description
3708  * :-------|:-------|:------|:--------------------------------------------------------------
3709  * [31:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW
3710  *
3711  */
3712 /*
3713  * Field : FILTERS_3_ADDRBASE_LOW
3714  *
3715  * Address LSB register.
3716  *
3717  * Field Access Macros:
3718  *
3719  */
3720 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW register field. */
3721 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_LSB 0
3722 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW register field. */
3723 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_MSB 31
3724 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW register field. */
3725 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_WIDTH 32
3726 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW register field value. */
3727 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_SET_MSK 0xffffffff
3728 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW register field value. */
3729 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_CLR_MSK 0x00000000
3730 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW register field. */
3731 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_RESET 0x0
3732 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW field value from a register. */
3733 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
3734 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW register field value suitable for setting the register. */
3735 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
3736 
3737 #ifndef __ASSEMBLY__
3738 /*
3739  * WARNING: The C register and register group struct declarations are provided for
3740  * convenience and illustrative purposes. They should, however, be used with
3741  * caution as the C language standard provides no guarantees about the alignment or
3742  * atomicity of device memory accesses. The recommended practice for writing
3743  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3744  * alt_write_word() functions.
3745  *
3746  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW.
3747  */
3748 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_s
3749 {
3750  uint32_t FILTERS_3_ADDRBASE_LOW : 32; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW */
3751 };
3752 
3753 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW. */
3754 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_s ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_t;
3755 #endif /* __ASSEMBLY__ */
3756 
3757 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW register. */
3758 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_RESET 0x00000000
3759 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW register from the beginning of the component. */
3760 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_OFST 0x100
3761 
3762 /*
3763  * Register : ddr_T_main_Probe_Filters_3_WindowSize
3764  *
3765  *
3766  * Register Layout
3767  *
3768  * Bits | Access | Reset | Description
3769  * :-------|:-------|:--------|:----------------------------------------------------------
3770  * [5:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE
3771  * [31:6] | ??? | Unknown | *UNDEFINED*
3772  *
3773  */
3774 /*
3775  * Field : FILTERS_3_WINDOWSIZE
3776  *
3777  * Register WindowSize contains the encoded address mask used to filter packets.
3778  * The effective Mask value is equal to ~(2max(WindowSize, packet.Len) - 1). A
3779  * packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows
3780  * filteringof packets having an intersection with the AddrBase/WindowSize burst
3781  * aligned region, even if the region is smaller than the packet.
3782  *
3783  * Field Access Macros:
3784  *
3785  */
3786 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE register field. */
3787 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_LSB 0
3788 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE register field. */
3789 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_MSB 5
3790 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE register field. */
3791 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_WIDTH 6
3792 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE register field value. */
3793 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_SET_MSK 0x0000003f
3794 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE register field value. */
3795 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_CLR_MSK 0xffffffc0
3796 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE register field. */
3797 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_RESET 0x0
3798 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE field value from a register. */
3799 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
3800 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE register field value suitable for setting the register. */
3801 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
3802 
3803 #ifndef __ASSEMBLY__
3804 /*
3805  * WARNING: The C register and register group struct declarations are provided for
3806  * convenience and illustrative purposes. They should, however, be used with
3807  * caution as the C language standard provides no guarantees about the alignment or
3808  * atomicity of device memory accesses. The recommended practice for writing
3809  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3810  * alt_write_word() functions.
3811  *
3812  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE.
3813  */
3814 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_s
3815 {
3816  uint32_t FILTERS_3_WINDOWSIZE : 6; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE */
3817  uint32_t : 26; /* *UNDEFINED* */
3818 };
3819 
3820 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE. */
3821 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_t;
3822 #endif /* __ASSEMBLY__ */
3823 
3824 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE register. */
3825 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_RESET 0x00000000
3826 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE register from the beginning of the component. */
3827 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_OFST 0x108
3828 
3829 /*
3830  * Register : ddr_T_main_Probe_Filters_3_SecurityBase
3831  *
3832  *
3833  * Register Layout
3834  *
3835  * Bits | Access | Reset | Description
3836  * :-------|:-------|:--------|:--------------------------------------------------------------
3837  * [2:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE
3838  * [31:3] | ??? | Unknown | *UNDEFINED*
3839  *
3840  */
3841 /*
3842  * Field : FILTERS_3_SECURITYBASE
3843  *
3844  * Register SecurityBase contains the security base used to filter packets.
3845  *
3846  * Field Access Macros:
3847  *
3848  */
3849 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE register field. */
3850 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_LSB 0
3851 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE register field. */
3852 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_MSB 2
3853 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE register field. */
3854 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_WIDTH 3
3855 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE register field value. */
3856 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_SET_MSK 0x00000007
3857 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE register field value. */
3858 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_CLR_MSK 0xfffffff8
3859 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE register field. */
3860 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_RESET 0x0
3861 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE field value from a register. */
3862 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
3863 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE register field value suitable for setting the register. */
3864 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
3865 
3866 #ifndef __ASSEMBLY__
3867 /*
3868  * WARNING: The C register and register group struct declarations are provided for
3869  * convenience and illustrative purposes. They should, however, be used with
3870  * caution as the C language standard provides no guarantees about the alignment or
3871  * atomicity of device memory accesses. The recommended practice for writing
3872  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3873  * alt_write_word() functions.
3874  *
3875  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE.
3876  */
3877 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_s
3878 {
3879  uint32_t FILTERS_3_SECURITYBASE : 3; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE */
3880  uint32_t : 29; /* *UNDEFINED* */
3881 };
3882 
3883 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE. */
3884 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_t;
3885 #endif /* __ASSEMBLY__ */
3886 
3887 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE register. */
3888 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_RESET 0x00000000
3889 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE register from the beginning of the component. */
3890 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_OFST 0x10c
3891 
3892 /*
3893  * Register : ddr_T_main_Probe_Filters_3_SecurityMask
3894  *
3895  *
3896  * Register Layout
3897  *
3898  * Bits | Access | Reset | Description
3899  * :-------|:-------|:--------|:------------------------------------------------------------
3900  * [2:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK
3901  * [31:3] | ??? | Unknown | *UNDEFINED*
3902  *
3903  */
3904 /*
3905  * Field : FILTERS_3_SECURITYMASK
3906  *
3907  * Register SecurityMask is contains the security mask used to filter packets. A
3908  * packet is a candidate when: packet.Security & SecurityMask = SecurityBase &
3909  * SecurityMasks.
3910  *
3911  * Field Access Macros:
3912  *
3913  */
3914 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK register field. */
3915 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_LSB 0
3916 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK register field. */
3917 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_MSB 2
3918 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK register field. */
3919 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_WIDTH 3
3920 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK register field value. */
3921 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_SET_MSK 0x00000007
3922 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK register field value. */
3923 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_CLR_MSK 0xfffffff8
3924 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK register field. */
3925 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_RESET 0x0
3926 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK field value from a register. */
3927 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
3928 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK register field value suitable for setting the register. */
3929 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
3930 
3931 #ifndef __ASSEMBLY__
3932 /*
3933  * WARNING: The C register and register group struct declarations are provided for
3934  * convenience and illustrative purposes. They should, however, be used with
3935  * caution as the C language standard provides no guarantees about the alignment or
3936  * atomicity of device memory accesses. The recommended practice for writing
3937  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3938  * alt_write_word() functions.
3939  *
3940  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK.
3941  */
3942 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_s
3943 {
3944  uint32_t FILTERS_3_SECURITYMASK : 3; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK */
3945  uint32_t : 29; /* *UNDEFINED* */
3946 };
3947 
3948 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK. */
3949 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_s ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_t;
3950 #endif /* __ASSEMBLY__ */
3951 
3952 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK register. */
3953 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_RESET 0x00000000
3954 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK register from the beginning of the component. */
3955 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_OFST 0x110
3956 
3957 /*
3958  * Register : ddr_T_main_Probe_Filters_3_Opcode
3959  *
3960  * Packet Probe register Opcode is a 4-bit register that selects candidate packets
3961  * based on packet opcodes (0 disables the filter):
3962  *
3963  * Register Layout
3964  *
3965  * Bits | Access | Reset | Description
3966  * :-------|:-------|:--------|:-------------------------------------------
3967  * [0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN
3968  * [1] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN
3969  * [2] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN
3970  * [3] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN
3971  * [31:4] | ??? | Unknown | *UNDEFINED*
3972  *
3973  */
3974 /*
3975  * Field : RDEN
3976  *
3977  * Selects RD packets.
3978  *
3979  * Field Access Macros:
3980  *
3981  */
3982 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN register field. */
3983 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_LSB 0
3984 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN register field. */
3985 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_MSB 0
3986 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN register field. */
3987 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_WIDTH 1
3988 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN register field value. */
3989 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_SET_MSK 0x00000001
3990 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN register field value. */
3991 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_CLR_MSK 0xfffffffe
3992 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN register field. */
3993 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_RESET 0x0
3994 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN field value from a register. */
3995 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
3996 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN register field value suitable for setting the register. */
3997 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
3998 
3999 /*
4000  * Field : WREN
4001  *
4002  * Selects WR packets.
4003  *
4004  * Field Access Macros:
4005  *
4006  */
4007 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN register field. */
4008 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_LSB 1
4009 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN register field. */
4010 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_MSB 1
4011 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN register field. */
4012 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_WIDTH 1
4013 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN register field value. */
4014 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_SET_MSK 0x00000002
4015 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN register field value. */
4016 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_CLR_MSK 0xfffffffd
4017 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN register field. */
4018 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_RESET 0x0
4019 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN field value from a register. */
4020 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
4021 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN register field value suitable for setting the register. */
4022 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
4023 
4024 /*
4025  * Field : LOCKEN
4026  *
4027  * Selects RDX-WR, RDL, WRC and Linked sequence.
4028  *
4029  * Field Access Macros:
4030  *
4031  */
4032 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN register field. */
4033 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_LSB 2
4034 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN register field. */
4035 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_MSB 2
4036 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN register field. */
4037 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_WIDTH 1
4038 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN register field value. */
4039 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_SET_MSK 0x00000004
4040 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN register field value. */
4041 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
4042 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN register field. */
4043 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_RESET 0x0
4044 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN field value from a register. */
4045 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
4046 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN register field value suitable for setting the register. */
4047 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
4048 
4049 /*
4050  * Field : URGEN
4051  *
4052  * Selects URG packets (urgency).
4053  *
4054  * Field Access Macros:
4055  *
4056  */
4057 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN register field. */
4058 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_LSB 3
4059 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN register field. */
4060 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_MSB 3
4061 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN register field. */
4062 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_WIDTH 1
4063 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN register field value. */
4064 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_SET_MSK 0x00000008
4065 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN register field value. */
4066 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_CLR_MSK 0xfffffff7
4067 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN register field. */
4068 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_RESET 0x0
4069 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN field value from a register. */
4070 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
4071 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN register field value suitable for setting the register. */
4072 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
4073 
4074 #ifndef __ASSEMBLY__
4075 /*
4076  * WARNING: The C register and register group struct declarations are provided for
4077  * convenience and illustrative purposes. They should, however, be used with
4078  * caution as the C language standard provides no guarantees about the alignment or
4079  * atomicity of device memory accesses. The recommended practice for writing
4080  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4081  * alt_write_word() functions.
4082  *
4083  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE.
4084  */
4085 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_s
4086 {
4087  uint32_t RDEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN */
4088  uint32_t WREN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN */
4089  uint32_t LOCKEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN */
4090  uint32_t URGEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN */
4091  uint32_t : 28; /* *UNDEFINED* */
4092 };
4093 
4094 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE. */
4095 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_t;
4096 #endif /* __ASSEMBLY__ */
4097 
4098 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE register. */
4099 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RESET 0x00000000
4100 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE register from the beginning of the component. */
4101 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_OFST 0x114
4102 
4103 /*
4104  * Register : ddr_T_main_Probe_Filters_3_Status
4105  *
4106  * Register Status is 2-bit register that selects candidate packets based on packet
4107  * status.
4108  *
4109  * Register Layout
4110  *
4111  * Bits | Access | Reset | Description
4112  * :-------|:-------|:--------|:----------------------------------------
4113  * [0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN
4114  * [1] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN
4115  * [31:2] | ??? | Unknown | *UNDEFINED*
4116  *
4117  */
4118 /*
4119  * Field : REQEN
4120  *
4121  * Selects REQ status packets.
4122  *
4123  * Field Access Macros:
4124  *
4125  */
4126 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN register field. */
4127 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_LSB 0
4128 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN register field. */
4129 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_MSB 0
4130 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN register field. */
4131 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_WIDTH 1
4132 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN register field value. */
4133 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_SET_MSK 0x00000001
4134 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN register field value. */
4135 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_CLR_MSK 0xfffffffe
4136 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN register field. */
4137 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_RESET 0x0
4138 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN field value from a register. */
4139 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_GET(value) (((value) & 0x00000001) >> 0)
4140 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN register field value suitable for setting the register. */
4141 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_SET(value) (((value) << 0) & 0x00000001)
4142 
4143 /*
4144  * Field : RSPEN
4145  *
4146  * Selects RSP and FAIL-CONT status packets.
4147  *
4148  * Field Access Macros:
4149  *
4150  */
4151 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN register field. */
4152 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_LSB 1
4153 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN register field. */
4154 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_MSB 1
4155 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN register field. */
4156 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_WIDTH 1
4157 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN register field value. */
4158 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_SET_MSK 0x00000002
4159 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN register field value. */
4160 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_CLR_MSK 0xfffffffd
4161 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN register field. */
4162 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_RESET 0x0
4163 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN field value from a register. */
4164 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
4165 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN register field value suitable for setting the register. */
4166 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_SET(value) (((value) << 1) & 0x00000002)
4167 
4168 #ifndef __ASSEMBLY__
4169 /*
4170  * WARNING: The C register and register group struct declarations are provided for
4171  * convenience and illustrative purposes. They should, however, be used with
4172  * caution as the C language standard provides no guarantees about the alignment or
4173  * atomicity of device memory accesses. The recommended practice for writing
4174  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4175  * alt_write_word() functions.
4176  *
4177  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT.
4178  */
4179 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_s
4180 {
4181  uint32_t REQEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN */
4182  uint32_t RSPEN : 1; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN */
4183  uint32_t : 30; /* *UNDEFINED* */
4184 };
4185 
4186 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT. */
4187 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_s ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_t;
4188 #endif /* __ASSEMBLY__ */
4189 
4190 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT register. */
4191 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RESET 0x00000000
4192 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT register from the beginning of the component. */
4193 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_OFST 0x118
4194 
4195 /*
4196  * Register : ddr_T_main_Probe_Filters_3_Length
4197  *
4198  *
4199  * Register Layout
4200  *
4201  * Bits | Access | Reset | Description
4202  * :-------|:-------|:--------|:--------------------------------------------
4203  * [3:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN
4204  * [31:4] | ??? | Unknown | *UNDEFINED*
4205  *
4206  */
4207 /*
4208  * Field : FILTERS_3_LENGTH
4209  *
4210  * Register Length is 4-bit register that selects candidate packets if their number
4211  * of bytes is less than or equal to 2**Length.
4212  *
4213  * Field Access Macros:
4214  *
4215  */
4216 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN register field. */
4217 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_LSB 0
4218 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN register field. */
4219 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_MSB 3
4220 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN register field. */
4221 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_WIDTH 4
4222 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN register field value. */
4223 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_SET_MSK 0x0000000f
4224 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN register field value. */
4225 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_CLR_MSK 0xfffffff0
4226 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN register field. */
4227 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_RESET 0x0
4228 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN field value from a register. */
4229 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_GET(value) (((value) & 0x0000000f) >> 0)
4230 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN register field value suitable for setting the register. */
4231 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_SET(value) (((value) << 0) & 0x0000000f)
4232 
4233 #ifndef __ASSEMBLY__
4234 /*
4235  * WARNING: The C register and register group struct declarations are provided for
4236  * convenience and illustrative purposes. They should, however, be used with
4237  * caution as the C language standard provides no guarantees about the alignment or
4238  * atomicity of device memory accesses. The recommended practice for writing
4239  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4240  * alt_write_word() functions.
4241  *
4242  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN.
4243  */
4244 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_s
4245 {
4246  uint32_t FILTERS_3_LENGTH : 4; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN */
4247  uint32_t : 28; /* *UNDEFINED* */
4248 };
4249 
4250 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN. */
4251 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_s ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_t;
4252 #endif /* __ASSEMBLY__ */
4253 
4254 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN register. */
4255 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_RESET 0x00000000
4256 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN register from the beginning of the component. */
4257 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_OFST 0x11c
4258 
4259 /*
4260  * Register : ddr_T_main_Probe_Filters_3_Urgency
4261  *
4262  *
4263  * Register Layout
4264  *
4265  * Bits | Access | Reset | Description
4266  * :-------|:-------|:--------|:----------------------------------------------------
4267  * [1:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY
4268  * [31:2] | ??? | Unknown | *UNDEFINED*
4269  *
4270  */
4271 /*
4272  * Field : FILTERS_3_URGENCY
4273  *
4274  * Register Urgency contains the minimum urgency level used to filter packets. A
4275  * packet is a candidate when its socket urgency is greater than or equal to the
4276  * urgency specified in the register.
4277  *
4278  * Field Access Macros:
4279  *
4280  */
4281 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY register field. */
4282 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_LSB 0
4283 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY register field. */
4284 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_MSB 1
4285 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY register field. */
4286 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_WIDTH 2
4287 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY register field value. */
4288 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_SET_MSK 0x00000003
4289 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY register field value. */
4290 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_CLR_MSK 0xfffffffc
4291 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY register field. */
4292 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_RESET 0x0
4293 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY field value from a register. */
4294 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
4295 /* Produces a ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY register field value suitable for setting the register. */
4296 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_SET(value) (((value) << 0) & 0x00000003)
4297 
4298 #ifndef __ASSEMBLY__
4299 /*
4300  * WARNING: The C register and register group struct declarations are provided for
4301  * convenience and illustrative purposes. They should, however, be used with
4302  * caution as the C language standard provides no guarantees about the alignment or
4303  * atomicity of device memory accesses. The recommended practice for writing
4304  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4305  * alt_write_word() functions.
4306  *
4307  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY.
4308  */
4309 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_s
4310 {
4311  uint32_t FILTERS_3_URGENCY : 2; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY */
4312  uint32_t : 30; /* *UNDEFINED* */
4313 };
4314 
4315 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY. */
4316 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_s ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_t;
4317 #endif /* __ASSEMBLY__ */
4318 
4319 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY register. */
4320 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_RESET 0x00000000
4321 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY register from the beginning of the component. */
4322 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_OFST 0x120
4323 
4324 /*
4325  * Register : ddr_T_main_Probe_Counters_0_Src
4326  *
4327  * Register CntSrc indicates the event source used to increment the counter.
4328  * Unassigned values (non-existing Press level or ExtEvent index, or unimplemented
4329  * Filter) are equivalent to OFF.
4330  *
4331  * Register Layout
4332  *
4333  * Bits | Access | Reset | Description
4334  * :-------|:-------|:--------|:-------------------------------------------
4335  * [4:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT
4336  * [31:5] | ??? | Unknown | *UNDEFINED*
4337  *
4338  */
4339 /*
4340  * Field : INTEVENT
4341  *
4342  * Internal packet event
4343  *
4344  * Field Access Macros:
4345  *
4346  */
4347 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT register field. */
4348 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_LSB 0
4349 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT register field. */
4350 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_MSB 4
4351 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT register field. */
4352 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_WIDTH 5
4353 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT register field value. */
4354 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_SET_MSK 0x0000001f
4355 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT register field value. */
4356 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_CLR_MSK 0xffffffe0
4357 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT register field. */
4358 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_RESET 0x0
4359 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT field value from a register. */
4360 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
4361 /* Produces a ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT register field value suitable for setting the register. */
4362 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
4363 
4364 #ifndef __ASSEMBLY__
4365 /*
4366  * WARNING: The C register and register group struct declarations are provided for
4367  * convenience and illustrative purposes. They should, however, be used with
4368  * caution as the C language standard provides no guarantees about the alignment or
4369  * atomicity of device memory accesses. The recommended practice for writing
4370  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4371  * alt_write_word() functions.
4372  *
4373  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC.
4374  */
4375 struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_s
4376 {
4377  uint32_t INTEVENT : 5; /* ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT */
4378  uint32_t : 27; /* *UNDEFINED* */
4379 };
4380 
4381 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC. */
4382 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_s ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_t;
4383 #endif /* __ASSEMBLY__ */
4384 
4385 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC register. */
4386 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_RESET 0x00000000
4387 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC register from the beginning of the component. */
4388 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_OFST 0x138
4389 
4390 /*
4391  * Register : ddr_T_main_Probe_Counters_0_AlarmMode
4392  *
4393  *
4394  * Register Layout
4395  *
4396  * Bits | Access | Reset | Description
4397  * :-------|:-------|:--------|:--------------------------------------------------------
4398  * [1:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD
4399  * [31:2] | ??? | Unknown | *UNDEFINED*
4400  *
4401  */
4402 /*
4403  * Field : COUNTERS_0_ALARMMODE
4404  *
4405  * Register AlarmMode is a 2-bit register that is present when parameter
4406  * statisticsCounterAlarm is set to True. The register defines the statistics-alarm
4407  * behavior of the counter.
4408  *
4409  * Field Access Macros:
4410  *
4411  */
4412 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field. */
4413 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_LSB 0
4414 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field. */
4415 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_MSB 1
4416 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field. */
4417 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_WIDTH 2
4418 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field value. */
4419 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_SET_MSK 0x00000003
4420 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field value. */
4421 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_CLR_MSK 0xfffffffc
4422 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field. */
4423 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_RESET 0x0
4424 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD field value from a register. */
4425 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
4426 /* Produces a ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field value suitable for setting the register. */
4427 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
4428 
4429 #ifndef __ASSEMBLY__
4430 /*
4431  * WARNING: The C register and register group struct declarations are provided for
4432  * convenience and illustrative purposes. They should, however, be used with
4433  * caution as the C language standard provides no guarantees about the alignment or
4434  * atomicity of device memory accesses. The recommended practice for writing
4435  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4436  * alt_write_word() functions.
4437  *
4438  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD.
4439  */
4440 struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_s
4441 {
4442  uint32_t COUNTERS_0_ALARMMODE : 2; /* ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD */
4443  uint32_t : 30; /* *UNDEFINED* */
4444 };
4445 
4446 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD. */
4447 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_s ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_t;
4448 #endif /* __ASSEMBLY__ */
4449 
4450 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD register. */
4451 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_RESET 0x00000000
4452 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD register from the beginning of the component. */
4453 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_OFST 0x13c
4454 
4455 /*
4456  * Register : ddr_T_main_Probe_Counters_0_Val
4457  *
4458  *
4459  * Register Layout
4460  *
4461  * Bits | Access | Reset | Description
4462  * :--------|:-------|:--------|:----------------------------------------------
4463  * [15:0] | R | 0x0 | ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL
4464  * [31:16] | ??? | Unknown | *UNDEFINED*
4465  *
4466  */
4467 /*
4468  * Field : COUNTERS_0_VAL
4469  *
4470  * Register Val is a read-only register that is always present. The register
4471  * containsthe statistics counter value either pending StatAlarm output, or when
4472  * statisticscollection is suspended subsequent to triggers or signal statSuspend.
4473  *
4474  * Field Access Macros:
4475  *
4476  */
4477 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL register field. */
4478 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_LSB 0
4479 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL register field. */
4480 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_MSB 15
4481 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL register field. */
4482 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_WIDTH 16
4483 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL register field value. */
4484 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_SET_MSK 0x0000ffff
4485 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL register field value. */
4486 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_CLR_MSK 0xffff0000
4487 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL register field. */
4488 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_RESET 0x0
4489 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL field value from a register. */
4490 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
4491 /* Produces a ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL register field value suitable for setting the register. */
4492 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_SET(value) (((value) << 0) & 0x0000ffff)
4493 
4494 #ifndef __ASSEMBLY__
4495 /*
4496  * WARNING: The C register and register group struct declarations are provided for
4497  * convenience and illustrative purposes. They should, however, be used with
4498  * caution as the C language standard provides no guarantees about the alignment or
4499  * atomicity of device memory accesses. The recommended practice for writing
4500  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4501  * alt_write_word() functions.
4502  *
4503  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL.
4504  */
4505 struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_s
4506 {
4507  const uint32_t COUNTERS_0_VAL : 16; /* ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL */
4508  uint32_t : 16; /* *UNDEFINED* */
4509 };
4510 
4511 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL. */
4512 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_s ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_t;
4513 #endif /* __ASSEMBLY__ */
4514 
4515 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL register. */
4516 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_RESET 0x00000000
4517 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL register from the beginning of the component. */
4518 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_OFST 0x140
4519 
4520 /*
4521  * Register : ddr_T_main_Probe_Counters_1_Src
4522  *
4523  * Register CntSrc indicates the event source used to increment the counter.
4524  * Unassigned values (non-existing Press level or ExtEvent index, or unimplemented
4525  * Filter) are equivalent to OFF.
4526  *
4527  * Register Layout
4528  *
4529  * Bits | Access | Reset | Description
4530  * :-------|:-------|:--------|:-------------------------------------------
4531  * [4:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT
4532  * [31:5] | ??? | Unknown | *UNDEFINED*
4533  *
4534  */
4535 /*
4536  * Field : INTEVENT
4537  *
4538  * Internal packet event
4539  *
4540  * Field Access Macros:
4541  *
4542  */
4543 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT register field. */
4544 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_LSB 0
4545 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT register field. */
4546 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_MSB 4
4547 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT register field. */
4548 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_WIDTH 5
4549 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT register field value. */
4550 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_SET_MSK 0x0000001f
4551 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT register field value. */
4552 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_CLR_MSK 0xffffffe0
4553 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT register field. */
4554 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_RESET 0x0
4555 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT field value from a register. */
4556 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
4557 /* Produces a ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT register field value suitable for setting the register. */
4558 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
4559 
4560 #ifndef __ASSEMBLY__
4561 /*
4562  * WARNING: The C register and register group struct declarations are provided for
4563  * convenience and illustrative purposes. They should, however, be used with
4564  * caution as the C language standard provides no guarantees about the alignment or
4565  * atomicity of device memory accesses. The recommended practice for writing
4566  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4567  * alt_write_word() functions.
4568  *
4569  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC.
4570  */
4571 struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_s
4572 {
4573  uint32_t INTEVENT : 5; /* ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT */
4574  uint32_t : 27; /* *UNDEFINED* */
4575 };
4576 
4577 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC. */
4578 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_s ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_t;
4579 #endif /* __ASSEMBLY__ */
4580 
4581 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC register. */
4582 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_RESET 0x00000000
4583 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC register from the beginning of the component. */
4584 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_OFST 0x14c
4585 
4586 /*
4587  * Register : ddr_T_main_Probe_Counters_1_AlarmMode
4588  *
4589  *
4590  * Register Layout
4591  *
4592  * Bits | Access | Reset | Description
4593  * :-------|:-------|:--------|:--------------------------------------------------------
4594  * [1:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD
4595  * [31:2] | ??? | Unknown | *UNDEFINED*
4596  *
4597  */
4598 /*
4599  * Field : COUNTERS_1_ALARMMODE
4600  *
4601  * Register AlarmMode is a 2-bit register that is present when parameter
4602  * statisticsCounterAlarm is set to True. The register defines the statistics-alarm
4603  * behavior of the counter.
4604  *
4605  * Field Access Macros:
4606  *
4607  */
4608 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field. */
4609 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_LSB 0
4610 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field. */
4611 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_MSB 1
4612 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field. */
4613 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_WIDTH 2
4614 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field value. */
4615 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_SET_MSK 0x00000003
4616 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field value. */
4617 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_CLR_MSK 0xfffffffc
4618 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field. */
4619 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_RESET 0x0
4620 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD field value from a register. */
4621 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
4622 /* Produces a ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field value suitable for setting the register. */
4623 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
4624 
4625 #ifndef __ASSEMBLY__
4626 /*
4627  * WARNING: The C register and register group struct declarations are provided for
4628  * convenience and illustrative purposes. They should, however, be used with
4629  * caution as the C language standard provides no guarantees about the alignment or
4630  * atomicity of device memory accesses. The recommended practice for writing
4631  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4632  * alt_write_word() functions.
4633  *
4634  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD.
4635  */
4636 struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_s
4637 {
4638  uint32_t COUNTERS_1_ALARMMODE : 2; /* ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD */
4639  uint32_t : 30; /* *UNDEFINED* */
4640 };
4641 
4642 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD. */
4643 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_s ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_t;
4644 #endif /* __ASSEMBLY__ */
4645 
4646 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD register. */
4647 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_RESET 0x00000000
4648 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD register from the beginning of the component. */
4649 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_OFST 0x150
4650 
4651 /*
4652  * Register : ddr_T_main_Probe_Counters_1_Val
4653  *
4654  *
4655  * Register Layout
4656  *
4657  * Bits | Access | Reset | Description
4658  * :--------|:-------|:--------|:----------------------------------------------
4659  * [15:0] | R | 0x0 | ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL
4660  * [31:16] | ??? | Unknown | *UNDEFINED*
4661  *
4662  */
4663 /*
4664  * Field : COUNTERS_1_VAL
4665  *
4666  * Register Val is a read-only register that is always present. The register
4667  * containsthe statistics counter value either pending StatAlarm output, or when
4668  * statisticscollection is suspended subsequent to triggers or signal statSuspend.
4669  *
4670  * Field Access Macros:
4671  *
4672  */
4673 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL register field. */
4674 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_LSB 0
4675 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL register field. */
4676 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_MSB 15
4677 /* The width in bits of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL register field. */
4678 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_WIDTH 16
4679 /* The mask used to set the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL register field value. */
4680 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_SET_MSK 0x0000ffff
4681 /* The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL register field value. */
4682 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_CLR_MSK 0xffff0000
4683 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL register field. */
4684 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_RESET 0x0
4685 /* Extracts the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL field value from a register. */
4686 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
4687 /* Produces a ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL register field value suitable for setting the register. */
4688 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_SET(value) (((value) << 0) & 0x0000ffff)
4689 
4690 #ifndef __ASSEMBLY__
4691 /*
4692  * WARNING: The C register and register group struct declarations are provided for
4693  * convenience and illustrative purposes. They should, however, be used with
4694  * caution as the C language standard provides no guarantees about the alignment or
4695  * atomicity of device memory accesses. The recommended practice for writing
4696  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4697  * alt_write_word() functions.
4698  *
4699  * The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL.
4700  */
4701 struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_s
4702 {
4703  const uint32_t COUNTERS_1_VAL : 16; /* ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL */
4704  uint32_t : 16; /* *UNDEFINED* */
4705 };
4706 
4707 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL. */
4708 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_s ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_t;
4709 #endif /* __ASSEMBLY__ */
4710 
4711 /* The reset value of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL register. */
4712 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_RESET 0x00000000
4713 /* The byte offset of the ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL register from the beginning of the component. */
4714 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_OFST 0x154
4715 
4716 #ifndef __ASSEMBLY__
4717 /*
4718  * WARNING: The C register and register group struct declarations are provided for
4719  * convenience and illustrative purposes. They should, however, be used with
4720  * caution as the C language standard provides no guarantees about the alignment or
4721  * atomicity of device memory accesses. The recommended practice for writing
4722  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4723  * alt_write_word() functions.
4724  *
4725  * The struct declaration for register group ALT_NOC_MPU_DDR_T_PRB.
4726  */
4727 struct ALT_NOC_MPU_DDR_T_PRB_s
4728 {
4729  ALT_NOC_MPU_DDR_T_PRB_COREID_t ddr_T_main_Probe_Id_CoreId; /* ALT_NOC_MPU_DDR_T_PRB_COREID */
4730  ALT_NOC_MPU_DDR_T_PRB_REVID_t ddr_T_main_Probe_Id_RevisionId; /* ALT_NOC_MPU_DDR_T_PRB_REVID */
4731  ALT_NOC_MPU_DDR_T_PRB_MAINCTL_t ddr_T_main_Probe_MainCtl; /* ALT_NOC_MPU_DDR_T_PRB_MAINCTL */
4732  ALT_NOC_MPU_DDR_T_PRB_CFGCTL_t ddr_T_main_Probe_CfgCtl; /* ALT_NOC_MPU_DDR_T_PRB_CFGCTL */
4733  volatile uint32_t _pad_0x10_0x13; /* *UNDEFINED* */
4734  ALT_NOC_MPU_DDR_T_PRB_FLTLUT_t ddr_T_main_Probe_FilterLut; /* ALT_NOC_MPU_DDR_T_PRB_FLTLUT */
4735  ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_t ddr_T_main_Probe_TraceAlarmEn; /* ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN */
4736  ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_t ddr_T_main_Probe_TraceAlarmStatus; /* ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT */
4737  ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_t ddr_T_main_Probe_TraceAlarmClr; /* ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR */
4738  ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_t ddr_T_main_Probe_StatPeriod; /* ALT_NOC_MPU_DDR_T_PRB_STATPERIOD */
4739  ALT_NOC_MPU_DDR_T_PRB_STATGO_t ddr_T_main_Probe_StatGo; /* ALT_NOC_MPU_DDR_T_PRB_STATGO */
4740  ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_t ddr_T_main_Probe_StatAlarmMin; /* ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN */
4741  ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_t ddr_T_main_Probe_StatAlarmMax; /* ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX */
4742  ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_t ddr_T_main_Probe_StatAlarmStatus; /* ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT */
4743  ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_t ddr_T_main_Probe_StatAlarmClr; /* ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR */
4744  ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_t ddr_T_main_Probe_StatAlarmEn; /* ALT_NOC_MPU_DDR_T_PRB_STATALARMEN */
4745  volatile uint32_t _pad_0x40_0x43; /* *UNDEFINED* */
4746  ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_t ddr_T_main_Probe_Filters_0_RouteIdBase; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE */
4747  ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_t ddr_T_main_Probe_Filters_0_RouteIdMask; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK */
4748  ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_t ddr_T_main_Probe_Filters_0_AddrBase_Low; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW */
4749  volatile uint32_t _pad_0x50_0x53; /* *UNDEFINED* */
4750  ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_t ddr_T_main_Probe_Filters_0_WindowSize; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE */
4751  ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_t ddr_T_main_Probe_Filters_0_SecurityBase; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE */
4752  ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_t ddr_T_main_Probe_Filters_0_SecurityMask; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK */
4753  ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_t ddr_T_main_Probe_Filters_0_Opcode; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE */
4754  ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_t ddr_T_main_Probe_Filters_0_Status; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT */
4755  ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_t ddr_T_main_Probe_Filters_0_Length; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN */
4756  ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_t ddr_T_main_Probe_Filters_0_Urgency; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY */
4757  volatile uint32_t _pad_0x70_0x7f[4]; /* *UNDEFINED* */
4758  ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_t ddr_T_main_Probe_Filters_1_RouteIdBase; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE */
4759  ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_t ddr_T_main_Probe_Filters_1_RouteIdMask; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK */
4760  ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_t ddr_T_main_Probe_Filters_1_AddrBase_Low; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW */
4761  volatile uint32_t _pad_0x8c_0x8f; /* *UNDEFINED* */
4762  ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_t ddr_T_main_Probe_Filters_1_WindowSize; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE */
4763  ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_t ddr_T_main_Probe_Filters_1_SecurityBase; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE */
4764  ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_t ddr_T_main_Probe_Filters_1_SecurityMask; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK */
4765  ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_t ddr_T_main_Probe_Filters_1_Opcode; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE */
4766  ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_t ddr_T_main_Probe_Filters_1_Status; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT */
4767  ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_t ddr_T_main_Probe_Filters_1_Length; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN */
4768  ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_t ddr_T_main_Probe_Filters_1_Urgency; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY */
4769  volatile uint32_t _pad_0xac_0xbb[4]; /* *UNDEFINED* */
4770  ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_t ddr_T_main_Probe_Filters_2_RouteIdBase; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE */
4771  ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_t ddr_T_main_Probe_Filters_2_RouteIdMask; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK */
4772  ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_t ddr_T_main_Probe_Filters_2_AddrBase_Low; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW */
4773  volatile uint32_t _pad_0xc8_0xcb; /* *UNDEFINED* */
4774  ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_t ddr_T_main_Probe_Filters_2_WindowSize; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE */
4775  ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_t ddr_T_main_Probe_Filters_2_SecurityBase; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE */
4776  ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_t ddr_T_main_Probe_Filters_2_SecurityMask; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK */
4777  ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_t ddr_T_main_Probe_Filters_2_Opcode; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE */
4778  ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_t ddr_T_main_Probe_Filters_2_Status; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT */
4779  ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_t ddr_T_main_Probe_Filters_2_Length; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN */
4780  ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_t ddr_T_main_Probe_Filters_2_Urgency; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY */
4781  volatile uint32_t _pad_0xe8_0xf7[4]; /* *UNDEFINED* */
4782  ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_t ddr_T_main_Probe_Filters_3_RouteIdBase; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE */
4783  ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_t ddr_T_main_Probe_Filters_3_RouteIdMask; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK */
4784  ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_t ddr_T_main_Probe_Filters_3_AddrBase_Low; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW */
4785  volatile uint32_t _pad_0x104_0x107; /* *UNDEFINED* */
4786  ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_t ddr_T_main_Probe_Filters_3_WindowSize; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE */
4787  ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_t ddr_T_main_Probe_Filters_3_SecurityBase; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE */
4788  ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_t ddr_T_main_Probe_Filters_3_SecurityMask; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK */
4789  ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_t ddr_T_main_Probe_Filters_3_Opcode; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE */
4790  ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_t ddr_T_main_Probe_Filters_3_Status; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT */
4791  ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_t ddr_T_main_Probe_Filters_3_Length; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN */
4792  ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_t ddr_T_main_Probe_Filters_3_Urgency; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY */
4793  volatile uint32_t _pad_0x124_0x137[5]; /* *UNDEFINED* */
4794  ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_t ddr_T_main_Probe_Counters_0_Src; /* ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC */
4795  ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_t ddr_T_main_Probe_Counters_0_AlarmMode; /* ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD */
4796  ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_t ddr_T_main_Probe_Counters_0_Val; /* ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL */
4797  volatile uint32_t _pad_0x144_0x14b[2]; /* *UNDEFINED* */
4798  ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_t ddr_T_main_Probe_Counters_1_Src; /* ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC */
4799  ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_t ddr_T_main_Probe_Counters_1_AlarmMode; /* ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD */
4800  ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_t ddr_T_main_Probe_Counters_1_Val; /* ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL */
4801  volatile uint32_t _pad_0x158_0x400[170]; /* *UNDEFINED* */
4802 };
4803 
4804 /* The typedef declaration for register group ALT_NOC_MPU_DDR_T_PRB. */
4805 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_s ALT_NOC_MPU_DDR_T_PRB_t;
4806 /* The struct declaration for the raw register contents of register group ALT_NOC_MPU_DDR_T_PRB. */
4807 struct ALT_NOC_MPU_DDR_T_PRB_raw_s
4808 {
4809  volatile uint32_t ddr_T_main_Probe_Id_CoreId; /* ALT_NOC_MPU_DDR_T_PRB_COREID */
4810  volatile uint32_t ddr_T_main_Probe_Id_RevisionId; /* ALT_NOC_MPU_DDR_T_PRB_REVID */
4811  volatile uint32_t ddr_T_main_Probe_MainCtl; /* ALT_NOC_MPU_DDR_T_PRB_MAINCTL */
4812  volatile uint32_t ddr_T_main_Probe_CfgCtl; /* ALT_NOC_MPU_DDR_T_PRB_CFGCTL */
4813  uint32_t _pad_0x10_0x13; /* *UNDEFINED* */
4814  volatile uint32_t ddr_T_main_Probe_FilterLut; /* ALT_NOC_MPU_DDR_T_PRB_FLTLUT */
4815  volatile uint32_t ddr_T_main_Probe_TraceAlarmEn; /* ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN */
4816  volatile uint32_t ddr_T_main_Probe_TraceAlarmStatus; /* ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT */
4817  volatile uint32_t ddr_T_main_Probe_TraceAlarmClr; /* ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR */
4818  volatile uint32_t ddr_T_main_Probe_StatPeriod; /* ALT_NOC_MPU_DDR_T_PRB_STATPERIOD */
4819  volatile uint32_t ddr_T_main_Probe_StatGo; /* ALT_NOC_MPU_DDR_T_PRB_STATGO */
4820  volatile uint32_t ddr_T_main_Probe_StatAlarmMin; /* ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN */
4821  volatile uint32_t ddr_T_main_Probe_StatAlarmMax; /* ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX */
4822  volatile uint32_t ddr_T_main_Probe_StatAlarmStatus; /* ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT */
4823  volatile uint32_t ddr_T_main_Probe_StatAlarmClr; /* ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR */
4824  volatile uint32_t ddr_T_main_Probe_StatAlarmEn; /* ALT_NOC_MPU_DDR_T_PRB_STATALARMEN */
4825  uint32_t _pad_0x40_0x43; /* *UNDEFINED* */
4826  volatile uint32_t ddr_T_main_Probe_Filters_0_RouteIdBase; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE */
4827  volatile uint32_t ddr_T_main_Probe_Filters_0_RouteIdMask; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK */
4828  volatile uint32_t ddr_T_main_Probe_Filters_0_AddrBase_Low; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW */
4829  uint32_t _pad_0x50_0x53; /* *UNDEFINED* */
4830  volatile uint32_t ddr_T_main_Probe_Filters_0_WindowSize; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE */
4831  volatile uint32_t ddr_T_main_Probe_Filters_0_SecurityBase; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE */
4832  volatile uint32_t ddr_T_main_Probe_Filters_0_SecurityMask; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK */
4833  volatile uint32_t ddr_T_main_Probe_Filters_0_Opcode; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE */
4834  volatile uint32_t ddr_T_main_Probe_Filters_0_Status; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT */
4835  volatile uint32_t ddr_T_main_Probe_Filters_0_Length; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN */
4836  volatile uint32_t ddr_T_main_Probe_Filters_0_Urgency; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY */
4837  uint32_t _pad_0x70_0x7f[4]; /* *UNDEFINED* */
4838  volatile uint32_t ddr_T_main_Probe_Filters_1_RouteIdBase; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE */
4839  volatile uint32_t ddr_T_main_Probe_Filters_1_RouteIdMask; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK */
4840  volatile uint32_t ddr_T_main_Probe_Filters_1_AddrBase_Low; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW */
4841  uint32_t _pad_0x8c_0x8f; /* *UNDEFINED* */
4842  volatile uint32_t ddr_T_main_Probe_Filters_1_WindowSize; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE */
4843  volatile uint32_t ddr_T_main_Probe_Filters_1_SecurityBase; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE */
4844  volatile uint32_t ddr_T_main_Probe_Filters_1_SecurityMask; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK */
4845  volatile uint32_t ddr_T_main_Probe_Filters_1_Opcode; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE */
4846  volatile uint32_t ddr_T_main_Probe_Filters_1_Status; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT */
4847  volatile uint32_t ddr_T_main_Probe_Filters_1_Length; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN */
4848  volatile uint32_t ddr_T_main_Probe_Filters_1_Urgency; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY */
4849  uint32_t _pad_0xac_0xbb[4]; /* *UNDEFINED* */
4850  volatile uint32_t ddr_T_main_Probe_Filters_2_RouteIdBase; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE */
4851  volatile uint32_t ddr_T_main_Probe_Filters_2_RouteIdMask; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK */
4852  volatile uint32_t ddr_T_main_Probe_Filters_2_AddrBase_Low; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW */
4853  uint32_t _pad_0xc8_0xcb; /* *UNDEFINED* */
4854  volatile uint32_t ddr_T_main_Probe_Filters_2_WindowSize; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE */
4855  volatile uint32_t ddr_T_main_Probe_Filters_2_SecurityBase; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE */
4856  volatile uint32_t ddr_T_main_Probe_Filters_2_SecurityMask; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK */
4857  volatile uint32_t ddr_T_main_Probe_Filters_2_Opcode; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE */
4858  volatile uint32_t ddr_T_main_Probe_Filters_2_Status; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT */
4859  volatile uint32_t ddr_T_main_Probe_Filters_2_Length; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN */
4860  volatile uint32_t ddr_T_main_Probe_Filters_2_Urgency; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY */
4861  uint32_t _pad_0xe8_0xf7[4]; /* *UNDEFINED* */
4862  volatile uint32_t ddr_T_main_Probe_Filters_3_RouteIdBase; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE */
4863  volatile uint32_t ddr_T_main_Probe_Filters_3_RouteIdMask; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK */
4864  volatile uint32_t ddr_T_main_Probe_Filters_3_AddrBase_Low; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW */
4865  uint32_t _pad_0x104_0x107; /* *UNDEFINED* */
4866  volatile uint32_t ddr_T_main_Probe_Filters_3_WindowSize; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE */
4867  volatile uint32_t ddr_T_main_Probe_Filters_3_SecurityBase; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE */
4868  volatile uint32_t ddr_T_main_Probe_Filters_3_SecurityMask; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK */
4869  volatile uint32_t ddr_T_main_Probe_Filters_3_Opcode; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE */
4870  volatile uint32_t ddr_T_main_Probe_Filters_3_Status; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT */
4871  volatile uint32_t ddr_T_main_Probe_Filters_3_Length; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN */
4872  volatile uint32_t ddr_T_main_Probe_Filters_3_Urgency; /* ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY */
4873  uint32_t _pad_0x124_0x137[5]; /* *UNDEFINED* */
4874  volatile uint32_t ddr_T_main_Probe_Counters_0_Src; /* ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC */
4875  volatile uint32_t ddr_T_main_Probe_Counters_0_AlarmMode; /* ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD */
4876  volatile uint32_t ddr_T_main_Probe_Counters_0_Val; /* ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL */
4877  uint32_t _pad_0x144_0x14b[2]; /* *UNDEFINED* */
4878  volatile uint32_t ddr_T_main_Probe_Counters_1_Src; /* ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC */
4879  volatile uint32_t ddr_T_main_Probe_Counters_1_AlarmMode; /* ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD */
4880  volatile uint32_t ddr_T_main_Probe_Counters_1_Val; /* ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL */
4881  uint32_t _pad_0x158_0x400[170]; /* *UNDEFINED* */
4882 };
4883 
4884 /* The typedef declaration for the raw register contents of register group ALT_NOC_MPU_DDR_T_PRB. */
4885 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_raw_s ALT_NOC_MPU_DDR_T_PRB_raw_t;
4886 #endif /* __ASSEMBLY__ */
4887 
4888 
4889 /*
4890  * Component : ALT_NOC_MPU_DDR_T_SCHED
4891  *
4892  */
4893 /*
4894  * Register : ddr_T_main_Scheduler_Id_CoreId
4895  *
4896  * Register Layout
4897  *
4898  * Bits | Access | Reset | Description
4899  * :-------|:-------|:---------|:----------------------------------------
4900  * [7:0] | R | 0x2 | ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID
4901  * [31:8] | R | 0x7242e2 | ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM
4902  *
4903  */
4904 /*
4905  * Field : CORETYPEID
4906  *
4907  * Field identifying the type of IP.
4908  *
4909  * Field Access Macros:
4910  *
4911  */
4912 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID register field. */
4913 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_LSB 0
4914 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID register field. */
4915 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_MSB 7
4916 /* The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID register field. */
4917 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_WIDTH 8
4918 /* The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID register field value. */
4919 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_SET_MSK 0x000000ff
4920 /* The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID register field value. */
4921 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_CLR_MSK 0xffffff00
4922 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID register field. */
4923 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_RESET 0x2
4924 /* Extracts the ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID field value from a register. */
4925 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_GET(value) (((value) & 0x000000ff) >> 0)
4926 /* Produces a ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID register field value suitable for setting the register. */
4927 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_SET(value) (((value) << 0) & 0x000000ff)
4928 
4929 /*
4930  * Field : CORECHECKSUM
4931  *
4932  * Field containing a checksum of the parameters of the IP.
4933  *
4934  * Field Access Macros:
4935  *
4936  */
4937 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM register field. */
4938 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_LSB 8
4939 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM register field. */
4940 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_MSB 31
4941 /* The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM register field. */
4942 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_WIDTH 24
4943 /* The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM register field value. */
4944 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_SET_MSK 0xffffff00
4945 /* The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM register field value. */
4946 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_CLR_MSK 0x000000ff
4947 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM register field. */
4948 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_RESET 0x7242e2
4949 /* Extracts the ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM field value from a register. */
4950 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
4951 /* Produces a ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM register field value suitable for setting the register. */
4952 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
4953 
4954 #ifndef __ASSEMBLY__
4955 /*
4956  * WARNING: The C register and register group struct declarations are provided for
4957  * convenience and illustrative purposes. They should, however, be used with
4958  * caution as the C language standard provides no guarantees about the alignment or
4959  * atomicity of device memory accesses. The recommended practice for writing
4960  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4961  * alt_write_word() functions.
4962  *
4963  * The struct declaration for register ALT_NOC_MPU_DDR_T_SCHED_COREID.
4964  */
4965 struct ALT_NOC_MPU_DDR_T_SCHED_COREID_s
4966 {
4967  const uint32_t CORETYPEID : 8; /* ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID */
4968  const uint32_t CORECHECKSUM : 24; /* ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM */
4969 };
4970 
4971 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_SCHED_COREID. */
4972 typedef volatile struct ALT_NOC_MPU_DDR_T_SCHED_COREID_s ALT_NOC_MPU_DDR_T_SCHED_COREID_t;
4973 #endif /* __ASSEMBLY__ */
4974 
4975 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_COREID register. */
4976 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_RESET 0x7242e202
4977 /* The byte offset of the ALT_NOC_MPU_DDR_T_SCHED_COREID register from the beginning of the component. */
4978 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_OFST 0x0
4979 
4980 /*
4981  * Register : ddr_T_main_Scheduler_Id_RevisionId
4982  *
4983  * Register Layout
4984  *
4985  * Bits | Access | Reset | Description
4986  * :-------|:-------|:--------|:----------------------------------------
4987  * [7:0] | R | 0x0 | ALT_NOC_MPU_DDR_T_SCHED_REVID_UID
4988  * [31:8] | R | 0x129ff | ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID
4989  *
4990  */
4991 /*
4992  * Field : USERID
4993  *
4994  * Field containing a user defined value, not used anywhere inside the IP itself.
4995  *
4996  * Field Access Macros:
4997  *
4998  */
4999 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_REVID_UID register field. */
5000 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_LSB 0
5001 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_REVID_UID register field. */
5002 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_MSB 7
5003 /* The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_REVID_UID register field. */
5004 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_WIDTH 8
5005 /* The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_REVID_UID register field value. */
5006 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_SET_MSK 0x000000ff
5007 /* The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_REVID_UID register field value. */
5008 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_CLR_MSK 0xffffff00
5009 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_REVID_UID register field. */
5010 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_RESET 0x0
5011 /* Extracts the ALT_NOC_MPU_DDR_T_SCHED_REVID_UID field value from a register. */
5012 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_GET(value) (((value) & 0x000000ff) >> 0)
5013 /* Produces a ALT_NOC_MPU_DDR_T_SCHED_REVID_UID register field value suitable for setting the register. */
5014 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_SET(value) (((value) << 0) & 0x000000ff)
5015 
5016 /*
5017  * Field : FLEXNOCID
5018  *
5019  * Field containing the build revision of the software used to generate the IP HDL
5020  * code.
5021  *
5022  * Field Access Macros:
5023  *
5024  */
5025 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID register field. */
5026 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_LSB 8
5027 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID register field. */
5028 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_MSB 31
5029 /* The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID register field. */
5030 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_WIDTH 24
5031 /* The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID register field value. */
5032 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_SET_MSK 0xffffff00
5033 /* The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID register field value. */
5034 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_CLR_MSK 0x000000ff
5035 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID register field. */
5036 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_RESET 0x129ff
5037 /* Extracts the ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID field value from a register. */
5038 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
5039 /* Produces a ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID register field value suitable for setting the register. */
5040 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
5041 
5042 #ifndef __ASSEMBLY__
5043 /*
5044  * WARNING: The C register and register group struct declarations are provided for
5045  * convenience and illustrative purposes. They should, however, be used with
5046  * caution as the C language standard provides no guarantees about the alignment or
5047  * atomicity of device memory accesses. The recommended practice for writing
5048  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5049  * alt_write_word() functions.
5050  *
5051  * The struct declaration for register ALT_NOC_MPU_DDR_T_SCHED_REVID.
5052  */
5053 struct ALT_NOC_MPU_DDR_T_SCHED_REVID_s
5054 {
5055  const uint32_t USERID : 8; /* ALT_NOC_MPU_DDR_T_SCHED_REVID_UID */
5056  const uint32_t FLEXNOCID : 24; /* ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID */
5057 };
5058 
5059 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_SCHED_REVID. */
5060 typedef volatile struct ALT_NOC_MPU_DDR_T_SCHED_REVID_s ALT_NOC_MPU_DDR_T_SCHED_REVID_t;
5061 #endif /* __ASSEMBLY__ */
5062 
5063 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_REVID register. */
5064 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_RESET 0x0129ff00
5065 /* The byte offset of the ALT_NOC_MPU_DDR_T_SCHED_REVID register from the beginning of the component. */
5066 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_OFST 0x4
5067 
5068 /*
5069  * Register : ddr_T_main_Scheduler_DdrConf
5070  *
5071  * ddr configuration definition.
5072  *
5073  * Register Layout
5074  *
5075  * Bits | Access | Reset | Description
5076  * :-------|:-------|:--------|:----------------------------------------
5077  * [4:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5078  * [31:5] | ??? | Unknown | *UNDEFINED*
5079  *
5080  */
5081 /*
5082  * Field : DDRCONF
5083  *
5084  * Selector of predefined ddrConf configuration
5085  *
5086  * Field Enumeration Values:
5087  *
5088  * Enum | Value | Description
5089  * :-----------------------------------------------------|:------|:------------
5090  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R12_B3_C10 | 0x00 |
5091  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R13_B3_C10 | 0x01 |
5092  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R14_B3_C10 | 0x02 |
5093  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R15_B3_C10 | 0x03 |
5094  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R16_B3_C10 | 0x04 |
5095  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R17_B3_C10 | 0x05 |
5096  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R14_B3_C11 | 0x06 |
5097  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R15_B3_C11 | 0x07 |
5098  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R16_B3_C11 | 0x08 |
5099  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R15_B3_C12 | 0x09 |
5100  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R14_B4_C10 | 0x0A |
5101  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R15_B4_C10 | 0x0B |
5102  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R16_B4_C10 | 0x0C |
5103  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R17_B4_C10 | 0x0D |
5104  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R12_C10 | 0x0E |
5105  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R13_C10 | 0x0F |
5106  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R14_C10 | 0x10 |
5107  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R15_C10 | 0x11 |
5108  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R16_C10 | 0x12 |
5109  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R17_C10 | 0x13 |
5110  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R14_C11 | 0x14 |
5111  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R15_C11 | 0x15 |
5112  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R16_C11 | 0x16 |
5113  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R15_C12 | 0x17 |
5114  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B4_R14_C10 | 0x18 |
5115  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B4_R15_C10 | 0x19 |
5116  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B4_R16_C10 | 0x1A |
5117  * ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B4_R17_C10 | 0x1B |
5118  *
5119  * Field Access Macros:
5120  *
5121  */
5122 /*
5123  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5124  *
5125  * All types
5126  */
5127 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R12_B3_C10 0x00
5128 /*
5129  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5130  *
5131  * All types
5132  */
5133 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R13_B3_C10 0x01
5134 /*
5135  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5136  *
5137  * All types
5138  */
5139 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R14_B3_C10 0x02
5140 /*
5141  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5142  *
5143  * All types
5144  */
5145 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R15_B3_C10 0x03
5146 /*
5147  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5148  *
5149  * All types
5150  */
5151 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R16_B3_C10 0x04
5152 /*
5153  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5154  *
5155  * All types
5156  */
5157 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R17_B3_C10 0x05
5158 /*
5159  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5160  *
5161  * LPDDR x16
5162  */
5163 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R14_B3_C11 0x06
5164 /*
5165  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5166  *
5167  * LPDDR x16/x32
5168  */
5169 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R15_B3_C11 0x07
5170 /*
5171  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5172  *
5173  * DDR3 8Gb
5174  */
5175 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R16_B3_C11 0x08
5176 /*
5177  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5178  *
5179  * LPDDR3 16Gb x16 only
5180  */
5181 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R15_B3_C12 0x09
5182 /*
5183  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5184  *
5185  * DDR4 only
5186  */
5187 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R14_B4_C10 0x0A
5188 /*
5189  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5190  *
5191  * DDR4 only
5192  */
5193 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R15_B4_C10 0x0B
5194 /*
5195  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5196  *
5197  * DDR4 only
5198  */
5199 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R16_B4_C10 0x0C
5200 /*
5201  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5202  *
5203  * DDR4 only
5204  */
5205 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R17_B4_C10 0x0D
5206 /*
5207  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5208  *
5209  * Min DDR3 512Mbit x16
5210  */
5211 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R12_C10 0x0E
5212 /*
5213  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5214  *
5215  * DDR3 512Mb x8 or 1Gb x16
5216  */
5217 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R13_C10 0x0F
5218 /*
5219  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5220  *
5221  * Min DDR4 1Gb x8 or DDR3 1Gb x8 or 2Gb x16
5222  */
5223 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R14_C10 0x10
5224 /*
5225  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5226  *
5227  * DDR3 2Gb x8 & 4Gb x16 or LPDDR3 8Gb x32
5228  */
5229 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R15_C10 0x11
5230 /*
5231  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5232  *
5233  * DDR3 4Gb x8 & 8Gb x16
5234  */
5235 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R16_C10 0x12
5236 /*
5237  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5238  *
5239  * DDR4 16Gb x16
5240  */
5241 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R17_C10 0x13
5242 /*
5243  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5244  *
5245  * LPDDR3 4Gb x16
5246  */
5247 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R14_C11 0x14
5248 /*
5249  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5250  *
5251  * LPDDR3 8Gb x16 or 16Gb x32
5252  */
5253 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R15_C11 0x15
5254 /*
5255  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5256  *
5257  * DDR3 8Gb x8
5258  */
5259 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R16_C11 0x16
5260 /*
5261  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5262  *
5263  * LPDDR3 16Gb x16 only
5264  */
5265 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R15_C12 0x17
5266 /*
5267  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5268  *
5269  * DDR4 2Gb x8
5270  */
5271 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B4_R14_C10 0x18
5272 /*
5273  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5274  *
5275  * DDR4 4Gb x8
5276  */
5277 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B4_R15_C10 0x19
5278 /*
5279  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5280  *
5281  * DDR4 8Gb x8
5282  */
5283 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B4_R16_C10 0x1A
5284 /*
5285  * Enumerated value for register field ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF
5286  *
5287  * DDR4 16Gb x8
5288  */
5289 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B4_R17_C10 0x1B
5290 
5291 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF register field. */
5292 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_LSB 0
5293 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF register field. */
5294 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_MSB 4
5295 /* The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF register field. */
5296 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_WIDTH 5
5297 /* The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF register field value. */
5298 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_SET_MSK 0x0000001f
5299 /* The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF register field value. */
5300 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_CLR_MSK 0xffffffe0
5301 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF register field. */
5302 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_RESET 0x0
5303 /* Extracts the ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF field value from a register. */
5304 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_GET(value) (((value) & 0x0000001f) >> 0)
5305 /* Produces a ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF register field value suitable for setting the register. */
5306 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_SET(value) (((value) << 0) & 0x0000001f)
5307 
5308 #ifndef __ASSEMBLY__
5309 /*
5310  * WARNING: The C register and register group struct declarations are provided for
5311  * convenience and illustrative purposes. They should, however, be used with
5312  * caution as the C language standard provides no guarantees about the alignment or
5313  * atomicity of device memory accesses. The recommended practice for writing
5314  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5315  * alt_write_word() functions.
5316  *
5317  * The struct declaration for register ALT_NOC_MPU_DDR_T_SCHED_DDRCONF.
5318  */
5319 struct ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_s
5320 {
5321  uint32_t DDRCONF : 5; /* ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF */
5322  uint32_t : 27; /* *UNDEFINED* */
5323 };
5324 
5325 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_SCHED_DDRCONF. */
5326 typedef volatile struct ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_s ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_t;
5327 #endif /* __ASSEMBLY__ */
5328 
5329 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DDRCONF register. */
5330 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_RESET 0x00000000
5331 /* The byte offset of the ALT_NOC_MPU_DDR_T_SCHED_DDRCONF register from the beginning of the component. */
5332 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_OFST 0x8
5333 
5334 /*
5335  * Register : ddr_T_main_Scheduler_DdrTiming
5336  *
5337  * ddr timing definition.
5338  *
5339  * Register Layout
5340  *
5341  * Bits | Access | Reset | Description
5342  * :--------|:-------|:------|:-------------------------------------------
5343  * [5:0] | RW | 0x1c | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT
5344  * [11:6] | RW | 0x13 | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS
5345  * [17:12] | RW | 0x21 | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS
5346  * [20:18] | RW | 0x2 | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN
5347  * [25:21] | RW | 0x1 | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR
5348  * [30:26] | RW | 0xb | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD
5349  * [31] | RW | 0x1 | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO
5350  *
5351  */
5352 /*
5353  * Field : ACTTOACT
5354  *
5355  * Minimum number of scheduler clock cycles between two consecutive DRAM Activate
5356  * commands on the same bank.
5357  *
5358  * Field Access Macros:
5359  *
5360  */
5361 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT register field. */
5362 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB 0
5363 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT register field. */
5364 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_MSB 5
5365 /* The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT register field. */
5366 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_WIDTH 6
5367 /* The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT register field value. */
5368 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_SET_MSK 0x0000003f
5369 /* The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT register field value. */
5370 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_CLR_MSK 0xffffffc0
5371 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT register field. */
5372 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_RESET 0x1c
5373 /* Extracts the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT field value from a register. */
5374 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_GET(value) (((value) & 0x0000003f) >> 0)
5375 /* Produces a ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT register field value suitable for setting the register. */
5376 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_SET(value) (((value) << 0) & 0x0000003f)
5377 
5378 /*
5379  * Field : RDTOMISS
5380  *
5381  * Minimum number of scheduler clock cycles between the last DRAM Read command and
5382  * a new Read or Write command in another page of the same bank.
5383  *
5384  * Field Access Macros:
5385  *
5386  */
5387 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS register field. */
5388 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB 6
5389 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS register field. */
5390 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_MSB 11
5391 /* The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS register field. */
5392 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_WIDTH 6
5393 /* The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS register field value. */
5394 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_SET_MSK 0x00000fc0
5395 /* The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS register field value. */
5396 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_CLR_MSK 0xfffff03f
5397 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS register field. */
5398 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_RESET 0x13
5399 /* Extracts the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS field value from a register. */
5400 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_GET(value) (((value) & 0x00000fc0) >> 6)
5401 /* Produces a ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS register field value suitable for setting the register. */
5402 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_SET(value) (((value) << 6) & 0x00000fc0)
5403 
5404 /*
5405  * Field : WRTOMISS
5406  *
5407  * Minimum number of scheduler clock cycles between the last DRAM Write command and
5408  * a new Read or Write command in another page of the same bank.
5409  *
5410  * Field Access Macros:
5411  *
5412  */
5413 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS register field. */
5414 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB 12
5415 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS register field. */
5416 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_MSB 17
5417 /* The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS register field. */
5418 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_WIDTH 6
5419 /* The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS register field value. */
5420 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_SET_MSK 0x0003f000
5421 /* The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS register field value. */
5422 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_CLR_MSK 0xfffc0fff
5423 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS register field. */
5424 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_RESET 0x21
5425 /* Extracts the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS field value from a register. */
5426 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_GET(value) (((value) & 0x0003f000) >> 12)
5427 /* Produces a ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS register field value suitable for setting the register. */
5428 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_SET(value) (((value) << 12) & 0x0003f000)
5429 
5430 /*
5431  * Field : BURSTLEN
5432  *
5433  * DRAM burst duration on the DRAM data bus in scheduler clock cycles. Also equal
5434  * to scheduler clock cycles between two DRAM commands.
5435  *
5436  * Field Access Macros:
5437  *
5438  */
5439 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN register field. */
5440 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB 18
5441 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN register field. */
5442 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_MSB 20
5443 /* The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN register field. */
5444 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_WIDTH 3
5445 /* The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN register field value. */
5446 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_SET_MSK 0x001c0000
5447 /* The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN register field value. */
5448 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_CLR_MSK 0xffe3ffff
5449 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN register field. */
5450 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_RESET 0x2
5451 /* Extracts the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN field value from a register. */
5452 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_GET(value) (((value) & 0x001c0000) >> 18)
5453 /* Produces a ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN register field value suitable for setting the register. */
5454 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_SET(value) (((value) << 18) & 0x001c0000)
5455 
5456 /*
5457  * Field : RDTOWR
5458  *
5459  * Minimum number of scheduler clock cycles between the last DRAM Read command and
5460  * a Write command.
5461  *
5462  * Field Access Macros:
5463  *
5464  */
5465 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR register field. */
5466 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB 21
5467 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR register field. */
5468 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_MSB 25
5469 /* The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR register field. */
5470 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_WIDTH 5
5471 /* The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR register field value. */
5472 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_SET_MSK 0x03e00000
5473 /* The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR register field value. */
5474 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_CLR_MSK 0xfc1fffff
5475 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR register field. */
5476 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_RESET 0x1
5477 /* Extracts the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR field value from a register. */
5478 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_GET(value) (((value) & 0x03e00000) >> 21)
5479 /* Produces a ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR register field value suitable for setting the register. */
5480 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_SET(value) (((value) << 21) & 0x03e00000)
5481 
5482 /*
5483  * Field : WRTORD
5484  *
5485  * Minimum number of scheduler clock cycles between the last DRAM Write command and
5486  * a Read command.
5487  *
5488  * Field Access Macros:
5489  *
5490  */
5491 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD register field. */
5492 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB 26
5493 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD register field. */
5494 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_MSB 30
5495 /* The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD register field. */
5496 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_WIDTH 5
5497 /* The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD register field value. */
5498 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_SET_MSK 0x7c000000
5499 /* The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD register field value. */
5500 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_CLR_MSK 0x83ffffff
5501 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD register field. */
5502 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_RESET 0xb
5503 /* Extracts the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD field value from a register. */
5504 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_GET(value) (((value) & 0x7c000000) >> 26)
5505 /* Produces a ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD register field value suitable for setting the register. */
5506 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_SET(value) (((value) << 26) & 0x7c000000)
5507 
5508 /*
5509  * Field : BWRATIO
5510  *
5511  * Number of cycle minus 1 the DDR chip needs to process one Generic socket word.
5512  *
5513  * Field Access Macros:
5514  *
5515  */
5516 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO register field. */
5517 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB 31
5518 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO register field. */
5519 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_MSB 31
5520 /* The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO register field. */
5521 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_WIDTH 1
5522 /* The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO register field value. */
5523 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_SET_MSK 0x80000000
5524 /* The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO register field value. */
5525 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_CLR_MSK 0x7fffffff
5526 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO register field. */
5527 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_RESET 0x1
5528 /* Extracts the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO field value from a register. */
5529 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_GET(value) (((value) & 0x80000000) >> 31)
5530 /* Produces a ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO register field value suitable for setting the register. */
5531 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_SET(value) (((value) << 31) & 0x80000000)
5532 
5533 #ifndef __ASSEMBLY__
5534 /*
5535  * WARNING: The C register and register group struct declarations are provided for
5536  * convenience and illustrative purposes. They should, however, be used with
5537  * caution as the C language standard provides no guarantees about the alignment or
5538  * atomicity of device memory accesses. The recommended practice for writing
5539  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5540  * alt_write_word() functions.
5541  *
5542  * The struct declaration for register ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING.
5543  */
5544 struct ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_s
5545 {
5546  uint32_t ACTTOACT : 6; /* ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT */
5547  uint32_t RDTOMISS : 6; /* ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS */
5548  uint32_t WRTOMISS : 6; /* ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS */
5549  uint32_t BURSTLEN : 3; /* ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN */
5550  uint32_t RDTOWR : 5; /* ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR */
5551  uint32_t WRTORD : 5; /* ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD */
5552  uint32_t BWRATIO : 1; /* ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO */
5553 };
5554 
5555 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING. */
5556 typedef volatile struct ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_s ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_t;
5557 #endif /* __ASSEMBLY__ */
5558 
5559 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING register. */
5560 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RESET 0xac2a14dc
5561 /* The byte offset of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING register from the beginning of the component. */
5562 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_OFST 0xc
5563 
5564 /*
5565  * Register : ddr_T_main_Scheduler_DdrMode
5566  *
5567  * ddr mode definition.
5568  *
5569  * Register Layout
5570  *
5571  * Bits | Access | Reset | Description
5572  * :-------|:-------|:--------|:-----------------------------------------------
5573  * [0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE
5574  * [1] | RW | 0x0 | ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED
5575  * [31:2] | ??? | Unknown | *UNDEFINED*
5576  *
5577  */
5578 /*
5579  * Field : AUTOPRECHARGE
5580  *
5581  * When set to one, pages are automatically closed after each access, when set to
5582  * zero, pages are left opened until an access in a different page occurs
5583  *
5584  * Field Access Macros:
5585  *
5586  */
5587 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE register field. */
5588 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_LSB 0
5589 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE register field. */
5590 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_MSB 0
5591 /* The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE register field. */
5592 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_WIDTH 1
5593 /* The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE register field value. */
5594 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_SET_MSK 0x00000001
5595 /* The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE register field value. */
5596 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_CLR_MSK 0xfffffffe
5597 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE register field. */
5598 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_RESET 0x0
5599 /* Extracts the ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE field value from a register. */
5600 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_GET(value) (((value) & 0x00000001) >> 0)
5601 /* Produces a ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE register field value suitable for setting the register. */
5602 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_SET(value) (((value) << 0) & 0x00000001)
5603 
5604 /*
5605  * Field : BWRATIOEXTENDED
5606  *
5607  * When set to 1, support for 4x Bwratio.
5608  *
5609  * Field Access Macros:
5610  *
5611  */
5612 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED register field. */
5613 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB 1
5614 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED register field. */
5615 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_MSB 1
5616 /* The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED register field. */
5617 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_WIDTH 1
5618 /* The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED register field value. */
5619 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_SET_MSK 0x00000002
5620 /* The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED register field value. */
5621 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_CLR_MSK 0xfffffffd
5622 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED register field. */
5623 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_RESET 0x0
5624 /* Extracts the ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED field value from a register. */
5625 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_GET(value) (((value) & 0x00000002) >> 1)
5626 /* Produces a ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED register field value suitable for setting the register. */
5627 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_SET(value) (((value) << 1) & 0x00000002)
5628 
5629 #ifndef __ASSEMBLY__
5630 /*
5631  * WARNING: The C register and register group struct declarations are provided for
5632  * convenience and illustrative purposes. They should, however, be used with
5633  * caution as the C language standard provides no guarantees about the alignment or
5634  * atomicity of device memory accesses. The recommended practice for writing
5635  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5636  * alt_write_word() functions.
5637  *
5638  * The struct declaration for register ALT_NOC_MPU_DDR_T_SCHED_DDRMOD.
5639  */
5640 struct ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_s
5641 {
5642  uint32_t AUTOPRECHARGE : 1; /* ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE */
5643  uint32_t BWRATIOEXTENDED : 1; /* ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED */
5644  uint32_t : 30; /* *UNDEFINED* */
5645 };
5646 
5647 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_SCHED_DDRMOD. */
5648 typedef volatile struct ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_s ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_t;
5649 #endif /* __ASSEMBLY__ */
5650 
5651 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DDRMOD register. */
5652 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_RESET 0x00000000
5653 /* The byte offset of the ALT_NOC_MPU_DDR_T_SCHED_DDRMOD register from the beginning of the component. */
5654 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_OFST 0x10
5655 
5656 /*
5657  * Register : ddr_T_main_Scheduler_ReadLatency
5658  *
5659  *
5660  * Register Layout
5661  *
5662  * Bits | Access | Reset | Description
5663  * :-------|:-------|:--------|:--------------------------------------------
5664  * [7:0] | RW | 0x13 | ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY
5665  * [31:8] | ??? | Unknown | *UNDEFINED*
5666  *
5667  */
5668 /*
5669  * Field : READLATENCY
5670  *
5671  * Maximun delay between a read request and the first data response.
5672  *
5673  * Field Access Macros:
5674  *
5675  */
5676 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY register field. */
5677 #define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_LSB 0
5678 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY register field. */
5679 #define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_MSB 7
5680 /* The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY register field. */
5681 #define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_WIDTH 8
5682 /* The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY register field value. */
5683 #define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_SET_MSK 0x000000ff
5684 /* The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY register field value. */
5685 #define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_CLR_MSK 0xffffff00
5686 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY register field. */
5687 #define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_RESET 0x13
5688 /* Extracts the ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY field value from a register. */
5689 #define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_GET(value) (((value) & 0x000000ff) >> 0)
5690 /* Produces a ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY register field value suitable for setting the register. */
5691 #define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_SET(value) (((value) << 0) & 0x000000ff)
5692 
5693 #ifndef __ASSEMBLY__
5694 /*
5695  * WARNING: The C register and register group struct declarations are provided for
5696  * convenience and illustrative purposes. They should, however, be used with
5697  * caution as the C language standard provides no guarantees about the alignment or
5698  * atomicity of device memory accesses. The recommended practice for writing
5699  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5700  * alt_write_word() functions.
5701  *
5702  * The struct declaration for register ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY.
5703  */
5704 struct ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_s
5705 {
5706  uint32_t READLATENCY : 8; /* ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY */
5707  uint32_t : 24; /* *UNDEFINED* */
5708 };
5709 
5710 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY. */
5711 typedef volatile struct ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_s ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_t;
5712 #endif /* __ASSEMBLY__ */
5713 
5714 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY register. */
5715 #define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RESET 0x00000013
5716 /* The byte offset of the ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY register from the beginning of the component. */
5717 #define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_OFST 0x14
5718 
5719 /*
5720  * Register : ddr_T_main_Scheduler_Activate
5721  *
5722  * timing values concerning Activate commands, in Generic clock unit.
5723  *
5724  * Register Layout
5725  *
5726  * Bits | Access | Reset | Description
5727  * :--------|:-------|:--------|:-----------------------------------------
5728  * [3:0] | RW | 0x2 | ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD
5729  * [9:4] | RW | 0xd | ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW
5730  * [10] | RW | 0x1 | ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK
5731  * [31:11] | ??? | Unknown | *UNDEFINED*
5732  *
5733  */
5734 /*
5735  * Field : RRD
5736  *
5737  * Number of cycle between two consecutive Activate commands on different Banks of
5738  * the same device.
5739  *
5740  * Field Access Macros:
5741  *
5742  */
5743 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD register field. */
5744 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB 0
5745 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD register field. */
5746 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_MSB 3
5747 /* The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD register field. */
5748 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_WIDTH 4
5749 /* The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD register field value. */
5750 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_SET_MSK 0x0000000f
5751 /* The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD register field value. */
5752 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_CLR_MSK 0xfffffff0
5753 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD register field. */
5754 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_RESET 0x2
5755 /* Extracts the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD field value from a register. */
5756 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_GET(value) (((value) & 0x0000000f) >> 0)
5757 /* Produces a ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD register field value suitable for setting the register. */
5758 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_SET(value) (((value) << 0) & 0x0000000f)
5759 
5760 /*
5761  * Field : FAW
5762  *
5763  * Number of cycle of the FAW period.
5764  *
5765  * Field Access Macros:
5766  *
5767  */
5768 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW register field. */
5769 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB 4
5770 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW register field. */
5771 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_MSB 9
5772 /* The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW register field. */
5773 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_WIDTH 6
5774 /* The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW register field value. */
5775 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_SET_MSK 0x000003f0
5776 /* The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW register field value. */
5777 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_CLR_MSK 0xfffffc0f
5778 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW register field. */
5779 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_RESET 0xd
5780 /* Extracts the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW field value from a register. */
5781 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_GET(value) (((value) & 0x000003f0) >> 4)
5782 /* Produces a ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW register field value suitable for setting the register. */
5783 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_SET(value) (((value) << 4) & 0x000003f0)
5784 
5785 /*
5786  * Field : FAWBANK
5787  *
5788  * Number of Bank of a given device involved in the FAW period.
5789  *
5790  * Field Access Macros:
5791  *
5792  */
5793 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK register field. */
5794 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB 10
5795 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK register field. */
5796 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_MSB 10
5797 /* The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK register field. */
5798 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_WIDTH 1
5799 /* The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK register field value. */
5800 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_SET_MSK 0x00000400
5801 /* The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK register field value. */
5802 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_CLR_MSK 0xfffffbff
5803 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK register field. */
5804 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_RESET 0x1
5805 /* Extracts the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK field value from a register. */
5806 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_GET(value) (((value) & 0x00000400) >> 10)
5807 /* Produces a ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK register field value suitable for setting the register. */
5808 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_SET(value) (((value) << 10) & 0x00000400)
5809 
5810 #ifndef __ASSEMBLY__
5811 /*
5812  * WARNING: The C register and register group struct declarations are provided for
5813  * convenience and illustrative purposes. They should, however, be used with
5814  * caution as the C language standard provides no guarantees about the alignment or
5815  * atomicity of device memory accesses. The recommended practice for writing
5816  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5817  * alt_write_word() functions.
5818  *
5819  * The struct declaration for register ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE.
5820  */
5821 struct ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_s
5822 {
5823  uint32_t RRD : 4; /* ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD */
5824  uint32_t FAW : 6; /* ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW */
5825  uint32_t FAWBANK : 1; /* ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK */
5826  uint32_t : 21; /* *UNDEFINED* */
5827 };
5828 
5829 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE. */
5830 typedef volatile struct ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_s ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_t;
5831 #endif /* __ASSEMBLY__ */
5832 
5833 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE register. */
5834 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RESET 0x000004d2
5835 /* The byte offset of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE register from the beginning of the component. */
5836 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_OFST 0x38
5837 
5838 /*
5839  * Register : ddr_T_main_Scheduler_DevToDev
5840  *
5841  * timing values concerning device to device data bus ownership change, in Generic
5842  * clock unit.
5843  *
5844  * Register Layout
5845  *
5846  * Bits | Access | Reset | Description
5847  * :-------|:-------|:--------|:-------------------------------------------
5848  * [1:0] | RW | 0x1 | ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD
5849  * [3:2] | RW | 0x1 | ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR
5850  * [5:4] | RW | 0x1 | ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD
5851  * [31:6] | ??? | Unknown | *UNDEFINED*
5852  *
5853  */
5854 /*
5855  * Field : BUSRDTORD
5856  *
5857  * number of cycle between the last read data of a device and the first read data
5858  * of another device.
5859  *
5860  * Field Access Macros:
5861  *
5862  */
5863 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD register field. */
5864 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB 0
5865 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD register field. */
5866 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_MSB 1
5867 /* The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD register field. */
5868 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_WIDTH 2
5869 /* The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD register field value. */
5870 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_SET_MSK 0x00000003
5871 /* The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD register field value. */
5872 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_CLR_MSK 0xfffffffc
5873 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD register field. */
5874 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_RESET 0x1
5875 /* Extracts the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD field value from a register. */
5876 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_GET(value) (((value) & 0x00000003) >> 0)
5877 /* Produces a ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD register field value suitable for setting the register. */
5878 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_SET(value) (((value) << 0) & 0x00000003)
5879 
5880 /*
5881  * Field : BUSRDTOWR
5882  *
5883  * number of cycle between the last read data of a device and the first write data
5884  * to another device.
5885  *
5886  * Field Access Macros:
5887  *
5888  */
5889 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR register field. */
5890 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB 2
5891 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR register field. */
5892 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_MSB 3
5893 /* The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR register field. */
5894 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_WIDTH 2
5895 /* The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR register field value. */
5896 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_SET_MSK 0x0000000c
5897 /* The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR register field value. */
5898 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_CLR_MSK 0xfffffff3
5899 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR register field. */
5900 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_RESET 0x1
5901 /* Extracts the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR field value from a register. */
5902 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_GET(value) (((value) & 0x0000000c) >> 2)
5903 /* Produces a ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR register field value suitable for setting the register. */
5904 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_SET(value) (((value) << 2) & 0x0000000c)
5905 
5906 /*
5907  * Field : BUSWRTORD
5908  *
5909  * number of cycle between the last write data to a device and the first read data
5910  * of another device.
5911  *
5912  * Field Access Macros:
5913  *
5914  */
5915 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD register field. */
5916 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB 4
5917 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD register field. */
5918 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_MSB 5
5919 /* The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD register field. */
5920 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_WIDTH 2
5921 /* The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD register field value. */
5922 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_SET_MSK 0x00000030
5923 /* The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD register field value. */
5924 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_CLR_MSK 0xffffffcf
5925 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD register field. */
5926 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_RESET 0x1
5927 /* Extracts the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD field value from a register. */
5928 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_GET(value) (((value) & 0x00000030) >> 4)
5929 /* Produces a ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD register field value suitable for setting the register. */
5930 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_SET(value) (((value) << 4) & 0x00000030)
5931 
5932 #ifndef __ASSEMBLY__
5933 /*
5934  * WARNING: The C register and register group struct declarations are provided for
5935  * convenience and illustrative purposes. They should, however, be used with
5936  * caution as the C language standard provides no guarantees about the alignment or
5937  * atomicity of device memory accesses. The recommended practice for writing
5938  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5939  * alt_write_word() functions.
5940  *
5941  * The struct declaration for register ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV.
5942  */
5943 struct ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_s
5944 {
5945  uint32_t BUSRDTORD : 2; /* ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD */
5946  uint32_t BUSRDTOWR : 2; /* ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR */
5947  uint32_t BUSWRTORD : 2; /* ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD */
5948  uint32_t : 26; /* *UNDEFINED* */
5949 };
5950 
5951 /* The typedef declaration for register ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV. */
5952 typedef volatile struct ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_s ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_t;
5953 #endif /* __ASSEMBLY__ */
5954 
5955 /* The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV register. */
5956 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_RESET 0x00000015
5957 /* The byte offset of the ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV register from the beginning of the component. */
5958 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_OFST 0x3c
5959 
5960 #ifndef __ASSEMBLY__
5961 /*
5962  * WARNING: The C register and register group struct declarations are provided for
5963  * convenience and illustrative purposes. They should, however, be used with
5964  * caution as the C language standard provides no guarantees about the alignment or
5965  * atomicity of device memory accesses. The recommended practice for writing
5966  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5967  * alt_write_word() functions.
5968  *
5969  * The struct declaration for register group ALT_NOC_MPU_DDR_T_SCHED.
5970  */
5971 struct ALT_NOC_MPU_DDR_T_SCHED_s
5972 {
5973  ALT_NOC_MPU_DDR_T_SCHED_COREID_t ddr_T_main_Scheduler_Id_CoreId; /* ALT_NOC_MPU_DDR_T_SCHED_COREID */
5974  ALT_NOC_MPU_DDR_T_SCHED_REVID_t ddr_T_main_Scheduler_Id_RevisionId; /* ALT_NOC_MPU_DDR_T_SCHED_REVID */
5975  ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_t ddr_T_main_Scheduler_DdrConf; /* ALT_NOC_MPU_DDR_T_SCHED_DDRCONF */
5976  ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_t ddr_T_main_Scheduler_DdrTiming; /* ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING */
5977  ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_t ddr_T_main_Scheduler_DdrMode; /* ALT_NOC_MPU_DDR_T_SCHED_DDRMOD */
5978  ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_t ddr_T_main_Scheduler_ReadLatency; /* ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY */
5979  volatile uint32_t _pad_0x18_0x37[8]; /* *UNDEFINED* */
5980  ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_t ddr_T_main_Scheduler_Activate; /* ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE */
5981  ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_t ddr_T_main_Scheduler_DevToDev; /* ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV */
5982  volatile uint32_t _pad_0x40_0x80[16]; /* *UNDEFINED* */
5983 };
5984 
5985 /* The typedef declaration for register group ALT_NOC_MPU_DDR_T_SCHED. */
5986 typedef volatile struct ALT_NOC_MPU_DDR_T_SCHED_s ALT_NOC_MPU_DDR_T_SCHED_t;
5987 /* The struct declaration for the raw register contents of register group ALT_NOC_MPU_DDR_T_SCHED. */
5988 struct ALT_NOC_MPU_DDR_T_SCHED_raw_s
5989 {
5990  volatile uint32_t ddr_T_main_Scheduler_Id_CoreId; /* ALT_NOC_MPU_DDR_T_SCHED_COREID */
5991  volatile uint32_t ddr_T_main_Scheduler_Id_RevisionId; /* ALT_NOC_MPU_DDR_T_SCHED_REVID */
5992  volatile uint32_t ddr_T_main_Scheduler_DdrConf; /* ALT_NOC_MPU_DDR_T_SCHED_DDRCONF */
5993  volatile uint32_t ddr_T_main_Scheduler_DdrTiming; /* ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING */
5994  volatile uint32_t ddr_T_main_Scheduler_DdrMode; /* ALT_NOC_MPU_DDR_T_SCHED_DDRMOD */
5995  volatile uint32_t ddr_T_main_Scheduler_ReadLatency; /* ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY */
5996  uint32_t _pad_0x18_0x37[8]; /* *UNDEFINED* */
5997  volatile uint32_t ddr_T_main_Scheduler_Activate; /* ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE */
5998  volatile uint32_t ddr_T_main_Scheduler_DevToDev; /* ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV */
5999  uint32_t _pad_0x40_0x80[16]; /* *UNDEFINED* */
6000 };
6001 
6002 /* The typedef declaration for the raw register contents of register group ALT_NOC_MPU_DDR_T_SCHED. */
6003 typedef volatile struct ALT_NOC_MPU_DDR_T_SCHED_raw_s ALT_NOC_MPU_DDR_T_SCHED_raw_t;
6004 #endif /* __ASSEMBLY__ */
6005 
6006 
6007 #ifdef __cplusplus
6008 }
6009 #endif /* __cplusplus */
6010 #endif /* __ALT_SOCAL_NOC_MPU_DDR_H__ */
6011