Hardware Libraries  20.1
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alt_nand.h
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32 
33 /* Altera - ALT_NAND_CFG */
34 
35 #ifndef __ALT_SOCAL_NAND_H__
36 #define __ALT_SOCAL_NAND_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_NAND_CFG
50  *
51  */
52 /*
53  * Register : device_reset
54  *
55  * Device reset. Controller sends a RESET command to device.
56  *
57  * Controller resets bit after sending command to device
58  *
59  * Register Layout
60  *
61  * Bits | Access | Reset | Description
62  * :-------|:-------|:--------|:------------------------------
63  * [0] | RW | 0x0 | ALT_NAND_CFG_DEVICE_RST_BANK0
64  * [1] | RW | 0x0 | ALT_NAND_CFG_DEVICE_RST_BANK1
65  * [2] | RW | 0x0 | ALT_NAND_CFG_DEVICE_RST_BANK2
66  * [3] | RW | 0x0 | ALT_NAND_CFG_DEVICE_RST_BANK3
67  * [31:4] | ??? | Unknown | *UNDEFINED*
68  *
69  */
70 /*
71  * Field : bank0
72  *
73  * Issues reset to bank 0. Controller resets the bit after
74  *
75  * reset command is issued to device.
76  *
77  * Field Access Macros:
78  *
79  */
80 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK0 register field. */
81 #define ALT_NAND_CFG_DEVICE_RST_BANK0_LSB 0
82 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK0 register field. */
83 #define ALT_NAND_CFG_DEVICE_RST_BANK0_MSB 0
84 /* The width in bits of the ALT_NAND_CFG_DEVICE_RST_BANK0 register field. */
85 #define ALT_NAND_CFG_DEVICE_RST_BANK0_WIDTH 1
86 /* The mask used to set the ALT_NAND_CFG_DEVICE_RST_BANK0 register field value. */
87 #define ALT_NAND_CFG_DEVICE_RST_BANK0_SET_MSK 0x00000001
88 /* The mask used to clear the ALT_NAND_CFG_DEVICE_RST_BANK0 register field value. */
89 #define ALT_NAND_CFG_DEVICE_RST_BANK0_CLR_MSK 0xfffffffe
90 /* The reset value of the ALT_NAND_CFG_DEVICE_RST_BANK0 register field. */
91 #define ALT_NAND_CFG_DEVICE_RST_BANK0_RESET 0x0
92 /* Extracts the ALT_NAND_CFG_DEVICE_RST_BANK0 field value from a register. */
93 #define ALT_NAND_CFG_DEVICE_RST_BANK0_GET(value) (((value) & 0x00000001) >> 0)
94 /* Produces a ALT_NAND_CFG_DEVICE_RST_BANK0 register field value suitable for setting the register. */
95 #define ALT_NAND_CFG_DEVICE_RST_BANK0_SET(value) (((value) << 0) & 0x00000001)
96 
97 /*
98  * Field : bank1
99  *
100  * Issues reset to bank 1. Controller resets the bit after
101  *
102  * reset command is issued to device.
103  *
104  * Field Access Macros:
105  *
106  */
107 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK1 register field. */
108 #define ALT_NAND_CFG_DEVICE_RST_BANK1_LSB 1
109 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK1 register field. */
110 #define ALT_NAND_CFG_DEVICE_RST_BANK1_MSB 1
111 /* The width in bits of the ALT_NAND_CFG_DEVICE_RST_BANK1 register field. */
112 #define ALT_NAND_CFG_DEVICE_RST_BANK1_WIDTH 1
113 /* The mask used to set the ALT_NAND_CFG_DEVICE_RST_BANK1 register field value. */
114 #define ALT_NAND_CFG_DEVICE_RST_BANK1_SET_MSK 0x00000002
115 /* The mask used to clear the ALT_NAND_CFG_DEVICE_RST_BANK1 register field value. */
116 #define ALT_NAND_CFG_DEVICE_RST_BANK1_CLR_MSK 0xfffffffd
117 /* The reset value of the ALT_NAND_CFG_DEVICE_RST_BANK1 register field. */
118 #define ALT_NAND_CFG_DEVICE_RST_BANK1_RESET 0x0
119 /* Extracts the ALT_NAND_CFG_DEVICE_RST_BANK1 field value from a register. */
120 #define ALT_NAND_CFG_DEVICE_RST_BANK1_GET(value) (((value) & 0x00000002) >> 1)
121 /* Produces a ALT_NAND_CFG_DEVICE_RST_BANK1 register field value suitable for setting the register. */
122 #define ALT_NAND_CFG_DEVICE_RST_BANK1_SET(value) (((value) << 1) & 0x00000002)
123 
124 /*
125  * Field : bank2
126  *
127  * Issues reset to bank 2. Controller resets the bit after
128  *
129  * reset command is issued to device.
130  *
131  * Field Access Macros:
132  *
133  */
134 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK2 register field. */
135 #define ALT_NAND_CFG_DEVICE_RST_BANK2_LSB 2
136 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK2 register field. */
137 #define ALT_NAND_CFG_DEVICE_RST_BANK2_MSB 2
138 /* The width in bits of the ALT_NAND_CFG_DEVICE_RST_BANK2 register field. */
139 #define ALT_NAND_CFG_DEVICE_RST_BANK2_WIDTH 1
140 /* The mask used to set the ALT_NAND_CFG_DEVICE_RST_BANK2 register field value. */
141 #define ALT_NAND_CFG_DEVICE_RST_BANK2_SET_MSK 0x00000004
142 /* The mask used to clear the ALT_NAND_CFG_DEVICE_RST_BANK2 register field value. */
143 #define ALT_NAND_CFG_DEVICE_RST_BANK2_CLR_MSK 0xfffffffb
144 /* The reset value of the ALT_NAND_CFG_DEVICE_RST_BANK2 register field. */
145 #define ALT_NAND_CFG_DEVICE_RST_BANK2_RESET 0x0
146 /* Extracts the ALT_NAND_CFG_DEVICE_RST_BANK2 field value from a register. */
147 #define ALT_NAND_CFG_DEVICE_RST_BANK2_GET(value) (((value) & 0x00000004) >> 2)
148 /* Produces a ALT_NAND_CFG_DEVICE_RST_BANK2 register field value suitable for setting the register. */
149 #define ALT_NAND_CFG_DEVICE_RST_BANK2_SET(value) (((value) << 2) & 0x00000004)
150 
151 /*
152  * Field : bank3
153  *
154  * Issues reset to bank 3. Controller resets the bit after
155  *
156  * reset command is issued to device.
157  *
158  * Field Access Macros:
159  *
160  */
161 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK3 register field. */
162 #define ALT_NAND_CFG_DEVICE_RST_BANK3_LSB 3
163 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK3 register field. */
164 #define ALT_NAND_CFG_DEVICE_RST_BANK3_MSB 3
165 /* The width in bits of the ALT_NAND_CFG_DEVICE_RST_BANK3 register field. */
166 #define ALT_NAND_CFG_DEVICE_RST_BANK3_WIDTH 1
167 /* The mask used to set the ALT_NAND_CFG_DEVICE_RST_BANK3 register field value. */
168 #define ALT_NAND_CFG_DEVICE_RST_BANK3_SET_MSK 0x00000008
169 /* The mask used to clear the ALT_NAND_CFG_DEVICE_RST_BANK3 register field value. */
170 #define ALT_NAND_CFG_DEVICE_RST_BANK3_CLR_MSK 0xfffffff7
171 /* The reset value of the ALT_NAND_CFG_DEVICE_RST_BANK3 register field. */
172 #define ALT_NAND_CFG_DEVICE_RST_BANK3_RESET 0x0
173 /* Extracts the ALT_NAND_CFG_DEVICE_RST_BANK3 field value from a register. */
174 #define ALT_NAND_CFG_DEVICE_RST_BANK3_GET(value) (((value) & 0x00000008) >> 3)
175 /* Produces a ALT_NAND_CFG_DEVICE_RST_BANK3 register field value suitable for setting the register. */
176 #define ALT_NAND_CFG_DEVICE_RST_BANK3_SET(value) (((value) << 3) & 0x00000008)
177 
178 #ifndef __ASSEMBLY__
179 /*
180  * WARNING: The C register and register group struct declarations are provided for
181  * convenience and illustrative purposes. They should, however, be used with
182  * caution as the C language standard provides no guarantees about the alignment or
183  * atomicity of device memory accesses. The recommended practice for writing
184  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
185  * alt_write_word() functions.
186  *
187  * The struct declaration for register ALT_NAND_CFG_DEVICE_RST.
188  */
189 struct ALT_NAND_CFG_DEVICE_RST_s
190 {
191  uint32_t bank0 : 1; /* ALT_NAND_CFG_DEVICE_RST_BANK0 */
192  uint32_t bank1 : 1; /* ALT_NAND_CFG_DEVICE_RST_BANK1 */
193  uint32_t bank2 : 1; /* ALT_NAND_CFG_DEVICE_RST_BANK2 */
194  uint32_t bank3 : 1; /* ALT_NAND_CFG_DEVICE_RST_BANK3 */
195  uint32_t : 28; /* *UNDEFINED* */
196 };
197 
198 /* The typedef declaration for register ALT_NAND_CFG_DEVICE_RST. */
199 typedef volatile struct ALT_NAND_CFG_DEVICE_RST_s ALT_NAND_CFG_DEVICE_RST_t;
200 #endif /* __ASSEMBLY__ */
201 
202 /* The reset value of the ALT_NAND_CFG_DEVICE_RST register. */
203 #define ALT_NAND_CFG_DEVICE_RST_RESET 0x00000000
204 /* The byte offset of the ALT_NAND_CFG_DEVICE_RST register from the beginning of the component. */
205 #define ALT_NAND_CFG_DEVICE_RST_OFST 0x0
206 
207 /*
208  * Register : transfer_spare_reg
209  *
210  * Default data transfer mode. (Ignored during Spare only mode)
211  *
212  * Register Layout
213  *
214  * Bits | Access | Reset | Description
215  * :-------|:-------|:--------|:--------------------------------
216  * [0] | RW | 0x0 | ALT_NAND_CFG_TFR_SPARE_REG_FLAG
217  * [31:1] | ??? | Unknown | *UNDEFINED*
218  *
219  */
220 /*
221  * Field : flag
222  *
223  * On all read or write commands through Map 01, if this bit is set,
224  *
225  * data in spare area of memory will be transfered to host along with
226  *
227  * main area of data. The main area will be transfered followed by
228  *
229  * spare area.[list][*]1 - MAIN+SPARE [*]0 - MAIN[/list]
230  *
231  * Field Access Macros:
232  *
233  */
234 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TFR_SPARE_REG_FLAG register field. */
235 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_LSB 0
236 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TFR_SPARE_REG_FLAG register field. */
237 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_MSB 0
238 /* The width in bits of the ALT_NAND_CFG_TFR_SPARE_REG_FLAG register field. */
239 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_WIDTH 1
240 /* The mask used to set the ALT_NAND_CFG_TFR_SPARE_REG_FLAG register field value. */
241 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_SET_MSK 0x00000001
242 /* The mask used to clear the ALT_NAND_CFG_TFR_SPARE_REG_FLAG register field value. */
243 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_CLR_MSK 0xfffffffe
244 /* The reset value of the ALT_NAND_CFG_TFR_SPARE_REG_FLAG register field. */
245 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_RESET 0x0
246 /* Extracts the ALT_NAND_CFG_TFR_SPARE_REG_FLAG field value from a register. */
247 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_GET(value) (((value) & 0x00000001) >> 0)
248 /* Produces a ALT_NAND_CFG_TFR_SPARE_REG_FLAG register field value suitable for setting the register. */
249 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_SET(value) (((value) << 0) & 0x00000001)
250 
251 #ifndef __ASSEMBLY__
252 /*
253  * WARNING: The C register and register group struct declarations are provided for
254  * convenience and illustrative purposes. They should, however, be used with
255  * caution as the C language standard provides no guarantees about the alignment or
256  * atomicity of device memory accesses. The recommended practice for writing
257  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
258  * alt_write_word() functions.
259  *
260  * The struct declaration for register ALT_NAND_CFG_TFR_SPARE_REG.
261  */
262 struct ALT_NAND_CFG_TFR_SPARE_REG_s
263 {
264  uint32_t flag : 1; /* ALT_NAND_CFG_TFR_SPARE_REG_FLAG */
265  uint32_t : 31; /* *UNDEFINED* */
266 };
267 
268 /* The typedef declaration for register ALT_NAND_CFG_TFR_SPARE_REG. */
269 typedef volatile struct ALT_NAND_CFG_TFR_SPARE_REG_s ALT_NAND_CFG_TFR_SPARE_REG_t;
270 #endif /* __ASSEMBLY__ */
271 
272 /* The reset value of the ALT_NAND_CFG_TFR_SPARE_REG register. */
273 #define ALT_NAND_CFG_TFR_SPARE_REG_RESET 0x00000000
274 /* The byte offset of the ALT_NAND_CFG_TFR_SPARE_REG register from the beginning of the component. */
275 #define ALT_NAND_CFG_TFR_SPARE_REG_OFST 0x10
276 
277 /*
278  * Register : load_wait_cnt
279  *
280  * Wait count value for Load operation
281  *
282  * Register Layout
283  *
284  * Bits | Access | Reset | Description
285  * :--------|:-------|:--------|:-------------------------------
286  * [15:0] | RW | 0x1f4 | ALT_NAND_CFG_LD_WAIT_CNT_VALUE
287  * [31:16] | ??? | Unknown | *UNDEFINED*
288  *
289  */
290 /*
291  * Field : value
292  *
293  * Number of clock cycles after issue of load operation before
294  *
295  * Cadence NAND Flash Controller polls for status. This values is of
296  *
297  * relevance for status polling mode of operation and has been
298  *
299  * provided to minimize redundant polling after issuing a command.
300  *
301  * After a load command, the first polling will happen after this many
302  *
303  * number of cycles have elapsed and then on polling will happen every
304  *
305  * intmon_cyc_cnt cycles.
306  *
307  * The default values is equal to the
308  *
309  * default value of intmon_cyc_cnt.
310  *
311  * Field Access Macros:
312  *
313  */
314 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_LD_WAIT_CNT_VALUE register field. */
315 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_LSB 0
316 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_LD_WAIT_CNT_VALUE register field. */
317 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_MSB 15
318 /* The width in bits of the ALT_NAND_CFG_LD_WAIT_CNT_VALUE register field. */
319 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_WIDTH 16
320 /* The mask used to set the ALT_NAND_CFG_LD_WAIT_CNT_VALUE register field value. */
321 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
322 /* The mask used to clear the ALT_NAND_CFG_LD_WAIT_CNT_VALUE register field value. */
323 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
324 /* The reset value of the ALT_NAND_CFG_LD_WAIT_CNT_VALUE register field. */
325 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_RESET 0x1f4
326 /* Extracts the ALT_NAND_CFG_LD_WAIT_CNT_VALUE field value from a register. */
327 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
328 /* Produces a ALT_NAND_CFG_LD_WAIT_CNT_VALUE register field value suitable for setting the register. */
329 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
330 
331 #ifndef __ASSEMBLY__
332 /*
333  * WARNING: The C register and register group struct declarations are provided for
334  * convenience and illustrative purposes. They should, however, be used with
335  * caution as the C language standard provides no guarantees about the alignment or
336  * atomicity of device memory accesses. The recommended practice for writing
337  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
338  * alt_write_word() functions.
339  *
340  * The struct declaration for register ALT_NAND_CFG_LD_WAIT_CNT.
341  */
342 struct ALT_NAND_CFG_LD_WAIT_CNT_s
343 {
344  uint32_t value : 16; /* ALT_NAND_CFG_LD_WAIT_CNT_VALUE */
345  uint32_t : 16; /* *UNDEFINED* */
346 };
347 
348 /* The typedef declaration for register ALT_NAND_CFG_LD_WAIT_CNT. */
349 typedef volatile struct ALT_NAND_CFG_LD_WAIT_CNT_s ALT_NAND_CFG_LD_WAIT_CNT_t;
350 #endif /* __ASSEMBLY__ */
351 
352 /* The reset value of the ALT_NAND_CFG_LD_WAIT_CNT register. */
353 #define ALT_NAND_CFG_LD_WAIT_CNT_RESET 0x000001f4
354 /* The byte offset of the ALT_NAND_CFG_LD_WAIT_CNT register from the beginning of the component. */
355 #define ALT_NAND_CFG_LD_WAIT_CNT_OFST 0x20
356 
357 /*
358  * Register : program_wait_cnt
359  *
360  * Wait count value for Program operation
361  *
362  * Register Layout
363  *
364  * Bits | Access | Reset | Description
365  * :--------|:-------|:--------|:------------------------------------
366  * [15:0] | RW | 0x1f40 | ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE
367  * [31:16] | ??? | Unknown | *UNDEFINED*
368  *
369  */
370 /*
371  * Field : value
372  *
373  * Number of clock cycles after issue of program operation before
374  *
375  * Cadence NAND Flash Controller polls for status. This values is of
376  *
377  * relevance for status polling mode of operation and has been
378  *
379  * provided to minimize redundant polling after issuing a command.
380  *
381  * After a program command, the first polling will happen after this many
382  *
383  * number of cycles have elapsed and then on polling will happen every
384  *
385  * intmon_cyc_cnt cycles.
386  *
387  * The default values is equal to the
388  *
389  * default value of intmon_cyc_cnt. The controller internally multiplies
390  *
391  * the value programmed into this register by 16 to provide a wider
392  *
393  * range for polling.
394  *
395  * Field Access Macros:
396  *
397  */
398 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field. */
399 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_LSB 0
400 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field. */
401 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_MSB 15
402 /* The width in bits of the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field. */
403 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_WIDTH 16
404 /* The mask used to set the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field value. */
405 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
406 /* The mask used to clear the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field value. */
407 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
408 /* The reset value of the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field. */
409 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_RESET 0x1f40
410 /* Extracts the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE field value from a register. */
411 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
412 /* Produces a ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field value suitable for setting the register. */
413 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
414 
415 #ifndef __ASSEMBLY__
416 /*
417  * WARNING: The C register and register group struct declarations are provided for
418  * convenience and illustrative purposes. They should, however, be used with
419  * caution as the C language standard provides no guarantees about the alignment or
420  * atomicity of device memory accesses. The recommended practice for writing
421  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
422  * alt_write_word() functions.
423  *
424  * The struct declaration for register ALT_NAND_CFG_PROGRAM_WAIT_CNT.
425  */
426 struct ALT_NAND_CFG_PROGRAM_WAIT_CNT_s
427 {
428  uint32_t value : 16; /* ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE */
429  uint32_t : 16; /* *UNDEFINED* */
430 };
431 
432 /* The typedef declaration for register ALT_NAND_CFG_PROGRAM_WAIT_CNT. */
433 typedef volatile struct ALT_NAND_CFG_PROGRAM_WAIT_CNT_s ALT_NAND_CFG_PROGRAM_WAIT_CNT_t;
434 #endif /* __ASSEMBLY__ */
435 
436 /* The reset value of the ALT_NAND_CFG_PROGRAM_WAIT_CNT register. */
437 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_RESET 0x00001f40
438 /* The byte offset of the ALT_NAND_CFG_PROGRAM_WAIT_CNT register from the beginning of the component. */
439 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_OFST 0x30
440 
441 /*
442  * Register : erase_wait_cnt
443  *
444  * Wait count value for Erase operation
445  *
446  * Register Layout
447  *
448  * Bits | Access | Reset | Description
449  * :--------|:-------|:--------|:----------------------------------
450  * [15:0] | RW | 0x1f40 | ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE
451  * [31:16] | ??? | Unknown | *UNDEFINED*
452  *
453  */
454 /*
455  * Field : value
456  *
457  * Number of clock cycles after issue of erase operation before
458  *
459  * Cadence NAND Flash Controller polls for status. This values is of
460  *
461  * relevance for status polling mode of operation and has been
462  *
463  * provided to minimize redundant polling after issuing a command.
464  *
465  * After a erase command, the first polling will happen after this many
466  *
467  * number of cycles have elapsed and then on polling will happen every
468  *
469  * intmon_cyc_cnt cycles.
470  *
471  * The default values is equal to the
472  *
473  * default value of intmon_cyc_cnt. The controller internally multiplies
474  *
475  * the value programmed into this register by 16 to provide a wider
476  *
477  * range for polling.
478  *
479  * Field Access Macros:
480  *
481  */
482 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field. */
483 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_LSB 0
484 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field. */
485 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_MSB 15
486 /* The width in bits of the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field. */
487 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_WIDTH 16
488 /* The mask used to set the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field value. */
489 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
490 /* The mask used to clear the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field value. */
491 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
492 /* The reset value of the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field. */
493 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_RESET 0x1f40
494 /* Extracts the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE field value from a register. */
495 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
496 /* Produces a ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field value suitable for setting the register. */
497 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
498 
499 #ifndef __ASSEMBLY__
500 /*
501  * WARNING: The C register and register group struct declarations are provided for
502  * convenience and illustrative purposes. They should, however, be used with
503  * caution as the C language standard provides no guarantees about the alignment or
504  * atomicity of device memory accesses. The recommended practice for writing
505  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
506  * alt_write_word() functions.
507  *
508  * The struct declaration for register ALT_NAND_CFG_ERASE_WAIT_CNT.
509  */
510 struct ALT_NAND_CFG_ERASE_WAIT_CNT_s
511 {
512  uint32_t value : 16; /* ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE */
513  uint32_t : 16; /* *UNDEFINED* */
514 };
515 
516 /* The typedef declaration for register ALT_NAND_CFG_ERASE_WAIT_CNT. */
517 typedef volatile struct ALT_NAND_CFG_ERASE_WAIT_CNT_s ALT_NAND_CFG_ERASE_WAIT_CNT_t;
518 #endif /* __ASSEMBLY__ */
519 
520 /* The reset value of the ALT_NAND_CFG_ERASE_WAIT_CNT register. */
521 #define ALT_NAND_CFG_ERASE_WAIT_CNT_RESET 0x00001f40
522 /* The byte offset of the ALT_NAND_CFG_ERASE_WAIT_CNT register from the beginning of the component. */
523 #define ALT_NAND_CFG_ERASE_WAIT_CNT_OFST 0x40
524 
525 /*
526  * Register : int_mon_cyccnt
527  *
528  * Interrupt monitor cycle count value
529  *
530  * Register Layout
531  *
532  * Bits | Access | Reset | Description
533  * :--------|:-------|:--------|:----------------------------------
534  * [15:0] | RW | 0x1f4 | ALT_NAND_CFG_INT_MON_CYCCNT_VALUE
535  * [31:16] | ??? | Unknown | *UNDEFINED*
536  *
537  */
538 /*
539  * Field : value
540  *
541  * In polling mode, sets the number of cycles Cadence Flash Controller
542  *
543  * must wait before checking the status register. This register is
544  *
545  * only used when R/B pins are not available to Cadence NAND Flash
546  *
547  * Controller.
548  *
549  * Field Access Macros:
550  *
551  */
552 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field. */
553 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_LSB 0
554 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field. */
555 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_MSB 15
556 /* The width in bits of the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field. */
557 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_WIDTH 16
558 /* The mask used to set the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field value. */
559 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_SET_MSK 0x0000ffff
560 /* The mask used to clear the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field value. */
561 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_CLR_MSK 0xffff0000
562 /* The reset value of the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field. */
563 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_RESET 0x1f4
564 /* Extracts the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE field value from a register. */
565 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
566 /* Produces a ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field value suitable for setting the register. */
567 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
568 
569 #ifndef __ASSEMBLY__
570 /*
571  * WARNING: The C register and register group struct declarations are provided for
572  * convenience and illustrative purposes. They should, however, be used with
573  * caution as the C language standard provides no guarantees about the alignment or
574  * atomicity of device memory accesses. The recommended practice for writing
575  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
576  * alt_write_word() functions.
577  *
578  * The struct declaration for register ALT_NAND_CFG_INT_MON_CYCCNT.
579  */
580 struct ALT_NAND_CFG_INT_MON_CYCCNT_s
581 {
582  uint32_t value : 16; /* ALT_NAND_CFG_INT_MON_CYCCNT_VALUE */
583  uint32_t : 16; /* *UNDEFINED* */
584 };
585 
586 /* The typedef declaration for register ALT_NAND_CFG_INT_MON_CYCCNT. */
587 typedef volatile struct ALT_NAND_CFG_INT_MON_CYCCNT_s ALT_NAND_CFG_INT_MON_CYCCNT_t;
588 #endif /* __ASSEMBLY__ */
589 
590 /* The reset value of the ALT_NAND_CFG_INT_MON_CYCCNT register. */
591 #define ALT_NAND_CFG_INT_MON_CYCCNT_RESET 0x000001f4
592 /* The byte offset of the ALT_NAND_CFG_INT_MON_CYCCNT register from the beginning of the component. */
593 #define ALT_NAND_CFG_INT_MON_CYCCNT_OFST 0x50
594 
595 /*
596  * Register : rb_pin_enabled
597  *
598  * Interrupt or polling mode. Ready/Busy pin is enabled from device.
599  *
600  * Register Layout
601  *
602  * Bits | Access | Reset | Description
603  * :-------|:-------|:--------|:------------------------------
604  * [0] | RW | 0x1 | ALT_NAND_CFG_RB_PIN_END_BANK0
605  * [1] | RW | 0x0 | ALT_NAND_CFG_RB_PIN_END_BANK1
606  * [2] | RW | 0x0 | ALT_NAND_CFG_RB_PIN_END_BANK2
607  * [3] | RW | 0x0 | ALT_NAND_CFG_RB_PIN_END_BANK3
608  * [31:4] | ??? | Unknown | *UNDEFINED*
609  *
610  */
611 /*
612  * Field : bank0
613  *
614  * Sets Cadence Flash Controller in interrupt pin or polling mode
615  *
616  * [list][*]1 - R/B pin enabled for bank 0. Interrupt pin mode.
617  *
618  * [*]0 - R/B pin disabled for bank 0. Polling mode.[/list]
619  *
620  * Field Access Macros:
621  *
622  */
623 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK0 register field. */
624 #define ALT_NAND_CFG_RB_PIN_END_BANK0_LSB 0
625 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK0 register field. */
626 #define ALT_NAND_CFG_RB_PIN_END_BANK0_MSB 0
627 /* The width in bits of the ALT_NAND_CFG_RB_PIN_END_BANK0 register field. */
628 #define ALT_NAND_CFG_RB_PIN_END_BANK0_WIDTH 1
629 /* The mask used to set the ALT_NAND_CFG_RB_PIN_END_BANK0 register field value. */
630 #define ALT_NAND_CFG_RB_PIN_END_BANK0_SET_MSK 0x00000001
631 /* The mask used to clear the ALT_NAND_CFG_RB_PIN_END_BANK0 register field value. */
632 #define ALT_NAND_CFG_RB_PIN_END_BANK0_CLR_MSK 0xfffffffe
633 /* The reset value of the ALT_NAND_CFG_RB_PIN_END_BANK0 register field. */
634 #define ALT_NAND_CFG_RB_PIN_END_BANK0_RESET 0x1
635 /* Extracts the ALT_NAND_CFG_RB_PIN_END_BANK0 field value from a register. */
636 #define ALT_NAND_CFG_RB_PIN_END_BANK0_GET(value) (((value) & 0x00000001) >> 0)
637 /* Produces a ALT_NAND_CFG_RB_PIN_END_BANK0 register field value suitable for setting the register. */
638 #define ALT_NAND_CFG_RB_PIN_END_BANK0_SET(value) (((value) << 0) & 0x00000001)
639 
640 /*
641  * Field : bank1
642  *
643  * Sets Cadence Flash Controller in interrupt pin or polling mode
644  *
645  * [list][*]1 - R/B pin enabled for bank 1. Interrupt pin mode.
646  *
647  * [*]0 - R/B pin disabled for bank 1. Polling mode.[/list]
648  *
649  * Field Access Macros:
650  *
651  */
652 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK1 register field. */
653 #define ALT_NAND_CFG_RB_PIN_END_BANK1_LSB 1
654 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK1 register field. */
655 #define ALT_NAND_CFG_RB_PIN_END_BANK1_MSB 1
656 /* The width in bits of the ALT_NAND_CFG_RB_PIN_END_BANK1 register field. */
657 #define ALT_NAND_CFG_RB_PIN_END_BANK1_WIDTH 1
658 /* The mask used to set the ALT_NAND_CFG_RB_PIN_END_BANK1 register field value. */
659 #define ALT_NAND_CFG_RB_PIN_END_BANK1_SET_MSK 0x00000002
660 /* The mask used to clear the ALT_NAND_CFG_RB_PIN_END_BANK1 register field value. */
661 #define ALT_NAND_CFG_RB_PIN_END_BANK1_CLR_MSK 0xfffffffd
662 /* The reset value of the ALT_NAND_CFG_RB_PIN_END_BANK1 register field. */
663 #define ALT_NAND_CFG_RB_PIN_END_BANK1_RESET 0x0
664 /* Extracts the ALT_NAND_CFG_RB_PIN_END_BANK1 field value from a register. */
665 #define ALT_NAND_CFG_RB_PIN_END_BANK1_GET(value) (((value) & 0x00000002) >> 1)
666 /* Produces a ALT_NAND_CFG_RB_PIN_END_BANK1 register field value suitable for setting the register. */
667 #define ALT_NAND_CFG_RB_PIN_END_BANK1_SET(value) (((value) << 1) & 0x00000002)
668 
669 /*
670  * Field : bank2
671  *
672  * Sets Cadence Flash Controller in interrupt pin or polling mode
673  *
674  * [list][*]1 - R/B pin enabled for bank 2. Interrupt pin mode.
675  *
676  * [*]0 - R/B pin disabled for bank 2. Polling mode.[/list]
677  *
678  * Field Access Macros:
679  *
680  */
681 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK2 register field. */
682 #define ALT_NAND_CFG_RB_PIN_END_BANK2_LSB 2
683 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK2 register field. */
684 #define ALT_NAND_CFG_RB_PIN_END_BANK2_MSB 2
685 /* The width in bits of the ALT_NAND_CFG_RB_PIN_END_BANK2 register field. */
686 #define ALT_NAND_CFG_RB_PIN_END_BANK2_WIDTH 1
687 /* The mask used to set the ALT_NAND_CFG_RB_PIN_END_BANK2 register field value. */
688 #define ALT_NAND_CFG_RB_PIN_END_BANK2_SET_MSK 0x00000004
689 /* The mask used to clear the ALT_NAND_CFG_RB_PIN_END_BANK2 register field value. */
690 #define ALT_NAND_CFG_RB_PIN_END_BANK2_CLR_MSK 0xfffffffb
691 /* The reset value of the ALT_NAND_CFG_RB_PIN_END_BANK2 register field. */
692 #define ALT_NAND_CFG_RB_PIN_END_BANK2_RESET 0x0
693 /* Extracts the ALT_NAND_CFG_RB_PIN_END_BANK2 field value from a register. */
694 #define ALT_NAND_CFG_RB_PIN_END_BANK2_GET(value) (((value) & 0x00000004) >> 2)
695 /* Produces a ALT_NAND_CFG_RB_PIN_END_BANK2 register field value suitable for setting the register. */
696 #define ALT_NAND_CFG_RB_PIN_END_BANK2_SET(value) (((value) << 2) & 0x00000004)
697 
698 /*
699  * Field : bank3
700  *
701  * Sets Cadence Flash Controller in interrupt pin or polling mode
702  *
703  * [list][*]1 - R/B pin enabled for bank 3. Interrupt pin mode.
704  *
705  * [*]0 - R/B pin disabled for bank 3. Polling mode.[/list]
706  *
707  * Field Access Macros:
708  *
709  */
710 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK3 register field. */
711 #define ALT_NAND_CFG_RB_PIN_END_BANK3_LSB 3
712 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK3 register field. */
713 #define ALT_NAND_CFG_RB_PIN_END_BANK3_MSB 3
714 /* The width in bits of the ALT_NAND_CFG_RB_PIN_END_BANK3 register field. */
715 #define ALT_NAND_CFG_RB_PIN_END_BANK3_WIDTH 1
716 /* The mask used to set the ALT_NAND_CFG_RB_PIN_END_BANK3 register field value. */
717 #define ALT_NAND_CFG_RB_PIN_END_BANK3_SET_MSK 0x00000008
718 /* The mask used to clear the ALT_NAND_CFG_RB_PIN_END_BANK3 register field value. */
719 #define ALT_NAND_CFG_RB_PIN_END_BANK3_CLR_MSK 0xfffffff7
720 /* The reset value of the ALT_NAND_CFG_RB_PIN_END_BANK3 register field. */
721 #define ALT_NAND_CFG_RB_PIN_END_BANK3_RESET 0x0
722 /* Extracts the ALT_NAND_CFG_RB_PIN_END_BANK3 field value from a register. */
723 #define ALT_NAND_CFG_RB_PIN_END_BANK3_GET(value) (((value) & 0x00000008) >> 3)
724 /* Produces a ALT_NAND_CFG_RB_PIN_END_BANK3 register field value suitable for setting the register. */
725 #define ALT_NAND_CFG_RB_PIN_END_BANK3_SET(value) (((value) << 3) & 0x00000008)
726 
727 #ifndef __ASSEMBLY__
728 /*
729  * WARNING: The C register and register group struct declarations are provided for
730  * convenience and illustrative purposes. They should, however, be used with
731  * caution as the C language standard provides no guarantees about the alignment or
732  * atomicity of device memory accesses. The recommended practice for writing
733  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
734  * alt_write_word() functions.
735  *
736  * The struct declaration for register ALT_NAND_CFG_RB_PIN_END.
737  */
738 struct ALT_NAND_CFG_RB_PIN_END_s
739 {
740  uint32_t bank0 : 1; /* ALT_NAND_CFG_RB_PIN_END_BANK0 */
741  uint32_t bank1 : 1; /* ALT_NAND_CFG_RB_PIN_END_BANK1 */
742  uint32_t bank2 : 1; /* ALT_NAND_CFG_RB_PIN_END_BANK2 */
743  uint32_t bank3 : 1; /* ALT_NAND_CFG_RB_PIN_END_BANK3 */
744  uint32_t : 28; /* *UNDEFINED* */
745 };
746 
747 /* The typedef declaration for register ALT_NAND_CFG_RB_PIN_END. */
748 typedef volatile struct ALT_NAND_CFG_RB_PIN_END_s ALT_NAND_CFG_RB_PIN_END_t;
749 #endif /* __ASSEMBLY__ */
750 
751 /* The reset value of the ALT_NAND_CFG_RB_PIN_END register. */
752 #define ALT_NAND_CFG_RB_PIN_END_RESET 0x00000001
753 /* The byte offset of the ALT_NAND_CFG_RB_PIN_END register from the beginning of the component. */
754 #define ALT_NAND_CFG_RB_PIN_END_OFST 0x60
755 
756 /*
757  * Register : multiplane_operation
758  *
759  * Multiplane transfer mode. Pipelined read, copyback, erase
760  *
761  * and program commands are transfered in multiplane mode
762  *
763  * Register Layout
764  *
765  * Bits | Access | Reset | Description
766  * :-------|:-------|:--------|:--------------------------------
767  * [0] | RW | 0x0 | ALT_NAND_CFG_MULTIPLANE_OP_FLAG
768  * [31:1] | ??? | Unknown | *UNDEFINED*
769  *
770  */
771 /*
772  * Field : flag
773  *
774  * [list][*]1 - Multiplane operation enabled
775  *
776  * [*]0 - Multiplane operation disabled[/list]
777  *
778  * Field Access Macros:
779  *
780  */
781 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_MULTIPLANE_OP_FLAG register field. */
782 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_LSB 0
783 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_MULTIPLANE_OP_FLAG register field. */
784 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_MSB 0
785 /* The width in bits of the ALT_NAND_CFG_MULTIPLANE_OP_FLAG register field. */
786 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_WIDTH 1
787 /* The mask used to set the ALT_NAND_CFG_MULTIPLANE_OP_FLAG register field value. */
788 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_SET_MSK 0x00000001
789 /* The mask used to clear the ALT_NAND_CFG_MULTIPLANE_OP_FLAG register field value. */
790 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_CLR_MSK 0xfffffffe
791 /* The reset value of the ALT_NAND_CFG_MULTIPLANE_OP_FLAG register field. */
792 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_RESET 0x0
793 /* Extracts the ALT_NAND_CFG_MULTIPLANE_OP_FLAG field value from a register. */
794 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_GET(value) (((value) & 0x00000001) >> 0)
795 /* Produces a ALT_NAND_CFG_MULTIPLANE_OP_FLAG register field value suitable for setting the register. */
796 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_SET(value) (((value) << 0) & 0x00000001)
797 
798 #ifndef __ASSEMBLY__
799 /*
800  * WARNING: The C register and register group struct declarations are provided for
801  * convenience and illustrative purposes. They should, however, be used with
802  * caution as the C language standard provides no guarantees about the alignment or
803  * atomicity of device memory accesses. The recommended practice for writing
804  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
805  * alt_write_word() functions.
806  *
807  * The struct declaration for register ALT_NAND_CFG_MULTIPLANE_OP.
808  */
809 struct ALT_NAND_CFG_MULTIPLANE_OP_s
810 {
811  uint32_t flag : 1; /* ALT_NAND_CFG_MULTIPLANE_OP_FLAG */
812  uint32_t : 31; /* *UNDEFINED* */
813 };
814 
815 /* The typedef declaration for register ALT_NAND_CFG_MULTIPLANE_OP. */
816 typedef volatile struct ALT_NAND_CFG_MULTIPLANE_OP_s ALT_NAND_CFG_MULTIPLANE_OP_t;
817 #endif /* __ASSEMBLY__ */
818 
819 /* The reset value of the ALT_NAND_CFG_MULTIPLANE_OP register. */
820 #define ALT_NAND_CFG_MULTIPLANE_OP_RESET 0x00000000
821 /* The byte offset of the ALT_NAND_CFG_MULTIPLANE_OP register from the beginning of the component. */
822 #define ALT_NAND_CFG_MULTIPLANE_OP_OFST 0x70
823 
824 /*
825  * Register : multiplane_read_enable
826  *
827  * Device supports multiplane read command sequence
828  *
829  * Register Layout
830  *
831  * Bits | Access | Reset | Description
832  * :-------|:-------|:--------|:-----------------------------------
833  * [0] | RW | 0x0 | ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG
834  * [31:1] | ??? | Unknown | *UNDEFINED*
835  *
836  */
837 /*
838  * Field : flag
839  *
840  * Certain devices support dedicated multiplane read command sequences
841  *
842  * to read data in the same fashion as is written with multiplane program
843  *
844  * commands. This bit set should be set for the above devices. When not set,
845  *
846  * pipeline reads in multiplane mode will still happen in the order of multiplane
847  *
848  * writes, though normal read command sequences will be issued to the device.
849  *
850  * [list][*]1 - Device supports multiplane read sequence
851  *
852  * [*]0 - Device does not support multiplane read sequence[/list]
853  *
854  * Field Access Macros:
855  *
856  */
857 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG register field. */
858 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_LSB 0
859 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG register field. */
860 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_MSB 0
861 /* The width in bits of the ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG register field. */
862 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_WIDTH 1
863 /* The mask used to set the ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG register field value. */
864 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_SET_MSK 0x00000001
865 /* The mask used to clear the ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG register field value. */
866 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_CLR_MSK 0xfffffffe
867 /* The reset value of the ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG register field. */
868 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_RESET 0x0
869 /* Extracts the ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG field value from a register. */
870 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
871 /* Produces a ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG register field value suitable for setting the register. */
872 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
873 
874 #ifndef __ASSEMBLY__
875 /*
876  * WARNING: The C register and register group struct declarations are provided for
877  * convenience and illustrative purposes. They should, however, be used with
878  * caution as the C language standard provides no guarantees about the alignment or
879  * atomicity of device memory accesses. The recommended practice for writing
880  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
881  * alt_write_word() functions.
882  *
883  * The struct declaration for register ALT_NAND_CFG_MULTIPLANE_RD_EN.
884  */
885 struct ALT_NAND_CFG_MULTIPLANE_RD_EN_s
886 {
887  uint32_t flag : 1; /* ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG */
888  uint32_t : 31; /* *UNDEFINED* */
889 };
890 
891 /* The typedef declaration for register ALT_NAND_CFG_MULTIPLANE_RD_EN. */
892 typedef volatile struct ALT_NAND_CFG_MULTIPLANE_RD_EN_s ALT_NAND_CFG_MULTIPLANE_RD_EN_t;
893 #endif /* __ASSEMBLY__ */
894 
895 /* The reset value of the ALT_NAND_CFG_MULTIPLANE_RD_EN register. */
896 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_RESET 0x00000000
897 /* The byte offset of the ALT_NAND_CFG_MULTIPLANE_RD_EN register from the beginning of the component. */
898 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_OFST 0x80
899 
900 /*
901  * Register : copyback_disable
902  *
903  * Device does not support copyback command sequence
904  *
905  * Register Layout
906  *
907  * Bits | Access | Reset | Description
908  * :-------|:-------|:--------|:-------------------------------
909  * [0] | RW | 0x0 | ALT_NAND_CFG_COPYBACK_DIS_FLAG
910  * [31:1] | ??? | Unknown | *UNDEFINED*
911  *
912  */
913 /*
914  * Field : flag
915  *
916  * [list][*]1 - Copyback disabled [*]0 - Copyback enabled[/list]
917  *
918  * Field Access Macros:
919  *
920  */
921 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_COPYBACK_DIS_FLAG register field. */
922 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_LSB 0
923 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_COPYBACK_DIS_FLAG register field. */
924 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_MSB 0
925 /* The width in bits of the ALT_NAND_CFG_COPYBACK_DIS_FLAG register field. */
926 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_WIDTH 1
927 /* The mask used to set the ALT_NAND_CFG_COPYBACK_DIS_FLAG register field value. */
928 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_SET_MSK 0x00000001
929 /* The mask used to clear the ALT_NAND_CFG_COPYBACK_DIS_FLAG register field value. */
930 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_CLR_MSK 0xfffffffe
931 /* The reset value of the ALT_NAND_CFG_COPYBACK_DIS_FLAG register field. */
932 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_RESET 0x0
933 /* Extracts the ALT_NAND_CFG_COPYBACK_DIS_FLAG field value from a register. */
934 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_GET(value) (((value) & 0x00000001) >> 0)
935 /* Produces a ALT_NAND_CFG_COPYBACK_DIS_FLAG register field value suitable for setting the register. */
936 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_SET(value) (((value) << 0) & 0x00000001)
937 
938 #ifndef __ASSEMBLY__
939 /*
940  * WARNING: The C register and register group struct declarations are provided for
941  * convenience and illustrative purposes. They should, however, be used with
942  * caution as the C language standard provides no guarantees about the alignment or
943  * atomicity of device memory accesses. The recommended practice for writing
944  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
945  * alt_write_word() functions.
946  *
947  * The struct declaration for register ALT_NAND_CFG_COPYBACK_DIS.
948  */
949 struct ALT_NAND_CFG_COPYBACK_DIS_s
950 {
951  uint32_t flag : 1; /* ALT_NAND_CFG_COPYBACK_DIS_FLAG */
952  uint32_t : 31; /* *UNDEFINED* */
953 };
954 
955 /* The typedef declaration for register ALT_NAND_CFG_COPYBACK_DIS. */
956 typedef volatile struct ALT_NAND_CFG_COPYBACK_DIS_s ALT_NAND_CFG_COPYBACK_DIS_t;
957 #endif /* __ASSEMBLY__ */
958 
959 /* The reset value of the ALT_NAND_CFG_COPYBACK_DIS register. */
960 #define ALT_NAND_CFG_COPYBACK_DIS_RESET 0x00000000
961 /* The byte offset of the ALT_NAND_CFG_COPYBACK_DIS register from the beginning of the component. */
962 #define ALT_NAND_CFG_COPYBACK_DIS_OFST 0x90
963 
964 /*
965  * Register : cache_write_enable
966  *
967  * Device supports cache write command sequence
968  *
969  * Register Layout
970  *
971  * Bits | Access | Reset | Description
972  * :-------|:-------|:--------|:------------------------------
973  * [0] | RW | 0x0 | ALT_NAND_CFG_CACHE_WR_EN_FLAG
974  * [31:1] | ??? | Unknown | *UNDEFINED*
975  *
976  */
977 /*
978  * Field : flag
979  *
980  * [list][*]1 - Cache write supported [*]0 - Cache write not supported[/list]
981  *
982  * Field Access Macros:
983  *
984  */
985 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_CACHE_WR_EN_FLAG register field. */
986 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_LSB 0
987 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_CACHE_WR_EN_FLAG register field. */
988 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_MSB 0
989 /* The width in bits of the ALT_NAND_CFG_CACHE_WR_EN_FLAG register field. */
990 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_WIDTH 1
991 /* The mask used to set the ALT_NAND_CFG_CACHE_WR_EN_FLAG register field value. */
992 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_SET_MSK 0x00000001
993 /* The mask used to clear the ALT_NAND_CFG_CACHE_WR_EN_FLAG register field value. */
994 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_CLR_MSK 0xfffffffe
995 /* The reset value of the ALT_NAND_CFG_CACHE_WR_EN_FLAG register field. */
996 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_RESET 0x0
997 /* Extracts the ALT_NAND_CFG_CACHE_WR_EN_FLAG field value from a register. */
998 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
999 /* Produces a ALT_NAND_CFG_CACHE_WR_EN_FLAG register field value suitable for setting the register. */
1000 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
1001 
1002 #ifndef __ASSEMBLY__
1003 /*
1004  * WARNING: The C register and register group struct declarations are provided for
1005  * convenience and illustrative purposes. They should, however, be used with
1006  * caution as the C language standard provides no guarantees about the alignment or
1007  * atomicity of device memory accesses. The recommended practice for writing
1008  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1009  * alt_write_word() functions.
1010  *
1011  * The struct declaration for register ALT_NAND_CFG_CACHE_WR_EN.
1012  */
1013 struct ALT_NAND_CFG_CACHE_WR_EN_s
1014 {
1015  uint32_t flag : 1; /* ALT_NAND_CFG_CACHE_WR_EN_FLAG */
1016  uint32_t : 31; /* *UNDEFINED* */
1017 };
1018 
1019 /* The typedef declaration for register ALT_NAND_CFG_CACHE_WR_EN. */
1020 typedef volatile struct ALT_NAND_CFG_CACHE_WR_EN_s ALT_NAND_CFG_CACHE_WR_EN_t;
1021 #endif /* __ASSEMBLY__ */
1022 
1023 /* The reset value of the ALT_NAND_CFG_CACHE_WR_EN register. */
1024 #define ALT_NAND_CFG_CACHE_WR_EN_RESET 0x00000000
1025 /* The byte offset of the ALT_NAND_CFG_CACHE_WR_EN register from the beginning of the component. */
1026 #define ALT_NAND_CFG_CACHE_WR_EN_OFST 0xa0
1027 
1028 /*
1029  * Register : cache_read_enable
1030  *
1031  * Device supports cache read command sequence
1032  *
1033  * Register Layout
1034  *
1035  * Bits | Access | Reset | Description
1036  * :-------|:-------|:--------|:------------------------------
1037  * [0] | RW | 0x0 | ALT_NAND_CFG_CACHE_RD_EN_FLAG
1038  * [31:1] | ??? | Unknown | *UNDEFINED*
1039  *
1040  */
1041 /*
1042  * Field : flag
1043  *
1044  * [list][*]1 - Cache read supported [*]0 - Cache read not supported[/list]
1045  *
1046  * Field Access Macros:
1047  *
1048  */
1049 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_CACHE_RD_EN_FLAG register field. */
1050 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_LSB 0
1051 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_CACHE_RD_EN_FLAG register field. */
1052 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_MSB 0
1053 /* The width in bits of the ALT_NAND_CFG_CACHE_RD_EN_FLAG register field. */
1054 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_WIDTH 1
1055 /* The mask used to set the ALT_NAND_CFG_CACHE_RD_EN_FLAG register field value. */
1056 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_SET_MSK 0x00000001
1057 /* The mask used to clear the ALT_NAND_CFG_CACHE_RD_EN_FLAG register field value. */
1058 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_CLR_MSK 0xfffffffe
1059 /* The reset value of the ALT_NAND_CFG_CACHE_RD_EN_FLAG register field. */
1060 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_RESET 0x0
1061 /* Extracts the ALT_NAND_CFG_CACHE_RD_EN_FLAG field value from a register. */
1062 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1063 /* Produces a ALT_NAND_CFG_CACHE_RD_EN_FLAG register field value suitable for setting the register. */
1064 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
1065 
1066 #ifndef __ASSEMBLY__
1067 /*
1068  * WARNING: The C register and register group struct declarations are provided for
1069  * convenience and illustrative purposes. They should, however, be used with
1070  * caution as the C language standard provides no guarantees about the alignment or
1071  * atomicity of device memory accesses. The recommended practice for writing
1072  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1073  * alt_write_word() functions.
1074  *
1075  * The struct declaration for register ALT_NAND_CFG_CACHE_RD_EN.
1076  */
1077 struct ALT_NAND_CFG_CACHE_RD_EN_s
1078 {
1079  uint32_t flag : 1; /* ALT_NAND_CFG_CACHE_RD_EN_FLAG */
1080  uint32_t : 31; /* *UNDEFINED* */
1081 };
1082 
1083 /* The typedef declaration for register ALT_NAND_CFG_CACHE_RD_EN. */
1084 typedef volatile struct ALT_NAND_CFG_CACHE_RD_EN_s ALT_NAND_CFG_CACHE_RD_EN_t;
1085 #endif /* __ASSEMBLY__ */
1086 
1087 /* The reset value of the ALT_NAND_CFG_CACHE_RD_EN register. */
1088 #define ALT_NAND_CFG_CACHE_RD_EN_RESET 0x00000000
1089 /* The byte offset of the ALT_NAND_CFG_CACHE_RD_EN register from the beginning of the component. */
1090 #define ALT_NAND_CFG_CACHE_RD_EN_OFST 0xb0
1091 
1092 /*
1093  * Register : prefetch_mode
1094  *
1095  * Enables read data prefetching to faster performance
1096  *
1097  * Register Layout
1098  *
1099  * Bits | Access | Reset | Description
1100  * :--------|:-------|:--------|:---------------------------------------------
1101  * [0] | RW | 0x1 | ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN
1102  * [3:1] | ??? | Unknown | *UNDEFINED*
1103  * [15:4] | RW | 0x0 | ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN
1104  * [31:16] | ??? | Unknown | *UNDEFINED*
1105  *
1106  */
1107 /*
1108  * Field : prefetch_en
1109  *
1110  * Enable prefetch of Data
1111  *
1112  * Field Access Macros:
1113  *
1114  */
1115 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN register field. */
1116 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_LSB 0
1117 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN register field. */
1118 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_MSB 0
1119 /* The width in bits of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN register field. */
1120 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_WIDTH 1
1121 /* The mask used to set the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN register field value. */
1122 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_SET_MSK 0x00000001
1123 /* The mask used to clear the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN register field value. */
1124 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_CLR_MSK 0xfffffffe
1125 /* The reset value of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN register field. */
1126 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_RESET 0x1
1127 /* Extracts the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN field value from a register. */
1128 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_GET(value) (((value) & 0x00000001) >> 0)
1129 /* Produces a ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN register field value suitable for setting the register. */
1130 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_SET(value) (((value) << 0) & 0x00000001)
1131 
1132 /*
1133  * Field : prefetch_burst_length
1134  *
1135  * If prefetch_en is set and prefetch_burst_length is set to ZERO, the controller
1136  * will
1137  *
1138  * start prefetching data only after the receiving the first Map01 read command for
1139  * the page.
1140  *
1141  * If prefetch_en is set and prefetch_burst_length is set to a non-ZERO, valid
1142  * value,
1143  *
1144  * the controller will start prefetching data corresponding to this value even
1145  * before
1146  *
1147  * the first Map01 for the current page has been received.
1148  *
1149  * The value written here should be in bytes.
1150  *
1151  * Field Access Macros:
1152  *
1153  */
1154 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN register field. */
1155 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_LSB 4
1156 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN register field. */
1157 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_MSB 15
1158 /* The width in bits of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN register field. */
1159 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_WIDTH 12
1160 /* The mask used to set the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN register field value. */
1161 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_SET_MSK 0x0000fff0
1162 /* The mask used to clear the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN register field value. */
1163 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_CLR_MSK 0xffff000f
1164 /* The reset value of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN register field. */
1165 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_RESET 0x0
1166 /* Extracts the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN field value from a register. */
1167 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_GET(value) (((value) & 0x0000fff0) >> 4)
1168 /* Produces a ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN register field value suitable for setting the register. */
1169 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_SET(value) (((value) << 4) & 0x0000fff0)
1170 
1171 #ifndef __ASSEMBLY__
1172 /*
1173  * WARNING: The C register and register group struct declarations are provided for
1174  * convenience and illustrative purposes. They should, however, be used with
1175  * caution as the C language standard provides no guarantees about the alignment or
1176  * atomicity of device memory accesses. The recommended practice for writing
1177  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1178  * alt_write_word() functions.
1179  *
1180  * The struct declaration for register ALT_NAND_CFG_PREFETCH_MOD.
1181  */
1182 struct ALT_NAND_CFG_PREFETCH_MOD_s
1183 {
1184  uint32_t prefetch_en : 1; /* ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN */
1185  uint32_t : 3; /* *UNDEFINED* */
1186  uint32_t prefetch_burst_length : 12; /* ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN */
1187  uint32_t : 16; /* *UNDEFINED* */
1188 };
1189 
1190 /* The typedef declaration for register ALT_NAND_CFG_PREFETCH_MOD. */
1191 typedef volatile struct ALT_NAND_CFG_PREFETCH_MOD_s ALT_NAND_CFG_PREFETCH_MOD_t;
1192 #endif /* __ASSEMBLY__ */
1193 
1194 /* The reset value of the ALT_NAND_CFG_PREFETCH_MOD register. */
1195 #define ALT_NAND_CFG_PREFETCH_MOD_RESET 0x00000001
1196 /* The byte offset of the ALT_NAND_CFG_PREFETCH_MOD register from the beginning of the component. */
1197 #define ALT_NAND_CFG_PREFETCH_MOD_OFST 0xc0
1198 
1199 /*
1200  * Register : chip_enable_dont_care
1201  *
1202  * Device can work in the chip enable dont care mode
1203  *
1204  * Register Layout
1205  *
1206  * Bits | Access | Reset | Description
1207  * :-------|:-------|:--------|:------------------------------------
1208  * [0] | RW | 0x0 | ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG
1209  * [31:1] | ??? | Unknown | *UNDEFINED*
1210  *
1211  */
1212 /*
1213  * Field : flag
1214  *
1215  * Controller can interleave commands between banks when this feature is enabled.
1216  *
1217  * [list][*]1 - Device in dont care mode
1218  *
1219  * [*]0 - Device cares for chip enable[/list]
1220  *
1221  * Field Access Macros:
1222  *
1223  */
1224 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG register field. */
1225 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_LSB 0
1226 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG register field. */
1227 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_MSB 0
1228 /* The width in bits of the ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG register field. */
1229 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_WIDTH 1
1230 /* The mask used to set the ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG register field value. */
1231 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_SET_MSK 0x00000001
1232 /* The mask used to clear the ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG register field value. */
1233 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_CLR_MSK 0xfffffffe
1234 /* The reset value of the ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG register field. */
1235 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_RESET 0x0
1236 /* Extracts the ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG field value from a register. */
1237 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1238 /* Produces a ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG register field value suitable for setting the register. */
1239 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_SET(value) (((value) << 0) & 0x00000001)
1240 
1241 #ifndef __ASSEMBLY__
1242 /*
1243  * WARNING: The C register and register group struct declarations are provided for
1244  * convenience and illustrative purposes. They should, however, be used with
1245  * caution as the C language standard provides no guarantees about the alignment or
1246  * atomicity of device memory accesses. The recommended practice for writing
1247  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1248  * alt_write_word() functions.
1249  *
1250  * The struct declaration for register ALT_NAND_CFG_CHIP_EN_DONT_CARE.
1251  */
1252 struct ALT_NAND_CFG_CHIP_EN_DONT_CARE_s
1253 {
1254  uint32_t flag : 1; /* ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG */
1255  uint32_t : 31; /* *UNDEFINED* */
1256 };
1257 
1258 /* The typedef declaration for register ALT_NAND_CFG_CHIP_EN_DONT_CARE. */
1259 typedef volatile struct ALT_NAND_CFG_CHIP_EN_DONT_CARE_s ALT_NAND_CFG_CHIP_EN_DONT_CARE_t;
1260 #endif /* __ASSEMBLY__ */
1261 
1262 /* The reset value of the ALT_NAND_CFG_CHIP_EN_DONT_CARE register. */
1263 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_RESET 0x00000000
1264 /* The byte offset of the ALT_NAND_CFG_CHIP_EN_DONT_CARE register from the beginning of the component. */
1265 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_OFST 0xd0
1266 
1267 /*
1268  * Register : ecc_enable
1269  *
1270  * Enable controller ECC check bit generation and correction
1271  *
1272  * Register Layout
1273  *
1274  * Bits | Access | Reset | Description
1275  * :-------|:-------|:--------|:-------------------------
1276  * [0] | RW | 0x1 | ALT_NAND_CFG_ECC_EN_FLAG
1277  * [31:1] | ??? | Unknown | *UNDEFINED*
1278  *
1279  */
1280 /*
1281  * Field : flag
1282  *
1283  * Enables or disables controller ECC capabilities. When enabled, controller
1284  * calculates
1285  *
1286  * ECC check-bits and writes them onto device on program operation. On page reads,
1287  *
1288  * check-bits are recomputed and errors reported, if any, after comparing with
1289  * stored
1290  *
1291  * check-bits. When disabled, controller does not compute check-bits.
1292  *
1293  * [list][*]1 - ECC Enabled [*]0 - ECC disabled[/list]
1294  *
1295  * Field Access Macros:
1296  *
1297  */
1298 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_ECC_EN_FLAG register field. */
1299 #define ALT_NAND_CFG_ECC_EN_FLAG_LSB 0
1300 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_ECC_EN_FLAG register field. */
1301 #define ALT_NAND_CFG_ECC_EN_FLAG_MSB 0
1302 /* The width in bits of the ALT_NAND_CFG_ECC_EN_FLAG register field. */
1303 #define ALT_NAND_CFG_ECC_EN_FLAG_WIDTH 1
1304 /* The mask used to set the ALT_NAND_CFG_ECC_EN_FLAG register field value. */
1305 #define ALT_NAND_CFG_ECC_EN_FLAG_SET_MSK 0x00000001
1306 /* The mask used to clear the ALT_NAND_CFG_ECC_EN_FLAG register field value. */
1307 #define ALT_NAND_CFG_ECC_EN_FLAG_CLR_MSK 0xfffffffe
1308 /* The reset value of the ALT_NAND_CFG_ECC_EN_FLAG register field. */
1309 #define ALT_NAND_CFG_ECC_EN_FLAG_RESET 0x1
1310 /* Extracts the ALT_NAND_CFG_ECC_EN_FLAG field value from a register. */
1311 #define ALT_NAND_CFG_ECC_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1312 /* Produces a ALT_NAND_CFG_ECC_EN_FLAG register field value suitable for setting the register. */
1313 #define ALT_NAND_CFG_ECC_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
1314 
1315 #ifndef __ASSEMBLY__
1316 /*
1317  * WARNING: The C register and register group struct declarations are provided for
1318  * convenience and illustrative purposes. They should, however, be used with
1319  * caution as the C language standard provides no guarantees about the alignment or
1320  * atomicity of device memory accesses. The recommended practice for writing
1321  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1322  * alt_write_word() functions.
1323  *
1324  * The struct declaration for register ALT_NAND_CFG_ECC_EN.
1325  */
1326 struct ALT_NAND_CFG_ECC_EN_s
1327 {
1328  uint32_t flag : 1; /* ALT_NAND_CFG_ECC_EN_FLAG */
1329  uint32_t : 31; /* *UNDEFINED* */
1330 };
1331 
1332 /* The typedef declaration for register ALT_NAND_CFG_ECC_EN. */
1333 typedef volatile struct ALT_NAND_CFG_ECC_EN_s ALT_NAND_CFG_ECC_EN_t;
1334 #endif /* __ASSEMBLY__ */
1335 
1336 /* The reset value of the ALT_NAND_CFG_ECC_EN register. */
1337 #define ALT_NAND_CFG_ECC_EN_RESET 0x00000001
1338 /* The byte offset of the ALT_NAND_CFG_ECC_EN register from the beginning of the component. */
1339 #define ALT_NAND_CFG_ECC_EN_OFST 0xe0
1340 
1341 /*
1342  * Register : global_int_enable
1343  *
1344  * Global Interrupt enable and Error/Timeout disable.
1345  *
1346  * Register Layout
1347  *
1348  * Bits | Access | Reset | Description
1349  * :-------|:-------|:--------|:---------------------------------------
1350  * [0] | RW | 0x0 | ALT_NAND_CFG_GLOB_INT_EN_FLAG
1351  * [3:1] | ??? | Unknown | *UNDEFINED*
1352  * [4] | RW | 0x0 | ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS
1353  * [7:5] | ??? | Unknown | *UNDEFINED*
1354  * [8] | RW | 0x0 | ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS
1355  * [31:9] | ??? | Unknown | *UNDEFINED*
1356  *
1357  */
1358 /*
1359  * Field : flag
1360  *
1361  * Host will receive an interrupt only when this bit is set.
1362  *
1363  * Field Access Macros:
1364  *
1365  */
1366 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_GLOB_INT_EN_FLAG register field. */
1367 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_LSB 0
1368 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_GLOB_INT_EN_FLAG register field. */
1369 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_MSB 0
1370 /* The width in bits of the ALT_NAND_CFG_GLOB_INT_EN_FLAG register field. */
1371 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_WIDTH 1
1372 /* The mask used to set the ALT_NAND_CFG_GLOB_INT_EN_FLAG register field value. */
1373 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_SET_MSK 0x00000001
1374 /* The mask used to clear the ALT_NAND_CFG_GLOB_INT_EN_FLAG register field value. */
1375 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_CLR_MSK 0xfffffffe
1376 /* The reset value of the ALT_NAND_CFG_GLOB_INT_EN_FLAG register field. */
1377 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_RESET 0x0
1378 /* Extracts the ALT_NAND_CFG_GLOB_INT_EN_FLAG field value from a register. */
1379 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1380 /* Produces a ALT_NAND_CFG_GLOB_INT_EN_FLAG register field value suitable for setting the register. */
1381 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
1382 
1383 /*
1384  * Field : timeout_disable
1385  *
1386  * Watchdog timer logic will be de-activated when
1387  *
1388  * this bit is set.
1389  *
1390  * Field Access Macros:
1391  *
1392  */
1393 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS register field. */
1394 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_LSB 4
1395 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS register field. */
1396 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_MSB 4
1397 /* The width in bits of the ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS register field. */
1398 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_WIDTH 1
1399 /* The mask used to set the ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS register field value. */
1400 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_SET_MSK 0x00000010
1401 /* The mask used to clear the ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS register field value. */
1402 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_CLR_MSK 0xffffffef
1403 /* The reset value of the ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS register field. */
1404 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_RESET 0x0
1405 /* Extracts the ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS field value from a register. */
1406 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_GET(value) (((value) & 0x00000010) >> 4)
1407 /* Produces a ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS register field value suitable for setting the register. */
1408 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_SET(value) (((value) << 4) & 0x00000010)
1409 
1410 /*
1411  * Field : error_rpt_disable
1412  *
1413  * Command and ECC uncorrectable failures will not be
1414  *
1415  * reported when this bit is set
1416  *
1417  * Field Access Macros:
1418  *
1419  */
1420 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS register field. */
1421 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_LSB 8
1422 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS register field. */
1423 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_MSB 8
1424 /* The width in bits of the ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS register field. */
1425 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_WIDTH 1
1426 /* The mask used to set the ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS register field value. */
1427 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_SET_MSK 0x00000100
1428 /* The mask used to clear the ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS register field value. */
1429 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_CLR_MSK 0xfffffeff
1430 /* The reset value of the ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS register field. */
1431 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_RESET 0x0
1432 /* Extracts the ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS field value from a register. */
1433 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_GET(value) (((value) & 0x00000100) >> 8)
1434 /* Produces a ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS register field value suitable for setting the register. */
1435 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_SET(value) (((value) << 8) & 0x00000100)
1436 
1437 #ifndef __ASSEMBLY__
1438 /*
1439  * WARNING: The C register and register group struct declarations are provided for
1440  * convenience and illustrative purposes. They should, however, be used with
1441  * caution as the C language standard provides no guarantees about the alignment or
1442  * atomicity of device memory accesses. The recommended practice for writing
1443  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1444  * alt_write_word() functions.
1445  *
1446  * The struct declaration for register ALT_NAND_CFG_GLOB_INT_EN.
1447  */
1448 struct ALT_NAND_CFG_GLOB_INT_EN_s
1449 {
1450  uint32_t flag : 1; /* ALT_NAND_CFG_GLOB_INT_EN_FLAG */
1451  uint32_t : 3; /* *UNDEFINED* */
1452  uint32_t timeout_disable : 1; /* ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS */
1453  uint32_t : 3; /* *UNDEFINED* */
1454  uint32_t error_rpt_disable : 1; /* ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS */
1455  uint32_t : 23; /* *UNDEFINED* */
1456 };
1457 
1458 /* The typedef declaration for register ALT_NAND_CFG_GLOB_INT_EN. */
1459 typedef volatile struct ALT_NAND_CFG_GLOB_INT_EN_s ALT_NAND_CFG_GLOB_INT_EN_t;
1460 #endif /* __ASSEMBLY__ */
1461 
1462 /* The reset value of the ALT_NAND_CFG_GLOB_INT_EN register. */
1463 #define ALT_NAND_CFG_GLOB_INT_EN_RESET 0x00000000
1464 /* The byte offset of the ALT_NAND_CFG_GLOB_INT_EN register from the beginning of the component. */
1465 #define ALT_NAND_CFG_GLOB_INT_EN_OFST 0xf0
1466 
1467 /*
1468  * Register : twhr2_and_we_2_re
1469  *
1470  * Register Layout
1471  *
1472  * Bits | Access | Reset | Description
1473  * :--------|:-------|:--------|:---------------------------------------
1474  * [5:0] | RW | 0x32 | ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE
1475  * [7:6] | ??? | Unknown | *UNDEFINED*
1476  * [13:8] | RW | 0x14 | ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2
1477  * [31:14] | ??? | Unknown | *UNDEFINED*
1478  *
1479  */
1480 /*
1481  * Field : we_2_re
1482  *
1483  * Signifies the number of bus interface clk_x clocks that should be introduced
1484  * between
1485  *
1486  * write enable going high to read enable going low. The number of clocks is the
1487  *
1488  * function of device parameter Twhr and controller clock frequency.
1489  *
1490  * Field Access Macros:
1491  *
1492  */
1493 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field. */
1494 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_LSB 0
1495 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field. */
1496 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_MSB 5
1497 /* The width in bits of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field. */
1498 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_WIDTH 6
1499 /* The mask used to set the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field value. */
1500 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_SET_MSK 0x0000003f
1501 /* The mask used to clear the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field value. */
1502 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_CLR_MSK 0xffffffc0
1503 /* The reset value of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field. */
1504 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_RESET 0x32
1505 /* Extracts the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE field value from a register. */
1506 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_GET(value) (((value) & 0x0000003f) >> 0)
1507 /* Produces a ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field value suitable for setting the register. */
1508 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_SET(value) (((value) << 0) & 0x0000003f)
1509 
1510 /*
1511  * Field : twhr2
1512  *
1513  * Signifies the number of controller clocks that should be introduced between
1514  *
1515  * the last command of a random data output command to the start of the data
1516  * transfer.
1517  *
1518  * Field Access Macros:
1519  *
1520  */
1521 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field. */
1522 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_LSB 8
1523 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field. */
1524 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_MSB 13
1525 /* The width in bits of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field. */
1526 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_WIDTH 6
1527 /* The mask used to set the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field value. */
1528 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_SET_MSK 0x00003f00
1529 /* The mask used to clear the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field value. */
1530 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_CLR_MSK 0xffffc0ff
1531 /* The reset value of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field. */
1532 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_RESET 0x14
1533 /* Extracts the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 field value from a register. */
1534 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_GET(value) (((value) & 0x00003f00) >> 8)
1535 /* Produces a ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field value suitable for setting the register. */
1536 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_SET(value) (((value) << 8) & 0x00003f00)
1537 
1538 #ifndef __ASSEMBLY__
1539 /*
1540  * WARNING: The C register and register group struct declarations are provided for
1541  * convenience and illustrative purposes. They should, however, be used with
1542  * caution as the C language standard provides no guarantees about the alignment or
1543  * atomicity of device memory accesses. The recommended practice for writing
1544  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1545  * alt_write_word() functions.
1546  *
1547  * The struct declaration for register ALT_NAND_CFG_TWHR2_AND_WE_2_RE.
1548  */
1549 struct ALT_NAND_CFG_TWHR2_AND_WE_2_RE_s
1550 {
1551  uint32_t we_2_re : 6; /* ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE */
1552  uint32_t : 2; /* *UNDEFINED* */
1553  uint32_t twhr2 : 6; /* ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 */
1554  uint32_t : 18; /* *UNDEFINED* */
1555 };
1556 
1557 /* The typedef declaration for register ALT_NAND_CFG_TWHR2_AND_WE_2_RE. */
1558 typedef volatile struct ALT_NAND_CFG_TWHR2_AND_WE_2_RE_s ALT_NAND_CFG_TWHR2_AND_WE_2_RE_t;
1559 #endif /* __ASSEMBLY__ */
1560 
1561 /* The reset value of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE register. */
1562 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_RESET 0x00001432
1563 /* The byte offset of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE register from the beginning of the component. */
1564 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_OFST 0x100
1565 
1566 /*
1567  * Register : tcwaw_and_addr_2_data
1568  *
1569  * Register Layout
1570  *
1571  * Bits | Access | Reset | Description
1572  * :--------|:-------|:--------|:-----------------------------------------------
1573  * [6:0] | RW | 0x32 | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA
1574  * [7] | ??? | Unknown | *UNDEFINED*
1575  * [13:8] | RW | 0x14 | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW
1576  * [31:14] | ??? | Unknown | *UNDEFINED*
1577  *
1578  */
1579 /*
1580  * Field : addr_2_data
1581  *
1582  * Signifies the number of bus interface clk_x clocks that should be introduced
1583  *
1584  * between an address to a data input cycle. The number of clocks is the function
1585  * of device
1586  *
1587  * parameter Tadl and controller clock frequency.
1588  *
1589  * Field Access Macros:
1590  *
1591  */
1592 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field. */
1593 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_LSB 0
1594 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field. */
1595 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_MSB 6
1596 /* The width in bits of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field. */
1597 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_WIDTH 7
1598 /* The mask used to set the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field value. */
1599 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_SET_MSK 0x0000007f
1600 /* The mask used to clear the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field value. */
1601 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_CLR_MSK 0xffffff80
1602 /* The reset value of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field. */
1603 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_RESET 0x32
1604 /* Extracts the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA field value from a register. */
1605 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_GET(value) (((value) & 0x0000007f) >> 0)
1606 /* Produces a ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field value suitable for setting the register. */
1607 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_SET(value) (((value) << 0) & 0x0000007f)
1608 
1609 /*
1610  * Field : tcwaw
1611  *
1612  * Signifies the number of controller clocks that should be introduced between
1613  *
1614  * the command cycle of a random data input command to the address cycle of the
1615  * random
1616  *
1617  * data input command.
1618  *
1619  * Field Access Macros:
1620  *
1621  */
1622 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field. */
1623 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_LSB 8
1624 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field. */
1625 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_MSB 13
1626 /* The width in bits of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field. */
1627 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_WIDTH 6
1628 /* The mask used to set the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field value. */
1629 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_SET_MSK 0x00003f00
1630 /* The mask used to clear the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field value. */
1631 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_CLR_MSK 0xffffc0ff
1632 /* The reset value of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field. */
1633 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_RESET 0x14
1634 /* Extracts the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW field value from a register. */
1635 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_GET(value) (((value) & 0x00003f00) >> 8)
1636 /* Produces a ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field value suitable for setting the register. */
1637 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_SET(value) (((value) << 8) & 0x00003f00)
1638 
1639 #ifndef __ASSEMBLY__
1640 /*
1641  * WARNING: The C register and register group struct declarations are provided for
1642  * convenience and illustrative purposes. They should, however, be used with
1643  * caution as the C language standard provides no guarantees about the alignment or
1644  * atomicity of device memory accesses. The recommended practice for writing
1645  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1646  * alt_write_word() functions.
1647  *
1648  * The struct declaration for register ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA.
1649  */
1650 struct ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_s
1651 {
1652  uint32_t addr_2_data : 7; /* ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA */
1653  uint32_t : 1; /* *UNDEFINED* */
1654  uint32_t tcwaw : 6; /* ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW */
1655  uint32_t : 18; /* *UNDEFINED* */
1656 };
1657 
1658 /* The typedef declaration for register ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA. */
1659 typedef volatile struct ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_s ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_t;
1660 #endif /* __ASSEMBLY__ */
1661 
1662 /* The reset value of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA register. */
1663 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_RESET 0x00001432
1664 /* The byte offset of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA register from the beginning of the component. */
1665 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_OFST 0x110
1666 
1667 /*
1668  * Register : re_2_we
1669  *
1670  * Timing parameter between re high to we low (Trhw)
1671  *
1672  * Register Layout
1673  *
1674  * Bits | Access | Reset | Description
1675  * :-------|:-------|:--------|:---------------------------
1676  * [5:0] | RW | 0x32 | ALT_NAND_CFG_RE_2_WE_VALUE
1677  * [31:6] | ??? | Unknown | *UNDEFINED*
1678  *
1679  */
1680 /*
1681  * Field : value
1682  *
1683  * Signifies the number of bus interface clk_x clocks that should be introduced
1684  * between
1685  *
1686  * read enable going high to write enable going low. The number of clocks is the
1687  *
1688  * function of device parameter Trhw and controller clock frequency.
1689  *
1690  * Field Access Macros:
1691  *
1692  */
1693 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RE_2_WE_VALUE register field. */
1694 #define ALT_NAND_CFG_RE_2_WE_VALUE_LSB 0
1695 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RE_2_WE_VALUE register field. */
1696 #define ALT_NAND_CFG_RE_2_WE_VALUE_MSB 5
1697 /* The width in bits of the ALT_NAND_CFG_RE_2_WE_VALUE register field. */
1698 #define ALT_NAND_CFG_RE_2_WE_VALUE_WIDTH 6
1699 /* The mask used to set the ALT_NAND_CFG_RE_2_WE_VALUE register field value. */
1700 #define ALT_NAND_CFG_RE_2_WE_VALUE_SET_MSK 0x0000003f
1701 /* The mask used to clear the ALT_NAND_CFG_RE_2_WE_VALUE register field value. */
1702 #define ALT_NAND_CFG_RE_2_WE_VALUE_CLR_MSK 0xffffffc0
1703 /* The reset value of the ALT_NAND_CFG_RE_2_WE_VALUE register field. */
1704 #define ALT_NAND_CFG_RE_2_WE_VALUE_RESET 0x32
1705 /* Extracts the ALT_NAND_CFG_RE_2_WE_VALUE field value from a register. */
1706 #define ALT_NAND_CFG_RE_2_WE_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
1707 /* Produces a ALT_NAND_CFG_RE_2_WE_VALUE register field value suitable for setting the register. */
1708 #define ALT_NAND_CFG_RE_2_WE_VALUE_SET(value) (((value) << 0) & 0x0000003f)
1709 
1710 #ifndef __ASSEMBLY__
1711 /*
1712  * WARNING: The C register and register group struct declarations are provided for
1713  * convenience and illustrative purposes. They should, however, be used with
1714  * caution as the C language standard provides no guarantees about the alignment or
1715  * atomicity of device memory accesses. The recommended practice for writing
1716  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1717  * alt_write_word() functions.
1718  *
1719  * The struct declaration for register ALT_NAND_CFG_RE_2_WE.
1720  */
1721 struct ALT_NAND_CFG_RE_2_WE_s
1722 {
1723  uint32_t value : 6; /* ALT_NAND_CFG_RE_2_WE_VALUE */
1724  uint32_t : 26; /* *UNDEFINED* */
1725 };
1726 
1727 /* The typedef declaration for register ALT_NAND_CFG_RE_2_WE. */
1728 typedef volatile struct ALT_NAND_CFG_RE_2_WE_s ALT_NAND_CFG_RE_2_WE_t;
1729 #endif /* __ASSEMBLY__ */
1730 
1731 /* The reset value of the ALT_NAND_CFG_RE_2_WE register. */
1732 #define ALT_NAND_CFG_RE_2_WE_RESET 0x00000032
1733 /* The byte offset of the ALT_NAND_CFG_RE_2_WE register from the beginning of the component. */
1734 #define ALT_NAND_CFG_RE_2_WE_OFST 0x120
1735 
1736 /*
1737  * Register : acc_clks
1738  *
1739  * Timing parameter from read enable going low to capture read data
1740  *
1741  * Register Layout
1742  *
1743  * Bits | Access | Reset | Description
1744  * :-------|:-------|:--------|:----------------------------
1745  * [3:0] | RW | 0x0 | ALT_NAND_CFG_ACC_CLKS_VALUE
1746  * [31:4] | ??? | Unknown | *UNDEFINED*
1747  *
1748  */
1749 /*
1750  * Field : value
1751  *
1752  * Signifies the number of bus interface clk_x clock cycles, controller
1753  *
1754  * should wait from read enable going low to sending out a strobe of clk_x for
1755  *
1756  * capturing of incoming data.
1757  *
1758  * Field Access Macros:
1759  *
1760  */
1761 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_ACC_CLKS_VALUE register field. */
1762 #define ALT_NAND_CFG_ACC_CLKS_VALUE_LSB 0
1763 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_ACC_CLKS_VALUE register field. */
1764 #define ALT_NAND_CFG_ACC_CLKS_VALUE_MSB 3
1765 /* The width in bits of the ALT_NAND_CFG_ACC_CLKS_VALUE register field. */
1766 #define ALT_NAND_CFG_ACC_CLKS_VALUE_WIDTH 4
1767 /* The mask used to set the ALT_NAND_CFG_ACC_CLKS_VALUE register field value. */
1768 #define ALT_NAND_CFG_ACC_CLKS_VALUE_SET_MSK 0x0000000f
1769 /* The mask used to clear the ALT_NAND_CFG_ACC_CLKS_VALUE register field value. */
1770 #define ALT_NAND_CFG_ACC_CLKS_VALUE_CLR_MSK 0xfffffff0
1771 /* The reset value of the ALT_NAND_CFG_ACC_CLKS_VALUE register field. */
1772 #define ALT_NAND_CFG_ACC_CLKS_VALUE_RESET 0x0
1773 /* Extracts the ALT_NAND_CFG_ACC_CLKS_VALUE field value from a register. */
1774 #define ALT_NAND_CFG_ACC_CLKS_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
1775 /* Produces a ALT_NAND_CFG_ACC_CLKS_VALUE register field value suitable for setting the register. */
1776 #define ALT_NAND_CFG_ACC_CLKS_VALUE_SET(value) (((value) << 0) & 0x0000000f)
1777 
1778 #ifndef __ASSEMBLY__
1779 /*
1780  * WARNING: The C register and register group struct declarations are provided for
1781  * convenience and illustrative purposes. They should, however, be used with
1782  * caution as the C language standard provides no guarantees about the alignment or
1783  * atomicity of device memory accesses. The recommended practice for writing
1784  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1785  * alt_write_word() functions.
1786  *
1787  * The struct declaration for register ALT_NAND_CFG_ACC_CLKS.
1788  */
1789 struct ALT_NAND_CFG_ACC_CLKS_s
1790 {
1791  uint32_t value : 4; /* ALT_NAND_CFG_ACC_CLKS_VALUE */
1792  uint32_t : 28; /* *UNDEFINED* */
1793 };
1794 
1795 /* The typedef declaration for register ALT_NAND_CFG_ACC_CLKS. */
1796 typedef volatile struct ALT_NAND_CFG_ACC_CLKS_s ALT_NAND_CFG_ACC_CLKS_t;
1797 #endif /* __ASSEMBLY__ */
1798 
1799 /* The reset value of the ALT_NAND_CFG_ACC_CLKS register. */
1800 #define ALT_NAND_CFG_ACC_CLKS_RESET 0x00000000
1801 /* The byte offset of the ALT_NAND_CFG_ACC_CLKS register from the beginning of the component. */
1802 #define ALT_NAND_CFG_ACC_CLKS_OFST 0x130
1803 
1804 /*
1805  * Register : number_of_planes
1806  *
1807  * Number of planes in the device
1808  *
1809  * Register Layout
1810  *
1811  * Bits | Access | Reset | Description
1812  * :-------|:-------|:--------|:------------------------------------
1813  * [2:0] | RW | 0x0 | ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE
1814  * [31:3] | ??? | Unknown | *UNDEFINED*
1815  *
1816  */
1817 /*
1818  * Field : value
1819  *
1820  * Controller will read Electronic Signature of devices and populate
1821  *
1822  * this field as the number of planes information is present in the signature.
1823  *
1824  * For 512B device, this information needs to be programmed by software.
1825  *
1826  * Software could also choose to override the populated value.
1827  *
1828  * The values in the fields should be as follows[list]
1829  *
1830  * [*]3'h0 - Monoplane device
1831  *
1832  * [*]3'h1 - Two plane device
1833  *
1834  * [*]3'h3 - 4 plane device
1835  *
1836  * [*]3'h7 - 8 plane device
1837  *
1838  * [*]All other values - Reserved[/list]
1839  *
1840  * Field Access Macros:
1841  *
1842  */
1843 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field. */
1844 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_LSB 0
1845 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field. */
1846 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_MSB 2
1847 /* The width in bits of the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field. */
1848 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_WIDTH 3
1849 /* The mask used to set the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field value. */
1850 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_SET_MSK 0x00000007
1851 /* The mask used to clear the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field value. */
1852 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_CLR_MSK 0xfffffff8
1853 /* The reset value of the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field. */
1854 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_RESET 0x0
1855 /* Extracts the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE field value from a register. */
1856 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_GET(value) (((value) & 0x00000007) >> 0)
1857 /* Produces a ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field value suitable for setting the register. */
1858 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_SET(value) (((value) << 0) & 0x00000007)
1859 
1860 #ifndef __ASSEMBLY__
1861 /*
1862  * WARNING: The C register and register group struct declarations are provided for
1863  * convenience and illustrative purposes. They should, however, be used with
1864  * caution as the C language standard provides no guarantees about the alignment or
1865  * atomicity of device memory accesses. The recommended practice for writing
1866  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1867  * alt_write_word() functions.
1868  *
1869  * The struct declaration for register ALT_NAND_CFG_NUMBER_OF_PLANES.
1870  */
1871 struct ALT_NAND_CFG_NUMBER_OF_PLANES_s
1872 {
1873  uint32_t value : 3; /* ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE */
1874  uint32_t : 29; /* *UNDEFINED* */
1875 };
1876 
1877 /* The typedef declaration for register ALT_NAND_CFG_NUMBER_OF_PLANES. */
1878 typedef volatile struct ALT_NAND_CFG_NUMBER_OF_PLANES_s ALT_NAND_CFG_NUMBER_OF_PLANES_t;
1879 #endif /* __ASSEMBLY__ */
1880 
1881 /* The reset value of the ALT_NAND_CFG_NUMBER_OF_PLANES register. */
1882 #define ALT_NAND_CFG_NUMBER_OF_PLANES_RESET 0x00000000
1883 /* The byte offset of the ALT_NAND_CFG_NUMBER_OF_PLANES register from the beginning of the component. */
1884 #define ALT_NAND_CFG_NUMBER_OF_PLANES_OFST 0x140
1885 
1886 /*
1887  * Register : pages_per_block
1888  *
1889  * Number of pages in a block
1890  *
1891  * Register Layout
1892  *
1893  * Bits | Access | Reset | Description
1894  * :--------|:-------|:--------|:-----------------------------------
1895  * [15:0] | RW | 0x0 | ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE
1896  * [31:16] | ??? | Unknown | *UNDEFINED*
1897  *
1898  */
1899 /*
1900  * Field : value
1901  *
1902  * Controller will read Electronic Signature of devices and populate
1903  *
1904  * this field. For 512B devices, bootstrap_512B_device will determine the value of
1905  *
1906  * this field to be of 32. Software could also choose to override the populated
1907  *
1908  * value.
1909  *
1910  * Field Access Macros:
1911  *
1912  */
1913 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field. */
1914 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_LSB 0
1915 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field. */
1916 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_MSB 15
1917 /* The width in bits of the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field. */
1918 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_WIDTH 16
1919 /* The mask used to set the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field value. */
1920 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_SET_MSK 0x0000ffff
1921 /* The mask used to clear the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field value. */
1922 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_CLR_MSK 0xffff0000
1923 /* The reset value of the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field. */
1924 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_RESET 0x0
1925 /* Extracts the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE field value from a register. */
1926 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
1927 /* Produces a ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field value suitable for setting the register. */
1928 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
1929 
1930 #ifndef __ASSEMBLY__
1931 /*
1932  * WARNING: The C register and register group struct declarations are provided for
1933  * convenience and illustrative purposes. They should, however, be used with
1934  * caution as the C language standard provides no guarantees about the alignment or
1935  * atomicity of device memory accesses. The recommended practice for writing
1936  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1937  * alt_write_word() functions.
1938  *
1939  * The struct declaration for register ALT_NAND_CFG_PAGES_PER_BLOCK.
1940  */
1941 struct ALT_NAND_CFG_PAGES_PER_BLOCK_s
1942 {
1943  uint32_t value : 16; /* ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE */
1944  uint32_t : 16; /* *UNDEFINED* */
1945 };
1946 
1947 /* The typedef declaration for register ALT_NAND_CFG_PAGES_PER_BLOCK. */
1948 typedef volatile struct ALT_NAND_CFG_PAGES_PER_BLOCK_s ALT_NAND_CFG_PAGES_PER_BLOCK_t;
1949 #endif /* __ASSEMBLY__ */
1950 
1951 /* The reset value of the ALT_NAND_CFG_PAGES_PER_BLOCK register. */
1952 #define ALT_NAND_CFG_PAGES_PER_BLOCK_RESET 0x00000000
1953 /* The byte offset of the ALT_NAND_CFG_PAGES_PER_BLOCK register from the beginning of the component. */
1954 #define ALT_NAND_CFG_PAGES_PER_BLOCK_OFST 0x150
1955 
1956 /*
1957  * Register : device_width
1958  *
1959  * I/O width of attached devices
1960  *
1961  * Register Layout
1962  *
1963  * Bits | Access | Reset | Description
1964  * :-------|:-------|:--------|:--------------------------------
1965  * [1:0] | RW | 0x3 | ALT_NAND_CFG_DEVICE_WIDTH_VALUE
1966  * [31:2] | ??? | Unknown | *UNDEFINED*
1967  *
1968  */
1969 /*
1970  * Field : value
1971  *
1972  * Controller will read Electronic Signature of devices and populate
1973  *
1974  * this field. For 512B devices, bootstrap_x16_device will determine the value of
1975  *
1976  * this field. Software could also choose to override the populated value.
1977  *
1978  * The values in this field should be as follows[list][*]2'h00 - 8bit device[*]
1979  *
1980  * 2'h01 - 16bit device[*]All other values - Reserved[/list]
1981  *
1982  * Field Access Macros:
1983  *
1984  */
1985 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field. */
1986 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_LSB 0
1987 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field. */
1988 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_MSB 1
1989 /* The width in bits of the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field. */
1990 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_WIDTH 2
1991 /* The mask used to set the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field value. */
1992 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_SET_MSK 0x00000003
1993 /* The mask used to clear the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field value. */
1994 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_CLR_MSK 0xfffffffc
1995 /* The reset value of the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field. */
1996 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_RESET 0x3
1997 /* Extracts the ALT_NAND_CFG_DEVICE_WIDTH_VALUE field value from a register. */
1998 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_GET(value) (((value) & 0x00000003) >> 0)
1999 /* Produces a ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field value suitable for setting the register. */
2000 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_SET(value) (((value) << 0) & 0x00000003)
2001 
2002 #ifndef __ASSEMBLY__
2003 /*
2004  * WARNING: The C register and register group struct declarations are provided for
2005  * convenience and illustrative purposes. They should, however, be used with
2006  * caution as the C language standard provides no guarantees about the alignment or
2007  * atomicity of device memory accesses. The recommended practice for writing
2008  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2009  * alt_write_word() functions.
2010  *
2011  * The struct declaration for register ALT_NAND_CFG_DEVICE_WIDTH.
2012  */
2013 struct ALT_NAND_CFG_DEVICE_WIDTH_s
2014 {
2015  uint32_t value : 2; /* ALT_NAND_CFG_DEVICE_WIDTH_VALUE */
2016  uint32_t : 30; /* *UNDEFINED* */
2017 };
2018 
2019 /* The typedef declaration for register ALT_NAND_CFG_DEVICE_WIDTH. */
2020 typedef volatile struct ALT_NAND_CFG_DEVICE_WIDTH_s ALT_NAND_CFG_DEVICE_WIDTH_t;
2021 #endif /* __ASSEMBLY__ */
2022 
2023 /* The reset value of the ALT_NAND_CFG_DEVICE_WIDTH register. */
2024 #define ALT_NAND_CFG_DEVICE_WIDTH_RESET 0x00000003
2025 /* The byte offset of the ALT_NAND_CFG_DEVICE_WIDTH register from the beginning of the component. */
2026 #define ALT_NAND_CFG_DEVICE_WIDTH_OFST 0x160
2027 
2028 /*
2029  * Register : device_main_area_size
2030  *
2031  * Page main area size of device in bytes
2032  *
2033  * Register Layout
2034  *
2035  * Bits | Access | Reset | Description
2036  * :--------|:-------|:--------|:-----------------------------------------
2037  * [15:0] | RW | 0x0 | ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE
2038  * [31:16] | ??? | Unknown | *UNDEFINED*
2039  *
2040  */
2041 /*
2042  * Field : value
2043  *
2044  * Controller will read Electronic Signature of devices and populate
2045  *
2046  * this field. For 512B devices, bootstrap_512B_device will determine the value
2047  *
2048  * of this field to be 512. Software could also choose to override the populated
2049  *
2050  * value.
2051  *
2052  * Field Access Macros:
2053  *
2054  */
2055 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field. */
2056 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_LSB 0
2057 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field. */
2058 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_MSB 15
2059 /* The width in bits of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field. */
2060 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_WIDTH 16
2061 /* The mask used to set the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field value. */
2062 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_SET_MSK 0x0000ffff
2063 /* The mask used to clear the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field value. */
2064 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_CLR_MSK 0xffff0000
2065 /* The reset value of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field. */
2066 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_RESET 0x0
2067 /* Extracts the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE field value from a register. */
2068 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
2069 /* Produces a ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field value suitable for setting the register. */
2070 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
2071 
2072 #ifndef __ASSEMBLY__
2073 /*
2074  * WARNING: The C register and register group struct declarations are provided for
2075  * convenience and illustrative purposes. They should, however, be used with
2076  * caution as the C language standard provides no guarantees about the alignment or
2077  * atomicity of device memory accesses. The recommended practice for writing
2078  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2079  * alt_write_word() functions.
2080  *
2081  * The struct declaration for register ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE.
2082  */
2083 struct ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_s
2084 {
2085  uint32_t value : 16; /* ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE */
2086  uint32_t : 16; /* *UNDEFINED* */
2087 };
2088 
2089 /* The typedef declaration for register ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE. */
2090 typedef volatile struct ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_s ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_t;
2091 #endif /* __ASSEMBLY__ */
2092 
2093 /* The reset value of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE register. */
2094 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_RESET 0x00000000
2095 /* The byte offset of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE register from the beginning of the component. */
2096 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_OFST 0x170
2097 
2098 /*
2099  * Register : device_spare_area_size
2100  *
2101  * Page spare area size of device in bytes
2102  *
2103  * Register Layout
2104  *
2105  * Bits | Access | Reset | Description
2106  * :--------|:-------|:--------|:------------------------------------------
2107  * [15:0] | RW | 0x0 | ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE
2108  * [31:16] | ??? | Unknown | *UNDEFINED*
2109  *
2110  */
2111 /*
2112  * Field : value
2113  *
2114  * Controller will read Electronic Signature of devices and populate
2115  *
2116  * this field. For 512B devices, bootstrap_512B_device will determine the value
2117  *
2118  * of this field to be 16. Software could also choose to override the populated
2119  *
2120  * value.
2121  *
2122  * Field Access Macros:
2123  *
2124  */
2125 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field. */
2126 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_LSB 0
2127 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field. */
2128 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_MSB 15
2129 /* The width in bits of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field. */
2130 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_WIDTH 16
2131 /* The mask used to set the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field value. */
2132 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_SET_MSK 0x0000ffff
2133 /* The mask used to clear the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field value. */
2134 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_CLR_MSK 0xffff0000
2135 /* The reset value of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field. */
2136 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_RESET 0x0
2137 /* Extracts the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE field value from a register. */
2138 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
2139 /* Produces a ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field value suitable for setting the register. */
2140 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
2141 
2142 #ifndef __ASSEMBLY__
2143 /*
2144  * WARNING: The C register and register group struct declarations are provided for
2145  * convenience and illustrative purposes. They should, however, be used with
2146  * caution as the C language standard provides no guarantees about the alignment or
2147  * atomicity of device memory accesses. The recommended practice for writing
2148  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2149  * alt_write_word() functions.
2150  *
2151  * The struct declaration for register ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE.
2152  */
2153 struct ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_s
2154 {
2155  uint32_t value : 16; /* ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE */
2156  uint32_t : 16; /* *UNDEFINED* */
2157 };
2158 
2159 /* The typedef declaration for register ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE. */
2160 typedef volatile struct ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_s ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_t;
2161 #endif /* __ASSEMBLY__ */
2162 
2163 /* The reset value of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE register. */
2164 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_RESET 0x00000000
2165 /* The byte offset of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE register from the beginning of the component. */
2166 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_OFST 0x180
2167 
2168 /*
2169  * Register : two_row_addr_cycles
2170  *
2171  * Attached device has only 2 ROW address cycles
2172  *
2173  * Register Layout
2174  *
2175  * Bits | Access | Reset | Description
2176  * :-------|:-------|:--------|:--------------------------------------
2177  * [0] | RW | 0x0 | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG
2178  * [3:1] | ??? | Unknown | *UNDEFINED*
2179  * [4] | RW | 0x0 | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR
2180  * [31:5] | ??? | Unknown | *UNDEFINED*
2181  *
2182  */
2183 /*
2184  * Field : flag
2185  *
2186  * This flag must be set for devices which allow for 2 ROW address cycles instead
2187  *
2188  * of the usual 3. Alternatively, bootstrap_two_row_addr_cycles when asserted will
2189  *
2190  * set this flag.
2191  *
2192  * Field Access Macros:
2193  *
2194  */
2195 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field. */
2196 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_LSB 0
2197 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field. */
2198 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_MSB 0
2199 /* The width in bits of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field. */
2200 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_WIDTH 1
2201 /* The mask used to set the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field value. */
2202 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_SET_MSK 0x00000001
2203 /* The mask used to clear the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field value. */
2204 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_CLR_MSK 0xfffffffe
2205 /* The reset value of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field. */
2206 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_RESET 0x0
2207 /* Extracts the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG field value from a register. */
2208 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_GET(value) (((value) & 0x00000001) >> 0)
2209 /* Produces a ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field value suitable for setting the register. */
2210 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_SET(value) (((value) << 0) & 0x00000001)
2211 
2212 /*
2213  * Field : four
2214  *
2215  * This flag must be set for devices which allow for 4 ROW address cycles instead
2216  *
2217  * of the usual 3.
2218  *
2219  * Field Access Macros:
2220  *
2221  */
2222 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR register field. */
2223 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_LSB 4
2224 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR register field. */
2225 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_MSB 4
2226 /* The width in bits of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR register field. */
2227 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_WIDTH 1
2228 /* The mask used to set the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR register field value. */
2229 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_SET_MSK 0x00000010
2230 /* The mask used to clear the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR register field value. */
2231 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_CLR_MSK 0xffffffef
2232 /* The reset value of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR register field. */
2233 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_RESET 0x0
2234 /* Extracts the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR field value from a register. */
2235 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_GET(value) (((value) & 0x00000010) >> 4)
2236 /* Produces a ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR register field value suitable for setting the register. */
2237 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_SET(value) (((value) << 4) & 0x00000010)
2238 
2239 #ifndef __ASSEMBLY__
2240 /*
2241  * WARNING: The C register and register group struct declarations are provided for
2242  * convenience and illustrative purposes. They should, however, be used with
2243  * caution as the C language standard provides no guarantees about the alignment or
2244  * atomicity of device memory accesses. The recommended practice for writing
2245  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2246  * alt_write_word() functions.
2247  *
2248  * The struct declaration for register ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES.
2249  */
2250 struct ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_s
2251 {
2252  uint32_t flag : 1; /* ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG */
2253  uint32_t : 3; /* *UNDEFINED* */
2254  uint32_t four : 1; /* ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR */
2255  uint32_t : 27; /* *UNDEFINED* */
2256 };
2257 
2258 /* The typedef declaration for register ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES. */
2259 typedef volatile struct ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_s ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_t;
2260 #endif /* __ASSEMBLY__ */
2261 
2262 /* The reset value of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES register. */
2263 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_RESET 0x00000000
2264 /* The byte offset of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES register from the beginning of the component. */
2265 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_OFST 0x190
2266 
2267 /*
2268  * Register : multiplane_addr_restrict
2269  *
2270  * Address restriction for multiplane commands
2271  *
2272  * Register Layout
2273  *
2274  * Bits | Access | Reset | Description
2275  * :-------|:-------|:--------|:-------------------------------------------
2276  * [0] | RW | 0x0 | ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG
2277  * [31:1] | ??? | Unknown | *UNDEFINED*
2278  *
2279  */
2280 /*
2281  * Field : flag
2282  *
2283  * This flag must be set for devices which require that during multiplane
2284  *
2285  * operations all but the address for the last plane should have their address
2286  *
2287  * cycles tied low. The last plane address cycles has proper values. This
2288  *
2289  * ensures multiplane address restrictions in the device.
2290  *
2291  * Field Access Macros:
2292  *
2293  */
2294 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field. */
2295 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_LSB 0
2296 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field. */
2297 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_MSB 0
2298 /* The width in bits of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field. */
2299 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_WIDTH 1
2300 /* The mask used to set the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field value. */
2301 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_SET_MSK 0x00000001
2302 /* The mask used to clear the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field value. */
2303 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_CLR_MSK 0xfffffffe
2304 /* The reset value of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field. */
2305 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_RESET 0x0
2306 /* Extracts the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG field value from a register. */
2307 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_GET(value) (((value) & 0x00000001) >> 0)
2308 /* Produces a ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field value suitable for setting the register. */
2309 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_SET(value) (((value) << 0) & 0x00000001)
2310 
2311 #ifndef __ASSEMBLY__
2312 /*
2313  * WARNING: The C register and register group struct declarations are provided for
2314  * convenience and illustrative purposes. They should, however, be used with
2315  * caution as the C language standard provides no guarantees about the alignment or
2316  * atomicity of device memory accesses. The recommended practice for writing
2317  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2318  * alt_write_word() functions.
2319  *
2320  * The struct declaration for register ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT.
2321  */
2322 struct ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_s
2323 {
2324  uint32_t flag : 1; /* ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG */
2325  uint32_t : 31; /* *UNDEFINED* */
2326 };
2327 
2328 /* The typedef declaration for register ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT. */
2329 typedef volatile struct ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_s ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_t;
2330 #endif /* __ASSEMBLY__ */
2331 
2332 /* The reset value of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT register. */
2333 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_RESET 0x00000000
2334 /* The byte offset of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT register from the beginning of the component. */
2335 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_OFST 0x1a0
2336 
2337 /*
2338  * Register : ecc_correction
2339  *
2340  * Correction capability required and the Erase threshold value.
2341  *
2342  * Register Layout
2343  *
2344  * Bits | Access | Reset | Description
2345  * :--------|:-------|:--------|:--------------------------------------------
2346  * [7:0] | RW | 0x8 | ALT_NAND_CFG_ECC_CORRECTION_VALUE
2347  * [15:8] | ??? | Unknown | *UNDEFINED*
2348  * [31:16] | RW | 0x0 | ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD
2349  *
2350  */
2351 /*
2352  * Field : value
2353  *
2354  * The required correction capability. A smaller correction capability will
2355  *
2356  * lead to lesser number of ECC check-bits being written per ECC sector.
2357  *
2358  * The supported ECC correction levels are -
2359  *
2360  * [list]
2361  *
2362  * [*] 16,8,4 over 512 bytes.
2363  *
2364  * [*] 24 over 1024 bytes.
2365  *
2366  * [*] All other values will cause the correction value in the controller
2367  *
2368  * to fall back to the previously selected value.
2369  *
2370  * [/list]
2371  *
2372  * Field Access Macros:
2373  *
2374  */
2375 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field. */
2376 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_LSB 0
2377 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field. */
2378 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_MSB 7
2379 /* The width in bits of the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field. */
2380 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_WIDTH 8
2381 /* The mask used to set the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field value. */
2382 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_SET_MSK 0x000000ff
2383 /* The mask used to clear the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field value. */
2384 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_CLR_MSK 0xffffff00
2385 /* The reset value of the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field. */
2386 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_RESET 0x8
2387 /* Extracts the ALT_NAND_CFG_ECC_CORRECTION_VALUE field value from a register. */
2388 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
2389 /* Produces a ALT_NAND_CFG_ECC_CORRECTION_VALUE register field value suitable for setting the register. */
2390 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_SET(value) (((value) << 0) & 0x000000ff)
2391 
2392 /*
2393  * Field : erase_threshold
2394  *
2395  * This value informs the ECC logic of the number of 0's to count
2396  *
2397  * in a page before considering it as Erased. If the number of 0's in
2398  *
2399  * the page being read is less than the value in this register,
2400  *
2401  * an erased page is inferred and no un-correctable error will be flagged
2402  *
2403  * for that page. If ECC is disabled, the erased_page interrupt shall be
2404  *
2405  * set as explained above. If ECC is enabled, in addition to the above
2406  *
2407  * condition, only when the ECC logic detects an un-correctable error for
2408  *
2409  * that page will the erased_page interrupt be flagged. If the ECC logic
2410  *
2411  * detects a no-error or correctable error page, this erased page interrupt
2412  *
2413  * will not be set. A value of ZERO in this register will disabled checking for
2414  *
2415  * erased pages. Erased page detection logic will be activated only in MAIN or
2416  *
2417  * MAIN+SPARE or META-DATA(if available) modes of operation.
2418  *
2419  * Field Access Macros:
2420  *
2421  */
2422 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD register field. */
2423 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_LSB 16
2424 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD register field. */
2425 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_MSB 31
2426 /* The width in bits of the ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD register field. */
2427 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_WIDTH 16
2428 /* The mask used to set the ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD register field value. */
2429 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_SET_MSK 0xffff0000
2430 /* The mask used to clear the ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD register field value. */
2431 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_CLR_MSK 0x0000ffff
2432 /* The reset value of the ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD register field. */
2433 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_RESET 0x0
2434 /* Extracts the ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD field value from a register. */
2435 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_GET(value) (((value) & 0xffff0000) >> 16)
2436 /* Produces a ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD register field value suitable for setting the register. */
2437 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_SET(value) (((value) << 16) & 0xffff0000)
2438 
2439 #ifndef __ASSEMBLY__
2440 /*
2441  * WARNING: The C register and register group struct declarations are provided for
2442  * convenience and illustrative purposes. They should, however, be used with
2443  * caution as the C language standard provides no guarantees about the alignment or
2444  * atomicity of device memory accesses. The recommended practice for writing
2445  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2446  * alt_write_word() functions.
2447  *
2448  * The struct declaration for register ALT_NAND_CFG_ECC_CORRECTION.
2449  */
2450 struct ALT_NAND_CFG_ECC_CORRECTION_s
2451 {
2452  uint32_t value : 8; /* ALT_NAND_CFG_ECC_CORRECTION_VALUE */
2453  uint32_t : 8; /* *UNDEFINED* */
2454  uint32_t erase_threshold : 16; /* ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD */
2455 };
2456 
2457 /* The typedef declaration for register ALT_NAND_CFG_ECC_CORRECTION. */
2458 typedef volatile struct ALT_NAND_CFG_ECC_CORRECTION_s ALT_NAND_CFG_ECC_CORRECTION_t;
2459 #endif /* __ASSEMBLY__ */
2460 
2461 /* The reset value of the ALT_NAND_CFG_ECC_CORRECTION register. */
2462 #define ALT_NAND_CFG_ECC_CORRECTION_RESET 0x00000008
2463 /* The byte offset of the ALT_NAND_CFG_ECC_CORRECTION register from the beginning of the component. */
2464 #define ALT_NAND_CFG_ECC_CORRECTION_OFST 0x1b0
2465 
2466 /*
2467  * Register : read_mode
2468  *
2469  * The type of read sequence that the controller will follow for pipe read
2470  * commands.
2471  *
2472  * Register Layout
2473  *
2474  * Bits | Access | Reset | Description
2475  * :-------|:-------|:--------|:--------------------------
2476  * [3:0] | RW | 0x0 | ALT_NAND_CFG_RD_MOD_VALUE
2477  * [31:4] | ??? | Unknown | *UNDEFINED*
2478  *
2479  */
2480 /*
2481  * Field : value
2482  *
2483  * The values in the field should be as follows[list]
2484  *
2485  * [*]4'h0 - This value informs the controller that the pipe read sequence to
2486  * follow is of
2487  *
2488  * a normal read.
2489  *
2490  * For 512 byte page devices, Normal read sequence is,
2491  *
2492  * C00, Address, Data, .....
2493  *
2494  * For devices with page size greater that 512 bytes, the sequence is,
2495  *
2496  * C00, Address, C30, Data.....
2497  *
2498  * [*]4'h1 - This value informs the controller that the pipe read sequence to
2499  * follow is of
2500  *
2501  * a Cache Read with the following sequence,
2502  *
2503  * C00, Address, C30, C31, Data, C31, Data, ....., C3F, Data.
2504  *
2505  * [*]4'h2 - This value informs the controller that the pipe read sequence to
2506  * follow is of
2507  *
2508  * a Cache Read with the following sequence,
2509  *
2510  * C00, Address, C31, Data, Data, ....., C34.
2511  *
2512  * [*]4'h3 - This value informs the controller that the pipe read sequence to
2513  * follow is of
2514  *
2515  * a 'N' Plane Read with the following sequence,
2516  *
2517  * C00, Address, C00, Address, C30, Data, C06, Address, CE0, Data.....
2518  *
2519  * [*]4'h4 - This value informs the controller that the pipe read sequence to
2520  * follow is of
2521  *
2522  * a 'N' Plane Read with the following sequence,
2523  *
2524  * C60, Address, C60, Address, C30, C00, Address, C05, Address, CE0, Data, C00,
2525  *
2526  * Address, C05, Address, CE0, Data.....
2527  *
2528  * [*]4'h5 - This value informs the controller that the pipe read sequence to
2529  * follow is of
2530  *
2531  * a 'N' Plane Cache Read with the following sequence,
2532  *
2533  * C60, Address, C60, Address, C30, C31, C00, Address, C05, Address, CE0, Data,
2534  *
2535  * C00, Address, C05, Address, CE0, Data, ....., C3F, C00, Address, C05, Address,
2536  *
2537  * CE0, Data, C00, Address, C05, Address, CE0, Data
2538  *
2539  * [*]4'h6 - This value informs the controller that the pipe read sequence to
2540  * follow is of
2541  *
2542  * a 'N' Plane Read with the following sequence,
2543  *
2544  * C00, Address, C32, .., C00, Address, C30, C06, Address, CE0, Data,
2545  *
2546  * C06, Address, CE0, Data,....
2547  *
2548  * [*]4'h7 - This value informs the controller that the pipe read sequence to
2549  * follow is of
2550  *
2551  * a 'N' Plane Cache Read with the following sequence,
2552  *
2553  * C00, Address, C32,..., C00, Address, C30, C31,C06, Address, CE0, Data,
2554  *
2555  * C31, C06, Address, CE0, Data, C3F, C06, Address, CE0, Data....
2556  *
2557  * [*]4'h8 - This value informs the controller that the pipe read sequence to
2558  * follow is of
2559  *
2560  * a 'N' Plane Cache Read with the following sequence,
2561  *
2562  * C60, Address, C60, Address, C33, C31, C00, Address, C05, Address, CE0, Data,
2563  *
2564  * C00, Address, C05, Address, CE0, Data, ....., C3F, C00, Address, C05, Address,
2565  *
2566  * CE0, Data, C00, Address, C05, Address, CE0, Data
2567  *
2568  * [*]4'h9 - 4'h15 - Reserved.
2569  *
2570  * [/list]
2571  *
2572  * ..... indicates that the previous sequence is repeated till the last page.
2573  *
2574  * Field Access Macros:
2575  *
2576  */
2577 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RD_MOD_VALUE register field. */
2578 #define ALT_NAND_CFG_RD_MOD_VALUE_LSB 0
2579 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RD_MOD_VALUE register field. */
2580 #define ALT_NAND_CFG_RD_MOD_VALUE_MSB 3
2581 /* The width in bits of the ALT_NAND_CFG_RD_MOD_VALUE register field. */
2582 #define ALT_NAND_CFG_RD_MOD_VALUE_WIDTH 4
2583 /* The mask used to set the ALT_NAND_CFG_RD_MOD_VALUE register field value. */
2584 #define ALT_NAND_CFG_RD_MOD_VALUE_SET_MSK 0x0000000f
2585 /* The mask used to clear the ALT_NAND_CFG_RD_MOD_VALUE register field value. */
2586 #define ALT_NAND_CFG_RD_MOD_VALUE_CLR_MSK 0xfffffff0
2587 /* The reset value of the ALT_NAND_CFG_RD_MOD_VALUE register field. */
2588 #define ALT_NAND_CFG_RD_MOD_VALUE_RESET 0x0
2589 /* Extracts the ALT_NAND_CFG_RD_MOD_VALUE field value from a register. */
2590 #define ALT_NAND_CFG_RD_MOD_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2591 /* Produces a ALT_NAND_CFG_RD_MOD_VALUE register field value suitable for setting the register. */
2592 #define ALT_NAND_CFG_RD_MOD_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2593 
2594 #ifndef __ASSEMBLY__
2595 /*
2596  * WARNING: The C register and register group struct declarations are provided for
2597  * convenience and illustrative purposes. They should, however, be used with
2598  * caution as the C language standard provides no guarantees about the alignment or
2599  * atomicity of device memory accesses. The recommended practice for writing
2600  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2601  * alt_write_word() functions.
2602  *
2603  * The struct declaration for register ALT_NAND_CFG_RD_MOD.
2604  */
2605 struct ALT_NAND_CFG_RD_MOD_s
2606 {
2607  uint32_t value : 4; /* ALT_NAND_CFG_RD_MOD_VALUE */
2608  uint32_t : 28; /* *UNDEFINED* */
2609 };
2610 
2611 /* The typedef declaration for register ALT_NAND_CFG_RD_MOD. */
2612 typedef volatile struct ALT_NAND_CFG_RD_MOD_s ALT_NAND_CFG_RD_MOD_t;
2613 #endif /* __ASSEMBLY__ */
2614 
2615 /* The reset value of the ALT_NAND_CFG_RD_MOD register. */
2616 #define ALT_NAND_CFG_RD_MOD_RESET 0x00000000
2617 /* The byte offset of the ALT_NAND_CFG_RD_MOD register from the beginning of the component. */
2618 #define ALT_NAND_CFG_RD_MOD_OFST 0x1c0
2619 
2620 /*
2621  * Register : write_mode
2622  *
2623  * The type of write sequence that the controller will follow for pipe write
2624  * commands.
2625  *
2626  * Register Layout
2627  *
2628  * Bits | Access | Reset | Description
2629  * :-------|:-------|:--------|:--------------------------
2630  * [3:0] | RW | 0x0 | ALT_NAND_CFG_WR_MOD_VALUE
2631  * [31:4] | ??? | Unknown | *UNDEFINED*
2632  *
2633  */
2634 /*
2635  * Field : value
2636  *
2637  * The values in the field should be as follows[list]
2638  *
2639  * [*]4'h0 - This value informs the controller that the pipe write sequence to
2640  * follow is of
2641  *
2642  * a normal write with the following sequence,
2643  *
2644  * C80, Address, Data, C10.....
2645  *
2646  * [*]4'h1 - This value informs the controller that the pipe write sequence to
2647  * follow is of
2648  *
2649  * a Cache Program with the following sequence,
2650  *
2651  * C80, Address, Data, C15, ....., C80, Address, Data, C10.
2652  *
2653  * [*]4'h2 - This value informs the controller that the pipe write sequence to
2654  * follow is of
2655  *
2656  * a Two/Four Plane Program with the following sequence,
2657  *
2658  * C80, Address, Data, C11, C81, Address, Data, C10.....
2659  *
2660  * [*]4'h3 - This value informs the controller that the pipe write sequence to
2661  * follow is of
2662  *
2663  * a 'N' Plane Program with the following sequence,
2664  *
2665  * C80, Address, Data, C11, C80, Address, Data, C10.....
2666  *
2667  * [*]4'h4 - This value informs the controller that the pipe write sequence to
2668  * follow is of
2669  *
2670  * a 'N' Plane Cache Program with the following sequence,
2671  *
2672  * C80, Address, Data, C11, C80, Address, Data, C15.....C80, Address, Data, C11,
2673  *
2674  * C80, Address, Data, C10.
2675  *
2676  * [*]4'h5 - This value informs the controller that the pipe write sequence to
2677  * follow is of
2678  *
2679  * a 'N' Plane Cache Program with the following sequence,
2680  *
2681  * C80, Address, Data, C11, C81, Address, Data, C15.....C80, Address, Data, C11,
2682  *
2683  * C81, Address, Data, C10.
2684  *
2685  * [*]4'h6 - 4'h15 - Reserved.
2686  *
2687  * [/list]
2688  *
2689  * ..... indicates that the previous sequence is repeated till the last page.
2690  *
2691  * Field Access Macros:
2692  *
2693  */
2694 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_WR_MOD_VALUE register field. */
2695 #define ALT_NAND_CFG_WR_MOD_VALUE_LSB 0
2696 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_WR_MOD_VALUE register field. */
2697 #define ALT_NAND_CFG_WR_MOD_VALUE_MSB 3
2698 /* The width in bits of the ALT_NAND_CFG_WR_MOD_VALUE register field. */
2699 #define ALT_NAND_CFG_WR_MOD_VALUE_WIDTH 4
2700 /* The mask used to set the ALT_NAND_CFG_WR_MOD_VALUE register field value. */
2701 #define ALT_NAND_CFG_WR_MOD_VALUE_SET_MSK 0x0000000f
2702 /* The mask used to clear the ALT_NAND_CFG_WR_MOD_VALUE register field value. */
2703 #define ALT_NAND_CFG_WR_MOD_VALUE_CLR_MSK 0xfffffff0
2704 /* The reset value of the ALT_NAND_CFG_WR_MOD_VALUE register field. */
2705 #define ALT_NAND_CFG_WR_MOD_VALUE_RESET 0x0
2706 /* Extracts the ALT_NAND_CFG_WR_MOD_VALUE field value from a register. */
2707 #define ALT_NAND_CFG_WR_MOD_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2708 /* Produces a ALT_NAND_CFG_WR_MOD_VALUE register field value suitable for setting the register. */
2709 #define ALT_NAND_CFG_WR_MOD_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2710 
2711 #ifndef __ASSEMBLY__
2712 /*
2713  * WARNING: The C register and register group struct declarations are provided for
2714  * convenience and illustrative purposes. They should, however, be used with
2715  * caution as the C language standard provides no guarantees about the alignment or
2716  * atomicity of device memory accesses. The recommended practice for writing
2717  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2718  * alt_write_word() functions.
2719  *
2720  * The struct declaration for register ALT_NAND_CFG_WR_MOD.
2721  */
2722 struct ALT_NAND_CFG_WR_MOD_s
2723 {
2724  uint32_t value : 4; /* ALT_NAND_CFG_WR_MOD_VALUE */
2725  uint32_t : 28; /* *UNDEFINED* */
2726 };
2727 
2728 /* The typedef declaration for register ALT_NAND_CFG_WR_MOD. */
2729 typedef volatile struct ALT_NAND_CFG_WR_MOD_s ALT_NAND_CFG_WR_MOD_t;
2730 #endif /* __ASSEMBLY__ */
2731 
2732 /* The reset value of the ALT_NAND_CFG_WR_MOD register. */
2733 #define ALT_NAND_CFG_WR_MOD_RESET 0x00000000
2734 /* The byte offset of the ALT_NAND_CFG_WR_MOD register from the beginning of the component. */
2735 #define ALT_NAND_CFG_WR_MOD_OFST 0x1d0
2736 
2737 /*
2738  * Register : copyback_mode
2739  *
2740  * The type of copyback sequence that the controller will follow.
2741  *
2742  * Register Layout
2743  *
2744  * Bits | Access | Reset | Description
2745  * :-------|:-------|:--------|:--------------------------------
2746  * [3:0] | RW | 0x0 | ALT_NAND_CFG_COPYBACK_MOD_VALUE
2747  * [31:4] | ??? | Unknown | *UNDEFINED*
2748  *
2749  */
2750 /*
2751  * Field : value
2752  *
2753  * The values in the field should be as follows[list]
2754  *
2755  * [*]4'h0 - This value informs the controller that the copyback sequence to follow
2756  * is,
2757  *
2758  * C00, Address, C35, C85, Address, C10
2759  *
2760  * [*]4'h1 - This value informs the controller that the copyback sequence to follow
2761  * is,
2762  *
2763  * C00, Address, C30, C8C, Address, C10
2764  *
2765  * [*]4'h2 - This value informs the controller that the copyback sequence to follow
2766  * is,
2767  *
2768  * C00, Address, C8A, Address, C10
2769  *
2770  * [*]4'h3 - This value informs the controller that the copyback sequence to follow
2771  * is of
2772  *
2773  * a four plane copyback sequence,
2774  *
2775  * C00, Address, C03, Address, C03, Address, C03, Address, C8A, Address, C11,
2776  *
2777  * C8A, Address, C11, C8A, Address, C11, C8A, Address, C10.
2778  *
2779  * [*]4'h4 - This value informs the controller that the copyback sequence to follow
2780  * is of
2781  *
2782  * a two plane copyback sequence,
2783  *
2784  * C00, Address, C35, C00, Address, C35, C85, Address, C11, C81, Address, C10.
2785  *
2786  * [*]4'h5 - This value informs the controller that the copyback sequence to follow
2787  * is of
2788  *
2789  * a two plane copyback sequence,
2790  *
2791  * C60, Address, C60, Address, C35, C85, Address, C11, C81, Address, C10.
2792  *
2793  * [*]4'h6 - This value informs the controller that the copyback sequence to follow
2794  * is of
2795  *
2796  * a two plane copyback sequence,
2797  *
2798  * C00, Address, C00, Address, C35, C85, Address, C11, C80, Address, C10.
2799  *
2800  * [*]4'h7 - This value informs the controller that the copyback sequence to follow
2801  * is of
2802  *
2803  * a two plane copyback sequence,
2804  *
2805  * C60, Address, C60, Address, C30, C8C, Address, C11, C8C, Address, C10.
2806  *
2807  * [*]4'h8 - 4'h15 - Reserved.[/list]
2808  *
2809  * Field Access Macros:
2810  *
2811  */
2812 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_COPYBACK_MOD_VALUE register field. */
2813 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_LSB 0
2814 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_COPYBACK_MOD_VALUE register field. */
2815 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_MSB 3
2816 /* The width in bits of the ALT_NAND_CFG_COPYBACK_MOD_VALUE register field. */
2817 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_WIDTH 4
2818 /* The mask used to set the ALT_NAND_CFG_COPYBACK_MOD_VALUE register field value. */
2819 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_SET_MSK 0x0000000f
2820 /* The mask used to clear the ALT_NAND_CFG_COPYBACK_MOD_VALUE register field value. */
2821 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_CLR_MSK 0xfffffff0
2822 /* The reset value of the ALT_NAND_CFG_COPYBACK_MOD_VALUE register field. */
2823 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_RESET 0x0
2824 /* Extracts the ALT_NAND_CFG_COPYBACK_MOD_VALUE field value from a register. */
2825 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2826 /* Produces a ALT_NAND_CFG_COPYBACK_MOD_VALUE register field value suitable for setting the register. */
2827 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2828 
2829 #ifndef __ASSEMBLY__
2830 /*
2831  * WARNING: The C register and register group struct declarations are provided for
2832  * convenience and illustrative purposes. They should, however, be used with
2833  * caution as the C language standard provides no guarantees about the alignment or
2834  * atomicity of device memory accesses. The recommended practice for writing
2835  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2836  * alt_write_word() functions.
2837  *
2838  * The struct declaration for register ALT_NAND_CFG_COPYBACK_MOD.
2839  */
2840 struct ALT_NAND_CFG_COPYBACK_MOD_s
2841 {
2842  uint32_t value : 4; /* ALT_NAND_CFG_COPYBACK_MOD_VALUE */
2843  uint32_t : 28; /* *UNDEFINED* */
2844 };
2845 
2846 /* The typedef declaration for register ALT_NAND_CFG_COPYBACK_MOD. */
2847 typedef volatile struct ALT_NAND_CFG_COPYBACK_MOD_s ALT_NAND_CFG_COPYBACK_MOD_t;
2848 #endif /* __ASSEMBLY__ */
2849 
2850 /* The reset value of the ALT_NAND_CFG_COPYBACK_MOD register. */
2851 #define ALT_NAND_CFG_COPYBACK_MOD_RESET 0x00000000
2852 /* The byte offset of the ALT_NAND_CFG_COPYBACK_MOD register from the beginning of the component. */
2853 #define ALT_NAND_CFG_COPYBACK_MOD_OFST 0x1e0
2854 
2855 /*
2856  * Register : rdwr_en_lo_cnt
2857  *
2858  * Read/Write Enable low pulse width
2859  *
2860  * Register Layout
2861  *
2862  * Bits | Access | Reset | Description
2863  * :-------|:-------|:--------|:----------------------------------
2864  * [4:0] | RW | 0x12 | ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE
2865  * [31:5] | ??? | Unknown | *UNDEFINED*
2866  *
2867  */
2868 /*
2869  * Field : value
2870  *
2871  * Number of clk_x cycles that read or write enable will kept low to meet the min
2872  *
2873  * Trp/Twp parameter of the device. The value in this register plus rdwr_en_hi_cnt
2874  *
2875  * register value should meet the min cycle time of the device connected. The
2876  * default
2877  *
2878  * value is calculated assuming the max clk_x time period of 4ns to work with ONFI
2879  *
2880  * Mode 0 mode of 100ns device cycle time. This assumes a 1x/5x clocking scheme.
2881  *
2882  * Field Access Macros:
2883  *
2884  */
2885 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field. */
2886 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_LSB 0
2887 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field. */
2888 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_MSB 4
2889 /* The width in bits of the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field. */
2890 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_WIDTH 5
2891 /* The mask used to set the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field value. */
2892 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_SET_MSK 0x0000001f
2893 /* The mask used to clear the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field value. */
2894 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_CLR_MSK 0xffffffe0
2895 /* The reset value of the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field. */
2896 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_RESET 0x12
2897 /* Extracts the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE field value from a register. */
2898 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
2899 /* Produces a ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field value suitable for setting the register. */
2900 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
2901 
2902 #ifndef __ASSEMBLY__
2903 /*
2904  * WARNING: The C register and register group struct declarations are provided for
2905  * convenience and illustrative purposes. They should, however, be used with
2906  * caution as the C language standard provides no guarantees about the alignment or
2907  * atomicity of device memory accesses. The recommended practice for writing
2908  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2909  * alt_write_word() functions.
2910  *
2911  * The struct declaration for register ALT_NAND_CFG_RDWR_EN_LO_CNT.
2912  */
2913 struct ALT_NAND_CFG_RDWR_EN_LO_CNT_s
2914 {
2915  uint32_t value : 5; /* ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE */
2916  uint32_t : 27; /* *UNDEFINED* */
2917 };
2918 
2919 /* The typedef declaration for register ALT_NAND_CFG_RDWR_EN_LO_CNT. */
2920 typedef volatile struct ALT_NAND_CFG_RDWR_EN_LO_CNT_s ALT_NAND_CFG_RDWR_EN_LO_CNT_t;
2921 #endif /* __ASSEMBLY__ */
2922 
2923 /* The reset value of the ALT_NAND_CFG_RDWR_EN_LO_CNT register. */
2924 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_RESET 0x00000012
2925 /* The byte offset of the ALT_NAND_CFG_RDWR_EN_LO_CNT register from the beginning of the component. */
2926 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_OFST 0x1f0
2927 
2928 /*
2929  * Register : rdwr_en_hi_cnt
2930  *
2931  * Read/Write Enable high pulse width
2932  *
2933  * Register Layout
2934  *
2935  * Bits | Access | Reset | Description
2936  * :-------|:-------|:--------|:----------------------------------
2937  * [4:0] | RW | 0xc | ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE
2938  * [31:5] | ??? | Unknown | *UNDEFINED*
2939  *
2940  */
2941 /*
2942  * Field : value
2943  *
2944  * Number of clk_x cycles that read or write enable will kept high to meet the min
2945  *
2946  * Treh/Tweh parameter of the device. The value in this register plus
2947  * rdwr_en_lo_cnt
2948  *
2949  * register value should meet the min cycle time of the device connected. The
2950  * default
2951  *
2952  * value is calculated assuming the max clk_x time period of 4ns to work with ONFI
2953  *
2954  * Mode 0 mode of 100ns device cycle time. This assumes a 1x/5x clocking scheme.
2955  *
2956  * Field Access Macros:
2957  *
2958  */
2959 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field. */
2960 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_LSB 0
2961 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field. */
2962 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_MSB 4
2963 /* The width in bits of the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field. */
2964 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_WIDTH 5
2965 /* The mask used to set the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field value. */
2966 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_SET_MSK 0x0000001f
2967 /* The mask used to clear the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field value. */
2968 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_CLR_MSK 0xffffffe0
2969 /* The reset value of the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field. */
2970 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_RESET 0xc
2971 /* Extracts the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE field value from a register. */
2972 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
2973 /* Produces a ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field value suitable for setting the register. */
2974 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
2975 
2976 #ifndef __ASSEMBLY__
2977 /*
2978  * WARNING: The C register and register group struct declarations are provided for
2979  * convenience and illustrative purposes. They should, however, be used with
2980  * caution as the C language standard provides no guarantees about the alignment or
2981  * atomicity of device memory accesses. The recommended practice for writing
2982  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2983  * alt_write_word() functions.
2984  *
2985  * The struct declaration for register ALT_NAND_CFG_RDWR_EN_HI_CNT.
2986  */
2987 struct ALT_NAND_CFG_RDWR_EN_HI_CNT_s
2988 {
2989  uint32_t value : 5; /* ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE */
2990  uint32_t : 27; /* *UNDEFINED* */
2991 };
2992 
2993 /* The typedef declaration for register ALT_NAND_CFG_RDWR_EN_HI_CNT. */
2994 typedef volatile struct ALT_NAND_CFG_RDWR_EN_HI_CNT_s ALT_NAND_CFG_RDWR_EN_HI_CNT_t;
2995 #endif /* __ASSEMBLY__ */
2996 
2997 /* The reset value of the ALT_NAND_CFG_RDWR_EN_HI_CNT register. */
2998 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_RESET 0x0000000c
2999 /* The byte offset of the ALT_NAND_CFG_RDWR_EN_HI_CNT register from the beginning of the component. */
3000 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_OFST 0x200
3001 
3002 /*
3003  * Register : max_rd_delay
3004  *
3005  * Max round trip read data delay for data capture
3006  *
3007  * Register Layout
3008  *
3009  * Bits | Access | Reset | Description
3010  * :-------|:-------|:--------|:--------------------------------
3011  * [3:0] | RW | 0x0 | ALT_NAND_CFG_MAX_RD_DELAY_VALUE
3012  * [31:4] | ??? | Unknown | *UNDEFINED*
3013  *
3014  */
3015 /*
3016  * Field : value
3017  *
3018  * Number of clk_x cycles after generation of feedback clk_x_out pulse when it is
3019  * safe
3020  *
3021  * to synchronize received data to clk_x domain. Data should have been registered
3022  * with
3023  *
3024  * clk_x_in and stable by the time max_rd_delay cycles has elapsed. Please see
3025  * timing
3026  *
3027  * diagram in bus interface timing section of this guide for further elaboration. A
3028  *
3029  * default value of zero will mean a value of clk_x multiple minus one.
3030  *
3031  * Field Access Macros:
3032  *
3033  */
3034 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field. */
3035 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_LSB 0
3036 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field. */
3037 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_MSB 3
3038 /* The width in bits of the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field. */
3039 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_WIDTH 4
3040 /* The mask used to set the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field value. */
3041 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_SET_MSK 0x0000000f
3042 /* The mask used to clear the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field value. */
3043 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_CLR_MSK 0xfffffff0
3044 /* The reset value of the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field. */
3045 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_RESET 0x0
3046 /* Extracts the ALT_NAND_CFG_MAX_RD_DELAY_VALUE field value from a register. */
3047 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
3048 /* Produces a ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field value suitable for setting the register. */
3049 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_SET(value) (((value) << 0) & 0x0000000f)
3050 
3051 #ifndef __ASSEMBLY__
3052 /*
3053  * WARNING: The C register and register group struct declarations are provided for
3054  * convenience and illustrative purposes. They should, however, be used with
3055  * caution as the C language standard provides no guarantees about the alignment or
3056  * atomicity of device memory accesses. The recommended practice for writing
3057  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3058  * alt_write_word() functions.
3059  *
3060  * The struct declaration for register ALT_NAND_CFG_MAX_RD_DELAY.
3061  */
3062 struct ALT_NAND_CFG_MAX_RD_DELAY_s
3063 {
3064  uint32_t value : 4; /* ALT_NAND_CFG_MAX_RD_DELAY_VALUE */
3065  uint32_t : 28; /* *UNDEFINED* */
3066 };
3067 
3068 /* The typedef declaration for register ALT_NAND_CFG_MAX_RD_DELAY. */
3069 typedef volatile struct ALT_NAND_CFG_MAX_RD_DELAY_s ALT_NAND_CFG_MAX_RD_DELAY_t;
3070 #endif /* __ASSEMBLY__ */
3071 
3072 /* The reset value of the ALT_NAND_CFG_MAX_RD_DELAY register. */
3073 #define ALT_NAND_CFG_MAX_RD_DELAY_RESET 0x00000000
3074 /* The byte offset of the ALT_NAND_CFG_MAX_RD_DELAY register from the beginning of the component. */
3075 #define ALT_NAND_CFG_MAX_RD_DELAY_OFST 0x210
3076 
3077 /*
3078  * Register : cs_setup_cnt
3079  *
3080  * Chip select setup/tWB time
3081  *
3082  * Register Layout
3083  *
3084  * Bits | Access | Reset | Description
3085  * :--------|:-------|:--------|:--------------------------------
3086  * [4:0] | RW | 0x3 | ALT_NAND_CFG_CS_SETUP_CNT_VALUE
3087  * [11:5] | ??? | Unknown | *UNDEFINED*
3088  * [17:12] | RW | 0xa | ALT_NAND_CFG_CS_SETUP_CNT_TWB
3089  * [31:18] | ??? | Unknown | *UNDEFINED*
3090  *
3091  */
3092 /*
3093  * Field : value
3094  *
3095  * Number of clk_x cycles required for meeting chip select setup time. This
3096  * register
3097  *
3098  * refers to device timing parameter Tcs. The value in this registers reflects the
3099  * extra
3100  *
3101  * setup cycles for chip select before read/write enable signal is set low. The
3102  * default value
3103  *
3104  * is calculated for ONFI Timing mode 0 Tcs = 70ns and maximum clk_x period of 4ns
3105  * for
3106  *
3107  * 1x/5x clock multiple for 20ns cycle time device.
3108  *
3109  * Please refer to Figure 3.3 for the relationship between the cs_setup_cnt and
3110  * rdwr_en_lo_cnt values.
3111  *
3112  * Field Access Macros:
3113  *
3114  */
3115 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field. */
3116 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_LSB 0
3117 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field. */
3118 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_MSB 4
3119 /* The width in bits of the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field. */
3120 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_WIDTH 5
3121 /* The mask used to set the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field value. */
3122 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_SET_MSK 0x0000001f
3123 /* The mask used to clear the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field value. */
3124 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_CLR_MSK 0xffffffe0
3125 /* The reset value of the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field. */
3126 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_RESET 0x3
3127 /* Extracts the ALT_NAND_CFG_CS_SETUP_CNT_VALUE field value from a register. */
3128 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
3129 /* Produces a ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field value suitable for setting the register. */
3130 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
3131 
3132 /*
3133  * Field : twb
3134  *
3135  * Number of clk_x cycles required for meeting the tWB time. This register
3136  *
3137  * refers to device timing parameter TWB.
3138  *
3139  * Field Access Macros:
3140  *
3141  */
3142 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_CS_SETUP_CNT_TWB register field. */
3143 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_LSB 12
3144 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_CS_SETUP_CNT_TWB register field. */
3145 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_MSB 17
3146 /* The width in bits of the ALT_NAND_CFG_CS_SETUP_CNT_TWB register field. */
3147 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_WIDTH 6
3148 /* The mask used to set the ALT_NAND_CFG_CS_SETUP_CNT_TWB register field value. */
3149 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_SET_MSK 0x0003f000
3150 /* The mask used to clear the ALT_NAND_CFG_CS_SETUP_CNT_TWB register field value. */
3151 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_CLR_MSK 0xfffc0fff
3152 /* The reset value of the ALT_NAND_CFG_CS_SETUP_CNT_TWB register field. */
3153 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_RESET 0xa
3154 /* Extracts the ALT_NAND_CFG_CS_SETUP_CNT_TWB field value from a register. */
3155 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_GET(value) (((value) & 0x0003f000) >> 12)
3156 /* Produces a ALT_NAND_CFG_CS_SETUP_CNT_TWB register field value suitable for setting the register. */
3157 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_SET(value) (((value) << 12) & 0x0003f000)
3158 
3159 #ifndef __ASSEMBLY__
3160 /*
3161  * WARNING: The C register and register group struct declarations are provided for
3162  * convenience and illustrative purposes. They should, however, be used with
3163  * caution as the C language standard provides no guarantees about the alignment or
3164  * atomicity of device memory accesses. The recommended practice for writing
3165  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3166  * alt_write_word() functions.
3167  *
3168  * The struct declaration for register ALT_NAND_CFG_CS_SETUP_CNT.
3169  */
3170 struct ALT_NAND_CFG_CS_SETUP_CNT_s
3171 {
3172  uint32_t value : 5; /* ALT_NAND_CFG_CS_SETUP_CNT_VALUE */
3173  uint32_t : 7; /* *UNDEFINED* */
3174  uint32_t twb : 6; /* ALT_NAND_CFG_CS_SETUP_CNT_TWB */
3175  uint32_t : 14; /* *UNDEFINED* */
3176 };
3177 
3178 /* The typedef declaration for register ALT_NAND_CFG_CS_SETUP_CNT. */
3179 typedef volatile struct ALT_NAND_CFG_CS_SETUP_CNT_s ALT_NAND_CFG_CS_SETUP_CNT_t;
3180 #endif /* __ASSEMBLY__ */
3181 
3182 /* The reset value of the ALT_NAND_CFG_CS_SETUP_CNT register. */
3183 #define ALT_NAND_CFG_CS_SETUP_CNT_RESET 0x0000a003
3184 /* The byte offset of the ALT_NAND_CFG_CS_SETUP_CNT register from the beginning of the component. */
3185 #define ALT_NAND_CFG_CS_SETUP_CNT_OFST 0x220
3186 
3187 /*
3188  * Register : spare_area_skip_bytes
3189  *
3190  * Spare area skip bytes
3191  *
3192  * Register Layout
3193  *
3194  * Bits | Access | Reset | Description
3195  * :-------|:-------|:--------|:-----------------------------------------
3196  * [5:0] | RW | 0x0 | ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE
3197  * [31:6] | ??? | Unknown | *UNDEFINED*
3198  *
3199  */
3200 /*
3201  * Field : value
3202  *
3203  * Number of bytes to skip from start of spare area before last ECC sector
3204  *
3205  * data starts. The bytes will be written with the value programmed in the
3206  *
3207  * spare_area_marker register. This register could be potentially used to
3208  *
3209  * preserve the bad block marker in the spare area by marking it good.
3210  *
3211  * The default value is zero which means no bytes will be skipped and
3212  *
3213  * last ECC sector will start from the beginning of spare area. This value
3214  *
3215  * should be an even number.
3216  *
3217  * Field Access Macros:
3218  *
3219  */
3220 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field. */
3221 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_LSB 0
3222 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field. */
3223 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_MSB 5
3224 /* The width in bits of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field. */
3225 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_WIDTH 6
3226 /* The mask used to set the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field value. */
3227 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_SET_MSK 0x0000003f
3228 /* The mask used to clear the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field value. */
3229 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_CLR_MSK 0xffffffc0
3230 /* The reset value of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field. */
3231 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_RESET 0x0
3232 /* Extracts the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE field value from a register. */
3233 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
3234 /* Produces a ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field value suitable for setting the register. */
3235 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_SET(value) (((value) << 0) & 0x0000003f)
3236 
3237 #ifndef __ASSEMBLY__
3238 /*
3239  * WARNING: The C register and register group struct declarations are provided for
3240  * convenience and illustrative purposes. They should, however, be used with
3241  * caution as the C language standard provides no guarantees about the alignment or
3242  * atomicity of device memory accesses. The recommended practice for writing
3243  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3244  * alt_write_word() functions.
3245  *
3246  * The struct declaration for register ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES.
3247  */
3248 struct ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_s
3249 {
3250  uint32_t value : 6; /* ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE */
3251  uint32_t : 26; /* *UNDEFINED* */
3252 };
3253 
3254 /* The typedef declaration for register ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES. */
3255 typedef volatile struct ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_s ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_t;
3256 #endif /* __ASSEMBLY__ */
3257 
3258 /* The reset value of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES register. */
3259 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_RESET 0x00000000
3260 /* The byte offset of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES register from the beginning of the component. */
3261 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_OFST 0x230
3262 
3263 /*
3264  * Register : spare_area_marker
3265  *
3266  * Spare area marker value
3267  *
3268  * Register Layout
3269  *
3270  * Bits | Access | Reset | Description
3271  * :--------|:-------|:--------|:-------------------------------------
3272  * [15:0] | RW | 0xffff | ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE
3273  * [31:16] | ??? | Unknown | *UNDEFINED*
3274  *
3275  */
3276 /*
3277  * Field : value
3278  *
3279  * A 16bit value that will be written in the spare area skip bytes. This value
3280  *
3281  * will be used by controller while in the MAIN mode of data transfer.
3282  *
3283  * Field Access Macros:
3284  *
3285  */
3286 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field. */
3287 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_LSB 0
3288 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field. */
3289 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_MSB 15
3290 /* The width in bits of the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field. */
3291 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_WIDTH 16
3292 /* The mask used to set the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field value. */
3293 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_SET_MSK 0x0000ffff
3294 /* The mask used to clear the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field value. */
3295 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_CLR_MSK 0xffff0000
3296 /* The reset value of the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field. */
3297 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_RESET 0xffff
3298 /* Extracts the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE field value from a register. */
3299 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3300 /* Produces a ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field value suitable for setting the register. */
3301 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3302 
3303 #ifndef __ASSEMBLY__
3304 /*
3305  * WARNING: The C register and register group struct declarations are provided for
3306  * convenience and illustrative purposes. They should, however, be used with
3307  * caution as the C language standard provides no guarantees about the alignment or
3308  * atomicity of device memory accesses. The recommended practice for writing
3309  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3310  * alt_write_word() functions.
3311  *
3312  * The struct declaration for register ALT_NAND_CFG_SPARE_AREA_MARKER.
3313  */
3314 struct ALT_NAND_CFG_SPARE_AREA_MARKER_s
3315 {
3316  uint32_t value : 16; /* ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE */
3317  uint32_t : 16; /* *UNDEFINED* */
3318 };
3319 
3320 /* The typedef declaration for register ALT_NAND_CFG_SPARE_AREA_MARKER. */
3321 typedef volatile struct ALT_NAND_CFG_SPARE_AREA_MARKER_s ALT_NAND_CFG_SPARE_AREA_MARKER_t;
3322 #endif /* __ASSEMBLY__ */
3323 
3324 /* The reset value of the ALT_NAND_CFG_SPARE_AREA_MARKER register. */
3325 #define ALT_NAND_CFG_SPARE_AREA_MARKER_RESET 0x0000ffff
3326 /* The byte offset of the ALT_NAND_CFG_SPARE_AREA_MARKER register from the beginning of the component. */
3327 #define ALT_NAND_CFG_SPARE_AREA_MARKER_OFST 0x240
3328 
3329 /*
3330  * Register : devices_connected
3331  *
3332  * Number of Devices connected on one bank
3333  *
3334  * Register Layout
3335  *
3336  * Bits | Access | Reset | Description
3337  * :-------|:-------|:--------|:-------------------------------------
3338  * [2:0] | RW | 0x0 | ALT_NAND_CFG_DEVICES_CONNECTED_VALUE
3339  * [31:3] | ??? | Unknown | *UNDEFINED*
3340  *
3341  */
3342 /*
3343  * Field : value
3344  *
3345  * Indicates the number of devices connected to a bank. At POR, the value loaded
3346  *
3347  * is the maximum possible devices that could be connected in this configuration.
3348  *
3349  * Field Access Macros:
3350  *
3351  */
3352 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field. */
3353 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_LSB 0
3354 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field. */
3355 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_MSB 2
3356 /* The width in bits of the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field. */
3357 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_WIDTH 3
3358 /* The mask used to set the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field value. */
3359 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_SET_MSK 0x00000007
3360 /* The mask used to clear the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field value. */
3361 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_CLR_MSK 0xfffffff8
3362 /* The reset value of the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field. */
3363 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_RESET 0x0
3364 /* Extracts the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE field value from a register. */
3365 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_GET(value) (((value) & 0x00000007) >> 0)
3366 /* Produces a ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field value suitable for setting the register. */
3367 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_SET(value) (((value) << 0) & 0x00000007)
3368 
3369 #ifndef __ASSEMBLY__
3370 /*
3371  * WARNING: The C register and register group struct declarations are provided for
3372  * convenience and illustrative purposes. They should, however, be used with
3373  * caution as the C language standard provides no guarantees about the alignment or
3374  * atomicity of device memory accesses. The recommended practice for writing
3375  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3376  * alt_write_word() functions.
3377  *
3378  * The struct declaration for register ALT_NAND_CFG_DEVICES_CONNECTED.
3379  */
3380 struct ALT_NAND_CFG_DEVICES_CONNECTED_s
3381 {
3382  uint32_t value : 3; /* ALT_NAND_CFG_DEVICES_CONNECTED_VALUE */
3383  uint32_t : 29; /* *UNDEFINED* */
3384 };
3385 
3386 /* The typedef declaration for register ALT_NAND_CFG_DEVICES_CONNECTED. */
3387 typedef volatile struct ALT_NAND_CFG_DEVICES_CONNECTED_s ALT_NAND_CFG_DEVICES_CONNECTED_t;
3388 #endif /* __ASSEMBLY__ */
3389 
3390 /* The reset value of the ALT_NAND_CFG_DEVICES_CONNECTED register. */
3391 #define ALT_NAND_CFG_DEVICES_CONNECTED_RESET 0x00000000
3392 /* The byte offset of the ALT_NAND_CFG_DEVICES_CONNECTED register from the beginning of the component. */
3393 #define ALT_NAND_CFG_DEVICES_CONNECTED_OFST 0x250
3394 
3395 /*
3396  * Register : die_mask
3397  *
3398  * Indicates the die differentiator in case of NAND devices with stacked dies.
3399  *
3400  * Register Layout
3401  *
3402  * Bits | Access | Reset | Description
3403  * :--------|:-------|:--------|:---------------------------
3404  * [15:0] | RW | 0x0 | ALT_NAND_CFG_DIE_MSK_VALUE
3405  * [31:16] | ??? | Unknown | *UNDEFINED*
3406  *
3407  */
3408 /*
3409  * Field : value
3410  *
3411  * The die_mask register information will be used for devices having address
3412  * restrictions.
3413  *
3414  * For example, in certain Samsung devices, when the first address in a two-plane
3415  * command
3416  *
3417  * is being sent, it is expected that the address is all zeros. But if the NAND
3418  * device
3419  *
3420  * internally has multiple dies stacked, the die information (MSB of final row
3421  * address) has
3422  *
3423  * to be sent.
3424  *
3425  * The value programmed in this register will be used to mask the address while
3426  * sending
3427  *
3428  * out the last row address.
3429  *
3430  * Field Access Macros:
3431  *
3432  */
3433 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DIE_MSK_VALUE register field. */
3434 #define ALT_NAND_CFG_DIE_MSK_VALUE_LSB 0
3435 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DIE_MSK_VALUE register field. */
3436 #define ALT_NAND_CFG_DIE_MSK_VALUE_MSB 15
3437 /* The width in bits of the ALT_NAND_CFG_DIE_MSK_VALUE register field. */
3438 #define ALT_NAND_CFG_DIE_MSK_VALUE_WIDTH 16
3439 /* The mask used to set the ALT_NAND_CFG_DIE_MSK_VALUE register field value. */
3440 #define ALT_NAND_CFG_DIE_MSK_VALUE_SET_MSK 0x0000ffff
3441 /* The mask used to clear the ALT_NAND_CFG_DIE_MSK_VALUE register field value. */
3442 #define ALT_NAND_CFG_DIE_MSK_VALUE_CLR_MSK 0xffff0000
3443 /* The reset value of the ALT_NAND_CFG_DIE_MSK_VALUE register field. */
3444 #define ALT_NAND_CFG_DIE_MSK_VALUE_RESET 0x0
3445 /* Extracts the ALT_NAND_CFG_DIE_MSK_VALUE field value from a register. */
3446 #define ALT_NAND_CFG_DIE_MSK_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3447 /* Produces a ALT_NAND_CFG_DIE_MSK_VALUE register field value suitable for setting the register. */
3448 #define ALT_NAND_CFG_DIE_MSK_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3449 
3450 #ifndef __ASSEMBLY__
3451 /*
3452  * WARNING: The C register and register group struct declarations are provided for
3453  * convenience and illustrative purposes. They should, however, be used with
3454  * caution as the C language standard provides no guarantees about the alignment or
3455  * atomicity of device memory accesses. The recommended practice for writing
3456  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3457  * alt_write_word() functions.
3458  *
3459  * The struct declaration for register ALT_NAND_CFG_DIE_MSK.
3460  */
3461 struct ALT_NAND_CFG_DIE_MSK_s
3462 {
3463  uint32_t value : 16; /* ALT_NAND_CFG_DIE_MSK_VALUE */
3464  uint32_t : 16; /* *UNDEFINED* */
3465 };
3466 
3467 /* The typedef declaration for register ALT_NAND_CFG_DIE_MSK. */
3468 typedef volatile struct ALT_NAND_CFG_DIE_MSK_s ALT_NAND_CFG_DIE_MSK_t;
3469 #endif /* __ASSEMBLY__ */
3470 
3471 /* The reset value of the ALT_NAND_CFG_DIE_MSK register. */
3472 #define ALT_NAND_CFG_DIE_MSK_RESET 0x00000000
3473 /* The byte offset of the ALT_NAND_CFG_DIE_MSK register from the beginning of the component. */
3474 #define ALT_NAND_CFG_DIE_MSK_OFST 0x260
3475 
3476 /*
3477  * Register : first_block_of_next_plane
3478  *
3479  * The starting block address of the next plane in a multi plane device.
3480  *
3481  * Register Layout
3482  *
3483  * Bits | Access | Reset | Description
3484  * :--------|:-------|:--------|:---------------------------------------------
3485  * [15:0] | RW | 0x1 | ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE
3486  * [31:16] | ??? | Unknown | *UNDEFINED*
3487  *
3488  */
3489 /*
3490  * Field : value
3491  *
3492  * This values informs the controller of the plane structure of the device.
3493  *
3494  * In case the device is a multi plane device and the value here is 1, the
3495  *
3496  * controller understands that the next plane starts from Block number 1
3497  *
3498  * and in conjunction with the number of planes parameter can decide upon the
3499  *
3500  * distribution of blocks in a plane in the device.
3501  *
3502  * Field Access Macros:
3503  *
3504  */
3505 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field. */
3506 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_LSB 0
3507 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field. */
3508 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_MSB 15
3509 /* The width in bits of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field. */
3510 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_WIDTH 16
3511 /* The mask used to set the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field value. */
3512 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_SET_MSK 0x0000ffff
3513 /* The mask used to clear the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field value. */
3514 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_CLR_MSK 0xffff0000
3515 /* The reset value of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field. */
3516 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_RESET 0x1
3517 /* Extracts the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE field value from a register. */
3518 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3519 /* Produces a ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field value suitable for setting the register. */
3520 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3521 
3522 #ifndef __ASSEMBLY__
3523 /*
3524  * WARNING: The C register and register group struct declarations are provided for
3525  * convenience and illustrative purposes. They should, however, be used with
3526  * caution as the C language standard provides no guarantees about the alignment or
3527  * atomicity of device memory accesses. The recommended practice for writing
3528  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3529  * alt_write_word() functions.
3530  *
3531  * The struct declaration for register ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE.
3532  */
3533 struct ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_s
3534 {
3535  uint32_t value : 16; /* ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE */
3536  uint32_t : 16; /* *UNDEFINED* */
3537 };
3538 
3539 /* The typedef declaration for register ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE. */
3540 typedef volatile struct ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_s ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_t;
3541 #endif /* __ASSEMBLY__ */
3542 
3543 /* The reset value of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE register. */
3544 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_RESET 0x00000001
3545 /* The byte offset of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE register from the beginning of the component. */
3546 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_OFST 0x270
3547 
3548 /*
3549  * Register : write_protect
3550  *
3551  * This register is used to control the assertion/de-assertion of the WP# pin to
3552  * the device.
3553  *
3554  * Register Layout
3555  *
3556  * Bits | Access | Reset | Description
3557  * :-------|:-------|:--------|:-----------------------------
3558  * [0] | RW | 0x1 | ALT_NAND_CFG_WR_PROTECT_FLAG
3559  * [31:1] | ??? | Unknown | *UNDEFINED*
3560  *
3561  */
3562 /*
3563  * Field : flag
3564  *
3565  * When the controller is in reset, the WP# pin is always asserted to the device.
3566  * Once the
3567  *
3568  * reset is removed, the WP# is de-asserted. The software will then have to come
3569  * and program
3570  *
3571  * this bit to assert/de-assert the same.
3572  *
3573  * [list][*]1 - Write protect de-assert [*]0 - Write protect assert[/list]
3574  *
3575  * Field Access Macros:
3576  *
3577  */
3578 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_WR_PROTECT_FLAG register field. */
3579 #define ALT_NAND_CFG_WR_PROTECT_FLAG_LSB 0
3580 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_WR_PROTECT_FLAG register field. */
3581 #define ALT_NAND_CFG_WR_PROTECT_FLAG_MSB 0
3582 /* The width in bits of the ALT_NAND_CFG_WR_PROTECT_FLAG register field. */
3583 #define ALT_NAND_CFG_WR_PROTECT_FLAG_WIDTH 1
3584 /* The mask used to set the ALT_NAND_CFG_WR_PROTECT_FLAG register field value. */
3585 #define ALT_NAND_CFG_WR_PROTECT_FLAG_SET_MSK 0x00000001
3586 /* The mask used to clear the ALT_NAND_CFG_WR_PROTECT_FLAG register field value. */
3587 #define ALT_NAND_CFG_WR_PROTECT_FLAG_CLR_MSK 0xfffffffe
3588 /* The reset value of the ALT_NAND_CFG_WR_PROTECT_FLAG register field. */
3589 #define ALT_NAND_CFG_WR_PROTECT_FLAG_RESET 0x1
3590 /* Extracts the ALT_NAND_CFG_WR_PROTECT_FLAG field value from a register. */
3591 #define ALT_NAND_CFG_WR_PROTECT_FLAG_GET(value) (((value) & 0x00000001) >> 0)
3592 /* Produces a ALT_NAND_CFG_WR_PROTECT_FLAG register field value suitable for setting the register. */
3593 #define ALT_NAND_CFG_WR_PROTECT_FLAG_SET(value) (((value) << 0) & 0x00000001)
3594 
3595 #ifndef __ASSEMBLY__
3596 /*
3597  * WARNING: The C register and register group struct declarations are provided for
3598  * convenience and illustrative purposes. They should, however, be used with
3599  * caution as the C language standard provides no guarantees about the alignment or
3600  * atomicity of device memory accesses. The recommended practice for writing
3601  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3602  * alt_write_word() functions.
3603  *
3604  * The struct declaration for register ALT_NAND_CFG_WR_PROTECT.
3605  */
3606 struct ALT_NAND_CFG_WR_PROTECT_s
3607 {
3608  uint32_t flag : 1; /* ALT_NAND_CFG_WR_PROTECT_FLAG */
3609  uint32_t : 31; /* *UNDEFINED* */
3610 };
3611 
3612 /* The typedef declaration for register ALT_NAND_CFG_WR_PROTECT. */
3613 typedef volatile struct ALT_NAND_CFG_WR_PROTECT_s ALT_NAND_CFG_WR_PROTECT_t;
3614 #endif /* __ASSEMBLY__ */
3615 
3616 /* The reset value of the ALT_NAND_CFG_WR_PROTECT register. */
3617 #define ALT_NAND_CFG_WR_PROTECT_RESET 0x00000001
3618 /* The byte offset of the ALT_NAND_CFG_WR_PROTECT register from the beginning of the component. */
3619 #define ALT_NAND_CFG_WR_PROTECT_OFST 0x280
3620 
3621 /*
3622  * Register : re_2_re
3623  *
3624  * Timing parameter between re high to re low (Trhz) for the next bank
3625  *
3626  * Register Layout
3627  *
3628  * Bits | Access | Reset | Description
3629  * :-------|:-------|:--------|:---------------------------
3630  * [5:0] | RW | 0x32 | ALT_NAND_CFG_RE_2_RE_VALUE
3631  * [31:6] | ??? | Unknown | *UNDEFINED*
3632  *
3633  */
3634 /*
3635  * Field : value
3636  *
3637  * Signifies the number of bus interface clk_x clocks that should be introduced
3638  * between
3639  *
3640  * read enable going high to a bank to the read enable going low to the next bank.
3641  * The number
3642  *
3643  * of clocks is the function of device parameter Trhz and controller clock
3644  * frequency.
3645  *
3646  * Field Access Macros:
3647  *
3648  */
3649 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RE_2_RE_VALUE register field. */
3650 #define ALT_NAND_CFG_RE_2_RE_VALUE_LSB 0
3651 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RE_2_RE_VALUE register field. */
3652 #define ALT_NAND_CFG_RE_2_RE_VALUE_MSB 5
3653 /* The width in bits of the ALT_NAND_CFG_RE_2_RE_VALUE register field. */
3654 #define ALT_NAND_CFG_RE_2_RE_VALUE_WIDTH 6
3655 /* The mask used to set the ALT_NAND_CFG_RE_2_RE_VALUE register field value. */
3656 #define ALT_NAND_CFG_RE_2_RE_VALUE_SET_MSK 0x0000003f
3657 /* The mask used to clear the ALT_NAND_CFG_RE_2_RE_VALUE register field value. */
3658 #define ALT_NAND_CFG_RE_2_RE_VALUE_CLR_MSK 0xffffffc0
3659 /* The reset value of the ALT_NAND_CFG_RE_2_RE_VALUE register field. */
3660 #define ALT_NAND_CFG_RE_2_RE_VALUE_RESET 0x32
3661 /* Extracts the ALT_NAND_CFG_RE_2_RE_VALUE field value from a register. */
3662 #define ALT_NAND_CFG_RE_2_RE_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
3663 /* Produces a ALT_NAND_CFG_RE_2_RE_VALUE register field value suitable for setting the register. */
3664 #define ALT_NAND_CFG_RE_2_RE_VALUE_SET(value) (((value) << 0) & 0x0000003f)
3665 
3666 #ifndef __ASSEMBLY__
3667 /*
3668  * WARNING: The C register and register group struct declarations are provided for
3669  * convenience and illustrative purposes. They should, however, be used with
3670  * caution as the C language standard provides no guarantees about the alignment or
3671  * atomicity of device memory accesses. The recommended practice for writing
3672  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3673  * alt_write_word() functions.
3674  *
3675  * The struct declaration for register ALT_NAND_CFG_RE_2_RE.
3676  */
3677 struct ALT_NAND_CFG_RE_2_RE_s
3678 {
3679  uint32_t value : 6; /* ALT_NAND_CFG_RE_2_RE_VALUE */
3680  uint32_t : 26; /* *UNDEFINED* */
3681 };
3682 
3683 /* The typedef declaration for register ALT_NAND_CFG_RE_2_RE. */
3684 typedef volatile struct ALT_NAND_CFG_RE_2_RE_s ALT_NAND_CFG_RE_2_RE_t;
3685 #endif /* __ASSEMBLY__ */
3686 
3687 /* The reset value of the ALT_NAND_CFG_RE_2_RE register. */
3688 #define ALT_NAND_CFG_RE_2_RE_RESET 0x00000032
3689 /* The byte offset of the ALT_NAND_CFG_RE_2_RE register from the beginning of the component. */
3690 #define ALT_NAND_CFG_RE_2_RE_OFST 0x290
3691 
3692 /*
3693  * Register : por_reset_count
3694  *
3695  * The number of cycles the controller waits after POR to issue the first RESET
3696  * command
3697  *
3698  * to the device.
3699  *
3700  * Register Layout
3701  *
3702  * Bits | Access | Reset | Description
3703  * :--------|:-------|:--------|:---------------------------------
3704  * [15:0] | RW | 0x13b | ALT_NAND_CFG_POR_RST_COUNT_VALUE
3705  * [31:16] | ??? | Unknown | *UNDEFINED*
3706  *
3707  */
3708 /*
3709  * Field : value
3710  *
3711  * The controller waits for this number of cycles before issuing the first
3712  *
3713  * RESET command to the device. The number in this register is multiplied
3714  *
3715  * internally by 16 in the controller to form the final reset wait count.
3716  *
3717  * Field Access Macros:
3718  *
3719  */
3720 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field. */
3721 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_LSB 0
3722 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field. */
3723 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_MSB 15
3724 /* The width in bits of the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field. */
3725 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_WIDTH 16
3726 /* The mask used to set the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field value. */
3727 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_SET_MSK 0x0000ffff
3728 /* The mask used to clear the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field value. */
3729 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_CLR_MSK 0xffff0000
3730 /* The reset value of the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field. */
3731 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_RESET 0x13b
3732 /* Extracts the ALT_NAND_CFG_POR_RST_COUNT_VALUE field value from a register. */
3733 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3734 /* Produces a ALT_NAND_CFG_POR_RST_COUNT_VALUE register field value suitable for setting the register. */
3735 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3736 
3737 #ifndef __ASSEMBLY__
3738 /*
3739  * WARNING: The C register and register group struct declarations are provided for
3740  * convenience and illustrative purposes. They should, however, be used with
3741  * caution as the C language standard provides no guarantees about the alignment or
3742  * atomicity of device memory accesses. The recommended practice for writing
3743  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3744  * alt_write_word() functions.
3745  *
3746  * The struct declaration for register ALT_NAND_CFG_POR_RST_COUNT.
3747  */
3748 struct ALT_NAND_CFG_POR_RST_COUNT_s
3749 {
3750  uint32_t value : 16; /* ALT_NAND_CFG_POR_RST_COUNT_VALUE */
3751  uint32_t : 16; /* *UNDEFINED* */
3752 };
3753 
3754 /* The typedef declaration for register ALT_NAND_CFG_POR_RST_COUNT. */
3755 typedef volatile struct ALT_NAND_CFG_POR_RST_COUNT_s ALT_NAND_CFG_POR_RST_COUNT_t;
3756 #endif /* __ASSEMBLY__ */
3757 
3758 /* The reset value of the ALT_NAND_CFG_POR_RST_COUNT register. */
3759 #define ALT_NAND_CFG_POR_RST_COUNT_RESET 0x0000013b
3760 /* The byte offset of the ALT_NAND_CFG_POR_RST_COUNT register from the beginning of the component. */
3761 #define ALT_NAND_CFG_POR_RST_COUNT_OFST 0x2a0
3762 
3763 /*
3764  * Register : watchdog_reset_count
3765  *
3766  * The number of cycles the controller waits before flagging a
3767  *
3768  * watchdog timeout interrupt.
3769  *
3770  * Register Layout
3771  *
3772  * Bits | Access | Reset | Description
3773  * :--------|:-------|:--------|:--------------------------------
3774  * [15:0] | RW | 0x5b9a | ALT_NAND_CFG_WD_RST_COUNT_VALUE
3775  * [31:16] | ??? | Unknown | *UNDEFINED*
3776  *
3777  */
3778 /*
3779  * Field : value
3780  *
3781  * The controller waits for this number of cycles before issuing
3782  *
3783  * a watchdog timeout interrupt. The value in this register is
3784  *
3785  * multiplied internally by 32 in the controller to form the final
3786  *
3787  * watchdog counter.
3788  *
3789  * Field Access Macros:
3790  *
3791  */
3792 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_WD_RST_COUNT_VALUE register field. */
3793 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_LSB 0
3794 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_WD_RST_COUNT_VALUE register field. */
3795 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_MSB 15
3796 /* The width in bits of the ALT_NAND_CFG_WD_RST_COUNT_VALUE register field. */
3797 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_WIDTH 16
3798 /* The mask used to set the ALT_NAND_CFG_WD_RST_COUNT_VALUE register field value. */
3799 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_SET_MSK 0x0000ffff
3800 /* The mask used to clear the ALT_NAND_CFG_WD_RST_COUNT_VALUE register field value. */
3801 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_CLR_MSK 0xffff0000
3802 /* The reset value of the ALT_NAND_CFG_WD_RST_COUNT_VALUE register field. */
3803 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_RESET 0x5b9a
3804 /* Extracts the ALT_NAND_CFG_WD_RST_COUNT_VALUE field value from a register. */
3805 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3806 /* Produces a ALT_NAND_CFG_WD_RST_COUNT_VALUE register field value suitable for setting the register. */
3807 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3808 
3809 #ifndef __ASSEMBLY__
3810 /*
3811  * WARNING: The C register and register group struct declarations are provided for
3812  * convenience and illustrative purposes. They should, however, be used with
3813  * caution as the C language standard provides no guarantees about the alignment or
3814  * atomicity of device memory accesses. The recommended practice for writing
3815  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3816  * alt_write_word() functions.
3817  *
3818  * The struct declaration for register ALT_NAND_CFG_WD_RST_COUNT.
3819  */
3820 struct ALT_NAND_CFG_WD_RST_COUNT_s
3821 {
3822  uint32_t value : 16; /* ALT_NAND_CFG_WD_RST_COUNT_VALUE */
3823  uint32_t : 16; /* *UNDEFINED* */
3824 };
3825 
3826 /* The typedef declaration for register ALT_NAND_CFG_WD_RST_COUNT. */
3827 typedef volatile struct ALT_NAND_CFG_WD_RST_COUNT_s ALT_NAND_CFG_WD_RST_COUNT_t;
3828 #endif /* __ASSEMBLY__ */
3829 
3830 /* The reset value of the ALT_NAND_CFG_WD_RST_COUNT register. */
3831 #define ALT_NAND_CFG_WD_RST_COUNT_RESET 0x00005b9a
3832 /* The byte offset of the ALT_NAND_CFG_WD_RST_COUNT register from the beginning of the component. */
3833 #define ALT_NAND_CFG_WD_RST_COUNT_OFST 0x2b0
3834 
3835 #ifndef __ASSEMBLY__
3836 /*
3837  * WARNING: The C register and register group struct declarations are provided for
3838  * convenience and illustrative purposes. They should, however, be used with
3839  * caution as the C language standard provides no guarantees about the alignment or
3840  * atomicity of device memory accesses. The recommended practice for writing
3841  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3842  * alt_write_word() functions.
3843  *
3844  * The struct declaration for register group ALT_NAND_CFG.
3845  */
3846 struct ALT_NAND_CFG_s
3847 {
3848  ALT_NAND_CFG_DEVICE_RST_t device_reset; /* ALT_NAND_CFG_DEVICE_RST */
3849  volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
3850  ALT_NAND_CFG_TFR_SPARE_REG_t transfer_spare_reg; /* ALT_NAND_CFG_TFR_SPARE_REG */
3851  volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
3852  ALT_NAND_CFG_LD_WAIT_CNT_t load_wait_cnt; /* ALT_NAND_CFG_LD_WAIT_CNT */
3853  volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
3854  ALT_NAND_CFG_PROGRAM_WAIT_CNT_t program_wait_cnt; /* ALT_NAND_CFG_PROGRAM_WAIT_CNT */
3855  volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
3856  ALT_NAND_CFG_ERASE_WAIT_CNT_t erase_wait_cnt; /* ALT_NAND_CFG_ERASE_WAIT_CNT */
3857  volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
3858  ALT_NAND_CFG_INT_MON_CYCCNT_t int_mon_cyccnt; /* ALT_NAND_CFG_INT_MON_CYCCNT */
3859  volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
3860  ALT_NAND_CFG_RB_PIN_END_t rb_pin_enabled; /* ALT_NAND_CFG_RB_PIN_END */
3861  volatile uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */
3862  ALT_NAND_CFG_MULTIPLANE_OP_t multiplane_operation; /* ALT_NAND_CFG_MULTIPLANE_OP */
3863  volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
3864  ALT_NAND_CFG_MULTIPLANE_RD_EN_t multiplane_read_enable; /* ALT_NAND_CFG_MULTIPLANE_RD_EN */
3865  volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
3866  ALT_NAND_CFG_COPYBACK_DIS_t copyback_disable; /* ALT_NAND_CFG_COPYBACK_DIS */
3867  volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
3868  ALT_NAND_CFG_CACHE_WR_EN_t cache_write_enable; /* ALT_NAND_CFG_CACHE_WR_EN */
3869  volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
3870  ALT_NAND_CFG_CACHE_RD_EN_t cache_read_enable; /* ALT_NAND_CFG_CACHE_RD_EN */
3871  volatile uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */
3872  ALT_NAND_CFG_PREFETCH_MOD_t prefetch_mode; /* ALT_NAND_CFG_PREFETCH_MOD */
3873  volatile uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */
3874  ALT_NAND_CFG_CHIP_EN_DONT_CARE_t chip_enable_dont_care; /* ALT_NAND_CFG_CHIP_EN_DONT_CARE */
3875  volatile uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */
3876  ALT_NAND_CFG_ECC_EN_t ecc_enable; /* ALT_NAND_CFG_ECC_EN */
3877  volatile uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */
3878  ALT_NAND_CFG_GLOB_INT_EN_t global_int_enable; /* ALT_NAND_CFG_GLOB_INT_EN */
3879  volatile uint32_t _pad_0xf4_0xff[3]; /* *UNDEFINED* */
3880  ALT_NAND_CFG_TWHR2_AND_WE_2_RE_t twhr2_and_we_2_re; /* ALT_NAND_CFG_TWHR2_AND_WE_2_RE */
3881  volatile uint32_t _pad_0x104_0x10f[3]; /* *UNDEFINED* */
3882  ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_t tcwaw_and_addr_2_data; /* ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA */
3883  volatile uint32_t _pad_0x114_0x11f[3]; /* *UNDEFINED* */
3884  ALT_NAND_CFG_RE_2_WE_t re_2_we; /* ALT_NAND_CFG_RE_2_WE */
3885  volatile uint32_t _pad_0x124_0x12f[3]; /* *UNDEFINED* */
3886  ALT_NAND_CFG_ACC_CLKS_t acc_clks; /* ALT_NAND_CFG_ACC_CLKS */
3887  volatile uint32_t _pad_0x134_0x13f[3]; /* *UNDEFINED* */
3888  ALT_NAND_CFG_NUMBER_OF_PLANES_t number_of_planes; /* ALT_NAND_CFG_NUMBER_OF_PLANES */
3889  volatile uint32_t _pad_0x144_0x14f[3]; /* *UNDEFINED* */
3890  ALT_NAND_CFG_PAGES_PER_BLOCK_t pages_per_block; /* ALT_NAND_CFG_PAGES_PER_BLOCK */
3891  volatile uint32_t _pad_0x154_0x15f[3]; /* *UNDEFINED* */
3892  ALT_NAND_CFG_DEVICE_WIDTH_t device_width; /* ALT_NAND_CFG_DEVICE_WIDTH */
3893  volatile uint32_t _pad_0x164_0x16f[3]; /* *UNDEFINED* */
3894  ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_t device_main_area_size; /* ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE */
3895  volatile uint32_t _pad_0x174_0x17f[3]; /* *UNDEFINED* */
3896  ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_t device_spare_area_size; /* ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE */
3897  volatile uint32_t _pad_0x184_0x18f[3]; /* *UNDEFINED* */
3898  ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_t two_row_addr_cycles; /* ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES */
3899  volatile uint32_t _pad_0x194_0x19f[3]; /* *UNDEFINED* */
3900  ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_t multiplane_addr_restrict; /* ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT */
3901  volatile uint32_t _pad_0x1a4_0x1af[3]; /* *UNDEFINED* */
3902  ALT_NAND_CFG_ECC_CORRECTION_t ecc_correction; /* ALT_NAND_CFG_ECC_CORRECTION */
3903  volatile uint32_t _pad_0x1b4_0x1bf[3]; /* *UNDEFINED* */
3904  ALT_NAND_CFG_RD_MOD_t read_mode; /* ALT_NAND_CFG_RD_MOD */
3905  volatile uint32_t _pad_0x1c4_0x1cf[3]; /* *UNDEFINED* */
3906  ALT_NAND_CFG_WR_MOD_t write_mode; /* ALT_NAND_CFG_WR_MOD */
3907  volatile uint32_t _pad_0x1d4_0x1df[3]; /* *UNDEFINED* */
3908  ALT_NAND_CFG_COPYBACK_MOD_t copyback_mode; /* ALT_NAND_CFG_COPYBACK_MOD */
3909  volatile uint32_t _pad_0x1e4_0x1ef[3]; /* *UNDEFINED* */
3910  ALT_NAND_CFG_RDWR_EN_LO_CNT_t rdwr_en_lo_cnt; /* ALT_NAND_CFG_RDWR_EN_LO_CNT */
3911  volatile uint32_t _pad_0x1f4_0x1ff[3]; /* *UNDEFINED* */
3912  ALT_NAND_CFG_RDWR_EN_HI_CNT_t rdwr_en_hi_cnt; /* ALT_NAND_CFG_RDWR_EN_HI_CNT */
3913  volatile uint32_t _pad_0x204_0x20f[3]; /* *UNDEFINED* */
3914  ALT_NAND_CFG_MAX_RD_DELAY_t max_rd_delay; /* ALT_NAND_CFG_MAX_RD_DELAY */
3915  volatile uint32_t _pad_0x214_0x21f[3]; /* *UNDEFINED* */
3916  ALT_NAND_CFG_CS_SETUP_CNT_t cs_setup_cnt; /* ALT_NAND_CFG_CS_SETUP_CNT */
3917  volatile uint32_t _pad_0x224_0x22f[3]; /* *UNDEFINED* */
3918  ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_t spare_area_skip_bytes; /* ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES */
3919  volatile uint32_t _pad_0x234_0x23f[3]; /* *UNDEFINED* */
3920  ALT_NAND_CFG_SPARE_AREA_MARKER_t spare_area_marker; /* ALT_NAND_CFG_SPARE_AREA_MARKER */
3921  volatile uint32_t _pad_0x244_0x24f[3]; /* *UNDEFINED* */
3922  ALT_NAND_CFG_DEVICES_CONNECTED_t devices_connected; /* ALT_NAND_CFG_DEVICES_CONNECTED */
3923  volatile uint32_t _pad_0x254_0x25f[3]; /* *UNDEFINED* */
3924  ALT_NAND_CFG_DIE_MSK_t die_mask; /* ALT_NAND_CFG_DIE_MSK */
3925  volatile uint32_t _pad_0x264_0x26f[3]; /* *UNDEFINED* */
3926  ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_t first_block_of_next_plane; /* ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE */
3927  volatile uint32_t _pad_0x274_0x27f[3]; /* *UNDEFINED* */
3928  ALT_NAND_CFG_WR_PROTECT_t write_protect; /* ALT_NAND_CFG_WR_PROTECT */
3929  volatile uint32_t _pad_0x284_0x28f[3]; /* *UNDEFINED* */
3930  ALT_NAND_CFG_RE_2_RE_t re_2_re; /* ALT_NAND_CFG_RE_2_RE */
3931  volatile uint32_t _pad_0x294_0x29f[3]; /* *UNDEFINED* */
3932  ALT_NAND_CFG_POR_RST_COUNT_t por_reset_count; /* ALT_NAND_CFG_POR_RST_COUNT */
3933  volatile uint32_t _pad_0x2a4_0x2af[3]; /* *UNDEFINED* */
3934  ALT_NAND_CFG_WD_RST_COUNT_t watchdog_reset_count; /* ALT_NAND_CFG_WD_RST_COUNT */
3935 };
3936 
3937 /* The typedef declaration for register group ALT_NAND_CFG. */
3938 typedef volatile struct ALT_NAND_CFG_s ALT_NAND_CFG_t;
3939 /* The struct declaration for the raw register contents of register group ALT_NAND_CFG. */
3940 struct ALT_NAND_CFG_raw_s
3941 {
3942  volatile uint32_t device_reset; /* ALT_NAND_CFG_DEVICE_RST */
3943  uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
3944  volatile uint32_t transfer_spare_reg; /* ALT_NAND_CFG_TFR_SPARE_REG */
3945  uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
3946  volatile uint32_t load_wait_cnt; /* ALT_NAND_CFG_LD_WAIT_CNT */
3947  uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
3948  volatile uint32_t program_wait_cnt; /* ALT_NAND_CFG_PROGRAM_WAIT_CNT */
3949  uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
3950  volatile uint32_t erase_wait_cnt; /* ALT_NAND_CFG_ERASE_WAIT_CNT */
3951  uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
3952  volatile uint32_t int_mon_cyccnt; /* ALT_NAND_CFG_INT_MON_CYCCNT */
3953  uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
3954  volatile uint32_t rb_pin_enabled; /* ALT_NAND_CFG_RB_PIN_END */
3955  uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */
3956  volatile uint32_t multiplane_operation; /* ALT_NAND_CFG_MULTIPLANE_OP */
3957  uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
3958  volatile uint32_t multiplane_read_enable; /* ALT_NAND_CFG_MULTIPLANE_RD_EN */
3959  uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
3960  volatile uint32_t copyback_disable; /* ALT_NAND_CFG_COPYBACK_DIS */
3961  uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
3962  volatile uint32_t cache_write_enable; /* ALT_NAND_CFG_CACHE_WR_EN */
3963  uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
3964  volatile uint32_t cache_read_enable; /* ALT_NAND_CFG_CACHE_RD_EN */
3965  uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */
3966  volatile uint32_t prefetch_mode; /* ALT_NAND_CFG_PREFETCH_MOD */
3967  uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */
3968  volatile uint32_t chip_enable_dont_care; /* ALT_NAND_CFG_CHIP_EN_DONT_CARE */
3969  uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */
3970  volatile uint32_t ecc_enable; /* ALT_NAND_CFG_ECC_EN */
3971  uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */
3972  volatile uint32_t global_int_enable; /* ALT_NAND_CFG_GLOB_INT_EN */
3973  uint32_t _pad_0xf4_0xff[3]; /* *UNDEFINED* */
3974  volatile uint32_t twhr2_and_we_2_re; /* ALT_NAND_CFG_TWHR2_AND_WE_2_RE */
3975  uint32_t _pad_0x104_0x10f[3]; /* *UNDEFINED* */
3976  volatile uint32_t tcwaw_and_addr_2_data; /* ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA */
3977  uint32_t _pad_0x114_0x11f[3]; /* *UNDEFINED* */
3978  volatile uint32_t re_2_we; /* ALT_NAND_CFG_RE_2_WE */
3979  uint32_t _pad_0x124_0x12f[3]; /* *UNDEFINED* */
3980  volatile uint32_t acc_clks; /* ALT_NAND_CFG_ACC_CLKS */
3981  uint32_t _pad_0x134_0x13f[3]; /* *UNDEFINED* */
3982  volatile uint32_t number_of_planes; /* ALT_NAND_CFG_NUMBER_OF_PLANES */
3983  uint32_t _pad_0x144_0x14f[3]; /* *UNDEFINED* */
3984  volatile uint32_t pages_per_block; /* ALT_NAND_CFG_PAGES_PER_BLOCK */
3985  uint32_t _pad_0x154_0x15f[3]; /* *UNDEFINED* */
3986  volatile uint32_t device_width; /* ALT_NAND_CFG_DEVICE_WIDTH */
3987  uint32_t _pad_0x164_0x16f[3]; /* *UNDEFINED* */
3988  volatile uint32_t device_main_area_size; /* ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE */
3989  uint32_t _pad_0x174_0x17f[3]; /* *UNDEFINED* */
3990  volatile uint32_t device_spare_area_size; /* ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE */
3991  uint32_t _pad_0x184_0x18f[3]; /* *UNDEFINED* */
3992  volatile uint32_t two_row_addr_cycles; /* ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES */
3993  uint32_t _pad_0x194_0x19f[3]; /* *UNDEFINED* */
3994  volatile uint32_t multiplane_addr_restrict; /* ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT */
3995  uint32_t _pad_0x1a4_0x1af[3]; /* *UNDEFINED* */
3996  volatile uint32_t ecc_correction; /* ALT_NAND_CFG_ECC_CORRECTION */
3997  uint32_t _pad_0x1b4_0x1bf[3]; /* *UNDEFINED* */
3998  volatile uint32_t read_mode; /* ALT_NAND_CFG_RD_MOD */
3999  uint32_t _pad_0x1c4_0x1cf[3]; /* *UNDEFINED* */
4000  volatile uint32_t write_mode; /* ALT_NAND_CFG_WR_MOD */
4001  uint32_t _pad_0x1d4_0x1df[3]; /* *UNDEFINED* */
4002  volatile uint32_t copyback_mode; /* ALT_NAND_CFG_COPYBACK_MOD */
4003  uint32_t _pad_0x1e4_0x1ef[3]; /* *UNDEFINED* */
4004  volatile uint32_t rdwr_en_lo_cnt; /* ALT_NAND_CFG_RDWR_EN_LO_CNT */
4005  uint32_t _pad_0x1f4_0x1ff[3]; /* *UNDEFINED* */
4006  volatile uint32_t rdwr_en_hi_cnt; /* ALT_NAND_CFG_RDWR_EN_HI_CNT */
4007  uint32_t _pad_0x204_0x20f[3]; /* *UNDEFINED* */
4008  volatile uint32_t max_rd_delay; /* ALT_NAND_CFG_MAX_RD_DELAY */
4009  uint32_t _pad_0x214_0x21f[3]; /* *UNDEFINED* */
4010  volatile uint32_t cs_setup_cnt; /* ALT_NAND_CFG_CS_SETUP_CNT */
4011  uint32_t _pad_0x224_0x22f[3]; /* *UNDEFINED* */
4012  volatile uint32_t spare_area_skip_bytes; /* ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES */
4013  uint32_t _pad_0x234_0x23f[3]; /* *UNDEFINED* */
4014  volatile uint32_t spare_area_marker; /* ALT_NAND_CFG_SPARE_AREA_MARKER */
4015  uint32_t _pad_0x244_0x24f[3]; /* *UNDEFINED* */
4016  volatile uint32_t devices_connected; /* ALT_NAND_CFG_DEVICES_CONNECTED */
4017  uint32_t _pad_0x254_0x25f[3]; /* *UNDEFINED* */
4018  volatile uint32_t die_mask; /* ALT_NAND_CFG_DIE_MSK */
4019  uint32_t _pad_0x264_0x26f[3]; /* *UNDEFINED* */
4020  volatile uint32_t first_block_of_next_plane; /* ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE */
4021  uint32_t _pad_0x274_0x27f[3]; /* *UNDEFINED* */
4022  volatile uint32_t write_protect; /* ALT_NAND_CFG_WR_PROTECT */
4023  uint32_t _pad_0x284_0x28f[3]; /* *UNDEFINED* */
4024  volatile uint32_t re_2_re; /* ALT_NAND_CFG_RE_2_RE */
4025  uint32_t _pad_0x294_0x29f[3]; /* *UNDEFINED* */
4026  volatile uint32_t por_reset_count; /* ALT_NAND_CFG_POR_RST_COUNT */
4027  uint32_t _pad_0x2a4_0x2af[3]; /* *UNDEFINED* */
4028  volatile uint32_t watchdog_reset_count; /* ALT_NAND_CFG_WD_RST_COUNT */
4029 };
4030 
4031 /* The typedef declaration for the raw register contents of register group ALT_NAND_CFG. */
4032 typedef volatile struct ALT_NAND_CFG_raw_s ALT_NAND_CFG_raw_t;
4033 #endif /* __ASSEMBLY__ */
4034 
4035 
4036 /*
4037  * Component : ALT_NAND_PARAM
4038  *
4039  */
4040 /*
4041  * Register : manufacturer_id
4042  *
4043  * Register Layout
4044  *
4045  * Bits | Access | Reset | Description
4046  * :-------|:-------|:--------|:-------------------------------------
4047  * [7:0] | RW | 0x0 | ALT_NAND_PARAM_MANUFACTURER_ID_VALUE
4048  * [31:8] | ??? | Unknown | *UNDEFINED*
4049  *
4050  */
4051 /*
4052  * Field : value
4053  *
4054  * Manufacturer ID
4055  *
4056  * Field Access Macros:
4057  *
4058  */
4059 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field. */
4060 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_LSB 0
4061 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field. */
4062 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_MSB 7
4063 /* The width in bits of the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field. */
4064 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_WIDTH 8
4065 /* The mask used to set the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field value. */
4066 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_SET_MSK 0x000000ff
4067 /* The mask used to clear the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field value. */
4068 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_CLR_MSK 0xffffff00
4069 /* The reset value of the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field. */
4070 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_RESET 0x0
4071 /* Extracts the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE field value from a register. */
4072 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4073 /* Produces a ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field value suitable for setting the register. */
4074 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4075 
4076 #ifndef __ASSEMBLY__
4077 /*
4078  * WARNING: The C register and register group struct declarations are provided for
4079  * convenience and illustrative purposes. They should, however, be used with
4080  * caution as the C language standard provides no guarantees about the alignment or
4081  * atomicity of device memory accesses. The recommended practice for writing
4082  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4083  * alt_write_word() functions.
4084  *
4085  * The struct declaration for register ALT_NAND_PARAM_MANUFACTURER_ID.
4086  */
4087 struct ALT_NAND_PARAM_MANUFACTURER_ID_s
4088 {
4089  uint32_t value : 8; /* ALT_NAND_PARAM_MANUFACTURER_ID_VALUE */
4090  uint32_t : 24; /* *UNDEFINED* */
4091 };
4092 
4093 /* The typedef declaration for register ALT_NAND_PARAM_MANUFACTURER_ID. */
4094 typedef volatile struct ALT_NAND_PARAM_MANUFACTURER_ID_s ALT_NAND_PARAM_MANUFACTURER_ID_t;
4095 #endif /* __ASSEMBLY__ */
4096 
4097 /* The reset value of the ALT_NAND_PARAM_MANUFACTURER_ID register. */
4098 #define ALT_NAND_PARAM_MANUFACTURER_ID_RESET 0x00000000
4099 /* The byte offset of the ALT_NAND_PARAM_MANUFACTURER_ID register from the beginning of the component. */
4100 #define ALT_NAND_PARAM_MANUFACTURER_ID_OFST 0x0
4101 
4102 /*
4103  * Register : device_id
4104  *
4105  * Register Layout
4106  *
4107  * Bits | Access | Reset | Description
4108  * :-------|:-------|:--------|:-------------------------------
4109  * [7:0] | R | 0x0 | ALT_NAND_PARAM_DEVICE_ID_VALUE
4110  * [31:8] | ??? | Unknown | *UNDEFINED*
4111  *
4112  */
4113 /*
4114  * Field : value
4115  *
4116  * Device ID
4117  *
4118  * Field Access Macros:
4119  *
4120  */
4121 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_DEVICE_ID_VALUE register field. */
4122 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_LSB 0
4123 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_DEVICE_ID_VALUE register field. */
4124 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_MSB 7
4125 /* The width in bits of the ALT_NAND_PARAM_DEVICE_ID_VALUE register field. */
4126 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_WIDTH 8
4127 /* The mask used to set the ALT_NAND_PARAM_DEVICE_ID_VALUE register field value. */
4128 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_SET_MSK 0x000000ff
4129 /* The mask used to clear the ALT_NAND_PARAM_DEVICE_ID_VALUE register field value. */
4130 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_CLR_MSK 0xffffff00
4131 /* The reset value of the ALT_NAND_PARAM_DEVICE_ID_VALUE register field. */
4132 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_RESET 0x0
4133 /* Extracts the ALT_NAND_PARAM_DEVICE_ID_VALUE field value from a register. */
4134 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4135 /* Produces a ALT_NAND_PARAM_DEVICE_ID_VALUE register field value suitable for setting the register. */
4136 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4137 
4138 #ifndef __ASSEMBLY__
4139 /*
4140  * WARNING: The C register and register group struct declarations are provided for
4141  * convenience and illustrative purposes. They should, however, be used with
4142  * caution as the C language standard provides no guarantees about the alignment or
4143  * atomicity of device memory accesses. The recommended practice for writing
4144  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4145  * alt_write_word() functions.
4146  *
4147  * The struct declaration for register ALT_NAND_PARAM_DEVICE_ID.
4148  */
4149 struct ALT_NAND_PARAM_DEVICE_ID_s
4150 {
4151  const uint32_t value : 8; /* ALT_NAND_PARAM_DEVICE_ID_VALUE */
4152  uint32_t : 24; /* *UNDEFINED* */
4153 };
4154 
4155 /* The typedef declaration for register ALT_NAND_PARAM_DEVICE_ID. */
4156 typedef volatile struct ALT_NAND_PARAM_DEVICE_ID_s ALT_NAND_PARAM_DEVICE_ID_t;
4157 #endif /* __ASSEMBLY__ */
4158 
4159 /* The reset value of the ALT_NAND_PARAM_DEVICE_ID register. */
4160 #define ALT_NAND_PARAM_DEVICE_ID_RESET 0x00000000
4161 /* The byte offset of the ALT_NAND_PARAM_DEVICE_ID register from the beginning of the component. */
4162 #define ALT_NAND_PARAM_DEVICE_ID_OFST 0x10
4163 
4164 /*
4165  * Register : device_param_0
4166  *
4167  * Register Layout
4168  *
4169  * Bits | Access | Reset | Description
4170  * :-------|:-------|:--------|:------------------------------------
4171  * [7:0] | R | 0x0 | ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE
4172  * [31:8] | ??? | Unknown | *UNDEFINED*
4173  *
4174  */
4175 /*
4176  * Field : value
4177  *
4178  * 3rd byte relating to Device Signature. This register is
4179  *
4180  * updated only for Legacy NAND devices.
4181  *
4182  * Field Access Macros:
4183  *
4184  */
4185 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field. */
4186 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_LSB 0
4187 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field. */
4188 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_MSB 7
4189 /* The width in bits of the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field. */
4190 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_WIDTH 8
4191 /* The mask used to set the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field value. */
4192 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_SET_MSK 0x000000ff
4193 /* The mask used to clear the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field value. */
4194 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_CLR_MSK 0xffffff00
4195 /* The reset value of the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field. */
4196 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_RESET 0x0
4197 /* Extracts the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE field value from a register. */
4198 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4199 /* Produces a ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field value suitable for setting the register. */
4200 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4201 
4202 #ifndef __ASSEMBLY__
4203 /*
4204  * WARNING: The C register and register group struct declarations are provided for
4205  * convenience and illustrative purposes. They should, however, be used with
4206  * caution as the C language standard provides no guarantees about the alignment or
4207  * atomicity of device memory accesses. The recommended practice for writing
4208  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4209  * alt_write_word() functions.
4210  *
4211  * The struct declaration for register ALT_NAND_PARAM_DEVICE_PARAM_0.
4212  */
4213 struct ALT_NAND_PARAM_DEVICE_PARAM_0_s
4214 {
4215  const uint32_t value : 8; /* ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE */
4216  uint32_t : 24; /* *UNDEFINED* */
4217 };
4218 
4219 /* The typedef declaration for register ALT_NAND_PARAM_DEVICE_PARAM_0. */
4220 typedef volatile struct ALT_NAND_PARAM_DEVICE_PARAM_0_s ALT_NAND_PARAM_DEVICE_PARAM_0_t;
4221 #endif /* __ASSEMBLY__ */
4222 
4223 /* The reset value of the ALT_NAND_PARAM_DEVICE_PARAM_0 register. */
4224 #define ALT_NAND_PARAM_DEVICE_PARAM_0_RESET 0x00000000
4225 /* The byte offset of the ALT_NAND_PARAM_DEVICE_PARAM_0 register from the beginning of the component. */
4226 #define ALT_NAND_PARAM_DEVICE_PARAM_0_OFST 0x20
4227 
4228 /*
4229  * Register : device_param_1
4230  *
4231  * Register Layout
4232  *
4233  * Bits | Access | Reset | Description
4234  * :-------|:-------|:--------|:------------------------------------
4235  * [7:0] | R | 0x0 | ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE
4236  * [31:8] | ??? | Unknown | *UNDEFINED*
4237  *
4238  */
4239 /*
4240  * Field : value
4241  *
4242  * 4th byte relating to Device Signature. This register is
4243  *
4244  * updated only for Legacy NAND devices.
4245  *
4246  * Field Access Macros:
4247  *
4248  */
4249 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field. */
4250 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_LSB 0
4251 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field. */
4252 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_MSB 7
4253 /* The width in bits of the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field. */
4254 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_WIDTH 8
4255 /* The mask used to set the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field value. */
4256 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_SET_MSK 0x000000ff
4257 /* The mask used to clear the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field value. */
4258 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_CLR_MSK 0xffffff00
4259 /* The reset value of the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field. */
4260 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_RESET 0x0
4261 /* Extracts the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE field value from a register. */
4262 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4263 /* Produces a ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field value suitable for setting the register. */
4264 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4265 
4266 #ifndef __ASSEMBLY__
4267 /*
4268  * WARNING: The C register and register group struct declarations are provided for
4269  * convenience and illustrative purposes. They should, however, be used with
4270  * caution as the C language standard provides no guarantees about the alignment or
4271  * atomicity of device memory accesses. The recommended practice for writing
4272  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4273  * alt_write_word() functions.
4274  *
4275  * The struct declaration for register ALT_NAND_PARAM_DEVICE_PARAM_1.
4276  */
4277 struct ALT_NAND_PARAM_DEVICE_PARAM_1_s
4278 {
4279  const uint32_t value : 8; /* ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE */
4280  uint32_t : 24; /* *UNDEFINED* */
4281 };
4282 
4283 /* The typedef declaration for register ALT_NAND_PARAM_DEVICE_PARAM_1. */
4284 typedef volatile struct ALT_NAND_PARAM_DEVICE_PARAM_1_s ALT_NAND_PARAM_DEVICE_PARAM_1_t;
4285 #endif /* __ASSEMBLY__ */
4286 
4287 /* The reset value of the ALT_NAND_PARAM_DEVICE_PARAM_1 register. */
4288 #define ALT_NAND_PARAM_DEVICE_PARAM_1_RESET 0x00000000
4289 /* The byte offset of the ALT_NAND_PARAM_DEVICE_PARAM_1 register from the beginning of the component. */
4290 #define ALT_NAND_PARAM_DEVICE_PARAM_1_OFST 0x30
4291 
4292 /*
4293  * Register : device_param_2
4294  *
4295  * Register Layout
4296  *
4297  * Bits | Access | Reset | Description
4298  * :-------|:-------|:--------|:------------------------------------
4299  * [7:0] | R | 0x0 | ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE
4300  * [31:8] | ??? | Unknown | *UNDEFINED*
4301  *
4302  */
4303 /*
4304  * Field : value
4305  *
4306  * Reserved.
4307  *
4308  * Field Access Macros:
4309  *
4310  */
4311 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field. */
4312 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_LSB 0
4313 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field. */
4314 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_MSB 7
4315 /* The width in bits of the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field. */
4316 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_WIDTH 8
4317 /* The mask used to set the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field value. */
4318 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_SET_MSK 0x000000ff
4319 /* The mask used to clear the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field value. */
4320 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_CLR_MSK 0xffffff00
4321 /* The reset value of the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field. */
4322 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_RESET 0x0
4323 /* Extracts the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE field value from a register. */
4324 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4325 /* Produces a ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field value suitable for setting the register. */
4326 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4327 
4328 #ifndef __ASSEMBLY__
4329 /*
4330  * WARNING: The C register and register group struct declarations are provided for
4331  * convenience and illustrative purposes. They should, however, be used with
4332  * caution as the C language standard provides no guarantees about the alignment or
4333  * atomicity of device memory accesses. The recommended practice for writing
4334  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4335  * alt_write_word() functions.
4336  *
4337  * The struct declaration for register ALT_NAND_PARAM_DEVICE_PARAM_2.
4338  */
4339 struct ALT_NAND_PARAM_DEVICE_PARAM_2_s
4340 {
4341  const uint32_t value : 8; /* ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE */
4342  uint32_t : 24; /* *UNDEFINED* */
4343 };
4344 
4345 /* The typedef declaration for register ALT_NAND_PARAM_DEVICE_PARAM_2. */
4346 typedef volatile struct ALT_NAND_PARAM_DEVICE_PARAM_2_s ALT_NAND_PARAM_DEVICE_PARAM_2_t;
4347 #endif /* __ASSEMBLY__ */
4348 
4349 /* The reset value of the ALT_NAND_PARAM_DEVICE_PARAM_2 register. */
4350 #define ALT_NAND_PARAM_DEVICE_PARAM_2_RESET 0x00000000
4351 /* The byte offset of the ALT_NAND_PARAM_DEVICE_PARAM_2 register from the beginning of the component. */
4352 #define ALT_NAND_PARAM_DEVICE_PARAM_2_OFST 0x40
4353 
4354 /*
4355  * Register : logical_page_data_size
4356  *
4357  * Logical page data area size in bytes
4358  *
4359  * Register Layout
4360  *
4361  * Bits | Access | Reset | Description
4362  * :--------|:-------|:--------|:--------------------------------------------
4363  * [15:0] | R | 0x0 | ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE
4364  * [31:16] | ??? | Unknown | *UNDEFINED*
4365  *
4366  */
4367 /*
4368  * Field : value
4369  *
4370  * Logical page spare area size in bytes. If multiple devices are
4371  *
4372  * connected on a single chip select, physical page data size will be
4373  *
4374  * multiplied by the number of devices to arrive at logical page size.
4375  *
4376  * Field Access Macros:
4377  *
4378  */
4379 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field. */
4380 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_LSB 0
4381 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field. */
4382 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_MSB 15
4383 /* The width in bits of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field. */
4384 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_WIDTH 16
4385 /* The mask used to set the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field value. */
4386 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_SET_MSK 0x0000ffff
4387 /* The mask used to clear the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field value. */
4388 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_CLR_MSK 0xffff0000
4389 /* The reset value of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field. */
4390 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_RESET 0x0
4391 /* Extracts the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE field value from a register. */
4392 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4393 /* Produces a ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field value suitable for setting the register. */
4394 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4395 
4396 #ifndef __ASSEMBLY__
4397 /*
4398  * WARNING: The C register and register group struct declarations are provided for
4399  * convenience and illustrative purposes. They should, however, be used with
4400  * caution as the C language standard provides no guarantees about the alignment or
4401  * atomicity of device memory accesses. The recommended practice for writing
4402  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4403  * alt_write_word() functions.
4404  *
4405  * The struct declaration for register ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE.
4406  */
4407 struct ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_s
4408 {
4409  const uint32_t value : 16; /* ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE */
4410  uint32_t : 16; /* *UNDEFINED* */
4411 };
4412 
4413 /* The typedef declaration for register ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE. */
4414 typedef volatile struct ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_s ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_t;
4415 #endif /* __ASSEMBLY__ */
4416 
4417 /* The reset value of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE register. */
4418 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_RESET 0x00000000
4419 /* The byte offset of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE register from the beginning of the component. */
4420 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_OFST 0x50
4421 
4422 /*
4423  * Register : logical_page_spare_size
4424  *
4425  * Logical page data area size in bytes
4426  *
4427  * Register Layout
4428  *
4429  * Bits | Access | Reset | Description
4430  * :--------|:-------|:--------|:---------------------------------------------
4431  * [15:0] | R | 0x0 | ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE
4432  * [31:16] | ??? | Unknown | *UNDEFINED*
4433  *
4434  */
4435 /*
4436  * Field : value
4437  *
4438  * Logical page spare area size in bytes. If multiple devices are
4439  *
4440  * connected on a single chip select, physical page spare size will be
4441  *
4442  * multiplied by the number of devices to arrive at logical page size.
4443  *
4444  * Field Access Macros:
4445  *
4446  */
4447 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field. */
4448 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_LSB 0
4449 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field. */
4450 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_MSB 15
4451 /* The width in bits of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field. */
4452 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_WIDTH 16
4453 /* The mask used to set the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field value. */
4454 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_SET_MSK 0x0000ffff
4455 /* The mask used to clear the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field value. */
4456 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_CLR_MSK 0xffff0000
4457 /* The reset value of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field. */
4458 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_RESET 0x0
4459 /* Extracts the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE field value from a register. */
4460 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4461 /* Produces a ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field value suitable for setting the register. */
4462 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4463 
4464 #ifndef __ASSEMBLY__
4465 /*
4466  * WARNING: The C register and register group struct declarations are provided for
4467  * convenience and illustrative purposes. They should, however, be used with
4468  * caution as the C language standard provides no guarantees about the alignment or
4469  * atomicity of device memory accesses. The recommended practice for writing
4470  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4471  * alt_write_word() functions.
4472  *
4473  * The struct declaration for register ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE.
4474  */
4475 struct ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_s
4476 {
4477  const uint32_t value : 16; /* ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE */
4478  uint32_t : 16; /* *UNDEFINED* */
4479 };
4480 
4481 /* The typedef declaration for register ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE. */
4482 typedef volatile struct ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_s ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_t;
4483 #endif /* __ASSEMBLY__ */
4484 
4485 /* The reset value of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE register. */
4486 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_RESET 0x00000000
4487 /* The byte offset of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE register from the beginning of the component. */
4488 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_OFST 0x60
4489 
4490 /*
4491  * Register : revision
4492  *
4493  * Controller Revision
4494  *
4495  * Register Layout
4496  *
4497  * Bits | Access | Reset | Description
4498  * :--------|:-------|:--------|:------------------------------
4499  * [7:0] | R | 0x5 | ALT_NAND_PARAM_REVISION_VALUE
4500  * [15:8] | R | 0x1 | ALT_NAND_PARAM_REVISION_MINOR
4501  * [31:16] | ??? | Unknown | *UNDEFINED*
4502  *
4503  */
4504 /*
4505  * Field : value
4506  *
4507  * The Major revision number of the controller
4508  *
4509  * Field Access Macros:
4510  *
4511  */
4512 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_REVISION_VALUE register field. */
4513 #define ALT_NAND_PARAM_REVISION_VALUE_LSB 0
4514 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_REVISION_VALUE register field. */
4515 #define ALT_NAND_PARAM_REVISION_VALUE_MSB 7
4516 /* The width in bits of the ALT_NAND_PARAM_REVISION_VALUE register field. */
4517 #define ALT_NAND_PARAM_REVISION_VALUE_WIDTH 8
4518 /* The mask used to set the ALT_NAND_PARAM_REVISION_VALUE register field value. */
4519 #define ALT_NAND_PARAM_REVISION_VALUE_SET_MSK 0x000000ff
4520 /* The mask used to clear the ALT_NAND_PARAM_REVISION_VALUE register field value. */
4521 #define ALT_NAND_PARAM_REVISION_VALUE_CLR_MSK 0xffffff00
4522 /* The reset value of the ALT_NAND_PARAM_REVISION_VALUE register field. */
4523 #define ALT_NAND_PARAM_REVISION_VALUE_RESET 0x5
4524 /* Extracts the ALT_NAND_PARAM_REVISION_VALUE field value from a register. */
4525 #define ALT_NAND_PARAM_REVISION_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4526 /* Produces a ALT_NAND_PARAM_REVISION_VALUE register field value suitable for setting the register. */
4527 #define ALT_NAND_PARAM_REVISION_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4528 
4529 /*
4530  * Field : minor
4531  *
4532  * The Minor revision number of the controller
4533  *
4534  * Field Access Macros:
4535  *
4536  */
4537 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_REVISION_MINOR register field. */
4538 #define ALT_NAND_PARAM_REVISION_MINOR_LSB 8
4539 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_REVISION_MINOR register field. */
4540 #define ALT_NAND_PARAM_REVISION_MINOR_MSB 15
4541 /* The width in bits of the ALT_NAND_PARAM_REVISION_MINOR register field. */
4542 #define ALT_NAND_PARAM_REVISION_MINOR_WIDTH 8
4543 /* The mask used to set the ALT_NAND_PARAM_REVISION_MINOR register field value. */
4544 #define ALT_NAND_PARAM_REVISION_MINOR_SET_MSK 0x0000ff00
4545 /* The mask used to clear the ALT_NAND_PARAM_REVISION_MINOR register field value. */
4546 #define ALT_NAND_PARAM_REVISION_MINOR_CLR_MSK 0xffff00ff
4547 /* The reset value of the ALT_NAND_PARAM_REVISION_MINOR register field. */
4548 #define ALT_NAND_PARAM_REVISION_MINOR_RESET 0x1
4549 /* Extracts the ALT_NAND_PARAM_REVISION_MINOR field value from a register. */
4550 #define ALT_NAND_PARAM_REVISION_MINOR_GET(value) (((value) & 0x0000ff00) >> 8)
4551 /* Produces a ALT_NAND_PARAM_REVISION_MINOR register field value suitable for setting the register. */
4552 #define ALT_NAND_PARAM_REVISION_MINOR_SET(value) (((value) << 8) & 0x0000ff00)
4553 
4554 #ifndef __ASSEMBLY__
4555 /*
4556  * WARNING: The C register and register group struct declarations are provided for
4557  * convenience and illustrative purposes. They should, however, be used with
4558  * caution as the C language standard provides no guarantees about the alignment or
4559  * atomicity of device memory accesses. The recommended practice for writing
4560  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4561  * alt_write_word() functions.
4562  *
4563  * The struct declaration for register ALT_NAND_PARAM_REVISION.
4564  */
4565 struct ALT_NAND_PARAM_REVISION_s
4566 {
4567  const uint32_t value : 8; /* ALT_NAND_PARAM_REVISION_VALUE */
4568  const uint32_t minor : 8; /* ALT_NAND_PARAM_REVISION_MINOR */
4569  uint32_t : 16; /* *UNDEFINED* */
4570 };
4571 
4572 /* The typedef declaration for register ALT_NAND_PARAM_REVISION. */
4573 typedef volatile struct ALT_NAND_PARAM_REVISION_s ALT_NAND_PARAM_REVISION_t;
4574 #endif /* __ASSEMBLY__ */
4575 
4576 /* The reset value of the ALT_NAND_PARAM_REVISION register. */
4577 #define ALT_NAND_PARAM_REVISION_RESET 0x00000105
4578 /* The byte offset of the ALT_NAND_PARAM_REVISION register from the beginning of the component. */
4579 #define ALT_NAND_PARAM_REVISION_OFST 0x70
4580 
4581 /*
4582  * Register : onfi_device_features
4583  *
4584  * Features supported by the connected ONFI device
4585  *
4586  * Register Layout
4587  *
4588  * Bits | Access | Reset | Description
4589  * :--------|:-------|:--------|:---------------------------------------
4590  * [15:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE
4591  * [31:16] | ??? | Unknown | *UNDEFINED*
4592  *
4593  */
4594 /*
4595  * Field : value
4596  *
4597  * The values in the field should be interpreted as follows[list]
4598  *
4599  * [*]Bit 0 - Supports 16 bit data bus width.
4600  *
4601  * [*]Bit 1 - Supports multiple LUN operations.
4602  *
4603  * [*]Bit 2 - Supports non-sequential page programming.
4604  *
4605  * [*]Bit 3 - Supports interleaved program and erase operations.
4606  *
4607  * [*]Bit 4 - Supports odd to even page copyback.
4608  *
4609  * [*]Bit 5 - Supports source synchronous.
4610  *
4611  * [*]Bit 6 - Supports interleaved read operations.
4612  *
4613  * [*]Bit 7 - Supports extended parameter page.
4614  *
4615  * [*]Bit 8 - Supports program page register clear enhancement.
4616  *
4617  * [*]Bit 9 - Supports EZNAND.
4618  *
4619  * [*]Bit 10 - Supports NV-DDR2.
4620  *
4621  * [*]Bit 11 - Supports Volume Addressing.
4622  *
4623  * [*]Bit 12 - Supports External Vpp.
4624  *
4625  * [*]Bit 13-15 - Reserved.[/list]
4626  *
4627  * Field Access Macros:
4628  *
4629  */
4630 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE register field. */
4631 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_LSB 0
4632 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE register field. */
4633 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_MSB 15
4634 /* The width in bits of the ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE register field. */
4635 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_WIDTH 16
4636 /* The mask used to set the ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE register field value. */
4637 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_SET_MSK 0x0000ffff
4638 /* The mask used to clear the ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE register field value. */
4639 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_CLR_MSK 0xffff0000
4640 /* The reset value of the ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE register field. */
4641 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_RESET 0x0
4642 /* Extracts the ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE field value from a register. */
4643 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4644 /* Produces a ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE register field value suitable for setting the register. */
4645 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4646 
4647 #ifndef __ASSEMBLY__
4648 /*
4649  * WARNING: The C register and register group struct declarations are provided for
4650  * convenience and illustrative purposes. They should, however, be used with
4651  * caution as the C language standard provides no guarantees about the alignment or
4652  * atomicity of device memory accesses. The recommended practice for writing
4653  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4654  * alt_write_word() functions.
4655  *
4656  * The struct declaration for register ALT_NAND_PARAM_ONFI_DEV_FEATURES.
4657  */
4658 struct ALT_NAND_PARAM_ONFI_DEV_FEATURES_s
4659 {
4660  const uint32_t value : 16; /* ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE */
4661  uint32_t : 16; /* *UNDEFINED* */
4662 };
4663 
4664 /* The typedef declaration for register ALT_NAND_PARAM_ONFI_DEV_FEATURES. */
4665 typedef volatile struct ALT_NAND_PARAM_ONFI_DEV_FEATURES_s ALT_NAND_PARAM_ONFI_DEV_FEATURES_t;
4666 #endif /* __ASSEMBLY__ */
4667 
4668 /* The reset value of the ALT_NAND_PARAM_ONFI_DEV_FEATURES register. */
4669 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_RESET 0x00000000
4670 /* The byte offset of the ALT_NAND_PARAM_ONFI_DEV_FEATURES register from the beginning of the component. */
4671 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_OFST 0x80
4672 
4673 /*
4674  * Register : onfi_optional_commands
4675  *
4676  * Optional commands supported by the connected ONFI device
4677  *
4678  * Register Layout
4679  *
4680  * Bits | Access | Reset | Description
4681  * :--------|:-------|:--------|:----------------------------------------
4682  * [15:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE
4683  * [31:16] | ??? | Unknown | *UNDEFINED*
4684  *
4685  */
4686 /*
4687  * Field : value
4688  *
4689  * The values in the field should be interpreted as follows[list]
4690  *
4691  * [*]Bit 0 - Supports page cache program command.
4692  *
4693  * [*]Bit 1 - Supports read cache commands.
4694  *
4695  * [*]Bit 2 - Supports get and set features.
4696  *
4697  * [*]Bit 3 - Supports read status enhanced commands.
4698  *
4699  * [*]Bit 4 - Supports copyback.
4700  *
4701  * [*]Bit 5 - Supports Read Unique Id.
4702  *
4703  * [*]Bit 6 - Supports Change Read Column Enhanced.
4704  *
4705  * [*]Bit 7 - Supports change row address.
4706  *
4707  * [*]Bit 8 - Supports Change small data move.
4708  *
4709  * [*]Bit 9 - Supports RESET LUN.
4710  *
4711  * [*]Bit 10 - Supports Volume Select.
4712  *
4713  * [*]Bit 11 - Supports ODT Configure.
4714  *
4715  * [*]Bit 12-15 - Reserved.[/list]
4716  *
4717  * Field Access Macros:
4718  *
4719  */
4720 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE register field. */
4721 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_LSB 0
4722 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE register field. */
4723 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_MSB 15
4724 /* The width in bits of the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE register field. */
4725 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_WIDTH 16
4726 /* The mask used to set the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE register field value. */
4727 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_SET_MSK 0x0000ffff
4728 /* The mask used to clear the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE register field value. */
4729 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_CLR_MSK 0xffff0000
4730 /* The reset value of the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE register field. */
4731 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_RESET 0x0
4732 /* Extracts the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE field value from a register. */
4733 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4734 /* Produces a ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE register field value suitable for setting the register. */
4735 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4736 
4737 #ifndef __ASSEMBLY__
4738 /*
4739  * WARNING: The C register and register group struct declarations are provided for
4740  * convenience and illustrative purposes. They should, however, be used with
4741  * caution as the C language standard provides no guarantees about the alignment or
4742  * atomicity of device memory accesses. The recommended practice for writing
4743  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4744  * alt_write_word() functions.
4745  *
4746  * The struct declaration for register ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS.
4747  */
4748 struct ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_s
4749 {
4750  const uint32_t value : 16; /* ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE */
4751  uint32_t : 16; /* *UNDEFINED* */
4752 };
4753 
4754 /* The typedef declaration for register ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS. */
4755 typedef volatile struct ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_s ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_t;
4756 #endif /* __ASSEMBLY__ */
4757 
4758 /* The reset value of the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS register. */
4759 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_RESET 0x00000000
4760 /* The byte offset of the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS register from the beginning of the component. */
4761 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_OFST 0x90
4762 
4763 /*
4764  * Register : onfi_timing_mode
4765  *
4766  * Asynchronous Timing modes supported by the connected ONFI device
4767  *
4768  * Register Layout
4769  *
4770  * Bits | Access | Reset | Description
4771  * :-------|:-------|:--------|:-------------------------------------
4772  * [5:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE
4773  * [31:6] | ??? | Unknown | *UNDEFINED*
4774  *
4775  */
4776 /*
4777  * Field : value
4778  *
4779  * The values in the field should be interpreted as follows[list]
4780  *
4781  * [*]Bit 0 - Supports Timing mode 0.
4782  *
4783  * [*]Bit 1 - Supports Timing mode 1.
4784  *
4785  * [*]Bit 2 - Supports Timing mode 2.
4786  *
4787  * [*]Bit 3 - Supports Timing mode 3.
4788  *
4789  * [*]Bit 4 - Supports Timing mode 4.
4790  *
4791  * [*]Bit 5 - Supports Timing mode 5.[/list]
4792  *
4793  * Field Access Macros:
4794  *
4795  */
4796 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field. */
4797 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_LSB 0
4798 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field. */
4799 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_MSB 5
4800 /* The width in bits of the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field. */
4801 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_WIDTH 6
4802 /* The mask used to set the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field value. */
4803 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_SET_MSK 0x0000003f
4804 /* The mask used to clear the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field value. */
4805 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_CLR_MSK 0xffffffc0
4806 /* The reset value of the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field. */
4807 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_RESET 0x0
4808 /* Extracts the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE field value from a register. */
4809 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
4810 /* Produces a ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field value suitable for setting the register. */
4811 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_SET(value) (((value) << 0) & 0x0000003f)
4812 
4813 #ifndef __ASSEMBLY__
4814 /*
4815  * WARNING: The C register and register group struct declarations are provided for
4816  * convenience and illustrative purposes. They should, however, be used with
4817  * caution as the C language standard provides no guarantees about the alignment or
4818  * atomicity of device memory accesses. The recommended practice for writing
4819  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4820  * alt_write_word() functions.
4821  *
4822  * The struct declaration for register ALT_NAND_PARAM_ONFI_TIMING_MOD.
4823  */
4824 struct ALT_NAND_PARAM_ONFI_TIMING_MOD_s
4825 {
4826  const uint32_t value : 6; /* ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE */
4827  uint32_t : 26; /* *UNDEFINED* */
4828 };
4829 
4830 /* The typedef declaration for register ALT_NAND_PARAM_ONFI_TIMING_MOD. */
4831 typedef volatile struct ALT_NAND_PARAM_ONFI_TIMING_MOD_s ALT_NAND_PARAM_ONFI_TIMING_MOD_t;
4832 #endif /* __ASSEMBLY__ */
4833 
4834 /* The reset value of the ALT_NAND_PARAM_ONFI_TIMING_MOD register. */
4835 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_RESET 0x00000000
4836 /* The byte offset of the ALT_NAND_PARAM_ONFI_TIMING_MOD register from the beginning of the component. */
4837 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_OFST 0xa0
4838 
4839 /*
4840  * Register : onfi_pgm_cache_timing_mode
4841  *
4842  * Asynchronous Program Cache Timing modes supported by the connected ONFI device
4843  *
4844  * Register Layout
4845  *
4846  * Bits | Access | Reset | Description
4847  * :-------|:-------|:--------|:-----------------------------------------------
4848  * [5:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE
4849  * [31:6] | ??? | Unknown | *UNDEFINED*
4850  *
4851  */
4852 /*
4853  * Field : value
4854  *
4855  * The values in the field should be interpreted as follows[list]
4856  *
4857  * [*]Bit 0 - Supports Timing mode 0.
4858  *
4859  * [*]Bit 1 - Supports Timing mode 1.
4860  *
4861  * [*]Bit 2 - Supports Timing mode 2.
4862  *
4863  * [*]Bit 3 - Supports Timing mode 3.
4864  *
4865  * [*]Bit 4 - Supports Timing mode 4.
4866  *
4867  * [*]Bit 5 - Supports Timing mode 5.[/list]
4868  *
4869  * Field Access Macros:
4870  *
4871  */
4872 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE register field. */
4873 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_LSB 0
4874 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE register field. */
4875 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_MSB 5
4876 /* The width in bits of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE register field. */
4877 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_WIDTH 6
4878 /* The mask used to set the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE register field value. */
4879 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_SET_MSK 0x0000003f
4880 /* The mask used to clear the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE register field value. */
4881 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_CLR_MSK 0xffffffc0
4882 /* The reset value of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE register field. */
4883 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_RESET 0x0
4884 /* Extracts the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE field value from a register. */
4885 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
4886 /* Produces a ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE register field value suitable for setting the register. */
4887 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_SET(value) (((value) << 0) & 0x0000003f)
4888 
4889 #ifndef __ASSEMBLY__
4890 /*
4891  * WARNING: The C register and register group struct declarations are provided for
4892  * convenience and illustrative purposes. They should, however, be used with
4893  * caution as the C language standard provides no guarantees about the alignment or
4894  * atomicity of device memory accesses. The recommended practice for writing
4895  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4896  * alt_write_word() functions.
4897  *
4898  * The struct declaration for register ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD.
4899  */
4900 struct ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_s
4901 {
4902  const uint32_t value : 6; /* ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE */
4903  uint32_t : 26; /* *UNDEFINED* */
4904 };
4905 
4906 /* The typedef declaration for register ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD. */
4907 typedef volatile struct ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_s ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_t;
4908 #endif /* __ASSEMBLY__ */
4909 
4910 /* The reset value of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD register. */
4911 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_RESET 0x00000000
4912 /* The byte offset of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD register from the beginning of the component. */
4913 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_OFST 0xb0
4914 
4915 /*
4916  * Register : onfi_device_no_of_luns
4917  *
4918  * Indicates if the device is an ONFI compliant device and the number
4919  *
4920  * of LUNS present in the device
4921  *
4922  * Register Layout
4923  *
4924  * Bits | Access | Reset | Description
4925  * :--------|:-------|:--------|:-----------------------------------------------------------------------
4926  * [7:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS
4927  * [8] | RW | 0x0 | ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE
4928  * [11:9] | ??? | Unknown | *UNDEFINED*
4929  * [12] | RW | 0x0 | ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT
4930  * [15:13] | ??? | Unknown | *UNDEFINED*
4931  * [16] | RW | 0x0 | ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ
4932  * [19:17] | ??? | Unknown | *UNDEFINED*
4933  * [20] | RW | 0x0 | ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE
4934  * [31:21] | ??? | Unknown | *UNDEFINED*
4935  *
4936  */
4937 /*
4938  * Field : no_of_luns
4939  *
4940  * Indicates the number of LUNS present in the device
4941  *
4942  * Field Access Macros:
4943  *
4944  */
4945 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS register field. */
4946 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_LSB 0
4947 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS register field. */
4948 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_MSB 7
4949 /* The width in bits of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS register field. */
4950 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_WIDTH 8
4951 /* The mask used to set the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS register field value. */
4952 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_SET_MSK 0x000000ff
4953 /* The mask used to clear the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS register field value. */
4954 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_CLR_MSK 0xffffff00
4955 /* The reset value of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS register field. */
4956 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_RESET 0x0
4957 /* Extracts the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS field value from a register. */
4958 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_GET(value) (((value) & 0x000000ff) >> 0)
4959 /* Produces a ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS register field value suitable for setting the register. */
4960 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_SET(value) (((value) << 0) & 0x000000ff)
4961 
4962 /*
4963  * Field : onfi_device
4964  *
4965  * Indicates if the device is an ONFI compliant device.[list]
4966  *
4967  * [*]0 - Non-ONFI compliant device
4968  *
4969  * [*]1 - ONFI compliant device[/list]
4970  *
4971  * Field Access Macros:
4972  *
4973  */
4974 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE register field. */
4975 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_LSB 8
4976 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE register field. */
4977 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_MSB 8
4978 /* The width in bits of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE register field. */
4979 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_WIDTH 1
4980 /* The mask used to set the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE register field value. */
4981 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_SET_MSK 0x00000100
4982 /* The mask used to clear the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE register field value. */
4983 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_CLR_MSK 0xfffffeff
4984 /* The reset value of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE register field. */
4985 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_RESET 0x0
4986 /* Extracts the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE field value from a register. */
4987 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_GET(value) (((value) & 0x00000100) >> 8)
4988 /* Produces a ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE register field value suitable for setting the register. */
4989 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_SET(value) (((value) << 8) & 0x00000100)
4990 
4991 /*
4992  * Field : prog_page_reg_clear_enhancement
4993  *
4994  * Device supports program page register clear enhancement.In such a device,
4995  *
4996  * a program can be initiated in a LUN even if a read command is ongoing in
4997  *
4998  * another LUN in the device.
4999  *
5000  * [list][*]1 - Program page register clear enhancement supported
5001  *
5002  * [*]0 - Program page register clear enhancement not supported[/list]
5003  *
5004  * Field Access Macros:
5005  *
5006  */
5007 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT register field. */
5008 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_LSB 12
5009 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT register field. */
5010 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_MSB 12
5011 /* The width in bits of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT register field. */
5012 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_WIDTH 1
5013 /* The mask used to set the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT register field value. */
5014 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_SET_MSK 0x00001000
5015 /* The mask used to clear the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT register field value. */
5016 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_CLR_MSK 0xffffefff
5017 /* The reset value of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT register field. */
5018 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_RESET 0x0
5019 /* Extracts the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT field value from a register. */
5020 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_GET(value) (((value) & 0x00001000) >> 12)
5021 /* Produces a ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT register field value suitable for setting the register. */
5022 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_SET(value) (((value) << 12) & 0x00001000)
5023 
5024 /*
5025  * Field : onfi_jedec_multiplane_erase_seq
5026  *
5027  * Device supports ONFI JEDEC Multiplane erase sequence.(Only valid for Onfi
5028  * devices)
5029  *
5030  * [list][*]1 - ONFI JEDEC Multiplane erase sequence supported
5031  *
5032  * [*]0 - ONFI JEDEC Multiplane erase sequence not supported[/list]
5033  *
5034  * Field Access Macros:
5035  *
5036  */
5037 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ register field. */
5038 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_LSB 16
5039 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ register field. */
5040 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_MSB 16
5041 /* The width in bits of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ register field. */
5042 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_WIDTH 1
5043 /* The mask used to set the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ register field value. */
5044 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_SET_MSK 0x00010000
5045 /* The mask used to clear the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ register field value. */
5046 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_CLR_MSK 0xfffeffff
5047 /* The reset value of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ register field. */
5048 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_RESET 0x0
5049 /* Extracts the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ field value from a register. */
5050 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_GET(value) (((value) & 0x00010000) >> 16)
5051 /* Produces a ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ register field value suitable for setting the register. */
5052 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_SET(value) (((value) << 16) & 0x00010000)
5053 
5054 /*
5055  * Field : ce_reduction_volume_addr_and_change
5056  *
5057  * Device supports CE pin reduction with volume assignments,volume addressing
5058  *
5059  * and volume change command sequence.For any device configured by host to be used
5060  * in
5061  *
5062  * volume addressing mode, this bit must be set to 1.
5063  *
5064  * [list][*]1 - supported [*]0 - Not supported[/list]
5065  *
5066  * Field Access Macros:
5067  *
5068  */
5069 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE register field. */
5070 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_LSB 20
5071 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE register field. */
5072 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_MSB 20
5073 /* The width in bits of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE register field. */
5074 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_WIDTH 1
5075 /* The mask used to set the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE register field value. */
5076 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_SET_MSK 0x00100000
5077 /* The mask used to clear the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE register field value. */
5078 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_CLR_MSK 0xffefffff
5079 /* The reset value of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE register field. */
5080 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_RESET 0x0
5081 /* Extracts the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE field value from a register. */
5082 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_GET(value) (((value) & 0x00100000) >> 20)
5083 /* Produces a ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE register field value suitable for setting the register. */
5084 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_SET(value) (((value) << 20) & 0x00100000)
5085 
5086 #ifndef __ASSEMBLY__
5087 /*
5088  * WARNING: The C register and register group struct declarations are provided for
5089  * convenience and illustrative purposes. They should, however, be used with
5090  * caution as the C language standard provides no guarantees about the alignment or
5091  * atomicity of device memory accesses. The recommended practice for writing
5092  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5093  * alt_write_word() functions.
5094  *
5095  * The struct declaration for register ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS.
5096  */
5097 struct ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_s
5098 {
5099  const uint32_t no_of_luns : 8; /* ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS */
5100  uint32_t onfi_device : 1; /* ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE */
5101  uint32_t : 3; /* *UNDEFINED* */
5102  uint32_t prog_page_reg_clear_enhancement : 1; /* ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT */
5103  uint32_t : 3; /* *UNDEFINED* */
5104  uint32_t onfi_jedec_multiplane_erase_seq : 1; /* ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ */
5105  uint32_t : 3; /* *UNDEFINED* */
5106  uint32_t ce_reduction_volume_addr_and_change : 1; /* ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE */
5107  uint32_t : 11; /* *UNDEFINED* */
5108 };
5109 
5110 /* The typedef declaration for register ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS. */
5111 typedef volatile struct ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_s ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_t;
5112 #endif /* __ASSEMBLY__ */
5113 
5114 /* The reset value of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS register. */
5115 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_RESET 0x00000000
5116 /* The byte offset of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS register from the beginning of the component. */
5117 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_OFST 0xc0
5118 
5119 /*
5120  * Register : onfi_device_no_of_blocks_per_lun_l
5121  *
5122  * Lower bits of number of blocks per LUN present in
5123  *
5124  * the ONFI complaint device.
5125  *
5126  * Register Layout
5127  *
5128  * Bits | Access | Reset | Description
5129  * :--------|:-------|:--------|:---------------------------------------------
5130  * [15:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE
5131  * [31:16] | ??? | Unknown | *UNDEFINED*
5132  *
5133  */
5134 /*
5135  * Field : value
5136  *
5137  * Indicates the lower bits of number of blocks per
5138  *
5139  * LUN present in the ONFI complaint device.
5140  *
5141  * Field Access Macros:
5142  *
5143  */
5144 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE register field. */
5145 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_LSB 0
5146 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE register field. */
5147 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_MSB 15
5148 /* The width in bits of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE register field. */
5149 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_WIDTH 16
5150 /* The mask used to set the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE register field value. */
5151 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_SET_MSK 0x0000ffff
5152 /* The mask used to clear the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE register field value. */
5153 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_CLR_MSK 0xffff0000
5154 /* The reset value of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE register field. */
5155 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_RESET 0x0
5156 /* Extracts the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE field value from a register. */
5157 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
5158 /* Produces a ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE register field value suitable for setting the register. */
5159 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
5160 
5161 #ifndef __ASSEMBLY__
5162 /*
5163  * WARNING: The C register and register group struct declarations are provided for
5164  * convenience and illustrative purposes. They should, however, be used with
5165  * caution as the C language standard provides no guarantees about the alignment or
5166  * atomicity of device memory accesses. The recommended practice for writing
5167  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5168  * alt_write_word() functions.
5169  *
5170  * The struct declaration for register ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L.
5171  */
5172 struct ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_s
5173 {
5174  const uint32_t value : 16; /* ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE */
5175  uint32_t : 16; /* *UNDEFINED* */
5176 };
5177 
5178 /* The typedef declaration for register ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L. */
5179 typedef volatile struct ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_s ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_t;
5180 #endif /* __ASSEMBLY__ */
5181 
5182 /* The reset value of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L register. */
5183 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_RESET 0x00000000
5184 /* The byte offset of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L register from the beginning of the component. */
5185 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_OFST 0xd0
5186 
5187 /*
5188  * Register : onfi_device_no_of_blocks_per_lun_u
5189  *
5190  * Upper bits of number of blocks per LUN present in
5191  *
5192  * the ONFI complaint device.
5193  *
5194  * Register Layout
5195  *
5196  * Bits | Access | Reset | Description
5197  * :--------|:-------|:--------|:---------------------------------------------
5198  * [15:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE
5199  * [31:16] | ??? | Unknown | *UNDEFINED*
5200  *
5201  */
5202 /*
5203  * Field : value
5204  *
5205  * Indicates the upper bits of number of blocks per
5206  *
5207  * LUN present in the ONFI complaint device.
5208  *
5209  * Field Access Macros:
5210  *
5211  */
5212 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE register field. */
5213 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_LSB 0
5214 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE register field. */
5215 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_MSB 15
5216 /* The width in bits of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE register field. */
5217 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_WIDTH 16
5218 /* The mask used to set the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE register field value. */
5219 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_SET_MSK 0x0000ffff
5220 /* The mask used to clear the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE register field value. */
5221 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_CLR_MSK 0xffff0000
5222 /* The reset value of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE register field. */
5223 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_RESET 0x0
5224 /* Extracts the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE field value from a register. */
5225 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
5226 /* Produces a ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE register field value suitable for setting the register. */
5227 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
5228 
5229 #ifndef __ASSEMBLY__
5230 /*
5231  * WARNING: The C register and register group struct declarations are provided for
5232  * convenience and illustrative purposes. They should, however, be used with
5233  * caution as the C language standard provides no guarantees about the alignment or
5234  * atomicity of device memory accesses. The recommended practice for writing
5235  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5236  * alt_write_word() functions.
5237  *
5238  * The struct declaration for register ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U.
5239  */
5240 struct ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_s
5241 {
5242  const uint32_t value : 16; /* ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE */
5243  uint32_t : 16; /* *UNDEFINED* */
5244 };
5245 
5246 /* The typedef declaration for register ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U. */
5247 typedef volatile struct ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_s ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_t;
5248 #endif /* __ASSEMBLY__ */
5249 
5250 /* The reset value of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U register. */
5251 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_RESET 0x00000000
5252 /* The byte offset of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U register from the beginning of the component. */
5253 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_OFST 0xe0
5254 
5255 /*
5256  * Register : features
5257  *
5258  * Shows Available hardware features or attributes
5259  *
5260  * Register Layout
5261  *
5262  * Bits | Access | Reset | Description
5263  * :--------|:-------|:--------|:--------------------------------------
5264  * [1:0] | R | 0x2 | ALT_NAND_PARAM_FEATURES_N_BANKS
5265  * [5:2] | ??? | Unknown | *UNDEFINED*
5266  * [6] | R | 0x1 | ALT_NAND_PARAM_FEATURES_DMA
5267  * [7] | R | 0x1 | ALT_NAND_PARAM_FEATURES_CMD_DMA
5268  * [8] | R | 0x0 | ALT_NAND_PARAM_FEATURES_PARTITION
5269  * [9] | R | 0x0 | ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND
5270  * [10] | R | 0x0 | ALT_NAND_PARAM_FEATURES_GPREG
5271  * [11] | R | 0x1 | ALT_NAND_PARAM_FEATURES_INDEX_ADDR
5272  * [12] | R | 0x0 | ALT_NAND_PARAM_FEATURES_DFI_INTF
5273  * [13] | R | 0x0 | ALT_NAND_PARAM_FEATURES_LBA
5274  * [31:14] | ??? | Unknown | *UNDEFINED*
5275  *
5276  */
5277 /*
5278  * Field : n_banks
5279  *
5280  * Maximum number of banks supported by hardware. This is an
5281  *
5282  * encoded value.
5283  *
5284  * [list][*]0 - One bank
5285  *
5286  * [*]1 - Two banks
5287  *
5288  * [*]2 - Four banks
5289  *
5290  * [*]3 - Eight banks[/list]
5291  *
5292  * Field Access Macros:
5293  *
5294  */
5295 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_N_BANKS register field. */
5296 #define ALT_NAND_PARAM_FEATURES_N_BANKS_LSB 0
5297 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_N_BANKS register field. */
5298 #define ALT_NAND_PARAM_FEATURES_N_BANKS_MSB 1
5299 /* The width in bits of the ALT_NAND_PARAM_FEATURES_N_BANKS register field. */
5300 #define ALT_NAND_PARAM_FEATURES_N_BANKS_WIDTH 2
5301 /* The mask used to set the ALT_NAND_PARAM_FEATURES_N_BANKS register field value. */
5302 #define ALT_NAND_PARAM_FEATURES_N_BANKS_SET_MSK 0x00000003
5303 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_N_BANKS register field value. */
5304 #define ALT_NAND_PARAM_FEATURES_N_BANKS_CLR_MSK 0xfffffffc
5305 /* The reset value of the ALT_NAND_PARAM_FEATURES_N_BANKS register field. */
5306 #define ALT_NAND_PARAM_FEATURES_N_BANKS_RESET 0x2
5307 /* Extracts the ALT_NAND_PARAM_FEATURES_N_BANKS field value from a register. */
5308 #define ALT_NAND_PARAM_FEATURES_N_BANKS_GET(value) (((value) & 0x00000003) >> 0)
5309 /* Produces a ALT_NAND_PARAM_FEATURES_N_BANKS register field value suitable for setting the register. */
5310 #define ALT_NAND_PARAM_FEATURES_N_BANKS_SET(value) (((value) << 0) & 0x00000003)
5311 
5312 /*
5313  * Field : dma
5314  *
5315  * if set, DATA-DMA is present in hardware.
5316  *
5317  * Field Access Macros:
5318  *
5319  */
5320 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_DMA register field. */
5321 #define ALT_NAND_PARAM_FEATURES_DMA_LSB 6
5322 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_DMA register field. */
5323 #define ALT_NAND_PARAM_FEATURES_DMA_MSB 6
5324 /* The width in bits of the ALT_NAND_PARAM_FEATURES_DMA register field. */
5325 #define ALT_NAND_PARAM_FEATURES_DMA_WIDTH 1
5326 /* The mask used to set the ALT_NAND_PARAM_FEATURES_DMA register field value. */
5327 #define ALT_NAND_PARAM_FEATURES_DMA_SET_MSK 0x00000040
5328 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_DMA register field value. */
5329 #define ALT_NAND_PARAM_FEATURES_DMA_CLR_MSK 0xffffffbf
5330 /* The reset value of the ALT_NAND_PARAM_FEATURES_DMA register field. */
5331 #define ALT_NAND_PARAM_FEATURES_DMA_RESET 0x1
5332 /* Extracts the ALT_NAND_PARAM_FEATURES_DMA field value from a register. */
5333 #define ALT_NAND_PARAM_FEATURES_DMA_GET(value) (((value) & 0x00000040) >> 6)
5334 /* Produces a ALT_NAND_PARAM_FEATURES_DMA register field value suitable for setting the register. */
5335 #define ALT_NAND_PARAM_FEATURES_DMA_SET(value) (((value) << 6) & 0x00000040)
5336 
5337 /*
5338  * Field : cmd_dma
5339  *
5340  * if set, CMD-DMA is present in hardware.
5341  *
5342  * Field Access Macros:
5343  *
5344  */
5345 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_CMD_DMA register field. */
5346 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_LSB 7
5347 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_CMD_DMA register field. */
5348 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_MSB 7
5349 /* The width in bits of the ALT_NAND_PARAM_FEATURES_CMD_DMA register field. */
5350 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_WIDTH 1
5351 /* The mask used to set the ALT_NAND_PARAM_FEATURES_CMD_DMA register field value. */
5352 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_SET_MSK 0x00000080
5353 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_CMD_DMA register field value. */
5354 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_CLR_MSK 0xffffff7f
5355 /* The reset value of the ALT_NAND_PARAM_FEATURES_CMD_DMA register field. */
5356 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_RESET 0x1
5357 /* Extracts the ALT_NAND_PARAM_FEATURES_CMD_DMA field value from a register. */
5358 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_GET(value) (((value) & 0x00000080) >> 7)
5359 /* Produces a ALT_NAND_PARAM_FEATURES_CMD_DMA register field value suitable for setting the register. */
5360 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_SET(value) (((value) << 7) & 0x00000080)
5361 
5362 /*
5363  * Field : partition
5364  *
5365  * if set, Partition logic is present in hardware.
5366  *
5367  * Field Access Macros:
5368  *
5369  */
5370 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_PARTITION register field. */
5371 #define ALT_NAND_PARAM_FEATURES_PARTITION_LSB 8
5372 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_PARTITION register field. */
5373 #define ALT_NAND_PARAM_FEATURES_PARTITION_MSB 8
5374 /* The width in bits of the ALT_NAND_PARAM_FEATURES_PARTITION register field. */
5375 #define ALT_NAND_PARAM_FEATURES_PARTITION_WIDTH 1
5376 /* The mask used to set the ALT_NAND_PARAM_FEATURES_PARTITION register field value. */
5377 #define ALT_NAND_PARAM_FEATURES_PARTITION_SET_MSK 0x00000100
5378 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_PARTITION register field value. */
5379 #define ALT_NAND_PARAM_FEATURES_PARTITION_CLR_MSK 0xfffffeff
5380 /* The reset value of the ALT_NAND_PARAM_FEATURES_PARTITION register field. */
5381 #define ALT_NAND_PARAM_FEATURES_PARTITION_RESET 0x0
5382 /* Extracts the ALT_NAND_PARAM_FEATURES_PARTITION field value from a register. */
5383 #define ALT_NAND_PARAM_FEATURES_PARTITION_GET(value) (((value) & 0x00000100) >> 8)
5384 /* Produces a ALT_NAND_PARAM_FEATURES_PARTITION register field value suitable for setting the register. */
5385 #define ALT_NAND_PARAM_FEATURES_PARTITION_SET(value) (((value) << 8) & 0x00000100)
5386 
5387 /*
5388  * Field : xdma_sideband
5389  *
5390  * if set, Side band DMA signals are present in hardware.
5391  *
5392  * Field Access Macros:
5393  *
5394  */
5395 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field. */
5396 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_LSB 9
5397 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field. */
5398 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_MSB 9
5399 /* The width in bits of the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field. */
5400 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_WIDTH 1
5401 /* The mask used to set the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field value. */
5402 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_SET_MSK 0x00000200
5403 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field value. */
5404 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_CLR_MSK 0xfffffdff
5405 /* The reset value of the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field. */
5406 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_RESET 0x0
5407 /* Extracts the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND field value from a register. */
5408 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_GET(value) (((value) & 0x00000200) >> 9)
5409 /* Produces a ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field value suitable for setting the register. */
5410 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_SET(value) (((value) << 9) & 0x00000200)
5411 
5412 /*
5413  * Field : gpreg
5414  *
5415  * if set, General purpose registers are is present in hardware.
5416  *
5417  * Field Access Macros:
5418  *
5419  */
5420 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_GPREG register field. */
5421 #define ALT_NAND_PARAM_FEATURES_GPREG_LSB 10
5422 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_GPREG register field. */
5423 #define ALT_NAND_PARAM_FEATURES_GPREG_MSB 10
5424 /* The width in bits of the ALT_NAND_PARAM_FEATURES_GPREG register field. */
5425 #define ALT_NAND_PARAM_FEATURES_GPREG_WIDTH 1
5426 /* The mask used to set the ALT_NAND_PARAM_FEATURES_GPREG register field value. */
5427 #define ALT_NAND_PARAM_FEATURES_GPREG_SET_MSK 0x00000400
5428 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_GPREG register field value. */
5429 #define ALT_NAND_PARAM_FEATURES_GPREG_CLR_MSK 0xfffffbff
5430 /* The reset value of the ALT_NAND_PARAM_FEATURES_GPREG register field. */
5431 #define ALT_NAND_PARAM_FEATURES_GPREG_RESET 0x0
5432 /* Extracts the ALT_NAND_PARAM_FEATURES_GPREG field value from a register. */
5433 #define ALT_NAND_PARAM_FEATURES_GPREG_GET(value) (((value) & 0x00000400) >> 10)
5434 /* Produces a ALT_NAND_PARAM_FEATURES_GPREG register field value suitable for setting the register. */
5435 #define ALT_NAND_PARAM_FEATURES_GPREG_SET(value) (((value) << 10) & 0x00000400)
5436 
5437 /*
5438  * Field : index_addr
5439  *
5440  * if set, hardware support only Indexed addressing.
5441  *
5442  * Field Access Macros:
5443  *
5444  */
5445 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field. */
5446 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_LSB 11
5447 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field. */
5448 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_MSB 11
5449 /* The width in bits of the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field. */
5450 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_WIDTH 1
5451 /* The mask used to set the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field value. */
5452 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_SET_MSK 0x00000800
5453 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field value. */
5454 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_CLR_MSK 0xfffff7ff
5455 /* The reset value of the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field. */
5456 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_RESET 0x1
5457 /* Extracts the ALT_NAND_PARAM_FEATURES_INDEX_ADDR field value from a register. */
5458 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_GET(value) (((value) & 0x00000800) >> 11)
5459 /* Produces a ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field value suitable for setting the register. */
5460 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_SET(value) (((value) << 11) & 0x00000800)
5461 
5462 /*
5463  * Field : dfi_intf
5464  *
5465  * if set, hardware supports ONFI2.x synchronous interface.
5466  *
5467  * Field Access Macros:
5468  *
5469  */
5470 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_DFI_INTF register field. */
5471 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_LSB 12
5472 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_DFI_INTF register field. */
5473 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_MSB 12
5474 /* The width in bits of the ALT_NAND_PARAM_FEATURES_DFI_INTF register field. */
5475 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_WIDTH 1
5476 /* The mask used to set the ALT_NAND_PARAM_FEATURES_DFI_INTF register field value. */
5477 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_SET_MSK 0x00001000
5478 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_DFI_INTF register field value. */
5479 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_CLR_MSK 0xffffefff
5480 /* The reset value of the ALT_NAND_PARAM_FEATURES_DFI_INTF register field. */
5481 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_RESET 0x0
5482 /* Extracts the ALT_NAND_PARAM_FEATURES_DFI_INTF field value from a register. */
5483 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_GET(value) (((value) & 0x00001000) >> 12)
5484 /* Produces a ALT_NAND_PARAM_FEATURES_DFI_INTF register field value suitable for setting the register. */
5485 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_SET(value) (((value) << 12) & 0x00001000)
5486 
5487 /*
5488  * Field : lba
5489  *
5490  * if set, hardware supports Toshiba LBA devices.
5491  *
5492  * Field Access Macros:
5493  *
5494  */
5495 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_LBA register field. */
5496 #define ALT_NAND_PARAM_FEATURES_LBA_LSB 13
5497 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_LBA register field. */
5498 #define ALT_NAND_PARAM_FEATURES_LBA_MSB 13
5499 /* The width in bits of the ALT_NAND_PARAM_FEATURES_LBA register field. */
5500 #define ALT_NAND_PARAM_FEATURES_LBA_WIDTH 1
5501 /* The mask used to set the ALT_NAND_PARAM_FEATURES_LBA register field value. */
5502 #define ALT_NAND_PARAM_FEATURES_LBA_SET_MSK 0x00002000
5503 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_LBA register field value. */
5504 #define ALT_NAND_PARAM_FEATURES_LBA_CLR_MSK 0xffffdfff
5505 /* The reset value of the ALT_NAND_PARAM_FEATURES_LBA register field. */
5506 #define ALT_NAND_PARAM_FEATURES_LBA_RESET 0x0
5507 /* Extracts the ALT_NAND_PARAM_FEATURES_LBA field value from a register. */
5508 #define ALT_NAND_PARAM_FEATURES_LBA_GET(value) (((value) & 0x00002000) >> 13)
5509 /* Produces a ALT_NAND_PARAM_FEATURES_LBA register field value suitable for setting the register. */
5510 #define ALT_NAND_PARAM_FEATURES_LBA_SET(value) (((value) << 13) & 0x00002000)
5511 
5512 #ifndef __ASSEMBLY__
5513 /*
5514  * WARNING: The C register and register group struct declarations are provided for
5515  * convenience and illustrative purposes. They should, however, be used with
5516  * caution as the C language standard provides no guarantees about the alignment or
5517  * atomicity of device memory accesses. The recommended practice for writing
5518  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5519  * alt_write_word() functions.
5520  *
5521  * The struct declaration for register ALT_NAND_PARAM_FEATURES.
5522  */
5523 struct ALT_NAND_PARAM_FEATURES_s
5524 {
5525  const uint32_t n_banks : 2; /* ALT_NAND_PARAM_FEATURES_N_BANKS */
5526  uint32_t : 4; /* *UNDEFINED* */
5527  const uint32_t dma : 1; /* ALT_NAND_PARAM_FEATURES_DMA */
5528  const uint32_t cmd_dma : 1; /* ALT_NAND_PARAM_FEATURES_CMD_DMA */
5529  const uint32_t partition : 1; /* ALT_NAND_PARAM_FEATURES_PARTITION */
5530  const uint32_t xdma_sideband : 1; /* ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND */
5531  const uint32_t gpreg : 1; /* ALT_NAND_PARAM_FEATURES_GPREG */
5532  const uint32_t index_addr : 1; /* ALT_NAND_PARAM_FEATURES_INDEX_ADDR */
5533  const uint32_t dfi_intf : 1; /* ALT_NAND_PARAM_FEATURES_DFI_INTF */
5534  const uint32_t lba : 1; /* ALT_NAND_PARAM_FEATURES_LBA */
5535  uint32_t : 18; /* *UNDEFINED* */
5536 };
5537 
5538 /* The typedef declaration for register ALT_NAND_PARAM_FEATURES. */
5539 typedef volatile struct ALT_NAND_PARAM_FEATURES_s ALT_NAND_PARAM_FEATURES_t;
5540 #endif /* __ASSEMBLY__ */
5541 
5542 /* The reset value of the ALT_NAND_PARAM_FEATURES register. */
5543 #define ALT_NAND_PARAM_FEATURES_RESET 0x000008c2
5544 /* The byte offset of the ALT_NAND_PARAM_FEATURES register from the beginning of the component. */
5545 #define ALT_NAND_PARAM_FEATURES_OFST 0xf0
5546 
5547 #ifndef __ASSEMBLY__
5548 /*
5549  * WARNING: The C register and register group struct declarations are provided for
5550  * convenience and illustrative purposes. They should, however, be used with
5551  * caution as the C language standard provides no guarantees about the alignment or
5552  * atomicity of device memory accesses. The recommended practice for writing
5553  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5554  * alt_write_word() functions.
5555  *
5556  * The struct declaration for register group ALT_NAND_PARAM.
5557  */
5558 struct ALT_NAND_PARAM_s
5559 {
5560  ALT_NAND_PARAM_MANUFACTURER_ID_t manufacturer_id; /* ALT_NAND_PARAM_MANUFACTURER_ID */
5561  volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
5562  ALT_NAND_PARAM_DEVICE_ID_t device_id; /* ALT_NAND_PARAM_DEVICE_ID */
5563  volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
5564  ALT_NAND_PARAM_DEVICE_PARAM_0_t device_param_0; /* ALT_NAND_PARAM_DEVICE_PARAM_0 */
5565  volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
5566  ALT_NAND_PARAM_DEVICE_PARAM_1_t device_param_1; /* ALT_NAND_PARAM_DEVICE_PARAM_1 */
5567  volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
5568  ALT_NAND_PARAM_DEVICE_PARAM_2_t device_param_2; /* ALT_NAND_PARAM_DEVICE_PARAM_2 */
5569  volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
5570  ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_t logical_page_data_size; /* ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE */
5571  volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
5572  ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_t logical_page_spare_size; /* ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE */
5573  volatile uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */
5574  ALT_NAND_PARAM_REVISION_t revision; /* ALT_NAND_PARAM_REVISION */
5575  volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
5576  ALT_NAND_PARAM_ONFI_DEV_FEATURES_t onfi_device_features; /* ALT_NAND_PARAM_ONFI_DEV_FEATURES */
5577  volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
5578  ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_t onfi_optional_commands; /* ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS */
5579  volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
5580  ALT_NAND_PARAM_ONFI_TIMING_MOD_t onfi_timing_mode; /* ALT_NAND_PARAM_ONFI_TIMING_MOD */
5581  volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
5582  ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_t onfi_pgm_cache_timing_mode; /* ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD */
5583  volatile uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */
5584  ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_t onfi_device_no_of_luns; /* ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS */
5585  volatile uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */
5586  ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_t onfi_device_no_of_blocks_per_lun_l; /* ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L */
5587  volatile uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */
5588  ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_t onfi_device_no_of_blocks_per_lun_u; /* ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U */
5589  volatile uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */
5590  ALT_NAND_PARAM_FEATURES_t features; /* ALT_NAND_PARAM_FEATURES */
5591 };
5592 
5593 /* The typedef declaration for register group ALT_NAND_PARAM. */
5594 typedef volatile struct ALT_NAND_PARAM_s ALT_NAND_PARAM_t;
5595 /* The struct declaration for the raw register contents of register group ALT_NAND_PARAM. */
5596 struct ALT_NAND_PARAM_raw_s
5597 {
5598  volatile uint32_t manufacturer_id; /* ALT_NAND_PARAM_MANUFACTURER_ID */
5599  uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
5600  volatile uint32_t device_id; /* ALT_NAND_PARAM_DEVICE_ID */
5601  uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
5602  volatile uint32_t device_param_0; /* ALT_NAND_PARAM_DEVICE_PARAM_0 */
5603  uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
5604  volatile uint32_t device_param_1; /* ALT_NAND_PARAM_DEVICE_PARAM_1 */
5605  uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
5606  volatile uint32_t device_param_2; /* ALT_NAND_PARAM_DEVICE_PARAM_2 */
5607  uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
5608  volatile uint32_t logical_page_data_size; /* ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE */
5609  uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
5610  volatile uint32_t logical_page_spare_size; /* ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE */
5611  uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */
5612  volatile uint32_t revision; /* ALT_NAND_PARAM_REVISION */
5613  uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
5614  volatile uint32_t onfi_device_features; /* ALT_NAND_PARAM_ONFI_DEV_FEATURES */
5615  uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
5616  volatile uint32_t onfi_optional_commands; /* ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS */
5617  uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
5618  volatile uint32_t onfi_timing_mode; /* ALT_NAND_PARAM_ONFI_TIMING_MOD */
5619  uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
5620  volatile uint32_t onfi_pgm_cache_timing_mode; /* ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD */
5621  uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */
5622  volatile uint32_t onfi_device_no_of_luns; /* ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS */
5623  uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */
5624  volatile uint32_t onfi_device_no_of_blocks_per_lun_l; /* ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L */
5625  uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */
5626  volatile uint32_t onfi_device_no_of_blocks_per_lun_u; /* ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U */
5627  uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */
5628  volatile uint32_t features; /* ALT_NAND_PARAM_FEATURES */
5629 };
5630 
5631 /* The typedef declaration for the raw register contents of register group ALT_NAND_PARAM. */
5632 typedef volatile struct ALT_NAND_PARAM_raw_s ALT_NAND_PARAM_raw_t;
5633 #endif /* __ASSEMBLY__ */
5634 
5635 
5636 /*
5637  * Component : ALT_NAND_STAT
5638  *
5639  */
5640 /*
5641  * Register : transfer_mode
5642  *
5643  * Current data transfer mode is Main only, Spare only or Main+Spare.
5644  *
5645  * This information is per bank.
5646  *
5647  * Register Layout
5648  *
5649  * Bits | Access | Reset | Description
5650  * :-------|:-------|:--------|:-----------------------------
5651  * [1:0] | R | 0x0 | ALT_NAND_STAT_TFR_MOD_VALUE0
5652  * [3:2] | R | 0x0 | ALT_NAND_STAT_TFR_MOD_VALUE1
5653  * [5:4] | R | 0x0 | ALT_NAND_STAT_TFR_MOD_VALUE2
5654  * [7:6] | R | 0x0 | ALT_NAND_STAT_TFR_MOD_VALUE3
5655  * [31:8] | ??? | Unknown | *UNDEFINED*
5656  *
5657  */
5658 /*
5659  * Field : value0
5660  *
5661  * [list][*]00 - Bank 0 is in Main mode [*]01 - Bank 0 is in Spare mode [*]10 -
5662  * Bank 0 is in Main+Spare mode[/list]
5663  *
5664  * Field Access Macros:
5665  *
5666  */
5667 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE0 register field. */
5668 #define ALT_NAND_STAT_TFR_MOD_VALUE0_LSB 0
5669 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE0 register field. */
5670 #define ALT_NAND_STAT_TFR_MOD_VALUE0_MSB 1
5671 /* The width in bits of the ALT_NAND_STAT_TFR_MOD_VALUE0 register field. */
5672 #define ALT_NAND_STAT_TFR_MOD_VALUE0_WIDTH 2
5673 /* The mask used to set the ALT_NAND_STAT_TFR_MOD_VALUE0 register field value. */
5674 #define ALT_NAND_STAT_TFR_MOD_VALUE0_SET_MSK 0x00000003
5675 /* The mask used to clear the ALT_NAND_STAT_TFR_MOD_VALUE0 register field value. */
5676 #define ALT_NAND_STAT_TFR_MOD_VALUE0_CLR_MSK 0xfffffffc
5677 /* The reset value of the ALT_NAND_STAT_TFR_MOD_VALUE0 register field. */
5678 #define ALT_NAND_STAT_TFR_MOD_VALUE0_RESET 0x0
5679 /* Extracts the ALT_NAND_STAT_TFR_MOD_VALUE0 field value from a register. */
5680 #define ALT_NAND_STAT_TFR_MOD_VALUE0_GET(value) (((value) & 0x00000003) >> 0)
5681 /* Produces a ALT_NAND_STAT_TFR_MOD_VALUE0 register field value suitable for setting the register. */
5682 #define ALT_NAND_STAT_TFR_MOD_VALUE0_SET(value) (((value) << 0) & 0x00000003)
5683 
5684 /*
5685  * Field : value1
5686  *
5687  * [list][*]00 - Bank 1 is in Main mode [*]01 - Bank 1 is in Spare mode [*]10 -
5688  * Bank 1 is in Main+Spare mode[/list]
5689  *
5690  * Field Access Macros:
5691  *
5692  */
5693 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE1 register field. */
5694 #define ALT_NAND_STAT_TFR_MOD_VALUE1_LSB 2
5695 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE1 register field. */
5696 #define ALT_NAND_STAT_TFR_MOD_VALUE1_MSB 3
5697 /* The width in bits of the ALT_NAND_STAT_TFR_MOD_VALUE1 register field. */
5698 #define ALT_NAND_STAT_TFR_MOD_VALUE1_WIDTH 2
5699 /* The mask used to set the ALT_NAND_STAT_TFR_MOD_VALUE1 register field value. */
5700 #define ALT_NAND_STAT_TFR_MOD_VALUE1_SET_MSK 0x0000000c
5701 /* The mask used to clear the ALT_NAND_STAT_TFR_MOD_VALUE1 register field value. */
5702 #define ALT_NAND_STAT_TFR_MOD_VALUE1_CLR_MSK 0xfffffff3
5703 /* The reset value of the ALT_NAND_STAT_TFR_MOD_VALUE1 register field. */
5704 #define ALT_NAND_STAT_TFR_MOD_VALUE1_RESET 0x0
5705 /* Extracts the ALT_NAND_STAT_TFR_MOD_VALUE1 field value from a register. */
5706 #define ALT_NAND_STAT_TFR_MOD_VALUE1_GET(value) (((value) & 0x0000000c) >> 2)
5707 /* Produces a ALT_NAND_STAT_TFR_MOD_VALUE1 register field value suitable for setting the register. */
5708 #define ALT_NAND_STAT_TFR_MOD_VALUE1_SET(value) (((value) << 2) & 0x0000000c)
5709 
5710 /*
5711  * Field : value2
5712  *
5713  * [list][*]00 - Bank 2 is in Main mode [*]01 - Bank 2 is in Spare mode [*]10 -
5714  * Bank 2 is in Main+Spare mode[/list]
5715  *
5716  * Field Access Macros:
5717  *
5718  */
5719 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE2 register field. */
5720 #define ALT_NAND_STAT_TFR_MOD_VALUE2_LSB 4
5721 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE2 register field. */
5722 #define ALT_NAND_STAT_TFR_MOD_VALUE2_MSB 5
5723 /* The width in bits of the ALT_NAND_STAT_TFR_MOD_VALUE2 register field. */
5724 #define ALT_NAND_STAT_TFR_MOD_VALUE2_WIDTH 2
5725 /* The mask used to set the ALT_NAND_STAT_TFR_MOD_VALUE2 register field value. */
5726 #define ALT_NAND_STAT_TFR_MOD_VALUE2_SET_MSK 0x00000030
5727 /* The mask used to clear the ALT_NAND_STAT_TFR_MOD_VALUE2 register field value. */
5728 #define ALT_NAND_STAT_TFR_MOD_VALUE2_CLR_MSK 0xffffffcf
5729 /* The reset value of the ALT_NAND_STAT_TFR_MOD_VALUE2 register field. */
5730 #define ALT_NAND_STAT_TFR_MOD_VALUE2_RESET 0x0
5731 /* Extracts the ALT_NAND_STAT_TFR_MOD_VALUE2 field value from a register. */
5732 #define ALT_NAND_STAT_TFR_MOD_VALUE2_GET(value) (((value) & 0x00000030) >> 4)
5733 /* Produces a ALT_NAND_STAT_TFR_MOD_VALUE2 register field value suitable for setting the register. */
5734 #define ALT_NAND_STAT_TFR_MOD_VALUE2_SET(value) (((value) << 4) & 0x00000030)
5735 
5736 /*
5737  * Field : value3
5738  *
5739  * [list][*]00 - Bank 3 is in Main mode [*]01 - Bank 3 is in Spare mode [*]10 -
5740  * Bank 3 is in Main+Spare mode[/list]
5741  *
5742  * Field Access Macros:
5743  *
5744  */
5745 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE3 register field. */
5746 #define ALT_NAND_STAT_TFR_MOD_VALUE3_LSB 6
5747 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE3 register field. */
5748 #define ALT_NAND_STAT_TFR_MOD_VALUE3_MSB 7
5749 /* The width in bits of the ALT_NAND_STAT_TFR_MOD_VALUE3 register field. */
5750 #define ALT_NAND_STAT_TFR_MOD_VALUE3_WIDTH 2
5751 /* The mask used to set the ALT_NAND_STAT_TFR_MOD_VALUE3 register field value. */
5752 #define ALT_NAND_STAT_TFR_MOD_VALUE3_SET_MSK 0x000000c0
5753 /* The mask used to clear the ALT_NAND_STAT_TFR_MOD_VALUE3 register field value. */
5754 #define ALT_NAND_STAT_TFR_MOD_VALUE3_CLR_MSK 0xffffff3f
5755 /* The reset value of the ALT_NAND_STAT_TFR_MOD_VALUE3 register field. */
5756 #define ALT_NAND_STAT_TFR_MOD_VALUE3_RESET 0x0
5757 /* Extracts the ALT_NAND_STAT_TFR_MOD_VALUE3 field value from a register. */
5758 #define ALT_NAND_STAT_TFR_MOD_VALUE3_GET(value) (((value) & 0x000000c0) >> 6)
5759 /* Produces a ALT_NAND_STAT_TFR_MOD_VALUE3 register field value suitable for setting the register. */
5760 #define ALT_NAND_STAT_TFR_MOD_VALUE3_SET(value) (((value) << 6) & 0x000000c0)
5761 
5762 #ifndef __ASSEMBLY__
5763 /*
5764  * WARNING: The C register and register group struct declarations are provided for
5765  * convenience and illustrative purposes. They should, however, be used with
5766  * caution as the C language standard provides no guarantees about the alignment or
5767  * atomicity of device memory accesses. The recommended practice for writing
5768  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5769  * alt_write_word() functions.
5770  *
5771  * The struct declaration for register ALT_NAND_STAT_TFR_MOD.
5772  */
5773 struct ALT_NAND_STAT_TFR_MOD_s
5774 {
5775  const uint32_t value0 : 2; /* ALT_NAND_STAT_TFR_MOD_VALUE0 */
5776  const uint32_t value1 : 2; /* ALT_NAND_STAT_TFR_MOD_VALUE1 */
5777  const uint32_t value2 : 2; /* ALT_NAND_STAT_TFR_MOD_VALUE2 */
5778  const uint32_t value3 : 2; /* ALT_NAND_STAT_TFR_MOD_VALUE3 */
5779  uint32_t : 24; /* *UNDEFINED* */
5780 };
5781 
5782 /* The typedef declaration for register ALT_NAND_STAT_TFR_MOD. */
5783 typedef volatile struct ALT_NAND_STAT_TFR_MOD_s ALT_NAND_STAT_TFR_MOD_t;
5784 #endif /* __ASSEMBLY__ */
5785 
5786 /* The reset value of the ALT_NAND_STAT_TFR_MOD register. */
5787 #define ALT_NAND_STAT_TFR_MOD_RESET 0x00000000
5788 /* The byte offset of the ALT_NAND_STAT_TFR_MOD register from the beginning of the component. */
5789 #define ALT_NAND_STAT_TFR_MOD_OFST 0x0
5790 
5791 /*
5792  * Register : intr_status0
5793  *
5794  * Interrupt status register for bank 0
5795  *
5796  * Register Layout
5797  *
5798  * Bits | Access | Reset | Description
5799  * :--------|:-------|:--------|:----------------------------------------------
5800  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR
5801  * [1] | ??? | Unknown | *UNDEFINED*
5802  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP
5803  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_TIME_OUT
5804  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL
5805  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL
5806  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_LD_COMP
5807  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP
5808  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_ERASE_COMP
5809  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP
5810  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK
5811  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD
5812  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_INT_ACT
5813  * [13] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_RST_COMP
5814  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR
5815  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC
5816  * [16] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE
5817  * [31:17] | ??? | Unknown | *UNDEFINED*
5818  *
5819  */
5820 /*
5821  * Field : ecc_uncor_err
5822  *
5823  * Ecc logic detected uncorrectable error while reading data from flash device.
5824  *
5825  * Field Access Macros:
5826  *
5827  */
5828 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR register field. */
5829 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_LSB 0
5830 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR register field. */
5831 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_MSB 0
5832 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR register field. */
5833 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_WIDTH 1
5834 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR register field value. */
5835 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_SET_MSK 0x00000001
5836 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR register field value. */
5837 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
5838 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR register field. */
5839 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_RESET 0x0
5840 /* Extracts the ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR field value from a register. */
5841 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
5842 /* Produces a ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR register field value suitable for setting the register. */
5843 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
5844 
5845 /*
5846  * Field : dma_cmd_comp
5847  *
5848  * A data DMA command has completed on this bank
5849  *
5850  * Field Access Macros:
5851  *
5852  */
5853 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP register field. */
5854 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_LSB 2
5855 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP register field. */
5856 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_MSB 2
5857 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP register field. */
5858 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_WIDTH 1
5859 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP register field value. */
5860 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_SET_MSK 0x00000004
5861 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP register field value. */
5862 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_CLR_MSK 0xfffffffb
5863 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP register field. */
5864 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_RESET 0x0
5865 /* Extracts the ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP field value from a register. */
5866 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
5867 /* Produces a ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP register field value suitable for setting the register. */
5868 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
5869 
5870 /*
5871  * Field : time_out
5872  *
5873  * Watchdog timer has triggered in the controller due to one of the reasons like
5874  * device
5875  *
5876  * not responding or controller state machine did not get back to idle
5877  *
5878  * Field Access Macros:
5879  *
5880  */
5881 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_TIME_OUT register field. */
5882 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_LSB 3
5883 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_TIME_OUT register field. */
5884 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_MSB 3
5885 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_TIME_OUT register field. */
5886 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_WIDTH 1
5887 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_TIME_OUT register field value. */
5888 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_SET_MSK 0x00000008
5889 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_TIME_OUT register field value. */
5890 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_CLR_MSK 0xfffffff7
5891 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_TIME_OUT register field. */
5892 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_RESET 0x0
5893 /* Extracts the ALT_NAND_STAT_INTR_STAT0_TIME_OUT field value from a register. */
5894 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
5895 /* Produces a ALT_NAND_STAT_INTR_STAT0_TIME_OUT register field value suitable for setting the register. */
5896 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
5897 
5898 /*
5899  * Field : program_fail
5900  *
5901  * Program failure occurred in the device on issuance of a program command.
5902  * err_block_addr
5903  *
5904  * and err_page_addr contain the block address and page address that failed program
5905  * operation.
5906  *
5907  * Field Access Macros:
5908  *
5909  */
5910 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL register field. */
5911 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_LSB 4
5912 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL register field. */
5913 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_MSB 4
5914 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL register field. */
5915 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_WIDTH 1
5916 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL register field value. */
5917 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_SET_MSK 0x00000010
5918 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL register field value. */
5919 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_CLR_MSK 0xffffffef
5920 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL register field. */
5921 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_RESET 0x0
5922 /* Extracts the ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL field value from a register. */
5923 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
5924 /* Produces a ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL register field value suitable for setting the register. */
5925 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
5926 
5927 /*
5928  * Field : erase_fail
5929  *
5930  * Erase failure occurred in the device on issuance of a erase command.
5931  * err_block_addr
5932  *
5933  * and err_page_addr contain the block address and page address that failed erase
5934  * operation.
5935  *
5936  * Field Access Macros:
5937  *
5938  */
5939 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL register field. */
5940 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_LSB 5
5941 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL register field. */
5942 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_MSB 5
5943 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL register field. */
5944 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_WIDTH 1
5945 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL register field value. */
5946 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_SET_MSK 0x00000020
5947 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL register field value. */
5948 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_CLR_MSK 0xffffffdf
5949 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL register field. */
5950 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_RESET 0x0
5951 /* Extracts the ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL field value from a register. */
5952 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
5953 /* Produces a ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL register field value suitable for setting the register. */
5954 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
5955 
5956 /*
5957  * Field : load_comp
5958  *
5959  * Device finished the last issued load command.
5960  *
5961  * Field Access Macros:
5962  *
5963  */
5964 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_LD_COMP register field. */
5965 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_LSB 6
5966 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_LD_COMP register field. */
5967 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_MSB 6
5968 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_LD_COMP register field. */
5969 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_WIDTH 1
5970 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_LD_COMP register field value. */
5971 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_SET_MSK 0x00000040
5972 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_LD_COMP register field value. */
5973 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_CLR_MSK 0xffffffbf
5974 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_LD_COMP register field. */
5975 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_RESET 0x0
5976 /* Extracts the ALT_NAND_STAT_INTR_STAT0_LD_COMP field value from a register. */
5977 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
5978 /* Produces a ALT_NAND_STAT_INTR_STAT0_LD_COMP register field value suitable for setting the register. */
5979 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
5980 
5981 /*
5982  * Field : program_comp
5983  *
5984  * Device finished the last issued program command.
5985  *
5986  * Field Access Macros:
5987  *
5988  */
5989 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP register field. */
5990 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_LSB 7
5991 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP register field. */
5992 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_MSB 7
5993 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP register field. */
5994 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_WIDTH 1
5995 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP register field value. */
5996 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_SET_MSK 0x00000080
5997 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP register field value. */
5998 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_CLR_MSK 0xffffff7f
5999 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP register field. */
6000 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_RESET 0x0
6001 /* Extracts the ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP field value from a register. */
6002 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
6003 /* Produces a ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP register field value suitable for setting the register. */
6004 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
6005 
6006 /*
6007  * Field : erase_comp
6008  *
6009  * Device erase operation complete
6010  *
6011  * Field Access Macros:
6012  *
6013  */
6014 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_ERASE_COMP register field. */
6015 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_LSB 8
6016 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_ERASE_COMP register field. */
6017 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_MSB 8
6018 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_ERASE_COMP register field. */
6019 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_WIDTH 1
6020 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_ERASE_COMP register field value. */
6021 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_SET_MSK 0x00000100
6022 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_ERASE_COMP register field value. */
6023 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_CLR_MSK 0xfffffeff
6024 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_ERASE_COMP register field. */
6025 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_RESET 0x0
6026 /* Extracts the ALT_NAND_STAT_INTR_STAT0_ERASE_COMP field value from a register. */
6027 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
6028 /* Produces a ALT_NAND_STAT_INTR_STAT0_ERASE_COMP register field value suitable for setting the register. */
6029 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
6030 
6031 /*
6032  * Field : pipe_cpybck_cmd_comp
6033  *
6034  * A pipeline command or a copyback bank command has completed on this particular
6035  * bank
6036  *
6037  * Field Access Macros:
6038  *
6039  */
6040 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP register field. */
6041 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_LSB 9
6042 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP register field. */
6043 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_MSB 9
6044 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP register field. */
6045 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_WIDTH 1
6046 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP register field value. */
6047 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
6048 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP register field value. */
6049 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
6050 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP register field. */
6051 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_RESET 0x0
6052 /* Extracts the ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP field value from a register. */
6053 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
6054 /* Produces a ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
6055 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
6056 
6057 /*
6058  * Field : locked_blk
6059  *
6060  * The address to program or erase operation is to a locked block and the operation
6061  * failed
6062  *
6063  * due to this reason
6064  *
6065  * Field Access Macros:
6066  *
6067  */
6068 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK register field. */
6069 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_LSB 10
6070 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK register field. */
6071 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_MSB 10
6072 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK register field. */
6073 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_WIDTH 1
6074 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK register field value. */
6075 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_SET_MSK 0x00000400
6076 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK register field value. */
6077 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_CLR_MSK 0xfffffbff
6078 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK register field. */
6079 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_RESET 0x0
6080 /* Extracts the ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK field value from a register. */
6081 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
6082 /* Produces a ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK register field value suitable for setting the register. */
6083 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
6084 
6085 /*
6086  * Field : unsup_cmd
6087  *
6088  * An unsupported command was received. This interrupt is set when an invalid
6089  * command is
6090  *
6091  * received, or when a command sequence is broken.
6092  *
6093  * Field Access Macros:
6094  *
6095  */
6096 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD register field. */
6097 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_LSB 11
6098 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD register field. */
6099 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_MSB 11
6100 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD register field. */
6101 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_WIDTH 1
6102 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD register field value. */
6103 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_SET_MSK 0x00000800
6104 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD register field value. */
6105 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_CLR_MSK 0xfffff7ff
6106 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD register field. */
6107 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_RESET 0x0
6108 /* Extracts the ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD field value from a register. */
6109 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
6110 /* Produces a ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD register field value suitable for setting the register. */
6111 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
6112 
6113 /*
6114  * Field : int_act
6115  *
6116  * R/B pin of device transitioned from low to high
6117  *
6118  * Field Access Macros:
6119  *
6120  */
6121 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_INT_ACT register field. */
6122 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_LSB 12
6123 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_INT_ACT register field. */
6124 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_MSB 12
6125 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_INT_ACT register field. */
6126 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_WIDTH 1
6127 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_INT_ACT register field value. */
6128 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_SET_MSK 0x00001000
6129 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_INT_ACT register field value. */
6130 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_CLR_MSK 0xffffefff
6131 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_INT_ACT register field. */
6132 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_RESET 0x0
6133 /* Extracts the ALT_NAND_STAT_INTR_STAT0_INT_ACT field value from a register. */
6134 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
6135 /* Produces a ALT_NAND_STAT_INTR_STAT0_INT_ACT register field value suitable for setting the register. */
6136 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
6137 
6138 /*
6139  * Field : rst_comp
6140  *
6141  * Controller has finished reset and initialization process
6142  *
6143  * Field Access Macros:
6144  *
6145  */
6146 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_RST_COMP register field. */
6147 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_LSB 13
6148 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_RST_COMP register field. */
6149 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_MSB 13
6150 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_RST_COMP register field. */
6151 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_WIDTH 1
6152 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_RST_COMP register field value. */
6153 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_SET_MSK 0x00002000
6154 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_RST_COMP register field value. */
6155 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_CLR_MSK 0xffffdfff
6156 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_RST_COMP register field. */
6157 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_RESET 0x0
6158 /* Extracts the ALT_NAND_STAT_INTR_STAT0_RST_COMP field value from a register. */
6159 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
6160 /* Produces a ALT_NAND_STAT_INTR_STAT0_RST_COMP register field value suitable for setting the register. */
6161 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
6162 
6163 /*
6164  * Field : pipe_cmd_err
6165  *
6166  * A pipeline command sequence has been violated. This occurs when Map 01 page
6167  * read/write
6168  *
6169  * address does not match the corresponding expected address from the pipeline
6170  * commands issued
6171  *
6172  * earlier.
6173  *
6174  * Field Access Macros:
6175  *
6176  */
6177 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR register field. */
6178 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_LSB 14
6179 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR register field. */
6180 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_MSB 14
6181 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR register field. */
6182 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_WIDTH 1
6183 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR register field value. */
6184 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_SET_MSK 0x00004000
6185 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR register field value. */
6186 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
6187 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR register field. */
6188 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_RESET 0x0
6189 /* Extracts the ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR field value from a register. */
6190 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
6191 /* Produces a ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR register field value suitable for setting the register. */
6192 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
6193 
6194 /*
6195  * Field : page_xfer_inc
6196  *
6197  * For every page of data transfer to or from the device, this bit will be set.
6198  *
6199  * Field Access Macros:
6200  *
6201  */
6202 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC register field. */
6203 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_LSB 15
6204 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC register field. */
6205 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_MSB 15
6206 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC register field. */
6207 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_WIDTH 1
6208 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC register field value. */
6209 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_SET_MSK 0x00008000
6210 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC register field value. */
6211 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_CLR_MSK 0xffff7fff
6212 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC register field. */
6213 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_RESET 0x0
6214 /* Extracts the ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC field value from a register. */
6215 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
6216 /* Produces a ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC register field value suitable for setting the register. */
6217 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
6218 
6219 /*
6220  * Field : erased_page
6221  *
6222  * If an erased page is detected on reads, this bit will be set. The detection of
6223  * erased
6224  *
6225  * page is based on the number of 0's in the page. If the number of 0's in the page
6226  * being
6227  *
6228  * read is less than the value in the erase_threshold (programmable register),
6229  *
6230  * an erased page is inferred and no un-correctable error will be flagged for that
6231  * page.
6232  *
6233  * If ECC is disabled, the erased_page interrupt shall be set as explained above.
6234  * If ECC is
6235  *
6236  * enabled, in addition to the above condition, only when the ECC logic detects an
6237  *
6238  * un-correctable error for that page will the erased_page interrupt be flagged. If
6239  * the ECC
6240  *
6241  * logic detects a no-error or correctable error page, this erased page interrupt
6242  * will not
6243  *
6244  * be set.
6245  *
6246  * Field Access Macros:
6247  *
6248  */
6249 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE register field. */
6250 #define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_LSB 16
6251 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE register field. */
6252 #define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_MSB 16
6253 /* The width in bits of the ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE register field. */
6254 #define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_WIDTH 1
6255 /* The mask used to set the ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE register field value. */
6256 #define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_SET_MSK 0x00010000
6257 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE register field value. */
6258 #define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_CLR_MSK 0xfffeffff
6259 /* The reset value of the ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE register field. */
6260 #define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_RESET 0x0
6261 /* Extracts the ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE field value from a register. */
6262 #define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
6263 /* Produces a ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE register field value suitable for setting the register. */
6264 #define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
6265 
6266 #ifndef __ASSEMBLY__
6267 /*
6268  * WARNING: The C register and register group struct declarations are provided for
6269  * convenience and illustrative purposes. They should, however, be used with
6270  * caution as the C language standard provides no guarantees about the alignment or
6271  * atomicity of device memory accesses. The recommended practice for writing
6272  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6273  * alt_write_word() functions.
6274  *
6275  * The struct declaration for register ALT_NAND_STAT_INTR_STAT0.
6276  */
6277 struct ALT_NAND_STAT_INTR_STAT0_s
6278 {
6279  uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR */
6280  uint32_t : 1; /* *UNDEFINED* */
6281  uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP */
6282  uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_STAT0_TIME_OUT */
6283  uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL */
6284  uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL */
6285  uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_STAT0_LD_COMP */
6286  uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP */
6287  uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_STAT0_ERASE_COMP */
6288  uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP */
6289  uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK */
6290  uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD */
6291  uint32_t int_act : 1; /* ALT_NAND_STAT_INTR_STAT0_INT_ACT */
6292  uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_STAT0_RST_COMP */
6293  uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR */
6294  uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC */
6295  uint32_t erased_page : 1; /* ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE */
6296  uint32_t : 15; /* *UNDEFINED* */
6297 };
6298 
6299 /* The typedef declaration for register ALT_NAND_STAT_INTR_STAT0. */
6300 typedef volatile struct ALT_NAND_STAT_INTR_STAT0_s ALT_NAND_STAT_INTR_STAT0_t;
6301 #endif /* __ASSEMBLY__ */
6302 
6303 /* The reset value of the ALT_NAND_STAT_INTR_STAT0 register. */
6304 #define ALT_NAND_STAT_INTR_STAT0_RESET 0x00000000
6305 /* The byte offset of the ALT_NAND_STAT_INTR_STAT0 register from the beginning of the component. */
6306 #define ALT_NAND_STAT_INTR_STAT0_OFST 0x10
6307 
6308 /*
6309  * Register : intr_en0
6310  *
6311  * Enables corresponding interrupt bit in interrupt register
6312  *
6313  * for bank 0
6314  *
6315  * Register Layout
6316  *
6317  * Bits | Access | Reset | Description
6318  * :--------|:-------|:--------|:--------------------------------------------
6319  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR
6320  * [1] | ??? | Unknown | *UNDEFINED*
6321  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP
6322  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_TIME_OUT
6323  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL
6324  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_ERASE_FAIL
6325  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_LD_COMP
6326  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP
6327  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_ERASE_COMP
6328  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP
6329  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_LOCKED_BLK
6330  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_UNSUP_CMD
6331  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_INT_ACT
6332  * [13] | RW | 0x1 | ALT_NAND_STAT_INTR_EN0_RST_COMP
6333  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR
6334  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC
6335  * [16] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_ERASED_PAGE
6336  * [31:17] | ??? | Unknown | *UNDEFINED*
6337  *
6338  */
6339 /*
6340  * Field : ecc_uncor_err
6341  *
6342  * If set, Controller will interrupt processor when Ecc logic detects uncorrectable
6343  * error.
6344  *
6345  * Field Access Macros:
6346  *
6347  */
6348 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field. */
6349 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_LSB 0
6350 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field. */
6351 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_MSB 0
6352 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field. */
6353 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_WIDTH 1
6354 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field value. */
6355 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_SET_MSK 0x00000001
6356 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field value. */
6357 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
6358 /* The reset value of the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field. */
6359 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_RESET 0x0
6360 /* Extracts the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR field value from a register. */
6361 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
6362 /* Produces a ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field value suitable for setting the register. */
6363 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
6364 
6365 /*
6366  * Field : dma_cmd_comp
6367  *
6368  * A data DMA command has completed on this bank
6369  *
6370  * Field Access Macros:
6371  *
6372  */
6373 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field. */
6374 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_LSB 2
6375 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field. */
6376 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_MSB 2
6377 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field. */
6378 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_WIDTH 1
6379 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field value. */
6380 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_SET_MSK 0x00000004
6381 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field value. */
6382 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_CLR_MSK 0xfffffffb
6383 /* The reset value of the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field. */
6384 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_RESET 0x0
6385 /* Extracts the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP field value from a register. */
6386 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
6387 /* Produces a ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field value suitable for setting the register. */
6388 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
6389 
6390 /*
6391  * Field : time_out
6392  *
6393  * Watchdog timer has triggered in the controller due to one of the reasons like
6394  * device
6395  *
6396  * not responding or controller state machine did not get back to idle
6397  *
6398  * Field Access Macros:
6399  *
6400  */
6401 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field. */
6402 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_LSB 3
6403 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field. */
6404 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_MSB 3
6405 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field. */
6406 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_WIDTH 1
6407 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field value. */
6408 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_SET_MSK 0x00000008
6409 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field value. */
6410 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_CLR_MSK 0xfffffff7
6411 /* The reset value of the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field. */
6412 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_RESET 0x0
6413 /* Extracts the ALT_NAND_STAT_INTR_EN0_TIME_OUT field value from a register. */
6414 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
6415 /* Produces a ALT_NAND_STAT_INTR_EN0_TIME_OUT register field value suitable for setting the register. */
6416 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
6417 
6418 /*
6419  * Field : program_fail
6420  *
6421  * Program failure occurred in the device on issuance of a program command.
6422  * err_block_addr
6423  *
6424  * and err_page_addr contain the block address and page address that failed program
6425  * operation.
6426  *
6427  * Field Access Macros:
6428  *
6429  */
6430 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field. */
6431 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_LSB 4
6432 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field. */
6433 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_MSB 4
6434 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field. */
6435 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_WIDTH 1
6436 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field value. */
6437 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_SET_MSK 0x00000010
6438 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field value. */
6439 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_CLR_MSK 0xffffffef
6440 /* The reset value of the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field. */
6441 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_RESET 0x0
6442 /* Extracts the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL field value from a register. */
6443 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
6444 /* Produces a ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field value suitable for setting the register. */
6445 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
6446 
6447 /*
6448  * Field : erase_fail
6449  *
6450  * Erase failure occurred in the device on issuance of a erase command.
6451  * err_block_addr
6452  *
6453  * and err_page_addr contain the block address and page address that failed erase
6454  * operation.
6455  *
6456  * Field Access Macros:
6457  *
6458  */
6459 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field. */
6460 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_LSB 5
6461 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field. */
6462 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_MSB 5
6463 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field. */
6464 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_WIDTH 1
6465 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field value. */
6466 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_SET_MSK 0x00000020
6467 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field value. */
6468 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_CLR_MSK 0xffffffdf
6469 /* The reset value of the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field. */
6470 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_RESET 0x0
6471 /* Extracts the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL field value from a register. */
6472 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
6473 /* Produces a ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field value suitable for setting the register. */
6474 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
6475 
6476 /*
6477  * Field : load_comp
6478  *
6479  * Device finished the last issued load command.
6480  *
6481  * Field Access Macros:
6482  *
6483  */
6484 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_LD_COMP register field. */
6485 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_LSB 6
6486 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_LD_COMP register field. */
6487 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_MSB 6
6488 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_LD_COMP register field. */
6489 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_WIDTH 1
6490 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_LD_COMP register field value. */
6491 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_SET_MSK 0x00000040
6492 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_LD_COMP register field value. */
6493 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_CLR_MSK 0xffffffbf
6494 /* The reset value of the ALT_NAND_STAT_INTR_EN0_LD_COMP register field. */
6495 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_RESET 0x0
6496 /* Extracts the ALT_NAND_STAT_INTR_EN0_LD_COMP field value from a register. */
6497 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
6498 /* Produces a ALT_NAND_STAT_INTR_EN0_LD_COMP register field value suitable for setting the register. */
6499 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
6500 
6501 /*
6502  * Field : program_comp
6503  *
6504  * Device finished the last issued program command.
6505  *
6506  * Field Access Macros:
6507  *
6508  */
6509 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field. */
6510 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_LSB 7
6511 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field. */
6512 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_MSB 7
6513 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field. */
6514 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_WIDTH 1
6515 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field value. */
6516 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_SET_MSK 0x00000080
6517 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field value. */
6518 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_CLR_MSK 0xffffff7f
6519 /* The reset value of the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field. */
6520 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_RESET 0x0
6521 /* Extracts the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP field value from a register. */
6522 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
6523 /* Produces a ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field value suitable for setting the register. */
6524 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
6525 
6526 /*
6527  * Field : erase_comp
6528  *
6529  * Device erase operation complete
6530  *
6531  * Field Access Macros:
6532  *
6533  */
6534 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field. */
6535 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_LSB 8
6536 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field. */
6537 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_MSB 8
6538 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field. */
6539 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_WIDTH 1
6540 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field value. */
6541 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_SET_MSK 0x00000100
6542 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field value. */
6543 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_CLR_MSK 0xfffffeff
6544 /* The reset value of the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field. */
6545 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_RESET 0x0
6546 /* Extracts the ALT_NAND_STAT_INTR_EN0_ERASE_COMP field value from a register. */
6547 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
6548 /* Produces a ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field value suitable for setting the register. */
6549 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
6550 
6551 /*
6552  * Field : pipe_cpybck_cmd_comp
6553  *
6554  * A pipeline command or a copyback bank command has completed on this particular
6555  * bank
6556  *
6557  * Field Access Macros:
6558  *
6559  */
6560 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field. */
6561 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_LSB 9
6562 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field. */
6563 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_MSB 9
6564 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field. */
6565 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_WIDTH 1
6566 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field value. */
6567 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
6568 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field value. */
6569 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
6570 /* The reset value of the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field. */
6571 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_RESET 0x0
6572 /* Extracts the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP field value from a register. */
6573 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
6574 /* Produces a ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
6575 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
6576 
6577 /*
6578  * Field : locked_blk
6579  *
6580  * The address to program or erase operation is to a locked block and the operation
6581  * failed
6582  *
6583  * due to this reason
6584  *
6585  * Field Access Macros:
6586  *
6587  */
6588 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field. */
6589 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_LSB 10
6590 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field. */
6591 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_MSB 10
6592 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field. */
6593 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_WIDTH 1
6594 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field value. */
6595 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_SET_MSK 0x00000400
6596 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field value. */
6597 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_CLR_MSK 0xfffffbff
6598 /* The reset value of the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field. */
6599 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_RESET 0x0
6600 /* Extracts the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK field value from a register. */
6601 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
6602 /* Produces a ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field value suitable for setting the register. */
6603 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
6604 
6605 /*
6606  * Field : unsup_cmd
6607  *
6608  * An unsupported command was received. This interrupt is set when an invalid
6609  * command is
6610  *
6611  * received, or when a command sequence is broken.
6612  *
6613  * Field Access Macros:
6614  *
6615  */
6616 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field. */
6617 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_LSB 11
6618 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field. */
6619 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_MSB 11
6620 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field. */
6621 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_WIDTH 1
6622 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field value. */
6623 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_SET_MSK 0x00000800
6624 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field value. */
6625 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_CLR_MSK 0xfffff7ff
6626 /* The reset value of the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field. */
6627 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_RESET 0x0
6628 /* Extracts the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD field value from a register. */
6629 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
6630 /* Produces a ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field value suitable for setting the register. */
6631 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
6632 
6633 /*
6634  * Field : int_act
6635  *
6636  * R/B pin of device transitioned from low to high
6637  *
6638  * Field Access Macros:
6639  *
6640  */
6641 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_INT_ACT register field. */
6642 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_LSB 12
6643 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_INT_ACT register field. */
6644 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_MSB 12
6645 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_INT_ACT register field. */
6646 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_WIDTH 1
6647 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_INT_ACT register field value. */
6648 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_SET_MSK 0x00001000
6649 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_INT_ACT register field value. */
6650 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_CLR_MSK 0xffffefff
6651 /* The reset value of the ALT_NAND_STAT_INTR_EN0_INT_ACT register field. */
6652 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_RESET 0x0
6653 /* Extracts the ALT_NAND_STAT_INTR_EN0_INT_ACT field value from a register. */
6654 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
6655 /* Produces a ALT_NAND_STAT_INTR_EN0_INT_ACT register field value suitable for setting the register. */
6656 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
6657 
6658 /*
6659  * Field : rst_comp
6660  *
6661  * A reset command has completed on this bank
6662  *
6663  * Field Access Macros:
6664  *
6665  */
6666 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_RST_COMP register field. */
6667 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_LSB 13
6668 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_RST_COMP register field. */
6669 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_MSB 13
6670 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_RST_COMP register field. */
6671 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_WIDTH 1
6672 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_RST_COMP register field value. */
6673 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_SET_MSK 0x00002000
6674 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_RST_COMP register field value. */
6675 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_CLR_MSK 0xffffdfff
6676 /* The reset value of the ALT_NAND_STAT_INTR_EN0_RST_COMP register field. */
6677 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_RESET 0x1
6678 /* Extracts the ALT_NAND_STAT_INTR_EN0_RST_COMP field value from a register. */
6679 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
6680 /* Produces a ALT_NAND_STAT_INTR_EN0_RST_COMP register field value suitable for setting the register. */
6681 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
6682 
6683 /*
6684  * Field : pipe_cmd_err
6685  *
6686  * A pipeline command sequence has been violated. This occurs when Map 01 page
6687  * read/write
6688  *
6689  * address does not match the corresponding expected address from the pipeline
6690  * commands issued
6691  *
6692  * earlier.
6693  *
6694  * Field Access Macros:
6695  *
6696  */
6697 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field. */
6698 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_LSB 14
6699 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field. */
6700 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_MSB 14
6701 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field. */
6702 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_WIDTH 1
6703 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field value. */
6704 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_SET_MSK 0x00004000
6705 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field value. */
6706 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
6707 /* The reset value of the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field. */
6708 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_RESET 0x0
6709 /* Extracts the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR field value from a register. */
6710 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
6711 /* Produces a ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field value suitable for setting the register. */
6712 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
6713 
6714 /*
6715  * Field : page_xfer_inc
6716  *
6717  * For every page of data transfer to or from the device, this bit will be set.
6718  *
6719  * Field Access Macros:
6720  *
6721  */
6722 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field. */
6723 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_LSB 15
6724 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field. */
6725 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_MSB 15
6726 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field. */
6727 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_WIDTH 1
6728 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field value. */
6729 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_SET_MSK 0x00008000
6730 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field value. */
6731 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_CLR_MSK 0xffff7fff
6732 /* The reset value of the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field. */
6733 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_RESET 0x0
6734 /* Extracts the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC field value from a register. */
6735 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
6736 /* Produces a ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field value suitable for setting the register. */
6737 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
6738 
6739 /*
6740  * Field : erased_page
6741  *
6742  * If an erased page is detected on reads, this bit will be set. The detection of
6743  * erased
6744  *
6745  * page is based on the number of 0's in the page. If the number of 0's in the page
6746  * being
6747  *
6748  * read is less than the value in the erase_threshold (programmable register),
6749  *
6750  * an erased page is inferred and no un-correctable error will be flagged for that
6751  * page.
6752  *
6753  * If ECC is disabled, the erased_page interrupt shall be set as explained above.
6754  * If ECC is
6755  *
6756  * enabled, in addition to the above condition, only when the ECC logic detects an
6757  *
6758  * un-correctable error for that page will the erased_page interrupt be flagged. If
6759  * the ECC
6760  *
6761  * logic detects a no-error or correctable error page, this erased page interrupt
6762  * will not
6763  *
6764  * be set.
6765  *
6766  * Field Access Macros:
6767  *
6768  */
6769 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_ERASED_PAGE register field. */
6770 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_LSB 16
6771 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_ERASED_PAGE register field. */
6772 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_MSB 16
6773 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_ERASED_PAGE register field. */
6774 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_WIDTH 1
6775 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_ERASED_PAGE register field value. */
6776 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_SET_MSK 0x00010000
6777 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_ERASED_PAGE register field value. */
6778 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_CLR_MSK 0xfffeffff
6779 /* The reset value of the ALT_NAND_STAT_INTR_EN0_ERASED_PAGE register field. */
6780 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_RESET 0x0
6781 /* Extracts the ALT_NAND_STAT_INTR_EN0_ERASED_PAGE field value from a register. */
6782 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
6783 /* Produces a ALT_NAND_STAT_INTR_EN0_ERASED_PAGE register field value suitable for setting the register. */
6784 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
6785 
6786 #ifndef __ASSEMBLY__
6787 /*
6788  * WARNING: The C register and register group struct declarations are provided for
6789  * convenience and illustrative purposes. They should, however, be used with
6790  * caution as the C language standard provides no guarantees about the alignment or
6791  * atomicity of device memory accesses. The recommended practice for writing
6792  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6793  * alt_write_word() functions.
6794  *
6795  * The struct declaration for register ALT_NAND_STAT_INTR_EN0.
6796  */
6797 struct ALT_NAND_STAT_INTR_EN0_s
6798 {
6799  uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR */
6800  uint32_t : 1; /* *UNDEFINED* */
6801  uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP */
6802  uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_EN0_TIME_OUT */
6803  uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL */
6804  uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_EN0_ERASE_FAIL */
6805  uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_EN0_LD_COMP */
6806  uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP */
6807  uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_EN0_ERASE_COMP */
6808  uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP */
6809  uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_EN0_LOCKED_BLK */
6810  uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_EN0_UNSUP_CMD */
6811  uint32_t int_act : 1; /* ALT_NAND_STAT_INTR_EN0_INT_ACT */
6812  uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_EN0_RST_COMP */
6813  uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR */
6814  uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC */
6815  uint32_t erased_page : 1; /* ALT_NAND_STAT_INTR_EN0_ERASED_PAGE */
6816  uint32_t : 15; /* *UNDEFINED* */
6817 };
6818 
6819 /* The typedef declaration for register ALT_NAND_STAT_INTR_EN0. */
6820 typedef volatile struct ALT_NAND_STAT_INTR_EN0_s ALT_NAND_STAT_INTR_EN0_t;
6821 #endif /* __ASSEMBLY__ */
6822 
6823 /* The reset value of the ALT_NAND_STAT_INTR_EN0 register. */
6824 #define ALT_NAND_STAT_INTR_EN0_RESET 0x00002000
6825 /* The byte offset of the ALT_NAND_STAT_INTR_EN0 register from the beginning of the component. */
6826 #define ALT_NAND_STAT_INTR_EN0_OFST 0x20
6827 
6828 /*
6829  * Register : page_cnt0
6830  *
6831  * Decrementing page count bank 0
6832  *
6833  * Register Layout
6834  *
6835  * Bits | Access | Reset | Description
6836  * :-------|:-------|:--------|:------------------------------
6837  * [7:0] | R | 0x0 | ALT_NAND_STAT_PAGE_CNT0_VALUE
6838  * [31:8] | ??? | Unknown | *UNDEFINED*
6839  *
6840  */
6841 /*
6842  * Field : value
6843  *
6844  * Maintains a decrementing count of the number of pages in
6845  *
6846  * the multi-page (pipeline and copyback) command being executed.
6847  *
6848  * Field Access Macros:
6849  *
6850  */
6851 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_PAGE_CNT0_VALUE register field. */
6852 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_LSB 0
6853 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_PAGE_CNT0_VALUE register field. */
6854 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_MSB 7
6855 /* The width in bits of the ALT_NAND_STAT_PAGE_CNT0_VALUE register field. */
6856 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_WIDTH 8
6857 /* The mask used to set the ALT_NAND_STAT_PAGE_CNT0_VALUE register field value. */
6858 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_SET_MSK 0x000000ff
6859 /* The mask used to clear the ALT_NAND_STAT_PAGE_CNT0_VALUE register field value. */
6860 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_CLR_MSK 0xffffff00
6861 /* The reset value of the ALT_NAND_STAT_PAGE_CNT0_VALUE register field. */
6862 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_RESET 0x0
6863 /* Extracts the ALT_NAND_STAT_PAGE_CNT0_VALUE field value from a register. */
6864 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
6865 /* Produces a ALT_NAND_STAT_PAGE_CNT0_VALUE register field value suitable for setting the register. */
6866 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_SET(value) (((value) << 0) & 0x000000ff)
6867 
6868 #ifndef __ASSEMBLY__
6869 /*
6870  * WARNING: The C register and register group struct declarations are provided for
6871  * convenience and illustrative purposes. They should, however, be used with
6872  * caution as the C language standard provides no guarantees about the alignment or
6873  * atomicity of device memory accesses. The recommended practice for writing
6874  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6875  * alt_write_word() functions.
6876  *
6877  * The struct declaration for register ALT_NAND_STAT_PAGE_CNT0.
6878  */
6879 struct ALT_NAND_STAT_PAGE_CNT0_s
6880 {
6881  const uint32_t value : 8; /* ALT_NAND_STAT_PAGE_CNT0_VALUE */
6882  uint32_t : 24; /* *UNDEFINED* */
6883 };
6884 
6885 /* The typedef declaration for register ALT_NAND_STAT_PAGE_CNT0. */
6886 typedef volatile struct ALT_NAND_STAT_PAGE_CNT0_s ALT_NAND_STAT_PAGE_CNT0_t;
6887 #endif /* __ASSEMBLY__ */
6888 
6889 /* The reset value of the ALT_NAND_STAT_PAGE_CNT0 register. */
6890 #define ALT_NAND_STAT_PAGE_CNT0_RESET 0x00000000
6891 /* The byte offset of the ALT_NAND_STAT_PAGE_CNT0 register from the beginning of the component. */
6892 #define ALT_NAND_STAT_PAGE_CNT0_OFST 0x30
6893 
6894 /*
6895  * Register : err_page_addr0
6896  *
6897  * Erred page address bank 0
6898  *
6899  * Register Layout
6900  *
6901  * Bits | Access | Reset | Description
6902  * :--------|:-------|:--------|:-----------------------------------
6903  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE
6904  * [31:16] | ??? | Unknown | *UNDEFINED*
6905  *
6906  */
6907 /*
6908  * Field : value
6909  *
6910  * Holds the page address that resulted in a failure on program
6911  *
6912  * or erase operation.
6913  *
6914  * Field Access Macros:
6915  *
6916  */
6917 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field. */
6918 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_LSB 0
6919 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field. */
6920 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_MSB 15
6921 /* The width in bits of the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field. */
6922 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_WIDTH 16
6923 /* The mask used to set the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field value. */
6924 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_SET_MSK 0x0000ffff
6925 /* The mask used to clear the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field value. */
6926 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_CLR_MSK 0xffff0000
6927 /* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field. */
6928 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_RESET 0x0
6929 /* Extracts the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE field value from a register. */
6930 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
6931 /* Produces a ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field value suitable for setting the register. */
6932 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
6933 
6934 #ifndef __ASSEMBLY__
6935 /*
6936  * WARNING: The C register and register group struct declarations are provided for
6937  * convenience and illustrative purposes. They should, however, be used with
6938  * caution as the C language standard provides no guarantees about the alignment or
6939  * atomicity of device memory accesses. The recommended practice for writing
6940  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6941  * alt_write_word() functions.
6942  *
6943  * The struct declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR0.
6944  */
6945 struct ALT_NAND_STAT_ERR_PAGE_ADDR0_s
6946 {
6947  const uint32_t value : 16; /* ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE */
6948  uint32_t : 16; /* *UNDEFINED* */
6949 };
6950 
6951 /* The typedef declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR0. */
6952 typedef volatile struct ALT_NAND_STAT_ERR_PAGE_ADDR0_s ALT_NAND_STAT_ERR_PAGE_ADDR0_t;
6953 #endif /* __ASSEMBLY__ */
6954 
6955 /* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR0 register. */
6956 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_RESET 0x00000000
6957 /* The byte offset of the ALT_NAND_STAT_ERR_PAGE_ADDR0 register from the beginning of the component. */
6958 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_OFST 0x40
6959 
6960 /*
6961  * Register : err_block_addr0
6962  *
6963  * Erred block address bank 0
6964  *
6965  * Register Layout
6966  *
6967  * Bits | Access | Reset | Description
6968  * :--------|:-------|:--------|:------------------------------------
6969  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE
6970  * [31:16] | ??? | Unknown | *UNDEFINED*
6971  *
6972  */
6973 /*
6974  * Field : value
6975  *
6976  * Holds the block address that resulted in a failure on program
6977  *
6978  * or erase operation.
6979  *
6980  * Field Access Macros:
6981  *
6982  */
6983 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field. */
6984 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_LSB 0
6985 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field. */
6986 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_MSB 15
6987 /* The width in bits of the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field. */
6988 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_WIDTH 16
6989 /* The mask used to set the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field value. */
6990 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_SET_MSK 0x0000ffff
6991 /* The mask used to clear the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field value. */
6992 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_CLR_MSK 0xffff0000
6993 /* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field. */
6994 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_RESET 0x0
6995 /* Extracts the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE field value from a register. */
6996 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
6997 /* Produces a ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field value suitable for setting the register. */
6998 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
6999 
7000 #ifndef __ASSEMBLY__
7001 /*
7002  * WARNING: The C register and register group struct declarations are provided for
7003  * convenience and illustrative purposes. They should, however, be used with
7004  * caution as the C language standard provides no guarantees about the alignment or
7005  * atomicity of device memory accesses. The recommended practice for writing
7006  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7007  * alt_write_word() functions.
7008  *
7009  * The struct declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR0.
7010  */
7011 struct ALT_NAND_STAT_ERR_BLOCK_ADDR0_s
7012 {
7013  const uint32_t value : 16; /* ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE */
7014  uint32_t : 16; /* *UNDEFINED* */
7015 };
7016 
7017 /* The typedef declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR0. */
7018 typedef volatile struct ALT_NAND_STAT_ERR_BLOCK_ADDR0_s ALT_NAND_STAT_ERR_BLOCK_ADDR0_t;
7019 #endif /* __ASSEMBLY__ */
7020 
7021 /* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR0 register. */
7022 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_RESET 0x00000000
7023 /* The byte offset of the ALT_NAND_STAT_ERR_BLOCK_ADDR0 register from the beginning of the component. */
7024 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_OFST 0x50
7025 
7026 /*
7027  * Register : intr_status1
7028  *
7029  * Interrupt status register for bank 1
7030  *
7031  * Register Layout
7032  *
7033  * Bits | Access | Reset | Description
7034  * :--------|:-------|:--------|:----------------------------------------------
7035  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR
7036  * [1] | ??? | Unknown | *UNDEFINED*
7037  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP
7038  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_TIME_OUT
7039  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL
7040  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL
7041  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_LD_COMP
7042  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP
7043  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_ERASE_COMP
7044  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP
7045  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK
7046  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD
7047  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_INT_ACT
7048  * [13] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_RST_COMP
7049  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR
7050  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC
7051  * [16] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE
7052  * [31:17] | ??? | Unknown | *UNDEFINED*
7053  *
7054  */
7055 /*
7056  * Field : ecc_uncor_err
7057  *
7058  * Ecc logic detected uncorrectable error while reading data from flash device.
7059  *
7060  * Field Access Macros:
7061  *
7062  */
7063 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR register field. */
7064 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_LSB 0
7065 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR register field. */
7066 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_MSB 0
7067 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR register field. */
7068 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_WIDTH 1
7069 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR register field value. */
7070 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_SET_MSK 0x00000001
7071 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR register field value. */
7072 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
7073 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR register field. */
7074 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_RESET 0x0
7075 /* Extracts the ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR field value from a register. */
7076 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
7077 /* Produces a ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR register field value suitable for setting the register. */
7078 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
7079 
7080 /*
7081  * Field : dma_cmd_comp
7082  *
7083  * A data DMA command has completed on this bank
7084  *
7085  * Field Access Macros:
7086  *
7087  */
7088 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP register field. */
7089 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_LSB 2
7090 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP register field. */
7091 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_MSB 2
7092 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP register field. */
7093 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_WIDTH 1
7094 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP register field value. */
7095 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_SET_MSK 0x00000004
7096 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP register field value. */
7097 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_CLR_MSK 0xfffffffb
7098 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP register field. */
7099 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_RESET 0x0
7100 /* Extracts the ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP field value from a register. */
7101 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
7102 /* Produces a ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP register field value suitable for setting the register. */
7103 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
7104 
7105 /*
7106  * Field : time_out
7107  *
7108  * Watchdog timer has triggered in the controller due to one of the reasons like
7109  * device
7110  *
7111  * not responding or controller state machine did not get back to idle
7112  *
7113  * Field Access Macros:
7114  *
7115  */
7116 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_TIME_OUT register field. */
7117 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_LSB 3
7118 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_TIME_OUT register field. */
7119 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_MSB 3
7120 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_TIME_OUT register field. */
7121 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_WIDTH 1
7122 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_TIME_OUT register field value. */
7123 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_SET_MSK 0x00000008
7124 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_TIME_OUT register field value. */
7125 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_CLR_MSK 0xfffffff7
7126 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_TIME_OUT register field. */
7127 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_RESET 0x0
7128 /* Extracts the ALT_NAND_STAT_INTR_STAT1_TIME_OUT field value from a register. */
7129 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
7130 /* Produces a ALT_NAND_STAT_INTR_STAT1_TIME_OUT register field value suitable for setting the register. */
7131 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
7132 
7133 /*
7134  * Field : program_fail
7135  *
7136  * Program failure occurred in the device on issuance of a program command.
7137  * err_block_addr
7138  *
7139  * and err_page_addr contain the block address and page address that failed program
7140  * operation.
7141  *
7142  * Field Access Macros:
7143  *
7144  */
7145 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL register field. */
7146 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_LSB 4
7147 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL register field. */
7148 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_MSB 4
7149 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL register field. */
7150 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_WIDTH 1
7151 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL register field value. */
7152 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_SET_MSK 0x00000010
7153 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL register field value. */
7154 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_CLR_MSK 0xffffffef
7155 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL register field. */
7156 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_RESET 0x0
7157 /* Extracts the ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL field value from a register. */
7158 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
7159 /* Produces a ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL register field value suitable for setting the register. */
7160 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
7161 
7162 /*
7163  * Field : erase_fail
7164  *
7165  * Erase failure occurred in the device on issuance of a erase command.
7166  * err_block_addr
7167  *
7168  * and err_page_addr contain the block address and page address that failed erase
7169  * operation.
7170  *
7171  * Field Access Macros:
7172  *
7173  */
7174 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL register field. */
7175 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_LSB 5
7176 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL register field. */
7177 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_MSB 5
7178 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL register field. */
7179 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_WIDTH 1
7180 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL register field value. */
7181 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_SET_MSK 0x00000020
7182 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL register field value. */
7183 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_CLR_MSK 0xffffffdf
7184 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL register field. */
7185 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_RESET 0x0
7186 /* Extracts the ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL field value from a register. */
7187 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
7188 /* Produces a ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL register field value suitable for setting the register. */
7189 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
7190 
7191 /*
7192  * Field : load_comp
7193  *
7194  * Device finished the last issued load command.
7195  *
7196  * Field Access Macros:
7197  *
7198  */
7199 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_LD_COMP register field. */
7200 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_LSB 6
7201 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_LD_COMP register field. */
7202 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_MSB 6
7203 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_LD_COMP register field. */
7204 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_WIDTH 1
7205 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_LD_COMP register field value. */
7206 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_SET_MSK 0x00000040
7207 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_LD_COMP register field value. */
7208 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_CLR_MSK 0xffffffbf
7209 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_LD_COMP register field. */
7210 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_RESET 0x0
7211 /* Extracts the ALT_NAND_STAT_INTR_STAT1_LD_COMP field value from a register. */
7212 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
7213 /* Produces a ALT_NAND_STAT_INTR_STAT1_LD_COMP register field value suitable for setting the register. */
7214 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
7215 
7216 /*
7217  * Field : program_comp
7218  *
7219  * Device finished the last issued program command.
7220  *
7221  * Field Access Macros:
7222  *
7223  */
7224 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP register field. */
7225 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_LSB 7
7226 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP register field. */
7227 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_MSB 7
7228 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP register field. */
7229 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_WIDTH 1
7230 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP register field value. */
7231 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_SET_MSK 0x00000080
7232 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP register field value. */
7233 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_CLR_MSK 0xffffff7f
7234 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP register field. */
7235 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_RESET 0x0
7236 /* Extracts the ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP field value from a register. */
7237 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
7238 /* Produces a ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP register field value suitable for setting the register. */
7239 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
7240 
7241 /*
7242  * Field : erase_comp
7243  *
7244  * Device erase operation complete
7245  *
7246  * Field Access Macros:
7247  *
7248  */
7249 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_ERASE_COMP register field. */
7250 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_LSB 8
7251 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_ERASE_COMP register field. */
7252 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_MSB 8
7253 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_ERASE_COMP register field. */
7254 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_WIDTH 1
7255 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_ERASE_COMP register field value. */
7256 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_SET_MSK 0x00000100
7257 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_ERASE_COMP register field value. */
7258 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_CLR_MSK 0xfffffeff
7259 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_ERASE_COMP register field. */
7260 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_RESET 0x0
7261 /* Extracts the ALT_NAND_STAT_INTR_STAT1_ERASE_COMP field value from a register. */
7262 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
7263 /* Produces a ALT_NAND_STAT_INTR_STAT1_ERASE_COMP register field value suitable for setting the register. */
7264 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
7265 
7266 /*
7267  * Field : pipe_cpybck_cmd_comp
7268  *
7269  * A pipeline command or a copyback bank command has completed on this particular
7270  * bank
7271  *
7272  * Field Access Macros:
7273  *
7274  */
7275 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP register field. */
7276 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_LSB 9
7277 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP register field. */
7278 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_MSB 9
7279 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP register field. */
7280 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_WIDTH 1
7281 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP register field value. */
7282 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
7283 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP register field value. */
7284 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
7285 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP register field. */
7286 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_RESET 0x0
7287 /* Extracts the ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP field value from a register. */
7288 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
7289 /* Produces a ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
7290 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
7291 
7292 /*
7293  * Field : locked_blk
7294  *
7295  * The address to program or erase operation is to a locked block and the operation
7296  * failed
7297  *
7298  * due to this reason
7299  *
7300  * Field Access Macros:
7301  *
7302  */
7303 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK register field. */
7304 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_LSB 10
7305 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK register field. */
7306 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_MSB 10
7307 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK register field. */
7308 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_WIDTH 1
7309 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK register field value. */
7310 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_SET_MSK 0x00000400
7311 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK register field value. */
7312 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_CLR_MSK 0xfffffbff
7313 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK register field. */
7314 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_RESET 0x0
7315 /* Extracts the ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK field value from a register. */
7316 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
7317 /* Produces a ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK register field value suitable for setting the register. */
7318 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
7319 
7320 /*
7321  * Field : unsup_cmd
7322  *
7323  * An unsupported command was received. This interrupt is set when an invalid
7324  * command is
7325  *
7326  * received, or when a command sequence is broken.
7327  *
7328  * Field Access Macros:
7329  *
7330  */
7331 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD register field. */
7332 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_LSB 11
7333 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD register field. */
7334 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_MSB 11
7335 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD register field. */
7336 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_WIDTH 1
7337 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD register field value. */
7338 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_SET_MSK 0x00000800
7339 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD register field value. */
7340 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_CLR_MSK 0xfffff7ff
7341 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD register field. */
7342 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_RESET 0x0
7343 /* Extracts the ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD field value from a register. */
7344 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
7345 /* Produces a ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD register field value suitable for setting the register. */
7346 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
7347 
7348 /*
7349  * Field : int_act
7350  *
7351  * R/B pin of device transitioned from low to high
7352  *
7353  * Field Access Macros:
7354  *
7355  */
7356 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_INT_ACT register field. */
7357 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_LSB 12
7358 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_INT_ACT register field. */
7359 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_MSB 12
7360 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_INT_ACT register field. */
7361 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_WIDTH 1
7362 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_INT_ACT register field value. */
7363 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_SET_MSK 0x00001000
7364 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_INT_ACT register field value. */
7365 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_CLR_MSK 0xffffefff
7366 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_INT_ACT register field. */
7367 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_RESET 0x0
7368 /* Extracts the ALT_NAND_STAT_INTR_STAT1_INT_ACT field value from a register. */
7369 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
7370 /* Produces a ALT_NAND_STAT_INTR_STAT1_INT_ACT register field value suitable for setting the register. */
7371 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
7372 
7373 /*
7374  * Field : rst_comp
7375  *
7376  * The Cadence NAND Flash Memory Controller has completed its reset and
7377  * initialization process
7378  *
7379  * Field Access Macros:
7380  *
7381  */
7382 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_RST_COMP register field. */
7383 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_LSB 13
7384 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_RST_COMP register field. */
7385 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_MSB 13
7386 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_RST_COMP register field. */
7387 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_WIDTH 1
7388 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_RST_COMP register field value. */
7389 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_SET_MSK 0x00002000
7390 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_RST_COMP register field value. */
7391 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_CLR_MSK 0xffffdfff
7392 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_RST_COMP register field. */
7393 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_RESET 0x0
7394 /* Extracts the ALT_NAND_STAT_INTR_STAT1_RST_COMP field value from a register. */
7395 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
7396 /* Produces a ALT_NAND_STAT_INTR_STAT1_RST_COMP register field value suitable for setting the register. */
7397 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
7398 
7399 /*
7400  * Field : pipe_cmd_err
7401  *
7402  * A pipeline command sequence has been violated. This occurs when Map 01 page
7403  * read/write
7404  *
7405  * address does not match the corresponding expected address from the pipeline
7406  * commands issued
7407  *
7408  * earlier.
7409  *
7410  * Field Access Macros:
7411  *
7412  */
7413 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR register field. */
7414 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_LSB 14
7415 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR register field. */
7416 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_MSB 14
7417 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR register field. */
7418 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_WIDTH 1
7419 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR register field value. */
7420 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_SET_MSK 0x00004000
7421 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR register field value. */
7422 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
7423 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR register field. */
7424 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_RESET 0x0
7425 /* Extracts the ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR field value from a register. */
7426 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
7427 /* Produces a ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR register field value suitable for setting the register. */
7428 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
7429 
7430 /*
7431  * Field : page_xfer_inc
7432  *
7433  * For every page of data transfer to or from the device, this bit will be set.
7434  *
7435  * Field Access Macros:
7436  *
7437  */
7438 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC register field. */
7439 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_LSB 15
7440 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC register field. */
7441 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_MSB 15
7442 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC register field. */
7443 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_WIDTH 1
7444 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC register field value. */
7445 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_SET_MSK 0x00008000
7446 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC register field value. */
7447 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_CLR_MSK 0xffff7fff
7448 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC register field. */
7449 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_RESET 0x0
7450 /* Extracts the ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC field value from a register. */
7451 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
7452 /* Produces a ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC register field value suitable for setting the register. */
7453 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
7454 
7455 /*
7456  * Field : erased_page
7457  *
7458  * If an erased page is detected on reads, this bit will be set. The detection of
7459  * erased
7460  *
7461  * page is based on the number of 0's in the page. If the number of 0's in the page
7462  * being
7463  *
7464  * read is less than the value in the erase_threshold (programmable register),
7465  *
7466  * an erased page is inferred and no un-correctable error will be flagged for that
7467  * page.
7468  *
7469  * If ECC is disabled, the erased_page interrupt shall be set as explained above.
7470  * If ECC is
7471  *
7472  * enabled, in addition to the above condition, only when the ECC logic detects an
7473  *
7474  * un-correctable error for that page will the erased_page interrupt be flagged. If
7475  * the ECC
7476  *
7477  * logic detects a no-error or correctable error page, this erased page interrupt
7478  * will not
7479  *
7480  * be set.
7481  *
7482  * Field Access Macros:
7483  *
7484  */
7485 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE register field. */
7486 #define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_LSB 16
7487 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE register field. */
7488 #define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_MSB 16
7489 /* The width in bits of the ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE register field. */
7490 #define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_WIDTH 1
7491 /* The mask used to set the ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE register field value. */
7492 #define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_SET_MSK 0x00010000
7493 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE register field value. */
7494 #define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_CLR_MSK 0xfffeffff
7495 /* The reset value of the ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE register field. */
7496 #define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_RESET 0x0
7497 /* Extracts the ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE field value from a register. */
7498 #define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
7499 /* Produces a ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE register field value suitable for setting the register. */
7500 #define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
7501 
7502 #ifndef __ASSEMBLY__
7503 /*
7504  * WARNING: The C register and register group struct declarations are provided for
7505  * convenience and illustrative purposes. They should, however, be used with
7506  * caution as the C language standard provides no guarantees about the alignment or
7507  * atomicity of device memory accesses. The recommended practice for writing
7508  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7509  * alt_write_word() functions.
7510  *
7511  * The struct declaration for register ALT_NAND_STAT_INTR_STAT1.
7512  */
7513 struct ALT_NAND_STAT_INTR_STAT1_s
7514 {
7515  uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR */
7516  uint32_t : 1; /* *UNDEFINED* */
7517  uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP */
7518  uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_STAT1_TIME_OUT */
7519  uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL */
7520  uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL */
7521  uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_STAT1_LD_COMP */
7522  uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP */
7523  uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_STAT1_ERASE_COMP */
7524  uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP */
7525  uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK */
7526  uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD */
7527  uint32_t int_act : 1; /* ALT_NAND_STAT_INTR_STAT1_INT_ACT */
7528  uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_STAT1_RST_COMP */
7529  uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR */
7530  uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC */
7531  uint32_t erased_page : 1; /* ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE */
7532  uint32_t : 15; /* *UNDEFINED* */
7533 };
7534 
7535 /* The typedef declaration for register ALT_NAND_STAT_INTR_STAT1. */
7536 typedef volatile struct ALT_NAND_STAT_INTR_STAT1_s ALT_NAND_STAT_INTR_STAT1_t;
7537 #endif /* __ASSEMBLY__ */
7538 
7539 /* The reset value of the ALT_NAND_STAT_INTR_STAT1 register. */
7540 #define ALT_NAND_STAT_INTR_STAT1_RESET 0x00000000
7541 /* The byte offset of the ALT_NAND_STAT_INTR_STAT1 register from the beginning of the component. */
7542 #define ALT_NAND_STAT_INTR_STAT1_OFST 0x60
7543 
7544 /*
7545  * Register : intr_en1
7546  *
7547  * Enables corresponding interrupt bit in interrupt register
7548  *
7549  * for bank 1
7550  *
7551  * Register Layout
7552  *
7553  * Bits | Access | Reset | Description
7554  * :--------|:-------|:--------|:--------------------------------------------
7555  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR
7556  * [1] | ??? | Unknown | *UNDEFINED*
7557  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP
7558  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_TIME_OUT
7559  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL
7560  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_ERASE_FAIL
7561  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_LD_COMP
7562  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP
7563  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_ERASE_COMP
7564  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP
7565  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_LOCKED_BLK
7566  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_UNSUP_CMD
7567  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_INT_ACT
7568  * [13] | RW | 0x1 | ALT_NAND_STAT_INTR_EN1_RST_COMP
7569  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR
7570  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC
7571  * [16] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_ERASED_PAGE
7572  * [31:17] | ??? | Unknown | *UNDEFINED*
7573  *
7574  */
7575 /*
7576  * Field : ecc_uncor_err
7577  *
7578  * If set, Controller will interrupt processor when Ecc logic detects uncorrectable
7579  * error.
7580  *
7581  * Field Access Macros:
7582  *
7583  */
7584 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field. */
7585 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_LSB 0
7586 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field. */
7587 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_MSB 0
7588 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field. */
7589 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_WIDTH 1
7590 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field value. */
7591 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_SET_MSK 0x00000001
7592 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field value. */
7593 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
7594 /* The reset value of the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field. */
7595 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_RESET 0x0
7596 /* Extracts the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR field value from a register. */
7597 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
7598 /* Produces a ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field value suitable for setting the register. */
7599 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
7600 
7601 /*
7602  * Field : dma_cmd_comp
7603  *
7604  * A data DMA command has completed on this bank
7605  *
7606  * Field Access Macros:
7607  *
7608  */
7609 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field. */
7610 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_LSB 2
7611 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field. */
7612 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_MSB 2
7613 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field. */
7614 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_WIDTH 1
7615 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field value. */
7616 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_SET_MSK 0x00000004
7617 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field value. */
7618 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_CLR_MSK 0xfffffffb
7619 /* The reset value of the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field. */
7620 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_RESET 0x0
7621 /* Extracts the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP field value from a register. */
7622 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
7623 /* Produces a ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field value suitable for setting the register. */
7624 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
7625 
7626 /*
7627  * Field : time_out
7628  *
7629  * Watchdog timer has triggered in the controller due to one of the reasons like
7630  * device
7631  *
7632  * not responding or controller state machine did not get back to idle
7633  *
7634  * Field Access Macros:
7635  *
7636  */
7637 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field. */
7638 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_LSB 3
7639 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field. */
7640 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_MSB 3
7641 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field. */
7642 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_WIDTH 1
7643 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field value. */
7644 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_SET_MSK 0x00000008
7645 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field value. */
7646 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_CLR_MSK 0xfffffff7
7647 /* The reset value of the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field. */
7648 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_RESET 0x0
7649 /* Extracts the ALT_NAND_STAT_INTR_EN1_TIME_OUT field value from a register. */
7650 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
7651 /* Produces a ALT_NAND_STAT_INTR_EN1_TIME_OUT register field value suitable for setting the register. */
7652 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
7653 
7654 /*
7655  * Field : program_fail
7656  *
7657  * Program failure occurred in the device on issuance of a program command.
7658  * err_block_addr
7659  *
7660  * and err_page_addr contain the block address and page address that failed program
7661  * operation.
7662  *
7663  * Field Access Macros:
7664  *
7665  */
7666 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field. */
7667 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_LSB 4
7668 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field. */
7669 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_MSB 4
7670 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field. */
7671 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_WIDTH 1
7672 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field value. */
7673 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_SET_MSK 0x00000010
7674 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field value. */
7675 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_CLR_MSK 0xffffffef
7676 /* The reset value of the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field. */
7677 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_RESET 0x0
7678 /* Extracts the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL field value from a register. */
7679 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
7680 /* Produces a ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field value suitable for setting the register. */
7681 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
7682 
7683 /*
7684  * Field : erase_fail
7685  *
7686  * Erase failure occurred in the device on issuance of a erase command.
7687  * err_block_addr
7688  *
7689  * and err_page_addr contain the block address and page address that failed erase
7690  * operation.
7691  *
7692  * Field Access Macros:
7693  *
7694  */
7695 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field. */
7696 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_LSB 5
7697 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field. */
7698 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_MSB 5
7699 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field. */
7700 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_WIDTH 1
7701 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field value. */
7702 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_SET_MSK 0x00000020
7703 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field value. */
7704 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_CLR_MSK 0xffffffdf
7705 /* The reset value of the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field. */
7706 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_RESET 0x0
7707 /* Extracts the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL field value from a register. */
7708 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
7709 /* Produces a ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field value suitable for setting the register. */
7710 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
7711 
7712 /*
7713  * Field : load_comp
7714  *
7715  * Device finished the last issued load command.
7716  *
7717  * Field Access Macros:
7718  *
7719  */
7720 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_LD_COMP register field. */
7721 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_LSB 6
7722 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_LD_COMP register field. */
7723 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_MSB 6
7724 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_LD_COMP register field. */
7725 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_WIDTH 1
7726 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_LD_COMP register field value. */
7727 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_SET_MSK 0x00000040
7728 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_LD_COMP register field value. */
7729 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_CLR_MSK 0xffffffbf
7730 /* The reset value of the ALT_NAND_STAT_INTR_EN1_LD_COMP register field. */
7731 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_RESET 0x0
7732 /* Extracts the ALT_NAND_STAT_INTR_EN1_LD_COMP field value from a register. */
7733 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
7734 /* Produces a ALT_NAND_STAT_INTR_EN1_LD_COMP register field value suitable for setting the register. */
7735 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
7736 
7737 /*
7738  * Field : program_comp
7739  *
7740  * Device finished the last issued program command.
7741  *
7742  * Field Access Macros:
7743  *
7744  */
7745 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field. */
7746 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_LSB 7
7747 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field. */
7748 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_MSB 7
7749 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field. */
7750 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_WIDTH 1
7751 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field value. */
7752 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_SET_MSK 0x00000080
7753 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field value. */
7754 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_CLR_MSK 0xffffff7f
7755 /* The reset value of the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field. */
7756 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_RESET 0x0
7757 /* Extracts the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP field value from a register. */
7758 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
7759 /* Produces a ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field value suitable for setting the register. */
7760 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
7761 
7762 /*
7763  * Field : erase_comp
7764  *
7765  * Device erase operation complete
7766  *
7767  * Field Access Macros:
7768  *
7769  */
7770 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field. */
7771 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_LSB 8
7772 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field. */
7773 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_MSB 8
7774 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field. */
7775 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_WIDTH 1
7776 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field value. */
7777 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_SET_MSK 0x00000100
7778 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field value. */
7779 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_CLR_MSK 0xfffffeff
7780 /* The reset value of the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field. */
7781 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_RESET 0x0
7782 /* Extracts the ALT_NAND_STAT_INTR_EN1_ERASE_COMP field value from a register. */
7783 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
7784 /* Produces a ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field value suitable for setting the register. */
7785 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
7786 
7787 /*
7788  * Field : pipe_cpybck_cmd_comp
7789  *
7790  * A pipeline command or a copyback bank command has completed on this particular
7791  * bank
7792  *
7793  * Field Access Macros:
7794  *
7795  */
7796 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field. */
7797 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_LSB 9
7798 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field. */
7799 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_MSB 9
7800 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field. */
7801 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_WIDTH 1
7802 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field value. */
7803 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
7804 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field value. */
7805 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
7806 /* The reset value of the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field. */
7807 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_RESET 0x0
7808 /* Extracts the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP field value from a register. */
7809 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
7810 /* Produces a ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
7811 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
7812 
7813 /*
7814  * Field : locked_blk
7815  *
7816  * The address to program or erase operation is to a locked block and the operation
7817  * failed
7818  *
7819  * due to this reason
7820  *
7821  * Field Access Macros:
7822  *
7823  */
7824 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field. */
7825 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_LSB 10
7826 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field. */
7827 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_MSB 10
7828 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field. */
7829 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_WIDTH 1
7830 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field value. */
7831 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_SET_MSK 0x00000400
7832 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field value. */
7833 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_CLR_MSK 0xfffffbff
7834 /* The reset value of the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field. */
7835 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_RESET 0x0
7836 /* Extracts the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK field value from a register. */
7837 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
7838 /* Produces a ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field value suitable for setting the register. */
7839 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
7840 
7841 /*
7842  * Field : unsup_cmd
7843  *
7844  * An unsupported command was received. This interrupt is set when an invalid
7845  * command is
7846  *
7847  * received, or when a command sequence is broken.
7848  *
7849  * Field Access Macros:
7850  *
7851  */
7852 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field. */
7853 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_LSB 11
7854 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field. */
7855 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_MSB 11
7856 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field. */
7857 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_WIDTH 1
7858 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field value. */
7859 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_SET_MSK 0x00000800
7860 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field value. */
7861 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_CLR_MSK 0xfffff7ff
7862 /* The reset value of the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field. */
7863 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_RESET 0x0
7864 /* Extracts the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD field value from a register. */
7865 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
7866 /* Produces a ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field value suitable for setting the register. */
7867 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
7868 
7869 /*
7870  * Field : int_act
7871  *
7872  * R/B pin of device transitioned from low to high
7873  *
7874  * Field Access Macros:
7875  *
7876  */
7877 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_INT_ACT register field. */
7878 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_LSB 12
7879 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_INT_ACT register field. */
7880 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_MSB 12
7881 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_INT_ACT register field. */
7882 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_WIDTH 1
7883 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_INT_ACT register field value. */
7884 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_SET_MSK 0x00001000
7885 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_INT_ACT register field value. */
7886 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_CLR_MSK 0xffffefff
7887 /* The reset value of the ALT_NAND_STAT_INTR_EN1_INT_ACT register field. */
7888 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_RESET 0x0
7889 /* Extracts the ALT_NAND_STAT_INTR_EN1_INT_ACT field value from a register. */
7890 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
7891 /* Produces a ALT_NAND_STAT_INTR_EN1_INT_ACT register field value suitable for setting the register. */
7892 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
7893 
7894 /*
7895  * Field : rst_comp
7896  *
7897  * A reset command has completed on this bank
7898  *
7899  * Field Access Macros:
7900  *
7901  */
7902 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_RST_COMP register field. */
7903 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_LSB 13
7904 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_RST_COMP register field. */
7905 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_MSB 13
7906 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_RST_COMP register field. */
7907 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_WIDTH 1
7908 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_RST_COMP register field value. */
7909 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_SET_MSK 0x00002000
7910 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_RST_COMP register field value. */
7911 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_CLR_MSK 0xffffdfff
7912 /* The reset value of the ALT_NAND_STAT_INTR_EN1_RST_COMP register field. */
7913 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_RESET 0x1
7914 /* Extracts the ALT_NAND_STAT_INTR_EN1_RST_COMP field value from a register. */
7915 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
7916 /* Produces a ALT_NAND_STAT_INTR_EN1_RST_COMP register field value suitable for setting the register. */
7917 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
7918 
7919 /*
7920  * Field : pipe_cmd_err
7921  *
7922  * A pipeline command sequence has been violated. This occurs when Map 01 page
7923  * read/write
7924  *
7925  * address does not match the corresponding expected address from the pipeline
7926  * commands issued
7927  *
7928  * earlier.
7929  *
7930  * Field Access Macros:
7931  *
7932  */
7933 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field. */
7934 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_LSB 14
7935 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field. */
7936 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_MSB 14
7937 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field. */
7938 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_WIDTH 1
7939 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field value. */
7940 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_SET_MSK 0x00004000
7941 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field value. */
7942 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
7943 /* The reset value of the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field. */
7944 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_RESET 0x0
7945 /* Extracts the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR field value from a register. */
7946 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
7947 /* Produces a ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field value suitable for setting the register. */
7948 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
7949 
7950 /*
7951  * Field : page_xfer_inc
7952  *
7953  * For every page of data transfer to or from the device, this bit will be set.
7954  *
7955  * Field Access Macros:
7956  *
7957  */
7958 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field. */
7959 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_LSB 15
7960 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field. */
7961 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_MSB 15
7962 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field. */
7963 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_WIDTH 1
7964 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field value. */
7965 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_SET_MSK 0x00008000
7966 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field value. */
7967 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_CLR_MSK 0xffff7fff
7968 /* The reset value of the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field. */
7969 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_RESET 0x0
7970 /* Extracts the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC field value from a register. */
7971 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
7972 /* Produces a ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field value suitable for setting the register. */
7973 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
7974 
7975 /*
7976  * Field : erased_page
7977  *
7978  * If an erased page is detected on reads, this bit will be set. The detection of
7979  * erased
7980  *
7981  * page is based on the number of 0's in the page. If the number of 0's in the page
7982  * being
7983  *
7984  * read is less than the value in the erase_threshold (programmable register),
7985  *
7986  * an erased page is inferred and no un-correctable error will be flagged for that
7987  * page.
7988  *
7989  * If ECC is disabled, the erased_page interrupt shall be set as explained above.
7990  * If ECC is
7991  *
7992  * enabled, in addition to the above condition, only when the ECC logic detects an
7993  *
7994  * un-correctable error for that page will the erased_page interrupt be flagged. If
7995  * the ECC
7996  *
7997  * logic detects a no-error or correctable error page, this erased page interrupt
7998  * will not
7999  *
8000  * be set.
8001  *
8002  * Field Access Macros:
8003  *
8004  */
8005 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_ERASED_PAGE register field. */
8006 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_LSB 16
8007 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_ERASED_PAGE register field. */
8008 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_MSB 16
8009 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_ERASED_PAGE register field. */
8010 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_WIDTH 1
8011 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_ERASED_PAGE register field value. */
8012 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_SET_MSK 0x00010000
8013 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_ERASED_PAGE register field value. */
8014 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_CLR_MSK 0xfffeffff
8015 /* The reset value of the ALT_NAND_STAT_INTR_EN1_ERASED_PAGE register field. */
8016 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_RESET 0x0
8017 /* Extracts the ALT_NAND_STAT_INTR_EN1_ERASED_PAGE field value from a register. */
8018 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
8019 /* Produces a ALT_NAND_STAT_INTR_EN1_ERASED_PAGE register field value suitable for setting the register. */
8020 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
8021 
8022 #ifndef __ASSEMBLY__
8023 /*
8024  * WARNING: The C register and register group struct declarations are provided for
8025  * convenience and illustrative purposes. They should, however, be used with
8026  * caution as the C language standard provides no guarantees about the alignment or
8027  * atomicity of device memory accesses. The recommended practice for writing
8028  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8029  * alt_write_word() functions.
8030  *
8031  * The struct declaration for register ALT_NAND_STAT_INTR_EN1.
8032  */
8033 struct ALT_NAND_STAT_INTR_EN1_s
8034 {
8035  uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR */
8036  uint32_t : 1; /* *UNDEFINED* */
8037  uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP */
8038  uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_EN1_TIME_OUT */
8039  uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL */
8040  uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_EN1_ERASE_FAIL */
8041  uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_EN1_LD_COMP */
8042  uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP */
8043  uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_EN1_ERASE_COMP */
8044  uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP */
8045  uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_EN1_LOCKED_BLK */
8046  uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_EN1_UNSUP_CMD */
8047  uint32_t int_act : 1; /* ALT_NAND_STAT_INTR_EN1_INT_ACT */
8048  uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_EN1_RST_COMP */
8049  uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR */
8050  uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC */
8051  uint32_t erased_page : 1; /* ALT_NAND_STAT_INTR_EN1_ERASED_PAGE */
8052  uint32_t : 15; /* *UNDEFINED* */
8053 };
8054 
8055 /* The typedef declaration for register ALT_NAND_STAT_INTR_EN1. */
8056 typedef volatile struct ALT_NAND_STAT_INTR_EN1_s ALT_NAND_STAT_INTR_EN1_t;
8057 #endif /* __ASSEMBLY__ */
8058 
8059 /* The reset value of the ALT_NAND_STAT_INTR_EN1 register. */
8060 #define ALT_NAND_STAT_INTR_EN1_RESET 0x00002000
8061 /* The byte offset of the ALT_NAND_STAT_INTR_EN1 register from the beginning of the component. */
8062 #define ALT_NAND_STAT_INTR_EN1_OFST 0x70
8063 
8064 /*
8065  * Register : page_cnt1
8066  *
8067  * Decrementing page count bank 1
8068  *
8069  * Register Layout
8070  *
8071  * Bits | Access | Reset | Description
8072  * :-------|:-------|:--------|:------------------------------
8073  * [7:0] | R | 0x0 | ALT_NAND_STAT_PAGE_CNT1_VALUE
8074  * [31:8] | ??? | Unknown | *UNDEFINED*
8075  *
8076  */
8077 /*
8078  * Field : value
8079  *
8080  * Maintains a decrementing count of the number of pages in
8081  *
8082  * the multi-page (pipeline and copyback) command being executed.
8083  *
8084  * Field Access Macros:
8085  *
8086  */
8087 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_PAGE_CNT1_VALUE register field. */
8088 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_LSB 0
8089 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_PAGE_CNT1_VALUE register field. */
8090 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_MSB 7
8091 /* The width in bits of the ALT_NAND_STAT_PAGE_CNT1_VALUE register field. */
8092 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_WIDTH 8
8093 /* The mask used to set the ALT_NAND_STAT_PAGE_CNT1_VALUE register field value. */
8094 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_SET_MSK 0x000000ff
8095 /* The mask used to clear the ALT_NAND_STAT_PAGE_CNT1_VALUE register field value. */
8096 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_CLR_MSK 0xffffff00
8097 /* The reset value of the ALT_NAND_STAT_PAGE_CNT1_VALUE register field. */
8098 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_RESET 0x0
8099 /* Extracts the ALT_NAND_STAT_PAGE_CNT1_VALUE field value from a register. */
8100 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
8101 /* Produces a ALT_NAND_STAT_PAGE_CNT1_VALUE register field value suitable for setting the register. */
8102 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_SET(value) (((value) << 0) & 0x000000ff)
8103 
8104 #ifndef __ASSEMBLY__
8105 /*
8106  * WARNING: The C register and register group struct declarations are provided for
8107  * convenience and illustrative purposes. They should, however, be used with
8108  * caution as the C language standard provides no guarantees about the alignment or
8109  * atomicity of device memory accesses. The recommended practice for writing
8110  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8111  * alt_write_word() functions.
8112  *
8113  * The struct declaration for register ALT_NAND_STAT_PAGE_CNT1.
8114  */
8115 struct ALT_NAND_STAT_PAGE_CNT1_s
8116 {
8117  const uint32_t value : 8; /* ALT_NAND_STAT_PAGE_CNT1_VALUE */
8118  uint32_t : 24; /* *UNDEFINED* */
8119 };
8120 
8121 /* The typedef declaration for register ALT_NAND_STAT_PAGE_CNT1. */
8122 typedef volatile struct ALT_NAND_STAT_PAGE_CNT1_s ALT_NAND_STAT_PAGE_CNT1_t;
8123 #endif /* __ASSEMBLY__ */
8124 
8125 /* The reset value of the ALT_NAND_STAT_PAGE_CNT1 register. */
8126 #define ALT_NAND_STAT_PAGE_CNT1_RESET 0x00000000
8127 /* The byte offset of the ALT_NAND_STAT_PAGE_CNT1 register from the beginning of the component. */
8128 #define ALT_NAND_STAT_PAGE_CNT1_OFST 0x80
8129 
8130 /*
8131  * Register : err_page_addr1
8132  *
8133  * Erred page address bank 1
8134  *
8135  * Register Layout
8136  *
8137  * Bits | Access | Reset | Description
8138  * :--------|:-------|:--------|:-----------------------------------
8139  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE
8140  * [31:16] | ??? | Unknown | *UNDEFINED*
8141  *
8142  */
8143 /*
8144  * Field : value
8145  *
8146  * Holds the page address that resulted in a failure on program
8147  *
8148  * or erase operation.
8149  *
8150  * Field Access Macros:
8151  *
8152  */
8153 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field. */
8154 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_LSB 0
8155 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field. */
8156 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_MSB 15
8157 /* The width in bits of the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field. */
8158 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_WIDTH 16
8159 /* The mask used to set the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field value. */
8160 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_SET_MSK 0x0000ffff
8161 /* The mask used to clear the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field value. */
8162 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_CLR_MSK 0xffff0000
8163 /* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field. */
8164 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_RESET 0x0
8165 /* Extracts the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE field value from a register. */
8166 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
8167 /* Produces a ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field value suitable for setting the register. */
8168 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
8169 
8170 #ifndef __ASSEMBLY__
8171 /*
8172  * WARNING: The C register and register group struct declarations are provided for
8173  * convenience and illustrative purposes. They should, however, be used with
8174  * caution as the C language standard provides no guarantees about the alignment or
8175  * atomicity of device memory accesses. The recommended practice for writing
8176  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8177  * alt_write_word() functions.
8178  *
8179  * The struct declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR1.
8180  */
8181 struct ALT_NAND_STAT_ERR_PAGE_ADDR1_s
8182 {
8183  const uint32_t value : 16; /* ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE */
8184  uint32_t : 16; /* *UNDEFINED* */
8185 };
8186 
8187 /* The typedef declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR1. */
8188 typedef volatile struct ALT_NAND_STAT_ERR_PAGE_ADDR1_s ALT_NAND_STAT_ERR_PAGE_ADDR1_t;
8189 #endif /* __ASSEMBLY__ */
8190 
8191 /* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR1 register. */
8192 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_RESET 0x00000000
8193 /* The byte offset of the ALT_NAND_STAT_ERR_PAGE_ADDR1 register from the beginning of the component. */
8194 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_OFST 0x90
8195 
8196 /*
8197  * Register : err_block_addr1
8198  *
8199  * Erred block address bank 1
8200  *
8201  * Register Layout
8202  *
8203  * Bits | Access | Reset | Description
8204  * :--------|:-------|:--------|:------------------------------------
8205  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE
8206  * [31:16] | ??? | Unknown | *UNDEFINED*
8207  *
8208  */
8209 /*
8210  * Field : value
8211  *
8212  * Holds the block address that resulted in a failure on program
8213  *
8214  * or erase operation.
8215  *
8216  * Field Access Macros:
8217  *
8218  */
8219 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field. */
8220 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_LSB 0
8221 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field. */
8222 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_MSB 15
8223 /* The width in bits of the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field. */
8224 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_WIDTH 16
8225 /* The mask used to set the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field value. */
8226 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_SET_MSK 0x0000ffff
8227 /* The mask used to clear the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field value. */
8228 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_CLR_MSK 0xffff0000
8229 /* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field. */
8230 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_RESET 0x0
8231 /* Extracts the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE field value from a register. */
8232 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
8233 /* Produces a ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field value suitable for setting the register. */
8234 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
8235 
8236 #ifndef __ASSEMBLY__
8237 /*
8238  * WARNING: The C register and register group struct declarations are provided for
8239  * convenience and illustrative purposes. They should, however, be used with
8240  * caution as the C language standard provides no guarantees about the alignment or
8241  * atomicity of device memory accesses. The recommended practice for writing
8242  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8243  * alt_write_word() functions.
8244  *
8245  * The struct declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR1.
8246  */
8247 struct ALT_NAND_STAT_ERR_BLOCK_ADDR1_s
8248 {
8249  const uint32_t value : 16; /* ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE */
8250  uint32_t : 16; /* *UNDEFINED* */
8251 };
8252 
8253 /* The typedef declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR1. */
8254 typedef volatile struct ALT_NAND_STAT_ERR_BLOCK_ADDR1_s ALT_NAND_STAT_ERR_BLOCK_ADDR1_t;
8255 #endif /* __ASSEMBLY__ */
8256 
8257 /* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR1 register. */
8258 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_RESET 0x00000000
8259 /* The byte offset of the ALT_NAND_STAT_ERR_BLOCK_ADDR1 register from the beginning of the component. */
8260 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_OFST 0xa0
8261 
8262 /*
8263  * Register : intr_status2
8264  *
8265  * Interrupt status register for bank 2
8266  *
8267  * Register Layout
8268  *
8269  * Bits | Access | Reset | Description
8270  * :--------|:-------|:--------|:----------------------------------------------
8271  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR
8272  * [1] | ??? | Unknown | *UNDEFINED*
8273  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP
8274  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_TIME_OUT
8275  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL
8276  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL
8277  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_LD_COMP
8278  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP
8279  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_ERASE_COMP
8280  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP
8281  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK
8282  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD
8283  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_INT_ACT
8284  * [13] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_RST_COMP
8285  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR
8286  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC
8287  * [16] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE
8288  * [31:17] | ??? | Unknown | *UNDEFINED*
8289  *
8290  */
8291 /*
8292  * Field : ecc_uncor_err
8293  *
8294  * Ecc logic detected uncorrectable error while reading data from flash device.
8295  *
8296  * Field Access Macros:
8297  *
8298  */
8299 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR register field. */
8300 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_LSB 0
8301 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR register field. */
8302 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_MSB 0
8303 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR register field. */
8304 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_WIDTH 1
8305 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR register field value. */
8306 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_SET_MSK 0x00000001
8307 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR register field value. */
8308 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
8309 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR register field. */
8310 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_RESET 0x0
8311 /* Extracts the ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR field value from a register. */
8312 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
8313 /* Produces a ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR register field value suitable for setting the register. */
8314 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
8315 
8316 /*
8317  * Field : dma_cmd_comp
8318  *
8319  * A data DMA command has completed on this bank
8320  *
8321  * Field Access Macros:
8322  *
8323  */
8324 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP register field. */
8325 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_LSB 2
8326 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP register field. */
8327 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_MSB 2
8328 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP register field. */
8329 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_WIDTH 1
8330 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP register field value. */
8331 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_SET_MSK 0x00000004
8332 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP register field value. */
8333 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_CLR_MSK 0xfffffffb
8334 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP register field. */
8335 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_RESET 0x0
8336 /* Extracts the ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP field value from a register. */
8337 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
8338 /* Produces a ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP register field value suitable for setting the register. */
8339 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
8340 
8341 /*
8342  * Field : time_out
8343  *
8344  * Watchdog timer has triggered in the controller due to one of the reasons like
8345  * device
8346  *
8347  * not responding or controller state machine did not get back to idle
8348  *
8349  * Field Access Macros:
8350  *
8351  */
8352 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_TIME_OUT register field. */
8353 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_LSB 3
8354 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_TIME_OUT register field. */
8355 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_MSB 3
8356 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_TIME_OUT register field. */
8357 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_WIDTH 1
8358 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_TIME_OUT register field value. */
8359 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_SET_MSK 0x00000008
8360 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_TIME_OUT register field value. */
8361 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_CLR_MSK 0xfffffff7
8362 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_TIME_OUT register field. */
8363 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_RESET 0x0
8364 /* Extracts the ALT_NAND_STAT_INTR_STAT2_TIME_OUT field value from a register. */
8365 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
8366 /* Produces a ALT_NAND_STAT_INTR_STAT2_TIME_OUT register field value suitable for setting the register. */
8367 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
8368 
8369 /*
8370  * Field : program_fail
8371  *
8372  * Program failure occurred in the device on issuance of a program command.
8373  * err_block_addr
8374  *
8375  * and err_page_addr contain the block address and page address that failed program
8376  * operation.
8377  *
8378  * Field Access Macros:
8379  *
8380  */
8381 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL register field. */
8382 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_LSB 4
8383 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL register field. */
8384 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_MSB 4
8385 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL register field. */
8386 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_WIDTH 1
8387 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL register field value. */
8388 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_SET_MSK 0x00000010
8389 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL register field value. */
8390 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_CLR_MSK 0xffffffef
8391 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL register field. */
8392 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_RESET 0x0
8393 /* Extracts the ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL field value from a register. */
8394 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
8395 /* Produces a ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL register field value suitable for setting the register. */
8396 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
8397 
8398 /*
8399  * Field : erase_fail
8400  *
8401  * Erase failure occurred in the device on issuance of a erase command.
8402  * err_block_addr
8403  *
8404  * and err_page_addr contain the block address and page address that failed erase
8405  * operation.
8406  *
8407  * Field Access Macros:
8408  *
8409  */
8410 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL register field. */
8411 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_LSB 5
8412 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL register field. */
8413 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_MSB 5
8414 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL register field. */
8415 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_WIDTH 1
8416 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL register field value. */
8417 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_SET_MSK 0x00000020
8418 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL register field value. */
8419 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_CLR_MSK 0xffffffdf
8420 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL register field. */
8421 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_RESET 0x0
8422 /* Extracts the ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL field value from a register. */
8423 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
8424 /* Produces a ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL register field value suitable for setting the register. */
8425 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
8426 
8427 /*
8428  * Field : load_comp
8429  *
8430  * Device finished the last issued load command.
8431  *
8432  * Field Access Macros:
8433  *
8434  */
8435 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_LD_COMP register field. */
8436 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_LSB 6
8437 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_LD_COMP register field. */
8438 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_MSB 6
8439 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_LD_COMP register field. */
8440 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_WIDTH 1
8441 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_LD_COMP register field value. */
8442 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_SET_MSK 0x00000040
8443 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_LD_COMP register field value. */
8444 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_CLR_MSK 0xffffffbf
8445 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_LD_COMP register field. */
8446 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_RESET 0x0
8447 /* Extracts the ALT_NAND_STAT_INTR_STAT2_LD_COMP field value from a register. */
8448 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
8449 /* Produces a ALT_NAND_STAT_INTR_STAT2_LD_COMP register field value suitable for setting the register. */
8450 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
8451 
8452 /*
8453  * Field : program_comp
8454  *
8455  * Device finished the last issued program command.
8456  *
8457  * Field Access Macros:
8458  *
8459  */
8460 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP register field. */
8461 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_LSB 7
8462 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP register field. */
8463 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_MSB 7
8464 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP register field. */
8465 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_WIDTH 1
8466 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP register field value. */
8467 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_SET_MSK 0x00000080
8468 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP register field value. */
8469 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_CLR_MSK 0xffffff7f
8470 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP register field. */
8471 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_RESET 0x0
8472 /* Extracts the ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP field value from a register. */
8473 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
8474 /* Produces a ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP register field value suitable for setting the register. */
8475 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
8476 
8477 /*
8478  * Field : erase_comp
8479  *
8480  * Device erase operation complete
8481  *
8482  * Field Access Macros:
8483  *
8484  */
8485 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_ERASE_COMP register field. */
8486 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_LSB 8
8487 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_ERASE_COMP register field. */
8488 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_MSB 8
8489 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_ERASE_COMP register field. */
8490 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_WIDTH 1
8491 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_ERASE_COMP register field value. */
8492 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_SET_MSK 0x00000100
8493 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_ERASE_COMP register field value. */
8494 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_CLR_MSK 0xfffffeff
8495 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_ERASE_COMP register field. */
8496 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_RESET 0x0
8497 /* Extracts the ALT_NAND_STAT_INTR_STAT2_ERASE_COMP field value from a register. */
8498 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
8499 /* Produces a ALT_NAND_STAT_INTR_STAT2_ERASE_COMP register field value suitable for setting the register. */
8500 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
8501 
8502 /*
8503  * Field : pipe_cpybck_cmd_comp
8504  *
8505  * A pipeline command or a copyback bank command has completed on this particular
8506  * bank
8507  *
8508  * Field Access Macros:
8509  *
8510  */
8511 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP register field. */
8512 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_LSB 9
8513 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP register field. */
8514 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_MSB 9
8515 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP register field. */
8516 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_WIDTH 1
8517 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP register field value. */
8518 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
8519 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP register field value. */
8520 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
8521 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP register field. */
8522 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_RESET 0x0
8523 /* Extracts the ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP field value from a register. */
8524 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
8525 /* Produces a ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
8526 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
8527 
8528 /*
8529  * Field : locked_blk
8530  *
8531  * The address to program or erase operation is to a locked block and the operation
8532  * failed
8533  *
8534  * due to this reason
8535  *
8536  * Field Access Macros:
8537  *
8538  */
8539 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK register field. */
8540 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_LSB 10
8541 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK register field. */
8542 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_MSB 10
8543 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK register field. */
8544 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_WIDTH 1
8545 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK register field value. */
8546 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_SET_MSK 0x00000400
8547 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK register field value. */
8548 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_CLR_MSK 0xfffffbff
8549 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK register field. */
8550 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_RESET 0x0
8551 /* Extracts the ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK field value from a register. */
8552 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
8553 /* Produces a ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK register field value suitable for setting the register. */
8554 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
8555 
8556 /*
8557  * Field : unsup_cmd
8558  *
8559  * An unsupported command was received. This interrupt is set when an invalid
8560  * command is
8561  *
8562  * received, or when a command sequence is broken.
8563  *
8564  * Field Access Macros:
8565  *
8566  */
8567 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD register field. */
8568 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_LSB 11
8569 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD register field. */
8570 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_MSB 11
8571 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD register field. */
8572 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_WIDTH 1
8573 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD register field value. */
8574 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_SET_MSK 0x00000800
8575 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD register field value. */
8576 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_CLR_MSK 0xfffff7ff
8577 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD register field. */
8578 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_RESET 0x0
8579 /* Extracts the ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD field value from a register. */
8580 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
8581 /* Produces a ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD register field value suitable for setting the register. */
8582 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
8583 
8584 /*
8585  * Field : int_act
8586  *
8587  * R/B pin of device transitioned from low to high
8588  *
8589  * Field Access Macros:
8590  *
8591  */
8592 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_INT_ACT register field. */
8593 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_LSB 12
8594 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_INT_ACT register field. */
8595 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_MSB 12
8596 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_INT_ACT register field. */
8597 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_WIDTH 1
8598 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_INT_ACT register field value. */
8599 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_SET_MSK 0x00001000
8600 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_INT_ACT register field value. */
8601 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_CLR_MSK 0xffffefff
8602 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_INT_ACT register field. */
8603 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_RESET 0x0
8604 /* Extracts the ALT_NAND_STAT_INTR_STAT2_INT_ACT field value from a register. */
8605 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
8606 /* Produces a ALT_NAND_STAT_INTR_STAT2_INT_ACT register field value suitable for setting the register. */
8607 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
8608 
8609 /*
8610  * Field : rst_comp
8611  *
8612  * The Cadence NAND Flash Memory Controller has completed its reset and
8613  * initialization process
8614  *
8615  * Field Access Macros:
8616  *
8617  */
8618 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_RST_COMP register field. */
8619 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_LSB 13
8620 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_RST_COMP register field. */
8621 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_MSB 13
8622 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_RST_COMP register field. */
8623 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_WIDTH 1
8624 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_RST_COMP register field value. */
8625 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_SET_MSK 0x00002000
8626 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_RST_COMP register field value. */
8627 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_CLR_MSK 0xffffdfff
8628 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_RST_COMP register field. */
8629 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_RESET 0x0
8630 /* Extracts the ALT_NAND_STAT_INTR_STAT2_RST_COMP field value from a register. */
8631 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
8632 /* Produces a ALT_NAND_STAT_INTR_STAT2_RST_COMP register field value suitable for setting the register. */
8633 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
8634 
8635 /*
8636  * Field : pipe_cmd_err
8637  *
8638  * A pipeline command sequence has been violated. This occurs when Map 01 page
8639  * read/write
8640  *
8641  * address does not match the corresponding expected address from the pipeline
8642  * commands issued
8643  *
8644  * earlier.
8645  *
8646  * Field Access Macros:
8647  *
8648  */
8649 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR register field. */
8650 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_LSB 14
8651 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR register field. */
8652 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_MSB 14
8653 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR register field. */
8654 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_WIDTH 1
8655 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR register field value. */
8656 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_SET_MSK 0x00004000
8657 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR register field value. */
8658 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
8659 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR register field. */
8660 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_RESET 0x0
8661 /* Extracts the ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR field value from a register. */
8662 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
8663 /* Produces a ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR register field value suitable for setting the register. */
8664 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
8665 
8666 /*
8667  * Field : page_xfer_inc
8668  *
8669  * For every page of data transfer to or from the device, this bit will be set.
8670  *
8671  * Field Access Macros:
8672  *
8673  */
8674 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC register field. */
8675 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_LSB 15
8676 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC register field. */
8677 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_MSB 15
8678 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC register field. */
8679 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_WIDTH 1
8680 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC register field value. */
8681 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_SET_MSK 0x00008000
8682 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC register field value. */
8683 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_CLR_MSK 0xffff7fff
8684 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC register field. */
8685 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_RESET 0x0
8686 /* Extracts the ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC field value from a register. */
8687 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
8688 /* Produces a ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC register field value suitable for setting the register. */
8689 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
8690 
8691 /*
8692  * Field : erased_page
8693  *
8694  * If an erased page is detected on reads, this bit will be set. The detection of
8695  * erased
8696  *
8697  * page is based on the number of 0's in the page. If the number of 0's in the page
8698  * being
8699  *
8700  * read is less than the value in the erase_threshold (programmable register),
8701  *
8702  * an erased page is inferred and no un-correctable error will be flagged for that
8703  * page.
8704  *
8705  * If ECC is disabled, the erased_page interrupt shall be set as explained above.
8706  * If ECC is
8707  *
8708  * enabled, in addition to the above condition, only when the ECC logic detects an
8709  *
8710  * un-correctable error for that page will the erased_page interrupt be flagged. If
8711  * the ECC
8712  *
8713  * logic detects a no-error or correctable error page, this erased page interrupt
8714  * will not
8715  *
8716  * be set.
8717  *
8718  * Field Access Macros:
8719  *
8720  */
8721 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE register field. */
8722 #define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_LSB 16
8723 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE register field. */
8724 #define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_MSB 16
8725 /* The width in bits of the ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE register field. */
8726 #define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_WIDTH 1
8727 /* The mask used to set the ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE register field value. */
8728 #define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_SET_MSK 0x00010000
8729 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE register field value. */
8730 #define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_CLR_MSK 0xfffeffff
8731 /* The reset value of the ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE register field. */
8732 #define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_RESET 0x0
8733 /* Extracts the ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE field value from a register. */
8734 #define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
8735 /* Produces a ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE register field value suitable for setting the register. */
8736 #define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
8737 
8738 #ifndef __ASSEMBLY__
8739 /*
8740  * WARNING: The C register and register group struct declarations are provided for
8741  * convenience and illustrative purposes. They should, however, be used with
8742  * caution as the C language standard provides no guarantees about the alignment or
8743  * atomicity of device memory accesses. The recommended practice for writing
8744  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8745  * alt_write_word() functions.
8746  *
8747  * The struct declaration for register ALT_NAND_STAT_INTR_STAT2.
8748  */
8749 struct ALT_NAND_STAT_INTR_STAT2_s
8750 {
8751  uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR */
8752  uint32_t : 1; /* *UNDEFINED* */
8753  uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP */
8754  uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_STAT2_TIME_OUT */
8755  uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL */
8756  uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL */
8757  uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_STAT2_LD_COMP */
8758  uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP */
8759  uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_STAT2_ERASE_COMP */
8760  uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP */
8761  uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK */
8762  uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD */
8763  uint32_t int_act : 1; /* ALT_NAND_STAT_INTR_STAT2_INT_ACT */
8764  uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_STAT2_RST_COMP */
8765  uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR */
8766  uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC */
8767  uint32_t erased_page : 1; /* ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE */
8768  uint32_t : 15; /* *UNDEFINED* */
8769 };
8770 
8771 /* The typedef declaration for register ALT_NAND_STAT_INTR_STAT2. */
8772 typedef volatile struct ALT_NAND_STAT_INTR_STAT2_s ALT_NAND_STAT_INTR_STAT2_t;
8773 #endif /* __ASSEMBLY__ */
8774 
8775 /* The reset value of the ALT_NAND_STAT_INTR_STAT2 register. */
8776 #define ALT_NAND_STAT_INTR_STAT2_RESET 0x00000000
8777 /* The byte offset of the ALT_NAND_STAT_INTR_STAT2 register from the beginning of the component. */
8778 #define ALT_NAND_STAT_INTR_STAT2_OFST 0xb0
8779 
8780 /*
8781  * Register : intr_en2
8782  *
8783  * Enables corresponding interrupt bit in interrupt register
8784  *
8785  * for bank 2
8786  *
8787  * Register Layout
8788  *
8789  * Bits | Access | Reset | Description
8790  * :--------|:-------|:--------|:--------------------------------------------
8791  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR
8792  * [1] | ??? | Unknown | *UNDEFINED*
8793  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP
8794  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_TIME_OUT
8795  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL
8796  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_ERASE_FAIL
8797  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_LD_COMP
8798  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP
8799  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_ERASE_COMP
8800  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP
8801  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_LOCKED_BLK
8802  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_UNSUP_CMD
8803  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_INT_ACT
8804  * [13] | RW | 0x1 | ALT_NAND_STAT_INTR_EN2_RST_COMP
8805  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR
8806  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC
8807  * [16] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_ERASED_PAGE
8808  * [31:17] | ??? | Unknown | *UNDEFINED*
8809  *
8810  */
8811 /*
8812  * Field : ecc_uncor_err
8813  *
8814  * If set, Controller will interrupt processor when Ecc logic detects uncorrectable
8815  * error.
8816  *
8817  * Field Access Macros:
8818  *
8819  */
8820 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field. */
8821 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_LSB 0
8822 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field. */
8823 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_MSB 0
8824 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field. */
8825 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_WIDTH 1
8826 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field value. */
8827 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_SET_MSK 0x00000001
8828 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field value. */
8829 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
8830 /* The reset value of the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field. */
8831 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_RESET 0x0
8832 /* Extracts the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR field value from a register. */
8833 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
8834 /* Produces a ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field value suitable for setting the register. */
8835 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
8836 
8837 /*
8838  * Field : dma_cmd_comp
8839  *
8840  * A data DMA command has completed on this bank
8841  *
8842  * Field Access Macros:
8843  *
8844  */
8845 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field. */
8846 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_LSB 2
8847 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field. */
8848 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_MSB 2
8849 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field. */
8850 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_WIDTH 1
8851 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field value. */
8852 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_SET_MSK 0x00000004
8853 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field value. */
8854 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_CLR_MSK 0xfffffffb
8855 /* The reset value of the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field. */
8856 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_RESET 0x0
8857 /* Extracts the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP field value from a register. */
8858 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
8859 /* Produces a ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field value suitable for setting the register. */
8860 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
8861 
8862 /*
8863  * Field : time_out
8864  *
8865  * Watchdog timer has triggered in the controller due to one of the reasons like
8866  * device
8867  *
8868  * not responding or controller state machine did not get back to idle
8869  *
8870  * Field Access Macros:
8871  *
8872  */
8873 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field. */
8874 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_LSB 3
8875 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field. */
8876 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_MSB 3
8877 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field. */
8878 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_WIDTH 1
8879 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field value. */
8880 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_SET_MSK 0x00000008
8881 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field value. */
8882 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_CLR_MSK 0xfffffff7
8883 /* The reset value of the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field. */
8884 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_RESET 0x0
8885 /* Extracts the ALT_NAND_STAT_INTR_EN2_TIME_OUT field value from a register. */
8886 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
8887 /* Produces a ALT_NAND_STAT_INTR_EN2_TIME_OUT register field value suitable for setting the register. */
8888 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
8889 
8890 /*
8891  * Field : program_fail
8892  *
8893  * Program failure occurred in the device on issuance of a program command.
8894  * err_block_addr
8895  *
8896  * and err_page_addr contain the block address and page address that failed program
8897  * operation.
8898  *
8899  * Field Access Macros:
8900  *
8901  */
8902 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field. */
8903 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_LSB 4
8904 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field. */
8905 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_MSB 4
8906 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field. */
8907 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_WIDTH 1
8908 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field value. */
8909 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_SET_MSK 0x00000010
8910 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field value. */
8911 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_CLR_MSK 0xffffffef
8912 /* The reset value of the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field. */
8913 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_RESET 0x0
8914 /* Extracts the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL field value from a register. */
8915 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
8916 /* Produces a ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field value suitable for setting the register. */
8917 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
8918 
8919 /*
8920  * Field : erase_fail
8921  *
8922  * Erase failure occurred in the device on issuance of a erase command.
8923  * err_block_addr
8924  *
8925  * and err_page_addr contain the block address and page address that failed erase
8926  * operation.
8927  *
8928  * Field Access Macros:
8929  *
8930  */
8931 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field. */
8932 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_LSB 5
8933 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field. */
8934 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_MSB 5
8935 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field. */
8936 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_WIDTH 1
8937 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field value. */
8938 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_SET_MSK 0x00000020
8939 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field value. */
8940 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_CLR_MSK 0xffffffdf
8941 /* The reset value of the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field. */
8942 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_RESET 0x0
8943 /* Extracts the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL field value from a register. */
8944 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
8945 /* Produces a ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field value suitable for setting the register. */
8946 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
8947 
8948 /*
8949  * Field : load_comp
8950  *
8951  * Device finished the last issued load command.
8952  *
8953  * Field Access Macros:
8954  *
8955  */
8956 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_LD_COMP register field. */
8957 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_LSB 6
8958 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_LD_COMP register field. */
8959 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_MSB 6
8960 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_LD_COMP register field. */
8961 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_WIDTH 1
8962 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_LD_COMP register field value. */
8963 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_SET_MSK 0x00000040
8964 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_LD_COMP register field value. */
8965 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_CLR_MSK 0xffffffbf
8966 /* The reset value of the ALT_NAND_STAT_INTR_EN2_LD_COMP register field. */
8967 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_RESET 0x0
8968 /* Extracts the ALT_NAND_STAT_INTR_EN2_LD_COMP field value from a register. */
8969 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
8970 /* Produces a ALT_NAND_STAT_INTR_EN2_LD_COMP register field value suitable for setting the register. */
8971 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
8972 
8973 /*
8974  * Field : program_comp
8975  *
8976  * Device finished the last issued program command.
8977  *
8978  * Field Access Macros:
8979  *
8980  */
8981 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field. */
8982 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_LSB 7
8983 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field. */
8984 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_MSB 7
8985 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field. */
8986 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_WIDTH 1
8987 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field value. */
8988 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_SET_MSK 0x00000080
8989 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field value. */
8990 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_CLR_MSK 0xffffff7f
8991 /* The reset value of the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field. */
8992 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_RESET 0x0
8993 /* Extracts the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP field value from a register. */
8994 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
8995 /* Produces a ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field value suitable for setting the register. */
8996 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
8997 
8998 /*
8999  * Field : erase_comp
9000  *
9001  * Device erase operation complete
9002  *
9003  * Field Access Macros:
9004  *
9005  */
9006 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field. */
9007 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_LSB 8
9008 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field. */
9009 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_MSB 8
9010 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field. */
9011 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_WIDTH 1
9012 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field value. */
9013 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_SET_MSK 0x00000100
9014 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field value. */
9015 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_CLR_MSK 0xfffffeff
9016 /* The reset value of the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field. */
9017 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_RESET 0x0
9018 /* Extracts the ALT_NAND_STAT_INTR_EN2_ERASE_COMP field value from a register. */
9019 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
9020 /* Produces a ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field value suitable for setting the register. */
9021 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
9022 
9023 /*
9024  * Field : pipe_cpybck_cmd_comp
9025  *
9026  * A pipeline command or a copyback bank command has completed on this particular
9027  * bank
9028  *
9029  * Field Access Macros:
9030  *
9031  */
9032 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field. */
9033 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_LSB 9
9034 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field. */
9035 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_MSB 9
9036 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field. */
9037 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_WIDTH 1
9038 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field value. */
9039 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
9040 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field value. */
9041 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
9042 /* The reset value of the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field. */
9043 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_RESET 0x0
9044 /* Extracts the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP field value from a register. */
9045 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
9046 /* Produces a ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
9047 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
9048 
9049 /*
9050  * Field : locked_blk
9051  *
9052  * The address to program or erase operation is to a locked block and the operation
9053  * failed
9054  *
9055  * due to this reason
9056  *
9057  * Field Access Macros:
9058  *
9059  */
9060 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field. */
9061 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_LSB 10
9062 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field. */
9063 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_MSB 10
9064 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field. */
9065 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_WIDTH 1
9066 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field value. */
9067 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_SET_MSK 0x00000400
9068 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field value. */
9069 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_CLR_MSK 0xfffffbff
9070 /* The reset value of the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field. */
9071 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_RESET 0x0
9072 /* Extracts the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK field value from a register. */
9073 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
9074 /* Produces a ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field value suitable for setting the register. */
9075 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
9076 
9077 /*
9078  * Field : unsup_cmd
9079  *
9080  * An unsupported command was received. This interrupt is set when an invalid
9081  * command is
9082  *
9083  * received, or when a command sequence is broken.
9084  *
9085  * Field Access Macros:
9086  *
9087  */
9088 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field. */
9089 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_LSB 11
9090 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field. */
9091 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_MSB 11
9092 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field. */
9093 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_WIDTH 1
9094 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field value. */
9095 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_SET_MSK 0x00000800
9096 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field value. */
9097 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_CLR_MSK 0xfffff7ff
9098 /* The reset value of the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field. */
9099 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_RESET 0x0
9100 /* Extracts the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD field value from a register. */
9101 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
9102 /* Produces a ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field value suitable for setting the register. */
9103 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
9104 
9105 /*
9106  * Field : int_act
9107  *
9108  * R/B pin of device transitioned from low to high
9109  *
9110  * Field Access Macros:
9111  *
9112  */
9113 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_INT_ACT register field. */
9114 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_LSB 12
9115 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_INT_ACT register field. */
9116 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_MSB 12
9117 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_INT_ACT register field. */
9118 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_WIDTH 1
9119 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_INT_ACT register field value. */
9120 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_SET_MSK 0x00001000
9121 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_INT_ACT register field value. */
9122 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_CLR_MSK 0xffffefff
9123 /* The reset value of the ALT_NAND_STAT_INTR_EN2_INT_ACT register field. */
9124 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_RESET 0x0
9125 /* Extracts the ALT_NAND_STAT_INTR_EN2_INT_ACT field value from a register. */
9126 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
9127 /* Produces a ALT_NAND_STAT_INTR_EN2_INT_ACT register field value suitable for setting the register. */
9128 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
9129 
9130 /*
9131  * Field : rst_comp
9132  *
9133  * A reset command has completed on this bank
9134  *
9135  * Field Access Macros:
9136  *
9137  */
9138 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_RST_COMP register field. */
9139 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_LSB 13
9140 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_RST_COMP register field. */
9141 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_MSB 13
9142 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_RST_COMP register field. */
9143 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_WIDTH 1
9144 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_RST_COMP register field value. */
9145 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_SET_MSK 0x00002000
9146 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_RST_COMP register field value. */
9147 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_CLR_MSK 0xffffdfff
9148 /* The reset value of the ALT_NAND_STAT_INTR_EN2_RST_COMP register field. */
9149 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_RESET 0x1
9150 /* Extracts the ALT_NAND_STAT_INTR_EN2_RST_COMP field value from a register. */
9151 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
9152 /* Produces a ALT_NAND_STAT_INTR_EN2_RST_COMP register field value suitable for setting the register. */
9153 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
9154 
9155 /*
9156  * Field : pipe_cmd_err
9157  *
9158  * A pipeline command sequence has been violated. This occurs when Map 01 page
9159  * read/write
9160  *
9161  * address does not match the corresponding expected address from the pipeline
9162  * commands issued
9163  *
9164  * earlier.
9165  *
9166  * Field Access Macros:
9167  *
9168  */
9169 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field. */
9170 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_LSB 14
9171 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field. */
9172 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_MSB 14
9173 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field. */
9174 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_WIDTH 1
9175 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field value. */
9176 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_SET_MSK 0x00004000
9177 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field value. */
9178 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
9179 /* The reset value of the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field. */
9180 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_RESET 0x0
9181 /* Extracts the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR field value from a register. */
9182 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
9183 /* Produces a ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field value suitable for setting the register. */
9184 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
9185 
9186 /*
9187  * Field : page_xfer_inc
9188  *
9189  * For every page of data transfer to or from the device, this bit will be set.
9190  *
9191  * Field Access Macros:
9192  *
9193  */
9194 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field. */
9195 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_LSB 15
9196 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field. */
9197 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_MSB 15
9198 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field. */
9199 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_WIDTH 1
9200 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field value. */
9201 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_SET_MSK 0x00008000
9202 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field value. */
9203 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_CLR_MSK 0xffff7fff
9204 /* The reset value of the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field. */
9205 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_RESET 0x0
9206 /* Extracts the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC field value from a register. */
9207 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
9208 /* Produces a ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field value suitable for setting the register. */
9209 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
9210 
9211 /*
9212  * Field : erased_page
9213  *
9214  * If an erased page is detected on reads, this bit will be set. The detection of
9215  * erased
9216  *
9217  * page is based on the number of 0's in the page. If the number of 0's in the page
9218  * being
9219  *
9220  * read is less than the value in the erase_threshold (programmable register),
9221  *
9222  * an erased page is inferred and no un-correctable error will be flagged for that
9223  * page.
9224  *
9225  * If ECC is disabled, the erased_page interrupt shall be set as explained above.
9226  * If ECC is
9227  *
9228  * enabled, in addition to the above condition, only when the ECC logic detects an
9229  *
9230  * un-correctable error for that page will the erased_page interrupt be flagged. If
9231  * the ECC
9232  *
9233  * logic detects a no-error or correctable error page, this erased page interrupt
9234  * will not
9235  *
9236  * be set.
9237  *
9238  * Field Access Macros:
9239  *
9240  */
9241 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_ERASED_PAGE register field. */
9242 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_LSB 16
9243 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_ERASED_PAGE register field. */
9244 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_MSB 16
9245 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_ERASED_PAGE register field. */
9246 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_WIDTH 1
9247 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_ERASED_PAGE register field value. */
9248 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_SET_MSK 0x00010000
9249 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_ERASED_PAGE register field value. */
9250 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_CLR_MSK 0xfffeffff
9251 /* The reset value of the ALT_NAND_STAT_INTR_EN2_ERASED_PAGE register field. */
9252 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_RESET 0x0
9253 /* Extracts the ALT_NAND_STAT_INTR_EN2_ERASED_PAGE field value from a register. */
9254 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
9255 /* Produces a ALT_NAND_STAT_INTR_EN2_ERASED_PAGE register field value suitable for setting the register. */
9256 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
9257 
9258 #ifndef __ASSEMBLY__
9259 /*
9260  * WARNING: The C register and register group struct declarations are provided for
9261  * convenience and illustrative purposes. They should, however, be used with
9262  * caution as the C language standard provides no guarantees about the alignment or
9263  * atomicity of device memory accesses. The recommended practice for writing
9264  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9265  * alt_write_word() functions.
9266  *
9267  * The struct declaration for register ALT_NAND_STAT_INTR_EN2.
9268  */
9269 struct ALT_NAND_STAT_INTR_EN2_s
9270 {
9271  uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR */
9272  uint32_t : 1; /* *UNDEFINED* */
9273  uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP */
9274  uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_EN2_TIME_OUT */
9275  uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL */
9276  uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_EN2_ERASE_FAIL */
9277  uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_EN2_LD_COMP */
9278  uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP */
9279  uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_EN2_ERASE_COMP */
9280  uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP */
9281  uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_EN2_LOCKED_BLK */
9282  uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_EN2_UNSUP_CMD */
9283  uint32_t int_act : 1; /* ALT_NAND_STAT_INTR_EN2_INT_ACT */
9284  uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_EN2_RST_COMP */
9285  uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR */
9286  uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC */
9287  uint32_t erased_page : 1; /* ALT_NAND_STAT_INTR_EN2_ERASED_PAGE */
9288  uint32_t : 15; /* *UNDEFINED* */
9289 };
9290 
9291 /* The typedef declaration for register ALT_NAND_STAT_INTR_EN2. */
9292 typedef volatile struct ALT_NAND_STAT_INTR_EN2_s ALT_NAND_STAT_INTR_EN2_t;
9293 #endif /* __ASSEMBLY__ */
9294 
9295 /* The reset value of the ALT_NAND_STAT_INTR_EN2 register. */
9296 #define ALT_NAND_STAT_INTR_EN2_RESET 0x00002000
9297 /* The byte offset of the ALT_NAND_STAT_INTR_EN2 register from the beginning of the component. */
9298 #define ALT_NAND_STAT_INTR_EN2_OFST 0xc0
9299 
9300 /*
9301  * Register : page_cnt2
9302  *
9303  * Decrementing page count bank 2
9304  *
9305  * Register Layout
9306  *
9307  * Bits | Access | Reset | Description
9308  * :-------|:-------|:--------|:------------------------------
9309  * [7:0] | R | 0x0 | ALT_NAND_STAT_PAGE_CNT2_VALUE
9310  * [31:8] | ??? | Unknown | *UNDEFINED*
9311  *
9312  */
9313 /*
9314  * Field : value
9315  *
9316  * Maintains a decrementing count of the number of pages in
9317  *
9318  * the multi-page (pipeline and copyback) command being executed.
9319  *
9320  * Field Access Macros:
9321  *
9322  */
9323 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_PAGE_CNT2_VALUE register field. */
9324 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_LSB 0
9325 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_PAGE_CNT2_VALUE register field. */
9326 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_MSB 7
9327 /* The width in bits of the ALT_NAND_STAT_PAGE_CNT2_VALUE register field. */
9328 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_WIDTH 8
9329 /* The mask used to set the ALT_NAND_STAT_PAGE_CNT2_VALUE register field value. */
9330 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_SET_MSK 0x000000ff
9331 /* The mask used to clear the ALT_NAND_STAT_PAGE_CNT2_VALUE register field value. */
9332 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_CLR_MSK 0xffffff00
9333 /* The reset value of the ALT_NAND_STAT_PAGE_CNT2_VALUE register field. */
9334 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_RESET 0x0
9335 /* Extracts the ALT_NAND_STAT_PAGE_CNT2_VALUE field value from a register. */
9336 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
9337 /* Produces a ALT_NAND_STAT_PAGE_CNT2_VALUE register field value suitable for setting the register. */
9338 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_SET(value) (((value) << 0) & 0x000000ff)
9339 
9340 #ifndef __ASSEMBLY__
9341 /*
9342  * WARNING: The C register and register group struct declarations are provided for
9343  * convenience and illustrative purposes. They should, however, be used with
9344  * caution as the C language standard provides no guarantees about the alignment or
9345  * atomicity of device memory accesses. The recommended practice for writing
9346  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9347  * alt_write_word() functions.
9348  *
9349  * The struct declaration for register ALT_NAND_STAT_PAGE_CNT2.
9350  */
9351 struct ALT_NAND_STAT_PAGE_CNT2_s
9352 {
9353  const uint32_t value : 8; /* ALT_NAND_STAT_PAGE_CNT2_VALUE */
9354  uint32_t : 24; /* *UNDEFINED* */
9355 };
9356 
9357 /* The typedef declaration for register ALT_NAND_STAT_PAGE_CNT2. */
9358 typedef volatile struct ALT_NAND_STAT_PAGE_CNT2_s ALT_NAND_STAT_PAGE_CNT2_t;
9359 #endif /* __ASSEMBLY__ */
9360 
9361 /* The reset value of the ALT_NAND_STAT_PAGE_CNT2 register. */
9362 #define ALT_NAND_STAT_PAGE_CNT2_RESET 0x00000000
9363 /* The byte offset of the ALT_NAND_STAT_PAGE_CNT2 register from the beginning of the component. */
9364 #define ALT_NAND_STAT_PAGE_CNT2_OFST 0xd0
9365 
9366 /*
9367  * Register : err_page_addr2
9368  *
9369  * Erred page address bank 2
9370  *
9371  * Register Layout
9372  *
9373  * Bits | Access | Reset | Description
9374  * :--------|:-------|:--------|:-----------------------------------
9375  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE
9376  * [31:16] | ??? | Unknown | *UNDEFINED*
9377  *
9378  */
9379 /*
9380  * Field : value
9381  *
9382  * Holds the page address that resulted in a failure on program
9383  *
9384  * or erase operation.
9385  *
9386  * Field Access Macros:
9387  *
9388  */
9389 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field. */
9390 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_LSB 0
9391 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field. */
9392 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_MSB 15
9393 /* The width in bits of the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field. */
9394 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_WIDTH 16
9395 /* The mask used to set the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field value. */
9396 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_SET_MSK 0x0000ffff
9397 /* The mask used to clear the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field value. */
9398 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_CLR_MSK 0xffff0000
9399 /* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field. */
9400 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_RESET 0x0
9401 /* Extracts the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE field value from a register. */
9402 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
9403 /* Produces a ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field value suitable for setting the register. */
9404 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
9405 
9406 #ifndef __ASSEMBLY__
9407 /*
9408  * WARNING: The C register and register group struct declarations are provided for
9409  * convenience and illustrative purposes. They should, however, be used with
9410  * caution as the C language standard provides no guarantees about the alignment or
9411  * atomicity of device memory accesses. The recommended practice for writing
9412  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9413  * alt_write_word() functions.
9414  *
9415  * The struct declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR2.
9416  */
9417 struct ALT_NAND_STAT_ERR_PAGE_ADDR2_s
9418 {
9419  const uint32_t value : 16; /* ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE */
9420  uint32_t : 16; /* *UNDEFINED* */
9421 };
9422 
9423 /* The typedef declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR2. */
9424 typedef volatile struct ALT_NAND_STAT_ERR_PAGE_ADDR2_s ALT_NAND_STAT_ERR_PAGE_ADDR2_t;
9425 #endif /* __ASSEMBLY__ */
9426 
9427 /* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR2 register. */
9428 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_RESET 0x00000000
9429 /* The byte offset of the ALT_NAND_STAT_ERR_PAGE_ADDR2 register from the beginning of the component. */
9430 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_OFST 0xe0
9431 
9432 /*
9433  * Register : err_block_addr2
9434  *
9435  * Erred block address bank 2
9436  *
9437  * Register Layout
9438  *
9439  * Bits | Access | Reset | Description
9440  * :--------|:-------|:--------|:------------------------------------
9441  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE
9442  * [31:16] | ??? | Unknown | *UNDEFINED*
9443  *
9444  */
9445 /*
9446  * Field : value
9447  *
9448  * Holds the block address that resulted in a failure on program
9449  *
9450  * or erase operation.
9451  *
9452  * Field Access Macros:
9453  *
9454  */
9455 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field. */
9456 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_LSB 0
9457 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field. */
9458 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_MSB 15
9459 /* The width in bits of the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field. */
9460 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_WIDTH 16
9461 /* The mask used to set the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field value. */
9462 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_SET_MSK 0x0000ffff
9463 /* The mask used to clear the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field value. */
9464 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_CLR_MSK 0xffff0000
9465 /* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field. */
9466 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_RESET 0x0
9467 /* Extracts the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE field value from a register. */
9468 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
9469 /* Produces a ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field value suitable for setting the register. */
9470 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
9471 
9472 #ifndef __ASSEMBLY__
9473 /*
9474  * WARNING: The C register and register group struct declarations are provided for
9475  * convenience and illustrative purposes. They should, however, be used with
9476  * caution as the C language standard provides no guarantees about the alignment or
9477  * atomicity of device memory accesses. The recommended practice for writing
9478  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9479  * alt_write_word() functions.
9480  *
9481  * The struct declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR2.
9482  */
9483 struct ALT_NAND_STAT_ERR_BLOCK_ADDR2_s
9484 {
9485  const uint32_t value : 16; /* ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE */
9486  uint32_t : 16; /* *UNDEFINED* */
9487 };
9488 
9489 /* The typedef declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR2. */
9490 typedef volatile struct ALT_NAND_STAT_ERR_BLOCK_ADDR2_s ALT_NAND_STAT_ERR_BLOCK_ADDR2_t;
9491 #endif /* __ASSEMBLY__ */
9492 
9493 /* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR2 register. */
9494 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_RESET 0x00000000
9495 /* The byte offset of the ALT_NAND_STAT_ERR_BLOCK_ADDR2 register from the beginning of the component. */
9496 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_OFST 0xf0
9497 
9498 /*
9499  * Register : intr_status3
9500  *
9501  * Interrupt status register for bank 3
9502  *
9503  * Register Layout
9504  *
9505  * Bits | Access | Reset | Description
9506  * :--------|:-------|:--------|:----------------------------------------------
9507  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR
9508  * [1] | ??? | Unknown | *UNDEFINED*
9509  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP
9510  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_TIME_OUT
9511  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL
9512  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL
9513  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_LD_COMP
9514  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP
9515  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_ERASE_COMP
9516  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP
9517  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK
9518  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD
9519  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_INT_ACT
9520  * [13] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_RST_COMP
9521  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR
9522  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC
9523  * [16] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE
9524  * [31:17] | ??? | Unknown | *UNDEFINED*
9525  *
9526  */
9527 /*
9528  * Field : ecc_uncor_err
9529  *
9530  * Ecc logic detected uncorrectable error while reading data from flash device.
9531  *
9532  * Field Access Macros:
9533  *
9534  */
9535 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field. */
9536 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_LSB 0
9537 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field. */
9538 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_MSB 0
9539 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field. */
9540 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_WIDTH 1
9541 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field value. */
9542 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_SET_MSK 0x00000001
9543 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field value. */
9544 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
9545 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field. */
9546 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_RESET 0x0
9547 /* Extracts the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR field value from a register. */
9548 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
9549 /* Produces a ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field value suitable for setting the register. */
9550 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
9551 
9552 /*
9553  * Field : dma_cmd_comp
9554  *
9555  * A data DMA command has completed on this bank
9556  *
9557  * Field Access Macros:
9558  *
9559  */
9560 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field. */
9561 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_LSB 2
9562 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field. */
9563 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_MSB 2
9564 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field. */
9565 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_WIDTH 1
9566 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field value. */
9567 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_SET_MSK 0x00000004
9568 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field value. */
9569 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_CLR_MSK 0xfffffffb
9570 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field. */
9571 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_RESET 0x0
9572 /* Extracts the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP field value from a register. */
9573 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
9574 /* Produces a ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field value suitable for setting the register. */
9575 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
9576 
9577 /*
9578  * Field : time_out
9579  *
9580  * Watchdog timer has triggered in the controller due to one of the reasons like
9581  * device
9582  *
9583  * not responding or controller state machine did not get back to idle
9584  *
9585  * Field Access Macros:
9586  *
9587  */
9588 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field. */
9589 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_LSB 3
9590 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field. */
9591 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_MSB 3
9592 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field. */
9593 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_WIDTH 1
9594 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field value. */
9595 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_SET_MSK 0x00000008
9596 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field value. */
9597 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_CLR_MSK 0xfffffff7
9598 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field. */
9599 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_RESET 0x0
9600 /* Extracts the ALT_NAND_STAT_INTR_STAT3_TIME_OUT field value from a register. */
9601 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
9602 /* Produces a ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field value suitable for setting the register. */
9603 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
9604 
9605 /*
9606  * Field : program_fail
9607  *
9608  * Program failure occurred in the device on issuance of a program command.
9609  * err_block_addr
9610  *
9611  * and err_page_addr contain the block address and page address that failed program
9612  * operation.
9613  *
9614  * Field Access Macros:
9615  *
9616  */
9617 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field. */
9618 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_LSB 4
9619 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field. */
9620 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_MSB 4
9621 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field. */
9622 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_WIDTH 1
9623 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field value. */
9624 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_SET_MSK 0x00000010
9625 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field value. */
9626 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_CLR_MSK 0xffffffef
9627 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field. */
9628 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_RESET 0x0
9629 /* Extracts the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL field value from a register. */
9630 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
9631 /* Produces a ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field value suitable for setting the register. */
9632 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
9633 
9634 /*
9635  * Field : erase_fail
9636  *
9637  * Erase failure occurred in the device on issuance of a erase command.
9638  * err_block_addr
9639  *
9640  * and err_page_addr contain the block address and page address that failed erase
9641  * operation.
9642  *
9643  * Field Access Macros:
9644  *
9645  */
9646 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field. */
9647 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_LSB 5
9648 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field. */
9649 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_MSB 5
9650 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field. */
9651 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_WIDTH 1
9652 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field value. */
9653 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_SET_MSK 0x00000020
9654 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field value. */
9655 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_CLR_MSK 0xffffffdf
9656 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field. */
9657 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_RESET 0x0
9658 /* Extracts the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL field value from a register. */
9659 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
9660 /* Produces a ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field value suitable for setting the register. */
9661 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
9662 
9663 /*
9664  * Field : load_comp
9665  *
9666  * Device finished the last issued load command.
9667  *
9668  * Field Access Macros:
9669  *
9670  */
9671 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field. */
9672 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_LSB 6
9673 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field. */
9674 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_MSB 6
9675 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field. */
9676 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_WIDTH 1
9677 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field value. */
9678 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_SET_MSK 0x00000040
9679 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field value. */
9680 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_CLR_MSK 0xffffffbf
9681 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field. */
9682 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_RESET 0x0
9683 /* Extracts the ALT_NAND_STAT_INTR_STAT3_LD_COMP field value from a register. */
9684 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
9685 /* Produces a ALT_NAND_STAT_INTR_STAT3_LD_COMP register field value suitable for setting the register. */
9686 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
9687 
9688 /*
9689  * Field : program_comp
9690  *
9691  * Device finished the last issued program command.
9692  *
9693  * Field Access Macros:
9694  *
9695  */
9696 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field. */
9697 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_LSB 7
9698 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field. */
9699 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_MSB 7
9700 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field. */
9701 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_WIDTH 1
9702 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field value. */
9703 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_SET_MSK 0x00000080
9704 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field value. */
9705 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_CLR_MSK 0xffffff7f
9706 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field. */
9707 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_RESET 0x0
9708 /* Extracts the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP field value from a register. */
9709 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
9710 /* Produces a ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field value suitable for setting the register. */
9711 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
9712 
9713 /*
9714  * Field : erase_comp
9715  *
9716  * Device erase operation complete
9717  *
9718  * Field Access Macros:
9719  *
9720  */
9721 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field. */
9722 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_LSB 8
9723 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field. */
9724 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_MSB 8
9725 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field. */
9726 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_WIDTH 1
9727 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field value. */
9728 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_SET_MSK 0x00000100
9729 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field value. */
9730 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_CLR_MSK 0xfffffeff
9731 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field. */
9732 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_RESET 0x0
9733 /* Extracts the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP field value from a register. */
9734 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
9735 /* Produces a ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field value suitable for setting the register. */
9736 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
9737 
9738 /*
9739  * Field : pipe_cpybck_cmd_comp
9740  *
9741  * A pipeline command or a copyback bank command has completed on this particular
9742  * bank
9743  *
9744  * Field Access Macros:
9745  *
9746  */
9747 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field. */
9748 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_LSB 9
9749 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field. */
9750 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_MSB 9
9751 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field. */
9752 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_WIDTH 1
9753 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field value. */
9754 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
9755 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field value. */
9756 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
9757 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field. */
9758 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_RESET 0x0
9759 /* Extracts the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP field value from a register. */
9760 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
9761 /* Produces a ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
9762 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
9763 
9764 /*
9765  * Field : locked_blk
9766  *
9767  * The address to program or erase operation is to a locked block and the operation
9768  * failed
9769  *
9770  * due to this reason
9771  *
9772  * Field Access Macros:
9773  *
9774  */
9775 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field. */
9776 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_LSB 10
9777 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field. */
9778 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_MSB 10
9779 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field. */
9780 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_WIDTH 1
9781 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field value. */
9782 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_SET_MSK 0x00000400
9783 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field value. */
9784 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_CLR_MSK 0xfffffbff
9785 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field. */
9786 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_RESET 0x0
9787 /* Extracts the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK field value from a register. */
9788 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
9789 /* Produces a ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field value suitable for setting the register. */
9790 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
9791 
9792 /*
9793  * Field : unsup_cmd
9794  *
9795  * An unsupported command was received. This interrupt is set when an invalid
9796  * command is
9797  *
9798  * received, or when a command sequence is broken.
9799  *
9800  * Field Access Macros:
9801  *
9802  */
9803 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field. */
9804 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_LSB 11
9805 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field. */
9806 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_MSB 11
9807 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field. */
9808 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_WIDTH 1
9809 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field value. */
9810 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_SET_MSK 0x00000800
9811 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field value. */
9812 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_CLR_MSK 0xfffff7ff
9813 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field. */
9814 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_RESET 0x0
9815 /* Extracts the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD field value from a register. */
9816 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
9817 /* Produces a ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field value suitable for setting the register. */
9818 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
9819 
9820 /*
9821  * Field : int_act
9822  *
9823  * R/B pin of device transitioned from low to high
9824  *
9825  * Field Access Macros:
9826  *
9827  */
9828 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field. */
9829 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_LSB 12
9830 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field. */
9831 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_MSB 12
9832 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field. */
9833 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_WIDTH 1
9834 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field value. */
9835 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_SET_MSK 0x00001000
9836 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field value. */
9837 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_CLR_MSK 0xffffefff
9838 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field. */
9839 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_RESET 0x0
9840 /* Extracts the ALT_NAND_STAT_INTR_STAT3_INT_ACT field value from a register. */
9841 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
9842 /* Produces a ALT_NAND_STAT_INTR_STAT3_INT_ACT register field value suitable for setting the register. */
9843 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
9844 
9845 /*
9846  * Field : rst_comp
9847  *
9848  * The Cadence NAND Flash Memory Controller has completed its reset and
9849  * initialization process
9850  *
9851  * Field Access Macros:
9852  *
9853  */
9854 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field. */
9855 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_LSB 13
9856 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field. */
9857 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_MSB 13
9858 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field. */
9859 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_WIDTH 1
9860 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field value. */
9861 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_SET_MSK 0x00002000
9862 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field value. */
9863 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_CLR_MSK 0xffffdfff
9864 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field. */
9865 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_RESET 0x0
9866 /* Extracts the ALT_NAND_STAT_INTR_STAT3_RST_COMP field value from a register. */
9867 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
9868 /* Produces a ALT_NAND_STAT_INTR_STAT3_RST_COMP register field value suitable for setting the register. */
9869 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
9870 
9871 /*
9872  * Field : pipe_cmd_err
9873  *
9874  * A pipeline command sequence has been violated. This occurs when Map 01 page
9875  * read/write
9876  *
9877  * address does not match the corresponding expected address from the pipeline
9878  * commands issued
9879  *
9880  * earlier.
9881  *
9882  * Field Access Macros:
9883  *
9884  */
9885 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field. */
9886 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_LSB 14
9887 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field. */
9888 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_MSB 14
9889 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field. */
9890 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_WIDTH 1
9891 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field value. */
9892 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_SET_MSK 0x00004000
9893 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field value. */
9894 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
9895 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field. */
9896 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_RESET 0x0
9897 /* Extracts the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR field value from a register. */
9898 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
9899 /* Produces a ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field value suitable for setting the register. */
9900 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
9901 
9902 /*
9903  * Field : page_xfer_inc
9904  *
9905  * For every page of data transfer to or from the device, this bit will be set.
9906  *
9907  * Field Access Macros:
9908  *
9909  */
9910 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field. */
9911 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_LSB 15
9912 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field. */
9913 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_MSB 15
9914 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field. */
9915 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_WIDTH 1
9916 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field value. */
9917 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_SET_MSK 0x00008000
9918 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field value. */
9919 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_CLR_MSK 0xffff7fff
9920 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field. */
9921 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_RESET 0x0
9922 /* Extracts the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC field value from a register. */
9923 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
9924 /* Produces a ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field value suitable for setting the register. */
9925 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
9926 
9927 /*
9928  * Field : erased_page
9929  *
9930  * If an erased page is detected on reads, this bit will be set. The detection of
9931  * erased
9932  *
9933  * page is based on the number of 0's in the page. If the number of 0's in the page
9934  * being
9935  *
9936  * read is less than the value in the erase_threshold (programmable register),
9937  *
9938  * an erased page is inferred and no un-correctable error will be flagged for that
9939  * page.
9940  *
9941  * If ECC is disabled, the erased_page interrupt shall be set as explained above.
9942  * If ECC is
9943  *
9944  * enabled, in addition to the above condition, only when the ECC logic detects an
9945  *
9946  * un-correctable error for that page will the erased_page interrupt be flagged. If
9947  * the ECC
9948  *
9949  * logic detects a no-error or correctable error page, this erased page interrupt
9950  * will not
9951  *
9952  * be set.
9953  *
9954  * Field Access Macros:
9955  *
9956  */
9957 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE register field. */
9958 #define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_LSB 16
9959 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE register field. */
9960 #define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_MSB 16
9961 /* The width in bits of the ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE register field. */
9962 #define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_WIDTH 1
9963 /* The mask used to set the ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE register field value. */
9964 #define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_SET_MSK 0x00010000
9965 /* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE register field value. */
9966 #define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_CLR_MSK 0xfffeffff
9967 /* The reset value of the ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE register field. */
9968 #define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_RESET 0x0
9969 /* Extracts the ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE field value from a register. */
9970 #define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
9971 /* Produces a ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE register field value suitable for setting the register. */
9972 #define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
9973 
9974 #ifndef __ASSEMBLY__
9975 /*
9976  * WARNING: The C register and register group struct declarations are provided for
9977  * convenience and illustrative purposes. They should, however, be used with
9978  * caution as the C language standard provides no guarantees about the alignment or
9979  * atomicity of device memory accesses. The recommended practice for writing
9980  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9981  * alt_write_word() functions.
9982  *
9983  * The struct declaration for register ALT_NAND_STAT_INTR_STAT3.
9984  */
9985 struct ALT_NAND_STAT_INTR_STAT3_s
9986 {
9987  uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR */
9988  uint32_t : 1; /* *UNDEFINED* */
9989  uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP */
9990  uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_STAT3_TIME_OUT */
9991  uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL */
9992  uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL */
9993  uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_STAT3_LD_COMP */
9994  uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP */
9995  uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_STAT3_ERASE_COMP */
9996  uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP */
9997  uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK */
9998  uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD */
9999  uint32_t int_act : 1; /* ALT_NAND_STAT_INTR_STAT3_INT_ACT */
10000  uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_STAT3_RST_COMP */
10001  uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR */
10002  uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC */
10003  uint32_t erased_page : 1; /* ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE */
10004  uint32_t : 15; /* *UNDEFINED* */
10005 };
10006 
10007 /* The typedef declaration for register ALT_NAND_STAT_INTR_STAT3. */
10008 typedef volatile struct ALT_NAND_STAT_INTR_STAT3_s ALT_NAND_STAT_INTR_STAT3_t;
10009 #endif /* __ASSEMBLY__ */
10010 
10011 /* The reset value of the ALT_NAND_STAT_INTR_STAT3 register. */
10012 #define ALT_NAND_STAT_INTR_STAT3_RESET 0x00000000
10013 /* The byte offset of the ALT_NAND_STAT_INTR_STAT3 register from the beginning of the component. */
10014 #define ALT_NAND_STAT_INTR_STAT3_OFST 0x100
10015 
10016 /*
10017  * Register : intr_en3
10018  *
10019  * Enables corresponding interrupt bit in interrupt register
10020  *
10021  * for bank 3
10022  *
10023  * Register Layout
10024  *
10025  * Bits | Access | Reset | Description
10026  * :--------|:-------|:--------|:--------------------------------------------
10027  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR
10028  * [1] | ??? | Unknown | *UNDEFINED*
10029  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP
10030  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_TIME_OUT
10031  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL
10032  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_ERASE_FAIL
10033  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_LD_COMP
10034  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP
10035  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_ERASE_COMP
10036  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP
10037  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_LOCKED_BLK
10038  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_UNSUP_CMD
10039  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_INT_ACT
10040  * [13] | RW | 0x1 | ALT_NAND_STAT_INTR_EN3_RST_COMP
10041  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR
10042  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC
10043  * [16] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_ERASED_PAGE
10044  * [31:17] | ??? | Unknown | *UNDEFINED*
10045  *
10046  */
10047 /*
10048  * Field : ecc_uncor_err
10049  *
10050  * If set, Controller will interrupt processor when Ecc logic detects uncorrectable
10051  * error.
10052  *
10053  * Field Access Macros:
10054  *
10055  */
10056 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field. */
10057 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_LSB 0
10058 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field. */
10059 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_MSB 0
10060 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field. */
10061 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_WIDTH 1
10062 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field value. */
10063 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_SET_MSK 0x00000001
10064 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field value. */
10065 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
10066 /* The reset value of the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field. */
10067 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_RESET 0x0
10068 /* Extracts the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR field value from a register. */
10069 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
10070 /* Produces a ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field value suitable for setting the register. */
10071 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
10072 
10073 /*
10074  * Field : dma_cmd_comp
10075  *
10076  * A data DMA command has completed on this bank
10077  *
10078  * Field Access Macros:
10079  *
10080  */
10081 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field. */
10082 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_LSB 2
10083 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field. */
10084 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_MSB 2
10085 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field. */
10086 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_WIDTH 1
10087 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field value. */
10088 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_SET_MSK 0x00000004
10089 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field value. */
10090 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_CLR_MSK 0xfffffffb
10091 /* The reset value of the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field. */
10092 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_RESET 0x0
10093 /* Extracts the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP field value from a register. */
10094 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
10095 /* Produces a ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field value suitable for setting the register. */
10096 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
10097 
10098 /*
10099  * Field : time_out
10100  *
10101  * Watchdog timer has triggered in the controller due to one of the reasons like
10102  * device
10103  *
10104  * not responding or controller state machine did not get back to idle
10105  *
10106  * Field Access Macros:
10107  *
10108  */
10109 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field. */
10110 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_LSB 3
10111 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field. */
10112 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_MSB 3
10113 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field. */
10114 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_WIDTH 1
10115 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field value. */
10116 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_SET_MSK 0x00000008
10117 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field value. */
10118 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_CLR_MSK 0xfffffff7
10119 /* The reset value of the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field. */
10120 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_RESET 0x0
10121 /* Extracts the ALT_NAND_STAT_INTR_EN3_TIME_OUT field value from a register. */
10122 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
10123 /* Produces a ALT_NAND_STAT_INTR_EN3_TIME_OUT register field value suitable for setting the register. */
10124 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
10125 
10126 /*
10127  * Field : program_fail
10128  *
10129  * Program failure occurred in the device on issuance of a program command.
10130  * err_block_addr
10131  *
10132  * and err_page_addr contain the block address and page address that failed program
10133  * operation.
10134  *
10135  * Field Access Macros:
10136  *
10137  */
10138 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field. */
10139 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_LSB 4
10140 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field. */
10141 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_MSB 4
10142 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field. */
10143 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_WIDTH 1
10144 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field value. */
10145 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_SET_MSK 0x00000010
10146 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field value. */
10147 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_CLR_MSK 0xffffffef
10148 /* The reset value of the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field. */
10149 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_RESET 0x0
10150 /* Extracts the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL field value from a register. */
10151 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
10152 /* Produces a ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field value suitable for setting the register. */
10153 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
10154 
10155 /*
10156  * Field : erase_fail
10157  *
10158  * Erase failure occurred in the device on issuance of a erase command.
10159  * err_block_addr
10160  *
10161  * and err_page_addr contain the block address and page address that failed erase
10162  * operation.
10163  *
10164  * Field Access Macros:
10165  *
10166  */
10167 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field. */
10168 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_LSB 5
10169 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field. */
10170 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_MSB 5
10171 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field. */
10172 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_WIDTH 1
10173 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field value. */
10174 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_SET_MSK 0x00000020
10175 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field value. */
10176 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_CLR_MSK 0xffffffdf
10177 /* The reset value of the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field. */
10178 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_RESET 0x0
10179 /* Extracts the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL field value from a register. */
10180 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
10181 /* Produces a ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field value suitable for setting the register. */
10182 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
10183 
10184 /*
10185  * Field : load_comp
10186  *
10187  * Device finished the last issued load command.
10188  *
10189  * Field Access Macros:
10190  *
10191  */
10192 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_LD_COMP register field. */
10193 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_LSB 6
10194 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_LD_COMP register field. */
10195 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_MSB 6
10196 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_LD_COMP register field. */
10197 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_WIDTH 1
10198 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_LD_COMP register field value. */
10199 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_SET_MSK 0x00000040
10200 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_LD_COMP register field value. */
10201 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_CLR_MSK 0xffffffbf
10202 /* The reset value of the ALT_NAND_STAT_INTR_EN3_LD_COMP register field. */
10203 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_RESET 0x0
10204 /* Extracts the ALT_NAND_STAT_INTR_EN3_LD_COMP field value from a register. */
10205 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
10206 /* Produces a ALT_NAND_STAT_INTR_EN3_LD_COMP register field value suitable for setting the register. */
10207 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
10208 
10209 /*
10210  * Field : program_comp
10211  *
10212  * Device finished the last issued program command.
10213  *
10214  * Field Access Macros:
10215  *
10216  */
10217 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field. */
10218 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_LSB 7
10219 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field. */
10220 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_MSB 7
10221 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field. */
10222 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_WIDTH 1
10223 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field value. */
10224 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_SET_MSK 0x00000080
10225 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field value. */
10226 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_CLR_MSK 0xffffff7f
10227 /* The reset value of the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field. */
10228 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_RESET 0x0
10229 /* Extracts the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP field value from a register. */
10230 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
10231 /* Produces a ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field value suitable for setting the register. */
10232 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
10233 
10234 /*
10235  * Field : erase_comp
10236  *
10237  * Device erase operation complete
10238  *
10239  * Field Access Macros:
10240  *
10241  */
10242 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field. */
10243 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_LSB 8
10244 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field. */
10245 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_MSB 8
10246 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field. */
10247 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_WIDTH 1
10248 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field value. */
10249 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_SET_MSK 0x00000100
10250 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field value. */
10251 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_CLR_MSK 0xfffffeff
10252 /* The reset value of the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field. */
10253 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_RESET 0x0
10254 /* Extracts the ALT_NAND_STAT_INTR_EN3_ERASE_COMP field value from a register. */
10255 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
10256 /* Produces a ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field value suitable for setting the register. */
10257 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
10258 
10259 /*
10260  * Field : pipe_cpybck_cmd_comp
10261  *
10262  * A pipeline command or a copyback bank command has completed on this particular
10263  * bank
10264  *
10265  * Field Access Macros:
10266  *
10267  */
10268 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field. */
10269 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_LSB 9
10270 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field. */
10271 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_MSB 9
10272 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field. */
10273 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_WIDTH 1
10274 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field value. */
10275 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
10276 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field value. */
10277 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
10278 /* The reset value of the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field. */
10279 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_RESET 0x0
10280 /* Extracts the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP field value from a register. */
10281 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
10282 /* Produces a ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
10283 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
10284 
10285 /*
10286  * Field : locked_blk
10287  *
10288  * The address to program or erase operation is to a locked block and the operation
10289  * failed
10290  *
10291  * due to this reason
10292  *
10293  * Field Access Macros:
10294  *
10295  */
10296 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field. */
10297 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_LSB 10
10298 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field. */
10299 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_MSB 10
10300 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field. */
10301 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_WIDTH 1
10302 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field value. */
10303 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_SET_MSK 0x00000400
10304 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field value. */
10305 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_CLR_MSK 0xfffffbff
10306 /* The reset value of the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field. */
10307 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_RESET 0x0
10308 /* Extracts the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK field value from a register. */
10309 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
10310 /* Produces a ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field value suitable for setting the register. */
10311 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
10312 
10313 /*
10314  * Field : unsup_cmd
10315  *
10316  * An unsupported command was received. This interrupt is set when an invalid
10317  * command is
10318  *
10319  * received, or when a command sequence is broken.
10320  *
10321  * Field Access Macros:
10322  *
10323  */
10324 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field. */
10325 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_LSB 11
10326 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field. */
10327 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_MSB 11
10328 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field. */
10329 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_WIDTH 1
10330 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field value. */
10331 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_SET_MSK 0x00000800
10332 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field value. */
10333 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_CLR_MSK 0xfffff7ff
10334 /* The reset value of the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field. */
10335 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_RESET 0x0
10336 /* Extracts the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD field value from a register. */
10337 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
10338 /* Produces a ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field value suitable for setting the register. */
10339 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
10340 
10341 /*
10342  * Field : int_act
10343  *
10344  * R/B pin of device transitioned from low to high
10345  *
10346  * Field Access Macros:
10347  *
10348  */
10349 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_INT_ACT register field. */
10350 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_LSB 12
10351 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_INT_ACT register field. */
10352 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_MSB 12
10353 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_INT_ACT register field. */
10354 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_WIDTH 1
10355 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_INT_ACT register field value. */
10356 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_SET_MSK 0x00001000
10357 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_INT_ACT register field value. */
10358 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_CLR_MSK 0xffffefff
10359 /* The reset value of the ALT_NAND_STAT_INTR_EN3_INT_ACT register field. */
10360 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_RESET 0x0
10361 /* Extracts the ALT_NAND_STAT_INTR_EN3_INT_ACT field value from a register. */
10362 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
10363 /* Produces a ALT_NAND_STAT_INTR_EN3_INT_ACT register field value suitable for setting the register. */
10364 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
10365 
10366 /*
10367  * Field : rst_comp
10368  *
10369  * A reset command has completed on this bank
10370  *
10371  * Field Access Macros:
10372  *
10373  */
10374 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_RST_COMP register field. */
10375 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_LSB 13
10376 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_RST_COMP register field. */
10377 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_MSB 13
10378 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_RST_COMP register field. */
10379 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_WIDTH 1
10380 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_RST_COMP register field value. */
10381 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_SET_MSK 0x00002000
10382 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_RST_COMP register field value. */
10383 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_CLR_MSK 0xffffdfff
10384 /* The reset value of the ALT_NAND_STAT_INTR_EN3_RST_COMP register field. */
10385 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_RESET 0x1
10386 /* Extracts the ALT_NAND_STAT_INTR_EN3_RST_COMP field value from a register. */
10387 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
10388 /* Produces a ALT_NAND_STAT_INTR_EN3_RST_COMP register field value suitable for setting the register. */
10389 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
10390 
10391 /*
10392  * Field : pipe_cmd_err
10393  *
10394  * A pipeline command sequence has been violated. This occurs when Map 01 page
10395  * read/write
10396  *
10397  * address does not match the corresponding expected address from the pipeline
10398  * commands issued
10399  *
10400  * earlier.
10401  *
10402  * Field Access Macros:
10403  *
10404  */
10405 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field. */
10406 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_LSB 14
10407 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field. */
10408 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_MSB 14
10409 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field. */
10410 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_WIDTH 1
10411 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field value. */
10412 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_SET_MSK 0x00004000
10413 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field value. */
10414 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
10415 /* The reset value of the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field. */
10416 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_RESET 0x0
10417 /* Extracts the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR field value from a register. */
10418 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
10419 /* Produces a ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field value suitable for setting the register. */
10420 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
10421 
10422 /*
10423  * Field : page_xfer_inc
10424  *
10425  * For every page of data transfer to or from the device, this bit will be set.
10426  *
10427  * Field Access Macros:
10428  *
10429  */
10430 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field. */
10431 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_LSB 15
10432 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field. */
10433 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_MSB 15
10434 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field. */
10435 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_WIDTH 1
10436 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field value. */
10437 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_SET_MSK 0x00008000
10438 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field value. */
10439 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_CLR_MSK 0xffff7fff
10440 /* The reset value of the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field. */
10441 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_RESET 0x0
10442 /* Extracts the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC field value from a register. */
10443 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
10444 /* Produces a ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field value suitable for setting the register. */
10445 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
10446 
10447 /*
10448  * Field : erased_page
10449  *
10450  * If an erased page is detected on reads, this bit will be set. The detection of
10451  * erased
10452  *
10453  * page is based on the number of 0's in the page. If the number of 0's in the page
10454  * being
10455  *
10456  * read is less than the value in the erase_threshold (programmable register),
10457  *
10458  * an erased page is inferred and no un-correctable error will be flagged for that
10459  * page.
10460  *
10461  * If ECC is disabled, the erased_page interrupt shall be set as explained above.
10462  * If ECC is
10463  *
10464  * enabled, in addition to the above condition, only when the ECC logic detects an
10465  *
10466  * un-correctable error for that page will the erased_page interrupt be flagged. If
10467  * the ECC
10468  *
10469  * logic detects a no-error or correctable error page, this erased page interrupt
10470  * will not
10471  *
10472  * be set.
10473  *
10474  * Field Access Macros:
10475  *
10476  */
10477 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_ERASED_PAGE register field. */
10478 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_LSB 16
10479 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_ERASED_PAGE register field. */
10480 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_MSB 16
10481 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_ERASED_PAGE register field. */
10482 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_WIDTH 1
10483 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_ERASED_PAGE register field value. */
10484 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_SET_MSK 0x00010000
10485 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_ERASED_PAGE register field value. */
10486 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_CLR_MSK 0xfffeffff
10487 /* The reset value of the ALT_NAND_STAT_INTR_EN3_ERASED_PAGE register field. */
10488 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_RESET 0x0
10489 /* Extracts the ALT_NAND_STAT_INTR_EN3_ERASED_PAGE field value from a register. */
10490 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
10491 /* Produces a ALT_NAND_STAT_INTR_EN3_ERASED_PAGE register field value suitable for setting the register. */
10492 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
10493 
10494 #ifndef __ASSEMBLY__
10495 /*
10496  * WARNING: The C register and register group struct declarations are provided for
10497  * convenience and illustrative purposes. They should, however, be used with
10498  * caution as the C language standard provides no guarantees about the alignment or
10499  * atomicity of device memory accesses. The recommended practice for writing
10500  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10501  * alt_write_word() functions.
10502  *
10503  * The struct declaration for register ALT_NAND_STAT_INTR_EN3.
10504  */
10505 struct ALT_NAND_STAT_INTR_EN3_s
10506 {
10507  uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR */
10508  uint32_t : 1; /* *UNDEFINED* */
10509  uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP */
10510  uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_EN3_TIME_OUT */
10511  uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL */
10512  uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_EN3_ERASE_FAIL */
10513  uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_EN3_LD_COMP */
10514  uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP */
10515  uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_EN3_ERASE_COMP */
10516  uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP */
10517  uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_EN3_LOCKED_BLK */
10518  uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_EN3_UNSUP_CMD */
10519  uint32_t int_act : 1; /* ALT_NAND_STAT_INTR_EN3_INT_ACT */
10520  uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_EN3_RST_COMP */
10521  uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR */
10522  uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC */
10523  uint32_t erased_page : 1; /* ALT_NAND_STAT_INTR_EN3_ERASED_PAGE */
10524  uint32_t : 15; /* *UNDEFINED* */
10525 };
10526 
10527 /* The typedef declaration for register ALT_NAND_STAT_INTR_EN3. */
10528 typedef volatile struct ALT_NAND_STAT_INTR_EN3_s ALT_NAND_STAT_INTR_EN3_t;
10529 #endif /* __ASSEMBLY__ */
10530 
10531 /* The reset value of the ALT_NAND_STAT_INTR_EN3 register. */
10532 #define ALT_NAND_STAT_INTR_EN3_RESET 0x00002000
10533 /* The byte offset of the ALT_NAND_STAT_INTR_EN3 register from the beginning of the component. */
10534 #define ALT_NAND_STAT_INTR_EN3_OFST 0x110
10535 
10536 /*
10537  * Register : page_cnt3
10538  *
10539  * Decrementing page count bank 3
10540  *
10541  * Register Layout
10542  *
10543  * Bits | Access | Reset | Description
10544  * :-------|:-------|:--------|:------------------------------
10545  * [7:0] | R | 0x0 | ALT_NAND_STAT_PAGE_CNT3_VALUE
10546  * [31:8] | ??? | Unknown | *UNDEFINED*
10547  *
10548  */
10549 /*
10550  * Field : value
10551  *
10552  * Maintains a decrementing count of the number of pages in
10553  *
10554  * the multi-page (pipeline and copyback) command being executed.
10555  *
10556  * Field Access Macros:
10557  *
10558  */
10559 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_PAGE_CNT3_VALUE register field. */
10560 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_LSB 0
10561 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_PAGE_CNT3_VALUE register field. */
10562 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_MSB 7
10563 /* The width in bits of the ALT_NAND_STAT_PAGE_CNT3_VALUE register field. */
10564 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_WIDTH 8
10565 /* The mask used to set the ALT_NAND_STAT_PAGE_CNT3_VALUE register field value. */
10566 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_SET_MSK 0x000000ff
10567 /* The mask used to clear the ALT_NAND_STAT_PAGE_CNT3_VALUE register field value. */
10568 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_CLR_MSK 0xffffff00
10569 /* The reset value of the ALT_NAND_STAT_PAGE_CNT3_VALUE register field. */
10570 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_RESET 0x0
10571 /* Extracts the ALT_NAND_STAT_PAGE_CNT3_VALUE field value from a register. */
10572 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
10573 /* Produces a ALT_NAND_STAT_PAGE_CNT3_VALUE register field value suitable for setting the register. */
10574 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_SET(value) (((value) << 0) & 0x000000ff)
10575 
10576 #ifndef __ASSEMBLY__
10577 /*
10578  * WARNING: The C register and register group struct declarations are provided for
10579  * convenience and illustrative purposes. They should, however, be used with
10580  * caution as the C language standard provides no guarantees about the alignment or
10581  * atomicity of device memory accesses. The recommended practice for writing
10582  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10583  * alt_write_word() functions.
10584  *
10585  * The struct declaration for register ALT_NAND_STAT_PAGE_CNT3.
10586  */
10587 struct ALT_NAND_STAT_PAGE_CNT3_s
10588 {
10589  const uint32_t value : 8; /* ALT_NAND_STAT_PAGE_CNT3_VALUE */
10590  uint32_t : 24; /* *UNDEFINED* */
10591 };
10592 
10593 /* The typedef declaration for register ALT_NAND_STAT_PAGE_CNT3. */
10594 typedef volatile struct ALT_NAND_STAT_PAGE_CNT3_s ALT_NAND_STAT_PAGE_CNT3_t;
10595 #endif /* __ASSEMBLY__ */
10596 
10597 /* The reset value of the ALT_NAND_STAT_PAGE_CNT3 register. */
10598 #define ALT_NAND_STAT_PAGE_CNT3_RESET 0x00000000
10599 /* The byte offset of the ALT_NAND_STAT_PAGE_CNT3 register from the beginning of the component. */
10600 #define ALT_NAND_STAT_PAGE_CNT3_OFST 0x120
10601 
10602 /*
10603  * Register : err_page_addr3
10604  *
10605  * Erred page address bank 3
10606  *
10607  * Register Layout
10608  *
10609  * Bits | Access | Reset | Description
10610  * :--------|:-------|:--------|:-----------------------------------
10611  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE
10612  * [31:16] | ??? | Unknown | *UNDEFINED*
10613  *
10614  */
10615 /*
10616  * Field : value
10617  *
10618  * Holds the page address that resulted in a failure on program
10619  *
10620  * or erase operation.
10621  *
10622  * Field Access Macros:
10623  *
10624  */
10625 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field. */
10626 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_LSB 0
10627 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field. */
10628 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_MSB 15
10629 /* The width in bits of the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field. */
10630 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_WIDTH 16
10631 /* The mask used to set the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field value. */
10632 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_SET_MSK 0x0000ffff
10633 /* The mask used to clear the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field value. */
10634 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_CLR_MSK 0xffff0000
10635 /* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field. */
10636 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_RESET 0x0
10637 /* Extracts the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE field value from a register. */
10638 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
10639 /* Produces a ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field value suitable for setting the register. */
10640 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
10641 
10642 #ifndef __ASSEMBLY__
10643 /*
10644  * WARNING: The C register and register group struct declarations are provided for
10645  * convenience and illustrative purposes. They should, however, be used with
10646  * caution as the C language standard provides no guarantees about the alignment or
10647  * atomicity of device memory accesses. The recommended practice for writing
10648  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10649  * alt_write_word() functions.
10650  *
10651  * The struct declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR3.
10652  */
10653 struct ALT_NAND_STAT_ERR_PAGE_ADDR3_s
10654 {
10655  const uint32_t value : 16; /* ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE */
10656  uint32_t : 16; /* *UNDEFINED* */
10657 };
10658 
10659 /* The typedef declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR3. */
10660 typedef volatile struct ALT_NAND_STAT_ERR_PAGE_ADDR3_s ALT_NAND_STAT_ERR_PAGE_ADDR3_t;
10661 #endif /* __ASSEMBLY__ */
10662 
10663 /* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR3 register. */
10664 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_RESET 0x00000000
10665 /* The byte offset of the ALT_NAND_STAT_ERR_PAGE_ADDR3 register from the beginning of the component. */
10666 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_OFST 0x130
10667 
10668 /*
10669  * Register : err_block_addr3
10670  *
10671  * Erred block address bank 3
10672  *
10673  * Register Layout
10674  *
10675  * Bits | Access | Reset | Description
10676  * :--------|:-------|:--------|:------------------------------------
10677  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE
10678  * [31:16] | ??? | Unknown | *UNDEFINED*
10679  *
10680  */
10681 /*
10682  * Field : value
10683  *
10684  * Holds the block address that resulted in a failure on program
10685  *
10686  * or erase operation.
10687  *
10688  * Field Access Macros:
10689  *
10690  */
10691 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field. */
10692 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_LSB 0
10693 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field. */
10694 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_MSB 15
10695 /* The width in bits of the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field. */
10696 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_WIDTH 16
10697 /* The mask used to set the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field value. */
10698 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_SET_MSK 0x0000ffff
10699 /* The mask used to clear the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field value. */
10700 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_CLR_MSK 0xffff0000
10701 /* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field. */
10702 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_RESET 0x0
10703 /* Extracts the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE field value from a register. */
10704 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
10705 /* Produces a ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field value suitable for setting the register. */
10706 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
10707 
10708 #ifndef __ASSEMBLY__
10709 /*
10710  * WARNING: The C register and register group struct declarations are provided for
10711  * convenience and illustrative purposes. They should, however, be used with
10712  * caution as the C language standard provides no guarantees about the alignment or
10713  * atomicity of device memory accesses. The recommended practice for writing
10714  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10715  * alt_write_word() functions.
10716  *
10717  * The struct declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR3.
10718  */
10719 struct ALT_NAND_STAT_ERR_BLOCK_ADDR3_s
10720 {
10721  const uint32_t value : 16; /* ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE */
10722  uint32_t : 16; /* *UNDEFINED* */
10723 };
10724 
10725 /* The typedef declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR3. */
10726 typedef volatile struct ALT_NAND_STAT_ERR_BLOCK_ADDR3_s ALT_NAND_STAT_ERR_BLOCK_ADDR3_t;
10727 #endif /* __ASSEMBLY__ */
10728 
10729 /* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR3 register. */
10730 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_RESET 0x00000000
10731 /* The byte offset of the ALT_NAND_STAT_ERR_BLOCK_ADDR3 register from the beginning of the component. */
10732 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_OFST 0x140
10733 
10734 #ifndef __ASSEMBLY__
10735 /*
10736  * WARNING: The C register and register group struct declarations are provided for
10737  * convenience and illustrative purposes. They should, however, be used with
10738  * caution as the C language standard provides no guarantees about the alignment or
10739  * atomicity of device memory accesses. The recommended practice for writing
10740  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10741  * alt_write_word() functions.
10742  *
10743  * The struct declaration for register group ALT_NAND_STAT.
10744  */
10745 struct ALT_NAND_STAT_s
10746 {
10747  ALT_NAND_STAT_TFR_MOD_t transfer_mode; /* ALT_NAND_STAT_TFR_MOD */
10748  volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
10749  ALT_NAND_STAT_INTR_STAT0_t intr_status0; /* ALT_NAND_STAT_INTR_STAT0 */
10750  volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
10751  ALT_NAND_STAT_INTR_EN0_t intr_en0; /* ALT_NAND_STAT_INTR_EN0 */
10752  volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
10753  ALT_NAND_STAT_PAGE_CNT0_t page_cnt0; /* ALT_NAND_STAT_PAGE_CNT0 */
10754  volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
10755  ALT_NAND_STAT_ERR_PAGE_ADDR0_t err_page_addr0; /* ALT_NAND_STAT_ERR_PAGE_ADDR0 */
10756  volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
10757  ALT_NAND_STAT_ERR_BLOCK_ADDR0_t err_block_addr0; /* ALT_NAND_STAT_ERR_BLOCK_ADDR0 */
10758  volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
10759  ALT_NAND_STAT_INTR_STAT1_t intr_status1; /* ALT_NAND_STAT_INTR_STAT1 */
10760  volatile uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */
10761  ALT_NAND_STAT_INTR_EN1_t intr_en1; /* ALT_NAND_STAT_INTR_EN1 */
10762  volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
10763  ALT_NAND_STAT_PAGE_CNT1_t page_cnt1; /* ALT_NAND_STAT_PAGE_CNT1 */
10764  volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
10765  ALT_NAND_STAT_ERR_PAGE_ADDR1_t err_page_addr1; /* ALT_NAND_STAT_ERR_PAGE_ADDR1 */
10766  volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
10767  ALT_NAND_STAT_ERR_BLOCK_ADDR1_t err_block_addr1; /* ALT_NAND_STAT_ERR_BLOCK_ADDR1 */
10768  volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
10769  ALT_NAND_STAT_INTR_STAT2_t intr_status2; /* ALT_NAND_STAT_INTR_STAT2 */
10770  volatile uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */
10771  ALT_NAND_STAT_INTR_EN2_t intr_en2; /* ALT_NAND_STAT_INTR_EN2 */
10772  volatile uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */
10773  ALT_NAND_STAT_PAGE_CNT2_t page_cnt2; /* ALT_NAND_STAT_PAGE_CNT2 */
10774  volatile uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */
10775  ALT_NAND_STAT_ERR_PAGE_ADDR2_t err_page_addr2; /* ALT_NAND_STAT_ERR_PAGE_ADDR2 */
10776  volatile uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */
10777  ALT_NAND_STAT_ERR_BLOCK_ADDR2_t err_block_addr2; /* ALT_NAND_STAT_ERR_BLOCK_ADDR2 */
10778  volatile uint32_t _pad_0xf4_0xff[3]; /* *UNDEFINED* */
10779  ALT_NAND_STAT_INTR_STAT3_t intr_status3; /* ALT_NAND_STAT_INTR_STAT3 */
10780  volatile uint32_t _pad_0x104_0x10f[3]; /* *UNDEFINED* */
10781  ALT_NAND_STAT_INTR_EN3_t intr_en3; /* ALT_NAND_STAT_INTR_EN3 */
10782  volatile uint32_t _pad_0x114_0x11f[3]; /* *UNDEFINED* */
10783  ALT_NAND_STAT_PAGE_CNT3_t page_cnt3; /* ALT_NAND_STAT_PAGE_CNT3 */
10784  volatile uint32_t _pad_0x124_0x12f[3]; /* *UNDEFINED* */
10785  ALT_NAND_STAT_ERR_PAGE_ADDR3_t err_page_addr3; /* ALT_NAND_STAT_ERR_PAGE_ADDR3 */
10786  volatile uint32_t _pad_0x134_0x13f[3]; /* *UNDEFINED* */
10787  ALT_NAND_STAT_ERR_BLOCK_ADDR3_t err_block_addr3; /* ALT_NAND_STAT_ERR_BLOCK_ADDR3 */
10788 };
10789 
10790 /* The typedef declaration for register group ALT_NAND_STAT. */
10791 typedef volatile struct ALT_NAND_STAT_s ALT_NAND_STAT_t;
10792 /* The struct declaration for the raw register contents of register group ALT_NAND_STAT. */
10793 struct ALT_NAND_STAT_raw_s
10794 {
10795  volatile uint32_t transfer_mode; /* ALT_NAND_STAT_TFR_MOD */
10796  uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
10797  volatile uint32_t intr_status0; /* ALT_NAND_STAT_INTR_STAT0 */
10798  uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
10799  volatile uint32_t intr_en0; /* ALT_NAND_STAT_INTR_EN0 */
10800  uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
10801  volatile uint32_t page_cnt0; /* ALT_NAND_STAT_PAGE_CNT0 */
10802  uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
10803  volatile uint32_t err_page_addr0; /* ALT_NAND_STAT_ERR_PAGE_ADDR0 */
10804  uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
10805  volatile uint32_t err_block_addr0; /* ALT_NAND_STAT_ERR_BLOCK_ADDR0 */
10806  uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
10807  volatile uint32_t intr_status1; /* ALT_NAND_STAT_INTR_STAT1 */
10808  uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */
10809  volatile uint32_t intr_en1; /* ALT_NAND_STAT_INTR_EN1 */
10810  uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
10811  volatile uint32_t page_cnt1; /* ALT_NAND_STAT_PAGE_CNT1 */
10812  uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
10813  volatile uint32_t err_page_addr1; /* ALT_NAND_STAT_ERR_PAGE_ADDR1 */
10814  uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
10815  volatile uint32_t err_block_addr1; /* ALT_NAND_STAT_ERR_BLOCK_ADDR1 */
10816  uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
10817  volatile uint32_t intr_status2; /* ALT_NAND_STAT_INTR_STAT2 */
10818  uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */
10819  volatile uint32_t intr_en2; /* ALT_NAND_STAT_INTR_EN2 */
10820  uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */
10821  volatile uint32_t page_cnt2; /* ALT_NAND_STAT_PAGE_CNT2 */
10822  uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */
10823  volatile uint32_t err_page_addr2; /* ALT_NAND_STAT_ERR_PAGE_ADDR2 */
10824  uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */
10825  volatile uint32_t err_block_addr2; /* ALT_NAND_STAT_ERR_BLOCK_ADDR2 */
10826  uint32_t _pad_0xf4_0xff[3]; /* *UNDEFINED* */
10827  volatile uint32_t intr_status3; /* ALT_NAND_STAT_INTR_STAT3 */
10828  uint32_t _pad_0x104_0x10f[3]; /* *UNDEFINED* */
10829  volatile uint32_t intr_en3; /* ALT_NAND_STAT_INTR_EN3 */
10830  uint32_t _pad_0x114_0x11f[3]; /* *UNDEFINED* */
10831  volatile uint32_t page_cnt3; /* ALT_NAND_STAT_PAGE_CNT3 */
10832  uint32_t _pad_0x124_0x12f[3]; /* *UNDEFINED* */
10833  volatile uint32_t err_page_addr3; /* ALT_NAND_STAT_ERR_PAGE_ADDR3 */
10834  uint32_t _pad_0x134_0x13f[3]; /* *UNDEFINED* */
10835  volatile uint32_t err_block_addr3; /* ALT_NAND_STAT_ERR_BLOCK_ADDR3 */
10836 };
10837 
10838 /* The typedef declaration for the raw register contents of register group ALT_NAND_STAT. */
10839 typedef volatile struct ALT_NAND_STAT_raw_s ALT_NAND_STAT_raw_t;
10840 #endif /* __ASSEMBLY__ */
10841 
10842 
10843 /*
10844  * Component : ALT_NAND_ECC
10845  *
10846  */
10847 /*
10848  * Register : ecccorinfo_b01
10849  *
10850  * ECC Error correction Information register. Controller updates this register when
10851  * it completes
10852  *
10853  * a transaction. The values are held in this register till a new transaction
10854  * completes.
10855  *
10856  * Register Layout
10857  *
10858  * Bits | Access | Reset | Description
10859  * :--------|:-------|:--------|:------------------------------------------
10860  * [6:0] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0
10861  * [7] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0
10862  * [14:8] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1
10863  * [15] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1
10864  * [31:16] | ??? | Unknown | *UNDEFINED*
10865  *
10866  */
10867 /*
10868  * Field : max_errors_b0
10869  *
10870  * Maximum of number of errors corrected per sector in Bank0. This field is not
10871  * valid for
10872  *
10873  * uncorrectable errors. A value of zero indicates that no ECC error occurred in
10874  * last completed
10875  *
10876  * transaction.
10877  *
10878  * Field Access Macros:
10879  *
10880  */
10881 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field. */
10882 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_LSB 0
10883 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field. */
10884 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_MSB 6
10885 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field. */
10886 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_WIDTH 7
10887 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field value. */
10888 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_SET_MSK 0x0000007f
10889 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field value. */
10890 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_CLR_MSK 0xffffff80
10891 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field. */
10892 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_RESET 0x0
10893 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 field value from a register. */
10894 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_GET(value) (((value) & 0x0000007f) >> 0)
10895 /* Produces a ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field value suitable for setting the register. */
10896 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_SET(value) (((value) << 0) & 0x0000007f)
10897 
10898 /*
10899  * Field : uncor_err_b0
10900  *
10901  * Uncorrectable error occurred while reading pages for last transaction in Bank0.
10902  * Uncorrectable
10903  *
10904  * errors also generate interrupts in intr_statusx register.
10905  *
10906  * Field Access Macros:
10907  *
10908  */
10909 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field. */
10910 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_LSB 7
10911 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field. */
10912 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_MSB 7
10913 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field. */
10914 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_WIDTH 1
10915 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field value. */
10916 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_SET_MSK 0x00000080
10917 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field value. */
10918 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_CLR_MSK 0xffffff7f
10919 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field. */
10920 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_RESET 0x0
10921 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 field value from a register. */
10922 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_GET(value) (((value) & 0x00000080) >> 7)
10923 /* Produces a ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field value suitable for setting the register. */
10924 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_SET(value) (((value) << 7) & 0x00000080)
10925 
10926 /*
10927  * Field : max_errors_b1
10928  *
10929  * Maximum of number of errors corrected per sector in Bank1. This field is not
10930  * valid for
10931  *
10932  * uncorrectable errors. A value of zero indicates that no ECC error occurred in
10933  * last
10934  *
10935  * completed transaction.
10936  *
10937  * Field Access Macros:
10938  *
10939  */
10940 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field. */
10941 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_LSB 8
10942 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field. */
10943 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_MSB 14
10944 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field. */
10945 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_WIDTH 7
10946 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field value. */
10947 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_SET_MSK 0x00007f00
10948 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field value. */
10949 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_CLR_MSK 0xffff80ff
10950 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field. */
10951 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_RESET 0x0
10952 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 field value from a register. */
10953 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_GET(value) (((value) & 0x00007f00) >> 8)
10954 /* Produces a ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field value suitable for setting the register. */
10955 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_SET(value) (((value) << 8) & 0x00007f00)
10956 
10957 /*
10958  * Field : uncor_err_b1
10959  *
10960  * Uncorrectable error occurred while reading pages for last transaction in Bank1.
10961  * Uncorrectable
10962  *
10963  * errors also generate interrupts in intr_statusx register.
10964  *
10965  * Field Access Macros:
10966  *
10967  */
10968 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field. */
10969 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_LSB 15
10970 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field. */
10971 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_MSB 15
10972 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field. */
10973 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_WIDTH 1
10974 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field value. */
10975 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_SET_MSK 0x00008000
10976 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field value. */
10977 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_CLR_MSK 0xffff7fff
10978 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field. */
10979 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_RESET 0x0
10980 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 field value from a register. */
10981 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_GET(value) (((value) & 0x00008000) >> 15)
10982 /* Produces a ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field value suitable for setting the register. */
10983 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_SET(value) (((value) << 15) & 0x00008000)
10984 
10985 #ifndef __ASSEMBLY__
10986 /*
10987  * WARNING: The C register and register group struct declarations are provided for
10988  * convenience and illustrative purposes. They should, however, be used with
10989  * caution as the C language standard provides no guarantees about the alignment or
10990  * atomicity of device memory accesses. The recommended practice for writing
10991  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10992  * alt_write_word() functions.
10993  *
10994  * The struct declaration for register ALT_NAND_ECC_ECCCORINFO_B01.
10995  */
10996 struct ALT_NAND_ECC_ECCCORINFO_B01_s
10997 {
10998  const uint32_t max_errors_b0 : 7; /* ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 */
10999  const uint32_t uncor_err_b0 : 1; /* ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 */
11000  const uint32_t max_errors_b1 : 7; /* ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 */
11001  const uint32_t uncor_err_b1 : 1; /* ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 */
11002  uint32_t : 16; /* *UNDEFINED* */
11003 };
11004 
11005 /* The typedef declaration for register ALT_NAND_ECC_ECCCORINFO_B01. */
11006 typedef volatile struct ALT_NAND_ECC_ECCCORINFO_B01_s ALT_NAND_ECC_ECCCORINFO_B01_t;
11007 #endif /* __ASSEMBLY__ */
11008 
11009 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B01 register. */
11010 #define ALT_NAND_ECC_ECCCORINFO_B01_RESET 0x00000000
11011 /* The byte offset of the ALT_NAND_ECC_ECCCORINFO_B01 register from the beginning of the component. */
11012 #define ALT_NAND_ECC_ECCCORINFO_B01_OFST 0x0
11013 
11014 /*
11015  * Register : ecccorinfo_b23
11016  *
11017  * ECC Error correction Information register. Controller updates this register when
11018  * it completes
11019  *
11020  * a transaction. The values are held in this register till a new transaction
11021  * completes.
11022  *
11023  * Register Layout
11024  *
11025  * Bits | Access | Reset | Description
11026  * :--------|:-------|:--------|:------------------------------------------
11027  * [6:0] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2
11028  * [7] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2
11029  * [14:8] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3
11030  * [15] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3
11031  * [31:16] | ??? | Unknown | *UNDEFINED*
11032  *
11033  */
11034 /*
11035  * Field : max_errors_b2
11036  *
11037  * Maximum of number of errors corrected per sector in Bank2. This field is not
11038  * valid for
11039  *
11040  * uncorrectable errors. A value of zero indicates that no ECC error occurred in
11041  * last completed
11042  *
11043  * transaction.
11044  *
11045  * Field Access Macros:
11046  *
11047  */
11048 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field. */
11049 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_LSB 0
11050 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field. */
11051 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_MSB 6
11052 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field. */
11053 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_WIDTH 7
11054 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field value. */
11055 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_SET_MSK 0x0000007f
11056 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field value. */
11057 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_CLR_MSK 0xffffff80
11058 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field. */
11059 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_RESET 0x0
11060 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 field value from a register. */
11061 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_GET(value) (((value) & 0x0000007f) >> 0)
11062 /* Produces a ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field value suitable for setting the register. */
11063 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_SET(value) (((value) << 0) & 0x0000007f)
11064 
11065 /*
11066  * Field : uncor_err_b2
11067  *
11068  * Uncorrectable error occurred while reading pages for last transaction in Bank2.
11069  * Uncorrectable
11070  *
11071  * errors also generate interrupts in intr_statusx register.
11072  *
11073  * Field Access Macros:
11074  *
11075  */
11076 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field. */
11077 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_LSB 7
11078 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field. */
11079 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_MSB 7
11080 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field. */
11081 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_WIDTH 1
11082 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field value. */
11083 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_SET_MSK 0x00000080
11084 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field value. */
11085 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_CLR_MSK 0xffffff7f
11086 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field. */
11087 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_RESET 0x0
11088 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 field value from a register. */
11089 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_GET(value) (((value) & 0x00000080) >> 7)
11090 /* Produces a ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field value suitable for setting the register. */
11091 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_SET(value) (((value) << 7) & 0x00000080)
11092 
11093 /*
11094  * Field : max_errors_b3
11095  *
11096  * Maximum of number of errors corrected per sector in Bank3. This field is not
11097  * valid for
11098  *
11099  * uncorrectable errors. A value of zero indicates that no ECC error occurred in
11100  * last
11101  *
11102  * completed transaction.
11103  *
11104  * Field Access Macros:
11105  *
11106  */
11107 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field. */
11108 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_LSB 8
11109 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field. */
11110 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_MSB 14
11111 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field. */
11112 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_WIDTH 7
11113 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field value. */
11114 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_SET_MSK 0x00007f00
11115 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field value. */
11116 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_CLR_MSK 0xffff80ff
11117 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field. */
11118 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_RESET 0x0
11119 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 field value from a register. */
11120 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_GET(value) (((value) & 0x00007f00) >> 8)
11121 /* Produces a ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field value suitable for setting the register. */
11122 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_SET(value) (((value) << 8) & 0x00007f00)
11123 
11124 /*
11125  * Field : uncor_err_b3
11126  *
11127  * Uncorrectable error occurred while reading pages for last transaction in Bank3.
11128  * Uncorrectable
11129  *
11130  * errors also generate interrupts in intr_statusx register.
11131  *
11132  * Field Access Macros:
11133  *
11134  */
11135 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field. */
11136 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_LSB 15
11137 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field. */
11138 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_MSB 15
11139 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field. */
11140 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_WIDTH 1
11141 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field value. */
11142 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_SET_MSK 0x00008000
11143 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field value. */
11144 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_CLR_MSK 0xffff7fff
11145 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field. */
11146 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_RESET 0x0
11147 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 field value from a register. */
11148 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_GET(value) (((value) & 0x00008000) >> 15)
11149 /* Produces a ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field value suitable for setting the register. */
11150 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_SET(value) (((value) << 15) & 0x00008000)
11151 
11152 #ifndef __ASSEMBLY__
11153 /*
11154  * WARNING: The C register and register group struct declarations are provided for
11155  * convenience and illustrative purposes. They should, however, be used with
11156  * caution as the C language standard provides no guarantees about the alignment or
11157  * atomicity of device memory accesses. The recommended practice for writing
11158  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11159  * alt_write_word() functions.
11160  *
11161  * The struct declaration for register ALT_NAND_ECC_ECCCORINFO_B23.
11162  */
11163 struct ALT_NAND_ECC_ECCCORINFO_B23_s
11164 {
11165  const uint32_t max_errors_b2 : 7; /* ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 */
11166  const uint32_t uncor_err_b2 : 1; /* ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 */
11167  const uint32_t max_errors_b3 : 7; /* ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 */
11168  const uint32_t uncor_err_b3 : 1; /* ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 */
11169  uint32_t : 16; /* *UNDEFINED* */
11170 };
11171 
11172 /* The typedef declaration for register ALT_NAND_ECC_ECCCORINFO_B23. */
11173 typedef volatile struct ALT_NAND_ECC_ECCCORINFO_B23_s ALT_NAND_ECC_ECCCORINFO_B23_t;
11174 #endif /* __ASSEMBLY__ */
11175 
11176 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B23 register. */
11177 #define ALT_NAND_ECC_ECCCORINFO_B23_RESET 0x00000000
11178 /* The byte offset of the ALT_NAND_ECC_ECCCORINFO_B23 register from the beginning of the component. */
11179 #define ALT_NAND_ECC_ECCCORINFO_B23_OFST 0x10
11180 
11181 #ifndef __ASSEMBLY__
11182 /*
11183  * WARNING: The C register and register group struct declarations are provided for
11184  * convenience and illustrative purposes. They should, however, be used with
11185  * caution as the C language standard provides no guarantees about the alignment or
11186  * atomicity of device memory accesses. The recommended practice for writing
11187  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11188  * alt_write_word() functions.
11189  *
11190  * The struct declaration for register group ALT_NAND_ECC.
11191  */
11192 struct ALT_NAND_ECC_s
11193 {
11194  ALT_NAND_ECC_ECCCORINFO_B01_t ecccorinfo_b01; /* ALT_NAND_ECC_ECCCORINFO_B01 */
11195  volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
11196  ALT_NAND_ECC_ECCCORINFO_B23_t ecccorinfo_b23; /* ALT_NAND_ECC_ECCCORINFO_B23 */
11197 };
11198 
11199 /* The typedef declaration for register group ALT_NAND_ECC. */
11200 typedef volatile struct ALT_NAND_ECC_s ALT_NAND_ECC_t;
11201 /* The struct declaration for the raw register contents of register group ALT_NAND_ECC. */
11202 struct ALT_NAND_ECC_raw_s
11203 {
11204  volatile uint32_t ecccorinfo_b01; /* ALT_NAND_ECC_ECCCORINFO_B01 */
11205  uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
11206  volatile uint32_t ecccorinfo_b23; /* ALT_NAND_ECC_ECCCORINFO_B23 */
11207 };
11208 
11209 /* The typedef declaration for the raw register contents of register group ALT_NAND_ECC. */
11210 typedef volatile struct ALT_NAND_ECC_raw_s ALT_NAND_ECC_raw_t;
11211 #endif /* __ASSEMBLY__ */
11212 
11213 
11214 /*
11215  * Component : ALT_NAND_DMA
11216  *
11217  */
11218 /*
11219  * Register : dma_enable
11220  *
11221  * Register Layout
11222  *
11223  * Bits | Access | Reset | Description
11224  * :-------|:-------|:--------|:-------------------------
11225  * [0] | RW | 0x0 | ALT_NAND_DMA_DMA_EN_FLAG
11226  * [31:1] | ??? | Unknown | *UNDEFINED*
11227  *
11228  */
11229 /*
11230  * Field : flag
11231  *
11232  * Enables data DMA operation in the controller
11233  *
11234  * 1 - Enable DMA 0 - Disable DMA
11235  *
11236  * Field Access Macros:
11237  *
11238  */
11239 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_EN_FLAG register field. */
11240 #define ALT_NAND_DMA_DMA_EN_FLAG_LSB 0
11241 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_EN_FLAG register field. */
11242 #define ALT_NAND_DMA_DMA_EN_FLAG_MSB 0
11243 /* The width in bits of the ALT_NAND_DMA_DMA_EN_FLAG register field. */
11244 #define ALT_NAND_DMA_DMA_EN_FLAG_WIDTH 1
11245 /* The mask used to set the ALT_NAND_DMA_DMA_EN_FLAG register field value. */
11246 #define ALT_NAND_DMA_DMA_EN_FLAG_SET_MSK 0x00000001
11247 /* The mask used to clear the ALT_NAND_DMA_DMA_EN_FLAG register field value. */
11248 #define ALT_NAND_DMA_DMA_EN_FLAG_CLR_MSK 0xfffffffe
11249 /* The reset value of the ALT_NAND_DMA_DMA_EN_FLAG register field. */
11250 #define ALT_NAND_DMA_DMA_EN_FLAG_RESET 0x0
11251 /* Extracts the ALT_NAND_DMA_DMA_EN_FLAG field value from a register. */
11252 #define ALT_NAND_DMA_DMA_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
11253 /* Produces a ALT_NAND_DMA_DMA_EN_FLAG register field value suitable for setting the register. */
11254 #define ALT_NAND_DMA_DMA_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
11255 
11256 #ifndef __ASSEMBLY__
11257 /*
11258  * WARNING: The C register and register group struct declarations are provided for
11259  * convenience and illustrative purposes. They should, however, be used with
11260  * caution as the C language standard provides no guarantees about the alignment or
11261  * atomicity of device memory accesses. The recommended practice for writing
11262  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11263  * alt_write_word() functions.
11264  *
11265  * The struct declaration for register ALT_NAND_DMA_DMA_EN.
11266  */
11267 struct ALT_NAND_DMA_DMA_EN_s
11268 {
11269  uint32_t flag : 1; /* ALT_NAND_DMA_DMA_EN_FLAG */
11270  uint32_t : 31; /* *UNDEFINED* */
11271 };
11272 
11273 /* The typedef declaration for register ALT_NAND_DMA_DMA_EN. */
11274 typedef volatile struct ALT_NAND_DMA_DMA_EN_s ALT_NAND_DMA_DMA_EN_t;
11275 #endif /* __ASSEMBLY__ */
11276 
11277 /* The reset value of the ALT_NAND_DMA_DMA_EN register. */
11278 #define ALT_NAND_DMA_DMA_EN_RESET 0x00000000
11279 /* The byte offset of the ALT_NAND_DMA_DMA_EN register from the beginning of the component. */
11280 #define ALT_NAND_DMA_DMA_EN_OFST 0x0
11281 
11282 /*
11283  * Register : dma_intr
11284  *
11285  * DMA interrupt register
11286  *
11287  * Register Layout
11288  *
11289  * Bits | Access | Reset | Description
11290  * :-------|:-------|:--------|:-----------------------------------------
11291  * [0] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_TGT_ERROR
11292  * [1] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0
11293  * [2] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1
11294  * [3] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2
11295  * [4] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3
11296  * [5] | ??? | Unknown | *UNDEFINED*
11297  * [6] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE
11298  * [31:7] | ??? | Unknown | *UNDEFINED*
11299  *
11300  */
11301 /*
11302  * Field : target_error
11303  *
11304  * Controller initiator interface received an ERROR target response for a
11305  * transaction.
11306  *
11307  * Field Access Macros:
11308  *
11309  */
11310 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_TGT_ERROR register field. */
11311 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_LSB 0
11312 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_TGT_ERROR register field. */
11313 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_MSB 0
11314 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_TGT_ERROR register field. */
11315 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_WIDTH 1
11316 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_TGT_ERROR register field value. */
11317 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_SET_MSK 0x00000001
11318 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_TGT_ERROR register field value. */
11319 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_CLR_MSK 0xfffffffe
11320 /* The reset value of the ALT_NAND_DMA_DMA_INTR_TGT_ERROR register field. */
11321 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_RESET 0x0
11322 /* Extracts the ALT_NAND_DMA_DMA_INTR_TGT_ERROR field value from a register. */
11323 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_GET(value) (((value) & 0x00000001) >> 0)
11324 /* Produces a ALT_NAND_DMA_DMA_INTR_TGT_ERROR register field value suitable for setting the register. */
11325 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_SET(value) (((value) << 0) & 0x00000001)
11326 
11327 /*
11328  * Field : desc_comp_channel0
11329  *
11330  * Indicates CMD-DMA channel 0 descriptor execution done (updated when interrupt
11331  * bit in cmd flags set).
11332  *
11333  * Field Access Macros:
11334  *
11335  */
11336 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0 register field. */
11337 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_LSB 1
11338 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0 register field. */
11339 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_MSB 1
11340 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0 register field. */
11341 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_WIDTH 1
11342 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0 register field value. */
11343 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_SET_MSK 0x00000002
11344 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0 register field value. */
11345 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_CLR_MSK 0xfffffffd
11346 /* The reset value of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0 register field. */
11347 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_RESET 0x0
11348 /* Extracts the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0 field value from a register. */
11349 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_GET(value) (((value) & 0x00000002) >> 1)
11350 /* Produces a ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0 register field value suitable for setting the register. */
11351 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_SET(value) (((value) << 1) & 0x00000002)
11352 
11353 /*
11354  * Field : desc_comp_channel1
11355  *
11356  * Indicates CMD-DMA channel 1 descriptor execution done (updated when interrupt
11357  * bit in cmd flags set).
11358  *
11359  * Field Access Macros:
11360  *
11361  */
11362 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1 register field. */
11363 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_LSB 2
11364 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1 register field. */
11365 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_MSB 2
11366 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1 register field. */
11367 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_WIDTH 1
11368 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1 register field value. */
11369 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_SET_MSK 0x00000004
11370 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1 register field value. */
11371 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_CLR_MSK 0xfffffffb
11372 /* The reset value of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1 register field. */
11373 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_RESET 0x0
11374 /* Extracts the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1 field value from a register. */
11375 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_GET(value) (((value) & 0x00000004) >> 2)
11376 /* Produces a ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1 register field value suitable for setting the register. */
11377 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_SET(value) (((value) << 2) & 0x00000004)
11378 
11379 /*
11380  * Field : desc_comp_channel2
11381  *
11382  * Indicates CMD-DMA channel 2 descriptor execution done (updated when interrupt
11383  * bit in cmd flags set).
11384  *
11385  * Field Access Macros:
11386  *
11387  */
11388 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2 register field. */
11389 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_LSB 3
11390 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2 register field. */
11391 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_MSB 3
11392 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2 register field. */
11393 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_WIDTH 1
11394 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2 register field value. */
11395 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_SET_MSK 0x00000008
11396 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2 register field value. */
11397 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_CLR_MSK 0xfffffff7
11398 /* The reset value of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2 register field. */
11399 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_RESET 0x0
11400 /* Extracts the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2 field value from a register. */
11401 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_GET(value) (((value) & 0x00000008) >> 3)
11402 /* Produces a ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2 register field value suitable for setting the register. */
11403 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_SET(value) (((value) << 3) & 0x00000008)
11404 
11405 /*
11406  * Field : desc_comp_channel3
11407  *
11408  * Indicates CMD-DMA channel 3 descriptor execution done (updated when interrupt
11409  * bit in cmd flags set).
11410  *
11411  * Field Access Macros:
11412  *
11413  */
11414 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3 register field. */
11415 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_LSB 4
11416 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3 register field. */
11417 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_MSB 4
11418 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3 register field. */
11419 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_WIDTH 1
11420 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3 register field value. */
11421 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_SET_MSK 0x00000010
11422 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3 register field value. */
11423 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_CLR_MSK 0xffffffef
11424 /* The reset value of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3 register field. */
11425 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_RESET 0x0
11426 /* Extracts the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3 field value from a register. */
11427 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_GET(value) (((value) & 0x00000010) >> 4)
11428 /* Produces a ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3 register field value suitable for setting the register. */
11429 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_SET(value) (((value) << 4) & 0x00000010)
11430 
11431 /*
11432  * Field : cmddma_idle
11433  *
11434  * Command DMA became IDLE after completing all descriptors
11435  *
11436  * Field Access Macros:
11437  *
11438  */
11439 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE register field. */
11440 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_LSB 6
11441 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE register field. */
11442 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_MSB 6
11443 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE register field. */
11444 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_WIDTH 1
11445 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE register field value. */
11446 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_SET_MSK 0x00000040
11447 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE register field value. */
11448 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_CLR_MSK 0xffffffbf
11449 /* The reset value of the ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE register field. */
11450 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_RESET 0x0
11451 /* Extracts the ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE field value from a register. */
11452 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_GET(value) (((value) & 0x00000040) >> 6)
11453 /* Produces a ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE register field value suitable for setting the register. */
11454 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_SET(value) (((value) << 6) & 0x00000040)
11455 
11456 #ifndef __ASSEMBLY__
11457 /*
11458  * WARNING: The C register and register group struct declarations are provided for
11459  * convenience and illustrative purposes. They should, however, be used with
11460  * caution as the C language standard provides no guarantees about the alignment or
11461  * atomicity of device memory accesses. The recommended practice for writing
11462  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11463  * alt_write_word() functions.
11464  *
11465  * The struct declaration for register ALT_NAND_DMA_DMA_INTR.
11466  */
11467 struct ALT_NAND_DMA_DMA_INTR_s
11468 {
11469  uint32_t target_error : 1; /* ALT_NAND_DMA_DMA_INTR_TGT_ERROR */
11470  uint32_t desc_comp_channel0 : 1; /* ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0 */
11471  uint32_t desc_comp_channel1 : 1; /* ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1 */
11472  uint32_t desc_comp_channel2 : 1; /* ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2 */
11473  uint32_t desc_comp_channel3 : 1; /* ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3 */
11474  uint32_t : 1; /* *UNDEFINED* */
11475  uint32_t cmddma_idle : 1; /* ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE */
11476  uint32_t : 25; /* *UNDEFINED* */
11477 };
11478 
11479 /* The typedef declaration for register ALT_NAND_DMA_DMA_INTR. */
11480 typedef volatile struct ALT_NAND_DMA_DMA_INTR_s ALT_NAND_DMA_DMA_INTR_t;
11481 #endif /* __ASSEMBLY__ */
11482 
11483 /* The reset value of the ALT_NAND_DMA_DMA_INTR register. */
11484 #define ALT_NAND_DMA_DMA_INTR_RESET 0x00000000
11485 /* The byte offset of the ALT_NAND_DMA_DMA_INTR register from the beginning of the component. */
11486 #define ALT_NAND_DMA_DMA_INTR_OFST 0x20
11487 
11488 /*
11489  * Register : dma_intr_en
11490  *
11491  * Enables corresponding interrupt bit in dma interrupt register
11492  *
11493  * Register Layout
11494  *
11495  * Bits | Access | Reset | Description
11496  * :-------|:-------|:--------|:--------------------------------------------
11497  * [0] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR
11498  * [1] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0
11499  * [2] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1
11500  * [3] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2
11501  * [4] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3
11502  * [5] | ??? | Unknown | *UNDEFINED*
11503  * [6] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE
11504  * [31:7] | ??? | Unknown | *UNDEFINED*
11505  *
11506  */
11507 /*
11508  * Field : target_error
11509  *
11510  * Controller initiator interface received an ERROR target response for a
11511  * transaction.
11512  *
11513  * Field Access Macros:
11514  *
11515  */
11516 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field. */
11517 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_LSB 0
11518 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field. */
11519 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_MSB 0
11520 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field. */
11521 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_WIDTH 1
11522 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field value. */
11523 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_SET_MSK 0x00000001
11524 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field value. */
11525 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_CLR_MSK 0xfffffffe
11526 /* The reset value of the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field. */
11527 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_RESET 0x0
11528 /* Extracts the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR field value from a register. */
11529 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_GET(value) (((value) & 0x00000001) >> 0)
11530 /* Produces a ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field value suitable for setting the register. */
11531 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_SET(value) (((value) << 0) & 0x00000001)
11532 
11533 /*
11534  * Field : desc_comp_channel0
11535  *
11536  * Enable bit to indicates CMD-DMA channel 0 descriptor execution done (updated
11537  * when interrupt bit in cmd flags set).
11538  *
11539  * Field Access Macros:
11540  *
11541  */
11542 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 register field. */
11543 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_LSB 1
11544 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 register field. */
11545 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_MSB 1
11546 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 register field. */
11547 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_WIDTH 1
11548 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 register field value. */
11549 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_SET_MSK 0x00000002
11550 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 register field value. */
11551 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_CLR_MSK 0xfffffffd
11552 /* The reset value of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 register field. */
11553 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_RESET 0x0
11554 /* Extracts the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 field value from a register. */
11555 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_GET(value) (((value) & 0x00000002) >> 1)
11556 /* Produces a ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 register field value suitable for setting the register. */
11557 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_SET(value) (((value) << 1) & 0x00000002)
11558 
11559 /*
11560  * Field : desc_comp_channel1
11561  *
11562  * Enable bit to indicates CMD-DMA channel 1 descriptor execution done (updated
11563  * when interrupt bit in cmd flags set).
11564  *
11565  * Field Access Macros:
11566  *
11567  */
11568 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 register field. */
11569 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_LSB 2
11570 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 register field. */
11571 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_MSB 2
11572 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 register field. */
11573 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_WIDTH 1
11574 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 register field value. */
11575 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_SET_MSK 0x00000004
11576 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 register field value. */
11577 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_CLR_MSK 0xfffffffb
11578 /* The reset value of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 register field. */
11579 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_RESET 0x0
11580 /* Extracts the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 field value from a register. */
11581 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_GET(value) (((value) & 0x00000004) >> 2)
11582 /* Produces a ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 register field value suitable for setting the register. */
11583 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_SET(value) (((value) << 2) & 0x00000004)
11584 
11585 /*
11586  * Field : desc_comp_channel2
11587  *
11588  * Enable bit to indicates CMD-DMA channel 2 descriptor execution done (updated
11589  * when interrupt bit in cmd flags set).
11590  *
11591  * Field Access Macros:
11592  *
11593  */
11594 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 register field. */
11595 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_LSB 3
11596 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 register field. */
11597 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_MSB 3
11598 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 register field. */
11599 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_WIDTH 1
11600 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 register field value. */
11601 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_SET_MSK 0x00000008
11602 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 register field value. */
11603 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_CLR_MSK 0xfffffff7
11604 /* The reset value of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 register field. */
11605 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_RESET 0x0
11606 /* Extracts the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 field value from a register. */
11607 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_GET(value) (((value) & 0x00000008) >> 3)
11608 /* Produces a ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 register field value suitable for setting the register. */
11609 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_SET(value) (((value) << 3) & 0x00000008)
11610 
11611 /*
11612  * Field : desc_comp_channel3
11613  *
11614  * Enable bit to indicates CMD-DMA channel 3 descriptor execution done (updated
11615  * when interrupt bit in cmd flags set).
11616  *
11617  * Field Access Macros:
11618  *
11619  */
11620 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 register field. */
11621 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_LSB 4
11622 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 register field. */
11623 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_MSB 4
11624 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 register field. */
11625 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_WIDTH 1
11626 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 register field value. */
11627 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_SET_MSK 0x00000010
11628 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 register field value. */
11629 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_CLR_MSK 0xffffffef
11630 /* The reset value of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 register field. */
11631 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_RESET 0x0
11632 /* Extracts the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 field value from a register. */
11633 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_GET(value) (((value) & 0x00000010) >> 4)
11634 /* Produces a ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 register field value suitable for setting the register. */
11635 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_SET(value) (((value) << 4) & 0x00000010)
11636 
11637 /*
11638  * Field : cmddma_idle
11639  *
11640  * Interrupt processor when command DMA becomes IDLE after completing all
11641  *
11642  * descriptors.
11643  *
11644  * Field Access Macros:
11645  *
11646  */
11647 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE register field. */
11648 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_LSB 6
11649 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE register field. */
11650 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_MSB 6
11651 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE register field. */
11652 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_WIDTH 1
11653 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE register field value. */
11654 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_SET_MSK 0x00000040
11655 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE register field value. */
11656 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_CLR_MSK 0xffffffbf
11657 /* The reset value of the ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE register field. */
11658 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_RESET 0x0
11659 /* Extracts the ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE field value from a register. */
11660 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_GET(value) (((value) & 0x00000040) >> 6)
11661 /* Produces a ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE register field value suitable for setting the register. */
11662 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_SET(value) (((value) << 6) & 0x00000040)
11663 
11664 #ifndef __ASSEMBLY__
11665 /*
11666  * WARNING: The C register and register group struct declarations are provided for
11667  * convenience and illustrative purposes. They should, however, be used with
11668  * caution as the C language standard provides no guarantees about the alignment or
11669  * atomicity of device memory accesses. The recommended practice for writing
11670  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11671  * alt_write_word() functions.
11672  *
11673  * The struct declaration for register ALT_NAND_DMA_DMA_INTR_EN.
11674  */
11675 struct ALT_NAND_DMA_DMA_INTR_EN_s
11676 {
11677  uint32_t target_error : 1; /* ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR */
11678  uint32_t desc_comp_channel0 : 1; /* ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 */
11679  uint32_t desc_comp_channel1 : 1; /* ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 */
11680  uint32_t desc_comp_channel2 : 1; /* ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 */
11681  uint32_t desc_comp_channel3 : 1; /* ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 */
11682  uint32_t : 1; /* *UNDEFINED* */
11683  uint32_t cmddma_idle : 1; /* ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE */
11684  uint32_t : 25; /* *UNDEFINED* */
11685 };
11686 
11687 /* The typedef declaration for register ALT_NAND_DMA_DMA_INTR_EN. */
11688 typedef volatile struct ALT_NAND_DMA_DMA_INTR_EN_s ALT_NAND_DMA_DMA_INTR_EN_t;
11689 #endif /* __ASSEMBLY__ */
11690 
11691 /* The reset value of the ALT_NAND_DMA_DMA_INTR_EN register. */
11692 #define ALT_NAND_DMA_DMA_INTR_EN_RESET 0x00000000
11693 /* The byte offset of the ALT_NAND_DMA_DMA_INTR_EN register from the beginning of the component. */
11694 #define ALT_NAND_DMA_DMA_INTR_EN_OFST 0x30
11695 
11696 /*
11697  * Register : target_err_addr_lo
11698  *
11699  * Transaction address for which controller initiator interface received an ERROR
11700  * target response.
11701  *
11702  * Register Layout
11703  *
11704  * Bits | Access | Reset | Description
11705  * :--------|:-------|:--------|:-----------------------------------
11706  * [15:0] | R | 0x0 | ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE
11707  * [31:16] | ??? | Unknown | *UNDEFINED*
11708  *
11709  */
11710 /*
11711  * Field : value
11712  *
11713  * Least significant 16 bits
11714  *
11715  * Field Access Macros:
11716  *
11717  */
11718 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE register field. */
11719 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_LSB 0
11720 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE register field. */
11721 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_MSB 15
11722 /* The width in bits of the ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE register field. */
11723 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_WIDTH 16
11724 /* The mask used to set the ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE register field value. */
11725 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_SET_MSK 0x0000ffff
11726 /* The mask used to clear the ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE register field value. */
11727 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_CLR_MSK 0xffff0000
11728 /* The reset value of the ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE register field. */
11729 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_RESET 0x0
11730 /* Extracts the ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE field value from a register. */
11731 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
11732 /* Produces a ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE register field value suitable for setting the register. */
11733 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
11734 
11735 #ifndef __ASSEMBLY__
11736 /*
11737  * WARNING: The C register and register group struct declarations are provided for
11738  * convenience and illustrative purposes. They should, however, be used with
11739  * caution as the C language standard provides no guarantees about the alignment or
11740  * atomicity of device memory accesses. The recommended practice for writing
11741  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11742  * alt_write_word() functions.
11743  *
11744  * The struct declaration for register ALT_NAND_DMA_TGT_ERR_ADDR_LO.
11745  */
11746 struct ALT_NAND_DMA_TGT_ERR_ADDR_LO_s
11747 {
11748  const uint32_t value : 16; /* ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE */
11749  uint32_t : 16; /* *UNDEFINED* */
11750 };
11751 
11752 /* The typedef declaration for register ALT_NAND_DMA_TGT_ERR_ADDR_LO. */
11753 typedef volatile struct ALT_NAND_DMA_TGT_ERR_ADDR_LO_s ALT_NAND_DMA_TGT_ERR_ADDR_LO_t;
11754 #endif /* __ASSEMBLY__ */
11755 
11756 /* The reset value of the ALT_NAND_DMA_TGT_ERR_ADDR_LO register. */
11757 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_RESET 0x00000000
11758 /* The byte offset of the ALT_NAND_DMA_TGT_ERR_ADDR_LO register from the beginning of the component. */
11759 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_OFST 0x40
11760 
11761 /*
11762  * Register : target_err_addr_hi
11763  *
11764  * Transaction address for which controller initiator interface received an ERROR
11765  * target response.
11766  *
11767  * Register Layout
11768  *
11769  * Bits | Access | Reset | Description
11770  * :--------|:-------|:--------|:-----------------------------------
11771  * [15:0] | R | 0x0 | ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE
11772  * [31:16] | ??? | Unknown | *UNDEFINED*
11773  *
11774  */
11775 /*
11776  * Field : value
11777  *
11778  * Most significant 16 bits
11779  *
11780  * Field Access Macros:
11781  *
11782  */
11783 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE register field. */
11784 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_LSB 0
11785 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE register field. */
11786 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_MSB 15
11787 /* The width in bits of the ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE register field. */
11788 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_WIDTH 16
11789 /* The mask used to set the ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE register field value. */
11790 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_SET_MSK 0x0000ffff
11791 /* The mask used to clear the ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE register field value. */
11792 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_CLR_MSK 0xffff0000
11793 /* The reset value of the ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE register field. */
11794 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_RESET 0x0
11795 /* Extracts the ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE field value from a register. */
11796 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
11797 /* Produces a ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE register field value suitable for setting the register. */
11798 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
11799 
11800 #ifndef __ASSEMBLY__
11801 /*
11802  * WARNING: The C register and register group struct declarations are provided for
11803  * convenience and illustrative purposes. They should, however, be used with
11804  * caution as the C language standard provides no guarantees about the alignment or
11805  * atomicity of device memory accesses. The recommended practice for writing
11806  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11807  * alt_write_word() functions.
11808  *
11809  * The struct declaration for register ALT_NAND_DMA_TGT_ERR_ADDR_HI.
11810  */
11811 struct ALT_NAND_DMA_TGT_ERR_ADDR_HI_s
11812 {
11813  const uint32_t value : 16; /* ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE */
11814  uint32_t : 16; /* *UNDEFINED* */
11815 };
11816 
11817 /* The typedef declaration for register ALT_NAND_DMA_TGT_ERR_ADDR_HI. */
11818 typedef volatile struct ALT_NAND_DMA_TGT_ERR_ADDR_HI_s ALT_NAND_DMA_TGT_ERR_ADDR_HI_t;
11819 #endif /* __ASSEMBLY__ */
11820 
11821 /* The reset value of the ALT_NAND_DMA_TGT_ERR_ADDR_HI register. */
11822 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_RESET 0x00000000
11823 /* The byte offset of the ALT_NAND_DMA_TGT_ERR_ADDR_HI register from the beginning of the component. */
11824 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_OFST 0x50
11825 
11826 /*
11827  * Register : chnl_active
11828  *
11829  * Indicates CMD-DMA channel activity status
11830  *
11831  * Register Layout
11832  *
11833  * Bits | Access | Reset | Description
11834  * :-------|:-------|:--------|:-------------------------------
11835  * [0] | R | 0x0 | ALT_NAND_DMA_CHNL_ACT_CHANNEL0
11836  * [1] | R | 0x0 | ALT_NAND_DMA_CHNL_ACT_CHANNEL1
11837  * [2] | R | 0x0 | ALT_NAND_DMA_CHNL_ACT_CHANNEL2
11838  * [3] | R | 0x0 | ALT_NAND_DMA_CHNL_ACT_CHANNEL3
11839  * [31:4] | ??? | Unknown | *UNDEFINED*
11840  *
11841  */
11842 /*
11843  * Field : channel0
11844  *
11845  * CMD-DMA channel 0 is active
11846  *
11847  * Field Access Macros:
11848  *
11849  */
11850 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CHNL_ACT_CHANNEL0 register field. */
11851 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_LSB 0
11852 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CHNL_ACT_CHANNEL0 register field. */
11853 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_MSB 0
11854 /* The width in bits of the ALT_NAND_DMA_CHNL_ACT_CHANNEL0 register field. */
11855 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_WIDTH 1
11856 /* The mask used to set the ALT_NAND_DMA_CHNL_ACT_CHANNEL0 register field value. */
11857 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_SET_MSK 0x00000001
11858 /* The mask used to clear the ALT_NAND_DMA_CHNL_ACT_CHANNEL0 register field value. */
11859 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_CLR_MSK 0xfffffffe
11860 /* The reset value of the ALT_NAND_DMA_CHNL_ACT_CHANNEL0 register field. */
11861 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_RESET 0x0
11862 /* Extracts the ALT_NAND_DMA_CHNL_ACT_CHANNEL0 field value from a register. */
11863 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_GET(value) (((value) & 0x00000001) >> 0)
11864 /* Produces a ALT_NAND_DMA_CHNL_ACT_CHANNEL0 register field value suitable for setting the register. */
11865 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_SET(value) (((value) << 0) & 0x00000001)
11866 
11867 /*
11868  * Field : channel1
11869  *
11870  * CMD-DMA channel 1 is active
11871  *
11872  * Field Access Macros:
11873  *
11874  */
11875 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CHNL_ACT_CHANNEL1 register field. */
11876 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_LSB 1
11877 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CHNL_ACT_CHANNEL1 register field. */
11878 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_MSB 1
11879 /* The width in bits of the ALT_NAND_DMA_CHNL_ACT_CHANNEL1 register field. */
11880 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_WIDTH 1
11881 /* The mask used to set the ALT_NAND_DMA_CHNL_ACT_CHANNEL1 register field value. */
11882 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_SET_MSK 0x00000002
11883 /* The mask used to clear the ALT_NAND_DMA_CHNL_ACT_CHANNEL1 register field value. */
11884 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_CLR_MSK 0xfffffffd
11885 /* The reset value of the ALT_NAND_DMA_CHNL_ACT_CHANNEL1 register field. */
11886 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_RESET 0x0
11887 /* Extracts the ALT_NAND_DMA_CHNL_ACT_CHANNEL1 field value from a register. */
11888 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_GET(value) (((value) & 0x00000002) >> 1)
11889 /* Produces a ALT_NAND_DMA_CHNL_ACT_CHANNEL1 register field value suitable for setting the register. */
11890 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_SET(value) (((value) << 1) & 0x00000002)
11891 
11892 /*
11893  * Field : channel2
11894  *
11895  * CMD-DMA channel 2 is active
11896  *
11897  * Field Access Macros:
11898  *
11899  */
11900 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CHNL_ACT_CHANNEL2 register field. */
11901 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_LSB 2
11902 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CHNL_ACT_CHANNEL2 register field. */
11903 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_MSB 2
11904 /* The width in bits of the ALT_NAND_DMA_CHNL_ACT_CHANNEL2 register field. */
11905 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_WIDTH 1
11906 /* The mask used to set the ALT_NAND_DMA_CHNL_ACT_CHANNEL2 register field value. */
11907 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_SET_MSK 0x00000004
11908 /* The mask used to clear the ALT_NAND_DMA_CHNL_ACT_CHANNEL2 register field value. */
11909 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_CLR_MSK 0xfffffffb
11910 /* The reset value of the ALT_NAND_DMA_CHNL_ACT_CHANNEL2 register field. */
11911 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_RESET 0x0
11912 /* Extracts the ALT_NAND_DMA_CHNL_ACT_CHANNEL2 field value from a register. */
11913 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_GET(value) (((value) & 0x00000004) >> 2)
11914 /* Produces a ALT_NAND_DMA_CHNL_ACT_CHANNEL2 register field value suitable for setting the register. */
11915 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_SET(value) (((value) << 2) & 0x00000004)
11916 
11917 /*
11918  * Field : channel3
11919  *
11920  * CMD-DMA channel 3 is active
11921  *
11922  * Field Access Macros:
11923  *
11924  */
11925 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CHNL_ACT_CHANNEL3 register field. */
11926 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_LSB 3
11927 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CHNL_ACT_CHANNEL3 register field. */
11928 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_MSB 3
11929 /* The width in bits of the ALT_NAND_DMA_CHNL_ACT_CHANNEL3 register field. */
11930 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_WIDTH 1
11931 /* The mask used to set the ALT_NAND_DMA_CHNL_ACT_CHANNEL3 register field value. */
11932 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_SET_MSK 0x00000008
11933 /* The mask used to clear the ALT_NAND_DMA_CHNL_ACT_CHANNEL3 register field value. */
11934 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_CLR_MSK 0xfffffff7
11935 /* The reset value of the ALT_NAND_DMA_CHNL_ACT_CHANNEL3 register field. */
11936 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_RESET 0x0
11937 /* Extracts the ALT_NAND_DMA_CHNL_ACT_CHANNEL3 field value from a register. */
11938 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_GET(value) (((value) & 0x00000008) >> 3)
11939 /* Produces a ALT_NAND_DMA_CHNL_ACT_CHANNEL3 register field value suitable for setting the register. */
11940 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_SET(value) (((value) << 3) & 0x00000008)
11941 
11942 #ifndef __ASSEMBLY__
11943 /*
11944  * WARNING: The C register and register group struct declarations are provided for
11945  * convenience and illustrative purposes. They should, however, be used with
11946  * caution as the C language standard provides no guarantees about the alignment or
11947  * atomicity of device memory accesses. The recommended practice for writing
11948  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11949  * alt_write_word() functions.
11950  *
11951  * The struct declaration for register ALT_NAND_DMA_CHNL_ACT.
11952  */
11953 struct ALT_NAND_DMA_CHNL_ACT_s
11954 {
11955  const uint32_t channel0 : 1; /* ALT_NAND_DMA_CHNL_ACT_CHANNEL0 */
11956  const uint32_t channel1 : 1; /* ALT_NAND_DMA_CHNL_ACT_CHANNEL1 */
11957  const uint32_t channel2 : 1; /* ALT_NAND_DMA_CHNL_ACT_CHANNEL2 */
11958  const uint32_t channel3 : 1; /* ALT_NAND_DMA_CHNL_ACT_CHANNEL3 */
11959  uint32_t : 28; /* *UNDEFINED* */
11960 };
11961 
11962 /* The typedef declaration for register ALT_NAND_DMA_CHNL_ACT. */
11963 typedef volatile struct ALT_NAND_DMA_CHNL_ACT_s ALT_NAND_DMA_CHNL_ACT_t;
11964 #endif /* __ASSEMBLY__ */
11965 
11966 /* The reset value of the ALT_NAND_DMA_CHNL_ACT register. */
11967 #define ALT_NAND_DMA_CHNL_ACT_RESET 0x00000000
11968 /* The byte offset of the ALT_NAND_DMA_CHNL_ACT register from the beginning of the component. */
11969 #define ALT_NAND_DMA_CHNL_ACT_OFST 0x60
11970 
11971 /*
11972  * Register : flash_burst_length
11973  *
11974  * Register Layout
11975  *
11976  * Bits | Access | Reset | Description
11977  * :-------|:-------|:--------|:----------------------------------------------------
11978  * [1:0] | RW | 0x1 | ALT_NAND_DMA_FLSH_BURST_LEN_VALUE
11979  * [3:2] | ??? | Unknown | *UNDEFINED*
11980  * [4] | RW | 0x0 | ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST
11981  * [7:5] | ??? | Unknown | *UNDEFINED*
11982  * [31:8] | RW | 0x0 | ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE
11983  *
11984  */
11985 /*
11986  * Field : value
11987  *
11988  * Sets the burst used by data dma for transferring data to/from flash device.
11989  *
11990  * This burst length is different and is larger than the burst length on the
11991  *
11992  * host bus so that larger amount of data can be transferred to/from device,
11993  *
11994  * descreasing controller data transfer overhead in the process.
11995  *
11996  * 00 - 64 bytes, 01 - 128 bytes, 10 - 256 bytes, 11 - 512 bytes.
11997  *
11998  * The host burst size multiplied by the number of outstanding requests on the
11999  *
12000  * host side should be greater than equal to this value. If not, the device side
12001  *
12002  * burst length will be equal to host side burst length.
12003  *
12004  * Field Access Macros:
12005  *
12006  */
12007 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field. */
12008 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_LSB 0
12009 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field. */
12010 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_MSB 1
12011 /* The width in bits of the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field. */
12012 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_WIDTH 2
12013 /* The mask used to set the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field value. */
12014 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_SET_MSK 0x00000003
12015 /* The mask used to clear the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field value. */
12016 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_CLR_MSK 0xfffffffc
12017 /* The reset value of the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field. */
12018 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_RESET 0x1
12019 /* Extracts the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE field value from a register. */
12020 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_GET(value) (((value) & 0x00000003) >> 0)
12021 /* Produces a ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field value suitable for setting the register. */
12022 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_SET(value) (((value) << 0) & 0x00000003)
12023 
12024 /*
12025  * Field : continous_burst
12026  *
12027  * When this bit is set, the Data DMA will burst the entire page from/to the
12028  *
12029  * flash device. Please make sure that the host system can provide/sink data
12030  *
12031  * at a fast pace to avoid unnecessary pausing of data on the device interface.
12032  *
12033  * Field Access Macros:
12034  *
12035  */
12036 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field. */
12037 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_LSB 4
12038 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field. */
12039 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_MSB 4
12040 /* The width in bits of the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field. */
12041 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_WIDTH 1
12042 /* The mask used to set the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field value. */
12043 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_SET_MSK 0x00000010
12044 /* The mask used to clear the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field value. */
12045 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_CLR_MSK 0xffffffef
12046 /* The reset value of the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field. */
12047 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_RESET 0x0
12048 /* Extracts the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST field value from a register. */
12049 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_GET(value) (((value) & 0x00000010) >> 4)
12050 /* Produces a ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field value suitable for setting the register. */
12051 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_SET(value) (((value) << 4) & 0x00000010)
12052 
12053 /*
12054  * Field : polling_sync_counter_value
12055  *
12056  * Number of cycles CMDDMA channel has to wait before polling the SYNC Pointer
12057  * again.
12058  *
12059  * If this counter value is 0, no polling is done.
12060  *
12061  * Field Access Macros:
12062  *
12063  */
12064 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE register field. */
12065 #define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_LSB 8
12066 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE register field. */
12067 #define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_MSB 31
12068 /* The width in bits of the ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE register field. */
12069 #define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_WIDTH 24
12070 /* The mask used to set the ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE register field value. */
12071 #define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_SET_MSK 0xffffff00
12072 /* The mask used to clear the ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE register field value. */
12073 #define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_CLR_MSK 0x000000ff
12074 /* The reset value of the ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE register field. */
12075 #define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_RESET 0x0
12076 /* Extracts the ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE field value from a register. */
12077 #define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_GET(value) (((value) & 0xffffff00) >> 8)
12078 /* Produces a ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE register field value suitable for setting the register. */
12079 #define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_SET(value) (((value) << 8) & 0xffffff00)
12080 
12081 #ifndef __ASSEMBLY__
12082 /*
12083  * WARNING: The C register and register group struct declarations are provided for
12084  * convenience and illustrative purposes. They should, however, be used with
12085  * caution as the C language standard provides no guarantees about the alignment or
12086  * atomicity of device memory accesses. The recommended practice for writing
12087  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12088  * alt_write_word() functions.
12089  *
12090  * The struct declaration for register ALT_NAND_DMA_FLSH_BURST_LEN.
12091  */
12092 struct ALT_NAND_DMA_FLSH_BURST_LEN_s
12093 {
12094  uint32_t value : 2; /* ALT_NAND_DMA_FLSH_BURST_LEN_VALUE */
12095  uint32_t : 2; /* *UNDEFINED* */
12096  uint32_t continous_burst : 1; /* ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST */
12097  uint32_t : 3; /* *UNDEFINED* */
12098  uint32_t polling_sync_counter_value : 24; /* ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE */
12099 };
12100 
12101 /* The typedef declaration for register ALT_NAND_DMA_FLSH_BURST_LEN. */
12102 typedef volatile struct ALT_NAND_DMA_FLSH_BURST_LEN_s ALT_NAND_DMA_FLSH_BURST_LEN_t;
12103 #endif /* __ASSEMBLY__ */
12104 
12105 /* The reset value of the ALT_NAND_DMA_FLSH_BURST_LEN register. */
12106 #define ALT_NAND_DMA_FLSH_BURST_LEN_RESET 0x00000001
12107 /* The byte offset of the ALT_NAND_DMA_FLSH_BURST_LEN register from the beginning of the component. */
12108 #define ALT_NAND_DMA_FLSH_BURST_LEN_OFST 0x70
12109 
12110 /*
12111  * Register : chip_interleave_enable_and_allow_int_reads
12112  *
12113  * Register Layout
12114  *
12115  * Bits | Access | Reset | Description
12116  * :-------|:-------|:--------|:----------------------------------------------
12117  * [0] | RW | 0x0 | ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN
12118  * [3:1] | ??? | Unknown | *UNDEFINED*
12119  * [4] | RW | 0x1 | ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS
12120  * [7:5] | ??? | Unknown | *UNDEFINED*
12121  * [8] | RW | 0x1 | ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN
12122  * [31:9] | ??? | Unknown | *UNDEFINED*
12123  *
12124  */
12125 /*
12126  * Field : chip_interleave_enable
12127  *
12128  * This bit informs the controller to enable or disable interleaving
12129  *
12130  * among banks/LUNS to increase the net performance of the controller.
12131  *
12132  * [list][*]1 - Enable interleaving [*]0 - Disable Interleaving[/list]
12133  *
12134  * Field Access Macros:
12135  *
12136  */
12137 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field. */
12138 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_LSB 0
12139 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field. */
12140 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_MSB 0
12141 /* The width in bits of the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field. */
12142 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_WIDTH 1
12143 /* The mask used to set the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field value. */
12144 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_SET_MSK 0x00000001
12145 /* The mask used to clear the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field value. */
12146 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_CLR_MSK 0xfffffffe
12147 /* The reset value of the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field. */
12148 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_RESET 0x0
12149 /* Extracts the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN field value from a register. */
12150 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_GET(value) (((value) & 0x00000001) >> 0)
12151 /* Produces a ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field value suitable for setting the register. */
12152 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_SET(value) (((value) << 0) & 0x00000001)
12153 
12154 /*
12155  * Field : allow_int_reads_within_luns
12156  *
12157  * This bit informs the controller to enable or disable simultaneous read accesses
12158  *
12159  * to different LUNS in the same bank. This bit is of importance only if the
12160  * controller
12161  *
12162  * supports interleaved operations among LUNs and if the device has multiple LUNS.
12163  *
12164  * If the bit is disabled, the controller will send read commands to different LUNS
12165  * of
12166  *
12167  * of the same bank only sequentially and if enabled, the controller will issue
12168  * simultaneous
12169  *
12170  * read accesses to LUNS of same bank if required.
12171  *
12172  * [list][*]1 - Enable [*]0 - Disable[/list]
12173  *
12174  * Field Access Macros:
12175  *
12176  */
12177 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field. */
12178 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_LSB 4
12179 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field. */
12180 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_MSB 4
12181 /* The width in bits of the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field. */
12182 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_WIDTH 1
12183 /* The mask used to set the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field value. */
12184 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_SET_MSK 0x00000010
12185 /* The mask used to clear the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field value. */
12186 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_CLR_MSK 0xffffffef
12187 /* The reset value of the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field. */
12188 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_RESET 0x1
12189 /* Extracts the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS field value from a register. */
12190 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_GET(value) (((value) & 0x00000010) >> 4)
12191 /* Produces a ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field value suitable for setting the register. */
12192 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_SET(value) (((value) << 4) & 0x00000010)
12193 
12194 /*
12195  * Field : cmd_dma_error_enable
12196  *
12197  * This bit informs the CDMA channels to stop working on any new MAP10 Command
12198  * DMAcommands from the host after encountering an
12199  *
12200  * error situation till the error bit for that corresponding channel is cleared in
12201  * the cmd_dma_channel_error register by f/w.
12202  *
12203  * When the CDMA channel encounters an error, it will set the corresponding error
12204  * bit in cmd_dma_channel_error register
12205  *
12206  * If this bit is set, the channel will stop executing any further commands
12207  *
12208  * till f/w comes and clears the error bit in the cmd_dma_channel_error_register.
12209  *
12210  * If this bit is not set, controller will still keep on executing new commands
12211  * issued from f/w.
12212  *
12213  * Field Access Macros:
12214  *
12215  */
12216 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN register field. */
12217 #define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_LSB 8
12218 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN register field. */
12219 #define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_MSB 8
12220 /* The width in bits of the ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN register field. */
12221 #define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_WIDTH 1
12222 /* The mask used to set the ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN register field value. */
12223 #define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_SET_MSK 0x00000100
12224 /* The mask used to clear the ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN register field value. */
12225 #define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_CLR_MSK 0xfffffeff
12226 /* The reset value of the ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN register field. */
12227 #define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_RESET 0x1
12228 /* Extracts the ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN field value from a register. */
12229 #define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_GET(value) (((value) & 0x00000100) >> 8)
12230 /* Produces a ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN register field value suitable for setting the register. */
12231 #define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_SET(value) (((value) << 8) & 0x00000100)
12232 
12233 #ifndef __ASSEMBLY__
12234 /*
12235  * WARNING: The C register and register group struct declarations are provided for
12236  * convenience and illustrative purposes. They should, however, be used with
12237  * caution as the C language standard provides no guarantees about the alignment or
12238  * atomicity of device memory accesses. The recommended practice for writing
12239  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12240  * alt_write_word() functions.
12241  *
12242  * The struct declaration for register ALT_NAND_DMA_INTRLV.
12243  */
12244 struct ALT_NAND_DMA_INTRLV_s
12245 {
12246  uint32_t chip_interleave_enable : 1; /* ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN */
12247  uint32_t : 3; /* *UNDEFINED* */
12248  uint32_t allow_int_reads_within_luns : 1; /* ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS */
12249  uint32_t : 3; /* *UNDEFINED* */
12250  uint32_t cmd_dma_error_enable : 1; /* ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN */
12251  uint32_t : 23; /* *UNDEFINED* */
12252 };
12253 
12254 /* The typedef declaration for register ALT_NAND_DMA_INTRLV. */
12255 typedef volatile struct ALT_NAND_DMA_INTRLV_s ALT_NAND_DMA_INTRLV_t;
12256 #endif /* __ASSEMBLY__ */
12257 
12258 /* The reset value of the ALT_NAND_DMA_INTRLV register. */
12259 #define ALT_NAND_DMA_INTRLV_RESET 0x00000110
12260 /* The byte offset of the ALT_NAND_DMA_INTRLV register from the beginning of the component. */
12261 #define ALT_NAND_DMA_INTRLV_OFST 0x80
12262 
12263 /*
12264  * Register : rescan_buffer_flag
12265  *
12266  * Rescan buffer flag.
12267  *
12268  * Register Layout
12269  *
12270  * Bits | Access | Reset | Description
12271  * :-------|:-------|:--------|:----------------------------------
12272  * [3:0] | RW | 0x0 | ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG
12273  * [31:4] | ??? | Unknown | *UNDEFINED*
12274  *
12275  */
12276 /*
12277  * Field : flag
12278  *
12279  * This register can be used to force rescan of buffer flags in any of the cmd-dma
12280  * channels.
12281  *
12282  * The bit index decides the Channel number. Cmd-dma would rescan the buffer flag
12283  * for matching
12284  *
12285  * condition and it executes the descriptor if it is ready. Hardware clears this
12286  * register after
12287  *
12288  * generating the trigger event.
12289  *
12290  * Field Access Macros:
12291  *
12292  */
12293 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG register field. */
12294 #define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_LSB 0
12295 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG register field. */
12296 #define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_MSB 3
12297 /* The width in bits of the ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG register field. */
12298 #define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_WIDTH 4
12299 /* The mask used to set the ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG register field value. */
12300 #define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_SET_MSK 0x0000000f
12301 /* The mask used to clear the ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG register field value. */
12302 #define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_CLR_MSK 0xfffffff0
12303 /* The reset value of the ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG register field. */
12304 #define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_RESET 0x0
12305 /* Extracts the ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG field value from a register. */
12306 #define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_GET(value) (((value) & 0x0000000f) >> 0)
12307 /* Produces a ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG register field value suitable for setting the register. */
12308 #define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_SET(value) (((value) << 0) & 0x0000000f)
12309 
12310 #ifndef __ASSEMBLY__
12311 /*
12312  * WARNING: The C register and register group struct declarations are provided for
12313  * convenience and illustrative purposes. They should, however, be used with
12314  * caution as the C language standard provides no guarantees about the alignment or
12315  * atomicity of device memory accesses. The recommended practice for writing
12316  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12317  * alt_write_word() functions.
12318  *
12319  * The struct declaration for register ALT_NAND_DMA_RESCAN_BUF_FLAG.
12320  */
12321 struct ALT_NAND_DMA_RESCAN_BUF_FLAG_s
12322 {
12323  uint32_t flag : 4; /* ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG */
12324  uint32_t : 28; /* *UNDEFINED* */
12325 };
12326 
12327 /* The typedef declaration for register ALT_NAND_DMA_RESCAN_BUF_FLAG. */
12328 typedef volatile struct ALT_NAND_DMA_RESCAN_BUF_FLAG_s ALT_NAND_DMA_RESCAN_BUF_FLAG_t;
12329 #endif /* __ASSEMBLY__ */
12330 
12331 /* The reset value of the ALT_NAND_DMA_RESCAN_BUF_FLAG register. */
12332 #define ALT_NAND_DMA_RESCAN_BUF_FLAG_RESET 0x00000000
12333 /* The byte offset of the ALT_NAND_DMA_RESCAN_BUF_FLAG register from the beginning of the component. */
12334 #define ALT_NAND_DMA_RESCAN_BUF_FLAG_OFST 0x90
12335 
12336 /*
12337  * Register : no_of_blocks_per_lun
12338  *
12339  * Register Layout
12340  *
12341  * Bits | Access | Reset | Description
12342  * :--------|:-------|:--------|:---------------------------------------------------------------
12343  * [3:0] | RW | 0xf | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE
12344  * [23:4] | ??? | Unknown | *UNDEFINED*
12345  * [24] | RW | 0x0 | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP
12346  * [27:25] | ??? | Unknown | *UNDEFINED*
12347  * [28] | RW | 0x0 | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC
12348  * [31:29] | ??? | Unknown | *UNDEFINED*
12349  *
12350  */
12351 /*
12352  * Field : value
12353  *
12354  * Indicates the first block of next LUN. This information is used for extracting
12355  * the target LUN during LUN interleaving.
12356  *
12357  * After Initialization, if the controller detects an ONFi device,
12358  *
12359  * this field is automatically updated by the controller.
12360  *
12361  * For other devices, software will need to write to this register
12362  *
12363  * for proper interleaving.
12364  *
12365  * The value in this register is interpreted as follows-
12366  *
12367  * [list][*]0 - Next LUN starts from 1024.
12368  *
12369  * [*]1 - Next LUN starts from 2048.
12370  *
12371  * [*]2 - Next LUN starts from 4096 and so on...
12372  *
12373  * [/list]
12374  *
12375  * Field Access Macros:
12376  *
12377  */
12378 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field. */
12379 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_LSB 0
12380 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field. */
12381 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_MSB 3
12382 /* The width in bits of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field. */
12383 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_WIDTH 4
12384 /* The mask used to set the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field value. */
12385 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_SET_MSK 0x0000000f
12386 /* The mask used to clear the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field value. */
12387 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_CLR_MSK 0xfffffff0
12388 /* The reset value of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field. */
12389 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_RESET 0xf
12390 /* Extracts the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE field value from a register. */
12391 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
12392 /* Produces a ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field value suitable for setting the register. */
12393 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_SET(value) (((value) << 0) & 0x0000000f)
12394 
12395 /*
12396  * Field : update_sync_before_prog_comp
12397  *
12398  * Update SYNC Pointer after the data is written to flash and dont wait for program
12399  *
12400  * to complete. If this value is 0, CMD DMA waits for page program to get over
12401  *
12402  * before updating the sync pointer. This bit should be set to 0 if the controller
12403  *
12404  * is being accessed in non-Command DMA mode.
12405  *
12406  * Field Access Macros:
12407  *
12408  */
12409 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP register field. */
12410 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_LSB 24
12411 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP register field. */
12412 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_MSB 24
12413 /* The width in bits of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP register field. */
12414 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_WIDTH 1
12415 /* The mask used to set the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP register field value. */
12416 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_SET_MSK 0x01000000
12417 /* The mask used to clear the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP register field value. */
12418 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_CLR_MSK 0xfeffffff
12419 /* The reset value of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP register field. */
12420 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_RESET 0x0
12421 /* Extracts the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP field value from a register. */
12422 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_GET(value) (((value) & 0x01000000) >> 24)
12423 /* Produces a ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP register field value suitable for setting the register. */
12424 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_SET(value) (((value) << 24) & 0x01000000)
12425 
12426 /*
12427  * Field : issue_read_before_sync
12428  *
12429  * Issue LOAD cmd to flash core even if SYNC condition is not satisfied. But the
12430  * data is read
12431  *
12432  * from the device (for this load) only after the SYNC condition has been
12433  * satisfied.
12434  *
12435  * If this value is 0, CMD DMA waits for SYNC before issuing a READ command.
12436  *
12437  * This bit should be set to 0 if the controller is being accessed in non-Command
12438  * DMA mode.
12439  *
12440  * Field Access Macros:
12441  *
12442  */
12443 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC register field. */
12444 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_LSB 28
12445 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC register field. */
12446 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_MSB 28
12447 /* The width in bits of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC register field. */
12448 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_WIDTH 1
12449 /* The mask used to set the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC register field value. */
12450 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_SET_MSK 0x10000000
12451 /* The mask used to clear the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC register field value. */
12452 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_CLR_MSK 0xefffffff
12453 /* The reset value of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC register field. */
12454 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_RESET 0x0
12455 /* Extracts the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC field value from a register. */
12456 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_GET(value) (((value) & 0x10000000) >> 28)
12457 /* Produces a ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC register field value suitable for setting the register. */
12458 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_SET(value) (((value) << 28) & 0x10000000)
12459 
12460 #ifndef __ASSEMBLY__
12461 /*
12462  * WARNING: The C register and register group struct declarations are provided for
12463  * convenience and illustrative purposes. They should, however, be used with
12464  * caution as the C language standard provides no guarantees about the alignment or
12465  * atomicity of device memory accesses. The recommended practice for writing
12466  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12467  * alt_write_word() functions.
12468  *
12469  * The struct declaration for register ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN.
12470  */
12471 struct ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_s
12472 {
12473  uint32_t value : 4; /* ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE */
12474  uint32_t : 20; /* *UNDEFINED* */
12475  uint32_t update_sync_before_prog_comp : 1; /* ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP */
12476  uint32_t : 3; /* *UNDEFINED* */
12477  uint32_t issue_read_before_sync : 1; /* ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC */
12478  uint32_t : 3; /* *UNDEFINED* */
12479 };
12480 
12481 /* The typedef declaration for register ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN. */
12482 typedef volatile struct ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_s ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_t;
12483 #endif /* __ASSEMBLY__ */
12484 
12485 /* The reset value of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN register. */
12486 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_RESET 0x0000000f
12487 /* The byte offset of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN register from the beginning of the component. */
12488 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_OFST 0xa0
12489 
12490 /*
12491  * Register : lun_status_cmd
12492  *
12493  * Indicates the command to be sent while checking status of the next LUN.
12494  *
12495  * Register Layout
12496  *
12497  * Bits | Access | Reset | Description
12498  * :--------|:-------|:--------|:--------------------------------
12499  * [15:0] | RW | 0x7878 | ALT_NAND_DMA_LUN_STAT_CMD_VALUE
12500  * [31:16] | ??? | Unknown | *UNDEFINED*
12501  *
12502  */
12503 /*
12504  * Field : value
12505  *
12506  * [list][*]7:0 - Indicates the command to check the
12507  *
12508  * status of the first LUN/Die.
12509  *
12510  * [*]15:8 - Indicates the command to check the
12511  *
12512  * status of the other LUN/Die.[/list]
12513  *
12514  * Field Access Macros:
12515  *
12516  */
12517 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_LUN_STAT_CMD_VALUE register field. */
12518 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_LSB 0
12519 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_LUN_STAT_CMD_VALUE register field. */
12520 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_MSB 15
12521 /* The width in bits of the ALT_NAND_DMA_LUN_STAT_CMD_VALUE register field. */
12522 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_WIDTH 16
12523 /* The mask used to set the ALT_NAND_DMA_LUN_STAT_CMD_VALUE register field value. */
12524 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_SET_MSK 0x0000ffff
12525 /* The mask used to clear the ALT_NAND_DMA_LUN_STAT_CMD_VALUE register field value. */
12526 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_CLR_MSK 0xffff0000
12527 /* The reset value of the ALT_NAND_DMA_LUN_STAT_CMD_VALUE register field. */
12528 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_RESET 0x7878
12529 /* Extracts the ALT_NAND_DMA_LUN_STAT_CMD_VALUE field value from a register. */
12530 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
12531 /* Produces a ALT_NAND_DMA_LUN_STAT_CMD_VALUE register field value suitable for setting the register. */
12532 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
12533 
12534 #ifndef __ASSEMBLY__
12535 /*
12536  * WARNING: The C register and register group struct declarations are provided for
12537  * convenience and illustrative purposes. They should, however, be used with
12538  * caution as the C language standard provides no guarantees about the alignment or
12539  * atomicity of device memory accesses. The recommended practice for writing
12540  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12541  * alt_write_word() functions.
12542  *
12543  * The struct declaration for register ALT_NAND_DMA_LUN_STAT_CMD.
12544  */
12545 struct ALT_NAND_DMA_LUN_STAT_CMD_s
12546 {
12547  uint32_t value : 16; /* ALT_NAND_DMA_LUN_STAT_CMD_VALUE */
12548  uint32_t : 16; /* *UNDEFINED* */
12549 };
12550 
12551 /* The typedef declaration for register ALT_NAND_DMA_LUN_STAT_CMD. */
12552 typedef volatile struct ALT_NAND_DMA_LUN_STAT_CMD_s ALT_NAND_DMA_LUN_STAT_CMD_t;
12553 #endif /* __ASSEMBLY__ */
12554 
12555 /* The reset value of the ALT_NAND_DMA_LUN_STAT_CMD register. */
12556 #define ALT_NAND_DMA_LUN_STAT_CMD_RESET 0x00007878
12557 /* The byte offset of the ALT_NAND_DMA_LUN_STAT_CMD register from the beginning of the component. */
12558 #define ALT_NAND_DMA_LUN_STAT_CMD_OFST 0xb0
12559 
12560 /*
12561  * Register : cmd_dma_channel_error
12562  *
12563  * Bits indicating CMD-DMA channel receiving an error condition. To get more
12564  * information on the error, s/w needs to read the status field of the descriptor.
12565  *
12566  * Register Layout
12567  *
12568  * Bits | Access | Reset | Description
12569  * :-------|:-------|:--------|:--------------------------------------------
12570  * [0] | RW | 0x0 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0
12571  * [1] | RW | 0x0 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1
12572  * [2] | RW | 0x0 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2
12573  * [3] | RW | 0x0 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3
12574  * [31:4] | ??? | Unknown | *UNDEFINED*
12575  *
12576  */
12577 /*
12578  * Field : channel0
12579  *
12580  * CMD-DMA channel 0 received an error.
12581  *
12582  * Field Access Macros:
12583  *
12584  */
12585 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 register field. */
12586 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_LSB 0
12587 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 register field. */
12588 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_MSB 0
12589 /* The width in bits of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 register field. */
12590 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_WIDTH 1
12591 /* The mask used to set the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 register field value. */
12592 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_SET_MSK 0x00000001
12593 /* The mask used to clear the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 register field value. */
12594 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_CLR_MSK 0xfffffffe
12595 /* The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 register field. */
12596 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_RESET 0x0
12597 /* Extracts the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 field value from a register. */
12598 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_GET(value) (((value) & 0x00000001) >> 0)
12599 /* Produces a ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 register field value suitable for setting the register. */
12600 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_SET(value) (((value) << 0) & 0x00000001)
12601 
12602 /*
12603  * Field : channel1
12604  *
12605  * CMD-DMA channel 1 received an error.
12606  *
12607  * Field Access Macros:
12608  *
12609  */
12610 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 register field. */
12611 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_LSB 1
12612 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 register field. */
12613 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_MSB 1
12614 /* The width in bits of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 register field. */
12615 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_WIDTH 1
12616 /* The mask used to set the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 register field value. */
12617 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_SET_MSK 0x00000002
12618 /* The mask used to clear the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 register field value. */
12619 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_CLR_MSK 0xfffffffd
12620 /* The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 register field. */
12621 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_RESET 0x0
12622 /* Extracts the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 field value from a register. */
12623 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_GET(value) (((value) & 0x00000002) >> 1)
12624 /* Produces a ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 register field value suitable for setting the register. */
12625 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_SET(value) (((value) << 1) & 0x00000002)
12626 
12627 /*
12628  * Field : channel2
12629  *
12630  * CMD-DMA channel 2 received an error.
12631  *
12632  * Field Access Macros:
12633  *
12634  */
12635 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 register field. */
12636 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_LSB 2
12637 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 register field. */
12638 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_MSB 2
12639 /* The width in bits of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 register field. */
12640 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_WIDTH 1
12641 /* The mask used to set the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 register field value. */
12642 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_SET_MSK 0x00000004
12643 /* The mask used to clear the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 register field value. */
12644 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_CLR_MSK 0xfffffffb
12645 /* The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 register field. */
12646 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_RESET 0x0
12647 /* Extracts the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 field value from a register. */
12648 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_GET(value) (((value) & 0x00000004) >> 2)
12649 /* Produces a ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 register field value suitable for setting the register. */
12650 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_SET(value) (((value) << 2) & 0x00000004)
12651 
12652 /*
12653  * Field : channel3
12654  *
12655  * CMD-DMA channel 3 received an error.
12656  *
12657  * Field Access Macros:
12658  *
12659  */
12660 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 register field. */
12661 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_LSB 3
12662 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 register field. */
12663 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_MSB 3
12664 /* The width in bits of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 register field. */
12665 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_WIDTH 1
12666 /* The mask used to set the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 register field value. */
12667 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_SET_MSK 0x00000008
12668 /* The mask used to clear the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 register field value. */
12669 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_CLR_MSK 0xfffffff7
12670 /* The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 register field. */
12671 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_RESET 0x0
12672 /* Extracts the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 field value from a register. */
12673 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_GET(value) (((value) & 0x00000008) >> 3)
12674 /* Produces a ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 register field value suitable for setting the register. */
12675 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_SET(value) (((value) << 3) & 0x00000008)
12676 
12677 #ifndef __ASSEMBLY__
12678 /*
12679  * WARNING: The C register and register group struct declarations are provided for
12680  * convenience and illustrative purposes. They should, however, be used with
12681  * caution as the C language standard provides no guarantees about the alignment or
12682  * atomicity of device memory accesses. The recommended practice for writing
12683  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12684  * alt_write_word() functions.
12685  *
12686  * The struct declaration for register ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR.
12687  */
12688 struct ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_s
12689 {
12690  uint32_t channel0 : 1; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 */
12691  uint32_t channel1 : 1; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 */
12692  uint32_t channel2 : 1; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 */
12693  uint32_t channel3 : 1; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 */
12694  uint32_t : 28; /* *UNDEFINED* */
12695 };
12696 
12697 /* The typedef declaration for register ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR. */
12698 typedef volatile struct ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_s ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_t;
12699 #endif /* __ASSEMBLY__ */
12700 
12701 /* The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR register. */
12702 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_RESET 0x00000000
12703 /* The byte offset of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR register from the beginning of the component. */
12704 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_OFST 0xc0
12705 
12706 /*
12707  * Register : cmd_dma_channel_error_en
12708  *
12709  * Enable bits indicating CMD-DMA channel receiving an error condition. To get more
12710  * information on the error, s/w needs to read the status field of the descriptor.
12711  *
12712  * Register Layout
12713  *
12714  * Bits | Access | Reset | Description
12715  * :-------|:-------|:--------|:-----------------------------------------------
12716  * [0] | RW | 0x0 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0
12717  * [1] | RW | 0x0 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1
12718  * [2] | RW | 0x0 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2
12719  * [3] | RW | 0x0 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3
12720  * [31:4] | ??? | Unknown | *UNDEFINED*
12721  *
12722  */
12723 /*
12724  * Field : channel0
12725  *
12726  * enable bit for CMD-DMA channel 0 receiving an error
12727  *
12728  * Field Access Macros:
12729  *
12730  */
12731 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0 register field. */
12732 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_LSB 0
12733 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0 register field. */
12734 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_MSB 0
12735 /* The width in bits of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0 register field. */
12736 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_WIDTH 1
12737 /* The mask used to set the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0 register field value. */
12738 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_SET_MSK 0x00000001
12739 /* The mask used to clear the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0 register field value. */
12740 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_CLR_MSK 0xfffffffe
12741 /* The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0 register field. */
12742 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_RESET 0x0
12743 /* Extracts the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0 field value from a register. */
12744 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_GET(value) (((value) & 0x00000001) >> 0)
12745 /* Produces a ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0 register field value suitable for setting the register. */
12746 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_SET(value) (((value) << 0) & 0x00000001)
12747 
12748 /*
12749  * Field : channel1
12750  *
12751  * enable bit for CMD-DMA channel 1 receiving an error
12752  *
12753  * Field Access Macros:
12754  *
12755  */
12756 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1 register field. */
12757 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_LSB 1
12758 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1 register field. */
12759 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_MSB 1
12760 /* The width in bits of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1 register field. */
12761 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_WIDTH 1
12762 /* The mask used to set the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1 register field value. */
12763 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_SET_MSK 0x00000002
12764 /* The mask used to clear the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1 register field value. */
12765 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_CLR_MSK 0xfffffffd
12766 /* The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1 register field. */
12767 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_RESET 0x0
12768 /* Extracts the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1 field value from a register. */
12769 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_GET(value) (((value) & 0x00000002) >> 1)
12770 /* Produces a ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1 register field value suitable for setting the register. */
12771 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_SET(value) (((value) << 1) & 0x00000002)
12772 
12773 /*
12774  * Field : channel2
12775  *
12776  * enable bit for CMD-DMA channel 2 receiving an error
12777  *
12778  * Field Access Macros:
12779  *
12780  */
12781 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2 register field. */
12782 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_LSB 2
12783 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2 register field. */
12784 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_MSB 2
12785 /* The width in bits of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2 register field. */
12786 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_WIDTH 1
12787 /* The mask used to set the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2 register field value. */
12788 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_SET_MSK 0x00000004
12789 /* The mask used to clear the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2 register field value. */
12790 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_CLR_MSK 0xfffffffb
12791 /* The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2 register field. */
12792 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_RESET 0x0
12793 /* Extracts the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2 field value from a register. */
12794 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_GET(value) (((value) & 0x00000004) >> 2)
12795 /* Produces a ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2 register field value suitable for setting the register. */
12796 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_SET(value) (((value) << 2) & 0x00000004)
12797 
12798 /*
12799  * Field : channel3
12800  *
12801  * enable bit for CMD-DMA channel 3 receiving an error
12802  *
12803  * Field Access Macros:
12804  *
12805  */
12806 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3 register field. */
12807 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_LSB 3
12808 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3 register field. */
12809 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_MSB 3
12810 /* The width in bits of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3 register field. */
12811 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_WIDTH 1
12812 /* The mask used to set the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3 register field value. */
12813 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_SET_MSK 0x00000008
12814 /* The mask used to clear the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3 register field value. */
12815 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_CLR_MSK 0xfffffff7
12816 /* The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3 register field. */
12817 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_RESET 0x0
12818 /* Extracts the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3 field value from a register. */
12819 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_GET(value) (((value) & 0x00000008) >> 3)
12820 /* Produces a ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3 register field value suitable for setting the register. */
12821 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_SET(value) (((value) << 3) & 0x00000008)
12822 
12823 #ifndef __ASSEMBLY__
12824 /*
12825  * WARNING: The C register and register group struct declarations are provided for
12826  * convenience and illustrative purposes. They should, however, be used with
12827  * caution as the C language standard provides no guarantees about the alignment or
12828  * atomicity of device memory accesses. The recommended practice for writing
12829  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12830  * alt_write_word() functions.
12831  *
12832  * The struct declaration for register ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN.
12833  */
12834 struct ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_s
12835 {
12836  uint32_t channel0 : 1; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0 */
12837  uint32_t channel1 : 1; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1 */
12838  uint32_t channel2 : 1; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2 */
12839  uint32_t channel3 : 1; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3 */
12840  uint32_t : 28; /* *UNDEFINED* */
12841 };
12842 
12843 /* The typedef declaration for register ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN. */
12844 typedef volatile struct ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_s ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_t;
12845 #endif /* __ASSEMBLY__ */
12846 
12847 /* The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN register. */
12848 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_RESET 0x00000000
12849 /* The byte offset of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN register from the beginning of the component. */
12850 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_OFST 0xd0
12851 
12852 #ifndef __ASSEMBLY__
12853 /*
12854  * WARNING: The C register and register group struct declarations are provided for
12855  * convenience and illustrative purposes. They should, however, be used with
12856  * caution as the C language standard provides no guarantees about the alignment or
12857  * atomicity of device memory accesses. The recommended practice for writing
12858  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12859  * alt_write_word() functions.
12860  *
12861  * The struct declaration for register group ALT_NAND_DMA.
12862  */
12863 struct ALT_NAND_DMA_s
12864 {
12865  ALT_NAND_DMA_DMA_EN_t dma_enable; /* ALT_NAND_DMA_DMA_EN */
12866  volatile uint32_t _pad_0x4_0x1f[7]; /* *UNDEFINED* */
12867  ALT_NAND_DMA_DMA_INTR_t dma_intr; /* ALT_NAND_DMA_DMA_INTR */
12868  volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
12869  ALT_NAND_DMA_DMA_INTR_EN_t dma_intr_en; /* ALT_NAND_DMA_DMA_INTR_EN */
12870  volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
12871  ALT_NAND_DMA_TGT_ERR_ADDR_LO_t target_err_addr_lo; /* ALT_NAND_DMA_TGT_ERR_ADDR_LO */
12872  volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
12873  ALT_NAND_DMA_TGT_ERR_ADDR_HI_t target_err_addr_hi; /* ALT_NAND_DMA_TGT_ERR_ADDR_HI */
12874  volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
12875  ALT_NAND_DMA_CHNL_ACT_t chnl_active; /* ALT_NAND_DMA_CHNL_ACT */
12876  volatile uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */
12877  ALT_NAND_DMA_FLSH_BURST_LEN_t flash_burst_length; /* ALT_NAND_DMA_FLSH_BURST_LEN */
12878  volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
12879  ALT_NAND_DMA_INTRLV_t chip_interleave_enable_and_allow_int_reads; /* ALT_NAND_DMA_INTRLV */
12880  volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
12881  ALT_NAND_DMA_RESCAN_BUF_FLAG_t rescan_buffer_flag; /* ALT_NAND_DMA_RESCAN_BUF_FLAG */
12882  volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
12883  ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_t no_of_blocks_per_lun; /* ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN */
12884  volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
12885  ALT_NAND_DMA_LUN_STAT_CMD_t lun_status_cmd; /* ALT_NAND_DMA_LUN_STAT_CMD */
12886  volatile uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */
12887  ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_t cmd_dma_channel_error; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR */
12888  volatile uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */
12889  ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_t cmd_dma_channel_error_en; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN */
12890 };
12891 
12892 /* The typedef declaration for register group ALT_NAND_DMA. */
12893 typedef volatile struct ALT_NAND_DMA_s ALT_NAND_DMA_t;
12894 /* The struct declaration for the raw register contents of register group ALT_NAND_DMA. */
12895 struct ALT_NAND_DMA_raw_s
12896 {
12897  volatile uint32_t dma_enable; /* ALT_NAND_DMA_DMA_EN */
12898  uint32_t _pad_0x4_0x1f[7]; /* *UNDEFINED* */
12899  volatile uint32_t dma_intr; /* ALT_NAND_DMA_DMA_INTR */
12900  uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
12901  volatile uint32_t dma_intr_en; /* ALT_NAND_DMA_DMA_INTR_EN */
12902  uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
12903  volatile uint32_t target_err_addr_lo; /* ALT_NAND_DMA_TGT_ERR_ADDR_LO */
12904  uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
12905  volatile uint32_t target_err_addr_hi; /* ALT_NAND_DMA_TGT_ERR_ADDR_HI */
12906  uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
12907  volatile uint32_t chnl_active; /* ALT_NAND_DMA_CHNL_ACT */
12908  uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */
12909  volatile uint32_t flash_burst_length; /* ALT_NAND_DMA_FLSH_BURST_LEN */
12910  uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
12911  volatile uint32_t chip_interleave_enable_and_allow_int_reads; /* ALT_NAND_DMA_INTRLV */
12912  uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
12913  volatile uint32_t rescan_buffer_flag; /* ALT_NAND_DMA_RESCAN_BUF_FLAG */
12914  uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
12915  volatile uint32_t no_of_blocks_per_lun; /* ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN */
12916  uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
12917  volatile uint32_t lun_status_cmd; /* ALT_NAND_DMA_LUN_STAT_CMD */
12918  uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */
12919  volatile uint32_t cmd_dma_channel_error; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR */
12920  uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */
12921  volatile uint32_t cmd_dma_channel_error_en; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN */
12922 };
12923 
12924 /* The typedef declaration for the raw register contents of register group ALT_NAND_DMA. */
12925 typedef volatile struct ALT_NAND_DMA_raw_s ALT_NAND_DMA_raw_t;
12926 #endif /* __ASSEMBLY__ */
12927 
12928 
12929 #ifdef __cplusplus
12930 }
12931 #endif /* __cplusplus */
12932 #endif /* __ALT_SOCAL_NAND_H__ */
12933