35 #ifndef __ALT_SOCAL_I2C_H__
36 #define __ALT_SOCAL_I2C_H__
121 #define ALT_I2C_CON_MST_MOD_E_DIS 0x0
127 #define ALT_I2C_CON_MST_MOD_E_EN 0x1
130 #define ALT_I2C_CON_MST_MOD_LSB 0
132 #define ALT_I2C_CON_MST_MOD_MSB 0
134 #define ALT_I2C_CON_MST_MOD_WIDTH 1
136 #define ALT_I2C_CON_MST_MOD_SET_MSK 0x00000001
138 #define ALT_I2C_CON_MST_MOD_CLR_MSK 0xfffffffe
140 #define ALT_I2C_CON_MST_MOD_RESET 0x1
142 #define ALT_I2C_CON_MST_MOD_GET(value) (((value) & 0x00000001) >> 0)
144 #define ALT_I2C_CON_MST_MOD_SET(value) (((value) << 0) & 0x00000001)
186 #define ALT_I2C_CON_SPEED_E_STANDARD 0x1
192 #define ALT_I2C_CON_SPEED_E_FAST 0x2
195 #define ALT_I2C_CON_SPEED_LSB 1
197 #define ALT_I2C_CON_SPEED_MSB 2
199 #define ALT_I2C_CON_SPEED_WIDTH 2
201 #define ALT_I2C_CON_SPEED_SET_MSK 0x00000006
203 #define ALT_I2C_CON_SPEED_CLR_MSK 0xfffffff9
205 #define ALT_I2C_CON_SPEED_RESET 0x2
207 #define ALT_I2C_CON_SPEED_GET(value) (((value) & 0x00000006) >> 1)
209 #define ALT_I2C_CON_SPEED_SET(value) (((value) << 1) & 0x00000006)
247 #define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT 0x0
253 #define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT 0x1
256 #define ALT_I2C_CON_IC_10BITADDR_SLV_LSB 3
258 #define ALT_I2C_CON_IC_10BITADDR_SLV_MSB 3
260 #define ALT_I2C_CON_IC_10BITADDR_SLV_WIDTH 1
262 #define ALT_I2C_CON_IC_10BITADDR_SLV_SET_MSK 0x00000008
264 #define ALT_I2C_CON_IC_10BITADDR_SLV_CLR_MSK 0xfffffff7
266 #define ALT_I2C_CON_IC_10BITADDR_SLV_RESET 0x1
268 #define ALT_I2C_CON_IC_10BITADDR_SLV_GET(value) (((value) & 0x00000008) >> 3)
270 #define ALT_I2C_CON_IC_10BITADDR_SLV_SET(value) (((value) << 3) & 0x00000008)
320 #define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT 0x0
326 #define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT 0x1
329 #define ALT_I2C_CON_IC_10BITADDR_MST_LSB 4
331 #define ALT_I2C_CON_IC_10BITADDR_MST_MSB 4
333 #define ALT_I2C_CON_IC_10BITADDR_MST_WIDTH 1
335 #define ALT_I2C_CON_IC_10BITADDR_MST_SET_MSK 0x00000010
337 #define ALT_I2C_CON_IC_10BITADDR_MST_CLR_MSK 0xffffffef
339 #define ALT_I2C_CON_IC_10BITADDR_MST_RESET 0x1
341 #define ALT_I2C_CON_IC_10BITADDR_MST_GET(value) (((value) & 0x00000010) >> 4)
343 #define ALT_I2C_CON_IC_10BITADDR_MST_SET(value) (((value) << 4) & 0x00000010)
403 #define ALT_I2C_CON_IC_RESTART_EN_E_DIS 0x0
409 #define ALT_I2C_CON_IC_RESTART_EN_E_EN 0x1
412 #define ALT_I2C_CON_IC_RESTART_EN_LSB 5
414 #define ALT_I2C_CON_IC_RESTART_EN_MSB 5
416 #define ALT_I2C_CON_IC_RESTART_EN_WIDTH 1
418 #define ALT_I2C_CON_IC_RESTART_EN_SET_MSK 0x00000020
420 #define ALT_I2C_CON_IC_RESTART_EN_CLR_MSK 0xffffffdf
422 #define ALT_I2C_CON_IC_RESTART_EN_RESET 0x1
424 #define ALT_I2C_CON_IC_RESTART_EN_GET(value) (((value) & 0x00000020) >> 5)
426 #define ALT_I2C_CON_IC_RESTART_EN_SET(value) (((value) << 5) & 0x00000020)
476 #define ALT_I2C_CON_IC_SLV_DIS_E_EN 0x0
482 #define ALT_I2C_CON_IC_SLV_DIS_E_DIS 0x1
485 #define ALT_I2C_CON_IC_SLV_DIS_LSB 6
487 #define ALT_I2C_CON_IC_SLV_DIS_MSB 6
489 #define ALT_I2C_CON_IC_SLV_DIS_WIDTH 1
491 #define ALT_I2C_CON_IC_SLV_DIS_SET_MSK 0x00000040
493 #define ALT_I2C_CON_IC_SLV_DIS_CLR_MSK 0xffffffbf
495 #define ALT_I2C_CON_IC_SLV_DIS_RESET 0x1
497 #define ALT_I2C_CON_IC_SLV_DIS_GET(value) (((value) & 0x00000040) >> 6)
499 #define ALT_I2C_CON_IC_SLV_DIS_SET(value) (((value) << 6) & 0x00000040)
529 #define ALT_I2C_CON_STOP_DET_IFADDRED_LSB 7
531 #define ALT_I2C_CON_STOP_DET_IFADDRED_MSB 7
533 #define ALT_I2C_CON_STOP_DET_IFADDRED_WIDTH 1
535 #define ALT_I2C_CON_STOP_DET_IFADDRED_SET_MSK 0x00000080
537 #define ALT_I2C_CON_STOP_DET_IFADDRED_CLR_MSK 0xffffff7f
539 #define ALT_I2C_CON_STOP_DET_IFADDRED_RESET 0x0
541 #define ALT_I2C_CON_STOP_DET_IFADDRED_GET(value) (((value) & 0x00000080) >> 7)
543 #define ALT_I2C_CON_STOP_DET_IFADDRED_SET(value) (((value) << 7) & 0x00000080)
558 #define ALT_I2C_CON_TX_EMPTY_CTL_LSB 8
560 #define ALT_I2C_CON_TX_EMPTY_CTL_MSB 8
562 #define ALT_I2C_CON_TX_EMPTY_CTL_WIDTH 1
564 #define ALT_I2C_CON_TX_EMPTY_CTL_SET_MSK 0x00000100
566 #define ALT_I2C_CON_TX_EMPTY_CTL_CLR_MSK 0xfffffeff
568 #define ALT_I2C_CON_TX_EMPTY_CTL_RESET 0x0
570 #define ALT_I2C_CON_TX_EMPTY_CTL_GET(value) (((value) & 0x00000100) >> 8)
572 #define ALT_I2C_CON_TX_EMPTY_CTL_SET(value) (((value) << 8) & 0x00000100)
598 #define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_LSB 9
600 #define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_MSB 9
602 #define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_WIDTH 1
604 #define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_SET_MSK 0x00000200
606 #define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_CLR_MSK 0xfffffdff
608 #define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_RESET 0x0
610 #define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_GET(value) (((value) & 0x00000200) >> 9)
612 #define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_SET(value) (((value) << 9) & 0x00000200)
623 #define ALT_I2C_CON_RSVD_IC_CON_31TO10_LSB 10
625 #define ALT_I2C_CON_RSVD_IC_CON_31TO10_MSB 31
627 #define ALT_I2C_CON_RSVD_IC_CON_31TO10_WIDTH 22
629 #define ALT_I2C_CON_RSVD_IC_CON_31TO10_SET_MSK 0xfffffc00
631 #define ALT_I2C_CON_RSVD_IC_CON_31TO10_CLR_MSK 0x000003ff
633 #define ALT_I2C_CON_RSVD_IC_CON_31TO10_RESET 0x0
635 #define ALT_I2C_CON_RSVD_IC_CON_31TO10_GET(value) (((value) & 0xfffffc00) >> 10)
637 #define ALT_I2C_CON_RSVD_IC_CON_31TO10_SET(value) (((value) << 10) & 0xfffffc00)
652 uint32_t master_mode : 1;
654 uint32_t ic_10bitaddr_slave : 1;
655 const uint32_t ic_10bitaddr_master : 1;
656 uint32_t ic_restart_en : 1;
657 uint32_t ic_slave_disable : 1;
658 uint32_t stop_det_ifaddressed : 1;
659 uint32_t tx_empty_ctrl : 1;
660 uint32_t rx_fifo_full_hld_ctrl : 1;
661 const uint32_t rsvd_ic_con_31to10 : 22;
665 typedef volatile struct ALT_I2C_CON_s ALT_I2C_CON_t;
669 #define ALT_I2C_CON_RESET 0x0000007d
671 #define ALT_I2C_CON_OFST 0x0
673 #define ALT_I2C_CON_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CON_OFST))
754 #define ALT_I2C_TAR_IC_TAR_LSB 0
756 #define ALT_I2C_TAR_IC_TAR_MSB 9
758 #define ALT_I2C_TAR_IC_TAR_WIDTH 10
760 #define ALT_I2C_TAR_IC_TAR_SET_MSK 0x000003ff
762 #define ALT_I2C_TAR_IC_TAR_CLR_MSK 0xfffffc00
764 #define ALT_I2C_TAR_IC_TAR_RESET 0x55
766 #define ALT_I2C_TAR_IC_TAR_GET(value) (((value) & 0x000003ff) >> 0)
768 #define ALT_I2C_TAR_IC_TAR_SET(value) (((value) << 0) & 0x000003ff)
808 #define ALT_I2C_TAR_GC_OR_START_E_GENCALL 0x0
814 #define ALT_I2C_TAR_GC_OR_START_E_STARTBYTE 0x1
817 #define ALT_I2C_TAR_GC_OR_START_LSB 10
819 #define ALT_I2C_TAR_GC_OR_START_MSB 10
821 #define ALT_I2C_TAR_GC_OR_START_WIDTH 1
823 #define ALT_I2C_TAR_GC_OR_START_SET_MSK 0x00000400
825 #define ALT_I2C_TAR_GC_OR_START_CLR_MSK 0xfffffbff
827 #define ALT_I2C_TAR_GC_OR_START_RESET 0x0
829 #define ALT_I2C_TAR_GC_OR_START_GET(value) (((value) & 0x00000400) >> 10)
831 #define ALT_I2C_TAR_GC_OR_START_SET(value) (((value) << 10) & 0x00000400)
865 #define ALT_I2C_TAR_SPECIAL_E_GENCALL 0x0
871 #define ALT_I2C_TAR_SPECIAL_E_STARTBYTE 0x1
874 #define ALT_I2C_TAR_SPECIAL_LSB 11
876 #define ALT_I2C_TAR_SPECIAL_MSB 11
878 #define ALT_I2C_TAR_SPECIAL_WIDTH 1
880 #define ALT_I2C_TAR_SPECIAL_SET_MSK 0x00000800
882 #define ALT_I2C_TAR_SPECIAL_CLR_MSK 0xfffff7ff
884 #define ALT_I2C_TAR_SPECIAL_RESET 0x0
886 #define ALT_I2C_TAR_SPECIAL_GET(value) (((value) & 0x00000800) >> 11)
888 #define ALT_I2C_TAR_SPECIAL_SET(value) (((value) << 11) & 0x00000800)
926 #define ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 0x0
932 #define ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 0x1
935 #define ALT_I2C_TAR_IC_10BITADDR_MST_LSB 12
937 #define ALT_I2C_TAR_IC_10BITADDR_MST_MSB 12
939 #define ALT_I2C_TAR_IC_10BITADDR_MST_WIDTH 1
941 #define ALT_I2C_TAR_IC_10BITADDR_MST_SET_MSK 0x00001000
943 #define ALT_I2C_TAR_IC_10BITADDR_MST_CLR_MSK 0xffffefff
945 #define ALT_I2C_TAR_IC_10BITADDR_MST_RESET 0x1
947 #define ALT_I2C_TAR_IC_10BITADDR_MST_GET(value) (((value) & 0x00001000) >> 12)
949 #define ALT_I2C_TAR_IC_10BITADDR_MST_SET(value) (((value) << 12) & 0x00001000)
964 uint32_t ic_tar : 10;
965 uint32_t gc_or_start : 1;
966 uint32_t special : 1;
967 uint32_t ic_10bitaddr_master : 1;
972 typedef volatile struct ALT_I2C_TAR_s ALT_I2C_TAR_t;
976 #define ALT_I2C_TAR_RESET 0x00001055
978 #define ALT_I2C_TAR_OFST 0x4
980 #define ALT_I2C_TAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TAR_OFST))
1032 #define ALT_I2C_SAR_IC_SAR_LSB 0
1034 #define ALT_I2C_SAR_IC_SAR_MSB 9
1036 #define ALT_I2C_SAR_IC_SAR_WIDTH 10
1038 #define ALT_I2C_SAR_IC_SAR_SET_MSK 0x000003ff
1040 #define ALT_I2C_SAR_IC_SAR_CLR_MSK 0xfffffc00
1042 #define ALT_I2C_SAR_IC_SAR_RESET 0x55
1044 #define ALT_I2C_SAR_IC_SAR_GET(value) (((value) & 0x000003ff) >> 0)
1046 #define ALT_I2C_SAR_IC_SAR_SET(value) (((value) << 0) & 0x000003ff)
1048 #ifndef __ASSEMBLY__
1059 struct ALT_I2C_SAR_s
1061 uint32_t ic_sar : 10;
1066 typedef volatile struct ALT_I2C_SAR_s ALT_I2C_SAR_t;
1070 #define ALT_I2C_SAR_RESET 0x00000055
1072 #define ALT_I2C_SAR_OFST 0x8
1074 #define ALT_I2C_SAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SAR_OFST))
1137 #define ALT_I2C_DATA_CMD_DAT_LSB 0
1139 #define ALT_I2C_DATA_CMD_DAT_MSB 7
1141 #define ALT_I2C_DATA_CMD_DAT_WIDTH 8
1143 #define ALT_I2C_DATA_CMD_DAT_SET_MSK 0x000000ff
1145 #define ALT_I2C_DATA_CMD_DAT_CLR_MSK 0xffffff00
1147 #define ALT_I2C_DATA_CMD_DAT_RESET 0x0
1149 #define ALT_I2C_DATA_CMD_DAT_GET(value) (((value) & 0x000000ff) >> 0)
1151 #define ALT_I2C_DATA_CMD_DAT_SET(value) (((value) << 0) & 0x000000ff)
1218 #define ALT_I2C_DATA_CMD_CMD_E_WR 0x0
1224 #define ALT_I2C_DATA_CMD_CMD_E_RD 0x1
1227 #define ALT_I2C_DATA_CMD_CMD_LSB 8
1229 #define ALT_I2C_DATA_CMD_CMD_MSB 8
1231 #define ALT_I2C_DATA_CMD_CMD_WIDTH 1
1233 #define ALT_I2C_DATA_CMD_CMD_SET_MSK 0x00000100
1235 #define ALT_I2C_DATA_CMD_CMD_CLR_MSK 0xfffffeff
1237 #define ALT_I2C_DATA_CMD_CMD_RESET 0x0
1239 #define ALT_I2C_DATA_CMD_CMD_GET(value) (((value) & 0x00000100) >> 8)
1241 #define ALT_I2C_DATA_CMD_CMD_SET(value) (((value) << 8) & 0x00000100)
1274 #define ALT_I2C_DATA_CMD_STOP_LSB 9
1276 #define ALT_I2C_DATA_CMD_STOP_MSB 9
1278 #define ALT_I2C_DATA_CMD_STOP_WIDTH 1
1280 #define ALT_I2C_DATA_CMD_STOP_SET_MSK 0x00000200
1282 #define ALT_I2C_DATA_CMD_STOP_CLR_MSK 0xfffffdff
1284 #define ALT_I2C_DATA_CMD_STOP_RESET 0x0
1286 #define ALT_I2C_DATA_CMD_STOP_GET(value) (((value) & 0x00000200) >> 9)
1288 #define ALT_I2C_DATA_CMD_STOP_SET(value) (((value) << 9) & 0x00000200)
1318 #define ALT_I2C_DATA_CMD_RESTART_LSB 10
1320 #define ALT_I2C_DATA_CMD_RESTART_MSB 10
1322 #define ALT_I2C_DATA_CMD_RESTART_WIDTH 1
1324 #define ALT_I2C_DATA_CMD_RESTART_SET_MSK 0x00000400
1326 #define ALT_I2C_DATA_CMD_RESTART_CLR_MSK 0xfffffbff
1328 #define ALT_I2C_DATA_CMD_RESTART_RESET 0x0
1330 #define ALT_I2C_DATA_CMD_RESTART_GET(value) (((value) & 0x00000400) >> 10)
1332 #define ALT_I2C_DATA_CMD_RESTART_SET(value) (((value) << 10) & 0x00000400)
1334 #ifndef __ASSEMBLY__
1345 struct ALT_I2C_DATA_CMD_s
1350 uint32_t restart : 1;
1355 typedef volatile struct ALT_I2C_DATA_CMD_s ALT_I2C_DATA_CMD_t;
1359 #define ALT_I2C_DATA_CMD_RESET 0x00000000
1361 #define ALT_I2C_DATA_CMD_OFST 0x10
1363 #define ALT_I2C_DATA_CMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DATA_CMD_OFST))
1425 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB 0
1427 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB 15
1429 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_WIDTH 16
1431 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET_MSK 0x0000ffff
1433 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_CLR_MSK 0xffff0000
1435 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET 0x190
1437 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0)
1439 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff)
1441 #ifndef __ASSEMBLY__
1452 struct ALT_I2C_SS_SCL_HCNT_s
1454 uint32_t ic_ss_scl_hcnt : 16;
1459 typedef volatile struct ALT_I2C_SS_SCL_HCNT_s ALT_I2C_SS_SCL_HCNT_t;
1463 #define ALT_I2C_SS_SCL_HCNT_RESET 0x00000190
1465 #define ALT_I2C_SS_SCL_HCNT_OFST 0x14
1467 #define ALT_I2C_SS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_HCNT_OFST))
1523 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB 0
1525 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB 15
1527 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_WIDTH 16
1529 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET_MSK 0x0000ffff
1531 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_CLR_MSK 0xffff0000
1533 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET 0x1d6
1535 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0)
1537 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff)
1539 #ifndef __ASSEMBLY__
1550 struct ALT_I2C_SS_SCL_LCNT_s
1552 uint32_t ic_ss_scl_lcnt : 16;
1557 typedef volatile struct ALT_I2C_SS_SCL_LCNT_s ALT_I2C_SS_SCL_LCNT_t;
1561 #define ALT_I2C_SS_SCL_LCNT_RESET 0x000001d6
1563 #define ALT_I2C_SS_SCL_LCNT_OFST 0x18
1565 #define ALT_I2C_SS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_LCNT_OFST))
1626 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB 0
1628 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB 15
1630 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_WIDTH 16
1632 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET_MSK 0x0000ffff
1634 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_CLR_MSK 0xffff0000
1636 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET 0x3c
1638 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0)
1640 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff)
1642 #ifndef __ASSEMBLY__
1653 struct ALT_I2C_FS_SCL_HCNT_s
1655 uint32_t ic_fs_scl_hcnt : 16;
1660 typedef volatile struct ALT_I2C_FS_SCL_HCNT_s ALT_I2C_FS_SCL_HCNT_t;
1664 #define ALT_I2C_FS_SCL_HCNT_RESET 0x0000003c
1666 #define ALT_I2C_FS_SCL_HCNT_OFST 0x1c
1668 #define ALT_I2C_FS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_HCNT_OFST))
1732 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB 0
1734 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB 15
1736 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_WIDTH 16
1738 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET_MSK 0x0000ffff
1740 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_CLR_MSK 0xffff0000
1742 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET 0x82
1744 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0)
1746 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff)
1748 #ifndef __ASSEMBLY__
1759 struct ALT_I2C_FS_SCL_LCNT_s
1761 uint32_t ic_fs_scl_lcnt : 16;
1766 typedef volatile struct ALT_I2C_FS_SCL_LCNT_s ALT_I2C_FS_SCL_LCNT_t;
1770 #define ALT_I2C_FS_SCL_LCNT_RESET 0x00000082
1772 #define ALT_I2C_FS_SCL_LCNT_OFST 0x20
1774 #define ALT_I2C_FS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_LCNT_OFST))
1833 #define ALT_I2C_INTR_STAT_R_RX_UNDER_LSB 0
1835 #define ALT_I2C_INTR_STAT_R_RX_UNDER_MSB 0
1837 #define ALT_I2C_INTR_STAT_R_RX_UNDER_WIDTH 1
1839 #define ALT_I2C_INTR_STAT_R_RX_UNDER_SET_MSK 0x00000001
1841 #define ALT_I2C_INTR_STAT_R_RX_UNDER_CLR_MSK 0xfffffffe
1843 #define ALT_I2C_INTR_STAT_R_RX_UNDER_RESET 0x0
1845 #define ALT_I2C_INTR_STAT_R_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
1847 #define ALT_I2C_INTR_STAT_R_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
1875 #define ALT_I2C_INTR_STAT_R_RX_OVER_LSB 1
1877 #define ALT_I2C_INTR_STAT_R_RX_OVER_MSB 1
1879 #define ALT_I2C_INTR_STAT_R_RX_OVER_WIDTH 1
1881 #define ALT_I2C_INTR_STAT_R_RX_OVER_SET_MSK 0x00000002
1883 #define ALT_I2C_INTR_STAT_R_RX_OVER_CLR_MSK 0xfffffffd
1885 #define ALT_I2C_INTR_STAT_R_RX_OVER_RESET 0x0
1887 #define ALT_I2C_INTR_STAT_R_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
1889 #define ALT_I2C_INTR_STAT_R_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
1912 #define ALT_I2C_INTR_STAT_R_RX_FULL_LSB 2
1914 #define ALT_I2C_INTR_STAT_R_RX_FULL_MSB 2
1916 #define ALT_I2C_INTR_STAT_R_RX_FULL_WIDTH 1
1918 #define ALT_I2C_INTR_STAT_R_RX_FULL_SET_MSK 0x00000004
1920 #define ALT_I2C_INTR_STAT_R_RX_FULL_CLR_MSK 0xfffffffb
1922 #define ALT_I2C_INTR_STAT_R_RX_FULL_RESET 0x0
1924 #define ALT_I2C_INTR_STAT_R_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
1926 #define ALT_I2C_INTR_STAT_R_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
1947 #define ALT_I2C_INTR_STAT_R_TX_OVER_LSB 3
1949 #define ALT_I2C_INTR_STAT_R_TX_OVER_MSB 3
1951 #define ALT_I2C_INTR_STAT_R_TX_OVER_WIDTH 1
1953 #define ALT_I2C_INTR_STAT_R_TX_OVER_SET_MSK 0x00000008
1955 #define ALT_I2C_INTR_STAT_R_TX_OVER_CLR_MSK 0xfffffff7
1957 #define ALT_I2C_INTR_STAT_R_TX_OVER_RESET 0x0
1959 #define ALT_I2C_INTR_STAT_R_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
1961 #define ALT_I2C_INTR_STAT_R_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
2000 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_LSB 4
2002 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_MSB 4
2004 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_WIDTH 1
2006 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET_MSK 0x00000010
2008 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_CLR_MSK 0xffffffef
2010 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_RESET 0x0
2012 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
2014 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
2040 #define ALT_I2C_INTR_STAT_R_RD_REQ_LSB 5
2042 #define ALT_I2C_INTR_STAT_R_RD_REQ_MSB 5
2044 #define ALT_I2C_INTR_STAT_R_RD_REQ_WIDTH 1
2046 #define ALT_I2C_INTR_STAT_R_RD_REQ_SET_MSK 0x00000020
2048 #define ALT_I2C_INTR_STAT_R_RD_REQ_CLR_MSK 0xffffffdf
2050 #define ALT_I2C_INTR_STAT_R_RD_REQ_RESET 0x0
2052 #define ALT_I2C_INTR_STAT_R_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
2054 #define ALT_I2C_INTR_STAT_R_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
2087 #define ALT_I2C_INTR_STAT_R_TX_ABRT_LSB 6
2089 #define ALT_I2C_INTR_STAT_R_TX_ABRT_MSB 6
2091 #define ALT_I2C_INTR_STAT_R_TX_ABRT_WIDTH 1
2093 #define ALT_I2C_INTR_STAT_R_TX_ABRT_SET_MSK 0x00000040
2095 #define ALT_I2C_INTR_STAT_R_TX_ABRT_CLR_MSK 0xffffffbf
2097 #define ALT_I2C_INTR_STAT_R_TX_ABRT_RESET 0x0
2099 #define ALT_I2C_INTR_STAT_R_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
2101 #define ALT_I2C_INTR_STAT_R_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
2120 #define ALT_I2C_INTR_STAT_R_RX_DONE_LSB 7
2122 #define ALT_I2C_INTR_STAT_R_RX_DONE_MSB 7
2124 #define ALT_I2C_INTR_STAT_R_RX_DONE_WIDTH 1
2126 #define ALT_I2C_INTR_STAT_R_RX_DONE_SET_MSK 0x00000080
2128 #define ALT_I2C_INTR_STAT_R_RX_DONE_CLR_MSK 0xffffff7f
2130 #define ALT_I2C_INTR_STAT_R_RX_DONE_RESET 0x0
2132 #define ALT_I2C_INTR_STAT_R_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
2134 #define ALT_I2C_INTR_STAT_R_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
2164 #define ALT_I2C_INTR_STAT_R_ACTIVITY_LSB 8
2166 #define ALT_I2C_INTR_STAT_R_ACTIVITY_MSB 8
2168 #define ALT_I2C_INTR_STAT_R_ACTIVITY_WIDTH 1
2170 #define ALT_I2C_INTR_STAT_R_ACTIVITY_SET_MSK 0x00000100
2172 #define ALT_I2C_INTR_STAT_R_ACTIVITY_CLR_MSK 0xfffffeff
2174 #define ALT_I2C_INTR_STAT_R_ACTIVITY_RESET 0x0
2176 #define ALT_I2C_INTR_STAT_R_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
2178 #define ALT_I2C_INTR_STAT_R_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
2220 #define ALT_I2C_INTR_STAT_R_STOP_DET_LSB 9
2222 #define ALT_I2C_INTR_STAT_R_STOP_DET_MSB 9
2224 #define ALT_I2C_INTR_STAT_R_STOP_DET_WIDTH 1
2226 #define ALT_I2C_INTR_STAT_R_STOP_DET_SET_MSK 0x00000200
2228 #define ALT_I2C_INTR_STAT_R_STOP_DET_CLR_MSK 0xfffffdff
2230 #define ALT_I2C_INTR_STAT_R_STOP_DET_RESET 0x0
2232 #define ALT_I2C_INTR_STAT_R_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
2234 #define ALT_I2C_INTR_STAT_R_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
2251 #define ALT_I2C_INTR_STAT_R_START_DET_LSB 10
2253 #define ALT_I2C_INTR_STAT_R_START_DET_MSB 10
2255 #define ALT_I2C_INTR_STAT_R_START_DET_WIDTH 1
2257 #define ALT_I2C_INTR_STAT_R_START_DET_SET_MSK 0x00000400
2259 #define ALT_I2C_INTR_STAT_R_START_DET_CLR_MSK 0xfffffbff
2261 #define ALT_I2C_INTR_STAT_R_START_DET_RESET 0x0
2263 #define ALT_I2C_INTR_STAT_R_START_DET_GET(value) (((value) & 0x00000400) >> 10)
2265 #define ALT_I2C_INTR_STAT_R_START_DET_SET(value) (((value) << 10) & 0x00000400)
2284 #define ALT_I2C_INTR_STAT_R_GEN_CALL_LSB 11
2286 #define ALT_I2C_INTR_STAT_R_GEN_CALL_MSB 11
2288 #define ALT_I2C_INTR_STAT_R_GEN_CALL_WIDTH 1
2290 #define ALT_I2C_INTR_STAT_R_GEN_CALL_SET_MSK 0x00000800
2292 #define ALT_I2C_INTR_STAT_R_GEN_CALL_CLR_MSK 0xfffff7ff
2294 #define ALT_I2C_INTR_STAT_R_GEN_CALL_RESET 0x0
2296 #define ALT_I2C_INTR_STAT_R_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
2298 #define ALT_I2C_INTR_STAT_R_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
2314 #define ALT_I2C_INTR_STAT_R_RESTART_DET_LSB 12
2316 #define ALT_I2C_INTR_STAT_R_RESTART_DET_MSB 12
2318 #define ALT_I2C_INTR_STAT_R_RESTART_DET_WIDTH 1
2320 #define ALT_I2C_INTR_STAT_R_RESTART_DET_SET_MSK 0x00001000
2322 #define ALT_I2C_INTR_STAT_R_RESTART_DET_CLR_MSK 0xffffefff
2324 #define ALT_I2C_INTR_STAT_R_RESTART_DET_RESET 0x0
2326 #define ALT_I2C_INTR_STAT_R_RESTART_DET_GET(value) (((value) & 0x00001000) >> 12)
2328 #define ALT_I2C_INTR_STAT_R_RESTART_DET_SET(value) (((value) << 12) & 0x00001000)
2343 #define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_LSB 13
2345 #define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_MSB 13
2347 #define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_WIDTH 1
2349 #define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_SET_MSK 0x00002000
2351 #define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_CLR_MSK 0xffffdfff
2353 #define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_RESET 0x0
2355 #define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_GET(value) (((value) & 0x00002000) >> 13)
2357 #define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_SET(value) (((value) << 13) & 0x00002000)
2359 #ifndef __ASSEMBLY__
2370 struct ALT_I2C_INTR_STAT_s
2372 const uint32_t r_rx_under : 1;
2373 const uint32_t r_rx_over : 1;
2374 const uint32_t r_rx_full : 1;
2375 const uint32_t r_tx_over : 1;
2376 const uint32_t r_tx_empty : 1;
2377 const uint32_t r_rd_req : 1;
2378 const uint32_t r_tx_abrt : 1;
2379 const uint32_t r_rx_done : 1;
2380 const uint32_t r_activity : 1;
2381 const uint32_t r_stop_det : 1;
2382 const uint32_t r_start_det : 1;
2383 const uint32_t r_gen_call : 1;
2384 const uint32_t r_restart_det : 1;
2385 const uint32_t r_master_on_hold : 1;
2390 typedef volatile struct ALT_I2C_INTR_STAT_s ALT_I2C_INTR_STAT_t;
2394 #define ALT_I2C_INTR_STAT_RESET 0x00000000
2396 #define ALT_I2C_INTR_STAT_OFST 0x2c
2398 #define ALT_I2C_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_STAT_OFST))
2454 #define ALT_I2C_INTR_MSK_M_RX_UNDER_LSB 0
2456 #define ALT_I2C_INTR_MSK_M_RX_UNDER_MSB 0
2458 #define ALT_I2C_INTR_MSK_M_RX_UNDER_WIDTH 1
2460 #define ALT_I2C_INTR_MSK_M_RX_UNDER_SET_MSK 0x00000001
2462 #define ALT_I2C_INTR_MSK_M_RX_UNDER_CLR_MSK 0xfffffffe
2464 #define ALT_I2C_INTR_MSK_M_RX_UNDER_RESET 0x1
2466 #define ALT_I2C_INTR_MSK_M_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
2468 #define ALT_I2C_INTR_MSK_M_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
2481 #define ALT_I2C_INTR_MSK_M_RX_OVER_LSB 1
2483 #define ALT_I2C_INTR_MSK_M_RX_OVER_MSB 1
2485 #define ALT_I2C_INTR_MSK_M_RX_OVER_WIDTH 1
2487 #define ALT_I2C_INTR_MSK_M_RX_OVER_SET_MSK 0x00000002
2489 #define ALT_I2C_INTR_MSK_M_RX_OVER_CLR_MSK 0xfffffffd
2491 #define ALT_I2C_INTR_MSK_M_RX_OVER_RESET 0x1
2493 #define ALT_I2C_INTR_MSK_M_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
2495 #define ALT_I2C_INTR_MSK_M_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
2508 #define ALT_I2C_INTR_MSK_M_RX_FULL_LSB 2
2510 #define ALT_I2C_INTR_MSK_M_RX_FULL_MSB 2
2512 #define ALT_I2C_INTR_MSK_M_RX_FULL_WIDTH 1
2514 #define ALT_I2C_INTR_MSK_M_RX_FULL_SET_MSK 0x00000004
2516 #define ALT_I2C_INTR_MSK_M_RX_FULL_CLR_MSK 0xfffffffb
2518 #define ALT_I2C_INTR_MSK_M_RX_FULL_RESET 0x1
2520 #define ALT_I2C_INTR_MSK_M_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
2522 #define ALT_I2C_INTR_MSK_M_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
2535 #define ALT_I2C_INTR_MSK_M_TX_OVER_LSB 3
2537 #define ALT_I2C_INTR_MSK_M_TX_OVER_MSB 3
2539 #define ALT_I2C_INTR_MSK_M_TX_OVER_WIDTH 1
2541 #define ALT_I2C_INTR_MSK_M_TX_OVER_SET_MSK 0x00000008
2543 #define ALT_I2C_INTR_MSK_M_TX_OVER_CLR_MSK 0xfffffff7
2545 #define ALT_I2C_INTR_MSK_M_TX_OVER_RESET 0x1
2547 #define ALT_I2C_INTR_MSK_M_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
2549 #define ALT_I2C_INTR_MSK_M_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
2562 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_LSB 4
2564 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_MSB 4
2566 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_WIDTH 1
2568 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET_MSK 0x00000010
2570 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_CLR_MSK 0xffffffef
2572 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_RESET 0x1
2574 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
2576 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
2589 #define ALT_I2C_INTR_MSK_M_RD_REQ_LSB 5
2591 #define ALT_I2C_INTR_MSK_M_RD_REQ_MSB 5
2593 #define ALT_I2C_INTR_MSK_M_RD_REQ_WIDTH 1
2595 #define ALT_I2C_INTR_MSK_M_RD_REQ_SET_MSK 0x00000020
2597 #define ALT_I2C_INTR_MSK_M_RD_REQ_CLR_MSK 0xffffffdf
2599 #define ALT_I2C_INTR_MSK_M_RD_REQ_RESET 0x1
2601 #define ALT_I2C_INTR_MSK_M_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
2603 #define ALT_I2C_INTR_MSK_M_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
2616 #define ALT_I2C_INTR_MSK_M_TX_ABRT_LSB 6
2618 #define ALT_I2C_INTR_MSK_M_TX_ABRT_MSB 6
2620 #define ALT_I2C_INTR_MSK_M_TX_ABRT_WIDTH 1
2622 #define ALT_I2C_INTR_MSK_M_TX_ABRT_SET_MSK 0x00000040
2624 #define ALT_I2C_INTR_MSK_M_TX_ABRT_CLR_MSK 0xffffffbf
2626 #define ALT_I2C_INTR_MSK_M_TX_ABRT_RESET 0x1
2628 #define ALT_I2C_INTR_MSK_M_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
2630 #define ALT_I2C_INTR_MSK_M_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
2643 #define ALT_I2C_INTR_MSK_M_RX_DONE_LSB 7
2645 #define ALT_I2C_INTR_MSK_M_RX_DONE_MSB 7
2647 #define ALT_I2C_INTR_MSK_M_RX_DONE_WIDTH 1
2649 #define ALT_I2C_INTR_MSK_M_RX_DONE_SET_MSK 0x00000080
2651 #define ALT_I2C_INTR_MSK_M_RX_DONE_CLR_MSK 0xffffff7f
2653 #define ALT_I2C_INTR_MSK_M_RX_DONE_RESET 0x1
2655 #define ALT_I2C_INTR_MSK_M_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
2657 #define ALT_I2C_INTR_MSK_M_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
2670 #define ALT_I2C_INTR_MSK_M_ACTIVITY_LSB 8
2672 #define ALT_I2C_INTR_MSK_M_ACTIVITY_MSB 8
2674 #define ALT_I2C_INTR_MSK_M_ACTIVITY_WIDTH 1
2676 #define ALT_I2C_INTR_MSK_M_ACTIVITY_SET_MSK 0x00000100
2678 #define ALT_I2C_INTR_MSK_M_ACTIVITY_CLR_MSK 0xfffffeff
2680 #define ALT_I2C_INTR_MSK_M_ACTIVITY_RESET 0x0
2682 #define ALT_I2C_INTR_MSK_M_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
2684 #define ALT_I2C_INTR_MSK_M_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
2697 #define ALT_I2C_INTR_MSK_M_STOP_DET_LSB 9
2699 #define ALT_I2C_INTR_MSK_M_STOP_DET_MSB 9
2701 #define ALT_I2C_INTR_MSK_M_STOP_DET_WIDTH 1
2703 #define ALT_I2C_INTR_MSK_M_STOP_DET_SET_MSK 0x00000200
2705 #define ALT_I2C_INTR_MSK_M_STOP_DET_CLR_MSK 0xfffffdff
2707 #define ALT_I2C_INTR_MSK_M_STOP_DET_RESET 0x0
2709 #define ALT_I2C_INTR_MSK_M_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
2711 #define ALT_I2C_INTR_MSK_M_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
2724 #define ALT_I2C_INTR_MSK_M_START_DET_LSB 10
2726 #define ALT_I2C_INTR_MSK_M_START_DET_MSB 10
2728 #define ALT_I2C_INTR_MSK_M_START_DET_WIDTH 1
2730 #define ALT_I2C_INTR_MSK_M_START_DET_SET_MSK 0x00000400
2732 #define ALT_I2C_INTR_MSK_M_START_DET_CLR_MSK 0xfffffbff
2734 #define ALT_I2C_INTR_MSK_M_START_DET_RESET 0x0
2736 #define ALT_I2C_INTR_MSK_M_START_DET_GET(value) (((value) & 0x00000400) >> 10)
2738 #define ALT_I2C_INTR_MSK_M_START_DET_SET(value) (((value) << 10) & 0x00000400)
2751 #define ALT_I2C_INTR_MSK_M_GEN_CALL_LSB 11
2753 #define ALT_I2C_INTR_MSK_M_GEN_CALL_MSB 11
2755 #define ALT_I2C_INTR_MSK_M_GEN_CALL_WIDTH 1
2757 #define ALT_I2C_INTR_MSK_M_GEN_CALL_SET_MSK 0x00000800
2759 #define ALT_I2C_INTR_MSK_M_GEN_CALL_CLR_MSK 0xfffff7ff
2761 #define ALT_I2C_INTR_MSK_M_GEN_CALL_RESET 0x1
2763 #define ALT_I2C_INTR_MSK_M_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
2765 #define ALT_I2C_INTR_MSK_M_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
2778 #define ALT_I2C_INTR_MSK_M_RESTART_DET_LSB 12
2780 #define ALT_I2C_INTR_MSK_M_RESTART_DET_MSB 12
2782 #define ALT_I2C_INTR_MSK_M_RESTART_DET_WIDTH 1
2784 #define ALT_I2C_INTR_MSK_M_RESTART_DET_SET_MSK 0x00001000
2786 #define ALT_I2C_INTR_MSK_M_RESTART_DET_CLR_MSK 0xffffefff
2788 #define ALT_I2C_INTR_MSK_M_RESTART_DET_RESET 0x0
2790 #define ALT_I2C_INTR_MSK_M_RESTART_DET_GET(value) (((value) & 0x00001000) >> 12)
2792 #define ALT_I2C_INTR_MSK_M_RESTART_DET_SET(value) (((value) << 12) & 0x00001000)
2805 #define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_LSB 13
2807 #define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_MSB 13
2809 #define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_WIDTH 1
2811 #define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_SET_MSK 0x00002000
2813 #define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_CLR_MSK 0xffffdfff
2815 #define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_RESET 0x0
2817 #define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_GET(value) (((value) & 0x00002000) >> 13)
2819 #define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_SET(value) (((value) << 13) & 0x00002000)
2821 #ifndef __ASSEMBLY__
2832 struct ALT_I2C_INTR_MSK_s
2834 uint32_t m_rx_under : 1;
2835 uint32_t m_rx_over : 1;
2836 uint32_t m_rx_full : 1;
2837 uint32_t m_tx_over : 1;
2838 uint32_t m_tx_empty : 1;
2839 uint32_t m_rd_req : 1;
2840 uint32_t m_tx_abrt : 1;
2841 uint32_t m_rx_done : 1;
2842 uint32_t m_activity : 1;
2843 uint32_t m_stop_det : 1;
2844 uint32_t m_start_det : 1;
2845 uint32_t m_gen_call : 1;
2846 uint32_t m_restart_det : 1;
2847 uint32_t m_master_on_hold : 1;
2852 typedef volatile struct ALT_I2C_INTR_MSK_s ALT_I2C_INTR_MSK_t;
2856 #define ALT_I2C_INTR_MSK_RESET 0x000008ff
2858 #define ALT_I2C_INTR_MSK_OFST 0x30
2860 #define ALT_I2C_INTR_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_MSK_OFST))
2915 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_LSB 0
2917 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_MSB 0
2919 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_WIDTH 1
2921 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET_MSK 0x00000001
2923 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_CLR_MSK 0xfffffffe
2925 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_RESET 0x0
2927 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
2929 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
2957 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_LSB 1
2959 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_MSB 1
2961 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_WIDTH 1
2963 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET_MSK 0x00000002
2965 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_CLR_MSK 0xfffffffd
2967 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_RESET 0x0
2969 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
2971 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
2994 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_LSB 2
2996 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_MSB 2
2998 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_WIDTH 1
3000 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET_MSK 0x00000004
3002 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_CLR_MSK 0xfffffffb
3004 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_RESET 0x0
3006 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
3008 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
3029 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_LSB 3
3031 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_MSB 3
3033 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_WIDTH 1
3035 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET_MSK 0x00000008
3037 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_CLR_MSK 0xfffffff7
3039 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_RESET 0x0
3041 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
3043 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
3084 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_LSB 4
3086 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_MSB 4
3088 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_WIDTH 1
3090 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET_MSK 0x00000010
3092 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_CLR_MSK 0xffffffef
3094 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_RESET 0x0
3096 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
3098 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
3124 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_LSB 5
3126 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_MSB 5
3128 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_WIDTH 1
3130 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET_MSK 0x00000020
3132 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_CLR_MSK 0xffffffdf
3134 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_RESET 0x0
3136 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
3138 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
3171 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_LSB 6
3173 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_MSB 6
3175 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_WIDTH 1
3177 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET_MSK 0x00000040
3179 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_CLR_MSK 0xffffffbf
3181 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_RESET 0x0
3183 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
3185 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
3204 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_LSB 7
3206 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_MSB 7
3208 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_WIDTH 1
3210 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET_MSK 0x00000080
3212 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_CLR_MSK 0xffffff7f
3214 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_RESET 0x0
3216 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
3218 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
3248 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_LSB 8
3250 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_MSB 8
3252 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_WIDTH 1
3254 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET_MSK 0x00000100
3256 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_CLR_MSK 0xfffffeff
3258 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_RESET 0x0
3260 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
3262 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
3303 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_LSB 9
3305 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_MSB 9
3307 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_WIDTH 1
3309 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET_MSK 0x00000200
3311 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_CLR_MSK 0xfffffdff
3313 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_RESET 0x0
3315 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
3317 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
3334 #define ALT_I2C_RAW_INTR_STAT_START_DET_LSB 10
3336 #define ALT_I2C_RAW_INTR_STAT_START_DET_MSB 10
3338 #define ALT_I2C_RAW_INTR_STAT_START_DET_WIDTH 1
3340 #define ALT_I2C_RAW_INTR_STAT_START_DET_SET_MSK 0x00000400
3342 #define ALT_I2C_RAW_INTR_STAT_START_DET_CLR_MSK 0xfffffbff
3344 #define ALT_I2C_RAW_INTR_STAT_START_DET_RESET 0x0
3346 #define ALT_I2C_RAW_INTR_STAT_START_DET_GET(value) (((value) & 0x00000400) >> 10)
3348 #define ALT_I2C_RAW_INTR_STAT_START_DET_SET(value) (((value) << 10) & 0x00000400)
3367 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_LSB 11
3369 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_MSB 11
3371 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_WIDTH 1
3373 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET_MSK 0x00000800
3375 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_CLR_MSK 0xfffff7ff
3377 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_RESET 0x0
3379 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
3381 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
3406 #define ALT_I2C_RAW_INTR_STAT_RESTART_DET_LSB 12
3408 #define ALT_I2C_RAW_INTR_STAT_RESTART_DET_MSB 12
3410 #define ALT_I2C_RAW_INTR_STAT_RESTART_DET_WIDTH 1
3412 #define ALT_I2C_RAW_INTR_STAT_RESTART_DET_SET_MSK 0x00001000
3414 #define ALT_I2C_RAW_INTR_STAT_RESTART_DET_CLR_MSK 0xffffefff
3416 #define ALT_I2C_RAW_INTR_STAT_RESTART_DET_RESET 0x0
3418 #define ALT_I2C_RAW_INTR_STAT_RESTART_DET_GET(value) (((value) & 0x00001000) >> 12)
3420 #define ALT_I2C_RAW_INTR_STAT_RESTART_DET_SET(value) (((value) << 12) & 0x00001000)
3435 #define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_LSB 13
3437 #define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_MSB 13
3439 #define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_WIDTH 1
3441 #define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_SET_MSK 0x00002000
3443 #define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_CLR_MSK 0xffffdfff
3445 #define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_RESET 0x0
3447 #define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_GET(value) (((value) & 0x00002000) >> 13)
3449 #define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_SET(value) (((value) << 13) & 0x00002000)
3451 #ifndef __ASSEMBLY__
3462 struct ALT_I2C_RAW_INTR_STAT_s
3464 const uint32_t rx_under : 1;
3465 const uint32_t rx_over : 1;
3466 const uint32_t rx_full : 1;
3467 const uint32_t tx_over : 1;
3468 const uint32_t tx_empty : 1;
3469 const uint32_t rd_req : 1;
3470 const uint32_t tx_abrt : 1;
3471 const uint32_t rx_done : 1;
3472 const uint32_t activity : 1;
3473 const uint32_t stop_det : 1;
3474 const uint32_t start_det : 1;
3475 const uint32_t gen_call : 1;
3476 const uint32_t restart_det : 1;
3477 const uint32_t master_on_hold : 1;
3482 typedef volatile struct ALT_I2C_RAW_INTR_STAT_s ALT_I2C_RAW_INTR_STAT_t;
3486 #define ALT_I2C_RAW_INTR_STAT_RESET 0x00000000
3488 #define ALT_I2C_RAW_INTR_STAT_OFST 0x34
3490 #define ALT_I2C_RAW_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RAW_INTR_STAT_OFST))
3538 #define ALT_I2C_RX_TL_RX_TL_LSB 0
3540 #define ALT_I2C_RX_TL_RX_TL_MSB 7
3542 #define ALT_I2C_RX_TL_RX_TL_WIDTH 8
3544 #define ALT_I2C_RX_TL_RX_TL_SET_MSK 0x000000ff
3546 #define ALT_I2C_RX_TL_RX_TL_CLR_MSK 0xffffff00
3548 #define ALT_I2C_RX_TL_RX_TL_RESET 0x0
3550 #define ALT_I2C_RX_TL_RX_TL_GET(value) (((value) & 0x000000ff) >> 0)
3552 #define ALT_I2C_RX_TL_RX_TL_SET(value) (((value) << 0) & 0x000000ff)
3554 #ifndef __ASSEMBLY__
3565 struct ALT_I2C_RX_TL_s
3572 typedef volatile struct ALT_I2C_RX_TL_s ALT_I2C_RX_TL_t;
3576 #define ALT_I2C_RX_TL_RESET 0x00000000
3578 #define ALT_I2C_RX_TL_OFST 0x38
3580 #define ALT_I2C_RX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RX_TL_OFST))
3628 #define ALT_I2C_TX_TL_TX_TL_LSB 0
3630 #define ALT_I2C_TX_TL_TX_TL_MSB 7
3632 #define ALT_I2C_TX_TL_TX_TL_WIDTH 8
3634 #define ALT_I2C_TX_TL_TX_TL_SET_MSK 0x000000ff
3636 #define ALT_I2C_TX_TL_TX_TL_CLR_MSK 0xffffff00
3638 #define ALT_I2C_TX_TL_TX_TL_RESET 0x0
3640 #define ALT_I2C_TX_TL_TX_TL_GET(value) (((value) & 0x000000ff) >> 0)
3642 #define ALT_I2C_TX_TL_TX_TL_SET(value) (((value) << 0) & 0x000000ff)
3644 #ifndef __ASSEMBLY__
3655 struct ALT_I2C_TX_TL_s
3662 typedef volatile struct ALT_I2C_TX_TL_s ALT_I2C_TX_TL_t;
3666 #define ALT_I2C_TX_TL_RESET 0x00000000
3668 #define ALT_I2C_TX_TL_OFST 0x3c
3670 #define ALT_I2C_TX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_TL_OFST))
3710 #define ALT_I2C_CLR_INTR_CLR_INTR_LSB 0
3712 #define ALT_I2C_CLR_INTR_CLR_INTR_MSB 0
3714 #define ALT_I2C_CLR_INTR_CLR_INTR_WIDTH 1
3716 #define ALT_I2C_CLR_INTR_CLR_INTR_SET_MSK 0x00000001
3718 #define ALT_I2C_CLR_INTR_CLR_INTR_CLR_MSK 0xfffffffe
3720 #define ALT_I2C_CLR_INTR_CLR_INTR_RESET 0x0
3722 #define ALT_I2C_CLR_INTR_CLR_INTR_GET(value) (((value) & 0x00000001) >> 0)
3724 #define ALT_I2C_CLR_INTR_CLR_INTR_SET(value) (((value) << 0) & 0x00000001)
3726 #ifndef __ASSEMBLY__
3737 struct ALT_I2C_CLR_INTR_s
3739 const uint32_t clr_intr : 1;
3744 typedef volatile struct ALT_I2C_CLR_INTR_s ALT_I2C_CLR_INTR_t;
3748 #define ALT_I2C_CLR_INTR_RESET 0x00000000
3750 #define ALT_I2C_CLR_INTR_OFST 0x40
3752 #define ALT_I2C_CLR_INTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_INTR_OFST))
3786 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_LSB 0
3788 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_MSB 0
3790 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_WIDTH 1
3792 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET_MSK 0x00000001
3794 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_CLR_MSK 0xfffffffe
3796 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_RESET 0x0
3798 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
3800 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
3802 #ifndef __ASSEMBLY__
3813 struct ALT_I2C_CLR_RX_UNDER_s
3815 const uint32_t clr_rx_under : 1;
3820 typedef volatile struct ALT_I2C_CLR_RX_UNDER_s ALT_I2C_CLR_RX_UNDER_t;
3824 #define ALT_I2C_CLR_RX_UNDER_RESET 0x00000000
3826 #define ALT_I2C_CLR_RX_UNDER_OFST 0x44
3828 #define ALT_I2C_CLR_RX_UNDER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_UNDER_OFST))
3862 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_LSB 0
3864 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_MSB 0
3866 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_WIDTH 1
3868 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET_MSK 0x00000001
3870 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_CLR_MSK 0xfffffffe
3872 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_RESET 0x0
3874 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_GET(value) (((value) & 0x00000001) >> 0)
3876 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET(value) (((value) << 0) & 0x00000001)
3878 #ifndef __ASSEMBLY__
3889 struct ALT_I2C_CLR_RX_OVER_s
3891 const uint32_t clr_rx_over : 1;
3896 typedef volatile struct ALT_I2C_CLR_RX_OVER_s ALT_I2C_CLR_RX_OVER_t;
3900 #define ALT_I2C_CLR_RX_OVER_RESET 0x00000000
3902 #define ALT_I2C_CLR_RX_OVER_OFST 0x48
3904 #define ALT_I2C_CLR_RX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_OVER_OFST))
3938 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_LSB 0
3940 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_MSB 0
3942 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_WIDTH 1
3944 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET_MSK 0x00000001
3946 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_CLR_MSK 0xfffffffe
3948 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_RESET 0x0
3950 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_GET(value) (((value) & 0x00000001) >> 0)
3952 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET(value) (((value) << 0) & 0x00000001)
3954 #ifndef __ASSEMBLY__
3965 struct ALT_I2C_CLR_TX_OVER_s
3967 const uint32_t clr_tx_over : 1;
3972 typedef volatile struct ALT_I2C_CLR_TX_OVER_s ALT_I2C_CLR_TX_OVER_t;
3976 #define ALT_I2C_CLR_TX_OVER_RESET 0x00000000
3978 #define ALT_I2C_CLR_TX_OVER_OFST 0x4c
3980 #define ALT_I2C_CLR_TX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_OVER_OFST))
4014 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_LSB 0
4016 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_MSB 0
4018 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_WIDTH 1
4020 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET_MSK 0x00000001
4022 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_CLR_MSK 0xfffffffe
4024 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_RESET 0x0
4026 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_GET(value) (((value) & 0x00000001) >> 0)
4028 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET(value) (((value) << 0) & 0x00000001)
4030 #ifndef __ASSEMBLY__
4041 struct ALT_I2C_CLR_RD_REQ_s
4043 const uint32_t clr_rd_req : 1;
4048 typedef volatile struct ALT_I2C_CLR_RD_REQ_s ALT_I2C_CLR_RD_REQ_t;
4052 #define ALT_I2C_CLR_RD_REQ_RESET 0x00000000
4054 #define ALT_I2C_CLR_RD_REQ_OFST 0x50
4056 #define ALT_I2C_CLR_RD_REQ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RD_REQ_OFST))
4100 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_LSB 0
4102 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_MSB 0
4104 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_WIDTH 1
4106 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET_MSK 0x00000001
4108 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_CLR_MSK 0xfffffffe
4110 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_RESET 0x0
4112 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_GET(value) (((value) & 0x00000001) >> 0)
4114 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET(value) (((value) << 0) & 0x00000001)
4116 #ifndef __ASSEMBLY__
4127 struct ALT_I2C_CLR_TX_ABRT_s
4129 const uint32_t clr_tx_abort : 1;
4134 typedef volatile struct ALT_I2C_CLR_TX_ABRT_s ALT_I2C_CLR_TX_ABRT_t;
4138 #define ALT_I2C_CLR_TX_ABRT_RESET 0x00000000
4140 #define ALT_I2C_CLR_TX_ABRT_OFST 0x54
4142 #define ALT_I2C_CLR_TX_ABRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_ABRT_OFST))
4176 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_LSB 0
4178 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_MSB 0
4180 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_WIDTH 1
4182 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET_MSK 0x00000001
4184 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_CLR_MSK 0xfffffffe
4186 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_RESET 0x0
4188 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_GET(value) (((value) & 0x00000001) >> 0)
4190 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET(value) (((value) << 0) & 0x00000001)
4192 #ifndef __ASSEMBLY__
4203 struct ALT_I2C_CLR_RX_DONE_s
4205 const uint32_t clr_rx_done : 1;
4210 typedef volatile struct ALT_I2C_CLR_RX_DONE_s ALT_I2C_CLR_RX_DONE_t;
4214 #define ALT_I2C_CLR_RX_DONE_RESET 0x00000000
4216 #define ALT_I2C_CLR_RX_DONE_OFST 0x58
4218 #define ALT_I2C_CLR_RX_DONE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_DONE_OFST))
4264 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_LSB 0
4266 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_MSB 0
4268 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_WIDTH 1
4270 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET_MSK 0x00000001
4272 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_CLR_MSK 0xfffffffe
4274 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_RESET 0x0
4276 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0)
4278 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET(value) (((value) << 0) & 0x00000001)
4280 #ifndef __ASSEMBLY__
4291 struct ALT_I2C_CLR_ACTIVITY_s
4293 const uint32_t clr_activity : 1;
4298 typedef volatile struct ALT_I2C_CLR_ACTIVITY_s ALT_I2C_CLR_ACTIVITY_t;
4302 #define ALT_I2C_CLR_ACTIVITY_RESET 0x00000000
4304 #define ALT_I2C_CLR_ACTIVITY_OFST 0x5c
4306 #define ALT_I2C_CLR_ACTIVITY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_ACTIVITY_OFST))
4340 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_LSB 0
4342 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_MSB 0
4344 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_WIDTH 1
4346 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET_MSK 0x00000001
4348 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_CLR_MSK 0xfffffffe
4350 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_RESET 0x0
4352 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_GET(value) (((value) & 0x00000001) >> 0)
4354 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET(value) (((value) << 0) & 0x00000001)
4356 #ifndef __ASSEMBLY__
4367 struct ALT_I2C_CLR_STOP_DET_s
4369 const uint32_t clr_stop_det : 1;
4374 typedef volatile struct ALT_I2C_CLR_STOP_DET_s ALT_I2C_CLR_STOP_DET_t;
4378 #define ALT_I2C_CLR_STOP_DET_RESET 0x00000000
4380 #define ALT_I2C_CLR_STOP_DET_OFST 0x60
4382 #define ALT_I2C_CLR_STOP_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_STOP_DET_OFST))
4416 #define ALT_I2C_CLR_START_DET_CLR_START_DET_LSB 0
4418 #define ALT_I2C_CLR_START_DET_CLR_START_DET_MSB 0
4420 #define ALT_I2C_CLR_START_DET_CLR_START_DET_WIDTH 1
4422 #define ALT_I2C_CLR_START_DET_CLR_START_DET_SET_MSK 0x00000001
4424 #define ALT_I2C_CLR_START_DET_CLR_START_DET_CLR_MSK 0xfffffffe
4426 #define ALT_I2C_CLR_START_DET_CLR_START_DET_RESET 0x0
4428 #define ALT_I2C_CLR_START_DET_CLR_START_DET_GET(value) (((value) & 0x00000001) >> 0)
4430 #define ALT_I2C_CLR_START_DET_CLR_START_DET_SET(value) (((value) << 0) & 0x00000001)
4432 #ifndef __ASSEMBLY__
4443 struct ALT_I2C_CLR_START_DET_s
4445 const uint32_t clr_start_det : 1;
4450 typedef volatile struct ALT_I2C_CLR_START_DET_s ALT_I2C_CLR_START_DET_t;
4454 #define ALT_I2C_CLR_START_DET_RESET 0x00000000
4456 #define ALT_I2C_CLR_START_DET_OFST 0x64
4458 #define ALT_I2C_CLR_START_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_START_DET_OFST))
4492 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_LSB 0
4494 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_MSB 0
4496 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_WIDTH 1
4498 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET_MSK 0x00000001
4500 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_CLR_MSK 0xfffffffe
4502 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_RESET 0x0
4504 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0)
4506 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET(value) (((value) << 0) & 0x00000001)
4508 #ifndef __ASSEMBLY__
4519 struct ALT_I2C_CLR_GEN_CALL_s
4521 const uint32_t clr_gen_call : 1;
4526 typedef volatile struct ALT_I2C_CLR_GEN_CALL_s ALT_I2C_CLR_GEN_CALL_t;
4530 #define ALT_I2C_CLR_GEN_CALL_RESET 0x00000000
4532 #define ALT_I2C_CLR_GEN_CALL_OFST 0x68
4534 #define ALT_I2C_CLR_GEN_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_GEN_CALL_OFST))
4616 #define ALT_I2C_EN_EN_E_DIS 0x0
4622 #define ALT_I2C_EN_EN_E_EN 0x1
4625 #define ALT_I2C_EN_EN_LSB 0
4627 #define ALT_I2C_EN_EN_MSB 0
4629 #define ALT_I2C_EN_EN_WIDTH 1
4631 #define ALT_I2C_EN_EN_SET_MSK 0x00000001
4633 #define ALT_I2C_EN_EN_CLR_MSK 0xfffffffe
4635 #define ALT_I2C_EN_EN_RESET 0x0
4637 #define ALT_I2C_EN_EN_GET(value) (((value) & 0x00000001) >> 0)
4639 #define ALT_I2C_EN_EN_SET(value) (((value) << 0) & 0x00000001)
4673 #define ALT_I2C_EN_TXABT_LSB 1
4675 #define ALT_I2C_EN_TXABT_MSB 1
4677 #define ALT_I2C_EN_TXABT_WIDTH 1
4679 #define ALT_I2C_EN_TXABT_SET_MSK 0x00000002
4681 #define ALT_I2C_EN_TXABT_CLR_MSK 0xfffffffd
4683 #define ALT_I2C_EN_TXABT_RESET 0x0
4685 #define ALT_I2C_EN_TXABT_GET(value) (((value) & 0x00000002) >> 1)
4687 #define ALT_I2C_EN_TXABT_SET(value) (((value) << 1) & 0x00000002)
4689 #ifndef __ASSEMBLY__
4702 uint32_t enable : 1;
4703 uint32_t txabort : 1;
4708 typedef volatile struct ALT_I2C_EN_s ALT_I2C_EN_t;
4712 #define ALT_I2C_EN_RESET 0x00000000
4714 #define ALT_I2C_EN_OFST 0x6c
4716 #define ALT_I2C_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_OFST))
4776 #define ALT_I2C_STAT_ACTIVITY_LSB 0
4778 #define ALT_I2C_STAT_ACTIVITY_MSB 0
4780 #define ALT_I2C_STAT_ACTIVITY_WIDTH 1
4782 #define ALT_I2C_STAT_ACTIVITY_SET_MSK 0x00000001
4784 #define ALT_I2C_STAT_ACTIVITY_CLR_MSK 0xfffffffe
4786 #define ALT_I2C_STAT_ACTIVITY_RESET 0x0
4788 #define ALT_I2C_STAT_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0)
4790 #define ALT_I2C_STAT_ACTIVITY_SET(value) (((value) << 0) & 0x00000001)
4822 #define ALT_I2C_STAT_TFNF_E_FULL 0x0
4828 #define ALT_I2C_STAT_TFNF_E_NOTFULL 0x1
4831 #define ALT_I2C_STAT_TFNF_LSB 1
4833 #define ALT_I2C_STAT_TFNF_MSB 1
4835 #define ALT_I2C_STAT_TFNF_WIDTH 1
4837 #define ALT_I2C_STAT_TFNF_SET_MSK 0x00000002
4839 #define ALT_I2C_STAT_TFNF_CLR_MSK 0xfffffffd
4841 #define ALT_I2C_STAT_TFNF_RESET 0x1
4843 #define ALT_I2C_STAT_TFNF_GET(value) (((value) & 0x00000002) >> 1)
4845 #define ALT_I2C_STAT_TFNF_SET(value) (((value) << 1) & 0x00000002)
4879 #define ALT_I2C_STAT_TFE_E_NOTEMPTY 0x0
4885 #define ALT_I2C_STAT_TFE_E_EMPTY 0x1
4888 #define ALT_I2C_STAT_TFE_LSB 2
4890 #define ALT_I2C_STAT_TFE_MSB 2
4892 #define ALT_I2C_STAT_TFE_WIDTH 1
4894 #define ALT_I2C_STAT_TFE_SET_MSK 0x00000004
4896 #define ALT_I2C_STAT_TFE_CLR_MSK 0xfffffffb
4898 #define ALT_I2C_STAT_TFE_RESET 0x1
4900 #define ALT_I2C_STAT_TFE_GET(value) (((value) & 0x00000004) >> 2)
4902 #define ALT_I2C_STAT_TFE_SET(value) (((value) << 2) & 0x00000004)
4934 #define ALT_I2C_STAT_RFNE_E_EMPTY 0x0
4940 #define ALT_I2C_STAT_RFNE_E_NOTEMPTY 0x1
4943 #define ALT_I2C_STAT_RFNE_LSB 3
4945 #define ALT_I2C_STAT_RFNE_MSB 3
4947 #define ALT_I2C_STAT_RFNE_WIDTH 1
4949 #define ALT_I2C_STAT_RFNE_SET_MSK 0x00000008
4951 #define ALT_I2C_STAT_RFNE_CLR_MSK 0xfffffff7
4953 #define ALT_I2C_STAT_RFNE_RESET 0x0
4955 #define ALT_I2C_STAT_RFNE_GET(value) (((value) & 0x00000008) >> 3)
4957 #define ALT_I2C_STAT_RFNE_SET(value) (((value) << 3) & 0x00000008)
4991 #define ALT_I2C_STAT_RFF_E_NOTFULL 0x0
4997 #define ALT_I2C_STAT_RFF_E_FULL 0x1
5000 #define ALT_I2C_STAT_RFF_LSB 4
5002 #define ALT_I2C_STAT_RFF_MSB 4
5004 #define ALT_I2C_STAT_RFF_WIDTH 1
5006 #define ALT_I2C_STAT_RFF_SET_MSK 0x00000010
5008 #define ALT_I2C_STAT_RFF_CLR_MSK 0xffffffef
5010 #define ALT_I2C_STAT_RFF_RESET 0x0
5012 #define ALT_I2C_STAT_RFF_GET(value) (((value) & 0x00000010) >> 4)
5014 #define ALT_I2C_STAT_RFF_SET(value) (((value) << 4) & 0x00000010)
5058 #define ALT_I2C_STAT_MST_ACTIVITY_E_IDLE 0x0
5064 #define ALT_I2C_STAT_MST_ACTIVITY_E_NOTIDLE 0x1
5067 #define ALT_I2C_STAT_MST_ACTIVITY_LSB 5
5069 #define ALT_I2C_STAT_MST_ACTIVITY_MSB 5
5071 #define ALT_I2C_STAT_MST_ACTIVITY_WIDTH 1
5073 #define ALT_I2C_STAT_MST_ACTIVITY_SET_MSK 0x00000020
5075 #define ALT_I2C_STAT_MST_ACTIVITY_CLR_MSK 0xffffffdf
5077 #define ALT_I2C_STAT_MST_ACTIVITY_RESET 0x0
5079 #define ALT_I2C_STAT_MST_ACTIVITY_GET(value) (((value) & 0x00000020) >> 5)
5081 #define ALT_I2C_STAT_MST_ACTIVITY_SET(value) (((value) << 5) & 0x00000020)
5119 #define ALT_I2C_STAT_SLV_ACTIVITY_E_IDLE 0x0
5125 #define ALT_I2C_STAT_SLV_ACTIVITY_E_NOTIDLE 0x1
5128 #define ALT_I2C_STAT_SLV_ACTIVITY_LSB 6
5130 #define ALT_I2C_STAT_SLV_ACTIVITY_MSB 6
5132 #define ALT_I2C_STAT_SLV_ACTIVITY_WIDTH 1
5134 #define ALT_I2C_STAT_SLV_ACTIVITY_SET_MSK 0x00000040
5136 #define ALT_I2C_STAT_SLV_ACTIVITY_CLR_MSK 0xffffffbf
5138 #define ALT_I2C_STAT_SLV_ACTIVITY_RESET 0x0
5140 #define ALT_I2C_STAT_SLV_ACTIVITY_GET(value) (((value) & 0x00000040) >> 6)
5142 #define ALT_I2C_STAT_SLV_ACTIVITY_SET(value) (((value) << 6) & 0x00000040)
5144 #ifndef __ASSEMBLY__
5155 struct ALT_I2C_STAT_s
5157 const uint32_t activity : 1;
5158 const uint32_t tfnf : 1;
5159 const uint32_t tfe : 1;
5160 const uint32_t rfne : 1;
5161 const uint32_t rff : 1;
5162 const uint32_t mst_activity : 1;
5163 const uint32_t slv_activity : 1;
5168 typedef volatile struct ALT_I2C_STAT_s ALT_I2C_STAT_t;
5172 #define ALT_I2C_STAT_RESET 0x00000006
5174 #define ALT_I2C_STAT_OFST 0x70
5176 #define ALT_I2C_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_STAT_OFST))
5232 #define ALT_I2C_TXFLR_TXFLR_LSB 0
5234 #define ALT_I2C_TXFLR_TXFLR_MSB 6
5236 #define ALT_I2C_TXFLR_TXFLR_WIDTH 7
5238 #define ALT_I2C_TXFLR_TXFLR_SET_MSK 0x0000007f
5240 #define ALT_I2C_TXFLR_TXFLR_CLR_MSK 0xffffff80
5242 #define ALT_I2C_TXFLR_TXFLR_RESET 0x0
5244 #define ALT_I2C_TXFLR_TXFLR_GET(value) (((value) & 0x0000007f) >> 0)
5246 #define ALT_I2C_TXFLR_TXFLR_SET(value) (((value) << 0) & 0x0000007f)
5248 #ifndef __ASSEMBLY__
5259 struct ALT_I2C_TXFLR_s
5261 const uint32_t txflr : 7;
5266 typedef volatile struct ALT_I2C_TXFLR_s ALT_I2C_TXFLR_t;
5270 #define ALT_I2C_TXFLR_RESET 0x00000000
5272 #define ALT_I2C_TXFLR_OFST 0x74
5274 #define ALT_I2C_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TXFLR_OFST))
5328 #define ALT_I2C_RXFLR_RXFLR_LSB 0
5330 #define ALT_I2C_RXFLR_RXFLR_MSB 6
5332 #define ALT_I2C_RXFLR_RXFLR_WIDTH 7
5334 #define ALT_I2C_RXFLR_RXFLR_SET_MSK 0x0000007f
5336 #define ALT_I2C_RXFLR_RXFLR_CLR_MSK 0xffffff80
5338 #define ALT_I2C_RXFLR_RXFLR_RESET 0x0
5340 #define ALT_I2C_RXFLR_RXFLR_GET(value) (((value) & 0x0000007f) >> 0)
5342 #define ALT_I2C_RXFLR_RXFLR_SET(value) (((value) << 0) & 0x0000007f)
5344 #ifndef __ASSEMBLY__
5355 struct ALT_I2C_RXFLR_s
5357 const uint32_t rxflr : 7;
5362 typedef volatile struct ALT_I2C_RXFLR_s ALT_I2C_RXFLR_t;
5366 #define ALT_I2C_RXFLR_RESET 0x00000000
5368 #define ALT_I2C_RXFLR_OFST 0x78
5370 #define ALT_I2C_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RXFLR_OFST))
5421 #define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_LSB 0
5423 #define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_MSB 15
5425 #define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_WIDTH 16
5427 #define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_SET_MSK 0x0000ffff
5429 #define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_CLR_MSK 0xffff0000
5431 #define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_RESET 0x1
5433 #define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_GET(value) (((value) & 0x0000ffff) >> 0)
5435 #define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_SET(value) (((value) << 0) & 0x0000ffff)
5450 #define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_LSB 16
5452 #define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_MSB 23
5454 #define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_WIDTH 8
5456 #define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_SET_MSK 0x00ff0000
5458 #define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_CLR_MSK 0xff00ffff
5460 #define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_RESET 0x0
5462 #define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_GET(value) (((value) & 0x00ff0000) >> 16)
5464 #define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_SET(value) (((value) << 16) & 0x00ff0000)
5466 #ifndef __ASSEMBLY__
5477 struct ALT_I2C_SDA_HOLD_s
5479 uint32_t ic_sda_tx_hold : 16;
5480 uint32_t ic_sda_rx_hold : 8;
5485 typedef volatile struct ALT_I2C_SDA_HOLD_s ALT_I2C_SDA_HOLD_t;
5489 #define ALT_I2C_SDA_HOLD_RESET 0x00000001
5491 #define ALT_I2C_SDA_HOLD_OFST 0x7c
5493 #define ALT_I2C_SDA_HOLD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_HOLD_OFST))
5574 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_LSB 0
5576 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_MSB 0
5578 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_WIDTH 1
5580 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET_MSK 0x00000001
5582 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_CLR_MSK 0xfffffffe
5584 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_RESET 0x0
5586 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_GET(value) (((value) & 0x00000001) >> 0)
5588 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET(value) (((value) << 0) & 0x00000001)
5609 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_LSB 1
5611 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_MSB 1
5613 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_WIDTH 1
5615 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET_MSK 0x00000002
5617 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_CLR_MSK 0xfffffffd
5619 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_RESET 0x0
5621 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_GET(value) (((value) & 0x00000002) >> 1)
5623 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET(value) (((value) << 1) & 0x00000002)
5644 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_LSB 2
5646 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_MSB 2
5648 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_WIDTH 1
5650 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET_MSK 0x00000004
5652 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_CLR_MSK 0xfffffffb
5654 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_RESET 0x0
5656 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_GET(value) (((value) & 0x00000004) >> 2)
5658 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET(value) (((value) << 2) & 0x00000004)
5683 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_LSB 3
5685 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_MSB 3
5687 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_WIDTH 1
5689 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET_MSK 0x00000008
5691 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_CLR_MSK 0xfffffff7
5693 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_RESET 0x0
5695 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_GET(value) (((value) & 0x00000008) >> 3)
5697 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET(value) (((value) << 3) & 0x00000008)
5716 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_LSB 4
5718 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_MSB 4
5720 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_WIDTH 1
5722 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET_MSK 0x00000010
5724 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_CLR_MSK 0xffffffef
5726 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_RESET 0x0
5728 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_GET(value) (((value) & 0x00000010) >> 4)
5730 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET(value) (((value) << 4) & 0x00000010)
5753 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_LSB 5
5755 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_MSB 5
5757 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_WIDTH 1
5759 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET_MSK 0x00000020
5761 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_CLR_MSK 0xffffffdf
5763 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_RESET 0x0
5765 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_GET(value) (((value) & 0x00000020) >> 5)
5767 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET(value) (((value) << 5) & 0x00000020)
5786 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_LSB 6
5788 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_MSB 6
5790 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_WIDTH 1
5792 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET_MSK 0x00000040
5794 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_CLR_MSK 0xffffffbf
5796 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_RESET 0x0
5798 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_GET(value) (((value) & 0x00000040) >> 6)
5800 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET(value) (((value) << 6) & 0x00000040)
5817 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_LSB 7
5819 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_MSB 7
5821 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_WIDTH 1
5823 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET_MSK 0x00000080
5825 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_CLR_MSK 0xffffff7f
5827 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_RESET 0x0
5829 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_GET(value) (((value) & 0x00000080) >> 7)
5831 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET(value) (((value) << 7) & 0x00000080)
5856 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_LSB 8
5858 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_MSB 8
5860 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_WIDTH 1
5862 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET_MSK 0x00000100
5864 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_CLR_MSK 0xfffffeff
5866 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_RESET 0x0
5868 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_GET(value) (((value) & 0x00000100) >> 8)
5870 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET(value) (((value) << 8) & 0x00000100)
5913 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_LSB 9
5915 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_MSB 9
5917 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_WIDTH 1
5919 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET_MSK 0x00000200
5921 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_CLR_MSK 0xfffffdff
5923 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_RESET 0x0
5925 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_GET(value) (((value) & 0x00000200) >> 9)
5927 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET(value) (((value) << 9) & 0x00000200)
5948 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_LSB 10
5950 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_MSB 10
5952 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_WIDTH 1
5954 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET_MSK 0x00000400
5956 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_CLR_MSK 0xfffffbff
5958 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_RESET 0x0
5960 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_GET(value) (((value) & 0x00000400) >> 10)
5962 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET(value) (((value) << 10) & 0x00000400)
5981 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_LSB 11
5983 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_MSB 11
5985 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_WIDTH 1
5987 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET_MSK 0x00000800
5989 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_CLR_MSK 0xfffff7ff
5991 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_RESET 0x0
5993 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_GET(value) (((value) & 0x00000800) >> 11)
5995 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET(value) (((value) << 11) & 0x00000800)
6018 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_LSB 12
6020 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_MSB 12
6022 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_WIDTH 1
6024 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET_MSK 0x00001000
6026 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_CLR_MSK 0xffffefff
6028 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_RESET 0x0
6030 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_GET(value) (((value) & 0x00001000) >> 12)
6032 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET(value) (((value) << 12) & 0x00001000)
6053 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_LSB 13
6055 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_MSB 13
6057 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_WIDTH 1
6059 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET_MSK 0x00002000
6061 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_CLR_MSK 0xffffdfff
6063 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_RESET 0x0
6065 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_GET(value) (((value) & 0x00002000) >> 13)
6067 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET(value) (((value) << 13) & 0x00002000)
6106 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_LSB 14
6108 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_MSB 14
6110 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_WIDTH 1
6112 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET_MSK 0x00004000
6114 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_CLR_MSK 0xffffbfff
6116 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_RESET 0x0
6118 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_GET(value) (((value) & 0x00004000) >> 14)
6120 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET(value) (((value) << 14) & 0x00004000)
6143 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_LSB 15
6145 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_MSB 15
6147 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_WIDTH 1
6149 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET_MSK 0x00008000
6151 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_CLR_MSK 0xffff7fff
6153 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_RESET 0x0
6155 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_GET(value) (((value) & 0x00008000) >> 15)
6157 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET(value) (((value) << 15) & 0x00008000)
6174 #define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_LSB 16
6176 #define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_MSB 16
6178 #define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_WIDTH 1
6180 #define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_SET_MSK 0x00010000
6182 #define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_CLR_MSK 0xfffeffff
6184 #define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_RESET 0x0
6186 #define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_GET(value) (((value) & 0x00010000) >> 16)
6188 #define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_SET(value) (((value) << 16) & 0x00010000)
6201 #define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_LSB 17
6203 #define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_MSB 22
6205 #define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_WIDTH 6
6207 #define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_SET_MSK 0x007e0000
6209 #define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_CLR_MSK 0xff81ffff
6211 #define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_RESET 0x0
6213 #define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_GET(value) (((value) & 0x007e0000) >> 17)
6215 #define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_SET(value) (((value) << 17) & 0x007e0000)
6234 #define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_LSB 23
6236 #define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_MSB 31
6238 #define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_WIDTH 9
6240 #define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_SET_MSK 0xff800000
6242 #define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_CLR_MSK 0x007fffff
6244 #define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_RESET 0x0
6246 #define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_GET(value) (((value) & 0xff800000) >> 23)
6248 #define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_SET(value) (((value) << 23) & 0xff800000)
6250 #ifndef __ASSEMBLY__
6261 struct ALT_I2C_TX_ABRT_SRC_s
6263 const uint32_t abrt_7b_addr_noack : 1;
6264 const uint32_t abrt_10addr1_noack : 1;
6265 const uint32_t abrt_10addr2_noack : 1;
6266 const uint32_t abrt_txdata_noack : 1;
6267 const uint32_t abrt_gcall_noack : 1;
6268 const uint32_t abrt_gcall_read : 1;
6269 const uint32_t abrt_hs_ackdet : 1;
6270 const uint32_t abrt_sbyte_ackdet : 1;
6271 const uint32_t abrt_hs_norstrt : 1;
6272 const uint32_t abrt_sbyte_norstrt : 1;
6273 const uint32_t abrt_10b_rd_norstrt : 1;
6274 const uint32_t abrt_master_dis : 1;
6275 const uint32_t arb_lost : 1;
6276 const uint32_t abrt_slvflush_txfifo : 1;
6277 const uint32_t abrt_slv_arblost : 1;
6278 const uint32_t abrt_slvrd_intx : 1;
6279 const uint32_t abrt_user_abrt : 1;
6280 const uint32_t rsvd_ic_tx_abrt_source_22to17 : 6;
6281 const uint32_t tx_flush_cnt : 9;
6285 typedef volatile struct ALT_I2C_TX_ABRT_SRC_s ALT_I2C_TX_ABRT_SRC_t;
6289 #define ALT_I2C_TX_ABRT_SRC_RESET 0x00000000
6291 #define ALT_I2C_TX_ABRT_SRC_OFST 0x80
6293 #define ALT_I2C_TX_ABRT_SRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_ABRT_SRC_OFST))
6368 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_NORM 0x0
6374 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_AFTERDBYTE 0x1
6377 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_LSB 0
6379 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_MSB 0
6381 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_WIDTH 1
6383 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET_MSK 0x00000001
6385 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_CLR_MSK 0xfffffffe
6387 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_RESET 0x0
6389 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_GET(value) (((value) & 0x00000001) >> 0)
6391 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET(value) (((value) << 0) & 0x00000001)
6393 #ifndef __ASSEMBLY__
6404 struct ALT_I2C_SLV_DATA_NACK_ONLY_s
6411 typedef volatile struct ALT_I2C_SLV_DATA_NACK_ONLY_s ALT_I2C_SLV_DATA_NACK_ONLY_t;
6415 #define ALT_I2C_SLV_DATA_NACK_ONLY_RESET 0x00000000
6417 #define ALT_I2C_SLV_DATA_NACK_ONLY_OFST 0x84
6419 #define ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SLV_DATA_NACK_ONLY_OFST))
6487 #define ALT_I2C_DMA_CR_RDMAE_E_DIS 0x0
6493 #define ALT_I2C_DMA_CR_RDMAE_E_EN 0x1
6496 #define ALT_I2C_DMA_CR_RDMAE_LSB 0
6498 #define ALT_I2C_DMA_CR_RDMAE_MSB 0
6500 #define ALT_I2C_DMA_CR_RDMAE_WIDTH 1
6502 #define ALT_I2C_DMA_CR_RDMAE_SET_MSK 0x00000001
6504 #define ALT_I2C_DMA_CR_RDMAE_CLR_MSK 0xfffffffe
6506 #define ALT_I2C_DMA_CR_RDMAE_RESET 0x0
6508 #define ALT_I2C_DMA_CR_RDMAE_GET(value) (((value) & 0x00000001) >> 0)
6510 #define ALT_I2C_DMA_CR_RDMAE_SET(value) (((value) << 0) & 0x00000001)
6542 #define ALT_I2C_DMA_CR_TDMAE_E_DIS 0x0
6548 #define ALT_I2C_DMA_CR_TDMAE_E_EN 0x1
6551 #define ALT_I2C_DMA_CR_TDMAE_LSB 1
6553 #define ALT_I2C_DMA_CR_TDMAE_MSB 1
6555 #define ALT_I2C_DMA_CR_TDMAE_WIDTH 1
6557 #define ALT_I2C_DMA_CR_TDMAE_SET_MSK 0x00000002
6559 #define ALT_I2C_DMA_CR_TDMAE_CLR_MSK 0xfffffffd
6561 #define ALT_I2C_DMA_CR_TDMAE_RESET 0x0
6563 #define ALT_I2C_DMA_CR_TDMAE_GET(value) (((value) & 0x00000002) >> 1)
6565 #define ALT_I2C_DMA_CR_TDMAE_SET(value) (((value) << 1) & 0x00000002)
6576 #define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_LSB 2
6578 #define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_MSB 31
6580 #define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_WIDTH 30
6582 #define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_SET_MSK 0xfffffffc
6584 #define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_CLR_MSK 0x00000003
6586 #define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_RESET 0x0
6588 #define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_GET(value) (((value) & 0xfffffffc) >> 2)
6590 #define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_SET(value) (((value) << 2) & 0xfffffffc)
6592 #ifndef __ASSEMBLY__
6603 struct ALT_I2C_DMA_CR_s
6607 const uint32_t rsvd_ic_dma_cr_31to2 : 30;
6611 typedef volatile struct ALT_I2C_DMA_CR_s ALT_I2C_DMA_CR_t;
6615 #define ALT_I2C_DMA_CR_RESET 0x00000000
6617 #define ALT_I2C_DMA_CR_OFST 0x88
6619 #define ALT_I2C_DMA_CR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_CR_OFST))
6675 #define ALT_I2C_DMA_TDLR_DMATDL_LSB 0
6677 #define ALT_I2C_DMA_TDLR_DMATDL_MSB 5
6679 #define ALT_I2C_DMA_TDLR_DMATDL_WIDTH 6
6681 #define ALT_I2C_DMA_TDLR_DMATDL_SET_MSK 0x0000003f
6683 #define ALT_I2C_DMA_TDLR_DMATDL_CLR_MSK 0xffffffc0
6685 #define ALT_I2C_DMA_TDLR_DMATDL_RESET 0x0
6687 #define ALT_I2C_DMA_TDLR_DMATDL_GET(value) (((value) & 0x0000003f) >> 0)
6689 #define ALT_I2C_DMA_TDLR_DMATDL_SET(value) (((value) << 0) & 0x0000003f)
6691 #ifndef __ASSEMBLY__
6702 struct ALT_I2C_DMA_TDLR_s
6704 uint32_t dmatdl : 6;
6709 typedef volatile struct ALT_I2C_DMA_TDLR_s ALT_I2C_DMA_TDLR_t;
6713 #define ALT_I2C_DMA_TDLR_RESET 0x00000000
6715 #define ALT_I2C_DMA_TDLR_OFST 0x8c
6717 #define ALT_I2C_DMA_TDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_TDLR_OFST))
6775 #define ALT_I2C_DMA_RDLR_DMARDL_LSB 0
6777 #define ALT_I2C_DMA_RDLR_DMARDL_MSB 5
6779 #define ALT_I2C_DMA_RDLR_DMARDL_WIDTH 6
6781 #define ALT_I2C_DMA_RDLR_DMARDL_SET_MSK 0x0000003f
6783 #define ALT_I2C_DMA_RDLR_DMARDL_CLR_MSK 0xffffffc0
6785 #define ALT_I2C_DMA_RDLR_DMARDL_RESET 0x0
6787 #define ALT_I2C_DMA_RDLR_DMARDL_GET(value) (((value) & 0x0000003f) >> 0)
6789 #define ALT_I2C_DMA_RDLR_DMARDL_SET(value) (((value) << 0) & 0x0000003f)
6791 #ifndef __ASSEMBLY__
6802 struct ALT_I2C_DMA_RDLR_s
6804 uint32_t dmardl : 6;
6809 typedef volatile struct ALT_I2C_DMA_RDLR_s ALT_I2C_DMA_RDLR_t;
6813 #define ALT_I2C_DMA_RDLR_RESET 0x00000000
6815 #define ALT_I2C_DMA_RDLR_OFST 0x90
6817 #define ALT_I2C_DMA_RDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_RDLR_OFST))
6869 #define ALT_I2C_SDA_SETUP_SDA_SETUP_LSB 0
6871 #define ALT_I2C_SDA_SETUP_SDA_SETUP_MSB 7
6873 #define ALT_I2C_SDA_SETUP_SDA_SETUP_WIDTH 8
6875 #define ALT_I2C_SDA_SETUP_SDA_SETUP_SET_MSK 0x000000ff
6877 #define ALT_I2C_SDA_SETUP_SDA_SETUP_CLR_MSK 0xffffff00
6879 #define ALT_I2C_SDA_SETUP_SDA_SETUP_RESET 0x64
6881 #define ALT_I2C_SDA_SETUP_SDA_SETUP_GET(value) (((value) & 0x000000ff) >> 0)
6883 #define ALT_I2C_SDA_SETUP_SDA_SETUP_SET(value) (((value) << 0) & 0x000000ff)
6885 #ifndef __ASSEMBLY__
6896 struct ALT_I2C_SDA_SETUP_s
6898 uint32_t sda_setup : 8;
6903 typedef volatile struct ALT_I2C_SDA_SETUP_s ALT_I2C_SDA_SETUP_t;
6907 #define ALT_I2C_SDA_SETUP_RESET 0x00000064
6909 #define ALT_I2C_SDA_SETUP_OFST 0x94
6911 #define ALT_I2C_SDA_SETUP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_SETUP_OFST))
6972 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_NACK 0x0
6978 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ACK 0x1
6981 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB 0
6983 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB 0
6985 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_WIDTH 1
6987 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET_MSK 0x00000001
6989 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_CLR_MSK 0xfffffffe
6991 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET 0x1
6993 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0)
6995 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET(value) (((value) << 0) & 0x00000001)
7006 #define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_LSB 1
7008 #define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_MSB 31
7010 #define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_WIDTH 31
7012 #define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_SET_MSK 0xfffffffe
7014 #define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_CLR_MSK 0x00000001
7016 #define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_RESET 0x0
7018 #define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_GET(value) (((value) & 0xfffffffe) >> 1)
7020 #define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_SET(value) (((value) << 1) & 0xfffffffe)
7022 #ifndef __ASSEMBLY__
7033 struct ALT_I2C_ACK_GENERAL_CALL_s
7035 uint32_t ack_gen_call : 1;
7036 const uint32_t rsvd_ic_ack_gen_31to1 : 31;
7040 typedef volatile struct ALT_I2C_ACK_GENERAL_CALL_s ALT_I2C_ACK_GENERAL_CALL_t;
7044 #define ALT_I2C_ACK_GENERAL_CALL_RESET 0x00000001
7046 #define ALT_I2C_ACK_GENERAL_CALL_OFST 0x98
7048 #define ALT_I2C_ACK_GENERAL_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_ACK_GENERAL_CALL_OFST))
7124 #define ALT_I2C_EN_STAT_IC_EN_LSB 0
7126 #define ALT_I2C_EN_STAT_IC_EN_MSB 0
7128 #define ALT_I2C_EN_STAT_IC_EN_WIDTH 1
7130 #define ALT_I2C_EN_STAT_IC_EN_SET_MSK 0x00000001
7132 #define ALT_I2C_EN_STAT_IC_EN_CLR_MSK 0xfffffffe
7134 #define ALT_I2C_EN_STAT_IC_EN_RESET 0x0
7136 #define ALT_I2C_EN_STAT_IC_EN_GET(value) (((value) & 0x00000001) >> 0)
7138 #define ALT_I2C_EN_STAT_IC_EN_SET(value) (((value) << 0) & 0x00000001)
7195 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_LSB 1
7197 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_MSB 1
7199 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_WIDTH 1
7201 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET_MSK 0x00000002
7203 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_CLR_MSK 0xfffffffd
7205 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_RESET 0x0
7207 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_GET(value) (((value) & 0x00000002) >> 1)
7209 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET(value) (((value) << 1) & 0x00000002)
7252 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_LSB 2
7254 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_MSB 2
7256 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_WIDTH 1
7258 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET_MSK 0x00000004
7260 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_CLR_MSK 0xfffffffb
7262 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_RESET 0x0
7264 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_GET(value) (((value) & 0x00000004) >> 2)
7266 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET(value) (((value) << 2) & 0x00000004)
7268 #ifndef __ASSEMBLY__
7279 struct ALT_I2C_EN_STAT_s
7281 const uint32_t ic_en : 1;
7282 const uint32_t slv_disabled_while_busy : 1;
7283 const uint32_t slv_rx_data_lost : 1;
7288 typedef volatile struct ALT_I2C_EN_STAT_s ALT_I2C_EN_STAT_t;
7292 #define ALT_I2C_EN_STAT_RESET 0x00000000
7294 #define ALT_I2C_EN_STAT_OFST 0x9c
7296 #define ALT_I2C_EN_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_STAT_OFST))
7357 #define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_LSB 0
7359 #define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_MSB 7
7361 #define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_WIDTH 8
7363 #define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_SET_MSK 0x000000ff
7365 #define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_CLR_MSK 0xffffff00
7367 #define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_RESET 0x2
7369 #define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_GET(value) (((value) & 0x000000ff) >> 0)
7371 #define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_SET(value) (((value) << 0) & 0x000000ff)
7373 #ifndef __ASSEMBLY__
7384 struct ALT_I2C_FS_SPKLEN_s
7386 uint32_t ic_fs_spklen : 8;
7391 typedef volatile struct ALT_I2C_FS_SPKLEN_s ALT_I2C_FS_SPKLEN_t;
7395 #define ALT_I2C_FS_SPKLEN_RESET 0x00000002
7397 #define ALT_I2C_FS_SPKLEN_OFST 0xa0
7399 #define ALT_I2C_FS_SPKLEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SPKLEN_OFST))
7433 #define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_LSB 0
7435 #define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_MSB 0
7437 #define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_WIDTH 1
7439 #define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_SET_MSK 0x00000001
7441 #define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_CLR_MSK 0xfffffffe
7443 #define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_RESET 0x0
7445 #define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_GET(value) (((value) & 0x00000001) >> 0)
7447 #define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_SET(value) (((value) << 0) & 0x00000001)
7449 #ifndef __ASSEMBLY__
7460 struct ALT_I2C_CLR_RESTART_DET_s
7462 const uint32_t clr_restart_det : 1;
7467 typedef volatile struct ALT_I2C_CLR_RESTART_DET_s ALT_I2C_CLR_RESTART_DET_t;
7471 #define ALT_I2C_CLR_RESTART_DET_RESET 0x00000000
7473 #define ALT_I2C_CLR_RESTART_DET_OFST 0xa8
7475 #define ALT_I2C_CLR_RESTART_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RESTART_DET_OFST))
7542 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2
7545 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_LSB 0
7547 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_MSB 1
7549 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_WIDTH 2
7551 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET_MSK 0x00000003
7553 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc
7555 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_RESET 0x2
7557 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0)
7559 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003)
7592 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST 0x2
7595 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_LSB 2
7597 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_MSB 3
7599 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_WIDTH 2
7601 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET_MSK 0x0000000c
7603 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_CLR_MSK 0xfffffff3
7605 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_RESET 0x2
7607 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_GET(value) (((value) & 0x0000000c) >> 2)
7609 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET(value) (((value) << 2) & 0x0000000c)
7638 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR 0x0
7641 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_LSB 4
7643 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_MSB 4
7645 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_WIDTH 1
7647 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET_MSK 0x00000010
7649 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_CLR_MSK 0xffffffef
7651 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_RESET 0x0
7653 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_GET(value) (((value) & 0x00000010) >> 4)
7655 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET(value) (((value) << 4) & 0x00000010)
7684 #define ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED 0x1
7687 #define ALT_I2C_COMP_PARAM_1_INTR_IO_LSB 5
7689 #define ALT_I2C_COMP_PARAM_1_INTR_IO_MSB 5
7691 #define ALT_I2C_COMP_PARAM_1_INTR_IO_WIDTH 1
7693 #define ALT_I2C_COMP_PARAM_1_INTR_IO_SET_MSK 0x00000020
7695 #define ALT_I2C_COMP_PARAM_1_INTR_IO_CLR_MSK 0xffffffdf
7697 #define ALT_I2C_COMP_PARAM_1_INTR_IO_RESET 0x1
7699 #define ALT_I2C_COMP_PARAM_1_INTR_IO_GET(value) (((value) & 0x00000020) >> 5)
7701 #define ALT_I2C_COMP_PARAM_1_INTR_IO_SET(value) (((value) << 5) & 0x00000020)
7730 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT 0x1
7733 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_LSB 6
7735 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_MSB 6
7737 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_WIDTH 1
7739 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET_MSK 0x00000040
7741 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_CLR_MSK 0xffffffbf
7743 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_RESET 0x1
7745 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_GET(value) (((value) & 0x00000040) >> 6)
7747 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET(value) (((value) << 6) & 0x00000040)
7786 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1
7789 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_LSB 7
7791 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_MSB 7
7793 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_WIDTH 1
7795 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET_MSK 0x00000080
7797 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_CLR_MSK 0xffffff7f
7799 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_RESET 0x1
7801 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00000080) >> 7)
7803 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET(value) (((value) << 7) & 0x00000080)
7838 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES 0x40
7841 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_LSB 8
7843 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_MSB 15
7845 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_WIDTH 8
7847 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET_MSK 0x0000ff00
7849 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_CLR_MSK 0xffff00ff
7851 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_RESET 0x3f
7853 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_GET(value) (((value) & 0x0000ff00) >> 8)
7855 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET(value) (((value) << 8) & 0x0000ff00)
7890 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES 0x40
7893 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_LSB 16
7895 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_MSB 23
7897 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_WIDTH 8
7899 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET_MSK 0x00ff0000
7901 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_CLR_MSK 0xff00ffff
7903 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_RESET 0x3f
7905 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_GET(value) (((value) & 0x00ff0000) >> 16)
7907 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET(value) (((value) << 16) & 0x00ff0000)
7909 #ifndef __ASSEMBLY__
7920 struct ALT_I2C_COMP_PARAM_1_s
7922 const uint32_t apb_data_width : 2;
7923 const uint32_t max_speed_mode : 2;
7924 const uint32_t hc_count_values : 1;
7925 const uint32_t intr_io : 1;
7926 const uint32_t has_dma : 1;
7927 const uint32_t add_encoded_params : 1;
7928 const uint32_t rx_buffer_depth : 8;
7929 const uint32_t tx_buffer_depth : 8;
7934 typedef volatile struct ALT_I2C_COMP_PARAM_1_s ALT_I2C_COMP_PARAM_1_t;
7938 #define ALT_I2C_COMP_PARAM_1_RESET 0x003f3fea
7940 #define ALT_I2C_COMP_PARAM_1_OFST 0xf4
7942 #define ALT_I2C_COMP_PARAM_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_PARAM_1_OFST))
7985 #define ALT_I2C_COMP_VER_IC_COMP_VER_E_VER_1_21A 0x3132312a
7988 #define ALT_I2C_COMP_VER_IC_COMP_VER_LSB 0
7990 #define ALT_I2C_COMP_VER_IC_COMP_VER_MSB 31
7992 #define ALT_I2C_COMP_VER_IC_COMP_VER_WIDTH 32
7994 #define ALT_I2C_COMP_VER_IC_COMP_VER_SET_MSK 0xffffffff
7996 #define ALT_I2C_COMP_VER_IC_COMP_VER_CLR_MSK 0x00000000
7998 #define ALT_I2C_COMP_VER_IC_COMP_VER_RESET 0x3132312a
8000 #define ALT_I2C_COMP_VER_IC_COMP_VER_GET(value) (((value) & 0xffffffff) >> 0)
8002 #define ALT_I2C_COMP_VER_IC_COMP_VER_SET(value) (((value) << 0) & 0xffffffff)
8004 #ifndef __ASSEMBLY__
8015 struct ALT_I2C_COMP_VER_s
8017 const uint32_t ic_comp_version : 32;
8021 typedef volatile struct ALT_I2C_COMP_VER_s ALT_I2C_COMP_VER_t;
8025 #define ALT_I2C_COMP_VER_RESET 0x3132312a
8027 #define ALT_I2C_COMP_VER_OFST 0xf8
8029 #define ALT_I2C_COMP_VER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_VER_OFST))
8066 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_LSB 0
8068 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_MSB 31
8070 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_WIDTH 32
8072 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET_MSK 0xffffffff
8074 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_CLR_MSK 0x00000000
8076 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_RESET 0x44570140
8078 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_GET(value) (((value) & 0xffffffff) >> 0)
8080 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET(value) (((value) << 0) & 0xffffffff)
8082 #ifndef __ASSEMBLY__
8093 struct ALT_I2C_COMP_TYPE_s
8095 const uint32_t ic_comp_type : 32;
8099 typedef volatile struct ALT_I2C_COMP_TYPE_s ALT_I2C_COMP_TYPE_t;
8103 #define ALT_I2C_COMP_TYPE_RESET 0x44570140
8105 #define ALT_I2C_COMP_TYPE_OFST 0xfc
8107 #define ALT_I2C_COMP_TYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_TYPE_OFST))
8109 #ifndef __ASSEMBLY__
8122 ALT_I2C_CON_t ic_con;
8123 ALT_I2C_TAR_t ic_tar;
8124 ALT_I2C_SAR_t ic_sar;
8125 volatile uint32_t _pad_0xc_0xf;
8126 ALT_I2C_DATA_CMD_t ic_data_cmd;
8127 ALT_I2C_SS_SCL_HCNT_t ic_ss_scl_hcnt;
8128 ALT_I2C_SS_SCL_LCNT_t ic_ss_scl_lcnt;
8129 ALT_I2C_FS_SCL_HCNT_t ic_fs_scl_hcnt;
8130 ALT_I2C_FS_SCL_LCNT_t ic_fs_scl_lcnt;
8131 volatile uint32_t _pad_0x24_0x2b[2];
8132 ALT_I2C_INTR_STAT_t ic_intr_stat;
8133 ALT_I2C_INTR_MSK_t ic_intr_mask;
8134 ALT_I2C_RAW_INTR_STAT_t ic_raw_intr_stat;
8135 ALT_I2C_RX_TL_t ic_rx_tl;
8136 ALT_I2C_TX_TL_t ic_tx_tl;
8137 ALT_I2C_CLR_INTR_t ic_clr_intr;
8138 ALT_I2C_CLR_RX_UNDER_t ic_clr_rx_under;
8139 ALT_I2C_CLR_RX_OVER_t ic_clr_rx_over;
8140 ALT_I2C_CLR_TX_OVER_t ic_clr_tx_over;
8141 ALT_I2C_CLR_RD_REQ_t ic_clr_rd_req;
8142 ALT_I2C_CLR_TX_ABRT_t ic_clr_tx_abrt;
8143 ALT_I2C_CLR_RX_DONE_t ic_clr_rx_done;
8144 ALT_I2C_CLR_ACTIVITY_t ic_clr_activity;
8145 ALT_I2C_CLR_STOP_DET_t ic_clr_stop_det;
8146 ALT_I2C_CLR_START_DET_t ic_clr_start_det;
8147 ALT_I2C_CLR_GEN_CALL_t ic_clr_gen_call;
8148 ALT_I2C_EN_t ic_enable;
8149 ALT_I2C_STAT_t ic_status;
8150 ALT_I2C_TXFLR_t ic_txflr;
8151 ALT_I2C_RXFLR_t ic_rxflr;
8152 ALT_I2C_SDA_HOLD_t ic_sda_hold;
8153 ALT_I2C_TX_ABRT_SRC_t ic_tx_abrt_source;
8154 ALT_I2C_SLV_DATA_NACK_ONLY_t ic_slv_data_nack_only;
8155 ALT_I2C_DMA_CR_t ic_dma_cr;
8156 ALT_I2C_DMA_TDLR_t ic_dma_tdlr;
8157 ALT_I2C_DMA_RDLR_t ic_dma_rdlr;
8158 ALT_I2C_SDA_SETUP_t ic_sda_setup;
8159 ALT_I2C_ACK_GENERAL_CALL_t ic_ack_general_call;
8160 ALT_I2C_EN_STAT_t ic_enable_status;
8161 ALT_I2C_FS_SPKLEN_t ic_fs_spklen;
8162 volatile uint32_t _pad_0xa4_0xa7;
8163 ALT_I2C_CLR_RESTART_DET_t ic_clr_restart_det;
8164 volatile uint32_t _pad_0xac_0xf3[18];
8165 ALT_I2C_COMP_PARAM_1_t ic_comp_param_1;
8166 ALT_I2C_COMP_VER_t ic_comp_version;
8167 ALT_I2C_COMP_TYPE_t ic_comp_type;
8171 typedef volatile struct ALT_I2C_s ALT_I2C_t;
8173 struct ALT_I2C_raw_s
8175 volatile uint32_t ic_con;
8176 volatile uint32_t ic_tar;
8177 volatile uint32_t ic_sar;
8178 uint32_t _pad_0xc_0xf;
8179 volatile uint32_t ic_data_cmd;
8180 volatile uint32_t ic_ss_scl_hcnt;
8181 volatile uint32_t ic_ss_scl_lcnt;
8182 volatile uint32_t ic_fs_scl_hcnt;
8183 volatile uint32_t ic_fs_scl_lcnt;
8184 uint32_t _pad_0x24_0x2b[2];
8185 volatile uint32_t ic_intr_stat;
8186 volatile uint32_t ic_intr_mask;
8187 volatile uint32_t ic_raw_intr_stat;
8188 volatile uint32_t ic_rx_tl;
8189 volatile uint32_t ic_tx_tl;
8190 volatile uint32_t ic_clr_intr;
8191 volatile uint32_t ic_clr_rx_under;
8192 volatile uint32_t ic_clr_rx_over;
8193 volatile uint32_t ic_clr_tx_over;
8194 volatile uint32_t ic_clr_rd_req;
8195 volatile uint32_t ic_clr_tx_abrt;
8196 volatile uint32_t ic_clr_rx_done;
8197 volatile uint32_t ic_clr_activity;
8198 volatile uint32_t ic_clr_stop_det;
8199 volatile uint32_t ic_clr_start_det;
8200 volatile uint32_t ic_clr_gen_call;
8201 volatile uint32_t ic_enable;
8202 volatile uint32_t ic_status;
8203 volatile uint32_t ic_txflr;
8204 volatile uint32_t ic_rxflr;
8205 volatile uint32_t ic_sda_hold;
8206 volatile uint32_t ic_tx_abrt_source;
8207 volatile uint32_t ic_slv_data_nack_only;
8208 volatile uint32_t ic_dma_cr;
8209 volatile uint32_t ic_dma_tdlr;
8210 volatile uint32_t ic_dma_rdlr;
8211 volatile uint32_t ic_sda_setup;
8212 volatile uint32_t ic_ack_general_call;
8213 volatile uint32_t ic_enable_status;
8214 volatile uint32_t ic_fs_spklen;
8215 uint32_t _pad_0xa4_0xa7;
8216 volatile uint32_t ic_clr_restart_det;
8217 uint32_t _pad_0xac_0xf3[18];
8218 volatile uint32_t ic_comp_param_1;
8219 volatile uint32_t ic_comp_version;
8220 volatile uint32_t ic_comp_type;
8224 typedef volatile struct ALT_I2C_raw_s ALT_I2C_raw_t;