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alt_noc_mpu_m1toddrresp_main_rate.h
1 /***********************************************************************************
2 * *
3 * Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
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31 ***********************************************************************************/
32 
33 /* Altera - ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE */
34 
35 #ifndef __ALT_SOCAL_NOC_MPU_M1TODDRRESP_MAIN_RATE_H__
36 #define __ALT_SOCAL_NOC_MPU_M1TODDRRESP_MAIN_RATE_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE
50  *
51  */
52 /*
53  * Register : MPU_M1toDDRResp_main_RateAdapter_Id_CoreId
54  *
55  * Register Layout
56  *
57  * Bits | Access | Reset | Description
58  * :-------|:-------|:---------|:----------------------------------------------------------------------------
59  * [7:0] | R | 0x1 | ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID
60  * [31:8] | R | 0xc8a2b3 | ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM
61  *
62  */
63 /*
64  * Field : CORETYPEID
65  *
66  * Field identifying the type of IP.
67  *
68  * Field Access Macros:
69  *
70  */
71 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID register field. */
72 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID_LSB 0
73 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID register field. */
74 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID_MSB 7
75 /* The width in bits of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID register field. */
76 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID_WIDTH 8
77 /* The mask used to set the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID register field value. */
78 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID_SET_MSK 0x000000ff
79 /* The mask used to clear the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID register field value. */
80 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID_CLR_MSK 0xffffff00
81 /* The reset value of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID register field. */
82 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID_RESET 0x1
83 /* Extracts the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID field value from a register. */
84 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID_GET(value) (((value) & 0x000000ff) >> 0)
85 /* Produces a ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID register field value suitable for setting the register. */
86 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID_SET(value) (((value) << 0) & 0x000000ff)
87 
88 /*
89  * Field : CORECHECKSUM
90  *
91  * Field containing a checksum of the parameters of the IP.
92  *
93  * Field Access Macros:
94  *
95  */
96 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM register field. */
97 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM_LSB 8
98 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM register field. */
99 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM_MSB 31
100 /* The width in bits of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM register field. */
101 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM_WIDTH 24
102 /* The mask used to set the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM register field value. */
103 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM_SET_MSK 0xffffff00
104 /* The mask used to clear the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM register field value. */
105 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM_CLR_MSK 0x000000ff
106 /* The reset value of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM register field. */
107 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM_RESET 0xc8a2b3
108 /* Extracts the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM field value from a register. */
109 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
110 /* Produces a ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM register field value suitable for setting the register. */
111 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
112 
113 #ifndef __ASSEMBLY__
114 /*
115  * WARNING: The C register and register group struct declarations are provided for
116  * convenience and illustrative purposes. They should, however, be used with
117  * caution as the C language standard provides no guarantees about the alignment or
118  * atomicity of device memory accesses. The recommended practice for writing
119  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
120  * alt_write_word() functions.
121  *
122  * The struct declaration for register ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID.
123  */
124 struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_s
125 {
126  const uint32_t CORETYPEID : 8; /* ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_TYPEID */
127  const uint32_t CORECHECKSUM : 24; /* ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_CHECKSUM */
128 };
129 
130 /* The typedef declaration for register ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID. */
131 typedef volatile struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_s ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_t;
132 #endif /* __ASSEMBLY__ */
133 
134 /* The reset value of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID register. */
135 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_RESET 0xc8a2b301
136 /* The byte offset of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID register from the beginning of the component. */
137 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_OFST 0x0
138 
139 /*
140  * Register : MPU_M1toDDRResp_main_RateAdapter_Id_RevisionId
141  *
142  * Register Layout
143  *
144  * Bits | Access | Reset | Description
145  * :-------|:-------|:--------|:----------------------------------------------------------------------------
146  * [7:0] | R | 0x0 | ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID
147  * [31:8] | R | 0x129ff | ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID
148  *
149  */
150 /*
151  * Field : USERID
152  *
153  * Field containing a user defined value, not used anywhere inside the IP itself.
154  *
155  * Field Access Macros:
156  *
157  */
158 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID register field. */
159 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID_LSB 0
160 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID register field. */
161 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID_MSB 7
162 /* The width in bits of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID register field. */
163 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID_WIDTH 8
164 /* The mask used to set the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID register field value. */
165 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID_SET_MSK 0x000000ff
166 /* The mask used to clear the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID register field value. */
167 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID_CLR_MSK 0xffffff00
168 /* The reset value of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID register field. */
169 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID_RESET 0x0
170 /* Extracts the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID field value from a register. */
171 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID_GET(value) (((value) & 0x000000ff) >> 0)
172 /* Produces a ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID register field value suitable for setting the register. */
173 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID_SET(value) (((value) << 0) & 0x000000ff)
174 
175 /*
176  * Field : FLEXNOCID
177  *
178  * Field containing the build revision of the software used to generate the IP HDL
179  * code.
180  *
181  * Field Access Macros:
182  *
183  */
184 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID register field. */
185 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID_LSB 8
186 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID register field. */
187 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID_MSB 31
188 /* The width in bits of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID register field. */
189 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID_WIDTH 24
190 /* The mask used to set the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID register field value. */
191 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID_SET_MSK 0xffffff00
192 /* The mask used to clear the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID register field value. */
193 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID_CLR_MSK 0x000000ff
194 /* The reset value of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID register field. */
195 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID_RESET 0x129ff
196 /* Extracts the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID field value from a register. */
197 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
198 /* Produces a ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID register field value suitable for setting the register. */
199 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
200 
201 #ifndef __ASSEMBLY__
202 /*
203  * WARNING: The C register and register group struct declarations are provided for
204  * convenience and illustrative purposes. They should, however, be used with
205  * caution as the C language standard provides no guarantees about the alignment or
206  * atomicity of device memory accesses. The recommended practice for writing
207  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
208  * alt_write_word() functions.
209  *
210  * The struct declaration for register ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID.
211  */
212 struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_s
213 {
214  const uint32_t USERID : 8; /* ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_UID */
215  const uint32_t FLEXNOCID : 24; /* ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_FLEXNOCID */
216 };
217 
218 /* The typedef declaration for register ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID. */
219 typedef volatile struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_s ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_t;
220 #endif /* __ASSEMBLY__ */
221 
222 /* The reset value of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID register. */
223 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_RESET 0x0129ff00
224 /* The byte offset of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID register from the beginning of the component. */
225 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_OFST 0x4
226 
227 /*
228  * Register : MPU_M1toDDRResp_main_RateAdapter_Rate
229  *
230  *
231  * Register Layout
232  *
233  * Bits | Access | Reset | Description
234  * :--------|:-------|:--------|:----------------------------------------------------------------------
235  * [9:0] | RW | 0x0 | ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE
236  * [31:10] | ??? | Unknown | *UNDEFINED*
237  *
238  */
239 /*
240  * Field : RATE
241  *
242  * The ratio of outgoing to incoming throughput. This value determines what portion
243  * of a received packet will be stored before its head is transmitted. An optimal
244  * setting avoids transmitting bubbles, while adding no delay to packets. The ratio
245  * is expressed as 256 / (ratio - 1). For example, a 3:1 ratio of outgoing to
246  * incoming throughput would be indicated by value 0x06E. Note that throughput is
247  * the product of clock frequency x data bus width. A value of 0x000 causes the
248  * rate adapter to store a packet until either the entire packet is received or the
249  * buffer becomes full.
250  *
251  * Field Access Macros:
252  *
253  */
254 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE register field. */
255 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE_LSB 0
256 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE register field. */
257 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE_MSB 9
258 /* The width in bits of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE register field. */
259 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE_WIDTH 10
260 /* The mask used to set the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE register field value. */
261 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE_SET_MSK 0x000003ff
262 /* The mask used to clear the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE register field value. */
263 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE_CLR_MSK 0xfffffc00
264 /* The reset value of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE register field. */
265 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE_RESET 0x0
266 /* Extracts the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE field value from a register. */
267 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE_GET(value) (((value) & 0x000003ff) >> 0)
268 /* Produces a ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE register field value suitable for setting the register. */
269 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE_SET(value) (((value) << 0) & 0x000003ff)
270 
271 #ifndef __ASSEMBLY__
272 /*
273  * WARNING: The C register and register group struct declarations are provided for
274  * convenience and illustrative purposes. They should, however, be used with
275  * caution as the C language standard provides no guarantees about the alignment or
276  * atomicity of device memory accesses. The recommended practice for writing
277  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
278  * alt_write_word() functions.
279  *
280  * The struct declaration for register ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE.
281  */
282 struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_s
283 {
284  uint32_t RATE : 10; /* ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RATE */
285  uint32_t : 22; /* *UNDEFINED* */
286 };
287 
288 /* The typedef declaration for register ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE. */
289 typedef volatile struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_s ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_t;
290 #endif /* __ASSEMBLY__ */
291 
292 /* The reset value of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE register. */
293 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_RESET 0x00000000
294 /* The byte offset of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE register from the beginning of the component. */
295 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_OFST 0x8
296 
297 /*
298  * Register : MPU_M1toDDRResp_main_RateAdapter_Bypass
299  *
300  *
301  * Register Layout
302  *
303  * Bits | Access | Reset | Description
304  * :-------|:-------|:--------|:--------------------------------------------------------------------------
305  * [0] | RW | 0x0 | ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS
306  * [31:1] | ??? | Unknown | *UNDEFINED*
307  *
308  */
309 /*
310  * Field : BYPASS
311  *
312  * Disable the rate adaptation capability. This causes the rate adapter to act as a
313  * FIFO by transmitting received words, without delay, as soon as they can be
314  * transmitted. This setting is useful when the incoming throughput is equal to or
315  * greater than the downstream throughput.
316  *
317  * Field Access Macros:
318  *
319  */
320 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS register field. */
321 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS_LSB 0
322 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS register field. */
323 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS_MSB 0
324 /* The width in bits of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS register field. */
325 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS_WIDTH 1
326 /* The mask used to set the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS register field value. */
327 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS_SET_MSK 0x00000001
328 /* The mask used to clear the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS register field value. */
329 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS_CLR_MSK 0xfffffffe
330 /* The reset value of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS register field. */
331 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS_RESET 0x0
332 /* Extracts the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS field value from a register. */
333 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS_GET(value) (((value) & 0x00000001) >> 0)
334 /* Produces a ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS register field value suitable for setting the register. */
335 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS_SET(value) (((value) << 0) & 0x00000001)
336 
337 #ifndef __ASSEMBLY__
338 /*
339  * WARNING: The C register and register group struct declarations are provided for
340  * convenience and illustrative purposes. They should, however, be used with
341  * caution as the C language standard provides no guarantees about the alignment or
342  * atomicity of device memory accesses. The recommended practice for writing
343  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
344  * alt_write_word() functions.
345  *
346  * The struct declaration for register ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS.
347  */
348 struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_s
349 {
350  uint32_t BYPASS : 1; /* ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_BYPASS */
351  uint32_t : 31; /* *UNDEFINED* */
352 };
353 
354 /* The typedef declaration for register ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS. */
355 typedef volatile struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_s ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_t;
356 #endif /* __ASSEMBLY__ */
357 
358 /* The reset value of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS register. */
359 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_RESET 0x00000000
360 /* The byte offset of the ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS register from the beginning of the component. */
361 #define ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_OFST 0xc
362 
363 #ifndef __ASSEMBLY__
364 /*
365  * WARNING: The C register and register group struct declarations are provided for
366  * convenience and illustrative purposes. They should, however, be used with
367  * caution as the C language standard provides no guarantees about the alignment or
368  * atomicity of device memory accesses. The recommended practice for writing
369  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
370  * alt_write_word() functions.
371  *
372  * The struct declaration for register group ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE.
373  */
374 struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_s
375 {
376  ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID_t MPU_M1toDDRResp_main_RateAdapter_Id_CoreId; /* ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID */
377  ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID_t MPU_M1toDDRResp_main_RateAdapter_Id_RevisionId; /* ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID */
378  ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE_t MPU_M1toDDRResp_main_RateAdapter_Rate; /* ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE */
379  ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS_t MPU_M1toDDRResp_main_RateAdapter_Bypass; /* ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS */
380  volatile uint32_t _pad_0x10_0x80[28]; /* *UNDEFINED* */
381 };
382 
383 /* The typedef declaration for register group ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE. */
384 typedef volatile struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_s ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_t;
385 /* The struct declaration for the raw register contents of register group ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE. */
386 struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_raw_s
387 {
388  volatile uint32_t MPU_M1toDDRResp_main_RateAdapter_Id_CoreId; /* ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_COREID */
389  volatile uint32_t MPU_M1toDDRResp_main_RateAdapter_Id_RevisionId; /* ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_REVID */
390  volatile uint32_t MPU_M1toDDRResp_main_RateAdapter_Rate; /* ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_RATE */
391  volatile uint32_t MPU_M1toDDRResp_main_RateAdapter_Bypass; /* ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_MPU_M1TODDRRESP_MAIN_RATE_BYPASS */
392  uint32_t _pad_0x10_0x80[28]; /* *UNDEFINED* */
393 };
394 
395 /* The typedef declaration for the raw register contents of register group ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE. */
396 typedef volatile struct ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_raw_s ALT_NOC_MPU_M1TODDRRESP_MAIN_RATE_raw_t;
397 #endif /* __ASSEMBLY__ */
398 
399 
400 #ifdef __cplusplus
401 }
402 #endif /* __cplusplus */
403 #endif /* __ALT_SOCAL_NOC_MPU_M1TODDRRESP_MAIN_RATE_H__ */
404