35 #ifndef __ALT_SOCAL_ECC_QSPI_H__
36 #define __ALT_SOCAL_ECC_QSPI_H__
74 #define ALT_ECC_QSPI_IP_REV_ID_SIREV_LSB 0
76 #define ALT_ECC_QSPI_IP_REV_ID_SIREV_MSB 15
78 #define ALT_ECC_QSPI_IP_REV_ID_SIREV_WIDTH 16
80 #define ALT_ECC_QSPI_IP_REV_ID_SIREV_SET_MSK 0x0000ffff
82 #define ALT_ECC_QSPI_IP_REV_ID_SIREV_CLR_MSK 0xffff0000
84 #define ALT_ECC_QSPI_IP_REV_ID_SIREV_RESET 0x0
86 #define ALT_ECC_QSPI_IP_REV_ID_SIREV_GET(value) (((value) & 0x0000ffff) >> 0)
88 #define ALT_ECC_QSPI_IP_REV_ID_SIREV_SET(value) (((value) << 0) & 0x0000ffff)
101 struct ALT_ECC_QSPI_IP_REV_ID_s
103 const uint32_t SIREV : 16;
108 typedef volatile struct ALT_ECC_QSPI_IP_REV_ID_s ALT_ECC_QSPI_IP_REV_ID_t;
112 #define ALT_ECC_QSPI_IP_REV_ID_RESET 0x00000000
114 #define ALT_ECC_QSPI_IP_REV_ID_OFST 0x0
142 #define ALT_ECC_QSPI_CTL_ECC_EN_LSB 0
144 #define ALT_ECC_QSPI_CTL_ECC_EN_MSB 0
146 #define ALT_ECC_QSPI_CTL_ECC_EN_WIDTH 1
148 #define ALT_ECC_QSPI_CTL_ECC_EN_SET_MSK 0x00000001
150 #define ALT_ECC_QSPI_CTL_ECC_EN_CLR_MSK 0xfffffffe
152 #define ALT_ECC_QSPI_CTL_ECC_EN_RESET 0x0
154 #define ALT_ECC_QSPI_CTL_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
156 #define ALT_ECC_QSPI_CTL_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
167 #define ALT_ECC_QSPI_CTL_CNT_RSTA_LSB 8
169 #define ALT_ECC_QSPI_CTL_CNT_RSTA_MSB 8
171 #define ALT_ECC_QSPI_CTL_CNT_RSTA_WIDTH 1
173 #define ALT_ECC_QSPI_CTL_CNT_RSTA_SET_MSK 0x00000100
175 #define ALT_ECC_QSPI_CTL_CNT_RSTA_CLR_MSK 0xfffffeff
177 #define ALT_ECC_QSPI_CTL_CNT_RSTA_RESET 0x0
179 #define ALT_ECC_QSPI_CTL_CNT_RSTA_GET(value) (((value) & 0x00000100) >> 8)
181 #define ALT_ECC_QSPI_CTL_CNT_RSTA_SET(value) (((value) << 8) & 0x00000100)
192 #define ALT_ECC_QSPI_CTL_INITA_LSB 16
194 #define ALT_ECC_QSPI_CTL_INITA_MSB 16
196 #define ALT_ECC_QSPI_CTL_INITA_WIDTH 1
198 #define ALT_ECC_QSPI_CTL_INITA_SET_MSK 0x00010000
200 #define ALT_ECC_QSPI_CTL_INITA_CLR_MSK 0xfffeffff
202 #define ALT_ECC_QSPI_CTL_INITA_RESET 0x0
204 #define ALT_ECC_QSPI_CTL_INITA_GET(value) (((value) & 0x00010000) >> 16)
206 #define ALT_ECC_QSPI_CTL_INITA_SET(value) (((value) << 16) & 0x00010000)
219 struct ALT_ECC_QSPI_CTL_s
223 uint32_t CNT_RSTA : 1;
230 typedef volatile struct ALT_ECC_QSPI_CTL_s ALT_ECC_QSPI_CTL_t;
234 #define ALT_ECC_QSPI_CTL_RESET 0x00000000
236 #define ALT_ECC_QSPI_CTL_OFST 0x8
261 #define ALT_ECC_QSPI_INITSTAT_INITCOMPLETEA_LSB 0
263 #define ALT_ECC_QSPI_INITSTAT_INITCOMPLETEA_MSB 0
265 #define ALT_ECC_QSPI_INITSTAT_INITCOMPLETEA_WIDTH 1
267 #define ALT_ECC_QSPI_INITSTAT_INITCOMPLETEA_SET_MSK 0x00000001
269 #define ALT_ECC_QSPI_INITSTAT_INITCOMPLETEA_CLR_MSK 0xfffffffe
271 #define ALT_ECC_QSPI_INITSTAT_INITCOMPLETEA_RESET 0x0
273 #define ALT_ECC_QSPI_INITSTAT_INITCOMPLETEA_GET(value) (((value) & 0x00000001) >> 0)
275 #define ALT_ECC_QSPI_INITSTAT_INITCOMPLETEA_SET(value) (((value) << 0) & 0x00000001)
288 struct ALT_ECC_QSPI_INITSTAT_s
290 uint32_t INITCOMPLETEA : 1;
295 typedef volatile struct ALT_ECC_QSPI_INITSTAT_s ALT_ECC_QSPI_INITSTAT_t;
299 #define ALT_ECC_QSPI_INITSTAT_RESET 0x00000000
301 #define ALT_ECC_QSPI_INITSTAT_OFST 0xc
325 #define ALT_ECC_QSPI_ERRINTEN_SERRINTEN_LSB 0
327 #define ALT_ECC_QSPI_ERRINTEN_SERRINTEN_MSB 0
329 #define ALT_ECC_QSPI_ERRINTEN_SERRINTEN_WIDTH 1
331 #define ALT_ECC_QSPI_ERRINTEN_SERRINTEN_SET_MSK 0x00000001
333 #define ALT_ECC_QSPI_ERRINTEN_SERRINTEN_CLR_MSK 0xfffffffe
335 #define ALT_ECC_QSPI_ERRINTEN_SERRINTEN_RESET 0x0
337 #define ALT_ECC_QSPI_ERRINTEN_SERRINTEN_GET(value) (((value) & 0x00000001) >> 0)
339 #define ALT_ECC_QSPI_ERRINTEN_SERRINTEN_SET(value) (((value) << 0) & 0x00000001)
352 struct ALT_ECC_QSPI_ERRINTEN_s
354 uint32_t SERRINTEN : 1;
359 typedef volatile struct ALT_ECC_QSPI_ERRINTEN_s ALT_ECC_QSPI_ERRINTEN_t;
363 #define ALT_ECC_QSPI_ERRINTEN_RESET 0x00000000
365 #define ALT_ECC_QSPI_ERRINTEN_OFST 0x10
389 #define ALT_ECC_QSPI_ERRINTENS_SERRINTS_LSB 0
391 #define ALT_ECC_QSPI_ERRINTENS_SERRINTS_MSB 0
393 #define ALT_ECC_QSPI_ERRINTENS_SERRINTS_WIDTH 1
395 #define ALT_ECC_QSPI_ERRINTENS_SERRINTS_SET_MSK 0x00000001
397 #define ALT_ECC_QSPI_ERRINTENS_SERRINTS_CLR_MSK 0xfffffffe
399 #define ALT_ECC_QSPI_ERRINTENS_SERRINTS_RESET 0x0
401 #define ALT_ECC_QSPI_ERRINTENS_SERRINTS_GET(value) (((value) & 0x00000001) >> 0)
403 #define ALT_ECC_QSPI_ERRINTENS_SERRINTS_SET(value) (((value) << 0) & 0x00000001)
416 struct ALT_ECC_QSPI_ERRINTENS_s
418 uint32_t SERRINTS : 1;
423 typedef volatile struct ALT_ECC_QSPI_ERRINTENS_s ALT_ECC_QSPI_ERRINTENS_t;
427 #define ALT_ECC_QSPI_ERRINTENS_RESET 0x00000000
429 #define ALT_ECC_QSPI_ERRINTENS_OFST 0x14
460 #define ALT_ECC_QSPI_ERRINTENR_SERRINTR_LSB 0
462 #define ALT_ECC_QSPI_ERRINTENR_SERRINTR_MSB 0
464 #define ALT_ECC_QSPI_ERRINTENR_SERRINTR_WIDTH 1
466 #define ALT_ECC_QSPI_ERRINTENR_SERRINTR_SET_MSK 0x00000001
468 #define ALT_ECC_QSPI_ERRINTENR_SERRINTR_CLR_MSK 0xfffffffe
470 #define ALT_ECC_QSPI_ERRINTENR_SERRINTR_RESET 0x0
472 #define ALT_ECC_QSPI_ERRINTENR_SERRINTR_GET(value) (((value) & 0x00000001) >> 0)
474 #define ALT_ECC_QSPI_ERRINTENR_SERRINTR_SET(value) (((value) << 0) & 0x00000001)
487 struct ALT_ECC_QSPI_ERRINTENR_s
489 uint32_t SERRINTR : 1;
494 typedef volatile struct ALT_ECC_QSPI_ERRINTENR_s ALT_ECC_QSPI_ERRINTENR_t;
498 #define ALT_ECC_QSPI_ERRINTENR_RESET 0x00000000
500 #define ALT_ECC_QSPI_ERRINTENR_OFST 0x18
528 #define ALT_ECC_QSPI_INTMOD_INTMOD_LSB 0
530 #define ALT_ECC_QSPI_INTMOD_INTMOD_MSB 0
532 #define ALT_ECC_QSPI_INTMOD_INTMOD_WIDTH 1
534 #define ALT_ECC_QSPI_INTMOD_INTMOD_SET_MSK 0x00000001
536 #define ALT_ECC_QSPI_INTMOD_INTMOD_CLR_MSK 0xfffffffe
538 #define ALT_ECC_QSPI_INTMOD_INTMOD_RESET 0x0
540 #define ALT_ECC_QSPI_INTMOD_INTMOD_GET(value) (((value) & 0x00000001) >> 0)
542 #define ALT_ECC_QSPI_INTMOD_INTMOD_SET(value) (((value) << 0) & 0x00000001)
553 #define ALT_ECC_QSPI_INTMOD_INTONOVF_LSB 8
555 #define ALT_ECC_QSPI_INTMOD_INTONOVF_MSB 8
557 #define ALT_ECC_QSPI_INTMOD_INTONOVF_WIDTH 1
559 #define ALT_ECC_QSPI_INTMOD_INTONOVF_SET_MSK 0x00000100
561 #define ALT_ECC_QSPI_INTMOD_INTONOVF_CLR_MSK 0xfffffeff
563 #define ALT_ECC_QSPI_INTMOD_INTONOVF_RESET 0x0
565 #define ALT_ECC_QSPI_INTMOD_INTONOVF_GET(value) (((value) & 0x00000100) >> 8)
567 #define ALT_ECC_QSPI_INTMOD_INTONOVF_SET(value) (((value) << 8) & 0x00000100)
578 #define ALT_ECC_QSPI_INTMOD_INTONCMP_LSB 16
580 #define ALT_ECC_QSPI_INTMOD_INTONCMP_MSB 16
582 #define ALT_ECC_QSPI_INTMOD_INTONCMP_WIDTH 1
584 #define ALT_ECC_QSPI_INTMOD_INTONCMP_SET_MSK 0x00010000
586 #define ALT_ECC_QSPI_INTMOD_INTONCMP_CLR_MSK 0xfffeffff
588 #define ALT_ECC_QSPI_INTMOD_INTONCMP_RESET 0x0
590 #define ALT_ECC_QSPI_INTMOD_INTONCMP_GET(value) (((value) & 0x00010000) >> 16)
592 #define ALT_ECC_QSPI_INTMOD_INTONCMP_SET(value) (((value) << 16) & 0x00010000)
605 struct ALT_ECC_QSPI_INTMOD_s
607 uint32_t INTMODE : 1;
609 uint32_t INTONOVF : 1;
611 uint32_t INTONCMP : 1;
616 typedef volatile struct ALT_ECC_QSPI_INTMOD_s ALT_ECC_QSPI_INTMOD_t;
620 #define ALT_ECC_QSPI_INTMOD_RESET 0x00000000
622 #define ALT_ECC_QSPI_INTMOD_OFST 0x1c
650 #define ALT_ECC_QSPI_INTSTAT_SERRPENA_LSB 0
652 #define ALT_ECC_QSPI_INTSTAT_SERRPENA_MSB 0
654 #define ALT_ECC_QSPI_INTSTAT_SERRPENA_WIDTH 1
656 #define ALT_ECC_QSPI_INTSTAT_SERRPENA_SET_MSK 0x00000001
658 #define ALT_ECC_QSPI_INTSTAT_SERRPENA_CLR_MSK 0xfffffffe
660 #define ALT_ECC_QSPI_INTSTAT_SERRPENA_RESET 0x0
662 #define ALT_ECC_QSPI_INTSTAT_SERRPENA_GET(value) (((value) & 0x00000001) >> 0)
664 #define ALT_ECC_QSPI_INTSTAT_SERRPENA_SET(value) (((value) << 0) & 0x00000001)
675 #define ALT_ECC_QSPI_INTSTAT_DERRPENA_LSB 8
677 #define ALT_ECC_QSPI_INTSTAT_DERRPENA_MSB 8
679 #define ALT_ECC_QSPI_INTSTAT_DERRPENA_WIDTH 1
681 #define ALT_ECC_QSPI_INTSTAT_DERRPENA_SET_MSK 0x00000100
683 #define ALT_ECC_QSPI_INTSTAT_DERRPENA_CLR_MSK 0xfffffeff
685 #define ALT_ECC_QSPI_INTSTAT_DERRPENA_RESET 0x0
687 #define ALT_ECC_QSPI_INTSTAT_DERRPENA_GET(value) (((value) & 0x00000100) >> 8)
689 #define ALT_ECC_QSPI_INTSTAT_DERRPENA_SET(value) (((value) << 8) & 0x00000100)
702 struct ALT_ECC_QSPI_INTSTAT_s
704 uint32_t SERRPENA : 1;
706 uint32_t DERRPENA : 1;
711 typedef volatile struct ALT_ECC_QSPI_INTSTAT_s ALT_ECC_QSPI_INTSTAT_t;
715 #define ALT_ECC_QSPI_INTSTAT_RESET 0x00000000
717 #define ALT_ECC_QSPI_INTSTAT_OFST 0x20
743 #define ALT_ECC_QSPI_INTTEST_TSERRA_LSB 0
745 #define ALT_ECC_QSPI_INTTEST_TSERRA_MSB 0
747 #define ALT_ECC_QSPI_INTTEST_TSERRA_WIDTH 1
749 #define ALT_ECC_QSPI_INTTEST_TSERRA_SET_MSK 0x00000001
751 #define ALT_ECC_QSPI_INTTEST_TSERRA_CLR_MSK 0xfffffffe
753 #define ALT_ECC_QSPI_INTTEST_TSERRA_RESET 0x0
755 #define ALT_ECC_QSPI_INTTEST_TSERRA_GET(value) (((value) & 0x00000001) >> 0)
757 #define ALT_ECC_QSPI_INTTEST_TSERRA_SET(value) (((value) << 0) & 0x00000001)
768 #define ALT_ECC_QSPI_INTTEST_TDERRA_LSB 8
770 #define ALT_ECC_QSPI_INTTEST_TDERRA_MSB 8
772 #define ALT_ECC_QSPI_INTTEST_TDERRA_WIDTH 1
774 #define ALT_ECC_QSPI_INTTEST_TDERRA_SET_MSK 0x00000100
776 #define ALT_ECC_QSPI_INTTEST_TDERRA_CLR_MSK 0xfffffeff
778 #define ALT_ECC_QSPI_INTTEST_TDERRA_RESET 0x0
780 #define ALT_ECC_QSPI_INTTEST_TDERRA_GET(value) (((value) & 0x00000100) >> 8)
782 #define ALT_ECC_QSPI_INTTEST_TDERRA_SET(value) (((value) << 8) & 0x00000100)
795 struct ALT_ECC_QSPI_INTTEST_s
804 typedef volatile struct ALT_ECC_QSPI_INTTEST_s ALT_ECC_QSPI_INTTEST_t;
808 #define ALT_ECC_QSPI_INTTEST_RESET 0x00000000
810 #define ALT_ECC_QSPI_INTTEST_OFST 0x24
834 #define ALT_ECC_QSPI_MODSTAT_CMPFLGA_LSB 0
836 #define ALT_ECC_QSPI_MODSTAT_CMPFLGA_MSB 0
838 #define ALT_ECC_QSPI_MODSTAT_CMPFLGA_WIDTH 1
840 #define ALT_ECC_QSPI_MODSTAT_CMPFLGA_SET_MSK 0x00000001
842 #define ALT_ECC_QSPI_MODSTAT_CMPFLGA_CLR_MSK 0xfffffffe
844 #define ALT_ECC_QSPI_MODSTAT_CMPFLGA_RESET 0x0
846 #define ALT_ECC_QSPI_MODSTAT_CMPFLGA_GET(value) (((value) & 0x00000001) >> 0)
848 #define ALT_ECC_QSPI_MODSTAT_CMPFLGA_SET(value) (((value) << 0) & 0x00000001)
861 struct ALT_ECC_QSPI_MODSTAT_s
863 uint32_t CMPFLGA : 1;
868 typedef volatile struct ALT_ECC_QSPI_MODSTAT_s ALT_ECC_QSPI_MODSTAT_t;
872 #define ALT_ECC_QSPI_MODSTAT_RESET 0x00000000
874 #define ALT_ECC_QSPI_MODSTAT_OFST 0x28
899 #define ALT_ECC_QSPI_DERRADDRA_ADDR_LSB 0
901 #define ALT_ECC_QSPI_DERRADDRA_ADDR_MSB 6
903 #define ALT_ECC_QSPI_DERRADDRA_ADDR_WIDTH 7
905 #define ALT_ECC_QSPI_DERRADDRA_ADDR_SET_MSK 0x0000007f
907 #define ALT_ECC_QSPI_DERRADDRA_ADDR_CLR_MSK 0xffffff80
909 #define ALT_ECC_QSPI_DERRADDRA_ADDR_RESET 0x0
911 #define ALT_ECC_QSPI_DERRADDRA_ADDR_GET(value) (((value) & 0x0000007f) >> 0)
913 #define ALT_ECC_QSPI_DERRADDRA_ADDR_SET(value) (((value) << 0) & 0x0000007f)
926 struct ALT_ECC_QSPI_DERRADDRA_s
928 uint32_t Address : 7;
933 typedef volatile struct ALT_ECC_QSPI_DERRADDRA_s ALT_ECC_QSPI_DERRADDRA_t;
937 #define ALT_ECC_QSPI_DERRADDRA_RESET 0x00000000
939 #define ALT_ECC_QSPI_DERRADDRA_OFST 0x2c
964 #define ALT_ECC_QSPI_SERRADDRA_ADDR_LSB 0
966 #define ALT_ECC_QSPI_SERRADDRA_ADDR_MSB 6
968 #define ALT_ECC_QSPI_SERRADDRA_ADDR_WIDTH 7
970 #define ALT_ECC_QSPI_SERRADDRA_ADDR_SET_MSK 0x0000007f
972 #define ALT_ECC_QSPI_SERRADDRA_ADDR_CLR_MSK 0xffffff80
974 #define ALT_ECC_QSPI_SERRADDRA_ADDR_RESET 0x0
976 #define ALT_ECC_QSPI_SERRADDRA_ADDR_GET(value) (((value) & 0x0000007f) >> 0)
978 #define ALT_ECC_QSPI_SERRADDRA_ADDR_SET(value) (((value) << 0) & 0x0000007f)
991 struct ALT_ECC_QSPI_SERRADDRA_s
993 uint32_t Address : 7;
998 typedef volatile struct ALT_ECC_QSPI_SERRADDRA_s ALT_ECC_QSPI_SERRADDRA_t;
1002 #define ALT_ECC_QSPI_SERRADDRA_RESET 0x00000000
1004 #define ALT_ECC_QSPI_SERRADDRA_OFST 0x30
1027 #define ALT_ECC_QSPI_SERRCNTREG_SERRCNT_LSB 0
1029 #define ALT_ECC_QSPI_SERRCNTREG_SERRCNT_MSB 31
1031 #define ALT_ECC_QSPI_SERRCNTREG_SERRCNT_WIDTH 32
1033 #define ALT_ECC_QSPI_SERRCNTREG_SERRCNT_SET_MSK 0xffffffff
1035 #define ALT_ECC_QSPI_SERRCNTREG_SERRCNT_CLR_MSK 0x00000000
1037 #define ALT_ECC_QSPI_SERRCNTREG_SERRCNT_RESET 0x0
1039 #define ALT_ECC_QSPI_SERRCNTREG_SERRCNT_GET(value) (((value) & 0xffffffff) >> 0)
1041 #define ALT_ECC_QSPI_SERRCNTREG_SERRCNT_SET(value) (((value) << 0) & 0xffffffff)
1043 #ifndef __ASSEMBLY__
1054 struct ALT_ECC_QSPI_SERRCNTREG_s
1056 uint32_t SERRCNT : 32;
1060 typedef volatile struct ALT_ECC_QSPI_SERRCNTREG_s ALT_ECC_QSPI_SERRCNTREG_t;
1064 #define ALT_ECC_QSPI_SERRCNTREG_RESET 0x00000000
1066 #define ALT_ECC_QSPI_SERRCNTREG_OFST 0x3c
1091 #define ALT_ECC_QSPI_ADDRBUS_ECC_ADDRBUS_LSB 0
1093 #define ALT_ECC_QSPI_ADDRBUS_ECC_ADDRBUS_MSB 6
1095 #define ALT_ECC_QSPI_ADDRBUS_ECC_ADDRBUS_WIDTH 7
1097 #define ALT_ECC_QSPI_ADDRBUS_ECC_ADDRBUS_SET_MSK 0x0000007f
1099 #define ALT_ECC_QSPI_ADDRBUS_ECC_ADDRBUS_CLR_MSK 0xffffff80
1101 #define ALT_ECC_QSPI_ADDRBUS_ECC_ADDRBUS_RESET 0x0
1103 #define ALT_ECC_QSPI_ADDRBUS_ECC_ADDRBUS_GET(value) (((value) & 0x0000007f) >> 0)
1105 #define ALT_ECC_QSPI_ADDRBUS_ECC_ADDRBUS_SET(value) (((value) << 0) & 0x0000007f)
1107 #ifndef __ASSEMBLY__
1118 struct ALT_ECC_QSPI_ADDRBUS_s
1120 uint32_t ECC_AddrBUS : 7;
1125 typedef volatile struct ALT_ECC_QSPI_ADDRBUS_s ALT_ECC_QSPI_ADDRBUS_t;
1129 #define ALT_ECC_QSPI_ADDRBUS_RESET 0x00000000
1131 #define ALT_ECC_QSPI_ADDRBUS_OFST 0x40
1133 #define ALT_ECC_QSPI_ADDRBUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_QSPI_ADDRBUS_OFST))
1156 #define ALT_ECC_QSPI_RDATA0BUS_ECC_RDATABUS_LSB 0
1158 #define ALT_ECC_QSPI_RDATA0BUS_ECC_RDATABUS_MSB 31
1160 #define ALT_ECC_QSPI_RDATA0BUS_ECC_RDATABUS_WIDTH 32
1162 #define ALT_ECC_QSPI_RDATA0BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1164 #define ALT_ECC_QSPI_RDATA0BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1166 #define ALT_ECC_QSPI_RDATA0BUS_ECC_RDATABUS_RESET 0x0
1168 #define ALT_ECC_QSPI_RDATA0BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1170 #define ALT_ECC_QSPI_RDATA0BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1172 #ifndef __ASSEMBLY__
1183 struct ALT_ECC_QSPI_RDATA0BUS_s
1185 uint32_t ECC_RDataBUS : 32;
1189 typedef volatile struct ALT_ECC_QSPI_RDATA0BUS_s ALT_ECC_QSPI_RDATA0BUS_t;
1193 #define ALT_ECC_QSPI_RDATA0BUS_RESET 0x00000000
1195 #define ALT_ECC_QSPI_RDATA0BUS_OFST 0x44
1197 #define ALT_ECC_QSPI_RDATA0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_QSPI_RDATA0BUS_OFST))
1220 #define ALT_ECC_QSPI_RDATA1BUS_ECC_RDATABUS_LSB 0
1222 #define ALT_ECC_QSPI_RDATA1BUS_ECC_RDATABUS_MSB 31
1224 #define ALT_ECC_QSPI_RDATA1BUS_ECC_RDATABUS_WIDTH 32
1226 #define ALT_ECC_QSPI_RDATA1BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1228 #define ALT_ECC_QSPI_RDATA1BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1230 #define ALT_ECC_QSPI_RDATA1BUS_ECC_RDATABUS_RESET 0x0
1232 #define ALT_ECC_QSPI_RDATA1BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1234 #define ALT_ECC_QSPI_RDATA1BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1236 #ifndef __ASSEMBLY__
1247 struct ALT_ECC_QSPI_RDATA1BUS_s
1249 uint32_t ECC_RDataBUS : 32;
1253 typedef volatile struct ALT_ECC_QSPI_RDATA1BUS_s ALT_ECC_QSPI_RDATA1BUS_t;
1257 #define ALT_ECC_QSPI_RDATA1BUS_RESET 0x00000000
1259 #define ALT_ECC_QSPI_RDATA1BUS_OFST 0x48
1261 #define ALT_ECC_QSPI_RDATA1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_QSPI_RDATA1BUS_OFST))
1284 #define ALT_ECC_QSPI_RDATA2BUS_ECC_RDATABUS_LSB 0
1286 #define ALT_ECC_QSPI_RDATA2BUS_ECC_RDATABUS_MSB 31
1288 #define ALT_ECC_QSPI_RDATA2BUS_ECC_RDATABUS_WIDTH 32
1290 #define ALT_ECC_QSPI_RDATA2BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1292 #define ALT_ECC_QSPI_RDATA2BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1294 #define ALT_ECC_QSPI_RDATA2BUS_ECC_RDATABUS_RESET 0x0
1296 #define ALT_ECC_QSPI_RDATA2BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1298 #define ALT_ECC_QSPI_RDATA2BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1300 #ifndef __ASSEMBLY__
1311 struct ALT_ECC_QSPI_RDATA2BUS_s
1313 uint32_t ECC_RDataBUS : 32;
1317 typedef volatile struct ALT_ECC_QSPI_RDATA2BUS_s ALT_ECC_QSPI_RDATA2BUS_t;
1321 #define ALT_ECC_QSPI_RDATA2BUS_RESET 0x00000000
1323 #define ALT_ECC_QSPI_RDATA2BUS_OFST 0x4c
1325 #define ALT_ECC_QSPI_RDATA2BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_QSPI_RDATA2BUS_OFST))
1348 #define ALT_ECC_QSPI_RDATA3BUS_ECC_RDATABUS_LSB 0
1350 #define ALT_ECC_QSPI_RDATA3BUS_ECC_RDATABUS_MSB 31
1352 #define ALT_ECC_QSPI_RDATA3BUS_ECC_RDATABUS_WIDTH 32
1354 #define ALT_ECC_QSPI_RDATA3BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1356 #define ALT_ECC_QSPI_RDATA3BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1358 #define ALT_ECC_QSPI_RDATA3BUS_ECC_RDATABUS_RESET 0x0
1360 #define ALT_ECC_QSPI_RDATA3BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1362 #define ALT_ECC_QSPI_RDATA3BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1364 #ifndef __ASSEMBLY__
1375 struct ALT_ECC_QSPI_RDATA3BUS_s
1377 uint32_t ECC_RDataBUS : 32;
1381 typedef volatile struct ALT_ECC_QSPI_RDATA3BUS_s ALT_ECC_QSPI_RDATA3BUS_t;
1385 #define ALT_ECC_QSPI_RDATA3BUS_RESET 0x00000000
1387 #define ALT_ECC_QSPI_RDATA3BUS_OFST 0x50
1389 #define ALT_ECC_QSPI_RDATA3BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_QSPI_RDATA3BUS_OFST))
1412 #define ALT_ECC_QSPI_WDATA0BUS_ECC_WDATABUS_LSB 0
1414 #define ALT_ECC_QSPI_WDATA0BUS_ECC_WDATABUS_MSB 31
1416 #define ALT_ECC_QSPI_WDATA0BUS_ECC_WDATABUS_WIDTH 32
1418 #define ALT_ECC_QSPI_WDATA0BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1420 #define ALT_ECC_QSPI_WDATA0BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1422 #define ALT_ECC_QSPI_WDATA0BUS_ECC_WDATABUS_RESET 0x0
1424 #define ALT_ECC_QSPI_WDATA0BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1426 #define ALT_ECC_QSPI_WDATA0BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1428 #ifndef __ASSEMBLY__
1439 struct ALT_ECC_QSPI_WDATA0BUS_s
1441 uint32_t ECC_WDataBUS : 32;
1445 typedef volatile struct ALT_ECC_QSPI_WDATA0BUS_s ALT_ECC_QSPI_WDATA0BUS_t;
1449 #define ALT_ECC_QSPI_WDATA0BUS_RESET 0x00000000
1451 #define ALT_ECC_QSPI_WDATA0BUS_OFST 0x54
1453 #define ALT_ECC_QSPI_WDATA0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_QSPI_WDATA0BUS_OFST))
1476 #define ALT_ECC_QSPI_WDATA1BUS_ECC_WDATABUS_LSB 0
1478 #define ALT_ECC_QSPI_WDATA1BUS_ECC_WDATABUS_MSB 31
1480 #define ALT_ECC_QSPI_WDATA1BUS_ECC_WDATABUS_WIDTH 32
1482 #define ALT_ECC_QSPI_WDATA1BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1484 #define ALT_ECC_QSPI_WDATA1BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1486 #define ALT_ECC_QSPI_WDATA1BUS_ECC_WDATABUS_RESET 0x0
1488 #define ALT_ECC_QSPI_WDATA1BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1490 #define ALT_ECC_QSPI_WDATA1BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1492 #ifndef __ASSEMBLY__
1503 struct ALT_ECC_QSPI_WDATA1BUS_s
1505 uint32_t ECC_WDataBUS : 32;
1509 typedef volatile struct ALT_ECC_QSPI_WDATA1BUS_s ALT_ECC_QSPI_WDATA1BUS_t;
1513 #define ALT_ECC_QSPI_WDATA1BUS_RESET 0x00000000
1515 #define ALT_ECC_QSPI_WDATA1BUS_OFST 0x58
1517 #define ALT_ECC_QSPI_WDATA1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_QSPI_WDATA1BUS_OFST))
1540 #define ALT_ECC_QSPI_WDATA2BUS_ECC_WDATABUS_LSB 0
1542 #define ALT_ECC_QSPI_WDATA2BUS_ECC_WDATABUS_MSB 31
1544 #define ALT_ECC_QSPI_WDATA2BUS_ECC_WDATABUS_WIDTH 32
1546 #define ALT_ECC_QSPI_WDATA2BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1548 #define ALT_ECC_QSPI_WDATA2BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1550 #define ALT_ECC_QSPI_WDATA2BUS_ECC_WDATABUS_RESET 0x0
1552 #define ALT_ECC_QSPI_WDATA2BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1554 #define ALT_ECC_QSPI_WDATA2BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1556 #ifndef __ASSEMBLY__
1567 struct ALT_ECC_QSPI_WDATA2BUS_s
1569 uint32_t ECC_WDataBUS : 32;
1573 typedef volatile struct ALT_ECC_QSPI_WDATA2BUS_s ALT_ECC_QSPI_WDATA2BUS_t;
1577 #define ALT_ECC_QSPI_WDATA2BUS_RESET 0x00000000
1579 #define ALT_ECC_QSPI_WDATA2BUS_OFST 0x5c
1581 #define ALT_ECC_QSPI_WDATA2BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_QSPI_WDATA2BUS_OFST))
1604 #define ALT_ECC_QSPI_WDATA3BUS_ECC_WDATABUS_LSB 0
1606 #define ALT_ECC_QSPI_WDATA3BUS_ECC_WDATABUS_MSB 31
1608 #define ALT_ECC_QSPI_WDATA3BUS_ECC_WDATABUS_WIDTH 32
1610 #define ALT_ECC_QSPI_WDATA3BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1612 #define ALT_ECC_QSPI_WDATA3BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1614 #define ALT_ECC_QSPI_WDATA3BUS_ECC_WDATABUS_RESET 0x0
1616 #define ALT_ECC_QSPI_WDATA3BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1618 #define ALT_ECC_QSPI_WDATA3BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1620 #ifndef __ASSEMBLY__
1631 struct ALT_ECC_QSPI_WDATA3BUS_s
1633 uint32_t ECC_WDataBUS : 32;
1637 typedef volatile struct ALT_ECC_QSPI_WDATA3BUS_s ALT_ECC_QSPI_WDATA3BUS_t;
1641 #define ALT_ECC_QSPI_WDATA3BUS_RESET 0x00000000
1643 #define ALT_ECC_QSPI_WDATA3BUS_OFST 0x60
1645 #define ALT_ECC_QSPI_WDATA3BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_QSPI_WDATA3BUS_OFST))
1676 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC0BUS_LSB 0
1678 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC0BUS_MSB 6
1680 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC0BUS_WIDTH 7
1682 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC0BUS_SET_MSK 0x0000007f
1684 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC0BUS_CLR_MSK 0xffffff80
1686 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC0BUS_RESET 0x0
1688 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC0BUS_GET(value) (((value) & 0x0000007f) >> 0)
1690 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC0BUS_SET(value) (((value) << 0) & 0x0000007f)
1701 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC1BUS_LSB 8
1703 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC1BUS_MSB 14
1705 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC1BUS_WIDTH 7
1707 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC1BUS_SET_MSK 0x00007f00
1709 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC1BUS_CLR_MSK 0xffff80ff
1711 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC1BUS_RESET 0x0
1713 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC1BUS_GET(value) (((value) & 0x00007f00) >> 8)
1715 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC1BUS_SET(value) (((value) << 8) & 0x00007f00)
1726 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC2BUS_LSB 16
1728 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC2BUS_MSB 22
1730 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC2BUS_WIDTH 7
1732 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC2BUS_SET_MSK 0x007f0000
1734 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC2BUS_CLR_MSK 0xff80ffff
1736 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC2BUS_RESET 0x0
1738 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC2BUS_GET(value) (((value) & 0x007f0000) >> 16)
1740 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC2BUS_SET(value) (((value) << 16) & 0x007f0000)
1751 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC3BUS_LSB 24
1753 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC3BUS_MSB 30
1755 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC3BUS_WIDTH 7
1757 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC3BUS_SET_MSK 0x7f000000
1759 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC3BUS_CLR_MSK 0x80ffffff
1761 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC3BUS_RESET 0x0
1763 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC3BUS_GET(value) (((value) & 0x7f000000) >> 24)
1765 #define ALT_ECC_QSPI_RDATAECC0BUS_ECC_RDATAECC3BUS_SET(value) (((value) << 24) & 0x7f000000)
1767 #ifndef __ASSEMBLY__
1778 struct ALT_ECC_QSPI_RDATAECC0BUS_s
1780 uint32_t ECC_RDataecc0BUS : 7;
1782 uint32_t ECC_RDataecc1BUS : 7;
1784 uint32_t ECC_RDataecc2BUS : 7;
1786 uint32_t ECC_RDataecc3BUS : 7;
1791 typedef volatile struct ALT_ECC_QSPI_RDATAECC0BUS_s ALT_ECC_QSPI_RDATAECC0BUS_t;
1795 #define ALT_ECC_QSPI_RDATAECC0BUS_RESET 0x00000000
1797 #define ALT_ECC_QSPI_RDATAECC0BUS_OFST 0x64
1799 #define ALT_ECC_QSPI_RDATAECC0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_QSPI_RDATAECC0BUS_OFST))
1830 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC4BUS_LSB 0
1832 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC4BUS_MSB 6
1834 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC4BUS_WIDTH 7
1836 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC4BUS_SET_MSK 0x0000007f
1838 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC4BUS_CLR_MSK 0xffffff80
1840 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC4BUS_RESET 0x0
1842 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC4BUS_GET(value) (((value) & 0x0000007f) >> 0)
1844 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC4BUS_SET(value) (((value) << 0) & 0x0000007f)
1855 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC5BUS_LSB 8
1857 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC5BUS_MSB 14
1859 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC5BUS_WIDTH 7
1861 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC5BUS_SET_MSK 0x00007f00
1863 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC5BUS_CLR_MSK 0xffff80ff
1865 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC5BUS_RESET 0x0
1867 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC5BUS_GET(value) (((value) & 0x00007f00) >> 8)
1869 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC5BUS_SET(value) (((value) << 8) & 0x00007f00)
1880 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC6BUS_LSB 16
1882 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC6BUS_MSB 22
1884 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC6BUS_WIDTH 7
1886 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC6BUS_SET_MSK 0x007f0000
1888 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC6BUS_CLR_MSK 0xff80ffff
1890 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC6BUS_RESET 0x0
1892 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC6BUS_GET(value) (((value) & 0x007f0000) >> 16)
1894 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC6BUS_SET(value) (((value) << 16) & 0x007f0000)
1905 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC7BUS_LSB 24
1907 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC7BUS_MSB 30
1909 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC7BUS_WIDTH 7
1911 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC7BUS_SET_MSK 0x7f000000
1913 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC7BUS_CLR_MSK 0x80ffffff
1915 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC7BUS_RESET 0x0
1917 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC7BUS_GET(value) (((value) & 0x7f000000) >> 24)
1919 #define ALT_ECC_QSPI_RDATAECC1BUS_ECC_RDATAECC7BUS_SET(value) (((value) << 24) & 0x7f000000)
1921 #ifndef __ASSEMBLY__
1932 struct ALT_ECC_QSPI_RDATAECC1BUS_s
1934 uint32_t ECC_RDataecc4BUS : 7;
1936 uint32_t ECC_RDataecc5BUS : 7;
1938 uint32_t ECC_RDataecc6BUS : 7;
1940 uint32_t ECC_RDataecc7BUS : 7;
1945 typedef volatile struct ALT_ECC_QSPI_RDATAECC1BUS_s ALT_ECC_QSPI_RDATAECC1BUS_t;
1949 #define ALT_ECC_QSPI_RDATAECC1BUS_RESET 0x00000000
1951 #define ALT_ECC_QSPI_RDATAECC1BUS_OFST 0x68
1953 #define ALT_ECC_QSPI_RDATAECC1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_QSPI_RDATAECC1BUS_OFST))
1984 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC0BUS_LSB 0
1986 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC0BUS_MSB 6
1988 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC0BUS_WIDTH 7
1990 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC0BUS_SET_MSK 0x0000007f
1992 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC0BUS_CLR_MSK 0xffffff80
1994 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC0BUS_RESET 0x0
1996 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC0BUS_GET(value) (((value) & 0x0000007f) >> 0)
1998 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC0BUS_SET(value) (((value) << 0) & 0x0000007f)
2009 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC1BUS_LSB 8
2011 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC1BUS_MSB 14
2013 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC1BUS_WIDTH 7
2015 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC1BUS_SET_MSK 0x00007f00
2017 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC1BUS_CLR_MSK 0xffff80ff
2019 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC1BUS_RESET 0x0
2021 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC1BUS_GET(value) (((value) & 0x00007f00) >> 8)
2023 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC1BUS_SET(value) (((value) << 8) & 0x00007f00)
2034 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC2BUS_LSB 16
2036 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC2BUS_MSB 22
2038 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC2BUS_WIDTH 7
2040 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC2BUS_SET_MSK 0x007f0000
2042 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC2BUS_CLR_MSK 0xff80ffff
2044 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC2BUS_RESET 0x0
2046 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC2BUS_GET(value) (((value) & 0x007f0000) >> 16)
2048 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC2BUS_SET(value) (((value) << 16) & 0x007f0000)
2059 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC3BUS_LSB 24
2061 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC3BUS_MSB 30
2063 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC3BUS_WIDTH 7
2065 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC3BUS_SET_MSK 0x7f000000
2067 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC3BUS_CLR_MSK 0x80ffffff
2069 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC3BUS_RESET 0x0
2071 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC3BUS_GET(value) (((value) & 0x7f000000) >> 24)
2073 #define ALT_ECC_QSPI_WDATAECC0BUS_ECC_WDATAECC3BUS_SET(value) (((value) << 24) & 0x7f000000)
2075 #ifndef __ASSEMBLY__
2086 struct ALT_ECC_QSPI_WDATAECC0BUS_s
2088 uint32_t ECC_WDataecc0BUS : 7;
2090 uint32_t ECC_WDataecc1BUS : 7;
2092 uint32_t ECC_WDataecc2BUS : 7;
2094 uint32_t ECC_WDataecc3BUS : 7;
2099 typedef volatile struct ALT_ECC_QSPI_WDATAECC0BUS_s ALT_ECC_QSPI_WDATAECC0BUS_t;
2103 #define ALT_ECC_QSPI_WDATAECC0BUS_RESET 0x00000000
2105 #define ALT_ECC_QSPI_WDATAECC0BUS_OFST 0x6c
2107 #define ALT_ECC_QSPI_WDATAECC0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_QSPI_WDATAECC0BUS_OFST))
2138 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC4BUS_LSB 0
2140 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC4BUS_MSB 6
2142 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC4BUS_WIDTH 7
2144 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC4BUS_SET_MSK 0x0000007f
2146 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC4BUS_CLR_MSK 0xffffff80
2148 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC4BUS_RESET 0x0
2150 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC4BUS_GET(value) (((value) & 0x0000007f) >> 0)
2152 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC4BUS_SET(value) (((value) << 0) & 0x0000007f)
2163 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC5BUS_LSB 8
2165 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC5BUS_MSB 14
2167 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC5BUS_WIDTH 7
2169 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC5BUS_SET_MSK 0x00007f00
2171 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC5BUS_CLR_MSK 0xffff80ff
2173 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC5BUS_RESET 0x0
2175 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC5BUS_GET(value) (((value) & 0x00007f00) >> 8)
2177 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC5BUS_SET(value) (((value) << 8) & 0x00007f00)
2188 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC6BUS_LSB 16
2190 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC6BUS_MSB 22
2192 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC6BUS_WIDTH 7
2194 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC6BUS_SET_MSK 0x007f0000
2196 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC6BUS_CLR_MSK 0xff80ffff
2198 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC6BUS_RESET 0x0
2200 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC6BUS_GET(value) (((value) & 0x007f0000) >> 16)
2202 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC6BUS_SET(value) (((value) << 16) & 0x007f0000)
2213 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC7BUS_LSB 24
2215 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC7BUS_MSB 30
2217 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC7BUS_WIDTH 7
2219 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC7BUS_SET_MSK 0x7f000000
2221 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC7BUS_CLR_MSK 0x80ffffff
2223 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC7BUS_RESET 0x0
2225 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC7BUS_GET(value) (((value) & 0x7f000000) >> 24)
2227 #define ALT_ECC_QSPI_WDATAECC1BUS_ECC_WDATAECC7BUS_SET(value) (((value) << 24) & 0x7f000000)
2229 #ifndef __ASSEMBLY__
2240 struct ALT_ECC_QSPI_WDATAECC1BUS_s
2242 uint32_t ECC_WDataecc4BUS : 7;
2244 uint32_t ECC_WDataecc5BUS : 7;
2246 uint32_t ECC_WDataecc6BUS : 7;
2248 uint32_t ECC_WDataecc7BUS : 7;
2253 typedef volatile struct ALT_ECC_QSPI_WDATAECC1BUS_s ALT_ECC_QSPI_WDATAECC1BUS_t;
2257 #define ALT_ECC_QSPI_WDATAECC1BUS_RESET 0x00000000
2259 #define ALT_ECC_QSPI_WDATAECC1BUS_OFST 0x70
2261 #define ALT_ECC_QSPI_WDATAECC1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_QSPI_WDATAECC1BUS_OFST))
2285 #define ALT_ECC_QSPI_DBYTECTL_DBEN_LSB 0
2287 #define ALT_ECC_QSPI_DBYTECTL_DBEN_MSB 0
2289 #define ALT_ECC_QSPI_DBYTECTL_DBEN_WIDTH 1
2291 #define ALT_ECC_QSPI_DBYTECTL_DBEN_SET_MSK 0x00000001
2293 #define ALT_ECC_QSPI_DBYTECTL_DBEN_CLR_MSK 0xfffffffe
2295 #define ALT_ECC_QSPI_DBYTECTL_DBEN_RESET 0x0
2297 #define ALT_ECC_QSPI_DBYTECTL_DBEN_GET(value) (((value) & 0x00000001) >> 0)
2299 #define ALT_ECC_QSPI_DBYTECTL_DBEN_SET(value) (((value) << 0) & 0x00000001)
2301 #ifndef __ASSEMBLY__
2312 struct ALT_ECC_QSPI_DBYTECTL_s
2319 typedef volatile struct ALT_ECC_QSPI_DBYTECTL_s ALT_ECC_QSPI_DBYTECTL_t;
2323 #define ALT_ECC_QSPI_DBYTECTL_RESET 0x00000000
2325 #define ALT_ECC_QSPI_DBYTECTL_OFST 0x74
2327 #define ALT_ECC_QSPI_DBYTECTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_QSPI_DBYTECTL_OFST))
2359 #define ALT_ECC_QSPI_ACCCTL_DATAOVR_LSB 0
2361 #define ALT_ECC_QSPI_ACCCTL_DATAOVR_MSB 0
2363 #define ALT_ECC_QSPI_ACCCTL_DATAOVR_WIDTH 1
2365 #define ALT_ECC_QSPI_ACCCTL_DATAOVR_SET_MSK 0x00000001
2367 #define ALT_ECC_QSPI_ACCCTL_DATAOVR_CLR_MSK 0xfffffffe
2369 #define ALT_ECC_QSPI_ACCCTL_DATAOVR_RESET 0x0
2371 #define ALT_ECC_QSPI_ACCCTL_DATAOVR_GET(value) (((value) & 0x00000001) >> 0)
2373 #define ALT_ECC_QSPI_ACCCTL_DATAOVR_SET(value) (((value) << 0) & 0x00000001)
2384 #define ALT_ECC_QSPI_ACCCTL_ECCOVR_LSB 1
2386 #define ALT_ECC_QSPI_ACCCTL_ECCOVR_MSB 1
2388 #define ALT_ECC_QSPI_ACCCTL_ECCOVR_WIDTH 1
2390 #define ALT_ECC_QSPI_ACCCTL_ECCOVR_SET_MSK 0x00000002
2392 #define ALT_ECC_QSPI_ACCCTL_ECCOVR_CLR_MSK 0xfffffffd
2394 #define ALT_ECC_QSPI_ACCCTL_ECCOVR_RESET 0x0
2396 #define ALT_ECC_QSPI_ACCCTL_ECCOVR_GET(value) (((value) & 0x00000002) >> 1)
2398 #define ALT_ECC_QSPI_ACCCTL_ECCOVR_SET(value) (((value) << 1) & 0x00000002)
2409 #define ALT_ECC_QSPI_ACCCTL_RDWR_LSB 8
2411 #define ALT_ECC_QSPI_ACCCTL_RDWR_MSB 8
2413 #define ALT_ECC_QSPI_ACCCTL_RDWR_WIDTH 1
2415 #define ALT_ECC_QSPI_ACCCTL_RDWR_SET_MSK 0x00000100
2417 #define ALT_ECC_QSPI_ACCCTL_RDWR_CLR_MSK 0xfffffeff
2419 #define ALT_ECC_QSPI_ACCCTL_RDWR_RESET 0x0
2421 #define ALT_ECC_QSPI_ACCCTL_RDWR_GET(value) (((value) & 0x00000100) >> 8)
2423 #define ALT_ECC_QSPI_ACCCTL_RDWR_SET(value) (((value) << 8) & 0x00000100)
2425 #ifndef __ASSEMBLY__
2436 struct ALT_ECC_QSPI_ACCCTL_s
2438 uint32_t DATAOVR : 1;
2439 uint32_t ECCOVR : 1;
2446 typedef volatile struct ALT_ECC_QSPI_ACCCTL_s ALT_ECC_QSPI_ACCCTL_t;
2450 #define ALT_ECC_QSPI_ACCCTL_RESET 0x00000000
2452 #define ALT_ECC_QSPI_ACCCTL_OFST 0x78
2454 #define ALT_ECC_QSPI_ACCCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_QSPI_ACCCTL_OFST))
2479 #define ALT_ECC_QSPI_STARTACC_ENBUSA_LSB 16
2481 #define ALT_ECC_QSPI_STARTACC_ENBUSA_MSB 16
2483 #define ALT_ECC_QSPI_STARTACC_ENBUSA_WIDTH 1
2485 #define ALT_ECC_QSPI_STARTACC_ENBUSA_SET_MSK 0x00010000
2487 #define ALT_ECC_QSPI_STARTACC_ENBUSA_CLR_MSK 0xfffeffff
2489 #define ALT_ECC_QSPI_STARTACC_ENBUSA_RESET 0x0
2491 #define ALT_ECC_QSPI_STARTACC_ENBUSA_GET(value) (((value) & 0x00010000) >> 16)
2493 #define ALT_ECC_QSPI_STARTACC_ENBUSA_SET(value) (((value) << 16) & 0x00010000)
2495 #ifndef __ASSEMBLY__
2506 struct ALT_ECC_QSPI_STARTACC_s
2509 uint32_t ENBUSA : 1;
2514 typedef volatile struct ALT_ECC_QSPI_STARTACC_s ALT_ECC_QSPI_STARTACC_t;
2518 #define ALT_ECC_QSPI_STARTACC_RESET 0x00000000
2520 #define ALT_ECC_QSPI_STARTACC_OFST 0x7c
2522 #define ALT_ECC_QSPI_STARTACC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_QSPI_STARTACC_OFST))
2546 #define ALT_ECC_QSPI_WDCTL_WDEN_RAM_LSB 0
2548 #define ALT_ECC_QSPI_WDCTL_WDEN_RAM_MSB 0
2550 #define ALT_ECC_QSPI_WDCTL_WDEN_RAM_WIDTH 1
2552 #define ALT_ECC_QSPI_WDCTL_WDEN_RAM_SET_MSK 0x00000001
2554 #define ALT_ECC_QSPI_WDCTL_WDEN_RAM_CLR_MSK 0xfffffffe
2556 #define ALT_ECC_QSPI_WDCTL_WDEN_RAM_RESET 0x0
2558 #define ALT_ECC_QSPI_WDCTL_WDEN_RAM_GET(value) (((value) & 0x00000001) >> 0)
2560 #define ALT_ECC_QSPI_WDCTL_WDEN_RAM_SET(value) (((value) << 0) & 0x00000001)
2562 #ifndef __ASSEMBLY__
2573 struct ALT_ECC_QSPI_WDCTL_s
2575 uint32_t WDEN_RAM : 1;
2580 typedef volatile struct ALT_ECC_QSPI_WDCTL_s ALT_ECC_QSPI_WDCTL_t;
2584 #define ALT_ECC_QSPI_WDCTL_RESET 0x00000000
2586 #define ALT_ECC_QSPI_WDCTL_OFST 0x80
2588 #define ALT_ECC_QSPI_WDCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_QSPI_WDCTL_OFST))
2617 #define ALT_ECC_QSPI_SERRLKUPA0_ADDR_LSB 0
2619 #define ALT_ECC_QSPI_SERRLKUPA0_ADDR_MSB 6
2621 #define ALT_ECC_QSPI_SERRLKUPA0_ADDR_WIDTH 7
2623 #define ALT_ECC_QSPI_SERRLKUPA0_ADDR_SET_MSK 0x0000007f
2625 #define ALT_ECC_QSPI_SERRLKUPA0_ADDR_CLR_MSK 0xffffff80
2627 #define ALT_ECC_QSPI_SERRLKUPA0_ADDR_RESET 0x0
2629 #define ALT_ECC_QSPI_SERRLKUPA0_ADDR_GET(value) (((value) & 0x0000007f) >> 0)
2631 #define ALT_ECC_QSPI_SERRLKUPA0_ADDR_SET(value) (((value) << 0) & 0x0000007f)
2643 #define ALT_ECC_QSPI_SERRLKUPA0_VALID_LSB 31
2645 #define ALT_ECC_QSPI_SERRLKUPA0_VALID_MSB 31
2647 #define ALT_ECC_QSPI_SERRLKUPA0_VALID_WIDTH 1
2649 #define ALT_ECC_QSPI_SERRLKUPA0_VALID_SET_MSK 0x80000000
2651 #define ALT_ECC_QSPI_SERRLKUPA0_VALID_CLR_MSK 0x7fffffff
2653 #define ALT_ECC_QSPI_SERRLKUPA0_VALID_RESET 0x0
2655 #define ALT_ECC_QSPI_SERRLKUPA0_VALID_GET(value) (((value) & 0x80000000) >> 31)
2657 #define ALT_ECC_QSPI_SERRLKUPA0_VALID_SET(value) (((value) << 31) & 0x80000000)
2659 #ifndef __ASSEMBLY__
2670 struct ALT_ECC_QSPI_SERRLKUPA0_s
2672 const uint32_t Address : 7;
2678 typedef volatile struct ALT_ECC_QSPI_SERRLKUPA0_s ALT_ECC_QSPI_SERRLKUPA0_t;
2682 #define ALT_ECC_QSPI_SERRLKUPA0_RESET 0x00000000
2684 #define ALT_ECC_QSPI_SERRLKUPA0_OFST 0x90
2686 #ifndef __ASSEMBLY__
2697 struct ALT_ECC_QSPI_s
2699 ALT_ECC_QSPI_IP_REV_ID_t IP_REV_ID;
2700 volatile uint32_t _pad_0x4_0x7;
2701 ALT_ECC_QSPI_CTL_t CTRL;
2702 ALT_ECC_QSPI_INITSTAT_t INITSTAT;
2703 ALT_ECC_QSPI_ERRINTEN_t ERRINTEN;
2704 ALT_ECC_QSPI_ERRINTENS_t ERRINTENS;
2705 ALT_ECC_QSPI_ERRINTENR_t ERRINTENR;
2706 ALT_ECC_QSPI_INTMOD_t INTMODE;
2707 ALT_ECC_QSPI_INTSTAT_t INTSTAT;
2708 ALT_ECC_QSPI_INTTEST_t INTTEST;
2709 ALT_ECC_QSPI_MODSTAT_t MODSTAT;
2710 ALT_ECC_QSPI_DERRADDRA_t DERRADDRA;
2711 ALT_ECC_QSPI_SERRADDRA_t SERRADDRA;
2712 volatile uint32_t _pad_0x34_0x3b[2];
2713 ALT_ECC_QSPI_SERRCNTREG_t SERRCNTREG;
2714 ALT_ECC_QSPI_ADDRBUS_t ECC_Addrbus;
2715 ALT_ECC_QSPI_RDATA0BUS_t ECC_RData0bus;
2716 ALT_ECC_QSPI_RDATA1BUS_t ECC_RData1bus;
2717 ALT_ECC_QSPI_RDATA2BUS_t ECC_RData2bus;
2718 ALT_ECC_QSPI_RDATA3BUS_t ECC_RData3bus;
2719 ALT_ECC_QSPI_WDATA0BUS_t ECC_WData0bus;
2720 ALT_ECC_QSPI_WDATA1BUS_t ECC_WData1bus;
2721 ALT_ECC_QSPI_WDATA2BUS_t ECC_WData2bus;
2722 ALT_ECC_QSPI_WDATA3BUS_t ECC_WData3bus;
2723 ALT_ECC_QSPI_RDATAECC0BUS_t ECC_RDataecc0bus;
2724 ALT_ECC_QSPI_RDATAECC1BUS_t ECC_RDataecc1bus;
2725 ALT_ECC_QSPI_WDATAECC0BUS_t ECC_WDataecc0bus;
2726 ALT_ECC_QSPI_WDATAECC1BUS_t ECC_WDataecc1bus;
2727 ALT_ECC_QSPI_DBYTECTL_t ECC_dbytectrl;
2728 ALT_ECC_QSPI_ACCCTL_t ECC_accctrl;
2729 ALT_ECC_QSPI_STARTACC_t ECC_startacc;
2730 ALT_ECC_QSPI_WDCTL_t ECC_wdctrl;
2731 volatile uint32_t _pad_0x84_0x8f[3];
2732 ALT_ECC_QSPI_SERRLKUPA0_t SERRLKUPA0;
2733 volatile uint32_t _pad_0x94_0x400[219];
2737 typedef volatile struct ALT_ECC_QSPI_s ALT_ECC_QSPI_t;
2739 struct ALT_ECC_QSPI_raw_s
2741 volatile uint32_t IP_REV_ID;
2742 uint32_t _pad_0x4_0x7;
2743 volatile uint32_t CTRL;
2744 volatile uint32_t INITSTAT;
2745 volatile uint32_t ERRINTEN;
2746 volatile uint32_t ERRINTENS;
2747 volatile uint32_t ERRINTENR;
2748 volatile uint32_t INTMODE;
2749 volatile uint32_t INTSTAT;
2750 volatile uint32_t INTTEST;
2751 volatile uint32_t MODSTAT;
2752 volatile uint32_t DERRADDRA;
2753 volatile uint32_t SERRADDRA;
2754 uint32_t _pad_0x34_0x3b[2];
2755 volatile uint32_t SERRCNTREG;
2756 volatile uint32_t ECC_Addrbus;
2757 volatile uint32_t ECC_RData0bus;
2758 volatile uint32_t ECC_RData1bus;
2759 volatile uint32_t ECC_RData2bus;
2760 volatile uint32_t ECC_RData3bus;
2761 volatile uint32_t ECC_WData0bus;
2762 volatile uint32_t ECC_WData1bus;
2763 volatile uint32_t ECC_WData2bus;
2764 volatile uint32_t ECC_WData3bus;
2765 volatile uint32_t ECC_RDataecc0bus;
2766 volatile uint32_t ECC_RDataecc1bus;
2767 volatile uint32_t ECC_WDataecc0bus;
2768 volatile uint32_t ECC_WDataecc1bus;
2769 volatile uint32_t ECC_dbytectrl;
2770 volatile uint32_t ECC_accctrl;
2771 volatile uint32_t ECC_startacc;
2772 volatile uint32_t ECC_wdctrl;
2773 uint32_t _pad_0x84_0x8f[3];
2774 volatile uint32_t SERRLKUPA0;
2775 uint32_t _pad_0x94_0x400[219];
2779 typedef volatile struct ALT_ECC_QSPI_raw_s ALT_ECC_QSPI_raw_t;