Hardware Libraries  20.1
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alt_i2c.h
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32 
33 /* Altera - ALT_I2C */
34 
35 #ifndef __ALT_SOCAL_I2C_H__
36 #define __ALT_SOCAL_I2C_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : I2C
50  * DW_apb_i2c address block
51  *
52  */
53 /*
54  * Register : I2C Control Register - IC_CON
55  *
56  * Name: I2C Control Register
57  *
58  * Size: 20 bits
59  *
60  * Address Offset: 0x00
61  *
62  * Read/Write Access:
63  *
64  * If configuration parameter I2C_DYNAMIC_TAR_UPDATE=1 bit 4 is readonly.
65  *
66  * If configuration parameter IC_RX_FULL_HLD_BUS_EN =0 bit 9 is readonly.
67  *
68  * If configuration parameter IC_STOP_DET_IF_MASTER_ACTIVE =0 bit 10 is readonly.
69  *
70  * If configuration parameter IC_BUS_CLEAR_FEATURE=0 bit 11 is readonly
71  *
72  * If configuration parameter IC_OPTIONAL_SAR=0 bit 16 is readonly
73  *
74  * If configuration parameter IC_SMBUS=0 bit 17 is readonly
75  *
76  * If configuration parameter IC_SMBUS_ARP=0 bits 18 & 19 are readonly
77  *
78  * This register can be written only when the DW_apb_i2c
79  *
80  * is disabled, which corresponds to the IC_ENABLE[0] register
81  *
82  * being set to 0. Writes at other times have no effect.
83  *
84  * Register Layout
85  *
86  * Bits | Access | Reset | Description
87  * :--------|:-------|:------|:-------------------------------------------------
88  * [0] | RW | 0x1 | ALT_I2C_IC_CON_MASTER_MODE
89  * [2:1] | RW | 0x2 | ALT_I2C_IC_CON_SPEED
90  * [3] | RW | 0x1 | ALT_I2C_IC_CON_IC_10BITADDR_SLAVE
91  * [4] | R | 0x1 | ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY
92  * [5] | RW | 0x1 | ALT_I2C_IC_CON_IC_RESTART_EN
93  * [6] | RW | 0x1 | ALT_I2C_IC_CON_IC_SLAVE_DISABLE
94  * [7] | RW | 0x0 | ALT_I2C_IC_CON_STOP_DET_IFADDRESSED
95  * [8] | RW | 0x0 | ALT_I2C_IC_CON_TX_EMPTY_CTRL
96  * [9] | R | 0x0 | ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL
97  * [10] | R | 0x0 | ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE
98  * [11] | R | 0x0 | ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL
99  * [15:12] | R | 0x0 | ALT_I2C_IC_CON_RSVD_IC_CON_1
100  * [16] | R | 0x0 | ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL
101  * [17] | R | 0x0 | ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN
102  * [18] | R | 0x0 | ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN
103  * [19] | R | 0x0 | ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN
104  * [31:20] | R | 0x0 | ALT_I2C_IC_CON_RSVD_IC_CON_2
105  *
106  */
107 /*
108  * Field : MASTER_MODE
109  *
110  * This bit controls whether the DW_apb_i2c master is enabled.
111  *
112  * 0: master disabled
113  *
114  * 1: master enabled
115  *
116  * Reset value: IC_MASTER_MODE configuration parameter
117  *
118  * NOTE: Software should ensure that if this bit is written with '1'
119  *
120  * then bit 6 should also be written with a '1'.
121  *
122  * Field Enumeration Values:
123  *
124  * Enum | Value | Description
125  * :--------------------------------------|:------|:------------------------
126  * ALT_I2C_IC_CON_MASTER_MODE_E_DISABLED | 0x0 | Master mode is disabled
127  * ALT_I2C_IC_CON_MASTER_MODE_E_ENABLED | 0x1 | Master mode is enabled
128  *
129  * Field Access Macros:
130  *
131  */
132 /*
133  * Enumerated value for register field ALT_I2C_IC_CON_MASTER_MODE
134  *
135  * Master mode is disabled
136  */
137 #define ALT_I2C_IC_CON_MASTER_MODE_E_DISABLED 0x0
138 /*
139  * Enumerated value for register field ALT_I2C_IC_CON_MASTER_MODE
140  *
141  * Master mode is enabled
142  */
143 #define ALT_I2C_IC_CON_MASTER_MODE_E_ENABLED 0x1
144 
145 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CON_MASTER_MODE register field. */
146 #define ALT_I2C_IC_CON_MASTER_MODE_LSB 0
147 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CON_MASTER_MODE register field. */
148 #define ALT_I2C_IC_CON_MASTER_MODE_MSB 0
149 /* The width in bits of the ALT_I2C_IC_CON_MASTER_MODE register field. */
150 #define ALT_I2C_IC_CON_MASTER_MODE_WIDTH 1
151 /* The mask used to set the ALT_I2C_IC_CON_MASTER_MODE register field value. */
152 #define ALT_I2C_IC_CON_MASTER_MODE_SET_MSK 0x00000001
153 /* The mask used to clear the ALT_I2C_IC_CON_MASTER_MODE register field value. */
154 #define ALT_I2C_IC_CON_MASTER_MODE_CLR_MSK 0xfffffffe
155 /* The reset value of the ALT_I2C_IC_CON_MASTER_MODE register field. */
156 #define ALT_I2C_IC_CON_MASTER_MODE_RESET 0x1
157 /* Extracts the ALT_I2C_IC_CON_MASTER_MODE field value from a register. */
158 #define ALT_I2C_IC_CON_MASTER_MODE_GET(value) (((value) & 0x00000001) >> 0)
159 /* Produces a ALT_I2C_IC_CON_MASTER_MODE register field value suitable for setting the register. */
160 #define ALT_I2C_IC_CON_MASTER_MODE_SET(value) (((value) << 0) & 0x00000001)
161 
162 /*
163  * Field : SPEED
164  *
165  * These bits control at which speed the DW_apb_i2c operates; its
166  *
167  * setting is relevant only if one is operating the DW_apb_i2c in
168  *
169  * master mode. Hardware protects against illegal values being
170  *
171  * programmed by software. This register should be programmed
172  *
173  * only with a value in the range of 1 to IC_MAX_SPEED_MODE;
174  *
175  * otherwise, hardware updates this register with the value of
176  *
177  * IC_MAX_SPEED_MODE.
178  *
179  * 1: standard mode (100 kbit/s)
180  *
181  * 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)
182  *
183  * 3: high speed mode (3.4 Mbit/s)
184  *
185  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
186  *
187  * Reset value: IC_MAX_SPEED_MODE configuration
188  *
189  * Field Enumeration Values:
190  *
191  * Enum | Value | Description
192  * :--------------------------------|:------|:------------------------------------
193  * ALT_I2C_IC_CON_SPEED_E_STANDARD | 0x1 | Standard Speed mode of operation
194  * ALT_I2C_IC_CON_SPEED_E_FAST | 0x2 | Fast or Fast Plus mode of operation
195  * ALT_I2C_IC_CON_SPEED_E_HIGH | 0x3 | High Speed mode of operation
196  *
197  * Field Access Macros:
198  *
199  */
200 /*
201  * Enumerated value for register field ALT_I2C_IC_CON_SPEED
202  *
203  * Standard Speed mode of operation
204  */
205 #define ALT_I2C_IC_CON_SPEED_E_STANDARD 0x1
206 /*
207  * Enumerated value for register field ALT_I2C_IC_CON_SPEED
208  *
209  * Fast or Fast Plus mode of operation
210  */
211 #define ALT_I2C_IC_CON_SPEED_E_FAST 0x2
212 /*
213  * Enumerated value for register field ALT_I2C_IC_CON_SPEED
214  *
215  * High Speed mode of operation
216  */
217 #define ALT_I2C_IC_CON_SPEED_E_HIGH 0x3
218 
219 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CON_SPEED register field. */
220 #define ALT_I2C_IC_CON_SPEED_LSB 1
221 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CON_SPEED register field. */
222 #define ALT_I2C_IC_CON_SPEED_MSB 2
223 /* The width in bits of the ALT_I2C_IC_CON_SPEED register field. */
224 #define ALT_I2C_IC_CON_SPEED_WIDTH 2
225 /* The mask used to set the ALT_I2C_IC_CON_SPEED register field value. */
226 #define ALT_I2C_IC_CON_SPEED_SET_MSK 0x00000006
227 /* The mask used to clear the ALT_I2C_IC_CON_SPEED register field value. */
228 #define ALT_I2C_IC_CON_SPEED_CLR_MSK 0xfffffff9
229 /* The reset value of the ALT_I2C_IC_CON_SPEED register field. */
230 #define ALT_I2C_IC_CON_SPEED_RESET 0x2
231 /* Extracts the ALT_I2C_IC_CON_SPEED field value from a register. */
232 #define ALT_I2C_IC_CON_SPEED_GET(value) (((value) & 0x00000006) >> 1)
233 /* Produces a ALT_I2C_IC_CON_SPEED register field value suitable for setting the register. */
234 #define ALT_I2C_IC_CON_SPEED_SET(value) (((value) << 1) & 0x00000006)
235 
236 /*
237  * Field : IC_10BITADDR_SLAVE
238  *
239  * When acting as a slave, this bit controls whether the DW_apb_i2c
240  *
241  * responds to 7- or 10-bit addresses.
242  *
243  * 0: 7-bit addressing. The DW_apb_i2c ignores transactions that
244  *
245  * involve 10-bit addressing; for 7-bit addressing,
246  *
247  * only the lower 7 bits of the IC_SAR register are compared.
248  *
249  * 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit
250  *
251  * addressing transfers that match the full 10 bits of the IC_SAR
252  *
253  * register.
254  *
255  * Reset value: IC_10BITADDR_SLAVE configuration parameter
256  *
257  * Field Enumeration Values:
258  *
259  * Enum | Value | Description
260  * :------------------------------------------------|:------|:-----------------------
261  * ALT_I2C_IC_CON_IC_10BITADDR_SLAVE_E_ADDR_7BITS | 0x0 | Slave 7Bit addressing
262  * ALT_I2C_IC_CON_IC_10BITADDR_SLAVE_E_ADDR_10BITS | 0x1 | Slave 10Bit addressing
263  *
264  * Field Access Macros:
265  *
266  */
267 /*
268  * Enumerated value for register field ALT_I2C_IC_CON_IC_10BITADDR_SLAVE
269  *
270  * Slave 7Bit addressing
271  */
272 #define ALT_I2C_IC_CON_IC_10BITADDR_SLAVE_E_ADDR_7BITS 0x0
273 /*
274  * Enumerated value for register field ALT_I2C_IC_CON_IC_10BITADDR_SLAVE
275  *
276  * Slave 10Bit addressing
277  */
278 #define ALT_I2C_IC_CON_IC_10BITADDR_SLAVE_E_ADDR_10BITS 0x1
279 
280 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CON_IC_10BITADDR_SLAVE register field. */
281 #define ALT_I2C_IC_CON_IC_10BITADDR_SLAVE_LSB 3
282 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CON_IC_10BITADDR_SLAVE register field. */
283 #define ALT_I2C_IC_CON_IC_10BITADDR_SLAVE_MSB 3
284 /* The width in bits of the ALT_I2C_IC_CON_IC_10BITADDR_SLAVE register field. */
285 #define ALT_I2C_IC_CON_IC_10BITADDR_SLAVE_WIDTH 1
286 /* The mask used to set the ALT_I2C_IC_CON_IC_10BITADDR_SLAVE register field value. */
287 #define ALT_I2C_IC_CON_IC_10BITADDR_SLAVE_SET_MSK 0x00000008
288 /* The mask used to clear the ALT_I2C_IC_CON_IC_10BITADDR_SLAVE register field value. */
289 #define ALT_I2C_IC_CON_IC_10BITADDR_SLAVE_CLR_MSK 0xfffffff7
290 /* The reset value of the ALT_I2C_IC_CON_IC_10BITADDR_SLAVE register field. */
291 #define ALT_I2C_IC_CON_IC_10BITADDR_SLAVE_RESET 0x1
292 /* Extracts the ALT_I2C_IC_CON_IC_10BITADDR_SLAVE field value from a register. */
293 #define ALT_I2C_IC_CON_IC_10BITADDR_SLAVE_GET(value) (((value) & 0x00000008) >> 3)
294 /* Produces a ALT_I2C_IC_CON_IC_10BITADDR_SLAVE register field value suitable for setting the register. */
295 #define ALT_I2C_IC_CON_IC_10BITADDR_SLAVE_SET(value) (((value) << 3) & 0x00000008)
296 
297 /*
298  * Field : IC_10BITADDR_MASTER_rd_only
299  *
300  * If the I2C_DYNAMIC_TAR_UPDATE configuration parameter is
301  *
302  * set to 'No' (0), this bit is named IC_10BITADDR_MASTER and
303  *
304  * controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit
305  *
306  * addressing mode when acting as a master.
307  *
308  * If I2C_DYNAMIC_TAR_UPDATE is set to 'Yes' (1), the
309  *
310  * function of this bit is handled by bit 12 of IC_TAR register, and
311  *
312  * becomes a read-only copy called
313  *
314  * IC_10BITADDR_MASTER_rd_only.
315  *
316  * 0: 7-bit addressing
317  *
318  * 1: 10-bit addressing
319  *
320  * Dependencies: If I2C_DYNAMIC_TAR_UPDATE = 1, then this
321  *
322  * bit is read-only. If I2C_DYNAMIC_TAR_UPDATE = 0, then this
323  *
324  * bit can be read or write.
325  *
326  * Reset value: IC_10BITADDR_MASTER configuration
327  *
328  * parameter
329  *
330  * Field Enumeration Values:
331  *
332  * Enum | Value | Description
333  * :---------------------------------------------------------|:------|:-----------------------------
334  * ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_E_ADDR_7BITS | 0x0 | Master 7Bit addressing mode
335  * ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_E_ADDR_10BITS | 0x1 | Master 10Bit addressing mode
336  *
337  * Field Access Macros:
338  *
339  */
340 /*
341  * Enumerated value for register field ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY
342  *
343  * Master 7Bit addressing mode
344  */
345 #define ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_E_ADDR_7BITS 0x0
346 /*
347  * Enumerated value for register field ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY
348  *
349  * Master 10Bit addressing mode
350  */
351 #define ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_E_ADDR_10BITS 0x1
352 
353 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY register field. */
354 #define ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_LSB 4
355 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY register field. */
356 #define ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_MSB 4
357 /* The width in bits of the ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY register field. */
358 #define ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_WIDTH 1
359 /* The mask used to set the ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY register field value. */
360 #define ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_SET_MSK 0x00000010
361 /* The mask used to clear the ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY register field value. */
362 #define ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_CLR_MSK 0xffffffef
363 /* The reset value of the ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY register field. */
364 #define ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_RESET 0x1
365 /* Extracts the ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY field value from a register. */
366 #define ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_GET(value) (((value) & 0x00000010) >> 4)
367 /* Produces a ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY register field value suitable for setting the register. */
368 #define ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_SET(value) (((value) << 4) & 0x00000010)
369 
370 /*
371  * Field : IC_RESTART_EN
372  *
373  * Determines whether RESTART conditions may be sent when
374  *
375  * acting as a master. Some older slaves do not support handling
376  *
377  * RESTART conditions; however, RESTART conditions are used in
378  *
379  * several DW_apb_i2c operations.
380  *
381  * 0: disable
382  *
383  * 1: enable
384  *
385  * When RESTART is disabled, the master is prohibited from
386  *
387  * performing the following functions:
388  *
389  * * Change direction within a transfer (split)
390  *
391  * * Send a START BYTE
392  *
393  * * High-speed mode operation
394  *
395  * * Combined format transfers in 7-bit addressing modes
396  *
397  * * Read operation with a 10-bit address
398  *
399  * * Send multiple bytes per transfer
400  *
401  * By replacing RESTART condition followed by a STOP and a
402  *
403  * subsequent START condition, split operations are broken down
404  *
405  * into multiple DW_apb_i2c transfers. If the above operations are
406  *
407  * performed, it will result in setting bit 6 (TX_ABRT) of the
408  *
409  * IC_RAW_INTR_STAT register.
410  *
411  * Reset value: IC_RESTART_EN configuration parameter
412  *
413  * Field Enumeration Values:
414  *
415  * Enum | Value | Description
416  * :----------------------------------------|:------|:------------------------
417  * ALT_I2C_IC_CON_IC_RESTART_EN_E_DISABLED | 0x0 | Master restart disabled
418  * ALT_I2C_IC_CON_IC_RESTART_EN_E_ENABLED | 0x1 | Master restart enabled
419  *
420  * Field Access Macros:
421  *
422  */
423 /*
424  * Enumerated value for register field ALT_I2C_IC_CON_IC_RESTART_EN
425  *
426  * Master restart disabled
427  */
428 #define ALT_I2C_IC_CON_IC_RESTART_EN_E_DISABLED 0x0
429 /*
430  * Enumerated value for register field ALT_I2C_IC_CON_IC_RESTART_EN
431  *
432  * Master restart enabled
433  */
434 #define ALT_I2C_IC_CON_IC_RESTART_EN_E_ENABLED 0x1
435 
436 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CON_IC_RESTART_EN register field. */
437 #define ALT_I2C_IC_CON_IC_RESTART_EN_LSB 5
438 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CON_IC_RESTART_EN register field. */
439 #define ALT_I2C_IC_CON_IC_RESTART_EN_MSB 5
440 /* The width in bits of the ALT_I2C_IC_CON_IC_RESTART_EN register field. */
441 #define ALT_I2C_IC_CON_IC_RESTART_EN_WIDTH 1
442 /* The mask used to set the ALT_I2C_IC_CON_IC_RESTART_EN register field value. */
443 #define ALT_I2C_IC_CON_IC_RESTART_EN_SET_MSK 0x00000020
444 /* The mask used to clear the ALT_I2C_IC_CON_IC_RESTART_EN register field value. */
445 #define ALT_I2C_IC_CON_IC_RESTART_EN_CLR_MSK 0xffffffdf
446 /* The reset value of the ALT_I2C_IC_CON_IC_RESTART_EN register field. */
447 #define ALT_I2C_IC_CON_IC_RESTART_EN_RESET 0x1
448 /* Extracts the ALT_I2C_IC_CON_IC_RESTART_EN field value from a register. */
449 #define ALT_I2C_IC_CON_IC_RESTART_EN_GET(value) (((value) & 0x00000020) >> 5)
450 /* Produces a ALT_I2C_IC_CON_IC_RESTART_EN register field value suitable for setting the register. */
451 #define ALT_I2C_IC_CON_IC_RESTART_EN_SET(value) (((value) << 5) & 0x00000020)
452 
453 /*
454  * Field : IC_SLAVE_DISABLE
455  *
456  * This bit controls whether I2C has its slave disabled,
457  *
458  * which means once the presetn signal is applied, then
459  *
460  * this bit takes on the value of the configuration parameter
461  *
462  * IC_SLAVE_DISABLE. You have the choice of having the slave enabled
463  *
464  * or disabled after reset is applied, which means software does not
465  *
466  * have to configure the slave. By default, the slave is always enabled
467  *
468  * (in reset state as well). If you need to disable it after reset, set
469  *
470  * this bit to 1.
471  *
472  * If this bit is set (slave is disabled), DW_apb_i2c functions only as
473  *
474  * a master and does not perform any action that requires a slave.
475  *
476  * 0: slave is enabled
477  *
478  * 1: slave is disabled
479  *
480  * Reset value: IC_SLAVE_DISABLE configuration parameter
481  *
482  * NOTE: Software should ensure that if this bit is written with 0,
483  *
484  * then bit 0 should also be written with a 0.
485  *
486  * Field Enumeration Values:
487  *
488  * Enum | Value | Description
489  * :-------------------------------------------------|:------|:-----------------------
490  * ALT_I2C_IC_CON_IC_SLAVE_DISABLE_E_SLAVE_ENABLED | 0x0 | Slave mode is enabled
491  * ALT_I2C_IC_CON_IC_SLAVE_DISABLE_E_SLAVE_DISABLED | 0x1 | Slave mode is disabled
492  *
493  * Field Access Macros:
494  *
495  */
496 /*
497  * Enumerated value for register field ALT_I2C_IC_CON_IC_SLAVE_DISABLE
498  *
499  * Slave mode is enabled
500  */
501 #define ALT_I2C_IC_CON_IC_SLAVE_DISABLE_E_SLAVE_ENABLED 0x0
502 /*
503  * Enumerated value for register field ALT_I2C_IC_CON_IC_SLAVE_DISABLE
504  *
505  * Slave mode is disabled
506  */
507 #define ALT_I2C_IC_CON_IC_SLAVE_DISABLE_E_SLAVE_DISABLED 0x1
508 
509 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CON_IC_SLAVE_DISABLE register field. */
510 #define ALT_I2C_IC_CON_IC_SLAVE_DISABLE_LSB 6
511 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CON_IC_SLAVE_DISABLE register field. */
512 #define ALT_I2C_IC_CON_IC_SLAVE_DISABLE_MSB 6
513 /* The width in bits of the ALT_I2C_IC_CON_IC_SLAVE_DISABLE register field. */
514 #define ALT_I2C_IC_CON_IC_SLAVE_DISABLE_WIDTH 1
515 /* The mask used to set the ALT_I2C_IC_CON_IC_SLAVE_DISABLE register field value. */
516 #define ALT_I2C_IC_CON_IC_SLAVE_DISABLE_SET_MSK 0x00000040
517 /* The mask used to clear the ALT_I2C_IC_CON_IC_SLAVE_DISABLE register field value. */
518 #define ALT_I2C_IC_CON_IC_SLAVE_DISABLE_CLR_MSK 0xffffffbf
519 /* The reset value of the ALT_I2C_IC_CON_IC_SLAVE_DISABLE register field. */
520 #define ALT_I2C_IC_CON_IC_SLAVE_DISABLE_RESET 0x1
521 /* Extracts the ALT_I2C_IC_CON_IC_SLAVE_DISABLE field value from a register. */
522 #define ALT_I2C_IC_CON_IC_SLAVE_DISABLE_GET(value) (((value) & 0x00000040) >> 6)
523 /* Produces a ALT_I2C_IC_CON_IC_SLAVE_DISABLE register field value suitable for setting the register. */
524 #define ALT_I2C_IC_CON_IC_SLAVE_DISABLE_SET(value) (((value) << 6) & 0x00000040)
525 
526 /*
527  * Field : STOP_DET_IFADDRESSED
528  *
529  * In slave mode:
530  *
531  * 1: issues the STOP_DET interrrupt only when it is addressed.
532  *
533  * 0: issues the STOP_DET irrespective of whether it's addressed or not.
534  *
535  * Dependencies: This register bit value is applicable in the slave mode only
536  * (MASTER_MODE = 1'b0)
537  *
538  * Reset value: 0x0
539  *
540  * NOTE: During a general call address, this slave does not issue the
541  *
542  * STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if
543  *
544  * the slave responds to the general call address by generating ACK.
545  *
546  * The STOP_DET interrupt is generated only when the transmitted
547  *
548  * address matches the slave address (SAR).
549  *
550  * Field Enumeration Values:
551  *
552  * Enum | Value | Description
553  * :-----------------------------------------------|:------|:---------------------------------------------
554  * ALT_I2C_IC_CON_STOP_DET_IFADDRESSED_E_DISABLED | 0x0 | slave issues STOP_DET intr always
555  * ALT_I2C_IC_CON_STOP_DET_IFADDRESSED_E_ENABLED | 0x1 | slave issues STOP_DET intr only if addressed
556  *
557  * Field Access Macros:
558  *
559  */
560 /*
561  * Enumerated value for register field ALT_I2C_IC_CON_STOP_DET_IFADDRESSED
562  *
563  * slave issues STOP_DET intr always
564  */
565 #define ALT_I2C_IC_CON_STOP_DET_IFADDRESSED_E_DISABLED 0x0
566 /*
567  * Enumerated value for register field ALT_I2C_IC_CON_STOP_DET_IFADDRESSED
568  *
569  * slave issues STOP_DET intr only if addressed
570  */
571 #define ALT_I2C_IC_CON_STOP_DET_IFADDRESSED_E_ENABLED 0x1
572 
573 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CON_STOP_DET_IFADDRESSED register field. */
574 #define ALT_I2C_IC_CON_STOP_DET_IFADDRESSED_LSB 7
575 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CON_STOP_DET_IFADDRESSED register field. */
576 #define ALT_I2C_IC_CON_STOP_DET_IFADDRESSED_MSB 7
577 /* The width in bits of the ALT_I2C_IC_CON_STOP_DET_IFADDRESSED register field. */
578 #define ALT_I2C_IC_CON_STOP_DET_IFADDRESSED_WIDTH 1
579 /* The mask used to set the ALT_I2C_IC_CON_STOP_DET_IFADDRESSED register field value. */
580 #define ALT_I2C_IC_CON_STOP_DET_IFADDRESSED_SET_MSK 0x00000080
581 /* The mask used to clear the ALT_I2C_IC_CON_STOP_DET_IFADDRESSED register field value. */
582 #define ALT_I2C_IC_CON_STOP_DET_IFADDRESSED_CLR_MSK 0xffffff7f
583 /* The reset value of the ALT_I2C_IC_CON_STOP_DET_IFADDRESSED register field. */
584 #define ALT_I2C_IC_CON_STOP_DET_IFADDRESSED_RESET 0x0
585 /* Extracts the ALT_I2C_IC_CON_STOP_DET_IFADDRESSED field value from a register. */
586 #define ALT_I2C_IC_CON_STOP_DET_IFADDRESSED_GET(value) (((value) & 0x00000080) >> 7)
587 /* Produces a ALT_I2C_IC_CON_STOP_DET_IFADDRESSED register field value suitable for setting the register. */
588 #define ALT_I2C_IC_CON_STOP_DET_IFADDRESSED_SET(value) (((value) << 7) & 0x00000080)
589 
590 /*
591  * Field : TX_EMPTY_CTRL
592  *
593  * This bit controls the generation
594  *
595  * of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.
596  *
597  * Reset value: 0x0.
598  *
599  * Field Enumeration Values:
600  *
601  * Enum | Value | Description
602  * :----------------------------------------|:------|:--------------------------------------------
603  * ALT_I2C_IC_CON_TX_EMPTY_CTRL_E_DISABLED | 0x0 | Default behaviour of TX_EMPTY interrupt
604  * ALT_I2C_IC_CON_TX_EMPTY_CTRL_E_ENABLED | 0x1 | Controlled generation of TX_EMPTY interrupt
605  *
606  * Field Access Macros:
607  *
608  */
609 /*
610  * Enumerated value for register field ALT_I2C_IC_CON_TX_EMPTY_CTRL
611  *
612  * Default behaviour of TX_EMPTY interrupt
613  */
614 #define ALT_I2C_IC_CON_TX_EMPTY_CTRL_E_DISABLED 0x0
615 /*
616  * Enumerated value for register field ALT_I2C_IC_CON_TX_EMPTY_CTRL
617  *
618  * Controlled generation of TX_EMPTY interrupt
619  */
620 #define ALT_I2C_IC_CON_TX_EMPTY_CTRL_E_ENABLED 0x1
621 
622 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CON_TX_EMPTY_CTRL register field. */
623 #define ALT_I2C_IC_CON_TX_EMPTY_CTRL_LSB 8
624 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CON_TX_EMPTY_CTRL register field. */
625 #define ALT_I2C_IC_CON_TX_EMPTY_CTRL_MSB 8
626 /* The width in bits of the ALT_I2C_IC_CON_TX_EMPTY_CTRL register field. */
627 #define ALT_I2C_IC_CON_TX_EMPTY_CTRL_WIDTH 1
628 /* The mask used to set the ALT_I2C_IC_CON_TX_EMPTY_CTRL register field value. */
629 #define ALT_I2C_IC_CON_TX_EMPTY_CTRL_SET_MSK 0x00000100
630 /* The mask used to clear the ALT_I2C_IC_CON_TX_EMPTY_CTRL register field value. */
631 #define ALT_I2C_IC_CON_TX_EMPTY_CTRL_CLR_MSK 0xfffffeff
632 /* The reset value of the ALT_I2C_IC_CON_TX_EMPTY_CTRL register field. */
633 #define ALT_I2C_IC_CON_TX_EMPTY_CTRL_RESET 0x0
634 /* Extracts the ALT_I2C_IC_CON_TX_EMPTY_CTRL field value from a register. */
635 #define ALT_I2C_IC_CON_TX_EMPTY_CTRL_GET(value) (((value) & 0x00000100) >> 8)
636 /* Produces a ALT_I2C_IC_CON_TX_EMPTY_CTRL register field value suitable for setting the register. */
637 #define ALT_I2C_IC_CON_TX_EMPTY_CTRL_SET(value) (((value) << 8) & 0x00000100)
638 
639 /*
640  * Field : RX_FIFO_FULL_HLD_CTRL
641  *
642  * This bit controls whether
643  *
644  * DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its
645  * RX_BUFFER_DEPTH,
646  *
647  * as described in the IC_RX_FULL_HLD_BUS_EN parameter.
648  *
649  * Dependencies: This register bit value is applicable only when the
650  *
651  * IC_RX_FULL_HLD_BUS_EN configuration parameter is set to 1 and
652  * IC_ULTRA_FAST_MODE=0
653  *
654  * If IC_RX_FULL_HLD_BUS_EN = 0, then this bit is read-only.
655  *
656  * If IC_RX_FULL_HLD_BUS_EN = 1, then this bit can be read or write.
657  *
658  * Reset value: 0x0.
659  *
660  * Field Enumeration Values:
661  *
662  * Enum | Value | Description
663  * :------------------------------------------------|:------|:------------------------------
664  * ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_E_DISABLED | 0x0 | Overflow when RX_FIFO is full
665  * ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_E_ENABLED | 0x1 | Hold bus when RX_FIFO is full
666  *
667  * Field Access Macros:
668  *
669  */
670 /*
671  * Enumerated value for register field ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL
672  *
673  * Overflow when RX_FIFO is full
674  */
675 #define ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_E_DISABLED 0x0
676 /*
677  * Enumerated value for register field ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL
678  *
679  * Hold bus when RX_FIFO is full
680  */
681 #define ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_E_ENABLED 0x1
682 
683 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL register field. */
684 #define ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_LSB 9
685 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL register field. */
686 #define ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_MSB 9
687 /* The width in bits of the ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL register field. */
688 #define ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_WIDTH 1
689 /* The mask used to set the ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL register field value. */
690 #define ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_SET_MSK 0x00000200
691 /* The mask used to clear the ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL register field value. */
692 #define ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_CLR_MSK 0xfffffdff
693 /* The reset value of the ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL register field. */
694 #define ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_RESET 0x0
695 /* Extracts the ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL field value from a register. */
696 #define ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_GET(value) (((value) & 0x00000200) >> 9)
697 /* Produces a ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL register field value suitable for setting the register. */
698 #define ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_SET(value) (((value) << 9) & 0x00000200)
699 
700 /*
701  * Field : STOP_DET_IF_MASTER_ACTIVE
702  *
703  * In Master mode:
704  *
705  * 1'b1: issues the STOP_DET interrupt only when master is active.
706  *
707  * 1'b0: issues the STOP_DET irrespective of whether master is active or not.
708  *
709  * Dependencies: This Register bit value is applicable only when
710  * IC_STOP_DET_IF_MASTER_ACTIVE=1 and IC_ULTRA_FAST_MODE=0
711  *
712  * Reset value: 0x0.
713  *
714  * Field Enumeration Values:
715  *
716  * Enum | Value | Description
717  * :----------------------------------------------------|:------|:------------------------------------------------
718  * ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_E_DISABLED | 0x0 | Master issues the STOP_DET interrupt
719  * : | | irrespective of whether master is active or not
720  * ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_E_ENABLED | 0x1 | Master issues the STOP_DET interrupt only when
721  * : | | master is active
722  *
723  * Field Access Macros:
724  *
725  */
726 /*
727  * Enumerated value for register field ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE
728  *
729  * Master issues the STOP_DET interrupt irrespective of whether master is active or
730  * not
731  */
732 #define ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_E_DISABLED 0x0
733 /*
734  * Enumerated value for register field ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE
735  *
736  * Master issues the STOP_DET interrupt only when master is active
737  */
738 #define ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_E_ENABLED 0x1
739 
740 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE register field. */
741 #define ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_LSB 10
742 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE register field. */
743 #define ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_MSB 10
744 /* The width in bits of the ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE register field. */
745 #define ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_WIDTH 1
746 /* The mask used to set the ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE register field value. */
747 #define ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_SET_MSK 0x00000400
748 /* The mask used to clear the ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE register field value. */
749 #define ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_CLR_MSK 0xfffffbff
750 /* The reset value of the ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE register field. */
751 #define ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_RESET 0x0
752 /* Extracts the ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE field value from a register. */
753 #define ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_GET(value) (((value) & 0x00000400) >> 10)
754 /* Produces a ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE register field value suitable for setting the register. */
755 #define ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_SET(value) (((value) << 10) & 0x00000400)
756 
757 /*
758  * Field : RSVD_BUS_CLEAR_FEATURE_CTRL
759  *
760  * Reserved bits - Read Only
761  *
762  * Field Access Macros:
763  *
764  */
765 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL register field. */
766 #define ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL_LSB 11
767 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL register field. */
768 #define ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL_MSB 11
769 /* The width in bits of the ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL register field. */
770 #define ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL_WIDTH 1
771 /* The mask used to set the ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL register field value. */
772 #define ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL_SET_MSK 0x00000800
773 /* The mask used to clear the ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL register field value. */
774 #define ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL_CLR_MSK 0xfffff7ff
775 /* The reset value of the ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL register field. */
776 #define ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL_RESET 0x0
777 /* Extracts the ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL field value from a register. */
778 #define ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL_GET(value) (((value) & 0x00000800) >> 11)
779 /* Produces a ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL register field value suitable for setting the register. */
780 #define ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL_SET(value) (((value) << 11) & 0x00000800)
781 
782 /*
783  * Field : RSVD_IC_CON_1
784  *
785  * Reserved bits - Read Only
786  *
787  * Field Access Macros:
788  *
789  */
790 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CON_RSVD_IC_CON_1 register field. */
791 #define ALT_I2C_IC_CON_RSVD_IC_CON_1_LSB 12
792 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CON_RSVD_IC_CON_1 register field. */
793 #define ALT_I2C_IC_CON_RSVD_IC_CON_1_MSB 15
794 /* The width in bits of the ALT_I2C_IC_CON_RSVD_IC_CON_1 register field. */
795 #define ALT_I2C_IC_CON_RSVD_IC_CON_1_WIDTH 4
796 /* The mask used to set the ALT_I2C_IC_CON_RSVD_IC_CON_1 register field value. */
797 #define ALT_I2C_IC_CON_RSVD_IC_CON_1_SET_MSK 0x0000f000
798 /* The mask used to clear the ALT_I2C_IC_CON_RSVD_IC_CON_1 register field value. */
799 #define ALT_I2C_IC_CON_RSVD_IC_CON_1_CLR_MSK 0xffff0fff
800 /* The reset value of the ALT_I2C_IC_CON_RSVD_IC_CON_1 register field. */
801 #define ALT_I2C_IC_CON_RSVD_IC_CON_1_RESET 0x0
802 /* Extracts the ALT_I2C_IC_CON_RSVD_IC_CON_1 field value from a register. */
803 #define ALT_I2C_IC_CON_RSVD_IC_CON_1_GET(value) (((value) & 0x0000f000) >> 12)
804 /* Produces a ALT_I2C_IC_CON_RSVD_IC_CON_1 register field value suitable for setting the register. */
805 #define ALT_I2C_IC_CON_RSVD_IC_CON_1_SET(value) (((value) << 12) & 0x0000f000)
806 
807 /*
808  * Field : RSVD_OPTIONAL_SAR_CTRL
809  *
810  * Reserved bits - Read Only
811  *
812  * Field Access Macros:
813  *
814  */
815 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL register field. */
816 #define ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL_LSB 16
817 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL register field. */
818 #define ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL_MSB 16
819 /* The width in bits of the ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL register field. */
820 #define ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL_WIDTH 1
821 /* The mask used to set the ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL register field value. */
822 #define ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL_SET_MSK 0x00010000
823 /* The mask used to clear the ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL register field value. */
824 #define ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL_CLR_MSK 0xfffeffff
825 /* The reset value of the ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL register field. */
826 #define ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL_RESET 0x0
827 /* Extracts the ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL field value from a register. */
828 #define ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL_GET(value) (((value) & 0x00010000) >> 16)
829 /* Produces a ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL register field value suitable for setting the register. */
830 #define ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL_SET(value) (((value) << 16) & 0x00010000)
831 
832 /*
833  * Field : RSVD_SMBUS_SLAVE_QUICK_EN
834  *
835  * Reserved bits - Read Only
836  *
837  * Field Access Macros:
838  *
839  */
840 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN register field. */
841 #define ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN_LSB 17
842 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN register field. */
843 #define ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN_MSB 17
844 /* The width in bits of the ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN register field. */
845 #define ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN_WIDTH 1
846 /* The mask used to set the ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN register field value. */
847 #define ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN_SET_MSK 0x00020000
848 /* The mask used to clear the ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN register field value. */
849 #define ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN_CLR_MSK 0xfffdffff
850 /* The reset value of the ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN register field. */
851 #define ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN_RESET 0x0
852 /* Extracts the ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN field value from a register. */
853 #define ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN_GET(value) (((value) & 0x00020000) >> 17)
854 /* Produces a ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN register field value suitable for setting the register. */
855 #define ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN_SET(value) (((value) << 17) & 0x00020000)
856 
857 /*
858  * Field : RSVD_SMBUS_ARP_EN
859  *
860  * Reserved bits - Read Only
861  *
862  * Field Access Macros:
863  *
864  */
865 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN register field. */
866 #define ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN_LSB 18
867 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN register field. */
868 #define ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN_MSB 18
869 /* The width in bits of the ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN register field. */
870 #define ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN_WIDTH 1
871 /* The mask used to set the ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN register field value. */
872 #define ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN_SET_MSK 0x00040000
873 /* The mask used to clear the ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN register field value. */
874 #define ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN_CLR_MSK 0xfffbffff
875 /* The reset value of the ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN register field. */
876 #define ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN_RESET 0x0
877 /* Extracts the ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN field value from a register. */
878 #define ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN_GET(value) (((value) & 0x00040000) >> 18)
879 /* Produces a ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN register field value suitable for setting the register. */
880 #define ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN_SET(value) (((value) << 18) & 0x00040000)
881 
882 /*
883  * Field : RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN
884  *
885  * Reserved bits - Read Only
886  *
887  * Field Access Macros:
888  *
889  */
890 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN register field. */
891 #define ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN_LSB 19
892 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN register field. */
893 #define ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN_MSB 19
894 /* The width in bits of the ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN register field. */
895 #define ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN_WIDTH 1
896 /* The mask used to set the ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN register field value. */
897 #define ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN_SET_MSK 0x00080000
898 /* The mask used to clear the ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN register field value. */
899 #define ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN_CLR_MSK 0xfff7ffff
900 /* The reset value of the ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN register field. */
901 #define ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN_RESET 0x0
902 /* Extracts the ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN field value from a register. */
903 #define ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN_GET(value) (((value) & 0x00080000) >> 19)
904 /* Produces a ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN register field value suitable for setting the register. */
905 #define ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN_SET(value) (((value) << 19) & 0x00080000)
906 
907 /*
908  * Field : RSVD_IC_CON_2
909  *
910  * Reserved bits - Read Only
911  *
912  * Field Access Macros:
913  *
914  */
915 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CON_RSVD_IC_CON_2 register field. */
916 #define ALT_I2C_IC_CON_RSVD_IC_CON_2_LSB 20
917 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CON_RSVD_IC_CON_2 register field. */
918 #define ALT_I2C_IC_CON_RSVD_IC_CON_2_MSB 31
919 /* The width in bits of the ALT_I2C_IC_CON_RSVD_IC_CON_2 register field. */
920 #define ALT_I2C_IC_CON_RSVD_IC_CON_2_WIDTH 12
921 /* The mask used to set the ALT_I2C_IC_CON_RSVD_IC_CON_2 register field value. */
922 #define ALT_I2C_IC_CON_RSVD_IC_CON_2_SET_MSK 0xfff00000
923 /* The mask used to clear the ALT_I2C_IC_CON_RSVD_IC_CON_2 register field value. */
924 #define ALT_I2C_IC_CON_RSVD_IC_CON_2_CLR_MSK 0x000fffff
925 /* The reset value of the ALT_I2C_IC_CON_RSVD_IC_CON_2 register field. */
926 #define ALT_I2C_IC_CON_RSVD_IC_CON_2_RESET 0x0
927 /* Extracts the ALT_I2C_IC_CON_RSVD_IC_CON_2 field value from a register. */
928 #define ALT_I2C_IC_CON_RSVD_IC_CON_2_GET(value) (((value) & 0xfff00000) >> 20)
929 /* Produces a ALT_I2C_IC_CON_RSVD_IC_CON_2 register field value suitable for setting the register. */
930 #define ALT_I2C_IC_CON_RSVD_IC_CON_2_SET(value) (((value) << 20) & 0xfff00000)
931 
932 #ifndef __ASSEMBLY__
933 /*
934  * WARNING: The C register and register group struct declarations are provided for
935  * convenience and illustrative purposes. They should, however, be used with
936  * caution as the C language standard provides no guarantees about the alignment or
937  * atomicity of device memory accesses. The recommended practice for coding device
938  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
939  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
940  * alt_write_dword() functions for 64 bit registers.
941  *
942  * The struct declaration for register ALT_I2C_IC_CON.
943  */
944 struct ALT_I2C_IC_CON_s
945 {
946  volatile uint32_t MASTER_MODE : 1; /* ALT_I2C_IC_CON_MASTER_MODE */
947  volatile uint32_t SPEED : 2; /* ALT_I2C_IC_CON_SPEED */
948  volatile uint32_t IC_10BITADDR_SLAVE : 1; /* ALT_I2C_IC_CON_IC_10BITADDR_SLAVE */
949  const volatile uint32_t IC_10BITADDR_MASTER_rd_only : 1; /* ALT_I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY */
950  volatile uint32_t IC_RESTART_EN : 1; /* ALT_I2C_IC_CON_IC_RESTART_EN */
951  volatile uint32_t IC_SLAVE_DISABLE : 1; /* ALT_I2C_IC_CON_IC_SLAVE_DISABLE */
952  volatile uint32_t STOP_DET_IFADDRESSED : 1; /* ALT_I2C_IC_CON_STOP_DET_IFADDRESSED */
953  volatile uint32_t TX_EMPTY_CTRL : 1; /* ALT_I2C_IC_CON_TX_EMPTY_CTRL */
954  const volatile uint32_t RX_FIFO_FULL_HLD_CTRL : 1; /* ALT_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL */
955  const volatile uint32_t STOP_DET_IF_MASTER_ACTIVE : 1; /* ALT_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE */
956  const volatile uint32_t RSVD_BUS_CLEAR_FEATURE_CTRL : 1; /* ALT_I2C_IC_CON_RSVD_BUS_CLEAR_FEATURE_CTRL */
957  const volatile uint32_t RSVD_IC_CON_1 : 4; /* ALT_I2C_IC_CON_RSVD_IC_CON_1 */
958  const volatile uint32_t RSVD_OPTIONAL_SAR_CTRL : 1; /* ALT_I2C_IC_CON_RSVD_OPTIONAL_SAR_CTRL */
959  const volatile uint32_t RSVD_SMBUS_SLAVE_QUICK_EN : 1; /* ALT_I2C_IC_CON_RSVD_SMBUS_SLAVE_QUICK_EN */
960  const volatile uint32_t RSVD_SMBUS_ARP_EN : 1; /* ALT_I2C_IC_CON_RSVD_SMBUS_ARP_EN */
961  const volatile uint32_t RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN : 1; /* ALT_I2C_IC_CON_RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN */
962  const volatile uint32_t RSVD_IC_CON_2 : 12; /* ALT_I2C_IC_CON_RSVD_IC_CON_2 */
963 };
964 
965 /* The typedef declaration for register ALT_I2C_IC_CON. */
966 typedef struct ALT_I2C_IC_CON_s ALT_I2C_IC_CON_t;
967 #endif /* __ASSEMBLY__ */
968 
969 /* The reset value of the ALT_I2C_IC_CON register. */
970 #define ALT_I2C_IC_CON_RESET 0x0000007d
971 /* The byte offset of the ALT_I2C_IC_CON register from the beginning of the component. */
972 #define ALT_I2C_IC_CON_OFST 0x0
973 /* The address of the ALT_I2C_IC_CON register. */
974 #define ALT_I2C_IC_CON_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CON_OFST))
975 
976 /*
977  * Register : I2C Target Address Register - IC_TAR
978  *
979  * Name: I2C Target Address Register
980  *
981  * Size: 12 bits; when I2C_DYNAMIC_TAR_UPDATE = 0 and IC_DEVICE_ID = 0
982  *
983  * 13 bits; when I2C_DYNAMIC_TAR_UPDATE = 1 and IC_DEVICE_ID = 0
984  *
985  * 14 bits; when IC_DEVICE_ID=1 irrespective of I2C_DYNAMIC_TAR_UPDATE is set.
986  *
987  * 17 bits; when IC_SMBUS=1
988  *
989  * Address Offset: 0x04
990  *
991  * Read/Write Access: Read/Write
992  *
993  * If the configuration parameter I2C_DYNAMIC_TAR_UPDATE is set to 'No' (0),
994  *
995  * this register is 12 bits wide, and bits 31:12 are reserved. This register
996  *
997  * can be written to only when IC_ENABLE[0] is set to 0.
998  *
999  * However, if I2C_DYNAMIC_TAR_UPDATE = 1, then the register becomes 13 bits wide.
1000  *
1001  * All bits can be dynamically updated as long as any set of the following
1002  *
1003  * conditions are true:
1004  *
1005  * * DW_apb_i2c is NOT enabled (IC_ENABLE[0] is set to 0);
1006  *
1007  * or
1008  *
1009  * * DW_apb_i2c is enabled (IC_ENABLE[0]=1);
1010  *
1011  * AND
1012  *
1013  * DW_apb_i2c is NOT engaged in any Master (tx, rx) operation (IC_STATUS[5]=0);
1014  *
1015  * AND
1016  *
1017  * DW_apb_i2c is enabled to operate in Master mode (IC_CON[0]=1);
1018  *
1019  * AND
1020  *
1021  * there are NO entries in the TX FIFO (IC_STATUS[2]=1)
1022  *
1023  * Register Layout
1024  *
1025  * Bits | Access | Reset | Description
1026  * :--------|:-------|:------|:------------------------------------
1027  * [9:0] | RW | 0x55 | ALT_I2C_IC_TAR_IC_TAR
1028  * [10] | RW | 0x0 | ALT_I2C_IC_TAR_GC_OR_START
1029  * [11] | RW | 0x0 | ALT_I2C_IC_TAR_SPECIAL
1030  * [12] | RW | 0x1 | ALT_I2C_IC_TAR_IC_10BITADDR_MASTER
1031  * [13] | R | 0x0 | ALT_I2C_IC_TAR_RSVD_DEVICE_ID
1032  * [15:14] | R | 0x0 | ALT_I2C_IC_TAR_RSVD_IC_TAR_1
1033  * [16] | R | 0x0 | ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD
1034  * [31:17] | R | 0x0 | ALT_I2C_IC_TAR_RSVD_IC_TAR_2
1035  *
1036  */
1037 /*
1038  * Field : IC_TAR
1039  *
1040  * This is the target address for any master transaction. When
1041  *
1042  * transmitting a General Call, these bits are ignored. To generate a
1043  *
1044  * START BYTE, the CPU needs to write only once into these bits.
1045  *
1046  * Reset value: IC_DEFAULT_TAR_SLAVE_ADDR configuration
1047  *
1048  * parameter
1049  *
1050  * If the IC_TAR and IC_SAR are the same, loopback exists but the
1051  *
1052  * FIFOs are shared between master and slave, so full loopback is
1053  *
1054  * not feasible. Only one direction loopback mode is supported
1055  *
1056  * (simplex), not duplex. A master cannot transmit to itself; it can
1057  *
1058  * transmit to only a slave.
1059  *
1060  * Field Access Macros:
1061  *
1062  */
1063 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TAR_IC_TAR register field. */
1064 #define ALT_I2C_IC_TAR_IC_TAR_LSB 0
1065 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TAR_IC_TAR register field. */
1066 #define ALT_I2C_IC_TAR_IC_TAR_MSB 9
1067 /* The width in bits of the ALT_I2C_IC_TAR_IC_TAR register field. */
1068 #define ALT_I2C_IC_TAR_IC_TAR_WIDTH 10
1069 /* The mask used to set the ALT_I2C_IC_TAR_IC_TAR register field value. */
1070 #define ALT_I2C_IC_TAR_IC_TAR_SET_MSK 0x000003ff
1071 /* The mask used to clear the ALT_I2C_IC_TAR_IC_TAR register field value. */
1072 #define ALT_I2C_IC_TAR_IC_TAR_CLR_MSK 0xfffffc00
1073 /* The reset value of the ALT_I2C_IC_TAR_IC_TAR register field. */
1074 #define ALT_I2C_IC_TAR_IC_TAR_RESET 0x55
1075 /* Extracts the ALT_I2C_IC_TAR_IC_TAR field value from a register. */
1076 #define ALT_I2C_IC_TAR_IC_TAR_GET(value) (((value) & 0x000003ff) >> 0)
1077 /* Produces a ALT_I2C_IC_TAR_IC_TAR register field value suitable for setting the register. */
1078 #define ALT_I2C_IC_TAR_IC_TAR_SET(value) (((value) << 0) & 0x000003ff)
1079 
1080 /*
1081  * Field : GC_OR_START
1082  *
1083  * If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit
1084  * indicates whether a
1085  *
1086  * General Call or START byte command is to be performed by the
1087  *
1088  * DW_apb_i2c.
1089  *
1090  * 0: General Call Address after issuing a General Call, only writes
1091  *
1092  * may be performed. Attempting to issue a read command results in
1093  *
1094  * setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.
1095  *
1096  * The DW_apb_i2c remains in General Call mode until the
1097  *
1098  * SPECIAL bit value (bit 11) is cleared.
1099  *
1100  * 1: START BYTE
1101  *
1102  * Reset value: 0x0
1103  *
1104  * Field Enumeration Values:
1105  *
1106  * Enum | Value | Description
1107  * :------------------------------------------|:------|:-------------------------------
1108  * ALT_I2C_IC_TAR_GC_OR_START_E_GENERAL_CALL | 0x0 | GENERAL_CALL byte transmission
1109  * ALT_I2C_IC_TAR_GC_OR_START_E_START_BYTE | 0x1 | START byte transmission
1110  *
1111  * Field Access Macros:
1112  *
1113  */
1114 /*
1115  * Enumerated value for register field ALT_I2C_IC_TAR_GC_OR_START
1116  *
1117  * GENERAL_CALL byte transmission
1118  */
1119 #define ALT_I2C_IC_TAR_GC_OR_START_E_GENERAL_CALL 0x0
1120 /*
1121  * Enumerated value for register field ALT_I2C_IC_TAR_GC_OR_START
1122  *
1123  * START byte transmission
1124  */
1125 #define ALT_I2C_IC_TAR_GC_OR_START_E_START_BYTE 0x1
1126 
1127 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TAR_GC_OR_START register field. */
1128 #define ALT_I2C_IC_TAR_GC_OR_START_LSB 10
1129 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TAR_GC_OR_START register field. */
1130 #define ALT_I2C_IC_TAR_GC_OR_START_MSB 10
1131 /* The width in bits of the ALT_I2C_IC_TAR_GC_OR_START register field. */
1132 #define ALT_I2C_IC_TAR_GC_OR_START_WIDTH 1
1133 /* The mask used to set the ALT_I2C_IC_TAR_GC_OR_START register field value. */
1134 #define ALT_I2C_IC_TAR_GC_OR_START_SET_MSK 0x00000400
1135 /* The mask used to clear the ALT_I2C_IC_TAR_GC_OR_START register field value. */
1136 #define ALT_I2C_IC_TAR_GC_OR_START_CLR_MSK 0xfffffbff
1137 /* The reset value of the ALT_I2C_IC_TAR_GC_OR_START register field. */
1138 #define ALT_I2C_IC_TAR_GC_OR_START_RESET 0x0
1139 /* Extracts the ALT_I2C_IC_TAR_GC_OR_START field value from a register. */
1140 #define ALT_I2C_IC_TAR_GC_OR_START_GET(value) (((value) & 0x00000400) >> 10)
1141 /* Produces a ALT_I2C_IC_TAR_GC_OR_START register field value suitable for setting the register. */
1142 #define ALT_I2C_IC_TAR_GC_OR_START_SET(value) (((value) << 10) & 0x00000400)
1143 
1144 /*
1145  * Field : SPECIAL
1146  *
1147  * This bit indicates whether software performs a Device-ID or General Call or
1148  *
1149  * START BYTE command.
1150  *
1151  * 0: ignore bit 10 GC_OR_START and use IC_TAR normally
1152  *
1153  * 1: perform special I2C command as specified in Device_ID or GC_OR_START
1154  *
1155  * bit
1156  *
1157  * Reset value: 0x0
1158  *
1159  * Field Enumeration Values:
1160  *
1161  * Enum | Value | Description
1162  * :----------------------------------|:------|:----------------------------------------
1163  * ALT_I2C_IC_TAR_SPECIAL_E_DISABLED | 0x0 | Disables programming of GENERAL_CALL or
1164  * : | | START_BYTE transmission
1165  * ALT_I2C_IC_TAR_SPECIAL_E_ENABLED | 0x1 | Enables programming of GENERAL_CALL or
1166  * : | | START_BYTE transmission
1167  *
1168  * Field Access Macros:
1169  *
1170  */
1171 /*
1172  * Enumerated value for register field ALT_I2C_IC_TAR_SPECIAL
1173  *
1174  * Disables programming of GENERAL_CALL or START_BYTE transmission
1175  */
1176 #define ALT_I2C_IC_TAR_SPECIAL_E_DISABLED 0x0
1177 /*
1178  * Enumerated value for register field ALT_I2C_IC_TAR_SPECIAL
1179  *
1180  * Enables programming of GENERAL_CALL or START_BYTE transmission
1181  */
1182 #define ALT_I2C_IC_TAR_SPECIAL_E_ENABLED 0x1
1183 
1184 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TAR_SPECIAL register field. */
1185 #define ALT_I2C_IC_TAR_SPECIAL_LSB 11
1186 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TAR_SPECIAL register field. */
1187 #define ALT_I2C_IC_TAR_SPECIAL_MSB 11
1188 /* The width in bits of the ALT_I2C_IC_TAR_SPECIAL register field. */
1189 #define ALT_I2C_IC_TAR_SPECIAL_WIDTH 1
1190 /* The mask used to set the ALT_I2C_IC_TAR_SPECIAL register field value. */
1191 #define ALT_I2C_IC_TAR_SPECIAL_SET_MSK 0x00000800
1192 /* The mask used to clear the ALT_I2C_IC_TAR_SPECIAL register field value. */
1193 #define ALT_I2C_IC_TAR_SPECIAL_CLR_MSK 0xfffff7ff
1194 /* The reset value of the ALT_I2C_IC_TAR_SPECIAL register field. */
1195 #define ALT_I2C_IC_TAR_SPECIAL_RESET 0x0
1196 /* Extracts the ALT_I2C_IC_TAR_SPECIAL field value from a register. */
1197 #define ALT_I2C_IC_TAR_SPECIAL_GET(value) (((value) & 0x00000800) >> 11)
1198 /* Produces a ALT_I2C_IC_TAR_SPECIAL register field value suitable for setting the register. */
1199 #define ALT_I2C_IC_TAR_SPECIAL_SET(value) (((value) << 11) & 0x00000800)
1200 
1201 /*
1202  * Field : IC_10BITADDR_MASTER
1203  *
1204  * This bit controls whether the DW_apb_i2c starts its transfers in 7-
1205  *
1206  * or 10-bit addressing mode when acting as a master.
1207  *
1208  * 0: 7-bit addressing
1209  *
1210  * 1: 10-bit addressing
1211  *
1212  * Dependencies: This bit exists in this register only if the
1213  *
1214  * I2C_DYNAMIC_TAR_UPDATE configuration parameter is set
1215  *
1216  * to 'Yes' (1).
1217  *
1218  * Reset value: IC_10BITADDR_MASTER configuration
1219  *
1220  * parameter
1221  *
1222  * Field Enumeration Values:
1223  *
1224  * Enum | Value | Description
1225  * :-------------------------------------------------|:------|:----------------------------------
1226  * ALT_I2C_IC_TAR_IC_10BITADDR_MASTER_E_ADDR_7BITS | 0x0 | Address 7Bit transmission format
1227  * ALT_I2C_IC_TAR_IC_10BITADDR_MASTER_E_ADDR_10BITS | 0x1 | Address 10Bit transmission format
1228  *
1229  * Field Access Macros:
1230  *
1231  */
1232 /*
1233  * Enumerated value for register field ALT_I2C_IC_TAR_IC_10BITADDR_MASTER
1234  *
1235  * Address 7Bit transmission format
1236  */
1237 #define ALT_I2C_IC_TAR_IC_10BITADDR_MASTER_E_ADDR_7BITS 0x0
1238 /*
1239  * Enumerated value for register field ALT_I2C_IC_TAR_IC_10BITADDR_MASTER
1240  *
1241  * Address 10Bit transmission format
1242  */
1243 #define ALT_I2C_IC_TAR_IC_10BITADDR_MASTER_E_ADDR_10BITS 0x1
1244 
1245 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TAR_IC_10BITADDR_MASTER register field. */
1246 #define ALT_I2C_IC_TAR_IC_10BITADDR_MASTER_LSB 12
1247 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TAR_IC_10BITADDR_MASTER register field. */
1248 #define ALT_I2C_IC_TAR_IC_10BITADDR_MASTER_MSB 12
1249 /* The width in bits of the ALT_I2C_IC_TAR_IC_10BITADDR_MASTER register field. */
1250 #define ALT_I2C_IC_TAR_IC_10BITADDR_MASTER_WIDTH 1
1251 /* The mask used to set the ALT_I2C_IC_TAR_IC_10BITADDR_MASTER register field value. */
1252 #define ALT_I2C_IC_TAR_IC_10BITADDR_MASTER_SET_MSK 0x00001000
1253 /* The mask used to clear the ALT_I2C_IC_TAR_IC_10BITADDR_MASTER register field value. */
1254 #define ALT_I2C_IC_TAR_IC_10BITADDR_MASTER_CLR_MSK 0xffffefff
1255 /* The reset value of the ALT_I2C_IC_TAR_IC_10BITADDR_MASTER register field. */
1256 #define ALT_I2C_IC_TAR_IC_10BITADDR_MASTER_RESET 0x1
1257 /* Extracts the ALT_I2C_IC_TAR_IC_10BITADDR_MASTER field value from a register. */
1258 #define ALT_I2C_IC_TAR_IC_10BITADDR_MASTER_GET(value) (((value) & 0x00001000) >> 12)
1259 /* Produces a ALT_I2C_IC_TAR_IC_10BITADDR_MASTER register field value suitable for setting the register. */
1260 #define ALT_I2C_IC_TAR_IC_10BITADDR_MASTER_SET(value) (((value) << 12) & 0x00001000)
1261 
1262 /*
1263  * Field : RSVD_DEVICE_ID
1264  *
1265  * Reserved bits - Read Only
1266  *
1267  * Field Access Macros:
1268  *
1269  */
1270 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TAR_RSVD_DEVICE_ID register field. */
1271 #define ALT_I2C_IC_TAR_RSVD_DEVICE_ID_LSB 13
1272 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TAR_RSVD_DEVICE_ID register field. */
1273 #define ALT_I2C_IC_TAR_RSVD_DEVICE_ID_MSB 13
1274 /* The width in bits of the ALT_I2C_IC_TAR_RSVD_DEVICE_ID register field. */
1275 #define ALT_I2C_IC_TAR_RSVD_DEVICE_ID_WIDTH 1
1276 /* The mask used to set the ALT_I2C_IC_TAR_RSVD_DEVICE_ID register field value. */
1277 #define ALT_I2C_IC_TAR_RSVD_DEVICE_ID_SET_MSK 0x00002000
1278 /* The mask used to clear the ALT_I2C_IC_TAR_RSVD_DEVICE_ID register field value. */
1279 #define ALT_I2C_IC_TAR_RSVD_DEVICE_ID_CLR_MSK 0xffffdfff
1280 /* The reset value of the ALT_I2C_IC_TAR_RSVD_DEVICE_ID register field. */
1281 #define ALT_I2C_IC_TAR_RSVD_DEVICE_ID_RESET 0x0
1282 /* Extracts the ALT_I2C_IC_TAR_RSVD_DEVICE_ID field value from a register. */
1283 #define ALT_I2C_IC_TAR_RSVD_DEVICE_ID_GET(value) (((value) & 0x00002000) >> 13)
1284 /* Produces a ALT_I2C_IC_TAR_RSVD_DEVICE_ID register field value suitable for setting the register. */
1285 #define ALT_I2C_IC_TAR_RSVD_DEVICE_ID_SET(value) (((value) << 13) & 0x00002000)
1286 
1287 /*
1288  * Field : RSVD_IC_TAR_1
1289  *
1290  * Reserved bits - Read Only
1291  *
1292  * Field Access Macros:
1293  *
1294  */
1295 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TAR_RSVD_IC_TAR_1 register field. */
1296 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_1_LSB 14
1297 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TAR_RSVD_IC_TAR_1 register field. */
1298 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_1_MSB 15
1299 /* The width in bits of the ALT_I2C_IC_TAR_RSVD_IC_TAR_1 register field. */
1300 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_1_WIDTH 2
1301 /* The mask used to set the ALT_I2C_IC_TAR_RSVD_IC_TAR_1 register field value. */
1302 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_1_SET_MSK 0x0000c000
1303 /* The mask used to clear the ALT_I2C_IC_TAR_RSVD_IC_TAR_1 register field value. */
1304 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_1_CLR_MSK 0xffff3fff
1305 /* The reset value of the ALT_I2C_IC_TAR_RSVD_IC_TAR_1 register field. */
1306 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_1_RESET 0x0
1307 /* Extracts the ALT_I2C_IC_TAR_RSVD_IC_TAR_1 field value from a register. */
1308 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_1_GET(value) (((value) & 0x0000c000) >> 14)
1309 /* Produces a ALT_I2C_IC_TAR_RSVD_IC_TAR_1 register field value suitable for setting the register. */
1310 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_1_SET(value) (((value) << 14) & 0x0000c000)
1311 
1312 /*
1313  * Field : RSVD_SMBUS_QUICK_CMD
1314  *
1315  * Reserved bits - Read Only
1316  *
1317  * Field Access Macros:
1318  *
1319  */
1320 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD register field. */
1321 #define ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD_LSB 16
1322 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD register field. */
1323 #define ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD_MSB 16
1324 /* The width in bits of the ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD register field. */
1325 #define ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD_WIDTH 1
1326 /* The mask used to set the ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD register field value. */
1327 #define ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD_SET_MSK 0x00010000
1328 /* The mask used to clear the ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD register field value. */
1329 #define ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD_CLR_MSK 0xfffeffff
1330 /* The reset value of the ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD register field. */
1331 #define ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD_RESET 0x0
1332 /* Extracts the ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD field value from a register. */
1333 #define ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD_GET(value) (((value) & 0x00010000) >> 16)
1334 /* Produces a ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD register field value suitable for setting the register. */
1335 #define ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD_SET(value) (((value) << 16) & 0x00010000)
1336 
1337 /*
1338  * Field : RSVD_IC_TAR_2
1339  *
1340  * Reserved bits - Read Only
1341  *
1342  * Field Access Macros:
1343  *
1344  */
1345 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TAR_RSVD_IC_TAR_2 register field. */
1346 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_2_LSB 17
1347 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TAR_RSVD_IC_TAR_2 register field. */
1348 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_2_MSB 31
1349 /* The width in bits of the ALT_I2C_IC_TAR_RSVD_IC_TAR_2 register field. */
1350 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_2_WIDTH 15
1351 /* The mask used to set the ALT_I2C_IC_TAR_RSVD_IC_TAR_2 register field value. */
1352 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_2_SET_MSK 0xfffe0000
1353 /* The mask used to clear the ALT_I2C_IC_TAR_RSVD_IC_TAR_2 register field value. */
1354 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_2_CLR_MSK 0x0001ffff
1355 /* The reset value of the ALT_I2C_IC_TAR_RSVD_IC_TAR_2 register field. */
1356 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_2_RESET 0x0
1357 /* Extracts the ALT_I2C_IC_TAR_RSVD_IC_TAR_2 field value from a register. */
1358 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_2_GET(value) (((value) & 0xfffe0000) >> 17)
1359 /* Produces a ALT_I2C_IC_TAR_RSVD_IC_TAR_2 register field value suitable for setting the register. */
1360 #define ALT_I2C_IC_TAR_RSVD_IC_TAR_2_SET(value) (((value) << 17) & 0xfffe0000)
1361 
1362 #ifndef __ASSEMBLY__
1363 /*
1364  * WARNING: The C register and register group struct declarations are provided for
1365  * convenience and illustrative purposes. They should, however, be used with
1366  * caution as the C language standard provides no guarantees about the alignment or
1367  * atomicity of device memory accesses. The recommended practice for coding device
1368  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1369  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1370  * alt_write_dword() functions for 64 bit registers.
1371  *
1372  * The struct declaration for register ALT_I2C_IC_TAR.
1373  */
1374 struct ALT_I2C_IC_TAR_s
1375 {
1376  volatile uint32_t IC_TAR : 10; /* ALT_I2C_IC_TAR_IC_TAR */
1377  volatile uint32_t GC_OR_START : 1; /* ALT_I2C_IC_TAR_GC_OR_START */
1378  volatile uint32_t SPECIAL : 1; /* ALT_I2C_IC_TAR_SPECIAL */
1379  volatile uint32_t IC_10BITADDR_MASTER : 1; /* ALT_I2C_IC_TAR_IC_10BITADDR_MASTER */
1380  const volatile uint32_t RSVD_DEVICE_ID : 1; /* ALT_I2C_IC_TAR_RSVD_DEVICE_ID */
1381  const volatile uint32_t RSVD_IC_TAR_1 : 2; /* ALT_I2C_IC_TAR_RSVD_IC_TAR_1 */
1382  const volatile uint32_t RSVD_SMBUS_QUICK_CMD : 1; /* ALT_I2C_IC_TAR_RSVD_SMBUS_QUICK_CMD */
1383  const volatile uint32_t RSVD_IC_TAR_2 : 15; /* ALT_I2C_IC_TAR_RSVD_IC_TAR_2 */
1384 };
1385 
1386 /* The typedef declaration for register ALT_I2C_IC_TAR. */
1387 typedef struct ALT_I2C_IC_TAR_s ALT_I2C_IC_TAR_t;
1388 #endif /* __ASSEMBLY__ */
1389 
1390 /* The reset value of the ALT_I2C_IC_TAR register. */
1391 #define ALT_I2C_IC_TAR_RESET 0x00001055
1392 /* The byte offset of the ALT_I2C_IC_TAR register from the beginning of the component. */
1393 #define ALT_I2C_IC_TAR_OFST 0x4
1394 /* The address of the ALT_I2C_IC_TAR register. */
1395 #define ALT_I2C_IC_TAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_TAR_OFST))
1396 
1397 /*
1398  * Register : I2C Slave Address Register - IC_SAR
1399  *
1400  * Name: I2C Slave Address Register
1401  *
1402  * Size: 10 bits
1403  *
1404  * Address Offset: 0x08
1405  *
1406  * Read/Write Access: Read/Write
1407  *
1408  * Register Layout
1409  *
1410  * Bits | Access | Reset | Description
1411  * :--------|:-------|:------|:---------------------------
1412  * [9:0] | RW | 0x55 | ALT_I2C_IC_SAR_IC_SAR
1413  * [31:10] | R | 0x0 | ALT_I2C_IC_SAR_RSVD_IC_SAR
1414  *
1415  */
1416 /*
1417  * Field : IC_SAR
1418  *
1419  * The IC_SAR holds the slave address when the I2C is operating as a slave. For
1420  * 7-bit
1421  *
1422  * addressing, only IC_SAR[6:0] is used.
1423  *
1424  * This register can be written only when the I2C interface is disabled, which
1425  *
1426  * corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times
1427  * have
1428  *
1429  * no effect.
1430  *
1431  * Note
1432  *
1433  * The default values cannot be any of the reserved address locations:
1434  *
1435  * that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the
1436  *
1437  * device is not guaranteed if you program the IC_SAR or IC_TAR to
1438  *
1439  * a reserved value.
1440  *
1441  * Reset value: IC_DEFAULT_SLAVE_ADDR configuration parameter
1442  *
1443  * Field Access Macros:
1444  *
1445  */
1446 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_SAR_IC_SAR register field. */
1447 #define ALT_I2C_IC_SAR_IC_SAR_LSB 0
1448 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_SAR_IC_SAR register field. */
1449 #define ALT_I2C_IC_SAR_IC_SAR_MSB 9
1450 /* The width in bits of the ALT_I2C_IC_SAR_IC_SAR register field. */
1451 #define ALT_I2C_IC_SAR_IC_SAR_WIDTH 10
1452 /* The mask used to set the ALT_I2C_IC_SAR_IC_SAR register field value. */
1453 #define ALT_I2C_IC_SAR_IC_SAR_SET_MSK 0x000003ff
1454 /* The mask used to clear the ALT_I2C_IC_SAR_IC_SAR register field value. */
1455 #define ALT_I2C_IC_SAR_IC_SAR_CLR_MSK 0xfffffc00
1456 /* The reset value of the ALT_I2C_IC_SAR_IC_SAR register field. */
1457 #define ALT_I2C_IC_SAR_IC_SAR_RESET 0x55
1458 /* Extracts the ALT_I2C_IC_SAR_IC_SAR field value from a register. */
1459 #define ALT_I2C_IC_SAR_IC_SAR_GET(value) (((value) & 0x000003ff) >> 0)
1460 /* Produces a ALT_I2C_IC_SAR_IC_SAR register field value suitable for setting the register. */
1461 #define ALT_I2C_IC_SAR_IC_SAR_SET(value) (((value) << 0) & 0x000003ff)
1462 
1463 /*
1464  * Field : RSVD_IC_SAR
1465  *
1466  * Reserved bits - Read Only
1467  *
1468  * Field Access Macros:
1469  *
1470  */
1471 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_SAR_RSVD_IC_SAR register field. */
1472 #define ALT_I2C_IC_SAR_RSVD_IC_SAR_LSB 10
1473 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_SAR_RSVD_IC_SAR register field. */
1474 #define ALT_I2C_IC_SAR_RSVD_IC_SAR_MSB 31
1475 /* The width in bits of the ALT_I2C_IC_SAR_RSVD_IC_SAR register field. */
1476 #define ALT_I2C_IC_SAR_RSVD_IC_SAR_WIDTH 22
1477 /* The mask used to set the ALT_I2C_IC_SAR_RSVD_IC_SAR register field value. */
1478 #define ALT_I2C_IC_SAR_RSVD_IC_SAR_SET_MSK 0xfffffc00
1479 /* The mask used to clear the ALT_I2C_IC_SAR_RSVD_IC_SAR register field value. */
1480 #define ALT_I2C_IC_SAR_RSVD_IC_SAR_CLR_MSK 0x000003ff
1481 /* The reset value of the ALT_I2C_IC_SAR_RSVD_IC_SAR register field. */
1482 #define ALT_I2C_IC_SAR_RSVD_IC_SAR_RESET 0x0
1483 /* Extracts the ALT_I2C_IC_SAR_RSVD_IC_SAR field value from a register. */
1484 #define ALT_I2C_IC_SAR_RSVD_IC_SAR_GET(value) (((value) & 0xfffffc00) >> 10)
1485 /* Produces a ALT_I2C_IC_SAR_RSVD_IC_SAR register field value suitable for setting the register. */
1486 #define ALT_I2C_IC_SAR_RSVD_IC_SAR_SET(value) (((value) << 10) & 0xfffffc00)
1487 
1488 #ifndef __ASSEMBLY__
1489 /*
1490  * WARNING: The C register and register group struct declarations are provided for
1491  * convenience and illustrative purposes. They should, however, be used with
1492  * caution as the C language standard provides no guarantees about the alignment or
1493  * atomicity of device memory accesses. The recommended practice for coding device
1494  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1495  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1496  * alt_write_dword() functions for 64 bit registers.
1497  *
1498  * The struct declaration for register ALT_I2C_IC_SAR.
1499  */
1500 struct ALT_I2C_IC_SAR_s
1501 {
1502  volatile uint32_t IC_SAR : 10; /* ALT_I2C_IC_SAR_IC_SAR */
1503  const volatile uint32_t RSVD_IC_SAR : 22; /* ALT_I2C_IC_SAR_RSVD_IC_SAR */
1504 };
1505 
1506 /* The typedef declaration for register ALT_I2C_IC_SAR. */
1507 typedef struct ALT_I2C_IC_SAR_s ALT_I2C_IC_SAR_t;
1508 #endif /* __ASSEMBLY__ */
1509 
1510 /* The reset value of the ALT_I2C_IC_SAR register. */
1511 #define ALT_I2C_IC_SAR_RESET 0x00000055
1512 /* The byte offset of the ALT_I2C_IC_SAR register from the beginning of the component. */
1513 #define ALT_I2C_IC_SAR_OFST 0x8
1514 /* The address of the ALT_I2C_IC_SAR register. */
1515 #define ALT_I2C_IC_SAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_SAR_OFST))
1516 
1517 /*
1518  * Register : I2C Rx/Tx Data Buffer and Command Register - IC_DATA_CMD
1519  *
1520  * Name: I2C Rx/Tx Data Buffer and Command Register;
1521  *
1522  * this is the register the CPU writes to when
1523  *
1524  * filling the TX FIFO and the CPU reads from when
1525  *
1526  * retrieving bytes from RX FIFO
1527  *
1528  * Size:
1529  *
1530  * Write
1531  *
1532  * 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1
1533  *
1534  * 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0
1535  *
1536  * Read
1537  *
1538  * 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1
1539  *
1540  * 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0
1541  *
1542  * Address Offset: 0x10
1543  *
1544  * Read/Write Access: Read/Write
1545  *
1546  * NOTE: With nine bits required for writes,
1547  *
1548  * the DW_apb_i2c requires 16-bit data on the
1549  *
1550  * APB bus transfers when writing into the
1551  *
1552  * transmit FIFO. Eight-bit transfers remain for
1553  *
1554  * reads from the receive FIFO.
1555  *
1556  * Register Layout
1557  *
1558  * Bits | Access | Reset | Description
1559  * :--------|:-------|:------|:-------------------------------------
1560  * [7:0] | RW | 0x0 | ALT_I2C_IC_DATA_CMD_DAT
1561  * [8] | W | 0x0 | ALT_I2C_IC_DATA_CMD_CMD
1562  * [9] | W | 0x0 | ALT_I2C_IC_DATA_CMD_STOP
1563  * [10] | W | 0x0 | ALT_I2C_IC_DATA_CMD_RESTART
1564  * [11] | R | 0x0 | ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE
1565  * [31:12] | R | 0x0 | ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD
1566  *
1567  */
1568 /*
1569  * Field : DAT
1570  *
1571  * This register contains the data to be transmitted or received on the I2C bus.
1572  *
1573  * If you are writing to this register and want to perform a read,
1574  *
1575  * bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read
1576  *
1577  * this register, these bits return the value of data received on the
1578  *
1579  * DW_apb_i2c interface.
1580  *
1581  * Reset value: 0x0
1582  *
1583  * Field Access Macros:
1584  *
1585  */
1586 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_DATA_CMD_DAT register field. */
1587 #define ALT_I2C_IC_DATA_CMD_DAT_LSB 0
1588 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_DATA_CMD_DAT register field. */
1589 #define ALT_I2C_IC_DATA_CMD_DAT_MSB 7
1590 /* The width in bits of the ALT_I2C_IC_DATA_CMD_DAT register field. */
1591 #define ALT_I2C_IC_DATA_CMD_DAT_WIDTH 8
1592 /* The mask used to set the ALT_I2C_IC_DATA_CMD_DAT register field value. */
1593 #define ALT_I2C_IC_DATA_CMD_DAT_SET_MSK 0x000000ff
1594 /* The mask used to clear the ALT_I2C_IC_DATA_CMD_DAT register field value. */
1595 #define ALT_I2C_IC_DATA_CMD_DAT_CLR_MSK 0xffffff00
1596 /* The reset value of the ALT_I2C_IC_DATA_CMD_DAT register field. */
1597 #define ALT_I2C_IC_DATA_CMD_DAT_RESET 0x0
1598 /* Extracts the ALT_I2C_IC_DATA_CMD_DAT field value from a register. */
1599 #define ALT_I2C_IC_DATA_CMD_DAT_GET(value) (((value) & 0x000000ff) >> 0)
1600 /* Produces a ALT_I2C_IC_DATA_CMD_DAT register field value suitable for setting the register. */
1601 #define ALT_I2C_IC_DATA_CMD_DAT_SET(value) (((value) << 0) & 0x000000ff)
1602 
1603 /*
1604  * Field : CMD
1605  *
1606  * This bit controls whether a read or a write is performed.
1607  *
1608  * This bit does not control the direction when the DW_apb_i2c
1609  *
1610  * acts as a slave. It controls only the direction
1611  *
1612  * when it acts as a master.
1613  *
1614  * 1 = Read
1615  *
1616  * 0 = Write
1617  *
1618  * When a command is entered in the TX FIFO, this bit distinguishes the write and
1619  *
1620  * read commands. In slave-receiver mode, this bit is a 'don't care' because writes
1621  * to
1622  *
1623  * this register are not required. In slave-transmitter mode, a '0' indicates that
1624  * CPU
1625  *
1626  * data is to be transmitted and as DAT or IC_DATA_CMD[7:0].
1627  *
1628  * When programming this bit, you should remember the following: attempting to
1629  *
1630  * perform a read operation after a General Call command has been sent results in a
1631  *
1632  * TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11
1633  *
1634  * (SPECIAL) in the IC_TAR register has been cleared.
1635  *
1636  * If a '1' is written to this bit after receiving a RD_REQ interrupt, then a
1637  * TX_ABRT
1638  *
1639  * interrupt occurs.
1640  *
1641  * NOTE: It is possible that while attempting a master I2C read transfer on
1642  *
1643  * DW_apb_i2c, a RD_REQ interrupt may have occurred simultaneously due to a
1644  *
1645  * remote I2C master addressing DW_apb_i2c. In this type of scenario, DW_apb_i2c
1646  *
1647  * ignores the IC_DATA_CMD write, generates a TX_ABRT interrupt, and waits to
1648  *
1649  * service the RD_REQ interrupt.
1650  *
1651  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
1652  *
1653  * Reset value: 0x0
1654  *
1655  * Field Enumeration Values:
1656  *
1657  * Enum | Value | Description
1658  * :--------------------------------|:------|:---------------------
1659  * ALT_I2C_IC_DATA_CMD_CMD_E_WRITE | 0x0 | Master Write Command
1660  * ALT_I2C_IC_DATA_CMD_CMD_E_READ | 0x1 | Master Read Command
1661  *
1662  * Field Access Macros:
1663  *
1664  */
1665 /*
1666  * Enumerated value for register field ALT_I2C_IC_DATA_CMD_CMD
1667  *
1668  * Master Write Command
1669  */
1670 #define ALT_I2C_IC_DATA_CMD_CMD_E_WRITE 0x0
1671 /*
1672  * Enumerated value for register field ALT_I2C_IC_DATA_CMD_CMD
1673  *
1674  * Master Read Command
1675  */
1676 #define ALT_I2C_IC_DATA_CMD_CMD_E_READ 0x1
1677 
1678 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_DATA_CMD_CMD register field. */
1679 #define ALT_I2C_IC_DATA_CMD_CMD_LSB 8
1680 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_DATA_CMD_CMD register field. */
1681 #define ALT_I2C_IC_DATA_CMD_CMD_MSB 8
1682 /* The width in bits of the ALT_I2C_IC_DATA_CMD_CMD register field. */
1683 #define ALT_I2C_IC_DATA_CMD_CMD_WIDTH 1
1684 /* The mask used to set the ALT_I2C_IC_DATA_CMD_CMD register field value. */
1685 #define ALT_I2C_IC_DATA_CMD_CMD_SET_MSK 0x00000100
1686 /* The mask used to clear the ALT_I2C_IC_DATA_CMD_CMD register field value. */
1687 #define ALT_I2C_IC_DATA_CMD_CMD_CLR_MSK 0xfffffeff
1688 /* The reset value of the ALT_I2C_IC_DATA_CMD_CMD register field. */
1689 #define ALT_I2C_IC_DATA_CMD_CMD_RESET 0x0
1690 /* Extracts the ALT_I2C_IC_DATA_CMD_CMD field value from a register. */
1691 #define ALT_I2C_IC_DATA_CMD_CMD_GET(value) (((value) & 0x00000100) >> 8)
1692 /* Produces a ALT_I2C_IC_DATA_CMD_CMD register field value suitable for setting the register. */
1693 #define ALT_I2C_IC_DATA_CMD_CMD_SET(value) (((value) << 8) & 0x00000100)
1694 
1695 /*
1696  * Field : STOP
1697  *
1698  * This bit controls whether a STOP is issued after the byte is sent or received.
1699  *
1700  * This bit is available only if IC_EMPTYFIFO_HOLD_MASTER_EN is configured to 1.
1701  *
1702  * 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is
1703  *
1704  * empty. If the Tx FIFO is not empty, the master immediately tries to start a new
1705  *
1706  * transfer by issuing a START and arbitrating for the bus.
1707  *
1708  * 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO
1709  * is
1710  *
1711  * empty. If the Tx FIFO is not empty, the master continues the current transfer by
1712  *
1713  * sending/receiving data bytes according to the value of the CMD bit. If the Tx
1714  * FIFO
1715  *
1716  * is empty, the master holds the SCL line low and stalls the bus until a new
1717  *
1718  * command is available in the Tx FIFO.
1719  *
1720  * Reset value: 0x0
1721  *
1722  * Field Enumeration Values:
1723  *
1724  * Enum | Value | Description
1725  * :-----------------------------------|:------|:------------------------------------
1726  * ALT_I2C_IC_DATA_CMD_STOP_E_DISABLE | 0x0 | Donot Issue STOP after this command
1727  * ALT_I2C_IC_DATA_CMD_STOP_E_ENABLE | 0x1 | Issue STOP after this command
1728  *
1729  * Field Access Macros:
1730  *
1731  */
1732 /*
1733  * Enumerated value for register field ALT_I2C_IC_DATA_CMD_STOP
1734  *
1735  * Donot Issue STOP after this command
1736  */
1737 #define ALT_I2C_IC_DATA_CMD_STOP_E_DISABLE 0x0
1738 /*
1739  * Enumerated value for register field ALT_I2C_IC_DATA_CMD_STOP
1740  *
1741  * Issue STOP after this command
1742  */
1743 #define ALT_I2C_IC_DATA_CMD_STOP_E_ENABLE 0x1
1744 
1745 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_DATA_CMD_STOP register field. */
1746 #define ALT_I2C_IC_DATA_CMD_STOP_LSB 9
1747 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_DATA_CMD_STOP register field. */
1748 #define ALT_I2C_IC_DATA_CMD_STOP_MSB 9
1749 /* The width in bits of the ALT_I2C_IC_DATA_CMD_STOP register field. */
1750 #define ALT_I2C_IC_DATA_CMD_STOP_WIDTH 1
1751 /* The mask used to set the ALT_I2C_IC_DATA_CMD_STOP register field value. */
1752 #define ALT_I2C_IC_DATA_CMD_STOP_SET_MSK 0x00000200
1753 /* The mask used to clear the ALT_I2C_IC_DATA_CMD_STOP register field value. */
1754 #define ALT_I2C_IC_DATA_CMD_STOP_CLR_MSK 0xfffffdff
1755 /* The reset value of the ALT_I2C_IC_DATA_CMD_STOP register field. */
1756 #define ALT_I2C_IC_DATA_CMD_STOP_RESET 0x0
1757 /* Extracts the ALT_I2C_IC_DATA_CMD_STOP field value from a register. */
1758 #define ALT_I2C_IC_DATA_CMD_STOP_GET(value) (((value) & 0x00000200) >> 9)
1759 /* Produces a ALT_I2C_IC_DATA_CMD_STOP register field value suitable for setting the register. */
1760 #define ALT_I2C_IC_DATA_CMD_STOP_SET(value) (((value) << 9) & 0x00000200)
1761 
1762 /*
1763  * Field : RESTART
1764  *
1765  * This bit controls whether a RESTART is issued before the byte is sent or
1766  * received.
1767  *
1768  * This bit is available only if IC_EMPTYFIFO_HOLD_MASTER_EN is configured to 1.
1769  *
1770  * 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is
1771  *
1772  * sent/received (according to the value of CMD), regardless of whether or not the
1773  *
1774  * transfer direction is changing from the previous command; if IC_RESTART_EN
1775  *
1776  * is 0, a STOP followed by a START is issued instead.
1777  *
1778  * 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is
1779  *
1780  * changing from the previous command; if IC_RESTART_EN is 0, a STOP followed
1781  *
1782  * by a START is issued instead.
1783  *
1784  * Reset value: 0x0
1785  *
1786  * Field Enumeration Values:
1787  *
1788  * Enum | Value | Description
1789  * :--------------------------------------|:------|:----------------------------------------
1790  * ALT_I2C_IC_DATA_CMD_RESTART_E_DISABLE | 0x0 | Donot Issue RESTART before this command
1791  * ALT_I2C_IC_DATA_CMD_RESTART_E_ENABLE | 0x1 | Issue RESTART before this command
1792  *
1793  * Field Access Macros:
1794  *
1795  */
1796 /*
1797  * Enumerated value for register field ALT_I2C_IC_DATA_CMD_RESTART
1798  *
1799  * Donot Issue RESTART before this command
1800  */
1801 #define ALT_I2C_IC_DATA_CMD_RESTART_E_DISABLE 0x0
1802 /*
1803  * Enumerated value for register field ALT_I2C_IC_DATA_CMD_RESTART
1804  *
1805  * Issue RESTART before this command
1806  */
1807 #define ALT_I2C_IC_DATA_CMD_RESTART_E_ENABLE 0x1
1808 
1809 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_DATA_CMD_RESTART register field. */
1810 #define ALT_I2C_IC_DATA_CMD_RESTART_LSB 10
1811 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_DATA_CMD_RESTART register field. */
1812 #define ALT_I2C_IC_DATA_CMD_RESTART_MSB 10
1813 /* The width in bits of the ALT_I2C_IC_DATA_CMD_RESTART register field. */
1814 #define ALT_I2C_IC_DATA_CMD_RESTART_WIDTH 1
1815 /* The mask used to set the ALT_I2C_IC_DATA_CMD_RESTART register field value. */
1816 #define ALT_I2C_IC_DATA_CMD_RESTART_SET_MSK 0x00000400
1817 /* The mask used to clear the ALT_I2C_IC_DATA_CMD_RESTART register field value. */
1818 #define ALT_I2C_IC_DATA_CMD_RESTART_CLR_MSK 0xfffffbff
1819 /* The reset value of the ALT_I2C_IC_DATA_CMD_RESTART register field. */
1820 #define ALT_I2C_IC_DATA_CMD_RESTART_RESET 0x0
1821 /* Extracts the ALT_I2C_IC_DATA_CMD_RESTART field value from a register. */
1822 #define ALT_I2C_IC_DATA_CMD_RESTART_GET(value) (((value) & 0x00000400) >> 10)
1823 /* Produces a ALT_I2C_IC_DATA_CMD_RESTART register field value suitable for setting the register. */
1824 #define ALT_I2C_IC_DATA_CMD_RESTART_SET(value) (((value) << 10) & 0x00000400)
1825 
1826 /*
1827  * Field : FIRST_DATA_BYTE
1828  *
1829  * Indicates the first data byte
1830  *
1831  * received after the address phase for receive transfer in Master receiver or
1832  * Slave receiver mode.
1833  *
1834  * Reset value : 0x0
1835  *
1836  * Dependencies: This Register bit value is applicable only when
1837  * FIRST_DATA_BYTE_STATUS=1
1838  *
1839  * NOTE: In case of APB_DATA_WIDTH=8,
1840  *
1841  * a. The user has to perform two APB Reads to IC_DATA_CMD in order to get
1842  * status on 11 bit.
1843  *
1844  * b. Inorder to read the 11 bit, the user has to perform the first data byte
1845  * read [7:0] (offset 0x10)
1846  *
1847  * and then perform the second read[15:8](offset 0x11) in order to know the status
1848  * of 11 bit
1849  *
1850  * (whether the data received in previous read is a first data byte or not).
1851  *
1852  * c. The 11th bit is an optional read field, user can ignore 2nd byte read
1853  * [15:8] (offset 0x11)
1854  *
1855  * if not interested in FIRST_DATA_BYTE status.
1856  *
1857  * Field Enumeration Values:
1858  *
1859  * Enum | Value | Description
1860  * :-----------------------------------------------|:------|:----------------------------------
1861  * ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE_E_INACTIVE | 0x0 | Sequential data byte received
1862  * ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE_E_ACTIVE | 0x1 | Non sequential data byte received
1863  *
1864  * Field Access Macros:
1865  *
1866  */
1867 /*
1868  * Enumerated value for register field ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE
1869  *
1870  * Sequential data byte received
1871  */
1872 #define ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE_E_INACTIVE 0x0
1873 /*
1874  * Enumerated value for register field ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE
1875  *
1876  * Non sequential data byte received
1877  */
1878 #define ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE_E_ACTIVE 0x1
1879 
1880 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE register field. */
1881 #define ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE_LSB 11
1882 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE register field. */
1883 #define ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE_MSB 11
1884 /* The width in bits of the ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE register field. */
1885 #define ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE_WIDTH 1
1886 /* The mask used to set the ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE register field value. */
1887 #define ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE_SET_MSK 0x00000800
1888 /* The mask used to clear the ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE register field value. */
1889 #define ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE_CLR_MSK 0xfffff7ff
1890 /* The reset value of the ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE register field. */
1891 #define ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE_RESET 0x0
1892 /* Extracts the ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE field value from a register. */
1893 #define ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE_GET(value) (((value) & 0x00000800) >> 11)
1894 /* Produces a ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE register field value suitable for setting the register. */
1895 #define ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE_SET(value) (((value) << 11) & 0x00000800)
1896 
1897 /*
1898  * Field : RSVD_IC_DATA_CMD
1899  *
1900  * Reserved bits - Read Only
1901  *
1902  * Field Access Macros:
1903  *
1904  */
1905 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD register field. */
1906 #define ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD_LSB 12
1907 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD register field. */
1908 #define ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD_MSB 31
1909 /* The width in bits of the ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD register field. */
1910 #define ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD_WIDTH 20
1911 /* The mask used to set the ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD register field value. */
1912 #define ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD_SET_MSK 0xfffff000
1913 /* The mask used to clear the ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD register field value. */
1914 #define ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD_CLR_MSK 0x00000fff
1915 /* The reset value of the ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD register field. */
1916 #define ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD_RESET 0x0
1917 /* Extracts the ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD field value from a register. */
1918 #define ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD_GET(value) (((value) & 0xfffff000) >> 12)
1919 /* Produces a ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD register field value suitable for setting the register. */
1920 #define ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD_SET(value) (((value) << 12) & 0xfffff000)
1921 
1922 #ifndef __ASSEMBLY__
1923 /*
1924  * WARNING: The C register and register group struct declarations are provided for
1925  * convenience and illustrative purposes. They should, however, be used with
1926  * caution as the C language standard provides no guarantees about the alignment or
1927  * atomicity of device memory accesses. The recommended practice for coding device
1928  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1929  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1930  * alt_write_dword() functions for 64 bit registers.
1931  *
1932  * The struct declaration for register ALT_I2C_IC_DATA_CMD.
1933  */
1934 struct ALT_I2C_IC_DATA_CMD_s
1935 {
1936  volatile uint32_t DAT : 8; /* ALT_I2C_IC_DATA_CMD_DAT */
1937  volatile uint32_t CMD : 1; /* ALT_I2C_IC_DATA_CMD_CMD */
1938  volatile uint32_t STOP : 1; /* ALT_I2C_IC_DATA_CMD_STOP */
1939  volatile uint32_t RESTART : 1; /* ALT_I2C_IC_DATA_CMD_RESTART */
1940  const volatile uint32_t FIRST_DATA_BYTE : 1; /* ALT_I2C_IC_DATA_CMD_FIRST_DATA_BYTE */
1941  const volatile uint32_t RSVD_IC_DATA_CMD : 20; /* ALT_I2C_IC_DATA_CMD_RSVD_IC_DATA_CMD */
1942 };
1943 
1944 /* The typedef declaration for register ALT_I2C_IC_DATA_CMD. */
1945 typedef struct ALT_I2C_IC_DATA_CMD_s ALT_I2C_IC_DATA_CMD_t;
1946 #endif /* __ASSEMBLY__ */
1947 
1948 /* The reset value of the ALT_I2C_IC_DATA_CMD register. */
1949 #define ALT_I2C_IC_DATA_CMD_RESET 0x00000000
1950 /* The byte offset of the ALT_I2C_IC_DATA_CMD register from the beginning of the component. */
1951 #define ALT_I2C_IC_DATA_CMD_OFST 0x10
1952 /* The address of the ALT_I2C_IC_DATA_CMD register. */
1953 #define ALT_I2C_IC_DATA_CMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_DATA_CMD_OFST))
1954 
1955 /*
1956  * Register : Standard Speed I2C Clock SCL High Count Register - IC_SS_SCL_HCNT
1957  *
1958  * Name: Standard Speed I2C Clock SCL High Count Register
1959  *
1960  * Size: 16 bits
1961  *
1962  * Address Offset: 0x14
1963  *
1964  * Read/Write Access: Read/Write
1965  *
1966  * Dependencies: This register is not applicable when IC_ULTRA_FAST_MODE=1
1967  *
1968  * Register Layout
1969  *
1970  * Bits | Access | Reset | Description
1971  * :--------|:-------|:------|:-------------------------------------------------
1972  * [15:0] | RW | 0x1f4 | ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT
1973  * [31:16] | R | 0x0 | ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT
1974  *
1975  */
1976 /*
1977  * Field : IC_SS_SCL_HCNT
1978  *
1979  * This register must be set before any I2C bus transaction can take place to
1980  *
1981  * ensure proper I/O timing. This register sets the SCL clock high-period
1982  *
1983  * count for standard speed.
1984  *
1985  * This register can be written only when the I2C interface is disabled which
1986  *
1987  * corresponds to the IC_ENABLE[0] register being set to 0. Writes at other
1988  *
1989  * times have no effect.
1990  *
1991  * The minimum valid value is 6; hardware prevents values less than this
1992  *
1993  * being written, and if attempted results in 6 being set. For designs with
1994  *
1995  * APB_DATA_WIDTH = 8, the order of programming is important to ensure
1996  *
1997  * the correct operation of the DW_apb_i2c. The lower byte must be
1998  *
1999  * programmed first. Then the upper byte is programmed.
2000  *
2001  * When the configuration parameter IC_HC_COUNT_VALUES is set to 1,
2002  *
2003  * this register is read only.
2004  *
2005  * NOTE: This register must not be programmed to a value higher than
2006  *
2007  * 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle
2008  *
2009  * condition when this counter reaches a value of IC_SS_SCL_HCNT + 10.
2010  *
2011  * Reset value: IC_SS_SCL_HIGH_COUNT configuration parameter
2012  *
2013  * Field Access Macros:
2014  *
2015  */
2016 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */
2017 #define ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB 0
2018 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */
2019 #define ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB 15
2020 /* The width in bits of the ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */
2021 #define ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_WIDTH 16
2022 /* The mask used to set the ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value. */
2023 #define ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET_MSK 0x0000ffff
2024 /* The mask used to clear the ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value. */
2025 #define ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_CLR_MSK 0xffff0000
2026 /* The reset value of the ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */
2027 #define ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET 0x1f4
2028 /* Extracts the ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT field value from a register. */
2029 #define ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0)
2030 /* Produces a ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value suitable for setting the register. */
2031 #define ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff)
2032 
2033 /*
2034  * Field : RSVD_IC_SS_SCL_HIGH_COUNT
2035  *
2036  * Reserved bits - Read Only
2037  *
2038  * Field Access Macros:
2039  *
2040  */
2041 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT register field. */
2042 #define ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT_LSB 16
2043 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT register field. */
2044 #define ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT_MSB 31
2045 /* The width in bits of the ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT register field. */
2046 #define ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT_WIDTH 16
2047 /* The mask used to set the ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT register field value. */
2048 #define ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT_SET_MSK 0xffff0000
2049 /* The mask used to clear the ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT register field value. */
2050 #define ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT_CLR_MSK 0x0000ffff
2051 /* The reset value of the ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT register field. */
2052 #define ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT_RESET 0x0
2053 /* Extracts the ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT field value from a register. */
2054 #define ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT_GET(value) (((value) & 0xffff0000) >> 16)
2055 /* Produces a ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT register field value suitable for setting the register. */
2056 #define ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT_SET(value) (((value) << 16) & 0xffff0000)
2057 
2058 #ifndef __ASSEMBLY__
2059 /*
2060  * WARNING: The C register and register group struct declarations are provided for
2061  * convenience and illustrative purposes. They should, however, be used with
2062  * caution as the C language standard provides no guarantees about the alignment or
2063  * atomicity of device memory accesses. The recommended practice for coding device
2064  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2065  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2066  * alt_write_dword() functions for 64 bit registers.
2067  *
2068  * The struct declaration for register ALT_I2C_IC_SS_SCL_HCNT.
2069  */
2070 struct ALT_I2C_IC_SS_SCL_HCNT_s
2071 {
2072  volatile uint32_t IC_SS_SCL_HCNT : 16; /* ALT_I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT */
2073  const volatile uint32_t RSVD_IC_SS_SCL_HIGH_COUNT : 16; /* ALT_I2C_IC_SS_SCL_HCNT_RSVD_IC_SS_SCL_HIGH_COUNT */
2074 };
2075 
2076 /* The typedef declaration for register ALT_I2C_IC_SS_SCL_HCNT. */
2077 typedef struct ALT_I2C_IC_SS_SCL_HCNT_s ALT_I2C_IC_SS_SCL_HCNT_t;
2078 #endif /* __ASSEMBLY__ */
2079 
2080 /* The reset value of the ALT_I2C_IC_SS_SCL_HCNT register. */
2081 #define ALT_I2C_IC_SS_SCL_HCNT_RESET 0x000001f4
2082 /* The byte offset of the ALT_I2C_IC_SS_SCL_HCNT register from the beginning of the component. */
2083 #define ALT_I2C_IC_SS_SCL_HCNT_OFST 0x14
2084 /* The address of the ALT_I2C_IC_SS_SCL_HCNT register. */
2085 #define ALT_I2C_IC_SS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_SS_SCL_HCNT_OFST))
2086 
2087 /*
2088  * Register : Standard Speed I2C Clock SCL Low Count Register - IC_SS_SCL_LCNT
2089  *
2090  * Name: Standard Speed I2C Clock SCL Low Count Register
2091  *
2092  * Size: 16 bits
2093  *
2094  * Address Offset: 0x18
2095  *
2096  * Read/Write Access: Read/Write
2097  *
2098  * Dependencies: This register is not applicable when IC_ULTRA_FAST_MODE=1
2099  *
2100  * Register Layout
2101  *
2102  * Bits | Access | Reset | Description
2103  * :--------|:-------|:------|:------------------------------------------------
2104  * [15:0] | RW | 0x24c | ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT
2105  * [31:16] | R | 0x0 | ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT
2106  *
2107  */
2108 /*
2109  * Field : IC_SS_SCL_LCNT
2110  *
2111  * This register must be set before any I2C bus transaction can take place to
2112  *
2113  * ensure proper I/O timing. This register sets the SCL clock low period
2114  *
2115  * count for standard speed.
2116  *
2117  * This register can be written only when the I2C interface is disabled which
2118  *
2119  * corresponds to the IC_ENABLE[0] register being set to 0. Writes at other
2120  *
2121  * times have no effect.
2122  *
2123  * The minimum valid value is 8; hardware prevents values less than this
2124  *
2125  * being written, and if attempted, results in 8 being set. For designs with
2126  *
2127  * APB_DATA_WIDTH = 8, the order of programming is important to
2128  *
2129  * ensure the correct operation of DW_apb_i2c. The lower byte must be
2130  *
2131  * programmed first, and then the upper byte is programmed.
2132  *
2133  * When the configuration parameter IC_HC_COUNT_VALUES is set to 1,
2134  *
2135  * this register is read only.
2136  *
2137  * Reset value: IC_SS_SCL_LOW_COUNT configuration parameter
2138  *
2139  * Field Access Macros:
2140  *
2141  */
2142 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */
2143 #define ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB 0
2144 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */
2145 #define ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB 15
2146 /* The width in bits of the ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */
2147 #define ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_WIDTH 16
2148 /* The mask used to set the ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value. */
2149 #define ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET_MSK 0x0000ffff
2150 /* The mask used to clear the ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value. */
2151 #define ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_CLR_MSK 0xffff0000
2152 /* The reset value of the ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */
2153 #define ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET 0x24c
2154 /* Extracts the ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT field value from a register. */
2155 #define ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0)
2156 /* Produces a ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value suitable for setting the register. */
2157 #define ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff)
2158 
2159 /*
2160  * Field : RSVD_IC_SS_SCL_LOW_COUNT
2161  *
2162  * Reserved bits - Read Only
2163  *
2164  * Field Access Macros:
2165  *
2166  */
2167 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT register field. */
2168 #define ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT_LSB 16
2169 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT register field. */
2170 #define ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT_MSB 31
2171 /* The width in bits of the ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT register field. */
2172 #define ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT_WIDTH 16
2173 /* The mask used to set the ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT register field value. */
2174 #define ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT_SET_MSK 0xffff0000
2175 /* The mask used to clear the ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT register field value. */
2176 #define ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT_CLR_MSK 0x0000ffff
2177 /* The reset value of the ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT register field. */
2178 #define ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT_RESET 0x0
2179 /* Extracts the ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT field value from a register. */
2180 #define ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT_GET(value) (((value) & 0xffff0000) >> 16)
2181 /* Produces a ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT register field value suitable for setting the register. */
2182 #define ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT_SET(value) (((value) << 16) & 0xffff0000)
2183 
2184 #ifndef __ASSEMBLY__
2185 /*
2186  * WARNING: The C register and register group struct declarations are provided for
2187  * convenience and illustrative purposes. They should, however, be used with
2188  * caution as the C language standard provides no guarantees about the alignment or
2189  * atomicity of device memory accesses. The recommended practice for coding device
2190  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2191  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2192  * alt_write_dword() functions for 64 bit registers.
2193  *
2194  * The struct declaration for register ALT_I2C_IC_SS_SCL_LCNT.
2195  */
2196 struct ALT_I2C_IC_SS_SCL_LCNT_s
2197 {
2198  volatile uint32_t IC_SS_SCL_LCNT : 16; /* ALT_I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT */
2199  const volatile uint32_t RSVD_IC_SS_SCL_LOW_COUNT : 16; /* ALT_I2C_IC_SS_SCL_LCNT_RSVD_IC_SS_SCL_LOW_COUNT */
2200 };
2201 
2202 /* The typedef declaration for register ALT_I2C_IC_SS_SCL_LCNT. */
2203 typedef struct ALT_I2C_IC_SS_SCL_LCNT_s ALT_I2C_IC_SS_SCL_LCNT_t;
2204 #endif /* __ASSEMBLY__ */
2205 
2206 /* The reset value of the ALT_I2C_IC_SS_SCL_LCNT register. */
2207 #define ALT_I2C_IC_SS_SCL_LCNT_RESET 0x0000024c
2208 /* The byte offset of the ALT_I2C_IC_SS_SCL_LCNT register from the beginning of the component. */
2209 #define ALT_I2C_IC_SS_SCL_LCNT_OFST 0x18
2210 /* The address of the ALT_I2C_IC_SS_SCL_LCNT register. */
2211 #define ALT_I2C_IC_SS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_SS_SCL_LCNT_OFST))
2212 
2213 /*
2214  * Register : Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register - IC_FS_SCL_HCNT
2215  *
2216  * Name: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
2217  *
2218  * Size: 16 bits
2219  *
2220  * Address Offset: 0x1c
2221  *
2222  * Read/Write Access: Read/Write
2223  *
2224  * Dependencies: This register is not applicable when IC_ULTRA_FAST_MODE=1
2225  *
2226  * Register Layout
2227  *
2228  * Bits | Access | Reset | Description
2229  * :--------|:-------|:------|:-------------------------------------------
2230  * [15:0] | RW | 0x4b | ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT
2231  * [31:16] | R | 0x0 | ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT
2232  *
2233  */
2234 /*
2235  * Field : IC_FS_SCL_HCNT
2236  *
2237  * This register must be set before any I2C bus transaction can take place to
2238  *
2239  * ensure proper I/O timing. This register sets the SCL clock high-period
2240  *
2241  * count for fast mode or fast mode plus. It is used in high-speed mode to send the
2242  * Master Code
2243  *
2244  * and START BYTE or General CALL.
2245  *
2246  * This register goes away and becomes read-only returning 0s if
2247  *
2248  * IC_MAX_SPEED_MODE = standard. This register can be written only
2249  *
2250  * when the I2C interface is disabled, which corresponds to the IC_ENABLE[0]
2251  *
2252  * register being set to 0. Writes at other times have no effect.
2253  *
2254  * The minimum valid value is 6; hardware prevents values less than this
2255  *
2256  * being written, and if attempted results in 6 being set. For designs with
2257  *
2258  * APB_DATA_WIDTH == 8 the order of programming is important to
2259  *
2260  * ensure the correct operation of the DW_apb_i2c. The lower byte must be
2261  *
2262  * programmed first. Then the upper byte is programmed.
2263  *
2264  * When the configuration parameter IC_HC_COUNT_VALUES is set to 1,
2265  *
2266  * this register is read only.
2267  *
2268  * Reset value: IC_FS_SCL_HIGH_COUNT configuration parameter
2269  *
2270  * Field Access Macros:
2271  *
2272  */
2273 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */
2274 #define ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB 0
2275 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */
2276 #define ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB 15
2277 /* The width in bits of the ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */
2278 #define ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_WIDTH 16
2279 /* The mask used to set the ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value. */
2280 #define ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET_MSK 0x0000ffff
2281 /* The mask used to clear the ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value. */
2282 #define ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_CLR_MSK 0xffff0000
2283 /* The reset value of the ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */
2284 #define ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET 0x4b
2285 /* Extracts the ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT field value from a register. */
2286 #define ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0)
2287 /* Produces a ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value suitable for setting the register. */
2288 #define ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff)
2289 
2290 /*
2291  * Field : RSVD_IC_FS_SCL_HCNT
2292  *
2293  * Reserved bits - Read Only
2294  *
2295  * Field Access Macros:
2296  *
2297  */
2298 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT register field. */
2299 #define ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT_LSB 16
2300 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT register field. */
2301 #define ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT_MSB 31
2302 /* The width in bits of the ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT register field. */
2303 #define ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT_WIDTH 16
2304 /* The mask used to set the ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT register field value. */
2305 #define ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT_SET_MSK 0xffff0000
2306 /* The mask used to clear the ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT register field value. */
2307 #define ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT_CLR_MSK 0x0000ffff
2308 /* The reset value of the ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT register field. */
2309 #define ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT_RESET 0x0
2310 /* Extracts the ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT field value from a register. */
2311 #define ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT_GET(value) (((value) & 0xffff0000) >> 16)
2312 /* Produces a ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT register field value suitable for setting the register. */
2313 #define ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT_SET(value) (((value) << 16) & 0xffff0000)
2314 
2315 #ifndef __ASSEMBLY__
2316 /*
2317  * WARNING: The C register and register group struct declarations are provided for
2318  * convenience and illustrative purposes. They should, however, be used with
2319  * caution as the C language standard provides no guarantees about the alignment or
2320  * atomicity of device memory accesses. The recommended practice for coding device
2321  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2322  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2323  * alt_write_dword() functions for 64 bit registers.
2324  *
2325  * The struct declaration for register ALT_I2C_IC_FS_SCL_HCNT.
2326  */
2327 struct ALT_I2C_IC_FS_SCL_HCNT_s
2328 {
2329  volatile uint32_t IC_FS_SCL_HCNT : 16; /* ALT_I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT */
2330  const volatile uint32_t RSVD_IC_FS_SCL_HCNT : 16; /* ALT_I2C_IC_FS_SCL_HCNT_RSVD_IC_FS_SCL_HCNT */
2331 };
2332 
2333 /* The typedef declaration for register ALT_I2C_IC_FS_SCL_HCNT. */
2334 typedef struct ALT_I2C_IC_FS_SCL_HCNT_s ALT_I2C_IC_FS_SCL_HCNT_t;
2335 #endif /* __ASSEMBLY__ */
2336 
2337 /* The reset value of the ALT_I2C_IC_FS_SCL_HCNT register. */
2338 #define ALT_I2C_IC_FS_SCL_HCNT_RESET 0x0000004b
2339 /* The byte offset of the ALT_I2C_IC_FS_SCL_HCNT register from the beginning of the component. */
2340 #define ALT_I2C_IC_FS_SCL_HCNT_OFST 0x1c
2341 /* The address of the ALT_I2C_IC_FS_SCL_HCNT register. */
2342 #define ALT_I2C_IC_FS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_FS_SCL_HCNT_OFST))
2343 
2344 /*
2345  * Register : Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register - IC_FS_SCL_LCNT
2346  *
2347  * Name: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
2348  *
2349  * Size: 16 bits
2350  *
2351  * Address Offset: 0x20
2352  *
2353  * Read/Write Access: Read/Write
2354  *
2355  * Dependencies: This register is not applicable when IC_ULTRA_FAST_MODE=1
2356  *
2357  * Register Layout
2358  *
2359  * Bits | Access | Reset | Description
2360  * :--------|:-------|:------|:-------------------------------------------
2361  * [15:0] | RW | 0xa3 | ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT
2362  * [31:16] | R | 0x0 | ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT
2363  *
2364  */
2365 /*
2366  * Field : IC_FS_SCL_LCNT
2367  *
2368  * This register must be set before any I2C bus transaction can take place to
2369  *
2370  * ensure proper I/O timing. This register sets the SCL clock low period count
2371  *
2372  * for fast speed. It is used in high-speed mode to send the Master Code and
2373  *
2374  * START BYTE or General CALL.
2375  *
2376  * This register goes away and becomes read-only returning 0s if
2377  *
2378  * IC_MAX_SPEED_MODE = standard.
2379  *
2380  * This register can be written only when the I2C interface is disabled, which
2381  *
2382  * corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times
2383  *
2384  * have no effect.
2385  *
2386  * The minimum valid value is 8; hardware prevents values less than this
2387  *
2388  * being written, and if attempted results in 8 being set. For designs with
2389  *
2390  * APB_DATA_WIDTH = 8 the order of programming is important to ensure
2391  *
2392  * the correct operation of the DW_apb_i2c. The lower byte must be
2393  *
2394  * programmed first. Then the upper byte is programmed. If the value is less
2395  *
2396  * than 8 then the count value gets changed to 8.
2397  *
2398  * When the configuration parameter IC_HC_COUNT_VALUES is set to 1,
2399  *
2400  * this register is read only.
2401  *
2402  * Reset value: IC_FS_SCL_LOW_COUNT configuration parameter
2403  *
2404  * Field Access Macros:
2405  *
2406  */
2407 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */
2408 #define ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB 0
2409 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */
2410 #define ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB 15
2411 /* The width in bits of the ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */
2412 #define ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_WIDTH 16
2413 /* The mask used to set the ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value. */
2414 #define ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET_MSK 0x0000ffff
2415 /* The mask used to clear the ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value. */
2416 #define ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_CLR_MSK 0xffff0000
2417 /* The reset value of the ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */
2418 #define ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET 0xa3
2419 /* Extracts the ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT field value from a register. */
2420 #define ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0)
2421 /* Produces a ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value suitable for setting the register. */
2422 #define ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff)
2423 
2424 /*
2425  * Field : RSVD_IC_FS_SCL_LCNT
2426  *
2427  * Reserved bits - Read Only
2428  *
2429  * Field Access Macros:
2430  *
2431  */
2432 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT register field. */
2433 #define ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT_LSB 16
2434 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT register field. */
2435 #define ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT_MSB 31
2436 /* The width in bits of the ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT register field. */
2437 #define ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT_WIDTH 16
2438 /* The mask used to set the ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT register field value. */
2439 #define ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT_SET_MSK 0xffff0000
2440 /* The mask used to clear the ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT register field value. */
2441 #define ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT_CLR_MSK 0x0000ffff
2442 /* The reset value of the ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT register field. */
2443 #define ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT_RESET 0x0
2444 /* Extracts the ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT field value from a register. */
2445 #define ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT_GET(value) (((value) & 0xffff0000) >> 16)
2446 /* Produces a ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT register field value suitable for setting the register. */
2447 #define ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT_SET(value) (((value) << 16) & 0xffff0000)
2448 
2449 #ifndef __ASSEMBLY__
2450 /*
2451  * WARNING: The C register and register group struct declarations are provided for
2452  * convenience and illustrative purposes. They should, however, be used with
2453  * caution as the C language standard provides no guarantees about the alignment or
2454  * atomicity of device memory accesses. The recommended practice for coding device
2455  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2456  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2457  * alt_write_dword() functions for 64 bit registers.
2458  *
2459  * The struct declaration for register ALT_I2C_IC_FS_SCL_LCNT.
2460  */
2461 struct ALT_I2C_IC_FS_SCL_LCNT_s
2462 {
2463  volatile uint32_t IC_FS_SCL_LCNT : 16; /* ALT_I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT */
2464  const volatile uint32_t RSVD_IC_FS_SCL_LCNT : 16; /* ALT_I2C_IC_FS_SCL_LCNT_RSVD_IC_FS_SCL_LCNT */
2465 };
2466 
2467 /* The typedef declaration for register ALT_I2C_IC_FS_SCL_LCNT. */
2468 typedef struct ALT_I2C_IC_FS_SCL_LCNT_s ALT_I2C_IC_FS_SCL_LCNT_t;
2469 #endif /* __ASSEMBLY__ */
2470 
2471 /* The reset value of the ALT_I2C_IC_FS_SCL_LCNT register. */
2472 #define ALT_I2C_IC_FS_SCL_LCNT_RESET 0x000000a3
2473 /* The byte offset of the ALT_I2C_IC_FS_SCL_LCNT register from the beginning of the component. */
2474 #define ALT_I2C_IC_FS_SCL_LCNT_OFST 0x20
2475 /* The address of the ALT_I2C_IC_FS_SCL_LCNT register. */
2476 #define ALT_I2C_IC_FS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_FS_SCL_LCNT_OFST))
2477 
2478 /*
2479  * Register : High Speed I2C Clock SCL Low Count Register - IC_INTR_STAT
2480  *
2481  * Name: I2C Interrupt Status Register
2482  *
2483  * Size: 15 bits
2484  *
2485  * Address Offset: 0x2C
2486  *
2487  * Read/Write Access: Read
2488  *
2489  * Each bit in this register has a corresponding mask bit
2490  *
2491  * in the IC_INTR_MASK register. These bits are cleared by reading the matching
2492  *
2493  * interrupt clear register. The unmasked raw versions of these bits are
2494  *
2495  * available in the IC_RAW_INTR_STAT register.
2496  *
2497  * Register Layout
2498  *
2499  * Bits | Access | Reset | Description
2500  * :--------|:-------|:------|:---------------------------------------------
2501  * [0] | R | 0x0 | ALT_I2C_IC_INTR_STAT_R_RX_UNDER
2502  * [1] | R | 0x0 | ALT_I2C_IC_INTR_STAT_R_RX_OVER
2503  * [2] | R | 0x0 | ALT_I2C_IC_INTR_STAT_R_RX_FULL
2504  * [3] | R | 0x0 | ALT_I2C_IC_INTR_STAT_R_TX_OVER
2505  * [4] | R | 0x0 | ALT_I2C_IC_INTR_STAT_R_TX_EMPTY
2506  * [5] | R | 0x0 | ALT_I2C_IC_INTR_STAT_R_RD_REQ
2507  * [6] | R | 0x0 | ALT_I2C_IC_INTR_STAT_R_TX_ABRT
2508  * [7] | R | 0x0 | ALT_I2C_IC_INTR_STAT_R_RX_DONE
2509  * [8] | R | 0x0 | ALT_I2C_IC_INTR_STAT_R_ACTIVITY
2510  * [9] | R | 0x0 | ALT_I2C_IC_INTR_STAT_R_STOP_DET
2511  * [10] | R | 0x0 | ALT_I2C_IC_INTR_STAT_R_START_DET
2512  * [11] | R | 0x0 | ALT_I2C_IC_INTR_STAT_R_GEN_CALL
2513  * [12] | R | 0x0 | ALT_I2C_IC_INTR_STAT_R_RESTART_DET
2514  * [13] | R | 0x0 | ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD
2515  * [14] | R | 0x0 | ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW
2516  * [31:15] | R | 0x0 | ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT
2517  *
2518  */
2519 /*
2520  * Field : R_RX_UNDER
2521  *
2522  * Set if the processor attempts to read the receive buffer when it is empty by
2523  *
2524  * reading from the IC_DATA_CMD register. If the module is disabled
2525  *
2526  * (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state
2527  *
2528  * machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
2529  *
2530  * Reset value: 0x0
2531  *
2532  * Field Enumeration Values:
2533  *
2534  * Enum | Value | Description
2535  * :-------------------------------------------|:------|:-------------------------------
2536  * ALT_I2C_IC_INTR_STAT_R_RX_UNDER_E_INACTIVE | 0x0 | RX_UNDER interrupt is inactive
2537  * ALT_I2C_IC_INTR_STAT_R_RX_UNDER_E_ACTIVE | 0x1 | RX_UNDER interrupt is active
2538  *
2539  * Field Access Macros:
2540  *
2541  */
2542 /*
2543  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_RX_UNDER
2544  *
2545  * RX_UNDER interrupt is inactive
2546  */
2547 #define ALT_I2C_IC_INTR_STAT_R_RX_UNDER_E_INACTIVE 0x0
2548 /*
2549  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_RX_UNDER
2550  *
2551  * RX_UNDER interrupt is active
2552  */
2553 #define ALT_I2C_IC_INTR_STAT_R_RX_UNDER_E_ACTIVE 0x1
2554 
2555 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_STAT_R_RX_UNDER register field. */
2556 #define ALT_I2C_IC_INTR_STAT_R_RX_UNDER_LSB 0
2557 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_STAT_R_RX_UNDER register field. */
2558 #define ALT_I2C_IC_INTR_STAT_R_RX_UNDER_MSB 0
2559 /* The width in bits of the ALT_I2C_IC_INTR_STAT_R_RX_UNDER register field. */
2560 #define ALT_I2C_IC_INTR_STAT_R_RX_UNDER_WIDTH 1
2561 /* The mask used to set the ALT_I2C_IC_INTR_STAT_R_RX_UNDER register field value. */
2562 #define ALT_I2C_IC_INTR_STAT_R_RX_UNDER_SET_MSK 0x00000001
2563 /* The mask used to clear the ALT_I2C_IC_INTR_STAT_R_RX_UNDER register field value. */
2564 #define ALT_I2C_IC_INTR_STAT_R_RX_UNDER_CLR_MSK 0xfffffffe
2565 /* The reset value of the ALT_I2C_IC_INTR_STAT_R_RX_UNDER register field. */
2566 #define ALT_I2C_IC_INTR_STAT_R_RX_UNDER_RESET 0x0
2567 /* Extracts the ALT_I2C_IC_INTR_STAT_R_RX_UNDER field value from a register. */
2568 #define ALT_I2C_IC_INTR_STAT_R_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
2569 /* Produces a ALT_I2C_IC_INTR_STAT_R_RX_UNDER register field value suitable for setting the register. */
2570 #define ALT_I2C_IC_INTR_STAT_R_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
2571 
2572 /*
2573  * Field : R_RX_OVER
2574  *
2575  * Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and
2576  *
2577  * an additional byte is received from an external I2C device. The DW_apb_i2c
2578  *
2579  * acknowledges this, but any data bytes received after the FIFO is full are lost.
2580  * If
2581  *
2582  * the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the
2583  *
2584  * master or slave state machines go into idle, and when ic_en goes to 0, this
2585  *
2586  * interrupt is cleared.
2587  *
2588  * NOTE: If configuration parameter IC_RX_FULL_HLD_BUS_EN is Enabled and IC_CON[9]
2589  * bit (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH,
2590  *
2591  * then the RX_OVER interrupt will never occur, because the Rx FIFO will never
2592  * overflow.
2593  *
2594  * Reset value: 0x0
2595  *
2596  * Field Enumeration Values:
2597  *
2598  * Enum | Value | Description
2599  * :------------------------------------------|:------|:--------------------------------
2600  * ALT_I2C_IC_INTR_STAT_R_RX_OVER_E_INACTIVE | 0x0 | R_RX_OVER interrupt is inactive
2601  * ALT_I2C_IC_INTR_STAT_R_RX_OVER_E_ACTIVE | 0x1 | R_RX_OVER interrupt is active
2602  *
2603  * Field Access Macros:
2604  *
2605  */
2606 /*
2607  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_RX_OVER
2608  *
2609  * R_RX_OVER interrupt is inactive
2610  */
2611 #define ALT_I2C_IC_INTR_STAT_R_RX_OVER_E_INACTIVE 0x0
2612 /*
2613  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_RX_OVER
2614  *
2615  * R_RX_OVER interrupt is active
2616  */
2617 #define ALT_I2C_IC_INTR_STAT_R_RX_OVER_E_ACTIVE 0x1
2618 
2619 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_STAT_R_RX_OVER register field. */
2620 #define ALT_I2C_IC_INTR_STAT_R_RX_OVER_LSB 1
2621 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_STAT_R_RX_OVER register field. */
2622 #define ALT_I2C_IC_INTR_STAT_R_RX_OVER_MSB 1
2623 /* The width in bits of the ALT_I2C_IC_INTR_STAT_R_RX_OVER register field. */
2624 #define ALT_I2C_IC_INTR_STAT_R_RX_OVER_WIDTH 1
2625 /* The mask used to set the ALT_I2C_IC_INTR_STAT_R_RX_OVER register field value. */
2626 #define ALT_I2C_IC_INTR_STAT_R_RX_OVER_SET_MSK 0x00000002
2627 /* The mask used to clear the ALT_I2C_IC_INTR_STAT_R_RX_OVER register field value. */
2628 #define ALT_I2C_IC_INTR_STAT_R_RX_OVER_CLR_MSK 0xfffffffd
2629 /* The reset value of the ALT_I2C_IC_INTR_STAT_R_RX_OVER register field. */
2630 #define ALT_I2C_IC_INTR_STAT_R_RX_OVER_RESET 0x0
2631 /* Extracts the ALT_I2C_IC_INTR_STAT_R_RX_OVER field value from a register. */
2632 #define ALT_I2C_IC_INTR_STAT_R_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
2633 /* Produces a ALT_I2C_IC_INTR_STAT_R_RX_OVER register field value suitable for setting the register. */
2634 #define ALT_I2C_IC_INTR_STAT_R_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
2635 
2636 /*
2637  * Field : R_RX_FULL
2638  *
2639  * Set when the receive buffer reaches or goes above the RX_TL threshold in the
2640  *
2641  * IC_RX_TL register. It is automatically cleared by hardware when buffer level
2642  *
2643  * goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the
2644  *
2645  * RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this
2646  *
2647  * bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of
2648  *
2649  * the activity that continues.
2650  *
2651  * Reset value: 0x0
2652  *
2653  * Field Enumeration Values:
2654  *
2655  * Enum | Value | Description
2656  * :------------------------------------------|:------|:--------------------------------
2657  * ALT_I2C_IC_INTR_STAT_R_RX_FULL_E_INACTIVE | 0x0 | R_RX_FULL interrupt is inactive
2658  * ALT_I2C_IC_INTR_STAT_R_RX_FULL_E_ACTIVE | 0x1 | R_RX_FULL interrupt is active
2659  *
2660  * Field Access Macros:
2661  *
2662  */
2663 /*
2664  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_RX_FULL
2665  *
2666  * R_RX_FULL interrupt is inactive
2667  */
2668 #define ALT_I2C_IC_INTR_STAT_R_RX_FULL_E_INACTIVE 0x0
2669 /*
2670  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_RX_FULL
2671  *
2672  * R_RX_FULL interrupt is active
2673  */
2674 #define ALT_I2C_IC_INTR_STAT_R_RX_FULL_E_ACTIVE 0x1
2675 
2676 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_STAT_R_RX_FULL register field. */
2677 #define ALT_I2C_IC_INTR_STAT_R_RX_FULL_LSB 2
2678 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_STAT_R_RX_FULL register field. */
2679 #define ALT_I2C_IC_INTR_STAT_R_RX_FULL_MSB 2
2680 /* The width in bits of the ALT_I2C_IC_INTR_STAT_R_RX_FULL register field. */
2681 #define ALT_I2C_IC_INTR_STAT_R_RX_FULL_WIDTH 1
2682 /* The mask used to set the ALT_I2C_IC_INTR_STAT_R_RX_FULL register field value. */
2683 #define ALT_I2C_IC_INTR_STAT_R_RX_FULL_SET_MSK 0x00000004
2684 /* The mask used to clear the ALT_I2C_IC_INTR_STAT_R_RX_FULL register field value. */
2685 #define ALT_I2C_IC_INTR_STAT_R_RX_FULL_CLR_MSK 0xfffffffb
2686 /* The reset value of the ALT_I2C_IC_INTR_STAT_R_RX_FULL register field. */
2687 #define ALT_I2C_IC_INTR_STAT_R_RX_FULL_RESET 0x0
2688 /* Extracts the ALT_I2C_IC_INTR_STAT_R_RX_FULL field value from a register. */
2689 #define ALT_I2C_IC_INTR_STAT_R_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
2690 /* Produces a ALT_I2C_IC_INTR_STAT_R_RX_FULL register field value suitable for setting the register. */
2691 #define ALT_I2C_IC_INTR_STAT_R_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
2692 
2693 /*
2694  * Field : R_TX_OVER
2695  *
2696  * Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH
2697  *
2698  * and the processor attempts to issue another I2C command by writing to the
2699  *
2700  * IC_DATA_CMD register. When the module is disabled, this bit keeps its level
2701  *
2702  * until the master or slave state machines go into idle, and when ic_en goes to 0,
2703  *
2704  * this interrupt is cleared.
2705  *
2706  * Reset value: 0x0
2707  *
2708  * Field Enumeration Values:
2709  *
2710  * Enum | Value | Description
2711  * :------------------------------------------|:------|:--------------------------------
2712  * ALT_I2C_IC_INTR_STAT_R_TX_OVER_E_INACTIVE | 0x0 | R_TX_OVER interrupt is inactive
2713  * ALT_I2C_IC_INTR_STAT_R_TX_OVER_E_ACTIVE | 0x1 | R_TX_OVER interrupt is active
2714  *
2715  * Field Access Macros:
2716  *
2717  */
2718 /*
2719  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_TX_OVER
2720  *
2721  * R_TX_OVER interrupt is inactive
2722  */
2723 #define ALT_I2C_IC_INTR_STAT_R_TX_OVER_E_INACTIVE 0x0
2724 /*
2725  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_TX_OVER
2726  *
2727  * R_TX_OVER interrupt is active
2728  */
2729 #define ALT_I2C_IC_INTR_STAT_R_TX_OVER_E_ACTIVE 0x1
2730 
2731 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_STAT_R_TX_OVER register field. */
2732 #define ALT_I2C_IC_INTR_STAT_R_TX_OVER_LSB 3
2733 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_STAT_R_TX_OVER register field. */
2734 #define ALT_I2C_IC_INTR_STAT_R_TX_OVER_MSB 3
2735 /* The width in bits of the ALT_I2C_IC_INTR_STAT_R_TX_OVER register field. */
2736 #define ALT_I2C_IC_INTR_STAT_R_TX_OVER_WIDTH 1
2737 /* The mask used to set the ALT_I2C_IC_INTR_STAT_R_TX_OVER register field value. */
2738 #define ALT_I2C_IC_INTR_STAT_R_TX_OVER_SET_MSK 0x00000008
2739 /* The mask used to clear the ALT_I2C_IC_INTR_STAT_R_TX_OVER register field value. */
2740 #define ALT_I2C_IC_INTR_STAT_R_TX_OVER_CLR_MSK 0xfffffff7
2741 /* The reset value of the ALT_I2C_IC_INTR_STAT_R_TX_OVER register field. */
2742 #define ALT_I2C_IC_INTR_STAT_R_TX_OVER_RESET 0x0
2743 /* Extracts the ALT_I2C_IC_INTR_STAT_R_TX_OVER field value from a register. */
2744 #define ALT_I2C_IC_INTR_STAT_R_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
2745 /* Produces a ALT_I2C_IC_INTR_STAT_R_TX_OVER register field value suitable for setting the register. */
2746 #define ALT_I2C_IC_INTR_STAT_R_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
2747 
2748 /*
2749  * Field : R_TX_EMPTY
2750  *
2751  * The behavior of the TX_EMPTY interrupt status differs based on the
2752  *
2753  * TX_EMPTY_CTRL selection in the IC_CON register.
2754  *
2755  * When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or
2756  * below the threshold
2757  *
2758  * value set in the IC_TX_TL register.
2759  *
2760  * When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or
2761  * below the threshold
2762  *
2763  * value set in the IC_TX_TL register and the transmission of the
2764  *
2765  * address/data from the internal shift register for the most recently popped
2766  *
2767  * command is completed.
2768  *
2769  * It is automatically cleared by hardware when the buffer level goes above the
2770  *
2771  * threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in
2772  *
2773  * reset. There the TX FIFO looks like it has no data within it, so this bit is set
2774  *
2775  * to 1, provided there is activity in the master or slave state machines. When
2776  *
2777  * there is no longer any activity, then with ic_en=0, this bit is set to 0.
2778  *
2779  * Reset value: 0x0
2780  *
2781  * Field Enumeration Values:
2782  *
2783  * Enum | Value | Description
2784  * :-------------------------------------------|:------|:---------------------------------
2785  * ALT_I2C_IC_INTR_STAT_R_TX_EMPTY_E_INACTIVE | 0x0 | R_TX_EMPTY interrupt is inactive
2786  * ALT_I2C_IC_INTR_STAT_R_TX_EMPTY_E_ACTIVE | 0x1 | R_TX_EMPTY interrupt is active
2787  *
2788  * Field Access Macros:
2789  *
2790  */
2791 /*
2792  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_TX_EMPTY
2793  *
2794  * R_TX_EMPTY interrupt is inactive
2795  */
2796 #define ALT_I2C_IC_INTR_STAT_R_TX_EMPTY_E_INACTIVE 0x0
2797 /*
2798  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_TX_EMPTY
2799  *
2800  * R_TX_EMPTY interrupt is active
2801  */
2802 #define ALT_I2C_IC_INTR_STAT_R_TX_EMPTY_E_ACTIVE 0x1
2803 
2804 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_STAT_R_TX_EMPTY register field. */
2805 #define ALT_I2C_IC_INTR_STAT_R_TX_EMPTY_LSB 4
2806 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_STAT_R_TX_EMPTY register field. */
2807 #define ALT_I2C_IC_INTR_STAT_R_TX_EMPTY_MSB 4
2808 /* The width in bits of the ALT_I2C_IC_INTR_STAT_R_TX_EMPTY register field. */
2809 #define ALT_I2C_IC_INTR_STAT_R_TX_EMPTY_WIDTH 1
2810 /* The mask used to set the ALT_I2C_IC_INTR_STAT_R_TX_EMPTY register field value. */
2811 #define ALT_I2C_IC_INTR_STAT_R_TX_EMPTY_SET_MSK 0x00000010
2812 /* The mask used to clear the ALT_I2C_IC_INTR_STAT_R_TX_EMPTY register field value. */
2813 #define ALT_I2C_IC_INTR_STAT_R_TX_EMPTY_CLR_MSK 0xffffffef
2814 /* The reset value of the ALT_I2C_IC_INTR_STAT_R_TX_EMPTY register field. */
2815 #define ALT_I2C_IC_INTR_STAT_R_TX_EMPTY_RESET 0x0
2816 /* Extracts the ALT_I2C_IC_INTR_STAT_R_TX_EMPTY field value from a register. */
2817 #define ALT_I2C_IC_INTR_STAT_R_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
2818 /* Produces a ALT_I2C_IC_INTR_STAT_R_TX_EMPTY register field value suitable for setting the register. */
2819 #define ALT_I2C_IC_INTR_STAT_R_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
2820 
2821 /*
2822  * Field : R_RD_REQ
2823  *
2824  * This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C
2825  *
2826  * master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds
2827  *
2828  * the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which
2829  * means
2830  *
2831  * that the slave has been addressed by a remote master that is asking for data to
2832  *
2833  * be transferred. The processor must respond to this interrupt and then write the
2834  *
2835  * requested data to the IC_DATA_CMD register. This bit is set to 0 just after the
2836  *
2837  * processor reads the IC_CLR_RD_REQ register.
2838  *
2839  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
2840  *
2841  * Reset value: 0x0
2842  *
2843  * Field Enumeration Values:
2844  *
2845  * Enum | Value | Description
2846  * :-----------------------------------------|:------|:-------------------------------
2847  * ALT_I2C_IC_INTR_STAT_R_RD_REQ_E_INACTIVE | 0x0 | R_RD_REQ interrupt is inactive
2848  * ALT_I2C_IC_INTR_STAT_R_RD_REQ_E_ACTIVE | 0x1 | R_RD_REQ interrupt is active
2849  *
2850  * Field Access Macros:
2851  *
2852  */
2853 /*
2854  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_RD_REQ
2855  *
2856  * R_RD_REQ interrupt is inactive
2857  */
2858 #define ALT_I2C_IC_INTR_STAT_R_RD_REQ_E_INACTIVE 0x0
2859 /*
2860  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_RD_REQ
2861  *
2862  * R_RD_REQ interrupt is active
2863  */
2864 #define ALT_I2C_IC_INTR_STAT_R_RD_REQ_E_ACTIVE 0x1
2865 
2866 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_STAT_R_RD_REQ register field. */
2867 #define ALT_I2C_IC_INTR_STAT_R_RD_REQ_LSB 5
2868 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_STAT_R_RD_REQ register field. */
2869 #define ALT_I2C_IC_INTR_STAT_R_RD_REQ_MSB 5
2870 /* The width in bits of the ALT_I2C_IC_INTR_STAT_R_RD_REQ register field. */
2871 #define ALT_I2C_IC_INTR_STAT_R_RD_REQ_WIDTH 1
2872 /* The mask used to set the ALT_I2C_IC_INTR_STAT_R_RD_REQ register field value. */
2873 #define ALT_I2C_IC_INTR_STAT_R_RD_REQ_SET_MSK 0x00000020
2874 /* The mask used to clear the ALT_I2C_IC_INTR_STAT_R_RD_REQ register field value. */
2875 #define ALT_I2C_IC_INTR_STAT_R_RD_REQ_CLR_MSK 0xffffffdf
2876 /* The reset value of the ALT_I2C_IC_INTR_STAT_R_RD_REQ register field. */
2877 #define ALT_I2C_IC_INTR_STAT_R_RD_REQ_RESET 0x0
2878 /* Extracts the ALT_I2C_IC_INTR_STAT_R_RD_REQ field value from a register. */
2879 #define ALT_I2C_IC_INTR_STAT_R_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
2880 /* Produces a ALT_I2C_IC_INTR_STAT_R_RD_REQ register field value suitable for setting the register. */
2881 #define ALT_I2C_IC_INTR_STAT_R_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
2882 
2883 /*
2884  * Field : R_TX_ABRT
2885  *
2886  * This bit indicates if DW_apb_i2c, as an I2C transmitter,
2887  *
2888  * is unable to complete the intended actions on the
2889  *
2890  * contents of the transmit FIFO. This situation can
2891  *
2892  * occur both as an I2C master or an I2C slave, and is
2893  *
2894  * referred to as a 'transmit abort'.
2895  *
2896  * When this bit is set to 1, the IC_TX_ABRT_SOURCE register
2897  *
2898  * indicates the reason why the transmit abort takes places.
2899  *
2900  * NOTE: The DW_apb_i2c flushes/resets/empties the TX FIFO whenever this
2901  *
2902  * bit is set. The TX FIFO remains in this flushed state until the register
2903  *
2904  * IC_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then
2905  *
2906  * ready to accept more data bytes from the APB interface.
2907  *
2908  * Reset value: 0x0
2909  *
2910  * Field Enumeration Values:
2911  *
2912  * Enum | Value | Description
2913  * :------------------------------------------|:------|:--------------------------------
2914  * ALT_I2C_IC_INTR_STAT_R_TX_ABRT_E_INACTIVE | 0x0 | R_TX_ABRT interrupt is inactive
2915  * ALT_I2C_IC_INTR_STAT_R_TX_ABRT_E_ACTIVE | 0x1 | R_TX_ABRT interrupt is active
2916  *
2917  * Field Access Macros:
2918  *
2919  */
2920 /*
2921  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_TX_ABRT
2922  *
2923  * R_TX_ABRT interrupt is inactive
2924  */
2925 #define ALT_I2C_IC_INTR_STAT_R_TX_ABRT_E_INACTIVE 0x0
2926 /*
2927  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_TX_ABRT
2928  *
2929  * R_TX_ABRT interrupt is active
2930  */
2931 #define ALT_I2C_IC_INTR_STAT_R_TX_ABRT_E_ACTIVE 0x1
2932 
2933 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_STAT_R_TX_ABRT register field. */
2934 #define ALT_I2C_IC_INTR_STAT_R_TX_ABRT_LSB 6
2935 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_STAT_R_TX_ABRT register field. */
2936 #define ALT_I2C_IC_INTR_STAT_R_TX_ABRT_MSB 6
2937 /* The width in bits of the ALT_I2C_IC_INTR_STAT_R_TX_ABRT register field. */
2938 #define ALT_I2C_IC_INTR_STAT_R_TX_ABRT_WIDTH 1
2939 /* The mask used to set the ALT_I2C_IC_INTR_STAT_R_TX_ABRT register field value. */
2940 #define ALT_I2C_IC_INTR_STAT_R_TX_ABRT_SET_MSK 0x00000040
2941 /* The mask used to clear the ALT_I2C_IC_INTR_STAT_R_TX_ABRT register field value. */
2942 #define ALT_I2C_IC_INTR_STAT_R_TX_ABRT_CLR_MSK 0xffffffbf
2943 /* The reset value of the ALT_I2C_IC_INTR_STAT_R_TX_ABRT register field. */
2944 #define ALT_I2C_IC_INTR_STAT_R_TX_ABRT_RESET 0x0
2945 /* Extracts the ALT_I2C_IC_INTR_STAT_R_TX_ABRT field value from a register. */
2946 #define ALT_I2C_IC_INTR_STAT_R_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
2947 /* Produces a ALT_I2C_IC_INTR_STAT_R_TX_ABRT register field value suitable for setting the register. */
2948 #define ALT_I2C_IC_INTR_STAT_R_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
2949 
2950 /*
2951  * Field : R_RX_DONE
2952  *
2953  * When the DW_apb_i2c is acting as a slave-transmitter,
2954  *
2955  * this bit is set to 1 if the master does not acknowledge
2956  *
2957  * a transmitted byte. This occurs on the last byte of
2958  *
2959  * the transmission, indicating that the transmission is done.
2960  *
2961  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
2962  *
2963  * Reset value: 0x0
2964  *
2965  * Field Enumeration Values:
2966  *
2967  * Enum | Value | Description
2968  * :------------------------------------------|:------|:--------------------------------
2969  * ALT_I2C_IC_INTR_STAT_R_RX_DONE_E_INACTIVE | 0x0 | R_RX_DONE interrupt is inactive
2970  * ALT_I2C_IC_INTR_STAT_R_RX_DONE_E_ACTIVE | 0x1 | R_RX_DONE interrupt is active
2971  *
2972  * Field Access Macros:
2973  *
2974  */
2975 /*
2976  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_RX_DONE
2977  *
2978  * R_RX_DONE interrupt is inactive
2979  */
2980 #define ALT_I2C_IC_INTR_STAT_R_RX_DONE_E_INACTIVE 0x0
2981 /*
2982  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_RX_DONE
2983  *
2984  * R_RX_DONE interrupt is active
2985  */
2986 #define ALT_I2C_IC_INTR_STAT_R_RX_DONE_E_ACTIVE 0x1
2987 
2988 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_STAT_R_RX_DONE register field. */
2989 #define ALT_I2C_IC_INTR_STAT_R_RX_DONE_LSB 7
2990 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_STAT_R_RX_DONE register field. */
2991 #define ALT_I2C_IC_INTR_STAT_R_RX_DONE_MSB 7
2992 /* The width in bits of the ALT_I2C_IC_INTR_STAT_R_RX_DONE register field. */
2993 #define ALT_I2C_IC_INTR_STAT_R_RX_DONE_WIDTH 1
2994 /* The mask used to set the ALT_I2C_IC_INTR_STAT_R_RX_DONE register field value. */
2995 #define ALT_I2C_IC_INTR_STAT_R_RX_DONE_SET_MSK 0x00000080
2996 /* The mask used to clear the ALT_I2C_IC_INTR_STAT_R_RX_DONE register field value. */
2997 #define ALT_I2C_IC_INTR_STAT_R_RX_DONE_CLR_MSK 0xffffff7f
2998 /* The reset value of the ALT_I2C_IC_INTR_STAT_R_RX_DONE register field. */
2999 #define ALT_I2C_IC_INTR_STAT_R_RX_DONE_RESET 0x0
3000 /* Extracts the ALT_I2C_IC_INTR_STAT_R_RX_DONE field value from a register. */
3001 #define ALT_I2C_IC_INTR_STAT_R_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
3002 /* Produces a ALT_I2C_IC_INTR_STAT_R_RX_DONE register field value suitable for setting the register. */
3003 #define ALT_I2C_IC_INTR_STAT_R_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
3004 
3005 /*
3006  * Field : R_ACTIVITY
3007  *
3008  * This bit captures DW_apb_i2c activity and stays set until it is cleared. There
3009  *
3010  * are four ways to clear it:
3011  *
3012  * * Disabling the DW_apb_i2c
3013  *
3014  * * Reading the IC_CLR_ACTIVITY register
3015  *
3016  * * Reading the IC_CLR_INTR register
3017  *
3018  * * System reset
3019  *
3020  * Once this bit is set, it stays set unless one of the four methods is used to
3021  * clear it.
3022  *
3023  * Even if the DW_apb_i2c module is idle, this bit remains set until cleared,
3024  *
3025  * indicating that there was activity on the bus.
3026  *
3027  * Reset value: 0x0
3028  *
3029  * Field Enumeration Values:
3030  *
3031  * Enum | Value | Description
3032  * :-------------------------------------------|:------|:---------------------------------
3033  * ALT_I2C_IC_INTR_STAT_R_ACTIVITY_E_INACTIVE | 0x0 | R_ACTIVITY interrupt is inactive
3034  * ALT_I2C_IC_INTR_STAT_R_ACTIVITY_E_ACTIVE | 0x1 | R_ACTIVITY interrupt is active
3035  *
3036  * Field Access Macros:
3037  *
3038  */
3039 /*
3040  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_ACTIVITY
3041  *
3042  * R_ACTIVITY interrupt is inactive
3043  */
3044 #define ALT_I2C_IC_INTR_STAT_R_ACTIVITY_E_INACTIVE 0x0
3045 /*
3046  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_ACTIVITY
3047  *
3048  * R_ACTIVITY interrupt is active
3049  */
3050 #define ALT_I2C_IC_INTR_STAT_R_ACTIVITY_E_ACTIVE 0x1
3051 
3052 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_STAT_R_ACTIVITY register field. */
3053 #define ALT_I2C_IC_INTR_STAT_R_ACTIVITY_LSB 8
3054 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_STAT_R_ACTIVITY register field. */
3055 #define ALT_I2C_IC_INTR_STAT_R_ACTIVITY_MSB 8
3056 /* The width in bits of the ALT_I2C_IC_INTR_STAT_R_ACTIVITY register field. */
3057 #define ALT_I2C_IC_INTR_STAT_R_ACTIVITY_WIDTH 1
3058 /* The mask used to set the ALT_I2C_IC_INTR_STAT_R_ACTIVITY register field value. */
3059 #define ALT_I2C_IC_INTR_STAT_R_ACTIVITY_SET_MSK 0x00000100
3060 /* The mask used to clear the ALT_I2C_IC_INTR_STAT_R_ACTIVITY register field value. */
3061 #define ALT_I2C_IC_INTR_STAT_R_ACTIVITY_CLR_MSK 0xfffffeff
3062 /* The reset value of the ALT_I2C_IC_INTR_STAT_R_ACTIVITY register field. */
3063 #define ALT_I2C_IC_INTR_STAT_R_ACTIVITY_RESET 0x0
3064 /* Extracts the ALT_I2C_IC_INTR_STAT_R_ACTIVITY field value from a register. */
3065 #define ALT_I2C_IC_INTR_STAT_R_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
3066 /* Produces a ALT_I2C_IC_INTR_STAT_R_ACTIVITY register field value suitable for setting the register. */
3067 #define ALT_I2C_IC_INTR_STAT_R_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
3068 
3069 /*
3070  * Field : R_STOP_DET
3071  *
3072  * The behavior of the STOP_DET interrupt status differs based on the
3073  *
3074  * STOP_DET_IFADDRESSED selection in the IC_CON register
3075  *
3076  * When STOP_DET_IFADDRESSED =0 : Indicates whether a STOP condition has occurred
3077  * on the I2C interface
3078  *
3079  * regardless of whether DW_apb_i2c is operating in slave or master mode.
3080  *
3081  * In slave mode, a STOP_DET interrupt is generated irrespective of whether
3082  *
3083  * the slave is addressed or not.
3084  *
3085  * When STOP_DET_IFADDRESSED = 1 :
3086  *
3087  * In Master Mode (MASTER_MODE = 1'b1), indicates a STOP condition has occured on
3088  * the I2C interface.
3089  *
3090  * In Slave Mode (MASTER_MODE = 1'b0),STOP_DET interrupt is generated only if the
3091  * slave is addressed.
3092  *
3093  * NOTE: During a general call address, this slave does not issue a STOP_DET
3094  *
3095  * interrupt if STOP_DET_IFADDRESSED=1'b1, even if the slave responds to
3096  *
3097  * the general call address by generating ACK. The STOP_DET interrupt is
3098  *
3099  * generated only when the transmitted address matches the slave address
3100  *
3101  * (SAR).
3102  *
3103  * Reset value: 0x0
3104  *
3105  * Field Enumeration Values:
3106  *
3107  * Enum | Value | Description
3108  * :-------------------------------------------|:------|:---------------------------------
3109  * ALT_I2C_IC_INTR_STAT_R_STOP_DET_E_INACTIVE | 0x0 | R_STOP_DET interrupt is inactive
3110  * ALT_I2C_IC_INTR_STAT_R_STOP_DET_E_ACTIVE | 0x1 | R_STOP_DET interrupt is active
3111  *
3112  * Field Access Macros:
3113  *
3114  */
3115 /*
3116  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_STOP_DET
3117  *
3118  * R_STOP_DET interrupt is inactive
3119  */
3120 #define ALT_I2C_IC_INTR_STAT_R_STOP_DET_E_INACTIVE 0x0
3121 /*
3122  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_STOP_DET
3123  *
3124  * R_STOP_DET interrupt is active
3125  */
3126 #define ALT_I2C_IC_INTR_STAT_R_STOP_DET_E_ACTIVE 0x1
3127 
3128 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_STAT_R_STOP_DET register field. */
3129 #define ALT_I2C_IC_INTR_STAT_R_STOP_DET_LSB 9
3130 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_STAT_R_STOP_DET register field. */
3131 #define ALT_I2C_IC_INTR_STAT_R_STOP_DET_MSB 9
3132 /* The width in bits of the ALT_I2C_IC_INTR_STAT_R_STOP_DET register field. */
3133 #define ALT_I2C_IC_INTR_STAT_R_STOP_DET_WIDTH 1
3134 /* The mask used to set the ALT_I2C_IC_INTR_STAT_R_STOP_DET register field value. */
3135 #define ALT_I2C_IC_INTR_STAT_R_STOP_DET_SET_MSK 0x00000200
3136 /* The mask used to clear the ALT_I2C_IC_INTR_STAT_R_STOP_DET register field value. */
3137 #define ALT_I2C_IC_INTR_STAT_R_STOP_DET_CLR_MSK 0xfffffdff
3138 /* The reset value of the ALT_I2C_IC_INTR_STAT_R_STOP_DET register field. */
3139 #define ALT_I2C_IC_INTR_STAT_R_STOP_DET_RESET 0x0
3140 /* Extracts the ALT_I2C_IC_INTR_STAT_R_STOP_DET field value from a register. */
3141 #define ALT_I2C_IC_INTR_STAT_R_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
3142 /* Produces a ALT_I2C_IC_INTR_STAT_R_STOP_DET register field value suitable for setting the register. */
3143 #define ALT_I2C_IC_INTR_STAT_R_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
3144 
3145 /*
3146  * Field : R_START_DET
3147  *
3148  * Indicates whether a START or RESTART condition has occurred on the I2C
3149  *
3150  * interface regardless of whether DW_apb_i2c is operating in slave or master
3151  *
3152  * mode.
3153  *
3154  * Reset value: 0x0
3155  *
3156  * Field Enumeration Values:
3157  *
3158  * Enum | Value | Description
3159  * :--------------------------------------------|:------|:----------------------------------
3160  * ALT_I2C_IC_INTR_STAT_R_START_DET_E_INACTIVE | 0x0 | R_START_DET interrupt is inactive
3161  * ALT_I2C_IC_INTR_STAT_R_START_DET_E_ACTIVE | 0x1 | R_START_DET interrupt is active
3162  *
3163  * Field Access Macros:
3164  *
3165  */
3166 /*
3167  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_START_DET
3168  *
3169  * R_START_DET interrupt is inactive
3170  */
3171 #define ALT_I2C_IC_INTR_STAT_R_START_DET_E_INACTIVE 0x0
3172 /*
3173  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_START_DET
3174  *
3175  * R_START_DET interrupt is active
3176  */
3177 #define ALT_I2C_IC_INTR_STAT_R_START_DET_E_ACTIVE 0x1
3178 
3179 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_STAT_R_START_DET register field. */
3180 #define ALT_I2C_IC_INTR_STAT_R_START_DET_LSB 10
3181 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_STAT_R_START_DET register field. */
3182 #define ALT_I2C_IC_INTR_STAT_R_START_DET_MSB 10
3183 /* The width in bits of the ALT_I2C_IC_INTR_STAT_R_START_DET register field. */
3184 #define ALT_I2C_IC_INTR_STAT_R_START_DET_WIDTH 1
3185 /* The mask used to set the ALT_I2C_IC_INTR_STAT_R_START_DET register field value. */
3186 #define ALT_I2C_IC_INTR_STAT_R_START_DET_SET_MSK 0x00000400
3187 /* The mask used to clear the ALT_I2C_IC_INTR_STAT_R_START_DET register field value. */
3188 #define ALT_I2C_IC_INTR_STAT_R_START_DET_CLR_MSK 0xfffffbff
3189 /* The reset value of the ALT_I2C_IC_INTR_STAT_R_START_DET register field. */
3190 #define ALT_I2C_IC_INTR_STAT_R_START_DET_RESET 0x0
3191 /* Extracts the ALT_I2C_IC_INTR_STAT_R_START_DET field value from a register. */
3192 #define ALT_I2C_IC_INTR_STAT_R_START_DET_GET(value) (((value) & 0x00000400) >> 10)
3193 /* Produces a ALT_I2C_IC_INTR_STAT_R_START_DET register field value suitable for setting the register. */
3194 #define ALT_I2C_IC_INTR_STAT_R_START_DET_SET(value) (((value) << 10) & 0x00000400)
3195 
3196 /*
3197  * Field : R_GEN_CALL
3198  *
3199  * Set only when a General Call address is received and it is acknowledged. It
3200  *
3201  * stays set until it is cleared either by disabling DW_apb_i2c or when the CPU
3202  *
3203  * reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the
3204  *
3205  * received data in the Rx buffer.
3206  *
3207  * Reset value: 0x0
3208  *
3209  * Field Enumeration Values:
3210  *
3211  * Enum | Value | Description
3212  * :-------------------------------------------|:------|:---------------------------------
3213  * ALT_I2C_IC_INTR_STAT_R_GEN_CALL_E_INACTIVE | 0x0 | R_GEN_CALL interrupt is inactive
3214  * ALT_I2C_IC_INTR_STAT_R_GEN_CALL_E_ACTIVE | 0x1 | R_GEN_CALL interrupt is active
3215  *
3216  * Field Access Macros:
3217  *
3218  */
3219 /*
3220  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_GEN_CALL
3221  *
3222  * R_GEN_CALL interrupt is inactive
3223  */
3224 #define ALT_I2C_IC_INTR_STAT_R_GEN_CALL_E_INACTIVE 0x0
3225 /*
3226  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_GEN_CALL
3227  *
3228  * R_GEN_CALL interrupt is active
3229  */
3230 #define ALT_I2C_IC_INTR_STAT_R_GEN_CALL_E_ACTIVE 0x1
3231 
3232 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_STAT_R_GEN_CALL register field. */
3233 #define ALT_I2C_IC_INTR_STAT_R_GEN_CALL_LSB 11
3234 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_STAT_R_GEN_CALL register field. */
3235 #define ALT_I2C_IC_INTR_STAT_R_GEN_CALL_MSB 11
3236 /* The width in bits of the ALT_I2C_IC_INTR_STAT_R_GEN_CALL register field. */
3237 #define ALT_I2C_IC_INTR_STAT_R_GEN_CALL_WIDTH 1
3238 /* The mask used to set the ALT_I2C_IC_INTR_STAT_R_GEN_CALL register field value. */
3239 #define ALT_I2C_IC_INTR_STAT_R_GEN_CALL_SET_MSK 0x00000800
3240 /* The mask used to clear the ALT_I2C_IC_INTR_STAT_R_GEN_CALL register field value. */
3241 #define ALT_I2C_IC_INTR_STAT_R_GEN_CALL_CLR_MSK 0xfffff7ff
3242 /* The reset value of the ALT_I2C_IC_INTR_STAT_R_GEN_CALL register field. */
3243 #define ALT_I2C_IC_INTR_STAT_R_GEN_CALL_RESET 0x0
3244 /* Extracts the ALT_I2C_IC_INTR_STAT_R_GEN_CALL field value from a register. */
3245 #define ALT_I2C_IC_INTR_STAT_R_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
3246 /* Produces a ALT_I2C_IC_INTR_STAT_R_GEN_CALL register field value suitable for setting the register. */
3247 #define ALT_I2C_IC_INTR_STAT_R_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
3248 
3249 /*
3250  * Field : R_RESTART_DET
3251  *
3252  * Indicates a RESTART condition has occurred on the I2C
3253  *
3254  * interface when DW_apb_i2c is operating in slave mode and addressed. This feature
3255  * is avaliable only when IC_SLV_RESTART_DET_EN is enabled.
3256  *
3257  * Reset value: 0x0
3258  *
3259  * Field Enumeration Values:
3260  *
3261  * Enum | Value | Description
3262  * :----------------------------------------------|:------|:------------------------------------
3263  * ALT_I2C_IC_INTR_STAT_R_RESTART_DET_E_INACTIVE | 0x0 | R_RESTART_DET interrupt is inactive
3264  * ALT_I2C_IC_INTR_STAT_R_RESTART_DET_E_ACTIVE | 0x1 | R_RESTART_DET interrupt is active
3265  *
3266  * Field Access Macros:
3267  *
3268  */
3269 /*
3270  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_RESTART_DET
3271  *
3272  * R_RESTART_DET interrupt is inactive
3273  */
3274 #define ALT_I2C_IC_INTR_STAT_R_RESTART_DET_E_INACTIVE 0x0
3275 /*
3276  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_RESTART_DET
3277  *
3278  * R_RESTART_DET interrupt is active
3279  */
3280 #define ALT_I2C_IC_INTR_STAT_R_RESTART_DET_E_ACTIVE 0x1
3281 
3282 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_STAT_R_RESTART_DET register field. */
3283 #define ALT_I2C_IC_INTR_STAT_R_RESTART_DET_LSB 12
3284 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_STAT_R_RESTART_DET register field. */
3285 #define ALT_I2C_IC_INTR_STAT_R_RESTART_DET_MSB 12
3286 /* The width in bits of the ALT_I2C_IC_INTR_STAT_R_RESTART_DET register field. */
3287 #define ALT_I2C_IC_INTR_STAT_R_RESTART_DET_WIDTH 1
3288 /* The mask used to set the ALT_I2C_IC_INTR_STAT_R_RESTART_DET register field value. */
3289 #define ALT_I2C_IC_INTR_STAT_R_RESTART_DET_SET_MSK 0x00001000
3290 /* The mask used to clear the ALT_I2C_IC_INTR_STAT_R_RESTART_DET register field value. */
3291 #define ALT_I2C_IC_INTR_STAT_R_RESTART_DET_CLR_MSK 0xffffefff
3292 /* The reset value of the ALT_I2C_IC_INTR_STAT_R_RESTART_DET register field. */
3293 #define ALT_I2C_IC_INTR_STAT_R_RESTART_DET_RESET 0x0
3294 /* Extracts the ALT_I2C_IC_INTR_STAT_R_RESTART_DET field value from a register. */
3295 #define ALT_I2C_IC_INTR_STAT_R_RESTART_DET_GET(value) (((value) & 0x00001000) >> 12)
3296 /* Produces a ALT_I2C_IC_INTR_STAT_R_RESTART_DET register field value suitable for setting the register. */
3297 #define ALT_I2C_IC_INTR_STAT_R_RESTART_DET_SET(value) (((value) << 12) & 0x00001000)
3298 
3299 /*
3300  * Field : R_MASTER_ON_HOLD
3301  *
3302  * Indicates whether master is holding the bus and TX FIFO is empty.
3303  *
3304  * Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and IC_EMPTYFIFO_HOLD_MASTER_EN=1.
3305  *
3306  * Reset value: 0x0
3307  *
3308  * Field Enumeration Values:
3309  *
3310  * Enum | Value | Description
3311  * :-------------------------------------------------|:------|:---------------------------------------
3312  * ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_E_INACTIVE | 0x0 | R_MASTER_ON_HOLD interrupt is inactive
3313  * ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_E_ACTIVE | 0x1 | R_MASTER_ON_HOLD interrupt is active
3314  *
3315  * Field Access Macros:
3316  *
3317  */
3318 /*
3319  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD
3320  *
3321  * R_MASTER_ON_HOLD interrupt is inactive
3322  */
3323 #define ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_E_INACTIVE 0x0
3324 /*
3325  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD
3326  *
3327  * R_MASTER_ON_HOLD interrupt is active
3328  */
3329 #define ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_E_ACTIVE 0x1
3330 
3331 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD register field. */
3332 #define ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_LSB 13
3333 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD register field. */
3334 #define ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_MSB 13
3335 /* The width in bits of the ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD register field. */
3336 #define ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_WIDTH 1
3337 /* The mask used to set the ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD register field value. */
3338 #define ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_SET_MSK 0x00002000
3339 /* The mask used to clear the ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD register field value. */
3340 #define ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_CLR_MSK 0xffffdfff
3341 /* The reset value of the ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD register field. */
3342 #define ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_RESET 0x0
3343 /* Extracts the ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD field value from a register. */
3344 #define ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_GET(value) (((value) & 0x00002000) >> 13)
3345 /* Produces a ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD register field value suitable for setting the register. */
3346 #define ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_SET(value) (((value) << 13) & 0x00002000)
3347 
3348 /*
3349  * Field : RSVD_R_SCL_STUCK_AT_LOW
3350  *
3351  * Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT
3352  * number of ic_clk periods.
3353  *
3354  * This bit is set to 0 just after the user reads the IC_CLR_SCL_STCK_DET
3355  * register.Enabled only when IC_BUS_CLEAR_FEATURE=1
3356  *
3357  * Reset Value = 0x0
3358  *
3359  * Field Enumeration Values:
3360  *
3361  * Enum | Value | Description
3362  * :--------------------------------------------------------|:------|:-----------------------------------------
3363  * ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW_E_INACTIVE | 0x0 | R_SCL_STUCK_AT_LOW interrupt is inactive
3364  * ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW_E_ACTIVE | 0x1 | R_SCL_STUCK_AT_LOW interrupt is active
3365  *
3366  * Field Access Macros:
3367  *
3368  */
3369 /*
3370  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW
3371  *
3372  * R_SCL_STUCK_AT_LOW interrupt is inactive
3373  */
3374 #define ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW_E_INACTIVE 0x0
3375 /*
3376  * Enumerated value for register field ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW
3377  *
3378  * R_SCL_STUCK_AT_LOW interrupt is active
3379  */
3380 #define ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW_E_ACTIVE 0x1
3381 
3382 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW register field. */
3383 #define ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW_LSB 14
3384 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW register field. */
3385 #define ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW_MSB 14
3386 /* The width in bits of the ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW register field. */
3387 #define ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW_WIDTH 1
3388 /* The mask used to set the ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW register field value. */
3389 #define ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW_SET_MSK 0x00004000
3390 /* The mask used to clear the ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW register field value. */
3391 #define ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW_CLR_MSK 0xffffbfff
3392 /* The reset value of the ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW register field. */
3393 #define ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW_RESET 0x0
3394 /* Extracts the ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW field value from a register. */
3395 #define ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW_GET(value) (((value) & 0x00004000) >> 14)
3396 /* Produces a ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW register field value suitable for setting the register. */
3397 #define ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW_SET(value) (((value) << 14) & 0x00004000)
3398 
3399 /*
3400  * Field : RSVD_IC_INTR_STAT
3401  *
3402  * Reserved bits - Read Only
3403  *
3404  * Field Access Macros:
3405  *
3406  */
3407 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT register field. */
3408 #define ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT_LSB 15
3409 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT register field. */
3410 #define ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT_MSB 31
3411 /* The width in bits of the ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT register field. */
3412 #define ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT_WIDTH 17
3413 /* The mask used to set the ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT register field value. */
3414 #define ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT_SET_MSK 0xffff8000
3415 /* The mask used to clear the ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT register field value. */
3416 #define ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT_CLR_MSK 0x00007fff
3417 /* The reset value of the ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT register field. */
3418 #define ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT_RESET 0x0
3419 /* Extracts the ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT field value from a register. */
3420 #define ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT_GET(value) (((value) & 0xffff8000) >> 15)
3421 /* Produces a ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT register field value suitable for setting the register. */
3422 #define ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT_SET(value) (((value) << 15) & 0xffff8000)
3423 
3424 #ifndef __ASSEMBLY__
3425 /*
3426  * WARNING: The C register and register group struct declarations are provided for
3427  * convenience and illustrative purposes. They should, however, be used with
3428  * caution as the C language standard provides no guarantees about the alignment or
3429  * atomicity of device memory accesses. The recommended practice for coding device
3430  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3431  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3432  * alt_write_dword() functions for 64 bit registers.
3433  *
3434  * The struct declaration for register ALT_I2C_IC_INTR_STAT.
3435  */
3436 struct ALT_I2C_IC_INTR_STAT_s
3437 {
3438  const volatile uint32_t R_RX_UNDER : 1; /* ALT_I2C_IC_INTR_STAT_R_RX_UNDER */
3439  const volatile uint32_t R_RX_OVER : 1; /* ALT_I2C_IC_INTR_STAT_R_RX_OVER */
3440  const volatile uint32_t R_RX_FULL : 1; /* ALT_I2C_IC_INTR_STAT_R_RX_FULL */
3441  const volatile uint32_t R_TX_OVER : 1; /* ALT_I2C_IC_INTR_STAT_R_TX_OVER */
3442  const volatile uint32_t R_TX_EMPTY : 1; /* ALT_I2C_IC_INTR_STAT_R_TX_EMPTY */
3443  const volatile uint32_t R_RD_REQ : 1; /* ALT_I2C_IC_INTR_STAT_R_RD_REQ */
3444  const volatile uint32_t R_TX_ABRT : 1; /* ALT_I2C_IC_INTR_STAT_R_TX_ABRT */
3445  const volatile uint32_t R_RX_DONE : 1; /* ALT_I2C_IC_INTR_STAT_R_RX_DONE */
3446  const volatile uint32_t R_ACTIVITY : 1; /* ALT_I2C_IC_INTR_STAT_R_ACTIVITY */
3447  const volatile uint32_t R_STOP_DET : 1; /* ALT_I2C_IC_INTR_STAT_R_STOP_DET */
3448  const volatile uint32_t R_START_DET : 1; /* ALT_I2C_IC_INTR_STAT_R_START_DET */
3449  const volatile uint32_t R_GEN_CALL : 1; /* ALT_I2C_IC_INTR_STAT_R_GEN_CALL */
3450  const volatile uint32_t R_RESTART_DET : 1; /* ALT_I2C_IC_INTR_STAT_R_RESTART_DET */
3451  const volatile uint32_t R_MASTER_ON_HOLD : 1; /* ALT_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD */
3452  const volatile uint32_t RSVD_R_SCL_STUCK_AT_LOW : 1; /* ALT_I2C_IC_INTR_STAT_RSVD_R_SCL_STUCK_AT_LOW */
3453  const volatile uint32_t RSVD_IC_INTR_STAT : 17; /* ALT_I2C_IC_INTR_STAT_RSVD_IC_INTR_STAT */
3454 };
3455 
3456 /* The typedef declaration for register ALT_I2C_IC_INTR_STAT. */
3457 typedef struct ALT_I2C_IC_INTR_STAT_s ALT_I2C_IC_INTR_STAT_t;
3458 #endif /* __ASSEMBLY__ */
3459 
3460 /* The reset value of the ALT_I2C_IC_INTR_STAT register. */
3461 #define ALT_I2C_IC_INTR_STAT_RESET 0x00000000
3462 /* The byte offset of the ALT_I2C_IC_INTR_STAT register from the beginning of the component. */
3463 #define ALT_I2C_IC_INTR_STAT_OFST 0x2c
3464 /* The address of the ALT_I2C_IC_INTR_STAT register. */
3465 #define ALT_I2C_IC_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_INTR_STAT_OFST))
3466 
3467 /*
3468  * Register : I2C Interrupt Mask Register - IC_INTR_MASK
3469  *
3470  * Name: I2C Interrupt Mask Register
3471  *
3472  * Size: 15 bits
3473  *
3474  * Address Offset: 0x30
3475  *
3476  * Read/Write Access: Read/Write However,
3477  *
3478  * if configuration parameter IC_SLV_RESTART_DET = 0, bit 13 is read only;
3479  *
3480  * if configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0 or
3481  * IC_EMPTYFIFO_HOLD_MASTER_EN = 0, bit 14 is read only.
3482  *
3483  * if configuration parameter IC_BUS_CLEAR_FEATURE = 0, bit 15 is read only.
3484  *
3485  * These bits mask their corresponding interrupt status bits.
3486  *
3487  * They are active high; a value of 0 prevents a bit from
3488  *
3489  * generating an interrupt.
3490  *
3491  * Register Layout
3492  *
3493  * Bits | Access | Reset | Description
3494  * :--------|:-------|:------|:---------------------------------------------
3495  * [0] | RW | 0x1 | ALT_I2C_IC_INTR_MASK_M_RX_UNDER
3496  * [1] | RW | 0x1 | ALT_I2C_IC_INTR_MASK_M_RX_OVER
3497  * [2] | RW | 0x1 | ALT_I2C_IC_INTR_MASK_M_RX_FULL
3498  * [3] | RW | 0x1 | ALT_I2C_IC_INTR_MASK_M_TX_OVER
3499  * [4] | RW | 0x1 | ALT_I2C_IC_INTR_MASK_M_TX_EMPTY
3500  * [5] | RW | 0x1 | ALT_I2C_IC_INTR_MASK_M_RD_REQ
3501  * [6] | RW | 0x1 | ALT_I2C_IC_INTR_MASK_M_TX_ABRT
3502  * [7] | RW | 0x1 | ALT_I2C_IC_INTR_MASK_M_RX_DONE
3503  * [8] | RW | 0x0 | ALT_I2C_IC_INTR_MASK_M_ACTIVITY
3504  * [9] | RW | 0x0 | ALT_I2C_IC_INTR_MASK_M_STOP_DET
3505  * [10] | RW | 0x0 | ALT_I2C_IC_INTR_MASK_M_START_DET
3506  * [11] | RW | 0x1 | ALT_I2C_IC_INTR_MASK_M_GEN_CALL
3507  * [12] | RW | 0x0 | ALT_I2C_IC_INTR_MASK_M_RESTART_DET
3508  * [13] | RW | 0x0 | ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD
3509  * [14] | R | 0x0 | ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW
3510  * [31:15] | R | 0x0 | ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT
3511  *
3512  */
3513 /*
3514  * Field : M_RX_UNDER
3515  *
3516  * This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.
3517  *
3518  * Reset value: 0x1
3519  *
3520  * Field Enumeration Values:
3521  *
3522  * Enum | Value | Description
3523  * :-------------------------------------------|:------|:-------------------------------
3524  * ALT_I2C_IC_INTR_MASK_M_RX_UNDER_E_ENABLED | 0x0 | RX_UNDER interrupt is masked
3525  * ALT_I2C_IC_INTR_MASK_M_RX_UNDER_E_DISABLED | 0x1 | RX_UNDER interrupt is unmasked
3526  *
3527  * Field Access Macros:
3528  *
3529  */
3530 /*
3531  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_RX_UNDER
3532  *
3533  * RX_UNDER interrupt is masked
3534  */
3535 #define ALT_I2C_IC_INTR_MASK_M_RX_UNDER_E_ENABLED 0x0
3536 /*
3537  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_RX_UNDER
3538  *
3539  * RX_UNDER interrupt is unmasked
3540  */
3541 #define ALT_I2C_IC_INTR_MASK_M_RX_UNDER_E_DISABLED 0x1
3542 
3543 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_MASK_M_RX_UNDER register field. */
3544 #define ALT_I2C_IC_INTR_MASK_M_RX_UNDER_LSB 0
3545 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_MASK_M_RX_UNDER register field. */
3546 #define ALT_I2C_IC_INTR_MASK_M_RX_UNDER_MSB 0
3547 /* The width in bits of the ALT_I2C_IC_INTR_MASK_M_RX_UNDER register field. */
3548 #define ALT_I2C_IC_INTR_MASK_M_RX_UNDER_WIDTH 1
3549 /* The mask used to set the ALT_I2C_IC_INTR_MASK_M_RX_UNDER register field value. */
3550 #define ALT_I2C_IC_INTR_MASK_M_RX_UNDER_SET_MSK 0x00000001
3551 /* The mask used to clear the ALT_I2C_IC_INTR_MASK_M_RX_UNDER register field value. */
3552 #define ALT_I2C_IC_INTR_MASK_M_RX_UNDER_CLR_MSK 0xfffffffe
3553 /* The reset value of the ALT_I2C_IC_INTR_MASK_M_RX_UNDER register field. */
3554 #define ALT_I2C_IC_INTR_MASK_M_RX_UNDER_RESET 0x1
3555 /* Extracts the ALT_I2C_IC_INTR_MASK_M_RX_UNDER field value from a register. */
3556 #define ALT_I2C_IC_INTR_MASK_M_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
3557 /* Produces a ALT_I2C_IC_INTR_MASK_M_RX_UNDER register field value suitable for setting the register. */
3558 #define ALT_I2C_IC_INTR_MASK_M_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
3559 
3560 /*
3561  * Field : M_RX_OVER
3562  *
3563  * This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.
3564  *
3565  * Reset value: 0x1
3566  *
3567  * Field Enumeration Values:
3568  *
3569  * Enum | Value | Description
3570  * :------------------------------------------|:------|:------------------------------
3571  * ALT_I2C_IC_INTR_MASK_M_RX_OVER_E_ENABLED | 0x0 | RX_OVER interrupt is masked
3572  * ALT_I2C_IC_INTR_MASK_M_RX_OVER_E_DISABLED | 0x1 | RX_OVER interrupt is unmasked
3573  *
3574  * Field Access Macros:
3575  *
3576  */
3577 /*
3578  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_RX_OVER
3579  *
3580  * RX_OVER interrupt is masked
3581  */
3582 #define ALT_I2C_IC_INTR_MASK_M_RX_OVER_E_ENABLED 0x0
3583 /*
3584  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_RX_OVER
3585  *
3586  * RX_OVER interrupt is unmasked
3587  */
3588 #define ALT_I2C_IC_INTR_MASK_M_RX_OVER_E_DISABLED 0x1
3589 
3590 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_MASK_M_RX_OVER register field. */
3591 #define ALT_I2C_IC_INTR_MASK_M_RX_OVER_LSB 1
3592 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_MASK_M_RX_OVER register field. */
3593 #define ALT_I2C_IC_INTR_MASK_M_RX_OVER_MSB 1
3594 /* The width in bits of the ALT_I2C_IC_INTR_MASK_M_RX_OVER register field. */
3595 #define ALT_I2C_IC_INTR_MASK_M_RX_OVER_WIDTH 1
3596 /* The mask used to set the ALT_I2C_IC_INTR_MASK_M_RX_OVER register field value. */
3597 #define ALT_I2C_IC_INTR_MASK_M_RX_OVER_SET_MSK 0x00000002
3598 /* The mask used to clear the ALT_I2C_IC_INTR_MASK_M_RX_OVER register field value. */
3599 #define ALT_I2C_IC_INTR_MASK_M_RX_OVER_CLR_MSK 0xfffffffd
3600 /* The reset value of the ALT_I2C_IC_INTR_MASK_M_RX_OVER register field. */
3601 #define ALT_I2C_IC_INTR_MASK_M_RX_OVER_RESET 0x1
3602 /* Extracts the ALT_I2C_IC_INTR_MASK_M_RX_OVER field value from a register. */
3603 #define ALT_I2C_IC_INTR_MASK_M_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
3604 /* Produces a ALT_I2C_IC_INTR_MASK_M_RX_OVER register field value suitable for setting the register. */
3605 #define ALT_I2C_IC_INTR_MASK_M_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
3606 
3607 /*
3608  * Field : M_RX_FULL
3609  *
3610  * This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.
3611  *
3612  * Reset value: 0x1
3613  *
3614  * Field Enumeration Values:
3615  *
3616  * Enum | Value | Description
3617  * :------------------------------------------|:------|:------------------------------
3618  * ALT_I2C_IC_INTR_MASK_M_RX_FULL_E_ENABLED | 0x0 | RX_FULL interrupt is masked
3619  * ALT_I2C_IC_INTR_MASK_M_RX_FULL_E_DISABLED | 0x1 | RX_FULL interrupt is unmasked
3620  *
3621  * Field Access Macros:
3622  *
3623  */
3624 /*
3625  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_RX_FULL
3626  *
3627  * RX_FULL interrupt is masked
3628  */
3629 #define ALT_I2C_IC_INTR_MASK_M_RX_FULL_E_ENABLED 0x0
3630 /*
3631  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_RX_FULL
3632  *
3633  * RX_FULL interrupt is unmasked
3634  */
3635 #define ALT_I2C_IC_INTR_MASK_M_RX_FULL_E_DISABLED 0x1
3636 
3637 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_MASK_M_RX_FULL register field. */
3638 #define ALT_I2C_IC_INTR_MASK_M_RX_FULL_LSB 2
3639 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_MASK_M_RX_FULL register field. */
3640 #define ALT_I2C_IC_INTR_MASK_M_RX_FULL_MSB 2
3641 /* The width in bits of the ALT_I2C_IC_INTR_MASK_M_RX_FULL register field. */
3642 #define ALT_I2C_IC_INTR_MASK_M_RX_FULL_WIDTH 1
3643 /* The mask used to set the ALT_I2C_IC_INTR_MASK_M_RX_FULL register field value. */
3644 #define ALT_I2C_IC_INTR_MASK_M_RX_FULL_SET_MSK 0x00000004
3645 /* The mask used to clear the ALT_I2C_IC_INTR_MASK_M_RX_FULL register field value. */
3646 #define ALT_I2C_IC_INTR_MASK_M_RX_FULL_CLR_MSK 0xfffffffb
3647 /* The reset value of the ALT_I2C_IC_INTR_MASK_M_RX_FULL register field. */
3648 #define ALT_I2C_IC_INTR_MASK_M_RX_FULL_RESET 0x1
3649 /* Extracts the ALT_I2C_IC_INTR_MASK_M_RX_FULL field value from a register. */
3650 #define ALT_I2C_IC_INTR_MASK_M_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
3651 /* Produces a ALT_I2C_IC_INTR_MASK_M_RX_FULL register field value suitable for setting the register. */
3652 #define ALT_I2C_IC_INTR_MASK_M_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
3653 
3654 /*
3655  * Field : M_TX_OVER
3656  *
3657  * This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.
3658  *
3659  * Reset value: 0x1
3660  *
3661  * Field Enumeration Values:
3662  *
3663  * Enum | Value | Description
3664  * :------------------------------------------|:------|:------------------------------
3665  * ALT_I2C_IC_INTR_MASK_M_TX_OVER_E_ENABLED | 0x0 | TX_OVER interrupt is masked
3666  * ALT_I2C_IC_INTR_MASK_M_TX_OVER_E_DISABLED | 0x1 | TX_OVER interrupt is unmasked
3667  *
3668  * Field Access Macros:
3669  *
3670  */
3671 /*
3672  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_TX_OVER
3673  *
3674  * TX_OVER interrupt is masked
3675  */
3676 #define ALT_I2C_IC_INTR_MASK_M_TX_OVER_E_ENABLED 0x0
3677 /*
3678  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_TX_OVER
3679  *
3680  * TX_OVER interrupt is unmasked
3681  */
3682 #define ALT_I2C_IC_INTR_MASK_M_TX_OVER_E_DISABLED 0x1
3683 
3684 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_MASK_M_TX_OVER register field. */
3685 #define ALT_I2C_IC_INTR_MASK_M_TX_OVER_LSB 3
3686 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_MASK_M_TX_OVER register field. */
3687 #define ALT_I2C_IC_INTR_MASK_M_TX_OVER_MSB 3
3688 /* The width in bits of the ALT_I2C_IC_INTR_MASK_M_TX_OVER register field. */
3689 #define ALT_I2C_IC_INTR_MASK_M_TX_OVER_WIDTH 1
3690 /* The mask used to set the ALT_I2C_IC_INTR_MASK_M_TX_OVER register field value. */
3691 #define ALT_I2C_IC_INTR_MASK_M_TX_OVER_SET_MSK 0x00000008
3692 /* The mask used to clear the ALT_I2C_IC_INTR_MASK_M_TX_OVER register field value. */
3693 #define ALT_I2C_IC_INTR_MASK_M_TX_OVER_CLR_MSK 0xfffffff7
3694 /* The reset value of the ALT_I2C_IC_INTR_MASK_M_TX_OVER register field. */
3695 #define ALT_I2C_IC_INTR_MASK_M_TX_OVER_RESET 0x1
3696 /* Extracts the ALT_I2C_IC_INTR_MASK_M_TX_OVER field value from a register. */
3697 #define ALT_I2C_IC_INTR_MASK_M_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
3698 /* Produces a ALT_I2C_IC_INTR_MASK_M_TX_OVER register field value suitable for setting the register. */
3699 #define ALT_I2C_IC_INTR_MASK_M_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
3700 
3701 /*
3702  * Field : M_TX_EMPTY
3703  *
3704  * This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.
3705  *
3706  * Reset value: 0x1
3707  *
3708  * Field Enumeration Values:
3709  *
3710  * Enum | Value | Description
3711  * :-------------------------------------------|:------|:-------------------------------
3712  * ALT_I2C_IC_INTR_MASK_M_TX_EMPTY_E_ENABLED | 0x0 | TX_EMPTY interrupt is masked
3713  * ALT_I2C_IC_INTR_MASK_M_TX_EMPTY_E_DISABLED | 0x1 | TX_EMPTY interrupt is unmasked
3714  *
3715  * Field Access Macros:
3716  *
3717  */
3718 /*
3719  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_TX_EMPTY
3720  *
3721  * TX_EMPTY interrupt is masked
3722  */
3723 #define ALT_I2C_IC_INTR_MASK_M_TX_EMPTY_E_ENABLED 0x0
3724 /*
3725  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_TX_EMPTY
3726  *
3727  * TX_EMPTY interrupt is unmasked
3728  */
3729 #define ALT_I2C_IC_INTR_MASK_M_TX_EMPTY_E_DISABLED 0x1
3730 
3731 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_MASK_M_TX_EMPTY register field. */
3732 #define ALT_I2C_IC_INTR_MASK_M_TX_EMPTY_LSB 4
3733 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_MASK_M_TX_EMPTY register field. */
3734 #define ALT_I2C_IC_INTR_MASK_M_TX_EMPTY_MSB 4
3735 /* The width in bits of the ALT_I2C_IC_INTR_MASK_M_TX_EMPTY register field. */
3736 #define ALT_I2C_IC_INTR_MASK_M_TX_EMPTY_WIDTH 1
3737 /* The mask used to set the ALT_I2C_IC_INTR_MASK_M_TX_EMPTY register field value. */
3738 #define ALT_I2C_IC_INTR_MASK_M_TX_EMPTY_SET_MSK 0x00000010
3739 /* The mask used to clear the ALT_I2C_IC_INTR_MASK_M_TX_EMPTY register field value. */
3740 #define ALT_I2C_IC_INTR_MASK_M_TX_EMPTY_CLR_MSK 0xffffffef
3741 /* The reset value of the ALT_I2C_IC_INTR_MASK_M_TX_EMPTY register field. */
3742 #define ALT_I2C_IC_INTR_MASK_M_TX_EMPTY_RESET 0x1
3743 /* Extracts the ALT_I2C_IC_INTR_MASK_M_TX_EMPTY field value from a register. */
3744 #define ALT_I2C_IC_INTR_MASK_M_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
3745 /* Produces a ALT_I2C_IC_INTR_MASK_M_TX_EMPTY register field value suitable for setting the register. */
3746 #define ALT_I2C_IC_INTR_MASK_M_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
3747 
3748 /*
3749  * Field : M_RD_REQ
3750  *
3751  * This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.
3752  *
3753  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
3754  *
3755  * Reset value: 0x1
3756  *
3757  * Field Enumeration Values:
3758  *
3759  * Enum | Value | Description
3760  * :-----------------------------------------|:------|:-----------------------------
3761  * ALT_I2C_IC_INTR_MASK_M_RD_REQ_E_ENABLED | 0x0 | RD_REQ interrupt is masked
3762  * ALT_I2C_IC_INTR_MASK_M_RD_REQ_E_DISABLED | 0x1 | RD_REQ interrupt is unmasked
3763  *
3764  * Field Access Macros:
3765  *
3766  */
3767 /*
3768  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_RD_REQ
3769  *
3770  * RD_REQ interrupt is masked
3771  */
3772 #define ALT_I2C_IC_INTR_MASK_M_RD_REQ_E_ENABLED 0x0
3773 /*
3774  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_RD_REQ
3775  *
3776  * RD_REQ interrupt is unmasked
3777  */
3778 #define ALT_I2C_IC_INTR_MASK_M_RD_REQ_E_DISABLED 0x1
3779 
3780 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_MASK_M_RD_REQ register field. */
3781 #define ALT_I2C_IC_INTR_MASK_M_RD_REQ_LSB 5
3782 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_MASK_M_RD_REQ register field. */
3783 #define ALT_I2C_IC_INTR_MASK_M_RD_REQ_MSB 5
3784 /* The width in bits of the ALT_I2C_IC_INTR_MASK_M_RD_REQ register field. */
3785 #define ALT_I2C_IC_INTR_MASK_M_RD_REQ_WIDTH 1
3786 /* The mask used to set the ALT_I2C_IC_INTR_MASK_M_RD_REQ register field value. */
3787 #define ALT_I2C_IC_INTR_MASK_M_RD_REQ_SET_MSK 0x00000020
3788 /* The mask used to clear the ALT_I2C_IC_INTR_MASK_M_RD_REQ register field value. */
3789 #define ALT_I2C_IC_INTR_MASK_M_RD_REQ_CLR_MSK 0xffffffdf
3790 /* The reset value of the ALT_I2C_IC_INTR_MASK_M_RD_REQ register field. */
3791 #define ALT_I2C_IC_INTR_MASK_M_RD_REQ_RESET 0x1
3792 /* Extracts the ALT_I2C_IC_INTR_MASK_M_RD_REQ field value from a register. */
3793 #define ALT_I2C_IC_INTR_MASK_M_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
3794 /* Produces a ALT_I2C_IC_INTR_MASK_M_RD_REQ register field value suitable for setting the register. */
3795 #define ALT_I2C_IC_INTR_MASK_M_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
3796 
3797 /*
3798  * Field : M_TX_ABRT
3799  *
3800  * This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.
3801  *
3802  * Reset value: 0x1
3803  *
3804  * Field Enumeration Values:
3805  *
3806  * Enum | Value | Description
3807  * :------------------------------------------|:------|:-------------------------------
3808  * ALT_I2C_IC_INTR_MASK_M_TX_ABRT_E_ENABLED | 0x0 | TX_ABORT interrupt is masked
3809  * ALT_I2C_IC_INTR_MASK_M_TX_ABRT_E_DISABLED | 0x1 | TX_ABORT interrupt is unmasked
3810  *
3811  * Field Access Macros:
3812  *
3813  */
3814 /*
3815  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_TX_ABRT
3816  *
3817  * TX_ABORT interrupt is masked
3818  */
3819 #define ALT_I2C_IC_INTR_MASK_M_TX_ABRT_E_ENABLED 0x0
3820 /*
3821  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_TX_ABRT
3822  *
3823  * TX_ABORT interrupt is unmasked
3824  */
3825 #define ALT_I2C_IC_INTR_MASK_M_TX_ABRT_E_DISABLED 0x1
3826 
3827 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_MASK_M_TX_ABRT register field. */
3828 #define ALT_I2C_IC_INTR_MASK_M_TX_ABRT_LSB 6
3829 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_MASK_M_TX_ABRT register field. */
3830 #define ALT_I2C_IC_INTR_MASK_M_TX_ABRT_MSB 6
3831 /* The width in bits of the ALT_I2C_IC_INTR_MASK_M_TX_ABRT register field. */
3832 #define ALT_I2C_IC_INTR_MASK_M_TX_ABRT_WIDTH 1
3833 /* The mask used to set the ALT_I2C_IC_INTR_MASK_M_TX_ABRT register field value. */
3834 #define ALT_I2C_IC_INTR_MASK_M_TX_ABRT_SET_MSK 0x00000040
3835 /* The mask used to clear the ALT_I2C_IC_INTR_MASK_M_TX_ABRT register field value. */
3836 #define ALT_I2C_IC_INTR_MASK_M_TX_ABRT_CLR_MSK 0xffffffbf
3837 /* The reset value of the ALT_I2C_IC_INTR_MASK_M_TX_ABRT register field. */
3838 #define ALT_I2C_IC_INTR_MASK_M_TX_ABRT_RESET 0x1
3839 /* Extracts the ALT_I2C_IC_INTR_MASK_M_TX_ABRT field value from a register. */
3840 #define ALT_I2C_IC_INTR_MASK_M_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
3841 /* Produces a ALT_I2C_IC_INTR_MASK_M_TX_ABRT register field value suitable for setting the register. */
3842 #define ALT_I2C_IC_INTR_MASK_M_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
3843 
3844 /*
3845  * Field : M_RX_DONE
3846  *
3847  * This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.
3848  *
3849  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
3850  *
3851  * Reset value: 0x1
3852  *
3853  * Field Enumeration Values:
3854  *
3855  * Enum | Value | Description
3856  * :------------------------------------------|:------|:------------------------------
3857  * ALT_I2C_IC_INTR_MASK_M_RX_DONE_E_ENABLED | 0x0 | RX_DONE interrupt is masked
3858  * ALT_I2C_IC_INTR_MASK_M_RX_DONE_E_DISABLED | 0x1 | RX_DONE interrupt is unmasked
3859  *
3860  * Field Access Macros:
3861  *
3862  */
3863 /*
3864  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_RX_DONE
3865  *
3866  * RX_DONE interrupt is masked
3867  */
3868 #define ALT_I2C_IC_INTR_MASK_M_RX_DONE_E_ENABLED 0x0
3869 /*
3870  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_RX_DONE
3871  *
3872  * RX_DONE interrupt is unmasked
3873  */
3874 #define ALT_I2C_IC_INTR_MASK_M_RX_DONE_E_DISABLED 0x1
3875 
3876 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_MASK_M_RX_DONE register field. */
3877 #define ALT_I2C_IC_INTR_MASK_M_RX_DONE_LSB 7
3878 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_MASK_M_RX_DONE register field. */
3879 #define ALT_I2C_IC_INTR_MASK_M_RX_DONE_MSB 7
3880 /* The width in bits of the ALT_I2C_IC_INTR_MASK_M_RX_DONE register field. */
3881 #define ALT_I2C_IC_INTR_MASK_M_RX_DONE_WIDTH 1
3882 /* The mask used to set the ALT_I2C_IC_INTR_MASK_M_RX_DONE register field value. */
3883 #define ALT_I2C_IC_INTR_MASK_M_RX_DONE_SET_MSK 0x00000080
3884 /* The mask used to clear the ALT_I2C_IC_INTR_MASK_M_RX_DONE register field value. */
3885 #define ALT_I2C_IC_INTR_MASK_M_RX_DONE_CLR_MSK 0xffffff7f
3886 /* The reset value of the ALT_I2C_IC_INTR_MASK_M_RX_DONE register field. */
3887 #define ALT_I2C_IC_INTR_MASK_M_RX_DONE_RESET 0x1
3888 /* Extracts the ALT_I2C_IC_INTR_MASK_M_RX_DONE field value from a register. */
3889 #define ALT_I2C_IC_INTR_MASK_M_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
3890 /* Produces a ALT_I2C_IC_INTR_MASK_M_RX_DONE register field value suitable for setting the register. */
3891 #define ALT_I2C_IC_INTR_MASK_M_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
3892 
3893 /*
3894  * Field : M_ACTIVITY
3895  *
3896  * This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.
3897  *
3898  * Reset value: 0x0
3899  *
3900  * Field Enumeration Values:
3901  *
3902  * Enum | Value | Description
3903  * :-------------------------------------------|:------|:-------------------------------
3904  * ALT_I2C_IC_INTR_MASK_M_ACTIVITY_E_ENABLED | 0x0 | ACTIVITY interrupt is masked
3905  * ALT_I2C_IC_INTR_MASK_M_ACTIVITY_E_DISABLED | 0x1 | ACTIVITY interrupt is unmasked
3906  *
3907  * Field Access Macros:
3908  *
3909  */
3910 /*
3911  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_ACTIVITY
3912  *
3913  * ACTIVITY interrupt is masked
3914  */
3915 #define ALT_I2C_IC_INTR_MASK_M_ACTIVITY_E_ENABLED 0x0
3916 /*
3917  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_ACTIVITY
3918  *
3919  * ACTIVITY interrupt is unmasked
3920  */
3921 #define ALT_I2C_IC_INTR_MASK_M_ACTIVITY_E_DISABLED 0x1
3922 
3923 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_MASK_M_ACTIVITY register field. */
3924 #define ALT_I2C_IC_INTR_MASK_M_ACTIVITY_LSB 8
3925 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_MASK_M_ACTIVITY register field. */
3926 #define ALT_I2C_IC_INTR_MASK_M_ACTIVITY_MSB 8
3927 /* The width in bits of the ALT_I2C_IC_INTR_MASK_M_ACTIVITY register field. */
3928 #define ALT_I2C_IC_INTR_MASK_M_ACTIVITY_WIDTH 1
3929 /* The mask used to set the ALT_I2C_IC_INTR_MASK_M_ACTIVITY register field value. */
3930 #define ALT_I2C_IC_INTR_MASK_M_ACTIVITY_SET_MSK 0x00000100
3931 /* The mask used to clear the ALT_I2C_IC_INTR_MASK_M_ACTIVITY register field value. */
3932 #define ALT_I2C_IC_INTR_MASK_M_ACTIVITY_CLR_MSK 0xfffffeff
3933 /* The reset value of the ALT_I2C_IC_INTR_MASK_M_ACTIVITY register field. */
3934 #define ALT_I2C_IC_INTR_MASK_M_ACTIVITY_RESET 0x0
3935 /* Extracts the ALT_I2C_IC_INTR_MASK_M_ACTIVITY field value from a register. */
3936 #define ALT_I2C_IC_INTR_MASK_M_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
3937 /* Produces a ALT_I2C_IC_INTR_MASK_M_ACTIVITY register field value suitable for setting the register. */
3938 #define ALT_I2C_IC_INTR_MASK_M_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
3939 
3940 /*
3941  * Field : M_STOP_DET
3942  *
3943  * This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.
3944  *
3945  * Reset value: 0x0
3946  *
3947  * Field Enumeration Values:
3948  *
3949  * Enum | Value | Description
3950  * :-------------------------------------------|:------|:-------------------------------
3951  * ALT_I2C_IC_INTR_MASK_M_STOP_DET_E_ENABLED | 0x0 | STOP_DET interrupt is masked
3952  * ALT_I2C_IC_INTR_MASK_M_STOP_DET_E_DISABLED | 0x1 | STOP_DET interrupt is unmasked
3953  *
3954  * Field Access Macros:
3955  *
3956  */
3957 /*
3958  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_STOP_DET
3959  *
3960  * STOP_DET interrupt is masked
3961  */
3962 #define ALT_I2C_IC_INTR_MASK_M_STOP_DET_E_ENABLED 0x0
3963 /*
3964  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_STOP_DET
3965  *
3966  * STOP_DET interrupt is unmasked
3967  */
3968 #define ALT_I2C_IC_INTR_MASK_M_STOP_DET_E_DISABLED 0x1
3969 
3970 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_MASK_M_STOP_DET register field. */
3971 #define ALT_I2C_IC_INTR_MASK_M_STOP_DET_LSB 9
3972 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_MASK_M_STOP_DET register field. */
3973 #define ALT_I2C_IC_INTR_MASK_M_STOP_DET_MSB 9
3974 /* The width in bits of the ALT_I2C_IC_INTR_MASK_M_STOP_DET register field. */
3975 #define ALT_I2C_IC_INTR_MASK_M_STOP_DET_WIDTH 1
3976 /* The mask used to set the ALT_I2C_IC_INTR_MASK_M_STOP_DET register field value. */
3977 #define ALT_I2C_IC_INTR_MASK_M_STOP_DET_SET_MSK 0x00000200
3978 /* The mask used to clear the ALT_I2C_IC_INTR_MASK_M_STOP_DET register field value. */
3979 #define ALT_I2C_IC_INTR_MASK_M_STOP_DET_CLR_MSK 0xfffffdff
3980 /* The reset value of the ALT_I2C_IC_INTR_MASK_M_STOP_DET register field. */
3981 #define ALT_I2C_IC_INTR_MASK_M_STOP_DET_RESET 0x0
3982 /* Extracts the ALT_I2C_IC_INTR_MASK_M_STOP_DET field value from a register. */
3983 #define ALT_I2C_IC_INTR_MASK_M_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
3984 /* Produces a ALT_I2C_IC_INTR_MASK_M_STOP_DET register field value suitable for setting the register. */
3985 #define ALT_I2C_IC_INTR_MASK_M_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
3986 
3987 /*
3988  * Field : M_START_DET
3989  *
3990  * This bit masks the R_START_DET interrupt in IC_INTR_STAT register.
3991  *
3992  * Reset value: 0x0
3993  *
3994  * Field Enumeration Values:
3995  *
3996  * Enum | Value | Description
3997  * :--------------------------------------------|:------|:--------------------------------
3998  * ALT_I2C_IC_INTR_MASK_M_START_DET_E_ENABLED | 0x0 | START_DET interrupt is masked
3999  * ALT_I2C_IC_INTR_MASK_M_START_DET_E_DISABLED | 0x1 | START_DET interrupt is unmasked
4000  *
4001  * Field Access Macros:
4002  *
4003  */
4004 /*
4005  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_START_DET
4006  *
4007  * START_DET interrupt is masked
4008  */
4009 #define ALT_I2C_IC_INTR_MASK_M_START_DET_E_ENABLED 0x0
4010 /*
4011  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_START_DET
4012  *
4013  * START_DET interrupt is unmasked
4014  */
4015 #define ALT_I2C_IC_INTR_MASK_M_START_DET_E_DISABLED 0x1
4016 
4017 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_MASK_M_START_DET register field. */
4018 #define ALT_I2C_IC_INTR_MASK_M_START_DET_LSB 10
4019 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_MASK_M_START_DET register field. */
4020 #define ALT_I2C_IC_INTR_MASK_M_START_DET_MSB 10
4021 /* The width in bits of the ALT_I2C_IC_INTR_MASK_M_START_DET register field. */
4022 #define ALT_I2C_IC_INTR_MASK_M_START_DET_WIDTH 1
4023 /* The mask used to set the ALT_I2C_IC_INTR_MASK_M_START_DET register field value. */
4024 #define ALT_I2C_IC_INTR_MASK_M_START_DET_SET_MSK 0x00000400
4025 /* The mask used to clear the ALT_I2C_IC_INTR_MASK_M_START_DET register field value. */
4026 #define ALT_I2C_IC_INTR_MASK_M_START_DET_CLR_MSK 0xfffffbff
4027 /* The reset value of the ALT_I2C_IC_INTR_MASK_M_START_DET register field. */
4028 #define ALT_I2C_IC_INTR_MASK_M_START_DET_RESET 0x0
4029 /* Extracts the ALT_I2C_IC_INTR_MASK_M_START_DET field value from a register. */
4030 #define ALT_I2C_IC_INTR_MASK_M_START_DET_GET(value) (((value) & 0x00000400) >> 10)
4031 /* Produces a ALT_I2C_IC_INTR_MASK_M_START_DET register field value suitable for setting the register. */
4032 #define ALT_I2C_IC_INTR_MASK_M_START_DET_SET(value) (((value) << 10) & 0x00000400)
4033 
4034 /*
4035  * Field : M_GEN_CALL
4036  *
4037  * This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.
4038  *
4039  * Reset value: 0x1
4040  *
4041  * Field Enumeration Values:
4042  *
4043  * Enum | Value | Description
4044  * :-------------------------------------------|:------|:-------------------------------
4045  * ALT_I2C_IC_INTR_MASK_M_GEN_CALL_E_ENABLED | 0x0 | GEN_CALL interrupt is masked
4046  * ALT_I2C_IC_INTR_MASK_M_GEN_CALL_E_DISABLED | 0x1 | GEN_CALL interrupt is unmasked
4047  *
4048  * Field Access Macros:
4049  *
4050  */
4051 /*
4052  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_GEN_CALL
4053  *
4054  * GEN_CALL interrupt is masked
4055  */
4056 #define ALT_I2C_IC_INTR_MASK_M_GEN_CALL_E_ENABLED 0x0
4057 /*
4058  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_GEN_CALL
4059  *
4060  * GEN_CALL interrupt is unmasked
4061  */
4062 #define ALT_I2C_IC_INTR_MASK_M_GEN_CALL_E_DISABLED 0x1
4063 
4064 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_MASK_M_GEN_CALL register field. */
4065 #define ALT_I2C_IC_INTR_MASK_M_GEN_CALL_LSB 11
4066 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_MASK_M_GEN_CALL register field. */
4067 #define ALT_I2C_IC_INTR_MASK_M_GEN_CALL_MSB 11
4068 /* The width in bits of the ALT_I2C_IC_INTR_MASK_M_GEN_CALL register field. */
4069 #define ALT_I2C_IC_INTR_MASK_M_GEN_CALL_WIDTH 1
4070 /* The mask used to set the ALT_I2C_IC_INTR_MASK_M_GEN_CALL register field value. */
4071 #define ALT_I2C_IC_INTR_MASK_M_GEN_CALL_SET_MSK 0x00000800
4072 /* The mask used to clear the ALT_I2C_IC_INTR_MASK_M_GEN_CALL register field value. */
4073 #define ALT_I2C_IC_INTR_MASK_M_GEN_CALL_CLR_MSK 0xfffff7ff
4074 /* The reset value of the ALT_I2C_IC_INTR_MASK_M_GEN_CALL register field. */
4075 #define ALT_I2C_IC_INTR_MASK_M_GEN_CALL_RESET 0x1
4076 /* Extracts the ALT_I2C_IC_INTR_MASK_M_GEN_CALL field value from a register. */
4077 #define ALT_I2C_IC_INTR_MASK_M_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
4078 /* Produces a ALT_I2C_IC_INTR_MASK_M_GEN_CALL register field value suitable for setting the register. */
4079 #define ALT_I2C_IC_INTR_MASK_M_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
4080 
4081 /*
4082  * Field : M_RESTART_DET
4083  *
4084  * This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.
4085  *
4086  * Reset value: 0x0
4087  *
4088  * Field Enumeration Values:
4089  *
4090  * Enum | Value | Description
4091  * :----------------------------------------------|:------|:----------------------------------
4092  * ALT_I2C_IC_INTR_MASK_M_RESTART_DET_E_ENABLED | 0x0 | RESTART_DET interrupt is masked
4093  * ALT_I2C_IC_INTR_MASK_M_RESTART_DET_E_DISABLED | 0x1 | RESTART_DET interrupt is unmasked
4094  *
4095  * Field Access Macros:
4096  *
4097  */
4098 /*
4099  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_RESTART_DET
4100  *
4101  * RESTART_DET interrupt is masked
4102  */
4103 #define ALT_I2C_IC_INTR_MASK_M_RESTART_DET_E_ENABLED 0x0
4104 /*
4105  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_RESTART_DET
4106  *
4107  * RESTART_DET interrupt is unmasked
4108  */
4109 #define ALT_I2C_IC_INTR_MASK_M_RESTART_DET_E_DISABLED 0x1
4110 
4111 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_MASK_M_RESTART_DET register field. */
4112 #define ALT_I2C_IC_INTR_MASK_M_RESTART_DET_LSB 12
4113 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_MASK_M_RESTART_DET register field. */
4114 #define ALT_I2C_IC_INTR_MASK_M_RESTART_DET_MSB 12
4115 /* The width in bits of the ALT_I2C_IC_INTR_MASK_M_RESTART_DET register field. */
4116 #define ALT_I2C_IC_INTR_MASK_M_RESTART_DET_WIDTH 1
4117 /* The mask used to set the ALT_I2C_IC_INTR_MASK_M_RESTART_DET register field value. */
4118 #define ALT_I2C_IC_INTR_MASK_M_RESTART_DET_SET_MSK 0x00001000
4119 /* The mask used to clear the ALT_I2C_IC_INTR_MASK_M_RESTART_DET register field value. */
4120 #define ALT_I2C_IC_INTR_MASK_M_RESTART_DET_CLR_MSK 0xffffefff
4121 /* The reset value of the ALT_I2C_IC_INTR_MASK_M_RESTART_DET register field. */
4122 #define ALT_I2C_IC_INTR_MASK_M_RESTART_DET_RESET 0x0
4123 /* Extracts the ALT_I2C_IC_INTR_MASK_M_RESTART_DET field value from a register. */
4124 #define ALT_I2C_IC_INTR_MASK_M_RESTART_DET_GET(value) (((value) & 0x00001000) >> 12)
4125 /* Produces a ALT_I2C_IC_INTR_MASK_M_RESTART_DET register field value suitable for setting the register. */
4126 #define ALT_I2C_IC_INTR_MASK_M_RESTART_DET_SET(value) (((value) << 12) & 0x00001000)
4127 
4128 /*
4129  * Field : M_MASTER_ON_HOLD
4130  *
4131  * This bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register.
4132  *
4133  * Reset value: 0x0
4134  *
4135  * Field Enumeration Values:
4136  *
4137  * Enum | Value | Description
4138  * :-------------------------------------------------|:------|:-------------------------------------
4139  * ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_E_ENABLED | 0x0 | MASTER_ON_HOLD interrupt is masked
4140  * ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_E_DISABLED | 0x1 | MASTER_ON_HOLD interrupt is unmasked
4141  *
4142  * Field Access Macros:
4143  *
4144  */
4145 /*
4146  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD
4147  *
4148  * MASTER_ON_HOLD interrupt is masked
4149  */
4150 #define ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_E_ENABLED 0x0
4151 /*
4152  * Enumerated value for register field ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD
4153  *
4154  * MASTER_ON_HOLD interrupt is unmasked
4155  */
4156 #define ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_E_DISABLED 0x1
4157 
4158 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD register field. */
4159 #define ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_LSB 13
4160 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD register field. */
4161 #define ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_MSB 13
4162 /* The width in bits of the ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD register field. */
4163 #define ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_WIDTH 1
4164 /* The mask used to set the ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD register field value. */
4165 #define ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_SET_MSK 0x00002000
4166 /* The mask used to clear the ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD register field value. */
4167 #define ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_CLR_MSK 0xffffdfff
4168 /* The reset value of the ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD register field. */
4169 #define ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_RESET 0x0
4170 /* Extracts the ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD field value from a register. */
4171 #define ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_GET(value) (((value) & 0x00002000) >> 13)
4172 /* Produces a ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD register field value suitable for setting the register. */
4173 #define ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_SET(value) (((value) << 13) & 0x00002000)
4174 
4175 /*
4176  * Field : RSVD_M_SCL_STUCK_AT_LOW
4177  *
4178  * Reserved bits - Read Only
4179  *
4180  * Field Access Macros:
4181  *
4182  */
4183 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW register field. */
4184 #define ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW_LSB 14
4185 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW register field. */
4186 #define ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW_MSB 14
4187 /* The width in bits of the ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW register field. */
4188 #define ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW_WIDTH 1
4189 /* The mask used to set the ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW register field value. */
4190 #define ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW_SET_MSK 0x00004000
4191 /* The mask used to clear the ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW register field value. */
4192 #define ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW_CLR_MSK 0xffffbfff
4193 /* The reset value of the ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW register field. */
4194 #define ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW_RESET 0x0
4195 /* Extracts the ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW field value from a register. */
4196 #define ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW_GET(value) (((value) & 0x00004000) >> 14)
4197 /* Produces a ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW register field value suitable for setting the register. */
4198 #define ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW_SET(value) (((value) << 14) & 0x00004000)
4199 
4200 /*
4201  * Field : RSVD_IC_INTR_STAT
4202  *
4203  * Reserved bits - Read Only
4204  *
4205  * Field Access Macros:
4206  *
4207  */
4208 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT register field. */
4209 #define ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT_LSB 15
4210 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT register field. */
4211 #define ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT_MSB 31
4212 /* The width in bits of the ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT register field. */
4213 #define ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT_WIDTH 17
4214 /* The mask used to set the ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT register field value. */
4215 #define ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT_SET_MSK 0xffff8000
4216 /* The mask used to clear the ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT register field value. */
4217 #define ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT_CLR_MSK 0x00007fff
4218 /* The reset value of the ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT register field. */
4219 #define ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT_RESET 0x0
4220 /* Extracts the ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT field value from a register. */
4221 #define ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT_GET(value) (((value) & 0xffff8000) >> 15)
4222 /* Produces a ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT register field value suitable for setting the register. */
4223 #define ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT_SET(value) (((value) << 15) & 0xffff8000)
4224 
4225 #ifndef __ASSEMBLY__
4226 /*
4227  * WARNING: The C register and register group struct declarations are provided for
4228  * convenience and illustrative purposes. They should, however, be used with
4229  * caution as the C language standard provides no guarantees about the alignment or
4230  * atomicity of device memory accesses. The recommended practice for coding device
4231  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4232  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4233  * alt_write_dword() functions for 64 bit registers.
4234  *
4235  * The struct declaration for register ALT_I2C_IC_INTR_MASK.
4236  */
4237 struct ALT_I2C_IC_INTR_MASK_s
4238 {
4239  volatile uint32_t M_RX_UNDER : 1; /* ALT_I2C_IC_INTR_MASK_M_RX_UNDER */
4240  volatile uint32_t M_RX_OVER : 1; /* ALT_I2C_IC_INTR_MASK_M_RX_OVER */
4241  volatile uint32_t M_RX_FULL : 1; /* ALT_I2C_IC_INTR_MASK_M_RX_FULL */
4242  volatile uint32_t M_TX_OVER : 1; /* ALT_I2C_IC_INTR_MASK_M_TX_OVER */
4243  volatile uint32_t M_TX_EMPTY : 1; /* ALT_I2C_IC_INTR_MASK_M_TX_EMPTY */
4244  volatile uint32_t M_RD_REQ : 1; /* ALT_I2C_IC_INTR_MASK_M_RD_REQ */
4245  volatile uint32_t M_TX_ABRT : 1; /* ALT_I2C_IC_INTR_MASK_M_TX_ABRT */
4246  volatile uint32_t M_RX_DONE : 1; /* ALT_I2C_IC_INTR_MASK_M_RX_DONE */
4247  volatile uint32_t M_ACTIVITY : 1; /* ALT_I2C_IC_INTR_MASK_M_ACTIVITY */
4248  volatile uint32_t M_STOP_DET : 1; /* ALT_I2C_IC_INTR_MASK_M_STOP_DET */
4249  volatile uint32_t M_START_DET : 1; /* ALT_I2C_IC_INTR_MASK_M_START_DET */
4250  volatile uint32_t M_GEN_CALL : 1; /* ALT_I2C_IC_INTR_MASK_M_GEN_CALL */
4251  volatile uint32_t M_RESTART_DET : 1; /* ALT_I2C_IC_INTR_MASK_M_RESTART_DET */
4252  volatile uint32_t M_MASTER_ON_HOLD : 1; /* ALT_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD */
4253  const volatile uint32_t RSVD_M_SCL_STUCK_AT_LOW : 1; /* ALT_I2C_IC_INTR_MASK_RSVD_M_SCL_STUCK_AT_LOW */
4254  const volatile uint32_t RSVD_IC_INTR_STAT : 17; /* ALT_I2C_IC_INTR_MASK_RSVD_IC_INTR_STAT */
4255 };
4256 
4257 /* The typedef declaration for register ALT_I2C_IC_INTR_MASK. */
4258 typedef struct ALT_I2C_IC_INTR_MASK_s ALT_I2C_IC_INTR_MASK_t;
4259 #endif /* __ASSEMBLY__ */
4260 
4261 /* The reset value of the ALT_I2C_IC_INTR_MASK register. */
4262 #define ALT_I2C_IC_INTR_MASK_RESET 0x000008ff
4263 /* The byte offset of the ALT_I2C_IC_INTR_MASK register from the beginning of the component. */
4264 #define ALT_I2C_IC_INTR_MASK_OFST 0x30
4265 /* The address of the ALT_I2C_IC_INTR_MASK register. */
4266 #define ALT_I2C_IC_INTR_MASK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_INTR_MASK_OFST))
4267 
4268 /*
4269  * Register : I2C Raw Interrupt Status Register - IC_RAW_INTR_STAT
4270  *
4271  * Name: I2C Raw Interrupt Status Register
4272  *
4273  * Size: 15 bits
4274  *
4275  * Address Offset: 0x34
4276  *
4277  * Read/Write Access: Read
4278  *
4279  * Unlike the IC_INTR_STAT register, these bits are not masked so they
4280  *
4281  * always show the true status of the DW_apb_i2c.
4282  *
4283  * Register Layout
4284  *
4285  * Bits | Access | Reset | Description
4286  * :--------|:-------|:------|:-----------------------------------------------
4287  * [0] | R | 0x0 | ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER
4288  * [1] | R | 0x0 | ALT_I2C_IC_RAW_INTR_STAT_RX_OVER
4289  * [2] | R | 0x0 | ALT_I2C_IC_RAW_INTR_STAT_RX_FULL
4290  * [3] | R | 0x0 | ALT_I2C_IC_RAW_INTR_STAT_TX_OVER
4291  * [4] | R | 0x0 | ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY
4292  * [5] | R | 0x0 | ALT_I2C_IC_RAW_INTR_STAT_RD_REQ
4293  * [6] | R | 0x0 | ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT
4294  * [7] | R | 0x0 | ALT_I2C_IC_RAW_INTR_STAT_RX_DONE
4295  * [8] | R | 0x0 | ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY
4296  * [9] | R | 0x0 | ALT_I2C_IC_RAW_INTR_STAT_STOP_DET
4297  * [10] | R | 0x0 | ALT_I2C_IC_RAW_INTR_STAT_START_DET
4298  * [11] | R | 0x0 | ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL
4299  * [12] | R | 0x0 | ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET
4300  * [13] | R | 0x0 | ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD
4301  * [14] | R | 0x0 | ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW
4302  * [31:15] | R | 0x0 | ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT
4303  *
4304  */
4305 /*
4306  * Field : RX_UNDER
4307  *
4308  * Set if the processor attempts to read the receive buffer when it is empty by
4309  *
4310  * reading from the IC_DATA_CMD register. If the module is disabled
4311  *
4312  * (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state
4313  *
4314  * machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
4315  *
4316  * Reset value: 0x0
4317  *
4318  * Field Enumeration Values:
4319  *
4320  * Enum | Value | Description
4321  * :---------------------------------------------|:------|:-------------------------------
4322  * ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER_E_INACTIVE | 0x0 | RX_UNDER interrupt is inactive
4323  * ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER_E_ACTIVE | 0x1 | RX_UNDER interrupt is active
4324  *
4325  * Field Access Macros:
4326  *
4327  */
4328 /*
4329  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER
4330  *
4331  * RX_UNDER interrupt is inactive
4332  */
4333 #define ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER_E_INACTIVE 0x0
4334 /*
4335  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER
4336  *
4337  * RX_UNDER interrupt is active
4338  */
4339 #define ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER_E_ACTIVE 0x1
4340 
4341 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER register field. */
4342 #define ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER_LSB 0
4343 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER register field. */
4344 #define ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER_MSB 0
4345 /* The width in bits of the ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER register field. */
4346 #define ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER_WIDTH 1
4347 /* The mask used to set the ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER register field value. */
4348 #define ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER_SET_MSK 0x00000001
4349 /* The mask used to clear the ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER register field value. */
4350 #define ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER_CLR_MSK 0xfffffffe
4351 /* The reset value of the ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER register field. */
4352 #define ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER_RESET 0x0
4353 /* Extracts the ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER field value from a register. */
4354 #define ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
4355 /* Produces a ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER register field value suitable for setting the register. */
4356 #define ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
4357 
4358 /*
4359  * Field : RX_OVER
4360  *
4361  * Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and
4362  *
4363  * an additional byte is received from an external I2C device. The DW_apb_i2c
4364  *
4365  * acknowledges this, but any data bytes received after the FIFO is full are lost.
4366  * If
4367  *
4368  * the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the
4369  *
4370  * master or slave state machines go into idle, and when ic_en goes to 0, this
4371  *
4372  * interrupt is cleared.
4373  *
4374  * NOTE: If the parameter IC_RX_FULL_HLD_BUS_EN=1, then the RX_OVER interrupt is
4375  *
4376  * never set to 1, because the criteria to set this interrupt are never met.
4377  *
4378  * Reset value: 0x0
4379  *
4380  * Field Enumeration Values:
4381  *
4382  * Enum | Value | Description
4383  * :--------------------------------------------|:------|:------------------------------
4384  * ALT_I2C_IC_RAW_INTR_STAT_RX_OVER_E_INACTIVE | 0x0 | RX_OVER interrupt is inactive
4385  * ALT_I2C_IC_RAW_INTR_STAT_RX_OVER_E_ACTIVE | 0x1 | RX_OVER interrupt is active
4386  *
4387  * Field Access Macros:
4388  *
4389  */
4390 /*
4391  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_RX_OVER
4392  *
4393  * RX_OVER interrupt is inactive
4394  */
4395 #define ALT_I2C_IC_RAW_INTR_STAT_RX_OVER_E_INACTIVE 0x0
4396 /*
4397  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_RX_OVER
4398  *
4399  * RX_OVER interrupt is active
4400  */
4401 #define ALT_I2C_IC_RAW_INTR_STAT_RX_OVER_E_ACTIVE 0x1
4402 
4403 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_RAW_INTR_STAT_RX_OVER register field. */
4404 #define ALT_I2C_IC_RAW_INTR_STAT_RX_OVER_LSB 1
4405 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_RAW_INTR_STAT_RX_OVER register field. */
4406 #define ALT_I2C_IC_RAW_INTR_STAT_RX_OVER_MSB 1
4407 /* The width in bits of the ALT_I2C_IC_RAW_INTR_STAT_RX_OVER register field. */
4408 #define ALT_I2C_IC_RAW_INTR_STAT_RX_OVER_WIDTH 1
4409 /* The mask used to set the ALT_I2C_IC_RAW_INTR_STAT_RX_OVER register field value. */
4410 #define ALT_I2C_IC_RAW_INTR_STAT_RX_OVER_SET_MSK 0x00000002
4411 /* The mask used to clear the ALT_I2C_IC_RAW_INTR_STAT_RX_OVER register field value. */
4412 #define ALT_I2C_IC_RAW_INTR_STAT_RX_OVER_CLR_MSK 0xfffffffd
4413 /* The reset value of the ALT_I2C_IC_RAW_INTR_STAT_RX_OVER register field. */
4414 #define ALT_I2C_IC_RAW_INTR_STAT_RX_OVER_RESET 0x0
4415 /* Extracts the ALT_I2C_IC_RAW_INTR_STAT_RX_OVER field value from a register. */
4416 #define ALT_I2C_IC_RAW_INTR_STAT_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
4417 /* Produces a ALT_I2C_IC_RAW_INTR_STAT_RX_OVER register field value suitable for setting the register. */
4418 #define ALT_I2C_IC_RAW_INTR_STAT_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
4419 
4420 /*
4421  * Field : RX_FULL
4422  *
4423  * Set when the receive buffer reaches or goes above the RX_TL threshold in the
4424  *
4425  * IC_RX_TL register. It is automatically cleared by hardware when buffer level
4426  *
4427  * goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the
4428  *
4429  * RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this
4430  *
4431  * bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of
4432  *
4433  * the activity that continues.
4434  *
4435  * Reset value: 0x0
4436  *
4437  * Field Enumeration Values:
4438  *
4439  * Enum | Value | Description
4440  * :--------------------------------------------|:------|:------------------------------
4441  * ALT_I2C_IC_RAW_INTR_STAT_RX_FULL_E_INACTIVE | 0x0 | RX_FULL interrupt is inactive
4442  * ALT_I2C_IC_RAW_INTR_STAT_RX_FULL_E_ACTIVE | 0x1 | RX_FULL interrupt is active
4443  *
4444  * Field Access Macros:
4445  *
4446  */
4447 /*
4448  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_RX_FULL
4449  *
4450  * RX_FULL interrupt is inactive
4451  */
4452 #define ALT_I2C_IC_RAW_INTR_STAT_RX_FULL_E_INACTIVE 0x0
4453 /*
4454  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_RX_FULL
4455  *
4456  * RX_FULL interrupt is active
4457  */
4458 #define ALT_I2C_IC_RAW_INTR_STAT_RX_FULL_E_ACTIVE 0x1
4459 
4460 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_RAW_INTR_STAT_RX_FULL register field. */
4461 #define ALT_I2C_IC_RAW_INTR_STAT_RX_FULL_LSB 2
4462 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_RAW_INTR_STAT_RX_FULL register field. */
4463 #define ALT_I2C_IC_RAW_INTR_STAT_RX_FULL_MSB 2
4464 /* The width in bits of the ALT_I2C_IC_RAW_INTR_STAT_RX_FULL register field. */
4465 #define ALT_I2C_IC_RAW_INTR_STAT_RX_FULL_WIDTH 1
4466 /* The mask used to set the ALT_I2C_IC_RAW_INTR_STAT_RX_FULL register field value. */
4467 #define ALT_I2C_IC_RAW_INTR_STAT_RX_FULL_SET_MSK 0x00000004
4468 /* The mask used to clear the ALT_I2C_IC_RAW_INTR_STAT_RX_FULL register field value. */
4469 #define ALT_I2C_IC_RAW_INTR_STAT_RX_FULL_CLR_MSK 0xfffffffb
4470 /* The reset value of the ALT_I2C_IC_RAW_INTR_STAT_RX_FULL register field. */
4471 #define ALT_I2C_IC_RAW_INTR_STAT_RX_FULL_RESET 0x0
4472 /* Extracts the ALT_I2C_IC_RAW_INTR_STAT_RX_FULL field value from a register. */
4473 #define ALT_I2C_IC_RAW_INTR_STAT_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
4474 /* Produces a ALT_I2C_IC_RAW_INTR_STAT_RX_FULL register field value suitable for setting the register. */
4475 #define ALT_I2C_IC_RAW_INTR_STAT_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
4476 
4477 /*
4478  * Field : TX_OVER
4479  *
4480  * Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH
4481  *
4482  * and the processor attempts to issue another I2C command by writing to the
4483  *
4484  * IC_DATA_CMD register. When the module is disabled, this bit keeps its level
4485  *
4486  * until the master or slave state machines go into idle, and when ic_en goes to 0,
4487  *
4488  * this interrupt is cleared.
4489  *
4490  * Reset value: 0x0
4491  *
4492  * Field Enumeration Values:
4493  *
4494  * Enum | Value | Description
4495  * :--------------------------------------------|:------|:------------------------------
4496  * ALT_I2C_IC_RAW_INTR_STAT_TX_OVER_E_INACTIVE | 0x0 | TX_OVER interrupt is inactive
4497  * ALT_I2C_IC_RAW_INTR_STAT_TX_OVER_E_ACTIVE | 0x1 | TX_OVER interrupt is active
4498  *
4499  * Field Access Macros:
4500  *
4501  */
4502 /*
4503  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_TX_OVER
4504  *
4505  * TX_OVER interrupt is inactive
4506  */
4507 #define ALT_I2C_IC_RAW_INTR_STAT_TX_OVER_E_INACTIVE 0x0
4508 /*
4509  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_TX_OVER
4510  *
4511  * TX_OVER interrupt is active
4512  */
4513 #define ALT_I2C_IC_RAW_INTR_STAT_TX_OVER_E_ACTIVE 0x1
4514 
4515 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_RAW_INTR_STAT_TX_OVER register field. */
4516 #define ALT_I2C_IC_RAW_INTR_STAT_TX_OVER_LSB 3
4517 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_RAW_INTR_STAT_TX_OVER register field. */
4518 #define ALT_I2C_IC_RAW_INTR_STAT_TX_OVER_MSB 3
4519 /* The width in bits of the ALT_I2C_IC_RAW_INTR_STAT_TX_OVER register field. */
4520 #define ALT_I2C_IC_RAW_INTR_STAT_TX_OVER_WIDTH 1
4521 /* The mask used to set the ALT_I2C_IC_RAW_INTR_STAT_TX_OVER register field value. */
4522 #define ALT_I2C_IC_RAW_INTR_STAT_TX_OVER_SET_MSK 0x00000008
4523 /* The mask used to clear the ALT_I2C_IC_RAW_INTR_STAT_TX_OVER register field value. */
4524 #define ALT_I2C_IC_RAW_INTR_STAT_TX_OVER_CLR_MSK 0xfffffff7
4525 /* The reset value of the ALT_I2C_IC_RAW_INTR_STAT_TX_OVER register field. */
4526 #define ALT_I2C_IC_RAW_INTR_STAT_TX_OVER_RESET 0x0
4527 /* Extracts the ALT_I2C_IC_RAW_INTR_STAT_TX_OVER field value from a register. */
4528 #define ALT_I2C_IC_RAW_INTR_STAT_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
4529 /* Produces a ALT_I2C_IC_RAW_INTR_STAT_TX_OVER register field value suitable for setting the register. */
4530 #define ALT_I2C_IC_RAW_INTR_STAT_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
4531 
4532 /*
4533  * Field : TX_EMPTY
4534  *
4535  * The behavior of the TX_EMPTY interrupt status
4536  *
4537  * differs based on the TX_EMPTY_CTRL selection in the IC_CON register.
4538  *
4539  * When TX_EMPTY_CTRL = 0:
4540  *
4541  * This bit is set to 1 when the transmit buffer is at or below the threshold value
4542  * set in the IC_TX_TL register.
4543  *
4544  * When TX_EMPTY_CTRL = 1:
4545  *
4546  * This bit is set to 1 when the transmit buffer is at or below the threshold
4547  * value.
4548  *
4549  * set in the IC_TX_TL register and the transmission of the address/data from
4550  *
4551  * the internal shift register for the most recently popped command is completed.
4552  *
4553  * It is automatically cleared by hardware when the buffer level goes above the
4554  *
4555  * threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in
4556  *
4557  * reset. There the TX FIFO looks like it has no data within it, so this bit is set
4558  * to 1,
4559  *
4560  * provided there is activity in the master or slave state machines. When there is
4561  * no
4562  *
4563  * longer any activity, then with ic_en=0, this bit is set to 0.
4564  *
4565  * Reset value: 0x0.
4566  *
4567  * Field Enumeration Values:
4568  *
4569  * Enum | Value | Description
4570  * :---------------------------------------------|:------|:-------------------------------
4571  * ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY_E_INACTIVE | 0x0 | TX_EMPTY interrupt is inactive
4572  * ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY_E_ACTIVE | 0x1 | TX_EMPTY interrupt is active
4573  *
4574  * Field Access Macros:
4575  *
4576  */
4577 /*
4578  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY
4579  *
4580  * TX_EMPTY interrupt is inactive
4581  */
4582 #define ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY_E_INACTIVE 0x0
4583 /*
4584  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY
4585  *
4586  * TX_EMPTY interrupt is active
4587  */
4588 #define ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY_E_ACTIVE 0x1
4589 
4590 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY register field. */
4591 #define ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY_LSB 4
4592 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY register field. */
4593 #define ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY_MSB 4
4594 /* The width in bits of the ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY register field. */
4595 #define ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY_WIDTH 1
4596 /* The mask used to set the ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY register field value. */
4597 #define ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY_SET_MSK 0x00000010
4598 /* The mask used to clear the ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY register field value. */
4599 #define ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY_CLR_MSK 0xffffffef
4600 /* The reset value of the ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY register field. */
4601 #define ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY_RESET 0x0
4602 /* Extracts the ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY field value from a register. */
4603 #define ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
4604 /* Produces a ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY register field value suitable for setting the register. */
4605 #define ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
4606 
4607 /*
4608  * Field : RD_REQ
4609  *
4610  * This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C
4611  *
4612  * master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds
4613  *
4614  * the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which
4615  * means
4616  *
4617  * that the slave has been addressed by a remote master that is asking for data to
4618  *
4619  * be transferred. The processor must respond to this interrupt and then write the
4620  *
4621  * requested data to the IC_DATA_CMD register. This bit is set to 0 just after the
4622  *
4623  * processor reads the IC_CLR_RD_REQ register.
4624  *
4625  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
4626  *
4627  * Reset value: 0x0
4628  *
4629  * Field Enumeration Values:
4630  *
4631  * Enum | Value | Description
4632  * :-------------------------------------------|:------|:-----------------------------
4633  * ALT_I2C_IC_RAW_INTR_STAT_RD_REQ_E_INACTIVE | 0x0 | RD_REQ interrupt is inactive
4634  * ALT_I2C_IC_RAW_INTR_STAT_RD_REQ_E_ACTIVE | 0x1 | RD_REQ interrupt is active
4635  *
4636  * Field Access Macros:
4637  *
4638  */
4639 /*
4640  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_RD_REQ
4641  *
4642  * RD_REQ interrupt is inactive
4643  */
4644 #define ALT_I2C_IC_RAW_INTR_STAT_RD_REQ_E_INACTIVE 0x0
4645 /*
4646  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_RD_REQ
4647  *
4648  * RD_REQ interrupt is active
4649  */
4650 #define ALT_I2C_IC_RAW_INTR_STAT_RD_REQ_E_ACTIVE 0x1
4651 
4652 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_RAW_INTR_STAT_RD_REQ register field. */
4653 #define ALT_I2C_IC_RAW_INTR_STAT_RD_REQ_LSB 5
4654 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_RAW_INTR_STAT_RD_REQ register field. */
4655 #define ALT_I2C_IC_RAW_INTR_STAT_RD_REQ_MSB 5
4656 /* The width in bits of the ALT_I2C_IC_RAW_INTR_STAT_RD_REQ register field. */
4657 #define ALT_I2C_IC_RAW_INTR_STAT_RD_REQ_WIDTH 1
4658 /* The mask used to set the ALT_I2C_IC_RAW_INTR_STAT_RD_REQ register field value. */
4659 #define ALT_I2C_IC_RAW_INTR_STAT_RD_REQ_SET_MSK 0x00000020
4660 /* The mask used to clear the ALT_I2C_IC_RAW_INTR_STAT_RD_REQ register field value. */
4661 #define ALT_I2C_IC_RAW_INTR_STAT_RD_REQ_CLR_MSK 0xffffffdf
4662 /* The reset value of the ALT_I2C_IC_RAW_INTR_STAT_RD_REQ register field. */
4663 #define ALT_I2C_IC_RAW_INTR_STAT_RD_REQ_RESET 0x0
4664 /* Extracts the ALT_I2C_IC_RAW_INTR_STAT_RD_REQ field value from a register. */
4665 #define ALT_I2C_IC_RAW_INTR_STAT_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
4666 /* Produces a ALT_I2C_IC_RAW_INTR_STAT_RD_REQ register field value suitable for setting the register. */
4667 #define ALT_I2C_IC_RAW_INTR_STAT_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
4668 
4669 /*
4670  * Field : TX_ABRT
4671  *
4672  * This bit indicates if DW_apb_i2c, as an I2C transmitter,
4673  *
4674  * is unable to complete the intended actions on the
4675  *
4676  * contents of the transmit FIFO. This situation can
4677  *
4678  * occur both as an I2C master or an I2C slave, and is
4679  *
4680  * referred to as a 'transmit abort'.
4681  *
4682  * When this bit is set to 1, the IC_TX_ABRT_SOURCE register
4683  *
4684  * indicates the reason why the transmit abort takes places.
4685  *
4686  * NOTE: The DW_apb_i2c flushes/resets/empties only the TX_FIFO whenever
4687  *
4688  * there is a transmit abort caused by any of the events tracked by the
4689  *
4690  * IC_TX_ABRT_SOURCE register. The Tx FIFO remains in this flushed state
4691  *
4692  * until the register IC_CLR_TX_ABRT is read. Once this read is performed, the
4693  *
4694  * Tx FIFO is then ready to accept more data bytes from the APB interface. RX
4695  *
4696  * FIFO flush because of TX_ABRT is controlled by the coreConsultant parameter
4697  * IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT.
4698  *
4699  * Reset value: 0x0
4700  *
4701  * Field Enumeration Values:
4702  *
4703  * Enum | Value | Description
4704  * :--------------------------------------------|:------|:------------------------------
4705  * ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT_E_INACTIVE | 0x0 | TX_ABRT interrupt is inactive
4706  * ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT_E_ACTIVE | 0x1 | TX_ABRT interrupt is active
4707  *
4708  * Field Access Macros:
4709  *
4710  */
4711 /*
4712  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT
4713  *
4714  * TX_ABRT interrupt is inactive
4715  */
4716 #define ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT_E_INACTIVE 0x0
4717 /*
4718  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT
4719  *
4720  * TX_ABRT interrupt is active
4721  */
4722 #define ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT_E_ACTIVE 0x1
4723 
4724 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT register field. */
4725 #define ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT_LSB 6
4726 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT register field. */
4727 #define ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT_MSB 6
4728 /* The width in bits of the ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT register field. */
4729 #define ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT_WIDTH 1
4730 /* The mask used to set the ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT register field value. */
4731 #define ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT_SET_MSK 0x00000040
4732 /* The mask used to clear the ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT register field value. */
4733 #define ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT_CLR_MSK 0xffffffbf
4734 /* The reset value of the ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT register field. */
4735 #define ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT_RESET 0x0
4736 /* Extracts the ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT field value from a register. */
4737 #define ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
4738 /* Produces a ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT register field value suitable for setting the register. */
4739 #define ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
4740 
4741 /*
4742  * Field : RX_DONE
4743  *
4744  * When the DW_apb_i2c is acting as a slave-transmitter,
4745  *
4746  * this bit is set to 1 if the master does not acknowledge
4747  *
4748  * a transmitted byte. This occurs on the last byte of
4749  *
4750  * the transmission, indicating that the transmission is done.
4751  *
4752  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
4753  *
4754  * Reset value: 0x0
4755  *
4756  * Field Enumeration Values:
4757  *
4758  * Enum | Value | Description
4759  * :--------------------------------------------|:------|:------------------------------
4760  * ALT_I2C_IC_RAW_INTR_STAT_RX_DONE_E_INACTIVE | 0x0 | RX_DONE interrupt is inactive
4761  * ALT_I2C_IC_RAW_INTR_STAT_RX_DONE_E_ACTIVE | 0x1 | RX_DONE interrupt is active
4762  *
4763  * Field Access Macros:
4764  *
4765  */
4766 /*
4767  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_RX_DONE
4768  *
4769  * RX_DONE interrupt is inactive
4770  */
4771 #define ALT_I2C_IC_RAW_INTR_STAT_RX_DONE_E_INACTIVE 0x0
4772 /*
4773  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_RX_DONE
4774  *
4775  * RX_DONE interrupt is active
4776  */
4777 #define ALT_I2C_IC_RAW_INTR_STAT_RX_DONE_E_ACTIVE 0x1
4778 
4779 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_RAW_INTR_STAT_RX_DONE register field. */
4780 #define ALT_I2C_IC_RAW_INTR_STAT_RX_DONE_LSB 7
4781 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_RAW_INTR_STAT_RX_DONE register field. */
4782 #define ALT_I2C_IC_RAW_INTR_STAT_RX_DONE_MSB 7
4783 /* The width in bits of the ALT_I2C_IC_RAW_INTR_STAT_RX_DONE register field. */
4784 #define ALT_I2C_IC_RAW_INTR_STAT_RX_DONE_WIDTH 1
4785 /* The mask used to set the ALT_I2C_IC_RAW_INTR_STAT_RX_DONE register field value. */
4786 #define ALT_I2C_IC_RAW_INTR_STAT_RX_DONE_SET_MSK 0x00000080
4787 /* The mask used to clear the ALT_I2C_IC_RAW_INTR_STAT_RX_DONE register field value. */
4788 #define ALT_I2C_IC_RAW_INTR_STAT_RX_DONE_CLR_MSK 0xffffff7f
4789 /* The reset value of the ALT_I2C_IC_RAW_INTR_STAT_RX_DONE register field. */
4790 #define ALT_I2C_IC_RAW_INTR_STAT_RX_DONE_RESET 0x0
4791 /* Extracts the ALT_I2C_IC_RAW_INTR_STAT_RX_DONE field value from a register. */
4792 #define ALT_I2C_IC_RAW_INTR_STAT_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
4793 /* Produces a ALT_I2C_IC_RAW_INTR_STAT_RX_DONE register field value suitable for setting the register. */
4794 #define ALT_I2C_IC_RAW_INTR_STAT_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
4795 
4796 /*
4797  * Field : RAW_INTR_ACTIVITY
4798  *
4799  * This bit captures DW_apb_i2c activity and stays set until it is cleared. There
4800  *
4801  * are four ways to clear it:
4802  *
4803  * * Disabling the DW_apb_i2c
4804  *
4805  * * Reading the IC_CLR_ACTIVITY register
4806  *
4807  * * Reading the IC_CLR_INTR register
4808  *
4809  * * System reset
4810  *
4811  * Once this bit is set, it stays set unless one of the four methods is used to
4812  * clear it.
4813  *
4814  * Even if the DW_apb_i2c module is idle, this bit remains set until cleared,
4815  *
4816  * indicating that there was activity on the bus.
4817  *
4818  * Reset value: 0x0
4819  *
4820  * Field Enumeration Values:
4821  *
4822  * Enum | Value | Description
4823  * :------------------------------------------------------|:------|:----------------------------------------
4824  * ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY_E_INACTIVE | 0x0 | RAW_INTR_ACTIVITY interrupt is inactive
4825  * ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY_E_ACTIVE | 0x1 | RAW_INTR_ACTIVITY interrupt is active
4826  *
4827  * Field Access Macros:
4828  *
4829  */
4830 /*
4831  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY
4832  *
4833  * RAW_INTR_ACTIVITY interrupt is inactive
4834  */
4835 #define ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY_E_INACTIVE 0x0
4836 /*
4837  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY
4838  *
4839  * RAW_INTR_ACTIVITY interrupt is active
4840  */
4841 #define ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY_E_ACTIVE 0x1
4842 
4843 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY register field. */
4844 #define ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY_LSB 8
4845 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY register field. */
4846 #define ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY_MSB 8
4847 /* The width in bits of the ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY register field. */
4848 #define ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY_WIDTH 1
4849 /* The mask used to set the ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY register field value. */
4850 #define ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY_SET_MSK 0x00000100
4851 /* The mask used to clear the ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY register field value. */
4852 #define ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY_CLR_MSK 0xfffffeff
4853 /* The reset value of the ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY register field. */
4854 #define ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY_RESET 0x0
4855 /* Extracts the ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY field value from a register. */
4856 #define ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
4857 /* Produces a ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY register field value suitable for setting the register. */
4858 #define ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
4859 
4860 /*
4861  * Field : STOP_DET
4862  *
4863  * Indicates whether a STOP condition
4864  *
4865  * has occurred on the I2C interface regardless of whether DW_apb_i2c is operating
4866  * in slave or master mode.
4867  *
4868  * In Slave Mode:
4869  *
4870  * If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued
4871  * only if slave is addressed.
4872  *
4873  * Note: During general call address, this slave will not issue the STOP_DET
4874  * interrupt if STOP_DET_IF_ADDRESSED = 1'b1,
4875  *
4876  * even if slave responds for general call address by generating ACK.
4877  *
4878  * The STOP_DET interrupt is generated only when the transmitted address matches
4879  * with the slave address(SAR).
4880  *
4881  * If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued
4882  * irrespective of whether it's being addressed.
4883  *
4884  * In Master Mode:
4885  *
4886  * if IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be
4887  * issued only if Master is active.
4888  *
4889  * If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued
4890  * irrespective of whether master is active or not.
4891  *
4892  * In Master mode, this field is not dependent on IC_CON[10]
4893  * (STOP_DET_IF_MASTER_ACTIVE) when IC_ULTRA_FAST_MODE=1
4894  *
4895  * Reset value: 0x0
4896  *
4897  * Field Enumeration Values:
4898  *
4899  * Enum | Value | Description
4900  * :---------------------------------------------|:------|:-------------------------------
4901  * ALT_I2C_IC_RAW_INTR_STAT_STOP_DET_E_INACTIVE | 0x0 | STOP_DET interrupt is inactive
4902  * ALT_I2C_IC_RAW_INTR_STAT_STOP_DET_E_ACTIVE | 0x1 | STOP_DET interrupt is active
4903  *
4904  * Field Access Macros:
4905  *
4906  */
4907 /*
4908  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_STOP_DET
4909  *
4910  * STOP_DET interrupt is inactive
4911  */
4912 #define ALT_I2C_IC_RAW_INTR_STAT_STOP_DET_E_INACTIVE 0x0
4913 /*
4914  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_STOP_DET
4915  *
4916  * STOP_DET interrupt is active
4917  */
4918 #define ALT_I2C_IC_RAW_INTR_STAT_STOP_DET_E_ACTIVE 0x1
4919 
4920 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_RAW_INTR_STAT_STOP_DET register field. */
4921 #define ALT_I2C_IC_RAW_INTR_STAT_STOP_DET_LSB 9
4922 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_RAW_INTR_STAT_STOP_DET register field. */
4923 #define ALT_I2C_IC_RAW_INTR_STAT_STOP_DET_MSB 9
4924 /* The width in bits of the ALT_I2C_IC_RAW_INTR_STAT_STOP_DET register field. */
4925 #define ALT_I2C_IC_RAW_INTR_STAT_STOP_DET_WIDTH 1
4926 /* The mask used to set the ALT_I2C_IC_RAW_INTR_STAT_STOP_DET register field value. */
4927 #define ALT_I2C_IC_RAW_INTR_STAT_STOP_DET_SET_MSK 0x00000200
4928 /* The mask used to clear the ALT_I2C_IC_RAW_INTR_STAT_STOP_DET register field value. */
4929 #define ALT_I2C_IC_RAW_INTR_STAT_STOP_DET_CLR_MSK 0xfffffdff
4930 /* The reset value of the ALT_I2C_IC_RAW_INTR_STAT_STOP_DET register field. */
4931 #define ALT_I2C_IC_RAW_INTR_STAT_STOP_DET_RESET 0x0
4932 /* Extracts the ALT_I2C_IC_RAW_INTR_STAT_STOP_DET field value from a register. */
4933 #define ALT_I2C_IC_RAW_INTR_STAT_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
4934 /* Produces a ALT_I2C_IC_RAW_INTR_STAT_STOP_DET register field value suitable for setting the register. */
4935 #define ALT_I2C_IC_RAW_INTR_STAT_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
4936 
4937 /*
4938  * Field : START_DET
4939  *
4940  * Indicates whether a START or RESTART condition has occurred on the I2C
4941  *
4942  * interface regardless of whether DW_apb_i2c is operating in slave or master
4943  *
4944  * mode.
4945  *
4946  * Reset value: 0x0
4947  *
4948  * Field Enumeration Values:
4949  *
4950  * Enum | Value | Description
4951  * :----------------------------------------------|:------|:--------------------------------
4952  * ALT_I2C_IC_RAW_INTR_STAT_START_DET_E_INACTIVE | 0x0 | START_DET interrupt is inactive
4953  * ALT_I2C_IC_RAW_INTR_STAT_START_DET_E_ACTIVE | 0x1 | START_DET interrupt is active
4954  *
4955  * Field Access Macros:
4956  *
4957  */
4958 /*
4959  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_START_DET
4960  *
4961  * START_DET interrupt is inactive
4962  */
4963 #define ALT_I2C_IC_RAW_INTR_STAT_START_DET_E_INACTIVE 0x0
4964 /*
4965  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_START_DET
4966  *
4967  * START_DET interrupt is active
4968  */
4969 #define ALT_I2C_IC_RAW_INTR_STAT_START_DET_E_ACTIVE 0x1
4970 
4971 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_RAW_INTR_STAT_START_DET register field. */
4972 #define ALT_I2C_IC_RAW_INTR_STAT_START_DET_LSB 10
4973 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_RAW_INTR_STAT_START_DET register field. */
4974 #define ALT_I2C_IC_RAW_INTR_STAT_START_DET_MSB 10
4975 /* The width in bits of the ALT_I2C_IC_RAW_INTR_STAT_START_DET register field. */
4976 #define ALT_I2C_IC_RAW_INTR_STAT_START_DET_WIDTH 1
4977 /* The mask used to set the ALT_I2C_IC_RAW_INTR_STAT_START_DET register field value. */
4978 #define ALT_I2C_IC_RAW_INTR_STAT_START_DET_SET_MSK 0x00000400
4979 /* The mask used to clear the ALT_I2C_IC_RAW_INTR_STAT_START_DET register field value. */
4980 #define ALT_I2C_IC_RAW_INTR_STAT_START_DET_CLR_MSK 0xfffffbff
4981 /* The reset value of the ALT_I2C_IC_RAW_INTR_STAT_START_DET register field. */
4982 #define ALT_I2C_IC_RAW_INTR_STAT_START_DET_RESET 0x0
4983 /* Extracts the ALT_I2C_IC_RAW_INTR_STAT_START_DET field value from a register. */
4984 #define ALT_I2C_IC_RAW_INTR_STAT_START_DET_GET(value) (((value) & 0x00000400) >> 10)
4985 /* Produces a ALT_I2C_IC_RAW_INTR_STAT_START_DET register field value suitable for setting the register. */
4986 #define ALT_I2C_IC_RAW_INTR_STAT_START_DET_SET(value) (((value) << 10) & 0x00000400)
4987 
4988 /*
4989  * Field : GEN_CALL
4990  *
4991  * Set only when a General Call address is received and it is acknowledged. It
4992  *
4993  * stays set until it is cleared either by disabling DW_apb_i2c or when the CPU
4994  *
4995  * reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the
4996  *
4997  * received data in the Rx buffer.
4998  *
4999  * Reset value: 0x0
5000  *
5001  * Field Enumeration Values:
5002  *
5003  * Enum | Value | Description
5004  * :---------------------------------------------|:------|:-------------------------------
5005  * ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL_E_INACTIVE | 0x0 | GEN_CALL interrupt is inactive
5006  * ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL_E_ACTIVE | 0x1 | GEN_CALL interrupt is active
5007  *
5008  * Field Access Macros:
5009  *
5010  */
5011 /*
5012  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL
5013  *
5014  * GEN_CALL interrupt is inactive
5015  */
5016 #define ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL_E_INACTIVE 0x0
5017 /*
5018  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL
5019  *
5020  * GEN_CALL interrupt is active
5021  */
5022 #define ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL_E_ACTIVE 0x1
5023 
5024 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL register field. */
5025 #define ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL_LSB 11
5026 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL register field. */
5027 #define ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL_MSB 11
5028 /* The width in bits of the ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL register field. */
5029 #define ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL_WIDTH 1
5030 /* The mask used to set the ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL register field value. */
5031 #define ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL_SET_MSK 0x00000800
5032 /* The mask used to clear the ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL register field value. */
5033 #define ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL_CLR_MSK 0xfffff7ff
5034 /* The reset value of the ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL register field. */
5035 #define ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL_RESET 0x0
5036 /* Extracts the ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL field value from a register. */
5037 #define ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
5038 /* Produces a ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL register field value suitable for setting the register. */
5039 #define ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
5040 
5041 /*
5042  * Field : RESTART_DET
5043  *
5044  * Indicates whether a RESTART condition has occurred on the I2C interface
5045  *
5046  * when DW_apb_i2c is operating in Slave mode and the slave is being addressed.
5047  * Enabled only when IC_SLV_RESTART_DET_EN=1.
5048  *
5049  * (Note:Following are exceptions where the Restart interrupt will not get
5050  * generated.
5051  *
5052  * In the case of High speed Mode or Startbyte transfer, where the Restart comes
5053  * before the Address field as per the
5054  *
5055  * I2C protocol defined format, the Slave is still not in the addressed mode and
5056  * hence will not generate the RESTART_DET interrupt.)
5057  *
5058  * Reset value: 0x0
5059  *
5060  * Field Enumeration Values:
5061  *
5062  * Enum | Value | Description
5063  * :------------------------------------------------|:------|:----------------------------------
5064  * ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET_E_INACTIVE | 0x0 | RESTART_DET interrupt is inactive
5065  * ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET_E_ACTIVE | 0x1 | RESTART_DET interrupt is active
5066  *
5067  * Field Access Macros:
5068  *
5069  */
5070 /*
5071  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET
5072  *
5073  * RESTART_DET interrupt is inactive
5074  */
5075 #define ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET_E_INACTIVE 0x0
5076 /*
5077  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET
5078  *
5079  * RESTART_DET interrupt is active
5080  */
5081 #define ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET_E_ACTIVE 0x1
5082 
5083 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET register field. */
5084 #define ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET_LSB 12
5085 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET register field. */
5086 #define ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET_MSB 12
5087 /* The width in bits of the ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET register field. */
5088 #define ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET_WIDTH 1
5089 /* The mask used to set the ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET register field value. */
5090 #define ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET_SET_MSK 0x00001000
5091 /* The mask used to clear the ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET register field value. */
5092 #define ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET_CLR_MSK 0xffffefff
5093 /* The reset value of the ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET register field. */
5094 #define ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET_RESET 0x0
5095 /* Extracts the ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET field value from a register. */
5096 #define ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET_GET(value) (((value) & 0x00001000) >> 12)
5097 /* Produces a ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET register field value suitable for setting the register. */
5098 #define ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET_SET(value) (((value) << 12) & 0x00001000)
5099 
5100 /*
5101  * Field : MASTER_ON_HOLD
5102  *
5103  * Indicates whether master is holding the bus and TX FIFO is empty.
5104  *
5105  * Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and IC_EMPTYFIFO_HOLD_MASTER_EN=1.
5106  *
5107  * Reset value: 0x0
5108  *
5109  * Field Enumeration Values:
5110  *
5111  * Enum | Value | Description
5112  * :---------------------------------------------------|:------|:-------------------------------------
5113  * ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_E_INACTIVE | 0x0 | MASTER_ON_HOLD interrupt is inactive
5114  * ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_E_ACTIVE | 0x1 | MASTER_ON_HOLD interrupt is active
5115  *
5116  * Field Access Macros:
5117  *
5118  */
5119 /*
5120  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD
5121  *
5122  * MASTER_ON_HOLD interrupt is inactive
5123  */
5124 #define ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_E_INACTIVE 0x0
5125 /*
5126  * Enumerated value for register field ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD
5127  *
5128  * MASTER_ON_HOLD interrupt is active
5129  */
5130 #define ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_E_ACTIVE 0x1
5131 
5132 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD register field. */
5133 #define ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_LSB 13
5134 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD register field. */
5135 #define ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_MSB 13
5136 /* The width in bits of the ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD register field. */
5137 #define ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_WIDTH 1
5138 /* The mask used to set the ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD register field value. */
5139 #define ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_SET_MSK 0x00002000
5140 /* The mask used to clear the ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD register field value. */
5141 #define ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_CLR_MSK 0xffffdfff
5142 /* The reset value of the ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD register field. */
5143 #define ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_RESET 0x0
5144 /* Extracts the ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD field value from a register. */
5145 #define ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_GET(value) (((value) & 0x00002000) >> 13)
5146 /* Produces a ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD register field value suitable for setting the register. */
5147 #define ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_SET(value) (((value) << 13) & 0x00002000)
5148 
5149 /*
5150  * Field : RSVD_SCL_STUCK_AT_LOW
5151  *
5152  * Reserved bits - Read Only
5153  *
5154  * Field Access Macros:
5155  *
5156  */
5157 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW register field. */
5158 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW_LSB 14
5159 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW register field. */
5160 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW_MSB 14
5161 /* The width in bits of the ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW register field. */
5162 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW_WIDTH 1
5163 /* The mask used to set the ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW register field value. */
5164 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW_SET_MSK 0x00004000
5165 /* The mask used to clear the ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW register field value. */
5166 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW_CLR_MSK 0xffffbfff
5167 /* The reset value of the ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW register field. */
5168 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW_RESET 0x0
5169 /* Extracts the ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW field value from a register. */
5170 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW_GET(value) (((value) & 0x00004000) >> 14)
5171 /* Produces a ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW register field value suitable for setting the register. */
5172 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW_SET(value) (((value) << 14) & 0x00004000)
5173 
5174 /*
5175  * Field : RSVD_IC_RAW_INTR_STAT
5176  *
5177  * Reserved bits - Read Only
5178  *
5179  * Field Access Macros:
5180  *
5181  */
5182 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT register field. */
5183 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT_LSB 15
5184 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT register field. */
5185 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT_MSB 31
5186 /* The width in bits of the ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT register field. */
5187 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT_WIDTH 17
5188 /* The mask used to set the ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT register field value. */
5189 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT_SET_MSK 0xffff8000
5190 /* The mask used to clear the ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT register field value. */
5191 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT_CLR_MSK 0x00007fff
5192 /* The reset value of the ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT register field. */
5193 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT_RESET 0x0
5194 /* Extracts the ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT field value from a register. */
5195 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT_GET(value) (((value) & 0xffff8000) >> 15)
5196 /* Produces a ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT register field value suitable for setting the register. */
5197 #define ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT_SET(value) (((value) << 15) & 0xffff8000)
5198 
5199 #ifndef __ASSEMBLY__
5200 /*
5201  * WARNING: The C register and register group struct declarations are provided for
5202  * convenience and illustrative purposes. They should, however, be used with
5203  * caution as the C language standard provides no guarantees about the alignment or
5204  * atomicity of device memory accesses. The recommended practice for coding device
5205  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5206  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5207  * alt_write_dword() functions for 64 bit registers.
5208  *
5209  * The struct declaration for register ALT_I2C_IC_RAW_INTR_STAT.
5210  */
5211 struct ALT_I2C_IC_RAW_INTR_STAT_s
5212 {
5213  const volatile uint32_t RX_UNDER : 1; /* ALT_I2C_IC_RAW_INTR_STAT_RX_UNDER */
5214  const volatile uint32_t RX_OVER : 1; /* ALT_I2C_IC_RAW_INTR_STAT_RX_OVER */
5215  const volatile uint32_t RX_FULL : 1; /* ALT_I2C_IC_RAW_INTR_STAT_RX_FULL */
5216  const volatile uint32_t TX_OVER : 1; /* ALT_I2C_IC_RAW_INTR_STAT_TX_OVER */
5217  const volatile uint32_t TX_EMPTY : 1; /* ALT_I2C_IC_RAW_INTR_STAT_TX_EMPTY */
5218  const volatile uint32_t RD_REQ : 1; /* ALT_I2C_IC_RAW_INTR_STAT_RD_REQ */
5219  const volatile uint32_t TX_ABRT : 1; /* ALT_I2C_IC_RAW_INTR_STAT_TX_ABRT */
5220  const volatile uint32_t RX_DONE : 1; /* ALT_I2C_IC_RAW_INTR_STAT_RX_DONE */
5221  const volatile uint32_t RAW_INTR_ACTIVITY : 1; /* ALT_I2C_IC_RAW_INTR_STAT_RAW_INTR_ACTIVITY */
5222  const volatile uint32_t STOP_DET : 1; /* ALT_I2C_IC_RAW_INTR_STAT_STOP_DET */
5223  const volatile uint32_t START_DET : 1; /* ALT_I2C_IC_RAW_INTR_STAT_START_DET */
5224  const volatile uint32_t GEN_CALL : 1; /* ALT_I2C_IC_RAW_INTR_STAT_GEN_CALL */
5225  const volatile uint32_t RESTART_DET : 1; /* ALT_I2C_IC_RAW_INTR_STAT_RESTART_DET */
5226  const volatile uint32_t MASTER_ON_HOLD : 1; /* ALT_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD */
5227  const volatile uint32_t RSVD_SCL_STUCK_AT_LOW : 1; /* ALT_I2C_IC_RAW_INTR_STAT_RSVD_SCL_STUCK_AT_LOW */
5228  const volatile uint32_t RSVD_IC_RAW_INTR_STAT : 17; /* ALT_I2C_IC_RAW_INTR_STAT_RSVD_IC_RAW_INTR_STAT */
5229 };
5230 
5231 /* The typedef declaration for register ALT_I2C_IC_RAW_INTR_STAT. */
5232 typedef struct ALT_I2C_IC_RAW_INTR_STAT_s ALT_I2C_IC_RAW_INTR_STAT_t;
5233 #endif /* __ASSEMBLY__ */
5234 
5235 /* The reset value of the ALT_I2C_IC_RAW_INTR_STAT register. */
5236 #define ALT_I2C_IC_RAW_INTR_STAT_RESET 0x00000000
5237 /* The byte offset of the ALT_I2C_IC_RAW_INTR_STAT register from the beginning of the component. */
5238 #define ALT_I2C_IC_RAW_INTR_STAT_OFST 0x34
5239 /* The address of the ALT_I2C_IC_RAW_INTR_STAT register. */
5240 #define ALT_I2C_IC_RAW_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_RAW_INTR_STAT_OFST))
5241 
5242 /*
5243  * Register : I2C Receive FIFO Threshold Register - IC_RX_TL
5244  *
5245  * Name: I2C Receive FIFO Threshold Register
5246  *
5247  * Size: 8bits
5248  *
5249  * Address Offset: 0x38
5250  *
5251  * Read/Write Access: Read/Write
5252  *
5253  * Register Layout
5254  *
5255  * Bits | Access | Reset | Description
5256  * :-------|:-------|:------|:-------------------------------
5257  * [7:0] | RW | 0x0 | ALT_I2C_IC_RX_TL_RX_TL
5258  * [31:8] | R | 0x0 | ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL
5259  *
5260  */
5261 /*
5262  * Field : RX_TL
5263  *
5264  * Receive FIFO Threshold Level
5265  *
5266  * Controls the level of entries (or above) that triggers
5267  *
5268  * the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register).
5269  *
5270  * The valid range is 0-255, with the additional restriction that
5271  *
5272  * hardware does not allow this value to be set to a value larger
5273  *
5274  * than the depth of the buffer. If an attempt is made to do that,
5275  *
5276  * the actual value set will be the maximum depth of the buffer.
5277  *
5278  * A value of 0 sets the threshold for 1 entry, and a value of 255
5279  *
5280  * sets the threshold for 256 entries.
5281  *
5282  * Reset value: IC_RX_TL configuration parameter
5283  *
5284  * Field Access Macros:
5285  *
5286  */
5287 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_RX_TL_RX_TL register field. */
5288 #define ALT_I2C_IC_RX_TL_RX_TL_LSB 0
5289 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_RX_TL_RX_TL register field. */
5290 #define ALT_I2C_IC_RX_TL_RX_TL_MSB 7
5291 /* The width in bits of the ALT_I2C_IC_RX_TL_RX_TL register field. */
5292 #define ALT_I2C_IC_RX_TL_RX_TL_WIDTH 8
5293 /* The mask used to set the ALT_I2C_IC_RX_TL_RX_TL register field value. */
5294 #define ALT_I2C_IC_RX_TL_RX_TL_SET_MSK 0x000000ff
5295 /* The mask used to clear the ALT_I2C_IC_RX_TL_RX_TL register field value. */
5296 #define ALT_I2C_IC_RX_TL_RX_TL_CLR_MSK 0xffffff00
5297 /* The reset value of the ALT_I2C_IC_RX_TL_RX_TL register field. */
5298 #define ALT_I2C_IC_RX_TL_RX_TL_RESET 0x0
5299 /* Extracts the ALT_I2C_IC_RX_TL_RX_TL field value from a register. */
5300 #define ALT_I2C_IC_RX_TL_RX_TL_GET(value) (((value) & 0x000000ff) >> 0)
5301 /* Produces a ALT_I2C_IC_RX_TL_RX_TL register field value suitable for setting the register. */
5302 #define ALT_I2C_IC_RX_TL_RX_TL_SET(value) (((value) << 0) & 0x000000ff)
5303 
5304 /*
5305  * Field : RSVD_IC_RX_TL
5306  *
5307  * Reserved bits - Read Only
5308  *
5309  * Field Access Macros:
5310  *
5311  */
5312 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL register field. */
5313 #define ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL_LSB 8
5314 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL register field. */
5315 #define ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL_MSB 31
5316 /* The width in bits of the ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL register field. */
5317 #define ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL_WIDTH 24
5318 /* The mask used to set the ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL register field value. */
5319 #define ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL_SET_MSK 0xffffff00
5320 /* The mask used to clear the ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL register field value. */
5321 #define ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL_CLR_MSK 0x000000ff
5322 /* The reset value of the ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL register field. */
5323 #define ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL_RESET 0x0
5324 /* Extracts the ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL field value from a register. */
5325 #define ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL_GET(value) (((value) & 0xffffff00) >> 8)
5326 /* Produces a ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL register field value suitable for setting the register. */
5327 #define ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL_SET(value) (((value) << 8) & 0xffffff00)
5328 
5329 #ifndef __ASSEMBLY__
5330 /*
5331  * WARNING: The C register and register group struct declarations are provided for
5332  * convenience and illustrative purposes. They should, however, be used with
5333  * caution as the C language standard provides no guarantees about the alignment or
5334  * atomicity of device memory accesses. The recommended practice for coding device
5335  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5336  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5337  * alt_write_dword() functions for 64 bit registers.
5338  *
5339  * The struct declaration for register ALT_I2C_IC_RX_TL.
5340  */
5341 struct ALT_I2C_IC_RX_TL_s
5342 {
5343  volatile uint32_t RX_TL : 8; /* ALT_I2C_IC_RX_TL_RX_TL */
5344  const volatile uint32_t RSVD_IC_RX_TL : 24; /* ALT_I2C_IC_RX_TL_RSVD_IC_RX_TL */
5345 };
5346 
5347 /* The typedef declaration for register ALT_I2C_IC_RX_TL. */
5348 typedef struct ALT_I2C_IC_RX_TL_s ALT_I2C_IC_RX_TL_t;
5349 #endif /* __ASSEMBLY__ */
5350 
5351 /* The reset value of the ALT_I2C_IC_RX_TL register. */
5352 #define ALT_I2C_IC_RX_TL_RESET 0x00000000
5353 /* The byte offset of the ALT_I2C_IC_RX_TL register from the beginning of the component. */
5354 #define ALT_I2C_IC_RX_TL_OFST 0x38
5355 /* The address of the ALT_I2C_IC_RX_TL register. */
5356 #define ALT_I2C_IC_RX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_RX_TL_OFST))
5357 
5358 /*
5359  * Register : I2C Transmit FIFO Threshold Register - IC_TX_TL
5360  *
5361  * Name: I2C Transmit FIFO Threshold Register
5362  *
5363  * Size: 8 bits
5364  *
5365  * Address Offset: 0x3c
5366  *
5367  * Read/Write Access: Read/Write
5368  *
5369  * Register Layout
5370  *
5371  * Bits | Access | Reset | Description
5372  * :-------|:-------|:------|:-------------------------------
5373  * [7:0] | RW | 0x0 | ALT_I2C_IC_TX_TL_TX_TL
5374  * [31:8] | R | 0x0 | ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL
5375  *
5376  */
5377 /*
5378  * Field : TX_TL
5379  *
5380  * Transmit FIFO Threshold Level
5381  *
5382  * Controls the level of entries (or below) that trigger
5383  *
5384  * the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register).
5385  *
5386  * The valid range is 0-255, with the additional restriction that
5387  *
5388  * it may not be set to value larger than the depth of the buffer.
5389  *
5390  * If an attempt is made to do that, the actual value set will be
5391  *
5392  * the maximum depth of the buffer.
5393  *
5394  * A value of 0 sets the threshold for 0 entries, and a value of 255
5395  *
5396  * sets the threshold for 255 entries.
5397  *
5398  * Reset value: IC_TX_TL configuration parameter
5399  *
5400  * Field Access Macros:
5401  *
5402  */
5403 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_TL_TX_TL register field. */
5404 #define ALT_I2C_IC_TX_TL_TX_TL_LSB 0
5405 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_TL_TX_TL register field. */
5406 #define ALT_I2C_IC_TX_TL_TX_TL_MSB 7
5407 /* The width in bits of the ALT_I2C_IC_TX_TL_TX_TL register field. */
5408 #define ALT_I2C_IC_TX_TL_TX_TL_WIDTH 8
5409 /* The mask used to set the ALT_I2C_IC_TX_TL_TX_TL register field value. */
5410 #define ALT_I2C_IC_TX_TL_TX_TL_SET_MSK 0x000000ff
5411 /* The mask used to clear the ALT_I2C_IC_TX_TL_TX_TL register field value. */
5412 #define ALT_I2C_IC_TX_TL_TX_TL_CLR_MSK 0xffffff00
5413 /* The reset value of the ALT_I2C_IC_TX_TL_TX_TL register field. */
5414 #define ALT_I2C_IC_TX_TL_TX_TL_RESET 0x0
5415 /* Extracts the ALT_I2C_IC_TX_TL_TX_TL field value from a register. */
5416 #define ALT_I2C_IC_TX_TL_TX_TL_GET(value) (((value) & 0x000000ff) >> 0)
5417 /* Produces a ALT_I2C_IC_TX_TL_TX_TL register field value suitable for setting the register. */
5418 #define ALT_I2C_IC_TX_TL_TX_TL_SET(value) (((value) << 0) & 0x000000ff)
5419 
5420 /*
5421  * Field : RSVD_IC_TX_TL
5422  *
5423  * Reserved bits - Read Only
5424  *
5425  * Field Access Macros:
5426  *
5427  */
5428 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL register field. */
5429 #define ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL_LSB 8
5430 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL register field. */
5431 #define ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL_MSB 31
5432 /* The width in bits of the ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL register field. */
5433 #define ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL_WIDTH 24
5434 /* The mask used to set the ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL register field value. */
5435 #define ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL_SET_MSK 0xffffff00
5436 /* The mask used to clear the ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL register field value. */
5437 #define ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL_CLR_MSK 0x000000ff
5438 /* The reset value of the ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL register field. */
5439 #define ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL_RESET 0x0
5440 /* Extracts the ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL field value from a register. */
5441 #define ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL_GET(value) (((value) & 0xffffff00) >> 8)
5442 /* Produces a ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL register field value suitable for setting the register. */
5443 #define ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL_SET(value) (((value) << 8) & 0xffffff00)
5444 
5445 #ifndef __ASSEMBLY__
5446 /*
5447  * WARNING: The C register and register group struct declarations are provided for
5448  * convenience and illustrative purposes. They should, however, be used with
5449  * caution as the C language standard provides no guarantees about the alignment or
5450  * atomicity of device memory accesses. The recommended practice for coding device
5451  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5452  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5453  * alt_write_dword() functions for 64 bit registers.
5454  *
5455  * The struct declaration for register ALT_I2C_IC_TX_TL.
5456  */
5457 struct ALT_I2C_IC_TX_TL_s
5458 {
5459  volatile uint32_t TX_TL : 8; /* ALT_I2C_IC_TX_TL_TX_TL */
5460  const volatile uint32_t RSVD_IC_TX_TL : 24; /* ALT_I2C_IC_TX_TL_RSVD_IC_TX_TL */
5461 };
5462 
5463 /* The typedef declaration for register ALT_I2C_IC_TX_TL. */
5464 typedef struct ALT_I2C_IC_TX_TL_s ALT_I2C_IC_TX_TL_t;
5465 #endif /* __ASSEMBLY__ */
5466 
5467 /* The reset value of the ALT_I2C_IC_TX_TL register. */
5468 #define ALT_I2C_IC_TX_TL_RESET 0x00000000
5469 /* The byte offset of the ALT_I2C_IC_TX_TL register from the beginning of the component. */
5470 #define ALT_I2C_IC_TX_TL_OFST 0x3c
5471 /* The address of the ALT_I2C_IC_TX_TL register. */
5472 #define ALT_I2C_IC_TX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_TX_TL_OFST))
5473 
5474 /*
5475  * Register : Clear Combined and Individual Interrupt Register - IC_CLR_INTR
5476  *
5477  * Name: Clear Combined and Individual Interrupt Register
5478  *
5479  * Size: 1 bit
5480  *
5481  * Address Offset: 0x40
5482  *
5483  * Read/Write Access: Read
5484  *
5485  * Register Layout
5486  *
5487  * Bits | Access | Reset | Description
5488  * :-------|:-------|:------|:-------------------------------------
5489  * [0] | R | 0x0 | ALT_I2C_IC_CLR_INTR_CLR_INTR
5490  * [31:1] | R | 0x0 | ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR
5491  *
5492  */
5493 /*
5494  * Field : CLR_INTR
5495  *
5496  * Read this register to clear the combined interrupt,
5497  *
5498  * all individual interrupts, and the IC_TX_ABRT_SOURCE register.
5499  *
5500  * This bit does not clear hardware clearable interrupts but software
5501  *
5502  * clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register
5503  *
5504  * for an exception to clearing IC_TX_ABRT_SOURCE.
5505  *
5506  * Reset value: 0x0
5507  *
5508  * Field Access Macros:
5509  *
5510  */
5511 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_INTR_CLR_INTR register field. */
5512 #define ALT_I2C_IC_CLR_INTR_CLR_INTR_LSB 0
5513 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_INTR_CLR_INTR register field. */
5514 #define ALT_I2C_IC_CLR_INTR_CLR_INTR_MSB 0
5515 /* The width in bits of the ALT_I2C_IC_CLR_INTR_CLR_INTR register field. */
5516 #define ALT_I2C_IC_CLR_INTR_CLR_INTR_WIDTH 1
5517 /* The mask used to set the ALT_I2C_IC_CLR_INTR_CLR_INTR register field value. */
5518 #define ALT_I2C_IC_CLR_INTR_CLR_INTR_SET_MSK 0x00000001
5519 /* The mask used to clear the ALT_I2C_IC_CLR_INTR_CLR_INTR register field value. */
5520 #define ALT_I2C_IC_CLR_INTR_CLR_INTR_CLR_MSK 0xfffffffe
5521 /* The reset value of the ALT_I2C_IC_CLR_INTR_CLR_INTR register field. */
5522 #define ALT_I2C_IC_CLR_INTR_CLR_INTR_RESET 0x0
5523 /* Extracts the ALT_I2C_IC_CLR_INTR_CLR_INTR field value from a register. */
5524 #define ALT_I2C_IC_CLR_INTR_CLR_INTR_GET(value) (((value) & 0x00000001) >> 0)
5525 /* Produces a ALT_I2C_IC_CLR_INTR_CLR_INTR register field value suitable for setting the register. */
5526 #define ALT_I2C_IC_CLR_INTR_CLR_INTR_SET(value) (((value) << 0) & 0x00000001)
5527 
5528 /*
5529  * Field : RSVD_IC_CLR_INTR
5530  *
5531  * Reserved bits - Read Only
5532  *
5533  * Field Access Macros:
5534  *
5535  */
5536 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR register field. */
5537 #define ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR_LSB 1
5538 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR register field. */
5539 #define ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR_MSB 31
5540 /* The width in bits of the ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR register field. */
5541 #define ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR_WIDTH 31
5542 /* The mask used to set the ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR register field value. */
5543 #define ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR_SET_MSK 0xfffffffe
5544 /* The mask used to clear the ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR register field value. */
5545 #define ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR_CLR_MSK 0x00000001
5546 /* The reset value of the ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR register field. */
5547 #define ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR_RESET 0x0
5548 /* Extracts the ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR field value from a register. */
5549 #define ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR_GET(value) (((value) & 0xfffffffe) >> 1)
5550 /* Produces a ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR register field value suitable for setting the register. */
5551 #define ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR_SET(value) (((value) << 1) & 0xfffffffe)
5552 
5553 #ifndef __ASSEMBLY__
5554 /*
5555  * WARNING: The C register and register group struct declarations are provided for
5556  * convenience and illustrative purposes. They should, however, be used with
5557  * caution as the C language standard provides no guarantees about the alignment or
5558  * atomicity of device memory accesses. The recommended practice for coding device
5559  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5560  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5561  * alt_write_dword() functions for 64 bit registers.
5562  *
5563  * The struct declaration for register ALT_I2C_IC_CLR_INTR.
5564  */
5565 struct ALT_I2C_IC_CLR_INTR_s
5566 {
5567  const volatile uint32_t CLR_INTR : 1; /* ALT_I2C_IC_CLR_INTR_CLR_INTR */
5568  const volatile uint32_t RSVD_IC_CLR_INTR : 31; /* ALT_I2C_IC_CLR_INTR_RSVD_IC_CLR_INTR */
5569 };
5570 
5571 /* The typedef declaration for register ALT_I2C_IC_CLR_INTR. */
5572 typedef struct ALT_I2C_IC_CLR_INTR_s ALT_I2C_IC_CLR_INTR_t;
5573 #endif /* __ASSEMBLY__ */
5574 
5575 /* The reset value of the ALT_I2C_IC_CLR_INTR register. */
5576 #define ALT_I2C_IC_CLR_INTR_RESET 0x00000000
5577 /* The byte offset of the ALT_I2C_IC_CLR_INTR register from the beginning of the component. */
5578 #define ALT_I2C_IC_CLR_INTR_OFST 0x40
5579 /* The address of the ALT_I2C_IC_CLR_INTR register. */
5580 #define ALT_I2C_IC_CLR_INTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_INTR_OFST))
5581 
5582 /*
5583  * Register : Clear RX_UNDER Interrupt Register - IC_CLR_RX_UNDER
5584  *
5585  * Name: Clear RX_UNDER Interrupt Register
5586  *
5587  * Size: 1 bit
5588  *
5589  * Address Offset: 0x44
5590  *
5591  * Read/Write Access: Read
5592  *
5593  * Register Layout
5594  *
5595  * Bits | Access | Reset | Description
5596  * :-------|:-------|:------|:---------------------------------------------
5597  * [0] | R | 0x0 | ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER
5598  * [31:1] | R | 0x0 | ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER
5599  *
5600  */
5601 /*
5602  * Field : CLR_RX_UNDER
5603  *
5604  * Read this register to clear the RX_UNDER
5605  *
5606  * interrupt (bit 0) of the IC_RAW_INTR_STAT register.
5607  *
5608  * Reset value: 0x0
5609  *
5610  * Field Access Macros:
5611  *
5612  */
5613 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER register field. */
5614 #define ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_LSB 0
5615 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER register field. */
5616 #define ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_MSB 0
5617 /* The width in bits of the ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER register field. */
5618 #define ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_WIDTH 1
5619 /* The mask used to set the ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER register field value. */
5620 #define ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_SET_MSK 0x00000001
5621 /* The mask used to clear the ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER register field value. */
5622 #define ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_CLR_MSK 0xfffffffe
5623 /* The reset value of the ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER register field. */
5624 #define ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_RESET 0x0
5625 /* Extracts the ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER field value from a register. */
5626 #define ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
5627 /* Produces a ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER register field value suitable for setting the register. */
5628 #define ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
5629 
5630 /*
5631  * Field : RSVD_IC_CLR_RX_UNDER
5632  *
5633  * Reserved bits - Read Only
5634  *
5635  * Field Access Macros:
5636  *
5637  */
5638 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER register field. */
5639 #define ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER_LSB 1
5640 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER register field. */
5641 #define ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER_MSB 31
5642 /* The width in bits of the ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER register field. */
5643 #define ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER_WIDTH 31
5644 /* The mask used to set the ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER register field value. */
5645 #define ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER_SET_MSK 0xfffffffe
5646 /* The mask used to clear the ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER register field value. */
5647 #define ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER_CLR_MSK 0x00000001
5648 /* The reset value of the ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER register field. */
5649 #define ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER_RESET 0x0
5650 /* Extracts the ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER field value from a register. */
5651 #define ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER_GET(value) (((value) & 0xfffffffe) >> 1)
5652 /* Produces a ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER register field value suitable for setting the register. */
5653 #define ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER_SET(value) (((value) << 1) & 0xfffffffe)
5654 
5655 #ifndef __ASSEMBLY__
5656 /*
5657  * WARNING: The C register and register group struct declarations are provided for
5658  * convenience and illustrative purposes. They should, however, be used with
5659  * caution as the C language standard provides no guarantees about the alignment or
5660  * atomicity of device memory accesses. The recommended practice for coding device
5661  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5662  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5663  * alt_write_dword() functions for 64 bit registers.
5664  *
5665  * The struct declaration for register ALT_I2C_IC_CLR_RX_UNDER.
5666  */
5667 struct ALT_I2C_IC_CLR_RX_UNDER_s
5668 {
5669  const volatile uint32_t CLR_RX_UNDER : 1; /* ALT_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER */
5670  const volatile uint32_t RSVD_IC_CLR_RX_UNDER : 31; /* ALT_I2C_IC_CLR_RX_UNDER_RSVD_IC_CLR_RX_UNDER */
5671 };
5672 
5673 /* The typedef declaration for register ALT_I2C_IC_CLR_RX_UNDER. */
5674 typedef struct ALT_I2C_IC_CLR_RX_UNDER_s ALT_I2C_IC_CLR_RX_UNDER_t;
5675 #endif /* __ASSEMBLY__ */
5676 
5677 /* The reset value of the ALT_I2C_IC_CLR_RX_UNDER register. */
5678 #define ALT_I2C_IC_CLR_RX_UNDER_RESET 0x00000000
5679 /* The byte offset of the ALT_I2C_IC_CLR_RX_UNDER register from the beginning of the component. */
5680 #define ALT_I2C_IC_CLR_RX_UNDER_OFST 0x44
5681 /* The address of the ALT_I2C_IC_CLR_RX_UNDER register. */
5682 #define ALT_I2C_IC_CLR_RX_UNDER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_RX_UNDER_OFST))
5683 
5684 /*
5685  * Register : Clear RX_OVER Interrupt Register - IC_CLR_RX_OVER
5686  *
5687  * Name: Clear RX_OVER Interrupt Register
5688  *
5689  * Size: 1 bit
5690  *
5691  * Address Offset: 0x48
5692  *
5693  * Read/Write Access: Read
5694  *
5695  * Register Layout
5696  *
5697  * Bits | Access | Reset | Description
5698  * :-------|:-------|:------|:-------------------------------------------
5699  * [0] | R | 0x0 | ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER
5700  * [31:1] | R | 0x0 | ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER
5701  *
5702  */
5703 /*
5704  * Field : CLR_RX_OVER
5705  *
5706  * Read this register to clear the RX_OVER
5707  *
5708  * interrupt (bit 1) of the IC_RAW_INTR_STAT register.
5709  *
5710  * Reset value: 0x0
5711  *
5712  * Field Access Macros:
5713  *
5714  */
5715 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER register field. */
5716 #define ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER_LSB 0
5717 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER register field. */
5718 #define ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER_MSB 0
5719 /* The width in bits of the ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER register field. */
5720 #define ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER_WIDTH 1
5721 /* The mask used to set the ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER register field value. */
5722 #define ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER_SET_MSK 0x00000001
5723 /* The mask used to clear the ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER register field value. */
5724 #define ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER_CLR_MSK 0xfffffffe
5725 /* The reset value of the ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER register field. */
5726 #define ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER_RESET 0x0
5727 /* Extracts the ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER field value from a register. */
5728 #define ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER_GET(value) (((value) & 0x00000001) >> 0)
5729 /* Produces a ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER register field value suitable for setting the register. */
5730 #define ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER_SET(value) (((value) << 0) & 0x00000001)
5731 
5732 /*
5733  * Field : RSVD_IC_CLR_RX_OVER
5734  *
5735  * Reserved bits - Read Only
5736  *
5737  * Field Access Macros:
5738  *
5739  */
5740 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER register field. */
5741 #define ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER_LSB 1
5742 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER register field. */
5743 #define ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER_MSB 31
5744 /* The width in bits of the ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER register field. */
5745 #define ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER_WIDTH 31
5746 /* The mask used to set the ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER register field value. */
5747 #define ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER_SET_MSK 0xfffffffe
5748 /* The mask used to clear the ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER register field value. */
5749 #define ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER_CLR_MSK 0x00000001
5750 /* The reset value of the ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER register field. */
5751 #define ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER_RESET 0x0
5752 /* Extracts the ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER field value from a register. */
5753 #define ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER_GET(value) (((value) & 0xfffffffe) >> 1)
5754 /* Produces a ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER register field value suitable for setting the register. */
5755 #define ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER_SET(value) (((value) << 1) & 0xfffffffe)
5756 
5757 #ifndef __ASSEMBLY__
5758 /*
5759  * WARNING: The C register and register group struct declarations are provided for
5760  * convenience and illustrative purposes. They should, however, be used with
5761  * caution as the C language standard provides no guarantees about the alignment or
5762  * atomicity of device memory accesses. The recommended practice for coding device
5763  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5764  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5765  * alt_write_dword() functions for 64 bit registers.
5766  *
5767  * The struct declaration for register ALT_I2C_IC_CLR_RX_OVER.
5768  */
5769 struct ALT_I2C_IC_CLR_RX_OVER_s
5770 {
5771  const volatile uint32_t CLR_RX_OVER : 1; /* ALT_I2C_IC_CLR_RX_OVER_CLR_RX_OVER */
5772  const volatile uint32_t RSVD_IC_CLR_RX_OVER : 31; /* ALT_I2C_IC_CLR_RX_OVER_RSVD_IC_CLR_RX_OVER */
5773 };
5774 
5775 /* The typedef declaration for register ALT_I2C_IC_CLR_RX_OVER. */
5776 typedef struct ALT_I2C_IC_CLR_RX_OVER_s ALT_I2C_IC_CLR_RX_OVER_t;
5777 #endif /* __ASSEMBLY__ */
5778 
5779 /* The reset value of the ALT_I2C_IC_CLR_RX_OVER register. */
5780 #define ALT_I2C_IC_CLR_RX_OVER_RESET 0x00000000
5781 /* The byte offset of the ALT_I2C_IC_CLR_RX_OVER register from the beginning of the component. */
5782 #define ALT_I2C_IC_CLR_RX_OVER_OFST 0x48
5783 /* The address of the ALT_I2C_IC_CLR_RX_OVER register. */
5784 #define ALT_I2C_IC_CLR_RX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_RX_OVER_OFST))
5785 
5786 /*
5787  * Register : Clear TX_OVER Interrupt Register - IC_CLR_TX_OVER
5788  *
5789  * Name: Clear TX_OVER Interrupt Register
5790  *
5791  * Size: 1 bit
5792  *
5793  * Address Offset: 0x4c
5794  *
5795  * Read/Write Access: Read
5796  *
5797  * Register Layout
5798  *
5799  * Bits | Access | Reset | Description
5800  * :-------|:-------|:------|:-------------------------------------------
5801  * [0] | R | 0x0 | ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER
5802  * [31:1] | R | 0x0 | ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER
5803  *
5804  */
5805 /*
5806  * Field : CLR_TX_OVER
5807  *
5808  * Read this register to clear the TX_OVER
5809  *
5810  * interrupt (bit 3) of the IC_RAW_INTR_STAT register.
5811  *
5812  * Reset value: 0x0
5813  *
5814  * Field Access Macros:
5815  *
5816  */
5817 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER register field. */
5818 #define ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER_LSB 0
5819 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER register field. */
5820 #define ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER_MSB 0
5821 /* The width in bits of the ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER register field. */
5822 #define ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER_WIDTH 1
5823 /* The mask used to set the ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER register field value. */
5824 #define ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER_SET_MSK 0x00000001
5825 /* The mask used to clear the ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER register field value. */
5826 #define ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER_CLR_MSK 0xfffffffe
5827 /* The reset value of the ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER register field. */
5828 #define ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER_RESET 0x0
5829 /* Extracts the ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER field value from a register. */
5830 #define ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER_GET(value) (((value) & 0x00000001) >> 0)
5831 /* Produces a ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER register field value suitable for setting the register. */
5832 #define ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER_SET(value) (((value) << 0) & 0x00000001)
5833 
5834 /*
5835  * Field : RSVD_IC_CLR_TX_OVER
5836  *
5837  * Reserved bits - Read Only
5838  *
5839  * Field Access Macros:
5840  *
5841  */
5842 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER register field. */
5843 #define ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER_LSB 1
5844 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER register field. */
5845 #define ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER_MSB 31
5846 /* The width in bits of the ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER register field. */
5847 #define ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER_WIDTH 31
5848 /* The mask used to set the ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER register field value. */
5849 #define ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER_SET_MSK 0xfffffffe
5850 /* The mask used to clear the ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER register field value. */
5851 #define ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER_CLR_MSK 0x00000001
5852 /* The reset value of the ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER register field. */
5853 #define ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER_RESET 0x0
5854 /* Extracts the ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER field value from a register. */
5855 #define ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER_GET(value) (((value) & 0xfffffffe) >> 1)
5856 /* Produces a ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER register field value suitable for setting the register. */
5857 #define ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER_SET(value) (((value) << 1) & 0xfffffffe)
5858 
5859 #ifndef __ASSEMBLY__
5860 /*
5861  * WARNING: The C register and register group struct declarations are provided for
5862  * convenience and illustrative purposes. They should, however, be used with
5863  * caution as the C language standard provides no guarantees about the alignment or
5864  * atomicity of device memory accesses. The recommended practice for coding device
5865  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5866  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5867  * alt_write_dword() functions for 64 bit registers.
5868  *
5869  * The struct declaration for register ALT_I2C_IC_CLR_TX_OVER.
5870  */
5871 struct ALT_I2C_IC_CLR_TX_OVER_s
5872 {
5873  const volatile uint32_t CLR_TX_OVER : 1; /* ALT_I2C_IC_CLR_TX_OVER_CLR_TX_OVER */
5874  const volatile uint32_t RSVD_IC_CLR_TX_OVER : 31; /* ALT_I2C_IC_CLR_TX_OVER_RSVD_IC_CLR_TX_OVER */
5875 };
5876 
5877 /* The typedef declaration for register ALT_I2C_IC_CLR_TX_OVER. */
5878 typedef struct ALT_I2C_IC_CLR_TX_OVER_s ALT_I2C_IC_CLR_TX_OVER_t;
5879 #endif /* __ASSEMBLY__ */
5880 
5881 /* The reset value of the ALT_I2C_IC_CLR_TX_OVER register. */
5882 #define ALT_I2C_IC_CLR_TX_OVER_RESET 0x00000000
5883 /* The byte offset of the ALT_I2C_IC_CLR_TX_OVER register from the beginning of the component. */
5884 #define ALT_I2C_IC_CLR_TX_OVER_OFST 0x4c
5885 /* The address of the ALT_I2C_IC_CLR_TX_OVER register. */
5886 #define ALT_I2C_IC_CLR_TX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_TX_OVER_OFST))
5887 
5888 /*
5889  * Register : Clear RD_REQ Interrupt Register - IC_CLR_RD_REQ
5890  *
5891  * Name: Clear RD_REQ Interrupt Register
5892  *
5893  * Size: 1 bit
5894  *
5895  * Address Offset: 0x50
5896  *
5897  * Read/Write Access: Read
5898  *
5899  * Dependencies: This register is not applicable when IC_ULTRA_FAST_MODE=1
5900  *
5901  * Register Layout
5902  *
5903  * Bits | Access | Reset | Description
5904  * :-------|:-------|:------|:-----------------------------------------
5905  * [0] | R | 0x0 | ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ
5906  * [31:1] | R | 0x0 | ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ
5907  *
5908  */
5909 /*
5910  * Field : CLR_RD_REQ
5911  *
5912  * Read this register to clear the RD_REQ
5913  *
5914  * interrupt (bit 5) of the IC_RAW_INTR_STAT register.
5915  *
5916  * Reset value: 0x0
5917  *
5918  * Field Access Macros:
5919  *
5920  */
5921 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ register field. */
5922 #define ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ_LSB 0
5923 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ register field. */
5924 #define ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ_MSB 0
5925 /* The width in bits of the ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ register field. */
5926 #define ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ_WIDTH 1
5927 /* The mask used to set the ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ register field value. */
5928 #define ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ_SET_MSK 0x00000001
5929 /* The mask used to clear the ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ register field value. */
5930 #define ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ_CLR_MSK 0xfffffffe
5931 /* The reset value of the ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ register field. */
5932 #define ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ_RESET 0x0
5933 /* Extracts the ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ field value from a register. */
5934 #define ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ_GET(value) (((value) & 0x00000001) >> 0)
5935 /* Produces a ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ register field value suitable for setting the register. */
5936 #define ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ_SET(value) (((value) << 0) & 0x00000001)
5937 
5938 /*
5939  * Field : RSVD_IC_CLR_RD_REQ
5940  *
5941  * Reserved bits - Read Only
5942  *
5943  * Field Access Macros:
5944  *
5945  */
5946 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ register field. */
5947 #define ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ_LSB 1
5948 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ register field. */
5949 #define ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ_MSB 31
5950 /* The width in bits of the ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ register field. */
5951 #define ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ_WIDTH 31
5952 /* The mask used to set the ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ register field value. */
5953 #define ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ_SET_MSK 0xfffffffe
5954 /* The mask used to clear the ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ register field value. */
5955 #define ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ_CLR_MSK 0x00000001
5956 /* The reset value of the ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ register field. */
5957 #define ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ_RESET 0x0
5958 /* Extracts the ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ field value from a register. */
5959 #define ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ_GET(value) (((value) & 0xfffffffe) >> 1)
5960 /* Produces a ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ register field value suitable for setting the register. */
5961 #define ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ_SET(value) (((value) << 1) & 0xfffffffe)
5962 
5963 #ifndef __ASSEMBLY__
5964 /*
5965  * WARNING: The C register and register group struct declarations are provided for
5966  * convenience and illustrative purposes. They should, however, be used with
5967  * caution as the C language standard provides no guarantees about the alignment or
5968  * atomicity of device memory accesses. The recommended practice for coding device
5969  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5970  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5971  * alt_write_dword() functions for 64 bit registers.
5972  *
5973  * The struct declaration for register ALT_I2C_IC_CLR_RD_REQ.
5974  */
5975 struct ALT_I2C_IC_CLR_RD_REQ_s
5976 {
5977  const volatile uint32_t CLR_RD_REQ : 1; /* ALT_I2C_IC_CLR_RD_REQ_CLR_RD_REQ */
5978  const volatile uint32_t RSVD_IC_CLR_RD_REQ : 31; /* ALT_I2C_IC_CLR_RD_REQ_RSVD_IC_CLR_RD_REQ */
5979 };
5980 
5981 /* The typedef declaration for register ALT_I2C_IC_CLR_RD_REQ. */
5982 typedef struct ALT_I2C_IC_CLR_RD_REQ_s ALT_I2C_IC_CLR_RD_REQ_t;
5983 #endif /* __ASSEMBLY__ */
5984 
5985 /* The reset value of the ALT_I2C_IC_CLR_RD_REQ register. */
5986 #define ALT_I2C_IC_CLR_RD_REQ_RESET 0x00000000
5987 /* The byte offset of the ALT_I2C_IC_CLR_RD_REQ register from the beginning of the component. */
5988 #define ALT_I2C_IC_CLR_RD_REQ_OFST 0x50
5989 /* The address of the ALT_I2C_IC_CLR_RD_REQ register. */
5990 #define ALT_I2C_IC_CLR_RD_REQ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_RD_REQ_OFST))
5991 
5992 /*
5993  * Register : Clear TX_ABRT Interrupt Register - IC_CLR_TX_ABRT
5994  *
5995  * Name: Clear TX_ABRT Interrupt Register
5996  *
5997  * Size: 1 bit
5998  *
5999  * Address Offset: 0x54
6000  *
6001  * Read/Write Access: Read
6002  *
6003  * Register Layout
6004  *
6005  * Bits | Access | Reset | Description
6006  * :-------|:-------|:------|:-------------------------------------------
6007  * [0] | R | 0x0 | ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT
6008  * [31:1] | R | 0x0 | ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT
6009  *
6010  */
6011 /*
6012  * Field : CLR_TX_ABRT
6013  *
6014  * Read this register to clear the TX_ABRT
6015  *
6016  * interrupt (bit 6) of the IC_RAW_INTR_STAT register,
6017  *
6018  * and the IC_TX_ABRT_SOURCE register.
6019  *
6020  * This also releases the TX FIFO from the flushed/reset
6021  *
6022  * state, allowing more writes to the TX FIFO.
6023  *
6024  * Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for
6025  *
6026  * an exception to clearing IC_TX_ABRT_SOURCE.
6027  *
6028  * Reset value: 0x0
6029  *
6030  * Field Access Macros:
6031  *
6032  */
6033 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT register field. */
6034 #define ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_LSB 0
6035 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT register field. */
6036 #define ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_MSB 0
6037 /* The width in bits of the ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT register field. */
6038 #define ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_WIDTH 1
6039 /* The mask used to set the ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT register field value. */
6040 #define ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_SET_MSK 0x00000001
6041 /* The mask used to clear the ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT register field value. */
6042 #define ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_CLR_MSK 0xfffffffe
6043 /* The reset value of the ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT register field. */
6044 #define ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_RESET 0x0
6045 /* Extracts the ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT field value from a register. */
6046 #define ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_GET(value) (((value) & 0x00000001) >> 0)
6047 /* Produces a ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT register field value suitable for setting the register. */
6048 #define ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_SET(value) (((value) << 0) & 0x00000001)
6049 
6050 /*
6051  * Field : RSVD_IC_CLR_TX_ABRT
6052  *
6053  * Reserved bits - Read Only
6054  *
6055  * Field Access Macros:
6056  *
6057  */
6058 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT register field. */
6059 #define ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT_LSB 1
6060 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT register field. */
6061 #define ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT_MSB 31
6062 /* The width in bits of the ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT register field. */
6063 #define ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT_WIDTH 31
6064 /* The mask used to set the ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT register field value. */
6065 #define ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT_SET_MSK 0xfffffffe
6066 /* The mask used to clear the ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT register field value. */
6067 #define ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT_CLR_MSK 0x00000001
6068 /* The reset value of the ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT register field. */
6069 #define ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT_RESET 0x0
6070 /* Extracts the ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT field value from a register. */
6071 #define ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT_GET(value) (((value) & 0xfffffffe) >> 1)
6072 /* Produces a ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT register field value suitable for setting the register. */
6073 #define ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT_SET(value) (((value) << 1) & 0xfffffffe)
6074 
6075 #ifndef __ASSEMBLY__
6076 /*
6077  * WARNING: The C register and register group struct declarations are provided for
6078  * convenience and illustrative purposes. They should, however, be used with
6079  * caution as the C language standard provides no guarantees about the alignment or
6080  * atomicity of device memory accesses. The recommended practice for coding device
6081  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6082  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6083  * alt_write_dword() functions for 64 bit registers.
6084  *
6085  * The struct declaration for register ALT_I2C_IC_CLR_TX_ABRT.
6086  */
6087 struct ALT_I2C_IC_CLR_TX_ABRT_s
6088 {
6089  const volatile uint32_t CLR_TX_ABRT : 1; /* ALT_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT */
6090  const volatile uint32_t RSVD_IC_CLR_TX_ABRT : 31; /* ALT_I2C_IC_CLR_TX_ABRT_RSVD_IC_CLR_TX_ABRT */
6091 };
6092 
6093 /* The typedef declaration for register ALT_I2C_IC_CLR_TX_ABRT. */
6094 typedef struct ALT_I2C_IC_CLR_TX_ABRT_s ALT_I2C_IC_CLR_TX_ABRT_t;
6095 #endif /* __ASSEMBLY__ */
6096 
6097 /* The reset value of the ALT_I2C_IC_CLR_TX_ABRT register. */
6098 #define ALT_I2C_IC_CLR_TX_ABRT_RESET 0x00000000
6099 /* The byte offset of the ALT_I2C_IC_CLR_TX_ABRT register from the beginning of the component. */
6100 #define ALT_I2C_IC_CLR_TX_ABRT_OFST 0x54
6101 /* The address of the ALT_I2C_IC_CLR_TX_ABRT register. */
6102 #define ALT_I2C_IC_CLR_TX_ABRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_TX_ABRT_OFST))
6103 
6104 /*
6105  * Register : Clear RX_DONE Interrupt Register - IC_CLR_RX_DONE
6106  *
6107  * Name: Clear RX_DONE Interrupt Register
6108  *
6109  * Size: 1 bit
6110  *
6111  * Address Offset: 0x58
6112  *
6113  * Read/Write Access: Read
6114  *
6115  * Dependencies: This register is not applicable when IC_ULTRA_FAST_MODE=1
6116  *
6117  * Register Layout
6118  *
6119  * Bits | Access | Reset | Description
6120  * :-------|:-------|:------|:-------------------------------------------
6121  * [0] | R | 0x0 | ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE
6122  * [31:1] | R | 0x0 | ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE
6123  *
6124  */
6125 /*
6126  * Field : CLR_RX_DONE
6127  *
6128  * Read this register to clear the RX_DONE
6129  *
6130  * interrupt (bit 7) of the IC_RAW_INTR_STAT register.
6131  *
6132  * Reset value: 0x0
6133  *
6134  * Field Access Macros:
6135  *
6136  */
6137 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE register field. */
6138 #define ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE_LSB 0
6139 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE register field. */
6140 #define ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE_MSB 0
6141 /* The width in bits of the ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE register field. */
6142 #define ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE_WIDTH 1
6143 /* The mask used to set the ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE register field value. */
6144 #define ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE_SET_MSK 0x00000001
6145 /* The mask used to clear the ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE register field value. */
6146 #define ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE_CLR_MSK 0xfffffffe
6147 /* The reset value of the ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE register field. */
6148 #define ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE_RESET 0x0
6149 /* Extracts the ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE field value from a register. */
6150 #define ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE_GET(value) (((value) & 0x00000001) >> 0)
6151 /* Produces a ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE register field value suitable for setting the register. */
6152 #define ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE_SET(value) (((value) << 0) & 0x00000001)
6153 
6154 /*
6155  * Field : RSVD_IC_CLR_RX_DONE
6156  *
6157  * Reserved bits - Read Only
6158  *
6159  * Field Access Macros:
6160  *
6161  */
6162 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE register field. */
6163 #define ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE_LSB 1
6164 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE register field. */
6165 #define ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE_MSB 31
6166 /* The width in bits of the ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE register field. */
6167 #define ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE_WIDTH 31
6168 /* The mask used to set the ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE register field value. */
6169 #define ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE_SET_MSK 0xfffffffe
6170 /* The mask used to clear the ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE register field value. */
6171 #define ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE_CLR_MSK 0x00000001
6172 /* The reset value of the ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE register field. */
6173 #define ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE_RESET 0x0
6174 /* Extracts the ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE field value from a register. */
6175 #define ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE_GET(value) (((value) & 0xfffffffe) >> 1)
6176 /* Produces a ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE register field value suitable for setting the register. */
6177 #define ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE_SET(value) (((value) << 1) & 0xfffffffe)
6178 
6179 #ifndef __ASSEMBLY__
6180 /*
6181  * WARNING: The C register and register group struct declarations are provided for
6182  * convenience and illustrative purposes. They should, however, be used with
6183  * caution as the C language standard provides no guarantees about the alignment or
6184  * atomicity of device memory accesses. The recommended practice for coding device
6185  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6186  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6187  * alt_write_dword() functions for 64 bit registers.
6188  *
6189  * The struct declaration for register ALT_I2C_IC_CLR_RX_DONE.
6190  */
6191 struct ALT_I2C_IC_CLR_RX_DONE_s
6192 {
6193  const volatile uint32_t CLR_RX_DONE : 1; /* ALT_I2C_IC_CLR_RX_DONE_CLR_RX_DONE */
6194  const volatile uint32_t RSVD_IC_CLR_RX_DONE : 31; /* ALT_I2C_IC_CLR_RX_DONE_RSVD_IC_CLR_RX_DONE */
6195 };
6196 
6197 /* The typedef declaration for register ALT_I2C_IC_CLR_RX_DONE. */
6198 typedef struct ALT_I2C_IC_CLR_RX_DONE_s ALT_I2C_IC_CLR_RX_DONE_t;
6199 #endif /* __ASSEMBLY__ */
6200 
6201 /* The reset value of the ALT_I2C_IC_CLR_RX_DONE register. */
6202 #define ALT_I2C_IC_CLR_RX_DONE_RESET 0x00000000
6203 /* The byte offset of the ALT_I2C_IC_CLR_RX_DONE register from the beginning of the component. */
6204 #define ALT_I2C_IC_CLR_RX_DONE_OFST 0x58
6205 /* The address of the ALT_I2C_IC_CLR_RX_DONE register. */
6206 #define ALT_I2C_IC_CLR_RX_DONE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_RX_DONE_OFST))
6207 
6208 /*
6209  * Register : Clear ACTIVITY Interrupt Register - IC_CLR_ACTIVITY
6210  *
6211  * Name: Clear ACTIVITY Interrupt Register
6212  *
6213  * Size: 1 bit
6214  *
6215  * Address Offset: 0x5c
6216  *
6217  * Read/Write Access: Read
6218  *
6219  * Register Layout
6220  *
6221  * Bits | Access | Reset | Description
6222  * :-------|:-------|:------|:---------------------------------------------
6223  * [0] | R | 0x0 | ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY
6224  * [31:1] | R | 0x0 | ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY
6225  *
6226  */
6227 /*
6228  * Field : CLR_ACTIVITY
6229  *
6230  * Reading this register clears the ACTIVITY
6231  *
6232  * interrupt if the I2C is not active anymore. If the
6233  *
6234  * I2C module is still active on the bus, the ACTIVITY
6235  *
6236  * interrupt bit continues to be set. It is automatically
6237  *
6238  * cleared by hardware if the module is disabled and if
6239  *
6240  * there is no further activity on the bus. The value read
6241  *
6242  * from this register to get status of the ACTIVITY interrupt
6243  *
6244  * (bit 8) of the IC_RAW_INTR_STAT register.
6245  *
6246  * Reset value: 0x0
6247  *
6248  * Field Access Macros:
6249  *
6250  */
6251 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY register field. */
6252 #define ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_LSB 0
6253 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY register field. */
6254 #define ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_MSB 0
6255 /* The width in bits of the ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY register field. */
6256 #define ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_WIDTH 1
6257 /* The mask used to set the ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY register field value. */
6258 #define ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_SET_MSK 0x00000001
6259 /* The mask used to clear the ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY register field value. */
6260 #define ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_CLR_MSK 0xfffffffe
6261 /* The reset value of the ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY register field. */
6262 #define ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_RESET 0x0
6263 /* Extracts the ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY field value from a register. */
6264 #define ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0)
6265 /* Produces a ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY register field value suitable for setting the register. */
6266 #define ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_SET(value) (((value) << 0) & 0x00000001)
6267 
6268 /*
6269  * Field : RSVD_IC_CLR_ACTIVITY
6270  *
6271  * Reserved bits - Read Only
6272  *
6273  * Field Access Macros:
6274  *
6275  */
6276 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY register field. */
6277 #define ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY_LSB 1
6278 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY register field. */
6279 #define ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY_MSB 31
6280 /* The width in bits of the ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY register field. */
6281 #define ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY_WIDTH 31
6282 /* The mask used to set the ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY register field value. */
6283 #define ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY_SET_MSK 0xfffffffe
6284 /* The mask used to clear the ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY register field value. */
6285 #define ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY_CLR_MSK 0x00000001
6286 /* The reset value of the ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY register field. */
6287 #define ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY_RESET 0x0
6288 /* Extracts the ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY field value from a register. */
6289 #define ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY_GET(value) (((value) & 0xfffffffe) >> 1)
6290 /* Produces a ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY register field value suitable for setting the register. */
6291 #define ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY_SET(value) (((value) << 1) & 0xfffffffe)
6292 
6293 #ifndef __ASSEMBLY__
6294 /*
6295  * WARNING: The C register and register group struct declarations are provided for
6296  * convenience and illustrative purposes. They should, however, be used with
6297  * caution as the C language standard provides no guarantees about the alignment or
6298  * atomicity of device memory accesses. The recommended practice for coding device
6299  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6300  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6301  * alt_write_dword() functions for 64 bit registers.
6302  *
6303  * The struct declaration for register ALT_I2C_IC_CLR_ACTIVITY.
6304  */
6305 struct ALT_I2C_IC_CLR_ACTIVITY_s
6306 {
6307  const volatile uint32_t CLR_ACTIVITY : 1; /* ALT_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY */
6308  const volatile uint32_t RSVD_IC_CLR_ACTIVITY : 31; /* ALT_I2C_IC_CLR_ACTIVITY_RSVD_IC_CLR_ACTIVITY */
6309 };
6310 
6311 /* The typedef declaration for register ALT_I2C_IC_CLR_ACTIVITY. */
6312 typedef struct ALT_I2C_IC_CLR_ACTIVITY_s ALT_I2C_IC_CLR_ACTIVITY_t;
6313 #endif /* __ASSEMBLY__ */
6314 
6315 /* The reset value of the ALT_I2C_IC_CLR_ACTIVITY register. */
6316 #define ALT_I2C_IC_CLR_ACTIVITY_RESET 0x00000000
6317 /* The byte offset of the ALT_I2C_IC_CLR_ACTIVITY register from the beginning of the component. */
6318 #define ALT_I2C_IC_CLR_ACTIVITY_OFST 0x5c
6319 /* The address of the ALT_I2C_IC_CLR_ACTIVITY register. */
6320 #define ALT_I2C_IC_CLR_ACTIVITY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_ACTIVITY_OFST))
6321 
6322 /*
6323  * Register : Clear STOP_DET Interrupt Register - IC_CLR_STOP_DET
6324  *
6325  * Name: Clear STOP_DET Interrupt Register
6326  *
6327  * Size: 1 bit
6328  *
6329  * Address Offset: 0x60
6330  *
6331  * Read/Write Access: Read
6332  *
6333  * Register Layout
6334  *
6335  * Bits | Access | Reset | Description
6336  * :-------|:-------|:------|:---------------------------------------------
6337  * [0] | R | 0x0 | ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET
6338  * [31:1] | R | 0x0 | ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET
6339  *
6340  */
6341 /*
6342  * Field : CLR_STOP_DET
6343  *
6344  * Read this register to clear the STOP_DET
6345  *
6346  * interrupt (bit 9) of the IC_RAW_INTR_STAT register.
6347  *
6348  * Reset value: 0x0
6349  *
6350  * Field Access Macros:
6351  *
6352  */
6353 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET register field. */
6354 #define ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET_LSB 0
6355 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET register field. */
6356 #define ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET_MSB 0
6357 /* The width in bits of the ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET register field. */
6358 #define ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET_WIDTH 1
6359 /* The mask used to set the ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET register field value. */
6360 #define ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET_SET_MSK 0x00000001
6361 /* The mask used to clear the ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET register field value. */
6362 #define ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET_CLR_MSK 0xfffffffe
6363 /* The reset value of the ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET register field. */
6364 #define ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET_RESET 0x0
6365 /* Extracts the ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET field value from a register. */
6366 #define ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET_GET(value) (((value) & 0x00000001) >> 0)
6367 /* Produces a ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET register field value suitable for setting the register. */
6368 #define ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET_SET(value) (((value) << 0) & 0x00000001)
6369 
6370 /*
6371  * Field : RSVD_IC_CLR_STOP_DET
6372  *
6373  * Reserved bits - Read Only
6374  *
6375  * Field Access Macros:
6376  *
6377  */
6378 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET register field. */
6379 #define ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET_LSB 1
6380 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET register field. */
6381 #define ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET_MSB 31
6382 /* The width in bits of the ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET register field. */
6383 #define ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET_WIDTH 31
6384 /* The mask used to set the ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET register field value. */
6385 #define ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET_SET_MSK 0xfffffffe
6386 /* The mask used to clear the ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET register field value. */
6387 #define ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET_CLR_MSK 0x00000001
6388 /* The reset value of the ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET register field. */
6389 #define ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET_RESET 0x0
6390 /* Extracts the ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET field value from a register. */
6391 #define ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET_GET(value) (((value) & 0xfffffffe) >> 1)
6392 /* Produces a ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET register field value suitable for setting the register. */
6393 #define ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET_SET(value) (((value) << 1) & 0xfffffffe)
6394 
6395 #ifndef __ASSEMBLY__
6396 /*
6397  * WARNING: The C register and register group struct declarations are provided for
6398  * convenience and illustrative purposes. They should, however, be used with
6399  * caution as the C language standard provides no guarantees about the alignment or
6400  * atomicity of device memory accesses. The recommended practice for coding device
6401  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6402  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6403  * alt_write_dword() functions for 64 bit registers.
6404  *
6405  * The struct declaration for register ALT_I2C_IC_CLR_STOP_DET.
6406  */
6407 struct ALT_I2C_IC_CLR_STOP_DET_s
6408 {
6409  const volatile uint32_t CLR_STOP_DET : 1; /* ALT_I2C_IC_CLR_STOP_DET_CLR_STOP_DET */
6410  const volatile uint32_t RSVD_IC_CLR_STOP_DET : 31; /* ALT_I2C_IC_CLR_STOP_DET_RSVD_IC_CLR_STOP_DET */
6411 };
6412 
6413 /* The typedef declaration for register ALT_I2C_IC_CLR_STOP_DET. */
6414 typedef struct ALT_I2C_IC_CLR_STOP_DET_s ALT_I2C_IC_CLR_STOP_DET_t;
6415 #endif /* __ASSEMBLY__ */
6416 
6417 /* The reset value of the ALT_I2C_IC_CLR_STOP_DET register. */
6418 #define ALT_I2C_IC_CLR_STOP_DET_RESET 0x00000000
6419 /* The byte offset of the ALT_I2C_IC_CLR_STOP_DET register from the beginning of the component. */
6420 #define ALT_I2C_IC_CLR_STOP_DET_OFST 0x60
6421 /* The address of the ALT_I2C_IC_CLR_STOP_DET register. */
6422 #define ALT_I2C_IC_CLR_STOP_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_STOP_DET_OFST))
6423 
6424 /*
6425  * Register : Clear START_DET Interrupt Register - IC_CLR_START_DET
6426  *
6427  * Name: Clear START_DET Interrupt Register
6428  *
6429  * Size: 1 bit
6430  *
6431  * Address Offset: 0x64
6432  *
6433  * Read/Write Access: Read
6434  *
6435  * Register Layout
6436  *
6437  * Bits | Access | Reset | Description
6438  * :-------|:-------|:------|:-----------------------------------------------
6439  * [0] | R | 0x0 | ALT_I2C_IC_CLR_START_DET_CLR_START_DET
6440  * [31:1] | R | 0x0 | ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET
6441  *
6442  */
6443 /*
6444  * Field : CLR_START_DET
6445  *
6446  * Read this register to clear the START_DET
6447  *
6448  * interrupt (bit 10) of the IC_RAW_INTR_STAT register.
6449  *
6450  * Reset value: 0x0
6451  *
6452  * Field Access Macros:
6453  *
6454  */
6455 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_START_DET_CLR_START_DET register field. */
6456 #define ALT_I2C_IC_CLR_START_DET_CLR_START_DET_LSB 0
6457 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_START_DET_CLR_START_DET register field. */
6458 #define ALT_I2C_IC_CLR_START_DET_CLR_START_DET_MSB 0
6459 /* The width in bits of the ALT_I2C_IC_CLR_START_DET_CLR_START_DET register field. */
6460 #define ALT_I2C_IC_CLR_START_DET_CLR_START_DET_WIDTH 1
6461 /* The mask used to set the ALT_I2C_IC_CLR_START_DET_CLR_START_DET register field value. */
6462 #define ALT_I2C_IC_CLR_START_DET_CLR_START_DET_SET_MSK 0x00000001
6463 /* The mask used to clear the ALT_I2C_IC_CLR_START_DET_CLR_START_DET register field value. */
6464 #define ALT_I2C_IC_CLR_START_DET_CLR_START_DET_CLR_MSK 0xfffffffe
6465 /* The reset value of the ALT_I2C_IC_CLR_START_DET_CLR_START_DET register field. */
6466 #define ALT_I2C_IC_CLR_START_DET_CLR_START_DET_RESET 0x0
6467 /* Extracts the ALT_I2C_IC_CLR_START_DET_CLR_START_DET field value from a register. */
6468 #define ALT_I2C_IC_CLR_START_DET_CLR_START_DET_GET(value) (((value) & 0x00000001) >> 0)
6469 /* Produces a ALT_I2C_IC_CLR_START_DET_CLR_START_DET register field value suitable for setting the register. */
6470 #define ALT_I2C_IC_CLR_START_DET_CLR_START_DET_SET(value) (((value) << 0) & 0x00000001)
6471 
6472 /*
6473  * Field : RSVD_IC_CLR_START_DET
6474  *
6475  * Reserved bits - Read Only
6476  *
6477  * Field Access Macros:
6478  *
6479  */
6480 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET register field. */
6481 #define ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET_LSB 1
6482 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET register field. */
6483 #define ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET_MSB 31
6484 /* The width in bits of the ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET register field. */
6485 #define ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET_WIDTH 31
6486 /* The mask used to set the ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET register field value. */
6487 #define ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET_SET_MSK 0xfffffffe
6488 /* The mask used to clear the ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET register field value. */
6489 #define ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET_CLR_MSK 0x00000001
6490 /* The reset value of the ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET register field. */
6491 #define ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET_RESET 0x0
6492 /* Extracts the ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET field value from a register. */
6493 #define ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET_GET(value) (((value) & 0xfffffffe) >> 1)
6494 /* Produces a ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET register field value suitable for setting the register. */
6495 #define ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET_SET(value) (((value) << 1) & 0xfffffffe)
6496 
6497 #ifndef __ASSEMBLY__
6498 /*
6499  * WARNING: The C register and register group struct declarations are provided for
6500  * convenience and illustrative purposes. They should, however, be used with
6501  * caution as the C language standard provides no guarantees about the alignment or
6502  * atomicity of device memory accesses. The recommended practice for coding device
6503  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6504  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6505  * alt_write_dword() functions for 64 bit registers.
6506  *
6507  * The struct declaration for register ALT_I2C_IC_CLR_START_DET.
6508  */
6509 struct ALT_I2C_IC_CLR_START_DET_s
6510 {
6511  const volatile uint32_t CLR_START_DET : 1; /* ALT_I2C_IC_CLR_START_DET_CLR_START_DET */
6512  const volatile uint32_t RSVD_IC_CLR_START_DET : 31; /* ALT_I2C_IC_CLR_START_DET_RSVD_IC_CLR_START_DET */
6513 };
6514 
6515 /* The typedef declaration for register ALT_I2C_IC_CLR_START_DET. */
6516 typedef struct ALT_I2C_IC_CLR_START_DET_s ALT_I2C_IC_CLR_START_DET_t;
6517 #endif /* __ASSEMBLY__ */
6518 
6519 /* The reset value of the ALT_I2C_IC_CLR_START_DET register. */
6520 #define ALT_I2C_IC_CLR_START_DET_RESET 0x00000000
6521 /* The byte offset of the ALT_I2C_IC_CLR_START_DET register from the beginning of the component. */
6522 #define ALT_I2C_IC_CLR_START_DET_OFST 0x64
6523 /* The address of the ALT_I2C_IC_CLR_START_DET register. */
6524 #define ALT_I2C_IC_CLR_START_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_START_DET_OFST))
6525 
6526 /*
6527  * Register : Clear GEN_CALL Interrupt Register - IC_CLR_GEN_CALL
6528  *
6529  * Name: Clear GEN_CALL Interrupt Register
6530  *
6531  * Size: 1 bit
6532  *
6533  * Address Offset: 0x68
6534  *
6535  * Read/Write Access: Read
6536  *
6537  * Register Layout
6538  *
6539  * Bits | Access | Reset | Description
6540  * :-------|:-------|:------|:---------------------------------------------
6541  * [0] | R | 0x0 | ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL
6542  * [31:1] | R | 0x0 | ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL
6543  *
6544  */
6545 /*
6546  * Field : CLR_GEN_CALL
6547  *
6548  * Read this register to clear the GEN_CALL
6549  *
6550  * interrupt (bit 11) of IC_RAW_INTR_STAT register.
6551  *
6552  * Reset value: 0x0
6553  *
6554  * Field Access Macros:
6555  *
6556  */
6557 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL register field. */
6558 #define ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_LSB 0
6559 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL register field. */
6560 #define ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_MSB 0
6561 /* The width in bits of the ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL register field. */
6562 #define ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_WIDTH 1
6563 /* The mask used to set the ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL register field value. */
6564 #define ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_SET_MSK 0x00000001
6565 /* The mask used to clear the ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL register field value. */
6566 #define ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_CLR_MSK 0xfffffffe
6567 /* The reset value of the ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL register field. */
6568 #define ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_RESET 0x0
6569 /* Extracts the ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL field value from a register. */
6570 #define ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0)
6571 /* Produces a ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL register field value suitable for setting the register. */
6572 #define ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_SET(value) (((value) << 0) & 0x00000001)
6573 
6574 /*
6575  * Field : RSVD_IC_CLR_GEN_CALL
6576  *
6577  * Reserved bits - Read Only
6578  *
6579  * Field Access Macros:
6580  *
6581  */
6582 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL register field. */
6583 #define ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL_LSB 1
6584 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL register field. */
6585 #define ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL_MSB 31
6586 /* The width in bits of the ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL register field. */
6587 #define ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL_WIDTH 31
6588 /* The mask used to set the ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL register field value. */
6589 #define ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL_SET_MSK 0xfffffffe
6590 /* The mask used to clear the ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL register field value. */
6591 #define ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL_CLR_MSK 0x00000001
6592 /* The reset value of the ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL register field. */
6593 #define ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL_RESET 0x0
6594 /* Extracts the ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL field value from a register. */
6595 #define ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL_GET(value) (((value) & 0xfffffffe) >> 1)
6596 /* Produces a ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL register field value suitable for setting the register. */
6597 #define ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL_SET(value) (((value) << 1) & 0xfffffffe)
6598 
6599 #ifndef __ASSEMBLY__
6600 /*
6601  * WARNING: The C register and register group struct declarations are provided for
6602  * convenience and illustrative purposes. They should, however, be used with
6603  * caution as the C language standard provides no guarantees about the alignment or
6604  * atomicity of device memory accesses. The recommended practice for coding device
6605  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6606  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6607  * alt_write_dword() functions for 64 bit registers.
6608  *
6609  * The struct declaration for register ALT_I2C_IC_CLR_GEN_CALL.
6610  */
6611 struct ALT_I2C_IC_CLR_GEN_CALL_s
6612 {
6613  const volatile uint32_t CLR_GEN_CALL : 1; /* ALT_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL */
6614  const volatile uint32_t RSVD_IC_CLR_GEN_CALL : 31; /* ALT_I2C_IC_CLR_GEN_CALL_RSVD_IC_CLR_GEN_CALL */
6615 };
6616 
6617 /* The typedef declaration for register ALT_I2C_IC_CLR_GEN_CALL. */
6618 typedef struct ALT_I2C_IC_CLR_GEN_CALL_s ALT_I2C_IC_CLR_GEN_CALL_t;
6619 #endif /* __ASSEMBLY__ */
6620 
6621 /* The reset value of the ALT_I2C_IC_CLR_GEN_CALL register. */
6622 #define ALT_I2C_IC_CLR_GEN_CALL_RESET 0x00000000
6623 /* The byte offset of the ALT_I2C_IC_CLR_GEN_CALL register from the beginning of the component. */
6624 #define ALT_I2C_IC_CLR_GEN_CALL_OFST 0x68
6625 /* The address of the ALT_I2C_IC_CLR_GEN_CALL register. */
6626 #define ALT_I2C_IC_CLR_GEN_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_GEN_CALL_OFST))
6627 
6628 /*
6629  * Register : I2C ENABLE Register - IC_ENABLE
6630  *
6631  * Name: I2C Enable Register
6632  *
6633  * Size: 18 bits
6634  *
6635  * Address Offset: 0x6c
6636  *
6637  * Read/Write Access: Read/Write
6638  *
6639  * Bit 16 is read only when IC_SMBUS=0.
6640  *
6641  * Bits 17 & 18 are read only when IC_SMBUS_SUSPEND_ALERT=0.
6642  *
6643  * Register Layout
6644  *
6645  * Bits | Access | Reset | Description
6646  * :--------|:-------|:------|:-------------------------------------------------
6647  * [0] | RW | 0x0 | ALT_I2C_IC_ENABLE_ENABLE
6648  * [1] | RW | 0x0 | ALT_I2C_IC_ENABLE_ABORT
6649  * [2] | RW | 0x0 | ALT_I2C_IC_ENABLE_TX_CMD_BLOCK
6650  * [3] | R | 0x0 | ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE
6651  * [15:4] | R | 0x0 | ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1
6652  * [16] | R | 0x0 | ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET
6653  * [17] | R | 0x0 | ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN
6654  * [18] | R | 0x0 | ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN
6655  * [31:19] | R | 0x0 | ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2
6656  *
6657  */
6658 /*
6659  * Field : ENABLE
6660  *
6661  * Controls whether the DW_apb_i2c is enabled.
6662  *
6663  * 0: Disables DW_apb_i2c (TX and RX FIFOs are
6664  *
6665  * held in an erased state)
6666  *
6667  * 1: Enables DW_apb_i2c
6668  *
6669  * Software can disable DW_apb_i2c while it is active.
6670  *
6671  * However, it is important that care be taken to ensure
6672  *
6673  * that DW_apb_i2c is disabled properly.
6674  *
6675  * When DW_apb_i2c is disabled, the following occurs:
6676  *
6677  * * The TX FIFO and RX FIFO get flushed.
6678  *
6679  * * Status bits in the IC_INTR_STAT register are still
6680  *
6681  * active until DW_apb_i2c goes into IDLE state.
6682  *
6683  * If the module is transmitting, it stops as well as deletes
6684  *
6685  * the contents of the transmit buffer after the current transfer
6686  *
6687  * is complete. If the module is receiving, the DW_apb_i2c stops
6688  *
6689  * the current transfer at the end of the current byte and does not
6690  *
6691  * acknowledge the transfer.
6692  *
6693  * In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE
6694  *
6695  * parameter set to asynchronous (1), there is a two ic_clk delay
6696  *
6697  * when enabling or disabling the DW_apb_i2c.
6698  *
6699  * Reset value: 0x0
6700  *
6701  * Field Enumeration Values:
6702  *
6703  * Enum | Value | Description
6704  * :------------------------------------|:------|:----------------
6705  * ALT_I2C_IC_ENABLE_ENABLE_E_DISABLED | 0x0 | I2C is disabled
6706  * ALT_I2C_IC_ENABLE_ENABLE_E_ENABLED | 0x1 | I2C is enabled
6707  *
6708  * Field Access Macros:
6709  *
6710  */
6711 /*
6712  * Enumerated value for register field ALT_I2C_IC_ENABLE_ENABLE
6713  *
6714  * I2C is disabled
6715  */
6716 #define ALT_I2C_IC_ENABLE_ENABLE_E_DISABLED 0x0
6717 /*
6718  * Enumerated value for register field ALT_I2C_IC_ENABLE_ENABLE
6719  *
6720  * I2C is enabled
6721  */
6722 #define ALT_I2C_IC_ENABLE_ENABLE_E_ENABLED 0x1
6723 
6724 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_ENABLE_ENABLE register field. */
6725 #define ALT_I2C_IC_ENABLE_ENABLE_LSB 0
6726 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_ENABLE_ENABLE register field. */
6727 #define ALT_I2C_IC_ENABLE_ENABLE_MSB 0
6728 /* The width in bits of the ALT_I2C_IC_ENABLE_ENABLE register field. */
6729 #define ALT_I2C_IC_ENABLE_ENABLE_WIDTH 1
6730 /* The mask used to set the ALT_I2C_IC_ENABLE_ENABLE register field value. */
6731 #define ALT_I2C_IC_ENABLE_ENABLE_SET_MSK 0x00000001
6732 /* The mask used to clear the ALT_I2C_IC_ENABLE_ENABLE register field value. */
6733 #define ALT_I2C_IC_ENABLE_ENABLE_CLR_MSK 0xfffffffe
6734 /* The reset value of the ALT_I2C_IC_ENABLE_ENABLE register field. */
6735 #define ALT_I2C_IC_ENABLE_ENABLE_RESET 0x0
6736 /* Extracts the ALT_I2C_IC_ENABLE_ENABLE field value from a register. */
6737 #define ALT_I2C_IC_ENABLE_ENABLE_GET(value) (((value) & 0x00000001) >> 0)
6738 /* Produces a ALT_I2C_IC_ENABLE_ENABLE register field value suitable for setting the register. */
6739 #define ALT_I2C_IC_ENABLE_ENABLE_SET(value) (((value) << 0) & 0x00000001)
6740 
6741 /*
6742  * Field : ABORT
6743  *
6744  * When set, the controller initiates the transfer abort.
6745  *
6746  * 0: ABORT not initiated or ABORT done
6747  *
6748  * 1: ABORT operation in progress
6749  *
6750  * The software can abort the I2C transfer in master mode by setting this bit. The
6751  * software
6752  *
6753  * can set this bit only when ENABLE is already set; otherwise, the controller
6754  * ignores any
6755  *
6756  * write to ABORT bit. The software cannot clear the ABORT bit once set. In
6757  * response to
6758  *
6759  * an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing
6760  * the
6761  *
6762  * current transfer, then sets the TX_ABORT interrupt after the abort operation.
6763  * The
6764  *
6765  * ABORT bit is cleared automatically after the abort operation.
6766  *
6767  * Reset value: 0x0
6768  *
6769  * Field Enumeration Values:
6770  *
6771  * Enum | Value | Description
6772  * :----------------------------------|:------|:--------------------------------
6773  * ALT_I2C_IC_ENABLE_ABORT_E_DISABLE | 0x0 | ABORT operation not in progress
6774  * ALT_I2C_IC_ENABLE_ABORT_E_ENABLED | 0x1 | ABORT operation in progress
6775  *
6776  * Field Access Macros:
6777  *
6778  */
6779 /*
6780  * Enumerated value for register field ALT_I2C_IC_ENABLE_ABORT
6781  *
6782  * ABORT operation not in progress
6783  */
6784 #define ALT_I2C_IC_ENABLE_ABORT_E_DISABLE 0x0
6785 /*
6786  * Enumerated value for register field ALT_I2C_IC_ENABLE_ABORT
6787  *
6788  * ABORT operation in progress
6789  */
6790 #define ALT_I2C_IC_ENABLE_ABORT_E_ENABLED 0x1
6791 
6792 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_ENABLE_ABORT register field. */
6793 #define ALT_I2C_IC_ENABLE_ABORT_LSB 1
6794 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_ENABLE_ABORT register field. */
6795 #define ALT_I2C_IC_ENABLE_ABORT_MSB 1
6796 /* The width in bits of the ALT_I2C_IC_ENABLE_ABORT register field. */
6797 #define ALT_I2C_IC_ENABLE_ABORT_WIDTH 1
6798 /* The mask used to set the ALT_I2C_IC_ENABLE_ABORT register field value. */
6799 #define ALT_I2C_IC_ENABLE_ABORT_SET_MSK 0x00000002
6800 /* The mask used to clear the ALT_I2C_IC_ENABLE_ABORT register field value. */
6801 #define ALT_I2C_IC_ENABLE_ABORT_CLR_MSK 0xfffffffd
6802 /* The reset value of the ALT_I2C_IC_ENABLE_ABORT register field. */
6803 #define ALT_I2C_IC_ENABLE_ABORT_RESET 0x0
6804 /* Extracts the ALT_I2C_IC_ENABLE_ABORT field value from a register. */
6805 #define ALT_I2C_IC_ENABLE_ABORT_GET(value) (((value) & 0x00000002) >> 1)
6806 /* Produces a ALT_I2C_IC_ENABLE_ABORT register field value suitable for setting the register. */
6807 #define ALT_I2C_IC_ENABLE_ABORT_SET(value) (((value) << 1) & 0x00000002)
6808 
6809 /*
6810  * Field : TX_CMD_BLOCK
6811  *
6812  * In Master mode
6813  *
6814  * 1'b1 blocks the transmission of data on I2C bus even if Tx FIFO has data to
6815  * transmit.
6816  *
6817  * 1'b0 The transmission of data starts on I2C bus automatically, as soon as the
6818  * first data is available in the Tx FIFO.
6819  *
6820  * Reset value : IC_TX_CMD_BLOCK_DEFAULT
6821  *
6822  * Dependencies: This Register bit value is applicable only when IC_TX_CMD_BLOCK
6823  * =1
6824  *
6825  * NOTE:In order to block the execution of Master commands,
6826  *
6827  * set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and
6828  * Master is in Idle state (IC_STATUS[5] == 0).
6829  *
6830  * Then any further commands put in the Tx FIFO will not get executed until
6831  * TX_CMD_BLOCK bit is unset.
6832  *
6833  * Field Enumeration Values:
6834  *
6835  * Enum | Value | Description
6836  * :---------------------------------------------|:------|:---------------------------------
6837  * ALT_I2C_IC_ENABLE_TX_CMD_BLOCK_E_NOT_BLOCKED | 0x0 | Tx Command execution not blocked
6838  * ALT_I2C_IC_ENABLE_TX_CMD_BLOCK_E_BLOCKED | 0x1 | Tx Command execution blocked
6839  *
6840  * Field Access Macros:
6841  *
6842  */
6843 /*
6844  * Enumerated value for register field ALT_I2C_IC_ENABLE_TX_CMD_BLOCK
6845  *
6846  * Tx Command execution not blocked
6847  */
6848 #define ALT_I2C_IC_ENABLE_TX_CMD_BLOCK_E_NOT_BLOCKED 0x0
6849 /*
6850  * Enumerated value for register field ALT_I2C_IC_ENABLE_TX_CMD_BLOCK
6851  *
6852  * Tx Command execution blocked
6853  */
6854 #define ALT_I2C_IC_ENABLE_TX_CMD_BLOCK_E_BLOCKED 0x1
6855 
6856 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_ENABLE_TX_CMD_BLOCK register field. */
6857 #define ALT_I2C_IC_ENABLE_TX_CMD_BLOCK_LSB 2
6858 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_ENABLE_TX_CMD_BLOCK register field. */
6859 #define ALT_I2C_IC_ENABLE_TX_CMD_BLOCK_MSB 2
6860 /* The width in bits of the ALT_I2C_IC_ENABLE_TX_CMD_BLOCK register field. */
6861 #define ALT_I2C_IC_ENABLE_TX_CMD_BLOCK_WIDTH 1
6862 /* The mask used to set the ALT_I2C_IC_ENABLE_TX_CMD_BLOCK register field value. */
6863 #define ALT_I2C_IC_ENABLE_TX_CMD_BLOCK_SET_MSK 0x00000004
6864 /* The mask used to clear the ALT_I2C_IC_ENABLE_TX_CMD_BLOCK register field value. */
6865 #define ALT_I2C_IC_ENABLE_TX_CMD_BLOCK_CLR_MSK 0xfffffffb
6866 /* The reset value of the ALT_I2C_IC_ENABLE_TX_CMD_BLOCK register field. */
6867 #define ALT_I2C_IC_ENABLE_TX_CMD_BLOCK_RESET 0x0
6868 /* Extracts the ALT_I2C_IC_ENABLE_TX_CMD_BLOCK field value from a register. */
6869 #define ALT_I2C_IC_ENABLE_TX_CMD_BLOCK_GET(value) (((value) & 0x00000004) >> 2)
6870 /* Produces a ALT_I2C_IC_ENABLE_TX_CMD_BLOCK register field value suitable for setting the register. */
6871 #define ALT_I2C_IC_ENABLE_TX_CMD_BLOCK_SET(value) (((value) << 2) & 0x00000004)
6872 
6873 /*
6874  * Field : RSVD_SDA_STUCK_RECOVERY_ENABLE
6875  *
6876  * Reserved bits - Read Only
6877  *
6878  * Field Access Macros:
6879  *
6880  */
6881 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE register field. */
6882 #define ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE_LSB 3
6883 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE register field. */
6884 #define ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE_MSB 3
6885 /* The width in bits of the ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE register field. */
6886 #define ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE_WIDTH 1
6887 /* The mask used to set the ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE register field value. */
6888 #define ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE_SET_MSK 0x00000008
6889 /* The mask used to clear the ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE register field value. */
6890 #define ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE_CLR_MSK 0xfffffff7
6891 /* The reset value of the ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE register field. */
6892 #define ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE_RESET 0x0
6893 /* Extracts the ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE field value from a register. */
6894 #define ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE_GET(value) (((value) & 0x00000008) >> 3)
6895 /* Produces a ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE register field value suitable for setting the register. */
6896 #define ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE_SET(value) (((value) << 3) & 0x00000008)
6897 
6898 /*
6899  * Field : RSVD_IC_ENABLE_1
6900  *
6901  * Reserved bits - Read Only
6902  *
6903  * Field Access Macros:
6904  *
6905  */
6906 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1 register field. */
6907 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1_LSB 4
6908 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1 register field. */
6909 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1_MSB 15
6910 /* The width in bits of the ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1 register field. */
6911 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1_WIDTH 12
6912 /* The mask used to set the ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1 register field value. */
6913 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1_SET_MSK 0x0000fff0
6914 /* The mask used to clear the ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1 register field value. */
6915 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1_CLR_MSK 0xffff000f
6916 /* The reset value of the ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1 register field. */
6917 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1_RESET 0x0
6918 /* Extracts the ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1 field value from a register. */
6919 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1_GET(value) (((value) & 0x0000fff0) >> 4)
6920 /* Produces a ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1 register field value suitable for setting the register. */
6921 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1_SET(value) (((value) << 4) & 0x0000fff0)
6922 
6923 /*
6924  * Field : RSVD_SMBUS_CLK_RESET
6925  *
6926  * Reserved bits - Read Only
6927  *
6928  * Field Access Macros:
6929  *
6930  */
6931 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET register field. */
6932 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET_LSB 16
6933 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET register field. */
6934 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET_MSB 16
6935 /* The width in bits of the ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET register field. */
6936 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET_WIDTH 1
6937 /* The mask used to set the ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET register field value. */
6938 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET_SET_MSK 0x00010000
6939 /* The mask used to clear the ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET register field value. */
6940 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET_CLR_MSK 0xfffeffff
6941 /* The reset value of the ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET register field. */
6942 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET_RESET 0x0
6943 /* Extracts the ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET field value from a register. */
6944 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET_GET(value) (((value) & 0x00010000) >> 16)
6945 /* Produces a ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET register field value suitable for setting the register. */
6946 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET_SET(value) (((value) << 16) & 0x00010000)
6947 
6948 /*
6949  * Field : RSVD_SMBUS_SUSPEND_EN
6950  *
6951  * Reserved bits - Read Only
6952  *
6953  * Field Access Macros:
6954  *
6955  */
6956 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN register field. */
6957 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN_LSB 17
6958 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN register field. */
6959 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN_MSB 17
6960 /* The width in bits of the ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN register field. */
6961 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN_WIDTH 1
6962 /* The mask used to set the ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN register field value. */
6963 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN_SET_MSK 0x00020000
6964 /* The mask used to clear the ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN register field value. */
6965 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN_CLR_MSK 0xfffdffff
6966 /* The reset value of the ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN register field. */
6967 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN_RESET 0x0
6968 /* Extracts the ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN field value from a register. */
6969 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN_GET(value) (((value) & 0x00020000) >> 17)
6970 /* Produces a ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN register field value suitable for setting the register. */
6971 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN_SET(value) (((value) << 17) & 0x00020000)
6972 
6973 /*
6974  * Field : RSVD_SMBUS_ALERT_EN
6975  *
6976  * Reserved bits - Read Only
6977  *
6978  * Field Access Macros:
6979  *
6980  */
6981 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN register field. */
6982 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN_LSB 18
6983 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN register field. */
6984 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN_MSB 18
6985 /* The width in bits of the ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN register field. */
6986 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN_WIDTH 1
6987 /* The mask used to set the ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN register field value. */
6988 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN_SET_MSK 0x00040000
6989 /* The mask used to clear the ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN register field value. */
6990 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN_CLR_MSK 0xfffbffff
6991 /* The reset value of the ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN register field. */
6992 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN_RESET 0x0
6993 /* Extracts the ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN field value from a register. */
6994 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN_GET(value) (((value) & 0x00040000) >> 18)
6995 /* Produces a ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN register field value suitable for setting the register. */
6996 #define ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN_SET(value) (((value) << 18) & 0x00040000)
6997 
6998 /*
6999  * Field : RSVD_IC_ENABLE_2
7000  *
7001  * Reserved bits - Read Only
7002  *
7003  * Field Access Macros:
7004  *
7005  */
7006 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2 register field. */
7007 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2_LSB 19
7008 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2 register field. */
7009 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2_MSB 31
7010 /* The width in bits of the ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2 register field. */
7011 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2_WIDTH 13
7012 /* The mask used to set the ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2 register field value. */
7013 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2_SET_MSK 0xfff80000
7014 /* The mask used to clear the ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2 register field value. */
7015 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2_CLR_MSK 0x0007ffff
7016 /* The reset value of the ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2 register field. */
7017 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2_RESET 0x0
7018 /* Extracts the ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2 field value from a register. */
7019 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2_GET(value) (((value) & 0xfff80000) >> 19)
7020 /* Produces a ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2 register field value suitable for setting the register. */
7021 #define ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2_SET(value) (((value) << 19) & 0xfff80000)
7022 
7023 #ifndef __ASSEMBLY__
7024 /*
7025  * WARNING: The C register and register group struct declarations are provided for
7026  * convenience and illustrative purposes. They should, however, be used with
7027  * caution as the C language standard provides no guarantees about the alignment or
7028  * atomicity of device memory accesses. The recommended practice for coding device
7029  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7030  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7031  * alt_write_dword() functions for 64 bit registers.
7032  *
7033  * The struct declaration for register ALT_I2C_IC_ENABLE.
7034  */
7035 struct ALT_I2C_IC_ENABLE_s
7036 {
7037  volatile uint32_t ENABLE : 1; /* ALT_I2C_IC_ENABLE_ENABLE */
7038  volatile uint32_t ABORT : 1; /* ALT_I2C_IC_ENABLE_ABORT */
7039  volatile uint32_t TX_CMD_BLOCK : 1; /* ALT_I2C_IC_ENABLE_TX_CMD_BLOCK */
7040  const volatile uint32_t RSVD_SDA_STUCK_RECOVERY_ENABLE : 1; /* ALT_I2C_IC_ENABLE_RSVD_SDA_STUCK_RECOVERY_ENABLE */
7041  const volatile uint32_t RSVD_IC_ENABLE_1 : 12; /* ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_1 */
7042  const volatile uint32_t RSVD_SMBUS_CLK_RESET : 1; /* ALT_I2C_IC_ENABLE_RSVD_SMBUS_CLK_RESET */
7043  const volatile uint32_t RSVD_SMBUS_SUSPEND_EN : 1; /* ALT_I2C_IC_ENABLE_RSVD_SMBUS_SUSPEND_EN */
7044  const volatile uint32_t RSVD_SMBUS_ALERT_EN : 1; /* ALT_I2C_IC_ENABLE_RSVD_SMBUS_ALERT_EN */
7045  const volatile uint32_t RSVD_IC_ENABLE_2 : 13; /* ALT_I2C_IC_ENABLE_RSVD_IC_ENABLE_2 */
7046 };
7047 
7048 /* The typedef declaration for register ALT_I2C_IC_ENABLE. */
7049 typedef struct ALT_I2C_IC_ENABLE_s ALT_I2C_IC_ENABLE_t;
7050 #endif /* __ASSEMBLY__ */
7051 
7052 /* The reset value of the ALT_I2C_IC_ENABLE register. */
7053 #define ALT_I2C_IC_ENABLE_RESET 0x00000000
7054 /* The byte offset of the ALT_I2C_IC_ENABLE register from the beginning of the component. */
7055 #define ALT_I2C_IC_ENABLE_OFST 0x6c
7056 /* The address of the ALT_I2C_IC_ENABLE register. */
7057 #define ALT_I2C_IC_ENABLE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_ENABLE_OFST))
7058 
7059 /*
7060  * Register : I2C STATUS Register - IC_STATUS
7061  *
7062  * Name: I2C Status Register
7063  *
7064  * Size: 21 bits
7065  *
7066  * Address Offset: 0x70
7067  *
7068  * Read/Write Access: Read
7069  *
7070  * This is a read-only register used to indicate the current
7071  *
7072  * transfer status and FIFO status. The status register may be
7073  *
7074  * read at any time. None of the bits in this register request
7075  *
7076  * an interrupt.
7077  *
7078  * When the I2C is disabled by writing 0 in bit 0 of the
7079  *
7080  * IC_ENABLE register:
7081  *
7082  * * Bits 1 and 2 are set to 1
7083  *
7084  * * Bits 3 and 10 are set to 0
7085  *
7086  * When the master or slave state machines goes to idle
7087  *
7088  * and ic_en=0:
7089  *
7090  * * Bits 5 and 6 are set to 0
7091  *
7092  * Register Layout
7093  *
7094  * Bits | Access | Reset | Description
7095  * :--------|:-------|:------|:-------------------------------------------------
7096  * [0] | R | 0x0 | ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY
7097  * [1] | R | 0x1 | ALT_I2C_IC_STATUS_TFNF
7098  * [2] | R | 0x1 | ALT_I2C_IC_STATUS_TFE
7099  * [3] | R | 0x0 | ALT_I2C_IC_STATUS_RFNE
7100  * [4] | R | 0x0 | ALT_I2C_IC_STATUS_RFF
7101  * [5] | R | 0x0 | ALT_I2C_IC_STATUS_MST_ACTIVITY
7102  * [6] | R | 0x0 | ALT_I2C_IC_STATUS_SLV_ACTIVITY
7103  * [7] | R | 0x0 | ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY
7104  * [8] | R | 0x0 | ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL
7105  * [9] | R | 0x0 | ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY
7106  * [10] | R | 0x0 | ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL
7107  * [11] | R | 0x0 | ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED
7108  * [15:12] | R | 0x0 | ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1
7109  * [16] | R | 0x0 | ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT
7110  * [17] | R | 0x0 | ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID
7111  * [18] | R | 0x0 | ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED
7112  * [19] | R | 0x0 | ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS
7113  * [20] | R | 0x0 | ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS
7114  * [31:21] | R | 0x0 | ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2
7115  *
7116  */
7117 /*
7118  * Field : IC_STATUS_ACTIVITY
7119  *
7120  * I2C Activity Status.
7121  *
7122  * Reset value: 0x0
7123  *
7124  * Field Enumeration Values:
7125  *
7126  * Enum | Value | Description
7127  * :------------------------------------------------|:------|:--------------
7128  * ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY_E_INACTIVE | 0x0 | I2C is idle
7129  * ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY_E_ACTIVE | 0x1 | I2C is active
7130  *
7131  * Field Access Macros:
7132  *
7133  */
7134 /*
7135  * Enumerated value for register field ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY
7136  *
7137  * I2C is idle
7138  */
7139 #define ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY_E_INACTIVE 0x0
7140 /*
7141  * Enumerated value for register field ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY
7142  *
7143  * I2C is active
7144  */
7145 #define ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY_E_ACTIVE 0x1
7146 
7147 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY register field. */
7148 #define ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY_LSB 0
7149 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY register field. */
7150 #define ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY_MSB 0
7151 /* The width in bits of the ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY register field. */
7152 #define ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY_WIDTH 1
7153 /* The mask used to set the ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY register field value. */
7154 #define ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY_SET_MSK 0x00000001
7155 /* The mask used to clear the ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY register field value. */
7156 #define ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY_CLR_MSK 0xfffffffe
7157 /* The reset value of the ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY register field. */
7158 #define ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY_RESET 0x0
7159 /* Extracts the ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY field value from a register. */
7160 #define ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0)
7161 /* Produces a ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY register field value suitable for setting the register. */
7162 #define ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY_SET(value) (((value) << 0) & 0x00000001)
7163 
7164 /*
7165  * Field : TFNF
7166  *
7167  * Transmit FIFO Not Full.
7168  *
7169  * Set when the transmit FIFO contains one or more
7170  *
7171  * empty locations, and is cleared when the FIFO is full.
7172  *
7173  * 0: Transmit FIFO is full
7174  *
7175  * 1: Transmit FIFO is not full
7176  *
7177  * Reset value: 0x1
7178  *
7179  * Field Enumeration Values:
7180  *
7181  * Enum | Value | Description
7182  * :----------------------------------|:------|:-----------------
7183  * ALT_I2C_IC_STATUS_TFNF_E_FULL | 0x0 | Tx FIFO is full
7184  * ALT_I2C_IC_STATUS_TFNF_E_NOT_FULL | 0x1 | Tx FIFO not full
7185  *
7186  * Field Access Macros:
7187  *
7188  */
7189 /*
7190  * Enumerated value for register field ALT_I2C_IC_STATUS_TFNF
7191  *
7192  * Tx FIFO is full
7193  */
7194 #define ALT_I2C_IC_STATUS_TFNF_E_FULL 0x0
7195 /*
7196  * Enumerated value for register field ALT_I2C_IC_STATUS_TFNF
7197  *
7198  * Tx FIFO not full
7199  */
7200 #define ALT_I2C_IC_STATUS_TFNF_E_NOT_FULL 0x1
7201 
7202 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_STATUS_TFNF register field. */
7203 #define ALT_I2C_IC_STATUS_TFNF_LSB 1
7204 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_STATUS_TFNF register field. */
7205 #define ALT_I2C_IC_STATUS_TFNF_MSB 1
7206 /* The width in bits of the ALT_I2C_IC_STATUS_TFNF register field. */
7207 #define ALT_I2C_IC_STATUS_TFNF_WIDTH 1
7208 /* The mask used to set the ALT_I2C_IC_STATUS_TFNF register field value. */
7209 #define ALT_I2C_IC_STATUS_TFNF_SET_MSK 0x00000002
7210 /* The mask used to clear the ALT_I2C_IC_STATUS_TFNF register field value. */
7211 #define ALT_I2C_IC_STATUS_TFNF_CLR_MSK 0xfffffffd
7212 /* The reset value of the ALT_I2C_IC_STATUS_TFNF register field. */
7213 #define ALT_I2C_IC_STATUS_TFNF_RESET 0x1
7214 /* Extracts the ALT_I2C_IC_STATUS_TFNF field value from a register. */
7215 #define ALT_I2C_IC_STATUS_TFNF_GET(value) (((value) & 0x00000002) >> 1)
7216 /* Produces a ALT_I2C_IC_STATUS_TFNF register field value suitable for setting the register. */
7217 #define ALT_I2C_IC_STATUS_TFNF_SET(value) (((value) << 1) & 0x00000002)
7218 
7219 /*
7220  * Field : TFE
7221  *
7222  * Transmit FIFO Completely Empty.
7223  *
7224  * When the transmit FIFO is completely empty, this bit is set.
7225  *
7226  * When it contains one or more valid entries, this bit is
7227  *
7228  * cleared. This bit field does not request an interrupt.
7229  *
7230  * 0: Transmit FIFO is not empty
7231  *
7232  * 1: Transmit FIFO is empty
7233  *
7234  * Reset value: 0x1
7235  *
7236  * Field Enumeration Values:
7237  *
7238  * Enum | Value | Description
7239  * :----------------------------------|:------|:------------------
7240  * ALT_I2C_IC_STATUS_TFE_E_NON_EMPTY | 0x0 | Tx FIFO not empty
7241  * ALT_I2C_IC_STATUS_TFE_E_EMPTY | 0x1 | Tx FIFO is empty
7242  *
7243  * Field Access Macros:
7244  *
7245  */
7246 /*
7247  * Enumerated value for register field ALT_I2C_IC_STATUS_TFE
7248  *
7249  * Tx FIFO not empty
7250  */
7251 #define ALT_I2C_IC_STATUS_TFE_E_NON_EMPTY 0x0
7252 /*
7253  * Enumerated value for register field ALT_I2C_IC_STATUS_TFE
7254  *
7255  * Tx FIFO is empty
7256  */
7257 #define ALT_I2C_IC_STATUS_TFE_E_EMPTY 0x1
7258 
7259 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_STATUS_TFE register field. */
7260 #define ALT_I2C_IC_STATUS_TFE_LSB 2
7261 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_STATUS_TFE register field. */
7262 #define ALT_I2C_IC_STATUS_TFE_MSB 2
7263 /* The width in bits of the ALT_I2C_IC_STATUS_TFE register field. */
7264 #define ALT_I2C_IC_STATUS_TFE_WIDTH 1
7265 /* The mask used to set the ALT_I2C_IC_STATUS_TFE register field value. */
7266 #define ALT_I2C_IC_STATUS_TFE_SET_MSK 0x00000004
7267 /* The mask used to clear the ALT_I2C_IC_STATUS_TFE register field value. */
7268 #define ALT_I2C_IC_STATUS_TFE_CLR_MSK 0xfffffffb
7269 /* The reset value of the ALT_I2C_IC_STATUS_TFE register field. */
7270 #define ALT_I2C_IC_STATUS_TFE_RESET 0x1
7271 /* Extracts the ALT_I2C_IC_STATUS_TFE field value from a register. */
7272 #define ALT_I2C_IC_STATUS_TFE_GET(value) (((value) & 0x00000004) >> 2)
7273 /* Produces a ALT_I2C_IC_STATUS_TFE register field value suitable for setting the register. */
7274 #define ALT_I2C_IC_STATUS_TFE_SET(value) (((value) << 2) & 0x00000004)
7275 
7276 /*
7277  * Field : RFNE
7278  *
7279  * Receive FIFO Not Empty.
7280  *
7281  * This bit is set when the receive FIFO contains one or
7282  *
7283  * more entries; it is cleared when the receive FIFO is empty.
7284  *
7285  * 0: Receive FIFO is empty
7286  *
7287  * 1: Receive FIFO is not empty
7288  *
7289  * Reset value: 0x0
7290  *
7291  * Field Enumeration Values:
7292  *
7293  * Enum | Value | Description
7294  * :-----------------------------------|:------|:------------------
7295  * ALT_I2C_IC_STATUS_RFNE_E_EMPTY | 0x0 | Rx FIFO is empty
7296  * ALT_I2C_IC_STATUS_RFNE_E_NOT_EMPTY | 0x1 | Rx FIFO not empty
7297  *
7298  * Field Access Macros:
7299  *
7300  */
7301 /*
7302  * Enumerated value for register field ALT_I2C_IC_STATUS_RFNE
7303  *
7304  * Rx FIFO is empty
7305  */
7306 #define ALT_I2C_IC_STATUS_RFNE_E_EMPTY 0x0
7307 /*
7308  * Enumerated value for register field ALT_I2C_IC_STATUS_RFNE
7309  *
7310  * Rx FIFO not empty
7311  */
7312 #define ALT_I2C_IC_STATUS_RFNE_E_NOT_EMPTY 0x1
7313 
7314 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_STATUS_RFNE register field. */
7315 #define ALT_I2C_IC_STATUS_RFNE_LSB 3
7316 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_STATUS_RFNE register field. */
7317 #define ALT_I2C_IC_STATUS_RFNE_MSB 3
7318 /* The width in bits of the ALT_I2C_IC_STATUS_RFNE register field. */
7319 #define ALT_I2C_IC_STATUS_RFNE_WIDTH 1
7320 /* The mask used to set the ALT_I2C_IC_STATUS_RFNE register field value. */
7321 #define ALT_I2C_IC_STATUS_RFNE_SET_MSK 0x00000008
7322 /* The mask used to clear the ALT_I2C_IC_STATUS_RFNE register field value. */
7323 #define ALT_I2C_IC_STATUS_RFNE_CLR_MSK 0xfffffff7
7324 /* The reset value of the ALT_I2C_IC_STATUS_RFNE register field. */
7325 #define ALT_I2C_IC_STATUS_RFNE_RESET 0x0
7326 /* Extracts the ALT_I2C_IC_STATUS_RFNE field value from a register. */
7327 #define ALT_I2C_IC_STATUS_RFNE_GET(value) (((value) & 0x00000008) >> 3)
7328 /* Produces a ALT_I2C_IC_STATUS_RFNE register field value suitable for setting the register. */
7329 #define ALT_I2C_IC_STATUS_RFNE_SET(value) (((value) << 3) & 0x00000008)
7330 
7331 /*
7332  * Field : RFF
7333  *
7334  * Receive FIFO Completely Full.
7335  *
7336  * When the receive FIFO is completely full, this
7337  *
7338  * bit is set. When the receive FIFO contains one
7339  *
7340  * or more empty location, this bit is cleared.
7341  *
7342  * 0: Receive FIFO is not full
7343  *
7344  * 1: Receive FIFO is full
7345  *
7346  * Reset value: 0x0
7347  *
7348  * Field Enumeration Values:
7349  *
7350  * Enum | Value | Description
7351  * :---------------------------------|:------|:-----------------
7352  * ALT_I2C_IC_STATUS_RFF_E_NOT_FULL | 0x0 | Rx FIFO not full
7353  * ALT_I2C_IC_STATUS_RFF_E_FULL | 0x1 | Rx FIFO is full
7354  *
7355  * Field Access Macros:
7356  *
7357  */
7358 /*
7359  * Enumerated value for register field ALT_I2C_IC_STATUS_RFF
7360  *
7361  * Rx FIFO not full
7362  */
7363 #define ALT_I2C_IC_STATUS_RFF_E_NOT_FULL 0x0
7364 /*
7365  * Enumerated value for register field ALT_I2C_IC_STATUS_RFF
7366  *
7367  * Rx FIFO is full
7368  */
7369 #define ALT_I2C_IC_STATUS_RFF_E_FULL 0x1
7370 
7371 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_STATUS_RFF register field. */
7372 #define ALT_I2C_IC_STATUS_RFF_LSB 4
7373 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_STATUS_RFF register field. */
7374 #define ALT_I2C_IC_STATUS_RFF_MSB 4
7375 /* The width in bits of the ALT_I2C_IC_STATUS_RFF register field. */
7376 #define ALT_I2C_IC_STATUS_RFF_WIDTH 1
7377 /* The mask used to set the ALT_I2C_IC_STATUS_RFF register field value. */
7378 #define ALT_I2C_IC_STATUS_RFF_SET_MSK 0x00000010
7379 /* The mask used to clear the ALT_I2C_IC_STATUS_RFF register field value. */
7380 #define ALT_I2C_IC_STATUS_RFF_CLR_MSK 0xffffffef
7381 /* The reset value of the ALT_I2C_IC_STATUS_RFF register field. */
7382 #define ALT_I2C_IC_STATUS_RFF_RESET 0x0
7383 /* Extracts the ALT_I2C_IC_STATUS_RFF field value from a register. */
7384 #define ALT_I2C_IC_STATUS_RFF_GET(value) (((value) & 0x00000010) >> 4)
7385 /* Produces a ALT_I2C_IC_STATUS_RFF register field value suitable for setting the register. */
7386 #define ALT_I2C_IC_STATUS_RFF_SET(value) (((value) << 4) & 0x00000010)
7387 
7388 /*
7389  * Field : MST_ACTIVITY
7390  *
7391  * Master FSM Activity Status.
7392  *
7393  * When the Master Finite State Machine (FSM) is
7394  *
7395  * not in the IDLE state, this bit is set.
7396  *
7397  * 0: Master FSM is in IDLE state so the Master part
7398  *
7399  * of DW_apb_i2c is not Active
7400  *
7401  * 1: Master FSM is not in IDLE state so the Master
7402  *
7403  * part of DW_apb_i2c is Active
7404  *
7405  * Note
7406  *
7407  * IC_STATUS[0]-that is, ACTIVITY bit-is the OR of
7408  *
7409  * SLV_ACTIVITY and MST_ACTIVITY bits.
7410  *
7411  * Reset value: 0x0
7412  *
7413  * Field Enumeration Values:
7414  *
7415  * Enum | Value | Description
7416  * :----------------------------------------|:------|:----------------
7417  * ALT_I2C_IC_STATUS_MST_ACTIVITY_E_IDLE | 0x0 | Master is idle
7418  * ALT_I2C_IC_STATUS_MST_ACTIVITY_E_ACTIVE | 0x1 | Master not idle
7419  *
7420  * Field Access Macros:
7421  *
7422  */
7423 /*
7424  * Enumerated value for register field ALT_I2C_IC_STATUS_MST_ACTIVITY
7425  *
7426  * Master is idle
7427  */
7428 #define ALT_I2C_IC_STATUS_MST_ACTIVITY_E_IDLE 0x0
7429 /*
7430  * Enumerated value for register field ALT_I2C_IC_STATUS_MST_ACTIVITY
7431  *
7432  * Master not idle
7433  */
7434 #define ALT_I2C_IC_STATUS_MST_ACTIVITY_E_ACTIVE 0x1
7435 
7436 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_STATUS_MST_ACTIVITY register field. */
7437 #define ALT_I2C_IC_STATUS_MST_ACTIVITY_LSB 5
7438 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_STATUS_MST_ACTIVITY register field. */
7439 #define ALT_I2C_IC_STATUS_MST_ACTIVITY_MSB 5
7440 /* The width in bits of the ALT_I2C_IC_STATUS_MST_ACTIVITY register field. */
7441 #define ALT_I2C_IC_STATUS_MST_ACTIVITY_WIDTH 1
7442 /* The mask used to set the ALT_I2C_IC_STATUS_MST_ACTIVITY register field value. */
7443 #define ALT_I2C_IC_STATUS_MST_ACTIVITY_SET_MSK 0x00000020
7444 /* The mask used to clear the ALT_I2C_IC_STATUS_MST_ACTIVITY register field value. */
7445 #define ALT_I2C_IC_STATUS_MST_ACTIVITY_CLR_MSK 0xffffffdf
7446 /* The reset value of the ALT_I2C_IC_STATUS_MST_ACTIVITY register field. */
7447 #define ALT_I2C_IC_STATUS_MST_ACTIVITY_RESET 0x0
7448 /* Extracts the ALT_I2C_IC_STATUS_MST_ACTIVITY field value from a register. */
7449 #define ALT_I2C_IC_STATUS_MST_ACTIVITY_GET(value) (((value) & 0x00000020) >> 5)
7450 /* Produces a ALT_I2C_IC_STATUS_MST_ACTIVITY register field value suitable for setting the register. */
7451 #define ALT_I2C_IC_STATUS_MST_ACTIVITY_SET(value) (((value) << 5) & 0x00000020)
7452 
7453 /*
7454  * Field : SLV_ACTIVITY
7455  *
7456  * Slave FSM Activity Status.
7457  *
7458  * When the Slave Finite State Machine (FSM) is not
7459  *
7460  * in the IDLE state, this bit is set.
7461  *
7462  * 0: Slave FSM is in IDLE state so the Slave part of
7463  *
7464  * DW_apb_i2c is not Active
7465  *
7466  * 1: Slave FSM is not in IDLE state so the Slave part
7467  *
7468  * of DW_apb_i2c is Active
7469  *
7470  * Reset value: 0x0
7471  *
7472  * Field Enumeration Values:
7473  *
7474  * Enum | Value | Description
7475  * :----------------------------------------|:------|:---------------
7476  * ALT_I2C_IC_STATUS_SLV_ACTIVITY_E_IDLE | 0x0 | Slave is idle
7477  * ALT_I2C_IC_STATUS_SLV_ACTIVITY_E_ACTIVE | 0x1 | Slave not idle
7478  *
7479  * Field Access Macros:
7480  *
7481  */
7482 /*
7483  * Enumerated value for register field ALT_I2C_IC_STATUS_SLV_ACTIVITY
7484  *
7485  * Slave is idle
7486  */
7487 #define ALT_I2C_IC_STATUS_SLV_ACTIVITY_E_IDLE 0x0
7488 /*
7489  * Enumerated value for register field ALT_I2C_IC_STATUS_SLV_ACTIVITY
7490  *
7491  * Slave not idle
7492  */
7493 #define ALT_I2C_IC_STATUS_SLV_ACTIVITY_E_ACTIVE 0x1
7494 
7495 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_STATUS_SLV_ACTIVITY register field. */
7496 #define ALT_I2C_IC_STATUS_SLV_ACTIVITY_LSB 6
7497 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_STATUS_SLV_ACTIVITY register field. */
7498 #define ALT_I2C_IC_STATUS_SLV_ACTIVITY_MSB 6
7499 /* The width in bits of the ALT_I2C_IC_STATUS_SLV_ACTIVITY register field. */
7500 #define ALT_I2C_IC_STATUS_SLV_ACTIVITY_WIDTH 1
7501 /* The mask used to set the ALT_I2C_IC_STATUS_SLV_ACTIVITY register field value. */
7502 #define ALT_I2C_IC_STATUS_SLV_ACTIVITY_SET_MSK 0x00000040
7503 /* The mask used to clear the ALT_I2C_IC_STATUS_SLV_ACTIVITY register field value. */
7504 #define ALT_I2C_IC_STATUS_SLV_ACTIVITY_CLR_MSK 0xffffffbf
7505 /* The reset value of the ALT_I2C_IC_STATUS_SLV_ACTIVITY register field. */
7506 #define ALT_I2C_IC_STATUS_SLV_ACTIVITY_RESET 0x0
7507 /* Extracts the ALT_I2C_IC_STATUS_SLV_ACTIVITY field value from a register. */
7508 #define ALT_I2C_IC_STATUS_SLV_ACTIVITY_GET(value) (((value) & 0x00000040) >> 6)
7509 /* Produces a ALT_I2C_IC_STATUS_SLV_ACTIVITY register field value suitable for setting the register. */
7510 #define ALT_I2C_IC_STATUS_SLV_ACTIVITY_SET(value) (((value) << 6) & 0x00000040)
7511 
7512 /*
7513  * Field : RSVD_MST_HOLD_TX_FIFO_EMPTY
7514  *
7515  * Reserved bits - Read Only
7516  *
7517  * Field Access Macros:
7518  *
7519  */
7520 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY register field. */
7521 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY_LSB 7
7522 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY register field. */
7523 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY_MSB 7
7524 /* The width in bits of the ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY register field. */
7525 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY_WIDTH 1
7526 /* The mask used to set the ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY register field value. */
7527 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY_SET_MSK 0x00000080
7528 /* The mask used to clear the ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY register field value. */
7529 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY_CLR_MSK 0xffffff7f
7530 /* The reset value of the ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY register field. */
7531 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY_RESET 0x0
7532 /* Extracts the ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY field value from a register. */
7533 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY_GET(value) (((value) & 0x00000080) >> 7)
7534 /* Produces a ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY register field value suitable for setting the register. */
7535 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY_SET(value) (((value) << 7) & 0x00000080)
7536 
7537 /*
7538  * Field : RSVD_MST_HOLD_RX_FIFO_FULL
7539  *
7540  * Reserved bits - Read Only
7541  *
7542  * Field Access Macros:
7543  *
7544  */
7545 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL register field. */
7546 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL_LSB 8
7547 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL register field. */
7548 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL_MSB 8
7549 /* The width in bits of the ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL register field. */
7550 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL_WIDTH 1
7551 /* The mask used to set the ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL register field value. */
7552 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL_SET_MSK 0x00000100
7553 /* The mask used to clear the ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL register field value. */
7554 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL_CLR_MSK 0xfffffeff
7555 /* The reset value of the ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL register field. */
7556 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL_RESET 0x0
7557 /* Extracts the ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL field value from a register. */
7558 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL_GET(value) (((value) & 0x00000100) >> 8)
7559 /* Produces a ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL register field value suitable for setting the register. */
7560 #define ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL_SET(value) (((value) << 8) & 0x00000100)
7561 
7562 /*
7563  * Field : RSVD_SLV_HOLD_TX_FIFO_EMPTY
7564  *
7565  * Reserved bits - Read Only
7566  *
7567  * Field Access Macros:
7568  *
7569  */
7570 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY register field. */
7571 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY_LSB 9
7572 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY register field. */
7573 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY_MSB 9
7574 /* The width in bits of the ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY register field. */
7575 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY_WIDTH 1
7576 /* The mask used to set the ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY register field value. */
7577 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY_SET_MSK 0x00000200
7578 /* The mask used to clear the ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY register field value. */
7579 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY_CLR_MSK 0xfffffdff
7580 /* The reset value of the ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY register field. */
7581 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY_RESET 0x0
7582 /* Extracts the ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY field value from a register. */
7583 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY_GET(value) (((value) & 0x00000200) >> 9)
7584 /* Produces a ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY register field value suitable for setting the register. */
7585 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY_SET(value) (((value) << 9) & 0x00000200)
7586 
7587 /*
7588  * Field : RSVD_SLV_HOLD_RX_FIFO_FULL
7589  *
7590  * Reserved bits - Read Only
7591  *
7592  * Field Access Macros:
7593  *
7594  */
7595 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL register field. */
7596 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL_LSB 10
7597 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL register field. */
7598 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL_MSB 10
7599 /* The width in bits of the ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL register field. */
7600 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL_WIDTH 1
7601 /* The mask used to set the ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL register field value. */
7602 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL_SET_MSK 0x00000400
7603 /* The mask used to clear the ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL register field value. */
7604 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL_CLR_MSK 0xfffffbff
7605 /* The reset value of the ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL register field. */
7606 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL_RESET 0x0
7607 /* Extracts the ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL field value from a register. */
7608 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL_GET(value) (((value) & 0x00000400) >> 10)
7609 /* Produces a ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL register field value suitable for setting the register. */
7610 #define ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL_SET(value) (((value) << 10) & 0x00000400)
7611 
7612 /*
7613  * Field : RSVD_SDA_STUCK_NOT_RECOVERED
7614  *
7615  * Reserved bits - Read Only
7616  *
7617  * Field Access Macros:
7618  *
7619  */
7620 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED register field. */
7621 #define ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED_LSB 11
7622 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED register field. */
7623 #define ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED_MSB 11
7624 /* The width in bits of the ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED register field. */
7625 #define ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED_WIDTH 1
7626 /* The mask used to set the ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED register field value. */
7627 #define ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED_SET_MSK 0x00000800
7628 /* The mask used to clear the ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED register field value. */
7629 #define ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED_CLR_MSK 0xfffff7ff
7630 /* The reset value of the ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED register field. */
7631 #define ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED_RESET 0x0
7632 /* Extracts the ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED field value from a register. */
7633 #define ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED_GET(value) (((value) & 0x00000800) >> 11)
7634 /* Produces a ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED register field value suitable for setting the register. */
7635 #define ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED_SET(value) (((value) << 11) & 0x00000800)
7636 
7637 /*
7638  * Field : RSVD_IC_STATUS_1
7639  *
7640  * Reserved bits - Read Only
7641  *
7642  * Field Access Macros:
7643  *
7644  */
7645 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1 register field. */
7646 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1_LSB 12
7647 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1 register field. */
7648 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1_MSB 15
7649 /* The width in bits of the ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1 register field. */
7650 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1_WIDTH 4
7651 /* The mask used to set the ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1 register field value. */
7652 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1_SET_MSK 0x0000f000
7653 /* The mask used to clear the ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1 register field value. */
7654 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1_CLR_MSK 0xffff0fff
7655 /* The reset value of the ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1 register field. */
7656 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1_RESET 0x0
7657 /* Extracts the ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1 field value from a register. */
7658 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1_GET(value) (((value) & 0x0000f000) >> 12)
7659 /* Produces a ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1 register field value suitable for setting the register. */
7660 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1_SET(value) (((value) << 12) & 0x0000f000)
7661 
7662 /*
7663  * Field : RSVD_SMBUS_QUICK_CMD_BIT
7664  *
7665  * Reserved bits - Read Only
7666  *
7667  * Field Access Macros:
7668  *
7669  */
7670 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT register field. */
7671 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT_LSB 16
7672 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT register field. */
7673 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT_MSB 16
7674 /* The width in bits of the ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT register field. */
7675 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT_WIDTH 1
7676 /* The mask used to set the ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT register field value. */
7677 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT_SET_MSK 0x00010000
7678 /* The mask used to clear the ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT register field value. */
7679 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT_CLR_MSK 0xfffeffff
7680 /* The reset value of the ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT register field. */
7681 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT_RESET 0x0
7682 /* Extracts the ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT field value from a register. */
7683 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT_GET(value) (((value) & 0x00010000) >> 16)
7684 /* Produces a ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT register field value suitable for setting the register. */
7685 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT_SET(value) (((value) << 16) & 0x00010000)
7686 
7687 /*
7688  * Field : RSVD_SMBUS_SLAVE_ADDR_VALID
7689  *
7690  * Reserved bits - Read Only
7691  *
7692  * Field Access Macros:
7693  *
7694  */
7695 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID register field. */
7696 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID_LSB 17
7697 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID register field. */
7698 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID_MSB 17
7699 /* The width in bits of the ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID register field. */
7700 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID_WIDTH 1
7701 /* The mask used to set the ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID register field value. */
7702 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID_SET_MSK 0x00020000
7703 /* The mask used to clear the ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID register field value. */
7704 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID_CLR_MSK 0xfffdffff
7705 /* The reset value of the ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID register field. */
7706 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID_RESET 0x0
7707 /* Extracts the ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID field value from a register. */
7708 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID_GET(value) (((value) & 0x00020000) >> 17)
7709 /* Produces a ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID register field value suitable for setting the register. */
7710 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID_SET(value) (((value) << 17) & 0x00020000)
7711 
7712 /*
7713  * Field : RSVD_SMBUS_SLAVE_ADDR_RESOLVED
7714  *
7715  * Reserved bits - Read Only
7716  *
7717  * Field Access Macros:
7718  *
7719  */
7720 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED register field. */
7721 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED_LSB 18
7722 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED register field. */
7723 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED_MSB 18
7724 /* The width in bits of the ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED register field. */
7725 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED_WIDTH 1
7726 /* The mask used to set the ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED register field value. */
7727 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED_SET_MSK 0x00040000
7728 /* The mask used to clear the ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED register field value. */
7729 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED_CLR_MSK 0xfffbffff
7730 /* The reset value of the ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED register field. */
7731 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED_RESET 0x0
7732 /* Extracts the ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED field value from a register. */
7733 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED_GET(value) (((value) & 0x00040000) >> 18)
7734 /* Produces a ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED register field value suitable for setting the register. */
7735 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED_SET(value) (((value) << 18) & 0x00040000)
7736 
7737 /*
7738  * Field : RSVD_SMBUS_SUSPEND_STATUS
7739  *
7740  * Reserved bits - Read Only
7741  *
7742  * Field Access Macros:
7743  *
7744  */
7745 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS register field. */
7746 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS_LSB 19
7747 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS register field. */
7748 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS_MSB 19
7749 /* The width in bits of the ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS register field. */
7750 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS_WIDTH 1
7751 /* The mask used to set the ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS register field value. */
7752 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS_SET_MSK 0x00080000
7753 /* The mask used to clear the ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS register field value. */
7754 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS_CLR_MSK 0xfff7ffff
7755 /* The reset value of the ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS register field. */
7756 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS_RESET 0x0
7757 /* Extracts the ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS field value from a register. */
7758 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS_GET(value) (((value) & 0x00080000) >> 19)
7759 /* Produces a ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS register field value suitable for setting the register. */
7760 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS_SET(value) (((value) << 19) & 0x00080000)
7761 
7762 /*
7763  * Field : RSVD_SMBUS_ALERT_STATUS
7764  *
7765  * Reserved bits - Read Only
7766  *
7767  * Field Access Macros:
7768  *
7769  */
7770 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS register field. */
7771 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS_LSB 20
7772 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS register field. */
7773 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS_MSB 20
7774 /* The width in bits of the ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS register field. */
7775 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS_WIDTH 1
7776 /* The mask used to set the ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS register field value. */
7777 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS_SET_MSK 0x00100000
7778 /* The mask used to clear the ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS register field value. */
7779 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS_CLR_MSK 0xffefffff
7780 /* The reset value of the ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS register field. */
7781 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS_RESET 0x0
7782 /* Extracts the ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS field value from a register. */
7783 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS_GET(value) (((value) & 0x00100000) >> 20)
7784 /* Produces a ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS register field value suitable for setting the register. */
7785 #define ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS_SET(value) (((value) << 20) & 0x00100000)
7786 
7787 /*
7788  * Field : RSVD_IC_STATUS_2
7789  *
7790  * Reserved bits - Read Only
7791  *
7792  * Field Access Macros:
7793  *
7794  */
7795 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2 register field. */
7796 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2_LSB 21
7797 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2 register field. */
7798 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2_MSB 31
7799 /* The width in bits of the ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2 register field. */
7800 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2_WIDTH 11
7801 /* The mask used to set the ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2 register field value. */
7802 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2_SET_MSK 0xffe00000
7803 /* The mask used to clear the ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2 register field value. */
7804 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2_CLR_MSK 0x001fffff
7805 /* The reset value of the ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2 register field. */
7806 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2_RESET 0x0
7807 /* Extracts the ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2 field value from a register. */
7808 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2_GET(value) (((value) & 0xffe00000) >> 21)
7809 /* Produces a ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2 register field value suitable for setting the register. */
7810 #define ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2_SET(value) (((value) << 21) & 0xffe00000)
7811 
7812 #ifndef __ASSEMBLY__
7813 /*
7814  * WARNING: The C register and register group struct declarations are provided for
7815  * convenience and illustrative purposes. They should, however, be used with
7816  * caution as the C language standard provides no guarantees about the alignment or
7817  * atomicity of device memory accesses. The recommended practice for coding device
7818  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7819  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7820  * alt_write_dword() functions for 64 bit registers.
7821  *
7822  * The struct declaration for register ALT_I2C_IC_STATUS.
7823  */
7824 struct ALT_I2C_IC_STATUS_s
7825 {
7826  const volatile uint32_t IC_STATUS_ACTIVITY : 1; /* ALT_I2C_IC_STATUS_IC_STATUS_ACTIVITY */
7827  const volatile uint32_t TFNF : 1; /* ALT_I2C_IC_STATUS_TFNF */
7828  const volatile uint32_t TFE : 1; /* ALT_I2C_IC_STATUS_TFE */
7829  const volatile uint32_t RFNE : 1; /* ALT_I2C_IC_STATUS_RFNE */
7830  const volatile uint32_t RFF : 1; /* ALT_I2C_IC_STATUS_RFF */
7831  const volatile uint32_t MST_ACTIVITY : 1; /* ALT_I2C_IC_STATUS_MST_ACTIVITY */
7832  const volatile uint32_t SLV_ACTIVITY : 1; /* ALT_I2C_IC_STATUS_SLV_ACTIVITY */
7833  const volatile uint32_t RSVD_MST_HOLD_TX_FIFO_EMPTY : 1; /* ALT_I2C_IC_STATUS_RSVD_MST_HOLD_TX_FIFO_EMPTY */
7834  const volatile uint32_t RSVD_MST_HOLD_RX_FIFO_FULL : 1; /* ALT_I2C_IC_STATUS_RSVD_MST_HOLD_RX_FIFO_FULL */
7835  const volatile uint32_t RSVD_SLV_HOLD_TX_FIFO_EMPTY : 1; /* ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_TX_FIFO_EMPTY */
7836  const volatile uint32_t RSVD_SLV_HOLD_RX_FIFO_FULL : 1; /* ALT_I2C_IC_STATUS_RSVD_SLV_HOLD_RX_FIFO_FULL */
7837  const volatile uint32_t RSVD_SDA_STUCK_NOT_RECOVERED : 1; /* ALT_I2C_IC_STATUS_RSVD_SDA_STUCK_NOT_RECOVERED */
7838  const volatile uint32_t RSVD_IC_STATUS_1 : 4; /* ALT_I2C_IC_STATUS_RSVD_IC_STATUS_1 */
7839  const volatile uint32_t RSVD_SMBUS_QUICK_CMD_BIT : 1; /* ALT_I2C_IC_STATUS_RSVD_SMBUS_QUICK_CMD_BIT */
7840  const volatile uint32_t RSVD_SMBUS_SLAVE_ADDR_VALID : 1; /* ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_VALID */
7841  const volatile uint32_t RSVD_SMBUS_SLAVE_ADDR_RESOLVED : 1; /* ALT_I2C_IC_STATUS_RSVD_SMBUS_SLAVE_ADDR_RESOLVED */
7842  const volatile uint32_t RSVD_SMBUS_SUSPEND_STATUS : 1; /* ALT_I2C_IC_STATUS_RSVD_SMBUS_SUSPEND_STATUS */
7843  const volatile uint32_t RSVD_SMBUS_ALERT_STATUS : 1; /* ALT_I2C_IC_STATUS_RSVD_SMBUS_ALERT_STATUS */
7844  const volatile uint32_t RSVD_IC_STATUS_2 : 11; /* ALT_I2C_IC_STATUS_RSVD_IC_STATUS_2 */
7845 };
7846 
7847 /* The typedef declaration for register ALT_I2C_IC_STATUS. */
7848 typedef struct ALT_I2C_IC_STATUS_s ALT_I2C_IC_STATUS_t;
7849 #endif /* __ASSEMBLY__ */
7850 
7851 /* The reset value of the ALT_I2C_IC_STATUS register. */
7852 #define ALT_I2C_IC_STATUS_RESET 0x00000006
7853 /* The byte offset of the ALT_I2C_IC_STATUS register from the beginning of the component. */
7854 #define ALT_I2C_IC_STATUS_OFST 0x70
7855 /* The address of the ALT_I2C_IC_STATUS register. */
7856 #define ALT_I2C_IC_STATUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_STATUS_OFST))
7857 
7858 /*
7859  * Register : I2C Transmit FIFO Level Register - IC_TXFLR
7860  *
7861  * Name: I2C Transmit FIFO Level Register
7862  *
7863  * Size: TX_ABW + 1
7864  *
7865  * Address Offset: 0x74
7866  *
7867  * Read/Write Access: Read
7868  *
7869  * This register contains the number of valid data
7870  *
7871  * entries in the transmit FIFO buffer. It is cleared
7872  *
7873  * whenever:
7874  *
7875  * * The I2C is disabled
7876  *
7877  * * There is a transmit abort that is, TX_ABRT bit is
7878  *
7879  * set in the IC_RAW_INTR_STAT register
7880  *
7881  * * The slave bulk transmit mode is aborted
7882  *
7883  * The register increments whenever data is placed into
7884  *
7885  * the transmit FIFO and decrements when data is
7886  *
7887  * taken from the transmit FIFO.
7888  *
7889  * Register Layout
7890  *
7891  * Bits | Access | Reset | Description
7892  * :-------|:-------|:------|:----------------------------
7893  * [6:0] | R | 0x0 | ALT_I2C_IC_TXFLR_TXFLR
7894  * [31:7] | R | 0x0 | ALT_I2C_IC_TXFLR_RSVD_TXFLR
7895  *
7896  */
7897 /*
7898  * Field : TXFLR
7899  *
7900  * Transmit FIFO Level.
7901  *
7902  * Contains the number of valid data entries in the
7903  *
7904  * transmit FIFO.
7905  *
7906  * Reset value: 0x0
7907  *
7908  * Field Access Macros:
7909  *
7910  */
7911 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TXFLR_TXFLR register field. */
7912 #define ALT_I2C_IC_TXFLR_TXFLR_LSB 0
7913 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TXFLR_TXFLR register field. */
7914 #define ALT_I2C_IC_TXFLR_TXFLR_MSB 6
7915 /* The width in bits of the ALT_I2C_IC_TXFLR_TXFLR register field. */
7916 #define ALT_I2C_IC_TXFLR_TXFLR_WIDTH 7
7917 /* The mask used to set the ALT_I2C_IC_TXFLR_TXFLR register field value. */
7918 #define ALT_I2C_IC_TXFLR_TXFLR_SET_MSK 0x0000007f
7919 /* The mask used to clear the ALT_I2C_IC_TXFLR_TXFLR register field value. */
7920 #define ALT_I2C_IC_TXFLR_TXFLR_CLR_MSK 0xffffff80
7921 /* The reset value of the ALT_I2C_IC_TXFLR_TXFLR register field. */
7922 #define ALT_I2C_IC_TXFLR_TXFLR_RESET 0x0
7923 /* Extracts the ALT_I2C_IC_TXFLR_TXFLR field value from a register. */
7924 #define ALT_I2C_IC_TXFLR_TXFLR_GET(value) (((value) & 0x0000007f) >> 0)
7925 /* Produces a ALT_I2C_IC_TXFLR_TXFLR register field value suitable for setting the register. */
7926 #define ALT_I2C_IC_TXFLR_TXFLR_SET(value) (((value) << 0) & 0x0000007f)
7927 
7928 /*
7929  * Field : RSVD_TXFLR
7930  *
7931  * Reserved bits - Read Only
7932  *
7933  * Field Access Macros:
7934  *
7935  */
7936 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TXFLR_RSVD_TXFLR register field. */
7937 #define ALT_I2C_IC_TXFLR_RSVD_TXFLR_LSB 7
7938 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TXFLR_RSVD_TXFLR register field. */
7939 #define ALT_I2C_IC_TXFLR_RSVD_TXFLR_MSB 31
7940 /* The width in bits of the ALT_I2C_IC_TXFLR_RSVD_TXFLR register field. */
7941 #define ALT_I2C_IC_TXFLR_RSVD_TXFLR_WIDTH 25
7942 /* The mask used to set the ALT_I2C_IC_TXFLR_RSVD_TXFLR register field value. */
7943 #define ALT_I2C_IC_TXFLR_RSVD_TXFLR_SET_MSK 0xffffff80
7944 /* The mask used to clear the ALT_I2C_IC_TXFLR_RSVD_TXFLR register field value. */
7945 #define ALT_I2C_IC_TXFLR_RSVD_TXFLR_CLR_MSK 0x0000007f
7946 /* The reset value of the ALT_I2C_IC_TXFLR_RSVD_TXFLR register field. */
7947 #define ALT_I2C_IC_TXFLR_RSVD_TXFLR_RESET 0x0
7948 /* Extracts the ALT_I2C_IC_TXFLR_RSVD_TXFLR field value from a register. */
7949 #define ALT_I2C_IC_TXFLR_RSVD_TXFLR_GET(value) (((value) & 0xffffff80) >> 7)
7950 /* Produces a ALT_I2C_IC_TXFLR_RSVD_TXFLR register field value suitable for setting the register. */
7951 #define ALT_I2C_IC_TXFLR_RSVD_TXFLR_SET(value) (((value) << 7) & 0xffffff80)
7952 
7953 #ifndef __ASSEMBLY__
7954 /*
7955  * WARNING: The C register and register group struct declarations are provided for
7956  * convenience and illustrative purposes. They should, however, be used with
7957  * caution as the C language standard provides no guarantees about the alignment or
7958  * atomicity of device memory accesses. The recommended practice for coding device
7959  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7960  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7961  * alt_write_dword() functions for 64 bit registers.
7962  *
7963  * The struct declaration for register ALT_I2C_IC_TXFLR.
7964  */
7965 struct ALT_I2C_IC_TXFLR_s
7966 {
7967  const volatile uint32_t TXFLR : 7; /* ALT_I2C_IC_TXFLR_TXFLR */
7968  const volatile uint32_t RSVD_TXFLR : 25; /* ALT_I2C_IC_TXFLR_RSVD_TXFLR */
7969 };
7970 
7971 /* The typedef declaration for register ALT_I2C_IC_TXFLR. */
7972 typedef struct ALT_I2C_IC_TXFLR_s ALT_I2C_IC_TXFLR_t;
7973 #endif /* __ASSEMBLY__ */
7974 
7975 /* The reset value of the ALT_I2C_IC_TXFLR register. */
7976 #define ALT_I2C_IC_TXFLR_RESET 0x00000000
7977 /* The byte offset of the ALT_I2C_IC_TXFLR register from the beginning of the component. */
7978 #define ALT_I2C_IC_TXFLR_OFST 0x74
7979 /* The address of the ALT_I2C_IC_TXFLR register. */
7980 #define ALT_I2C_IC_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_TXFLR_OFST))
7981 
7982 /*
7983  * Register : I2C Receive FIFO Level Register - IC_RXFLR
7984  *
7985  * Name: I2C Receive FIFO Level Register
7986  *
7987  * Size: RX_ABW + 1
7988  *
7989  * Address Offset: 0x78
7990  *
7991  * Read/Write Access: Read
7992  *
7993  * This register contains the number of valid data
7994  *
7995  * entries in the receive FIFO buffer. It is cleared
7996  *
7997  * whenever:
7998  *
7999  * * The I2C is disabled
8000  *
8001  * * Whenever there is a transmit abort caused by any
8002  *
8003  * of the events tracked in IC_TX_ABRT_SOURCE
8004  *
8005  * The register increments whenever data is placed into
8006  *
8007  * the receive FIFO and decrements when data is
8008  *
8009  * taken from the receive FIFO.
8010  *
8011  * Register Layout
8012  *
8013  * Bits | Access | Reset | Description
8014  * :-------|:-------|:------|:----------------------------
8015  * [6:0] | R | 0x0 | ALT_I2C_IC_RXFLR_RXFLR
8016  * [31:7] | R | 0x0 | ALT_I2C_IC_RXFLR_RSVD_RXFLR
8017  *
8018  */
8019 /*
8020  * Field : RXFLR
8021  *
8022  * Receive FIFO Level.
8023  *
8024  * Contains the number of valid data entries in the
8025  *
8026  * receive FIFO.
8027  *
8028  * Reset value: 0x0
8029  *
8030  * Field Access Macros:
8031  *
8032  */
8033 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_RXFLR_RXFLR register field. */
8034 #define ALT_I2C_IC_RXFLR_RXFLR_LSB 0
8035 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_RXFLR_RXFLR register field. */
8036 #define ALT_I2C_IC_RXFLR_RXFLR_MSB 6
8037 /* The width in bits of the ALT_I2C_IC_RXFLR_RXFLR register field. */
8038 #define ALT_I2C_IC_RXFLR_RXFLR_WIDTH 7
8039 /* The mask used to set the ALT_I2C_IC_RXFLR_RXFLR register field value. */
8040 #define ALT_I2C_IC_RXFLR_RXFLR_SET_MSK 0x0000007f
8041 /* The mask used to clear the ALT_I2C_IC_RXFLR_RXFLR register field value. */
8042 #define ALT_I2C_IC_RXFLR_RXFLR_CLR_MSK 0xffffff80
8043 /* The reset value of the ALT_I2C_IC_RXFLR_RXFLR register field. */
8044 #define ALT_I2C_IC_RXFLR_RXFLR_RESET 0x0
8045 /* Extracts the ALT_I2C_IC_RXFLR_RXFLR field value from a register. */
8046 #define ALT_I2C_IC_RXFLR_RXFLR_GET(value) (((value) & 0x0000007f) >> 0)
8047 /* Produces a ALT_I2C_IC_RXFLR_RXFLR register field value suitable for setting the register. */
8048 #define ALT_I2C_IC_RXFLR_RXFLR_SET(value) (((value) << 0) & 0x0000007f)
8049 
8050 /*
8051  * Field : RSVD_RXFLR
8052  *
8053  * Reserved bits - Read Only
8054  *
8055  * Field Access Macros:
8056  *
8057  */
8058 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_RXFLR_RSVD_RXFLR register field. */
8059 #define ALT_I2C_IC_RXFLR_RSVD_RXFLR_LSB 7
8060 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_RXFLR_RSVD_RXFLR register field. */
8061 #define ALT_I2C_IC_RXFLR_RSVD_RXFLR_MSB 31
8062 /* The width in bits of the ALT_I2C_IC_RXFLR_RSVD_RXFLR register field. */
8063 #define ALT_I2C_IC_RXFLR_RSVD_RXFLR_WIDTH 25
8064 /* The mask used to set the ALT_I2C_IC_RXFLR_RSVD_RXFLR register field value. */
8065 #define ALT_I2C_IC_RXFLR_RSVD_RXFLR_SET_MSK 0xffffff80
8066 /* The mask used to clear the ALT_I2C_IC_RXFLR_RSVD_RXFLR register field value. */
8067 #define ALT_I2C_IC_RXFLR_RSVD_RXFLR_CLR_MSK 0x0000007f
8068 /* The reset value of the ALT_I2C_IC_RXFLR_RSVD_RXFLR register field. */
8069 #define ALT_I2C_IC_RXFLR_RSVD_RXFLR_RESET 0x0
8070 /* Extracts the ALT_I2C_IC_RXFLR_RSVD_RXFLR field value from a register. */
8071 #define ALT_I2C_IC_RXFLR_RSVD_RXFLR_GET(value) (((value) & 0xffffff80) >> 7)
8072 /* Produces a ALT_I2C_IC_RXFLR_RSVD_RXFLR register field value suitable for setting the register. */
8073 #define ALT_I2C_IC_RXFLR_RSVD_RXFLR_SET(value) (((value) << 7) & 0xffffff80)
8074 
8075 #ifndef __ASSEMBLY__
8076 /*
8077  * WARNING: The C register and register group struct declarations are provided for
8078  * convenience and illustrative purposes. They should, however, be used with
8079  * caution as the C language standard provides no guarantees about the alignment or
8080  * atomicity of device memory accesses. The recommended practice for coding device
8081  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8082  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8083  * alt_write_dword() functions for 64 bit registers.
8084  *
8085  * The struct declaration for register ALT_I2C_IC_RXFLR.
8086  */
8087 struct ALT_I2C_IC_RXFLR_s
8088 {
8089  const volatile uint32_t RXFLR : 7; /* ALT_I2C_IC_RXFLR_RXFLR */
8090  const volatile uint32_t RSVD_RXFLR : 25; /* ALT_I2C_IC_RXFLR_RSVD_RXFLR */
8091 };
8092 
8093 /* The typedef declaration for register ALT_I2C_IC_RXFLR. */
8094 typedef struct ALT_I2C_IC_RXFLR_s ALT_I2C_IC_RXFLR_t;
8095 #endif /* __ASSEMBLY__ */
8096 
8097 /* The reset value of the ALT_I2C_IC_RXFLR register. */
8098 #define ALT_I2C_IC_RXFLR_RESET 0x00000000
8099 /* The byte offset of the ALT_I2C_IC_RXFLR register from the beginning of the component. */
8100 #define ALT_I2C_IC_RXFLR_OFST 0x78
8101 /* The address of the ALT_I2C_IC_RXFLR register. */
8102 #define ALT_I2C_IC_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_RXFLR_OFST))
8103 
8104 /*
8105  * Register : I2C SDA Hold Time Length Register - IC_SDA_HOLD
8106  *
8107  * Name: I2C SDA Hold Time Length Register
8108  *
8109  * Size: 24 bits
8110  *
8111  * Address Offset: 0x7c
8112  *
8113  * Read/Write Access: Read/Write
8114  *
8115  * The bits [15:0] of this register are used to control the hold time of SDA during
8116  *
8117  * transmit in both slave and master mode (after SCL goes from HIGH to LOW).
8118  *
8119  * The bits [23:16] of this register are used to extend the SDA transition (if any)
8120  *
8121  * whenever SCL is HIGH in the receiver in either master or slave mode.
8122  *
8123  * The values in this register are in units of ic_clk period.
8124  *
8125  * This register controls the amount of time delay.
8126  *
8127  * The relevant I2C requirement is thd:DAT as detailed in the I2C
8128  *
8129  * Bus Specification.
8130  *
8131  * Register Layout
8132  *
8133  * Bits | Access | Reset | Description
8134  * :--------|:-------|:------|:-------------------------------------
8135  * [15:0] | RW | 0x1 | ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD
8136  * [23:16] | RW | 0x0 | ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD
8137  * [31:24] | R | 0x0 | ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD
8138  *
8139  */
8140 /*
8141  * Field : IC_SDA_TX_HOLD
8142  *
8143  * Sets the required SDA hold time
8144  *
8145  * in units of ic_clk period, when DW_apb_i2c acts as a transmitter.
8146  *
8147  * Reset value: IC_DEFAULT_SDA_HOLD[15:0].
8148  *
8149  * Field Access Macros:
8150  *
8151  */
8152 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD register field. */
8153 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_LSB 0
8154 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD register field. */
8155 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_MSB 15
8156 /* The width in bits of the ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD register field. */
8157 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_WIDTH 16
8158 /* The mask used to set the ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD register field value. */
8159 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_SET_MSK 0x0000ffff
8160 /* The mask used to clear the ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD register field value. */
8161 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_CLR_MSK 0xffff0000
8162 /* The reset value of the ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD register field. */
8163 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_RESET 0x1
8164 /* Extracts the ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD field value from a register. */
8165 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_GET(value) (((value) & 0x0000ffff) >> 0)
8166 /* Produces a ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD register field value suitable for setting the register. */
8167 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_SET(value) (((value) << 0) & 0x0000ffff)
8168 
8169 /*
8170  * Field : IC_SDA_RX_HOLD
8171  *
8172  * Sets the required SDA hold time
8173  *
8174  * in units of ic_clk period, when DW_apb_i2c acts as a receiver.
8175  *
8176  * Reset value: IC_DEFAULT_SDA_HOLD[23:16].
8177  *
8178  * Field Access Macros:
8179  *
8180  */
8181 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD register field. */
8182 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_LSB 16
8183 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD register field. */
8184 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_MSB 23
8185 /* The width in bits of the ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD register field. */
8186 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_WIDTH 8
8187 /* The mask used to set the ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD register field value. */
8188 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_SET_MSK 0x00ff0000
8189 /* The mask used to clear the ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD register field value. */
8190 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_CLR_MSK 0xff00ffff
8191 /* The reset value of the ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD register field. */
8192 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_RESET 0x0
8193 /* Extracts the ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD field value from a register. */
8194 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_GET(value) (((value) & 0x00ff0000) >> 16)
8195 /* Produces a ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD register field value suitable for setting the register. */
8196 #define ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_SET(value) (((value) << 16) & 0x00ff0000)
8197 
8198 /*
8199  * Field : RSVD_IC_SDA_HOLD
8200  *
8201  * Reserved bits - Read Only
8202  *
8203  * Field Access Macros:
8204  *
8205  */
8206 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD register field. */
8207 #define ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD_LSB 24
8208 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD register field. */
8209 #define ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD_MSB 31
8210 /* The width in bits of the ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD register field. */
8211 #define ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD_WIDTH 8
8212 /* The mask used to set the ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD register field value. */
8213 #define ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD_SET_MSK 0xff000000
8214 /* The mask used to clear the ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD register field value. */
8215 #define ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD_CLR_MSK 0x00ffffff
8216 /* The reset value of the ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD register field. */
8217 #define ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD_RESET 0x0
8218 /* Extracts the ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD field value from a register. */
8219 #define ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD_GET(value) (((value) & 0xff000000) >> 24)
8220 /* Produces a ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD register field value suitable for setting the register. */
8221 #define ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD_SET(value) (((value) << 24) & 0xff000000)
8222 
8223 #ifndef __ASSEMBLY__
8224 /*
8225  * WARNING: The C register and register group struct declarations are provided for
8226  * convenience and illustrative purposes. They should, however, be used with
8227  * caution as the C language standard provides no guarantees about the alignment or
8228  * atomicity of device memory accesses. The recommended practice for coding device
8229  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8230  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8231  * alt_write_dword() functions for 64 bit registers.
8232  *
8233  * The struct declaration for register ALT_I2C_IC_SDA_HOLD.
8234  */
8235 struct ALT_I2C_IC_SDA_HOLD_s
8236 {
8237  volatile uint32_t IC_SDA_TX_HOLD : 16; /* ALT_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD */
8238  volatile uint32_t IC_SDA_RX_HOLD : 8; /* ALT_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD */
8239  const volatile uint32_t RSVD_IC_SDA_HOLD : 8; /* ALT_I2C_IC_SDA_HOLD_RSVD_IC_SDA_HOLD */
8240 };
8241 
8242 /* The typedef declaration for register ALT_I2C_IC_SDA_HOLD. */
8243 typedef struct ALT_I2C_IC_SDA_HOLD_s ALT_I2C_IC_SDA_HOLD_t;
8244 #endif /* __ASSEMBLY__ */
8245 
8246 /* The reset value of the ALT_I2C_IC_SDA_HOLD register. */
8247 #define ALT_I2C_IC_SDA_HOLD_RESET 0x00000001
8248 /* The byte offset of the ALT_I2C_IC_SDA_HOLD register from the beginning of the component. */
8249 #define ALT_I2C_IC_SDA_HOLD_OFST 0x7c
8250 /* The address of the ALT_I2C_IC_SDA_HOLD register. */
8251 #define ALT_I2C_IC_SDA_HOLD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_SDA_HOLD_OFST))
8252 
8253 /*
8254  * Register : I2C Transmit Abort Source Register - IC_TX_ABRT_SOURCE
8255  *
8256  * Name: I2C Transmit Abort Source Register
8257  *
8258  * Size: 32 bits
8259  *
8260  * Address Offset: 0x80
8261  *
8262  * Read/Write Access: Read
8263  *
8264  * This register has 32 bits that indicate the source
8265  *
8266  * of the TX_ABRT bit. Except for Bit 9, this register is
8267  *
8268  * cleared whenever the IC_CLR_TX_ABRT register or the
8269  *
8270  * IC_CLR_INTR register is read. To clear Bit 9, the source
8271  *
8272  * of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must
8273  *
8274  * be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared
8275  *
8276  * (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).
8277  *
8278  * Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this
8279  *
8280  * bit can be cleared in the same manner as other bits in this
8281  *
8282  * register. If the source of the ABRT_SBYTE_NORSTRT is not fixed
8283  *
8284  * before attempting to clear this bit, Bit 9 clears for one cycle
8285  *
8286  * and is then re-asserted.
8287  *
8288  * Register Layout
8289  *
8290  * Bits | Access | Reset | Description
8291  * :--------|:-------|:------|:-----------------------------------------------------
8292  * [0] | R | 0x0 | ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK
8293  * [1] | R | 0x0 | ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK
8294  * [2] | R | 0x0 | ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK
8295  * [3] | R | 0x0 | ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK
8296  * [4] | R | 0x0 | ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK
8297  * [5] | R | 0x0 | ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ
8298  * [6] | R | 0x0 | ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET
8299  * [7] | R | 0x0 | ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET
8300  * [8] | R | 0x0 | ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT
8301  * [9] | R | 0x0 | ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT
8302  * [10] | R | 0x0 | ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT
8303  * [11] | R | 0x0 | ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS
8304  * [12] | R | 0x0 | ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST
8305  * [13] | R | 0x0 | ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO
8306  * [14] | R | 0x0 | ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST
8307  * [15] | R | 0x0 | ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX
8308  * [16] | R | 0x0 | ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT
8309  * [17] | R | 0x0 | ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW
8310  * [20:18] | R | 0x0 | ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE
8311  * [22:21] | R | 0x0 | ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE
8312  * [31:23] | R | 0x0 | ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT
8313  *
8314  */
8315 /*
8316  * Field : ABRT_7B_ADDR_NOACK
8317  *
8318  * 1: Master is in 7-bit addressing mode
8319  *
8320  * and the address sent was not
8321  *
8322  * acknowledged by any slave.
8323  *
8324  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
8325  *
8326  * Reset value: 0x0
8327  *
8328  * Role of DW_apb_i2c: Master-Transmitter
8329  *
8330  * or Master-Receiver
8331  *
8332  * Field Enumeration Values:
8333  *
8334  * Enum | Value | Description
8335  * :--------------------------------------------------------|:------|:---------------------------------------------
8336  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_E_INACTIVE | 0x0 | This abort is not generated
8337  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_E_ACTIVE | 0x1 | This abort is generated because of NOACK for
8338  * : | | 7-bit address
8339  *
8340  * Field Access Macros:
8341  *
8342  */
8343 /*
8344  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK
8345  *
8346  * This abort is not generated
8347  */
8348 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_E_INACTIVE 0x0
8349 /*
8350  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK
8351  *
8352  * This abort is generated because of NOACK for 7-bit address
8353  */
8354 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_E_ACTIVE 0x1
8355 
8356 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK register field. */
8357 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_LSB 0
8358 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK register field. */
8359 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MSB 0
8360 /* The width in bits of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK register field. */
8361 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_WIDTH 1
8362 /* The mask used to set the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK register field value. */
8363 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_SET_MSK 0x00000001
8364 /* The mask used to clear the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK register field value. */
8365 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_CLR_MSK 0xfffffffe
8366 /* The reset value of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK register field. */
8367 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_RESET 0x0
8368 /* Extracts the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK field value from a register. */
8369 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_GET(value) (((value) & 0x00000001) >> 0)
8370 /* Produces a ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK register field value suitable for setting the register. */
8371 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_SET(value) (((value) << 0) & 0x00000001)
8372 
8373 /*
8374  * Field : ABRT_10ADDR1_NOACK
8375  *
8376  * 1: Master is in 10-bit address mode and
8377  *
8378  * the first 10-bit address byte was not
8379  *
8380  * acknowledged by any slave.
8381  *
8382  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
8383  *
8384  * Reset value: 0x0
8385  *
8386  * Role of DW_apb_i2c: Master-Transmitter
8387  *
8388  * or Master-Receiver
8389  *
8390  * Field Enumeration Values:
8391  *
8392  * Enum | Value | Description
8393  * :--------------------------------------------------------|:------|:-----------------------------------------------
8394  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_E_INACTIVE | 0x0 | This abort is not generated
8395  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_E_ACTIVE | 0x1 | Byte 1 of 10Bit Address not ACKed by any slave
8396  *
8397  * Field Access Macros:
8398  *
8399  */
8400 /*
8401  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK
8402  *
8403  * This abort is not generated
8404  */
8405 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_E_INACTIVE 0x0
8406 /*
8407  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK
8408  *
8409  * Byte 1 of 10Bit Address not ACKed by any slave
8410  */
8411 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_E_ACTIVE 0x1
8412 
8413 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK register field. */
8414 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_LSB 1
8415 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK register field. */
8416 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MSB 1
8417 /* The width in bits of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK register field. */
8418 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_WIDTH 1
8419 /* The mask used to set the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK register field value. */
8420 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_SET_MSK 0x00000002
8421 /* The mask used to clear the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK register field value. */
8422 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_CLR_MSK 0xfffffffd
8423 /* The reset value of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK register field. */
8424 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_RESET 0x0
8425 /* Extracts the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK field value from a register. */
8426 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_GET(value) (((value) & 0x00000002) >> 1)
8427 /* Produces a ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK register field value suitable for setting the register. */
8428 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_SET(value) (((value) << 1) & 0x00000002)
8429 
8430 /*
8431  * Field : ABRT_10ADDR2_NOACK
8432  *
8433  * 1: Master is in 10-bit address mode and
8434  *
8435  * the second address byte of the 10-bit
8436  *
8437  * address was not acknowledged by any slave.
8438  *
8439  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
8440  *
8441  * Reset value: 0x0
8442  *
8443  * Role of DW_apb_i2c: Master-Transmitter
8444  *
8445  * or Master-Receiver
8446  *
8447  * Field Enumeration Values:
8448  *
8449  * Enum | Value | Description
8450  * :--------------------------------------------------------|:------|:-----------------------------------------------
8451  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_E_INACTIVE | 0x0 | This abort is not generated
8452  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_E_ACTIVE | 0x1 | Byte 2 of 10Bit Address not ACKed by any slave
8453  *
8454  * Field Access Macros:
8455  *
8456  */
8457 /*
8458  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK
8459  *
8460  * This abort is not generated
8461  */
8462 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_E_INACTIVE 0x0
8463 /*
8464  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK
8465  *
8466  * Byte 2 of 10Bit Address not ACKed by any slave
8467  */
8468 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_E_ACTIVE 0x1
8469 
8470 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK register field. */
8471 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_LSB 2
8472 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK register field. */
8473 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MSB 2
8474 /* The width in bits of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK register field. */
8475 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_WIDTH 1
8476 /* The mask used to set the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK register field value. */
8477 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_SET_MSK 0x00000004
8478 /* The mask used to clear the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK register field value. */
8479 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_CLR_MSK 0xfffffffb
8480 /* The reset value of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK register field. */
8481 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_RESET 0x0
8482 /* Extracts the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK field value from a register. */
8483 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_GET(value) (((value) & 0x00000004) >> 2)
8484 /* Produces a ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK register field value suitable for setting the register. */
8485 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_SET(value) (((value) << 2) & 0x00000004)
8486 
8487 /*
8488  * Field : ABRT_TXDATA_NOACK
8489  *
8490  * 1: This is a master-mode only bit.
8491  *
8492  * Master has received an
8493  *
8494  * acknowledgement for the address, but
8495  *
8496  * when it sent data byte(s) following the
8497  *
8498  * address, it did not receive an
8499  *
8500  * acknowledge from the remote slave(s).
8501  *
8502  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
8503  *
8504  * Reset value: 0x0
8505  *
8506  * Role of DW_apb_i2c: Master-Transmitter
8507  *
8508  * Field Enumeration Values:
8509  *
8510  * Enum | Value | Description
8511  * :--------------------------------------------------------------------------|:------|:-----------------------------------------------
8512  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_E_ABRT_TXDATA_NOACK_VOID | 0x0 | Transmitted data non-ACKed by addressed slave-
8513  * : | | scenario not present
8514  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_E_ABRT_TXDATA_NOACK_GENERATED | 0x1 | Transmitted data not ACKed by addressed slave
8515  *
8516  * Field Access Macros:
8517  *
8518  */
8519 /*
8520  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK
8521  *
8522  * Transmitted data non-ACKed by addressed slave-scenario not present
8523  */
8524 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_E_ABRT_TXDATA_NOACK_VOID 0x0
8525 /*
8526  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK
8527  *
8528  * Transmitted data not ACKed by addressed slave
8529  */
8530 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_E_ABRT_TXDATA_NOACK_GENERATED 0x1
8531 
8532 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK register field. */
8533 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_LSB 3
8534 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK register field. */
8535 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MSB 3
8536 /* The width in bits of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK register field. */
8537 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_WIDTH 1
8538 /* The mask used to set the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK register field value. */
8539 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_SET_MSK 0x00000008
8540 /* The mask used to clear the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK register field value. */
8541 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_CLR_MSK 0xfffffff7
8542 /* The reset value of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK register field. */
8543 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET 0x0
8544 /* Extracts the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK field value from a register. */
8545 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_GET(value) (((value) & 0x00000008) >> 3)
8546 /* Produces a ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK register field value suitable for setting the register. */
8547 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_SET(value) (((value) << 3) & 0x00000008)
8548 
8549 /*
8550  * Field : ABRT_GCALL_NOACK
8551  *
8552  * 1: DW_apb_i2c in master mode sent a
8553  *
8554  * General Call and no slave on the bus
8555  *
8556  * acknowledged the General Call.
8557  *
8558  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
8559  *
8560  * Reset value: 0x0
8561  *
8562  * Role of DW_apb_i2c: Master-Transmitter
8563  *
8564  * Field Enumeration Values:
8565  *
8566  * Enum | Value | Description
8567  * :------------------------------------------------------------------------|:------|:------------------------------------------
8568  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_E_ABRT_GCALL_NOACK_VOID | 0x0 | GCALL not ACKed by any slave-scenario not
8569  * : | | present
8570  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_E_ABRT_GCALL_NOACK_GENERATED | 0x1 | GCALL not ACKed by any slave
8571  *
8572  * Field Access Macros:
8573  *
8574  */
8575 /*
8576  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK
8577  *
8578  * GCALL not ACKed by any slave-scenario not present
8579  */
8580 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_E_ABRT_GCALL_NOACK_VOID 0x0
8581 /*
8582  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK
8583  *
8584  * GCALL not ACKed by any slave
8585  */
8586 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_E_ABRT_GCALL_NOACK_GENERATED 0x1
8587 
8588 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK register field. */
8589 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_LSB 4
8590 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK register field. */
8591 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MSB 4
8592 /* The width in bits of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK register field. */
8593 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_WIDTH 1
8594 /* The mask used to set the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK register field value. */
8595 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_SET_MSK 0x00000010
8596 /* The mask used to clear the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK register field value. */
8597 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_CLR_MSK 0xffffffef
8598 /* The reset value of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK register field. */
8599 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_RESET 0x0
8600 /* Extracts the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK field value from a register. */
8601 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_GET(value) (((value) & 0x00000010) >> 4)
8602 /* Produces a ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK register field value suitable for setting the register. */
8603 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_SET(value) (((value) << 4) & 0x00000010)
8604 
8605 /*
8606  * Field : ABRT_GCALL_READ
8607  *
8608  * 1: DW_apb_i2c in master mode sent a
8609  *
8610  * General Call but the user programmed
8611  *
8612  * the byte following the General Call to
8613  *
8614  * be a read from the bus
8615  *
8616  * (IC_DATA_CMD[9] is set to 1).
8617  *
8618  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
8619  *
8620  * Reset value: 0x0
8621  *
8622  * Role of DW_apb_i2c: Master-Transmitter
8623  *
8624  * Field Enumeration Values:
8625  *
8626  * Enum | Value | Description
8627  * :----------------------------------------------------------------------|:------|:------------------------------------------------
8628  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_E_ABRT_GCALL_READ_VOID | 0x0 | GCALL is followed by read from bus-scenario not
8629  * : | | present
8630  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_E_ABRT_GCALL_READ_GENERATED | 0x1 | GCALL is followed by read from bus
8631  *
8632  * Field Access Macros:
8633  *
8634  */
8635 /*
8636  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ
8637  *
8638  * GCALL is followed by read from bus-scenario not present
8639  */
8640 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_E_ABRT_GCALL_READ_VOID 0x0
8641 /*
8642  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ
8643  *
8644  * GCALL is followed by read from bus
8645  */
8646 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_E_ABRT_GCALL_READ_GENERATED 0x1
8647 
8648 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ register field. */
8649 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_LSB 5
8650 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ register field. */
8651 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MSB 5
8652 /* The width in bits of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ register field. */
8653 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_WIDTH 1
8654 /* The mask used to set the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ register field value. */
8655 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_SET_MSK 0x00000020
8656 /* The mask used to clear the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ register field value. */
8657 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_CLR_MSK 0xffffffdf
8658 /* The reset value of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ register field. */
8659 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_RESET 0x0
8660 /* Extracts the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ field value from a register. */
8661 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_GET(value) (((value) & 0x00000020) >> 5)
8662 /* Produces a ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ register field value suitable for setting the register. */
8663 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_SET(value) (((value) << 5) & 0x00000020)
8664 
8665 /*
8666  * Field : ABRT_HS_ACKDET
8667  *
8668  * 1: Master is in High Speed mode and
8669  *
8670  * the High Speed Master code was
8671  *
8672  * acknowledged (wrong behavior).
8673  *
8674  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
8675  *
8676  * Reset value: 0x0
8677  *
8678  * Role of DW_apb_i2c: Master
8679  *
8680  * Field Enumeration Values:
8681  *
8682  * Enum | Value | Description
8683  * :-----------------------------------------------------------------|:------|:----------------------------------------------
8684  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_E_ABRT_HS_ACK_VOID | 0x0 | HS Master code ACKed in HS Mode- scenario not
8685  * : | | present
8686  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_E_ABRT_HS_ACK_GENERATED | 0x1 | HS Master code ACKed in HS Mode
8687  *
8688  * Field Access Macros:
8689  *
8690  */
8691 /*
8692  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET
8693  *
8694  * HS Master code ACKed in HS Mode- scenario not present
8695  */
8696 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_E_ABRT_HS_ACK_VOID 0x0
8697 /*
8698  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET
8699  *
8700  * HS Master code ACKed in HS Mode
8701  */
8702 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_E_ABRT_HS_ACK_GENERATED 0x1
8703 
8704 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET register field. */
8705 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_LSB 6
8706 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET register field. */
8707 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MSB 6
8708 /* The width in bits of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET register field. */
8709 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_WIDTH 1
8710 /* The mask used to set the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET register field value. */
8711 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_SET_MSK 0x00000040
8712 /* The mask used to clear the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET register field value. */
8713 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_CLR_MSK 0xffffffbf
8714 /* The reset value of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET register field. */
8715 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_RESET 0x0
8716 /* Extracts the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET field value from a register. */
8717 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_GET(value) (((value) & 0x00000040) >> 6)
8718 /* Produces a ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET register field value suitable for setting the register. */
8719 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_SET(value) (((value) << 6) & 0x00000040)
8720 
8721 /*
8722  * Field : ABRT_SBYTE_ACKDET
8723  *
8724  * 1: Master has sent a START Byte and
8725  *
8726  * the START Byte was acknowledged (wrong behavior).
8727  *
8728  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
8729  *
8730  * Reset value: 0x0
8731  *
8732  * Role of DW_apb_i2c: Master
8733  *
8734  * Field Enumeration Values:
8735  *
8736  * Enum | Value | Description
8737  * :--------------------------------------------------------------------------|:------|:------------------------------------------
8738  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_E_ABRT_SBYTE_ACKDET_VOID | 0x0 | ACK detected for START byte- scenario not
8739  * : | | present
8740  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_E_ABRT_SBYTE_ACKDET_GENERATED | 0x1 | ACK detected for START byte
8741  *
8742  * Field Access Macros:
8743  *
8744  */
8745 /*
8746  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET
8747  *
8748  * ACK detected for START byte- scenario not present
8749  */
8750 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_E_ABRT_SBYTE_ACKDET_VOID 0x0
8751 /*
8752  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET
8753  *
8754  * ACK detected for START byte
8755  */
8756 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_E_ABRT_SBYTE_ACKDET_GENERATED 0x1
8757 
8758 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET register field. */
8759 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_LSB 7
8760 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET register field. */
8761 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MSB 7
8762 /* The width in bits of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET register field. */
8763 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_WIDTH 1
8764 /* The mask used to set the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET register field value. */
8765 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_SET_MSK 0x00000080
8766 /* The mask used to clear the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET register field value. */
8767 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_CLR_MSK 0xffffff7f
8768 /* The reset value of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET register field. */
8769 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_RESET 0x0
8770 /* Extracts the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET field value from a register. */
8771 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_GET(value) (((value) & 0x00000080) >> 7)
8772 /* Produces a ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET register field value suitable for setting the register. */
8773 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_SET(value) (((value) << 7) & 0x00000080)
8774 
8775 /*
8776  * Field : ABRT_HS_NORSTRT
8777  *
8778  * 1: The restart is disabled
8779  *
8780  * (IC_RESTART_EN bit (IC_CON[5]) =0)
8781  *
8782  * and the user is trying to use the
8783  *
8784  * master to transfer data in High Speed
8785  *
8786  * mode.
8787  *
8788  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
8789  *
8790  * Reset value: 0x0
8791  *
8792  * Role of DW_apb_i2c: Master-Transmitter
8793  *
8794  * or Master-Receiver
8795  *
8796  * Field Enumeration Values:
8797  *
8798  * Enum | Value | Description
8799  * :----------------------------------------------------------------------|:------|:---------------------------------------------
8800  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_E_ABRT_HS_NORSTRT_VOID | 0x0 | User trying to switch Master to HS mode when
8801  * : | | RESTART disabled- scenario not present
8802  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_E_ABRT_HS_NORSTRT_GENERATED | 0x1 | User trying to switch Master to HS mode when
8803  * : | | RESTART disabled
8804  *
8805  * Field Access Macros:
8806  *
8807  */
8808 /*
8809  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT
8810  *
8811  * User trying to switch Master to HS mode when RESTART disabled- scenario not
8812  * present
8813  */
8814 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_E_ABRT_HS_NORSTRT_VOID 0x0
8815 /*
8816  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT
8817  *
8818  * User trying to switch Master to HS mode when RESTART disabled
8819  */
8820 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_E_ABRT_HS_NORSTRT_GENERATED 0x1
8821 
8822 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT register field. */
8823 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_LSB 8
8824 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT register field. */
8825 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MSB 8
8826 /* The width in bits of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT register field. */
8827 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_WIDTH 1
8828 /* The mask used to set the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT register field value. */
8829 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_SET_MSK 0x00000100
8830 /* The mask used to clear the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT register field value. */
8831 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_CLR_MSK 0xfffffeff
8832 /* The reset value of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT register field. */
8833 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET 0x0
8834 /* Extracts the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT field value from a register. */
8835 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_GET(value) (((value) & 0x00000100) >> 8)
8836 /* Produces a ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT register field value suitable for setting the register. */
8837 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_SET(value) (((value) << 8) & 0x00000100)
8838 
8839 /*
8840  * Field : ABRT_SBYTE_NORSTRT
8841  *
8842  * To clear Bit 9, the source of the
8843  *
8844  * ABRT_SBYTE_NORSTRT must be fixed first;
8845  *
8846  * restart must be enabled (IC_CON[5]=1),
8847  *
8848  * the SPECIAL bit must be cleared (IC_TAR[11]),
8849  *
8850  * or the GC_OR_START bit must be cleared
8851  *
8852  * (IC_TAR[10]). Once the source of the
8853  *
8854  * ABRT_SBYTE_NORSTRT is fixed,
8855  *
8856  * then this bit can be cleared in the same
8857  *
8858  * manner as other bits in this register. If
8859  *
8860  * the source of the ABRT_SBYTE_NORSTRT is not fixed
8861  *
8862  * before attempting to clear this bit, bit 9
8863  *
8864  * clears for one cycle and then gets reasserted.
8865  *
8866  * 1: The restart is disabled (IC_RESTART_EN bit
8867  *
8868  * (IC_CON[5]) =0) and the user is trying to
8869  *
8870  * send a START Byte.
8871  *
8872  * Reset value: 0x0
8873  *
8874  * Role of DW_apb_i2c: Master
8875  *
8876  * Field Enumeration Values:
8877  *
8878  * Enum | Value | Description
8879  * :----------------------------------------------------------------------------|:------|:--------------------------------------------
8880  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_E_ABRT_SBYTE_NORSTRT_VOID | 0x0 | User trying to send START byte when RESTART
8881  * : | | disabled- scenario not present
8882  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_E_ABRT_SBYTE_NORSTRT_GENERATED | 0x1 | User trying to send START byte when RESTART
8883  * : | | disabled
8884  *
8885  * Field Access Macros:
8886  *
8887  */
8888 /*
8889  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT
8890  *
8891  * User trying to send START byte when RESTART disabled- scenario not present
8892  */
8893 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_E_ABRT_SBYTE_NORSTRT_VOID 0x0
8894 /*
8895  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT
8896  *
8897  * User trying to send START byte when RESTART disabled
8898  */
8899 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_E_ABRT_SBYTE_NORSTRT_GENERATED 0x1
8900 
8901 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT register field. */
8902 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_LSB 9
8903 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT register field. */
8904 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MSB 9
8905 /* The width in bits of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT register field. */
8906 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_WIDTH 1
8907 /* The mask used to set the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT register field value. */
8908 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_SET_MSK 0x00000200
8909 /* The mask used to clear the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT register field value. */
8910 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_CLR_MSK 0xfffffdff
8911 /* The reset value of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT register field. */
8912 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET 0x0
8913 /* Extracts the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT field value from a register. */
8914 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_GET(value) (((value) & 0x00000200) >> 9)
8915 /* Produces a ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT register field value suitable for setting the register. */
8916 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_SET(value) (((value) << 9) & 0x00000200)
8917 
8918 /*
8919  * Field : ABRT_10B_RD_NORSTRT
8920  *
8921  * 1: The restart is disabled
8922  *
8923  * (IC_RESTART_EN bit (IC_CON[5]) =0)
8924  *
8925  * and the master sends a read
8926  *
8927  * command in 10-bit addressing mode.
8928  *
8929  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
8930  *
8931  * Reset value: 0x0
8932  *
8933  * Role of DW_apb_i2c: Master-Receiver
8934  *
8935  * Field Enumeration Values:
8936  *
8937  * Enum | Value | Description
8938  * :----------------------------------------------------------------------|:------|:-----------------------------------------------
8939  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_E_ABRT_10B_RD_VOID | 0x0 | Master not trying to read in 10Bit addressing
8940  * : | | mode when RESTART disabled
8941  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_E_ABRT_10B_RD_GENERATED | 0x1 | Master trying to read in 10Bit addressing mode
8942  * : | | when RESTART disabled
8943  *
8944  * Field Access Macros:
8945  *
8946  */
8947 /*
8948  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT
8949  *
8950  * Master not trying to read in 10Bit addressing mode when RESTART disabled
8951  */
8952 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_E_ABRT_10B_RD_VOID 0x0
8953 /*
8954  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT
8955  *
8956  * Master trying to read in 10Bit addressing mode when RESTART disabled
8957  */
8958 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_E_ABRT_10B_RD_GENERATED 0x1
8959 
8960 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT register field. */
8961 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_LSB 10
8962 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT register field. */
8963 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB 10
8964 /* The width in bits of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT register field. */
8965 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_WIDTH 1
8966 /* The mask used to set the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT register field value. */
8967 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_SET_MSK 0x00000400
8968 /* The mask used to clear the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT register field value. */
8969 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_CLR_MSK 0xfffffbff
8970 /* The reset value of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT register field. */
8971 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET 0x0
8972 /* Extracts the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT field value from a register. */
8973 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_GET(value) (((value) & 0x00000400) >> 10)
8974 /* Produces a ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT register field value suitable for setting the register. */
8975 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_SET(value) (((value) << 10) & 0x00000400)
8976 
8977 /*
8978  * Field : ABRT_MASTER_DIS
8979  *
8980  * 1: User tries to initiate a Master
8981  *
8982  * operation with the Master mode disabled.
8983  *
8984  * Reset value: 0x0
8985  *
8986  * Role of DW_apb_i2c: Master-Transmitter
8987  *
8988  * or Master-Receiver
8989  *
8990  * Field Enumeration Values:
8991  *
8992  * Enum | Value | Description
8993  * :----------------------------------------------------------------------|:------|:---------------------------------------------
8994  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_E_ABRT_MASTER_DIS_VOID | 0x0 | User initiating master operation when MASTER
8995  * : | | disabled- scenario not present
8996  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_E_ABRT_MASTER_DIS_GENERATED | 0x1 | User intitating master operation when MASTER
8997  * : | | disabled
8998  *
8999  * Field Access Macros:
9000  *
9001  */
9002 /*
9003  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS
9004  *
9005  * User initiating master operation when MASTER disabled- scenario not present
9006  */
9007 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_E_ABRT_MASTER_DIS_VOID 0x0
9008 /*
9009  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS
9010  *
9011  * User intitating master operation when MASTER disabled
9012  */
9013 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_E_ABRT_MASTER_DIS_GENERATED 0x1
9014 
9015 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS register field. */
9016 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_LSB 11
9017 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS register field. */
9018 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MSB 11
9019 /* The width in bits of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS register field. */
9020 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_WIDTH 1
9021 /* The mask used to set the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS register field value. */
9022 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_SET_MSK 0x00000800
9023 /* The mask used to clear the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS register field value. */
9024 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_CLR_MSK 0xfffff7ff
9025 /* The reset value of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS register field. */
9026 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET 0x0
9027 /* Extracts the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS field value from a register. */
9028 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_GET(value) (((value) & 0x00000800) >> 11)
9029 /* Produces a ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS register field value suitable for setting the register. */
9030 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_SET(value) (((value) << 11) & 0x00000800)
9031 
9032 /*
9033  * Field : ARB_LOST
9034  *
9035  * 1: Master has lost arbitration, or if
9036  *
9037  * IC_TX_ABRT_SOURCE[14] is also
9038  *
9039  * set, then the slave transmitter has lost
9040  *
9041  * arbitration.
9042  *
9043  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
9044  *
9045  * Reset value: 0x0
9046  *
9047  * Role of DW_apb_i2c: Master-Transmitter
9048  *
9049  * or Slave-Transmitter
9050  *
9051  * Field Enumeration Values:
9052  *
9053  * Enum | Value | Description
9054  * :---------------------------------------------------------|:------|:----------------------------------------------
9055  * ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST_E_ABRT_LOST_VOID | 0x0 | Master or Slave-Transmitter lost arbitration-
9056  * : | | scenario not present
9057  * ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST_E_ABRT_LOST_GENERATED | 0x1 | Master or Slave-Transmitter lost arbitration
9058  *
9059  * Field Access Macros:
9060  *
9061  */
9062 /*
9063  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST
9064  *
9065  * Master or Slave-Transmitter lost arbitration- scenario not present
9066  */
9067 #define ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST_E_ABRT_LOST_VOID 0x0
9068 /*
9069  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST
9070  *
9071  * Master or Slave-Transmitter lost arbitration
9072  */
9073 #define ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST_E_ABRT_LOST_GENERATED 0x1
9074 
9075 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST register field. */
9076 #define ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST_LSB 12
9077 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST register field. */
9078 #define ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MSB 12
9079 /* The width in bits of the ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST register field. */
9080 #define ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST_WIDTH 1
9081 /* The mask used to set the ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST register field value. */
9082 #define ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST_SET_MSK 0x00001000
9083 /* The mask used to clear the ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST register field value. */
9084 #define ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST_CLR_MSK 0xffffefff
9085 /* The reset value of the ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST register field. */
9086 #define ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET 0x0
9087 /* Extracts the ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST field value from a register. */
9088 #define ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST_GET(value) (((value) & 0x00001000) >> 12)
9089 /* Produces a ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST register field value suitable for setting the register. */
9090 #define ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST_SET(value) (((value) << 12) & 0x00001000)
9091 
9092 /*
9093  * Field : ABRT_SLVFLUSH_TXFIFO
9094  *
9095  * 1: Slave has received a read command
9096  *
9097  * and some data exists in the TX FIFO so
9098  *
9099  * the slave issues a TX_ABRT interrupt to
9100  *
9101  * flush old data in TX FIFO.
9102  *
9103  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
9104  *
9105  * Reset value: 0x0
9106  *
9107  * Role of DW_apb_i2c: Slave-Transmitter
9108  *
9109  * Field Enumeration Values:
9110  *
9111  * Enum | Value | Description
9112  * :--------------------------------------------------------------------------------|:------|:--------------------------------------------
9113  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_E_ABRT_SLVFLUSH_TXFIFO_VOID | 0x0 | Slave flushes existing data in TX-FIFO upon
9114  * : | | getting read command- scenario not present
9115  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_E_ABRT_SLVFLUSH_TXFIFO_GENERATED | 0x1 | Slave flushes existing data in TX-FIFO upon
9116  * : | | getting read command
9117  *
9118  * Field Access Macros:
9119  *
9120  */
9121 /*
9122  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO
9123  *
9124  * Slave flushes existing data in TX-FIFO upon getting read command- scenario not
9125  * present
9126  */
9127 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_E_ABRT_SLVFLUSH_TXFIFO_VOID 0x0
9128 /*
9129  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO
9130  *
9131  * Slave flushes existing data in TX-FIFO upon getting read command
9132  */
9133 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_E_ABRT_SLVFLUSH_TXFIFO_GENERATED 0x1
9134 
9135 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO register field. */
9136 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_LSB 13
9137 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO register field. */
9138 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB 13
9139 /* The width in bits of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO register field. */
9140 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_WIDTH 1
9141 /* The mask used to set the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO register field value. */
9142 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_SET_MSK 0x00002000
9143 /* The mask used to clear the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO register field value. */
9144 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_CLR_MSK 0xffffdfff
9145 /* The reset value of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO register field. */
9146 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET 0x0
9147 /* Extracts the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO field value from a register. */
9148 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_GET(value) (((value) & 0x00002000) >> 13)
9149 /* Produces a ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO register field value suitable for setting the register. */
9150 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_SET(value) (((value) << 13) & 0x00002000)
9151 
9152 /*
9153  * Field : ABRT_SLV_ARBLOST
9154  *
9155  * 1: Slave lost the bus while transmitting
9156  *
9157  * data to a remote master.
9158  *
9159  * IC_TX_ABRT_SOURCE[12] is set at
9160  *
9161  * the same time.
9162  *
9163  * Note: Even though the slave never
9164  *
9165  * 'owns' the bus, something could go
9166  *
9167  * wrong on the bus. This is a fail safe
9168  *
9169  * check. For instance, during a data
9170  *
9171  * transmission at the low-to-high
9172  *
9173  * transition of SCL, if what is on the data
9174  *
9175  * bus is not what is supposed to be
9176  *
9177  * transmitted, then DW_apb_i2c no
9178  *
9179  * longer own the bus.
9180  *
9181  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
9182  *
9183  * Reset value: 0x0
9184  *
9185  * Role of DW_apb_i2c: Slave-Transmitter
9186  *
9187  * Field Enumeration Values:
9188  *
9189  * Enum | Value | Description
9190  * :------------------------------------------------------------------------|:------|:-----------------------------------------
9191  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_E_ABRT_SLV_ARBLOST_VOID | 0x0 | Slave lost arbitration to remote master-
9192  * : | | scenario not present
9193  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_E_ABRT_SLV_ARBLOST_GENERATED | 0x1 | Slave lost arbitration to remote master
9194  *
9195  * Field Access Macros:
9196  *
9197  */
9198 /*
9199  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST
9200  *
9201  * Slave lost arbitration to remote master- scenario not present
9202  */
9203 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_E_ABRT_SLV_ARBLOST_VOID 0x0
9204 /*
9205  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST
9206  *
9207  * Slave lost arbitration to remote master
9208  */
9209 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_E_ABRT_SLV_ARBLOST_GENERATED 0x1
9210 
9211 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST register field. */
9212 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_LSB 14
9213 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST register field. */
9214 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MSB 14
9215 /* The width in bits of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST register field. */
9216 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_WIDTH 1
9217 /* The mask used to set the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST register field value. */
9218 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_SET_MSK 0x00004000
9219 /* The mask used to clear the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST register field value. */
9220 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_CLR_MSK 0xffffbfff
9221 /* The reset value of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST register field. */
9222 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_RESET 0x0
9223 /* Extracts the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST field value from a register. */
9224 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_GET(value) (((value) & 0x00004000) >> 14)
9225 /* Produces a ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST register field value suitable for setting the register. */
9226 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_SET(value) (((value) << 14) & 0x00004000)
9227 
9228 /*
9229  * Field : ABRT_SLVRD_INTX
9230  *
9231  * 1: When the processor side responds to
9232  *
9233  * a slave mode request for data to be
9234  *
9235  * transmitted to a remote master and user
9236  *
9237  * writes a 1 in CMD (bit 8) of
9238  *
9239  * IC_DATA_CMD register.
9240  *
9241  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
9242  *
9243  * Reset value: 0x0
9244  *
9245  * Role of DW_apb_i2c: Slave-Transmitter
9246  *
9247  * Field Enumeration Values:
9248  *
9249  * Enum | Value | Description
9250  * :----------------------------------------------------------------------|:------|:---------------------------------------------
9251  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_E_ABRT_SLVRD_INTX_VOID | 0x0 | Slave trying to transmit to remote master in
9252  * : | | read mode- scenario not present
9253  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_E_ABRT_SLVRD_INTX_GENERATED | 0x1 | Slave trying to transmit to remote master in
9254  * : | | read mode
9255  *
9256  * Field Access Macros:
9257  *
9258  */
9259 /*
9260  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX
9261  *
9262  * Slave trying to transmit to remote master in read mode- scenario not present
9263  */
9264 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_E_ABRT_SLVRD_INTX_VOID 0x0
9265 /*
9266  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX
9267  *
9268  * Slave trying to transmit to remote master in read mode
9269  */
9270 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_E_ABRT_SLVRD_INTX_GENERATED 0x1
9271 
9272 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX register field. */
9273 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_LSB 15
9274 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX register field. */
9275 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MSB 15
9276 /* The width in bits of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX register field. */
9277 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_WIDTH 1
9278 /* The mask used to set the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX register field value. */
9279 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_SET_MSK 0x00008000
9280 /* The mask used to clear the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX register field value. */
9281 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_CLR_MSK 0xffff7fff
9282 /* The reset value of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX register field. */
9283 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET 0x0
9284 /* Extracts the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX field value from a register. */
9285 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_GET(value) (((value) & 0x00008000) >> 15)
9286 /* Produces a ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX register field value suitable for setting the register. */
9287 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_SET(value) (((value) << 15) & 0x00008000)
9288 
9289 /*
9290  * Field : ABRT_USER_ABRT
9291  *
9292  * This is a master-mode-only bit. Master has
9293  *
9294  * detected the transfer abort (IC_ENABLE[1])
9295  *
9296  * Reset value: 0x0
9297  *
9298  * Role of DW_apb_i2c: Master-Transmitter
9299  *
9300  * Field Enumeration Values:
9301  *
9302  * Enum | Value | Description
9303  * :--------------------------------------------------------------------|:------|:------------------------------------------------
9304  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_E_ABRT_USER_ABRT_VOID | 0x0 | Transfer abort detected by master- scenario not
9305  * : | | present
9306  * ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_E_ABRT_USER_ABRT_GENERATED | 0x1 | Transfer abort detected by master
9307  *
9308  * Field Access Macros:
9309  *
9310  */
9311 /*
9312  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT
9313  *
9314  * Transfer abort detected by master- scenario not present
9315  */
9316 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_E_ABRT_USER_ABRT_VOID 0x0
9317 /*
9318  * Enumerated value for register field ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT
9319  *
9320  * Transfer abort detected by master
9321  */
9322 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_E_ABRT_USER_ABRT_GENERATED 0x1
9323 
9324 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT register field. */
9325 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_LSB 16
9326 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT register field. */
9327 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_MSB 16
9328 /* The width in bits of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT register field. */
9329 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_WIDTH 1
9330 /* The mask used to set the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT register field value. */
9331 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_SET_MSK 0x00010000
9332 /* The mask used to clear the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT register field value. */
9333 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_CLR_MSK 0xfffeffff
9334 /* The reset value of the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT register field. */
9335 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_RESET 0x0
9336 /* Extracts the ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT field value from a register. */
9337 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_GET(value) (((value) & 0x00010000) >> 16)
9338 /* Produces a ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT register field value suitable for setting the register. */
9339 #define ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_SET(value) (((value) << 16) & 0x00010000)
9340 
9341 /*
9342  * Field : RSVD_ABRT_SDA_STUCK_AT_LOW
9343  *
9344  * Field Access Macros:
9345  *
9346  */
9347 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW register field. */
9348 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW_LSB 17
9349 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW register field. */
9350 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW_MSB 17
9351 /* The width in bits of the ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW register field. */
9352 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW_WIDTH 1
9353 /* The mask used to set the ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW register field value. */
9354 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW_SET_MSK 0x00020000
9355 /* The mask used to clear the ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW register field value. */
9356 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW_CLR_MSK 0xfffdffff
9357 /* The reset value of the ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW register field. */
9358 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW_RESET 0x0
9359 /* Extracts the ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW field value from a register. */
9360 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW_GET(value) (((value) & 0x00020000) >> 17)
9361 /* Produces a ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW register field value suitable for setting the register. */
9362 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW_SET(value) (((value) << 17) & 0x00020000)
9363 
9364 /*
9365  * Field : RSVD_ABRT_DEVICE_WRITE
9366  *
9367  * Reserved bits - Read Only
9368  *
9369  * Field Access Macros:
9370  *
9371  */
9372 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE register field. */
9373 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE_LSB 18
9374 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE register field. */
9375 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE_MSB 20
9376 /* The width in bits of the ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE register field. */
9377 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE_WIDTH 3
9378 /* The mask used to set the ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE register field value. */
9379 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE_SET_MSK 0x001c0000
9380 /* The mask used to clear the ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE register field value. */
9381 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE_CLR_MSK 0xffe3ffff
9382 /* The reset value of the ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE register field. */
9383 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE_RESET 0x0
9384 /* Extracts the ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE field value from a register. */
9385 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE_GET(value) (((value) & 0x001c0000) >> 18)
9386 /* Produces a ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE register field value suitable for setting the register. */
9387 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE_SET(value) (((value) << 18) & 0x001c0000)
9388 
9389 /*
9390  * Field : RSVD_IC_TX_ABRT_SOURCE
9391  *
9392  * Reserved bits - Read Only
9393  *
9394  * Field Access Macros:
9395  *
9396  */
9397 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE register field. */
9398 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE_LSB 21
9399 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE register field. */
9400 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE_MSB 22
9401 /* The width in bits of the ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE register field. */
9402 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE_WIDTH 2
9403 /* The mask used to set the ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE register field value. */
9404 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE_SET_MSK 0x00600000
9405 /* The mask used to clear the ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE register field value. */
9406 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE_CLR_MSK 0xff9fffff
9407 /* The reset value of the ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE register field. */
9408 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE_RESET 0x0
9409 /* Extracts the ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE field value from a register. */
9410 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE_GET(value) (((value) & 0x00600000) >> 21)
9411 /* Produces a ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE register field value suitable for setting the register. */
9412 #define ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE_SET(value) (((value) << 21) & 0x00600000)
9413 
9414 /*
9415  * Field : TX_FLUSH_CNT
9416  *
9417  * This field indicates the
9418  *
9419  * number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt.
9420  *
9421  * It is cleared whenever I2C is disabled.
9422  *
9423  * Reset value: 0x0
9424  *
9425  * Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter
9426  *
9427  * Field Access Macros:
9428  *
9429  */
9430 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT register field. */
9431 #define ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_LSB 23
9432 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT register field. */
9433 #define ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_MSB 31
9434 /* The width in bits of the ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT register field. */
9435 #define ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_WIDTH 9
9436 /* The mask used to set the ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT register field value. */
9437 #define ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_SET_MSK 0xff800000
9438 /* The mask used to clear the ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT register field value. */
9439 #define ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_CLR_MSK 0x007fffff
9440 /* The reset value of the ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT register field. */
9441 #define ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_RESET 0x0
9442 /* Extracts the ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT field value from a register. */
9443 #define ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_GET(value) (((value) & 0xff800000) >> 23)
9444 /* Produces a ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT register field value suitable for setting the register. */
9445 #define ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_SET(value) (((value) << 23) & 0xff800000)
9446 
9447 #ifndef __ASSEMBLY__
9448 /*
9449  * WARNING: The C register and register group struct declarations are provided for
9450  * convenience and illustrative purposes. They should, however, be used with
9451  * caution as the C language standard provides no guarantees about the alignment or
9452  * atomicity of device memory accesses. The recommended practice for coding device
9453  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9454  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9455  * alt_write_dword() functions for 64 bit registers.
9456  *
9457  * The struct declaration for register ALT_I2C_IC_TX_ABRT_SOURCE.
9458  */
9459 struct ALT_I2C_IC_TX_ABRT_SOURCE_s
9460 {
9461  const volatile uint32_t ABRT_7B_ADDR_NOACK : 1; /* ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK */
9462  const volatile uint32_t ABRT_10ADDR1_NOACK : 1; /* ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK */
9463  const volatile uint32_t ABRT_10ADDR2_NOACK : 1; /* ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK */
9464  const volatile uint32_t ABRT_TXDATA_NOACK : 1; /* ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK */
9465  const volatile uint32_t ABRT_GCALL_NOACK : 1; /* ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK */
9466  const volatile uint32_t ABRT_GCALL_READ : 1; /* ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ */
9467  const volatile uint32_t ABRT_HS_ACKDET : 1; /* ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET */
9468  const volatile uint32_t ABRT_SBYTE_ACKDET : 1; /* ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET */
9469  const volatile uint32_t ABRT_HS_NORSTRT : 1; /* ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT */
9470  const volatile uint32_t ABRT_SBYTE_NORSTRT : 1; /* ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT */
9471  const volatile uint32_t ABRT_10B_RD_NORSTRT : 1; /* ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT */
9472  const volatile uint32_t ABRT_MASTER_DIS : 1; /* ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS */
9473  const volatile uint32_t ARB_LOST : 1; /* ALT_I2C_IC_TX_ABRT_SOURCE_ARB_LOST */
9474  const volatile uint32_t ABRT_SLVFLUSH_TXFIFO : 1; /* ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO */
9475  const volatile uint32_t ABRT_SLV_ARBLOST : 1; /* ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST */
9476  const volatile uint32_t ABRT_SLVRD_INTX : 1; /* ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX */
9477  const volatile uint32_t ABRT_USER_ABRT : 1; /* ALT_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT */
9478  const volatile uint32_t RSVD_ABRT_SDA_STUCK_AT_LOW : 1; /* ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_SDA_STUCK_AT_LOW */
9479  const volatile uint32_t RSVD_ABRT_DEVICE_WRITE : 3; /* ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_ABRT_DEVICE_WRITE */
9480  const volatile uint32_t RSVD_IC_TX_ABRT_SOURCE : 2; /* ALT_I2C_IC_TX_ABRT_SOURCE_RSVD_IC_TX_ABRT_SOURCE */
9481  const volatile uint32_t TX_FLUSH_CNT : 9; /* ALT_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT */
9482 };
9483 
9484 /* The typedef declaration for register ALT_I2C_IC_TX_ABRT_SOURCE. */
9485 typedef struct ALT_I2C_IC_TX_ABRT_SOURCE_s ALT_I2C_IC_TX_ABRT_SOURCE_t;
9486 #endif /* __ASSEMBLY__ */
9487 
9488 /* The reset value of the ALT_I2C_IC_TX_ABRT_SOURCE register. */
9489 #define ALT_I2C_IC_TX_ABRT_SOURCE_RESET 0x00000000
9490 /* The byte offset of the ALT_I2C_IC_TX_ABRT_SOURCE register from the beginning of the component. */
9491 #define ALT_I2C_IC_TX_ABRT_SOURCE_OFST 0x80
9492 /* The address of the ALT_I2C_IC_TX_ABRT_SOURCE register. */
9493 #define ALT_I2C_IC_TX_ABRT_SOURCE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_TX_ABRT_SOURCE_OFST))
9494 
9495 /*
9496  * Register : Generate Slave Data NACK Register - IC_SLV_DATA_NACK_ONLY
9497  *
9498  * Name: Generate Slave Data NACK Register
9499  *
9500  * Size: 1 bit
9501  *
9502  * Address Offset: 0x84
9503  *
9504  * Read/Write Access: Read/Write
9505  *
9506  * The register is used to generate a NACK for
9507  *
9508  * the data part of a transfer when DW_apb_i2c is
9509  *
9510  * acting as a slave-receiver. This register only
9511  *
9512  * exists when the IC_SLV_DATA_NACK_ONLY parameter
9513  *
9514  * is set to 1. When this parameter disabled, this
9515  *
9516  * register does not exist and writing to the register's
9517  *
9518  * address has no effect.
9519  *
9520  * Dependencies: This register is not applicable when IC_ULTRA_FAST_MODE=1
9521  *
9522  * Register Layout
9523  *
9524  * Bits | Access | Reset | Description
9525  * :-------|:-------|:------|:---------------------------------------------------------
9526  * [0] | RW | 0x0 | ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK
9527  * [31:1] | R | 0x0 | ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY
9528  *
9529  */
9530 /*
9531  * Field : NACK
9532  *
9533  * Generate NACK.
9534  *
9535  * This NACK generation only occurs when DW_apb_i2c is a
9536  *
9537  * slave-receiver. If this register is set to a value of 1,
9538  *
9539  * it can only generate a NACK after a data byte is received;
9540  *
9541  * hence, the data transfer is aborted and the data received
9542  *
9543  * is not pushed to the receive buffer.
9544  *
9545  * When the register is set to a value of 0, it generates
9546  *
9547  * NACK/ACK, depending on normal criteria.
9548  *
9549  * 1 = generate NACK after data byte received
9550  *
9551  * 0 = generate NACK/ACK normally
9552  *
9553  * Reset value: 0x0
9554  *
9555  * Field Enumeration Values:
9556  *
9557  * Enum | Value | Description
9558  * :----------------------------------------------|:------|:----------------------------------------
9559  * ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK_E_DISABLED | 0x0 | Slave reciever generates NACK normally
9560  * ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK_E_ENABLED | 0x1 | Slave reciever generates NACK upon data
9561  * : | | reception only
9562  *
9563  * Field Access Macros:
9564  *
9565  */
9566 /*
9567  * Enumerated value for register field ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK
9568  *
9569  * Slave reciever generates NACK normally
9570  */
9571 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK_E_DISABLED 0x0
9572 /*
9573  * Enumerated value for register field ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK
9574  *
9575  * Slave reciever generates NACK upon data reception only
9576  */
9577 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK_E_ENABLED 0x1
9578 
9579 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK register field. */
9580 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK_LSB 0
9581 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK register field. */
9582 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK_MSB 0
9583 /* The width in bits of the ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK register field. */
9584 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK_WIDTH 1
9585 /* The mask used to set the ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK register field value. */
9586 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK_SET_MSK 0x00000001
9587 /* The mask used to clear the ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK register field value. */
9588 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK_CLR_MSK 0xfffffffe
9589 /* The reset value of the ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK register field. */
9590 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK_RESET 0x0
9591 /* Extracts the ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK field value from a register. */
9592 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK_GET(value) (((value) & 0x00000001) >> 0)
9593 /* Produces a ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK register field value suitable for setting the register. */
9594 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK_SET(value) (((value) << 0) & 0x00000001)
9595 
9596 /*
9597  * Field : RSVD_IC_SLV_DATA_NACK_ONLY
9598  *
9599  * Reserved bits - Read Only
9600  *
9601  * Field Access Macros:
9602  *
9603  */
9604 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY register field. */
9605 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY_LSB 1
9606 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY register field. */
9607 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY_MSB 31
9608 /* The width in bits of the ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY register field. */
9609 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY_WIDTH 31
9610 /* The mask used to set the ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY register field value. */
9611 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY_SET_MSK 0xfffffffe
9612 /* The mask used to clear the ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY register field value. */
9613 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY_CLR_MSK 0x00000001
9614 /* The reset value of the ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY register field. */
9615 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY_RESET 0x0
9616 /* Extracts the ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY field value from a register. */
9617 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY_GET(value) (((value) & 0xfffffffe) >> 1)
9618 /* Produces a ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY register field value suitable for setting the register. */
9619 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY_SET(value) (((value) << 1) & 0xfffffffe)
9620 
9621 #ifndef __ASSEMBLY__
9622 /*
9623  * WARNING: The C register and register group struct declarations are provided for
9624  * convenience and illustrative purposes. They should, however, be used with
9625  * caution as the C language standard provides no guarantees about the alignment or
9626  * atomicity of device memory accesses. The recommended practice for coding device
9627  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9628  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9629  * alt_write_dword() functions for 64 bit registers.
9630  *
9631  * The struct declaration for register ALT_I2C_IC_SLV_DATA_NACK_ONLY.
9632  */
9633 struct ALT_I2C_IC_SLV_DATA_NACK_ONLY_s
9634 {
9635  volatile uint32_t NACK : 1; /* ALT_I2C_IC_SLV_DATA_NACK_ONLY_NACK */
9636  const volatile uint32_t RSVD_IC_SLV_DATA_NACK_ONLY : 31; /* ALT_I2C_IC_SLV_DATA_NACK_ONLY_RSVD_IC_SLV_DATA_NACK_ONLY */
9637 };
9638 
9639 /* The typedef declaration for register ALT_I2C_IC_SLV_DATA_NACK_ONLY. */
9640 typedef struct ALT_I2C_IC_SLV_DATA_NACK_ONLY_s ALT_I2C_IC_SLV_DATA_NACK_ONLY_t;
9641 #endif /* __ASSEMBLY__ */
9642 
9643 /* The reset value of the ALT_I2C_IC_SLV_DATA_NACK_ONLY register. */
9644 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_RESET 0x00000000
9645 /* The byte offset of the ALT_I2C_IC_SLV_DATA_NACK_ONLY register from the beginning of the component. */
9646 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_OFST 0x84
9647 /* The address of the ALT_I2C_IC_SLV_DATA_NACK_ONLY register. */
9648 #define ALT_I2C_IC_SLV_DATA_NACK_ONLY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_SLV_DATA_NACK_ONLY_OFST))
9649 
9650 /*
9651  * Register : DMA Control Register - IC_DMA_CR
9652  *
9653  * Name: DMA Control Register
9654  *
9655  * Size: 2 bits
9656  *
9657  * Address Offset: 0x88
9658  *
9659  * Read/Write Access: Read/Write
9660  *
9661  * This register is only valid when DW_apb_i2c is configured
9662  *
9663  * with a set of DMA Controller interface signals (IC_HAS_DMA = 1).
9664  *
9665  * When DW_apb_i2c is not configured for DMA operation, this register
9666  *
9667  * does not exist and writing to the register's address has no
9668  *
9669  * effect and reading from this register address will return zero.
9670  *
9671  * The register is used to enable the DMA Controller interface operation.
9672  *
9673  * There is a separate bit for transmit and receive. This can be programmed
9674  *
9675  * regardless of the state of IC_ENABLE.
9676  *
9677  * Register Layout
9678  *
9679  * Bits | Access | Reset | Description
9680  * :-------|:-------|:------|:--------------------------------------
9681  * [0] | RW | 0x0 | ALT_I2C_IC_DMA_CR_RDMAE
9682  * [1] | RW | 0x0 | ALT_I2C_IC_DMA_CR_TDMAE
9683  * [31:2] | R | 0x0 | ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31
9684  *
9685  */
9686 /*
9687  * Field : RDMAE
9688  *
9689  * Receive DMA Enable.
9690  *
9691  * This bit enables/disables the receive FIFO DMA
9692  *
9693  * channel.
9694  *
9695  * 0 = Receive DMA disabled
9696  *
9697  * 1 = Receive DMA enabled
9698  *
9699  * Reset value: 0x0
9700  *
9701  * Field Enumeration Values:
9702  *
9703  * Enum | Value | Description
9704  * :-----------------------------------|:------|:----------------------------------
9705  * ALT_I2C_IC_DMA_CR_RDMAE_E_DISABLED | 0x0 | Receive FIFO DMA channel disabled
9706  * ALT_I2C_IC_DMA_CR_RDMAE_E_ENABLED | 0x1 | Receive FIFO DMA channel enabled
9707  *
9708  * Field Access Macros:
9709  *
9710  */
9711 /*
9712  * Enumerated value for register field ALT_I2C_IC_DMA_CR_RDMAE
9713  *
9714  * Receive FIFO DMA channel disabled
9715  */
9716 #define ALT_I2C_IC_DMA_CR_RDMAE_E_DISABLED 0x0
9717 /*
9718  * Enumerated value for register field ALT_I2C_IC_DMA_CR_RDMAE
9719  *
9720  * Receive FIFO DMA channel enabled
9721  */
9722 #define ALT_I2C_IC_DMA_CR_RDMAE_E_ENABLED 0x1
9723 
9724 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_DMA_CR_RDMAE register field. */
9725 #define ALT_I2C_IC_DMA_CR_RDMAE_LSB 0
9726 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_DMA_CR_RDMAE register field. */
9727 #define ALT_I2C_IC_DMA_CR_RDMAE_MSB 0
9728 /* The width in bits of the ALT_I2C_IC_DMA_CR_RDMAE register field. */
9729 #define ALT_I2C_IC_DMA_CR_RDMAE_WIDTH 1
9730 /* The mask used to set the ALT_I2C_IC_DMA_CR_RDMAE register field value. */
9731 #define ALT_I2C_IC_DMA_CR_RDMAE_SET_MSK 0x00000001
9732 /* The mask used to clear the ALT_I2C_IC_DMA_CR_RDMAE register field value. */
9733 #define ALT_I2C_IC_DMA_CR_RDMAE_CLR_MSK 0xfffffffe
9734 /* The reset value of the ALT_I2C_IC_DMA_CR_RDMAE register field. */
9735 #define ALT_I2C_IC_DMA_CR_RDMAE_RESET 0x0
9736 /* Extracts the ALT_I2C_IC_DMA_CR_RDMAE field value from a register. */
9737 #define ALT_I2C_IC_DMA_CR_RDMAE_GET(value) (((value) & 0x00000001) >> 0)
9738 /* Produces a ALT_I2C_IC_DMA_CR_RDMAE register field value suitable for setting the register. */
9739 #define ALT_I2C_IC_DMA_CR_RDMAE_SET(value) (((value) << 0) & 0x00000001)
9740 
9741 /*
9742  * Field : TDMAE
9743  *
9744  * Transmit DMA Enable.
9745  *
9746  * //This bit enables/disables the transmit FIFO DMA
9747  *
9748  * channel.
9749  *
9750  * 0 = Transmit DMA disabled
9751  *
9752  * 1 = Transmit DMA enabled
9753  *
9754  * Reset value: 0x0
9755  *
9756  * Field Enumeration Values:
9757  *
9758  * Enum | Value | Description
9759  * :-----------------------------------|:------|:-----------------------------------
9760  * ALT_I2C_IC_DMA_CR_TDMAE_E_DISABLED | 0x0 | transmit FIFO DMA channel disabled
9761  * ALT_I2C_IC_DMA_CR_TDMAE_E_ENABLED | 0x1 | Transmit FIFO DMA channel enabled
9762  *
9763  * Field Access Macros:
9764  *
9765  */
9766 /*
9767  * Enumerated value for register field ALT_I2C_IC_DMA_CR_TDMAE
9768  *
9769  * transmit FIFO DMA channel disabled
9770  */
9771 #define ALT_I2C_IC_DMA_CR_TDMAE_E_DISABLED 0x0
9772 /*
9773  * Enumerated value for register field ALT_I2C_IC_DMA_CR_TDMAE
9774  *
9775  * Transmit FIFO DMA channel enabled
9776  */
9777 #define ALT_I2C_IC_DMA_CR_TDMAE_E_ENABLED 0x1
9778 
9779 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_DMA_CR_TDMAE register field. */
9780 #define ALT_I2C_IC_DMA_CR_TDMAE_LSB 1
9781 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_DMA_CR_TDMAE register field. */
9782 #define ALT_I2C_IC_DMA_CR_TDMAE_MSB 1
9783 /* The width in bits of the ALT_I2C_IC_DMA_CR_TDMAE register field. */
9784 #define ALT_I2C_IC_DMA_CR_TDMAE_WIDTH 1
9785 /* The mask used to set the ALT_I2C_IC_DMA_CR_TDMAE register field value. */
9786 #define ALT_I2C_IC_DMA_CR_TDMAE_SET_MSK 0x00000002
9787 /* The mask used to clear the ALT_I2C_IC_DMA_CR_TDMAE register field value. */
9788 #define ALT_I2C_IC_DMA_CR_TDMAE_CLR_MSK 0xfffffffd
9789 /* The reset value of the ALT_I2C_IC_DMA_CR_TDMAE register field. */
9790 #define ALT_I2C_IC_DMA_CR_TDMAE_RESET 0x0
9791 /* Extracts the ALT_I2C_IC_DMA_CR_TDMAE field value from a register. */
9792 #define ALT_I2C_IC_DMA_CR_TDMAE_GET(value) (((value) & 0x00000002) >> 1)
9793 /* Produces a ALT_I2C_IC_DMA_CR_TDMAE register field value suitable for setting the register. */
9794 #define ALT_I2C_IC_DMA_CR_TDMAE_SET(value) (((value) << 1) & 0x00000002)
9795 
9796 /*
9797  * Field : RSVD_IC_DMA_CR_2_31
9798  *
9799  * Reserved bits [31:1] - Read Only
9800  *
9801  * Field Access Macros:
9802  *
9803  */
9804 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31 register field. */
9805 #define ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31_LSB 2
9806 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31 register field. */
9807 #define ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31_MSB 31
9808 /* The width in bits of the ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31 register field. */
9809 #define ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31_WIDTH 30
9810 /* The mask used to set the ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31 register field value. */
9811 #define ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31_SET_MSK 0xfffffffc
9812 /* The mask used to clear the ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31 register field value. */
9813 #define ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31_CLR_MSK 0x00000003
9814 /* The reset value of the ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31 register field. */
9815 #define ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31_RESET 0x0
9816 /* Extracts the ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31 field value from a register. */
9817 #define ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31_GET(value) (((value) & 0xfffffffc) >> 2)
9818 /* Produces a ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31 register field value suitable for setting the register. */
9819 #define ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31_SET(value) (((value) << 2) & 0xfffffffc)
9820 
9821 #ifndef __ASSEMBLY__
9822 /*
9823  * WARNING: The C register and register group struct declarations are provided for
9824  * convenience and illustrative purposes. They should, however, be used with
9825  * caution as the C language standard provides no guarantees about the alignment or
9826  * atomicity of device memory accesses. The recommended practice for coding device
9827  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9828  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9829  * alt_write_dword() functions for 64 bit registers.
9830  *
9831  * The struct declaration for register ALT_I2C_IC_DMA_CR.
9832  */
9833 struct ALT_I2C_IC_DMA_CR_s
9834 {
9835  volatile uint32_t RDMAE : 1; /* ALT_I2C_IC_DMA_CR_RDMAE */
9836  volatile uint32_t TDMAE : 1; /* ALT_I2C_IC_DMA_CR_TDMAE */
9837  const volatile uint32_t RSVD_IC_DMA_CR_2_31 : 30; /* ALT_I2C_IC_DMA_CR_RSVD_IC_DMA_CR_2_31 */
9838 };
9839 
9840 /* The typedef declaration for register ALT_I2C_IC_DMA_CR. */
9841 typedef struct ALT_I2C_IC_DMA_CR_s ALT_I2C_IC_DMA_CR_t;
9842 #endif /* __ASSEMBLY__ */
9843 
9844 /* The reset value of the ALT_I2C_IC_DMA_CR register. */
9845 #define ALT_I2C_IC_DMA_CR_RESET 0x00000000
9846 /* The byte offset of the ALT_I2C_IC_DMA_CR register from the beginning of the component. */
9847 #define ALT_I2C_IC_DMA_CR_OFST 0x88
9848 /* The address of the ALT_I2C_IC_DMA_CR register. */
9849 #define ALT_I2C_IC_DMA_CR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_DMA_CR_OFST))
9850 
9851 /*
9852  * Register : DMA Transmit Data Level Register - IC_DMA_TDLR
9853  *
9854  * Name: DMA Transmit Data Level Register
9855  *
9856  * Size: log2(IC_TX_BUFFER_DEPTH) bits
9857  *
9858  * Address Offset: 0x8c
9859  *
9860  * Read/Write Access: Read/Write
9861  *
9862  * This register is only valid when the DW_apb_i2c
9863  *
9864  * is configured with a set of DMA interface signals
9865  *
9866  * (IC_HAS_DMA = 1). When DW_apb_i2c is not configured
9867  *
9868  * for DMA operation, this register does not exist;
9869  *
9870  * writing to its address has no effect; reading from
9871  *
9872  * its address returns zero.
9873  *
9874  * Register Layout
9875  *
9876  * Bits | Access | Reset | Description
9877  * :-------|:-------|:------|:----------------------------------
9878  * [5:0] | RW | 0x0 | ALT_I2C_IC_DMA_TDLR_DMATDL
9879  * [31:6] | R | 0x0 | ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR
9880  *
9881  */
9882 /*
9883  * Field : DMATDL
9884  *
9885  * Transmit Data Level.
9886  *
9887  * This bit field controls the level at which a
9888  *
9889  * DMA request is made by the transmit logic. It
9890  *
9891  * is equal to the watermark level; that is, the
9892  *
9893  * dma_tx_req signal is generated when the number
9894  *
9895  * of valid data entries in the transmit FIFO is
9896  *
9897  * equal to or below this field value, and TDMAE = 1.
9898  *
9899  * Reset value: 0x0
9900  *
9901  * Field Access Macros:
9902  *
9903  */
9904 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_DMA_TDLR_DMATDL register field. */
9905 #define ALT_I2C_IC_DMA_TDLR_DMATDL_LSB 0
9906 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_DMA_TDLR_DMATDL register field. */
9907 #define ALT_I2C_IC_DMA_TDLR_DMATDL_MSB 5
9908 /* The width in bits of the ALT_I2C_IC_DMA_TDLR_DMATDL register field. */
9909 #define ALT_I2C_IC_DMA_TDLR_DMATDL_WIDTH 6
9910 /* The mask used to set the ALT_I2C_IC_DMA_TDLR_DMATDL register field value. */
9911 #define ALT_I2C_IC_DMA_TDLR_DMATDL_SET_MSK 0x0000003f
9912 /* The mask used to clear the ALT_I2C_IC_DMA_TDLR_DMATDL register field value. */
9913 #define ALT_I2C_IC_DMA_TDLR_DMATDL_CLR_MSK 0xffffffc0
9914 /* The reset value of the ALT_I2C_IC_DMA_TDLR_DMATDL register field. */
9915 #define ALT_I2C_IC_DMA_TDLR_DMATDL_RESET 0x0
9916 /* Extracts the ALT_I2C_IC_DMA_TDLR_DMATDL field value from a register. */
9917 #define ALT_I2C_IC_DMA_TDLR_DMATDL_GET(value) (((value) & 0x0000003f) >> 0)
9918 /* Produces a ALT_I2C_IC_DMA_TDLR_DMATDL register field value suitable for setting the register. */
9919 #define ALT_I2C_IC_DMA_TDLR_DMATDL_SET(value) (((value) << 0) & 0x0000003f)
9920 
9921 /*
9922  * Field : RSVD_DMA_TDLR
9923  *
9924  * Reserved bits - Read Only
9925  *
9926  * Field Access Macros:
9927  *
9928  */
9929 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR register field. */
9930 #define ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR_LSB 6
9931 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR register field. */
9932 #define ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR_MSB 31
9933 /* The width in bits of the ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR register field. */
9934 #define ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR_WIDTH 26
9935 /* The mask used to set the ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR register field value. */
9936 #define ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR_SET_MSK 0xffffffc0
9937 /* The mask used to clear the ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR register field value. */
9938 #define ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR_CLR_MSK 0x0000003f
9939 /* The reset value of the ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR register field. */
9940 #define ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR_RESET 0x0
9941 /* Extracts the ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR field value from a register. */
9942 #define ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR_GET(value) (((value) & 0xffffffc0) >> 6)
9943 /* Produces a ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR register field value suitable for setting the register. */
9944 #define ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR_SET(value) (((value) << 6) & 0xffffffc0)
9945 
9946 #ifndef __ASSEMBLY__
9947 /*
9948  * WARNING: The C register and register group struct declarations are provided for
9949  * convenience and illustrative purposes. They should, however, be used with
9950  * caution as the C language standard provides no guarantees about the alignment or
9951  * atomicity of device memory accesses. The recommended practice for coding device
9952  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9953  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9954  * alt_write_dword() functions for 64 bit registers.
9955  *
9956  * The struct declaration for register ALT_I2C_IC_DMA_TDLR.
9957  */
9958 struct ALT_I2C_IC_DMA_TDLR_s
9959 {
9960  volatile uint32_t DMATDL : 6; /* ALT_I2C_IC_DMA_TDLR_DMATDL */
9961  const volatile uint32_t RSVD_DMA_TDLR : 26; /* ALT_I2C_IC_DMA_TDLR_RSVD_DMA_TDLR */
9962 };
9963 
9964 /* The typedef declaration for register ALT_I2C_IC_DMA_TDLR. */
9965 typedef struct ALT_I2C_IC_DMA_TDLR_s ALT_I2C_IC_DMA_TDLR_t;
9966 #endif /* __ASSEMBLY__ */
9967 
9968 /* The reset value of the ALT_I2C_IC_DMA_TDLR register. */
9969 #define ALT_I2C_IC_DMA_TDLR_RESET 0x00000000
9970 /* The byte offset of the ALT_I2C_IC_DMA_TDLR register from the beginning of the component. */
9971 #define ALT_I2C_IC_DMA_TDLR_OFST 0x8c
9972 /* The address of the ALT_I2C_IC_DMA_TDLR register. */
9973 #define ALT_I2C_IC_DMA_TDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_DMA_TDLR_OFST))
9974 
9975 /*
9976  * Register : DMA Transmit Data Level Register - IC_DMA_RDLR
9977  *
9978  * Name: I2C Receive Data Level Register
9979  *
9980  * Size: log2(IC_RX_BUFFER_DEPTH) bits
9981  *
9982  * Address Offset: 0x90
9983  *
9984  * Read/Write Access: Read/Write
9985  *
9986  * This register is only valid when DW_apb_i2c
9987  *
9988  * is configured with a set of DMA interface signals
9989  *
9990  * (IC_HAS_DMA = 1). When DW_apb_i2c is not configured
9991  *
9992  * for DMA operation, this register does not exist;
9993  *
9994  * writing to its address has no effect; reading from
9995  *
9996  * its address returns zero.
9997  *
9998  * Register Layout
9999  *
10000  * Bits | Access | Reset | Description
10001  * :-------|:-------|:------|:----------------------------------
10002  * [5:0] | RW | 0x0 | ALT_I2C_IC_DMA_RDLR_DMARDL
10003  * [31:6] | R | 0x0 | ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR
10004  *
10005  */
10006 /*
10007  * Field : DMARDL
10008  *
10009  * Receive Data Level.
10010  *
10011  * This bit field controls the level at which a DMA
10012  *
10013  * request is made by the receive logic. The watermark level =
10014  *
10015  * DMARDL+1; that is, dma_rx_req is generated when the number
10016  *
10017  * of valid data entries in the receive FIFO is equal to or more
10018  *
10019  * than this field value + 1, and RDMAE =1. For instance, when
10020  *
10021  * DMARDL is 0, then dma_rx_req is asserted when 1 or more data
10022  *
10023  * entries are present in the receive FIFO.
10024  *
10025  * Reset value: 0x0
10026  *
10027  * Field Access Macros:
10028  *
10029  */
10030 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_DMA_RDLR_DMARDL register field. */
10031 #define ALT_I2C_IC_DMA_RDLR_DMARDL_LSB 0
10032 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_DMA_RDLR_DMARDL register field. */
10033 #define ALT_I2C_IC_DMA_RDLR_DMARDL_MSB 5
10034 /* The width in bits of the ALT_I2C_IC_DMA_RDLR_DMARDL register field. */
10035 #define ALT_I2C_IC_DMA_RDLR_DMARDL_WIDTH 6
10036 /* The mask used to set the ALT_I2C_IC_DMA_RDLR_DMARDL register field value. */
10037 #define ALT_I2C_IC_DMA_RDLR_DMARDL_SET_MSK 0x0000003f
10038 /* The mask used to clear the ALT_I2C_IC_DMA_RDLR_DMARDL register field value. */
10039 #define ALT_I2C_IC_DMA_RDLR_DMARDL_CLR_MSK 0xffffffc0
10040 /* The reset value of the ALT_I2C_IC_DMA_RDLR_DMARDL register field. */
10041 #define ALT_I2C_IC_DMA_RDLR_DMARDL_RESET 0x0
10042 /* Extracts the ALT_I2C_IC_DMA_RDLR_DMARDL field value from a register. */
10043 #define ALT_I2C_IC_DMA_RDLR_DMARDL_GET(value) (((value) & 0x0000003f) >> 0)
10044 /* Produces a ALT_I2C_IC_DMA_RDLR_DMARDL register field value suitable for setting the register. */
10045 #define ALT_I2C_IC_DMA_RDLR_DMARDL_SET(value) (((value) << 0) & 0x0000003f)
10046 
10047 /*
10048  * Field : RSVD_DMA_RDLR
10049  *
10050  * Reserved bits - Read Only
10051  *
10052  * Field Access Macros:
10053  *
10054  */
10055 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR register field. */
10056 #define ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR_LSB 6
10057 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR register field. */
10058 #define ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR_MSB 31
10059 /* The width in bits of the ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR register field. */
10060 #define ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR_WIDTH 26
10061 /* The mask used to set the ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR register field value. */
10062 #define ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR_SET_MSK 0xffffffc0
10063 /* The mask used to clear the ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR register field value. */
10064 #define ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR_CLR_MSK 0x0000003f
10065 /* The reset value of the ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR register field. */
10066 #define ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR_RESET 0x0
10067 /* Extracts the ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR field value from a register. */
10068 #define ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR_GET(value) (((value) & 0xffffffc0) >> 6)
10069 /* Produces a ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR register field value suitable for setting the register. */
10070 #define ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR_SET(value) (((value) << 6) & 0xffffffc0)
10071 
10072 #ifndef __ASSEMBLY__
10073 /*
10074  * WARNING: The C register and register group struct declarations are provided for
10075  * convenience and illustrative purposes. They should, however, be used with
10076  * caution as the C language standard provides no guarantees about the alignment or
10077  * atomicity of device memory accesses. The recommended practice for coding device
10078  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10079  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10080  * alt_write_dword() functions for 64 bit registers.
10081  *
10082  * The struct declaration for register ALT_I2C_IC_DMA_RDLR.
10083  */
10084 struct ALT_I2C_IC_DMA_RDLR_s
10085 {
10086  volatile uint32_t DMARDL : 6; /* ALT_I2C_IC_DMA_RDLR_DMARDL */
10087  const volatile uint32_t RSVD_DMA_RDLR : 26; /* ALT_I2C_IC_DMA_RDLR_RSVD_DMA_RDLR */
10088 };
10089 
10090 /* The typedef declaration for register ALT_I2C_IC_DMA_RDLR. */
10091 typedef struct ALT_I2C_IC_DMA_RDLR_s ALT_I2C_IC_DMA_RDLR_t;
10092 #endif /* __ASSEMBLY__ */
10093 
10094 /* The reset value of the ALT_I2C_IC_DMA_RDLR register. */
10095 #define ALT_I2C_IC_DMA_RDLR_RESET 0x00000000
10096 /* The byte offset of the ALT_I2C_IC_DMA_RDLR register from the beginning of the component. */
10097 #define ALT_I2C_IC_DMA_RDLR_OFST 0x90
10098 /* The address of the ALT_I2C_IC_DMA_RDLR register. */
10099 #define ALT_I2C_IC_DMA_RDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_DMA_RDLR_OFST))
10100 
10101 /*
10102  * Register : I2C SDA Setup Register - IC_SDA_SETUP
10103  *
10104  * Name: I2C SDA Setup Register
10105  *
10106  * Size: 8 bits
10107  *
10108  * Address Offset: 0x94
10109  *
10110  * Read/Write Access: Read/Write
10111  *
10112  * This register controls the amount of time delay
10113  *
10114  * (in terms of number of ic_clk clock periods) introduced
10115  *
10116  * in the rising edge of SCL, relative to SDA changing, when
10117  *
10118  * DW_apb_i2c services a read request in a slave-transmitter operation.
10119  *
10120  * The relevant I2C requirement is tSU:DAT (note 4) as detailed in the
10121  *
10122  * I2C Bus Specification.
10123  *
10124  * Dependencies: This register is not applicable when IC_ULTRA_FAST_MODE=1
10125  *
10126  * Register Layout
10127  *
10128  * Bits | Access | Reset | Description
10129  * :-------|:-------|:------|:---------------------------------------
10130  * [7:0] | RW | 0x64 | ALT_I2C_IC_SDA_SETUP_SDA_SETUP
10131  * [31:8] | R | 0x0 | ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP
10132  *
10133  */
10134 /*
10135  * Field : SDA_SETUP
10136  *
10137  * SDA Setup.
10138  *
10139  * It is recommended that if the required delay is 1000ns,
10140  *
10141  * then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP
10142  *
10143  * should be programmed to a value of 11.
10144  *
10145  * Default Reset value: 0x64, but can be hardcoded by setting
10146  *
10147  * the IC_DEFAULT_SDA_SETUP configuration parameter.
10148  *
10149  * Field Access Macros:
10150  *
10151  */
10152 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_SDA_SETUP_SDA_SETUP register field. */
10153 #define ALT_I2C_IC_SDA_SETUP_SDA_SETUP_LSB 0
10154 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_SDA_SETUP_SDA_SETUP register field. */
10155 #define ALT_I2C_IC_SDA_SETUP_SDA_SETUP_MSB 7
10156 /* The width in bits of the ALT_I2C_IC_SDA_SETUP_SDA_SETUP register field. */
10157 #define ALT_I2C_IC_SDA_SETUP_SDA_SETUP_WIDTH 8
10158 /* The mask used to set the ALT_I2C_IC_SDA_SETUP_SDA_SETUP register field value. */
10159 #define ALT_I2C_IC_SDA_SETUP_SDA_SETUP_SET_MSK 0x000000ff
10160 /* The mask used to clear the ALT_I2C_IC_SDA_SETUP_SDA_SETUP register field value. */
10161 #define ALT_I2C_IC_SDA_SETUP_SDA_SETUP_CLR_MSK 0xffffff00
10162 /* The reset value of the ALT_I2C_IC_SDA_SETUP_SDA_SETUP register field. */
10163 #define ALT_I2C_IC_SDA_SETUP_SDA_SETUP_RESET 0x64
10164 /* Extracts the ALT_I2C_IC_SDA_SETUP_SDA_SETUP field value from a register. */
10165 #define ALT_I2C_IC_SDA_SETUP_SDA_SETUP_GET(value) (((value) & 0x000000ff) >> 0)
10166 /* Produces a ALT_I2C_IC_SDA_SETUP_SDA_SETUP register field value suitable for setting the register. */
10167 #define ALT_I2C_IC_SDA_SETUP_SDA_SETUP_SET(value) (((value) << 0) & 0x000000ff)
10168 
10169 /*
10170  * Field : RSVD_IC_SDA_SETUP
10171  *
10172  * Reserved bits - Read Only
10173  *
10174  * Field Access Macros:
10175  *
10176  */
10177 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP register field. */
10178 #define ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP_LSB 8
10179 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP register field. */
10180 #define ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP_MSB 31
10181 /* The width in bits of the ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP register field. */
10182 #define ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP_WIDTH 24
10183 /* The mask used to set the ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP register field value. */
10184 #define ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP_SET_MSK 0xffffff00
10185 /* The mask used to clear the ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP register field value. */
10186 #define ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP_CLR_MSK 0x000000ff
10187 /* The reset value of the ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP register field. */
10188 #define ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP_RESET 0x0
10189 /* Extracts the ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP field value from a register. */
10190 #define ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP_GET(value) (((value) & 0xffffff00) >> 8)
10191 /* Produces a ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP register field value suitable for setting the register. */
10192 #define ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP_SET(value) (((value) << 8) & 0xffffff00)
10193 
10194 #ifndef __ASSEMBLY__
10195 /*
10196  * WARNING: The C register and register group struct declarations are provided for
10197  * convenience and illustrative purposes. They should, however, be used with
10198  * caution as the C language standard provides no guarantees about the alignment or
10199  * atomicity of device memory accesses. The recommended practice for coding device
10200  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10201  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10202  * alt_write_dword() functions for 64 bit registers.
10203  *
10204  * The struct declaration for register ALT_I2C_IC_SDA_SETUP.
10205  */
10206 struct ALT_I2C_IC_SDA_SETUP_s
10207 {
10208  volatile uint32_t SDA_SETUP : 8; /* ALT_I2C_IC_SDA_SETUP_SDA_SETUP */
10209  const volatile uint32_t RSVD_IC_SDA_SETUP : 24; /* ALT_I2C_IC_SDA_SETUP_RSVD_IC_SDA_SETUP */
10210 };
10211 
10212 /* The typedef declaration for register ALT_I2C_IC_SDA_SETUP. */
10213 typedef struct ALT_I2C_IC_SDA_SETUP_s ALT_I2C_IC_SDA_SETUP_t;
10214 #endif /* __ASSEMBLY__ */
10215 
10216 /* The reset value of the ALT_I2C_IC_SDA_SETUP register. */
10217 #define ALT_I2C_IC_SDA_SETUP_RESET 0x00000064
10218 /* The byte offset of the ALT_I2C_IC_SDA_SETUP register from the beginning of the component. */
10219 #define ALT_I2C_IC_SDA_SETUP_OFST 0x94
10220 /* The address of the ALT_I2C_IC_SDA_SETUP register. */
10221 #define ALT_I2C_IC_SDA_SETUP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_SDA_SETUP_OFST))
10222 
10223 /*
10224  * Register : I2C ACK General Call Register - IC_ACK_GENERAL_CALL
10225  *
10226  * Name: I2C ACK General Call Register
10227  *
10228  * Size: 1 bit
10229  *
10230  * Address Offset: 0x98
10231  *
10232  * Read/Write Access: Read/Write
10233  *
10234  * The register controls whether DW_apb_i2c responds
10235  *
10236  * with a ACK or NACK when it receives an I2C
10237  *
10238  * General Call address.
10239  *
10240  * Note :This register is applicable only when the DW_apb_i2c is in slave mode
10241  *
10242  * Dependencies: This register is not applicable when IC_ULTRA_FAST_MODE=1
10243  *
10244  * Register Layout
10245  *
10246  * Bits | Access | Reset | Description
10247  * :-------|:-------|:------|:-------------------------------------------------
10248  * [0] | RW | 0x1 | ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL
10249  * [31:1] | R | 0x0 | ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31
10250  *
10251  */
10252 /*
10253  * Field : ACK_GEN_CALL
10254  *
10255  * ACK General Call.
10256  *
10257  * When set to 1, DW_apb_i2c responds with a ACK
10258  *
10259  * (by asserting ic_data_oe) when it receives a General Call.
10260  *
10261  * Otherwise, DW_apb_i2c responds with a NACK
10262  *
10263  * (by negating ic_data_oe).
10264  *
10265  * Default Reset value: 0x1, but can be hardcoded by setting the
10266  *
10267  * IC_DEFAULT_ACK_GENERAL_CALL configuration parameter.
10268  *
10269  * Field Enumeration Values:
10270  *
10271  * Enum | Value | Description
10272  * :----------------------------------------------------|:------|:--------------------------------
10273  * ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_E_DISABLED | 0x0 | Generate NACK for General Call
10274  * ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ENABLED | 0x1 | Generate ACK for a General Call
10275  *
10276  * Field Access Macros:
10277  *
10278  */
10279 /*
10280  * Enumerated value for register field ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL
10281  *
10282  * Generate NACK for General Call
10283  */
10284 #define ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_E_DISABLED 0x0
10285 /*
10286  * Enumerated value for register field ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL
10287  *
10288  * Generate ACK for a General Call
10289  */
10290 #define ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ENABLED 0x1
10291 
10292 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */
10293 #define ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB 0
10294 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */
10295 #define ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB 0
10296 /* The width in bits of the ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */
10297 #define ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_WIDTH 1
10298 /* The mask used to set the ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL register field value. */
10299 #define ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_SET_MSK 0x00000001
10300 /* The mask used to clear the ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL register field value. */
10301 #define ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_CLR_MSK 0xfffffffe
10302 /* The reset value of the ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */
10303 #define ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET 0x1
10304 /* Extracts the ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL field value from a register. */
10305 #define ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0)
10306 /* Produces a ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL register field value suitable for setting the register. */
10307 #define ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_SET(value) (((value) << 0) & 0x00000001)
10308 
10309 /*
10310  * Field : RSVD_IC_ACK_GEN_1_31
10311  *
10312  * Reserved bits [31:1] - Read Only
10313  *
10314  * Field Access Macros:
10315  *
10316  */
10317 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31 register field. */
10318 #define ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31_LSB 1
10319 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31 register field. */
10320 #define ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31_MSB 31
10321 /* The width in bits of the ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31 register field. */
10322 #define ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31_WIDTH 31
10323 /* The mask used to set the ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31 register field value. */
10324 #define ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31_SET_MSK 0xfffffffe
10325 /* The mask used to clear the ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31 register field value. */
10326 #define ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31_CLR_MSK 0x00000001
10327 /* The reset value of the ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31 register field. */
10328 #define ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31_RESET 0x0
10329 /* Extracts the ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31 field value from a register. */
10330 #define ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31_GET(value) (((value) & 0xfffffffe) >> 1)
10331 /* Produces a ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31 register field value suitable for setting the register. */
10332 #define ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31_SET(value) (((value) << 1) & 0xfffffffe)
10333 
10334 #ifndef __ASSEMBLY__
10335 /*
10336  * WARNING: The C register and register group struct declarations are provided for
10337  * convenience and illustrative purposes. They should, however, be used with
10338  * caution as the C language standard provides no guarantees about the alignment or
10339  * atomicity of device memory accesses. The recommended practice for coding device
10340  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10341  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10342  * alt_write_dword() functions for 64 bit registers.
10343  *
10344  * The struct declaration for register ALT_I2C_IC_ACK_GENERAL_CALL.
10345  */
10346 struct ALT_I2C_IC_ACK_GENERAL_CALL_s
10347 {
10348  volatile uint32_t ACK_GEN_CALL : 1; /* ALT_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL */
10349  const volatile uint32_t RSVD_IC_ACK_GEN_1_31 : 31; /* ALT_I2C_IC_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_1_31 */
10350 };
10351 
10352 /* The typedef declaration for register ALT_I2C_IC_ACK_GENERAL_CALL. */
10353 typedef struct ALT_I2C_IC_ACK_GENERAL_CALL_s ALT_I2C_IC_ACK_GENERAL_CALL_t;
10354 #endif /* __ASSEMBLY__ */
10355 
10356 /* The reset value of the ALT_I2C_IC_ACK_GENERAL_CALL register. */
10357 #define ALT_I2C_IC_ACK_GENERAL_CALL_RESET 0x00000001
10358 /* The byte offset of the ALT_I2C_IC_ACK_GENERAL_CALL register from the beginning of the component. */
10359 #define ALT_I2C_IC_ACK_GENERAL_CALL_OFST 0x98
10360 /* The address of the ALT_I2C_IC_ACK_GENERAL_CALL register. */
10361 #define ALT_I2C_IC_ACK_GENERAL_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_ACK_GENERAL_CALL_OFST))
10362 
10363 /*
10364  * Register : I2C Enable Status Register - IC_ENABLE_STATUS
10365  *
10366  * Name: I2C Enable Status Register
10367  *
10368  * Size: 3 bits
10369  *
10370  * Address Offset: 0x9C
10371  *
10372  * Read/Write Access: Read
10373  *
10374  * The register is used to report the DW_apb_i2c hardware
10375  *
10376  * status when the IC_ENABLE[0] register is set from 1 to 0;
10377  *
10378  * that is, when DW_apb_i2c is disabled.
10379  *
10380  * If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0,
10381  *
10382  * and bit 0 is forced to 1.
10383  *
10384  * If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid
10385  *
10386  * as soon as bit 0 is read as '0'.
10387  *
10388  * Note
10389  *
10390  * When IC_ENABLE[0] has been written with '0'a delay occurs for
10391  *
10392  * bit 0 to be read as '0' because disabling the DW_apb_i2c
10393  *
10394  * depends on I2C bus activities.
10395  *
10396  * Register Layout
10397  *
10398  * Bits | Access | Reset | Description
10399  * :-------|:-------|:------|:-------------------------------------------------
10400  * [0] | R | 0x0 | ALT_I2C_IC_ENABLE_STATUS_IC_EN
10401  * [1] | R | 0x0 | ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY
10402  * [2] | R | 0x0 | ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST
10403  * [31:3] | R | 0x0 | ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS
10404  *
10405  */
10406 /*
10407  * Field : IC_EN
10408  *
10409  * ic_en Status.
10410  *
10411  * This bit always reflects the value driven
10412  *
10413  * on the output port ic_en.
10414  *
10415  * When read as 1, DW_apb_i2c is deemed to be in
10416  *
10417  * an enabled state.
10418  *
10419  * When read as 0, DW_apb_i2c is deemed completely
10420  *
10421  * inactive.
10422  *
10423  * NOTE: The CPU can safely read this bit anytime.
10424  *
10425  * When this bit is read as 0, the CPU can safely
10426  *
10427  * read SLV_RX_DATA_LOST (bit 2) and
10428  *
10429  * SLV_DISABLED_WHILE_BUSY (bit 1).
10430  *
10431  * Reset value: 0x0
10432  *
10433  * Field Enumeration Values:
10434  *
10435  * Enum | Value | Description
10436  * :------------------------------------------|:------|:-------------
10437  * ALT_I2C_IC_ENABLE_STATUS_IC_EN_E_DISABLED | 0x0 | I2C disabled
10438  * ALT_I2C_IC_ENABLE_STATUS_IC_EN_E_ENABLED | 0x1 | I2C enabled
10439  *
10440  * Field Access Macros:
10441  *
10442  */
10443 /*
10444  * Enumerated value for register field ALT_I2C_IC_ENABLE_STATUS_IC_EN
10445  *
10446  * I2C disabled
10447  */
10448 #define ALT_I2C_IC_ENABLE_STATUS_IC_EN_E_DISABLED 0x0
10449 /*
10450  * Enumerated value for register field ALT_I2C_IC_ENABLE_STATUS_IC_EN
10451  *
10452  * I2C enabled
10453  */
10454 #define ALT_I2C_IC_ENABLE_STATUS_IC_EN_E_ENABLED 0x1
10455 
10456 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_ENABLE_STATUS_IC_EN register field. */
10457 #define ALT_I2C_IC_ENABLE_STATUS_IC_EN_LSB 0
10458 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_ENABLE_STATUS_IC_EN register field. */
10459 #define ALT_I2C_IC_ENABLE_STATUS_IC_EN_MSB 0
10460 /* The width in bits of the ALT_I2C_IC_ENABLE_STATUS_IC_EN register field. */
10461 #define ALT_I2C_IC_ENABLE_STATUS_IC_EN_WIDTH 1
10462 /* The mask used to set the ALT_I2C_IC_ENABLE_STATUS_IC_EN register field value. */
10463 #define ALT_I2C_IC_ENABLE_STATUS_IC_EN_SET_MSK 0x00000001
10464 /* The mask used to clear the ALT_I2C_IC_ENABLE_STATUS_IC_EN register field value. */
10465 #define ALT_I2C_IC_ENABLE_STATUS_IC_EN_CLR_MSK 0xfffffffe
10466 /* The reset value of the ALT_I2C_IC_ENABLE_STATUS_IC_EN register field. */
10467 #define ALT_I2C_IC_ENABLE_STATUS_IC_EN_RESET 0x0
10468 /* Extracts the ALT_I2C_IC_ENABLE_STATUS_IC_EN field value from a register. */
10469 #define ALT_I2C_IC_ENABLE_STATUS_IC_EN_GET(value) (((value) & 0x00000001) >> 0)
10470 /* Produces a ALT_I2C_IC_ENABLE_STATUS_IC_EN register field value suitable for setting the register. */
10471 #define ALT_I2C_IC_ENABLE_STATUS_IC_EN_SET(value) (((value) << 0) & 0x00000001)
10472 
10473 /*
10474  * Field : SLV_DISABLED_WHILE_BUSY
10475  *
10476  * Slave Disabled While Busy (Transmit, Receive).
10477  *
10478  * This bit indicates if a potential or active Slave
10479  *
10480  * operation has been aborted due to the setting bit 0 of
10481  *
10482  * the IC_ENABLE register from 1 to 0. This bit is set
10483  *
10484  * when the CPU writes a 0 to the IC_ENABLE register
10485  *
10486  * while: (a) DW_apb_i2c is receiving the address byte
10487  *
10488  * of the Slave-Transmitter operation from a remote master;
10489  *
10490  * OR, (b) address and data bytes of the Slave-Receiver
10491  *
10492  * operation from a remote master.
10493  *
10494  * When read as 1, DW_apb_i2c is deemed to have forced a
10495  *
10496  * NACK during any part of an I2C transfer, irrespective
10497  *
10498  * of whether the I2C address matches the slave address set
10499  *
10500  * in DW_apb_i2c (IC_SAR register) OR if the transfer is
10501  *
10502  * completed before IC_ENABLE is set to 0 but has not
10503  *
10504  * taken effect.
10505  *
10506  * NOTE: If the remote I2C master terminates the transfer
10507  *
10508  * with a STOP condition before the DW_apb_i2c has a chance
10509  *
10510  * to NACK a transfer, and IC_ENABLE[0] has been set to 0, then
10511  *
10512  * this bit will also be set to 1.
10513  *
10514  * When read as 0, DW_apb_i2c is deemed to have been disabled
10515  *
10516  * when there is master activity, or when the I2C bus is idle.
10517  *
10518  * NOTE: The CPU can safely read this bit when IC_EN (bit 0)
10519  *
10520  * is read as 0.
10521  *
10522  * Reset value: 0x0
10523  *
10524  * Field Enumeration Values:
10525  *
10526  * Enum | Value | Description
10527  * :------------------------------------------------------------|:------|:------------------------------------
10528  * ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_E_INACTIVE | 0x0 | Slave is disabled when it is idle
10529  * ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_E_ACTIVE | 0x1 | Slave is disabled when it is active
10530  *
10531  * Field Access Macros:
10532  *
10533  */
10534 /*
10535  * Enumerated value for register field ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY
10536  *
10537  * Slave is disabled when it is idle
10538  */
10539 #define ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_E_INACTIVE 0x0
10540 /*
10541  * Enumerated value for register field ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY
10542  *
10543  * Slave is disabled when it is active
10544  */
10545 #define ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_E_ACTIVE 0x1
10546 
10547 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY register field. */
10548 #define ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_LSB 1
10549 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY register field. */
10550 #define ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MSB 1
10551 /* The width in bits of the ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY register field. */
10552 #define ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_WIDTH 1
10553 /* The mask used to set the ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY register field value. */
10554 #define ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_SET_MSK 0x00000002
10555 /* The mask used to clear the ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY register field value. */
10556 #define ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_CLR_MSK 0xfffffffd
10557 /* The reset value of the ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY register field. */
10558 #define ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_RESET 0x0
10559 /* Extracts the ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY field value from a register. */
10560 #define ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_GET(value) (((value) & 0x00000002) >> 1)
10561 /* Produces a ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY register field value suitable for setting the register. */
10562 #define ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_SET(value) (((value) << 1) & 0x00000002)
10563 
10564 /*
10565  * Field : SLV_RX_DATA_LOST
10566  *
10567  * Slave Received Data Lost.
10568  *
10569  * This bit indicates if a Slave-Receiver operation has been
10570  *
10571  * aborted with at least one data byte received from an
10572  *
10573  * I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0.
10574  *
10575  * When read as 1, DW_apb_i2c is deemed to have been actively engaged
10576  *
10577  * in an aborted I2C transfer (with matching address) and the
10578  *
10579  * data phase of the I2C transfer has been entered, even though
10580  *
10581  * a data byte has been responded with a NACK.
10582  *
10583  * NOTE: If the remote I2C master terminates the transfer with a
10584  *
10585  * STOP condition before the DW_apb_i2c has a chance to NACK a
10586  *
10587  * transfer, and IC_ENABLE[0] has been set to 0, then this bit is
10588  *
10589  * also set to 1.
10590  *
10591  * When read as 0, DW_apb_i2c is deemed to have been disabled without
10592  *
10593  * being actively involved in the data phase of a Slave-Receiver transfer.
10594  *
10595  * NOTE: The CPU can safely read this bit when IC_EN (bit 0) is
10596  *
10597  * read as 0.
10598  *
10599  * Reset value: 0x0
10600  *
10601  * Field Enumeration Values:
10602  *
10603  * Enum | Value | Description
10604  * :-----------------------------------------------------|:------|:--------------------------
10605  * ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_E_INACTIVE | 0x0 | Slave RX Data is not lost
10606  * ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_E_ACTIVE | 0x1 | Slave RX Data is lost
10607  *
10608  * Field Access Macros:
10609  *
10610  */
10611 /*
10612  * Enumerated value for register field ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST
10613  *
10614  * Slave RX Data is not lost
10615  */
10616 #define ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_E_INACTIVE 0x0
10617 /*
10618  * Enumerated value for register field ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST
10619  *
10620  * Slave RX Data is lost
10621  */
10622 #define ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_E_ACTIVE 0x1
10623 
10624 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST register field. */
10625 #define ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_LSB 2
10626 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST register field. */
10627 #define ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MSB 2
10628 /* The width in bits of the ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST register field. */
10629 #define ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_WIDTH 1
10630 /* The mask used to set the ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST register field value. */
10631 #define ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_SET_MSK 0x00000004
10632 /* The mask used to clear the ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST register field value. */
10633 #define ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_CLR_MSK 0xfffffffb
10634 /* The reset value of the ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST register field. */
10635 #define ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_RESET 0x0
10636 /* Extracts the ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST field value from a register. */
10637 #define ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_GET(value) (((value) & 0x00000004) >> 2)
10638 /* Produces a ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST register field value suitable for setting the register. */
10639 #define ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_SET(value) (((value) << 2) & 0x00000004)
10640 
10641 /*
10642  * Field : RSVD_IC_ENABLE_STATUS
10643  *
10644  * Reserved bits - Read Only
10645  *
10646  * Field Access Macros:
10647  *
10648  */
10649 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS register field. */
10650 #define ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS_LSB 3
10651 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS register field. */
10652 #define ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS_MSB 31
10653 /* The width in bits of the ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS register field. */
10654 #define ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS_WIDTH 29
10655 /* The mask used to set the ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS register field value. */
10656 #define ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS_SET_MSK 0xfffffff8
10657 /* The mask used to clear the ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS register field value. */
10658 #define ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS_CLR_MSK 0x00000007
10659 /* The reset value of the ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS register field. */
10660 #define ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS_RESET 0x0
10661 /* Extracts the ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS field value from a register. */
10662 #define ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS_GET(value) (((value) & 0xfffffff8) >> 3)
10663 /* Produces a ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS register field value suitable for setting the register. */
10664 #define ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS_SET(value) (((value) << 3) & 0xfffffff8)
10665 
10666 #ifndef __ASSEMBLY__
10667 /*
10668  * WARNING: The C register and register group struct declarations are provided for
10669  * convenience and illustrative purposes. They should, however, be used with
10670  * caution as the C language standard provides no guarantees about the alignment or
10671  * atomicity of device memory accesses. The recommended practice for coding device
10672  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10673  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10674  * alt_write_dword() functions for 64 bit registers.
10675  *
10676  * The struct declaration for register ALT_I2C_IC_ENABLE_STATUS.
10677  */
10678 struct ALT_I2C_IC_ENABLE_STATUS_s
10679 {
10680  const volatile uint32_t IC_EN : 1; /* ALT_I2C_IC_ENABLE_STATUS_IC_EN */
10681  const volatile uint32_t SLV_DISABLED_WHILE_BUSY : 1; /* ALT_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY */
10682  const volatile uint32_t SLV_RX_DATA_LOST : 1; /* ALT_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST */
10683  const volatile uint32_t RSVD_IC_ENABLE_STATUS : 29; /* ALT_I2C_IC_ENABLE_STATUS_RSVD_IC_ENABLE_STATUS */
10684 };
10685 
10686 /* The typedef declaration for register ALT_I2C_IC_ENABLE_STATUS. */
10687 typedef struct ALT_I2C_IC_ENABLE_STATUS_s ALT_I2C_IC_ENABLE_STATUS_t;
10688 #endif /* __ASSEMBLY__ */
10689 
10690 /* The reset value of the ALT_I2C_IC_ENABLE_STATUS register. */
10691 #define ALT_I2C_IC_ENABLE_STATUS_RESET 0x00000000
10692 /* The byte offset of the ALT_I2C_IC_ENABLE_STATUS register from the beginning of the component. */
10693 #define ALT_I2C_IC_ENABLE_STATUS_OFST 0x9c
10694 /* The address of the ALT_I2C_IC_ENABLE_STATUS register. */
10695 #define ALT_I2C_IC_ENABLE_STATUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_ENABLE_STATUS_OFST))
10696 
10697 /*
10698  * Register : I2C SS, FS or FM+ spike suppression limit - IC_FS_SPKLEN
10699  *
10700  * Name: I2C SS, FS or FM+ spike suppression limit
10701  *
10702  * Size: 8 bits
10703  *
10704  * Address: 0xA0
10705  *
10706  * Read/Write Access: Read/Write
10707  *
10708  * This register is used to store the duration, measured in ic_clk cycles,
10709  *
10710  * of the longest spike that is filtered out by the spike suppression logic w
10711  *
10712  * hen the component is operating in SS, FS or FM+ modes.
10713  *
10714  * The relevant I2C requirement is tSP (table 4) as detailed in the
10715  *
10716  * I2C Bus Specification. This register must be programmed with a minimum value of
10717  * 1.
10718  *
10719  * Dependencies: This register is not applicable when IC_ULTRA_FAST_MODE=1
10720  *
10721  * Register Layout
10722  *
10723  * Bits | Access | Reset | Description
10724  * :-------|:-------|:------|:---------------------------------------
10725  * [7:0] | RW | 0x2 | ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN
10726  * [31:8] | R | 0x0 | ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN
10727  *
10728  */
10729 /*
10730  * Field : IC_FS_SPKLEN
10731  *
10732  * This register must be set before any I2C bus transaction can take place to
10733  *
10734  * ensure stable operation. This register sets the duration, measured in ic_clk
10735  * cycles,
10736  *
10737  * of the longest spike in the SCL or SDA lines that will be filtered out by the
10738  * spike
10739  *
10740  * suppression logic.
10741  *
10742  * This register can be written only when the I2C interface is disabled which
10743  *
10744  * corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times
10745  *
10746  * have no effect.
10747  *
10748  * The minimum valid value is 1; hardware prevents values less than this being
10749  *
10750  * written, and if attempted results in 1 being set.
10751  *
10752  * Default Reset value: IC_DEFAULT_FS_SPKLEN configuration parameter.
10753  *
10754  * Field Access Macros:
10755  *
10756  */
10757 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN register field. */
10758 #define ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_LSB 0
10759 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN register field. */
10760 #define ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_MSB 7
10761 /* The width in bits of the ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN register field. */
10762 #define ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_WIDTH 8
10763 /* The mask used to set the ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN register field value. */
10764 #define ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_SET_MSK 0x000000ff
10765 /* The mask used to clear the ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN register field value. */
10766 #define ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_CLR_MSK 0xffffff00
10767 /* The reset value of the ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN register field. */
10768 #define ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_RESET 0x2
10769 /* Extracts the ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN field value from a register. */
10770 #define ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_GET(value) (((value) & 0x000000ff) >> 0)
10771 /* Produces a ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN register field value suitable for setting the register. */
10772 #define ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_SET(value) (((value) << 0) & 0x000000ff)
10773 
10774 /*
10775  * Field : RSVD_IC_FS_SPKLEN
10776  *
10777  * Reserved bits - Read Only
10778  *
10779  * Field Access Macros:
10780  *
10781  */
10782 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN register field. */
10783 #define ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN_LSB 8
10784 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN register field. */
10785 #define ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN_MSB 31
10786 /* The width in bits of the ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN register field. */
10787 #define ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN_WIDTH 24
10788 /* The mask used to set the ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN register field value. */
10789 #define ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN_SET_MSK 0xffffff00
10790 /* The mask used to clear the ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN register field value. */
10791 #define ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN_CLR_MSK 0x000000ff
10792 /* The reset value of the ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN register field. */
10793 #define ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN_RESET 0x0
10794 /* Extracts the ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN field value from a register. */
10795 #define ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN_GET(value) (((value) & 0xffffff00) >> 8)
10796 /* Produces a ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN register field value suitable for setting the register. */
10797 #define ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN_SET(value) (((value) << 8) & 0xffffff00)
10798 
10799 #ifndef __ASSEMBLY__
10800 /*
10801  * WARNING: The C register and register group struct declarations are provided for
10802  * convenience and illustrative purposes. They should, however, be used with
10803  * caution as the C language standard provides no guarantees about the alignment or
10804  * atomicity of device memory accesses. The recommended practice for coding device
10805  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10806  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10807  * alt_write_dword() functions for 64 bit registers.
10808  *
10809  * The struct declaration for register ALT_I2C_IC_FS_SPKLEN.
10810  */
10811 struct ALT_I2C_IC_FS_SPKLEN_s
10812 {
10813  volatile uint32_t IC_FS_SPKLEN : 8; /* ALT_I2C_IC_FS_SPKLEN_IC_FS_SPKLEN */
10814  const volatile uint32_t RSVD_IC_FS_SPKLEN : 24; /* ALT_I2C_IC_FS_SPKLEN_RSVD_IC_FS_SPKLEN */
10815 };
10816 
10817 /* The typedef declaration for register ALT_I2C_IC_FS_SPKLEN. */
10818 typedef struct ALT_I2C_IC_FS_SPKLEN_s ALT_I2C_IC_FS_SPKLEN_t;
10819 #endif /* __ASSEMBLY__ */
10820 
10821 /* The reset value of the ALT_I2C_IC_FS_SPKLEN register. */
10822 #define ALT_I2C_IC_FS_SPKLEN_RESET 0x00000002
10823 /* The byte offset of the ALT_I2C_IC_FS_SPKLEN register from the beginning of the component. */
10824 #define ALT_I2C_IC_FS_SPKLEN_OFST 0xa0
10825 /* The address of the ALT_I2C_IC_FS_SPKLEN register. */
10826 #define ALT_I2C_IC_FS_SPKLEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_FS_SPKLEN_OFST))
10827 
10828 /*
10829  * Register : Clear RESTART_DET Interrupt Register - IC_CLR_RESTART_DET
10830  *
10831  * Name: Clear RESTART_DET Interrupt Register
10832  *
10833  * Size: 1 bit
10834  *
10835  * Address Offset: 0xA8
10836  *
10837  * Read/Write Access: Read
10838  *
10839  * Register Layout
10840  *
10841  * Bits | Access | Reset | Description
10842  * :-------|:-------|:------|:---------------------------------------------------
10843  * [0] | R | 0x0 | ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET
10844  * [31:1] | R | 0x0 | ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET
10845  *
10846  */
10847 /*
10848  * Field : CLR_RESTART_DET
10849  *
10850  * Read this register to clear the RESTART_DET
10851  *
10852  * interrupt (bit 12) of IC_RAW_INTR_STAT register.
10853  *
10854  * Reset value: 0x0
10855  *
10856  * Field Access Macros:
10857  *
10858  */
10859 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET register field. */
10860 #define ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_LSB 0
10861 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET register field. */
10862 #define ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_MSB 0
10863 /* The width in bits of the ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET register field. */
10864 #define ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_WIDTH 1
10865 /* The mask used to set the ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET register field value. */
10866 #define ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_SET_MSK 0x00000001
10867 /* The mask used to clear the ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET register field value. */
10868 #define ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_CLR_MSK 0xfffffffe
10869 /* The reset value of the ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET register field. */
10870 #define ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_RESET 0x0
10871 /* Extracts the ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET field value from a register. */
10872 #define ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_GET(value) (((value) & 0x00000001) >> 0)
10873 /* Produces a ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET register field value suitable for setting the register. */
10874 #define ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_SET(value) (((value) << 0) & 0x00000001)
10875 
10876 /*
10877  * Field : RSVD_IC_CLR_RESTART_DET
10878  *
10879  * Reserved bits - Read Only
10880  *
10881  * Field Access Macros:
10882  *
10883  */
10884 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET register field. */
10885 #define ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET_LSB 1
10886 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET register field. */
10887 #define ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET_MSB 31
10888 /* The width in bits of the ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET register field. */
10889 #define ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET_WIDTH 31
10890 /* The mask used to set the ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET register field value. */
10891 #define ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET_SET_MSK 0xfffffffe
10892 /* The mask used to clear the ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET register field value. */
10893 #define ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET_CLR_MSK 0x00000001
10894 /* The reset value of the ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET register field. */
10895 #define ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET_RESET 0x0
10896 /* Extracts the ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET field value from a register. */
10897 #define ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET_GET(value) (((value) & 0xfffffffe) >> 1)
10898 /* Produces a ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET register field value suitable for setting the register. */
10899 #define ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET_SET(value) (((value) << 1) & 0xfffffffe)
10900 
10901 #ifndef __ASSEMBLY__
10902 /*
10903  * WARNING: The C register and register group struct declarations are provided for
10904  * convenience and illustrative purposes. They should, however, be used with
10905  * caution as the C language standard provides no guarantees about the alignment or
10906  * atomicity of device memory accesses. The recommended practice for coding device
10907  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10908  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10909  * alt_write_dword() functions for 64 bit registers.
10910  *
10911  * The struct declaration for register ALT_I2C_IC_CLR_RESTART_DET.
10912  */
10913 struct ALT_I2C_IC_CLR_RESTART_DET_s
10914 {
10915  const volatile uint32_t CLR_RESTART_DET : 1; /* ALT_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET */
10916  const volatile uint32_t RSVD_IC_CLR_RESTART_DET : 31; /* ALT_I2C_IC_CLR_RESTART_DET_RSVD_IC_CLR_RESTART_DET */
10917 };
10918 
10919 /* The typedef declaration for register ALT_I2C_IC_CLR_RESTART_DET. */
10920 typedef struct ALT_I2C_IC_CLR_RESTART_DET_s ALT_I2C_IC_CLR_RESTART_DET_t;
10921 #endif /* __ASSEMBLY__ */
10922 
10923 /* The reset value of the ALT_I2C_IC_CLR_RESTART_DET register. */
10924 #define ALT_I2C_IC_CLR_RESTART_DET_RESET 0x00000000
10925 /* The byte offset of the ALT_I2C_IC_CLR_RESTART_DET register from the beginning of the component. */
10926 #define ALT_I2C_IC_CLR_RESTART_DET_OFST 0xa8
10927 /* The address of the ALT_I2C_IC_CLR_RESTART_DET register. */
10928 #define ALT_I2C_IC_CLR_RESTART_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_CLR_RESTART_DET_OFST))
10929 
10930 /*
10931  * Register : Component Parameter Register 1 - IC_COMP_PARAM_1
10932  *
10933  * Name: Component Parameter Register 1
10934  *
10935  * Size: 32 bits
10936  *
10937  * Address Offset: 0xf4
10938  *
10939  * Read/Write Access: Read
10940  *
10941  * Note
10942  *
10943  * This is a constant read-only register that contains
10944  *
10945  * encoded information about the component's parameter settings.
10946  *
10947  * The reset value depends on coreConsultant parameter(s).
10948  *
10949  * Register Layout
10950  *
10951  * Bits | Access | Reset | Description
10952  * :--------|:-------|:------|:---------------------------------------------
10953  * [1:0] | R | 0x2 | ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH
10954  * [3:2] | R | 0x2 | ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE
10955  * [4] | R | 0x0 | ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES
10956  * [5] | R | 0x1 | ALT_I2C_IC_COMP_PARAM_1_INTR_IO
10957  * [6] | R | 0x1 | ALT_I2C_IC_COMP_PARAM_1_HAS_DMA
10958  * [7] | R | 0x1 | ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS
10959  * [15:8] | R | 0x3f | ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH
10960  * [23:16] | R | 0x3f | ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH
10961  * [31:24] | R | 0x0 | ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1
10962  *
10963  */
10964 /*
10965  * Field : APB_DATA_WIDTH
10966  *
10967  * The value of this register is
10968  *
10969  * derived from the APB_DATA_WIDTH coreConsultant
10970  *
10971  * parameter.
10972  *
10973  * 0x0: 8 bits
10974  *
10975  * 0x1: 16 bits
10976  *
10977  * 0x2: 32 bits
10978  *
10979  * 0x3: Reserved
10980  *
10981  * Field Enumeration Values:
10982  *
10983  * Enum | Value | Description
10984  * :----------------------------------------------------|:------|:------------------------------
10985  * ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_E_APB_08BITS | 0x0 | APB data bus width is 08 bits
10986  * ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_E_APB_16BITS | 0x1 | APB data bus width is 16 bits
10987  * ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_E_APB_32BITS | 0x2 | APB data bus width is 32 bits
10988  *
10989  * Field Access Macros:
10990  *
10991  */
10992 /*
10993  * Enumerated value for register field ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH
10994  *
10995  * APB data bus width is 08 bits
10996  */
10997 #define ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_E_APB_08BITS 0x0
10998 /*
10999  * Enumerated value for register field ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH
11000  *
11001  * APB data bus width is 16 bits
11002  */
11003 #define ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_E_APB_16BITS 0x1
11004 /*
11005  * Enumerated value for register field ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH
11006  *
11007  * APB data bus width is 32 bits
11008  */
11009 #define ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_E_APB_32BITS 0x2
11010 
11011 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH register field. */
11012 #define ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_LSB 0
11013 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH register field. */
11014 #define ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_MSB 1
11015 /* The width in bits of the ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH register field. */
11016 #define ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_WIDTH 2
11017 /* The mask used to set the ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH register field value. */
11018 #define ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_SET_MSK 0x00000003
11019 /* The mask used to clear the ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH register field value. */
11020 #define ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc
11021 /* The reset value of the ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH register field. */
11022 #define ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_RESET 0x2
11023 /* Extracts the ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH field value from a register. */
11024 #define ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0)
11025 /* Produces a ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH register field value suitable for setting the register. */
11026 #define ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003)
11027 
11028 /*
11029  * Field : MAX_SPEED_MODE
11030  *
11031  * The value of this register is
11032  *
11033  * derived from the IC_MAX_SPEED_MODE coreConsultant
11034  *
11035  * parameter.
11036  *
11037  * 0x0: Reserved
11038  *
11039  * 0x1: Standard
11040  *
11041  * 0x2: Fast
11042  *
11043  * 0x3: High
11044  *
11045  * Dependencies: This field is not applicable when IC_ULTRA_FAST_MODE=1
11046  *
11047  * Field Enumeration Values:
11048  *
11049  * Enum | Value | Description
11050  * :--------------------------------------------------|:------|:------------------------------
11051  * ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_E_STANDARD | 0x1 | IC MAX SPEED is STANDARD MODE
11052  * ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_E_FAST | 0x2 | IC MAX SPEED is FAST MODE
11053  * ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_E_HIGH | 0x3 | IC MAX SPEED is HIGH MODE
11054  *
11055  * Field Access Macros:
11056  *
11057  */
11058 /*
11059  * Enumerated value for register field ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE
11060  *
11061  * IC MAX SPEED is STANDARD MODE
11062  */
11063 #define ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_E_STANDARD 0x1
11064 /*
11065  * Enumerated value for register field ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE
11066  *
11067  * IC MAX SPEED is FAST MODE
11068  */
11069 #define ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_E_FAST 0x2
11070 /*
11071  * Enumerated value for register field ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE
11072  *
11073  * IC MAX SPEED is HIGH MODE
11074  */
11075 #define ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_E_HIGH 0x3
11076 
11077 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE register field. */
11078 #define ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_LSB 2
11079 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE register field. */
11080 #define ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_MSB 3
11081 /* The width in bits of the ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE register field. */
11082 #define ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_WIDTH 2
11083 /* The mask used to set the ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE register field value. */
11084 #define ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_SET_MSK 0x0000000c
11085 /* The mask used to clear the ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE register field value. */
11086 #define ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_CLR_MSK 0xfffffff3
11087 /* The reset value of the ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE register field. */
11088 #define ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_RESET 0x2
11089 /* Extracts the ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE field value from a register. */
11090 #define ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_GET(value) (((value) & 0x0000000c) >> 2)
11091 /* Produces a ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE register field value suitable for setting the register. */
11092 #define ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_SET(value) (((value) << 2) & 0x0000000c)
11093 
11094 /*
11095  * Field : HC_COUNT_VALUES
11096  *
11097  * The value of this register is
11098  *
11099  * derived from the IC_HC_COUNT VALUES coreConsultant
11100  *
11101  * parameter
11102  *
11103  * 0: False
11104  *
11105  * 1: True
11106  *
11107  * Field Enumeration Values:
11108  *
11109  * Enum | Value | Description
11110  * :---------------------------------------------------|:------|:---------------------------------------
11111  * ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_E_DISABLED | 0x0 | Disables capability of reading encoded
11112  * : | | parameters
11113  * ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_E_ENABLED | 0x1 | Enables Capability of reading encoded
11114  * : | | parameters
11115  *
11116  * Field Access Macros:
11117  *
11118  */
11119 /*
11120  * Enumerated value for register field ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES
11121  *
11122  * Disables capability of reading encoded parameters
11123  */
11124 #define ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_E_DISABLED 0x0
11125 /*
11126  * Enumerated value for register field ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES
11127  *
11128  * Enables Capability of reading encoded parameters
11129  */
11130 #define ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_E_ENABLED 0x1
11131 
11132 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES register field. */
11133 #define ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_LSB 4
11134 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES register field. */
11135 #define ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_MSB 4
11136 /* The width in bits of the ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES register field. */
11137 #define ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_WIDTH 1
11138 /* The mask used to set the ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES register field value. */
11139 #define ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_SET_MSK 0x00000010
11140 /* The mask used to clear the ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES register field value. */
11141 #define ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_CLR_MSK 0xffffffef
11142 /* The reset value of the ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES register field. */
11143 #define ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_RESET 0x0
11144 /* Extracts the ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES field value from a register. */
11145 #define ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_GET(value) (((value) & 0x00000010) >> 4)
11146 /* Produces a ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES register field value suitable for setting the register. */
11147 #define ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_SET(value) (((value) << 4) & 0x00000010)
11148 
11149 /*
11150  * Field : INTR_IO
11151  *
11152  * The value of this register is
11153  *
11154  * derived from the IC_INTR_IO coreConsultant
11155  *
11156  * parameter
11157  *
11158  * 0: Individual
11159  *
11160  * 1: Combined
11161  *
11162  * Field Enumeration Values:
11163  *
11164  * Enum | Value | Description
11165  * :---------------------------------------------|:------|:-----------------------------
11166  * ALT_I2C_IC_COMP_PARAM_1_INTR_IO_E_INDIVIDUAL | 0x0 | INDIVIDUAL Interrupt outputs
11167  * ALT_I2C_IC_COMP_PARAM_1_INTR_IO_E_COMBINED | 0x1 | COMBINED Interrupt outputs
11168  *
11169  * Field Access Macros:
11170  *
11171  */
11172 /*
11173  * Enumerated value for register field ALT_I2C_IC_COMP_PARAM_1_INTR_IO
11174  *
11175  * INDIVIDUAL Interrupt outputs
11176  */
11177 #define ALT_I2C_IC_COMP_PARAM_1_INTR_IO_E_INDIVIDUAL 0x0
11178 /*
11179  * Enumerated value for register field ALT_I2C_IC_COMP_PARAM_1_INTR_IO
11180  *
11181  * COMBINED Interrupt outputs
11182  */
11183 #define ALT_I2C_IC_COMP_PARAM_1_INTR_IO_E_COMBINED 0x1
11184 
11185 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_COMP_PARAM_1_INTR_IO register field. */
11186 #define ALT_I2C_IC_COMP_PARAM_1_INTR_IO_LSB 5
11187 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_COMP_PARAM_1_INTR_IO register field. */
11188 #define ALT_I2C_IC_COMP_PARAM_1_INTR_IO_MSB 5
11189 /* The width in bits of the ALT_I2C_IC_COMP_PARAM_1_INTR_IO register field. */
11190 #define ALT_I2C_IC_COMP_PARAM_1_INTR_IO_WIDTH 1
11191 /* The mask used to set the ALT_I2C_IC_COMP_PARAM_1_INTR_IO register field value. */
11192 #define ALT_I2C_IC_COMP_PARAM_1_INTR_IO_SET_MSK 0x00000020
11193 /* The mask used to clear the ALT_I2C_IC_COMP_PARAM_1_INTR_IO register field value. */
11194 #define ALT_I2C_IC_COMP_PARAM_1_INTR_IO_CLR_MSK 0xffffffdf
11195 /* The reset value of the ALT_I2C_IC_COMP_PARAM_1_INTR_IO register field. */
11196 #define ALT_I2C_IC_COMP_PARAM_1_INTR_IO_RESET 0x1
11197 /* Extracts the ALT_I2C_IC_COMP_PARAM_1_INTR_IO field value from a register. */
11198 #define ALT_I2C_IC_COMP_PARAM_1_INTR_IO_GET(value) (((value) & 0x00000020) >> 5)
11199 /* Produces a ALT_I2C_IC_COMP_PARAM_1_INTR_IO register field value suitable for setting the register. */
11200 #define ALT_I2C_IC_COMP_PARAM_1_INTR_IO_SET(value) (((value) << 5) & 0x00000020)
11201 
11202 /*
11203  * Field : HAS_DMA
11204  *
11205  * The value of this register is
11206  *
11207  * derived from the IC_HAS_DMA coreConsultant
11208  *
11209  * parameter
11210  *
11211  * 0: False
11212  *
11213  * 1: True
11214  *
11215  * Field Enumeration Values:
11216  *
11217  * Enum | Value | Description
11218  * :-------------------------------------------|:------|:-------------------------------------
11219  * ALT_I2C_IC_COMP_PARAM_1_HAS_DMA_E_DISABLED | 0x0 | DMA handshaking signals are disabled
11220  * ALT_I2C_IC_COMP_PARAM_1_HAS_DMA_E_ENABLED | 0x1 | DMA handshaking signals are enabled
11221  *
11222  * Field Access Macros:
11223  *
11224  */
11225 /*
11226  * Enumerated value for register field ALT_I2C_IC_COMP_PARAM_1_HAS_DMA
11227  *
11228  * DMA handshaking signals are disabled
11229  */
11230 #define ALT_I2C_IC_COMP_PARAM_1_HAS_DMA_E_DISABLED 0x0
11231 /*
11232  * Enumerated value for register field ALT_I2C_IC_COMP_PARAM_1_HAS_DMA
11233  *
11234  * DMA handshaking signals are enabled
11235  */
11236 #define ALT_I2C_IC_COMP_PARAM_1_HAS_DMA_E_ENABLED 0x1
11237 
11238 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_COMP_PARAM_1_HAS_DMA register field. */
11239 #define ALT_I2C_IC_COMP_PARAM_1_HAS_DMA_LSB 6
11240 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_COMP_PARAM_1_HAS_DMA register field. */
11241 #define ALT_I2C_IC_COMP_PARAM_1_HAS_DMA_MSB 6
11242 /* The width in bits of the ALT_I2C_IC_COMP_PARAM_1_HAS_DMA register field. */
11243 #define ALT_I2C_IC_COMP_PARAM_1_HAS_DMA_WIDTH 1
11244 /* The mask used to set the ALT_I2C_IC_COMP_PARAM_1_HAS_DMA register field value. */
11245 #define ALT_I2C_IC_COMP_PARAM_1_HAS_DMA_SET_MSK 0x00000040
11246 /* The mask used to clear the ALT_I2C_IC_COMP_PARAM_1_HAS_DMA register field value. */
11247 #define ALT_I2C_IC_COMP_PARAM_1_HAS_DMA_CLR_MSK 0xffffffbf
11248 /* The reset value of the ALT_I2C_IC_COMP_PARAM_1_HAS_DMA register field. */
11249 #define ALT_I2C_IC_COMP_PARAM_1_HAS_DMA_RESET 0x1
11250 /* Extracts the ALT_I2C_IC_COMP_PARAM_1_HAS_DMA field value from a register. */
11251 #define ALT_I2C_IC_COMP_PARAM_1_HAS_DMA_GET(value) (((value) & 0x00000040) >> 6)
11252 /* Produces a ALT_I2C_IC_COMP_PARAM_1_HAS_DMA register field value suitable for setting the register. */
11253 #define ALT_I2C_IC_COMP_PARAM_1_HAS_DMA_SET(value) (((value) << 6) & 0x00000040)
11254 
11255 /*
11256  * Field : ADD_ENCODED_PARAMS
11257  *
11258  * The value of this register is derived
11259  *
11260  * from the IC_ADD_ENCODED_PARAMS coreConsultant
11261  *
11262  * parameter.
11263  *
11264  * Reading 1 in this bit means that the capability
11265  *
11266  * of reading these encoded parameters via software has been
11267  *
11268  * included. Otherwise, the entire register is 0 regardless of
11269  *
11270  * the setting of any other parameters that are encoded in the
11271  *
11272  * bits.
11273  *
11274  * 0: False
11275  *
11276  * 1: True
11277  *
11278  * Field Enumeration Values:
11279  *
11280  * Enum | Value | Description
11281  * :------------------------------------------------------|:------|:---------------------------------------
11282  * ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_E_DISBALED | 0x0 | Disables capability of reading encoded
11283  * : | | parameters
11284  * ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_E_ENABLED | 0x1 | Enables capability of reading encoded
11285  * : | | parameters
11286  *
11287  * Field Access Macros:
11288  *
11289  */
11290 /*
11291  * Enumerated value for register field ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS
11292  *
11293  * Disables capability of reading encoded parameters
11294  */
11295 #define ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_E_DISBALED 0x0
11296 /*
11297  * Enumerated value for register field ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS
11298  *
11299  * Enables capability of reading encoded parameters
11300  */
11301 #define ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_E_ENABLED 0x1
11302 
11303 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS register field. */
11304 #define ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_LSB 7
11305 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS register field. */
11306 #define ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_MSB 7
11307 /* The width in bits of the ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS register field. */
11308 #define ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_WIDTH 1
11309 /* The mask used to set the ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS register field value. */
11310 #define ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_SET_MSK 0x00000080
11311 /* The mask used to clear the ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS register field value. */
11312 #define ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_CLR_MSK 0xffffff7f
11313 /* The reset value of the ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS register field. */
11314 #define ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_RESET 0x1
11315 /* Extracts the ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS field value from a register. */
11316 #define ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_GET(value) (((value) & 0x00000080) >> 7)
11317 /* Produces a ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS register field value suitable for setting the register. */
11318 #define ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_SET(value) (((value) << 7) & 0x00000080)
11319 
11320 /*
11321  * Field : RX_BUFFER_DEPTH
11322  *
11323  * The value of this register is
11324  *
11325  * derived from the IC_RX_BUFFER_DEPTH coreConsultant
11326  *
11327  * parameter.
11328  *
11329  * 0x00: Reserved
11330  *
11331  * 0x01: 2
11332  *
11333  * 0x02: 3
11334  *
11335  * to
11336  *
11337  * 0xFF: 256
11338  *
11339  * Field Access Macros:
11340  *
11341  */
11342 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH register field. */
11343 #define ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_LSB 8
11344 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH register field. */
11345 #define ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_MSB 15
11346 /* The width in bits of the ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH register field. */
11347 #define ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_WIDTH 8
11348 /* The mask used to set the ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH register field value. */
11349 #define ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_SET_MSK 0x0000ff00
11350 /* The mask used to clear the ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH register field value. */
11351 #define ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_CLR_MSK 0xffff00ff
11352 /* The reset value of the ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH register field. */
11353 #define ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_RESET 0x3f
11354 /* Extracts the ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH field value from a register. */
11355 #define ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_GET(value) (((value) & 0x0000ff00) >> 8)
11356 /* Produces a ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH register field value suitable for setting the register. */
11357 #define ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_SET(value) (((value) << 8) & 0x0000ff00)
11358 
11359 /*
11360  * Field : TX_BUFFER_DEPTH
11361  *
11362  * The value of this register is derived
11363  *
11364  * from the IC_TX_BUFFER_DEPTH coreConsultant
11365  *
11366  * parameter.
11367  *
11368  * 0x00 = Reserved
11369  *
11370  * 0x01 = 2
11371  *
11372  * 0x02 = 3
11373  *
11374  * to
11375  *
11376  * 0xFF = 256
11377  *
11378  * Field Access Macros:
11379  *
11380  */
11381 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH register field. */
11382 #define ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_LSB 16
11383 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH register field. */
11384 #define ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_MSB 23
11385 /* The width in bits of the ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH register field. */
11386 #define ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_WIDTH 8
11387 /* The mask used to set the ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH register field value. */
11388 #define ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_SET_MSK 0x00ff0000
11389 /* The mask used to clear the ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH register field value. */
11390 #define ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_CLR_MSK 0xff00ffff
11391 /* The reset value of the ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH register field. */
11392 #define ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_RESET 0x3f
11393 /* Extracts the ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH field value from a register. */
11394 #define ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_GET(value) (((value) & 0x00ff0000) >> 16)
11395 /* Produces a ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH register field value suitable for setting the register. */
11396 #define ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_SET(value) (((value) << 16) & 0x00ff0000)
11397 
11398 /*
11399  * Field : RSVD_IC_COMP_PARAM_1
11400  *
11401  * Reserved bits - Read Only
11402  *
11403  * Field Access Macros:
11404  *
11405  */
11406 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1 register field. */
11407 #define ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1_LSB 24
11408 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1 register field. */
11409 #define ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1_MSB 31
11410 /* The width in bits of the ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1 register field. */
11411 #define ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1_WIDTH 8
11412 /* The mask used to set the ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1 register field value. */
11413 #define ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1_SET_MSK 0xff000000
11414 /* The mask used to clear the ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1 register field value. */
11415 #define ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1_CLR_MSK 0x00ffffff
11416 /* The reset value of the ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1 register field. */
11417 #define ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1_RESET 0x0
11418 /* Extracts the ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1 field value from a register. */
11419 #define ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1_GET(value) (((value) & 0xff000000) >> 24)
11420 /* Produces a ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1 register field value suitable for setting the register. */
11421 #define ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1_SET(value) (((value) << 24) & 0xff000000)
11422 
11423 #ifndef __ASSEMBLY__
11424 /*
11425  * WARNING: The C register and register group struct declarations are provided for
11426  * convenience and illustrative purposes. They should, however, be used with
11427  * caution as the C language standard provides no guarantees about the alignment or
11428  * atomicity of device memory accesses. The recommended practice for coding device
11429  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11430  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11431  * alt_write_dword() functions for 64 bit registers.
11432  *
11433  * The struct declaration for register ALT_I2C_IC_COMP_PARAM_1.
11434  */
11435 struct ALT_I2C_IC_COMP_PARAM_1_s
11436 {
11437  const volatile uint32_t APB_DATA_WIDTH : 2; /* ALT_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH */
11438  const volatile uint32_t MAX_SPEED_MODE : 2; /* ALT_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE */
11439  const volatile uint32_t HC_COUNT_VALUES : 1; /* ALT_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES */
11440  const volatile uint32_t INTR_IO : 1; /* ALT_I2C_IC_COMP_PARAM_1_INTR_IO */
11441  const volatile uint32_t HAS_DMA : 1; /* ALT_I2C_IC_COMP_PARAM_1_HAS_DMA */
11442  const volatile uint32_t ADD_ENCODED_PARAMS : 1; /* ALT_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS */
11443  const volatile uint32_t RX_BUFFER_DEPTH : 8; /* ALT_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH */
11444  const volatile uint32_t TX_BUFFER_DEPTH : 8; /* ALT_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH */
11445  const volatile uint32_t RSVD_IC_COMP_PARAM_1 : 8; /* ALT_I2C_IC_COMP_PARAM_1_RSVD_IC_COMP_PARAM_1 */
11446 };
11447 
11448 /* The typedef declaration for register ALT_I2C_IC_COMP_PARAM_1. */
11449 typedef struct ALT_I2C_IC_COMP_PARAM_1_s ALT_I2C_IC_COMP_PARAM_1_t;
11450 #endif /* __ASSEMBLY__ */
11451 
11452 /* The reset value of the ALT_I2C_IC_COMP_PARAM_1 register. */
11453 #define ALT_I2C_IC_COMP_PARAM_1_RESET 0x003f3fea
11454 /* The byte offset of the ALT_I2C_IC_COMP_PARAM_1 register from the beginning of the component. */
11455 #define ALT_I2C_IC_COMP_PARAM_1_OFST 0xf4
11456 /* The address of the ALT_I2C_IC_COMP_PARAM_1 register. */
11457 #define ALT_I2C_IC_COMP_PARAM_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_COMP_PARAM_1_OFST))
11458 
11459 /*
11460  * Register : I2C Component Version Register - IC_COMP_VERSION
11461  *
11462  * Name: I2C Component Version Register
11463  *
11464  * Size: 32 bits
11465  *
11466  * Address Offset: 0xf8
11467  *
11468  * Read/Write Access: Read
11469  *
11470  * Register Layout
11471  *
11472  * Bits | Access | Reset | Description
11473  * :-------|:-------|:-----------|:----------------------------------------
11474  * [31:0] | R | 0x3230302a | ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION
11475  *
11476  */
11477 /*
11478  * Field : IC_COMP_VERSION
11479  *
11480  * Specific values for this register are
11481  *
11482  * described in the Releases Table in the
11483  *
11484  * DW_apb_i2c Release Notes
11485  *
11486  * Field Access Macros:
11487  *
11488  */
11489 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION register field. */
11490 #define ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION_LSB 0
11491 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION register field. */
11492 #define ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION_MSB 31
11493 /* The width in bits of the ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION register field. */
11494 #define ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION_WIDTH 32
11495 /* The mask used to set the ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION register field value. */
11496 #define ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION_SET_MSK 0xffffffff
11497 /* The mask used to clear the ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION register field value. */
11498 #define ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION_CLR_MSK 0x00000000
11499 /* The reset value of the ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION register field. */
11500 #define ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION_RESET 0x3230302a
11501 /* Extracts the ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION field value from a register. */
11502 #define ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION_GET(value) (((value) & 0xffffffff) >> 0)
11503 /* Produces a ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION register field value suitable for setting the register. */
11504 #define ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION_SET(value) (((value) << 0) & 0xffffffff)
11505 
11506 #ifndef __ASSEMBLY__
11507 /*
11508  * WARNING: The C register and register group struct declarations are provided for
11509  * convenience and illustrative purposes. They should, however, be used with
11510  * caution as the C language standard provides no guarantees about the alignment or
11511  * atomicity of device memory accesses. The recommended practice for coding device
11512  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11513  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11514  * alt_write_dword() functions for 64 bit registers.
11515  *
11516  * The struct declaration for register ALT_I2C_IC_COMP_VERSION.
11517  */
11518 struct ALT_I2C_IC_COMP_VERSION_s
11519 {
11520  const volatile uint32_t IC_COMP_VERSION : 32; /* ALT_I2C_IC_COMP_VERSION_IC_COMP_VERSION */
11521 };
11522 
11523 /* The typedef declaration for register ALT_I2C_IC_COMP_VERSION. */
11524 typedef struct ALT_I2C_IC_COMP_VERSION_s ALT_I2C_IC_COMP_VERSION_t;
11525 #endif /* __ASSEMBLY__ */
11526 
11527 /* The reset value of the ALT_I2C_IC_COMP_VERSION register. */
11528 #define ALT_I2C_IC_COMP_VERSION_RESET 0x3230302a
11529 /* The byte offset of the ALT_I2C_IC_COMP_VERSION register from the beginning of the component. */
11530 #define ALT_I2C_IC_COMP_VERSION_OFST 0xf8
11531 /* The address of the ALT_I2C_IC_COMP_VERSION register. */
11532 #define ALT_I2C_IC_COMP_VERSION_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_COMP_VERSION_OFST))
11533 
11534 /*
11535  * Register : I2C Component Type Register - IC_COMP_TYPE
11536  *
11537  * Name: I2C Component Type Register
11538  *
11539  * Size: 32 bits
11540  *
11541  * Address Offset: 0xfc
11542  *
11543  * Read/Write Access: Read
11544  *
11545  * Register Layout
11546  *
11547  * Bits | Access | Reset | Description
11548  * :-------|:-------|:-----------|:----------------------------------
11549  * [31:0] | R | 0x44570140 | ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE
11550  *
11551  */
11552 /*
11553  * Field : IC_COMP_TYPE
11554  *
11555  * Designware Component Type number
11556  *
11557  * = 0x44_57_01_40. This assigned unique
11558  *
11559  * hex value is constant and is derived
11560  *
11561  * from the two ASCII letters 'DW' followed
11562  *
11563  * by a 16-bit unsigned number.
11564  *
11565  * Field Access Macros:
11566  *
11567  */
11568 /* The Least Significant Bit (LSB) position of the ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE register field. */
11569 #define ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE_LSB 0
11570 /* The Most Significant Bit (MSB) position of the ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE register field. */
11571 #define ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE_MSB 31
11572 /* The width in bits of the ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE register field. */
11573 #define ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE_WIDTH 32
11574 /* The mask used to set the ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE register field value. */
11575 #define ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE_SET_MSK 0xffffffff
11576 /* The mask used to clear the ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE register field value. */
11577 #define ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE_CLR_MSK 0x00000000
11578 /* The reset value of the ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE register field. */
11579 #define ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE_RESET 0x44570140
11580 /* Extracts the ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE field value from a register. */
11581 #define ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE_GET(value) (((value) & 0xffffffff) >> 0)
11582 /* Produces a ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE register field value suitable for setting the register. */
11583 #define ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE_SET(value) (((value) << 0) & 0xffffffff)
11584 
11585 #ifndef __ASSEMBLY__
11586 /*
11587  * WARNING: The C register and register group struct declarations are provided for
11588  * convenience and illustrative purposes. They should, however, be used with
11589  * caution as the C language standard provides no guarantees about the alignment or
11590  * atomicity of device memory accesses. The recommended practice for coding device
11591  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11592  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11593  * alt_write_dword() functions for 64 bit registers.
11594  *
11595  * The struct declaration for register ALT_I2C_IC_COMP_TYPE.
11596  */
11597 struct ALT_I2C_IC_COMP_TYPE_s
11598 {
11599  const volatile uint32_t IC_COMP_TYPE : 32; /* ALT_I2C_IC_COMP_TYPE_IC_COMP_TYPE */
11600 };
11601 
11602 /* The typedef declaration for register ALT_I2C_IC_COMP_TYPE. */
11603 typedef struct ALT_I2C_IC_COMP_TYPE_s ALT_I2C_IC_COMP_TYPE_t;
11604 #endif /* __ASSEMBLY__ */
11605 
11606 /* The reset value of the ALT_I2C_IC_COMP_TYPE register. */
11607 #define ALT_I2C_IC_COMP_TYPE_RESET 0x44570140
11608 /* The byte offset of the ALT_I2C_IC_COMP_TYPE register from the beginning of the component. */
11609 #define ALT_I2C_IC_COMP_TYPE_OFST 0xfc
11610 /* The address of the ALT_I2C_IC_COMP_TYPE register. */
11611 #define ALT_I2C_IC_COMP_TYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_IC_COMP_TYPE_OFST))
11612 
11613 #ifndef __ASSEMBLY__
11614 /*
11615  * WARNING: The C register and register group struct declarations are provided for
11616  * convenience and illustrative purposes. They should, however, be used with
11617  * caution as the C language standard provides no guarantees about the alignment or
11618  * atomicity of device memory accesses. The recommended practice for coding device
11619  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11620  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11621  * alt_write_dword() functions for 64 bit registers.
11622  *
11623  * The struct declaration for register group ALT_I2C.
11624  */
11625 struct ALT_I2C_s
11626 {
11627  volatile ALT_I2C_IC_CON_t IC_CON; /* ALT_I2C_IC_CON */
11628  volatile ALT_I2C_IC_TAR_t IC_TAR; /* ALT_I2C_IC_TAR */
11629  volatile ALT_I2C_IC_SAR_t IC_SAR; /* ALT_I2C_IC_SAR */
11630  volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
11631  volatile ALT_I2C_IC_DATA_CMD_t IC_DATA_CMD; /* ALT_I2C_IC_DATA_CMD */
11632  volatile ALT_I2C_IC_SS_SCL_HCNT_t IC_SS_SCL_HCNT; /* ALT_I2C_IC_SS_SCL_HCNT */
11633  volatile ALT_I2C_IC_SS_SCL_LCNT_t IC_SS_SCL_LCNT; /* ALT_I2C_IC_SS_SCL_LCNT */
11634  volatile ALT_I2C_IC_FS_SCL_HCNT_t IC_FS_SCL_HCNT; /* ALT_I2C_IC_FS_SCL_HCNT */
11635  volatile ALT_I2C_IC_FS_SCL_LCNT_t IC_FS_SCL_LCNT; /* ALT_I2C_IC_FS_SCL_LCNT */
11636  volatile uint32_t _pad_0x24_0x2b[2]; /* *UNDEFINED* */
11637  volatile ALT_I2C_IC_INTR_STAT_t IC_INTR_STAT; /* ALT_I2C_IC_INTR_STAT */
11638  volatile ALT_I2C_IC_INTR_MASK_t IC_INTR_MASK; /* ALT_I2C_IC_INTR_MASK */
11639  volatile ALT_I2C_IC_RAW_INTR_STAT_t IC_RAW_INTR_STAT; /* ALT_I2C_IC_RAW_INTR_STAT */
11640  volatile ALT_I2C_IC_RX_TL_t IC_RX_TL; /* ALT_I2C_IC_RX_TL */
11641  volatile ALT_I2C_IC_TX_TL_t IC_TX_TL; /* ALT_I2C_IC_TX_TL */
11642  volatile ALT_I2C_IC_CLR_INTR_t IC_CLR_INTR; /* ALT_I2C_IC_CLR_INTR */
11643  volatile ALT_I2C_IC_CLR_RX_UNDER_t IC_CLR_RX_UNDER; /* ALT_I2C_IC_CLR_RX_UNDER */
11644  volatile ALT_I2C_IC_CLR_RX_OVER_t IC_CLR_RX_OVER; /* ALT_I2C_IC_CLR_RX_OVER */
11645  volatile ALT_I2C_IC_CLR_TX_OVER_t IC_CLR_TX_OVER; /* ALT_I2C_IC_CLR_TX_OVER */
11646  volatile ALT_I2C_IC_CLR_RD_REQ_t IC_CLR_RD_REQ; /* ALT_I2C_IC_CLR_RD_REQ */
11647  volatile ALT_I2C_IC_CLR_TX_ABRT_t IC_CLR_TX_ABRT; /* ALT_I2C_IC_CLR_TX_ABRT */
11648  volatile ALT_I2C_IC_CLR_RX_DONE_t IC_CLR_RX_DONE; /* ALT_I2C_IC_CLR_RX_DONE */
11649  volatile ALT_I2C_IC_CLR_ACTIVITY_t IC_CLR_ACTIVITY; /* ALT_I2C_IC_CLR_ACTIVITY */
11650  volatile ALT_I2C_IC_CLR_STOP_DET_t IC_CLR_STOP_DET; /* ALT_I2C_IC_CLR_STOP_DET */
11651  volatile ALT_I2C_IC_CLR_START_DET_t IC_CLR_START_DET; /* ALT_I2C_IC_CLR_START_DET */
11652  volatile ALT_I2C_IC_CLR_GEN_CALL_t IC_CLR_GEN_CALL; /* ALT_I2C_IC_CLR_GEN_CALL */
11653  volatile ALT_I2C_IC_ENABLE_t IC_ENABLE; /* ALT_I2C_IC_ENABLE */
11654  volatile ALT_I2C_IC_STATUS_t IC_STATUS; /* ALT_I2C_IC_STATUS */
11655  volatile ALT_I2C_IC_TXFLR_t IC_TXFLR; /* ALT_I2C_IC_TXFLR */
11656  volatile ALT_I2C_IC_RXFLR_t IC_RXFLR; /* ALT_I2C_IC_RXFLR */
11657  volatile ALT_I2C_IC_SDA_HOLD_t IC_SDA_HOLD; /* ALT_I2C_IC_SDA_HOLD */
11658  volatile ALT_I2C_IC_TX_ABRT_SOURCE_t IC_TX_ABRT_SOURCE; /* ALT_I2C_IC_TX_ABRT_SOURCE */
11659  volatile ALT_I2C_IC_SLV_DATA_NACK_ONLY_t IC_SLV_DATA_NACK_ONLY; /* ALT_I2C_IC_SLV_DATA_NACK_ONLY */
11660  volatile ALT_I2C_IC_DMA_CR_t IC_DMA_CR; /* ALT_I2C_IC_DMA_CR */
11661  volatile ALT_I2C_IC_DMA_TDLR_t IC_DMA_TDLR; /* ALT_I2C_IC_DMA_TDLR */
11662  volatile ALT_I2C_IC_DMA_RDLR_t IC_DMA_RDLR; /* ALT_I2C_IC_DMA_RDLR */
11663  volatile ALT_I2C_IC_SDA_SETUP_t IC_SDA_SETUP; /* ALT_I2C_IC_SDA_SETUP */
11664  volatile ALT_I2C_IC_ACK_GENERAL_CALL_t IC_ACK_GENERAL_CALL; /* ALT_I2C_IC_ACK_GENERAL_CALL */
11665  volatile ALT_I2C_IC_ENABLE_STATUS_t IC_ENABLE_STATUS; /* ALT_I2C_IC_ENABLE_STATUS */
11666  volatile ALT_I2C_IC_FS_SPKLEN_t IC_FS_SPKLEN; /* ALT_I2C_IC_FS_SPKLEN */
11667  volatile uint32_t _pad_0xa4_0xa7; /* *UNDEFINED* */
11668  volatile ALT_I2C_IC_CLR_RESTART_DET_t IC_CLR_RESTART_DET; /* ALT_I2C_IC_CLR_RESTART_DET */
11669  volatile uint32_t _pad_0xac_0xf3[18]; /* *UNDEFINED* */
11670  volatile ALT_I2C_IC_COMP_PARAM_1_t IC_COMP_PARAM_1; /* ALT_I2C_IC_COMP_PARAM_1 */
11671  volatile ALT_I2C_IC_COMP_VERSION_t IC_COMP_VERSION; /* ALT_I2C_IC_COMP_VERSION */
11672  volatile ALT_I2C_IC_COMP_TYPE_t IC_COMP_TYPE; /* ALT_I2C_IC_COMP_TYPE */
11673 };
11674 
11675 /* The typedef declaration for register group ALT_I2C. */
11676 typedef struct ALT_I2C_s ALT_I2C_t;
11677 /* The struct declaration for the raw register contents of register group ALT_I2C. */
11678 struct ALT_I2C_raw_s
11679 {
11680  volatile uint32_t IC_CON; /* ALT_I2C_IC_CON */
11681  volatile uint32_t IC_TAR; /* ALT_I2C_IC_TAR */
11682  volatile uint32_t IC_SAR; /* ALT_I2C_IC_SAR */
11683  volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
11684  volatile uint32_t IC_DATA_CMD; /* ALT_I2C_IC_DATA_CMD */
11685  volatile uint32_t IC_SS_SCL_HCNT; /* ALT_I2C_IC_SS_SCL_HCNT */
11686  volatile uint32_t IC_SS_SCL_LCNT; /* ALT_I2C_IC_SS_SCL_LCNT */
11687  volatile uint32_t IC_FS_SCL_HCNT; /* ALT_I2C_IC_FS_SCL_HCNT */
11688  volatile uint32_t IC_FS_SCL_LCNT; /* ALT_I2C_IC_FS_SCL_LCNT */
11689  volatile uint32_t _pad_0x24_0x2b[2]; /* *UNDEFINED* */
11690  volatile uint32_t IC_INTR_STAT; /* ALT_I2C_IC_INTR_STAT */
11691  volatile uint32_t IC_INTR_MASK; /* ALT_I2C_IC_INTR_MASK */
11692  volatile uint32_t IC_RAW_INTR_STAT; /* ALT_I2C_IC_RAW_INTR_STAT */
11693  volatile uint32_t IC_RX_TL; /* ALT_I2C_IC_RX_TL */
11694  volatile uint32_t IC_TX_TL; /* ALT_I2C_IC_TX_TL */
11695  volatile uint32_t IC_CLR_INTR; /* ALT_I2C_IC_CLR_INTR */
11696  volatile uint32_t IC_CLR_RX_UNDER; /* ALT_I2C_IC_CLR_RX_UNDER */
11697  volatile uint32_t IC_CLR_RX_OVER; /* ALT_I2C_IC_CLR_RX_OVER */
11698  volatile uint32_t IC_CLR_TX_OVER; /* ALT_I2C_IC_CLR_TX_OVER */
11699  volatile uint32_t IC_CLR_RD_REQ; /* ALT_I2C_IC_CLR_RD_REQ */
11700  volatile uint32_t IC_CLR_TX_ABRT; /* ALT_I2C_IC_CLR_TX_ABRT */
11701  volatile uint32_t IC_CLR_RX_DONE; /* ALT_I2C_IC_CLR_RX_DONE */
11702  volatile uint32_t IC_CLR_ACTIVITY; /* ALT_I2C_IC_CLR_ACTIVITY */
11703  volatile uint32_t IC_CLR_STOP_DET; /* ALT_I2C_IC_CLR_STOP_DET */
11704  volatile uint32_t IC_CLR_START_DET; /* ALT_I2C_IC_CLR_START_DET */
11705  volatile uint32_t IC_CLR_GEN_CALL; /* ALT_I2C_IC_CLR_GEN_CALL */
11706  volatile uint32_t IC_ENABLE; /* ALT_I2C_IC_ENABLE */
11707  volatile uint32_t IC_STATUS; /* ALT_I2C_IC_STATUS */
11708  volatile uint32_t IC_TXFLR; /* ALT_I2C_IC_TXFLR */
11709  volatile uint32_t IC_RXFLR; /* ALT_I2C_IC_RXFLR */
11710  volatile uint32_t IC_SDA_HOLD; /* ALT_I2C_IC_SDA_HOLD */
11711  volatile uint32_t IC_TX_ABRT_SOURCE; /* ALT_I2C_IC_TX_ABRT_SOURCE */
11712  volatile uint32_t IC_SLV_DATA_NACK_ONLY; /* ALT_I2C_IC_SLV_DATA_NACK_ONLY */
11713  volatile uint32_t IC_DMA_CR; /* ALT_I2C_IC_DMA_CR */
11714  volatile uint32_t IC_DMA_TDLR; /* ALT_I2C_IC_DMA_TDLR */
11715  volatile uint32_t IC_DMA_RDLR; /* ALT_I2C_IC_DMA_RDLR */
11716  volatile uint32_t IC_SDA_SETUP; /* ALT_I2C_IC_SDA_SETUP */
11717  volatile uint32_t IC_ACK_GENERAL_CALL; /* ALT_I2C_IC_ACK_GENERAL_CALL */
11718  volatile uint32_t IC_ENABLE_STATUS; /* ALT_I2C_IC_ENABLE_STATUS */
11719  volatile uint32_t IC_FS_SPKLEN; /* ALT_I2C_IC_FS_SPKLEN */
11720  volatile uint32_t _pad_0xa4_0xa7; /* *UNDEFINED* */
11721  volatile uint32_t IC_CLR_RESTART_DET; /* ALT_I2C_IC_CLR_RESTART_DET */
11722  volatile uint32_t _pad_0xac_0xf3[18]; /* *UNDEFINED* */
11723  volatile uint32_t IC_COMP_PARAM_1; /* ALT_I2C_IC_COMP_PARAM_1 */
11724  volatile uint32_t IC_COMP_VERSION; /* ALT_I2C_IC_COMP_VERSION */
11725  volatile uint32_t IC_COMP_TYPE; /* ALT_I2C_IC_COMP_TYPE */
11726 };
11727 
11728 /* The typedef declaration for the raw register contents of register group ALT_I2C. */
11729 typedef struct ALT_I2C_raw_s ALT_I2C_raw_t;
11730 #endif /* __ASSEMBLY__ */
11731 
11732 
11733 #ifdef __cplusplus
11734 }
11735 #endif /* __cplusplus */
11736 #endif /* __ALT_SOCAL_I2C_H__ */
11737