35 #ifndef __ALT_SOCAL_RSTMGR_H__
36 #define __ALT_SOCAL_RSTMGR_H__
106 #define ALT_RSTMGR_STAT_PORHPSVOLTRST_LSB 0
108 #define ALT_RSTMGR_STAT_PORHPSVOLTRST_MSB 0
110 #define ALT_RSTMGR_STAT_PORHPSVOLTRST_WIDTH 1
112 #define ALT_RSTMGR_STAT_PORHPSVOLTRST_SET_MSK 0x00000001
114 #define ALT_RSTMGR_STAT_PORHPSVOLTRST_CLR_MSK 0xfffffffe
116 #define ALT_RSTMGR_STAT_PORHPSVOLTRST_RESET 0x0
118 #define ALT_RSTMGR_STAT_PORHPSVOLTRST_GET(value) (((value) & 0x00000001) >> 0)
120 #define ALT_RSTMGR_STAT_PORHPSVOLTRST_SET(value) (((value) << 0) & 0x00000001)
132 #define ALT_RSTMGR_STAT_PORFPGAVOLTRST_LSB 1
134 #define ALT_RSTMGR_STAT_PORFPGAVOLTRST_MSB 1
136 #define ALT_RSTMGR_STAT_PORFPGAVOLTRST_WIDTH 1
138 #define ALT_RSTMGR_STAT_PORFPGAVOLTRST_SET_MSK 0x00000002
140 #define ALT_RSTMGR_STAT_PORFPGAVOLTRST_CLR_MSK 0xfffffffd
142 #define ALT_RSTMGR_STAT_PORFPGAVOLTRST_RESET 0x0
144 #define ALT_RSTMGR_STAT_PORFPGAVOLTRST_GET(value) (((value) & 0x00000002) >> 1)
146 #define ALT_RSTMGR_STAT_PORFPGAVOLTRST_SET(value) (((value) << 1) & 0x00000002)
157 #define ALT_RSTMGR_STAT_NPORPINRST_LSB 2
159 #define ALT_RSTMGR_STAT_NPORPINRST_MSB 2
161 #define ALT_RSTMGR_STAT_NPORPINRST_WIDTH 1
163 #define ALT_RSTMGR_STAT_NPORPINRST_SET_MSK 0x00000004
165 #define ALT_RSTMGR_STAT_NPORPINRST_CLR_MSK 0xfffffffb
167 #define ALT_RSTMGR_STAT_NPORPINRST_RESET 0x0
169 #define ALT_RSTMGR_STAT_NPORPINRST_GET(value) (((value) & 0x00000004) >> 2)
171 #define ALT_RSTMGR_STAT_NPORPINRST_SET(value) (((value) << 2) & 0x00000004)
182 #define ALT_RSTMGR_STAT_FPGACOLDRST_LSB 3
184 #define ALT_RSTMGR_STAT_FPGACOLDRST_MSB 3
186 #define ALT_RSTMGR_STAT_FPGACOLDRST_WIDTH 1
188 #define ALT_RSTMGR_STAT_FPGACOLDRST_SET_MSK 0x00000008
190 #define ALT_RSTMGR_STAT_FPGACOLDRST_CLR_MSK 0xfffffff7
192 #define ALT_RSTMGR_STAT_FPGACOLDRST_RESET 0x0
194 #define ALT_RSTMGR_STAT_FPGACOLDRST_GET(value) (((value) & 0x00000008) >> 3)
196 #define ALT_RSTMGR_STAT_FPGACOLDRST_SET(value) (((value) << 3) & 0x00000008)
207 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_LSB 4
209 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_MSB 4
211 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_WIDTH 1
213 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET_MSK 0x00000010
215 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_CLR_MSK 0xffffffef
217 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_RESET 0x0
219 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_GET(value) (((value) & 0x00000010) >> 4)
221 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET(value) (((value) << 4) & 0x00000010)
232 #define ALT_RSTMGR_STAT_SWCOLDRST_LSB 5
234 #define ALT_RSTMGR_STAT_SWCOLDRST_MSB 5
236 #define ALT_RSTMGR_STAT_SWCOLDRST_WIDTH 1
238 #define ALT_RSTMGR_STAT_SWCOLDRST_SET_MSK 0x00000020
240 #define ALT_RSTMGR_STAT_SWCOLDRST_CLR_MSK 0xffffffdf
242 #define ALT_RSTMGR_STAT_SWCOLDRST_RESET 0x0
244 #define ALT_RSTMGR_STAT_SWCOLDRST_GET(value) (((value) & 0x00000020) >> 5)
246 #define ALT_RSTMGR_STAT_SWCOLDRST_SET(value) (((value) << 5) & 0x00000020)
257 #define ALT_RSTMGR_STAT_NRSTPINRST_LSB 8
259 #define ALT_RSTMGR_STAT_NRSTPINRST_MSB 8
261 #define ALT_RSTMGR_STAT_NRSTPINRST_WIDTH 1
263 #define ALT_RSTMGR_STAT_NRSTPINRST_SET_MSK 0x00000100
265 #define ALT_RSTMGR_STAT_NRSTPINRST_CLR_MSK 0xfffffeff
267 #define ALT_RSTMGR_STAT_NRSTPINRST_RESET 0x0
269 #define ALT_RSTMGR_STAT_NRSTPINRST_GET(value) (((value) & 0x00000100) >> 8)
271 #define ALT_RSTMGR_STAT_NRSTPINRST_SET(value) (((value) << 8) & 0x00000100)
282 #define ALT_RSTMGR_STAT_FPGAWARMRST_LSB 9
284 #define ALT_RSTMGR_STAT_FPGAWARMRST_MSB 9
286 #define ALT_RSTMGR_STAT_FPGAWARMRST_WIDTH 1
288 #define ALT_RSTMGR_STAT_FPGAWARMRST_SET_MSK 0x00000200
290 #define ALT_RSTMGR_STAT_FPGAWARMRST_CLR_MSK 0xfffffdff
292 #define ALT_RSTMGR_STAT_FPGAWARMRST_RESET 0x0
294 #define ALT_RSTMGR_STAT_FPGAWARMRST_GET(value) (((value) & 0x00000200) >> 9)
296 #define ALT_RSTMGR_STAT_FPGAWARMRST_SET(value) (((value) << 9) & 0x00000200)
308 #define ALT_RSTMGR_STAT_SWWARMRST_LSB 10
310 #define ALT_RSTMGR_STAT_SWWARMRST_MSB 10
312 #define ALT_RSTMGR_STAT_SWWARMRST_WIDTH 1
314 #define ALT_RSTMGR_STAT_SWWARMRST_SET_MSK 0x00000400
316 #define ALT_RSTMGR_STAT_SWWARMRST_CLR_MSK 0xfffffbff
318 #define ALT_RSTMGR_STAT_SWWARMRST_RESET 0x0
320 #define ALT_RSTMGR_STAT_SWWARMRST_GET(value) (((value) & 0x00000400) >> 10)
322 #define ALT_RSTMGR_STAT_SWWARMRST_SET(value) (((value) << 10) & 0x00000400)
333 #define ALT_RSTMGR_STAT_MPUWD0RST_LSB 11
335 #define ALT_RSTMGR_STAT_MPUWD0RST_MSB 11
337 #define ALT_RSTMGR_STAT_MPUWD0RST_WIDTH 1
339 #define ALT_RSTMGR_STAT_MPUWD0RST_SET_MSK 0x00000800
341 #define ALT_RSTMGR_STAT_MPUWD0RST_CLR_MSK 0xfffff7ff
343 #define ALT_RSTMGR_STAT_MPUWD0RST_RESET 0x0
345 #define ALT_RSTMGR_STAT_MPUWD0RST_GET(value) (((value) & 0x00000800) >> 11)
347 #define ALT_RSTMGR_STAT_MPUWD0RST_SET(value) (((value) << 11) & 0x00000800)
358 #define ALT_RSTMGR_STAT_MPUWD1RST_LSB 12
360 #define ALT_RSTMGR_STAT_MPUWD1RST_MSB 12
362 #define ALT_RSTMGR_STAT_MPUWD1RST_WIDTH 1
364 #define ALT_RSTMGR_STAT_MPUWD1RST_SET_MSK 0x00001000
366 #define ALT_RSTMGR_STAT_MPUWD1RST_CLR_MSK 0xffffefff
368 #define ALT_RSTMGR_STAT_MPUWD1RST_RESET 0x0
370 #define ALT_RSTMGR_STAT_MPUWD1RST_GET(value) (((value) & 0x00001000) >> 12)
372 #define ALT_RSTMGR_STAT_MPUWD1RST_SET(value) (((value) << 12) & 0x00001000)
383 #define ALT_RSTMGR_STAT_L4WD0RST_LSB 13
385 #define ALT_RSTMGR_STAT_L4WD0RST_MSB 13
387 #define ALT_RSTMGR_STAT_L4WD0RST_WIDTH 1
389 #define ALT_RSTMGR_STAT_L4WD0RST_SET_MSK 0x00002000
391 #define ALT_RSTMGR_STAT_L4WD0RST_CLR_MSK 0xffffdfff
393 #define ALT_RSTMGR_STAT_L4WD0RST_RESET 0x0
395 #define ALT_RSTMGR_STAT_L4WD0RST_GET(value) (((value) & 0x00002000) >> 13)
397 #define ALT_RSTMGR_STAT_L4WD0RST_SET(value) (((value) << 13) & 0x00002000)
408 #define ALT_RSTMGR_STAT_L4WD1RST_LSB 14
410 #define ALT_RSTMGR_STAT_L4WD1RST_MSB 14
412 #define ALT_RSTMGR_STAT_L4WD1RST_WIDTH 1
414 #define ALT_RSTMGR_STAT_L4WD1RST_SET_MSK 0x00004000
416 #define ALT_RSTMGR_STAT_L4WD1RST_CLR_MSK 0xffffbfff
418 #define ALT_RSTMGR_STAT_L4WD1RST_RESET 0x0
420 #define ALT_RSTMGR_STAT_L4WD1RST_GET(value) (((value) & 0x00004000) >> 14)
422 #define ALT_RSTMGR_STAT_L4WD1RST_SET(value) (((value) << 14) & 0x00004000)
433 #define ALT_RSTMGR_STAT_FPGADBGRST_LSB 16
435 #define ALT_RSTMGR_STAT_FPGADBGRST_MSB 16
437 #define ALT_RSTMGR_STAT_FPGADBGRST_WIDTH 1
439 #define ALT_RSTMGR_STAT_FPGADBGRST_SET_MSK 0x00010000
441 #define ALT_RSTMGR_STAT_FPGADBGRST_CLR_MSK 0xfffeffff
443 #define ALT_RSTMGR_STAT_FPGADBGRST_RESET 0x0
445 #define ALT_RSTMGR_STAT_FPGADBGRST_GET(value) (((value) & 0x00010000) >> 16)
447 #define ALT_RSTMGR_STAT_FPGADBGRST_SET(value) (((value) << 16) & 0x00010000)
458 #define ALT_RSTMGR_STAT_CDBGREQRST_LSB 17
460 #define ALT_RSTMGR_STAT_CDBGREQRST_MSB 17
462 #define ALT_RSTMGR_STAT_CDBGREQRST_WIDTH 1
464 #define ALT_RSTMGR_STAT_CDBGREQRST_SET_MSK 0x00020000
466 #define ALT_RSTMGR_STAT_CDBGREQRST_CLR_MSK 0xfffdffff
468 #define ALT_RSTMGR_STAT_CDBGREQRST_RESET 0x0
470 #define ALT_RSTMGR_STAT_CDBGREQRST_GET(value) (((value) & 0x00020000) >> 17)
472 #define ALT_RSTMGR_STAT_CDBGREQRST_SET(value) (((value) << 17) & 0x00020000)
485 struct ALT_RSTMGR_STAT_s
487 uint32_t porhpsvoltrst : 1;
488 uint32_t porfpgavoltrst : 1;
489 uint32_t nporpinrst : 1;
490 uint32_t fpgacoldrst : 1;
491 uint32_t configiocoldrst : 1;
492 uint32_t swcoldrst : 1;
494 uint32_t nrstpinrst : 1;
495 uint32_t fpgawarmrst : 1;
496 uint32_t swwarmrst : 1;
497 uint32_t mpuwd0rst : 1;
498 uint32_t mpuwd1rst : 1;
499 uint32_t l4wd0rst : 1;
500 uint32_t l4wd1rst : 1;
502 uint32_t fpgadbgrst : 1;
503 uint32_t cdbgreqrst : 1;
508 typedef volatile struct ALT_RSTMGR_STAT_s ALT_RSTMGR_STAT_t;
512 #define ALT_RSTMGR_STAT_RESET 0x00000000
514 #define ALT_RSTMGR_STAT_OFST 0x0
565 #define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_LSB 0
567 #define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_MSB 0
569 #define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_WIDTH 1
571 #define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_SET_MSK 0x00000001
573 #define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_CLR_MSK 0xfffffffe
575 #define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_RESET 0x0
577 #define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_GET(value) (((value) & 0x00000001) >> 0)
579 #define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_SET(value) (((value) << 0) & 0x00000001)
590 #define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_LSB 1
592 #define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_MSB 1
594 #define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_WIDTH 1
596 #define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_SET_MSK 0x00000002
598 #define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_CLR_MSK 0xfffffffd
600 #define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_RESET 0x0
602 #define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_GET(value) (((value) & 0x00000002) >> 1)
604 #define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_SET(value) (((value) << 1) & 0x00000002)
615 #define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_LSB 2
617 #define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_MSB 2
619 #define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_WIDTH 1
621 #define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_SET_MSK 0x00000004
623 #define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_CLR_MSK 0xfffffffb
625 #define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_RESET 0x0
627 #define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_GET(value) (((value) & 0x00000004) >> 2)
629 #define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_SET(value) (((value) << 2) & 0x00000004)
640 #define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_LSB 3
642 #define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_MSB 3
644 #define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_WIDTH 1
646 #define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_SET_MSK 0x00000008
648 #define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_CLR_MSK 0xfffffff7
650 #define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_RESET 0x0
652 #define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_GET(value) (((value) & 0x00000008) >> 3)
654 #define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_SET(value) (((value) << 3) & 0x00000008)
665 #define ALT_RSTMGR_RAMSTAT_DMARAMCLR_LSB 4
667 #define ALT_RSTMGR_RAMSTAT_DMARAMCLR_MSB 4
669 #define ALT_RSTMGR_RAMSTAT_DMARAMCLR_WIDTH 1
671 #define ALT_RSTMGR_RAMSTAT_DMARAMCLR_SET_MSK 0x00000010
673 #define ALT_RSTMGR_RAMSTAT_DMARAMCLR_CLR_MSK 0xffffffef
675 #define ALT_RSTMGR_RAMSTAT_DMARAMCLR_RESET 0x0
677 #define ALT_RSTMGR_RAMSTAT_DMARAMCLR_GET(value) (((value) & 0x00000010) >> 4)
679 #define ALT_RSTMGR_RAMSTAT_DMARAMCLR_SET(value) (((value) << 4) & 0x00000010)
690 #define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_LSB 5
692 #define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_MSB 5
694 #define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_WIDTH 1
696 #define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_SET_MSK 0x00000020
698 #define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_CLR_MSK 0xffffffdf
700 #define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_RESET 0x0
702 #define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_GET(value) (((value) & 0x00000020) >> 5)
704 #define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_SET(value) (((value) << 5) & 0x00000020)
715 #define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_LSB 6
717 #define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_MSB 6
719 #define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_WIDTH 1
721 #define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_SET_MSK 0x00000040
723 #define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_CLR_MSK 0xffffffbf
725 #define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_RESET 0x0
727 #define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_GET(value) (((value) & 0x00000040) >> 6)
729 #define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_SET(value) (((value) << 6) & 0x00000040)
740 #define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_LSB 7
742 #define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_MSB 7
744 #define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_WIDTH 1
746 #define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_SET_MSK 0x00000080
748 #define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_CLR_MSK 0xffffff7f
750 #define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_RESET 0x0
752 #define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_GET(value) (((value) & 0x00000080) >> 7)
754 #define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_SET(value) (((value) << 7) & 0x00000080)
765 #define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_LSB 8
767 #define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_MSB 8
769 #define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_WIDTH 1
771 #define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_SET_MSK 0x00000100
773 #define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_CLR_MSK 0xfffffeff
775 #define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_RESET 0x0
777 #define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_GET(value) (((value) & 0x00000100) >> 8)
779 #define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_SET(value) (((value) << 8) & 0x00000100)
790 #define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_LSB 9
792 #define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_MSB 9
794 #define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_WIDTH 1
796 #define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_SET_MSK 0x00000200
798 #define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_CLR_MSK 0xfffffdff
800 #define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_RESET 0x0
802 #define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_GET(value) (((value) & 0x00000200) >> 9)
804 #define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_SET(value) (((value) << 9) & 0x00000200)
815 #define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_LSB 10
817 #define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_MSB 10
819 #define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_WIDTH 1
821 #define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_SET_MSK 0x00000400
823 #define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_CLR_MSK 0xfffffbff
825 #define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_RESET 0x0
827 #define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_GET(value) (((value) & 0x00000400) >> 10)
829 #define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_SET(value) (((value) << 10) & 0x00000400)
840 #define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_LSB 11
842 #define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_MSB 11
844 #define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_WIDTH 1
846 #define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_SET_MSK 0x00000800
848 #define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_CLR_MSK 0xfffff7ff
850 #define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_RESET 0x0
852 #define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_GET(value) (((value) & 0x00000800) >> 11)
854 #define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_SET(value) (((value) << 11) & 0x00000800)
865 #define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_LSB 12
867 #define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_MSB 12
869 #define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_WIDTH 1
871 #define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_SET_MSK 0x00001000
873 #define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_CLR_MSK 0xffffefff
875 #define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_RESET 0x0
877 #define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_GET(value) (((value) & 0x00001000) >> 12)
879 #define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_SET(value) (((value) << 12) & 0x00001000)
890 #define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_LSB 13
892 #define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_MSB 13
894 #define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_WIDTH 1
896 #define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_SET_MSK 0x00002000
898 #define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_CLR_MSK 0xffffdfff
900 #define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_RESET 0x0
902 #define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_GET(value) (((value) & 0x00002000) >> 13)
904 #define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_SET(value) (((value) << 13) & 0x00002000)
915 #define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_LSB 14
917 #define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_MSB 14
919 #define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_WIDTH 1
921 #define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_SET_MSK 0x00004000
923 #define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_CLR_MSK 0xffffbfff
925 #define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_RESET 0x0
927 #define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_GET(value) (((value) & 0x00004000) >> 14)
929 #define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_SET(value) (((value) << 14) & 0x00004000)
940 #define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_LSB 15
942 #define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_MSB 15
944 #define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_WIDTH 1
946 #define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_SET_MSK 0x00008000
948 #define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_CLR_MSK 0xffff7fff
950 #define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_RESET 0x0
952 #define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_GET(value) (((value) & 0x00008000) >> 15)
954 #define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_SET(value) (((value) << 15) & 0x00008000)
966 #define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_LSB 16
968 #define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_MSB 16
970 #define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_WIDTH 1
972 #define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_SET_MSK 0x00010000
974 #define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_CLR_MSK 0xfffeffff
976 #define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_RESET 0x0
978 #define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_GET(value) (((value) & 0x00010000) >> 16)
980 #define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_SET(value) (((value) << 16) & 0x00010000)
991 #define ALT_RSTMGR_RAMSTAT_MPUL1TMO_LSB 17
993 #define ALT_RSTMGR_RAMSTAT_MPUL1TMO_MSB 17
995 #define ALT_RSTMGR_RAMSTAT_MPUL1TMO_WIDTH 1
997 #define ALT_RSTMGR_RAMSTAT_MPUL1TMO_SET_MSK 0x00020000
999 #define ALT_RSTMGR_RAMSTAT_MPUL1TMO_CLR_MSK 0xfffdffff
1001 #define ALT_RSTMGR_RAMSTAT_MPUL1TMO_RESET 0x0
1003 #define ALT_RSTMGR_RAMSTAT_MPUL1TMO_GET(value) (((value) & 0x00020000) >> 17)
1005 #define ALT_RSTMGR_RAMSTAT_MPUL1TMO_SET(value) (((value) << 17) & 0x00020000)
1007 #ifndef __ASSEMBLY__
1018 struct ALT_RSTMGR_RAMSTAT_s
1020 uint32_t onchipramclr : 1;
1021 uint32_t otg0ramclr : 1;
1022 uint32_t otg1ramclr : 1;
1023 uint32_t sdmmcramclr : 1;
1024 uint32_t dmaramclr : 1;
1025 uint32_t nandwramclr : 1;
1026 uint32_t nandrramclr : 1;
1027 uint32_t nanderamclr : 1;
1028 uint32_t emac0rxramclr : 1;
1029 uint32_t emac0txramclr : 1;
1030 uint32_t emac1rxramclr : 1;
1031 uint32_t emac1txramclr : 1;
1032 uint32_t emac2txramclr : 1;
1033 uint32_t emac2rxramclr : 1;
1034 uint32_t qspiramclr : 1;
1035 uint32_t mwpramclr : 1;
1036 uint32_t mpul1ramclr : 1;
1037 uint32_t mpul1timeout : 1;
1042 typedef volatile struct ALT_RSTMGR_RAMSTAT_s ALT_RSTMGR_RAMSTAT_t;
1046 #define ALT_RSTMGR_RAMSTAT_RESET 0x00000000
1048 #define ALT_RSTMGR_RAMSTAT_OFST 0x4
1094 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_LSB 0
1096 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_MSB 0
1098 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_WIDTH 1
1100 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_SET_MSK 0x00000001
1102 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_CLR_MSK 0xfffffffe
1104 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_RESET 0x0
1106 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_GET(value) (((value) & 0x00000001) >> 0)
1108 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_SET(value) (((value) << 0) & 0x00000001)
1121 #define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_LSB 1
1123 #define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_MSB 1
1125 #define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_WIDTH 1
1127 #define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_SET_MSK 0x00000002
1129 #define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_CLR_MSK 0xfffffffd
1131 #define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_RESET 0x0
1133 #define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_GET(value) (((value) & 0x00000002) >> 1)
1135 #define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_SET(value) (((value) << 1) & 0x00000002)
1148 #define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_LSB 2
1150 #define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_MSB 2
1152 #define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_WIDTH 1
1154 #define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_SET_MSK 0x00000004
1156 #define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_CLR_MSK 0xfffffffb
1158 #define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_RESET 0x0
1160 #define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_GET(value) (((value) & 0x00000004) >> 2)
1162 #define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_SET(value) (((value) << 2) & 0x00000004)
1175 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_LSB 3
1177 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_MSB 3
1179 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_WIDTH 1
1181 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_SET_MSK 0x00000008
1183 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_CLR_MSK 0xfffffff7
1185 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_RESET 0x0
1187 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_GET(value) (((value) & 0x00000008) >> 3)
1189 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_SET(value) (((value) << 3) & 0x00000008)
1191 #ifndef __ASSEMBLY__
1202 struct ALT_RSTMGR_MISCSTAT_s
1204 uint32_t sdrselfreftimeout : 1;
1205 uint32_t fpgamgrhstimeout : 1;
1206 uint32_t fpgahstimeout : 1;
1207 uint32_t etrstalltimeout : 1;
1212 typedef volatile struct ALT_RSTMGR_MISCSTAT_s ALT_RSTMGR_MISCSTAT_t;
1216 #define ALT_RSTMGR_MISCSTAT_RESET 0x00000000
1218 #define ALT_RSTMGR_MISCSTAT_OFST 0x8
1245 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_LSB 0
1247 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_MSB 0
1249 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_WIDTH 1
1251 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK 0x00000001
1253 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_CLR_MSK 0xfffffffe
1255 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_RESET 0x0
1257 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_GET(value) (((value) & 0x00000001) >> 0)
1259 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET(value) (((value) << 0) & 0x00000001)
1271 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_LSB 1
1273 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_MSB 1
1275 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_WIDTH 1
1277 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK 0x00000002
1279 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_CLR_MSK 0xfffffffd
1281 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_RESET 0x0
1283 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_GET(value) (((value) & 0x00000002) >> 1)
1285 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET(value) (((value) << 1) & 0x00000002)
1287 #ifndef __ASSEMBLY__
1298 struct ALT_RSTMGR_CTL_s
1300 uint32_t swcoldrstreq : 1;
1301 uint32_t swwarmrstreq : 1;
1306 typedef volatile struct ALT_RSTMGR_CTL_s ALT_RSTMGR_CTL_t;
1310 #define ALT_RSTMGR_CTL_RESET 0x00100000
1312 #define ALT_RSTMGR_CTL_OFST 0xc
1344 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_LSB 0
1346 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_MSB 0
1348 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_WIDTH 1
1350 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK 0x00000001
1352 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_CLR_MSK 0xfffffffe
1354 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_RESET 0x0
1356 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_GET(value) (((value) & 0x00000001) >> 0)
1358 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET(value) (((value) << 0) & 0x00000001)
1379 #define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_LSB 1
1381 #define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_MSB 1
1383 #define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_WIDTH 1
1385 #define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET_MSK 0x00000002
1387 #define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_CLR_MSK 0xfffffffd
1389 #define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_RESET 0x0
1391 #define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_GET(value) (((value) & 0x00000002) >> 1)
1393 #define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET(value) (((value) << 1) & 0x00000002)
1411 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_LSB 2
1413 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_MSB 2
1415 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_WIDTH 1
1417 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK 0x00000004
1419 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_CLR_MSK 0xfffffffb
1421 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_RESET 0x0
1423 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_GET(value) (((value) & 0x00000004) >> 2)
1425 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET(value) (((value) << 2) & 0x00000004)
1441 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_LSB 3
1443 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_MSB 3
1445 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_WIDTH 1
1447 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK 0x00000008
1449 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_CLR_MSK 0xfffffff7
1451 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_RESET 0x0
1453 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_GET(value) (((value) & 0x00000008) >> 3)
1455 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET(value) (((value) << 3) & 0x00000008)
1457 #ifndef __ASSEMBLY__
1468 struct ALT_RSTMGR_HDSKEN_s
1470 uint32_t sdrselfrefen : 1;
1471 uint32_t fpgamgrhsen : 1;
1472 uint32_t fpgahsen : 1;
1473 uint32_t etrstallen : 1;
1478 typedef volatile struct ALT_RSTMGR_HDSKEN_s ALT_RSTMGR_HDSKEN_t;
1482 #define ALT_RSTMGR_HDSKEN_RESET 0x00100000
1484 #define ALT_RSTMGR_HDSKEN_OFST 0x10
1524 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_LSB 0
1526 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_MSB 0
1528 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_WIDTH 1
1530 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_SET_MSK 0x00000001
1532 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_CLR_MSK 0xfffffffe
1534 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_RESET 0x0
1536 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_GET(value) (((value) & 0x00000001) >> 0)
1538 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_SET(value) (((value) << 0) & 0x00000001)
1554 #define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_LSB 1
1556 #define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_MSB 1
1558 #define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_WIDTH 1
1560 #define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_SET_MSK 0x00000002
1562 #define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_CLR_MSK 0xfffffffd
1564 #define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_RESET 0x0
1566 #define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_GET(value) (((value) & 0x00000002) >> 1)
1568 #define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_SET(value) (((value) << 1) & 0x00000002)
1583 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_LSB 2
1585 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_MSB 2
1587 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_WIDTH 1
1589 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_SET_MSK 0x00000004
1591 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_CLR_MSK 0xfffffffb
1593 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_RESET 0x0
1595 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_GET(value) (((value) & 0x00000004) >> 2)
1597 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_SET(value) (((value) << 2) & 0x00000004)
1613 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_LSB 3
1615 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_MSB 3
1617 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_WIDTH 1
1619 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_SET_MSK 0x00000008
1621 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_CLR_MSK 0xfffffff7
1623 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_RESET 0x0
1625 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_GET(value) (((value) & 0x00000008) >> 3)
1627 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_SET(value) (((value) << 3) & 0x00000008)
1629 #ifndef __ASSEMBLY__
1640 struct ALT_RSTMGR_HDSKREQ_s
1642 uint32_t sdrselfrefreq : 1;
1643 uint32_t fpgamgrhsreq : 1;
1644 uint32_t fpgahsreq : 1;
1645 uint32_t etrstallreq : 1;
1650 typedef volatile struct ALT_RSTMGR_HDSKREQ_s ALT_RSTMGR_HDSKREQ_t;
1654 #define ALT_RSTMGR_HDSKREQ_RESET 0x00100000
1656 #define ALT_RSTMGR_HDSKREQ_OFST 0x14
1694 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_LSB 0
1696 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_MSB 0
1698 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_WIDTH 1
1700 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_SET_MSK 0x00000001
1702 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_CLR_MSK 0xfffffffe
1704 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_RESET 0x0
1706 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_GET(value) (((value) & 0x00000001) >> 0)
1708 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_SET(value) (((value) << 0) & 0x00000001)
1720 #define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_LSB 1
1722 #define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_MSB 1
1724 #define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_WIDTH 1
1726 #define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_SET_MSK 0x00000002
1728 #define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_CLR_MSK 0xfffffffd
1730 #define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_RESET 0x0
1732 #define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_GET(value) (((value) & 0x00000002) >> 1)
1734 #define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_SET(value) (((value) << 1) & 0x00000002)
1746 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_LSB 2
1748 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_MSB 2
1750 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_WIDTH 1
1752 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_SET_MSK 0x00000004
1754 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_CLR_MSK 0xfffffffb
1756 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_RESET 0x0
1758 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_GET(value) (((value) & 0x00000004) >> 2)
1760 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_SET(value) (((value) << 2) & 0x00000004)
1772 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_LSB 3
1774 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_MSB 3
1776 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_WIDTH 1
1778 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_SET_MSK 0x00000008
1780 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_CLR_MSK 0xfffffff7
1782 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_RESET 0x0
1784 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_GET(value) (((value) & 0x00000008) >> 3)
1786 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_SET(value) (((value) << 3) & 0x00000008)
1801 #define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_LSB 8
1803 #define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_MSB 8
1805 #define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_WIDTH 1
1807 #define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_SET_MSK 0x00000100
1809 #define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_CLR_MSK 0xfffffeff
1811 #define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_RESET 0x0
1813 #define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_GET(value) (((value) & 0x00000100) >> 8)
1815 #define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_SET(value) (((value) << 8) & 0x00000100)
1817 #ifndef __ASSEMBLY__
1828 struct ALT_RSTMGR_HDSKACK_s
1830 const uint32_t sdrselfreqack : 1;
1831 const uint32_t fpgamgrhsack : 1;
1832 const uint32_t fpgahsack : 1;
1833 const uint32_t etrstallack : 1;
1835 uint32_t etrstallwarmrst : 1;
1840 typedef volatile struct ALT_RSTMGR_HDSKACK_s ALT_RSTMGR_HDSKACK_t;
1844 #define ALT_RSTMGR_HDSKACK_RESET 0x00100000
1846 #define ALT_RSTMGR_HDSKACK_OFST 0x18
1876 #define ALT_RSTMGR_COUNTS_NRSTCNT_LSB 0
1878 #define ALT_RSTMGR_COUNTS_NRSTCNT_MSB 19
1880 #define ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH 20
1882 #define ALT_RSTMGR_COUNTS_NRSTCNT_SET_MSK 0x000fffff
1884 #define ALT_RSTMGR_COUNTS_NRSTCNT_CLR_MSK 0xfff00000
1886 #define ALT_RSTMGR_COUNTS_NRSTCNT_RESET 0x800
1888 #define ALT_RSTMGR_COUNTS_NRSTCNT_GET(value) (((value) & 0x000fffff) >> 0)
1890 #define ALT_RSTMGR_COUNTS_NRSTCNT_SET(value) (((value) << 0) & 0x000fffff)
1903 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_LSB 24
1905 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_MSB 31
1907 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH 8
1909 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET_MSK 0xff000000
1911 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_CLR_MSK 0x00ffffff
1913 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_RESET 0x80
1915 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_GET(value) (((value) & 0xff000000) >> 24)
1917 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET(value) (((value) << 24) & 0xff000000)
1919 #ifndef __ASSEMBLY__
1930 struct ALT_RSTMGR_COUNTS_s
1932 uint32_t nrstcnt : 20;
1934 uint32_t warmrstcycles : 8;
1938 typedef volatile struct ALT_RSTMGR_COUNTS_s ALT_RSTMGR_COUNTS_t;
1942 #define ALT_RSTMGR_COUNTS_RESET 0x80000800
1944 #define ALT_RSTMGR_COUNTS_OFST 0x1c
1994 #define ALT_RSTMGR_MPUMODRST_CPU0_LSB 0
1996 #define ALT_RSTMGR_MPUMODRST_CPU0_MSB 0
1998 #define ALT_RSTMGR_MPUMODRST_CPU0_WIDTH 1
2000 #define ALT_RSTMGR_MPUMODRST_CPU0_SET_MSK 0x00000001
2002 #define ALT_RSTMGR_MPUMODRST_CPU0_CLR_MSK 0xfffffffe
2004 #define ALT_RSTMGR_MPUMODRST_CPU0_RESET 0x0
2006 #define ALT_RSTMGR_MPUMODRST_CPU0_GET(value) (((value) & 0x00000001) >> 0)
2008 #define ALT_RSTMGR_MPUMODRST_CPU0_SET(value) (((value) << 0) & 0x00000001)
2026 #define ALT_RSTMGR_MPUMODRST_CPU1_LSB 1
2028 #define ALT_RSTMGR_MPUMODRST_CPU1_MSB 1
2030 #define ALT_RSTMGR_MPUMODRST_CPU1_WIDTH 1
2032 #define ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK 0x00000002
2034 #define ALT_RSTMGR_MPUMODRST_CPU1_CLR_MSK 0xfffffffd
2036 #define ALT_RSTMGR_MPUMODRST_CPU1_RESET 0x1
2038 #define ALT_RSTMGR_MPUMODRST_CPU1_GET(value) (((value) & 0x00000002) >> 1)
2040 #define ALT_RSTMGR_MPUMODRST_CPU1_SET(value) (((value) << 1) & 0x00000002)
2051 #define ALT_RSTMGR_MPUMODRST_WDS_LSB 2
2053 #define ALT_RSTMGR_MPUMODRST_WDS_MSB 2
2055 #define ALT_RSTMGR_MPUMODRST_WDS_WIDTH 1
2057 #define ALT_RSTMGR_MPUMODRST_WDS_SET_MSK 0x00000004
2059 #define ALT_RSTMGR_MPUMODRST_WDS_CLR_MSK 0xfffffffb
2061 #define ALT_RSTMGR_MPUMODRST_WDS_RESET 0x0
2063 #define ALT_RSTMGR_MPUMODRST_WDS_GET(value) (((value) & 0x00000004) >> 2)
2065 #define ALT_RSTMGR_MPUMODRST_WDS_SET(value) (((value) << 2) & 0x00000004)
2078 #define ALT_RSTMGR_MPUMODRST_SCUPER_LSB 3
2080 #define ALT_RSTMGR_MPUMODRST_SCUPER_MSB 3
2082 #define ALT_RSTMGR_MPUMODRST_SCUPER_WIDTH 1
2084 #define ALT_RSTMGR_MPUMODRST_SCUPER_SET_MSK 0x00000008
2086 #define ALT_RSTMGR_MPUMODRST_SCUPER_CLR_MSK 0xfffffff7
2088 #define ALT_RSTMGR_MPUMODRST_SCUPER_RESET 0x0
2090 #define ALT_RSTMGR_MPUMODRST_SCUPER_GET(value) (((value) & 0x00000008) >> 3)
2092 #define ALT_RSTMGR_MPUMODRST_SCUPER_SET(value) (((value) << 3) & 0x00000008)
2094 #ifndef __ASSEMBLY__
2105 struct ALT_RSTMGR_MPUMODRST_s
2110 uint32_t scuper : 1;
2115 typedef volatile struct ALT_RSTMGR_MPUMODRST_s ALT_RSTMGR_MPUMODRST_t;
2119 #define ALT_RSTMGR_MPUMODRST_RESET 0x00000002
2121 #define ALT_RSTMGR_MPUMODRST_OFST 0x20
2194 #define ALT_RSTMGR_PER0MODRST_EMAC0_LSB 0
2196 #define ALT_RSTMGR_PER0MODRST_EMAC0_MSB 0
2198 #define ALT_RSTMGR_PER0MODRST_EMAC0_WIDTH 1
2200 #define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK 0x00000001
2202 #define ALT_RSTMGR_PER0MODRST_EMAC0_CLR_MSK 0xfffffffe
2204 #define ALT_RSTMGR_PER0MODRST_EMAC0_RESET 0x1
2206 #define ALT_RSTMGR_PER0MODRST_EMAC0_GET(value) (((value) & 0x00000001) >> 0)
2208 #define ALT_RSTMGR_PER0MODRST_EMAC0_SET(value) (((value) << 0) & 0x00000001)
2219 #define ALT_RSTMGR_PER0MODRST_EMAC1_LSB 1
2221 #define ALT_RSTMGR_PER0MODRST_EMAC1_MSB 1
2223 #define ALT_RSTMGR_PER0MODRST_EMAC1_WIDTH 1
2225 #define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK 0x00000002
2227 #define ALT_RSTMGR_PER0MODRST_EMAC1_CLR_MSK 0xfffffffd
2229 #define ALT_RSTMGR_PER0MODRST_EMAC1_RESET 0x1
2231 #define ALT_RSTMGR_PER0MODRST_EMAC1_GET(value) (((value) & 0x00000002) >> 1)
2233 #define ALT_RSTMGR_PER0MODRST_EMAC1_SET(value) (((value) << 1) & 0x00000002)
2244 #define ALT_RSTMGR_PER0MODRST_EMAC2_LSB 2
2246 #define ALT_RSTMGR_PER0MODRST_EMAC2_MSB 2
2248 #define ALT_RSTMGR_PER0MODRST_EMAC2_WIDTH 1
2250 #define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK 0x00000004
2252 #define ALT_RSTMGR_PER0MODRST_EMAC2_CLR_MSK 0xfffffffb
2254 #define ALT_RSTMGR_PER0MODRST_EMAC2_RESET 0x1
2256 #define ALT_RSTMGR_PER0MODRST_EMAC2_GET(value) (((value) & 0x00000004) >> 2)
2258 #define ALT_RSTMGR_PER0MODRST_EMAC2_SET(value) (((value) << 2) & 0x00000004)
2269 #define ALT_RSTMGR_PER0MODRST_USB0_LSB 3
2271 #define ALT_RSTMGR_PER0MODRST_USB0_MSB 3
2273 #define ALT_RSTMGR_PER0MODRST_USB0_WIDTH 1
2275 #define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK 0x00000008
2277 #define ALT_RSTMGR_PER0MODRST_USB0_CLR_MSK 0xfffffff7
2279 #define ALT_RSTMGR_PER0MODRST_USB0_RESET 0x1
2281 #define ALT_RSTMGR_PER0MODRST_USB0_GET(value) (((value) & 0x00000008) >> 3)
2283 #define ALT_RSTMGR_PER0MODRST_USB0_SET(value) (((value) << 3) & 0x00000008)
2294 #define ALT_RSTMGR_PER0MODRST_USB1_LSB 4
2296 #define ALT_RSTMGR_PER0MODRST_USB1_MSB 4
2298 #define ALT_RSTMGR_PER0MODRST_USB1_WIDTH 1
2300 #define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK 0x00000010
2302 #define ALT_RSTMGR_PER0MODRST_USB1_CLR_MSK 0xffffffef
2304 #define ALT_RSTMGR_PER0MODRST_USB1_RESET 0x1
2306 #define ALT_RSTMGR_PER0MODRST_USB1_GET(value) (((value) & 0x00000010) >> 4)
2308 #define ALT_RSTMGR_PER0MODRST_USB1_SET(value) (((value) << 4) & 0x00000010)
2319 #define ALT_RSTMGR_PER0MODRST_NAND_LSB 5
2321 #define ALT_RSTMGR_PER0MODRST_NAND_MSB 5
2323 #define ALT_RSTMGR_PER0MODRST_NAND_WIDTH 1
2325 #define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK 0x00000020
2327 #define ALT_RSTMGR_PER0MODRST_NAND_CLR_MSK 0xffffffdf
2329 #define ALT_RSTMGR_PER0MODRST_NAND_RESET 0x1
2331 #define ALT_RSTMGR_PER0MODRST_NAND_GET(value) (((value) & 0x00000020) >> 5)
2333 #define ALT_RSTMGR_PER0MODRST_NAND_SET(value) (((value) << 5) & 0x00000020)
2344 #define ALT_RSTMGR_PER0MODRST_QSPI_LSB 6
2346 #define ALT_RSTMGR_PER0MODRST_QSPI_MSB 6
2348 #define ALT_RSTMGR_PER0MODRST_QSPI_WIDTH 1
2350 #define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK 0x00000040
2352 #define ALT_RSTMGR_PER0MODRST_QSPI_CLR_MSK 0xffffffbf
2354 #define ALT_RSTMGR_PER0MODRST_QSPI_RESET 0x1
2356 #define ALT_RSTMGR_PER0MODRST_QSPI_GET(value) (((value) & 0x00000040) >> 6)
2358 #define ALT_RSTMGR_PER0MODRST_QSPI_SET(value) (((value) << 6) & 0x00000040)
2369 #define ALT_RSTMGR_PER0MODRST_SDMMC_LSB 7
2371 #define ALT_RSTMGR_PER0MODRST_SDMMC_MSB 7
2373 #define ALT_RSTMGR_PER0MODRST_SDMMC_WIDTH 1
2375 #define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK 0x00000080
2377 #define ALT_RSTMGR_PER0MODRST_SDMMC_CLR_MSK 0xffffff7f
2379 #define ALT_RSTMGR_PER0MODRST_SDMMC_RESET 0x1
2381 #define ALT_RSTMGR_PER0MODRST_SDMMC_GET(value) (((value) & 0x00000080) >> 7)
2383 #define ALT_RSTMGR_PER0MODRST_SDMMC_SET(value) (((value) << 7) & 0x00000080)
2394 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_LSB 8
2396 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_MSB 8
2398 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_WIDTH 1
2400 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_SET_MSK 0x00000100
2402 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_CLR_MSK 0xfffffeff
2404 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_RESET 0x1
2406 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_GET(value) (((value) & 0x00000100) >> 8)
2408 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_SET(value) (((value) << 8) & 0x00000100)
2419 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_LSB 9
2421 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_MSB 9
2423 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_WIDTH 1
2425 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_SET_MSK 0x00000200
2427 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_CLR_MSK 0xfffffdff
2429 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_RESET 0x1
2431 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_GET(value) (((value) & 0x00000200) >> 9)
2433 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_SET(value) (((value) << 9) & 0x00000200)
2444 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_LSB 10
2446 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_MSB 10
2448 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_WIDTH 1
2450 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_SET_MSK 0x00000400
2452 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_CLR_MSK 0xfffffbff
2454 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_RESET 0x1
2456 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_GET(value) (((value) & 0x00000400) >> 10)
2458 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_SET(value) (((value) << 10) & 0x00000400)
2469 #define ALT_RSTMGR_PER0MODRST_USB0OCP_LSB 11
2471 #define ALT_RSTMGR_PER0MODRST_USB0OCP_MSB 11
2473 #define ALT_RSTMGR_PER0MODRST_USB0OCP_WIDTH 1
2475 #define ALT_RSTMGR_PER0MODRST_USB0OCP_SET_MSK 0x00000800
2477 #define ALT_RSTMGR_PER0MODRST_USB0OCP_CLR_MSK 0xfffff7ff
2479 #define ALT_RSTMGR_PER0MODRST_USB0OCP_RESET 0x1
2481 #define ALT_RSTMGR_PER0MODRST_USB0OCP_GET(value) (((value) & 0x00000800) >> 11)
2483 #define ALT_RSTMGR_PER0MODRST_USB0OCP_SET(value) (((value) << 11) & 0x00000800)
2494 #define ALT_RSTMGR_PER0MODRST_USB1OCP_LSB 12
2496 #define ALT_RSTMGR_PER0MODRST_USB1OCP_MSB 12
2498 #define ALT_RSTMGR_PER0MODRST_USB1OCP_WIDTH 1
2500 #define ALT_RSTMGR_PER0MODRST_USB1OCP_SET_MSK 0x00001000
2502 #define ALT_RSTMGR_PER0MODRST_USB1OCP_CLR_MSK 0xffffefff
2504 #define ALT_RSTMGR_PER0MODRST_USB1OCP_RESET 0x1
2506 #define ALT_RSTMGR_PER0MODRST_USB1OCP_GET(value) (((value) & 0x00001000) >> 12)
2508 #define ALT_RSTMGR_PER0MODRST_USB1OCP_SET(value) (((value) << 12) & 0x00001000)
2519 #define ALT_RSTMGR_PER0MODRST_NANDOCP_LSB 13
2521 #define ALT_RSTMGR_PER0MODRST_NANDOCP_MSB 13
2523 #define ALT_RSTMGR_PER0MODRST_NANDOCP_WIDTH 1
2525 #define ALT_RSTMGR_PER0MODRST_NANDOCP_SET_MSK 0x00002000
2527 #define ALT_RSTMGR_PER0MODRST_NANDOCP_CLR_MSK 0xffffdfff
2529 #define ALT_RSTMGR_PER0MODRST_NANDOCP_RESET 0x1
2531 #define ALT_RSTMGR_PER0MODRST_NANDOCP_GET(value) (((value) & 0x00002000) >> 13)
2533 #define ALT_RSTMGR_PER0MODRST_NANDOCP_SET(value) (((value) << 13) & 0x00002000)
2544 #define ALT_RSTMGR_PER0MODRST_QSPIOCP_LSB 14
2546 #define ALT_RSTMGR_PER0MODRST_QSPIOCP_MSB 14
2548 #define ALT_RSTMGR_PER0MODRST_QSPIOCP_WIDTH 1
2550 #define ALT_RSTMGR_PER0MODRST_QSPIOCP_SET_MSK 0x00004000
2552 #define ALT_RSTMGR_PER0MODRST_QSPIOCP_CLR_MSK 0xffffbfff
2554 #define ALT_RSTMGR_PER0MODRST_QSPIOCP_RESET 0x1
2556 #define ALT_RSTMGR_PER0MODRST_QSPIOCP_GET(value) (((value) & 0x00004000) >> 14)
2558 #define ALT_RSTMGR_PER0MODRST_QSPIOCP_SET(value) (((value) << 14) & 0x00004000)
2569 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_LSB 15
2571 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_MSB 15
2573 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_WIDTH 1
2575 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_SET_MSK 0x00008000
2577 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_CLR_MSK 0xffff7fff
2579 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_RESET 0x1
2581 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_GET(value) (((value) & 0x00008000) >> 15)
2583 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_SET(value) (((value) << 15) & 0x00008000)
2594 #define ALT_RSTMGR_PER0MODRST_DMA_LSB 16
2596 #define ALT_RSTMGR_PER0MODRST_DMA_MSB 16
2598 #define ALT_RSTMGR_PER0MODRST_DMA_WIDTH 1
2600 #define ALT_RSTMGR_PER0MODRST_DMA_SET_MSK 0x00010000
2602 #define ALT_RSTMGR_PER0MODRST_DMA_CLR_MSK 0xfffeffff
2604 #define ALT_RSTMGR_PER0MODRST_DMA_RESET 0x1
2606 #define ALT_RSTMGR_PER0MODRST_DMA_GET(value) (((value) & 0x00010000) >> 16)
2608 #define ALT_RSTMGR_PER0MODRST_DMA_SET(value) (((value) << 16) & 0x00010000)
2619 #define ALT_RSTMGR_PER0MODRST_SPIM0_LSB 17
2621 #define ALT_RSTMGR_PER0MODRST_SPIM0_MSB 17
2623 #define ALT_RSTMGR_PER0MODRST_SPIM0_WIDTH 1
2625 #define ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK 0x00020000
2627 #define ALT_RSTMGR_PER0MODRST_SPIM0_CLR_MSK 0xfffdffff
2629 #define ALT_RSTMGR_PER0MODRST_SPIM0_RESET 0x1
2631 #define ALT_RSTMGR_PER0MODRST_SPIM0_GET(value) (((value) & 0x00020000) >> 17)
2633 #define ALT_RSTMGR_PER0MODRST_SPIM0_SET(value) (((value) << 17) & 0x00020000)
2644 #define ALT_RSTMGR_PER0MODRST_SPIM1_LSB 18
2646 #define ALT_RSTMGR_PER0MODRST_SPIM1_MSB 18
2648 #define ALT_RSTMGR_PER0MODRST_SPIM1_WIDTH 1
2650 #define ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK 0x00040000
2652 #define ALT_RSTMGR_PER0MODRST_SPIM1_CLR_MSK 0xfffbffff
2654 #define ALT_RSTMGR_PER0MODRST_SPIM1_RESET 0x1
2656 #define ALT_RSTMGR_PER0MODRST_SPIM1_GET(value) (((value) & 0x00040000) >> 18)
2658 #define ALT_RSTMGR_PER0MODRST_SPIM1_SET(value) (((value) << 18) & 0x00040000)
2669 #define ALT_RSTMGR_PER0MODRST_SPIS0_LSB 19
2671 #define ALT_RSTMGR_PER0MODRST_SPIS0_MSB 19
2673 #define ALT_RSTMGR_PER0MODRST_SPIS0_WIDTH 1
2675 #define ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK 0x00080000
2677 #define ALT_RSTMGR_PER0MODRST_SPIS0_CLR_MSK 0xfff7ffff
2679 #define ALT_RSTMGR_PER0MODRST_SPIS0_RESET 0x1
2681 #define ALT_RSTMGR_PER0MODRST_SPIS0_GET(value) (((value) & 0x00080000) >> 19)
2683 #define ALT_RSTMGR_PER0MODRST_SPIS0_SET(value) (((value) << 19) & 0x00080000)
2694 #define ALT_RSTMGR_PER0MODRST_SPIS1_LSB 20
2696 #define ALT_RSTMGR_PER0MODRST_SPIS1_MSB 20
2698 #define ALT_RSTMGR_PER0MODRST_SPIS1_WIDTH 1
2700 #define ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK 0x00100000
2702 #define ALT_RSTMGR_PER0MODRST_SPIS1_CLR_MSK 0xffefffff
2704 #define ALT_RSTMGR_PER0MODRST_SPIS1_RESET 0x1
2706 #define ALT_RSTMGR_PER0MODRST_SPIS1_GET(value) (((value) & 0x00100000) >> 20)
2708 #define ALT_RSTMGR_PER0MODRST_SPIS1_SET(value) (((value) << 20) & 0x00100000)
2719 #define ALT_RSTMGR_PER0MODRST_DMAOCP_LSB 21
2721 #define ALT_RSTMGR_PER0MODRST_DMAOCP_MSB 21
2723 #define ALT_RSTMGR_PER0MODRST_DMAOCP_WIDTH 1
2725 #define ALT_RSTMGR_PER0MODRST_DMAOCP_SET_MSK 0x00200000
2727 #define ALT_RSTMGR_PER0MODRST_DMAOCP_CLR_MSK 0xffdfffff
2729 #define ALT_RSTMGR_PER0MODRST_DMAOCP_RESET 0x1
2731 #define ALT_RSTMGR_PER0MODRST_DMAOCP_GET(value) (((value) & 0x00200000) >> 21)
2733 #define ALT_RSTMGR_PER0MODRST_DMAOCP_SET(value) (((value) << 21) & 0x00200000)
2744 #define ALT_RSTMGR_PER0MODRST_EMACPTP_LSB 22
2746 #define ALT_RSTMGR_PER0MODRST_EMACPTP_MSB 22
2748 #define ALT_RSTMGR_PER0MODRST_EMACPTP_WIDTH 1
2750 #define ALT_RSTMGR_PER0MODRST_EMACPTP_SET_MSK 0x00400000
2752 #define ALT_RSTMGR_PER0MODRST_EMACPTP_CLR_MSK 0xffbfffff
2754 #define ALT_RSTMGR_PER0MODRST_EMACPTP_RESET 0x1
2756 #define ALT_RSTMGR_PER0MODRST_EMACPTP_GET(value) (((value) & 0x00400000) >> 22)
2758 #define ALT_RSTMGR_PER0MODRST_EMACPTP_SET(value) (((value) << 22) & 0x00400000)
2770 #define ALT_RSTMGR_PER0MODRST_DMAIF0_LSB 24
2772 #define ALT_RSTMGR_PER0MODRST_DMAIF0_MSB 24
2774 #define ALT_RSTMGR_PER0MODRST_DMAIF0_WIDTH 1
2776 #define ALT_RSTMGR_PER0MODRST_DMAIF0_SET_MSK 0x01000000
2778 #define ALT_RSTMGR_PER0MODRST_DMAIF0_CLR_MSK 0xfeffffff
2780 #define ALT_RSTMGR_PER0MODRST_DMAIF0_RESET 0x1
2782 #define ALT_RSTMGR_PER0MODRST_DMAIF0_GET(value) (((value) & 0x01000000) >> 24)
2784 #define ALT_RSTMGR_PER0MODRST_DMAIF0_SET(value) (((value) << 24) & 0x01000000)
2796 #define ALT_RSTMGR_PER0MODRST_DMAIF1_LSB 25
2798 #define ALT_RSTMGR_PER0MODRST_DMAIF1_MSB 25
2800 #define ALT_RSTMGR_PER0MODRST_DMAIF1_WIDTH 1
2802 #define ALT_RSTMGR_PER0MODRST_DMAIF1_SET_MSK 0x02000000
2804 #define ALT_RSTMGR_PER0MODRST_DMAIF1_CLR_MSK 0xfdffffff
2806 #define ALT_RSTMGR_PER0MODRST_DMAIF1_RESET 0x1
2808 #define ALT_RSTMGR_PER0MODRST_DMAIF1_GET(value) (((value) & 0x02000000) >> 25)
2810 #define ALT_RSTMGR_PER0MODRST_DMAIF1_SET(value) (((value) << 25) & 0x02000000)
2822 #define ALT_RSTMGR_PER0MODRST_DMAIF2_LSB 26
2824 #define ALT_RSTMGR_PER0MODRST_DMAIF2_MSB 26
2826 #define ALT_RSTMGR_PER0MODRST_DMAIF2_WIDTH 1
2828 #define ALT_RSTMGR_PER0MODRST_DMAIF2_SET_MSK 0x04000000
2830 #define ALT_RSTMGR_PER0MODRST_DMAIF2_CLR_MSK 0xfbffffff
2832 #define ALT_RSTMGR_PER0MODRST_DMAIF2_RESET 0x1
2834 #define ALT_RSTMGR_PER0MODRST_DMAIF2_GET(value) (((value) & 0x04000000) >> 26)
2836 #define ALT_RSTMGR_PER0MODRST_DMAIF2_SET(value) (((value) << 26) & 0x04000000)
2848 #define ALT_RSTMGR_PER0MODRST_DMAIF3_LSB 27
2850 #define ALT_RSTMGR_PER0MODRST_DMAIF3_MSB 27
2852 #define ALT_RSTMGR_PER0MODRST_DMAIF3_WIDTH 1
2854 #define ALT_RSTMGR_PER0MODRST_DMAIF3_SET_MSK 0x08000000
2856 #define ALT_RSTMGR_PER0MODRST_DMAIF3_CLR_MSK 0xf7ffffff
2858 #define ALT_RSTMGR_PER0MODRST_DMAIF3_RESET 0x1
2860 #define ALT_RSTMGR_PER0MODRST_DMAIF3_GET(value) (((value) & 0x08000000) >> 27)
2862 #define ALT_RSTMGR_PER0MODRST_DMAIF3_SET(value) (((value) << 27) & 0x08000000)
2874 #define ALT_RSTMGR_PER0MODRST_DMAIF4_LSB 28
2876 #define ALT_RSTMGR_PER0MODRST_DMAIF4_MSB 28
2878 #define ALT_RSTMGR_PER0MODRST_DMAIF4_WIDTH 1
2880 #define ALT_RSTMGR_PER0MODRST_DMAIF4_SET_MSK 0x10000000
2882 #define ALT_RSTMGR_PER0MODRST_DMAIF4_CLR_MSK 0xefffffff
2884 #define ALT_RSTMGR_PER0MODRST_DMAIF4_RESET 0x1
2886 #define ALT_RSTMGR_PER0MODRST_DMAIF4_GET(value) (((value) & 0x10000000) >> 28)
2888 #define ALT_RSTMGR_PER0MODRST_DMAIF4_SET(value) (((value) << 28) & 0x10000000)
2900 #define ALT_RSTMGR_PER0MODRST_DMAIF5_LSB 29
2902 #define ALT_RSTMGR_PER0MODRST_DMAIF5_MSB 29
2904 #define ALT_RSTMGR_PER0MODRST_DMAIF5_WIDTH 1
2906 #define ALT_RSTMGR_PER0MODRST_DMAIF5_SET_MSK 0x20000000
2908 #define ALT_RSTMGR_PER0MODRST_DMAIF5_CLR_MSK 0xdfffffff
2910 #define ALT_RSTMGR_PER0MODRST_DMAIF5_RESET 0x1
2912 #define ALT_RSTMGR_PER0MODRST_DMAIF5_GET(value) (((value) & 0x20000000) >> 29)
2914 #define ALT_RSTMGR_PER0MODRST_DMAIF5_SET(value) (((value) << 29) & 0x20000000)
2926 #define ALT_RSTMGR_PER0MODRST_DMAIF6_LSB 30
2928 #define ALT_RSTMGR_PER0MODRST_DMAIF6_MSB 30
2930 #define ALT_RSTMGR_PER0MODRST_DMAIF6_WIDTH 1
2932 #define ALT_RSTMGR_PER0MODRST_DMAIF6_SET_MSK 0x40000000
2934 #define ALT_RSTMGR_PER0MODRST_DMAIF6_CLR_MSK 0xbfffffff
2936 #define ALT_RSTMGR_PER0MODRST_DMAIF6_RESET 0x1
2938 #define ALT_RSTMGR_PER0MODRST_DMAIF6_GET(value) (((value) & 0x40000000) >> 30)
2940 #define ALT_RSTMGR_PER0MODRST_DMAIF6_SET(value) (((value) << 30) & 0x40000000)
2952 #define ALT_RSTMGR_PER0MODRST_DMAIF7_LSB 31
2954 #define ALT_RSTMGR_PER0MODRST_DMAIF7_MSB 31
2956 #define ALT_RSTMGR_PER0MODRST_DMAIF7_WIDTH 1
2958 #define ALT_RSTMGR_PER0MODRST_DMAIF7_SET_MSK 0x80000000
2960 #define ALT_RSTMGR_PER0MODRST_DMAIF7_CLR_MSK 0x7fffffff
2962 #define ALT_RSTMGR_PER0MODRST_DMAIF7_RESET 0x1
2964 #define ALT_RSTMGR_PER0MODRST_DMAIF7_GET(value) (((value) & 0x80000000) >> 31)
2966 #define ALT_RSTMGR_PER0MODRST_DMAIF7_SET(value) (((value) << 31) & 0x80000000)
2968 #ifndef __ASSEMBLY__
2979 struct ALT_RSTMGR_PER0MODRST_s
2989 uint32_t emac0ocp : 1;
2990 uint32_t emac1ocp : 1;
2991 uint32_t emac2ocp : 1;
2992 uint32_t usb0ocp : 1;
2993 uint32_t usb1ocp : 1;
2994 uint32_t nandocp : 1;
2995 uint32_t qspiocp : 1;
2996 uint32_t sdmmcocp : 1;
3002 uint32_t dmaocp : 1;
3003 uint32_t emacptp : 1;
3005 uint32_t dmaif0 : 1;
3006 uint32_t dmaif1 : 1;
3007 uint32_t dmaif2 : 1;
3008 uint32_t dmaif3 : 1;
3009 uint32_t dmaif4 : 1;
3010 uint32_t dmaif5 : 1;
3011 uint32_t dmaif6 : 1;
3012 uint32_t dmaif7 : 1;
3016 typedef volatile struct ALT_RSTMGR_PER0MODRST_s ALT_RSTMGR_PER0MODRST_t;
3020 #define ALT_RSTMGR_PER0MODRST_RESET 0xff7fffff
3022 #define ALT_RSTMGR_PER0MODRST_OFST 0x24
3081 #define ALT_RSTMGR_PER1MODRST_WD0_LSB 0
3083 #define ALT_RSTMGR_PER1MODRST_WD0_MSB 0
3085 #define ALT_RSTMGR_PER1MODRST_WD0_WIDTH 1
3087 #define ALT_RSTMGR_PER1MODRST_WD0_SET_MSK 0x00000001
3089 #define ALT_RSTMGR_PER1MODRST_WD0_CLR_MSK 0xfffffffe
3091 #define ALT_RSTMGR_PER1MODRST_WD0_RESET 0x1
3093 #define ALT_RSTMGR_PER1MODRST_WD0_GET(value) (((value) & 0x00000001) >> 0)
3095 #define ALT_RSTMGR_PER1MODRST_WD0_SET(value) (((value) << 0) & 0x00000001)
3106 #define ALT_RSTMGR_PER1MODRST_WD1_LSB 1
3108 #define ALT_RSTMGR_PER1MODRST_WD1_MSB 1
3110 #define ALT_RSTMGR_PER1MODRST_WD1_WIDTH 1
3112 #define ALT_RSTMGR_PER1MODRST_WD1_SET_MSK 0x00000002
3114 #define ALT_RSTMGR_PER1MODRST_WD1_CLR_MSK 0xfffffffd
3116 #define ALT_RSTMGR_PER1MODRST_WD1_RESET 0x1
3118 #define ALT_RSTMGR_PER1MODRST_WD1_GET(value) (((value) & 0x00000002) >> 1)
3120 #define ALT_RSTMGR_PER1MODRST_WD1_SET(value) (((value) << 1) & 0x00000002)
3131 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_LSB 2
3133 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_MSB 2
3135 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_WIDTH 1
3137 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_SET_MSK 0x00000004
3139 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_CLR_MSK 0xfffffffb
3141 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_RESET 0x1
3143 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_GET(value) (((value) & 0x00000004) >> 2)
3145 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_SET(value) (((value) << 2) & 0x00000004)
3156 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_LSB 3
3158 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_MSB 3
3160 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_WIDTH 1
3162 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_SET_MSK 0x00000008
3164 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_CLR_MSK 0xfffffff7
3166 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_RESET 0x1
3168 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_GET(value) (((value) & 0x00000008) >> 3)
3170 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_SET(value) (((value) << 3) & 0x00000008)
3181 #define ALT_RSTMGR_PER1MODRST_SPTMR0_LSB 4
3183 #define ALT_RSTMGR_PER1MODRST_SPTMR0_MSB 4
3185 #define ALT_RSTMGR_PER1MODRST_SPTMR0_WIDTH 1
3187 #define ALT_RSTMGR_PER1MODRST_SPTMR0_SET_MSK 0x00000010
3189 #define ALT_RSTMGR_PER1MODRST_SPTMR0_CLR_MSK 0xffffffef
3191 #define ALT_RSTMGR_PER1MODRST_SPTMR0_RESET 0x1
3193 #define ALT_RSTMGR_PER1MODRST_SPTMR0_GET(value) (((value) & 0x00000010) >> 4)
3195 #define ALT_RSTMGR_PER1MODRST_SPTMR0_SET(value) (((value) << 4) & 0x00000010)
3206 #define ALT_RSTMGR_PER1MODRST_SPTMR1_LSB 5
3208 #define ALT_RSTMGR_PER1MODRST_SPTMR1_MSB 5
3210 #define ALT_RSTMGR_PER1MODRST_SPTMR1_WIDTH 1
3212 #define ALT_RSTMGR_PER1MODRST_SPTMR1_SET_MSK 0x00000020
3214 #define ALT_RSTMGR_PER1MODRST_SPTMR1_CLR_MSK 0xffffffdf
3216 #define ALT_RSTMGR_PER1MODRST_SPTMR1_RESET 0x1
3218 #define ALT_RSTMGR_PER1MODRST_SPTMR1_GET(value) (((value) & 0x00000020) >> 5)
3220 #define ALT_RSTMGR_PER1MODRST_SPTMR1_SET(value) (((value) << 5) & 0x00000020)
3231 #define ALT_RSTMGR_PER1MODRST_I2C0_LSB 8
3233 #define ALT_RSTMGR_PER1MODRST_I2C0_MSB 8
3235 #define ALT_RSTMGR_PER1MODRST_I2C0_WIDTH 1
3237 #define ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK 0x00000100
3239 #define ALT_RSTMGR_PER1MODRST_I2C0_CLR_MSK 0xfffffeff
3241 #define ALT_RSTMGR_PER1MODRST_I2C0_RESET 0x1
3243 #define ALT_RSTMGR_PER1MODRST_I2C0_GET(value) (((value) & 0x00000100) >> 8)
3245 #define ALT_RSTMGR_PER1MODRST_I2C0_SET(value) (((value) << 8) & 0x00000100)
3256 #define ALT_RSTMGR_PER1MODRST_I2C1_LSB 9
3258 #define ALT_RSTMGR_PER1MODRST_I2C1_MSB 9
3260 #define ALT_RSTMGR_PER1MODRST_I2C1_WIDTH 1
3262 #define ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK 0x00000200
3264 #define ALT_RSTMGR_PER1MODRST_I2C1_CLR_MSK 0xfffffdff
3266 #define ALT_RSTMGR_PER1MODRST_I2C1_RESET 0x1
3268 #define ALT_RSTMGR_PER1MODRST_I2C1_GET(value) (((value) & 0x00000200) >> 9)
3270 #define ALT_RSTMGR_PER1MODRST_I2C1_SET(value) (((value) << 9) & 0x00000200)
3281 #define ALT_RSTMGR_PER1MODRST_I2C2_LSB 10
3283 #define ALT_RSTMGR_PER1MODRST_I2C2_MSB 10
3285 #define ALT_RSTMGR_PER1MODRST_I2C2_WIDTH 1
3287 #define ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK 0x00000400
3289 #define ALT_RSTMGR_PER1MODRST_I2C2_CLR_MSK 0xfffffbff
3291 #define ALT_RSTMGR_PER1MODRST_I2C2_RESET 0x1
3293 #define ALT_RSTMGR_PER1MODRST_I2C2_GET(value) (((value) & 0x00000400) >> 10)
3295 #define ALT_RSTMGR_PER1MODRST_I2C2_SET(value) (((value) << 10) & 0x00000400)
3306 #define ALT_RSTMGR_PER1MODRST_I2C3_LSB 11
3308 #define ALT_RSTMGR_PER1MODRST_I2C3_MSB 11
3310 #define ALT_RSTMGR_PER1MODRST_I2C3_WIDTH 1
3312 #define ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK 0x00000800
3314 #define ALT_RSTMGR_PER1MODRST_I2C3_CLR_MSK 0xfffff7ff
3316 #define ALT_RSTMGR_PER1MODRST_I2C3_RESET 0x1
3318 #define ALT_RSTMGR_PER1MODRST_I2C3_GET(value) (((value) & 0x00000800) >> 11)
3320 #define ALT_RSTMGR_PER1MODRST_I2C3_SET(value) (((value) << 11) & 0x00000800)
3331 #define ALT_RSTMGR_PER1MODRST_I2C4_LSB 12
3333 #define ALT_RSTMGR_PER1MODRST_I2C4_MSB 12
3335 #define ALT_RSTMGR_PER1MODRST_I2C4_WIDTH 1
3337 #define ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK 0x00001000
3339 #define ALT_RSTMGR_PER1MODRST_I2C4_CLR_MSK 0xffffefff
3341 #define ALT_RSTMGR_PER1MODRST_I2C4_RESET 0x1
3343 #define ALT_RSTMGR_PER1MODRST_I2C4_GET(value) (((value) & 0x00001000) >> 12)
3345 #define ALT_RSTMGR_PER1MODRST_I2C4_SET(value) (((value) << 12) & 0x00001000)
3356 #define ALT_RSTMGR_PER1MODRST_UART0_LSB 16
3358 #define ALT_RSTMGR_PER1MODRST_UART0_MSB 16
3360 #define ALT_RSTMGR_PER1MODRST_UART0_WIDTH 1
3362 #define ALT_RSTMGR_PER1MODRST_UART0_SET_MSK 0x00010000
3364 #define ALT_RSTMGR_PER1MODRST_UART0_CLR_MSK 0xfffeffff
3366 #define ALT_RSTMGR_PER1MODRST_UART0_RESET 0x1
3368 #define ALT_RSTMGR_PER1MODRST_UART0_GET(value) (((value) & 0x00010000) >> 16)
3370 #define ALT_RSTMGR_PER1MODRST_UART0_SET(value) (((value) << 16) & 0x00010000)
3381 #define ALT_RSTMGR_PER1MODRST_UART1_LSB 17
3383 #define ALT_RSTMGR_PER1MODRST_UART1_MSB 17
3385 #define ALT_RSTMGR_PER1MODRST_UART1_WIDTH 1
3387 #define ALT_RSTMGR_PER1MODRST_UART1_SET_MSK 0x00020000
3389 #define ALT_RSTMGR_PER1MODRST_UART1_CLR_MSK 0xfffdffff
3391 #define ALT_RSTMGR_PER1MODRST_UART1_RESET 0x1
3393 #define ALT_RSTMGR_PER1MODRST_UART1_GET(value) (((value) & 0x00020000) >> 17)
3395 #define ALT_RSTMGR_PER1MODRST_UART1_SET(value) (((value) << 17) & 0x00020000)
3406 #define ALT_RSTMGR_PER1MODRST_GPIO0_LSB 24
3408 #define ALT_RSTMGR_PER1MODRST_GPIO0_MSB 24
3410 #define ALT_RSTMGR_PER1MODRST_GPIO0_WIDTH 1
3412 #define ALT_RSTMGR_PER1MODRST_GPIO0_SET_MSK 0x01000000
3414 #define ALT_RSTMGR_PER1MODRST_GPIO0_CLR_MSK 0xfeffffff
3416 #define ALT_RSTMGR_PER1MODRST_GPIO0_RESET 0x1
3418 #define ALT_RSTMGR_PER1MODRST_GPIO0_GET(value) (((value) & 0x01000000) >> 24)
3420 #define ALT_RSTMGR_PER1MODRST_GPIO0_SET(value) (((value) << 24) & 0x01000000)
3431 #define ALT_RSTMGR_PER1MODRST_GPIO1_LSB 25
3433 #define ALT_RSTMGR_PER1MODRST_GPIO1_MSB 25
3435 #define ALT_RSTMGR_PER1MODRST_GPIO1_WIDTH 1
3437 #define ALT_RSTMGR_PER1MODRST_GPIO1_SET_MSK 0x02000000
3439 #define ALT_RSTMGR_PER1MODRST_GPIO1_CLR_MSK 0xfdffffff
3441 #define ALT_RSTMGR_PER1MODRST_GPIO1_RESET 0x1
3443 #define ALT_RSTMGR_PER1MODRST_GPIO1_GET(value) (((value) & 0x02000000) >> 25)
3445 #define ALT_RSTMGR_PER1MODRST_GPIO1_SET(value) (((value) << 25) & 0x02000000)
3456 #define ALT_RSTMGR_PER1MODRST_GPIO2_LSB 26
3458 #define ALT_RSTMGR_PER1MODRST_GPIO2_MSB 26
3460 #define ALT_RSTMGR_PER1MODRST_GPIO2_WIDTH 1
3462 #define ALT_RSTMGR_PER1MODRST_GPIO2_SET_MSK 0x04000000
3464 #define ALT_RSTMGR_PER1MODRST_GPIO2_CLR_MSK 0xfbffffff
3466 #define ALT_RSTMGR_PER1MODRST_GPIO2_RESET 0x1
3468 #define ALT_RSTMGR_PER1MODRST_GPIO2_GET(value) (((value) & 0x04000000) >> 26)
3470 #define ALT_RSTMGR_PER1MODRST_GPIO2_SET(value) (((value) << 26) & 0x04000000)
3472 #ifndef __ASSEMBLY__
3483 struct ALT_RSTMGR_PER1MODRST_s
3485 uint32_t watchdog0 : 1;
3486 uint32_t watchdog1 : 1;
3487 uint32_t l4systimer0 : 1;
3488 uint32_t l4systimer1 : 1;
3489 uint32_t sptimer0 : 1;
3490 uint32_t sptimer1 : 1;
3508 typedef volatile struct ALT_RSTMGR_PER1MODRST_s ALT_RSTMGR_PER1MODRST_t;
3512 #define ALT_RSTMGR_PER1MODRST_RESET 0x07031f3f
3514 #define ALT_RSTMGR_PER1MODRST_OFST 0x28
3561 #define ALT_RSTMGR_BRGMODRST_H2F_LSB 0
3563 #define ALT_RSTMGR_BRGMODRST_H2F_MSB 0
3565 #define ALT_RSTMGR_BRGMODRST_H2F_WIDTH 1
3567 #define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK 0x00000001
3569 #define ALT_RSTMGR_BRGMODRST_H2F_CLR_MSK 0xfffffffe
3571 #define ALT_RSTMGR_BRGMODRST_H2F_RESET 0x1
3573 #define ALT_RSTMGR_BRGMODRST_H2F_GET(value) (((value) & 0x00000001) >> 0)
3575 #define ALT_RSTMGR_BRGMODRST_H2F_SET(value) (((value) << 0) & 0x00000001)
3586 #define ALT_RSTMGR_BRGMODRST_LWH2F_LSB 1
3588 #define ALT_RSTMGR_BRGMODRST_LWH2F_MSB 1
3590 #define ALT_RSTMGR_BRGMODRST_LWH2F_WIDTH 1
3592 #define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK 0x00000002
3594 #define ALT_RSTMGR_BRGMODRST_LWH2F_CLR_MSK 0xfffffffd
3596 #define ALT_RSTMGR_BRGMODRST_LWH2F_RESET 0x1
3598 #define ALT_RSTMGR_BRGMODRST_LWH2F_GET(value) (((value) & 0x00000002) >> 1)
3600 #define ALT_RSTMGR_BRGMODRST_LWH2F_SET(value) (((value) << 1) & 0x00000002)
3611 #define ALT_RSTMGR_BRGMODRST_F2H_LSB 2
3613 #define ALT_RSTMGR_BRGMODRST_F2H_MSB 2
3615 #define ALT_RSTMGR_BRGMODRST_F2H_WIDTH 1
3617 #define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK 0x00000004
3619 #define ALT_RSTMGR_BRGMODRST_F2H_CLR_MSK 0xfffffffb
3621 #define ALT_RSTMGR_BRGMODRST_F2H_RESET 0x1
3623 #define ALT_RSTMGR_BRGMODRST_F2H_GET(value) (((value) & 0x00000004) >> 2)
3625 #define ALT_RSTMGR_BRGMODRST_F2H_SET(value) (((value) << 2) & 0x00000004)
3636 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_LSB 3
3638 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_MSB 3
3640 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_WIDTH 1
3642 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK 0x00000008
3644 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_CLR_MSK 0xfffffff7
3646 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_RESET 0x1
3648 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_GET(value) (((value) & 0x00000008) >> 3)
3650 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET(value) (((value) << 3) & 0x00000008)
3661 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_LSB 4
3663 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_MSB 4
3665 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_WIDTH 1
3667 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK 0x00000010
3669 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_CLR_MSK 0xffffffef
3671 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_RESET 0x1
3673 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_GET(value) (((value) & 0x00000010) >> 4)
3675 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET(value) (((value) << 4) & 0x00000010)
3686 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_LSB 5
3688 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_MSB 5
3690 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_WIDTH 1
3692 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK 0x00000020
3694 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_CLR_MSK 0xffffffdf
3696 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_RESET 0x1
3698 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_GET(value) (((value) & 0x00000020) >> 5)
3700 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET(value) (((value) << 5) & 0x00000020)
3711 #define ALT_RSTMGR_BRGMODRST_DDRSCH_LSB 6
3713 #define ALT_RSTMGR_BRGMODRST_DDRSCH_MSB 6
3715 #define ALT_RSTMGR_BRGMODRST_DDRSCH_WIDTH 1
3717 #define ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK 0x00000040
3719 #define ALT_RSTMGR_BRGMODRST_DDRSCH_CLR_MSK 0xffffffbf
3721 #define ALT_RSTMGR_BRGMODRST_DDRSCH_RESET 0x1
3723 #define ALT_RSTMGR_BRGMODRST_DDRSCH_GET(value) (((value) & 0x00000040) >> 6)
3725 #define ALT_RSTMGR_BRGMODRST_DDRSCH_SET(value) (((value) << 6) & 0x00000040)
3727 #ifndef __ASSEMBLY__
3738 struct ALT_RSTMGR_BRGMODRST_s
3740 uint32_t hps2fpga : 1;
3741 uint32_t lwhps2fpga : 1;
3742 uint32_t fpga2hps : 1;
3743 uint32_t f2ssdram0 : 1;
3744 uint32_t f2ssdram1 : 1;
3745 uint32_t f2ssdram2 : 1;
3746 uint32_t ddrsch : 1;
3751 typedef volatile struct ALT_RSTMGR_BRGMODRST_s ALT_RSTMGR_BRGMODRST_t;
3755 #define ALT_RSTMGR_BRGMODRST_RESET 0x0000007f
3757 #define ALT_RSTMGR_BRGMODRST_OFST 0x2c
3799 #define ALT_RSTMGR_SYSMODRST_ROM_LSB 0
3801 #define ALT_RSTMGR_SYSMODRST_ROM_MSB 0
3803 #define ALT_RSTMGR_SYSMODRST_ROM_WIDTH 1
3805 #define ALT_RSTMGR_SYSMODRST_ROM_SET_MSK 0x00000001
3807 #define ALT_RSTMGR_SYSMODRST_ROM_CLR_MSK 0xfffffffe
3809 #define ALT_RSTMGR_SYSMODRST_ROM_RESET 0x0
3811 #define ALT_RSTMGR_SYSMODRST_ROM_GET(value) (((value) & 0x00000001) >> 0)
3813 #define ALT_RSTMGR_SYSMODRST_ROM_SET(value) (((value) << 0) & 0x00000001)
3824 #define ALT_RSTMGR_SYSMODRST_OCRAM_LSB 1
3826 #define ALT_RSTMGR_SYSMODRST_OCRAM_MSB 1
3828 #define ALT_RSTMGR_SYSMODRST_OCRAM_WIDTH 1
3830 #define ALT_RSTMGR_SYSMODRST_OCRAM_SET_MSK 0x00000002
3832 #define ALT_RSTMGR_SYSMODRST_OCRAM_CLR_MSK 0xfffffffd
3834 #define ALT_RSTMGR_SYSMODRST_OCRAM_RESET 0x0
3836 #define ALT_RSTMGR_SYSMODRST_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
3838 #define ALT_RSTMGR_SYSMODRST_OCRAM_SET(value) (((value) << 1) & 0x00000002)
3849 #define ALT_RSTMGR_SYSMODRST_FPGAMGR_LSB 3
3851 #define ALT_RSTMGR_SYSMODRST_FPGAMGR_MSB 3
3853 #define ALT_RSTMGR_SYSMODRST_FPGAMGR_WIDTH 1
3855 #define ALT_RSTMGR_SYSMODRST_FPGAMGR_SET_MSK 0x00000008
3857 #define ALT_RSTMGR_SYSMODRST_FPGAMGR_CLR_MSK 0xfffffff7
3859 #define ALT_RSTMGR_SYSMODRST_FPGAMGR_RESET 0x0
3861 #define ALT_RSTMGR_SYSMODRST_FPGAMGR_GET(value) (((value) & 0x00000008) >> 3)
3863 #define ALT_RSTMGR_SYSMODRST_FPGAMGR_SET(value) (((value) << 3) & 0x00000008)
3875 #define ALT_RSTMGR_SYSMODRST_S2F_LSB 4
3877 #define ALT_RSTMGR_SYSMODRST_S2F_MSB 4
3879 #define ALT_RSTMGR_SYSMODRST_S2F_WIDTH 1
3881 #define ALT_RSTMGR_SYSMODRST_S2F_SET_MSK 0x00000010
3883 #define ALT_RSTMGR_SYSMODRST_S2F_CLR_MSK 0xffffffef
3885 #define ALT_RSTMGR_SYSMODRST_S2F_RESET 0x0
3887 #define ALT_RSTMGR_SYSMODRST_S2F_GET(value) (((value) & 0x00000010) >> 4)
3889 #define ALT_RSTMGR_SYSMODRST_S2F_SET(value) (((value) << 4) & 0x00000010)
3900 #define ALT_RSTMGR_SYSMODRST_SYSDBG_LSB 5
3902 #define ALT_RSTMGR_SYSMODRST_SYSDBG_MSB 5
3904 #define ALT_RSTMGR_SYSMODRST_SYSDBG_WIDTH 1
3906 #define ALT_RSTMGR_SYSMODRST_SYSDBG_SET_MSK 0x00000020
3908 #define ALT_RSTMGR_SYSMODRST_SYSDBG_CLR_MSK 0xffffffdf
3910 #define ALT_RSTMGR_SYSMODRST_SYSDBG_RESET 0x0
3912 #define ALT_RSTMGR_SYSMODRST_SYSDBG_GET(value) (((value) & 0x00000020) >> 5)
3914 #define ALT_RSTMGR_SYSMODRST_SYSDBG_SET(value) (((value) << 5) & 0x00000020)
3925 #define ALT_RSTMGR_SYSMODRST_OCRAMOCP_LSB 6
3927 #define ALT_RSTMGR_SYSMODRST_OCRAMOCP_MSB 6
3929 #define ALT_RSTMGR_SYSMODRST_OCRAMOCP_WIDTH 1
3931 #define ALT_RSTMGR_SYSMODRST_OCRAMOCP_SET_MSK 0x00000040
3933 #define ALT_RSTMGR_SYSMODRST_OCRAMOCP_CLR_MSK 0xffffffbf
3935 #define ALT_RSTMGR_SYSMODRST_OCRAMOCP_RESET 0x0
3937 #define ALT_RSTMGR_SYSMODRST_OCRAMOCP_GET(value) (((value) & 0x00000040) >> 6)
3939 #define ALT_RSTMGR_SYSMODRST_OCRAMOCP_SET(value) (((value) << 6) & 0x00000040)
3941 #ifndef __ASSEMBLY__
3952 struct ALT_RSTMGR_SYSMODRST_s
3957 uint32_t fpgamgr : 1;
3959 uint32_t sysdbg : 1;
3960 uint32_t ocramocp : 1;
3965 typedef volatile struct ALT_RSTMGR_SYSMODRST_s ALT_RSTMGR_SYSMODRST_t;
3969 #define ALT_RSTMGR_SYSMODRST_RESET 0x00000000
3971 #define ALT_RSTMGR_SYSMODRST_OFST 0x30
4013 #define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_LSB 0
4015 #define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_MSB 0
4017 #define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_WIDTH 1
4019 #define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_SET_MSK 0x00000001
4021 #define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_CLR_MSK 0xfffffffe
4023 #define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_RESET 0x0
4025 #define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_GET(value) (((value) & 0x00000001) >> 0)
4027 #define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_SET(value) (((value) << 0) & 0x00000001)
4039 #define ALT_RSTMGR_COLDMODRST_S2FCOLD_LSB 3
4041 #define ALT_RSTMGR_COLDMODRST_S2FCOLD_MSB 3
4043 #define ALT_RSTMGR_COLDMODRST_S2FCOLD_WIDTH 1
4045 #define ALT_RSTMGR_COLDMODRST_S2FCOLD_SET_MSK 0x00000008
4047 #define ALT_RSTMGR_COLDMODRST_S2FCOLD_CLR_MSK 0xfffffff7
4049 #define ALT_RSTMGR_COLDMODRST_S2FCOLD_RESET 0x0
4051 #define ALT_RSTMGR_COLDMODRST_S2FCOLD_GET(value) (((value) & 0x00000008) >> 3)
4053 #define ALT_RSTMGR_COLDMODRST_S2FCOLD_SET(value) (((value) << 3) & 0x00000008)
4064 #define ALT_RSTMGR_COLDMODRST_TSCOLD_LSB 4
4066 #define ALT_RSTMGR_COLDMODRST_TSCOLD_MSB 4
4068 #define ALT_RSTMGR_COLDMODRST_TSCOLD_WIDTH 1
4070 #define ALT_RSTMGR_COLDMODRST_TSCOLD_SET_MSK 0x00000010
4072 #define ALT_RSTMGR_COLDMODRST_TSCOLD_CLR_MSK 0xffffffef
4074 #define ALT_RSTMGR_COLDMODRST_TSCOLD_RESET 0x0
4076 #define ALT_RSTMGR_COLDMODRST_TSCOLD_GET(value) (((value) & 0x00000010) >> 4)
4078 #define ALT_RSTMGR_COLDMODRST_TSCOLD_SET(value) (((value) << 4) & 0x00000010)
4090 #define ALT_RSTMGR_COLDMODRST_TAPCOLD_LSB 5
4092 #define ALT_RSTMGR_COLDMODRST_TAPCOLD_MSB 5
4094 #define ALT_RSTMGR_COLDMODRST_TAPCOLD_WIDTH 1
4096 #define ALT_RSTMGR_COLDMODRST_TAPCOLD_SET_MSK 0x00000020
4098 #define ALT_RSTMGR_COLDMODRST_TAPCOLD_CLR_MSK 0xffffffdf
4100 #define ALT_RSTMGR_COLDMODRST_TAPCOLD_RESET 0x0
4102 #define ALT_RSTMGR_COLDMODRST_TAPCOLD_GET(value) (((value) & 0x00000020) >> 5)
4104 #define ALT_RSTMGR_COLDMODRST_TAPCOLD_SET(value) (((value) << 5) & 0x00000020)
4115 #define ALT_RSTMGR_COLDMODRST_HMCCOLD_LSB 6
4117 #define ALT_RSTMGR_COLDMODRST_HMCCOLD_MSB 6
4119 #define ALT_RSTMGR_COLDMODRST_HMCCOLD_WIDTH 1
4121 #define ALT_RSTMGR_COLDMODRST_HMCCOLD_SET_MSK 0x00000040
4123 #define ALT_RSTMGR_COLDMODRST_HMCCOLD_CLR_MSK 0xffffffbf
4125 #define ALT_RSTMGR_COLDMODRST_HMCCOLD_RESET 0x0
4127 #define ALT_RSTMGR_COLDMODRST_HMCCOLD_GET(value) (((value) & 0x00000040) >> 6)
4129 #define ALT_RSTMGR_COLDMODRST_HMCCOLD_SET(value) (((value) << 6) & 0x00000040)
4141 #define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_LSB 7
4143 #define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_MSB 7
4145 #define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_WIDTH 1
4147 #define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_SET_MSK 0x00000080
4149 #define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_CLR_MSK 0xffffff7f
4151 #define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_RESET 0x0
4153 #define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_GET(value) (((value) & 0x00000080) >> 7)
4155 #define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_SET(value) (((value) << 7) & 0x00000080)
4157 #ifndef __ASSEMBLY__
4168 struct ALT_RSTMGR_COLDMODRST_s
4170 uint32_t clkmgrcold : 1;
4172 uint32_t s2fcold : 1;
4173 uint32_t timestampcold : 1;
4174 uint32_t tapcold : 1;
4175 uint32_t hmccold : 1;
4176 uint32_t iomgrcold : 1;
4181 typedef volatile struct ALT_RSTMGR_COLDMODRST_s ALT_RSTMGR_COLDMODRST_t;
4185 #define ALT_RSTMGR_COLDMODRST_RESET 0x00000000
4187 #define ALT_RSTMGR_COLDMODRST_OFST 0x34
4223 #define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_LSB 0
4225 #define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_MSB 0
4227 #define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_WIDTH 1
4229 #define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_SET_MSK 0x00000001
4231 #define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_CLR_MSK 0xfffffffe
4233 #define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_RESET 0x0
4235 #define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_GET(value) (((value) & 0x00000001) >> 0)
4237 #define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_SET(value) (((value) << 0) & 0x00000001)
4239 #ifndef __ASSEMBLY__
4250 struct ALT_RSTMGR_NRSTMODRST_s
4252 uint32_t nrstpinoe : 1;
4257 typedef volatile struct ALT_RSTMGR_NRSTMODRST_s ALT_RSTMGR_NRSTMODRST_t;
4261 #define ALT_RSTMGR_NRSTMODRST_RESET 0x00000000
4263 #define ALT_RSTMGR_NRSTMODRST_OFST 0x38
4299 #define ALT_RSTMGR_DBGMODRST_DBG_LSB 0
4301 #define ALT_RSTMGR_DBGMODRST_DBG_MSB 0
4303 #define ALT_RSTMGR_DBGMODRST_DBG_WIDTH 1
4305 #define ALT_RSTMGR_DBGMODRST_DBG_SET_MSK 0x00000001
4307 #define ALT_RSTMGR_DBGMODRST_DBG_CLR_MSK 0xfffffffe
4309 #define ALT_RSTMGR_DBGMODRST_DBG_RESET 0x0
4311 #define ALT_RSTMGR_DBGMODRST_DBG_GET(value) (((value) & 0x00000001) >> 0)
4313 #define ALT_RSTMGR_DBGMODRST_DBG_SET(value) (((value) << 0) & 0x00000001)
4315 #ifndef __ASSEMBLY__
4326 struct ALT_RSTMGR_DBGMODRST_s
4333 typedef volatile struct ALT_RSTMGR_DBGMODRST_s ALT_RSTMGR_DBGMODRST_t;
4337 #define ALT_RSTMGR_DBGMODRST_RESET 0x00000000
4339 #define ALT_RSTMGR_DBGMODRST_OFST 0x3c
4374 #define ALT_RSTMGR_MPUWARMMSK_WDS_LSB 0
4376 #define ALT_RSTMGR_MPUWARMMSK_WDS_MSB 0
4378 #define ALT_RSTMGR_MPUWARMMSK_WDS_WIDTH 1
4380 #define ALT_RSTMGR_MPUWARMMSK_WDS_SET_MSK 0x00000001
4382 #define ALT_RSTMGR_MPUWARMMSK_WDS_CLR_MSK 0xfffffffe
4384 #define ALT_RSTMGR_MPUWARMMSK_WDS_RESET 0x1
4386 #define ALT_RSTMGR_MPUWARMMSK_WDS_GET(value) (((value) & 0x00000001) >> 0)
4388 #define ALT_RSTMGR_MPUWARMMSK_WDS_SET(value) (((value) << 0) & 0x00000001)
4390 #ifndef __ASSEMBLY__
4401 struct ALT_RSTMGR_MPUWARMMSK_s
4408 typedef volatile struct ALT_RSTMGR_MPUWARMMSK_s ALT_RSTMGR_MPUWARMMSK_t;
4412 #define ALT_RSTMGR_MPUWARMMSK_RESET 0x0000001f
4414 #define ALT_RSTMGR_MPUWARMMSK_OFST 0x40
4478 #define ALT_RSTMGR_PER0WARMMSK_EMAC0_LSB 0
4480 #define ALT_RSTMGR_PER0WARMMSK_EMAC0_MSB 0
4482 #define ALT_RSTMGR_PER0WARMMSK_EMAC0_WIDTH 1
4484 #define ALT_RSTMGR_PER0WARMMSK_EMAC0_SET_MSK 0x00000001
4486 #define ALT_RSTMGR_PER0WARMMSK_EMAC0_CLR_MSK 0xfffffffe
4488 #define ALT_RSTMGR_PER0WARMMSK_EMAC0_RESET 0x1
4490 #define ALT_RSTMGR_PER0WARMMSK_EMAC0_GET(value) (((value) & 0x00000001) >> 0)
4492 #define ALT_RSTMGR_PER0WARMMSK_EMAC0_SET(value) (((value) << 0) & 0x00000001)
4503 #define ALT_RSTMGR_PER0WARMMSK_EMAC1_LSB 1
4505 #define ALT_RSTMGR_PER0WARMMSK_EMAC1_MSB 1
4507 #define ALT_RSTMGR_PER0WARMMSK_EMAC1_WIDTH 1
4509 #define ALT_RSTMGR_PER0WARMMSK_EMAC1_SET_MSK 0x00000002
4511 #define ALT_RSTMGR_PER0WARMMSK_EMAC1_CLR_MSK 0xfffffffd
4513 #define ALT_RSTMGR_PER0WARMMSK_EMAC1_RESET 0x1
4515 #define ALT_RSTMGR_PER0WARMMSK_EMAC1_GET(value) (((value) & 0x00000002) >> 1)
4517 #define ALT_RSTMGR_PER0WARMMSK_EMAC1_SET(value) (((value) << 1) & 0x00000002)
4528 #define ALT_RSTMGR_PER0WARMMSK_EMAC2_LSB 2
4530 #define ALT_RSTMGR_PER0WARMMSK_EMAC2_MSB 2
4532 #define ALT_RSTMGR_PER0WARMMSK_EMAC2_WIDTH 1
4534 #define ALT_RSTMGR_PER0WARMMSK_EMAC2_SET_MSK 0x00000004
4536 #define ALT_RSTMGR_PER0WARMMSK_EMAC2_CLR_MSK 0xfffffffb
4538 #define ALT_RSTMGR_PER0WARMMSK_EMAC2_RESET 0x1
4540 #define ALT_RSTMGR_PER0WARMMSK_EMAC2_GET(value) (((value) & 0x00000004) >> 2)
4542 #define ALT_RSTMGR_PER0WARMMSK_EMAC2_SET(value) (((value) << 2) & 0x00000004)
4553 #define ALT_RSTMGR_PER0WARMMSK_USB0_LSB 3
4555 #define ALT_RSTMGR_PER0WARMMSK_USB0_MSB 3
4557 #define ALT_RSTMGR_PER0WARMMSK_USB0_WIDTH 1
4559 #define ALT_RSTMGR_PER0WARMMSK_USB0_SET_MSK 0x00000008
4561 #define ALT_RSTMGR_PER0WARMMSK_USB0_CLR_MSK 0xfffffff7
4563 #define ALT_RSTMGR_PER0WARMMSK_USB0_RESET 0x1
4565 #define ALT_RSTMGR_PER0WARMMSK_USB0_GET(value) (((value) & 0x00000008) >> 3)
4567 #define ALT_RSTMGR_PER0WARMMSK_USB0_SET(value) (((value) << 3) & 0x00000008)
4578 #define ALT_RSTMGR_PER0WARMMSK_USB1_LSB 4
4580 #define ALT_RSTMGR_PER0WARMMSK_USB1_MSB 4
4582 #define ALT_RSTMGR_PER0WARMMSK_USB1_WIDTH 1
4584 #define ALT_RSTMGR_PER0WARMMSK_USB1_SET_MSK 0x00000010
4586 #define ALT_RSTMGR_PER0WARMMSK_USB1_CLR_MSK 0xffffffef
4588 #define ALT_RSTMGR_PER0WARMMSK_USB1_RESET 0x1
4590 #define ALT_RSTMGR_PER0WARMMSK_USB1_GET(value) (((value) & 0x00000010) >> 4)
4592 #define ALT_RSTMGR_PER0WARMMSK_USB1_SET(value) (((value) << 4) & 0x00000010)
4603 #define ALT_RSTMGR_PER0WARMMSK_NAND_LSB 5
4605 #define ALT_RSTMGR_PER0WARMMSK_NAND_MSB 5
4607 #define ALT_RSTMGR_PER0WARMMSK_NAND_WIDTH 1
4609 #define ALT_RSTMGR_PER0WARMMSK_NAND_SET_MSK 0x00000020
4611 #define ALT_RSTMGR_PER0WARMMSK_NAND_CLR_MSK 0xffffffdf
4613 #define ALT_RSTMGR_PER0WARMMSK_NAND_RESET 0x1
4615 #define ALT_RSTMGR_PER0WARMMSK_NAND_GET(value) (((value) & 0x00000020) >> 5)
4617 #define ALT_RSTMGR_PER0WARMMSK_NAND_SET(value) (((value) << 5) & 0x00000020)
4628 #define ALT_RSTMGR_PER0WARMMSK_QSPI_LSB 6
4630 #define ALT_RSTMGR_PER0WARMMSK_QSPI_MSB 6
4632 #define ALT_RSTMGR_PER0WARMMSK_QSPI_WIDTH 1
4634 #define ALT_RSTMGR_PER0WARMMSK_QSPI_SET_MSK 0x00000040
4636 #define ALT_RSTMGR_PER0WARMMSK_QSPI_CLR_MSK 0xffffffbf
4638 #define ALT_RSTMGR_PER0WARMMSK_QSPI_RESET 0x1
4640 #define ALT_RSTMGR_PER0WARMMSK_QSPI_GET(value) (((value) & 0x00000040) >> 6)
4642 #define ALT_RSTMGR_PER0WARMMSK_QSPI_SET(value) (((value) << 6) & 0x00000040)
4653 #define ALT_RSTMGR_PER0WARMMSK_SDMMC_LSB 7
4655 #define ALT_RSTMGR_PER0WARMMSK_SDMMC_MSB 7
4657 #define ALT_RSTMGR_PER0WARMMSK_SDMMC_WIDTH 1
4659 #define ALT_RSTMGR_PER0WARMMSK_SDMMC_SET_MSK 0x00000080
4661 #define ALT_RSTMGR_PER0WARMMSK_SDMMC_CLR_MSK 0xffffff7f
4663 #define ALT_RSTMGR_PER0WARMMSK_SDMMC_RESET 0x1
4665 #define ALT_RSTMGR_PER0WARMMSK_SDMMC_GET(value) (((value) & 0x00000080) >> 7)
4667 #define ALT_RSTMGR_PER0WARMMSK_SDMMC_SET(value) (((value) << 7) & 0x00000080)
4678 #define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_LSB 8
4680 #define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_MSB 8
4682 #define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_WIDTH 1
4684 #define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_SET_MSK 0x00000100
4686 #define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_CLR_MSK 0xfffffeff
4688 #define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_RESET 0x1
4690 #define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_GET(value) (((value) & 0x00000100) >> 8)
4692 #define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_SET(value) (((value) << 8) & 0x00000100)
4703 #define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_LSB 9
4705 #define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_MSB 9
4707 #define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_WIDTH 1
4709 #define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_SET_MSK 0x00000200
4711 #define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_CLR_MSK 0xfffffdff
4713 #define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_RESET 0x1
4715 #define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_GET(value) (((value) & 0x00000200) >> 9)
4717 #define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_SET(value) (((value) << 9) & 0x00000200)
4728 #define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_LSB 10
4730 #define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_MSB 10
4732 #define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_WIDTH 1
4734 #define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_SET_MSK 0x00000400
4736 #define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_CLR_MSK 0xfffffbff
4738 #define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_RESET 0x1
4740 #define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_GET(value) (((value) & 0x00000400) >> 10)
4742 #define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_SET(value) (((value) << 10) & 0x00000400)
4753 #define ALT_RSTMGR_PER0WARMMSK_USB0OCP_LSB 11
4755 #define ALT_RSTMGR_PER0WARMMSK_USB0OCP_MSB 11
4757 #define ALT_RSTMGR_PER0WARMMSK_USB0OCP_WIDTH 1
4759 #define ALT_RSTMGR_PER0WARMMSK_USB0OCP_SET_MSK 0x00000800
4761 #define ALT_RSTMGR_PER0WARMMSK_USB0OCP_CLR_MSK 0xfffff7ff
4763 #define ALT_RSTMGR_PER0WARMMSK_USB0OCP_RESET 0x1
4765 #define ALT_RSTMGR_PER0WARMMSK_USB0OCP_GET(value) (((value) & 0x00000800) >> 11)
4767 #define ALT_RSTMGR_PER0WARMMSK_USB0OCP_SET(value) (((value) << 11) & 0x00000800)
4778 #define ALT_RSTMGR_PER0WARMMSK_USB1OCP_LSB 12
4780 #define ALT_RSTMGR_PER0WARMMSK_USB1OCP_MSB 12
4782 #define ALT_RSTMGR_PER0WARMMSK_USB1OCP_WIDTH 1
4784 #define ALT_RSTMGR_PER0WARMMSK_USB1OCP_SET_MSK 0x00001000
4786 #define ALT_RSTMGR_PER0WARMMSK_USB1OCP_CLR_MSK 0xffffefff
4788 #define ALT_RSTMGR_PER0WARMMSK_USB1OCP_RESET 0x1
4790 #define ALT_RSTMGR_PER0WARMMSK_USB1OCP_GET(value) (((value) & 0x00001000) >> 12)
4792 #define ALT_RSTMGR_PER0WARMMSK_USB1OCP_SET(value) (((value) << 12) & 0x00001000)
4803 #define ALT_RSTMGR_PER0WARMMSK_NANDOCP_LSB 13
4805 #define ALT_RSTMGR_PER0WARMMSK_NANDOCP_MSB 13
4807 #define ALT_RSTMGR_PER0WARMMSK_NANDOCP_WIDTH 1
4809 #define ALT_RSTMGR_PER0WARMMSK_NANDOCP_SET_MSK 0x00002000
4811 #define ALT_RSTMGR_PER0WARMMSK_NANDOCP_CLR_MSK 0xffffdfff
4813 #define ALT_RSTMGR_PER0WARMMSK_NANDOCP_RESET 0x1
4815 #define ALT_RSTMGR_PER0WARMMSK_NANDOCP_GET(value) (((value) & 0x00002000) >> 13)
4817 #define ALT_RSTMGR_PER0WARMMSK_NANDOCP_SET(value) (((value) << 13) & 0x00002000)
4828 #define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_LSB 14
4830 #define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_MSB 14
4832 #define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_WIDTH 1
4834 #define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_SET_MSK 0x00004000
4836 #define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_CLR_MSK 0xffffbfff
4838 #define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_RESET 0x1
4840 #define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_GET(value) (((value) & 0x00004000) >> 14)
4842 #define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_SET(value) (((value) << 14) & 0x00004000)
4853 #define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_LSB 15
4855 #define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_MSB 15
4857 #define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_WIDTH 1
4859 #define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_SET_MSK 0x00008000
4861 #define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_CLR_MSK 0xffff7fff
4863 #define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_RESET 0x1
4865 #define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_GET(value) (((value) & 0x00008000) >> 15)
4867 #define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_SET(value) (((value) << 15) & 0x00008000)
4878 #define ALT_RSTMGR_PER0WARMMSK_DMA_LSB 16
4880 #define ALT_RSTMGR_PER0WARMMSK_DMA_MSB 16
4882 #define ALT_RSTMGR_PER0WARMMSK_DMA_WIDTH 1
4884 #define ALT_RSTMGR_PER0WARMMSK_DMA_SET_MSK 0x00010000
4886 #define ALT_RSTMGR_PER0WARMMSK_DMA_CLR_MSK 0xfffeffff
4888 #define ALT_RSTMGR_PER0WARMMSK_DMA_RESET 0x1
4890 #define ALT_RSTMGR_PER0WARMMSK_DMA_GET(value) (((value) & 0x00010000) >> 16)
4892 #define ALT_RSTMGR_PER0WARMMSK_DMA_SET(value) (((value) << 16) & 0x00010000)
4903 #define ALT_RSTMGR_PER0WARMMSK_SPIM0_LSB 17
4905 #define ALT_RSTMGR_PER0WARMMSK_SPIM0_MSB 17
4907 #define ALT_RSTMGR_PER0WARMMSK_SPIM0_WIDTH 1
4909 #define ALT_RSTMGR_PER0WARMMSK_SPIM0_SET_MSK 0x00020000
4911 #define ALT_RSTMGR_PER0WARMMSK_SPIM0_CLR_MSK 0xfffdffff
4913 #define ALT_RSTMGR_PER0WARMMSK_SPIM0_RESET 0x1
4915 #define ALT_RSTMGR_PER0WARMMSK_SPIM0_GET(value) (((value) & 0x00020000) >> 17)
4917 #define ALT_RSTMGR_PER0WARMMSK_SPIM0_SET(value) (((value) << 17) & 0x00020000)
4928 #define ALT_RSTMGR_PER0WARMMSK_SPIM1_LSB 18
4930 #define ALT_RSTMGR_PER0WARMMSK_SPIM1_MSB 18
4932 #define ALT_RSTMGR_PER0WARMMSK_SPIM1_WIDTH 1
4934 #define ALT_RSTMGR_PER0WARMMSK_SPIM1_SET_MSK 0x00040000
4936 #define ALT_RSTMGR_PER0WARMMSK_SPIM1_CLR_MSK 0xfffbffff
4938 #define ALT_RSTMGR_PER0WARMMSK_SPIM1_RESET 0x1
4940 #define ALT_RSTMGR_PER0WARMMSK_SPIM1_GET(value) (((value) & 0x00040000) >> 18)
4942 #define ALT_RSTMGR_PER0WARMMSK_SPIM1_SET(value) (((value) << 18) & 0x00040000)
4953 #define ALT_RSTMGR_PER0WARMMSK_SPIS0_LSB 19
4955 #define ALT_RSTMGR_PER0WARMMSK_SPIS0_MSB 19
4957 #define ALT_RSTMGR_PER0WARMMSK_SPIS0_WIDTH 1
4959 #define ALT_RSTMGR_PER0WARMMSK_SPIS0_SET_MSK 0x00080000
4961 #define ALT_RSTMGR_PER0WARMMSK_SPIS0_CLR_MSK 0xfff7ffff
4963 #define ALT_RSTMGR_PER0WARMMSK_SPIS0_RESET 0x1
4965 #define ALT_RSTMGR_PER0WARMMSK_SPIS0_GET(value) (((value) & 0x00080000) >> 19)
4967 #define ALT_RSTMGR_PER0WARMMSK_SPIS0_SET(value) (((value) << 19) & 0x00080000)
4978 #define ALT_RSTMGR_PER0WARMMSK_SPIS1_LSB 20
4980 #define ALT_RSTMGR_PER0WARMMSK_SPIS1_MSB 20
4982 #define ALT_RSTMGR_PER0WARMMSK_SPIS1_WIDTH 1
4984 #define ALT_RSTMGR_PER0WARMMSK_SPIS1_SET_MSK 0x00100000
4986 #define ALT_RSTMGR_PER0WARMMSK_SPIS1_CLR_MSK 0xffefffff
4988 #define ALT_RSTMGR_PER0WARMMSK_SPIS1_RESET 0x1
4990 #define ALT_RSTMGR_PER0WARMMSK_SPIS1_GET(value) (((value) & 0x00100000) >> 20)
4992 #define ALT_RSTMGR_PER0WARMMSK_SPIS1_SET(value) (((value) << 20) & 0x00100000)
5004 #define ALT_RSTMGR_PER0WARMMSK_DMAOCP_LSB 21
5006 #define ALT_RSTMGR_PER0WARMMSK_DMAOCP_MSB 21
5008 #define ALT_RSTMGR_PER0WARMMSK_DMAOCP_WIDTH 1
5010 #define ALT_RSTMGR_PER0WARMMSK_DMAOCP_SET_MSK 0x00200000
5012 #define ALT_RSTMGR_PER0WARMMSK_DMAOCP_CLR_MSK 0xffdfffff
5014 #define ALT_RSTMGR_PER0WARMMSK_DMAOCP_RESET 0x1
5016 #define ALT_RSTMGR_PER0WARMMSK_DMAOCP_GET(value) (((value) & 0x00200000) >> 21)
5018 #define ALT_RSTMGR_PER0WARMMSK_DMAOCP_SET(value) (((value) << 21) & 0x00200000)
5029 #define ALT_RSTMGR_PER0WARMMSK_EMACPTP_LSB 22
5031 #define ALT_RSTMGR_PER0WARMMSK_EMACPTP_MSB 22
5033 #define ALT_RSTMGR_PER0WARMMSK_EMACPTP_WIDTH 1
5035 #define ALT_RSTMGR_PER0WARMMSK_EMACPTP_SET_MSK 0x00400000
5037 #define ALT_RSTMGR_PER0WARMMSK_EMACPTP_CLR_MSK 0xffbfffff
5039 #define ALT_RSTMGR_PER0WARMMSK_EMACPTP_RESET 0x1
5041 #define ALT_RSTMGR_PER0WARMMSK_EMACPTP_GET(value) (((value) & 0x00400000) >> 22)
5043 #define ALT_RSTMGR_PER0WARMMSK_EMACPTP_SET(value) (((value) << 22) & 0x00400000)
5055 #define ALT_RSTMGR_PER0WARMMSK_DMAIF0_LSB 24
5057 #define ALT_RSTMGR_PER0WARMMSK_DMAIF0_MSB 24
5059 #define ALT_RSTMGR_PER0WARMMSK_DMAIF0_WIDTH 1
5061 #define ALT_RSTMGR_PER0WARMMSK_DMAIF0_SET_MSK 0x01000000
5063 #define ALT_RSTMGR_PER0WARMMSK_DMAIF0_CLR_MSK 0xfeffffff
5065 #define ALT_RSTMGR_PER0WARMMSK_DMAIF0_RESET 0x1
5067 #define ALT_RSTMGR_PER0WARMMSK_DMAIF0_GET(value) (((value) & 0x01000000) >> 24)
5069 #define ALT_RSTMGR_PER0WARMMSK_DMAIF0_SET(value) (((value) << 24) & 0x01000000)
5081 #define ALT_RSTMGR_PER0WARMMSK_DMAIF1_LSB 25
5083 #define ALT_RSTMGR_PER0WARMMSK_DMAIF1_MSB 25
5085 #define ALT_RSTMGR_PER0WARMMSK_DMAIF1_WIDTH 1
5087 #define ALT_RSTMGR_PER0WARMMSK_DMAIF1_SET_MSK 0x02000000
5089 #define ALT_RSTMGR_PER0WARMMSK_DMAIF1_CLR_MSK 0xfdffffff
5091 #define ALT_RSTMGR_PER0WARMMSK_DMAIF1_RESET 0x1
5093 #define ALT_RSTMGR_PER0WARMMSK_DMAIF1_GET(value) (((value) & 0x02000000) >> 25)
5095 #define ALT_RSTMGR_PER0WARMMSK_DMAIF1_SET(value) (((value) << 25) & 0x02000000)
5107 #define ALT_RSTMGR_PER0WARMMSK_DMAIF2_LSB 26
5109 #define ALT_RSTMGR_PER0WARMMSK_DMAIF2_MSB 26
5111 #define ALT_RSTMGR_PER0WARMMSK_DMAIF2_WIDTH 1
5113 #define ALT_RSTMGR_PER0WARMMSK_DMAIF2_SET_MSK 0x04000000
5115 #define ALT_RSTMGR_PER0WARMMSK_DMAIF2_CLR_MSK 0xfbffffff
5117 #define ALT_RSTMGR_PER0WARMMSK_DMAIF2_RESET 0x1
5119 #define ALT_RSTMGR_PER0WARMMSK_DMAIF2_GET(value) (((value) & 0x04000000) >> 26)
5121 #define ALT_RSTMGR_PER0WARMMSK_DMAIF2_SET(value) (((value) << 26) & 0x04000000)
5133 #define ALT_RSTMGR_PER0WARMMSK_DMAIF3_LSB 27
5135 #define ALT_RSTMGR_PER0WARMMSK_DMAIF3_MSB 27
5137 #define ALT_RSTMGR_PER0WARMMSK_DMAIF3_WIDTH 1
5139 #define ALT_RSTMGR_PER0WARMMSK_DMAIF3_SET_MSK 0x08000000
5141 #define ALT_RSTMGR_PER0WARMMSK_DMAIF3_CLR_MSK 0xf7ffffff
5143 #define ALT_RSTMGR_PER0WARMMSK_DMAIF3_RESET 0x1
5145 #define ALT_RSTMGR_PER0WARMMSK_DMAIF3_GET(value) (((value) & 0x08000000) >> 27)
5147 #define ALT_RSTMGR_PER0WARMMSK_DMAIF3_SET(value) (((value) << 27) & 0x08000000)
5159 #define ALT_RSTMGR_PER0WARMMSK_DMAIF4_LSB 28
5161 #define ALT_RSTMGR_PER0WARMMSK_DMAIF4_MSB 28
5163 #define ALT_RSTMGR_PER0WARMMSK_DMAIF4_WIDTH 1
5165 #define ALT_RSTMGR_PER0WARMMSK_DMAIF4_SET_MSK 0x10000000
5167 #define ALT_RSTMGR_PER0WARMMSK_DMAIF4_CLR_MSK 0xefffffff
5169 #define ALT_RSTMGR_PER0WARMMSK_DMAIF4_RESET 0x1
5171 #define ALT_RSTMGR_PER0WARMMSK_DMAIF4_GET(value) (((value) & 0x10000000) >> 28)
5173 #define ALT_RSTMGR_PER0WARMMSK_DMAIF4_SET(value) (((value) << 28) & 0x10000000)
5185 #define ALT_RSTMGR_PER0WARMMSK_DMAIF5_LSB 29
5187 #define ALT_RSTMGR_PER0WARMMSK_DMAIF5_MSB 29
5189 #define ALT_RSTMGR_PER0WARMMSK_DMAIF5_WIDTH 1
5191 #define ALT_RSTMGR_PER0WARMMSK_DMAIF5_SET_MSK 0x20000000
5193 #define ALT_RSTMGR_PER0WARMMSK_DMAIF5_CLR_MSK 0xdfffffff
5195 #define ALT_RSTMGR_PER0WARMMSK_DMAIF5_RESET 0x1
5197 #define ALT_RSTMGR_PER0WARMMSK_DMAIF5_GET(value) (((value) & 0x20000000) >> 29)
5199 #define ALT_RSTMGR_PER0WARMMSK_DMAIF5_SET(value) (((value) << 29) & 0x20000000)
5211 #define ALT_RSTMGR_PER0WARMMSK_DMAIF6_LSB 30
5213 #define ALT_RSTMGR_PER0WARMMSK_DMAIF6_MSB 30
5215 #define ALT_RSTMGR_PER0WARMMSK_DMAIF6_WIDTH 1
5217 #define ALT_RSTMGR_PER0WARMMSK_DMAIF6_SET_MSK 0x40000000
5219 #define ALT_RSTMGR_PER0WARMMSK_DMAIF6_CLR_MSK 0xbfffffff
5221 #define ALT_RSTMGR_PER0WARMMSK_DMAIF6_RESET 0x1
5223 #define ALT_RSTMGR_PER0WARMMSK_DMAIF6_GET(value) (((value) & 0x40000000) >> 30)
5225 #define ALT_RSTMGR_PER0WARMMSK_DMAIF6_SET(value) (((value) << 30) & 0x40000000)
5237 #define ALT_RSTMGR_PER0WARMMSK_DMAIF7_LSB 31
5239 #define ALT_RSTMGR_PER0WARMMSK_DMAIF7_MSB 31
5241 #define ALT_RSTMGR_PER0WARMMSK_DMAIF7_WIDTH 1
5243 #define ALT_RSTMGR_PER0WARMMSK_DMAIF7_SET_MSK 0x80000000
5245 #define ALT_RSTMGR_PER0WARMMSK_DMAIF7_CLR_MSK 0x7fffffff
5247 #define ALT_RSTMGR_PER0WARMMSK_DMAIF7_RESET 0x1
5249 #define ALT_RSTMGR_PER0WARMMSK_DMAIF7_GET(value) (((value) & 0x80000000) >> 31)
5251 #define ALT_RSTMGR_PER0WARMMSK_DMAIF7_SET(value) (((value) << 31) & 0x80000000)
5253 #ifndef __ASSEMBLY__
5264 struct ALT_RSTMGR_PER0WARMMSK_s
5274 uint32_t emac0ocp : 1;
5275 uint32_t emac1ocp : 1;
5276 uint32_t emac2ocp : 1;
5277 uint32_t usb0ocp : 1;
5278 uint32_t usb1ocp : 1;
5279 uint32_t nandocp : 1;
5280 uint32_t qspiocp : 1;
5281 uint32_t sdmmcocp : 1;
5287 uint32_t dmaocp : 1;
5288 uint32_t emacptp : 1;
5290 uint32_t dmaif0 : 1;
5291 uint32_t dmaif1 : 1;
5292 uint32_t dmaif2 : 1;
5293 uint32_t dmaif3 : 1;
5294 uint32_t dmaif4 : 1;
5295 uint32_t dmaif5 : 1;
5296 uint32_t dmaif6 : 1;
5297 uint32_t dmaif7 : 1;
5301 typedef volatile struct ALT_RSTMGR_PER0WARMMSK_s ALT_RSTMGR_PER0WARMMSK_t;
5305 #define ALT_RSTMGR_PER0WARMMSK_RESET 0xff7fffff
5307 #define ALT_RSTMGR_PER0WARMMSK_OFST 0x44
5359 #define ALT_RSTMGR_PER1WARMMSK_WD0_LSB 0
5361 #define ALT_RSTMGR_PER1WARMMSK_WD0_MSB 0
5363 #define ALT_RSTMGR_PER1WARMMSK_WD0_WIDTH 1
5365 #define ALT_RSTMGR_PER1WARMMSK_WD0_SET_MSK 0x00000001
5367 #define ALT_RSTMGR_PER1WARMMSK_WD0_CLR_MSK 0xfffffffe
5369 #define ALT_RSTMGR_PER1WARMMSK_WD0_RESET 0x1
5371 #define ALT_RSTMGR_PER1WARMMSK_WD0_GET(value) (((value) & 0x00000001) >> 0)
5373 #define ALT_RSTMGR_PER1WARMMSK_WD0_SET(value) (((value) << 0) & 0x00000001)
5384 #define ALT_RSTMGR_PER1WARMMSK_WD1_LSB 1
5386 #define ALT_RSTMGR_PER1WARMMSK_WD1_MSB 1
5388 #define ALT_RSTMGR_PER1WARMMSK_WD1_WIDTH 1
5390 #define ALT_RSTMGR_PER1WARMMSK_WD1_SET_MSK 0x00000002
5392 #define ALT_RSTMGR_PER1WARMMSK_WD1_CLR_MSK 0xfffffffd
5394 #define ALT_RSTMGR_PER1WARMMSK_WD1_RESET 0x1
5396 #define ALT_RSTMGR_PER1WARMMSK_WD1_GET(value) (((value) & 0x00000002) >> 1)
5398 #define ALT_RSTMGR_PER1WARMMSK_WD1_SET(value) (((value) << 1) & 0x00000002)
5409 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_LSB 2
5411 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_MSB 2
5413 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_WIDTH 1
5415 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_SET_MSK 0x00000004
5417 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_CLR_MSK 0xfffffffb
5419 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_RESET 0x1
5421 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_GET(value) (((value) & 0x00000004) >> 2)
5423 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_SET(value) (((value) << 2) & 0x00000004)
5434 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_LSB 3
5436 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_MSB 3
5438 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_WIDTH 1
5440 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_SET_MSK 0x00000008
5442 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_CLR_MSK 0xfffffff7
5444 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_RESET 0x1
5446 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_GET(value) (((value) & 0x00000008) >> 3)
5448 #define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_SET(value) (((value) << 3) & 0x00000008)
5459 #define ALT_RSTMGR_PER1WARMMSK_SPTMR0_LSB 4
5461 #define ALT_RSTMGR_PER1WARMMSK_SPTMR0_MSB 4
5463 #define ALT_RSTMGR_PER1WARMMSK_SPTMR0_WIDTH 1
5465 #define ALT_RSTMGR_PER1WARMMSK_SPTMR0_SET_MSK 0x00000010
5467 #define ALT_RSTMGR_PER1WARMMSK_SPTMR0_CLR_MSK 0xffffffef
5469 #define ALT_RSTMGR_PER1WARMMSK_SPTMR0_RESET 0x1
5471 #define ALT_RSTMGR_PER1WARMMSK_SPTMR0_GET(value) (((value) & 0x00000010) >> 4)
5473 #define ALT_RSTMGR_PER1WARMMSK_SPTMR0_SET(value) (((value) << 4) & 0x00000010)
5484 #define ALT_RSTMGR_PER1WARMMSK_SPTMR1_LSB 5
5486 #define ALT_RSTMGR_PER1WARMMSK_SPTMR1_MSB 5
5488 #define ALT_RSTMGR_PER1WARMMSK_SPTMR1_WIDTH 1
5490 #define ALT_RSTMGR_PER1WARMMSK_SPTMR1_SET_MSK 0x00000020
5492 #define ALT_RSTMGR_PER1WARMMSK_SPTMR1_CLR_MSK 0xffffffdf
5494 #define ALT_RSTMGR_PER1WARMMSK_SPTMR1_RESET 0x1
5496 #define ALT_RSTMGR_PER1WARMMSK_SPTMR1_GET(value) (((value) & 0x00000020) >> 5)
5498 #define ALT_RSTMGR_PER1WARMMSK_SPTMR1_SET(value) (((value) << 5) & 0x00000020)
5509 #define ALT_RSTMGR_PER1WARMMSK_I2C0_LSB 8
5511 #define ALT_RSTMGR_PER1WARMMSK_I2C0_MSB 8
5513 #define ALT_RSTMGR_PER1WARMMSK_I2C0_WIDTH 1
5515 #define ALT_RSTMGR_PER1WARMMSK_I2C0_SET_MSK 0x00000100
5517 #define ALT_RSTMGR_PER1WARMMSK_I2C0_CLR_MSK 0xfffffeff
5519 #define ALT_RSTMGR_PER1WARMMSK_I2C0_RESET 0x1
5521 #define ALT_RSTMGR_PER1WARMMSK_I2C0_GET(value) (((value) & 0x00000100) >> 8)
5523 #define ALT_RSTMGR_PER1WARMMSK_I2C0_SET(value) (((value) << 8) & 0x00000100)
5534 #define ALT_RSTMGR_PER1WARMMSK_I2C1_LSB 9
5536 #define ALT_RSTMGR_PER1WARMMSK_I2C1_MSB 9
5538 #define ALT_RSTMGR_PER1WARMMSK_I2C1_WIDTH 1
5540 #define ALT_RSTMGR_PER1WARMMSK_I2C1_SET_MSK 0x00000200
5542 #define ALT_RSTMGR_PER1WARMMSK_I2C1_CLR_MSK 0xfffffdff
5544 #define ALT_RSTMGR_PER1WARMMSK_I2C1_RESET 0x1
5546 #define ALT_RSTMGR_PER1WARMMSK_I2C1_GET(value) (((value) & 0x00000200) >> 9)
5548 #define ALT_RSTMGR_PER1WARMMSK_I2C1_SET(value) (((value) << 9) & 0x00000200)
5559 #define ALT_RSTMGR_PER1WARMMSK_I2C2_LSB 10
5561 #define ALT_RSTMGR_PER1WARMMSK_I2C2_MSB 10
5563 #define ALT_RSTMGR_PER1WARMMSK_I2C2_WIDTH 1
5565 #define ALT_RSTMGR_PER1WARMMSK_I2C2_SET_MSK 0x00000400
5567 #define ALT_RSTMGR_PER1WARMMSK_I2C2_CLR_MSK 0xfffffbff
5569 #define ALT_RSTMGR_PER1WARMMSK_I2C2_RESET 0x1
5571 #define ALT_RSTMGR_PER1WARMMSK_I2C2_GET(value) (((value) & 0x00000400) >> 10)
5573 #define ALT_RSTMGR_PER1WARMMSK_I2C2_SET(value) (((value) << 10) & 0x00000400)
5584 #define ALT_RSTMGR_PER1WARMMSK_I2C3_LSB 11
5586 #define ALT_RSTMGR_PER1WARMMSK_I2C3_MSB 11
5588 #define ALT_RSTMGR_PER1WARMMSK_I2C3_WIDTH 1
5590 #define ALT_RSTMGR_PER1WARMMSK_I2C3_SET_MSK 0x00000800
5592 #define ALT_RSTMGR_PER1WARMMSK_I2C3_CLR_MSK 0xfffff7ff
5594 #define ALT_RSTMGR_PER1WARMMSK_I2C3_RESET 0x1
5596 #define ALT_RSTMGR_PER1WARMMSK_I2C3_GET(value) (((value) & 0x00000800) >> 11)
5598 #define ALT_RSTMGR_PER1WARMMSK_I2C3_SET(value) (((value) << 11) & 0x00000800)
5609 #define ALT_RSTMGR_PER1WARMMSK_I2C4_LSB 12
5611 #define ALT_RSTMGR_PER1WARMMSK_I2C4_MSB 12
5613 #define ALT_RSTMGR_PER1WARMMSK_I2C4_WIDTH 1
5615 #define ALT_RSTMGR_PER1WARMMSK_I2C4_SET_MSK 0x00001000
5617 #define ALT_RSTMGR_PER1WARMMSK_I2C4_CLR_MSK 0xffffefff
5619 #define ALT_RSTMGR_PER1WARMMSK_I2C4_RESET 0x1
5621 #define ALT_RSTMGR_PER1WARMMSK_I2C4_GET(value) (((value) & 0x00001000) >> 12)
5623 #define ALT_RSTMGR_PER1WARMMSK_I2C4_SET(value) (((value) << 12) & 0x00001000)
5634 #define ALT_RSTMGR_PER1WARMMSK_UART0_LSB 16
5636 #define ALT_RSTMGR_PER1WARMMSK_UART0_MSB 16
5638 #define ALT_RSTMGR_PER1WARMMSK_UART0_WIDTH 1
5640 #define ALT_RSTMGR_PER1WARMMSK_UART0_SET_MSK 0x00010000
5642 #define ALT_RSTMGR_PER1WARMMSK_UART0_CLR_MSK 0xfffeffff
5644 #define ALT_RSTMGR_PER1WARMMSK_UART0_RESET 0x1
5646 #define ALT_RSTMGR_PER1WARMMSK_UART0_GET(value) (((value) & 0x00010000) >> 16)
5648 #define ALT_RSTMGR_PER1WARMMSK_UART0_SET(value) (((value) << 16) & 0x00010000)
5659 #define ALT_RSTMGR_PER1WARMMSK_UART1_LSB 17
5661 #define ALT_RSTMGR_PER1WARMMSK_UART1_MSB 17
5663 #define ALT_RSTMGR_PER1WARMMSK_UART1_WIDTH 1
5665 #define ALT_RSTMGR_PER1WARMMSK_UART1_SET_MSK 0x00020000
5667 #define ALT_RSTMGR_PER1WARMMSK_UART1_CLR_MSK 0xfffdffff
5669 #define ALT_RSTMGR_PER1WARMMSK_UART1_RESET 0x1
5671 #define ALT_RSTMGR_PER1WARMMSK_UART1_GET(value) (((value) & 0x00020000) >> 17)
5673 #define ALT_RSTMGR_PER1WARMMSK_UART1_SET(value) (((value) << 17) & 0x00020000)
5684 #define ALT_RSTMGR_PER1WARMMSK_GPIO0_LSB 24
5686 #define ALT_RSTMGR_PER1WARMMSK_GPIO0_MSB 24
5688 #define ALT_RSTMGR_PER1WARMMSK_GPIO0_WIDTH 1
5690 #define ALT_RSTMGR_PER1WARMMSK_GPIO0_SET_MSK 0x01000000
5692 #define ALT_RSTMGR_PER1WARMMSK_GPIO0_CLR_MSK 0xfeffffff
5694 #define ALT_RSTMGR_PER1WARMMSK_GPIO0_RESET 0x1
5696 #define ALT_RSTMGR_PER1WARMMSK_GPIO0_GET(value) (((value) & 0x01000000) >> 24)
5698 #define ALT_RSTMGR_PER1WARMMSK_GPIO0_SET(value) (((value) << 24) & 0x01000000)
5709 #define ALT_RSTMGR_PER1WARMMSK_GPIO1_LSB 25
5711 #define ALT_RSTMGR_PER1WARMMSK_GPIO1_MSB 25
5713 #define ALT_RSTMGR_PER1WARMMSK_GPIO1_WIDTH 1
5715 #define ALT_RSTMGR_PER1WARMMSK_GPIO1_SET_MSK 0x02000000
5717 #define ALT_RSTMGR_PER1WARMMSK_GPIO1_CLR_MSK 0xfdffffff
5719 #define ALT_RSTMGR_PER1WARMMSK_GPIO1_RESET 0x1
5721 #define ALT_RSTMGR_PER1WARMMSK_GPIO1_GET(value) (((value) & 0x02000000) >> 25)
5723 #define ALT_RSTMGR_PER1WARMMSK_GPIO1_SET(value) (((value) << 25) & 0x02000000)
5734 #define ALT_RSTMGR_PER1WARMMSK_GPIO2_LSB 26
5736 #define ALT_RSTMGR_PER1WARMMSK_GPIO2_MSB 26
5738 #define ALT_RSTMGR_PER1WARMMSK_GPIO2_WIDTH 1
5740 #define ALT_RSTMGR_PER1WARMMSK_GPIO2_SET_MSK 0x04000000
5742 #define ALT_RSTMGR_PER1WARMMSK_GPIO2_CLR_MSK 0xfbffffff
5744 #define ALT_RSTMGR_PER1WARMMSK_GPIO2_RESET 0x1
5746 #define ALT_RSTMGR_PER1WARMMSK_GPIO2_GET(value) (((value) & 0x04000000) >> 26)
5748 #define ALT_RSTMGR_PER1WARMMSK_GPIO2_SET(value) (((value) << 26) & 0x04000000)
5750 #ifndef __ASSEMBLY__
5761 struct ALT_RSTMGR_PER1WARMMSK_s
5763 uint32_t watchdog0 : 1;
5764 uint32_t watchdog1 : 1;
5765 uint32_t l4systimer0 : 1;
5766 uint32_t l4systimer1 : 1;
5767 uint32_t sptimer0 : 1;
5768 uint32_t sptimer1 : 1;
5786 typedef volatile struct ALT_RSTMGR_PER1WARMMSK_s ALT_RSTMGR_PER1WARMMSK_t;
5790 #define ALT_RSTMGR_PER1WARMMSK_RESET 0x07031f3f
5792 #define ALT_RSTMGR_PER1WARMMSK_OFST 0x48
5832 #define ALT_RSTMGR_BRGWARMMSK_H2F_LSB 0
5834 #define ALT_RSTMGR_BRGWARMMSK_H2F_MSB 0
5836 #define ALT_RSTMGR_BRGWARMMSK_H2F_WIDTH 1
5838 #define ALT_RSTMGR_BRGWARMMSK_H2F_SET_MSK 0x00000001
5840 #define ALT_RSTMGR_BRGWARMMSK_H2F_CLR_MSK 0xfffffffe
5842 #define ALT_RSTMGR_BRGWARMMSK_H2F_RESET 0x1
5844 #define ALT_RSTMGR_BRGWARMMSK_H2F_GET(value) (((value) & 0x00000001) >> 0)
5846 #define ALT_RSTMGR_BRGWARMMSK_H2F_SET(value) (((value) << 0) & 0x00000001)
5857 #define ALT_RSTMGR_BRGWARMMSK_LWH2F_LSB 1
5859 #define ALT_RSTMGR_BRGWARMMSK_LWH2F_MSB 1
5861 #define ALT_RSTMGR_BRGWARMMSK_LWH2F_WIDTH 1
5863 #define ALT_RSTMGR_BRGWARMMSK_LWH2F_SET_MSK 0x00000002
5865 #define ALT_RSTMGR_BRGWARMMSK_LWH2F_CLR_MSK 0xfffffffd
5867 #define ALT_RSTMGR_BRGWARMMSK_LWH2F_RESET 0x1
5869 #define ALT_RSTMGR_BRGWARMMSK_LWH2F_GET(value) (((value) & 0x00000002) >> 1)
5871 #define ALT_RSTMGR_BRGWARMMSK_LWH2F_SET(value) (((value) << 1) & 0x00000002)
5882 #define ALT_RSTMGR_BRGWARMMSK_F2H_LSB 2
5884 #define ALT_RSTMGR_BRGWARMMSK_F2H_MSB 2
5886 #define ALT_RSTMGR_BRGWARMMSK_F2H_WIDTH 1
5888 #define ALT_RSTMGR_BRGWARMMSK_F2H_SET_MSK 0x00000004
5890 #define ALT_RSTMGR_BRGWARMMSK_F2H_CLR_MSK 0xfffffffb
5892 #define ALT_RSTMGR_BRGWARMMSK_F2H_RESET 0x1
5894 #define ALT_RSTMGR_BRGWARMMSK_F2H_GET(value) (((value) & 0x00000004) >> 2)
5896 #define ALT_RSTMGR_BRGWARMMSK_F2H_SET(value) (((value) << 2) & 0x00000004)
5907 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_LSB 3
5909 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_MSB 3
5911 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_WIDTH 1
5913 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_SET_MSK 0x00000008
5915 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_CLR_MSK 0xfffffff7
5917 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_RESET 0x1
5919 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_GET(value) (((value) & 0x00000008) >> 3)
5921 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_SET(value) (((value) << 3) & 0x00000008)
5932 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_LSB 4
5934 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_MSB 4
5936 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_WIDTH 1
5938 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_SET_MSK 0x00000010
5940 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_CLR_MSK 0xffffffef
5942 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_RESET 0x1
5944 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_GET(value) (((value) & 0x00000010) >> 4)
5946 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_SET(value) (((value) << 4) & 0x00000010)
5957 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_LSB 5
5959 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_MSB 5
5961 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_WIDTH 1
5963 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_SET_MSK 0x00000020
5965 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_CLR_MSK 0xffffffdf
5967 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_RESET 0x1
5969 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_GET(value) (((value) & 0x00000020) >> 5)
5971 #define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_SET(value) (((value) << 5) & 0x00000020)
5982 #define ALT_RSTMGR_BRGWARMMSK_DDRSCH_LSB 6
5984 #define ALT_RSTMGR_BRGWARMMSK_DDRSCH_MSB 6
5986 #define ALT_RSTMGR_BRGWARMMSK_DDRSCH_WIDTH 1
5988 #define ALT_RSTMGR_BRGWARMMSK_DDRSCH_SET_MSK 0x00000040
5990 #define ALT_RSTMGR_BRGWARMMSK_DDRSCH_CLR_MSK 0xffffffbf
5992 #define ALT_RSTMGR_BRGWARMMSK_DDRSCH_RESET 0x1
5994 #define ALT_RSTMGR_BRGWARMMSK_DDRSCH_GET(value) (((value) & 0x00000040) >> 6)
5996 #define ALT_RSTMGR_BRGWARMMSK_DDRSCH_SET(value) (((value) << 6) & 0x00000040)
5998 #ifndef __ASSEMBLY__
6009 struct ALT_RSTMGR_BRGWARMMSK_s
6011 uint32_t hps2fpga : 1;
6012 uint32_t lwhps2fpga : 1;
6013 uint32_t fpga2hps : 1;
6014 uint32_t f2ssdram0 : 1;
6015 uint32_t f2ssdram1 : 1;
6016 uint32_t f2ssdram2 : 1;
6017 uint32_t ddrsch : 1;
6022 typedef volatile struct ALT_RSTMGR_BRGWARMMSK_s ALT_RSTMGR_BRGWARMMSK_t;
6026 #define ALT_RSTMGR_BRGWARMMSK_RESET 0x0000007f
6028 #define ALT_RSTMGR_BRGWARMMSK_OFST 0x4c
6071 #define ALT_RSTMGR_SYSWARMMSK_ROM_LSB 0
6073 #define ALT_RSTMGR_SYSWARMMSK_ROM_MSB 0
6075 #define ALT_RSTMGR_SYSWARMMSK_ROM_WIDTH 1
6077 #define ALT_RSTMGR_SYSWARMMSK_ROM_SET_MSK 0x00000001
6079 #define ALT_RSTMGR_SYSWARMMSK_ROM_CLR_MSK 0xfffffffe
6081 #define ALT_RSTMGR_SYSWARMMSK_ROM_RESET 0x1
6083 #define ALT_RSTMGR_SYSWARMMSK_ROM_GET(value) (((value) & 0x00000001) >> 0)
6085 #define ALT_RSTMGR_SYSWARMMSK_ROM_SET(value) (((value) << 0) & 0x00000001)
6096 #define ALT_RSTMGR_SYSWARMMSK_OCRAM_LSB 1
6098 #define ALT_RSTMGR_SYSWARMMSK_OCRAM_MSB 1
6100 #define ALT_RSTMGR_SYSWARMMSK_OCRAM_WIDTH 1
6102 #define ALT_RSTMGR_SYSWARMMSK_OCRAM_SET_MSK 0x00000002
6104 #define ALT_RSTMGR_SYSWARMMSK_OCRAM_CLR_MSK 0xfffffffd
6106 #define ALT_RSTMGR_SYSWARMMSK_OCRAM_RESET 0x1
6108 #define ALT_RSTMGR_SYSWARMMSK_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
6110 #define ALT_RSTMGR_SYSWARMMSK_OCRAM_SET(value) (((value) << 1) & 0x00000002)
6121 #define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_LSB 3
6123 #define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_MSB 3
6125 #define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_WIDTH 1
6127 #define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_SET_MSK 0x00000008
6129 #define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_CLR_MSK 0xfffffff7
6131 #define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_RESET 0x1
6133 #define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_GET(value) (((value) & 0x00000008) >> 3)
6135 #define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_SET(value) (((value) << 3) & 0x00000008)
6147 #define ALT_RSTMGR_SYSWARMMSK_S2F_LSB 4
6149 #define ALT_RSTMGR_SYSWARMMSK_S2F_MSB 4
6151 #define ALT_RSTMGR_SYSWARMMSK_S2F_WIDTH 1
6153 #define ALT_RSTMGR_SYSWARMMSK_S2F_SET_MSK 0x00000010
6155 #define ALT_RSTMGR_SYSWARMMSK_S2F_CLR_MSK 0xffffffef
6157 #define ALT_RSTMGR_SYSWARMMSK_S2F_RESET 0x1
6159 #define ALT_RSTMGR_SYSWARMMSK_S2F_GET(value) (((value) & 0x00000010) >> 4)
6161 #define ALT_RSTMGR_SYSWARMMSK_S2F_SET(value) (((value) << 4) & 0x00000010)
6173 #define ALT_RSTMGR_SYSWARMMSK_SYSDBG_LSB 5
6175 #define ALT_RSTMGR_SYSWARMMSK_SYSDBG_MSB 5
6177 #define ALT_RSTMGR_SYSWARMMSK_SYSDBG_WIDTH 1
6179 #define ALT_RSTMGR_SYSWARMMSK_SYSDBG_SET_MSK 0x00000020
6181 #define ALT_RSTMGR_SYSWARMMSK_SYSDBG_CLR_MSK 0xffffffdf
6183 #define ALT_RSTMGR_SYSWARMMSK_SYSDBG_RESET 0x1
6185 #define ALT_RSTMGR_SYSWARMMSK_SYSDBG_GET(value) (((value) & 0x00000020) >> 5)
6187 #define ALT_RSTMGR_SYSWARMMSK_SYSDBG_SET(value) (((value) << 5) & 0x00000020)
6198 #define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_LSB 6
6200 #define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_MSB 6
6202 #define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_WIDTH 1
6204 #define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_SET_MSK 0x00000040
6206 #define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_CLR_MSK 0xffffffbf
6208 #define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_RESET 0x1
6210 #define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_GET(value) (((value) & 0x00000040) >> 6)
6212 #define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_SET(value) (((value) << 6) & 0x00000040)
6214 #ifndef __ASSEMBLY__
6225 struct ALT_RSTMGR_SYSWARMMSK_s
6230 uint32_t fpgamgr : 1;
6232 uint32_t sysdbg : 1;
6233 uint32_t ocramocp : 1;
6238 typedef volatile struct ALT_RSTMGR_SYSWARMMSK_s ALT_RSTMGR_SYSWARMMSK_t;
6242 #define ALT_RSTMGR_SYSWARMMSK_RESET 0x000001ff
6244 #define ALT_RSTMGR_SYSWARMMSK_OFST 0x50
6281 #define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_LSB 0
6283 #define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_MSB 0
6285 #define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_WIDTH 1
6287 #define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_SET_MSK 0x00000001
6289 #define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_CLR_MSK 0xfffffffe
6291 #define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_RESET 0x1
6293 #define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_GET(value) (((value) & 0x00000001) >> 0)
6295 #define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_SET(value) (((value) << 0) & 0x00000001)
6297 #ifndef __ASSEMBLY__
6308 struct ALT_RSTMGR_NRSTWARMMSK_s
6310 uint32_t nrstpinoe : 1;
6315 typedef volatile struct ALT_RSTMGR_NRSTWARMMSK_s ALT_RSTMGR_NRSTWARMMSK_t;
6319 #define ALT_RSTMGR_NRSTWARMMSK_RESET 0x00000001
6321 #define ALT_RSTMGR_NRSTWARMMSK_OFST 0x54
6359 #define ALT_RSTMGR_L3WARMMSK_L3_LSB 0
6361 #define ALT_RSTMGR_L3WARMMSK_L3_MSB 0
6363 #define ALT_RSTMGR_L3WARMMSK_L3_WIDTH 1
6365 #define ALT_RSTMGR_L3WARMMSK_L3_SET_MSK 0x00000001
6367 #define ALT_RSTMGR_L3WARMMSK_L3_CLR_MSK 0xfffffffe
6369 #define ALT_RSTMGR_L3WARMMSK_L3_RESET 0x1
6371 #define ALT_RSTMGR_L3WARMMSK_L3_GET(value) (((value) & 0x00000001) >> 0)
6373 #define ALT_RSTMGR_L3WARMMSK_L3_SET(value) (((value) << 0) & 0x00000001)
6375 #ifndef __ASSEMBLY__
6386 struct ALT_RSTMGR_L3WARMMSK_s
6393 typedef volatile struct ALT_RSTMGR_L3WARMMSK_s ALT_RSTMGR_L3WARMMSK_t;
6397 #define ALT_RSTMGR_L3WARMMSK_RESET 0x00000001
6399 #define ALT_RSTMGR_L3WARMMSK_OFST 0x58
6424 #define ALT_RSTMGR_TSTSTA_WARMRSTST_LSB 0
6426 #define ALT_RSTMGR_TSTSTA_WARMRSTST_MSB 3
6428 #define ALT_RSTMGR_TSTSTA_WARMRSTST_WIDTH 4
6430 #define ALT_RSTMGR_TSTSTA_WARMRSTST_SET_MSK 0x0000000f
6432 #define ALT_RSTMGR_TSTSTA_WARMRSTST_CLR_MSK 0xfffffff0
6434 #define ALT_RSTMGR_TSTSTA_WARMRSTST_RESET 0x0
6436 #define ALT_RSTMGR_TSTSTA_WARMRSTST_GET(value) (((value) & 0x0000000f) >> 0)
6438 #define ALT_RSTMGR_TSTSTA_WARMRSTST_SET(value) (((value) << 0) & 0x0000000f)
6449 #define ALT_RSTMGR_TSTSTA_DBGRSTST_LSB 4
6451 #define ALT_RSTMGR_TSTSTA_DBGRSTST_MSB 6
6453 #define ALT_RSTMGR_TSTSTA_DBGRSTST_WIDTH 3
6455 #define ALT_RSTMGR_TSTSTA_DBGRSTST_SET_MSK 0x00000070
6457 #define ALT_RSTMGR_TSTSTA_DBGRSTST_CLR_MSK 0xffffff8f
6459 #define ALT_RSTMGR_TSTSTA_DBGRSTST_RESET 0x0
6461 #define ALT_RSTMGR_TSTSTA_DBGRSTST_GET(value) (((value) & 0x00000070) >> 4)
6463 #define ALT_RSTMGR_TSTSTA_DBGRSTST_SET(value) (((value) << 4) & 0x00000070)
6465 #ifndef __ASSEMBLY__
6476 struct ALT_RSTMGR_TSTSTA_s
6478 const uint32_t warmrstst : 4;
6479 const uint32_t dbgrstst : 3;
6484 typedef volatile struct ALT_RSTMGR_TSTSTA_s ALT_RSTMGR_TSTSTA_t;
6488 #define ALT_RSTMGR_TSTSTA_RESET 0x00000000
6490 #define ALT_RSTMGR_TSTSTA_OFST 0x5c
6513 #define ALT_RSTMGR_TSTSCRATCH_FLD0_LSB 0
6515 #define ALT_RSTMGR_TSTSCRATCH_FLD0_MSB 31
6517 #define ALT_RSTMGR_TSTSCRATCH_FLD0_WIDTH 32
6519 #define ALT_RSTMGR_TSTSCRATCH_FLD0_SET_MSK 0xffffffff
6521 #define ALT_RSTMGR_TSTSCRATCH_FLD0_CLR_MSK 0x00000000
6523 #define ALT_RSTMGR_TSTSCRATCH_FLD0_RESET 0x0
6525 #define ALT_RSTMGR_TSTSCRATCH_FLD0_GET(value) (((value) & 0xffffffff) >> 0)
6527 #define ALT_RSTMGR_TSTSCRATCH_FLD0_SET(value) (((value) << 0) & 0xffffffff)
6529 #ifndef __ASSEMBLY__
6540 struct ALT_RSTMGR_TSTSCRATCH_s
6546 typedef volatile struct ALT_RSTMGR_TSTSCRATCH_s ALT_RSTMGR_TSTSCRATCH_t;
6550 #define ALT_RSTMGR_TSTSCRATCH_RESET 0x00000000
6552 #define ALT_RSTMGR_TSTSCRATCH_OFST 0x60
6580 #define ALT_RSTMGR_HDSKTMO_VAL_LSB 0
6582 #define ALT_RSTMGR_HDSKTMO_VAL_MSB 24
6584 #define ALT_RSTMGR_HDSKTMO_VAL_WIDTH 25
6586 #define ALT_RSTMGR_HDSKTMO_VAL_SET_MSK 0x01ffffff
6588 #define ALT_RSTMGR_HDSKTMO_VAL_CLR_MSK 0xfe000000
6590 #define ALT_RSTMGR_HDSKTMO_VAL_RESET 0x2800
6592 #define ALT_RSTMGR_HDSKTMO_VAL_GET(value) (((value) & 0x01ffffff) >> 0)
6594 #define ALT_RSTMGR_HDSKTMO_VAL_SET(value) (((value) << 0) & 0x01ffffff)
6596 #ifndef __ASSEMBLY__
6607 struct ALT_RSTMGR_HDSKTMO_s
6614 typedef volatile struct ALT_RSTMGR_HDSKTMO_s ALT_RSTMGR_HDSKTMO_t;
6618 #define ALT_RSTMGR_HDSKTMO_RESET 0x00002800
6620 #define ALT_RSTMGR_HDSKTMO_OFST 0x64
6644 #define ALT_RSTMGR_HMCINTR_INTR_LSB 0
6646 #define ALT_RSTMGR_HMCINTR_INTR_MSB 0
6648 #define ALT_RSTMGR_HMCINTR_INTR_WIDTH 1
6650 #define ALT_RSTMGR_HMCINTR_INTR_SET_MSK 0x00000001
6652 #define ALT_RSTMGR_HMCINTR_INTR_CLR_MSK 0xfffffffe
6654 #define ALT_RSTMGR_HMCINTR_INTR_RESET 0x0
6656 #define ALT_RSTMGR_HMCINTR_INTR_GET(value) (((value) & 0x00000001) >> 0)
6658 #define ALT_RSTMGR_HMCINTR_INTR_SET(value) (((value) << 0) & 0x00000001)
6660 #ifndef __ASSEMBLY__
6671 struct ALT_RSTMGR_HMCINTR_s
6678 typedef volatile struct ALT_RSTMGR_HMCINTR_s ALT_RSTMGR_HMCINTR_t;
6682 #define ALT_RSTMGR_HMCINTR_RESET 0x00000000
6684 #define ALT_RSTMGR_HMCINTR_OFST 0x68
6708 #define ALT_RSTMGR_HMCINTREN_EN_LSB 0
6710 #define ALT_RSTMGR_HMCINTREN_EN_MSB 0
6712 #define ALT_RSTMGR_HMCINTREN_EN_WIDTH 1
6714 #define ALT_RSTMGR_HMCINTREN_EN_SET_MSK 0x00000001
6716 #define ALT_RSTMGR_HMCINTREN_EN_CLR_MSK 0xfffffffe
6718 #define ALT_RSTMGR_HMCINTREN_EN_RESET 0x0
6720 #define ALT_RSTMGR_HMCINTREN_EN_GET(value) (((value) & 0x00000001) >> 0)
6722 #define ALT_RSTMGR_HMCINTREN_EN_SET(value) (((value) << 0) & 0x00000001)
6724 #ifndef __ASSEMBLY__
6735 struct ALT_RSTMGR_HMCINTREN_s
6742 typedef volatile struct ALT_RSTMGR_HMCINTREN_s ALT_RSTMGR_HMCINTREN_t;
6746 #define ALT_RSTMGR_HMCINTREN_RESET 0x00000000
6748 #define ALT_RSTMGR_HMCINTREN_OFST 0x6c
6772 #define ALT_RSTMGR_HMCINTRENS_EN_LSB 0
6774 #define ALT_RSTMGR_HMCINTRENS_EN_MSB 0
6776 #define ALT_RSTMGR_HMCINTRENS_EN_WIDTH 1
6778 #define ALT_RSTMGR_HMCINTRENS_EN_SET_MSK 0x00000001
6780 #define ALT_RSTMGR_HMCINTRENS_EN_CLR_MSK 0xfffffffe
6782 #define ALT_RSTMGR_HMCINTRENS_EN_RESET 0x0
6784 #define ALT_RSTMGR_HMCINTRENS_EN_GET(value) (((value) & 0x00000001) >> 0)
6786 #define ALT_RSTMGR_HMCINTRENS_EN_SET(value) (((value) << 0) & 0x00000001)
6788 #ifndef __ASSEMBLY__
6799 struct ALT_RSTMGR_HMCINTRENS_s
6806 typedef volatile struct ALT_RSTMGR_HMCINTRENS_s ALT_RSTMGR_HMCINTRENS_t;
6810 #define ALT_RSTMGR_HMCINTRENS_RESET 0x00000000
6812 #define ALT_RSTMGR_HMCINTRENS_OFST 0x70
6836 #define ALT_RSTMGR_HMCINTRENR_EN_LSB 0
6838 #define ALT_RSTMGR_HMCINTRENR_EN_MSB 0
6840 #define ALT_RSTMGR_HMCINTRENR_EN_WIDTH 1
6842 #define ALT_RSTMGR_HMCINTRENR_EN_SET_MSK 0x00000001
6844 #define ALT_RSTMGR_HMCINTRENR_EN_CLR_MSK 0xfffffffe
6846 #define ALT_RSTMGR_HMCINTRENR_EN_RESET 0x0
6848 #define ALT_RSTMGR_HMCINTRENR_EN_GET(value) (((value) & 0x00000001) >> 0)
6850 #define ALT_RSTMGR_HMCINTRENR_EN_SET(value) (((value) << 0) & 0x00000001)
6852 #ifndef __ASSEMBLY__
6863 struct ALT_RSTMGR_HMCINTRENR_s
6870 typedef volatile struct ALT_RSTMGR_HMCINTRENR_s ALT_RSTMGR_HMCINTRENR_t;
6874 #define ALT_RSTMGR_HMCINTRENR_RESET 0x00000000
6876 #define ALT_RSTMGR_HMCINTRENR_OFST 0x74
6900 #define ALT_RSTMGR_HMCGPOUT_OUT_LSB 0
6902 #define ALT_RSTMGR_HMCGPOUT_OUT_MSB 7
6904 #define ALT_RSTMGR_HMCGPOUT_OUT_WIDTH 8
6906 #define ALT_RSTMGR_HMCGPOUT_OUT_SET_MSK 0x000000ff
6908 #define ALT_RSTMGR_HMCGPOUT_OUT_CLR_MSK 0xffffff00
6910 #define ALT_RSTMGR_HMCGPOUT_OUT_RESET 0x0
6912 #define ALT_RSTMGR_HMCGPOUT_OUT_GET(value) (((value) & 0x000000ff) >> 0)
6914 #define ALT_RSTMGR_HMCGPOUT_OUT_SET(value) (((value) << 0) & 0x000000ff)
6916 #ifndef __ASSEMBLY__
6927 struct ALT_RSTMGR_HMCGPOUT_s
6934 typedef volatile struct ALT_RSTMGR_HMCGPOUT_s ALT_RSTMGR_HMCGPOUT_t;
6938 #define ALT_RSTMGR_HMCGPOUT_RESET 0x00000000
6940 #define ALT_RSTMGR_HMCGPOUT_OFST 0x78
6964 #define ALT_RSTMGR_HMCGPIN_IN_LSB 0
6966 #define ALT_RSTMGR_HMCGPIN_IN_MSB 7
6968 #define ALT_RSTMGR_HMCGPIN_IN_WIDTH 8
6970 #define ALT_RSTMGR_HMCGPIN_IN_SET_MSK 0x000000ff
6972 #define ALT_RSTMGR_HMCGPIN_IN_CLR_MSK 0xffffff00
6974 #define ALT_RSTMGR_HMCGPIN_IN_RESET 0x0
6976 #define ALT_RSTMGR_HMCGPIN_IN_GET(value) (((value) & 0x000000ff) >> 0)
6978 #define ALT_RSTMGR_HMCGPIN_IN_SET(value) (((value) << 0) & 0x000000ff)
6980 #ifndef __ASSEMBLY__
6991 struct ALT_RSTMGR_HMCGPIN_s
6993 const uint32_t in : 8;
6998 typedef volatile struct ALT_RSTMGR_HMCGPIN_s ALT_RSTMGR_HMCGPIN_t;
7002 #define ALT_RSTMGR_HMCGPIN_RESET 0x00000000
7004 #define ALT_RSTMGR_HMCGPIN_OFST 0x7c
7006 #ifndef __ASSEMBLY__
7019 ALT_RSTMGR_STAT_t stat;
7020 ALT_RSTMGR_RAMSTAT_t ramstat;
7021 ALT_RSTMGR_MISCSTAT_t miscstat;
7022 ALT_RSTMGR_CTL_t ctrl;
7023 ALT_RSTMGR_HDSKEN_t hdsken;
7024 ALT_RSTMGR_HDSKREQ_t hdskreq;
7025 ALT_RSTMGR_HDSKACK_t hdskack;
7026 ALT_RSTMGR_COUNTS_t counts;
7027 ALT_RSTMGR_MPUMODRST_t mpumodrst;
7028 ALT_RSTMGR_PER0MODRST_t per0modrst;
7029 ALT_RSTMGR_PER1MODRST_t per1modrst;
7030 ALT_RSTMGR_BRGMODRST_t brgmodrst;
7031 ALT_RSTMGR_SYSMODRST_t sysmodrst;
7032 ALT_RSTMGR_COLDMODRST_t coldmodrst;
7033 ALT_RSTMGR_NRSTMODRST_t nrstmodrst;
7034 ALT_RSTMGR_DBGMODRST_t dbgmodrst;
7035 ALT_RSTMGR_MPUWARMMSK_t mpuwarmmask;
7036 ALT_RSTMGR_PER0WARMMSK_t per0warmmask;
7037 ALT_RSTMGR_PER1WARMMSK_t per1warmmask;
7038 ALT_RSTMGR_BRGWARMMSK_t brgwarmmask;
7039 ALT_RSTMGR_SYSWARMMSK_t syswarmmask;
7040 ALT_RSTMGR_NRSTWARMMSK_t nrstwarmmask;
7041 ALT_RSTMGR_L3WARMMSK_t l3warmmask;
7042 ALT_RSTMGR_TSTSTA_t tststa;
7043 ALT_RSTMGR_TSTSCRATCH_t tstscratch;
7044 ALT_RSTMGR_HDSKTMO_t hdsktimeout;
7045 ALT_RSTMGR_HMCINTR_t hmcintr;
7046 ALT_RSTMGR_HMCINTREN_t hmcintren;
7047 ALT_RSTMGR_HMCINTRENS_t hmcintrens;
7048 ALT_RSTMGR_HMCINTRENR_t hmcintrenr;
7049 ALT_RSTMGR_HMCGPOUT_t hmcgpout;
7050 ALT_RSTMGR_HMCGPIN_t hmcgpin;
7051 volatile uint32_t _pad_0x80_0x100[32];
7055 typedef volatile struct ALT_RSTMGR_s ALT_RSTMGR_t;
7057 struct ALT_RSTMGR_raw_s
7059 volatile uint32_t stat;
7060 volatile uint32_t ramstat;
7061 volatile uint32_t miscstat;
7062 volatile uint32_t ctrl;
7063 volatile uint32_t hdsken;
7064 volatile uint32_t hdskreq;
7065 volatile uint32_t hdskack;
7066 volatile uint32_t counts;
7067 volatile uint32_t mpumodrst;
7068 volatile uint32_t per0modrst;
7069 volatile uint32_t per1modrst;
7070 volatile uint32_t brgmodrst;
7071 volatile uint32_t sysmodrst;
7072 volatile uint32_t coldmodrst;
7073 volatile uint32_t nrstmodrst;
7074 volatile uint32_t dbgmodrst;
7075 volatile uint32_t mpuwarmmask;
7076 volatile uint32_t per0warmmask;
7077 volatile uint32_t per1warmmask;
7078 volatile uint32_t brgwarmmask;
7079 volatile uint32_t syswarmmask;
7080 volatile uint32_t nrstwarmmask;
7081 volatile uint32_t l3warmmask;
7082 volatile uint32_t tststa;
7083 volatile uint32_t tstscratch;
7084 volatile uint32_t hdsktimeout;
7085 volatile uint32_t hmcintr;
7086 volatile uint32_t hmcintren;
7087 volatile uint32_t hmcintrens;
7088 volatile uint32_t hmcintrenr;
7089 volatile uint32_t hmcgpout;
7090 volatile uint32_t hmcgpin;
7091 uint32_t _pad_0x80_0x100[32];
7095 typedef volatile struct ALT_RSTMGR_raw_s ALT_RSTMGR_raw_t;